From c8e2d9d304ab082a6d14d0770a1fb787bdf4d2f3 Mon Sep 17 00:00:00 2001 From: ReillyMcK Date: Thu, 5 Dec 2024 07:09:33 -0700 Subject: [PATCH] I/O wrappers for koios designs --- .../koios/attention_layer/attention_layer.v | 4091 + .../koios/attention_layer/attention_random.sv | 53 + designs/koios/attention_layer/design.yaml | 1 + designs/koios/bnn/bnn.v | 32595 +++ designs/koios/bnn/bnn_random.sv | 92 + designs/koios/bnn/design.yaml | 1 + .../bwave_large_random.sv | 228 + .../bwave_like.fixed.large.v | 8091 + .../koios/bwave_like.fixed.large/design.yaml | 1 + .../bwave_like.fixed.small.v | 4903 + .../bwave_small_random.sv | 200 + .../koios/bwave_like.fixed.small/design.yaml | 1 + .../bwave_large_random.sv | 315 + .../bwave_like.float.large.v | 25206 ++ .../koios/bwave_like.float.large/design.yaml | 1 + .../bwave_like.float.small.v | 12340 + .../bwave_small_random.sv | 257 + .../koios/bwave_like.float.small/design.yaml | 1 + .../koios/clstm_like.large/clstm_like.large.v | 35251 +++ .../koios/clstm_like.large/clstm_random.sv | 135 + designs/koios/clstm_like.large/design.yaml | 1 + .../clstm_like.medium/clstm_like.medium.v | 26284 ++ .../koios/clstm_like.medium/clstm_random.sv | 119 + designs/koios/clstm_like.medium/design.yaml | 1 + .../koios/clstm_like.small/clstm_like.small.v | 17107 ++ .../koios/clstm_like.small/clstm_random.sv | 102 + designs/koios/clstm_like.small/design.yaml | 1 + designs/koios/conv_layer/conv_layer.v | 2869 + designs/koios/conv_layer/conv_layer_random.sv | 89 + designs/koios/conv_layer/design.yaml | 1 + designs/koios/conv_layer_hls/conv_layer_hls.v | 7807 + .../koios/conv_layer_hls/conv_layer_random.sv | 447 + designs/koios/conv_layer_hls/design.yaml | 1 + designs/koios/dla_like.large/design.yaml | 1 + designs/koios/dla_like.large/dla_like.large.v | 69918 +++++ designs/koios/dla_like.large/dla_random.sv | 276 + designs/koios/dla_like.medium/design.yaml | 1 + .../koios/dla_like.medium/dla_like.medium.v | 30630 ++ designs/koios/dla_like.medium/dla_random.sv | 156 + designs/koios/dla_like.small/design.yaml | 1 + designs/koios/dla_like.small/dla_like.small.v | 14570 + designs/koios/dla_like.small/dla_random.sv | 96 + designs/koios/dnnweaver/cl_wrapper_random.sv | 1044 + designs/koios/dnnweaver/design.yaml | 1 + designs/koios/dnnweaver/dnnweaver.v | 14842 + designs/koios/eltwise_layer/design.yaml | 1 + designs/koios/eltwise_layer/eltwise_layer.v | 3057 + designs/koios/gemm_layer/design.yaml | 1 + designs/koios/gemm_layer/gemm_layer.v | 7976 + designs/koios/gemm_layer/gemm_random.sv | 191 + designs/koios/lenet/design.yaml | 1 + designs/koios/lenet/lenet.v | 227190 +++++++++++++++ designs/koios/lstm/design.yaml | 1 + designs/koios/lstm/lstm.v | 1652 + designs/koios/lstm/lstm_random.sv | 67 + designs/koios/reduction_layer/design.yaml | 1 + .../koios/reduction_layer/reduction_layer.v | 1368 + designs/koios/robot_rl/design.yaml | 1 + designs/koios/robot_rl/robot_rl.v | 5122 + designs/koios/softmax/design.yaml | 1 + designs/koios/softmax/softmax.v | 3424 + designs/koios/softmax/softmax_random.sv | 82 + designs/koios/spmv/design.yaml | 1 + designs/koios/spmv/spmv.v | 3791 + designs/koios/tdarknet_like.large/design.yaml | 1 + .../tdarknet_like.large/tdarknet_like.large.v | 200559 +++++++++++++ designs/koios/tdarknet_like.small/design.yaml | 1 + .../tdarknet_like.small/tdarknet_like.small.v | 114900 ++++++++ designs/koios/test/design.yaml | 1 + designs/koios/test/test.v | 608 + designs/koios/tpu_like.large.os/design.yaml | 1 + .../tpu_like.large.os/tpu_like.large.os.v | 15691 + designs/koios/tpu_like.large.os/tpu_random.sv | 143 + designs/koios/tpu_like.large.ws/design.yaml | 1 + .../tpu_like.large.ws/tpu_like.large.ws.v | 23768 ++ designs/koios/tpu_like.large.ws/tpu_random.sv | 171 + designs/koios/tpu_like.small.os/design.yaml | 1 + .../tpu_like.small.os/tpu_like.small.os.v | 5961 + designs/koios/tpu_like.small.os/tpu_random.sv | 130 + designs/koios/tpu_like.small.ws/design.yaml | 1 + .../tpu_like.small.ws/tpu_like.small.ws.v | 10537 + designs/koios/tpu_like.small.ws/tpu_random.sv | 155 + designs/ooc/a25_decode/a25_decode_random.sv | 2 +- designs/ooc/a25_execute/a25_execute_random.sv | 2 +- designs/ooc/a25_fetch/a25_fetch_random.sv | 2 +- designs/ooc/a25_mem/a25_mem_random.sv | 2 +- .../ooc/a25_wishbone/a25_wishbone_random.sv | 2 +- designs/ooc/aes128/aes128_random.sv | 2 +- designs/ooc/ahbctrl/ahbctrl_random.sv | 2 +- designs/ooc/ahbjtag/ahbjtag_random.sv | 2 +- designs/ooc/ahbuart/ahbuart_random.sv | 2 +- designs/ooc/amber/amber_random.sv | 2 +- designs/ooc/apbctrl/apbctrl_random.sv | 2 +- designs/ooc/bubblesort/bubblesort_random.sv | 2 +- designs/ooc/des3_area/des3_area_random.sv | 2 +- designs/ooc/des3_perf/des3_perf_random.sv | 2 +- designs/ooc/dsu3/dsu3_random.sv | 2 +- designs/ooc/grethm/grethm_random.sv | 2 +- designs/ooc/irqmp/irqmp_random.sv | 2 +- designs/ooc/leon3s/leon3s_random.sv | 2 +- designs/ooc/m32632/m32632_random.sv | 2 +- designs/ooc/mctrl/mctrl_random.sv | 2 +- .../ooc/md5_pipelined/md5_pipelined_random.sv | 2 +- designs/ooc/mpeg2fpga/mpeg2fpga_random.sv | 2 +- .../sha3_high_throughput_random.sv | 2 +- .../sha3_low_throughput_random.sv | 2 +- designs/ooc/spimctrl/spimctrl_random.sv | 2 +- designs/ooc/sudoku/sudoku_random.sv | 2 +- designs/{ooc => }/random_number_generator.sv | 0 designs/vtr_benchmarks/bgm/bgm_random.sv | 2 +- .../paj_boundtop_hierarchy_no_mem_random.sv | 2 +- designs/vtr_benchmarks/mcml/mcml_random.sv | 2 +- .../mkDelayWorker32B_random.sv | 2 +- .../mkPktMerge/mkPktMerge_random.sv | 2 +- .../mkSMAdapter4B/mkSMAdapter4B_random.sv | 2 +- .../or1200/or1200_flat_random.sv | 2 +- .../paj_raygentop_hierarchy_no_mem_random.sv | 2 +- .../sv_chip0_hierarchy_no_mem_random.sv | 2 +- .../sv_chip2_hierarchy_no_mem_random.sv | 2 +- tests/weekly/vivado_koios.yaml | 37 + 120 files changed, 936759 insertions(+), 36 deletions(-) create mode 100644 designs/koios/attention_layer/attention_layer.v create mode 100644 designs/koios/attention_layer/attention_random.sv create mode 100644 designs/koios/attention_layer/design.yaml create mode 100644 designs/koios/bnn/bnn.v create mode 100644 designs/koios/bnn/bnn_random.sv create mode 100644 designs/koios/bnn/design.yaml create mode 100644 designs/koios/bwave_like.fixed.large/bwave_large_random.sv create mode 100644 designs/koios/bwave_like.fixed.large/bwave_like.fixed.large.v create mode 100644 designs/koios/bwave_like.fixed.large/design.yaml create mode 100644 designs/koios/bwave_like.fixed.small/bwave_like.fixed.small.v create mode 100644 designs/koios/bwave_like.fixed.small/bwave_small_random.sv create mode 100644 designs/koios/bwave_like.fixed.small/design.yaml create mode 100644 designs/koios/bwave_like.float.large/bwave_large_random.sv create mode 100644 designs/koios/bwave_like.float.large/bwave_like.float.large.v create mode 100644 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mode 100644 designs/koios/conv_layer/design.yaml create mode 100644 designs/koios/conv_layer_hls/conv_layer_hls.v create mode 100644 designs/koios/conv_layer_hls/conv_layer_random.sv create mode 100644 designs/koios/conv_layer_hls/design.yaml create mode 100644 designs/koios/dla_like.large/design.yaml create mode 100644 designs/koios/dla_like.large/dla_like.large.v create mode 100644 designs/koios/dla_like.large/dla_random.sv create mode 100644 designs/koios/dla_like.medium/design.yaml create mode 100644 designs/koios/dla_like.medium/dla_like.medium.v create mode 100644 designs/koios/dla_like.medium/dla_random.sv create mode 100644 designs/koios/dla_like.small/design.yaml create mode 100644 designs/koios/dla_like.small/dla_like.small.v create mode 100644 designs/koios/dla_like.small/dla_random.sv create mode 100644 designs/koios/dnnweaver/cl_wrapper_random.sv create mode 100644 designs/koios/dnnweaver/design.yaml create mode 100644 designs/koios/dnnweaver/dnnweaver.v create mode 100644 designs/koios/eltwise_layer/design.yaml create mode 100644 designs/koios/eltwise_layer/eltwise_layer.v create mode 100644 designs/koios/gemm_layer/design.yaml create mode 100644 designs/koios/gemm_layer/gemm_layer.v create mode 100644 designs/koios/gemm_layer/gemm_random.sv create mode 100644 designs/koios/lenet/design.yaml create mode 100644 designs/koios/lenet/lenet.v create mode 100644 designs/koios/lstm/design.yaml create mode 100644 designs/koios/lstm/lstm.v create mode 100644 designs/koios/lstm/lstm_random.sv create mode 100644 designs/koios/reduction_layer/design.yaml create mode 100644 designs/koios/reduction_layer/reduction_layer.v create mode 100644 designs/koios/robot_rl/design.yaml create mode 100644 designs/koios/robot_rl/robot_rl.v create mode 100644 designs/koios/softmax/design.yaml create mode 100644 designs/koios/softmax/softmax.v create mode 100644 designs/koios/softmax/softmax_random.sv create mode 100644 designs/koios/spmv/design.yaml create mode 100644 designs/koios/spmv/spmv.v create mode 100644 designs/koios/tdarknet_like.large/design.yaml create mode 100644 designs/koios/tdarknet_like.large/tdarknet_like.large.v create mode 100644 designs/koios/tdarknet_like.small/design.yaml create mode 100644 designs/koios/tdarknet_like.small/tdarknet_like.small.v create mode 100644 designs/koios/test/design.yaml create mode 100644 designs/koios/test/test.v create mode 100644 designs/koios/tpu_like.large.os/design.yaml create mode 100644 designs/koios/tpu_like.large.os/tpu_like.large.os.v create mode 100644 designs/koios/tpu_like.large.os/tpu_random.sv create mode 100644 designs/koios/tpu_like.large.ws/design.yaml create mode 100644 designs/koios/tpu_like.large.ws/tpu_like.large.ws.v create mode 100644 designs/koios/tpu_like.large.ws/tpu_random.sv create mode 100644 designs/koios/tpu_like.small.os/design.yaml create mode 100644 designs/koios/tpu_like.small.os/tpu_like.small.os.v create mode 100644 designs/koios/tpu_like.small.os/tpu_random.sv create mode 100644 designs/koios/tpu_like.small.ws/design.yaml create mode 100644 designs/koios/tpu_like.small.ws/tpu_like.small.ws.v create mode 100644 designs/koios/tpu_like.small.ws/tpu_random.sv rename designs/{ooc => }/random_number_generator.sv (100%) create mode 100644 tests/weekly/vivado_koios.yaml diff --git a/designs/koios/attention_layer/attention_layer.v b/designs/koios/attention_layer/attention_layer.v new file mode 100644 index 000000000..f3fab46db --- /dev/null +++ b/designs/koios/attention_layer/attention_layer.v @@ -0,0 +1,4091 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Aishwarya Rajen +////////////////////////////////////////////////////////////////////////////// + +//`define SIMULATION_MEMORY +//`define SIMULATION_addfp + +`define VECTOR_DEPTH 64 //Q,K,V vector size +`define DATA_WIDTH 16 +`define VECTOR_BITS 1024 // 16 bit each (16x64) +`define NUM_WORDS 32 //num of words in the sentence +`define BUF_AWIDTH 4 //16 entries in each buffer ram +`define BUF_LOC_SIZE 4 //4 words in each addr location +`define OUT_RAM_DEPTH 512 //512 entries in output bram +`define LOG_OUT_RAM_DEPTH 9 //512 entries in output bram + +///////////////////////////////////////////////////////////////////////////// +//Self-Attention Layer +///////////////////////////////////////////////////////////////////////////// +//Fig 2 (left) of the "Attention is all you need" paper. +//Design of the self-attention layer module which is useful +//in the Transformer deep learning architecture. +//Fixed Point 16(4.12) format is used. +//This design takes in the Query Vector Q,Key Vector K and +//Value vector V dervied from the word embeddings as input. +//The Q,K,V matrices are stored and accessed through Dual Port RAMs +//This is a pipelined design comprising of matrix vector multiplcation, +//scaling, Softmax layer and a final matrix vector multiplication stage. +//Double buffering has been used at the input and output of the softmax +//inorder to hide the latency of the softmax design. +//The final outputs also get stored in a DPRAM which is interfaced through I/O. +////////////////////////////////////////////////////////////////////////////// + +`ifdef BFLOAT16 +`define EXPONENT 8 +`define MANTISSA 7 +`else // for ieee half precision fp16 +`define EXPONENT 5 +`define MANTISSA 10 +`endif + +`define SIGN 1 +`define DWIDTH (`SIGN+`EXPONENT+`MANTISSA) + +module attention_layer( +input clk, +input rst, +input start, +input [4:0] q_rd_addr, //start address of q +input [4:0] k_rd_addr, //start address of k +input [4:0] v_rd_addr, //start address of v +input [2:0] wren_qkv_ext, //To write data into Q,K,V BRAMs externally +input [4:0] address_ext, //External write address +input [`VECTOR_BITS-1:0] data_ext, //Data to be written +input [`LOG_OUT_RAM_DEPTH-1:0] out_rd_addr, //To read stored outputs from outside +output [`DATA_WIDTH-1:0] out_part1, //16 bit output from out bram +output [`DATA_WIDTH-1:0] out_part2 //16 bit output from out bram +); + + +reg q_en,k_en,v_en; +reg [4:0] q_addr,k_addr; +reg [4:0] v_addr; +wire [`VECTOR_BITS-1:0] q,k; +wire [(`NUM_WORDS*`DATA_WIDTH)-1:0] v_part1; +wire [(`NUM_WORDS*`DATA_WIDTH)-1:0] v_part2; + +//Dummy input/ouputs connected to DPRAM to ensure VTR doesn't optimize the BRAM out. +reg [`VECTOR_BITS-1:0] dummyin_q,dummyin_k; +reg [(`NUM_WORDS*`DATA_WIDTH)-1:0] dummyin_v; +wire [`VECTOR_BITS-1:0] dummyout_q,dummyout_k; +wire [(`NUM_WORDS*`DATA_WIDTH)-1:0] dummyout_v1; +wire [(`NUM_WORDS*`DATA_WIDTH)-1:0] dummyout_v2; + +reg [4:0] count; +wire [`VECTOR_BITS-1:0] mul_out; +wire [`DATA_WIDTH-1:0] qiki, scaled_qiki; +reg flag; +wire [`NUM_WORDS*`DATA_WIDTH-1:0] mul_out2_part1; +wire [`NUM_WORDS*`DATA_WIDTH-1:0] mul_out2_part2; +wire [`DATA_WIDTH-1:0] softmulv_part1; +wire [`DATA_WIDTH-1:0] softmulv_part2; + +//Input/output connections of the buffers +reg [`BUF_AWIDTH-1:0] wr_addr_12; +reg wr_addr_34; +wire [`BUF_AWIDTH-1:0] rd_addr_12; +reg rd_addr_34; +reg [`BUF_LOC_SIZE*`DATA_WIDTH-1:0] wr_data_12; +reg [(8*`BUF_LOC_SIZE*`DATA_WIDTH)-1:0]wr_data_34; +reg [`BUF_LOC_SIZE-1:0] word_we0_12,word_we1_12; +reg [`NUM_WORDS-1:0] word_we0_34,word_we1_34; +wire [`BUF_LOC_SIZE*`DATA_WIDTH-1:0] data_to_softmax; +wire [`NUM_WORDS*`DATA_WIDTH-1:0] data_to_MVM; +reg [`BUF_LOC_SIZE*`DATA_WIDTH-1:0] dummyin_buf12; +reg [`NUM_WORDS*`DATA_WIDTH-1:0] dummyin_buf34; +wire [`BUF_LOC_SIZE*`DATA_WIDTH-1:0] dummyout_buf12; +wire [`NUM_WORDS*`DATA_WIDTH-1:0] dummyout_buf34; +reg [1:0] word_count; + +//softmax +wire [`DATA_WIDTH-1:0] soft_out0,soft_out1,soft_out2,soft_out3; +reg soft_init,soft_start; +wire soft_done; +wire [`BUF_AWIDTH-1:0] soft_strt_addr,soft_end_addr,soft_rd_addr,soft_sub0_addr,soft_sub1_addr; +reg choose_buf; +reg buff_done; + +reg [4:0] soft_word_count; +wire [8*`BUF_LOC_SIZE*`DATA_WIDTH-1:0] comb_softout; +reg vector_complete; +//reg strt_softmulv; +reg [5:0] v_count,v_count_ff; + +reg [8:0] out_wr_addr; +reg [8:0] addr_a,addr_b; +reg wren_a,wren_b; +reg [`DATA_WIDTH-1:0] dummy_b; +wire [`DATA_WIDTH-1:0] dummy_a1; +wire [`DATA_WIDTH-1:0] dummy_a2; +reg strt_out_write; +reg soft_out_strt, soft_out_end; +reg first_time; + +//BRAMs that hold Q,K,V matrices +dpram Q(.clk(clk),.address_a(q_addr),.address_b(address_ext),.wren_a(q_en),.wren_b(wren_qkv_ext[0]),.data_a(dummyin_q),.data_b(data_ext),.out_a(q),.out_b(dummyout_q)); +dpram K(.clk(clk),.address_a(k_addr),.address_b(address_ext),.wren_a(k_en),.wren_b(wren_qkv_ext[0]),.data_a(dummyin_k),.data_b(data_ext),.out_a(k),.out_b(dummyout_k)); +dpram_t V_part1(.clk(clk),.address_a(v_addr),.address_b(address_ext),.wren_a(v_en),.wren_b(wren_qkv_ext[0]),.data_a(dummyin_v),.data_b(data_ext[511:0]),.out_a(v_part1),.out_b(dummyout_v1)); +dpram_t V_part2(.clk(clk),.address_a(v_addr),.address_b(address_ext),.wren_a(v_en),.wren_b(wren_qkv_ext[0]),.data_a(dummyin_v),.data_b(data_ext[1023:512]),.out_a(v_part2),.out_b(dummyout_v2)); + +//Multiplying Q and K vector +vecmat_mul qk_mul (.clk(clk),.reset(rst),.vector(q),.matrix(k),.tmp(mul_out)); +vecmat_add qk_acc (.clk(clk),.reset(rst),.mulout(mul_out),.data_out(qiki)); + +//Scaling (dividing by 8) +divideby8 scale(.data(qiki),.out(scaled_qiki)); + +//Buffers 1 and 2 at the input to softmax block (2 buffers are present in a single bram) +//Each location stores 4 words together to feed to softmax +wordwise_bram in_buffer12 +( .addr0(wr_addr_12), + .d0(wr_data_12), + .we0(word_we0_12), + .q0(dummyout_buf12), + .addr1(rd_addr_12), //from softmax + .d1(dummyin_buf12), + .we1(word_we1_12), + .q1(data_to_softmax), //to softmax + .clk(clk) +); + +//Buffers 3 and 4 at the output of softmax block +//Each location stores 32 words to make it easy to feed to MVM +wordwise_bram_2 out_buffer34 +( .addr0(wr_addr_34), + .d0(wr_data_34), + .we0(word_we0_34), + .q0(dummyout_buf34), + .addr1(rd_addr_34), + .d1(dummyin_buf34), + .we1(word_we1_34), + .q1(data_to_MVM), //to MVM + .clk(clk) +); + +//Softmax layer has a parallelism of 4 +softmax soft( + .inp(data_to_softmax), + .sub0_inp(data_to_softmax), + .sub1_inp(data_to_softmax), + .start_addr(soft_strt_addr), + .end_addr(soft_end_addr), + .addr(soft_rd_addr), + .sub0_inp_addr(soft_sub0_addr), + .sub1_inp_addr(soft_sub1_addr), + .outp0(soft_out0), + .outp1(soft_out1), + .outp2(soft_out2), + .outp3(soft_out3), + .init(soft_init), + .start(soft_start), + .done(soft_done), + .clk(clk), + .reset(rst) +// .addr_sel(addr_select) +); + +//Multiplying output of softmax with V matrix. +//this is done using 2 MVMs. We parallelize by processing 32 rows in each MVM +//this results in the total operation taking 30+change cycles. +//this is done to balance the pipeline. MVM1 takes 30+change cycles, SOFTMAX +//takes 30+change cycles, MVM2 now takes 30+change cycles. If we don't use +//2 MVMs for MVM2, then it'll take 60+change cycles. + +//First MVM will only process first 32 rows of the +//matrix V. +vecmat_mul_32 rv_mul_1 (.clk(clk),.reset(rst),.vector(data_to_MVM),.matrix(v_part1),.tmp(mul_out2_part1)); +vecmat_add_32 rv_acc_1 (.clk(clk),.reset(rst),.mulout(mul_out2_part1),.data_out(softmulv_part1)); + +//second set of MVM for multiplying the output of softmax (vector) with the +//V matrix. this MVM will process the next 32 rows of the matrix V. +vecmat_mul_32 rv_mul_2 (.clk(clk),.reset(rst),.vector(data_to_MVM),.matrix(v_part2),.tmp(mul_out2_part2)); +vecmat_add_32 rv_acc_2 (.clk(clk),.reset(rst),.mulout(mul_out2_part2),.data_out(softmulv_part2)); + +//output BRAM can store upto 512 elements of `DATA_WIDTH +dpram_small out_ram_part1 (.clk(clk),.address_a(out_wr_addr),.address_b(out_rd_addr),.wren_a(wren_a),.wren_b(wren_b),.data_a(softmulv_part1),.data_b(dummy_b),.out_a(dummy_a1),.out_b(out_part1)); +dpram_small out_ram_part2 (.clk(clk),.address_a(out_wr_addr),.address_b(out_rd_addr),.wren_a(wren_a),.wren_b(wren_b),.data_a(softmulv_part2),.data_b(dummy_b),.out_a(dummy_a2),.out_b(out_part2)); + +assign rd_addr_12 = soft_rd_addr|soft_sub0_addr|soft_sub1_addr ; +//assign rd_addr_12 = (addr_select)?soft_rd_addr:soft_sub0_addr|soft_sub1_addr ; + + + +assign soft_strt_addr = (~choose_buf)?4'd0:4'd7; +assign soft_end_addr = (~choose_buf)?4'd7:4'd15; + + + +always @(posedge clk) begin + + if (rst) begin + q_addr <=0; + k_addr <=0; + q_en <=0; + k_en <=0; + count <=0; + dummyin_q <= 0; + dummyin_k <=0; + dummyin_v <= 0; + word_we0_12<=1; + dummyin_buf12 <= 0; + word_we1_12 <= 0; //softmax always reads from buff 1&2 + wr_addr_12 <= 0; + word_count <= 0; + choose_buf <= 1; + first_time <=1; + soft_init <=0; + end + else begin + if (start ==1) begin + q_addr <= q_rd_addr; + k_addr <= k_rd_addr; + count <= count+1'b1; + end + else begin + //Reading data from the K,Q BRAMs to feed to MVM + //K vector increments every cycle and Q increments after multiplication with the whole set of K vectors is complete + k_addr <= k_addr+1'b1; + if(count==0) + q_addr <= q_addr+1'b1; + if(count>4) + flag <= 1; //to ensure initially there is a 4 cycle pipeline stage delay + + //Writing scaled output to the buffers + if(flag == 1) begin + if(word_count==0) + word_we0_12 <= 4'b0001; + else + word_we0_12 <= word_we0_12 <<1; //creating write enable for diff words in same addr loc. + + if(word_we0_12 == 4'b1000) + wr_addr_12 <= wr_addr_12+1'b1; //addr gets incremented every 4 words + + + word_count <= word_count+1'b1; + + if(count==4) + buff_done <= 1; //indicates one of the buffers being full + else if(soft_init|soft_start == 1) + buff_done <= 0; //shows buff data has been sent to softmax + + + + if(buff_done == 1) begin //start softmax after one buffer is full (32 words in in_buffer12) + //start softmax when buff is done for the first time + //& start softmax only after it finishes outputing previous values + if(first_time==1 || soft_out_end==1) begin + first_time <= 0; + soft_init <= 1; + choose_buf <= ~choose_buf; //to alternate between the two buffers 1 & 2 within one ram + end + end + else if(soft_init==1) begin + soft_init <= 0; + soft_start <= 1; + end + else + soft_start <=0; + + end + + count <= count+1'b1; + wr_data_12 <= scaled_qiki<<(`DATA_WIDTH*(word_count)); //word data sent to softmax + + + end + + end +end + + +always @(posedge clk) begin + + //SOFTMAX control + if(rst) begin + soft_out_strt <= 0; + soft_out_end <= 0; + end + else begin + if(soft_done==1) begin + soft_out_strt <=1; + soft_out_end <= 0; + end + else begin + if(soft_out_strt==1) begin + soft_out_end <=1; + soft_out_strt <=0; + end + else if(soft_start==1) //indicates that the next set of inputs have been given to softmax + soft_out_end <= 0; + end + end +end + +//concatenate the 4 outputs from softmax +assign comb_softout = {{448{1'b0}},soft_out3,soft_out2,soft_out1,soft_out0}; + +//Control logic for the output side of softmax +always@(posedge clk) begin + if(rst) begin + word_we0_34 <= 32'h0000000f; + wr_addr_34 <= 0; + wr_data_34 <= 0; + dummyin_buf34 <=0; + soft_word_count <=0; + rd_addr_34 <= 0; + word_we1_34 <= 0; + //strt_softmulv <= 0; + v_en <= 0; + v_addr <= 0; + v_count <= 0; + out_wr_addr <= 0; + wren_a <= 1; + wren_b <= 0; + dummy_b <=0; + end + else begin + if(start==1) + v_addr <= v_rd_addr; + + //storing output data from softmax on to buffers 3 & 4 + if(soft_done == 1) begin + if(soft_word_count==0) + word_we0_34 <= 32'h0000000f; //write all words of a loc simultaneously + else + word_we0_34 <= word_we0_34<<4; + + wr_data_34 <= comb_softout<<(`DATA_WIDTH*soft_word_count); + soft_word_count <= soft_word_count+3'd4; //every cycle we write 4 words together + end + else begin + word_we0_34 <= 0; + if(word_we0_34==32'hf0000000) begin + + wr_addr_34 <= wr_addr_34+1'b1; + vector_complete <=1; //indicates atleast one buffer has data + end + end + //MVM with V matrix control logic (1x32 * 32x64) + if(vector_complete==1) begin + v_addr <= v_addr+1'b1; + v_count <= v_count+1'b1; + end + + if(v_count==31) begin + rd_addr_34 <= ~rd_addr_34; //change addr to read data to MVM block + //mvm_complete <= 1; //pulse indicates completion on one mvm multiplication of soft vector and V + end + else + //mvm_complete <= 0; + + if(v_count==4) //output write 4 stage pipeline delay for MVM + strt_out_write <=1; + + if(strt_out_write==1) + out_wr_addr <= out_wr_addr+1'b1; + + end +end + +endmodule + + +//Scaling by arithmetic right shifting +module divideby8 +( + input [`DATA_WIDTH-1:0] data, + output reg [`DATA_WIDTH-1:0] out + ); + + reg [`DATA_WIDTH-1:0] mask; + + always@(*) begin + if (data[`DATA_WIDTH-1] == 1) + mask = 16'b1110000000000000; + else + mask = 0; + + out = mask|(data>>3); + end + +endmodule + + + +module vecmat_mul #( parameter arraysize=1024,parameter vectdepth=64) +( + input clk, + input reset, + input [arraysize-1:0] vector, //q vector + input [arraysize-1:0] matrix, //vector from K matrix + output [arraysize-1:0] tmp + ); + + signedmul mult_u0(.clk(clk),.a(vector[0*16+:16]),.b(matrix[0*16+:16]),.c(tmp[0*16+:16])); + signedmul mult_u1(.clk(clk),.a(vector[1*16+:16]),.b(matrix[1*16+:16]),.c(tmp[1*16+:16])); + signedmul mult_u2(.clk(clk),.a(vector[2*16+:16]),.b(matrix[2*16+:16]),.c(tmp[2*16+:16])); + signedmul mult_u3(.clk(clk),.a(vector[3*16+:16]),.b(matrix[3*16+:16]),.c(tmp[3*16+:16])); + signedmul mult_u4(.clk(clk),.a(vector[4*16+:16]),.b(matrix[4*16+:16]),.c(tmp[4*16+:16])); + signedmul mult_u5(.clk(clk),.a(vector[5*16+:16]),.b(matrix[5*16+:16]),.c(tmp[5*16+:16])); + signedmul mult_u6(.clk(clk),.a(vector[6*16+:16]),.b(matrix[6*16+:16]),.c(tmp[6*16+:16])); + signedmul mult_u7(.clk(clk),.a(vector[7*16+:16]),.b(matrix[7*16+:16]),.c(tmp[7*16+:16])); + signedmul mult_u8(.clk(clk),.a(vector[8*16+:16]),.b(matrix[8*16+:16]),.c(tmp[8*16+:16])); + signedmul mult_u9(.clk(clk),.a(vector[9*16+:16]),.b(matrix[9*16+:16]),.c(tmp[9*16+:16])); + signedmul mult_u10(.clk(clk),.a(vector[10*16+:16]),.b(matrix[10*16+:16]),.c(tmp[10*16+:16])); + signedmul mult_u11(.clk(clk),.a(vector[11*16+:16]),.b(matrix[11*16+:16]),.c(tmp[11*16+:16])); + signedmul mult_u12(.clk(clk),.a(vector[12*16+:16]),.b(matrix[12*16+:16]),.c(tmp[12*16+:16])); + signedmul mult_u13(.clk(clk),.a(vector[13*16+:16]),.b(matrix[13*16+:16]),.c(tmp[13*16+:16])); + signedmul mult_u14(.clk(clk),.a(vector[14*16+:16]),.b(matrix[14*16+:16]),.c(tmp[14*16+:16])); + signedmul mult_u15(.clk(clk),.a(vector[15*16+:16]),.b(matrix[15*16+:16]),.c(tmp[15*16+:16])); + signedmul mult_u16(.clk(clk),.a(vector[16*16+:16]),.b(matrix[16*16+:16]),.c(tmp[16*16+:16])); + signedmul mult_u17(.clk(clk),.a(vector[17*16+:16]),.b(matrix[17*16+:16]),.c(tmp[17*16+:16])); + signedmul mult_u18(.clk(clk),.a(vector[18*16+:16]),.b(matrix[18*16+:16]),.c(tmp[18*16+:16])); + signedmul mult_u19(.clk(clk),.a(vector[19*16+:16]),.b(matrix[19*16+:16]),.c(tmp[19*16+:16])); + signedmul mult_u20(.clk(clk),.a(vector[20*16+:16]),.b(matrix[20*16+:16]),.c(tmp[20*16+:16])); + signedmul mult_u21(.clk(clk),.a(vector[21*16+:16]),.b(matrix[21*16+:16]),.c(tmp[21*16+:16])); + signedmul mult_u22(.clk(clk),.a(vector[22*16+:16]),.b(matrix[22*16+:16]),.c(tmp[22*16+:16])); + signedmul mult_u23(.clk(clk),.a(vector[23*16+:16]),.b(matrix[23*16+:16]),.c(tmp[23*16+:16])); + signedmul mult_u24(.clk(clk),.a(vector[24*16+:16]),.b(matrix[24*16+:16]),.c(tmp[24*16+:16])); + signedmul mult_u25(.clk(clk),.a(vector[25*16+:16]),.b(matrix[25*16+:16]),.c(tmp[25*16+:16])); + signedmul mult_u26(.clk(clk),.a(vector[26*16+:16]),.b(matrix[26*16+:16]),.c(tmp[26*16+:16])); + signedmul mult_u27(.clk(clk),.a(vector[27*16+:16]),.b(matrix[27*16+:16]),.c(tmp[27*16+:16])); + signedmul mult_u28(.clk(clk),.a(vector[28*16+:16]),.b(matrix[28*16+:16]),.c(tmp[28*16+:16])); + signedmul mult_u29(.clk(clk),.a(vector[29*16+:16]),.b(matrix[29*16+:16]),.c(tmp[29*16+:16])); + signedmul mult_u30(.clk(clk),.a(vector[30*16+:16]),.b(matrix[30*16+:16]),.c(tmp[30*16+:16])); + signedmul mult_u31(.clk(clk),.a(vector[31*16+:16]),.b(matrix[31*16+:16]),.c(tmp[31*16+:16])); + signedmul mult_u32(.clk(clk),.a(vector[32*16+:16]),.b(matrix[32*16+:16]),.c(tmp[32*16+:16])); + signedmul mult_u33(.clk(clk),.a(vector[33*16+:16]),.b(matrix[33*16+:16]),.c(tmp[33*16+:16])); + signedmul mult_u34(.clk(clk),.a(vector[34*16+:16]),.b(matrix[34*16+:16]),.c(tmp[34*16+:16])); + signedmul mult_u35(.clk(clk),.a(vector[35*16+:16]),.b(matrix[35*16+:16]),.c(tmp[35*16+:16])); + signedmul mult_u36(.clk(clk),.a(vector[36*16+:16]),.b(matrix[36*16+:16]),.c(tmp[36*16+:16])); + signedmul mult_u37(.clk(clk),.a(vector[37*16+:16]),.b(matrix[37*16+:16]),.c(tmp[37*16+:16])); + signedmul mult_u38(.clk(clk),.a(vector[38*16+:16]),.b(matrix[38*16+:16]),.c(tmp[38*16+:16])); + signedmul mult_u39(.clk(clk),.a(vector[39*16+:16]),.b(matrix[39*16+:16]),.c(tmp[39*16+:16])); + signedmul mult_u40(.clk(clk),.a(vector[40*16+:16]),.b(matrix[40*16+:16]),.c(tmp[40*16+:16])); + signedmul mult_u41(.clk(clk),.a(vector[41*16+:16]),.b(matrix[41*16+:16]),.c(tmp[41*16+:16])); + signedmul mult_u42(.clk(clk),.a(vector[42*16+:16]),.b(matrix[42*16+:16]),.c(tmp[42*16+:16])); + signedmul mult_u43(.clk(clk),.a(vector[43*16+:16]),.b(matrix[43*16+:16]),.c(tmp[43*16+:16])); + signedmul mult_u44(.clk(clk),.a(vector[44*16+:16]),.b(matrix[44*16+:16]),.c(tmp[44*16+:16])); + signedmul mult_u45(.clk(clk),.a(vector[45*16+:16]),.b(matrix[45*16+:16]),.c(tmp[45*16+:16])); + signedmul mult_u46(.clk(clk),.a(vector[46*16+:16]),.b(matrix[46*16+:16]),.c(tmp[46*16+:16])); + signedmul mult_u47(.clk(clk),.a(vector[47*16+:16]),.b(matrix[47*16+:16]),.c(tmp[47*16+:16])); + signedmul mult_u48(.clk(clk),.a(vector[48*16+:16]),.b(matrix[48*16+:16]),.c(tmp[48*16+:16])); + signedmul mult_u49(.clk(clk),.a(vector[49*16+:16]),.b(matrix[49*16+:16]),.c(tmp[49*16+:16])); + signedmul mult_u50(.clk(clk),.a(vector[50*16+:16]),.b(matrix[50*16+:16]),.c(tmp[50*16+:16])); + signedmul mult_u51(.clk(clk),.a(vector[51*16+:16]),.b(matrix[51*16+:16]),.c(tmp[51*16+:16])); + signedmul mult_u52(.clk(clk),.a(vector[52*16+:16]),.b(matrix[52*16+:16]),.c(tmp[52*16+:16])); + signedmul mult_u53(.clk(clk),.a(vector[53*16+:16]),.b(matrix[53*16+:16]),.c(tmp[53*16+:16])); + signedmul mult_u54(.clk(clk),.a(vector[54*16+:16]),.b(matrix[54*16+:16]),.c(tmp[54*16+:16])); + signedmul mult_u55(.clk(clk),.a(vector[55*16+:16]),.b(matrix[55*16+:16]),.c(tmp[55*16+:16])); + signedmul mult_u56(.clk(clk),.a(vector[56*16+:16]),.b(matrix[56*16+:16]),.c(tmp[56*16+:16])); + signedmul mult_u57(.clk(clk),.a(vector[57*16+:16]),.b(matrix[57*16+:16]),.c(tmp[57*16+:16])); + signedmul mult_u58(.clk(clk),.a(vector[58*16+:16]),.b(matrix[58*16+:16]),.c(tmp[58*16+:16])); + signedmul mult_u59(.clk(clk),.a(vector[59*16+:16]),.b(matrix[59*16+:16]),.c(tmp[59*16+:16])); + signedmul mult_u60(.clk(clk),.a(vector[60*16+:16]),.b(matrix[60*16+:16]),.c(tmp[60*16+:16])); + signedmul mult_u61(.clk(clk),.a(vector[61*16+:16]),.b(matrix[61*16+:16]),.c(tmp[61*16+:16])); + signedmul mult_u62(.clk(clk),.a(vector[62*16+:16]),.b(matrix[62*16+:16]),.c(tmp[62*16+:16])); + signedmul mult_u63(.clk(clk),.a(vector[63*16+:16]),.b(matrix[63*16+:16]),.c(tmp[63*16+:16])); + + + +endmodule + +module vecmat_add #(parameter arraysize=1024,parameter vectdepth=64) + ( + input clk,reset, + input [arraysize-1:0] mulout, + output reg [15:0] data_out + ); + + wire [15:0] tmp0, tmp1 ,tmp2 ,tmp3 ,tmp4 ,tmp5 ,tmp6 ,tmp7 ,tmp8 ,tmp9 ,tmp10 ,tmp11 ,tmp12 ,tmp13 ,tmp14 ,tmp15 ,tmp16 ,tmp17 ,tmp18 ,tmp19 ,tmp20 ,tmp21 ,tmp22 ,tmp23 ,tmp24 ,tmp25 ,tmp26 ,tmp27 ,tmp28 ,tmp29 ,tmp30 ,tmp31 ,tmp32 ,tmp33 ,tmp34 ,tmp35 ,tmp36 ,tmp37 ,tmp38 ,tmp39 ,tmp40 ,tmp41 ,tmp42 ,tmp43 ,tmp44 ,tmp45 ,tmp46 ,tmp47 ,tmp48 ,tmp49 ,tmp50,tmp51 ,tmp52 ,tmp53,tmp54 ,tmp55 ,tmp56 ,tmp57 ,tmp58, tmp59 ,tmp60 ,tmp61,tmp62; + reg[31:0] i; + reg [15:0] ff1,ff3,ff5,ff7,ff9,ff11,ff13,ff15,ff17,ff19,ff21,ff23,ff25,ff27,ff29,ff31; + + always @(posedge clk) begin + if(~reset) begin + data_out <= tmp61; + + //adding a flop pipeline stage + ff1 <= tmp1; + ff3 <= tmp3; + ff5 <= tmp5; + ff7 <= tmp7; + ff9 <= tmp9; + ff11 <= tmp11; + ff13 <= tmp13; + ff15 <= tmp15; + ff17 <= tmp17; + ff19 <= tmp19; + ff21 <= tmp21; + ff23 <= tmp23; + ff25 <= tmp25; + ff27 <= tmp27; + ff29 <= tmp29; + ff31 <= tmp31; + end + end + + // fixed point addition + qadd2 Add_u0(.a(mulout[16*0+:16]),.b(mulout[16*1+:16]),.c(tmp0)); + qadd2 Add_u2(.a(mulout[16*2+:16]),.b(mulout[16*3+:16]),.c(tmp2)); + qadd2 Add_u4(.a(mulout[16*4+:16]),.b(mulout[16*5+:16]),.c(tmp4)); + qadd2 Add_u6(.a(mulout[16*6+:16]),.b(mulout[16*7+:16]),.c(tmp6)); + qadd2 Add_u8(.a(mulout[16*8+:16]),.b(mulout[16*9+:16]),.c(tmp8)); + qadd2 Add_u10(.a(mulout[16*10+:16]),.b(mulout[16*11+:16]),.c(tmp10)); + qadd2 Add_u12(.a(mulout[16*12+:16]),.b(mulout[16*13+:16]),.c(tmp12)); + qadd2 Add_u14(.a(mulout[16*14+:16]),.b(mulout[16*15+:16]),.c(tmp14)); + qadd2 Add_u16(.a(mulout[16*16+:16]),.b(mulout[16*17+:16]),.c(tmp16)); + qadd2 Add_u18(.a(mulout[16*18+:16]),.b(mulout[16*19+:16]),.c(tmp18)); + qadd2 Add_u20(.a(mulout[16*20+:16]),.b(mulout[16*21+:16]),.c(tmp20)); + qadd2 Add_u22(.a(mulout[16*22+:16]),.b(mulout[16*23+:16]),.c(tmp22)); + qadd2 Add_u24(.a(mulout[16*24+:16]),.b(mulout[16*25+:16]),.c(tmp24)); + qadd2 Add_u26(.a(mulout[16*26+:16]),.b(mulout[16*27+:16]),.c(tmp26)); + qadd2 Add_u28(.a(mulout[16*28+:16]),.b(mulout[16*29+:16]),.c(tmp28)); + qadd2 Add_u30(.a(mulout[16*30+:16]),.b(mulout[16*31+:16]),.c(tmp30)); + qadd2 Add_u32(.a(mulout[16*32+:16]),.b(mulout[16*33+:16]),.c(tmp32)); + qadd2 Add_u34(.a(mulout[16*34+:16]),.b(mulout[16*35+:16]),.c(tmp34)); + qadd2 Add_u36(.a(mulout[16*36+:16]),.b(mulout[16*37+:16]),.c(tmp36)); + qadd2 Add_u38(.a(mulout[16*38+:16]),.b(mulout[16*39+:16]),.c(tmp38)); + qadd2 Add_u40(.a(mulout[16*40+:16]),.b(mulout[16*41+:16]),.c(tmp40)); + qadd2 Add_u42(.a(mulout[16*42+:16]),.b(mulout[16*43+:16]),.c(tmp42)); + qadd2 Add_u44(.a(mulout[16*44+:16]),.b(mulout[16*45+:16]),.c(tmp44)); + qadd2 Add_u46(.a(mulout[16*46+:16]),.b(mulout[16*47+:16]),.c(tmp46)); + qadd2 Add_u48(.a(mulout[16*48+:16]),.b(mulout[16*49+:16]),.c(tmp48)); + qadd2 Add_u50(.a(mulout[16*50+:16]),.b(mulout[16*51+:16]),.c(tmp50)); + qadd2 Add_u52(.a(mulout[16*52+:16]),.b(mulout[16*53+:16]),.c(tmp52)); + qadd2 Add_u54(.a(mulout[16*54+:16]),.b(mulout[16*55+:16]),.c(tmp54)); + qadd2 Add_u56(.a(mulout[16*56+:16]),.b(mulout[16*57+:16]),.c(tmp56)); + qadd2 Add_u58(.a(mulout[16*58+:16]),.b(mulout[16*59+:16]),.c(tmp58)); + qadd2 Add_u60(.a(mulout[16*60+:16]),.b(mulout[16*61+:16]),.c(tmp60)); + qadd2 Add_u62(.a(mulout[16*62+:16]),.b(mulout[16*63+:16]),.c(tmp62)); + + qadd2 Add_u1(.a(tmp0),.b(tmp2),.c(tmp1)); + qadd2 Add_u3(.a(tmp4),.b(tmp6),.c(tmp3)); + qadd2 Add_u5(.a(tmp8),.b(tmp10),.c(tmp5)); + qadd2 Add_u7(.a(tmp12),.b(tmp14),.c(tmp7)); + qadd2 Add_u9(.a(tmp16),.b(tmp18),.c(tmp9)); + qadd2 Add_u11(.a(tmp20),.b(tmp22),.c(tmp11)); + qadd2 Add_u13(.a(tmp24),.b(tmp26),.c(tmp13)); + qadd2 Add_u15(.a(tmp28),.b(tmp30),.c(tmp15)); + qadd2 Add_u17(.a(tmp32),.b(tmp34),.c(tmp17)); + qadd2 Add_u19(.a(tmp36),.b(tmp38),.c(tmp19)); + qadd2 Add_u21(.a(tmp40),.b(tmp42),.c(tmp21)); + qadd2 Add_u23(.a(tmp44),.b(tmp46),.c(tmp23)); + qadd2 Add_u25(.a(tmp48),.b(tmp50),.c(tmp25)); + qadd2 Add_u27(.a(tmp52),.b(tmp54),.c(tmp27)); + qadd2 Add_u29(.a(tmp56),.b(tmp58),.c(tmp29)); + qadd2 Add_u31(.a(tmp60),.b(tmp62),.c(tmp31)); + + qadd2 Add_u33(.a(ff1),.b(ff3),.c(tmp33)); + qadd2 Add_u35(.a(ff5),.b(ff7),.c(tmp35)); + qadd2 Add_u37(.a(ff9),.b(ff11),.c(tmp37)); + qadd2 Add_u39(.a(ff13),.b(ff15),.c(tmp39)); + qadd2 Add_u41(.a(ff17),.b(ff19),.c(tmp41)); + qadd2 Add_u43(.a(ff21),.b(ff23),.c(tmp43)); + qadd2 Add_u45(.a(ff25),.b(ff27),.c(tmp45)); + qadd2 Add_u47(.a(ff29),.b(ff31),.c(tmp47)); + + qadd2 Add_u49(.a(tmp33),.b(tmp35),.c(tmp49)); + qadd2 Add_u51(.a(tmp37),.b(tmp39),.c(tmp51)); + qadd2 Add_u53(.a(tmp41),.b(tmp43),.c(tmp53)); + qadd2 Add_u55(.a(tmp45),.b(tmp47),.c(tmp55)); + + qadd2 Add_u57(.a(tmp49),.b(tmp51),.c(tmp57)); + qadd2 Add_u59(.a(tmp53),.b(tmp55),.c(tmp59)); + + qadd2 Add_u61(.a(tmp57),.b(tmp59),.c(tmp61)); + +endmodule + +module vecmat_mul_32 #( parameter arraysize=512,parameter vectdepth=32) //,matsize=64) // varraysize=1024 vectwidth=64,matsize=4096 +( + input clk, + input reset, + input [arraysize-1:0] vector, //softmax vector + input [arraysize-1:0] matrix, //vector from V matrix + output [arraysize-1:0] tmp + ); + +/*always @(posedge clk) begin + if(~reset) begin + + vector <= data; + matrix <= W; + + end + end */ + + + signedmul mult_u0(.clk(clk),.a(vector[0*16+:16]),.b(matrix[0*16+:16]),.c(tmp[0*16+:16])); + signedmul mult_u1(.clk(clk),.a(vector[1*16+:16]),.b(matrix[1*16+:16]),.c(tmp[1*16+:16])); + signedmul mult_u2(.clk(clk),.a(vector[2*16+:16]),.b(matrix[2*16+:16]),.c(tmp[2*16+:16])); + signedmul mult_u3(.clk(clk),.a(vector[3*16+:16]),.b(matrix[3*16+:16]),.c(tmp[3*16+:16])); + signedmul mult_u4(.clk(clk),.a(vector[4*16+:16]),.b(matrix[4*16+:16]),.c(tmp[4*16+:16])); + signedmul mult_u5(.clk(clk),.a(vector[5*16+:16]),.b(matrix[5*16+:16]),.c(tmp[5*16+:16])); + signedmul mult_u6(.clk(clk),.a(vector[6*16+:16]),.b(matrix[6*16+:16]),.c(tmp[6*16+:16])); + signedmul mult_u7(.clk(clk),.a(vector[7*16+:16]),.b(matrix[7*16+:16]),.c(tmp[7*16+:16])); + signedmul mult_u8(.clk(clk),.a(vector[8*16+:16]),.b(matrix[8*16+:16]),.c(tmp[8*16+:16])); + signedmul mult_u9(.clk(clk),.a(vector[9*16+:16]),.b(matrix[9*16+:16]),.c(tmp[9*16+:16])); + signedmul mult_u10(.clk(clk),.a(vector[10*16+:16]),.b(matrix[10*16+:16]),.c(tmp[10*16+:16])); + signedmul mult_u11(.clk(clk),.a(vector[11*16+:16]),.b(matrix[11*16+:16]),.c(tmp[11*16+:16])); + signedmul mult_u12(.clk(clk),.a(vector[12*16+:16]),.b(matrix[12*16+:16]),.c(tmp[12*16+:16])); + signedmul mult_u13(.clk(clk),.a(vector[13*16+:16]),.b(matrix[13*16+:16]),.c(tmp[13*16+:16])); + signedmul mult_u14(.clk(clk),.a(vector[14*16+:16]),.b(matrix[14*16+:16]),.c(tmp[14*16+:16])); + signedmul mult_u15(.clk(clk),.a(vector[15*16+:16]),.b(matrix[15*16+:16]),.c(tmp[15*16+:16])); + signedmul mult_u16(.clk(clk),.a(vector[16*16+:16]),.b(matrix[16*16+:16]),.c(tmp[16*16+:16])); + signedmul mult_u17(.clk(clk),.a(vector[17*16+:16]),.b(matrix[17*16+:16]),.c(tmp[17*16+:16])); + signedmul mult_u18(.clk(clk),.a(vector[18*16+:16]),.b(matrix[18*16+:16]),.c(tmp[18*16+:16])); + signedmul mult_u19(.clk(clk),.a(vector[19*16+:16]),.b(matrix[19*16+:16]),.c(tmp[19*16+:16])); + signedmul mult_u20(.clk(clk),.a(vector[20*16+:16]),.b(matrix[20*16+:16]),.c(tmp[20*16+:16])); + signedmul mult_u21(.clk(clk),.a(vector[21*16+:16]),.b(matrix[21*16+:16]),.c(tmp[21*16+:16])); + signedmul mult_u22(.clk(clk),.a(vector[22*16+:16]),.b(matrix[22*16+:16]),.c(tmp[22*16+:16])); + signedmul mult_u23(.clk(clk),.a(vector[23*16+:16]),.b(matrix[23*16+:16]),.c(tmp[23*16+:16])); + signedmul mult_u24(.clk(clk),.a(vector[24*16+:16]),.b(matrix[24*16+:16]),.c(tmp[24*16+:16])); + signedmul mult_u25(.clk(clk),.a(vector[25*16+:16]),.b(matrix[25*16+:16]),.c(tmp[25*16+:16])); + signedmul mult_u26(.clk(clk),.a(vector[26*16+:16]),.b(matrix[26*16+:16]),.c(tmp[26*16+:16])); + signedmul mult_u27(.clk(clk),.a(vector[27*16+:16]),.b(matrix[27*16+:16]),.c(tmp[27*16+:16])); + signedmul mult_u28(.clk(clk),.a(vector[28*16+:16]),.b(matrix[28*16+:16]),.c(tmp[28*16+:16])); + signedmul mult_u29(.clk(clk),.a(vector[29*16+:16]),.b(matrix[29*16+:16]),.c(tmp[29*16+:16])); + signedmul mult_u30(.clk(clk),.a(vector[30*16+:16]),.b(matrix[30*16+:16]),.c(tmp[30*16+:16])); + signedmul mult_u31(.clk(clk),.a(vector[31*16+:16]),.b(matrix[31*16+:16]),.c(tmp[31*16+:16])); + + +endmodule + +module vecmat_add_32 #(parameter arraysize=512,parameter vectdepth=32) + ( + input clk,reset, + input [arraysize-1:0] mulout, + output reg [15:0] data_out + ); + + wire [15:0] tmp0, tmp1 ,tmp2 ,tmp3 ,tmp4 ,tmp5 ,tmp6 ,tmp7 ,tmp8 ,tmp9 ,tmp10 ,tmp11 ,tmp12 ,tmp13 ,tmp14 ,tmp15 ,tmp16 ,tmp17 ,tmp18 ,tmp19 ,tmp20 ,tmp21 ,tmp22 ,tmp23 ,tmp24 ,tmp25 ,tmp26 ,tmp27 ,tmp28 ,tmp29 ,tmp30 ,tmp31 ,tmp32 ,tmp33 ,tmp34 ,tmp35 ,tmp36 ,tmp37 ,tmp38 ,tmp39 ,tmp40 ,tmp41 ,tmp42 ,tmp43 ,tmp44 ,tmp45 ,tmp46 ,tmp47 ,tmp48 ,tmp49 ,tmp50,tmp51 ,tmp52 ,tmp53,tmp54 ,tmp55 ,tmp56 ,tmp57 ,tmp58, tmp59 ,tmp60 ,tmp61,tmp62; + reg[31:0] i; + reg [15:0] ff1,ff3,ff5,ff7,ff9,ff11,ff13,ff15,ff17,ff19,ff21,ff23,ff25,ff27,ff29,ff31; + + always @(posedge clk) begin + if(~reset) begin + data_out <= tmp57; + + //adding a flop pipeline stage + ff1 <= tmp1; + ff3 <= tmp3; + ff5 <= tmp5; + ff7 <= tmp7; + ff9 <= tmp9; + ff11 <= tmp11; + ff13 <= tmp13; + ff15 <= tmp15; + end + end + + // fixed point addition + qadd2 Add_u0(.a(mulout[16*0+:16]),.b(mulout[16*1+:16]),.c(tmp0)); + qadd2 Add_u2(.a(mulout[16*2+:16]),.b(mulout[16*3+:16]),.c(tmp2)); + qadd2 Add_u4(.a(mulout[16*4+:16]),.b(mulout[16*5+:16]),.c(tmp4)); + qadd2 Add_u6(.a(mulout[16*6+:16]),.b(mulout[16*7+:16]),.c(tmp6)); + qadd2 Add_u8(.a(mulout[16*8+:16]),.b(mulout[16*9+:16]),.c(tmp8)); + qadd2 Add_u10(.a(mulout[16*10+:16]),.b(mulout[16*11+:16]),.c(tmp10)); + qadd2 Add_u12(.a(mulout[16*12+:16]),.b(mulout[16*13+:16]),.c(tmp12)); + qadd2 Add_u14(.a(mulout[16*14+:16]),.b(mulout[16*15+:16]),.c(tmp14)); + qadd2 Add_u16(.a(mulout[16*16+:16]),.b(mulout[16*17+:16]),.c(tmp16)); + qadd2 Add_u18(.a(mulout[16*18+:16]),.b(mulout[16*19+:16]),.c(tmp18)); + qadd2 Add_u20(.a(mulout[16*20+:16]),.b(mulout[16*21+:16]),.c(tmp20)); + qadd2 Add_u22(.a(mulout[16*22+:16]),.b(mulout[16*23+:16]),.c(tmp22)); + qadd2 Add_u24(.a(mulout[16*24+:16]),.b(mulout[16*25+:16]),.c(tmp24)); + qadd2 Add_u26(.a(mulout[16*26+:16]),.b(mulout[16*27+:16]),.c(tmp26)); + qadd2 Add_u28(.a(mulout[16*28+:16]),.b(mulout[16*29+:16]),.c(tmp28)); + qadd2 Add_u30(.a(mulout[16*30+:16]),.b(mulout[16*31+:16]),.c(tmp30)); + + qadd2 Add_u1(.a(tmp0),.b(tmp2),.c(tmp1)); + qadd2 Add_u3(.a(tmp4),.b(tmp6),.c(tmp3)); + qadd2 Add_u5(.a(tmp8),.b(tmp10),.c(tmp5)); + qadd2 Add_u7(.a(tmp12),.b(tmp14),.c(tmp7)); + qadd2 Add_u9(.a(tmp16),.b(tmp18),.c(tmp9)); + qadd2 Add_u11(.a(tmp20),.b(tmp22),.c(tmp11)); + qadd2 Add_u13(.a(tmp24),.b(tmp26),.c(tmp13)); + qadd2 Add_u15(.a(tmp28),.b(tmp30),.c(tmp15)); + + qadd2 Add_u33(.a(ff1),.b(ff3),.c(tmp33)); + qadd2 Add_u35(.a(ff5),.b(ff7),.c(tmp35)); + qadd2 Add_u37(.a(ff9),.b(ff11),.c(tmp37)); + qadd2 Add_u39(.a(ff13),.b(ff15),.c(tmp39)); + + qadd2 Add_u49(.a(tmp33),.b(tmp35),.c(tmp49)); + qadd2 Add_u51(.a(tmp37),.b(tmp39),.c(tmp51)); + + qadd2 Add_u57(.a(tmp49),.b(tmp51),.c(tmp57)); + +endmodule + +module signedmul( + input clk, + input [15:0] a, + input [15:0] b, + output [15:0] c +); + +wire [31:0] result; +wire [15:0] a_new; +wire [15:0] b_new; + +reg [15:0] a_ff; +reg [15:0] b_ff; +reg [31:0] result_ff; +reg a_sign,b_sign,a_sign_ff,b_sign_ff; + +assign c = (b_sign_ff==a_sign_ff)?result_ff[26:12]:(~result_ff[26:12]+1'b1); +assign a_new = a[15]?(~a + 1'b1):a; +assign b_new = b[15]?(~b + 1'b1):b; +assign result = a_ff*b_ff; + +always@(posedge clk) begin + a_ff <= a_new; + b_ff <= b_new; + + a_sign <= a[15]; + b_sign <= b[15]; + a_sign_ff <= a_sign; + b_sign_ff <= b_sign; + result_ff <= result; + +end + + +endmodule + + +module qadd2( + input [15:0] a, + input [15:0] b, + output [15:0] c + ); + +assign c = a + b; + + +endmodule + + + +module dpram ( +input clk, +input [4:0] address_a, +input [4:0] address_b, +input wren_a, +input wren_b, +input [(`VECTOR_BITS-1):0] data_a, +input [(`VECTOR_BITS-1):0] data_b, +output reg [(`VECTOR_BITS-1):0] out_a, +output reg [(`VECTOR_BITS-1):0] out_b +); + + +`ifndef hard_mem + +reg [`VECTOR_BITS-1:0] ram[`NUM_WORDS-1:0]; + +always @ (posedge clk) begin + if (wren_a) begin + ram[address_a] <= data_a; + end + else begin + out_a <= ram[address_a]; + end +end + +always @ (posedge clk) begin + if (wren_b) begin + ram[address_b] <= data_b; + end + else begin + out_b <= ram[address_b]; + end +end + +`else + +defparam u_dual_port_ram.ADDR_WIDTH = 5; +defparam u_dual_port_ram.DATA_WIDTH = `VECTOR_BITS; + +dual_port_ram u_dual_port_ram( +.addr1(address_a), +.we1(wren_a), +.data1(data_a), +.out1(out_a), +.addr2(address_b), +.we2(wren_b), +.data2(data_b), +.out2(out_b), +.clk(clk) +); + +`endif + +endmodule + + +module dpram_t ( +input clk, +input [4:0] address_a, +input [4:0] address_b, +input wren_a, +input wren_b, +input [((`NUM_WORDS*`DATA_WIDTH)-1):0] data_a, +input [((`NUM_WORDS*`DATA_WIDTH)-1):0] data_b, +output reg [((`NUM_WORDS*`DATA_WIDTH)-1):0] out_a, +output reg [((`NUM_WORDS*`DATA_WIDTH)-1):0] out_b +); + + +`ifndef hard_mem + +reg [(`NUM_WORDS*`DATA_WIDTH)-1:0] ram[`VECTOR_DEPTH-1:0]; + +always @ (posedge clk) begin + if (wren_a) begin + ram[address_a] <= data_a; + end + else begin + out_a <= ram[address_a]; + end +end + +always @ (posedge clk) begin + if (wren_b) begin + ram[address_b] <= data_b; + end + else begin + out_b <= ram[address_b]; + end +end + +`else + +defparam u_dual_port_ram.ADDR_WIDTH = 5; +defparam u_dual_port_ram.DATA_WIDTH = `NUM_WORDS*`DATA_WIDTH; + +dual_port_ram u_dual_port_ram( +.addr1(address_a), +.we1(wren_a), +.data1(data_a), +.out1(out_a), +.addr2(address_b), +.we2(wren_b), +.data2(data_b), +.out2(out_b), +.clk(clk) +); + +`endif + +endmodule + +module dpram_small ( +input clk, +input [8:0] address_a, +input [8:0] address_b, +input wren_a, +input wren_b, +input [`DATA_WIDTH-1:0] data_a, +input [`DATA_WIDTH-1:0] data_b, +output reg [`DATA_WIDTH-1:0] out_a, +output reg [`DATA_WIDTH-1:0] out_b +); + + +`ifndef hard_mem + +reg [`DATA_WIDTH-1:0] ram[`OUT_RAM_DEPTH-1:0]; + +always @ (posedge clk) begin + if (wren_a) begin + ram[address_a] <= data_a; + end + out_a <= ram[address_a]; +end + +always @ (posedge clk) begin + if (wren_b) begin + ram[address_b] <= data_b; + end + out_b <= ram[address_b]; +end + +`else +defparam u_dual_port_ram.ADDR_WIDTH = 9; +defparam u_dual_port_ram.DATA_WIDTH = `DATA_WIDTH; + +dual_port_ram u_dual_port_ram( +.addr1(address_a), +.we1(wren_a), +.data1(data_a), +.out1(out_a), +.addr2(address_b), +.we2(wren_b), +.data2(data_b), +.out2(out_b), +.clk(clk) +); + +`endif + +endmodule + + + +module wordwise_bram ( + addr0, + d0, + we0, + q0, + addr1, + d1, + we1, + q1, + clk); + +input [`BUF_AWIDTH-1:0] addr0; +input [`BUF_AWIDTH-1:0] addr1; +input [`BUF_LOC_SIZE*`DATA_WIDTH-1:0] d0; +input [`BUF_LOC_SIZE*`DATA_WIDTH-1:0] d1; +input [`BUF_LOC_SIZE-1:0] we0; +input [`BUF_LOC_SIZE-1:0] we1; +output [`BUF_LOC_SIZE*`DATA_WIDTH-1:0] q0; +output [`BUF_LOC_SIZE*`DATA_WIDTH-1:0] q1; +input clk; + +genvar i; + +generate +`ifdef QUARTUS + for (i=0;i<`BUF_LOC_SIZE;i=i+1) begin: gen_dpram +`else + for (i=0;i<`BUF_LOC_SIZE;i=i+1) begin +`endif + dpram_original #(.AWIDTH(`BUF_AWIDTH),.DWIDTH(`DATA_WIDTH),.NUM_WORDS(1<<`BUF_AWIDTH)) dp1 (.clk(clk),.address_a(addr0),.address_b(addr1),.wren_a(we0[i]),.wren_b(we1[i]),.data_a(d0[i*`DATA_WIDTH +: `DATA_WIDTH]),.data_b(d1[i*`DATA_WIDTH +: `DATA_WIDTH]),.out_a(q0[i*`DATA_WIDTH +: `DATA_WIDTH]),.out_b(q1[i*`DATA_WIDTH +: `DATA_WIDTH])); + end +endgenerate + +endmodule + + +module wordwise_bram_2 ( + addr0, + d0, + we0, + q0, + addr1, + d1, + we1, + q1, + clk); + +input addr0; +input addr1; +input [8*`BUF_LOC_SIZE*`DATA_WIDTH-1:0] d0; +input [8*`BUF_LOC_SIZE*`DATA_WIDTH-1:0] d1; +input [8*`BUF_LOC_SIZE-1:0] we0; +input [8*`BUF_LOC_SIZE-1:0] we1; +output [8*`BUF_LOC_SIZE*`DATA_WIDTH-1:0] q0; +output [8*`BUF_LOC_SIZE*`DATA_WIDTH-1:0] q1; +input clk; + +genvar i; + +generate +`ifdef QUARTUS + for (i=0;i<`NUM_WORDS;i=i+1) begin: gen_dpram_2 +`else + for (i=0;i<`NUM_WORDS;i=i+1) begin +`endif + dpram_original #(.AWIDTH(1),.DWIDTH(`DATA_WIDTH),.NUM_WORDS(1<<1)) dp1 (.clk(clk),.address_a(addr0),.address_b(addr1),.wren_a(we0[i]),.wren_b(we1[i]),.data_a(d0[i*`DATA_WIDTH +: `DATA_WIDTH]),.data_b(d1[i*`DATA_WIDTH +: `DATA_WIDTH]),.out_a(q0[i*`DATA_WIDTH +: `DATA_WIDTH]),.out_b(q1[i*`DATA_WIDTH +: `DATA_WIDTH])); + end +endgenerate + +endmodule + + +module dpram_original ( + clk, + address_a, + address_b, + wren_a, + wren_b, + data_a, + data_b, + out_a, + out_b +); +parameter AWIDTH=10; +parameter NUM_WORDS=1024; +parameter DWIDTH=32; +input clk; +input [(AWIDTH-1):0] address_a; +input [(AWIDTH-1):0] address_b; +input wren_a; +input wren_b; +input [(DWIDTH-1):0] data_a; +input [(DWIDTH-1):0] data_b; +output reg [(DWIDTH-1):0] out_a; +output reg [(DWIDTH-1):0] out_b; + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram[NUM_WORDS-1:0]; +always @ (posedge clk) begin + if (wren_a) begin + ram[address_a] <= data_a; + end + out_a <= ram[address_a]; +end + +always @ (posedge clk) begin + if (wren_b) begin + ram[address_b] <= data_b; + end + out_b <= ram[address_b]; +end + +`else + +defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; +defparam u_dual_port_ram.DATA_WIDTH = DWIDTH; + +dual_port_ram u_dual_port_ram( +.addr1(address_a), +.we1(wren_a), +.data1(data_a), +.out1(out_a), +.addr2(address_b), +.we2(wren_b), +.data2(data_b), +.out2(out_b), +.clk(clk) +); + +`endif +endmodule + +///////////////////////////////////////////////////////////////// +// Softmax block +// Authors: Pragnesh Patel and Aman Arora +///////////////////////////////////////////////////////////////// + +//softmax_p4_smem_rfixed16_alut_v512_b2_0_10.v +`ifndef DEFINES_DONE +`define DEFINES_DONE +`define DATAWIDTH (`SIGN+`EXPONENT+`MANTISSA) +`define IEEE_COMPLIANCE 1 +`define NUM 4 +`define ADDRSIZE 4 +`endif + +//fixed adder adds unsigned fixed numbers. Overflow flag is high in case of overflow +module softmax( + inp, //data in from memory to max block + sub0_inp, //data inputs from memory to first-stage subtractors + sub1_inp, //data inputs from memory to second-stage subtractors + + start_addr, //the first address that contains input data in the on-chip memory + end_addr, //max address containing required data + + addr, //address corresponding to data inp + sub0_inp_addr, //address corresponding to sub0_inp + sub1_inp_addr, //address corresponding to sub1_inp + //addr_sel, + outp0, + outp1, + outp2, + outp3, + + clk, + reset, + init, //the signal indicating to latch the new start address + done, //done signal asserts when the softmax calculation is over + start); //start signal for the overall softmax operation + + input clk; + input reset; + input start; + input init; + + input [`DATAWIDTH*`NUM-1:0] inp; + input [`DATAWIDTH*`NUM-1:0] sub0_inp; + input [`DATAWIDTH*`NUM-1:0] sub1_inp; + input [`ADDRSIZE-1:0] end_addr; + input [`ADDRSIZE-1:0] start_addr; + + output [`ADDRSIZE-1 :0] addr; + output [`ADDRSIZE-1:0] sub0_inp_addr; + output [`ADDRSIZE-1:0] sub1_inp_addr; + //output addr_sel; + output [`DATAWIDTH-1:0] outp0; + output [`DATAWIDTH-1:0] outp1; + output [`DATAWIDTH-1:0] outp2; + output [`DATAWIDTH-1:0] outp3; + output done; + + reg [`DATAWIDTH*`NUM-1:0] inp_reg; + reg [`ADDRSIZE-1:0] addr; + reg [`DATAWIDTH*`NUM-1:0] sub0_inp_reg; + reg [`DATAWIDTH*`NUM-1:0] sub1_inp_reg; + reg [`ADDRSIZE-1:0] sub0_inp_addr; + reg [`ADDRSIZE-1:0] sub1_inp_addr; + + + ////-----------control signals--------------//// + reg mode1_start; + reg mode1_run; + reg mode2_start; + reg mode2_run; + + reg mode3_stage_run2; + reg mode3_stage_run; + reg mode7_stage_run2; + reg mode7_stage_run; + + reg mode3_run; + + reg mode1_stage1_run_a; + reg mode1_stage0_run; + reg mode1_stage1_run; + wire mode1_stage2_run; + assign mode1_stage2_run = mode1_run; + + reg mode4_stage1_run_a; + reg mode4_stage2_run_a; + reg mode4_stage0_run; + reg mode4_stage1_run; + reg mode4_stage2_run; + + reg mode5_run; + reg mode6_run; + reg mode7_run; + reg presub_start; + reg presub_run; + reg presub_run_2; + reg presub_run_1; + reg presub_run_0; + reg done; + + //assign addr_sel = mode1_run & ~mode2_start; + + always @(posedge clk)begin + mode4_stage1_run_a <= mode4_stage1_run; + mode4_stage2_run_a <= mode4_stage2_run; + end + + always @(posedge clk)begin + mode1_stage1_run_a <= mode1_stage1_run; + end + + always @(posedge clk) begin + if(reset) begin + addr <= 0; + mode1_start <= 0; + mode1_run <= 0; + end + //init latch the input address + else if(init) begin + addr <= start_addr; + end + //start the mode1 max calculation + else if(start)begin + mode1_start <= 1; + end + //logic when to finish mode1 and trigger mode2 to latch the mode2 address + else if(mode1_start && addr < end_addr) begin + addr <= addr + 1'b1; + mode1_run <= 1; + end else if(addr == end_addr)begin + addr <= 0; + mode1_run <= 0; + mode1_start <= 0; + end else begin + mode1_run <= 0; + end + end + + //always @(posedge clk) begin + // if(reset) begin + // mode1_stage2_run <= 0; + // end + // else if (mode1_run == 1) begin + // mode1_stage2_run <= 1; + // end + // else begin + // mode1_stage2_run <= 0; + // end + //end + + always @(posedge clk) begin + if(reset) begin + mode1_stage1_run <= 0; + end + else if (mode1_stage2_run == 1) begin + mode1_stage1_run <= 1; + end + else begin + mode1_stage1_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode1_stage0_run <= 0; + end + else if (mode1_stage1_run == 1) begin + mode1_stage0_run <= 1; + end + else begin + mode1_stage0_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + sub0_inp_addr <= 0; + sub0_inp_reg <= 0; + mode2_start <= 0; + mode2_run <= 0; + end + else if (mode1_stage1_run_a & ~mode1_stage1_run) begin + //else if ((mode1_start) && (addr == (end_addr - 1))) begin + mode2_start <= 1; + sub0_inp_addr <= start_addr; + end + //logic when to finish mode2 + else if(mode2_start && sub0_inp_addr < end_addr) begin + sub0_inp_addr <= sub0_inp_addr + 1'b1; + sub0_inp_reg <= sub0_inp; + mode2_run <= 1; + end + else if(sub0_inp_addr == end_addr)begin + sub0_inp_addr <= 0; + sub0_inp_reg <= 0; + mode2_run <= 0; + mode2_start <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode3_stage_run2 <= 0; + end + //logic when to trigger mode3 + else if(mode2_run == 1) begin + mode3_stage_run2 <= 1; + end else begin + mode3_stage_run2 <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode3_stage_run <= 0; + end + else if(mode3_stage_run2 == 1) begin + mode3_stage_run <= 1; + end else begin + mode3_stage_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode3_run <= 0; + end + else if(mode3_stage_run == 1) begin + mode3_run <= 1; + end else begin + mode3_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode4_stage2_run <= 0; + end + //logic when to trigger mode4 last stage adderTree, since the final results of adderTree + //is always ready 1 cycle after mode3 finishes, so there is no need on extra + //logic to control the adderTree outputs + else if (mode3_run == 1) begin + mode4_stage2_run <= 1; + end else begin + mode4_stage2_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode4_stage1_run <= 0; + end + else if (mode4_stage2_run == 1) begin + mode4_stage1_run <= 1; + end else begin + mode4_stage1_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode4_stage0_run <= 0; + end + else if (mode4_stage1_run == 1) begin + mode4_stage0_run <= 1; + end else begin + mode4_stage0_run <= 0; + end + end + + reg mode5_stage0_run; + reg mode5_stage1_run; + reg mode5_stage2_run; + wire mode5_stage3_run = mode5_run; + + always @(posedge clk) begin + if(reset) begin + mode5_run <= 0; + end + //mode5 should be triggered right at the falling edge of mode4_stage1_run + else if(mode4_stage1_run_a & ~mode4_stage1_run) begin + mode5_run <= 1; + end + else if(mode4_stage1_run == 0) begin + mode5_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode5_stage2_run <= 0; + end + else if (mode5_stage3_run == 1) begin + mode5_stage2_run <= 1; + end + else begin + mode5_stage2_run <= 0; + end + end + always @(posedge clk) begin + if(reset) begin + mode5_stage1_run <= 0; + end + else if (mode5_stage2_run == 1) begin + mode5_stage1_run <= 1; + end + else begin + mode5_stage1_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode5_stage0_run <= 0; + end + else if (mode5_stage1_run == 1) begin + mode5_stage0_run <= 1; + end + else begin + mode5_stage0_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + presub_start <= 0; + sub1_inp_addr <= 0; + sub1_inp_reg <= 0; + presub_run <= 0; + end + else if(mode4_stage2_run_a & ~mode4_stage2_run) begin + presub_start <= 1; + sub1_inp_addr <= start_addr; + sub1_inp_reg <= sub1_inp; + end + else if(~reset && presub_start && sub1_inp_addr < end_addr)begin + sub1_inp_addr <= sub1_inp_addr + 1'b1; + sub1_inp_reg <= sub1_inp; + presub_run <= 1; + end + else if(sub1_inp_addr == end_addr) begin + presub_run <= 0; + presub_start <= 0; + sub1_inp_addr <= 0; + sub1_inp_reg <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + presub_run_2 <= 0; + end + else if (presub_run == 1) begin + presub_run_2 <= 1; + end + else begin + presub_run_2 <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + presub_run_1 <= 0; + end + else if (presub_run_2 == 1) begin + presub_run_1 <= 1; + end + else begin + presub_run_1 <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + presub_run_0 <= 0; + end + else if (presub_run_1 == 1) begin + presub_run_0 <= 1; + end + else begin + presub_run_0 <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode6_run <= 0; + end + else if(presub_run_0) begin + mode6_run <= 1; + end else begin + mode6_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode7_stage_run2 <= 0; + end + else if(mode6_run == 1) begin + mode7_stage_run2 <= 1; + end else begin + mode7_stage_run2 <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode7_stage_run <= 0; + end + else if(mode7_stage_run2 == 1) begin + mode7_stage_run <= 1; + end else begin + mode7_stage_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode7_run <= 0; + end + else if(mode7_stage_run == 1) begin + mode7_run <= 1; + end else begin + mode7_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + done <= 0; + end + else if(mode7_run) begin + done <= 1; + end else begin + done <= 0; + end + end + + ////------mode1 max block---------/////// + wire [`DATAWIDTH-1:0] max_outp; + + mode1_max_tree mode1_max( + .inp0(inp[`DATAWIDTH*1-1:`DATAWIDTH*0]), + .inp1(inp[`DATAWIDTH*2-1:`DATAWIDTH*1]), + .inp2(inp[`DATAWIDTH*3-1:`DATAWIDTH*2]), + .inp3(inp[`DATAWIDTH*4-1:`DATAWIDTH*3]), + .mode1_stage2_run(mode1_stage2_run), + .mode1_stage1_run(mode1_stage1_run), + .mode1_stage0_run(mode1_stage0_run), + .clk(clk), + .reset(reset), + .outp(max_outp)); + + ////------mode2 subtraction---------/////// + wire [`DATAWIDTH-1:0] mode2_outp_sub0; + wire [`DATAWIDTH-1:0] mode2_outp_sub1; + wire [`DATAWIDTH-1:0] mode2_outp_sub2; + wire [`DATAWIDTH-1:0] mode2_outp_sub3; + mode2_sub mode2_sub( + .a_inp0(sub0_inp_reg[`DATAWIDTH*1-1:`DATAWIDTH*0]), + .a_inp1(sub0_inp_reg[`DATAWIDTH*2-1:`DATAWIDTH*1]), + .a_inp2(sub0_inp_reg[`DATAWIDTH*3-1:`DATAWIDTH*2]), + .a_inp3(sub0_inp_reg[`DATAWIDTH*4-1:`DATAWIDTH*3]), + .outp0(mode2_outp_sub0), + .outp1(mode2_outp_sub1), + .outp2(mode2_outp_sub2), + .outp3(mode2_outp_sub3), + .b_inp(max_outp)); + + reg [`DATAWIDTH-1:0] mode2_outp_sub0_reg; + reg [`DATAWIDTH-1:0] mode2_outp_sub1_reg; + reg [`DATAWIDTH-1:0] mode2_outp_sub2_reg; + reg [`DATAWIDTH-1:0] mode2_outp_sub3_reg; + always @(posedge clk) begin + if (reset) begin + mode2_outp_sub0_reg <= 0; + mode2_outp_sub1_reg <= 0; + mode2_outp_sub2_reg <= 0; + mode2_outp_sub3_reg <= 0; + end else if (mode2_run) begin + mode2_outp_sub0_reg <= mode2_outp_sub0; + mode2_outp_sub1_reg <= mode2_outp_sub1; + mode2_outp_sub2_reg <= mode2_outp_sub2; + mode2_outp_sub3_reg <= mode2_outp_sub3; + end + end + + ////------mode3 exponential---------/////// + wire [`DATAWIDTH-1:0] mode3_outp_exp0; + wire [`DATAWIDTH-1:0] mode3_outp_exp1; + wire [`DATAWIDTH-1:0] mode3_outp_exp2; + wire [`DATAWIDTH-1:0] mode3_outp_exp3; + mode3_exp mode3_exp( + .inp0(mode2_outp_sub0_reg), + .inp1(mode2_outp_sub1_reg), + .inp2(mode2_outp_sub2_reg), + .inp3(mode2_outp_sub3_reg), + + .clk(clk), + .reset(reset), + .stage_run(mode3_stage_run), + .stage_run2(mode3_stage_run2), + + .outp0(mode3_outp_exp0), + .outp1(mode3_outp_exp1), + .outp2(mode3_outp_exp2), + .outp3(mode3_outp_exp3) + ); + + reg [`DATAWIDTH-1:0] mode3_outp_exp0_reg; + reg [`DATAWIDTH-1:0] mode3_outp_exp1_reg; + reg [`DATAWIDTH-1:0] mode3_outp_exp2_reg; + reg [`DATAWIDTH-1:0] mode3_outp_exp3_reg; + always @(posedge clk) begin + if (reset) begin + mode3_outp_exp0_reg <= 0; + mode3_outp_exp1_reg <= 0; + mode3_outp_exp2_reg <= 0; + mode3_outp_exp3_reg <= 0; + end else if (mode3_run) begin + mode3_outp_exp0_reg <= mode3_outp_exp0; + mode3_outp_exp1_reg <= mode3_outp_exp1; + mode3_outp_exp2_reg <= mode3_outp_exp2; + mode3_outp_exp3_reg <= mode3_outp_exp3; + end + end + + //////------mode4 pipelined adder tree---------/////// + wire [`DATAWIDTH-1:0] mode4_adder_tree_outp; + mode4_adder_tree mode4_adder_tree( + .inp0(mode3_outp_exp0_reg), + .inp1(mode3_outp_exp1_reg), + .inp2(mode3_outp_exp2_reg), + .inp3(mode3_outp_exp3_reg), + .mode4_stage2_run(mode4_stage2_run), + .mode4_stage1_run(mode4_stage1_run), + .mode4_stage0_run(mode4_stage0_run), + + .clk(clk), + .reset(reset), + .outp(mode4_adder_tree_outp) + ); + + + //////------mode5 log---------/////// + wire [`DATAWIDTH-1:0] mode5_outp_log; + reg [`DATAWIDTH-1:0] mode5_outp_log_reg; + mode5_ln mode5_ln(.inp(mode4_adder_tree_outp), .outp(mode5_outp_log), .clk(clk), .reset(reset), .mode5_stage3_run(mode5_stage3_run), .mode5_stage2_run(mode5_stage2_run), .mode5_stage1_run(mode5_stage1_run) ); + + always @(posedge clk) begin + if(reset) begin + mode5_outp_log_reg <= 0; + end else if(mode5_stage0_run) begin + mode5_outp_log_reg <= mode5_outp_log; + end + end + + //////------mode6 pre-sub---------/////// + wire [`DATAWIDTH-1:0] mode6_outp_presub0; + wire [`DATAWIDTH-1:0] mode6_outp_presub1; + wire [`DATAWIDTH-1:0] mode6_outp_presub2; + wire [`DATAWIDTH-1:0] mode6_outp_presub3; + reg [`DATAWIDTH-1:0] mode6_outp_presub0_reg_3; + reg [`DATAWIDTH-1:0] mode6_outp_presub1_reg_3; + reg [`DATAWIDTH-1:0] mode6_outp_presub2_reg_3; + reg [`DATAWIDTH-1:0] mode6_outp_presub3_reg_3; + reg [`DATAWIDTH-1:0] mode6_outp_presub0_reg_2; + reg [`DATAWIDTH-1:0] mode6_outp_presub1_reg_2; + reg [`DATAWIDTH-1:0] mode6_outp_presub2_reg_2; + reg [`DATAWIDTH-1:0] mode6_outp_presub3_reg_2; + reg [`DATAWIDTH-1:0] mode6_outp_presub0_reg_1; + reg [`DATAWIDTH-1:0] mode6_outp_presub1_reg_1; + reg [`DATAWIDTH-1:0] mode6_outp_presub2_reg_1; + reg [`DATAWIDTH-1:0] mode6_outp_presub3_reg_1; + reg [`DATAWIDTH-1:0] mode6_outp_presub0_reg_0; + reg [`DATAWIDTH-1:0] mode6_outp_presub1_reg_0; + reg [`DATAWIDTH-1:0] mode6_outp_presub2_reg_0; + reg [`DATAWIDTH-1:0] mode6_outp_presub3_reg_0; + + + + mode6_sub pre_sub( + .a_inp0(sub1_inp_reg[`DATAWIDTH*1-1:`DATAWIDTH*0]), + .a_inp1(sub1_inp_reg[`DATAWIDTH*2-1:`DATAWIDTH*1]), + .a_inp2(sub1_inp_reg[`DATAWIDTH*3-1:`DATAWIDTH*2]), + .a_inp3(sub1_inp_reg[`DATAWIDTH*4-1:`DATAWIDTH*3]), + .b_inp(max_outp), + .outp0(mode6_outp_presub0), + .outp1(mode6_outp_presub1), + .outp2(mode6_outp_presub2), + .outp3(mode6_outp_presub3) + ); + always @(posedge clk) begin + if (reset) begin + mode6_outp_presub0_reg_3 <= 0; + mode6_outp_presub1_reg_3 <= 0; + mode6_outp_presub2_reg_3 <= 0; + mode6_outp_presub3_reg_3 <= 0; + end else if (presub_run) begin + mode6_outp_presub0_reg_3 <= mode6_outp_presub0; + mode6_outp_presub1_reg_3 <= mode6_outp_presub1; + mode6_outp_presub2_reg_3 <= mode6_outp_presub2; + mode6_outp_presub3_reg_3 <= mode6_outp_presub3; + end + end + + always @(posedge clk) begin + if (reset) begin + mode6_outp_presub0_reg_2 <= 0; + mode6_outp_presub1_reg_2 <= 0; + mode6_outp_presub2_reg_2 <= 0; + mode6_outp_presub3_reg_2 <= 0; + end else if (presub_run_2) begin + mode6_outp_presub0_reg_2 <= mode6_outp_presub0_reg_3; + mode6_outp_presub1_reg_2 <= mode6_outp_presub1_reg_3; + mode6_outp_presub2_reg_2 <= mode6_outp_presub2_reg_3; + mode6_outp_presub3_reg_2 <= mode6_outp_presub3_reg_3; + end + end + + always @(posedge clk) begin + if (reset) begin + mode6_outp_presub0_reg_1 <= 0; + mode6_outp_presub1_reg_1 <= 0; + mode6_outp_presub2_reg_1 <= 0; + mode6_outp_presub3_reg_1 <= 0; + end else if (presub_run_1) begin + mode6_outp_presub0_reg_1 <= mode6_outp_presub0_reg_2; + mode6_outp_presub1_reg_1 <= mode6_outp_presub1_reg_2; + mode6_outp_presub2_reg_1 <= mode6_outp_presub2_reg_2; + mode6_outp_presub3_reg_1 <= mode6_outp_presub3_reg_2; + end + end + + always @(posedge clk) begin + if (reset) begin + mode6_outp_presub0_reg_0 <= 0; + mode6_outp_presub1_reg_0 <= 0; + mode6_outp_presub2_reg_0 <= 0; + mode6_outp_presub3_reg_0 <= 0; + end else if (presub_run_0) begin + mode6_outp_presub0_reg_0 <= mode6_outp_presub0_reg_1; + mode6_outp_presub1_reg_0 <= mode6_outp_presub1_reg_1; + mode6_outp_presub2_reg_0 <= mode6_outp_presub2_reg_1; + mode6_outp_presub3_reg_0 <= mode6_outp_presub3_reg_1; + end + end + + //////------mode6 logsub ---------/////// + wire [`DATAWIDTH-1:0] mode6_outp_logsub0; + wire [`DATAWIDTH-1:0] mode6_outp_logsub1; + wire [`DATAWIDTH-1:0] mode6_outp_logsub2; + wire [`DATAWIDTH-1:0] mode6_outp_logsub3; + reg [`DATAWIDTH-1:0] mode6_outp_logsub0_reg; + reg [`DATAWIDTH-1:0] mode6_outp_logsub1_reg; + reg [`DATAWIDTH-1:0] mode6_outp_logsub2_reg; + reg [`DATAWIDTH-1:0] mode6_outp_logsub3_reg; + + mode6_sub log_sub( + .a_inp0(mode6_outp_presub0_reg_0), + .a_inp1(mode6_outp_presub1_reg_0), + .a_inp2(mode6_outp_presub2_reg_0), + .a_inp3(mode6_outp_presub3_reg_0), + .b_inp(mode5_outp_log_reg), + .outp0(mode6_outp_logsub0), + .outp1(mode6_outp_logsub1), + .outp2(mode6_outp_logsub2), + .outp3(mode6_outp_logsub3) + ); + always @(posedge clk) begin + if (reset) begin + mode6_outp_logsub0_reg <= 0; + mode6_outp_logsub1_reg <= 0; + mode6_outp_logsub2_reg <= 0; + mode6_outp_logsub3_reg <= 0; + end else if (mode6_run) begin + mode6_outp_logsub0_reg <= mode6_outp_logsub0; + mode6_outp_logsub1_reg <= mode6_outp_logsub1; + mode6_outp_logsub2_reg <= mode6_outp_logsub2; + mode6_outp_logsub3_reg <= mode6_outp_logsub3; + end + end + + //////------mode7 exp---------/////// + wire [`DATAWIDTH-1:0] outp0_temp; + wire [`DATAWIDTH-1:0] outp1_temp; + wire [`DATAWIDTH-1:0] outp2_temp; + wire [`DATAWIDTH-1:0] outp3_temp; + reg [`DATAWIDTH-1:0] outp0; + reg [`DATAWIDTH-1:0] outp1; + reg [`DATAWIDTH-1:0] outp2; + reg [`DATAWIDTH-1:0] outp3; + + mode7_exp mode7_exp( + .inp0(mode6_outp_logsub0_reg), + .inp1(mode6_outp_logsub1_reg), + .inp2(mode6_outp_logsub2_reg), + .inp3(mode6_outp_logsub3_reg), + + .clk(clk), + .reset(reset), + .stage_run(mode7_stage_run), + .stage_run2(mode7_stage_run2), + + .outp0(outp0_temp), + .outp1(outp1_temp), + .outp2(outp2_temp), + .outp3(outp3_temp) + ); + always @(posedge clk) begin + if (reset) begin + outp0 <= 0; + outp1 <= 0; + outp2 <= 0; + outp3 <= 0; + end else if (mode7_run) begin + outp0 <= outp0_temp; + outp1 <= outp1_temp; + outp2 <= outp2_temp; + outp3 <= outp3_temp; + end + end + +endmodule + + + +module mode1_max_tree( + inp0, + inp1, + inp2, + inp3, + + mode1_stage2_run, + mode1_stage1_run, + mode1_stage0_run, + clk, + reset, + outp + +); + + input [`DATAWIDTH-1 : 0] inp0; + input [`DATAWIDTH-1 : 0] inp1; + input [`DATAWIDTH-1 : 0] inp2; + input [`DATAWIDTH-1 : 0] inp3; + + input mode1_stage2_run; + input mode1_stage1_run; + input mode1_stage0_run; + input clk; + input reset; + + output reg [`DATAWIDTH-1 : 0] outp; + + wire [`DATAWIDTH-1 : 0] cmp0_out_stage2; + wire [`DATAWIDTH-1 : 0] cmp1_out_stage2; + wire [`DATAWIDTH-1 : 0] cmp0_out_stage1; + wire [`DATAWIDTH-1 : 0] cmp0_out_stage0; + + reg [`DATAWIDTH-1 : 0] cmp0_out_stage2_reg; + reg [`DATAWIDTH-1 : 0] cmp1_out_stage2_reg; + reg [`DATAWIDTH-1 : 0] cmp0_out_stage1_reg; + + always @(posedge clk) begin + if (reset) begin + outp <= 0; + end + + else if(~reset && mode1_stage0_run) begin + outp <= cmp0_out_stage0; + end + + end + +wire cmp0_stage2_aeb; +wire cmp0_stage2_aneb; +wire cmp0_stage2_alb; +wire cmp0_stage2_aleb; +wire cmp0_stage2_agb; +wire cmp0_stage2_ageb; + +wire cmp1_stage2_aeb; +wire cmp1_stage2_aneb; +wire cmp1_stage2_alb; +wire cmp1_stage2_aleb; +wire cmp1_stage2_agb; +wire cmp1_stage2_ageb; + +wire cmp0_stage1_aeb; +wire cmp0_stage1_aneb; +wire cmp0_stage1_alb; +wire cmp0_stage1_aleb; +wire cmp0_stage1_agb; +wire cmp0_stage1_ageb; + +wire cmp0_stage0_aeb; +wire cmp0_stage0_aneb; +wire cmp0_stage0_alb; +wire cmp0_stage0_aleb; +wire cmp0_stage0_agb; +wire cmp0_stage0_ageb; + +comparator cmp0_stage2(.a(inp0), .b(inp1), .aeb(cmp0_stage2_aeb), .aneb(cmp0_stage2_aneb), .alb(cmp0_stage2_alb), .aleb(cmp0_stage2_aleb), .agb(cmp0_stage2_agb), .ageb(cmp0_stage2_ageb)); +assign cmp0_out_stage2 = (cmp0_stage2_ageb==1'b1) ? inp0 : inp1; + +comparator cmp1_stage2(.a(inp2), .b(inp3), .aeb(cmp1_stage2_aeb), .aneb(cmp1_stage2_aneb), .alb(cmp1_stage2_alb), .aleb(cmp1_stage2_aleb), .agb(cmp1_stage2_agb), .ageb(cmp1_stage2_ageb)); +assign cmp1_out_stage2 = (cmp1_stage2_ageb==1'b1) ? inp2 : inp3; + +always @(posedge clk) begin + if (reset) begin + cmp0_out_stage2_reg <= 16'b0; + cmp1_out_stage2_reg <= 16'b0; + end + else if (~reset && mode1_stage2_run) begin + cmp0_out_stage2_reg <= cmp0_out_stage2; + cmp1_out_stage2_reg <= cmp1_out_stage2; + end +end + +comparator cmp0_stage1(.a(cmp0_out_stage2_reg), .b(cmp1_out_stage2_reg), .aeb(cmp0_stage1_aeb), .aneb(cmp0_stage1_aneb), .alb(cmp0_stage1_alb), .aleb(cmp0_stage1_aleb), .agb(cmp0_stage1_agb), .ageb(cmp0_stage1_ageb)); +assign cmp0_out_stage1 = (cmp0_stage1_ageb==1'b1) ? cmp0_out_stage2_reg: cmp1_out_stage2_reg; + +always @(posedge clk) begin + if (reset) begin + cmp0_out_stage1_reg <= 16'b0; + end + else if (~reset && mode1_stage1_run) begin + cmp0_out_stage1_reg <= cmp0_out_stage1; + + end +end + +comparator cmp0_stage0(.a(outp), .b(cmp0_out_stage1_reg), .aeb(cmp0_stage0_aeb), .aneb(cmp0_stage0_aneb), .alb(cmp0_stage0_alb), .aleb(cmp0_stage0_aleb), .agb(cmp0_stage0_agb), .ageb(cmp0_stage0_ageb)); +assign cmp0_out_stage0 = (cmp0_stage0_ageb==1'b1) ? outp : cmp0_out_stage1_reg; + +endmodule + + +module mode2_sub( + a_inp0, + a_inp1, + a_inp2, + a_inp3, + outp0, + outp1, + outp2, + outp3, + b_inp +); + + input [`DATAWIDTH-1 : 0] a_inp0; + input [`DATAWIDTH-1 : 0] a_inp1; + input [`DATAWIDTH-1 : 0] a_inp2; + input [`DATAWIDTH-1 : 0] a_inp3; + output [`DATAWIDTH-1 : 0] outp0; + output [`DATAWIDTH-1 : 0] outp1; + output [`DATAWIDTH-1 : 0] outp2; + output [`DATAWIDTH-1 : 0] outp3; + input [`DATAWIDTH-1 : 0] b_inp; + + // 0 add, 1 sub + fixed_point_addsub sub0(.a(a_inp0), .b(b_inp), .operation(1'b1), .result(outp0)); + fixed_point_addsub sub1(.a(a_inp1), .b(b_inp), .operation(1'b1), .result(outp1)); + fixed_point_addsub sub2(.a(a_inp2), .b(b_inp), .operation(1'b1), .result(outp2)); + fixed_point_addsub sub3(.a(a_inp3), .b(b_inp), .operation(1'b1), .result(outp3)); + +endmodule + + +module mode3_exp( + inp0, + inp1, + inp2, + inp3, + + clk, + reset, + stage_run, + stage_run2, + + outp0, + outp1, + outp2, + outp3 +); + + input [`DATAWIDTH-1 : 0] inp0; + input [`DATAWIDTH-1 : 0] inp1; + input [`DATAWIDTH-1 : 0] inp2; + input [`DATAWIDTH-1 : 0] inp3; + + input clk; + input reset; + input stage_run; + input stage_run2; + + output [`DATAWIDTH-1 : 0] outp0; + output [`DATAWIDTH-1 : 0] outp1; + output [`DATAWIDTH-1 : 0] outp2; + output [`DATAWIDTH-1 : 0] outp3; + expunit exp0(.a(inp0), .z(outp0), .stage_run(stage_run), .stage_run2(stage_run2), .clk(clk), .reset(reset)); + expunit exp1(.a(inp1), .z(outp1), .stage_run(stage_run), .stage_run2(stage_run2), .clk(clk), .reset(reset)); + expunit exp2(.a(inp2), .z(outp2), .stage_run(stage_run), .stage_run2(stage_run2), .clk(clk), .reset(reset)); + expunit exp3(.a(inp3), .z(outp3), .stage_run(stage_run), .stage_run2(stage_run2), .clk(clk), .reset(reset)); +endmodule + + +module mode4_adder_tree( + inp0, + inp1, + inp2, + inp3, + mode4_stage0_run, + mode4_stage1_run, + mode4_stage2_run, + + clk, + reset, + outp +); + + input clk; + input reset; + input [`DATAWIDTH-1 : 0] inp0; + input [`DATAWIDTH-1 : 0] inp1; + input [`DATAWIDTH-1 : 0] inp2; + input [`DATAWIDTH-1 : 0] inp3; + output [`DATAWIDTH-1 : 0] outp; + input mode4_stage0_run; + input mode4_stage1_run; + input mode4_stage2_run; + + wire [`DATAWIDTH-1 : 0] add0_out_stage2; + reg [`DATAWIDTH-1 : 0] add0_out_stage2_reg; + wire [`DATAWIDTH-1 : 0] add1_out_stage2; + reg [`DATAWIDTH-1 : 0] add1_out_stage2_reg; + + wire [`DATAWIDTH-1 : 0] add0_out_stage1; + reg [`DATAWIDTH-1 : 0] add0_out_stage1_reg; + + wire [`DATAWIDTH-1 : 0] add0_out_stage0; + reg [`DATAWIDTH-1 : 0] outp; +/* + always @(posedge clk) begin + if (reset) begin + outp <= 0; + add0_out_stage2_reg <= 0; + add1_out_stage2_reg <= 0; + add0_out_stage1_reg <= 0; + end + + if(~reset && mode4_stage2_run) begin + add0_out_stage2_reg <= add0_out_stage2; + add1_out_stage2_reg <= add1_out_stage2; + end + + if(~reset && mode4_stage1_run) begin + add0_out_stage1_reg <= add0_out_stage1; + end + + if(~reset && mode4_stage0_run) begin + outp <= add0_out_stage0; + end + end +*/ +always @ (posedge clk) begin + if(~reset && mode4_stage2_run) begin + add0_out_stage2_reg <= add0_out_stage2; + add1_out_stage2_reg <= add1_out_stage2; + end + + else if (reset) begin + add0_out_stage2_reg <= 0; + add1_out_stage2_reg <= 0; + end +end + +always @ (posedge clk) begin + if(~reset && mode4_stage1_run) begin + add0_out_stage1_reg <= add0_out_stage1; + end + else if (reset) begin + add0_out_stage1_reg <= 0; + end +end + +always @ (posedge clk) begin + if(~reset && mode4_stage0_run) begin + outp <= add0_out_stage0; + end + else if (reset) begin + outp <= 0; + end +end + + // 0 add, 1 sub + fixed_point_addsub add0_stage2(.a(inp0), .b(inp1), .operation(1'b0), .result(add0_out_stage2)); + fixed_point_addsub add1_stage2(.a(inp2), .b(inp3), .operation(1'b0), .result(add1_out_stage2)); + fixed_point_addsub add0_stage1(.a(add0_out_stage2_reg), .b(add1_out_stage2_reg), .operation(1'b0), .result(add0_out_stage1)); + fixed_point_addsub add0_stage0(.a(outp), .b(add0_out_stage1_reg), .operation(1'b0), .result(add0_out_stage0)); + +endmodule + +module mode5_ln(inp, outp, clk, reset, mode5_stage3_run, mode5_stage2_run, mode5_stage1_run); + input [`DATAWIDTH-1 : 0] inp; + output [`DATAWIDTH-1 : 0] outp; + input clk,reset; + input mode5_stage3_run; + input mode5_stage2_run; + input mode5_stage1_run; + + logunit ln(.fpin(inp), .fpout(outp), .clk(clk), .reset(reset), .mode5_stage3_run(mode5_stage3_run), .mode5_stage2_run(mode5_stage2_run), .mode5_stage1_run(mode5_stage1_run)); +endmodule + +module mode6_sub( + a_inp0, + a_inp1, + a_inp2, + a_inp3, + b_inp, + outp0, + outp1, + outp2, + outp3 +); + + input [`DATAWIDTH-1 : 0] a_inp0; + input [`DATAWIDTH-1 : 0] a_inp1; + input [`DATAWIDTH-1 : 0] a_inp2; + input [`DATAWIDTH-1 : 0] a_inp3; + input [`DATAWIDTH-1 : 0] b_inp; + output [`DATAWIDTH-1 : 0] outp0; + output [`DATAWIDTH-1 : 0] outp1; + output [`DATAWIDTH-1 : 0] outp2; + output [`DATAWIDTH-1 : 0] outp3; + + // 0 add, 1 sub + fixed_point_addsub sub0(.a(a_inp0), .b(b_inp), .operation(1'b1), .result(outp0)); + fixed_point_addsub sub1(.a(a_inp1), .b(b_inp), .operation(1'b1), .result(outp1)); + fixed_point_addsub sub2(.a(a_inp2), .b(b_inp), .operation(1'b1), .result(outp2)); + fixed_point_addsub sub3(.a(a_inp3), .b(b_inp), .operation(1'b1), .result(outp3)); + +endmodule + + +module mode7_exp( + inp0, + inp1, + inp2, + inp3, + + clk, + reset, + stage_run, + stage_run2, + + outp0, + outp1, + outp2, + outp3 +); + + input [`DATAWIDTH-1 : 0] inp0; + input [`DATAWIDTH-1 : 0] inp1; + input [`DATAWIDTH-1 : 0] inp2; + input [`DATAWIDTH-1 : 0] inp3; + + input clk; + input reset; + input stage_run; + input stage_run2; + + output [`DATAWIDTH-1 : 0] outp0; + output [`DATAWIDTH-1 : 0] outp1; + output [`DATAWIDTH-1 : 0] outp2; + output [`DATAWIDTH-1 : 0] outp3; + expunit exp0(.a(inp0), .z(outp0), .stage_run(stage_run), .stage_run2(stage_run2), .clk(clk), .reset(reset)); + expunit exp1(.a(inp1), .z(outp1), .stage_run(stage_run), .stage_run2(stage_run2), .clk(clk), .reset(reset)); + expunit exp2(.a(inp2), .z(outp2), .stage_run(stage_run), .stage_run2(stage_run2), .clk(clk), .reset(reset)); + expunit exp3(.a(inp3), .z(outp3), .stage_run(stage_run), .stage_run2(stage_run2), .clk(clk), .reset(reset)); +endmodule + +//============================================================================ +// Fixed point add/sub module +//============================================================================ +module fixed_point_addsub( + a, + b, + operation, // 0 add, 1 sub + result + ); + + // Input ports + input [`DATAWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DATAWIDTH-1:0] b ; // Input B, a 32-bit floating point number + input operation ; // Operation select signal + + // Output ports + output reg [`DATAWIDTH-1:0] result ; // Result of the operation + + reg [`DATAWIDTH:0] result_t ; + wire [`DATAWIDTH-1:0] b_t ; + + assign b_t = ~b + 1'b1; + + always@(*) begin + if (operation == 1'b0) begin + result_t = a + b; + end + else begin + result_t = a + b_t; + end + end + + + always @ (*) begin + if (result_t[16] == 1'b1 && operation == 1'b0) begin + result = 16'h7000; + end + else if (result_t[16] == 1'b1 && operation == 1'b1) begin + result = 16'h8000; + end + else begin + result = result_t[15:0]; + end + end + // Pipeline Registers + //reg [79:0] pipe_1; // Pipeline register PreAlign->Align1 + + +endmodule + + +//============================================================================ +// Comparator module +//============================================================================ + + +module comparator( +a, +b, +aeb, +aneb, +alb, +aleb, +agb, +ageb +); + +input [15:0] a; +input [15:0] b; +output aeb; +output aneb; +output alb; +output aleb; +output agb; +output ageb; + + +reg lt; +reg eq; +reg gt; + +wire [15:0] a_t; +wire [15:0] b_t; + +assign a_t = (~a[15:0])+1'b1; +assign b_t = (~b[15:0])+1'b1; + +always @(*) begin + if (a[15] == 1'b0 && b[15] == 1'b1) begin + if (a != b) begin + eq = 1'b0; + lt = 1'b0; + gt = 1'b1; + end + else begin + eq = 1'b1; + lt = 1'b0; + gt = 1'b0; + end + end + else if (a[15] == 1'b1 && b[15] == 1'b0) begin + if (a != b) begin + lt = 1'b1; + gt = 1'b0; + eq = 1'b0; + end + else begin + lt = 1'b0; + gt = 1'b0; + eq = 1'b1; + end + end + else if (a[15] == 1'b0 && b[15] == 1'b0) begin + if (a > b) begin + lt = 1'b0; + gt = 1'b1; + eq = 1'b0; + end + else if (a < b) begin + lt = 1'b1; + gt = 1'b0; + eq = 1'b0; + end + else begin + lt = 1'b0; + gt = 1'b0; + eq = 1'b1; + end + end + else begin + if (a_t > b_t) begin + lt = 1'b1; + gt = 1'b0; + eq = 1'b0; + end + else if (a_t < b_t) begin + lt = 1'b0; + gt = 1'b1; + eq = 1'b0; + end + else begin + lt = 1'b0; + gt = 1'b0; + eq = 1'b1; + end + end +end + + +//Result flags +assign aeb = eq; +assign aneb = ~eq; +assign alb = lt; +assign aleb = lt | eq; +assign agb = gt; +assign ageb = gt | eq; + +endmodule + + + +////////////////////////////////////////////////////// +// Log unit +// Author: Pragnesh Patel +////////////////////////////////////////////////////// + + +module logunit (fpin, fpout, clk, reset, mode5_stage3_run, mode5_stage2_run, mode5_stage1_run); + + input [15:0] fpin; + output [15:0] fpout; + input clk,reset; + + input mode5_stage3_run; + input mode5_stage2_run; + input mode5_stage1_run; + // input mode5_stage0_run; + + wire [15: 0] fxout1; + wire [15: 0] fxout2; + wire [15:0] fpin_f; + wire [15:0] fpout_f; + reg [15:0] fpin_f_reg; + reg [15:0] fpout_f_reg; + reg [15: 0] fxout1_reg; + reg [15: 0] fxout2_reg; + //reg [15: 0] pipe1; + //reg [15: 0] pipe2; + + int_to_float_fp16 int_float (.input_a(fpin),.output_z(fpin_f)); + FPLUT1 lut1 (.addr(fpin_f_reg[14:10]),.log(fxout1)); + FP8LUT2 lut2 (.addr(fpin_f_reg[9:2]),.log(fxout2)); +`ifdef complex_dsp +addition_fp_clk_16 u_add(.clk(clk), .a(fxout1_reg), .b(fxout2_reg), .out(fpout_f)); +`else +FPAddSub u_FPAddSub (.clk(clk), .rst(1'b0), .a(fxout1_reg), .b(fxout2_reg), .operation(1'b0), .result(fpout_f), .flags()); +`endif + + float_to_int_fp16 float_int (.input_a(fpout_f_reg),.output_z(fpout)); + + always @(posedge clk) begin + /*if (reset) begin + fpin_f_reg <= 16'b0; + end */ + //if (~reset && mode5_stage2_run) begin + if (mode5_stage3_run) begin + fpin_f_reg <= fpin_f; + end + end + + always @(posedge clk) begin + /*if (reset) begin + fpin_f_reg <= 16'b0; + end */ + //if (~reset && mode5_stage2_run) begin + if (mode5_stage2_run) begin + fxout2_reg <= fxout2; + fxout1_reg <= fxout1; + end + end + + always @(posedge clk) begin + /*if (reset) begin + fpout_f_reg <= 16'b0; + end */ + //if (~reset && mode5_stage1_run) begin + if (mode5_stage1_run) begin + fpout_f_reg <= fpout_f; + end + end +endmodule + +module float_to_int_fp16( + input_a, + output_z); + + + input [15:0] input_a; + output [15:0] output_z; + + + wire [27:0] z; + wire [5:0] a_e, sub_a_e; + wire a_s; + wire [15:0] a_m; + wire [27:0] a_m_shift; + + align_t dut_align (input_a,a_m,a_e,a_s); + sub_t dut_sub (a_e,sub_a_e); + am_shift_t dut_am_shift (a_e,sub_a_e,a_m,a_m_shift); + two_comp_t dut_two_comp (a_m_shift,a_s,z); + final_out_t dut_final_out (z, a_e, output_z); + +endmodule + +module align_t ( + input [15:0] input_a, + output [15:0] a_m, + output [5:0] a_e, + output a_s); + + wire [15:0] a; + + assign a = input_a; + assign a_m[15:5] = {1'b1, a[9 : 0]}; + assign a_m[4:0] = 5'b0; + assign a_e = a[14 : 10] - 4'd15; + assign a_s = a[15]; + +endmodule + +module sub_t ( + input [5:0] a_e, + output [5:0] sub_a_e); + +assign sub_a_e = 4'd15 - a_e; + +endmodule + +module am_shift_t ( + input [5:0] a_e, + input [5:0] sub_a_e, + input [15:0] a_m, + output reg [27:0] a_m_shift); + +always@(a_e or sub_a_e or a_m) begin + if (a_e <= 15 && a_e >= 0 ) begin + a_m_shift = {a_m,12'b0} >> sub_a_e; + end + else begin + a_m_shift = 24'h0; + end + end + +endmodule + +module two_comp_t ( + input [27:0] a_m_shift, + input a_s, + output [27:0] z); + +assign z = a_s ? -a_m_shift : a_m_shift; // 2's complement + +endmodule + +module final_out_t ( + input [27:0] z, + input [5:0] a_e, + output [15:0] output_z); + + reg [27:0] output_z_temp; + +always@(a_e or z) begin + if (a_e[5] == 1'b1 && a_e[4:0] == 5'd15) begin + output_z_temp = 27'b0; + end + else if (a_e[5] == 0 && a_e[4:0] > 5'd15) begin + output_z_temp = 27'hFFFF; + end + else begin + output_z_temp = z << 12; + end + end + assign output_z = output_z_temp[27:12]; +endmodule + +module int_to_float_fp16( + input_a, + output_z); + + + input [15:0] input_a; + output [15:0] output_z; + + + wire [15:0] value; + wire z_s; + wire [4:0] tmp_cnt; + wire [4:0] sub_a_e; + wire [4:0] sub_z_e; + wire [15:0] a_m_shift; + wire [10:0] z_m_final; + wire [4:0] z_e_final; + //wire [31:0] z; + + align dut_align (input_a,value,z_s); + lzc dut_lzc (value,tmp_cnt); + sub dut_sub (tmp_cnt,sub_a_e); + sub2 dut_sub2 (sub_a_e,sub_z_e); + am_shift dut_am_shift (value,sub_a_e,a_m_shift); + exception dut_exception (a_m_shift,sub_z_e,z_m_final,z_e_final); + final_out dut_final_out (input_a,z_m_final,z_e_final,z_s,output_z); + + +endmodule + +module align ( + input [15:0] a, + output [15:0] value, +output z_s); + + + assign value = a[15] ? -a : a; + assign z_s = a[15]; + +endmodule + +/*module align2 ( +input [31:0] value, +output [31:0] z_m, +//output [7:0] z_r, +//output [7:0] z_e); + + + //z_e <= 8'd31; + z_m <= value[31:0]; + //z_r <= value[7:0]; + +endmodule*/ + +module lzc ( + input [15:0] z_m, + output reg [4:0] tmp_cnt_final); + + wire [15:0] Sj_int; + //wire [15:0] val32; +wire [7:0] val8; +wire [3:0] val4; + wire [4:0] tmp_cnt; + +assign Sj_int = z_m; + +assign tmp_cnt[4] = 1'b0; +assign tmp_cnt[3] = (Sj_int[15:8] == 8'b0); +assign val8 = tmp_cnt[3] ? Sj_int[7:0] : Sj_int[15:8]; +assign tmp_cnt[2] = (val8[7:4] == 4'b0); +assign val4 = tmp_cnt[2] ? val8[3:0] : val8[7:4]; +assign tmp_cnt[1] = (val4[3:2] == 2'b0); +assign tmp_cnt[0] = tmp_cnt[1] ? ~val4[1] : ~val4[3]; + +always@(Sj_int or tmp_cnt) +begin + if (Sj_int[15:0] == 16'b0) + tmp_cnt_final = 5'd16; +else + begin + tmp_cnt_final = tmp_cnt; +end +end +endmodule + +module sub ( + input [4:0] a_e, + output [4:0] sub_a_e); + +assign sub_a_e = a_e; + +endmodule + +module sub2 ( + input [4:0] a_e, + output [4:0] sub_a_e); + +assign sub_a_e = 5'd15 - a_e; + +endmodule + +module am_shift ( + input [15:0] a_m, + input [4:0] tmp_cnt, + output [15:0] a_m_shift); + +assign a_m_shift = a_m << tmp_cnt; +endmodule + +module exception ( + input [15:0] a_m_shift, + input [4:0] z_e, + output reg [10:0] z_m_final, + output reg [4:0] z_e_final +); + +wire guard; +wire round_bit; +wire sticky; + wire [10:0] z_m; + + assign guard = a_m_shift[4]; + assign round_bit = a_m_shift[3]; + assign sticky = a_m_shift[2:0] != 0; + + assign z_m = a_m_shift[15:5]; + +always@(guard or round_bit or sticky or z_m or z_e) +begin +if (guard && (round_bit || sticky || z_m[0])) begin + z_m_final = z_m + 1'b1; + if (z_m == 11'b11111111111) begin + z_e_final = z_e + 1'b1; + end + else z_e_final = z_e; + end +else begin + z_m_final = z_m; + z_e_final = z_e; +end +end +endmodule + +module final_out ( + input [15:0] a, + input [10:0] z_m, + input [4:0] z_e, + input z_s, + output reg [15:0] output_z); + + always@(a or z_m or z_e or z_s) begin + if (a == 16'b0) begin + output_z = 16'b0; + end + else begin + output_z[9:0] = z_m[9:0]; + output_z[14:10] = z_e + 2'd3; + output_z[15] = z_s; + end + end + +endmodule + +module FPLUT1(addr, log); + input [4:0] addr; + output reg [15:0] log; + + always @(addr) begin + case (addr) + 5'b0 : log = 16'b1111110000000000; + 5'b1 : log = 16'b1100100011011010; + 5'b10 : log = 16'b1100100010000001; + 5'b11 : log = 16'b1100100000101001; + 5'b100 : log = 16'b1100011110100000; + 5'b101 : log = 16'b1100011011101110; + 5'b110 : log = 16'b1100011000111101; + 5'b111 : log = 16'b1100010110001100; + 5'b1000 : log = 16'b1100010011011010; + 5'b1001 : log = 16'b1100010000101001; + 5'b1010 : log = 16'b1100001011101110; + 5'b1011 : log = 16'b1100000110001100; + 5'b1100 : log = 16'b1100000000101001; + 5'b1101 : log = 16'b1011110110001100; + 5'b1110 : log = 16'b1011100110001100; + 5'b1111 : log = 16'b0000000000000000; + 5'b10000 : log = 16'b0011100110001100; + 5'b10001 : log = 16'b0011110110001100; + 5'b10010 : log = 16'b0100000000101001; + 5'b10011 : log = 16'b0100000110001100; + 5'b10100 : log = 16'b0100001011101110; + 5'b10101 : log = 16'b0100010000101001; + 5'b10110 : log = 16'b0100010011011010; + 5'b10111 : log = 16'b0100010110001100; + 5'b11000 : log = 16'b0100011000111101; + 5'b11001 : log = 16'b0100011011101110; + 5'b11010 : log = 16'b0100011110100000; + 5'b11011 : log = 16'b0100100000101001; + 5'b11100 : log = 16'b0100100010000001; + 5'b11101 : log = 16'b0100100011011010; + 5'b11110 : log = 16'b0100100100110011; + 5'b11111 : log = 16'b0111110000000000; + endcase + end +endmodule + +module FP8LUT2(addr, log); + input [7:0] addr; + output reg [15:0] log; + + always @(addr) begin + case (addr) + 8'b0 : log = 16'b0000000000000000; + 8'b1 : log = 16'b0001101111111100; + 8'b10 : log = 16'b0001111111111000; + 8'b11 : log = 16'b0010000111110111; + 8'b100 : log = 16'b0010001111110000; + 8'b101 : log = 16'b0010010011110100; + 8'b110 : log = 16'b0010010111101110; + 8'b111 : log = 16'b0010011011101000; + 8'b1000 : log = 16'b0010011111100001; + 8'b1001 : log = 16'b0010100001101100; + 8'b1010 : log = 16'b0010100011101000; + 8'b1011 : log = 16'b0010100101100011; + 8'b1100 : log = 16'b0010100111011101; + 8'b1101 : log = 16'b0010101001010111; + 8'b1110 : log = 16'b0010101011010001; + 8'b1111 : log = 16'b0010101101001010; + 8'b10000 : log = 16'b0010101111000011; + 8'b10001 : log = 16'b0010110000011101; + 8'b10010 : log = 16'b0010110001011001; + 8'b10011 : log = 16'b0010110010010101; + 8'b10100 : log = 16'b0010110011010000; + 8'b10101 : log = 16'b0010110100001100; + 8'b10110 : log = 16'b0010110101000111; + 8'b10111 : log = 16'b0010110110000010; + 8'b11000 : log = 16'b0010110110111100; + 8'b11001 : log = 16'b0010110111110111; + 8'b11010 : log = 16'b0010111000110001; + 8'b11011 : log = 16'b0010111001101011; + 8'b11100 : log = 16'b0010111010100101; + 8'b11101 : log = 16'b0010111011011110; + 8'b11110 : log = 16'b0010111100011000; + 8'b11111 : log = 16'b0010111101010001; + 8'b100000 : log = 16'b0010111110001010; + 8'b100001 : log = 16'b0010111111000011; + 8'b100010 : log = 16'b0010111111111011; + 8'b100011 : log = 16'b0011000000011010; + 8'b100100 : log = 16'b0011000000110110; + 8'b100101 : log = 16'b0011000001010010; + 8'b100110 : log = 16'b0011000001101110; + 8'b100111 : log = 16'b0011000010001010; + 8'b101000 : log = 16'b0011000010100101; + 8'b101001 : log = 16'b0011000011000001; + 8'b101010 : log = 16'b0011000011011100; + 8'b101011 : log = 16'b0011000011111000; + 8'b101100 : log = 16'b0011000100010011; + 8'b101101 : log = 16'b0011000100101111; + 8'b101110 : log = 16'b0011000101001010; + 8'b101111 : log = 16'b0011000101100101; + 8'b110000 : log = 16'b0011000110000000; + 8'b110001 : log = 16'b0011000110011011; + 8'b110010 : log = 16'b0011000110110110; + 8'b110011 : log = 16'b0011000111010000; + 8'b110100 : log = 16'b0011000111101011; + 8'b110101 : log = 16'b0011001000000101; + 8'b110110 : log = 16'b0011001000100000; + 8'b110111 : log = 16'b0011001000111010; + 8'b111000 : log = 16'b0011001001010101; + 8'b111001 : log = 16'b0011001001101111; + 8'b111010 : log = 16'b0011001010001001; + 8'b111011 : log = 16'b0011001010100011; + 8'b111100 : log = 16'b0011001010111101; + 8'b111101 : log = 16'b0011001011010111; + 8'b111110 : log = 16'b0011001011110001; + 8'b111111 : log = 16'b0011001100001010; + 8'b1000000 : log = 16'b0011001100100100; + 8'b1000001 : log = 16'b0011001100111110; + 8'b1000010 : log = 16'b0011001101010111; + 8'b1000011 : log = 16'b0011001101110000; + 8'b1000100 : log = 16'b0011001110001010; + 8'b1000101 : log = 16'b0011001110100011; + 8'b1000110 : log = 16'b0011001110111100; + 8'b1000111 : log = 16'b0011001111010101; + 8'b1001000 : log = 16'b0011001111101110; + 8'b1001001 : log = 16'b0011010000000100; + 8'b1001010 : log = 16'b0011010000010000; + 8'b1001011 : log = 16'b0011010000011100; + 8'b1001100 : log = 16'b0011010000101001; + 8'b1001101 : log = 16'b0011010000110101; + 8'b1001110 : log = 16'b0011010001000001; + 8'b1001111 : log = 16'b0011010001001110; + 8'b1010000 : log = 16'b0011010001011010; + 8'b1010001 : log = 16'b0011010001100110; + 8'b1010010 : log = 16'b0011010001110010; + 8'b1010011 : log = 16'b0011010001111110; + 8'b1010100 : log = 16'b0011010010001010; + 8'b1010101 : log = 16'b0011010010010110; + 8'b1010110 : log = 16'b0011010010100010; + 8'b1010111 : log = 16'b0011010010101110; + 8'b1011000 : log = 16'b0011010010111010; + 8'b1011001 : log = 16'b0011010011000110; + 8'b1011010 : log = 16'b0011010011010010; + 8'b1011011 : log = 16'b0011010011011110; + 8'b1011100 : log = 16'b0011010011101010; + 8'b1011101 : log = 16'b0011010011110101; + 8'b1011110 : log = 16'b0011010100000001; + 8'b1011111 : log = 16'b0011010100001101; + 8'b1100000 : log = 16'b0011010100011000; + 8'b1100001 : log = 16'b0011010100100100; + 8'b1100010 : log = 16'b0011010100110000; + 8'b1100011 : log = 16'b0011010100111011; + 8'b1100100 : log = 16'b0011010101000111; + 8'b1100101 : log = 16'b0011010101010010; + 8'b1100110 : log = 16'b0011010101011110; + 8'b1100111 : log = 16'b0011010101101001; + 8'b1101000 : log = 16'b0011010101110100; + 8'b1101001 : log = 16'b0011010110000000; + 8'b1101010 : log = 16'b0011010110001011; + 8'b1101011 : log = 16'b0011010110010110; + 8'b1101100 : log = 16'b0011010110100010; + 8'b1101101 : log = 16'b0011010110101101; + 8'b1101110 : log = 16'b0011010110111000; + 8'b1101111 : log = 16'b0011010111000011; + 8'b1110000 : log = 16'b0011010111001110; + 8'b1110001 : log = 16'b0011010111011010; + 8'b1110010 : log = 16'b0011010111100101; + 8'b1110011 : log = 16'b0011010111110000; + 8'b1110100 : log = 16'b0011010111111011; + 8'b1110101 : log = 16'b0011011000000110; + 8'b1110110 : log = 16'b0011011000010001; + 8'b1110111 : log = 16'b0011011000011100; + 8'b1111000 : log = 16'b0011011000100111; + 8'b1111001 : log = 16'b0011011000110001; + 8'b1111010 : log = 16'b0011011000111100; + 8'b1111011 : log = 16'b0011011001000111; + 8'b1111100 : log = 16'b0011011001010010; + 8'b1111101 : log = 16'b0011011001011101; + 8'b1111110 : log = 16'b0011011001100111; + 8'b1111111 : log = 16'b0011011001110010; + 8'b10000000 : log = 16'b0011011001111101; + 8'b10000001 : log = 16'b0011011010000111; + 8'b10000010 : log = 16'b0011011010010010; + 8'b10000011 : log = 16'b0011011010011101; + 8'b10000100 : log = 16'b0011011010100111; + 8'b10000101 : log = 16'b0011011010110010; + 8'b10000110 : log = 16'b0011011010111100; + 8'b10000111 : log = 16'b0011011011000111; + 8'b10001000 : log = 16'b0011011011010001; + 8'b10001001 : log = 16'b0011011011011100; + 8'b10001010 : log = 16'b0011011011100110; + 8'b10001011 : log = 16'b0011011011110000; + 8'b10001100 : log = 16'b0011011011111011; + 8'b10001101 : log = 16'b0011011100000101; + 8'b10001110 : log = 16'b0011011100001111; + 8'b10001111 : log = 16'b0011011100011010; + 8'b10010000 : log = 16'b0011011100100100; + 8'b10010001 : log = 16'b0011011100101110; + 8'b10010010 : log = 16'b0011011100111000; + 8'b10010011 : log = 16'b0011011101000011; + 8'b10010100 : log = 16'b0011011101001101; + 8'b10010101 : log = 16'b0011011101010111; + 8'b10010110 : log = 16'b0011011101100001; + 8'b10010111 : log = 16'b0011011101101011; + 8'b10011000 : log = 16'b0011011101110101; + 8'b10011001 : log = 16'b0011011101111111; + 8'b10011010 : log = 16'b0011011110001001; + 8'b10011011 : log = 16'b0011011110010011; + 8'b10011100 : log = 16'b0011011110011101; + 8'b10011101 : log = 16'b0011011110100111; + 8'b10011110 : log = 16'b0011011110110001; + 8'b10011111 : log = 16'b0011011110111011; + 8'b10100000 : log = 16'b0011011111000101; + 8'b10100001 : log = 16'b0011011111001110; + 8'b10100010 : log = 16'b0011011111011000; + 8'b10100011 : log = 16'b0011011111100010; + 8'b10100100 : log = 16'b0011011111101100; + 8'b10100101 : log = 16'b0011011111110110; + 8'b10100110 : log = 16'b0011011111111111; + 8'b10100111 : log = 16'b0011100000000100; + 8'b10101000 : log = 16'b0011100000001001; + 8'b10101001 : log = 16'b0011100000001110; + 8'b10101010 : log = 16'b0011100000010011; + 8'b10101011 : log = 16'b0011100000011000; + 8'b10101100 : log = 16'b0011100000011101; + 8'b10101101 : log = 16'b0011100000100001; + 8'b10101110 : log = 16'b0011100000100110; + 8'b10101111 : log = 16'b0011100000101011; + 8'b10110000 : log = 16'b0011100000110000; + 8'b10110001 : log = 16'b0011100000110100; + 8'b10110010 : log = 16'b0011100000111001; + 8'b10110011 : log = 16'b0011100000111110; + 8'b10110100 : log = 16'b0011100001000010; + 8'b10110101 : log = 16'b0011100001000111; + 8'b10110110 : log = 16'b0011100001001100; + 8'b10110111 : log = 16'b0011100001010001; + 8'b10111000 : log = 16'b0011100001010101; + 8'b10111001 : log = 16'b0011100001011010; + 8'b10111010 : log = 16'b0011100001011110; + 8'b10111011 : log = 16'b0011100001100011; + 8'b10111100 : log = 16'b0011100001101000; + 8'b10111101 : log = 16'b0011100001101100; + 8'b10111110 : log = 16'b0011100001110001; + 8'b10111111 : log = 16'b0011100001110110; + 8'b11000000 : log = 16'b0011100001111010; + 8'b11000001 : log = 16'b0011100001111111; + 8'b11000010 : log = 16'b0011100010000011; + 8'b11000011 : log = 16'b0011100010001000; + 8'b11000100 : log = 16'b0011100010001100; + 8'b11000101 : log = 16'b0011100010010001; + 8'b11000110 : log = 16'b0011100010010101; + 8'b11000111 : log = 16'b0011100010011010; + 8'b11001000 : log = 16'b0011100010011110; + 8'b11001001 : log = 16'b0011100010100011; + 8'b11001010 : log = 16'b0011100010100111; + 8'b11001011 : log = 16'b0011100010101100; + 8'b11001100 : log = 16'b0011100010110000; + 8'b11001101 : log = 16'b0011100010110101; + 8'b11001110 : log = 16'b0011100010111001; + 8'b11001111 : log = 16'b0011100010111110; + 8'b11010000 : log = 16'b0011100011000010; + 8'b11010001 : log = 16'b0011100011000110; + 8'b11010010 : log = 16'b0011100011001011; + 8'b11010011 : log = 16'b0011100011001111; + 8'b11010100 : log = 16'b0011100011010100; + 8'b11010101 : log = 16'b0011100011011000; + 8'b11010110 : log = 16'b0011100011011100; + 8'b11010111 : log = 16'b0011100011100001; + 8'b11011000 : log = 16'b0011100011100101; + 8'b11011001 : log = 16'b0011100011101001; + 8'b11011010 : log = 16'b0011100011101110; + 8'b11011011 : log = 16'b0011100011110010; + 8'b11011100 : log = 16'b0011100011110110; + 8'b11011101 : log = 16'b0011100011111011; + 8'b11011110 : log = 16'b0011100011111111; + 8'b11011111 : log = 16'b0011100100000011; + 8'b11100000 : log = 16'b0011100100000111; + 8'b11100001 : log = 16'b0011100100001100; + 8'b11100010 : log = 16'b0011100100010000; + 8'b11100011 : log = 16'b0011100100010100; + 8'b11100100 : log = 16'b0011100100011000; + 8'b11100101 : log = 16'b0011100100011101; + 8'b11100110 : log = 16'b0011100100100001; + 8'b11100111 : log = 16'b0011100100100101; + 8'b11101000 : log = 16'b0011100100101001; + 8'b11101001 : log = 16'b0011100100101101; + 8'b11101010 : log = 16'b0011100100110010; + 8'b11101011 : log = 16'b0011100100110110; + 8'b11101100 : log = 16'b0011100100111010; + 8'b11101101 : log = 16'b0011100100111110; + 8'b11101110 : log = 16'b0011100101000010; + 8'b11101111 : log = 16'b0011100101000110; + 8'b11110000 : log = 16'b0011100101001011; + 8'b11110001 : log = 16'b0011100101001111; + 8'b11110010 : log = 16'b0011100101010011; + 8'b11110011 : log = 16'b0011100101010111; + 8'b11110100 : log = 16'b0011100101011011; + 8'b11110101 : log = 16'b0011100101011111; + 8'b11110110 : log = 16'b0011100101100011; + 8'b11110111 : log = 16'b0011100101100111; + 8'b11111000 : log = 16'b0011100101101011; + 8'b11111001 : log = 16'b0011100101101111; + 8'b11111010 : log = 16'b0011100101110011; + 8'b11111011 : log = 16'b0011100101110111; + 8'b11111100 : log = 16'b0011100101111100; + 8'b11111101 : log = 16'b0011100110000000; + 8'b11111110 : log = 16'b0011100110000100; + 8'b11111111 : log = 16'b0011100110001000; + endcase + end +endmodule + + +////////////////////////////////////////////////////// +// Exponential unit +// Author: Pragnesh Patel +////////////////////////////////////////////////////// + +module expunit (a, z, stage_run, stage_run2, clk, reset); + + input [15:0] a; + input stage_run; + input stage_run2; + input clk; + input reset; + output reg [15:0] z; + + reg [31:0] LUTout_reg; + reg [31:0] LUTout_reg2; + reg [15:0] a_reg; + reg [15:0] a_reg2; + reg [15:0] a_comp_reg; + reg [31:0] Mult_out_reg; + wire [31:0] LUTout; + wire [31:0] Mult_out; + wire [15:0] a_comp; + wire [15:0] z_out; + + + always @(posedge clk) begin + if(reset) begin + LUTout_reg2 <= 0; + a_reg2 <= 0; + a_comp_reg <= 0; + end + else if(stage_run2) begin + LUTout_reg2 <= LUTout; + a_reg2 <= a; + a_comp_reg <= a_comp; + end + end + + always @(posedge clk) begin + if(reset) begin + Mult_out_reg <= 0; + LUTout_reg <= 0; + a_reg <= 0; + end + else if(stage_run) begin + Mult_out_reg <= Mult_out; + LUTout_reg <= LUTout_reg2; + a_reg <= a_reg2; + end + end + + assign a_comp = ~a + 1'b1; + ExpLUT lut(.clk(clk), .addr(a_comp[14:8]), .exp(LUTout)); + assign Mult_out = ~(a_comp_reg*LUTout_reg2[31:16])+1; + assign z_out = Mult_out_reg[27:12] + LUTout_reg[15:0]; + + always@(z_out or a_reg) begin + if (a_reg[15:12] == 4'b1000) begin + z = 12'b1; + end + else + z = z_out; + end + +endmodule + +module ExpLUT(clk, addr, exp); + input clk; + input [6:0] addr; + output reg [31:0] exp; + + always @(posedge clk) begin + case (addr) + 7'b0000000 : exp <= 32'b00001111100000100001000000000000; + 7'b0000001 : exp <= 32'b00001110100100100000111111110000; + 7'b0000010 : exp <= 32'b00001101101100000000111111010100; + 7'b0000011 : exp <= 32'b00001100110110110000111110101100; + 7'b0000100 : exp <= 32'b00001100000101000000111101111011; + 7'b0000101 : exp <= 32'b00001011010110000000111101000000; + 7'b0000110 : exp <= 32'b00001010101010000000111011111110; + 7'b0000111 : exp <= 32'b00001010000000110000111010110110; + 7'b0001000 : exp <= 32'b00001001011010000000111001101000; + 7'b0001001 : exp <= 32'b00001000110101100000111000010110; + 7'b0001010 : exp <= 32'b00001000010011010000110111000000; + 7'b0001011 : exp <= 32'b00000111110011000000110101101000; + 7'b0001100 : exp <= 32'b00000111010100110000110100001101; + 7'b0001101 : exp <= 32'b00000110111000010000110010110001; + 7'b0001110 : exp <= 32'b00000110011101110000110001010011; + 7'b0001111 : exp <= 32'b00000110000100100000101111110101; + 7'b0010000 : exp <= 32'b00000101101101000000101110010111; + 7'b0010001 : exp <= 32'b00000101010111000000101100111001; + 7'b0010010 : exp <= 32'b00000101000010010000101011011011; + 7'b0010011 : exp <= 32'b00000100101110100000101001111111; + 7'b0010100 : exp <= 32'b00000100011100010000101000100011; + 7'b0010101 : exp <= 32'b00000100001011000000100111001001; + 7'b0010110 : exp <= 32'b00000011111010110000100101110000; + 7'b0010111 : exp <= 32'b00000011101011110000100100011000; + 7'b0011000 : exp <= 32'b00000011011101010000100011000010; + 7'b0011001 : exp <= 32'b00000011010000000000100001101111; + 7'b0011010 : exp <= 32'b00000011000011010000100000011101; + 7'b0011011 : exp <= 32'b00000010110111100000011111001101; + 7'b0011100 : exp <= 32'b00000010101100010000011101111111; + 7'b0011101 : exp <= 32'b00000010100010000000011100110011; + 7'b0011110 : exp <= 32'b00000010011000000000011011101001; + 7'b0011111 : exp <= 32'b00000010001111000000011010100010; + 7'b0100000 : exp <= 32'b00000010000110010000011001011101; + 7'b0100001 : exp <= 32'b00000001111110000000011000011001; + 7'b0100010 : exp <= 32'b00000001110110100000010111011000; + 7'b0100011 : exp <= 32'b00000001101111010000010110011010; + 7'b0100100 : exp <= 32'b00000001101000100000010101011101; + 7'b0100101 : exp <= 32'b00000001100010010000010100100010; + 7'b0100110 : exp <= 32'b00000001011100010000010011101010; + 7'b0100111 : exp <= 32'b00000001010110100000010010110011; + 7'b0101000 : exp <= 32'b00000001010001010000010001111111; + 7'b0101001 : exp <= 32'b00000001001100100000010001001100; + 7'b0101010 : exp <= 32'b00000001000111110000010000011011; + 7'b0101011 : exp <= 32'b00000001000011100000001111101100; + 7'b0101100 : exp <= 32'b00000000111111010000001110111111; + 7'b0101101 : exp <= 32'b00000000111011100000001110010100; + 7'b0101110 : exp <= 32'b00000000111000000000001101101011; + 7'b0101111 : exp <= 32'b00000000110100100000001101000011; + 7'b0110000 : exp <= 32'b00000000110001010000001100011100; + 7'b0110001 : exp <= 32'b00000000101110010000001011111000; + 7'b0110010 : exp <= 32'b00000000101011100000001011010101; + 7'b0110011 : exp <= 32'b00000000101000110000001010110011; + 7'b0110100 : exp <= 32'b00000000100110010000001010010011; + 7'b0110101 : exp <= 32'b00000000100100000000001001110100; + 7'b0110110 : exp <= 32'b00000000100001110000001001010110; + 7'b0110111 : exp <= 32'b00000000011111110000001000111010; + 7'b0111000 : exp <= 32'b00000000011101110000001000011111; + 7'b0111001 : exp <= 32'b00000000011100000000001000000101; + 7'b0111010 : exp <= 32'b00000000011010010000000111101100; + 7'b0111011 : exp <= 32'b00000000011000110000000111010101; + 7'b0111100 : exp <= 32'b00000000010111010000000110111110; + 7'b0111101 : exp <= 32'b00000000010101110000000110101000; + 7'b0111110 : exp <= 32'b00000000010100100000000110010100; + 7'b0111111 : exp <= 32'b00000000010011010000000110000000; + 7'b1000000 : exp <= 32'b00000000010010000000000101101101; + 7'b1000001 : exp <= 32'b00000000010001000000000101011100; + 7'b1000010 : exp <= 32'b00000000010000000000000101001010; + 7'b1000011 : exp <= 32'b00000000001111000000000100111010; + 7'b1000100 : exp <= 32'b00000000001110000000000100101011; + 7'b1000101 : exp <= 32'b00000000001101010000000100011100; + 7'b1000110 : exp <= 32'b00000000001100010000000100001110; + 7'b1000111 : exp <= 32'b00000000001011100000000100000000; + 7'b1001000 : exp <= 32'b00000000001011000000000011110011; + 7'b1001001 : exp <= 32'b00000000001010010000000011100111; + 7'b1001010 : exp <= 32'b00000000001001100000000011011100; + 7'b1001011 : exp <= 32'b00000000001001000000000011010001; + 7'b1001100 : exp <= 32'b00000000001000100000000011000110; + 7'b1001101 : exp <= 32'b00000000001000000000000010111100; + 7'b1001110 : exp <= 32'b00000000000111100000000010110011; + 7'b1001111 : exp <= 32'b00000000000111000000000010101001; + 7'b1010000 : exp <= 32'b00000000000110100000000010100001; + 7'b1010001 : exp <= 32'b00000000000110010000000010011001; + 7'b1010010 : exp <= 32'b00000000000101110000000010010001; + 7'b1010011 : exp <= 32'b00000000000101100000000010001001; + 7'b1010100 : exp <= 32'b00000000000101000000000010000010; + 7'b1010101 : exp <= 32'b00000000000100110000000001111100; + 7'b1010110 : exp <= 32'b00000000000100100000000001110101; + 7'b1010111 : exp <= 32'b00000000000100010000000001101111; + 7'b1011000 : exp <= 32'b00000000000100000000000001101001; + 7'b1011001 : exp <= 32'b00000000000011110000000001100100; + 7'b1011010 : exp <= 32'b00000000000011100000000001011111; + 7'b1011011 : exp <= 32'b00000000000011010000000001011010; + 7'b1011100 : exp <= 32'b00000000000011000000000001010101; + 7'b1011101 : exp <= 32'b00000000000010110000000001010001; + 7'b1011110 : exp <= 32'b00000000000010110000000001001101; + 7'b1011111 : exp <= 32'b00000000000010100000000001001001; + 7'b1100000 : exp <= 32'b00000000000010010000000001000101; + 7'b1100001 : exp <= 32'b00000000000010010000000001000001; + 7'b1100010 : exp <= 32'b00000000000010000000000000111110; + 7'b1100011 : exp <= 32'b00000000000010000000000000111010; + 7'b1100100 : exp <= 32'b00000000000001110000000000110111; + 7'b1100101 : exp <= 32'b00000000000001110000000000110100; + 7'b1100110 : exp <= 32'b00000000000001100000000000110010; + 7'b1100111 : exp <= 32'b00000000000001100000000000101111; + 7'b1101000 : exp <= 32'b00000000000001010000000000101100; + 7'b1101001 : exp <= 32'b00000000000001010000000000101010; + 7'b1101010 : exp <= 32'b00000000000001010000000000101000; + 7'b1101011 : exp <= 32'b00000000000001000000000000100110; + 7'b1101100 : exp <= 32'b00000000000001000000000000100100; + 7'b1101101 : exp <= 32'b00000000000001000000000000100010; + 7'b1101110 : exp <= 32'b00000000000001000000000000100000; + 7'b1101111 : exp <= 32'b00000000000000110000000000011110; + 7'b1110000 : exp <= 32'b00000000000000110000000000011101; + 7'b1110001 : exp <= 32'b00000000000000110000000000011011; + 7'b1110010 : exp <= 32'b00000000000000110000000000011010; + 7'b1110011 : exp <= 32'b00000000000000110000000000011000; + 7'b1110100 : exp <= 32'b00000000000000100000000000010111; + 7'b1110101 : exp <= 32'b00000000000000100000000000010110; + 7'b1110110 : exp <= 32'b00000000000000100000000000010100; + 7'b1110111 : exp <= 32'b00000000000000100000000000010011; + 7'b1111000 : exp <= 32'b00000000000000100000000000010010; + 7'b1111001 : exp <= 32'b00000000000000100000000000010001; + 7'b1111010 : exp <= 32'b00000000000000010000000000010000; + 7'b1111011 : exp <= 32'b00000000000000010000000000001111; + 7'b1111100 : exp <= 32'b00000000000000010000000000001111; + 7'b1111101 : exp <= 32'b00000000000000010000000000001110; + 7'b1111110 : exp <= 32'b00000000000000010000000000001101; + 7'b1111111 : exp <= 32'b00000000000000010000000000001100; + endcase + end +endmodule + +`ifdef SIMULATION_addfp +module adder_fp( + input clk, + input [15:0] a, + input [15:0] b, + output [15:0] out +); + assign out = a+b; +endmodule +`endif + + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Definition of a 16-bit floating point adder/subtractor +// This is a heavily modified version of: +// https://github.com/fbrosser/DSP48E1-FP/tree/master/src/FP_AddSub +// Original author: Fredrik Brosser +// Abridged by: Samidh Mehta +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// + +`ifndef complex_dsp + +module FPAddSub( + //bf16, + clk, + rst, + a, + b, + operation, // 0 add, 1 sub + result, + flags + ); + //input bf16; //1 for Bfloat16, 0 for IEEE half precision + + // Clock and reset + input clk ; // Clock signal + input rst ; // Reset (active high, resets pipeline registers) + + // Input ports + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + input operation ; // Operation select signal + + // Output ports + output [`DWIDTH-1:0] result ; // Result of the operation + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Pipeline Registers + //reg [79:0] pipe_1; // Pipeline register PreAlign->Align1 + reg [2*`EXPONENT + 2*`DWIDTH + 5:0] pipe_1; // Pipeline register PreAlign->Align1 + + //reg [67:0] pipe_2; // Pipeline register Align1->Align3 + //reg [2*`EXPONENT+ 2*`MANTISSA + 8:0] pipe_2; // Pipeline register Align1->Align3 + wire [2*`EXPONENT+ 2*`MANTISSA + 8:0] pipe_2; + + //reg [76:0] pipe_3; 68 // Pipeline register Align1->Align3 + reg [2*`EXPONENT+ 2*`MANTISSA + 9:0] pipe_3; // Pipeline register Align1->Align3 + + //reg [69:0] pipe_4; // Pipeline register Align3->Execute + //reg [2*`EXPONENT+ 2*`MANTISSA + 9:0] pipe_4; // Pipeline register Align3->Execute + wire [2*`EXPONENT+ 2*`MANTISSA + 9:0] pipe_4; + + //reg [51:0] pipe_5; // Pipeline register Execute->Normalize + reg [`DWIDTH+`EXPONENT+11:0] pipe_5; // Pipeline register Execute->Normalize + + //reg [56:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + //reg [`DWIDTH+`EXPONENT+16:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + wire [`DWIDTH+`EXPONENT+16:0] pipe_6; + + //reg [56:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + //reg [`DWIDTH+`EXPONENT+16:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + wire [`DWIDTH+`EXPONENT+16:0] pipe_7; + //reg [54:0] pipe_8; // Pipeline register NormalizeShift3->Round + reg [`EXPONENT*2+`MANTISSA+15:0] pipe_8; // Pipeline register NormalizeShift3->Round + + //reg [40:0] pipe_9; // Pipeline register NormalizeShift3->Round + //reg [`DWIDTH+8:0] pipe_9; // Pipeline register NormalizeShift3->Round + wire [`DWIDTH+8:0] pipe_9; + + // Internal wires between modules + wire [`DWIDTH-2:0] Aout_0 ; // A - sign + wire [`DWIDTH-2:0] Bout_0 ; // B - sign + wire Opout_0 ; // A's sign + wire Sa_0 ; // A's sign + wire Sb_0 ; // B's sign + wire MaxAB_1 ; // Indicates the larger of A and B(0/A, 1/B) + wire [`EXPONENT-1:0] CExp_1 ; // Common Exponent + wire [`EXPONENT-1:0] Shift_1 ; // Number of steps to smaller mantissa shift right (align) + wire [`MANTISSA-1:0] Mmax_1 ; // Larger mantissa + wire [4:0] InputExc_0 ; // Input numbers are exceptions + wire [2*`EXPONENT-1:0] ShiftDet_0 ; + wire [`MANTISSA-1:0] MminS_1 ; // Smaller mantissa after 0/16 shift + wire [`MANTISSA:0] MminS_2 ; // Smaller mantissa after 0/4/8/12 shift + wire [`MANTISSA:0] Mmin_3 ; // Smaller mantissa after 0/1/2/3 shift + wire [`DWIDTH:0] Sum_4 ; + wire PSgn_4 ; + wire Opr_4 ; + wire [`EXPONENT-1:0] Shift_5 ; // Number of steps to shift sum left (normalize) + wire [`DWIDTH:0] SumS_5 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_6 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_7 ; // Sum after 0/16 shift + wire [`MANTISSA-1:0] NormM_8 ; // Normalized mantissa + wire [`EXPONENT:0] NormE_8; // Adjusted exponent + wire ZeroSum_8 ; // Zero flag + wire NegE_8 ; // Flag indicating negative exponent + wire R_8 ; // Round bit + wire S_8 ; // Final sticky bit + wire FG_8 ; // Final sticky bit + wire [`DWIDTH-1:0] P_int ; + wire EOF ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_PrealignModule PrealignModule + ( // Inputs + a, b, operation, + // Outputs + Sa_0, Sb_0, ShiftDet_0[2*`EXPONENT-1:0], InputExc_0[4:0], Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Opout_0) ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_AlignModule AlignModule + ( // Inputs + pipe_1[2*`EXPONENT + 2*`DWIDTH + 4: 2*`EXPONENT +`DWIDTH + 6], pipe_1[2*`EXPONENT +`DWIDTH + 5 : 2*`EXPONENT +7], pipe_1[2*`EXPONENT+4:5], + // Outputs + CExp_1[`EXPONENT-1:0], MaxAB_1, Shift_1[`EXPONENT-1:0], MminS_1[`MANTISSA-1:0], Mmax_1[`MANTISSA-1:0]) ; + + // Alignment Shift Stage 1 + FPAddSub_AlignShift1 AlignShift1 + ( // Inputs + //bf16, + pipe_2[`MANTISSA-1:0], pipe_2[`EXPONENT+ 2*`MANTISSA + 4 : 2*`MANTISSA + 7], + // Outputs + MminS_2[`MANTISSA:0]) ; + + // Alignment Shift Stage 3 and compution of guard and sticky bits + FPAddSub_AlignShift2 AlignShift2 + ( // Inputs + pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+7:2*`MANTISSA+6], + // Outputs + Mmin_3[`MANTISSA:0]) ; + + // Perform mantissa addition + FPAddSub_ExecutionModule ExecutionModule + ( // Inputs + pipe_4[`MANTISSA*2+5:`MANTISSA+6], pipe_4[`MANTISSA:0], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 8], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 7], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 6], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 9], + // Outputs + Sum_4[`DWIDTH:0], PSgn_4, Opr_4) ; + + // Prepare normalization of result + FPAddSub_NormalizeModule NormalizeModule + ( // Inputs + pipe_5[`DWIDTH:0], + // Outputs + SumS_5[`DWIDTH:0], Shift_5[4:0]) ; + + // Normalization Shift Stage 1 + FPAddSub_NormalizeShift1 NormalizeShift1 + ( // Inputs + pipe_6[`DWIDTH:0], pipe_6[`DWIDTH+`EXPONENT+14:`DWIDTH+`EXPONENT+11], + // Outputs + SumS_7[`DWIDTH:0]) ; + + // Normalization Shift Stage 3 and final guard, sticky and round bits + FPAddSub_NormalizeShift2 NormalizeShift2 + ( // Inputs + pipe_7[`DWIDTH:0], pipe_7[`DWIDTH+`EXPONENT+5:`DWIDTH+6], pipe_7[`DWIDTH+`EXPONENT+15:`DWIDTH+`EXPONENT+11], + // Outputs + NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8, FG_8) ; + + // Round and put result together + FPAddSub_RoundModule RoundModule + ( // Inputs + pipe_8[3], pipe_8[4+`EXPONENT:4], pipe_8[`EXPONENT+`MANTISSA+4:5+`EXPONENT], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT*2+`MANTISSA+15], pipe_8[`EXPONENT*2+`MANTISSA+12], pipe_8[`EXPONENT*2+`MANTISSA+11], pipe_8[`EXPONENT*2+`MANTISSA+14], pipe_8[`EXPONENT*2+`MANTISSA+10], + // Outputs + P_int[`DWIDTH-1:0], EOF) ; + + // Check for exceptions + FPAddSub_ExceptionModule Exceptionmodule + ( // Inputs + pipe_9[8+`DWIDTH:9], pipe_9[8], pipe_9[7], pipe_9[6], pipe_9[5:1], pipe_9[0], + // Outputs + result[`DWIDTH-1:0], flags[4:0]) ; + + +assign pipe_2 = {pipe_1[2*`EXPONENT + 2*`DWIDTH + 5], pipe_1[2*`EXPONENT +6:2*`EXPONENT +5], MaxAB_1, CExp_1[`EXPONENT-1:0], Shift_1[`EXPONENT-1:0], Mmax_1[`MANTISSA-1:0], pipe_1[4:0], MminS_1[`MANTISSA-1:0]} ; +assign pipe_4 = {pipe_3[2*`EXPONENT+ 2*`MANTISSA + 9:`MANTISSA+1], Mmin_3[`MANTISSA:0]} ; +assign pipe_6 = {pipe_5[`DWIDTH+`EXPONENT+11], Shift_5[4:0], pipe_5[`DWIDTH+`EXPONENT+10:`DWIDTH+1], SumS_5[`DWIDTH:0]} ; +assign pipe_7 = {pipe_6[`DWIDTH+`EXPONENT+16:`DWIDTH+1], SumS_7[`DWIDTH:0]} ; +assign pipe_9 = {P_int[`DWIDTH-1:0], pipe_8[2], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT+`MANTISSA+9:`EXPONENT+`MANTISSA+5], EOF} ; + + always @ (posedge clk) begin + if(rst) begin + pipe_1 <= 0; + //pipe_2 <= 0; + pipe_3 <= 0; + //pipe_4 <= 0; + pipe_5 <= 0; + //pipe_6 <= 0; + //pipe_7 <= 0; + pipe_8 <= 0; + //pipe_9 <= 0; + end + else begin +/* PIPE_1: + [2*`EXPONENT + 2*`DWIDTH + 5] Opout_0 + [2*`EXPONENT + 2*`DWIDTH + 4: 2*`EXPONENT +`DWIDTH + 6] A_out0 + [2*`EXPONENT +`DWIDTH + 5 : 2*`EXPONENT +7] Bout_0 + [2*`EXPONENT +6] Sa_0 + [2*`EXPONENT +5] Sb_0 + [2*`EXPONENT +4 : 5] ShiftDet_0 + [4:0] Input Exc +*/ + pipe_1 <= {Opout_0, Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Sa_0, Sb_0, ShiftDet_0[2*`EXPONENT -1:0], InputExc_0[4:0]} ; +/* PIPE_2 +[2*`EXPONENT+ 2*`MANTISSA + 8] operation +[2*`EXPONENT+ 2*`MANTISSA + 7] Sa_0 +[2*`EXPONENT+ 2*`MANTISSA + 6] Sb_0 +[2*`EXPONENT+ 2*`MANTISSA + 5] MaxAB_0 +[2*`EXPONENT+ 2*`MANTISSA + 4:`EXPONENT+ 2*`MANTISSA + 5] CExp_0 +[`EXPONENT+ 2*`MANTISSA + 4 : 2*`MANTISSA + 5] Shift_0 +[2*`MANTISSA + 4:`MANTISSA + 5] Mmax_0 +[`MANTISSA + 4 : `MANTISSA] InputExc_0 +[`MANTISSA-1:0] MminS_1 +*/ + //pipe_2 <= {pipe_1[2*`EXPONENT + 2*`DWIDTH + 5], pipe_1[2*`EXPONENT +6:2*`EXPONENT +5], MaxAB_1, CExp_1[`EXPONENT-1:0], Shift_1[`EXPONENT-1:0], Mmax_1[`MANTISSA-1:0], pipe_1[4:0], MminS_1[`MANTISSA-1:0]} ; +/* PIPE_3 +[2*`EXPONENT+ 2*`MANTISSA + 9] operation +[2*`EXPONENT+ 2*`MANTISSA + 8] Sa_0 +[2*`EXPONENT+ 2*`MANTISSA + 7] Sb_0 +[2*`EXPONENT+ 2*`MANTISSA + 6] MaxAB_0 +[2*`EXPONENT+ 2*`MANTISSA + 5:`EXPONENT+ 2*`MANTISSA + 6] CExp_0 +[`EXPONENT+ 2*`MANTISSA + 5 : 2*`MANTISSA + 6] Shift_0 +[2*`MANTISSA + 5:`MANTISSA + 6] Mmax_0 +[`MANTISSA + 5 : `MANTISSA + 1] InputExc_0 +[`MANTISSA:0] MminS_2 +*/ + pipe_3 <= {pipe_2[2*`EXPONENT+ 2*`MANTISSA + 8:`MANTISSA], MminS_2[`MANTISSA:0]} ; +/* PIPE_4 +[2*`EXPONENT+ 2*`MANTISSA + 9] operation +[2*`EXPONENT+ 2*`MANTISSA + 8] Sa_0 +[2*`EXPONENT+ 2*`MANTISSA + 7] Sb_0 +[2*`EXPONENT+ 2*`MANTISSA + 6] MaxAB_0 +[2*`EXPONENT+ 2*`MANTISSA + 5:`EXPONENT+ 2*`MANTISSA + 6] CExp_0 +[`EXPONENT+ 2*`MANTISSA + 5 : 2*`MANTISSA + 6] Shift_0 +[2*`MANTISSA + 5:`MANTISSA + 6] Mmax_0 +[`MANTISSA + 5 : `MANTISSA + 1] InputExc_0 +[`MANTISSA:0] MminS_3 +*/ + //pipe_4 <= {pipe_3[2*`EXPONENT+ 2*`MANTISSA + 9:`MANTISSA+1], Mmin_3[`MANTISSA:0]} ; +/* PIPE_5 : +[`DWIDTH+ `EXPONENT + 11] operation +[`DWIDTH+ `EXPONENT + 10] PSgn_4 +[`DWIDTH+ `EXPONENT + 9] Opr_4 +[`DWIDTH+ `EXPONENT + 8] Sa_0 +[`DWIDTH+ `EXPONENT + 7] Sb_0 +[`DWIDTH+ `EXPONENT + 6] MaxAB_0 +[`DWIDTH+ `EXPONENT + 5 :`DWIDTH+6] CExp_0 +[`DWIDTH+5:`DWIDTH+1] InputExc_0 +[`DWIDTH:0] Sum_4 +*/ + pipe_5 <= {pipe_4[2*`EXPONENT+ 2*`MANTISSA + 9], PSgn_4, Opr_4, pipe_4[2*`EXPONENT+ 2*`MANTISSA + 8:`EXPONENT+ 2*`MANTISSA + 6], pipe_4[`MANTISSA+5:`MANTISSA+1], Sum_4[`DWIDTH:0]} ; +/* PIPE_6 : +[`DWIDTH+ `EXPONENT + 16] operation +[`DWIDTH+ `EXPONENT + 15:`DWIDTH+ `EXPONENT + 11] Shift_5 +[`DWIDTH+ `EXPONENT + 10] PSgn_4 +[`DWIDTH+ `EXPONENT + 9] Opr_4 +[`DWIDTH+ `EXPONENT + 8] Sa_0 +[`DWIDTH+ `EXPONENT + 7] Sb_0 +[`DWIDTH+ `EXPONENT + 6] MaxAB_0 +[`DWIDTH+ `EXPONENT + 5 :`DWIDTH+6] CExp_0 +[`DWIDTH+5:`DWIDTH+1] InputExc_0 +[`DWIDTH:0] Sum_4 +*/ + //pipe_6 <= {pipe_5[`DWIDTH+`EXPONENT+11], Shift_5[4:0], pipe_5[`DWIDTH+`EXPONENT+10:`DWIDTH+1], SumS_5[`DWIDTH:0]} ; +/* PIPE_7 : +[`DWIDTH+ `EXPONENT + 16] operation +[`DWIDTH+ `EXPONENT + 15:`DWIDTH+ `EXPONENT + 11] Shift_5 +[`DWIDTH+ `EXPONENT + 10] PSgn_4 +[`DWIDTH+ `EXPONENT + 9] Opr_4 +[`DWIDTH+ `EXPONENT + 8] Sa_0 +[`DWIDTH+ `EXPONENT + 7] Sb_0 +[`DWIDTH+ `EXPONENT + 6] MaxAB_0 +[`DWIDTH+ `EXPONENT + 5 :`DWIDTH+6] CExp_0 +[`DWIDTH+5:`DWIDTH+1] InputExc_0 +[`DWIDTH:0] Sum_4 +*/ + //pipe_7 <= {pipe_6[`DWIDTH+`EXPONENT+16:`DWIDTH+1], SumS_7[`DWIDTH:0]} ; +/* PIPE_8: +[2*`EXPONENT + `MANTISSA + 15] FG_8 +[2*`EXPONENT + `MANTISSA + 14] operation +[2*`EXPONENT + `MANTISSA + 13] PSgn_4 +[2*`EXPONENT + `MANTISSA + 12] Sa_0 +[2*`EXPONENT + `MANTISSA + 11] Sb_0 +[2*`EXPONENT + `MANTISSA + 10] MaxAB_0 +[2*`EXPONENT + `MANTISSA + 9:`EXPONENT + `MANTISSA + 10] CExp_0 +[`EXPONENT + `MANTISSA + 9:`EXPONENT + `MANTISSA + 5] InputExc_8 +[`EXPONENT + `MANTISSA + 4 :`EXPONENT + 5] NormM_8 +[`EXPONENT + 4 :4] NormE_8 +[3] ZeroSum_8 +[2] NegE_8 +[1] R_8 +[0] S_8 +*/ + pipe_8 <= {FG_8, pipe_7[`DWIDTH+`EXPONENT+16], pipe_7[`DWIDTH+`EXPONENT+10], pipe_7[`DWIDTH+`EXPONENT+8:`DWIDTH+1], NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8} ; +/* pipe_9: +[`DWIDTH + 8 :9] P_int +[8] NegE_8 +[7] R_8 +[6] S_8 +[5:1] InputExc_8 +[0] EOF +*/ + //pipe_9 <= {P_int[`DWIDTH-1:0], pipe_8[2], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT+`MANTISSA+9:`EXPONENT+`MANTISSA+5], EOF} ; + end + end + +endmodule + + +// +// Description: The pre-alignment module is responsible for taking the inputs +// apart and checking the parts for exceptions. +// The exponent difference is also calculated in this module. +// + + +module FPAddSub_PrealignModule( + A, + B, + operation, + Sa, + Sb, + ShiftDet, + InputExc, + Aout, + Bout, + Opout + ); + + // Input ports + input [`DWIDTH-1:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] B ; // Input B, a 32-bit floating point number + input operation ; + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [2*`EXPONENT-1:0] ShiftDet ; + output [4:0] InputExc ; // Input numbers are exceptions + output [`DWIDTH-2:0] Aout ; + output [`DWIDTH-2:0] Bout ; + output Opout ; + + // Internal signals // If signal is high... + wire ANaN ; // A is a NaN (Not-a-Number) + wire BNaN ; // B is a NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`EXPONENT-1:0] DAB ; // ExpA - ExpB + wire [`EXPONENT-1:0] DBA ; // ExpB - ExpA + + assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + + // Put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + + //assign DAB = (A[30:23] - B[30:23]) ; + //assign DBA = (B[30:23] - A[30:23]) ; + assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1'b1) ; + assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1'b1) ; + + assign Sa = A[`DWIDTH-1] ; // A's sign bit + assign Sb = B[`DWIDTH-1] ; // B's sign bit + assign ShiftDet = {DBA[`EXPONENT-1:0], DAB[`EXPONENT-1:0]} ; // Shift data + assign Opout = operation ; + assign Aout = A[`DWIDTH-2:0] ; + assign Bout = B[`DWIDTH-2:0] ; + +endmodule + + +// +// Description: The alignment module determines the larger input operand and +// sets the mantissas, shift and common exponent accordingly. +// + + +module FPAddSub_AlignModule ( + A, + B, + ShiftDet, + CExp, + MaxAB, + Shift, + Mmin, + Mmax + ); + + // Input ports + input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-2:0] B ; // Input B, a 32-bit floating point number + input [2*`EXPONENT-1:0] ShiftDet ; + + // Output ports + output [`EXPONENT-1:0] CExp ; // Common Exponent + output MaxAB ; // Incidates larger of A and B (0/A, 1/B) + output [`EXPONENT-1:0] Shift ; // Number of steps to smaller mantissa shift right + output [`MANTISSA-1:0] Mmin ; // Smaller mantissa + output [`MANTISSA-1:0] Mmax ; // Larger mantissa + + // Internal signals + //wire BOF ; // Check for shifting overflow if B is larger + //wire AOF ; // Check for shifting overflow if A is larger + + assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]) ; + //assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits + //assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits + + // Determine final shift value + //assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ; + + assign Shift = MaxAB ? ShiftDet[2*`EXPONENT-1:`EXPONENT] : ShiftDet[`EXPONENT-1:0] ; + + // Take out smaller mantissa and append shift space + assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0] ; + + // Take out larger mantissa + assign Mmax = MaxAB ? B[`MANTISSA-1:0]: A[`MANTISSA-1:0] ; + + // Common exponent + assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]) ; + +endmodule + + +// Description: Alignment shift stage 1, performs 16|12|8|4 shift +// + + +// ONLY THIS MODULE IS HARDCODED for half precision fp16 and bfloat16 +module FPAddSub_AlignShift1( + //bf16, + MminP, + Shift, + Mmin + ); + + // Input ports + //input bf16; + input [`MANTISSA-1:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bits + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + + wire bf16; + assign bf16 = 1'b1; //hardcoding to 1, to avoid ODIN issue. a `ifdef here wasn't working. apparently, nested `ifdefs don't work + + // Internal signals + reg [`MANTISSA:0] Lvl1; + reg [`MANTISSA:0] Lvl2; + wire [2*`MANTISSA+1:0] Stage1; + integer i; // Loop variable + + always @(*) begin + if (bf16 == 1'b1) begin +//hardcoding for bfloat16 + //For bfloat16, we can shift the mantissa by a max of 7 bits since mantissa has a width of 7. + //Hence if either, bit[3]/bit[4]/bit[5]/bit[6]/bit[7] is 1, we can make it 0. This corresponds to bits [5:1] in our updated shift which doesn't contain last 2 bits. + //Lvl1 <= (Shift[1]|Shift[2]|Shift[3]|Shift[4]|Shift[5]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width + Lvl1 <= (|Shift[`EXPONENT-3:1]) ? 11'd0 : {1'b1, MminP}; // MANTISSA + 1 width + end + else begin + //for half precision fp16, 10 bits can be shifted. Hence, only shifts till 10 (01010)can be made. + Lvl1 <= Shift[2] ? 11'd0 : {1'b1, MminP}; + end + end + + assign Stage1 = {Lvl1, Lvl1}; //2*MANTISSA + 2 width + + always @(*) begin // Rotate {0 | 4 } bits + if(bf16 == 1'b1) begin + case (Shift[0]) + // Rotate by 0 + 1'b0: Lvl2 <= Stage1[`MANTISSA:0]; + // Rotate by 4 + 1'b1: Lvl2 <= Stage1[`MANTISSA+4:4]; + //1'b1: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+4]; end end + endcase + end + else begin + case (Shift[1:0]) // Rotate {0 | 4 | 8} bits + // Rotate by 0 + 2'b00: Lvl2 <= Stage1[`MANTISSA:0]; + // Rotate by 4 + 2'b01: Lvl2 <= Stage1[`MANTISSA+4:4]; + //2'b01: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+4]; end end + // Rotate by 8 + 2'b10: Lvl2 <= Stage1[`MANTISSA+8:8]; + //2'b10: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+8]; end end + // Rotate by 12 + 2'b11: Lvl2[`MANTISSA: 0] <= 0; + //2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end + default: Lvl2[`MANTISSA: 0] <= 0; + endcase + end + end + + // Assign output to next shift stage + assign Mmin = Lvl2; + +endmodule + + +// Description: Alignment shift stage 2, performs 3|2|1 shift +// + + +module FPAddSub_AlignShift2( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`MANTISSA:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [1:0] Shift ; // Shift amount. Last 2 bits + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + // Internal Signal + reg [`MANTISSA:0] Lvl3; + wire [2*`MANTISSA+1:0] Stage2; + integer j; // Loop variable + + assign Stage2 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl3 <= Stage2[`MANTISSA:0]; + // Rotate by 1 + 2'b01: Lvl3 <= Stage2[`MANTISSA+1:1]; + //2'b01: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+1]; end end + // Rotate by 2 + 2'b10: Lvl3 <= Stage2[`MANTISSA+2:2]; + //2'b10: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+2]; end end + // Rotate by 3 + 2'b11: Lvl3 <= Stage2[`MANTISSA+3:3]; + //2'b11: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+3]; end end + default: Lvl3 <= Stage2[`MANTISSA+3:3]; + //default: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+3]; end end + endcase + end + + // Assign output + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + + +// +// Description: Module that executes the addition or subtraction on mantissas. +// + + +module FPAddSub_ExecutionModule( + Mmax, + Mmin, + Sa, + Sb, + MaxAB, + OpMode, + Sum, + PSgn, + Opr + ); + + // Input ports + input [`MANTISSA-1:0] Mmax ; // The larger mantissa + input [`MANTISSA:0] Mmin ; // The smaller mantissa + input Sa ; // Sign bit of larger number + input Sb ; // Sign bit of smaller number + input MaxAB ; // Indicates the larger number (0/A, 1/B) + input OpMode ; // Operation to be performed (0/Add, 1/Sub) + + // Output ports + output [`DWIDTH:0] Sum ; // The result of the operation + output PSgn ; // The sign for the result + output Opr ; // The effective (performed) operation + + wire [`EXPONENT-1:0]temp_1; + + assign Opr = (OpMode^Sa^Sb); // Resolve sign to determine operation + assign temp_1 = 0; + // Perform effective operation +//SAMIDH_UNSURE 5--> 8 + + assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, temp_1} - {Mmin, temp_1}) : ({1'b1, Mmax, temp_1} + {Mmin, temp_1}) ; + + // Assign result sign + assign PSgn = (MaxAB ? Sb : Sa) ; + +endmodule + + +// +// Description: Determine the normalization shift amount and perform 16-shift +// + + +module FPAddSub_NormalizeModule( + Sum, + Mmin, + Shift + ); + + // Input ports + input [`DWIDTH:0] Sum ; // Mantissa sum including hidden 1 and GRS + + // Output ports + output [`DWIDTH:0] Mmin ; // Mantissa after 16|0 shift + output [4:0] Shift ; // Shift amount + //Changes in this doesn't matter since even Bfloat16 can't go beyond 7 shift to the mantissa (only 3 bits valid here) + // Determine normalization shift amount by finding leading nought + assign Shift = ( + Sum[16] ? 5'b00000 : + Sum[15] ? 5'b00001 : + Sum[14] ? 5'b00010 : + Sum[13] ? 5'b00011 : + Sum[12] ? 5'b00100 : + Sum[11] ? 5'b00101 : + Sum[10] ? 5'b00110 : + Sum[9] ? 5'b00111 : + Sum[8] ? 5'b01000 : + Sum[7] ? 5'b01001 : + Sum[6] ? 5'b01010 : + Sum[5] ? 5'b01011 : + Sum[4] ? 5'b01100 : 5'b01101 + // Sum[19] ? 5'b01101 : + // Sum[18] ? 5'b01110 : + // Sum[17] ? 5'b01111 : + // Sum[16] ? 5'b10000 : + // Sum[15] ? 5'b10001 : + // Sum[14] ? 5'b10010 : + // Sum[13] ? 5'b10011 : + // Sum[12] ? 5'b10100 : + // Sum[11] ? 5'b10101 : + // Sum[10] ? 5'b10110 : + // Sum[9] ? 5'b10111 : + // Sum[8] ? 5'b11000 : + // Sum[7] ? 5'b11001 : 5'b11010 + ); + + reg [`DWIDTH:0] Lvl1; + + always @(*) begin + // Rotate by 16? + Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum; + end + + // Assign outputs + assign Mmin = Lvl1; // Take out smaller mantissa + +endmodule + + +// Description: Normalization shift stage 1, performs 12|8|4|3|2|1|0 shift +// +//Hardcoding loop start and end values of i. To avoid ODIN limitations. i=`DWIDTH*2+1 wasn't working. + +module FPAddSub_NormalizeShift1( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`DWIDTH:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [3:0] Shift ; // Shift amount + + // Output ports + output [`DWIDTH:0] Mmin ; // The smaller mantissa + + reg [`DWIDTH:0] Lvl2; + wire [2*`DWIDTH+1:0] Stage1; + reg [`DWIDTH:0] Lvl3; + wire [2*`DWIDTH+1:0] Stage2; + integer i; // Loop variable + + assign Stage1 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 4 | 8 | 12} bits + case (Shift[3:2]) + // Rotate by 0 + 2'b00: Lvl2 <= Stage1[`DWIDTH:0]; + // Rotate by 4' + 2'b01: Lvl2[16:0] <= Stage1[28:13]; + //2'b01: begin for (i=33; i>=17; i=i-1) begin Lvl2[i-`DWIDTH-1] <= Stage1[i-4]; end Lvl2[3:0] <= 0; end + // Rotate by 8 + 2'b10: Lvl2[16:0] <= Stage1[24:9]; + //2'b10: begin for (i=33; i>=17; i=i-1) begin Lvl2[i-`DWIDTH-1] <= Stage1[i-8]; end Lvl2[7:0] <= 0; end + // Rotate by 12 + 2'b11: Lvl2[16:0] <= Stage1[20:5]; + //2'b11: begin for (i=33; i>=17; i=i-1) begin Lvl2[i-`DWIDTH-1] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end + //default: begin for (i=33; i>=17; i=i-1) begin Lvl2[i-`DWIDTH-1] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end + default: Lvl2[16:0] <= Stage1[20:5]; + endcase + end + + assign Stage2 = {Lvl2, Lvl2}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl3 <= Stage2[`DWIDTH:0]; + // Rotate by 1 + 2'b01: Lvl3[16:0] <= Stage2[31:16]; + //2'b01: begin for (i=33; i>=17; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-1]; end Lvl3[0] <= 0; end + // Rotate by 2 + 2'b10: Lvl3[16:0] <= Stage2[30:15]; + //2'b10: begin for (i=33; i>=17; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-2]; end Lvl3[1:0] <= 0; end + // Rotate by 3 + 2'b11: Lvl3[16:0] <= Stage2[29:14]; + //2'b11: begin for (i=33; i>=17; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end + default: Lvl3[16:0] <= Stage2[29:14]; + //default: begin for (i=33; i>=17; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end + endcase + end + + // Assign outputs + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + + +// Description: Normalization shift stage 2, calculates post-normalization +// mantissa and exponent, as well as the bits used in rounding +// + + +module FPAddSub_NormalizeShift2( + PSSum, + CExp, + Shift, + NormM, + NormE, + ZeroSum, + NegE, + R, + S, + FG + ); + + // Input ports + input [`DWIDTH:0] PSSum ; // The Pre-Shift-Sum + input [`EXPONENT-1:0] CExp ; + input [4:0] Shift ; // Amount to be shifted + + // Output ports + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output [`EXPONENT:0] NormE ; // Adjusted exponent + output ZeroSum ; // Zero flag + output NegE ; // Flag indicating negative exponent + output R ; // Round bit + output S ; // Final sticky bit + output FG ; + + // Internal signals + wire MSBShift ; // Flag indicating that a second shift is needed + wire [`EXPONENT:0] ExpOF ; // MSB set in sum indicates overflow + wire [`EXPONENT:0] ExpOK ; // MSB not set, no adjustment + + // Calculate normalized exponent and mantissa, check for all-zero sum + assign MSBShift = PSSum[`DWIDTH] ; // Check MSB in unnormalized sum + assign ZeroSum = ~|PSSum ; // Check for all zero sum + assign ExpOK = CExp - Shift ; // Adjust exponent for new normalized mantissa + assign NegE = ExpOK[`EXPONENT] ; // Check for exponent overflow + assign ExpOF = CExp - Shift + 1'b1 ; // If MSB set, add one to exponent(x2) + assign NormE = MSBShift ? ExpOF : ExpOK ; // Check for exponent overflow + assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1] ; // The new, normalized mantissa + + // Also need to compute sticky and round bits for the rounding stage + assign FG = PSSum[`EXPONENT] ; + assign R = PSSum[`EXPONENT-1] ; + assign S = |PSSum[`EXPONENT-2:0] ; + +endmodule + + +// Description: Performs 'Round to nearest, tie to even'-rounding on the +// normalized mantissa according to the G, R, S bits. Calculates +// final result and checks for exponent overflow. +// + + +module FPAddSub_RoundModule( + ZeroSum, + NormE, + NormM, + R, + S, + G, + Sa, + Sb, + Ctrl, + MaxAB, + Z, + EOF + ); + + // Input ports + input ZeroSum ; // Sum is zero + input [`EXPONENT:0] NormE ; // Normalized exponent + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input R ; // Round bit + input S ; // Sticky bit + input G ; + input Sa ; // A's sign bit + input Sb ; // B's sign bit + input Ctrl ; // Control bit (operation) + input MaxAB ; + + // Output ports + output [`DWIDTH-1:0] Z ; // Final result + output EOF ; + + // Internal signals + wire [`MANTISSA:0] RoundUpM ; // Rounded up sum with room for overflow + wire [`MANTISSA-1:0] RoundM ; // The final rounded sum + wire [`EXPONENT:0] RoundE ; // Rounded exponent (note extra bit due to poential overflow ) + wire RoundUp ; // Flag indicating that the sum should be rounded up + wire FSgn; + wire ExpAdd ; // May have to add 1 to compensate for overflow + wire RoundOF ; // Rounding overflow + + wire [`EXPONENT:0]temp_2; + assign temp_2 = 0; + // The cases where we need to round upwards (= adding one) in Round to nearest, tie to even + assign RoundUp = (G & ((R | S) | NormM[0])) ; + + // Note that in the other cases (rounding down), the sum is already 'rounded' + assign RoundUpM = (NormM + 1'b1) ; // The sum, rounded up by 1 + assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM) ; // Compute final mantissa + assign RoundOF = RoundUp & RoundUpM[`MANTISSA] ; // Check for overflow when rounding up + + // Calculate post-rounding exponent + assign ExpAdd = (RoundOF ? 1'b1 : 1'b0) ; // Add 1 to exponent to compensate for overflow + assign RoundE = ZeroSum ? temp_2 : (NormE + ExpAdd) ; // Final exponent + + // If zero, need to determine sign according to rounding + assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ; + + // Assign final result + assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]} ; + + // Indicate exponent overflow + assign EOF = RoundE[`EXPONENT]; + +endmodule + + +// +// Description: Check the final result for exception conditions and set +// flags accordingly. +// + + +module FPAddSub_ExceptionModule( + Z, + NegE, + R, + S, + InputExc, + EOF, + P, + Flags + ); + + // Input ports + input [`DWIDTH-1:0] Z ; // Final product + input NegE ; // Negative exponent? + input R ; // Round bit + input S ; // Sticky bit + input [4:0] InputExc ; // Exceptions in inputs A and B + input EOF ; + + // Output ports + output [`DWIDTH-1:0] P ; // Final result + output [4:0] Flags ; // Exception flags + + // Internal signals + wire Overflow ; // Overflow flag + wire Underflow ; // Underflow flag + wire DivideByZero ; // Divide-by-Zero flag (always 0 in Add/Sub) + wire Invalid ; // Invalid inputs or result + wire Inexact ; // Result is inexact because of rounding + + // Exception flags + + // Result is too big to be represented + assign Overflow = EOF | InputExc[1] | InputExc[0] ; + + // Result is too small to be represented + assign Underflow = NegE & (R | S); + + // Infinite result computed exactly from finite operands + assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0]; + + // Invalid inputs or operation + assign Invalid = |(InputExc[4:2]) ; + + // Inexact answer due to rounding, overflow or underflow + assign Inexact = (R | S) | Overflow | Underflow; + + // Put pieces together to form final result + assign P = Z ; + + // Collect exception flags + assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact} ; + +endmodule + +`endif + diff --git a/designs/koios/attention_layer/attention_random.sv b/designs/koios/attention_layer/attention_random.sv new file mode 100644 index 000000000..84704f518 --- /dev/null +++ b/designs/koios/attention_layer/attention_random.sv @@ -0,0 +1,53 @@ +/* +* attention_random top level module that incorporates the random number generator +* to allow bitstream generation without Vivado optimizing wrapped inputs +*/ +`include "../../random_number_generator.sv" + +`define VECTOR_DEPTH 64 //Q,K,V vector size +`define DATA_WIDTH 16 +`define VECTOR_BITS 1024 // 16 bit each (16x64) +`define NUM_WORDS 32 //num of words in the sentence +`define BUF_AWIDTH 4 //16 entries in each buffer ram +`define BUF_LOC_SIZE 4 //4 words in each addr location +`define OUT_RAM_DEPTH 512 //512 entries in output bram +`define LOG_OUT_RAM_DEPTH 9 //512 entries in output bram + +module attention_random( + input logic clk, + input logic reset, + input logic start, + input [4:0] q_rd_addr, + input [4:0] k_rd_addr, + input [4:0] v_rd_addr, + input [2:0] wren_qkv_ext, + input [4:0] address_ext, + input [`LOG_OUT_RAM_DEPTH-1:0] out_rd_addr, + output [`DATA_WIDTH-1:0] out_part1, + output [`DATA_WIDTH-1:0] out_part2 +); + +logic [`VECTOR_BITS-1:0] data_in; + +RandomNumberGenerator #(`VECTOR_BITS, `VECTOR_BITS) rng1( + .clk(clk), + .reset(reset), + .random_number(data_in) +); + +attention_layer attn( + .clk(clk), + .rst(reset), + .start(start), + .q_rd_addr(q_rd_addr), //start address of q + .k_rd_addr(k_rd_addr), //start address of k + .v_rd_addr(v_rd_addr), //start address of v + .wren_qkv_ext(wren_qkv_ext), //To write data into Q,K,V BRAMs externally + .address_ext(address_ext), //External write address + .data_ext(data_in), //Data to be written + .out_rd_addr(out_rd_addr), //To read stored outputs from outside + .out_part1(out_part1), //16 bit output from out bram + .out_part2(out_part2) //16 bit output from out bram +); + +endmodule \ No newline at end of file diff --git a/designs/koios/attention_layer/design.yaml b/designs/koios/attention_layer/design.yaml new file mode 100644 index 000000000..54937c189 --- /dev/null +++ b/designs/koios/attention_layer/design.yaml @@ -0,0 +1 @@ +top: attention_random diff --git a/designs/koios/bnn/bnn.v b/designs/koios/bnn/bnn.v new file mode 100644 index 000000000..b9a895c7e --- /dev/null +++ b/designs/koios/bnn/bnn.v @@ -0,0 +1,32595 @@ +////////////////////////////////////////////////////////////////////////////// +//HLS generated design for 4-layered binary neural network +//The dataflow is specific to the network +//The design uses 16-bit fixed point for activations, binary for weights +//The dense layers are binary. Activation is relu. +//There is no memory, design uses registers to store activations and weights. +//Generated from HLS using hls4ml +//The network used was https://github.com/fastmachinelearning/example-models/blob/master/keras/KERAS_3layer_binarydense_relu_max.json +////////////////////////////////////////////////////////////////////////////// + +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +////////////////////////////////////////////////////////////////////////////// +// Abridged for VTR by: Aman Arora +////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1 ( + ap_clk, + ap_rst, + data_V_read, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3, + ap_return_4, + ap_return_5, + ap_return_6, + ap_return_7, + ap_return_8, + ap_return_9, + ap_return_10, + ap_return_11, + ap_return_12, + ap_return_13, + ap_return_14, + ap_return_15, + ap_return_16, + ap_return_17, + ap_return_18, + ap_return_19, + ap_return_20, + ap_return_21, + ap_return_22, + ap_return_23, + ap_return_24, + ap_return_25, + ap_return_26, + ap_return_27, + ap_return_28, + ap_return_29, + ap_return_30, + ap_return_31, + ap_return_32, + ap_return_33, + ap_return_34, + ap_return_35, + ap_return_36, + ap_return_37, + ap_return_38, + ap_return_39, + ap_return_40, + ap_return_41, + ap_return_42, + ap_return_43, + ap_return_44, + ap_return_45, + ap_return_46, + ap_return_47, + ap_return_48, + ap_return_49, + ap_return_50, + ap_return_51, + ap_return_52, + ap_return_53, + ap_return_54, + ap_return_55, + ap_return_56, + ap_return_57, + ap_return_58, + ap_return_59, + ap_return_60, + ap_return_61, + ap_return_62, + ap_return_63, + ap_ce +); + + +input ap_clk; +input ap_rst; +input [255:0] data_V_read; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; +output [15:0] ap_return_4; +output [15:0] ap_return_5; +output [15:0] ap_return_6; +output [15:0] ap_return_7; +output [15:0] ap_return_8; +output [15:0] ap_return_9; +output [15:0] ap_return_10; +output [15:0] ap_return_11; +output [15:0] ap_return_12; +output [15:0] ap_return_13; +output [15:0] ap_return_14; +output [15:0] ap_return_15; +output [15:0] ap_return_16; +output [15:0] ap_return_17; +output [15:0] ap_return_18; +output [15:0] ap_return_19; +output [15:0] ap_return_20; +output [15:0] ap_return_21; +output [15:0] ap_return_22; +output [15:0] ap_return_23; +output [15:0] ap_return_24; +output [15:0] ap_return_25; +output [15:0] ap_return_26; +output [15:0] ap_return_27; +output [15:0] ap_return_28; +output [15:0] ap_return_29; +output [15:0] ap_return_30; +output [15:0] ap_return_31; +output [15:0] ap_return_32; +output [15:0] ap_return_33; +output [15:0] ap_return_34; +output [15:0] ap_return_35; +output [15:0] ap_return_36; +output [15:0] ap_return_37; +output [15:0] ap_return_38; +output [15:0] ap_return_39; +output [15:0] ap_return_40; +output [15:0] ap_return_41; +output [15:0] ap_return_42; +output [15:0] ap_return_43; +output [15:0] ap_return_44; +output [15:0] ap_return_45; +output [15:0] ap_return_46; +output [15:0] ap_return_47; +output [15:0] ap_return_48; +output [15:0] ap_return_49; +output [15:0] ap_return_50; +output [15:0] ap_return_51; +output [15:0] ap_return_52; +output [15:0] ap_return_53; +output [15:0] ap_return_54; +output [15:0] ap_return_55; +output [15:0] ap_return_56; +output [15:0] ap_return_57; +output [15:0] ap_return_58; +output [15:0] ap_return_59; +output [15:0] ap_return_60; +output [15:0] ap_return_61; +output [15:0] ap_return_62; +output [15:0] ap_return_63; +input ap_ce; + +reg[15:0] ap_return_0; +reg[15:0] ap_return_1; +reg[15:0] ap_return_2; +reg[15:0] ap_return_3; +reg[15:0] ap_return_4; +reg[15:0] ap_return_5; +reg[15:0] ap_return_6; +reg[15:0] ap_return_7; +reg[15:0] ap_return_8; +reg[15:0] ap_return_9; +reg[15:0] ap_return_10; +reg[15:0] ap_return_11; +reg[15:0] ap_return_12; +reg[15:0] ap_return_13; +reg[15:0] ap_return_14; +reg[15:0] ap_return_15; +reg[15:0] ap_return_16; +reg[15:0] ap_return_17; +reg[15:0] ap_return_18; +reg[15:0] ap_return_19; +reg[15:0] ap_return_20; +reg[15:0] ap_return_21; +reg[15:0] ap_return_22; +reg[15:0] ap_return_23; +reg[15:0] ap_return_24; +reg[15:0] ap_return_25; +reg[15:0] ap_return_26; +reg[15:0] ap_return_27; +reg[15:0] ap_return_28; +reg[15:0] ap_return_29; +reg[15:0] ap_return_30; +reg[15:0] ap_return_31; +reg[15:0] ap_return_32; +reg[15:0] ap_return_33; +reg[15:0] ap_return_34; +reg[15:0] ap_return_35; +reg[15:0] ap_return_36; +reg[15:0] ap_return_37; +reg[15:0] ap_return_38; +reg[15:0] ap_return_39; +reg[15:0] ap_return_40; +reg[15:0] ap_return_41; +reg[15:0] ap_return_42; +reg[15:0] ap_return_43; +reg[15:0] ap_return_44; +reg[15:0] ap_return_45; +reg[15:0] ap_return_46; +reg[15:0] ap_return_47; +reg[15:0] ap_return_48; +reg[15:0] ap_return_49; +reg[15:0] ap_return_50; +reg[15:0] ap_return_51; +reg[15:0] ap_return_52; +reg[15:0] ap_return_53; +reg[15:0] ap_return_54; +reg[15:0] ap_return_55; +reg[15:0] ap_return_56; +reg[15:0] ap_return_57; +reg[15:0] ap_return_58; +reg[15:0] ap_return_59; +reg[15:0] ap_return_60; +reg[15:0] ap_return_61; +reg[15:0] ap_return_62; +reg[15:0] ap_return_63; + +wire [15:0] trunc_ln203_fu_88_p1; +reg [15:0] trunc_ln203_reg_3431; +wire ap_block_state1_pp0_stage0_iter0; +wire ap_block_state2_pp0_stage0_iter1; +wire ap_block_state3_pp0_stage0_iter2; +wire ap_block_state4_pp0_stage0_iter3; +wire ap_block_state5_pp0_stage0_iter4; +wire ap_block_state6_pp0_stage0_iter5; +wire ap_block_state7_pp0_stage0_iter6; +wire ap_block_state8_pp0_stage0_iter7; +wire ap_block_state9_pp0_stage0_iter8; +wire ap_block_pp0_stage0_11001; +wire [15:0] tmp_2_fu_92_p4; +reg [15:0] tmp_2_reg_3437; +reg [15:0] tmp_3_reg_3443; +reg [15:0] tmp_3_reg_3443_pp0_iter1_reg; +reg [15:0] tmp_3_reg_3443_pp0_iter2_reg; +reg [15:0] tmp_4_reg_3454; +reg [15:0] tmp_4_reg_3454_pp0_iter1_reg; +reg [15:0] tmp_4_reg_3454_pp0_iter2_reg; +reg [15:0] tmp_4_reg_3454_pp0_iter3_reg; +reg [15:0] tmp_4_reg_3454_pp0_iter4_reg; +reg [15:0] mult_307_V_reg_3472; +reg [15:0] mult_307_V_reg_3472_pp0_iter1_reg; +reg [15:0] mult_307_V_reg_3472_pp0_iter2_reg; +reg [15:0] mult_307_V_reg_3472_pp0_iter3_reg; +reg [15:0] mult_307_V_reg_3472_pp0_iter4_reg; +reg [15:0] mult_307_V_reg_3472_pp0_iter5_reg; +reg [15:0] mult_320_V_reg_3500; +reg [15:0] mult_320_V_reg_3500_pp0_iter1_reg; +reg [15:0] mult_320_V_reg_3500_pp0_iter2_reg; +reg [15:0] mult_320_V_reg_3500_pp0_iter3_reg; +reg [15:0] mult_320_V_reg_3500_pp0_iter4_reg; +reg [15:0] mult_320_V_reg_3500_pp0_iter5_reg; +reg [15:0] mult_386_V_reg_3539; +reg [15:0] mult_386_V_reg_3539_pp0_iter1_reg; +reg [15:0] mult_386_V_reg_3539_pp0_iter2_reg; +reg [15:0] mult_386_V_reg_3539_pp0_iter3_reg; +reg [15:0] mult_386_V_reg_3539_pp0_iter4_reg; +reg [15:0] mult_386_V_reg_3539_pp0_iter5_reg; +reg [15:0] mult_386_V_reg_3539_pp0_iter6_reg; +reg [15:0] mult_449_V_reg_3582; +reg [15:0] mult_449_V_reg_3582_pp0_iter1_reg; +reg [15:0] mult_449_V_reg_3582_pp0_iter2_reg; +reg [15:0] mult_449_V_reg_3582_pp0_iter3_reg; +reg [15:0] mult_449_V_reg_3582_pp0_iter4_reg; +reg [15:0] mult_449_V_reg_3582_pp0_iter5_reg; +reg [15:0] mult_449_V_reg_3582_pp0_iter6_reg; +reg [15:0] mult_512_V_reg_3629; +reg [15:0] mult_512_V_reg_3629_pp0_iter1_reg; +reg [15:0] mult_512_V_reg_3629_pp0_iter2_reg; +reg [15:0] mult_512_V_reg_3629_pp0_iter3_reg; +reg [15:0] mult_512_V_reg_3629_pp0_iter4_reg; +reg [15:0] mult_512_V_reg_3629_pp0_iter5_reg; +reg [15:0] mult_512_V_reg_3629_pp0_iter6_reg; +reg [15:0] mult_576_V_reg_3674; +reg [15:0] mult_576_V_reg_3674_pp0_iter1_reg; +reg [15:0] mult_576_V_reg_3674_pp0_iter2_reg; +reg [15:0] mult_576_V_reg_3674_pp0_iter3_reg; +reg [15:0] mult_576_V_reg_3674_pp0_iter4_reg; +reg [15:0] mult_576_V_reg_3674_pp0_iter5_reg; +reg [15:0] mult_576_V_reg_3674_pp0_iter6_reg; +reg [15:0] mult_640_V_reg_3716; +reg [15:0] mult_640_V_reg_3716_pp0_iter1_reg; +reg [15:0] mult_640_V_reg_3716_pp0_iter2_reg; +reg [15:0] mult_640_V_reg_3716_pp0_iter3_reg; +reg [15:0] mult_640_V_reg_3716_pp0_iter4_reg; +reg [15:0] mult_640_V_reg_3716_pp0_iter5_reg; +reg [15:0] mult_640_V_reg_3716_pp0_iter6_reg; +reg [15:0] mult_704_V_reg_3765; +reg [15:0] mult_704_V_reg_3765_pp0_iter1_reg; +reg [15:0] mult_704_V_reg_3765_pp0_iter2_reg; +reg [15:0] mult_704_V_reg_3765_pp0_iter3_reg; +reg [15:0] mult_704_V_reg_3765_pp0_iter4_reg; +reg [15:0] mult_704_V_reg_3765_pp0_iter5_reg; +reg [15:0] mult_704_V_reg_3765_pp0_iter6_reg; +reg [15:0] mult_704_V_reg_3765_pp0_iter7_reg; +reg [15:0] mult_770_V_reg_3814; +reg [15:0] mult_770_V_reg_3814_pp0_iter1_reg; +reg [15:0] mult_770_V_reg_3814_pp0_iter2_reg; +reg [15:0] mult_770_V_reg_3814_pp0_iter3_reg; +reg [15:0] mult_770_V_reg_3814_pp0_iter4_reg; +reg [15:0] mult_770_V_reg_3814_pp0_iter5_reg; +reg [15:0] mult_770_V_reg_3814_pp0_iter6_reg; +reg [15:0] mult_770_V_reg_3814_pp0_iter7_reg; +reg [15:0] mult_832_V_reg_3861; +reg [15:0] mult_832_V_reg_3861_pp0_iter1_reg; +reg [15:0] mult_832_V_reg_3861_pp0_iter2_reg; +reg [15:0] mult_832_V_reg_3861_pp0_iter3_reg; +reg [15:0] mult_832_V_reg_3861_pp0_iter4_reg; +reg [15:0] mult_832_V_reg_3861_pp0_iter5_reg; +reg [15:0] mult_832_V_reg_3861_pp0_iter6_reg; +reg [15:0] mult_832_V_reg_3861_pp0_iter7_reg; +reg [15:0] mult_896_V_reg_3909; +reg [15:0] mult_896_V_reg_3909_pp0_iter1_reg; +reg [15:0] mult_896_V_reg_3909_pp0_iter2_reg; +reg [15:0] mult_896_V_reg_3909_pp0_iter3_reg; +reg [15:0] mult_896_V_reg_3909_pp0_iter4_reg; +reg [15:0] mult_896_V_reg_3909_pp0_iter5_reg; +reg [15:0] mult_896_V_reg_3909_pp0_iter6_reg; +reg [15:0] mult_896_V_reg_3909_pp0_iter7_reg; +reg [15:0] mult_960_V_reg_3958; +reg [15:0] mult_960_V_reg_3958_pp0_iter1_reg; +reg [15:0] mult_960_V_reg_3958_pp0_iter2_reg; +reg [15:0] mult_960_V_reg_3958_pp0_iter3_reg; +reg [15:0] mult_960_V_reg_3958_pp0_iter4_reg; +reg [15:0] mult_960_V_reg_3958_pp0_iter5_reg; +reg [15:0] mult_960_V_reg_3958_pp0_iter6_reg; +reg [15:0] mult_960_V_reg_3958_pp0_iter7_reg; +wire [15:0] add_ln703_fu_242_p2; +reg [15:0] add_ln703_reg_4010; +reg [15:0] add_ln703_reg_4010_pp0_iter1_reg; +reg [15:0] add_ln703_reg_4010_pp0_iter2_reg; +wire [15:0] sub_ln703_fu_248_p2; +reg [15:0] sub_ln703_reg_4017; +reg [15:0] sub_ln703_reg_4017_pp0_iter2_reg; +wire [15:0] sub_ln703_531_fu_252_p2; +reg [15:0] sub_ln703_531_reg_4023; +reg [15:0] sub_ln703_531_reg_4023_pp0_iter2_reg; +wire [15:0] sub_ln703_534_fu_256_p2; +reg [15:0] sub_ln703_534_reg_4029; +reg [15:0] sub_ln703_534_reg_4029_pp0_iter2_reg; +reg [15:0] sub_ln703_534_reg_4029_pp0_iter3_reg; +reg [15:0] sub_ln703_534_reg_4029_pp0_iter4_reg; +wire [15:0] add_ln703_539_fu_260_p2; +reg [15:0] add_ln703_539_reg_4035; +reg [15:0] add_ln703_539_reg_4035_pp0_iter2_reg; +reg [15:0] add_ln703_539_reg_4035_pp0_iter3_reg; +wire [15:0] sub_ln703_533_fu_264_p2; +reg [15:0] sub_ln703_533_reg_4042; +reg [15:0] sub_ln703_533_reg_4042_pp0_iter3_reg; +reg [15:0] sub_ln703_533_reg_4042_pp0_iter4_reg; +wire [15:0] sub_ln703_538_fu_268_p2; +reg [15:0] sub_ln703_538_reg_4048; +reg [15:0] sub_ln703_538_reg_4048_pp0_iter3_reg; +reg [15:0] sub_ln703_538_reg_4048_pp0_iter4_reg; +reg [15:0] sub_ln703_538_reg_4048_pp0_iter5_reg; +wire [15:0] add_ln703_543_fu_272_p2; +reg [15:0] add_ln703_543_reg_4054; +reg [15:0] add_ln703_543_reg_4054_pp0_iter3_reg; +reg [15:0] add_ln703_543_reg_4054_pp0_iter4_reg; +wire [15:0] sub_ln703_532_fu_276_p2; +reg [15:0] sub_ln703_532_reg_4061; +reg [15:0] sub_ln703_532_reg_4061_pp0_iter4_reg; +wire [15:0] add_ln703_538_fu_280_p2; +reg [15:0] add_ln703_538_reg_4067; +reg [15:0] add_ln703_538_reg_4067_pp0_iter4_reg; +wire [15:0] sub_ln703_535_fu_284_p2; +reg [15:0] sub_ln703_535_reg_4073; +reg [15:0] sub_ln703_535_reg_4073_pp0_iter4_reg; +wire [15:0] add_ln703_540_fu_288_p2; +reg [15:0] add_ln703_540_reg_4079; +reg [15:0] add_ln703_540_reg_4079_pp0_iter4_reg; +wire [15:0] sub_ln703_537_fu_292_p2; +reg [15:0] sub_ln703_537_reg_4085; +reg [15:0] sub_ln703_537_reg_4085_pp0_iter4_reg; +reg [15:0] sub_ln703_537_reg_4085_pp0_iter5_reg; +wire [15:0] sub_ln703_543_fu_296_p2; +reg [15:0] sub_ln703_543_reg_4091; +reg [15:0] sub_ln703_543_reg_4091_pp0_iter4_reg; +wire [15:0] sub_ln703_545_fu_300_p2; +reg [15:0] sub_ln703_545_reg_4097; +reg [15:0] sub_ln703_545_reg_4097_pp0_iter4_reg; +reg [15:0] sub_ln703_545_reg_4097_pp0_iter5_reg; +wire [15:0] add_ln703_549_fu_304_p2; +reg [15:0] add_ln703_549_reg_4103; +reg [15:0] add_ln703_549_reg_4103_pp0_iter4_reg; +reg [15:0] add_ln703_549_reg_4103_pp0_iter5_reg; +wire [15:0] sub_ln703_540_fu_308_p2; +reg [15:0] sub_ln703_540_reg_4110; +reg [15:0] sub_ln703_540_reg_4110_pp0_iter5_reg; +wire [15:0] add_ln703_544_fu_312_p2; +reg [15:0] add_ln703_544_reg_4116; +reg [15:0] add_ln703_544_reg_4116_pp0_iter5_reg; +wire [15:0] sub_ln703_544_fu_316_p2; +reg [15:0] sub_ln703_544_reg_4122; +reg [15:0] sub_ln703_544_reg_4122_pp0_iter5_reg; +wire [15:0] add_ln703_547_fu_320_p2; +reg [15:0] add_ln703_547_reg_4128; +wire [15:0] add_ln703_554_fu_324_p2; +reg [15:0] add_ln703_554_reg_4134; +reg [15:0] add_ln703_554_reg_4134_pp0_iter5_reg; +wire [15:0] sub_ln703_558_fu_328_p2; +reg [15:0] sub_ln703_558_reg_4140; +reg [15:0] sub_ln703_558_reg_4140_pp0_iter5_reg; +wire [15:0] add_ln703_559_fu_332_p2; +reg [15:0] add_ln703_559_reg_4146; +reg [15:0] add_ln703_559_reg_4146_pp0_iter5_reg; +wire [15:0] add_ln703_560_fu_336_p2; +reg [15:0] add_ln703_560_reg_4153; +reg [15:0] add_ln703_560_reg_4153_pp0_iter5_reg; +wire [15:0] sub_ln703_536_fu_340_p2; +reg [15:0] sub_ln703_536_reg_4159; +wire [15:0] sub_ln703_539_fu_344_p2; +reg [15:0] sub_ln703_539_reg_4165; +wire [15:0] add_ln703_541_fu_348_p2; +reg [15:0] add_ln703_541_reg_4171; +wire [15:0] add_ln703_542_fu_352_p2; +reg [15:0] add_ln703_542_reg_4177; +wire [15:0] add_ln703_545_fu_364_p2; +reg [15:0] add_ln703_545_reg_4183; +wire [15:0] add_ln703_548_fu_368_p2; +reg [15:0] add_ln703_548_reg_4188; +wire [15:0] sub_ln703_549_fu_372_p2; +reg [15:0] sub_ln703_549_reg_4194; +wire [15:0] sub_ln703_550_fu_376_p2; +reg [15:0] sub_ln703_550_reg_4200; +wire [15:0] sub_ln703_551_fu_380_p2; +reg [15:0] sub_ln703_551_reg_4205; +wire [15:0] add_ln703_550_fu_384_p2; +reg [15:0] add_ln703_550_reg_4211; +wire [15:0] sub_ln703_552_fu_388_p2; +reg [15:0] sub_ln703_552_reg_4217; +wire [15:0] add_ln703_551_fu_393_p2; +reg [15:0] add_ln703_551_reg_4222; +wire [15:0] sub_ln703_554_fu_398_p2; +reg [15:0] sub_ln703_554_reg_4228; +wire [15:0] sub_ln703_557_fu_402_p2; +reg [15:0] sub_ln703_557_reg_4234; +wire [15:0] add_ln703_564_fu_406_p2; +reg [15:0] add_ln703_564_reg_4240; +wire [15:0] sub_ln703_570_fu_410_p2; +reg [15:0] sub_ln703_570_reg_4246; +wire [15:0] sub_ln703_576_fu_414_p2; +reg [15:0] sub_ln703_576_reg_4252; +reg [15:0] sub_ln703_576_reg_4252_pp0_iter6_reg; +wire [15:0] add_ln703_566_fu_418_p2; +reg [15:0] add_ln703_566_reg_4258; +reg [15:0] add_ln703_566_reg_4258_pp0_iter6_reg; +wire [15:0] sub_ln703_584_fu_422_p2; +reg [15:0] sub_ln703_584_reg_4264; +reg [15:0] sub_ln703_584_reg_4264_pp0_iter6_reg; +wire [15:0] add_ln703_568_fu_426_p2; +reg [15:0] add_ln703_568_reg_4270; +wire [15:0] sub_ln703_591_fu_430_p2; +reg [15:0] sub_ln703_591_reg_4277; +wire [15:0] add_ln703_597_fu_434_p2; +reg [15:0] add_ln703_597_reg_4282; +reg [15:0] add_ln703_597_reg_4282_pp0_iter6_reg; +wire [15:0] add_ln703_557_fu_488_p2; +reg [15:0] add_ln703_557_reg_4293; +wire [15:0] add_ln703_558_fu_498_p2; +reg [15:0] add_ln703_558_reg_4298; +wire [15:0] sub_ln703_567_fu_540_p2; +reg [15:0] sub_ln703_567_reg_4303; +wire [15:0] sub_ln703_572_fu_563_p2; +reg [15:0] sub_ln703_572_reg_4309; +wire [15:0] sub_ln703_574_fu_572_p2; +reg [15:0] sub_ln703_574_reg_4314; +wire [15:0] sub_ln703_578_fu_585_p2; +reg [15:0] sub_ln703_578_reg_4319; +wire [15:0] sub_ln703_579_fu_590_p2; +reg [15:0] sub_ln703_579_reg_4324; +wire [15:0] sub_ln703_582_fu_599_p2; +reg [15:0] sub_ln703_582_reg_4329; +wire [15:0] sub_ln703_585_fu_609_p2; +reg [15:0] sub_ln703_585_reg_4334; +wire [15:0] sub_ln703_586_fu_614_p2; +reg [15:0] sub_ln703_586_reg_4340; +wire [15:0] sub_ln703_587_fu_619_p2; +reg [15:0] sub_ln703_587_reg_4345; +wire [15:0] sub_ln703_588_fu_624_p2; +reg [15:0] sub_ln703_588_reg_4350; +wire [15:0] sub_ln703_589_fu_638_p2; +reg [15:0] sub_ln703_589_reg_4355; +wire [15:0] sub_ln703_590_fu_643_p2; +reg [15:0] sub_ln703_590_reg_4361; +wire [15:0] sub_ln703_592_fu_653_p2; +reg [15:0] sub_ln703_592_reg_4366; +wire [15:0] add_ln703_571_fu_657_p2; +reg [15:0] add_ln703_571_reg_4372; +wire [15:0] sub_ln703_594_fu_666_p2; +reg [15:0] sub_ln703_594_reg_4377; +wire [15:0] add_ln703_572_fu_670_p2; +reg [15:0] add_ln703_572_reg_4382; +wire [15:0] add_ln703_573_fu_675_p2; +reg [15:0] add_ln703_573_reg_4387; +wire [15:0] add_ln703_574_fu_679_p2; +reg [15:0] add_ln703_574_reg_4393; +wire [15:0] sub_ln703_596_fu_683_p2; +reg [15:0] sub_ln703_596_reg_4398; +wire [15:0] sub_ln703_599_fu_693_p2; +reg [15:0] sub_ln703_599_reg_4403; +wire [15:0] add_ln703_576_fu_702_p2; +reg [15:0] add_ln703_576_reg_4408; +wire [15:0] add_ln703_577_fu_707_p2; +reg [15:0] add_ln703_577_reg_4413; +wire [15:0] add_ln703_579_fu_716_p2; +reg [15:0] add_ln703_579_reg_4418; +wire [15:0] sub_ln703_605_fu_720_p2; +reg [15:0] sub_ln703_605_reg_4423; +wire [15:0] sub_ln703_608_fu_725_p2; +reg [15:0] sub_ln703_608_reg_4428; +wire [15:0] add_ln703_580_fu_730_p2; +reg [15:0] add_ln703_580_reg_4433; +wire [15:0] sub_ln703_610_fu_734_p2; +reg [15:0] sub_ln703_610_reg_4439; +wire [15:0] sub_ln703_611_fu_739_p2; +reg [15:0] sub_ln703_611_reg_4444; +wire [15:0] add_ln703_583_fu_754_p2; +reg [15:0] add_ln703_583_reg_4450; +wire [15:0] sub_ln703_613_fu_758_p2; +reg [15:0] sub_ln703_613_reg_4455; +wire [15:0] sub_ln703_617_fu_763_p2; +reg [15:0] sub_ln703_617_reg_4460; +wire [15:0] sub_ln703_620_fu_772_p2; +reg [15:0] sub_ln703_620_reg_4466; +wire [15:0] add_ln703_587_fu_786_p2; +reg [15:0] add_ln703_587_reg_4471; +wire [15:0] add_ln703_588_fu_792_p2; +reg [15:0] add_ln703_588_reg_4476; +wire [15:0] add_ln703_590_fu_801_p2; +reg [15:0] add_ln703_590_reg_4481; +wire [15:0] sub_ln703_627_fu_807_p2; +reg [15:0] sub_ln703_627_reg_4486; +wire [15:0] sub_ln703_632_fu_818_p2; +reg [15:0] sub_ln703_632_reg_4491; +wire [15:0] sub_ln703_641_fu_838_p2; +reg [15:0] sub_ln703_641_reg_4496; +wire [15:0] sub_ln703_645_fu_843_p2; +reg [15:0] sub_ln703_645_reg_4501; +wire [15:0] sub_ln703_660_fu_872_p2; +reg [15:0] sub_ln703_660_reg_4506; +wire [15:0] sub_ln703_661_fu_877_p2; +reg [15:0] sub_ln703_661_reg_4511; +wire [15:0] sub_ln703_662_fu_882_p2; +reg [15:0] sub_ln703_662_reg_4516; +wire [15:0] add_ln703_611_fu_887_p2; +reg [15:0] add_ln703_611_reg_4521; +wire [15:0] add_ln703_620_fu_891_p2; +reg [15:0] add_ln703_620_reg_4537; +wire [15:0] sub_ln703_671_fu_896_p2; +reg [15:0] sub_ln703_671_reg_4543; +wire [15:0] sub_ln703_676_fu_901_p2; +reg [15:0] sub_ln703_676_reg_4548; +wire [15:0] add_ln703_637_fu_906_p2; +reg [15:0] add_ln703_637_reg_4553; +wire [15:0] add_ln703_655_fu_910_p2; +reg [15:0] add_ln703_655_reg_4558; +wire [15:0] add_ln703_659_fu_914_p2; +reg [15:0] add_ln703_659_reg_4568; +wire [15:0] add_ln703_692_fu_920_p2; +reg [15:0] add_ln703_692_reg_4573; +reg [15:0] add_ln703_692_reg_4573_pp0_iter7_reg; +wire [15:0] add_ln703_631_fu_1397_p2; +reg [15:0] add_ln703_631_reg_4588; +wire [15:0] add_ln703_634_fu_1416_p2; +reg [15:0] add_ln703_634_reg_4593; +wire [15:0] sub_ln703_692_fu_1433_p2; +reg [15:0] sub_ln703_692_reg_4598; +wire [15:0] sub_ln703_693_fu_1438_p2; +reg [15:0] sub_ln703_693_reg_4603; +wire [15:0] add_ln703_639_fu_1459_p2; +reg [15:0] add_ln703_639_reg_4608; +wire [15:0] sub_ln703_695_fu_1464_p2; +reg [15:0] sub_ln703_695_reg_4613; +wire [15:0] sub_ln703_699_fu_1495_p2; +reg [15:0] sub_ln703_699_reg_4618; +wire [15:0] sub_ln703_700_fu_1500_p2; +reg [15:0] sub_ln703_700_reg_4623; +wire [15:0] add_ln703_642_fu_1505_p2; +reg [15:0] add_ln703_642_reg_4628; +wire [15:0] sub_ln703_701_fu_1509_p2; +reg [15:0] sub_ln703_701_reg_4633; +wire [15:0] sub_ln703_702_fu_1514_p2; +reg [15:0] sub_ln703_702_reg_4638; +wire [15:0] sub_ln703_704_fu_1524_p2; +reg [15:0] sub_ln703_704_reg_4643; +wire [15:0] add_ln703_645_fu_1538_p2; +reg [15:0] add_ln703_645_reg_4648; +wire [15:0] sub_ln703_706_fu_1548_p2; +reg [15:0] sub_ln703_706_reg_4653; +wire [15:0] add_ln703_646_fu_1553_p2; +reg [15:0] add_ln703_646_reg_4658; +wire [15:0] sub_ln703_707_fu_1559_p2; +reg [15:0] sub_ln703_707_reg_4663; +wire [15:0] sub_ln703_708_fu_1564_p2; +reg [15:0] sub_ln703_708_reg_4668; +wire [15:0] sub_ln703_709_fu_1569_p2; +reg [15:0] sub_ln703_709_reg_4673; +wire [15:0] sub_ln703_710_fu_1606_p2; +reg [15:0] sub_ln703_710_reg_4678; +wire [15:0] sub_ln703_711_fu_1611_p2; +reg [15:0] sub_ln703_711_reg_4683; +wire [15:0] sub_ln703_712_fu_1616_p2; +reg [15:0] sub_ln703_712_reg_4688; +wire [15:0] sub_ln703_714_fu_1626_p2; +reg [15:0] sub_ln703_714_reg_4693; +wire [15:0] sub_ln703_715_fu_1631_p2; +reg [15:0] sub_ln703_715_reg_4698; +wire [15:0] sub_ln703_716_fu_1636_p2; +reg [15:0] sub_ln703_716_reg_4703; +wire [15:0] sub_ln703_718_fu_1646_p2; +reg [15:0] sub_ln703_718_reg_4708; +wire [15:0] sub_ln703_720_fu_1676_p2; +reg [15:0] sub_ln703_720_reg_4713; +wire [15:0] sub_ln703_722_fu_1681_p2; +reg [15:0] sub_ln703_722_reg_4718; +wire [15:0] sub_ln703_724_fu_1686_p2; +reg [15:0] sub_ln703_724_reg_4723; +wire [15:0] sub_ln703_725_fu_1691_p2; +reg [15:0] sub_ln703_725_reg_4728; +wire [15:0] add_ln703_658_fu_1696_p2; +reg [15:0] add_ln703_658_reg_4733; +wire [15:0] sub_ln703_727_fu_1701_p2; +reg [15:0] sub_ln703_727_reg_4738; +wire [15:0] add_ln703_661_fu_1710_p2; +reg [15:0] add_ln703_661_reg_4744; +wire [15:0] sub_ln703_729_fu_1715_p2; +reg [15:0] sub_ln703_729_reg_4749; +wire [15:0] sub_ln703_730_fu_1720_p2; +reg [15:0] sub_ln703_730_reg_4754; +wire [15:0] sub_ln703_731_fu_1725_p2; +reg [15:0] sub_ln703_731_reg_4759; +wire [15:0] add_ln703_663_fu_1735_p2; +reg [15:0] add_ln703_663_reg_4764; +wire [15:0] sub_ln703_732_fu_1741_p2; +reg [15:0] sub_ln703_732_reg_4769; +wire [15:0] sub_ln703_738_fu_1757_p2; +reg [15:0] sub_ln703_738_reg_4774; +wire [15:0] sub_ln703_742_fu_1762_p2; +reg [15:0] sub_ln703_742_reg_4779; +wire [15:0] add_ln703_667_fu_1767_p2; +reg [15:0] add_ln703_667_reg_4784; +wire [15:0] sub_ln703_743_fu_1772_p2; +reg [15:0] sub_ln703_743_reg_4789; +wire [15:0] sub_ln703_744_fu_1777_p2; +reg [15:0] sub_ln703_744_reg_4794; +wire [15:0] sub_ln703_745_fu_1782_p2; +reg [15:0] sub_ln703_745_reg_4799; +wire [15:0] add_ln703_669_fu_1787_p2; +reg [15:0] add_ln703_669_reg_4804; +wire [15:0] sub_ln703_748_fu_1792_p2; +reg [15:0] sub_ln703_748_reg_4809; +wire [15:0] sub_ln703_751_fu_1797_p2; +reg [15:0] sub_ln703_751_reg_4814; +wire [15:0] add_ln703_670_fu_1802_p2; +reg [15:0] add_ln703_670_reg_4819; +wire [15:0] sub_ln703_752_fu_1807_p2; +reg [15:0] sub_ln703_752_reg_4824; +wire [15:0] add_ln703_672_fu_1812_p2; +reg [15:0] add_ln703_672_reg_4829; +wire [15:0] sub_ln703_753_fu_1817_p2; +reg [15:0] sub_ln703_753_reg_4834; +wire [15:0] add_ln703_674_fu_1822_p2; +reg [15:0] add_ln703_674_reg_4839; +wire [15:0] add_ln703_679_fu_1826_p2; +reg [15:0] add_ln703_679_reg_4847; +wire [15:0] sub_ln703_765_fu_1832_p2; +reg [15:0] sub_ln703_765_reg_4852; +wire [15:0] add_ln703_687_fu_1847_p2; +reg [15:0] add_ln703_687_reg_4857; +wire [15:0] add_ln703_688_fu_1853_p2; +reg [15:0] add_ln703_688_reg_4862; +wire [15:0] add_ln703_707_fu_1877_p2; +reg [15:0] add_ln703_707_reg_4867; +wire [15:0] add_ln703_711_fu_1887_p2; +reg [15:0] add_ln703_711_reg_4872; +wire [15:0] add_ln703_716_fu_1902_p2; +reg [15:0] add_ln703_716_reg_4877; +wire [15:0] add_ln703_722_fu_1913_p2; +reg [15:0] add_ln703_722_reg_4882; +wire [15:0] add_ln703_724_fu_1923_p2; +reg [15:0] add_ln703_724_reg_4887; +wire [15:0] add_ln703_727_fu_1934_p2; +reg [15:0] add_ln703_727_reg_4892; +wire [15:0] add_ln703_729_fu_1945_p2; +reg [15:0] add_ln703_729_reg_4897; +wire [15:0] add_ln703_732_fu_1956_p2; +reg [15:0] add_ln703_732_reg_4902; +wire [15:0] add_ln703_737_fu_1962_p2; +reg [15:0] add_ln703_737_reg_4907; +wire [15:0] add_ln703_739_fu_1966_p2; +reg [15:0] add_ln703_739_reg_4915; +wire [15:0] add_ln703_751_fu_1971_p2; +reg [15:0] add_ln703_751_reg_4920; +wire ap_block_pp0_stage0; +wire [15:0] sub_ln703_541_fu_356_p2; +wire [15:0] sub_ln703_542_fu_360_p2; +wire [15:0] add_ln703_546_fu_438_p2; +wire [15:0] sub_ln703_546_fu_442_p2; +wire [15:0] sub_ln703_547_fu_446_p2; +wire [15:0] sub_ln703_548_fu_450_p2; +wire [15:0] add_ln703_552_fu_454_p2; +wire [15:0] add_ln703_553_fu_458_p2; +wire [15:0] sub_ln703_553_fu_462_p2; +wire [15:0] add_ln703_555_fu_466_p2; +wire [15:0] sub_ln703_555_fu_470_p2; +wire [15:0] sub_ln703_556_fu_474_p2; +wire [15:0] add_ln703_556_fu_478_p2; +wire [15:0] sub_ln703_559_fu_483_p2; +wire [15:0] sub_ln703_560_fu_493_p2; +wire [15:0] sub_ln703_561_fu_502_p2; +wire [15:0] sub_ln703_562_fu_506_p2; +wire [15:0] add_ln703_561_fu_510_p2; +wire [15:0] add_ln703_562_fu_522_p2; +wire [15:0] add_ln703_567_fu_629_p2; +wire [15:0] add_ln703_563_fu_526_p2; +wire [15:0] sub_ln703_565_fu_530_p2; +wire [15:0] sub_ln703_566_fu_535_p2; +wire [15:0] sub_ln703_568_fu_545_p2; +wire [15:0] sub_ln703_569_fu_549_p2; +wire [15:0] add_ln703_565_fu_554_p2; +wire [15:0] sub_ln703_571_fu_558_p2; +wire [15:0] sub_ln703_573_fu_567_p2; +wire [15:0] sub_ln703_575_fu_577_p2; +wire [15:0] sub_ln703_577_fu_581_p2; +wire [15:0] sub_ln703_580_fu_594_p2; +wire [15:0] sub_ln703_583_fu_604_p2; +wire [15:0] sub_ln703_564_fu_518_p2; +wire [15:0] add_ln703_581_fu_744_p2; +wire [15:0] add_ln703_569_fu_633_p2; +wire [15:0] add_ln703_570_fu_648_p2; +wire [15:0] sub_ln703_593_fu_661_p2; +wire [15:0] add_ln703_585_fu_777_p2; +wire [15:0] add_ln703_586_fu_781_p2; +wire [15:0] sub_ln703_597_fu_688_p2; +wire [15:0] add_ln703_589_fu_797_p2; +wire [15:0] add_ln703_575_fu_698_p2; +wire [15:0] sub_ln703_602_fu_712_p2; +wire [15:0] add_ln703_595_fu_828_p2; +wire [15:0] add_ln703_582_fu_748_p2; +wire [15:0] sub_ln703_618_fu_768_p2; +wire [15:0] add_ln703_600_fu_848_p2; +wire [15:0] add_ln703_601_fu_852_p2; +wire [15:0] add_ln703_605_fu_862_p2; +wire [15:0] add_ln703_593_fu_812_p2; +wire [15:0] add_ln703_594_fu_823_p2; +wire [15:0] add_ln703_596_fu_832_p2; +wire [15:0] add_ln703_602_fu_856_p2; +wire [15:0] add_ln703_606_fu_866_p2; +wire [15:0] sub_ln703_563_fu_514_p2; +wire [15:0] sub_ln703_581_fu_924_p2; +wire [15:0] sub_ln703_595_fu_928_p2; +wire [15:0] sub_ln703_600_fu_936_p2; +wire [15:0] add_ln703_578_fu_944_p2; +wire [15:0] sub_ln703_607_fu_961_p2; +wire [15:0] sub_ln703_609_fu_965_p2; +wire [15:0] sub_ln703_612_fu_969_p2; +wire [15:0] add_ln703_584_fu_985_p2; +wire [15:0] sub_ln703_621_fu_993_p2; +wire [15:0] sub_ln703_623_fu_1002_p2; +wire [15:0] sub_ln703_624_fu_1006_p2; +wire [15:0] sub_ln703_625_fu_1010_p2; +wire [15:0] sub_ln703_598_fu_932_p2; +wire [15:0] add_ln703_591_fu_1027_p2; +wire [15:0] add_ln703_592_fu_1031_p2; +wire [15:0] sub_ln703_630_fu_1035_p2; +wire [15:0] sub_ln703_631_fu_1039_p2; +wire [15:0] add_ln703_598_fu_1052_p2; +wire [15:0] sub_ln703_604_fu_952_p2; +wire [15:0] sub_ln703_635_fu_1056_p2; +wire [15:0] sub_ln703_637_fu_1065_p2; +wire [15:0] sub_ln703_638_fu_1069_p2; +wire [15:0] add_ln703_599_fu_1073_p2; +wire [15:0] sub_ln703_639_fu_1078_p2; +wire [15:0] sub_ln703_643_fu_1091_p2; +wire [15:0] sub_ln703_644_fu_1095_p2; +wire [15:0] sub_ln703_615_fu_977_p2; +wire [15:0] sub_ln703_616_fu_981_p2; +wire [15:0] sub_ln703_646_fu_1099_p2; +wire [15:0] sub_ln703_636_fu_1060_p2; +wire [15:0] sub_ln703_647_fu_1104_p2; +wire [15:0] sub_ln703_648_fu_1108_p2; +wire [15:0] sub_ln703_649_fu_1113_p2; +wire [15:0] sub_ln703_651_fu_1122_p2; +wire [15:0] sub_ln703_652_fu_1127_p2; +wire [15:0] add_ln703_603_fu_1132_p2; +wire [15:0] sub_ln703_653_fu_1136_p2; +wire [15:0] add_ln703_604_fu_1140_p2; +wire [15:0] sub_ln703_655_fu_1149_p2; +wire [15:0] sub_ln703_629_fu_1022_p2; +wire [15:0] sub_ln703_656_fu_1153_p2; +wire [15:0] add_ln703_626_fu_1321_p2; +wire [15:0] sub_ln703_657_fu_1158_p2; +wire [15:0] add_ln703_607_fu_1163_p2; +wire [15:0] sub_ln703_658_fu_1167_p2; +wire [15:0] sub_ln703_659_fu_1171_p2; +wire [15:0] sub_ln703_601_fu_940_p2; +wire [15:0] add_ln703_628_fu_1350_p2; +wire [15:0] add_ln703_608_fu_1176_p2; +wire [15:0] add_ln703_609_fu_1181_p2; +wire [15:0] add_ln703_610_fu_1185_p2; +wire [15:0] sub_ln703_634_fu_1048_p2; +wire [15:0] sub_ln703_663_fu_1189_p2; +wire [15:0] add_ln703_612_fu_1194_p2; +wire [15:0] sub_ln703_664_fu_1199_p2; +wire [15:0] sub_ln703_606_fu_956_p2; +wire [15:0] add_ln703_632_fu_1407_p2; +wire [15:0] add_ln703_633_fu_1412_p2; +wire [15:0] sub_ln703_665_fu_1204_p2; +wire [15:0] add_ln703_613_fu_1209_p2; +wire [15:0] sub_ln703_666_fu_1214_p2; +wire [15:0] add_ln703_614_fu_1219_p2; +wire [15:0] sub_ln703_640_fu_1082_p2; +wire [15:0] add_ln703_638_fu_1454_p2; +wire [15:0] sub_ln703_667_fu_1224_p2; +wire [15:0] sub_ln703_642_fu_1086_p2; +wire [15:0] add_ln703_615_fu_1228_p2; +wire [15:0] sub_ln703_668_fu_1233_p2; +wire [15:0] add_ln703_616_fu_1238_p2; +wire [15:0] add_ln703_617_fu_1243_p2; +wire [15:0] add_ln703_618_fu_1248_p2; +wire [15:0] add_ln703_619_fu_1252_p2; +wire [15:0] add_ln703_621_fu_1256_p2; +wire [15:0] sub_ln703_669_fu_1261_p2; +wire [15:0] sub_ln703_670_fu_1266_p2; +wire [15:0] add_ln703_622_fu_1271_p2; +wire [15:0] add_ln703_643_fu_1529_p2; +wire [15:0] add_ln703_644_fu_1533_p2; +wire [15:0] add_ln703_623_fu_1276_p2; +wire [15:0] sub_ln703_650_fu_1118_p2; +wire [15:0] sub_ln703_672_fu_1281_p2; +wire [15:0] add_ln703_624_fu_1286_p2; +wire [15:0] sub_ln703_674_fu_1296_p2; +wire [15:0] sub_ln703_626_fu_1014_p2; +wire [15:0] add_ln703_648_fu_1579_p2; +wire [15:0] sub_ln703_677_fu_1306_p2; +wire [15:0] sub_ln703_628_fu_1018_p2; +wire [15:0] add_ln703_651_fu_1595_p2; +wire [15:0] add_ln703_625_fu_1311_p2; +wire [15:0] sub_ln703_678_fu_1316_p2; +wire [15:0] add_ln703_627_fu_1325_p2; +wire [15:0] sub_ln703_681_fu_1340_p2; +wire [15:0] sub_ln703_682_fu_1345_p2; +wire [15:0] add_ln703_629_fu_1355_p2; +wire [15:0] sub_ln703_683_fu_1360_p2; +wire [15:0] sub_ln703_684_fu_1365_p2; +wire [15:0] sub_ln703_686_fu_1374_p2; +wire [15:0] sub_ln703_687_fu_1378_p2; +wire [15:0] add_ln703_630_fu_1387_p2; +wire [15:0] sub_ln703_603_fu_948_p2; +wire [15:0] add_ln703_654_fu_1661_p2; +wire [15:0] add_ln703_656_fu_1666_p2; +wire [15:0] sub_ln703_689_fu_1392_p2; +wire [15:0] sub_ln703_690_fu_1402_p2; +wire [15:0] add_ln703_635_fu_1422_p2; +wire [15:0] sub_ln703_691_fu_1428_p2; +wire [15:0] sub_ln703_694_fu_1443_p2; +wire [15:0] add_ln703_636_fu_1448_p2; +wire [15:0] add_ln703_660_fu_1706_p2; +wire [15:0] add_ln703_640_fu_1469_p2; +wire [15:0] sub_ln703_696_fu_1475_p2; +wire [15:0] add_ln703_641_fu_1480_p2; +wire [15:0] sub_ln703_614_fu_973_p2; +wire [15:0] add_ln703_662_fu_1730_p2; +wire [15:0] sub_ln703_697_fu_1485_p2; +wire [15:0] sub_ln703_619_fu_989_p2; +wire [15:0] add_ln703_665_fu_1746_p2; +wire [15:0] sub_ln703_705_fu_1544_p2; +wire [15:0] add_ln703_647_fu_1574_p2; +wire [15:0] sub_ln703_675_fu_1301_p2; +wire [15:0] add_ln703_649_fu_1584_p2; +wire [15:0] add_ln703_650_fu_1590_p2; +wire [15:0] add_ln703_652_fu_1600_p2; +wire [15:0] sub_ln703_680_fu_1335_p2; +wire [15:0] sub_ln703_713_fu_1621_p2; +wire [15:0] sub_ln703_717_fu_1641_p2; +wire [15:0] sub_ln703_685_fu_1370_p2; +wire [15:0] add_ln703_653_fu_1651_p2; +wire [15:0] sub_ln703_719_fu_1656_p2; +wire [15:0] add_ln703_657_fu_1670_p2; +wire [15:0] sub_ln703_698_fu_1490_p2; +wire [15:0] add_ln703_666_fu_1751_p2; +wire [15:0] sub_ln703_654_fu_1145_p2; +wire [15:0] add_ln703_685_fu_1837_p2; +wire [15:0] add_ln703_686_fu_1842_p2; +wire [15:0] sub_ln703_679_fu_1330_p2; +wire [15:0] add_ln703_703_fu_1858_p2; +wire [15:0] add_ln703_705_fu_1867_p2; +wire [15:0] add_ln703_704_fu_1862_p2; +wire [15:0] add_ln703_706_fu_1871_p2; +wire [15:0] add_ln703_710_fu_1883_p2; +wire [15:0] sub_ln703_622_fu_997_p2; +wire [15:0] add_ln703_714_fu_1893_p2; +wire [15:0] add_ln703_715_fu_1898_p2; +wire [15:0] sub_ln703_673_fu_1291_p2; +wire [15:0] add_ln703_721_fu_1908_p2; +wire [15:0] add_ln703_723_fu_1919_p2; +wire [15:0] add_ln703_726_fu_1929_p2; +wire [15:0] sub_ln703_633_fu_1043_p2; +wire [15:0] add_ln703_728_fu_1940_p2; +wire [15:0] sub_ln703_688_fu_1382_p2; +wire [15:0] add_ln703_731_fu_1951_p2; +wire [15:0] sub_ln703_703_fu_1519_p2; +wire [15:0] sub_ln703_723_fu_1979_p2; +wire [15:0] sub_ln703_726_fu_1983_p2; +wire [15:0] add_ln703_664_fu_1991_p2; +wire [15:0] sub_ln703_736_fu_2007_p2; +wire [15:0] sub_ln703_739_fu_2015_p2; +wire [15:0] sub_ln703_740_fu_2019_p2; +wire [15:0] sub_ln703_741_fu_2023_p2; +wire [15:0] sub_ln703_746_fu_2027_p2; +wire [15:0] sub_ln703_747_fu_2031_p2; +wire [15:0] add_ln703_668_fu_2035_p2; +wire [15:0] sub_ln703_749_fu_2039_p2; +wire [15:0] sub_ln703_750_fu_2043_p2; +wire [15:0] add_ln703_671_fu_2047_p2; +wire [15:0] sub_ln703_754_fu_2051_p2; +wire [15:0] sub_ln703_721_fu_1975_p2; +wire [15:0] sub_ln703_755_fu_2055_p2; +wire [15:0] sub_ln703_757_fu_2064_p2; +wire [15:0] add_ln703_673_fu_2068_p2; +wire [15:0] add_ln703_675_fu_2072_p2; +wire [15:0] sub_ln703_758_fu_2076_p2; +wire [15:0] sub_ln703_759_fu_2081_p2; +wire [15:0] sub_ln703_728_fu_1987_p2; +wire [15:0] sub_ln703_761_fu_2089_p2; +wire [15:0] add_ln703_676_fu_2093_p2; +wire [15:0] sub_ln703_762_fu_2097_p2; +wire [15:0] add_ln703_677_fu_2101_p2; +wire [15:0] sub_ln703_763_fu_2105_p2; +wire [15:0] add_ln703_678_fu_2109_p2; +wire [15:0] sub_ln703_733_fu_1995_p2; +wire [15:0] sub_ln703_734_fu_1999_p2; +wire [15:0] sub_ln703_735_fu_2003_p2; +wire [15:0] add_ln703_680_fu_2118_p2; +wire [15:0] add_ln703_708_fu_2323_p2; +wire [15:0] sub_ln703_737_fu_2011_p2; +wire [15:0] sub_ln703_766_fu_2123_p2; +wire [15:0] add_ln703_717_fu_2342_p2; +wire [15:0] add_ln703_681_fu_2132_p2; +wire [15:0] add_ln703_682_fu_2136_p2; +wire [15:0] add_ln703_719_fu_2361_p2; +wire [15:0] add_ln703_683_fu_2146_p2; +wire [15:0] sub_ln703_769_fu_2150_p2; +wire [15:0] add_ln703_684_fu_2154_p2; +wire [15:0] sub_ln703_770_fu_2158_p2; +wire [15:0] sub_ln703_771_fu_2162_p2; +wire [15:0] add_ln703_689_fu_2181_p2; +wire [15:0] sub_ln703_775_fu_2185_p2; +wire [15:0] add_ln703_690_fu_2189_p2; +wire [15:0] add_ln703_691_fu_2193_p2; +wire [15:0] sub_ln703_778_fu_2207_p2; +wire [15:0] sub_ln703_779_fu_2211_p2; +wire [15:0] sub_ln703_780_fu_2215_p2; +wire [15:0] sub_ln703_781_fu_2220_p2; +wire [15:0] sub_ln703_782_fu_2224_p2; +wire [15:0] add_ln703_693_fu_2229_p2; +wire [15:0] add_ln703_694_fu_2234_p2; +wire [15:0] add_ln703_695_fu_2239_p2; +wire [15:0] sub_ln703_783_fu_2244_p2; +wire [15:0] sub_ln703_784_fu_2249_p2; +wire [15:0] sub_ln703_786_fu_2259_p2; +wire [15:0] add_ln703_696_fu_2264_p2; +wire [15:0] add_ln703_697_fu_2269_p2; +wire [15:0] sub_ln703_787_fu_2274_p2; +wire [15:0] add_ln703_698_fu_2279_p2; +wire [15:0] sub_ln703_788_fu_2284_p2; +wire [15:0] add_ln703_699_fu_2289_p2; +wire [15:0] sub_ln703_789_fu_2294_p2; +wire [15:0] add_ln703_700_fu_2303_p2; +wire [15:0] add_ln703_701_fu_2308_p2; +wire [15:0] add_ln703_702_fu_2313_p2; +wire [15:0] add_ln703_740_fu_2532_p2; +wire [15:0] add_ln703_709_fu_2327_p2; +wire [15:0] add_ln703_712_fu_2332_p2; +wire [15:0] add_ln703_713_fu_2337_p2; +wire [15:0] add_ln703_718_fu_2346_p2; +wire [15:0] sub_ln703_792_fu_2351_p2; +wire [15:0] add_ln703_720_fu_2365_p2; +wire [15:0] sub_ln703_768_fu_2141_p2; +wire [15:0] sub_ln703_794_fu_2370_p2; +wire [15:0] sub_ln703_795_fu_2375_p2; +wire [15:0] sub_ln703_796_fu_2380_p2; +wire [15:0] add_ln703_725_fu_2389_p2; +wire [15:0] sub_ln703_798_fu_2394_p2; +wire [15:0] sub_ln703_799_fu_2399_p2; +wire [15:0] sub_ln703_800_fu_2404_p2; +wire [15:0] sub_ln703_801_fu_2409_p2; +wire [15:0] sub_ln703_802_fu_2414_p2; +wire [15:0] sub_ln703_776_fu_2197_p2; +wire [15:0] sub_ln703_803_fu_2419_p2; +wire [15:0] add_ln703_730_fu_2424_p2; +wire [15:0] add_ln703_733_fu_2434_p2; +wire [15:0] add_ln703_750_fu_2669_p2; +wire [15:0] sub_ln703_805_fu_2439_p2; +wire [15:0] sub_ln703_806_fu_2444_p2; +wire [15:0] sub_ln703_807_fu_2449_p2; +wire [15:0] sub_ln703_756_fu_2059_p2; +wire [15:0] add_ln703_754_fu_2693_p2; +wire [15:0] sub_ln703_808_fu_2454_p2; +wire [15:0] sub_ln703_809_fu_2459_p2; +wire [15:0] sub_ln703_810_fu_2464_p2; +wire [15:0] sub_ln703_785_fu_2254_p2; +wire [15:0] add_ln703_734_fu_2469_p2; +wire [15:0] sub_ln703_760_fu_2085_p2; +wire [15:0] add_ln703_758_fu_2728_p2; +wire [15:0] sub_ln703_811_fu_2474_p2; +wire [15:0] sub_ln703_812_fu_2479_p2; +wire [15:0] add_ln703_735_fu_2484_p2; +wire [15:0] sub_ln703_813_fu_2489_p2; +wire [15:0] sub_ln703_814_fu_2494_p2; +wire [15:0] add_ln703_761_fu_2763_p2; +wire [15:0] add_ln703_762_fu_2767_p2; +wire [15:0] sub_ln703_815_fu_2499_p2; +wire [15:0] add_ln703_736_fu_2504_p2; +wire [15:0] sub_ln703_790_fu_2299_p2; +wire [15:0] sub_ln703_764_fu_2113_p2; +wire [15:0] add_ln703_765_fu_2792_p2; +wire [15:0] sub_ln703_816_fu_2509_p2; +wire [15:0] sub_ln703_817_fu_2514_p2; +wire [15:0] sub_ln703_818_fu_2519_p2; +wire [15:0] sub_ln703_819_fu_2524_p2; +wire [15:0] sub_ln703_791_fu_2318_p2; +wire [15:0] add_ln703_738_fu_2528_p2; +wire [15:0] add_ln703_741_fu_2536_p2; +wire [15:0] sub_ln703_820_fu_2541_p2; +wire [15:0] sub_ln703_821_fu_2546_p2; +wire [15:0] sub_ln703_822_fu_2550_p2; +wire [15:0] sub_ln703_823_fu_2555_p2; +wire [15:0] sub_ln703_824_fu_2560_p2; +wire [15:0] sub_ln703_825_fu_2564_p2; +wire [15:0] sub_ln703_767_fu_2127_p2; +wire [15:0] add_ln703_770_fu_2867_p2; +wire [15:0] add_ln703_742_fu_2569_p2; +wire [15:0] sub_ln703_793_fu_2356_p2; +wire [15:0] sub_ln703_826_fu_2574_p2; +wire [15:0] sub_ln703_827_fu_2579_p2; +wire [15:0] add_ln703_743_fu_2583_p2; +wire [15:0] sub_ln703_828_fu_2588_p2; +wire [15:0] sub_ln703_829_fu_2593_p2; +wire [15:0] sub_ln703_830_fu_2598_p2; +wire [15:0] sub_ln703_831_fu_2602_p2; +wire [15:0] sub_ln703_797_fu_2385_p2; +wire [15:0] sub_ln703_832_fu_2607_p2; +wire [15:0] add_ln703_744_fu_2612_p2; +wire [15:0] sub_ln703_772_fu_2166_p2; +wire [15:0] add_ln703_776_fu_2937_p2; +wire [15:0] sub_ln703_773_fu_2171_p2; +wire [15:0] add_ln703_778_fu_2947_p2; +wire [15:0] sub_ln703_774_fu_2176_p2; +wire [15:0] add_ln703_780_fu_2957_p2; +wire [15:0] add_ln703_745_fu_2617_p2; +wire [15:0] add_ln703_746_fu_2622_p2; +wire [15:0] add_ln703_747_fu_2627_p2; +wire [15:0] add_ln703_748_fu_2632_p2; +wire [15:0] add_ln703_749_fu_2637_p2; +wire [15:0] sub_ln703_777_fu_2202_p2; +wire [15:0] add_ln703_782_fu_2992_p2; +wire [15:0] sub_ln703_833_fu_2642_p2; +wire [15:0] sub_ln703_834_fu_2646_p2; +wire [15:0] sub_ln703_835_fu_2651_p2; +wire [15:0] sub_ln703_836_fu_2655_p2; +wire [15:0] sub_ln703_804_fu_2429_p2; +wire [15:0] add_ln703_786_fu_3027_p2; +wire [15:0] sub_ln703_837_fu_2660_p2; +wire [15:0] sub_ln703_838_fu_2664_p2; +wire [15:0] add_ln703_752_fu_2673_p2; +wire [15:0] acc_1_V_fu_2678_p2; +wire [15:0] acc_2_V_fu_2683_p2; +wire [15:0] acc_3_V_fu_2688_p2; +wire [15:0] acc_4_V_fu_2698_p2; +wire [15:0] acc_5_V_fu_2703_p2; +wire [15:0] acc_6_V_fu_2708_p2; +wire [15:0] acc_7_V_fu_2713_p2; +wire [15:0] acc_8_V_fu_2718_p2; +wire [15:0] acc_9_V_fu_2723_p2; +wire [15:0] acc_10_V_fu_2733_p2; +wire [15:0] acc_11_V_fu_2738_p2; +wire [15:0] acc_12_V_fu_2743_p2; +wire [15:0] acc_13_V_fu_2748_p2; +wire [15:0] acc_14_V_fu_2753_p2; +wire [15:0] acc_15_V_fu_2758_p2; +wire [15:0] acc_16_V_fu_2771_p2; +wire [15:0] acc_17_V_fu_2777_p2; +wire [15:0] acc_18_V_fu_2782_p2; +wire [15:0] acc_19_V_fu_2787_p2; +wire [15:0] acc_20_V_fu_2797_p2; +wire [15:0] acc_21_V_fu_2802_p2; +wire [15:0] acc_22_V_fu_2807_p2; +wire [15:0] acc_23_V_fu_2812_p2; +wire [15:0] acc_24_V_fu_2817_p2; +wire [15:0] acc_25_V_fu_2822_p2; +wire [15:0] acc_26_V_fu_2827_p2; +wire [15:0] acc_27_V_fu_2832_p2; +wire [15:0] acc_28_V_fu_2837_p2; +wire [15:0] acc_29_V_fu_2842_p2; +wire [15:0] acc_30_V_fu_2847_p2; +wire [15:0] acc_31_V_fu_2852_p2; +wire [15:0] acc_32_V_fu_2857_p2; +wire [15:0] acc_33_V_fu_2862_p2; +wire [15:0] acc_34_V_fu_2872_p2; +wire [15:0] acc_35_V_fu_2877_p2; +wire [15:0] acc_36_V_fu_2882_p2; +wire [15:0] acc_37_V_fu_2887_p2; +wire [15:0] acc_38_V_fu_2892_p2; +wire [15:0] acc_39_V_fu_2897_p2; +wire [15:0] acc_40_V_fu_2902_p2; +wire [15:0] acc_41_V_fu_2907_p2; +wire [15:0] acc_42_V_fu_2912_p2; +wire [15:0] acc_43_V_fu_2917_p2; +wire [15:0] acc_44_V_fu_2922_p2; +wire [15:0] acc_45_V_fu_2927_p2; +wire [15:0] acc_46_V_fu_2932_p2; +wire [15:0] acc_47_V_fu_2942_p2; +wire [15:0] acc_48_V_fu_2952_p2; +wire [15:0] acc_49_V_fu_2962_p2; +wire [15:0] acc_50_V_fu_2967_p2; +wire [15:0] acc_51_V_fu_2972_p2; +wire [15:0] acc_52_V_fu_2977_p2; +wire [15:0] acc_53_V_fu_2982_p2; +wire [15:0] acc_54_V_fu_2987_p2; +wire [15:0] acc_55_V_fu_2997_p2; +wire [15:0] acc_56_V_fu_3002_p2; +wire [15:0] acc_57_V_fu_3007_p2; +wire [15:0] acc_58_V_fu_3012_p2; +wire [15:0] acc_59_V_fu_3017_p2; +wire [15:0] acc_60_V_fu_3022_p2; +wire [15:0] acc_61_V_fu_3031_p2; +wire [15:0] acc_62_V_fu_3037_p2; +wire [15:0] acc_63_V_fu_3042_p2; +reg ap_ce_reg; +reg [255:0] data_V_read_int_reg; +reg [15:0] ap_return_0_int_reg; +reg [15:0] ap_return_1_int_reg; +reg [15:0] ap_return_2_int_reg; +reg [15:0] ap_return_3_int_reg; +reg [15:0] ap_return_4_int_reg; +reg [15:0] ap_return_5_int_reg; +reg [15:0] ap_return_6_int_reg; +reg [15:0] ap_return_7_int_reg; +reg [15:0] ap_return_8_int_reg; +reg [15:0] ap_return_9_int_reg; +reg [15:0] ap_return_10_int_reg; +reg [15:0] ap_return_11_int_reg; +reg [15:0] ap_return_12_int_reg; +reg [15:0] ap_return_13_int_reg; +reg [15:0] ap_return_14_int_reg; +reg [15:0] ap_return_15_int_reg; +reg [15:0] ap_return_16_int_reg; +reg [15:0] ap_return_17_int_reg; +reg [15:0] ap_return_18_int_reg; +reg [15:0] ap_return_19_int_reg; +reg [15:0] ap_return_20_int_reg; +reg [15:0] ap_return_21_int_reg; +reg [15:0] ap_return_22_int_reg; +reg [15:0] ap_return_23_int_reg; +reg [15:0] ap_return_24_int_reg; +reg [15:0] ap_return_25_int_reg; +reg [15:0] ap_return_26_int_reg; +reg [15:0] ap_return_27_int_reg; +reg [15:0] ap_return_28_int_reg; +reg [15:0] ap_return_29_int_reg; +reg [15:0] ap_return_30_int_reg; +reg [15:0] ap_return_31_int_reg; +reg [15:0] ap_return_32_int_reg; +reg [15:0] ap_return_33_int_reg; +reg [15:0] ap_return_34_int_reg; +reg [15:0] ap_return_35_int_reg; +reg [15:0] ap_return_36_int_reg; +reg [15:0] ap_return_37_int_reg; +reg [15:0] ap_return_38_int_reg; +reg [15:0] ap_return_39_int_reg; +reg [15:0] ap_return_40_int_reg; +reg [15:0] ap_return_41_int_reg; +reg [15:0] ap_return_42_int_reg; +reg [15:0] ap_return_43_int_reg; +reg [15:0] ap_return_44_int_reg; +reg [15:0] ap_return_45_int_reg; +reg [15:0] ap_return_46_int_reg; +reg [15:0] ap_return_47_int_reg; +reg [15:0] ap_return_48_int_reg; +reg [15:0] ap_return_49_int_reg; +reg [15:0] ap_return_50_int_reg; +reg [15:0] ap_return_51_int_reg; +reg [15:0] ap_return_52_int_reg; +reg [15:0] ap_return_53_int_reg; +reg [15:0] ap_return_54_int_reg; +reg [15:0] ap_return_55_int_reg; +reg [15:0] ap_return_56_int_reg; +reg [15:0] ap_return_57_int_reg; +reg [15:0] ap_return_58_int_reg; +reg [15:0] ap_return_59_int_reg; +reg [15:0] ap_return_60_int_reg; +reg [15:0] ap_return_61_int_reg; +reg [15:0] ap_return_62_int_reg; +reg [15:0] ap_return_63_int_reg; + +always @ (posedge ap_clk) begin + ap_ce_reg <= ap_ce; +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + add_ln703_538_reg_4067 <= add_ln703_538_fu_280_p2; + add_ln703_538_reg_4067_pp0_iter4_reg <= add_ln703_538_reg_4067; + add_ln703_539_reg_4035 <= add_ln703_539_fu_260_p2; + add_ln703_539_reg_4035_pp0_iter2_reg <= add_ln703_539_reg_4035; + add_ln703_539_reg_4035_pp0_iter3_reg <= add_ln703_539_reg_4035_pp0_iter2_reg; + add_ln703_540_reg_4079 <= add_ln703_540_fu_288_p2; + add_ln703_540_reg_4079_pp0_iter4_reg <= add_ln703_540_reg_4079; + add_ln703_541_reg_4171 <= add_ln703_541_fu_348_p2; + add_ln703_542_reg_4177 <= add_ln703_542_fu_352_p2; + add_ln703_543_reg_4054 <= add_ln703_543_fu_272_p2; + add_ln703_543_reg_4054_pp0_iter3_reg <= add_ln703_543_reg_4054; + add_ln703_543_reg_4054_pp0_iter4_reg <= add_ln703_543_reg_4054_pp0_iter3_reg; + add_ln703_544_reg_4116 <= add_ln703_544_fu_312_p2; + add_ln703_544_reg_4116_pp0_iter5_reg <= add_ln703_544_reg_4116; + add_ln703_545_reg_4183 <= add_ln703_545_fu_364_p2; + add_ln703_547_reg_4128 <= add_ln703_547_fu_320_p2; + add_ln703_548_reg_4188 <= add_ln703_548_fu_368_p2; + add_ln703_549_reg_4103 <= add_ln703_549_fu_304_p2; + add_ln703_549_reg_4103_pp0_iter4_reg <= add_ln703_549_reg_4103; + add_ln703_549_reg_4103_pp0_iter5_reg <= add_ln703_549_reg_4103_pp0_iter4_reg; + add_ln703_550_reg_4211 <= add_ln703_550_fu_384_p2; + add_ln703_551_reg_4222 <= add_ln703_551_fu_393_p2; + add_ln703_554_reg_4134 <= add_ln703_554_fu_324_p2; + add_ln703_554_reg_4134_pp0_iter5_reg <= add_ln703_554_reg_4134; + add_ln703_557_reg_4293 <= add_ln703_557_fu_488_p2; + add_ln703_558_reg_4298 <= add_ln703_558_fu_498_p2; + add_ln703_559_reg_4146 <= add_ln703_559_fu_332_p2; + add_ln703_559_reg_4146_pp0_iter5_reg <= add_ln703_559_reg_4146; + add_ln703_560_reg_4153 <= add_ln703_560_fu_336_p2; + add_ln703_560_reg_4153_pp0_iter5_reg <= add_ln703_560_reg_4153; + add_ln703_564_reg_4240 <= add_ln703_564_fu_406_p2; + add_ln703_566_reg_4258 <= add_ln703_566_fu_418_p2; + add_ln703_566_reg_4258_pp0_iter6_reg <= add_ln703_566_reg_4258; + add_ln703_568_reg_4270 <= add_ln703_568_fu_426_p2; + add_ln703_571_reg_4372 <= add_ln703_571_fu_657_p2; + add_ln703_572_reg_4382 <= add_ln703_572_fu_670_p2; + add_ln703_573_reg_4387 <= add_ln703_573_fu_675_p2; + add_ln703_574_reg_4393 <= add_ln703_574_fu_679_p2; + add_ln703_576_reg_4408 <= add_ln703_576_fu_702_p2; + add_ln703_577_reg_4413 <= add_ln703_577_fu_707_p2; + add_ln703_579_reg_4418 <= add_ln703_579_fu_716_p2; + add_ln703_580_reg_4433 <= add_ln703_580_fu_730_p2; + add_ln703_583_reg_4450 <= add_ln703_583_fu_754_p2; + add_ln703_587_reg_4471 <= add_ln703_587_fu_786_p2; + add_ln703_588_reg_4476 <= add_ln703_588_fu_792_p2; + add_ln703_590_reg_4481 <= add_ln703_590_fu_801_p2; + add_ln703_597_reg_4282 <= add_ln703_597_fu_434_p2; + add_ln703_597_reg_4282_pp0_iter6_reg <= add_ln703_597_reg_4282; + add_ln703_611_reg_4521 <= add_ln703_611_fu_887_p2; + add_ln703_620_reg_4537 <= add_ln703_620_fu_891_p2; + add_ln703_631_reg_4588 <= add_ln703_631_fu_1397_p2; + add_ln703_634_reg_4593 <= add_ln703_634_fu_1416_p2; + add_ln703_637_reg_4553 <= add_ln703_637_fu_906_p2; + add_ln703_639_reg_4608 <= add_ln703_639_fu_1459_p2; + add_ln703_642_reg_4628 <= add_ln703_642_fu_1505_p2; + add_ln703_645_reg_4648 <= add_ln703_645_fu_1538_p2; + add_ln703_646_reg_4658 <= add_ln703_646_fu_1553_p2; + add_ln703_655_reg_4558 <= add_ln703_655_fu_910_p2; + add_ln703_658_reg_4733 <= add_ln703_658_fu_1696_p2; + add_ln703_659_reg_4568 <= add_ln703_659_fu_914_p2; + add_ln703_661_reg_4744 <= add_ln703_661_fu_1710_p2; + add_ln703_663_reg_4764 <= add_ln703_663_fu_1735_p2; + add_ln703_667_reg_4784 <= add_ln703_667_fu_1767_p2; + add_ln703_669_reg_4804 <= add_ln703_669_fu_1787_p2; + add_ln703_670_reg_4819 <= add_ln703_670_fu_1802_p2; + add_ln703_672_reg_4829 <= add_ln703_672_fu_1812_p2; + add_ln703_674_reg_4839 <= add_ln703_674_fu_1822_p2; + add_ln703_679_reg_4847 <= add_ln703_679_fu_1826_p2; + add_ln703_687_reg_4857 <= add_ln703_687_fu_1847_p2; + add_ln703_688_reg_4862 <= add_ln703_688_fu_1853_p2; + add_ln703_692_reg_4573 <= add_ln703_692_fu_920_p2; + add_ln703_692_reg_4573_pp0_iter7_reg <= add_ln703_692_reg_4573; + add_ln703_707_reg_4867 <= add_ln703_707_fu_1877_p2; + add_ln703_711_reg_4872 <= add_ln703_711_fu_1887_p2; + add_ln703_716_reg_4877 <= add_ln703_716_fu_1902_p2; + add_ln703_722_reg_4882 <= add_ln703_722_fu_1913_p2; + add_ln703_724_reg_4887 <= add_ln703_724_fu_1923_p2; + add_ln703_727_reg_4892 <= add_ln703_727_fu_1934_p2; + add_ln703_729_reg_4897 <= add_ln703_729_fu_1945_p2; + add_ln703_732_reg_4902 <= add_ln703_732_fu_1956_p2; + add_ln703_737_reg_4907 <= add_ln703_737_fu_1962_p2; + add_ln703_739_reg_4915 <= add_ln703_739_fu_1966_p2; + add_ln703_751_reg_4920 <= add_ln703_751_fu_1971_p2; + add_ln703_reg_4010 <= add_ln703_fu_242_p2; + add_ln703_reg_4010_pp0_iter1_reg <= add_ln703_reg_4010; + add_ln703_reg_4010_pp0_iter2_reg <= add_ln703_reg_4010_pp0_iter1_reg; + mult_307_V_reg_3472 <= {{data_V_read_int_reg[79:64]}}; + mult_307_V_reg_3472_pp0_iter1_reg <= mult_307_V_reg_3472; + mult_307_V_reg_3472_pp0_iter2_reg <= mult_307_V_reg_3472_pp0_iter1_reg; + mult_307_V_reg_3472_pp0_iter3_reg <= mult_307_V_reg_3472_pp0_iter2_reg; + mult_307_V_reg_3472_pp0_iter4_reg <= mult_307_V_reg_3472_pp0_iter3_reg; + mult_307_V_reg_3472_pp0_iter5_reg <= mult_307_V_reg_3472_pp0_iter4_reg; + mult_320_V_reg_3500 <= {{data_V_read_int_reg[95:80]}}; + mult_320_V_reg_3500_pp0_iter1_reg <= mult_320_V_reg_3500; + mult_320_V_reg_3500_pp0_iter2_reg <= mult_320_V_reg_3500_pp0_iter1_reg; + mult_320_V_reg_3500_pp0_iter3_reg <= mult_320_V_reg_3500_pp0_iter2_reg; + mult_320_V_reg_3500_pp0_iter4_reg <= mult_320_V_reg_3500_pp0_iter3_reg; + mult_320_V_reg_3500_pp0_iter5_reg <= mult_320_V_reg_3500_pp0_iter4_reg; + mult_386_V_reg_3539 <= {{data_V_read_int_reg[111:96]}}; + mult_386_V_reg_3539_pp0_iter1_reg <= mult_386_V_reg_3539; + mult_386_V_reg_3539_pp0_iter2_reg <= mult_386_V_reg_3539_pp0_iter1_reg; + mult_386_V_reg_3539_pp0_iter3_reg <= mult_386_V_reg_3539_pp0_iter2_reg; + mult_386_V_reg_3539_pp0_iter4_reg <= mult_386_V_reg_3539_pp0_iter3_reg; + mult_386_V_reg_3539_pp0_iter5_reg <= mult_386_V_reg_3539_pp0_iter4_reg; + mult_386_V_reg_3539_pp0_iter6_reg <= mult_386_V_reg_3539_pp0_iter5_reg; + mult_449_V_reg_3582 <= {{data_V_read_int_reg[127:112]}}; + mult_449_V_reg_3582_pp0_iter1_reg <= mult_449_V_reg_3582; + mult_449_V_reg_3582_pp0_iter2_reg <= mult_449_V_reg_3582_pp0_iter1_reg; + mult_449_V_reg_3582_pp0_iter3_reg <= mult_449_V_reg_3582_pp0_iter2_reg; + mult_449_V_reg_3582_pp0_iter4_reg <= mult_449_V_reg_3582_pp0_iter3_reg; + mult_449_V_reg_3582_pp0_iter5_reg <= mult_449_V_reg_3582_pp0_iter4_reg; + mult_449_V_reg_3582_pp0_iter6_reg <= mult_449_V_reg_3582_pp0_iter5_reg; + mult_512_V_reg_3629 <= {{data_V_read_int_reg[143:128]}}; + mult_512_V_reg_3629_pp0_iter1_reg <= mult_512_V_reg_3629; + mult_512_V_reg_3629_pp0_iter2_reg <= mult_512_V_reg_3629_pp0_iter1_reg; + mult_512_V_reg_3629_pp0_iter3_reg <= mult_512_V_reg_3629_pp0_iter2_reg; + mult_512_V_reg_3629_pp0_iter4_reg <= mult_512_V_reg_3629_pp0_iter3_reg; + mult_512_V_reg_3629_pp0_iter5_reg <= mult_512_V_reg_3629_pp0_iter4_reg; + mult_512_V_reg_3629_pp0_iter6_reg <= mult_512_V_reg_3629_pp0_iter5_reg; + mult_576_V_reg_3674 <= {{data_V_read_int_reg[159:144]}}; + mult_576_V_reg_3674_pp0_iter1_reg <= mult_576_V_reg_3674; + mult_576_V_reg_3674_pp0_iter2_reg <= mult_576_V_reg_3674_pp0_iter1_reg; + mult_576_V_reg_3674_pp0_iter3_reg <= mult_576_V_reg_3674_pp0_iter2_reg; + mult_576_V_reg_3674_pp0_iter4_reg <= mult_576_V_reg_3674_pp0_iter3_reg; + mult_576_V_reg_3674_pp0_iter5_reg <= mult_576_V_reg_3674_pp0_iter4_reg; + mult_576_V_reg_3674_pp0_iter6_reg <= mult_576_V_reg_3674_pp0_iter5_reg; + mult_640_V_reg_3716 <= {{data_V_read_int_reg[175:160]}}; + mult_640_V_reg_3716_pp0_iter1_reg <= mult_640_V_reg_3716; + mult_640_V_reg_3716_pp0_iter2_reg <= mult_640_V_reg_3716_pp0_iter1_reg; + mult_640_V_reg_3716_pp0_iter3_reg <= mult_640_V_reg_3716_pp0_iter2_reg; + mult_640_V_reg_3716_pp0_iter4_reg <= mult_640_V_reg_3716_pp0_iter3_reg; + mult_640_V_reg_3716_pp0_iter5_reg <= mult_640_V_reg_3716_pp0_iter4_reg; + mult_640_V_reg_3716_pp0_iter6_reg <= mult_640_V_reg_3716_pp0_iter5_reg; + mult_704_V_reg_3765 <= {{data_V_read_int_reg[191:176]}}; + mult_704_V_reg_3765_pp0_iter1_reg <= mult_704_V_reg_3765; + mult_704_V_reg_3765_pp0_iter2_reg <= mult_704_V_reg_3765_pp0_iter1_reg; + mult_704_V_reg_3765_pp0_iter3_reg <= mult_704_V_reg_3765_pp0_iter2_reg; + mult_704_V_reg_3765_pp0_iter4_reg <= mult_704_V_reg_3765_pp0_iter3_reg; + mult_704_V_reg_3765_pp0_iter5_reg <= mult_704_V_reg_3765_pp0_iter4_reg; + mult_704_V_reg_3765_pp0_iter6_reg <= mult_704_V_reg_3765_pp0_iter5_reg; + mult_704_V_reg_3765_pp0_iter7_reg <= mult_704_V_reg_3765_pp0_iter6_reg; + mult_770_V_reg_3814 <= {{data_V_read_int_reg[207:192]}}; + mult_770_V_reg_3814_pp0_iter1_reg <= mult_770_V_reg_3814; + mult_770_V_reg_3814_pp0_iter2_reg <= mult_770_V_reg_3814_pp0_iter1_reg; + mult_770_V_reg_3814_pp0_iter3_reg <= mult_770_V_reg_3814_pp0_iter2_reg; + mult_770_V_reg_3814_pp0_iter4_reg <= mult_770_V_reg_3814_pp0_iter3_reg; + mult_770_V_reg_3814_pp0_iter5_reg <= mult_770_V_reg_3814_pp0_iter4_reg; + mult_770_V_reg_3814_pp0_iter6_reg <= mult_770_V_reg_3814_pp0_iter5_reg; + mult_770_V_reg_3814_pp0_iter7_reg <= mult_770_V_reg_3814_pp0_iter6_reg; + mult_832_V_reg_3861 <= {{data_V_read_int_reg[223:208]}}; + mult_832_V_reg_3861_pp0_iter1_reg <= mult_832_V_reg_3861; + mult_832_V_reg_3861_pp0_iter2_reg <= mult_832_V_reg_3861_pp0_iter1_reg; + mult_832_V_reg_3861_pp0_iter3_reg <= mult_832_V_reg_3861_pp0_iter2_reg; + mult_832_V_reg_3861_pp0_iter4_reg <= mult_832_V_reg_3861_pp0_iter3_reg; + mult_832_V_reg_3861_pp0_iter5_reg <= mult_832_V_reg_3861_pp0_iter4_reg; + mult_832_V_reg_3861_pp0_iter6_reg <= mult_832_V_reg_3861_pp0_iter5_reg; + mult_832_V_reg_3861_pp0_iter7_reg <= mult_832_V_reg_3861_pp0_iter6_reg; + mult_896_V_reg_3909 <= {{data_V_read_int_reg[239:224]}}; + mult_896_V_reg_3909_pp0_iter1_reg <= mult_896_V_reg_3909; + mult_896_V_reg_3909_pp0_iter2_reg <= mult_896_V_reg_3909_pp0_iter1_reg; + mult_896_V_reg_3909_pp0_iter3_reg <= mult_896_V_reg_3909_pp0_iter2_reg; + mult_896_V_reg_3909_pp0_iter4_reg <= mult_896_V_reg_3909_pp0_iter3_reg; + mult_896_V_reg_3909_pp0_iter5_reg <= mult_896_V_reg_3909_pp0_iter4_reg; + mult_896_V_reg_3909_pp0_iter6_reg <= mult_896_V_reg_3909_pp0_iter5_reg; + mult_896_V_reg_3909_pp0_iter7_reg <= mult_896_V_reg_3909_pp0_iter6_reg; + mult_960_V_reg_3958 <= {{data_V_read_int_reg[255:240]}}; + mult_960_V_reg_3958_pp0_iter1_reg <= mult_960_V_reg_3958; + mult_960_V_reg_3958_pp0_iter2_reg <= mult_960_V_reg_3958_pp0_iter1_reg; + mult_960_V_reg_3958_pp0_iter3_reg <= mult_960_V_reg_3958_pp0_iter2_reg; + mult_960_V_reg_3958_pp0_iter4_reg <= mult_960_V_reg_3958_pp0_iter3_reg; + mult_960_V_reg_3958_pp0_iter5_reg <= mult_960_V_reg_3958_pp0_iter4_reg; + mult_960_V_reg_3958_pp0_iter6_reg <= mult_960_V_reg_3958_pp0_iter5_reg; + mult_960_V_reg_3958_pp0_iter7_reg <= mult_960_V_reg_3958_pp0_iter6_reg; + sub_ln703_531_reg_4023 <= sub_ln703_531_fu_252_p2; + sub_ln703_531_reg_4023_pp0_iter2_reg <= sub_ln703_531_reg_4023; + sub_ln703_532_reg_4061 <= sub_ln703_532_fu_276_p2; + sub_ln703_532_reg_4061_pp0_iter4_reg <= sub_ln703_532_reg_4061; + sub_ln703_533_reg_4042 <= sub_ln703_533_fu_264_p2; + sub_ln703_533_reg_4042_pp0_iter3_reg <= sub_ln703_533_reg_4042; + sub_ln703_533_reg_4042_pp0_iter4_reg <= sub_ln703_533_reg_4042_pp0_iter3_reg; + sub_ln703_534_reg_4029 <= sub_ln703_534_fu_256_p2; + sub_ln703_534_reg_4029_pp0_iter2_reg <= sub_ln703_534_reg_4029; + sub_ln703_534_reg_4029_pp0_iter3_reg <= sub_ln703_534_reg_4029_pp0_iter2_reg; + sub_ln703_534_reg_4029_pp0_iter4_reg <= sub_ln703_534_reg_4029_pp0_iter3_reg; + sub_ln703_535_reg_4073 <= sub_ln703_535_fu_284_p2; + sub_ln703_535_reg_4073_pp0_iter4_reg <= sub_ln703_535_reg_4073; + sub_ln703_536_reg_4159 <= sub_ln703_536_fu_340_p2; + sub_ln703_537_reg_4085 <= sub_ln703_537_fu_292_p2; + sub_ln703_537_reg_4085_pp0_iter4_reg <= sub_ln703_537_reg_4085; + sub_ln703_537_reg_4085_pp0_iter5_reg <= sub_ln703_537_reg_4085_pp0_iter4_reg; + sub_ln703_538_reg_4048 <= sub_ln703_538_fu_268_p2; + sub_ln703_538_reg_4048_pp0_iter3_reg <= sub_ln703_538_reg_4048; + sub_ln703_538_reg_4048_pp0_iter4_reg <= sub_ln703_538_reg_4048_pp0_iter3_reg; + sub_ln703_538_reg_4048_pp0_iter5_reg <= sub_ln703_538_reg_4048_pp0_iter4_reg; + sub_ln703_539_reg_4165 <= sub_ln703_539_fu_344_p2; + sub_ln703_540_reg_4110 <= sub_ln703_540_fu_308_p2; + sub_ln703_540_reg_4110_pp0_iter5_reg <= sub_ln703_540_reg_4110; + sub_ln703_543_reg_4091 <= sub_ln703_543_fu_296_p2; + sub_ln703_543_reg_4091_pp0_iter4_reg <= sub_ln703_543_reg_4091; + sub_ln703_544_reg_4122 <= sub_ln703_544_fu_316_p2; + sub_ln703_544_reg_4122_pp0_iter5_reg <= sub_ln703_544_reg_4122; + sub_ln703_545_reg_4097 <= sub_ln703_545_fu_300_p2; + sub_ln703_545_reg_4097_pp0_iter4_reg <= sub_ln703_545_reg_4097; + sub_ln703_545_reg_4097_pp0_iter5_reg <= sub_ln703_545_reg_4097_pp0_iter4_reg; + sub_ln703_549_reg_4194 <= sub_ln703_549_fu_372_p2; + sub_ln703_550_reg_4200 <= sub_ln703_550_fu_376_p2; + sub_ln703_551_reg_4205 <= sub_ln703_551_fu_380_p2; + sub_ln703_552_reg_4217 <= sub_ln703_552_fu_388_p2; + sub_ln703_554_reg_4228 <= sub_ln703_554_fu_398_p2; + sub_ln703_557_reg_4234 <= sub_ln703_557_fu_402_p2; + sub_ln703_558_reg_4140 <= sub_ln703_558_fu_328_p2; + sub_ln703_558_reg_4140_pp0_iter5_reg <= sub_ln703_558_reg_4140; + sub_ln703_567_reg_4303 <= sub_ln703_567_fu_540_p2; + sub_ln703_570_reg_4246 <= sub_ln703_570_fu_410_p2; + sub_ln703_572_reg_4309 <= sub_ln703_572_fu_563_p2; + sub_ln703_574_reg_4314 <= sub_ln703_574_fu_572_p2; + sub_ln703_576_reg_4252 <= sub_ln703_576_fu_414_p2; + sub_ln703_576_reg_4252_pp0_iter6_reg <= sub_ln703_576_reg_4252; + sub_ln703_578_reg_4319 <= sub_ln703_578_fu_585_p2; + sub_ln703_579_reg_4324 <= sub_ln703_579_fu_590_p2; + sub_ln703_582_reg_4329 <= sub_ln703_582_fu_599_p2; + sub_ln703_584_reg_4264 <= sub_ln703_584_fu_422_p2; + sub_ln703_584_reg_4264_pp0_iter6_reg <= sub_ln703_584_reg_4264; + sub_ln703_585_reg_4334 <= sub_ln703_585_fu_609_p2; + sub_ln703_586_reg_4340 <= sub_ln703_586_fu_614_p2; + sub_ln703_587_reg_4345 <= sub_ln703_587_fu_619_p2; + sub_ln703_588_reg_4350 <= sub_ln703_588_fu_624_p2; + sub_ln703_589_reg_4355 <= sub_ln703_589_fu_638_p2; + sub_ln703_590_reg_4361 <= sub_ln703_590_fu_643_p2; + sub_ln703_591_reg_4277 <= sub_ln703_591_fu_430_p2; + sub_ln703_592_reg_4366 <= sub_ln703_592_fu_653_p2; + sub_ln703_594_reg_4377 <= sub_ln703_594_fu_666_p2; + sub_ln703_596_reg_4398 <= sub_ln703_596_fu_683_p2; + sub_ln703_599_reg_4403 <= sub_ln703_599_fu_693_p2; + sub_ln703_605_reg_4423 <= sub_ln703_605_fu_720_p2; + sub_ln703_608_reg_4428 <= sub_ln703_608_fu_725_p2; + sub_ln703_610_reg_4439 <= sub_ln703_610_fu_734_p2; + sub_ln703_611_reg_4444 <= sub_ln703_611_fu_739_p2; + sub_ln703_613_reg_4455 <= sub_ln703_613_fu_758_p2; + sub_ln703_617_reg_4460 <= sub_ln703_617_fu_763_p2; + sub_ln703_620_reg_4466 <= sub_ln703_620_fu_772_p2; + sub_ln703_627_reg_4486 <= sub_ln703_627_fu_807_p2; + sub_ln703_632_reg_4491 <= sub_ln703_632_fu_818_p2; + sub_ln703_641_reg_4496 <= sub_ln703_641_fu_838_p2; + sub_ln703_645_reg_4501 <= sub_ln703_645_fu_843_p2; + sub_ln703_660_reg_4506 <= sub_ln703_660_fu_872_p2; + sub_ln703_661_reg_4511 <= sub_ln703_661_fu_877_p2; + sub_ln703_662_reg_4516 <= sub_ln703_662_fu_882_p2; + sub_ln703_671_reg_4543 <= sub_ln703_671_fu_896_p2; + sub_ln703_676_reg_4548 <= sub_ln703_676_fu_901_p2; + sub_ln703_692_reg_4598 <= sub_ln703_692_fu_1433_p2; + sub_ln703_693_reg_4603 <= sub_ln703_693_fu_1438_p2; + sub_ln703_695_reg_4613 <= sub_ln703_695_fu_1464_p2; + sub_ln703_699_reg_4618 <= sub_ln703_699_fu_1495_p2; + sub_ln703_700_reg_4623 <= sub_ln703_700_fu_1500_p2; + sub_ln703_701_reg_4633 <= sub_ln703_701_fu_1509_p2; + sub_ln703_702_reg_4638 <= sub_ln703_702_fu_1514_p2; + sub_ln703_704_reg_4643 <= sub_ln703_704_fu_1524_p2; + sub_ln703_706_reg_4653 <= sub_ln703_706_fu_1548_p2; + sub_ln703_707_reg_4663 <= sub_ln703_707_fu_1559_p2; + sub_ln703_708_reg_4668 <= sub_ln703_708_fu_1564_p2; + sub_ln703_709_reg_4673 <= sub_ln703_709_fu_1569_p2; + sub_ln703_710_reg_4678 <= sub_ln703_710_fu_1606_p2; + sub_ln703_711_reg_4683 <= sub_ln703_711_fu_1611_p2; + sub_ln703_712_reg_4688 <= sub_ln703_712_fu_1616_p2; + sub_ln703_714_reg_4693 <= sub_ln703_714_fu_1626_p2; + sub_ln703_715_reg_4698 <= sub_ln703_715_fu_1631_p2; + sub_ln703_716_reg_4703 <= sub_ln703_716_fu_1636_p2; + sub_ln703_718_reg_4708 <= sub_ln703_718_fu_1646_p2; + sub_ln703_720_reg_4713 <= sub_ln703_720_fu_1676_p2; + sub_ln703_722_reg_4718 <= sub_ln703_722_fu_1681_p2; + sub_ln703_724_reg_4723 <= sub_ln703_724_fu_1686_p2; + sub_ln703_725_reg_4728 <= sub_ln703_725_fu_1691_p2; + sub_ln703_727_reg_4738 <= sub_ln703_727_fu_1701_p2; + sub_ln703_729_reg_4749 <= sub_ln703_729_fu_1715_p2; + sub_ln703_730_reg_4754 <= sub_ln703_730_fu_1720_p2; + sub_ln703_731_reg_4759 <= sub_ln703_731_fu_1725_p2; + sub_ln703_732_reg_4769 <= sub_ln703_732_fu_1741_p2; + sub_ln703_738_reg_4774 <= sub_ln703_738_fu_1757_p2; + sub_ln703_742_reg_4779 <= sub_ln703_742_fu_1762_p2; + sub_ln703_743_reg_4789 <= sub_ln703_743_fu_1772_p2; + sub_ln703_744_reg_4794 <= sub_ln703_744_fu_1777_p2; + sub_ln703_745_reg_4799 <= sub_ln703_745_fu_1782_p2; + sub_ln703_748_reg_4809 <= sub_ln703_748_fu_1792_p2; + sub_ln703_751_reg_4814 <= sub_ln703_751_fu_1797_p2; + sub_ln703_752_reg_4824 <= sub_ln703_752_fu_1807_p2; + sub_ln703_753_reg_4834 <= sub_ln703_753_fu_1817_p2; + sub_ln703_765_reg_4852 <= sub_ln703_765_fu_1832_p2; + sub_ln703_reg_4017 <= sub_ln703_fu_248_p2; + sub_ln703_reg_4017_pp0_iter2_reg <= sub_ln703_reg_4017; + tmp_2_reg_3437 <= {{data_V_read_int_reg[31:16]}}; + tmp_3_reg_3443 <= {{data_V_read_int_reg[47:32]}}; + tmp_3_reg_3443_pp0_iter1_reg <= tmp_3_reg_3443; + tmp_3_reg_3443_pp0_iter2_reg <= tmp_3_reg_3443_pp0_iter1_reg; + tmp_4_reg_3454 <= {{data_V_read_int_reg[63:48]}}; + tmp_4_reg_3454_pp0_iter1_reg <= tmp_4_reg_3454; + tmp_4_reg_3454_pp0_iter2_reg <= tmp_4_reg_3454_pp0_iter1_reg; + tmp_4_reg_3454_pp0_iter3_reg <= tmp_4_reg_3454_pp0_iter2_reg; + tmp_4_reg_3454_pp0_iter4_reg <= tmp_4_reg_3454_pp0_iter3_reg; + trunc_ln203_reg_3431 <= trunc_ln203_fu_88_p1; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce_reg)) begin + ap_return_0_int_reg <= add_ln703_752_fu_2673_p2; + ap_return_10_int_reg <= acc_10_V_fu_2733_p2; + ap_return_11_int_reg <= acc_11_V_fu_2738_p2; + ap_return_12_int_reg <= acc_12_V_fu_2743_p2; + ap_return_13_int_reg <= acc_13_V_fu_2748_p2; + ap_return_14_int_reg <= acc_14_V_fu_2753_p2; + ap_return_15_int_reg <= acc_15_V_fu_2758_p2; + ap_return_16_int_reg <= acc_16_V_fu_2771_p2; + ap_return_17_int_reg <= acc_17_V_fu_2777_p2; + ap_return_18_int_reg <= acc_18_V_fu_2782_p2; + ap_return_19_int_reg <= acc_19_V_fu_2787_p2; + ap_return_1_int_reg <= acc_1_V_fu_2678_p2; + ap_return_20_int_reg <= acc_20_V_fu_2797_p2; + ap_return_21_int_reg <= acc_21_V_fu_2802_p2; + ap_return_22_int_reg <= acc_22_V_fu_2807_p2; + ap_return_23_int_reg <= acc_23_V_fu_2812_p2; + ap_return_24_int_reg <= acc_24_V_fu_2817_p2; + ap_return_25_int_reg <= acc_25_V_fu_2822_p2; + ap_return_26_int_reg <= acc_26_V_fu_2827_p2; + ap_return_27_int_reg <= acc_27_V_fu_2832_p2; + ap_return_28_int_reg <= acc_28_V_fu_2837_p2; + ap_return_29_int_reg <= acc_29_V_fu_2842_p2; + ap_return_2_int_reg <= acc_2_V_fu_2683_p2; + ap_return_30_int_reg <= acc_30_V_fu_2847_p2; + ap_return_31_int_reg <= acc_31_V_fu_2852_p2; + ap_return_32_int_reg <= acc_32_V_fu_2857_p2; + ap_return_33_int_reg <= acc_33_V_fu_2862_p2; + ap_return_34_int_reg <= acc_34_V_fu_2872_p2; + ap_return_35_int_reg <= acc_35_V_fu_2877_p2; + ap_return_36_int_reg <= acc_36_V_fu_2882_p2; + ap_return_37_int_reg <= acc_37_V_fu_2887_p2; + ap_return_38_int_reg <= acc_38_V_fu_2892_p2; + ap_return_39_int_reg <= acc_39_V_fu_2897_p2; + ap_return_3_int_reg <= acc_3_V_fu_2688_p2; + ap_return_40_int_reg <= acc_40_V_fu_2902_p2; + ap_return_41_int_reg <= acc_41_V_fu_2907_p2; + ap_return_42_int_reg <= acc_42_V_fu_2912_p2; + ap_return_43_int_reg <= acc_43_V_fu_2917_p2; + ap_return_44_int_reg <= acc_44_V_fu_2922_p2; + ap_return_45_int_reg <= acc_45_V_fu_2927_p2; + ap_return_46_int_reg <= acc_46_V_fu_2932_p2; + ap_return_47_int_reg <= acc_47_V_fu_2942_p2; + ap_return_48_int_reg <= acc_48_V_fu_2952_p2; + ap_return_49_int_reg <= acc_49_V_fu_2962_p2; + ap_return_4_int_reg <= acc_4_V_fu_2698_p2; + ap_return_50_int_reg <= acc_50_V_fu_2967_p2; + ap_return_51_int_reg <= acc_51_V_fu_2972_p2; + ap_return_52_int_reg <= acc_52_V_fu_2977_p2; + ap_return_53_int_reg <= acc_53_V_fu_2982_p2; + ap_return_54_int_reg <= acc_54_V_fu_2987_p2; + ap_return_55_int_reg <= acc_55_V_fu_2997_p2; + ap_return_56_int_reg <= acc_56_V_fu_3002_p2; + ap_return_57_int_reg <= acc_57_V_fu_3007_p2; + ap_return_58_int_reg <= acc_58_V_fu_3012_p2; + ap_return_59_int_reg <= acc_59_V_fu_3017_p2; + ap_return_5_int_reg <= acc_5_V_fu_2703_p2; + ap_return_60_int_reg <= acc_60_V_fu_3022_p2; + ap_return_61_int_reg <= acc_61_V_fu_3031_p2; + ap_return_62_int_reg <= acc_62_V_fu_3037_p2; + ap_return_63_int_reg <= acc_63_V_fu_3042_p2; + ap_return_6_int_reg <= acc_6_V_fu_2708_p2; + ap_return_7_int_reg <= acc_7_V_fu_2713_p2; + ap_return_8_int_reg <= acc_8_V_fu_2718_p2; + ap_return_9_int_reg <= acc_9_V_fu_2723_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce)) begin + data_V_read_int_reg <= data_V_read; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_0 = ap_return_0_int_reg; + end else begin + ap_return_0 = add_ln703_752_fu_2673_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_1 = ap_return_1_int_reg; + end else begin + ap_return_1 = acc_1_V_fu_2678_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_10 = ap_return_10_int_reg; + end else begin + ap_return_10 = acc_10_V_fu_2733_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_11 = ap_return_11_int_reg; + end else begin + ap_return_11 = acc_11_V_fu_2738_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_12 = ap_return_12_int_reg; + end else begin + ap_return_12 = acc_12_V_fu_2743_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_13 = ap_return_13_int_reg; + end else begin + ap_return_13 = acc_13_V_fu_2748_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_14 = ap_return_14_int_reg; + end else begin + ap_return_14 = acc_14_V_fu_2753_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_15 = ap_return_15_int_reg; + end else begin + ap_return_15 = acc_15_V_fu_2758_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_16 = ap_return_16_int_reg; + end else begin + ap_return_16 = acc_16_V_fu_2771_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_17 = ap_return_17_int_reg; + end else begin + ap_return_17 = acc_17_V_fu_2777_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_18 = ap_return_18_int_reg; + end else begin + ap_return_18 = acc_18_V_fu_2782_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_19 = ap_return_19_int_reg; + end else begin + ap_return_19 = acc_19_V_fu_2787_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_2 = ap_return_2_int_reg; + end else begin + ap_return_2 = acc_2_V_fu_2683_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_20 = ap_return_20_int_reg; + end else begin + ap_return_20 = acc_20_V_fu_2797_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_21 = ap_return_21_int_reg; + end else begin + ap_return_21 = acc_21_V_fu_2802_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_22 = ap_return_22_int_reg; + end else begin + ap_return_22 = acc_22_V_fu_2807_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_23 = ap_return_23_int_reg; + end else begin + ap_return_23 = acc_23_V_fu_2812_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_24 = ap_return_24_int_reg; + end else begin + ap_return_24 = acc_24_V_fu_2817_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_25 = ap_return_25_int_reg; + end else begin + ap_return_25 = acc_25_V_fu_2822_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_26 = ap_return_26_int_reg; + end else begin + ap_return_26 = acc_26_V_fu_2827_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_27 = ap_return_27_int_reg; + end else begin + ap_return_27 = acc_27_V_fu_2832_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_28 = ap_return_28_int_reg; + end else begin + ap_return_28 = acc_28_V_fu_2837_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_29 = ap_return_29_int_reg; + end else begin + ap_return_29 = acc_29_V_fu_2842_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_3 = ap_return_3_int_reg; + end else begin + ap_return_3 = acc_3_V_fu_2688_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_30 = ap_return_30_int_reg; + end else begin + ap_return_30 = acc_30_V_fu_2847_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_31 = ap_return_31_int_reg; + end else begin + ap_return_31 = acc_31_V_fu_2852_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_32 = ap_return_32_int_reg; + end else begin + ap_return_32 = acc_32_V_fu_2857_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_33 = ap_return_33_int_reg; + end else begin + ap_return_33 = acc_33_V_fu_2862_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_34 = ap_return_34_int_reg; + end else begin + ap_return_34 = acc_34_V_fu_2872_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_35 = ap_return_35_int_reg; + end else begin + ap_return_35 = acc_35_V_fu_2877_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_36 = ap_return_36_int_reg; + end else begin + ap_return_36 = acc_36_V_fu_2882_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_37 = ap_return_37_int_reg; + end else begin + ap_return_37 = acc_37_V_fu_2887_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_38 = ap_return_38_int_reg; + end else begin + ap_return_38 = acc_38_V_fu_2892_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_39 = ap_return_39_int_reg; + end else begin + ap_return_39 = acc_39_V_fu_2897_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_4 = ap_return_4_int_reg; + end else begin + ap_return_4 = acc_4_V_fu_2698_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_40 = ap_return_40_int_reg; + end else begin + ap_return_40 = acc_40_V_fu_2902_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_41 = ap_return_41_int_reg; + end else begin + ap_return_41 = acc_41_V_fu_2907_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_42 = ap_return_42_int_reg; + end else begin + ap_return_42 = acc_42_V_fu_2912_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_43 = ap_return_43_int_reg; + end else begin + ap_return_43 = acc_43_V_fu_2917_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_44 = ap_return_44_int_reg; + end else begin + ap_return_44 = acc_44_V_fu_2922_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_45 = ap_return_45_int_reg; + end else begin + ap_return_45 = acc_45_V_fu_2927_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_46 = ap_return_46_int_reg; + end else begin + ap_return_46 = acc_46_V_fu_2932_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_47 = ap_return_47_int_reg; + end else begin + ap_return_47 = acc_47_V_fu_2942_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_48 = ap_return_48_int_reg; + end else begin + ap_return_48 = acc_48_V_fu_2952_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_49 = ap_return_49_int_reg; + end else begin + ap_return_49 = acc_49_V_fu_2962_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_5 = ap_return_5_int_reg; + end else begin + ap_return_5 = acc_5_V_fu_2703_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_50 = ap_return_50_int_reg; + end else begin + ap_return_50 = acc_50_V_fu_2967_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_51 = ap_return_51_int_reg; + end else begin + ap_return_51 = acc_51_V_fu_2972_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_52 = ap_return_52_int_reg; + end else begin + ap_return_52 = acc_52_V_fu_2977_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_53 = ap_return_53_int_reg; + end else begin + ap_return_53 = acc_53_V_fu_2982_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_54 = ap_return_54_int_reg; + end else begin + ap_return_54 = acc_54_V_fu_2987_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_55 = ap_return_55_int_reg; + end else begin + ap_return_55 = acc_55_V_fu_2997_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_56 = ap_return_56_int_reg; + end else begin + ap_return_56 = acc_56_V_fu_3002_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_57 = ap_return_57_int_reg; + end else begin + ap_return_57 = acc_57_V_fu_3007_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_58 = ap_return_58_int_reg; + end else begin + ap_return_58 = acc_58_V_fu_3012_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_59 = ap_return_59_int_reg; + end else begin + ap_return_59 = acc_59_V_fu_3017_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_6 = ap_return_6_int_reg; + end else begin + ap_return_6 = acc_6_V_fu_2708_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_60 = ap_return_60_int_reg; + end else begin + ap_return_60 = acc_60_V_fu_3022_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_61 = ap_return_61_int_reg; + end else begin + ap_return_61 = acc_61_V_fu_3031_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_62 = ap_return_62_int_reg; + end else begin + ap_return_62 = acc_62_V_fu_3037_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_63 = ap_return_63_int_reg; + end else begin + ap_return_63 = acc_63_V_fu_3042_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_7 = ap_return_7_int_reg; + end else begin + ap_return_7 = acc_7_V_fu_2713_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_8 = ap_return_8_int_reg; + end else begin + ap_return_8 = acc_8_V_fu_2718_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_9 = ap_return_9_int_reg; + end else begin + ap_return_9 = acc_9_V_fu_2723_p2; + end +end + +assign acc_10_V_fu_2733_p2 = (add_ln703_758_fu_2728_p2 + add_ln703_751_reg_4920); + +assign acc_11_V_fu_2738_p2 = (sub_ln703_811_fu_2474_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_12_V_fu_2743_p2 = (mult_960_V_reg_3958_pp0_iter7_reg + sub_ln703_812_fu_2479_p2); + +assign acc_13_V_fu_2748_p2 = (add_ln703_735_fu_2484_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_14_V_fu_2753_p2 = (sub_ln703_813_fu_2489_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_15_V_fu_2758_p2 = (sub_ln703_814_fu_2494_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_16_V_fu_2771_p2 = (add_ln703_761_fu_2763_p2 + add_ln703_762_fu_2767_p2); + +assign acc_17_V_fu_2777_p2 = (sub_ln703_815_fu_2499_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_18_V_fu_2782_p2 = (add_ln703_736_fu_2504_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_19_V_fu_2787_p2 = (sub_ln703_790_fu_2299_p2 + add_ln703_751_reg_4920); + +assign acc_1_V_fu_2678_p2 = (mult_960_V_reg_3958_pp0_iter7_reg + sub_ln703_805_fu_2439_p2); + +assign acc_20_V_fu_2797_p2 = (add_ln703_765_fu_2792_p2 + add_ln703_751_reg_4920); + +assign acc_21_V_fu_2802_p2 = (sub_ln703_816_fu_2509_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_22_V_fu_2807_p2 = (mult_960_V_reg_3958_pp0_iter7_reg + sub_ln703_817_fu_2514_p2); + +assign acc_23_V_fu_2812_p2 = (sub_ln703_818_fu_2519_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_24_V_fu_2817_p2 = (sub_ln703_819_fu_2524_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_25_V_fu_2822_p2 = (sub_ln703_791_fu_2318_p2 + add_ln703_751_reg_4920); + +assign acc_26_V_fu_2827_p2 = (add_ln703_738_fu_2528_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_27_V_fu_2832_p2 = (add_ln703_741_fu_2536_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_28_V_fu_2837_p2 = (sub_ln703_820_fu_2541_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_29_V_fu_2842_p2 = (sub_ln703_821_fu_2546_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_2_V_fu_2683_p2 = (sub_ln703_806_fu_2444_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_30_V_fu_2847_p2 = (mult_960_V_reg_3958_pp0_iter7_reg + sub_ln703_822_fu_2550_p2); + +assign acc_31_V_fu_2852_p2 = (sub_ln703_823_fu_2555_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_32_V_fu_2857_p2 = (sub_ln703_824_fu_2560_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_33_V_fu_2862_p2 = (sub_ln703_825_fu_2564_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_34_V_fu_2872_p2 = (add_ln703_770_fu_2867_p2 + add_ln703_751_reg_4920); + +assign acc_35_V_fu_2877_p2 = (add_ln703_742_fu_2569_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_36_V_fu_2882_p2 = (sub_ln703_793_fu_2356_p2 + add_ln703_751_reg_4920); + +assign acc_37_V_fu_2887_p2 = (sub_ln703_826_fu_2574_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_38_V_fu_2892_p2 = (mult_960_V_reg_3958_pp0_iter7_reg + sub_ln703_827_fu_2579_p2); + +assign acc_39_V_fu_2897_p2 = (add_ln703_743_fu_2583_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_3_V_fu_2688_p2 = (sub_ln703_807_fu_2449_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_40_V_fu_2902_p2 = (sub_ln703_828_fu_2588_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_41_V_fu_2907_p2 = (sub_ln703_829_fu_2593_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_42_V_fu_2912_p2 = (sub_ln703_830_fu_2598_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_43_V_fu_2917_p2 = (mult_960_V_reg_3958_pp0_iter7_reg + sub_ln703_831_fu_2602_p2); + +assign acc_44_V_fu_2922_p2 = (sub_ln703_797_fu_2385_p2 + add_ln703_751_reg_4920); + +assign acc_45_V_fu_2927_p2 = (sub_ln703_832_fu_2607_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_46_V_fu_2932_p2 = (add_ln703_744_fu_2612_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_47_V_fu_2942_p2 = (add_ln703_776_fu_2937_p2 + add_ln703_751_reg_4920); + +assign acc_48_V_fu_2952_p2 = (add_ln703_778_fu_2947_p2 + add_ln703_751_reg_4920); + +assign acc_49_V_fu_2962_p2 = (add_ln703_780_fu_2957_p2 + add_ln703_751_reg_4920); + +assign acc_4_V_fu_2698_p2 = (add_ln703_754_fu_2693_p2 + add_ln703_751_reg_4920); + +assign acc_50_V_fu_2967_p2 = (add_ln703_745_fu_2617_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_51_V_fu_2972_p2 = (add_ln703_746_fu_2622_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_52_V_fu_2977_p2 = (add_ln703_747_fu_2627_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_53_V_fu_2982_p2 = (add_ln703_748_fu_2632_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_54_V_fu_2987_p2 = (add_ln703_749_fu_2637_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_55_V_fu_2997_p2 = (add_ln703_782_fu_2992_p2 + add_ln703_751_reg_4920); + +assign acc_56_V_fu_3002_p2 = (sub_ln703_833_fu_2642_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_57_V_fu_3007_p2 = (mult_960_V_reg_3958_pp0_iter7_reg + sub_ln703_834_fu_2646_p2); + +assign acc_58_V_fu_3012_p2 = (sub_ln703_835_fu_2651_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_59_V_fu_3017_p2 = (sub_ln703_836_fu_2655_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_5_V_fu_2703_p2 = (sub_ln703_808_fu_2454_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_60_V_fu_3022_p2 = (sub_ln703_804_fu_2429_p2 + add_ln703_751_reg_4920); + +assign acc_61_V_fu_3031_p2 = (add_ln703_786_fu_3027_p2 + add_ln703_762_fu_2767_p2); + +assign acc_62_V_fu_3037_p2 = (sub_ln703_837_fu_2660_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_63_V_fu_3042_p2 = (sub_ln703_838_fu_2664_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_6_V_fu_2708_p2 = (sub_ln703_809_fu_2459_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign acc_7_V_fu_2713_p2 = (mult_960_V_reg_3958_pp0_iter7_reg + sub_ln703_810_fu_2464_p2); + +assign acc_8_V_fu_2718_p2 = (sub_ln703_785_fu_2254_p2 + add_ln703_751_reg_4920); + +assign acc_9_V_fu_2723_p2 = (add_ln703_734_fu_2469_p2 - mult_960_V_reg_3958_pp0_iter7_reg); + +assign add_ln703_538_fu_280_p2 = (tmp_3_reg_3443_pp0_iter2_reg + sub_ln703_reg_4017_pp0_iter2_reg); + +assign add_ln703_539_fu_260_p2 = (tmp_3_reg_3443 + add_ln703_reg_4010); + +assign add_ln703_540_fu_288_p2 = (tmp_3_reg_3443_pp0_iter2_reg + sub_ln703_531_reg_4023_pp0_iter2_reg); + +assign add_ln703_541_fu_348_p2 = (tmp_4_reg_3454_pp0_iter4_reg + sub_ln703_535_reg_4073_pp0_iter4_reg); + +assign add_ln703_542_fu_352_p2 = (tmp_4_reg_3454_pp0_iter4_reg + sub_ln703_534_reg_4029_pp0_iter4_reg); + +assign add_ln703_543_fu_272_p2 = (tmp_4_reg_3454_pp0_iter1_reg + add_ln703_539_reg_4035); + +assign add_ln703_544_fu_312_p2 = (tmp_4_reg_3454_pp0_iter3_reg + sub_ln703_532_reg_4061); + +assign add_ln703_545_fu_364_p2 = (tmp_4_reg_3454_pp0_iter4_reg + sub_ln703_533_reg_4042_pp0_iter4_reg); + +assign add_ln703_546_fu_438_p2 = (mult_307_V_reg_3472_pp0_iter5_reg + sub_ln703_536_reg_4159); + +assign add_ln703_547_fu_320_p2 = (mult_307_V_reg_3472_pp0_iter3_reg + tmp_4_reg_3454_pp0_iter3_reg); + +assign add_ln703_548_fu_368_p2 = (add_ln703_538_reg_4067_pp0_iter4_reg + add_ln703_547_reg_4128); + +assign add_ln703_549_fu_304_p2 = (mult_307_V_reg_3472_pp0_iter2_reg + add_ln703_543_reg_4054); + +assign add_ln703_550_fu_384_p2 = (add_ln703_540_reg_4079_pp0_iter4_reg + add_ln703_547_reg_4128); + +assign add_ln703_551_fu_393_p2 = (mult_307_V_reg_3472_pp0_iter4_reg + sub_ln703_542_fu_360_p2); + +assign add_ln703_552_fu_454_p2 = (mult_307_V_reg_3472_pp0_iter5_reg + add_ln703_542_reg_4177); + +assign add_ln703_553_fu_458_p2 = (mult_307_V_reg_3472_pp0_iter5_reg + sub_ln703_539_reg_4165); + +assign add_ln703_554_fu_324_p2 = (mult_307_V_reg_3472_pp0_iter3_reg + sub_ln703_543_reg_4091); + +assign add_ln703_555_fu_466_p2 = (mult_307_V_reg_3472_pp0_iter5_reg + sub_ln703_538_reg_4048_pp0_iter5_reg); + +assign add_ln703_556_fu_478_p2 = (mult_320_V_reg_3500_pp0_iter5_reg + add_ln703_546_fu_438_p2); + +assign add_ln703_557_fu_488_p2 = (mult_320_V_reg_3500_pp0_iter5_reg + sub_ln703_547_fu_446_p2); + +assign add_ln703_558_fu_498_p2 = (mult_320_V_reg_3500_pp0_iter5_reg + add_ln703_548_reg_4188); + +assign add_ln703_559_fu_332_p2 = (mult_320_V_reg_3500_pp0_iter3_reg + add_ln703_549_reg_4103); + +assign add_ln703_560_fu_336_p2 = (mult_320_V_reg_3500_pp0_iter3_reg + mult_307_V_reg_3472_pp0_iter3_reg); + +assign add_ln703_561_fu_510_p2 = (add_ln703_541_reg_4171 + add_ln703_560_reg_4153_pp0_iter5_reg); + +assign add_ln703_562_fu_522_p2 = (mult_320_V_reg_3500_pp0_iter5_reg + sub_ln703_552_reg_4217); + +assign add_ln703_563_fu_526_p2 = (mult_320_V_reg_3500_pp0_iter5_reg + add_ln703_551_reg_4222); + +assign add_ln703_564_fu_406_p2 = (add_ln703_544_reg_4116 + add_ln703_560_reg_4153); + +assign add_ln703_565_fu_554_p2 = (mult_320_V_reg_3500_pp0_iter5_reg + sub_ln703_544_reg_4122_pp0_iter5_reg); + +assign add_ln703_566_fu_418_p2 = (mult_386_V_reg_3539_pp0_iter4_reg + sub_ln703_558_reg_4140); + +assign add_ln703_567_fu_629_p2 = (mult_307_V_reg_3472_pp0_iter5_reg + sub_ln703_537_reg_4085_pp0_iter5_reg); + +assign add_ln703_568_fu_426_p2 = (mult_386_V_reg_3539_pp0_iter4_reg + mult_320_V_reg_3500_pp0_iter4_reg); + +assign add_ln703_569_fu_633_p2 = (add_ln703_567_fu_629_p2 + add_ln703_568_reg_4270); + +assign add_ln703_570_fu_648_p2 = (mult_386_V_reg_3539_pp0_iter5_reg + sub_ln703_566_fu_535_p2); + +assign add_ln703_571_fu_657_p2 = (sub_ln703_554_reg_4228 + add_ln703_568_reg_4270); + +assign add_ln703_572_fu_670_p2 = (mult_386_V_reg_3539_pp0_iter5_reg + sub_ln703_569_fu_549_p2); + +assign add_ln703_573_fu_675_p2 = (mult_386_V_reg_3539_pp0_iter5_reg + add_ln703_559_reg_4146_pp0_iter5_reg); + +assign add_ln703_574_fu_679_p2 = (mult_386_V_reg_3539_pp0_iter5_reg + sub_ln703_570_reg_4246); + +assign add_ln703_575_fu_698_p2 = (mult_386_V_reg_3539_pp0_iter5_reg + add_ln703_564_reg_4240); + +assign add_ln703_576_fu_702_p2 = (mult_386_V_reg_3539_pp0_iter5_reg + sub_ln703_575_fu_577_p2); + +assign add_ln703_577_fu_707_p2 = (mult_386_V_reg_3539_pp0_iter5_reg + sub_ln703_577_fu_581_p2); + +assign add_ln703_578_fu_944_p2 = (mult_386_V_reg_3539_pp0_iter6_reg + add_ln703_558_reg_4298); + +assign add_ln703_579_fu_716_p2 = (mult_386_V_reg_3539_pp0_iter5_reg + sub_ln703_576_reg_4252); + +assign add_ln703_580_fu_730_p2 = (mult_449_V_reg_3582_pp0_iter5_reg + sub_ln703_584_reg_4264); + +assign add_ln703_581_fu_744_p2 = (mult_449_V_reg_3582_pp0_iter5_reg + mult_386_V_reg_3539_pp0_iter5_reg); + +assign add_ln703_582_fu_748_p2 = (sub_ln703_564_fu_518_p2 + add_ln703_581_fu_744_p2); + +assign add_ln703_583_fu_754_p2 = (mult_449_V_reg_3582_pp0_iter5_reg + add_ln703_566_reg_4258); + +assign add_ln703_584_fu_985_p2 = (mult_449_V_reg_3582_pp0_iter6_reg + sub_ln703_592_reg_4366); + +assign add_ln703_585_fu_777_p2 = (mult_307_V_reg_3472_pp0_iter5_reg + sub_ln703_540_reg_4110_pp0_iter5_reg); + +assign add_ln703_586_fu_781_p2 = (mult_320_V_reg_3500_pp0_iter5_reg + add_ln703_581_fu_744_p2); + +assign add_ln703_587_fu_786_p2 = (add_ln703_585_fu_777_p2 + add_ln703_586_fu_781_p2); + +assign add_ln703_588_fu_792_p2 = (mult_449_V_reg_3582_pp0_iter5_reg + sub_ln703_597_fu_688_p2); + +assign add_ln703_589_fu_797_p2 = (mult_320_V_reg_3500_pp0_iter5_reg + sub_ln703_545_reg_4097_pp0_iter5_reg); + +assign add_ln703_590_fu_801_p2 = (add_ln703_589_fu_797_p2 + add_ln703_581_fu_744_p2); + +assign add_ln703_591_fu_1027_p2 = (mult_449_V_reg_3582_pp0_iter6_reg + add_ln703_573_reg_4387); + +assign add_ln703_592_fu_1031_p2 = (mult_449_V_reg_3582_pp0_iter6_reg + sub_ln703_589_reg_4355); + +assign add_ln703_593_fu_812_p2 = (sub_ln703_568_fu_545_p2 + add_ln703_581_fu_744_p2); + +assign add_ln703_594_fu_823_p2 = (sub_ln703_557_reg_4234 + add_ln703_581_fu_744_p2); + +assign add_ln703_595_fu_828_p2 = (mult_320_V_reg_3500_pp0_iter5_reg + add_ln703_550_reg_4211); + +assign add_ln703_596_fu_832_p2 = (add_ln703_595_fu_828_p2 + add_ln703_581_fu_744_p2); + +assign add_ln703_597_fu_434_p2 = (mult_512_V_reg_3629_pp0_iter4_reg + mult_449_V_reg_3582_pp0_iter4_reg); + +assign add_ln703_598_fu_1052_p2 = (sub_ln703_579_reg_4324 + add_ln703_597_reg_4282_pp0_iter6_reg); + +assign add_ln703_599_fu_1073_p2 = (mult_512_V_reg_3629_pp0_iter6_reg + sub_ln703_609_fu_965_p2); + +assign add_ln703_600_fu_848_p2 = (mult_320_V_reg_3500_pp0_iter5_reg + add_ln703_554_reg_4134_pp0_iter5_reg); + +assign add_ln703_601_fu_852_p2 = (mult_386_V_reg_3539_pp0_iter5_reg + add_ln703_597_reg_4282); + +assign add_ln703_602_fu_856_p2 = (add_ln703_600_fu_848_p2 + add_ln703_601_fu_852_p2); + +assign add_ln703_603_fu_1132_p2 = (sub_ln703_596_reg_4398 + add_ln703_597_reg_4282_pp0_iter6_reg); + +assign add_ln703_604_fu_1140_p2 = (sub_ln703_598_fu_932_p2 + add_ln703_597_reg_4282_pp0_iter6_reg); + +assign add_ln703_605_fu_862_p2 = (mult_320_V_reg_3500_pp0_iter5_reg + sub_ln703_549_reg_4194); + +assign add_ln703_606_fu_866_p2 = (add_ln703_605_fu_862_p2 + add_ln703_601_fu_852_p2); + +assign add_ln703_607_fu_1163_p2 = (mult_512_V_reg_3629_pp0_iter6_reg + sub_ln703_611_reg_4444); + +assign add_ln703_608_fu_1176_p2 = (mult_512_V_reg_3629_pp0_iter6_reg + sub_ln703_631_fu_1039_p2); + +assign add_ln703_609_fu_1181_p2 = (mult_512_V_reg_3629_pp0_iter6_reg + sub_ln703_632_reg_4491); + +assign add_ln703_610_fu_1185_p2 = (sub_ln703_586_reg_4340 + add_ln703_597_reg_4282_pp0_iter6_reg); + +assign add_ln703_611_fu_887_p2 = (mult_576_V_reg_3674_pp0_iter5_reg + mult_512_V_reg_3629_pp0_iter5_reg); + +assign add_ln703_612_fu_1194_p2 = (sub_ln703_604_fu_952_p2 + add_ln703_611_reg_4521); + +assign add_ln703_613_fu_1209_p2 = (mult_576_V_reg_3674_pp0_iter6_reg + sub_ln703_638_fu_1069_p2); + +assign add_ln703_614_fu_1219_p2 = (mult_576_V_reg_3674_pp0_iter6_reg + sub_ln703_639_fu_1078_p2); + +assign add_ln703_615_fu_1228_p2 = (mult_576_V_reg_3674_pp0_iter6_reg + sub_ln703_643_fu_1091_p2); + +assign add_ln703_616_fu_1238_p2 = (sub_ln703_615_fu_977_p2 + add_ln703_611_reg_4521); + +assign add_ln703_617_fu_1243_p2 = (sub_ln703_616_fu_981_p2 + add_ln703_611_reg_4521); + +assign add_ln703_618_fu_1248_p2 = (add_ln703_580_reg_4433 + add_ln703_611_reg_4521); + +assign add_ln703_619_fu_1252_p2 = (sub_ln703_617_reg_4460 + add_ln703_611_reg_4521); + +assign add_ln703_620_fu_891_p2 = (mult_576_V_reg_3674_pp0_iter5_reg + sub_ln703_645_fu_843_p2); + +assign add_ln703_621_fu_1256_p2 = (mult_576_V_reg_3674_pp0_iter6_reg + sub_ln703_646_fu_1099_p2); + +assign add_ln703_622_fu_1271_p2 = (mult_576_V_reg_3674_pp0_iter6_reg + sub_ln703_648_fu_1108_p2); + +assign add_ln703_623_fu_1276_p2 = (mult_576_V_reg_3674_pp0_iter6_reg + sub_ln703_649_fu_1113_p2); + +assign add_ln703_624_fu_1286_p2 = (mult_576_V_reg_3674_pp0_iter6_reg + sub_ln703_652_fu_1127_p2); + +assign add_ln703_625_fu_1311_p2 = (sub_ln703_629_fu_1022_p2 + add_ln703_611_reg_4521); + +assign add_ln703_626_fu_1321_p2 = (mult_449_V_reg_3582_pp0_iter6_reg + sub_ln703_587_reg_4345); + +assign add_ln703_627_fu_1325_p2 = (add_ln703_626_fu_1321_p2 + add_ln703_611_reg_4521); + +assign add_ln703_628_fu_1350_p2 = (mult_449_V_reg_3582_pp0_iter6_reg + sub_ln703_601_fu_940_p2); + +assign add_ln703_629_fu_1355_p2 = (add_ln703_628_fu_1350_p2 + add_ln703_611_reg_4521); + +assign add_ln703_630_fu_1387_p2 = (sub_ln703_634_fu_1048_p2 + add_ln703_611_reg_4521); + +assign add_ln703_631_fu_1397_p2 = (mult_640_V_reg_3716_pp0_iter6_reg + add_ln703_612_fu_1194_p2); + +assign add_ln703_632_fu_1407_p2 = (mult_512_V_reg_3629_pp0_iter6_reg + sub_ln703_606_fu_956_p2); + +assign add_ln703_633_fu_1412_p2 = (mult_640_V_reg_3716_pp0_iter6_reg + mult_576_V_reg_3674_pp0_iter6_reg); + +assign add_ln703_634_fu_1416_p2 = (add_ln703_632_fu_1407_p2 + add_ln703_633_fu_1412_p2); + +assign add_ln703_635_fu_1422_p2 = (sub_ln703_636_fu_1060_p2 + add_ln703_633_fu_1412_p2); + +assign add_ln703_636_fu_1448_p2 = (sub_ln703_640_fu_1082_p2 + add_ln703_633_fu_1412_p2); + +assign add_ln703_637_fu_906_p2 = (sub_ln703_551_reg_4205 + add_ln703_568_reg_4270); + +assign add_ln703_638_fu_1454_p2 = (add_ln703_597_reg_4282_pp0_iter6_reg + add_ln703_633_fu_1412_p2); + +assign add_ln703_639_fu_1459_p2 = (add_ln703_637_reg_4553 + add_ln703_638_fu_1454_p2); + +assign add_ln703_640_fu_1469_p2 = (sub_ln703_642_fu_1086_p2 + add_ln703_633_fu_1412_p2); + +assign add_ln703_641_fu_1480_p2 = (mult_640_V_reg_3716_pp0_iter6_reg + sub_ln703_668_fu_1233_p2); + +assign add_ln703_642_fu_1505_p2 = (mult_640_V_reg_3716_pp0_iter6_reg + add_ln703_620_reg_4537); + +assign add_ln703_643_fu_1529_p2 = (mult_449_V_reg_3582_pp0_iter6_reg + sub_ln703_585_reg_4334); + +assign add_ln703_644_fu_1533_p2 = (mult_512_V_reg_3629_pp0_iter6_reg + add_ln703_633_fu_1412_p2); + +assign add_ln703_645_fu_1538_p2 = (add_ln703_643_fu_1529_p2 + add_ln703_644_fu_1533_p2); + +assign add_ln703_646_fu_1553_p2 = (sub_ln703_650_fu_1118_p2 + add_ln703_633_fu_1412_p2); + +assign add_ln703_647_fu_1574_p2 = (mult_640_V_reg_3716_pp0_iter6_reg + sub_ln703_674_fu_1296_p2); + +assign add_ln703_648_fu_1579_p2 = (mult_512_V_reg_3629_pp0_iter6_reg + sub_ln703_626_fu_1014_p2); + +assign add_ln703_649_fu_1584_p2 = (add_ln703_648_fu_1579_p2 + add_ln703_633_fu_1412_p2); + +assign add_ln703_650_fu_1590_p2 = (mult_640_V_reg_3716_pp0_iter6_reg + sub_ln703_677_fu_1306_p2); + +assign add_ln703_651_fu_1595_p2 = (mult_512_V_reg_3629_pp0_iter6_reg + sub_ln703_628_fu_1018_p2); + +assign add_ln703_652_fu_1600_p2 = (add_ln703_651_fu_1595_p2 + add_ln703_633_fu_1412_p2); + +assign add_ln703_653_fu_1651_p2 = (mult_640_V_reg_3716_pp0_iter6_reg + sub_ln703_687_fu_1378_p2); + +assign add_ln703_654_fu_1661_p2 = (mult_512_V_reg_3629_pp0_iter6_reg + sub_ln703_603_fu_948_p2); + +assign add_ln703_655_fu_910_p2 = (mult_704_V_reg_3765_pp0_iter5_reg + mult_640_V_reg_3716_pp0_iter5_reg); + +assign add_ln703_656_fu_1666_p2 = (mult_576_V_reg_3674_pp0_iter6_reg + add_ln703_655_reg_4558); + +assign add_ln703_657_fu_1670_p2 = (add_ln703_654_fu_1661_p2 + add_ln703_656_fu_1666_p2); + +assign add_ln703_658_fu_1696_p2 = (mult_704_V_reg_3765_pp0_iter6_reg + sub_ln703_694_fu_1443_p2); + +assign add_ln703_659_fu_914_p2 = (sub_ln703_563_fu_514_p2 + add_ln703_581_fu_744_p2); + +assign add_ln703_660_fu_1706_p2 = (add_ln703_611_reg_4521 + add_ln703_655_reg_4558); + +assign add_ln703_661_fu_1710_p2 = (add_ln703_659_reg_4568 + add_ln703_660_fu_1706_p2); + +assign add_ln703_662_fu_1730_p2 = (mult_512_V_reg_3629_pp0_iter6_reg + sub_ln703_614_fu_973_p2); + +assign add_ln703_663_fu_1735_p2 = (add_ln703_662_fu_1730_p2 + add_ln703_656_fu_1666_p2); + +assign add_ln703_664_fu_1991_p2 = (mult_704_V_reg_3765_pp0_iter7_reg + sub_ln703_699_reg_4618); + +assign add_ln703_665_fu_1746_p2 = (mult_512_V_reg_3629_pp0_iter6_reg + sub_ln703_619_fu_989_p2); + +assign add_ln703_666_fu_1751_p2 = (add_ln703_665_fu_1746_p2 + add_ln703_656_fu_1666_p2); + +assign add_ln703_667_fu_1767_p2 = (sub_ln703_675_fu_1301_p2 + add_ln703_655_reg_4558); + +assign add_ln703_668_fu_2035_p2 = (mult_704_V_reg_3765_pp0_iter7_reg + sub_ln703_712_reg_4688); + +assign add_ln703_669_fu_1787_p2 = (sub_ln703_680_fu_1335_p2 + add_ln703_655_reg_4558); + +assign add_ln703_670_fu_1802_p2 = (sub_ln703_685_fu_1370_p2 + add_ln703_655_reg_4558); + +assign add_ln703_671_fu_2047_p2 = (mult_704_V_reg_3765_pp0_iter7_reg + sub_ln703_718_reg_4708); + +assign add_ln703_672_fu_1812_p2 = (mult_704_V_reg_3765_pp0_iter6_reg + sub_ln703_719_fu_1656_p2); + +assign add_ln703_673_fu_2068_p2 = (mult_770_V_reg_3814_pp0_iter7_reg + sub_ln703_725_reg_4728); + +assign add_ln703_674_fu_1822_p2 = (mult_770_V_reg_3814_pp0_iter6_reg + mult_704_V_reg_3765_pp0_iter6_reg); + +assign add_ln703_675_fu_2072_p2 = (sub_ln703_692_reg_4598 + add_ln703_674_reg_4839); + +assign add_ln703_676_fu_2093_p2 = (sub_ln703_695_reg_4613 + add_ln703_674_reg_4839); + +assign add_ln703_677_fu_2101_p2 = (mult_770_V_reg_3814_pp0_iter7_reg + sub_ln703_730_reg_4754); + +assign add_ln703_678_fu_2109_p2 = (mult_770_V_reg_3814_pp0_iter7_reg + sub_ln703_732_reg_4769); + +assign add_ln703_679_fu_1826_p2 = (sub_ln703_698_fu_1490_p2 + add_ln703_674_fu_1822_p2); + +assign add_ln703_680_fu_2118_p2 = (mult_770_V_reg_3814_pp0_iter7_reg + sub_ln703_736_fu_2007_p2); + +assign add_ln703_681_fu_2132_p2 = (mult_770_V_reg_3814_pp0_iter7_reg + sub_ln703_727_reg_4738); + +assign add_ln703_682_fu_2136_p2 = (mult_770_V_reg_3814_pp0_iter7_reg + sub_ln703_740_fu_2019_p2); + +assign add_ln703_683_fu_2146_p2 = (mult_770_V_reg_3814_pp0_iter7_reg + sub_ln703_742_reg_4779); + +assign add_ln703_684_fu_2154_p2 = (mult_770_V_reg_3814_pp0_iter7_reg + sub_ln703_743_reg_4789); + +assign add_ln703_685_fu_1837_p2 = (mult_576_V_reg_3674_pp0_iter6_reg + sub_ln703_654_fu_1145_p2); + +assign add_ln703_686_fu_1842_p2 = (mult_640_V_reg_3716_pp0_iter6_reg + add_ln703_674_fu_1822_p2); + +assign add_ln703_687_fu_1847_p2 = (add_ln703_685_fu_1837_p2 + add_ln703_686_fu_1842_p2); + +assign add_ln703_688_fu_1853_p2 = (mult_640_V_reg_3716_pp0_iter6_reg + sub_ln703_679_fu_1330_p2); + +assign add_ln703_689_fu_2181_p2 = (add_ln703_688_reg_4862 + add_ln703_674_reg_4839); + +assign add_ln703_690_fu_2189_p2 = (mult_770_V_reg_3814_pp0_iter7_reg + sub_ln703_748_reg_4809); + +assign add_ln703_691_fu_2193_p2 = (sub_ln703_714_reg_4693 + add_ln703_674_reg_4839); + +assign add_ln703_692_fu_920_p2 = (mult_832_V_reg_3861_pp0_iter5_reg + mult_770_V_reg_3814_pp0_iter5_reg); + +assign add_ln703_693_fu_2229_p2 = (sub_ln703_721_fu_1975_p2 + add_ln703_692_reg_4573_pp0_iter7_reg); + +assign add_ln703_694_fu_2234_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_755_fu_2055_p2); + +assign add_ln703_695_fu_2239_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_757_fu_2064_p2); + +assign add_ln703_696_fu_2264_p2 = (sub_ln703_728_fu_1987_p2 + add_ln703_692_reg_4573_pp0_iter7_reg); + +assign add_ln703_697_fu_2269_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_761_fu_2089_p2); + +assign add_ln703_698_fu_2279_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_762_fu_2097_p2); + +assign add_ln703_699_fu_2289_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_763_fu_2105_p2); + +assign add_ln703_700_fu_2303_p2 = (sub_ln703_733_fu_1995_p2 + add_ln703_692_reg_4573_pp0_iter7_reg); + +assign add_ln703_701_fu_2308_p2 = (sub_ln703_734_fu_1999_p2 + add_ln703_692_reg_4573_pp0_iter7_reg); + +assign add_ln703_702_fu_2313_p2 = (sub_ln703_735_fu_2003_p2 + add_ln703_692_reg_4573_pp0_iter7_reg); + +assign add_ln703_703_fu_1858_p2 = (mult_386_V_reg_3539_pp0_iter6_reg + sub_ln703_567_reg_4303); + +assign add_ln703_704_fu_1862_p2 = (add_ln703_703_fu_1858_p2 + add_ln703_597_reg_4282_pp0_iter6_reg); + +assign add_ln703_705_fu_1867_p2 = (mult_704_V_reg_3765_pp0_iter6_reg + add_ln703_692_reg_4573); + +assign add_ln703_706_fu_1871_p2 = (add_ln703_633_fu_1412_p2 + add_ln703_705_fu_1867_p2); + +assign add_ln703_707_fu_1877_p2 = (add_ln703_704_fu_1862_p2 + add_ln703_706_fu_1871_p2); + +assign add_ln703_708_fu_2323_p2 = (mult_704_V_reg_3765_pp0_iter7_reg + sub_ln703_704_reg_4643); + +assign add_ln703_709_fu_2327_p2 = (add_ln703_708_fu_2323_p2 + add_ln703_692_reg_4573_pp0_iter7_reg); + +assign add_ln703_710_fu_1883_p2 = (mult_640_V_reg_3716_pp0_iter6_reg + sub_ln703_671_reg_4543); + +assign add_ln703_711_fu_1887_p2 = (add_ln703_710_fu_1883_p2 + add_ln703_705_fu_1867_p2); + +assign add_ln703_712_fu_2332_p2 = (sub_ln703_737_fu_2011_p2 + add_ln703_692_reg_4573_pp0_iter7_reg); + +assign add_ln703_713_fu_2337_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_766_fu_2123_p2); + +assign add_ln703_714_fu_1893_p2 = (sub_ln703_622_fu_997_p2 + add_ln703_611_reg_4521); + +assign add_ln703_715_fu_1898_p2 = (add_ln703_655_reg_4558 + add_ln703_692_reg_4573); + +assign add_ln703_716_fu_1902_p2 = (add_ln703_714_fu_1893_p2 + add_ln703_715_fu_1898_p2); + +assign add_ln703_717_fu_2342_p2 = (mult_704_V_reg_3765_pp0_iter7_reg + sub_ln703_706_reg_4653); + +assign add_ln703_718_fu_2346_p2 = (add_ln703_717_fu_2342_p2 + add_ln703_692_reg_4573_pp0_iter7_reg); + +assign add_ln703_719_fu_2361_p2 = (mult_704_V_reg_3765_pp0_iter7_reg + sub_ln703_708_reg_4668); + +assign add_ln703_720_fu_2365_p2 = (add_ln703_719_fu_2361_p2 + add_ln703_692_reg_4573_pp0_iter7_reg); + +assign add_ln703_721_fu_1908_p2 = (mult_640_V_reg_3716_pp0_iter6_reg + sub_ln703_673_fu_1291_p2); + +assign add_ln703_722_fu_1913_p2 = (add_ln703_721_fu_1908_p2 + add_ln703_705_fu_1867_p2); + +assign add_ln703_723_fu_1919_p2 = (mult_640_V_reg_3716_pp0_iter6_reg + sub_ln703_676_reg_4548); + +assign add_ln703_724_fu_1923_p2 = (add_ln703_723_fu_1919_p2 + add_ln703_705_fu_1867_p2); + +assign add_ln703_725_fu_2389_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_770_fu_2158_p2); + +assign add_ln703_726_fu_1929_p2 = (sub_ln703_660_reg_4506 + add_ln703_633_fu_1412_p2); + +assign add_ln703_727_fu_1934_p2 = (add_ln703_726_fu_1929_p2 + add_ln703_705_fu_1867_p2); + +assign add_ln703_728_fu_1940_p2 = (sub_ln703_633_fu_1043_p2 + add_ln703_611_reg_4521); + +assign add_ln703_729_fu_1945_p2 = (add_ln703_728_fu_1940_p2 + add_ln703_715_fu_1898_p2); + +assign add_ln703_730_fu_2424_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_779_fu_2211_p2); + +assign add_ln703_731_fu_1951_p2 = (mult_640_V_reg_3716_pp0_iter6_reg + sub_ln703_688_fu_1382_p2); + +assign add_ln703_732_fu_1956_p2 = (add_ln703_731_fu_1951_p2 + add_ln703_705_fu_1867_p2); + +assign add_ln703_733_fu_2434_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_781_fu_2220_p2); + +assign add_ln703_734_fu_2469_p2 = (mult_896_V_reg_3909_pp0_iter7_reg + sub_ln703_786_fu_2259_p2); + +assign add_ln703_735_fu_2484_p2 = (mult_896_V_reg_3909_pp0_iter7_reg + sub_ln703_787_fu_2274_p2); + +assign add_ln703_736_fu_2504_p2 = (mult_896_V_reg_3909_pp0_iter7_reg + sub_ln703_789_fu_2294_p2); + +assign add_ln703_737_fu_1962_p2 = (mult_896_V_reg_3909_pp0_iter6_reg + mult_832_V_reg_3861_pp0_iter6_reg); + +assign add_ln703_738_fu_2528_p2 = (sub_ln703_765_reg_4852 + add_ln703_737_reg_4907); + +assign add_ln703_739_fu_1966_p2 = (mult_704_V_reg_3765_pp0_iter6_reg + sub_ln703_703_fu_1519_p2); + +assign add_ln703_740_fu_2532_p2 = (mult_770_V_reg_3814_pp0_iter7_reg + add_ln703_737_reg_4907); + +assign add_ln703_741_fu_2536_p2 = (add_ln703_739_reg_4915 + add_ln703_740_fu_2532_p2); + +assign add_ln703_742_fu_2569_p2 = (mult_896_V_reg_3909_pp0_iter7_reg + sub_ln703_792_fu_2351_p2); + +assign add_ln703_743_fu_2583_p2 = (sub_ln703_768_fu_2141_p2 + add_ln703_737_reg_4907); + +assign add_ln703_744_fu_2612_p2 = (mult_896_V_reg_3909_pp0_iter7_reg + sub_ln703_798_fu_2394_p2); + +assign add_ln703_745_fu_2617_p2 = (mult_896_V_reg_3909_pp0_iter7_reg + sub_ln703_799_fu_2399_p2); + +assign add_ln703_746_fu_2622_p2 = (mult_896_V_reg_3909_pp0_iter7_reg + sub_ln703_800_fu_2404_p2); + +assign add_ln703_747_fu_2627_p2 = (mult_896_V_reg_3909_pp0_iter7_reg + sub_ln703_801_fu_2409_p2); + +assign add_ln703_748_fu_2632_p2 = (mult_896_V_reg_3909_pp0_iter7_reg + sub_ln703_802_fu_2414_p2); + +assign add_ln703_749_fu_2637_p2 = (sub_ln703_776_fu_2197_p2 + add_ln703_737_reg_4907); + +assign add_ln703_750_fu_2669_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_753_reg_4834); + +assign add_ln703_751_fu_1971_p2 = (mult_960_V_reg_3958_pp0_iter6_reg + mult_896_V_reg_3909_pp0_iter6_reg); + +assign add_ln703_752_fu_2673_p2 = (add_ln703_750_fu_2669_p2 + add_ln703_751_reg_4920); + +assign add_ln703_754_fu_2693_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_756_fu_2059_p2); + +assign add_ln703_758_fu_2728_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_760_fu_2085_p2); + +assign add_ln703_761_fu_2763_p2 = (mult_770_V_reg_3814_pp0_iter7_reg + sub_ln703_731_reg_4759); + +assign add_ln703_762_fu_2767_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + add_ln703_751_reg_4920); + +assign add_ln703_765_fu_2792_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_764_fu_2113_p2); + +assign add_ln703_770_fu_2867_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_767_fu_2127_p2); + +assign add_ln703_776_fu_2937_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_772_fu_2166_p2); + +assign add_ln703_778_fu_2947_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_773_fu_2171_p2); + +assign add_ln703_780_fu_2957_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_774_fu_2176_p2); + +assign add_ln703_782_fu_2992_p2 = (mult_832_V_reg_3861_pp0_iter7_reg + sub_ln703_777_fu_2202_p2); + +assign add_ln703_786_fu_3027_p2 = (mult_770_V_reg_3814_pp0_iter7_reg + sub_ln703_752_reg_4824); + +assign add_ln703_fu_242_p2 = (tmp_2_fu_92_p4 + trunc_ln203_fu_88_p1); + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign sub_ln703_531_fu_252_p2 = (tmp_2_reg_3437 - trunc_ln203_reg_3431); + +assign sub_ln703_532_fu_276_p2 = (sub_ln703_reg_4017_pp0_iter2_reg - tmp_3_reg_3443_pp0_iter2_reg); + +assign sub_ln703_533_fu_264_p2 = (sub_ln703_531_reg_4023 - tmp_3_reg_3443_pp0_iter1_reg); + +assign sub_ln703_534_fu_256_p2 = (add_ln703_reg_4010 - tmp_3_reg_3443); + +assign sub_ln703_535_fu_284_p2 = (tmp_3_reg_3443_pp0_iter2_reg - add_ln703_reg_4010_pp0_iter2_reg); + +assign sub_ln703_536_fu_340_p2 = (sub_ln703_532_reg_4061_pp0_iter4_reg - tmp_4_reg_3454_pp0_iter4_reg); + +assign sub_ln703_537_fu_292_p2 = (sub_ln703_533_reg_4042 - tmp_4_reg_3454_pp0_iter2_reg); + +assign sub_ln703_538_fu_268_p2 = (sub_ln703_534_reg_4029 - tmp_4_reg_3454_pp0_iter1_reg); + +assign sub_ln703_539_fu_344_p2 = (add_ln703_538_reg_4067_pp0_iter4_reg - tmp_4_reg_3454_pp0_iter4_reg); + +assign sub_ln703_540_fu_308_p2 = (tmp_4_reg_3454_pp0_iter3_reg - add_ln703_539_reg_4035_pp0_iter3_reg); + +assign sub_ln703_541_fu_356_p2 = (add_ln703_540_reg_4079_pp0_iter4_reg - tmp_4_reg_3454_pp0_iter4_reg); + +assign sub_ln703_542_fu_360_p2 = (sub_ln703_535_reg_4073_pp0_iter4_reg - tmp_4_reg_3454_pp0_iter4_reg); + +assign sub_ln703_543_fu_296_p2 = (add_ln703_539_reg_4035_pp0_iter2_reg - tmp_4_reg_3454_pp0_iter2_reg); + +assign sub_ln703_544_fu_316_p2 = (sub_ln703_537_reg_4085 - mult_307_V_reg_3472_pp0_iter3_reg); + +assign sub_ln703_545_fu_300_p2 = (sub_ln703_538_reg_4048 - mult_307_V_reg_3472_pp0_iter2_reg); + +assign sub_ln703_546_fu_442_p2 = (sub_ln703_539_reg_4165 - mult_307_V_reg_3472_pp0_iter5_reg); + +assign sub_ln703_547_fu_446_p2 = (add_ln703_541_reg_4171 - mult_307_V_reg_3472_pp0_iter5_reg); + +assign sub_ln703_548_fu_450_p2 = (add_ln703_542_reg_4177 - mult_307_V_reg_3472_pp0_iter5_reg); + +assign sub_ln703_549_fu_372_p2 = (add_ln703_543_reg_4054_pp0_iter4_reg - mult_307_V_reg_3472_pp0_iter4_reg); + +assign sub_ln703_550_fu_376_p2 = (mult_307_V_reg_3472_pp0_iter4_reg - add_ln703_543_reg_4054_pp0_iter4_reg); + +assign sub_ln703_551_fu_380_p2 = (sub_ln703_540_reg_4110 - mult_307_V_reg_3472_pp0_iter4_reg); + +assign sub_ln703_552_fu_388_p2 = (sub_ln703_541_fu_356_p2 - mult_307_V_reg_3472_pp0_iter4_reg); + +assign sub_ln703_553_fu_462_p2 = (add_ln703_544_reg_4116_pp0_iter5_reg - mult_307_V_reg_3472_pp0_iter5_reg); + +assign sub_ln703_554_fu_398_p2 = (sub_ln703_543_reg_4091_pp0_iter4_reg - mult_307_V_reg_3472_pp0_iter4_reg); + +assign sub_ln703_555_fu_470_p2 = (sub_ln703_536_reg_4159 - mult_307_V_reg_3472_pp0_iter5_reg); + +assign sub_ln703_556_fu_474_p2 = (add_ln703_545_reg_4183 - mult_307_V_reg_3472_pp0_iter5_reg); + +assign sub_ln703_557_fu_402_p2 = (sub_ln703_544_reg_4122 - mult_320_V_reg_3500_pp0_iter4_reg); + +assign sub_ln703_558_fu_328_p2 = (sub_ln703_545_reg_4097 - mult_320_V_reg_3500_pp0_iter3_reg); + +assign sub_ln703_559_fu_483_p2 = (sub_ln703_546_fu_442_p2 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_560_fu_493_p2 = (sub_ln703_548_fu_450_p2 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_561_fu_502_p2 = (sub_ln703_549_reg_4194 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_562_fu_506_p2 = (sub_ln703_550_reg_4200 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_563_fu_514_p2 = (add_ln703_550_reg_4211 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_564_fu_518_p2 = (mult_320_V_reg_3500_pp0_iter5_reg - add_ln703_549_reg_4103_pp0_iter5_reg); + +assign sub_ln703_565_fu_530_p2 = (add_ln703_552_fu_454_p2 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_566_fu_535_p2 = (add_ln703_553_fu_458_p2 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_567_fu_540_p2 = (sub_ln703_553_fu_462_p2 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_568_fu_545_p2 = (sub_ln703_551_reg_4205 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_569_fu_549_p2 = (add_ln703_546_fu_438_p2 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_570_fu_410_p2 = (add_ln703_554_reg_4134 - mult_320_V_reg_3500_pp0_iter4_reg); + +assign sub_ln703_571_fu_558_p2 = (add_ln703_555_fu_466_p2 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_572_fu_563_p2 = (sub_ln703_554_reg_4228 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_573_fu_567_p2 = (sub_ln703_555_fu_470_p2 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_574_fu_572_p2 = (sub_ln703_556_fu_474_p2 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_575_fu_577_p2 = (add_ln703_548_reg_4188 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_576_fu_414_p2 = (add_ln703_549_reg_4103_pp0_iter4_reg - mult_320_V_reg_3500_pp0_iter4_reg); + +assign sub_ln703_577_fu_581_p2 = (add_ln703_551_reg_4222 - mult_320_V_reg_3500_pp0_iter5_reg); + +assign sub_ln703_578_fu_585_p2 = (add_ln703_556_fu_478_p2 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_579_fu_590_p2 = (sub_ln703_557_reg_4234 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_580_fu_594_p2 = (sub_ln703_559_fu_483_p2 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_581_fu_924_p2 = (add_ln703_557_reg_4293 - mult_386_V_reg_3539_pp0_iter6_reg); + +assign sub_ln703_582_fu_599_p2 = (sub_ln703_560_fu_493_p2 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_583_fu_604_p2 = (add_ln703_558_fu_498_p2 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_584_fu_422_p2 = (add_ln703_559_reg_4146 - mult_386_V_reg_3539_pp0_iter4_reg); + +assign sub_ln703_585_fu_609_p2 = (sub_ln703_561_fu_502_p2 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_586_fu_614_p2 = (sub_ln703_562_fu_506_p2 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_587_fu_619_p2 = (add_ln703_561_fu_510_p2 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_588_fu_624_p2 = (add_ln703_562_fu_522_p2 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_589_fu_638_p2 = (add_ln703_563_fu_526_p2 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_590_fu_643_p2 = (sub_ln703_565_fu_530_p2 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_591_fu_430_p2 = (mult_386_V_reg_3539_pp0_iter4_reg - add_ln703_559_reg_4146); + +assign sub_ln703_592_fu_653_p2 = (sub_ln703_558_reg_4140_pp0_iter5_reg - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_593_fu_661_p2 = (sub_ln703_568_fu_545_p2 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_594_fu_666_p2 = (add_ln703_564_reg_4240 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_595_fu_928_p2 = (sub_ln703_567_reg_4303 - mult_386_V_reg_3539_pp0_iter6_reg); + +assign sub_ln703_596_fu_683_p2 = (add_ln703_565_fu_554_p2 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_597_fu_688_p2 = (sub_ln703_571_fu_558_p2 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_598_fu_932_p2 = (sub_ln703_572_reg_4309 - mult_386_V_reg_3539_pp0_iter6_reg); + +assign sub_ln703_599_fu_693_p2 = (sub_ln703_573_fu_567_p2 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_600_fu_936_p2 = (sub_ln703_574_reg_4314 - mult_386_V_reg_3539_pp0_iter6_reg); + +assign sub_ln703_601_fu_940_p2 = (sub_ln703_576_reg_4252_pp0_iter6_reg - mult_386_V_reg_3539_pp0_iter6_reg); + +assign sub_ln703_602_fu_712_p2 = (sub_ln703_570_reg_4246 - mult_386_V_reg_3539_pp0_iter5_reg); + +assign sub_ln703_603_fu_948_p2 = (sub_ln703_578_reg_4319 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_604_fu_952_p2 = (add_ln703_566_reg_4258_pp0_iter6_reg - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_605_fu_720_p2 = (sub_ln703_580_fu_594_p2 - mult_449_V_reg_3582_pp0_iter5_reg); + +assign sub_ln703_606_fu_956_p2 = (sub_ln703_581_fu_924_p2 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_607_fu_961_p2 = (sub_ln703_582_reg_4329 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_608_fu_725_p2 = (sub_ln703_583_fu_604_p2 - mult_449_V_reg_3582_pp0_iter5_reg); + +assign sub_ln703_609_fu_965_p2 = (sub_ln703_585_reg_4334 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_610_fu_734_p2 = (sub_ln703_586_fu_614_p2 - mult_449_V_reg_3582_pp0_iter5_reg); + +assign sub_ln703_611_fu_739_p2 = (sub_ln703_587_fu_619_p2 - mult_449_V_reg_3582_pp0_iter5_reg); + +assign sub_ln703_612_fu_969_p2 = (sub_ln703_588_reg_4350 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_613_fu_758_p2 = (add_ln703_569_fu_633_p2 - mult_449_V_reg_3582_pp0_iter5_reg); + +assign sub_ln703_614_fu_973_p2 = (sub_ln703_589_reg_4355 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_615_fu_977_p2 = (sub_ln703_590_reg_4361 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_616_fu_981_p2 = (sub_ln703_584_reg_4264_pp0_iter6_reg - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_617_fu_763_p2 = (add_ln703_570_fu_648_p2 - mult_449_V_reg_3582_pp0_iter5_reg); + +assign sub_ln703_618_fu_768_p2 = (sub_ln703_591_reg_4277 - mult_449_V_reg_3582_pp0_iter5_reg); + +assign sub_ln703_619_fu_989_p2 = (add_ln703_571_reg_4372 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_620_fu_772_p2 = (sub_ln703_593_fu_661_p2 - mult_449_V_reg_3582_pp0_iter5_reg); + +assign sub_ln703_621_fu_993_p2 = (sub_ln703_594_reg_4377 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_622_fu_997_p2 = (sub_ln703_595_fu_928_p2 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_623_fu_1002_p2 = (add_ln703_572_reg_4382 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_624_fu_1006_p2 = (add_ln703_573_reg_4387 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_625_fu_1010_p2 = (add_ln703_574_reg_4393 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_626_fu_1014_p2 = (sub_ln703_599_reg_4403 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_627_fu_807_p2 = (add_ln703_575_fu_698_p2 - mult_449_V_reg_3582_pp0_iter5_reg); + +assign sub_ln703_628_fu_1018_p2 = (sub_ln703_592_reg_4366 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_629_fu_1022_p2 = (sub_ln703_600_fu_936_p2 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_630_fu_1035_p2 = (add_ln703_576_reg_4408 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_631_fu_1039_p2 = (add_ln703_577_reg_4413 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_632_fu_818_p2 = (sub_ln703_602_fu_712_p2 - mult_449_V_reg_3582_pp0_iter5_reg); + +assign sub_ln703_633_fu_1043_p2 = (add_ln703_578_fu_944_p2 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_634_fu_1048_p2 = (add_ln703_579_reg_4418 - mult_449_V_reg_3582_pp0_iter6_reg); + +assign sub_ln703_635_fu_1056_p2 = (sub_ln703_605_reg_4423 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_636_fu_1060_p2 = (sub_ln703_607_fu_961_p2 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_637_fu_1065_p2 = (sub_ln703_608_reg_4428 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_638_fu_1069_p2 = (add_ln703_580_reg_4433 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_639_fu_1078_p2 = (sub_ln703_610_reg_4439 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_640_fu_1082_p2 = (sub_ln703_611_reg_4444 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_641_fu_838_p2 = (add_ln703_582_fu_748_p2 - mult_512_V_reg_3629_pp0_iter5_reg); + +assign sub_ln703_642_fu_1086_p2 = (sub_ln703_612_fu_969_p2 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_643_fu_1091_p2 = (add_ln703_583_reg_4450 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_644_fu_1095_p2 = (sub_ln703_613_reg_4455 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_645_fu_843_p2 = (sub_ln703_618_fu_768_p2 - mult_512_V_reg_3629_pp0_iter5_reg); + +assign sub_ln703_646_fu_1099_p2 = (add_ln703_584_fu_985_p2 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_647_fu_1104_p2 = (sub_ln703_620_reg_4466 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_648_fu_1108_p2 = (sub_ln703_621_fu_993_p2 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_649_fu_1113_p2 = (sub_ln703_623_fu_1002_p2 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_650_fu_1118_p2 = (add_ln703_587_reg_4471 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_651_fu_1122_p2 = (sub_ln703_624_fu_1006_p2 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_652_fu_1127_p2 = (sub_ln703_625_fu_1010_p2 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_653_fu_1136_p2 = (add_ln703_588_reg_4476 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_654_fu_1145_p2 = (add_ln703_590_reg_4481 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_655_fu_1149_p2 = (sub_ln703_627_reg_4486 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_656_fu_1153_p2 = (add_ln703_591_fu_1027_p2 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_657_fu_1158_p2 = (add_ln703_592_fu_1031_p2 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_658_fu_1167_p2 = (sub_ln703_617_reg_4460 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_659_fu_1171_p2 = (sub_ln703_630_fu_1035_p2 - mult_512_V_reg_3629_pp0_iter6_reg); + +assign sub_ln703_660_fu_872_p2 = (add_ln703_593_fu_812_p2 - mult_512_V_reg_3629_pp0_iter5_reg); + +assign sub_ln703_661_fu_877_p2 = (add_ln703_594_fu_823_p2 - mult_512_V_reg_3629_pp0_iter5_reg); + +assign sub_ln703_662_fu_882_p2 = (add_ln703_596_fu_832_p2 - mult_512_V_reg_3629_pp0_iter5_reg); + +assign sub_ln703_663_fu_1189_p2 = (add_ln703_598_fu_1052_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_664_fu_1199_p2 = (sub_ln703_635_fu_1056_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_665_fu_1204_p2 = (sub_ln703_637_fu_1065_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_666_fu_1214_p2 = (add_ln703_599_fu_1073_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_667_fu_1224_p2 = (sub_ln703_641_reg_4496 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_668_fu_1233_p2 = (sub_ln703_644_fu_1095_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_669_fu_1261_p2 = (sub_ln703_636_fu_1060_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_670_fu_1266_p2 = (sub_ln703_647_fu_1104_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_671_fu_896_p2 = (add_ln703_602_fu_856_p2 - mult_576_V_reg_3674_pp0_iter5_reg); + +assign sub_ln703_672_fu_1281_p2 = (sub_ln703_651_fu_1122_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_673_fu_1291_p2 = (add_ln703_603_fu_1132_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_674_fu_1296_p2 = (sub_ln703_653_fu_1136_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_675_fu_1301_p2 = (add_ln703_604_fu_1140_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_676_fu_901_p2 = (add_ln703_606_fu_866_p2 - mult_576_V_reg_3674_pp0_iter5_reg); + +assign sub_ln703_677_fu_1306_p2 = (sub_ln703_655_fu_1149_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_678_fu_1316_p2 = (sub_ln703_656_fu_1153_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_679_fu_1330_p2 = (sub_ln703_657_fu_1158_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_680_fu_1335_p2 = (add_ln703_607_fu_1163_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_681_fu_1340_p2 = (sub_ln703_658_fu_1167_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_682_fu_1345_p2 = (sub_ln703_659_fu_1171_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_683_fu_1360_p2 = (add_ln703_608_fu_1176_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_684_fu_1365_p2 = (add_ln703_609_fu_1181_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_685_fu_1370_p2 = (sub_ln703_661_reg_4511 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_686_fu_1374_p2 = (sub_ln703_662_reg_4516 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_687_fu_1378_p2 = (sub_ln703_645_reg_4501 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_688_fu_1382_p2 = (add_ln703_610_fu_1185_p2 - mult_576_V_reg_3674_pp0_iter6_reg); + +assign sub_ln703_689_fu_1392_p2 = (sub_ln703_663_fu_1189_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_690_fu_1402_p2 = (sub_ln703_664_fu_1199_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_691_fu_1428_p2 = (sub_ln703_665_fu_1204_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_692_fu_1433_p2 = (add_ln703_613_fu_1209_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_693_fu_1438_p2 = (sub_ln703_666_fu_1214_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_694_fu_1443_p2 = (add_ln703_614_fu_1219_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_695_fu_1464_p2 = (sub_ln703_667_fu_1224_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_696_fu_1475_p2 = (add_ln703_615_fu_1228_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_697_fu_1485_p2 = (add_ln703_616_fu_1238_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_698_fu_1490_p2 = (add_ln703_617_fu_1243_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_699_fu_1495_p2 = (add_ln703_618_fu_1248_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_700_fu_1500_p2 = (add_ln703_619_fu_1252_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_701_fu_1509_p2 = (add_ln703_621_fu_1256_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_702_fu_1514_p2 = (sub_ln703_669_fu_1261_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_703_fu_1519_p2 = (sub_ln703_670_fu_1266_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_704_fu_1524_p2 = (add_ln703_622_fu_1271_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_705_fu_1544_p2 = (add_ln703_620_reg_4537 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_706_fu_1548_p2 = (add_ln703_623_fu_1276_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_707_fu_1559_p2 = (sub_ln703_672_fu_1281_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_708_fu_1564_p2 = (add_ln703_624_fu_1286_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_709_fu_1569_p2 = (add_ln703_612_fu_1194_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_710_fu_1606_p2 = (add_ln703_625_fu_1311_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_711_fu_1611_p2 = (sub_ln703_678_fu_1316_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_712_fu_1616_p2 = (add_ln703_627_fu_1325_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_713_fu_1621_p2 = (sub_ln703_681_fu_1340_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_714_fu_1626_p2 = (sub_ln703_682_fu_1345_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_715_fu_1631_p2 = (add_ln703_629_fu_1355_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_716_fu_1636_p2 = (sub_ln703_683_fu_1360_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_717_fu_1641_p2 = (sub_ln703_684_fu_1365_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_718_fu_1646_p2 = (sub_ln703_686_fu_1374_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_719_fu_1656_p2 = (add_ln703_630_fu_1387_p2 - mult_640_V_reg_3716_pp0_iter6_reg); + +assign sub_ln703_720_fu_1676_p2 = (sub_ln703_689_fu_1392_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_721_fu_1975_p2 = (add_ln703_631_reg_4588 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_722_fu_1681_p2 = (sub_ln703_690_fu_1402_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_723_fu_1979_p2 = (add_ln703_634_reg_4593 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_724_fu_1686_p2 = (add_ln703_635_fu_1422_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_725_fu_1691_p2 = (sub_ln703_691_fu_1428_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_726_fu_1983_p2 = (sub_ln703_693_reg_4603 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_727_fu_1701_p2 = (add_ln703_636_fu_1448_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_728_fu_1987_p2 = (add_ln703_639_reg_4608 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_729_fu_1715_p2 = (add_ln703_640_fu_1469_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_730_fu_1720_p2 = (sub_ln703_696_fu_1475_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_731_fu_1725_p2 = (add_ln703_641_fu_1480_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_732_fu_1741_p2 = (sub_ln703_697_fu_1485_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_733_fu_1995_p2 = (sub_ln703_700_reg_4623 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_734_fu_1999_p2 = (add_ln703_642_reg_4628 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_735_fu_2003_p2 = (sub_ln703_701_reg_4633 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_736_fu_2007_p2 = (sub_ln703_702_reg_4638 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_737_fu_2011_p2 = (add_ln703_645_reg_4648 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_738_fu_1757_p2 = (sub_ln703_705_fu_1544_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_739_fu_2015_p2 = (add_ln703_646_reg_4658 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_740_fu_2019_p2 = (sub_ln703_707_reg_4663 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_741_fu_2023_p2 = (sub_ln703_709_reg_4673 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_742_fu_1762_p2 = (add_ln703_647_fu_1574_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_743_fu_1772_p2 = (add_ln703_649_fu_1584_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_744_fu_1777_p2 = (add_ln703_650_fu_1590_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_745_fu_1782_p2 = (add_ln703_652_fu_1600_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_746_fu_2027_p2 = (sub_ln703_710_reg_4678 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_747_fu_2031_p2 = (sub_ln703_711_reg_4683 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_748_fu_1792_p2 = (sub_ln703_713_fu_1621_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_749_fu_2039_p2 = (sub_ln703_715_reg_4698 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_750_fu_2043_p2 = (sub_ln703_716_reg_4703 - mult_704_V_reg_3765_pp0_iter7_reg); + +assign sub_ln703_751_fu_1797_p2 = (sub_ln703_717_fu_1641_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_752_fu_1807_p2 = (add_ln703_653_fu_1651_p2 - mult_704_V_reg_3765_pp0_iter6_reg); + +assign sub_ln703_753_fu_1817_p2 = (add_ln703_657_fu_1670_p2 - mult_770_V_reg_3814_pp0_iter6_reg); + +assign sub_ln703_754_fu_2051_p2 = (sub_ln703_720_reg_4713 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_755_fu_2055_p2 = (sub_ln703_722_reg_4718 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_756_fu_2059_p2 = (sub_ln703_723_fu_1979_p2 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_757_fu_2064_p2 = (sub_ln703_724_reg_4723 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_758_fu_2076_p2 = (sub_ln703_726_fu_1983_p2 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_759_fu_2081_p2 = (add_ln703_658_reg_4733 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_760_fu_2085_p2 = (sub_ln703_727_reg_4738 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_761_fu_2089_p2 = (add_ln703_661_reg_4744 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_762_fu_2097_p2 = (sub_ln703_729_reg_4749 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_763_fu_2105_p2 = (add_ln703_663_reg_4764 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_764_fu_2113_p2 = (add_ln703_664_fu_1991_p2 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_765_fu_1832_p2 = (add_ln703_666_fu_1751_p2 - mult_770_V_reg_3814_pp0_iter6_reg); + +assign sub_ln703_766_fu_2123_p2 = (sub_ln703_738_reg_4774 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_767_fu_2127_p2 = (sub_ln703_739_fu_2015_p2 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_768_fu_2141_p2 = (sub_ln703_741_fu_2023_p2 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_769_fu_2150_p2 = (add_ln703_667_reg_4784 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_770_fu_2158_p2 = (sub_ln703_744_reg_4794 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_771_fu_2162_p2 = (sub_ln703_745_reg_4799 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_772_fu_2166_p2 = (sub_ln703_746_fu_2027_p2 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_773_fu_2171_p2 = (sub_ln703_747_fu_2031_p2 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_774_fu_2176_p2 = (add_ln703_668_fu_2035_p2 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_775_fu_2185_p2 = (add_ln703_669_reg_4804 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_776_fu_2197_p2 = (sub_ln703_749_fu_2039_p2 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_777_fu_2202_p2 = (sub_ln703_750_fu_2043_p2 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_778_fu_2207_p2 = (sub_ln703_751_reg_4814 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_779_fu_2211_p2 = (add_ln703_670_reg_4819 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_780_fu_2215_p2 = (add_ln703_671_fu_2047_p2 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_781_fu_2220_p2 = (add_ln703_672_reg_4829 - mult_770_V_reg_3814_pp0_iter7_reg); + +assign sub_ln703_782_fu_2224_p2 = (sub_ln703_754_fu_2051_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_783_fu_2244_p2 = (add_ln703_673_fu_2068_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_784_fu_2249_p2 = (add_ln703_675_fu_2072_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_785_fu_2254_p2 = (sub_ln703_758_fu_2076_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_786_fu_2259_p2 = (sub_ln703_759_fu_2081_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_787_fu_2274_p2 = (add_ln703_676_fu_2093_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_788_fu_2284_p2 = (add_ln703_677_fu_2101_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_789_fu_2294_p2 = (add_ln703_678_fu_2109_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_790_fu_2299_p2 = (add_ln703_679_reg_4847 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_791_fu_2318_p2 = (add_ln703_680_fu_2118_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_792_fu_2351_p2 = (add_ln703_681_fu_2132_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_793_fu_2356_p2 = (add_ln703_682_fu_2136_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_794_fu_2370_p2 = (add_ln703_683_fu_2146_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_795_fu_2375_p2 = (sub_ln703_769_fu_2150_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_796_fu_2380_p2 = (add_ln703_684_fu_2154_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_797_fu_2385_p2 = (add_ln703_687_reg_4857 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_798_fu_2394_p2 = (sub_ln703_771_fu_2162_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_799_fu_2399_p2 = (add_ln703_689_fu_2181_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_800_fu_2404_p2 = (sub_ln703_775_fu_2185_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_801_fu_2409_p2 = (add_ln703_690_fu_2189_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_802_fu_2414_p2 = (add_ln703_691_fu_2193_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_803_fu_2419_p2 = (sub_ln703_778_fu_2207_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_804_fu_2429_p2 = (sub_ln703_780_fu_2215_p2 - mult_832_V_reg_3861_pp0_iter7_reg); + +assign sub_ln703_805_fu_2439_p2 = (sub_ln703_782_fu_2224_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_806_fu_2444_p2 = (add_ln703_693_fu_2229_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_807_fu_2449_p2 = (add_ln703_694_fu_2234_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_808_fu_2454_p2 = (add_ln703_695_fu_2239_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_809_fu_2459_p2 = (sub_ln703_783_fu_2244_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_810_fu_2464_p2 = (sub_ln703_784_fu_2249_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_811_fu_2474_p2 = (add_ln703_696_fu_2264_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_812_fu_2479_p2 = (add_ln703_697_fu_2269_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_813_fu_2489_p2 = (add_ln703_698_fu_2279_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_814_fu_2494_p2 = (sub_ln703_788_fu_2284_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_815_fu_2499_p2 = (add_ln703_699_fu_2289_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_816_fu_2509_p2 = (add_ln703_700_fu_2303_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_817_fu_2514_p2 = (add_ln703_701_fu_2308_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_818_fu_2519_p2 = (add_ln703_702_fu_2313_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_819_fu_2524_p2 = (add_ln703_707_reg_4867 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_820_fu_2541_p2 = (add_ln703_709_fu_2327_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_821_fu_2546_p2 = (add_ln703_711_reg_4872 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_822_fu_2550_p2 = (add_ln703_712_fu_2332_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_823_fu_2555_p2 = (add_ln703_713_fu_2337_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_824_fu_2560_p2 = (add_ln703_716_reg_4877 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_825_fu_2564_p2 = (add_ln703_718_fu_2346_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_826_fu_2574_p2 = (add_ln703_720_fu_2365_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_827_fu_2579_p2 = (add_ln703_722_reg_4882 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_828_fu_2588_p2 = (sub_ln703_794_fu_2370_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_829_fu_2593_p2 = (sub_ln703_795_fu_2375_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_830_fu_2598_p2 = (add_ln703_724_reg_4887 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_831_fu_2602_p2 = (sub_ln703_796_fu_2380_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_832_fu_2607_p2 = (add_ln703_725_fu_2389_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_833_fu_2642_p2 = (add_ln703_727_reg_4892 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_834_fu_2646_p2 = (sub_ln703_803_fu_2419_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_835_fu_2651_p2 = (add_ln703_729_reg_4897 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_836_fu_2655_p2 = (add_ln703_730_fu_2424_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_837_fu_2660_p2 = (add_ln703_732_reg_4902 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_838_fu_2664_p2 = (add_ln703_733_fu_2434_p2 - mult_896_V_reg_3909_pp0_iter7_reg); + +assign sub_ln703_fu_248_p2 = (trunc_ln203_reg_3431 - tmp_2_reg_3437); + +assign tmp_2_fu_92_p4 = {{data_V_read_int_reg[31:16]}}; + +assign trunc_ln203_fu_88_p1 = data_V_read_int_reg[15:0]; + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1 +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2 ( + ap_clk, + ap_rst, + data_0_V_read, + data_1_V_read, + data_2_V_read, + data_3_V_read, + data_4_V_read, + data_5_V_read, + data_6_V_read, + data_7_V_read, + data_8_V_read, + data_9_V_read, + data_10_V_read, + data_11_V_read, + data_12_V_read, + data_13_V_read, + data_14_V_read, + data_15_V_read, + data_16_V_read, + data_17_V_read, + data_18_V_read, + data_19_V_read, + data_20_V_read, + data_21_V_read, + data_22_V_read, + data_23_V_read, + data_24_V_read, + data_25_V_read, + data_26_V_read, + data_27_V_read, + data_28_V_read, + data_29_V_read, + data_30_V_read, + data_31_V_read, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3, + ap_return_4, + ap_return_5, + ap_return_6, + ap_return_7, + ap_return_8, + ap_return_9, + ap_return_10, + ap_return_11, + ap_return_12, + ap_return_13, + ap_return_14, + ap_return_15, + ap_return_16, + ap_return_17, + ap_return_18, + ap_return_19, + ap_return_20, + ap_return_21, + ap_return_22, + ap_return_23, + ap_return_24, + ap_return_25, + ap_return_26, + ap_return_27, + ap_return_28, + ap_return_29, + ap_return_30, + ap_return_31, + ap_ce +); + + +input ap_clk; +input ap_rst; +input [15:0] data_0_V_read; +input [15:0] data_1_V_read; +input [15:0] data_2_V_read; +input [15:0] data_3_V_read; +input [15:0] data_4_V_read; +input [15:0] data_5_V_read; +input [15:0] data_6_V_read; +input [15:0] data_7_V_read; +input [15:0] data_8_V_read; +input [15:0] data_9_V_read; +input [15:0] data_10_V_read; +input [15:0] data_11_V_read; +input [15:0] data_12_V_read; +input [15:0] data_13_V_read; +input [15:0] data_14_V_read; +input [15:0] data_15_V_read; +input [15:0] data_16_V_read; +input [15:0] data_17_V_read; +input [15:0] data_18_V_read; +input [15:0] data_19_V_read; +input [15:0] data_20_V_read; +input [15:0] data_21_V_read; +input [15:0] data_22_V_read; +input [15:0] data_23_V_read; +input [15:0] data_24_V_read; +input [15:0] data_25_V_read; +input [15:0] data_26_V_read; +input [15:0] data_27_V_read; +input [15:0] data_28_V_read; +input [15:0] data_29_V_read; +input [15:0] data_30_V_read; +input [15:0] data_31_V_read; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; +output [15:0] ap_return_4; +output [15:0] ap_return_5; +output [15:0] ap_return_6; +output [15:0] ap_return_7; +output [15:0] ap_return_8; +output [15:0] ap_return_9; +output [15:0] ap_return_10; +output [15:0] ap_return_11; +output [15:0] ap_return_12; +output [15:0] ap_return_13; +output [15:0] ap_return_14; +output [15:0] ap_return_15; +output [15:0] ap_return_16; +output [15:0] ap_return_17; +output [15:0] ap_return_18; +output [15:0] ap_return_19; +output [15:0] ap_return_20; +output [15:0] ap_return_21; +output [15:0] ap_return_22; +output [15:0] ap_return_23; +output [15:0] ap_return_24; +output [15:0] ap_return_25; +output [15:0] ap_return_26; +output [15:0] ap_return_27; +output [15:0] ap_return_28; +output [15:0] ap_return_29; +output [15:0] ap_return_30; +output [15:0] ap_return_31; +input ap_ce; + +reg[15:0] ap_return_0; +reg[15:0] ap_return_1; +reg[15:0] ap_return_2; +reg[15:0] ap_return_3; +reg[15:0] ap_return_4; +reg[15:0] ap_return_5; +reg[15:0] ap_return_6; +reg[15:0] ap_return_7; +reg[15:0] ap_return_8; +reg[15:0] ap_return_9; +reg[15:0] ap_return_10; +reg[15:0] ap_return_11; +reg[15:0] ap_return_12; +reg[15:0] ap_return_13; +reg[15:0] ap_return_14; +reg[15:0] ap_return_15; +reg[15:0] ap_return_16; +reg[15:0] ap_return_17; +reg[15:0] ap_return_18; +reg[15:0] ap_return_19; +reg[15:0] ap_return_20; +reg[15:0] ap_return_21; +reg[15:0] ap_return_22; +reg[15:0] ap_return_23; +reg[15:0] ap_return_24; +reg[15:0] ap_return_25; +reg[15:0] ap_return_26; +reg[15:0] ap_return_27; +reg[15:0] ap_return_28; +reg[15:0] ap_return_29; +reg[15:0] ap_return_30; +reg[15:0] ap_return_31; + +reg [15:0] data_31_V_read32_reg_4221; +wire ap_block_state1_pp0_stage0_iter0; +wire ap_block_state2_pp0_stage0_iter1; +wire ap_block_state3_pp0_stage0_iter2; +wire ap_block_state4_pp0_stage0_iter3; +wire ap_block_state5_pp0_stage0_iter4; +wire ap_block_state6_pp0_stage0_iter5; +wire ap_block_state7_pp0_stage0_iter6; +wire ap_block_state8_pp0_stage0_iter7; +wire ap_block_state9_pp0_stage0_iter8; +wire ap_block_state10_pp0_stage0_iter9; +wire ap_block_pp0_stage0_11001; +reg [15:0] data_31_V_read32_reg_4221_pp0_iter1_reg; +reg [15:0] data_31_V_read32_reg_4221_pp0_iter2_reg; +reg [15:0] data_31_V_read32_reg_4221_pp0_iter3_reg; +reg [15:0] data_31_V_read32_reg_4221_pp0_iter4_reg; +reg [15:0] data_31_V_read32_reg_4221_pp0_iter5_reg; +reg [15:0] data_31_V_read32_reg_4221_pp0_iter6_reg; +reg [15:0] data_31_V_read32_reg_4221_pp0_iter7_reg; +reg [15:0] data_31_V_read32_reg_4221_pp0_iter8_reg; +reg [15:0] data_30_V_read31_reg_4250; +reg [15:0] data_30_V_read31_reg_4250_pp0_iter1_reg; +reg [15:0] data_30_V_read31_reg_4250_pp0_iter2_reg; +reg [15:0] data_30_V_read31_reg_4250_pp0_iter3_reg; +reg [15:0] data_30_V_read31_reg_4250_pp0_iter4_reg; +reg [15:0] data_30_V_read31_reg_4250_pp0_iter5_reg; +reg [15:0] data_30_V_read31_reg_4250_pp0_iter6_reg; +reg [15:0] data_30_V_read31_reg_4250_pp0_iter7_reg; +reg [15:0] data_30_V_read31_reg_4250_pp0_iter8_reg; +reg [15:0] data_29_V_read_7_reg_4279; +reg [15:0] data_29_V_read_7_reg_4279_pp0_iter1_reg; +reg [15:0] data_29_V_read_7_reg_4279_pp0_iter2_reg; +reg [15:0] data_29_V_read_7_reg_4279_pp0_iter3_reg; +reg [15:0] data_29_V_read_7_reg_4279_pp0_iter4_reg; +reg [15:0] data_29_V_read_7_reg_4279_pp0_iter5_reg; +reg [15:0] data_29_V_read_7_reg_4279_pp0_iter6_reg; +reg [15:0] data_29_V_read_7_reg_4279_pp0_iter7_reg; +reg [15:0] data_29_V_read_7_reg_4279_pp0_iter8_reg; +reg [15:0] data_28_V_read_7_reg_4313; +reg [15:0] data_28_V_read_7_reg_4313_pp0_iter1_reg; +reg [15:0] data_28_V_read_7_reg_4313_pp0_iter2_reg; +reg [15:0] data_28_V_read_7_reg_4313_pp0_iter3_reg; +reg [15:0] data_28_V_read_7_reg_4313_pp0_iter4_reg; +reg [15:0] data_28_V_read_7_reg_4313_pp0_iter5_reg; +reg [15:0] data_28_V_read_7_reg_4313_pp0_iter6_reg; +reg [15:0] data_28_V_read_7_reg_4313_pp0_iter7_reg; +reg [15:0] data_28_V_read_7_reg_4313_pp0_iter8_reg; +reg [15:0] data_27_V_read_8_reg_4342; +reg [15:0] data_27_V_read_8_reg_4342_pp0_iter1_reg; +reg [15:0] data_27_V_read_8_reg_4342_pp0_iter2_reg; +reg [15:0] data_27_V_read_8_reg_4342_pp0_iter3_reg; +reg [15:0] data_27_V_read_8_reg_4342_pp0_iter4_reg; +reg [15:0] data_27_V_read_8_reg_4342_pp0_iter5_reg; +reg [15:0] data_27_V_read_8_reg_4342_pp0_iter6_reg; +reg [15:0] data_27_V_read_8_reg_4342_pp0_iter7_reg; +reg [15:0] data_26_V_read27_reg_4365; +reg [15:0] data_26_V_read27_reg_4365_pp0_iter1_reg; +reg [15:0] data_26_V_read27_reg_4365_pp0_iter2_reg; +reg [15:0] data_26_V_read27_reg_4365_pp0_iter3_reg; +reg [15:0] data_26_V_read27_reg_4365_pp0_iter4_reg; +reg [15:0] data_26_V_read27_reg_4365_pp0_iter5_reg; +reg [15:0] data_26_V_read27_reg_4365_pp0_iter6_reg; +reg [15:0] data_26_V_read27_reg_4365_pp0_iter7_reg; +reg [15:0] data_25_V_read26_reg_4391; +reg [15:0] data_25_V_read26_reg_4391_pp0_iter1_reg; +reg [15:0] data_25_V_read26_reg_4391_pp0_iter2_reg; +reg [15:0] data_25_V_read26_reg_4391_pp0_iter3_reg; +reg [15:0] data_25_V_read26_reg_4391_pp0_iter4_reg; +reg [15:0] data_25_V_read26_reg_4391_pp0_iter5_reg; +reg [15:0] data_25_V_read26_reg_4391_pp0_iter6_reg; +reg [15:0] data_25_V_read26_reg_4391_pp0_iter7_reg; +reg [15:0] data_24_V_read25_reg_4421; +reg [15:0] data_24_V_read25_reg_4421_pp0_iter1_reg; +reg [15:0] data_24_V_read25_reg_4421_pp0_iter2_reg; +reg [15:0] data_24_V_read25_reg_4421_pp0_iter3_reg; +reg [15:0] data_24_V_read25_reg_4421_pp0_iter4_reg; +reg [15:0] data_24_V_read25_reg_4421_pp0_iter5_reg; +reg [15:0] data_24_V_read25_reg_4421_pp0_iter6_reg; +reg [15:0] data_24_V_read25_reg_4421_pp0_iter7_reg; +reg [15:0] data_23_V_read24_reg_4451; +reg [15:0] data_23_V_read24_reg_4451_pp0_iter1_reg; +reg [15:0] data_23_V_read24_reg_4451_pp0_iter2_reg; +reg [15:0] data_23_V_read24_reg_4451_pp0_iter3_reg; +reg [15:0] data_23_V_read24_reg_4451_pp0_iter4_reg; +reg [15:0] data_23_V_read24_reg_4451_pp0_iter5_reg; +reg [15:0] data_23_V_read24_reg_4451_pp0_iter6_reg; +reg [15:0] data_23_V_read24_reg_4451_pp0_iter7_reg; +reg [15:0] data_22_V_read23_reg_4483; +reg [15:0] data_22_V_read23_reg_4483_pp0_iter1_reg; +reg [15:0] data_22_V_read23_reg_4483_pp0_iter2_reg; +reg [15:0] data_22_V_read23_reg_4483_pp0_iter3_reg; +reg [15:0] data_22_V_read23_reg_4483_pp0_iter4_reg; +reg [15:0] data_22_V_read23_reg_4483_pp0_iter5_reg; +reg [15:0] data_22_V_read23_reg_4483_pp0_iter6_reg; +reg [15:0] data_22_V_read23_reg_4483_pp0_iter7_reg; +reg [15:0] data_21_V_read22_reg_4512; +reg [15:0] data_21_V_read22_reg_4512_pp0_iter1_reg; +reg [15:0] data_21_V_read22_reg_4512_pp0_iter2_reg; +reg [15:0] data_21_V_read22_reg_4512_pp0_iter3_reg; +reg [15:0] data_21_V_read22_reg_4512_pp0_iter4_reg; +reg [15:0] data_21_V_read22_reg_4512_pp0_iter5_reg; +reg [15:0] data_21_V_read22_reg_4512_pp0_iter6_reg; +reg [15:0] data_20_V_read21_reg_4539; +reg [15:0] data_20_V_read21_reg_4539_pp0_iter1_reg; +reg [15:0] data_20_V_read21_reg_4539_pp0_iter2_reg; +reg [15:0] data_20_V_read21_reg_4539_pp0_iter3_reg; +reg [15:0] data_20_V_read21_reg_4539_pp0_iter4_reg; +reg [15:0] data_20_V_read21_reg_4539_pp0_iter5_reg; +reg [15:0] data_20_V_read21_reg_4539_pp0_iter6_reg; +reg [15:0] data_19_V_read_7_reg_4567; +reg [15:0] data_19_V_read_7_reg_4567_pp0_iter1_reg; +reg [15:0] data_19_V_read_7_reg_4567_pp0_iter2_reg; +reg [15:0] data_19_V_read_7_reg_4567_pp0_iter3_reg; +reg [15:0] data_19_V_read_7_reg_4567_pp0_iter4_reg; +reg [15:0] data_19_V_read_7_reg_4567_pp0_iter5_reg; +reg [15:0] data_19_V_read_7_reg_4567_pp0_iter6_reg; +reg [15:0] data_18_V_read_7_reg_4594; +reg [15:0] data_18_V_read_7_reg_4594_pp0_iter1_reg; +reg [15:0] data_18_V_read_7_reg_4594_pp0_iter2_reg; +reg [15:0] data_18_V_read_7_reg_4594_pp0_iter3_reg; +reg [15:0] data_18_V_read_7_reg_4594_pp0_iter4_reg; +reg [15:0] data_18_V_read_7_reg_4594_pp0_iter5_reg; +reg [15:0] data_18_V_read_7_reg_4594_pp0_iter6_reg; +reg [15:0] data_17_V_read_8_reg_4621; +reg [15:0] data_17_V_read_8_reg_4621_pp0_iter1_reg; +reg [15:0] data_17_V_read_8_reg_4621_pp0_iter2_reg; +reg [15:0] data_17_V_read_8_reg_4621_pp0_iter3_reg; +reg [15:0] data_17_V_read_8_reg_4621_pp0_iter4_reg; +reg [15:0] data_17_V_read_8_reg_4621_pp0_iter5_reg; +reg [15:0] data_17_V_read_8_reg_4621_pp0_iter6_reg; +reg [15:0] data_16_V_read17_reg_4650; +reg [15:0] data_16_V_read17_reg_4650_pp0_iter1_reg; +reg [15:0] data_16_V_read17_reg_4650_pp0_iter2_reg; +reg [15:0] data_16_V_read17_reg_4650_pp0_iter3_reg; +reg [15:0] data_16_V_read17_reg_4650_pp0_iter4_reg; +reg [15:0] data_16_V_read17_reg_4650_pp0_iter5_reg; +reg [15:0] data_15_V_read16_reg_4682; +reg [15:0] data_15_V_read16_reg_4682_pp0_iter1_reg; +reg [15:0] data_15_V_read16_reg_4682_pp0_iter2_reg; +reg [15:0] data_15_V_read16_reg_4682_pp0_iter3_reg; +reg [15:0] data_15_V_read16_reg_4682_pp0_iter4_reg; +reg [15:0] data_15_V_read16_reg_4682_pp0_iter5_reg; +reg [15:0] data_14_V_read15_reg_4714; +reg [15:0] data_14_V_read15_reg_4714_pp0_iter1_reg; +reg [15:0] data_14_V_read15_reg_4714_pp0_iter2_reg; +reg [15:0] data_14_V_read15_reg_4714_pp0_iter3_reg; +reg [15:0] data_14_V_read15_reg_4714_pp0_iter4_reg; +reg [15:0] data_14_V_read15_reg_4714_pp0_iter5_reg; +reg [15:0] data_13_V_read14_reg_4745; +reg [15:0] data_13_V_read14_reg_4745_pp0_iter1_reg; +reg [15:0] data_13_V_read14_reg_4745_pp0_iter2_reg; +reg [15:0] data_13_V_read14_reg_4745_pp0_iter3_reg; +reg [15:0] data_13_V_read14_reg_4745_pp0_iter4_reg; +reg [15:0] data_13_V_read14_reg_4745_pp0_iter5_reg; +reg [15:0] data_12_V_read13_reg_4778; +reg [15:0] data_12_V_read13_reg_4778_pp0_iter1_reg; +reg [15:0] data_12_V_read13_reg_4778_pp0_iter2_reg; +reg [15:0] data_12_V_read13_reg_4778_pp0_iter3_reg; +reg [15:0] data_12_V_read13_reg_4778_pp0_iter4_reg; +reg [15:0] data_11_V_read12_reg_4808; +reg [15:0] data_11_V_read12_reg_4808_pp0_iter1_reg; +reg [15:0] data_11_V_read12_reg_4808_pp0_iter2_reg; +reg [15:0] data_11_V_read12_reg_4808_pp0_iter3_reg; +reg [15:0] data_11_V_read12_reg_4808_pp0_iter4_reg; +reg [15:0] data_10_V_read11_reg_4832; +reg [15:0] data_10_V_read11_reg_4832_pp0_iter1_reg; +reg [15:0] data_10_V_read11_reg_4832_pp0_iter2_reg; +reg [15:0] data_10_V_read11_reg_4832_pp0_iter3_reg; +reg [15:0] data_10_V_read11_reg_4832_pp0_iter4_reg; +reg [15:0] data_9_V_read_7_reg_4859; +reg [15:0] data_9_V_read_7_reg_4859_pp0_iter1_reg; +reg [15:0] data_9_V_read_7_reg_4859_pp0_iter2_reg; +reg [15:0] data_9_V_read_7_reg_4859_pp0_iter3_reg; +reg [15:0] data_9_V_read_7_reg_4859_pp0_iter4_reg; +reg [15:0] data_8_V_read_7_reg_4887; +reg [15:0] data_8_V_read_7_reg_4887_pp0_iter1_reg; +reg [15:0] data_8_V_read_7_reg_4887_pp0_iter2_reg; +reg [15:0] data_8_V_read_7_reg_4887_pp0_iter3_reg; +reg [15:0] data_7_V_read_8_reg_4916; +reg [15:0] data_7_V_read_8_reg_4916_pp0_iter1_reg; +reg [15:0] data_7_V_read_8_reg_4916_pp0_iter2_reg; +reg [15:0] data_7_V_read_8_reg_4916_pp0_iter3_reg; +reg [15:0] data_6_V_read_8_reg_4944; +reg [15:0] data_6_V_read_8_reg_4944_pp0_iter1_reg; +reg [15:0] data_6_V_read_8_reg_4944_pp0_iter2_reg; +reg [15:0] data_6_V_read_8_reg_4944_pp0_iter3_reg; +reg [15:0] data_5_V_read_8_reg_4969; +reg [15:0] data_5_V_read_8_reg_4969_pp0_iter1_reg; +reg [15:0] data_5_V_read_8_reg_4969_pp0_iter2_reg; +reg [15:0] data_5_V_read_8_reg_4969_pp0_iter3_reg; +reg [15:0] data_4_V_read_9_reg_4998; +reg [15:0] data_4_V_read_9_reg_4998_pp0_iter1_reg; +reg [15:0] data_4_V_read_9_reg_4998_pp0_iter2_reg; +reg [15:0] data_3_V_read_9_reg_5019; +reg [15:0] data_3_V_read_9_reg_5019_pp0_iter1_reg; +reg [15:0] data_3_V_read_9_reg_5019_pp0_iter2_reg; +reg [15:0] data_2_V_read_9_reg_5035; +wire [15:0] sub_ln703_fu_274_p2; +reg [15:0] sub_ln703_reg_5046; +wire [15:0] add_ln703_fu_280_p2; +reg [15:0] add_ln703_reg_5052; +wire [15:0] sub_ln703_73_fu_286_p2; +reg [15:0] sub_ln703_73_reg_5059; +wire [15:0] sub_ln703_74_fu_292_p2; +reg [15:0] sub_ln703_74_reg_5065; +reg [15:0] sub_ln703_74_reg_5065_pp0_iter2_reg; +wire [15:0] sub_ln703_76_fu_300_p2; +reg [15:0] sub_ln703_76_reg_5071; +reg [15:0] sub_ln703_76_reg_5071_pp0_iter2_reg; +wire [15:0] add_ln703_200_fu_304_p2; +reg [15:0] add_ln703_200_reg_5077; +reg [15:0] add_ln703_200_reg_5077_pp0_iter2_reg; +wire [15:0] sub_ln703_77_fu_308_p2; +reg [15:0] sub_ln703_77_reg_5084; +wire [15:0] add_ln703_201_fu_312_p2; +reg [15:0] add_ln703_201_reg_5090; +reg [15:0] add_ln703_201_reg_5090_pp0_iter2_reg; +wire [15:0] add_ln703_202_fu_316_p2; +reg [15:0] add_ln703_202_reg_5096; +reg [15:0] add_ln703_202_reg_5096_pp0_iter2_reg; +wire [15:0] add_ln703_204_fu_320_p2; +reg [15:0] add_ln703_204_reg_5101; +reg [15:0] add_ln703_204_reg_5101_pp0_iter2_reg; +wire [15:0] add_ln703_207_fu_325_p2; +reg [15:0] add_ln703_207_reg_5107; +reg [15:0] add_ln703_207_reg_5107_pp0_iter2_reg; +wire [15:0] add_ln703_203_fu_329_p2; +reg [15:0] add_ln703_203_reg_5113; +wire [15:0] add_ln703_205_fu_333_p2; +reg [15:0] add_ln703_205_reg_5119; +wire [15:0] sub_ln703_79_fu_337_p2; +reg [15:0] sub_ln703_79_reg_5125; +wire [15:0] add_ln703_206_fu_341_p2; +reg [15:0] add_ln703_206_reg_5131; +wire [15:0] add_ln703_208_fu_345_p2; +reg [15:0] add_ln703_208_reg_5137; +wire [15:0] add_ln703_210_fu_349_p2; +reg [15:0] add_ln703_210_reg_5143; +reg [15:0] add_ln703_210_reg_5143_pp0_iter3_reg; +wire [15:0] add_ln703_233_fu_353_p2; +reg [15:0] add_ln703_233_reg_5149; +reg [15:0] add_ln703_233_reg_5149_pp0_iter3_reg; +wire [15:0] add_ln703_247_fu_357_p2; +reg [15:0] add_ln703_247_reg_5159; +reg [15:0] add_ln703_247_reg_5159_pp0_iter3_reg; +wire [15:0] sub_ln703_89_fu_402_p2; +reg [15:0] sub_ln703_89_reg_5166; +wire [15:0] sub_ln703_91_fu_411_p2; +reg [15:0] sub_ln703_91_reg_5172; +wire [15:0] add_ln703_209_fu_416_p2; +reg [15:0] add_ln703_209_reg_5178; +wire [15:0] add_ln703_211_fu_420_p2; +reg [15:0] add_ln703_211_reg_5184; +wire [15:0] add_ln703_213_fu_429_p2; +reg [15:0] add_ln703_213_reg_5189; +wire [15:0] add_ln703_214_fu_433_p2; +reg [15:0] add_ln703_214_reg_5194; +wire [15:0] sub_ln703_93_fu_442_p2; +reg [15:0] sub_ln703_93_reg_5200; +wire [15:0] sub_ln703_94_fu_446_p2; +reg [15:0] sub_ln703_94_reg_5205; +wire [15:0] sub_ln703_96_fu_456_p2; +reg [15:0] sub_ln703_96_reg_5210; +wire [15:0] add_ln703_216_fu_461_p2; +reg [15:0] add_ln703_216_reg_5215; +wire [15:0] add_ln703_220_fu_484_p2; +reg [15:0] add_ln703_220_reg_5221; +wire [15:0] sub_ln703_105_fu_489_p2; +reg [15:0] sub_ln703_105_reg_5226; +wire [15:0] add_ln703_223_fu_507_p2; +reg [15:0] add_ln703_223_reg_5231; +wire [15:0] add_ln703_225_fu_513_p2; +reg [15:0] add_ln703_225_reg_5237; +wire [15:0] add_ln703_227_fu_522_p2; +reg [15:0] add_ln703_227_reg_5242; +wire [15:0] sub_ln703_113_fu_533_p2; +reg [15:0] sub_ln703_113_reg_5247; +wire [15:0] sub_ln703_114_fu_549_p2; +reg [15:0] sub_ln703_114_reg_5253; +wire [15:0] sub_ln703_117_fu_554_p2; +reg [15:0] sub_ln703_117_reg_5259; +wire [15:0] add_ln703_234_fu_564_p2; +reg [15:0] add_ln703_234_reg_5264; +wire [15:0] add_ln703_238_fu_569_p2; +reg [15:0] add_ln703_238_reg_5269; +wire [15:0] sub_ln703_126_fu_574_p2; +reg [15:0] sub_ln703_126_reg_5274; +wire [15:0] sub_ln703_129_fu_579_p2; +reg [15:0] sub_ln703_129_reg_5279; +wire [15:0] sub_ln703_133_fu_584_p2; +reg [15:0] sub_ln703_133_reg_5284; +wire [15:0] add_ln703_251_fu_589_p2; +reg [15:0] add_ln703_251_reg_5289; +wire [15:0] add_ln703_258_fu_593_p2; +reg [15:0] add_ln703_258_reg_5295; +wire [15:0] add_ln703_272_fu_597_p2; +reg [15:0] add_ln703_272_reg_5304; +reg [15:0] add_ln703_272_reg_5304_pp0_iter4_reg; +wire [15:0] add_ln703_304_fu_601_p2; +reg [15:0] add_ln703_304_reg_5314; +wire [15:0] add_ln703_246_fu_787_p2; +reg [15:0] add_ln703_246_reg_5320; +wire [15:0] sub_ln703_138_fu_816_p2; +reg [15:0] sub_ln703_138_reg_5325; +wire [15:0] sub_ln703_141_fu_835_p2; +reg [15:0] sub_ln703_141_reg_5330; +wire [15:0] sub_ln703_143_fu_844_p2; +reg [15:0] sub_ln703_143_reg_5335; +wire [15:0] sub_ln703_144_fu_858_p2; +reg [15:0] sub_ln703_144_reg_5340; +wire [15:0] sub_ln703_145_fu_863_p2; +reg [15:0] sub_ln703_145_reg_5345; +wire [15:0] sub_ln703_149_fu_901_p2; +reg [15:0] sub_ln703_149_reg_5350; +wire [15:0] sub_ln703_154_fu_920_p2; +reg [15:0] sub_ln703_154_reg_5355; +wire [15:0] add_ln703_261_fu_955_p2; +reg [15:0] add_ln703_261_reg_5360; +wire [15:0] sub_ln703_161_fu_960_p2; +reg [15:0] sub_ln703_161_reg_5365; +wire [15:0] sub_ln703_162_fu_980_p2; +reg [15:0] sub_ln703_162_reg_5370; +wire [15:0] sub_ln703_166_fu_1000_p2; +reg [15:0] sub_ln703_166_reg_5375; +wire [15:0] sub_ln703_171_fu_1015_p2; +reg [15:0] sub_ln703_171_reg_5380; +wire [15:0] sub_ln703_173_fu_1025_p2; +reg [15:0] sub_ln703_173_reg_5385; +wire [15:0] sub_ln703_176_fu_1040_p2; +reg [15:0] sub_ln703_176_reg_5390; +wire [15:0] sub_ln703_180_fu_1045_p2; +reg [15:0] sub_ln703_180_reg_5395; +wire [15:0] sub_ln703_181_fu_1050_p2; +reg [15:0] sub_ln703_181_reg_5400; +wire [15:0] add_ln703_267_fu_1055_p2; +reg [15:0] add_ln703_267_reg_5405; +wire [15:0] sub_ln703_182_fu_1060_p2; +reg [15:0] sub_ln703_182_reg_5410; +wire [15:0] add_ln703_268_fu_1065_p2; +reg [15:0] add_ln703_268_reg_5415; +wire [15:0] add_ln703_274_fu_1089_p2; +reg [15:0] add_ln703_274_reg_5420; +wire [15:0] sub_ln703_185_fu_1095_p2; +reg [15:0] sub_ln703_185_reg_5425; +wire [15:0] add_ln703_276_fu_1100_p2; +reg [15:0] add_ln703_276_reg_5430; +wire [15:0] add_ln703_278_fu_1105_p2; +reg [15:0] add_ln703_278_reg_5435; +wire [15:0] sub_ln703_187_fu_1110_p2; +reg [15:0] sub_ln703_187_reg_5440; +wire [15:0] sub_ln703_189_fu_1115_p2; +reg [15:0] sub_ln703_189_reg_5445; +wire [15:0] sub_ln703_191_fu_1120_p2; +reg [15:0] sub_ln703_191_reg_5450; +wire [15:0] add_ln703_281_fu_1129_p2; +reg [15:0] add_ln703_281_reg_5455; +wire [15:0] add_ln703_283_fu_1140_p2; +reg [15:0] add_ln703_283_reg_5460; +wire [15:0] sub_ln703_198_fu_1146_p2; +reg [15:0] sub_ln703_198_reg_5465; +wire [15:0] sub_ln703_199_fu_1151_p2; +reg [15:0] sub_ln703_199_reg_5470; +wire [15:0] add_ln703_288_fu_1156_p2; +reg [15:0] add_ln703_288_reg_5475; +wire [15:0] add_ln703_309_fu_1179_p2; +reg [15:0] add_ln703_309_reg_5484; +wire [15:0] add_ln703_314_fu_1183_p2; +reg [15:0] add_ln703_314_reg_5490; +wire [15:0] add_ln703_316_fu_1187_p2; +reg [15:0] add_ln703_316_reg_5496; +wire [15:0] sub_ln703_246_fu_1193_p2; +reg [15:0] sub_ln703_246_reg_5501; +wire [15:0] add_ln703_323_fu_1198_p2; +reg [15:0] add_ln703_323_reg_5506; +wire [15:0] sub_ln703_200_fu_1326_p2; +reg [15:0] sub_ln703_200_reg_5515; +wire [15:0] sub_ln703_203_fu_1339_p2; +reg [15:0] sub_ln703_203_reg_5520; +wire [15:0] add_ln703_287_fu_1354_p2; +reg [15:0] add_ln703_287_reg_5525; +wire [15:0] add_ln703_291_fu_1371_p2; +reg [15:0] add_ln703_291_reg_5530; +wire [15:0] sub_ln703_207_fu_1384_p2; +reg [15:0] sub_ln703_207_reg_5535; +wire [15:0] sub_ln703_212_fu_1412_p2; +reg [15:0] sub_ln703_212_reg_5540; +wire [15:0] sub_ln703_215_fu_1441_p2; +reg [15:0] sub_ln703_215_reg_5545; +wire [15:0] add_ln703_301_fu_1494_p2; +reg [15:0] add_ln703_301_reg_5550; +wire [15:0] add_ln703_307_fu_1504_p2; +reg [15:0] add_ln703_307_reg_5555; +wire [15:0] sub_ln703_229_fu_1518_p2; +reg [15:0] sub_ln703_229_reg_5560; +wire [15:0] sub_ln703_237_fu_1571_p2; +reg [15:0] sub_ln703_237_reg_5565; +wire [15:0] sub_ln703_238_fu_1576_p2; +reg [15:0] sub_ln703_238_reg_5570; +wire [15:0] sub_ln703_252_fu_1616_p2; +reg [15:0] sub_ln703_252_reg_5575; +wire [15:0] sub_ln703_253_fu_1621_p2; +reg [15:0] sub_ln703_253_reg_5580; +wire [15:0] sub_ln703_254_fu_1626_p2; +reg [15:0] sub_ln703_254_reg_5585; +wire [15:0] add_ln703_321_fu_1636_p2; +reg [15:0] add_ln703_321_reg_5590; +wire [15:0] sub_ln703_257_fu_1641_p2; +reg [15:0] sub_ln703_257_reg_5595; +wire [15:0] sub_ln703_261_fu_1646_p2; +reg [15:0] sub_ln703_261_reg_5600; +wire [15:0] sub_ln703_262_fu_1651_p2; +reg [15:0] sub_ln703_262_reg_5605; +wire [15:0] sub_ln703_263_fu_1671_p2; +reg [15:0] sub_ln703_263_reg_5610; +wire [15:0] sub_ln703_265_fu_1676_p2; +reg [15:0] sub_ln703_265_reg_5615; +wire [15:0] sub_ln703_266_fu_1681_p2; +reg [15:0] sub_ln703_266_reg_5620; +wire [15:0] add_ln703_326_fu_1686_p2; +reg [15:0] add_ln703_326_reg_5625; +wire [15:0] sub_ln703_270_fu_1695_p2; +reg [15:0] sub_ln703_270_reg_5630; +wire [15:0] sub_ln703_272_fu_1700_p2; +reg [15:0] sub_ln703_272_reg_5635; +wire [15:0] add_ln703_330_fu_1710_p2; +reg [15:0] add_ln703_330_reg_5640; +wire [15:0] add_ln703_335_fu_1730_p2; +reg [15:0] add_ln703_335_reg_5645; +wire [15:0] sub_ln703_278_fu_1735_p2; +reg [15:0] sub_ln703_278_reg_5650; +wire [15:0] add_ln703_339_fu_1740_p2; +reg [15:0] add_ln703_339_reg_5655; +wire [15:0] add_ln703_343_fu_1745_p2; +reg [15:0] add_ln703_343_reg_5660; +wire [15:0] sub_ln703_289_fu_1750_p2; +reg [15:0] sub_ln703_289_reg_5665; +wire [15:0] sub_ln703_290_fu_1755_p2; +reg [15:0] sub_ln703_290_reg_5670; +wire [15:0] add_ln703_347_fu_1760_p2; +reg [15:0] add_ln703_347_reg_5675; +wire [15:0] add_ln703_357_fu_1764_p2; +reg [15:0] add_ln703_357_reg_5683; +reg [15:0] add_ln703_357_reg_5683_pp0_iter6_reg; +wire [15:0] add_ln703_371_fu_1768_p2; +reg [15:0] add_ln703_371_reg_5691; +wire [15:0] add_ln703_384_fu_1772_p2; +reg [15:0] add_ln703_384_reg_5701; +reg [15:0] add_ln703_384_reg_5701_pp0_iter6_reg; +wire [15:0] add_ln703_394_fu_1776_p2; +reg [15:0] add_ln703_394_reg_5710; +reg [15:0] add_ln703_394_reg_5710_pp0_iter6_reg; +wire [15:0] add_ln703_404_fu_1780_p2; +reg [15:0] add_ln703_404_reg_5718; +reg [15:0] add_ln703_404_reg_5718_pp0_iter6_reg; +wire [15:0] sub_ln703_276_fu_1918_p2; +reg [15:0] sub_ln703_276_reg_5728; +wire [15:0] sub_ln703_283_fu_1975_p2; +reg [15:0] sub_ln703_283_reg_5733; +wire [15:0] sub_ln703_288_fu_2003_p2; +reg [15:0] sub_ln703_288_reg_5738; +wire [15:0] add_ln703_353_fu_2060_p2; +reg [15:0] add_ln703_353_reg_5743; +wire [15:0] sub_ln703_300_fu_2075_p2; +reg [15:0] sub_ln703_300_reg_5748; +wire [15:0] add_ln703_354_fu_2080_p2; +reg [15:0] add_ln703_354_reg_5753; +wire [15:0] sub_ln703_302_fu_2089_p2; +reg [15:0] sub_ln703_302_reg_5758; +wire [15:0] sub_ln703_304_fu_2099_p2; +reg [15:0] sub_ln703_304_reg_5763; +wire [15:0] add_ln703_359_fu_2127_p2; +reg [15:0] add_ln703_359_reg_5768; +wire [15:0] sub_ln703_309_fu_2148_p2; +reg [15:0] sub_ln703_309_reg_5773; +wire [15:0] sub_ln703_311_fu_2173_p2; +reg [15:0] sub_ln703_311_reg_5778; +wire [15:0] sub_ln703_318_fu_2203_p2; +reg [15:0] sub_ln703_318_reg_5783; +wire [15:0] sub_ln703_321_fu_2218_p2; +reg [15:0] sub_ln703_321_reg_5788; +wire [15:0] add_ln703_372_fu_2228_p2; +reg [15:0] add_ln703_372_reg_5793; +wire [15:0] sub_ln703_323_fu_2233_p2; +reg [15:0] sub_ln703_323_reg_5798; +wire [15:0] sub_ln703_324_fu_2238_p2; +reg [15:0] sub_ln703_324_reg_5803; +wire [15:0] sub_ln703_325_fu_2243_p2; +reg [15:0] sub_ln703_325_reg_5808; +wire [15:0] sub_ln703_327_fu_2248_p2; +reg [15:0] sub_ln703_327_reg_5813; +wire [15:0] sub_ln703_328_fu_2253_p2; +reg [15:0] sub_ln703_328_reg_5818; +wire [15:0] sub_ln703_331_fu_2258_p2; +reg [15:0] sub_ln703_331_reg_5823; +wire [15:0] sub_ln703_332_fu_2273_p2; +reg [15:0] sub_ln703_332_reg_5828; +wire [15:0] add_ln703_377_fu_2283_p2; +reg [15:0] add_ln703_377_reg_5833; +wire [15:0] add_ln703_379_fu_2292_p2; +reg [15:0] add_ln703_379_reg_5838; +wire [15:0] sub_ln703_335_fu_2302_p2; +reg [15:0] sub_ln703_335_reg_5843; +wire [15:0] add_ln703_381_fu_2307_p2; +reg [15:0] add_ln703_381_reg_5848; +wire [15:0] sub_ln703_343_fu_2312_p2; +reg [15:0] sub_ln703_343_reg_5853; +wire [15:0] add_ln703_390_fu_2326_p2; +reg [15:0] add_ln703_390_reg_5858; +wire [15:0] sub_ln703_346_fu_2332_p2; +reg [15:0] sub_ln703_346_reg_5863; +wire [15:0] add_ln703_400_fu_2346_p2; +reg [15:0] add_ln703_400_reg_5868; +wire [15:0] add_ln703_413_fu_2361_p2; +reg [15:0] add_ln703_413_reg_5873; +wire [15:0] add_ln703_415_fu_2372_p2; +reg [15:0] add_ln703_415_reg_5878; +wire [15:0] add_ln703_427_fu_2383_p2; +reg [15:0] add_ln703_427_reg_5883; +wire [15:0] add_ln703_428_fu_2389_p2; +reg [15:0] add_ln703_428_reg_5888; +wire [15:0] add_ln703_435_fu_2393_p2; +reg [15:0] add_ln703_435_reg_5894; +wire [15:0] add_ln703_446_fu_2397_p2; +reg [15:0] add_ln703_446_reg_5901; +wire [15:0] add_ln703_462_fu_2401_p2; +reg [15:0] add_ln703_462_reg_5909; +reg [15:0] add_ln703_462_reg_5909_pp0_iter7_reg; +reg [15:0] add_ln703_462_reg_5909_pp0_iter8_reg; +wire [15:0] sub_ln703_356_fu_2603_p2; +reg [15:0] sub_ln703_356_reg_5921; +wire [15:0] sub_ln703_357_fu_2608_p2; +reg [15:0] sub_ln703_357_reg_5926; +wire [15:0] add_ln703_402_fu_2631_p2; +reg [15:0] add_ln703_402_reg_5931; +wire [15:0] sub_ln703_361_fu_2636_p2; +reg [15:0] sub_ln703_361_reg_5936; +wire [15:0] sub_ln703_366_fu_2684_p2; +reg [15:0] sub_ln703_366_reg_5941; +wire [15:0] sub_ln703_369_fu_2699_p2; +reg [15:0] sub_ln703_369_reg_5946; +wire [15:0] add_ln703_410_fu_2709_p2; +reg [15:0] add_ln703_410_reg_5951; +wire [15:0] sub_ln703_374_fu_2728_p2; +reg [15:0] sub_ln703_374_reg_5956; +wire [15:0] add_ln703_418_fu_2741_p2; +reg [15:0] add_ln703_418_reg_5961; +wire [15:0] sub_ln703_375_fu_2747_p2; +reg [15:0] sub_ln703_375_reg_5966; +wire [15:0] sub_ln703_379_fu_2781_p2; +reg [15:0] sub_ln703_379_reg_5971; +wire [15:0] sub_ln703_381_fu_2791_p2; +reg [15:0] sub_ln703_381_reg_5976; +wire [15:0] add_ln703_424_fu_2806_p2; +reg [15:0] add_ln703_424_reg_5981; +wire [15:0] sub_ln703_385_fu_2811_p2; +reg [15:0] sub_ln703_385_reg_5986; +wire [15:0] sub_ln703_386_fu_2816_p2; +reg [15:0] sub_ln703_386_reg_5991; +wire [15:0] sub_ln703_389_fu_2839_p2; +reg [15:0] sub_ln703_389_reg_5996; +wire [15:0] sub_ln703_392_fu_2848_p2; +reg [15:0] sub_ln703_392_reg_6001; +wire [15:0] sub_ln703_397_fu_2863_p2; +reg [15:0] sub_ln703_397_reg_6006; +wire [15:0] add_ln703_434_fu_2873_p2; +reg [15:0] add_ln703_434_reg_6011; +wire [15:0] sub_ln703_402_fu_2878_p2; +reg [15:0] sub_ln703_402_reg_6016; +wire [15:0] add_ln703_436_fu_2883_p2; +reg [15:0] add_ln703_436_reg_6021; +wire [15:0] sub_ln703_408_fu_2893_p2; +reg [15:0] sub_ln703_408_reg_6026; +wire [15:0] sub_ln703_409_fu_2898_p2; +reg [15:0] sub_ln703_409_reg_6031; +wire [15:0] sub_ln703_411_fu_2903_p2; +reg [15:0] sub_ln703_411_reg_6036; +wire [15:0] add_ln703_442_fu_2917_p2; +reg [15:0] add_ln703_442_reg_6041; +wire [15:0] sub_ln703_416_fu_2923_p2; +reg [15:0] sub_ln703_416_reg_6046; +wire [15:0] add_ln703_444_fu_2928_p2; +reg [15:0] add_ln703_444_reg_6051; +wire [15:0] add_ln703_447_fu_2933_p2; +reg [15:0] add_ln703_447_reg_6056; +wire [15:0] sub_ln703_426_fu_2938_p2; +reg [15:0] sub_ln703_426_reg_6061; +wire [15:0] add_ln703_451_fu_2943_p2; +reg [15:0] add_ln703_451_reg_6066; +reg [15:0] add_ln703_451_reg_6066_pp0_iter8_reg; +wire [15:0] add_ln703_480_fu_2961_p2; +reg [15:0] add_ln703_480_reg_6072; +reg [15:0] add_ln703_480_reg_6072_pp0_iter8_reg; +wire [15:0] add_ln703_482_fu_2967_p2; +reg [15:0] add_ln703_482_reg_6077; +wire [15:0] add_ln703_491_fu_2971_p2; +reg [15:0] add_ln703_491_reg_6087; +reg [15:0] add_ln703_491_reg_6087_pp0_iter8_reg; +wire [15:0] add_ln703_509_fu_2976_p2; +reg [15:0] add_ln703_509_reg_6092; +reg [15:0] add_ln703_509_reg_6092_pp0_iter8_reg; +wire [15:0] add_ln703_516_fu_2980_p2; +reg [15:0] add_ln703_516_reg_6103; +reg [15:0] add_ln703_516_reg_6103_pp0_iter8_reg; +wire [15:0] sub_ln703_428_fu_3163_p2; +reg [15:0] sub_ln703_428_reg_6108; +wire [15:0] sub_ln703_434_fu_3199_p2; +reg [15:0] sub_ln703_434_reg_6113; +wire [15:0] sub_ln703_448_fu_3308_p2; +reg [15:0] sub_ln703_448_reg_6118; +wire [15:0] sub_ln703_450_fu_3318_p2; +reg [15:0] sub_ln703_450_reg_6123; +wire [15:0] add_ln703_463_fu_3328_p2; +reg [15:0] add_ln703_463_reg_6128; +wire [15:0] add_ln703_464_fu_3333_p2; +reg [15:0] add_ln703_464_reg_6133; +wire [15:0] add_ln703_465_fu_3338_p2; +reg [15:0] add_ln703_465_reg_6138; +wire [15:0] sub_ln703_451_fu_3343_p2; +reg [15:0] sub_ln703_451_reg_6143; +wire [15:0] sub_ln703_452_fu_3348_p2; +reg [15:0] sub_ln703_452_reg_6148; +wire [15:0] sub_ln703_453_fu_3353_p2; +reg [15:0] sub_ln703_453_reg_6153; +wire [15:0] add_ln703_467_fu_3363_p2; +reg [15:0] add_ln703_467_reg_6158; +wire [15:0] sub_ln703_454_fu_3368_p2; +reg [15:0] sub_ln703_454_reg_6163; +wire [15:0] sub_ln703_455_fu_3373_p2; +reg [15:0] sub_ln703_455_reg_6168; +wire [15:0] add_ln703_468_fu_3378_p2; +reg [15:0] add_ln703_468_reg_6173; +wire [15:0] sub_ln703_456_fu_3388_p2; +reg [15:0] sub_ln703_456_reg_6178; +wire [15:0] sub_ln703_457_fu_3393_p2; +reg [15:0] sub_ln703_457_reg_6183; +wire [15:0] add_ln703_471_fu_3403_p2; +reg [15:0] add_ln703_471_reg_6188; +wire [15:0] sub_ln703_458_fu_3408_p2; +reg [15:0] sub_ln703_458_reg_6193; +wire [15:0] sub_ln703_459_fu_3418_p2; +reg [15:0] sub_ln703_459_reg_6198; +wire [15:0] add_ln703_475_fu_3432_p2; +reg [15:0] add_ln703_475_reg_6203; +wire [15:0] sub_ln703_461_fu_3438_p2; +reg [15:0] sub_ln703_461_reg_6208; +wire [15:0] add_ln703_483_fu_3448_p2; +reg [15:0] add_ln703_483_reg_6213; +wire [15:0] sub_ln703_469_fu_3463_p2; +reg [15:0] sub_ln703_469_reg_6218; +wire [15:0] add_ln703_492_fu_3478_p2; +reg [15:0] add_ln703_492_reg_6223; +wire [15:0] sub_ln703_474_fu_3482_p2; +reg [15:0] sub_ln703_474_reg_6229; +wire [15:0] add_ln703_496_fu_3497_p2; +reg [15:0] add_ln703_496_reg_6234; +wire [15:0] add_ln703_497_fu_3501_p2; +reg [15:0] add_ln703_497_reg_6239; +wire [15:0] sub_ln703_486_fu_3507_p2; +reg [15:0] sub_ln703_486_reg_6244; +wire [15:0] sub_ln703_487_fu_3512_p2; +reg [15:0] sub_ln703_487_reg_6249; +wire [15:0] sub_ln703_491_fu_3517_p2; +reg [15:0] sub_ln703_491_reg_6254; +wire [15:0] sub_ln703_500_fu_3522_p2; +reg [15:0] sub_ln703_500_reg_6259; +wire [15:0] add_ln703_510_fu_3527_p2; +reg [15:0] add_ln703_510_reg_6264; +wire ap_block_pp0_stage0; +wire [15:0] sub_ln703_75_fu_296_p2; +wire [15:0] sub_ln703_78_fu_361_p2; +wire [15:0] sub_ln703_80_fu_365_p2; +wire [15:0] sub_ln703_81_fu_369_p2; +wire [15:0] sub_ln703_82_fu_373_p2; +wire [15:0] sub_ln703_84_fu_381_p2; +wire [15:0] sub_ln703_86_fu_389_p2; +wire [15:0] sub_ln703_87_fu_393_p2; +wire [15:0] sub_ln703_88_fu_398_p2; +wire [15:0] sub_ln703_90_fu_406_p2; +wire [15:0] add_ln703_212_fu_425_p2; +wire [15:0] sub_ln703_92_fu_437_p2; +wire [15:0] add_ln703_222_fu_503_p2; +wire [15:0] sub_ln703_85_fu_385_p2; +wire [15:0] sub_ln703_98_fu_466_p2; +wire [15:0] add_ln703_226_fu_518_p2; +wire [15:0] add_ln703_217_fu_470_p2; +wire [15:0] add_ln703_218_fu_474_p2; +wire [15:0] sub_ln703_83_fu_377_p2; +wire [15:0] add_ln703_230_fu_538_p2; +wire [15:0] add_ln703_219_fu_479_p2; +wire [15:0] sub_ln703_106_fu_494_p2; +wire [15:0] add_ln703_221_fu_499_p2; +wire [15:0] sub_ln703_95_fu_451_p2; +wire [15:0] sub_ln703_112_fu_528_p2; +wire [15:0] add_ln703_231_fu_543_p2; +wire [15:0] sub_ln703_118_fu_559_p2; +wire [15:0] add_ln703_215_fu_605_p2; +wire [15:0] sub_ln703_97_fu_609_p2; +wire [15:0] sub_ln703_99_fu_613_p2; +wire [15:0] sub_ln703_100_fu_617_p2; +wire [15:0] sub_ln703_101_fu_621_p2; +wire [15:0] sub_ln703_103_fu_629_p2; +wire [15:0] sub_ln703_108_fu_641_p2; +wire [15:0] add_ln703_224_fu_645_p2; +wire [15:0] sub_ln703_110_fu_654_p2; +wire [15:0] sub_ln703_111_fu_658_p2; +wire [15:0] add_ln703_228_fu_663_p2; +wire [15:0] add_ln703_229_fu_668_p2; +wire [15:0] add_ln703_232_fu_673_p2; +wire [15:0] sub_ln703_102_fu_625_p2; +wire [15:0] sub_ln703_115_fu_678_p2; +wire [15:0] sub_ln703_116_fu_683_p2; +wire [15:0] sub_ln703_107_fu_637_p2; +wire [15:0] add_ln703_243_fu_774_p2; +wire [15:0] sub_ln703_119_fu_687_p2; +wire [15:0] sub_ln703_121_fu_696_p2; +wire [15:0] sub_ln703_109_fu_649_p2; +wire [15:0] add_ln703_235_fu_701_p2; +wire [15:0] sub_ln703_122_fu_705_p2; +wire [15:0] add_ln703_236_fu_710_p2; +wire [15:0] add_ln703_237_fu_715_p2; +wire [15:0] sub_ln703_123_fu_719_p2; +wire [15:0] sub_ln703_125_fu_727_p2; +wire [15:0] sub_ln703_128_fu_736_p2; +wire [15:0] add_ln703_250_fu_849_p2; +wire [15:0] add_ln703_239_fu_750_p2; +wire [15:0] add_ln703_240_fu_755_p2; +wire [15:0] sub_ln703_132_fu_760_p2; +wire [15:0] add_ln703_253_fu_873_p2; +wire [15:0] add_ln703_241_fu_765_p2; +wire [15:0] add_ln703_255_fu_887_p2; +wire [15:0] add_ln703_242_fu_769_p2; +wire [15:0] add_ln703_244_fu_778_p2; +wire [15:0] add_ln703_245_fu_783_p2; +wire [15:0] sub_ln703_134_fu_792_p2; +wire [15:0] add_ln703_248_fu_801_p2; +wire [15:0] sub_ln703_139_fu_821_p2; +wire [15:0] sub_ln703_140_fu_826_p2; +wire [15:0] add_ln703_249_fu_830_p2; +wire [15:0] sub_ln703_124_fu_723_p2; +wire [15:0] sub_ln703_142_fu_840_p2; +wire [15:0] sub_ln703_127_fu_732_p2; +wire [15:0] sub_ln703_131_fu_745_p2; +wire [15:0] add_ln703_252_fu_853_p2; +wire [15:0] sub_ln703_104_fu_633_p2; +wire [15:0] add_ln703_263_fu_970_p2; +wire [15:0] add_ln703_262_fu_965_p2; +wire [15:0] sub_ln703_146_fu_868_p2; +wire [15:0] add_ln703_254_fu_877_p2; +wire [15:0] sub_ln703_147_fu_882_p2; +wire [15:0] add_ln703_256_fu_891_p2; +wire [15:0] sub_ln703_148_fu_896_p2; +wire [15:0] sub_ln703_151_fu_911_p2; +wire [15:0] sub_ln703_153_fu_915_p2; +wire [15:0] add_ln703_257_fu_925_p2; +wire [15:0] sub_ln703_156_fu_930_p2; +wire [15:0] sub_ln703_157_fu_935_p2; +wire [15:0] add_ln703_259_fu_940_p2; +wire [15:0] sub_ln703_159_fu_945_p2; +wire [15:0] add_ln703_260_fu_950_p2; +wire [15:0] add_ln703_264_fu_974_p2; +wire [15:0] sub_ln703_163_fu_985_p2; +wire [15:0] sub_ln703_164_fu_990_p2; +wire [15:0] sub_ln703_165_fu_995_p2; +wire [15:0] sub_ln703_150_fu_906_p2; +wire [15:0] sub_ln703_168_fu_1005_p2; +wire [15:0] sub_ln703_120_fu_691_p2; +wire [15:0] add_ln703_273_fu_1085_p2; +wire [15:0] add_ln703_271_fu_1080_p2; +wire [15:0] add_ln703_265_fu_1010_p2; +wire [15:0] sub_ln703_136_fu_806_p2; +wire [15:0] sub_ln703_137_fu_811_p2; +wire [15:0] sub_ln703_172_fu_1020_p2; +wire [15:0] sub_ln703_174_fu_1030_p2; +wire [15:0] sub_ln703_175_fu_1035_p2; +wire [15:0] add_ln703_280_fu_1125_p2; +wire [15:0] sub_ln703_130_fu_741_p2; +wire [15:0] add_ln703_282_fu_1135_p2; +wire [15:0] add_ln703_269_fu_1069_p2; +wire [15:0] sub_ln703_184_fu_1075_p2; +wire [15:0] add_ln703_302_fu_1160_p2; +wire [15:0] add_ln703_305_fu_1169_p2; +wire [15:0] add_ln703_303_fu_1164_p2; +wire [15:0] sub_ln703_135_fu_796_p2; +wire [15:0] add_ln703_306_fu_1173_p2; +wire [15:0] sub_ln703_152_fu_1202_p2; +wire [15:0] sub_ln703_155_fu_1206_p2; +wire [15:0] sub_ln703_158_fu_1210_p2; +wire [15:0] sub_ln703_160_fu_1214_p2; +wire [15:0] sub_ln703_167_fu_1218_p2; +wire [15:0] sub_ln703_169_fu_1222_p2; +wire [15:0] sub_ln703_170_fu_1227_p2; +wire [15:0] add_ln703_266_fu_1232_p2; +wire [15:0] sub_ln703_177_fu_1237_p2; +wire [15:0] sub_ln703_179_fu_1246_p2; +wire [15:0] add_ln703_284_fu_1296_p2; +wire [15:0] sub_ln703_183_fu_1250_p2; +wire [15:0] add_ln703_270_fu_1255_p2; +wire [15:0] add_ln703_275_fu_1260_p2; +wire [15:0] add_ln703_277_fu_1264_p2; +wire [15:0] add_ln703_279_fu_1268_p2; +wire [15:0] sub_ln703_186_fu_1272_p2; +wire [15:0] sub_ln703_190_fu_1281_p2; +wire [15:0] sub_ln703_192_fu_1286_p2; +wire [15:0] sub_ln703_178_fu_1242_p2; +wire [15:0] sub_ln703_193_fu_1291_p2; +wire [15:0] add_ln703_285_fu_1300_p2; +wire [15:0] add_ln703_286_fu_1305_p2; +wire [15:0] sub_ln703_194_fu_1309_p2; +wire [15:0] sub_ln703_195_fu_1313_p2; +wire [15:0] sub_ln703_196_fu_1317_p2; +wire [15:0] add_ln703_296_fu_1432_p2; +wire [15:0] sub_ln703_197_fu_1321_p2; +wire [15:0] sub_ln703_202_fu_1335_p2; +wire [15:0] sub_ln703_204_fu_1344_p2; +wire [15:0] sub_ln703_205_fu_1349_p2; +wire [15:0] add_ln703_289_fu_1359_p2; +wire [15:0] sub_ln703_206_fu_1363_p2; +wire [15:0] add_ln703_290_fu_1367_p2; +wire [15:0] add_ln703_292_fu_1376_p2; +wire [15:0] add_ln703_293_fu_1380_p2; +wire [15:0] sub_ln703_208_fu_1389_p2; +wire [15:0] add_ln703_294_fu_1397_p2; +wire [15:0] sub_ln703_210_fu_1402_p2; +wire [15:0] add_ln703_308_fu_1509_p2; +wire [15:0] sub_ln703_211_fu_1407_p2; +wire [15:0] add_ln703_311_fu_1523_p2; +wire [15:0] sub_ln703_213_fu_1417_p2; +wire [15:0] add_ln703_295_fu_1427_p2; +wire [15:0] add_ln703_297_fu_1436_p2; +wire [15:0] sub_ln703_217_fu_1450_p2; +wire [15:0] sub_ln703_201_fu_1331_p2; +wire [15:0] add_ln703_298_fu_1454_p2; +wire [15:0] add_ln703_317_fu_1562_p2; +wire [15:0] sub_ln703_220_fu_1459_p2; +wire [15:0] add_ln703_299_fu_1464_p2; +wire [15:0] sub_ln703_222_fu_1469_p2; +wire [15:0] add_ln703_300_fu_1474_p2; +wire [15:0] sub_ln703_223_fu_1479_p2; +wire [15:0] sub_ln703_225_fu_1484_p2; +wire [15:0] sub_ln703_226_fu_1489_p2; +wire [15:0] add_ln703_310_fu_1513_p2; +wire [15:0] add_ln703_312_fu_1527_p2; +wire [15:0] add_ln703_313_fu_1532_p2; +wire [15:0] sub_ln703_231_fu_1537_p2; +wire [15:0] sub_ln703_232_fu_1542_p2; +wire [15:0] add_ln703_315_fu_1552_p2; +wire [15:0] sub_ln703_236_fu_1557_p2; +wire [15:0] add_ln703_318_fu_1566_p2; +wire [15:0] sub_ln703_240_fu_1581_p2; +wire [15:0] sub_ln703_241_fu_1586_p2; +wire [15:0] sub_ln703_188_fu_1277_p2; +wire [15:0] add_ln703_324_fu_1661_p2; +wire [15:0] add_ln703_322_fu_1656_p2; +wire [15:0] add_ln703_319_fu_1591_p2; +wire [15:0] sub_ln703_242_fu_1596_p2; +wire [15:0] sub_ln703_243_fu_1601_p2; +wire [15:0] sub_ln703_228_fu_1499_p2; +wire [15:0] sub_ln703_248_fu_1606_p2; +wire [15:0] sub_ln703_251_fu_1611_p2; +wire [15:0] sub_ln703_214_fu_1422_p2; +wire [15:0] add_ln703_329_fu_1705_p2; +wire [15:0] sub_ln703_216_fu_1446_p2; +wire [15:0] add_ln703_332_fu_1715_p2; +wire [15:0] sub_ln703_234_fu_1547_p2; +wire [15:0] sub_ln703_256_fu_1631_p2; +wire [15:0] add_ln703_325_fu_1665_p2; +wire [15:0] sub_ln703_209_fu_1393_p2; +wire [15:0] sub_ln703_268_fu_1691_p2; +wire [15:0] add_ln703_333_fu_1720_p2; +wire [15:0] add_ln703_334_fu_1725_p2; +wire [15:0] sub_ln703_218_fu_1784_p2; +wire [15:0] sub_ln703_221_fu_1792_p2; +wire [15:0] sub_ln703_224_fu_1796_p2; +wire [15:0] sub_ln703_227_fu_1800_p2; +wire [15:0] sub_ln703_230_fu_1804_p2; +wire [15:0] sub_ln703_233_fu_1808_p2; +wire [15:0] sub_ln703_239_fu_1817_p2; +wire [15:0] add_ln703_320_fu_1822_p2; +wire [15:0] sub_ln703_245_fu_1832_p2; +wire [15:0] sub_ln703_247_fu_1836_p2; +wire [15:0] sub_ln703_249_fu_1840_p2; +wire [15:0] sub_ln703_250_fu_1844_p2; +wire [15:0] sub_ln703_255_fu_1849_p2; +wire [15:0] sub_ln703_258_fu_1854_p2; +wire [15:0] sub_ln703_260_fu_1862_p2; +wire [15:0] add_ln703_340_fu_1943_p2; +wire [15:0] add_ln703_341_fu_1947_p2; +wire [15:0] sub_ln703_269_fu_1877_p2; +wire [15:0] sub_ln703_271_fu_1882_p2; +wire [15:0] add_ln703_327_fu_1887_p2; +wire [15:0] add_ln703_328_fu_1892_p2; +wire [15:0] sub_ln703_273_fu_1896_p2; +wire [15:0] add_ln703_331_fu_1900_p2; +wire [15:0] sub_ln703_274_fu_1904_p2; +wire [15:0] sub_ln703_275_fu_1909_p2; +wire [15:0] sub_ln703_219_fu_1788_p2; +wire [15:0] add_ln703_350_fu_2026_p2; +wire [15:0] add_ln703_349_fu_2021_p2; +wire [15:0] add_ln703_336_fu_1913_p2; +wire [15:0] add_ln703_337_fu_1923_p2; +wire [15:0] sub_ln703_277_fu_1927_p2; +wire [15:0] sub_ln703_279_fu_1931_p2; +wire [15:0] sub_ln703_264_fu_1867_p2; +wire [15:0] sub_ln703_280_fu_1935_p2; +wire [15:0] add_ln703_338_fu_1939_p2; +wire [15:0] add_ln703_342_fu_1952_p2; +wire [15:0] sub_ln703_281_fu_1957_p2; +wire [15:0] sub_ln703_282_fu_1961_p2; +wire [15:0] add_ln703_344_fu_1966_p2; +wire [15:0] add_ln703_345_fu_1970_p2; +wire [15:0] sub_ln703_286_fu_1989_p2; +wire [15:0] add_ln703_346_fu_1993_p2; +wire [15:0] sub_ln703_235_fu_1812_p2; +wire [15:0] add_ln703_358_fu_2123_p2; +wire [15:0] add_ln703_356_fu_2118_p2; +wire [15:0] sub_ln703_291_fu_2008_p2; +wire [15:0] sub_ln703_292_fu_2012_p2; +wire [15:0] add_ln703_348_fu_2017_p2; +wire [15:0] add_ln703_351_fu_2030_p2; +wire [15:0] sub_ln703_259_fu_1858_p2; +wire [15:0] add_ln703_361_fu_2153_p2; +wire [15:0] sub_ln703_295_fu_2041_p2; +wire [15:0] sub_ln703_296_fu_2046_p2; +wire [15:0] add_ln703_352_fu_2051_p2; +wire [15:0] sub_ln703_297_fu_2055_p2; +wire [15:0] sub_ln703_298_fu_2065_p2; +wire [15:0] sub_ln703_301_fu_2085_p2; +wire [15:0] sub_ln703_303_fu_2094_p2; +wire [15:0] sub_ln703_305_fu_2104_p2; +wire [15:0] sub_ln703_306_fu_2109_p2; +wire [15:0] add_ln703_355_fu_2114_p2; +wire [15:0] sub_ln703_307_fu_2133_p2; +wire [15:0] add_ln703_360_fu_2138_p2; +wire [15:0] sub_ln703_308_fu_2143_p2; +wire [15:0] sub_ln703_293_fu_2036_p2; +wire [15:0] add_ln703_362_fu_2158_p2; +wire [15:0] add_ln703_363_fu_2163_p2; +wire [15:0] sub_ln703_310_fu_2168_p2; +wire [15:0] add_ln703_364_fu_2178_p2; +wire [15:0] add_ln703_365_fu_2183_p2; +wire [15:0] add_ln703_366_fu_2193_p2; +wire [15:0] sub_ln703_284_fu_1980_p2; +wire [15:0] add_ln703_374_fu_2263_p2; +wire [15:0] add_ln703_367_fu_2198_p2; +wire [15:0] sub_ln703_287_fu_1998_p2; +wire [15:0] add_ln703_376_fu_2278_p2; +wire [15:0] add_ln703_378_fu_2288_p2; +wire [15:0] sub_ln703_319_fu_2208_p2; +wire [15:0] add_ln703_369_fu_2213_p2; +wire [15:0] sub_ln703_322_fu_2223_p2; +wire [15:0] add_ln703_375_fu_2268_p2; +wire [15:0] sub_ln703_285_fu_1984_p2; +wire [15:0] add_ln703_389_fu_2322_p2; +wire [15:0] add_ln703_388_fu_2317_p2; +wire [15:0] add_ln703_380_fu_2297_p2; +wire [15:0] sub_ln703_267_fu_1872_p2; +wire [15:0] add_ln703_399_fu_2342_p2; +wire [15:0] add_ln703_398_fu_2337_p2; +wire [15:0] sub_ln703_299_fu_2070_p2; +wire [15:0] add_ln703_412_fu_2357_p2; +wire [15:0] add_ln703_411_fu_2352_p2; +wire [15:0] sub_ln703_315_fu_2188_p2; +wire [15:0] add_ln703_414_fu_2367_p2; +wire [15:0] sub_ln703_244_fu_1827_p2; +wire [15:0] add_ln703_426_fu_2378_p2; +wire [15:0] sub_ln703_313_fu_2413_p2; +wire [15:0] sub_ln703_314_fu_2417_p2; +wire [15:0] sub_ln703_316_fu_2421_p2; +wire [15:0] add_ln703_368_fu_2429_p2; +wire [15:0] add_ln703_370_fu_2437_p2; +wire [15:0] sub_ln703_326_fu_2441_p2; +wire [15:0] sub_ln703_312_fu_2409_p2; +wire [15:0] add_ln703_373_fu_2445_p2; +wire [15:0] sub_ln703_329_fu_2450_p2; +wire [15:0] sub_ln703_317_fu_2425_p2; +wire [15:0] sub_ln703_334_fu_2464_p2; +wire [15:0] sub_ln703_336_fu_2469_p2; +wire [15:0] sub_ln703_337_fu_2473_p2; +wire [15:0] sub_ln703_338_fu_2478_p2; +wire [15:0] sub_ln703_294_fu_2405_p2; +wire [15:0] add_ln703_395_fu_2564_p2; +wire [15:0] add_ln703_393_fu_2559_p2; +wire [15:0] sub_ln703_339_fu_2482_p2; +wire [15:0] add_ln703_382_fu_2486_p2; +wire [15:0] add_ln703_383_fu_2490_p2; +wire [15:0] sub_ln703_340_fu_2495_p2; +wire [15:0] add_ln703_385_fu_2499_p2; +wire [15:0] sub_ln703_341_fu_2504_p2; +wire [15:0] sub_ln703_342_fu_2509_p2; +wire [15:0] add_ln703_386_fu_2514_p2; +wire [15:0] add_ln703_387_fu_2518_p2; +wire [15:0] sub_ln703_344_fu_2523_p2; +wire [15:0] add_ln703_391_fu_2527_p2; +wire [15:0] sub_ln703_320_fu_2433_p2; +wire [15:0] add_ln703_403_fu_2645_p2; +wire [15:0] sub_ln703_347_fu_2536_p2; +wire [15:0] add_ln703_392_fu_2540_p2; +wire [15:0] sub_ln703_348_fu_2545_p2; +wire [15:0] sub_ln703_350_fu_2554_p2; +wire [15:0] add_ln703_407_fu_2675_p2; +wire [15:0] add_ln703_396_fu_2568_p2; +wire [15:0] sub_ln703_351_fu_2574_p2; +wire [15:0] sub_ln703_352_fu_2579_p2; +wire [15:0] sub_ln703_353_fu_2584_p2; +wire [15:0] sub_ln703_354_fu_2589_p2; +wire [15:0] sub_ln703_355_fu_2594_p2; +wire [15:0] add_ln703_397_fu_2599_p2; +wire [15:0] sub_ln703_358_fu_2613_p2; +wire [15:0] sub_ln703_359_fu_2618_p2; +wire [15:0] add_ln703_417_fu_2737_p2; +wire [15:0] add_ln703_416_fu_2733_p2; +wire [15:0] add_ln703_401_fu_2623_p2; +wire [15:0] sub_ln703_360_fu_2627_p2; +wire [15:0] add_ln703_419_fu_2757_p2; +wire [15:0] sub_ln703_333_fu_2460_p2; +wire [15:0] add_ln703_421_fu_2766_p2; +wire [15:0] sub_ln703_362_fu_2641_p2; +wire [15:0] add_ln703_405_fu_2650_p2; +wire [15:0] add_ln703_406_fu_2655_p2; +wire [15:0] sub_ln703_363_fu_2660_p2; +wire [15:0] sub_ln703_364_fu_2665_p2; +wire [15:0] add_ln703_408_fu_2679_p2; +wire [15:0] sub_ln703_367_fu_2689_p2; +wire [15:0] sub_ln703_368_fu_2694_p2; +wire [15:0] add_ln703_409_fu_2704_p2; +wire [15:0] add_ln703_429_fu_2825_p2; +wire [15:0] add_ln703_430_fu_2829_p2; +wire [15:0] sub_ln703_371_fu_2719_p2; +wire [15:0] sub_ln703_373_fu_2723_p2; +wire [15:0] sub_ln703_376_fu_2752_p2; +wire [15:0] add_ln703_420_fu_2761_p2; +wire [15:0] add_ln703_422_fu_2771_p2; +wire [15:0] sub_ln703_378_fu_2776_p2; +wire [15:0] sub_ln703_380_fu_2786_p2; +wire [15:0] sub_ln703_382_fu_2796_p2; +wire [15:0] sub_ln703_365_fu_2670_p2; +wire [15:0] sub_ln703_370_fu_2714_p2; +wire [15:0] sub_ln703_388_fu_2821_p2; +wire [15:0] add_ln703_431_fu_2834_p2; +wire [15:0] sub_ln703_391_fu_2844_p2; +wire [15:0] sub_ln703_330_fu_2455_p2; +wire [15:0] add_ln703_441_fu_2913_p2; +wire [15:0] add_ln703_440_fu_2908_p2; +wire [15:0] sub_ln703_396_fu_2858_p2; +wire [15:0] sub_ln703_400_fu_2868_p2; +wire [15:0] sub_ln703_383_fu_2801_p2; +wire [15:0] add_ln703_438_fu_2888_p2; +wire [15:0] sub_ln703_345_fu_2532_p2; +wire [15:0] add_ln703_477_fu_2947_p2; +wire [15:0] add_ln703_479_fu_2957_p2; +wire [15:0] add_ln703_478_fu_2952_p2; +wire [15:0] sub_ln703_395_fu_2853_p2; +wire [15:0] sub_ln703_349_fu_2549_p2; +wire [15:0] sub_ln703_372_fu_2985_p2; +wire [15:0] sub_ln703_377_fu_2989_p2; +wire [15:0] add_ln703_423_fu_2993_p2; +wire [15:0] sub_ln703_384_fu_2997_p2; +wire [15:0] add_ln703_425_fu_3001_p2; +wire [15:0] sub_ln703_387_fu_3005_p2; +wire [15:0] sub_ln703_390_fu_3009_p2; +wire [15:0] add_ln703_432_fu_3014_p2; +wire [15:0] sub_ln703_393_fu_3018_p2; +wire [15:0] sub_ln703_394_fu_3022_p2; +wire [15:0] sub_ln703_399_fu_3031_p2; +wire [15:0] add_ln703_433_fu_3036_p2; +wire [15:0] sub_ln703_401_fu_3040_p2; +wire [15:0] sub_ln703_403_fu_3044_p2; +wire [15:0] sub_ln703_404_fu_3049_p2; +wire [15:0] add_ln703_437_fu_3053_p2; +wire [15:0] sub_ln703_406_fu_3062_p2; +wire [15:0] sub_ln703_410_fu_3071_p2; +wire [15:0] add_ln703_439_fu_3075_p2; +wire [15:0] add_ln703_450_fu_3168_p2; +wire [15:0] sub_ln703_412_fu_3080_p2; +wire [15:0] add_ln703_443_fu_3099_p2; +wire [15:0] sub_ln703_417_fu_3103_p2; +wire [15:0] sub_ln703_418_fu_3108_p2; +wire [15:0] sub_ln703_419_fu_3113_p2; +wire [15:0] sub_ln703_420_fu_3117_p2; +wire [15:0] add_ln703_445_fu_3122_p2; +wire [15:0] sub_ln703_424_fu_3140_p2; +wire [15:0] add_ln703_455_fu_3237_p2; +wire [15:0] sub_ln703_405_fu_3057_p2; +wire [15:0] sub_ln703_425_fu_3145_p2; +wire [15:0] add_ln703_448_fu_3150_p2; +wire [15:0] sub_ln703_427_fu_3154_p2; +wire [15:0] add_ln703_449_fu_3158_p2; +wire [15:0] add_ln703_452_fu_3172_p2; +wire [15:0] sub_ln703_429_fu_3177_p2; +wire [15:0] sub_ln703_431_fu_3185_p2; +wire [15:0] sub_ln703_413_fu_3084_p2; +wire [15:0] sub_ln703_415_fu_3094_p2; +wire [15:0] sub_ln703_432_fu_3190_p2; +wire [15:0] sub_ln703_433_fu_3194_p2; +wire [15:0] sub_ln703_436_fu_3208_p2; +wire [15:0] sub_ln703_437_fu_3213_p2; +wire [15:0] add_ln703_453_fu_3218_p2; +wire [15:0] sub_ln703_438_fu_3223_p2; +wire [15:0] sub_ln703_421_fu_3126_p2; +wire [15:0] sub_ln703_439_fu_3228_p2; +wire [15:0] sub_ln703_422_fu_3130_p2; +wire [15:0] add_ln703_454_fu_3232_p2; +wire [15:0] add_ln703_456_fu_3241_p2; +wire [15:0] sub_ln703_440_fu_3247_p2; +wire [15:0] sub_ln703_407_fu_3066_p2; +wire [15:0] add_ln703_466_fu_3358_p2; +wire [15:0] sub_ln703_441_fu_3252_p2; +wire [15:0] sub_ln703_444_fu_3266_p2; +wire [15:0] sub_ln703_445_fu_3271_p2; +wire [15:0] sub_ln703_446_fu_3276_p2; +wire [15:0] add_ln703_457_fu_3281_p2; +wire [15:0] add_ln703_458_fu_3286_p2; +wire [15:0] sub_ln703_414_fu_3089_p2; +wire [15:0] add_ln703_470_fu_3398_p2; +wire [15:0] add_ln703_459_fu_3292_p2; +wire [15:0] sub_ln703_447_fu_3298_p2; +wire [15:0] add_ln703_460_fu_3303_p2; +wire [15:0] sub_ln703_398_fu_3026_p2; +wire [15:0] add_ln703_474_fu_3428_p2; +wire [15:0] add_ln703_473_fu_3423_p2; +wire [15:0] add_ln703_461_fu_3323_p2; +wire [15:0] sub_ln703_423_fu_3135_p2; +wire [15:0] add_ln703_481_fu_3443_p2; +wire [15:0] sub_ln703_442_fu_3256_p2; +wire [15:0] sub_ln703_443_fu_3261_p2; +wire [15:0] add_ln703_469_fu_3383_p2; +wire [15:0] sub_ln703_430_fu_3181_p2; +wire [15:0] add_ln703_489_fu_3468_p2; +wire [15:0] add_ln703_472_fu_3413_p2; +wire [15:0] sub_ln703_435_fu_3204_p2; +wire [15:0] add_ln703_494_fu_3487_p2; +wire [15:0] sub_ln703_449_fu_3313_p2; +wire [15:0] add_ln703_486_fu_3453_p2; +wire [15:0] add_ln703_487_fu_3458_p2; +wire [15:0] add_ln703_490_fu_3473_p2; +wire [15:0] add_ln703_495_fu_3492_p2; +wire [15:0] add_ln703_476_fu_3531_p2; +wire [15:0] sub_ln703_460_fu_3535_p2; +wire [15:0] sub_ln703_462_fu_3539_p2; +wire [15:0] sub_ln703_463_fu_3543_p2; +wire [15:0] sub_ln703_464_fu_3547_p2; +wire [15:0] sub_ln703_465_fu_3551_p2; +wire [15:0] add_ln703_484_fu_3555_p2; +wire [15:0] add_ln703_485_fu_3559_p2; +wire [15:0] sub_ln703_466_fu_3563_p2; +wire [15:0] sub_ln703_467_fu_3567_p2; +wire [15:0] add_ln703_488_fu_3571_p2; +wire [15:0] sub_ln703_468_fu_3575_p2; +wire [15:0] sub_ln703_470_fu_3579_p2; +wire [15:0] sub_ln703_471_fu_3583_p2; +wire [15:0] sub_ln703_472_fu_3587_p2; +wire [15:0] sub_ln703_473_fu_3591_p2; +wire [15:0] add_ln703_493_fu_3595_p2; +wire [15:0] sub_ln703_475_fu_3599_p2; +wire [15:0] sub_ln703_476_fu_3603_p2; +wire [15:0] sub_ln703_477_fu_3607_p2; +wire [15:0] sub_ln703_478_fu_3612_p2; +wire [15:0] add_ln703_498_fu_3616_p2; +wire [15:0] sub_ln703_479_fu_3621_p2; +wire [15:0] sub_ln703_480_fu_3626_p2; +wire [15:0] add_ln703_499_fu_3631_p2; +wire [15:0] sub_ln703_482_fu_3640_p2; +wire [15:0] sub_ln703_483_fu_3645_p2; +wire [15:0] sub_ln703_484_fu_3650_p2; +wire [15:0] add_ln703_500_fu_3655_p2; +wire [15:0] sub_ln703_485_fu_3660_p2; +wire [15:0] sub_ln703_488_fu_3665_p2; +wire [15:0] sub_ln703_489_fu_3670_p2; +wire [15:0] sub_ln703_492_fu_3679_p2; +wire [15:0] sub_ln703_493_fu_3684_p2; +wire [15:0] sub_ln703_494_fu_3689_p2; +wire [15:0] sub_ln703_495_fu_3694_p2; +wire [15:0] sub_ln703_496_fu_3699_p2; +wire [15:0] add_ln703_501_fu_3708_p2; +wire [15:0] add_ln703_502_fu_3713_p2; +wire [15:0] sub_ln703_499_fu_3723_p2; +wire [15:0] add_ln703_508_fu_3843_p2; +wire [15:0] sub_ln703_501_fu_3728_p2; +wire [15:0] sub_ln703_502_fu_3732_p2; +wire [15:0] add_ln703_514_fu_3862_p2; +wire [15:0] add_ln703_518_fu_3875_p2; +wire [15:0] add_ln703_517_fu_3871_p2; +wire [15:0] sub_ln703_503_fu_3737_p2; +wire [15:0] sub_ln703_504_fu_3742_p2; +wire [15:0] sub_ln703_505_fu_3747_p2; +wire [15:0] sub_ln703_481_fu_3636_p2; +wire [15:0] sub_ln703_506_fu_3752_p2; +wire [15:0] add_ln703_503_fu_3757_p2; +wire [15:0] sub_ln703_507_fu_3762_p2; +wire [15:0] sub_ln703_508_fu_3767_p2; +wire [15:0] sub_ln703_509_fu_3772_p2; +wire [15:0] add_ln703_504_fu_3777_p2; +wire [15:0] sub_ln703_510_fu_3781_p2; +wire [15:0] add_ln703_505_fu_3785_p2; +wire [15:0] add_ln703_527_fu_3949_p2; +wire [15:0] add_ln703_526_fu_3945_p2; +wire [15:0] sub_ln703_511_fu_3790_p2; +wire [15:0] sub_ln703_490_fu_3675_p2; +wire [15:0] add_ln703_506_fu_3795_p2; +wire [15:0] add_ln703_507_fu_3799_p2; +wire [15:0] sub_ln703_512_fu_3804_p2; +wire [15:0] sub_ln703_513_fu_3809_p2; +wire [15:0] sub_ln703_514_fu_3814_p2; +wire [15:0] sub_ln703_515_fu_3819_p2; +wire [15:0] sub_ln703_497_fu_3704_p2; +wire [15:0] sub_ln703_516_fu_3824_p2; +wire [15:0] sub_ln703_517_fu_3829_p2; +wire [15:0] sub_ln703_498_fu_3718_p2; +wire [15:0] sub_ln703_518_fu_3834_p2; +wire [15:0] sub_ln703_519_fu_3839_p2; +wire [15:0] add_ln703_511_fu_3847_p2; +wire [15:0] acc_1_V_fu_3852_p2; +wire [15:0] acc_2_V_fu_3857_p2; +wire [15:0] acc_3_V_fu_3866_p2; +wire [15:0] acc_4_V_fu_3879_p2; +wire [15:0] acc_5_V_fu_3885_p2; +wire [15:0] acc_6_V_fu_3890_p2; +wire [15:0] acc_7_V_fu_3895_p2; +wire [15:0] acc_8_V_fu_3900_p2; +wire [15:0] acc_9_V_fu_3905_p2; +wire [15:0] acc_10_V_fu_3910_p2; +wire [15:0] acc_11_V_fu_3915_p2; +wire [15:0] acc_12_V_fu_3920_p2; +wire [15:0] acc_13_V_fu_3925_p2; +wire [15:0] acc_14_V_fu_3930_p2; +wire [15:0] acc_15_V_fu_3935_p2; +wire [15:0] acc_16_V_fu_3940_p2; +wire [15:0] acc_17_V_fu_3953_p2; +wire [15:0] acc_18_V_fu_3959_p2; +wire [15:0] acc_19_V_fu_3964_p2; +wire [15:0] acc_20_V_fu_3969_p2; +wire [15:0] acc_21_V_fu_3974_p2; +wire [15:0] acc_22_V_fu_3979_p2; +wire [15:0] acc_23_V_fu_3984_p2; +wire [15:0] acc_24_V_fu_3989_p2; +wire [15:0] acc_25_V_fu_3994_p2; +wire [15:0] acc_26_V_fu_3999_p2; +wire [15:0] acc_27_V_fu_4004_p2; +wire [15:0] acc_28_V_fu_4009_p2; +wire [15:0] acc_29_V_fu_4014_p2; +wire [15:0] acc_30_V_fu_4019_p2; +wire [15:0] acc_31_V_fu_4024_p2; +reg ap_ce_reg; +reg [15:0] data_0_V_read_int_reg; +reg [15:0] data_1_V_read_int_reg; +reg [15:0] data_2_V_read_int_reg; +reg [15:0] data_3_V_read_int_reg; +reg [15:0] data_4_V_read_int_reg; +reg [15:0] data_5_V_read_int_reg; +reg [15:0] data_6_V_read_int_reg; +reg [15:0] data_7_V_read_int_reg; +reg [15:0] data_8_V_read_int_reg; +reg [15:0] data_9_V_read_int_reg; +reg [15:0] data_10_V_read_int_reg; +reg [15:0] data_11_V_read_int_reg; +reg [15:0] data_12_V_read_int_reg; +reg [15:0] data_13_V_read_int_reg; +reg [15:0] data_14_V_read_int_reg; +reg [15:0] data_15_V_read_int_reg; +reg [15:0] data_16_V_read_int_reg; +reg [15:0] data_17_V_read_int_reg; +reg [15:0] data_18_V_read_int_reg; +reg [15:0] data_19_V_read_int_reg; +reg [15:0] data_20_V_read_int_reg; +reg [15:0] data_21_V_read_int_reg; +reg [15:0] data_22_V_read_int_reg; +reg [15:0] data_23_V_read_int_reg; +reg [15:0] data_24_V_read_int_reg; +reg [15:0] data_25_V_read_int_reg; +reg [15:0] data_26_V_read_int_reg; +reg [15:0] data_27_V_read_int_reg; +reg [15:0] data_28_V_read_int_reg; +reg [15:0] data_29_V_read_int_reg; +reg [15:0] data_30_V_read_int_reg; +reg [15:0] data_31_V_read_int_reg; +reg [15:0] ap_return_0_int_reg; +reg [15:0] ap_return_1_int_reg; +reg [15:0] ap_return_2_int_reg; +reg [15:0] ap_return_3_int_reg; +reg [15:0] ap_return_4_int_reg; +reg [15:0] ap_return_5_int_reg; +reg [15:0] ap_return_6_int_reg; +reg [15:0] ap_return_7_int_reg; +reg [15:0] ap_return_8_int_reg; +reg [15:0] ap_return_9_int_reg; +reg [15:0] ap_return_10_int_reg; +reg [15:0] ap_return_11_int_reg; +reg [15:0] ap_return_12_int_reg; +reg [15:0] ap_return_13_int_reg; +reg [15:0] ap_return_14_int_reg; +reg [15:0] ap_return_15_int_reg; +reg [15:0] ap_return_16_int_reg; +reg [15:0] ap_return_17_int_reg; +reg [15:0] ap_return_18_int_reg; +reg [15:0] ap_return_19_int_reg; +reg [15:0] ap_return_20_int_reg; +reg [15:0] ap_return_21_int_reg; +reg [15:0] ap_return_22_int_reg; +reg [15:0] ap_return_23_int_reg; +reg [15:0] ap_return_24_int_reg; +reg [15:0] ap_return_25_int_reg; +reg [15:0] ap_return_26_int_reg; +reg [15:0] ap_return_27_int_reg; +reg [15:0] ap_return_28_int_reg; +reg [15:0] ap_return_29_int_reg; +reg [15:0] ap_return_30_int_reg; +reg [15:0] ap_return_31_int_reg; + +always @ (posedge ap_clk) begin + ap_ce_reg <= ap_ce; +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + add_ln703_200_reg_5077 <= add_ln703_200_fu_304_p2; + add_ln703_200_reg_5077_pp0_iter2_reg <= add_ln703_200_reg_5077; + add_ln703_201_reg_5090 <= add_ln703_201_fu_312_p2; + add_ln703_201_reg_5090_pp0_iter2_reg <= add_ln703_201_reg_5090; + add_ln703_202_reg_5096 <= add_ln703_202_fu_316_p2; + add_ln703_202_reg_5096_pp0_iter2_reg <= add_ln703_202_reg_5096; + add_ln703_203_reg_5113 <= add_ln703_203_fu_329_p2; + add_ln703_204_reg_5101 <= add_ln703_204_fu_320_p2; + add_ln703_204_reg_5101_pp0_iter2_reg <= add_ln703_204_reg_5101; + add_ln703_205_reg_5119 <= add_ln703_205_fu_333_p2; + add_ln703_206_reg_5131 <= add_ln703_206_fu_341_p2; + add_ln703_207_reg_5107 <= add_ln703_207_fu_325_p2; + add_ln703_207_reg_5107_pp0_iter2_reg <= add_ln703_207_reg_5107; + add_ln703_208_reg_5137 <= add_ln703_208_fu_345_p2; + add_ln703_209_reg_5178 <= add_ln703_209_fu_416_p2; + add_ln703_210_reg_5143 <= add_ln703_210_fu_349_p2; + add_ln703_210_reg_5143_pp0_iter3_reg <= add_ln703_210_reg_5143; + add_ln703_211_reg_5184 <= add_ln703_211_fu_420_p2; + add_ln703_213_reg_5189 <= add_ln703_213_fu_429_p2; + add_ln703_214_reg_5194 <= add_ln703_214_fu_433_p2; + add_ln703_216_reg_5215 <= add_ln703_216_fu_461_p2; + add_ln703_220_reg_5221 <= add_ln703_220_fu_484_p2; + add_ln703_223_reg_5231 <= add_ln703_223_fu_507_p2; + add_ln703_225_reg_5237 <= add_ln703_225_fu_513_p2; + add_ln703_227_reg_5242 <= add_ln703_227_fu_522_p2; + add_ln703_233_reg_5149 <= add_ln703_233_fu_353_p2; + add_ln703_233_reg_5149_pp0_iter3_reg <= add_ln703_233_reg_5149; + add_ln703_234_reg_5264 <= add_ln703_234_fu_564_p2; + add_ln703_238_reg_5269 <= add_ln703_238_fu_569_p2; + add_ln703_246_reg_5320 <= add_ln703_246_fu_787_p2; + add_ln703_247_reg_5159 <= add_ln703_247_fu_357_p2; + add_ln703_247_reg_5159_pp0_iter3_reg <= add_ln703_247_reg_5159; + add_ln703_251_reg_5289 <= add_ln703_251_fu_589_p2; + add_ln703_258_reg_5295 <= add_ln703_258_fu_593_p2; + add_ln703_261_reg_5360 <= add_ln703_261_fu_955_p2; + add_ln703_267_reg_5405 <= add_ln703_267_fu_1055_p2; + add_ln703_268_reg_5415 <= add_ln703_268_fu_1065_p2; + add_ln703_272_reg_5304 <= add_ln703_272_fu_597_p2; + add_ln703_272_reg_5304_pp0_iter4_reg <= add_ln703_272_reg_5304; + add_ln703_274_reg_5420 <= add_ln703_274_fu_1089_p2; + add_ln703_276_reg_5430 <= add_ln703_276_fu_1100_p2; + add_ln703_278_reg_5435 <= add_ln703_278_fu_1105_p2; + add_ln703_281_reg_5455 <= add_ln703_281_fu_1129_p2; + add_ln703_283_reg_5460 <= add_ln703_283_fu_1140_p2; + add_ln703_287_reg_5525 <= add_ln703_287_fu_1354_p2; + add_ln703_288_reg_5475 <= add_ln703_288_fu_1156_p2; + add_ln703_291_reg_5530 <= add_ln703_291_fu_1371_p2; + add_ln703_301_reg_5550 <= add_ln703_301_fu_1494_p2; + add_ln703_304_reg_5314 <= add_ln703_304_fu_601_p2; + add_ln703_307_reg_5555 <= add_ln703_307_fu_1504_p2; + add_ln703_309_reg_5484 <= add_ln703_309_fu_1179_p2; + add_ln703_314_reg_5490 <= add_ln703_314_fu_1183_p2; + add_ln703_316_reg_5496 <= add_ln703_316_fu_1187_p2; + add_ln703_321_reg_5590 <= add_ln703_321_fu_1636_p2; + add_ln703_323_reg_5506 <= add_ln703_323_fu_1198_p2; + add_ln703_326_reg_5625 <= add_ln703_326_fu_1686_p2; + add_ln703_330_reg_5640 <= add_ln703_330_fu_1710_p2; + add_ln703_335_reg_5645 <= add_ln703_335_fu_1730_p2; + add_ln703_339_reg_5655 <= add_ln703_339_fu_1740_p2; + add_ln703_343_reg_5660 <= add_ln703_343_fu_1745_p2; + add_ln703_347_reg_5675 <= add_ln703_347_fu_1760_p2; + add_ln703_353_reg_5743 <= add_ln703_353_fu_2060_p2; + add_ln703_354_reg_5753 <= add_ln703_354_fu_2080_p2; + add_ln703_357_reg_5683 <= add_ln703_357_fu_1764_p2; + add_ln703_357_reg_5683_pp0_iter6_reg <= add_ln703_357_reg_5683; + add_ln703_359_reg_5768 <= add_ln703_359_fu_2127_p2; + add_ln703_371_reg_5691 <= add_ln703_371_fu_1768_p2; + add_ln703_372_reg_5793 <= add_ln703_372_fu_2228_p2; + add_ln703_377_reg_5833 <= add_ln703_377_fu_2283_p2; + add_ln703_379_reg_5838 <= add_ln703_379_fu_2292_p2; + add_ln703_381_reg_5848 <= add_ln703_381_fu_2307_p2; + add_ln703_384_reg_5701 <= add_ln703_384_fu_1772_p2; + add_ln703_384_reg_5701_pp0_iter6_reg <= add_ln703_384_reg_5701; + add_ln703_390_reg_5858 <= add_ln703_390_fu_2326_p2; + add_ln703_394_reg_5710 <= add_ln703_394_fu_1776_p2; + add_ln703_394_reg_5710_pp0_iter6_reg <= add_ln703_394_reg_5710; + add_ln703_400_reg_5868 <= add_ln703_400_fu_2346_p2; + add_ln703_402_reg_5931 <= add_ln703_402_fu_2631_p2; + add_ln703_404_reg_5718 <= add_ln703_404_fu_1780_p2; + add_ln703_404_reg_5718_pp0_iter6_reg <= add_ln703_404_reg_5718; + add_ln703_410_reg_5951 <= add_ln703_410_fu_2709_p2; + add_ln703_413_reg_5873 <= add_ln703_413_fu_2361_p2; + add_ln703_415_reg_5878 <= add_ln703_415_fu_2372_p2; + add_ln703_418_reg_5961 <= add_ln703_418_fu_2741_p2; + add_ln703_424_reg_5981 <= add_ln703_424_fu_2806_p2; + add_ln703_427_reg_5883 <= add_ln703_427_fu_2383_p2; + add_ln703_428_reg_5888 <= add_ln703_428_fu_2389_p2; + add_ln703_434_reg_6011 <= add_ln703_434_fu_2873_p2; + add_ln703_435_reg_5894 <= add_ln703_435_fu_2393_p2; + add_ln703_436_reg_6021 <= add_ln703_436_fu_2883_p2; + add_ln703_442_reg_6041 <= add_ln703_442_fu_2917_p2; + add_ln703_444_reg_6051 <= add_ln703_444_fu_2928_p2; + add_ln703_446_reg_5901 <= add_ln703_446_fu_2397_p2; + add_ln703_447_reg_6056 <= add_ln703_447_fu_2933_p2; + add_ln703_451_reg_6066 <= add_ln703_451_fu_2943_p2; + add_ln703_451_reg_6066_pp0_iter8_reg <= add_ln703_451_reg_6066; + add_ln703_462_reg_5909 <= add_ln703_462_fu_2401_p2; + add_ln703_462_reg_5909_pp0_iter7_reg <= add_ln703_462_reg_5909; + add_ln703_462_reg_5909_pp0_iter8_reg <= add_ln703_462_reg_5909_pp0_iter7_reg; + add_ln703_463_reg_6128 <= add_ln703_463_fu_3328_p2; + add_ln703_464_reg_6133 <= add_ln703_464_fu_3333_p2; + add_ln703_465_reg_6138 <= add_ln703_465_fu_3338_p2; + add_ln703_467_reg_6158 <= add_ln703_467_fu_3363_p2; + add_ln703_468_reg_6173 <= add_ln703_468_fu_3378_p2; + add_ln703_471_reg_6188 <= add_ln703_471_fu_3403_p2; + add_ln703_475_reg_6203 <= add_ln703_475_fu_3432_p2; + add_ln703_480_reg_6072 <= add_ln703_480_fu_2961_p2; + add_ln703_480_reg_6072_pp0_iter8_reg <= add_ln703_480_reg_6072; + add_ln703_482_reg_6077 <= add_ln703_482_fu_2967_p2; + add_ln703_483_reg_6213 <= add_ln703_483_fu_3448_p2; + add_ln703_491_reg_6087 <= add_ln703_491_fu_2971_p2; + add_ln703_491_reg_6087_pp0_iter8_reg <= add_ln703_491_reg_6087; + add_ln703_492_reg_6223 <= add_ln703_492_fu_3478_p2; + add_ln703_496_reg_6234 <= add_ln703_496_fu_3497_p2; + add_ln703_497_reg_6239 <= add_ln703_497_fu_3501_p2; + add_ln703_509_reg_6092 <= add_ln703_509_fu_2976_p2; + add_ln703_509_reg_6092_pp0_iter8_reg <= add_ln703_509_reg_6092; + add_ln703_510_reg_6264 <= add_ln703_510_fu_3527_p2; + add_ln703_516_reg_6103 <= add_ln703_516_fu_2980_p2; + add_ln703_516_reg_6103_pp0_iter8_reg <= add_ln703_516_reg_6103; + add_ln703_reg_5052 <= add_ln703_fu_280_p2; + data_10_V_read11_reg_4832 <= data_10_V_read_int_reg; + data_10_V_read11_reg_4832_pp0_iter1_reg <= data_10_V_read11_reg_4832; + data_10_V_read11_reg_4832_pp0_iter2_reg <= data_10_V_read11_reg_4832_pp0_iter1_reg; + data_10_V_read11_reg_4832_pp0_iter3_reg <= data_10_V_read11_reg_4832_pp0_iter2_reg; + data_10_V_read11_reg_4832_pp0_iter4_reg <= data_10_V_read11_reg_4832_pp0_iter3_reg; + data_11_V_read12_reg_4808 <= data_11_V_read_int_reg; + data_11_V_read12_reg_4808_pp0_iter1_reg <= data_11_V_read12_reg_4808; + data_11_V_read12_reg_4808_pp0_iter2_reg <= data_11_V_read12_reg_4808_pp0_iter1_reg; + data_11_V_read12_reg_4808_pp0_iter3_reg <= data_11_V_read12_reg_4808_pp0_iter2_reg; + data_11_V_read12_reg_4808_pp0_iter4_reg <= data_11_V_read12_reg_4808_pp0_iter3_reg; + data_12_V_read13_reg_4778 <= data_12_V_read_int_reg; + data_12_V_read13_reg_4778_pp0_iter1_reg <= data_12_V_read13_reg_4778; + data_12_V_read13_reg_4778_pp0_iter2_reg <= data_12_V_read13_reg_4778_pp0_iter1_reg; + data_12_V_read13_reg_4778_pp0_iter3_reg <= data_12_V_read13_reg_4778_pp0_iter2_reg; + data_12_V_read13_reg_4778_pp0_iter4_reg <= data_12_V_read13_reg_4778_pp0_iter3_reg; + data_13_V_read14_reg_4745 <= data_13_V_read_int_reg; + data_13_V_read14_reg_4745_pp0_iter1_reg <= data_13_V_read14_reg_4745; + data_13_V_read14_reg_4745_pp0_iter2_reg <= data_13_V_read14_reg_4745_pp0_iter1_reg; + data_13_V_read14_reg_4745_pp0_iter3_reg <= data_13_V_read14_reg_4745_pp0_iter2_reg; + data_13_V_read14_reg_4745_pp0_iter4_reg <= data_13_V_read14_reg_4745_pp0_iter3_reg; + data_13_V_read14_reg_4745_pp0_iter5_reg <= data_13_V_read14_reg_4745_pp0_iter4_reg; + data_14_V_read15_reg_4714 <= data_14_V_read_int_reg; + data_14_V_read15_reg_4714_pp0_iter1_reg <= data_14_V_read15_reg_4714; + data_14_V_read15_reg_4714_pp0_iter2_reg <= data_14_V_read15_reg_4714_pp0_iter1_reg; + data_14_V_read15_reg_4714_pp0_iter3_reg <= data_14_V_read15_reg_4714_pp0_iter2_reg; + data_14_V_read15_reg_4714_pp0_iter4_reg <= data_14_V_read15_reg_4714_pp0_iter3_reg; + data_14_V_read15_reg_4714_pp0_iter5_reg <= data_14_V_read15_reg_4714_pp0_iter4_reg; + data_15_V_read16_reg_4682 <= data_15_V_read_int_reg; + data_15_V_read16_reg_4682_pp0_iter1_reg <= data_15_V_read16_reg_4682; + data_15_V_read16_reg_4682_pp0_iter2_reg <= data_15_V_read16_reg_4682_pp0_iter1_reg; + data_15_V_read16_reg_4682_pp0_iter3_reg <= data_15_V_read16_reg_4682_pp0_iter2_reg; + data_15_V_read16_reg_4682_pp0_iter4_reg <= data_15_V_read16_reg_4682_pp0_iter3_reg; + data_15_V_read16_reg_4682_pp0_iter5_reg <= data_15_V_read16_reg_4682_pp0_iter4_reg; + data_16_V_read17_reg_4650 <= data_16_V_read_int_reg; + data_16_V_read17_reg_4650_pp0_iter1_reg <= data_16_V_read17_reg_4650; + data_16_V_read17_reg_4650_pp0_iter2_reg <= data_16_V_read17_reg_4650_pp0_iter1_reg; + data_16_V_read17_reg_4650_pp0_iter3_reg <= data_16_V_read17_reg_4650_pp0_iter2_reg; + data_16_V_read17_reg_4650_pp0_iter4_reg <= data_16_V_read17_reg_4650_pp0_iter3_reg; + data_16_V_read17_reg_4650_pp0_iter5_reg <= data_16_V_read17_reg_4650_pp0_iter4_reg; + data_17_V_read_8_reg_4621 <= data_17_V_read_int_reg; + data_17_V_read_8_reg_4621_pp0_iter1_reg <= data_17_V_read_8_reg_4621; + data_17_V_read_8_reg_4621_pp0_iter2_reg <= data_17_V_read_8_reg_4621_pp0_iter1_reg; + data_17_V_read_8_reg_4621_pp0_iter3_reg <= data_17_V_read_8_reg_4621_pp0_iter2_reg; + data_17_V_read_8_reg_4621_pp0_iter4_reg <= data_17_V_read_8_reg_4621_pp0_iter3_reg; + data_17_V_read_8_reg_4621_pp0_iter5_reg <= data_17_V_read_8_reg_4621_pp0_iter4_reg; + data_17_V_read_8_reg_4621_pp0_iter6_reg <= data_17_V_read_8_reg_4621_pp0_iter5_reg; + data_18_V_read_7_reg_4594 <= data_18_V_read_int_reg; + data_18_V_read_7_reg_4594_pp0_iter1_reg <= data_18_V_read_7_reg_4594; + data_18_V_read_7_reg_4594_pp0_iter2_reg <= data_18_V_read_7_reg_4594_pp0_iter1_reg; + data_18_V_read_7_reg_4594_pp0_iter3_reg <= data_18_V_read_7_reg_4594_pp0_iter2_reg; + data_18_V_read_7_reg_4594_pp0_iter4_reg <= data_18_V_read_7_reg_4594_pp0_iter3_reg; + data_18_V_read_7_reg_4594_pp0_iter5_reg <= data_18_V_read_7_reg_4594_pp0_iter4_reg; + data_18_V_read_7_reg_4594_pp0_iter6_reg <= data_18_V_read_7_reg_4594_pp0_iter5_reg; + data_19_V_read_7_reg_4567 <= data_19_V_read_int_reg; + data_19_V_read_7_reg_4567_pp0_iter1_reg <= data_19_V_read_7_reg_4567; + data_19_V_read_7_reg_4567_pp0_iter2_reg <= data_19_V_read_7_reg_4567_pp0_iter1_reg; + data_19_V_read_7_reg_4567_pp0_iter3_reg <= data_19_V_read_7_reg_4567_pp0_iter2_reg; + data_19_V_read_7_reg_4567_pp0_iter4_reg <= data_19_V_read_7_reg_4567_pp0_iter3_reg; + data_19_V_read_7_reg_4567_pp0_iter5_reg <= data_19_V_read_7_reg_4567_pp0_iter4_reg; + data_19_V_read_7_reg_4567_pp0_iter6_reg <= data_19_V_read_7_reg_4567_pp0_iter5_reg; + data_20_V_read21_reg_4539 <= data_20_V_read_int_reg; + data_20_V_read21_reg_4539_pp0_iter1_reg <= data_20_V_read21_reg_4539; + data_20_V_read21_reg_4539_pp0_iter2_reg <= data_20_V_read21_reg_4539_pp0_iter1_reg; + data_20_V_read21_reg_4539_pp0_iter3_reg <= data_20_V_read21_reg_4539_pp0_iter2_reg; + data_20_V_read21_reg_4539_pp0_iter4_reg <= data_20_V_read21_reg_4539_pp0_iter3_reg; + data_20_V_read21_reg_4539_pp0_iter5_reg <= data_20_V_read21_reg_4539_pp0_iter4_reg; + data_20_V_read21_reg_4539_pp0_iter6_reg <= data_20_V_read21_reg_4539_pp0_iter5_reg; + data_21_V_read22_reg_4512 <= data_21_V_read_int_reg; + data_21_V_read22_reg_4512_pp0_iter1_reg <= data_21_V_read22_reg_4512; + data_21_V_read22_reg_4512_pp0_iter2_reg <= data_21_V_read22_reg_4512_pp0_iter1_reg; + data_21_V_read22_reg_4512_pp0_iter3_reg <= data_21_V_read22_reg_4512_pp0_iter2_reg; + data_21_V_read22_reg_4512_pp0_iter4_reg <= data_21_V_read22_reg_4512_pp0_iter3_reg; + data_21_V_read22_reg_4512_pp0_iter5_reg <= data_21_V_read22_reg_4512_pp0_iter4_reg; + data_21_V_read22_reg_4512_pp0_iter6_reg <= data_21_V_read22_reg_4512_pp0_iter5_reg; + data_22_V_read23_reg_4483 <= data_22_V_read_int_reg; + data_22_V_read23_reg_4483_pp0_iter1_reg <= data_22_V_read23_reg_4483; + data_22_V_read23_reg_4483_pp0_iter2_reg <= data_22_V_read23_reg_4483_pp0_iter1_reg; + data_22_V_read23_reg_4483_pp0_iter3_reg <= data_22_V_read23_reg_4483_pp0_iter2_reg; + data_22_V_read23_reg_4483_pp0_iter4_reg <= data_22_V_read23_reg_4483_pp0_iter3_reg; + data_22_V_read23_reg_4483_pp0_iter5_reg <= data_22_V_read23_reg_4483_pp0_iter4_reg; + data_22_V_read23_reg_4483_pp0_iter6_reg <= data_22_V_read23_reg_4483_pp0_iter5_reg; + data_22_V_read23_reg_4483_pp0_iter7_reg <= data_22_V_read23_reg_4483_pp0_iter6_reg; + data_23_V_read24_reg_4451 <= data_23_V_read_int_reg; + data_23_V_read24_reg_4451_pp0_iter1_reg <= data_23_V_read24_reg_4451; + data_23_V_read24_reg_4451_pp0_iter2_reg <= data_23_V_read24_reg_4451_pp0_iter1_reg; + data_23_V_read24_reg_4451_pp0_iter3_reg <= data_23_V_read24_reg_4451_pp0_iter2_reg; + data_23_V_read24_reg_4451_pp0_iter4_reg <= data_23_V_read24_reg_4451_pp0_iter3_reg; + data_23_V_read24_reg_4451_pp0_iter5_reg <= data_23_V_read24_reg_4451_pp0_iter4_reg; + data_23_V_read24_reg_4451_pp0_iter6_reg <= data_23_V_read24_reg_4451_pp0_iter5_reg; + data_23_V_read24_reg_4451_pp0_iter7_reg <= data_23_V_read24_reg_4451_pp0_iter6_reg; + data_24_V_read25_reg_4421 <= data_24_V_read_int_reg; + data_24_V_read25_reg_4421_pp0_iter1_reg <= data_24_V_read25_reg_4421; + data_24_V_read25_reg_4421_pp0_iter2_reg <= data_24_V_read25_reg_4421_pp0_iter1_reg; + data_24_V_read25_reg_4421_pp0_iter3_reg <= data_24_V_read25_reg_4421_pp0_iter2_reg; + data_24_V_read25_reg_4421_pp0_iter4_reg <= data_24_V_read25_reg_4421_pp0_iter3_reg; + data_24_V_read25_reg_4421_pp0_iter5_reg <= data_24_V_read25_reg_4421_pp0_iter4_reg; + data_24_V_read25_reg_4421_pp0_iter6_reg <= data_24_V_read25_reg_4421_pp0_iter5_reg; + data_24_V_read25_reg_4421_pp0_iter7_reg <= data_24_V_read25_reg_4421_pp0_iter6_reg; + data_25_V_read26_reg_4391 <= data_25_V_read_int_reg; + data_25_V_read26_reg_4391_pp0_iter1_reg <= data_25_V_read26_reg_4391; + data_25_V_read26_reg_4391_pp0_iter2_reg <= data_25_V_read26_reg_4391_pp0_iter1_reg; + data_25_V_read26_reg_4391_pp0_iter3_reg <= data_25_V_read26_reg_4391_pp0_iter2_reg; + data_25_V_read26_reg_4391_pp0_iter4_reg <= data_25_V_read26_reg_4391_pp0_iter3_reg; + data_25_V_read26_reg_4391_pp0_iter5_reg <= data_25_V_read26_reg_4391_pp0_iter4_reg; + data_25_V_read26_reg_4391_pp0_iter6_reg <= data_25_V_read26_reg_4391_pp0_iter5_reg; + data_25_V_read26_reg_4391_pp0_iter7_reg <= data_25_V_read26_reg_4391_pp0_iter6_reg; + data_26_V_read27_reg_4365 <= data_26_V_read_int_reg; + data_26_V_read27_reg_4365_pp0_iter1_reg <= data_26_V_read27_reg_4365; + data_26_V_read27_reg_4365_pp0_iter2_reg <= data_26_V_read27_reg_4365_pp0_iter1_reg; + data_26_V_read27_reg_4365_pp0_iter3_reg <= data_26_V_read27_reg_4365_pp0_iter2_reg; + data_26_V_read27_reg_4365_pp0_iter4_reg <= data_26_V_read27_reg_4365_pp0_iter3_reg; + data_26_V_read27_reg_4365_pp0_iter5_reg <= data_26_V_read27_reg_4365_pp0_iter4_reg; + data_26_V_read27_reg_4365_pp0_iter6_reg <= data_26_V_read27_reg_4365_pp0_iter5_reg; + data_26_V_read27_reg_4365_pp0_iter7_reg <= data_26_V_read27_reg_4365_pp0_iter6_reg; + data_27_V_read_8_reg_4342 <= data_27_V_read_int_reg; + data_27_V_read_8_reg_4342_pp0_iter1_reg <= data_27_V_read_8_reg_4342; + data_27_V_read_8_reg_4342_pp0_iter2_reg <= data_27_V_read_8_reg_4342_pp0_iter1_reg; + data_27_V_read_8_reg_4342_pp0_iter3_reg <= data_27_V_read_8_reg_4342_pp0_iter2_reg; + data_27_V_read_8_reg_4342_pp0_iter4_reg <= data_27_V_read_8_reg_4342_pp0_iter3_reg; + data_27_V_read_8_reg_4342_pp0_iter5_reg <= data_27_V_read_8_reg_4342_pp0_iter4_reg; + data_27_V_read_8_reg_4342_pp0_iter6_reg <= data_27_V_read_8_reg_4342_pp0_iter5_reg; + data_27_V_read_8_reg_4342_pp0_iter7_reg <= data_27_V_read_8_reg_4342_pp0_iter6_reg; + data_28_V_read_7_reg_4313 <= data_28_V_read_int_reg; + data_28_V_read_7_reg_4313_pp0_iter1_reg <= data_28_V_read_7_reg_4313; + data_28_V_read_7_reg_4313_pp0_iter2_reg <= data_28_V_read_7_reg_4313_pp0_iter1_reg; + data_28_V_read_7_reg_4313_pp0_iter3_reg <= data_28_V_read_7_reg_4313_pp0_iter2_reg; + data_28_V_read_7_reg_4313_pp0_iter4_reg <= data_28_V_read_7_reg_4313_pp0_iter3_reg; + data_28_V_read_7_reg_4313_pp0_iter5_reg <= data_28_V_read_7_reg_4313_pp0_iter4_reg; + data_28_V_read_7_reg_4313_pp0_iter6_reg <= data_28_V_read_7_reg_4313_pp0_iter5_reg; + data_28_V_read_7_reg_4313_pp0_iter7_reg <= data_28_V_read_7_reg_4313_pp0_iter6_reg; + data_28_V_read_7_reg_4313_pp0_iter8_reg <= data_28_V_read_7_reg_4313_pp0_iter7_reg; + data_29_V_read_7_reg_4279 <= data_29_V_read_int_reg; + data_29_V_read_7_reg_4279_pp0_iter1_reg <= data_29_V_read_7_reg_4279; + data_29_V_read_7_reg_4279_pp0_iter2_reg <= data_29_V_read_7_reg_4279_pp0_iter1_reg; + data_29_V_read_7_reg_4279_pp0_iter3_reg <= data_29_V_read_7_reg_4279_pp0_iter2_reg; + data_29_V_read_7_reg_4279_pp0_iter4_reg <= data_29_V_read_7_reg_4279_pp0_iter3_reg; + data_29_V_read_7_reg_4279_pp0_iter5_reg <= data_29_V_read_7_reg_4279_pp0_iter4_reg; + data_29_V_read_7_reg_4279_pp0_iter6_reg <= data_29_V_read_7_reg_4279_pp0_iter5_reg; + data_29_V_read_7_reg_4279_pp0_iter7_reg <= data_29_V_read_7_reg_4279_pp0_iter6_reg; + data_29_V_read_7_reg_4279_pp0_iter8_reg <= data_29_V_read_7_reg_4279_pp0_iter7_reg; + data_2_V_read_9_reg_5035 <= data_2_V_read_int_reg; + data_30_V_read31_reg_4250 <= data_30_V_read_int_reg; + data_30_V_read31_reg_4250_pp0_iter1_reg <= data_30_V_read31_reg_4250; + data_30_V_read31_reg_4250_pp0_iter2_reg <= data_30_V_read31_reg_4250_pp0_iter1_reg; + data_30_V_read31_reg_4250_pp0_iter3_reg <= data_30_V_read31_reg_4250_pp0_iter2_reg; + data_30_V_read31_reg_4250_pp0_iter4_reg <= data_30_V_read31_reg_4250_pp0_iter3_reg; + data_30_V_read31_reg_4250_pp0_iter5_reg <= data_30_V_read31_reg_4250_pp0_iter4_reg; + data_30_V_read31_reg_4250_pp0_iter6_reg <= data_30_V_read31_reg_4250_pp0_iter5_reg; + data_30_V_read31_reg_4250_pp0_iter7_reg <= data_30_V_read31_reg_4250_pp0_iter6_reg; + data_30_V_read31_reg_4250_pp0_iter8_reg <= data_30_V_read31_reg_4250_pp0_iter7_reg; + data_31_V_read32_reg_4221 <= data_31_V_read_int_reg; + data_31_V_read32_reg_4221_pp0_iter1_reg <= data_31_V_read32_reg_4221; + data_31_V_read32_reg_4221_pp0_iter2_reg <= data_31_V_read32_reg_4221_pp0_iter1_reg; + data_31_V_read32_reg_4221_pp0_iter3_reg <= data_31_V_read32_reg_4221_pp0_iter2_reg; + data_31_V_read32_reg_4221_pp0_iter4_reg <= data_31_V_read32_reg_4221_pp0_iter3_reg; + data_31_V_read32_reg_4221_pp0_iter5_reg <= data_31_V_read32_reg_4221_pp0_iter4_reg; + data_31_V_read32_reg_4221_pp0_iter6_reg <= data_31_V_read32_reg_4221_pp0_iter5_reg; + data_31_V_read32_reg_4221_pp0_iter7_reg <= data_31_V_read32_reg_4221_pp0_iter6_reg; + data_31_V_read32_reg_4221_pp0_iter8_reg <= data_31_V_read32_reg_4221_pp0_iter7_reg; + data_3_V_read_9_reg_5019 <= data_3_V_read_int_reg; + data_3_V_read_9_reg_5019_pp0_iter1_reg <= data_3_V_read_9_reg_5019; + data_3_V_read_9_reg_5019_pp0_iter2_reg <= data_3_V_read_9_reg_5019_pp0_iter1_reg; + data_4_V_read_9_reg_4998 <= data_4_V_read_int_reg; + data_4_V_read_9_reg_4998_pp0_iter1_reg <= data_4_V_read_9_reg_4998; + data_4_V_read_9_reg_4998_pp0_iter2_reg <= data_4_V_read_9_reg_4998_pp0_iter1_reg; + data_5_V_read_8_reg_4969 <= data_5_V_read_int_reg; + data_5_V_read_8_reg_4969_pp0_iter1_reg <= data_5_V_read_8_reg_4969; + data_5_V_read_8_reg_4969_pp0_iter2_reg <= data_5_V_read_8_reg_4969_pp0_iter1_reg; + data_5_V_read_8_reg_4969_pp0_iter3_reg <= data_5_V_read_8_reg_4969_pp0_iter2_reg; + data_6_V_read_8_reg_4944 <= data_6_V_read_int_reg; + data_6_V_read_8_reg_4944_pp0_iter1_reg <= data_6_V_read_8_reg_4944; + data_6_V_read_8_reg_4944_pp0_iter2_reg <= data_6_V_read_8_reg_4944_pp0_iter1_reg; + data_6_V_read_8_reg_4944_pp0_iter3_reg <= data_6_V_read_8_reg_4944_pp0_iter2_reg; + data_7_V_read_8_reg_4916 <= data_7_V_read_int_reg; + data_7_V_read_8_reg_4916_pp0_iter1_reg <= data_7_V_read_8_reg_4916; + data_7_V_read_8_reg_4916_pp0_iter2_reg <= data_7_V_read_8_reg_4916_pp0_iter1_reg; + data_7_V_read_8_reg_4916_pp0_iter3_reg <= data_7_V_read_8_reg_4916_pp0_iter2_reg; + data_8_V_read_7_reg_4887 <= data_8_V_read_int_reg; + data_8_V_read_7_reg_4887_pp0_iter1_reg <= data_8_V_read_7_reg_4887; + data_8_V_read_7_reg_4887_pp0_iter2_reg <= data_8_V_read_7_reg_4887_pp0_iter1_reg; + data_8_V_read_7_reg_4887_pp0_iter3_reg <= data_8_V_read_7_reg_4887_pp0_iter2_reg; + data_9_V_read_7_reg_4859 <= data_9_V_read_int_reg; + data_9_V_read_7_reg_4859_pp0_iter1_reg <= data_9_V_read_7_reg_4859; + data_9_V_read_7_reg_4859_pp0_iter2_reg <= data_9_V_read_7_reg_4859_pp0_iter1_reg; + data_9_V_read_7_reg_4859_pp0_iter3_reg <= data_9_V_read_7_reg_4859_pp0_iter2_reg; + data_9_V_read_7_reg_4859_pp0_iter4_reg <= data_9_V_read_7_reg_4859_pp0_iter3_reg; + sub_ln703_105_reg_5226 <= sub_ln703_105_fu_489_p2; + sub_ln703_113_reg_5247 <= sub_ln703_113_fu_533_p2; + sub_ln703_114_reg_5253 <= sub_ln703_114_fu_549_p2; + sub_ln703_117_reg_5259 <= sub_ln703_117_fu_554_p2; + sub_ln703_126_reg_5274 <= sub_ln703_126_fu_574_p2; + sub_ln703_129_reg_5279 <= sub_ln703_129_fu_579_p2; + sub_ln703_133_reg_5284 <= sub_ln703_133_fu_584_p2; + sub_ln703_138_reg_5325 <= sub_ln703_138_fu_816_p2; + sub_ln703_141_reg_5330 <= sub_ln703_141_fu_835_p2; + sub_ln703_143_reg_5335 <= sub_ln703_143_fu_844_p2; + sub_ln703_144_reg_5340 <= sub_ln703_144_fu_858_p2; + sub_ln703_145_reg_5345 <= sub_ln703_145_fu_863_p2; + sub_ln703_149_reg_5350 <= sub_ln703_149_fu_901_p2; + sub_ln703_154_reg_5355 <= sub_ln703_154_fu_920_p2; + sub_ln703_161_reg_5365 <= sub_ln703_161_fu_960_p2; + sub_ln703_162_reg_5370 <= sub_ln703_162_fu_980_p2; + sub_ln703_166_reg_5375 <= sub_ln703_166_fu_1000_p2; + sub_ln703_171_reg_5380 <= sub_ln703_171_fu_1015_p2; + sub_ln703_173_reg_5385 <= sub_ln703_173_fu_1025_p2; + sub_ln703_176_reg_5390 <= sub_ln703_176_fu_1040_p2; + sub_ln703_180_reg_5395 <= sub_ln703_180_fu_1045_p2; + sub_ln703_181_reg_5400 <= sub_ln703_181_fu_1050_p2; + sub_ln703_182_reg_5410 <= sub_ln703_182_fu_1060_p2; + sub_ln703_185_reg_5425 <= sub_ln703_185_fu_1095_p2; + sub_ln703_187_reg_5440 <= sub_ln703_187_fu_1110_p2; + sub_ln703_189_reg_5445 <= sub_ln703_189_fu_1115_p2; + sub_ln703_191_reg_5450 <= sub_ln703_191_fu_1120_p2; + sub_ln703_198_reg_5465 <= sub_ln703_198_fu_1146_p2; + sub_ln703_199_reg_5470 <= sub_ln703_199_fu_1151_p2; + sub_ln703_200_reg_5515 <= sub_ln703_200_fu_1326_p2; + sub_ln703_203_reg_5520 <= sub_ln703_203_fu_1339_p2; + sub_ln703_207_reg_5535 <= sub_ln703_207_fu_1384_p2; + sub_ln703_212_reg_5540 <= sub_ln703_212_fu_1412_p2; + sub_ln703_215_reg_5545 <= sub_ln703_215_fu_1441_p2; + sub_ln703_229_reg_5560 <= sub_ln703_229_fu_1518_p2; + sub_ln703_237_reg_5565 <= sub_ln703_237_fu_1571_p2; + sub_ln703_238_reg_5570 <= sub_ln703_238_fu_1576_p2; + sub_ln703_246_reg_5501 <= sub_ln703_246_fu_1193_p2; + sub_ln703_252_reg_5575 <= sub_ln703_252_fu_1616_p2; + sub_ln703_253_reg_5580 <= sub_ln703_253_fu_1621_p2; + sub_ln703_254_reg_5585 <= sub_ln703_254_fu_1626_p2; + sub_ln703_257_reg_5595 <= sub_ln703_257_fu_1641_p2; + sub_ln703_261_reg_5600 <= sub_ln703_261_fu_1646_p2; + sub_ln703_262_reg_5605 <= sub_ln703_262_fu_1651_p2; + sub_ln703_263_reg_5610 <= sub_ln703_263_fu_1671_p2; + sub_ln703_265_reg_5615 <= sub_ln703_265_fu_1676_p2; + sub_ln703_266_reg_5620 <= sub_ln703_266_fu_1681_p2; + sub_ln703_270_reg_5630 <= sub_ln703_270_fu_1695_p2; + sub_ln703_272_reg_5635 <= sub_ln703_272_fu_1700_p2; + sub_ln703_276_reg_5728 <= sub_ln703_276_fu_1918_p2; + sub_ln703_278_reg_5650 <= sub_ln703_278_fu_1735_p2; + sub_ln703_283_reg_5733 <= sub_ln703_283_fu_1975_p2; + sub_ln703_288_reg_5738 <= sub_ln703_288_fu_2003_p2; + sub_ln703_289_reg_5665 <= sub_ln703_289_fu_1750_p2; + sub_ln703_290_reg_5670 <= sub_ln703_290_fu_1755_p2; + sub_ln703_300_reg_5748 <= sub_ln703_300_fu_2075_p2; + sub_ln703_302_reg_5758 <= sub_ln703_302_fu_2089_p2; + sub_ln703_304_reg_5763 <= sub_ln703_304_fu_2099_p2; + sub_ln703_309_reg_5773 <= sub_ln703_309_fu_2148_p2; + sub_ln703_311_reg_5778 <= sub_ln703_311_fu_2173_p2; + sub_ln703_318_reg_5783 <= sub_ln703_318_fu_2203_p2; + sub_ln703_321_reg_5788 <= sub_ln703_321_fu_2218_p2; + sub_ln703_323_reg_5798 <= sub_ln703_323_fu_2233_p2; + sub_ln703_324_reg_5803 <= sub_ln703_324_fu_2238_p2; + sub_ln703_325_reg_5808 <= sub_ln703_325_fu_2243_p2; + sub_ln703_327_reg_5813 <= sub_ln703_327_fu_2248_p2; + sub_ln703_328_reg_5818 <= sub_ln703_328_fu_2253_p2; + sub_ln703_331_reg_5823 <= sub_ln703_331_fu_2258_p2; + sub_ln703_332_reg_5828 <= sub_ln703_332_fu_2273_p2; + sub_ln703_335_reg_5843 <= sub_ln703_335_fu_2302_p2; + sub_ln703_343_reg_5853 <= sub_ln703_343_fu_2312_p2; + sub_ln703_346_reg_5863 <= sub_ln703_346_fu_2332_p2; + sub_ln703_356_reg_5921 <= sub_ln703_356_fu_2603_p2; + sub_ln703_357_reg_5926 <= sub_ln703_357_fu_2608_p2; + sub_ln703_361_reg_5936 <= sub_ln703_361_fu_2636_p2; + sub_ln703_366_reg_5941 <= sub_ln703_366_fu_2684_p2; + sub_ln703_369_reg_5946 <= sub_ln703_369_fu_2699_p2; + sub_ln703_374_reg_5956 <= sub_ln703_374_fu_2728_p2; + sub_ln703_375_reg_5966 <= sub_ln703_375_fu_2747_p2; + sub_ln703_379_reg_5971 <= sub_ln703_379_fu_2781_p2; + sub_ln703_381_reg_5976 <= sub_ln703_381_fu_2791_p2; + sub_ln703_385_reg_5986 <= sub_ln703_385_fu_2811_p2; + sub_ln703_386_reg_5991 <= sub_ln703_386_fu_2816_p2; + sub_ln703_389_reg_5996 <= sub_ln703_389_fu_2839_p2; + sub_ln703_392_reg_6001 <= sub_ln703_392_fu_2848_p2; + sub_ln703_397_reg_6006 <= sub_ln703_397_fu_2863_p2; + sub_ln703_402_reg_6016 <= sub_ln703_402_fu_2878_p2; + sub_ln703_408_reg_6026 <= sub_ln703_408_fu_2893_p2; + sub_ln703_409_reg_6031 <= sub_ln703_409_fu_2898_p2; + sub_ln703_411_reg_6036 <= sub_ln703_411_fu_2903_p2; + sub_ln703_416_reg_6046 <= sub_ln703_416_fu_2923_p2; + sub_ln703_426_reg_6061 <= sub_ln703_426_fu_2938_p2; + sub_ln703_428_reg_6108 <= sub_ln703_428_fu_3163_p2; + sub_ln703_434_reg_6113 <= sub_ln703_434_fu_3199_p2; + sub_ln703_448_reg_6118 <= sub_ln703_448_fu_3308_p2; + sub_ln703_450_reg_6123 <= sub_ln703_450_fu_3318_p2; + sub_ln703_451_reg_6143 <= sub_ln703_451_fu_3343_p2; + sub_ln703_452_reg_6148 <= sub_ln703_452_fu_3348_p2; + sub_ln703_453_reg_6153 <= sub_ln703_453_fu_3353_p2; + sub_ln703_454_reg_6163 <= sub_ln703_454_fu_3368_p2; + sub_ln703_455_reg_6168 <= sub_ln703_455_fu_3373_p2; + sub_ln703_456_reg_6178 <= sub_ln703_456_fu_3388_p2; + sub_ln703_457_reg_6183 <= sub_ln703_457_fu_3393_p2; + sub_ln703_458_reg_6193 <= sub_ln703_458_fu_3408_p2; + sub_ln703_459_reg_6198 <= sub_ln703_459_fu_3418_p2; + sub_ln703_461_reg_6208 <= sub_ln703_461_fu_3438_p2; + sub_ln703_469_reg_6218 <= sub_ln703_469_fu_3463_p2; + sub_ln703_474_reg_6229 <= sub_ln703_474_fu_3482_p2; + sub_ln703_486_reg_6244 <= sub_ln703_486_fu_3507_p2; + sub_ln703_487_reg_6249 <= sub_ln703_487_fu_3512_p2; + sub_ln703_491_reg_6254 <= sub_ln703_491_fu_3517_p2; + sub_ln703_500_reg_6259 <= sub_ln703_500_fu_3522_p2; + sub_ln703_73_reg_5059 <= sub_ln703_73_fu_286_p2; + sub_ln703_74_reg_5065 <= sub_ln703_74_fu_292_p2; + sub_ln703_74_reg_5065_pp0_iter2_reg <= sub_ln703_74_reg_5065; + sub_ln703_76_reg_5071 <= sub_ln703_76_fu_300_p2; + sub_ln703_76_reg_5071_pp0_iter2_reg <= sub_ln703_76_reg_5071; + sub_ln703_77_reg_5084 <= sub_ln703_77_fu_308_p2; + sub_ln703_79_reg_5125 <= sub_ln703_79_fu_337_p2; + sub_ln703_89_reg_5166 <= sub_ln703_89_fu_402_p2; + sub_ln703_91_reg_5172 <= sub_ln703_91_fu_411_p2; + sub_ln703_93_reg_5200 <= sub_ln703_93_fu_442_p2; + sub_ln703_94_reg_5205 <= sub_ln703_94_fu_446_p2; + sub_ln703_96_reg_5210 <= sub_ln703_96_fu_456_p2; + sub_ln703_reg_5046 <= sub_ln703_fu_274_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce_reg)) begin + ap_return_0_int_reg <= add_ln703_511_fu_3847_p2; + ap_return_10_int_reg <= acc_10_V_fu_3910_p2; + ap_return_11_int_reg <= acc_11_V_fu_3915_p2; + ap_return_12_int_reg <= acc_12_V_fu_3920_p2; + ap_return_13_int_reg <= acc_13_V_fu_3925_p2; + ap_return_14_int_reg <= acc_14_V_fu_3930_p2; + ap_return_15_int_reg <= acc_15_V_fu_3935_p2; + ap_return_16_int_reg <= acc_16_V_fu_3940_p2; + ap_return_17_int_reg <= acc_17_V_fu_3953_p2; + ap_return_18_int_reg <= acc_18_V_fu_3959_p2; + ap_return_19_int_reg <= acc_19_V_fu_3964_p2; + ap_return_1_int_reg <= acc_1_V_fu_3852_p2; + ap_return_20_int_reg <= acc_20_V_fu_3969_p2; + ap_return_21_int_reg <= acc_21_V_fu_3974_p2; + ap_return_22_int_reg <= acc_22_V_fu_3979_p2; + ap_return_23_int_reg <= acc_23_V_fu_3984_p2; + ap_return_24_int_reg <= acc_24_V_fu_3989_p2; + ap_return_25_int_reg <= acc_25_V_fu_3994_p2; + ap_return_26_int_reg <= acc_26_V_fu_3999_p2; + ap_return_27_int_reg <= acc_27_V_fu_4004_p2; + ap_return_28_int_reg <= acc_28_V_fu_4009_p2; + ap_return_29_int_reg <= acc_29_V_fu_4014_p2; + ap_return_2_int_reg <= acc_2_V_fu_3857_p2; + ap_return_30_int_reg <= acc_30_V_fu_4019_p2; + ap_return_31_int_reg <= acc_31_V_fu_4024_p2; + ap_return_3_int_reg <= acc_3_V_fu_3866_p2; + ap_return_4_int_reg <= acc_4_V_fu_3879_p2; + ap_return_5_int_reg <= acc_5_V_fu_3885_p2; + ap_return_6_int_reg <= acc_6_V_fu_3890_p2; + ap_return_7_int_reg <= acc_7_V_fu_3895_p2; + ap_return_8_int_reg <= acc_8_V_fu_3900_p2; + ap_return_9_int_reg <= acc_9_V_fu_3905_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce)) begin + data_0_V_read_int_reg <= data_0_V_read; + data_10_V_read_int_reg <= data_10_V_read; + data_11_V_read_int_reg <= data_11_V_read; + data_12_V_read_int_reg <= data_12_V_read; + data_13_V_read_int_reg <= data_13_V_read; + data_14_V_read_int_reg <= data_14_V_read; + data_15_V_read_int_reg <= data_15_V_read; + data_16_V_read_int_reg <= data_16_V_read; + data_17_V_read_int_reg <= data_17_V_read; + data_18_V_read_int_reg <= data_18_V_read; + data_19_V_read_int_reg <= data_19_V_read; + data_1_V_read_int_reg <= data_1_V_read; + data_20_V_read_int_reg <= data_20_V_read; + data_21_V_read_int_reg <= data_21_V_read; + data_22_V_read_int_reg <= data_22_V_read; + data_23_V_read_int_reg <= data_23_V_read; + data_24_V_read_int_reg <= data_24_V_read; + data_25_V_read_int_reg <= data_25_V_read; + data_26_V_read_int_reg <= data_26_V_read; + data_27_V_read_int_reg <= data_27_V_read; + data_28_V_read_int_reg <= data_28_V_read; + data_29_V_read_int_reg <= data_29_V_read; + data_2_V_read_int_reg <= data_2_V_read; + data_30_V_read_int_reg <= data_30_V_read; + data_31_V_read_int_reg <= data_31_V_read; + data_3_V_read_int_reg <= data_3_V_read; + data_4_V_read_int_reg <= data_4_V_read; + data_5_V_read_int_reg <= data_5_V_read; + data_6_V_read_int_reg <= data_6_V_read; + data_7_V_read_int_reg <= data_7_V_read; + data_8_V_read_int_reg <= data_8_V_read; + data_9_V_read_int_reg <= data_9_V_read; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_0 = ap_return_0_int_reg; + end else begin + ap_return_0 = add_ln703_511_fu_3847_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_1 = ap_return_1_int_reg; + end else begin + ap_return_1 = acc_1_V_fu_3852_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_10 = ap_return_10_int_reg; + end else begin + ap_return_10 = acc_10_V_fu_3910_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_11 = ap_return_11_int_reg; + end else begin + ap_return_11 = acc_11_V_fu_3915_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_12 = ap_return_12_int_reg; + end else begin + ap_return_12 = acc_12_V_fu_3920_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_13 = ap_return_13_int_reg; + end else begin + ap_return_13 = acc_13_V_fu_3925_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_14 = ap_return_14_int_reg; + end else begin + ap_return_14 = acc_14_V_fu_3930_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_15 = ap_return_15_int_reg; + end else begin + ap_return_15 = acc_15_V_fu_3935_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_16 = ap_return_16_int_reg; + end else begin + ap_return_16 = acc_16_V_fu_3940_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_17 = ap_return_17_int_reg; + end else begin + ap_return_17 = acc_17_V_fu_3953_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_18 = ap_return_18_int_reg; + end else begin + ap_return_18 = acc_18_V_fu_3959_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_19 = ap_return_19_int_reg; + end else begin + ap_return_19 = acc_19_V_fu_3964_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_2 = ap_return_2_int_reg; + end else begin + ap_return_2 = acc_2_V_fu_3857_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_20 = ap_return_20_int_reg; + end else begin + ap_return_20 = acc_20_V_fu_3969_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_21 = ap_return_21_int_reg; + end else begin + ap_return_21 = acc_21_V_fu_3974_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_22 = ap_return_22_int_reg; + end else begin + ap_return_22 = acc_22_V_fu_3979_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_23 = ap_return_23_int_reg; + end else begin + ap_return_23 = acc_23_V_fu_3984_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_24 = ap_return_24_int_reg; + end else begin + ap_return_24 = acc_24_V_fu_3989_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_25 = ap_return_25_int_reg; + end else begin + ap_return_25 = acc_25_V_fu_3994_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_26 = ap_return_26_int_reg; + end else begin + ap_return_26 = acc_26_V_fu_3999_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_27 = ap_return_27_int_reg; + end else begin + ap_return_27 = acc_27_V_fu_4004_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_28 = ap_return_28_int_reg; + end else begin + ap_return_28 = acc_28_V_fu_4009_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_29 = ap_return_29_int_reg; + end else begin + ap_return_29 = acc_29_V_fu_4014_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_3 = ap_return_3_int_reg; + end else begin + ap_return_3 = acc_3_V_fu_3866_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_30 = ap_return_30_int_reg; + end else begin + ap_return_30 = acc_30_V_fu_4019_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_31 = ap_return_31_int_reg; + end else begin + ap_return_31 = acc_31_V_fu_4024_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_4 = ap_return_4_int_reg; + end else begin + ap_return_4 = acc_4_V_fu_3879_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_5 = ap_return_5_int_reg; + end else begin + ap_return_5 = acc_5_V_fu_3885_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_6 = ap_return_6_int_reg; + end else begin + ap_return_6 = acc_6_V_fu_3890_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_7 = ap_return_7_int_reg; + end else begin + ap_return_7 = acc_7_V_fu_3895_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_8 = ap_return_8_int_reg; + end else begin + ap_return_8 = acc_8_V_fu_3900_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_9 = ap_return_9_int_reg; + end else begin + ap_return_9 = acc_9_V_fu_3905_p2; + end +end + +assign acc_10_V_fu_3910_p2 = (add_ln703_503_fu_3757_p2 - data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_11_V_fu_3915_p2 = (sub_ln703_507_fu_3762_p2 - data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_12_V_fu_3920_p2 = (sub_ln703_508_fu_3767_p2 + data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_13_V_fu_3925_p2 = (sub_ln703_509_fu_3772_p2 - data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_14_V_fu_3930_p2 = (add_ln703_504_fu_3777_p2 - data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_15_V_fu_3935_p2 = (sub_ln703_510_fu_3781_p2 + data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_16_V_fu_3940_p2 = (add_ln703_505_fu_3785_p2 - data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_17_V_fu_3953_p2 = (add_ln703_527_fu_3949_p2 + add_ln703_526_fu_3945_p2); + +assign acc_18_V_fu_3959_p2 = (sub_ln703_511_fu_3790_p2 + data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_19_V_fu_3964_p2 = (add_ln703_509_reg_6092_pp0_iter8_reg + sub_ln703_490_fu_3675_p2); + +assign acc_1_V_fu_3852_p2 = (sub_ln703_501_fu_3728_p2 + data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_20_V_fu_3969_p2 = (add_ln703_506_fu_3795_p2 - data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_21_V_fu_3974_p2 = (add_ln703_507_fu_3799_p2 - data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_22_V_fu_3979_p2 = (sub_ln703_512_fu_3804_p2 + data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_23_V_fu_3984_p2 = (sub_ln703_513_fu_3809_p2 + data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_24_V_fu_3989_p2 = (sub_ln703_514_fu_3814_p2 + data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_25_V_fu_3994_p2 = (sub_ln703_515_fu_3819_p2 + data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_26_V_fu_3999_p2 = (add_ln703_509_reg_6092_pp0_iter8_reg + sub_ln703_497_fu_3704_p2); + +assign acc_27_V_fu_4004_p2 = (sub_ln703_516_fu_3824_p2 - data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_28_V_fu_4009_p2 = (sub_ln703_517_fu_3829_p2 + data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_29_V_fu_4014_p2 = (add_ln703_509_reg_6092_pp0_iter8_reg + sub_ln703_498_fu_3718_p2); + +assign acc_2_V_fu_3857_p2 = (sub_ln703_502_fu_3732_p2 + data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_30_V_fu_4019_p2 = (sub_ln703_518_fu_3834_p2 - data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_31_V_fu_4024_p2 = (sub_ln703_519_fu_3839_p2 - data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_3_V_fu_3866_p2 = (add_ln703_509_reg_6092_pp0_iter8_reg + add_ln703_514_fu_3862_p2); + +assign acc_4_V_fu_3879_p2 = (add_ln703_518_fu_3875_p2 + add_ln703_517_fu_3871_p2); + +assign acc_5_V_fu_3885_p2 = (sub_ln703_503_fu_3737_p2 + data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_6_V_fu_3890_p2 = (sub_ln703_504_fu_3742_p2 - data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_7_V_fu_3895_p2 = (sub_ln703_505_fu_3747_p2 + data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign acc_8_V_fu_3900_p2 = (add_ln703_509_reg_6092_pp0_iter8_reg + sub_ln703_481_fu_3636_p2); + +assign acc_9_V_fu_3905_p2 = (sub_ln703_506_fu_3752_p2 + data_31_V_read32_reg_4221_pp0_iter8_reg); + +assign add_ln703_200_fu_304_p2 = (add_ln703_reg_5052 + data_2_V_read_9_reg_5035); + +assign add_ln703_201_fu_312_p2 = (sub_ln703_reg_5046 + data_2_V_read_9_reg_5035); + +assign add_ln703_202_fu_316_p2 = (sub_ln703_73_reg_5059 + data_2_V_read_9_reg_5035); + +assign add_ln703_203_fu_329_p2 = (sub_ln703_74_reg_5065 + data_3_V_read_9_reg_5019_pp0_iter1_reg); + +assign add_ln703_204_fu_320_p2 = (sub_ln703_75_fu_296_p2 + data_3_V_read_9_reg_5019); + +assign add_ln703_205_fu_333_p2 = (add_ln703_200_reg_5077 + data_3_V_read_9_reg_5019_pp0_iter1_reg); + +assign add_ln703_206_fu_341_p2 = (sub_ln703_76_reg_5071 + data_3_V_read_9_reg_5019_pp0_iter1_reg); + +assign add_ln703_207_fu_325_p2 = (data_3_V_read_9_reg_5019 + data_4_V_read_9_reg_4998); + +assign add_ln703_208_fu_345_p2 = (add_ln703_207_reg_5107 + sub_ln703_77_reg_5084); + +assign add_ln703_209_fu_416_p2 = (add_ln703_205_reg_5119 + data_4_V_read_9_reg_4998_pp0_iter2_reg); + +assign add_ln703_210_fu_349_p2 = (add_ln703_204_reg_5101 + data_4_V_read_9_reg_4998_pp0_iter1_reg); + +assign add_ln703_211_fu_420_p2 = (sub_ln703_82_fu_373_p2 + data_4_V_read_9_reg_4998_pp0_iter2_reg); + +assign add_ln703_212_fu_425_p2 = (add_ln703_203_reg_5113 + data_4_V_read_9_reg_4998_pp0_iter2_reg); + +assign add_ln703_213_fu_429_p2 = (add_ln703_207_reg_5107_pp0_iter2_reg + add_ln703_201_reg_5090_pp0_iter2_reg); + +assign add_ln703_214_fu_433_p2 = (add_ln703_206_reg_5131 + data_4_V_read_9_reg_4998_pp0_iter2_reg); + +assign add_ln703_215_fu_605_p2 = (sub_ln703_89_reg_5166 + data_5_V_read_8_reg_4969_pp0_iter3_reg); + +assign add_ln703_216_fu_461_p2 = (sub_ln703_90_fu_406_p2 + data_5_V_read_8_reg_4969_pp0_iter2_reg); + +assign add_ln703_217_fu_470_p2 = (add_ln703_210_reg_5143 + data_5_V_read_8_reg_4969_pp0_iter2_reg); + +assign add_ln703_218_fu_474_p2 = (add_ln703_211_fu_420_p2 + data_5_V_read_8_reg_4969_pp0_iter2_reg); + +assign add_ln703_219_fu_479_p2 = (add_ln703_212_fu_425_p2 + data_5_V_read_8_reg_4969_pp0_iter2_reg); + +assign add_ln703_220_fu_484_p2 = (sub_ln703_87_fu_393_p2 + data_5_V_read_8_reg_4969_pp0_iter2_reg); + +assign add_ln703_221_fu_499_p2 = (add_ln703_208_reg_5137 + data_5_V_read_8_reg_4969_pp0_iter2_reg); + +assign add_ln703_222_fu_503_p2 = (data_5_V_read_8_reg_4969_pp0_iter2_reg + data_6_V_read_8_reg_4944_pp0_iter2_reg); + +assign add_ln703_223_fu_507_p2 = (add_ln703_222_fu_503_p2 + sub_ln703_85_fu_385_p2); + +assign add_ln703_224_fu_645_p2 = (sub_ln703_96_reg_5210 + data_6_V_read_8_reg_4944_pp0_iter3_reg); + +assign add_ln703_225_fu_513_p2 = (sub_ln703_98_fu_466_p2 + data_6_V_read_8_reg_4944_pp0_iter2_reg); + +assign add_ln703_226_fu_518_p2 = (sub_ln703_79_reg_5125 + data_4_V_read_9_reg_4998_pp0_iter2_reg); + +assign add_ln703_227_fu_522_p2 = (add_ln703_222_fu_503_p2 + add_ln703_226_fu_518_p2); + +assign add_ln703_228_fu_663_p2 = (sub_ln703_99_fu_613_p2 + data_6_V_read_8_reg_4944_pp0_iter3_reg); + +assign add_ln703_229_fu_668_p2 = (sub_ln703_100_fu_617_p2 + data_6_V_read_8_reg_4944_pp0_iter3_reg); + +assign add_ln703_230_fu_538_p2 = (sub_ln703_83_fu_377_p2 + data_4_V_read_9_reg_4998_pp0_iter2_reg); + +assign add_ln703_231_fu_543_p2 = (add_ln703_222_fu_503_p2 + add_ln703_230_fu_538_p2); + +assign add_ln703_232_fu_673_p2 = (sub_ln703_101_fu_621_p2 + data_6_V_read_8_reg_4944_pp0_iter3_reg); + +assign add_ln703_233_fu_353_p2 = (data_6_V_read_8_reg_4944_pp0_iter1_reg + data_7_V_read_8_reg_4916_pp0_iter1_reg); + +assign add_ln703_234_fu_564_p2 = (add_ln703_233_reg_5149 + sub_ln703_95_fu_451_p2); + +assign add_ln703_235_fu_701_p2 = (add_ln703_223_reg_5231 + data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign add_ln703_236_fu_710_p2 = (sub_ln703_111_fu_658_p2 + data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign add_ln703_237_fu_715_p2 = (add_ln703_233_reg_5149_pp0_iter3_reg + add_ln703_216_reg_5215); + +assign add_ln703_238_fu_569_p2 = (add_ln703_233_reg_5149 + sub_ln703_94_fu_446_p2); + +assign add_ln703_239_fu_750_p2 = (add_ln703_233_reg_5149_pp0_iter3_reg + sub_ln703_102_fu_625_p2); + +assign add_ln703_240_fu_755_p2 = (sub_ln703_115_fu_678_p2 + data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign add_ln703_241_fu_765_p2 = (sub_ln703_117_reg_5259 + data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign add_ln703_242_fu_769_p2 = (add_ln703_233_reg_5149_pp0_iter3_reg + sub_ln703_107_fu_637_p2); + +assign add_ln703_243_fu_774_p2 = (add_ln703_209_reg_5178 + data_5_V_read_8_reg_4969_pp0_iter3_reg); + +assign add_ln703_244_fu_778_p2 = (add_ln703_233_reg_5149_pp0_iter3_reg + add_ln703_243_fu_774_p2); + +assign add_ln703_245_fu_783_p2 = (sub_ln703_114_reg_5253 + data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign add_ln703_246_fu_787_p2 = (sub_ln703_119_fu_687_p2 + data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign add_ln703_247_fu_357_p2 = (data_7_V_read_8_reg_4916_pp0_iter1_reg + data_8_V_read_7_reg_4887_pp0_iter1_reg); + +assign add_ln703_248_fu_801_p2 = (add_ln703_247_reg_5159_pp0_iter3_reg + sub_ln703_109_fu_649_p2); + +assign add_ln703_249_fu_830_p2 = (sub_ln703_123_fu_719_p2 + data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign add_ln703_250_fu_849_p2 = (sub_ln703_91_reg_5172 + data_5_V_read_8_reg_4969_pp0_iter3_reg); + +assign add_ln703_251_fu_589_p2 = (add_ln703_247_reg_5159 + data_6_V_read_8_reg_4944_pp0_iter2_reg); + +assign add_ln703_252_fu_853_p2 = (add_ln703_251_reg_5289 + add_ln703_250_fu_849_p2); + +assign add_ln703_253_fu_873_p2 = (sub_ln703_105_reg_5226 + data_6_V_read_8_reg_4944_pp0_iter3_reg); + +assign add_ln703_254_fu_877_p2 = (add_ln703_247_reg_5159_pp0_iter3_reg + add_ln703_253_fu_873_p2); + +assign add_ln703_255_fu_887_p2 = (add_ln703_214_reg_5194 + data_5_V_read_8_reg_4969_pp0_iter3_reg); + +assign add_ln703_256_fu_891_p2 = (add_ln703_251_reg_5289 + add_ln703_255_fu_887_p2); + +assign add_ln703_257_fu_925_p2 = (sub_ln703_139_fu_821_p2 + data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign add_ln703_258_fu_593_p2 = (data_8_V_read_7_reg_4887_pp0_iter2_reg + data_9_V_read_7_reg_4859_pp0_iter2_reg); + +assign add_ln703_259_fu_940_p2 = (add_ln703_258_reg_5295 + sub_ln703_124_fu_723_p2); + +assign add_ln703_260_fu_950_p2 = (add_ln703_258_reg_5295 + sub_ln703_127_fu_732_p2); + +assign add_ln703_261_fu_955_p2 = (add_ln703_258_reg_5295 + sub_ln703_131_fu_745_p2); + +assign add_ln703_262_fu_965_p2 = (sub_ln703_104_fu_633_p2 + data_6_V_read_8_reg_4944_pp0_iter3_reg); + +assign add_ln703_263_fu_970_p2 = (add_ln703_258_reg_5295 + data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign add_ln703_264_fu_974_p2 = (add_ln703_263_fu_970_p2 + add_ln703_262_fu_965_p2); + +assign add_ln703_265_fu_1010_p2 = (sub_ln703_153_fu_915_p2 + data_10_V_read11_reg_4832_pp0_iter3_reg); + +assign add_ln703_266_fu_1232_p2 = (sub_ln703_158_fu_1210_p2 + data_10_V_read11_reg_4832_pp0_iter4_reg); + +assign add_ln703_267_fu_1055_p2 = (sub_ln703_164_fu_990_p2 + data_10_V_read11_reg_4832_pp0_iter3_reg); + +assign add_ln703_268_fu_1065_p2 = (data_9_V_read_7_reg_4859_pp0_iter3_reg + data_10_V_read11_reg_4832_pp0_iter3_reg); + +assign add_ln703_269_fu_1069_p2 = (add_ln703_268_fu_1065_p2 + sub_ln703_150_fu_906_p2); + +assign add_ln703_270_fu_1255_p2 = (sub_ln703_169_fu_1222_p2 + data_11_V_read12_reg_4808_pp0_iter4_reg); + +assign add_ln703_271_fu_1080_p2 = (sub_ln703_120_fu_691_p2 + data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign add_ln703_272_fu_597_p2 = (data_10_V_read11_reg_4832_pp0_iter2_reg + data_11_V_read12_reg_4808_pp0_iter2_reg); + +assign add_ln703_273_fu_1085_p2 = (add_ln703_272_reg_5304 + data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign add_ln703_274_fu_1089_p2 = (add_ln703_273_fu_1085_p2 + add_ln703_271_fu_1080_p2); + +assign add_ln703_275_fu_1260_p2 = (add_ln703_272_reg_5304_pp0_iter4_reg + sub_ln703_154_reg_5355); + +assign add_ln703_276_fu_1100_p2 = (sub_ln703_136_fu_806_p2 + data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign add_ln703_277_fu_1264_p2 = (add_ln703_272_reg_5304_pp0_iter4_reg + add_ln703_276_reg_5430); + +assign add_ln703_278_fu_1105_p2 = (sub_ln703_137_fu_811_p2 + data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign add_ln703_279_fu_1268_p2 = (add_ln703_272_reg_5304_pp0_iter4_reg + add_ln703_278_reg_5435); + +assign add_ln703_280_fu_1125_p2 = (sub_ln703_129_reg_5279 + data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign add_ln703_281_fu_1129_p2 = (add_ln703_273_fu_1085_p2 + add_ln703_280_fu_1125_p2); + +assign add_ln703_282_fu_1135_p2 = (sub_ln703_130_fu_741_p2 + data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign add_ln703_283_fu_1140_p2 = (add_ln703_273_fu_1085_p2 + add_ln703_282_fu_1135_p2); + +assign add_ln703_284_fu_1296_p2 = (sub_ln703_145_reg_5345 + data_9_V_read_7_reg_4859_pp0_iter4_reg); + +assign add_ln703_285_fu_1300_p2 = (add_ln703_272_reg_5304_pp0_iter4_reg + add_ln703_284_fu_1296_p2); + +assign add_ln703_286_fu_1305_p2 = (sub_ln703_180_reg_5395 + data_11_V_read12_reg_4808_pp0_iter4_reg); + +assign add_ln703_287_fu_1354_p2 = (sub_ln703_186_fu_1272_p2 + data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign add_ln703_288_fu_1156_p2 = (data_11_V_read12_reg_4808_pp0_iter3_reg + data_12_V_read13_reg_4778_pp0_iter3_reg); + +assign add_ln703_289_fu_1359_p2 = (add_ln703_288_reg_5475 + sub_ln703_171_reg_5380); + +assign add_ln703_290_fu_1367_p2 = (sub_ln703_189_reg_5445 + data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign add_ln703_291_fu_1371_p2 = (sub_ln703_190_fu_1281_p2 + data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign add_ln703_292_fu_1376_p2 = (sub_ln703_191_reg_5450 + data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign add_ln703_293_fu_1380_p2 = (add_ln703_288_reg_5475 + sub_ln703_176_reg_5390); + +assign add_ln703_294_fu_1397_p2 = (add_ln703_288_reg_5475 + sub_ln703_178_fu_1242_p2); + +assign add_ln703_295_fu_1427_p2 = (sub_ln703_196_fu_1317_p2 + data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign add_ln703_296_fu_1432_p2 = (sub_ln703_166_reg_5375 + data_10_V_read11_reg_4832_pp0_iter4_reg); + +assign add_ln703_297_fu_1436_p2 = (add_ln703_288_reg_5475 + add_ln703_296_fu_1432_p2); + +assign add_ln703_298_fu_1454_p2 = (sub_ln703_202_fu_1335_p2 + data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign add_ln703_299_fu_1464_p2 = (sub_ln703_205_fu_1349_p2 + data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign add_ln703_300_fu_1474_p2 = (sub_ln703_206_fu_1363_p2 + data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign add_ln703_301_fu_1494_p2 = (sub_ln703_208_fu_1389_p2 + data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign add_ln703_302_fu_1160_p2 = (sub_ln703_113_reg_5247 + data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign add_ln703_303_fu_1164_p2 = (add_ln703_258_reg_5295 + add_ln703_302_fu_1160_p2); + +assign add_ln703_304_fu_601_p2 = (data_12_V_read13_reg_4778_pp0_iter2_reg + data_13_V_read14_reg_4745_pp0_iter2_reg); + +assign add_ln703_305_fu_1169_p2 = (add_ln703_304_reg_5314 + add_ln703_272_reg_5304); + +assign add_ln703_306_fu_1173_p2 = (add_ln703_305_fu_1169_p2 + add_ln703_303_fu_1164_p2); + +assign add_ln703_307_fu_1504_p2 = (sub_ln703_210_fu_1402_p2 + data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign add_ln703_308_fu_1509_p2 = (add_ln703_268_reg_5415 + sub_ln703_144_reg_5340); + +assign add_ln703_309_fu_1179_p2 = (add_ln703_304_reg_5314 + data_11_V_read12_reg_4808_pp0_iter3_reg); + +assign add_ln703_310_fu_1513_p2 = (add_ln703_309_reg_5484 + add_ln703_308_fu_1509_p2); + +assign add_ln703_311_fu_1523_p2 = (sub_ln703_162_reg_5370 + data_10_V_read11_reg_4832_pp0_iter4_reg); + +assign add_ln703_312_fu_1527_p2 = (add_ln703_309_reg_5484 + add_ln703_311_fu_1523_p2); + +assign add_ln703_313_fu_1532_p2 = (sub_ln703_213_fu_1417_p2 + data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign add_ln703_314_fu_1183_p2 = (data_13_V_read14_reg_4745_pp0_iter3_reg + data_14_V_read15_reg_4714_pp0_iter3_reg); + +assign add_ln703_315_fu_1552_p2 = (add_ln703_314_reg_5490 + sub_ln703_201_fu_1331_p2); + +assign add_ln703_316_fu_1187_p2 = (add_ln703_268_fu_1065_p2 + sub_ln703_135_fu_796_p2); + +assign add_ln703_317_fu_1562_p2 = (add_ln703_314_reg_5490 + add_ln703_288_reg_5475); + +assign add_ln703_318_fu_1566_p2 = (add_ln703_317_fu_1562_p2 + add_ln703_316_reg_5496); + +assign add_ln703_319_fu_1591_p2 = (sub_ln703_223_fu_1479_p2 + data_14_V_read15_reg_4714_pp0_iter4_reg); + +assign add_ln703_320_fu_1822_p2 = (sub_ln703_224_fu_1796_p2 + data_14_V_read15_reg_4714_pp0_iter5_reg); + +assign add_ln703_321_fu_1636_p2 = (sub_ln703_236_fu_1557_p2 + data_15_V_read16_reg_4682_pp0_iter4_reg); + +assign add_ln703_322_fu_1656_p2 = (sub_ln703_188_fu_1277_p2 + data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign add_ln703_323_fu_1198_p2 = (data_14_V_read15_reg_4714_pp0_iter3_reg + data_15_V_read16_reg_4682_pp0_iter3_reg); + +assign add_ln703_324_fu_1661_p2 = (add_ln703_323_reg_5506 + data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign add_ln703_325_fu_1665_p2 = (add_ln703_324_fu_1661_p2 + add_ln703_322_fu_1656_p2); + +assign add_ln703_326_fu_1686_p2 = (add_ln703_323_reg_5506 + sub_ln703_228_fu_1499_p2); + +assign add_ln703_327_fu_1887_p2 = (sub_ln703_250_fu_1844_p2 + data_15_V_read16_reg_4682_pp0_iter5_reg); + +assign add_ln703_328_fu_1892_p2 = (sub_ln703_252_reg_5575 + data_15_V_read16_reg_4682_pp0_iter5_reg); + +assign add_ln703_329_fu_1705_p2 = (sub_ln703_214_fu_1422_p2 + data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign add_ln703_330_fu_1710_p2 = (add_ln703_323_reg_5506 + add_ln703_329_fu_1705_p2); + +assign add_ln703_331_fu_1900_p2 = (sub_ln703_254_reg_5585 + data_15_V_read16_reg_4682_pp0_iter5_reg); + +assign add_ln703_332_fu_1715_p2 = (sub_ln703_216_fu_1446_p2 + data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign add_ln703_333_fu_1720_p2 = (add_ln703_323_reg_5506 + add_ln703_332_fu_1715_p2); + +assign add_ln703_334_fu_1725_p2 = (add_ln703_323_reg_5506 + sub_ln703_234_fu_1547_p2); + +assign add_ln703_335_fu_1730_p2 = (sub_ln703_256_fu_1631_p2 + data_16_V_read17_reg_4650_pp0_iter4_reg); + +assign add_ln703_336_fu_1913_p2 = (sub_ln703_258_fu_1854_p2 + data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign add_ln703_337_fu_1923_p2 = (sub_ln703_261_reg_5600 + data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign add_ln703_338_fu_1939_p2 = (sub_ln703_266_reg_5620 + data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign add_ln703_339_fu_1740_p2 = (sub_ln703_209_fu_1393_p2 + data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign add_ln703_340_fu_1943_p2 = (data_15_V_read16_reg_4682_pp0_iter5_reg + data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign add_ln703_341_fu_1947_p2 = (add_ln703_340_fu_1943_p2 + data_14_V_read15_reg_4714_pp0_iter5_reg); + +assign add_ln703_342_fu_1952_p2 = (add_ln703_341_fu_1947_p2 + add_ln703_339_reg_5655); + +assign add_ln703_343_fu_1745_p2 = (sub_ln703_268_fu_1691_p2 + data_16_V_read17_reg_4650_pp0_iter4_reg); + +assign add_ln703_344_fu_1966_p2 = (sub_ln703_270_reg_5630 + data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign add_ln703_345_fu_1970_p2 = (sub_ln703_271_fu_1882_p2 + data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign add_ln703_346_fu_1993_p2 = (sub_ln703_273_fu_1896_p2 + data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign add_ln703_347_fu_1760_p2 = (data_16_V_read17_reg_4650_pp0_iter4_reg + data_17_V_read_8_reg_4621_pp0_iter4_reg); + +assign add_ln703_348_fu_2017_p2 = (add_ln703_347_reg_5675 + sub_ln703_257_reg_5595); + +assign add_ln703_349_fu_2021_p2 = (sub_ln703_219_fu_1788_p2 + data_14_V_read15_reg_4714_pp0_iter5_reg); + +assign add_ln703_350_fu_2026_p2 = (add_ln703_347_reg_5675 + data_15_V_read16_reg_4682_pp0_iter5_reg); + +assign add_ln703_351_fu_2030_p2 = (add_ln703_350_fu_2026_p2 + add_ln703_349_fu_2021_p2); + +assign add_ln703_352_fu_2051_p2 = (sub_ln703_278_reg_5650 + data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign add_ln703_353_fu_2060_p2 = (add_ln703_347_reg_5675 + sub_ln703_264_fu_1867_p2); + +assign add_ln703_354_fu_2080_p2 = (sub_ln703_281_fu_1957_p2 + data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign add_ln703_355_fu_2114_p2 = (sub_ln703_290_reg_5670 + data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign add_ln703_356_fu_2118_p2 = (sub_ln703_235_fu_1812_p2 + data_15_V_read16_reg_4682_pp0_iter5_reg); + +assign add_ln703_357_fu_1764_p2 = (data_17_V_read_8_reg_4621_pp0_iter4_reg + data_18_V_read_7_reg_4594_pp0_iter4_reg); + +assign add_ln703_358_fu_2123_p2 = (add_ln703_357_reg_5683 + data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign add_ln703_359_fu_2127_p2 = (add_ln703_358_fu_2123_p2 + add_ln703_356_fu_2118_p2); + +assign add_ln703_360_fu_2138_p2 = (sub_ln703_292_fu_2012_p2 + data_18_V_read_7_reg_4594_pp0_iter5_reg); + +assign add_ln703_361_fu_2153_p2 = (sub_ln703_259_fu_1858_p2 + data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign add_ln703_362_fu_2158_p2 = (add_ln703_357_reg_5683 + add_ln703_361_fu_2153_p2); + +assign add_ln703_363_fu_2163_p2 = (sub_ln703_295_fu_2041_p2 + data_18_V_read_7_reg_4594_pp0_iter5_reg); + +assign add_ln703_364_fu_2178_p2 = (sub_ln703_297_fu_2055_p2 + data_18_V_read_7_reg_4594_pp0_iter5_reg); + +assign add_ln703_365_fu_2183_p2 = (sub_ln703_298_fu_2065_p2 + data_18_V_read_7_reg_4594_pp0_iter5_reg); + +assign add_ln703_366_fu_2193_p2 = (sub_ln703_303_fu_2094_p2 + data_18_V_read_7_reg_4594_pp0_iter5_reg); + +assign add_ln703_367_fu_2198_p2 = (sub_ln703_305_fu_2104_p2 + data_18_V_read_7_reg_4594_pp0_iter5_reg); + +assign add_ln703_368_fu_2429_p2 = (add_ln703_357_reg_5683_pp0_iter6_reg + sub_ln703_288_reg_5738); + +assign add_ln703_369_fu_2213_p2 = (sub_ln703_307_fu_2133_p2 + data_19_V_read_7_reg_4567_pp0_iter5_reg); + +assign add_ln703_370_fu_2437_p2 = (sub_ln703_309_reg_5773 + data_19_V_read_7_reg_4567_pp0_iter6_reg); + +assign add_ln703_371_fu_1768_p2 = (data_18_V_read_7_reg_4594_pp0_iter4_reg + data_19_V_read_7_reg_4567_pp0_iter4_reg); + +assign add_ln703_372_fu_2228_p2 = (add_ln703_371_reg_5691 + sub_ln703_293_fu_2036_p2); + +assign add_ln703_373_fu_2445_p2 = (sub_ln703_313_fu_2413_p2 + data_19_V_read_7_reg_4567_pp0_iter6_reg); + +assign add_ln703_374_fu_2263_p2 = (sub_ln703_284_fu_1980_p2 + data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign add_ln703_375_fu_2268_p2 = (add_ln703_371_reg_5691 + add_ln703_374_fu_2263_p2); + +assign add_ln703_376_fu_2278_p2 = (sub_ln703_287_fu_1998_p2 + data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign add_ln703_377_fu_2283_p2 = (add_ln703_371_reg_5691 + add_ln703_376_fu_2278_p2); + +assign add_ln703_378_fu_2288_p2 = (sub_ln703_289_reg_5665 + data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign add_ln703_379_fu_2292_p2 = (add_ln703_371_reg_5691 + add_ln703_378_fu_2288_p2); + +assign add_ln703_380_fu_2297_p2 = (sub_ln703_319_fu_2208_p2 + data_19_V_read_7_reg_4567_pp0_iter5_reg); + +assign add_ln703_381_fu_2307_p2 = (sub_ln703_322_fu_2223_p2 + data_20_V_read21_reg_4539_pp0_iter5_reg); + +assign add_ln703_382_fu_2486_p2 = (sub_ln703_325_reg_5808 + data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign add_ln703_383_fu_2490_p2 = (sub_ln703_326_fu_2441_p2 + data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign add_ln703_384_fu_1772_p2 = (data_19_V_read_7_reg_4567_pp0_iter4_reg + data_20_V_read21_reg_4539_pp0_iter4_reg); + +assign add_ln703_385_fu_2499_p2 = (add_ln703_384_reg_5701_pp0_iter6_reg + sub_ln703_312_fu_2409_p2); + +assign add_ln703_386_fu_2514_p2 = (sub_ln703_331_reg_5823 + data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign add_ln703_387_fu_2518_p2 = (add_ln703_384_reg_5701_pp0_iter6_reg + sub_ln703_317_fu_2425_p2); + +assign add_ln703_388_fu_2317_p2 = (sub_ln703_285_fu_1984_p2 + data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign add_ln703_389_fu_2322_p2 = (add_ln703_384_reg_5701 + data_18_V_read_7_reg_4594_pp0_iter5_reg); + +assign add_ln703_390_fu_2326_p2 = (add_ln703_389_fu_2322_p2 + add_ln703_388_fu_2317_p2); + +assign add_ln703_391_fu_2527_p2 = (sub_ln703_334_fu_2464_p2 + data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign add_ln703_392_fu_2540_p2 = (sub_ln703_336_fu_2469_p2 + data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign add_ln703_393_fu_2559_p2 = (sub_ln703_294_fu_2405_p2 + data_18_V_read_7_reg_4594_pp0_iter6_reg); + +assign add_ln703_394_fu_1776_p2 = (data_20_V_read21_reg_4539_pp0_iter4_reg + data_21_V_read22_reg_4512_pp0_iter4_reg); + +assign add_ln703_395_fu_2564_p2 = (add_ln703_394_reg_5710_pp0_iter6_reg + data_19_V_read_7_reg_4567_pp0_iter6_reg); + +assign add_ln703_396_fu_2568_p2 = (add_ln703_395_fu_2564_p2 + add_ln703_393_fu_2559_p2); + +assign add_ln703_397_fu_2599_p2 = (add_ln703_394_reg_5710_pp0_iter6_reg + sub_ln703_328_reg_5818); + +assign add_ln703_398_fu_2337_p2 = (add_ln703_347_reg_5675 + sub_ln703_267_fu_1872_p2); + +assign add_ln703_399_fu_2342_p2 = (add_ln703_394_reg_5710 + add_ln703_371_reg_5691); + +assign add_ln703_400_fu_2346_p2 = (add_ln703_399_fu_2342_p2 + add_ln703_398_fu_2337_p2); + +assign add_ln703_401_fu_2623_p2 = (sub_ln703_343_reg_5853 + data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign add_ln703_402_fu_2631_p2 = (sub_ln703_344_fu_2523_p2 + data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign add_ln703_403_fu_2645_p2 = (sub_ln703_320_fu_2433_p2 + data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign add_ln703_404_fu_1780_p2 = (data_21_V_read22_reg_4512_pp0_iter4_reg + data_22_V_read23_reg_4483_pp0_iter4_reg); + +assign add_ln703_405_fu_2650_p2 = (add_ln703_404_reg_5718_pp0_iter6_reg + add_ln703_403_fu_2645_p2); + +assign add_ln703_406_fu_2655_p2 = (sub_ln703_347_fu_2536_p2 + data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign add_ln703_407_fu_2675_p2 = (sub_ln703_323_reg_5798 + data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign add_ln703_408_fu_2679_p2 = (add_ln703_404_reg_5718_pp0_iter6_reg + add_ln703_407_fu_2675_p2); + +assign add_ln703_409_fu_2704_p2 = (sub_ln703_354_fu_2589_p2 + data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign add_ln703_410_fu_2709_p2 = (sub_ln703_355_fu_2594_p2 + data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign add_ln703_411_fu_2352_p2 = (add_ln703_371_reg_5691 + sub_ln703_299_fu_2070_p2); + +assign add_ln703_412_fu_2357_p2 = (add_ln703_404_reg_5718 + data_20_V_read21_reg_4539_pp0_iter5_reg); + +assign add_ln703_413_fu_2361_p2 = (add_ln703_412_fu_2357_p2 + add_ln703_411_fu_2352_p2); + +assign add_ln703_414_fu_2367_p2 = (sub_ln703_315_fu_2188_p2 + data_19_V_read_7_reg_4567_pp0_iter5_reg); + +assign add_ln703_415_fu_2372_p2 = (add_ln703_412_fu_2357_p2 + add_ln703_414_fu_2367_p2); + +assign add_ln703_416_fu_2733_p2 = (add_ln703_357_reg_5683_pp0_iter6_reg + sub_ln703_283_reg_5733); + +assign add_ln703_417_fu_2737_p2 = (add_ln703_404_reg_5718_pp0_iter6_reg + add_ln703_384_reg_5701_pp0_iter6_reg); + +assign add_ln703_418_fu_2741_p2 = (add_ln703_417_fu_2737_p2 + add_ln703_416_fu_2733_p2); + +assign add_ln703_419_fu_2757_p2 = (sub_ln703_332_reg_5828 + data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign add_ln703_420_fu_2761_p2 = (add_ln703_404_reg_5718_pp0_iter6_reg + add_ln703_419_fu_2757_p2); + +assign add_ln703_421_fu_2766_p2 = (sub_ln703_333_fu_2460_p2 + data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign add_ln703_422_fu_2771_p2 = (add_ln703_404_reg_5718_pp0_iter6_reg + add_ln703_421_fu_2766_p2); + +assign add_ln703_423_fu_2993_p2 = (sub_ln703_361_reg_5936 + data_22_V_read23_reg_4483_pp0_iter7_reg); + +assign add_ln703_424_fu_2806_p2 = (sub_ln703_367_fu_2689_p2 + data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign add_ln703_425_fu_3001_p2 = (sub_ln703_369_reg_5946 + data_23_V_read24_reg_4451_pp0_iter7_reg); + +assign add_ln703_426_fu_2378_p2 = (sub_ln703_244_fu_1827_p2 + data_15_V_read16_reg_4682_pp0_iter5_reg); + +assign add_ln703_427_fu_2383_p2 = (add_ln703_358_fu_2123_p2 + add_ln703_426_fu_2378_p2); + +assign add_ln703_428_fu_2389_p2 = (data_22_V_read23_reg_4483_pp0_iter5_reg + data_23_V_read24_reg_4451_pp0_iter5_reg); + +assign add_ln703_429_fu_2825_p2 = (add_ln703_428_reg_5888 + data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign add_ln703_430_fu_2829_p2 = (add_ln703_429_fu_2825_p2 + add_ln703_384_reg_5701_pp0_iter6_reg); + +assign add_ln703_431_fu_2834_p2 = (add_ln703_430_fu_2829_p2 + add_ln703_427_reg_5883); + +assign add_ln703_432_fu_3014_p2 = (sub_ln703_374_reg_5956 + data_23_V_read24_reg_4451_pp0_iter7_reg); + +assign add_ln703_433_fu_3036_p2 = (sub_ln703_379_reg_5971 + data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign add_ln703_434_fu_2873_p2 = (sub_ln703_380_fu_2786_p2 + data_24_V_read25_reg_4421_pp0_iter6_reg); + +assign add_ln703_435_fu_2393_p2 = (data_23_V_read24_reg_4451_pp0_iter5_reg + data_24_V_read25_reg_4421_pp0_iter5_reg); + +assign add_ln703_436_fu_2883_p2 = (add_ln703_435_reg_5894 + sub_ln703_365_fu_2670_p2); + +assign add_ln703_437_fu_3053_p2 = (sub_ln703_385_reg_5986 + data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign add_ln703_438_fu_2888_p2 = (add_ln703_435_reg_5894 + sub_ln703_370_fu_2714_p2); + +assign add_ln703_439_fu_3075_p2 = (sub_ln703_390_fu_3009_p2 + data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign add_ln703_440_fu_2908_p2 = (add_ln703_394_reg_5710_pp0_iter6_reg + sub_ln703_330_fu_2455_p2); + +assign add_ln703_441_fu_2913_p2 = (add_ln703_435_reg_5894 + data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign add_ln703_442_fu_2917_p2 = (add_ln703_441_fu_2913_p2 + add_ln703_440_fu_2908_p2); + +assign add_ln703_443_fu_3099_p2 = (sub_ln703_397_reg_6006 + data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign add_ln703_444_fu_2928_p2 = (sub_ln703_400_fu_2868_p2 + data_24_V_read25_reg_4421_pp0_iter6_reg); + +assign add_ln703_445_fu_3122_p2 = (sub_ln703_402_reg_6016 + data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign add_ln703_446_fu_2397_p2 = (data_24_V_read25_reg_4421_pp0_iter5_reg + data_25_V_read26_reg_4391_pp0_iter5_reg); + +assign add_ln703_447_fu_2933_p2 = (add_ln703_446_reg_5901 + sub_ln703_383_fu_2801_p2); + +assign add_ln703_448_fu_3150_p2 = (sub_ln703_408_reg_6026 + data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign add_ln703_449_fu_3158_p2 = (sub_ln703_410_fu_3071_p2 + data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign add_ln703_450_fu_3168_p2 = (sub_ln703_357_reg_5926 + data_22_V_read23_reg_4483_pp0_iter7_reg); + +assign add_ln703_451_fu_2943_p2 = (add_ln703_446_reg_5901 + data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign add_ln703_452_fu_3172_p2 = (add_ln703_451_reg_6066 + add_ln703_450_fu_3168_p2); + +assign add_ln703_453_fu_3218_p2 = (sub_ln703_420_fu_3117_p2 + data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign add_ln703_454_fu_3232_p2 = (sub_ln703_424_fu_3140_p2 + data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign add_ln703_455_fu_3237_p2 = (data_25_V_read26_reg_4391_pp0_iter7_reg + data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign add_ln703_456_fu_3241_p2 = (add_ln703_455_fu_3237_p2 + sub_ln703_405_fu_3057_p2); + +assign add_ln703_457_fu_3281_p2 = (sub_ln703_431_fu_3185_p2 + data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign add_ln703_458_fu_3286_p2 = (add_ln703_455_fu_3237_p2 + sub_ln703_413_fu_3084_p2); + +assign add_ln703_459_fu_3292_p2 = (add_ln703_455_fu_3237_p2 + sub_ln703_415_fu_3094_p2); + +assign add_ln703_460_fu_3303_p2 = (sub_ln703_433_fu_3194_p2 + data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign add_ln703_461_fu_3323_p2 = (sub_ln703_438_fu_3223_p2 + data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign add_ln703_462_fu_2401_p2 = (data_26_V_read27_reg_4365_pp0_iter5_reg + data_27_V_read_8_reg_4342_pp0_iter5_reg); + +assign add_ln703_463_fu_3328_p2 = (add_ln703_462_reg_5909_pp0_iter7_reg + sub_ln703_421_fu_3126_p2); + +assign add_ln703_464_fu_3333_p2 = (sub_ln703_439_fu_3228_p2 + data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign add_ln703_465_fu_3338_p2 = (add_ln703_462_reg_5909_pp0_iter7_reg + sub_ln703_422_fu_3130_p2); + +assign add_ln703_466_fu_3358_p2 = (sub_ln703_407_fu_3066_p2 + data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign add_ln703_467_fu_3363_p2 = (add_ln703_462_reg_5909_pp0_iter7_reg + add_ln703_466_fu_3358_p2); + +assign add_ln703_468_fu_3378_p2 = (sub_ln703_445_fu_3271_p2 + data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign add_ln703_469_fu_3383_p2 = (sub_ln703_446_fu_3276_p2 + data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign add_ln703_470_fu_3398_p2 = (sub_ln703_414_fu_3089_p2 + data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign add_ln703_471_fu_3403_p2 = (add_ln703_462_reg_5909_pp0_iter7_reg + add_ln703_470_fu_3398_p2); + +assign add_ln703_472_fu_3413_p2 = (sub_ln703_447_fu_3298_p2 + data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign add_ln703_473_fu_3423_p2 = (sub_ln703_398_fu_3026_p2 + data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign add_ln703_474_fu_3428_p2 = (add_ln703_462_reg_5909_pp0_iter7_reg + data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign add_ln703_475_fu_3432_p2 = (add_ln703_474_fu_3428_p2 + add_ln703_473_fu_3423_p2); + +assign add_ln703_476_fu_3531_p2 = (add_ln703_462_reg_5909_pp0_iter8_reg + sub_ln703_434_reg_6113); + +assign add_ln703_477_fu_2947_p2 = (sub_ln703_345_fu_2532_p2 + data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign add_ln703_478_fu_2952_p2 = (add_ln703_428_reg_5888 + add_ln703_477_fu_2947_p2); + +assign add_ln703_479_fu_2957_p2 = (add_ln703_462_reg_5909 + add_ln703_446_reg_5901); + +assign add_ln703_480_fu_2961_p2 = (add_ln703_479_fu_2957_p2 + add_ln703_478_fu_2952_p2); + +assign add_ln703_481_fu_3443_p2 = (sub_ln703_423_fu_3135_p2 + data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign add_ln703_482_fu_2967_p2 = (data_27_V_read_8_reg_4342_pp0_iter6_reg + data_28_V_read_7_reg_4313_pp0_iter6_reg); + +assign add_ln703_483_fu_3448_p2 = (add_ln703_482_reg_6077 + add_ln703_481_fu_3443_p2); + +assign add_ln703_484_fu_3555_p2 = (sub_ln703_452_reg_6148 + data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign add_ln703_485_fu_3559_p2 = (sub_ln703_453_reg_6153 + data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign add_ln703_486_fu_3453_p2 = (add_ln703_482_reg_6077 + sub_ln703_442_fu_3256_p2); + +assign add_ln703_487_fu_3458_p2 = (add_ln703_482_reg_6077 + sub_ln703_443_fu_3261_p2); + +assign add_ln703_488_fu_3571_p2 = (sub_ln703_455_reg_6168 + data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign add_ln703_489_fu_3468_p2 = (sub_ln703_430_fu_3181_p2 + data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign add_ln703_490_fu_3473_p2 = (add_ln703_482_reg_6077 + add_ln703_489_fu_3468_p2); + +assign add_ln703_491_fu_2971_p2 = (add_ln703_446_reg_5901 + sub_ln703_395_fu_2853_p2); + +assign add_ln703_492_fu_3478_p2 = (add_ln703_482_reg_6077 + data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign add_ln703_493_fu_3595_p2 = (add_ln703_492_reg_6223 + add_ln703_491_reg_6087_pp0_iter8_reg); + +assign add_ln703_494_fu_3487_p2 = (sub_ln703_435_fu_3204_p2 + data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign add_ln703_495_fu_3492_p2 = (add_ln703_482_reg_6077 + add_ln703_494_fu_3487_p2); + +assign add_ln703_496_fu_3497_p2 = (data_28_V_read_7_reg_4313_pp0_iter7_reg + data_29_V_read_7_reg_4279_pp0_iter7_reg); + +assign add_ln703_497_fu_3501_p2 = (add_ln703_496_fu_3497_p2 + sub_ln703_449_fu_3313_p2); + +assign add_ln703_498_fu_3616_p2 = (sub_ln703_460_fu_3535_p2 + data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign add_ln703_499_fu_3631_p2 = (sub_ln703_464_fu_3547_p2 + data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign add_ln703_500_fu_3655_p2 = (sub_ln703_466_fu_3563_p2 + data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign add_ln703_501_fu_3708_p2 = (sub_ln703_475_fu_3599_p2 + data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign add_ln703_502_fu_3713_p2 = (sub_ln703_476_fu_3603_p2 + data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign add_ln703_503_fu_3757_p2 = (sub_ln703_483_fu_3645_p2 + data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign add_ln703_504_fu_3777_p2 = (sub_ln703_486_reg_6244 + data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign add_ln703_505_fu_3785_p2 = (sub_ln703_488_fu_3665_p2 + data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign add_ln703_506_fu_3795_p2 = (sub_ln703_491_reg_6254 + data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign add_ln703_507_fu_3799_p2 = (sub_ln703_492_fu_3679_p2 + data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign add_ln703_508_fu_3843_p2 = (sub_ln703_448_reg_6118 + data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign add_ln703_509_fu_2976_p2 = (data_30_V_read31_reg_4250_pp0_iter6_reg + data_31_V_read32_reg_4221_pp0_iter6_reg); + +assign add_ln703_510_fu_3527_p2 = (add_ln703_509_reg_6092 + data_29_V_read_7_reg_4279_pp0_iter7_reg); + +assign add_ln703_511_fu_3847_p2 = (add_ln703_510_reg_6264 + add_ln703_508_fu_3843_p2); + +assign add_ln703_514_fu_3862_p2 = (sub_ln703_461_reg_6208 + data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign add_ln703_516_fu_2980_p2 = (sub_ln703_349_fu_2549_p2 + data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign add_ln703_517_fu_3871_p2 = (add_ln703_451_reg_6066_pp0_iter8_reg + add_ln703_516_reg_6103_pp0_iter8_reg); + +assign add_ln703_518_fu_3875_p2 = (add_ln703_510_reg_6264 + add_ln703_492_reg_6223); + +assign add_ln703_526_fu_3945_p2 = (add_ln703_462_reg_5909_pp0_iter8_reg + sub_ln703_428_reg_6108); + +assign add_ln703_527_fu_3949_p2 = (add_ln703_509_reg_6092_pp0_iter8_reg + add_ln703_496_reg_6234); + +assign add_ln703_fu_280_p2 = (data_0_V_read_int_reg + data_1_V_read_int_reg); + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_state10_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign sub_ln703_100_fu_617_p2 = (add_ln703_210_reg_5143_pp0_iter3_reg - data_5_V_read_8_reg_4969_pp0_iter3_reg); + +assign sub_ln703_101_fu_621_p2 = (add_ln703_213_reg_5189 - data_5_V_read_8_reg_4969_pp0_iter3_reg); + +assign sub_ln703_102_fu_625_p2 = (sub_ln703_89_reg_5166 - data_5_V_read_8_reg_4969_pp0_iter3_reg); + +assign sub_ln703_103_fu_629_p2 = (add_ln703_214_reg_5194 - data_5_V_read_8_reg_4969_pp0_iter3_reg); + +assign sub_ln703_104_fu_633_p2 = (add_ln703_211_reg_5184 - data_5_V_read_8_reg_4969_pp0_iter3_reg); + +assign sub_ln703_105_fu_489_p2 = (sub_ln703_92_fu_437_p2 - data_5_V_read_8_reg_4969_pp0_iter2_reg); + +assign sub_ln703_106_fu_494_p2 = (add_ln703_212_fu_425_p2 - data_5_V_read_8_reg_4969_pp0_iter2_reg); + +assign sub_ln703_107_fu_637_p2 = (sub_ln703_93_reg_5200 - data_5_V_read_8_reg_4969_pp0_iter3_reg); + +assign sub_ln703_108_fu_641_p2 = (sub_ln703_94_reg_5205 - data_6_V_read_8_reg_4944_pp0_iter3_reg); + +assign sub_ln703_109_fu_649_p2 = (add_ln703_215_fu_605_p2 - data_6_V_read_8_reg_4944_pp0_iter3_reg); + +assign sub_ln703_110_fu_654_p2 = (add_ln703_216_reg_5215 - data_6_V_read_8_reg_4944_pp0_iter3_reg); + +assign sub_ln703_111_fu_658_p2 = (sub_ln703_97_fu_609_p2 - data_6_V_read_8_reg_4944_pp0_iter3_reg); + +assign sub_ln703_112_fu_528_p2 = (add_ln703_217_fu_470_p2 - data_6_V_read_8_reg_4944_pp0_iter2_reg); + +assign sub_ln703_113_fu_533_p2 = (add_ln703_218_fu_474_p2 - data_6_V_read_8_reg_4944_pp0_iter2_reg); + +assign sub_ln703_114_fu_549_p2 = (add_ln703_219_fu_479_p2 - data_6_V_read_8_reg_4944_pp0_iter2_reg); + +assign sub_ln703_115_fu_678_p2 = (sub_ln703_103_fu_629_p2 - data_6_V_read_8_reg_4944_pp0_iter3_reg); + +assign sub_ln703_116_fu_683_p2 = (add_ln703_220_reg_5221 - data_6_V_read_8_reg_4944_pp0_iter3_reg); + +assign sub_ln703_117_fu_554_p2 = (sub_ln703_106_fu_494_p2 - data_6_V_read_8_reg_4944_pp0_iter2_reg); + +assign sub_ln703_118_fu_559_p2 = (add_ln703_221_fu_499_p2 - data_6_V_read_8_reg_4944_pp0_iter2_reg); + +assign sub_ln703_119_fu_687_p2 = (add_ln703_223_reg_5231 - data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign sub_ln703_120_fu_691_p2 = (sub_ln703_108_fu_641_p2 - data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign sub_ln703_121_fu_696_p2 = (add_ln703_224_fu_645_p2 - data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign sub_ln703_122_fu_705_p2 = (sub_ln703_110_fu_654_p2 - data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign sub_ln703_123_fu_719_p2 = (add_ln703_225_reg_5237 - data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign sub_ln703_124_fu_723_p2 = (add_ln703_227_reg_5242 - data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign sub_ln703_125_fu_727_p2 = (add_ln703_228_fu_663_p2 - data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign sub_ln703_126_fu_574_p2 = (sub_ln703_112_fu_528_p2 - data_7_V_read_8_reg_4916_pp0_iter2_reg); + +assign sub_ln703_127_fu_732_p2 = (sub_ln703_113_reg_5247 - data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign sub_ln703_128_fu_736_p2 = (add_ln703_229_fu_668_p2 - data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign sub_ln703_129_fu_579_p2 = (add_ln703_231_fu_543_p2 - data_7_V_read_8_reg_4916_pp0_iter2_reg); + +assign sub_ln703_130_fu_741_p2 = (sub_ln703_114_reg_5253 - data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign sub_ln703_131_fu_745_p2 = (add_ln703_232_fu_673_p2 - data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign sub_ln703_132_fu_760_p2 = (sub_ln703_116_fu_683_p2 - data_7_V_read_8_reg_4916_pp0_iter3_reg); + +assign sub_ln703_133_fu_584_p2 = (sub_ln703_118_fu_559_p2 - data_7_V_read_8_reg_4916_pp0_iter2_reg); + +assign sub_ln703_134_fu_792_p2 = (add_ln703_234_reg_5264 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_135_fu_796_p2 = (sub_ln703_121_fu_696_p2 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_136_fu_806_p2 = (add_ln703_235_fu_701_p2 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_137_fu_811_p2 = (sub_ln703_122_fu_705_p2 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_138_fu_816_p2 = (add_ln703_236_fu_710_p2 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_139_fu_821_p2 = (add_ln703_237_fu_715_p2 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_140_fu_826_p2 = (add_ln703_238_reg_5269 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_141_fu_835_p2 = (sub_ln703_125_fu_727_p2 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_142_fu_840_p2 = (sub_ln703_126_reg_5274 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_143_fu_844_p2 = (sub_ln703_128_fu_736_p2 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_144_fu_858_p2 = (add_ln703_239_fu_750_p2 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_145_fu_863_p2 = (add_ln703_240_fu_755_p2 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_146_fu_868_p2 = (sub_ln703_132_fu_760_p2 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_147_fu_882_p2 = (add_ln703_241_fu_765_p2 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_148_fu_896_p2 = (add_ln703_242_fu_769_p2 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_149_fu_901_p2 = (add_ln703_244_fu_778_p2 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_150_fu_906_p2 = (add_ln703_245_fu_783_p2 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_151_fu_911_p2 = (sub_ln703_133_reg_5284 - data_8_V_read_7_reg_4887_pp0_iter3_reg); + +assign sub_ln703_152_fu_1202_p2 = (add_ln703_246_reg_5320 - data_9_V_read_7_reg_4859_pp0_iter4_reg); + +assign sub_ln703_153_fu_915_p2 = (sub_ln703_134_fu_792_p2 - data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign sub_ln703_154_fu_920_p2 = (add_ln703_248_fu_801_p2 - data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign sub_ln703_155_fu_1206_p2 = (sub_ln703_138_reg_5325 - data_9_V_read_7_reg_4859_pp0_iter4_reg); + +assign sub_ln703_156_fu_930_p2 = (sub_ln703_140_fu_826_p2 - data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign sub_ln703_157_fu_935_p2 = (add_ln703_249_fu_830_p2 - data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign sub_ln703_158_fu_1210_p2 = (sub_ln703_141_reg_5330 - data_9_V_read_7_reg_4859_pp0_iter4_reg); + +assign sub_ln703_159_fu_945_p2 = (sub_ln703_142_fu_840_p2 - data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign sub_ln703_160_fu_1214_p2 = (sub_ln703_143_reg_5335 - data_9_V_read_7_reg_4859_pp0_iter4_reg); + +assign sub_ln703_161_fu_960_p2 = (add_ln703_252_fu_853_p2 - data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign sub_ln703_162_fu_980_p2 = (sub_ln703_146_fu_868_p2 - data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign sub_ln703_163_fu_985_p2 = (add_ln703_254_fu_877_p2 - data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign sub_ln703_164_fu_990_p2 = (sub_ln703_147_fu_882_p2 - data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign sub_ln703_165_fu_995_p2 = (add_ln703_256_fu_891_p2 - data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign sub_ln703_166_fu_1000_p2 = (sub_ln703_148_fu_896_p2 - data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign sub_ln703_167_fu_1218_p2 = (sub_ln703_149_reg_5350 - data_9_V_read_7_reg_4859_pp0_iter4_reg); + +assign sub_ln703_168_fu_1005_p2 = (sub_ln703_151_fu_911_p2 - data_9_V_read_7_reg_4859_pp0_iter3_reg); + +assign sub_ln703_169_fu_1222_p2 = (sub_ln703_152_fu_1202_p2 - data_10_V_read11_reg_4832_pp0_iter4_reg); + +assign sub_ln703_170_fu_1227_p2 = (sub_ln703_155_fu_1206_p2 - data_10_V_read11_reg_4832_pp0_iter4_reg); + +assign sub_ln703_171_fu_1015_p2 = (add_ln703_257_fu_925_p2 - data_10_V_read11_reg_4832_pp0_iter3_reg); + +assign sub_ln703_172_fu_1020_p2 = (sub_ln703_156_fu_930_p2 - data_10_V_read11_reg_4832_pp0_iter3_reg); + +assign sub_ln703_173_fu_1025_p2 = (sub_ln703_157_fu_935_p2 - data_10_V_read11_reg_4832_pp0_iter3_reg); + +assign sub_ln703_174_fu_1030_p2 = (add_ln703_259_fu_940_p2 - data_10_V_read11_reg_4832_pp0_iter3_reg); + +assign sub_ln703_175_fu_1035_p2 = (sub_ln703_159_fu_945_p2 - data_10_V_read11_reg_4832_pp0_iter3_reg); + +assign sub_ln703_176_fu_1040_p2 = (add_ln703_260_fu_950_p2 - data_10_V_read11_reg_4832_pp0_iter3_reg); + +assign sub_ln703_177_fu_1237_p2 = (sub_ln703_160_fu_1214_p2 - data_10_V_read11_reg_4832_pp0_iter4_reg); + +assign sub_ln703_178_fu_1242_p2 = (add_ln703_261_reg_5360 - data_10_V_read11_reg_4832_pp0_iter4_reg); + +assign sub_ln703_179_fu_1246_p2 = (sub_ln703_161_reg_5365 - data_10_V_read11_reg_4832_pp0_iter4_reg); + +assign sub_ln703_180_fu_1045_p2 = (add_ln703_264_fu_974_p2 - data_10_V_read11_reg_4832_pp0_iter3_reg); + +assign sub_ln703_181_fu_1050_p2 = (sub_ln703_163_fu_985_p2 - data_10_V_read11_reg_4832_pp0_iter3_reg); + +assign sub_ln703_182_fu_1060_p2 = (sub_ln703_165_fu_995_p2 - data_10_V_read11_reg_4832_pp0_iter3_reg); + +assign sub_ln703_183_fu_1250_p2 = (sub_ln703_167_fu_1218_p2 - data_10_V_read11_reg_4832_pp0_iter4_reg); + +assign sub_ln703_184_fu_1075_p2 = (sub_ln703_168_fu_1005_p2 - data_10_V_read11_reg_4832_pp0_iter3_reg); + +assign sub_ln703_185_fu_1095_p2 = (add_ln703_265_fu_1010_p2 - data_11_V_read12_reg_4808_pp0_iter3_reg); + +assign sub_ln703_186_fu_1272_p2 = (sub_ln703_170_fu_1227_p2 - data_11_V_read12_reg_4808_pp0_iter4_reg); + +assign sub_ln703_187_fu_1110_p2 = (sub_ln703_172_fu_1020_p2 - data_11_V_read12_reg_4808_pp0_iter3_reg); + +assign sub_ln703_188_fu_1277_p2 = (sub_ln703_173_reg_5385 - data_11_V_read12_reg_4808_pp0_iter4_reg); + +assign sub_ln703_189_fu_1115_p2 = (sub_ln703_174_fu_1030_p2 - data_11_V_read12_reg_4808_pp0_iter3_reg); + +assign sub_ln703_190_fu_1281_p2 = (add_ln703_266_fu_1232_p2 - data_11_V_read12_reg_4808_pp0_iter4_reg); + +assign sub_ln703_191_fu_1120_p2 = (sub_ln703_175_fu_1035_p2 - data_11_V_read12_reg_4808_pp0_iter3_reg); + +assign sub_ln703_192_fu_1286_p2 = (sub_ln703_177_fu_1237_p2 - data_11_V_read12_reg_4808_pp0_iter4_reg); + +assign sub_ln703_193_fu_1291_p2 = (sub_ln703_179_fu_1246_p2 - data_11_V_read12_reg_4808_pp0_iter4_reg); + +assign sub_ln703_194_fu_1309_p2 = (sub_ln703_181_reg_5400 - data_11_V_read12_reg_4808_pp0_iter4_reg); + +assign sub_ln703_195_fu_1313_p2 = (add_ln703_267_reg_5405 - data_11_V_read12_reg_4808_pp0_iter4_reg); + +assign sub_ln703_196_fu_1317_p2 = (sub_ln703_182_reg_5410 - data_11_V_read12_reg_4808_pp0_iter4_reg); + +assign sub_ln703_197_fu_1321_p2 = (sub_ln703_183_fu_1250_p2 - data_11_V_read12_reg_4808_pp0_iter4_reg); + +assign sub_ln703_198_fu_1146_p2 = (add_ln703_269_fu_1069_p2 - data_11_V_read12_reg_4808_pp0_iter3_reg); + +assign sub_ln703_199_fu_1151_p2 = (sub_ln703_184_fu_1075_p2 - data_11_V_read12_reg_4808_pp0_iter3_reg); + +assign sub_ln703_200_fu_1326_p2 = (add_ln703_270_fu_1255_p2 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_201_fu_1331_p2 = (add_ln703_274_reg_5420 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_202_fu_1335_p2 = (sub_ln703_185_reg_5425 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_203_fu_1339_p2 = (add_ln703_275_fu_1260_p2 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_204_fu_1344_p2 = (add_ln703_277_fu_1264_p2 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_205_fu_1349_p2 = (add_ln703_279_fu_1268_p2 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_206_fu_1363_p2 = (sub_ln703_187_reg_5440 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_207_fu_1384_p2 = (sub_ln703_192_fu_1286_p2 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_208_fu_1389_p2 = (add_ln703_281_reg_5455 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_209_fu_1393_p2 = (add_ln703_283_reg_5460 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_210_fu_1402_p2 = (sub_ln703_193_fu_1291_p2 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_211_fu_1407_p2 = (add_ln703_285_fu_1300_p2 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_212_fu_1412_p2 = (add_ln703_286_fu_1305_p2 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_213_fu_1417_p2 = (sub_ln703_194_fu_1309_p2 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_214_fu_1422_p2 = (sub_ln703_195_fu_1313_p2 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_215_fu_1441_p2 = (sub_ln703_197_fu_1321_p2 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_216_fu_1446_p2 = (sub_ln703_198_reg_5465 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_217_fu_1450_p2 = (sub_ln703_199_reg_5470 - data_12_V_read13_reg_4778_pp0_iter4_reg); + +assign sub_ln703_218_fu_1784_p2 = (sub_ln703_200_reg_5515 - data_13_V_read14_reg_4745_pp0_iter5_reg); + +assign sub_ln703_219_fu_1788_p2 = (sub_ln703_203_reg_5520 - data_13_V_read14_reg_4745_pp0_iter5_reg); + +assign sub_ln703_220_fu_1459_p2 = (sub_ln703_204_fu_1344_p2 - data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign sub_ln703_221_fu_1792_p2 = (add_ln703_287_reg_5525 - data_13_V_read14_reg_4745_pp0_iter5_reg); + +assign sub_ln703_222_fu_1469_p2 = (add_ln703_289_fu_1359_p2 - data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign sub_ln703_223_fu_1479_p2 = (add_ln703_290_fu_1367_p2 - data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign sub_ln703_224_fu_1796_p2 = (add_ln703_291_reg_5530 - data_13_V_read14_reg_4745_pp0_iter5_reg); + +assign sub_ln703_225_fu_1484_p2 = (add_ln703_292_fu_1376_p2 - data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign sub_ln703_226_fu_1489_p2 = (add_ln703_293_fu_1380_p2 - data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign sub_ln703_227_fu_1800_p2 = (sub_ln703_207_reg_5535 - data_13_V_read14_reg_4745_pp0_iter5_reg); + +assign sub_ln703_228_fu_1499_p2 = (add_ln703_294_fu_1397_p2 - data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign sub_ln703_229_fu_1518_p2 = (sub_ln703_211_fu_1407_p2 - data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign sub_ln703_230_fu_1804_p2 = (sub_ln703_212_reg_5540 - data_13_V_read14_reg_4745_pp0_iter5_reg); + +assign sub_ln703_231_fu_1537_p2 = (add_ln703_295_fu_1427_p2 - data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign sub_ln703_232_fu_1542_p2 = (add_ln703_297_fu_1436_p2 - data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign sub_ln703_233_fu_1808_p2 = (sub_ln703_215_reg_5545 - data_13_V_read14_reg_4745_pp0_iter5_reg); + +assign sub_ln703_234_fu_1547_p2 = (sub_ln703_217_fu_1450_p2 - data_13_V_read14_reg_4745_pp0_iter4_reg); + +assign sub_ln703_235_fu_1812_p2 = (sub_ln703_218_fu_1784_p2 - data_14_V_read15_reg_4714_pp0_iter5_reg); + +assign sub_ln703_236_fu_1557_p2 = (add_ln703_298_fu_1454_p2 - data_14_V_read15_reg_4714_pp0_iter4_reg); + +assign sub_ln703_237_fu_1571_p2 = (sub_ln703_220_fu_1459_p2 - data_14_V_read15_reg_4714_pp0_iter4_reg); + +assign sub_ln703_238_fu_1576_p2 = (add_ln703_299_fu_1464_p2 - data_14_V_read15_reg_4714_pp0_iter4_reg); + +assign sub_ln703_239_fu_1817_p2 = (sub_ln703_221_fu_1792_p2 - data_14_V_read15_reg_4714_pp0_iter5_reg); + +assign sub_ln703_240_fu_1581_p2 = (sub_ln703_222_fu_1469_p2 - data_14_V_read15_reg_4714_pp0_iter4_reg); + +assign sub_ln703_241_fu_1586_p2 = (add_ln703_300_fu_1474_p2 - data_14_V_read15_reg_4714_pp0_iter4_reg); + +assign sub_ln703_242_fu_1596_p2 = (sub_ln703_225_fu_1484_p2 - data_14_V_read15_reg_4714_pp0_iter4_reg); + +assign sub_ln703_243_fu_1601_p2 = (sub_ln703_226_fu_1489_p2 - data_14_V_read15_reg_4714_pp0_iter4_reg); + +assign sub_ln703_244_fu_1827_p2 = (sub_ln703_227_fu_1800_p2 - data_14_V_read15_reg_4714_pp0_iter5_reg); + +assign sub_ln703_245_fu_1832_p2 = (add_ln703_301_reg_5550 - data_14_V_read15_reg_4714_pp0_iter5_reg); + +assign sub_ln703_246_fu_1193_p2 = (add_ln703_306_fu_1173_p2 - data_14_V_read15_reg_4714_pp0_iter3_reg); + +assign sub_ln703_247_fu_1836_p2 = (add_ln703_307_reg_5555 - data_14_V_read15_reg_4714_pp0_iter5_reg); + +assign sub_ln703_248_fu_1606_p2 = (add_ln703_310_fu_1513_p2 - data_14_V_read15_reg_4714_pp0_iter4_reg); + +assign sub_ln703_249_fu_1840_p2 = (sub_ln703_229_reg_5560 - data_14_V_read15_reg_4714_pp0_iter5_reg); + +assign sub_ln703_250_fu_1844_p2 = (sub_ln703_230_fu_1804_p2 - data_14_V_read15_reg_4714_pp0_iter5_reg); + +assign sub_ln703_251_fu_1611_p2 = (add_ln703_312_fu_1527_p2 - data_14_V_read15_reg_4714_pp0_iter4_reg); + +assign sub_ln703_252_fu_1616_p2 = (add_ln703_313_fu_1532_p2 - data_14_V_read15_reg_4714_pp0_iter4_reg); + +assign sub_ln703_253_fu_1621_p2 = (sub_ln703_231_fu_1537_p2 - data_14_V_read15_reg_4714_pp0_iter4_reg); + +assign sub_ln703_254_fu_1626_p2 = (sub_ln703_232_fu_1542_p2 - data_14_V_read15_reg_4714_pp0_iter4_reg); + +assign sub_ln703_255_fu_1849_p2 = (sub_ln703_233_fu_1808_p2 - data_14_V_read15_reg_4714_pp0_iter5_reg); + +assign sub_ln703_256_fu_1631_p2 = (add_ln703_315_fu_1552_p2 - data_15_V_read16_reg_4682_pp0_iter4_reg); + +assign sub_ln703_257_fu_1641_p2 = (add_ln703_318_fu_1566_p2 - data_15_V_read16_reg_4682_pp0_iter4_reg); + +assign sub_ln703_258_fu_1854_p2 = (sub_ln703_237_reg_5565 - data_15_V_read16_reg_4682_pp0_iter5_reg); + +assign sub_ln703_259_fu_1858_p2 = (sub_ln703_238_reg_5570 - data_15_V_read16_reg_4682_pp0_iter5_reg); + +assign sub_ln703_260_fu_1862_p2 = (sub_ln703_239_fu_1817_p2 - data_15_V_read16_reg_4682_pp0_iter5_reg); + +assign sub_ln703_261_fu_1646_p2 = (sub_ln703_240_fu_1581_p2 - data_15_V_read16_reg_4682_pp0_iter4_reg); + +assign sub_ln703_262_fu_1651_p2 = (sub_ln703_241_fu_1586_p2 - data_15_V_read16_reg_4682_pp0_iter4_reg); + +assign sub_ln703_263_fu_1671_p2 = (add_ln703_319_fu_1591_p2 - data_15_V_read16_reg_4682_pp0_iter4_reg); + +assign sub_ln703_264_fu_1867_p2 = (add_ln703_320_fu_1822_p2 - data_15_V_read16_reg_4682_pp0_iter5_reg); + +assign sub_ln703_265_fu_1676_p2 = (sub_ln703_242_fu_1596_p2 - data_15_V_read16_reg_4682_pp0_iter4_reg); + +assign sub_ln703_266_fu_1681_p2 = (sub_ln703_243_fu_1601_p2 - data_15_V_read16_reg_4682_pp0_iter4_reg); + +assign sub_ln703_267_fu_1872_p2 = (sub_ln703_245_fu_1832_p2 - data_15_V_read16_reg_4682_pp0_iter5_reg); + +assign sub_ln703_268_fu_1691_p2 = (sub_ln703_246_reg_5501 - data_15_V_read16_reg_4682_pp0_iter4_reg); + +assign sub_ln703_269_fu_1877_p2 = (sub_ln703_247_fu_1836_p2 - data_15_V_read16_reg_4682_pp0_iter5_reg); + +assign sub_ln703_270_fu_1695_p2 = (sub_ln703_248_fu_1606_p2 - data_15_V_read16_reg_4682_pp0_iter4_reg); + +assign sub_ln703_271_fu_1882_p2 = (sub_ln703_249_fu_1840_p2 - data_15_V_read16_reg_4682_pp0_iter5_reg); + +assign sub_ln703_272_fu_1700_p2 = (sub_ln703_251_fu_1611_p2 - data_15_V_read16_reg_4682_pp0_iter4_reg); + +assign sub_ln703_273_fu_1896_p2 = (sub_ln703_253_reg_5580 - data_15_V_read16_reg_4682_pp0_iter5_reg); + +assign sub_ln703_274_fu_1904_p2 = (sub_ln703_255_fu_1849_p2 - data_15_V_read16_reg_4682_pp0_iter5_reg); + +assign sub_ln703_275_fu_1909_p2 = (add_ln703_321_reg_5590 - data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign sub_ln703_276_fu_1918_p2 = (sub_ln703_260_fu_1862_p2 - data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign sub_ln703_277_fu_1927_p2 = (sub_ln703_262_reg_5605 - data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign sub_ln703_278_fu_1735_p2 = (add_ln703_325_fu_1665_p2 - data_16_V_read17_reg_4650_pp0_iter4_reg); + +assign sub_ln703_279_fu_1931_p2 = (sub_ln703_263_reg_5610 - data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign sub_ln703_280_fu_1935_p2 = (sub_ln703_265_reg_5615 - data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign sub_ln703_281_fu_1957_p2 = (add_ln703_326_reg_5625 - data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign sub_ln703_282_fu_1961_p2 = (sub_ln703_269_fu_1877_p2 - data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign sub_ln703_283_fu_1975_p2 = (add_ln703_327_fu_1887_p2 - data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign sub_ln703_284_fu_1980_p2 = (sub_ln703_272_reg_5635 - data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign sub_ln703_285_fu_1984_p2 = (add_ln703_328_fu_1892_p2 - data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign sub_ln703_286_fu_1989_p2 = (add_ln703_330_reg_5640 - data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign sub_ln703_287_fu_1998_p2 = (add_ln703_331_fu_1900_p2 - data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign sub_ln703_288_fu_2003_p2 = (sub_ln703_274_fu_1904_p2 - data_16_V_read17_reg_4650_pp0_iter5_reg); + +assign sub_ln703_289_fu_1750_p2 = (add_ln703_333_fu_1720_p2 - data_16_V_read17_reg_4650_pp0_iter4_reg); + +assign sub_ln703_290_fu_1755_p2 = (add_ln703_334_fu_1725_p2 - data_16_V_read17_reg_4650_pp0_iter4_reg); + +assign sub_ln703_291_fu_2008_p2 = (add_ln703_335_reg_5645 - data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign sub_ln703_292_fu_2012_p2 = (sub_ln703_275_fu_1909_p2 - data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign sub_ln703_293_fu_2036_p2 = (add_ln703_336_fu_1913_p2 - data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign sub_ln703_294_fu_2405_p2 = (sub_ln703_276_reg_5728 - data_17_V_read_8_reg_4621_pp0_iter6_reg); + +assign sub_ln703_295_fu_2041_p2 = (add_ln703_337_fu_1923_p2 - data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign sub_ln703_296_fu_2046_p2 = (sub_ln703_277_fu_1927_p2 - data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign sub_ln703_297_fu_2055_p2 = (sub_ln703_279_fu_1931_p2 - data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign sub_ln703_298_fu_2065_p2 = (sub_ln703_280_fu_1935_p2 - data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign sub_ln703_299_fu_2070_p2 = (add_ln703_338_fu_1939_p2 - data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign sub_ln703_300_fu_2075_p2 = (add_ln703_342_fu_1952_p2 - data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign sub_ln703_301_fu_2085_p2 = (add_ln703_343_reg_5660 - data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign sub_ln703_302_fu_2089_p2 = (sub_ln703_282_fu_1961_p2 - data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign sub_ln703_303_fu_2094_p2 = (add_ln703_344_fu_1966_p2 - data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign sub_ln703_304_fu_2099_p2 = (add_ln703_345_fu_1970_p2 - data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign sub_ln703_305_fu_2104_p2 = (sub_ln703_286_fu_1989_p2 - data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign sub_ln703_306_fu_2109_p2 = (add_ln703_346_fu_1993_p2 - data_17_V_read_8_reg_4621_pp0_iter5_reg); + +assign sub_ln703_307_fu_2133_p2 = (sub_ln703_291_fu_2008_p2 - data_18_V_read_7_reg_4594_pp0_iter5_reg); + +assign sub_ln703_308_fu_2143_p2 = (add_ln703_348_fu_2017_p2 - data_18_V_read_7_reg_4594_pp0_iter5_reg); + +assign sub_ln703_309_fu_2148_p2 = (add_ln703_351_fu_2030_p2 - data_18_V_read_7_reg_4594_pp0_iter5_reg); + +assign sub_ln703_310_fu_2168_p2 = (sub_ln703_296_fu_2046_p2 - data_18_V_read_7_reg_4594_pp0_iter5_reg); + +assign sub_ln703_311_fu_2173_p2 = (add_ln703_352_fu_2051_p2 - data_18_V_read_7_reg_4594_pp0_iter5_reg); + +assign sub_ln703_312_fu_2409_p2 = (add_ln703_353_reg_5743 - data_18_V_read_7_reg_4594_pp0_iter6_reg); + +assign sub_ln703_313_fu_2413_p2 = (sub_ln703_300_reg_5748 - data_18_V_read_7_reg_4594_pp0_iter6_reg); + +assign sub_ln703_314_fu_2417_p2 = (add_ln703_354_reg_5753 - data_18_V_read_7_reg_4594_pp0_iter6_reg); + +assign sub_ln703_315_fu_2188_p2 = (sub_ln703_301_fu_2085_p2 - data_18_V_read_7_reg_4594_pp0_iter5_reg); + +assign sub_ln703_316_fu_2421_p2 = (sub_ln703_302_reg_5758 - data_18_V_read_7_reg_4594_pp0_iter6_reg); + +assign sub_ln703_317_fu_2425_p2 = (sub_ln703_304_reg_5763 - data_18_V_read_7_reg_4594_pp0_iter6_reg); + +assign sub_ln703_318_fu_2203_p2 = (sub_ln703_306_fu_2109_p2 - data_18_V_read_7_reg_4594_pp0_iter5_reg); + +assign sub_ln703_319_fu_2208_p2 = (add_ln703_355_fu_2114_p2 - data_18_V_read_7_reg_4594_pp0_iter5_reg); + +assign sub_ln703_320_fu_2433_p2 = (add_ln703_359_reg_5768 - data_19_V_read_7_reg_4567_pp0_iter6_reg); + +assign sub_ln703_321_fu_2218_p2 = (add_ln703_360_fu_2138_p2 - data_19_V_read_7_reg_4567_pp0_iter5_reg); + +assign sub_ln703_322_fu_2223_p2 = (sub_ln703_308_fu_2143_p2 - data_19_V_read_7_reg_4567_pp0_iter5_reg); + +assign sub_ln703_323_fu_2233_p2 = (add_ln703_362_fu_2158_p2 - data_19_V_read_7_reg_4567_pp0_iter5_reg); + +assign sub_ln703_324_fu_2238_p2 = (add_ln703_363_fu_2163_p2 - data_19_V_read_7_reg_4567_pp0_iter5_reg); + +assign sub_ln703_325_fu_2243_p2 = (sub_ln703_310_fu_2168_p2 - data_19_V_read_7_reg_4567_pp0_iter5_reg); + +assign sub_ln703_326_fu_2441_p2 = (sub_ln703_311_reg_5778 - data_19_V_read_7_reg_4567_pp0_iter6_reg); + +assign sub_ln703_327_fu_2248_p2 = (add_ln703_364_fu_2178_p2 - data_19_V_read_7_reg_4567_pp0_iter5_reg); + +assign sub_ln703_328_fu_2253_p2 = (add_ln703_365_fu_2183_p2 - data_19_V_read_7_reg_4567_pp0_iter5_reg); + +assign sub_ln703_329_fu_2450_p2 = (sub_ln703_314_fu_2417_p2 - data_19_V_read_7_reg_4567_pp0_iter6_reg); + +assign sub_ln703_330_fu_2455_p2 = (sub_ln703_316_fu_2421_p2 - data_19_V_read_7_reg_4567_pp0_iter6_reg); + +assign sub_ln703_331_fu_2258_p2 = (add_ln703_366_fu_2193_p2 - data_19_V_read_7_reg_4567_pp0_iter5_reg); + +assign sub_ln703_332_fu_2273_p2 = (add_ln703_367_fu_2198_p2 - data_19_V_read_7_reg_4567_pp0_iter5_reg); + +assign sub_ln703_333_fu_2460_p2 = (sub_ln703_318_reg_5783 - data_19_V_read_7_reg_4567_pp0_iter6_reg); + +assign sub_ln703_334_fu_2464_p2 = (add_ln703_368_fu_2429_p2 - data_19_V_read_7_reg_4567_pp0_iter6_reg); + +assign sub_ln703_335_fu_2302_p2 = (add_ln703_369_fu_2213_p2 - data_20_V_read21_reg_4539_pp0_iter5_reg); + +assign sub_ln703_336_fu_2469_p2 = (sub_ln703_321_reg_5788 - data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign sub_ln703_337_fu_2473_p2 = (add_ln703_370_fu_2437_p2 - data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign sub_ln703_338_fu_2478_p2 = (add_ln703_372_reg_5793 - data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign sub_ln703_339_fu_2482_p2 = (sub_ln703_324_reg_5803 - data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign sub_ln703_340_fu_2495_p2 = (sub_ln703_327_reg_5813 - data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign sub_ln703_341_fu_2504_p2 = (add_ln703_373_fu_2445_p2 - data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign sub_ln703_342_fu_2509_p2 = (sub_ln703_329_fu_2450_p2 - data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign sub_ln703_343_fu_2312_p2 = (add_ln703_375_fu_2268_p2 - data_20_V_read21_reg_4539_pp0_iter5_reg); + +assign sub_ln703_344_fu_2523_p2 = (add_ln703_377_reg_5833 - data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign sub_ln703_345_fu_2532_p2 = (add_ln703_379_reg_5838 - data_20_V_read21_reg_4539_pp0_iter6_reg); + +assign sub_ln703_346_fu_2332_p2 = (add_ln703_380_fu_2297_p2 - data_20_V_read21_reg_4539_pp0_iter5_reg); + +assign sub_ln703_347_fu_2536_p2 = (sub_ln703_335_reg_5843 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_348_fu_2545_p2 = (add_ln703_381_reg_5848 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_349_fu_2549_p2 = (sub_ln703_337_fu_2473_p2 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_350_fu_2554_p2 = (sub_ln703_338_fu_2478_p2 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_351_fu_2574_p2 = (sub_ln703_339_fu_2482_p2 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_352_fu_2579_p2 = (add_ln703_382_fu_2486_p2 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_353_fu_2584_p2 = (add_ln703_383_fu_2490_p2 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_354_fu_2589_p2 = (sub_ln703_340_fu_2495_p2 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_355_fu_2594_p2 = (add_ln703_385_fu_2499_p2 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_356_fu_2603_p2 = (sub_ln703_341_fu_2504_p2 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_357_fu_2608_p2 = (sub_ln703_342_fu_2509_p2 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_358_fu_2613_p2 = (add_ln703_386_fu_2514_p2 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_359_fu_2618_p2 = (add_ln703_387_fu_2518_p2 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_360_fu_2627_p2 = (add_ln703_390_reg_5858 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_361_fu_2636_p2 = (add_ln703_391_fu_2527_p2 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_362_fu_2641_p2 = (sub_ln703_346_reg_5863 - data_21_V_read22_reg_4512_pp0_iter6_reg); + +assign sub_ln703_363_fu_2660_p2 = (add_ln703_392_fu_2540_p2 - data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign sub_ln703_364_fu_2665_p2 = (sub_ln703_348_fu_2545_p2 - data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign sub_ln703_365_fu_2670_p2 = (sub_ln703_350_fu_2554_p2 - data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign sub_ln703_366_fu_2684_p2 = (add_ln703_396_fu_2568_p2 - data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign sub_ln703_367_fu_2689_p2 = (sub_ln703_351_fu_2574_p2 - data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign sub_ln703_368_fu_2694_p2 = (sub_ln703_352_fu_2579_p2 - data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign sub_ln703_369_fu_2699_p2 = (sub_ln703_353_fu_2584_p2 - data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign sub_ln703_370_fu_2714_p2 = (add_ln703_397_fu_2599_p2 - data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign sub_ln703_371_fu_2719_p2 = (add_ln703_400_reg_5868 - data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign sub_ln703_372_fu_2985_p2 = (sub_ln703_356_reg_5921 - data_22_V_read23_reg_4483_pp0_iter7_reg); + +assign sub_ln703_373_fu_2723_p2 = (sub_ln703_358_fu_2613_p2 - data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign sub_ln703_374_fu_2728_p2 = (sub_ln703_359_fu_2618_p2 - data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign sub_ln703_375_fu_2747_p2 = (add_ln703_401_fu_2623_p2 - data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign sub_ln703_376_fu_2752_p2 = (sub_ln703_360_fu_2627_p2 - data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign sub_ln703_377_fu_2989_p2 = (add_ln703_402_reg_5931 - data_22_V_read23_reg_4483_pp0_iter7_reg); + +assign sub_ln703_378_fu_2776_p2 = (sub_ln703_362_fu_2641_p2 - data_22_V_read23_reg_4483_pp0_iter6_reg); + +assign sub_ln703_379_fu_2781_p2 = (add_ln703_405_fu_2650_p2 - data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign sub_ln703_380_fu_2786_p2 = (add_ln703_406_fu_2655_p2 - data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign sub_ln703_381_fu_2791_p2 = (sub_ln703_363_fu_2660_p2 - data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign sub_ln703_382_fu_2796_p2 = (sub_ln703_364_fu_2665_p2 - data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign sub_ln703_383_fu_2801_p2 = (add_ln703_408_fu_2679_p2 - data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign sub_ln703_384_fu_2997_p2 = (sub_ln703_366_reg_5941 - data_23_V_read24_reg_4451_pp0_iter7_reg); + +assign sub_ln703_385_fu_2811_p2 = (sub_ln703_368_fu_2694_p2 - data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign sub_ln703_386_fu_2816_p2 = (add_ln703_409_fu_2704_p2 - data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign sub_ln703_387_fu_3005_p2 = (add_ln703_410_reg_5951 - data_23_V_read24_reg_4451_pp0_iter7_reg); + +assign sub_ln703_388_fu_2821_p2 = (add_ln703_413_reg_5873 - data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign sub_ln703_389_fu_2839_p2 = (sub_ln703_371_fu_2719_p2 - data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign sub_ln703_390_fu_3009_p2 = (sub_ln703_372_fu_2985_p2 - data_23_V_read24_reg_4451_pp0_iter7_reg); + +assign sub_ln703_391_fu_2844_p2 = (add_ln703_415_reg_5878 - data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign sub_ln703_392_fu_2848_p2 = (sub_ln703_373_fu_2723_p2 - data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign sub_ln703_393_fu_3018_p2 = (add_ln703_418_reg_5961 - data_23_V_read24_reg_4451_pp0_iter7_reg); + +assign sub_ln703_394_fu_3022_p2 = (sub_ln703_375_reg_5966 - data_23_V_read24_reg_4451_pp0_iter7_reg); + +assign sub_ln703_395_fu_2853_p2 = (sub_ln703_376_fu_2752_p2 - data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign sub_ln703_396_fu_2858_p2 = (add_ln703_420_fu_2761_p2 - data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign sub_ln703_397_fu_2863_p2 = (add_ln703_422_fu_2771_p2 - data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign sub_ln703_398_fu_3026_p2 = (sub_ln703_377_fu_2989_p2 - data_23_V_read24_reg_4451_pp0_iter7_reg); + +assign sub_ln703_399_fu_3031_p2 = (add_ln703_423_fu_2993_p2 - data_23_V_read24_reg_4451_pp0_iter7_reg); + +assign sub_ln703_400_fu_2868_p2 = (sub_ln703_378_fu_2776_p2 - data_23_V_read24_reg_4451_pp0_iter6_reg); + +assign sub_ln703_401_fu_3040_p2 = (sub_ln703_381_reg_5976 - data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign sub_ln703_402_fu_2878_p2 = (sub_ln703_382_fu_2796_p2 - data_24_V_read25_reg_4421_pp0_iter6_reg); + +assign sub_ln703_403_fu_3044_p2 = (sub_ln703_384_fu_2997_p2 - data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign sub_ln703_404_fu_3049_p2 = (add_ln703_424_reg_5981 - data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign sub_ln703_405_fu_3057_p2 = (add_ln703_425_fu_3001_p2 - data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign sub_ln703_406_fu_3062_p2 = (sub_ln703_386_reg_5991 - data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign sub_ln703_407_fu_3066_p2 = (sub_ln703_387_fu_3005_p2 - data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign sub_ln703_408_fu_2893_p2 = (sub_ln703_388_fu_2821_p2 - data_24_V_read25_reg_4421_pp0_iter6_reg); + +assign sub_ln703_409_fu_2898_p2 = (add_ln703_431_fu_2834_p2 - data_24_V_read25_reg_4421_pp0_iter6_reg); + +assign sub_ln703_410_fu_3071_p2 = (sub_ln703_389_reg_5996 - data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign sub_ln703_411_fu_2903_p2 = (sub_ln703_391_fu_2844_p2 - data_24_V_read25_reg_4421_pp0_iter6_reg); + +assign sub_ln703_412_fu_3080_p2 = (sub_ln703_392_reg_6001 - data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign sub_ln703_413_fu_3084_p2 = (add_ln703_432_fu_3014_p2 - data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign sub_ln703_414_fu_3089_p2 = (sub_ln703_393_fu_3018_p2 - data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign sub_ln703_415_fu_3094_p2 = (sub_ln703_394_fu_3022_p2 - data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign sub_ln703_416_fu_2923_p2 = (sub_ln703_396_fu_2858_p2 - data_24_V_read25_reg_4421_pp0_iter6_reg); + +assign sub_ln703_417_fu_3103_p2 = (sub_ln703_399_fu_3031_p2 - data_24_V_read25_reg_4421_pp0_iter7_reg); + +assign sub_ln703_418_fu_3108_p2 = (add_ln703_433_fu_3036_p2 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_419_fu_3113_p2 = (add_ln703_434_reg_6011 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_420_fu_3117_p2 = (sub_ln703_401_fu_3040_p2 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_421_fu_3126_p2 = (add_ln703_436_reg_6021 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_422_fu_3130_p2 = (sub_ln703_403_fu_3044_p2 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_423_fu_3135_p2 = (sub_ln703_404_fu_3049_p2 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_424_fu_3140_p2 = (add_ln703_437_fu_3053_p2 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_425_fu_3145_p2 = (sub_ln703_406_fu_3062_p2 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_426_fu_2938_p2 = (add_ln703_438_fu_2888_p2 - data_25_V_read26_reg_4391_pp0_iter6_reg); + +assign sub_ln703_427_fu_3154_p2 = (sub_ln703_409_reg_6031 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_428_fu_3163_p2 = (add_ln703_439_fu_3075_p2 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_429_fu_3177_p2 = (sub_ln703_411_reg_6036 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_430_fu_3181_p2 = (add_ln703_442_reg_6041 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_431_fu_3185_p2 = (sub_ln703_412_fu_3080_p2 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_432_fu_3190_p2 = (sub_ln703_416_reg_6046 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_433_fu_3194_p2 = (add_ln703_443_fu_3099_p2 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_434_fu_3199_p2 = (sub_ln703_417_fu_3103_p2 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_435_fu_3204_p2 = (add_ln703_444_reg_6051 - data_25_V_read26_reg_4391_pp0_iter7_reg); + +assign sub_ln703_436_fu_3208_p2 = (sub_ln703_418_fu_3108_p2 - data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign sub_ln703_437_fu_3213_p2 = (sub_ln703_419_fu_3113_p2 - data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign sub_ln703_438_fu_3223_p2 = (add_ln703_445_fu_3122_p2 - data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign sub_ln703_439_fu_3228_p2 = (add_ln703_447_reg_6056 - data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign sub_ln703_440_fu_3247_p2 = (sub_ln703_425_fu_3145_p2 - data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign sub_ln703_441_fu_3252_p2 = (sub_ln703_426_reg_6061 - data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign sub_ln703_442_fu_3256_p2 = (add_ln703_448_fu_3150_p2 - data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign sub_ln703_443_fu_3261_p2 = (sub_ln703_427_fu_3154_p2 - data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign sub_ln703_444_fu_3266_p2 = (add_ln703_449_fu_3158_p2 - data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign sub_ln703_445_fu_3271_p2 = (add_ln703_452_fu_3172_p2 - data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign sub_ln703_446_fu_3276_p2 = (sub_ln703_429_fu_3177_p2 - data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign sub_ln703_447_fu_3298_p2 = (sub_ln703_432_fu_3190_p2 - data_26_V_read27_reg_4365_pp0_iter7_reg); + +assign sub_ln703_448_fu_3308_p2 = (sub_ln703_436_fu_3208_p2 - data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign sub_ln703_449_fu_3313_p2 = (sub_ln703_437_fu_3213_p2 - data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign sub_ln703_450_fu_3318_p2 = (add_ln703_453_fu_3218_p2 - data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign sub_ln703_451_fu_3343_p2 = (add_ln703_454_fu_3232_p2 - data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign sub_ln703_452_fu_3348_p2 = (add_ln703_456_fu_3241_p2 - data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign sub_ln703_453_fu_3353_p2 = (sub_ln703_440_fu_3247_p2 - data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign sub_ln703_454_fu_3368_p2 = (sub_ln703_441_fu_3252_p2 - data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign sub_ln703_455_fu_3373_p2 = (sub_ln703_444_fu_3266_p2 - data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign sub_ln703_456_fu_3388_p2 = (add_ln703_457_fu_3281_p2 - data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign sub_ln703_457_fu_3393_p2 = (add_ln703_458_fu_3286_p2 - data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign sub_ln703_458_fu_3408_p2 = (add_ln703_459_fu_3292_p2 - data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign sub_ln703_459_fu_3418_p2 = (add_ln703_460_fu_3303_p2 - data_27_V_read_8_reg_4342_pp0_iter7_reg); + +assign sub_ln703_460_fu_3535_p2 = (sub_ln703_450_reg_6123 - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_461_fu_3438_p2 = (add_ln703_461_fu_3323_p2 - data_28_V_read_7_reg_4313_pp0_iter7_reg); + +assign sub_ln703_462_fu_3539_p2 = (add_ln703_463_reg_6128 - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_463_fu_3543_p2 = (add_ln703_464_reg_6133 - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_464_fu_3547_p2 = (add_ln703_465_reg_6138 - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_465_fu_3551_p2 = (sub_ln703_451_reg_6143 - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_466_fu_3563_p2 = (add_ln703_467_reg_6158 - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_467_fu_3567_p2 = (sub_ln703_454_reg_6163 - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_468_fu_3575_p2 = (add_ln703_468_reg_6173 - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_469_fu_3463_p2 = (add_ln703_469_fu_3383_p2 - data_28_V_read_7_reg_4313_pp0_iter7_reg); + +assign sub_ln703_470_fu_3579_p2 = (sub_ln703_456_reg_6178 - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_471_fu_3583_p2 = (sub_ln703_457_reg_6183 - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_472_fu_3587_p2 = (add_ln703_471_reg_6188 - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_473_fu_3591_p2 = (sub_ln703_458_reg_6193 - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_474_fu_3482_p2 = (add_ln703_472_fu_3413_p2 - data_28_V_read_7_reg_4313_pp0_iter7_reg); + +assign sub_ln703_475_fu_3599_p2 = (sub_ln703_459_reg_6198 - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_476_fu_3603_p2 = (add_ln703_475_reg_6203 - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_477_fu_3607_p2 = (add_ln703_476_fu_3531_p2 - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_478_fu_3612_p2 = (add_ln703_480_reg_6072_pp0_iter8_reg - data_28_V_read_7_reg_4313_pp0_iter8_reg); + +assign sub_ln703_479_fu_3621_p2 = (sub_ln703_462_fu_3539_p2 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_480_fu_3626_p2 = (sub_ln703_463_fu_3543_p2 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_481_fu_3636_p2 = (add_ln703_483_reg_6213 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_482_fu_3640_p2 = (sub_ln703_465_fu_3551_p2 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_483_fu_3645_p2 = (add_ln703_484_fu_3555_p2 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_484_fu_3650_p2 = (add_ln703_485_fu_3559_p2 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_485_fu_3660_p2 = (sub_ln703_467_fu_3567_p2 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_486_fu_3507_p2 = (add_ln703_486_fu_3453_p2 - data_29_V_read_7_reg_4279_pp0_iter7_reg); + +assign sub_ln703_487_fu_3512_p2 = (add_ln703_487_fu_3458_p2 - data_29_V_read_7_reg_4279_pp0_iter7_reg); + +assign sub_ln703_488_fu_3665_p2 = (add_ln703_488_fu_3571_p2 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_489_fu_3670_p2 = (sub_ln703_468_fu_3575_p2 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_490_fu_3675_p2 = (sub_ln703_469_reg_6218 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_491_fu_3517_p2 = (add_ln703_490_fu_3473_p2 - data_29_V_read_7_reg_4279_pp0_iter7_reg); + +assign sub_ln703_492_fu_3679_p2 = (sub_ln703_470_fu_3579_p2 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_493_fu_3684_p2 = (sub_ln703_471_fu_3583_p2 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_494_fu_3689_p2 = (sub_ln703_472_fu_3587_p2 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_495_fu_3694_p2 = (sub_ln703_473_fu_3591_p2 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_496_fu_3699_p2 = (add_ln703_493_fu_3595_p2 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_497_fu_3704_p2 = (sub_ln703_474_reg_6229 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_498_fu_3718_p2 = (sub_ln703_477_fu_3607_p2 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_499_fu_3723_p2 = (sub_ln703_478_fu_3612_p2 - data_29_V_read_7_reg_4279_pp0_iter8_reg); + +assign sub_ln703_500_fu_3522_p2 = (add_ln703_495_fu_3492_p2 - data_29_V_read_7_reg_4279_pp0_iter7_reg); + +assign sub_ln703_501_fu_3728_p2 = (add_ln703_497_reg_6239 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_502_fu_3732_p2 = (add_ln703_498_fu_3616_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_503_fu_3737_p2 = (sub_ln703_479_fu_3621_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_504_fu_3742_p2 = (sub_ln703_480_fu_3626_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_505_fu_3747_p2 = (add_ln703_499_fu_3631_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_506_fu_3752_p2 = (sub_ln703_482_fu_3640_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_507_fu_3762_p2 = (sub_ln703_484_fu_3650_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_508_fu_3767_p2 = (add_ln703_500_fu_3655_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_509_fu_3772_p2 = (sub_ln703_485_fu_3660_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_510_fu_3781_p2 = (sub_ln703_487_reg_6249 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_511_fu_3790_p2 = (sub_ln703_489_fu_3670_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_512_fu_3804_p2 = (sub_ln703_493_fu_3684_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_513_fu_3809_p2 = (sub_ln703_494_fu_3689_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_514_fu_3814_p2 = (sub_ln703_495_fu_3694_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_515_fu_3819_p2 = (sub_ln703_496_fu_3699_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_516_fu_3824_p2 = (add_ln703_501_fu_3708_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_517_fu_3829_p2 = (add_ln703_502_fu_3713_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_518_fu_3834_p2 = (sub_ln703_499_fu_3723_p2 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_519_fu_3839_p2 = (sub_ln703_500_reg_6259 - data_30_V_read31_reg_4250_pp0_iter8_reg); + +assign sub_ln703_73_fu_286_p2 = (data_0_V_read_int_reg - data_1_V_read_int_reg); + +assign sub_ln703_74_fu_292_p2 = (sub_ln703_reg_5046 - data_2_V_read_9_reg_5035); + +assign sub_ln703_75_fu_296_p2 = (add_ln703_reg_5052 - data_2_V_read_9_reg_5035); + +assign sub_ln703_76_fu_300_p2 = (sub_ln703_73_reg_5059 - data_2_V_read_9_reg_5035); + +assign sub_ln703_77_fu_308_p2 = (data_2_V_read_9_reg_5035 - add_ln703_reg_5052); + +assign sub_ln703_78_fu_361_p2 = (sub_ln703_76_reg_5071_pp0_iter2_reg - data_3_V_read_9_reg_5019_pp0_iter2_reg); + +assign sub_ln703_79_fu_337_p2 = (sub_ln703_77_reg_5084 - data_3_V_read_9_reg_5019_pp0_iter1_reg); + +assign sub_ln703_80_fu_365_p2 = (add_ln703_201_reg_5090_pp0_iter2_reg - data_3_V_read_9_reg_5019_pp0_iter2_reg); + +assign sub_ln703_81_fu_369_p2 = (add_ln703_202_reg_5096_pp0_iter2_reg - data_3_V_read_9_reg_5019_pp0_iter2_reg); + +assign sub_ln703_82_fu_373_p2 = (data_3_V_read_9_reg_5019_pp0_iter2_reg - add_ln703_200_reg_5077_pp0_iter2_reg); + +assign sub_ln703_83_fu_377_p2 = (add_ln703_200_reg_5077_pp0_iter2_reg - data_3_V_read_9_reg_5019_pp0_iter2_reg); + +assign sub_ln703_84_fu_381_p2 = (sub_ln703_74_reg_5065_pp0_iter2_reg - data_3_V_read_9_reg_5019_pp0_iter2_reg); + +assign sub_ln703_85_fu_385_p2 = (add_ln703_203_reg_5113 - data_4_V_read_9_reg_4998_pp0_iter2_reg); + +assign sub_ln703_86_fu_389_p2 = (add_ln703_204_reg_5101_pp0_iter2_reg - data_4_V_read_9_reg_4998_pp0_iter2_reg); + +assign sub_ln703_87_fu_393_p2 = (sub_ln703_78_fu_361_p2 - data_4_V_read_9_reg_4998_pp0_iter2_reg); + +assign sub_ln703_88_fu_398_p2 = (data_4_V_read_9_reg_4998_pp0_iter2_reg - add_ln703_205_reg_5119); + +assign sub_ln703_89_fu_402_p2 = (sub_ln703_79_reg_5125 - data_4_V_read_9_reg_4998_pp0_iter2_reg); + +assign sub_ln703_90_fu_406_p2 = (sub_ln703_80_fu_365_p2 - data_4_V_read_9_reg_4998_pp0_iter2_reg); + +assign sub_ln703_91_fu_411_p2 = (sub_ln703_81_fu_369_p2 - data_4_V_read_9_reg_4998_pp0_iter2_reg); + +assign sub_ln703_92_fu_437_p2 = (sub_ln703_84_fu_381_p2 - data_4_V_read_9_reg_4998_pp0_iter2_reg); + +assign sub_ln703_93_fu_442_p2 = (add_ln703_206_reg_5131 - data_4_V_read_9_reg_4998_pp0_iter2_reg); + +assign sub_ln703_94_fu_446_p2 = (sub_ln703_86_fu_389_p2 - data_5_V_read_8_reg_4969_pp0_iter2_reg); + +assign sub_ln703_95_fu_451_p2 = (sub_ln703_87_fu_393_p2 - data_5_V_read_8_reg_4969_pp0_iter2_reg); + +assign sub_ln703_96_fu_456_p2 = (sub_ln703_88_fu_398_p2 - data_5_V_read_8_reg_4969_pp0_iter2_reg); + +assign sub_ln703_97_fu_609_p2 = (sub_ln703_91_reg_5172 - data_5_V_read_8_reg_4969_pp0_iter3_reg); + +assign sub_ln703_98_fu_466_p2 = (add_ln703_208_reg_5137 - data_5_V_read_8_reg_4969_pp0_iter2_reg); + +assign sub_ln703_99_fu_613_p2 = (data_5_V_read_8_reg_4969_pp0_iter3_reg - add_ln703_209_reg_5178); + +assign sub_ln703_fu_274_p2 = (data_1_V_read_int_reg - data_0_V_read_int_reg); + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2 +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s ( + ap_clk, + ap_rst, + data_0_V_read, + data_1_V_read, + data_2_V_read, + data_3_V_read, + data_4_V_read, + data_5_V_read, + data_6_V_read, + data_7_V_read, + data_8_V_read, + data_9_V_read, + data_10_V_read, + data_11_V_read, + data_12_V_read, + data_13_V_read, + data_14_V_read, + data_15_V_read, + data_16_V_read, + data_17_V_read, + data_18_V_read, + data_19_V_read, + data_20_V_read, + data_21_V_read, + data_22_V_read, + data_23_V_read, + data_24_V_read, + data_25_V_read, + data_26_V_read, + data_27_V_read, + data_28_V_read, + data_29_V_read, + data_30_V_read, + data_31_V_read, + data_32_V_read, + data_33_V_read, + data_34_V_read, + data_35_V_read, + data_36_V_read, + data_37_V_read, + data_38_V_read, + data_39_V_read, + data_40_V_read, + data_41_V_read, + data_42_V_read, + data_43_V_read, + data_44_V_read, + data_45_V_read, + data_46_V_read, + data_47_V_read, + data_48_V_read, + data_49_V_read, + data_50_V_read, + data_51_V_read, + data_52_V_read, + data_53_V_read, + data_54_V_read, + data_55_V_read, + data_56_V_read, + data_57_V_read, + data_58_V_read, + data_59_V_read, + data_60_V_read, + data_61_V_read, + data_62_V_read, + data_63_V_read, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3, + ap_return_4, + ap_return_5, + ap_return_6, + ap_return_7, + ap_return_8, + ap_return_9, + ap_return_10, + ap_return_11, + ap_return_12, + ap_return_13, + ap_return_14, + ap_return_15, + ap_return_16, + ap_return_17, + ap_return_18, + ap_return_19, + ap_return_20, + ap_return_21, + ap_return_22, + ap_return_23, + ap_return_24, + ap_return_25, + ap_return_26, + ap_return_27, + ap_return_28, + ap_return_29, + ap_return_30, + ap_return_31, + ap_ce +); + + +input ap_clk; +input ap_rst; +input [15:0] data_0_V_read; +input [15:0] data_1_V_read; +input [15:0] data_2_V_read; +input [15:0] data_3_V_read; +input [15:0] data_4_V_read; +input [15:0] data_5_V_read; +input [15:0] data_6_V_read; +input [15:0] data_7_V_read; +input [15:0] data_8_V_read; +input [15:0] data_9_V_read; +input [15:0] data_10_V_read; +input [15:0] data_11_V_read; +input [15:0] data_12_V_read; +input [15:0] data_13_V_read; +input [15:0] data_14_V_read; +input [15:0] data_15_V_read; +input [15:0] data_16_V_read; +input [15:0] data_17_V_read; +input [15:0] data_18_V_read; +input [15:0] data_19_V_read; +input [15:0] data_20_V_read; +input [15:0] data_21_V_read; +input [15:0] data_22_V_read; +input [15:0] data_23_V_read; +input [15:0] data_24_V_read; +input [15:0] data_25_V_read; +input [15:0] data_26_V_read; +input [15:0] data_27_V_read; +input [15:0] data_28_V_read; +input [15:0] data_29_V_read; +input [15:0] data_30_V_read; +input [15:0] data_31_V_read; +input [15:0] data_32_V_read; +input [15:0] data_33_V_read; +input [15:0] data_34_V_read; +input [15:0] data_35_V_read; +input [15:0] data_36_V_read; +input [15:0] data_37_V_read; +input [15:0] data_38_V_read; +input [15:0] data_39_V_read; +input [15:0] data_40_V_read; +input [15:0] data_41_V_read; +input [15:0] data_42_V_read; +input [15:0] data_43_V_read; +input [15:0] data_44_V_read; +input [15:0] data_45_V_read; +input [15:0] data_46_V_read; +input [15:0] data_47_V_read; +input [15:0] data_48_V_read; +input [15:0] data_49_V_read; +input [15:0] data_50_V_read; +input [15:0] data_51_V_read; +input [15:0] data_52_V_read; +input [15:0] data_53_V_read; +input [15:0] data_54_V_read; +input [15:0] data_55_V_read; +input [15:0] data_56_V_read; +input [15:0] data_57_V_read; +input [15:0] data_58_V_read; +input [15:0] data_59_V_read; +input [15:0] data_60_V_read; +input [15:0] data_61_V_read; +input [15:0] data_62_V_read; +input [15:0] data_63_V_read; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; +output [15:0] ap_return_4; +output [15:0] ap_return_5; +output [15:0] ap_return_6; +output [15:0] ap_return_7; +output [15:0] ap_return_8; +output [15:0] ap_return_9; +output [15:0] ap_return_10; +output [15:0] ap_return_11; +output [15:0] ap_return_12; +output [15:0] ap_return_13; +output [15:0] ap_return_14; +output [15:0] ap_return_15; +output [15:0] ap_return_16; +output [15:0] ap_return_17; +output [15:0] ap_return_18; +output [15:0] ap_return_19; +output [15:0] ap_return_20; +output [15:0] ap_return_21; +output [15:0] ap_return_22; +output [15:0] ap_return_23; +output [15:0] ap_return_24; +output [15:0] ap_return_25; +output [15:0] ap_return_26; +output [15:0] ap_return_27; +output [15:0] ap_return_28; +output [15:0] ap_return_29; +output [15:0] ap_return_30; +output [15:0] ap_return_31; +input ap_ce; + +reg[15:0] ap_return_0; +reg[15:0] ap_return_1; +reg[15:0] ap_return_2; +reg[15:0] ap_return_3; +reg[15:0] ap_return_4; +reg[15:0] ap_return_5; +reg[15:0] ap_return_6; +reg[15:0] ap_return_7; +reg[15:0] ap_return_8; +reg[15:0] ap_return_9; +reg[15:0] ap_return_10; +reg[15:0] ap_return_11; +reg[15:0] ap_return_12; +reg[15:0] ap_return_13; +reg[15:0] ap_return_14; +reg[15:0] ap_return_15; +reg[15:0] ap_return_16; +reg[15:0] ap_return_17; +reg[15:0] ap_return_18; +reg[15:0] ap_return_19; +reg[15:0] ap_return_20; +reg[15:0] ap_return_21; +reg[15:0] ap_return_22; +reg[15:0] ap_return_23; +reg[15:0] ap_return_24; +reg[15:0] ap_return_25; +reg[15:0] ap_return_26; +reg[15:0] ap_return_27; +reg[15:0] ap_return_28; +reg[15:0] ap_return_29; +reg[15:0] ap_return_30; +reg[15:0] ap_return_31; + +reg [15:0] data_63_V_read_3_reg_8620; +wire ap_block_state1_pp0_stage0_iter0; +wire ap_block_state2_pp0_stage0_iter1; +wire ap_block_state3_pp0_stage0_iter2; +wire ap_block_state4_pp0_stage0_iter3; +wire ap_block_state5_pp0_stage0_iter4; +wire ap_block_state6_pp0_stage0_iter5; +wire ap_block_state7_pp0_stage0_iter6; +wire ap_block_state8_pp0_stage0_iter7; +wire ap_block_state9_pp0_stage0_iter8; +wire ap_block_state10_pp0_stage0_iter9; +wire ap_block_state11_pp0_stage0_iter10; +wire ap_block_state12_pp0_stage0_iter11; +wire ap_block_state13_pp0_stage0_iter12; +wire ap_block_state14_pp0_stage0_iter13; +wire ap_block_state15_pp0_stage0_iter14; +wire ap_block_state16_pp0_stage0_iter15; +wire ap_block_state17_pp0_stage0_iter16; +wire ap_block_state18_pp0_stage0_iter17; +wire ap_block_pp0_stage0_11001; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter1_reg; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter2_reg; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter3_reg; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter4_reg; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter5_reg; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter6_reg; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter7_reg; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter8_reg; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter9_reg; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter10_reg; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter11_reg; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter12_reg; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter13_reg; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter14_reg; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter15_reg; +reg [15:0] data_63_V_read_3_reg_8620_pp0_iter16_reg; +reg [15:0] data_62_V_read_3_reg_8645; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter1_reg; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter2_reg; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter3_reg; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter4_reg; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter5_reg; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter6_reg; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter7_reg; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter8_reg; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter9_reg; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter10_reg; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter11_reg; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter12_reg; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter13_reg; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter14_reg; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter15_reg; +reg [15:0] data_62_V_read_3_reg_8645_pp0_iter16_reg; +reg [15:0] data_61_V_read62_reg_8663; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter1_reg; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter2_reg; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter3_reg; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter4_reg; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter5_reg; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter6_reg; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter7_reg; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter8_reg; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter9_reg; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter10_reg; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter11_reg; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter12_reg; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter13_reg; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter14_reg; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter15_reg; +reg [15:0] data_61_V_read62_reg_8663_pp0_iter16_reg; +reg [15:0] data_60_V_read61_reg_8691; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter1_reg; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter2_reg; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter3_reg; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter4_reg; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter5_reg; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter6_reg; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter7_reg; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter8_reg; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter9_reg; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter10_reg; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter11_reg; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter12_reg; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter13_reg; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter14_reg; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter15_reg; +reg [15:0] data_60_V_read61_reg_8691_pp0_iter16_reg; +reg [15:0] data_59_V_read_3_reg_8724; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter1_reg; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter2_reg; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter3_reg; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter4_reg; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter5_reg; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter6_reg; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter7_reg; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter8_reg; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter9_reg; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter10_reg; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter11_reg; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter12_reg; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter13_reg; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter14_reg; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter15_reg; +reg [15:0] data_59_V_read_3_reg_8724_pp0_iter16_reg; +reg [15:0] data_58_V_read_3_reg_8756; +reg [15:0] data_58_V_read_3_reg_8756_pp0_iter1_reg; +reg [15:0] data_58_V_read_3_reg_8756_pp0_iter2_reg; +reg [15:0] data_58_V_read_3_reg_8756_pp0_iter3_reg; +reg [15:0] data_58_V_read_3_reg_8756_pp0_iter4_reg; +reg [15:0] data_58_V_read_3_reg_8756_pp0_iter5_reg; +reg [15:0] data_58_V_read_3_reg_8756_pp0_iter6_reg; +reg [15:0] data_58_V_read_3_reg_8756_pp0_iter7_reg; +reg [15:0] data_58_V_read_3_reg_8756_pp0_iter8_reg; +reg [15:0] data_58_V_read_3_reg_8756_pp0_iter9_reg; +reg [15:0] data_58_V_read_3_reg_8756_pp0_iter10_reg; +reg [15:0] data_58_V_read_3_reg_8756_pp0_iter11_reg; +reg [15:0] data_58_V_read_3_reg_8756_pp0_iter12_reg; +reg [15:0] data_58_V_read_3_reg_8756_pp0_iter13_reg; +reg [15:0] data_58_V_read_3_reg_8756_pp0_iter14_reg; +reg [15:0] data_58_V_read_3_reg_8756_pp0_iter15_reg; +reg [15:0] data_57_V_read_3_reg_8786; +reg [15:0] data_57_V_read_3_reg_8786_pp0_iter1_reg; +reg [15:0] data_57_V_read_3_reg_8786_pp0_iter2_reg; +reg [15:0] data_57_V_read_3_reg_8786_pp0_iter3_reg; +reg [15:0] data_57_V_read_3_reg_8786_pp0_iter4_reg; +reg [15:0] data_57_V_read_3_reg_8786_pp0_iter5_reg; +reg [15:0] data_57_V_read_3_reg_8786_pp0_iter6_reg; +reg [15:0] data_57_V_read_3_reg_8786_pp0_iter7_reg; +reg [15:0] data_57_V_read_3_reg_8786_pp0_iter8_reg; +reg [15:0] data_57_V_read_3_reg_8786_pp0_iter9_reg; +reg [15:0] data_57_V_read_3_reg_8786_pp0_iter10_reg; +reg [15:0] data_57_V_read_3_reg_8786_pp0_iter11_reg; +reg [15:0] data_57_V_read_3_reg_8786_pp0_iter12_reg; +reg [15:0] data_57_V_read_3_reg_8786_pp0_iter13_reg; +reg [15:0] data_57_V_read_3_reg_8786_pp0_iter14_reg; +reg [15:0] data_57_V_read_3_reg_8786_pp0_iter15_reg; +reg [15:0] data_56_V_read_3_reg_8814; +reg [15:0] data_56_V_read_3_reg_8814_pp0_iter1_reg; +reg [15:0] data_56_V_read_3_reg_8814_pp0_iter2_reg; +reg [15:0] data_56_V_read_3_reg_8814_pp0_iter3_reg; +reg [15:0] data_56_V_read_3_reg_8814_pp0_iter4_reg; +reg [15:0] data_56_V_read_3_reg_8814_pp0_iter5_reg; +reg [15:0] data_56_V_read_3_reg_8814_pp0_iter6_reg; +reg [15:0] data_56_V_read_3_reg_8814_pp0_iter7_reg; +reg [15:0] data_56_V_read_3_reg_8814_pp0_iter8_reg; +reg [15:0] data_56_V_read_3_reg_8814_pp0_iter9_reg; +reg [15:0] data_56_V_read_3_reg_8814_pp0_iter10_reg; +reg [15:0] data_56_V_read_3_reg_8814_pp0_iter11_reg; +reg [15:0] data_56_V_read_3_reg_8814_pp0_iter12_reg; +reg [15:0] data_56_V_read_3_reg_8814_pp0_iter13_reg; +reg [15:0] data_56_V_read_3_reg_8814_pp0_iter14_reg; +reg [15:0] data_56_V_read_3_reg_8814_pp0_iter15_reg; +reg [15:0] data_55_V_read_3_reg_8844; +reg [15:0] data_55_V_read_3_reg_8844_pp0_iter1_reg; +reg [15:0] data_55_V_read_3_reg_8844_pp0_iter2_reg; +reg [15:0] data_55_V_read_3_reg_8844_pp0_iter3_reg; +reg [15:0] data_55_V_read_3_reg_8844_pp0_iter4_reg; +reg [15:0] data_55_V_read_3_reg_8844_pp0_iter5_reg; +reg [15:0] data_55_V_read_3_reg_8844_pp0_iter6_reg; +reg [15:0] data_55_V_read_3_reg_8844_pp0_iter7_reg; +reg [15:0] data_55_V_read_3_reg_8844_pp0_iter8_reg; +reg [15:0] data_55_V_read_3_reg_8844_pp0_iter9_reg; +reg [15:0] data_55_V_read_3_reg_8844_pp0_iter10_reg; +reg [15:0] data_55_V_read_3_reg_8844_pp0_iter11_reg; +reg [15:0] data_55_V_read_3_reg_8844_pp0_iter12_reg; +reg [15:0] data_55_V_read_3_reg_8844_pp0_iter13_reg; +reg [15:0] data_55_V_read_3_reg_8844_pp0_iter14_reg; +reg [15:0] data_55_V_read_3_reg_8844_pp0_iter15_reg; +reg [15:0] data_54_V_read_3_reg_8873; +reg [15:0] data_54_V_read_3_reg_8873_pp0_iter1_reg; +reg [15:0] data_54_V_read_3_reg_8873_pp0_iter2_reg; +reg [15:0] data_54_V_read_3_reg_8873_pp0_iter3_reg; +reg [15:0] data_54_V_read_3_reg_8873_pp0_iter4_reg; +reg [15:0] data_54_V_read_3_reg_8873_pp0_iter5_reg; +reg [15:0] data_54_V_read_3_reg_8873_pp0_iter6_reg; +reg [15:0] data_54_V_read_3_reg_8873_pp0_iter7_reg; +reg [15:0] data_54_V_read_3_reg_8873_pp0_iter8_reg; +reg [15:0] data_54_V_read_3_reg_8873_pp0_iter9_reg; +reg [15:0] data_54_V_read_3_reg_8873_pp0_iter10_reg; +reg [15:0] data_54_V_read_3_reg_8873_pp0_iter11_reg; +reg [15:0] data_54_V_read_3_reg_8873_pp0_iter12_reg; +reg [15:0] data_54_V_read_3_reg_8873_pp0_iter13_reg; +reg [15:0] data_54_V_read_3_reg_8873_pp0_iter14_reg; +reg [15:0] data_53_V_read_3_reg_8899; +reg [15:0] data_53_V_read_3_reg_8899_pp0_iter1_reg; +reg [15:0] data_53_V_read_3_reg_8899_pp0_iter2_reg; +reg [15:0] data_53_V_read_3_reg_8899_pp0_iter3_reg; +reg [15:0] data_53_V_read_3_reg_8899_pp0_iter4_reg; +reg [15:0] data_53_V_read_3_reg_8899_pp0_iter5_reg; +reg [15:0] data_53_V_read_3_reg_8899_pp0_iter6_reg; +reg [15:0] data_53_V_read_3_reg_8899_pp0_iter7_reg; +reg [15:0] data_53_V_read_3_reg_8899_pp0_iter8_reg; +reg [15:0] data_53_V_read_3_reg_8899_pp0_iter9_reg; +reg [15:0] data_53_V_read_3_reg_8899_pp0_iter10_reg; +reg [15:0] data_53_V_read_3_reg_8899_pp0_iter11_reg; +reg [15:0] data_53_V_read_3_reg_8899_pp0_iter12_reg; +reg [15:0] data_53_V_read_3_reg_8899_pp0_iter13_reg; +reg [15:0] data_53_V_read_3_reg_8899_pp0_iter14_reg; +reg [15:0] data_52_V_read_3_reg_8928; +reg [15:0] data_52_V_read_3_reg_8928_pp0_iter1_reg; +reg [15:0] data_52_V_read_3_reg_8928_pp0_iter2_reg; +reg [15:0] data_52_V_read_3_reg_8928_pp0_iter3_reg; +reg [15:0] data_52_V_read_3_reg_8928_pp0_iter4_reg; +reg [15:0] data_52_V_read_3_reg_8928_pp0_iter5_reg; +reg [15:0] data_52_V_read_3_reg_8928_pp0_iter6_reg; +reg [15:0] data_52_V_read_3_reg_8928_pp0_iter7_reg; +reg [15:0] data_52_V_read_3_reg_8928_pp0_iter8_reg; +reg [15:0] data_52_V_read_3_reg_8928_pp0_iter9_reg; +reg [15:0] data_52_V_read_3_reg_8928_pp0_iter10_reg; +reg [15:0] data_52_V_read_3_reg_8928_pp0_iter11_reg; +reg [15:0] data_52_V_read_3_reg_8928_pp0_iter12_reg; +reg [15:0] data_52_V_read_3_reg_8928_pp0_iter13_reg; +reg [15:0] data_52_V_read_3_reg_8928_pp0_iter14_reg; +reg [15:0] data_51_V_read52_reg_8956; +reg [15:0] data_51_V_read52_reg_8956_pp0_iter1_reg; +reg [15:0] data_51_V_read52_reg_8956_pp0_iter2_reg; +reg [15:0] data_51_V_read52_reg_8956_pp0_iter3_reg; +reg [15:0] data_51_V_read52_reg_8956_pp0_iter4_reg; +reg [15:0] data_51_V_read52_reg_8956_pp0_iter5_reg; +reg [15:0] data_51_V_read52_reg_8956_pp0_iter6_reg; +reg [15:0] data_51_V_read52_reg_8956_pp0_iter7_reg; +reg [15:0] data_51_V_read52_reg_8956_pp0_iter8_reg; +reg [15:0] data_51_V_read52_reg_8956_pp0_iter9_reg; +reg [15:0] data_51_V_read52_reg_8956_pp0_iter10_reg; +reg [15:0] data_51_V_read52_reg_8956_pp0_iter11_reg; +reg [15:0] data_51_V_read52_reg_8956_pp0_iter12_reg; +reg [15:0] data_51_V_read52_reg_8956_pp0_iter13_reg; +reg [15:0] data_51_V_read52_reg_8956_pp0_iter14_reg; +reg [15:0] data_50_V_read51_reg_8984; +reg [15:0] data_50_V_read51_reg_8984_pp0_iter1_reg; +reg [15:0] data_50_V_read51_reg_8984_pp0_iter2_reg; +reg [15:0] data_50_V_read51_reg_8984_pp0_iter3_reg; +reg [15:0] data_50_V_read51_reg_8984_pp0_iter4_reg; +reg [15:0] data_50_V_read51_reg_8984_pp0_iter5_reg; +reg [15:0] data_50_V_read51_reg_8984_pp0_iter6_reg; +reg [15:0] data_50_V_read51_reg_8984_pp0_iter7_reg; +reg [15:0] data_50_V_read51_reg_8984_pp0_iter8_reg; +reg [15:0] data_50_V_read51_reg_8984_pp0_iter9_reg; +reg [15:0] data_50_V_read51_reg_8984_pp0_iter10_reg; +reg [15:0] data_50_V_read51_reg_8984_pp0_iter11_reg; +reg [15:0] data_50_V_read51_reg_8984_pp0_iter12_reg; +reg [15:0] data_50_V_read51_reg_8984_pp0_iter13_reg; +reg [15:0] data_50_V_read51_reg_8984_pp0_iter14_reg; +reg [15:0] data_49_V_read_3_reg_9012; +reg [15:0] data_49_V_read_3_reg_9012_pp0_iter1_reg; +reg [15:0] data_49_V_read_3_reg_9012_pp0_iter2_reg; +reg [15:0] data_49_V_read_3_reg_9012_pp0_iter3_reg; +reg [15:0] data_49_V_read_3_reg_9012_pp0_iter4_reg; +reg [15:0] data_49_V_read_3_reg_9012_pp0_iter5_reg; +reg [15:0] data_49_V_read_3_reg_9012_pp0_iter6_reg; +reg [15:0] data_49_V_read_3_reg_9012_pp0_iter7_reg; +reg [15:0] data_49_V_read_3_reg_9012_pp0_iter8_reg; +reg [15:0] data_49_V_read_3_reg_9012_pp0_iter9_reg; +reg [15:0] data_49_V_read_3_reg_9012_pp0_iter10_reg; +reg [15:0] data_49_V_read_3_reg_9012_pp0_iter11_reg; +reg [15:0] data_49_V_read_3_reg_9012_pp0_iter12_reg; +reg [15:0] data_49_V_read_3_reg_9012_pp0_iter13_reg; +reg [15:0] data_48_V_read_3_reg_9040; +reg [15:0] data_48_V_read_3_reg_9040_pp0_iter1_reg; +reg [15:0] data_48_V_read_3_reg_9040_pp0_iter2_reg; +reg [15:0] data_48_V_read_3_reg_9040_pp0_iter3_reg; +reg [15:0] data_48_V_read_3_reg_9040_pp0_iter4_reg; +reg [15:0] data_48_V_read_3_reg_9040_pp0_iter5_reg; +reg [15:0] data_48_V_read_3_reg_9040_pp0_iter6_reg; +reg [15:0] data_48_V_read_3_reg_9040_pp0_iter7_reg; +reg [15:0] data_48_V_read_3_reg_9040_pp0_iter8_reg; +reg [15:0] data_48_V_read_3_reg_9040_pp0_iter9_reg; +reg [15:0] data_48_V_read_3_reg_9040_pp0_iter10_reg; +reg [15:0] data_48_V_read_3_reg_9040_pp0_iter11_reg; +reg [15:0] data_48_V_read_3_reg_9040_pp0_iter12_reg; +reg [15:0] data_48_V_read_3_reg_9040_pp0_iter13_reg; +reg [15:0] data_47_V_read_3_reg_9066; +reg [15:0] data_47_V_read_3_reg_9066_pp0_iter1_reg; +reg [15:0] data_47_V_read_3_reg_9066_pp0_iter2_reg; +reg [15:0] data_47_V_read_3_reg_9066_pp0_iter3_reg; +reg [15:0] data_47_V_read_3_reg_9066_pp0_iter4_reg; +reg [15:0] data_47_V_read_3_reg_9066_pp0_iter5_reg; +reg [15:0] data_47_V_read_3_reg_9066_pp0_iter6_reg; +reg [15:0] data_47_V_read_3_reg_9066_pp0_iter7_reg; +reg [15:0] data_47_V_read_3_reg_9066_pp0_iter8_reg; +reg [15:0] data_47_V_read_3_reg_9066_pp0_iter9_reg; +reg [15:0] data_47_V_read_3_reg_9066_pp0_iter10_reg; +reg [15:0] data_47_V_read_3_reg_9066_pp0_iter11_reg; +reg [15:0] data_47_V_read_3_reg_9066_pp0_iter12_reg; +reg [15:0] data_47_V_read_3_reg_9066_pp0_iter13_reg; +reg [15:0] data_46_V_read_3_reg_9094; +reg [15:0] data_46_V_read_3_reg_9094_pp0_iter1_reg; +reg [15:0] data_46_V_read_3_reg_9094_pp0_iter2_reg; +reg [15:0] data_46_V_read_3_reg_9094_pp0_iter3_reg; +reg [15:0] data_46_V_read_3_reg_9094_pp0_iter4_reg; +reg [15:0] data_46_V_read_3_reg_9094_pp0_iter5_reg; +reg [15:0] data_46_V_read_3_reg_9094_pp0_iter6_reg; +reg [15:0] data_46_V_read_3_reg_9094_pp0_iter7_reg; +reg [15:0] data_46_V_read_3_reg_9094_pp0_iter8_reg; +reg [15:0] data_46_V_read_3_reg_9094_pp0_iter9_reg; +reg [15:0] data_46_V_read_3_reg_9094_pp0_iter10_reg; +reg [15:0] data_46_V_read_3_reg_9094_pp0_iter11_reg; +reg [15:0] data_46_V_read_3_reg_9094_pp0_iter12_reg; +reg [15:0] data_46_V_read_3_reg_9094_pp0_iter13_reg; +reg [15:0] data_45_V_read_3_reg_9125; +reg [15:0] data_45_V_read_3_reg_9125_pp0_iter1_reg; +reg [15:0] data_45_V_read_3_reg_9125_pp0_iter2_reg; +reg [15:0] data_45_V_read_3_reg_9125_pp0_iter3_reg; +reg [15:0] data_45_V_read_3_reg_9125_pp0_iter4_reg; +reg [15:0] data_45_V_read_3_reg_9125_pp0_iter5_reg; +reg [15:0] data_45_V_read_3_reg_9125_pp0_iter6_reg; +reg [15:0] data_45_V_read_3_reg_9125_pp0_iter7_reg; +reg [15:0] data_45_V_read_3_reg_9125_pp0_iter8_reg; +reg [15:0] data_45_V_read_3_reg_9125_pp0_iter9_reg; +reg [15:0] data_45_V_read_3_reg_9125_pp0_iter10_reg; +reg [15:0] data_45_V_read_3_reg_9125_pp0_iter11_reg; +reg [15:0] data_45_V_read_3_reg_9125_pp0_iter12_reg; +reg [15:0] data_44_V_read_3_reg_9154; +reg [15:0] data_44_V_read_3_reg_9154_pp0_iter1_reg; +reg [15:0] data_44_V_read_3_reg_9154_pp0_iter2_reg; +reg [15:0] data_44_V_read_3_reg_9154_pp0_iter3_reg; +reg [15:0] data_44_V_read_3_reg_9154_pp0_iter4_reg; +reg [15:0] data_44_V_read_3_reg_9154_pp0_iter5_reg; +reg [15:0] data_44_V_read_3_reg_9154_pp0_iter6_reg; +reg [15:0] data_44_V_read_3_reg_9154_pp0_iter7_reg; +reg [15:0] data_44_V_read_3_reg_9154_pp0_iter8_reg; +reg [15:0] data_44_V_read_3_reg_9154_pp0_iter9_reg; +reg [15:0] data_44_V_read_3_reg_9154_pp0_iter10_reg; +reg [15:0] data_44_V_read_3_reg_9154_pp0_iter11_reg; +reg [15:0] data_44_V_read_3_reg_9154_pp0_iter12_reg; +reg [15:0] data_43_V_read_3_reg_9184; +reg [15:0] data_43_V_read_3_reg_9184_pp0_iter1_reg; +reg [15:0] data_43_V_read_3_reg_9184_pp0_iter2_reg; +reg [15:0] data_43_V_read_3_reg_9184_pp0_iter3_reg; +reg [15:0] data_43_V_read_3_reg_9184_pp0_iter4_reg; +reg [15:0] data_43_V_read_3_reg_9184_pp0_iter5_reg; +reg [15:0] data_43_V_read_3_reg_9184_pp0_iter6_reg; +reg [15:0] data_43_V_read_3_reg_9184_pp0_iter7_reg; +reg [15:0] data_43_V_read_3_reg_9184_pp0_iter8_reg; +reg [15:0] data_43_V_read_3_reg_9184_pp0_iter9_reg; +reg [15:0] data_43_V_read_3_reg_9184_pp0_iter10_reg; +reg [15:0] data_43_V_read_3_reg_9184_pp0_iter11_reg; +reg [15:0] data_43_V_read_3_reg_9184_pp0_iter12_reg; +reg [15:0] data_42_V_read_3_reg_9212; +reg [15:0] data_42_V_read_3_reg_9212_pp0_iter1_reg; +reg [15:0] data_42_V_read_3_reg_9212_pp0_iter2_reg; +reg [15:0] data_42_V_read_3_reg_9212_pp0_iter3_reg; +reg [15:0] data_42_V_read_3_reg_9212_pp0_iter4_reg; +reg [15:0] data_42_V_read_3_reg_9212_pp0_iter5_reg; +reg [15:0] data_42_V_read_3_reg_9212_pp0_iter6_reg; +reg [15:0] data_42_V_read_3_reg_9212_pp0_iter7_reg; +reg [15:0] data_42_V_read_3_reg_9212_pp0_iter8_reg; +reg [15:0] data_42_V_read_3_reg_9212_pp0_iter9_reg; +reg [15:0] data_42_V_read_3_reg_9212_pp0_iter10_reg; +reg [15:0] data_42_V_read_3_reg_9212_pp0_iter11_reg; +reg [15:0] data_42_V_read_3_reg_9212_pp0_iter12_reg; +reg [15:0] data_41_V_read42_reg_9242; +reg [15:0] data_41_V_read42_reg_9242_pp0_iter1_reg; +reg [15:0] data_41_V_read42_reg_9242_pp0_iter2_reg; +reg [15:0] data_41_V_read42_reg_9242_pp0_iter3_reg; +reg [15:0] data_41_V_read42_reg_9242_pp0_iter4_reg; +reg [15:0] data_41_V_read42_reg_9242_pp0_iter5_reg; +reg [15:0] data_41_V_read42_reg_9242_pp0_iter6_reg; +reg [15:0] data_41_V_read42_reg_9242_pp0_iter7_reg; +reg [15:0] data_41_V_read42_reg_9242_pp0_iter8_reg; +reg [15:0] data_41_V_read42_reg_9242_pp0_iter9_reg; +reg [15:0] data_41_V_read42_reg_9242_pp0_iter10_reg; +reg [15:0] data_41_V_read42_reg_9242_pp0_iter11_reg; +reg [15:0] data_40_V_read41_reg_9272; +reg [15:0] data_40_V_read41_reg_9272_pp0_iter1_reg; +reg [15:0] data_40_V_read41_reg_9272_pp0_iter2_reg; +reg [15:0] data_40_V_read41_reg_9272_pp0_iter3_reg; +reg [15:0] data_40_V_read41_reg_9272_pp0_iter4_reg; +reg [15:0] data_40_V_read41_reg_9272_pp0_iter5_reg; +reg [15:0] data_40_V_read41_reg_9272_pp0_iter6_reg; +reg [15:0] data_40_V_read41_reg_9272_pp0_iter7_reg; +reg [15:0] data_40_V_read41_reg_9272_pp0_iter8_reg; +reg [15:0] data_40_V_read41_reg_9272_pp0_iter9_reg; +reg [15:0] data_40_V_read41_reg_9272_pp0_iter10_reg; +reg [15:0] data_40_V_read41_reg_9272_pp0_iter11_reg; +reg [15:0] data_39_V_read_3_reg_9301; +reg [15:0] data_39_V_read_3_reg_9301_pp0_iter1_reg; +reg [15:0] data_39_V_read_3_reg_9301_pp0_iter2_reg; +reg [15:0] data_39_V_read_3_reg_9301_pp0_iter3_reg; +reg [15:0] data_39_V_read_3_reg_9301_pp0_iter4_reg; +reg [15:0] data_39_V_read_3_reg_9301_pp0_iter5_reg; +reg [15:0] data_39_V_read_3_reg_9301_pp0_iter6_reg; +reg [15:0] data_39_V_read_3_reg_9301_pp0_iter7_reg; +reg [15:0] data_39_V_read_3_reg_9301_pp0_iter8_reg; +reg [15:0] data_39_V_read_3_reg_9301_pp0_iter9_reg; +reg [15:0] data_39_V_read_3_reg_9301_pp0_iter10_reg; +reg [15:0] data_39_V_read_3_reg_9301_pp0_iter11_reg; +reg [15:0] data_38_V_read_3_reg_9328; +reg [15:0] data_38_V_read_3_reg_9328_pp0_iter1_reg; +reg [15:0] data_38_V_read_3_reg_9328_pp0_iter2_reg; +reg [15:0] data_38_V_read_3_reg_9328_pp0_iter3_reg; +reg [15:0] data_38_V_read_3_reg_9328_pp0_iter4_reg; +reg [15:0] data_38_V_read_3_reg_9328_pp0_iter5_reg; +reg [15:0] data_38_V_read_3_reg_9328_pp0_iter6_reg; +reg [15:0] data_38_V_read_3_reg_9328_pp0_iter7_reg; +reg [15:0] data_38_V_read_3_reg_9328_pp0_iter8_reg; +reg [15:0] data_38_V_read_3_reg_9328_pp0_iter9_reg; +reg [15:0] data_38_V_read_3_reg_9328_pp0_iter10_reg; +reg [15:0] data_38_V_read_3_reg_9328_pp0_iter11_reg; +reg [15:0] data_37_V_read_3_reg_9353; +reg [15:0] data_37_V_read_3_reg_9353_pp0_iter1_reg; +reg [15:0] data_37_V_read_3_reg_9353_pp0_iter2_reg; +reg [15:0] data_37_V_read_3_reg_9353_pp0_iter3_reg; +reg [15:0] data_37_V_read_3_reg_9353_pp0_iter4_reg; +reg [15:0] data_37_V_read_3_reg_9353_pp0_iter5_reg; +reg [15:0] data_37_V_read_3_reg_9353_pp0_iter6_reg; +reg [15:0] data_37_V_read_3_reg_9353_pp0_iter7_reg; +reg [15:0] data_37_V_read_3_reg_9353_pp0_iter8_reg; +reg [15:0] data_37_V_read_3_reg_9353_pp0_iter9_reg; +reg [15:0] data_37_V_read_3_reg_9353_pp0_iter10_reg; +reg [15:0] data_36_V_read_3_reg_9383; +reg [15:0] data_36_V_read_3_reg_9383_pp0_iter1_reg; +reg [15:0] data_36_V_read_3_reg_9383_pp0_iter2_reg; +reg [15:0] data_36_V_read_3_reg_9383_pp0_iter3_reg; +reg [15:0] data_36_V_read_3_reg_9383_pp0_iter4_reg; +reg [15:0] data_36_V_read_3_reg_9383_pp0_iter5_reg; +reg [15:0] data_36_V_read_3_reg_9383_pp0_iter6_reg; +reg [15:0] data_36_V_read_3_reg_9383_pp0_iter7_reg; +reg [15:0] data_36_V_read_3_reg_9383_pp0_iter8_reg; +reg [15:0] data_36_V_read_3_reg_9383_pp0_iter9_reg; +reg [15:0] data_36_V_read_3_reg_9383_pp0_iter10_reg; +reg [15:0] data_35_V_read_3_reg_9410; +reg [15:0] data_35_V_read_3_reg_9410_pp0_iter1_reg; +reg [15:0] data_35_V_read_3_reg_9410_pp0_iter2_reg; +reg [15:0] data_35_V_read_3_reg_9410_pp0_iter3_reg; +reg [15:0] data_35_V_read_3_reg_9410_pp0_iter4_reg; +reg [15:0] data_35_V_read_3_reg_9410_pp0_iter5_reg; +reg [15:0] data_35_V_read_3_reg_9410_pp0_iter6_reg; +reg [15:0] data_35_V_read_3_reg_9410_pp0_iter7_reg; +reg [15:0] data_35_V_read_3_reg_9410_pp0_iter8_reg; +reg [15:0] data_35_V_read_3_reg_9410_pp0_iter9_reg; +reg [15:0] data_35_V_read_3_reg_9410_pp0_iter10_reg; +reg [15:0] data_34_V_read_3_reg_9434; +reg [15:0] data_34_V_read_3_reg_9434_pp0_iter1_reg; +reg [15:0] data_34_V_read_3_reg_9434_pp0_iter2_reg; +reg [15:0] data_34_V_read_3_reg_9434_pp0_iter3_reg; +reg [15:0] data_34_V_read_3_reg_9434_pp0_iter4_reg; +reg [15:0] data_34_V_read_3_reg_9434_pp0_iter5_reg; +reg [15:0] data_34_V_read_3_reg_9434_pp0_iter6_reg; +reg [15:0] data_34_V_read_3_reg_9434_pp0_iter7_reg; +reg [15:0] data_34_V_read_3_reg_9434_pp0_iter8_reg; +reg [15:0] data_34_V_read_3_reg_9434_pp0_iter9_reg; +reg [15:0] data_34_V_read_3_reg_9434_pp0_iter10_reg; +reg [15:0] data_33_V_read_3_reg_9463; +reg [15:0] data_33_V_read_3_reg_9463_pp0_iter1_reg; +reg [15:0] data_33_V_read_3_reg_9463_pp0_iter2_reg; +reg [15:0] data_33_V_read_3_reg_9463_pp0_iter3_reg; +reg [15:0] data_33_V_read_3_reg_9463_pp0_iter4_reg; +reg [15:0] data_33_V_read_3_reg_9463_pp0_iter5_reg; +reg [15:0] data_33_V_read_3_reg_9463_pp0_iter6_reg; +reg [15:0] data_33_V_read_3_reg_9463_pp0_iter7_reg; +reg [15:0] data_33_V_read_3_reg_9463_pp0_iter8_reg; +reg [15:0] data_33_V_read_3_reg_9463_pp0_iter9_reg; +reg [15:0] data_33_V_read_3_reg_9463_pp0_iter10_reg; +reg [15:0] data_32_V_read_3_reg_9492; +reg [15:0] data_32_V_read_3_reg_9492_pp0_iter1_reg; +reg [15:0] data_32_V_read_3_reg_9492_pp0_iter2_reg; +reg [15:0] data_32_V_read_3_reg_9492_pp0_iter3_reg; +reg [15:0] data_32_V_read_3_reg_9492_pp0_iter4_reg; +reg [15:0] data_32_V_read_3_reg_9492_pp0_iter5_reg; +reg [15:0] data_32_V_read_3_reg_9492_pp0_iter6_reg; +reg [15:0] data_32_V_read_3_reg_9492_pp0_iter7_reg; +reg [15:0] data_32_V_read_3_reg_9492_pp0_iter8_reg; +reg [15:0] data_32_V_read_3_reg_9492_pp0_iter9_reg; +reg [15:0] data_31_V_read32_reg_9521; +reg [15:0] data_31_V_read32_reg_9521_pp0_iter1_reg; +reg [15:0] data_31_V_read32_reg_9521_pp0_iter2_reg; +reg [15:0] data_31_V_read32_reg_9521_pp0_iter3_reg; +reg [15:0] data_31_V_read32_reg_9521_pp0_iter4_reg; +reg [15:0] data_31_V_read32_reg_9521_pp0_iter5_reg; +reg [15:0] data_31_V_read32_reg_9521_pp0_iter6_reg; +reg [15:0] data_31_V_read32_reg_9521_pp0_iter7_reg; +reg [15:0] data_31_V_read32_reg_9521_pp0_iter8_reg; +reg [15:0] data_31_V_read32_reg_9521_pp0_iter9_reg; +reg [15:0] data_30_V_read31_reg_9549; +reg [15:0] data_30_V_read31_reg_9549_pp0_iter1_reg; +reg [15:0] data_30_V_read31_reg_9549_pp0_iter2_reg; +reg [15:0] data_30_V_read31_reg_9549_pp0_iter3_reg; +reg [15:0] data_30_V_read31_reg_9549_pp0_iter4_reg; +reg [15:0] data_30_V_read31_reg_9549_pp0_iter5_reg; +reg [15:0] data_30_V_read31_reg_9549_pp0_iter6_reg; +reg [15:0] data_30_V_read31_reg_9549_pp0_iter7_reg; +reg [15:0] data_30_V_read31_reg_9549_pp0_iter8_reg; +reg [15:0] data_30_V_read31_reg_9549_pp0_iter9_reg; +reg [15:0] data_29_V_read_8_reg_9573; +reg [15:0] data_29_V_read_8_reg_9573_pp0_iter1_reg; +reg [15:0] data_29_V_read_8_reg_9573_pp0_iter2_reg; +reg [15:0] data_29_V_read_8_reg_9573_pp0_iter3_reg; +reg [15:0] data_29_V_read_8_reg_9573_pp0_iter4_reg; +reg [15:0] data_29_V_read_8_reg_9573_pp0_iter5_reg; +reg [15:0] data_29_V_read_8_reg_9573_pp0_iter6_reg; +reg [15:0] data_29_V_read_8_reg_9573_pp0_iter7_reg; +reg [15:0] data_29_V_read_8_reg_9573_pp0_iter8_reg; +reg [15:0] data_29_V_read_8_reg_9573_pp0_iter9_reg; +reg [15:0] data_28_V_read_8_reg_9598; +reg [15:0] data_28_V_read_8_reg_9598_pp0_iter1_reg; +reg [15:0] data_28_V_read_8_reg_9598_pp0_iter2_reg; +reg [15:0] data_28_V_read_8_reg_9598_pp0_iter3_reg; +reg [15:0] data_28_V_read_8_reg_9598_pp0_iter4_reg; +reg [15:0] data_28_V_read_8_reg_9598_pp0_iter5_reg; +reg [15:0] data_28_V_read_8_reg_9598_pp0_iter6_reg; +reg [15:0] data_28_V_read_8_reg_9598_pp0_iter7_reg; +reg [15:0] data_28_V_read_8_reg_9598_pp0_iter8_reg; +reg [15:0] data_27_V_read28_reg_9625; +reg [15:0] data_27_V_read28_reg_9625_pp0_iter1_reg; +reg [15:0] data_27_V_read28_reg_9625_pp0_iter2_reg; +reg [15:0] data_27_V_read28_reg_9625_pp0_iter3_reg; +reg [15:0] data_27_V_read28_reg_9625_pp0_iter4_reg; +reg [15:0] data_27_V_read28_reg_9625_pp0_iter5_reg; +reg [15:0] data_27_V_read28_reg_9625_pp0_iter6_reg; +reg [15:0] data_27_V_read28_reg_9625_pp0_iter7_reg; +reg [15:0] data_27_V_read28_reg_9625_pp0_iter8_reg; +reg [15:0] data_26_V_read27_reg_9652; +reg [15:0] data_26_V_read27_reg_9652_pp0_iter1_reg; +reg [15:0] data_26_V_read27_reg_9652_pp0_iter2_reg; +reg [15:0] data_26_V_read27_reg_9652_pp0_iter3_reg; +reg [15:0] data_26_V_read27_reg_9652_pp0_iter4_reg; +reg [15:0] data_26_V_read27_reg_9652_pp0_iter5_reg; +reg [15:0] data_26_V_read27_reg_9652_pp0_iter6_reg; +reg [15:0] data_26_V_read27_reg_9652_pp0_iter7_reg; +reg [15:0] data_26_V_read27_reg_9652_pp0_iter8_reg; +reg [15:0] data_25_V_read26_reg_9677; +reg [15:0] data_25_V_read26_reg_9677_pp0_iter1_reg; +reg [15:0] data_25_V_read26_reg_9677_pp0_iter2_reg; +reg [15:0] data_25_V_read26_reg_9677_pp0_iter3_reg; +reg [15:0] data_25_V_read26_reg_9677_pp0_iter4_reg; +reg [15:0] data_25_V_read26_reg_9677_pp0_iter5_reg; +reg [15:0] data_25_V_read26_reg_9677_pp0_iter6_reg; +reg [15:0] data_25_V_read26_reg_9677_pp0_iter7_reg; +reg [15:0] data_25_V_read26_reg_9677_pp0_iter8_reg; +reg [15:0] data_24_V_read25_reg_9704; +reg [15:0] data_24_V_read25_reg_9704_pp0_iter1_reg; +reg [15:0] data_24_V_read25_reg_9704_pp0_iter2_reg; +reg [15:0] data_24_V_read25_reg_9704_pp0_iter3_reg; +reg [15:0] data_24_V_read25_reg_9704_pp0_iter4_reg; +reg [15:0] data_24_V_read25_reg_9704_pp0_iter5_reg; +reg [15:0] data_24_V_read25_reg_9704_pp0_iter6_reg; +reg [15:0] data_24_V_read25_reg_9704_pp0_iter7_reg; +reg [15:0] data_24_V_read25_reg_9704_pp0_iter8_reg; +reg [15:0] data_23_V_read24_reg_9730; +reg [15:0] data_23_V_read24_reg_9730_pp0_iter1_reg; +reg [15:0] data_23_V_read24_reg_9730_pp0_iter2_reg; +reg [15:0] data_23_V_read24_reg_9730_pp0_iter3_reg; +reg [15:0] data_23_V_read24_reg_9730_pp0_iter4_reg; +reg [15:0] data_23_V_read24_reg_9730_pp0_iter5_reg; +reg [15:0] data_23_V_read24_reg_9730_pp0_iter6_reg; +reg [15:0] data_23_V_read24_reg_9730_pp0_iter7_reg; +reg [15:0] data_22_V_read23_reg_9756; +reg [15:0] data_22_V_read23_reg_9756_pp0_iter1_reg; +reg [15:0] data_22_V_read23_reg_9756_pp0_iter2_reg; +reg [15:0] data_22_V_read23_reg_9756_pp0_iter3_reg; +reg [15:0] data_22_V_read23_reg_9756_pp0_iter4_reg; +reg [15:0] data_22_V_read23_reg_9756_pp0_iter5_reg; +reg [15:0] data_22_V_read23_reg_9756_pp0_iter6_reg; +reg [15:0] data_22_V_read23_reg_9756_pp0_iter7_reg; +reg [15:0] data_22_V_read23_reg_9756_pp0_iter8_reg; +reg [15:0] data_21_V_read22_reg_9784; +reg [15:0] data_21_V_read22_reg_9784_pp0_iter1_reg; +reg [15:0] data_21_V_read22_reg_9784_pp0_iter2_reg; +reg [15:0] data_21_V_read22_reg_9784_pp0_iter3_reg; +reg [15:0] data_21_V_read22_reg_9784_pp0_iter4_reg; +reg [15:0] data_21_V_read22_reg_9784_pp0_iter5_reg; +reg [15:0] data_21_V_read22_reg_9784_pp0_iter6_reg; +reg [15:0] data_21_V_read22_reg_9784_pp0_iter7_reg; +reg [15:0] data_20_V_read21_reg_9814; +reg [15:0] data_20_V_read21_reg_9814_pp0_iter1_reg; +reg [15:0] data_20_V_read21_reg_9814_pp0_iter2_reg; +reg [15:0] data_20_V_read21_reg_9814_pp0_iter3_reg; +reg [15:0] data_20_V_read21_reg_9814_pp0_iter4_reg; +reg [15:0] data_20_V_read21_reg_9814_pp0_iter5_reg; +reg [15:0] data_20_V_read21_reg_9814_pp0_iter6_reg; +reg [15:0] data_20_V_read21_reg_9814_pp0_iter7_reg; +reg [15:0] data_19_V_read_8_reg_9845; +reg [15:0] data_19_V_read_8_reg_9845_pp0_iter1_reg; +reg [15:0] data_19_V_read_8_reg_9845_pp0_iter2_reg; +reg [15:0] data_19_V_read_8_reg_9845_pp0_iter3_reg; +reg [15:0] data_19_V_read_8_reg_9845_pp0_iter4_reg; +reg [15:0] data_19_V_read_8_reg_9845_pp0_iter5_reg; +reg [15:0] data_19_V_read_8_reg_9845_pp0_iter6_reg; +reg [15:0] data_18_V_read_8_reg_9874; +reg [15:0] data_18_V_read_8_reg_9874_pp0_iter1_reg; +reg [15:0] data_18_V_read_8_reg_9874_pp0_iter2_reg; +reg [15:0] data_18_V_read_8_reg_9874_pp0_iter3_reg; +reg [15:0] data_18_V_read_8_reg_9874_pp0_iter4_reg; +reg [15:0] data_18_V_read_8_reg_9874_pp0_iter5_reg; +reg [15:0] data_18_V_read_8_reg_9874_pp0_iter6_reg; +reg [15:0] data_17_V_read18_reg_9904; +reg [15:0] data_17_V_read18_reg_9904_pp0_iter1_reg; +reg [15:0] data_17_V_read18_reg_9904_pp0_iter2_reg; +reg [15:0] data_17_V_read18_reg_9904_pp0_iter3_reg; +reg [15:0] data_17_V_read18_reg_9904_pp0_iter4_reg; +reg [15:0] data_17_V_read18_reg_9904_pp0_iter5_reg; +reg [15:0] data_17_V_read18_reg_9904_pp0_iter6_reg; +reg [15:0] data_16_V_read17_reg_9935; +reg [15:0] data_16_V_read17_reg_9935_pp0_iter1_reg; +reg [15:0] data_16_V_read17_reg_9935_pp0_iter2_reg; +reg [15:0] data_16_V_read17_reg_9935_pp0_iter3_reg; +reg [15:0] data_16_V_read17_reg_9935_pp0_iter4_reg; +reg [15:0] data_16_V_read17_reg_9935_pp0_iter5_reg; +reg [15:0] data_16_V_read17_reg_9935_pp0_iter6_reg; +reg [15:0] data_15_V_read16_reg_9962; +reg [15:0] data_15_V_read16_reg_9962_pp0_iter1_reg; +reg [15:0] data_15_V_read16_reg_9962_pp0_iter2_reg; +reg [15:0] data_15_V_read16_reg_9962_pp0_iter3_reg; +reg [15:0] data_15_V_read16_reg_9962_pp0_iter4_reg; +reg [15:0] data_15_V_read16_reg_9962_pp0_iter5_reg; +reg [15:0] data_14_V_read15_reg_9987; +reg [15:0] data_14_V_read15_reg_9987_pp0_iter1_reg; +reg [15:0] data_14_V_read15_reg_9987_pp0_iter2_reg; +reg [15:0] data_14_V_read15_reg_9987_pp0_iter3_reg; +reg [15:0] data_14_V_read15_reg_9987_pp0_iter4_reg; +reg [15:0] data_14_V_read15_reg_9987_pp0_iter5_reg; +reg [15:0] data_13_V_read14_reg_10015; +reg [15:0] data_13_V_read14_reg_10015_pp0_iter1_reg; +reg [15:0] data_13_V_read14_reg_10015_pp0_iter2_reg; +reg [15:0] data_13_V_read14_reg_10015_pp0_iter3_reg; +reg [15:0] data_13_V_read14_reg_10015_pp0_iter4_reg; +reg [15:0] data_13_V_read14_reg_10015_pp0_iter5_reg; +reg [15:0] data_12_V_read13_reg_10045; +reg [15:0] data_12_V_read13_reg_10045_pp0_iter1_reg; +reg [15:0] data_12_V_read13_reg_10045_pp0_iter2_reg; +reg [15:0] data_12_V_read13_reg_10045_pp0_iter3_reg; +reg [15:0] data_12_V_read13_reg_10045_pp0_iter4_reg; +reg [15:0] data_12_V_read13_reg_10045_pp0_iter5_reg; +reg [15:0] data_11_V_read12_reg_10075; +reg [15:0] data_11_V_read12_reg_10075_pp0_iter1_reg; +reg [15:0] data_11_V_read12_reg_10075_pp0_iter2_reg; +reg [15:0] data_11_V_read12_reg_10075_pp0_iter3_reg; +reg [15:0] data_11_V_read12_reg_10075_pp0_iter4_reg; +reg [15:0] data_11_V_read12_reg_10075_pp0_iter5_reg; +reg [15:0] data_10_V_read11_reg_10105; +reg [15:0] data_10_V_read11_reg_10105_pp0_iter1_reg; +reg [15:0] data_10_V_read11_reg_10105_pp0_iter2_reg; +reg [15:0] data_10_V_read11_reg_10105_pp0_iter3_reg; +reg [15:0] data_10_V_read11_reg_10105_pp0_iter4_reg; +reg [15:0] data_9_V_read_8_reg_10136; +reg [15:0] data_9_V_read_8_reg_10136_pp0_iter1_reg; +reg [15:0] data_9_V_read_8_reg_10136_pp0_iter2_reg; +reg [15:0] data_9_V_read_8_reg_10136_pp0_iter3_reg; +reg [15:0] data_9_V_read_8_reg_10136_pp0_iter4_reg; +reg [15:0] data_8_V_read_8_reg_10164; +reg [15:0] data_8_V_read_8_reg_10164_pp0_iter1_reg; +reg [15:0] data_8_V_read_8_reg_10164_pp0_iter2_reg; +reg [15:0] data_8_V_read_8_reg_10164_pp0_iter3_reg; +reg [15:0] data_8_V_read_8_reg_10164_pp0_iter4_reg; +reg [15:0] data_7_V_read_9_reg_10191; +reg [15:0] data_7_V_read_9_reg_10191_pp0_iter1_reg; +reg [15:0] data_7_V_read_9_reg_10191_pp0_iter2_reg; +reg [15:0] data_7_V_read_9_reg_10191_pp0_iter3_reg; +reg [15:0] data_7_V_read_9_reg_10191_pp0_iter4_reg; +reg [15:0] data_6_V_read_9_reg_10218; +reg [15:0] data_6_V_read_9_reg_10218_pp0_iter1_reg; +reg [15:0] data_6_V_read_9_reg_10218_pp0_iter2_reg; +reg [15:0] data_6_V_read_9_reg_10218_pp0_iter3_reg; +reg [15:0] data_5_V_read_9_reg_10245; +reg [15:0] data_5_V_read_9_reg_10245_pp0_iter1_reg; +reg [15:0] data_5_V_read_9_reg_10245_pp0_iter2_reg; +reg [15:0] data_5_V_read_9_reg_10245_pp0_iter3_reg; +reg [15:0] data_4_V_read_10_reg_10273; +reg [15:0] data_4_V_read_10_reg_10273_pp0_iter1_reg; +reg [15:0] data_4_V_read_10_reg_10273_pp0_iter2_reg; +reg [15:0] data_4_V_read_10_reg_10273_pp0_iter3_reg; +reg [15:0] data_3_V_read_10_reg_10295; +reg [15:0] data_3_V_read_10_reg_10295_pp0_iter1_reg; +reg [15:0] data_3_V_read_10_reg_10295_pp0_iter2_reg; +reg [15:0] data_2_V_read_10_reg_10312; +reg [15:0] data_2_V_read_10_reg_10312_pp0_iter1_reg; +reg [15:0] data_1_V_read_10_reg_10323; +reg [15:0] data_0_V_read_10_reg_10329; +wire [15:0] add_ln703_fu_530_p2; +reg [15:0] add_ln703_reg_10335; +reg [15:0] add_ln703_reg_10335_pp0_iter1_reg; +wire [15:0] sub_ln703_fu_536_p2; +reg [15:0] sub_ln703_reg_10342; +wire [15:0] sub_ln703_1_fu_540_p2; +reg [15:0] sub_ln703_1_reg_10348; +wire [15:0] add_ln703_131_fu_544_p2; +reg [15:0] add_ln703_131_reg_10354; +reg [15:0] add_ln703_131_reg_10354_pp0_iter2_reg; +wire [15:0] sub_ln703_4_fu_548_p2; +reg [15:0] sub_ln703_4_reg_10361; +reg [15:0] sub_ln703_4_reg_10361_pp0_iter2_reg; +wire [15:0] sub_ln703_2_fu_552_p2; +reg [15:0] sub_ln703_2_reg_10367; +wire [15:0] add_ln703_130_fu_556_p2; +reg [15:0] add_ln703_130_reg_10373; +wire [15:0] sub_ln703_3_fu_560_p2; +reg [15:0] sub_ln703_3_reg_10379; +wire [15:0] add_ln703_134_fu_568_p2; +reg [15:0] add_ln703_134_reg_10385; +wire [15:0] sub_ln703_8_fu_572_p2; +reg [15:0] sub_ln703_8_reg_10392; +wire [15:0] sub_ln703_11_fu_576_p2; +reg [15:0] sub_ln703_11_reg_10398; +reg [15:0] sub_ln703_11_reg_10398_pp0_iter3_reg; +wire [15:0] add_ln703_144_fu_589_p2; +reg [15:0] add_ln703_144_reg_10403; +reg [15:0] add_ln703_144_reg_10403_pp0_iter3_reg; +wire [15:0] sub_ln703_6_fu_595_p2; +reg [15:0] sub_ln703_6_reg_10408; +wire [15:0] add_ln703_132_fu_599_p2; +reg [15:0] add_ln703_132_reg_10414; +wire [15:0] sub_ln703_10_fu_615_p2; +reg [15:0] sub_ln703_10_reg_10420; +wire [15:0] add_ln703_135_fu_619_p2; +reg [15:0] add_ln703_135_reg_10425; +wire [15:0] sub_ln703_15_fu_631_p2; +reg [15:0] sub_ln703_15_reg_10430; +wire [15:0] sub_ln703_16_fu_640_p2; +reg [15:0] sub_ln703_16_reg_10436; +wire [15:0] add_ln703_140_fu_644_p2; +reg [15:0] add_ln703_140_reg_10442; +wire [15:0] add_ln703_141_fu_649_p2; +reg [15:0] add_ln703_141_reg_10447; +wire [15:0] sub_ln703_17_fu_653_p2; +reg [15:0] sub_ln703_17_reg_10453; +wire [15:0] sub_ln703_18_fu_658_p2; +reg [15:0] sub_ln703_18_reg_10459; +wire [15:0] sub_ln703_20_fu_662_p2; +reg [15:0] sub_ln703_20_reg_10465; +wire [15:0] sub_ln703_23_fu_666_p2; +reg [15:0] sub_ln703_23_reg_10471; +wire [15:0] sub_ln703_28_fu_671_p2; +reg [15:0] sub_ln703_28_reg_10476; +wire [15:0] add_ln703_158_fu_676_p2; +reg [15:0] add_ln703_158_reg_10482; +wire [15:0] add_ln703_161_fu_681_p2; +reg [15:0] add_ln703_161_reg_10487; +wire [15:0] add_ln703_179_fu_685_p2; +reg [15:0] add_ln703_179_reg_10495; +wire [15:0] add_ln703_153_fu_809_p2; +reg [15:0] add_ln703_153_reg_10503; +wire [15:0] sub_ln703_38_fu_814_p2; +reg [15:0] sub_ln703_38_reg_10508; +wire [15:0] sub_ln703_39_fu_819_p2; +reg [15:0] sub_ln703_39_reg_10513; +wire [15:0] sub_ln703_40_fu_824_p2; +reg [15:0] sub_ln703_40_reg_10519; +wire [15:0] sub_ln703_43_fu_838_p2; +reg [15:0] sub_ln703_43_reg_10524; +wire [15:0] add_ln703_157_fu_892_p2; +reg [15:0] add_ln703_157_reg_10529; +wire [15:0] sub_ln703_53_fu_912_p2; +reg [15:0] sub_ln703_53_reg_10534; +wire [15:0] add_ln703_162_fu_917_p2; +reg [15:0] add_ln703_162_reg_10539; +wire [15:0] sub_ln703_58_fu_922_p2; +reg [15:0] sub_ln703_58_reg_10545; +wire [15:0] sub_ln703_62_fu_942_p2; +reg [15:0] sub_ln703_62_reg_10550; +wire [15:0] sub_ln703_63_fu_947_p2; +reg [15:0] sub_ln703_63_reg_10555; +wire [15:0] sub_ln703_64_fu_957_p2; +reg [15:0] sub_ln703_64_reg_10560; +wire [15:0] add_ln703_170_fu_972_p2; +reg [15:0] add_ln703_170_reg_10566; +wire [15:0] add_ln703_171_fu_977_p2; +reg [15:0] add_ln703_171_reg_10571; +wire [15:0] add_ln703_173_fu_982_p2; +reg [15:0] add_ln703_173_reg_10576; +wire [15:0] sub_ln703_66_fu_987_p2; +reg [15:0] sub_ln703_66_reg_10581; +wire [15:0] sub_ln703_70_fu_992_p2; +reg [15:0] sub_ln703_70_reg_10586; +wire [15:0] add_ln703_177_fu_997_p2; +reg [15:0] add_ln703_177_reg_10591; +wire [15:0] sub_ln703_71_fu_1002_p2; +reg [15:0] sub_ln703_71_reg_10596; +wire [15:0] add_ln703_181_fu_1015_p2; +reg [15:0] add_ln703_181_reg_10601; +wire [15:0] add_ln703_183_fu_1021_p2; +reg [15:0] add_ln703_183_reg_10606; +wire [15:0] sub_ln703_73_fu_1026_p2; +reg [15:0] sub_ln703_73_reg_10611; +wire [15:0] sub_ln703_75_fu_1031_p2; +reg [15:0] sub_ln703_75_reg_10616; +wire [15:0] add_ln703_186_fu_1036_p2; +reg [15:0] add_ln703_186_reg_10621; +wire [15:0] add_ln703_192_fu_1050_p2; +reg [15:0] add_ln703_192_reg_10626; +wire [15:0] sub_ln703_92_fu_1054_p2; +reg [15:0] sub_ln703_92_reg_10636; +wire [15:0] add_ln703_204_fu_1059_p2; +reg [15:0] add_ln703_204_reg_10641; +wire [15:0] add_ln703_209_fu_1064_p2; +reg [15:0] add_ln703_209_reg_10646; +wire [15:0] add_ln703_213_fu_1068_p2; +reg [15:0] add_ln703_213_reg_10653; +wire [15:0] add_ln703_223_fu_1073_p2; +reg [15:0] add_ln703_223_reg_10658; +wire [15:0] add_ln703_252_fu_1077_p2; +reg [15:0] add_ln703_252_reg_10665; +reg [15:0] add_ln703_252_reg_10665_pp0_iter5_reg; +wire [15:0] add_ln703_254_fu_1081_p2; +reg [15:0] add_ln703_254_reg_10672; +wire [15:0] sub_ln703_96_fu_1294_p2; +reg [15:0] sub_ln703_96_reg_10677; +wire [15:0] add_ln703_207_fu_1299_p2; +reg [15:0] add_ln703_207_reg_10682; +wire [15:0] add_ln703_208_fu_1309_p2; +reg [15:0] add_ln703_208_reg_10687; +wire [15:0] add_ln703_210_fu_1314_p2; +reg [15:0] add_ln703_210_reg_10692; +wire [15:0] sub_ln703_98_fu_1319_p2; +reg [15:0] sub_ln703_98_reg_10697; +wire [15:0] add_ln703_216_fu_1358_p2; +reg [15:0] add_ln703_216_reg_10702; +wire [15:0] sub_ln703_106_fu_1378_p2; +reg [15:0] sub_ln703_106_reg_10707; +wire [15:0] sub_ln703_107_fu_1383_p2; +reg [15:0] sub_ln703_107_reg_10712; +wire [15:0] sub_ln703_108_fu_1388_p2; +reg [15:0] sub_ln703_108_reg_10717; +wire [15:0] sub_ln703_109_fu_1407_p2; +reg [15:0] sub_ln703_109_reg_10722; +wire [15:0] sub_ln703_115_fu_1432_p2; +reg [15:0] sub_ln703_115_reg_10727; +wire [15:0] add_ln703_224_fu_1437_p2; +reg [15:0] add_ln703_224_reg_10732; +wire [15:0] add_ln703_226_fu_1457_p2; +reg [15:0] add_ln703_226_reg_10737; +wire [15:0] sub_ln703_122_fu_1462_p2; +reg [15:0] sub_ln703_122_reg_10742; +wire [15:0] sub_ln703_123_fu_1467_p2; +reg [15:0] sub_ln703_123_reg_10747; +wire [15:0] add_ln703_227_fu_1472_p2; +reg [15:0] add_ln703_227_reg_10752; +wire [15:0] sub_ln703_125_fu_1482_p2; +reg [15:0] sub_ln703_125_reg_10757; +wire [15:0] sub_ln703_128_fu_1496_p2; +reg [15:0] sub_ln703_128_reg_10762; +wire [15:0] add_ln703_233_fu_1501_p2; +reg [15:0] add_ln703_233_reg_10767; +wire [15:0] add_ln703_236_fu_1511_p2; +reg [15:0] add_ln703_236_reg_10772; +wire [15:0] add_ln703_238_fu_1520_p2; +reg [15:0] add_ln703_238_reg_10777; +wire [15:0] sub_ln703_133_fu_1532_p2; +reg [15:0] sub_ln703_133_reg_10782; +wire [15:0] sub_ln703_137_fu_1548_p2; +reg [15:0] sub_ln703_137_reg_10787; +wire [15:0] sub_ln703_141_fu_1553_p2; +reg [15:0] sub_ln703_141_reg_10792; +wire [15:0] sub_ln703_142_fu_1558_p2; +reg [15:0] sub_ln703_142_reg_10797; +wire [15:0] add_ln703_247_fu_1563_p2; +reg [15:0] add_ln703_247_reg_10802; +wire [15:0] add_ln703_250_fu_1574_p2; +reg [15:0] add_ln703_250_reg_10807; +wire [15:0] sub_ln703_146_fu_1580_p2; +reg [15:0] sub_ln703_146_reg_10812; +wire [15:0] add_ln703_260_fu_1593_p2; +reg [15:0] add_ln703_260_reg_10817; +wire [15:0] sub_ln703_152_fu_1599_p2; +reg [15:0] sub_ln703_152_reg_10822; +wire [15:0] add_ln703_262_fu_1604_p2; +reg [15:0] add_ln703_262_reg_10827; +wire [15:0] sub_ln703_154_fu_1609_p2; +reg [15:0] sub_ln703_154_reg_10832; +wire [15:0] add_ln703_265_fu_1614_p2; +reg [15:0] add_ln703_265_reg_10837; +wire [15:0] add_ln703_280_fu_1618_p2; +reg [15:0] add_ln703_280_reg_10846; +wire [15:0] add_ln703_326_fu_1622_p2; +reg [15:0] add_ln703_326_reg_10855; +reg [15:0] add_ln703_326_reg_10855_pp0_iter6_reg; +wire [15:0] sub_ln703_166_fu_1834_p2; +reg [15:0] sub_ln703_166_reg_10863; +wire [15:0] sub_ln703_183_fu_1959_p2; +reg [15:0] sub_ln703_183_reg_10868; +wire [15:0] add_ln703_283_fu_1979_p2; +reg [15:0] add_ln703_283_reg_10873; +wire [15:0] sub_ln703_184_fu_1984_p2; +reg [15:0] sub_ln703_184_reg_10878; +wire [15:0] sub_ln703_186_fu_1994_p2; +reg [15:0] sub_ln703_186_reg_10883; +wire [15:0] add_ln703_285_fu_2009_p2; +reg [15:0] add_ln703_285_reg_10888; +wire [15:0] sub_ln703_191_fu_2029_p2; +reg [15:0] sub_ln703_191_reg_10893; +wire [15:0] add_ln703_289_fu_2034_p2; +reg [15:0] add_ln703_289_reg_10898; +wire [15:0] add_ln703_290_fu_2039_p2; +reg [15:0] add_ln703_290_reg_10903; +wire [15:0] sub_ln703_194_fu_2054_p2; +reg [15:0] sub_ln703_194_reg_10908; +wire [15:0] sub_ln703_196_fu_2074_p2; +reg [15:0] sub_ln703_196_reg_10913; +wire [15:0] add_ln703_294_fu_2084_p2; +reg [15:0] add_ln703_294_reg_10918; +wire [15:0] add_ln703_295_fu_2089_p2; +reg [15:0] add_ln703_295_reg_10923; +wire [15:0] add_ln703_300_fu_2093_p2; +reg [15:0] add_ln703_300_reg_10930; +wire [15:0] sub_ln703_198_fu_2099_p2; +reg [15:0] sub_ln703_198_reg_10935; +wire [15:0] add_ln703_303_fu_2104_p2; +reg [15:0] add_ln703_303_reg_10940; +wire [15:0] add_ln703_304_fu_2110_p2; +reg [15:0] add_ln703_304_reg_10945; +wire [15:0] sub_ln703_200_fu_2115_p2; +reg [15:0] sub_ln703_200_reg_10950; +wire [15:0] sub_ln703_202_fu_2120_p2; +reg [15:0] sub_ln703_202_reg_10955; +wire [15:0] add_ln703_307_fu_2125_p2; +reg [15:0] add_ln703_307_reg_10960; +wire [15:0] sub_ln703_203_fu_2131_p2; +reg [15:0] sub_ln703_203_reg_10965; +wire [15:0] add_ln703_309_fu_2136_p2; +reg [15:0] add_ln703_309_reg_10970; +wire [15:0] sub_ln703_204_fu_2142_p2; +reg [15:0] sub_ln703_204_reg_10975; +wire [15:0] add_ln703_310_fu_2147_p2; +reg [15:0] add_ln703_310_reg_10980; +wire [15:0] sub_ln703_208_fu_2152_p2; +reg [15:0] sub_ln703_208_reg_10985; +wire [15:0] sub_ln703_209_fu_2157_p2; +reg [15:0] sub_ln703_209_reg_10990; +wire [15:0] sub_ln703_210_fu_2162_p2; +reg [15:0] sub_ln703_210_reg_10995; +wire [15:0] sub_ln703_212_fu_2173_p2; +reg [15:0] sub_ln703_212_reg_11000; +wire [15:0] add_ln703_323_fu_2188_p2; +reg [15:0] add_ln703_323_reg_11005; +wire [15:0] sub_ln703_230_fu_2194_p2; +reg [15:0] sub_ln703_230_reg_11010; +wire [15:0] add_ln703_328_fu_2208_p2; +reg [15:0] add_ln703_328_reg_11015; +wire [15:0] sub_ln703_237_fu_2214_p2; +reg [15:0] sub_ln703_237_reg_11020; +wire [15:0] add_ln703_333_fu_2224_p2; +reg [15:0] add_ln703_333_reg_11025; +wire [15:0] add_ln703_341_fu_2230_p2; +reg [15:0] add_ln703_341_reg_11030; +wire [15:0] add_ln703_369_fu_2234_p2; +reg [15:0] add_ln703_369_reg_11037; +reg [15:0] add_ln703_369_reg_11037_pp0_iter7_reg; +wire [15:0] sub_ln703_234_fu_2395_p2; +reg [15:0] sub_ln703_234_reg_11046; +wire [15:0] sub_ln703_246_fu_2477_p2; +reg [15:0] sub_ln703_246_reg_11051; +wire [15:0] sub_ln703_249_fu_2496_p2; +reg [15:0] sub_ln703_249_reg_11056; +wire [15:0] sub_ln703_250_fu_2501_p2; +reg [15:0] sub_ln703_250_reg_11061; +wire [15:0] sub_ln703_251_fu_2506_p2; +reg [15:0] sub_ln703_251_reg_11066; +wire [15:0] add_ln703_342_fu_2520_p2; +reg [15:0] add_ln703_342_reg_11071; +wire [15:0] sub_ln703_254_fu_2525_p2; +reg [15:0] sub_ln703_254_reg_11076; +wire [15:0] sub_ln703_256_fu_2534_p2; +reg [15:0] sub_ln703_256_reg_11081; +wire [15:0] sub_ln703_257_fu_2539_p2; +reg [15:0] sub_ln703_257_reg_11086; +wire [15:0] sub_ln703_261_fu_2569_p2; +reg [15:0] sub_ln703_261_reg_11091; +wire [15:0] sub_ln703_262_fu_2574_p2; +reg [15:0] sub_ln703_262_reg_11096; +wire [15:0] sub_ln703_263_fu_2579_p2; +reg [15:0] sub_ln703_263_reg_11101; +wire [15:0] add_ln703_346_fu_2589_p2; +reg [15:0] add_ln703_346_reg_11106; +wire [15:0] add_ln703_350_fu_2602_p2; +reg [15:0] add_ln703_350_reg_11111; +wire [15:0] sub_ln703_265_fu_2613_p2; +reg [15:0] sub_ln703_265_reg_11116; +wire [15:0] sub_ln703_270_fu_2628_p2; +reg [15:0] sub_ln703_270_reg_11121; +wire [15:0] add_ln703_352_fu_2633_p2; +reg [15:0] add_ln703_352_reg_11126; +wire [15:0] add_ln703_354_fu_2638_p2; +reg [15:0] add_ln703_354_reg_11131; +wire [15:0] sub_ln703_272_fu_2647_p2; +reg [15:0] sub_ln703_272_reg_11138; +wire [15:0] sub_ln703_274_fu_2652_p2; +reg [15:0] sub_ln703_274_reg_11143; +wire [15:0] add_ln703_356_fu_2657_p2; +reg [15:0] add_ln703_356_reg_11148; +wire [15:0] sub_ln703_275_fu_2662_p2; +reg [15:0] sub_ln703_275_reg_11153; +wire [15:0] add_ln703_360_fu_2677_p2; +reg [15:0] add_ln703_360_reg_11158; +wire [15:0] sub_ln703_281_fu_2688_p2; +reg [15:0] sub_ln703_281_reg_11163; +wire [15:0] sub_ln703_284_fu_2698_p2; +reg [15:0] sub_ln703_284_reg_11168; +wire [15:0] sub_ln703_289_fu_2703_p2; +reg [15:0] sub_ln703_289_reg_11173; +wire [15:0] sub_ln703_293_fu_2708_p2; +reg [15:0] sub_ln703_293_reg_11178; +wire [15:0] sub_ln703_296_fu_2713_p2; +reg [15:0] sub_ln703_296_reg_11183; +wire [15:0] sub_ln703_301_fu_2718_p2; +reg [15:0] sub_ln703_301_reg_11188; +wire [15:0] add_ln703_371_fu_2732_p2; +reg [15:0] add_ln703_371_reg_11193; +wire [15:0] add_ln703_375_fu_2738_p2; +reg [15:0] add_ln703_375_reg_11198; +wire [15:0] add_ln703_384_fu_2743_p2; +reg [15:0] add_ln703_384_reg_11203; +wire [15:0] add_ln703_400_fu_2752_p2; +reg [15:0] add_ln703_400_reg_11210; +wire [15:0] add_ln703_402_fu_2758_p2; +reg [15:0] add_ln703_402_reg_11215; +reg [15:0] add_ln703_402_reg_11215_pp0_iter8_reg; +wire [15:0] add_ln703_424_fu_2762_p2; +reg [15:0] add_ln703_424_reg_11225; +wire [15:0] add_ln703_439_fu_2766_p2; +reg [15:0] add_ln703_439_reg_11233; +reg [15:0] add_ln703_439_reg_11233_pp0_iter8_reg; +wire [15:0] add_ln703_525_fu_2774_p2; +reg [15:0] add_ln703_525_reg_11243; +reg [15:0] add_ln703_525_reg_11243_pp0_iter8_reg; +reg [15:0] add_ln703_525_reg_11243_pp0_iter9_reg; +wire [15:0] add_ln703_534_fu_2779_p2; +reg [15:0] add_ln703_534_reg_11248; +reg [15:0] add_ln703_534_reg_11248_pp0_iter8_reg; +reg [15:0] add_ln703_534_reg_11248_pp0_iter9_reg; +wire [15:0] sub_ln703_313_fu_2998_p2; +reg [15:0] sub_ln703_313_reg_11257; +wire [15:0] add_ln703_386_fu_3015_p2; +reg [15:0] add_ln703_386_reg_11262; +wire [15:0] sub_ln703_315_fu_3021_p2; +reg [15:0] sub_ln703_315_reg_11267; +wire [15:0] add_ln703_390_fu_3050_p2; +reg [15:0] add_ln703_390_reg_11272; +wire [15:0] sub_ln703_326_fu_3101_p2; +reg [15:0] sub_ln703_326_reg_11277; +wire [15:0] sub_ln703_328_fu_3111_p2; +reg [15:0] sub_ln703_328_reg_11282; +wire [15:0] add_ln703_410_fu_3149_p2; +reg [15:0] add_ln703_410_reg_11287; +wire [15:0] sub_ln703_333_fu_3155_p2; +reg [15:0] sub_ln703_333_reg_11292; +wire [15:0] add_ln703_416_fu_3170_p2; +reg [15:0] add_ln703_416_reg_11297; +wire [15:0] sub_ln703_334_fu_3175_p2; +reg [15:0] sub_ln703_334_reg_11302; +wire [15:0] sub_ln703_336_fu_3180_p2; +reg [15:0] sub_ln703_336_reg_11307; +wire [15:0] add_ln703_417_fu_3185_p2; +reg [15:0] add_ln703_417_reg_11312; +wire [15:0] sub_ln703_339_fu_3200_p2; +reg [15:0] sub_ln703_339_reg_11317; +wire [15:0] sub_ln703_340_fu_3205_p2; +reg [15:0] sub_ln703_340_reg_11322; +wire [15:0] sub_ln703_342_fu_3215_p2; +reg [15:0] sub_ln703_342_reg_11327; +wire [15:0] sub_ln703_344_fu_3220_p2; +reg [15:0] sub_ln703_344_reg_11332; +wire [15:0] sub_ln703_345_fu_3234_p2; +reg [15:0] sub_ln703_345_reg_11337; +wire [15:0] sub_ln703_350_fu_3244_p2; +reg [15:0] sub_ln703_350_reg_11342; +wire [15:0] add_ln703_426_fu_3258_p2; +reg [15:0] add_ln703_426_reg_11347; +wire [15:0] sub_ln703_353_fu_3269_p2; +reg [15:0] sub_ln703_353_reg_11352; +wire [15:0] add_ln703_431_fu_3274_p2; +reg [15:0] add_ln703_431_reg_11357; +wire [15:0] add_ln703_435_fu_3284_p2; +reg [15:0] add_ln703_435_reg_11362; +wire [15:0] sub_ln703_356_fu_3290_p2; +reg [15:0] sub_ln703_356_reg_11367; +wire [15:0] sub_ln703_358_fu_3300_p2; +reg [15:0] sub_ln703_358_reg_11372; +wire [15:0] sub_ln703_362_fu_3305_p2; +reg [15:0] sub_ln703_362_reg_11377; +wire [15:0] add_ln703_438_fu_3310_p2; +reg [15:0] add_ln703_438_reg_11382; +wire [15:0] add_ln703_445_fu_3315_p2; +reg [15:0] add_ln703_445_reg_11387; +wire [15:0] add_ln703_447_fu_3320_p2; +reg [15:0] add_ln703_447_reg_11392; +wire [15:0] sub_ln703_371_fu_3324_p2; +reg [15:0] sub_ln703_371_reg_11397; +wire [15:0] add_ln703_451_fu_3329_p2; +reg [15:0] add_ln703_451_reg_11402; +wire [15:0] add_ln703_466_fu_3333_p2; +reg [15:0] add_ln703_466_reg_11410; +wire [15:0] add_ln703_471_fu_3337_p2; +reg [15:0] add_ln703_471_reg_11418; +wire [15:0] add_ln703_484_fu_3342_p2; +reg [15:0] add_ln703_484_reg_11423; +wire [15:0] add_ln703_490_fu_3347_p2; +reg [15:0] add_ln703_490_reg_11428; +wire [15:0] add_ln703_498_fu_3351_p2; +reg [15:0] add_ln703_498_reg_11436; +wire [15:0] add_ln703_507_fu_3356_p2; +reg [15:0] add_ln703_507_reg_11441; +reg [15:0] add_ln703_507_reg_11441_pp0_iter9_reg; +wire [15:0] add_ln703_528_fu_3360_p2; +reg [15:0] add_ln703_528_reg_11452; +reg [15:0] add_ln703_528_reg_11452_pp0_iter9_reg; +wire [15:0] add_ln703_535_fu_3364_p2; +reg [15:0] add_ln703_535_reg_11457; +wire [15:0] add_ln703_568_fu_3368_p2; +reg [15:0] add_ln703_568_reg_11464; +reg [15:0] add_ln703_568_reg_11464_pp0_iter9_reg; +wire [15:0] sub_ln703_384_fu_3645_p2; +reg [15:0] sub_ln703_384_reg_11474; +wire [15:0] add_ln703_469_fu_3655_p2; +reg [15:0] add_ln703_469_reg_11479; +wire [15:0] sub_ln703_386_fu_3660_p2; +reg [15:0] sub_ln703_386_reg_11484; +wire [15:0] sub_ln703_387_fu_3665_p2; +reg [15:0] sub_ln703_387_reg_11489; +wire [15:0] add_ln703_476_fu_3685_p2; +reg [15:0] add_ln703_476_reg_11494; +wire [15:0] sub_ln703_390_fu_3690_p2; +reg [15:0] sub_ln703_390_reg_11499; +wire [15:0] sub_ln703_393_fu_3705_p2; +reg [15:0] sub_ln703_393_reg_11504; +wire [15:0] sub_ln703_394_fu_3710_p2; +reg [15:0] sub_ln703_394_reg_11509; +wire [15:0] sub_ln703_395_fu_3720_p2; +reg [15:0] sub_ln703_395_reg_11514; +wire [15:0] add_ln703_478_fu_3730_p2; +reg [15:0] add_ln703_478_reg_11519; +wire [15:0] sub_ln703_399_fu_3761_p2; +reg [15:0] sub_ln703_399_reg_11524; +wire [15:0] sub_ln703_401_fu_3781_p2; +reg [15:0] sub_ln703_401_reg_11529; +wire [15:0] sub_ln703_402_fu_3786_p2; +reg [15:0] sub_ln703_402_reg_11534; +wire [15:0] sub_ln703_403_fu_3791_p2; +reg [15:0] sub_ln703_403_reg_11539; +wire [15:0] add_ln703_496_fu_3806_p2; +reg [15:0] add_ln703_496_reg_11544; +wire [15:0] add_ln703_497_fu_3811_p2; +reg [15:0] add_ln703_497_reg_11549; +wire [15:0] sub_ln703_405_fu_3816_p2; +reg [15:0] sub_ln703_405_reg_11554; +wire [15:0] add_ln703_506_fu_3839_p2; +reg [15:0] add_ln703_506_reg_11559; +wire [15:0] sub_ln703_408_fu_3845_p2; +reg [15:0] sub_ln703_408_reg_11564; +wire [15:0] sub_ln703_411_fu_3850_p2; +reg [15:0] sub_ln703_411_reg_11569; +wire [15:0] sub_ln703_412_fu_3855_p2; +reg [15:0] sub_ln703_412_reg_11574; +wire [15:0] sub_ln703_414_fu_3860_p2; +reg [15:0] sub_ln703_414_reg_11579; +wire [15:0] sub_ln703_416_fu_3865_p2; +reg [15:0] sub_ln703_416_reg_11584; +wire [15:0] add_ln703_512_fu_3878_p2; +reg [15:0] add_ln703_512_reg_11589; +wire [15:0] sub_ln703_419_fu_3884_p2; +reg [15:0] sub_ln703_419_reg_11594; +wire [15:0] add_ln703_515_fu_3889_p2; +reg [15:0] add_ln703_515_reg_11599; +wire [15:0] add_ln703_517_fu_3894_p2; +reg [15:0] add_ln703_517_reg_11604; +wire [15:0] add_ln703_537_fu_3912_p2; +reg [15:0] add_ln703_537_reg_11609; +wire [15:0] add_ln703_545_fu_3923_p2; +reg [15:0] add_ln703_545_reg_11614; +wire [15:0] add_ln703_556_fu_3933_p2; +reg [15:0] add_ln703_556_reg_11619; +wire [15:0] sub_ln703_440_fu_3938_p2; +reg [15:0] sub_ln703_440_reg_11624; +wire [15:0] add_ln703_560_fu_3943_p2; +reg [15:0] add_ln703_560_reg_11629; +wire [15:0] add_ln703_566_fu_3952_p2; +reg [15:0] add_ln703_566_reg_11635; +wire [15:0] add_ln703_569_fu_3957_p2; +reg [15:0] add_ln703_569_reg_11640; +wire [15:0] add_ln703_588_fu_3961_p2; +reg [15:0] add_ln703_588_reg_11646; +wire [15:0] add_ln703_600_fu_3965_p2; +reg [15:0] add_ln703_600_reg_11652; +reg [15:0] add_ln703_600_reg_11652_pp0_iter10_reg; +wire [15:0] add_ln703_621_fu_3969_p2; +reg [15:0] add_ln703_621_reg_11662; +reg [15:0] add_ln703_621_reg_11662_pp0_iter10_reg; +wire [15:0] sub_ln703_448_fu_4206_p2; +reg [15:0] sub_ln703_448_reg_11673; +wire [15:0] sub_ln703_452_fu_4231_p2; +reg [15:0] sub_ln703_452_reg_11678; +wire [15:0] sub_ln703_453_fu_4236_p2; +reg [15:0] sub_ln703_453_reg_11683; +wire [15:0] sub_ln703_458_fu_4270_p2; +reg [15:0] sub_ln703_458_reg_11688; +wire [15:0] sub_ln703_461_fu_4303_p2; +reg [15:0] sub_ln703_461_reg_11693; +wire [15:0] add_ln703_572_fu_4308_p2; +reg [15:0] add_ln703_572_reg_11698; +wire [15:0] sub_ln703_462_fu_4313_p2; +reg [15:0] sub_ln703_462_reg_11703; +wire [15:0] add_ln703_573_fu_4323_p2; +reg [15:0] add_ln703_573_reg_11708; +wire [15:0] sub_ln703_467_fu_4333_p2; +reg [15:0] sub_ln703_467_reg_11713; +wire [15:0] sub_ln703_468_fu_4353_p2; +reg [15:0] sub_ln703_468_reg_11718; +wire [15:0] add_ln703_581_fu_4358_p2; +reg [15:0] add_ln703_581_reg_11723; +wire [15:0] add_ln703_583_fu_4363_p2; +reg [15:0] add_ln703_583_reg_11728; +wire [15:0] sub_ln703_469_fu_4368_p2; +reg [15:0] sub_ln703_469_reg_11733; +wire [15:0] sub_ln703_470_fu_4373_p2; +reg [15:0] sub_ln703_470_reg_11738; +wire [15:0] add_ln703_586_fu_4398_p2; +reg [15:0] add_ln703_586_reg_11743; +wire [15:0] add_ln703_590_fu_4412_p2; +reg [15:0] add_ln703_590_reg_11748; +wire [15:0] sub_ln703_475_fu_4418_p2; +reg [15:0] sub_ln703_475_reg_11753; +wire [15:0] add_ln703_591_fu_4423_p2; +reg [15:0] add_ln703_591_reg_11758; +wire [15:0] add_ln703_592_fu_4428_p2; +reg [15:0] add_ln703_592_reg_11763; +wire [15:0] add_ln703_598_fu_4441_p2; +reg [15:0] add_ln703_598_reg_11768; +wire [15:0] sub_ln703_482_fu_4447_p2; +reg [15:0] sub_ln703_482_reg_11773; +wire [15:0] sub_ln703_483_fu_4452_p2; +reg [15:0] sub_ln703_483_reg_11778; +wire [15:0] sub_ln703_488_fu_4457_p2; +reg [15:0] sub_ln703_488_reg_11783; +wire [15:0] sub_ln703_490_fu_4462_p2; +reg [15:0] sub_ln703_490_reg_11788; +wire [15:0] sub_ln703_491_fu_4467_p2; +reg [15:0] sub_ln703_491_reg_11793; +wire [15:0] add_ln703_599_fu_4477_p2; +reg [15:0] add_ln703_599_reg_11798; +wire [15:0] add_ln703_609_fu_4501_p2; +reg [15:0] add_ln703_609_reg_11803; +wire [15:0] add_ln703_616_fu_4511_p2; +reg [15:0] add_ln703_616_reg_11808; +wire [15:0] sub_ln703_503_fu_4516_p2; +reg [15:0] sub_ln703_503_reg_11813; +wire [15:0] sub_ln703_505_fu_4521_p2; +reg [15:0] sub_ln703_505_reg_11818; +wire [15:0] add_ln703_633_fu_4531_p2; +reg [15:0] add_ln703_633_reg_11823; +wire [15:0] add_ln703_634_fu_4535_p2; +reg [15:0] add_ln703_634_reg_11828; +wire [15:0] add_ln703_639_fu_4541_p2; +reg [15:0] add_ln703_639_reg_11833; +wire [15:0] add_ln703_646_fu_4546_p2; +reg [15:0] add_ln703_646_reg_11838; +wire [15:0] add_ln703_650_fu_4550_p2; +reg [15:0] add_ln703_650_reg_11844; +reg [15:0] add_ln703_650_reg_11844_pp0_iter11_reg; +wire [15:0] add_ln703_667_fu_4554_p2; +reg [15:0] add_ln703_667_reg_11853; +wire [15:0] sub_ln703_526_fu_4860_p2; +reg [15:0] sub_ln703_526_reg_11864; +wire [15:0] sub_ln703_527_fu_4865_p2; +reg [15:0] sub_ln703_527_reg_11869; +wire [15:0] add_ln703_647_fu_4870_p2; +reg [15:0] add_ln703_647_reg_11874; +wire [15:0] sub_ln703_529_fu_4880_p2; +reg [15:0] sub_ln703_529_reg_11879; +wire [15:0] sub_ln703_532_fu_4894_p2; +reg [15:0] sub_ln703_532_reg_11884; +wire [15:0] add_ln703_648_fu_4899_p2; +reg [15:0] add_ln703_648_reg_11889; +wire [15:0] sub_ln703_533_fu_4904_p2; +reg [15:0] sub_ln703_533_reg_11894; +wire [15:0] sub_ln703_535_fu_4919_p2; +reg [15:0] sub_ln703_535_reg_11899; +wire [15:0] sub_ln703_538_fu_4934_p2; +reg [15:0] sub_ln703_538_reg_11904; +wire [15:0] sub_ln703_539_fu_4939_p2; +reg [15:0] sub_ln703_539_reg_11909; +wire [15:0] sub_ln703_540_fu_4944_p2; +reg [15:0] sub_ln703_540_reg_11914; +wire [15:0] sub_ln703_541_fu_4949_p2; +reg [15:0] sub_ln703_541_reg_11919; +wire [15:0] sub_ln703_542_fu_4954_p2; +reg [15:0] sub_ln703_542_reg_11924; +wire [15:0] add_ln703_651_fu_4959_p2; +reg [15:0] add_ln703_651_reg_11929; +wire [15:0] sub_ln703_544_fu_4984_p2; +reg [15:0] sub_ln703_544_reg_11934; +wire [15:0] add_ln703_660_fu_4994_p2; +reg [15:0] add_ln703_660_reg_11939; +wire [15:0] add_ln703_661_fu_4999_p2; +reg [15:0] add_ln703_661_reg_11944; +wire [15:0] sub_ln703_551_fu_5004_p2; +reg [15:0] sub_ln703_551_reg_11949; +wire [15:0] add_ln703_666_fu_5013_p2; +reg [15:0] add_ln703_666_reg_11954; +wire [15:0] add_ln703_668_fu_5019_p2; +reg [15:0] add_ln703_668_reg_11959; +wire [15:0] sub_ln703_556_fu_5024_p2; +reg [15:0] sub_ln703_556_reg_11964; +wire [15:0] sub_ln703_557_fu_5029_p2; +reg [15:0] sub_ln703_557_reg_11969; +wire [15:0] sub_ln703_558_fu_5034_p2; +reg [15:0] sub_ln703_558_reg_11974; +wire [15:0] add_ln703_676_fu_5052_p2; +reg [15:0] add_ln703_676_reg_11979; +wire [15:0] add_ln703_682_fu_5066_p2; +reg [15:0] add_ln703_682_reg_11984; +wire [15:0] add_ln703_685_fu_5077_p2; +reg [15:0] add_ln703_685_reg_11989; +wire [15:0] add_ln703_691_fu_5092_p2; +reg [15:0] add_ln703_691_reg_11994; +wire [15:0] add_ln703_697_fu_5096_p2; +reg [15:0] add_ln703_697_reg_12002; +wire [15:0] sub_ln703_573_fu_5101_p2; +reg [15:0] sub_ln703_573_reg_12007; +wire [15:0] sub_ln703_582_fu_5106_p2; +reg [15:0] sub_ln703_582_reg_12012; +wire [15:0] sub_ln703_583_fu_5111_p2; +reg [15:0] sub_ln703_583_reg_12017; +wire [15:0] add_ln703_703_fu_5116_p2; +reg [15:0] add_ln703_703_reg_12022; +wire [15:0] add_ln703_706_fu_5120_p2; +reg [15:0] add_ln703_706_reg_12031; +wire [15:0] add_ln703_722_fu_5125_p2; +reg [15:0] add_ln703_722_reg_12036; +wire [15:0] add_ln703_726_fu_5130_p2; +reg [15:0] add_ln703_726_reg_12041; +wire [15:0] add_ln703_737_fu_5134_p2; +reg [15:0] add_ln703_737_reg_12047; +wire [15:0] add_ln703_704_fu_5336_p2; +reg [15:0] add_ln703_704_reg_12056; +wire [15:0] sub_ln703_586_fu_5351_p2; +reg [15:0] sub_ln703_586_reg_12061; +wire [15:0] sub_ln703_589_fu_5375_p2; +reg [15:0] sub_ln703_589_reg_12066; +wire [15:0] sub_ln703_593_fu_5410_p2; +reg [15:0] sub_ln703_593_reg_12071; +wire [15:0] sub_ln703_594_fu_5415_p2; +reg [15:0] sub_ln703_594_reg_12076; +wire [15:0] sub_ln703_595_fu_5420_p2; +reg [15:0] sub_ln703_595_reg_12081; +wire [15:0] add_ln703_719_fu_5439_p2; +reg [15:0] add_ln703_719_reg_12086; +wire [15:0] sub_ln703_598_fu_5454_p2; +reg [15:0] sub_ln703_598_reg_12091; +wire [15:0] add_ln703_728_fu_5485_p2; +reg [15:0] add_ln703_728_reg_12096; +wire [15:0] sub_ln703_603_fu_5491_p2; +reg [15:0] sub_ln703_603_reg_12101; +wire [15:0] sub_ln703_604_fu_5496_p2; +reg [15:0] sub_ln703_604_reg_12106; +wire [15:0] sub_ln703_605_fu_5501_p2; +reg [15:0] sub_ln703_605_reg_12111; +wire [15:0] sub_ln703_608_fu_5511_p2; +reg [15:0] sub_ln703_608_reg_12116; +wire [15:0] sub_ln703_609_fu_5516_p2; +reg [15:0] sub_ln703_609_reg_12121; +wire [15:0] sub_ln703_610_fu_5521_p2; +reg [15:0] sub_ln703_610_reg_12126; +wire [15:0] sub_ln703_612_fu_5526_p2; +reg [15:0] sub_ln703_612_reg_12131; +wire [15:0] sub_ln703_613_fu_5531_p2; +reg [15:0] sub_ln703_613_reg_12136; +wire [15:0] sub_ln703_614_fu_5536_p2; +reg [15:0] sub_ln703_614_reg_12141; +wire [15:0] add_ln703_733_fu_5551_p2; +reg [15:0] add_ln703_733_reg_12146; +wire [15:0] add_ln703_734_fu_5556_p2; +reg [15:0] add_ln703_734_reg_12151; +wire [15:0] sub_ln703_618_fu_5566_p2; +reg [15:0] sub_ln703_618_reg_12156; +wire [15:0] add_ln703_735_fu_5571_p2; +reg [15:0] add_ln703_735_reg_12161; +wire [15:0] sub_ln703_624_fu_5596_p2; +reg [15:0] sub_ln703_624_reg_12166; +wire [15:0] sub_ln703_630_fu_5627_p2; +reg [15:0] sub_ln703_630_reg_12171; +wire [15:0] sub_ln703_631_fu_5632_p2; +reg [15:0] sub_ln703_631_reg_12176; +wire [15:0] sub_ln703_634_fu_5637_p2; +reg [15:0] sub_ln703_634_reg_12181; +wire [15:0] sub_ln703_637_fu_5642_p2; +reg [15:0] sub_ln703_637_reg_12186; +wire [15:0] sub_ln703_638_fu_5647_p2; +reg [15:0] sub_ln703_638_reg_12191; +wire [15:0] add_ln703_755_fu_5652_p2; +reg [15:0] add_ln703_755_reg_12196; +wire [15:0] sub_ln703_644_fu_5656_p2; +reg [15:0] sub_ln703_644_reg_12204; +wire [15:0] sub_ln703_648_fu_5661_p2; +reg [15:0] sub_ln703_648_reg_12209; +wire [15:0] sub_ln703_650_fu_5666_p2; +reg [15:0] sub_ln703_650_reg_12214; +wire [15:0] add_ln703_765_fu_5671_p2; +reg [15:0] add_ln703_765_reg_12219; +wire [15:0] add_ln703_778_fu_5675_p2; +reg [15:0] add_ln703_778_reg_12227; +wire [15:0] add_ln703_783_fu_5679_p2; +reg [15:0] add_ln703_783_reg_12236; +wire [15:0] add_ln703_816_fu_5684_p2; +reg [15:0] add_ln703_816_reg_12241; +reg [15:0] add_ln703_816_reg_12241_pp0_iter13_reg; +wire [15:0] sub_ln703_662_fu_5918_p2; +reg [15:0] sub_ln703_662_reg_12248; +wire [15:0] sub_ln703_665_fu_5932_p2; +reg [15:0] sub_ln703_665_reg_12253; +wire [15:0] add_ln703_770_fu_5950_p2; +reg [15:0] add_ln703_770_reg_12258; +wire [15:0] sub_ln703_667_fu_5956_p2; +reg [15:0] sub_ln703_667_reg_12263; +wire [15:0] sub_ln703_669_fu_5975_p2; +reg [15:0] sub_ln703_669_reg_12268; +wire [15:0] add_ln703_779_fu_6024_p2; +reg [15:0] add_ln703_779_reg_12273; +wire [15:0] sub_ln703_676_fu_6033_p2; +reg [15:0] sub_ln703_676_reg_12278; +wire [15:0] sub_ln703_678_fu_6052_p2; +reg [15:0] sub_ln703_678_reg_12283; +wire [15:0] sub_ln703_679_fu_6057_p2; +reg [15:0] sub_ln703_679_reg_12288; +wire [15:0] sub_ln703_680_fu_6062_p2; +reg [15:0] sub_ln703_680_reg_12293; +wire [15:0] sub_ln703_682_fu_6067_p2; +reg [15:0] sub_ln703_682_reg_12298; +wire [15:0] sub_ln703_684_fu_6072_p2; +reg [15:0] sub_ln703_684_reg_12303; +wire [15:0] sub_ln703_686_fu_6077_p2; +reg [15:0] sub_ln703_686_reg_12308; +wire [15:0] sub_ln703_687_fu_6086_p2; +reg [15:0] sub_ln703_687_reg_12313; +wire [15:0] sub_ln703_688_fu_6091_p2; +reg [15:0] sub_ln703_688_reg_12318; +wire [15:0] sub_ln703_690_fu_6101_p2; +reg [15:0] sub_ln703_690_reg_12323; +wire [15:0] sub_ln703_691_fu_6106_p2; +reg [15:0] sub_ln703_691_reg_12328; +wire [15:0] sub_ln703_692_fu_6111_p2; +reg [15:0] sub_ln703_692_reg_12333; +wire [15:0] sub_ln703_693_fu_6116_p2; +reg [15:0] sub_ln703_693_reg_12338; +wire [15:0] sub_ln703_694_fu_6126_p2; +reg [15:0] sub_ln703_694_reg_12343; +wire [15:0] add_ln703_791_fu_6131_p2; +reg [15:0] add_ln703_791_reg_12348; +wire [15:0] sub_ln703_696_fu_6136_p2; +reg [15:0] sub_ln703_696_reg_12353; +wire [15:0] sub_ln703_697_fu_6141_p2; +reg [15:0] sub_ln703_697_reg_12358; +wire [15:0] add_ln703_792_fu_6146_p2; +reg [15:0] add_ln703_792_reg_12363; +wire [15:0] add_ln703_796_fu_6160_p2; +reg [15:0] add_ln703_796_reg_12368; +wire [15:0] add_ln703_798_fu_6166_p2; +reg [15:0] add_ln703_798_reg_12373; +wire [15:0] sub_ln703_700_fu_6172_p2; +reg [15:0] sub_ln703_700_reg_12378; +wire [15:0] sub_ln703_704_fu_6177_p2; +reg [15:0] sub_ln703_704_reg_12383; +wire [15:0] sub_ln703_707_fu_6182_p2; +reg [15:0] sub_ln703_707_reg_12388; +wire [15:0] add_ln703_801_fu_6187_p2; +reg [15:0] add_ln703_801_reg_12393; +wire [15:0] add_ln703_802_fu_6192_p2; +reg [15:0] add_ln703_802_reg_12398; +wire [15:0] add_ln703_818_fu_6205_p2; +reg [15:0] add_ln703_818_reg_12409; +reg [15:0] add_ln703_818_reg_12409_pp0_iter14_reg; +wire [15:0] add_ln703_821_fu_6216_p2; +reg [15:0] add_ln703_821_reg_12414; +wire [15:0] add_ln703_826_fu_6222_p2; +reg [15:0] add_ln703_826_reg_12419; +wire [15:0] add_ln703_836_fu_6226_p2; +reg [15:0] add_ln703_836_reg_12428; +wire [15:0] add_ln703_849_fu_6230_p2; +reg [15:0] add_ln703_849_reg_12434; +reg [15:0] add_ln703_849_reg_12434_pp0_iter14_reg; +wire [15:0] add_ln703_867_fu_6234_p2; +reg [15:0] add_ln703_867_reg_12444; +reg [15:0] add_ln703_867_reg_12444_pp0_iter14_reg; +wire [15:0] sub_ln703_724_fu_6432_p2; +reg [15:0] sub_ln703_724_reg_12450; +wire [15:0] add_ln703_819_fu_6447_p2; +reg [15:0] add_ln703_819_reg_12455; +wire [15:0] sub_ln703_727_fu_6452_p2; +reg [15:0] sub_ln703_727_reg_12460; +wire [15:0] sub_ln703_728_fu_6457_p2; +reg [15:0] sub_ln703_728_reg_12465; +wire [15:0] sub_ln703_733_fu_6487_p2; +reg [15:0] sub_ln703_733_reg_12470; +wire [15:0] sub_ln703_736_fu_6502_p2; +reg [15:0] sub_ln703_736_reg_12475; +wire [15:0] add_ln703_825_fu_6526_p2; +reg [15:0] add_ln703_825_reg_12480; +wire [15:0] add_ln703_827_fu_6531_p2; +reg [15:0] add_ln703_827_reg_12485; +wire [15:0] add_ln703_831_fu_6554_p2; +reg [15:0] add_ln703_831_reg_12490; +wire [15:0] add_ln703_833_fu_6573_p2; +reg [15:0] add_ln703_833_reg_12495; +wire [15:0] sub_ln703_746_fu_6579_p2; +reg [15:0] sub_ln703_746_reg_12500; +wire [15:0] add_ln703_834_fu_6594_p2; +reg [15:0] add_ln703_834_reg_12505; +wire [15:0] sub_ln703_749_fu_6599_p2; +reg [15:0] sub_ln703_749_reg_12510; +wire [15:0] sub_ln703_757_fu_6629_p2; +reg [15:0] sub_ln703_757_reg_12515; +wire [15:0] add_ln703_838_fu_6634_p2; +reg [15:0] add_ln703_838_reg_12520; +wire [15:0] sub_ln703_759_fu_6639_p2; +reg [15:0] sub_ln703_759_reg_12525; +wire [15:0] sub_ln703_761_fu_6644_p2; +reg [15:0] sub_ln703_761_reg_12530; +wire [15:0] add_ln703_840_fu_6649_p2; +reg [15:0] add_ln703_840_reg_12535; +wire [15:0] sub_ln703_763_fu_6654_p2; +reg [15:0] sub_ln703_763_reg_12540; +wire [15:0] sub_ln703_767_fu_6659_p2; +reg [15:0] sub_ln703_767_reg_12545; +wire [15:0] add_ln703_841_fu_6664_p2; +reg [15:0] add_ln703_841_reg_12550; +wire [15:0] sub_ln703_769_fu_6684_p2; +reg [15:0] sub_ln703_769_reg_12555; +wire [15:0] add_ln703_845_fu_6689_p2; +reg [15:0] add_ln703_845_reg_12560; +wire [15:0] add_ln703_851_fu_6702_p2; +reg [15:0] add_ln703_851_reg_12565; +wire [15:0] sub_ln703_770_fu_6708_p2; +reg [15:0] sub_ln703_770_reg_12570; +wire [15:0] add_ln703_858_fu_6733_p2; +reg [15:0] add_ln703_858_reg_12575; +wire [15:0] sub_ln703_781_fu_6739_p2; +reg [15:0] sub_ln703_781_reg_12580; +wire [15:0] add_ln703_868_fu_6755_p2; +reg [15:0] add_ln703_868_reg_12585; +wire [15:0] sub_ln703_787_fu_6759_p2; +reg [15:0] sub_ln703_787_reg_12590; +wire [15:0] sub_ln703_799_fu_6764_p2; +reg [15:0] sub_ln703_799_reg_12595; +wire [15:0] add_ln703_876_fu_6769_p2; +reg [15:0] add_ln703_876_reg_12600; +wire [15:0] add_ln703_877_fu_6774_p2; +reg [15:0] add_ln703_877_reg_12605; +wire [15:0] add_ln703_894_fu_6778_p2; +reg [15:0] add_ln703_894_reg_12616; +reg [15:0] add_ln703_894_reg_12616_pp0_iter15_reg; +wire [15:0] add_ln703_905_fu_6782_p2; +reg [15:0] add_ln703_905_reg_12625; +wire [15:0] add_ln703_914_fu_6786_p2; +reg [15:0] add_ln703_914_reg_12632; +wire [15:0] add_ln703_920_fu_6791_p2; +reg [15:0] add_ln703_920_reg_12637; +reg [15:0] add_ln703_920_reg_12637_pp0_iter15_reg; +wire [15:0] sub_ln703_797_fu_7030_p2; +reg [15:0] sub_ln703_797_reg_12645; +wire [15:0] add_ln703_872_fu_7050_p2; +reg [15:0] add_ln703_872_reg_12650; +wire [15:0] add_ln703_873_fu_7055_p2; +reg [15:0] add_ln703_873_reg_12655; +wire [15:0] sub_ln703_801_fu_7060_p2; +reg [15:0] sub_ln703_801_reg_12660; +wire [15:0] sub_ln703_802_fu_7065_p2; +reg [15:0] sub_ln703_802_reg_12665; +wire [15:0] sub_ln703_805_fu_7079_p2; +reg [15:0] sub_ln703_805_reg_12670; +wire [15:0] add_ln703_874_fu_7084_p2; +reg [15:0] add_ln703_874_reg_12675; +wire [15:0] add_ln703_875_fu_7094_p2; +reg [15:0] add_ln703_875_reg_12680; +wire [15:0] sub_ln703_807_fu_7099_p2; +reg [15:0] sub_ln703_807_reg_12685; +wire [15:0] add_ln703_882_fu_7121_p2; +reg [15:0] add_ln703_882_reg_12690; +wire [15:0] add_ln703_884_fu_7132_p2; +reg [15:0] add_ln703_884_reg_12695; +wire [15:0] sub_ln703_808_fu_7137_p2; +reg [15:0] sub_ln703_808_reg_12700; +wire [15:0] add_ln703_888_fu_7156_p2; +reg [15:0] add_ln703_888_reg_12705; +wire [15:0] add_ln703_892_fu_7175_p2; +reg [15:0] add_ln703_892_reg_12710; +wire [15:0] add_ln703_893_fu_7180_p2; +reg [15:0] add_ln703_893_reg_12715; +wire [15:0] add_ln703_895_fu_7185_p2; +reg [15:0] add_ln703_895_reg_12720; +wire [15:0] add_ln703_896_fu_7190_p2; +reg [15:0] add_ln703_896_reg_12725; +wire [15:0] add_ln703_898_fu_7195_p2; +reg [15:0] add_ln703_898_reg_12730; +wire [15:0] sub_ln703_814_fu_7200_p2; +reg [15:0] sub_ln703_814_reg_12735; +wire [15:0] sub_ln703_816_fu_7205_p2; +reg [15:0] sub_ln703_816_reg_12740; +wire [15:0] sub_ln703_818_fu_7210_p2; +reg [15:0] sub_ln703_818_reg_12745; +wire [15:0] sub_ln703_820_fu_7215_p2; +reg [15:0] sub_ln703_820_reg_12750; +wire [15:0] sub_ln703_821_fu_7220_p2; +reg [15:0] sub_ln703_821_reg_12755; +wire [15:0] sub_ln703_823_fu_7225_p2; +reg [15:0] sub_ln703_823_reg_12760; +wire [15:0] sub_ln703_824_fu_7230_p2; +reg [15:0] sub_ln703_824_reg_12765; +wire [15:0] sub_ln703_825_fu_7235_p2; +reg [15:0] sub_ln703_825_reg_12770; +wire [15:0] add_ln703_906_fu_7245_p2; +reg [15:0] add_ln703_906_reg_12775; +wire [15:0] add_ln703_917_fu_7273_p2; +reg [15:0] add_ln703_917_reg_12780; +wire [15:0] add_ln703_922_fu_7287_p2; +reg [15:0] add_ln703_922_reg_12785; +wire [15:0] sub_ln703_852_fu_7319_p2; +reg [15:0] sub_ln703_852_reg_12790; +wire [15:0] sub_ln703_862_fu_7324_p2; +reg [15:0] sub_ln703_862_reg_12795; +wire [15:0] sub_ln703_869_fu_7329_p2; +reg [15:0] sub_ln703_869_reg_12800; +reg [15:0] sub_ln703_869_reg_12800_pp0_iter16_reg; +wire [15:0] add_ln703_946_fu_7334_p2; +reg [15:0] add_ln703_946_reg_12805; +wire [15:0] add_ln703_954_fu_7338_p2; +reg [15:0] add_ln703_954_reg_12812; +wire [15:0] add_ln703_985_fu_7342_p2; +reg [15:0] add_ln703_985_reg_12819; +reg [15:0] add_ln703_985_reg_12819_pp0_iter16_reg; +wire [15:0] sub_ln703_857_fu_7600_p2; +reg [15:0] sub_ln703_857_reg_12835; +wire [15:0] sub_ln703_858_fu_7605_p2; +reg [15:0] sub_ln703_858_reg_12840; +wire [15:0] add_ln703_934_fu_7610_p2; +reg [15:0] add_ln703_934_reg_12845; +wire [15:0] sub_ln703_859_fu_7615_p2; +reg [15:0] sub_ln703_859_reg_12850; +wire [15:0] add_ln703_936_fu_7634_p2; +reg [15:0] add_ln703_936_reg_12855; +wire [15:0] sub_ln703_863_fu_7639_p2; +reg [15:0] sub_ln703_863_reg_12860; +wire [15:0] sub_ln703_865_fu_7649_p2; +reg [15:0] sub_ln703_865_reg_12865; +wire [15:0] sub_ln703_866_fu_7654_p2; +reg [15:0] sub_ln703_866_reg_12870; +wire [15:0] add_ln703_938_fu_7663_p2; +reg [15:0] add_ln703_938_reg_12875; +wire [15:0] sub_ln703_867_fu_7669_p2; +reg [15:0] sub_ln703_867_reg_12880; +wire [15:0] sub_ln703_868_fu_7674_p2; +reg [15:0] sub_ln703_868_reg_12885; +wire [15:0] add_ln703_939_fu_7679_p2; +reg [15:0] add_ln703_939_reg_12890; +wire [15:0] sub_ln703_870_fu_7685_p2; +reg [15:0] sub_ln703_870_reg_12895; +wire [15:0] sub_ln703_873_fu_7710_p2; +reg [15:0] sub_ln703_873_reg_12900; +wire [15:0] add_ln703_943_fu_7719_p2; +reg [15:0] add_ln703_943_reg_12905; +wire [15:0] sub_ln703_875_fu_7730_p2; +reg [15:0] sub_ln703_875_reg_12910; +wire [15:0] sub_ln703_879_fu_7735_p2; +reg [15:0] sub_ln703_879_reg_12915; +wire [15:0] sub_ln703_880_fu_7750_p2; +reg [15:0] sub_ln703_880_reg_12920; +wire [15:0] sub_ln703_881_fu_7755_p2; +reg [15:0] sub_ln703_881_reg_12925; +wire [15:0] add_ln703_948_fu_7760_p2; +reg [15:0] add_ln703_948_reg_12930; +wire [15:0] sub_ln703_892_fu_7780_p2; +reg [15:0] sub_ln703_892_reg_12935; +wire [15:0] sub_ln703_893_fu_7785_p2; +reg [15:0] sub_ln703_893_reg_12940; +wire [15:0] sub_ln703_894_fu_7790_p2; +reg [15:0] sub_ln703_894_reg_12945; +wire [15:0] sub_ln703_895_fu_7795_p2; +reg [15:0] sub_ln703_895_reg_12950; +wire [15:0] sub_ln703_898_fu_7805_p2; +reg [15:0] sub_ln703_898_reg_12955; +wire [15:0] sub_ln703_904_fu_7810_p2; +reg [15:0] sub_ln703_904_reg_12960; +wire [15:0] add_ln703_958_fu_7827_p2; +reg [15:0] add_ln703_958_reg_12965; +wire [15:0] sub_ln703_911_fu_7833_p2; +reg [15:0] sub_ln703_911_reg_12970; +wire [15:0] sub_ln703_917_fu_7838_p2; +reg [15:0] sub_ln703_917_reg_12975; +wire [15:0] sub_ln703_922_fu_7843_p2; +reg [15:0] sub_ln703_922_reg_12980; +wire [15:0] add_ln703_964_fu_7848_p2; +reg [15:0] add_ln703_964_reg_12985; +wire [15:0] acc_21_V_fu_7872_p2; +reg [15:0] acc_21_V_reg_12991; +wire ap_block_pp0_stage0; +wire [15:0] sub_ln703_5_fu_564_p2; +wire [15:0] add_ln703_143_fu_585_p2; +wire [15:0] add_ln703_142_fu_581_p2; +wire [15:0] add_ln703_133_fu_603_p2; +wire [15:0] sub_ln703_7_fu_607_p2; +wire [15:0] sub_ln703_9_fu_611_p2; +wire [15:0] add_ln703_136_fu_623_p2; +wire [15:0] add_ln703_139_fu_636_p2; +wire [15:0] sub_ln703_12_fu_627_p2; +wire [15:0] sub_ln703_13_fu_689_p2; +wire [15:0] sub_ln703_14_fu_693_p2; +wire [15:0] add_ln703_137_fu_697_p2; +wire [15:0] add_ln703_138_fu_701_p2; +wire [15:0] sub_ln703_19_fu_705_p2; +wire [15:0] sub_ln703_22_fu_713_p2; +wire [15:0] sub_ln703_24_fu_717_p2; +wire [15:0] sub_ln703_25_fu_722_p2; +wire [15:0] sub_ln703_27_fu_732_p2; +wire [15:0] add_ln703_145_fu_736_p2; +wire [15:0] add_ln703_146_fu_741_p2; +wire [15:0] add_ln703_147_fu_745_p2; +wire [15:0] sub_ln703_29_fu_749_p2; +wire [15:0] sub_ln703_30_fu_753_p2; +wire [15:0] add_ln703_148_fu_757_p2; +wire [15:0] sub_ln703_31_fu_761_p2; +wire [15:0] sub_ln703_32_fu_765_p2; +wire [15:0] sub_ln703_33_fu_769_p2; +wire [15:0] add_ln703_155_fu_868_p2; +wire [15:0] add_ln703_149_fu_773_p2; +wire [15:0] sub_ln703_34_fu_778_p2; +wire [15:0] add_ln703_150_fu_782_p2; +wire [15:0] sub_ln703_35_fu_787_p2; +wire [15:0] add_ln703_151_fu_791_p2; +wire [15:0] sub_ln703_37_fu_800_p2; +wire [15:0] add_ln703_152_fu_804_p2; +wire [15:0] sub_ln703_26_fu_727_p2; +wire [15:0] sub_ln703_41_fu_829_p2; +wire [15:0] add_ln703_154_fu_843_p2; +wire [15:0] sub_ln703_44_fu_848_p2; +wire [15:0] sub_ln703_45_fu_853_p2; +wire [15:0] add_ln703_156_fu_872_p2; +wire [15:0] sub_ln703_48_fu_877_p2; +wire [15:0] sub_ln703_49_fu_882_p2; +wire [15:0] sub_ln703_21_fu_709_p2; +wire [15:0] add_ln703_166_fu_962_p2; +wire [15:0] sub_ln703_51_fu_897_p2; +wire [15:0] sub_ln703_36_fu_795_p2; +wire [15:0] add_ln703_160_fu_902_p2; +wire [15:0] sub_ln703_60_fu_927_p2; +wire [15:0] sub_ln703_61_fu_932_p2; +wire [15:0] add_ln703_164_fu_937_p2; +wire [15:0] add_ln703_180_fu_1011_p2; +wire [15:0] add_ln703_178_fu_1007_p2; +wire [15:0] sub_ln703_47_fu_863_p2; +wire [15:0] add_ln703_165_fu_952_p2; +wire [15:0] add_ln703_168_fu_967_p2; +wire [15:0] sub_ln703_50_fu_887_p2; +wire [15:0] add_ln703_187_fu_1041_p2; +wire [15:0] add_ln703_189_fu_1045_p2; +wire [15:0] sub_ln703_52_fu_907_p2; +wire [15:0] sub_ln703_46_fu_858_p2; +wire [15:0] sub_ln703_42_fu_833_p2; +wire [15:0] sub_ln703_54_fu_1086_p2; +wire [15:0] sub_ln703_55_fu_1090_p2; +wire [15:0] sub_ln703_56_fu_1094_p2; +wire [15:0] add_ln703_163_fu_1098_p2; +wire [15:0] sub_ln703_57_fu_1102_p2; +wire [15:0] sub_ln703_65_fu_1110_p2; +wire [15:0] add_ln703_174_fu_1114_p2; +wire [15:0] sub_ln703_67_fu_1119_p2; +wire [15:0] add_ln703_175_fu_1123_p2; +wire [15:0] add_ln703_176_fu_1128_p2; +wire [15:0] sub_ln703_69_fu_1138_p2; +wire [15:0] sub_ln703_59_fu_1106_p2; +wire [15:0] add_ln703_184_fu_1143_p2; +wire [15:0] sub_ln703_72_fu_1147_p2; +wire [15:0] sub_ln703_74_fu_1151_p2; +wire [15:0] sub_ln703_77_fu_1159_p2; +wire [15:0] sub_ln703_78_fu_1164_p2; +wire [15:0] sub_ln703_79_fu_1168_p2; +wire [15:0] add_ln703_190_fu_1172_p2; +wire [15:0] add_ln703_191_fu_1176_p2; +wire [15:0] add_ln703_193_fu_1180_p2; +wire [15:0] sub_ln703_80_fu_1184_p2; +wire [15:0] add_ln703_194_fu_1189_p2; +wire [15:0] sub_ln703_82_fu_1199_p2; +wire [15:0] sub_ln703_68_fu_1133_p2; +wire [15:0] add_ln703_195_fu_1204_p2; +wire [15:0] add_ln703_197_fu_1209_p2; +wire [15:0] add_ln703_199_fu_1213_p2; +wire [15:0] sub_ln703_83_fu_1218_p2; +wire [15:0] sub_ln703_84_fu_1222_p2; +wire [15:0] add_ln703_200_fu_1226_p2; +wire [15:0] add_ln703_214_fu_1349_p2; +wire [15:0] sub_ln703_85_fu_1230_p2; +wire [15:0] sub_ln703_87_fu_1238_p2; +wire [15:0] add_ln703_201_fu_1243_p2; +wire [15:0] sub_ln703_88_fu_1248_p2; +wire [15:0] sub_ln703_89_fu_1252_p2; +wire [15:0] sub_ln703_90_fu_1257_p2; +wire [15:0] sub_ln703_91_fu_1261_p2; +wire [15:0] add_ln703_217_fu_1393_p2; +wire [15:0] sub_ln703_76_fu_1155_p2; +wire [15:0] add_ln703_202_fu_1265_p2; +wire [15:0] add_ln703_203_fu_1270_p2; +wire [15:0] sub_ln703_93_fu_1275_p2; +wire [15:0] sub_ln703_94_fu_1280_p2; +wire [15:0] add_ln703_206_fu_1290_p2; +wire [15:0] sub_ln703_97_fu_1304_p2; +wire [15:0] sub_ln703_81_fu_1194_p2; +wire [15:0] sub_ln703_99_fu_1324_p2; +wire [15:0] add_ln703_211_fu_1339_p2; +wire [15:0] sub_ln703_102_fu_1344_p2; +wire [15:0] add_ln703_215_fu_1353_p2; +wire [15:0] sub_ln703_103_fu_1363_p2; +wire [15:0] sub_ln703_104_fu_1368_p2; +wire [15:0] sub_ln703_105_fu_1373_p2; +wire [15:0] add_ln703_219_fu_1397_p2; +wire [15:0] add_ln703_221_fu_1402_p2; +wire [15:0] sub_ln703_111_fu_1417_p2; +wire [15:0] sub_ln703_112_fu_1422_p2; +wire [15:0] sub_ln703_113_fu_1427_p2; +wire [15:0] sub_ln703_119_fu_1442_p2; +wire [15:0] add_ln703_237_fu_1516_p2; +wire [15:0] sub_ln703_100_fu_1329_p2; +wire [15:0] sub_ln703_101_fu_1334_p2; +wire [15:0] add_ln703_225_fu_1452_p2; +wire [15:0] sub_ln703_86_fu_1234_p2; +wire [15:0] add_ln703_242_fu_1537_p2; +wire [15:0] add_ln703_228_fu_1477_p2; +wire [15:0] sub_ln703_126_fu_1487_p2; +wire [15:0] add_ln703_232_fu_1492_p2; +wire [15:0] sub_ln703_110_fu_1412_p2; +wire [15:0] sub_ln703_95_fu_1285_p2; +wire [15:0] add_ln703_248_fu_1569_p2; +wire [15:0] sub_ln703_129_fu_1506_p2; +wire [15:0] add_ln703_259_fu_1589_p2; +wire [15:0] add_ln703_256_fu_1585_p2; +wire [15:0] add_ln703_240_fu_1526_p2; +wire [15:0] sub_ln703_120_fu_1447_p2; +wire [15:0] add_ln703_244_fu_1542_p2; +wire [15:0] add_ln703_222_fu_1626_p2; +wire [15:0] sub_ln703_114_fu_1630_p2; +wire [15:0] sub_ln703_118_fu_1642_p2; +wire [15:0] sub_ln703_121_fu_1646_p2; +wire [15:0] sub_ln703_124_fu_1650_p2; +wire [15:0] add_ln703_229_fu_1654_p2; +wire [15:0] add_ln703_230_fu_1658_p2; +wire [15:0] sub_ln703_127_fu_1662_p2; +wire [15:0] sub_ln703_130_fu_1666_p2; +wire [15:0] add_ln703_234_fu_1671_p2; +wire [15:0] add_ln703_235_fu_1676_p2; +wire [15:0] sub_ln703_131_fu_1680_p2; +wire [15:0] sub_ln703_117_fu_1638_p2; +wire [15:0] add_ln703_241_fu_1693_p2; +wire [15:0] sub_ln703_135_fu_1698_p2; +wire [15:0] sub_ln703_136_fu_1702_p2; +wire [15:0] sub_ln703_139_fu_1711_p2; +wire [15:0] sub_ln703_140_fu_1716_p2; +wire [15:0] add_ln703_245_fu_1721_p2; +wire [15:0] sub_ln703_145_fu_1734_p2; +wire [15:0] sub_ln703_148_fu_1743_p2; +wire [15:0] sub_ln703_149_fu_1748_p2; +wire [15:0] add_ln703_251_fu_1753_p2; +wire [15:0] add_ln703_253_fu_1758_p2; +wire [15:0] sub_ln703_132_fu_1684_p2; +wire [15:0] sub_ln703_150_fu_1763_p2; +wire [15:0] sub_ln703_151_fu_1767_p2; +wire [15:0] add_ln703_263_fu_1771_p2; +wire [15:0] sub_ln703_134_fu_1689_p2; +wire [15:0] add_ln703_269_fu_1891_p2; +wire [15:0] sub_ln703_156_fu_1785_p2; +wire [15:0] sub_ln703_157_fu_1790_p2; +wire [15:0] sub_ln703_138_fu_1706_p2; +wire [15:0] sub_ln703_160_fu_1804_p2; +wire [15:0] sub_ln703_161_fu_1809_p2; +wire [15:0] sub_ln703_162_fu_1813_p2; +wire [15:0] sub_ln703_143_fu_1725_p2; +wire [15:0] sub_ln703_163_fu_1817_p2; +wire [15:0] add_ln703_264_fu_1821_p2; +wire [15:0] sub_ln703_164_fu_1826_p2; +wire [15:0] sub_ln703_165_fu_1830_p2; +wire [15:0] sub_ln703_168_fu_1844_p2; +wire [15:0] sub_ln703_116_fu_1634_p2; +wire [15:0] add_ln703_281_fu_1969_p2; +wire [15:0] add_ln703_279_fu_1964_p2; +wire [15:0] sub_ln703_169_fu_1849_p2; +wire [15:0] add_ln703_266_fu_1854_p2; +wire [15:0] sub_ln703_172_fu_1868_p2; +wire [15:0] sub_ln703_173_fu_1873_p2; +wire [15:0] sub_ln703_174_fu_1877_p2; +wire [15:0] add_ln703_268_fu_1886_p2; +wire [15:0] sub_ln703_153_fu_1775_p2; +wire [15:0] add_ln703_271_fu_1895_p2; +wire [15:0] sub_ln703_155_fu_1780_p2; +wire [15:0] sub_ln703_178_fu_1909_p2; +wire [15:0] add_ln703_273_fu_1914_p2; +wire [15:0] sub_ln703_158_fu_1794_p2; +wire [15:0] sub_ln703_179_fu_1919_p2; +wire [15:0] add_ln703_274_fu_1924_p2; +wire [15:0] sub_ln703_180_fu_1929_p2; +wire [15:0] add_ln703_276_fu_1934_p2; +wire [15:0] add_ln703_277_fu_1939_p2; +wire [15:0] sub_ln703_144_fu_1730_p2; +wire [15:0] add_ln703_291_fu_2064_p2; +wire [15:0] sub_ln703_181_fu_1944_p2; +wire [15:0] add_ln703_278_fu_1954_p2; +wire [15:0] sub_ln703_147_fu_1738_p2; +wire [15:0] sub_ln703_167_fu_1839_p2; +wire [15:0] add_ln703_282_fu_1973_p2; +wire [15:0] sub_ln703_171_fu_1864_p2; +wire [15:0] sub_ln703_185_fu_1989_p2; +wire [15:0] sub_ln703_188_fu_2004_p2; +wire [15:0] sub_ln703_189_fu_2014_p2; +wire [15:0] sub_ln703_176_fu_1900_p2; +wire [15:0] add_ln703_287_fu_2019_p2; +wire [15:0] sub_ln703_177_fu_1904_p2; +wire [15:0] sub_ln703_190_fu_2024_p2; +wire [15:0] sub_ln703_159_fu_1799_p2; +wire [15:0] sub_ln703_192_fu_2044_p2; +wire [15:0] sub_ln703_195_fu_2059_p2; +wire [15:0] add_ln703_293_fu_2069_p2; +wire [15:0] sub_ln703_182_fu_1949_p2; +wire [15:0] sub_ln703_197_fu_2079_p2; +wire [15:0] add_ln703_316_fu_2178_p2; +wire [15:0] sub_ln703_187_fu_1999_p2; +wire [15:0] sub_ln703_193_fu_2049_p2; +wire [15:0] add_ln703_314_fu_2167_p2; +wire [15:0] sub_ln703_170_fu_1859_p2; +wire [15:0] add_ln703_327_fu_2204_p2; +wire [15:0] add_ln703_325_fu_2199_p2; +wire [15:0] add_ln703_317_fu_2182_p2; +wire [15:0] sub_ln703_175_fu_1881_p2; +wire [15:0] add_ln703_330_fu_2219_p2; +wire [15:0] add_ln703_296_fu_2238_p2; +wire [15:0] add_ln703_298_fu_2242_p2; +wire [15:0] sub_ln703_199_fu_2246_p2; +wire [15:0] add_ln703_301_fu_2250_p2; +wire [15:0] add_ln703_305_fu_2254_p2; +wire [15:0] sub_ln703_201_fu_2258_p2; +wire [15:0] sub_ln703_205_fu_2262_p2; +wire [15:0] sub_ln703_206_fu_2266_p2; +wire [15:0] add_ln703_312_fu_2270_p2; +wire [15:0] sub_ln703_207_fu_2274_p2; +wire [15:0] sub_ln703_211_fu_2278_p2; +wire [15:0] sub_ln703_213_fu_2282_p2; +wire [15:0] sub_ln703_215_fu_2292_p2; +wire [15:0] sub_ln703_216_fu_2296_p2; +wire [15:0] add_ln703_315_fu_2300_p2; +wire [15:0] sub_ln703_217_fu_2305_p2; +wire [15:0] sub_ln703_218_fu_2310_p2; +wire [15:0] sub_ln703_220_fu_2318_p2; +wire [15:0] add_ln703_318_fu_2323_p2; +wire [15:0] add_ln703_319_fu_2328_p2; +wire [15:0] sub_ln703_221_fu_2332_p2; +wire [15:0] add_ln703_320_fu_2336_p2; +wire [15:0] sub_ln703_222_fu_2340_p2; +wire [15:0] sub_ln703_224_fu_2348_p2; +wire [15:0] add_ln703_321_fu_2353_p2; +wire [15:0] sub_ln703_225_fu_2358_p2; +wire [15:0] sub_ln703_227_fu_2368_p2; +wire [15:0] sub_ln703_228_fu_2372_p2; +wire [15:0] sub_ln703_229_fu_2376_p2; +wire [15:0] sub_ln703_231_fu_2381_p2; +wire [15:0] sub_ln703_232_fu_2385_p2; +wire [15:0] sub_ln703_235_fu_2400_p2; +wire [15:0] add_ln703_324_fu_2405_p2; +wire [15:0] add_ln703_329_fu_2410_p2; +wire [15:0] sub_ln703_219_fu_2314_p2; +wire [15:0] sub_ln703_236_fu_2415_p2; +wire [15:0] add_ln703_335_fu_2420_p2; +wire [15:0] sub_ln703_238_fu_2424_p2; +wire [15:0] sub_ln703_239_fu_2429_p2; +wire [15:0] sub_ln703_240_fu_2434_p2; +wire [15:0] sub_ln703_241_fu_2439_p2; +wire [15:0] sub_ln703_242_fu_2444_p2; +wire [15:0] sub_ln703_223_fu_2344_p2; +wire [15:0] add_ln703_336_fu_2449_p2; +wire [15:0] sub_ln703_243_fu_2454_p2; +wire [15:0] add_ln703_337_fu_2459_p2; +wire [15:0] add_ln703_339_fu_2464_p2; +wire [15:0] sub_ln703_244_fu_2468_p2; +wire [15:0] add_ln703_349_fu_2598_p2; +wire [15:0] add_ln703_347_fu_2594_p2; +wire [15:0] sub_ln703_245_fu_2472_p2; +wire [15:0] sub_ln703_247_fu_2482_p2; +wire [15:0] sub_ln703_248_fu_2487_p2; +wire [15:0] add_ln703_340_fu_2491_p2; +wire [15:0] sub_ln703_252_fu_2511_p2; +wire [15:0] sub_ln703_253_fu_2515_p2; +wire [15:0] sub_ln703_255_fu_2530_p2; +wire [15:0] sub_ln703_258_fu_2544_p2; +wire [15:0] sub_ln703_259_fu_2549_p2; +wire [15:0] add_ln703_343_fu_2554_p2; +wire [15:0] add_ln703_345_fu_2564_p2; +wire [15:0] sub_ln703_226_fu_2363_p2; +wire [15:0] add_ln703_358_fu_2672_p2; +wire [15:0] sub_ln703_264_fu_2584_p2; +wire [15:0] add_ln703_351_fu_2608_p2; +wire [15:0] sub_ln703_266_fu_2618_p2; +wire [15:0] sub_ln703_267_fu_2623_p2; +wire [15:0] add_ln703_355_fu_2642_p2; +wire [15:0] sub_ln703_276_fu_2667_p2; +wire [15:0] add_ln703_361_fu_2683_p2; +wire [15:0] sub_ln703_283_fu_2693_p2; +wire [15:0] sub_ln703_233_fu_2390_p2; +wire [15:0] add_ln703_370_fu_2728_p2; +wire [15:0] add_ln703_368_fu_2723_p2; +wire [15:0] sub_ln703_260_fu_2559_p2; +wire [15:0] sub_ln703_214_fu_2287_p2; +wire [15:0] add_ln703_398_fu_2747_p2; +wire [15:0] add_ln703_523_fu_2770_p2; +wire [15:0] sub_ln703_268_fu_2783_p2; +wire [15:0] sub_ln703_269_fu_2787_p2; +wire [15:0] sub_ln703_271_fu_2791_p2; +wire [15:0] add_ln703_353_fu_2795_p2; +wire [15:0] add_ln703_357_fu_2811_p2; +wire [15:0] sub_ln703_279_fu_2815_p2; +wire [15:0] sub_ln703_280_fu_2819_p2; +wire [15:0] add_ln703_363_fu_2823_p2; +wire [15:0] add_ln703_364_fu_2831_p2; +wire [15:0] sub_ln703_285_fu_2836_p2; +wire [15:0] add_ln703_365_fu_2841_p2; +wire [15:0] sub_ln703_286_fu_2845_p2; +wire [15:0] sub_ln703_290_fu_2859_p2; +wire [15:0] sub_ln703_273_fu_2799_p2; +wire [15:0] sub_ln703_291_fu_2863_p2; +wire [15:0] sub_ln703_292_fu_2867_p2; +wire [15:0] add_ln703_366_fu_2871_p2; +wire [15:0] sub_ln703_295_fu_2880_p2; +wire [15:0] sub_ln703_297_fu_2884_p2; +wire [15:0] sub_ln703_298_fu_2889_p2; +wire [15:0] sub_ln703_299_fu_2894_p2; +wire [15:0] sub_ln703_300_fu_2898_p2; +wire [15:0] add_ln703_367_fu_2903_p2; +wire [15:0] sub_ln703_302_fu_2907_p2; +wire [15:0] add_ln703_385_fu_3011_p2; +wire [15:0] add_ln703_383_fu_3007_p2; +wire [15:0] sub_ln703_303_fu_2912_p2; +wire [15:0] sub_ln703_304_fu_2917_p2; +wire [15:0] add_ln703_372_fu_2927_p2; +wire [15:0] sub_ln703_306_fu_2931_p2; +wire [15:0] add_ln703_374_fu_2936_p2; +wire [15:0] add_ln703_387_fu_3046_p2; +wire [15:0] sub_ln703_307_fu_2941_p2; +wire [15:0] sub_ln703_308_fu_2946_p2; +wire [15:0] sub_ln703_309_fu_2951_p2; +wire [15:0] add_ln703_377_fu_2956_p2; +wire [15:0] add_ln703_378_fu_2960_p2; +wire [15:0] sub_ln703_277_fu_2803_p2; +wire [15:0] add_ln703_392_fu_3081_p2; +wire [15:0] add_ln703_379_fu_2964_p2; +wire [15:0] add_ln703_380_fu_2969_p2; +wire [15:0] add_ln703_381_fu_2973_p2; +wire [15:0] add_ln703_382_fu_2983_p2; +wire [15:0] sub_ln703_311_fu_2988_p2; +wire [15:0] sub_ln703_282_fu_2827_p2; +wire [15:0] add_ln703_395_fu_3116_p2; +wire [15:0] sub_ln703_312_fu_2993_p2; +wire [15:0] add_ln703_403_fu_3131_p2; +wire [15:0] sub_ln703_314_fu_3003_p2; +wire [15:0] add_ln703_406_fu_3145_p2; +wire [15:0] sub_ln703_316_fu_3026_p2; +wire [15:0] sub_ln703_305_fu_2922_p2; +wire [15:0] sub_ln703_288_fu_2854_p2; +wire [15:0] add_ln703_414_fu_3165_p2; +wire [15:0] sub_ln703_318_fu_3036_p2; +wire [15:0] add_ln703_391_fu_3061_p2; +wire [15:0] sub_ln703_321_fu_3066_p2; +wire [15:0] sub_ln703_322_fu_3071_p2; +wire [15:0] sub_ln703_323_fu_3076_p2; +wire [15:0] add_ln703_394_fu_3086_p2; +wire [15:0] sub_ln703_324_fu_3091_p2; +wire [15:0] sub_ln703_325_fu_3096_p2; +wire [15:0] sub_ln703_327_fu_3106_p2; +wire [15:0] add_ln703_397_fu_3121_p2; +wire [15:0] add_ln703_419_fu_3225_p2; +wire [15:0] add_ln703_404_fu_3135_p2; +wire [15:0] sub_ln703_331_fu_3140_p2; +wire [15:0] add_ln703_413_fu_3160_p2; +wire [15:0] sub_ln703_287_fu_2849_p2; +wire [15:0] add_ln703_425_fu_3254_p2; +wire [15:0] add_ln703_423_fu_3249_p2; +wire [15:0] sub_ln703_317_fu_3031_p2; +wire [15:0] sub_ln703_337_fu_3190_p2; +wire [15:0] sub_ln703_338_fu_3195_p2; +wire [15:0] sub_ln703_294_fu_2875_p2; +wire [15:0] add_ln703_432_fu_3279_p2; +wire [15:0] add_ln703_418_fu_3210_p2; +wire [15:0] add_ln703_421_fu_3229_p2; +wire [15:0] add_ln703_422_fu_3239_p2; +wire [15:0] add_ln703_428_fu_3264_p2; +wire [15:0] sub_ln703_320_fu_3056_p2; +wire [15:0] sub_ln703_310_fu_2978_p2; +wire [15:0] sub_ln703_357_fu_3295_p2; +wire [15:0] sub_ln703_319_fu_3041_p2; +wire [15:0] sub_ln703_329_fu_3126_p2; +wire [15:0] sub_ln703_278_fu_2807_p2; +wire [15:0] sub_ln703_332_fu_3376_p2; +wire [15:0] add_ln703_411_fu_3380_p2; +wire [15:0] sub_ln703_335_fu_3384_p2; +wire [15:0] sub_ln703_346_fu_3396_p2; +wire [15:0] sub_ln703_349_fu_3410_p2; +wire [15:0] add_ln703_429_fu_3418_p2; +wire [15:0] add_ln703_430_fu_3423_p2; +wire [15:0] sub_ln703_352_fu_3427_p2; +wire [15:0] sub_ln703_354_fu_3431_p2; +wire [15:0] sub_ln703_355_fu_3435_p2; +wire [15:0] sub_ln703_341_fu_3388_p2; +wire [15:0] add_ln703_436_fu_3439_p2; +wire [15:0] add_ln703_437_fu_3443_p2; +wire [15:0] sub_ln703_348_fu_3405_p2; +wire [15:0] sub_ln703_359_fu_3448_p2; +wire [15:0] sub_ln703_360_fu_3453_p2; +wire [15:0] sub_ln703_351_fu_3414_p2; +wire [15:0] add_ln703_459_fu_3557_p2; +wire [15:0] add_ln703_440_fu_3466_p2; +wire [15:0] sub_ln703_364_fu_3470_p2; +wire [15:0] add_ln703_441_fu_3480_p2; +wire [15:0] sub_ln703_366_fu_3484_p2; +wire [15:0] sub_ln703_367_fu_3488_p2; +wire [15:0] sub_ln703_368_fu_3493_p2; +wire [15:0] sub_ln703_369_fu_3497_p2; +wire [15:0] add_ln703_442_fu_3502_p2; +wire [15:0] add_ln703_444_fu_3506_p2; +wire [15:0] add_ln703_448_fu_3511_p2; +wire [15:0] sub_ln703_370_fu_3515_p2; +wire [15:0] add_ln703_450_fu_3520_p2; +wire [15:0] sub_ln703_330_fu_3372_p2; +wire [15:0] add_ln703_467_fu_3635_p2; +wire [15:0] add_ln703_465_fu_3630_p2; +wire [15:0] add_ln703_452_fu_3524_p2; +wire [15:0] add_ln703_453_fu_3528_p2; +wire [15:0] sub_ln703_372_fu_3532_p2; +wire [15:0] add_ln703_455_fu_3537_p2; +wire [15:0] add_ln703_456_fu_3542_p2; +wire [15:0] add_ln703_458_fu_3552_p2; +wire [15:0] add_ln703_461_fu_3561_p2; +wire [15:0] sub_ln703_363_fu_3461_p2; +wire [15:0] add_ln703_462_fu_3571_p2; +wire [15:0] sub_ln703_375_fu_3576_p2; +wire [15:0] add_ln703_463_fu_3581_p2; +wire [15:0] add_ln703_464_fu_3586_p2; +wire [15:0] sub_ln703_377_fu_3596_p2; +wire [15:0] sub_ln703_378_fu_3601_p2; +wire [15:0] sub_ln703_379_fu_3606_p2; +wire [15:0] sub_ln703_380_fu_3611_p2; +wire [15:0] sub_ln703_381_fu_3616_p2; +wire [15:0] sub_ln703_343_fu_3392_p2; +wire [15:0] add_ln703_479_fu_3735_p2; +wire [15:0] sub_ln703_382_fu_3621_p2; +wire [15:0] sub_ln703_383_fu_3626_p2; +wire [15:0] add_ln703_468_fu_3639_p2; +wire [15:0] sub_ln703_385_fu_3650_p2; +wire [15:0] sub_ln703_361_fu_3457_p2; +wire [15:0] add_ln703_489_fu_3771_p2; +wire [15:0] sub_ln703_388_fu_3670_p2; +wire [15:0] sub_ln703_389_fu_3675_p2; +wire [15:0] add_ln703_474_fu_3680_p2; +wire [15:0] sub_ln703_374_fu_3566_p2; +wire [15:0] sub_ln703_365_fu_3475_p2; +wire [15:0] add_ln703_494_fu_3801_p2; +wire [15:0] sub_ln703_391_fu_3695_p2; +wire [15:0] sub_ln703_392_fu_3700_p2; +wire [15:0] add_ln703_500_fu_3821_p2; +wire [15:0] add_ln703_504_fu_3830_p2; +wire [15:0] add_ln703_505_fu_3834_p2; +wire [15:0] add_ln703_501_fu_3825_p2; +wire [15:0] add_ln703_477_fu_3715_p2; +wire [15:0] add_ln703_482_fu_3740_p2; +wire [15:0] add_ln703_487_fu_3756_p2; +wire [15:0] add_ln703_488_fu_3766_p2; +wire [15:0] add_ln703_491_fu_3776_p2; +wire [15:0] add_ln703_511_fu_3874_p2; +wire [15:0] add_ln703_509_fu_3870_p2; +wire [15:0] add_ln703_493_fu_3796_p2; +wire [15:0] sub_ln703_396_fu_3725_p2; +wire [15:0] sub_ln703_397_fu_3746_p2; +wire [15:0] sub_ln703_398_fu_3751_p2; +wire [15:0] add_ln703_536_fu_3908_p2; +wire [15:0] add_ln703_532_fu_3904_p2; +wire [15:0] sub_ln703_373_fu_3547_p2; +wire [15:0] add_ln703_542_fu_3918_p2; +wire [15:0] sub_ln703_376_fu_3591_p2; +wire [15:0] add_ln703_553_fu_3928_p2; +wire [15:0] add_ln703_519_fu_3899_p2; +wire [15:0] sub_ln703_347_fu_3400_p2; +wire [15:0] add_ln703_564_fu_3947_p2; +wire [15:0] sub_ln703_400_fu_3973_p2; +wire [15:0] sub_ln703_404_fu_3977_p2; +wire [15:0] sub_ln703_407_fu_3985_p2; +wire [15:0] sub_ln703_409_fu_3989_p2; +wire [15:0] sub_ln703_410_fu_3993_p2; +wire [15:0] sub_ln703_413_fu_3997_p2; +wire [15:0] add_ln703_529_fu_4071_p2; +wire [15:0] add_ln703_508_fu_4006_p2; +wire [15:0] add_ln703_539_fu_4085_p2; +wire [15:0] sub_ln703_417_fu_4010_p2; +wire [15:0] sub_ln703_418_fu_4014_p2; +wire [15:0] sub_ln703_420_fu_4019_p2; +wire [15:0] sub_ln703_421_fu_4023_p2; +wire [15:0] sub_ln703_422_fu_4027_p2; +wire [15:0] sub_ln703_423_fu_4031_p2; +wire [15:0] add_ln703_513_fu_4035_p2; +wire [15:0] sub_ln703_424_fu_4040_p2; +wire [15:0] sub_ln703_426_fu_4049_p2; +wire [15:0] sub_ln703_427_fu_4054_p2; +wire [15:0] add_ln703_520_fu_4058_p2; +wire [15:0] add_ln703_521_fu_4062_p2; +wire [15:0] add_ln703_522_fu_4067_p2; +wire [15:0] add_ln703_538_fu_4075_p2; +wire [15:0] sub_ln703_428_fu_4080_p2; +wire [15:0] add_ln703_541_fu_4089_p2; +wire [15:0] add_ln703_546_fu_4094_p2; +wire [15:0] add_ln703_548_fu_4098_p2; +wire [15:0] sub_ln703_429_fu_4102_p2; +wire [15:0] sub_ln703_430_fu_4106_p2; +wire [15:0] add_ln703_550_fu_4111_p2; +wire [15:0] add_ln703_551_fu_4115_p2; +wire [15:0] sub_ln703_431_fu_4120_p2; +wire [15:0] sub_ln703_432_fu_4124_p2; +wire [15:0] add_ln703_552_fu_4139_p2; +wire [15:0] sub_ln703_436_fu_4149_p2; +wire [15:0] sub_ln703_425_fu_4044_p2; +wire [15:0] sub_ln703_437_fu_4154_p2; +wire [15:0] add_ln703_557_fu_4158_p2; +wire [15:0] sub_ln703_439_fu_4168_p2; +wire [15:0] sub_ln703_441_fu_4172_p2; +wire [15:0] sub_ln703_443_fu_4182_p2; +wire [15:0] add_ln703_570_fu_4294_p2; +wire [15:0] sub_ln703_445_fu_4192_p2; +wire [15:0] sub_ln703_446_fu_4197_p2; +wire [15:0] sub_ln703_447_fu_4202_p2; +wire [15:0] add_ln703_558_fu_4216_p2; +wire [15:0] sub_ln703_450_fu_4221_p2; +wire [15:0] sub_ln703_451_fu_4226_p2; +wire [15:0] add_ln703_559_fu_4241_p2; +wire [15:0] sub_ln703_433_fu_4129_p2; +wire [15:0] sub_ln703_406_fu_3981_p2; +wire [15:0] add_ln703_577_fu_4343_p2; +wire [15:0] sub_ln703_454_fu_4246_p2; +wire [15:0] sub_ln703_455_fu_4251_p2; +wire [15:0] sub_ln703_435_fu_4144_p2; +wire [15:0] sub_ln703_456_fu_4255_p2; +wire [15:0] add_ln703_561_fu_4260_p2; +wire [15:0] sub_ln703_457_fu_4265_p2; +wire [15:0] sub_ln703_438_fu_4163_p2; +wire [15:0] add_ln703_562_fu_4275_p2; +wire [15:0] add_ln703_563_fu_4280_p2; +wire [15:0] sub_ln703_460_fu_4289_p2; +wire [15:0] sub_ln703_415_fu_4001_p2; +wire [15:0] add_ln703_589_fu_4408_p2; +wire [15:0] add_ln703_587_fu_4403_p2; +wire [15:0] add_ln703_571_fu_4298_p2; +wire [15:0] sub_ln703_464_fu_4318_p2; +wire [15:0] sub_ln703_465_fu_4328_p2; +wire [15:0] add_ln703_597_fu_4437_p2; +wire [15:0] add_ln703_594_fu_4433_p2; +wire [15:0] add_ln703_576_fu_4338_p2; +wire [15:0] add_ln703_580_fu_4348_p2; +wire [15:0] sub_ln703_471_fu_4378_p2; +wire [15:0] add_ln703_585_fu_4383_p2; +wire [15:0] sub_ln703_473_fu_4388_p2; +wire [15:0] sub_ln703_474_fu_4393_p2; +wire [15:0] sub_ln703_442_fu_4177_p2; +wire [15:0] add_ln703_602_fu_4482_p2; +wire [15:0] add_ln703_607_fu_4491_p2; +wire [15:0] add_ln703_604_fu_4486_p2; +wire [15:0] sub_ln703_444_fu_4187_p2; +wire [15:0] sub_ln703_449_fu_4211_p2; +wire [15:0] add_ln703_614_fu_4506_p2; +wire [15:0] sub_ln703_492_fu_4472_p2; +wire [15:0] add_ln703_608_fu_4495_p2; +wire [15:0] sub_ln703_434_fu_4134_p2; +wire [15:0] add_ln703_631_fu_4526_p2; +wire [15:0] sub_ln703_459_fu_4284_p2; +wire [15:0] add_ln703_574_fu_4566_p2; +wire [15:0] sub_ln703_472_fu_4570_p2; +wire [15:0] sub_ln703_477_fu_4578_p2; +wire [15:0] sub_ln703_478_fu_4582_p2; +wire [15:0] sub_ln703_479_fu_4586_p2; +wire [15:0] sub_ln703_480_fu_4590_p2; +wire [15:0] sub_ln703_481_fu_4595_p2; +wire [15:0] sub_ln703_484_fu_4599_p2; +wire [15:0] sub_ln703_485_fu_4603_p2; +wire [15:0] sub_ln703_486_fu_4607_p2; +wire [15:0] add_ln703_601_fu_4620_p2; +wire [15:0] sub_ln703_493_fu_4624_p2; +wire [15:0] add_ln703_611_fu_4628_p2; +wire [15:0] sub_ln703_494_fu_4632_p2; +wire [15:0] sub_ln703_476_fu_4574_p2; +wire [15:0] add_ln703_612_fu_4640_p2; +wire [15:0] add_ln703_613_fu_4645_p2; +wire [15:0] sub_ln703_496_fu_4650_p2; +wire [15:0] sub_ln703_497_fu_4654_p2; +wire [15:0] sub_ln703_498_fu_4659_p2; +wire [15:0] sub_ln703_466_fu_4562_p2; +wire [15:0] add_ln703_624_fu_4754_p2; +wire [15:0] sub_ln703_500_fu_4668_p2; +wire [15:0] sub_ln703_501_fu_4672_p2; +wire [15:0] add_ln703_617_fu_4677_p2; +wire [15:0] sub_ln703_502_fu_4682_p2; +wire [15:0] add_ln703_618_fu_4687_p2; +wire [15:0] sub_ln703_487_fu_4611_p2; +wire [15:0] add_ln703_619_fu_4692_p2; +wire [15:0] sub_ln703_489_fu_4615_p2; +wire [15:0] add_ln703_620_fu_4696_p2; +wire [15:0] sub_ln703_504_fu_4700_p2; +wire [15:0] sub_ln703_506_fu_4705_p2; +wire [15:0] sub_ln703_507_fu_4710_p2; +wire [15:0] sub_ln703_508_fu_4715_p2; +wire [15:0] add_ln703_622_fu_4720_p2; +wire [15:0] sub_ln703_511_fu_4735_p2; +wire [15:0] add_ln703_623_fu_4739_p2; +wire [15:0] sub_ln703_512_fu_4744_p2; +wire [15:0] add_ln703_626_fu_4759_p2; +wire [15:0] sub_ln703_499_fu_4663_p2; +wire [15:0] sub_ln703_514_fu_4764_p2; +wire [15:0] add_ln703_627_fu_4769_p2; +wire [15:0] add_ln703_629_fu_4774_p2; +wire [15:0] sub_ln703_515_fu_4778_p2; +wire [15:0] sub_ln703_516_fu_4783_p2; +wire [15:0] sub_ln703_517_fu_4788_p2; +wire [15:0] add_ln703_636_fu_4793_p2; +wire [15:0] sub_ln703_518_fu_4798_p2; +wire [15:0] add_ln703_638_fu_4803_p2; +wire [15:0] sub_ln703_520_fu_4813_p2; +wire [15:0] add_ln703_642_fu_4817_p2; +wire [15:0] add_ln703_643_fu_4821_p2; +wire [15:0] add_ln703_644_fu_4826_p2; +wire [15:0] add_ln703_645_fu_4835_p2; +wire [15:0] sub_ln703_522_fu_4840_p2; +wire [15:0] sub_ln703_523_fu_4845_p2; +wire [15:0] sub_ln703_510_fu_4730_p2; +wire [15:0] sub_ln703_463_fu_4558_p2; +wire [15:0] add_ln703_655_fu_4969_p2; +wire [15:0] add_ln703_653_fu_4964_p2; +wire [15:0] sub_ln703_524_fu_4850_p2; +wire [15:0] sub_ln703_525_fu_4855_p2; +wire [15:0] sub_ln703_513_fu_4749_p2; +wire [15:0] sub_ln703_531_fu_4890_p2; +wire [15:0] sub_ln703_534_fu_4909_p2; +wire [15:0] add_ln703_649_fu_4914_p2; +wire [15:0] add_ln703_663_fu_5009_p2; +wire [15:0] sub_ln703_521_fu_4830_p2; +wire [15:0] add_ln703_656_fu_4973_p2; +wire [15:0] sub_ln703_543_fu_4979_p2; +wire [15:0] add_ln703_658_fu_4989_p2; +wire [15:0] sub_ln703_530_fu_4885_p2; +wire [15:0] add_ln703_675_fu_5048_p2; +wire [15:0] add_ln703_673_fu_5044_p2; +wire [15:0] add_ln703_681_fu_5062_p2; +wire [15:0] add_ln703_678_fu_5058_p2; +wire [15:0] sub_ln703_519_fu_4808_p2; +wire [15:0] add_ln703_683_fu_5072_p2; +wire [15:0] sub_ln703_536_fu_4924_p2; +wire [15:0] sub_ln703_537_fu_4929_p2; +wire [15:0] sub_ln703_528_fu_4875_p2; +wire [15:0] add_ln703_671_fu_5039_p2; +wire [15:0] add_ln703_687_fu_5082_p2; +wire [15:0] add_ln703_689_fu_5087_p2; +wire [15:0] sub_ln703_509_fu_4725_p2; +wire [15:0] sub_ln703_495_fu_4636_p2; +wire [15:0] sub_ln703_546_fu_5142_p2; +wire [15:0] sub_ln703_547_fu_5146_p2; +wire [15:0] add_ln703_659_fu_5150_p2; +wire [15:0] sub_ln703_548_fu_5154_p2; +wire [15:0] sub_ln703_550_fu_5162_p2; +wire [15:0] add_ln703_662_fu_5166_p2; +wire [15:0] sub_ln703_553_fu_5174_p2; +wire [15:0] sub_ln703_554_fu_5178_p2; +wire [15:0] sub_ln703_555_fu_5182_p2; +wire [15:0] add_ln703_669_fu_5186_p2; +wire [15:0] sub_ln703_560_fu_5195_p2; +wire [15:0] sub_ln703_561_fu_5200_p2; +wire [15:0] sub_ln703_562_fu_5205_p2; +wire [15:0] sub_ln703_564_fu_5214_p2; +wire [15:0] sub_ln703_565_fu_5219_p2; +wire [15:0] sub_ln703_566_fu_5223_p2; +wire [15:0] sub_ln703_567_fu_5227_p2; +wire [15:0] sub_ln703_568_fu_5232_p2; +wire [15:0] add_ln703_702_fu_5332_p2; +wire [15:0] sub_ln703_569_fu_5236_p2; +wire [15:0] add_ln703_690_fu_5240_p2; +wire [15:0] add_ln703_692_fu_5245_p2; +wire [15:0] add_ln703_693_fu_5249_p2; +wire [15:0] add_ln703_708_fu_5361_p2; +wire [15:0] add_ln703_694_fu_5254_p2; +wire [15:0] add_ln703_695_fu_5259_p2; +wire [15:0] sub_ln703_570_fu_5263_p2; +wire [15:0] sub_ln703_571_fu_5267_p2; +wire [15:0] sub_ln703_545_fu_5138_p2; +wire [15:0] add_ln703_710_fu_5390_p2; +wire [15:0] add_ln703_696_fu_5272_p2; +wire [15:0] sub_ln703_559_fu_5190_p2; +wire [15:0] sub_ln703_572_fu_5276_p2; +wire [15:0] add_ln703_699_fu_5281_p2; +wire [15:0] add_ln703_700_fu_5285_p2; +wire [15:0] sub_ln703_574_fu_5290_p2; +wire [15:0] sub_ln703_563_fu_5209_p2; +wire [15:0] sub_ln703_576_fu_5299_p2; +wire [15:0] sub_ln703_577_fu_5304_p2; +wire [15:0] add_ln703_701_fu_5313_p2; +wire [15:0] sub_ln703_579_fu_5318_p2; +wire [15:0] sub_ln703_580_fu_5323_p2; +wire [15:0] sub_ln703_581_fu_5328_p2; +wire [15:0] add_ln703_727_fu_5481_p2; +wire [15:0] add_ln703_724_fu_5477_p2; +wire [15:0] sub_ln703_587_fu_5356_p2; +wire [15:0] add_ln703_709_fu_5365_p2; +wire [15:0] sub_ln703_588_fu_5370_p2; +wire [15:0] sub_ln703_590_fu_5380_p2; +wire [15:0] sub_ln703_591_fu_5385_p2; +wire [15:0] add_ln703_712_fu_5395_p2; +wire [15:0] add_ln703_714_fu_5405_p2; +wire [15:0] add_ln703_715_fu_5425_p2; +wire [15:0] add_ln703_716_fu_5429_p2; +wire [15:0] add_ln703_718_fu_5434_p2; +wire [15:0] sub_ln703_596_fu_5444_p2; +wire [15:0] sub_ln703_578_fu_5308_p2; +wire [15:0] sub_ln703_597_fu_5449_p2; +wire [15:0] sub_ln703_599_fu_5459_p2; +wire [15:0] sub_ln703_600_fu_5464_p2; +wire [15:0] add_ln703_720_fu_5469_p2; +wire [15:0] sub_ln703_601_fu_5473_p2; +wire [15:0] sub_ln703_552_fu_5170_p2; +wire [15:0] add_ln703_738_fu_5581_p2; +wire [15:0] add_ln703_736_fu_5576_p2; +wire [15:0] sub_ln703_584_fu_5341_p2; +wire [15:0] sub_ln703_607_fu_5506_p2; +wire [15:0] sub_ln703_592_fu_5400_p2; +wire [15:0] sub_ln703_575_fu_5295_p2; +wire [15:0] add_ln703_745_fu_5606_p2; +wire [15:0] sub_ln703_549_fu_5158_p2; +wire [15:0] add_ln703_750_fu_5616_p2; +wire [15:0] add_ln703_730_fu_5541_p2; +wire [15:0] add_ln703_732_fu_5546_p2; +wire [15:0] sub_ln703_617_fu_5561_p2; +wire [15:0] add_ln703_739_fu_5585_p2; +wire [15:0] add_ln703_741_fu_5591_p2; +wire [15:0] add_ln703_744_fu_5601_p2; +wire [15:0] add_ln703_747_fu_5611_p2; +wire [15:0] add_ln703_753_fu_5621_p2; +wire [15:0] sub_ln703_585_fu_5346_p2; +wire [15:0] sub_ln703_602_fu_5688_p2; +wire [15:0] add_ln703_721_fu_5692_p2; +wire [15:0] add_ln703_729_fu_5700_p2; +wire [15:0] sub_ln703_615_fu_5708_p2; +wire [15:0] sub_ln703_619_fu_5716_p2; +wire [15:0] sub_ln703_620_fu_5721_p2; +wire [15:0] sub_ln703_622_fu_5730_p2; +wire [15:0] sub_ln703_623_fu_5734_p2; +wire [15:0] add_ln703_742_fu_5738_p2; +wire [15:0] sub_ln703_606_fu_5696_p2; +wire [15:0] sub_ln703_625_fu_5742_p2; +wire [15:0] sub_ln703_626_fu_5746_p2; +wire [15:0] sub_ln703_627_fu_5750_p2; +wire [15:0] sub_ln703_611_fu_5704_p2; +wire [15:0] sub_ln703_628_fu_5755_p2; +wire [15:0] add_ln703_748_fu_5759_p2; +wire [15:0] sub_ln703_629_fu_5763_p2; +wire [15:0] sub_ln703_632_fu_5768_p2; +wire [15:0] sub_ln703_633_fu_5772_p2; +wire [15:0] add_ln703_754_fu_5776_p2; +wire [15:0] sub_ln703_635_fu_5780_p2; +wire [15:0] sub_ln703_621_fu_5726_p2; +wire [15:0] sub_ln703_640_fu_5794_p2; +wire [15:0] sub_ln703_642_fu_5804_p2; +wire [15:0] add_ln703_756_fu_5809_p2; +wire [15:0] add_ln703_757_fu_5814_p2; +wire [15:0] add_ln703_759_fu_5818_p2; +wire [15:0] sub_ln703_643_fu_5822_p2; +wire [15:0] sub_ln703_646_fu_5832_p2; +wire [15:0] add_ln703_761_fu_5837_p2; +wire [15:0] add_ln703_769_fu_5946_p2; +wire [15:0] add_ln703_767_fu_5942_p2; +wire [15:0] add_ln703_763_fu_5842_p2; +wire [15:0] sub_ln703_647_fu_5846_p2; +wire [15:0] sub_ln703_649_fu_5851_p2; +wire [15:0] sub_ln703_651_fu_5856_p2; +wire [15:0] add_ln703_764_fu_5861_p2; +wire [15:0] sub_ln703_652_fu_5865_p2; +wire [15:0] sub_ln703_616_fu_5712_p2; +wire [15:0] add_ln703_775_fu_5994_p2; +wire [15:0] sub_ln703_653_fu_5870_p2; +wire [15:0] sub_ln703_654_fu_5875_p2; +wire [15:0] sub_ln703_655_fu_5879_p2; +wire [15:0] sub_ln703_656_fu_5884_p2; +wire [15:0] sub_ln703_636_fu_5784_p2; +wire [15:0] sub_ln703_657_fu_5889_p2; +wire [15:0] add_ln703_785_fu_6038_p2; +wire [15:0] add_ln703_766_fu_5893_p2; +wire [15:0] sub_ln703_658_fu_5898_p2; +wire [15:0] sub_ln703_659_fu_5903_p2; +wire [15:0] sub_ln703_660_fu_5908_p2; +wire [15:0] sub_ln703_664_fu_5928_p2; +wire [15:0] sub_ln703_666_fu_5937_p2; +wire [15:0] add_ln703_771_fu_5961_p2; +wire [15:0] add_ln703_772_fu_5966_p2; +wire [15:0] sub_ln703_668_fu_5971_p2; +wire [15:0] sub_ln703_670_fu_5980_p2; +wire [15:0] add_ln703_774_fu_5985_p2; +wire [15:0] sub_ln703_671_fu_5989_p2; +wire [15:0] add_ln703_777_fu_5999_p2; +wire [15:0] sub_ln703_672_fu_6004_p2; +wire [15:0] sub_ln703_673_fu_6009_p2; +wire [15:0] sub_ln703_674_fu_6014_p2; +wire [15:0] sub_ln703_675_fu_6019_p2; +wire [15:0] add_ln703_781_fu_6029_p2; +wire [15:0] add_ln703_786_fu_6042_p2; +wire [15:0] sub_ln703_677_fu_6047_p2; +wire [15:0] sub_ln703_641_fu_5799_p2; +wire [15:0] add_ln703_795_fu_6156_p2; +wire [15:0] add_ln703_794_fu_6151_p2; +wire [15:0] sub_ln703_663_fu_5923_p2; +wire [15:0] add_ln703_788_fu_6082_p2; +wire [15:0] sub_ln703_689_fu_6096_p2; +wire [15:0] add_ln703_790_fu_6121_p2; +wire [15:0] sub_ln703_639_fu_5789_p2; +wire [15:0] sub_ln703_661_fu_5913_p2; +wire [15:0] add_ln703_817_fu_6201_p2; +wire [15:0] add_ln703_815_fu_6196_p2; +wire [15:0] sub_ln703_645_fu_5827_p2; +wire [15:0] add_ln703_820_fu_6211_p2; +wire [15:0] sub_ln703_681_fu_6238_p2; +wire [15:0] sub_ln703_683_fu_6242_p2; +wire [15:0] sub_ln703_685_fu_6246_p2; +wire [15:0] add_ln703_789_fu_6250_p2; +wire [15:0] sub_ln703_695_fu_6254_p2; +wire [15:0] add_ln703_803_fu_6319_p2; +wire [15:0] add_ln703_793_fu_6258_p2; +wire [15:0] add_ln703_797_fu_6262_p2; +wire [15:0] sub_ln703_698_fu_6267_p2; +wire [15:0] sub_ln703_699_fu_6271_p2; +wire [15:0] add_ln703_799_fu_6276_p2; +wire [15:0] add_ln703_807_fu_6369_p2; +wire [15:0] sub_ln703_701_fu_6281_p2; +wire [15:0] sub_ln703_702_fu_6285_p2; +wire [15:0] sub_ln703_703_fu_6289_p2; +wire [15:0] sub_ln703_708_fu_6302_p2; +wire [15:0] sub_ln703_709_fu_6306_p2; +wire [15:0] add_ln703_800_fu_6315_p2; +wire [15:0] add_ln703_804_fu_6323_p2; +wire [15:0] sub_ln703_713_fu_6337_p2; +wire [15:0] add_ln703_805_fu_6341_p2; +wire [15:0] sub_ln703_714_fu_6345_p2; +wire [15:0] sub_ln703_715_fu_6350_p2; +wire [15:0] add_ln703_806_fu_6359_p2; +wire [15:0] add_ln703_808_fu_6373_p2; +wire [15:0] add_ln703_809_fu_6378_p2; +wire [15:0] sub_ln703_718_fu_6382_p2; +wire [15:0] sub_ln703_719_fu_6386_p2; +wire [15:0] sub_ln703_720_fu_6391_p2; +wire [15:0] add_ln703_810_fu_6396_p2; +wire [15:0] add_ln703_811_fu_6401_p2; +wire [15:0] add_ln703_812_fu_6405_p2; +wire [15:0] add_ln703_813_fu_6409_p2; +wire [15:0] sub_ln703_721_fu_6413_p2; +wire [15:0] add_ln703_823_fu_6512_p2; +wire [15:0] add_ln703_814_fu_6417_p2; +wire [15:0] sub_ln703_722_fu_6422_p2; +wire [15:0] sub_ln703_710_fu_6311_p2; +wire [15:0] sub_ln703_712_fu_6332_p2; +wire [15:0] sub_ln703_725_fu_6437_p2; +wire [15:0] add_ln703_830_fu_6550_p2; +wire [15:0] add_ln703_829_fu_6546_p2; +wire [15:0] sub_ln703_726_fu_6442_p2; +wire [15:0] add_ln703_832_fu_6569_p2; +wire [15:0] sub_ln703_729_fu_6462_p2; +wire [15:0] sub_ln703_730_fu_6467_p2; +wire [15:0] sub_ln703_731_fu_6472_p2; +wire [15:0] sub_ln703_732_fu_6477_p2; +wire [15:0] add_ln703_822_fu_6482_p2; +wire [15:0] sub_ln703_734_fu_6492_p2; +wire [15:0] sub_ln703_735_fu_6497_p2; +wire [15:0] sub_ln703_737_fu_6507_p2; +wire [15:0] add_ln703_824_fu_6516_p2; +wire [15:0] sub_ln703_723_fu_6427_p2; +wire [15:0] add_ln703_828_fu_6536_p2; +wire [15:0] sub_ln703_739_fu_6541_p2; +wire [15:0] sub_ln703_740_fu_6560_p2; +wire [15:0] sub_ln703_744_fu_6565_p2; +wire [15:0] sub_ln703_747_fu_6584_p2; +wire [15:0] sub_ln703_748_fu_6589_p2; +wire [15:0] sub_ln703_751_fu_6604_p2; +wire [15:0] sub_ln703_752_fu_6609_p2; +wire [15:0] sub_ln703_705_fu_6294_p2; +wire [15:0] add_ln703_843_fu_6674_p2; +wire [15:0] add_ln703_842_fu_6669_p2; +wire [15:0] sub_ln703_753_fu_6614_p2; +wire [15:0] sub_ln703_754_fu_6619_p2; +wire [15:0] add_ln703_850_fu_6698_p2; +wire [15:0] add_ln703_848_fu_6694_p2; +wire [15:0] add_ln703_837_fu_6624_p2; +wire [15:0] sub_ln703_711_fu_6328_p2; +wire [15:0] add_ln703_853_fu_6718_p2; +wire [15:0] add_ln703_852_fu_6713_p2; +wire [15:0] sub_ln703_716_fu_6354_p2; +wire [15:0] add_ln703_857_fu_6728_p2; +wire [15:0] add_ln703_844_fu_6678_p2; +wire [15:0] sub_ln703_706_fu_6298_p2; +wire [15:0] add_ln703_863_fu_6744_p2; +wire [15:0] add_ln703_854_fu_6722_p2; +wire [15:0] add_ln703_864_fu_6749_p2; +wire [15:0] sub_ln703_717_fu_6364_p2; +wire [15:0] sub_ln703_738_fu_6521_p2; +wire [15:0] sub_ln703_741_fu_6795_p2; +wire [15:0] sub_ln703_743_fu_6803_p2; +wire [15:0] sub_ln703_750_fu_6811_p2; +wire [15:0] add_ln703_835_fu_6815_p2; +wire [15:0] sub_ln703_755_fu_6819_p2; +wire [15:0] sub_ln703_756_fu_6823_p2; +wire [15:0] sub_ln703_758_fu_6827_p2; +wire [15:0] sub_ln703_760_fu_6831_p2; +wire [15:0] sub_ln703_742_fu_6799_p2; +wire [15:0] add_ln703_839_fu_6836_p2; +wire [15:0] sub_ln703_745_fu_6807_p2; +wire [15:0] sub_ln703_762_fu_6841_p2; +wire [15:0] sub_ln703_764_fu_6845_p2; +wire [15:0] sub_ln703_765_fu_6849_p2; +wire [15:0] sub_ln703_766_fu_6853_p2; +wire [15:0] add_ln703_846_fu_6863_p2; +wire [15:0] add_ln703_847_fu_6868_p2; +wire [15:0] add_ln703_866_fu_6972_p2; +wire [15:0] sub_ln703_772_fu_6877_p2; +wire [15:0] add_ln703_855_fu_6882_p2; +wire [15:0] add_ln703_856_fu_6891_p2; +wire [15:0] add_ln703_859_fu_6901_p2; +wire [15:0] add_ln703_860_fu_6905_p2; +wire [15:0] sub_ln703_775_fu_6910_p2; +wire [15:0] add_ln703_861_fu_6919_p2; +wire [15:0] add_ln703_862_fu_6923_p2; +wire [15:0] sub_ln703_777_fu_6928_p2; +wire [15:0] sub_ln703_778_fu_6933_p2; +wire [15:0] sub_ln703_779_fu_6938_p2; +wire [15:0] sub_ln703_782_fu_6946_p2; +wire [15:0] sub_ln703_783_fu_6950_p2; +wire [15:0] sub_ln703_784_fu_6954_p2; +wire [15:0] sub_ln703_785_fu_6959_p2; +wire [15:0] sub_ln703_786_fu_6964_p2; +wire [15:0] add_ln703_865_fu_6968_p2; +wire [15:0] add_ln703_869_fu_6976_p2; +wire [15:0] sub_ln703_790_fu_6991_p2; +wire [15:0] sub_ln703_791_fu_6996_p2; +wire [15:0] sub_ln703_792_fu_7000_p2; +wire [15:0] sub_ln703_793_fu_7005_p2; +wire [15:0] sub_ln703_794_fu_7010_p2; +wire [15:0] add_ln703_878_fu_7104_p2; +wire [15:0] add_ln703_881_fu_7117_p2; +wire [15:0] add_ln703_880_fu_7113_p2; +wire [15:0] sub_ln703_795_fu_7015_p2; +wire [15:0] sub_ln703_796_fu_7020_p2; +wire [15:0] add_ln703_870_fu_7025_p2; +wire [15:0] sub_ln703_798_fu_7035_p2; +wire [15:0] sub_ln703_768_fu_6858_p2; +wire [15:0] add_ln703_887_fu_7151_p2; +wire [15:0] add_ln703_871_fu_7040_p2; +wire [15:0] sub_ln703_800_fu_7045_p2; +wire [15:0] sub_ln703_803_fu_7070_p2; +wire [15:0] sub_ln703_804_fu_7075_p2; +wire [15:0] sub_ln703_788_fu_6981_p2; +wire [15:0] sub_ln703_773_fu_6886_p2; +wire [15:0] sub_ln703_774_fu_6896_p2; +wire [15:0] sub_ln703_806_fu_7089_p2; +wire [15:0] add_ln703_879_fu_7108_p2; +wire [15:0] add_ln703_883_fu_7127_p2; +wire [15:0] add_ln703_885_fu_7142_p2; +wire [15:0] add_ln703_886_fu_7147_p2; +wire [15:0] add_ln703_889_fu_7161_p2; +wire [15:0] sub_ln703_809_fu_7165_p2; +wire [15:0] sub_ln703_810_fu_7170_p2; +wire [15:0] sub_ln703_789_fu_6986_p2; +wire [15:0] add_ln703_904_fu_7240_p2; +wire [15:0] sub_ln703_780_fu_6942_p2; +wire [15:0] add_ln703_909_fu_7255_p2; +wire [15:0] add_ln703_908_fu_7250_p2; +wire [15:0] add_ln703_916_fu_7269_p2; +wire [15:0] add_ln703_915_fu_7265_p2; +wire [15:0] add_ln703_921_fu_7283_p2; +wire [15:0] add_ln703_919_fu_7279_p2; +wire [15:0] sub_ln703_771_fu_6873_p2; +wire [15:0] add_ln703_924_fu_7298_p2; +wire [15:0] add_ln703_923_fu_7293_p2; +wire [15:0] sub_ln703_776_fu_6915_p2; +wire [15:0] add_ln703_931_fu_7308_p2; +wire [15:0] add_ln703_910_fu_7259_p2; +wire [15:0] add_ln703_925_fu_7302_p2; +wire [15:0] add_ln703_932_fu_7313_p2; +wire [15:0] sub_ln703_811_fu_7346_p2; +wire [15:0] sub_ln703_812_fu_7350_p2; +wire [15:0] add_ln703_890_fu_7354_p2; +wire [15:0] add_ln703_891_fu_7358_p2; +wire [15:0] add_ln703_897_fu_7362_p2; +wire [15:0] add_ln703_899_fu_7366_p2; +wire [15:0] sub_ln703_813_fu_7370_p2; +wire [15:0] sub_ln703_815_fu_7374_p2; +wire [15:0] add_ln703_900_fu_7378_p2; +wire [15:0] add_ln703_901_fu_7390_p2; +wire [15:0] add_ln703_902_fu_7394_p2; +wire [15:0] sub_ln703_822_fu_7398_p2; +wire [15:0] add_ln703_903_fu_7402_p2; +wire [15:0] sub_ln703_826_fu_7407_p2; +wire [15:0] sub_ln703_827_fu_7412_p2; +wire [15:0] sub_ln703_828_fu_7417_p2; +wire [15:0] sub_ln703_829_fu_7422_p2; +wire [15:0] sub_ln703_831_fu_7430_p2; +wire [15:0] sub_ln703_832_fu_7434_p2; +wire [15:0] add_ln703_927_fu_7537_p2; +wire [15:0] sub_ln703_833_fu_7439_p2; +wire [15:0] sub_ln703_834_fu_7444_p2; +wire [15:0] sub_ln703_836_fu_7453_p2; +wire [15:0] sub_ln703_837_fu_7458_p2; +wire [15:0] sub_ln703_839_fu_7467_p2; +wire [15:0] add_ln703_907_fu_7477_p2; +wire [15:0] add_ln703_911_fu_7481_p2; +wire [15:0] sub_ln703_841_fu_7485_p2; +wire [15:0] add_ln703_912_fu_7490_p2; +wire [15:0] add_ln703_913_fu_7494_p2; +wire [15:0] sub_ln703_842_fu_7498_p2; +wire [15:0] sub_ln703_843_fu_7503_p2; +wire [15:0] sub_ln703_844_fu_7508_p2; +wire [15:0] add_ln703_918_fu_7513_p2; +wire [15:0] sub_ln703_845_fu_7518_p2; +wire [15:0] sub_ln703_846_fu_7523_p2; +wire [15:0] sub_ln703_847_fu_7528_p2; +wire [15:0] add_ln703_926_fu_7532_p2; +wire [15:0] add_ln703_928_fu_7541_p2; +wire [15:0] add_ln703_929_fu_7546_p2; +wire [15:0] sub_ln703_848_fu_7551_p2; +wire [15:0] add_ln703_937_fu_7659_p2; +wire [15:0] sub_ln703_835_fu_7449_p2; +wire [15:0] sub_ln703_849_fu_7556_p2; +wire [15:0] add_ln703_930_fu_7561_p2; +wire [15:0] sub_ln703_838_fu_7463_p2; +wire [15:0] sub_ln703_850_fu_7566_p2; +wire [15:0] sub_ln703_840_fu_7472_p2; +wire [15:0] sub_ln703_851_fu_7571_p2; +wire [15:0] sub_ln703_853_fu_7576_p2; +wire [15:0] add_ln703_933_fu_7581_p2; +wire [15:0] add_ln703_942_fu_7715_p2; +wire [15:0] sub_ln703_855_fu_7591_p2; +wire [15:0] sub_ln703_856_fu_7596_p2; +wire [15:0] sub_ln703_860_fu_7620_p2; +wire [15:0] sub_ln703_830_fu_7426_p2; +wire [15:0] add_ln703_945_fu_7740_p2; +wire [15:0] sub_ln703_861_fu_7625_p2; +wire [15:0] add_ln703_935_fu_7629_p2; +wire [15:0] sub_ln703_864_fu_7644_p2; +wire [15:0] sub_ln703_817_fu_7382_p2; +wire [15:0] add_ln703_950_fu_7770_p2; +wire [15:0] add_ln703_949_fu_7765_p2; +wire [15:0] add_ln703_940_fu_7690_p2; +wire [15:0] sub_ln703_871_fu_7696_p2; +wire [15:0] add_ln703_941_fu_7701_p2; +wire [15:0] sub_ln703_872_fu_7705_p2; +wire [15:0] sub_ln703_854_fu_7586_p2; +wire [15:0] sub_ln703_874_fu_7725_p2; +wire [15:0] add_ln703_947_fu_7745_p2; +wire [15:0] add_ln703_957_fu_7823_p2; +wire [15:0] add_ln703_956_fu_7819_p2; +wire [15:0] add_ln703_951_fu_7774_p2; +wire [15:0] add_ln703_952_fu_7800_p2; +wire [15:0] add_ln703_955_fu_7815_p2; +wire [15:0] sub_ln703_819_fu_7386_p2; +wire [15:0] add_ln703_1000_fu_7852_p2; +wire [15:0] add_ln703_1002_fu_7863_p2; +wire [15:0] add_ln703_1003_fu_7867_p2; +wire [15:0] add_ln703_1001_fu_7857_p2; +wire [15:0] sub_ln703_876_fu_7878_p2; +wire [15:0] add_ln703_944_fu_7882_p2; +wire [15:0] sub_ln703_877_fu_7886_p2; +wire [15:0] sub_ln703_878_fu_7890_p2; +wire [15:0] sub_ln703_883_fu_7898_p2; +wire [15:0] sub_ln703_885_fu_7906_p2; +wire [15:0] sub_ln703_888_fu_7918_p2; +wire [15:0] sub_ln703_889_fu_7922_p2; +wire [15:0] sub_ln703_890_fu_7926_p2; +wire [15:0] sub_ln703_891_fu_7930_p2; +wire [15:0] sub_ln703_896_fu_7934_p2; +wire [15:0] add_ln703_953_fu_7956_p2; +wire [15:0] sub_ln703_902_fu_7961_p2; +wire [15:0] sub_ln703_903_fu_7966_p2; +wire [15:0] sub_ln703_905_fu_7970_p2; +wire [15:0] sub_ln703_906_fu_7974_p2; +wire [15:0] sub_ln703_908_fu_7983_p2; +wire [15:0] sub_ln703_886_fu_7910_p2; +wire [15:0] add_ln703_959_fu_7997_p2; +wire [15:0] sub_ln703_913_fu_8007_p2; +wire [15:0] add_ln703_960_fu_8012_p2; +wire [15:0] add_ln703_961_fu_8016_p2; +wire [15:0] sub_ln703_914_fu_8020_p2; +wire [15:0] sub_ln703_915_fu_8024_p2; +wire [15:0] sub_ln703_897_fu_7938_p2; +wire [15:0] sub_ln703_918_fu_8033_p2; +wire [15:0] sub_ln703_921_fu_8047_p2; +wire [15:0] add_ln703_970_fu_8125_p2; +wire [15:0] add_ln703_962_fu_8052_p2; +wire [15:0] sub_ln703_923_fu_8057_p2; +wire [15:0] sub_ln703_882_fu_7894_p2; +wire [15:0] add_ln703_972_fu_8148_p2; +wire [15:0] sub_ln703_907_fu_7978_p2; +wire [15:0] add_ln703_963_fu_8062_p2; +wire [15:0] sub_ln703_884_fu_7902_p2; +wire [15:0] add_ln703_975_fu_8170_p2; +wire [15:0] add_ln703_965_fu_8067_p2; +wire [15:0] sub_ln703_887_fu_7914_p2; +wire [15:0] add_ln703_977_fu_8186_p2; +wire [15:0] sub_ln703_910_fu_7992_p2; +wire [15:0] sub_ln703_912_fu_8002_p2; +wire [15:0] sub_ln703_928_fu_8090_p2; +wire [15:0] sub_ln703_929_fu_8095_p2; +wire [15:0] add_ln703_966_fu_8100_p2; +wire [15:0] add_ln703_967_fu_8105_p2; +wire [15:0] add_ln703_968_fu_8110_p2; +wire [15:0] add_ln703_969_fu_8115_p2; +wire [15:0] sub_ln703_899_fu_7942_p2; +wire [15:0] add_ln703_982_fu_8239_p2; +wire [15:0] sub_ln703_900_fu_7946_p2; +wire [15:0] add_ln703_984_fu_8250_p2; +wire [15:0] sub_ln703_901_fu_7951_p2; +wire [15:0] add_ln703_987_fu_8260_p2; +wire [15:0] sub_ln703_919_fu_8037_p2; +wire [15:0] sub_ln703_920_fu_8042_p2; +wire [15:0] sub_ln703_930_fu_8120_p2; +wire [15:0] add_ln703_971_fu_8129_p2; +wire [15:0] sub_ln703_931_fu_8134_p2; +wire [15:0] sub_ln703_932_fu_8139_p2; +wire [15:0] sub_ln703_933_fu_8143_p2; +wire [15:0] add_ln703_973_fu_8153_p2; +wire [15:0] add_ln703_974_fu_8159_p2; +wire [15:0] sub_ln703_934_fu_8165_p2; +wire [15:0] add_ln703_976_fu_8175_p2; +wire [15:0] sub_ln703_909_fu_7987_p2; +wire [15:0] add_ln703_994_fu_8325_p2; +wire [15:0] sub_ln703_935_fu_8181_p2; +wire [15:0] add_ln703_978_fu_8191_p2; +wire [15:0] add_ln703_979_fu_8197_p2; +wire [15:0] sub_ln703_924_fu_8072_p2; +wire [15:0] sub_ln703_925_fu_8076_p2; +wire [15:0] sub_ln703_926_fu_8080_p2; +wire [15:0] add_ln703_980_fu_8203_p2; +wire [15:0] sub_ln703_927_fu_8085_p2; +wire [15:0] sub_ln703_936_fu_8209_p2; +wire [15:0] add_ln703_981_fu_8214_p2; +wire [15:0] sub_ln703_937_fu_8219_p2; +wire [15:0] sub_ln703_938_fu_8224_p2; +wire [15:0] sub_ln703_916_fu_8028_p2; +wire [15:0] add_ln703_1007_fu_8395_p2; +wire [15:0] sub_ln703_939_fu_8229_p2; +wire [15:0] add_ln703_1009_fu_8410_p2; +wire [15:0] sub_ln703_940_fu_8234_p2; +wire [15:0] add_ln703_983_fu_8244_p2; +wire [15:0] add_ln703_986_fu_8255_p2; +wire [15:0] acc_1_V_fu_8265_p2; +wire [15:0] acc_2_V_fu_8270_p2; +wire [15:0] acc_3_V_fu_8275_p2; +wire [15:0] acc_4_V_fu_8280_p2; +wire [15:0] acc_5_V_fu_8285_p2; +wire [15:0] acc_6_V_fu_8290_p2; +wire [15:0] acc_7_V_fu_8295_p2; +wire [15:0] acc_8_V_fu_8300_p2; +wire [15:0] acc_9_V_fu_8305_p2; +wire [15:0] acc_10_V_fu_8310_p2; +wire [15:0] acc_11_V_fu_8315_p2; +wire [15:0] acc_12_V_fu_8320_p2; +wire [15:0] acc_13_V_fu_8330_p2; +wire [15:0] acc_14_V_fu_8335_p2; +wire [15:0] acc_15_V_fu_8340_p2; +wire [15:0] acc_16_V_fu_8345_p2; +wire [15:0] acc_17_V_fu_8350_p2; +wire [15:0] acc_18_V_fu_8355_p2; +wire [15:0] acc_19_V_fu_8360_p2; +wire [15:0] acc_20_V_fu_8365_p2; +wire [15:0] acc_22_V_fu_8370_p2; +wire [15:0] acc_23_V_fu_8375_p2; +wire [15:0] acc_24_V_fu_8380_p2; +wire [15:0] acc_25_V_fu_8385_p2; +wire [15:0] acc_26_V_fu_8390_p2; +wire [15:0] acc_27_V_fu_8400_p2; +wire [15:0] acc_28_V_fu_8405_p2; +wire [15:0] acc_29_V_fu_8414_p2; +wire [15:0] acc_30_V_fu_8419_p2; +wire [15:0] acc_31_V_fu_8424_p2; +reg ap_ce_reg; +reg [15:0] data_0_V_read_int_reg; +reg [15:0] data_1_V_read_int_reg; +reg [15:0] data_2_V_read_int_reg; +reg [15:0] data_3_V_read_int_reg; +reg [15:0] data_4_V_read_int_reg; +reg [15:0] data_5_V_read_int_reg; +reg [15:0] data_6_V_read_int_reg; +reg [15:0] data_7_V_read_int_reg; +reg [15:0] data_8_V_read_int_reg; +reg [15:0] data_9_V_read_int_reg; +reg [15:0] data_10_V_read_int_reg; +reg [15:0] data_11_V_read_int_reg; +reg [15:0] data_12_V_read_int_reg; +reg [15:0] data_13_V_read_int_reg; +reg [15:0] data_14_V_read_int_reg; +reg [15:0] data_15_V_read_int_reg; +reg [15:0] data_16_V_read_int_reg; +reg [15:0] data_17_V_read_int_reg; +reg [15:0] data_18_V_read_int_reg; +reg [15:0] data_19_V_read_int_reg; +reg [15:0] data_20_V_read_int_reg; +reg [15:0] data_21_V_read_int_reg; +reg [15:0] data_22_V_read_int_reg; +reg [15:0] data_23_V_read_int_reg; +reg [15:0] data_24_V_read_int_reg; +reg [15:0] data_25_V_read_int_reg; +reg [15:0] data_26_V_read_int_reg; +reg [15:0] data_27_V_read_int_reg; +reg [15:0] data_28_V_read_int_reg; +reg [15:0] data_29_V_read_int_reg; +reg [15:0] data_30_V_read_int_reg; +reg [15:0] data_31_V_read_int_reg; +reg [15:0] data_32_V_read_int_reg; +reg [15:0] data_33_V_read_int_reg; +reg [15:0] data_34_V_read_int_reg; +reg [15:0] data_35_V_read_int_reg; +reg [15:0] data_36_V_read_int_reg; +reg [15:0] data_37_V_read_int_reg; +reg [15:0] data_38_V_read_int_reg; +reg [15:0] data_39_V_read_int_reg; +reg [15:0] data_40_V_read_int_reg; +reg [15:0] data_41_V_read_int_reg; +reg [15:0] data_42_V_read_int_reg; +reg [15:0] data_43_V_read_int_reg; +reg [15:0] data_44_V_read_int_reg; +reg [15:0] data_45_V_read_int_reg; +reg [15:0] data_46_V_read_int_reg; +reg [15:0] data_47_V_read_int_reg; +reg [15:0] data_48_V_read_int_reg; +reg [15:0] data_49_V_read_int_reg; +reg [15:0] data_50_V_read_int_reg; +reg [15:0] data_51_V_read_int_reg; +reg [15:0] data_52_V_read_int_reg; +reg [15:0] data_53_V_read_int_reg; +reg [15:0] data_54_V_read_int_reg; +reg [15:0] data_55_V_read_int_reg; +reg [15:0] data_56_V_read_int_reg; +reg [15:0] data_57_V_read_int_reg; +reg [15:0] data_58_V_read_int_reg; +reg [15:0] data_59_V_read_int_reg; +reg [15:0] data_60_V_read_int_reg; +reg [15:0] data_61_V_read_int_reg; +reg [15:0] data_62_V_read_int_reg; +reg [15:0] data_63_V_read_int_reg; +reg [15:0] ap_return_0_int_reg; +reg [15:0] ap_return_1_int_reg; +reg [15:0] ap_return_2_int_reg; +reg [15:0] ap_return_3_int_reg; +reg [15:0] ap_return_4_int_reg; +reg [15:0] ap_return_5_int_reg; +reg [15:0] ap_return_6_int_reg; +reg [15:0] ap_return_7_int_reg; +reg [15:0] ap_return_8_int_reg; +reg [15:0] ap_return_9_int_reg; +reg [15:0] ap_return_10_int_reg; +reg [15:0] ap_return_11_int_reg; +reg [15:0] ap_return_12_int_reg; +reg [15:0] ap_return_13_int_reg; +reg [15:0] ap_return_14_int_reg; +reg [15:0] ap_return_15_int_reg; +reg [15:0] ap_return_16_int_reg; +reg [15:0] ap_return_17_int_reg; +reg [15:0] ap_return_18_int_reg; +reg [15:0] ap_return_19_int_reg; +reg [15:0] ap_return_20_int_reg; +reg [15:0] ap_return_21_int_reg; +reg [15:0] ap_return_22_int_reg; +reg [15:0] ap_return_23_int_reg; +reg [15:0] ap_return_24_int_reg; +reg [15:0] ap_return_25_int_reg; +reg [15:0] ap_return_26_int_reg; +reg [15:0] ap_return_27_int_reg; +reg [15:0] ap_return_28_int_reg; +reg [15:0] ap_return_29_int_reg; +reg [15:0] ap_return_30_int_reg; +reg [15:0] ap_return_31_int_reg; + +always @ (posedge ap_clk) begin + ap_ce_reg <= ap_ce; +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + acc_21_V_reg_12991 <= acc_21_V_fu_7872_p2; + add_ln703_130_reg_10373 <= add_ln703_130_fu_556_p2; + add_ln703_131_reg_10354 <= add_ln703_131_fu_544_p2; + add_ln703_131_reg_10354_pp0_iter2_reg <= add_ln703_131_reg_10354; + add_ln703_132_reg_10414 <= add_ln703_132_fu_599_p2; + add_ln703_134_reg_10385 <= add_ln703_134_fu_568_p2; + add_ln703_135_reg_10425 <= add_ln703_135_fu_619_p2; + add_ln703_140_reg_10442 <= add_ln703_140_fu_644_p2; + add_ln703_141_reg_10447 <= add_ln703_141_fu_649_p2; + add_ln703_144_reg_10403 <= add_ln703_144_fu_589_p2; + add_ln703_144_reg_10403_pp0_iter3_reg <= add_ln703_144_reg_10403; + add_ln703_153_reg_10503 <= add_ln703_153_fu_809_p2; + add_ln703_157_reg_10529 <= add_ln703_157_fu_892_p2; + add_ln703_158_reg_10482 <= add_ln703_158_fu_676_p2; + add_ln703_161_reg_10487 <= add_ln703_161_fu_681_p2; + add_ln703_162_reg_10539 <= add_ln703_162_fu_917_p2; + add_ln703_170_reg_10566 <= add_ln703_170_fu_972_p2; + add_ln703_171_reg_10571 <= add_ln703_171_fu_977_p2; + add_ln703_173_reg_10576 <= add_ln703_173_fu_982_p2; + add_ln703_177_reg_10591 <= add_ln703_177_fu_997_p2; + add_ln703_179_reg_10495 <= add_ln703_179_fu_685_p2; + add_ln703_181_reg_10601 <= add_ln703_181_fu_1015_p2; + add_ln703_183_reg_10606 <= add_ln703_183_fu_1021_p2; + add_ln703_186_reg_10621 <= add_ln703_186_fu_1036_p2; + add_ln703_192_reg_10626 <= add_ln703_192_fu_1050_p2; + add_ln703_204_reg_10641 <= add_ln703_204_fu_1059_p2; + add_ln703_207_reg_10682 <= add_ln703_207_fu_1299_p2; + add_ln703_208_reg_10687 <= add_ln703_208_fu_1309_p2; + add_ln703_209_reg_10646 <= add_ln703_209_fu_1064_p2; + add_ln703_210_reg_10692 <= add_ln703_210_fu_1314_p2; + add_ln703_213_reg_10653 <= add_ln703_213_fu_1068_p2; + add_ln703_216_reg_10702 <= add_ln703_216_fu_1358_p2; + add_ln703_223_reg_10658 <= add_ln703_223_fu_1073_p2; + add_ln703_224_reg_10732 <= add_ln703_224_fu_1437_p2; + add_ln703_226_reg_10737 <= add_ln703_226_fu_1457_p2; + add_ln703_227_reg_10752 <= add_ln703_227_fu_1472_p2; + add_ln703_233_reg_10767 <= add_ln703_233_fu_1501_p2; + add_ln703_236_reg_10772 <= add_ln703_236_fu_1511_p2; + add_ln703_238_reg_10777 <= add_ln703_238_fu_1520_p2; + add_ln703_247_reg_10802 <= add_ln703_247_fu_1563_p2; + add_ln703_250_reg_10807 <= add_ln703_250_fu_1574_p2; + add_ln703_252_reg_10665 <= add_ln703_252_fu_1077_p2; + add_ln703_252_reg_10665_pp0_iter5_reg <= add_ln703_252_reg_10665; + add_ln703_254_reg_10672 <= add_ln703_254_fu_1081_p2; + add_ln703_260_reg_10817 <= add_ln703_260_fu_1593_p2; + add_ln703_262_reg_10827 <= add_ln703_262_fu_1604_p2; + add_ln703_265_reg_10837 <= add_ln703_265_fu_1614_p2; + add_ln703_280_reg_10846 <= add_ln703_280_fu_1618_p2; + add_ln703_283_reg_10873 <= add_ln703_283_fu_1979_p2; + add_ln703_285_reg_10888 <= add_ln703_285_fu_2009_p2; + add_ln703_289_reg_10898 <= add_ln703_289_fu_2034_p2; + add_ln703_290_reg_10903 <= add_ln703_290_fu_2039_p2; + add_ln703_294_reg_10918 <= add_ln703_294_fu_2084_p2; + add_ln703_295_reg_10923 <= add_ln703_295_fu_2089_p2; + add_ln703_300_reg_10930 <= add_ln703_300_fu_2093_p2; + add_ln703_303_reg_10940 <= add_ln703_303_fu_2104_p2; + add_ln703_304_reg_10945 <= add_ln703_304_fu_2110_p2; + add_ln703_307_reg_10960 <= add_ln703_307_fu_2125_p2; + add_ln703_309_reg_10970 <= add_ln703_309_fu_2136_p2; + add_ln703_310_reg_10980 <= add_ln703_310_fu_2147_p2; + add_ln703_323_reg_11005 <= add_ln703_323_fu_2188_p2; + add_ln703_326_reg_10855 <= add_ln703_326_fu_1622_p2; + add_ln703_326_reg_10855_pp0_iter6_reg <= add_ln703_326_reg_10855; + add_ln703_328_reg_11015 <= add_ln703_328_fu_2208_p2; + add_ln703_333_reg_11025 <= add_ln703_333_fu_2224_p2; + add_ln703_341_reg_11030 <= add_ln703_341_fu_2230_p2; + add_ln703_342_reg_11071 <= add_ln703_342_fu_2520_p2; + add_ln703_346_reg_11106 <= add_ln703_346_fu_2589_p2; + add_ln703_350_reg_11111 <= add_ln703_350_fu_2602_p2; + add_ln703_352_reg_11126 <= add_ln703_352_fu_2633_p2; + add_ln703_354_reg_11131 <= add_ln703_354_fu_2638_p2; + add_ln703_356_reg_11148 <= add_ln703_356_fu_2657_p2; + add_ln703_360_reg_11158 <= add_ln703_360_fu_2677_p2; + add_ln703_369_reg_11037 <= add_ln703_369_fu_2234_p2; + add_ln703_369_reg_11037_pp0_iter7_reg <= add_ln703_369_reg_11037; + add_ln703_371_reg_11193 <= add_ln703_371_fu_2732_p2; + add_ln703_375_reg_11198 <= add_ln703_375_fu_2738_p2; + add_ln703_384_reg_11203 <= add_ln703_384_fu_2743_p2; + add_ln703_386_reg_11262 <= add_ln703_386_fu_3015_p2; + add_ln703_390_reg_11272 <= add_ln703_390_fu_3050_p2; + add_ln703_400_reg_11210 <= add_ln703_400_fu_2752_p2; + add_ln703_402_reg_11215 <= add_ln703_402_fu_2758_p2; + add_ln703_402_reg_11215_pp0_iter8_reg <= add_ln703_402_reg_11215; + add_ln703_410_reg_11287 <= add_ln703_410_fu_3149_p2; + add_ln703_416_reg_11297 <= add_ln703_416_fu_3170_p2; + add_ln703_417_reg_11312 <= add_ln703_417_fu_3185_p2; + add_ln703_424_reg_11225 <= add_ln703_424_fu_2762_p2; + add_ln703_426_reg_11347 <= add_ln703_426_fu_3258_p2; + add_ln703_431_reg_11357 <= add_ln703_431_fu_3274_p2; + add_ln703_435_reg_11362 <= add_ln703_435_fu_3284_p2; + add_ln703_438_reg_11382 <= add_ln703_438_fu_3310_p2; + add_ln703_439_reg_11233 <= add_ln703_439_fu_2766_p2; + add_ln703_439_reg_11233_pp0_iter8_reg <= add_ln703_439_reg_11233; + add_ln703_445_reg_11387 <= add_ln703_445_fu_3315_p2; + add_ln703_447_reg_11392 <= add_ln703_447_fu_3320_p2; + add_ln703_451_reg_11402 <= add_ln703_451_fu_3329_p2; + add_ln703_466_reg_11410 <= add_ln703_466_fu_3333_p2; + add_ln703_469_reg_11479 <= add_ln703_469_fu_3655_p2; + add_ln703_471_reg_11418 <= add_ln703_471_fu_3337_p2; + add_ln703_476_reg_11494 <= add_ln703_476_fu_3685_p2; + add_ln703_478_reg_11519 <= add_ln703_478_fu_3730_p2; + add_ln703_484_reg_11423 <= add_ln703_484_fu_3342_p2; + add_ln703_490_reg_11428 <= add_ln703_490_fu_3347_p2; + add_ln703_496_reg_11544 <= add_ln703_496_fu_3806_p2; + add_ln703_497_reg_11549 <= add_ln703_497_fu_3811_p2; + add_ln703_498_reg_11436 <= add_ln703_498_fu_3351_p2; + add_ln703_506_reg_11559 <= add_ln703_506_fu_3839_p2; + add_ln703_507_reg_11441 <= add_ln703_507_fu_3356_p2; + add_ln703_507_reg_11441_pp0_iter9_reg <= add_ln703_507_reg_11441; + add_ln703_512_reg_11589 <= add_ln703_512_fu_3878_p2; + add_ln703_515_reg_11599 <= add_ln703_515_fu_3889_p2; + add_ln703_517_reg_11604 <= add_ln703_517_fu_3894_p2; + add_ln703_525_reg_11243 <= add_ln703_525_fu_2774_p2; + add_ln703_525_reg_11243_pp0_iter8_reg <= add_ln703_525_reg_11243; + add_ln703_525_reg_11243_pp0_iter9_reg <= add_ln703_525_reg_11243_pp0_iter8_reg; + add_ln703_528_reg_11452 <= add_ln703_528_fu_3360_p2; + add_ln703_528_reg_11452_pp0_iter9_reg <= add_ln703_528_reg_11452; + add_ln703_534_reg_11248 <= add_ln703_534_fu_2779_p2; + add_ln703_534_reg_11248_pp0_iter8_reg <= add_ln703_534_reg_11248; + add_ln703_534_reg_11248_pp0_iter9_reg <= add_ln703_534_reg_11248_pp0_iter8_reg; + add_ln703_535_reg_11457 <= add_ln703_535_fu_3364_p2; + add_ln703_537_reg_11609 <= add_ln703_537_fu_3912_p2; + add_ln703_545_reg_11614 <= add_ln703_545_fu_3923_p2; + add_ln703_556_reg_11619 <= add_ln703_556_fu_3933_p2; + add_ln703_560_reg_11629 <= add_ln703_560_fu_3943_p2; + add_ln703_566_reg_11635 <= add_ln703_566_fu_3952_p2; + add_ln703_568_reg_11464 <= add_ln703_568_fu_3368_p2; + add_ln703_568_reg_11464_pp0_iter9_reg <= add_ln703_568_reg_11464; + add_ln703_569_reg_11640 <= add_ln703_569_fu_3957_p2; + add_ln703_572_reg_11698 <= add_ln703_572_fu_4308_p2; + add_ln703_573_reg_11708 <= add_ln703_573_fu_4323_p2; + add_ln703_581_reg_11723 <= add_ln703_581_fu_4358_p2; + add_ln703_583_reg_11728 <= add_ln703_583_fu_4363_p2; + add_ln703_586_reg_11743 <= add_ln703_586_fu_4398_p2; + add_ln703_588_reg_11646 <= add_ln703_588_fu_3961_p2; + add_ln703_590_reg_11748 <= add_ln703_590_fu_4412_p2; + add_ln703_591_reg_11758 <= add_ln703_591_fu_4423_p2; + add_ln703_592_reg_11763 <= add_ln703_592_fu_4428_p2; + add_ln703_598_reg_11768 <= add_ln703_598_fu_4441_p2; + add_ln703_599_reg_11798 <= add_ln703_599_fu_4477_p2; + add_ln703_600_reg_11652 <= add_ln703_600_fu_3965_p2; + add_ln703_600_reg_11652_pp0_iter10_reg <= add_ln703_600_reg_11652; + add_ln703_609_reg_11803 <= add_ln703_609_fu_4501_p2; + add_ln703_616_reg_11808 <= add_ln703_616_fu_4511_p2; + add_ln703_621_reg_11662 <= add_ln703_621_fu_3969_p2; + add_ln703_621_reg_11662_pp0_iter10_reg <= add_ln703_621_reg_11662; + add_ln703_633_reg_11823 <= add_ln703_633_fu_4531_p2; + add_ln703_634_reg_11828 <= add_ln703_634_fu_4535_p2; + add_ln703_639_reg_11833 <= add_ln703_639_fu_4541_p2; + add_ln703_646_reg_11838 <= add_ln703_646_fu_4546_p2; + add_ln703_647_reg_11874 <= add_ln703_647_fu_4870_p2; + add_ln703_648_reg_11889 <= add_ln703_648_fu_4899_p2; + add_ln703_650_reg_11844 <= add_ln703_650_fu_4550_p2; + add_ln703_650_reg_11844_pp0_iter11_reg <= add_ln703_650_reg_11844; + add_ln703_651_reg_11929 <= add_ln703_651_fu_4959_p2; + add_ln703_660_reg_11939 <= add_ln703_660_fu_4994_p2; + add_ln703_661_reg_11944 <= add_ln703_661_fu_4999_p2; + add_ln703_666_reg_11954 <= add_ln703_666_fu_5013_p2; + add_ln703_667_reg_11853 <= add_ln703_667_fu_4554_p2; + add_ln703_668_reg_11959 <= add_ln703_668_fu_5019_p2; + add_ln703_676_reg_11979 <= add_ln703_676_fu_5052_p2; + add_ln703_682_reg_11984 <= add_ln703_682_fu_5066_p2; + add_ln703_685_reg_11989 <= add_ln703_685_fu_5077_p2; + add_ln703_691_reg_11994 <= add_ln703_691_fu_5092_p2; + add_ln703_697_reg_12002 <= add_ln703_697_fu_5096_p2; + add_ln703_703_reg_12022 <= add_ln703_703_fu_5116_p2; + add_ln703_704_reg_12056 <= add_ln703_704_fu_5336_p2; + add_ln703_706_reg_12031 <= add_ln703_706_fu_5120_p2; + add_ln703_719_reg_12086 <= add_ln703_719_fu_5439_p2; + add_ln703_722_reg_12036 <= add_ln703_722_fu_5125_p2; + add_ln703_726_reg_12041 <= add_ln703_726_fu_5130_p2; + add_ln703_728_reg_12096 <= add_ln703_728_fu_5485_p2; + add_ln703_733_reg_12146 <= add_ln703_733_fu_5551_p2; + add_ln703_734_reg_12151 <= add_ln703_734_fu_5556_p2; + add_ln703_735_reg_12161 <= add_ln703_735_fu_5571_p2; + add_ln703_737_reg_12047 <= add_ln703_737_fu_5134_p2; + add_ln703_755_reg_12196 <= add_ln703_755_fu_5652_p2; + add_ln703_765_reg_12219 <= add_ln703_765_fu_5671_p2; + add_ln703_770_reg_12258 <= add_ln703_770_fu_5950_p2; + add_ln703_778_reg_12227 <= add_ln703_778_fu_5675_p2; + add_ln703_779_reg_12273 <= add_ln703_779_fu_6024_p2; + add_ln703_783_reg_12236 <= add_ln703_783_fu_5679_p2; + add_ln703_791_reg_12348 <= add_ln703_791_fu_6131_p2; + add_ln703_792_reg_12363 <= add_ln703_792_fu_6146_p2; + add_ln703_796_reg_12368 <= add_ln703_796_fu_6160_p2; + add_ln703_798_reg_12373 <= add_ln703_798_fu_6166_p2; + add_ln703_801_reg_12393 <= add_ln703_801_fu_6187_p2; + add_ln703_802_reg_12398 <= add_ln703_802_fu_6192_p2; + add_ln703_816_reg_12241 <= add_ln703_816_fu_5684_p2; + add_ln703_816_reg_12241_pp0_iter13_reg <= add_ln703_816_reg_12241; + add_ln703_818_reg_12409 <= add_ln703_818_fu_6205_p2; + add_ln703_818_reg_12409_pp0_iter14_reg <= add_ln703_818_reg_12409; + add_ln703_819_reg_12455 <= add_ln703_819_fu_6447_p2; + add_ln703_821_reg_12414 <= add_ln703_821_fu_6216_p2; + add_ln703_825_reg_12480 <= add_ln703_825_fu_6526_p2; + add_ln703_826_reg_12419 <= add_ln703_826_fu_6222_p2; + add_ln703_827_reg_12485 <= add_ln703_827_fu_6531_p2; + add_ln703_831_reg_12490 <= add_ln703_831_fu_6554_p2; + add_ln703_833_reg_12495 <= add_ln703_833_fu_6573_p2; + add_ln703_834_reg_12505 <= add_ln703_834_fu_6594_p2; + add_ln703_836_reg_12428 <= add_ln703_836_fu_6226_p2; + add_ln703_838_reg_12520 <= add_ln703_838_fu_6634_p2; + add_ln703_840_reg_12535 <= add_ln703_840_fu_6649_p2; + add_ln703_841_reg_12550 <= add_ln703_841_fu_6664_p2; + add_ln703_845_reg_12560 <= add_ln703_845_fu_6689_p2; + add_ln703_849_reg_12434 <= add_ln703_849_fu_6230_p2; + add_ln703_849_reg_12434_pp0_iter14_reg <= add_ln703_849_reg_12434; + add_ln703_851_reg_12565 <= add_ln703_851_fu_6702_p2; + add_ln703_858_reg_12575 <= add_ln703_858_fu_6733_p2; + add_ln703_867_reg_12444 <= add_ln703_867_fu_6234_p2; + add_ln703_867_reg_12444_pp0_iter14_reg <= add_ln703_867_reg_12444; + add_ln703_868_reg_12585 <= add_ln703_868_fu_6755_p2; + add_ln703_872_reg_12650 <= add_ln703_872_fu_7050_p2; + add_ln703_873_reg_12655 <= add_ln703_873_fu_7055_p2; + add_ln703_874_reg_12675 <= add_ln703_874_fu_7084_p2; + add_ln703_875_reg_12680 <= add_ln703_875_fu_7094_p2; + add_ln703_876_reg_12600 <= add_ln703_876_fu_6769_p2; + add_ln703_877_reg_12605 <= add_ln703_877_fu_6774_p2; + add_ln703_882_reg_12690 <= add_ln703_882_fu_7121_p2; + add_ln703_884_reg_12695 <= add_ln703_884_fu_7132_p2; + add_ln703_888_reg_12705 <= add_ln703_888_fu_7156_p2; + add_ln703_892_reg_12710 <= add_ln703_892_fu_7175_p2; + add_ln703_893_reg_12715 <= add_ln703_893_fu_7180_p2; + add_ln703_894_reg_12616 <= add_ln703_894_fu_6778_p2; + add_ln703_894_reg_12616_pp0_iter15_reg <= add_ln703_894_reg_12616; + add_ln703_895_reg_12720 <= add_ln703_895_fu_7185_p2; + add_ln703_896_reg_12725 <= add_ln703_896_fu_7190_p2; + add_ln703_898_reg_12730 <= add_ln703_898_fu_7195_p2; + add_ln703_905_reg_12625 <= add_ln703_905_fu_6782_p2; + add_ln703_906_reg_12775 <= add_ln703_906_fu_7245_p2; + add_ln703_914_reg_12632 <= add_ln703_914_fu_6786_p2; + add_ln703_917_reg_12780 <= add_ln703_917_fu_7273_p2; + add_ln703_920_reg_12637 <= add_ln703_920_fu_6791_p2; + add_ln703_920_reg_12637_pp0_iter15_reg <= add_ln703_920_reg_12637; + add_ln703_922_reg_12785 <= add_ln703_922_fu_7287_p2; + add_ln703_934_reg_12845 <= add_ln703_934_fu_7610_p2; + add_ln703_936_reg_12855 <= add_ln703_936_fu_7634_p2; + add_ln703_938_reg_12875 <= add_ln703_938_fu_7663_p2; + add_ln703_939_reg_12890 <= add_ln703_939_fu_7679_p2; + add_ln703_943_reg_12905 <= add_ln703_943_fu_7719_p2; + add_ln703_946_reg_12805 <= add_ln703_946_fu_7334_p2; + add_ln703_948_reg_12930 <= add_ln703_948_fu_7760_p2; + add_ln703_954_reg_12812 <= add_ln703_954_fu_7338_p2; + add_ln703_958_reg_12965 <= add_ln703_958_fu_7827_p2; + add_ln703_964_reg_12985 <= add_ln703_964_fu_7848_p2; + add_ln703_985_reg_12819 <= add_ln703_985_fu_7342_p2; + add_ln703_985_reg_12819_pp0_iter16_reg <= add_ln703_985_reg_12819; + add_ln703_reg_10335 <= add_ln703_fu_530_p2; + add_ln703_reg_10335_pp0_iter1_reg <= add_ln703_reg_10335; + data_0_V_read_10_reg_10329 <= data_0_V_read_int_reg; + data_10_V_read11_reg_10105 <= data_10_V_read_int_reg; + data_10_V_read11_reg_10105_pp0_iter1_reg <= data_10_V_read11_reg_10105; + data_10_V_read11_reg_10105_pp0_iter2_reg <= data_10_V_read11_reg_10105_pp0_iter1_reg; + data_10_V_read11_reg_10105_pp0_iter3_reg <= data_10_V_read11_reg_10105_pp0_iter2_reg; + data_10_V_read11_reg_10105_pp0_iter4_reg <= data_10_V_read11_reg_10105_pp0_iter3_reg; + data_11_V_read12_reg_10075 <= data_11_V_read_int_reg; + data_11_V_read12_reg_10075_pp0_iter1_reg <= data_11_V_read12_reg_10075; + data_11_V_read12_reg_10075_pp0_iter2_reg <= data_11_V_read12_reg_10075_pp0_iter1_reg; + data_11_V_read12_reg_10075_pp0_iter3_reg <= data_11_V_read12_reg_10075_pp0_iter2_reg; + data_11_V_read12_reg_10075_pp0_iter4_reg <= data_11_V_read12_reg_10075_pp0_iter3_reg; + data_11_V_read12_reg_10075_pp0_iter5_reg <= data_11_V_read12_reg_10075_pp0_iter4_reg; + data_12_V_read13_reg_10045 <= data_12_V_read_int_reg; + data_12_V_read13_reg_10045_pp0_iter1_reg <= data_12_V_read13_reg_10045; + data_12_V_read13_reg_10045_pp0_iter2_reg <= data_12_V_read13_reg_10045_pp0_iter1_reg; + data_12_V_read13_reg_10045_pp0_iter3_reg <= data_12_V_read13_reg_10045_pp0_iter2_reg; + data_12_V_read13_reg_10045_pp0_iter4_reg <= data_12_V_read13_reg_10045_pp0_iter3_reg; + data_12_V_read13_reg_10045_pp0_iter5_reg <= data_12_V_read13_reg_10045_pp0_iter4_reg; + data_13_V_read14_reg_10015 <= data_13_V_read_int_reg; + data_13_V_read14_reg_10015_pp0_iter1_reg <= data_13_V_read14_reg_10015; + data_13_V_read14_reg_10015_pp0_iter2_reg <= data_13_V_read14_reg_10015_pp0_iter1_reg; + data_13_V_read14_reg_10015_pp0_iter3_reg <= data_13_V_read14_reg_10015_pp0_iter2_reg; + data_13_V_read14_reg_10015_pp0_iter4_reg <= data_13_V_read14_reg_10015_pp0_iter3_reg; + data_13_V_read14_reg_10015_pp0_iter5_reg <= data_13_V_read14_reg_10015_pp0_iter4_reg; + data_14_V_read15_reg_9987 <= data_14_V_read_int_reg; + data_14_V_read15_reg_9987_pp0_iter1_reg <= data_14_V_read15_reg_9987; + data_14_V_read15_reg_9987_pp0_iter2_reg <= data_14_V_read15_reg_9987_pp0_iter1_reg; + data_14_V_read15_reg_9987_pp0_iter3_reg <= data_14_V_read15_reg_9987_pp0_iter2_reg; + data_14_V_read15_reg_9987_pp0_iter4_reg <= data_14_V_read15_reg_9987_pp0_iter3_reg; + data_14_V_read15_reg_9987_pp0_iter5_reg <= data_14_V_read15_reg_9987_pp0_iter4_reg; + data_15_V_read16_reg_9962 <= data_15_V_read_int_reg; + data_15_V_read16_reg_9962_pp0_iter1_reg <= data_15_V_read16_reg_9962; + data_15_V_read16_reg_9962_pp0_iter2_reg <= data_15_V_read16_reg_9962_pp0_iter1_reg; + data_15_V_read16_reg_9962_pp0_iter3_reg <= data_15_V_read16_reg_9962_pp0_iter2_reg; + data_15_V_read16_reg_9962_pp0_iter4_reg <= data_15_V_read16_reg_9962_pp0_iter3_reg; + data_15_V_read16_reg_9962_pp0_iter5_reg <= data_15_V_read16_reg_9962_pp0_iter4_reg; + data_16_V_read17_reg_9935 <= data_16_V_read_int_reg; + data_16_V_read17_reg_9935_pp0_iter1_reg <= data_16_V_read17_reg_9935; + data_16_V_read17_reg_9935_pp0_iter2_reg <= data_16_V_read17_reg_9935_pp0_iter1_reg; + data_16_V_read17_reg_9935_pp0_iter3_reg <= data_16_V_read17_reg_9935_pp0_iter2_reg; + data_16_V_read17_reg_9935_pp0_iter4_reg <= data_16_V_read17_reg_9935_pp0_iter3_reg; + data_16_V_read17_reg_9935_pp0_iter5_reg <= data_16_V_read17_reg_9935_pp0_iter4_reg; + data_16_V_read17_reg_9935_pp0_iter6_reg <= data_16_V_read17_reg_9935_pp0_iter5_reg; + data_17_V_read18_reg_9904 <= data_17_V_read_int_reg; + data_17_V_read18_reg_9904_pp0_iter1_reg <= data_17_V_read18_reg_9904; + data_17_V_read18_reg_9904_pp0_iter2_reg <= data_17_V_read18_reg_9904_pp0_iter1_reg; + data_17_V_read18_reg_9904_pp0_iter3_reg <= data_17_V_read18_reg_9904_pp0_iter2_reg; + data_17_V_read18_reg_9904_pp0_iter4_reg <= data_17_V_read18_reg_9904_pp0_iter3_reg; + data_17_V_read18_reg_9904_pp0_iter5_reg <= data_17_V_read18_reg_9904_pp0_iter4_reg; + data_17_V_read18_reg_9904_pp0_iter6_reg <= data_17_V_read18_reg_9904_pp0_iter5_reg; + data_18_V_read_8_reg_9874 <= data_18_V_read_int_reg; + data_18_V_read_8_reg_9874_pp0_iter1_reg <= data_18_V_read_8_reg_9874; + data_18_V_read_8_reg_9874_pp0_iter2_reg <= data_18_V_read_8_reg_9874_pp0_iter1_reg; + data_18_V_read_8_reg_9874_pp0_iter3_reg <= data_18_V_read_8_reg_9874_pp0_iter2_reg; + data_18_V_read_8_reg_9874_pp0_iter4_reg <= data_18_V_read_8_reg_9874_pp0_iter3_reg; + data_18_V_read_8_reg_9874_pp0_iter5_reg <= data_18_V_read_8_reg_9874_pp0_iter4_reg; + data_18_V_read_8_reg_9874_pp0_iter6_reg <= data_18_V_read_8_reg_9874_pp0_iter5_reg; + data_19_V_read_8_reg_9845 <= data_19_V_read_int_reg; + data_19_V_read_8_reg_9845_pp0_iter1_reg <= data_19_V_read_8_reg_9845; + data_19_V_read_8_reg_9845_pp0_iter2_reg <= data_19_V_read_8_reg_9845_pp0_iter1_reg; + data_19_V_read_8_reg_9845_pp0_iter3_reg <= data_19_V_read_8_reg_9845_pp0_iter2_reg; + data_19_V_read_8_reg_9845_pp0_iter4_reg <= data_19_V_read_8_reg_9845_pp0_iter3_reg; + data_19_V_read_8_reg_9845_pp0_iter5_reg <= data_19_V_read_8_reg_9845_pp0_iter4_reg; + data_19_V_read_8_reg_9845_pp0_iter6_reg <= data_19_V_read_8_reg_9845_pp0_iter5_reg; + data_1_V_read_10_reg_10323 <= data_1_V_read_int_reg; + data_20_V_read21_reg_9814 <= data_20_V_read_int_reg; + data_20_V_read21_reg_9814_pp0_iter1_reg <= data_20_V_read21_reg_9814; + data_20_V_read21_reg_9814_pp0_iter2_reg <= data_20_V_read21_reg_9814_pp0_iter1_reg; + data_20_V_read21_reg_9814_pp0_iter3_reg <= data_20_V_read21_reg_9814_pp0_iter2_reg; + data_20_V_read21_reg_9814_pp0_iter4_reg <= data_20_V_read21_reg_9814_pp0_iter3_reg; + data_20_V_read21_reg_9814_pp0_iter5_reg <= data_20_V_read21_reg_9814_pp0_iter4_reg; + data_20_V_read21_reg_9814_pp0_iter6_reg <= data_20_V_read21_reg_9814_pp0_iter5_reg; + data_20_V_read21_reg_9814_pp0_iter7_reg <= data_20_V_read21_reg_9814_pp0_iter6_reg; + data_21_V_read22_reg_9784 <= data_21_V_read_int_reg; + data_21_V_read22_reg_9784_pp0_iter1_reg <= data_21_V_read22_reg_9784; + data_21_V_read22_reg_9784_pp0_iter2_reg <= data_21_V_read22_reg_9784_pp0_iter1_reg; + data_21_V_read22_reg_9784_pp0_iter3_reg <= data_21_V_read22_reg_9784_pp0_iter2_reg; + data_21_V_read22_reg_9784_pp0_iter4_reg <= data_21_V_read22_reg_9784_pp0_iter3_reg; + data_21_V_read22_reg_9784_pp0_iter5_reg <= data_21_V_read22_reg_9784_pp0_iter4_reg; + data_21_V_read22_reg_9784_pp0_iter6_reg <= data_21_V_read22_reg_9784_pp0_iter5_reg; + data_21_V_read22_reg_9784_pp0_iter7_reg <= data_21_V_read22_reg_9784_pp0_iter6_reg; + data_22_V_read23_reg_9756 <= data_22_V_read_int_reg; + data_22_V_read23_reg_9756_pp0_iter1_reg <= data_22_V_read23_reg_9756; + data_22_V_read23_reg_9756_pp0_iter2_reg <= data_22_V_read23_reg_9756_pp0_iter1_reg; + data_22_V_read23_reg_9756_pp0_iter3_reg <= data_22_V_read23_reg_9756_pp0_iter2_reg; + data_22_V_read23_reg_9756_pp0_iter4_reg <= data_22_V_read23_reg_9756_pp0_iter3_reg; + data_22_V_read23_reg_9756_pp0_iter5_reg <= data_22_V_read23_reg_9756_pp0_iter4_reg; + data_22_V_read23_reg_9756_pp0_iter6_reg <= data_22_V_read23_reg_9756_pp0_iter5_reg; + data_22_V_read23_reg_9756_pp0_iter7_reg <= data_22_V_read23_reg_9756_pp0_iter6_reg; + data_22_V_read23_reg_9756_pp0_iter8_reg <= data_22_V_read23_reg_9756_pp0_iter7_reg; + data_23_V_read24_reg_9730 <= data_23_V_read_int_reg; + data_23_V_read24_reg_9730_pp0_iter1_reg <= data_23_V_read24_reg_9730; + data_23_V_read24_reg_9730_pp0_iter2_reg <= data_23_V_read24_reg_9730_pp0_iter1_reg; + data_23_V_read24_reg_9730_pp0_iter3_reg <= data_23_V_read24_reg_9730_pp0_iter2_reg; + data_23_V_read24_reg_9730_pp0_iter4_reg <= data_23_V_read24_reg_9730_pp0_iter3_reg; + data_23_V_read24_reg_9730_pp0_iter5_reg <= data_23_V_read24_reg_9730_pp0_iter4_reg; + data_23_V_read24_reg_9730_pp0_iter6_reg <= data_23_V_read24_reg_9730_pp0_iter5_reg; + data_23_V_read24_reg_9730_pp0_iter7_reg <= data_23_V_read24_reg_9730_pp0_iter6_reg; + data_24_V_read25_reg_9704 <= data_24_V_read_int_reg; + data_24_V_read25_reg_9704_pp0_iter1_reg <= data_24_V_read25_reg_9704; + data_24_V_read25_reg_9704_pp0_iter2_reg <= data_24_V_read25_reg_9704_pp0_iter1_reg; + data_24_V_read25_reg_9704_pp0_iter3_reg <= data_24_V_read25_reg_9704_pp0_iter2_reg; + data_24_V_read25_reg_9704_pp0_iter4_reg <= data_24_V_read25_reg_9704_pp0_iter3_reg; + data_24_V_read25_reg_9704_pp0_iter5_reg <= data_24_V_read25_reg_9704_pp0_iter4_reg; + data_24_V_read25_reg_9704_pp0_iter6_reg <= data_24_V_read25_reg_9704_pp0_iter5_reg; + data_24_V_read25_reg_9704_pp0_iter7_reg <= data_24_V_read25_reg_9704_pp0_iter6_reg; + data_24_V_read25_reg_9704_pp0_iter8_reg <= data_24_V_read25_reg_9704_pp0_iter7_reg; + data_25_V_read26_reg_9677 <= data_25_V_read_int_reg; + data_25_V_read26_reg_9677_pp0_iter1_reg <= data_25_V_read26_reg_9677; + data_25_V_read26_reg_9677_pp0_iter2_reg <= data_25_V_read26_reg_9677_pp0_iter1_reg; + data_25_V_read26_reg_9677_pp0_iter3_reg <= data_25_V_read26_reg_9677_pp0_iter2_reg; + data_25_V_read26_reg_9677_pp0_iter4_reg <= data_25_V_read26_reg_9677_pp0_iter3_reg; + data_25_V_read26_reg_9677_pp0_iter5_reg <= data_25_V_read26_reg_9677_pp0_iter4_reg; + data_25_V_read26_reg_9677_pp0_iter6_reg <= data_25_V_read26_reg_9677_pp0_iter5_reg; + data_25_V_read26_reg_9677_pp0_iter7_reg <= data_25_V_read26_reg_9677_pp0_iter6_reg; + data_25_V_read26_reg_9677_pp0_iter8_reg <= data_25_V_read26_reg_9677_pp0_iter7_reg; + data_26_V_read27_reg_9652 <= data_26_V_read_int_reg; + data_26_V_read27_reg_9652_pp0_iter1_reg <= data_26_V_read27_reg_9652; + data_26_V_read27_reg_9652_pp0_iter2_reg <= data_26_V_read27_reg_9652_pp0_iter1_reg; + data_26_V_read27_reg_9652_pp0_iter3_reg <= data_26_V_read27_reg_9652_pp0_iter2_reg; + data_26_V_read27_reg_9652_pp0_iter4_reg <= data_26_V_read27_reg_9652_pp0_iter3_reg; + data_26_V_read27_reg_9652_pp0_iter5_reg <= data_26_V_read27_reg_9652_pp0_iter4_reg; + data_26_V_read27_reg_9652_pp0_iter6_reg <= data_26_V_read27_reg_9652_pp0_iter5_reg; + data_26_V_read27_reg_9652_pp0_iter7_reg <= data_26_V_read27_reg_9652_pp0_iter6_reg; + data_26_V_read27_reg_9652_pp0_iter8_reg <= data_26_V_read27_reg_9652_pp0_iter7_reg; + data_27_V_read28_reg_9625 <= data_27_V_read_int_reg; + data_27_V_read28_reg_9625_pp0_iter1_reg <= data_27_V_read28_reg_9625; + data_27_V_read28_reg_9625_pp0_iter2_reg <= data_27_V_read28_reg_9625_pp0_iter1_reg; + data_27_V_read28_reg_9625_pp0_iter3_reg <= data_27_V_read28_reg_9625_pp0_iter2_reg; + data_27_V_read28_reg_9625_pp0_iter4_reg <= data_27_V_read28_reg_9625_pp0_iter3_reg; + data_27_V_read28_reg_9625_pp0_iter5_reg <= data_27_V_read28_reg_9625_pp0_iter4_reg; + data_27_V_read28_reg_9625_pp0_iter6_reg <= data_27_V_read28_reg_9625_pp0_iter5_reg; + data_27_V_read28_reg_9625_pp0_iter7_reg <= data_27_V_read28_reg_9625_pp0_iter6_reg; + data_27_V_read28_reg_9625_pp0_iter8_reg <= data_27_V_read28_reg_9625_pp0_iter7_reg; + data_28_V_read_8_reg_9598 <= data_28_V_read_int_reg; + data_28_V_read_8_reg_9598_pp0_iter1_reg <= data_28_V_read_8_reg_9598; + data_28_V_read_8_reg_9598_pp0_iter2_reg <= data_28_V_read_8_reg_9598_pp0_iter1_reg; + data_28_V_read_8_reg_9598_pp0_iter3_reg <= data_28_V_read_8_reg_9598_pp0_iter2_reg; + data_28_V_read_8_reg_9598_pp0_iter4_reg <= data_28_V_read_8_reg_9598_pp0_iter3_reg; + data_28_V_read_8_reg_9598_pp0_iter5_reg <= data_28_V_read_8_reg_9598_pp0_iter4_reg; + data_28_V_read_8_reg_9598_pp0_iter6_reg <= data_28_V_read_8_reg_9598_pp0_iter5_reg; + data_28_V_read_8_reg_9598_pp0_iter7_reg <= data_28_V_read_8_reg_9598_pp0_iter6_reg; + data_28_V_read_8_reg_9598_pp0_iter8_reg <= data_28_V_read_8_reg_9598_pp0_iter7_reg; + data_29_V_read_8_reg_9573 <= data_29_V_read_int_reg; + data_29_V_read_8_reg_9573_pp0_iter1_reg <= data_29_V_read_8_reg_9573; + data_29_V_read_8_reg_9573_pp0_iter2_reg <= data_29_V_read_8_reg_9573_pp0_iter1_reg; + data_29_V_read_8_reg_9573_pp0_iter3_reg <= data_29_V_read_8_reg_9573_pp0_iter2_reg; + data_29_V_read_8_reg_9573_pp0_iter4_reg <= data_29_V_read_8_reg_9573_pp0_iter3_reg; + data_29_V_read_8_reg_9573_pp0_iter5_reg <= data_29_V_read_8_reg_9573_pp0_iter4_reg; + data_29_V_read_8_reg_9573_pp0_iter6_reg <= data_29_V_read_8_reg_9573_pp0_iter5_reg; + data_29_V_read_8_reg_9573_pp0_iter7_reg <= data_29_V_read_8_reg_9573_pp0_iter6_reg; + data_29_V_read_8_reg_9573_pp0_iter8_reg <= data_29_V_read_8_reg_9573_pp0_iter7_reg; + data_29_V_read_8_reg_9573_pp0_iter9_reg <= data_29_V_read_8_reg_9573_pp0_iter8_reg; + data_2_V_read_10_reg_10312 <= data_2_V_read_int_reg; + data_2_V_read_10_reg_10312_pp0_iter1_reg <= data_2_V_read_10_reg_10312; + data_30_V_read31_reg_9549 <= data_30_V_read_int_reg; + data_30_V_read31_reg_9549_pp0_iter1_reg <= data_30_V_read31_reg_9549; + data_30_V_read31_reg_9549_pp0_iter2_reg <= data_30_V_read31_reg_9549_pp0_iter1_reg; + data_30_V_read31_reg_9549_pp0_iter3_reg <= data_30_V_read31_reg_9549_pp0_iter2_reg; + data_30_V_read31_reg_9549_pp0_iter4_reg <= data_30_V_read31_reg_9549_pp0_iter3_reg; + data_30_V_read31_reg_9549_pp0_iter5_reg <= data_30_V_read31_reg_9549_pp0_iter4_reg; + data_30_V_read31_reg_9549_pp0_iter6_reg <= data_30_V_read31_reg_9549_pp0_iter5_reg; + data_30_V_read31_reg_9549_pp0_iter7_reg <= data_30_V_read31_reg_9549_pp0_iter6_reg; + data_30_V_read31_reg_9549_pp0_iter8_reg <= data_30_V_read31_reg_9549_pp0_iter7_reg; + data_30_V_read31_reg_9549_pp0_iter9_reg <= data_30_V_read31_reg_9549_pp0_iter8_reg; + data_31_V_read32_reg_9521 <= data_31_V_read_int_reg; + data_31_V_read32_reg_9521_pp0_iter1_reg <= data_31_V_read32_reg_9521; + data_31_V_read32_reg_9521_pp0_iter2_reg <= data_31_V_read32_reg_9521_pp0_iter1_reg; + data_31_V_read32_reg_9521_pp0_iter3_reg <= data_31_V_read32_reg_9521_pp0_iter2_reg; + data_31_V_read32_reg_9521_pp0_iter4_reg <= data_31_V_read32_reg_9521_pp0_iter3_reg; + data_31_V_read32_reg_9521_pp0_iter5_reg <= data_31_V_read32_reg_9521_pp0_iter4_reg; + data_31_V_read32_reg_9521_pp0_iter6_reg <= data_31_V_read32_reg_9521_pp0_iter5_reg; + data_31_V_read32_reg_9521_pp0_iter7_reg <= data_31_V_read32_reg_9521_pp0_iter6_reg; + data_31_V_read32_reg_9521_pp0_iter8_reg <= data_31_V_read32_reg_9521_pp0_iter7_reg; + data_31_V_read32_reg_9521_pp0_iter9_reg <= data_31_V_read32_reg_9521_pp0_iter8_reg; + data_32_V_read_3_reg_9492 <= data_32_V_read_int_reg; + data_32_V_read_3_reg_9492_pp0_iter1_reg <= data_32_V_read_3_reg_9492; + data_32_V_read_3_reg_9492_pp0_iter2_reg <= data_32_V_read_3_reg_9492_pp0_iter1_reg; + data_32_V_read_3_reg_9492_pp0_iter3_reg <= data_32_V_read_3_reg_9492_pp0_iter2_reg; + data_32_V_read_3_reg_9492_pp0_iter4_reg <= data_32_V_read_3_reg_9492_pp0_iter3_reg; + data_32_V_read_3_reg_9492_pp0_iter5_reg <= data_32_V_read_3_reg_9492_pp0_iter4_reg; + data_32_V_read_3_reg_9492_pp0_iter6_reg <= data_32_V_read_3_reg_9492_pp0_iter5_reg; + data_32_V_read_3_reg_9492_pp0_iter7_reg <= data_32_V_read_3_reg_9492_pp0_iter6_reg; + data_32_V_read_3_reg_9492_pp0_iter8_reg <= data_32_V_read_3_reg_9492_pp0_iter7_reg; + data_32_V_read_3_reg_9492_pp0_iter9_reg <= data_32_V_read_3_reg_9492_pp0_iter8_reg; + data_33_V_read_3_reg_9463 <= data_33_V_read_int_reg; + data_33_V_read_3_reg_9463_pp0_iter10_reg <= data_33_V_read_3_reg_9463_pp0_iter9_reg; + data_33_V_read_3_reg_9463_pp0_iter1_reg <= data_33_V_read_3_reg_9463; + data_33_V_read_3_reg_9463_pp0_iter2_reg <= data_33_V_read_3_reg_9463_pp0_iter1_reg; + data_33_V_read_3_reg_9463_pp0_iter3_reg <= data_33_V_read_3_reg_9463_pp0_iter2_reg; + data_33_V_read_3_reg_9463_pp0_iter4_reg <= data_33_V_read_3_reg_9463_pp0_iter3_reg; + data_33_V_read_3_reg_9463_pp0_iter5_reg <= data_33_V_read_3_reg_9463_pp0_iter4_reg; + data_33_V_read_3_reg_9463_pp0_iter6_reg <= data_33_V_read_3_reg_9463_pp0_iter5_reg; + data_33_V_read_3_reg_9463_pp0_iter7_reg <= data_33_V_read_3_reg_9463_pp0_iter6_reg; + data_33_V_read_3_reg_9463_pp0_iter8_reg <= data_33_V_read_3_reg_9463_pp0_iter7_reg; + data_33_V_read_3_reg_9463_pp0_iter9_reg <= data_33_V_read_3_reg_9463_pp0_iter8_reg; + data_34_V_read_3_reg_9434 <= data_34_V_read_int_reg; + data_34_V_read_3_reg_9434_pp0_iter10_reg <= data_34_V_read_3_reg_9434_pp0_iter9_reg; + data_34_V_read_3_reg_9434_pp0_iter1_reg <= data_34_V_read_3_reg_9434; + data_34_V_read_3_reg_9434_pp0_iter2_reg <= data_34_V_read_3_reg_9434_pp0_iter1_reg; + data_34_V_read_3_reg_9434_pp0_iter3_reg <= data_34_V_read_3_reg_9434_pp0_iter2_reg; + data_34_V_read_3_reg_9434_pp0_iter4_reg <= data_34_V_read_3_reg_9434_pp0_iter3_reg; + data_34_V_read_3_reg_9434_pp0_iter5_reg <= data_34_V_read_3_reg_9434_pp0_iter4_reg; + data_34_V_read_3_reg_9434_pp0_iter6_reg <= data_34_V_read_3_reg_9434_pp0_iter5_reg; + data_34_V_read_3_reg_9434_pp0_iter7_reg <= data_34_V_read_3_reg_9434_pp0_iter6_reg; + data_34_V_read_3_reg_9434_pp0_iter8_reg <= data_34_V_read_3_reg_9434_pp0_iter7_reg; + data_34_V_read_3_reg_9434_pp0_iter9_reg <= data_34_V_read_3_reg_9434_pp0_iter8_reg; + data_35_V_read_3_reg_9410 <= data_35_V_read_int_reg; + data_35_V_read_3_reg_9410_pp0_iter10_reg <= data_35_V_read_3_reg_9410_pp0_iter9_reg; + data_35_V_read_3_reg_9410_pp0_iter1_reg <= data_35_V_read_3_reg_9410; + data_35_V_read_3_reg_9410_pp0_iter2_reg <= data_35_V_read_3_reg_9410_pp0_iter1_reg; + data_35_V_read_3_reg_9410_pp0_iter3_reg <= data_35_V_read_3_reg_9410_pp0_iter2_reg; + data_35_V_read_3_reg_9410_pp0_iter4_reg <= data_35_V_read_3_reg_9410_pp0_iter3_reg; + data_35_V_read_3_reg_9410_pp0_iter5_reg <= data_35_V_read_3_reg_9410_pp0_iter4_reg; + data_35_V_read_3_reg_9410_pp0_iter6_reg <= data_35_V_read_3_reg_9410_pp0_iter5_reg; + data_35_V_read_3_reg_9410_pp0_iter7_reg <= data_35_V_read_3_reg_9410_pp0_iter6_reg; + data_35_V_read_3_reg_9410_pp0_iter8_reg <= data_35_V_read_3_reg_9410_pp0_iter7_reg; + data_35_V_read_3_reg_9410_pp0_iter9_reg <= data_35_V_read_3_reg_9410_pp0_iter8_reg; + data_36_V_read_3_reg_9383 <= data_36_V_read_int_reg; + data_36_V_read_3_reg_9383_pp0_iter10_reg <= data_36_V_read_3_reg_9383_pp0_iter9_reg; + data_36_V_read_3_reg_9383_pp0_iter1_reg <= data_36_V_read_3_reg_9383; + data_36_V_read_3_reg_9383_pp0_iter2_reg <= data_36_V_read_3_reg_9383_pp0_iter1_reg; + data_36_V_read_3_reg_9383_pp0_iter3_reg <= data_36_V_read_3_reg_9383_pp0_iter2_reg; + data_36_V_read_3_reg_9383_pp0_iter4_reg <= data_36_V_read_3_reg_9383_pp0_iter3_reg; + data_36_V_read_3_reg_9383_pp0_iter5_reg <= data_36_V_read_3_reg_9383_pp0_iter4_reg; + data_36_V_read_3_reg_9383_pp0_iter6_reg <= data_36_V_read_3_reg_9383_pp0_iter5_reg; + data_36_V_read_3_reg_9383_pp0_iter7_reg <= data_36_V_read_3_reg_9383_pp0_iter6_reg; + data_36_V_read_3_reg_9383_pp0_iter8_reg <= data_36_V_read_3_reg_9383_pp0_iter7_reg; + data_36_V_read_3_reg_9383_pp0_iter9_reg <= data_36_V_read_3_reg_9383_pp0_iter8_reg; + data_37_V_read_3_reg_9353 <= data_37_V_read_int_reg; + data_37_V_read_3_reg_9353_pp0_iter10_reg <= data_37_V_read_3_reg_9353_pp0_iter9_reg; + data_37_V_read_3_reg_9353_pp0_iter1_reg <= data_37_V_read_3_reg_9353; + data_37_V_read_3_reg_9353_pp0_iter2_reg <= data_37_V_read_3_reg_9353_pp0_iter1_reg; + data_37_V_read_3_reg_9353_pp0_iter3_reg <= data_37_V_read_3_reg_9353_pp0_iter2_reg; + data_37_V_read_3_reg_9353_pp0_iter4_reg <= data_37_V_read_3_reg_9353_pp0_iter3_reg; + data_37_V_read_3_reg_9353_pp0_iter5_reg <= data_37_V_read_3_reg_9353_pp0_iter4_reg; + data_37_V_read_3_reg_9353_pp0_iter6_reg <= data_37_V_read_3_reg_9353_pp0_iter5_reg; + data_37_V_read_3_reg_9353_pp0_iter7_reg <= data_37_V_read_3_reg_9353_pp0_iter6_reg; + data_37_V_read_3_reg_9353_pp0_iter8_reg <= data_37_V_read_3_reg_9353_pp0_iter7_reg; + data_37_V_read_3_reg_9353_pp0_iter9_reg <= data_37_V_read_3_reg_9353_pp0_iter8_reg; + data_38_V_read_3_reg_9328 <= data_38_V_read_int_reg; + data_38_V_read_3_reg_9328_pp0_iter10_reg <= data_38_V_read_3_reg_9328_pp0_iter9_reg; + data_38_V_read_3_reg_9328_pp0_iter11_reg <= data_38_V_read_3_reg_9328_pp0_iter10_reg; + data_38_V_read_3_reg_9328_pp0_iter1_reg <= data_38_V_read_3_reg_9328; + data_38_V_read_3_reg_9328_pp0_iter2_reg <= data_38_V_read_3_reg_9328_pp0_iter1_reg; + data_38_V_read_3_reg_9328_pp0_iter3_reg <= data_38_V_read_3_reg_9328_pp0_iter2_reg; + data_38_V_read_3_reg_9328_pp0_iter4_reg <= data_38_V_read_3_reg_9328_pp0_iter3_reg; + data_38_V_read_3_reg_9328_pp0_iter5_reg <= data_38_V_read_3_reg_9328_pp0_iter4_reg; + data_38_V_read_3_reg_9328_pp0_iter6_reg <= data_38_V_read_3_reg_9328_pp0_iter5_reg; + data_38_V_read_3_reg_9328_pp0_iter7_reg <= data_38_V_read_3_reg_9328_pp0_iter6_reg; + data_38_V_read_3_reg_9328_pp0_iter8_reg <= data_38_V_read_3_reg_9328_pp0_iter7_reg; + data_38_V_read_3_reg_9328_pp0_iter9_reg <= data_38_V_read_3_reg_9328_pp0_iter8_reg; + data_39_V_read_3_reg_9301 <= data_39_V_read_int_reg; + data_39_V_read_3_reg_9301_pp0_iter10_reg <= data_39_V_read_3_reg_9301_pp0_iter9_reg; + data_39_V_read_3_reg_9301_pp0_iter11_reg <= data_39_V_read_3_reg_9301_pp0_iter10_reg; + data_39_V_read_3_reg_9301_pp0_iter1_reg <= data_39_V_read_3_reg_9301; + data_39_V_read_3_reg_9301_pp0_iter2_reg <= data_39_V_read_3_reg_9301_pp0_iter1_reg; + data_39_V_read_3_reg_9301_pp0_iter3_reg <= data_39_V_read_3_reg_9301_pp0_iter2_reg; + data_39_V_read_3_reg_9301_pp0_iter4_reg <= data_39_V_read_3_reg_9301_pp0_iter3_reg; + data_39_V_read_3_reg_9301_pp0_iter5_reg <= data_39_V_read_3_reg_9301_pp0_iter4_reg; + data_39_V_read_3_reg_9301_pp0_iter6_reg <= data_39_V_read_3_reg_9301_pp0_iter5_reg; + data_39_V_read_3_reg_9301_pp0_iter7_reg <= data_39_V_read_3_reg_9301_pp0_iter6_reg; + data_39_V_read_3_reg_9301_pp0_iter8_reg <= data_39_V_read_3_reg_9301_pp0_iter7_reg; + data_39_V_read_3_reg_9301_pp0_iter9_reg <= data_39_V_read_3_reg_9301_pp0_iter8_reg; + data_3_V_read_10_reg_10295 <= data_3_V_read_int_reg; + data_3_V_read_10_reg_10295_pp0_iter1_reg <= data_3_V_read_10_reg_10295; + data_3_V_read_10_reg_10295_pp0_iter2_reg <= data_3_V_read_10_reg_10295_pp0_iter1_reg; + data_40_V_read41_reg_9272 <= data_40_V_read_int_reg; + data_40_V_read41_reg_9272_pp0_iter10_reg <= data_40_V_read41_reg_9272_pp0_iter9_reg; + data_40_V_read41_reg_9272_pp0_iter11_reg <= data_40_V_read41_reg_9272_pp0_iter10_reg; + data_40_V_read41_reg_9272_pp0_iter1_reg <= data_40_V_read41_reg_9272; + data_40_V_read41_reg_9272_pp0_iter2_reg <= data_40_V_read41_reg_9272_pp0_iter1_reg; + data_40_V_read41_reg_9272_pp0_iter3_reg <= data_40_V_read41_reg_9272_pp0_iter2_reg; + data_40_V_read41_reg_9272_pp0_iter4_reg <= data_40_V_read41_reg_9272_pp0_iter3_reg; + data_40_V_read41_reg_9272_pp0_iter5_reg <= data_40_V_read41_reg_9272_pp0_iter4_reg; + data_40_V_read41_reg_9272_pp0_iter6_reg <= data_40_V_read41_reg_9272_pp0_iter5_reg; + data_40_V_read41_reg_9272_pp0_iter7_reg <= data_40_V_read41_reg_9272_pp0_iter6_reg; + data_40_V_read41_reg_9272_pp0_iter8_reg <= data_40_V_read41_reg_9272_pp0_iter7_reg; + data_40_V_read41_reg_9272_pp0_iter9_reg <= data_40_V_read41_reg_9272_pp0_iter8_reg; + data_41_V_read42_reg_9242 <= data_41_V_read_int_reg; + data_41_V_read42_reg_9242_pp0_iter10_reg <= data_41_V_read42_reg_9242_pp0_iter9_reg; + data_41_V_read42_reg_9242_pp0_iter11_reg <= data_41_V_read42_reg_9242_pp0_iter10_reg; + data_41_V_read42_reg_9242_pp0_iter1_reg <= data_41_V_read42_reg_9242; + data_41_V_read42_reg_9242_pp0_iter2_reg <= data_41_V_read42_reg_9242_pp0_iter1_reg; + data_41_V_read42_reg_9242_pp0_iter3_reg <= data_41_V_read42_reg_9242_pp0_iter2_reg; + data_41_V_read42_reg_9242_pp0_iter4_reg <= data_41_V_read42_reg_9242_pp0_iter3_reg; + data_41_V_read42_reg_9242_pp0_iter5_reg <= data_41_V_read42_reg_9242_pp0_iter4_reg; + data_41_V_read42_reg_9242_pp0_iter6_reg <= data_41_V_read42_reg_9242_pp0_iter5_reg; + data_41_V_read42_reg_9242_pp0_iter7_reg <= data_41_V_read42_reg_9242_pp0_iter6_reg; + data_41_V_read42_reg_9242_pp0_iter8_reg <= data_41_V_read42_reg_9242_pp0_iter7_reg; + data_41_V_read42_reg_9242_pp0_iter9_reg <= data_41_V_read42_reg_9242_pp0_iter8_reg; + data_42_V_read_3_reg_9212 <= data_42_V_read_int_reg; + data_42_V_read_3_reg_9212_pp0_iter10_reg <= data_42_V_read_3_reg_9212_pp0_iter9_reg; + data_42_V_read_3_reg_9212_pp0_iter11_reg <= data_42_V_read_3_reg_9212_pp0_iter10_reg; + data_42_V_read_3_reg_9212_pp0_iter12_reg <= data_42_V_read_3_reg_9212_pp0_iter11_reg; + data_42_V_read_3_reg_9212_pp0_iter1_reg <= data_42_V_read_3_reg_9212; + data_42_V_read_3_reg_9212_pp0_iter2_reg <= data_42_V_read_3_reg_9212_pp0_iter1_reg; + data_42_V_read_3_reg_9212_pp0_iter3_reg <= data_42_V_read_3_reg_9212_pp0_iter2_reg; + data_42_V_read_3_reg_9212_pp0_iter4_reg <= data_42_V_read_3_reg_9212_pp0_iter3_reg; + data_42_V_read_3_reg_9212_pp0_iter5_reg <= data_42_V_read_3_reg_9212_pp0_iter4_reg; + data_42_V_read_3_reg_9212_pp0_iter6_reg <= data_42_V_read_3_reg_9212_pp0_iter5_reg; + data_42_V_read_3_reg_9212_pp0_iter7_reg <= data_42_V_read_3_reg_9212_pp0_iter6_reg; + data_42_V_read_3_reg_9212_pp0_iter8_reg <= data_42_V_read_3_reg_9212_pp0_iter7_reg; + data_42_V_read_3_reg_9212_pp0_iter9_reg <= data_42_V_read_3_reg_9212_pp0_iter8_reg; + data_43_V_read_3_reg_9184 <= data_43_V_read_int_reg; + data_43_V_read_3_reg_9184_pp0_iter10_reg <= data_43_V_read_3_reg_9184_pp0_iter9_reg; + data_43_V_read_3_reg_9184_pp0_iter11_reg <= data_43_V_read_3_reg_9184_pp0_iter10_reg; + data_43_V_read_3_reg_9184_pp0_iter12_reg <= data_43_V_read_3_reg_9184_pp0_iter11_reg; + data_43_V_read_3_reg_9184_pp0_iter1_reg <= data_43_V_read_3_reg_9184; + data_43_V_read_3_reg_9184_pp0_iter2_reg <= data_43_V_read_3_reg_9184_pp0_iter1_reg; + data_43_V_read_3_reg_9184_pp0_iter3_reg <= data_43_V_read_3_reg_9184_pp0_iter2_reg; + data_43_V_read_3_reg_9184_pp0_iter4_reg <= data_43_V_read_3_reg_9184_pp0_iter3_reg; + data_43_V_read_3_reg_9184_pp0_iter5_reg <= data_43_V_read_3_reg_9184_pp0_iter4_reg; + data_43_V_read_3_reg_9184_pp0_iter6_reg <= data_43_V_read_3_reg_9184_pp0_iter5_reg; + data_43_V_read_3_reg_9184_pp0_iter7_reg <= data_43_V_read_3_reg_9184_pp0_iter6_reg; + data_43_V_read_3_reg_9184_pp0_iter8_reg <= data_43_V_read_3_reg_9184_pp0_iter7_reg; + data_43_V_read_3_reg_9184_pp0_iter9_reg <= data_43_V_read_3_reg_9184_pp0_iter8_reg; + data_44_V_read_3_reg_9154 <= data_44_V_read_int_reg; + data_44_V_read_3_reg_9154_pp0_iter10_reg <= data_44_V_read_3_reg_9154_pp0_iter9_reg; + data_44_V_read_3_reg_9154_pp0_iter11_reg <= data_44_V_read_3_reg_9154_pp0_iter10_reg; + data_44_V_read_3_reg_9154_pp0_iter12_reg <= data_44_V_read_3_reg_9154_pp0_iter11_reg; + data_44_V_read_3_reg_9154_pp0_iter1_reg <= data_44_V_read_3_reg_9154; + data_44_V_read_3_reg_9154_pp0_iter2_reg <= data_44_V_read_3_reg_9154_pp0_iter1_reg; + data_44_V_read_3_reg_9154_pp0_iter3_reg <= data_44_V_read_3_reg_9154_pp0_iter2_reg; + data_44_V_read_3_reg_9154_pp0_iter4_reg <= data_44_V_read_3_reg_9154_pp0_iter3_reg; + data_44_V_read_3_reg_9154_pp0_iter5_reg <= data_44_V_read_3_reg_9154_pp0_iter4_reg; + data_44_V_read_3_reg_9154_pp0_iter6_reg <= data_44_V_read_3_reg_9154_pp0_iter5_reg; + data_44_V_read_3_reg_9154_pp0_iter7_reg <= data_44_V_read_3_reg_9154_pp0_iter6_reg; + data_44_V_read_3_reg_9154_pp0_iter8_reg <= data_44_V_read_3_reg_9154_pp0_iter7_reg; + data_44_V_read_3_reg_9154_pp0_iter9_reg <= data_44_V_read_3_reg_9154_pp0_iter8_reg; + data_45_V_read_3_reg_9125 <= data_45_V_read_int_reg; + data_45_V_read_3_reg_9125_pp0_iter10_reg <= data_45_V_read_3_reg_9125_pp0_iter9_reg; + data_45_V_read_3_reg_9125_pp0_iter11_reg <= data_45_V_read_3_reg_9125_pp0_iter10_reg; + data_45_V_read_3_reg_9125_pp0_iter12_reg <= data_45_V_read_3_reg_9125_pp0_iter11_reg; + data_45_V_read_3_reg_9125_pp0_iter1_reg <= data_45_V_read_3_reg_9125; + data_45_V_read_3_reg_9125_pp0_iter2_reg <= data_45_V_read_3_reg_9125_pp0_iter1_reg; + data_45_V_read_3_reg_9125_pp0_iter3_reg <= data_45_V_read_3_reg_9125_pp0_iter2_reg; + data_45_V_read_3_reg_9125_pp0_iter4_reg <= data_45_V_read_3_reg_9125_pp0_iter3_reg; + data_45_V_read_3_reg_9125_pp0_iter5_reg <= data_45_V_read_3_reg_9125_pp0_iter4_reg; + data_45_V_read_3_reg_9125_pp0_iter6_reg <= data_45_V_read_3_reg_9125_pp0_iter5_reg; + data_45_V_read_3_reg_9125_pp0_iter7_reg <= data_45_V_read_3_reg_9125_pp0_iter6_reg; + data_45_V_read_3_reg_9125_pp0_iter8_reg <= data_45_V_read_3_reg_9125_pp0_iter7_reg; + data_45_V_read_3_reg_9125_pp0_iter9_reg <= data_45_V_read_3_reg_9125_pp0_iter8_reg; + data_46_V_read_3_reg_9094 <= data_46_V_read_int_reg; + data_46_V_read_3_reg_9094_pp0_iter10_reg <= data_46_V_read_3_reg_9094_pp0_iter9_reg; + data_46_V_read_3_reg_9094_pp0_iter11_reg <= data_46_V_read_3_reg_9094_pp0_iter10_reg; + data_46_V_read_3_reg_9094_pp0_iter12_reg <= data_46_V_read_3_reg_9094_pp0_iter11_reg; + data_46_V_read_3_reg_9094_pp0_iter13_reg <= data_46_V_read_3_reg_9094_pp0_iter12_reg; + data_46_V_read_3_reg_9094_pp0_iter1_reg <= data_46_V_read_3_reg_9094; + data_46_V_read_3_reg_9094_pp0_iter2_reg <= data_46_V_read_3_reg_9094_pp0_iter1_reg; + data_46_V_read_3_reg_9094_pp0_iter3_reg <= data_46_V_read_3_reg_9094_pp0_iter2_reg; + data_46_V_read_3_reg_9094_pp0_iter4_reg <= data_46_V_read_3_reg_9094_pp0_iter3_reg; + data_46_V_read_3_reg_9094_pp0_iter5_reg <= data_46_V_read_3_reg_9094_pp0_iter4_reg; + data_46_V_read_3_reg_9094_pp0_iter6_reg <= data_46_V_read_3_reg_9094_pp0_iter5_reg; + data_46_V_read_3_reg_9094_pp0_iter7_reg <= data_46_V_read_3_reg_9094_pp0_iter6_reg; + data_46_V_read_3_reg_9094_pp0_iter8_reg <= data_46_V_read_3_reg_9094_pp0_iter7_reg; + data_46_V_read_3_reg_9094_pp0_iter9_reg <= data_46_V_read_3_reg_9094_pp0_iter8_reg; + data_47_V_read_3_reg_9066 <= data_47_V_read_int_reg; + data_47_V_read_3_reg_9066_pp0_iter10_reg <= data_47_V_read_3_reg_9066_pp0_iter9_reg; + data_47_V_read_3_reg_9066_pp0_iter11_reg <= data_47_V_read_3_reg_9066_pp0_iter10_reg; + data_47_V_read_3_reg_9066_pp0_iter12_reg <= data_47_V_read_3_reg_9066_pp0_iter11_reg; + data_47_V_read_3_reg_9066_pp0_iter13_reg <= data_47_V_read_3_reg_9066_pp0_iter12_reg; + data_47_V_read_3_reg_9066_pp0_iter1_reg <= data_47_V_read_3_reg_9066; + data_47_V_read_3_reg_9066_pp0_iter2_reg <= data_47_V_read_3_reg_9066_pp0_iter1_reg; + data_47_V_read_3_reg_9066_pp0_iter3_reg <= data_47_V_read_3_reg_9066_pp0_iter2_reg; + data_47_V_read_3_reg_9066_pp0_iter4_reg <= data_47_V_read_3_reg_9066_pp0_iter3_reg; + data_47_V_read_3_reg_9066_pp0_iter5_reg <= data_47_V_read_3_reg_9066_pp0_iter4_reg; + data_47_V_read_3_reg_9066_pp0_iter6_reg <= data_47_V_read_3_reg_9066_pp0_iter5_reg; + data_47_V_read_3_reg_9066_pp0_iter7_reg <= data_47_V_read_3_reg_9066_pp0_iter6_reg; + data_47_V_read_3_reg_9066_pp0_iter8_reg <= data_47_V_read_3_reg_9066_pp0_iter7_reg; + data_47_V_read_3_reg_9066_pp0_iter9_reg <= data_47_V_read_3_reg_9066_pp0_iter8_reg; + data_48_V_read_3_reg_9040 <= data_48_V_read_int_reg; + data_48_V_read_3_reg_9040_pp0_iter10_reg <= data_48_V_read_3_reg_9040_pp0_iter9_reg; + data_48_V_read_3_reg_9040_pp0_iter11_reg <= data_48_V_read_3_reg_9040_pp0_iter10_reg; + data_48_V_read_3_reg_9040_pp0_iter12_reg <= data_48_V_read_3_reg_9040_pp0_iter11_reg; + data_48_V_read_3_reg_9040_pp0_iter13_reg <= data_48_V_read_3_reg_9040_pp0_iter12_reg; + data_48_V_read_3_reg_9040_pp0_iter1_reg <= data_48_V_read_3_reg_9040; + data_48_V_read_3_reg_9040_pp0_iter2_reg <= data_48_V_read_3_reg_9040_pp0_iter1_reg; + data_48_V_read_3_reg_9040_pp0_iter3_reg <= data_48_V_read_3_reg_9040_pp0_iter2_reg; + data_48_V_read_3_reg_9040_pp0_iter4_reg <= data_48_V_read_3_reg_9040_pp0_iter3_reg; + data_48_V_read_3_reg_9040_pp0_iter5_reg <= data_48_V_read_3_reg_9040_pp0_iter4_reg; + data_48_V_read_3_reg_9040_pp0_iter6_reg <= data_48_V_read_3_reg_9040_pp0_iter5_reg; + data_48_V_read_3_reg_9040_pp0_iter7_reg <= data_48_V_read_3_reg_9040_pp0_iter6_reg; + data_48_V_read_3_reg_9040_pp0_iter8_reg <= data_48_V_read_3_reg_9040_pp0_iter7_reg; + data_48_V_read_3_reg_9040_pp0_iter9_reg <= data_48_V_read_3_reg_9040_pp0_iter8_reg; + data_49_V_read_3_reg_9012 <= data_49_V_read_int_reg; + data_49_V_read_3_reg_9012_pp0_iter10_reg <= data_49_V_read_3_reg_9012_pp0_iter9_reg; + data_49_V_read_3_reg_9012_pp0_iter11_reg <= data_49_V_read_3_reg_9012_pp0_iter10_reg; + data_49_V_read_3_reg_9012_pp0_iter12_reg <= data_49_V_read_3_reg_9012_pp0_iter11_reg; + data_49_V_read_3_reg_9012_pp0_iter13_reg <= data_49_V_read_3_reg_9012_pp0_iter12_reg; + data_49_V_read_3_reg_9012_pp0_iter1_reg <= data_49_V_read_3_reg_9012; + data_49_V_read_3_reg_9012_pp0_iter2_reg <= data_49_V_read_3_reg_9012_pp0_iter1_reg; + data_49_V_read_3_reg_9012_pp0_iter3_reg <= data_49_V_read_3_reg_9012_pp0_iter2_reg; + data_49_V_read_3_reg_9012_pp0_iter4_reg <= data_49_V_read_3_reg_9012_pp0_iter3_reg; + data_49_V_read_3_reg_9012_pp0_iter5_reg <= data_49_V_read_3_reg_9012_pp0_iter4_reg; + data_49_V_read_3_reg_9012_pp0_iter6_reg <= data_49_V_read_3_reg_9012_pp0_iter5_reg; + data_49_V_read_3_reg_9012_pp0_iter7_reg <= data_49_V_read_3_reg_9012_pp0_iter6_reg; + data_49_V_read_3_reg_9012_pp0_iter8_reg <= data_49_V_read_3_reg_9012_pp0_iter7_reg; + data_49_V_read_3_reg_9012_pp0_iter9_reg <= data_49_V_read_3_reg_9012_pp0_iter8_reg; + data_4_V_read_10_reg_10273 <= data_4_V_read_int_reg; + data_4_V_read_10_reg_10273_pp0_iter1_reg <= data_4_V_read_10_reg_10273; + data_4_V_read_10_reg_10273_pp0_iter2_reg <= data_4_V_read_10_reg_10273_pp0_iter1_reg; + data_4_V_read_10_reg_10273_pp0_iter3_reg <= data_4_V_read_10_reg_10273_pp0_iter2_reg; + data_50_V_read51_reg_8984 <= data_50_V_read_int_reg; + data_50_V_read51_reg_8984_pp0_iter10_reg <= data_50_V_read51_reg_8984_pp0_iter9_reg; + data_50_V_read51_reg_8984_pp0_iter11_reg <= data_50_V_read51_reg_8984_pp0_iter10_reg; + data_50_V_read51_reg_8984_pp0_iter12_reg <= data_50_V_read51_reg_8984_pp0_iter11_reg; + data_50_V_read51_reg_8984_pp0_iter13_reg <= data_50_V_read51_reg_8984_pp0_iter12_reg; + data_50_V_read51_reg_8984_pp0_iter14_reg <= data_50_V_read51_reg_8984_pp0_iter13_reg; + data_50_V_read51_reg_8984_pp0_iter1_reg <= data_50_V_read51_reg_8984; + data_50_V_read51_reg_8984_pp0_iter2_reg <= data_50_V_read51_reg_8984_pp0_iter1_reg; + data_50_V_read51_reg_8984_pp0_iter3_reg <= data_50_V_read51_reg_8984_pp0_iter2_reg; + data_50_V_read51_reg_8984_pp0_iter4_reg <= data_50_V_read51_reg_8984_pp0_iter3_reg; + data_50_V_read51_reg_8984_pp0_iter5_reg <= data_50_V_read51_reg_8984_pp0_iter4_reg; + data_50_V_read51_reg_8984_pp0_iter6_reg <= data_50_V_read51_reg_8984_pp0_iter5_reg; + data_50_V_read51_reg_8984_pp0_iter7_reg <= data_50_V_read51_reg_8984_pp0_iter6_reg; + data_50_V_read51_reg_8984_pp0_iter8_reg <= data_50_V_read51_reg_8984_pp0_iter7_reg; + data_50_V_read51_reg_8984_pp0_iter9_reg <= data_50_V_read51_reg_8984_pp0_iter8_reg; + data_51_V_read52_reg_8956 <= data_51_V_read_int_reg; + data_51_V_read52_reg_8956_pp0_iter10_reg <= data_51_V_read52_reg_8956_pp0_iter9_reg; + data_51_V_read52_reg_8956_pp0_iter11_reg <= data_51_V_read52_reg_8956_pp0_iter10_reg; + data_51_V_read52_reg_8956_pp0_iter12_reg <= data_51_V_read52_reg_8956_pp0_iter11_reg; + data_51_V_read52_reg_8956_pp0_iter13_reg <= data_51_V_read52_reg_8956_pp0_iter12_reg; + data_51_V_read52_reg_8956_pp0_iter14_reg <= data_51_V_read52_reg_8956_pp0_iter13_reg; + data_51_V_read52_reg_8956_pp0_iter1_reg <= data_51_V_read52_reg_8956; + data_51_V_read52_reg_8956_pp0_iter2_reg <= data_51_V_read52_reg_8956_pp0_iter1_reg; + data_51_V_read52_reg_8956_pp0_iter3_reg <= data_51_V_read52_reg_8956_pp0_iter2_reg; + data_51_V_read52_reg_8956_pp0_iter4_reg <= data_51_V_read52_reg_8956_pp0_iter3_reg; + data_51_V_read52_reg_8956_pp0_iter5_reg <= data_51_V_read52_reg_8956_pp0_iter4_reg; + data_51_V_read52_reg_8956_pp0_iter6_reg <= data_51_V_read52_reg_8956_pp0_iter5_reg; + data_51_V_read52_reg_8956_pp0_iter7_reg <= data_51_V_read52_reg_8956_pp0_iter6_reg; + data_51_V_read52_reg_8956_pp0_iter8_reg <= data_51_V_read52_reg_8956_pp0_iter7_reg; + data_51_V_read52_reg_8956_pp0_iter9_reg <= data_51_V_read52_reg_8956_pp0_iter8_reg; + data_52_V_read_3_reg_8928 <= data_52_V_read_int_reg; + data_52_V_read_3_reg_8928_pp0_iter10_reg <= data_52_V_read_3_reg_8928_pp0_iter9_reg; + data_52_V_read_3_reg_8928_pp0_iter11_reg <= data_52_V_read_3_reg_8928_pp0_iter10_reg; + data_52_V_read_3_reg_8928_pp0_iter12_reg <= data_52_V_read_3_reg_8928_pp0_iter11_reg; + data_52_V_read_3_reg_8928_pp0_iter13_reg <= data_52_V_read_3_reg_8928_pp0_iter12_reg; + data_52_V_read_3_reg_8928_pp0_iter14_reg <= data_52_V_read_3_reg_8928_pp0_iter13_reg; + data_52_V_read_3_reg_8928_pp0_iter1_reg <= data_52_V_read_3_reg_8928; + data_52_V_read_3_reg_8928_pp0_iter2_reg <= data_52_V_read_3_reg_8928_pp0_iter1_reg; + data_52_V_read_3_reg_8928_pp0_iter3_reg <= data_52_V_read_3_reg_8928_pp0_iter2_reg; + data_52_V_read_3_reg_8928_pp0_iter4_reg <= data_52_V_read_3_reg_8928_pp0_iter3_reg; + data_52_V_read_3_reg_8928_pp0_iter5_reg <= data_52_V_read_3_reg_8928_pp0_iter4_reg; + data_52_V_read_3_reg_8928_pp0_iter6_reg <= data_52_V_read_3_reg_8928_pp0_iter5_reg; + data_52_V_read_3_reg_8928_pp0_iter7_reg <= data_52_V_read_3_reg_8928_pp0_iter6_reg; + data_52_V_read_3_reg_8928_pp0_iter8_reg <= data_52_V_read_3_reg_8928_pp0_iter7_reg; + data_52_V_read_3_reg_8928_pp0_iter9_reg <= data_52_V_read_3_reg_8928_pp0_iter8_reg; + data_53_V_read_3_reg_8899 <= data_53_V_read_int_reg; + data_53_V_read_3_reg_8899_pp0_iter10_reg <= data_53_V_read_3_reg_8899_pp0_iter9_reg; + data_53_V_read_3_reg_8899_pp0_iter11_reg <= data_53_V_read_3_reg_8899_pp0_iter10_reg; + data_53_V_read_3_reg_8899_pp0_iter12_reg <= data_53_V_read_3_reg_8899_pp0_iter11_reg; + data_53_V_read_3_reg_8899_pp0_iter13_reg <= data_53_V_read_3_reg_8899_pp0_iter12_reg; + data_53_V_read_3_reg_8899_pp0_iter14_reg <= data_53_V_read_3_reg_8899_pp0_iter13_reg; + data_53_V_read_3_reg_8899_pp0_iter1_reg <= data_53_V_read_3_reg_8899; + data_53_V_read_3_reg_8899_pp0_iter2_reg <= data_53_V_read_3_reg_8899_pp0_iter1_reg; + data_53_V_read_3_reg_8899_pp0_iter3_reg <= data_53_V_read_3_reg_8899_pp0_iter2_reg; + data_53_V_read_3_reg_8899_pp0_iter4_reg <= data_53_V_read_3_reg_8899_pp0_iter3_reg; + data_53_V_read_3_reg_8899_pp0_iter5_reg <= data_53_V_read_3_reg_8899_pp0_iter4_reg; + data_53_V_read_3_reg_8899_pp0_iter6_reg <= data_53_V_read_3_reg_8899_pp0_iter5_reg; + data_53_V_read_3_reg_8899_pp0_iter7_reg <= data_53_V_read_3_reg_8899_pp0_iter6_reg; + data_53_V_read_3_reg_8899_pp0_iter8_reg <= data_53_V_read_3_reg_8899_pp0_iter7_reg; + data_53_V_read_3_reg_8899_pp0_iter9_reg <= data_53_V_read_3_reg_8899_pp0_iter8_reg; + data_54_V_read_3_reg_8873 <= data_54_V_read_int_reg; + data_54_V_read_3_reg_8873_pp0_iter10_reg <= data_54_V_read_3_reg_8873_pp0_iter9_reg; + data_54_V_read_3_reg_8873_pp0_iter11_reg <= data_54_V_read_3_reg_8873_pp0_iter10_reg; + data_54_V_read_3_reg_8873_pp0_iter12_reg <= data_54_V_read_3_reg_8873_pp0_iter11_reg; + data_54_V_read_3_reg_8873_pp0_iter13_reg <= data_54_V_read_3_reg_8873_pp0_iter12_reg; + data_54_V_read_3_reg_8873_pp0_iter14_reg <= data_54_V_read_3_reg_8873_pp0_iter13_reg; + data_54_V_read_3_reg_8873_pp0_iter1_reg <= data_54_V_read_3_reg_8873; + data_54_V_read_3_reg_8873_pp0_iter2_reg <= data_54_V_read_3_reg_8873_pp0_iter1_reg; + data_54_V_read_3_reg_8873_pp0_iter3_reg <= data_54_V_read_3_reg_8873_pp0_iter2_reg; + data_54_V_read_3_reg_8873_pp0_iter4_reg <= data_54_V_read_3_reg_8873_pp0_iter3_reg; + data_54_V_read_3_reg_8873_pp0_iter5_reg <= data_54_V_read_3_reg_8873_pp0_iter4_reg; + data_54_V_read_3_reg_8873_pp0_iter6_reg <= data_54_V_read_3_reg_8873_pp0_iter5_reg; + data_54_V_read_3_reg_8873_pp0_iter7_reg <= data_54_V_read_3_reg_8873_pp0_iter6_reg; + data_54_V_read_3_reg_8873_pp0_iter8_reg <= data_54_V_read_3_reg_8873_pp0_iter7_reg; + data_54_V_read_3_reg_8873_pp0_iter9_reg <= data_54_V_read_3_reg_8873_pp0_iter8_reg; + data_55_V_read_3_reg_8844 <= data_55_V_read_int_reg; + data_55_V_read_3_reg_8844_pp0_iter10_reg <= data_55_V_read_3_reg_8844_pp0_iter9_reg; + data_55_V_read_3_reg_8844_pp0_iter11_reg <= data_55_V_read_3_reg_8844_pp0_iter10_reg; + data_55_V_read_3_reg_8844_pp0_iter12_reg <= data_55_V_read_3_reg_8844_pp0_iter11_reg; + data_55_V_read_3_reg_8844_pp0_iter13_reg <= data_55_V_read_3_reg_8844_pp0_iter12_reg; + data_55_V_read_3_reg_8844_pp0_iter14_reg <= data_55_V_read_3_reg_8844_pp0_iter13_reg; + data_55_V_read_3_reg_8844_pp0_iter15_reg <= data_55_V_read_3_reg_8844_pp0_iter14_reg; + data_55_V_read_3_reg_8844_pp0_iter1_reg <= data_55_V_read_3_reg_8844; + data_55_V_read_3_reg_8844_pp0_iter2_reg <= data_55_V_read_3_reg_8844_pp0_iter1_reg; + data_55_V_read_3_reg_8844_pp0_iter3_reg <= data_55_V_read_3_reg_8844_pp0_iter2_reg; + data_55_V_read_3_reg_8844_pp0_iter4_reg <= data_55_V_read_3_reg_8844_pp0_iter3_reg; + data_55_V_read_3_reg_8844_pp0_iter5_reg <= data_55_V_read_3_reg_8844_pp0_iter4_reg; + data_55_V_read_3_reg_8844_pp0_iter6_reg <= data_55_V_read_3_reg_8844_pp0_iter5_reg; + data_55_V_read_3_reg_8844_pp0_iter7_reg <= data_55_V_read_3_reg_8844_pp0_iter6_reg; + data_55_V_read_3_reg_8844_pp0_iter8_reg <= data_55_V_read_3_reg_8844_pp0_iter7_reg; + data_55_V_read_3_reg_8844_pp0_iter9_reg <= data_55_V_read_3_reg_8844_pp0_iter8_reg; + data_56_V_read_3_reg_8814 <= data_56_V_read_int_reg; + data_56_V_read_3_reg_8814_pp0_iter10_reg <= data_56_V_read_3_reg_8814_pp0_iter9_reg; + data_56_V_read_3_reg_8814_pp0_iter11_reg <= data_56_V_read_3_reg_8814_pp0_iter10_reg; + data_56_V_read_3_reg_8814_pp0_iter12_reg <= data_56_V_read_3_reg_8814_pp0_iter11_reg; + data_56_V_read_3_reg_8814_pp0_iter13_reg <= data_56_V_read_3_reg_8814_pp0_iter12_reg; + data_56_V_read_3_reg_8814_pp0_iter14_reg <= data_56_V_read_3_reg_8814_pp0_iter13_reg; + data_56_V_read_3_reg_8814_pp0_iter15_reg <= data_56_V_read_3_reg_8814_pp0_iter14_reg; + data_56_V_read_3_reg_8814_pp0_iter1_reg <= data_56_V_read_3_reg_8814; + data_56_V_read_3_reg_8814_pp0_iter2_reg <= data_56_V_read_3_reg_8814_pp0_iter1_reg; + data_56_V_read_3_reg_8814_pp0_iter3_reg <= data_56_V_read_3_reg_8814_pp0_iter2_reg; + data_56_V_read_3_reg_8814_pp0_iter4_reg <= data_56_V_read_3_reg_8814_pp0_iter3_reg; + data_56_V_read_3_reg_8814_pp0_iter5_reg <= data_56_V_read_3_reg_8814_pp0_iter4_reg; + data_56_V_read_3_reg_8814_pp0_iter6_reg <= data_56_V_read_3_reg_8814_pp0_iter5_reg; + data_56_V_read_3_reg_8814_pp0_iter7_reg <= data_56_V_read_3_reg_8814_pp0_iter6_reg; + data_56_V_read_3_reg_8814_pp0_iter8_reg <= data_56_V_read_3_reg_8814_pp0_iter7_reg; + data_56_V_read_3_reg_8814_pp0_iter9_reg <= data_56_V_read_3_reg_8814_pp0_iter8_reg; + data_57_V_read_3_reg_8786 <= data_57_V_read_int_reg; + data_57_V_read_3_reg_8786_pp0_iter10_reg <= data_57_V_read_3_reg_8786_pp0_iter9_reg; + data_57_V_read_3_reg_8786_pp0_iter11_reg <= data_57_V_read_3_reg_8786_pp0_iter10_reg; + data_57_V_read_3_reg_8786_pp0_iter12_reg <= data_57_V_read_3_reg_8786_pp0_iter11_reg; + data_57_V_read_3_reg_8786_pp0_iter13_reg <= data_57_V_read_3_reg_8786_pp0_iter12_reg; + data_57_V_read_3_reg_8786_pp0_iter14_reg <= data_57_V_read_3_reg_8786_pp0_iter13_reg; + data_57_V_read_3_reg_8786_pp0_iter15_reg <= data_57_V_read_3_reg_8786_pp0_iter14_reg; + data_57_V_read_3_reg_8786_pp0_iter1_reg <= data_57_V_read_3_reg_8786; + data_57_V_read_3_reg_8786_pp0_iter2_reg <= data_57_V_read_3_reg_8786_pp0_iter1_reg; + data_57_V_read_3_reg_8786_pp0_iter3_reg <= data_57_V_read_3_reg_8786_pp0_iter2_reg; + data_57_V_read_3_reg_8786_pp0_iter4_reg <= data_57_V_read_3_reg_8786_pp0_iter3_reg; + data_57_V_read_3_reg_8786_pp0_iter5_reg <= data_57_V_read_3_reg_8786_pp0_iter4_reg; + data_57_V_read_3_reg_8786_pp0_iter6_reg <= data_57_V_read_3_reg_8786_pp0_iter5_reg; + data_57_V_read_3_reg_8786_pp0_iter7_reg <= data_57_V_read_3_reg_8786_pp0_iter6_reg; + data_57_V_read_3_reg_8786_pp0_iter8_reg <= data_57_V_read_3_reg_8786_pp0_iter7_reg; + data_57_V_read_3_reg_8786_pp0_iter9_reg <= data_57_V_read_3_reg_8786_pp0_iter8_reg; + data_58_V_read_3_reg_8756 <= data_58_V_read_int_reg; + data_58_V_read_3_reg_8756_pp0_iter10_reg <= data_58_V_read_3_reg_8756_pp0_iter9_reg; + data_58_V_read_3_reg_8756_pp0_iter11_reg <= data_58_V_read_3_reg_8756_pp0_iter10_reg; + data_58_V_read_3_reg_8756_pp0_iter12_reg <= data_58_V_read_3_reg_8756_pp0_iter11_reg; + data_58_V_read_3_reg_8756_pp0_iter13_reg <= data_58_V_read_3_reg_8756_pp0_iter12_reg; + data_58_V_read_3_reg_8756_pp0_iter14_reg <= data_58_V_read_3_reg_8756_pp0_iter13_reg; + data_58_V_read_3_reg_8756_pp0_iter15_reg <= data_58_V_read_3_reg_8756_pp0_iter14_reg; + data_58_V_read_3_reg_8756_pp0_iter1_reg <= data_58_V_read_3_reg_8756; + data_58_V_read_3_reg_8756_pp0_iter2_reg <= data_58_V_read_3_reg_8756_pp0_iter1_reg; + data_58_V_read_3_reg_8756_pp0_iter3_reg <= data_58_V_read_3_reg_8756_pp0_iter2_reg; + data_58_V_read_3_reg_8756_pp0_iter4_reg <= data_58_V_read_3_reg_8756_pp0_iter3_reg; + data_58_V_read_3_reg_8756_pp0_iter5_reg <= data_58_V_read_3_reg_8756_pp0_iter4_reg; + data_58_V_read_3_reg_8756_pp0_iter6_reg <= data_58_V_read_3_reg_8756_pp0_iter5_reg; + data_58_V_read_3_reg_8756_pp0_iter7_reg <= data_58_V_read_3_reg_8756_pp0_iter6_reg; + data_58_V_read_3_reg_8756_pp0_iter8_reg <= data_58_V_read_3_reg_8756_pp0_iter7_reg; + data_58_V_read_3_reg_8756_pp0_iter9_reg <= data_58_V_read_3_reg_8756_pp0_iter8_reg; + data_59_V_read_3_reg_8724 <= data_59_V_read_int_reg; + data_59_V_read_3_reg_8724_pp0_iter10_reg <= data_59_V_read_3_reg_8724_pp0_iter9_reg; + data_59_V_read_3_reg_8724_pp0_iter11_reg <= data_59_V_read_3_reg_8724_pp0_iter10_reg; + data_59_V_read_3_reg_8724_pp0_iter12_reg <= data_59_V_read_3_reg_8724_pp0_iter11_reg; + data_59_V_read_3_reg_8724_pp0_iter13_reg <= data_59_V_read_3_reg_8724_pp0_iter12_reg; + data_59_V_read_3_reg_8724_pp0_iter14_reg <= data_59_V_read_3_reg_8724_pp0_iter13_reg; + data_59_V_read_3_reg_8724_pp0_iter15_reg <= data_59_V_read_3_reg_8724_pp0_iter14_reg; + data_59_V_read_3_reg_8724_pp0_iter16_reg <= data_59_V_read_3_reg_8724_pp0_iter15_reg; + data_59_V_read_3_reg_8724_pp0_iter1_reg <= data_59_V_read_3_reg_8724; + data_59_V_read_3_reg_8724_pp0_iter2_reg <= data_59_V_read_3_reg_8724_pp0_iter1_reg; + data_59_V_read_3_reg_8724_pp0_iter3_reg <= data_59_V_read_3_reg_8724_pp0_iter2_reg; + data_59_V_read_3_reg_8724_pp0_iter4_reg <= data_59_V_read_3_reg_8724_pp0_iter3_reg; + data_59_V_read_3_reg_8724_pp0_iter5_reg <= data_59_V_read_3_reg_8724_pp0_iter4_reg; + data_59_V_read_3_reg_8724_pp0_iter6_reg <= data_59_V_read_3_reg_8724_pp0_iter5_reg; + data_59_V_read_3_reg_8724_pp0_iter7_reg <= data_59_V_read_3_reg_8724_pp0_iter6_reg; + data_59_V_read_3_reg_8724_pp0_iter8_reg <= data_59_V_read_3_reg_8724_pp0_iter7_reg; + data_59_V_read_3_reg_8724_pp0_iter9_reg <= data_59_V_read_3_reg_8724_pp0_iter8_reg; + data_5_V_read_9_reg_10245 <= data_5_V_read_int_reg; + data_5_V_read_9_reg_10245_pp0_iter1_reg <= data_5_V_read_9_reg_10245; + data_5_V_read_9_reg_10245_pp0_iter2_reg <= data_5_V_read_9_reg_10245_pp0_iter1_reg; + data_5_V_read_9_reg_10245_pp0_iter3_reg <= data_5_V_read_9_reg_10245_pp0_iter2_reg; + data_60_V_read61_reg_8691 <= data_60_V_read_int_reg; + data_60_V_read61_reg_8691_pp0_iter10_reg <= data_60_V_read61_reg_8691_pp0_iter9_reg; + data_60_V_read61_reg_8691_pp0_iter11_reg <= data_60_V_read61_reg_8691_pp0_iter10_reg; + data_60_V_read61_reg_8691_pp0_iter12_reg <= data_60_V_read61_reg_8691_pp0_iter11_reg; + data_60_V_read61_reg_8691_pp0_iter13_reg <= data_60_V_read61_reg_8691_pp0_iter12_reg; + data_60_V_read61_reg_8691_pp0_iter14_reg <= data_60_V_read61_reg_8691_pp0_iter13_reg; + data_60_V_read61_reg_8691_pp0_iter15_reg <= data_60_V_read61_reg_8691_pp0_iter14_reg; + data_60_V_read61_reg_8691_pp0_iter16_reg <= data_60_V_read61_reg_8691_pp0_iter15_reg; + data_60_V_read61_reg_8691_pp0_iter1_reg <= data_60_V_read61_reg_8691; + data_60_V_read61_reg_8691_pp0_iter2_reg <= data_60_V_read61_reg_8691_pp0_iter1_reg; + data_60_V_read61_reg_8691_pp0_iter3_reg <= data_60_V_read61_reg_8691_pp0_iter2_reg; + data_60_V_read61_reg_8691_pp0_iter4_reg <= data_60_V_read61_reg_8691_pp0_iter3_reg; + data_60_V_read61_reg_8691_pp0_iter5_reg <= data_60_V_read61_reg_8691_pp0_iter4_reg; + data_60_V_read61_reg_8691_pp0_iter6_reg <= data_60_V_read61_reg_8691_pp0_iter5_reg; + data_60_V_read61_reg_8691_pp0_iter7_reg <= data_60_V_read61_reg_8691_pp0_iter6_reg; + data_60_V_read61_reg_8691_pp0_iter8_reg <= data_60_V_read61_reg_8691_pp0_iter7_reg; + data_60_V_read61_reg_8691_pp0_iter9_reg <= data_60_V_read61_reg_8691_pp0_iter8_reg; + data_61_V_read62_reg_8663 <= data_61_V_read_int_reg; + data_61_V_read62_reg_8663_pp0_iter10_reg <= data_61_V_read62_reg_8663_pp0_iter9_reg; + data_61_V_read62_reg_8663_pp0_iter11_reg <= data_61_V_read62_reg_8663_pp0_iter10_reg; + data_61_V_read62_reg_8663_pp0_iter12_reg <= data_61_V_read62_reg_8663_pp0_iter11_reg; + data_61_V_read62_reg_8663_pp0_iter13_reg <= data_61_V_read62_reg_8663_pp0_iter12_reg; + data_61_V_read62_reg_8663_pp0_iter14_reg <= data_61_V_read62_reg_8663_pp0_iter13_reg; + data_61_V_read62_reg_8663_pp0_iter15_reg <= data_61_V_read62_reg_8663_pp0_iter14_reg; + data_61_V_read62_reg_8663_pp0_iter16_reg <= data_61_V_read62_reg_8663_pp0_iter15_reg; + data_61_V_read62_reg_8663_pp0_iter1_reg <= data_61_V_read62_reg_8663; + data_61_V_read62_reg_8663_pp0_iter2_reg <= data_61_V_read62_reg_8663_pp0_iter1_reg; + data_61_V_read62_reg_8663_pp0_iter3_reg <= data_61_V_read62_reg_8663_pp0_iter2_reg; + data_61_V_read62_reg_8663_pp0_iter4_reg <= data_61_V_read62_reg_8663_pp0_iter3_reg; + data_61_V_read62_reg_8663_pp0_iter5_reg <= data_61_V_read62_reg_8663_pp0_iter4_reg; + data_61_V_read62_reg_8663_pp0_iter6_reg <= data_61_V_read62_reg_8663_pp0_iter5_reg; + data_61_V_read62_reg_8663_pp0_iter7_reg <= data_61_V_read62_reg_8663_pp0_iter6_reg; + data_61_V_read62_reg_8663_pp0_iter8_reg <= data_61_V_read62_reg_8663_pp0_iter7_reg; + data_61_V_read62_reg_8663_pp0_iter9_reg <= data_61_V_read62_reg_8663_pp0_iter8_reg; + data_62_V_read_3_reg_8645 <= data_62_V_read_int_reg; + data_62_V_read_3_reg_8645_pp0_iter10_reg <= data_62_V_read_3_reg_8645_pp0_iter9_reg; + data_62_V_read_3_reg_8645_pp0_iter11_reg <= data_62_V_read_3_reg_8645_pp0_iter10_reg; + data_62_V_read_3_reg_8645_pp0_iter12_reg <= data_62_V_read_3_reg_8645_pp0_iter11_reg; + data_62_V_read_3_reg_8645_pp0_iter13_reg <= data_62_V_read_3_reg_8645_pp0_iter12_reg; + data_62_V_read_3_reg_8645_pp0_iter14_reg <= data_62_V_read_3_reg_8645_pp0_iter13_reg; + data_62_V_read_3_reg_8645_pp0_iter15_reg <= data_62_V_read_3_reg_8645_pp0_iter14_reg; + data_62_V_read_3_reg_8645_pp0_iter16_reg <= data_62_V_read_3_reg_8645_pp0_iter15_reg; + data_62_V_read_3_reg_8645_pp0_iter1_reg <= data_62_V_read_3_reg_8645; + data_62_V_read_3_reg_8645_pp0_iter2_reg <= data_62_V_read_3_reg_8645_pp0_iter1_reg; + data_62_V_read_3_reg_8645_pp0_iter3_reg <= data_62_V_read_3_reg_8645_pp0_iter2_reg; + data_62_V_read_3_reg_8645_pp0_iter4_reg <= data_62_V_read_3_reg_8645_pp0_iter3_reg; + data_62_V_read_3_reg_8645_pp0_iter5_reg <= data_62_V_read_3_reg_8645_pp0_iter4_reg; + data_62_V_read_3_reg_8645_pp0_iter6_reg <= data_62_V_read_3_reg_8645_pp0_iter5_reg; + data_62_V_read_3_reg_8645_pp0_iter7_reg <= data_62_V_read_3_reg_8645_pp0_iter6_reg; + data_62_V_read_3_reg_8645_pp0_iter8_reg <= data_62_V_read_3_reg_8645_pp0_iter7_reg; + data_62_V_read_3_reg_8645_pp0_iter9_reg <= data_62_V_read_3_reg_8645_pp0_iter8_reg; + data_63_V_read_3_reg_8620 <= data_63_V_read_int_reg; + data_63_V_read_3_reg_8620_pp0_iter10_reg <= data_63_V_read_3_reg_8620_pp0_iter9_reg; + data_63_V_read_3_reg_8620_pp0_iter11_reg <= data_63_V_read_3_reg_8620_pp0_iter10_reg; + data_63_V_read_3_reg_8620_pp0_iter12_reg <= data_63_V_read_3_reg_8620_pp0_iter11_reg; + data_63_V_read_3_reg_8620_pp0_iter13_reg <= data_63_V_read_3_reg_8620_pp0_iter12_reg; + data_63_V_read_3_reg_8620_pp0_iter14_reg <= data_63_V_read_3_reg_8620_pp0_iter13_reg; + data_63_V_read_3_reg_8620_pp0_iter15_reg <= data_63_V_read_3_reg_8620_pp0_iter14_reg; + data_63_V_read_3_reg_8620_pp0_iter16_reg <= data_63_V_read_3_reg_8620_pp0_iter15_reg; + data_63_V_read_3_reg_8620_pp0_iter1_reg <= data_63_V_read_3_reg_8620; + data_63_V_read_3_reg_8620_pp0_iter2_reg <= data_63_V_read_3_reg_8620_pp0_iter1_reg; + data_63_V_read_3_reg_8620_pp0_iter3_reg <= data_63_V_read_3_reg_8620_pp0_iter2_reg; + data_63_V_read_3_reg_8620_pp0_iter4_reg <= data_63_V_read_3_reg_8620_pp0_iter3_reg; + data_63_V_read_3_reg_8620_pp0_iter5_reg <= data_63_V_read_3_reg_8620_pp0_iter4_reg; + data_63_V_read_3_reg_8620_pp0_iter6_reg <= data_63_V_read_3_reg_8620_pp0_iter5_reg; + data_63_V_read_3_reg_8620_pp0_iter7_reg <= data_63_V_read_3_reg_8620_pp0_iter6_reg; + data_63_V_read_3_reg_8620_pp0_iter8_reg <= data_63_V_read_3_reg_8620_pp0_iter7_reg; + data_63_V_read_3_reg_8620_pp0_iter9_reg <= data_63_V_read_3_reg_8620_pp0_iter8_reg; + data_6_V_read_9_reg_10218 <= data_6_V_read_int_reg; + data_6_V_read_9_reg_10218_pp0_iter1_reg <= data_6_V_read_9_reg_10218; + data_6_V_read_9_reg_10218_pp0_iter2_reg <= data_6_V_read_9_reg_10218_pp0_iter1_reg; + data_6_V_read_9_reg_10218_pp0_iter3_reg <= data_6_V_read_9_reg_10218_pp0_iter2_reg; + data_7_V_read_9_reg_10191 <= data_7_V_read_int_reg; + data_7_V_read_9_reg_10191_pp0_iter1_reg <= data_7_V_read_9_reg_10191; + data_7_V_read_9_reg_10191_pp0_iter2_reg <= data_7_V_read_9_reg_10191_pp0_iter1_reg; + data_7_V_read_9_reg_10191_pp0_iter3_reg <= data_7_V_read_9_reg_10191_pp0_iter2_reg; + data_7_V_read_9_reg_10191_pp0_iter4_reg <= data_7_V_read_9_reg_10191_pp0_iter3_reg; + data_8_V_read_8_reg_10164 <= data_8_V_read_int_reg; + data_8_V_read_8_reg_10164_pp0_iter1_reg <= data_8_V_read_8_reg_10164; + data_8_V_read_8_reg_10164_pp0_iter2_reg <= data_8_V_read_8_reg_10164_pp0_iter1_reg; + data_8_V_read_8_reg_10164_pp0_iter3_reg <= data_8_V_read_8_reg_10164_pp0_iter2_reg; + data_8_V_read_8_reg_10164_pp0_iter4_reg <= data_8_V_read_8_reg_10164_pp0_iter3_reg; + data_9_V_read_8_reg_10136 <= data_9_V_read_int_reg; + data_9_V_read_8_reg_10136_pp0_iter1_reg <= data_9_V_read_8_reg_10136; + data_9_V_read_8_reg_10136_pp0_iter2_reg <= data_9_V_read_8_reg_10136_pp0_iter1_reg; + data_9_V_read_8_reg_10136_pp0_iter3_reg <= data_9_V_read_8_reg_10136_pp0_iter2_reg; + data_9_V_read_8_reg_10136_pp0_iter4_reg <= data_9_V_read_8_reg_10136_pp0_iter3_reg; + sub_ln703_106_reg_10707 <= sub_ln703_106_fu_1378_p2; + sub_ln703_107_reg_10712 <= sub_ln703_107_fu_1383_p2; + sub_ln703_108_reg_10717 <= sub_ln703_108_fu_1388_p2; + sub_ln703_109_reg_10722 <= sub_ln703_109_fu_1407_p2; + sub_ln703_10_reg_10420 <= sub_ln703_10_fu_615_p2; + sub_ln703_115_reg_10727 <= sub_ln703_115_fu_1432_p2; + sub_ln703_11_reg_10398 <= sub_ln703_11_fu_576_p2; + sub_ln703_11_reg_10398_pp0_iter3_reg <= sub_ln703_11_reg_10398; + sub_ln703_122_reg_10742 <= sub_ln703_122_fu_1462_p2; + sub_ln703_123_reg_10747 <= sub_ln703_123_fu_1467_p2; + sub_ln703_125_reg_10757 <= sub_ln703_125_fu_1482_p2; + sub_ln703_128_reg_10762 <= sub_ln703_128_fu_1496_p2; + sub_ln703_133_reg_10782 <= sub_ln703_133_fu_1532_p2; + sub_ln703_137_reg_10787 <= sub_ln703_137_fu_1548_p2; + sub_ln703_141_reg_10792 <= sub_ln703_141_fu_1553_p2; + sub_ln703_142_reg_10797 <= sub_ln703_142_fu_1558_p2; + sub_ln703_146_reg_10812 <= sub_ln703_146_fu_1580_p2; + sub_ln703_152_reg_10822 <= sub_ln703_152_fu_1599_p2; + sub_ln703_154_reg_10832 <= sub_ln703_154_fu_1609_p2; + sub_ln703_15_reg_10430 <= sub_ln703_15_fu_631_p2; + sub_ln703_166_reg_10863 <= sub_ln703_166_fu_1834_p2; + sub_ln703_16_reg_10436 <= sub_ln703_16_fu_640_p2; + sub_ln703_17_reg_10453 <= sub_ln703_17_fu_653_p2; + sub_ln703_183_reg_10868 <= sub_ln703_183_fu_1959_p2; + sub_ln703_184_reg_10878 <= sub_ln703_184_fu_1984_p2; + sub_ln703_186_reg_10883 <= sub_ln703_186_fu_1994_p2; + sub_ln703_18_reg_10459 <= sub_ln703_18_fu_658_p2; + sub_ln703_191_reg_10893 <= sub_ln703_191_fu_2029_p2; + sub_ln703_194_reg_10908 <= sub_ln703_194_fu_2054_p2; + sub_ln703_196_reg_10913 <= sub_ln703_196_fu_2074_p2; + sub_ln703_198_reg_10935 <= sub_ln703_198_fu_2099_p2; + sub_ln703_1_reg_10348 <= sub_ln703_1_fu_540_p2; + sub_ln703_200_reg_10950 <= sub_ln703_200_fu_2115_p2; + sub_ln703_202_reg_10955 <= sub_ln703_202_fu_2120_p2; + sub_ln703_203_reg_10965 <= sub_ln703_203_fu_2131_p2; + sub_ln703_204_reg_10975 <= sub_ln703_204_fu_2142_p2; + sub_ln703_208_reg_10985 <= sub_ln703_208_fu_2152_p2; + sub_ln703_209_reg_10990 <= sub_ln703_209_fu_2157_p2; + sub_ln703_20_reg_10465 <= sub_ln703_20_fu_662_p2; + sub_ln703_210_reg_10995 <= sub_ln703_210_fu_2162_p2; + sub_ln703_212_reg_11000 <= sub_ln703_212_fu_2173_p2; + sub_ln703_230_reg_11010 <= sub_ln703_230_fu_2194_p2; + sub_ln703_234_reg_11046 <= sub_ln703_234_fu_2395_p2; + sub_ln703_237_reg_11020 <= sub_ln703_237_fu_2214_p2; + sub_ln703_23_reg_10471 <= sub_ln703_23_fu_666_p2; + sub_ln703_246_reg_11051 <= sub_ln703_246_fu_2477_p2; + sub_ln703_249_reg_11056 <= sub_ln703_249_fu_2496_p2; + sub_ln703_250_reg_11061 <= sub_ln703_250_fu_2501_p2; + sub_ln703_251_reg_11066 <= sub_ln703_251_fu_2506_p2; + sub_ln703_254_reg_11076 <= sub_ln703_254_fu_2525_p2; + sub_ln703_256_reg_11081 <= sub_ln703_256_fu_2534_p2; + sub_ln703_257_reg_11086 <= sub_ln703_257_fu_2539_p2; + sub_ln703_261_reg_11091 <= sub_ln703_261_fu_2569_p2; + sub_ln703_262_reg_11096 <= sub_ln703_262_fu_2574_p2; + sub_ln703_263_reg_11101 <= sub_ln703_263_fu_2579_p2; + sub_ln703_265_reg_11116 <= sub_ln703_265_fu_2613_p2; + sub_ln703_270_reg_11121 <= sub_ln703_270_fu_2628_p2; + sub_ln703_272_reg_11138 <= sub_ln703_272_fu_2647_p2; + sub_ln703_274_reg_11143 <= sub_ln703_274_fu_2652_p2; + sub_ln703_275_reg_11153 <= sub_ln703_275_fu_2662_p2; + sub_ln703_281_reg_11163 <= sub_ln703_281_fu_2688_p2; + sub_ln703_284_reg_11168 <= sub_ln703_284_fu_2698_p2; + sub_ln703_289_reg_11173 <= sub_ln703_289_fu_2703_p2; + sub_ln703_28_reg_10476 <= sub_ln703_28_fu_671_p2; + sub_ln703_293_reg_11178 <= sub_ln703_293_fu_2708_p2; + sub_ln703_296_reg_11183 <= sub_ln703_296_fu_2713_p2; + sub_ln703_2_reg_10367 <= sub_ln703_2_fu_552_p2; + sub_ln703_301_reg_11188 <= sub_ln703_301_fu_2718_p2; + sub_ln703_313_reg_11257 <= sub_ln703_313_fu_2998_p2; + sub_ln703_315_reg_11267 <= sub_ln703_315_fu_3021_p2; + sub_ln703_326_reg_11277 <= sub_ln703_326_fu_3101_p2; + sub_ln703_328_reg_11282 <= sub_ln703_328_fu_3111_p2; + sub_ln703_333_reg_11292 <= sub_ln703_333_fu_3155_p2; + sub_ln703_334_reg_11302 <= sub_ln703_334_fu_3175_p2; + sub_ln703_336_reg_11307 <= sub_ln703_336_fu_3180_p2; + sub_ln703_339_reg_11317 <= sub_ln703_339_fu_3200_p2; + sub_ln703_340_reg_11322 <= sub_ln703_340_fu_3205_p2; + sub_ln703_342_reg_11327 <= sub_ln703_342_fu_3215_p2; + sub_ln703_344_reg_11332 <= sub_ln703_344_fu_3220_p2; + sub_ln703_345_reg_11337 <= sub_ln703_345_fu_3234_p2; + sub_ln703_350_reg_11342 <= sub_ln703_350_fu_3244_p2; + sub_ln703_353_reg_11352 <= sub_ln703_353_fu_3269_p2; + sub_ln703_356_reg_11367 <= sub_ln703_356_fu_3290_p2; + sub_ln703_358_reg_11372 <= sub_ln703_358_fu_3300_p2; + sub_ln703_362_reg_11377 <= sub_ln703_362_fu_3305_p2; + sub_ln703_371_reg_11397 <= sub_ln703_371_fu_3324_p2; + sub_ln703_384_reg_11474 <= sub_ln703_384_fu_3645_p2; + sub_ln703_386_reg_11484 <= sub_ln703_386_fu_3660_p2; + sub_ln703_387_reg_11489 <= sub_ln703_387_fu_3665_p2; + sub_ln703_38_reg_10508 <= sub_ln703_38_fu_814_p2; + sub_ln703_390_reg_11499 <= sub_ln703_390_fu_3690_p2; + sub_ln703_393_reg_11504 <= sub_ln703_393_fu_3705_p2; + sub_ln703_394_reg_11509 <= sub_ln703_394_fu_3710_p2; + sub_ln703_395_reg_11514 <= sub_ln703_395_fu_3720_p2; + sub_ln703_399_reg_11524 <= sub_ln703_399_fu_3761_p2; + sub_ln703_39_reg_10513 <= sub_ln703_39_fu_819_p2; + sub_ln703_3_reg_10379 <= sub_ln703_3_fu_560_p2; + sub_ln703_401_reg_11529 <= sub_ln703_401_fu_3781_p2; + sub_ln703_402_reg_11534 <= sub_ln703_402_fu_3786_p2; + sub_ln703_403_reg_11539 <= sub_ln703_403_fu_3791_p2; + sub_ln703_405_reg_11554 <= sub_ln703_405_fu_3816_p2; + sub_ln703_408_reg_11564 <= sub_ln703_408_fu_3845_p2; + sub_ln703_40_reg_10519 <= sub_ln703_40_fu_824_p2; + sub_ln703_411_reg_11569 <= sub_ln703_411_fu_3850_p2; + sub_ln703_412_reg_11574 <= sub_ln703_412_fu_3855_p2; + sub_ln703_414_reg_11579 <= sub_ln703_414_fu_3860_p2; + sub_ln703_416_reg_11584 <= sub_ln703_416_fu_3865_p2; + sub_ln703_419_reg_11594 <= sub_ln703_419_fu_3884_p2; + sub_ln703_43_reg_10524 <= sub_ln703_43_fu_838_p2; + sub_ln703_440_reg_11624 <= sub_ln703_440_fu_3938_p2; + sub_ln703_448_reg_11673 <= sub_ln703_448_fu_4206_p2; + sub_ln703_452_reg_11678 <= sub_ln703_452_fu_4231_p2; + sub_ln703_453_reg_11683 <= sub_ln703_453_fu_4236_p2; + sub_ln703_458_reg_11688 <= sub_ln703_458_fu_4270_p2; + sub_ln703_461_reg_11693 <= sub_ln703_461_fu_4303_p2; + sub_ln703_462_reg_11703 <= sub_ln703_462_fu_4313_p2; + sub_ln703_467_reg_11713 <= sub_ln703_467_fu_4333_p2; + sub_ln703_468_reg_11718 <= sub_ln703_468_fu_4353_p2; + sub_ln703_469_reg_11733 <= sub_ln703_469_fu_4368_p2; + sub_ln703_470_reg_11738 <= sub_ln703_470_fu_4373_p2; + sub_ln703_475_reg_11753 <= sub_ln703_475_fu_4418_p2; + sub_ln703_482_reg_11773 <= sub_ln703_482_fu_4447_p2; + sub_ln703_483_reg_11778 <= sub_ln703_483_fu_4452_p2; + sub_ln703_488_reg_11783 <= sub_ln703_488_fu_4457_p2; + sub_ln703_490_reg_11788 <= sub_ln703_490_fu_4462_p2; + sub_ln703_491_reg_11793 <= sub_ln703_491_fu_4467_p2; + sub_ln703_4_reg_10361 <= sub_ln703_4_fu_548_p2; + sub_ln703_4_reg_10361_pp0_iter2_reg <= sub_ln703_4_reg_10361; + sub_ln703_503_reg_11813 <= sub_ln703_503_fu_4516_p2; + sub_ln703_505_reg_11818 <= sub_ln703_505_fu_4521_p2; + sub_ln703_526_reg_11864 <= sub_ln703_526_fu_4860_p2; + sub_ln703_527_reg_11869 <= sub_ln703_527_fu_4865_p2; + sub_ln703_529_reg_11879 <= sub_ln703_529_fu_4880_p2; + sub_ln703_532_reg_11884 <= sub_ln703_532_fu_4894_p2; + sub_ln703_533_reg_11894 <= sub_ln703_533_fu_4904_p2; + sub_ln703_535_reg_11899 <= sub_ln703_535_fu_4919_p2; + sub_ln703_538_reg_11904 <= sub_ln703_538_fu_4934_p2; + sub_ln703_539_reg_11909 <= sub_ln703_539_fu_4939_p2; + sub_ln703_53_reg_10534 <= sub_ln703_53_fu_912_p2; + sub_ln703_540_reg_11914 <= sub_ln703_540_fu_4944_p2; + sub_ln703_541_reg_11919 <= sub_ln703_541_fu_4949_p2; + sub_ln703_542_reg_11924 <= sub_ln703_542_fu_4954_p2; + sub_ln703_544_reg_11934 <= sub_ln703_544_fu_4984_p2; + sub_ln703_551_reg_11949 <= sub_ln703_551_fu_5004_p2; + sub_ln703_556_reg_11964 <= sub_ln703_556_fu_5024_p2; + sub_ln703_557_reg_11969 <= sub_ln703_557_fu_5029_p2; + sub_ln703_558_reg_11974 <= sub_ln703_558_fu_5034_p2; + sub_ln703_573_reg_12007 <= sub_ln703_573_fu_5101_p2; + sub_ln703_582_reg_12012 <= sub_ln703_582_fu_5106_p2; + sub_ln703_583_reg_12017 <= sub_ln703_583_fu_5111_p2; + sub_ln703_586_reg_12061 <= sub_ln703_586_fu_5351_p2; + sub_ln703_589_reg_12066 <= sub_ln703_589_fu_5375_p2; + sub_ln703_58_reg_10545 <= sub_ln703_58_fu_922_p2; + sub_ln703_593_reg_12071 <= sub_ln703_593_fu_5410_p2; + sub_ln703_594_reg_12076 <= sub_ln703_594_fu_5415_p2; + sub_ln703_595_reg_12081 <= sub_ln703_595_fu_5420_p2; + sub_ln703_598_reg_12091 <= sub_ln703_598_fu_5454_p2; + sub_ln703_603_reg_12101 <= sub_ln703_603_fu_5491_p2; + sub_ln703_604_reg_12106 <= sub_ln703_604_fu_5496_p2; + sub_ln703_605_reg_12111 <= sub_ln703_605_fu_5501_p2; + sub_ln703_608_reg_12116 <= sub_ln703_608_fu_5511_p2; + sub_ln703_609_reg_12121 <= sub_ln703_609_fu_5516_p2; + sub_ln703_610_reg_12126 <= sub_ln703_610_fu_5521_p2; + sub_ln703_612_reg_12131 <= sub_ln703_612_fu_5526_p2; + sub_ln703_613_reg_12136 <= sub_ln703_613_fu_5531_p2; + sub_ln703_614_reg_12141 <= sub_ln703_614_fu_5536_p2; + sub_ln703_618_reg_12156 <= sub_ln703_618_fu_5566_p2; + sub_ln703_624_reg_12166 <= sub_ln703_624_fu_5596_p2; + sub_ln703_62_reg_10550 <= sub_ln703_62_fu_942_p2; + sub_ln703_630_reg_12171 <= sub_ln703_630_fu_5627_p2; + sub_ln703_631_reg_12176 <= sub_ln703_631_fu_5632_p2; + sub_ln703_634_reg_12181 <= sub_ln703_634_fu_5637_p2; + sub_ln703_637_reg_12186 <= sub_ln703_637_fu_5642_p2; + sub_ln703_638_reg_12191 <= sub_ln703_638_fu_5647_p2; + sub_ln703_63_reg_10555 <= sub_ln703_63_fu_947_p2; + sub_ln703_644_reg_12204 <= sub_ln703_644_fu_5656_p2; + sub_ln703_648_reg_12209 <= sub_ln703_648_fu_5661_p2; + sub_ln703_64_reg_10560 <= sub_ln703_64_fu_957_p2; + sub_ln703_650_reg_12214 <= sub_ln703_650_fu_5666_p2; + sub_ln703_662_reg_12248 <= sub_ln703_662_fu_5918_p2; + sub_ln703_665_reg_12253 <= sub_ln703_665_fu_5932_p2; + sub_ln703_667_reg_12263 <= sub_ln703_667_fu_5956_p2; + sub_ln703_669_reg_12268 <= sub_ln703_669_fu_5975_p2; + sub_ln703_66_reg_10581 <= sub_ln703_66_fu_987_p2; + sub_ln703_676_reg_12278 <= sub_ln703_676_fu_6033_p2; + sub_ln703_678_reg_12283 <= sub_ln703_678_fu_6052_p2; + sub_ln703_679_reg_12288 <= sub_ln703_679_fu_6057_p2; + sub_ln703_680_reg_12293 <= sub_ln703_680_fu_6062_p2; + sub_ln703_682_reg_12298 <= sub_ln703_682_fu_6067_p2; + sub_ln703_684_reg_12303 <= sub_ln703_684_fu_6072_p2; + sub_ln703_686_reg_12308 <= sub_ln703_686_fu_6077_p2; + sub_ln703_687_reg_12313 <= sub_ln703_687_fu_6086_p2; + sub_ln703_688_reg_12318 <= sub_ln703_688_fu_6091_p2; + sub_ln703_690_reg_12323 <= sub_ln703_690_fu_6101_p2; + sub_ln703_691_reg_12328 <= sub_ln703_691_fu_6106_p2; + sub_ln703_692_reg_12333 <= sub_ln703_692_fu_6111_p2; + sub_ln703_693_reg_12338 <= sub_ln703_693_fu_6116_p2; + sub_ln703_694_reg_12343 <= sub_ln703_694_fu_6126_p2; + sub_ln703_696_reg_12353 <= sub_ln703_696_fu_6136_p2; + sub_ln703_697_reg_12358 <= sub_ln703_697_fu_6141_p2; + sub_ln703_6_reg_10408 <= sub_ln703_6_fu_595_p2; + sub_ln703_700_reg_12378 <= sub_ln703_700_fu_6172_p2; + sub_ln703_704_reg_12383 <= sub_ln703_704_fu_6177_p2; + sub_ln703_707_reg_12388 <= sub_ln703_707_fu_6182_p2; + sub_ln703_70_reg_10586 <= sub_ln703_70_fu_992_p2; + sub_ln703_71_reg_10596 <= sub_ln703_71_fu_1002_p2; + sub_ln703_724_reg_12450 <= sub_ln703_724_fu_6432_p2; + sub_ln703_727_reg_12460 <= sub_ln703_727_fu_6452_p2; + sub_ln703_728_reg_12465 <= sub_ln703_728_fu_6457_p2; + sub_ln703_733_reg_12470 <= sub_ln703_733_fu_6487_p2; + sub_ln703_736_reg_12475 <= sub_ln703_736_fu_6502_p2; + sub_ln703_73_reg_10611 <= sub_ln703_73_fu_1026_p2; + sub_ln703_746_reg_12500 <= sub_ln703_746_fu_6579_p2; + sub_ln703_749_reg_12510 <= sub_ln703_749_fu_6599_p2; + sub_ln703_757_reg_12515 <= sub_ln703_757_fu_6629_p2; + sub_ln703_759_reg_12525 <= sub_ln703_759_fu_6639_p2; + sub_ln703_75_reg_10616 <= sub_ln703_75_fu_1031_p2; + sub_ln703_761_reg_12530 <= sub_ln703_761_fu_6644_p2; + sub_ln703_763_reg_12540 <= sub_ln703_763_fu_6654_p2; + sub_ln703_767_reg_12545 <= sub_ln703_767_fu_6659_p2; + sub_ln703_769_reg_12555 <= sub_ln703_769_fu_6684_p2; + sub_ln703_770_reg_12570 <= sub_ln703_770_fu_6708_p2; + sub_ln703_781_reg_12580 <= sub_ln703_781_fu_6739_p2; + sub_ln703_787_reg_12590 <= sub_ln703_787_fu_6759_p2; + sub_ln703_797_reg_12645 <= sub_ln703_797_fu_7030_p2; + sub_ln703_799_reg_12595 <= sub_ln703_799_fu_6764_p2; + sub_ln703_801_reg_12660 <= sub_ln703_801_fu_7060_p2; + sub_ln703_802_reg_12665 <= sub_ln703_802_fu_7065_p2; + sub_ln703_805_reg_12670 <= sub_ln703_805_fu_7079_p2; + sub_ln703_807_reg_12685 <= sub_ln703_807_fu_7099_p2; + sub_ln703_808_reg_12700 <= sub_ln703_808_fu_7137_p2; + sub_ln703_814_reg_12735 <= sub_ln703_814_fu_7200_p2; + sub_ln703_816_reg_12740 <= sub_ln703_816_fu_7205_p2; + sub_ln703_818_reg_12745 <= sub_ln703_818_fu_7210_p2; + sub_ln703_820_reg_12750 <= sub_ln703_820_fu_7215_p2; + sub_ln703_821_reg_12755 <= sub_ln703_821_fu_7220_p2; + sub_ln703_823_reg_12760 <= sub_ln703_823_fu_7225_p2; + sub_ln703_824_reg_12765 <= sub_ln703_824_fu_7230_p2; + sub_ln703_825_reg_12770 <= sub_ln703_825_fu_7235_p2; + sub_ln703_852_reg_12790 <= sub_ln703_852_fu_7319_p2; + sub_ln703_857_reg_12835 <= sub_ln703_857_fu_7600_p2; + sub_ln703_858_reg_12840 <= sub_ln703_858_fu_7605_p2; + sub_ln703_859_reg_12850 <= sub_ln703_859_fu_7615_p2; + sub_ln703_862_reg_12795 <= sub_ln703_862_fu_7324_p2; + sub_ln703_863_reg_12860 <= sub_ln703_863_fu_7639_p2; + sub_ln703_865_reg_12865 <= sub_ln703_865_fu_7649_p2; + sub_ln703_866_reg_12870 <= sub_ln703_866_fu_7654_p2; + sub_ln703_867_reg_12880 <= sub_ln703_867_fu_7669_p2; + sub_ln703_868_reg_12885 <= sub_ln703_868_fu_7674_p2; + sub_ln703_869_reg_12800 <= sub_ln703_869_fu_7329_p2; + sub_ln703_869_reg_12800_pp0_iter16_reg <= sub_ln703_869_reg_12800; + sub_ln703_870_reg_12895 <= sub_ln703_870_fu_7685_p2; + sub_ln703_873_reg_12900 <= sub_ln703_873_fu_7710_p2; + sub_ln703_875_reg_12910 <= sub_ln703_875_fu_7730_p2; + sub_ln703_879_reg_12915 <= sub_ln703_879_fu_7735_p2; + sub_ln703_880_reg_12920 <= sub_ln703_880_fu_7750_p2; + sub_ln703_881_reg_12925 <= sub_ln703_881_fu_7755_p2; + sub_ln703_892_reg_12935 <= sub_ln703_892_fu_7780_p2; + sub_ln703_893_reg_12940 <= sub_ln703_893_fu_7785_p2; + sub_ln703_894_reg_12945 <= sub_ln703_894_fu_7790_p2; + sub_ln703_895_reg_12950 <= sub_ln703_895_fu_7795_p2; + sub_ln703_898_reg_12955 <= sub_ln703_898_fu_7805_p2; + sub_ln703_8_reg_10392 <= sub_ln703_8_fu_572_p2; + sub_ln703_904_reg_12960 <= sub_ln703_904_fu_7810_p2; + sub_ln703_911_reg_12970 <= sub_ln703_911_fu_7833_p2; + sub_ln703_917_reg_12975 <= sub_ln703_917_fu_7838_p2; + sub_ln703_922_reg_12980 <= sub_ln703_922_fu_7843_p2; + sub_ln703_92_reg_10636 <= sub_ln703_92_fu_1054_p2; + sub_ln703_96_reg_10677 <= sub_ln703_96_fu_1294_p2; + sub_ln703_98_reg_10697 <= sub_ln703_98_fu_1319_p2; + sub_ln703_reg_10342 <= sub_ln703_fu_536_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce_reg)) begin + ap_return_0_int_reg <= add_ln703_986_fu_8255_p2; + ap_return_10_int_reg <= acc_10_V_fu_8310_p2; + ap_return_11_int_reg <= acc_11_V_fu_8315_p2; + ap_return_12_int_reg <= acc_12_V_fu_8320_p2; + ap_return_13_int_reg <= acc_13_V_fu_8330_p2; + ap_return_14_int_reg <= acc_14_V_fu_8335_p2; + ap_return_15_int_reg <= acc_15_V_fu_8340_p2; + ap_return_16_int_reg <= acc_16_V_fu_8345_p2; + ap_return_17_int_reg <= acc_17_V_fu_8350_p2; + ap_return_18_int_reg <= acc_18_V_fu_8355_p2; + ap_return_19_int_reg <= acc_19_V_fu_8360_p2; + ap_return_1_int_reg <= acc_1_V_fu_8265_p2; + ap_return_20_int_reg <= acc_20_V_fu_8365_p2; + ap_return_21_int_reg <= acc_21_V_reg_12991; + ap_return_22_int_reg <= acc_22_V_fu_8370_p2; + ap_return_23_int_reg <= acc_23_V_fu_8375_p2; + ap_return_24_int_reg <= acc_24_V_fu_8380_p2; + ap_return_25_int_reg <= acc_25_V_fu_8385_p2; + ap_return_26_int_reg <= acc_26_V_fu_8390_p2; + ap_return_27_int_reg <= acc_27_V_fu_8400_p2; + ap_return_28_int_reg <= acc_28_V_fu_8405_p2; + ap_return_29_int_reg <= acc_29_V_fu_8414_p2; + ap_return_2_int_reg <= acc_2_V_fu_8270_p2; + ap_return_30_int_reg <= acc_30_V_fu_8419_p2; + ap_return_31_int_reg <= acc_31_V_fu_8424_p2; + ap_return_3_int_reg <= acc_3_V_fu_8275_p2; + ap_return_4_int_reg <= acc_4_V_fu_8280_p2; + ap_return_5_int_reg <= acc_5_V_fu_8285_p2; + ap_return_6_int_reg <= acc_6_V_fu_8290_p2; + ap_return_7_int_reg <= acc_7_V_fu_8295_p2; + ap_return_8_int_reg <= acc_8_V_fu_8300_p2; + ap_return_9_int_reg <= acc_9_V_fu_8305_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce)) begin + data_0_V_read_int_reg <= data_0_V_read; + data_10_V_read_int_reg <= data_10_V_read; + data_11_V_read_int_reg <= data_11_V_read; + data_12_V_read_int_reg <= data_12_V_read; + data_13_V_read_int_reg <= data_13_V_read; + data_14_V_read_int_reg <= data_14_V_read; + data_15_V_read_int_reg <= data_15_V_read; + data_16_V_read_int_reg <= data_16_V_read; + data_17_V_read_int_reg <= data_17_V_read; + data_18_V_read_int_reg <= data_18_V_read; + data_19_V_read_int_reg <= data_19_V_read; + data_1_V_read_int_reg <= data_1_V_read; + data_20_V_read_int_reg <= data_20_V_read; + data_21_V_read_int_reg <= data_21_V_read; + data_22_V_read_int_reg <= data_22_V_read; + data_23_V_read_int_reg <= data_23_V_read; + data_24_V_read_int_reg <= data_24_V_read; + data_25_V_read_int_reg <= data_25_V_read; + data_26_V_read_int_reg <= data_26_V_read; + data_27_V_read_int_reg <= data_27_V_read; + data_28_V_read_int_reg <= data_28_V_read; + data_29_V_read_int_reg <= data_29_V_read; + data_2_V_read_int_reg <= data_2_V_read; + data_30_V_read_int_reg <= data_30_V_read; + data_31_V_read_int_reg <= data_31_V_read; + data_32_V_read_int_reg <= data_32_V_read; + data_33_V_read_int_reg <= data_33_V_read; + data_34_V_read_int_reg <= data_34_V_read; + data_35_V_read_int_reg <= data_35_V_read; + data_36_V_read_int_reg <= data_36_V_read; + data_37_V_read_int_reg <= data_37_V_read; + data_38_V_read_int_reg <= data_38_V_read; + data_39_V_read_int_reg <= data_39_V_read; + data_3_V_read_int_reg <= data_3_V_read; + data_40_V_read_int_reg <= data_40_V_read; + data_41_V_read_int_reg <= data_41_V_read; + data_42_V_read_int_reg <= data_42_V_read; + data_43_V_read_int_reg <= data_43_V_read; + data_44_V_read_int_reg <= data_44_V_read; + data_45_V_read_int_reg <= data_45_V_read; + data_46_V_read_int_reg <= data_46_V_read; + data_47_V_read_int_reg <= data_47_V_read; + data_48_V_read_int_reg <= data_48_V_read; + data_49_V_read_int_reg <= data_49_V_read; + data_4_V_read_int_reg <= data_4_V_read; + data_50_V_read_int_reg <= data_50_V_read; + data_51_V_read_int_reg <= data_51_V_read; + data_52_V_read_int_reg <= data_52_V_read; + data_53_V_read_int_reg <= data_53_V_read; + data_54_V_read_int_reg <= data_54_V_read; + data_55_V_read_int_reg <= data_55_V_read; + data_56_V_read_int_reg <= data_56_V_read; + data_57_V_read_int_reg <= data_57_V_read; + data_58_V_read_int_reg <= data_58_V_read; + data_59_V_read_int_reg <= data_59_V_read; + data_5_V_read_int_reg <= data_5_V_read; + data_60_V_read_int_reg <= data_60_V_read; + data_61_V_read_int_reg <= data_61_V_read; + data_62_V_read_int_reg <= data_62_V_read; + data_63_V_read_int_reg <= data_63_V_read; + data_6_V_read_int_reg <= data_6_V_read; + data_7_V_read_int_reg <= data_7_V_read; + data_8_V_read_int_reg <= data_8_V_read; + data_9_V_read_int_reg <= data_9_V_read; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_0 = ap_return_0_int_reg; + end else begin + ap_return_0 = add_ln703_986_fu_8255_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_1 = ap_return_1_int_reg; + end else begin + ap_return_1 = acc_1_V_fu_8265_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_10 = ap_return_10_int_reg; + end else begin + ap_return_10 = acc_10_V_fu_8310_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_11 = ap_return_11_int_reg; + end else begin + ap_return_11 = acc_11_V_fu_8315_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_12 = ap_return_12_int_reg; + end else begin + ap_return_12 = acc_12_V_fu_8320_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_13 = ap_return_13_int_reg; + end else begin + ap_return_13 = acc_13_V_fu_8330_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_14 = ap_return_14_int_reg; + end else begin + ap_return_14 = acc_14_V_fu_8335_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_15 = ap_return_15_int_reg; + end else begin + ap_return_15 = acc_15_V_fu_8340_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_16 = ap_return_16_int_reg; + end else begin + ap_return_16 = acc_16_V_fu_8345_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_17 = ap_return_17_int_reg; + end else begin + ap_return_17 = acc_17_V_fu_8350_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_18 = ap_return_18_int_reg; + end else begin + ap_return_18 = acc_18_V_fu_8355_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_19 = ap_return_19_int_reg; + end else begin + ap_return_19 = acc_19_V_fu_8360_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_2 = ap_return_2_int_reg; + end else begin + ap_return_2 = acc_2_V_fu_8270_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_20 = ap_return_20_int_reg; + end else begin + ap_return_20 = acc_20_V_fu_8365_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_21 = ap_return_21_int_reg; + end else begin + ap_return_21 = acc_21_V_reg_12991; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_22 = ap_return_22_int_reg; + end else begin + ap_return_22 = acc_22_V_fu_8370_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_23 = ap_return_23_int_reg; + end else begin + ap_return_23 = acc_23_V_fu_8375_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_24 = ap_return_24_int_reg; + end else begin + ap_return_24 = acc_24_V_fu_8380_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_25 = ap_return_25_int_reg; + end else begin + ap_return_25 = acc_25_V_fu_8385_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_26 = ap_return_26_int_reg; + end else begin + ap_return_26 = acc_26_V_fu_8390_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_27 = ap_return_27_int_reg; + end else begin + ap_return_27 = acc_27_V_fu_8400_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_28 = ap_return_28_int_reg; + end else begin + ap_return_28 = acc_28_V_fu_8405_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_29 = ap_return_29_int_reg; + end else begin + ap_return_29 = acc_29_V_fu_8414_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_3 = ap_return_3_int_reg; + end else begin + ap_return_3 = acc_3_V_fu_8275_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_30 = ap_return_30_int_reg; + end else begin + ap_return_30 = acc_30_V_fu_8419_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_31 = ap_return_31_int_reg; + end else begin + ap_return_31 = acc_31_V_fu_8424_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_4 = ap_return_4_int_reg; + end else begin + ap_return_4 = acc_4_V_fu_8280_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_5 = ap_return_5_int_reg; + end else begin + ap_return_5 = acc_5_V_fu_8285_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_6 = ap_return_6_int_reg; + end else begin + ap_return_6 = acc_6_V_fu_8290_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_7 = ap_return_7_int_reg; + end else begin + ap_return_7 = acc_7_V_fu_8295_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_8 = ap_return_8_int_reg; + end else begin + ap_return_8 = acc_8_V_fu_8300_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_9 = ap_return_9_int_reg; + end else begin + ap_return_9 = acc_9_V_fu_8305_p2; + end +end + +assign acc_10_V_fu_8310_p2 = (add_ln703_974_fu_8159_p2 - data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_11_V_fu_8315_p2 = (sub_ln703_934_fu_8165_p2 - data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_12_V_fu_8320_p2 = (add_ln703_976_fu_8175_p2 - data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_13_V_fu_8330_p2 = (add_ln703_985_reg_12819_pp0_iter16_reg + add_ln703_994_fu_8325_p2); + +assign acc_14_V_fu_8335_p2 = (sub_ln703_935_fu_8181_p2 + data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_15_V_fu_8340_p2 = (add_ln703_978_fu_8191_p2 - data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_16_V_fu_8345_p2 = (add_ln703_979_fu_8197_p2 - data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_17_V_fu_8350_p2 = (add_ln703_985_reg_12819_pp0_iter16_reg + sub_ln703_924_fu_8072_p2); + +assign acc_18_V_fu_8355_p2 = (add_ln703_985_reg_12819_pp0_iter16_reg + sub_ln703_925_fu_8076_p2); + +assign acc_19_V_fu_8360_p2 = (add_ln703_985_reg_12819_pp0_iter16_reg + sub_ln703_926_fu_8080_p2); + +assign acc_1_V_fu_8265_p2 = (add_ln703_985_reg_12819_pp0_iter16_reg + add_ln703_987_fu_8260_p2); + +assign acc_20_V_fu_8365_p2 = (add_ln703_980_fu_8203_p2 - data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_21_V_fu_7872_p2 = (add_ln703_1003_fu_7867_p2 + add_ln703_1001_fu_7857_p2); + +assign acc_22_V_fu_8370_p2 = (add_ln703_985_reg_12819_pp0_iter16_reg + sub_ln703_927_fu_8085_p2); + +assign acc_23_V_fu_8375_p2 = (sub_ln703_936_fu_8209_p2 + data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_24_V_fu_8380_p2 = (add_ln703_981_fu_8214_p2 - data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_25_V_fu_8385_p2 = (sub_ln703_937_fu_8219_p2 - data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_26_V_fu_8390_p2 = (sub_ln703_938_fu_8224_p2 - data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_27_V_fu_8400_p2 = (add_ln703_985_reg_12819_pp0_iter16_reg + add_ln703_1007_fu_8395_p2); + +assign acc_28_V_fu_8405_p2 = (sub_ln703_939_fu_8229_p2 - data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_29_V_fu_8414_p2 = (add_ln703_985_reg_12819_pp0_iter16_reg + add_ln703_1009_fu_8410_p2); + +assign acc_2_V_fu_8270_p2 = (add_ln703_985_reg_12819_pp0_iter16_reg + sub_ln703_919_fu_8037_p2); + +assign acc_30_V_fu_8419_p2 = (sub_ln703_940_fu_8234_p2 - data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_31_V_fu_8424_p2 = (add_ln703_983_fu_8244_p2 - data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_3_V_fu_8275_p2 = (add_ln703_985_reg_12819_pp0_iter16_reg + sub_ln703_920_fu_8042_p2); + +assign acc_4_V_fu_8280_p2 = (sub_ln703_930_fu_8120_p2 + data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_5_V_fu_8285_p2 = (add_ln703_971_fu_8129_p2 - data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_6_V_fu_8290_p2 = (sub_ln703_931_fu_8134_p2 - data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_7_V_fu_8295_p2 = (sub_ln703_932_fu_8139_p2 + data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_8_V_fu_8300_p2 = (sub_ln703_933_fu_8143_p2 + data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign acc_9_V_fu_8305_p2 = (add_ln703_973_fu_8153_p2 - data_63_V_read_3_reg_8620_pp0_iter16_reg); + +assign add_ln703_1000_fu_7852_p2 = (sub_ln703_819_fu_7386_p2 + data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign add_ln703_1001_fu_7857_p2 = (add_ln703_937_fu_7659_p2 + add_ln703_1000_fu_7852_p2); + +assign add_ln703_1002_fu_7863_p2 = (add_ln703_985_reg_12819 + data_61_V_read62_reg_8663_pp0_iter15_reg); + +assign add_ln703_1003_fu_7867_p2 = (add_ln703_1002_fu_7863_p2 + add_ln703_954_reg_12812); + +assign add_ln703_1007_fu_8395_p2 = (sub_ln703_916_fu_8028_p2 + data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign add_ln703_1009_fu_8410_p2 = (sub_ln703_917_reg_12975 + data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign add_ln703_130_fu_556_p2 = (sub_ln703_1_reg_10348 + data_2_V_read_10_reg_10312_pp0_iter1_reg); + +assign add_ln703_131_fu_544_p2 = (add_ln703_reg_10335 + data_2_V_read_10_reg_10312); + +assign add_ln703_132_fu_599_p2 = (add_ln703_130_reg_10373 + data_3_V_read_10_reg_10295_pp0_iter2_reg); + +assign add_ln703_133_fu_603_p2 = (sub_ln703_3_reg_10379 + data_3_V_read_10_reg_10295_pp0_iter2_reg); + +assign add_ln703_134_fu_568_p2 = (add_ln703_131_reg_10354 + data_3_V_read_10_reg_10295_pp0_iter1_reg); + +assign add_ln703_135_fu_619_p2 = (sub_ln703_2_reg_10367 + data_3_V_read_10_reg_10295_pp0_iter2_reg); + +assign add_ln703_136_fu_623_p2 = (sub_ln703_4_reg_10361_pp0_iter2_reg + data_3_V_read_10_reg_10295_pp0_iter2_reg); + +assign add_ln703_137_fu_697_p2 = (sub_ln703_6_reg_10408 + data_4_V_read_10_reg_10273_pp0_iter3_reg); + +assign add_ln703_138_fu_701_p2 = (add_ln703_132_reg_10414 + data_4_V_read_10_reg_10273_pp0_iter3_reg); + +assign add_ln703_139_fu_636_p2 = (add_ln703_134_reg_10385 + data_4_V_read_10_reg_10273_pp0_iter2_reg); + +assign add_ln703_140_fu_644_p2 = (sub_ln703_7_fu_607_p2 + data_4_V_read_10_reg_10273_pp0_iter2_reg); + +assign add_ln703_141_fu_649_p2 = (sub_ln703_8_reg_10392 + data_4_V_read_10_reg_10273_pp0_iter2_reg); + +assign add_ln703_142_fu_581_p2 = (sub_ln703_reg_10342 + data_2_V_read_10_reg_10312_pp0_iter1_reg); + +assign add_ln703_143_fu_585_p2 = (data_3_V_read_10_reg_10295_pp0_iter1_reg + data_4_V_read_10_reg_10273_pp0_iter1_reg); + +assign add_ln703_144_fu_589_p2 = (add_ln703_143_fu_585_p2 + add_ln703_142_fu_581_p2); + +assign add_ln703_145_fu_736_p2 = (add_ln703_138_fu_701_p2 + data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign add_ln703_146_fu_741_p2 = (sub_ln703_15_reg_10430 + data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign add_ln703_147_fu_745_p2 = (sub_ln703_16_reg_10436 + data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign add_ln703_148_fu_757_p2 = (add_ln703_141_reg_10447 + data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign add_ln703_149_fu_773_p2 = (sub_ln703_19_fu_705_p2 + data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign add_ln703_150_fu_782_p2 = (sub_ln703_22_fu_713_p2 + data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign add_ln703_151_fu_791_p2 = (sub_ln703_20_reg_10465 + data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign add_ln703_152_fu_804_p2 = (sub_ln703_24_fu_717_p2 + data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign add_ln703_153_fu_809_p2 = (sub_ln703_25_fu_722_p2 + data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign add_ln703_154_fu_843_p2 = (sub_ln703_30_fu_753_p2 + data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign add_ln703_155_fu_868_p2 = (data_5_V_read_9_reg_10245_pp0_iter3_reg + data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign add_ln703_156_fu_872_p2 = (add_ln703_155_fu_868_p2 + sub_ln703_18_reg_10459); + +assign add_ln703_157_fu_892_p2 = (sub_ln703_35_fu_787_p2 + data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign add_ln703_158_fu_676_p2 = (sub_ln703_12_fu_627_p2 + data_4_V_read_10_reg_10273_pp0_iter2_reg); + +assign add_ln703_160_fu_902_p2 = (add_ln703_155_fu_868_p2 + add_ln703_158_reg_10482); + +assign add_ln703_161_fu_681_p2 = (data_6_V_read_9_reg_10218_pp0_iter2_reg + data_7_V_read_9_reg_10191_pp0_iter2_reg); + +assign add_ln703_162_fu_917_p2 = (add_ln703_161_reg_10487 + sub_ln703_26_fu_727_p2); + +assign add_ln703_163_fu_1098_p2 = (sub_ln703_39_reg_10513 + data_7_V_read_9_reg_10191_pp0_iter4_reg); + +assign add_ln703_164_fu_937_p2 = (sub_ln703_45_fu_853_p2 + data_7_V_read_9_reg_10191_pp0_iter3_reg); + +assign add_ln703_165_fu_952_p2 = (sub_ln703_38_fu_814_p2 + data_7_V_read_9_reg_10191_pp0_iter3_reg); + +assign add_ln703_166_fu_962_p2 = (sub_ln703_21_fu_709_p2 + data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign add_ln703_168_fu_967_p2 = (add_ln703_161_reg_10487 + add_ln703_166_fu_962_p2); + +assign add_ln703_170_fu_972_p2 = (add_ln703_161_reg_10487 + add_ln703_149_fu_773_p2); + +assign add_ln703_171_fu_977_p2 = (sub_ln703_51_fu_897_p2 + data_7_V_read_9_reg_10191_pp0_iter3_reg); + +assign add_ln703_173_fu_982_p2 = (add_ln703_161_reg_10487 + sub_ln703_36_fu_795_p2); + +assign add_ln703_174_fu_1114_p2 = (sub_ln703_54_fu_1086_p2 + data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign add_ln703_175_fu_1123_p2 = (sub_ln703_55_fu_1090_p2 + data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign add_ln703_176_fu_1128_p2 = (sub_ln703_56_fu_1094_p2 + data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign add_ln703_177_fu_997_p2 = (sub_ln703_61_fu_932_p2 + data_8_V_read_8_reg_10164_pp0_iter3_reg); + +assign add_ln703_178_fu_1007_p2 = (sub_ln703_17_reg_10453 + data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign add_ln703_179_fu_685_p2 = (data_7_V_read_9_reg_10191_pp0_iter2_reg + data_8_V_read_8_reg_10164_pp0_iter2_reg); + +assign add_ln703_180_fu_1011_p2 = (add_ln703_179_reg_10495 + data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign add_ln703_181_fu_1015_p2 = (add_ln703_180_fu_1011_p2 + add_ln703_178_fu_1007_p2); + +assign add_ln703_183_fu_1021_p2 = (add_ln703_179_reg_10495 + sub_ln703_47_fu_863_p2); + +assign add_ln703_184_fu_1143_p2 = (sub_ln703_62_reg_10550 + data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign add_ln703_186_fu_1036_p2 = (add_ln703_179_reg_10495 + sub_ln703_50_fu_887_p2); + +assign add_ln703_187_fu_1041_p2 = (sub_ln703_28_reg_10476 + data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign add_ln703_189_fu_1045_p2 = (add_ln703_179_reg_10495 + add_ln703_187_fu_1041_p2); + +assign add_ln703_190_fu_1172_p2 = (sub_ln703_64_reg_10560 + data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign add_ln703_191_fu_1176_p2 = (sub_ln703_66_reg_10581 + data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign add_ln703_192_fu_1050_p2 = (data_8_V_read_8_reg_10164_pp0_iter3_reg + data_9_V_read_8_reg_10136_pp0_iter3_reg); + +assign add_ln703_193_fu_1180_p2 = (add_ln703_192_reg_10626 + sub_ln703_53_reg_10534); + +assign add_ln703_194_fu_1189_p2 = (sub_ln703_67_fu_1119_p2 + data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign add_ln703_195_fu_1204_p2 = (sub_ln703_69_fu_1138_p2 + data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign add_ln703_197_fu_1209_p2 = (add_ln703_192_reg_10626 + sub_ln703_58_reg_10545); + +assign add_ln703_199_fu_1213_p2 = (add_ln703_192_reg_10626 + sub_ln703_59_fu_1106_p2); + +assign add_ln703_200_fu_1226_p2 = (sub_ln703_71_reg_10596 + data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign add_ln703_201_fu_1243_p2 = (sub_ln703_72_fu_1147_p2 + data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign add_ln703_202_fu_1265_p2 = (sub_ln703_77_fu_1159_p2 + data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign add_ln703_203_fu_1270_p2 = (sub_ln703_78_fu_1164_p2 + data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign add_ln703_204_fu_1059_p2 = (sub_ln703_52_fu_907_p2 + data_7_V_read_9_reg_10191_pp0_iter3_reg); + +assign add_ln703_206_fu_1290_p2 = (add_ln703_192_reg_10626 + add_ln703_204_reg_10641); + +assign add_ln703_207_fu_1299_p2 = (sub_ln703_80_fu_1184_p2 + data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign add_ln703_208_fu_1309_p2 = (sub_ln703_82_fu_1199_p2 + data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign add_ln703_209_fu_1064_p2 = (data_9_V_read_8_reg_10136_pp0_iter3_reg + data_10_V_read11_reg_10105_pp0_iter3_reg); + +assign add_ln703_210_fu_1314_p2 = (add_ln703_209_reg_10646 + sub_ln703_68_fu_1133_p2); + +assign add_ln703_211_fu_1339_p2 = (sub_ln703_84_fu_1222_p2 + data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign add_ln703_213_fu_1068_p2 = (sub_ln703_46_fu_858_p2 + data_10_V_read11_reg_10105_pp0_iter3_reg); + +assign add_ln703_214_fu_1349_p2 = (add_ln703_213_reg_10653 + data_7_V_read_9_reg_10191_pp0_iter4_reg); + +assign add_ln703_215_fu_1353_p2 = (add_ln703_214_fu_1349_p2 + add_ln703_192_reg_10626); + +assign add_ln703_216_fu_1358_p2 = (sub_ln703_85_fu_1230_p2 + data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign add_ln703_217_fu_1393_p2 = (add_ln703_162_reg_10539 + data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign add_ln703_219_fu_1397_p2 = (add_ln703_209_reg_10646 + add_ln703_217_fu_1393_p2); + +assign add_ln703_221_fu_1402_p2 = (add_ln703_209_reg_10646 + sub_ln703_76_fu_1155_p2); + +assign add_ln703_222_fu_1626_p2 = (sub_ln703_96_reg_10677 + data_11_V_read12_reg_10075_pp0_iter5_reg); + +assign add_ln703_223_fu_1073_p2 = (data_10_V_read11_reg_10105_pp0_iter3_reg + data_11_V_read12_reg_10075_pp0_iter3_reg); + +assign add_ln703_224_fu_1437_p2 = (add_ln703_223_reg_10658 + sub_ln703_81_fu_1194_p2); + +assign add_ln703_225_fu_1452_p2 = (sub_ln703_102_fu_1344_p2 + data_11_V_read12_reg_10075_pp0_iter4_reg); + +assign add_ln703_226_fu_1457_p2 = (add_ln703_215_fu_1353_p2 + data_11_V_read12_reg_10075_pp0_iter4_reg); + +assign add_ln703_227_fu_1472_p2 = (sub_ln703_104_fu_1368_p2 + data_11_V_read12_reg_10075_pp0_iter4_reg); + +assign add_ln703_228_fu_1477_p2 = (sub_ln703_105_fu_1373_p2 + data_11_V_read12_reg_10075_pp0_iter4_reg); + +assign add_ln703_229_fu_1654_p2 = (sub_ln703_107_reg_10712 + data_11_V_read12_reg_10075_pp0_iter5_reg); + +assign add_ln703_230_fu_1658_p2 = (sub_ln703_108_reg_10717 + data_11_V_read12_reg_10075_pp0_iter5_reg); + +assign add_ln703_232_fu_1492_p2 = (add_ln703_223_reg_10658 + sub_ln703_92_reg_10636); + +assign add_ln703_233_fu_1501_p2 = (sub_ln703_112_fu_1422_p2 + data_11_V_read12_reg_10075_pp0_iter4_reg); + +assign add_ln703_234_fu_1671_p2 = (sub_ln703_114_fu_1630_p2 + data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign add_ln703_235_fu_1676_p2 = (sub_ln703_115_reg_10727 + data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign add_ln703_236_fu_1511_p2 = (sub_ln703_119_fu_1442_p2 + data_12_V_read13_reg_10045_pp0_iter4_reg); + +assign add_ln703_237_fu_1516_p2 = (data_11_V_read12_reg_10075_pp0_iter4_reg + data_12_V_read13_reg_10045_pp0_iter4_reg); + +assign add_ln703_238_fu_1520_p2 = (add_ln703_237_fu_1516_p2 + sub_ln703_100_fu_1329_p2); + +assign add_ln703_240_fu_1526_p2 = (add_ln703_237_fu_1516_p2 + sub_ln703_101_fu_1334_p2); + +assign add_ln703_241_fu_1693_p2 = (sub_ln703_121_fu_1646_p2 + data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign add_ln703_242_fu_1537_p2 = (sub_ln703_86_fu_1234_p2 + data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign add_ln703_244_fu_1542_p2 = (add_ln703_237_fu_1516_p2 + add_ln703_242_fu_1537_p2); + +assign add_ln703_245_fu_1721_p2 = (sub_ln703_125_reg_10757 + data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign add_ln703_247_fu_1563_p2 = (add_ln703_237_fu_1516_p2 + sub_ln703_110_fu_1412_p2); + +assign add_ln703_248_fu_1569_p2 = (sub_ln703_95_fu_1285_p2 + data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign add_ln703_250_fu_1574_p2 = (add_ln703_237_fu_1516_p2 + add_ln703_248_fu_1569_p2); + +assign add_ln703_251_fu_1753_p2 = (sub_ln703_131_fu_1680_p2 + data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign add_ln703_252_fu_1077_p2 = (data_12_V_read13_reg_10045_pp0_iter3_reg + data_13_V_read14_reg_10015_pp0_iter3_reg); + +assign add_ln703_253_fu_1758_p2 = (add_ln703_252_reg_10665_pp0_iter5_reg + sub_ln703_117_fu_1638_p2); + +assign add_ln703_254_fu_1081_p2 = (sub_ln703_42_fu_833_p2 + data_7_V_read_9_reg_10191_pp0_iter3_reg); + +assign add_ln703_256_fu_1585_p2 = (add_ln703_192_reg_10626 + add_ln703_254_reg_10672); + +assign add_ln703_259_fu_1589_p2 = (add_ln703_252_reg_10665 + add_ln703_223_reg_10658); + +assign add_ln703_260_fu_1593_p2 = (add_ln703_259_fu_1589_p2 + add_ln703_256_fu_1585_p2); + +assign add_ln703_262_fu_1604_p2 = (add_ln703_252_reg_10665 + sub_ln703_120_fu_1447_p2); + +assign add_ln703_263_fu_1771_p2 = (sub_ln703_133_reg_10782 + data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign add_ln703_264_fu_1821_p2 = (sub_ln703_145_fu_1734_p2 + data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign add_ln703_265_fu_1614_p2 = (data_13_V_read14_reg_10015_pp0_iter4_reg + data_14_V_read15_reg_9987_pp0_iter4_reg); + +assign add_ln703_266_fu_1854_p2 = (add_ln703_265_reg_10837 + sub_ln703_132_fu_1684_p2); + +assign add_ln703_268_fu_1886_p2 = (add_ln703_265_reg_10837 + sub_ln703_134_fu_1689_p2); + +assign add_ln703_269_fu_1891_p2 = (sub_ln703_122_reg_10742 + data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign add_ln703_271_fu_1895_p2 = (add_ln703_265_reg_10837 + add_ln703_269_fu_1891_p2); + +assign add_ln703_273_fu_1914_p2 = (add_ln703_265_reg_10837 + sub_ln703_138_fu_1706_p2); + +assign add_ln703_274_fu_1924_p2 = (sub_ln703_161_fu_1809_p2 + data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign add_ln703_276_fu_1934_p2 = (add_ln703_265_reg_10837 + sub_ln703_143_fu_1725_p2); + +assign add_ln703_277_fu_1939_p2 = (sub_ln703_163_fu_1817_p2 + data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign add_ln703_278_fu_1954_p2 = (sub_ln703_165_fu_1830_p2 + data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign add_ln703_279_fu_1964_p2 = (sub_ln703_116_fu_1634_p2 + data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign add_ln703_280_fu_1618_p2 = (data_14_V_read15_reg_9987_pp0_iter4_reg + data_15_V_read16_reg_9962_pp0_iter4_reg); + +assign add_ln703_281_fu_1969_p2 = (add_ln703_280_reg_10846 + data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign add_ln703_282_fu_1973_p2 = (add_ln703_281_fu_1969_p2 + add_ln703_279_fu_1964_p2); + +assign add_ln703_283_fu_1979_p2 = (sub_ln703_169_fu_1849_p2 + data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign add_ln703_285_fu_2009_p2 = (add_ln703_280_reg_10846 + sub_ln703_153_fu_1775_p2); + +assign add_ln703_287_fu_2019_p2 = (add_ln703_280_reg_10846 + sub_ln703_155_fu_1780_p2); + +assign add_ln703_289_fu_2034_p2 = (add_ln703_280_reg_10846 + sub_ln703_158_fu_1794_p2); + +assign add_ln703_290_fu_2039_p2 = (sub_ln703_179_fu_1919_p2 + data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign add_ln703_291_fu_2064_p2 = (sub_ln703_144_fu_1730_p2 + data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign add_ln703_293_fu_2069_p2 = (add_ln703_280_reg_10846 + add_ln703_291_fu_2064_p2); + +assign add_ln703_294_fu_2084_p2 = (sub_ln703_147_fu_1738_p2 + data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign add_ln703_295_fu_2089_p2 = (data_15_V_read16_reg_9962_pp0_iter5_reg + data_16_V_read17_reg_9935_pp0_iter5_reg); + +assign add_ln703_296_fu_2238_p2 = (add_ln703_295_reg_10923 + add_ln703_294_reg_10918); + +assign add_ln703_298_fu_2242_p2 = (add_ln703_295_reg_10923 + sub_ln703_166_reg_10863); + +assign add_ln703_300_fu_2093_p2 = (add_ln703_295_fu_2089_p2 + sub_ln703_167_fu_1839_p2); + +assign add_ln703_301_fu_2250_p2 = (sub_ln703_184_reg_10878 + data_16_V_read17_reg_9935_pp0_iter6_reg); + +assign add_ln703_303_fu_2104_p2 = (add_ln703_295_fu_2089_p2 + sub_ln703_171_fu_1864_p2); + +assign add_ln703_304_fu_2110_p2 = (sub_ln703_185_fu_1989_p2 + data_16_V_read17_reg_9935_pp0_iter5_reg); + +assign add_ln703_305_fu_2254_p2 = (sub_ln703_186_reg_10883 + data_16_V_read17_reg_9935_pp0_iter6_reg); + +assign add_ln703_307_fu_2125_p2 = (add_ln703_295_fu_2089_p2 + sub_ln703_176_fu_1900_p2); + +assign add_ln703_309_fu_2136_p2 = (add_ln703_295_fu_2089_p2 + sub_ln703_177_fu_1904_p2); + +assign add_ln703_310_fu_2147_p2 = (sub_ln703_159_fu_1799_p2 + data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign add_ln703_312_fu_2270_p2 = (add_ln703_295_reg_10923 + add_ln703_310_reg_10980); + +assign add_ln703_314_fu_2167_p2 = (add_ln703_295_fu_2089_p2 + sub_ln703_182_fu_1949_p2); + +assign add_ln703_315_fu_2300_p2 = (sub_ln703_199_fu_2246_p2 + data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign add_ln703_316_fu_2178_p2 = (data_16_V_read17_reg_9935_pp0_iter5_reg + data_17_V_read18_reg_9904_pp0_iter5_reg); + +assign add_ln703_317_fu_2182_p2 = (add_ln703_316_fu_2178_p2 + sub_ln703_187_fu_1999_p2); + +assign add_ln703_318_fu_2323_p2 = (sub_ln703_201_fu_2258_p2 + data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign add_ln703_319_fu_2328_p2 = (sub_ln703_202_reg_10955 + data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign add_ln703_320_fu_2336_p2 = (sub_ln703_203_reg_10965 + data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign add_ln703_321_fu_2353_p2 = (sub_ln703_206_fu_2266_p2 + data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign add_ln703_323_fu_2188_p2 = (add_ln703_316_fu_2178_p2 + sub_ln703_193_fu_2049_p2); + +assign add_ln703_324_fu_2405_p2 = (sub_ln703_217_fu_2305_p2 + data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign add_ln703_325_fu_2199_p2 = (sub_ln703_170_fu_1859_p2 + data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign add_ln703_326_fu_1622_p2 = (data_17_V_read18_reg_9904_pp0_iter4_reg + data_18_V_read_8_reg_9874_pp0_iter4_reg); + +assign add_ln703_327_fu_2204_p2 = (add_ln703_326_reg_10855 + data_16_V_read17_reg_9935_pp0_iter5_reg); + +assign add_ln703_328_fu_2208_p2 = (add_ln703_327_fu_2204_p2 + add_ln703_325_fu_2199_p2); + +assign add_ln703_329_fu_2410_p2 = (sub_ln703_218_fu_2310_p2 + data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign add_ln703_330_fu_2219_p2 = (sub_ln703_175_fu_1881_p2 + data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign add_ln703_333_fu_2224_p2 = (add_ln703_327_fu_2204_p2 + add_ln703_330_fu_2219_p2); + +assign add_ln703_335_fu_2420_p2 = (add_ln703_326_reg_10855_pp0_iter6_reg + sub_ln703_200_reg_10950); + +assign add_ln703_336_fu_2449_p2 = (sub_ln703_224_fu_2348_p2 + data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign add_ln703_337_fu_2459_p2 = (sub_ln703_225_fu_2358_p2 + data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign add_ln703_339_fu_2464_p2 = (add_ln703_326_reg_10855_pp0_iter6_reg + sub_ln703_208_reg_10985); + +assign add_ln703_340_fu_2491_p2 = (sub_ln703_231_fu_2381_p2 + data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign add_ln703_341_fu_2230_p2 = (data_18_V_read_8_reg_9874_pp0_iter5_reg + data_19_V_read_8_reg_9845_pp0_iter5_reg); + +assign add_ln703_342_fu_2520_p2 = (add_ln703_341_reg_11030 + sub_ln703_219_fu_2314_p2); + +assign add_ln703_343_fu_2554_p2 = (sub_ln703_241_fu_2439_p2 + data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign add_ln703_345_fu_2564_p2 = (add_ln703_341_reg_11030 + sub_ln703_223_fu_2344_p2); + +assign add_ln703_346_fu_2589_p2 = (sub_ln703_244_fu_2468_p2 + data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign add_ln703_347_fu_2594_p2 = (sub_ln703_194_reg_10908 + data_16_V_read17_reg_9935_pp0_iter6_reg); + +assign add_ln703_349_fu_2598_p2 = (add_ln703_341_reg_11030 + data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign add_ln703_350_fu_2602_p2 = (add_ln703_349_fu_2598_p2 + add_ln703_347_fu_2594_p2); + +assign add_ln703_351_fu_2608_p2 = (sub_ln703_245_fu_2472_p2 + data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign add_ln703_352_fu_2633_p2 = (sub_ln703_253_fu_2515_p2 + data_20_V_read21_reg_9814_pp0_iter6_reg); + +assign add_ln703_353_fu_2795_p2 = (sub_ln703_254_reg_11076 + data_20_V_read21_reg_9814_pp0_iter7_reg); + +assign add_ln703_354_fu_2638_p2 = (data_19_V_read_8_reg_9845_pp0_iter6_reg + data_20_V_read21_reg_9814_pp0_iter6_reg); + +assign add_ln703_355_fu_2642_p2 = (add_ln703_354_fu_2638_p2 + sub_ln703_237_reg_11020); + +assign add_ln703_356_fu_2657_p2 = (sub_ln703_259_fu_2549_p2 + data_20_V_read21_reg_9814_pp0_iter6_reg); + +assign add_ln703_357_fu_2811_p2 = (sub_ln703_263_reg_11101 + data_20_V_read21_reg_9814_pp0_iter7_reg); + +assign add_ln703_358_fu_2672_p2 = (sub_ln703_226_fu_2363_p2 + data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign add_ln703_360_fu_2677_p2 = (add_ln703_354_fu_2638_p2 + add_ln703_358_fu_2672_p2); + +assign add_ln703_361_fu_2683_p2 = (sub_ln703_264_fu_2584_p2 + data_20_V_read21_reg_9814_pp0_iter6_reg); + +assign add_ln703_363_fu_2823_p2 = (add_ln703_354_reg_11131 + sub_ln703_246_reg_11051); + +assign add_ln703_364_fu_2831_p2 = (sub_ln703_268_fu_2783_p2 + data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign add_ln703_365_fu_2841_p2 = (sub_ln703_270_reg_11121 + data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign add_ln703_366_fu_2871_p2 = (sub_ln703_275_reg_11153 + data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign add_ln703_367_fu_2903_p2 = (sub_ln703_284_reg_11168 + data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign add_ln703_368_fu_2723_p2 = (sub_ln703_233_fu_2390_p2 + data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign add_ln703_369_fu_2234_p2 = (data_21_V_read22_reg_9784_pp0_iter5_reg + data_22_V_read23_reg_9756_pp0_iter5_reg); + +assign add_ln703_370_fu_2728_p2 = (add_ln703_369_reg_11037 + data_20_V_read21_reg_9814_pp0_iter6_reg); + +assign add_ln703_371_fu_2732_p2 = (add_ln703_370_fu_2728_p2 + add_ln703_368_fu_2723_p2); + +assign add_ln703_372_fu_2927_p2 = (sub_ln703_289_reg_11173 + data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign add_ln703_374_fu_2936_p2 = (add_ln703_369_reg_11037_pp0_iter7_reg + sub_ln703_273_fu_2799_p2); + +assign add_ln703_375_fu_2738_p2 = (sub_ln703_260_fu_2559_p2 + data_20_V_read21_reg_9814_pp0_iter6_reg); + +assign add_ln703_377_fu_2956_p2 = (add_ln703_369_reg_11037_pp0_iter7_reg + add_ln703_375_reg_11198); + +assign add_ln703_378_fu_2960_p2 = (sub_ln703_293_reg_11178 + data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign add_ln703_379_fu_2964_p2 = (sub_ln703_295_fu_2880_p2 + data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign add_ln703_380_fu_2969_p2 = (sub_ln703_296_reg_11183 + data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign add_ln703_381_fu_2973_p2 = (sub_ln703_297_fu_2884_p2 + data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign add_ln703_382_fu_2983_p2 = (sub_ln703_299_fu_2894_p2 + data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign add_ln703_383_fu_3007_p2 = (sub_ln703_250_reg_11061 + data_20_V_read21_reg_9814_pp0_iter7_reg); + +assign add_ln703_384_fu_2743_p2 = (data_22_V_read23_reg_9756_pp0_iter6_reg + data_23_V_read24_reg_9730_pp0_iter6_reg); + +assign add_ln703_385_fu_3011_p2 = (add_ln703_384_reg_11203 + data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign add_ln703_386_fu_3015_p2 = (add_ln703_385_fu_3011_p2 + add_ln703_383_fu_3007_p2); + +assign add_ln703_387_fu_3046_p2 = (sub_ln703_257_reg_11086 + data_20_V_read21_reg_9814_pp0_iter7_reg); + +assign add_ln703_390_fu_3050_p2 = (add_ln703_385_fu_3011_p2 + add_ln703_387_fu_3046_p2); + +assign add_ln703_391_fu_3061_p2 = (sub_ln703_308_fu_2946_p2 + data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign add_ln703_392_fu_3081_p2 = (sub_ln703_277_fu_2803_p2 + data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign add_ln703_394_fu_3086_p2 = (add_ln703_384_reg_11203 + add_ln703_392_fu_3081_p2); + +assign add_ln703_395_fu_3116_p2 = (sub_ln703_282_fu_2827_p2 + data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign add_ln703_397_fu_3121_p2 = (add_ln703_384_reg_11203 + add_ln703_395_fu_3116_p2); + +assign add_ln703_398_fu_2747_p2 = (sub_ln703_214_fu_2287_p2 + data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign add_ln703_400_fu_2752_p2 = (add_ln703_354_fu_2638_p2 + add_ln703_398_fu_2747_p2); + +assign add_ln703_402_fu_2758_p2 = (data_23_V_read24_reg_9730_pp0_iter6_reg + data_24_V_read25_reg_9704_pp0_iter6_reg); + +assign add_ln703_403_fu_3131_p2 = (add_ln703_402_reg_11215 + add_ln703_369_reg_11037_pp0_iter7_reg); + +assign add_ln703_404_fu_3135_p2 = (add_ln703_403_fu_3131_p2 + add_ln703_400_reg_11210); + +assign add_ln703_406_fu_3145_p2 = (add_ln703_354_reg_11131 + sub_ln703_234_reg_11046); + +assign add_ln703_410_fu_3149_p2 = (add_ln703_403_fu_3131_p2 + add_ln703_406_fu_3145_p2); + +assign add_ln703_411_fu_3380_p2 = (sub_ln703_315_reg_11267 + data_24_V_read25_reg_9704_pp0_iter8_reg); + +assign add_ln703_413_fu_3160_p2 = (add_ln703_402_reg_11215 + sub_ln703_305_fu_2922_p2); + +assign add_ln703_414_fu_3165_p2 = (sub_ln703_288_fu_2854_p2 + data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign add_ln703_416_fu_3170_p2 = (add_ln703_402_reg_11215 + add_ln703_414_fu_3165_p2); + +assign add_ln703_417_fu_3185_p2 = (sub_ln703_321_fu_3066_p2 + data_24_V_read25_reg_9704_pp0_iter7_reg); + +assign add_ln703_418_fu_3210_p2 = (sub_ln703_325_fu_3096_p2 + data_24_V_read25_reg_9704_pp0_iter7_reg); + +assign add_ln703_419_fu_3225_p2 = (sub_ln703_301_reg_11188 + data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign add_ln703_421_fu_3229_p2 = (add_ln703_402_reg_11215 + add_ln703_419_fu_3225_p2); + +assign add_ln703_422_fu_3239_p2 = (sub_ln703_331_fu_3140_p2 + data_25_V_read26_reg_9677_pp0_iter7_reg); + +assign add_ln703_423_fu_3249_p2 = (sub_ln703_287_fu_2849_p2 + data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign add_ln703_424_fu_2762_p2 = (data_24_V_read25_reg_9704_pp0_iter6_reg + data_25_V_read26_reg_9677_pp0_iter6_reg); + +assign add_ln703_425_fu_3254_p2 = (add_ln703_424_reg_11225 + data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign add_ln703_426_fu_3258_p2 = (add_ln703_425_fu_3254_p2 + add_ln703_423_fu_3249_p2); + +assign add_ln703_428_fu_3264_p2 = (add_ln703_424_reg_11225 + sub_ln703_317_fu_3031_p2); + +assign add_ln703_429_fu_3418_p2 = (sub_ln703_335_fu_3384_p2 + data_25_V_read26_reg_9677_pp0_iter8_reg); + +assign add_ln703_430_fu_3423_p2 = (sub_ln703_336_reg_11307 + data_25_V_read26_reg_9677_pp0_iter8_reg); + +assign add_ln703_431_fu_3274_p2 = (sub_ln703_338_fu_3195_p2 + data_25_V_read26_reg_9677_pp0_iter7_reg); + +assign add_ln703_432_fu_3279_p2 = (sub_ln703_294_fu_2875_p2 + data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign add_ln703_435_fu_3284_p2 = (add_ln703_425_fu_3254_p2 + add_ln703_432_fu_3279_p2); + +assign add_ln703_436_fu_3439_p2 = (sub_ln703_342_reg_11327 + data_25_V_read26_reg_9677_pp0_iter8_reg); + +assign add_ln703_437_fu_3443_p2 = (sub_ln703_346_fu_3396_p2 + data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign add_ln703_438_fu_3310_p2 = (sub_ln703_320_fu_3056_p2 + data_24_V_read25_reg_9704_pp0_iter7_reg); + +assign add_ln703_439_fu_2766_p2 = (data_25_V_read26_reg_9677_pp0_iter6_reg + data_26_V_read27_reg_9652_pp0_iter6_reg); + +assign add_ln703_440_fu_3466_p2 = (add_ln703_439_reg_11233_pp0_iter8_reg + add_ln703_438_reg_11382); + +assign add_ln703_441_fu_3480_p2 = (sub_ln703_353_reg_11352 + data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign add_ln703_442_fu_3502_p2 = (sub_ln703_356_reg_11367 + data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign add_ln703_444_fu_3506_p2 = (add_ln703_439_reg_11233_pp0_iter8_reg + sub_ln703_341_fu_3388_p2); + +assign add_ln703_445_fu_3315_p2 = (sub_ln703_310_fu_2978_p2 + data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign add_ln703_447_fu_3320_p2 = (add_ln703_439_reg_11233 + data_24_V_read25_reg_9704_pp0_iter7_reg); + +assign add_ln703_448_fu_3511_p2 = (add_ln703_447_reg_11392 + add_ln703_445_reg_11387); + +assign add_ln703_450_fu_3520_p2 = (add_ln703_439_reg_11233_pp0_iter8_reg + sub_ln703_344_reg_11332); + +assign add_ln703_451_fu_3329_p2 = (data_26_V_read27_reg_9652_pp0_iter7_reg + data_27_V_read28_reg_9625_pp0_iter7_reg); + +assign add_ln703_452_fu_3524_p2 = (add_ln703_451_reg_11402 + sub_ln703_345_reg_11337); + +assign add_ln703_453_fu_3528_p2 = (sub_ln703_358_reg_11372 + data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign add_ln703_455_fu_3537_p2 = (add_ln703_451_reg_11402 + sub_ln703_348_fu_3405_p2); + +assign add_ln703_456_fu_3542_p2 = (sub_ln703_359_fu_3448_p2 + data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign add_ln703_458_fu_3552_p2 = (add_ln703_451_reg_11402 + sub_ln703_351_fu_3414_p2); + +assign add_ln703_459_fu_3557_p2 = (sub_ln703_334_reg_11302 + data_25_V_read26_reg_9677_pp0_iter8_reg); + +assign add_ln703_461_fu_3561_p2 = (add_ln703_451_reg_11402 + add_ln703_459_fu_3557_p2); + +assign add_ln703_462_fu_3571_p2 = (sub_ln703_364_fu_3470_p2 + data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign add_ln703_463_fu_3581_p2 = (sub_ln703_366_fu_3484_p2 + data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign add_ln703_464_fu_3586_p2 = (sub_ln703_367_fu_3488_p2 + data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign add_ln703_465_fu_3630_p2 = (sub_ln703_330_fu_3372_p2 + data_25_V_read26_reg_9677_pp0_iter8_reg); + +assign add_ln703_466_fu_3333_p2 = (data_27_V_read28_reg_9625_pp0_iter7_reg + data_28_V_read_8_reg_9598_pp0_iter7_reg); + +assign add_ln703_467_fu_3635_p2 = (add_ln703_466_reg_11410 + data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign add_ln703_468_fu_3639_p2 = (add_ln703_467_fu_3635_p2 + add_ln703_465_fu_3630_p2); + +assign add_ln703_469_fu_3655_p2 = (sub_ln703_372_fu_3532_p2 + data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign add_ln703_471_fu_3337_p2 = (add_ln703_424_reg_11225 + sub_ln703_319_fu_3041_p2); + +assign add_ln703_474_fu_3680_p2 = (add_ln703_467_fu_3635_p2 + add_ln703_471_reg_11418); + +assign add_ln703_476_fu_3685_p2 = (add_ln703_466_reg_11410 + sub_ln703_363_fu_3461_p2); + +assign add_ln703_477_fu_3715_p2 = (sub_ln703_378_fu_3601_p2 + data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign add_ln703_478_fu_3730_p2 = (sub_ln703_381_fu_3616_p2 + data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign add_ln703_479_fu_3735_p2 = (sub_ln703_343_fu_3392_p2 + data_25_V_read26_reg_9677_pp0_iter8_reg); + +assign add_ln703_482_fu_3740_p2 = (add_ln703_467_fu_3635_p2 + add_ln703_479_fu_3735_p2); + +assign add_ln703_484_fu_3342_p2 = (add_ln703_424_reg_11225 + sub_ln703_329_fu_3126_p2); + +assign add_ln703_487_fu_3756_p2 = (add_ln703_467_fu_3635_p2 + add_ln703_484_reg_11423); + +assign add_ln703_488_fu_3766_p2 = (sub_ln703_385_fu_3650_p2 + data_29_V_read_8_reg_9573_pp0_iter8_reg); + +assign add_ln703_489_fu_3771_p2 = (sub_ln703_361_fu_3457_p2 + data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign add_ln703_490_fu_3347_p2 = (data_28_V_read_8_reg_9598_pp0_iter7_reg + data_29_V_read_8_reg_9573_pp0_iter7_reg); + +assign add_ln703_491_fu_3776_p2 = (add_ln703_490_reg_11428 + add_ln703_489_fu_3771_p2); + +assign add_ln703_493_fu_3796_p2 = (add_ln703_490_reg_11428 + sub_ln703_374_fu_3566_p2); + +assign add_ln703_494_fu_3801_p2 = (sub_ln703_365_fu_3475_p2 + data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign add_ln703_496_fu_3806_p2 = (add_ln703_490_reg_11428 + add_ln703_494_fu_3801_p2); + +assign add_ln703_497_fu_3811_p2 = (sub_ln703_391_fu_3695_p2 + data_29_V_read_8_reg_9573_pp0_iter8_reg); + +assign add_ln703_498_fu_3351_p2 = (sub_ln703_278_fu_2807_p2 + data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign add_ln703_500_fu_3821_p2 = (add_ln703_402_reg_11215_pp0_iter8_reg + data_22_V_read23_reg_9756_pp0_iter8_reg); + +assign add_ln703_501_fu_3825_p2 = (add_ln703_500_fu_3821_p2 + add_ln703_498_reg_11436); + +assign add_ln703_504_fu_3830_p2 = (add_ln703_490_reg_11428 + data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign add_ln703_505_fu_3834_p2 = (add_ln703_504_fu_3830_p2 + add_ln703_439_reg_11233_pp0_iter8_reg); + +assign add_ln703_506_fu_3839_p2 = (add_ln703_505_fu_3834_p2 + add_ln703_501_fu_3825_p2); + +assign add_ln703_507_fu_3356_p2 = (data_29_V_read_8_reg_9573_pp0_iter7_reg + data_30_V_read31_reg_9549_pp0_iter7_reg); + +assign add_ln703_508_fu_4006_p2 = (add_ln703_507_reg_11441_pp0_iter9_reg + sub_ln703_386_reg_11484); + +assign add_ln703_509_fu_3870_p2 = (sub_ln703_362_reg_11377 + data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign add_ln703_511_fu_3874_p2 = (add_ln703_507_reg_11441 + data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign add_ln703_512_fu_3878_p2 = (add_ln703_511_fu_3874_p2 + add_ln703_509_fu_3870_p2); + +assign add_ln703_513_fu_4035_p2 = (sub_ln703_407_fu_3985_p2 + data_30_V_read31_reg_9549_pp0_iter9_reg); + +assign add_ln703_515_fu_3889_p2 = (add_ln703_507_reg_11441 + sub_ln703_396_fu_3725_p2); + +assign add_ln703_517_fu_3894_p2 = (add_ln703_507_reg_11441 + sub_ln703_397_fu_3746_p2); + +assign add_ln703_519_fu_3899_p2 = (add_ln703_507_reg_11441 + sub_ln703_398_fu_3751_p2); + +assign add_ln703_520_fu_4058_p2 = (sub_ln703_412_reg_11574 + data_30_V_read31_reg_9549_pp0_iter9_reg); + +assign add_ln703_521_fu_4062_p2 = (sub_ln703_413_fu_3997_p2 + data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign add_ln703_522_fu_4067_p2 = (sub_ln703_414_reg_11579 + data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign add_ln703_523_fu_2770_p2 = (sub_ln703_183_reg_10868 + data_16_V_read17_reg_9935_pp0_iter6_reg); + +assign add_ln703_525_fu_2774_p2 = (add_ln703_326_reg_10855_pp0_iter6_reg + add_ln703_523_fu_2770_p2); + +assign add_ln703_528_fu_3360_p2 = (add_ln703_369_reg_11037_pp0_iter7_reg + add_ln703_354_reg_11131); + +assign add_ln703_529_fu_4071_p2 = (add_ln703_528_reg_11452_pp0_iter9_reg + add_ln703_525_reg_11243_pp0_iter9_reg); + +assign add_ln703_532_fu_3904_p2 = (add_ln703_439_reg_11233_pp0_iter8_reg + add_ln703_402_reg_11215_pp0_iter8_reg); + +assign add_ln703_534_fu_2779_p2 = (data_30_V_read31_reg_9549_pp0_iter6_reg + data_31_V_read32_reg_9521_pp0_iter6_reg); + +assign add_ln703_535_fu_3364_p2 = (add_ln703_534_reg_11248 + data_29_V_read_8_reg_9573_pp0_iter7_reg); + +assign add_ln703_536_fu_3908_p2 = (add_ln703_535_reg_11457 + add_ln703_466_reg_11410); + +assign add_ln703_537_fu_3912_p2 = (add_ln703_536_fu_3908_p2 + add_ln703_532_fu_3904_p2); + +assign add_ln703_538_fu_4075_p2 = (add_ln703_537_reg_11609 + add_ln703_529_fu_4071_p2); + +assign add_ln703_539_fu_4085_p2 = (sub_ln703_387_reg_11489 + data_29_V_read_8_reg_9573_pp0_iter9_reg); + +assign add_ln703_541_fu_4089_p2 = (add_ln703_534_reg_11248_pp0_iter9_reg + add_ln703_539_fu_4085_p2); + +assign add_ln703_542_fu_3918_p2 = (sub_ln703_373_fu_3547_p2 + data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign add_ln703_545_fu_3923_p2 = (add_ln703_535_reg_11457 + add_ln703_542_fu_3918_p2); + +assign add_ln703_546_fu_4094_p2 = (sub_ln703_416_reg_11584 + data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign add_ln703_548_fu_4098_p2 = (add_ln703_534_reg_11248_pp0_iter9_reg + sub_ln703_401_reg_11529); + +assign add_ln703_550_fu_4111_p2 = (add_ln703_534_reg_11248_pp0_iter9_reg + sub_ln703_403_reg_11539); + +assign add_ln703_551_fu_4115_p2 = (sub_ln703_418_fu_4014_p2 + data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign add_ln703_552_fu_4139_p2 = (sub_ln703_423_fu_4031_p2 + data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign add_ln703_553_fu_3928_p2 = (sub_ln703_376_fu_3591_p2 + data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign add_ln703_556_fu_3933_p2 = (add_ln703_535_reg_11457 + add_ln703_553_fu_3928_p2); + +assign add_ln703_557_fu_4158_p2 = (sub_ln703_426_fu_4049_p2 + data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign add_ln703_558_fu_4216_p2 = (sub_ln703_429_fu_4102_p2 + data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign add_ln703_559_fu_4241_p2 = (sub_ln703_432_fu_4124_p2 + data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign add_ln703_560_fu_3943_p2 = (data_31_V_read32_reg_9521_pp0_iter8_reg + data_32_V_read_3_reg_9492_pp0_iter8_reg); + +assign add_ln703_561_fu_4260_p2 = (add_ln703_560_reg_11629 + sub_ln703_425_fu_4044_p2); + +assign add_ln703_562_fu_4275_p2 = (sub_ln703_439_fu_4168_p2 + data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign add_ln703_563_fu_4280_p2 = (sub_ln703_440_reg_11624 + data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign add_ln703_564_fu_3947_p2 = (sub_ln703_347_fu_3400_p2 + data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign add_ln703_566_fu_3952_p2 = (add_ln703_466_reg_11410 + add_ln703_564_fu_3947_p2); + +assign add_ln703_568_fu_3368_p2 = (data_32_V_read_3_reg_9492_pp0_iter7_reg + data_33_V_read_3_reg_9463_pp0_iter7_reg); + +assign add_ln703_569_fu_3957_p2 = (add_ln703_568_reg_11464 + data_31_V_read32_reg_9521_pp0_iter8_reg); + +assign add_ln703_570_fu_4294_p2 = (add_ln703_569_reg_11640 + add_ln703_507_reg_11441_pp0_iter9_reg); + +assign add_ln703_571_fu_4298_p2 = (add_ln703_570_fu_4294_p2 + add_ln703_566_reg_11635); + +assign add_ln703_572_fu_4308_p2 = (sub_ln703_446_fu_4197_p2 + data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign add_ln703_573_fu_4323_p2 = (sub_ln703_450_fu_4221_p2 + data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign add_ln703_574_fu_4566_p2 = (sub_ln703_453_reg_11683 + data_33_V_read_3_reg_9463_pp0_iter10_reg); + +assign add_ln703_576_fu_4338_p2 = (add_ln703_568_reg_11464_pp0_iter9_reg + sub_ln703_433_fu_4129_p2); + +assign add_ln703_577_fu_4343_p2 = (sub_ln703_406_fu_3981_p2 + data_30_V_read31_reg_9549_pp0_iter9_reg); + +assign add_ln703_580_fu_4348_p2 = (add_ln703_569_reg_11640 + add_ln703_577_fu_4343_p2); + +assign add_ln703_581_fu_4358_p2 = (sub_ln703_455_fu_4251_p2 + data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign add_ln703_583_fu_4363_p2 = (add_ln703_568_reg_11464_pp0_iter9_reg + sub_ln703_435_fu_4144_p2); + +assign add_ln703_585_fu_4383_p2 = (add_ln703_568_reg_11464_pp0_iter9_reg + sub_ln703_438_fu_4163_p2); + +assign add_ln703_586_fu_4398_p2 = (sub_ln703_460_fu_4289_p2 + data_34_V_read_3_reg_9434_pp0_iter9_reg); + +assign add_ln703_587_fu_4403_p2 = (sub_ln703_415_fu_4001_p2 + data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign add_ln703_588_fu_3961_p2 = (data_33_V_read_3_reg_9463_pp0_iter8_reg + data_34_V_read_3_reg_9434_pp0_iter8_reg); + +assign add_ln703_589_fu_4408_p2 = (add_ln703_588_reg_11646 + data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign add_ln703_590_fu_4412_p2 = (add_ln703_589_fu_4408_p2 + add_ln703_587_fu_4403_p2); + +assign add_ln703_591_fu_4423_p2 = (sub_ln703_464_fu_4318_p2 + data_34_V_read_3_reg_9434_pp0_iter9_reg); + +assign add_ln703_592_fu_4428_p2 = (sub_ln703_465_fu_4328_p2 + data_34_V_read_3_reg_9434_pp0_iter9_reg); + +assign add_ln703_594_fu_4433_p2 = (add_ln703_507_reg_11441_pp0_iter9_reg + sub_ln703_390_reg_11499); + +assign add_ln703_597_fu_4437_p2 = (add_ln703_588_reg_11646 + add_ln703_560_reg_11629); + +assign add_ln703_598_fu_4441_p2 = (add_ln703_597_fu_4437_p2 + add_ln703_594_fu_4433_p2); + +assign add_ln703_599_fu_4477_p2 = (sub_ln703_442_fu_4177_p2 + data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign add_ln703_600_fu_3965_p2 = (data_34_V_read_3_reg_9434_pp0_iter8_reg + data_35_V_read_3_reg_9410_pp0_iter8_reg); + +assign add_ln703_601_fu_4620_p2 = (add_ln703_600_reg_11652_pp0_iter10_reg + add_ln703_599_reg_11798); + +assign add_ln703_602_fu_4482_p2 = (sub_ln703_384_reg_11474 + data_29_V_read_8_reg_9573_pp0_iter9_reg); + +assign add_ln703_604_fu_4486_p2 = (add_ln703_534_reg_11248_pp0_iter9_reg + add_ln703_602_fu_4482_p2); + +assign add_ln703_607_fu_4491_p2 = (add_ln703_600_reg_11652 + add_ln703_568_reg_11464_pp0_iter9_reg); + +assign add_ln703_608_fu_4495_p2 = (add_ln703_607_fu_4491_p2 + add_ln703_604_fu_4486_p2); + +assign add_ln703_609_fu_4501_p2 = (sub_ln703_444_fu_4187_p2 + data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign add_ln703_611_fu_4628_p2 = (add_ln703_600_reg_11652_pp0_iter10_reg + add_ln703_609_reg_11803); + +assign add_ln703_612_fu_4640_p2 = (sub_ln703_477_fu_4578_p2 + data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign add_ln703_613_fu_4645_p2 = (sub_ln703_478_fu_4582_p2 + data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign add_ln703_614_fu_4506_p2 = (sub_ln703_449_fu_4211_p2 + data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign add_ln703_616_fu_4511_p2 = (add_ln703_600_reg_11652 + add_ln703_614_fu_4506_p2); + +assign add_ln703_617_fu_4677_p2 = (sub_ln703_484_fu_4599_p2 + data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign add_ln703_618_fu_4687_p2 = (sub_ln703_486_fu_4607_p2 + data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign add_ln703_619_fu_4692_p2 = (sub_ln703_488_reg_11783 + data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign add_ln703_620_fu_4696_p2 = (sub_ln703_491_reg_11793 + data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign add_ln703_621_fu_3969_p2 = (data_35_V_read_3_reg_9410_pp0_iter8_reg + data_36_V_read_3_reg_9383_pp0_iter8_reg); + +assign add_ln703_622_fu_4720_p2 = (add_ln703_621_reg_11662_pp0_iter10_reg + sub_ln703_476_fu_4574_p2); + +assign add_ln703_623_fu_4739_p2 = (sub_ln703_496_fu_4650_p2 + data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign add_ln703_624_fu_4754_p2 = (sub_ln703_466_fu_4562_p2 + data_34_V_read_3_reg_9434_pp0_iter10_reg); + +assign add_ln703_626_fu_4759_p2 = (add_ln703_621_reg_11662_pp0_iter10_reg + add_ln703_624_fu_4754_p2); + +assign add_ln703_627_fu_4769_p2 = (sub_ln703_501_fu_4672_p2 + data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign add_ln703_629_fu_4774_p2 = (add_ln703_621_reg_11662_pp0_iter10_reg + sub_ln703_482_reg_11773); + +assign add_ln703_631_fu_4526_p2 = (add_ln703_568_reg_11464_pp0_iter9_reg + sub_ln703_434_fu_4134_p2); + +assign add_ln703_633_fu_4531_p2 = (add_ln703_621_reg_11662 + data_34_V_read_3_reg_9434_pp0_iter9_reg); + +assign add_ln703_634_fu_4535_p2 = (add_ln703_633_fu_4531_p2 + add_ln703_631_fu_4526_p2); + +assign add_ln703_636_fu_4793_p2 = (add_ln703_621_reg_11662_pp0_iter10_reg + sub_ln703_487_fu_4611_p2); + +assign add_ln703_638_fu_4803_p2 = (add_ln703_621_reg_11662_pp0_iter10_reg + sub_ln703_489_fu_4615_p2); + +assign add_ln703_639_fu_4541_p2 = (sub_ln703_459_fu_4284_p2 + data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign add_ln703_642_fu_4817_p2 = (add_ln703_633_reg_11823 + add_ln703_639_reg_11833); + +assign add_ln703_643_fu_4821_p2 = (sub_ln703_504_fu_4700_p2 + data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign add_ln703_644_fu_4826_p2 = (sub_ln703_505_reg_11818 + data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign add_ln703_645_fu_4835_p2 = (sub_ln703_507_fu_4710_p2 + data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign add_ln703_646_fu_4546_p2 = (data_36_V_read_3_reg_9383_pp0_iter9_reg + data_37_V_read_3_reg_9353_pp0_iter9_reg); + +assign add_ln703_647_fu_4870_p2 = (add_ln703_646_reg_11838 + sub_ln703_499_fu_4663_p2); + +assign add_ln703_648_fu_4899_p2 = (sub_ln703_516_fu_4783_p2 + data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign add_ln703_649_fu_4914_p2 = (sub_ln703_518_fu_4798_p2 + data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign add_ln703_650_fu_4550_p2 = (data_37_V_read_3_reg_9353_pp0_iter9_reg + data_38_V_read_3_reg_9328_pp0_iter9_reg); + +assign add_ln703_651_fu_4959_p2 = (add_ln703_650_reg_11844 + sub_ln703_510_fu_4730_p2); + +assign add_ln703_653_fu_4964_p2 = (add_ln703_600_reg_11652_pp0_iter10_reg + sub_ln703_463_fu_4558_p2); + +assign add_ln703_655_fu_4969_p2 = (add_ln703_650_reg_11844 + data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign add_ln703_656_fu_4973_p2 = (add_ln703_655_fu_4969_p2 + add_ln703_653_fu_4964_p2); + +assign add_ln703_658_fu_4989_p2 = (add_ln703_650_reg_11844 + sub_ln703_513_fu_4749_p2); + +assign add_ln703_659_fu_5150_p2 = (sub_ln703_529_reg_11879 + data_38_V_read_3_reg_9328_pp0_iter11_reg); + +assign add_ln703_660_fu_4994_p2 = (sub_ln703_531_fu_4890_p2 + data_38_V_read_3_reg_9328_pp0_iter10_reg); + +assign add_ln703_661_fu_4999_p2 = (sub_ln703_534_fu_4909_p2 + data_38_V_read_3_reg_9328_pp0_iter10_reg); + +assign add_ln703_662_fu_5166_p2 = (sub_ln703_535_reg_11899 + data_38_V_read_3_reg_9328_pp0_iter11_reg); + +assign add_ln703_663_fu_5009_p2 = (sub_ln703_490_reg_11788 + data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign add_ln703_666_fu_5013_p2 = (add_ln703_655_fu_4969_p2 + add_ln703_663_fu_5009_p2); + +assign add_ln703_667_fu_4554_p2 = (data_38_V_read_3_reg_9328_pp0_iter9_reg + data_39_V_read_3_reg_9301_pp0_iter9_reg); + +assign add_ln703_668_fu_5019_p2 = (add_ln703_667_reg_11853 + sub_ln703_521_fu_4830_p2); + +assign add_ln703_669_fu_5186_p2 = (sub_ln703_544_reg_11934 + data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign add_ln703_671_fu_5039_p2 = (add_ln703_667_reg_11853 + sub_ln703_530_fu_4885_p2); + +assign add_ln703_673_fu_5044_p2 = (add_ln703_621_reg_11662_pp0_iter10_reg + sub_ln703_483_reg_11778); + +assign add_ln703_675_fu_5048_p2 = (add_ln703_667_reg_11853 + data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign add_ln703_676_fu_5052_p2 = (add_ln703_675_fu_5048_p2 + add_ln703_673_fu_5044_p2); + +assign add_ln703_678_fu_5058_p2 = (add_ln703_600_reg_11652_pp0_iter10_reg + sub_ln703_469_reg_11733); + +assign add_ln703_681_fu_5062_p2 = (add_ln703_667_reg_11853 + add_ln703_646_reg_11838); + +assign add_ln703_682_fu_5066_p2 = (add_ln703_681_fu_5062_p2 + add_ln703_678_fu_5058_p2); + +assign add_ln703_683_fu_5072_p2 = (sub_ln703_519_fu_4808_p2 + data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign add_ln703_685_fu_5077_p2 = (add_ln703_667_reg_11853 + add_ln703_683_fu_5072_p2); + +assign add_ln703_687_fu_5082_p2 = (add_ln703_667_reg_11853 + sub_ln703_536_fu_4924_p2); + +assign add_ln703_689_fu_5087_p2 = (add_ln703_667_reg_11853 + sub_ln703_537_fu_4929_p2); + +assign add_ln703_690_fu_5240_p2 = (sub_ln703_553_fu_5174_p2 + data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign add_ln703_691_fu_5092_p2 = (data_39_V_read_3_reg_9301_pp0_iter10_reg + data_40_V_read41_reg_9272_pp0_iter10_reg); + +assign add_ln703_692_fu_5245_p2 = (add_ln703_691_reg_11994 + sub_ln703_541_reg_11919); + +assign add_ln703_693_fu_5249_p2 = (sub_ln703_554_fu_5178_p2 + data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign add_ln703_694_fu_5254_p2 = (sub_ln703_555_fu_5182_p2 + data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign add_ln703_695_fu_5259_p2 = (sub_ln703_556_reg_11964 + data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign add_ln703_696_fu_5272_p2 = (sub_ln703_558_reg_11974 + data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign add_ln703_697_fu_5096_p2 = (sub_ln703_528_fu_4875_p2 + data_38_V_read_3_reg_9328_pp0_iter10_reg); + +assign add_ln703_699_fu_5281_p2 = (add_ln703_691_reg_11994 + add_ln703_697_reg_12002); + +assign add_ln703_700_fu_5285_p2 = (sub_ln703_561_fu_5200_p2 + data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign add_ln703_701_fu_5313_p2 = (sub_ln703_566_fu_5223_p2 + data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign add_ln703_702_fu_5332_p2 = (sub_ln703_538_reg_11904 + data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign add_ln703_703_fu_5116_p2 = (data_40_V_read41_reg_9272_pp0_iter10_reg + data_41_V_read42_reg_9242_pp0_iter10_reg); + +assign add_ln703_704_fu_5336_p2 = (add_ln703_703_reg_12022 + add_ln703_702_fu_5332_p2); + +assign add_ln703_706_fu_5120_p2 = (add_ln703_650_reg_11844 + sub_ln703_509_fu_4725_p2); + +assign add_ln703_708_fu_5361_p2 = (add_ln703_703_reg_12022 + data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign add_ln703_709_fu_5365_p2 = (add_ln703_708_fu_5361_p2 + add_ln703_706_reg_12031); + +assign add_ln703_710_fu_5390_p2 = (sub_ln703_545_fu_5138_p2 + data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign add_ln703_712_fu_5395_p2 = (add_ln703_703_reg_12022 + add_ln703_710_fu_5390_p2); + +assign add_ln703_714_fu_5405_p2 = (add_ln703_703_reg_12022 + sub_ln703_559_fu_5190_p2); + +assign add_ln703_715_fu_5425_p2 = (sub_ln703_573_reg_12007 + data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign add_ln703_716_fu_5429_p2 = (sub_ln703_574_fu_5290_p2 + data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign add_ln703_718_fu_5434_p2 = (add_ln703_703_reg_12022 + sub_ln703_563_fu_5209_p2); + +assign add_ln703_719_fu_5439_p2 = (sub_ln703_576_fu_5299_p2 + data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign add_ln703_720_fu_5469_p2 = (sub_ln703_582_reg_12012 + data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign add_ln703_721_fu_5692_p2 = (sub_ln703_586_reg_12061 + data_42_V_read_3_reg_9212_pp0_iter12_reg); + +assign add_ln703_722_fu_5125_p2 = (sub_ln703_495_fu_4636_p2 + data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign add_ln703_724_fu_5477_p2 = (add_ln703_650_reg_11844_pp0_iter11_reg + add_ln703_722_reg_12036); + +assign add_ln703_726_fu_5130_p2 = (data_41_V_read42_reg_9242_pp0_iter10_reg + data_42_V_read_3_reg_9212_pp0_iter10_reg); + +assign add_ln703_727_fu_5481_p2 = (add_ln703_726_reg_12041 + add_ln703_691_reg_11994); + +assign add_ln703_728_fu_5485_p2 = (add_ln703_727_fu_5481_p2 + add_ln703_724_fu_5477_p2); + +assign add_ln703_729_fu_5700_p2 = (sub_ln703_593_reg_12071 + data_42_V_read_3_reg_9212_pp0_iter12_reg); + +assign add_ln703_730_fu_5541_p2 = (sub_ln703_596_fu_5444_p2 + data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign add_ln703_732_fu_5546_p2 = (add_ln703_726_reg_12041 + sub_ln703_578_fu_5308_p2); + +assign add_ln703_733_fu_5551_p2 = (sub_ln703_597_fu_5449_p2 + data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign add_ln703_734_fu_5556_p2 = (sub_ln703_599_fu_5459_p2 + data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign add_ln703_735_fu_5571_p2 = (sub_ln703_601_fu_5473_p2 + data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign add_ln703_736_fu_5576_p2 = (sub_ln703_552_fu_5170_p2 + data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign add_ln703_737_fu_5134_p2 = (data_42_V_read_3_reg_9212_pp0_iter10_reg + data_43_V_read_3_reg_9184_pp0_iter10_reg); + +assign add_ln703_738_fu_5581_p2 = (add_ln703_737_reg_12047 + data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign add_ln703_739_fu_5585_p2 = (add_ln703_738_fu_5581_p2 + add_ln703_736_fu_5576_p2); + +assign add_ln703_741_fu_5591_p2 = (add_ln703_737_reg_12047 + sub_ln703_584_fu_5341_p2); + +assign add_ln703_742_fu_5738_p2 = (sub_ln703_605_reg_12111 + data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign add_ln703_744_fu_5601_p2 = (add_ln703_737_reg_12047 + sub_ln703_592_fu_5400_p2); + +assign add_ln703_745_fu_5606_p2 = (sub_ln703_575_fu_5295_p2 + data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign add_ln703_747_fu_5611_p2 = (add_ln703_737_reg_12047 + add_ln703_745_fu_5606_p2); + +assign add_ln703_748_fu_5759_p2 = (sub_ln703_614_reg_12141 + data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign add_ln703_750_fu_5616_p2 = (add_ln703_691_reg_11994 + sub_ln703_549_fu_5158_p2); + +assign add_ln703_753_fu_5621_p2 = (add_ln703_738_fu_5581_p2 + add_ln703_750_fu_5616_p2); + +assign add_ln703_754_fu_5776_p2 = (sub_ln703_618_reg_12156 + data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign add_ln703_755_fu_5652_p2 = (data_43_V_read_3_reg_9184_pp0_iter11_reg + data_44_V_read_3_reg_9154_pp0_iter11_reg); + +assign add_ln703_756_fu_5809_p2 = (add_ln703_755_reg_12196 + sub_ln703_606_fu_5696_p2); + +assign add_ln703_757_fu_5814_p2 = (sub_ln703_624_reg_12166 + data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign add_ln703_759_fu_5818_p2 = (add_ln703_755_reg_12196 + sub_ln703_608_reg_12116); + +assign add_ln703_761_fu_5837_p2 = (add_ln703_755_reg_12196 + sub_ln703_611_fu_5704_p2); + +assign add_ln703_763_fu_5842_p2 = (add_ln703_755_reg_12196 + sub_ln703_612_reg_12131); + +assign add_ln703_764_fu_5861_p2 = (sub_ln703_630_reg_12171 + data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign add_ln703_765_fu_5671_p2 = (data_44_V_read_3_reg_9154_pp0_iter11_reg + data_45_V_read_3_reg_9125_pp0_iter11_reg); + +assign add_ln703_766_fu_5893_p2 = (add_ln703_765_reg_12219 + sub_ln703_621_fu_5726_p2); + +assign add_ln703_767_fu_5942_p2 = (sub_ln703_595_reg_12081 + data_42_V_read_3_reg_9212_pp0_iter12_reg); + +assign add_ln703_769_fu_5946_p2 = (add_ln703_765_reg_12219 + data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign add_ln703_770_fu_5950_p2 = (add_ln703_769_fu_5946_p2 + add_ln703_767_fu_5942_p2); + +assign add_ln703_771_fu_5961_p2 = (sub_ln703_647_fu_5846_p2 + data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign add_ln703_772_fu_5966_p2 = (sub_ln703_649_fu_5851_p2 + data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign add_ln703_774_fu_5985_p2 = (add_ln703_765_reg_12219 + sub_ln703_631_reg_12176); + +assign add_ln703_775_fu_5994_p2 = (sub_ln703_616_fu_5712_p2 + data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign add_ln703_777_fu_5999_p2 = (add_ln703_765_reg_12219 + add_ln703_775_fu_5994_p2); + +assign add_ln703_778_fu_5675_p2 = (data_45_V_read_3_reg_9125_pp0_iter11_reg + data_46_V_read_3_reg_9094_pp0_iter11_reg); + +assign add_ln703_779_fu_6024_p2 = (add_ln703_778_reg_12227 + sub_ln703_636_fu_5784_p2); + +assign add_ln703_781_fu_6029_p2 = (add_ln703_778_reg_12227 + sub_ln703_637_reg_12186); + +assign add_ln703_783_fu_5679_p2 = (add_ln703_737_reg_12047 + sub_ln703_585_fu_5346_p2); + +assign add_ln703_785_fu_6038_p2 = (add_ln703_778_reg_12227 + data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign add_ln703_786_fu_6042_p2 = (add_ln703_785_fu_6038_p2 + add_ln703_783_reg_12236); + +assign add_ln703_788_fu_6082_p2 = (add_ln703_778_reg_12227 + sub_ln703_648_reg_12209); + +assign add_ln703_789_fu_6250_p2 = (sub_ln703_669_reg_12268 + data_46_V_read_3_reg_9094_pp0_iter13_reg); + +assign add_ln703_790_fu_6121_p2 = (sub_ln703_673_fu_6009_p2 + data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign add_ln703_791_fu_6131_p2 = (sub_ln703_675_fu_6019_p2 + data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign add_ln703_792_fu_6146_p2 = (sub_ln703_677_fu_6047_p2 + data_47_V_read_3_reg_9066_pp0_iter12_reg); + +assign add_ln703_793_fu_6258_p2 = (sub_ln703_678_reg_12283 + data_47_V_read_3_reg_9066_pp0_iter13_reg); + +assign add_ln703_794_fu_6151_p2 = (sub_ln703_641_fu_5799_p2 + data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign add_ln703_795_fu_6156_p2 = (data_46_V_read_3_reg_9094_pp0_iter12_reg + data_47_V_read_3_reg_9066_pp0_iter12_reg); + +assign add_ln703_796_fu_6160_p2 = (add_ln703_795_fu_6156_p2 + add_ln703_794_fu_6151_p2); + +assign add_ln703_797_fu_6262_p2 = (sub_ln703_681_fu_6238_p2 + data_47_V_read_3_reg_9066_pp0_iter13_reg); + +assign add_ln703_798_fu_6166_p2 = (add_ln703_795_fu_6156_p2 + sub_ln703_663_fu_5923_p2); + +assign add_ln703_799_fu_6276_p2 = (sub_ln703_685_fu_6246_p2 + data_47_V_read_3_reg_9066_pp0_iter13_reg); + +assign add_ln703_800_fu_6315_p2 = (sub_ln703_697_reg_12358 + data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign add_ln703_801_fu_6187_p2 = (sub_ln703_639_fu_5789_p2 + data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign add_ln703_802_fu_6192_p2 = (data_47_V_read_3_reg_9066_pp0_iter12_reg + data_48_V_read_3_reg_9040_pp0_iter12_reg); + +assign add_ln703_803_fu_6319_p2 = (add_ln703_802_reg_12398 + data_46_V_read_3_reg_9094_pp0_iter13_reg); + +assign add_ln703_804_fu_6323_p2 = (add_ln703_803_fu_6319_p2 + add_ln703_801_reg_12393); + +assign add_ln703_805_fu_6341_p2 = (add_ln703_802_reg_12398 + sub_ln703_680_reg_12293); + +assign add_ln703_806_fu_6359_p2 = (sub_ln703_699_fu_6271_p2 + data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign add_ln703_807_fu_6369_p2 = (sub_ln703_667_reg_12263 + data_46_V_read_3_reg_9094_pp0_iter13_reg); + +assign add_ln703_808_fu_6373_p2 = (add_ln703_802_reg_12398 + add_ln703_807_fu_6369_p2); + +assign add_ln703_809_fu_6378_p2 = (add_ln703_802_reg_12398 + sub_ln703_686_reg_12308); + +assign add_ln703_810_fu_6396_p2 = (sub_ln703_703_fu_6289_p2 + data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign add_ln703_811_fu_6401_p2 = (sub_ln703_704_reg_12383 + data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign add_ln703_812_fu_6405_p2 = (add_ln703_802_reg_12398 + sub_ln703_690_reg_12323); + +assign add_ln703_813_fu_6409_p2 = (add_ln703_802_reg_12398 + sub_ln703_692_reg_12333); + +assign add_ln703_814_fu_6417_p2 = (sub_ln703_708_fu_6302_p2 + data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign add_ln703_815_fu_6196_p2 = (sub_ln703_661_fu_5913_p2 + data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign add_ln703_816_fu_5684_p2 = (data_48_V_read_3_reg_9040_pp0_iter11_reg + data_49_V_read_3_reg_9012_pp0_iter11_reg); + +assign add_ln703_817_fu_6201_p2 = (add_ln703_816_reg_12241 + data_47_V_read_3_reg_9066_pp0_iter12_reg); + +assign add_ln703_818_fu_6205_p2 = (add_ln703_817_fu_6201_p2 + add_ln703_815_fu_6196_p2); + +assign add_ln703_819_fu_6447_p2 = (sub_ln703_714_fu_6345_p2 + data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign add_ln703_820_fu_6211_p2 = (add_ln703_778_reg_12227 + sub_ln703_645_fu_5827_p2); + +assign add_ln703_821_fu_6216_p2 = (add_ln703_817_fu_6201_p2 + add_ln703_820_fu_6211_p2); + +assign add_ln703_822_fu_6482_p2 = (sub_ln703_720_fu_6391_p2 + data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign add_ln703_823_fu_6512_p2 = (sub_ln703_694_reg_12343 + data_47_V_read_3_reg_9066_pp0_iter13_reg); + +assign add_ln703_824_fu_6516_p2 = (add_ln703_816_reg_12241_pp0_iter13_reg + add_ln703_823_fu_6512_p2); + +assign add_ln703_825_fu_6526_p2 = (sub_ln703_722_fu_6422_p2 + data_50_V_read51_reg_8984_pp0_iter13_reg); + +assign add_ln703_826_fu_6222_p2 = (data_49_V_read_3_reg_9012_pp0_iter12_reg + data_50_V_read51_reg_8984_pp0_iter12_reg); + +assign add_ln703_827_fu_6531_p2 = (add_ln703_826_reg_12419 + sub_ln703_710_fu_6311_p2); + +assign add_ln703_828_fu_6536_p2 = (add_ln703_826_reg_12419 + sub_ln703_712_fu_6332_p2); + +assign add_ln703_829_fu_6546_p2 = (sub_ln703_679_reg_12288 + data_47_V_read_3_reg_9066_pp0_iter13_reg); + +assign add_ln703_830_fu_6550_p2 = (add_ln703_826_reg_12419 + data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign add_ln703_831_fu_6554_p2 = (add_ln703_830_fu_6550_p2 + add_ln703_829_fu_6546_p2); + +assign add_ln703_832_fu_6569_p2 = (sub_ln703_684_reg_12303 + data_47_V_read_3_reg_9066_pp0_iter13_reg); + +assign add_ln703_833_fu_6573_p2 = (add_ln703_830_fu_6550_p2 + add_ln703_832_fu_6569_p2); + +assign add_ln703_834_fu_6594_p2 = (sub_ln703_732_fu_6477_p2 + data_50_V_read51_reg_8984_pp0_iter13_reg); + +assign add_ln703_835_fu_6815_p2 = (sub_ln703_736_reg_12475 + data_50_V_read51_reg_8984_pp0_iter14_reg); + +assign add_ln703_836_fu_6226_p2 = (data_50_V_read51_reg_8984_pp0_iter12_reg + data_51_V_read52_reg_8956_pp0_iter12_reg); + +assign add_ln703_837_fu_6624_p2 = (add_ln703_836_reg_12428 + sub_ln703_723_fu_6427_p2); + +assign add_ln703_838_fu_6634_p2 = (sub_ln703_739_fu_6541_p2 + data_51_V_read52_reg_8956_pp0_iter13_reg); + +assign add_ln703_839_fu_6836_p2 = (sub_ln703_743_fu_6803_p2 + data_51_V_read52_reg_8956_pp0_iter14_reg); + +assign add_ln703_840_fu_6649_p2 = (sub_ln703_747_fu_6584_p2 + data_51_V_read52_reg_8956_pp0_iter13_reg); + +assign add_ln703_841_fu_6664_p2 = (sub_ln703_752_fu_6609_p2 + data_51_V_read52_reg_8956_pp0_iter13_reg); + +assign add_ln703_842_fu_6669_p2 = (sub_ln703_705_fu_6294_p2 + data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign add_ln703_843_fu_6674_p2 = (add_ln703_836_reg_12428 + data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign add_ln703_844_fu_6678_p2 = (add_ln703_843_fu_6674_p2 + add_ln703_842_fu_6669_p2); + +assign add_ln703_845_fu_6689_p2 = (sub_ln703_754_fu_6619_p2 + data_51_V_read52_reg_8956_pp0_iter13_reg); + +assign add_ln703_846_fu_6863_p2 = (sub_ln703_755_fu_6819_p2 + data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign add_ln703_847_fu_6868_p2 = (sub_ln703_756_fu_6823_p2 + data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign add_ln703_848_fu_6694_p2 = (add_ln703_802_reg_12398 + sub_ln703_676_reg_12278); + +assign add_ln703_849_fu_6230_p2 = (data_51_V_read52_reg_8956_pp0_iter12_reg + data_52_V_read_3_reg_8928_pp0_iter12_reg); + +assign add_ln703_850_fu_6698_p2 = (add_ln703_849_reg_12434 + add_ln703_826_reg_12419); + +assign add_ln703_851_fu_6702_p2 = (add_ln703_850_fu_6698_p2 + add_ln703_848_fu_6694_p2); + +assign add_ln703_852_fu_6713_p2 = (sub_ln703_711_fu_6328_p2 + data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign add_ln703_853_fu_6718_p2 = (add_ln703_849_reg_12434 + data_50_V_read51_reg_8984_pp0_iter13_reg); + +assign add_ln703_854_fu_6722_p2 = (add_ln703_853_fu_6718_p2 + add_ln703_852_fu_6713_p2); + +assign add_ln703_855_fu_6882_p2 = (sub_ln703_759_reg_12525 + data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign add_ln703_856_fu_6891_p2 = (add_ln703_849_reg_12434_pp0_iter14_reg + sub_ln703_742_fu_6799_p2); + +assign add_ln703_857_fu_6728_p2 = (sub_ln703_716_fu_6354_p2 + data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign add_ln703_858_fu_6733_p2 = (add_ln703_853_fu_6718_p2 + add_ln703_857_fu_6728_p2); + +assign add_ln703_859_fu_6901_p2 = (sub_ln703_761_reg_12530 + data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign add_ln703_860_fu_6905_p2 = (add_ln703_849_reg_12434_pp0_iter14_reg + sub_ln703_745_fu_6807_p2); + +assign add_ln703_861_fu_6919_p2 = (sub_ln703_763_reg_12540 + data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign add_ln703_862_fu_6923_p2 = (sub_ln703_764_fu_6845_p2 + data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign add_ln703_863_fu_6744_p2 = (add_ln703_816_reg_12241_pp0_iter13_reg + sub_ln703_706_fu_6298_p2); + +assign add_ln703_864_fu_6749_p2 = (add_ln703_853_fu_6718_p2 + add_ln703_863_fu_6744_p2); + +assign add_ln703_865_fu_6968_p2 = (sub_ln703_770_reg_12570 + data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign add_ln703_866_fu_6972_p2 = (sub_ln703_724_reg_12450 + data_50_V_read51_reg_8984_pp0_iter14_reg); + +assign add_ln703_867_fu_6234_p2 = (data_52_V_read_3_reg_8928_pp0_iter12_reg + data_53_V_read_3_reg_8899_pp0_iter12_reg); + +assign add_ln703_868_fu_6755_p2 = (add_ln703_867_reg_12444 + data_51_V_read52_reg_8956_pp0_iter13_reg); + +assign add_ln703_869_fu_6976_p2 = (add_ln703_868_reg_12585 + add_ln703_866_fu_6972_p2); + +assign add_ln703_870_fu_7025_p2 = (sub_ln703_777_fu_6928_p2 + data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign add_ln703_871_fu_7040_p2 = (sub_ln703_782_fu_6946_p2 + data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign add_ln703_872_fu_7050_p2 = (sub_ln703_784_fu_6954_p2 + data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign add_ln703_873_fu_7055_p2 = (sub_ln703_785_fu_6959_p2 + data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign add_ln703_874_fu_7084_p2 = (sub_ln703_791_fu_6996_p2 + data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign add_ln703_875_fu_7094_p2 = (sub_ln703_793_fu_7005_p2 + data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign add_ln703_876_fu_6769_p2 = (add_ln703_826_reg_12419 + sub_ln703_717_fu_6364_p2); + +assign add_ln703_877_fu_6774_p2 = (data_53_V_read_3_reg_8899_pp0_iter13_reg + data_54_V_read_3_reg_8873_pp0_iter13_reg); + +assign add_ln703_878_fu_7104_p2 = (add_ln703_877_reg_12605 + add_ln703_849_reg_12434_pp0_iter14_reg); + +assign add_ln703_879_fu_7108_p2 = (add_ln703_878_fu_7104_p2 + add_ln703_876_reg_12600); + +assign add_ln703_880_fu_7113_p2 = (sub_ln703_746_reg_12500 + data_51_V_read52_reg_8956_pp0_iter14_reg); + +assign add_ln703_881_fu_7117_p2 = (add_ln703_877_reg_12605 + data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign add_ln703_882_fu_7121_p2 = (add_ln703_881_fu_7117_p2 + add_ln703_880_fu_7113_p2); + +assign add_ln703_883_fu_7127_p2 = (sub_ln703_795_fu_7015_p2 + data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign add_ln703_884_fu_7132_p2 = (sub_ln703_796_fu_7020_p2 + data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign add_ln703_885_fu_7142_p2 = (sub_ln703_798_fu_7035_p2 + data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign add_ln703_886_fu_7147_p2 = (add_ln703_877_reg_12605 + sub_ln703_781_reg_12580); + +assign add_ln703_887_fu_7151_p2 = (sub_ln703_768_fu_6858_p2 + data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign add_ln703_888_fu_7156_p2 = (add_ln703_877_reg_12605 + add_ln703_887_fu_7151_p2); + +assign add_ln703_889_fu_7161_p2 = (sub_ln703_799_reg_12595 + data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign add_ln703_890_fu_7354_p2 = (sub_ln703_801_reg_12660 + data_55_V_read_3_reg_8844_pp0_iter15_reg); + +assign add_ln703_891_fu_7358_p2 = (sub_ln703_802_reg_12665 + data_55_V_read_3_reg_8844_pp0_iter15_reg); + +assign add_ln703_892_fu_7175_p2 = (sub_ln703_803_fu_7070_p2 + data_55_V_read_3_reg_8844_pp0_iter14_reg); + +assign add_ln703_893_fu_7180_p2 = (sub_ln703_804_fu_7075_p2 + data_55_V_read_3_reg_8844_pp0_iter14_reg); + +assign add_ln703_894_fu_6778_p2 = (data_54_V_read_3_reg_8873_pp0_iter13_reg + data_55_V_read_3_reg_8844_pp0_iter13_reg); + +assign add_ln703_895_fu_7185_p2 = (add_ln703_894_reg_12616 + sub_ln703_788_fu_6981_p2); + +assign add_ln703_896_fu_7190_p2 = (sub_ln703_773_fu_6886_p2 + data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign add_ln703_897_fu_7362_p2 = (add_ln703_894_reg_12616_pp0_iter15_reg + add_ln703_896_reg_12725); + +assign add_ln703_898_fu_7195_p2 = (sub_ln703_774_fu_6896_p2 + data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign add_ln703_899_fu_7366_p2 = (add_ln703_894_reg_12616_pp0_iter15_reg + add_ln703_898_reg_12730); + +assign add_ln703_900_fu_7378_p2 = (sub_ln703_807_reg_12685 + data_55_V_read_3_reg_8844_pp0_iter15_reg); + +assign add_ln703_901_fu_7390_p2 = (sub_ln703_808_reg_12700 + data_55_V_read_3_reg_8844_pp0_iter15_reg); + +assign add_ln703_902_fu_7394_p2 = (add_ln703_894_reg_12616_pp0_iter15_reg + sub_ln703_797_reg_12645); + +assign add_ln703_903_fu_7402_p2 = (sub_ln703_811_fu_7346_p2 + data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign add_ln703_904_fu_7240_p2 = (sub_ln703_789_fu_6986_p2 + data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign add_ln703_905_fu_6782_p2 = (data_55_V_read_3_reg_8844_pp0_iter13_reg + data_56_V_read_3_reg_8814_pp0_iter13_reg); + +assign add_ln703_906_fu_7245_p2 = (add_ln703_905_reg_12625 + add_ln703_904_fu_7240_p2); + +assign add_ln703_907_fu_7477_p2 = (sub_ln703_820_reg_12750 + data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign add_ln703_908_fu_7250_p2 = (sub_ln703_780_fu_6942_p2 + data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign add_ln703_909_fu_7255_p2 = (add_ln703_905_reg_12625 + data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign add_ln703_910_fu_7259_p2 = (add_ln703_909_fu_7255_p2 + add_ln703_908_fu_7250_p2); + +assign add_ln703_911_fu_7481_p2 = (sub_ln703_821_reg_12755 + data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign add_ln703_912_fu_7490_p2 = (sub_ln703_824_reg_12765 + data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign add_ln703_913_fu_7494_p2 = (sub_ln703_825_reg_12770 + data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign add_ln703_914_fu_6786_p2 = (sub_ln703_738_fu_6521_p2 + data_50_V_read51_reg_8984_pp0_iter13_reg); + +assign add_ln703_915_fu_7265_p2 = (add_ln703_849_reg_12434_pp0_iter14_reg + add_ln703_914_reg_12632); + +assign add_ln703_916_fu_7269_p2 = (add_ln703_905_reg_12625 + add_ln703_877_reg_12605); + +assign add_ln703_917_fu_7273_p2 = (add_ln703_916_fu_7269_p2 + add_ln703_915_fu_7265_p2); + +assign add_ln703_918_fu_7513_p2 = (sub_ln703_828_fu_7417_p2 + data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign add_ln703_919_fu_7279_p2 = (add_ln703_867_reg_12444_pp0_iter14_reg + sub_ln703_757_reg_12515); + +assign add_ln703_920_fu_6791_p2 = (data_56_V_read_3_reg_8814_pp0_iter13_reg + data_57_V_read_3_reg_8786_pp0_iter13_reg); + +assign add_ln703_921_fu_7283_p2 = (add_ln703_920_reg_12637 + add_ln703_894_reg_12616); + +assign add_ln703_922_fu_7287_p2 = (add_ln703_921_fu_7283_p2 + add_ln703_919_fu_7279_p2); + +assign add_ln703_923_fu_7293_p2 = (add_ln703_877_reg_12605 + sub_ln703_771_fu_6873_p2); + +assign add_ln703_924_fu_7298_p2 = (add_ln703_920_reg_12637 + data_55_V_read_3_reg_8844_pp0_iter14_reg); + +assign add_ln703_925_fu_7302_p2 = (add_ln703_924_fu_7298_p2 + add_ln703_923_fu_7293_p2); + +assign add_ln703_926_fu_7532_p2 = (sub_ln703_832_fu_7434_p2 + data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign add_ln703_927_fu_7537_p2 = (sub_ln703_805_reg_12670 + data_55_V_read_3_reg_8844_pp0_iter15_reg); + +assign add_ln703_928_fu_7541_p2 = (add_ln703_920_reg_12637_pp0_iter15_reg + add_ln703_927_fu_7537_p2); + +assign add_ln703_929_fu_7546_p2 = (sub_ln703_833_fu_7439_p2 + data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign add_ln703_930_fu_7561_p2 = (sub_ln703_837_fu_7458_p2 + data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign add_ln703_931_fu_7308_p2 = (add_ln703_877_reg_12605 + sub_ln703_776_fu_6915_p2); + +assign add_ln703_932_fu_7313_p2 = (add_ln703_924_fu_7298_p2 + add_ln703_931_fu_7308_p2); + +assign add_ln703_933_fu_7581_p2 = (sub_ln703_841_fu_7485_p2 + data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign add_ln703_934_fu_7610_p2 = (sub_ln703_844_fu_7508_p2 + data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign add_ln703_935_fu_7629_p2 = (sub_ln703_846_fu_7523_p2 + data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign add_ln703_936_fu_7634_p2 = (sub_ln703_847_fu_7528_p2 + data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign add_ln703_937_fu_7659_p2 = (data_57_V_read_3_reg_8786_pp0_iter15_reg + data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign add_ln703_938_fu_7663_p2 = (add_ln703_937_fu_7659_p2 + sub_ln703_835_fu_7449_p2); + +assign add_ln703_939_fu_7679_p2 = (add_ln703_937_fu_7659_p2 + sub_ln703_838_fu_7463_p2); + +assign add_ln703_940_fu_7690_p2 = (add_ln703_937_fu_7659_p2 + sub_ln703_840_fu_7472_p2); + +assign add_ln703_941_fu_7701_p2 = (sub_ln703_852_reg_12790 + data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign add_ln703_942_fu_7715_p2 = (sub_ln703_823_reg_12760 + data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign add_ln703_943_fu_7719_p2 = (add_ln703_937_fu_7659_p2 + add_ln703_942_fu_7715_p2); + +assign add_ln703_944_fu_7882_p2 = (sub_ln703_858_reg_12840 + data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign add_ln703_945_fu_7740_p2 = (sub_ln703_830_fu_7426_p2 + data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign add_ln703_946_fu_7334_p2 = (data_58_V_read_3_reg_8756_pp0_iter14_reg + data_59_V_read_3_reg_8724_pp0_iter14_reg); + +assign add_ln703_947_fu_7745_p2 = (add_ln703_946_reg_12805 + add_ln703_945_fu_7740_p2); + +assign add_ln703_948_fu_7760_p2 = (sub_ln703_864_fu_7644_p2 + data_59_V_read_3_reg_8724_pp0_iter15_reg); + +assign add_ln703_949_fu_7765_p2 = (sub_ln703_817_fu_7382_p2 + data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign add_ln703_950_fu_7770_p2 = (add_ln703_946_reg_12805 + data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign add_ln703_951_fu_7774_p2 = (add_ln703_950_fu_7770_p2 + add_ln703_949_fu_7765_p2); + +assign add_ln703_952_fu_7800_p2 = (add_ln703_946_reg_12805 + sub_ln703_854_fu_7586_p2); + +assign add_ln703_953_fu_7956_p2 = (sub_ln703_877_fu_7886_p2 + data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign add_ln703_954_fu_7338_p2 = (data_59_V_read_3_reg_8724_pp0_iter14_reg + data_60_V_read61_reg_8691_pp0_iter14_reg); + +assign add_ln703_955_fu_7815_p2 = (add_ln703_954_reg_12812 + sub_ln703_862_reg_12795); + +assign add_ln703_956_fu_7819_p2 = (add_ln703_920_reg_12637_pp0_iter15_reg + sub_ln703_816_reg_12740); + +assign add_ln703_957_fu_7823_p2 = (add_ln703_954_reg_12812 + data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign add_ln703_958_fu_7827_p2 = (add_ln703_957_fu_7823_p2 + add_ln703_956_fu_7819_p2); + +assign add_ln703_959_fu_7997_p2 = (sub_ln703_889_fu_7922_p2 + data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign add_ln703_960_fu_8012_p2 = (sub_ln703_892_reg_12935 + data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign add_ln703_961_fu_8016_p2 = (sub_ln703_893_reg_12940 + data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign add_ln703_962_fu_8052_p2 = (sub_ln703_905_fu_7970_p2 + data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign add_ln703_963_fu_8062_p2 = (sub_ln703_908_fu_7983_p2 + data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign add_ln703_964_fu_7848_p2 = (data_60_V_read61_reg_8691_pp0_iter15_reg + data_61_V_read62_reg_8663_pp0_iter15_reg); + +assign add_ln703_965_fu_8067_p2 = (add_ln703_964_reg_12985 + sub_ln703_886_fu_7910_p2); + +assign add_ln703_966_fu_8100_p2 = (sub_ln703_914_fu_8020_p2 + data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign add_ln703_967_fu_8105_p2 = (sub_ln703_915_fu_8024_p2 + data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign add_ln703_968_fu_8110_p2 = (add_ln703_964_reg_12985 + sub_ln703_897_fu_7938_p2); + +assign add_ln703_969_fu_8115_p2 = (sub_ln703_918_fu_8033_p2 + data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign add_ln703_970_fu_8125_p2 = (data_61_V_read62_reg_8663_pp0_iter16_reg + data_62_V_read_3_reg_8645_pp0_iter16_reg); + +assign add_ln703_971_fu_8129_p2 = (add_ln703_970_fu_8125_p2 + sub_ln703_904_reg_12960); + +assign add_ln703_972_fu_8148_p2 = (sub_ln703_882_fu_7894_p2 + data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign add_ln703_973_fu_8153_p2 = (add_ln703_970_fu_8125_p2 + add_ln703_972_fu_8148_p2); + +assign add_ln703_974_fu_8159_p2 = (add_ln703_970_fu_8125_p2 + sub_ln703_907_fu_7978_p2); + +assign add_ln703_975_fu_8170_p2 = (sub_ln703_884_fu_7902_p2 + data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign add_ln703_976_fu_8175_p2 = (add_ln703_970_fu_8125_p2 + add_ln703_975_fu_8170_p2); + +assign add_ln703_977_fu_8186_p2 = (sub_ln703_887_fu_7914_p2 + data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign add_ln703_978_fu_8191_p2 = (add_ln703_970_fu_8125_p2 + add_ln703_977_fu_8186_p2); + +assign add_ln703_979_fu_8197_p2 = (add_ln703_970_fu_8125_p2 + sub_ln703_910_fu_7992_p2); + +assign add_ln703_980_fu_8203_p2 = (add_ln703_970_fu_8125_p2 + sub_ln703_912_fu_8002_p2); + +assign add_ln703_981_fu_8214_p2 = (sub_ln703_929_fu_8095_p2 + data_62_V_read_3_reg_8645_pp0_iter16_reg); + +assign add_ln703_982_fu_8239_p2 = (sub_ln703_899_fu_7942_p2 + data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign add_ln703_983_fu_8244_p2 = (add_ln703_970_fu_8125_p2 + add_ln703_982_fu_8239_p2); + +assign add_ln703_984_fu_8250_p2 = (sub_ln703_900_fu_7946_p2 + data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign add_ln703_985_fu_7342_p2 = (data_62_V_read_3_reg_8645_pp0_iter14_reg + data_63_V_read_3_reg_8620_pp0_iter14_reg); + +assign add_ln703_986_fu_8255_p2 = (add_ln703_985_reg_12819_pp0_iter16_reg + add_ln703_984_fu_8250_p2); + +assign add_ln703_987_fu_8260_p2 = (sub_ln703_901_fu_7951_p2 + data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign add_ln703_994_fu_8325_p2 = (sub_ln703_909_fu_7987_p2 + data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign add_ln703_fu_530_p2 = (data_0_V_read_int_reg + data_1_V_read_int_reg); + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_state10_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign sub_ln703_100_fu_1329_p2 = (add_ln703_199_fu_1213_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_101_fu_1334_p2 = (sub_ln703_83_fu_1218_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_102_fu_1344_p2 = (add_ln703_200_fu_1226_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_103_fu_1363_p2 = (sub_ln703_87_fu_1238_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_104_fu_1368_p2 = (add_ln703_201_fu_1243_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_105_fu_1373_p2 = (sub_ln703_88_fu_1248_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_106_fu_1378_p2 = (sub_ln703_89_fu_1252_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_107_fu_1383_p2 = (sub_ln703_90_fu_1257_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_108_fu_1388_p2 = (sub_ln703_91_fu_1261_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_109_fu_1407_p2 = (add_ln703_202_fu_1265_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_10_fu_615_p2 = (data_3_V_read_10_reg_10295_pp0_iter2_reg - add_ln703_131_reg_10354_pp0_iter2_reg); + +assign sub_ln703_110_fu_1412_p2 = (add_ln703_203_fu_1270_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_111_fu_1417_p2 = (sub_ln703_93_fu_1275_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_112_fu_1422_p2 = (sub_ln703_94_fu_1280_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_113_fu_1427_p2 = (add_ln703_206_fu_1290_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_114_fu_1630_p2 = (add_ln703_207_reg_10682 - data_11_V_read12_reg_10075_pp0_iter5_reg); + +assign sub_ln703_115_fu_1432_p2 = (sub_ln703_97_fu_1304_p2 - data_11_V_read12_reg_10075_pp0_iter4_reg); + +assign sub_ln703_116_fu_1634_p2 = (add_ln703_208_reg_10687 - data_11_V_read12_reg_10075_pp0_iter5_reg); + +assign sub_ln703_117_fu_1638_p2 = (add_ln703_210_reg_10692 - data_11_V_read12_reg_10075_pp0_iter5_reg); + +assign sub_ln703_118_fu_1642_p2 = (sub_ln703_98_reg_10697 - data_11_V_read12_reg_10075_pp0_iter5_reg); + +assign sub_ln703_119_fu_1442_p2 = (sub_ln703_99_fu_1324_p2 - data_11_V_read12_reg_10075_pp0_iter4_reg); + +assign sub_ln703_11_fu_576_p2 = (sub_ln703_5_fu_564_p2 - data_3_V_read_10_reg_10295_pp0_iter1_reg); + +assign sub_ln703_120_fu_1447_p2 = (add_ln703_211_fu_1339_p2 - data_11_V_read12_reg_10075_pp0_iter4_reg); + +assign sub_ln703_121_fu_1646_p2 = (add_ln703_216_reg_10702 - data_11_V_read12_reg_10075_pp0_iter5_reg); + +assign sub_ln703_122_fu_1462_p2 = (add_ln703_215_fu_1353_p2 - data_11_V_read12_reg_10075_pp0_iter4_reg); + +assign sub_ln703_123_fu_1467_p2 = (sub_ln703_103_fu_1363_p2 - data_11_V_read12_reg_10075_pp0_iter4_reg); + +assign sub_ln703_124_fu_1650_p2 = (sub_ln703_106_reg_10707 - data_11_V_read12_reg_10075_pp0_iter5_reg); + +assign sub_ln703_125_fu_1482_p2 = (add_ln703_219_fu_1397_p2 - data_11_V_read12_reg_10075_pp0_iter4_reg); + +assign sub_ln703_126_fu_1487_p2 = (add_ln703_221_fu_1402_p2 - data_11_V_read12_reg_10075_pp0_iter4_reg); + +assign sub_ln703_127_fu_1662_p2 = (sub_ln703_109_reg_10722 - data_11_V_read12_reg_10075_pp0_iter5_reg); + +assign sub_ln703_128_fu_1496_p2 = (sub_ln703_111_fu_1417_p2 - data_11_V_read12_reg_10075_pp0_iter4_reg); + +assign sub_ln703_129_fu_1506_p2 = (sub_ln703_113_fu_1427_p2 - data_11_V_read12_reg_10075_pp0_iter4_reg); + +assign sub_ln703_12_fu_627_p2 = (add_ln703_131_reg_10354_pp0_iter2_reg - data_3_V_read_10_reg_10295_pp0_iter2_reg); + +assign sub_ln703_130_fu_1666_p2 = (add_ln703_222_fu_1626_p2 - data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign sub_ln703_131_fu_1680_p2 = (add_ln703_224_reg_10732 - data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign sub_ln703_132_fu_1684_p2 = (sub_ln703_118_fu_1642_p2 - data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign sub_ln703_133_fu_1532_p2 = (add_ln703_225_fu_1452_p2 - data_12_V_read13_reg_10045_pp0_iter4_reg); + +assign sub_ln703_134_fu_1689_p2 = (add_ln703_226_reg_10737 - data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign sub_ln703_135_fu_1698_p2 = (sub_ln703_123_reg_10747 - data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign sub_ln703_136_fu_1702_p2 = (add_ln703_227_reg_10752 - data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign sub_ln703_137_fu_1548_p2 = (add_ln703_228_fu_1477_p2 - data_12_V_read13_reg_10045_pp0_iter4_reg); + +assign sub_ln703_138_fu_1706_p2 = (sub_ln703_124_fu_1650_p2 - data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign sub_ln703_139_fu_1711_p2 = (add_ln703_229_fu_1654_p2 - data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign sub_ln703_13_fu_689_p2 = (sub_ln703_6_reg_10408 - data_4_V_read_10_reg_10273_pp0_iter3_reg); + +assign sub_ln703_140_fu_1716_p2 = (add_ln703_230_fu_1658_p2 - data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign sub_ln703_141_fu_1553_p2 = (sub_ln703_126_fu_1487_p2 - data_12_V_read13_reg_10045_pp0_iter4_reg); + +assign sub_ln703_142_fu_1558_p2 = (add_ln703_232_fu_1492_p2 - data_12_V_read13_reg_10045_pp0_iter4_reg); + +assign sub_ln703_143_fu_1725_p2 = (sub_ln703_127_fu_1662_p2 - data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign sub_ln703_144_fu_1730_p2 = (sub_ln703_128_reg_10762 - data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign sub_ln703_145_fu_1734_p2 = (add_ln703_233_reg_10767 - data_12_V_read13_reg_10045_pp0_iter5_reg); + +assign sub_ln703_146_fu_1580_p2 = (sub_ln703_129_fu_1506_p2 - data_12_V_read13_reg_10045_pp0_iter4_reg); + +assign sub_ln703_147_fu_1738_p2 = (sub_ln703_130_fu_1666_p2 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_148_fu_1743_p2 = (add_ln703_234_fu_1671_p2 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_149_fu_1748_p2 = (add_ln703_235_fu_1676_p2 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_14_fu_693_p2 = (add_ln703_132_reg_10414 - data_4_V_read_10_reg_10273_pp0_iter3_reg); + +assign sub_ln703_150_fu_1763_p2 = (add_ln703_236_reg_10772 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_151_fu_1767_p2 = (add_ln703_238_reg_10777 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_152_fu_1599_p2 = (add_ln703_240_fu_1526_p2 - data_13_V_read14_reg_10015_pp0_iter4_reg); + +assign sub_ln703_153_fu_1775_p2 = (add_ln703_241_fu_1693_p2 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_154_fu_1609_p2 = (add_ln703_244_fu_1542_p2 - data_13_V_read14_reg_10015_pp0_iter4_reg); + +assign sub_ln703_155_fu_1780_p2 = (sub_ln703_135_fu_1698_p2 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_156_fu_1785_p2 = (sub_ln703_136_fu_1702_p2 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_157_fu_1790_p2 = (sub_ln703_137_reg_10787 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_158_fu_1794_p2 = (sub_ln703_139_fu_1711_p2 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_159_fu_1799_p2 = (sub_ln703_140_fu_1716_p2 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_15_fu_631_p2 = (add_ln703_133_fu_603_p2 - data_4_V_read_10_reg_10273_pp0_iter2_reg); + +assign sub_ln703_160_fu_1804_p2 = (add_ln703_245_fu_1721_p2 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_161_fu_1809_p2 = (sub_ln703_141_reg_10792 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_162_fu_1813_p2 = (sub_ln703_142_reg_10797 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_163_fu_1817_p2 = (add_ln703_247_reg_10802 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_164_fu_1826_p2 = (add_ln703_250_reg_10807 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_165_fu_1830_p2 = (sub_ln703_146_reg_10812 - data_13_V_read14_reg_10015_pp0_iter5_reg); + +assign sub_ln703_166_fu_1834_p2 = (sub_ln703_148_fu_1743_p2 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_167_fu_1839_p2 = (sub_ln703_149_fu_1748_p2 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_168_fu_1844_p2 = (add_ln703_251_fu_1753_p2 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_169_fu_1849_p2 = (add_ln703_253_fu_1758_p2 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_16_fu_640_p2 = (data_4_V_read_10_reg_10273_pp0_iter2_reg - add_ln703_134_reg_10385); + +assign sub_ln703_170_fu_1859_p2 = (sub_ln703_150_fu_1763_p2 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_171_fu_1864_p2 = (add_ln703_260_reg_10817 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_172_fu_1868_p2 = (sub_ln703_151_fu_1767_p2 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_173_fu_1873_p2 = (sub_ln703_152_reg_10822 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_174_fu_1877_p2 = (add_ln703_262_reg_10827 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_175_fu_1881_p2 = (add_ln703_263_fu_1771_p2 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_176_fu_1900_p2 = (sub_ln703_154_reg_10832 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_177_fu_1904_p2 = (sub_ln703_156_fu_1785_p2 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_178_fu_1909_p2 = (sub_ln703_157_fu_1790_p2 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_179_fu_1919_p2 = (sub_ln703_160_fu_1804_p2 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_17_fu_653_p2 = (sub_ln703_9_fu_611_p2 - data_4_V_read_10_reg_10273_pp0_iter2_reg); + +assign sub_ln703_180_fu_1929_p2 = (sub_ln703_162_fu_1813_p2 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_181_fu_1944_p2 = (add_ln703_264_fu_1821_p2 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_182_fu_1949_p2 = (sub_ln703_164_fu_1826_p2 - data_14_V_read15_reg_9987_pp0_iter5_reg); + +assign sub_ln703_183_fu_1959_p2 = (sub_ln703_168_fu_1844_p2 - data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign sub_ln703_184_fu_1984_p2 = (add_ln703_266_fu_1854_p2 - data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign sub_ln703_185_fu_1989_p2 = (sub_ln703_172_fu_1868_p2 - data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign sub_ln703_186_fu_1994_p2 = (sub_ln703_173_fu_1873_p2 - data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign sub_ln703_187_fu_1999_p2 = (sub_ln703_174_fu_1877_p2 - data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign sub_ln703_188_fu_2004_p2 = (add_ln703_268_fu_1886_p2 - data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign sub_ln703_189_fu_2014_p2 = (add_ln703_271_fu_1895_p2 - data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign sub_ln703_18_fu_658_p2 = (sub_ln703_8_reg_10392 - data_4_V_read_10_reg_10273_pp0_iter2_reg); + +assign sub_ln703_190_fu_2024_p2 = (sub_ln703_178_fu_1909_p2 - data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign sub_ln703_191_fu_2029_p2 = (add_ln703_273_fu_1914_p2 - data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign sub_ln703_192_fu_2044_p2 = (add_ln703_274_fu_1924_p2 - data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign sub_ln703_193_fu_2049_p2 = (sub_ln703_180_fu_1929_p2 - data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign sub_ln703_194_fu_2054_p2 = (add_ln703_276_fu_1934_p2 - data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign sub_ln703_195_fu_2059_p2 = (add_ln703_277_fu_1939_p2 - data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign sub_ln703_196_fu_2074_p2 = (sub_ln703_181_fu_1944_p2 - data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign sub_ln703_197_fu_2079_p2 = (add_ln703_278_fu_1954_p2 - data_15_V_read16_reg_9962_pp0_iter5_reg); + +assign sub_ln703_198_fu_2099_p2 = (add_ln703_282_fu_1973_p2 - data_16_V_read17_reg_9935_pp0_iter5_reg); + +assign sub_ln703_199_fu_2246_p2 = (add_ln703_283_reg_10873 - data_16_V_read17_reg_9935_pp0_iter6_reg); + +assign sub_ln703_19_fu_705_p2 = (sub_ln703_10_reg_10420 - data_4_V_read_10_reg_10273_pp0_iter3_reg); + +assign sub_ln703_1_fu_540_p2 = (data_0_V_read_10_reg_10329 - data_1_V_read_10_reg_10323); + +assign sub_ln703_200_fu_2115_p2 = (sub_ln703_188_fu_2004_p2 - data_16_V_read17_reg_9935_pp0_iter5_reg); + +assign sub_ln703_201_fu_2258_p2 = (add_ln703_285_reg_10888 - data_16_V_read17_reg_9935_pp0_iter6_reg); + +assign sub_ln703_202_fu_2120_p2 = (sub_ln703_189_fu_2014_p2 - data_16_V_read17_reg_9935_pp0_iter5_reg); + +assign sub_ln703_203_fu_2131_p2 = (add_ln703_287_fu_2019_p2 - data_16_V_read17_reg_9935_pp0_iter5_reg); + +assign sub_ln703_204_fu_2142_p2 = (sub_ln703_190_fu_2024_p2 - data_16_V_read17_reg_9935_pp0_iter5_reg); + +assign sub_ln703_205_fu_2262_p2 = (sub_ln703_191_reg_10893 - data_16_V_read17_reg_9935_pp0_iter6_reg); + +assign sub_ln703_206_fu_2266_p2 = (add_ln703_289_reg_10898 - data_16_V_read17_reg_9935_pp0_iter6_reg); + +assign sub_ln703_207_fu_2274_p2 = (add_ln703_290_reg_10903 - data_16_V_read17_reg_9935_pp0_iter6_reg); + +assign sub_ln703_208_fu_2152_p2 = (sub_ln703_192_fu_2044_p2 - data_16_V_read17_reg_9935_pp0_iter5_reg); + +assign sub_ln703_209_fu_2157_p2 = (sub_ln703_195_fu_2059_p2 - data_16_V_read17_reg_9935_pp0_iter5_reg); + +assign sub_ln703_20_fu_662_p2 = (add_ln703_134_reg_10385 - data_4_V_read_10_reg_10273_pp0_iter2_reg); + +assign sub_ln703_210_fu_2162_p2 = (add_ln703_293_fu_2069_p2 - data_16_V_read17_reg_9935_pp0_iter5_reg); + +assign sub_ln703_211_fu_2278_p2 = (sub_ln703_196_reg_10913 - data_16_V_read17_reg_9935_pp0_iter6_reg); + +assign sub_ln703_212_fu_2173_p2 = (sub_ln703_197_fu_2079_p2 - data_16_V_read17_reg_9935_pp0_iter5_reg); + +assign sub_ln703_213_fu_2282_p2 = (add_ln703_296_fu_2238_p2 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_214_fu_2287_p2 = (add_ln703_298_fu_2242_p2 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_215_fu_2292_p2 = (add_ln703_300_reg_10930 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_216_fu_2296_p2 = (sub_ln703_198_reg_10935 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_217_fu_2305_p2 = (add_ln703_301_fu_2250_p2 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_218_fu_2310_p2 = (add_ln703_303_reg_10940 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_219_fu_2314_p2 = (add_ln703_304_reg_10945 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_21_fu_709_p2 = (sub_ln703_11_reg_10398_pp0_iter3_reg - data_4_V_read_10_reg_10273_pp0_iter3_reg); + +assign sub_ln703_220_fu_2318_p2 = (add_ln703_305_fu_2254_p2 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_221_fu_2332_p2 = (add_ln703_307_reg_10960 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_222_fu_2340_p2 = (add_ln703_309_reg_10970 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_223_fu_2344_p2 = (sub_ln703_204_reg_10975 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_224_fu_2348_p2 = (sub_ln703_205_fu_2262_p2 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_225_fu_2358_p2 = (add_ln703_312_fu_2270_p2 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_226_fu_2363_p2 = (sub_ln703_207_fu_2274_p2 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_227_fu_2368_p2 = (sub_ln703_209_reg_10990 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_228_fu_2372_p2 = (sub_ln703_210_reg_10995 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_229_fu_2376_p2 = (sub_ln703_211_fu_2278_p2 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_22_fu_713_p2 = (add_ln703_135_reg_10425 - data_4_V_read_10_reg_10273_pp0_iter3_reg); + +assign sub_ln703_230_fu_2194_p2 = (add_ln703_314_fu_2167_p2 - data_17_V_read18_reg_9904_pp0_iter5_reg); + +assign sub_ln703_231_fu_2381_p2 = (sub_ln703_212_reg_11000 - data_17_V_read18_reg_9904_pp0_iter6_reg); + +assign sub_ln703_232_fu_2385_p2 = (sub_ln703_213_fu_2282_p2 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_233_fu_2390_p2 = (sub_ln703_215_fu_2292_p2 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_234_fu_2395_p2 = (sub_ln703_216_fu_2296_p2 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_235_fu_2400_p2 = (add_ln703_315_fu_2300_p2 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_236_fu_2415_p2 = (sub_ln703_220_fu_2318_p2 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_237_fu_2214_p2 = (add_ln703_317_fu_2182_p2 - data_18_V_read_8_reg_9874_pp0_iter5_reg); + +assign sub_ln703_238_fu_2424_p2 = (add_ln703_318_fu_2323_p2 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_239_fu_2429_p2 = (add_ln703_319_fu_2328_p2 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_23_fu_666_p2 = (add_ln703_136_fu_623_p2 - data_4_V_read_10_reg_10273_pp0_iter2_reg); + +assign sub_ln703_240_fu_2434_p2 = (sub_ln703_221_fu_2332_p2 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_241_fu_2439_p2 = (add_ln703_320_fu_2336_p2 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_242_fu_2444_p2 = (sub_ln703_222_fu_2340_p2 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_243_fu_2454_p2 = (add_ln703_321_fu_2353_p2 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_244_fu_2468_p2 = (add_ln703_323_reg_11005 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_245_fu_2472_p2 = (sub_ln703_227_fu_2368_p2 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_246_fu_2477_p2 = (sub_ln703_228_fu_2372_p2 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_247_fu_2482_p2 = (sub_ln703_229_fu_2376_p2 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_248_fu_2487_p2 = (sub_ln703_230_reg_11010 - data_18_V_read_8_reg_9874_pp0_iter6_reg); + +assign sub_ln703_249_fu_2496_p2 = (sub_ln703_232_fu_2385_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_24_fu_717_p2 = (sub_ln703_13_fu_689_p2 - data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign sub_ln703_250_fu_2501_p2 = (sub_ln703_235_fu_2400_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_251_fu_2506_p2 = (add_ln703_324_fu_2405_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_252_fu_2511_p2 = (add_ln703_328_reg_11015 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_253_fu_2515_p2 = (add_ln703_329_fu_2410_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_254_fu_2525_p2 = (sub_ln703_236_fu_2415_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_255_fu_2530_p2 = (add_ln703_333_reg_11025 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_256_fu_2534_p2 = (add_ln703_335_fu_2420_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_257_fu_2539_p2 = (sub_ln703_238_fu_2424_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_258_fu_2544_p2 = (sub_ln703_239_fu_2429_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_259_fu_2549_p2 = (sub_ln703_240_fu_2434_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_25_fu_722_p2 = (sub_ln703_14_fu_693_p2 - data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign sub_ln703_260_fu_2559_p2 = (sub_ln703_242_fu_2444_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_261_fu_2569_p2 = (add_ln703_336_fu_2449_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_262_fu_2574_p2 = (sub_ln703_243_fu_2454_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_263_fu_2579_p2 = (add_ln703_337_fu_2459_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_264_fu_2584_p2 = (add_ln703_339_fu_2464_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_265_fu_2613_p2 = (sub_ln703_247_fu_2482_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_266_fu_2618_p2 = (sub_ln703_248_fu_2487_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_267_fu_2623_p2 = (add_ln703_340_fu_2491_p2 - data_19_V_read_8_reg_9845_pp0_iter6_reg); + +assign sub_ln703_268_fu_2783_p2 = (sub_ln703_249_reg_11056 - data_20_V_read21_reg_9814_pp0_iter7_reg); + +assign sub_ln703_269_fu_2787_p2 = (sub_ln703_251_reg_11066 - data_20_V_read21_reg_9814_pp0_iter7_reg); + +assign sub_ln703_26_fu_727_p2 = (add_ln703_137_fu_697_p2 - data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign sub_ln703_270_fu_2628_p2 = (sub_ln703_252_fu_2511_p2 - data_20_V_read21_reg_9814_pp0_iter6_reg); + +assign sub_ln703_271_fu_2791_p2 = (add_ln703_342_reg_11071 - data_20_V_read21_reg_9814_pp0_iter7_reg); + +assign sub_ln703_272_fu_2647_p2 = (sub_ln703_255_fu_2530_p2 - data_20_V_read21_reg_9814_pp0_iter6_reg); + +assign sub_ln703_273_fu_2799_p2 = (sub_ln703_256_reg_11081 - data_20_V_read21_reg_9814_pp0_iter7_reg); + +assign sub_ln703_274_fu_2652_p2 = (sub_ln703_258_fu_2544_p2 - data_20_V_read21_reg_9814_pp0_iter6_reg); + +assign sub_ln703_275_fu_2662_p2 = (add_ln703_343_fu_2554_p2 - data_20_V_read21_reg_9814_pp0_iter6_reg); + +assign sub_ln703_276_fu_2667_p2 = (add_ln703_345_fu_2564_p2 - data_20_V_read21_reg_9814_pp0_iter6_reg); + +assign sub_ln703_277_fu_2803_p2 = (sub_ln703_261_reg_11091 - data_20_V_read21_reg_9814_pp0_iter7_reg); + +assign sub_ln703_278_fu_2807_p2 = (sub_ln703_262_reg_11096 - data_20_V_read21_reg_9814_pp0_iter7_reg); + +assign sub_ln703_279_fu_2815_p2 = (add_ln703_346_reg_11106 - data_20_V_read21_reg_9814_pp0_iter7_reg); + +assign sub_ln703_27_fu_732_p2 = (sub_ln703_15_reg_10430 - data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign sub_ln703_280_fu_2819_p2 = (add_ln703_350_reg_11111 - data_20_V_read21_reg_9814_pp0_iter7_reg); + +assign sub_ln703_281_fu_2688_p2 = (add_ln703_351_fu_2608_p2 - data_20_V_read21_reg_9814_pp0_iter6_reg); + +assign sub_ln703_282_fu_2827_p2 = (sub_ln703_265_reg_11116 - data_20_V_read21_reg_9814_pp0_iter7_reg); + +assign sub_ln703_283_fu_2693_p2 = (sub_ln703_266_fu_2618_p2 - data_20_V_read21_reg_9814_pp0_iter6_reg); + +assign sub_ln703_284_fu_2698_p2 = (sub_ln703_267_fu_2623_p2 - data_20_V_read21_reg_9814_pp0_iter6_reg); + +assign sub_ln703_285_fu_2836_p2 = (sub_ln703_269_fu_2787_p2 - data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign sub_ln703_286_fu_2845_p2 = (add_ln703_352_reg_11126 - data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign sub_ln703_287_fu_2849_p2 = (sub_ln703_271_fu_2791_p2 - data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign sub_ln703_288_fu_2854_p2 = (add_ln703_353_fu_2795_p2 - data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign sub_ln703_289_fu_2703_p2 = (add_ln703_355_fu_2642_p2 - data_21_V_read22_reg_9784_pp0_iter6_reg); + +assign sub_ln703_28_fu_671_p2 = (data_5_V_read_9_reg_10245_pp0_iter2_reg - add_ln703_139_fu_636_p2); + +assign sub_ln703_290_fu_2859_p2 = (sub_ln703_272_reg_11138 - data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign sub_ln703_291_fu_2863_p2 = (sub_ln703_274_reg_11143 - data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign sub_ln703_292_fu_2867_p2 = (add_ln703_356_reg_11148 - data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign sub_ln703_293_fu_2708_p2 = (sub_ln703_276_fu_2667_p2 - data_21_V_read22_reg_9784_pp0_iter6_reg); + +assign sub_ln703_294_fu_2875_p2 = (add_ln703_357_fu_2811_p2 - data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign sub_ln703_295_fu_2880_p2 = (add_ln703_360_reg_11158 - data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign sub_ln703_296_fu_2713_p2 = (add_ln703_361_fu_2683_p2 - data_21_V_read22_reg_9784_pp0_iter6_reg); + +assign sub_ln703_297_fu_2884_p2 = (sub_ln703_279_fu_2815_p2 - data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign sub_ln703_298_fu_2889_p2 = (sub_ln703_280_fu_2819_p2 - data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign sub_ln703_299_fu_2894_p2 = (sub_ln703_281_reg_11163 - data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign sub_ln703_29_fu_749_p2 = (sub_ln703_16_reg_10436 - data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign sub_ln703_2_fu_552_p2 = (sub_ln703_reg_10342 - data_2_V_read_10_reg_10312_pp0_iter1_reg); + +assign sub_ln703_300_fu_2898_p2 = (add_ln703_363_fu_2823_p2 - data_21_V_read22_reg_9784_pp0_iter7_reg); + +assign sub_ln703_301_fu_2718_p2 = (sub_ln703_283_fu_2693_p2 - data_21_V_read22_reg_9784_pp0_iter6_reg); + +assign sub_ln703_302_fu_2907_p2 = (add_ln703_364_fu_2831_p2 - data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign sub_ln703_303_fu_2912_p2 = (sub_ln703_285_fu_2836_p2 - data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign sub_ln703_304_fu_2917_p2 = (add_ln703_365_fu_2841_p2 - data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign sub_ln703_305_fu_2922_p2 = (sub_ln703_286_fu_2845_p2 - data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign sub_ln703_306_fu_2931_p2 = (sub_ln703_290_fu_2859_p2 - data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign sub_ln703_307_fu_2941_p2 = (sub_ln703_291_fu_2863_p2 - data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign sub_ln703_308_fu_2946_p2 = (sub_ln703_292_fu_2867_p2 - data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign sub_ln703_309_fu_2951_p2 = (add_ln703_366_fu_2871_p2 - data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign sub_ln703_30_fu_753_p2 = (add_ln703_140_reg_10442 - data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign sub_ln703_310_fu_2978_p2 = (sub_ln703_298_fu_2889_p2 - data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign sub_ln703_311_fu_2988_p2 = (sub_ln703_300_fu_2898_p2 - data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign sub_ln703_312_fu_2993_p2 = (add_ln703_367_fu_2903_p2 - data_22_V_read23_reg_9756_pp0_iter7_reg); + +assign sub_ln703_313_fu_2998_p2 = (sub_ln703_302_fu_2907_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_314_fu_3003_p2 = (add_ln703_371_reg_11193 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_315_fu_3021_p2 = (sub_ln703_303_fu_2912_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_316_fu_3026_p2 = (sub_ln703_304_fu_2917_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_317_fu_3031_p2 = (add_ln703_372_fu_2927_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_318_fu_3036_p2 = (sub_ln703_306_fu_2931_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_319_fu_3041_p2 = (add_ln703_374_fu_2936_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_31_fu_761_p2 = (add_ln703_144_reg_10403_pp0_iter3_reg - data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign sub_ln703_320_fu_3056_p2 = (sub_ln703_307_fu_2941_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_321_fu_3066_p2 = (sub_ln703_309_fu_2951_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_322_fu_3071_p2 = (add_ln703_377_fu_2956_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_323_fu_3076_p2 = (add_ln703_378_fu_2960_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_324_fu_3091_p2 = (add_ln703_379_fu_2964_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_325_fu_3096_p2 = (add_ln703_380_fu_2969_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_326_fu_3101_p2 = (add_ln703_381_fu_2973_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_327_fu_3106_p2 = (add_ln703_382_fu_2983_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_328_fu_3111_p2 = (sub_ln703_311_fu_2988_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_329_fu_3126_p2 = (sub_ln703_312_fu_2993_p2 - data_23_V_read24_reg_9730_pp0_iter7_reg); + +assign sub_ln703_32_fu_765_p2 = (add_ln703_141_reg_10447 - data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign sub_ln703_330_fu_3372_p2 = (sub_ln703_313_reg_11257 - data_24_V_read25_reg_9704_pp0_iter8_reg); + +assign sub_ln703_331_fu_3140_p2 = (sub_ln703_314_fu_3003_p2 - data_24_V_read25_reg_9704_pp0_iter7_reg); + +assign sub_ln703_332_fu_3376_p2 = (add_ln703_386_reg_11262 - data_24_V_read25_reg_9704_pp0_iter8_reg); + +assign sub_ln703_333_fu_3155_p2 = (sub_ln703_316_fu_3026_p2 - data_24_V_read25_reg_9704_pp0_iter7_reg); + +assign sub_ln703_334_fu_3175_p2 = (sub_ln703_318_fu_3036_p2 - data_24_V_read25_reg_9704_pp0_iter7_reg); + +assign sub_ln703_335_fu_3384_p2 = (add_ln703_390_reg_11272 - data_24_V_read25_reg_9704_pp0_iter8_reg); + +assign sub_ln703_336_fu_3180_p2 = (add_ln703_391_fu_3061_p2 - data_24_V_read25_reg_9704_pp0_iter7_reg); + +assign sub_ln703_337_fu_3190_p2 = (sub_ln703_322_fu_3071_p2 - data_24_V_read25_reg_9704_pp0_iter7_reg); + +assign sub_ln703_338_fu_3195_p2 = (sub_ln703_323_fu_3076_p2 - data_24_V_read25_reg_9704_pp0_iter7_reg); + +assign sub_ln703_339_fu_3200_p2 = (add_ln703_394_fu_3086_p2 - data_24_V_read25_reg_9704_pp0_iter7_reg); + +assign sub_ln703_33_fu_769_p2 = (sub_ln703_18_reg_10459 - data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign sub_ln703_340_fu_3205_p2 = (sub_ln703_324_fu_3091_p2 - data_24_V_read25_reg_9704_pp0_iter7_reg); + +assign sub_ln703_341_fu_3388_p2 = (sub_ln703_326_reg_11277 - data_24_V_read25_reg_9704_pp0_iter8_reg); + +assign sub_ln703_342_fu_3215_p2 = (sub_ln703_327_fu_3106_p2 - data_24_V_read25_reg_9704_pp0_iter7_reg); + +assign sub_ln703_343_fu_3392_p2 = (sub_ln703_328_reg_11282 - data_24_V_read25_reg_9704_pp0_iter8_reg); + +assign sub_ln703_344_fu_3220_p2 = (add_ln703_397_fu_3121_p2 - data_24_V_read25_reg_9704_pp0_iter7_reg); + +assign sub_ln703_345_fu_3234_p2 = (add_ln703_404_fu_3135_p2 - data_25_V_read26_reg_9677_pp0_iter7_reg); + +assign sub_ln703_346_fu_3396_p2 = (add_ln703_410_reg_11287 - data_25_V_read26_reg_9677_pp0_iter8_reg); + +assign sub_ln703_347_fu_3400_p2 = (sub_ln703_332_fu_3376_p2 - data_25_V_read26_reg_9677_pp0_iter8_reg); + +assign sub_ln703_348_fu_3405_p2 = (add_ln703_411_fu_3380_p2 - data_25_V_read26_reg_9677_pp0_iter8_reg); + +assign sub_ln703_349_fu_3410_p2 = (sub_ln703_333_reg_11292 - data_25_V_read26_reg_9677_pp0_iter8_reg); + +assign sub_ln703_34_fu_778_p2 = (sub_ln703_20_reg_10465 - data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign sub_ln703_350_fu_3244_p2 = (add_ln703_413_fu_3160_p2 - data_25_V_read26_reg_9677_pp0_iter7_reg); + +assign sub_ln703_351_fu_3414_p2 = (add_ln703_416_reg_11297 - data_25_V_read26_reg_9677_pp0_iter8_reg); + +assign sub_ln703_352_fu_3427_p2 = (add_ln703_417_reg_11312 - data_25_V_read26_reg_9677_pp0_iter8_reg); + +assign sub_ln703_353_fu_3269_p2 = (sub_ln703_337_fu_3190_p2 - data_25_V_read26_reg_9677_pp0_iter7_reg); + +assign sub_ln703_354_fu_3431_p2 = (sub_ln703_339_reg_11317 - data_25_V_read26_reg_9677_pp0_iter8_reg); + +assign sub_ln703_355_fu_3435_p2 = (sub_ln703_340_reg_11322 - data_25_V_read26_reg_9677_pp0_iter8_reg); + +assign sub_ln703_356_fu_3290_p2 = (add_ln703_418_fu_3210_p2 - data_25_V_read26_reg_9677_pp0_iter7_reg); + +assign sub_ln703_357_fu_3295_p2 = (add_ln703_421_fu_3229_p2 - data_25_V_read26_reg_9677_pp0_iter7_reg); + +assign sub_ln703_358_fu_3300_p2 = (add_ln703_422_fu_3239_p2 - data_26_V_read27_reg_9652_pp0_iter7_reg); + +assign sub_ln703_359_fu_3448_p2 = (sub_ln703_349_fu_3410_p2 - data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign sub_ln703_35_fu_787_p2 = (sub_ln703_23_reg_10471 - data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign sub_ln703_360_fu_3453_p2 = (sub_ln703_350_reg_11342 - data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign sub_ln703_361_fu_3457_p2 = (add_ln703_426_reg_11347 - data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign sub_ln703_362_fu_3305_p2 = (add_ln703_428_fu_3264_p2 - data_26_V_read27_reg_9652_pp0_iter7_reg); + +assign sub_ln703_363_fu_3461_p2 = (add_ln703_429_fu_3418_p2 - data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign sub_ln703_364_fu_3470_p2 = (add_ln703_430_fu_3423_p2 - data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign sub_ln703_365_fu_3475_p2 = (sub_ln703_352_fu_3427_p2 - data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign sub_ln703_366_fu_3484_p2 = (add_ln703_431_reg_11357 - data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign sub_ln703_367_fu_3488_p2 = (sub_ln703_354_fu_3431_p2 - data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign sub_ln703_368_fu_3493_p2 = (add_ln703_435_reg_11362 - data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign sub_ln703_369_fu_3497_p2 = (sub_ln703_355_fu_3435_p2 - data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign sub_ln703_36_fu_795_p2 = (add_ln703_138_fu_701_p2 - data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign sub_ln703_370_fu_3515_p2 = (add_ln703_436_fu_3439_p2 - data_26_V_read27_reg_9652_pp0_iter8_reg); + +assign sub_ln703_371_fu_3324_p2 = (sub_ln703_357_fu_3295_p2 - data_26_V_read27_reg_9652_pp0_iter7_reg); + +assign sub_ln703_372_fu_3532_p2 = (add_ln703_437_fu_3443_p2 - data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign sub_ln703_373_fu_3547_p2 = (sub_ln703_360_fu_3453_p2 - data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign sub_ln703_374_fu_3566_p2 = (add_ln703_440_fu_3466_p2 - data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign sub_ln703_375_fu_3576_p2 = (add_ln703_441_fu_3480_p2 - data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign sub_ln703_376_fu_3591_p2 = (sub_ln703_368_fu_3493_p2 - data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign sub_ln703_377_fu_3596_p2 = (sub_ln703_369_fu_3497_p2 - data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign sub_ln703_378_fu_3601_p2 = (add_ln703_442_fu_3502_p2 - data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign sub_ln703_379_fu_3606_p2 = (add_ln703_444_fu_3506_p2 - data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign sub_ln703_37_fu_800_p2 = (sub_ln703_17_reg_10453 - data_5_V_read_9_reg_10245_pp0_iter3_reg); + +assign sub_ln703_380_fu_3611_p2 = (add_ln703_448_fu_3511_p2 - data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign sub_ln703_381_fu_3616_p2 = (sub_ln703_370_fu_3515_p2 - data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign sub_ln703_382_fu_3621_p2 = (add_ln703_450_fu_3520_p2 - data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign sub_ln703_383_fu_3626_p2 = (sub_ln703_371_reg_11397 - data_27_V_read28_reg_9625_pp0_iter8_reg); + +assign sub_ln703_384_fu_3645_p2 = (add_ln703_452_fu_3524_p2 - data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign sub_ln703_385_fu_3650_p2 = (add_ln703_453_fu_3528_p2 - data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign sub_ln703_386_fu_3660_p2 = (add_ln703_455_fu_3537_p2 - data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign sub_ln703_387_fu_3665_p2 = (add_ln703_456_fu_3542_p2 - data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign sub_ln703_388_fu_3670_p2 = (add_ln703_458_fu_3552_p2 - data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign sub_ln703_389_fu_3675_p2 = (add_ln703_461_fu_3561_p2 - data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign sub_ln703_38_fu_814_p2 = (sub_ln703_27_fu_732_p2 - data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign sub_ln703_390_fu_3690_p2 = (add_ln703_462_fu_3571_p2 - data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign sub_ln703_391_fu_3695_p2 = (sub_ln703_375_fu_3576_p2 - data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign sub_ln703_392_fu_3700_p2 = (add_ln703_463_fu_3581_p2 - data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign sub_ln703_393_fu_3705_p2 = (add_ln703_464_fu_3586_p2 - data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign sub_ln703_394_fu_3710_p2 = (sub_ln703_377_fu_3596_p2 - data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign sub_ln703_395_fu_3720_p2 = (sub_ln703_379_fu_3606_p2 - data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign sub_ln703_396_fu_3725_p2 = (sub_ln703_380_fu_3611_p2 - data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign sub_ln703_397_fu_3746_p2 = (sub_ln703_382_fu_3621_p2 - data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign sub_ln703_398_fu_3751_p2 = (sub_ln703_383_fu_3626_p2 - data_28_V_read_8_reg_9598_pp0_iter8_reg); + +assign sub_ln703_399_fu_3761_p2 = (add_ln703_468_fu_3639_p2 - data_29_V_read_8_reg_9573_pp0_iter8_reg); + +assign sub_ln703_39_fu_819_p2 = (add_ln703_145_fu_736_p2 - data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign sub_ln703_3_fu_560_p2 = (sub_ln703_1_reg_10348 - data_2_V_read_10_reg_10312_pp0_iter1_reg); + +assign sub_ln703_400_fu_3973_p2 = (add_ln703_469_reg_11479 - data_29_V_read_8_reg_9573_pp0_iter9_reg); + +assign sub_ln703_401_fu_3781_p2 = (sub_ln703_388_fu_3670_p2 - data_29_V_read_8_reg_9573_pp0_iter8_reg); + +assign sub_ln703_402_fu_3786_p2 = (sub_ln703_389_fu_3675_p2 - data_29_V_read_8_reg_9573_pp0_iter8_reg); + +assign sub_ln703_403_fu_3791_p2 = (add_ln703_474_fu_3680_p2 - data_29_V_read_8_reg_9573_pp0_iter8_reg); + +assign sub_ln703_404_fu_3977_p2 = (add_ln703_476_reg_11494 - data_29_V_read_8_reg_9573_pp0_iter9_reg); + +assign sub_ln703_405_fu_3816_p2 = (sub_ln703_392_fu_3700_p2 - data_29_V_read_8_reg_9573_pp0_iter8_reg); + +assign sub_ln703_406_fu_3981_p2 = (sub_ln703_393_reg_11504 - data_29_V_read_8_reg_9573_pp0_iter9_reg); + +assign sub_ln703_407_fu_3985_p2 = (sub_ln703_394_reg_11509 - data_29_V_read_8_reg_9573_pp0_iter9_reg); + +assign sub_ln703_408_fu_3845_p2 = (add_ln703_477_fu_3715_p2 - data_29_V_read_8_reg_9573_pp0_iter8_reg); + +assign sub_ln703_409_fu_3989_p2 = (sub_ln703_395_reg_11514 - data_29_V_read_8_reg_9573_pp0_iter9_reg); + +assign sub_ln703_40_fu_824_p2 = (add_ln703_146_fu_741_p2 - data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign sub_ln703_410_fu_3993_p2 = (add_ln703_478_reg_11519 - data_29_V_read_8_reg_9573_pp0_iter9_reg); + +assign sub_ln703_411_fu_3850_p2 = (add_ln703_482_fu_3740_p2 - data_29_V_read_8_reg_9573_pp0_iter8_reg); + +assign sub_ln703_412_fu_3855_p2 = (add_ln703_487_fu_3756_p2 - data_29_V_read_8_reg_9573_pp0_iter8_reg); + +assign sub_ln703_413_fu_3997_p2 = (sub_ln703_399_reg_11524 - data_30_V_read31_reg_9549_pp0_iter9_reg); + +assign sub_ln703_414_fu_3860_p2 = (add_ln703_488_fu_3766_p2 - data_30_V_read31_reg_9549_pp0_iter8_reg); + +assign sub_ln703_415_fu_4001_p2 = (sub_ln703_400_fu_3973_p2 - data_30_V_read31_reg_9549_pp0_iter9_reg); + +assign sub_ln703_416_fu_3865_p2 = (add_ln703_491_fu_3776_p2 - data_30_V_read31_reg_9549_pp0_iter8_reg); + +assign sub_ln703_417_fu_4010_p2 = (sub_ln703_402_reg_11534 - data_30_V_read31_reg_9549_pp0_iter9_reg); + +assign sub_ln703_418_fu_4014_p2 = (sub_ln703_404_fu_3977_p2 - data_30_V_read31_reg_9549_pp0_iter9_reg); + +assign sub_ln703_419_fu_3884_p2 = (add_ln703_493_fu_3796_p2 - data_30_V_read31_reg_9549_pp0_iter8_reg); + +assign sub_ln703_41_fu_829_p2 = (sub_ln703_28_reg_10476 - data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign sub_ln703_420_fu_4019_p2 = (add_ln703_496_reg_11544 - data_30_V_read31_reg_9549_pp0_iter9_reg); + +assign sub_ln703_421_fu_4023_p2 = (add_ln703_497_reg_11549 - data_30_V_read31_reg_9549_pp0_iter9_reg); + +assign sub_ln703_422_fu_4027_p2 = (sub_ln703_405_reg_11554 - data_30_V_read31_reg_9549_pp0_iter9_reg); + +assign sub_ln703_423_fu_4031_p2 = (add_ln703_506_reg_11559 - data_30_V_read31_reg_9549_pp0_iter9_reg); + +assign sub_ln703_424_fu_4040_p2 = (sub_ln703_408_reg_11564 - data_30_V_read31_reg_9549_pp0_iter9_reg); + +assign sub_ln703_425_fu_4044_p2 = (sub_ln703_409_fu_3989_p2 - data_30_V_read31_reg_9549_pp0_iter9_reg); + +assign sub_ln703_426_fu_4049_p2 = (sub_ln703_410_fu_3993_p2 - data_30_V_read31_reg_9549_pp0_iter9_reg); + +assign sub_ln703_427_fu_4054_p2 = (sub_ln703_411_reg_11569 - data_30_V_read31_reg_9549_pp0_iter9_reg); + +assign sub_ln703_428_fu_4080_p2 = (add_ln703_508_fu_4006_p2 - data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign sub_ln703_429_fu_4102_p2 = (add_ln703_512_reg_11589 - data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign sub_ln703_42_fu_833_p2 = (add_ln703_147_fu_745_p2 - data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign sub_ln703_430_fu_4106_p2 = (sub_ln703_417_fu_4010_p2 - data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign sub_ln703_431_fu_4120_p2 = (sub_ln703_419_reg_11594 - data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign sub_ln703_432_fu_4124_p2 = (sub_ln703_420_fu_4019_p2 - data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign sub_ln703_433_fu_4129_p2 = (sub_ln703_421_fu_4023_p2 - data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign sub_ln703_434_fu_4134_p2 = (sub_ln703_422_fu_4027_p2 - data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign sub_ln703_435_fu_4144_p2 = (add_ln703_513_fu_4035_p2 - data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign sub_ln703_436_fu_4149_p2 = (sub_ln703_424_fu_4040_p2 - data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign sub_ln703_437_fu_4154_p2 = (add_ln703_515_reg_11599 - data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign sub_ln703_438_fu_4163_p2 = (sub_ln703_427_fu_4054_p2 - data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign sub_ln703_439_fu_4168_p2 = (add_ln703_517_reg_11604 - data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign sub_ln703_43_fu_838_p2 = (sub_ln703_29_fu_749_p2 - data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign sub_ln703_440_fu_3938_p2 = (add_ln703_519_fu_3899_p2 - data_31_V_read32_reg_9521_pp0_iter8_reg); + +assign sub_ln703_441_fu_4172_p2 = (add_ln703_520_fu_4058_p2 - data_31_V_read32_reg_9521_pp0_iter9_reg); + +assign sub_ln703_442_fu_4177_p2 = (add_ln703_521_fu_4062_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_443_fu_4182_p2 = (add_ln703_522_fu_4067_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_444_fu_4187_p2 = (add_ln703_538_fu_4075_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_445_fu_4192_p2 = (sub_ln703_428_fu_4080_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_446_fu_4197_p2 = (add_ln703_541_fu_4089_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_447_fu_4202_p2 = (add_ln703_545_reg_11614 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_448_fu_4206_p2 = (add_ln703_546_fu_4094_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_449_fu_4211_p2 = (add_ln703_548_fu_4098_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_44_fu_848_p2 = (add_ln703_148_fu_757_p2 - data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign sub_ln703_450_fu_4221_p2 = (sub_ln703_430_fu_4106_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_451_fu_4226_p2 = (add_ln703_550_fu_4111_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_452_fu_4231_p2 = (add_ln703_551_fu_4115_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_453_fu_4236_p2 = (sub_ln703_431_fu_4120_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_454_fu_4246_p2 = (add_ln703_552_fu_4139_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_455_fu_4251_p2 = (add_ln703_556_reg_11619 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_456_fu_4255_p2 = (sub_ln703_436_fu_4149_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_457_fu_4265_p2 = (sub_ln703_437_fu_4154_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_458_fu_4270_p2 = (add_ln703_557_fu_4158_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_459_fu_4284_p2 = (sub_ln703_441_fu_4172_p2 - data_32_V_read_3_reg_9492_pp0_iter9_reg); + +assign sub_ln703_45_fu_853_p2 = (sub_ln703_31_fu_761_p2 - data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign sub_ln703_460_fu_4289_p2 = (sub_ln703_443_fu_4182_p2 - data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign sub_ln703_461_fu_4303_p2 = (sub_ln703_445_fu_4192_p2 - data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign sub_ln703_462_fu_4313_p2 = (sub_ln703_447_fu_4202_p2 - data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign sub_ln703_463_fu_4558_p2 = (sub_ln703_448_reg_11673 - data_33_V_read_3_reg_9463_pp0_iter10_reg); + +assign sub_ln703_464_fu_4318_p2 = (add_ln703_558_fu_4216_p2 - data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign sub_ln703_465_fu_4328_p2 = (sub_ln703_451_fu_4226_p2 - data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign sub_ln703_466_fu_4562_p2 = (sub_ln703_452_reg_11678 - data_33_V_read_3_reg_9463_pp0_iter10_reg); + +assign sub_ln703_467_fu_4333_p2 = (add_ln703_559_fu_4241_p2 - data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign sub_ln703_468_fu_4353_p2 = (sub_ln703_454_fu_4246_p2 - data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign sub_ln703_469_fu_4368_p2 = (sub_ln703_456_fu_4255_p2 - data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign sub_ln703_46_fu_858_p2 = (sub_ln703_32_fu_765_p2 - data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign sub_ln703_470_fu_4373_p2 = (add_ln703_561_fu_4260_p2 - data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign sub_ln703_471_fu_4378_p2 = (sub_ln703_457_fu_4265_p2 - data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign sub_ln703_472_fu_4570_p2 = (sub_ln703_458_reg_11688 - data_33_V_read_3_reg_9463_pp0_iter10_reg); + +assign sub_ln703_473_fu_4388_p2 = (add_ln703_562_fu_4275_p2 - data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign sub_ln703_474_fu_4393_p2 = (add_ln703_563_fu_4280_p2 - data_33_V_read_3_reg_9463_pp0_iter9_reg); + +assign sub_ln703_475_fu_4418_p2 = (add_ln703_571_fu_4298_p2 - data_34_V_read_3_reg_9434_pp0_iter9_reg); + +assign sub_ln703_476_fu_4574_p2 = (sub_ln703_461_reg_11693 - data_34_V_read_3_reg_9434_pp0_iter10_reg); + +assign sub_ln703_477_fu_4578_p2 = (add_ln703_572_reg_11698 - data_34_V_read_3_reg_9434_pp0_iter10_reg); + +assign sub_ln703_478_fu_4582_p2 = (sub_ln703_462_reg_11703 - data_34_V_read_3_reg_9434_pp0_iter10_reg); + +assign sub_ln703_479_fu_4586_p2 = (add_ln703_573_reg_11708 - data_34_V_read_3_reg_9434_pp0_iter10_reg); + +assign sub_ln703_47_fu_863_p2 = (sub_ln703_33_fu_769_p2 - data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign sub_ln703_480_fu_4590_p2 = (add_ln703_574_fu_4566_p2 - data_34_V_read_3_reg_9434_pp0_iter10_reg); + +assign sub_ln703_481_fu_4595_p2 = (sub_ln703_467_reg_11713 - data_34_V_read_3_reg_9434_pp0_iter10_reg); + +assign sub_ln703_482_fu_4447_p2 = (add_ln703_576_fu_4338_p2 - data_34_V_read_3_reg_9434_pp0_iter9_reg); + +assign sub_ln703_483_fu_4452_p2 = (add_ln703_580_fu_4348_p2 - data_34_V_read_3_reg_9434_pp0_iter9_reg); + +assign sub_ln703_484_fu_4599_p2 = (sub_ln703_468_reg_11718 - data_34_V_read_3_reg_9434_pp0_iter10_reg); + +assign sub_ln703_485_fu_4603_p2 = (add_ln703_581_reg_11723 - data_34_V_read_3_reg_9434_pp0_iter10_reg); + +assign sub_ln703_486_fu_4607_p2 = (add_ln703_583_reg_11728 - data_34_V_read_3_reg_9434_pp0_iter10_reg); + +assign sub_ln703_487_fu_4611_p2 = (sub_ln703_470_reg_11738 - data_34_V_read_3_reg_9434_pp0_iter10_reg); + +assign sub_ln703_488_fu_4457_p2 = (sub_ln703_471_fu_4378_p2 - data_34_V_read_3_reg_9434_pp0_iter9_reg); + +assign sub_ln703_489_fu_4615_p2 = (sub_ln703_472_fu_4570_p2 - data_34_V_read_3_reg_9434_pp0_iter10_reg); + +assign sub_ln703_48_fu_877_p2 = (add_ln703_149_fu_773_p2 - data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign sub_ln703_490_fu_4462_p2 = (add_ln703_585_fu_4383_p2 - data_34_V_read_3_reg_9434_pp0_iter9_reg); + +assign sub_ln703_491_fu_4467_p2 = (sub_ln703_473_fu_4388_p2 - data_34_V_read_3_reg_9434_pp0_iter9_reg); + +assign sub_ln703_492_fu_4472_p2 = (sub_ln703_474_fu_4393_p2 - data_34_V_read_3_reg_9434_pp0_iter9_reg); + +assign sub_ln703_493_fu_4624_p2 = (add_ln703_586_reg_11743 - data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign sub_ln703_494_fu_4632_p2 = (add_ln703_590_reg_11748 - data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign sub_ln703_495_fu_4636_p2 = (sub_ln703_475_reg_11753 - data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign sub_ln703_496_fu_4650_p2 = (add_ln703_591_reg_11758 - data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign sub_ln703_497_fu_4654_p2 = (sub_ln703_479_fu_4586_p2 - data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign sub_ln703_498_fu_4659_p2 = (add_ln703_592_reg_11763 - data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign sub_ln703_499_fu_4663_p2 = (sub_ln703_480_fu_4590_p2 - data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign sub_ln703_49_fu_882_p2 = (sub_ln703_34_fu_778_p2 - data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign sub_ln703_4_fu_548_p2 = (add_ln703_reg_10335 - data_2_V_read_10_reg_10312); + +assign sub_ln703_500_fu_4668_p2 = (add_ln703_598_reg_11768 - data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign sub_ln703_501_fu_4672_p2 = (sub_ln703_481_fu_4595_p2 - data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign sub_ln703_502_fu_4682_p2 = (sub_ln703_485_fu_4603_p2 - data_35_V_read_3_reg_9410_pp0_iter10_reg); + +assign sub_ln703_503_fu_4516_p2 = (sub_ln703_492_fu_4472_p2 - data_35_V_read_3_reg_9410_pp0_iter9_reg); + +assign sub_ln703_504_fu_4700_p2 = (add_ln703_601_fu_4620_p2 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_505_fu_4521_p2 = (add_ln703_608_fu_4495_p2 - data_36_V_read_3_reg_9383_pp0_iter9_reg); + +assign sub_ln703_506_fu_4705_p2 = (sub_ln703_493_fu_4624_p2 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_507_fu_4710_p2 = (add_ln703_611_fu_4628_p2 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_508_fu_4715_p2 = (sub_ln703_494_fu_4632_p2 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_509_fu_4725_p2 = (add_ln703_612_fu_4640_p2 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_50_fu_887_p2 = (add_ln703_150_fu_782_p2 - data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign sub_ln703_510_fu_4730_p2 = (add_ln703_613_fu_4645_p2 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_511_fu_4735_p2 = (add_ln703_616_reg_11808 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_512_fu_4744_p2 = (sub_ln703_497_fu_4654_p2 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_513_fu_4749_p2 = (sub_ln703_498_fu_4659_p2 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_514_fu_4764_p2 = (sub_ln703_500_fu_4668_p2 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_515_fu_4778_p2 = (add_ln703_617_fu_4677_p2 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_516_fu_4783_p2 = (sub_ln703_502_fu_4682_p2 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_517_fu_4788_p2 = (add_ln703_618_fu_4687_p2 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_518_fu_4798_p2 = (add_ln703_619_fu_4692_p2 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_519_fu_4808_p2 = (add_ln703_620_fu_4696_p2 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_51_fu_897_p2 = (add_ln703_151_fu_791_p2 - data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign sub_ln703_520_fu_4813_p2 = (sub_ln703_503_reg_11813 - data_36_V_read_3_reg_9383_pp0_iter10_reg); + +assign sub_ln703_521_fu_4830_p2 = (sub_ln703_506_fu_4705_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_522_fu_4840_p2 = (sub_ln703_508_fu_4715_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_523_fu_4845_p2 = (add_ln703_622_fu_4720_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_524_fu_4850_p2 = (sub_ln703_511_fu_4735_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_525_fu_4855_p2 = (add_ln703_623_fu_4739_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_526_fu_4860_p2 = (sub_ln703_512_fu_4744_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_527_fu_4865_p2 = (add_ln703_626_fu_4759_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_528_fu_4875_p2 = (sub_ln703_514_fu_4764_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_529_fu_4880_p2 = (add_ln703_627_fu_4769_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_52_fu_907_p2 = (sub_ln703_37_fu_800_p2 - data_6_V_read_9_reg_10218_pp0_iter3_reg); + +assign sub_ln703_530_fu_4885_p2 = (add_ln703_629_fu_4774_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_531_fu_4890_p2 = (add_ln703_634_reg_11828 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_532_fu_4894_p2 = (sub_ln703_515_fu_4778_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_533_fu_4904_p2 = (sub_ln703_517_fu_4788_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_534_fu_4909_p2 = (add_ln703_636_fu_4793_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_535_fu_4919_p2 = (add_ln703_638_fu_4803_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_536_fu_4924_p2 = (sub_ln703_520_fu_4813_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_537_fu_4929_p2 = (add_ln703_642_fu_4817_p2 - data_37_V_read_3_reg_9353_pp0_iter10_reg); + +assign sub_ln703_538_fu_4934_p2 = (add_ln703_643_fu_4821_p2 - data_38_V_read_3_reg_9328_pp0_iter10_reg); + +assign sub_ln703_539_fu_4939_p2 = (add_ln703_644_fu_4826_p2 - data_38_V_read_3_reg_9328_pp0_iter10_reg); + +assign sub_ln703_53_fu_912_p2 = (add_ln703_152_fu_804_p2 - data_7_V_read_9_reg_10191_pp0_iter3_reg); + +assign sub_ln703_540_fu_4944_p2 = (add_ln703_645_fu_4835_p2 - data_38_V_read_3_reg_9328_pp0_iter10_reg); + +assign sub_ln703_541_fu_4949_p2 = (sub_ln703_522_fu_4840_p2 - data_38_V_read_3_reg_9328_pp0_iter10_reg); + +assign sub_ln703_542_fu_4954_p2 = (sub_ln703_523_fu_4845_p2 - data_38_V_read_3_reg_9328_pp0_iter10_reg); + +assign sub_ln703_543_fu_4979_p2 = (sub_ln703_524_fu_4850_p2 - data_38_V_read_3_reg_9328_pp0_iter10_reg); + +assign sub_ln703_544_fu_4984_p2 = (sub_ln703_525_fu_4855_p2 - data_38_V_read_3_reg_9328_pp0_iter10_reg); + +assign sub_ln703_545_fu_5138_p2 = (sub_ln703_526_reg_11864 - data_38_V_read_3_reg_9328_pp0_iter11_reg); + +assign sub_ln703_546_fu_5142_p2 = (sub_ln703_527_reg_11869 - data_38_V_read_3_reg_9328_pp0_iter11_reg); + +assign sub_ln703_547_fu_5146_p2 = (add_ln703_647_reg_11874 - data_38_V_read_3_reg_9328_pp0_iter11_reg); + +assign sub_ln703_548_fu_5154_p2 = (sub_ln703_532_reg_11884 - data_38_V_read_3_reg_9328_pp0_iter11_reg); + +assign sub_ln703_549_fu_5158_p2 = (add_ln703_648_reg_11889 - data_38_V_read_3_reg_9328_pp0_iter11_reg); + +assign sub_ln703_54_fu_1086_p2 = (add_ln703_153_reg_10503 - data_7_V_read_9_reg_10191_pp0_iter4_reg); + +assign sub_ln703_550_fu_5162_p2 = (sub_ln703_533_reg_11894 - data_38_V_read_3_reg_9328_pp0_iter11_reg); + +assign sub_ln703_551_fu_5004_p2 = (add_ln703_649_fu_4914_p2 - data_38_V_read_3_reg_9328_pp0_iter10_reg); + +assign sub_ln703_552_fu_5170_p2 = (sub_ln703_539_reg_11909 - data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign sub_ln703_553_fu_5174_p2 = (sub_ln703_540_reg_11914 - data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign sub_ln703_554_fu_5178_p2 = (sub_ln703_542_reg_11924 - data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign sub_ln703_555_fu_5182_p2 = (add_ln703_651_reg_11929 - data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign sub_ln703_556_fu_5024_p2 = (add_ln703_656_fu_4973_p2 - data_39_V_read_3_reg_9301_pp0_iter10_reg); + +assign sub_ln703_557_fu_5029_p2 = (sub_ln703_543_fu_4979_p2 - data_39_V_read_3_reg_9301_pp0_iter10_reg); + +assign sub_ln703_558_fu_5034_p2 = (add_ln703_658_fu_4989_p2 - data_39_V_read_3_reg_9301_pp0_iter10_reg); + +assign sub_ln703_559_fu_5190_p2 = (sub_ln703_546_fu_5142_p2 - data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign sub_ln703_55_fu_1090_p2 = (sub_ln703_38_reg_10508 - data_7_V_read_9_reg_10191_pp0_iter4_reg); + +assign sub_ln703_560_fu_5195_p2 = (sub_ln703_547_fu_5146_p2 - data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign sub_ln703_561_fu_5200_p2 = (add_ln703_659_fu_5150_p2 - data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign sub_ln703_562_fu_5205_p2 = (add_ln703_660_reg_11939 - data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign sub_ln703_563_fu_5209_p2 = (sub_ln703_548_fu_5154_p2 - data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign sub_ln703_564_fu_5214_p2 = (sub_ln703_550_fu_5162_p2 - data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign sub_ln703_565_fu_5219_p2 = (add_ln703_661_reg_11944 - data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign sub_ln703_566_fu_5223_p2 = (sub_ln703_551_reg_11949 - data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign sub_ln703_567_fu_5227_p2 = (add_ln703_662_fu_5166_p2 - data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign sub_ln703_568_fu_5232_p2 = (add_ln703_666_reg_11954 - data_39_V_read_3_reg_9301_pp0_iter11_reg); + +assign sub_ln703_569_fu_5236_p2 = (add_ln703_668_reg_11959 - data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign sub_ln703_56_fu_1094_p2 = (sub_ln703_39_reg_10513 - data_7_V_read_9_reg_10191_pp0_iter4_reg); + +assign sub_ln703_570_fu_5263_p2 = (sub_ln703_557_reg_11969 - data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign sub_ln703_571_fu_5267_p2 = (add_ln703_669_fu_5186_p2 - data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign sub_ln703_572_fu_5276_p2 = (sub_ln703_560_fu_5195_p2 - data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign sub_ln703_573_fu_5101_p2 = (add_ln703_671_fu_5039_p2 - data_40_V_read41_reg_9272_pp0_iter10_reg); + +assign sub_ln703_574_fu_5290_p2 = (sub_ln703_562_fu_5205_p2 - data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign sub_ln703_575_fu_5295_p2 = (add_ln703_676_reg_11979 - data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign sub_ln703_576_fu_5299_p2 = (sub_ln703_564_fu_5214_p2 - data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign sub_ln703_577_fu_5304_p2 = (add_ln703_682_reg_11984 - data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign sub_ln703_578_fu_5308_p2 = (sub_ln703_565_fu_5219_p2 - data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign sub_ln703_579_fu_5318_p2 = (sub_ln703_567_fu_5227_p2 - data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign sub_ln703_57_fu_1102_p2 = (sub_ln703_40_reg_10519 - data_7_V_read_9_reg_10191_pp0_iter4_reg); + +assign sub_ln703_580_fu_5323_p2 = (sub_ln703_568_fu_5232_p2 - data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign sub_ln703_581_fu_5328_p2 = (add_ln703_685_reg_11989 - data_40_V_read41_reg_9272_pp0_iter11_reg); + +assign sub_ln703_582_fu_5106_p2 = (add_ln703_687_fu_5082_p2 - data_40_V_read41_reg_9272_pp0_iter10_reg); + +assign sub_ln703_583_fu_5111_p2 = (add_ln703_689_fu_5087_p2 - data_40_V_read41_reg_9272_pp0_iter10_reg); + +assign sub_ln703_584_fu_5341_p2 = (sub_ln703_569_fu_5236_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_585_fu_5346_p2 = (add_ln703_690_fu_5240_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_586_fu_5351_p2 = (add_ln703_692_fu_5245_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_587_fu_5356_p2 = (add_ln703_693_fu_5249_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_588_fu_5370_p2 = (add_ln703_694_fu_5254_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_589_fu_5375_p2 = (add_ln703_695_fu_5259_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_58_fu_922_p2 = (sub_ln703_41_fu_829_p2 - data_7_V_read_9_reg_10191_pp0_iter3_reg); + +assign sub_ln703_590_fu_5380_p2 = (sub_ln703_570_fu_5263_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_591_fu_5385_p2 = (sub_ln703_571_fu_5267_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_592_fu_5400_p2 = (add_ln703_696_fu_5272_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_593_fu_5410_p2 = (sub_ln703_572_fu_5276_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_594_fu_5415_p2 = (add_ln703_699_fu_5281_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_595_fu_5420_p2 = (add_ln703_700_fu_5285_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_596_fu_5444_p2 = (sub_ln703_577_fu_5304_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_597_fu_5449_p2 = (add_ln703_701_fu_5313_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_598_fu_5454_p2 = (sub_ln703_579_fu_5318_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_599_fu_5459_p2 = (sub_ln703_580_fu_5323_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_59_fu_1106_p2 = (sub_ln703_43_reg_10524 - data_7_V_read_9_reg_10191_pp0_iter4_reg); + +assign sub_ln703_5_fu_564_p2 = (data_2_V_read_10_reg_10312_pp0_iter1_reg - add_ln703_reg_10335_pp0_iter1_reg); + +assign sub_ln703_600_fu_5464_p2 = (sub_ln703_581_fu_5328_p2 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_601_fu_5473_p2 = (sub_ln703_583_reg_12017 - data_41_V_read42_reg_9242_pp0_iter11_reg); + +assign sub_ln703_602_fu_5688_p2 = (add_ln703_704_reg_12056 - data_42_V_read_3_reg_9212_pp0_iter12_reg); + +assign sub_ln703_603_fu_5491_p2 = (sub_ln703_587_fu_5356_p2 - data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign sub_ln703_604_fu_5496_p2 = (add_ln703_709_fu_5365_p2 - data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign sub_ln703_605_fu_5501_p2 = (sub_ln703_588_fu_5370_p2 - data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign sub_ln703_606_fu_5696_p2 = (sub_ln703_589_reg_12066 - data_42_V_read_3_reg_9212_pp0_iter12_reg); + +assign sub_ln703_607_fu_5506_p2 = (sub_ln703_590_fu_5380_p2 - data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign sub_ln703_608_fu_5511_p2 = (sub_ln703_591_fu_5385_p2 - data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign sub_ln703_609_fu_5516_p2 = (add_ln703_712_fu_5395_p2 - data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign sub_ln703_60_fu_927_p2 = (add_ln703_154_fu_843_p2 - data_7_V_read_9_reg_10191_pp0_iter3_reg); + +assign sub_ln703_610_fu_5521_p2 = (add_ln703_714_fu_5405_p2 - data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign sub_ln703_611_fu_5704_p2 = (sub_ln703_594_reg_12076 - data_42_V_read_3_reg_9212_pp0_iter12_reg); + +assign sub_ln703_612_fu_5526_p2 = (add_ln703_715_fu_5425_p2 - data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign sub_ln703_613_fu_5531_p2 = (add_ln703_716_fu_5429_p2 - data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign sub_ln703_614_fu_5536_p2 = (add_ln703_718_fu_5434_p2 - data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign sub_ln703_615_fu_5708_p2 = (add_ln703_719_reg_12086 - data_42_V_read_3_reg_9212_pp0_iter12_reg); + +assign sub_ln703_616_fu_5712_p2 = (sub_ln703_598_reg_12091 - data_42_V_read_3_reg_9212_pp0_iter12_reg); + +assign sub_ln703_617_fu_5561_p2 = (sub_ln703_600_fu_5464_p2 - data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign sub_ln703_618_fu_5566_p2 = (add_ln703_720_fu_5469_p2 - data_42_V_read_3_reg_9212_pp0_iter11_reg); + +assign sub_ln703_619_fu_5716_p2 = (sub_ln703_602_fu_5688_p2 - data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign sub_ln703_61_fu_932_p2 = (sub_ln703_44_fu_848_p2 - data_7_V_read_9_reg_10191_pp0_iter3_reg); + +assign sub_ln703_620_fu_5721_p2 = (add_ln703_721_fu_5692_p2 - data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign sub_ln703_621_fu_5726_p2 = (add_ln703_728_reg_12096 - data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign sub_ln703_622_fu_5730_p2 = (sub_ln703_603_reg_12101 - data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign sub_ln703_623_fu_5734_p2 = (sub_ln703_604_reg_12106 - data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign sub_ln703_624_fu_5596_p2 = (sub_ln703_607_fu_5506_p2 - data_43_V_read_3_reg_9184_pp0_iter11_reg); + +assign sub_ln703_625_fu_5742_p2 = (sub_ln703_609_reg_12121 - data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign sub_ln703_626_fu_5746_p2 = (sub_ln703_610_reg_12126 - data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign sub_ln703_627_fu_5750_p2 = (add_ln703_729_fu_5700_p2 - data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign sub_ln703_628_fu_5755_p2 = (sub_ln703_613_reg_12136 - data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign sub_ln703_629_fu_5763_p2 = (sub_ln703_615_fu_5708_p2 - data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign sub_ln703_62_fu_942_p2 = (add_ln703_156_fu_872_p2 - data_7_V_read_9_reg_10191_pp0_iter3_reg); + +assign sub_ln703_630_fu_5627_p2 = (add_ln703_730_fu_5541_p2 - data_43_V_read_3_reg_9184_pp0_iter11_reg); + +assign sub_ln703_631_fu_5632_p2 = (add_ln703_732_fu_5546_p2 - data_43_V_read_3_reg_9184_pp0_iter11_reg); + +assign sub_ln703_632_fu_5768_p2 = (add_ln703_733_reg_12146 - data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign sub_ln703_633_fu_5772_p2 = (add_ln703_734_reg_12151 - data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign sub_ln703_634_fu_5637_p2 = (sub_ln703_617_fu_5561_p2 - data_43_V_read_3_reg_9184_pp0_iter11_reg); + +assign sub_ln703_635_fu_5780_p2 = (add_ln703_735_reg_12161 - data_43_V_read_3_reg_9184_pp0_iter12_reg); + +assign sub_ln703_636_fu_5784_p2 = (sub_ln703_619_fu_5716_p2 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_637_fu_5642_p2 = (add_ln703_739_fu_5585_p2 - data_44_V_read_3_reg_9154_pp0_iter11_reg); + +assign sub_ln703_638_fu_5647_p2 = (add_ln703_741_fu_5591_p2 - data_44_V_read_3_reg_9154_pp0_iter11_reg); + +assign sub_ln703_639_fu_5789_p2 = (sub_ln703_620_fu_5721_p2 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_63_fu_947_p2 = (sub_ln703_48_fu_877_p2 - data_7_V_read_9_reg_10191_pp0_iter3_reg); + +assign sub_ln703_640_fu_5794_p2 = (sub_ln703_622_fu_5730_p2 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_641_fu_5799_p2 = (sub_ln703_623_fu_5734_p2 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_642_fu_5804_p2 = (add_ln703_742_fu_5738_p2 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_643_fu_5822_p2 = (sub_ln703_625_fu_5742_p2 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_644_fu_5656_p2 = (add_ln703_744_fu_5601_p2 - data_44_V_read_3_reg_9154_pp0_iter11_reg); + +assign sub_ln703_645_fu_5827_p2 = (sub_ln703_626_fu_5746_p2 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_646_fu_5832_p2 = (sub_ln703_627_fu_5750_p2 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_647_fu_5846_p2 = (sub_ln703_628_fu_5755_p2 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_648_fu_5661_p2 = (add_ln703_747_fu_5611_p2 - data_44_V_read_3_reg_9154_pp0_iter11_reg); + +assign sub_ln703_649_fu_5851_p2 = (add_ln703_748_fu_5759_p2 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_64_fu_957_p2 = (sub_ln703_49_fu_882_p2 - data_7_V_read_9_reg_10191_pp0_iter3_reg); + +assign sub_ln703_650_fu_5666_p2 = (add_ln703_753_fu_5621_p2 - data_44_V_read_3_reg_9154_pp0_iter11_reg); + +assign sub_ln703_651_fu_5856_p2 = (sub_ln703_629_fu_5763_p2 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_652_fu_5865_p2 = (sub_ln703_632_fu_5768_p2 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_653_fu_5870_p2 = (sub_ln703_633_fu_5772_p2 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_654_fu_5875_p2 = (sub_ln703_634_reg_12181 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_655_fu_5879_p2 = (add_ln703_754_fu_5776_p2 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_656_fu_5884_p2 = (sub_ln703_635_fu_5780_p2 - data_44_V_read_3_reg_9154_pp0_iter12_reg); + +assign sub_ln703_657_fu_5889_p2 = (sub_ln703_638_reg_12191 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_658_fu_5898_p2 = (sub_ln703_640_fu_5794_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_659_fu_5903_p2 = (sub_ln703_642_fu_5804_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_65_fu_1110_p2 = (add_ln703_157_reg_10529 - data_7_V_read_9_reg_10191_pp0_iter4_reg); + +assign sub_ln703_660_fu_5908_p2 = (add_ln703_756_fu_5809_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_661_fu_5913_p2 = (add_ln703_757_fu_5814_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_662_fu_5918_p2 = (add_ln703_759_fu_5818_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_663_fu_5923_p2 = (sub_ln703_643_fu_5822_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_664_fu_5928_p2 = (sub_ln703_644_reg_12204 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_665_fu_5932_p2 = (sub_ln703_646_fu_5832_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_666_fu_5937_p2 = (add_ln703_761_fu_5837_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_667_fu_5956_p2 = (add_ln703_763_fu_5842_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_668_fu_5971_p2 = (sub_ln703_650_reg_12214 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_669_fu_5975_p2 = (sub_ln703_651_fu_5856_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_66_fu_987_p2 = (add_ln703_160_fu_902_p2 - data_7_V_read_9_reg_10191_pp0_iter3_reg); + +assign sub_ln703_670_fu_5980_p2 = (add_ln703_764_fu_5861_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_671_fu_5989_p2 = (sub_ln703_652_fu_5865_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_672_fu_6004_p2 = (sub_ln703_653_fu_5870_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_673_fu_6009_p2 = (sub_ln703_654_fu_5875_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_674_fu_6014_p2 = (sub_ln703_655_fu_5879_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_675_fu_6019_p2 = (sub_ln703_656_fu_5884_p2 - data_45_V_read_3_reg_9125_pp0_iter12_reg); + +assign sub_ln703_676_fu_6033_p2 = (sub_ln703_657_fu_5889_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_677_fu_6047_p2 = (add_ln703_766_fu_5893_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_678_fu_6052_p2 = (sub_ln703_658_fu_5898_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_679_fu_6057_p2 = (sub_ln703_659_fu_5903_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_67_fu_1119_p2 = (add_ln703_162_reg_10539 - data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign sub_ln703_680_fu_6062_p2 = (sub_ln703_660_fu_5908_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_681_fu_6238_p2 = (sub_ln703_662_reg_12248 - data_46_V_read_3_reg_9094_pp0_iter13_reg); + +assign sub_ln703_682_fu_6067_p2 = (sub_ln703_664_fu_5928_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_683_fu_6242_p2 = (sub_ln703_665_reg_12253 - data_46_V_read_3_reg_9094_pp0_iter13_reg); + +assign sub_ln703_684_fu_6072_p2 = (sub_ln703_666_fu_5937_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_685_fu_6246_p2 = (add_ln703_770_reg_12258 - data_46_V_read_3_reg_9094_pp0_iter13_reg); + +assign sub_ln703_686_fu_6077_p2 = (add_ln703_771_fu_5961_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_687_fu_6086_p2 = (add_ln703_772_fu_5966_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_688_fu_6091_p2 = (sub_ln703_668_fu_5971_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_689_fu_6096_p2 = (sub_ln703_670_fu_5980_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_68_fu_1133_p2 = (add_ln703_163_fu_1098_p2 - data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign sub_ln703_690_fu_6101_p2 = (add_ln703_774_fu_5985_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_691_fu_6106_p2 = (sub_ln703_671_fu_5989_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_692_fu_6111_p2 = (add_ln703_777_fu_5999_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_693_fu_6116_p2 = (sub_ln703_672_fu_6004_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_694_fu_6126_p2 = (sub_ln703_674_fu_6014_p2 - data_46_V_read_3_reg_9094_pp0_iter12_reg); + +assign sub_ln703_695_fu_6254_p2 = (add_ln703_779_reg_12273 - data_47_V_read_3_reg_9066_pp0_iter13_reg); + +assign sub_ln703_696_fu_6136_p2 = (add_ln703_781_fu_6029_p2 - data_47_V_read_3_reg_9066_pp0_iter12_reg); + +assign sub_ln703_697_fu_6141_p2 = (add_ln703_786_fu_6042_p2 - data_47_V_read_3_reg_9066_pp0_iter12_reg); + +assign sub_ln703_698_fu_6267_p2 = (sub_ln703_682_reg_12298 - data_47_V_read_3_reg_9066_pp0_iter13_reg); + +assign sub_ln703_699_fu_6271_p2 = (sub_ln703_683_fu_6242_p2 - data_47_V_read_3_reg_9066_pp0_iter13_reg); + +assign sub_ln703_69_fu_1138_p2 = (sub_ln703_57_fu_1102_p2 - data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign sub_ln703_6_fu_595_p2 = (sub_ln703_2_reg_10367 - data_3_V_read_10_reg_10295_pp0_iter2_reg); + +assign sub_ln703_700_fu_6172_p2 = (add_ln703_788_fu_6082_p2 - data_47_V_read_3_reg_9066_pp0_iter12_reg); + +assign sub_ln703_701_fu_6281_p2 = (sub_ln703_687_reg_12313 - data_47_V_read_3_reg_9066_pp0_iter13_reg); + +assign sub_ln703_702_fu_6285_p2 = (sub_ln703_688_reg_12318 - data_47_V_read_3_reg_9066_pp0_iter13_reg); + +assign sub_ln703_703_fu_6289_p2 = (add_ln703_789_fu_6250_p2 - data_47_V_read_3_reg_9066_pp0_iter13_reg); + +assign sub_ln703_704_fu_6177_p2 = (sub_ln703_689_fu_6096_p2 - data_47_V_read_3_reg_9066_pp0_iter12_reg); + +assign sub_ln703_705_fu_6294_p2 = (sub_ln703_691_reg_12328 - data_47_V_read_3_reg_9066_pp0_iter13_reg); + +assign sub_ln703_706_fu_6298_p2 = (sub_ln703_693_reg_12338 - data_47_V_read_3_reg_9066_pp0_iter13_reg); + +assign sub_ln703_707_fu_6182_p2 = (add_ln703_790_fu_6121_p2 - data_47_V_read_3_reg_9066_pp0_iter12_reg); + +assign sub_ln703_708_fu_6302_p2 = (add_ln703_791_reg_12348 - data_47_V_read_3_reg_9066_pp0_iter13_reg); + +assign sub_ln703_709_fu_6306_p2 = (sub_ln703_695_fu_6254_p2 - data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign sub_ln703_70_fu_992_p2 = (sub_ln703_60_fu_927_p2 - data_8_V_read_8_reg_10164_pp0_iter3_reg); + +assign sub_ln703_710_fu_6311_p2 = (sub_ln703_696_reg_12353 - data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign sub_ln703_711_fu_6328_p2 = (add_ln703_792_reg_12363 - data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign sub_ln703_712_fu_6332_p2 = (add_ln703_793_fu_6258_p2 - data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign sub_ln703_713_fu_6337_p2 = (add_ln703_796_reg_12368 - data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign sub_ln703_714_fu_6345_p2 = (add_ln703_797_fu_6262_p2 - data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign sub_ln703_715_fu_6350_p2 = (add_ln703_798_reg_12373 - data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign sub_ln703_716_fu_6354_p2 = (sub_ln703_698_fu_6267_p2 - data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign sub_ln703_717_fu_6364_p2 = (add_ln703_799_fu_6276_p2 - data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign sub_ln703_718_fu_6382_p2 = (sub_ln703_700_reg_12378 - data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign sub_ln703_719_fu_6386_p2 = (sub_ln703_701_fu_6281_p2 - data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign sub_ln703_71_fu_1002_p2 = (add_ln703_164_fu_937_p2 - data_8_V_read_8_reg_10164_pp0_iter3_reg); + +assign sub_ln703_720_fu_6391_p2 = (sub_ln703_702_fu_6285_p2 - data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign sub_ln703_721_fu_6413_p2 = (sub_ln703_707_reg_12388 - data_48_V_read_3_reg_9040_pp0_iter13_reg); + +assign sub_ln703_722_fu_6422_p2 = (sub_ln703_709_fu_6306_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_723_fu_6427_p2 = (add_ln703_800_fu_6315_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_724_fu_6432_p2 = (add_ln703_804_fu_6323_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_725_fu_6437_p2 = (sub_ln703_713_fu_6337_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_726_fu_6442_p2 = (add_ln703_805_fu_6341_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_727_fu_6452_p2 = (sub_ln703_715_fu_6350_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_728_fu_6457_p2 = (add_ln703_806_fu_6359_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_729_fu_6462_p2 = (add_ln703_808_fu_6373_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_72_fu_1147_p2 = (sub_ln703_63_reg_10555 - data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign sub_ln703_730_fu_6467_p2 = (add_ln703_809_fu_6378_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_731_fu_6472_p2 = (sub_ln703_718_fu_6382_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_732_fu_6477_p2 = (sub_ln703_719_fu_6386_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_733_fu_6487_p2 = (add_ln703_810_fu_6396_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_734_fu_6492_p2 = (add_ln703_811_fu_6401_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_735_fu_6497_p2 = (add_ln703_812_fu_6405_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_736_fu_6502_p2 = (add_ln703_813_fu_6409_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_737_fu_6507_p2 = (sub_ln703_721_fu_6413_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_738_fu_6521_p2 = (add_ln703_814_fu_6417_p2 - data_49_V_read_3_reg_9012_pp0_iter13_reg); + +assign sub_ln703_739_fu_6541_p2 = (sub_ln703_725_fu_6437_p2 - data_50_V_read51_reg_8984_pp0_iter13_reg); + +assign sub_ln703_73_fu_1026_p2 = (add_ln703_165_fu_952_p2 - data_8_V_read_8_reg_10164_pp0_iter3_reg); + +assign sub_ln703_740_fu_6560_p2 = (sub_ln703_726_fu_6442_p2 - data_50_V_read51_reg_8984_pp0_iter13_reg); + +assign sub_ln703_741_fu_6795_p2 = (add_ln703_818_reg_12409_pp0_iter14_reg - data_50_V_read51_reg_8984_pp0_iter14_reg); + +assign sub_ln703_742_fu_6799_p2 = (add_ln703_819_reg_12455 - data_50_V_read51_reg_8984_pp0_iter14_reg); + +assign sub_ln703_743_fu_6803_p2 = (sub_ln703_727_reg_12460 - data_50_V_read51_reg_8984_pp0_iter14_reg); + +assign sub_ln703_744_fu_6565_p2 = (add_ln703_821_reg_12414 - data_50_V_read51_reg_8984_pp0_iter13_reg); + +assign sub_ln703_745_fu_6807_p2 = (sub_ln703_728_reg_12465 - data_50_V_read51_reg_8984_pp0_iter14_reg); + +assign sub_ln703_746_fu_6579_p2 = (sub_ln703_729_fu_6462_p2 - data_50_V_read51_reg_8984_pp0_iter13_reg); + +assign sub_ln703_747_fu_6584_p2 = (sub_ln703_730_fu_6467_p2 - data_50_V_read51_reg_8984_pp0_iter13_reg); + +assign sub_ln703_748_fu_6589_p2 = (sub_ln703_731_fu_6472_p2 - data_50_V_read51_reg_8984_pp0_iter13_reg); + +assign sub_ln703_749_fu_6599_p2 = (add_ln703_822_fu_6482_p2 - data_50_V_read51_reg_8984_pp0_iter13_reg); + +assign sub_ln703_74_fu_1151_p2 = (sub_ln703_64_reg_10560 - data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign sub_ln703_750_fu_6811_p2 = (sub_ln703_733_reg_12470 - data_50_V_read51_reg_8984_pp0_iter14_reg); + +assign sub_ln703_751_fu_6604_p2 = (sub_ln703_734_fu_6492_p2 - data_50_V_read51_reg_8984_pp0_iter13_reg); + +assign sub_ln703_752_fu_6609_p2 = (sub_ln703_735_fu_6497_p2 - data_50_V_read51_reg_8984_pp0_iter13_reg); + +assign sub_ln703_753_fu_6614_p2 = (sub_ln703_737_fu_6507_p2 - data_50_V_read51_reg_8984_pp0_iter13_reg); + +assign sub_ln703_754_fu_6619_p2 = (add_ln703_824_fu_6516_p2 - data_50_V_read51_reg_8984_pp0_iter13_reg); + +assign sub_ln703_755_fu_6819_p2 = (add_ln703_825_reg_12480 - data_51_V_read52_reg_8956_pp0_iter14_reg); + +assign sub_ln703_756_fu_6823_p2 = (add_ln703_827_reg_12485 - data_51_V_read52_reg_8956_pp0_iter14_reg); + +assign sub_ln703_757_fu_6629_p2 = (add_ln703_828_fu_6536_p2 - data_51_V_read52_reg_8956_pp0_iter13_reg); + +assign sub_ln703_758_fu_6827_p2 = (add_ln703_831_reg_12490 - data_51_V_read52_reg_8956_pp0_iter14_reg); + +assign sub_ln703_759_fu_6639_p2 = (sub_ln703_740_fu_6560_p2 - data_51_V_read52_reg_8956_pp0_iter13_reg); + +assign sub_ln703_75_fu_1031_p2 = (add_ln703_168_fu_967_p2 - data_8_V_read_8_reg_10164_pp0_iter3_reg); + +assign sub_ln703_760_fu_6831_p2 = (sub_ln703_741_fu_6795_p2 - data_51_V_read52_reg_8956_pp0_iter14_reg); + +assign sub_ln703_761_fu_6644_p2 = (sub_ln703_744_fu_6565_p2 - data_51_V_read52_reg_8956_pp0_iter13_reg); + +assign sub_ln703_762_fu_6841_p2 = (add_ln703_833_reg_12495 - data_51_V_read52_reg_8956_pp0_iter14_reg); + +assign sub_ln703_763_fu_6654_p2 = (sub_ln703_748_fu_6589_p2 - data_51_V_read52_reg_8956_pp0_iter13_reg); + +assign sub_ln703_764_fu_6845_p2 = (add_ln703_834_reg_12505 - data_51_V_read52_reg_8956_pp0_iter14_reg); + +assign sub_ln703_765_fu_6849_p2 = (sub_ln703_749_reg_12510 - data_51_V_read52_reg_8956_pp0_iter14_reg); + +assign sub_ln703_766_fu_6853_p2 = (sub_ln703_750_fu_6811_p2 - data_51_V_read52_reg_8956_pp0_iter14_reg); + +assign sub_ln703_767_fu_6659_p2 = (sub_ln703_751_fu_6604_p2 - data_51_V_read52_reg_8956_pp0_iter13_reg); + +assign sub_ln703_768_fu_6858_p2 = (add_ln703_835_fu_6815_p2 - data_51_V_read52_reg_8956_pp0_iter14_reg); + +assign sub_ln703_769_fu_6684_p2 = (sub_ln703_753_fu_6614_p2 - data_51_V_read52_reg_8956_pp0_iter13_reg); + +assign sub_ln703_76_fu_1155_p2 = (add_ln703_170_reg_10566 - data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign sub_ln703_770_fu_6708_p2 = (add_ln703_837_fu_6624_p2 - data_52_V_read_3_reg_8928_pp0_iter13_reg); + +assign sub_ln703_771_fu_6873_p2 = (add_ln703_838_reg_12520 - data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign sub_ln703_772_fu_6877_p2 = (sub_ln703_758_fu_6827_p2 - data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign sub_ln703_773_fu_6886_p2 = (sub_ln703_760_fu_6831_p2 - data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign sub_ln703_774_fu_6896_p2 = (add_ln703_839_fu_6836_p2 - data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign sub_ln703_775_fu_6910_p2 = (sub_ln703_762_fu_6841_p2 - data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign sub_ln703_776_fu_6915_p2 = (add_ln703_840_reg_12535 - data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign sub_ln703_777_fu_6928_p2 = (sub_ln703_765_fu_6849_p2 - data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign sub_ln703_778_fu_6933_p2 = (sub_ln703_766_fu_6853_p2 - data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign sub_ln703_779_fu_6938_p2 = (sub_ln703_767_reg_12545 - data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign sub_ln703_77_fu_1159_p2 = (sub_ln703_65_fu_1110_p2 - data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign sub_ln703_780_fu_6942_p2 = (add_ln703_841_reg_12550 - data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign sub_ln703_781_fu_6739_p2 = (add_ln703_844_fu_6678_p2 - data_52_V_read_3_reg_8928_pp0_iter13_reg); + +assign sub_ln703_782_fu_6946_p2 = (sub_ln703_769_reg_12555 - data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign sub_ln703_783_fu_6950_p2 = (add_ln703_845_reg_12560 - data_52_V_read_3_reg_8928_pp0_iter14_reg); + +assign sub_ln703_784_fu_6954_p2 = (add_ln703_846_fu_6863_p2 - data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign sub_ln703_785_fu_6959_p2 = (add_ln703_847_fu_6868_p2 - data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign sub_ln703_786_fu_6964_p2 = (add_ln703_851_reg_12565 - data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign sub_ln703_787_fu_6759_p2 = (add_ln703_854_fu_6722_p2 - data_53_V_read_3_reg_8899_pp0_iter13_reg); + +assign sub_ln703_788_fu_6981_p2 = (sub_ln703_772_fu_6877_p2 - data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign sub_ln703_789_fu_6986_p2 = (add_ln703_855_fu_6882_p2 - data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign sub_ln703_78_fu_1164_p2 = (add_ln703_171_reg_10571 - data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign sub_ln703_790_fu_6991_p2 = (add_ln703_856_fu_6891_p2 - data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign sub_ln703_791_fu_6996_p2 = (add_ln703_858_reg_12575 - data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign sub_ln703_792_fu_7000_p2 = (add_ln703_859_fu_6901_p2 - data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign sub_ln703_793_fu_7005_p2 = (add_ln703_860_fu_6905_p2 - data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign sub_ln703_794_fu_7010_p2 = (sub_ln703_775_fu_6910_p2 - data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign sub_ln703_795_fu_7015_p2 = (add_ln703_861_fu_6919_p2 - data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign sub_ln703_796_fu_7020_p2 = (add_ln703_862_fu_6923_p2 - data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign sub_ln703_797_fu_7030_p2 = (sub_ln703_778_fu_6933_p2 - data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign sub_ln703_798_fu_7035_p2 = (sub_ln703_779_fu_6938_p2 - data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign sub_ln703_799_fu_6764_p2 = (add_ln703_864_fu_6749_p2 - data_53_V_read_3_reg_8899_pp0_iter13_reg); + +assign sub_ln703_79_fu_1168_p2 = (add_ln703_173_reg_10576 - data_8_V_read_8_reg_10164_pp0_iter4_reg); + +assign sub_ln703_7_fu_607_p2 = (add_ln703_130_reg_10373 - data_3_V_read_10_reg_10295_pp0_iter2_reg); + +assign sub_ln703_800_fu_7045_p2 = (sub_ln703_783_fu_6950_p2 - data_53_V_read_3_reg_8899_pp0_iter14_reg); + +assign sub_ln703_801_fu_7060_p2 = (sub_ln703_786_fu_6964_p2 - data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign sub_ln703_802_fu_7065_p2 = (add_ln703_865_fu_6968_p2 - data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign sub_ln703_803_fu_7070_p2 = (add_ln703_869_fu_6976_p2 - data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign sub_ln703_804_fu_7075_p2 = (sub_ln703_787_reg_12590 - data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign sub_ln703_805_fu_7079_p2 = (sub_ln703_790_fu_6991_p2 - data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign sub_ln703_806_fu_7089_p2 = (sub_ln703_792_fu_7000_p2 - data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign sub_ln703_807_fu_7099_p2 = (sub_ln703_794_fu_7010_p2 - data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign sub_ln703_808_fu_7137_p2 = (add_ln703_870_fu_7025_p2 - data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign sub_ln703_809_fu_7165_p2 = (add_ln703_871_fu_7040_p2 - data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign sub_ln703_80_fu_1184_p2 = (add_ln703_174_fu_1114_p2 - data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign sub_ln703_810_fu_7170_p2 = (sub_ln703_800_fu_7045_p2 - data_54_V_read_3_reg_8873_pp0_iter14_reg); + +assign sub_ln703_811_fu_7346_p2 = (add_ln703_872_reg_12650 - data_55_V_read_3_reg_8844_pp0_iter15_reg); + +assign sub_ln703_812_fu_7350_p2 = (add_ln703_873_reg_12655 - data_55_V_read_3_reg_8844_pp0_iter15_reg); + +assign sub_ln703_813_fu_7370_p2 = (add_ln703_874_reg_12675 - data_55_V_read_3_reg_8844_pp0_iter15_reg); + +assign sub_ln703_814_fu_7200_p2 = (sub_ln703_806_fu_7089_p2 - data_55_V_read_3_reg_8844_pp0_iter14_reg); + +assign sub_ln703_815_fu_7374_p2 = (add_ln703_875_reg_12680 - data_55_V_read_3_reg_8844_pp0_iter15_reg); + +assign sub_ln703_816_fu_7205_p2 = (add_ln703_879_fu_7108_p2 - data_55_V_read_3_reg_8844_pp0_iter14_reg); + +assign sub_ln703_817_fu_7382_p2 = (add_ln703_882_reg_12690 - data_55_V_read_3_reg_8844_pp0_iter15_reg); + +assign sub_ln703_818_fu_7210_p2 = (add_ln703_883_fu_7127_p2 - data_55_V_read_3_reg_8844_pp0_iter14_reg); + +assign sub_ln703_819_fu_7386_p2 = (add_ln703_884_reg_12695 - data_55_V_read_3_reg_8844_pp0_iter15_reg); + +assign sub_ln703_81_fu_1194_p2 = (add_ln703_175_fu_1123_p2 - data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign sub_ln703_820_fu_7215_p2 = (add_ln703_885_fu_7142_p2 - data_55_V_read_3_reg_8844_pp0_iter14_reg); + +assign sub_ln703_821_fu_7220_p2 = (add_ln703_886_fu_7147_p2 - data_55_V_read_3_reg_8844_pp0_iter14_reg); + +assign sub_ln703_822_fu_7398_p2 = (add_ln703_888_reg_12705 - data_55_V_read_3_reg_8844_pp0_iter15_reg); + +assign sub_ln703_823_fu_7225_p2 = (add_ln703_889_fu_7161_p2 - data_55_V_read_3_reg_8844_pp0_iter14_reg); + +assign sub_ln703_824_fu_7230_p2 = (sub_ln703_809_fu_7165_p2 - data_55_V_read_3_reg_8844_pp0_iter14_reg); + +assign sub_ln703_825_fu_7235_p2 = (sub_ln703_810_fu_7170_p2 - data_55_V_read_3_reg_8844_pp0_iter14_reg); + +assign sub_ln703_826_fu_7407_p2 = (sub_ln703_812_fu_7350_p2 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_827_fu_7412_p2 = (add_ln703_890_fu_7354_p2 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_828_fu_7417_p2 = (add_ln703_891_fu_7358_p2 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_829_fu_7422_p2 = (add_ln703_892_reg_12710 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_82_fu_1199_p2 = (add_ln703_176_fu_1128_p2 - data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign sub_ln703_830_fu_7426_p2 = (add_ln703_893_reg_12715 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_831_fu_7430_p2 = (add_ln703_895_reg_12720 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_832_fu_7434_p2 = (add_ln703_897_fu_7362_p2 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_833_fu_7439_p2 = (add_ln703_899_fu_7366_p2 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_834_fu_7444_p2 = (sub_ln703_813_fu_7370_p2 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_835_fu_7449_p2 = (sub_ln703_814_reg_12735 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_836_fu_7453_p2 = (sub_ln703_815_fu_7374_p2 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_837_fu_7458_p2 = (add_ln703_900_fu_7378_p2 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_838_fu_7463_p2 = (sub_ln703_818_reg_12745 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_839_fu_7467_p2 = (add_ln703_901_fu_7390_p2 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_83_fu_1218_p2 = (sub_ln703_70_reg_10586 - data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign sub_ln703_840_fu_7472_p2 = (add_ln703_902_fu_7394_p2 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_841_fu_7485_p2 = (sub_ln703_822_fu_7398_p2 - data_56_V_read_3_reg_8814_pp0_iter15_reg); + +assign sub_ln703_842_fu_7498_p2 = (add_ln703_903_fu_7402_p2 - data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign sub_ln703_843_fu_7503_p2 = (sub_ln703_826_fu_7407_p2 - data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign sub_ln703_844_fu_7508_p2 = (sub_ln703_827_fu_7412_p2 - data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign sub_ln703_845_fu_7518_p2 = (sub_ln703_829_fu_7422_p2 - data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign sub_ln703_846_fu_7523_p2 = (sub_ln703_831_fu_7430_p2 - data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign sub_ln703_847_fu_7528_p2 = (add_ln703_906_reg_12775 - data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign sub_ln703_848_fu_7551_p2 = (sub_ln703_834_fu_7444_p2 - data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign sub_ln703_849_fu_7556_p2 = (sub_ln703_836_fu_7453_p2 - data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign sub_ln703_84_fu_1222_p2 = (add_ln703_177_reg_10591 - data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign sub_ln703_850_fu_7566_p2 = (sub_ln703_839_fu_7467_p2 - data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign sub_ln703_851_fu_7571_p2 = (add_ln703_907_fu_7477_p2 - data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign sub_ln703_852_fu_7319_p2 = (add_ln703_910_fu_7259_p2 - data_57_V_read_3_reg_8786_pp0_iter14_reg); + +assign sub_ln703_853_fu_7576_p2 = (add_ln703_911_fu_7481_p2 - data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign sub_ln703_854_fu_7586_p2 = (add_ln703_912_fu_7490_p2 - data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign sub_ln703_855_fu_7591_p2 = (add_ln703_913_fu_7494_p2 - data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign sub_ln703_856_fu_7596_p2 = (add_ln703_917_reg_12780 - data_57_V_read_3_reg_8786_pp0_iter15_reg); + +assign sub_ln703_857_fu_7600_p2 = (sub_ln703_842_fu_7498_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_858_fu_7605_p2 = (sub_ln703_843_fu_7503_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_859_fu_7615_p2 = (add_ln703_918_fu_7513_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_85_fu_1230_p2 = (add_ln703_181_reg_10601 - data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign sub_ln703_860_fu_7620_p2 = (sub_ln703_845_fu_7518_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_861_fu_7625_p2 = (add_ln703_922_reg_12785 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_862_fu_7324_p2 = (add_ln703_925_fu_7302_p2 - data_58_V_read_3_reg_8756_pp0_iter14_reg); + +assign sub_ln703_863_fu_7639_p2 = (add_ln703_926_fu_7532_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_864_fu_7644_p2 = (add_ln703_928_fu_7541_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_865_fu_7649_p2 = (add_ln703_929_fu_7546_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_866_fu_7654_p2 = (sub_ln703_848_fu_7551_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_867_fu_7669_p2 = (sub_ln703_849_fu_7556_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_868_fu_7674_p2 = (add_ln703_930_fu_7561_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_869_fu_7329_p2 = (add_ln703_932_fu_7313_p2 - data_58_V_read_3_reg_8756_pp0_iter14_reg); + +assign sub_ln703_86_fu_1234_p2 = (add_ln703_183_reg_10606 - data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign sub_ln703_870_fu_7685_p2 = (sub_ln703_850_fu_7566_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_871_fu_7696_p2 = (sub_ln703_851_fu_7571_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_872_fu_7705_p2 = (sub_ln703_853_fu_7576_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_873_fu_7710_p2 = (add_ln703_933_fu_7581_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_874_fu_7725_p2 = (sub_ln703_855_fu_7591_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_875_fu_7730_p2 = (sub_ln703_856_fu_7596_p2 - data_58_V_read_3_reg_8756_pp0_iter15_reg); + +assign sub_ln703_876_fu_7878_p2 = (sub_ln703_857_reg_12835 - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_877_fu_7886_p2 = (add_ln703_934_reg_12845 - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_878_fu_7890_p2 = (sub_ln703_859_reg_12850 - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_879_fu_7735_p2 = (sub_ln703_860_fu_7620_p2 - data_59_V_read_3_reg_8724_pp0_iter15_reg); + +assign sub_ln703_87_fu_1238_p2 = (add_ln703_184_fu_1143_p2 - data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign sub_ln703_880_fu_7750_p2 = (sub_ln703_861_fu_7625_p2 - data_59_V_read_3_reg_8724_pp0_iter15_reg); + +assign sub_ln703_881_fu_7755_p2 = (add_ln703_935_fu_7629_p2 - data_59_V_read_3_reg_8724_pp0_iter15_reg); + +assign sub_ln703_882_fu_7894_p2 = (add_ln703_936_reg_12855 - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_883_fu_7898_p2 = (sub_ln703_863_reg_12860 - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_884_fu_7902_p2 = (sub_ln703_865_reg_12865 - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_885_fu_7906_p2 = (sub_ln703_866_reg_12870 - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_886_fu_7910_p2 = (add_ln703_938_reg_12875 - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_887_fu_7914_p2 = (sub_ln703_867_reg_12880 - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_888_fu_7918_p2 = (sub_ln703_868_reg_12885 - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_889_fu_7922_p2 = (sub_ln703_869_reg_12800_pp0_iter16_reg - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_88_fu_1248_p2 = (sub_ln703_73_reg_10611 - data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign sub_ln703_890_fu_7926_p2 = (add_ln703_939_reg_12890 - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_891_fu_7930_p2 = (sub_ln703_870_reg_12895 - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_892_fu_7780_p2 = (add_ln703_940_fu_7690_p2 - data_59_V_read_3_reg_8724_pp0_iter15_reg); + +assign sub_ln703_893_fu_7785_p2 = (sub_ln703_871_fu_7696_p2 - data_59_V_read_3_reg_8724_pp0_iter15_reg); + +assign sub_ln703_894_fu_7790_p2 = (add_ln703_941_fu_7701_p2 - data_59_V_read_3_reg_8724_pp0_iter15_reg); + +assign sub_ln703_895_fu_7795_p2 = (sub_ln703_872_fu_7705_p2 - data_59_V_read_3_reg_8724_pp0_iter15_reg); + +assign sub_ln703_896_fu_7934_p2 = (sub_ln703_873_reg_12900 - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_897_fu_7938_p2 = (add_ln703_943_reg_12905 - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_898_fu_7805_p2 = (sub_ln703_874_fu_7725_p2 - data_59_V_read_3_reg_8724_pp0_iter15_reg); + +assign sub_ln703_899_fu_7942_p2 = (sub_ln703_875_reg_12910 - data_59_V_read_3_reg_8724_pp0_iter16_reg); + +assign sub_ln703_89_fu_1252_p2 = (sub_ln703_74_fu_1151_p2 - data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign sub_ln703_8_fu_572_p2 = (sub_ln703_4_reg_10361 - data_3_V_read_10_reg_10295_pp0_iter1_reg); + +assign sub_ln703_900_fu_7946_p2 = (sub_ln703_876_fu_7878_p2 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_901_fu_7951_p2 = (add_ln703_944_fu_7882_p2 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_902_fu_7961_p2 = (sub_ln703_878_fu_7890_p2 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_903_fu_7966_p2 = (sub_ln703_879_reg_12915 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_904_fu_7810_p2 = (add_ln703_947_fu_7745_p2 - data_60_V_read61_reg_8691_pp0_iter15_reg); + +assign sub_ln703_905_fu_7970_p2 = (sub_ln703_880_reg_12920 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_906_fu_7974_p2 = (sub_ln703_881_reg_12925 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_907_fu_7978_p2 = (sub_ln703_883_fu_7898_p2 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_908_fu_7983_p2 = (add_ln703_948_reg_12930 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_909_fu_7987_p2 = (sub_ln703_885_fu_7906_p2 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_90_fu_1257_p2 = (sub_ln703_75_reg_10616 - data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign sub_ln703_910_fu_7992_p2 = (sub_ln703_888_fu_7918_p2 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_911_fu_7833_p2 = (add_ln703_951_fu_7774_p2 - data_60_V_read61_reg_8691_pp0_iter15_reg); + +assign sub_ln703_912_fu_8002_p2 = (sub_ln703_890_fu_7926_p2 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_913_fu_8007_p2 = (sub_ln703_891_fu_7930_p2 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_914_fu_8020_p2 = (sub_ln703_894_reg_12945 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_915_fu_8024_p2 = (sub_ln703_895_reg_12950 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_916_fu_8028_p2 = (sub_ln703_896_fu_7934_p2 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_917_fu_7838_p2 = (add_ln703_952_fu_7800_p2 - data_60_V_read61_reg_8691_pp0_iter15_reg); + +assign sub_ln703_918_fu_8033_p2 = (sub_ln703_898_reg_12955 - data_60_V_read61_reg_8691_pp0_iter16_reg); + +assign sub_ln703_919_fu_8037_p2 = (add_ln703_953_fu_7956_p2 - data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign sub_ln703_91_fu_1261_p2 = (add_ln703_186_reg_10621 - data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign sub_ln703_920_fu_8042_p2 = (sub_ln703_902_fu_7961_p2 - data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign sub_ln703_921_fu_8047_p2 = (sub_ln703_903_fu_7966_p2 - data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign sub_ln703_922_fu_7843_p2 = (add_ln703_955_fu_7815_p2 - data_61_V_read62_reg_8663_pp0_iter15_reg); + +assign sub_ln703_923_fu_8057_p2 = (sub_ln703_906_fu_7974_p2 - data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign sub_ln703_924_fu_8072_p2 = (add_ln703_958_reg_12965 - data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign sub_ln703_925_fu_8076_p2 = (sub_ln703_911_reg_12970 - data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign sub_ln703_926_fu_8080_p2 = (add_ln703_959_fu_7997_p2 - data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign sub_ln703_927_fu_8085_p2 = (sub_ln703_913_fu_8007_p2 - data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign sub_ln703_928_fu_8090_p2 = (add_ln703_960_fu_8012_p2 - data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign sub_ln703_929_fu_8095_p2 = (add_ln703_961_fu_8016_p2 - data_61_V_read62_reg_8663_pp0_iter16_reg); + +assign sub_ln703_92_fu_1054_p2 = (add_ln703_189_fu_1045_p2 - data_9_V_read_8_reg_10136_pp0_iter3_reg); + +assign sub_ln703_930_fu_8120_p2 = (sub_ln703_921_fu_8047_p2 - data_62_V_read_3_reg_8645_pp0_iter16_reg); + +assign sub_ln703_931_fu_8134_p2 = (add_ln703_962_fu_8052_p2 - data_62_V_read_3_reg_8645_pp0_iter16_reg); + +assign sub_ln703_932_fu_8139_p2 = (sub_ln703_922_reg_12980 - data_62_V_read_3_reg_8645_pp0_iter16_reg); + +assign sub_ln703_933_fu_8143_p2 = (sub_ln703_923_fu_8057_p2 - data_62_V_read_3_reg_8645_pp0_iter16_reg); + +assign sub_ln703_934_fu_8165_p2 = (add_ln703_963_fu_8062_p2 - data_62_V_read_3_reg_8645_pp0_iter16_reg); + +assign sub_ln703_935_fu_8181_p2 = (add_ln703_965_fu_8067_p2 - data_62_V_read_3_reg_8645_pp0_iter16_reg); + +assign sub_ln703_936_fu_8209_p2 = (sub_ln703_928_fu_8090_p2 - data_62_V_read_3_reg_8645_pp0_iter16_reg); + +assign sub_ln703_937_fu_8219_p2 = (add_ln703_966_fu_8100_p2 - data_62_V_read_3_reg_8645_pp0_iter16_reg); + +assign sub_ln703_938_fu_8224_p2 = (add_ln703_967_fu_8105_p2 - data_62_V_read_3_reg_8645_pp0_iter16_reg); + +assign sub_ln703_939_fu_8229_p2 = (add_ln703_968_fu_8110_p2 - data_62_V_read_3_reg_8645_pp0_iter16_reg); + +assign sub_ln703_93_fu_1275_p2 = (sub_ln703_79_fu_1168_p2 - data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign sub_ln703_940_fu_8234_p2 = (add_ln703_969_fu_8115_p2 - data_62_V_read_3_reg_8645_pp0_iter16_reg); + +assign sub_ln703_94_fu_1280_p2 = (add_ln703_190_fu_1172_p2 - data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign sub_ln703_95_fu_1285_p2 = (add_ln703_191_fu_1176_p2 - data_9_V_read_8_reg_10136_pp0_iter4_reg); + +assign sub_ln703_96_fu_1294_p2 = (add_ln703_193_fu_1180_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_97_fu_1304_p2 = (add_ln703_194_fu_1189_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_98_fu_1319_p2 = (add_ln703_195_fu_1204_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_99_fu_1324_p2 = (add_ln703_197_fu_1209_p2 - data_10_V_read11_reg_10105_pp0_iter4_reg); + +assign sub_ln703_9_fu_611_p2 = (sub_ln703_3_reg_10379 - data_3_V_read_10_reg_10295_pp0_iter2_reg); + +assign sub_ln703_fu_536_p2 = (data_1_V_read_10_reg_10323 - data_0_V_read_10_reg_10329); + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0 ( + ap_clk, + ap_rst, + data_0_V_read, + data_1_V_read, + data_2_V_read, + data_3_V_read, + data_4_V_read, + data_5_V_read, + data_6_V_read, + data_7_V_read, + data_8_V_read, + data_9_V_read, + data_10_V_read, + data_11_V_read, + data_12_V_read, + data_13_V_read, + data_14_V_read, + data_15_V_read, + data_16_V_read, + data_17_V_read, + data_18_V_read, + data_19_V_read, + data_20_V_read, + data_21_V_read, + data_22_V_read, + data_23_V_read, + data_24_V_read, + data_25_V_read, + data_26_V_read, + data_27_V_read, + data_28_V_read, + data_29_V_read, + data_30_V_read, + data_31_V_read, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3, + ap_return_4, + ap_ce +); + + +input ap_clk; +input ap_rst; +input [15:0] data_0_V_read; +input [15:0] data_1_V_read; +input [15:0] data_2_V_read; +input [15:0] data_3_V_read; +input [15:0] data_4_V_read; +input [15:0] data_5_V_read; +input [15:0] data_6_V_read; +input [15:0] data_7_V_read; +input [15:0] data_8_V_read; +input [15:0] data_9_V_read; +input [15:0] data_10_V_read; +input [15:0] data_11_V_read; +input [15:0] data_12_V_read; +input [15:0] data_13_V_read; +input [15:0] data_14_V_read; +input [15:0] data_15_V_read; +input [15:0] data_16_V_read; +input [15:0] data_17_V_read; +input [15:0] data_18_V_read; +input [15:0] data_19_V_read; +input [15:0] data_20_V_read; +input [15:0] data_21_V_read; +input [15:0] data_22_V_read; +input [15:0] data_23_V_read; +input [15:0] data_24_V_read; +input [15:0] data_25_V_read; +input [15:0] data_26_V_read; +input [15:0] data_27_V_read; +input [15:0] data_28_V_read; +input [15:0] data_29_V_read; +input [15:0] data_30_V_read; +input [15:0] data_31_V_read; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; +output [15:0] ap_return_4; +input ap_ce; + +reg[15:0] ap_return_0; +reg[15:0] ap_return_1; +reg[15:0] ap_return_2; +reg[15:0] ap_return_3; +reg[15:0] ap_return_4; + +reg [15:0] data_31_V_read32_reg_989; +wire ap_block_state1_pp0_stage0_iter0; +wire ap_block_state2_pp0_stage0_iter1; +wire ap_block_state3_pp0_stage0_iter2; +wire ap_block_state4_pp0_stage0_iter3; +wire ap_block_state5_pp0_stage0_iter4; +wire ap_block_state6_pp0_stage0_iter5; +wire ap_block_state7_pp0_stage0_iter6; +wire ap_block_state8_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +reg [15:0] data_31_V_read32_reg_989_pp0_iter1_reg; +reg [15:0] data_31_V_read32_reg_989_pp0_iter2_reg; +reg [15:0] data_31_V_read32_reg_989_pp0_iter3_reg; +reg [15:0] data_31_V_read32_reg_989_pp0_iter4_reg; +reg [15:0] data_31_V_read32_reg_989_pp0_iter5_reg; +reg [15:0] data_31_V_read32_reg_989_pp0_iter6_reg; +reg [15:0] data_30_V_read31_reg_998; +reg [15:0] data_30_V_read31_reg_998_pp0_iter1_reg; +reg [15:0] data_30_V_read31_reg_998_pp0_iter2_reg; +reg [15:0] data_30_V_read31_reg_998_pp0_iter3_reg; +reg [15:0] data_30_V_read31_reg_998_pp0_iter4_reg; +reg [15:0] data_30_V_read31_reg_998_pp0_iter5_reg; +reg [15:0] data_30_V_read31_reg_998_pp0_iter6_reg; +reg [15:0] data_29_V_read_6_reg_1006; +reg [15:0] data_29_V_read_6_reg_1006_pp0_iter1_reg; +reg [15:0] data_29_V_read_6_reg_1006_pp0_iter2_reg; +reg [15:0] data_29_V_read_6_reg_1006_pp0_iter3_reg; +reg [15:0] data_29_V_read_6_reg_1006_pp0_iter4_reg; +reg [15:0] data_29_V_read_6_reg_1006_pp0_iter5_reg; +reg [15:0] data_29_V_read_6_reg_1006_pp0_iter6_reg; +reg [15:0] data_28_V_read_6_reg_1014; +reg [15:0] data_28_V_read_6_reg_1014_pp0_iter1_reg; +reg [15:0] data_28_V_read_6_reg_1014_pp0_iter2_reg; +reg [15:0] data_28_V_read_6_reg_1014_pp0_iter3_reg; +reg [15:0] data_28_V_read_6_reg_1014_pp0_iter4_reg; +reg [15:0] data_28_V_read_6_reg_1014_pp0_iter5_reg; +reg [15:0] data_28_V_read_6_reg_1014_pp0_iter6_reg; +reg [15:0] data_27_V_read_7_reg_1023; +reg [15:0] data_27_V_read_7_reg_1023_pp0_iter1_reg; +reg [15:0] data_27_V_read_7_reg_1023_pp0_iter2_reg; +reg [15:0] data_27_V_read_7_reg_1023_pp0_iter3_reg; +reg [15:0] data_27_V_read_7_reg_1023_pp0_iter4_reg; +reg [15:0] data_27_V_read_7_reg_1023_pp0_iter5_reg; +reg [15:0] data_26_V_read_7_reg_1032; +reg [15:0] data_26_V_read_7_reg_1032_pp0_iter1_reg; +reg [15:0] data_26_V_read_7_reg_1032_pp0_iter2_reg; +reg [15:0] data_26_V_read_7_reg_1032_pp0_iter3_reg; +reg [15:0] data_26_V_read_7_reg_1032_pp0_iter4_reg; +reg [15:0] data_26_V_read_7_reg_1032_pp0_iter5_reg; +reg [15:0] data_25_V_read26_reg_1041; +reg [15:0] data_25_V_read26_reg_1041_pp0_iter1_reg; +reg [15:0] data_25_V_read26_reg_1041_pp0_iter2_reg; +reg [15:0] data_25_V_read26_reg_1041_pp0_iter3_reg; +reg [15:0] data_25_V_read26_reg_1041_pp0_iter4_reg; +reg [15:0] data_25_V_read26_reg_1041_pp0_iter5_reg; +reg [15:0] data_24_V_read25_reg_1050; +reg [15:0] data_24_V_read25_reg_1050_pp0_iter1_reg; +reg [15:0] data_24_V_read25_reg_1050_pp0_iter2_reg; +reg [15:0] data_24_V_read25_reg_1050_pp0_iter3_reg; +reg [15:0] data_24_V_read25_reg_1050_pp0_iter4_reg; +reg [15:0] data_24_V_read25_reg_1050_pp0_iter5_reg; +reg [15:0] data_23_V_read24_reg_1059; +reg [15:0] data_23_V_read24_reg_1059_pp0_iter1_reg; +reg [15:0] data_23_V_read24_reg_1059_pp0_iter2_reg; +reg [15:0] data_23_V_read24_reg_1059_pp0_iter3_reg; +reg [15:0] data_23_V_read24_reg_1059_pp0_iter4_reg; +reg [15:0] data_22_V_read23_reg_1068; +reg [15:0] data_22_V_read23_reg_1068_pp0_iter1_reg; +reg [15:0] data_22_V_read23_reg_1068_pp0_iter2_reg; +reg [15:0] data_22_V_read23_reg_1068_pp0_iter3_reg; +reg [15:0] data_22_V_read23_reg_1068_pp0_iter4_reg; +reg [15:0] data_22_V_read23_reg_1068_pp0_iter5_reg; +reg [15:0] data_21_V_read22_reg_1077; +reg [15:0] data_21_V_read22_reg_1077_pp0_iter1_reg; +reg [15:0] data_21_V_read22_reg_1077_pp0_iter2_reg; +reg [15:0] data_21_V_read22_reg_1077_pp0_iter3_reg; +reg [15:0] data_21_V_read22_reg_1077_pp0_iter4_reg; +reg [15:0] data_20_V_read21_reg_1086; +reg [15:0] data_20_V_read21_reg_1086_pp0_iter1_reg; +reg [15:0] data_20_V_read21_reg_1086_pp0_iter2_reg; +reg [15:0] data_20_V_read21_reg_1086_pp0_iter3_reg; +reg [15:0] data_20_V_read21_reg_1086_pp0_iter4_reg; +reg [15:0] data_19_V_read_6_reg_1095; +reg [15:0] data_19_V_read_6_reg_1095_pp0_iter1_reg; +reg [15:0] data_19_V_read_6_reg_1095_pp0_iter2_reg; +reg [15:0] data_19_V_read_6_reg_1095_pp0_iter3_reg; +reg [15:0] data_19_V_read_6_reg_1095_pp0_iter4_reg; +reg [15:0] data_18_V_read_6_reg_1103; +reg [15:0] data_18_V_read_6_reg_1103_pp0_iter1_reg; +reg [15:0] data_18_V_read_6_reg_1103_pp0_iter2_reg; +reg [15:0] data_18_V_read_6_reg_1103_pp0_iter3_reg; +reg [15:0] data_18_V_read_6_reg_1103_pp0_iter4_reg; +reg [15:0] data_17_V_read_7_reg_1111; +reg [15:0] data_17_V_read_7_reg_1111_pp0_iter1_reg; +reg [15:0] data_17_V_read_7_reg_1111_pp0_iter2_reg; +reg [15:0] data_17_V_read_7_reg_1111_pp0_iter3_reg; +reg [15:0] data_16_V_read_7_reg_1120; +reg [15:0] data_16_V_read_7_reg_1120_pp0_iter1_reg; +reg [15:0] data_16_V_read_7_reg_1120_pp0_iter2_reg; +reg [15:0] data_16_V_read_7_reg_1120_pp0_iter3_reg; +reg [15:0] data_15_V_read16_reg_1129; +reg [15:0] data_15_V_read16_reg_1129_pp0_iter1_reg; +reg [15:0] data_15_V_read16_reg_1129_pp0_iter2_reg; +reg [15:0] data_15_V_read16_reg_1129_pp0_iter3_reg; +reg [15:0] data_14_V_read15_reg_1138; +reg [15:0] data_14_V_read15_reg_1138_pp0_iter1_reg; +reg [15:0] data_14_V_read15_reg_1138_pp0_iter2_reg; +reg [15:0] data_14_V_read15_reg_1138_pp0_iter3_reg; +reg [15:0] data_13_V_read14_reg_1147; +reg [15:0] data_13_V_read14_reg_1147_pp0_iter1_reg; +reg [15:0] data_13_V_read14_reg_1147_pp0_iter2_reg; +reg [15:0] data_12_V_read13_reg_1156; +reg [15:0] data_12_V_read13_reg_1156_pp0_iter1_reg; +reg [15:0] data_12_V_read13_reg_1156_pp0_iter2_reg; +reg [15:0] data_11_V_read12_reg_1165; +reg [15:0] data_11_V_read12_reg_1165_pp0_iter1_reg; +reg [15:0] data_11_V_read12_reg_1165_pp0_iter2_reg; +reg [15:0] data_10_V_read11_reg_1174; +reg [15:0] data_10_V_read11_reg_1174_pp0_iter1_reg; +reg [15:0] data_10_V_read11_reg_1174_pp0_iter2_reg; +reg [15:0] data_9_V_read_6_reg_1183; +reg [15:0] data_9_V_read_6_reg_1183_pp0_iter1_reg; +reg [15:0] data_8_V_read_6_reg_1192; +reg [15:0] data_8_V_read_6_reg_1192_pp0_iter1_reg; +reg [15:0] data_7_V_read_7_reg_1201; +reg [15:0] data_7_V_read_7_reg_1201_pp0_iter1_reg; +reg [15:0] data_6_V_read_7_reg_1208; +reg [15:0] data_5_V_read_7_reg_1215; +reg [15:0] data_5_V_read_7_reg_1215_pp0_iter1_reg; +reg [15:0] data_4_V_read_8_reg_1224; +reg [15:0] data_3_V_read_8_reg_1232; +reg [15:0] data_2_V_read_8_reg_1240; +wire [15:0] add_ln703_fu_280_p2; +reg [15:0] add_ln703_reg_1246; +wire [15:0] sub_ln703_1_fu_286_p2; +reg [15:0] sub_ln703_1_reg_1252; +wire [15:0] sub_ln703_5_fu_319_p2; +reg [15:0] sub_ln703_5_reg_1258; +wire [15:0] sub_ln703_6_fu_324_p2; +reg [15:0] sub_ln703_6_reg_1263; +wire [15:0] add_ln703_136_fu_347_p2; +reg [15:0] add_ln703_136_reg_1268; +wire [15:0] sub_ln703_9_fu_353_p2; +reg [15:0] sub_ln703_9_reg_1273; +wire [15:0] add_ln703_138_fu_363_p2; +reg [15:0] add_ln703_138_reg_1278; +wire [15:0] add_ln703_139_fu_367_p2; +reg [15:0] add_ln703_139_reg_1284; +wire [15:0] add_ln703_145_fu_433_p2; +reg [15:0] add_ln703_145_reg_1289; +wire [15:0] sub_ln703_18_fu_443_p2; +reg [15:0] sub_ln703_18_reg_1294; +wire [15:0] add_ln703_146_fu_453_p2; +reg [15:0] add_ln703_146_reg_1299; +wire [15:0] add_ln703_147_fu_458_p2; +reg [15:0] add_ln703_147_reg_1304; +wire [15:0] add_ln703_148_fu_463_p2; +reg [15:0] add_ln703_148_reg_1309; +wire [15:0] add_ln703_149_fu_468_p2; +reg [15:0] add_ln703_149_reg_1314; +wire [15:0] sub_ln703_25_fu_517_p2; +reg [15:0] sub_ln703_25_reg_1319; +wire [15:0] sub_ln703_26_fu_527_p2; +reg [15:0] sub_ln703_26_reg_1324; +wire [15:0] sub_ln703_28_fu_537_p2; +reg [15:0] sub_ln703_28_reg_1329; +wire [15:0] sub_ln703_30_fu_542_p2; +reg [15:0] sub_ln703_30_reg_1334; +wire [15:0] sub_ln703_33_fu_562_p2; +reg [15:0] sub_ln703_33_reg_1339; +wire [15:0] add_ln703_166_fu_567_p2; +reg [15:0] add_ln703_166_reg_1344; +wire [15:0] add_ln703_163_fu_621_p2; +reg [15:0] add_ln703_163_reg_1350; +wire [15:0] sub_ln703_38_fu_626_p2; +reg [15:0] sub_ln703_38_reg_1355; +wire [15:0] add_ln703_167_fu_641_p2; +reg [15:0] add_ln703_167_reg_1360; +wire [15:0] sub_ln703_41_fu_646_p2; +reg [15:0] sub_ln703_41_reg_1365; +wire [15:0] add_ln703_176_fu_660_p2; +reg [15:0] add_ln703_176_reg_1370; +reg [15:0] add_ln703_176_reg_1370_pp0_iter5_reg; +wire [15:0] sub_ln703_46_fu_697_p2; +reg [15:0] sub_ln703_46_reg_1375; +wire [15:0] add_ln703_173_fu_732_p2; +reg [15:0] add_ln703_173_reg_1380; +wire [15:0] sub_ln703_49_fu_737_p2; +reg [15:0] sub_ln703_49_reg_1385; +wire [15:0] sub_ln703_50_fu_742_p2; +reg [15:0] sub_ln703_50_reg_1390; +wire [15:0] add_ln703_180_fu_760_p2; +reg [15:0] add_ln703_180_reg_1395; +wire [15:0] add_ln703_184_fu_770_p2; +reg [15:0] add_ln703_184_reg_1400; +wire [15:0] sub_ln703_61_fu_840_p2; +reg [15:0] sub_ln703_61_reg_1405; +wire [15:0] add_ln703_189_fu_855_p2; +reg [15:0] add_ln703_189_reg_1410; +wire [15:0] sub_ln703_62_fu_860_p2; +reg [15:0] sub_ln703_62_reg_1415; +wire [15:0] sub_ln703_64_fu_865_p2; +reg [15:0] sub_ln703_64_reg_1420; +wire [15:0] add_ln703_192_fu_870_p2; +reg [15:0] add_ln703_192_reg_1425; +wire [15:0] add_ln703_194_fu_874_p2; +reg [15:0] add_ln703_194_reg_1431; +wire ap_block_pp0_stage0; +wire [15:0] sub_ln703_fu_274_p2; +wire [15:0] add_ln703_130_fu_300_p2; +wire [15:0] sub_ln703_2_fu_292_p2; +wire [15:0] sub_ln703_3_fu_296_p2; +wire [15:0] add_ln703_131_fu_304_p2; +wire [15:0] sub_ln703_4_fu_309_p2; +wire [15:0] add_ln703_132_fu_314_p2; +wire [15:0] add_ln703_134_fu_338_p2; +wire [15:0] add_ln703_135_fu_342_p2; +wire [15:0] add_ln703_133_fu_334_p2; +wire [15:0] sub_ln703_8_fu_329_p2; +wire [15:0] add_ln703_137_fu_358_p2; +wire [15:0] sub_ln703_7_fu_373_p2; +wire [15:0] add_ln703_141_fu_386_p2; +wire [15:0] sub_ln703_10_fu_377_p2; +wire [15:0] add_ln703_140_fu_381_p2; +wire [15:0] add_ln703_142_fu_390_p2; +wire [15:0] add_ln703_143_fu_395_p2; +wire [15:0] add_ln703_144_fu_399_p2; +wire [15:0] sub_ln703_11_fu_404_p2; +wire [15:0] sub_ln703_13_fu_413_p2; +wire [15:0] sub_ln703_14_fu_418_p2; +wire [15:0] sub_ln703_15_fu_423_p2; +wire [15:0] sub_ln703_16_fu_428_p2; +wire [15:0] sub_ln703_17_fu_438_p2; +wire [15:0] sub_ln703_19_fu_448_p2; +wire [15:0] sub_ln703_12_fu_408_p2; +wire [15:0] sub_ln703_20_fu_472_p2; +wire [15:0] add_ln703_151_fu_489_p2; +wire [15:0] add_ln703_150_fu_476_p2; +wire [15:0] sub_ln703_21_fu_480_p2; +wire [15:0] sub_ln703_22_fu_485_p2; +wire [15:0] add_ln703_152_fu_493_p2; +wire [15:0] sub_ln703_24_fu_502_p2; +wire [15:0] add_ln703_153_fu_507_p2; +wire [15:0] add_ln703_154_fu_512_p2; +wire [15:0] add_ln703_155_fu_522_p2; +wire [15:0] sub_ln703_27_fu_532_p2; +wire [15:0] sub_ln703_23_fu_498_p2; +wire [15:0] add_ln703_158_fu_552_p2; +wire [15:0] add_ln703_157_fu_547_p2; +wire [15:0] add_ln703_159_fu_556_p2; +wire [15:0] add_ln703_156_fu_571_p2; +wire [15:0] sub_ln703_29_fu_575_p2; +wire [15:0] sub_ln703_32_fu_584_p2; +wire [15:0] add_ln703_160_fu_588_p2; +wire [15:0] add_ln703_161_fu_593_p2; +wire [15:0] sub_ln703_34_fu_597_p2; +wire [15:0] sub_ln703_35_fu_602_p2; +wire [15:0] add_ln703_162_fu_616_p2; +wire [15:0] add_ln703_164_fu_631_p2; +wire [15:0] sub_ln703_36_fu_607_p2; +wire [15:0] sub_ln703_37_fu_612_p2; +wire [15:0] add_ln703_165_fu_635_p2; +wire [15:0] sub_ln703_31_fu_579_p2; +wire [15:0] add_ln703_175_fu_656_p2; +wire [15:0] add_ln703_174_fu_651_p2; +wire [15:0] sub_ln703_39_fu_666_p2; +wire [15:0] add_ln703_168_fu_674_p2; +wire [15:0] sub_ln703_42_fu_679_p2; +wire [15:0] sub_ln703_43_fu_683_p2; +wire [15:0] sub_ln703_44_fu_688_p2; +wire [15:0] sub_ln703_45_fu_692_p2; +wire [15:0] sub_ln703_40_fu_670_p2; +wire [15:0] add_ln703_171_fu_717_p2; +wire [15:0] add_ln703_170_fu_712_p2; +wire [15:0] add_ln703_169_fu_702_p2; +wire [15:0] sub_ln703_47_fu_707_p2; +wire [15:0] add_ln703_172_fu_721_p2; +wire [15:0] sub_ln703_48_fu_727_p2; +wire [15:0] add_ln703_178_fu_751_p2; +wire [15:0] add_ln703_179_fu_755_p2; +wire [15:0] add_ln703_177_fu_747_p2; +wire [15:0] add_ln703_183_fu_766_p2; +wire [15:0] add_ln703_181_fu_775_p2; +wire [15:0] sub_ln703_51_fu_779_p2; +wire [15:0] sub_ln703_52_fu_783_p2; +wire [15:0] add_ln703_182_fu_806_p2; +wire [15:0] sub_ln703_53_fu_787_p2; +wire [15:0] sub_ln703_54_fu_791_p2; +wire [15:0] sub_ln703_56_fu_801_p2; +wire [15:0] add_ln703_185_fu_810_p2; +wire [15:0] add_ln703_186_fu_815_p2; +wire [15:0] sub_ln703_57_fu_820_p2; +wire [15:0] add_ln703_187_fu_845_p2; +wire [15:0] sub_ln703_55_fu_796_p2; +wire [15:0] sub_ln703_59_fu_830_p2; +wire [15:0] sub_ln703_60_fu_835_p2; +wire [15:0] add_ln703_188_fu_849_p2; +wire [15:0] sub_ln703_58_fu_825_p2; +wire [15:0] sub_ln703_63_fu_879_p2; +wire [15:0] sub_ln703_65_fu_883_p2; +wire [15:0] add_ln703_190_fu_887_p2; +wire [15:0] sub_ln703_66_fu_891_p2; +wire [15:0] add_ln703_195_fu_915_p2; +wire [15:0] add_ln703_191_fu_896_p2; +wire [15:0] sub_ln703_68_fu_906_p2; +wire [15:0] add_ln703_193_fu_911_p2; +wire [15:0] add_ln703_196_fu_919_p2; +wire [15:0] sub_ln703_69_fu_924_p2; +wire [15:0] add_ln703_198_fu_949_p2; +wire [15:0] sub_ln703_67_fu_901_p2; +wire [15:0] sub_ln703_70_fu_929_p2; +wire [15:0] acc_1_V_fu_934_p2; +wire [15:0] acc_2_V_fu_939_p2; +wire [15:0] acc_3_V_fu_944_p2; +wire [15:0] acc_4_V_fu_953_p2; +reg ap_ce_reg; +reg [15:0] data_0_V_read_int_reg; +reg [15:0] data_1_V_read_int_reg; +reg [15:0] data_2_V_read_int_reg; +reg [15:0] data_3_V_read_int_reg; +reg [15:0] data_4_V_read_int_reg; +reg [15:0] data_5_V_read_int_reg; +reg [15:0] data_6_V_read_int_reg; +reg [15:0] data_7_V_read_int_reg; +reg [15:0] data_8_V_read_int_reg; +reg [15:0] data_9_V_read_int_reg; +reg [15:0] data_10_V_read_int_reg; +reg [15:0] data_11_V_read_int_reg; +reg [15:0] data_12_V_read_int_reg; +reg [15:0] data_13_V_read_int_reg; +reg [15:0] data_14_V_read_int_reg; +reg [15:0] data_15_V_read_int_reg; +reg [15:0] data_16_V_read_int_reg; +reg [15:0] data_17_V_read_int_reg; +reg [15:0] data_18_V_read_int_reg; +reg [15:0] data_19_V_read_int_reg; +reg [15:0] data_20_V_read_int_reg; +reg [15:0] data_21_V_read_int_reg; +reg [15:0] data_22_V_read_int_reg; +reg [15:0] data_23_V_read_int_reg; +reg [15:0] data_24_V_read_int_reg; +reg [15:0] data_25_V_read_int_reg; +reg [15:0] data_26_V_read_int_reg; +reg [15:0] data_27_V_read_int_reg; +reg [15:0] data_28_V_read_int_reg; +reg [15:0] data_29_V_read_int_reg; +reg [15:0] data_30_V_read_int_reg; +reg [15:0] data_31_V_read_int_reg; +reg [15:0] ap_return_0_int_reg; +reg [15:0] ap_return_1_int_reg; +reg [15:0] ap_return_2_int_reg; +reg [15:0] ap_return_3_int_reg; +reg [15:0] ap_return_4_int_reg; + +always @ (posedge ap_clk) begin + ap_ce_reg <= ap_ce; +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln703_136_reg_1268 <= add_ln703_136_fu_347_p2; + add_ln703_138_reg_1278 <= add_ln703_138_fu_363_p2; + add_ln703_139_reg_1284 <= add_ln703_139_fu_367_p2; + add_ln703_145_reg_1289 <= add_ln703_145_fu_433_p2; + add_ln703_146_reg_1299 <= add_ln703_146_fu_453_p2; + add_ln703_147_reg_1304 <= add_ln703_147_fu_458_p2; + add_ln703_148_reg_1309 <= add_ln703_148_fu_463_p2; + add_ln703_149_reg_1314 <= add_ln703_149_fu_468_p2; + add_ln703_163_reg_1350 <= add_ln703_163_fu_621_p2; + add_ln703_166_reg_1344 <= add_ln703_166_fu_567_p2; + add_ln703_167_reg_1360 <= add_ln703_167_fu_641_p2; + add_ln703_173_reg_1380 <= add_ln703_173_fu_732_p2; + add_ln703_176_reg_1370 <= add_ln703_176_fu_660_p2; + add_ln703_176_reg_1370_pp0_iter5_reg <= add_ln703_176_reg_1370; + add_ln703_180_reg_1395 <= add_ln703_180_fu_760_p2; + add_ln703_184_reg_1400 <= add_ln703_184_fu_770_p2; + add_ln703_189_reg_1410 <= add_ln703_189_fu_855_p2; + add_ln703_192_reg_1425 <= add_ln703_192_fu_870_p2; + add_ln703_194_reg_1431 <= add_ln703_194_fu_874_p2; + add_ln703_reg_1246 <= add_ln703_fu_280_p2; + data_10_V_read11_reg_1174 <= data_10_V_read_int_reg; + data_10_V_read11_reg_1174_pp0_iter1_reg <= data_10_V_read11_reg_1174; + data_10_V_read11_reg_1174_pp0_iter2_reg <= data_10_V_read11_reg_1174_pp0_iter1_reg; + data_11_V_read12_reg_1165 <= data_11_V_read_int_reg; + data_11_V_read12_reg_1165_pp0_iter1_reg <= data_11_V_read12_reg_1165; + data_11_V_read12_reg_1165_pp0_iter2_reg <= data_11_V_read12_reg_1165_pp0_iter1_reg; + data_12_V_read13_reg_1156 <= data_12_V_read_int_reg; + data_12_V_read13_reg_1156_pp0_iter1_reg <= data_12_V_read13_reg_1156; + data_12_V_read13_reg_1156_pp0_iter2_reg <= data_12_V_read13_reg_1156_pp0_iter1_reg; + data_13_V_read14_reg_1147 <= data_13_V_read_int_reg; + data_13_V_read14_reg_1147_pp0_iter1_reg <= data_13_V_read14_reg_1147; + data_13_V_read14_reg_1147_pp0_iter2_reg <= data_13_V_read14_reg_1147_pp0_iter1_reg; + data_14_V_read15_reg_1138 <= data_14_V_read_int_reg; + data_14_V_read15_reg_1138_pp0_iter1_reg <= data_14_V_read15_reg_1138; + data_14_V_read15_reg_1138_pp0_iter2_reg <= data_14_V_read15_reg_1138_pp0_iter1_reg; + data_14_V_read15_reg_1138_pp0_iter3_reg <= data_14_V_read15_reg_1138_pp0_iter2_reg; + data_15_V_read16_reg_1129 <= data_15_V_read_int_reg; + data_15_V_read16_reg_1129_pp0_iter1_reg <= data_15_V_read16_reg_1129; + data_15_V_read16_reg_1129_pp0_iter2_reg <= data_15_V_read16_reg_1129_pp0_iter1_reg; + data_15_V_read16_reg_1129_pp0_iter3_reg <= data_15_V_read16_reg_1129_pp0_iter2_reg; + data_16_V_read_7_reg_1120 <= data_16_V_read_int_reg; + data_16_V_read_7_reg_1120_pp0_iter1_reg <= data_16_V_read_7_reg_1120; + data_16_V_read_7_reg_1120_pp0_iter2_reg <= data_16_V_read_7_reg_1120_pp0_iter1_reg; + data_16_V_read_7_reg_1120_pp0_iter3_reg <= data_16_V_read_7_reg_1120_pp0_iter2_reg; + data_17_V_read_7_reg_1111 <= data_17_V_read_int_reg; + data_17_V_read_7_reg_1111_pp0_iter1_reg <= data_17_V_read_7_reg_1111; + data_17_V_read_7_reg_1111_pp0_iter2_reg <= data_17_V_read_7_reg_1111_pp0_iter1_reg; + data_17_V_read_7_reg_1111_pp0_iter3_reg <= data_17_V_read_7_reg_1111_pp0_iter2_reg; + data_18_V_read_6_reg_1103 <= data_18_V_read_int_reg; + data_18_V_read_6_reg_1103_pp0_iter1_reg <= data_18_V_read_6_reg_1103; + data_18_V_read_6_reg_1103_pp0_iter2_reg <= data_18_V_read_6_reg_1103_pp0_iter1_reg; + data_18_V_read_6_reg_1103_pp0_iter3_reg <= data_18_V_read_6_reg_1103_pp0_iter2_reg; + data_18_V_read_6_reg_1103_pp0_iter4_reg <= data_18_V_read_6_reg_1103_pp0_iter3_reg; + data_19_V_read_6_reg_1095 <= data_19_V_read_int_reg; + data_19_V_read_6_reg_1095_pp0_iter1_reg <= data_19_V_read_6_reg_1095; + data_19_V_read_6_reg_1095_pp0_iter2_reg <= data_19_V_read_6_reg_1095_pp0_iter1_reg; + data_19_V_read_6_reg_1095_pp0_iter3_reg <= data_19_V_read_6_reg_1095_pp0_iter2_reg; + data_19_V_read_6_reg_1095_pp0_iter4_reg <= data_19_V_read_6_reg_1095_pp0_iter3_reg; + data_20_V_read21_reg_1086 <= data_20_V_read_int_reg; + data_20_V_read21_reg_1086_pp0_iter1_reg <= data_20_V_read21_reg_1086; + data_20_V_read21_reg_1086_pp0_iter2_reg <= data_20_V_read21_reg_1086_pp0_iter1_reg; + data_20_V_read21_reg_1086_pp0_iter3_reg <= data_20_V_read21_reg_1086_pp0_iter2_reg; + data_20_V_read21_reg_1086_pp0_iter4_reg <= data_20_V_read21_reg_1086_pp0_iter3_reg; + data_21_V_read22_reg_1077 <= data_21_V_read_int_reg; + data_21_V_read22_reg_1077_pp0_iter1_reg <= data_21_V_read22_reg_1077; + data_21_V_read22_reg_1077_pp0_iter2_reg <= data_21_V_read22_reg_1077_pp0_iter1_reg; + data_21_V_read22_reg_1077_pp0_iter3_reg <= data_21_V_read22_reg_1077_pp0_iter2_reg; + data_21_V_read22_reg_1077_pp0_iter4_reg <= data_21_V_read22_reg_1077_pp0_iter3_reg; + data_22_V_read23_reg_1068 <= data_22_V_read_int_reg; + data_22_V_read23_reg_1068_pp0_iter1_reg <= data_22_V_read23_reg_1068; + data_22_V_read23_reg_1068_pp0_iter2_reg <= data_22_V_read23_reg_1068_pp0_iter1_reg; + data_22_V_read23_reg_1068_pp0_iter3_reg <= data_22_V_read23_reg_1068_pp0_iter2_reg; + data_22_V_read23_reg_1068_pp0_iter4_reg <= data_22_V_read23_reg_1068_pp0_iter3_reg; + data_22_V_read23_reg_1068_pp0_iter5_reg <= data_22_V_read23_reg_1068_pp0_iter4_reg; + data_23_V_read24_reg_1059 <= data_23_V_read_int_reg; + data_23_V_read24_reg_1059_pp0_iter1_reg <= data_23_V_read24_reg_1059; + data_23_V_read24_reg_1059_pp0_iter2_reg <= data_23_V_read24_reg_1059_pp0_iter1_reg; + data_23_V_read24_reg_1059_pp0_iter3_reg <= data_23_V_read24_reg_1059_pp0_iter2_reg; + data_23_V_read24_reg_1059_pp0_iter4_reg <= data_23_V_read24_reg_1059_pp0_iter3_reg; + data_24_V_read25_reg_1050 <= data_24_V_read_int_reg; + data_24_V_read25_reg_1050_pp0_iter1_reg <= data_24_V_read25_reg_1050; + data_24_V_read25_reg_1050_pp0_iter2_reg <= data_24_V_read25_reg_1050_pp0_iter1_reg; + data_24_V_read25_reg_1050_pp0_iter3_reg <= data_24_V_read25_reg_1050_pp0_iter2_reg; + data_24_V_read25_reg_1050_pp0_iter4_reg <= data_24_V_read25_reg_1050_pp0_iter3_reg; + data_24_V_read25_reg_1050_pp0_iter5_reg <= data_24_V_read25_reg_1050_pp0_iter4_reg; + data_25_V_read26_reg_1041 <= data_25_V_read_int_reg; + data_25_V_read26_reg_1041_pp0_iter1_reg <= data_25_V_read26_reg_1041; + data_25_V_read26_reg_1041_pp0_iter2_reg <= data_25_V_read26_reg_1041_pp0_iter1_reg; + data_25_V_read26_reg_1041_pp0_iter3_reg <= data_25_V_read26_reg_1041_pp0_iter2_reg; + data_25_V_read26_reg_1041_pp0_iter4_reg <= data_25_V_read26_reg_1041_pp0_iter3_reg; + data_25_V_read26_reg_1041_pp0_iter5_reg <= data_25_V_read26_reg_1041_pp0_iter4_reg; + data_26_V_read_7_reg_1032 <= data_26_V_read_int_reg; + data_26_V_read_7_reg_1032_pp0_iter1_reg <= data_26_V_read_7_reg_1032; + data_26_V_read_7_reg_1032_pp0_iter2_reg <= data_26_V_read_7_reg_1032_pp0_iter1_reg; + data_26_V_read_7_reg_1032_pp0_iter3_reg <= data_26_V_read_7_reg_1032_pp0_iter2_reg; + data_26_V_read_7_reg_1032_pp0_iter4_reg <= data_26_V_read_7_reg_1032_pp0_iter3_reg; + data_26_V_read_7_reg_1032_pp0_iter5_reg <= data_26_V_read_7_reg_1032_pp0_iter4_reg; + data_27_V_read_7_reg_1023 <= data_27_V_read_int_reg; + data_27_V_read_7_reg_1023_pp0_iter1_reg <= data_27_V_read_7_reg_1023; + data_27_V_read_7_reg_1023_pp0_iter2_reg <= data_27_V_read_7_reg_1023_pp0_iter1_reg; + data_27_V_read_7_reg_1023_pp0_iter3_reg <= data_27_V_read_7_reg_1023_pp0_iter2_reg; + data_27_V_read_7_reg_1023_pp0_iter4_reg <= data_27_V_read_7_reg_1023_pp0_iter3_reg; + data_27_V_read_7_reg_1023_pp0_iter5_reg <= data_27_V_read_7_reg_1023_pp0_iter4_reg; + data_28_V_read_6_reg_1014 <= data_28_V_read_int_reg; + data_28_V_read_6_reg_1014_pp0_iter1_reg <= data_28_V_read_6_reg_1014; + data_28_V_read_6_reg_1014_pp0_iter2_reg <= data_28_V_read_6_reg_1014_pp0_iter1_reg; + data_28_V_read_6_reg_1014_pp0_iter3_reg <= data_28_V_read_6_reg_1014_pp0_iter2_reg; + data_28_V_read_6_reg_1014_pp0_iter4_reg <= data_28_V_read_6_reg_1014_pp0_iter3_reg; + data_28_V_read_6_reg_1014_pp0_iter5_reg <= data_28_V_read_6_reg_1014_pp0_iter4_reg; + data_28_V_read_6_reg_1014_pp0_iter6_reg <= data_28_V_read_6_reg_1014_pp0_iter5_reg; + data_29_V_read_6_reg_1006 <= data_29_V_read_int_reg; + data_29_V_read_6_reg_1006_pp0_iter1_reg <= data_29_V_read_6_reg_1006; + data_29_V_read_6_reg_1006_pp0_iter2_reg <= data_29_V_read_6_reg_1006_pp0_iter1_reg; + data_29_V_read_6_reg_1006_pp0_iter3_reg <= data_29_V_read_6_reg_1006_pp0_iter2_reg; + data_29_V_read_6_reg_1006_pp0_iter4_reg <= data_29_V_read_6_reg_1006_pp0_iter3_reg; + data_29_V_read_6_reg_1006_pp0_iter5_reg <= data_29_V_read_6_reg_1006_pp0_iter4_reg; + data_29_V_read_6_reg_1006_pp0_iter6_reg <= data_29_V_read_6_reg_1006_pp0_iter5_reg; + data_2_V_read_8_reg_1240 <= data_2_V_read_int_reg; + data_30_V_read31_reg_998 <= data_30_V_read_int_reg; + data_30_V_read31_reg_998_pp0_iter1_reg <= data_30_V_read31_reg_998; + data_30_V_read31_reg_998_pp0_iter2_reg <= data_30_V_read31_reg_998_pp0_iter1_reg; + data_30_V_read31_reg_998_pp0_iter3_reg <= data_30_V_read31_reg_998_pp0_iter2_reg; + data_30_V_read31_reg_998_pp0_iter4_reg <= data_30_V_read31_reg_998_pp0_iter3_reg; + data_30_V_read31_reg_998_pp0_iter5_reg <= data_30_V_read31_reg_998_pp0_iter4_reg; + data_30_V_read31_reg_998_pp0_iter6_reg <= data_30_V_read31_reg_998_pp0_iter5_reg; + data_31_V_read32_reg_989 <= data_31_V_read_int_reg; + data_31_V_read32_reg_989_pp0_iter1_reg <= data_31_V_read32_reg_989; + data_31_V_read32_reg_989_pp0_iter2_reg <= data_31_V_read32_reg_989_pp0_iter1_reg; + data_31_V_read32_reg_989_pp0_iter3_reg <= data_31_V_read32_reg_989_pp0_iter2_reg; + data_31_V_read32_reg_989_pp0_iter4_reg <= data_31_V_read32_reg_989_pp0_iter3_reg; + data_31_V_read32_reg_989_pp0_iter5_reg <= data_31_V_read32_reg_989_pp0_iter4_reg; + data_31_V_read32_reg_989_pp0_iter6_reg <= data_31_V_read32_reg_989_pp0_iter5_reg; + data_3_V_read_8_reg_1232 <= data_3_V_read_int_reg; + data_4_V_read_8_reg_1224 <= data_4_V_read_int_reg; + data_5_V_read_7_reg_1215 <= data_5_V_read_int_reg; + data_5_V_read_7_reg_1215_pp0_iter1_reg <= data_5_V_read_7_reg_1215; + data_6_V_read_7_reg_1208 <= data_6_V_read_int_reg; + data_7_V_read_7_reg_1201 <= data_7_V_read_int_reg; + data_7_V_read_7_reg_1201_pp0_iter1_reg <= data_7_V_read_7_reg_1201; + data_8_V_read_6_reg_1192 <= data_8_V_read_int_reg; + data_8_V_read_6_reg_1192_pp0_iter1_reg <= data_8_V_read_6_reg_1192; + data_9_V_read_6_reg_1183 <= data_9_V_read_int_reg; + data_9_V_read_6_reg_1183_pp0_iter1_reg <= data_9_V_read_6_reg_1183; + sub_ln703_18_reg_1294 <= sub_ln703_18_fu_443_p2; + sub_ln703_1_reg_1252 <= sub_ln703_1_fu_286_p2; + sub_ln703_25_reg_1319 <= sub_ln703_25_fu_517_p2; + sub_ln703_26_reg_1324 <= sub_ln703_26_fu_527_p2; + sub_ln703_28_reg_1329 <= sub_ln703_28_fu_537_p2; + sub_ln703_30_reg_1334 <= sub_ln703_30_fu_542_p2; + sub_ln703_33_reg_1339 <= sub_ln703_33_fu_562_p2; + sub_ln703_38_reg_1355 <= sub_ln703_38_fu_626_p2; + sub_ln703_41_reg_1365 <= sub_ln703_41_fu_646_p2; + sub_ln703_46_reg_1375 <= sub_ln703_46_fu_697_p2; + sub_ln703_49_reg_1385 <= sub_ln703_49_fu_737_p2; + sub_ln703_50_reg_1390 <= sub_ln703_50_fu_742_p2; + sub_ln703_5_reg_1258 <= sub_ln703_5_fu_319_p2; + sub_ln703_61_reg_1405 <= sub_ln703_61_fu_840_p2; + sub_ln703_62_reg_1415 <= sub_ln703_62_fu_860_p2; + sub_ln703_64_reg_1420 <= sub_ln703_64_fu_865_p2; + sub_ln703_6_reg_1263 <= sub_ln703_6_fu_324_p2; + sub_ln703_9_reg_1273 <= sub_ln703_9_fu_353_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce_reg)) begin + ap_return_0_int_reg <= sub_ln703_70_fu_929_p2; + ap_return_1_int_reg <= acc_1_V_fu_934_p2; + ap_return_2_int_reg <= acc_2_V_fu_939_p2; + ap_return_3_int_reg <= acc_3_V_fu_944_p2; + ap_return_4_int_reg <= acc_4_V_fu_953_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce)) begin + data_0_V_read_int_reg <= data_0_V_read; + data_10_V_read_int_reg <= data_10_V_read; + data_11_V_read_int_reg <= data_11_V_read; + data_12_V_read_int_reg <= data_12_V_read; + data_13_V_read_int_reg <= data_13_V_read; + data_14_V_read_int_reg <= data_14_V_read; + data_15_V_read_int_reg <= data_15_V_read; + data_16_V_read_int_reg <= data_16_V_read; + data_17_V_read_int_reg <= data_17_V_read; + data_18_V_read_int_reg <= data_18_V_read; + data_19_V_read_int_reg <= data_19_V_read; + data_1_V_read_int_reg <= data_1_V_read; + data_20_V_read_int_reg <= data_20_V_read; + data_21_V_read_int_reg <= data_21_V_read; + data_22_V_read_int_reg <= data_22_V_read; + data_23_V_read_int_reg <= data_23_V_read; + data_24_V_read_int_reg <= data_24_V_read; + data_25_V_read_int_reg <= data_25_V_read; + data_26_V_read_int_reg <= data_26_V_read; + data_27_V_read_int_reg <= data_27_V_read; + data_28_V_read_int_reg <= data_28_V_read; + data_29_V_read_int_reg <= data_29_V_read; + data_2_V_read_int_reg <= data_2_V_read; + data_30_V_read_int_reg <= data_30_V_read; + data_31_V_read_int_reg <= data_31_V_read; + data_3_V_read_int_reg <= data_3_V_read; + data_4_V_read_int_reg <= data_4_V_read; + data_5_V_read_int_reg <= data_5_V_read; + data_6_V_read_int_reg <= data_6_V_read; + data_7_V_read_int_reg <= data_7_V_read; + data_8_V_read_int_reg <= data_8_V_read; + data_9_V_read_int_reg <= data_9_V_read; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_0 = ap_return_0_int_reg; + end else begin + ap_return_0 = sub_ln703_70_fu_929_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_1 = ap_return_1_int_reg; + end else begin + ap_return_1 = acc_1_V_fu_934_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_2 = ap_return_2_int_reg; + end else begin + ap_return_2 = acc_2_V_fu_939_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_3 = ap_return_3_int_reg; + end else begin + ap_return_3 = acc_3_V_fu_944_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_4 = ap_return_4_int_reg; + end else begin + ap_return_4 = acc_4_V_fu_953_p2; + end +end + +assign acc_1_V_fu_934_p2 = (add_ln703_193_fu_911_p2 - data_31_V_read32_reg_989_pp0_iter6_reg); + +assign acc_2_V_fu_939_p2 = (add_ln703_196_fu_919_p2 - data_31_V_read32_reg_989_pp0_iter6_reg); + +assign acc_3_V_fu_944_p2 = (sub_ln703_69_fu_924_p2 + data_31_V_read32_reg_989_pp0_iter6_reg); + +assign acc_4_V_fu_953_p2 = (add_ln703_198_fu_949_p2 + sub_ln703_67_fu_901_p2); + +assign add_ln703_130_fu_300_p2 = (data_2_V_read_8_reg_1240 + data_3_V_read_8_reg_1232); + +assign add_ln703_131_fu_304_p2 = (add_ln703_130_fu_300_p2 + add_ln703_reg_1246); + +assign add_ln703_132_fu_314_p2 = (sub_ln703_3_fu_296_p2 + data_4_V_read_8_reg_1224); + +assign add_ln703_133_fu_334_p2 = (sub_ln703_1_reg_1252 + data_3_V_read_8_reg_1232); + +assign add_ln703_134_fu_338_p2 = (data_5_V_read_7_reg_1215 + data_6_V_read_7_reg_1208); + +assign add_ln703_135_fu_342_p2 = (add_ln703_134_fu_338_p2 + data_4_V_read_8_reg_1224); + +assign add_ln703_136_fu_347_p2 = (add_ln703_135_fu_342_p2 + add_ln703_133_fu_334_p2); + +assign add_ln703_137_fu_358_p2 = (add_ln703_132_fu_314_p2 + data_5_V_read_7_reg_1215); + +assign add_ln703_138_fu_363_p2 = (data_6_V_read_7_reg_1208 + data_7_V_read_7_reg_1201); + +assign add_ln703_139_fu_367_p2 = (add_ln703_138_fu_363_p2 + add_ln703_137_fu_358_p2); + +assign add_ln703_140_fu_381_p2 = (add_ln703_138_reg_1278 + sub_ln703_7_fu_373_p2); + +assign add_ln703_141_fu_386_p2 = (sub_ln703_6_reg_1263 + data_5_V_read_7_reg_1215_pp0_iter1_reg); + +assign add_ln703_142_fu_390_p2 = (add_ln703_138_reg_1278 + add_ln703_141_fu_386_p2); + +assign add_ln703_143_fu_395_p2 = (sub_ln703_9_reg_1273 + data_7_V_read_7_reg_1201_pp0_iter1_reg); + +assign add_ln703_144_fu_399_p2 = (sub_ln703_10_fu_377_p2 + data_8_V_read_6_reg_1192_pp0_iter1_reg); + +assign add_ln703_145_fu_433_p2 = (sub_ln703_13_fu_413_p2 + data_9_V_read_6_reg_1183_pp0_iter1_reg); + +assign add_ln703_146_fu_453_p2 = (sub_ln703_17_fu_438_p2 + data_10_V_read11_reg_1174_pp0_iter1_reg); + +assign add_ln703_147_fu_458_p2 = (sub_ln703_19_fu_448_p2 + data_11_V_read12_reg_1165_pp0_iter1_reg); + +assign add_ln703_148_fu_463_p2 = (sub_ln703_12_fu_408_p2 + data_9_V_read_6_reg_1183_pp0_iter1_reg); + +assign add_ln703_149_fu_468_p2 = (data_10_V_read11_reg_1174_pp0_iter1_reg + data_11_V_read12_reg_1165_pp0_iter1_reg); + +assign add_ln703_150_fu_476_p2 = (add_ln703_149_reg_1314 + add_ln703_148_reg_1309); + +assign add_ln703_151_fu_489_p2 = (data_11_V_read12_reg_1165_pp0_iter2_reg + data_12_V_read13_reg_1156_pp0_iter2_reg); + +assign add_ln703_152_fu_493_p2 = (add_ln703_151_fu_489_p2 + sub_ln703_18_reg_1294); + +assign add_ln703_153_fu_507_p2 = (sub_ln703_21_fu_480_p2 + data_12_V_read13_reg_1156_pp0_iter2_reg); + +assign add_ln703_154_fu_512_p2 = (sub_ln703_22_fu_485_p2 + data_12_V_read13_reg_1156_pp0_iter2_reg); + +assign add_ln703_155_fu_522_p2 = (sub_ln703_24_fu_502_p2 + data_13_V_read14_reg_1147_pp0_iter2_reg); + +assign add_ln703_156_fu_571_p2 = (sub_ln703_25_reg_1319 + data_14_V_read15_reg_1138_pp0_iter3_reg); + +assign add_ln703_157_fu_547_p2 = (sub_ln703_23_fu_498_p2 + data_13_V_read14_reg_1147_pp0_iter2_reg); + +assign add_ln703_158_fu_552_p2 = (data_14_V_read15_reg_1138_pp0_iter2_reg + data_15_V_read16_reg_1129_pp0_iter2_reg); + +assign add_ln703_159_fu_556_p2 = (add_ln703_158_fu_552_p2 + add_ln703_157_fu_547_p2); + +assign add_ln703_160_fu_588_p2 = (sub_ln703_29_fu_575_p2 + data_15_V_read16_reg_1129_pp0_iter3_reg); + +assign add_ln703_161_fu_593_p2 = (sub_ln703_30_reg_1334 + data_15_V_read16_reg_1129_pp0_iter3_reg); + +assign add_ln703_162_fu_616_p2 = (sub_ln703_34_fu_597_p2 + data_17_V_read_7_reg_1111_pp0_iter3_reg); + +assign add_ln703_163_fu_621_p2 = (sub_ln703_35_fu_602_p2 + data_17_V_read_7_reg_1111_pp0_iter3_reg); + +assign add_ln703_164_fu_631_p2 = (data_17_V_read_7_reg_1111_pp0_iter3_reg + data_18_V_read_6_reg_1103_pp0_iter3_reg); + +assign add_ln703_165_fu_635_p2 = (add_ln703_164_fu_631_p2 + sub_ln703_36_fu_607_p2); + +assign add_ln703_166_fu_567_p2 = (data_18_V_read_6_reg_1103_pp0_iter2_reg + data_19_V_read_6_reg_1095_pp0_iter2_reg); + +assign add_ln703_167_fu_641_p2 = (add_ln703_166_reg_1344 + sub_ln703_37_fu_612_p2); + +assign add_ln703_168_fu_674_p2 = (sub_ln703_39_fu_666_p2 + data_19_V_read_6_reg_1095_pp0_iter4_reg); + +assign add_ln703_169_fu_702_p2 = (sub_ln703_44_fu_688_p2 + data_21_V_read22_reg_1077_pp0_iter4_reg); + +assign add_ln703_170_fu_712_p2 = (sub_ln703_40_fu_670_p2 + data_20_V_read21_reg_1086_pp0_iter4_reg); + +assign add_ln703_171_fu_717_p2 = (data_21_V_read22_reg_1077_pp0_iter4_reg + data_22_V_read23_reg_1068_pp0_iter4_reg); + +assign add_ln703_172_fu_721_p2 = (add_ln703_171_fu_717_p2 + add_ln703_170_fu_712_p2); + +assign add_ln703_173_fu_732_p2 = (sub_ln703_47_fu_707_p2 + data_23_V_read24_reg_1059_pp0_iter4_reg); + +assign add_ln703_174_fu_651_p2 = (sub_ln703_31_fu_579_p2 + data_16_V_read_7_reg_1120_pp0_iter3_reg); + +assign add_ln703_175_fu_656_p2 = (add_ln703_166_reg_1344 + data_17_V_read_7_reg_1111_pp0_iter3_reg); + +assign add_ln703_176_fu_660_p2 = (add_ln703_175_fu_656_p2 + add_ln703_174_fu_651_p2); + +assign add_ln703_177_fu_747_p2 = (data_20_V_read21_reg_1086_pp0_iter4_reg + data_21_V_read22_reg_1077_pp0_iter4_reg); + +assign add_ln703_178_fu_751_p2 = (data_23_V_read24_reg_1059_pp0_iter4_reg + data_24_V_read25_reg_1050_pp0_iter4_reg); + +assign add_ln703_179_fu_755_p2 = (add_ln703_178_fu_751_p2 + data_22_V_read23_reg_1068_pp0_iter4_reg); + +assign add_ln703_180_fu_760_p2 = (add_ln703_179_fu_755_p2 + add_ln703_177_fu_747_p2); + +assign add_ln703_181_fu_775_p2 = (add_ln703_180_reg_1395 + add_ln703_176_reg_1370_pp0_iter5_reg); + +assign add_ln703_182_fu_806_p2 = (sub_ln703_46_reg_1375 + data_22_V_read23_reg_1068_pp0_iter5_reg); + +assign add_ln703_183_fu_766_p2 = (data_24_V_read25_reg_1050_pp0_iter4_reg + data_25_V_read26_reg_1041_pp0_iter4_reg); + +assign add_ln703_184_fu_770_p2 = (add_ln703_183_fu_766_p2 + data_23_V_read24_reg_1059_pp0_iter4_reg); + +assign add_ln703_185_fu_810_p2 = (add_ln703_184_reg_1400 + add_ln703_182_fu_806_p2); + +assign add_ln703_186_fu_815_p2 = (sub_ln703_53_fu_787_p2 + data_25_V_read26_reg_1041_pp0_iter5_reg); + +assign add_ln703_187_fu_845_p2 = (data_26_V_read_7_reg_1032_pp0_iter5_reg + data_27_V_read_7_reg_1023_pp0_iter5_reg); + +assign add_ln703_188_fu_849_p2 = (add_ln703_187_fu_845_p2 + sub_ln703_55_fu_796_p2); + +assign add_ln703_189_fu_855_p2 = (sub_ln703_59_fu_830_p2 + data_27_V_read_7_reg_1023_pp0_iter5_reg); + +assign add_ln703_190_fu_887_p2 = (sub_ln703_62_reg_1415 + data_28_V_read_6_reg_1014_pp0_iter6_reg); + +assign add_ln703_191_fu_896_p2 = (sub_ln703_65_fu_883_p2 + data_29_V_read_6_reg_1006_pp0_iter6_reg); + +assign add_ln703_192_fu_870_p2 = (data_29_V_read_6_reg_1006_pp0_iter5_reg + data_30_V_read31_reg_998_pp0_iter5_reg); + +assign add_ln703_193_fu_911_p2 = (add_ln703_192_reg_1425 + sub_ln703_64_reg_1420); + +assign add_ln703_194_fu_874_p2 = (sub_ln703_58_fu_825_p2 + data_27_V_read_7_reg_1023_pp0_iter5_reg); + +assign add_ln703_195_fu_915_p2 = (add_ln703_192_reg_1425 + data_28_V_read_6_reg_1014_pp0_iter6_reg); + +assign add_ln703_196_fu_919_p2 = (add_ln703_195_fu_915_p2 + add_ln703_194_reg_1431); + +assign add_ln703_198_fu_949_p2 = (data_30_V_read31_reg_998_pp0_iter6_reg + data_31_V_read32_reg_989_pp0_iter6_reg); + +assign add_ln703_fu_280_p2 = (data_0_V_read_int_reg + data_1_V_read_int_reg); + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign sub_ln703_10_fu_377_p2 = (add_ln703_136_reg_1268 - data_7_V_read_7_reg_1201_pp0_iter1_reg); + +assign sub_ln703_11_fu_404_p2 = (add_ln703_139_reg_1284 - data_8_V_read_6_reg_1192_pp0_iter1_reg); + +assign sub_ln703_12_fu_408_p2 = (add_ln703_140_fu_381_p2 - data_8_V_read_6_reg_1192_pp0_iter1_reg); + +assign sub_ln703_13_fu_413_p2 = (add_ln703_142_fu_390_p2 - data_8_V_read_6_reg_1192_pp0_iter1_reg); + +assign sub_ln703_14_fu_418_p2 = (add_ln703_143_fu_395_p2 - data_8_V_read_6_reg_1192_pp0_iter1_reg); + +assign sub_ln703_15_fu_423_p2 = (add_ln703_144_fu_399_p2 - data_9_V_read_6_reg_1183_pp0_iter1_reg); + +assign sub_ln703_16_fu_428_p2 = (sub_ln703_11_fu_404_p2 - data_9_V_read_6_reg_1183_pp0_iter1_reg); + +assign sub_ln703_17_fu_438_p2 = (sub_ln703_14_fu_418_p2 - data_9_V_read_6_reg_1183_pp0_iter1_reg); + +assign sub_ln703_18_fu_443_p2 = (sub_ln703_15_fu_423_p2 - data_10_V_read11_reg_1174_pp0_iter1_reg); + +assign sub_ln703_19_fu_448_p2 = (sub_ln703_16_fu_428_p2 - data_10_V_read11_reg_1174_pp0_iter1_reg); + +assign sub_ln703_1_fu_286_p2 = (sub_ln703_fu_274_p2 - data_2_V_read_int_reg); + +assign sub_ln703_20_fu_472_p2 = (add_ln703_145_reg_1289 - data_10_V_read11_reg_1174_pp0_iter2_reg); + +assign sub_ln703_21_fu_480_p2 = (sub_ln703_20_fu_472_p2 - data_11_V_read12_reg_1165_pp0_iter2_reg); + +assign sub_ln703_22_fu_485_p2 = (add_ln703_146_reg_1299 - data_11_V_read12_reg_1165_pp0_iter2_reg); + +assign sub_ln703_23_fu_498_p2 = (add_ln703_147_reg_1304 - data_12_V_read13_reg_1156_pp0_iter2_reg); + +assign sub_ln703_24_fu_502_p2 = (add_ln703_150_fu_476_p2 - data_12_V_read13_reg_1156_pp0_iter2_reg); + +assign sub_ln703_25_fu_517_p2 = (add_ln703_152_fu_493_p2 - data_13_V_read14_reg_1147_pp0_iter2_reg); + +assign sub_ln703_26_fu_527_p2 = (add_ln703_153_fu_507_p2 - data_13_V_read14_reg_1147_pp0_iter2_reg); + +assign sub_ln703_27_fu_532_p2 = (add_ln703_154_fu_512_p2 - data_13_V_read14_reg_1147_pp0_iter2_reg); + +assign sub_ln703_28_fu_537_p2 = (add_ln703_155_fu_522_p2 - data_14_V_read15_reg_1138_pp0_iter2_reg); + +assign sub_ln703_29_fu_575_p2 = (sub_ln703_26_reg_1324 - data_14_V_read15_reg_1138_pp0_iter3_reg); + +assign sub_ln703_2_fu_292_p2 = (data_2_V_read_8_reg_1240 - add_ln703_reg_1246); + +assign sub_ln703_30_fu_542_p2 = (sub_ln703_27_fu_532_p2 - data_14_V_read15_reg_1138_pp0_iter2_reg); + +assign sub_ln703_31_fu_579_p2 = (add_ln703_156_fu_571_p2 - data_15_V_read16_reg_1129_pp0_iter3_reg); + +assign sub_ln703_32_fu_584_p2 = (sub_ln703_28_reg_1329 - data_15_V_read16_reg_1129_pp0_iter3_reg); + +assign sub_ln703_33_fu_562_p2 = (add_ln703_159_fu_556_p2 - data_16_V_read_7_reg_1120_pp0_iter2_reg); + +assign sub_ln703_34_fu_597_p2 = (sub_ln703_32_fu_584_p2 - data_16_V_read_7_reg_1120_pp0_iter3_reg); + +assign sub_ln703_35_fu_602_p2 = (add_ln703_160_fu_588_p2 - data_16_V_read_7_reg_1120_pp0_iter3_reg); + +assign sub_ln703_36_fu_607_p2 = (add_ln703_161_fu_593_p2 - data_16_V_read_7_reg_1120_pp0_iter3_reg); + +assign sub_ln703_37_fu_612_p2 = (sub_ln703_33_reg_1339 - data_17_V_read_7_reg_1111_pp0_iter3_reg); + +assign sub_ln703_38_fu_626_p2 = (add_ln703_162_fu_616_p2 - data_18_V_read_6_reg_1103_pp0_iter3_reg); + +assign sub_ln703_39_fu_666_p2 = (add_ln703_163_reg_1350 - data_18_V_read_6_reg_1103_pp0_iter4_reg); + +assign sub_ln703_3_fu_296_p2 = (sub_ln703_1_reg_1252 - data_3_V_read_8_reg_1232); + +assign sub_ln703_40_fu_670_p2 = (sub_ln703_38_reg_1355 - data_19_V_read_6_reg_1095_pp0_iter4_reg); + +assign sub_ln703_41_fu_646_p2 = (add_ln703_165_fu_635_p2 - data_19_V_read_6_reg_1095_pp0_iter3_reg); + +assign sub_ln703_42_fu_679_p2 = (add_ln703_167_reg_1360 - data_20_V_read21_reg_1086_pp0_iter4_reg); + +assign sub_ln703_43_fu_683_p2 = (add_ln703_168_fu_674_p2 - data_20_V_read21_reg_1086_pp0_iter4_reg); + +assign sub_ln703_44_fu_688_p2 = (sub_ln703_41_reg_1365 - data_20_V_read21_reg_1086_pp0_iter4_reg); + +assign sub_ln703_45_fu_692_p2 = (sub_ln703_42_fu_679_p2 - data_21_V_read22_reg_1077_pp0_iter4_reg); + +assign sub_ln703_46_fu_697_p2 = (sub_ln703_43_fu_683_p2 - data_21_V_read22_reg_1077_pp0_iter4_reg); + +assign sub_ln703_47_fu_707_p2 = (sub_ln703_45_fu_692_p2 - data_22_V_read23_reg_1068_pp0_iter4_reg); + +assign sub_ln703_48_fu_727_p2 = (add_ln703_169_fu_702_p2 - data_22_V_read23_reg_1068_pp0_iter4_reg); + +assign sub_ln703_49_fu_737_p2 = (add_ln703_172_fu_721_p2 - data_23_V_read24_reg_1059_pp0_iter4_reg); + +assign sub_ln703_4_fu_309_p2 = (sub_ln703_2_fu_292_p2 - data_3_V_read_8_reg_1232); + +assign sub_ln703_50_fu_742_p2 = (sub_ln703_48_fu_727_p2 - data_23_V_read24_reg_1059_pp0_iter4_reg); + +assign sub_ln703_51_fu_779_p2 = (add_ln703_173_reg_1380 - data_24_V_read25_reg_1050_pp0_iter5_reg); + +assign sub_ln703_52_fu_783_p2 = (sub_ln703_49_reg_1385 - data_24_V_read25_reg_1050_pp0_iter5_reg); + +assign sub_ln703_53_fu_787_p2 = (sub_ln703_50_reg_1390 - data_24_V_read25_reg_1050_pp0_iter5_reg); + +assign sub_ln703_54_fu_791_p2 = (add_ln703_181_fu_775_p2 - data_25_V_read26_reg_1041_pp0_iter5_reg); + +assign sub_ln703_55_fu_796_p2 = (sub_ln703_51_fu_779_p2 - data_25_V_read26_reg_1041_pp0_iter5_reg); + +assign sub_ln703_56_fu_801_p2 = (sub_ln703_52_fu_783_p2 - data_25_V_read26_reg_1041_pp0_iter5_reg); + +assign sub_ln703_57_fu_820_p2 = (sub_ln703_54_fu_791_p2 - data_26_V_read_7_reg_1032_pp0_iter5_reg); + +assign sub_ln703_58_fu_825_p2 = (sub_ln703_56_fu_801_p2 - data_26_V_read_7_reg_1032_pp0_iter5_reg); + +assign sub_ln703_59_fu_830_p2 = (add_ln703_185_fu_810_p2 - data_26_V_read_7_reg_1032_pp0_iter5_reg); + +assign sub_ln703_5_fu_319_p2 = (add_ln703_131_fu_304_p2 - data_4_V_read_8_reg_1224); + +assign sub_ln703_60_fu_835_p2 = (add_ln703_186_fu_815_p2 - data_26_V_read_7_reg_1032_pp0_iter5_reg); + +assign sub_ln703_61_fu_840_p2 = (sub_ln703_57_fu_820_p2 - data_27_V_read_7_reg_1023_pp0_iter5_reg); + +assign sub_ln703_62_fu_860_p2 = (sub_ln703_60_fu_835_p2 - data_27_V_read_7_reg_1023_pp0_iter5_reg); + +assign sub_ln703_63_fu_879_p2 = (sub_ln703_61_reg_1405 - data_28_V_read_6_reg_1014_pp0_iter6_reg); + +assign sub_ln703_64_fu_865_p2 = (add_ln703_188_fu_849_p2 - data_28_V_read_6_reg_1014_pp0_iter5_reg); + +assign sub_ln703_65_fu_883_p2 = (add_ln703_189_reg_1410 - data_28_V_read_6_reg_1014_pp0_iter6_reg); + +assign sub_ln703_66_fu_891_p2 = (sub_ln703_63_fu_879_p2 - data_29_V_read_6_reg_1006_pp0_iter6_reg); + +assign sub_ln703_67_fu_901_p2 = (add_ln703_190_fu_887_p2 - data_29_V_read_6_reg_1006_pp0_iter6_reg); + +assign sub_ln703_68_fu_906_p2 = (sub_ln703_66_fu_891_p2 - data_30_V_read31_reg_998_pp0_iter6_reg); + +assign sub_ln703_69_fu_924_p2 = (add_ln703_191_fu_896_p2 - data_30_V_read31_reg_998_pp0_iter6_reg); + +assign sub_ln703_6_fu_324_p2 = (sub_ln703_4_fu_309_p2 - data_4_V_read_8_reg_1224); + +assign sub_ln703_70_fu_929_p2 = (sub_ln703_68_fu_906_p2 - data_31_V_read32_reg_989_pp0_iter6_reg); + +assign sub_ln703_7_fu_373_p2 = (sub_ln703_5_reg_1258 - data_5_V_read_7_reg_1215_pp0_iter1_reg); + +assign sub_ln703_8_fu_329_p2 = (add_ln703_132_fu_314_p2 - data_5_V_read_7_reg_1215); + +assign sub_ln703_9_fu_353_p2 = (sub_ln703_8_fu_329_p2 - data_6_V_read_7_reg_1208); + +assign sub_ln703_fu_274_p2 = (data_0_V_read_int_reg - data_1_V_read_int_reg); + +endmodule //dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0 +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module myproject_mul_16s_10ns_26_2_0_MulnS_4(clk, ce, a, b, p); +input clk; +input ce; +input [16 - 1 : 0] a; +input [10 - 1 : 0] b; +output[26 - 1 : 0] p; +reg [26 - 1 : 0] p; +wire [26 - 1 : 0] tmp_product; + +assign tmp_product = (a) * ({1'b0, b}); +always @ (posedge clk) begin + if (ce) begin + p <= tmp_product; + end +end +endmodule +`timescale 1 ns / 1 ps +module myproject_mul_16s_10ns_26_2_0( + clk, + reset, + ce, + din0, + din1, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input clk; +input reset; +input ce; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mul_16s_10ns_26_2_0_MulnS_4 myproject_mul_16s_10ns_26_2_0_MulnS_4_U( + .clk( clk ), + .ce( ce ), + .a( din0 ), + .b( din1 ), + .p( dout )); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module myproject_mul_16s_11ns_26_2_0_MulnS_1(clk, ce, a, b, p); +input clk; +input ce; +input [16 - 1 : 0] a; +input [11 - 1 : 0] b; +output[26 - 1 : 0] p; +reg [26 - 1 : 0] p; +wire [26 - 1 : 0] tmp_product; + +assign tmp_product = (a) * ({1'b0, b}); +always @ (posedge clk) begin + if (ce) begin + p <= tmp_product; + end +end +endmodule +`timescale 1 ns / 1 ps +module myproject_mul_16s_11ns_26_2_0( + clk, + reset, + ce, + din0, + din1, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input clk; +input reset; +input ce; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mul_16s_11ns_26_2_0_MulnS_1 myproject_mul_16s_11ns_26_2_0_MulnS_1_U( + .clk( clk ), + .ce( ce ), + .a( din0 ), + .b( din1 ), + .p( dout )); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module myproject_mul_16s_12ns_26_2_0_MulnS_0(clk, ce, a, b, p); +input clk; +input ce; +input [16 - 1 : 0] a; +input [12 - 1 : 0] b; +output[26 - 1 : 0] p; +reg [26 - 1 : 0] p; +wire [26 - 1 : 0] tmp_product; + +assign tmp_product = (a) * ({1'b0, b}); +always @ (posedge clk) begin + if (ce) begin + p <= tmp_product; + end +end +endmodule +`timescale 1 ns / 1 ps +module myproject_mul_16s_12ns_26_2_0( + clk, + reset, + ce, + din0, + din1, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input clk; +input reset; +input ce; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mul_16s_12ns_26_2_0_MulnS_0 myproject_mul_16s_12ns_26_2_0_MulnS_0_U( + .clk( clk ), + .ce( ce ), + .a( din0 ), + .b( din1 ), + .p( dout )); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module myproject_mul_16s_13ns_26_2_0_MulnS_2(clk, ce, a, b, p); +input clk; +input ce; +input [16 - 1 : 0] a; +input [13 - 1 : 0] b; +output[26 - 1 : 0] p; +reg [26 - 1 : 0] p; +wire [26 - 1 : 0] tmp_product; + +assign tmp_product = (a) * ({1'b0, b}); +always @ (posedge clk) begin + if (ce) begin + p <= tmp_product; + end +end +endmodule +`timescale 1 ns / 1 ps +module myproject_mul_16s_13ns_26_2_0( + clk, + reset, + ce, + din0, + din1, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input clk; +input reset; +input ce; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mul_16s_13ns_26_2_0_MulnS_2 myproject_mul_16s_13ns_26_2_0_MulnS_2_U( + .clk( clk ), + .ce( ce ), + .a( din0 ), + .b( din1 ), + .p( dout )); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module myproject_mul_16s_8ns_24_2_0_MulnS_5(clk, ce, a, b, p); +input clk; +input ce; +input [16 - 1 : 0] a; +input [8 - 1 : 0] b; +output[24 - 1 : 0] p; +reg [24 - 1 : 0] p; +wire [24 - 1 : 0] tmp_product; + +assign tmp_product = (a) * ({1'b0, b}); +always @ (posedge clk) begin + if (ce) begin + p <= tmp_product; + end +end +endmodule +`timescale 1 ns / 1 ps +module myproject_mul_16s_8ns_24_2_0( + clk, + reset, + ce, + din0, + din1, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input clk; +input reset; +input ce; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mul_16s_8ns_24_2_0_MulnS_5 myproject_mul_16s_8ns_24_2_0_MulnS_5_U( + .clk( clk ), + .ce( ce ), + .a( din0 ), + .b( din1 ), + .p( dout )); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module myproject_mul_16s_9ns_25_2_0_MulnS_3(clk, ce, a, b, p); +input clk; +input ce; +input [16 - 1 : 0] a; +input [9 - 1 : 0] b; +output[25 - 1 : 0] p; +reg [25 - 1 : 0] p; +wire [25 - 1 : 0] tmp_product; + +assign tmp_product = (a) * ({1'b0, b}); +always @ (posedge clk) begin + if (ce) begin + p <= tmp_product; + end +end +endmodule +`timescale 1 ns / 1 ps +module myproject_mul_16s_9ns_25_2_0( + clk, + reset, + ce, + din0, + din1, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input clk; +input reset; +input ce; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mul_16s_9ns_25_2_0_MulnS_3 myproject_mul_16s_9ns_25_2_0_MulnS_3_U( + .clk( clk ), + .ce( ce ), + .a( din0 ), + .b( din1 ), + .p( dout )); + +endmodule + +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + + +module bnn ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_idle, + ap_ready, + input1_V_ap_vld, + input1_V, + layer16_out_0_V, + layer16_out_0_V_ap_vld, + layer16_out_1_V, + layer16_out_1_V_ap_vld, + layer16_out_2_V, + layer16_out_2_V_ap_vld, + layer16_out_3_V, + layer16_out_3_V_ap_vld, + layer16_out_4_V, + layer16_out_4_V_ap_vld, + const_size_in_1, + const_size_in_1_ap_vld, + const_size_out_1, + const_size_out_1_ap_vld +); + +parameter ap_ST_fsm_pp0_stage0 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +input input1_V_ap_vld; +input [255:0] input1_V; +output [15:0] layer16_out_0_V; +output layer16_out_0_V_ap_vld; +output [15:0] layer16_out_1_V; +output layer16_out_1_V_ap_vld; +output [15:0] layer16_out_2_V; +output layer16_out_2_V_ap_vld; +output [15:0] layer16_out_3_V; +output layer16_out_3_V_ap_vld; +output [15:0] layer16_out_4_V; +output layer16_out_4_V_ap_vld; +output [15:0] const_size_in_1; +output const_size_in_1_ap_vld; +output [15:0] const_size_out_1; +output const_size_out_1_ap_vld; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg layer16_out_0_V_ap_vld; +reg layer16_out_1_V_ap_vld; +reg layer16_out_2_V_ap_vld; +reg layer16_out_3_V_ap_vld; +reg layer16_out_4_V_ap_vld; +reg const_size_in_1_ap_vld; +reg const_size_out_1_ap_vld; + +reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_pp0_stage0; +wire ap_enable_reg_pp0_iter0; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_enable_reg_pp0_iter22; +reg ap_enable_reg_pp0_iter23; +reg ap_enable_reg_pp0_iter24; +reg ap_enable_reg_pp0_iter25; +reg ap_enable_reg_pp0_iter26; +reg ap_enable_reg_pp0_iter27; +reg ap_enable_reg_pp0_iter28; +reg ap_enable_reg_pp0_iter29; +reg ap_enable_reg_pp0_iter30; +reg ap_enable_reg_pp0_iter31; +reg ap_enable_reg_pp0_iter32; +reg ap_enable_reg_pp0_iter33; +reg ap_enable_reg_pp0_iter34; +reg ap_enable_reg_pp0_iter35; +reg ap_enable_reg_pp0_iter36; +reg ap_enable_reg_pp0_iter37; +reg ap_enable_reg_pp0_iter38; +reg ap_enable_reg_pp0_iter39; +reg ap_enable_reg_pp0_iter40; +reg ap_enable_reg_pp0_iter41; +reg ap_enable_reg_pp0_iter42; +reg ap_enable_reg_pp0_iter43; +reg ap_enable_reg_pp0_iter44; +reg ap_enable_reg_pp0_iter45; +reg ap_enable_reg_pp0_iter46; +reg ap_enable_reg_pp0_iter47; +reg ap_enable_reg_pp0_iter48; +reg ap_enable_reg_pp0_iter49; +reg ap_enable_reg_pp0_iter50; +reg ap_enable_reg_pp0_iter51; +reg ap_enable_reg_pp0_iter52; +reg ap_enable_reg_pp0_iter53; +reg ap_enable_reg_pp0_iter54; +reg ap_enable_reg_pp0_iter55; +reg ap_enable_reg_pp0_iter56; +reg ap_enable_reg_pp0_iter57; +reg ap_enable_reg_pp0_iter58; +reg ap_enable_reg_pp0_iter59; +reg ap_enable_reg_pp0_iter60; +reg ap_enable_reg_pp0_iter61; +reg ap_enable_reg_pp0_iter62; +reg ap_enable_reg_pp0_iter63; +reg ap_enable_reg_pp0_iter64; +reg ap_enable_reg_pp0_iter65; +reg ap_enable_reg_pp0_iter66; +reg ap_enable_reg_pp0_iter67; +reg ap_idle_pp0; +reg input1_V_ap_vld_in_sig; +reg ap_block_state1_pp0_stage0_iter0; +wire ap_block_state2_pp0_stage0_iter1; +wire ap_block_state3_pp0_stage0_iter2; +wire ap_block_state4_pp0_stage0_iter3; +wire ap_block_state5_pp0_stage0_iter4; +wire ap_block_state6_pp0_stage0_iter5; +wire ap_block_state7_pp0_stage0_iter6; +wire ap_block_state8_pp0_stage0_iter7; +wire ap_block_state9_pp0_stage0_iter8; +wire ap_block_state10_pp0_stage0_iter9; +wire ap_block_state11_pp0_stage0_iter10; +wire ap_block_state12_pp0_stage0_iter11; +wire ap_block_state13_pp0_stage0_iter12; +wire ap_block_state14_pp0_stage0_iter13; +wire ap_block_state15_pp0_stage0_iter14; +wire ap_block_state16_pp0_stage0_iter15; +wire ap_block_state17_pp0_stage0_iter16; +wire ap_block_state18_pp0_stage0_iter17; +wire ap_block_state19_pp0_stage0_iter18; +wire ap_block_state20_pp0_stage0_iter19; +wire ap_block_state21_pp0_stage0_iter20; +wire ap_block_state22_pp0_stage0_iter21; +wire ap_block_state23_pp0_stage0_iter22; +wire ap_block_state24_pp0_stage0_iter23; +wire ap_block_state25_pp0_stage0_iter24; +wire ap_block_state26_pp0_stage0_iter25; +wire ap_block_state27_pp0_stage0_iter26; +wire ap_block_state28_pp0_stage0_iter27; +wire ap_block_state29_pp0_stage0_iter28; +wire ap_block_state30_pp0_stage0_iter29; +wire ap_block_state31_pp0_stage0_iter30; +wire ap_block_state32_pp0_stage0_iter31; +wire ap_block_state33_pp0_stage0_iter32; +wire ap_block_state34_pp0_stage0_iter33; +wire ap_block_state35_pp0_stage0_iter34; +wire ap_block_state36_pp0_stage0_iter35; +wire ap_block_state37_pp0_stage0_iter36; +wire ap_block_state38_pp0_stage0_iter37; +wire ap_block_state39_pp0_stage0_iter38; +wire ap_block_state40_pp0_stage0_iter39; +wire ap_block_state41_pp0_stage0_iter40; +wire ap_block_state42_pp0_stage0_iter41; +wire ap_block_state43_pp0_stage0_iter42; +wire ap_block_state44_pp0_stage0_iter43; +wire ap_block_state45_pp0_stage0_iter44; +wire ap_block_state46_pp0_stage0_iter45; +wire ap_block_state47_pp0_stage0_iter46; +wire ap_block_state48_pp0_stage0_iter47; +wire ap_block_state49_pp0_stage0_iter48; +wire ap_block_state50_pp0_stage0_iter49; +wire ap_block_state51_pp0_stage0_iter50; +wire ap_block_state52_pp0_stage0_iter51; +wire ap_block_state53_pp0_stage0_iter52; +wire ap_block_state54_pp0_stage0_iter53; +wire ap_block_state55_pp0_stage0_iter54; +wire ap_block_state56_pp0_stage0_iter55; +wire ap_block_state57_pp0_stage0_iter56; +wire ap_block_state58_pp0_stage0_iter57; +wire ap_block_state59_pp0_stage0_iter58; +wire ap_block_state60_pp0_stage0_iter59; +wire ap_block_state61_pp0_stage0_iter60; +wire ap_block_state62_pp0_stage0_iter61; +wire ap_block_state63_pp0_stage0_iter62; +wire ap_block_state64_pp0_stage0_iter63; +wire ap_block_state65_pp0_stage0_iter64; +wire ap_block_state66_pp0_stage0_iter65; +wire ap_block_state67_pp0_stage0_iter66; +wire ap_block_state68_pp0_stage0_iter67; +reg ap_block_pp0_stage0_11001; +reg [255:0] input1_V_preg; +reg [255:0] input1_V_in_sig; +reg input1_V_ap_vld_preg; +reg input1_V_blk_n; +wire ap_block_pp0_stage0; +reg [15:0] layer2_out_0_V_reg_2146; +reg [15:0] layer2_out_1_V_reg_2151; +reg [15:0] layer2_out_2_V_reg_2156; +reg [15:0] layer2_out_3_V_reg_2161; +reg [15:0] layer2_out_4_V_reg_2166; +reg [15:0] layer2_out_5_V_reg_2171; +reg [15:0] layer2_out_6_V_reg_2176; +reg [15:0] layer2_out_7_V_reg_2181; +reg [15:0] layer2_out_8_V_reg_2186; +reg [15:0] layer2_out_9_V_reg_2191; +reg [15:0] layer2_out_10_V_reg_2196; +reg [15:0] layer2_out_11_V_reg_2201; +reg [15:0] layer2_out_12_V_reg_2206; +reg [15:0] layer2_out_13_V_reg_2211; +reg [15:0] layer2_out_14_V_reg_2216; +reg [15:0] layer2_out_15_V_reg_2221; +reg [15:0] layer2_out_16_V_reg_2226; +reg [15:0] layer2_out_17_V_reg_2231; +reg [15:0] layer2_out_18_V_reg_2236; +reg [15:0] layer2_out_19_V_reg_2241; +reg [15:0] layer2_out_20_V_reg_2246; +reg [15:0] layer2_out_21_V_reg_2251; +reg [15:0] layer2_out_22_V_reg_2256; +reg [15:0] layer2_out_23_V_reg_2261; +reg [15:0] layer2_out_24_V_reg_2266; +reg [15:0] layer2_out_25_V_reg_2271; +reg [15:0] layer2_out_26_V_reg_2276; +reg [15:0] layer2_out_27_V_reg_2281; +reg [15:0] layer2_out_28_V_reg_2286; +reg [15:0] layer2_out_29_V_reg_2291; +reg [15:0] layer2_out_30_V_reg_2296; +reg [15:0] layer2_out_31_V_reg_2301; +reg [15:0] layer2_out_32_V_reg_2306; +reg [15:0] layer2_out_33_V_reg_2311; +reg [15:0] layer2_out_34_V_reg_2316; +reg [15:0] layer2_out_35_V_reg_2321; +reg [15:0] layer2_out_36_V_reg_2326; +reg [15:0] layer2_out_37_V_reg_2331; +reg [15:0] layer2_out_38_V_reg_2336; +reg [15:0] layer2_out_39_V_reg_2341; +reg [15:0] layer2_out_40_V_reg_2346; +reg [15:0] layer2_out_41_V_reg_2351; +reg [15:0] layer2_out_42_V_reg_2356; +reg [15:0] layer2_out_43_V_reg_2361; +reg [15:0] layer2_out_44_V_reg_2366; +reg [15:0] layer2_out_45_V_reg_2371; +reg [15:0] layer2_out_46_V_reg_2376; +reg [15:0] layer2_out_47_V_reg_2381; +reg [15:0] layer2_out_48_V_reg_2386; +reg [15:0] layer2_out_49_V_reg_2391; +reg [15:0] layer2_out_50_V_reg_2396; +reg [15:0] layer2_out_51_V_reg_2401; +reg [15:0] layer2_out_52_V_reg_2406; +reg [15:0] layer2_out_53_V_reg_2411; +reg [15:0] layer2_out_54_V_reg_2416; +reg [15:0] layer2_out_55_V_reg_2421; +reg [15:0] layer2_out_56_V_reg_2426; +reg [15:0] layer2_out_57_V_reg_2431; +reg [15:0] layer2_out_58_V_reg_2436; +reg [15:0] layer2_out_59_V_reg_2441; +reg [15:0] layer2_out_60_V_reg_2446; +reg [15:0] layer2_out_61_V_reg_2451; +reg [15:0] layer2_out_62_V_reg_2456; +reg [15:0] layer2_out_63_V_reg_2461; +reg [15:0] layer4_out_0_V_reg_2466; +reg [15:0] layer4_out_1_V_reg_2471; +reg [15:0] layer4_out_2_V_reg_2476; +reg [15:0] layer4_out_3_V_reg_2481; +reg [15:0] layer4_out_4_V_reg_2486; +reg [15:0] layer4_out_5_V_reg_2491; +reg [15:0] layer4_out_6_V_reg_2496; +reg [15:0] layer4_out_7_V_reg_2501; +reg [15:0] layer4_out_8_V_reg_2506; +reg [15:0] layer4_out_9_V_reg_2511; +reg [15:0] layer4_out_10_V_reg_2516; +reg [15:0] layer4_out_11_V_reg_2521; +reg [15:0] layer4_out_12_V_reg_2526; +reg [15:0] layer4_out_13_V_reg_2531; +reg [15:0] layer4_out_14_V_reg_2536; +reg [15:0] layer4_out_15_V_reg_2541; +reg [15:0] layer4_out_16_V_reg_2546; +reg [15:0] layer4_out_17_V_reg_2551; +reg [15:0] layer4_out_18_V_reg_2556; +reg [15:0] layer4_out_19_V_reg_2561; +reg [15:0] layer4_out_20_V_reg_2566; +reg [15:0] layer4_out_21_V_reg_2571; +reg [15:0] layer4_out_22_V_reg_2576; +reg [15:0] layer4_out_23_V_reg_2581; +reg [15:0] layer4_out_24_V_reg_2586; +reg [15:0] layer4_out_25_V_reg_2591; +reg [15:0] layer4_out_26_V_reg_2596; +reg [15:0] layer4_out_27_V_reg_2601; +reg [15:0] layer4_out_28_V_reg_2606; +reg [15:0] layer4_out_29_V_reg_2611; +reg [15:0] layer4_out_30_V_reg_2616; +reg [15:0] layer4_out_31_V_reg_2621; +reg [15:0] layer4_out_32_V_reg_2626; +reg [15:0] layer4_out_33_V_reg_2631; +reg [15:0] layer4_out_34_V_reg_2636; +reg [15:0] layer4_out_35_V_reg_2641; +reg [15:0] layer4_out_36_V_reg_2646; +reg [15:0] layer4_out_37_V_reg_2651; +reg [15:0] layer4_out_38_V_reg_2656; +reg [15:0] layer4_out_39_V_reg_2661; +reg [15:0] layer4_out_40_V_reg_2666; +reg [15:0] layer4_out_41_V_reg_2671; +reg [15:0] layer4_out_42_V_reg_2676; +reg [15:0] layer4_out_43_V_reg_2681; +reg [15:0] layer4_out_44_V_reg_2686; +reg [15:0] layer4_out_45_V_reg_2691; +reg [15:0] layer4_out_46_V_reg_2696; +reg [15:0] layer4_out_47_V_reg_2701; +reg [15:0] layer4_out_48_V_reg_2706; +reg [15:0] layer4_out_49_V_reg_2711; +reg [15:0] layer4_out_50_V_reg_2716; +reg [15:0] layer4_out_51_V_reg_2721; +reg [15:0] layer4_out_52_V_reg_2726; +reg [15:0] layer4_out_53_V_reg_2731; +reg [15:0] layer4_out_54_V_reg_2736; +reg [15:0] layer4_out_55_V_reg_2741; +reg [15:0] layer4_out_56_V_reg_2746; +reg [15:0] layer4_out_57_V_reg_2751; +reg [15:0] layer4_out_58_V_reg_2756; +reg [15:0] layer4_out_59_V_reg_2761; +reg [15:0] layer4_out_60_V_reg_2766; +reg [15:0] layer4_out_61_V_reg_2771; +reg [15:0] layer4_out_62_V_reg_2776; +reg [15:0] layer4_out_63_V_reg_2781; +reg [15:0] layer5_out_0_V_reg_2786; +reg [15:0] layer5_out_1_V_reg_2791; +reg [15:0] layer5_out_2_V_reg_2796; +reg [15:0] layer5_out_3_V_reg_2801; +reg [15:0] layer5_out_4_V_reg_2806; +reg [15:0] layer5_out_5_V_reg_2811; +reg [15:0] layer5_out_6_V_reg_2816; +reg [15:0] layer5_out_7_V_reg_2821; +reg [15:0] layer5_out_8_V_reg_2826; +reg [15:0] layer5_out_9_V_reg_2831; +reg [15:0] layer5_out_10_V_reg_2836; +reg [15:0] layer5_out_11_V_reg_2841; +reg [15:0] layer5_out_12_V_reg_2846; +reg [15:0] layer5_out_13_V_reg_2851; +reg [15:0] layer5_out_14_V_reg_2856; +reg [15:0] layer5_out_15_V_reg_2861; +reg [15:0] layer5_out_16_V_reg_2866; +reg [15:0] layer5_out_17_V_reg_2871; +reg [15:0] layer5_out_18_V_reg_2876; +reg [15:0] layer5_out_19_V_reg_2881; +reg [15:0] layer5_out_20_V_reg_2886; +reg [15:0] layer5_out_21_V_reg_2891; +reg [15:0] layer5_out_22_V_reg_2896; +reg [15:0] layer5_out_23_V_reg_2901; +reg [15:0] layer5_out_24_V_reg_2906; +reg [15:0] layer5_out_25_V_reg_2911; +reg [15:0] layer5_out_26_V_reg_2916; +reg [15:0] layer5_out_27_V_reg_2921; +reg [15:0] layer5_out_28_V_reg_2926; +reg [15:0] layer5_out_29_V_reg_2931; +reg [15:0] layer5_out_30_V_reg_2936; +reg [15:0] layer5_out_31_V_reg_2941; +reg [15:0] layer5_out_32_V_reg_2946; +reg [15:0] layer5_out_33_V_reg_2951; +reg [15:0] layer5_out_34_V_reg_2956; +reg [15:0] layer5_out_35_V_reg_2961; +reg [15:0] layer5_out_36_V_reg_2966; +reg [15:0] layer5_out_37_V_reg_2971; +reg [15:0] layer5_out_38_V_reg_2976; +reg [15:0] layer5_out_39_V_reg_2981; +reg [15:0] layer5_out_40_V_reg_2986; +reg [15:0] layer5_out_41_V_reg_2991; +reg [15:0] layer5_out_42_V_reg_2996; +reg [15:0] layer5_out_43_V_reg_3001; +reg [15:0] layer5_out_44_V_reg_3006; +reg [15:0] layer5_out_45_V_reg_3011; +reg [15:0] layer5_out_46_V_reg_3016; +reg [15:0] layer5_out_47_V_reg_3021; +reg [15:0] layer5_out_48_V_reg_3026; +reg [15:0] layer5_out_49_V_reg_3031; +reg [15:0] layer5_out_50_V_reg_3036; +reg [15:0] layer5_out_51_V_reg_3041; +reg [15:0] layer5_out_52_V_reg_3046; +reg [15:0] layer5_out_53_V_reg_3051; +reg [15:0] layer5_out_54_V_reg_3056; +reg [15:0] layer5_out_55_V_reg_3061; +reg [15:0] layer5_out_56_V_reg_3066; +reg [15:0] layer5_out_57_V_reg_3071; +reg [15:0] layer5_out_58_V_reg_3076; +reg [15:0] layer5_out_59_V_reg_3081; +reg [15:0] layer5_out_60_V_reg_3086; +reg [15:0] layer5_out_61_V_reg_3091; +reg [15:0] layer5_out_62_V_reg_3096; +reg [15:0] layer5_out_63_V_reg_3101; +reg [15:0] layer6_out_0_V_reg_3106; +reg [15:0] layer6_out_1_V_reg_3111; +reg [15:0] layer6_out_2_V_reg_3116; +reg [15:0] layer6_out_3_V_reg_3121; +reg [15:0] layer6_out_4_V_reg_3126; +reg [15:0] layer6_out_5_V_reg_3131; +reg [15:0] layer6_out_6_V_reg_3136; +reg [15:0] layer6_out_7_V_reg_3141; +reg [15:0] layer6_out_8_V_reg_3146; +reg [15:0] layer6_out_9_V_reg_3151; +reg [15:0] layer6_out_10_V_reg_3156; +reg [15:0] layer6_out_11_V_reg_3161; +reg [15:0] layer6_out_12_V_reg_3166; +reg [15:0] layer6_out_13_V_reg_3171; +reg [15:0] layer6_out_14_V_reg_3176; +reg [15:0] layer6_out_15_V_reg_3181; +reg [15:0] layer6_out_16_V_reg_3186; +reg [15:0] layer6_out_17_V_reg_3191; +reg [15:0] layer6_out_18_V_reg_3196; +reg [15:0] layer6_out_19_V_reg_3201; +reg [15:0] layer6_out_20_V_reg_3206; +reg [15:0] layer6_out_21_V_reg_3211; +reg [15:0] layer6_out_22_V_reg_3216; +reg [15:0] layer6_out_23_V_reg_3221; +reg [15:0] layer6_out_24_V_reg_3226; +reg [15:0] layer6_out_25_V_reg_3231; +reg [15:0] layer6_out_26_V_reg_3236; +reg [15:0] layer6_out_27_V_reg_3241; +reg [15:0] layer6_out_28_V_reg_3246; +reg [15:0] layer6_out_29_V_reg_3251; +reg [15:0] layer6_out_30_V_reg_3256; +reg [15:0] layer6_out_31_V_reg_3261; +reg [15:0] layer8_out_0_V_reg_3266; +reg [15:0] layer8_out_1_V_reg_3271; +reg [15:0] layer8_out_2_V_reg_3276; +reg [15:0] layer8_out_3_V_reg_3281; +reg [15:0] layer8_out_4_V_reg_3286; +reg [15:0] layer8_out_5_V_reg_3291; +reg [15:0] layer8_out_6_V_reg_3296; +reg [15:0] layer8_out_7_V_reg_3301; +reg [15:0] layer8_out_8_V_reg_3306; +reg [15:0] layer8_out_9_V_reg_3311; +reg [15:0] layer8_out_10_V_reg_3316; +reg [15:0] layer8_out_11_V_reg_3321; +reg [15:0] layer8_out_12_V_reg_3326; +reg [15:0] layer8_out_13_V_reg_3331; +reg [15:0] layer8_out_14_V_reg_3336; +reg [15:0] layer8_out_15_V_reg_3341; +reg [15:0] layer8_out_16_V_reg_3346; +reg [15:0] layer8_out_17_V_reg_3351; +reg [15:0] layer8_out_18_V_reg_3356; +reg [15:0] layer8_out_19_V_reg_3361; +reg [15:0] layer8_out_20_V_reg_3366; +reg [15:0] layer8_out_21_V_reg_3371; +reg [15:0] layer8_out_22_V_reg_3376; +reg [15:0] layer8_out_23_V_reg_3381; +reg [15:0] layer8_out_24_V_reg_3386; +reg [15:0] layer8_out_25_V_reg_3391; +reg [15:0] layer8_out_26_V_reg_3396; +reg [15:0] layer8_out_27_V_reg_3401; +reg [15:0] layer8_out_28_V_reg_3406; +reg [15:0] layer8_out_29_V_reg_3411; +reg [15:0] layer8_out_30_V_reg_3416; +reg [15:0] layer8_out_31_V_reg_3421; +reg [15:0] layer9_out_0_V_reg_3426; +reg [15:0] layer9_out_1_V_reg_3431; +reg [15:0] layer9_out_2_V_reg_3436; +reg [15:0] layer9_out_3_V_reg_3441; +reg [15:0] layer9_out_4_V_reg_3446; +reg [15:0] layer9_out_5_V_reg_3451; +reg [15:0] layer9_out_6_V_reg_3456; +reg [15:0] layer9_out_7_V_reg_3461; +reg [15:0] layer9_out_8_V_reg_3466; +reg [15:0] layer9_out_9_V_reg_3471; +reg [15:0] layer9_out_10_V_reg_3476; +reg [15:0] layer9_out_11_V_reg_3481; +reg [15:0] layer9_out_12_V_reg_3486; +reg [15:0] layer9_out_13_V_reg_3491; +reg [15:0] layer9_out_14_V_reg_3496; +reg [15:0] layer9_out_15_V_reg_3501; +reg [15:0] layer9_out_16_V_reg_3506; +reg [15:0] layer9_out_17_V_reg_3511; +reg [15:0] layer9_out_18_V_reg_3516; +reg [15:0] layer9_out_19_V_reg_3521; +reg [15:0] layer9_out_20_V_reg_3526; +reg [15:0] layer9_out_21_V_reg_3531; +reg [15:0] layer9_out_22_V_reg_3536; +reg [15:0] layer9_out_23_V_reg_3541; +reg [15:0] layer9_out_24_V_reg_3546; +reg [15:0] layer9_out_25_V_reg_3551; +reg [15:0] layer9_out_26_V_reg_3556; +reg [15:0] layer9_out_27_V_reg_3561; +reg [15:0] layer9_out_28_V_reg_3566; +reg [15:0] layer9_out_29_V_reg_3571; +reg [15:0] layer9_out_30_V_reg_3576; +reg [15:0] layer9_out_31_V_reg_3581; +reg [15:0] layer10_out_0_V_reg_3586; +reg [15:0] layer10_out_1_V_reg_3591; +reg [15:0] layer10_out_2_V_reg_3596; +reg [15:0] layer10_out_3_V_reg_3601; +reg [15:0] layer10_out_4_V_reg_3606; +reg [15:0] layer10_out_5_V_reg_3611; +reg [15:0] layer10_out_6_V_reg_3616; +reg [15:0] layer10_out_7_V_reg_3621; +reg [15:0] layer10_out_8_V_reg_3626; +reg [15:0] layer10_out_9_V_reg_3631; +reg [15:0] layer10_out_10_V_reg_3636; +reg [15:0] layer10_out_11_V_reg_3641; +reg [15:0] layer10_out_12_V_reg_3646; +reg [15:0] layer10_out_13_V_reg_3651; +reg [15:0] layer10_out_14_V_reg_3656; +reg [15:0] layer10_out_15_V_reg_3661; +reg [15:0] layer10_out_16_V_reg_3666; +reg [15:0] layer10_out_17_V_reg_3671; +reg [15:0] layer10_out_18_V_reg_3676; +reg [15:0] layer10_out_19_V_reg_3681; +reg [15:0] layer10_out_20_V_reg_3686; +reg [15:0] layer10_out_21_V_reg_3691; +reg [15:0] layer10_out_22_V_reg_3696; +reg [15:0] layer10_out_23_V_reg_3701; +reg [15:0] layer10_out_24_V_reg_3706; +reg [15:0] layer10_out_25_V_reg_3711; +reg [15:0] layer10_out_26_V_reg_3716; +reg [15:0] layer10_out_27_V_reg_3721; +reg [15:0] layer10_out_28_V_reg_3726; +reg [15:0] layer10_out_29_V_reg_3731; +reg [15:0] layer10_out_30_V_reg_3736; +reg [15:0] layer10_out_31_V_reg_3741; +reg [15:0] layer12_out_0_V_reg_3746; +reg [15:0] layer12_out_1_V_reg_3751; +reg [15:0] layer12_out_2_V_reg_3756; +reg [15:0] layer12_out_3_V_reg_3761; +reg [15:0] layer12_out_4_V_reg_3766; +reg [15:0] layer12_out_5_V_reg_3771; +reg [15:0] layer12_out_6_V_reg_3776; +reg [15:0] layer12_out_7_V_reg_3781; +reg [15:0] layer12_out_8_V_reg_3786; +reg [15:0] layer12_out_9_V_reg_3791; +reg [15:0] layer12_out_10_V_reg_3796; +reg [15:0] layer12_out_11_V_reg_3801; +reg [15:0] layer12_out_12_V_reg_3806; +reg [15:0] layer12_out_13_V_reg_3811; +reg [15:0] layer12_out_14_V_reg_3816; +reg [15:0] layer12_out_15_V_reg_3821; +reg [15:0] layer12_out_16_V_reg_3826; +reg [15:0] layer12_out_17_V_reg_3831; +reg [15:0] layer12_out_18_V_reg_3836; +reg [15:0] layer12_out_19_V_reg_3841; +reg [15:0] layer12_out_20_V_reg_3846; +reg [15:0] layer12_out_21_V_reg_3851; +reg [15:0] layer12_out_22_V_reg_3856; +reg [15:0] layer12_out_23_V_reg_3861; +reg [15:0] layer12_out_24_V_reg_3866; +reg [15:0] layer12_out_25_V_reg_3871; +reg [15:0] layer12_out_26_V_reg_3876; +reg [15:0] layer12_out_27_V_reg_3881; +reg [15:0] layer12_out_28_V_reg_3886; +reg [15:0] layer12_out_29_V_reg_3891; +reg [15:0] layer12_out_30_V_reg_3896; +reg [15:0] layer12_out_31_V_reg_3901; +reg [15:0] layer13_out_0_V_reg_3906; +reg [15:0] layer13_out_1_V_reg_3911; +reg [15:0] layer13_out_2_V_reg_3916; +reg [15:0] layer13_out_3_V_reg_3921; +reg [15:0] layer13_out_4_V_reg_3926; +reg [15:0] layer13_out_5_V_reg_3931; +reg [15:0] layer13_out_6_V_reg_3936; +reg [15:0] layer13_out_7_V_reg_3941; +reg [15:0] layer13_out_8_V_reg_3946; +reg [15:0] layer13_out_9_V_reg_3951; +reg [15:0] layer13_out_10_V_reg_3956; +reg [15:0] layer13_out_11_V_reg_3961; +reg [15:0] layer13_out_12_V_reg_3966; +reg [15:0] layer13_out_13_V_reg_3971; +reg [15:0] layer13_out_14_V_reg_3976; +reg [15:0] layer13_out_15_V_reg_3981; +reg [15:0] layer13_out_16_V_reg_3986; +reg [15:0] layer13_out_17_V_reg_3991; +reg [15:0] layer13_out_18_V_reg_3996; +reg [15:0] layer13_out_19_V_reg_4001; +reg [15:0] layer13_out_20_V_reg_4006; +reg [15:0] layer13_out_21_V_reg_4011; +reg [15:0] layer13_out_22_V_reg_4016; +reg [15:0] layer13_out_23_V_reg_4021; +reg [15:0] layer13_out_24_V_reg_4026; +reg [15:0] layer13_out_25_V_reg_4031; +reg [15:0] layer13_out_26_V_reg_4036; +reg [15:0] layer13_out_27_V_reg_4041; +reg [15:0] layer13_out_28_V_reg_4046; +reg [15:0] layer13_out_29_V_reg_4051; +reg [15:0] layer13_out_30_V_reg_4056; +reg [15:0] layer13_out_31_V_reg_4061; +reg [15:0] layer14_out_0_V_reg_4066; +reg [15:0] layer14_out_1_V_reg_4071; +reg [15:0] layer14_out_2_V_reg_4076; +reg [15:0] layer14_out_3_V_reg_4081; +reg [15:0] layer14_out_4_V_reg_4086; +reg ap_block_pp0_stage0_subdone; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_0; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_1; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_2; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_3; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_4; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_5; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_6; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_7; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_8; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_9; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_10; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_11; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_12; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_13; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_14; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_15; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_16; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_17; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_18; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_19; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_20; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_21; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_22; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_23; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_24; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_25; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_26; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_27; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_28; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_29; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_30; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_31; +reg grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_ce; +reg ap_block_state1_pp0_stage0_iter0_ignore_call210; +wire ap_block_state2_pp0_stage0_iter1_ignore_call210; +wire ap_block_state3_pp0_stage0_iter2_ignore_call210; +wire ap_block_state4_pp0_stage0_iter3_ignore_call210; +wire ap_block_state5_pp0_stage0_iter4_ignore_call210; +wire ap_block_state6_pp0_stage0_iter5_ignore_call210; +wire ap_block_state7_pp0_stage0_iter6_ignore_call210; +wire ap_block_state8_pp0_stage0_iter7_ignore_call210; +wire ap_block_state9_pp0_stage0_iter8_ignore_call210; +wire ap_block_state10_pp0_stage0_iter9_ignore_call210; +wire ap_block_state11_pp0_stage0_iter10_ignore_call210; +wire ap_block_state12_pp0_stage0_iter11_ignore_call210; +wire ap_block_state13_pp0_stage0_iter12_ignore_call210; +wire ap_block_state14_pp0_stage0_iter13_ignore_call210; +wire ap_block_state15_pp0_stage0_iter14_ignore_call210; +wire ap_block_state16_pp0_stage0_iter15_ignore_call210; +wire ap_block_state17_pp0_stage0_iter16_ignore_call210; +wire ap_block_state18_pp0_stage0_iter17_ignore_call210; +wire ap_block_state19_pp0_stage0_iter18_ignore_call210; +wire ap_block_state20_pp0_stage0_iter19_ignore_call210; +wire ap_block_state21_pp0_stage0_iter20_ignore_call210; +wire ap_block_state22_pp0_stage0_iter21_ignore_call210; +wire ap_block_state23_pp0_stage0_iter22_ignore_call210; +wire ap_block_state24_pp0_stage0_iter23_ignore_call210; +wire ap_block_state25_pp0_stage0_iter24_ignore_call210; +wire ap_block_state26_pp0_stage0_iter25_ignore_call210; +wire ap_block_state27_pp0_stage0_iter26_ignore_call210; +wire ap_block_state28_pp0_stage0_iter27_ignore_call210; +wire ap_block_state29_pp0_stage0_iter28_ignore_call210; +wire ap_block_state30_pp0_stage0_iter29_ignore_call210; +wire ap_block_state31_pp0_stage0_iter30_ignore_call210; +wire ap_block_state32_pp0_stage0_iter31_ignore_call210; +wire ap_block_state33_pp0_stage0_iter32_ignore_call210; +wire ap_block_state34_pp0_stage0_iter33_ignore_call210; +wire ap_block_state35_pp0_stage0_iter34_ignore_call210; +wire ap_block_state36_pp0_stage0_iter35_ignore_call210; +wire ap_block_state37_pp0_stage0_iter36_ignore_call210; +wire ap_block_state38_pp0_stage0_iter37_ignore_call210; +wire ap_block_state39_pp0_stage0_iter38_ignore_call210; +wire ap_block_state40_pp0_stage0_iter39_ignore_call210; +wire ap_block_state41_pp0_stage0_iter40_ignore_call210; +wire ap_block_state42_pp0_stage0_iter41_ignore_call210; +wire ap_block_state43_pp0_stage0_iter42_ignore_call210; +wire ap_block_state44_pp0_stage0_iter43_ignore_call210; +wire ap_block_state45_pp0_stage0_iter44_ignore_call210; +wire ap_block_state46_pp0_stage0_iter45_ignore_call210; +wire ap_block_state47_pp0_stage0_iter46_ignore_call210; +wire ap_block_state48_pp0_stage0_iter47_ignore_call210; +wire ap_block_state49_pp0_stage0_iter48_ignore_call210; +wire ap_block_state50_pp0_stage0_iter49_ignore_call210; +wire ap_block_state51_pp0_stage0_iter50_ignore_call210; +wire ap_block_state52_pp0_stage0_iter51_ignore_call210; +wire ap_block_state53_pp0_stage0_iter52_ignore_call210; +wire ap_block_state54_pp0_stage0_iter53_ignore_call210; +wire ap_block_state55_pp0_stage0_iter54_ignore_call210; +wire ap_block_state56_pp0_stage0_iter55_ignore_call210; +wire ap_block_state57_pp0_stage0_iter56_ignore_call210; +wire ap_block_state58_pp0_stage0_iter57_ignore_call210; +wire ap_block_state59_pp0_stage0_iter58_ignore_call210; +wire ap_block_state60_pp0_stage0_iter59_ignore_call210; +wire ap_block_state61_pp0_stage0_iter60_ignore_call210; +wire ap_block_state62_pp0_stage0_iter61_ignore_call210; +wire ap_block_state63_pp0_stage0_iter62_ignore_call210; +wire ap_block_state64_pp0_stage0_iter63_ignore_call210; +wire ap_block_state65_pp0_stage0_iter64_ignore_call210; +wire ap_block_state66_pp0_stage0_iter65_ignore_call210; +wire ap_block_state67_pp0_stage0_iter66_ignore_call210; +wire ap_block_state68_pp0_stage0_iter67_ignore_call210; +reg ap_block_pp0_stage0_11001_ignoreCallOp277; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_0; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_1; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_2; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_3; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_4; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_5; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_6; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_7; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_8; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_9; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_10; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_11; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_12; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_13; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_14; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_15; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_16; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_17; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_18; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_19; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_20; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_21; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_22; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_23; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_24; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_25; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_26; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_27; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_28; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_29; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_30; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_31; +reg grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_ce; +reg ap_block_state1_pp0_stage0_iter0_ignore_call309; +wire ap_block_state2_pp0_stage0_iter1_ignore_call309; +wire ap_block_state3_pp0_stage0_iter2_ignore_call309; +wire ap_block_state4_pp0_stage0_iter3_ignore_call309; +wire ap_block_state5_pp0_stage0_iter4_ignore_call309; +wire ap_block_state6_pp0_stage0_iter5_ignore_call309; +wire ap_block_state7_pp0_stage0_iter6_ignore_call309; +wire ap_block_state8_pp0_stage0_iter7_ignore_call309; +wire ap_block_state9_pp0_stage0_iter8_ignore_call309; +wire ap_block_state10_pp0_stage0_iter9_ignore_call309; +wire ap_block_state11_pp0_stage0_iter10_ignore_call309; +wire ap_block_state12_pp0_stage0_iter11_ignore_call309; +wire ap_block_state13_pp0_stage0_iter12_ignore_call309; +wire ap_block_state14_pp0_stage0_iter13_ignore_call309; +wire ap_block_state15_pp0_stage0_iter14_ignore_call309; +wire ap_block_state16_pp0_stage0_iter15_ignore_call309; +wire ap_block_state17_pp0_stage0_iter16_ignore_call309; +wire ap_block_state18_pp0_stage0_iter17_ignore_call309; +wire ap_block_state19_pp0_stage0_iter18_ignore_call309; +wire ap_block_state20_pp0_stage0_iter19_ignore_call309; +wire ap_block_state21_pp0_stage0_iter20_ignore_call309; +wire ap_block_state22_pp0_stage0_iter21_ignore_call309; +wire ap_block_state23_pp0_stage0_iter22_ignore_call309; +wire ap_block_state24_pp0_stage0_iter23_ignore_call309; +wire ap_block_state25_pp0_stage0_iter24_ignore_call309; +wire ap_block_state26_pp0_stage0_iter25_ignore_call309; +wire ap_block_state27_pp0_stage0_iter26_ignore_call309; +wire ap_block_state28_pp0_stage0_iter27_ignore_call309; +wire ap_block_state29_pp0_stage0_iter28_ignore_call309; +wire ap_block_state30_pp0_stage0_iter29_ignore_call309; +wire ap_block_state31_pp0_stage0_iter30_ignore_call309; +wire ap_block_state32_pp0_stage0_iter31_ignore_call309; +wire ap_block_state33_pp0_stage0_iter32_ignore_call309; +wire ap_block_state34_pp0_stage0_iter33_ignore_call309; +wire ap_block_state35_pp0_stage0_iter34_ignore_call309; +wire ap_block_state36_pp0_stage0_iter35_ignore_call309; +wire ap_block_state37_pp0_stage0_iter36_ignore_call309; +wire ap_block_state38_pp0_stage0_iter37_ignore_call309; +wire ap_block_state39_pp0_stage0_iter38_ignore_call309; +wire ap_block_state40_pp0_stage0_iter39_ignore_call309; +wire ap_block_state41_pp0_stage0_iter40_ignore_call309; +wire ap_block_state42_pp0_stage0_iter41_ignore_call309; +wire ap_block_state43_pp0_stage0_iter42_ignore_call309; +wire ap_block_state44_pp0_stage0_iter43_ignore_call309; +wire ap_block_state45_pp0_stage0_iter44_ignore_call309; +wire ap_block_state46_pp0_stage0_iter45_ignore_call309; +wire ap_block_state47_pp0_stage0_iter46_ignore_call309; +wire ap_block_state48_pp0_stage0_iter47_ignore_call309; +wire ap_block_state49_pp0_stage0_iter48_ignore_call309; +wire ap_block_state50_pp0_stage0_iter49_ignore_call309; +wire ap_block_state51_pp0_stage0_iter50_ignore_call309; +wire ap_block_state52_pp0_stage0_iter51_ignore_call309; +wire ap_block_state53_pp0_stage0_iter52_ignore_call309; +wire ap_block_state54_pp0_stage0_iter53_ignore_call309; +wire ap_block_state55_pp0_stage0_iter54_ignore_call309; +wire ap_block_state56_pp0_stage0_iter55_ignore_call309; +wire ap_block_state57_pp0_stage0_iter56_ignore_call309; +wire ap_block_state58_pp0_stage0_iter57_ignore_call309; +wire ap_block_state59_pp0_stage0_iter58_ignore_call309; +wire ap_block_state60_pp0_stage0_iter59_ignore_call309; +wire ap_block_state61_pp0_stage0_iter60_ignore_call309; +wire ap_block_state62_pp0_stage0_iter61_ignore_call309; +wire ap_block_state63_pp0_stage0_iter62_ignore_call309; +wire ap_block_state64_pp0_stage0_iter63_ignore_call309; +wire ap_block_state65_pp0_stage0_iter64_ignore_call309; +wire ap_block_state66_pp0_stage0_iter65_ignore_call309; +wire ap_block_state67_pp0_stage0_iter66_ignore_call309; +wire ap_block_state68_pp0_stage0_iter67_ignore_call309; +reg ap_block_pp0_stage0_11001_ignoreCallOp397; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_0; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_1; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_2; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_3; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_4; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_5; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_6; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_7; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_8; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_9; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_10; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_11; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_12; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_13; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_14; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_15; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_16; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_17; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_18; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_19; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_20; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_21; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_22; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_23; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_24; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_25; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_26; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_27; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_28; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_29; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_30; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_31; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_32; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_33; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_34; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_35; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_36; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_37; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_38; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_39; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_40; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_41; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_42; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_43; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_44; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_45; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_46; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_47; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_48; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_49; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_50; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_51; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_52; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_53; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_54; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_55; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_56; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_57; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_58; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_59; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_60; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_61; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_62; +wire [15:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_63; +reg grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_ce; +reg ap_block_state1_pp0_stage0_iter0_ignore_call15; +wire ap_block_state2_pp0_stage0_iter1_ignore_call15; +wire ap_block_state3_pp0_stage0_iter2_ignore_call15; +wire ap_block_state4_pp0_stage0_iter3_ignore_call15; +wire ap_block_state5_pp0_stage0_iter4_ignore_call15; +wire ap_block_state6_pp0_stage0_iter5_ignore_call15; +wire ap_block_state7_pp0_stage0_iter6_ignore_call15; +wire ap_block_state8_pp0_stage0_iter7_ignore_call15; +wire ap_block_state9_pp0_stage0_iter8_ignore_call15; +wire ap_block_state10_pp0_stage0_iter9_ignore_call15; +wire ap_block_state11_pp0_stage0_iter10_ignore_call15; +wire ap_block_state12_pp0_stage0_iter11_ignore_call15; +wire ap_block_state13_pp0_stage0_iter12_ignore_call15; +wire ap_block_state14_pp0_stage0_iter13_ignore_call15; +wire ap_block_state15_pp0_stage0_iter14_ignore_call15; +wire ap_block_state16_pp0_stage0_iter15_ignore_call15; +wire ap_block_state17_pp0_stage0_iter16_ignore_call15; +wire ap_block_state18_pp0_stage0_iter17_ignore_call15; +wire ap_block_state19_pp0_stage0_iter18_ignore_call15; +wire ap_block_state20_pp0_stage0_iter19_ignore_call15; +wire ap_block_state21_pp0_stage0_iter20_ignore_call15; +wire ap_block_state22_pp0_stage0_iter21_ignore_call15; +wire ap_block_state23_pp0_stage0_iter22_ignore_call15; +wire ap_block_state24_pp0_stage0_iter23_ignore_call15; +wire ap_block_state25_pp0_stage0_iter24_ignore_call15; +wire ap_block_state26_pp0_stage0_iter25_ignore_call15; +wire ap_block_state27_pp0_stage0_iter26_ignore_call15; +wire ap_block_state28_pp0_stage0_iter27_ignore_call15; +wire ap_block_state29_pp0_stage0_iter28_ignore_call15; +wire ap_block_state30_pp0_stage0_iter29_ignore_call15; +wire ap_block_state31_pp0_stage0_iter30_ignore_call15; +wire ap_block_state32_pp0_stage0_iter31_ignore_call15; +wire ap_block_state33_pp0_stage0_iter32_ignore_call15; +wire ap_block_state34_pp0_stage0_iter33_ignore_call15; +wire ap_block_state35_pp0_stage0_iter34_ignore_call15; +wire ap_block_state36_pp0_stage0_iter35_ignore_call15; +wire ap_block_state37_pp0_stage0_iter36_ignore_call15; +wire ap_block_state38_pp0_stage0_iter37_ignore_call15; +wire ap_block_state39_pp0_stage0_iter38_ignore_call15; +wire ap_block_state40_pp0_stage0_iter39_ignore_call15; +wire ap_block_state41_pp0_stage0_iter40_ignore_call15; +wire ap_block_state42_pp0_stage0_iter41_ignore_call15; +wire ap_block_state43_pp0_stage0_iter42_ignore_call15; +wire ap_block_state44_pp0_stage0_iter43_ignore_call15; +wire ap_block_state45_pp0_stage0_iter44_ignore_call15; +wire ap_block_state46_pp0_stage0_iter45_ignore_call15; +wire ap_block_state47_pp0_stage0_iter46_ignore_call15; +wire ap_block_state48_pp0_stage0_iter47_ignore_call15; +wire ap_block_state49_pp0_stage0_iter48_ignore_call15; +wire ap_block_state50_pp0_stage0_iter49_ignore_call15; +wire ap_block_state51_pp0_stage0_iter50_ignore_call15; +wire ap_block_state52_pp0_stage0_iter51_ignore_call15; +wire ap_block_state53_pp0_stage0_iter52_ignore_call15; +wire ap_block_state54_pp0_stage0_iter53_ignore_call15; +wire ap_block_state55_pp0_stage0_iter54_ignore_call15; +wire ap_block_state56_pp0_stage0_iter55_ignore_call15; +wire ap_block_state57_pp0_stage0_iter56_ignore_call15; +wire ap_block_state58_pp0_stage0_iter57_ignore_call15; +wire ap_block_state59_pp0_stage0_iter58_ignore_call15; +wire ap_block_state60_pp0_stage0_iter59_ignore_call15; +wire ap_block_state61_pp0_stage0_iter60_ignore_call15; +wire ap_block_state62_pp0_stage0_iter61_ignore_call15; +wire ap_block_state63_pp0_stage0_iter62_ignore_call15; +wire ap_block_state64_pp0_stage0_iter63_ignore_call15; +wire ap_block_state65_pp0_stage0_iter64_ignore_call15; +wire ap_block_state66_pp0_stage0_iter65_ignore_call15; +wire ap_block_state67_pp0_stage0_iter66_ignore_call15; +wire ap_block_state68_pp0_stage0_iter67_ignore_call15; +reg ap_block_pp0_stage0_11001_ignoreCallOp70; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_0; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_1; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_2; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_3; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_4; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_5; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_6; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_7; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_8; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_9; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_10; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_11; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_12; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_13; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_14; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_15; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_16; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_17; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_18; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_19; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_20; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_21; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_22; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_23; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_24; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_25; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_26; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_27; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_28; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_29; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_30; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_31; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_32; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_33; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_34; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_35; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_36; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_37; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_38; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_39; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_40; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_41; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_42; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_43; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_44; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_45; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_46; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_47; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_48; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_49; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_50; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_51; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_52; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_53; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_54; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_55; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_56; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_57; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_58; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_59; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_60; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_61; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_62; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_63; +reg grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_ce; +reg ap_block_state1_pp0_stage0_iter0_ignore_call80; +wire ap_block_state2_pp0_stage0_iter1_ignore_call80; +wire ap_block_state3_pp0_stage0_iter2_ignore_call80; +wire ap_block_state4_pp0_stage0_iter3_ignore_call80; +wire ap_block_state5_pp0_stage0_iter4_ignore_call80; +wire ap_block_state6_pp0_stage0_iter5_ignore_call80; +wire ap_block_state7_pp0_stage0_iter6_ignore_call80; +wire ap_block_state8_pp0_stage0_iter7_ignore_call80; +wire ap_block_state9_pp0_stage0_iter8_ignore_call80; +wire ap_block_state10_pp0_stage0_iter9_ignore_call80; +wire ap_block_state11_pp0_stage0_iter10_ignore_call80; +wire ap_block_state12_pp0_stage0_iter11_ignore_call80; +wire ap_block_state13_pp0_stage0_iter12_ignore_call80; +wire ap_block_state14_pp0_stage0_iter13_ignore_call80; +wire ap_block_state15_pp0_stage0_iter14_ignore_call80; +wire ap_block_state16_pp0_stage0_iter15_ignore_call80; +wire ap_block_state17_pp0_stage0_iter16_ignore_call80; +wire ap_block_state18_pp0_stage0_iter17_ignore_call80; +wire ap_block_state19_pp0_stage0_iter18_ignore_call80; +wire ap_block_state20_pp0_stage0_iter19_ignore_call80; +wire ap_block_state21_pp0_stage0_iter20_ignore_call80; +wire ap_block_state22_pp0_stage0_iter21_ignore_call80; +wire ap_block_state23_pp0_stage0_iter22_ignore_call80; +wire ap_block_state24_pp0_stage0_iter23_ignore_call80; +wire ap_block_state25_pp0_stage0_iter24_ignore_call80; +wire ap_block_state26_pp0_stage0_iter25_ignore_call80; +wire ap_block_state27_pp0_stage0_iter26_ignore_call80; +wire ap_block_state28_pp0_stage0_iter27_ignore_call80; +wire ap_block_state29_pp0_stage0_iter28_ignore_call80; +wire ap_block_state30_pp0_stage0_iter29_ignore_call80; +wire ap_block_state31_pp0_stage0_iter30_ignore_call80; +wire ap_block_state32_pp0_stage0_iter31_ignore_call80; +wire ap_block_state33_pp0_stage0_iter32_ignore_call80; +wire ap_block_state34_pp0_stage0_iter33_ignore_call80; +wire ap_block_state35_pp0_stage0_iter34_ignore_call80; +wire ap_block_state36_pp0_stage0_iter35_ignore_call80; +wire ap_block_state37_pp0_stage0_iter36_ignore_call80; +wire ap_block_state38_pp0_stage0_iter37_ignore_call80; +wire ap_block_state39_pp0_stage0_iter38_ignore_call80; +wire ap_block_state40_pp0_stage0_iter39_ignore_call80; +wire ap_block_state41_pp0_stage0_iter40_ignore_call80; +wire ap_block_state42_pp0_stage0_iter41_ignore_call80; +wire ap_block_state43_pp0_stage0_iter42_ignore_call80; +wire ap_block_state44_pp0_stage0_iter43_ignore_call80; +wire ap_block_state45_pp0_stage0_iter44_ignore_call80; +wire ap_block_state46_pp0_stage0_iter45_ignore_call80; +wire ap_block_state47_pp0_stage0_iter46_ignore_call80; +wire ap_block_state48_pp0_stage0_iter47_ignore_call80; +wire ap_block_state49_pp0_stage0_iter48_ignore_call80; +wire ap_block_state50_pp0_stage0_iter49_ignore_call80; +wire ap_block_state51_pp0_stage0_iter50_ignore_call80; +wire ap_block_state52_pp0_stage0_iter51_ignore_call80; +wire ap_block_state53_pp0_stage0_iter52_ignore_call80; +wire ap_block_state54_pp0_stage0_iter53_ignore_call80; +wire ap_block_state55_pp0_stage0_iter54_ignore_call80; +wire ap_block_state56_pp0_stage0_iter55_ignore_call80; +wire ap_block_state57_pp0_stage0_iter56_ignore_call80; +wire ap_block_state58_pp0_stage0_iter57_ignore_call80; +wire ap_block_state59_pp0_stage0_iter58_ignore_call80; +wire ap_block_state60_pp0_stage0_iter59_ignore_call80; +wire ap_block_state61_pp0_stage0_iter60_ignore_call80; +wire ap_block_state62_pp0_stage0_iter61_ignore_call80; +wire ap_block_state63_pp0_stage0_iter62_ignore_call80; +wire ap_block_state64_pp0_stage0_iter63_ignore_call80; +wire ap_block_state65_pp0_stage0_iter64_ignore_call80; +wire ap_block_state66_pp0_stage0_iter65_ignore_call80; +wire ap_block_state67_pp0_stage0_iter66_ignore_call80; +wire ap_block_state68_pp0_stage0_iter67_ignore_call80; +reg ap_block_pp0_stage0_11001_ignoreCallOp144; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_0; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_1; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_2; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_3; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_4; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_5; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_6; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_7; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_8; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_9; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_10; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_11; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_12; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_13; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_14; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_15; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_16; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_17; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_18; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_19; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_20; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_21; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_22; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_23; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_24; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_25; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_26; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_27; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_28; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_29; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_30; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_31; +reg grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_ce; +reg ap_block_state1_pp0_stage0_iter0_ignore_call342; +wire ap_block_state2_pp0_stage0_iter1_ignore_call342; +wire ap_block_state3_pp0_stage0_iter2_ignore_call342; +wire ap_block_state4_pp0_stage0_iter3_ignore_call342; +wire ap_block_state5_pp0_stage0_iter4_ignore_call342; +wire ap_block_state6_pp0_stage0_iter5_ignore_call342; +wire ap_block_state7_pp0_stage0_iter6_ignore_call342; +wire ap_block_state8_pp0_stage0_iter7_ignore_call342; +wire ap_block_state9_pp0_stage0_iter8_ignore_call342; +wire ap_block_state10_pp0_stage0_iter9_ignore_call342; +wire ap_block_state11_pp0_stage0_iter10_ignore_call342; +wire ap_block_state12_pp0_stage0_iter11_ignore_call342; +wire ap_block_state13_pp0_stage0_iter12_ignore_call342; +wire ap_block_state14_pp0_stage0_iter13_ignore_call342; +wire ap_block_state15_pp0_stage0_iter14_ignore_call342; +wire ap_block_state16_pp0_stage0_iter15_ignore_call342; +wire ap_block_state17_pp0_stage0_iter16_ignore_call342; +wire ap_block_state18_pp0_stage0_iter17_ignore_call342; +wire ap_block_state19_pp0_stage0_iter18_ignore_call342; +wire ap_block_state20_pp0_stage0_iter19_ignore_call342; +wire ap_block_state21_pp0_stage0_iter20_ignore_call342; +wire ap_block_state22_pp0_stage0_iter21_ignore_call342; +wire ap_block_state23_pp0_stage0_iter22_ignore_call342; +wire ap_block_state24_pp0_stage0_iter23_ignore_call342; +wire ap_block_state25_pp0_stage0_iter24_ignore_call342; +wire ap_block_state26_pp0_stage0_iter25_ignore_call342; +wire ap_block_state27_pp0_stage0_iter26_ignore_call342; +wire ap_block_state28_pp0_stage0_iter27_ignore_call342; +wire ap_block_state29_pp0_stage0_iter28_ignore_call342; +wire ap_block_state30_pp0_stage0_iter29_ignore_call342; +wire ap_block_state31_pp0_stage0_iter30_ignore_call342; +wire ap_block_state32_pp0_stage0_iter31_ignore_call342; +wire ap_block_state33_pp0_stage0_iter32_ignore_call342; +wire ap_block_state34_pp0_stage0_iter33_ignore_call342; +wire ap_block_state35_pp0_stage0_iter34_ignore_call342; +wire ap_block_state36_pp0_stage0_iter35_ignore_call342; +wire ap_block_state37_pp0_stage0_iter36_ignore_call342; +wire ap_block_state38_pp0_stage0_iter37_ignore_call342; +wire ap_block_state39_pp0_stage0_iter38_ignore_call342; +wire ap_block_state40_pp0_stage0_iter39_ignore_call342; +wire ap_block_state41_pp0_stage0_iter40_ignore_call342; +wire ap_block_state42_pp0_stage0_iter41_ignore_call342; +wire ap_block_state43_pp0_stage0_iter42_ignore_call342; +wire ap_block_state44_pp0_stage0_iter43_ignore_call342; +wire ap_block_state45_pp0_stage0_iter44_ignore_call342; +wire ap_block_state46_pp0_stage0_iter45_ignore_call342; +wire ap_block_state47_pp0_stage0_iter46_ignore_call342; +wire ap_block_state48_pp0_stage0_iter47_ignore_call342; +wire ap_block_state49_pp0_stage0_iter48_ignore_call342; +wire ap_block_state50_pp0_stage0_iter49_ignore_call342; +wire ap_block_state51_pp0_stage0_iter50_ignore_call342; +wire ap_block_state52_pp0_stage0_iter51_ignore_call342; +wire ap_block_state53_pp0_stage0_iter52_ignore_call342; +wire ap_block_state54_pp0_stage0_iter53_ignore_call342; +wire ap_block_state55_pp0_stage0_iter54_ignore_call342; +wire ap_block_state56_pp0_stage0_iter55_ignore_call342; +wire ap_block_state57_pp0_stage0_iter56_ignore_call342; +wire ap_block_state58_pp0_stage0_iter57_ignore_call342; +wire ap_block_state59_pp0_stage0_iter58_ignore_call342; +wire ap_block_state60_pp0_stage0_iter59_ignore_call342; +wire ap_block_state61_pp0_stage0_iter60_ignore_call342; +wire ap_block_state62_pp0_stage0_iter61_ignore_call342; +wire ap_block_state63_pp0_stage0_iter62_ignore_call342; +wire ap_block_state64_pp0_stage0_iter63_ignore_call342; +wire ap_block_state65_pp0_stage0_iter64_ignore_call342; +wire ap_block_state66_pp0_stage0_iter65_ignore_call342; +wire ap_block_state67_pp0_stage0_iter66_ignore_call342; +wire ap_block_state68_pp0_stage0_iter67_ignore_call342; +reg ap_block_pp0_stage0_11001_ignoreCallOp440; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_0; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_1; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_2; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_3; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_4; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_5; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_6; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_7; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_8; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_9; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_10; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_11; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_12; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_13; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_14; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_15; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_16; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_17; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_18; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_19; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_20; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_21; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_22; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_23; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_24; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_25; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_26; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_27; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_28; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_29; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_30; +wire [15:0] grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_31; +reg grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_ce; +reg ap_block_state1_pp0_stage0_iter0_ignore_call243; +wire ap_block_state2_pp0_stage0_iter1_ignore_call243; +wire ap_block_state3_pp0_stage0_iter2_ignore_call243; +wire ap_block_state4_pp0_stage0_iter3_ignore_call243; +wire ap_block_state5_pp0_stage0_iter4_ignore_call243; +wire ap_block_state6_pp0_stage0_iter5_ignore_call243; +wire ap_block_state7_pp0_stage0_iter6_ignore_call243; +wire ap_block_state8_pp0_stage0_iter7_ignore_call243; +wire ap_block_state9_pp0_stage0_iter8_ignore_call243; +wire ap_block_state10_pp0_stage0_iter9_ignore_call243; +wire ap_block_state11_pp0_stage0_iter10_ignore_call243; +wire ap_block_state12_pp0_stage0_iter11_ignore_call243; +wire ap_block_state13_pp0_stage0_iter12_ignore_call243; +wire ap_block_state14_pp0_stage0_iter13_ignore_call243; +wire ap_block_state15_pp0_stage0_iter14_ignore_call243; +wire ap_block_state16_pp0_stage0_iter15_ignore_call243; +wire ap_block_state17_pp0_stage0_iter16_ignore_call243; +wire ap_block_state18_pp0_stage0_iter17_ignore_call243; +wire ap_block_state19_pp0_stage0_iter18_ignore_call243; +wire ap_block_state20_pp0_stage0_iter19_ignore_call243; +wire ap_block_state21_pp0_stage0_iter20_ignore_call243; +wire ap_block_state22_pp0_stage0_iter21_ignore_call243; +wire ap_block_state23_pp0_stage0_iter22_ignore_call243; +wire ap_block_state24_pp0_stage0_iter23_ignore_call243; +wire ap_block_state25_pp0_stage0_iter24_ignore_call243; +wire ap_block_state26_pp0_stage0_iter25_ignore_call243; +wire ap_block_state27_pp0_stage0_iter26_ignore_call243; +wire ap_block_state28_pp0_stage0_iter27_ignore_call243; +wire ap_block_state29_pp0_stage0_iter28_ignore_call243; +wire ap_block_state30_pp0_stage0_iter29_ignore_call243; +wire ap_block_state31_pp0_stage0_iter30_ignore_call243; +wire ap_block_state32_pp0_stage0_iter31_ignore_call243; +wire ap_block_state33_pp0_stage0_iter32_ignore_call243; +wire ap_block_state34_pp0_stage0_iter33_ignore_call243; +wire ap_block_state35_pp0_stage0_iter34_ignore_call243; +wire ap_block_state36_pp0_stage0_iter35_ignore_call243; +wire ap_block_state37_pp0_stage0_iter36_ignore_call243; +wire ap_block_state38_pp0_stage0_iter37_ignore_call243; +wire ap_block_state39_pp0_stage0_iter38_ignore_call243; +wire ap_block_state40_pp0_stage0_iter39_ignore_call243; +wire ap_block_state41_pp0_stage0_iter40_ignore_call243; +wire ap_block_state42_pp0_stage0_iter41_ignore_call243; +wire ap_block_state43_pp0_stage0_iter42_ignore_call243; +wire ap_block_state44_pp0_stage0_iter43_ignore_call243; +wire ap_block_state45_pp0_stage0_iter44_ignore_call243; +wire ap_block_state46_pp0_stage0_iter45_ignore_call243; +wire ap_block_state47_pp0_stage0_iter46_ignore_call243; +wire ap_block_state48_pp0_stage0_iter47_ignore_call243; +wire ap_block_state49_pp0_stage0_iter48_ignore_call243; +wire ap_block_state50_pp0_stage0_iter49_ignore_call243; +wire ap_block_state51_pp0_stage0_iter50_ignore_call243; +wire ap_block_state52_pp0_stage0_iter51_ignore_call243; +wire ap_block_state53_pp0_stage0_iter52_ignore_call243; +wire ap_block_state54_pp0_stage0_iter53_ignore_call243; +wire ap_block_state55_pp0_stage0_iter54_ignore_call243; +wire ap_block_state56_pp0_stage0_iter55_ignore_call243; +wire ap_block_state57_pp0_stage0_iter56_ignore_call243; +wire ap_block_state58_pp0_stage0_iter57_ignore_call243; +wire ap_block_state59_pp0_stage0_iter58_ignore_call243; +wire ap_block_state60_pp0_stage0_iter59_ignore_call243; +wire ap_block_state61_pp0_stage0_iter60_ignore_call243; +wire ap_block_state62_pp0_stage0_iter61_ignore_call243; +wire ap_block_state63_pp0_stage0_iter62_ignore_call243; +wire ap_block_state64_pp0_stage0_iter63_ignore_call243; +wire ap_block_state65_pp0_stage0_iter64_ignore_call243; +wire ap_block_state66_pp0_stage0_iter65_ignore_call243; +wire ap_block_state67_pp0_stage0_iter66_ignore_call243; +wire ap_block_state68_pp0_stage0_iter67_ignore_call243; +reg ap_block_pp0_stage0_11001_ignoreCallOp328; +wire [15:0] grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_return_0; +wire [15:0] grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_return_1; +wire [15:0] grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_return_2; +wire [15:0] grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_return_3; +wire [15:0] grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_return_4; +reg grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_ce; +reg ap_block_state1_pp0_stage0_iter0_ignore_call408; +wire ap_block_state2_pp0_stage0_iter1_ignore_call408; +wire ap_block_state3_pp0_stage0_iter2_ignore_call408; +wire ap_block_state4_pp0_stage0_iter3_ignore_call408; +wire ap_block_state5_pp0_stage0_iter4_ignore_call408; +wire ap_block_state6_pp0_stage0_iter5_ignore_call408; +wire ap_block_state7_pp0_stage0_iter6_ignore_call408; +wire ap_block_state8_pp0_stage0_iter7_ignore_call408; +wire ap_block_state9_pp0_stage0_iter8_ignore_call408; +wire ap_block_state10_pp0_stage0_iter9_ignore_call408; +wire ap_block_state11_pp0_stage0_iter10_ignore_call408; +wire ap_block_state12_pp0_stage0_iter11_ignore_call408; +wire ap_block_state13_pp0_stage0_iter12_ignore_call408; +wire ap_block_state14_pp0_stage0_iter13_ignore_call408; +wire ap_block_state15_pp0_stage0_iter14_ignore_call408; +wire ap_block_state16_pp0_stage0_iter15_ignore_call408; +wire ap_block_state17_pp0_stage0_iter16_ignore_call408; +wire ap_block_state18_pp0_stage0_iter17_ignore_call408; +wire ap_block_state19_pp0_stage0_iter18_ignore_call408; +wire ap_block_state20_pp0_stage0_iter19_ignore_call408; +wire ap_block_state21_pp0_stage0_iter20_ignore_call408; +wire ap_block_state22_pp0_stage0_iter21_ignore_call408; +wire ap_block_state23_pp0_stage0_iter22_ignore_call408; +wire ap_block_state24_pp0_stage0_iter23_ignore_call408; +wire ap_block_state25_pp0_stage0_iter24_ignore_call408; +wire ap_block_state26_pp0_stage0_iter25_ignore_call408; +wire ap_block_state27_pp0_stage0_iter26_ignore_call408; +wire ap_block_state28_pp0_stage0_iter27_ignore_call408; +wire ap_block_state29_pp0_stage0_iter28_ignore_call408; +wire ap_block_state30_pp0_stage0_iter29_ignore_call408; +wire ap_block_state31_pp0_stage0_iter30_ignore_call408; +wire ap_block_state32_pp0_stage0_iter31_ignore_call408; +wire ap_block_state33_pp0_stage0_iter32_ignore_call408; +wire ap_block_state34_pp0_stage0_iter33_ignore_call408; +wire ap_block_state35_pp0_stage0_iter34_ignore_call408; +wire ap_block_state36_pp0_stage0_iter35_ignore_call408; +wire ap_block_state37_pp0_stage0_iter36_ignore_call408; +wire ap_block_state38_pp0_stage0_iter37_ignore_call408; +wire ap_block_state39_pp0_stage0_iter38_ignore_call408; +wire ap_block_state40_pp0_stage0_iter39_ignore_call408; +wire ap_block_state41_pp0_stage0_iter40_ignore_call408; +wire ap_block_state42_pp0_stage0_iter41_ignore_call408; +wire ap_block_state43_pp0_stage0_iter42_ignore_call408; +wire ap_block_state44_pp0_stage0_iter43_ignore_call408; +wire ap_block_state45_pp0_stage0_iter44_ignore_call408; +wire ap_block_state46_pp0_stage0_iter45_ignore_call408; +wire ap_block_state47_pp0_stage0_iter46_ignore_call408; +wire ap_block_state48_pp0_stage0_iter47_ignore_call408; +wire ap_block_state49_pp0_stage0_iter48_ignore_call408; +wire ap_block_state50_pp0_stage0_iter49_ignore_call408; +wire ap_block_state51_pp0_stage0_iter50_ignore_call408; +wire ap_block_state52_pp0_stage0_iter51_ignore_call408; +wire ap_block_state53_pp0_stage0_iter52_ignore_call408; +wire ap_block_state54_pp0_stage0_iter53_ignore_call408; +wire ap_block_state55_pp0_stage0_iter54_ignore_call408; +wire ap_block_state56_pp0_stage0_iter55_ignore_call408; +wire ap_block_state57_pp0_stage0_iter56_ignore_call408; +wire ap_block_state58_pp0_stage0_iter57_ignore_call408; +wire ap_block_state59_pp0_stage0_iter58_ignore_call408; +wire ap_block_state60_pp0_stage0_iter59_ignore_call408; +wire ap_block_state61_pp0_stage0_iter60_ignore_call408; +wire ap_block_state62_pp0_stage0_iter61_ignore_call408; +wire ap_block_state63_pp0_stage0_iter62_ignore_call408; +wire ap_block_state64_pp0_stage0_iter63_ignore_call408; +wire ap_block_state65_pp0_stage0_iter64_ignore_call408; +wire ap_block_state66_pp0_stage0_iter65_ignore_call408; +wire ap_block_state67_pp0_stage0_iter66_ignore_call408; +wire ap_block_state68_pp0_stage0_iter67_ignore_call408; +reg ap_block_pp0_stage0_11001_ignoreCallOp509; +wire call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_ready; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_0; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_1; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_2; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_3; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_4; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_5; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_6; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_7; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_8; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_9; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_10; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_11; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_12; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_13; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_14; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_15; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_16; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_17; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_18; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_19; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_20; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_21; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_22; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_23; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_24; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_25; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_26; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_27; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_28; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_29; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_30; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_31; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_32; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_33; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_34; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_35; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_36; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_37; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_38; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_39; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_40; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_41; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_42; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_43; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_44; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_45; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_46; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_47; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_48; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_49; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_50; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_51; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_52; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_53; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_54; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_55; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_56; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_57; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_58; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_59; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_60; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_61; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_62; +wire [15:0] call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_63; +wire call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_ready; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_0; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_1; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_2; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_3; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_4; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_5; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_6; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_7; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_8; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_9; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_10; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_11; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_12; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_13; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_14; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_15; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_16; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_17; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_18; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_19; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_20; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_21; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_22; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_23; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_24; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_25; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_26; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_27; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_28; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_29; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_30; +wire [15:0] call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_31; +wire call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_ready; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_0; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_1; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_2; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_3; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_4; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_5; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_6; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_7; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_8; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_9; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_10; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_11; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_12; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_13; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_14; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_15; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_16; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_17; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_18; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_19; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_20; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_21; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_22; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_23; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_24; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_25; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_26; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_27; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_28; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_29; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_30; +wire [15:0] call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_31; +wire [15:0] grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_return_0; +wire [15:0] grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_return_1; +wire [15:0] grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_return_2; +wire [15:0] grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_return_3; +wire [15:0] grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_return_4; +reg grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_ce; +reg ap_block_state1_pp0_stage0_iter0_ignore_call414; +wire ap_block_state2_pp0_stage0_iter1_ignore_call414; +wire ap_block_state3_pp0_stage0_iter2_ignore_call414; +wire ap_block_state4_pp0_stage0_iter3_ignore_call414; +wire ap_block_state5_pp0_stage0_iter4_ignore_call414; +wire ap_block_state6_pp0_stage0_iter5_ignore_call414; +wire ap_block_state7_pp0_stage0_iter6_ignore_call414; +wire ap_block_state8_pp0_stage0_iter7_ignore_call414; +wire ap_block_state9_pp0_stage0_iter8_ignore_call414; +wire ap_block_state10_pp0_stage0_iter9_ignore_call414; +wire ap_block_state11_pp0_stage0_iter10_ignore_call414; +wire ap_block_state12_pp0_stage0_iter11_ignore_call414; +wire ap_block_state13_pp0_stage0_iter12_ignore_call414; +wire ap_block_state14_pp0_stage0_iter13_ignore_call414; +wire ap_block_state15_pp0_stage0_iter14_ignore_call414; +wire ap_block_state16_pp0_stage0_iter15_ignore_call414; +wire ap_block_state17_pp0_stage0_iter16_ignore_call414; +wire ap_block_state18_pp0_stage0_iter17_ignore_call414; +wire ap_block_state19_pp0_stage0_iter18_ignore_call414; +wire ap_block_state20_pp0_stage0_iter19_ignore_call414; +wire ap_block_state21_pp0_stage0_iter20_ignore_call414; +wire ap_block_state22_pp0_stage0_iter21_ignore_call414; +wire ap_block_state23_pp0_stage0_iter22_ignore_call414; +wire ap_block_state24_pp0_stage0_iter23_ignore_call414; +wire ap_block_state25_pp0_stage0_iter24_ignore_call414; +wire ap_block_state26_pp0_stage0_iter25_ignore_call414; +wire ap_block_state27_pp0_stage0_iter26_ignore_call414; +wire ap_block_state28_pp0_stage0_iter27_ignore_call414; +wire ap_block_state29_pp0_stage0_iter28_ignore_call414; +wire ap_block_state30_pp0_stage0_iter29_ignore_call414; +wire ap_block_state31_pp0_stage0_iter30_ignore_call414; +wire ap_block_state32_pp0_stage0_iter31_ignore_call414; +wire ap_block_state33_pp0_stage0_iter32_ignore_call414; +wire ap_block_state34_pp0_stage0_iter33_ignore_call414; +wire ap_block_state35_pp0_stage0_iter34_ignore_call414; +wire ap_block_state36_pp0_stage0_iter35_ignore_call414; +wire ap_block_state37_pp0_stage0_iter36_ignore_call414; +wire ap_block_state38_pp0_stage0_iter37_ignore_call414; +wire ap_block_state39_pp0_stage0_iter38_ignore_call414; +wire ap_block_state40_pp0_stage0_iter39_ignore_call414; +wire ap_block_state41_pp0_stage0_iter40_ignore_call414; +wire ap_block_state42_pp0_stage0_iter41_ignore_call414; +wire ap_block_state43_pp0_stage0_iter42_ignore_call414; +wire ap_block_state44_pp0_stage0_iter43_ignore_call414; +wire ap_block_state45_pp0_stage0_iter44_ignore_call414; +wire ap_block_state46_pp0_stage0_iter45_ignore_call414; +wire ap_block_state47_pp0_stage0_iter46_ignore_call414; +wire ap_block_state48_pp0_stage0_iter47_ignore_call414; +wire ap_block_state49_pp0_stage0_iter48_ignore_call414; +wire ap_block_state50_pp0_stage0_iter49_ignore_call414; +wire ap_block_state51_pp0_stage0_iter50_ignore_call414; +wire ap_block_state52_pp0_stage0_iter51_ignore_call414; +wire ap_block_state53_pp0_stage0_iter52_ignore_call414; +wire ap_block_state54_pp0_stage0_iter53_ignore_call414; +wire ap_block_state55_pp0_stage0_iter54_ignore_call414; +wire ap_block_state56_pp0_stage0_iter55_ignore_call414; +wire ap_block_state57_pp0_stage0_iter56_ignore_call414; +wire ap_block_state58_pp0_stage0_iter57_ignore_call414; +wire ap_block_state59_pp0_stage0_iter58_ignore_call414; +wire ap_block_state60_pp0_stage0_iter59_ignore_call414; +wire ap_block_state61_pp0_stage0_iter60_ignore_call414; +wire ap_block_state62_pp0_stage0_iter61_ignore_call414; +wire ap_block_state63_pp0_stage0_iter62_ignore_call414; +wire ap_block_state64_pp0_stage0_iter63_ignore_call414; +wire ap_block_state65_pp0_stage0_iter64_ignore_call414; +wire ap_block_state66_pp0_stage0_iter65_ignore_call414; +wire ap_block_state67_pp0_stage0_iter66_ignore_call414; +wire ap_block_state68_pp0_stage0_iter67_ignore_call414; +reg ap_block_pp0_stage0_11001_ignoreCallOp523; +reg ap_block_pp0_stage0_01001; +reg [0:0] ap_NS_fsm; +reg ap_idle_pp0_0to66; +reg ap_reset_idle_pp0; +wire ap_enable_pp0; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 1'd1; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +#0 ap_enable_reg_pp0_iter23 = 1'b0; +#0 ap_enable_reg_pp0_iter24 = 1'b0; +#0 ap_enable_reg_pp0_iter25 = 1'b0; +#0 ap_enable_reg_pp0_iter26 = 1'b0; +#0 ap_enable_reg_pp0_iter27 = 1'b0; +#0 ap_enable_reg_pp0_iter28 = 1'b0; +#0 ap_enable_reg_pp0_iter29 = 1'b0; +#0 ap_enable_reg_pp0_iter30 = 1'b0; +#0 ap_enable_reg_pp0_iter31 = 1'b0; +#0 ap_enable_reg_pp0_iter32 = 1'b0; +#0 ap_enable_reg_pp0_iter33 = 1'b0; +#0 ap_enable_reg_pp0_iter34 = 1'b0; +#0 ap_enable_reg_pp0_iter35 = 1'b0; +#0 ap_enable_reg_pp0_iter36 = 1'b0; +#0 ap_enable_reg_pp0_iter37 = 1'b0; +#0 ap_enable_reg_pp0_iter38 = 1'b0; +#0 ap_enable_reg_pp0_iter39 = 1'b0; +#0 ap_enable_reg_pp0_iter40 = 1'b0; +#0 ap_enable_reg_pp0_iter41 = 1'b0; +#0 ap_enable_reg_pp0_iter42 = 1'b0; +#0 ap_enable_reg_pp0_iter43 = 1'b0; +#0 ap_enable_reg_pp0_iter44 = 1'b0; +#0 ap_enable_reg_pp0_iter45 = 1'b0; +#0 ap_enable_reg_pp0_iter46 = 1'b0; +#0 ap_enable_reg_pp0_iter47 = 1'b0; +#0 ap_enable_reg_pp0_iter48 = 1'b0; +#0 ap_enable_reg_pp0_iter49 = 1'b0; +#0 ap_enable_reg_pp0_iter50 = 1'b0; +#0 ap_enable_reg_pp0_iter51 = 1'b0; +#0 ap_enable_reg_pp0_iter52 = 1'b0; +#0 ap_enable_reg_pp0_iter53 = 1'b0; +#0 ap_enable_reg_pp0_iter54 = 1'b0; +#0 ap_enable_reg_pp0_iter55 = 1'b0; +#0 ap_enable_reg_pp0_iter56 = 1'b0; +#0 ap_enable_reg_pp0_iter57 = 1'b0; +#0 ap_enable_reg_pp0_iter58 = 1'b0; +#0 ap_enable_reg_pp0_iter59 = 1'b0; +#0 ap_enable_reg_pp0_iter60 = 1'b0; +#0 ap_enable_reg_pp0_iter61 = 1'b0; +#0 ap_enable_reg_pp0_iter62 = 1'b0; +#0 ap_enable_reg_pp0_iter63 = 1'b0; +#0 ap_enable_reg_pp0_iter64 = 1'b0; +#0 ap_enable_reg_pp0_iter65 = 1'b0; +#0 ap_enable_reg_pp0_iter66 = 1'b0; +#0 ap_enable_reg_pp0_iter67 = 1'b0; +#0 input1_V_preg = 256'd0; +#0 input1_V_ap_vld_preg = 1'b0; +end + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .data_0_V_read(layer5_out_0_V_reg_2786), + .data_1_V_read(layer5_out_1_V_reg_2791), + .data_2_V_read(layer5_out_2_V_reg_2796), + .data_3_V_read(layer5_out_3_V_reg_2801), + .data_4_V_read(layer5_out_4_V_reg_2806), + .data_5_V_read(layer5_out_5_V_reg_2811), + .data_6_V_read(layer5_out_6_V_reg_2816), + .data_7_V_read(layer5_out_7_V_reg_2821), + .data_8_V_read(layer5_out_8_V_reg_2826), + .data_9_V_read(layer5_out_9_V_reg_2831), + .data_10_V_read(layer5_out_10_V_reg_2836), + .data_11_V_read(layer5_out_11_V_reg_2841), + .data_12_V_read(layer5_out_12_V_reg_2846), + .data_13_V_read(layer5_out_13_V_reg_2851), + .data_14_V_read(layer5_out_14_V_reg_2856), + .data_15_V_read(layer5_out_15_V_reg_2861), + .data_16_V_read(layer5_out_16_V_reg_2866), + .data_17_V_read(layer5_out_17_V_reg_2871), + .data_18_V_read(layer5_out_18_V_reg_2876), + .data_19_V_read(layer5_out_19_V_reg_2881), + .data_20_V_read(layer5_out_20_V_reg_2886), + .data_21_V_read(layer5_out_21_V_reg_2891), + .data_22_V_read(layer5_out_22_V_reg_2896), + .data_23_V_read(layer5_out_23_V_reg_2901), + .data_24_V_read(layer5_out_24_V_reg_2906), + .data_25_V_read(layer5_out_25_V_reg_2911), + .data_26_V_read(layer5_out_26_V_reg_2916), + .data_27_V_read(layer5_out_27_V_reg_2921), + .data_28_V_read(layer5_out_28_V_reg_2926), + .data_29_V_read(layer5_out_29_V_reg_2931), + .data_30_V_read(layer5_out_30_V_reg_2936), + .data_31_V_read(layer5_out_31_V_reg_2941), + .data_32_V_read(layer5_out_32_V_reg_2946), + .data_33_V_read(layer5_out_33_V_reg_2951), + .data_34_V_read(layer5_out_34_V_reg_2956), + .data_35_V_read(layer5_out_35_V_reg_2961), + .data_36_V_read(layer5_out_36_V_reg_2966), + .data_37_V_read(layer5_out_37_V_reg_2971), + .data_38_V_read(layer5_out_38_V_reg_2976), + .data_39_V_read(layer5_out_39_V_reg_2981), + .data_40_V_read(layer5_out_40_V_reg_2986), + .data_41_V_read(layer5_out_41_V_reg_2991), + .data_42_V_read(layer5_out_42_V_reg_2996), + .data_43_V_read(layer5_out_43_V_reg_3001), + .data_44_V_read(layer5_out_44_V_reg_3006), + .data_45_V_read(layer5_out_45_V_reg_3011), + .data_46_V_read(layer5_out_46_V_reg_3016), + .data_47_V_read(layer5_out_47_V_reg_3021), + .data_48_V_read(layer5_out_48_V_reg_3026), + .data_49_V_read(layer5_out_49_V_reg_3031), + .data_50_V_read(layer5_out_50_V_reg_3036), + .data_51_V_read(layer5_out_51_V_reg_3041), + .data_52_V_read(layer5_out_52_V_reg_3046), + .data_53_V_read(layer5_out_53_V_reg_3051), + .data_54_V_read(layer5_out_54_V_reg_3056), + .data_55_V_read(layer5_out_55_V_reg_3061), + .data_56_V_read(layer5_out_56_V_reg_3066), + .data_57_V_read(layer5_out_57_V_reg_3071), + .data_58_V_read(layer5_out_58_V_reg_3076), + .data_59_V_read(layer5_out_59_V_reg_3081), + .data_60_V_read(layer5_out_60_V_reg_3086), + .data_61_V_read(layer5_out_61_V_reg_3091), + .data_62_V_read(layer5_out_62_V_reg_3096), + .data_63_V_read(layer5_out_63_V_reg_3101), + .ap_return_0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_0), + .ap_return_1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_1), + .ap_return_2(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_2), + .ap_return_3(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_3), + .ap_return_4(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_4), + .ap_return_5(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_5), + .ap_return_6(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_6), + .ap_return_7(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_7), + .ap_return_8(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_8), + .ap_return_9(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_9), + .ap_return_10(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_10), + .ap_return_11(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_11), + .ap_return_12(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_12), + .ap_return_13(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_13), + .ap_return_14(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_14), + .ap_return_15(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_15), + .ap_return_16(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_16), + .ap_return_17(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_17), + .ap_return_18(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_18), + .ap_return_19(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_19), + .ap_return_20(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_20), + .ap_return_21(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_21), + .ap_return_22(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_22), + .ap_return_23(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_23), + .ap_return_24(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_24), + .ap_return_25(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_25), + .ap_return_26(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_26), + .ap_return_27(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_27), + .ap_return_28(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_28), + .ap_return_29(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_29), + .ap_return_30(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_30), + .ap_return_31(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_31), + .ap_ce(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_ce) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2 grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .data_0_V_read(layer9_out_0_V_reg_3426), + .data_1_V_read(layer9_out_1_V_reg_3431), + .data_2_V_read(layer9_out_2_V_reg_3436), + .data_3_V_read(layer9_out_3_V_reg_3441), + .data_4_V_read(layer9_out_4_V_reg_3446), + .data_5_V_read(layer9_out_5_V_reg_3451), + .data_6_V_read(layer9_out_6_V_reg_3456), + .data_7_V_read(layer9_out_7_V_reg_3461), + .data_8_V_read(layer9_out_8_V_reg_3466), + .data_9_V_read(layer9_out_9_V_reg_3471), + .data_10_V_read(layer9_out_10_V_reg_3476), + .data_11_V_read(layer9_out_11_V_reg_3481), + .data_12_V_read(layer9_out_12_V_reg_3486), + .data_13_V_read(layer9_out_13_V_reg_3491), + .data_14_V_read(layer9_out_14_V_reg_3496), + .data_15_V_read(layer9_out_15_V_reg_3501), + .data_16_V_read(layer9_out_16_V_reg_3506), + .data_17_V_read(layer9_out_17_V_reg_3511), + .data_18_V_read(layer9_out_18_V_reg_3516), + .data_19_V_read(layer9_out_19_V_reg_3521), + .data_20_V_read(layer9_out_20_V_reg_3526), + .data_21_V_read(layer9_out_21_V_reg_3531), + .data_22_V_read(layer9_out_22_V_reg_3536), + .data_23_V_read(layer9_out_23_V_reg_3541), + .data_24_V_read(layer9_out_24_V_reg_3546), + .data_25_V_read(layer9_out_25_V_reg_3551), + .data_26_V_read(layer9_out_26_V_reg_3556), + .data_27_V_read(layer9_out_27_V_reg_3561), + .data_28_V_read(layer9_out_28_V_reg_3566), + .data_29_V_read(layer9_out_29_V_reg_3571), + .data_30_V_read(layer9_out_30_V_reg_3576), + .data_31_V_read(layer9_out_31_V_reg_3581), + .ap_return_0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_0), + .ap_return_1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_1), + .ap_return_2(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_2), + .ap_return_3(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_3), + .ap_return_4(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_4), + .ap_return_5(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_5), + .ap_return_6(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_6), + .ap_return_7(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_7), + .ap_return_8(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_8), + .ap_return_9(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_9), + .ap_return_10(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_10), + .ap_return_11(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_11), + .ap_return_12(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_12), + .ap_return_13(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_13), + .ap_return_14(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_14), + .ap_return_15(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_15), + .ap_return_16(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_16), + .ap_return_17(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_17), + .ap_return_18(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_18), + .ap_return_19(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_19), + .ap_return_20(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_20), + .ap_return_21(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_21), + .ap_return_22(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_22), + .ap_return_23(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_23), + .ap_return_24(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_24), + .ap_return_25(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_25), + .ap_return_26(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_26), + .ap_return_27(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_27), + .ap_return_28(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_28), + .ap_return_29(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_29), + .ap_return_30(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_30), + .ap_return_31(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_31), + .ap_ce(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_ce) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1 grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .data_V_read(input1_V_in_sig), + .ap_return_0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_0), + .ap_return_1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_1), + .ap_return_2(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_2), + .ap_return_3(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_3), + .ap_return_4(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_4), + .ap_return_5(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_5), + .ap_return_6(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_6), + .ap_return_7(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_7), + .ap_return_8(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_8), + .ap_return_9(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_9), + .ap_return_10(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_10), + .ap_return_11(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_11), + .ap_return_12(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_12), + .ap_return_13(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_13), + .ap_return_14(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_14), + .ap_return_15(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_15), + .ap_return_16(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_16), + .ap_return_17(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_17), + .ap_return_18(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_18), + .ap_return_19(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_19), + .ap_return_20(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_20), + .ap_return_21(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_21), + .ap_return_22(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_22), + .ap_return_23(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_23), + .ap_return_24(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_24), + .ap_return_25(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_25), + .ap_return_26(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_26), + .ap_return_27(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_27), + .ap_return_28(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_28), + .ap_return_29(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_29), + .ap_return_30(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_30), + .ap_return_31(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_31), + .ap_return_32(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_32), + .ap_return_33(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_33), + .ap_return_34(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_34), + .ap_return_35(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_35), + .ap_return_36(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_36), + .ap_return_37(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_37), + .ap_return_38(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_38), + .ap_return_39(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_39), + .ap_return_40(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_40), + .ap_return_41(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_41), + .ap_return_42(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_42), + .ap_return_43(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_43), + .ap_return_44(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_44), + .ap_return_45(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_45), + .ap_return_46(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_46), + .ap_return_47(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_47), + .ap_return_48(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_48), + .ap_return_49(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_49), + .ap_return_50(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_50), + .ap_return_51(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_51), + .ap_return_52(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_52), + .ap_return_53(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_53), + .ap_return_54(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_54), + .ap_return_55(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_55), + .ap_return_56(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_56), + .ap_return_57(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_57), + .ap_return_58(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_58), + .ap_return_59(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_59), + .ap_return_60(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_60), + .ap_return_61(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_61), + .ap_return_62(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_62), + .ap_return_63(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_63), + .ap_ce(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_ce) +); + +normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1 grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .data_0_V_read(layer2_out_0_V_reg_2146), + .data_1_V_read(layer2_out_1_V_reg_2151), + .data_2_V_read(layer2_out_2_V_reg_2156), + .data_3_V_read(layer2_out_3_V_reg_2161), + .data_4_V_read(layer2_out_4_V_reg_2166), + .data_5_V_read(layer2_out_5_V_reg_2171), + .data_6_V_read(layer2_out_6_V_reg_2176), + .data_7_V_read(layer2_out_7_V_reg_2181), + .data_8_V_read(layer2_out_8_V_reg_2186), + .data_9_V_read(layer2_out_9_V_reg_2191), + .data_10_V_read(layer2_out_10_V_reg_2196), + .data_11_V_read(layer2_out_11_V_reg_2201), + .data_12_V_read(layer2_out_12_V_reg_2206), + .data_13_V_read(layer2_out_13_V_reg_2211), + .data_14_V_read(layer2_out_14_V_reg_2216), + .data_15_V_read(layer2_out_15_V_reg_2221), + .data_16_V_read(layer2_out_16_V_reg_2226), + .data_17_V_read(layer2_out_17_V_reg_2231), + .data_18_V_read(layer2_out_18_V_reg_2236), + .data_19_V_read(layer2_out_19_V_reg_2241), + .data_20_V_read(layer2_out_20_V_reg_2246), + .data_21_V_read(layer2_out_21_V_reg_2251), + .data_22_V_read(layer2_out_22_V_reg_2256), + .data_23_V_read(layer2_out_23_V_reg_2261), + .data_24_V_read(layer2_out_24_V_reg_2266), + .data_25_V_read(layer2_out_25_V_reg_2271), + .data_26_V_read(layer2_out_26_V_reg_2276), + .data_27_V_read(layer2_out_27_V_reg_2281), + .data_28_V_read(layer2_out_28_V_reg_2286), + .data_29_V_read(layer2_out_29_V_reg_2291), + .data_30_V_read(layer2_out_30_V_reg_2296), + .data_31_V_read(layer2_out_31_V_reg_2301), + .data_32_V_read(layer2_out_32_V_reg_2306), + .data_33_V_read(layer2_out_33_V_reg_2311), + .data_34_V_read(layer2_out_34_V_reg_2316), + .data_35_V_read(layer2_out_35_V_reg_2321), + .data_36_V_read(layer2_out_36_V_reg_2326), + .data_37_V_read(layer2_out_37_V_reg_2331), + .data_38_V_read(layer2_out_38_V_reg_2336), + .data_39_V_read(layer2_out_39_V_reg_2341), + .data_40_V_read(layer2_out_40_V_reg_2346), + .data_41_V_read(layer2_out_41_V_reg_2351), + .data_42_V_read(layer2_out_42_V_reg_2356), + .data_43_V_read(layer2_out_43_V_reg_2361), + .data_44_V_read(layer2_out_44_V_reg_2366), + .data_45_V_read(layer2_out_45_V_reg_2371), + .data_46_V_read(layer2_out_46_V_reg_2376), + .data_47_V_read(layer2_out_47_V_reg_2381), + .data_48_V_read(layer2_out_48_V_reg_2386), + .data_49_V_read(layer2_out_49_V_reg_2391), + .data_50_V_read(layer2_out_50_V_reg_2396), + .data_51_V_read(layer2_out_51_V_reg_2401), + .data_52_V_read(layer2_out_52_V_reg_2406), + .data_53_V_read(layer2_out_53_V_reg_2411), + .data_54_V_read(layer2_out_54_V_reg_2416), + .data_55_V_read(layer2_out_55_V_reg_2421), + .data_56_V_read(layer2_out_56_V_reg_2426), + .data_57_V_read(layer2_out_57_V_reg_2431), + .data_58_V_read(layer2_out_58_V_reg_2436), + .data_59_V_read(layer2_out_59_V_reg_2441), + .data_60_V_read(layer2_out_60_V_reg_2446), + .data_61_V_read(layer2_out_61_V_reg_2451), + .data_62_V_read(layer2_out_62_V_reg_2456), + .data_63_V_read(layer2_out_63_V_reg_2461), + .ap_return_0(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_0), + .ap_return_1(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_1), + .ap_return_2(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_2), + .ap_return_3(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_3), + .ap_return_4(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_4), + .ap_return_5(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_5), + .ap_return_6(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_6), + .ap_return_7(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_7), + .ap_return_8(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_8), + .ap_return_9(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_9), + .ap_return_10(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_10), + .ap_return_11(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_11), + .ap_return_12(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_12), + .ap_return_13(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_13), + .ap_return_14(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_14), + .ap_return_15(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_15), + .ap_return_16(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_16), + .ap_return_17(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_17), + .ap_return_18(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_18), + .ap_return_19(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_19), + .ap_return_20(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_20), + .ap_return_21(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_21), + .ap_return_22(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_22), + .ap_return_23(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_23), + .ap_return_24(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_24), + .ap_return_25(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_25), + .ap_return_26(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_26), + .ap_return_27(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_27), + .ap_return_28(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_28), + .ap_return_29(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_29), + .ap_return_30(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_30), + .ap_return_31(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_31), + .ap_return_32(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_32), + .ap_return_33(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_33), + .ap_return_34(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_34), + .ap_return_35(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_35), + .ap_return_36(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_36), + .ap_return_37(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_37), + .ap_return_38(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_38), + .ap_return_39(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_39), + .ap_return_40(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_40), + .ap_return_41(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_41), + .ap_return_42(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_42), + .ap_return_43(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_43), + .ap_return_44(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_44), + .ap_return_45(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_45), + .ap_return_46(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_46), + .ap_return_47(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_47), + .ap_return_48(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_48), + .ap_return_49(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_49), + .ap_return_50(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_50), + .ap_return_51(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_51), + .ap_return_52(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_52), + .ap_return_53(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_53), + .ap_return_54(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_54), + .ap_return_55(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_55), + .ap_return_56(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_56), + .ap_return_57(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_57), + .ap_return_58(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_58), + .ap_return_59(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_59), + .ap_return_60(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_60), + .ap_return_61(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_61), + .ap_return_62(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_62), + .ap_return_63(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_63), + .ap_ce(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_ce) +); + +normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2 grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .data_0_V_read(layer10_out_0_V_reg_3586), + .data_1_V_read(layer10_out_1_V_reg_3591), + .data_2_V_read(layer10_out_2_V_reg_3596), + .data_3_V_read(layer10_out_3_V_reg_3601), + .data_4_V_read(layer10_out_4_V_reg_3606), + .data_5_V_read(layer10_out_5_V_reg_3611), + .data_6_V_read(layer10_out_6_V_reg_3616), + .data_7_V_read(layer10_out_7_V_reg_3621), + .data_8_V_read(layer10_out_8_V_reg_3626), + .data_9_V_read(layer10_out_9_V_reg_3631), + .data_10_V_read(layer10_out_10_V_reg_3636), + .data_11_V_read(layer10_out_11_V_reg_3641), + .data_12_V_read(layer10_out_12_V_reg_3646), + .data_13_V_read(layer10_out_13_V_reg_3651), + .data_14_V_read(layer10_out_14_V_reg_3656), + .data_15_V_read(layer10_out_15_V_reg_3661), + .data_16_V_read(layer10_out_16_V_reg_3666), + .data_17_V_read(layer10_out_17_V_reg_3671), + .data_18_V_read(layer10_out_18_V_reg_3676), + .data_19_V_read(layer10_out_19_V_reg_3681), + .data_20_V_read(layer10_out_20_V_reg_3686), + .data_21_V_read(layer10_out_21_V_reg_3691), + .data_22_V_read(layer10_out_22_V_reg_3696), + .data_23_V_read(layer10_out_23_V_reg_3701), + .data_24_V_read(layer10_out_24_V_reg_3706), + .data_25_V_read(layer10_out_25_V_reg_3711), + .data_26_V_read(layer10_out_26_V_reg_3716), + .data_27_V_read(layer10_out_27_V_reg_3721), + .data_28_V_read(layer10_out_28_V_reg_3726), + .data_29_V_read(layer10_out_29_V_reg_3731), + .data_30_V_read(layer10_out_30_V_reg_3736), + .data_31_V_read(layer10_out_31_V_reg_3741), + .ap_return_0(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_0), + .ap_return_1(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_1), + .ap_return_2(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_2), + .ap_return_3(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_3), + .ap_return_4(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_4), + .ap_return_5(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_5), + .ap_return_6(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_6), + .ap_return_7(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_7), + .ap_return_8(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_8), + .ap_return_9(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_9), + .ap_return_10(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_10), + .ap_return_11(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_11), + .ap_return_12(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_12), + .ap_return_13(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_13), + .ap_return_14(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_14), + .ap_return_15(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_15), + .ap_return_16(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_16), + .ap_return_17(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_17), + .ap_return_18(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_18), + .ap_return_19(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_19), + .ap_return_20(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_20), + .ap_return_21(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_21), + .ap_return_22(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_22), + .ap_return_23(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_23), + .ap_return_24(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_24), + .ap_return_25(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_25), + .ap_return_26(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_26), + .ap_return_27(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_27), + .ap_return_28(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_28), + .ap_return_29(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_29), + .ap_return_30(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_30), + .ap_return_31(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_31), + .ap_ce(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_ce) +); + +normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .data_0_V_read(layer6_out_0_V_reg_3106), + .data_1_V_read(layer6_out_1_V_reg_3111), + .data_2_V_read(layer6_out_2_V_reg_3116), + .data_3_V_read(layer6_out_3_V_reg_3121), + .data_4_V_read(layer6_out_4_V_reg_3126), + .data_5_V_read(layer6_out_5_V_reg_3131), + .data_6_V_read(layer6_out_6_V_reg_3136), + .data_7_V_read(layer6_out_7_V_reg_3141), + .data_8_V_read(layer6_out_8_V_reg_3146), + .data_9_V_read(layer6_out_9_V_reg_3151), + .data_10_V_read(layer6_out_10_V_reg_3156), + .data_11_V_read(layer6_out_11_V_reg_3161), + .data_12_V_read(layer6_out_12_V_reg_3166), + .data_13_V_read(layer6_out_13_V_reg_3171), + .data_14_V_read(layer6_out_14_V_reg_3176), + .data_15_V_read(layer6_out_15_V_reg_3181), + .data_16_V_read(layer6_out_16_V_reg_3186), + .data_17_V_read(layer6_out_17_V_reg_3191), + .data_18_V_read(layer6_out_18_V_reg_3196), + .data_19_V_read(layer6_out_19_V_reg_3201), + .data_20_V_read(layer6_out_20_V_reg_3206), + .data_21_V_read(layer6_out_21_V_reg_3211), + .data_22_V_read(layer6_out_22_V_reg_3216), + .data_23_V_read(layer6_out_23_V_reg_3221), + .data_24_V_read(layer6_out_24_V_reg_3226), + .data_25_V_read(layer6_out_25_V_reg_3231), + .data_26_V_read(layer6_out_26_V_reg_3236), + .data_27_V_read(layer6_out_27_V_reg_3241), + .data_28_V_read(layer6_out_28_V_reg_3246), + .data_29_V_read(layer6_out_29_V_reg_3251), + .data_30_V_read(layer6_out_30_V_reg_3256), + .data_31_V_read(layer6_out_31_V_reg_3261), + .ap_return_0(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_0), + .ap_return_1(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_1), + .ap_return_2(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_2), + .ap_return_3(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_3), + .ap_return_4(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_4), + .ap_return_5(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_5), + .ap_return_6(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_6), + .ap_return_7(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_7), + .ap_return_8(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_8), + .ap_return_9(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_9), + .ap_return_10(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_10), + .ap_return_11(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_11), + .ap_return_12(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_12), + .ap_return_13(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_13), + .ap_return_14(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_14), + .ap_return_15(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_15), + .ap_return_16(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_16), + .ap_return_17(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_17), + .ap_return_18(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_18), + .ap_return_19(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_19), + .ap_return_20(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_20), + .ap_return_21(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_21), + .ap_return_22(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_22), + .ap_return_23(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_23), + .ap_return_24(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_24), + .ap_return_25(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_25), + .ap_return_26(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_26), + .ap_return_27(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_27), + .ap_return_28(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_28), + .ap_return_29(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_29), + .ap_return_30(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_30), + .ap_return_31(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_31), + .ap_ce(grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_ce) +); + +dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0 grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .data_0_V_read(layer13_out_0_V_reg_3906), + .data_1_V_read(layer13_out_1_V_reg_3911), + .data_2_V_read(layer13_out_2_V_reg_3916), + .data_3_V_read(layer13_out_3_V_reg_3921), + .data_4_V_read(layer13_out_4_V_reg_3926), + .data_5_V_read(layer13_out_5_V_reg_3931), + .data_6_V_read(layer13_out_6_V_reg_3936), + .data_7_V_read(layer13_out_7_V_reg_3941), + .data_8_V_read(layer13_out_8_V_reg_3946), + .data_9_V_read(layer13_out_9_V_reg_3951), + .data_10_V_read(layer13_out_10_V_reg_3956), + .data_11_V_read(layer13_out_11_V_reg_3961), + .data_12_V_read(layer13_out_12_V_reg_3966), + .data_13_V_read(layer13_out_13_V_reg_3971), + .data_14_V_read(layer13_out_14_V_reg_3976), + .data_15_V_read(layer13_out_15_V_reg_3981), + .data_16_V_read(layer13_out_16_V_reg_3986), + .data_17_V_read(layer13_out_17_V_reg_3991), + .data_18_V_read(layer13_out_18_V_reg_3996), + .data_19_V_read(layer13_out_19_V_reg_4001), + .data_20_V_read(layer13_out_20_V_reg_4006), + .data_21_V_read(layer13_out_21_V_reg_4011), + .data_22_V_read(layer13_out_22_V_reg_4016), + .data_23_V_read(layer13_out_23_V_reg_4021), + .data_24_V_read(layer13_out_24_V_reg_4026), + .data_25_V_read(layer13_out_25_V_reg_4031), + .data_26_V_read(layer13_out_26_V_reg_4036), + .data_27_V_read(layer13_out_27_V_reg_4041), + .data_28_V_read(layer13_out_28_V_reg_4046), + .data_29_V_read(layer13_out_29_V_reg_4051), + .data_30_V_read(layer13_out_30_V_reg_4056), + .data_31_V_read(layer13_out_31_V_reg_4061), + .ap_return_0(grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_return_0), + .ap_return_1(grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_return_1), + .ap_return_2(grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_return_2), + .ap_return_3(grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_return_3), + .ap_return_4(grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_return_4), + .ap_ce(grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_ce) +); + +relu_max_ap_fixed_ap_fixed_1_relu1_config5_s call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411( + .ap_ready(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_ready), + .data_0_V_read(layer4_out_0_V_reg_2466), + .data_1_V_read(layer4_out_1_V_reg_2471), + .data_2_V_read(layer4_out_2_V_reg_2476), + .data_3_V_read(layer4_out_3_V_reg_2481), + .data_4_V_read(layer4_out_4_V_reg_2486), + .data_5_V_read(layer4_out_5_V_reg_2491), + .data_6_V_read(layer4_out_6_V_reg_2496), + .data_7_V_read(layer4_out_7_V_reg_2501), + .data_8_V_read(layer4_out_8_V_reg_2506), + .data_9_V_read(layer4_out_9_V_reg_2511), + .data_10_V_read(layer4_out_10_V_reg_2516), + .data_11_V_read(layer4_out_11_V_reg_2521), + .data_12_V_read(layer4_out_12_V_reg_2526), + .data_13_V_read(layer4_out_13_V_reg_2531), + .data_14_V_read(layer4_out_14_V_reg_2536), + .data_15_V_read(layer4_out_15_V_reg_2541), + .data_16_V_read(layer4_out_16_V_reg_2546), + .data_17_V_read(layer4_out_17_V_reg_2551), + .data_18_V_read(layer4_out_18_V_reg_2556), + .data_19_V_read(layer4_out_19_V_reg_2561), + .data_20_V_read(layer4_out_20_V_reg_2566), + .data_21_V_read(layer4_out_21_V_reg_2571), + .data_22_V_read(layer4_out_22_V_reg_2576), + .data_23_V_read(layer4_out_23_V_reg_2581), + .data_24_V_read(layer4_out_24_V_reg_2586), + .data_25_V_read(layer4_out_25_V_reg_2591), + .data_26_V_read(layer4_out_26_V_reg_2596), + .data_27_V_read(layer4_out_27_V_reg_2601), + .data_28_V_read(layer4_out_28_V_reg_2606), + .data_29_V_read(layer4_out_29_V_reg_2611), + .data_30_V_read(layer4_out_30_V_reg_2616), + .data_31_V_read(layer4_out_31_V_reg_2621), + .data_32_V_read(layer4_out_32_V_reg_2626), + .data_33_V_read(layer4_out_33_V_reg_2631), + .data_34_V_read(layer4_out_34_V_reg_2636), + .data_35_V_read(layer4_out_35_V_reg_2641), + .data_36_V_read(layer4_out_36_V_reg_2646), + .data_37_V_read(layer4_out_37_V_reg_2651), + .data_38_V_read(layer4_out_38_V_reg_2656), + .data_39_V_read(layer4_out_39_V_reg_2661), + .data_40_V_read(layer4_out_40_V_reg_2666), + .data_41_V_read(layer4_out_41_V_reg_2671), + .data_42_V_read(layer4_out_42_V_reg_2676), + .data_43_V_read(layer4_out_43_V_reg_2681), + .data_44_V_read(layer4_out_44_V_reg_2686), + .data_45_V_read(layer4_out_45_V_reg_2691), + .data_46_V_read(layer4_out_46_V_reg_2696), + .data_47_V_read(layer4_out_47_V_reg_2701), + .data_48_V_read(layer4_out_48_V_reg_2706), + .data_49_V_read(layer4_out_49_V_reg_2711), + .data_50_V_read(layer4_out_50_V_reg_2716), + .data_51_V_read(layer4_out_51_V_reg_2721), + .data_52_V_read(layer4_out_52_V_reg_2726), + .data_53_V_read(layer4_out_53_V_reg_2731), + .data_54_V_read(layer4_out_54_V_reg_2736), + .data_55_V_read(layer4_out_55_V_reg_2741), + .data_56_V_read(layer4_out_56_V_reg_2746), + .data_57_V_read(layer4_out_57_V_reg_2751), + .data_58_V_read(layer4_out_58_V_reg_2756), + .data_59_V_read(layer4_out_59_V_reg_2761), + .data_60_V_read(layer4_out_60_V_reg_2766), + .data_61_V_read(layer4_out_61_V_reg_2771), + .data_62_V_read(layer4_out_62_V_reg_2776), + .data_63_V_read(layer4_out_63_V_reg_2781), + .ap_return_0(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_0), + .ap_return_1(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_1), + .ap_return_2(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_2), + .ap_return_3(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_3), + .ap_return_4(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_4), + .ap_return_5(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_5), + .ap_return_6(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_6), + .ap_return_7(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_7), + .ap_return_8(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_8), + .ap_return_9(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_9), + .ap_return_10(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_10), + .ap_return_11(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_11), + .ap_return_12(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_12), + .ap_return_13(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_13), + .ap_return_14(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_14), + .ap_return_15(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_15), + .ap_return_16(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_16), + .ap_return_17(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_17), + .ap_return_18(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_18), + .ap_return_19(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_19), + .ap_return_20(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_20), + .ap_return_21(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_21), + .ap_return_22(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_22), + .ap_return_23(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_23), + .ap_return_24(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_24), + .ap_return_25(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_25), + .ap_return_26(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_26), + .ap_return_27(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_27), + .ap_return_28(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_28), + .ap_return_29(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_29), + .ap_return_30(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_30), + .ap_return_31(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_31), + .ap_return_32(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_32), + .ap_return_33(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_33), + .ap_return_34(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_34), + .ap_return_35(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_35), + .ap_return_36(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_36), + .ap_return_37(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_37), + .ap_return_38(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_38), + .ap_return_39(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_39), + .ap_return_40(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_40), + .ap_return_41(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_41), + .ap_return_42(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_42), + .ap_return_43(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_43), + .ap_return_44(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_44), + .ap_return_45(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_45), + .ap_return_46(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_46), + .ap_return_47(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_47), + .ap_return_48(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_48), + .ap_return_49(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_49), + .ap_return_50(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_50), + .ap_return_51(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_51), + .ap_return_52(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_52), + .ap_return_53(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_53), + .ap_return_54(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_54), + .ap_return_55(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_55), + .ap_return_56(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_56), + .ap_return_57(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_57), + .ap_return_58(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_58), + .ap_return_59(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_59), + .ap_return_60(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_60), + .ap_return_61(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_61), + .ap_return_62(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_62), + .ap_return_63(call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_63) +); + +relu_max_ap_fixed_ap_fixed_1_relu1_config9_s call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479( + .ap_ready(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_ready), + .data_0_V_read(layer8_out_0_V_reg_3266), + .data_1_V_read(layer8_out_1_V_reg_3271), + .data_2_V_read(layer8_out_2_V_reg_3276), + .data_3_V_read(layer8_out_3_V_reg_3281), + .data_4_V_read(layer8_out_4_V_reg_3286), + .data_5_V_read(layer8_out_5_V_reg_3291), + .data_6_V_read(layer8_out_6_V_reg_3296), + .data_7_V_read(layer8_out_7_V_reg_3301), + .data_8_V_read(layer8_out_8_V_reg_3306), + .data_9_V_read(layer8_out_9_V_reg_3311), + .data_10_V_read(layer8_out_10_V_reg_3316), + .data_11_V_read(layer8_out_11_V_reg_3321), + .data_12_V_read(layer8_out_12_V_reg_3326), + .data_13_V_read(layer8_out_13_V_reg_3331), + .data_14_V_read(layer8_out_14_V_reg_3336), + .data_15_V_read(layer8_out_15_V_reg_3341), + .data_16_V_read(layer8_out_16_V_reg_3346), + .data_17_V_read(layer8_out_17_V_reg_3351), + .data_18_V_read(layer8_out_18_V_reg_3356), + .data_19_V_read(layer8_out_19_V_reg_3361), + .data_20_V_read(layer8_out_20_V_reg_3366), + .data_21_V_read(layer8_out_21_V_reg_3371), + .data_22_V_read(layer8_out_22_V_reg_3376), + .data_23_V_read(layer8_out_23_V_reg_3381), + .data_24_V_read(layer8_out_24_V_reg_3386), + .data_25_V_read(layer8_out_25_V_reg_3391), + .data_26_V_read(layer8_out_26_V_reg_3396), + .data_27_V_read(layer8_out_27_V_reg_3401), + .data_28_V_read(layer8_out_28_V_reg_3406), + .data_29_V_read(layer8_out_29_V_reg_3411), + .data_30_V_read(layer8_out_30_V_reg_3416), + .data_31_V_read(layer8_out_31_V_reg_3421), + .ap_return_0(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_0), + .ap_return_1(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_1), + .ap_return_2(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_2), + .ap_return_3(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_3), + .ap_return_4(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_4), + .ap_return_5(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_5), + .ap_return_6(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_6), + .ap_return_7(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_7), + .ap_return_8(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_8), + .ap_return_9(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_9), + .ap_return_10(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_10), + .ap_return_11(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_11), + .ap_return_12(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_12), + .ap_return_13(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_13), + .ap_return_14(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_14), + .ap_return_15(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_15), + .ap_return_16(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_16), + .ap_return_17(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_17), + .ap_return_18(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_18), + .ap_return_19(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_19), + .ap_return_20(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_20), + .ap_return_21(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_21), + .ap_return_22(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_22), + .ap_return_23(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_23), + .ap_return_24(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_24), + .ap_return_25(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_25), + .ap_return_26(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_26), + .ap_return_27(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_27), + .ap_return_28(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_28), + .ap_return_29(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_29), + .ap_return_30(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_30), + .ap_return_31(call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_31) +); + +relu_max_ap_fixed_ap_fixed_1_relu1_config13_s call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515( + .ap_ready(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_ready), + .data_0_V_read(layer12_out_0_V_reg_3746), + .data_1_V_read(layer12_out_1_V_reg_3751), + .data_2_V_read(layer12_out_2_V_reg_3756), + .data_3_V_read(layer12_out_3_V_reg_3761), + .data_4_V_read(layer12_out_4_V_reg_3766), + .data_5_V_read(layer12_out_5_V_reg_3771), + .data_6_V_read(layer12_out_6_V_reg_3776), + .data_7_V_read(layer12_out_7_V_reg_3781), + .data_8_V_read(layer12_out_8_V_reg_3786), + .data_9_V_read(layer12_out_9_V_reg_3791), + .data_10_V_read(layer12_out_10_V_reg_3796), + .data_11_V_read(layer12_out_11_V_reg_3801), + .data_12_V_read(layer12_out_12_V_reg_3806), + .data_13_V_read(layer12_out_13_V_reg_3811), + .data_14_V_read(layer12_out_14_V_reg_3816), + .data_15_V_read(layer12_out_15_V_reg_3821), + .data_16_V_read(layer12_out_16_V_reg_3826), + .data_17_V_read(layer12_out_17_V_reg_3831), + .data_18_V_read(layer12_out_18_V_reg_3836), + .data_19_V_read(layer12_out_19_V_reg_3841), + .data_20_V_read(layer12_out_20_V_reg_3846), + .data_21_V_read(layer12_out_21_V_reg_3851), + .data_22_V_read(layer12_out_22_V_reg_3856), + .data_23_V_read(layer12_out_23_V_reg_3861), + .data_24_V_read(layer12_out_24_V_reg_3866), + .data_25_V_read(layer12_out_25_V_reg_3871), + .data_26_V_read(layer12_out_26_V_reg_3876), + .data_27_V_read(layer12_out_27_V_reg_3881), + .data_28_V_read(layer12_out_28_V_reg_3886), + .data_29_V_read(layer12_out_29_V_reg_3891), + .data_30_V_read(layer12_out_30_V_reg_3896), + .data_31_V_read(layer12_out_31_V_reg_3901), + .ap_return_0(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_0), + .ap_return_1(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_1), + .ap_return_2(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_2), + .ap_return_3(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_3), + .ap_return_4(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_4), + .ap_return_5(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_5), + .ap_return_6(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_6), + .ap_return_7(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_7), + .ap_return_8(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_8), + .ap_return_9(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_9), + .ap_return_10(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_10), + .ap_return_11(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_11), + .ap_return_12(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_12), + .ap_return_13(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_13), + .ap_return_14(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_14), + .ap_return_15(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_15), + .ap_return_16(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_16), + .ap_return_17(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_17), + .ap_return_18(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_18), + .ap_return_19(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_19), + .ap_return_20(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_20), + .ap_return_21(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_21), + .ap_return_22(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_22), + .ap_return_23(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_23), + .ap_return_24(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_24), + .ap_return_25(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_25), + .ap_return_26(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_26), + .ap_return_27(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_27), + .ap_return_28(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_28), + .ap_return_29(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_29), + .ap_return_30(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_30), + .ap_return_31(call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_31) +); + +normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0 grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .data_0_V_read(layer14_out_0_V_reg_4066), + .data_1_V_read(layer14_out_1_V_reg_4071), + .data_2_V_read(layer14_out_2_V_reg_4076), + .data_3_V_read(layer14_out_3_V_reg_4081), + .data_4_V_read(layer14_out_4_V_reg_4086), + .ap_return_0(grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_return_0), + .ap_return_1(grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_return_1), + .ap_return_2(grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_return_2), + .ap_return_3(grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_return_3), + .ap_return_4(grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_return_4), + .ap_ce(grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_ce) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_pp0_stage0; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_enable_reg_pp0_iter1 <= ap_start; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter23 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter23 <= ap_enable_reg_pp0_iter22; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter24 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter24 <= ap_enable_reg_pp0_iter23; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter25 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter25 <= ap_enable_reg_pp0_iter24; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter26 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter26 <= ap_enable_reg_pp0_iter25; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter27 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter27 <= ap_enable_reg_pp0_iter26; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter28 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter28 <= ap_enable_reg_pp0_iter27; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter29 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter29 <= ap_enable_reg_pp0_iter28; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter30 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter30 <= ap_enable_reg_pp0_iter29; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter31 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter31 <= ap_enable_reg_pp0_iter30; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter32 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter32 <= ap_enable_reg_pp0_iter31; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter33 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter33 <= ap_enable_reg_pp0_iter32; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter34 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter34 <= ap_enable_reg_pp0_iter33; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter35 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter35 <= ap_enable_reg_pp0_iter34; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter36 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter36 <= ap_enable_reg_pp0_iter35; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter37 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter37 <= ap_enable_reg_pp0_iter36; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter38 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter38 <= ap_enable_reg_pp0_iter37; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter39 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter39 <= ap_enable_reg_pp0_iter38; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter40 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter40 <= ap_enable_reg_pp0_iter39; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter41 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter41 <= ap_enable_reg_pp0_iter40; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter42 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter42 <= ap_enable_reg_pp0_iter41; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter43 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter43 <= ap_enable_reg_pp0_iter42; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter44 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter44 <= ap_enable_reg_pp0_iter43; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter45 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter45 <= ap_enable_reg_pp0_iter44; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter46 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter46 <= ap_enable_reg_pp0_iter45; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter47 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter47 <= ap_enable_reg_pp0_iter46; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter48 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter48 <= ap_enable_reg_pp0_iter47; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter49 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter49 <= ap_enable_reg_pp0_iter48; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter50 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter50 <= ap_enable_reg_pp0_iter49; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter51 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter51 <= ap_enable_reg_pp0_iter50; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter52 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter52 <= ap_enable_reg_pp0_iter51; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter53 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter53 <= ap_enable_reg_pp0_iter52; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter54 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter54 <= ap_enable_reg_pp0_iter53; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter55 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter55 <= ap_enable_reg_pp0_iter54; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter56 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter56 <= ap_enable_reg_pp0_iter55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter57 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter57 <= ap_enable_reg_pp0_iter56; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter58 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter58 <= ap_enable_reg_pp0_iter57; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter59 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter59 <= ap_enable_reg_pp0_iter58; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter60 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter60 <= ap_enable_reg_pp0_iter59; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter61 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter61 <= ap_enable_reg_pp0_iter60; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter62 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter62 <= ap_enable_reg_pp0_iter61; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter63 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter63 <= ap_enable_reg_pp0_iter62; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter64 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter64 <= ap_enable_reg_pp0_iter63; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter65 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter65 <= ap_enable_reg_pp0_iter64; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter66 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter66 <= ap_enable_reg_pp0_iter65; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter67 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter67 <= ap_enable_reg_pp0_iter66; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + input1_V_ap_vld_preg <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_start == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + input1_V_ap_vld_preg <= 1'b0; + end else if ((~((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0)) & (input1_V_ap_vld == 1'b1))) begin + input1_V_ap_vld_preg <= input1_V_ap_vld; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + input1_V_preg <= 256'd0; + end else begin + if ((~((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0)) & (input1_V_ap_vld == 1'b1))) begin + input1_V_preg <= input1_V; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + layer10_out_0_V_reg_3586 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_0; + layer10_out_10_V_reg_3636 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_10; + layer10_out_11_V_reg_3641 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_11; + layer10_out_12_V_reg_3646 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_12; + layer10_out_13_V_reg_3651 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_13; + layer10_out_14_V_reg_3656 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_14; + layer10_out_15_V_reg_3661 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_15; + layer10_out_16_V_reg_3666 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_16; + layer10_out_17_V_reg_3671 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_17; + layer10_out_18_V_reg_3676 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_18; + layer10_out_19_V_reg_3681 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_19; + layer10_out_1_V_reg_3591 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_1; + layer10_out_20_V_reg_3686 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_20; + layer10_out_21_V_reg_3691 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_21; + layer10_out_22_V_reg_3696 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_22; + layer10_out_23_V_reg_3701 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_23; + layer10_out_24_V_reg_3706 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_24; + layer10_out_25_V_reg_3711 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_25; + layer10_out_26_V_reg_3716 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_26; + layer10_out_27_V_reg_3721 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_27; + layer10_out_28_V_reg_3726 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_28; + layer10_out_29_V_reg_3731 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_29; + layer10_out_2_V_reg_3596 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_2; + layer10_out_30_V_reg_3736 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_30; + layer10_out_31_V_reg_3741 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_31; + layer10_out_3_V_reg_3601 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_3; + layer10_out_4_V_reg_3606 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_4; + layer10_out_5_V_reg_3611 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_5; + layer10_out_6_V_reg_3616 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_6; + layer10_out_7_V_reg_3621 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_7; + layer10_out_8_V_reg_3626 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_8; + layer10_out_9_V_reg_3631 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_return_9; + layer12_out_0_V_reg_3746 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_0; + layer12_out_10_V_reg_3796 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_10; + layer12_out_11_V_reg_3801 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_11; + layer12_out_12_V_reg_3806 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_12; + layer12_out_13_V_reg_3811 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_13; + layer12_out_14_V_reg_3816 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_14; + layer12_out_15_V_reg_3821 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_15; + layer12_out_16_V_reg_3826 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_16; + layer12_out_17_V_reg_3831 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_17; + layer12_out_18_V_reg_3836 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_18; + layer12_out_19_V_reg_3841 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_19; + layer12_out_1_V_reg_3751 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_1; + layer12_out_20_V_reg_3846 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_20; + layer12_out_21_V_reg_3851 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_21; + layer12_out_22_V_reg_3856 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_22; + layer12_out_23_V_reg_3861 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_23; + layer12_out_24_V_reg_3866 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_24; + layer12_out_25_V_reg_3871 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_25; + layer12_out_26_V_reg_3876 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_26; + layer12_out_27_V_reg_3881 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_27; + layer12_out_28_V_reg_3886 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_28; + layer12_out_29_V_reg_3891 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_29; + layer12_out_2_V_reg_3756 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_2; + layer12_out_30_V_reg_3896 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_30; + layer12_out_31_V_reg_3901 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_31; + layer12_out_3_V_reg_3761 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_3; + layer12_out_4_V_reg_3766 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_4; + layer12_out_5_V_reg_3771 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_5; + layer12_out_6_V_reg_3776 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_6; + layer12_out_7_V_reg_3781 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_7; + layer12_out_8_V_reg_3786 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_8; + layer12_out_9_V_reg_3791 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_return_9; + layer13_out_0_V_reg_3906 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_0; + layer13_out_10_V_reg_3956 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_10; + layer13_out_11_V_reg_3961 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_11; + layer13_out_12_V_reg_3966 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_12; + layer13_out_13_V_reg_3971 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_13; + layer13_out_14_V_reg_3976 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_14; + layer13_out_15_V_reg_3981 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_15; + layer13_out_16_V_reg_3986 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_16; + layer13_out_17_V_reg_3991 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_17; + layer13_out_18_V_reg_3996 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_18; + layer13_out_19_V_reg_4001 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_19; + layer13_out_1_V_reg_3911 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_1; + layer13_out_20_V_reg_4006 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_20; + layer13_out_21_V_reg_4011 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_21; + layer13_out_22_V_reg_4016 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_22; + layer13_out_23_V_reg_4021 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_23; + layer13_out_24_V_reg_4026 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_24; + layer13_out_25_V_reg_4031 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_25; + layer13_out_26_V_reg_4036 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_26; + layer13_out_27_V_reg_4041 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_27; + layer13_out_28_V_reg_4046 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_28; + layer13_out_29_V_reg_4051 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_29; + layer13_out_2_V_reg_3916 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_2; + layer13_out_30_V_reg_4056 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_30; + layer13_out_31_V_reg_4061 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_31; + layer13_out_3_V_reg_3921 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_3; + layer13_out_4_V_reg_3926 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_4; + layer13_out_5_V_reg_3931 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_5; + layer13_out_6_V_reg_3936 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_6; + layer13_out_7_V_reg_3941 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_7; + layer13_out_8_V_reg_3946 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_8; + layer13_out_9_V_reg_3951 <= call_ret_i2_relu_max_ap_fixed_ap_fixed_1_relu1_config13_s_fu_515_ap_return_9; + layer14_out_0_V_reg_4066 <= grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_return_0; + layer14_out_1_V_reg_4071 <= grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_return_1; + layer14_out_2_V_reg_4076 <= grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_return_2; + layer14_out_3_V_reg_4081 <= grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_return_3; + layer14_out_4_V_reg_4086 <= grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_return_4; + layer2_out_0_V_reg_2146 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_0; + layer2_out_10_V_reg_2196 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_10; + layer2_out_11_V_reg_2201 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_11; + layer2_out_12_V_reg_2206 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_12; + layer2_out_13_V_reg_2211 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_13; + layer2_out_14_V_reg_2216 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_14; + layer2_out_15_V_reg_2221 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_15; + layer2_out_16_V_reg_2226 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_16; + layer2_out_17_V_reg_2231 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_17; + layer2_out_18_V_reg_2236 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_18; + layer2_out_19_V_reg_2241 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_19; + layer2_out_1_V_reg_2151 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_1; + layer2_out_20_V_reg_2246 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_20; + layer2_out_21_V_reg_2251 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_21; + layer2_out_22_V_reg_2256 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_22; + layer2_out_23_V_reg_2261 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_23; + layer2_out_24_V_reg_2266 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_24; + layer2_out_25_V_reg_2271 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_25; + layer2_out_26_V_reg_2276 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_26; + layer2_out_27_V_reg_2281 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_27; + layer2_out_28_V_reg_2286 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_28; + layer2_out_29_V_reg_2291 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_29; + layer2_out_2_V_reg_2156 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_2; + layer2_out_30_V_reg_2296 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_30; + layer2_out_31_V_reg_2301 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_31; + layer2_out_32_V_reg_2306 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_32; + layer2_out_33_V_reg_2311 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_33; + layer2_out_34_V_reg_2316 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_34; + layer2_out_35_V_reg_2321 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_35; + layer2_out_36_V_reg_2326 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_36; + layer2_out_37_V_reg_2331 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_37; + layer2_out_38_V_reg_2336 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_38; + layer2_out_39_V_reg_2341 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_39; + layer2_out_3_V_reg_2161 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_3; + layer2_out_40_V_reg_2346 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_40; + layer2_out_41_V_reg_2351 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_41; + layer2_out_42_V_reg_2356 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_42; + layer2_out_43_V_reg_2361 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_43; + layer2_out_44_V_reg_2366 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_44; + layer2_out_45_V_reg_2371 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_45; + layer2_out_46_V_reg_2376 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_46; + layer2_out_47_V_reg_2381 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_47; + layer2_out_48_V_reg_2386 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_48; + layer2_out_49_V_reg_2391 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_49; + layer2_out_4_V_reg_2166 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_4; + layer2_out_50_V_reg_2396 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_50; + layer2_out_51_V_reg_2401 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_51; + layer2_out_52_V_reg_2406 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_52; + layer2_out_53_V_reg_2411 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_53; + layer2_out_54_V_reg_2416 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_54; + layer2_out_55_V_reg_2421 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_55; + layer2_out_56_V_reg_2426 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_56; + layer2_out_57_V_reg_2431 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_57; + layer2_out_58_V_reg_2436 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_58; + layer2_out_59_V_reg_2441 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_59; + layer2_out_5_V_reg_2171 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_5; + layer2_out_60_V_reg_2446 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_60; + layer2_out_61_V_reg_2451 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_61; + layer2_out_62_V_reg_2456 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_62; + layer2_out_63_V_reg_2461 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_63; + layer2_out_6_V_reg_2176 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_6; + layer2_out_7_V_reg_2181 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_7; + layer2_out_8_V_reg_2186 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_8; + layer2_out_9_V_reg_2191 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_return_9; + layer4_out_0_V_reg_2466 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_0; + layer4_out_10_V_reg_2516 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_10; + layer4_out_11_V_reg_2521 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_11; + layer4_out_12_V_reg_2526 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_12; + layer4_out_13_V_reg_2531 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_13; + layer4_out_14_V_reg_2536 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_14; + layer4_out_15_V_reg_2541 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_15; + layer4_out_16_V_reg_2546 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_16; + layer4_out_17_V_reg_2551 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_17; + layer4_out_18_V_reg_2556 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_18; + layer4_out_19_V_reg_2561 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_19; + layer4_out_1_V_reg_2471 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_1; + layer4_out_20_V_reg_2566 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_20; + layer4_out_21_V_reg_2571 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_21; + layer4_out_22_V_reg_2576 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_22; + layer4_out_23_V_reg_2581 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_23; + layer4_out_24_V_reg_2586 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_24; + layer4_out_25_V_reg_2591 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_25; + layer4_out_26_V_reg_2596 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_26; + layer4_out_27_V_reg_2601 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_27; + layer4_out_28_V_reg_2606 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_28; + layer4_out_29_V_reg_2611 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_29; + layer4_out_2_V_reg_2476 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_2; + layer4_out_30_V_reg_2616 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_30; + layer4_out_31_V_reg_2621 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_31; + layer4_out_32_V_reg_2626 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_32; + layer4_out_33_V_reg_2631 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_33; + layer4_out_34_V_reg_2636 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_34; + layer4_out_35_V_reg_2641 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_35; + layer4_out_36_V_reg_2646 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_36; + layer4_out_37_V_reg_2651 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_37; + layer4_out_38_V_reg_2656 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_38; + layer4_out_39_V_reg_2661 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_39; + layer4_out_3_V_reg_2481 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_3; + layer4_out_40_V_reg_2666 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_40; + layer4_out_41_V_reg_2671 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_41; + layer4_out_42_V_reg_2676 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_42; + layer4_out_43_V_reg_2681 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_43; + layer4_out_44_V_reg_2686 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_44; + layer4_out_45_V_reg_2691 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_45; + layer4_out_46_V_reg_2696 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_46; + layer4_out_47_V_reg_2701 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_47; + layer4_out_48_V_reg_2706 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_48; + layer4_out_49_V_reg_2711 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_49; + layer4_out_4_V_reg_2486 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_4; + layer4_out_50_V_reg_2716 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_50; + layer4_out_51_V_reg_2721 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_51; + layer4_out_52_V_reg_2726 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_52; + layer4_out_53_V_reg_2731 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_53; + layer4_out_54_V_reg_2736 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_54; + layer4_out_55_V_reg_2741 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_55; + layer4_out_56_V_reg_2746 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_56; + layer4_out_57_V_reg_2751 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_57; + layer4_out_58_V_reg_2756 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_58; + layer4_out_59_V_reg_2761 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_59; + layer4_out_5_V_reg_2491 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_5; + layer4_out_60_V_reg_2766 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_60; + layer4_out_61_V_reg_2771 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_61; + layer4_out_62_V_reg_2776 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_62; + layer4_out_63_V_reg_2781 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_63; + layer4_out_6_V_reg_2496 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_6; + layer4_out_7_V_reg_2501 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_7; + layer4_out_8_V_reg_2506 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_8; + layer4_out_9_V_reg_2511 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_return_9; + layer5_out_0_V_reg_2786 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_0; + layer5_out_10_V_reg_2836 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_10; + layer5_out_11_V_reg_2841 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_11; + layer5_out_12_V_reg_2846 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_12; + layer5_out_13_V_reg_2851 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_13; + layer5_out_14_V_reg_2856 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_14; + layer5_out_15_V_reg_2861 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_15; + layer5_out_16_V_reg_2866 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_16; + layer5_out_17_V_reg_2871 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_17; + layer5_out_18_V_reg_2876 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_18; + layer5_out_19_V_reg_2881 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_19; + layer5_out_1_V_reg_2791 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_1; + layer5_out_20_V_reg_2886 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_20; + layer5_out_21_V_reg_2891 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_21; + layer5_out_22_V_reg_2896 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_22; + layer5_out_23_V_reg_2901 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_23; + layer5_out_24_V_reg_2906 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_24; + layer5_out_25_V_reg_2911 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_25; + layer5_out_26_V_reg_2916 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_26; + layer5_out_27_V_reg_2921 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_27; + layer5_out_28_V_reg_2926 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_28; + layer5_out_29_V_reg_2931 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_29; + layer5_out_2_V_reg_2796 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_2; + layer5_out_30_V_reg_2936 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_30; + layer5_out_31_V_reg_2941 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_31; + layer5_out_32_V_reg_2946 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_32; + layer5_out_33_V_reg_2951 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_33; + layer5_out_34_V_reg_2956 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_34; + layer5_out_35_V_reg_2961 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_35; + layer5_out_36_V_reg_2966 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_36; + layer5_out_37_V_reg_2971 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_37; + layer5_out_38_V_reg_2976 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_38; + layer5_out_39_V_reg_2981 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_39; + layer5_out_3_V_reg_2801 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_3; + layer5_out_40_V_reg_2986 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_40; + layer5_out_41_V_reg_2991 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_41; + layer5_out_42_V_reg_2996 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_42; + layer5_out_43_V_reg_3001 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_43; + layer5_out_44_V_reg_3006 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_44; + layer5_out_45_V_reg_3011 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_45; + layer5_out_46_V_reg_3016 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_46; + layer5_out_47_V_reg_3021 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_47; + layer5_out_48_V_reg_3026 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_48; + layer5_out_49_V_reg_3031 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_49; + layer5_out_4_V_reg_2806 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_4; + layer5_out_50_V_reg_3036 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_50; + layer5_out_51_V_reg_3041 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_51; + layer5_out_52_V_reg_3046 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_52; + layer5_out_53_V_reg_3051 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_53; + layer5_out_54_V_reg_3056 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_54; + layer5_out_55_V_reg_3061 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_55; + layer5_out_56_V_reg_3066 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_56; + layer5_out_57_V_reg_3071 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_57; + layer5_out_58_V_reg_3076 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_58; + layer5_out_59_V_reg_3081 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_59; + layer5_out_5_V_reg_2811 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_5; + layer5_out_60_V_reg_3086 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_60; + layer5_out_61_V_reg_3091 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_61; + layer5_out_62_V_reg_3096 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_62; + layer5_out_63_V_reg_3101 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_63; + layer5_out_6_V_reg_2816 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_6; + layer5_out_7_V_reg_2821 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_7; + layer5_out_8_V_reg_2826 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_8; + layer5_out_9_V_reg_2831 <= call_ret_i_relu_max_ap_fixed_ap_fixed_1_relu1_config5_s_fu_411_ap_return_9; + layer6_out_0_V_reg_3106 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_0; + layer6_out_10_V_reg_3156 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_10; + layer6_out_11_V_reg_3161 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_11; + layer6_out_12_V_reg_3166 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_12; + layer6_out_13_V_reg_3171 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_13; + layer6_out_14_V_reg_3176 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_14; + layer6_out_15_V_reg_3181 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_15; + layer6_out_16_V_reg_3186 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_16; + layer6_out_17_V_reg_3191 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_17; + layer6_out_18_V_reg_3196 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_18; + layer6_out_19_V_reg_3201 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_19; + layer6_out_1_V_reg_3111 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_1; + layer6_out_20_V_reg_3206 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_20; + layer6_out_21_V_reg_3211 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_21; + layer6_out_22_V_reg_3216 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_22; + layer6_out_23_V_reg_3221 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_23; + layer6_out_24_V_reg_3226 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_24; + layer6_out_25_V_reg_3231 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_25; + layer6_out_26_V_reg_3236 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_26; + layer6_out_27_V_reg_3241 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_27; + layer6_out_28_V_reg_3246 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_28; + layer6_out_29_V_reg_3251 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_29; + layer6_out_2_V_reg_3116 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_2; + layer6_out_30_V_reg_3256 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_30; + layer6_out_31_V_reg_3261 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_31; + layer6_out_3_V_reg_3121 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_3; + layer6_out_4_V_reg_3126 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_4; + layer6_out_5_V_reg_3131 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_5; + layer6_out_6_V_reg_3136 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_6; + layer6_out_7_V_reg_3141 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_7; + layer6_out_8_V_reg_3146 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_8; + layer6_out_9_V_reg_3151 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_return_9; + layer8_out_0_V_reg_3266 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_0; + layer8_out_10_V_reg_3316 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_10; + layer8_out_11_V_reg_3321 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_11; + layer8_out_12_V_reg_3326 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_12; + layer8_out_13_V_reg_3331 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_13; + layer8_out_14_V_reg_3336 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_14; + layer8_out_15_V_reg_3341 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_15; + layer8_out_16_V_reg_3346 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_16; + layer8_out_17_V_reg_3351 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_17; + layer8_out_18_V_reg_3356 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_18; + layer8_out_19_V_reg_3361 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_19; + layer8_out_1_V_reg_3271 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_1; + layer8_out_20_V_reg_3366 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_20; + layer8_out_21_V_reg_3371 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_21; + layer8_out_22_V_reg_3376 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_22; + layer8_out_23_V_reg_3381 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_23; + layer8_out_24_V_reg_3386 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_24; + layer8_out_25_V_reg_3391 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_25; + layer8_out_26_V_reg_3396 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_26; + layer8_out_27_V_reg_3401 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_27; + layer8_out_28_V_reg_3406 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_28; + layer8_out_29_V_reg_3411 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_29; + layer8_out_2_V_reg_3276 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_2; + layer8_out_30_V_reg_3416 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_30; + layer8_out_31_V_reg_3421 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_31; + layer8_out_3_V_reg_3281 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_3; + layer8_out_4_V_reg_3286 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_4; + layer8_out_5_V_reg_3291 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_5; + layer8_out_6_V_reg_3296 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_6; + layer8_out_7_V_reg_3301 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_7; + layer8_out_8_V_reg_3306 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_8; + layer8_out_9_V_reg_3311 <= grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_return_9; + layer9_out_0_V_reg_3426 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_0; + layer9_out_10_V_reg_3476 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_10; + layer9_out_11_V_reg_3481 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_11; + layer9_out_12_V_reg_3486 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_12; + layer9_out_13_V_reg_3491 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_13; + layer9_out_14_V_reg_3496 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_14; + layer9_out_15_V_reg_3501 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_15; + layer9_out_16_V_reg_3506 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_16; + layer9_out_17_V_reg_3511 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_17; + layer9_out_18_V_reg_3516 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_18; + layer9_out_19_V_reg_3521 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_19; + layer9_out_1_V_reg_3431 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_1; + layer9_out_20_V_reg_3526 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_20; + layer9_out_21_V_reg_3531 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_21; + layer9_out_22_V_reg_3536 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_22; + layer9_out_23_V_reg_3541 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_23; + layer9_out_24_V_reg_3546 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_24; + layer9_out_25_V_reg_3551 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_25; + layer9_out_26_V_reg_3556 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_26; + layer9_out_27_V_reg_3561 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_27; + layer9_out_28_V_reg_3566 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_28; + layer9_out_29_V_reg_3571 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_29; + layer9_out_2_V_reg_3436 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_2; + layer9_out_30_V_reg_3576 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_30; + layer9_out_31_V_reg_3581 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_31; + layer9_out_3_V_reg_3441 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_3; + layer9_out_4_V_reg_3446 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_4; + layer9_out_5_V_reg_3451 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_5; + layer9_out_6_V_reg_3456 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_6; + layer9_out_7_V_reg_3461 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_7; + layer9_out_8_V_reg_3466 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_8; + layer9_out_9_V_reg_3471 <= call_ret_i1_relu_max_ap_fixed_ap_fixed_1_relu1_config9_s_fu_479_ap_return_9; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter67 == 1'b1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (ap_idle_pp0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter26 == 1'b0) & (ap_enable_reg_pp0_iter25 == 1'b0) & (ap_enable_reg_pp0_iter24 == 1'b0) & (ap_enable_reg_pp0_iter23 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter67 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter66 == 1'b0) & (ap_enable_reg_pp0_iter65 == 1'b0) & (ap_enable_reg_pp0_iter64 == 1'b0) & (ap_enable_reg_pp0_iter63 == 1'b0) & (ap_enable_reg_pp0_iter62 == 1'b0) & (ap_enable_reg_pp0_iter61 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter60 == 1'b0) & (ap_enable_reg_pp0_iter59 == 1'b0) & (ap_enable_reg_pp0_iter58 == 1'b0) & (ap_enable_reg_pp0_iter57 == 1'b0) & (ap_enable_reg_pp0_iter56 == 1'b0) & (ap_enable_reg_pp0_iter55 == 1'b0) & (ap_enable_reg_pp0_iter54 == 1'b0) & (ap_enable_reg_pp0_iter53 == 1'b0) & (ap_enable_reg_pp0_iter52 == 1'b0) & (ap_enable_reg_pp0_iter51 == 1'b0) & (ap_enable_reg_pp0_iter50 == 1'b0) & (ap_enable_reg_pp0_iter49 == 1'b0) & (ap_enable_reg_pp0_iter48 == 1'b0) & (ap_enable_reg_pp0_iter47 == 1'b0) & (ap_enable_reg_pp0_iter46 == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b0) & (ap_enable_reg_pp0_iter44 == 1'b0) & (ap_enable_reg_pp0_iter43 == 1'b0) & (ap_enable_reg_pp0_iter42 == 1'b0) & (ap_enable_reg_pp0_iter41 == 1'b0) & (ap_enable_reg_pp0_iter40 == 1'b0) & (ap_enable_reg_pp0_iter39 == 1'b0) & (ap_enable_reg_pp0_iter38 == 1'b0) & (ap_enable_reg_pp0_iter37 == 1'b0) & (ap_enable_reg_pp0_iter36 == 1'b0) & (ap_enable_reg_pp0_iter35 == 1'b0) & (ap_enable_reg_pp0_iter34 == 1'b0) & (ap_enable_reg_pp0_iter33 == 1'b0) & (ap_enable_reg_pp0_iter32 == 1'b0) & (ap_enable_reg_pp0_iter31 == 1'b0) & (ap_enable_reg_pp0_iter30 == 1'b0) & (ap_enable_reg_pp0_iter29 == 1'b0) & (ap_enable_reg_pp0_iter28 == 1'b0) & (ap_enable_reg_pp0_iter27 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter26 == 1'b0) & (ap_enable_reg_pp0_iter25 == 1'b0) & (ap_enable_reg_pp0_iter24 == 1'b0) & (ap_enable_reg_pp0_iter23 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter66 == 1'b0) & (ap_enable_reg_pp0_iter65 == 1'b0) & (ap_enable_reg_pp0_iter64 == 1'b0) & (ap_enable_reg_pp0_iter63 == 1'b0) & (ap_enable_reg_pp0_iter62 == 1'b0) & (ap_enable_reg_pp0_iter61 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter60 == 1'b0) & (ap_enable_reg_pp0_iter59 == 1'b0) & (ap_enable_reg_pp0_iter58 == 1'b0) & (ap_enable_reg_pp0_iter57 == 1'b0) & (ap_enable_reg_pp0_iter56 == 1'b0) & (ap_enable_reg_pp0_iter55 == 1'b0) & (ap_enable_reg_pp0_iter54 == 1'b0) & (ap_enable_reg_pp0_iter53 == 1'b0) & (ap_enable_reg_pp0_iter52 == 1'b0) & (ap_enable_reg_pp0_iter51 == 1'b0) & (ap_enable_reg_pp0_iter50 == 1'b0) & (ap_enable_reg_pp0_iter49 == 1'b0) & (ap_enable_reg_pp0_iter48 == 1'b0) & (ap_enable_reg_pp0_iter47 == 1'b0) & (ap_enable_reg_pp0_iter46 == 1'b0) & (ap_enable_reg_pp0_iter45 == 1'b0) & (ap_enable_reg_pp0_iter44 == 1'b0) & (ap_enable_reg_pp0_iter43 == 1'b0) & (ap_enable_reg_pp0_iter42 == 1'b0) & (ap_enable_reg_pp0_iter41 == 1'b0) & (ap_enable_reg_pp0_iter40 == 1'b0) & (ap_enable_reg_pp0_iter39 == 1'b0) & (ap_enable_reg_pp0_iter38 == 1'b0) & (ap_enable_reg_pp0_iter37 == 1'b0) & (ap_enable_reg_pp0_iter36 == 1'b0) & (ap_enable_reg_pp0_iter35 == 1'b0) & (ap_enable_reg_pp0_iter34 == 1'b0) & (ap_enable_reg_pp0_iter33 == 1'b0) & (ap_enable_reg_pp0_iter32 == 1'b0) & (ap_enable_reg_pp0_iter31 == 1'b0) & (ap_enable_reg_pp0_iter30 == 1'b0) & (ap_enable_reg_pp0_iter29 == 1'b0) & (ap_enable_reg_pp0_iter28 == 1'b0) & (ap_enable_reg_pp0_iter27 == 1'b0))) begin + ap_idle_pp0_0to66 = 1'b1; + end else begin + ap_idle_pp0_0to66 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_start == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (ap_idle_pp0_0to66 == 1'b1))) begin + ap_reset_idle_pp0 = 1'b1; + end else begin + ap_reset_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter67 == 1'b1))) begin + const_size_in_1_ap_vld = 1'b1; + end else begin + const_size_in_1_ap_vld = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter67 == 1'b1))) begin + const_size_out_1_ap_vld = 1'b1; + end else begin + const_size_out_1_ap_vld = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp70) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_ce = 1'b1; + end else begin + grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_229_ap_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp397) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_ce = 1'b1; + end else begin + grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_193_ap_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp277) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_ce = 1'b1; + end else begin + grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_125_ap_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp509) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_ce = 1'b1; + end else begin + grp_dense_latency_ap_fixed_ap_fixed_config14_0_0_0_0_0_0_fu_375_ap_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp144) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_ce = 1'b1; + end else begin + grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_235_ap_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp440) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_ce = 1'b1; + end else begin + grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2_fu_303_ap_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp328) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_ce = 1'b1; + end else begin + grp_normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_339_ap_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001_ignoreCallOp523) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_ce = 1'b1; + end else begin + grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_ce = 1'b0; + end +end + +always @ (*) begin + if ((input1_V_ap_vld == 1'b1)) begin + input1_V_ap_vld_in_sig = input1_V_ap_vld; + end else begin + input1_V_ap_vld_in_sig = input1_V_ap_vld_preg; + end +end + +always @ (*) begin + if (((ap_start == 1'b1) & (1'b0 == ap_block_pp0_stage0) & (ap_start == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + input1_V_blk_n = input1_V_ap_vld; + end else begin + input1_V_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((input1_V_ap_vld == 1'b1)) begin + input1_V_in_sig = input1_V; + end else begin + input1_V_in_sig = input1_V_preg; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter67 == 1'b1))) begin + layer16_out_0_V_ap_vld = 1'b1; + end else begin + layer16_out_0_V_ap_vld = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter67 == 1'b1))) begin + layer16_out_1_V_ap_vld = 1'b1; + end else begin + layer16_out_1_V_ap_vld = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter67 == 1'b1))) begin + layer16_out_2_V_ap_vld = 1'b1; + end else begin + layer16_out_2_V_ap_vld = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter67 == 1'b1))) begin + layer16_out_3_V_ap_vld = 1'b1; + end else begin + layer16_out_3_V_ap_vld = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter67 == 1'b1))) begin + layer16_out_4_V_ap_vld = 1'b1; + end else begin + layer16_out_4_V_ap_vld = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_pp0_stage0 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + default : begin + ap_NS_fsm = 1'b0; + end + endcase +end + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_pp0_stage0_01001 = ((ap_start == 1'b1) & ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0))); +end + +always @ (*) begin + ap_block_pp0_stage0_11001 = ((ap_start == 1'b1) & ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0))); +end + +always @ (*) begin + ap_block_pp0_stage0_11001_ignoreCallOp144 = ((ap_start == 1'b1) & ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0))); +end + +always @ (*) begin + ap_block_pp0_stage0_11001_ignoreCallOp277 = ((ap_start == 1'b1) & ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0))); +end + +always @ (*) begin + ap_block_pp0_stage0_11001_ignoreCallOp328 = ((ap_start == 1'b1) & ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0))); +end + +always @ (*) begin + ap_block_pp0_stage0_11001_ignoreCallOp397 = ((ap_start == 1'b1) & ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0))); +end + +always @ (*) begin + ap_block_pp0_stage0_11001_ignoreCallOp440 = ((ap_start == 1'b1) & ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0))); +end + +always @ (*) begin + ap_block_pp0_stage0_11001_ignoreCallOp509 = ((ap_start == 1'b1) & ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0))); +end + +always @ (*) begin + ap_block_pp0_stage0_11001_ignoreCallOp523 = ((ap_start == 1'b1) & ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0))); +end + +always @ (*) begin + ap_block_pp0_stage0_11001_ignoreCallOp70 = ((ap_start == 1'b1) & ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0))); +end + +always @ (*) begin + ap_block_pp0_stage0_subdone = ((ap_start == 1'b1) & ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0))); +end + +assign ap_block_state10_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state10_pp0_stage0_iter9_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state10_pp0_stage0_iter9_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state10_pp0_stage0_iter9_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state10_pp0_stage0_iter9_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state10_pp0_stage0_iter9_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state10_pp0_stage0_iter9_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state10_pp0_stage0_iter9_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state10_pp0_stage0_iter9_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter10_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter10_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter10_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter10_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter10_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter10_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter10_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter10_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter11_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter11_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter11_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter11_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter11_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter11_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter11_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter11_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter12_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter12_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter12_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter12_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter12_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter12_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter12_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter12_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter13_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter13_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter13_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter13_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter13_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter13_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter13_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter13_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter14_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter14_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter14_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter14_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter14_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter14_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter14_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter14_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter15_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter15_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter15_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter15_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter15_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter15_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter15_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter15_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter16_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter16_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter16_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter16_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter16_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter16_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter16_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter16_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter17_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter17_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter17_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter17_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter17_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter17_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter17_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter17_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter18_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter18_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter18_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter18_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter18_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter18_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter18_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter18_ignore_call80 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1_pp0_stage0_iter0 = ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0)); +end + +always @ (*) begin + ap_block_state1_pp0_stage0_iter0_ignore_call15 = ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0)); +end + +always @ (*) begin + ap_block_state1_pp0_stage0_iter0_ignore_call210 = ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0)); +end + +always @ (*) begin + ap_block_state1_pp0_stage0_iter0_ignore_call243 = ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0)); +end + +always @ (*) begin + ap_block_state1_pp0_stage0_iter0_ignore_call309 = ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0)); +end + +always @ (*) begin + ap_block_state1_pp0_stage0_iter0_ignore_call342 = ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0)); +end + +always @ (*) begin + ap_block_state1_pp0_stage0_iter0_ignore_call408 = ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0)); +end + +always @ (*) begin + ap_block_state1_pp0_stage0_iter0_ignore_call414 = ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0)); +end + +always @ (*) begin + ap_block_state1_pp0_stage0_iter0_ignore_call80 = ((ap_start == 1'b0) | (input1_V_ap_vld_in_sig == 1'b0)); +end + +assign ap_block_state20_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter19_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter19_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter19_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter19_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter19_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter19_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter19_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter19_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter20_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter20_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter20_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter20_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter20_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter20_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter20_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter20_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter21_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter21_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter21_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter21_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter21_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter21_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter21_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter21_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter22_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter22_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter22_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter22_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter22_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter22_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter22_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter22_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter23 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter23_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter23_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter23_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter23_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter23_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter23_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter23_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter23_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state25_pp0_stage0_iter24 = ~(1'b1 == 1'b1); + +assign ap_block_state25_pp0_stage0_iter24_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state25_pp0_stage0_iter24_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state25_pp0_stage0_iter24_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state25_pp0_stage0_iter24_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state25_pp0_stage0_iter24_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state25_pp0_stage0_iter24_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state25_pp0_stage0_iter24_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state25_pp0_stage0_iter24_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state26_pp0_stage0_iter25 = ~(1'b1 == 1'b1); + +assign ap_block_state26_pp0_stage0_iter25_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state26_pp0_stage0_iter25_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state26_pp0_stage0_iter25_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state26_pp0_stage0_iter25_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state26_pp0_stage0_iter25_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state26_pp0_stage0_iter25_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state26_pp0_stage0_iter25_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state26_pp0_stage0_iter25_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state27_pp0_stage0_iter26 = ~(1'b1 == 1'b1); + +assign ap_block_state27_pp0_stage0_iter26_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state27_pp0_stage0_iter26_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state27_pp0_stage0_iter26_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state27_pp0_stage0_iter26_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state27_pp0_stage0_iter26_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state27_pp0_stage0_iter26_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state27_pp0_stage0_iter26_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state27_pp0_stage0_iter26_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state28_pp0_stage0_iter27 = ~(1'b1 == 1'b1); + +assign ap_block_state28_pp0_stage0_iter27_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state28_pp0_stage0_iter27_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state28_pp0_stage0_iter27_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state28_pp0_stage0_iter27_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state28_pp0_stage0_iter27_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state28_pp0_stage0_iter27_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state28_pp0_stage0_iter27_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state28_pp0_stage0_iter27_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state29_pp0_stage0_iter28 = ~(1'b1 == 1'b1); + +assign ap_block_state29_pp0_stage0_iter28_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state29_pp0_stage0_iter28_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state29_pp0_stage0_iter28_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state29_pp0_stage0_iter28_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state29_pp0_stage0_iter28_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state29_pp0_stage0_iter28_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state29_pp0_stage0_iter28_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state29_pp0_stage0_iter28_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state30_pp0_stage0_iter29 = ~(1'b1 == 1'b1); + +assign ap_block_state30_pp0_stage0_iter29_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state30_pp0_stage0_iter29_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state30_pp0_stage0_iter29_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state30_pp0_stage0_iter29_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state30_pp0_stage0_iter29_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state30_pp0_stage0_iter29_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state30_pp0_stage0_iter29_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state30_pp0_stage0_iter29_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state31_pp0_stage0_iter30 = ~(1'b1 == 1'b1); + +assign ap_block_state31_pp0_stage0_iter30_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state31_pp0_stage0_iter30_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state31_pp0_stage0_iter30_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state31_pp0_stage0_iter30_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state31_pp0_stage0_iter30_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state31_pp0_stage0_iter30_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state31_pp0_stage0_iter30_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state31_pp0_stage0_iter30_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state32_pp0_stage0_iter31 = ~(1'b1 == 1'b1); + +assign ap_block_state32_pp0_stage0_iter31_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state32_pp0_stage0_iter31_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state32_pp0_stage0_iter31_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state32_pp0_stage0_iter31_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state32_pp0_stage0_iter31_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state32_pp0_stage0_iter31_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state32_pp0_stage0_iter31_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state32_pp0_stage0_iter31_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state33_pp0_stage0_iter32 = ~(1'b1 == 1'b1); + +assign ap_block_state33_pp0_stage0_iter32_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state33_pp0_stage0_iter32_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state33_pp0_stage0_iter32_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state33_pp0_stage0_iter32_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state33_pp0_stage0_iter32_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state33_pp0_stage0_iter32_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state33_pp0_stage0_iter32_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state33_pp0_stage0_iter32_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state34_pp0_stage0_iter33 = ~(1'b1 == 1'b1); + +assign ap_block_state34_pp0_stage0_iter33_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state34_pp0_stage0_iter33_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state34_pp0_stage0_iter33_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state34_pp0_stage0_iter33_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state34_pp0_stage0_iter33_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state34_pp0_stage0_iter33_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state34_pp0_stage0_iter33_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state34_pp0_stage0_iter33_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state35_pp0_stage0_iter34 = ~(1'b1 == 1'b1); + +assign ap_block_state35_pp0_stage0_iter34_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state35_pp0_stage0_iter34_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state35_pp0_stage0_iter34_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state35_pp0_stage0_iter34_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state35_pp0_stage0_iter34_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state35_pp0_stage0_iter34_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state35_pp0_stage0_iter34_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state35_pp0_stage0_iter34_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state36_pp0_stage0_iter35 = ~(1'b1 == 1'b1); + +assign ap_block_state36_pp0_stage0_iter35_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state36_pp0_stage0_iter35_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state36_pp0_stage0_iter35_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state36_pp0_stage0_iter35_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state36_pp0_stage0_iter35_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state36_pp0_stage0_iter35_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state36_pp0_stage0_iter35_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state36_pp0_stage0_iter35_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state37_pp0_stage0_iter36 = ~(1'b1 == 1'b1); + +assign ap_block_state37_pp0_stage0_iter36_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state37_pp0_stage0_iter36_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state37_pp0_stage0_iter36_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state37_pp0_stage0_iter36_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state37_pp0_stage0_iter36_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state37_pp0_stage0_iter36_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state37_pp0_stage0_iter36_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state37_pp0_stage0_iter36_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state38_pp0_stage0_iter37 = ~(1'b1 == 1'b1); + +assign ap_block_state38_pp0_stage0_iter37_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state38_pp0_stage0_iter37_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state38_pp0_stage0_iter37_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state38_pp0_stage0_iter37_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state38_pp0_stage0_iter37_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state38_pp0_stage0_iter37_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state38_pp0_stage0_iter37_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state38_pp0_stage0_iter37_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state39_pp0_stage0_iter38 = ~(1'b1 == 1'b1); + +assign ap_block_state39_pp0_stage0_iter38_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state39_pp0_stage0_iter38_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state39_pp0_stage0_iter38_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state39_pp0_stage0_iter38_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state39_pp0_stage0_iter38_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state39_pp0_stage0_iter38_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state39_pp0_stage0_iter38_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state39_pp0_stage0_iter38_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state40_pp0_stage0_iter39 = ~(1'b1 == 1'b1); + +assign ap_block_state40_pp0_stage0_iter39_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state40_pp0_stage0_iter39_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state40_pp0_stage0_iter39_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state40_pp0_stage0_iter39_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state40_pp0_stage0_iter39_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state40_pp0_stage0_iter39_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state40_pp0_stage0_iter39_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state40_pp0_stage0_iter39_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state41_pp0_stage0_iter40 = ~(1'b1 == 1'b1); + +assign ap_block_state41_pp0_stage0_iter40_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state41_pp0_stage0_iter40_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state41_pp0_stage0_iter40_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state41_pp0_stage0_iter40_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state41_pp0_stage0_iter40_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state41_pp0_stage0_iter40_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state41_pp0_stage0_iter40_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state41_pp0_stage0_iter40_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state42_pp0_stage0_iter41 = ~(1'b1 == 1'b1); + +assign ap_block_state42_pp0_stage0_iter41_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state42_pp0_stage0_iter41_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state42_pp0_stage0_iter41_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state42_pp0_stage0_iter41_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state42_pp0_stage0_iter41_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state42_pp0_stage0_iter41_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state42_pp0_stage0_iter41_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state42_pp0_stage0_iter41_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state43_pp0_stage0_iter42 = ~(1'b1 == 1'b1); + +assign ap_block_state43_pp0_stage0_iter42_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state43_pp0_stage0_iter42_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state43_pp0_stage0_iter42_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state43_pp0_stage0_iter42_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state43_pp0_stage0_iter42_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state43_pp0_stage0_iter42_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state43_pp0_stage0_iter42_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state43_pp0_stage0_iter42_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state44_pp0_stage0_iter43 = ~(1'b1 == 1'b1); + +assign ap_block_state44_pp0_stage0_iter43_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state44_pp0_stage0_iter43_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state44_pp0_stage0_iter43_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state44_pp0_stage0_iter43_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state44_pp0_stage0_iter43_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state44_pp0_stage0_iter43_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state44_pp0_stage0_iter43_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state44_pp0_stage0_iter43_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state45_pp0_stage0_iter44 = ~(1'b1 == 1'b1); + +assign ap_block_state45_pp0_stage0_iter44_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state45_pp0_stage0_iter44_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state45_pp0_stage0_iter44_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state45_pp0_stage0_iter44_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state45_pp0_stage0_iter44_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state45_pp0_stage0_iter44_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state45_pp0_stage0_iter44_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state45_pp0_stage0_iter44_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state46_pp0_stage0_iter45 = ~(1'b1 == 1'b1); + +assign ap_block_state46_pp0_stage0_iter45_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state46_pp0_stage0_iter45_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state46_pp0_stage0_iter45_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state46_pp0_stage0_iter45_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state46_pp0_stage0_iter45_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state46_pp0_stage0_iter45_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state46_pp0_stage0_iter45_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state46_pp0_stage0_iter45_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state47_pp0_stage0_iter46 = ~(1'b1 == 1'b1); + +assign ap_block_state47_pp0_stage0_iter46_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state47_pp0_stage0_iter46_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state47_pp0_stage0_iter46_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state47_pp0_stage0_iter46_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state47_pp0_stage0_iter46_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state47_pp0_stage0_iter46_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state47_pp0_stage0_iter46_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state47_pp0_stage0_iter46_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state48_pp0_stage0_iter47 = ~(1'b1 == 1'b1); + +assign ap_block_state48_pp0_stage0_iter47_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state48_pp0_stage0_iter47_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state48_pp0_stage0_iter47_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state48_pp0_stage0_iter47_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state48_pp0_stage0_iter47_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state48_pp0_stage0_iter47_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state48_pp0_stage0_iter47_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state48_pp0_stage0_iter47_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state49_pp0_stage0_iter48 = ~(1'b1 == 1'b1); + +assign ap_block_state49_pp0_stage0_iter48_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state49_pp0_stage0_iter48_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state49_pp0_stage0_iter48_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state49_pp0_stage0_iter48_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state49_pp0_stage0_iter48_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state49_pp0_stage0_iter48_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state49_pp0_stage0_iter48_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state49_pp0_stage0_iter48_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter3_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter3_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter3_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter3_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter3_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter3_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter3_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter3_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state50_pp0_stage0_iter49 = ~(1'b1 == 1'b1); + +assign ap_block_state50_pp0_stage0_iter49_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state50_pp0_stage0_iter49_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state50_pp0_stage0_iter49_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state50_pp0_stage0_iter49_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state50_pp0_stage0_iter49_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state50_pp0_stage0_iter49_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state50_pp0_stage0_iter49_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state50_pp0_stage0_iter49_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state51_pp0_stage0_iter50 = ~(1'b1 == 1'b1); + +assign ap_block_state51_pp0_stage0_iter50_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state51_pp0_stage0_iter50_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state51_pp0_stage0_iter50_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state51_pp0_stage0_iter50_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state51_pp0_stage0_iter50_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state51_pp0_stage0_iter50_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state51_pp0_stage0_iter50_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state51_pp0_stage0_iter50_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state52_pp0_stage0_iter51 = ~(1'b1 == 1'b1); + +assign ap_block_state52_pp0_stage0_iter51_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state52_pp0_stage0_iter51_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state52_pp0_stage0_iter51_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state52_pp0_stage0_iter51_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state52_pp0_stage0_iter51_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state52_pp0_stage0_iter51_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state52_pp0_stage0_iter51_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state52_pp0_stage0_iter51_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state53_pp0_stage0_iter52 = ~(1'b1 == 1'b1); + +assign ap_block_state53_pp0_stage0_iter52_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state53_pp0_stage0_iter52_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state53_pp0_stage0_iter52_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state53_pp0_stage0_iter52_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state53_pp0_stage0_iter52_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state53_pp0_stage0_iter52_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state53_pp0_stage0_iter52_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state53_pp0_stage0_iter52_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state54_pp0_stage0_iter53 = ~(1'b1 == 1'b1); + +assign ap_block_state54_pp0_stage0_iter53_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state54_pp0_stage0_iter53_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state54_pp0_stage0_iter53_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state54_pp0_stage0_iter53_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state54_pp0_stage0_iter53_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state54_pp0_stage0_iter53_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state54_pp0_stage0_iter53_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state54_pp0_stage0_iter53_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state55_pp0_stage0_iter54 = ~(1'b1 == 1'b1); + +assign ap_block_state55_pp0_stage0_iter54_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state55_pp0_stage0_iter54_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state55_pp0_stage0_iter54_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state55_pp0_stage0_iter54_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state55_pp0_stage0_iter54_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state55_pp0_stage0_iter54_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state55_pp0_stage0_iter54_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state55_pp0_stage0_iter54_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state56_pp0_stage0_iter55 = ~(1'b1 == 1'b1); + +assign ap_block_state56_pp0_stage0_iter55_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state56_pp0_stage0_iter55_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state56_pp0_stage0_iter55_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state56_pp0_stage0_iter55_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state56_pp0_stage0_iter55_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state56_pp0_stage0_iter55_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state56_pp0_stage0_iter55_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state56_pp0_stage0_iter55_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state57_pp0_stage0_iter56 = ~(1'b1 == 1'b1); + +assign ap_block_state57_pp0_stage0_iter56_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state57_pp0_stage0_iter56_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state57_pp0_stage0_iter56_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state57_pp0_stage0_iter56_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state57_pp0_stage0_iter56_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state57_pp0_stage0_iter56_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state57_pp0_stage0_iter56_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state57_pp0_stage0_iter56_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state58_pp0_stage0_iter57 = ~(1'b1 == 1'b1); + +assign ap_block_state58_pp0_stage0_iter57_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state58_pp0_stage0_iter57_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state58_pp0_stage0_iter57_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state58_pp0_stage0_iter57_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state58_pp0_stage0_iter57_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state58_pp0_stage0_iter57_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state58_pp0_stage0_iter57_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state58_pp0_stage0_iter57_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state59_pp0_stage0_iter58 = ~(1'b1 == 1'b1); + +assign ap_block_state59_pp0_stage0_iter58_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state59_pp0_stage0_iter58_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state59_pp0_stage0_iter58_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state59_pp0_stage0_iter58_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state59_pp0_stage0_iter58_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state59_pp0_stage0_iter58_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state59_pp0_stage0_iter58_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state59_pp0_stage0_iter58_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter4_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter4_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter4_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter4_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter4_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter4_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter4_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter4_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state60_pp0_stage0_iter59 = ~(1'b1 == 1'b1); + +assign ap_block_state60_pp0_stage0_iter59_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state60_pp0_stage0_iter59_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state60_pp0_stage0_iter59_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state60_pp0_stage0_iter59_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state60_pp0_stage0_iter59_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state60_pp0_stage0_iter59_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state60_pp0_stage0_iter59_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state60_pp0_stage0_iter59_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state61_pp0_stage0_iter60 = ~(1'b1 == 1'b1); + +assign ap_block_state61_pp0_stage0_iter60_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state61_pp0_stage0_iter60_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state61_pp0_stage0_iter60_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state61_pp0_stage0_iter60_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state61_pp0_stage0_iter60_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state61_pp0_stage0_iter60_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state61_pp0_stage0_iter60_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state61_pp0_stage0_iter60_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state62_pp0_stage0_iter61 = ~(1'b1 == 1'b1); + +assign ap_block_state62_pp0_stage0_iter61_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state62_pp0_stage0_iter61_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state62_pp0_stage0_iter61_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state62_pp0_stage0_iter61_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state62_pp0_stage0_iter61_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state62_pp0_stage0_iter61_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state62_pp0_stage0_iter61_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state62_pp0_stage0_iter61_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state63_pp0_stage0_iter62 = ~(1'b1 == 1'b1); + +assign ap_block_state63_pp0_stage0_iter62_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state63_pp0_stage0_iter62_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state63_pp0_stage0_iter62_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state63_pp0_stage0_iter62_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state63_pp0_stage0_iter62_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state63_pp0_stage0_iter62_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state63_pp0_stage0_iter62_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state63_pp0_stage0_iter62_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state64_pp0_stage0_iter63 = ~(1'b1 == 1'b1); + +assign ap_block_state64_pp0_stage0_iter63_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state64_pp0_stage0_iter63_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state64_pp0_stage0_iter63_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state64_pp0_stage0_iter63_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state64_pp0_stage0_iter63_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state64_pp0_stage0_iter63_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state64_pp0_stage0_iter63_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state64_pp0_stage0_iter63_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state65_pp0_stage0_iter64 = ~(1'b1 == 1'b1); + +assign ap_block_state65_pp0_stage0_iter64_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state65_pp0_stage0_iter64_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state65_pp0_stage0_iter64_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state65_pp0_stage0_iter64_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state65_pp0_stage0_iter64_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state65_pp0_stage0_iter64_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state65_pp0_stage0_iter64_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state65_pp0_stage0_iter64_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state66_pp0_stage0_iter65 = ~(1'b1 == 1'b1); + +assign ap_block_state66_pp0_stage0_iter65_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state66_pp0_stage0_iter65_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state66_pp0_stage0_iter65_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state66_pp0_stage0_iter65_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state66_pp0_stage0_iter65_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state66_pp0_stage0_iter65_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state66_pp0_stage0_iter65_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state66_pp0_stage0_iter65_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state67_pp0_stage0_iter66 = ~(1'b1 == 1'b1); + +assign ap_block_state67_pp0_stage0_iter66_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state67_pp0_stage0_iter66_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state67_pp0_stage0_iter66_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state67_pp0_stage0_iter66_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state67_pp0_stage0_iter66_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state67_pp0_stage0_iter66_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state67_pp0_stage0_iter66_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state67_pp0_stage0_iter66_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state68_pp0_stage0_iter67 = ~(1'b1 == 1'b1); + +assign ap_block_state68_pp0_stage0_iter67_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state68_pp0_stage0_iter67_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state68_pp0_stage0_iter67_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state68_pp0_stage0_iter67_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state68_pp0_stage0_iter67_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state68_pp0_stage0_iter67_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state68_pp0_stage0_iter67_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state68_pp0_stage0_iter67_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter5_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter5_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter5_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter5_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter5_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter5_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter5_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter5_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter6_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter6_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter6_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter6_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter6_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter6_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter6_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter6_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter7_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter7_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter7_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter7_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter7_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter7_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter7_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter7_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter8_ignore_call15 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter8_ignore_call210 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter8_ignore_call243 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter8_ignore_call309 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter8_ignore_call342 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter8_ignore_call408 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter8_ignore_call414 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter8_ignore_call80 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_enable_reg_pp0_iter0 = ap_start; + +assign const_size_in_1 = 16'd16; + +assign const_size_out_1 = 16'd5; + +assign layer16_out_0_V = grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_return_0; + +assign layer16_out_1_V = grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_return_1; + +assign layer16_out_2_V = grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_return_2; + +assign layer16_out_3_V = grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_return_3; + +assign layer16_out_4_V = grp_normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0_fu_551_ap_return_4; + +endmodule //myproject +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1 ( + ap_clk, + ap_rst, + data_0_V_read, + data_1_V_read, + data_2_V_read, + data_3_V_read, + data_4_V_read, + data_5_V_read, + data_6_V_read, + data_7_V_read, + data_8_V_read, + data_9_V_read, + data_10_V_read, + data_11_V_read, + data_12_V_read, + data_13_V_read, + data_14_V_read, + data_15_V_read, + data_16_V_read, + data_17_V_read, + data_18_V_read, + data_19_V_read, + data_20_V_read, + data_21_V_read, + data_22_V_read, + data_23_V_read, + data_24_V_read, + data_25_V_read, + data_26_V_read, + data_27_V_read, + data_28_V_read, + data_29_V_read, + data_30_V_read, + data_31_V_read, + data_32_V_read, + data_33_V_read, + data_34_V_read, + data_35_V_read, + data_36_V_read, + data_37_V_read, + data_38_V_read, + data_39_V_read, + data_40_V_read, + data_41_V_read, + data_42_V_read, + data_43_V_read, + data_44_V_read, + data_45_V_read, + data_46_V_read, + data_47_V_read, + data_48_V_read, + data_49_V_read, + data_50_V_read, + data_51_V_read, + data_52_V_read, + data_53_V_read, + data_54_V_read, + data_55_V_read, + data_56_V_read, + data_57_V_read, + data_58_V_read, + data_59_V_read, + data_60_V_read, + data_61_V_read, + data_62_V_read, + data_63_V_read, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3, + ap_return_4, + ap_return_5, + ap_return_6, + ap_return_7, + ap_return_8, + ap_return_9, + ap_return_10, + ap_return_11, + ap_return_12, + ap_return_13, + ap_return_14, + ap_return_15, + ap_return_16, + ap_return_17, + ap_return_18, + ap_return_19, + ap_return_20, + ap_return_21, + ap_return_22, + ap_return_23, + ap_return_24, + ap_return_25, + ap_return_26, + ap_return_27, + ap_return_28, + ap_return_29, + ap_return_30, + ap_return_31, + ap_return_32, + ap_return_33, + ap_return_34, + ap_return_35, + ap_return_36, + ap_return_37, + ap_return_38, + ap_return_39, + ap_return_40, + ap_return_41, + ap_return_42, + ap_return_43, + ap_return_44, + ap_return_45, + ap_return_46, + ap_return_47, + ap_return_48, + ap_return_49, + ap_return_50, + ap_return_51, + ap_return_52, + ap_return_53, + ap_return_54, + ap_return_55, + ap_return_56, + ap_return_57, + ap_return_58, + ap_return_59, + ap_return_60, + ap_return_61, + ap_return_62, + ap_return_63, + ap_ce +); + + +input ap_clk; +input ap_rst; +input [15:0] data_0_V_read; +input [15:0] data_1_V_read; +input [15:0] data_2_V_read; +input [15:0] data_3_V_read; +input [15:0] data_4_V_read; +input [15:0] data_5_V_read; +input [15:0] data_6_V_read; +input [15:0] data_7_V_read; +input [15:0] data_8_V_read; +input [15:0] data_9_V_read; +input [15:0] data_10_V_read; +input [15:0] data_11_V_read; +input [15:0] data_12_V_read; +input [15:0] data_13_V_read; +input [15:0] data_14_V_read; +input [15:0] data_15_V_read; +input [15:0] data_16_V_read; +input [15:0] data_17_V_read; +input [15:0] data_18_V_read; +input [15:0] data_19_V_read; +input [15:0] data_20_V_read; +input [15:0] data_21_V_read; +input [15:0] data_22_V_read; +input [15:0] data_23_V_read; +input [15:0] data_24_V_read; +input [15:0] data_25_V_read; +input [15:0] data_26_V_read; +input [15:0] data_27_V_read; +input [15:0] data_28_V_read; +input [15:0] data_29_V_read; +input [15:0] data_30_V_read; +input [15:0] data_31_V_read; +input [15:0] data_32_V_read; +input [15:0] data_33_V_read; +input [15:0] data_34_V_read; +input [15:0] data_35_V_read; +input [15:0] data_36_V_read; +input [15:0] data_37_V_read; +input [15:0] data_38_V_read; +input [15:0] data_39_V_read; +input [15:0] data_40_V_read; +input [15:0] data_41_V_read; +input [15:0] data_42_V_read; +input [15:0] data_43_V_read; +input [15:0] data_44_V_read; +input [15:0] data_45_V_read; +input [15:0] data_46_V_read; +input [15:0] data_47_V_read; +input [15:0] data_48_V_read; +input [15:0] data_49_V_read; +input [15:0] data_50_V_read; +input [15:0] data_51_V_read; +input [15:0] data_52_V_read; +input [15:0] data_53_V_read; +input [15:0] data_54_V_read; +input [15:0] data_55_V_read; +input [15:0] data_56_V_read; +input [15:0] data_57_V_read; +input [15:0] data_58_V_read; +input [15:0] data_59_V_read; +input [15:0] data_60_V_read; +input [15:0] data_61_V_read; +input [15:0] data_62_V_read; +input [15:0] data_63_V_read; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; +output [15:0] ap_return_4; +output [15:0] ap_return_5; +output [15:0] ap_return_6; +output [15:0] ap_return_7; +output [15:0] ap_return_8; +output [15:0] ap_return_9; +output [15:0] ap_return_10; +output [15:0] ap_return_11; +output [15:0] ap_return_12; +output [15:0] ap_return_13; +output [15:0] ap_return_14; +output [15:0] ap_return_15; +output [15:0] ap_return_16; +output [15:0] ap_return_17; +output [15:0] ap_return_18; +output [15:0] ap_return_19; +output [15:0] ap_return_20; +output [15:0] ap_return_21; +output [15:0] ap_return_22; +output [15:0] ap_return_23; +output [15:0] ap_return_24; +output [15:0] ap_return_25; +output [15:0] ap_return_26; +output [15:0] ap_return_27; +output [15:0] ap_return_28; +output [15:0] ap_return_29; +output [15:0] ap_return_30; +output [15:0] ap_return_31; +output [15:0] ap_return_32; +output [15:0] ap_return_33; +output [15:0] ap_return_34; +output [15:0] ap_return_35; +output [15:0] ap_return_36; +output [15:0] ap_return_37; +output [15:0] ap_return_38; +output [15:0] ap_return_39; +output [15:0] ap_return_40; +output [15:0] ap_return_41; +output [15:0] ap_return_42; +output [15:0] ap_return_43; +output [15:0] ap_return_44; +output [15:0] ap_return_45; +output [15:0] ap_return_46; +output [15:0] ap_return_47; +output [15:0] ap_return_48; +output [15:0] ap_return_49; +output [15:0] ap_return_50; +output [15:0] ap_return_51; +output [15:0] ap_return_52; +output [15:0] ap_return_53; +output [15:0] ap_return_54; +output [15:0] ap_return_55; +output [15:0] ap_return_56; +output [15:0] ap_return_57; +output [15:0] ap_return_58; +output [15:0] ap_return_59; +output [15:0] ap_return_60; +output [15:0] ap_return_61; +output [15:0] ap_return_62; +output [15:0] ap_return_63; +input ap_ce; + +reg[15:0] ap_return_0; +reg[15:0] ap_return_1; +reg[15:0] ap_return_2; +reg[15:0] ap_return_3; +reg[15:0] ap_return_4; +reg[15:0] ap_return_5; +reg[15:0] ap_return_6; +reg[15:0] ap_return_7; +reg[15:0] ap_return_8; +reg[15:0] ap_return_9; +reg[15:0] ap_return_10; +reg[15:0] ap_return_11; +reg[15:0] ap_return_12; +reg[15:0] ap_return_13; +reg[15:0] ap_return_14; +reg[15:0] ap_return_15; +reg[15:0] ap_return_16; +reg[15:0] ap_return_17; +reg[15:0] ap_return_18; +reg[15:0] ap_return_19; +reg[15:0] ap_return_20; +reg[15:0] ap_return_21; +reg[15:0] ap_return_22; +reg[15:0] ap_return_23; +reg[15:0] ap_return_24; +reg[15:0] ap_return_25; +reg[15:0] ap_return_26; +reg[15:0] ap_return_27; +reg[15:0] ap_return_28; +reg[15:0] ap_return_29; +reg[15:0] ap_return_30; +reg[15:0] ap_return_31; +reg[15:0] ap_return_32; +reg[15:0] ap_return_33; +reg[15:0] ap_return_34; +reg[15:0] ap_return_35; +reg[15:0] ap_return_36; +reg[15:0] ap_return_37; +reg[15:0] ap_return_38; +reg[15:0] ap_return_39; +reg[15:0] ap_return_40; +reg[15:0] ap_return_41; +reg[15:0] ap_return_42; +reg[15:0] ap_return_43; +reg[15:0] ap_return_44; +reg[15:0] ap_return_45; +reg[15:0] ap_return_46; +reg[15:0] ap_return_47; +reg[15:0] ap_return_48; +reg[15:0] ap_return_49; +reg[15:0] ap_return_50; +reg[15:0] ap_return_51; +reg[15:0] ap_return_52; +reg[15:0] ap_return_53; +reg[15:0] ap_return_54; +reg[15:0] ap_return_55; +reg[15:0] ap_return_56; +reg[15:0] ap_return_57; +reg[15:0] ap_return_58; +reg[15:0] ap_return_59; +reg[15:0] ap_return_60; +reg[15:0] ap_return_61; +reg[15:0] ap_return_62; +reg[15:0] ap_return_63; + +reg [15:0] data_46_V_read_2_reg_18625; +wire ap_block_state1_pp0_stage0_iter0; +wire ap_block_state2_pp0_stage0_iter1; +wire ap_block_state3_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [15:0] data_42_V_read_2_reg_18631; +reg [15:0] data_39_V_read_2_reg_18637; +reg [15:0] trunc_ln_reg_18948; +reg [15:0] trunc_ln708_31_reg_18953; +reg [15:0] trunc_ln708_32_reg_18958; +reg [15:0] trunc_ln708_s_reg_18963; +reg [15:0] trunc_ln708_33_reg_18968; +reg [15:0] trunc_ln708_34_reg_18973; +reg [15:0] trunc_ln708_35_reg_18978; +reg [15:0] trunc_ln708_36_reg_18983; +reg [15:0] trunc_ln708_37_reg_18988; +reg [15:0] trunc_ln708_38_reg_18993; +reg [15:0] trunc_ln708_39_reg_18998; +reg [15:0] trunc_ln708_40_reg_19003; +reg [15:0] trunc_ln708_41_reg_19008; +reg [15:0] trunc_ln708_42_reg_19013; +reg [15:0] trunc_ln708_43_reg_19018; +reg [15:0] trunc_ln708_44_reg_19023; +reg [15:0] trunc_ln708_45_reg_19028; +reg [15:0] trunc_ln708_46_reg_19033; +reg [15:0] trunc_ln708_47_reg_19038; +reg [15:0] trunc_ln708_48_reg_19043; +reg [15:0] trunc_ln708_49_reg_19048; +reg [15:0] trunc_ln708_50_reg_19053; +reg [15:0] trunc_ln708_51_reg_19058; +reg [15:0] trunc_ln708_52_reg_19063; +reg [15:0] trunc_ln708_53_reg_19068; +reg [15:0] trunc_ln708_54_reg_19073; +reg [15:0] trunc_ln708_55_reg_19078; +reg [15:0] trunc_ln708_56_reg_19083; +reg [15:0] trunc_ln708_57_reg_19088; +reg [15:0] trunc_ln708_58_reg_19093; +reg [15:0] trunc_ln708_59_reg_19098; +reg [15:0] trunc_ln708_60_reg_19103; +reg [15:0] trunc_ln708_61_reg_19108; +reg [15:0] trunc_ln708_62_reg_19113; +reg [15:0] trunc_ln708_63_reg_19118; +reg [15:0] trunc_ln708_64_reg_19123; +reg [15:0] trunc_ln708_65_reg_19128; +reg [15:0] trunc_ln708_66_reg_19133; +reg [15:0] trunc_ln708_67_reg_19138; +reg [15:0] trunc_ln708_68_reg_19143; +reg [15:0] trunc_ln708_69_reg_19148; +reg [15:0] trunc_ln708_70_reg_19153; +reg [15:0] trunc_ln708_71_reg_19158; +reg [15:0] trunc_ln708_72_reg_19163; +reg [15:0] trunc_ln708_73_reg_19168; +reg [15:0] trunc_ln708_74_reg_19173; +reg [15:0] trunc_ln708_75_reg_19178; +reg [15:0] trunc_ln708_76_reg_19183; +reg [15:0] trunc_ln708_77_reg_19188; +reg [15:0] trunc_ln708_78_reg_19193; +reg [15:0] trunc_ln708_79_reg_19198; +reg [15:0] trunc_ln708_80_reg_19203; +reg [15:0] trunc_ln708_81_reg_19208; +reg [15:0] trunc_ln708_82_reg_19213; +reg [15:0] trunc_ln708_83_reg_19218; +reg [15:0] trunc_ln708_84_reg_19223; +reg [15:0] trunc_ln708_85_reg_19228; +reg [15:0] trunc_ln708_86_reg_19233; +reg [15:0] trunc_ln708_87_reg_19238; +reg [15:0] trunc_ln708_88_reg_19243; +reg [15:0] trunc_ln708_89_reg_19248; +reg [15:0] trunc_ln708_90_reg_19253; +reg [15:0] trunc_ln708_91_reg_19258; +reg [15:0] trunc_ln708_92_reg_19263; +wire [11:0] grp_fu_804_p1; +wire ap_block_pp0_stage0; +wire [11:0] grp_fu_805_p1; +wire [11:0] grp_fu_806_p1; +wire [11:0] grp_fu_807_p1; +wire [10:0] grp_fu_808_p1; +wire [10:0] grp_fu_809_p1; +wire [11:0] grp_fu_810_p1; +wire [10:0] grp_fu_811_p1; +wire [11:0] grp_fu_812_p1; +wire [12:0] grp_fu_813_p1; +wire [11:0] grp_fu_814_p1; +wire [11:0] grp_fu_815_p1; +wire [11:0] grp_fu_816_p1; +wire [11:0] grp_fu_818_p1; +wire [10:0] grp_fu_819_p1; +wire [11:0] grp_fu_820_p1; +wire [11:0] grp_fu_821_p1; +wire [11:0] grp_fu_822_p1; +wire [11:0] grp_fu_823_p1; +wire [11:0] grp_fu_824_p1; +wire [10:0] grp_fu_825_p1; +wire [11:0] grp_fu_826_p1; +wire [11:0] grp_fu_827_p1; +wire [10:0] grp_fu_828_p1; +wire [10:0] grp_fu_829_p1; +wire [11:0] grp_fu_830_p1; +wire [10:0] grp_fu_831_p1; +wire [10:0] grp_fu_832_p1; +wire [11:0] grp_fu_833_p1; +wire [10:0] grp_fu_834_p1; +wire [11:0] grp_fu_835_p1; +wire [11:0] grp_fu_837_p1; +wire [12:0] grp_fu_838_p1; +wire [10:0] grp_fu_839_p1; +wire [11:0] grp_fu_840_p1; +wire [10:0] grp_fu_841_p1; +wire [11:0] grp_fu_842_p1; +wire [10:0] grp_fu_843_p1; +wire [10:0] grp_fu_844_p1; +wire [10:0] grp_fu_845_p1; +wire [11:0] grp_fu_846_p1; +wire [11:0] grp_fu_847_p1; +wire [10:0] grp_fu_848_p1; +wire [11:0] grp_fu_849_p1; +wire [10:0] grp_fu_850_p1; +wire [11:0] grp_fu_851_p1; +wire [11:0] grp_fu_852_p1; +wire [10:0] grp_fu_853_p1; +wire [12:0] grp_fu_854_p1; +wire [11:0] grp_fu_855_p1; +wire [10:0] grp_fu_856_p1; +wire [11:0] grp_fu_857_p1; +wire [10:0] grp_fu_858_p1; +wire [11:0] grp_fu_859_p1; +wire [11:0] grp_fu_860_p1; +wire [11:0] grp_fu_861_p1; +wire [11:0] grp_fu_862_p1; +wire [11:0] grp_fu_863_p1; +wire [10:0] grp_fu_864_p1; +wire [11:0] grp_fu_866_p1; +wire [12:0] grp_fu_867_p1; +wire [25:0] grp_fu_852_p2; +wire [25:0] grp_fu_832_p2; +wire [25:0] grp_fu_860_p2; +wire [25:0] grp_fu_828_p2; +wire [25:0] grp_fu_857_p2; +wire [25:0] grp_fu_846_p2; +wire [25:0] grp_fu_829_p2; +wire [25:0] grp_fu_866_p2; +wire [25:0] grp_fu_819_p2; +wire [25:0] grp_fu_844_p2; +wire [25:0] grp_fu_859_p2; +wire [25:0] grp_fu_856_p2; +wire [25:0] grp_fu_834_p2; +wire [25:0] grp_fu_813_p2; +wire [25:0] grp_fu_816_p2; +wire [25:0] grp_fu_812_p2; +wire [25:0] grp_fu_837_p2; +wire [25:0] grp_fu_849_p2; +wire [25:0] grp_fu_818_p2; +wire [25:0] grp_fu_810_p2; +wire [25:0] grp_fu_815_p2; +wire [25:0] grp_fu_811_p2; +wire [25:0] grp_fu_824_p2; +wire [25:0] grp_fu_830_p2; +wire [25:0] grp_fu_839_p2; +wire [25:0] grp_fu_850_p2; +wire [25:0] grp_fu_827_p2; +wire [25:0] grp_fu_847_p2; +wire [25:0] grp_fu_845_p2; +wire [25:0] grp_fu_853_p2; +wire [25:0] grp_fu_814_p2; +wire [25:0] grp_fu_840_p2; +wire [25:0] grp_fu_808_p2; +wire [25:0] grp_fu_858_p2; +wire [25:0] grp_fu_835_p2; +wire [25:0] grp_fu_804_p2; +wire [25:0] grp_fu_841_p2; +wire [25:0] grp_fu_807_p2; +wire [25:0] grp_fu_825_p2; +wire [22:0] shl_ln1118_5_fu_17614_p3; +wire [25:0] shl_ln_fu_17607_p3; +wire [25:0] sext_ln1118_73_fu_17621_p1; +wire [25:0] add_ln1118_fu_17625_p2; +wire [25:0] grp_fu_867_p2; +wire [25:0] grp_fu_822_p2; +wire [25:0] sext_ln1118_76_fu_17661_p1; +wire [25:0] shl_ln1118_6_fu_17664_p3; +wire [25:0] add_ln1118_1_fu_17671_p2; +wire [25:0] grp_fu_851_p2; +wire [25:0] grp_fu_826_p2; +wire [25:0] grp_fu_855_p2; +wire [21:0] shl_ln1118_8_fu_17724_p3; +wire [25:0] shl_ln1118_7_fu_17717_p3; +wire [25:0] sext_ln1118_80_fu_17731_p1; +wire [25:0] add_ln1118_2_fu_17735_p2; +wire [25:0] grp_fu_838_p2; +wire [25:0] grp_fu_861_p2; +wire [25:0] grp_fu_843_p2; +wire [25:0] grp_fu_862_p2; +wire [25:0] grp_fu_863_p2; +wire [25:0] grp_fu_823_p2; +wire [25:0] grp_fu_848_p2; +wire [25:0] grp_fu_854_p2; +wire [25:0] grp_fu_821_p2; +wire [25:0] grp_fu_831_p2; +wire [25:0] grp_fu_864_p2; +wire [25:0] grp_fu_809_p2; +wire [25:0] grp_fu_842_p2; +wire [25:0] grp_fu_805_p2; +wire [25:0] grp_fu_833_p2; +wire [25:0] grp_fu_806_p2; +wire [25:0] grp_fu_820_p2; +wire [15:0] add_ln703_fu_17921_p2; +wire [15:0] add_ln703_36_fu_17926_p2; +wire [15:0] add_ln703_37_fu_17931_p2; +wire [15:0] add_ln703_38_fu_17936_p2; +wire [15:0] add_ln703_39_fu_17941_p2; +wire [15:0] add_ln703_40_fu_17946_p2; +wire [15:0] add_ln703_41_fu_17951_p2; +wire [15:0] add_ln703_42_fu_17956_p2; +wire [15:0] add_ln703_43_fu_17961_p2; +wire [15:0] add_ln703_44_fu_17966_p2; +wire [15:0] add_ln703_45_fu_17971_p2; +wire [15:0] add_ln703_46_fu_17976_p2; +wire [15:0] add_ln703_47_fu_17981_p2; +wire [15:0] add_ln703_48_fu_17986_p2; +wire [15:0] add_ln703_49_fu_17991_p2; +wire [15:0] add_ln703_50_fu_17996_p2; +wire [15:0] add_ln703_51_fu_18001_p2; +wire [15:0] add_ln703_52_fu_18006_p2; +wire [15:0] add_ln703_53_fu_18011_p2; +wire [15:0] add_ln703_54_fu_18016_p2; +wire [15:0] add_ln703_55_fu_18021_p2; +wire [15:0] add_ln703_56_fu_18026_p2; +wire [15:0] add_ln703_57_fu_18031_p2; +wire [15:0] add_ln703_58_fu_18036_p2; +wire [15:0] add_ln703_59_fu_18041_p2; +wire [15:0] add_ln703_60_fu_18046_p2; +wire [15:0] add_ln703_61_fu_18051_p2; +wire [15:0] add_ln703_62_fu_18056_p2; +wire [15:0] add_ln703_63_fu_18061_p2; +wire [15:0] add_ln703_64_fu_18066_p2; +wire [15:0] add_ln703_65_fu_18071_p2; +wire [15:0] add_ln703_66_fu_18076_p2; +wire [15:0] add_ln703_67_fu_18081_p2; +wire [15:0] add_ln703_68_fu_18086_p2; +wire [15:0] add_ln703_69_fu_18091_p2; +wire [15:0] add_ln703_70_fu_18096_p2; +wire [15:0] add_ln703_71_fu_18101_p2; +wire [15:0] add_ln703_72_fu_18106_p2; +wire [15:0] add_ln703_73_fu_18111_p2; +wire [15:0] add_ln703_74_fu_18116_p2; +wire [15:0] add_ln703_75_fu_18121_p2; +wire [15:0] add_ln703_76_fu_18126_p2; +wire [15:0] add_ln703_77_fu_18131_p2; +wire [15:0] add_ln703_78_fu_18136_p2; +wire [15:0] add_ln703_79_fu_18141_p2; +wire [15:0] add_ln703_80_fu_18146_p2; +wire [15:0] add_ln703_81_fu_18151_p2; +wire [15:0] add_ln703_82_fu_18156_p2; +wire [15:0] add_ln703_83_fu_18161_p2; +wire [15:0] add_ln703_84_fu_18166_p2; +wire [15:0] add_ln703_85_fu_18171_p2; +wire [15:0] add_ln703_86_fu_18176_p2; +wire [15:0] add_ln703_87_fu_18181_p2; +wire [15:0] add_ln703_88_fu_18186_p2; +wire [15:0] add_ln703_89_fu_18191_p2; +wire [15:0] add_ln703_90_fu_18196_p2; +wire [15:0] add_ln703_91_fu_18201_p2; +wire [15:0] add_ln703_92_fu_18206_p2; +wire [15:0] add_ln703_93_fu_18211_p2; +wire [15:0] add_ln703_94_fu_18216_p2; +wire [15:0] add_ln703_95_fu_18221_p2; +wire [15:0] add_ln703_96_fu_18226_p2; +wire [15:0] add_ln703_97_fu_18231_p2; +wire [15:0] add_ln703_98_fu_18236_p2; +reg grp_fu_804_ce; +reg grp_fu_805_ce; +reg grp_fu_806_ce; +reg grp_fu_807_ce; +reg grp_fu_808_ce; +reg grp_fu_809_ce; +reg grp_fu_810_ce; +reg grp_fu_811_ce; +reg grp_fu_812_ce; +reg grp_fu_813_ce; +reg grp_fu_814_ce; +reg grp_fu_815_ce; +reg grp_fu_816_ce; +reg grp_fu_818_ce; +reg grp_fu_819_ce; +reg grp_fu_820_ce; +reg grp_fu_821_ce; +reg grp_fu_822_ce; +reg grp_fu_823_ce; +reg grp_fu_824_ce; +reg grp_fu_825_ce; +reg grp_fu_826_ce; +reg grp_fu_827_ce; +reg grp_fu_828_ce; +reg grp_fu_829_ce; +reg grp_fu_830_ce; +reg grp_fu_831_ce; +reg grp_fu_832_ce; +reg grp_fu_833_ce; +reg grp_fu_834_ce; +reg grp_fu_835_ce; +reg grp_fu_837_ce; +reg grp_fu_838_ce; +reg grp_fu_839_ce; +reg grp_fu_840_ce; +reg grp_fu_841_ce; +reg grp_fu_842_ce; +reg grp_fu_843_ce; +reg grp_fu_844_ce; +reg grp_fu_845_ce; +reg grp_fu_846_ce; +reg grp_fu_847_ce; +reg grp_fu_848_ce; +reg grp_fu_849_ce; +reg grp_fu_850_ce; +reg grp_fu_851_ce; +reg grp_fu_852_ce; +reg grp_fu_853_ce; +reg grp_fu_854_ce; +reg grp_fu_855_ce; +reg grp_fu_856_ce; +reg grp_fu_857_ce; +reg grp_fu_858_ce; +reg grp_fu_859_ce; +reg grp_fu_860_ce; +reg grp_fu_861_ce; +reg grp_fu_862_ce; +reg grp_fu_863_ce; +reg grp_fu_864_ce; +reg grp_fu_866_ce; +reg grp_fu_867_ce; +reg ap_ce_reg; +reg [15:0] data_0_V_read_int_reg; +reg [15:0] data_1_V_read_int_reg; +reg [15:0] data_2_V_read_int_reg; +reg [15:0] data_3_V_read_int_reg; +reg [15:0] data_4_V_read_int_reg; +reg [15:0] data_5_V_read_int_reg; +reg [15:0] data_6_V_read_int_reg; +reg [15:0] data_7_V_read_int_reg; +reg [15:0] data_8_V_read_int_reg; +reg [15:0] data_9_V_read_int_reg; +reg [15:0] data_10_V_read_int_reg; +reg [15:0] data_11_V_read_int_reg; +reg [15:0] data_12_V_read_int_reg; +reg [15:0] data_13_V_read_int_reg; +reg [15:0] data_14_V_read_int_reg; +reg [15:0] data_15_V_read_int_reg; +reg [15:0] data_16_V_read_int_reg; +reg [15:0] data_17_V_read_int_reg; +reg [15:0] data_18_V_read_int_reg; +reg [15:0] data_19_V_read_int_reg; +reg [15:0] data_20_V_read_int_reg; +reg [15:0] data_21_V_read_int_reg; +reg [15:0] data_22_V_read_int_reg; +reg [15:0] data_23_V_read_int_reg; +reg [15:0] data_24_V_read_int_reg; +reg [15:0] data_25_V_read_int_reg; +reg [15:0] data_26_V_read_int_reg; +reg [15:0] data_27_V_read_int_reg; +reg [15:0] data_28_V_read_int_reg; +reg [15:0] data_29_V_read_int_reg; +reg [15:0] data_30_V_read_int_reg; +reg [15:0] data_31_V_read_int_reg; +reg [15:0] data_32_V_read_int_reg; +reg [15:0] data_33_V_read_int_reg; +reg [15:0] data_34_V_read_int_reg; +reg [15:0] data_35_V_read_int_reg; +reg [15:0] data_36_V_read_int_reg; +reg [15:0] data_37_V_read_int_reg; +reg [15:0] data_38_V_read_int_reg; +reg [15:0] data_39_V_read_int_reg; +reg [15:0] data_40_V_read_int_reg; +reg [15:0] data_41_V_read_int_reg; +reg [15:0] data_42_V_read_int_reg; +reg [15:0] data_43_V_read_int_reg; +reg [15:0] data_44_V_read_int_reg; +reg [15:0] data_45_V_read_int_reg; +reg [15:0] data_46_V_read_int_reg; +reg [15:0] data_47_V_read_int_reg; +reg [15:0] data_48_V_read_int_reg; +reg [15:0] data_49_V_read_int_reg; +reg [15:0] data_50_V_read_int_reg; +reg [15:0] data_51_V_read_int_reg; +reg [15:0] data_52_V_read_int_reg; +reg [15:0] data_53_V_read_int_reg; +reg [15:0] data_54_V_read_int_reg; +reg [15:0] data_55_V_read_int_reg; +reg [15:0] data_56_V_read_int_reg; +reg [15:0] data_57_V_read_int_reg; +reg [15:0] data_58_V_read_int_reg; +reg [15:0] data_59_V_read_int_reg; +reg [15:0] data_60_V_read_int_reg; +reg [15:0] data_61_V_read_int_reg; +reg [15:0] data_62_V_read_int_reg; +reg [15:0] data_63_V_read_int_reg; +reg [15:0] ap_return_0_int_reg; +reg [15:0] ap_return_1_int_reg; +reg [15:0] ap_return_2_int_reg; +reg [15:0] ap_return_3_int_reg; +reg [15:0] ap_return_4_int_reg; +reg [15:0] ap_return_5_int_reg; +reg [15:0] ap_return_6_int_reg; +reg [15:0] ap_return_7_int_reg; +reg [15:0] ap_return_8_int_reg; +reg [15:0] ap_return_9_int_reg; +reg [15:0] ap_return_10_int_reg; +reg [15:0] ap_return_11_int_reg; +reg [15:0] ap_return_12_int_reg; +reg [15:0] ap_return_13_int_reg; +reg [15:0] ap_return_14_int_reg; +reg [15:0] ap_return_15_int_reg; +reg [15:0] ap_return_16_int_reg; +reg [15:0] ap_return_17_int_reg; +reg [15:0] ap_return_18_int_reg; +reg [15:0] ap_return_19_int_reg; +reg [15:0] ap_return_20_int_reg; +reg [15:0] ap_return_21_int_reg; +reg [15:0] ap_return_22_int_reg; +reg [15:0] ap_return_23_int_reg; +reg [15:0] ap_return_24_int_reg; +reg [15:0] ap_return_25_int_reg; +reg [15:0] ap_return_26_int_reg; +reg [15:0] ap_return_27_int_reg; +reg [15:0] ap_return_28_int_reg; +reg [15:0] ap_return_29_int_reg; +reg [15:0] ap_return_30_int_reg; +reg [15:0] ap_return_31_int_reg; +reg [15:0] ap_return_32_int_reg; +reg [15:0] ap_return_33_int_reg; +reg [15:0] ap_return_34_int_reg; +reg [15:0] ap_return_35_int_reg; +reg [15:0] ap_return_36_int_reg; +reg [15:0] ap_return_37_int_reg; +reg [15:0] ap_return_38_int_reg; +reg [15:0] ap_return_39_int_reg; +reg [15:0] ap_return_40_int_reg; +reg [15:0] ap_return_41_int_reg; +reg [15:0] ap_return_42_int_reg; +reg [15:0] ap_return_43_int_reg; +reg [15:0] ap_return_44_int_reg; +reg [15:0] ap_return_45_int_reg; +reg [15:0] ap_return_46_int_reg; +reg [15:0] ap_return_47_int_reg; +reg [15:0] ap_return_48_int_reg; +reg [15:0] ap_return_49_int_reg; +reg [15:0] ap_return_50_int_reg; +reg [15:0] ap_return_51_int_reg; +reg [15:0] ap_return_52_int_reg; +reg [15:0] ap_return_53_int_reg; +reg [15:0] ap_return_54_int_reg; +reg [15:0] ap_return_55_int_reg; +reg [15:0] ap_return_56_int_reg; +reg [15:0] ap_return_57_int_reg; +reg [15:0] ap_return_58_int_reg; +reg [15:0] ap_return_59_int_reg; +reg [15:0] ap_return_60_int_reg; +reg [15:0] ap_return_61_int_reg; +reg [15:0] ap_return_62_int_reg; +reg [15:0] ap_return_63_int_reg; + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U2( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_35_V_read_int_reg), + .din1(grp_fu_804_p1), + .ce(grp_fu_804_ce), + .dout(grp_fu_804_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U3( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_60_V_read_int_reg), + .din1(grp_fu_805_p1), + .ce(grp_fu_805_ce), + .dout(grp_fu_805_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U4( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_62_V_read_int_reg), + .din1(grp_fu_806_p1), + .ce(grp_fu_806_ce), + .dout(grp_fu_806_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U5( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_37_V_read_int_reg), + .din1(grp_fu_807_p1), + .ce(grp_fu_807_ce), + .dout(grp_fu_807_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U6( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_32_V_read_int_reg), + .din1(grp_fu_808_p1), + .ce(grp_fu_808_ce), + .dout(grp_fu_808_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U7( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_58_V_read_int_reg), + .din1(grp_fu_809_p1), + .ce(grp_fu_809_ce), + .dout(grp_fu_809_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U8( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_19_V_read_int_reg), + .din1(grp_fu_810_p1), + .ce(grp_fu_810_ce), + .dout(grp_fu_810_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U9( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_21_V_read_int_reg), + .din1(grp_fu_811_p1), + .ce(grp_fu_811_ce), + .dout(grp_fu_811_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U10( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_15_V_read_int_reg), + .din1(grp_fu_812_p1), + .ce(grp_fu_812_ce), + .dout(grp_fu_812_p2) +); + +myproject_mul_16s_13ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 13 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_13ns_26_2_0_U11( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_13_V_read_int_reg), + .din1(grp_fu_813_p1), + .ce(grp_fu_813_ce), + .dout(grp_fu_813_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U12( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_30_V_read_int_reg), + .din1(grp_fu_814_p1), + .ce(grp_fu_814_ce), + .dout(grp_fu_814_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U13( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_20_V_read_int_reg), + .din1(grp_fu_815_p1), + .ce(grp_fu_815_ce), + .dout(grp_fu_815_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U14( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_14_V_read_int_reg), + .din1(grp_fu_816_p1), + .ce(grp_fu_816_ce), + .dout(grp_fu_816_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U15( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_18_V_read_int_reg), + .din1(grp_fu_818_p1), + .ce(grp_fu_818_ce), + .dout(grp_fu_818_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U16( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_8_V_read_int_reg), + .din1(grp_fu_819_p1), + .ce(grp_fu_819_ce), + .dout(grp_fu_819_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U17( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_63_V_read_int_reg), + .din1(grp_fu_820_p1), + .ce(grp_fu_820_ce), + .dout(grp_fu_820_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U18( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_55_V_read_int_reg), + .din1(grp_fu_821_p1), + .ce(grp_fu_821_ce), + .dout(grp_fu_821_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U19( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_41_V_read_int_reg), + .din1(grp_fu_822_p1), + .ce(grp_fu_822_ce), + .dout(grp_fu_822_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U20( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_52_V_read_int_reg), + .din1(grp_fu_823_p1), + .ce(grp_fu_823_ce), + .dout(grp_fu_823_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U21( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_22_V_read_int_reg), + .din1(grp_fu_824_p1), + .ce(grp_fu_824_ce), + .dout(grp_fu_824_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U22( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_38_V_read_int_reg), + .din1(grp_fu_825_p1), + .ce(grp_fu_825_ce), + .dout(grp_fu_825_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U23( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_44_V_read_int_reg), + .din1(grp_fu_826_p1), + .ce(grp_fu_826_ce), + .dout(grp_fu_826_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U24( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_26_V_read_int_reg), + .din1(grp_fu_827_p1), + .ce(grp_fu_827_ce), + .dout(grp_fu_827_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U25( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_3_V_read_int_reg), + .din1(grp_fu_828_p1), + .ce(grp_fu_828_ce), + .dout(grp_fu_828_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U26( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_6_V_read_int_reg), + .din1(grp_fu_829_p1), + .ce(grp_fu_829_ce), + .dout(grp_fu_829_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U27( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_23_V_read_int_reg), + .din1(grp_fu_830_p1), + .ce(grp_fu_830_ce), + .dout(grp_fu_830_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U28( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_56_V_read_int_reg), + .din1(grp_fu_831_p1), + .ce(grp_fu_831_ce), + .dout(grp_fu_831_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U29( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_1_V_read_int_reg), + .din1(grp_fu_832_p1), + .ce(grp_fu_832_ce), + .dout(grp_fu_832_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U30( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_61_V_read_int_reg), + .din1(grp_fu_833_p1), + .ce(grp_fu_833_ce), + .dout(grp_fu_833_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U31( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_12_V_read_int_reg), + .din1(grp_fu_834_p1), + .ce(grp_fu_834_ce), + .dout(grp_fu_834_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U32( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_34_V_read_int_reg), + .din1(grp_fu_835_p1), + .ce(grp_fu_835_ce), + .dout(grp_fu_835_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U33( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_16_V_read_int_reg), + .din1(grp_fu_837_p1), + .ce(grp_fu_837_ce), + .dout(grp_fu_837_p2) +); + +myproject_mul_16s_13ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 13 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_13ns_26_2_0_U34( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_47_V_read_int_reg), + .din1(grp_fu_838_p1), + .ce(grp_fu_838_ce), + .dout(grp_fu_838_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U35( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_24_V_read_int_reg), + .din1(grp_fu_839_p1), + .ce(grp_fu_839_ce), + .dout(grp_fu_839_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U36( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_31_V_read_int_reg), + .din1(grp_fu_840_p1), + .ce(grp_fu_840_ce), + .dout(grp_fu_840_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U37( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_36_V_read_int_reg), + .din1(grp_fu_841_p1), + .ce(grp_fu_841_ce), + .dout(grp_fu_841_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U38( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_59_V_read_int_reg), + .din1(grp_fu_842_p1), + .ce(grp_fu_842_ce), + .dout(grp_fu_842_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U39( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_49_V_read_int_reg), + .din1(grp_fu_843_p1), + .ce(grp_fu_843_ce), + .dout(grp_fu_843_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U40( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_9_V_read_int_reg), + .din1(grp_fu_844_p1), + .ce(grp_fu_844_ce), + .dout(grp_fu_844_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U41( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_28_V_read_int_reg), + .din1(grp_fu_845_p1), + .ce(grp_fu_845_ce), + .dout(grp_fu_845_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U42( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_5_V_read_int_reg), + .din1(grp_fu_846_p1), + .ce(grp_fu_846_ce), + .dout(grp_fu_846_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U43( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_27_V_read_int_reg), + .din1(grp_fu_847_p1), + .ce(grp_fu_847_ce), + .dout(grp_fu_847_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U44( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_53_V_read_int_reg), + .din1(grp_fu_848_p1), + .ce(grp_fu_848_ce), + .dout(grp_fu_848_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U45( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_17_V_read_int_reg), + .din1(grp_fu_849_p1), + .ce(grp_fu_849_ce), + .dout(grp_fu_849_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U46( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_25_V_read_int_reg), + .din1(grp_fu_850_p1), + .ce(grp_fu_850_ce), + .dout(grp_fu_850_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U47( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_43_V_read_int_reg), + .din1(grp_fu_851_p1), + .ce(grp_fu_851_ce), + .dout(grp_fu_851_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U48( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_0_V_read_int_reg), + .din1(grp_fu_852_p1), + .ce(grp_fu_852_ce), + .dout(grp_fu_852_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U49( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_29_V_read_int_reg), + .din1(grp_fu_853_p1), + .ce(grp_fu_853_ce), + .dout(grp_fu_853_p2) +); + +myproject_mul_16s_13ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 13 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_13ns_26_2_0_U50( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_54_V_read_int_reg), + .din1(grp_fu_854_p1), + .ce(grp_fu_854_ce), + .dout(grp_fu_854_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U51( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_45_V_read_int_reg), + .din1(grp_fu_855_p1), + .ce(grp_fu_855_ce), + .dout(grp_fu_855_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U52( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_11_V_read_int_reg), + .din1(grp_fu_856_p1), + .ce(grp_fu_856_ce), + .dout(grp_fu_856_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U53( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_4_V_read_int_reg), + .din1(grp_fu_857_p1), + .ce(grp_fu_857_ce), + .dout(grp_fu_857_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U54( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_33_V_read_int_reg), + .din1(grp_fu_858_p1), + .ce(grp_fu_858_ce), + .dout(grp_fu_858_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U55( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_10_V_read_int_reg), + .din1(grp_fu_859_p1), + .ce(grp_fu_859_ce), + .dout(grp_fu_859_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U56( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_2_V_read_int_reg), + .din1(grp_fu_860_p1), + .ce(grp_fu_860_ce), + .dout(grp_fu_860_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U57( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_48_V_read_int_reg), + .din1(grp_fu_861_p1), + .ce(grp_fu_861_ce), + .dout(grp_fu_861_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U58( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_50_V_read_int_reg), + .din1(grp_fu_862_p1), + .ce(grp_fu_862_ce), + .dout(grp_fu_862_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U59( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_51_V_read_int_reg), + .din1(grp_fu_863_p1), + .ce(grp_fu_863_ce), + .dout(grp_fu_863_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U60( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_57_V_read_int_reg), + .din1(grp_fu_864_p1), + .ce(grp_fu_864_ce), + .dout(grp_fu_864_p2) +); + +myproject_mul_16s_12ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 12 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_12ns_26_2_0_U61( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_7_V_read_int_reg), + .din1(grp_fu_866_p1), + .ce(grp_fu_866_ce), + .dout(grp_fu_866_p2) +); + +myproject_mul_16s_13ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 13 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_13ns_26_2_0_U62( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_40_V_read_int_reg), + .din1(grp_fu_867_p1), + .ce(grp_fu_867_ce), + .dout(grp_fu_867_p2) +); + +always @ (posedge ap_clk) begin + ap_ce_reg <= ap_ce; +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce_reg)) begin + ap_return_0_int_reg <= add_ln703_fu_17921_p2; + ap_return_10_int_reg <= add_ln703_45_fu_17971_p2; + ap_return_11_int_reg <= add_ln703_46_fu_17976_p2; + ap_return_12_int_reg <= add_ln703_47_fu_17981_p2; + ap_return_13_int_reg <= add_ln703_48_fu_17986_p2; + ap_return_14_int_reg <= add_ln703_49_fu_17991_p2; + ap_return_15_int_reg <= add_ln703_50_fu_17996_p2; + ap_return_16_int_reg <= add_ln703_51_fu_18001_p2; + ap_return_17_int_reg <= add_ln703_52_fu_18006_p2; + ap_return_18_int_reg <= add_ln703_53_fu_18011_p2; + ap_return_19_int_reg <= add_ln703_54_fu_18016_p2; + ap_return_1_int_reg <= add_ln703_36_fu_17926_p2; + ap_return_20_int_reg <= add_ln703_55_fu_18021_p2; + ap_return_21_int_reg <= add_ln703_56_fu_18026_p2; + ap_return_22_int_reg <= add_ln703_57_fu_18031_p2; + ap_return_23_int_reg <= add_ln703_58_fu_18036_p2; + ap_return_24_int_reg <= add_ln703_59_fu_18041_p2; + ap_return_25_int_reg <= add_ln703_60_fu_18046_p2; + ap_return_26_int_reg <= add_ln703_61_fu_18051_p2; + ap_return_27_int_reg <= add_ln703_62_fu_18056_p2; + ap_return_28_int_reg <= add_ln703_63_fu_18061_p2; + ap_return_29_int_reg <= add_ln703_64_fu_18066_p2; + ap_return_2_int_reg <= add_ln703_37_fu_17931_p2; + ap_return_30_int_reg <= add_ln703_65_fu_18071_p2; + ap_return_31_int_reg <= add_ln703_66_fu_18076_p2; + ap_return_32_int_reg <= add_ln703_67_fu_18081_p2; + ap_return_33_int_reg <= add_ln703_68_fu_18086_p2; + ap_return_34_int_reg <= add_ln703_69_fu_18091_p2; + ap_return_35_int_reg <= add_ln703_70_fu_18096_p2; + ap_return_36_int_reg <= add_ln703_71_fu_18101_p2; + ap_return_37_int_reg <= add_ln703_72_fu_18106_p2; + ap_return_38_int_reg <= add_ln703_73_fu_18111_p2; + ap_return_39_int_reg <= add_ln703_74_fu_18116_p2; + ap_return_3_int_reg <= add_ln703_38_fu_17936_p2; + ap_return_40_int_reg <= add_ln703_75_fu_18121_p2; + ap_return_41_int_reg <= add_ln703_76_fu_18126_p2; + ap_return_42_int_reg <= add_ln703_77_fu_18131_p2; + ap_return_43_int_reg <= add_ln703_78_fu_18136_p2; + ap_return_44_int_reg <= add_ln703_79_fu_18141_p2; + ap_return_45_int_reg <= add_ln703_80_fu_18146_p2; + ap_return_46_int_reg <= add_ln703_81_fu_18151_p2; + ap_return_47_int_reg <= add_ln703_82_fu_18156_p2; + ap_return_48_int_reg <= add_ln703_83_fu_18161_p2; + ap_return_49_int_reg <= add_ln703_84_fu_18166_p2; + ap_return_4_int_reg <= add_ln703_39_fu_17941_p2; + ap_return_50_int_reg <= add_ln703_85_fu_18171_p2; + ap_return_51_int_reg <= add_ln703_86_fu_18176_p2; + ap_return_52_int_reg <= add_ln703_87_fu_18181_p2; + ap_return_53_int_reg <= add_ln703_88_fu_18186_p2; + ap_return_54_int_reg <= add_ln703_89_fu_18191_p2; + ap_return_55_int_reg <= add_ln703_90_fu_18196_p2; + ap_return_56_int_reg <= add_ln703_91_fu_18201_p2; + ap_return_57_int_reg <= add_ln703_92_fu_18206_p2; + ap_return_58_int_reg <= add_ln703_93_fu_18211_p2; + ap_return_59_int_reg <= add_ln703_94_fu_18216_p2; + ap_return_5_int_reg <= add_ln703_40_fu_17946_p2; + ap_return_60_int_reg <= add_ln703_95_fu_18221_p2; + ap_return_61_int_reg <= add_ln703_96_fu_18226_p2; + ap_return_62_int_reg <= add_ln703_97_fu_18231_p2; + ap_return_63_int_reg <= add_ln703_98_fu_18236_p2; + ap_return_6_int_reg <= add_ln703_41_fu_17951_p2; + ap_return_7_int_reg <= add_ln703_42_fu_17956_p2; + ap_return_8_int_reg <= add_ln703_43_fu_17961_p2; + ap_return_9_int_reg <= add_ln703_44_fu_17966_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce)) begin + data_0_V_read_int_reg <= data_0_V_read; + data_10_V_read_int_reg <= data_10_V_read; + data_11_V_read_int_reg <= data_11_V_read; + data_12_V_read_int_reg <= data_12_V_read; + data_13_V_read_int_reg <= data_13_V_read; + data_14_V_read_int_reg <= data_14_V_read; + data_15_V_read_int_reg <= data_15_V_read; + data_16_V_read_int_reg <= data_16_V_read; + data_17_V_read_int_reg <= data_17_V_read; + data_18_V_read_int_reg <= data_18_V_read; + data_19_V_read_int_reg <= data_19_V_read; + data_1_V_read_int_reg <= data_1_V_read; + data_20_V_read_int_reg <= data_20_V_read; + data_21_V_read_int_reg <= data_21_V_read; + data_22_V_read_int_reg <= data_22_V_read; + data_23_V_read_int_reg <= data_23_V_read; + data_24_V_read_int_reg <= data_24_V_read; + data_25_V_read_int_reg <= data_25_V_read; + data_26_V_read_int_reg <= data_26_V_read; + data_27_V_read_int_reg <= data_27_V_read; + data_28_V_read_int_reg <= data_28_V_read; + data_29_V_read_int_reg <= data_29_V_read; + data_2_V_read_int_reg <= data_2_V_read; + data_30_V_read_int_reg <= data_30_V_read; + data_31_V_read_int_reg <= data_31_V_read; + data_32_V_read_int_reg <= data_32_V_read; + data_33_V_read_int_reg <= data_33_V_read; + data_34_V_read_int_reg <= data_34_V_read; + data_35_V_read_int_reg <= data_35_V_read; + data_36_V_read_int_reg <= data_36_V_read; + data_37_V_read_int_reg <= data_37_V_read; + data_38_V_read_int_reg <= data_38_V_read; + data_39_V_read_int_reg <= data_39_V_read; + data_3_V_read_int_reg <= data_3_V_read; + data_40_V_read_int_reg <= data_40_V_read; + data_41_V_read_int_reg <= data_41_V_read; + data_42_V_read_int_reg <= data_42_V_read; + data_43_V_read_int_reg <= data_43_V_read; + data_44_V_read_int_reg <= data_44_V_read; + data_45_V_read_int_reg <= data_45_V_read; + data_46_V_read_int_reg <= data_46_V_read; + data_47_V_read_int_reg <= data_47_V_read; + data_48_V_read_int_reg <= data_48_V_read; + data_49_V_read_int_reg <= data_49_V_read; + data_4_V_read_int_reg <= data_4_V_read; + data_50_V_read_int_reg <= data_50_V_read; + data_51_V_read_int_reg <= data_51_V_read; + data_52_V_read_int_reg <= data_52_V_read; + data_53_V_read_int_reg <= data_53_V_read; + data_54_V_read_int_reg <= data_54_V_read; + data_55_V_read_int_reg <= data_55_V_read; + data_56_V_read_int_reg <= data_56_V_read; + data_57_V_read_int_reg <= data_57_V_read; + data_58_V_read_int_reg <= data_58_V_read; + data_59_V_read_int_reg <= data_59_V_read; + data_5_V_read_int_reg <= data_5_V_read; + data_60_V_read_int_reg <= data_60_V_read; + data_61_V_read_int_reg <= data_61_V_read; + data_62_V_read_int_reg <= data_62_V_read; + data_63_V_read_int_reg <= data_63_V_read; + data_6_V_read_int_reg <= data_6_V_read; + data_7_V_read_int_reg <= data_7_V_read; + data_8_V_read_int_reg <= data_8_V_read; + data_9_V_read_int_reg <= data_9_V_read; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + data_39_V_read_2_reg_18637 <= data_39_V_read_int_reg; + data_42_V_read_2_reg_18631 <= data_42_V_read_int_reg; + data_46_V_read_2_reg_18625 <= data_46_V_read_int_reg; + trunc_ln708_31_reg_18953 <= {{grp_fu_832_p2[25:10]}}; + trunc_ln708_32_reg_18958 <= {{grp_fu_860_p2[25:10]}}; + trunc_ln708_33_reg_18968 <= {{grp_fu_857_p2[25:10]}}; + trunc_ln708_34_reg_18973 <= {{grp_fu_846_p2[25:10]}}; + trunc_ln708_35_reg_18978 <= {{grp_fu_829_p2[25:10]}}; + trunc_ln708_36_reg_18983 <= {{grp_fu_866_p2[25:10]}}; + trunc_ln708_37_reg_18988 <= {{grp_fu_819_p2[25:10]}}; + trunc_ln708_38_reg_18993 <= {{grp_fu_844_p2[25:10]}}; + trunc_ln708_39_reg_18998 <= {{grp_fu_859_p2[25:10]}}; + trunc_ln708_40_reg_19003 <= {{grp_fu_856_p2[25:10]}}; + trunc_ln708_41_reg_19008 <= {{grp_fu_834_p2[25:10]}}; + trunc_ln708_42_reg_19013 <= {{grp_fu_813_p2[25:10]}}; + trunc_ln708_43_reg_19018 <= {{grp_fu_816_p2[25:10]}}; + trunc_ln708_44_reg_19023 <= {{grp_fu_812_p2[25:10]}}; + trunc_ln708_45_reg_19028 <= {{grp_fu_837_p2[25:10]}}; + trunc_ln708_46_reg_19033 <= {{grp_fu_849_p2[25:10]}}; + trunc_ln708_47_reg_19038 <= {{grp_fu_818_p2[25:10]}}; + trunc_ln708_48_reg_19043 <= {{grp_fu_810_p2[25:10]}}; + trunc_ln708_49_reg_19048 <= {{grp_fu_815_p2[25:10]}}; + trunc_ln708_50_reg_19053 <= {{grp_fu_811_p2[25:10]}}; + trunc_ln708_51_reg_19058 <= {{grp_fu_824_p2[25:10]}}; + trunc_ln708_52_reg_19063 <= {{grp_fu_830_p2[25:10]}}; + trunc_ln708_53_reg_19068 <= {{grp_fu_839_p2[25:10]}}; + trunc_ln708_54_reg_19073 <= {{grp_fu_850_p2[25:10]}}; + trunc_ln708_55_reg_19078 <= {{grp_fu_827_p2[25:10]}}; + trunc_ln708_56_reg_19083 <= {{grp_fu_847_p2[25:10]}}; + trunc_ln708_57_reg_19088 <= {{grp_fu_845_p2[25:10]}}; + trunc_ln708_58_reg_19093 <= {{grp_fu_853_p2[25:10]}}; + trunc_ln708_59_reg_19098 <= {{grp_fu_814_p2[25:10]}}; + trunc_ln708_60_reg_19103 <= {{grp_fu_840_p2[25:10]}}; + trunc_ln708_61_reg_19108 <= {{grp_fu_808_p2[25:10]}}; + trunc_ln708_62_reg_19113 <= {{grp_fu_858_p2[25:10]}}; + trunc_ln708_63_reg_19118 <= {{grp_fu_835_p2[25:10]}}; + trunc_ln708_64_reg_19123 <= {{grp_fu_804_p2[25:10]}}; + trunc_ln708_65_reg_19128 <= {{grp_fu_841_p2[25:10]}}; + trunc_ln708_66_reg_19133 <= {{grp_fu_807_p2[25:10]}}; + trunc_ln708_67_reg_19138 <= {{grp_fu_825_p2[25:10]}}; + trunc_ln708_68_reg_19143 <= {{add_ln1118_fu_17625_p2[25:10]}}; + trunc_ln708_69_reg_19148 <= {{grp_fu_867_p2[25:10]}}; + trunc_ln708_70_reg_19153 <= {{grp_fu_822_p2[25:10]}}; + trunc_ln708_71_reg_19158 <= {{add_ln1118_1_fu_17671_p2[25:10]}}; + trunc_ln708_72_reg_19163 <= {{grp_fu_851_p2[25:10]}}; + trunc_ln708_73_reg_19168 <= {{grp_fu_826_p2[25:10]}}; + trunc_ln708_74_reg_19173 <= {{grp_fu_855_p2[25:10]}}; + trunc_ln708_75_reg_19178 <= {{add_ln1118_2_fu_17735_p2[25:10]}}; + trunc_ln708_76_reg_19183 <= {{grp_fu_838_p2[25:10]}}; + trunc_ln708_77_reg_19188 <= {{grp_fu_861_p2[25:10]}}; + trunc_ln708_78_reg_19193 <= {{grp_fu_843_p2[25:10]}}; + trunc_ln708_79_reg_19198 <= {{grp_fu_862_p2[25:10]}}; + trunc_ln708_80_reg_19203 <= {{grp_fu_863_p2[25:10]}}; + trunc_ln708_81_reg_19208 <= {{grp_fu_823_p2[25:10]}}; + trunc_ln708_82_reg_19213 <= {{grp_fu_848_p2[25:10]}}; + trunc_ln708_83_reg_19218 <= {{grp_fu_854_p2[25:10]}}; + trunc_ln708_84_reg_19223 <= {{grp_fu_821_p2[25:10]}}; + trunc_ln708_85_reg_19228 <= {{grp_fu_831_p2[25:10]}}; + trunc_ln708_86_reg_19233 <= {{grp_fu_864_p2[25:10]}}; + trunc_ln708_87_reg_19238 <= {{grp_fu_809_p2[25:10]}}; + trunc_ln708_88_reg_19243 <= {{grp_fu_842_p2[25:10]}}; + trunc_ln708_89_reg_19248 <= {{grp_fu_805_p2[25:10]}}; + trunc_ln708_90_reg_19253 <= {{grp_fu_833_p2[25:10]}}; + trunc_ln708_91_reg_19258 <= {{grp_fu_806_p2[25:10]}}; + trunc_ln708_92_reg_19263 <= {{grp_fu_820_p2[25:10]}}; + trunc_ln708_s_reg_18963 <= {{grp_fu_828_p2[25:10]}}; + trunc_ln_reg_18948 <= {{grp_fu_852_p2[25:10]}}; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_0 = ap_return_0_int_reg; + end else begin + ap_return_0 = add_ln703_fu_17921_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_1 = ap_return_1_int_reg; + end else begin + ap_return_1 = add_ln703_36_fu_17926_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_10 = ap_return_10_int_reg; + end else begin + ap_return_10 = add_ln703_45_fu_17971_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_11 = ap_return_11_int_reg; + end else begin + ap_return_11 = add_ln703_46_fu_17976_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_12 = ap_return_12_int_reg; + end else begin + ap_return_12 = add_ln703_47_fu_17981_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_13 = ap_return_13_int_reg; + end else begin + ap_return_13 = add_ln703_48_fu_17986_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_14 = ap_return_14_int_reg; + end else begin + ap_return_14 = add_ln703_49_fu_17991_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_15 = ap_return_15_int_reg; + end else begin + ap_return_15 = add_ln703_50_fu_17996_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_16 = ap_return_16_int_reg; + end else begin + ap_return_16 = add_ln703_51_fu_18001_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_17 = ap_return_17_int_reg; + end else begin + ap_return_17 = add_ln703_52_fu_18006_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_18 = ap_return_18_int_reg; + end else begin + ap_return_18 = add_ln703_53_fu_18011_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_19 = ap_return_19_int_reg; + end else begin + ap_return_19 = add_ln703_54_fu_18016_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_2 = ap_return_2_int_reg; + end else begin + ap_return_2 = add_ln703_37_fu_17931_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_20 = ap_return_20_int_reg; + end else begin + ap_return_20 = add_ln703_55_fu_18021_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_21 = ap_return_21_int_reg; + end else begin + ap_return_21 = add_ln703_56_fu_18026_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_22 = ap_return_22_int_reg; + end else begin + ap_return_22 = add_ln703_57_fu_18031_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_23 = ap_return_23_int_reg; + end else begin + ap_return_23 = add_ln703_58_fu_18036_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_24 = ap_return_24_int_reg; + end else begin + ap_return_24 = add_ln703_59_fu_18041_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_25 = ap_return_25_int_reg; + end else begin + ap_return_25 = add_ln703_60_fu_18046_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_26 = ap_return_26_int_reg; + end else begin + ap_return_26 = add_ln703_61_fu_18051_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_27 = ap_return_27_int_reg; + end else begin + ap_return_27 = add_ln703_62_fu_18056_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_28 = ap_return_28_int_reg; + end else begin + ap_return_28 = add_ln703_63_fu_18061_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_29 = ap_return_29_int_reg; + end else begin + ap_return_29 = add_ln703_64_fu_18066_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_3 = ap_return_3_int_reg; + end else begin + ap_return_3 = add_ln703_38_fu_17936_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_30 = ap_return_30_int_reg; + end else begin + ap_return_30 = add_ln703_65_fu_18071_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_31 = ap_return_31_int_reg; + end else begin + ap_return_31 = add_ln703_66_fu_18076_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_32 = ap_return_32_int_reg; + end else begin + ap_return_32 = add_ln703_67_fu_18081_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_33 = ap_return_33_int_reg; + end else begin + ap_return_33 = add_ln703_68_fu_18086_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_34 = ap_return_34_int_reg; + end else begin + ap_return_34 = add_ln703_69_fu_18091_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_35 = ap_return_35_int_reg; + end else begin + ap_return_35 = add_ln703_70_fu_18096_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_36 = ap_return_36_int_reg; + end else begin + ap_return_36 = add_ln703_71_fu_18101_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_37 = ap_return_37_int_reg; + end else begin + ap_return_37 = add_ln703_72_fu_18106_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_38 = ap_return_38_int_reg; + end else begin + ap_return_38 = add_ln703_73_fu_18111_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_39 = ap_return_39_int_reg; + end else begin + ap_return_39 = add_ln703_74_fu_18116_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_4 = ap_return_4_int_reg; + end else begin + ap_return_4 = add_ln703_39_fu_17941_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_40 = ap_return_40_int_reg; + end else begin + ap_return_40 = add_ln703_75_fu_18121_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_41 = ap_return_41_int_reg; + end else begin + ap_return_41 = add_ln703_76_fu_18126_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_42 = ap_return_42_int_reg; + end else begin + ap_return_42 = add_ln703_77_fu_18131_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_43 = ap_return_43_int_reg; + end else begin + ap_return_43 = add_ln703_78_fu_18136_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_44 = ap_return_44_int_reg; + end else begin + ap_return_44 = add_ln703_79_fu_18141_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_45 = ap_return_45_int_reg; + end else begin + ap_return_45 = add_ln703_80_fu_18146_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_46 = ap_return_46_int_reg; + end else begin + ap_return_46 = add_ln703_81_fu_18151_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_47 = ap_return_47_int_reg; + end else begin + ap_return_47 = add_ln703_82_fu_18156_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_48 = ap_return_48_int_reg; + end else begin + ap_return_48 = add_ln703_83_fu_18161_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_49 = ap_return_49_int_reg; + end else begin + ap_return_49 = add_ln703_84_fu_18166_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_5 = ap_return_5_int_reg; + end else begin + ap_return_5 = add_ln703_40_fu_17946_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_50 = ap_return_50_int_reg; + end else begin + ap_return_50 = add_ln703_85_fu_18171_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_51 = ap_return_51_int_reg; + end else begin + ap_return_51 = add_ln703_86_fu_18176_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_52 = ap_return_52_int_reg; + end else begin + ap_return_52 = add_ln703_87_fu_18181_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_53 = ap_return_53_int_reg; + end else begin + ap_return_53 = add_ln703_88_fu_18186_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_54 = ap_return_54_int_reg; + end else begin + ap_return_54 = add_ln703_89_fu_18191_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_55 = ap_return_55_int_reg; + end else begin + ap_return_55 = add_ln703_90_fu_18196_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_56 = ap_return_56_int_reg; + end else begin + ap_return_56 = add_ln703_91_fu_18201_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_57 = ap_return_57_int_reg; + end else begin + ap_return_57 = add_ln703_92_fu_18206_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_58 = ap_return_58_int_reg; + end else begin + ap_return_58 = add_ln703_93_fu_18211_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_59 = ap_return_59_int_reg; + end else begin + ap_return_59 = add_ln703_94_fu_18216_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_6 = ap_return_6_int_reg; + end else begin + ap_return_6 = add_ln703_41_fu_17951_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_60 = ap_return_60_int_reg; + end else begin + ap_return_60 = add_ln703_95_fu_18221_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_61 = ap_return_61_int_reg; + end else begin + ap_return_61 = add_ln703_96_fu_18226_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_62 = ap_return_62_int_reg; + end else begin + ap_return_62 = add_ln703_97_fu_18231_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_63 = ap_return_63_int_reg; + end else begin + ap_return_63 = add_ln703_98_fu_18236_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_7 = ap_return_7_int_reg; + end else begin + ap_return_7 = add_ln703_42_fu_17956_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_8 = ap_return_8_int_reg; + end else begin + ap_return_8 = add_ln703_43_fu_17961_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_9 = ap_return_9_int_reg; + end else begin + ap_return_9 = add_ln703_44_fu_17966_p2; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_804_ce = 1'b1; + end else begin + grp_fu_804_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_805_ce = 1'b1; + end else begin + grp_fu_805_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_806_ce = 1'b1; + end else begin + grp_fu_806_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_807_ce = 1'b1; + end else begin + grp_fu_807_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_808_ce = 1'b1; + end else begin + grp_fu_808_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_809_ce = 1'b1; + end else begin + grp_fu_809_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_810_ce = 1'b1; + end else begin + grp_fu_810_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_811_ce = 1'b1; + end else begin + grp_fu_811_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_812_ce = 1'b1; + end else begin + grp_fu_812_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_813_ce = 1'b1; + end else begin + grp_fu_813_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_814_ce = 1'b1; + end else begin + grp_fu_814_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_815_ce = 1'b1; + end else begin + grp_fu_815_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_816_ce = 1'b1; + end else begin + grp_fu_816_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_818_ce = 1'b1; + end else begin + grp_fu_818_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_819_ce = 1'b1; + end else begin + grp_fu_819_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_820_ce = 1'b1; + end else begin + grp_fu_820_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_821_ce = 1'b1; + end else begin + grp_fu_821_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_822_ce = 1'b1; + end else begin + grp_fu_822_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_823_ce = 1'b1; + end else begin + grp_fu_823_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_824_ce = 1'b1; + end else begin + grp_fu_824_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_825_ce = 1'b1; + end else begin + grp_fu_825_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_826_ce = 1'b1; + end else begin + grp_fu_826_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_827_ce = 1'b1; + end else begin + grp_fu_827_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_828_ce = 1'b1; + end else begin + grp_fu_828_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_829_ce = 1'b1; + end else begin + grp_fu_829_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_830_ce = 1'b1; + end else begin + grp_fu_830_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_831_ce = 1'b1; + end else begin + grp_fu_831_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_832_ce = 1'b1; + end else begin + grp_fu_832_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_833_ce = 1'b1; + end else begin + grp_fu_833_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_834_ce = 1'b1; + end else begin + grp_fu_834_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_835_ce = 1'b1; + end else begin + grp_fu_835_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_837_ce = 1'b1; + end else begin + grp_fu_837_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_838_ce = 1'b1; + end else begin + grp_fu_838_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_839_ce = 1'b1; + end else begin + grp_fu_839_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_840_ce = 1'b1; + end else begin + grp_fu_840_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_841_ce = 1'b1; + end else begin + grp_fu_841_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_842_ce = 1'b1; + end else begin + grp_fu_842_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_843_ce = 1'b1; + end else begin + grp_fu_843_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_844_ce = 1'b1; + end else begin + grp_fu_844_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_845_ce = 1'b1; + end else begin + grp_fu_845_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_846_ce = 1'b1; + end else begin + grp_fu_846_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_847_ce = 1'b1; + end else begin + grp_fu_847_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_848_ce = 1'b1; + end else begin + grp_fu_848_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_849_ce = 1'b1; + end else begin + grp_fu_849_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_850_ce = 1'b1; + end else begin + grp_fu_850_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_851_ce = 1'b1; + end else begin + grp_fu_851_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_852_ce = 1'b1; + end else begin + grp_fu_852_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_853_ce = 1'b1; + end else begin + grp_fu_853_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_854_ce = 1'b1; + end else begin + grp_fu_854_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_855_ce = 1'b1; + end else begin + grp_fu_855_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_856_ce = 1'b1; + end else begin + grp_fu_856_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_857_ce = 1'b1; + end else begin + grp_fu_857_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_858_ce = 1'b1; + end else begin + grp_fu_858_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_859_ce = 1'b1; + end else begin + grp_fu_859_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_860_ce = 1'b1; + end else begin + grp_fu_860_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_861_ce = 1'b1; + end else begin + grp_fu_861_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_862_ce = 1'b1; + end else begin + grp_fu_862_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_863_ce = 1'b1; + end else begin + grp_fu_863_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_864_ce = 1'b1; + end else begin + grp_fu_864_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_866_ce = 1'b1; + end else begin + grp_fu_866_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_ce_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + grp_fu_867_ce = 1'b1; + end else begin + grp_fu_867_ce = 1'b0; + end +end + +assign add_ln1118_1_fu_17671_p2 = ((sext_ln1118_76_fu_17661_p1) + (shl_ln1118_6_fu_17664_p3)); + +assign add_ln1118_2_fu_17735_p2 = ((shl_ln1118_7_fu_17717_p3) + (sext_ln1118_80_fu_17731_p1)); + +assign add_ln1118_fu_17625_p2 = ((shl_ln_fu_17607_p3) + (sext_ln1118_73_fu_17621_p1)); + +assign add_ln703_36_fu_17926_p2 = (trunc_ln708_31_reg_18953 + 16'd2428); + +assign add_ln703_37_fu_17931_p2 = ((trunc_ln708_32_reg_18958) + (16'd63557)); + +assign add_ln703_38_fu_17936_p2 = (trunc_ln708_s_reg_18963 + 16'd2668); + +assign add_ln703_39_fu_17941_p2 = (trunc_ln708_33_reg_18968 + 16'd770); + +assign add_ln703_40_fu_17946_p2 = ((trunc_ln708_34_reg_18973) + (16'd65261)); + +assign add_ln703_41_fu_17951_p2 = (trunc_ln708_35_reg_18978 + 16'd1774); + +assign add_ln703_42_fu_17956_p2 = ((trunc_ln708_36_reg_18983) + (16'd61620)); + +assign add_ln703_43_fu_17961_p2 = (trunc_ln708_37_reg_18988 + 16'd1134); + +assign add_ln703_44_fu_17966_p2 = (trunc_ln708_38_reg_18993 + 16'd3344); + +assign add_ln703_45_fu_17971_p2 = (trunc_ln708_39_reg_18998 + 16'd476); + +assign add_ln703_46_fu_17976_p2 = ((trunc_ln708_40_reg_19003) + (16'd65055)); + +assign add_ln703_47_fu_17981_p2 = ((trunc_ln708_41_reg_19008) + (16'd63350)); + +assign add_ln703_48_fu_17986_p2 = (trunc_ln708_42_reg_19013 + 16'd6336); + +assign add_ln703_49_fu_17991_p2 = (trunc_ln708_43_reg_19018 + 16'd779); + +assign add_ln703_50_fu_17996_p2 = ((trunc_ln708_44_reg_19023) + (16'd65093)); + +assign add_ln703_51_fu_18001_p2 = ((trunc_ln708_45_reg_19028) + (16'd64452)); + +assign add_ln703_52_fu_18006_p2 = (trunc_ln708_46_reg_19033 + 16'd150); + +assign add_ln703_53_fu_18011_p2 = ((trunc_ln708_47_reg_19038) + (16'd64356)); + +assign add_ln703_54_fu_18016_p2 = ((trunc_ln708_48_reg_19043) + (16'd61833)); + +assign add_ln703_55_fu_18021_p2 = ((trunc_ln708_49_reg_19048) + (16'd62693)); + +assign add_ln703_56_fu_18026_p2 = ((trunc_ln708_50_reg_19053) + (16'd65182)); + +assign add_ln703_57_fu_18031_p2 = ((trunc_ln708_51_reg_19058) + (16'd65467)); + +assign add_ln703_58_fu_18036_p2 = ((trunc_ln708_52_reg_19063) + (16'd65273)); + +assign add_ln703_59_fu_18041_p2 = ((trunc_ln708_53_reg_19068) + (16'd64093)); + +assign add_ln703_60_fu_18046_p2 = (trunc_ln708_54_reg_19073 + 16'd639); + +assign add_ln703_61_fu_18051_p2 = ((trunc_ln708_55_reg_19078) + (16'd61811)); + +assign add_ln703_62_fu_18056_p2 = (trunc_ln708_56_reg_19083 + 16'd2997); + +assign add_ln703_63_fu_18061_p2 = ((trunc_ln708_57_reg_19088) + (16'd65397)); + +assign add_ln703_64_fu_18066_p2 = ((trunc_ln708_58_reg_19093) + (16'd62604)); + +assign add_ln703_65_fu_18071_p2 = ((trunc_ln708_59_reg_19098) + (16'd60961)); + +assign add_ln703_66_fu_18076_p2 = (trunc_ln708_60_reg_19103 + 16'd3539); + +assign add_ln703_67_fu_18081_p2 = ((trunc_ln708_61_reg_19108) + (16'd64305)); + +assign add_ln703_68_fu_18086_p2 = ((trunc_ln708_62_reg_19113) + (16'd64971)); + +assign add_ln703_69_fu_18091_p2 = (trunc_ln708_63_reg_19118 + 16'd427); + +assign add_ln703_70_fu_18096_p2 = (trunc_ln708_64_reg_19123 + 16'd942); + +assign add_ln703_71_fu_18101_p2 = ((trunc_ln708_65_reg_19128) + (16'd64448)); + +assign add_ln703_72_fu_18106_p2 = ((trunc_ln708_66_reg_19133) + (16'd61149)); + +assign add_ln703_73_fu_18111_p2 = ((trunc_ln708_67_reg_19138) + (16'd63555)); + +assign add_ln703_74_fu_18116_p2 = ((trunc_ln708_68_reg_19143) + (16'd64965)); + +assign add_ln703_75_fu_18121_p2 = ((trunc_ln708_69_reg_19148) + (16'd65184)); + +assign add_ln703_76_fu_18126_p2 = ((trunc_ln708_70_reg_19153) + (16'd65085)); + +assign add_ln703_77_fu_18131_p2 = ((trunc_ln708_71_reg_19158) + (16'd63019)); + +assign add_ln703_78_fu_18136_p2 = (trunc_ln708_72_reg_19163 + 16'd436); + +assign add_ln703_79_fu_18141_p2 = ((trunc_ln708_73_reg_19168) + (16'd62012)); + +assign add_ln703_80_fu_18146_p2 = (trunc_ln708_74_reg_19173 + 16'd946); + +assign add_ln703_81_fu_18151_p2 = ((trunc_ln708_75_reg_19178) + (16'd65281)); + +assign add_ln703_82_fu_18156_p2 = (trunc_ln708_76_reg_19183 + 16'd473); + +assign add_ln703_83_fu_18161_p2 = ((trunc_ln708_77_reg_19188) + (16'd64458)); + +assign add_ln703_84_fu_18166_p2 = ((trunc_ln708_78_reg_19193) + (16'd65219)); + +assign add_ln703_85_fu_18171_p2 = (trunc_ln708_79_reg_19198 + 16'd1658); + +assign add_ln703_86_fu_18176_p2 = (trunc_ln708_80_reg_19203 + 16'd2181); + +assign add_ln703_87_fu_18181_p2 = (trunc_ln708_81_reg_19208 + 16'd1895); + +assign add_ln703_88_fu_18186_p2 = (trunc_ln708_82_reg_19213 + 16'd792); + +assign add_ln703_89_fu_18191_p2 = ((trunc_ln708_83_reg_19218) + (16'd62636)); + +assign add_ln703_90_fu_18196_p2 = (trunc_ln708_84_reg_19223 + 16'd1428); + +assign add_ln703_91_fu_18201_p2 = ((trunc_ln708_85_reg_19228) + (16'd64938)); + +assign add_ln703_92_fu_18206_p2 = (trunc_ln708_86_reg_19233 + 16'd931); + +assign add_ln703_93_fu_18211_p2 = ((trunc_ln708_87_reg_19238) + (16'd63398)); + +assign add_ln703_94_fu_18216_p2 = (trunc_ln708_88_reg_19243 + 16'd1118); + +assign add_ln703_95_fu_18221_p2 = (trunc_ln708_89_reg_19248 + 16'd139); + +assign add_ln703_96_fu_18226_p2 = (trunc_ln708_90_reg_19253 + 16'd1493); + +assign add_ln703_97_fu_18231_p2 = (trunc_ln708_91_reg_19258 + 16'd396); + +assign add_ln703_98_fu_18236_p2 = ((trunc_ln708_92_reg_19263) + (16'd61920)); + +assign add_ln703_fu_17921_p2 = ((trunc_ln_reg_18948) + (16'd64219)); + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign grp_fu_804_p1 = 12'd1206; + +assign grp_fu_805_p1 = 12'd1155; + +assign grp_fu_806_p1 = 12'd1317; + +assign grp_fu_807_p1 = 12'd1776; + +assign grp_fu_808_p1 = 11'd753; + +assign grp_fu_809_p1 = 11'd689; + +assign grp_fu_810_p1 = 12'd1209; + +assign grp_fu_811_p1 = 11'd880; + +assign grp_fu_812_p1 = 12'd1483; + +assign grp_fu_813_p1 = 13'd2953; + +assign grp_fu_814_p1 = 12'd1379; + +assign grp_fu_815_p1 = 12'd1208; + +assign grp_fu_816_p1 = 12'd1089; + +assign grp_fu_818_p1 = 12'd1827; + +assign grp_fu_819_p1 = 11'd811; + +assign grp_fu_820_p1 = 12'd1718; + +assign grp_fu_821_p1 = 12'd1103; + +assign grp_fu_822_p1 = 12'd1465; + +assign grp_fu_823_p1 = 12'd1094; + +assign grp_fu_824_p1 = 12'd1816; + +assign grp_fu_825_p1 = 11'd850; + +assign grp_fu_826_p1 = 12'd1241; + +assign grp_fu_827_p1 = 12'd1315; + +assign grp_fu_828_p1 = 11'd929; + +assign grp_fu_829_p1 = 11'd931; + +assign grp_fu_830_p1 = 12'd1361; + +assign grp_fu_831_p1 = 11'd793; + +assign grp_fu_832_p1 = 11'd999; + +assign grp_fu_833_p1 = 12'd1589; + +assign grp_fu_834_p1 = 11'd667; + +assign grp_fu_835_p1 = 12'd1731; + +assign grp_fu_837_p1 = 12'd1192; + +assign grp_fu_838_p1 = 13'd2114; + +assign grp_fu_839_p1 = 11'd832; + +assign grp_fu_840_p1 = 12'd1254; + +assign grp_fu_841_p1 = 11'd998; + +assign grp_fu_842_p1 = 12'd1583; + +assign grp_fu_843_p1 = 11'd947; + +assign grp_fu_844_p1 = 11'd882; + +assign grp_fu_845_p1 = 11'd936; + +assign grp_fu_846_p1 = 12'd1168; + +assign grp_fu_847_p1 = 12'd1604; + +assign grp_fu_848_p1 = 11'd991; + +assign grp_fu_849_p1 = 12'd1117; + +assign grp_fu_850_p1 = 11'd817; + +assign grp_fu_851_p1 = 12'd1116; + +assign grp_fu_852_p1 = 12'd1611; + +assign grp_fu_853_p1 = 11'd773; + +assign grp_fu_854_p1 = 13'd2327; + +assign grp_fu_855_p1 = 12'd1031; + +assign grp_fu_856_p1 = 11'd868; + +assign grp_fu_857_p1 = 12'd1751; + +assign grp_fu_858_p1 = 11'd669; + +assign grp_fu_859_p1 = 12'd1054; + +assign grp_fu_860_p1 = 12'd1055; + +assign grp_fu_861_p1 = 12'd1256; + +assign grp_fu_862_p1 = 12'd1713; + +assign grp_fu_863_p1 = 12'd1267; + +assign grp_fu_864_p1 = 11'd901; + +assign grp_fu_866_p1 = 12'd1881; + +assign grp_fu_867_p1 = 13'd2145; + +assign sext_ln1118_73_fu_17621_p1 = (shl_ln1118_5_fu_17614_p3); + +assign sext_ln1118_76_fu_17661_p1 = data_42_V_read_2_reg_18631; + +assign sext_ln1118_80_fu_17731_p1 = (shl_ln1118_8_fu_17724_p3); + +assign shl_ln1118_5_fu_17614_p3 = {{data_39_V_read_2_reg_18637}, {7'd0}}; + +assign shl_ln1118_6_fu_17664_p3 = {{data_42_V_read_2_reg_18631}, {10'd0}}; + +assign shl_ln1118_7_fu_17717_p3 = {{data_46_V_read_2_reg_18625}, {10'd0}}; + +assign shl_ln1118_8_fu_17724_p3 = {{data_46_V_read_2_reg_18625}, {6'd0}}; + +assign shl_ln_fu_17607_p3 = {{data_39_V_read_2_reg_18637}, {10'd0}}; + +endmodule //normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1 +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2 ( + ap_clk, + ap_rst, + data_0_V_read, + data_1_V_read, + data_2_V_read, + data_3_V_read, + data_4_V_read, + data_5_V_read, + data_6_V_read, + data_7_V_read, + data_8_V_read, + data_9_V_read, + data_10_V_read, + data_11_V_read, + data_12_V_read, + data_13_V_read, + data_14_V_read, + data_15_V_read, + data_16_V_read, + data_17_V_read, + data_18_V_read, + data_19_V_read, + data_20_V_read, + data_21_V_read, + data_22_V_read, + data_23_V_read, + data_24_V_read, + data_25_V_read, + data_26_V_read, + data_27_V_read, + data_28_V_read, + data_29_V_read, + data_30_V_read, + data_31_V_read, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3, + ap_return_4, + ap_return_5, + ap_return_6, + ap_return_7, + ap_return_8, + ap_return_9, + ap_return_10, + ap_return_11, + ap_return_12, + ap_return_13, + ap_return_14, + ap_return_15, + ap_return_16, + ap_return_17, + ap_return_18, + ap_return_19, + ap_return_20, + ap_return_21, + ap_return_22, + ap_return_23, + ap_return_24, + ap_return_25, + ap_return_26, + ap_return_27, + ap_return_28, + ap_return_29, + ap_return_30, + ap_return_31, + ap_ce +); + + +input ap_clk; +input ap_rst; +input [15:0] data_0_V_read; +input [15:0] data_1_V_read; +input [15:0] data_2_V_read; +input [15:0] data_3_V_read; +input [15:0] data_4_V_read; +input [15:0] data_5_V_read; +input [15:0] data_6_V_read; +input [15:0] data_7_V_read; +input [15:0] data_8_V_read; +input [15:0] data_9_V_read; +input [15:0] data_10_V_read; +input [15:0] data_11_V_read; +input [15:0] data_12_V_read; +input [15:0] data_13_V_read; +input [15:0] data_14_V_read; +input [15:0] data_15_V_read; +input [15:0] data_16_V_read; +input [15:0] data_17_V_read; +input [15:0] data_18_V_read; +input [15:0] data_19_V_read; +input [15:0] data_20_V_read; +input [15:0] data_21_V_read; +input [15:0] data_22_V_read; +input [15:0] data_23_V_read; +input [15:0] data_24_V_read; +input [15:0] data_25_V_read; +input [15:0] data_26_V_read; +input [15:0] data_27_V_read; +input [15:0] data_28_V_read; +input [15:0] data_29_V_read; +input [15:0] data_30_V_read; +input [15:0] data_31_V_read; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; +output [15:0] ap_return_4; +output [15:0] ap_return_5; +output [15:0] ap_return_6; +output [15:0] ap_return_7; +output [15:0] ap_return_8; +output [15:0] ap_return_9; +output [15:0] ap_return_10; +output [15:0] ap_return_11; +output [15:0] ap_return_12; +output [15:0] ap_return_13; +output [15:0] ap_return_14; +output [15:0] ap_return_15; +output [15:0] ap_return_16; +output [15:0] ap_return_17; +output [15:0] ap_return_18; +output [15:0] ap_return_19; +output [15:0] ap_return_20; +output [15:0] ap_return_21; +output [15:0] ap_return_22; +output [15:0] ap_return_23; +output [15:0] ap_return_24; +output [15:0] ap_return_25; +output [15:0] ap_return_26; +output [15:0] ap_return_27; +output [15:0] ap_return_28; +output [15:0] ap_return_29; +output [15:0] ap_return_30; +output [15:0] ap_return_31; +input ap_ce; + +reg[15:0] ap_return_0; +reg[15:0] ap_return_1; +reg[15:0] ap_return_2; +reg[15:0] ap_return_3; +reg[15:0] ap_return_4; +reg[15:0] ap_return_5; +reg[15:0] ap_return_6; +reg[15:0] ap_return_7; +reg[15:0] ap_return_8; +reg[15:0] ap_return_9; +reg[15:0] ap_return_10; +reg[15:0] ap_return_11; +reg[15:0] ap_return_12; +reg[15:0] ap_return_13; +reg[15:0] ap_return_14; +reg[15:0] ap_return_15; +reg[15:0] ap_return_16; +reg[15:0] ap_return_17; +reg[15:0] ap_return_18; +reg[15:0] ap_return_19; +reg[15:0] ap_return_20; +reg[15:0] ap_return_21; +reg[15:0] ap_return_22; +reg[15:0] ap_return_23; +reg[15:0] ap_return_24; +reg[15:0] ap_return_25; +reg[15:0] ap_return_26; +reg[15:0] ap_return_27; +reg[15:0] ap_return_28; +reg[15:0] ap_return_29; +reg[15:0] ap_return_30; +reg[15:0] ap_return_31; + +wire ap_block_state1_pp0_stage0_iter0; +wire ap_block_state2_pp0_stage0_iter1; +wire ap_block_state3_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [14:0] trunc_ln708_13_reg_5613; +reg [14:0] trunc_ln708_13_reg_5613_pp0_iter1_reg; +reg [13:0] tmp_385_reg_5703; +reg [14:0] trunc_ln708_s_reg_5708; +reg [15:0] trunc_ln708_4_reg_5713; +reg [14:0] trunc_ln708_5_reg_5718; +reg [15:0] trunc_ln708_6_reg_5723; +reg [15:0] trunc_ln708_7_reg_5728; +reg [14:0] trunc_ln708_8_reg_5733; +reg [14:0] trunc_ln708_9_reg_5738; +reg [15:0] trunc_ln708_1_reg_5743; +reg [15:0] trunc_ln708_2_reg_5748; +reg [15:0] trunc_ln708_3_reg_5753; +reg [15:0] trunc_ln708_10_reg_5758; +reg [15:0] trunc_ln708_11_reg_5763; +reg [15:0] trunc_ln708_12_reg_5768; +reg [15:0] trunc_ln708_14_reg_5773; +reg [14:0] trunc_ln708_15_reg_5778; +reg [14:0] trunc_ln708_16_reg_5783; +reg [15:0] trunc_ln708_17_reg_5788; +reg [14:0] trunc_ln708_18_reg_5793; +reg [15:0] trunc_ln708_19_reg_5798; +reg [15:0] trunc_ln708_20_reg_5803; +reg [15:0] trunc_ln708_21_reg_5808; +reg [15:0] trunc_ln708_22_reg_5813; +reg [15:0] trunc_ln708_23_reg_5818; +reg [15:0] trunc_ln708_24_reg_5823; +reg [15:0] trunc_ln708_25_reg_5828; +reg [15:0] trunc_ln708_26_reg_5833; +reg [15:0] trunc_ln708_27_reg_5838; +reg [15:0] trunc_ln708_28_reg_5843; +reg [15:0] trunc_ln708_29_reg_5848; +reg [14:0] trunc_ln708_30_reg_5853; +wire [9:0] grp_fu_424_p1; +wire ap_block_pp0_stage0; +wire [9:0] grp_fu_425_p1; +wire [8:0] grp_fu_426_p1; +wire [8:0] grp_fu_427_p1; +wire [9:0] grp_fu_428_p1; +wire [9:0] grp_fu_429_p1; +wire [8:0] grp_fu_430_p1; +wire [9:0] grp_fu_431_p1; +wire [8:0] grp_fu_432_p1; +wire [8:0] grp_fu_433_p1; +wire [9:0] grp_fu_435_p1; +wire [7:0] grp_fu_436_p1; +wire [9:0] grp_fu_437_p1; +wire [8:0] grp_fu_438_p1; +wire [8:0] grp_fu_439_p1; +wire [9:0] grp_fu_440_p1; +wire [9:0] grp_fu_441_p1; +wire [9:0] grp_fu_442_p1; +wire [9:0] grp_fu_443_p1; +wire [10:0] grp_fu_444_p1; +wire [8:0] grp_fu_445_p1; +wire [10:0] grp_fu_446_p1; +wire [9:0] grp_fu_447_p1; +wire [9:0] grp_fu_448_p1; +wire [10:0] grp_fu_449_p1; +wire [9:0] grp_fu_450_p1; +wire [9:0] grp_fu_451_p1; +wire [9:0] grp_fu_452_p1; +wire [9:0] grp_fu_453_p1; +wire [9:0] grp_fu_454_p1; +wire [9:0] grp_fu_455_p1; +wire [23:0] shl_ln_fu_4712_p3; +wire [16:0] shl_ln1118_9_fu_4724_p3; +wire [24:0] sext_ln1118_17_fu_4720_p1; +wire [24:0] sext_ln1118_18_fu_4732_p1; +wire [24:0] sub_ln1118_fu_4736_p2; +wire [23:0] grp_fu_436_p2; +wire [24:0] grp_fu_426_p2; +wire [25:0] grp_fu_435_p2; +wire [24:0] grp_fu_439_p2; +wire [25:0] grp_fu_440_p2; +wire [25:0] grp_fu_449_p2; +wire [24:0] grp_fu_432_p2; +wire [24:0] grp_fu_430_p2; +wire [25:0] grp_fu_441_p2; +wire [25:0] grp_fu_451_p2; +wire [25:0] grp_fu_425_p2; +wire [25:0] grp_fu_450_p2; +wire [25:0] grp_fu_428_p2; +wire [25:0] grp_fu_442_p2; +wire [25:0] grp_fu_446_p2; +wire [24:0] grp_fu_427_p2; +wire [24:0] grp_fu_445_p2; +wire [25:0] grp_fu_424_p2; +wire [24:0] grp_fu_438_p2; +wire [25:0] grp_fu_453_p2; +wire [25:0] grp_fu_431_p2; +wire [25:0] grp_fu_429_p2; +wire [25:0] grp_fu_455_p2; +wire [25:0] grp_fu_444_p2; +wire [25:0] grp_fu_448_p2; +wire [25:0] grp_fu_443_p2; +wire [25:0] grp_fu_452_p2; +wire [25:0] grp_fu_437_p2; +wire [25:0] grp_fu_447_p2; +wire [25:0] grp_fu_454_p2; +wire [24:0] grp_fu_433_p2; +wire [14:0] sext_ln703_fu_5147_p1; +wire [14:0] add_ln703_fu_5150_p2; +wire [15:0] sext_ln708_fu_5160_p1; +wire [15:0] sext_ln708_4_fu_5174_p1; +wire [15:0] sext_ln708_5_fu_5193_p1; +wire [15:0] sext_ln708_6_fu_5202_p1; +wire [15:0] sext_ln708_7_fu_5241_p1; +wire [15:0] sext_ln708_8_fu_5255_p1; +wire [15:0] sext_ln708_9_fu_5264_p1; +wire [15:0] sext_ln708_10_fu_5278_p1; +wire [15:0] sext_ln708_11_fu_5342_p1; +wire [15:0] sext_ln703_2_fu_5156_p1; +wire [15:0] add_ln703_5_fu_5163_p2; +wire [15:0] add_ln703_6_fu_5169_p2; +wire [15:0] add_ln703_7_fu_5177_p2; +wire [15:0] add_ln703_8_fu_5183_p2; +wire [15:0] add_ln703_9_fu_5188_p2; +wire [15:0] add_ln703_10_fu_5196_p2; +wire [15:0] add_ln703_11_fu_5205_p2; +wire [15:0] add_ln703_12_fu_5211_p2; +wire [15:0] add_ln703_13_fu_5216_p2; +wire [15:0] add_ln703_14_fu_5221_p2; +wire [15:0] add_ln703_15_fu_5226_p2; +wire [15:0] add_ln703_16_fu_5231_p2; +wire [15:0] add_ln703_17_fu_5236_p2; +wire [15:0] add_ln703_18_fu_5244_p2; +wire [15:0] add_ln703_19_fu_5250_p2; +wire [15:0] add_ln703_20_fu_5258_p2; +wire [15:0] add_ln703_21_fu_5267_p2; +wire [15:0] add_ln703_22_fu_5273_p2; +wire [15:0] add_ln703_23_fu_5281_p2; +wire [15:0] add_ln703_24_fu_5287_p2; +wire [15:0] add_ln703_25_fu_5292_p2; +wire [15:0] add_ln703_26_fu_5297_p2; +wire [15:0] add_ln703_27_fu_5302_p2; +wire [15:0] add_ln703_28_fu_5307_p2; +wire [15:0] add_ln703_29_fu_5312_p2; +wire [15:0] add_ln703_30_fu_5317_p2; +wire [15:0] add_ln703_31_fu_5322_p2; +wire [15:0] add_ln703_32_fu_5327_p2; +wire [15:0] add_ln703_33_fu_5332_p2; +wire [15:0] add_ln703_34_fu_5337_p2; +wire [15:0] add_ln703_35_fu_5345_p2; +reg grp_fu_424_ce; +reg grp_fu_425_ce; +reg grp_fu_426_ce; +reg grp_fu_427_ce; +reg grp_fu_428_ce; +reg grp_fu_429_ce; +reg grp_fu_430_ce; +reg grp_fu_431_ce; +reg grp_fu_432_ce; +reg grp_fu_433_ce; +reg grp_fu_435_ce; +reg grp_fu_436_ce; +reg grp_fu_437_ce; +reg grp_fu_438_ce; +reg grp_fu_439_ce; +reg grp_fu_440_ce; +reg grp_fu_441_ce; +reg grp_fu_442_ce; +reg grp_fu_443_ce; +reg grp_fu_444_ce; +reg grp_fu_445_ce; +reg grp_fu_446_ce; +reg grp_fu_447_ce; +reg grp_fu_448_ce; +reg grp_fu_449_ce; +reg grp_fu_450_ce; +reg grp_fu_451_ce; +reg grp_fu_452_ce; +reg grp_fu_453_ce; +reg grp_fu_454_ce; +reg grp_fu_455_ce; +reg ap_ce_reg; +reg [15:0] data_0_V_read_int_reg; +reg [15:0] data_1_V_read_int_reg; +reg [15:0] data_2_V_read_int_reg; +reg [15:0] data_3_V_read_int_reg; +reg [15:0] data_4_V_read_int_reg; +reg [15:0] data_5_V_read_int_reg; +reg [15:0] data_6_V_read_int_reg; +reg [15:0] data_7_V_read_int_reg; +reg [15:0] data_8_V_read_int_reg; +reg [15:0] data_9_V_read_int_reg; +reg [15:0] data_10_V_read_int_reg; +reg [15:0] data_11_V_read_int_reg; +reg [15:0] data_12_V_read_int_reg; +reg [15:0] data_13_V_read_int_reg; +reg [15:0] data_14_V_read_int_reg; +reg [15:0] data_15_V_read_int_reg; +reg [15:0] data_16_V_read_int_reg; +reg [15:0] data_17_V_read_int_reg; +reg [15:0] data_18_V_read_int_reg; +reg [15:0] data_19_V_read_int_reg; +reg [15:0] data_20_V_read_int_reg; +reg [15:0] data_21_V_read_int_reg; +reg [15:0] data_22_V_read_int_reg; +reg [15:0] data_23_V_read_int_reg; +reg [15:0] data_24_V_read_int_reg; +reg [15:0] data_25_V_read_int_reg; +reg [15:0] data_26_V_read_int_reg; +reg [15:0] data_27_V_read_int_reg; +reg [15:0] data_28_V_read_int_reg; +reg [15:0] data_29_V_read_int_reg; +reg [15:0] data_30_V_read_int_reg; +reg [15:0] data_31_V_read_int_reg; +reg [15:0] ap_return_0_int_reg; +reg [15:0] ap_return_1_int_reg; +reg [15:0] ap_return_2_int_reg; +reg [15:0] ap_return_3_int_reg; +reg [15:0] ap_return_4_int_reg; +reg [15:0] ap_return_5_int_reg; +reg [15:0] ap_return_6_int_reg; +reg [15:0] ap_return_7_int_reg; +reg [15:0] ap_return_8_int_reg; +reg [15:0] ap_return_9_int_reg; +reg [15:0] ap_return_10_int_reg; +reg [15:0] ap_return_11_int_reg; +reg [15:0] ap_return_12_int_reg; +reg [15:0] ap_return_13_int_reg; +reg [15:0] ap_return_14_int_reg; +reg [15:0] ap_return_15_int_reg; +reg [15:0] ap_return_16_int_reg; +reg [15:0] ap_return_17_int_reg; +reg [15:0] ap_return_18_int_reg; +reg [15:0] ap_return_19_int_reg; +reg [15:0] ap_return_20_int_reg; +reg [15:0] ap_return_21_int_reg; +reg [15:0] ap_return_22_int_reg; +reg [15:0] ap_return_23_int_reg; +reg [15:0] ap_return_24_int_reg; +reg [15:0] ap_return_25_int_reg; +reg [15:0] ap_return_26_int_reg; +reg [15:0] ap_return_27_int_reg; +reg [15:0] ap_return_28_int_reg; +reg [15:0] ap_return_29_int_reg; +reg [15:0] ap_return_30_int_reg; +reg [15:0] ap_return_31_int_reg; + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U385( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_18_V_read_int_reg), + .din1(grp_fu_424_p1), + .ce(grp_fu_424_ce), + .dout(grp_fu_424_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U386( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_10_V_read_int_reg), + .din1(grp_fu_425_p1), + .ce(grp_fu_425_ce), + .dout(grp_fu_425_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U387( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_1_V_read_int_reg), + .din1(grp_fu_426_p1), + .ce(grp_fu_426_ce), + .dout(grp_fu_426_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U388( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_16_V_read_int_reg), + .din1(grp_fu_427_p1), + .ce(grp_fu_427_ce), + .dout(grp_fu_427_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U389( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_12_V_read_int_reg), + .din1(grp_fu_428_p1), + .ce(grp_fu_428_ce), + .dout(grp_fu_428_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U390( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_22_V_read_int_reg), + .din1(grp_fu_429_p1), + .ce(grp_fu_429_ce), + .dout(grp_fu_429_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U391( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_7_V_read_int_reg), + .din1(grp_fu_430_p1), + .ce(grp_fu_430_ce), + .dout(grp_fu_430_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U392( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_21_V_read_int_reg), + .din1(grp_fu_431_p1), + .ce(grp_fu_431_ce), + .dout(grp_fu_431_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U393( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_6_V_read_int_reg), + .din1(grp_fu_432_p1), + .ce(grp_fu_432_ce), + .dout(grp_fu_432_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U394( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_31_V_read_int_reg), + .din1(grp_fu_433_p1), + .ce(grp_fu_433_ce), + .dout(grp_fu_433_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U395( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_2_V_read_int_reg), + .din1(grp_fu_435_p1), + .ce(grp_fu_435_ce), + .dout(grp_fu_435_p2) +); + +myproject_mul_16s_8ns_24_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 8 ), + .dout_WIDTH( 24 )) +myproject_mul_16s_8ns_24_2_0_U396( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_0_V_read_int_reg), + .din1(grp_fu_436_p1), + .ce(grp_fu_436_ce), + .dout(grp_fu_436_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U397( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_28_V_read_int_reg), + .din1(grp_fu_437_p1), + .ce(grp_fu_437_ce), + .dout(grp_fu_437_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U398( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_19_V_read_int_reg), + .din1(grp_fu_438_p1), + .ce(grp_fu_438_ce), + .dout(grp_fu_438_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U399( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_3_V_read_int_reg), + .din1(grp_fu_439_p1), + .ce(grp_fu_439_ce), + .dout(grp_fu_439_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U400( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_4_V_read_int_reg), + .din1(grp_fu_440_p1), + .ce(grp_fu_440_ce), + .dout(grp_fu_440_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U401( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_8_V_read_int_reg), + .din1(grp_fu_441_p1), + .ce(grp_fu_441_ce), + .dout(grp_fu_441_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U402( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_13_V_read_int_reg), + .din1(grp_fu_442_p1), + .ce(grp_fu_442_ce), + .dout(grp_fu_442_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U403( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_26_V_read_int_reg), + .din1(grp_fu_443_p1), + .ce(grp_fu_443_ce), + .dout(grp_fu_443_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U404( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_24_V_read_int_reg), + .din1(grp_fu_444_p1), + .ce(grp_fu_444_ce), + .dout(grp_fu_444_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U405( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_17_V_read_int_reg), + .din1(grp_fu_445_p1), + .ce(grp_fu_445_ce), + .dout(grp_fu_445_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U406( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_15_V_read_int_reg), + .din1(grp_fu_446_p1), + .ce(grp_fu_446_ce), + .dout(grp_fu_446_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U407( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_29_V_read_int_reg), + .din1(grp_fu_447_p1), + .ce(grp_fu_447_ce), + .dout(grp_fu_447_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U408( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_25_V_read_int_reg), + .din1(grp_fu_448_p1), + .ce(grp_fu_448_ce), + .dout(grp_fu_448_p2) +); + +myproject_mul_16s_11ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 11 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_11ns_26_2_0_U409( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_5_V_read_int_reg), + .din1(grp_fu_449_p1), + .ce(grp_fu_449_ce), + .dout(grp_fu_449_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U410( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_11_V_read_int_reg), + .din1(grp_fu_450_p1), + .ce(grp_fu_450_ce), + .dout(grp_fu_450_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U411( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_9_V_read_int_reg), + .din1(grp_fu_451_p1), + .ce(grp_fu_451_ce), + .dout(grp_fu_451_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U412( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_27_V_read_int_reg), + .din1(grp_fu_452_p1), + .ce(grp_fu_452_ce), + .dout(grp_fu_452_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U413( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_20_V_read_int_reg), + .din1(grp_fu_453_p1), + .ce(grp_fu_453_ce), + .dout(grp_fu_453_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U414( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_30_V_read_int_reg), + .din1(grp_fu_454_p1), + .ce(grp_fu_454_ce), + .dout(grp_fu_454_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U415( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_23_V_read_int_reg), + .din1(grp_fu_455_p1), + .ce(grp_fu_455_ce), + .dout(grp_fu_455_p2) +); + +always @ (posedge ap_clk) begin + ap_ce_reg <= ap_ce; +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce_reg)) begin + ap_return_0_int_reg <= sext_ln703_2_fu_5156_p1; + ap_return_10_int_reg <= add_ln703_14_fu_5221_p2; + ap_return_11_int_reg <= add_ln703_15_fu_5226_p2; + ap_return_12_int_reg <= add_ln703_16_fu_5231_p2; + ap_return_13_int_reg <= add_ln703_17_fu_5236_p2; + ap_return_14_int_reg <= add_ln703_18_fu_5244_p2; + ap_return_15_int_reg <= add_ln703_19_fu_5250_p2; + ap_return_16_int_reg <= add_ln703_20_fu_5258_p2; + ap_return_17_int_reg <= add_ln703_21_fu_5267_p2; + ap_return_18_int_reg <= add_ln703_22_fu_5273_p2; + ap_return_19_int_reg <= add_ln703_23_fu_5281_p2; + ap_return_1_int_reg <= add_ln703_5_fu_5163_p2; + ap_return_20_int_reg <= add_ln703_24_fu_5287_p2; + ap_return_21_int_reg <= add_ln703_25_fu_5292_p2; + ap_return_22_int_reg <= add_ln703_26_fu_5297_p2; + ap_return_23_int_reg <= add_ln703_27_fu_5302_p2; + ap_return_24_int_reg <= add_ln703_28_fu_5307_p2; + ap_return_25_int_reg <= add_ln703_29_fu_5312_p2; + ap_return_26_int_reg <= add_ln703_30_fu_5317_p2; + ap_return_27_int_reg <= add_ln703_31_fu_5322_p2; + ap_return_28_int_reg <= add_ln703_32_fu_5327_p2; + ap_return_29_int_reg <= add_ln703_33_fu_5332_p2; + ap_return_2_int_reg <= add_ln703_6_fu_5169_p2; + ap_return_30_int_reg <= add_ln703_34_fu_5337_p2; + ap_return_31_int_reg <= add_ln703_35_fu_5345_p2; + ap_return_3_int_reg <= add_ln703_7_fu_5177_p2; + ap_return_4_int_reg <= add_ln703_8_fu_5183_p2; + ap_return_5_int_reg <= add_ln703_9_fu_5188_p2; + ap_return_6_int_reg <= add_ln703_10_fu_5196_p2; + ap_return_7_int_reg <= add_ln703_11_fu_5205_p2; + ap_return_8_int_reg <= add_ln703_12_fu_5211_p2; + ap_return_9_int_reg <= add_ln703_13_fu_5216_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce)) begin + data_0_V_read_int_reg <= data_0_V_read; + data_10_V_read_int_reg <= data_10_V_read; + data_11_V_read_int_reg <= data_11_V_read; + data_12_V_read_int_reg <= data_12_V_read; + data_13_V_read_int_reg <= data_13_V_read; + data_14_V_read_int_reg <= data_14_V_read; + data_15_V_read_int_reg <= data_15_V_read; + data_16_V_read_int_reg <= data_16_V_read; + data_17_V_read_int_reg <= data_17_V_read; + data_18_V_read_int_reg <= data_18_V_read; + data_19_V_read_int_reg <= data_19_V_read; + data_1_V_read_int_reg <= data_1_V_read; + data_20_V_read_int_reg <= data_20_V_read; + data_21_V_read_int_reg <= data_21_V_read; + data_22_V_read_int_reg <= data_22_V_read; + data_23_V_read_int_reg <= data_23_V_read; + data_24_V_read_int_reg <= data_24_V_read; + data_25_V_read_int_reg <= data_25_V_read; + data_26_V_read_int_reg <= data_26_V_read; + data_27_V_read_int_reg <= data_27_V_read; + data_28_V_read_int_reg <= data_28_V_read; + data_29_V_read_int_reg <= data_29_V_read; + data_2_V_read_int_reg <= data_2_V_read; + data_30_V_read_int_reg <= data_30_V_read; + data_31_V_read_int_reg <= data_31_V_read; + data_3_V_read_int_reg <= data_3_V_read; + data_4_V_read_int_reg <= data_4_V_read; + data_5_V_read_int_reg <= data_5_V_read; + data_6_V_read_int_reg <= data_6_V_read; + data_7_V_read_int_reg <= data_7_V_read; + data_8_V_read_int_reg <= data_8_V_read; + data_9_V_read_int_reg <= data_9_V_read; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + tmp_385_reg_5703 <= {{grp_fu_436_p2[23:10]}}; + trunc_ln708_10_reg_5758 <= {{grp_fu_450_p2[25:10]}}; + trunc_ln708_11_reg_5763 <= {{grp_fu_428_p2[25:10]}}; + trunc_ln708_12_reg_5768 <= {{grp_fu_442_p2[25:10]}}; + trunc_ln708_13_reg_5613 <= {{sub_ln1118_fu_4736_p2[24:10]}}; + trunc_ln708_13_reg_5613_pp0_iter1_reg <= trunc_ln708_13_reg_5613; + trunc_ln708_14_reg_5773 <= {{grp_fu_446_p2[25:10]}}; + trunc_ln708_15_reg_5778 <= {{grp_fu_427_p2[24:10]}}; + trunc_ln708_16_reg_5783 <= {{grp_fu_445_p2[24:10]}}; + trunc_ln708_17_reg_5788 <= {{grp_fu_424_p2[25:10]}}; + trunc_ln708_18_reg_5793 <= {{grp_fu_438_p2[24:10]}}; + trunc_ln708_19_reg_5798 <= {{grp_fu_453_p2[25:10]}}; + trunc_ln708_1_reg_5743 <= {{grp_fu_441_p2[25:10]}}; + trunc_ln708_20_reg_5803 <= {{grp_fu_431_p2[25:10]}}; + trunc_ln708_21_reg_5808 <= {{grp_fu_429_p2[25:10]}}; + trunc_ln708_22_reg_5813 <= {{grp_fu_455_p2[25:10]}}; + trunc_ln708_23_reg_5818 <= {{grp_fu_444_p2[25:10]}}; + trunc_ln708_24_reg_5823 <= {{grp_fu_448_p2[25:10]}}; + trunc_ln708_25_reg_5828 <= {{grp_fu_443_p2[25:10]}}; + trunc_ln708_26_reg_5833 <= {{grp_fu_452_p2[25:10]}}; + trunc_ln708_27_reg_5838 <= {{grp_fu_437_p2[25:10]}}; + trunc_ln708_28_reg_5843 <= {{grp_fu_447_p2[25:10]}}; + trunc_ln708_29_reg_5848 <= {{grp_fu_454_p2[25:10]}}; + trunc_ln708_2_reg_5748 <= {{grp_fu_451_p2[25:10]}}; + trunc_ln708_30_reg_5853 <= {{grp_fu_433_p2[24:10]}}; + trunc_ln708_3_reg_5753 <= {{grp_fu_425_p2[25:10]}}; + trunc_ln708_4_reg_5713 <= {{grp_fu_435_p2[25:10]}}; + trunc_ln708_5_reg_5718 <= {{grp_fu_439_p2[24:10]}}; + trunc_ln708_6_reg_5723 <= {{grp_fu_440_p2[25:10]}}; + trunc_ln708_7_reg_5728 <= {{grp_fu_449_p2[25:10]}}; + trunc_ln708_8_reg_5733 <= {{grp_fu_432_p2[24:10]}}; + trunc_ln708_9_reg_5738 <= {{grp_fu_430_p2[24:10]}}; + trunc_ln708_s_reg_5708 <= {{grp_fu_426_p2[24:10]}}; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_0 = ap_return_0_int_reg; + end else begin + ap_return_0 = sext_ln703_2_fu_5156_p1; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_1 = ap_return_1_int_reg; + end else begin + ap_return_1 = add_ln703_5_fu_5163_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_10 = ap_return_10_int_reg; + end else begin + ap_return_10 = add_ln703_14_fu_5221_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_11 = ap_return_11_int_reg; + end else begin + ap_return_11 = add_ln703_15_fu_5226_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_12 = ap_return_12_int_reg; + end else begin + ap_return_12 = add_ln703_16_fu_5231_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_13 = ap_return_13_int_reg; + end else begin + ap_return_13 = add_ln703_17_fu_5236_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_14 = ap_return_14_int_reg; + end else begin + ap_return_14 = add_ln703_18_fu_5244_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_15 = ap_return_15_int_reg; + end else begin + ap_return_15 = add_ln703_19_fu_5250_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_16 = ap_return_16_int_reg; + end else begin + ap_return_16 = add_ln703_20_fu_5258_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_17 = ap_return_17_int_reg; + end else begin + ap_return_17 = add_ln703_21_fu_5267_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_18 = ap_return_18_int_reg; + end else begin + ap_return_18 = add_ln703_22_fu_5273_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_19 = ap_return_19_int_reg; + end else begin + ap_return_19 = add_ln703_23_fu_5281_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_2 = ap_return_2_int_reg; + end else begin + ap_return_2 = add_ln703_6_fu_5169_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_20 = ap_return_20_int_reg; + end else begin + ap_return_20 = add_ln703_24_fu_5287_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_21 = ap_return_21_int_reg; + end else begin + ap_return_21 = add_ln703_25_fu_5292_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_22 = ap_return_22_int_reg; + end else begin + ap_return_22 = add_ln703_26_fu_5297_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_23 = ap_return_23_int_reg; + end else begin + ap_return_23 = add_ln703_27_fu_5302_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_24 = ap_return_24_int_reg; + end else begin + ap_return_24 = add_ln703_28_fu_5307_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_25 = ap_return_25_int_reg; + end else begin + ap_return_25 = add_ln703_29_fu_5312_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_26 = ap_return_26_int_reg; + end else begin + ap_return_26 = add_ln703_30_fu_5317_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_27 = ap_return_27_int_reg; + end else begin + ap_return_27 = add_ln703_31_fu_5322_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_28 = ap_return_28_int_reg; + end else begin + ap_return_28 = add_ln703_32_fu_5327_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_29 = ap_return_29_int_reg; + end else begin + ap_return_29 = add_ln703_33_fu_5332_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_3 = ap_return_3_int_reg; + end else begin + ap_return_3 = add_ln703_7_fu_5177_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_30 = ap_return_30_int_reg; + end else begin + ap_return_30 = add_ln703_34_fu_5337_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_31 = ap_return_31_int_reg; + end else begin + ap_return_31 = add_ln703_35_fu_5345_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_4 = ap_return_4_int_reg; + end else begin + ap_return_4 = add_ln703_8_fu_5183_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_5 = ap_return_5_int_reg; + end else begin + ap_return_5 = add_ln703_9_fu_5188_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_6 = ap_return_6_int_reg; + end else begin + ap_return_6 = add_ln703_10_fu_5196_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_7 = ap_return_7_int_reg; + end else begin + ap_return_7 = add_ln703_11_fu_5205_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_8 = ap_return_8_int_reg; + end else begin + ap_return_8 = add_ln703_12_fu_5211_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_9 = ap_return_9_int_reg; + end else begin + ap_return_9 = add_ln703_13_fu_5216_p2; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_424_ce = 1'b1; + end else begin + grp_fu_424_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_425_ce = 1'b1; + end else begin + grp_fu_425_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_426_ce = 1'b1; + end else begin + grp_fu_426_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_427_ce = 1'b1; + end else begin + grp_fu_427_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_428_ce = 1'b1; + end else begin + grp_fu_428_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_429_ce = 1'b1; + end else begin + grp_fu_429_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_430_ce = 1'b1; + end else begin + grp_fu_430_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_431_ce = 1'b1; + end else begin + grp_fu_431_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_432_ce = 1'b1; + end else begin + grp_fu_432_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_433_ce = 1'b1; + end else begin + grp_fu_433_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_435_ce = 1'b1; + end else begin + grp_fu_435_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_436_ce = 1'b1; + end else begin + grp_fu_436_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_437_ce = 1'b1; + end else begin + grp_fu_437_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_438_ce = 1'b1; + end else begin + grp_fu_438_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_439_ce = 1'b1; + end else begin + grp_fu_439_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_440_ce = 1'b1; + end else begin + grp_fu_440_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_441_ce = 1'b1; + end else begin + grp_fu_441_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_442_ce = 1'b1; + end else begin + grp_fu_442_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_443_ce = 1'b1; + end else begin + grp_fu_443_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_444_ce = 1'b1; + end else begin + grp_fu_444_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_445_ce = 1'b1; + end else begin + grp_fu_445_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_446_ce = 1'b1; + end else begin + grp_fu_446_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_447_ce = 1'b1; + end else begin + grp_fu_447_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_448_ce = 1'b1; + end else begin + grp_fu_448_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_449_ce = 1'b1; + end else begin + grp_fu_449_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_450_ce = 1'b1; + end else begin + grp_fu_450_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_451_ce = 1'b1; + end else begin + grp_fu_451_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_452_ce = 1'b1; + end else begin + grp_fu_452_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_453_ce = 1'b1; + end else begin + grp_fu_453_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_454_ce = 1'b1; + end else begin + grp_fu_454_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_455_ce = 1'b1; + end else begin + grp_fu_455_ce = 1'b0; + end +end + +assign add_ln703_10_fu_5196_p2 = ((sext_ln708_5_fu_5193_p1) + (16'd446)); + +assign add_ln703_11_fu_5205_p2 = ((sext_ln708_6_fu_5202_p1) + (16'd597)); + +assign add_ln703_12_fu_5211_p2 = (trunc_ln708_1_reg_5743 + 16'd408); + +assign add_ln703_13_fu_5216_p2 = (trunc_ln708_2_reg_5748 + 16'd634); + +assign add_ln703_14_fu_5221_p2 = ((trunc_ln708_3_reg_5753) + (16'd65224)); + +assign add_ln703_15_fu_5226_p2 = (trunc_ln708_10_reg_5758 + 16'd1821); + +assign add_ln703_16_fu_5231_p2 = ((trunc_ln708_11_reg_5763) + (16'd64651)); + +assign add_ln703_17_fu_5236_p2 = (trunc_ln708_12_reg_5768 + 16'd672); + +assign add_ln703_18_fu_5244_p2 = ((sext_ln708_7_fu_5241_p1) + (16'd445)); + +assign add_ln703_19_fu_5250_p2 = (trunc_ln708_14_reg_5773 + 16'd15); + +assign add_ln703_20_fu_5258_p2 = ((sext_ln708_8_fu_5255_p1) + (16'd64909)); + +assign add_ln703_21_fu_5267_p2 = ((sext_ln708_9_fu_5264_p1) + (16'd65100)); + +assign add_ln703_22_fu_5273_p2 = ((trunc_ln708_17_reg_5788) + (16'd64899)); + +assign add_ln703_23_fu_5281_p2 = ((sext_ln708_10_fu_5278_p1) + (16'd439)); + +assign add_ln703_24_fu_5287_p2 = ((trunc_ln708_19_reg_5798) + (16'd64895)); + +assign add_ln703_25_fu_5292_p2 = (trunc_ln708_20_reg_5803 + 16'd379); + +assign add_ln703_26_fu_5297_p2 = ((trunc_ln708_21_reg_5808) + (16'd65532)); + +assign add_ln703_27_fu_5302_p2 = ((trunc_ln708_22_reg_5813) + (16'd65400)); + +assign add_ln703_28_fu_5307_p2 = (trunc_ln708_23_reg_5818 + 16'd622); + +assign add_ln703_29_fu_5312_p2 = (trunc_ln708_24_reg_5823 + 16'd15); + +assign add_ln703_30_fu_5317_p2 = ((trunc_ln708_25_reg_5828) + (16'd65459)); + +assign add_ln703_31_fu_5322_p2 = (trunc_ln708_26_reg_5833 + 16'd416); + +assign add_ln703_32_fu_5327_p2 = (trunc_ln708_27_reg_5838 + 16'd31); + +assign add_ln703_33_fu_5332_p2 = ((trunc_ln708_28_reg_5843) + (16'd65502)); + +assign add_ln703_34_fu_5337_p2 = ((trunc_ln708_29_reg_5848) + (16'd64870)); + +assign add_ln703_35_fu_5345_p2 = ((sext_ln708_11_fu_5342_p1) + (16'd288)); + +assign add_ln703_5_fu_5163_p2 = ((sext_ln708_fu_5160_p1) + (16'd65252)); + +assign add_ln703_6_fu_5169_p2 = (trunc_ln708_4_reg_5713 + 16'd617); + +assign add_ln703_7_fu_5177_p2 = ((sext_ln708_4_fu_5174_p1) + (16'd129)); + +assign add_ln703_8_fu_5183_p2 = ((trunc_ln708_6_reg_5723) + (16'd64666)); + +assign add_ln703_9_fu_5188_p2 = ((trunc_ln708_7_reg_5728) + (16'd65475)); + +assign add_ln703_fu_5150_p2 = ((sext_ln703_fu_5147_p1) + (15'd32383)); + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign grp_fu_424_p1 = 10'd421; + +assign grp_fu_425_p1 = 10'd353; + +assign grp_fu_426_p1 = 9'd197; + +assign grp_fu_427_p1 = 9'd198; + +assign grp_fu_428_p1 = 10'd365; + +assign grp_fu_429_p1 = 10'd359; + +assign grp_fu_430_p1 = 9'd194; + +assign grp_fu_431_p1 = 10'd358; + +assign grp_fu_432_p1 = 9'd198; + +assign grp_fu_433_p1 = 9'd253; + +assign grp_fu_435_p1 = 10'd316; + +assign grp_fu_436_p1 = 8'd125; + +assign grp_fu_437_p1 = 10'd453; + +assign grp_fu_438_p1 = 9'd233; + +assign grp_fu_439_p1 = 9'd220; + +assign grp_fu_440_p1 = 10'd341; + +assign grp_fu_441_p1 = 10'd294; + +assign grp_fu_442_p1 = 10'd310; + +assign grp_fu_443_p1 = 10'd280; + +assign grp_fu_444_p1 = 11'd617; + +assign grp_fu_445_p1 = 9'd241; + +assign grp_fu_446_p1 = 11'd618; + +assign grp_fu_447_p1 = 10'd319; + +assign grp_fu_448_p1 = 10'd385; + +assign grp_fu_449_p1 = 11'd616; + +assign grp_fu_450_p1 = 10'd486; + +assign grp_fu_451_p1 = 10'd447; + +assign grp_fu_452_p1 = 10'd324; + +assign grp_fu_453_p1 = 10'd484; + +assign grp_fu_454_p1 = 10'd487; + +assign grp_fu_455_p1 = 10'd485; + +assign sext_ln1118_17_fu_4720_p1 = (shl_ln_fu_4712_p3); + +assign sext_ln1118_18_fu_4732_p1 = (shl_ln1118_9_fu_4724_p3); + +assign sext_ln703_2_fu_5156_p1 = (add_ln703_fu_5150_p2); + +assign sext_ln703_fu_5147_p1 = (tmp_385_reg_5703); + +assign sext_ln708_10_fu_5278_p1 = (trunc_ln708_18_reg_5793); + +assign sext_ln708_11_fu_5342_p1 = (trunc_ln708_30_reg_5853); + +assign sext_ln708_4_fu_5174_p1 = (trunc_ln708_5_reg_5718); + +assign sext_ln708_5_fu_5193_p1 = (trunc_ln708_8_reg_5733); + +assign sext_ln708_6_fu_5202_p1 = (trunc_ln708_9_reg_5738); + +assign sext_ln708_7_fu_5241_p1 = (trunc_ln708_13_reg_5613_pp0_iter1_reg); + +assign sext_ln708_8_fu_5255_p1 = (trunc_ln708_15_reg_5778); + +assign sext_ln708_9_fu_5264_p1 = (trunc_ln708_16_reg_5783); + +assign sext_ln708_fu_5160_p1 = (trunc_ln708_s_reg_5708); + +assign shl_ln1118_9_fu_4724_p3 = {{data_14_V_read_int_reg}, {1'd0}}; + +assign shl_ln_fu_4712_p3 = {{data_14_V_read_int_reg}, {8'd0}}; + +assign sub_ln1118_fu_4736_p2 = ((sext_ln1118_17_fu_4720_p1) - (sext_ln1118_18_fu_4732_p1)); + +endmodule //normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_2 +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s ( + ap_clk, + ap_rst, + data_0_V_read, + data_1_V_read, + data_2_V_read, + data_3_V_read, + data_4_V_read, + data_5_V_read, + data_6_V_read, + data_7_V_read, + data_8_V_read, + data_9_V_read, + data_10_V_read, + data_11_V_read, + data_12_V_read, + data_13_V_read, + data_14_V_read, + data_15_V_read, + data_16_V_read, + data_17_V_read, + data_18_V_read, + data_19_V_read, + data_20_V_read, + data_21_V_read, + data_22_V_read, + data_23_V_read, + data_24_V_read, + data_25_V_read, + data_26_V_read, + data_27_V_read, + data_28_V_read, + data_29_V_read, + data_30_V_read, + data_31_V_read, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3, + ap_return_4, + ap_return_5, + ap_return_6, + ap_return_7, + ap_return_8, + ap_return_9, + ap_return_10, + ap_return_11, + ap_return_12, + ap_return_13, + ap_return_14, + ap_return_15, + ap_return_16, + ap_return_17, + ap_return_18, + ap_return_19, + ap_return_20, + ap_return_21, + ap_return_22, + ap_return_23, + ap_return_24, + ap_return_25, + ap_return_26, + ap_return_27, + ap_return_28, + ap_return_29, + ap_return_30, + ap_return_31, + ap_ce +); + + +input ap_clk; +input ap_rst; +input [15:0] data_0_V_read; +input [15:0] data_1_V_read; +input [15:0] data_2_V_read; +input [15:0] data_3_V_read; +input [15:0] data_4_V_read; +input [15:0] data_5_V_read; +input [15:0] data_6_V_read; +input [15:0] data_7_V_read; +input [15:0] data_8_V_read; +input [15:0] data_9_V_read; +input [15:0] data_10_V_read; +input [15:0] data_11_V_read; +input [15:0] data_12_V_read; +input [15:0] data_13_V_read; +input [15:0] data_14_V_read; +input [15:0] data_15_V_read; +input [15:0] data_16_V_read; +input [15:0] data_17_V_read; +input [15:0] data_18_V_read; +input [15:0] data_19_V_read; +input [15:0] data_20_V_read; +input [15:0] data_21_V_read; +input [15:0] data_22_V_read; +input [15:0] data_23_V_read; +input [15:0] data_24_V_read; +input [15:0] data_25_V_read; +input [15:0] data_26_V_read; +input [15:0] data_27_V_read; +input [15:0] data_28_V_read; +input [15:0] data_29_V_read; +input [15:0] data_30_V_read; +input [15:0] data_31_V_read; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; +output [15:0] ap_return_4; +output [15:0] ap_return_5; +output [15:0] ap_return_6; +output [15:0] ap_return_7; +output [15:0] ap_return_8; +output [15:0] ap_return_9; +output [15:0] ap_return_10; +output [15:0] ap_return_11; +output [15:0] ap_return_12; +output [15:0] ap_return_13; +output [15:0] ap_return_14; +output [15:0] ap_return_15; +output [15:0] ap_return_16; +output [15:0] ap_return_17; +output [15:0] ap_return_18; +output [15:0] ap_return_19; +output [15:0] ap_return_20; +output [15:0] ap_return_21; +output [15:0] ap_return_22; +output [15:0] ap_return_23; +output [15:0] ap_return_24; +output [15:0] ap_return_25; +output [15:0] ap_return_26; +output [15:0] ap_return_27; +output [15:0] ap_return_28; +output [15:0] ap_return_29; +output [15:0] ap_return_30; +output [15:0] ap_return_31; +input ap_ce; + +reg[15:0] ap_return_0; +reg[15:0] ap_return_1; +reg[15:0] ap_return_2; +reg[15:0] ap_return_3; +reg[15:0] ap_return_4; +reg[15:0] ap_return_5; +reg[15:0] ap_return_6; +reg[15:0] ap_return_7; +reg[15:0] ap_return_8; +reg[15:0] ap_return_9; +reg[15:0] ap_return_10; +reg[15:0] ap_return_11; +reg[15:0] ap_return_12; +reg[15:0] ap_return_13; +reg[15:0] ap_return_14; +reg[15:0] ap_return_15; +reg[15:0] ap_return_16; +reg[15:0] ap_return_17; +reg[15:0] ap_return_18; +reg[15:0] ap_return_19; +reg[15:0] ap_return_20; +reg[15:0] ap_return_21; +reg[15:0] ap_return_22; +reg[15:0] ap_return_23; +reg[15:0] ap_return_24; +reg[15:0] ap_return_25; +reg[15:0] ap_return_26; +reg[15:0] ap_return_27; +reg[15:0] ap_return_28; +reg[15:0] ap_return_29; +reg[15:0] ap_return_30; +reg[15:0] ap_return_31; + +wire ap_block_state1_pp0_stage0_iter0; +wire ap_block_state2_pp0_stage0_iter1; +wire ap_block_state3_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [14:0] trunc_ln708_22_reg_5489; +reg [14:0] trunc_ln708_22_reg_5489_pp0_iter1_reg; +reg [14:0] trunc_ln708_27_reg_5514; +reg [14:0] trunc_ln708_27_reg_5514_pp0_iter1_reg; +reg [13:0] tmp_386_reg_5519; +reg [13:0] tmp_386_reg_5519_pp0_iter1_reg; +reg [14:0] trunc_ln_reg_5539; +reg [14:0] trunc_ln708_1_reg_5544; +reg [14:0] trunc_ln708_2_reg_5549; +reg [14:0] trunc_ln708_3_reg_5554; +reg [14:0] trunc_ln708_4_reg_5559; +reg [14:0] trunc_ln708_5_reg_5564; +reg [15:0] trunc_ln708_6_reg_5569; +reg [14:0] trunc_ln708_7_reg_5574; +reg [14:0] trunc_ln708_8_reg_5579; +reg [15:0] trunc_ln708_9_reg_5584; +reg [14:0] trunc_ln708_10_reg_5589; +reg [15:0] trunc_ln708_11_reg_5594; +reg [14:0] trunc_ln708_12_reg_5599; +reg [14:0] trunc_ln708_13_reg_5604; +reg [14:0] trunc_ln708_14_reg_5609; +reg [14:0] trunc_ln708_15_reg_5614; +reg [15:0] trunc_ln708_16_reg_5619; +reg [15:0] trunc_ln708_17_reg_5624; +reg [14:0] trunc_ln708_18_reg_5629; +reg [15:0] trunc_ln708_19_reg_5634; +reg [14:0] trunc_ln708_20_reg_5639; +reg [14:0] trunc_ln708_21_reg_5644; +reg [14:0] trunc_ln708_23_reg_5649; +reg [14:0] trunc_ln708_24_reg_5654; +reg [14:0] trunc_ln708_25_reg_5659; +reg [14:0] trunc_ln708_26_reg_5664; +reg [14:0] trunc_ln708_29_reg_5669; +reg [14:0] trunc_ln708_30_reg_5674; +reg [15:0] trunc_ln708_31_reg_5679; +wire [8:0] grp_fu_428_p1; +wire ap_block_pp0_stage0; +wire [8:0] grp_fu_430_p1; +wire [8:0] grp_fu_431_p1; +wire [8:0] grp_fu_432_p1; +wire [8:0] grp_fu_433_p1; +wire [8:0] grp_fu_435_p1; +wire [8:0] grp_fu_436_p1; +wire [9:0] grp_fu_437_p1; +wire [9:0] grp_fu_438_p1; +wire [9:0] grp_fu_439_p1; +wire [9:0] grp_fu_440_p1; +wire [8:0] grp_fu_441_p1; +wire [8:0] grp_fu_442_p1; +wire [8:0] grp_fu_443_p1; +wire [8:0] grp_fu_444_p1; +wire [9:0] grp_fu_445_p1; +wire [8:0] grp_fu_446_p1; +wire [8:0] grp_fu_447_p1; +wire [8:0] grp_fu_448_p1; +wire [8:0] grp_fu_449_p1; +wire [8:0] grp_fu_451_p1; +wire [8:0] grp_fu_452_p1; +wire [9:0] grp_fu_453_p1; +wire [8:0] grp_fu_454_p1; +wire [9:0] grp_fu_455_p1; +wire [8:0] grp_fu_456_p1; +wire [8:0] grp_fu_457_p1; +wire [8:0] grp_fu_458_p1; +wire [8:0] grp_fu_459_p1; +wire [15:0] sext_ln1118_22_fu_4486_p0; +wire [15:0] shl_ln_fu_4490_p1; +wire [23:0] shl_ln_fu_4490_p3; +wire [24:0] sext_ln1118_23_fu_4498_p1; +wire [24:0] sext_ln1118_22_fu_4486_p1; +wire [24:0] add_ln1118_fu_4502_p2; +wire [23:0] shl_ln1118_1_fu_4538_p3; +wire [21:0] shl_ln1118_2_fu_4550_p3; +wire [24:0] sext_ln1118_29_fu_4558_p1; +wire [24:0] sext_ln1118_28_fu_4546_p1; +wire [24:0] add_ln1118_1_fu_4562_p2; +wire [22:0] shl_ln1118_3_fu_4578_p3; +wire [20:0] shl_ln1118_4_fu_4590_p3; +wire [23:0] sext_ln1118_31_fu_4598_p1; +wire [23:0] sext_ln1118_30_fu_4586_p1; +wire [23:0] add_ln1118_2_fu_4602_p2; +wire [24:0] grp_fu_435_p2; +wire [24:0] grp_fu_442_p2; +wire [24:0] grp_fu_446_p2; +wire [24:0] grp_fu_458_p2; +wire [24:0] grp_fu_444_p2; +wire [24:0] grp_fu_454_p2; +wire [25:0] grp_fu_437_p2; +wire [24:0] grp_fu_452_p2; +wire [24:0] grp_fu_436_p2; +wire [25:0] grp_fu_445_p2; +wire [24:0] grp_fu_448_p2; +wire [25:0] grp_fu_438_p2; +wire [24:0] grp_fu_443_p2; +wire [24:0] grp_fu_431_p2; +wire [24:0] grp_fu_428_p2; +wire [24:0] grp_fu_456_p2; +wire [25:0] grp_fu_455_p2; +wire [25:0] grp_fu_439_p2; +wire [24:0] grp_fu_433_p2; +wire [25:0] grp_fu_453_p2; +wire [24:0] grp_fu_451_p2; +wire [24:0] grp_fu_430_p2; +wire [24:0] grp_fu_447_p2; +wire [24:0] grp_fu_449_p2; +wire [24:0] grp_fu_441_p2; +wire [24:0] grp_fu_459_p2; +wire [24:0] grp_fu_457_p2; +wire [24:0] grp_fu_432_p2; +wire [25:0] grp_fu_440_p2; +wire [15:0] sext_ln708_fu_4923_p1; +wire [15:0] sext_ln708_1_fu_4932_p1; +wire [15:0] sext_ln708_2_fu_4941_p1; +wire [15:0] sext_ln708_3_fu_4950_p1; +wire [15:0] sext_ln708_4_fu_4959_p1; +wire [15:0] sext_ln708_5_fu_4968_p1; +wire [15:0] sext_ln708_6_fu_4982_p1; +wire [15:0] sext_ln708_7_fu_4991_p1; +wire [15:0] sext_ln708_8_fu_5005_p1; +wire [15:0] sext_ln708_9_fu_5019_p1; +wire [15:0] sext_ln708_10_fu_5028_p1; +wire [15:0] sext_ln708_11_fu_5037_p1; +wire [15:0] sext_ln708_12_fu_5046_p1; +wire [15:0] sext_ln708_13_fu_5065_p1; +wire [15:0] sext_ln708_14_fu_5079_p1; +wire [15:0] sext_ln708_15_fu_5088_p1; +wire [15:0] sext_ln708_16_fu_5097_p1; +wire [15:0] sext_ln708_17_fu_5106_p1; +wire [15:0] sext_ln708_18_fu_5115_p1; +wire [15:0] sext_ln708_19_fu_5124_p1; +wire [15:0] sext_ln708_20_fu_5133_p1; +wire [15:0] sext_ln708_21_fu_5142_p1; +wire [14:0] sext_ln703_fu_5151_p1; +wire [14:0] add_ln703_126_fu_5154_p2; +wire [15:0] sext_ln708_22_fu_5164_p1; +wire [15:0] sext_ln708_23_fu_5173_p1; +wire [15:0] add_ln703_fu_4926_p2; +wire [15:0] add_ln703_99_fu_4935_p2; +wire [15:0] add_ln703_100_fu_4944_p2; +wire [15:0] add_ln703_101_fu_4953_p2; +wire [15:0] add_ln703_102_fu_4962_p2; +wire [15:0] add_ln703_103_fu_4971_p2; +wire [15:0] add_ln703_104_fu_4977_p2; +wire [15:0] add_ln703_105_fu_4985_p2; +wire [15:0] add_ln703_106_fu_4994_p2; +wire [15:0] add_ln703_107_fu_5000_p2; +wire [15:0] add_ln703_108_fu_5008_p2; +wire [15:0] add_ln703_109_fu_5014_p2; +wire [15:0] add_ln703_110_fu_5022_p2; +wire [15:0] add_ln703_111_fu_5031_p2; +wire [15:0] add_ln703_112_fu_5040_p2; +wire [15:0] add_ln703_113_fu_5049_p2; +wire [15:0] add_ln703_114_fu_5055_p2; +wire [15:0] add_ln703_115_fu_5060_p2; +wire [15:0] add_ln703_116_fu_5068_p2; +wire [15:0] add_ln703_117_fu_5074_p2; +wire [15:0] add_ln703_118_fu_5082_p2; +wire [15:0] add_ln703_119_fu_5091_p2; +wire [15:0] add_ln703_120_fu_5100_p2; +wire [15:0] add_ln703_121_fu_5109_p2; +wire [15:0] add_ln703_122_fu_5118_p2; +wire [15:0] add_ln703_123_fu_5127_p2; +wire [15:0] add_ln703_124_fu_5136_p2; +wire [15:0] add_ln703_125_fu_5145_p2; +wire [15:0] sext_ln703_3_fu_5160_p1; +wire [15:0] add_ln703_127_fu_5167_p2; +wire [15:0] add_ln703_128_fu_5176_p2; +wire [15:0] add_ln703_129_fu_5182_p2; +reg grp_fu_428_ce; +reg grp_fu_430_ce; +reg grp_fu_431_ce; +reg grp_fu_432_ce; +reg grp_fu_433_ce; +reg grp_fu_435_ce; +reg grp_fu_436_ce; +reg grp_fu_437_ce; +reg grp_fu_438_ce; +reg grp_fu_439_ce; +reg grp_fu_440_ce; +reg grp_fu_441_ce; +reg grp_fu_442_ce; +reg grp_fu_443_ce; +reg grp_fu_444_ce; +reg grp_fu_445_ce; +reg grp_fu_446_ce; +reg grp_fu_447_ce; +reg grp_fu_448_ce; +reg grp_fu_449_ce; +reg grp_fu_451_ce; +reg grp_fu_452_ce; +reg grp_fu_453_ce; +reg grp_fu_454_ce; +reg grp_fu_455_ce; +reg grp_fu_456_ce; +reg grp_fu_457_ce; +reg grp_fu_458_ce; +reg grp_fu_459_ce; +reg ap_ce_reg; +reg [15:0] data_0_V_read_int_reg; +reg [15:0] data_1_V_read_int_reg; +reg [15:0] data_2_V_read_int_reg; +reg [15:0] data_3_V_read_int_reg; +reg [15:0] data_4_V_read_int_reg; +reg [15:0] data_5_V_read_int_reg; +reg [15:0] data_6_V_read_int_reg; +reg [15:0] data_7_V_read_int_reg; +reg [15:0] data_8_V_read_int_reg; +reg [15:0] data_9_V_read_int_reg; +reg [15:0] data_10_V_read_int_reg; +reg [15:0] data_11_V_read_int_reg; +reg [15:0] data_12_V_read_int_reg; +reg [15:0] data_13_V_read_int_reg; +reg [15:0] data_14_V_read_int_reg; +reg [15:0] data_15_V_read_int_reg; +reg [15:0] data_16_V_read_int_reg; +reg [15:0] data_17_V_read_int_reg; +reg [15:0] data_18_V_read_int_reg; +reg [15:0] data_19_V_read_int_reg; +reg [15:0] data_20_V_read_int_reg; +reg [15:0] data_21_V_read_int_reg; +reg [15:0] data_22_V_read_int_reg; +reg [15:0] data_23_V_read_int_reg; +reg [15:0] data_24_V_read_int_reg; +reg [15:0] data_25_V_read_int_reg; +reg [15:0] data_26_V_read_int_reg; +reg [15:0] data_27_V_read_int_reg; +reg [15:0] data_28_V_read_int_reg; +reg [15:0] data_29_V_read_int_reg; +reg [15:0] data_30_V_read_int_reg; +reg [15:0] data_31_V_read_int_reg; +reg [15:0] ap_return_0_int_reg; +reg [15:0] ap_return_1_int_reg; +reg [15:0] ap_return_2_int_reg; +reg [15:0] ap_return_3_int_reg; +reg [15:0] ap_return_4_int_reg; +reg [15:0] ap_return_5_int_reg; +reg [15:0] ap_return_6_int_reg; +reg [15:0] ap_return_7_int_reg; +reg [15:0] ap_return_8_int_reg; +reg [15:0] ap_return_9_int_reg; +reg [15:0] ap_return_10_int_reg; +reg [15:0] ap_return_11_int_reg; +reg [15:0] ap_return_12_int_reg; +reg [15:0] ap_return_13_int_reg; +reg [15:0] ap_return_14_int_reg; +reg [15:0] ap_return_15_int_reg; +reg [15:0] ap_return_16_int_reg; +reg [15:0] ap_return_17_int_reg; +reg [15:0] ap_return_18_int_reg; +reg [15:0] ap_return_19_int_reg; +reg [15:0] ap_return_20_int_reg; +reg [15:0] ap_return_21_int_reg; +reg [15:0] ap_return_22_int_reg; +reg [15:0] ap_return_23_int_reg; +reg [15:0] ap_return_24_int_reg; +reg [15:0] ap_return_25_int_reg; +reg [15:0] ap_return_26_int_reg; +reg [15:0] ap_return_27_int_reg; +reg [15:0] ap_return_28_int_reg; +reg [15:0] ap_return_29_int_reg; +reg [15:0] ap_return_30_int_reg; +reg [15:0] ap_return_31_int_reg; + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U258( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_14_V_read_int_reg), + .din1(grp_fu_428_p1), + .ce(grp_fu_428_ce), + .dout(grp_fu_428_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U259( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_21_V_read_int_reg), + .din1(grp_fu_430_p1), + .ce(grp_fu_430_ce), + .dout(grp_fu_430_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U260( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_13_V_read_int_reg), + .din1(grp_fu_431_p1), + .ce(grp_fu_431_ce), + .dout(grp_fu_431_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U261( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_30_V_read_int_reg), + .din1(grp_fu_432_p1), + .ce(grp_fu_432_ce), + .dout(grp_fu_432_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U262( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_18_V_read_int_reg), + .din1(grp_fu_433_p1), + .ce(grp_fu_433_ce), + .dout(grp_fu_433_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U263( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_0_V_read_int_reg), + .din1(grp_fu_435_p1), + .ce(grp_fu_435_ce), + .dout(grp_fu_435_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U264( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_8_V_read_int_reg), + .din1(grp_fu_436_p1), + .ce(grp_fu_436_ce), + .dout(grp_fu_436_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U265( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_6_V_read_int_reg), + .din1(grp_fu_437_p1), + .ce(grp_fu_437_ce), + .dout(grp_fu_437_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U266( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_11_V_read_int_reg), + .din1(grp_fu_438_p1), + .ce(grp_fu_438_ce), + .dout(grp_fu_438_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U267( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_17_V_read_int_reg), + .din1(grp_fu_439_p1), + .ce(grp_fu_439_ce), + .dout(grp_fu_439_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U268( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_31_V_read_int_reg), + .din1(grp_fu_440_p1), + .ce(grp_fu_440_ce), + .dout(grp_fu_440_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U269( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_25_V_read_int_reg), + .din1(grp_fu_441_p1), + .ce(grp_fu_441_ce), + .dout(grp_fu_441_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U270( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_1_V_read_int_reg), + .din1(grp_fu_442_p1), + .ce(grp_fu_442_ce), + .dout(grp_fu_442_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U271( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_12_V_read_int_reg), + .din1(grp_fu_443_p1), + .ce(grp_fu_443_ce), + .dout(grp_fu_443_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U272( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_4_V_read_int_reg), + .din1(grp_fu_444_p1), + .ce(grp_fu_444_ce), + .dout(grp_fu_444_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U273( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_9_V_read_int_reg), + .din1(grp_fu_445_p1), + .ce(grp_fu_445_ce), + .dout(grp_fu_445_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U274( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_2_V_read_int_reg), + .din1(grp_fu_446_p1), + .ce(grp_fu_446_ce), + .dout(grp_fu_446_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U275( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_23_V_read_int_reg), + .din1(grp_fu_447_p1), + .ce(grp_fu_447_ce), + .dout(grp_fu_447_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U276( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_10_V_read_int_reg), + .din1(grp_fu_448_p1), + .ce(grp_fu_448_ce), + .dout(grp_fu_448_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U277( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_24_V_read_int_reg), + .din1(grp_fu_449_p1), + .ce(grp_fu_449_ce), + .dout(grp_fu_449_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U278( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_20_V_read_int_reg), + .din1(grp_fu_451_p1), + .ce(grp_fu_451_ce), + .dout(grp_fu_451_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U279( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_7_V_read_int_reg), + .din1(grp_fu_452_p1), + .ce(grp_fu_452_ce), + .dout(grp_fu_452_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U280( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_19_V_read_int_reg), + .din1(grp_fu_453_p1), + .ce(grp_fu_453_ce), + .dout(grp_fu_453_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U281( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_5_V_read_int_reg), + .din1(grp_fu_454_p1), + .ce(grp_fu_454_ce), + .dout(grp_fu_454_p2) +); + +myproject_mul_16s_10ns_26_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 10 ), + .dout_WIDTH( 26 )) +myproject_mul_16s_10ns_26_2_0_U282( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_16_V_read_int_reg), + .din1(grp_fu_455_p1), + .ce(grp_fu_455_ce), + .dout(grp_fu_455_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U283( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_15_V_read_int_reg), + .din1(grp_fu_456_p1), + .ce(grp_fu_456_ce), + .dout(grp_fu_456_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U284( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_29_V_read_int_reg), + .din1(grp_fu_457_p1), + .ce(grp_fu_457_ce), + .dout(grp_fu_457_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U285( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_3_V_read_int_reg), + .din1(grp_fu_458_p1), + .ce(grp_fu_458_ce), + .dout(grp_fu_458_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U286( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_26_V_read_int_reg), + .din1(grp_fu_459_p1), + .ce(grp_fu_459_ce), + .dout(grp_fu_459_p2) +); + +always @ (posedge ap_clk) begin + ap_ce_reg <= ap_ce; +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce_reg)) begin + ap_return_0_int_reg <= add_ln703_fu_4926_p2; + ap_return_10_int_reg <= add_ln703_108_fu_5008_p2; + ap_return_11_int_reg <= add_ln703_109_fu_5014_p2; + ap_return_12_int_reg <= add_ln703_110_fu_5022_p2; + ap_return_13_int_reg <= add_ln703_111_fu_5031_p2; + ap_return_14_int_reg <= add_ln703_112_fu_5040_p2; + ap_return_15_int_reg <= add_ln703_113_fu_5049_p2; + ap_return_16_int_reg <= add_ln703_114_fu_5055_p2; + ap_return_17_int_reg <= add_ln703_115_fu_5060_p2; + ap_return_18_int_reg <= add_ln703_116_fu_5068_p2; + ap_return_19_int_reg <= add_ln703_117_fu_5074_p2; + ap_return_1_int_reg <= add_ln703_99_fu_4935_p2; + ap_return_20_int_reg <= add_ln703_118_fu_5082_p2; + ap_return_21_int_reg <= add_ln703_119_fu_5091_p2; + ap_return_22_int_reg <= add_ln703_120_fu_5100_p2; + ap_return_23_int_reg <= add_ln703_121_fu_5109_p2; + ap_return_24_int_reg <= add_ln703_122_fu_5118_p2; + ap_return_25_int_reg <= add_ln703_123_fu_5127_p2; + ap_return_26_int_reg <= add_ln703_124_fu_5136_p2; + ap_return_27_int_reg <= add_ln703_125_fu_5145_p2; + ap_return_28_int_reg <= sext_ln703_3_fu_5160_p1; + ap_return_29_int_reg <= add_ln703_127_fu_5167_p2; + ap_return_2_int_reg <= add_ln703_100_fu_4944_p2; + ap_return_30_int_reg <= add_ln703_128_fu_5176_p2; + ap_return_31_int_reg <= add_ln703_129_fu_5182_p2; + ap_return_3_int_reg <= add_ln703_101_fu_4953_p2; + ap_return_4_int_reg <= add_ln703_102_fu_4962_p2; + ap_return_5_int_reg <= add_ln703_103_fu_4971_p2; + ap_return_6_int_reg <= add_ln703_104_fu_4977_p2; + ap_return_7_int_reg <= add_ln703_105_fu_4985_p2; + ap_return_8_int_reg <= add_ln703_106_fu_4994_p2; + ap_return_9_int_reg <= add_ln703_107_fu_5000_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce)) begin + data_0_V_read_int_reg <= data_0_V_read; + data_10_V_read_int_reg <= data_10_V_read; + data_11_V_read_int_reg <= data_11_V_read; + data_12_V_read_int_reg <= data_12_V_read; + data_13_V_read_int_reg <= data_13_V_read; + data_14_V_read_int_reg <= data_14_V_read; + data_15_V_read_int_reg <= data_15_V_read; + data_16_V_read_int_reg <= data_16_V_read; + data_17_V_read_int_reg <= data_17_V_read; + data_18_V_read_int_reg <= data_18_V_read; + data_19_V_read_int_reg <= data_19_V_read; + data_1_V_read_int_reg <= data_1_V_read; + data_20_V_read_int_reg <= data_20_V_read; + data_21_V_read_int_reg <= data_21_V_read; + data_22_V_read_int_reg <= data_22_V_read; + data_23_V_read_int_reg <= data_23_V_read; + data_24_V_read_int_reg <= data_24_V_read; + data_25_V_read_int_reg <= data_25_V_read; + data_26_V_read_int_reg <= data_26_V_read; + data_27_V_read_int_reg <= data_27_V_read; + data_28_V_read_int_reg <= data_28_V_read; + data_29_V_read_int_reg <= data_29_V_read; + data_2_V_read_int_reg <= data_2_V_read; + data_30_V_read_int_reg <= data_30_V_read; + data_31_V_read_int_reg <= data_31_V_read; + data_3_V_read_int_reg <= data_3_V_read; + data_4_V_read_int_reg <= data_4_V_read; + data_5_V_read_int_reg <= data_5_V_read; + data_6_V_read_int_reg <= data_6_V_read; + data_7_V_read_int_reg <= data_7_V_read; + data_8_V_read_int_reg <= data_8_V_read; + data_9_V_read_int_reg <= data_9_V_read; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + tmp_386_reg_5519 <= {{add_ln1118_2_fu_4602_p2[23:10]}}; + tmp_386_reg_5519_pp0_iter1_reg <= tmp_386_reg_5519; + trunc_ln708_10_reg_5589 <= {{grp_fu_448_p2[24:10]}}; + trunc_ln708_11_reg_5594 <= {{grp_fu_438_p2[25:10]}}; + trunc_ln708_12_reg_5599 <= {{grp_fu_443_p2[24:10]}}; + trunc_ln708_13_reg_5604 <= {{grp_fu_431_p2[24:10]}}; + trunc_ln708_14_reg_5609 <= {{grp_fu_428_p2[24:10]}}; + trunc_ln708_15_reg_5614 <= {{grp_fu_456_p2[24:10]}}; + trunc_ln708_16_reg_5619 <= {{grp_fu_455_p2[25:10]}}; + trunc_ln708_17_reg_5624 <= {{grp_fu_439_p2[25:10]}}; + trunc_ln708_18_reg_5629 <= {{grp_fu_433_p2[24:10]}}; + trunc_ln708_19_reg_5634 <= {{grp_fu_453_p2[25:10]}}; + trunc_ln708_1_reg_5544 <= {{grp_fu_442_p2[24:10]}}; + trunc_ln708_20_reg_5639 <= {{grp_fu_451_p2[24:10]}}; + trunc_ln708_21_reg_5644 <= {{grp_fu_430_p2[24:10]}}; + trunc_ln708_22_reg_5489 <= {{add_ln1118_fu_4502_p2[24:10]}}; + trunc_ln708_22_reg_5489_pp0_iter1_reg <= trunc_ln708_22_reg_5489; + trunc_ln708_23_reg_5649 <= {{grp_fu_447_p2[24:10]}}; + trunc_ln708_24_reg_5654 <= {{grp_fu_449_p2[24:10]}}; + trunc_ln708_25_reg_5659 <= {{grp_fu_441_p2[24:10]}}; + trunc_ln708_26_reg_5664 <= {{grp_fu_459_p2[24:10]}}; + trunc_ln708_27_reg_5514 <= {{add_ln1118_1_fu_4562_p2[24:10]}}; + trunc_ln708_27_reg_5514_pp0_iter1_reg <= trunc_ln708_27_reg_5514; + trunc_ln708_29_reg_5669 <= {{grp_fu_457_p2[24:10]}}; + trunc_ln708_2_reg_5549 <= {{grp_fu_446_p2[24:10]}}; + trunc_ln708_30_reg_5674 <= {{grp_fu_432_p2[24:10]}}; + trunc_ln708_31_reg_5679 <= {{grp_fu_440_p2[25:10]}}; + trunc_ln708_3_reg_5554 <= {{grp_fu_458_p2[24:10]}}; + trunc_ln708_4_reg_5559 <= {{grp_fu_444_p2[24:10]}}; + trunc_ln708_5_reg_5564 <= {{grp_fu_454_p2[24:10]}}; + trunc_ln708_6_reg_5569 <= {{grp_fu_437_p2[25:10]}}; + trunc_ln708_7_reg_5574 <= {{grp_fu_452_p2[24:10]}}; + trunc_ln708_8_reg_5579 <= {{grp_fu_436_p2[24:10]}}; + trunc_ln708_9_reg_5584 <= {{grp_fu_445_p2[25:10]}}; + trunc_ln_reg_5539 <= {{grp_fu_435_p2[24:10]}}; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_0 = ap_return_0_int_reg; + end else begin + ap_return_0 = add_ln703_fu_4926_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_1 = ap_return_1_int_reg; + end else begin + ap_return_1 = add_ln703_99_fu_4935_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_10 = ap_return_10_int_reg; + end else begin + ap_return_10 = add_ln703_108_fu_5008_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_11 = ap_return_11_int_reg; + end else begin + ap_return_11 = add_ln703_109_fu_5014_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_12 = ap_return_12_int_reg; + end else begin + ap_return_12 = add_ln703_110_fu_5022_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_13 = ap_return_13_int_reg; + end else begin + ap_return_13 = add_ln703_111_fu_5031_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_14 = ap_return_14_int_reg; + end else begin + ap_return_14 = add_ln703_112_fu_5040_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_15 = ap_return_15_int_reg; + end else begin + ap_return_15 = add_ln703_113_fu_5049_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_16 = ap_return_16_int_reg; + end else begin + ap_return_16 = add_ln703_114_fu_5055_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_17 = ap_return_17_int_reg; + end else begin + ap_return_17 = add_ln703_115_fu_5060_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_18 = ap_return_18_int_reg; + end else begin + ap_return_18 = add_ln703_116_fu_5068_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_19 = ap_return_19_int_reg; + end else begin + ap_return_19 = add_ln703_117_fu_5074_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_2 = ap_return_2_int_reg; + end else begin + ap_return_2 = add_ln703_100_fu_4944_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_20 = ap_return_20_int_reg; + end else begin + ap_return_20 = add_ln703_118_fu_5082_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_21 = ap_return_21_int_reg; + end else begin + ap_return_21 = add_ln703_119_fu_5091_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_22 = ap_return_22_int_reg; + end else begin + ap_return_22 = add_ln703_120_fu_5100_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_23 = ap_return_23_int_reg; + end else begin + ap_return_23 = add_ln703_121_fu_5109_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_24 = ap_return_24_int_reg; + end else begin + ap_return_24 = add_ln703_122_fu_5118_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_25 = ap_return_25_int_reg; + end else begin + ap_return_25 = add_ln703_123_fu_5127_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_26 = ap_return_26_int_reg; + end else begin + ap_return_26 = add_ln703_124_fu_5136_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_27 = ap_return_27_int_reg; + end else begin + ap_return_27 = add_ln703_125_fu_5145_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_28 = ap_return_28_int_reg; + end else begin + ap_return_28 = sext_ln703_3_fu_5160_p1; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_29 = ap_return_29_int_reg; + end else begin + ap_return_29 = add_ln703_127_fu_5167_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_3 = ap_return_3_int_reg; + end else begin + ap_return_3 = add_ln703_101_fu_4953_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_30 = ap_return_30_int_reg; + end else begin + ap_return_30 = add_ln703_128_fu_5176_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_31 = ap_return_31_int_reg; + end else begin + ap_return_31 = add_ln703_129_fu_5182_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_4 = ap_return_4_int_reg; + end else begin + ap_return_4 = add_ln703_102_fu_4962_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_5 = ap_return_5_int_reg; + end else begin + ap_return_5 = add_ln703_103_fu_4971_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_6 = ap_return_6_int_reg; + end else begin + ap_return_6 = add_ln703_104_fu_4977_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_7 = ap_return_7_int_reg; + end else begin + ap_return_7 = add_ln703_105_fu_4985_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_8 = ap_return_8_int_reg; + end else begin + ap_return_8 = add_ln703_106_fu_4994_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_9 = ap_return_9_int_reg; + end else begin + ap_return_9 = add_ln703_107_fu_5000_p2; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_428_ce = 1'b1; + end else begin + grp_fu_428_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_430_ce = 1'b1; + end else begin + grp_fu_430_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_431_ce = 1'b1; + end else begin + grp_fu_431_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_432_ce = 1'b1; + end else begin + grp_fu_432_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_433_ce = 1'b1; + end else begin + grp_fu_433_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_435_ce = 1'b1; + end else begin + grp_fu_435_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_436_ce = 1'b1; + end else begin + grp_fu_436_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_437_ce = 1'b1; + end else begin + grp_fu_437_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_438_ce = 1'b1; + end else begin + grp_fu_438_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_439_ce = 1'b1; + end else begin + grp_fu_439_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_440_ce = 1'b1; + end else begin + grp_fu_440_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_441_ce = 1'b1; + end else begin + grp_fu_441_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_442_ce = 1'b1; + end else begin + grp_fu_442_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_443_ce = 1'b1; + end else begin + grp_fu_443_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_444_ce = 1'b1; + end else begin + grp_fu_444_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_445_ce = 1'b1; + end else begin + grp_fu_445_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_446_ce = 1'b1; + end else begin + grp_fu_446_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_447_ce = 1'b1; + end else begin + grp_fu_447_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_448_ce = 1'b1; + end else begin + grp_fu_448_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_449_ce = 1'b1; + end else begin + grp_fu_449_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_451_ce = 1'b1; + end else begin + grp_fu_451_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_452_ce = 1'b1; + end else begin + grp_fu_452_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_453_ce = 1'b1; + end else begin + grp_fu_453_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_454_ce = 1'b1; + end else begin + grp_fu_454_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_455_ce = 1'b1; + end else begin + grp_fu_455_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_456_ce = 1'b1; + end else begin + grp_fu_456_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_457_ce = 1'b1; + end else begin + grp_fu_457_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_458_ce = 1'b1; + end else begin + grp_fu_458_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_459_ce = 1'b1; + end else begin + grp_fu_459_ce = 1'b0; + end +end + +assign add_ln1118_1_fu_4562_p2 = ((sext_ln1118_29_fu_4558_p1) + (sext_ln1118_28_fu_4546_p1)); + +assign add_ln1118_2_fu_4602_p2 = ((sext_ln1118_31_fu_4598_p1) + (sext_ln1118_30_fu_4586_p1)); + +assign add_ln1118_fu_4502_p2 = ((sext_ln1118_23_fu_4498_p1) + (sext_ln1118_22_fu_4486_p1)); + +assign add_ln703_100_fu_4944_p2 = ((sext_ln708_2_fu_4941_p1) + (16'd176)); + +assign add_ln703_101_fu_4953_p2 = ((sext_ln708_3_fu_4950_p1) + (16'd64535)); + +assign add_ln703_102_fu_4962_p2 = ((sext_ln708_4_fu_4959_p1) + (16'd65060)); + +assign add_ln703_103_fu_4971_p2 = ((sext_ln708_5_fu_4968_p1) + (16'd65037)); + +assign add_ln703_104_fu_4977_p2 = (trunc_ln708_6_reg_5569 + 16'd1387); + +assign add_ln703_105_fu_4985_p2 = ((sext_ln708_6_fu_4982_p1) + (16'd179)); + +assign add_ln703_106_fu_4994_p2 = ((sext_ln708_7_fu_4991_p1) + (16'd65351)); + +assign add_ln703_107_fu_5000_p2 = ((trunc_ln708_9_reg_5584) + (16'd64930)); + +assign add_ln703_108_fu_5008_p2 = ((sext_ln708_8_fu_5005_p1) + (16'd725)); + +assign add_ln703_109_fu_5014_p2 = ((trunc_ln708_11_reg_5594) + (16'd65311)); + +assign add_ln703_110_fu_5022_p2 = ((sext_ln708_9_fu_5019_p1) + (16'd419)); + +assign add_ln703_111_fu_5031_p2 = ((sext_ln708_10_fu_5028_p1) + (16'd64983)); + +assign add_ln703_112_fu_5040_p2 = ((sext_ln708_11_fu_5037_p1) + (16'd25)); + +assign add_ln703_113_fu_5049_p2 = ((sext_ln708_12_fu_5046_p1) + (16'd346)); + +assign add_ln703_114_fu_5055_p2 = (trunc_ln708_16_reg_5619 + 16'd474); + +assign add_ln703_115_fu_5060_p2 = ((trunc_ln708_17_reg_5624) + (16'd64364)); + +assign add_ln703_116_fu_5068_p2 = ((sext_ln708_13_fu_5065_p1) + (16'd65227)); + +assign add_ln703_117_fu_5074_p2 = (trunc_ln708_19_reg_5634 + 16'd881); + +assign add_ln703_118_fu_5082_p2 = ((sext_ln708_14_fu_5079_p1) + (16'd511)); + +assign add_ln703_119_fu_5091_p2 = ((sext_ln708_15_fu_5088_p1) + (16'd64887)); + +assign add_ln703_120_fu_5100_p2 = ((sext_ln708_16_fu_5097_p1) + (16'd65275)); + +assign add_ln703_121_fu_5109_p2 = ((sext_ln708_17_fu_5106_p1) + (16'd664)); + +assign add_ln703_122_fu_5118_p2 = ((sext_ln708_18_fu_5115_p1) + (16'd513)); + +assign add_ln703_123_fu_5127_p2 = ((sext_ln708_19_fu_5124_p1) + (16'd833)); + +assign add_ln703_124_fu_5136_p2 = ((sext_ln708_20_fu_5133_p1) + (16'd332)); + +assign add_ln703_125_fu_5145_p2 = ((sext_ln708_21_fu_5142_p1) + (16'd65271)); + +assign add_ln703_126_fu_5154_p2 = ((sext_ln703_fu_5151_p1) + (15'd32312)); + +assign add_ln703_127_fu_5167_p2 = ((sext_ln708_22_fu_5164_p1) + (16'd423)); + +assign add_ln703_128_fu_5176_p2 = ((sext_ln708_23_fu_5173_p1) + (16'd399)); + +assign add_ln703_129_fu_5182_p2 = ((trunc_ln708_31_reg_5679) + (16'd65410)); + +assign add_ln703_99_fu_4935_p2 = ((sext_ln708_1_fu_4932_p1) + (16'd64428)); + +assign add_ln703_fu_4926_p2 = ((sext_ln708_fu_4923_p1) + (16'd316)); + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign grp_fu_428_p1 = 9'd183; + +assign grp_fu_430_p1 = 9'd161; + +assign grp_fu_431_p1 = 9'd206; + +assign grp_fu_432_p1 = 9'd215; + +assign grp_fu_433_p1 = 9'd189; + +assign grp_fu_435_p1 = 9'd199; + +assign grp_fu_436_p1 = 9'd185; + +assign grp_fu_437_p1 = 10'd356; + +assign grp_fu_438_p1 = 10'd338; + +assign grp_fu_439_p1 = 10'd308; + +assign grp_fu_440_p1 = 10'd394; + +assign grp_fu_441_p1 = 9'd239; + +assign grp_fu_442_p1 = 9'd222; + +assign grp_fu_443_p1 = 9'd142; + +assign grp_fu_444_p1 = 9'd239; + +assign grp_fu_445_p1 = 10'd310; + +assign grp_fu_446_p1 = 9'd231; + +assign grp_fu_447_p1 = 9'd134; + +assign grp_fu_448_p1 = 9'd225; + +assign grp_fu_449_p1 = 9'd209; + +assign grp_fu_451_p1 = 9'd140; + +assign grp_fu_452_p1 = 9'd228; + +assign grp_fu_453_p1 = 10'd380; + +assign grp_fu_454_p1 = 9'd145; + +assign grp_fu_455_p1 = 10'd393; + +assign grp_fu_456_p1 = 9'd241; + +assign grp_fu_457_p1 = 9'd169; + +assign grp_fu_458_p1 = 9'd241; + +assign grp_fu_459_p1 = 9'd233; + +assign sext_ln1118_22_fu_4486_p0 = data_22_V_read_int_reg; + +assign sext_ln1118_22_fu_4486_p1 = sext_ln1118_22_fu_4486_p0; + +assign sext_ln1118_23_fu_4498_p1 = (shl_ln_fu_4490_p3); + +assign sext_ln1118_28_fu_4546_p1 = (shl_ln1118_1_fu_4538_p3); + +assign sext_ln1118_29_fu_4558_p1 = (shl_ln1118_2_fu_4550_p3); + +assign sext_ln1118_30_fu_4586_p1 = (shl_ln1118_3_fu_4578_p3); + +assign sext_ln1118_31_fu_4598_p1 = (shl_ln1118_4_fu_4590_p3); + +assign sext_ln703_3_fu_5160_p1 = (add_ln703_126_fu_5154_p2); + +assign sext_ln703_fu_5151_p1 = (tmp_386_reg_5519_pp0_iter1_reg); + +assign sext_ln708_10_fu_5028_p1 = (trunc_ln708_13_reg_5604); + +assign sext_ln708_11_fu_5037_p1 = (trunc_ln708_14_reg_5609); + +assign sext_ln708_12_fu_5046_p1 = (trunc_ln708_15_reg_5614); + +assign sext_ln708_13_fu_5065_p1 = (trunc_ln708_18_reg_5629); + +assign sext_ln708_14_fu_5079_p1 = (trunc_ln708_20_reg_5639); + +assign sext_ln708_15_fu_5088_p1 = (trunc_ln708_21_reg_5644); + +assign sext_ln708_16_fu_5097_p1 = (trunc_ln708_22_reg_5489_pp0_iter1_reg); + +assign sext_ln708_17_fu_5106_p1 = (trunc_ln708_23_reg_5649); + +assign sext_ln708_18_fu_5115_p1 = (trunc_ln708_24_reg_5654); + +assign sext_ln708_19_fu_5124_p1 = (trunc_ln708_25_reg_5659); + +assign sext_ln708_1_fu_4932_p1 = (trunc_ln708_1_reg_5544); + +assign sext_ln708_20_fu_5133_p1 = (trunc_ln708_26_reg_5664); + +assign sext_ln708_21_fu_5142_p1 = (trunc_ln708_27_reg_5514_pp0_iter1_reg); + +assign sext_ln708_22_fu_5164_p1 = (trunc_ln708_29_reg_5669); + +assign sext_ln708_23_fu_5173_p1 = (trunc_ln708_30_reg_5674); + +assign sext_ln708_2_fu_4941_p1 = (trunc_ln708_2_reg_5549); + +assign sext_ln708_3_fu_4950_p1 = (trunc_ln708_3_reg_5554); + +assign sext_ln708_4_fu_4959_p1 = (trunc_ln708_4_reg_5559); + +assign sext_ln708_5_fu_4968_p1 = (trunc_ln708_5_reg_5564); + +assign sext_ln708_6_fu_4982_p1 = (trunc_ln708_7_reg_5574); + +assign sext_ln708_7_fu_4991_p1 = (trunc_ln708_8_reg_5579); + +assign sext_ln708_8_fu_5005_p1 = (trunc_ln708_10_reg_5589); + +assign sext_ln708_9_fu_5019_p1 = (trunc_ln708_12_reg_5599); + +assign sext_ln708_fu_4923_p1 = (trunc_ln_reg_5539); + +assign shl_ln1118_1_fu_4538_p3 = {{data_27_V_read_int_reg}, {8'd0}}; + +assign shl_ln1118_2_fu_4550_p3 = {{data_27_V_read_int_reg}, {6'd0}}; + +assign shl_ln1118_3_fu_4578_p3 = {{data_28_V_read_int_reg}, {7'd0}}; + +assign shl_ln1118_4_fu_4590_p3 = {{data_28_V_read_int_reg}, {5'd0}}; + +assign shl_ln_fu_4490_p1 = data_22_V_read_int_reg; + +assign shl_ln_fu_4490_p3 = {{shl_ln_fu_4490_p1}, {8'd0}}; + +endmodule //normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0 ( + ap_clk, + ap_rst, + data_0_V_read, + data_1_V_read, + data_2_V_read, + data_3_V_read, + data_4_V_read, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3, + ap_return_4, + ap_ce +); + + +input ap_clk; +input ap_rst; +input [15:0] data_0_V_read; +input [15:0] data_1_V_read; +input [15:0] data_2_V_read; +input [15:0] data_3_V_read; +input [15:0] data_4_V_read; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; +output [15:0] ap_return_4; +input ap_ce; + +reg[15:0] ap_return_0; +reg[15:0] ap_return_1; +reg[15:0] ap_return_2; +reg[15:0] ap_return_3; +reg[15:0] ap_return_4; + +wire ap_block_state1_pp0_stage0_iter0; +wire ap_block_state2_pp0_stage0_iter1; +wire ap_block_state3_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [12:0] trunc_ln708_s_reg_362; +reg [12:0] trunc_ln708_s_reg_362_pp0_iter1_reg; +reg [14:0] trunc_ln_reg_382; +reg [14:0] trunc_ln708_1_reg_387; +reg [14:0] trunc_ln708_2_reg_392; +reg [14:0] trunc_ln708_3_reg_397; +wire [8:0] grp_fu_95_p1; +wire ap_block_pp0_stage0; +wire [8:0] grp_fu_96_p1; +wire [8:0] grp_fu_97_p1; +wire [8:0] grp_fu_98_p1; +wire [24:0] grp_fu_98_p2; +wire [24:0] grp_fu_96_p2; +wire [24:0] grp_fu_97_p2; +wire [24:0] grp_fu_95_p2; +wire [15:0] sext_ln708_fu_278_p1; +wire [13:0] sext_ln703_fu_287_p1; +wire [13:0] add_ln703_1_fu_290_p2; +wire [15:0] sext_ln708_1_fu_300_p1; +wire [15:0] sext_ln708_2_fu_309_p1; +wire [15:0] sext_ln708_3_fu_318_p1; +wire [15:0] add_ln703_fu_281_p2; +wire [15:0] sext_ln703_1_fu_296_p1; +wire [15:0] add_ln703_2_fu_303_p2; +wire [15:0] add_ln703_3_fu_312_p2; +wire [15:0] add_ln703_4_fu_321_p2; +reg grp_fu_95_ce; +reg grp_fu_96_ce; +reg grp_fu_97_ce; +reg grp_fu_98_ce; +reg ap_ce_reg; +reg [15:0] data_0_V_read_int_reg; +reg [15:0] data_1_V_read_int_reg; +reg [15:0] data_2_V_read_int_reg; +reg [15:0] data_3_V_read_int_reg; +reg [15:0] data_4_V_read_int_reg; +reg [15:0] ap_return_0_int_reg; +reg [15:0] ap_return_1_int_reg; +reg [15:0] ap_return_2_int_reg; +reg [15:0] ap_return_3_int_reg; +reg [15:0] ap_return_4_int_reg; + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U513( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_4_V_read_int_reg), + .din1(grp_fu_95_p1), + .ce(grp_fu_95_ce), + .dout(grp_fu_95_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U514( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_2_V_read_int_reg), + .din1(grp_fu_96_p1), + .ce(grp_fu_96_ce), + .dout(grp_fu_96_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U515( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_3_V_read_int_reg), + .din1(grp_fu_97_p1), + .ce(grp_fu_97_ce), + .dout(grp_fu_97_p2) +); + +myproject_mul_16s_9ns_25_2_0 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 25 )) +myproject_mul_16s_9ns_25_2_0_U516( + .clk(ap_clk), + .reset(ap_rst), + .din0(data_0_V_read_int_reg), + .din1(grp_fu_98_p1), + .ce(grp_fu_98_ce), + .dout(grp_fu_98_p2) +); + +always @ (posedge ap_clk) begin + ap_ce_reg <= ap_ce; +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce_reg)) begin + ap_return_0_int_reg <= add_ln703_fu_281_p2; + ap_return_1_int_reg <= sext_ln703_1_fu_296_p1; + ap_return_2_int_reg <= add_ln703_2_fu_303_p2; + ap_return_3_int_reg <= add_ln703_3_fu_312_p2; + ap_return_4_int_reg <= add_ln703_4_fu_321_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_ce)) begin + data_0_V_read_int_reg <= data_0_V_read; + data_1_V_read_int_reg <= data_1_V_read; + data_2_V_read_int_reg <= data_2_V_read; + data_3_V_read_int_reg <= data_3_V_read; + data_4_V_read_int_reg <= data_4_V_read; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + trunc_ln708_1_reg_387 <= {{grp_fu_96_p2[24:10]}}; + trunc_ln708_2_reg_392 <= {{grp_fu_97_p2[24:10]}}; + trunc_ln708_3_reg_397 <= {{grp_fu_95_p2[24:10]}}; + trunc_ln708_s_reg_362 <= {{data_1_V_read_int_reg[15:3]}}; + trunc_ln708_s_reg_362_pp0_iter1_reg <= trunc_ln708_s_reg_362; + trunc_ln_reg_382 <= {{grp_fu_98_p2[24:10]}}; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_0 = ap_return_0_int_reg; + end else begin + ap_return_0 = add_ln703_fu_281_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_1 = ap_return_1_int_reg; + end else begin + ap_return_1 = sext_ln703_1_fu_296_p1; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_2 = ap_return_2_int_reg; + end else begin + ap_return_2 = add_ln703_2_fu_303_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_3 = ap_return_3_int_reg; + end else begin + ap_return_3 = add_ln703_3_fu_312_p2; + end +end + +always @ (*) begin + if ((1'b0 == ap_ce_reg)) begin + ap_return_4 = ap_return_4_int_reg; + end else begin + ap_return_4 = add_ln703_4_fu_321_p2; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_95_ce = 1'b1; + end else begin + grp_fu_95_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_96_ce = 1'b1; + end else begin + grp_fu_96_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_97_ce = 1'b1; + end else begin + grp_fu_97_ce = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_ce_reg))) begin + grp_fu_98_ce = 1'b1; + end else begin + grp_fu_98_ce = 1'b0; + end +end + +assign add_ln703_1_fu_290_p2 = ((sext_ln703_fu_287_p1) + (14'd15560)); + +assign add_ln703_2_fu_303_p2 = ((sext_ln708_1_fu_300_p1) + (16'd64405)); + +assign add_ln703_3_fu_312_p2 = ((sext_ln708_2_fu_309_p1) + (16'd64656)); + +assign add_ln703_4_fu_321_p2 = ((sext_ln708_3_fu_318_p1) + (16'd65325)); + +assign add_ln703_fu_281_p2 = ((sext_ln708_fu_278_p1) + (16'd64860)); + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_state1_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign grp_fu_95_p1 = 9'd162; + +assign grp_fu_96_p1 = 9'd239; + +assign grp_fu_97_p1 = 9'd221; + +assign grp_fu_98_p1 = 9'd174; + +assign sext_ln703_1_fu_296_p1 = (add_ln703_1_fu_290_p2); + +assign sext_ln703_fu_287_p1 = (trunc_ln708_s_reg_362_pp0_iter1_reg); + +assign sext_ln708_1_fu_300_p1 = (trunc_ln708_1_reg_387); + +assign sext_ln708_2_fu_309_p1 = (trunc_ln708_2_reg_392); + +assign sext_ln708_3_fu_318_p1 = (trunc_ln708_3_reg_397); + +assign sext_ln708_fu_278_p1 = (trunc_ln_reg_382); + +endmodule //normalize_ap_fixed_ap_fixed_config16_0_0_0_0_0_0_0_0_0_0 +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module relu_max_ap_fixed_ap_fixed_1_relu1_config13_s ( + ap_ready, + data_0_V_read, + data_1_V_read, + data_2_V_read, + data_3_V_read, + data_4_V_read, + data_5_V_read, + data_6_V_read, + data_7_V_read, + data_8_V_read, + data_9_V_read, + data_10_V_read, + data_11_V_read, + data_12_V_read, + data_13_V_read, + data_14_V_read, + data_15_V_read, + data_16_V_read, + data_17_V_read, + data_18_V_read, + data_19_V_read, + data_20_V_read, + data_21_V_read, + data_22_V_read, + data_23_V_read, + data_24_V_read, + data_25_V_read, + data_26_V_read, + data_27_V_read, + data_28_V_read, + data_29_V_read, + data_30_V_read, + data_31_V_read, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3, + ap_return_4, + ap_return_5, + ap_return_6, + ap_return_7, + ap_return_8, + ap_return_9, + ap_return_10, + ap_return_11, + ap_return_12, + ap_return_13, + ap_return_14, + ap_return_15, + ap_return_16, + ap_return_17, + ap_return_18, + ap_return_19, + ap_return_20, + ap_return_21, + ap_return_22, + ap_return_23, + ap_return_24, + ap_return_25, + ap_return_26, + ap_return_27, + ap_return_28, + ap_return_29, + ap_return_30, + ap_return_31 +); + + +output ap_ready; +input [15:0] data_0_V_read; +input [15:0] data_1_V_read; +input [15:0] data_2_V_read; +input [15:0] data_3_V_read; +input [15:0] data_4_V_read; +input [15:0] data_5_V_read; +input [15:0] data_6_V_read; +input [15:0] data_7_V_read; +input [15:0] data_8_V_read; +input [15:0] data_9_V_read; +input [15:0] data_10_V_read; +input [15:0] data_11_V_read; +input [15:0] data_12_V_read; +input [15:0] data_13_V_read; +input [15:0] data_14_V_read; +input [15:0] data_15_V_read; +input [15:0] data_16_V_read; +input [15:0] data_17_V_read; +input [15:0] data_18_V_read; +input [15:0] data_19_V_read; +input [15:0] data_20_V_read; +input [15:0] data_21_V_read; +input [15:0] data_22_V_read; +input [15:0] data_23_V_read; +input [15:0] data_24_V_read; +input [15:0] data_25_V_read; +input [15:0] data_26_V_read; +input [15:0] data_27_V_read; +input [15:0] data_28_V_read; +input [15:0] data_29_V_read; +input [15:0] data_30_V_read; +input [15:0] data_31_V_read; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; +output [15:0] ap_return_4; +output [15:0] ap_return_5; +output [15:0] ap_return_6; +output [15:0] ap_return_7; +output [15:0] ap_return_8; +output [15:0] ap_return_9; +output [15:0] ap_return_10; +output [15:0] ap_return_11; +output [15:0] ap_return_12; +output [15:0] ap_return_13; +output [15:0] ap_return_14; +output [15:0] ap_return_15; +output [15:0] ap_return_16; +output [15:0] ap_return_17; +output [15:0] ap_return_18; +output [15:0] ap_return_19; +output [15:0] ap_return_20; +output [15:0] ap_return_21; +output [15:0] ap_return_22; +output [15:0] ap_return_23; +output [15:0] ap_return_24; +output [15:0] ap_return_25; +output [15:0] ap_return_26; +output [15:0] ap_return_27; +output [15:0] ap_return_28; +output [15:0] ap_return_29; +output [15:0] ap_return_30; +output [15:0] ap_return_31; + +wire [0:0] tmp_290_fu_302_p3; +wire [0:0] xor_ln1495_fu_310_p2; +wire [10:0] tmp_291_fu_316_p3; +wire [0:0] tmp_289_fu_288_p3; +wire [0:0] icmp_ln1494_fu_296_p2; +wire [0:0] or_ln1495_fu_328_p2; +wire [15:0] zext_ln1495_fu_324_p1; +wire [0:0] tmp_293_fu_356_p3; +wire [0:0] xor_ln1495_95_fu_364_p2; +wire [10:0] tmp_294_fu_370_p3; +wire [0:0] tmp_292_fu_342_p3; +wire [0:0] icmp_ln1494_1_fu_350_p2; +wire [0:0] or_ln1495_95_fu_382_p2; +wire [15:0] zext_ln1495_95_fu_378_p1; +wire [0:0] tmp_296_fu_410_p3; +wire [0:0] xor_ln1495_96_fu_418_p2; +wire [10:0] tmp_297_fu_424_p3; +wire [0:0] tmp_295_fu_396_p3; +wire [0:0] icmp_ln1494_2_fu_404_p2; +wire [0:0] or_ln1495_96_fu_436_p2; +wire [15:0] zext_ln1495_96_fu_432_p1; +wire [0:0] tmp_299_fu_464_p3; +wire [0:0] xor_ln1495_97_fu_472_p2; +wire [10:0] tmp_300_fu_478_p3; +wire [0:0] tmp_298_fu_450_p3; +wire [0:0] icmp_ln1494_3_fu_458_p2; +wire [0:0] or_ln1495_97_fu_490_p2; +wire [15:0] zext_ln1495_97_fu_486_p1; +wire [0:0] tmp_302_fu_518_p3; +wire [0:0] xor_ln1495_98_fu_526_p2; +wire [10:0] tmp_303_fu_532_p3; +wire [0:0] tmp_301_fu_504_p3; +wire [0:0] icmp_ln1494_4_fu_512_p2; +wire [0:0] or_ln1495_98_fu_544_p2; +wire [15:0] zext_ln1495_98_fu_540_p1; +wire [0:0] tmp_305_fu_572_p3; +wire [0:0] xor_ln1495_99_fu_580_p2; +wire [10:0] tmp_306_fu_586_p3; +wire [0:0] tmp_304_fu_558_p3; +wire [0:0] icmp_ln1494_5_fu_566_p2; +wire [0:0] or_ln1495_99_fu_598_p2; +wire [15:0] zext_ln1495_99_fu_594_p1; +wire [0:0] tmp_308_fu_626_p3; +wire [0:0] xor_ln1495_100_fu_634_p2; +wire [10:0] tmp_309_fu_640_p3; +wire [0:0] tmp_307_fu_612_p3; +wire [0:0] icmp_ln1494_6_fu_620_p2; +wire [0:0] or_ln1495_100_fu_652_p2; +wire [15:0] zext_ln1495_100_fu_648_p1; +wire [0:0] tmp_311_fu_680_p3; +wire [0:0] xor_ln1495_101_fu_688_p2; +wire [10:0] tmp_312_fu_694_p3; +wire [0:0] tmp_310_fu_666_p3; +wire [0:0] icmp_ln1494_7_fu_674_p2; +wire [0:0] or_ln1495_101_fu_706_p2; +wire [15:0] zext_ln1495_101_fu_702_p1; +wire [0:0] tmp_314_fu_734_p3; +wire [0:0] xor_ln1495_102_fu_742_p2; +wire [10:0] tmp_315_fu_748_p3; +wire [0:0] tmp_313_fu_720_p3; +wire [0:0] icmp_ln1494_8_fu_728_p2; +wire [0:0] or_ln1495_102_fu_760_p2; +wire [15:0] zext_ln1495_102_fu_756_p1; +wire [0:0] tmp_317_fu_788_p3; +wire [0:0] xor_ln1495_103_fu_796_p2; +wire [10:0] tmp_318_fu_802_p3; +wire [0:0] tmp_316_fu_774_p3; +wire [0:0] icmp_ln1494_9_fu_782_p2; +wire [0:0] or_ln1495_103_fu_814_p2; +wire [15:0] zext_ln1495_103_fu_810_p1; +wire [0:0] tmp_320_fu_842_p3; +wire [0:0] xor_ln1495_104_fu_850_p2; +wire [10:0] tmp_321_fu_856_p3; +wire [0:0] tmp_319_fu_828_p3; +wire [0:0] icmp_ln1494_10_fu_836_p2; +wire [0:0] or_ln1495_104_fu_868_p2; +wire [15:0] zext_ln1495_104_fu_864_p1; +wire [0:0] tmp_323_fu_896_p3; +wire [0:0] xor_ln1495_105_fu_904_p2; +wire [10:0] tmp_324_fu_910_p3; +wire [0:0] tmp_322_fu_882_p3; +wire [0:0] icmp_ln1494_11_fu_890_p2; +wire [0:0] or_ln1495_105_fu_922_p2; +wire [15:0] zext_ln1495_105_fu_918_p1; +wire [0:0] tmp_326_fu_950_p3; +wire [0:0] xor_ln1495_106_fu_958_p2; +wire [10:0] tmp_327_fu_964_p3; +wire [0:0] tmp_325_fu_936_p3; +wire [0:0] icmp_ln1494_12_fu_944_p2; +wire [0:0] or_ln1495_106_fu_976_p2; +wire [15:0] zext_ln1495_106_fu_972_p1; +wire [0:0] tmp_329_fu_1004_p3; +wire [0:0] xor_ln1495_107_fu_1012_p2; +wire [10:0] tmp_330_fu_1018_p3; +wire [0:0] tmp_328_fu_990_p3; +wire [0:0] icmp_ln1494_13_fu_998_p2; +wire [0:0] or_ln1495_107_fu_1030_p2; +wire [15:0] zext_ln1495_107_fu_1026_p1; +wire [0:0] tmp_332_fu_1058_p3; +wire [0:0] xor_ln1495_108_fu_1066_p2; +wire [10:0] tmp_333_fu_1072_p3; +wire [0:0] tmp_331_fu_1044_p3; +wire [0:0] icmp_ln1494_14_fu_1052_p2; +wire [0:0] or_ln1495_108_fu_1084_p2; +wire [15:0] zext_ln1495_108_fu_1080_p1; +wire [0:0] tmp_335_fu_1112_p3; +wire [0:0] xor_ln1495_109_fu_1120_p2; +wire [10:0] tmp_336_fu_1126_p3; +wire [0:0] tmp_334_fu_1098_p3; +wire [0:0] icmp_ln1494_15_fu_1106_p2; +wire [0:0] or_ln1495_109_fu_1138_p2; +wire [15:0] zext_ln1495_109_fu_1134_p1; +wire [0:0] tmp_338_fu_1166_p3; +wire [0:0] xor_ln1495_110_fu_1174_p2; +wire [10:0] tmp_339_fu_1180_p3; +wire [0:0] tmp_337_fu_1152_p3; +wire [0:0] icmp_ln1494_16_fu_1160_p2; +wire [0:0] or_ln1495_110_fu_1192_p2; +wire [15:0] zext_ln1495_110_fu_1188_p1; +wire [0:0] tmp_341_fu_1220_p3; +wire [0:0] xor_ln1495_111_fu_1228_p2; +wire [10:0] tmp_342_fu_1234_p3; +wire [0:0] tmp_340_fu_1206_p3; +wire [0:0] icmp_ln1494_17_fu_1214_p2; +wire [0:0] or_ln1495_111_fu_1246_p2; +wire [15:0] zext_ln1495_111_fu_1242_p1; +wire [0:0] tmp_344_fu_1274_p3; +wire [0:0] xor_ln1495_112_fu_1282_p2; +wire [10:0] tmp_345_fu_1288_p3; +wire [0:0] tmp_343_fu_1260_p3; +wire [0:0] icmp_ln1494_18_fu_1268_p2; +wire [0:0] or_ln1495_112_fu_1300_p2; +wire [15:0] zext_ln1495_112_fu_1296_p1; +wire [0:0] tmp_347_fu_1328_p3; +wire [0:0] xor_ln1495_113_fu_1336_p2; +wire [10:0] tmp_348_fu_1342_p3; +wire [0:0] tmp_346_fu_1314_p3; +wire [0:0] icmp_ln1494_19_fu_1322_p2; +wire [0:0] or_ln1495_113_fu_1354_p2; +wire [15:0] zext_ln1495_113_fu_1350_p1; +wire [0:0] tmp_350_fu_1382_p3; +wire [0:0] xor_ln1495_114_fu_1390_p2; +wire [10:0] tmp_351_fu_1396_p3; +wire [0:0] tmp_349_fu_1368_p3; +wire [0:0] icmp_ln1494_20_fu_1376_p2; +wire [0:0] or_ln1495_114_fu_1408_p2; +wire [15:0] zext_ln1495_114_fu_1404_p1; +wire [0:0] tmp_353_fu_1436_p3; +wire [0:0] xor_ln1495_115_fu_1444_p2; +wire [10:0] tmp_354_fu_1450_p3; +wire [0:0] tmp_352_fu_1422_p3; +wire [0:0] icmp_ln1494_21_fu_1430_p2; +wire [0:0] or_ln1495_115_fu_1462_p2; +wire [15:0] zext_ln1495_115_fu_1458_p1; +wire [0:0] tmp_356_fu_1490_p3; +wire [0:0] xor_ln1495_116_fu_1498_p2; +wire [10:0] tmp_357_fu_1504_p3; +wire [0:0] tmp_355_fu_1476_p3; +wire [0:0] icmp_ln1494_22_fu_1484_p2; +wire [0:0] or_ln1495_116_fu_1516_p2; +wire [15:0] zext_ln1495_116_fu_1512_p1; +wire [0:0] tmp_359_fu_1544_p3; +wire [0:0] xor_ln1495_117_fu_1552_p2; +wire [10:0] tmp_360_fu_1558_p3; +wire [0:0] tmp_358_fu_1530_p3; +wire [0:0] icmp_ln1494_23_fu_1538_p2; +wire [0:0] or_ln1495_117_fu_1570_p2; +wire [15:0] zext_ln1495_117_fu_1566_p1; +wire [0:0] tmp_362_fu_1598_p3; +wire [0:0] xor_ln1495_118_fu_1606_p2; +wire [10:0] tmp_363_fu_1612_p3; +wire [0:0] tmp_361_fu_1584_p3; +wire [0:0] icmp_ln1494_24_fu_1592_p2; +wire [0:0] or_ln1495_118_fu_1624_p2; +wire [15:0] zext_ln1495_118_fu_1620_p1; +wire [0:0] tmp_365_fu_1652_p3; +wire [0:0] xor_ln1495_119_fu_1660_p2; +wire [10:0] tmp_366_fu_1666_p3; +wire [0:0] tmp_364_fu_1638_p3; +wire [0:0] icmp_ln1494_25_fu_1646_p2; +wire [0:0] or_ln1495_119_fu_1678_p2; +wire [15:0] zext_ln1495_119_fu_1674_p1; +wire [0:0] tmp_368_fu_1706_p3; +wire [0:0] xor_ln1495_120_fu_1714_p2; +wire [10:0] tmp_369_fu_1720_p3; +wire [0:0] tmp_367_fu_1692_p3; +wire [0:0] icmp_ln1494_26_fu_1700_p2; +wire [0:0] or_ln1495_120_fu_1732_p2; +wire [15:0] zext_ln1495_120_fu_1728_p1; +wire [0:0] tmp_371_fu_1760_p3; +wire [0:0] xor_ln1495_121_fu_1768_p2; +wire [10:0] tmp_372_fu_1774_p3; +wire [0:0] tmp_370_fu_1746_p3; +wire [0:0] icmp_ln1494_27_fu_1754_p2; +wire [0:0] or_ln1495_121_fu_1786_p2; +wire [15:0] zext_ln1495_121_fu_1782_p1; +wire [0:0] tmp_374_fu_1814_p3; +wire [0:0] xor_ln1495_122_fu_1822_p2; +wire [10:0] tmp_375_fu_1828_p3; +wire [0:0] tmp_373_fu_1800_p3; +wire [0:0] icmp_ln1494_28_fu_1808_p2; +wire [0:0] or_ln1495_122_fu_1840_p2; +wire [15:0] zext_ln1495_122_fu_1836_p1; +wire [0:0] tmp_377_fu_1868_p3; +wire [0:0] xor_ln1495_123_fu_1876_p2; +wire [10:0] tmp_378_fu_1882_p3; +wire [0:0] tmp_376_fu_1854_p3; +wire [0:0] icmp_ln1494_29_fu_1862_p2; +wire [0:0] or_ln1495_123_fu_1894_p2; +wire [15:0] zext_ln1495_123_fu_1890_p1; +wire [0:0] tmp_380_fu_1922_p3; +wire [0:0] xor_ln1495_124_fu_1930_p2; +wire [10:0] tmp_381_fu_1936_p3; +wire [0:0] tmp_379_fu_1908_p3; +wire [0:0] icmp_ln1494_30_fu_1916_p2; +wire [0:0] or_ln1495_124_fu_1948_p2; +wire [15:0] zext_ln1495_124_fu_1944_p1; +wire [0:0] tmp_383_fu_1976_p3; +wire [0:0] xor_ln1495_125_fu_1984_p2; +wire [10:0] tmp_384_fu_1990_p3; +wire [0:0] tmp_382_fu_1962_p3; +wire [0:0] icmp_ln1494_31_fu_1970_p2; +wire [0:0] or_ln1495_125_fu_2002_p2; +wire [15:0] zext_ln1495_125_fu_1998_p1; +wire [15:0] select_ln1495_fu_334_p3; +wire [15:0] select_ln1495_95_fu_388_p3; +wire [15:0] select_ln1495_96_fu_442_p3; +wire [15:0] select_ln1495_97_fu_496_p3; +wire [15:0] select_ln1495_98_fu_550_p3; +wire [15:0] select_ln1495_99_fu_604_p3; +wire [15:0] select_ln1495_100_fu_658_p3; +wire [15:0] select_ln1495_101_fu_712_p3; +wire [15:0] select_ln1495_102_fu_766_p3; +wire [15:0] select_ln1495_103_fu_820_p3; +wire [15:0] select_ln1495_104_fu_874_p3; +wire [15:0] select_ln1495_105_fu_928_p3; +wire [15:0] select_ln1495_106_fu_982_p3; +wire [15:0] select_ln1495_107_fu_1036_p3; +wire [15:0] select_ln1495_108_fu_1090_p3; +wire [15:0] select_ln1495_109_fu_1144_p3; +wire [15:0] select_ln1495_110_fu_1198_p3; +wire [15:0] select_ln1495_111_fu_1252_p3; +wire [15:0] select_ln1495_112_fu_1306_p3; +wire [15:0] select_ln1495_113_fu_1360_p3; +wire [15:0] select_ln1495_114_fu_1414_p3; +wire [15:0] select_ln1495_115_fu_1468_p3; +wire [15:0] select_ln1495_116_fu_1522_p3; +wire [15:0] select_ln1495_117_fu_1576_p3; +wire [15:0] select_ln1495_118_fu_1630_p3; +wire [15:0] select_ln1495_119_fu_1684_p3; +wire [15:0] select_ln1495_120_fu_1738_p3; +wire [15:0] select_ln1495_121_fu_1792_p3; +wire [15:0] select_ln1495_122_fu_1846_p3; +wire [15:0] select_ln1495_123_fu_1900_p3; +wire [15:0] select_ln1495_124_fu_1954_p3; +wire [15:0] select_ln1495_125_fu_2008_p3; + +assign ap_ready = 1'b1; + +assign ap_return_0 = select_ln1495_fu_334_p3; + +assign ap_return_1 = select_ln1495_95_fu_388_p3; + +assign ap_return_10 = select_ln1495_104_fu_874_p3; + +assign ap_return_11 = select_ln1495_105_fu_928_p3; + +assign ap_return_12 = select_ln1495_106_fu_982_p3; + +assign ap_return_13 = select_ln1495_107_fu_1036_p3; + +assign ap_return_14 = select_ln1495_108_fu_1090_p3; + +assign ap_return_15 = select_ln1495_109_fu_1144_p3; + +assign ap_return_16 = select_ln1495_110_fu_1198_p3; + +assign ap_return_17 = select_ln1495_111_fu_1252_p3; + +assign ap_return_18 = select_ln1495_112_fu_1306_p3; + +assign ap_return_19 = select_ln1495_113_fu_1360_p3; + +assign ap_return_2 = select_ln1495_96_fu_442_p3; + +assign ap_return_20 = select_ln1495_114_fu_1414_p3; + +assign ap_return_21 = select_ln1495_115_fu_1468_p3; + +assign ap_return_22 = select_ln1495_116_fu_1522_p3; + +assign ap_return_23 = select_ln1495_117_fu_1576_p3; + +assign ap_return_24 = select_ln1495_118_fu_1630_p3; + +assign ap_return_25 = select_ln1495_119_fu_1684_p3; + +assign ap_return_26 = select_ln1495_120_fu_1738_p3; + +assign ap_return_27 = select_ln1495_121_fu_1792_p3; + +assign ap_return_28 = select_ln1495_122_fu_1846_p3; + +assign ap_return_29 = select_ln1495_123_fu_1900_p3; + +assign ap_return_3 = select_ln1495_97_fu_496_p3; + +assign ap_return_30 = select_ln1495_124_fu_1954_p3; + +assign ap_return_31 = select_ln1495_125_fu_2008_p3; + +assign ap_return_4 = select_ln1495_98_fu_550_p3; + +assign ap_return_5 = select_ln1495_99_fu_604_p3; + +assign ap_return_6 = select_ln1495_100_fu_658_p3; + +assign ap_return_7 = select_ln1495_101_fu_712_p3; + +assign ap_return_8 = select_ln1495_102_fu_766_p3; + +assign ap_return_9 = select_ln1495_103_fu_820_p3; + +assign icmp_ln1494_10_fu_836_p2 = (((data_10_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_11_fu_890_p2 = (((data_11_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_12_fu_944_p2 = (((data_12_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_13_fu_998_p2 = (((data_13_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_14_fu_1052_p2 = (((data_14_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_15_fu_1106_p2 = (((data_15_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_16_fu_1160_p2 = (((data_16_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_17_fu_1214_p2 = (((data_17_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_18_fu_1268_p2 = (((data_18_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_19_fu_1322_p2 = (((data_19_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_1_fu_350_p2 = (((data_1_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_20_fu_1376_p2 = (((data_20_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_21_fu_1430_p2 = (((data_21_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_22_fu_1484_p2 = (((data_22_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_23_fu_1538_p2 = (((data_23_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_24_fu_1592_p2 = (((data_24_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_25_fu_1646_p2 = (((data_25_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_26_fu_1700_p2 = (((data_26_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_27_fu_1754_p2 = (((data_27_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_28_fu_1808_p2 = (((data_28_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_29_fu_1862_p2 = (((data_29_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_2_fu_404_p2 = (((data_2_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_30_fu_1916_p2 = (((data_30_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_31_fu_1970_p2 = (((data_31_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_3_fu_458_p2 = (((data_3_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_4_fu_512_p2 = (((data_4_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_5_fu_566_p2 = (((data_5_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_6_fu_620_p2 = (((data_6_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_7_fu_674_p2 = (((data_7_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_8_fu_728_p2 = (((data_8_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_9_fu_782_p2 = (((data_9_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_fu_296_p2 = (((data_0_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign or_ln1495_100_fu_652_p2 = (tmp_307_fu_612_p3 | icmp_ln1494_6_fu_620_p2); + +assign or_ln1495_101_fu_706_p2 = (tmp_310_fu_666_p3 | icmp_ln1494_7_fu_674_p2); + +assign or_ln1495_102_fu_760_p2 = (tmp_313_fu_720_p3 | icmp_ln1494_8_fu_728_p2); + +assign or_ln1495_103_fu_814_p2 = (tmp_316_fu_774_p3 | icmp_ln1494_9_fu_782_p2); + +assign or_ln1495_104_fu_868_p2 = (tmp_319_fu_828_p3 | icmp_ln1494_10_fu_836_p2); + +assign or_ln1495_105_fu_922_p2 = (tmp_322_fu_882_p3 | icmp_ln1494_11_fu_890_p2); + +assign or_ln1495_106_fu_976_p2 = (tmp_325_fu_936_p3 | icmp_ln1494_12_fu_944_p2); + +assign or_ln1495_107_fu_1030_p2 = (tmp_328_fu_990_p3 | icmp_ln1494_13_fu_998_p2); + +assign or_ln1495_108_fu_1084_p2 = (tmp_331_fu_1044_p3 | icmp_ln1494_14_fu_1052_p2); + +assign or_ln1495_109_fu_1138_p2 = (tmp_334_fu_1098_p3 | icmp_ln1494_15_fu_1106_p2); + +assign or_ln1495_110_fu_1192_p2 = (tmp_337_fu_1152_p3 | icmp_ln1494_16_fu_1160_p2); + +assign or_ln1495_111_fu_1246_p2 = (tmp_340_fu_1206_p3 | icmp_ln1494_17_fu_1214_p2); + +assign or_ln1495_112_fu_1300_p2 = (tmp_343_fu_1260_p3 | icmp_ln1494_18_fu_1268_p2); + +assign or_ln1495_113_fu_1354_p2 = (tmp_346_fu_1314_p3 | icmp_ln1494_19_fu_1322_p2); + +assign or_ln1495_114_fu_1408_p2 = (tmp_349_fu_1368_p3 | icmp_ln1494_20_fu_1376_p2); + +assign or_ln1495_115_fu_1462_p2 = (tmp_352_fu_1422_p3 | icmp_ln1494_21_fu_1430_p2); + +assign or_ln1495_116_fu_1516_p2 = (tmp_355_fu_1476_p3 | icmp_ln1494_22_fu_1484_p2); + +assign or_ln1495_117_fu_1570_p2 = (tmp_358_fu_1530_p3 | icmp_ln1494_23_fu_1538_p2); + +assign or_ln1495_118_fu_1624_p2 = (tmp_361_fu_1584_p3 | icmp_ln1494_24_fu_1592_p2); + +assign or_ln1495_119_fu_1678_p2 = (tmp_364_fu_1638_p3 | icmp_ln1494_25_fu_1646_p2); + +assign or_ln1495_120_fu_1732_p2 = (tmp_367_fu_1692_p3 | icmp_ln1494_26_fu_1700_p2); + +assign or_ln1495_121_fu_1786_p2 = (tmp_370_fu_1746_p3 | icmp_ln1494_27_fu_1754_p2); + +assign or_ln1495_122_fu_1840_p2 = (tmp_373_fu_1800_p3 | icmp_ln1494_28_fu_1808_p2); + +assign or_ln1495_123_fu_1894_p2 = (tmp_376_fu_1854_p3 | icmp_ln1494_29_fu_1862_p2); + +assign or_ln1495_124_fu_1948_p2 = (tmp_379_fu_1908_p3 | icmp_ln1494_30_fu_1916_p2); + +assign or_ln1495_125_fu_2002_p2 = (tmp_382_fu_1962_p3 | icmp_ln1494_31_fu_1970_p2); + +assign or_ln1495_95_fu_382_p2 = (tmp_292_fu_342_p3 | icmp_ln1494_1_fu_350_p2); + +assign or_ln1495_96_fu_436_p2 = (tmp_295_fu_396_p3 | icmp_ln1494_2_fu_404_p2); + +assign or_ln1495_97_fu_490_p2 = (tmp_298_fu_450_p3 | icmp_ln1494_3_fu_458_p2); + +assign or_ln1495_98_fu_544_p2 = (tmp_301_fu_504_p3 | icmp_ln1494_4_fu_512_p2); + +assign or_ln1495_99_fu_598_p2 = (tmp_304_fu_558_p3 | icmp_ln1494_5_fu_566_p2); + +assign or_ln1495_fu_328_p2 = (tmp_289_fu_288_p3 | icmp_ln1494_fu_296_p2); + +assign select_ln1495_100_fu_658_p3 = ((or_ln1495_100_fu_652_p2[0:0] == 1'b1) ? zext_ln1495_100_fu_648_p1 : data_6_V_read); + +assign select_ln1495_101_fu_712_p3 = ((or_ln1495_101_fu_706_p2[0:0] == 1'b1) ? zext_ln1495_101_fu_702_p1 : data_7_V_read); + +assign select_ln1495_102_fu_766_p3 = ((or_ln1495_102_fu_760_p2[0:0] == 1'b1) ? zext_ln1495_102_fu_756_p1 : data_8_V_read); + +assign select_ln1495_103_fu_820_p3 = ((or_ln1495_103_fu_814_p2[0:0] == 1'b1) ? zext_ln1495_103_fu_810_p1 : data_9_V_read); + +assign select_ln1495_104_fu_874_p3 = ((or_ln1495_104_fu_868_p2[0:0] == 1'b1) ? zext_ln1495_104_fu_864_p1 : data_10_V_read); + +assign select_ln1495_105_fu_928_p3 = ((or_ln1495_105_fu_922_p2[0:0] == 1'b1) ? zext_ln1495_105_fu_918_p1 : data_11_V_read); + +assign select_ln1495_106_fu_982_p3 = ((or_ln1495_106_fu_976_p2[0:0] == 1'b1) ? zext_ln1495_106_fu_972_p1 : data_12_V_read); + +assign select_ln1495_107_fu_1036_p3 = ((or_ln1495_107_fu_1030_p2[0:0] == 1'b1) ? zext_ln1495_107_fu_1026_p1 : data_13_V_read); + +assign select_ln1495_108_fu_1090_p3 = ((or_ln1495_108_fu_1084_p2[0:0] == 1'b1) ? zext_ln1495_108_fu_1080_p1 : data_14_V_read); + +assign select_ln1495_109_fu_1144_p3 = ((or_ln1495_109_fu_1138_p2[0:0] == 1'b1) ? zext_ln1495_109_fu_1134_p1 : data_15_V_read); + +assign select_ln1495_110_fu_1198_p3 = ((or_ln1495_110_fu_1192_p2[0:0] == 1'b1) ? zext_ln1495_110_fu_1188_p1 : data_16_V_read); + +assign select_ln1495_111_fu_1252_p3 = ((or_ln1495_111_fu_1246_p2[0:0] == 1'b1) ? zext_ln1495_111_fu_1242_p1 : data_17_V_read); + +assign select_ln1495_112_fu_1306_p3 = ((or_ln1495_112_fu_1300_p2[0:0] == 1'b1) ? zext_ln1495_112_fu_1296_p1 : data_18_V_read); + +assign select_ln1495_113_fu_1360_p3 = ((or_ln1495_113_fu_1354_p2[0:0] == 1'b1) ? zext_ln1495_113_fu_1350_p1 : data_19_V_read); + +assign select_ln1495_114_fu_1414_p3 = ((or_ln1495_114_fu_1408_p2[0:0] == 1'b1) ? zext_ln1495_114_fu_1404_p1 : data_20_V_read); + +assign select_ln1495_115_fu_1468_p3 = ((or_ln1495_115_fu_1462_p2[0:0] == 1'b1) ? zext_ln1495_115_fu_1458_p1 : data_21_V_read); + +assign select_ln1495_116_fu_1522_p3 = ((or_ln1495_116_fu_1516_p2[0:0] == 1'b1) ? zext_ln1495_116_fu_1512_p1 : data_22_V_read); + +assign select_ln1495_117_fu_1576_p3 = ((or_ln1495_117_fu_1570_p2[0:0] == 1'b1) ? zext_ln1495_117_fu_1566_p1 : data_23_V_read); + +assign select_ln1495_118_fu_1630_p3 = ((or_ln1495_118_fu_1624_p2[0:0] == 1'b1) ? zext_ln1495_118_fu_1620_p1 : data_24_V_read); + +assign select_ln1495_119_fu_1684_p3 = ((or_ln1495_119_fu_1678_p2[0:0] == 1'b1) ? zext_ln1495_119_fu_1674_p1 : data_25_V_read); + +assign select_ln1495_120_fu_1738_p3 = ((or_ln1495_120_fu_1732_p2[0:0] == 1'b1) ? zext_ln1495_120_fu_1728_p1 : data_26_V_read); + +assign select_ln1495_121_fu_1792_p3 = ((or_ln1495_121_fu_1786_p2[0:0] == 1'b1) ? zext_ln1495_121_fu_1782_p1 : data_27_V_read); + +assign select_ln1495_122_fu_1846_p3 = ((or_ln1495_122_fu_1840_p2[0:0] == 1'b1) ? zext_ln1495_122_fu_1836_p1 : data_28_V_read); + +assign select_ln1495_123_fu_1900_p3 = ((or_ln1495_123_fu_1894_p2[0:0] == 1'b1) ? zext_ln1495_123_fu_1890_p1 : data_29_V_read); + +assign select_ln1495_124_fu_1954_p3 = ((or_ln1495_124_fu_1948_p2[0:0] == 1'b1) ? zext_ln1495_124_fu_1944_p1 : data_30_V_read); + +assign select_ln1495_125_fu_2008_p3 = ((or_ln1495_125_fu_2002_p2[0:0] == 1'b1) ? zext_ln1495_125_fu_1998_p1 : data_31_V_read); + +assign select_ln1495_95_fu_388_p3 = ((or_ln1495_95_fu_382_p2[0:0] == 1'b1) ? zext_ln1495_95_fu_378_p1 : data_1_V_read); + +assign select_ln1495_96_fu_442_p3 = ((or_ln1495_96_fu_436_p2[0:0] == 1'b1) ? zext_ln1495_96_fu_432_p1 : data_2_V_read); + +assign select_ln1495_97_fu_496_p3 = ((or_ln1495_97_fu_490_p2[0:0] == 1'b1) ? zext_ln1495_97_fu_486_p1 : data_3_V_read); + +assign select_ln1495_98_fu_550_p3 = ((or_ln1495_98_fu_544_p2[0:0] == 1'b1) ? zext_ln1495_98_fu_540_p1 : data_4_V_read); + +assign select_ln1495_99_fu_604_p3 = ((or_ln1495_99_fu_598_p2[0:0] == 1'b1) ? zext_ln1495_99_fu_594_p1 : data_5_V_read); + +assign select_ln1495_fu_334_p3 = ((or_ln1495_fu_328_p2[0:0] == 1'b1) ? zext_ln1495_fu_324_p1 : data_0_V_read); + +assign tmp_289_fu_288_p3 = data_0_V_read[32'd15]; + +assign tmp_290_fu_302_p3 = data_0_V_read[32'd15]; + +assign tmp_291_fu_316_p3 = {{xor_ln1495_fu_310_p2}, {10'd0}}; + +assign tmp_292_fu_342_p3 = data_1_V_read[32'd15]; + +assign tmp_293_fu_356_p3 = data_1_V_read[32'd15]; + +assign tmp_294_fu_370_p3 = {{xor_ln1495_95_fu_364_p2}, {10'd0}}; + +assign tmp_295_fu_396_p3 = data_2_V_read[32'd15]; + +assign tmp_296_fu_410_p3 = data_2_V_read[32'd15]; + +assign tmp_297_fu_424_p3 = {{xor_ln1495_96_fu_418_p2}, {10'd0}}; + +assign tmp_298_fu_450_p3 = data_3_V_read[32'd15]; + +assign tmp_299_fu_464_p3 = data_3_V_read[32'd15]; + +assign tmp_300_fu_478_p3 = {{xor_ln1495_97_fu_472_p2}, {10'd0}}; + +assign tmp_301_fu_504_p3 = data_4_V_read[32'd15]; + +assign tmp_302_fu_518_p3 = data_4_V_read[32'd15]; + +assign tmp_303_fu_532_p3 = {{xor_ln1495_98_fu_526_p2}, {10'd0}}; + +assign tmp_304_fu_558_p3 = data_5_V_read[32'd15]; + +assign tmp_305_fu_572_p3 = data_5_V_read[32'd15]; + +assign tmp_306_fu_586_p3 = {{xor_ln1495_99_fu_580_p2}, {10'd0}}; + +assign tmp_307_fu_612_p3 = data_6_V_read[32'd15]; + +assign tmp_308_fu_626_p3 = data_6_V_read[32'd15]; + +assign tmp_309_fu_640_p3 = {{xor_ln1495_100_fu_634_p2}, {10'd0}}; + +assign tmp_310_fu_666_p3 = data_7_V_read[32'd15]; + +assign tmp_311_fu_680_p3 = data_7_V_read[32'd15]; + +assign tmp_312_fu_694_p3 = {{xor_ln1495_101_fu_688_p2}, {10'd0}}; + +assign tmp_313_fu_720_p3 = data_8_V_read[32'd15]; + +assign tmp_314_fu_734_p3 = data_8_V_read[32'd15]; + +assign tmp_315_fu_748_p3 = {{xor_ln1495_102_fu_742_p2}, {10'd0}}; + +assign tmp_316_fu_774_p3 = data_9_V_read[32'd15]; + +assign tmp_317_fu_788_p3 = data_9_V_read[32'd15]; + +assign tmp_318_fu_802_p3 = {{xor_ln1495_103_fu_796_p2}, {10'd0}}; + +assign tmp_319_fu_828_p3 = data_10_V_read[32'd15]; + +assign tmp_320_fu_842_p3 = data_10_V_read[32'd15]; + +assign tmp_321_fu_856_p3 = {{xor_ln1495_104_fu_850_p2}, {10'd0}}; + +assign tmp_322_fu_882_p3 = data_11_V_read[32'd15]; + +assign tmp_323_fu_896_p3 = data_11_V_read[32'd15]; + +assign tmp_324_fu_910_p3 = {{xor_ln1495_105_fu_904_p2}, {10'd0}}; + +assign tmp_325_fu_936_p3 = data_12_V_read[32'd15]; + +assign tmp_326_fu_950_p3 = data_12_V_read[32'd15]; + +assign tmp_327_fu_964_p3 = {{xor_ln1495_106_fu_958_p2}, {10'd0}}; + +assign tmp_328_fu_990_p3 = data_13_V_read[32'd15]; + +assign tmp_329_fu_1004_p3 = data_13_V_read[32'd15]; + +assign tmp_330_fu_1018_p3 = {{xor_ln1495_107_fu_1012_p2}, {10'd0}}; + +assign tmp_331_fu_1044_p3 = data_14_V_read[32'd15]; + +assign tmp_332_fu_1058_p3 = data_14_V_read[32'd15]; + +assign tmp_333_fu_1072_p3 = {{xor_ln1495_108_fu_1066_p2}, {10'd0}}; + +assign tmp_334_fu_1098_p3 = data_15_V_read[32'd15]; + +assign tmp_335_fu_1112_p3 = data_15_V_read[32'd15]; + +assign tmp_336_fu_1126_p3 = {{xor_ln1495_109_fu_1120_p2}, {10'd0}}; + +assign tmp_337_fu_1152_p3 = data_16_V_read[32'd15]; + +assign tmp_338_fu_1166_p3 = data_16_V_read[32'd15]; + +assign tmp_339_fu_1180_p3 = {{xor_ln1495_110_fu_1174_p2}, {10'd0}}; + +assign tmp_340_fu_1206_p3 = data_17_V_read[32'd15]; + +assign tmp_341_fu_1220_p3 = data_17_V_read[32'd15]; + +assign tmp_342_fu_1234_p3 = {{xor_ln1495_111_fu_1228_p2}, {10'd0}}; + +assign tmp_343_fu_1260_p3 = data_18_V_read[32'd15]; + +assign tmp_344_fu_1274_p3 = data_18_V_read[32'd15]; + +assign tmp_345_fu_1288_p3 = {{xor_ln1495_112_fu_1282_p2}, {10'd0}}; + +assign tmp_346_fu_1314_p3 = data_19_V_read[32'd15]; + +assign tmp_347_fu_1328_p3 = data_19_V_read[32'd15]; + +assign tmp_348_fu_1342_p3 = {{xor_ln1495_113_fu_1336_p2}, {10'd0}}; + +assign tmp_349_fu_1368_p3 = data_20_V_read[32'd15]; + +assign tmp_350_fu_1382_p3 = data_20_V_read[32'd15]; + +assign tmp_351_fu_1396_p3 = {{xor_ln1495_114_fu_1390_p2}, {10'd0}}; + +assign tmp_352_fu_1422_p3 = data_21_V_read[32'd15]; + +assign tmp_353_fu_1436_p3 = data_21_V_read[32'd15]; + +assign tmp_354_fu_1450_p3 = {{xor_ln1495_115_fu_1444_p2}, {10'd0}}; + +assign tmp_355_fu_1476_p3 = data_22_V_read[32'd15]; + +assign tmp_356_fu_1490_p3 = data_22_V_read[32'd15]; + +assign tmp_357_fu_1504_p3 = {{xor_ln1495_116_fu_1498_p2}, {10'd0}}; + +assign tmp_358_fu_1530_p3 = data_23_V_read[32'd15]; + +assign tmp_359_fu_1544_p3 = data_23_V_read[32'd15]; + +assign tmp_360_fu_1558_p3 = {{xor_ln1495_117_fu_1552_p2}, {10'd0}}; + +assign tmp_361_fu_1584_p3 = data_24_V_read[32'd15]; + +assign tmp_362_fu_1598_p3 = data_24_V_read[32'd15]; + +assign tmp_363_fu_1612_p3 = {{xor_ln1495_118_fu_1606_p2}, {10'd0}}; + +assign tmp_364_fu_1638_p3 = data_25_V_read[32'd15]; + +assign tmp_365_fu_1652_p3 = data_25_V_read[32'd15]; + +assign tmp_366_fu_1666_p3 = {{xor_ln1495_119_fu_1660_p2}, {10'd0}}; + +assign tmp_367_fu_1692_p3 = data_26_V_read[32'd15]; + +assign tmp_368_fu_1706_p3 = data_26_V_read[32'd15]; + +assign tmp_369_fu_1720_p3 = {{xor_ln1495_120_fu_1714_p2}, {10'd0}}; + +assign tmp_370_fu_1746_p3 = data_27_V_read[32'd15]; + +assign tmp_371_fu_1760_p3 = data_27_V_read[32'd15]; + +assign tmp_372_fu_1774_p3 = {{xor_ln1495_121_fu_1768_p2}, {10'd0}}; + +assign tmp_373_fu_1800_p3 = data_28_V_read[32'd15]; + +assign tmp_374_fu_1814_p3 = data_28_V_read[32'd15]; + +assign tmp_375_fu_1828_p3 = {{xor_ln1495_122_fu_1822_p2}, {10'd0}}; + +assign tmp_376_fu_1854_p3 = data_29_V_read[32'd15]; + +assign tmp_377_fu_1868_p3 = data_29_V_read[32'd15]; + +assign tmp_378_fu_1882_p3 = {{xor_ln1495_123_fu_1876_p2}, {10'd0}}; + +assign tmp_379_fu_1908_p3 = data_30_V_read[32'd15]; + +assign tmp_380_fu_1922_p3 = data_30_V_read[32'd15]; + +assign tmp_381_fu_1936_p3 = {{xor_ln1495_124_fu_1930_p2}, {10'd0}}; + +assign tmp_382_fu_1962_p3 = data_31_V_read[32'd15]; + +assign tmp_383_fu_1976_p3 = data_31_V_read[32'd15]; + +assign tmp_384_fu_1990_p3 = {{xor_ln1495_125_fu_1984_p2}, {10'd0}}; + +assign xor_ln1495_100_fu_634_p2 = (tmp_308_fu_626_p3 ^ 1'd1); + +assign xor_ln1495_101_fu_688_p2 = (tmp_311_fu_680_p3 ^ 1'd1); + +assign xor_ln1495_102_fu_742_p2 = (tmp_314_fu_734_p3 ^ 1'd1); + +assign xor_ln1495_103_fu_796_p2 = (tmp_317_fu_788_p3 ^ 1'd1); + +assign xor_ln1495_104_fu_850_p2 = (tmp_320_fu_842_p3 ^ 1'd1); + +assign xor_ln1495_105_fu_904_p2 = (tmp_323_fu_896_p3 ^ 1'd1); + +assign xor_ln1495_106_fu_958_p2 = (tmp_326_fu_950_p3 ^ 1'd1); + +assign xor_ln1495_107_fu_1012_p2 = (tmp_329_fu_1004_p3 ^ 1'd1); + +assign xor_ln1495_108_fu_1066_p2 = (tmp_332_fu_1058_p3 ^ 1'd1); + +assign xor_ln1495_109_fu_1120_p2 = (tmp_335_fu_1112_p3 ^ 1'd1); + +assign xor_ln1495_110_fu_1174_p2 = (tmp_338_fu_1166_p3 ^ 1'd1); + +assign xor_ln1495_111_fu_1228_p2 = (tmp_341_fu_1220_p3 ^ 1'd1); + +assign xor_ln1495_112_fu_1282_p2 = (tmp_344_fu_1274_p3 ^ 1'd1); + +assign xor_ln1495_113_fu_1336_p2 = (tmp_347_fu_1328_p3 ^ 1'd1); + +assign xor_ln1495_114_fu_1390_p2 = (tmp_350_fu_1382_p3 ^ 1'd1); + +assign xor_ln1495_115_fu_1444_p2 = (tmp_353_fu_1436_p3 ^ 1'd1); + +assign xor_ln1495_116_fu_1498_p2 = (tmp_356_fu_1490_p3 ^ 1'd1); + +assign xor_ln1495_117_fu_1552_p2 = (tmp_359_fu_1544_p3 ^ 1'd1); + +assign xor_ln1495_118_fu_1606_p2 = (tmp_362_fu_1598_p3 ^ 1'd1); + +assign xor_ln1495_119_fu_1660_p2 = (tmp_365_fu_1652_p3 ^ 1'd1); + +assign xor_ln1495_120_fu_1714_p2 = (tmp_368_fu_1706_p3 ^ 1'd1); + +assign xor_ln1495_121_fu_1768_p2 = (tmp_371_fu_1760_p3 ^ 1'd1); + +assign xor_ln1495_122_fu_1822_p2 = (tmp_374_fu_1814_p3 ^ 1'd1); + +assign xor_ln1495_123_fu_1876_p2 = (tmp_377_fu_1868_p3 ^ 1'd1); + +assign xor_ln1495_124_fu_1930_p2 = (tmp_380_fu_1922_p3 ^ 1'd1); + +assign xor_ln1495_125_fu_1984_p2 = (tmp_383_fu_1976_p3 ^ 1'd1); + +assign xor_ln1495_95_fu_364_p2 = (tmp_293_fu_356_p3 ^ 1'd1); + +assign xor_ln1495_96_fu_418_p2 = (tmp_296_fu_410_p3 ^ 1'd1); + +assign xor_ln1495_97_fu_472_p2 = (tmp_299_fu_464_p3 ^ 1'd1); + +assign xor_ln1495_98_fu_526_p2 = (tmp_302_fu_518_p3 ^ 1'd1); + +assign xor_ln1495_99_fu_580_p2 = (tmp_305_fu_572_p3 ^ 1'd1); + +assign xor_ln1495_fu_310_p2 = (tmp_290_fu_302_p3 ^ 1'd1); + +assign zext_ln1495_100_fu_648_p1 = tmp_309_fu_640_p3; + +assign zext_ln1495_101_fu_702_p1 = tmp_312_fu_694_p3; + +assign zext_ln1495_102_fu_756_p1 = tmp_315_fu_748_p3; + +assign zext_ln1495_103_fu_810_p1 = tmp_318_fu_802_p3; + +assign zext_ln1495_104_fu_864_p1 = tmp_321_fu_856_p3; + +assign zext_ln1495_105_fu_918_p1 = tmp_324_fu_910_p3; + +assign zext_ln1495_106_fu_972_p1 = tmp_327_fu_964_p3; + +assign zext_ln1495_107_fu_1026_p1 = tmp_330_fu_1018_p3; + +assign zext_ln1495_108_fu_1080_p1 = tmp_333_fu_1072_p3; + +assign zext_ln1495_109_fu_1134_p1 = tmp_336_fu_1126_p3; + +assign zext_ln1495_110_fu_1188_p1 = tmp_339_fu_1180_p3; + +assign zext_ln1495_111_fu_1242_p1 = tmp_342_fu_1234_p3; + +assign zext_ln1495_112_fu_1296_p1 = tmp_345_fu_1288_p3; + +assign zext_ln1495_113_fu_1350_p1 = tmp_348_fu_1342_p3; + +assign zext_ln1495_114_fu_1404_p1 = tmp_351_fu_1396_p3; + +assign zext_ln1495_115_fu_1458_p1 = tmp_354_fu_1450_p3; + +assign zext_ln1495_116_fu_1512_p1 = tmp_357_fu_1504_p3; + +assign zext_ln1495_117_fu_1566_p1 = tmp_360_fu_1558_p3; + +assign zext_ln1495_118_fu_1620_p1 = tmp_363_fu_1612_p3; + +assign zext_ln1495_119_fu_1674_p1 = tmp_366_fu_1666_p3; + +assign zext_ln1495_120_fu_1728_p1 = tmp_369_fu_1720_p3; + +assign zext_ln1495_121_fu_1782_p1 = tmp_372_fu_1774_p3; + +assign zext_ln1495_122_fu_1836_p1 = tmp_375_fu_1828_p3; + +assign zext_ln1495_123_fu_1890_p1 = tmp_378_fu_1882_p3; + +assign zext_ln1495_124_fu_1944_p1 = tmp_381_fu_1936_p3; + +assign zext_ln1495_125_fu_1998_p1 = tmp_384_fu_1990_p3; + +assign zext_ln1495_95_fu_378_p1 = tmp_294_fu_370_p3; + +assign zext_ln1495_96_fu_432_p1 = tmp_297_fu_424_p3; + +assign zext_ln1495_97_fu_486_p1 = tmp_300_fu_478_p3; + +assign zext_ln1495_98_fu_540_p1 = tmp_303_fu_532_p3; + +assign zext_ln1495_99_fu_594_p1 = tmp_306_fu_586_p3; + +assign zext_ln1495_fu_324_p1 = tmp_291_fu_316_p3; + +endmodule //relu_max_ap_fixed_ap_fixed_1_relu1_config13_s +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module relu_max_ap_fixed_ap_fixed_1_relu1_config5_s ( + ap_ready, + data_0_V_read, + data_1_V_read, + data_2_V_read, + data_3_V_read, + data_4_V_read, + data_5_V_read, + data_6_V_read, + data_7_V_read, + data_8_V_read, + data_9_V_read, + data_10_V_read, + data_11_V_read, + data_12_V_read, + data_13_V_read, + data_14_V_read, + data_15_V_read, + data_16_V_read, + data_17_V_read, + data_18_V_read, + data_19_V_read, + data_20_V_read, + data_21_V_read, + data_22_V_read, + data_23_V_read, + data_24_V_read, + data_25_V_read, + data_26_V_read, + data_27_V_read, + data_28_V_read, + data_29_V_read, + data_30_V_read, + data_31_V_read, + data_32_V_read, + data_33_V_read, + data_34_V_read, + data_35_V_read, + data_36_V_read, + data_37_V_read, + data_38_V_read, + data_39_V_read, + data_40_V_read, + data_41_V_read, + data_42_V_read, + data_43_V_read, + data_44_V_read, + data_45_V_read, + data_46_V_read, + data_47_V_read, + data_48_V_read, + data_49_V_read, + data_50_V_read, + data_51_V_read, + data_52_V_read, + data_53_V_read, + data_54_V_read, + data_55_V_read, + data_56_V_read, + data_57_V_read, + data_58_V_read, + data_59_V_read, + data_60_V_read, + data_61_V_read, + data_62_V_read, + data_63_V_read, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3, + ap_return_4, + ap_return_5, + ap_return_6, + ap_return_7, + ap_return_8, + ap_return_9, + ap_return_10, + ap_return_11, + ap_return_12, + ap_return_13, + ap_return_14, + ap_return_15, + ap_return_16, + ap_return_17, + ap_return_18, + ap_return_19, + ap_return_20, + ap_return_21, + ap_return_22, + ap_return_23, + ap_return_24, + ap_return_25, + ap_return_26, + ap_return_27, + ap_return_28, + ap_return_29, + ap_return_30, + ap_return_31, + ap_return_32, + ap_return_33, + ap_return_34, + ap_return_35, + ap_return_36, + ap_return_37, + ap_return_38, + ap_return_39, + ap_return_40, + ap_return_41, + ap_return_42, + ap_return_43, + ap_return_44, + ap_return_45, + ap_return_46, + ap_return_47, + ap_return_48, + ap_return_49, + ap_return_50, + ap_return_51, + ap_return_52, + ap_return_53, + ap_return_54, + ap_return_55, + ap_return_56, + ap_return_57, + ap_return_58, + ap_return_59, + ap_return_60, + ap_return_61, + ap_return_62, + ap_return_63 +); + + +output ap_ready; +input [15:0] data_0_V_read; +input [15:0] data_1_V_read; +input [15:0] data_2_V_read; +input [15:0] data_3_V_read; +input [15:0] data_4_V_read; +input [15:0] data_5_V_read; +input [15:0] data_6_V_read; +input [15:0] data_7_V_read; +input [15:0] data_8_V_read; +input [15:0] data_9_V_read; +input [15:0] data_10_V_read; +input [15:0] data_11_V_read; +input [15:0] data_12_V_read; +input [15:0] data_13_V_read; +input [15:0] data_14_V_read; +input [15:0] data_15_V_read; +input [15:0] data_16_V_read; +input [15:0] data_17_V_read; +input [15:0] data_18_V_read; +input [15:0] data_19_V_read; +input [15:0] data_20_V_read; +input [15:0] data_21_V_read; +input [15:0] data_22_V_read; +input [15:0] data_23_V_read; +input [15:0] data_24_V_read; +input [15:0] data_25_V_read; +input [15:0] data_26_V_read; +input [15:0] data_27_V_read; +input [15:0] data_28_V_read; +input [15:0] data_29_V_read; +input [15:0] data_30_V_read; +input [15:0] data_31_V_read; +input [15:0] data_32_V_read; +input [15:0] data_33_V_read; +input [15:0] data_34_V_read; +input [15:0] data_35_V_read; +input [15:0] data_36_V_read; +input [15:0] data_37_V_read; +input [15:0] data_38_V_read; +input [15:0] data_39_V_read; +input [15:0] data_40_V_read; +input [15:0] data_41_V_read; +input [15:0] data_42_V_read; +input [15:0] data_43_V_read; +input [15:0] data_44_V_read; +input [15:0] data_45_V_read; +input [15:0] data_46_V_read; +input [15:0] data_47_V_read; +input [15:0] data_48_V_read; +input [15:0] data_49_V_read; +input [15:0] data_50_V_read; +input [15:0] data_51_V_read; +input [15:0] data_52_V_read; +input [15:0] data_53_V_read; +input [15:0] data_54_V_read; +input [15:0] data_55_V_read; +input [15:0] data_56_V_read; +input [15:0] data_57_V_read; +input [15:0] data_58_V_read; +input [15:0] data_59_V_read; +input [15:0] data_60_V_read; +input [15:0] data_61_V_read; +input [15:0] data_62_V_read; +input [15:0] data_63_V_read; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; +output [15:0] ap_return_4; +output [15:0] ap_return_5; +output [15:0] ap_return_6; +output [15:0] ap_return_7; +output [15:0] ap_return_8; +output [15:0] ap_return_9; +output [15:0] ap_return_10; +output [15:0] ap_return_11; +output [15:0] ap_return_12; +output [15:0] ap_return_13; +output [15:0] ap_return_14; +output [15:0] ap_return_15; +output [15:0] ap_return_16; +output [15:0] ap_return_17; +output [15:0] ap_return_18; +output [15:0] ap_return_19; +output [15:0] ap_return_20; +output [15:0] ap_return_21; +output [15:0] ap_return_22; +output [15:0] ap_return_23; +output [15:0] ap_return_24; +output [15:0] ap_return_25; +output [15:0] ap_return_26; +output [15:0] ap_return_27; +output [15:0] ap_return_28; +output [15:0] ap_return_29; +output [15:0] ap_return_30; +output [15:0] ap_return_31; +output [15:0] ap_return_32; +output [15:0] ap_return_33; +output [15:0] ap_return_34; +output [15:0] ap_return_35; +output [15:0] ap_return_36; +output [15:0] ap_return_37; +output [15:0] ap_return_38; +output [15:0] ap_return_39; +output [15:0] ap_return_40; +output [15:0] ap_return_41; +output [15:0] ap_return_42; +output [15:0] ap_return_43; +output [15:0] ap_return_44; +output [15:0] ap_return_45; +output [15:0] ap_return_46; +output [15:0] ap_return_47; +output [15:0] ap_return_48; +output [15:0] ap_return_49; +output [15:0] ap_return_50; +output [15:0] ap_return_51; +output [15:0] ap_return_52; +output [15:0] ap_return_53; +output [15:0] ap_return_54; +output [15:0] ap_return_55; +output [15:0] ap_return_56; +output [15:0] ap_return_57; +output [15:0] ap_return_58; +output [15:0] ap_return_59; +output [15:0] ap_return_60; +output [15:0] ap_return_61; +output [15:0] ap_return_62; +output [15:0] ap_return_63; + +wire [0:0] tmp_98_fu_558_p3; +wire [0:0] xor_ln1495_fu_566_p2; +wire [10:0] tmp_99_fu_572_p3; +wire [0:0] tmp_97_fu_544_p3; +wire [0:0] icmp_ln1494_fu_552_p2; +wire [0:0] or_ln1495_fu_584_p2; +wire [15:0] zext_ln1495_fu_580_p1; +wire [0:0] tmp_101_fu_612_p3; +wire [0:0] xor_ln1495_32_fu_620_p2; +wire [10:0] tmp_102_fu_626_p3; +wire [0:0] tmp_100_fu_598_p3; +wire [0:0] icmp_ln1494_1_fu_606_p2; +wire [0:0] or_ln1495_32_fu_638_p2; +wire [15:0] zext_ln1495_32_fu_634_p1; +wire [0:0] tmp_104_fu_666_p3; +wire [0:0] xor_ln1495_33_fu_674_p2; +wire [10:0] tmp_105_fu_680_p3; +wire [0:0] tmp_103_fu_652_p3; +wire [0:0] icmp_ln1494_2_fu_660_p2; +wire [0:0] or_ln1495_33_fu_692_p2; +wire [15:0] zext_ln1495_33_fu_688_p1; +wire [0:0] tmp_107_fu_720_p3; +wire [0:0] xor_ln1495_34_fu_728_p2; +wire [10:0] tmp_108_fu_734_p3; +wire [0:0] tmp_106_fu_706_p3; +wire [0:0] icmp_ln1494_3_fu_714_p2; +wire [0:0] or_ln1495_34_fu_746_p2; +wire [15:0] zext_ln1495_34_fu_742_p1; +wire [0:0] tmp_110_fu_774_p3; +wire [0:0] xor_ln1495_35_fu_782_p2; +wire [10:0] tmp_111_fu_788_p3; +wire [0:0] tmp_109_fu_760_p3; +wire [0:0] icmp_ln1494_4_fu_768_p2; +wire [0:0] or_ln1495_35_fu_800_p2; +wire [15:0] zext_ln1495_35_fu_796_p1; +wire [0:0] tmp_113_fu_828_p3; +wire [0:0] xor_ln1495_36_fu_836_p2; +wire [10:0] tmp_114_fu_842_p3; +wire [0:0] tmp_112_fu_814_p3; +wire [0:0] icmp_ln1494_5_fu_822_p2; +wire [0:0] or_ln1495_36_fu_854_p2; +wire [15:0] zext_ln1495_36_fu_850_p1; +wire [0:0] tmp_116_fu_882_p3; +wire [0:0] xor_ln1495_37_fu_890_p2; +wire [10:0] tmp_117_fu_896_p3; +wire [0:0] tmp_115_fu_868_p3; +wire [0:0] icmp_ln1494_6_fu_876_p2; +wire [0:0] or_ln1495_37_fu_908_p2; +wire [15:0] zext_ln1495_37_fu_904_p1; +wire [0:0] tmp_119_fu_936_p3; +wire [0:0] xor_ln1495_38_fu_944_p2; +wire [10:0] tmp_120_fu_950_p3; +wire [0:0] tmp_118_fu_922_p3; +wire [0:0] icmp_ln1494_7_fu_930_p2; +wire [0:0] or_ln1495_38_fu_962_p2; +wire [15:0] zext_ln1495_38_fu_958_p1; +wire [0:0] tmp_122_fu_990_p3; +wire [0:0] xor_ln1495_39_fu_998_p2; +wire [10:0] tmp_123_fu_1004_p3; +wire [0:0] tmp_121_fu_976_p3; +wire [0:0] icmp_ln1494_8_fu_984_p2; +wire [0:0] or_ln1495_39_fu_1016_p2; +wire [15:0] zext_ln1495_39_fu_1012_p1; +wire [0:0] tmp_125_fu_1044_p3; +wire [0:0] xor_ln1495_40_fu_1052_p2; +wire [10:0] tmp_126_fu_1058_p3; +wire [0:0] tmp_124_fu_1030_p3; +wire [0:0] icmp_ln1494_9_fu_1038_p2; +wire [0:0] or_ln1495_40_fu_1070_p2; +wire [15:0] zext_ln1495_40_fu_1066_p1; +wire [0:0] tmp_128_fu_1098_p3; +wire [0:0] xor_ln1495_41_fu_1106_p2; +wire [10:0] tmp_129_fu_1112_p3; +wire [0:0] tmp_127_fu_1084_p3; +wire [0:0] icmp_ln1494_10_fu_1092_p2; +wire [0:0] or_ln1495_41_fu_1124_p2; +wire [15:0] zext_ln1495_41_fu_1120_p1; +wire [0:0] tmp_131_fu_1152_p3; +wire [0:0] xor_ln1495_42_fu_1160_p2; +wire [10:0] tmp_132_fu_1166_p3; +wire [0:0] tmp_130_fu_1138_p3; +wire [0:0] icmp_ln1494_11_fu_1146_p2; +wire [0:0] or_ln1495_42_fu_1178_p2; +wire [15:0] zext_ln1495_42_fu_1174_p1; +wire [0:0] tmp_134_fu_1206_p3; +wire [0:0] xor_ln1495_43_fu_1214_p2; +wire [10:0] tmp_135_fu_1220_p3; +wire [0:0] tmp_133_fu_1192_p3; +wire [0:0] icmp_ln1494_12_fu_1200_p2; +wire [0:0] or_ln1495_43_fu_1232_p2; +wire [15:0] zext_ln1495_43_fu_1228_p1; +wire [0:0] tmp_137_fu_1260_p3; +wire [0:0] xor_ln1495_44_fu_1268_p2; +wire [10:0] tmp_138_fu_1274_p3; +wire [0:0] tmp_136_fu_1246_p3; +wire [0:0] icmp_ln1494_13_fu_1254_p2; +wire [0:0] or_ln1495_44_fu_1286_p2; +wire [15:0] zext_ln1495_44_fu_1282_p1; +wire [0:0] tmp_140_fu_1314_p3; +wire [0:0] xor_ln1495_45_fu_1322_p2; +wire [10:0] tmp_141_fu_1328_p3; +wire [0:0] tmp_139_fu_1300_p3; +wire [0:0] icmp_ln1494_14_fu_1308_p2; +wire [0:0] or_ln1495_45_fu_1340_p2; +wire [15:0] zext_ln1495_45_fu_1336_p1; +wire [0:0] tmp_143_fu_1368_p3; +wire [0:0] xor_ln1495_46_fu_1376_p2; +wire [10:0] tmp_144_fu_1382_p3; +wire [0:0] tmp_142_fu_1354_p3; +wire [0:0] icmp_ln1494_15_fu_1362_p2; +wire [0:0] or_ln1495_46_fu_1394_p2; +wire [15:0] zext_ln1495_46_fu_1390_p1; +wire [0:0] tmp_146_fu_1422_p3; +wire [0:0] xor_ln1495_47_fu_1430_p2; +wire [10:0] tmp_147_fu_1436_p3; +wire [0:0] tmp_145_fu_1408_p3; +wire [0:0] icmp_ln1494_16_fu_1416_p2; +wire [0:0] or_ln1495_47_fu_1448_p2; +wire [15:0] zext_ln1495_47_fu_1444_p1; +wire [0:0] tmp_149_fu_1476_p3; +wire [0:0] xor_ln1495_48_fu_1484_p2; +wire [10:0] tmp_150_fu_1490_p3; +wire [0:0] tmp_148_fu_1462_p3; +wire [0:0] icmp_ln1494_17_fu_1470_p2; +wire [0:0] or_ln1495_48_fu_1502_p2; +wire [15:0] zext_ln1495_48_fu_1498_p1; +wire [0:0] tmp_152_fu_1530_p3; +wire [0:0] xor_ln1495_49_fu_1538_p2; +wire [10:0] tmp_153_fu_1544_p3; +wire [0:0] tmp_151_fu_1516_p3; +wire [0:0] icmp_ln1494_18_fu_1524_p2; +wire [0:0] or_ln1495_49_fu_1556_p2; +wire [15:0] zext_ln1495_49_fu_1552_p1; +wire [0:0] tmp_155_fu_1584_p3; +wire [0:0] xor_ln1495_50_fu_1592_p2; +wire [10:0] tmp_156_fu_1598_p3; +wire [0:0] tmp_154_fu_1570_p3; +wire [0:0] icmp_ln1494_19_fu_1578_p2; +wire [0:0] or_ln1495_50_fu_1610_p2; +wire [15:0] zext_ln1495_50_fu_1606_p1; +wire [0:0] tmp_158_fu_1638_p3; +wire [0:0] xor_ln1495_51_fu_1646_p2; +wire [10:0] tmp_159_fu_1652_p3; +wire [0:0] tmp_157_fu_1624_p3; +wire [0:0] icmp_ln1494_20_fu_1632_p2; +wire [0:0] or_ln1495_51_fu_1664_p2; +wire [15:0] zext_ln1495_51_fu_1660_p1; +wire [0:0] tmp_161_fu_1692_p3; +wire [0:0] xor_ln1495_52_fu_1700_p2; +wire [10:0] tmp_162_fu_1706_p3; +wire [0:0] tmp_160_fu_1678_p3; +wire [0:0] icmp_ln1494_21_fu_1686_p2; +wire [0:0] or_ln1495_52_fu_1718_p2; +wire [15:0] zext_ln1495_52_fu_1714_p1; +wire [0:0] tmp_164_fu_1746_p3; +wire [0:0] xor_ln1495_53_fu_1754_p2; +wire [10:0] tmp_165_fu_1760_p3; +wire [0:0] tmp_163_fu_1732_p3; +wire [0:0] icmp_ln1494_22_fu_1740_p2; +wire [0:0] or_ln1495_53_fu_1772_p2; +wire [15:0] zext_ln1495_53_fu_1768_p1; +wire [0:0] tmp_167_fu_1800_p3; +wire [0:0] xor_ln1495_54_fu_1808_p2; +wire [10:0] tmp_168_fu_1814_p3; +wire [0:0] tmp_166_fu_1786_p3; +wire [0:0] icmp_ln1494_23_fu_1794_p2; +wire [0:0] or_ln1495_54_fu_1826_p2; +wire [15:0] zext_ln1495_54_fu_1822_p1; +wire [0:0] tmp_170_fu_1854_p3; +wire [0:0] xor_ln1495_55_fu_1862_p2; +wire [10:0] tmp_171_fu_1868_p3; +wire [0:0] tmp_169_fu_1840_p3; +wire [0:0] icmp_ln1494_24_fu_1848_p2; +wire [0:0] or_ln1495_55_fu_1880_p2; +wire [15:0] zext_ln1495_55_fu_1876_p1; +wire [0:0] tmp_173_fu_1908_p3; +wire [0:0] xor_ln1495_56_fu_1916_p2; +wire [10:0] tmp_174_fu_1922_p3; +wire [0:0] tmp_172_fu_1894_p3; +wire [0:0] icmp_ln1494_25_fu_1902_p2; +wire [0:0] or_ln1495_56_fu_1934_p2; +wire [15:0] zext_ln1495_56_fu_1930_p1; +wire [0:0] tmp_176_fu_1962_p3; +wire [0:0] xor_ln1495_57_fu_1970_p2; +wire [10:0] tmp_177_fu_1976_p3; +wire [0:0] tmp_175_fu_1948_p3; +wire [0:0] icmp_ln1494_26_fu_1956_p2; +wire [0:0] or_ln1495_57_fu_1988_p2; +wire [15:0] zext_ln1495_57_fu_1984_p1; +wire [0:0] tmp_179_fu_2016_p3; +wire [0:0] xor_ln1495_58_fu_2024_p2; +wire [10:0] tmp_180_fu_2030_p3; +wire [0:0] tmp_178_fu_2002_p3; +wire [0:0] icmp_ln1494_27_fu_2010_p2; +wire [0:0] or_ln1495_58_fu_2042_p2; +wire [15:0] zext_ln1495_58_fu_2038_p1; +wire [0:0] tmp_182_fu_2070_p3; +wire [0:0] xor_ln1495_59_fu_2078_p2; +wire [10:0] tmp_183_fu_2084_p3; +wire [0:0] tmp_181_fu_2056_p3; +wire [0:0] icmp_ln1494_28_fu_2064_p2; +wire [0:0] or_ln1495_59_fu_2096_p2; +wire [15:0] zext_ln1495_59_fu_2092_p1; +wire [0:0] tmp_185_fu_2124_p3; +wire [0:0] xor_ln1495_60_fu_2132_p2; +wire [10:0] tmp_186_fu_2138_p3; +wire [0:0] tmp_184_fu_2110_p3; +wire [0:0] icmp_ln1494_29_fu_2118_p2; +wire [0:0] or_ln1495_60_fu_2150_p2; +wire [15:0] zext_ln1495_60_fu_2146_p1; +wire [0:0] tmp_188_fu_2178_p3; +wire [0:0] xor_ln1495_61_fu_2186_p2; +wire [10:0] tmp_189_fu_2192_p3; +wire [0:0] tmp_187_fu_2164_p3; +wire [0:0] icmp_ln1494_30_fu_2172_p2; +wire [0:0] or_ln1495_61_fu_2204_p2; +wire [15:0] zext_ln1495_61_fu_2200_p1; +wire [0:0] tmp_191_fu_2232_p3; +wire [0:0] xor_ln1495_62_fu_2240_p2; +wire [10:0] tmp_192_fu_2246_p3; +wire [0:0] tmp_190_fu_2218_p3; +wire [0:0] icmp_ln1494_31_fu_2226_p2; +wire [0:0] or_ln1495_62_fu_2258_p2; +wire [15:0] zext_ln1495_62_fu_2254_p1; +wire [0:0] tmp_194_fu_2286_p3; +wire [0:0] xor_ln1495_63_fu_2294_p2; +wire [10:0] tmp_195_fu_2300_p3; +wire [0:0] tmp_193_fu_2272_p3; +wire [0:0] icmp_ln1494_32_fu_2280_p2; +wire [0:0] or_ln1495_63_fu_2312_p2; +wire [15:0] zext_ln1495_63_fu_2308_p1; +wire [0:0] tmp_197_fu_2340_p3; +wire [0:0] xor_ln1495_64_fu_2348_p2; +wire [10:0] tmp_198_fu_2354_p3; +wire [0:0] tmp_196_fu_2326_p3; +wire [0:0] icmp_ln1494_33_fu_2334_p2; +wire [0:0] or_ln1495_64_fu_2366_p2; +wire [15:0] zext_ln1495_64_fu_2362_p1; +wire [0:0] tmp_200_fu_2394_p3; +wire [0:0] xor_ln1495_65_fu_2402_p2; +wire [10:0] tmp_201_fu_2408_p3; +wire [0:0] tmp_199_fu_2380_p3; +wire [0:0] icmp_ln1494_34_fu_2388_p2; +wire [0:0] or_ln1495_65_fu_2420_p2; +wire [15:0] zext_ln1495_65_fu_2416_p1; +wire [0:0] tmp_203_fu_2448_p3; +wire [0:0] xor_ln1495_66_fu_2456_p2; +wire [10:0] tmp_204_fu_2462_p3; +wire [0:0] tmp_202_fu_2434_p3; +wire [0:0] icmp_ln1494_35_fu_2442_p2; +wire [0:0] or_ln1495_66_fu_2474_p2; +wire [15:0] zext_ln1495_66_fu_2470_p1; +wire [0:0] tmp_206_fu_2502_p3; +wire [0:0] xor_ln1495_67_fu_2510_p2; +wire [10:0] tmp_207_fu_2516_p3; +wire [0:0] tmp_205_fu_2488_p3; +wire [0:0] icmp_ln1494_36_fu_2496_p2; +wire [0:0] or_ln1495_67_fu_2528_p2; +wire [15:0] zext_ln1495_67_fu_2524_p1; +wire [0:0] tmp_209_fu_2556_p3; +wire [0:0] xor_ln1495_68_fu_2564_p2; +wire [10:0] tmp_210_fu_2570_p3; +wire [0:0] tmp_208_fu_2542_p3; +wire [0:0] icmp_ln1494_37_fu_2550_p2; +wire [0:0] or_ln1495_68_fu_2582_p2; +wire [15:0] zext_ln1495_68_fu_2578_p1; +wire [0:0] tmp_212_fu_2610_p3; +wire [0:0] xor_ln1495_69_fu_2618_p2; +wire [10:0] tmp_213_fu_2624_p3; +wire [0:0] tmp_211_fu_2596_p3; +wire [0:0] icmp_ln1494_38_fu_2604_p2; +wire [0:0] or_ln1495_69_fu_2636_p2; +wire [15:0] zext_ln1495_69_fu_2632_p1; +wire [0:0] tmp_215_fu_2664_p3; +wire [0:0] xor_ln1495_70_fu_2672_p2; +wire [10:0] tmp_216_fu_2678_p3; +wire [0:0] tmp_214_fu_2650_p3; +wire [0:0] icmp_ln1494_39_fu_2658_p2; +wire [0:0] or_ln1495_70_fu_2690_p2; +wire [15:0] zext_ln1495_70_fu_2686_p1; +wire [0:0] tmp_218_fu_2718_p3; +wire [0:0] xor_ln1495_71_fu_2726_p2; +wire [10:0] tmp_219_fu_2732_p3; +wire [0:0] tmp_217_fu_2704_p3; +wire [0:0] icmp_ln1494_40_fu_2712_p2; +wire [0:0] or_ln1495_71_fu_2744_p2; +wire [15:0] zext_ln1495_71_fu_2740_p1; +wire [0:0] tmp_221_fu_2772_p3; +wire [0:0] xor_ln1495_72_fu_2780_p2; +wire [10:0] tmp_222_fu_2786_p3; +wire [0:0] tmp_220_fu_2758_p3; +wire [0:0] icmp_ln1494_41_fu_2766_p2; +wire [0:0] or_ln1495_72_fu_2798_p2; +wire [15:0] zext_ln1495_72_fu_2794_p1; +wire [0:0] tmp_224_fu_2826_p3; +wire [0:0] xor_ln1495_73_fu_2834_p2; +wire [10:0] tmp_225_fu_2840_p3; +wire [0:0] tmp_223_fu_2812_p3; +wire [0:0] icmp_ln1494_42_fu_2820_p2; +wire [0:0] or_ln1495_73_fu_2852_p2; +wire [15:0] zext_ln1495_73_fu_2848_p1; +wire [0:0] tmp_227_fu_2880_p3; +wire [0:0] xor_ln1495_74_fu_2888_p2; +wire [10:0] tmp_228_fu_2894_p3; +wire [0:0] tmp_226_fu_2866_p3; +wire [0:0] icmp_ln1494_43_fu_2874_p2; +wire [0:0] or_ln1495_74_fu_2906_p2; +wire [15:0] zext_ln1495_74_fu_2902_p1; +wire [0:0] tmp_230_fu_2934_p3; +wire [0:0] xor_ln1495_75_fu_2942_p2; +wire [10:0] tmp_231_fu_2948_p3; +wire [0:0] tmp_229_fu_2920_p3; +wire [0:0] icmp_ln1494_44_fu_2928_p2; +wire [0:0] or_ln1495_75_fu_2960_p2; +wire [15:0] zext_ln1495_75_fu_2956_p1; +wire [0:0] tmp_233_fu_2988_p3; +wire [0:0] xor_ln1495_76_fu_2996_p2; +wire [10:0] tmp_234_fu_3002_p3; +wire [0:0] tmp_232_fu_2974_p3; +wire [0:0] icmp_ln1494_45_fu_2982_p2; +wire [0:0] or_ln1495_76_fu_3014_p2; +wire [15:0] zext_ln1495_76_fu_3010_p1; +wire [0:0] tmp_236_fu_3042_p3; +wire [0:0] xor_ln1495_77_fu_3050_p2; +wire [10:0] tmp_237_fu_3056_p3; +wire [0:0] tmp_235_fu_3028_p3; +wire [0:0] icmp_ln1494_46_fu_3036_p2; +wire [0:0] or_ln1495_77_fu_3068_p2; +wire [15:0] zext_ln1495_77_fu_3064_p1; +wire [0:0] tmp_239_fu_3096_p3; +wire [0:0] xor_ln1495_78_fu_3104_p2; +wire [10:0] tmp_240_fu_3110_p3; +wire [0:0] tmp_238_fu_3082_p3; +wire [0:0] icmp_ln1494_47_fu_3090_p2; +wire [0:0] or_ln1495_78_fu_3122_p2; +wire [15:0] zext_ln1495_78_fu_3118_p1; +wire [0:0] tmp_242_fu_3150_p3; +wire [0:0] xor_ln1495_79_fu_3158_p2; +wire [10:0] tmp_243_fu_3164_p3; +wire [0:0] tmp_241_fu_3136_p3; +wire [0:0] icmp_ln1494_48_fu_3144_p2; +wire [0:0] or_ln1495_79_fu_3176_p2; +wire [15:0] zext_ln1495_79_fu_3172_p1; +wire [0:0] tmp_245_fu_3204_p3; +wire [0:0] xor_ln1495_80_fu_3212_p2; +wire [10:0] tmp_246_fu_3218_p3; +wire [0:0] tmp_244_fu_3190_p3; +wire [0:0] icmp_ln1494_49_fu_3198_p2; +wire [0:0] or_ln1495_80_fu_3230_p2; +wire [15:0] zext_ln1495_80_fu_3226_p1; +wire [0:0] tmp_248_fu_3258_p3; +wire [0:0] xor_ln1495_81_fu_3266_p2; +wire [10:0] tmp_249_fu_3272_p3; +wire [0:0] tmp_247_fu_3244_p3; +wire [0:0] icmp_ln1494_50_fu_3252_p2; +wire [0:0] or_ln1495_81_fu_3284_p2; +wire [15:0] zext_ln1495_81_fu_3280_p1; +wire [0:0] tmp_251_fu_3312_p3; +wire [0:0] xor_ln1495_82_fu_3320_p2; +wire [10:0] tmp_252_fu_3326_p3; +wire [0:0] tmp_250_fu_3298_p3; +wire [0:0] icmp_ln1494_51_fu_3306_p2; +wire [0:0] or_ln1495_82_fu_3338_p2; +wire [15:0] zext_ln1495_82_fu_3334_p1; +wire [0:0] tmp_254_fu_3366_p3; +wire [0:0] xor_ln1495_83_fu_3374_p2; +wire [10:0] tmp_255_fu_3380_p3; +wire [0:0] tmp_253_fu_3352_p3; +wire [0:0] icmp_ln1494_52_fu_3360_p2; +wire [0:0] or_ln1495_83_fu_3392_p2; +wire [15:0] zext_ln1495_83_fu_3388_p1; +wire [0:0] tmp_257_fu_3420_p3; +wire [0:0] xor_ln1495_84_fu_3428_p2; +wire [10:0] tmp_258_fu_3434_p3; +wire [0:0] tmp_256_fu_3406_p3; +wire [0:0] icmp_ln1494_53_fu_3414_p2; +wire [0:0] or_ln1495_84_fu_3446_p2; +wire [15:0] zext_ln1495_84_fu_3442_p1; +wire [0:0] tmp_260_fu_3474_p3; +wire [0:0] xor_ln1495_85_fu_3482_p2; +wire [10:0] tmp_261_fu_3488_p3; +wire [0:0] tmp_259_fu_3460_p3; +wire [0:0] icmp_ln1494_54_fu_3468_p2; +wire [0:0] or_ln1495_85_fu_3500_p2; +wire [15:0] zext_ln1495_85_fu_3496_p1; +wire [0:0] tmp_263_fu_3528_p3; +wire [0:0] xor_ln1495_86_fu_3536_p2; +wire [10:0] tmp_264_fu_3542_p3; +wire [0:0] tmp_262_fu_3514_p3; +wire [0:0] icmp_ln1494_55_fu_3522_p2; +wire [0:0] or_ln1495_86_fu_3554_p2; +wire [15:0] zext_ln1495_86_fu_3550_p1; +wire [0:0] tmp_266_fu_3582_p3; +wire [0:0] xor_ln1495_87_fu_3590_p2; +wire [10:0] tmp_267_fu_3596_p3; +wire [0:0] tmp_265_fu_3568_p3; +wire [0:0] icmp_ln1494_56_fu_3576_p2; +wire [0:0] or_ln1495_87_fu_3608_p2; +wire [15:0] zext_ln1495_87_fu_3604_p1; +wire [0:0] tmp_269_fu_3636_p3; +wire [0:0] xor_ln1495_88_fu_3644_p2; +wire [10:0] tmp_270_fu_3650_p3; +wire [0:0] tmp_268_fu_3622_p3; +wire [0:0] icmp_ln1494_57_fu_3630_p2; +wire [0:0] or_ln1495_88_fu_3662_p2; +wire [15:0] zext_ln1495_88_fu_3658_p1; +wire [0:0] tmp_272_fu_3690_p3; +wire [0:0] xor_ln1495_89_fu_3698_p2; +wire [10:0] tmp_273_fu_3704_p3; +wire [0:0] tmp_271_fu_3676_p3; +wire [0:0] icmp_ln1494_58_fu_3684_p2; +wire [0:0] or_ln1495_89_fu_3716_p2; +wire [15:0] zext_ln1495_89_fu_3712_p1; +wire [0:0] tmp_275_fu_3744_p3; +wire [0:0] xor_ln1495_90_fu_3752_p2; +wire [10:0] tmp_276_fu_3758_p3; +wire [0:0] tmp_274_fu_3730_p3; +wire [0:0] icmp_ln1494_59_fu_3738_p2; +wire [0:0] or_ln1495_90_fu_3770_p2; +wire [15:0] zext_ln1495_90_fu_3766_p1; +wire [0:0] tmp_278_fu_3798_p3; +wire [0:0] xor_ln1495_91_fu_3806_p2; +wire [10:0] tmp_279_fu_3812_p3; +wire [0:0] tmp_277_fu_3784_p3; +wire [0:0] icmp_ln1494_60_fu_3792_p2; +wire [0:0] or_ln1495_91_fu_3824_p2; +wire [15:0] zext_ln1495_91_fu_3820_p1; +wire [0:0] tmp_281_fu_3852_p3; +wire [0:0] xor_ln1495_92_fu_3860_p2; +wire [10:0] tmp_282_fu_3866_p3; +wire [0:0] tmp_280_fu_3838_p3; +wire [0:0] icmp_ln1494_61_fu_3846_p2; +wire [0:0] or_ln1495_92_fu_3878_p2; +wire [15:0] zext_ln1495_92_fu_3874_p1; +wire [0:0] tmp_284_fu_3906_p3; +wire [0:0] xor_ln1495_93_fu_3914_p2; +wire [10:0] tmp_285_fu_3920_p3; +wire [0:0] tmp_283_fu_3892_p3; +wire [0:0] icmp_ln1494_62_fu_3900_p2; +wire [0:0] or_ln1495_93_fu_3932_p2; +wire [15:0] zext_ln1495_93_fu_3928_p1; +wire [0:0] tmp_287_fu_3960_p3; +wire [0:0] xor_ln1495_94_fu_3968_p2; +wire [10:0] tmp_288_fu_3974_p3; +wire [0:0] tmp_286_fu_3946_p3; +wire [0:0] icmp_ln1494_63_fu_3954_p2; +wire [0:0] or_ln1495_94_fu_3986_p2; +wire [15:0] zext_ln1495_94_fu_3982_p1; +wire [15:0] select_ln1495_fu_590_p3; +wire [15:0] select_ln1495_32_fu_644_p3; +wire [15:0] select_ln1495_33_fu_698_p3; +wire [15:0] select_ln1495_34_fu_752_p3; +wire [15:0] select_ln1495_35_fu_806_p3; +wire [15:0] select_ln1495_36_fu_860_p3; +wire [15:0] select_ln1495_37_fu_914_p3; +wire [15:0] select_ln1495_38_fu_968_p3; +wire [15:0] select_ln1495_39_fu_1022_p3; +wire [15:0] select_ln1495_40_fu_1076_p3; +wire [15:0] select_ln1495_41_fu_1130_p3; +wire [15:0] select_ln1495_42_fu_1184_p3; +wire [15:0] select_ln1495_43_fu_1238_p3; +wire [15:0] select_ln1495_44_fu_1292_p3; +wire [15:0] select_ln1495_45_fu_1346_p3; +wire [15:0] select_ln1495_46_fu_1400_p3; +wire [15:0] select_ln1495_47_fu_1454_p3; +wire [15:0] select_ln1495_48_fu_1508_p3; +wire [15:0] select_ln1495_49_fu_1562_p3; +wire [15:0] select_ln1495_50_fu_1616_p3; +wire [15:0] select_ln1495_51_fu_1670_p3; +wire [15:0] select_ln1495_52_fu_1724_p3; +wire [15:0] select_ln1495_53_fu_1778_p3; +wire [15:0] select_ln1495_54_fu_1832_p3; +wire [15:0] select_ln1495_55_fu_1886_p3; +wire [15:0] select_ln1495_56_fu_1940_p3; +wire [15:0] select_ln1495_57_fu_1994_p3; +wire [15:0] select_ln1495_58_fu_2048_p3; +wire [15:0] select_ln1495_59_fu_2102_p3; +wire [15:0] select_ln1495_60_fu_2156_p3; +wire [15:0] select_ln1495_61_fu_2210_p3; +wire [15:0] select_ln1495_62_fu_2264_p3; +wire [15:0] select_ln1495_63_fu_2318_p3; +wire [15:0] select_ln1495_64_fu_2372_p3; +wire [15:0] select_ln1495_65_fu_2426_p3; +wire [15:0] select_ln1495_66_fu_2480_p3; +wire [15:0] select_ln1495_67_fu_2534_p3; +wire [15:0] select_ln1495_68_fu_2588_p3; +wire [15:0] select_ln1495_69_fu_2642_p3; +wire [15:0] select_ln1495_70_fu_2696_p3; +wire [15:0] select_ln1495_71_fu_2750_p3; +wire [15:0] select_ln1495_72_fu_2804_p3; +wire [15:0] select_ln1495_73_fu_2858_p3; +wire [15:0] select_ln1495_74_fu_2912_p3; +wire [15:0] select_ln1495_75_fu_2966_p3; +wire [15:0] select_ln1495_76_fu_3020_p3; +wire [15:0] select_ln1495_77_fu_3074_p3; +wire [15:0] select_ln1495_78_fu_3128_p3; +wire [15:0] select_ln1495_79_fu_3182_p3; +wire [15:0] select_ln1495_80_fu_3236_p3; +wire [15:0] select_ln1495_81_fu_3290_p3; +wire [15:0] select_ln1495_82_fu_3344_p3; +wire [15:0] select_ln1495_83_fu_3398_p3; +wire [15:0] select_ln1495_84_fu_3452_p3; +wire [15:0] select_ln1495_85_fu_3506_p3; +wire [15:0] select_ln1495_86_fu_3560_p3; +wire [15:0] select_ln1495_87_fu_3614_p3; +wire [15:0] select_ln1495_88_fu_3668_p3; +wire [15:0] select_ln1495_89_fu_3722_p3; +wire [15:0] select_ln1495_90_fu_3776_p3; +wire [15:0] select_ln1495_91_fu_3830_p3; +wire [15:0] select_ln1495_92_fu_3884_p3; +wire [15:0] select_ln1495_93_fu_3938_p3; +wire [15:0] select_ln1495_94_fu_3992_p3; + +assign ap_ready = 1'b1; + +assign ap_return_0 = select_ln1495_fu_590_p3; + +assign ap_return_1 = select_ln1495_32_fu_644_p3; + +assign ap_return_10 = select_ln1495_41_fu_1130_p3; + +assign ap_return_11 = select_ln1495_42_fu_1184_p3; + +assign ap_return_12 = select_ln1495_43_fu_1238_p3; + +assign ap_return_13 = select_ln1495_44_fu_1292_p3; + +assign ap_return_14 = select_ln1495_45_fu_1346_p3; + +assign ap_return_15 = select_ln1495_46_fu_1400_p3; + +assign ap_return_16 = select_ln1495_47_fu_1454_p3; + +assign ap_return_17 = select_ln1495_48_fu_1508_p3; + +assign ap_return_18 = select_ln1495_49_fu_1562_p3; + +assign ap_return_19 = select_ln1495_50_fu_1616_p3; + +assign ap_return_2 = select_ln1495_33_fu_698_p3; + +assign ap_return_20 = select_ln1495_51_fu_1670_p3; + +assign ap_return_21 = select_ln1495_52_fu_1724_p3; + +assign ap_return_22 = select_ln1495_53_fu_1778_p3; + +assign ap_return_23 = select_ln1495_54_fu_1832_p3; + +assign ap_return_24 = select_ln1495_55_fu_1886_p3; + +assign ap_return_25 = select_ln1495_56_fu_1940_p3; + +assign ap_return_26 = select_ln1495_57_fu_1994_p3; + +assign ap_return_27 = select_ln1495_58_fu_2048_p3; + +assign ap_return_28 = select_ln1495_59_fu_2102_p3; + +assign ap_return_29 = select_ln1495_60_fu_2156_p3; + +assign ap_return_3 = select_ln1495_34_fu_752_p3; + +assign ap_return_30 = select_ln1495_61_fu_2210_p3; + +assign ap_return_31 = select_ln1495_62_fu_2264_p3; + +assign ap_return_32 = select_ln1495_63_fu_2318_p3; + +assign ap_return_33 = select_ln1495_64_fu_2372_p3; + +assign ap_return_34 = select_ln1495_65_fu_2426_p3; + +assign ap_return_35 = select_ln1495_66_fu_2480_p3; + +assign ap_return_36 = select_ln1495_67_fu_2534_p3; + +assign ap_return_37 = select_ln1495_68_fu_2588_p3; + +assign ap_return_38 = select_ln1495_69_fu_2642_p3; + +assign ap_return_39 = select_ln1495_70_fu_2696_p3; + +assign ap_return_4 = select_ln1495_35_fu_806_p3; + +assign ap_return_40 = select_ln1495_71_fu_2750_p3; + +assign ap_return_41 = select_ln1495_72_fu_2804_p3; + +assign ap_return_42 = select_ln1495_73_fu_2858_p3; + +assign ap_return_43 = select_ln1495_74_fu_2912_p3; + +assign ap_return_44 = select_ln1495_75_fu_2966_p3; + +assign ap_return_45 = select_ln1495_76_fu_3020_p3; + +assign ap_return_46 = select_ln1495_77_fu_3074_p3; + +assign ap_return_47 = select_ln1495_78_fu_3128_p3; + +assign ap_return_48 = select_ln1495_79_fu_3182_p3; + +assign ap_return_49 = select_ln1495_80_fu_3236_p3; + +assign ap_return_5 = select_ln1495_36_fu_860_p3; + +assign ap_return_50 = select_ln1495_81_fu_3290_p3; + +assign ap_return_51 = select_ln1495_82_fu_3344_p3; + +assign ap_return_52 = select_ln1495_83_fu_3398_p3; + +assign ap_return_53 = select_ln1495_84_fu_3452_p3; + +assign ap_return_54 = select_ln1495_85_fu_3506_p3; + +assign ap_return_55 = select_ln1495_86_fu_3560_p3; + +assign ap_return_56 = select_ln1495_87_fu_3614_p3; + +assign ap_return_57 = select_ln1495_88_fu_3668_p3; + +assign ap_return_58 = select_ln1495_89_fu_3722_p3; + +assign ap_return_59 = select_ln1495_90_fu_3776_p3; + +assign ap_return_6 = select_ln1495_37_fu_914_p3; + +assign ap_return_60 = select_ln1495_91_fu_3830_p3; + +assign ap_return_61 = select_ln1495_92_fu_3884_p3; + +assign ap_return_62 = select_ln1495_93_fu_3938_p3; + +assign ap_return_63 = select_ln1495_94_fu_3992_p3; + +assign ap_return_7 = select_ln1495_38_fu_968_p3; + +assign ap_return_8 = select_ln1495_39_fu_1022_p3; + +assign ap_return_9 = select_ln1495_40_fu_1076_p3; + +assign icmp_ln1494_10_fu_1092_p2 = (((data_10_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_11_fu_1146_p2 = (((data_11_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_12_fu_1200_p2 = (((data_12_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_13_fu_1254_p2 = (((data_13_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_14_fu_1308_p2 = (((data_14_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_15_fu_1362_p2 = (((data_15_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_16_fu_1416_p2 = (((data_16_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_17_fu_1470_p2 = (((data_17_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_18_fu_1524_p2 = (((data_18_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_19_fu_1578_p2 = (((data_19_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_1_fu_606_p2 = (((data_1_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_20_fu_1632_p2 = (((data_20_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_21_fu_1686_p2 = (((data_21_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_22_fu_1740_p2 = (((data_22_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_23_fu_1794_p2 = (((data_23_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_24_fu_1848_p2 = (((data_24_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_25_fu_1902_p2 = (((data_25_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_26_fu_1956_p2 = (((data_26_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_27_fu_2010_p2 = (((data_27_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_28_fu_2064_p2 = (((data_28_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_29_fu_2118_p2 = (((data_29_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_2_fu_660_p2 = (((data_2_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_30_fu_2172_p2 = (((data_30_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_31_fu_2226_p2 = (((data_31_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_32_fu_2280_p2 = (((data_32_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_33_fu_2334_p2 = (((data_33_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_34_fu_2388_p2 = (((data_34_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_35_fu_2442_p2 = (((data_35_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_36_fu_2496_p2 = (((data_36_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_37_fu_2550_p2 = (((data_37_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_38_fu_2604_p2 = (((data_38_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_39_fu_2658_p2 = (((data_39_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_3_fu_714_p2 = (((data_3_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_40_fu_2712_p2 = (((data_40_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_41_fu_2766_p2 = (((data_41_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_42_fu_2820_p2 = (((data_42_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_43_fu_2874_p2 = (((data_43_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_44_fu_2928_p2 = (((data_44_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_45_fu_2982_p2 = (((data_45_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_46_fu_3036_p2 = (((data_46_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_47_fu_3090_p2 = (((data_47_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_48_fu_3144_p2 = (((data_48_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_49_fu_3198_p2 = (((data_49_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_4_fu_768_p2 = (((data_4_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_50_fu_3252_p2 = (((data_50_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_51_fu_3306_p2 = (((data_51_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_52_fu_3360_p2 = (((data_52_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_53_fu_3414_p2 = (((data_53_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_54_fu_3468_p2 = (((data_54_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_55_fu_3522_p2 = (((data_55_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_56_fu_3576_p2 = (((data_56_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_57_fu_3630_p2 = (((data_57_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_58_fu_3684_p2 = (((data_58_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_59_fu_3738_p2 = (((data_59_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_5_fu_822_p2 = (((data_5_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_60_fu_3792_p2 = (((data_60_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_61_fu_3846_p2 = (((data_61_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_62_fu_3900_p2 = (((data_62_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_63_fu_3954_p2 = (((data_63_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_6_fu_876_p2 = (((data_6_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_7_fu_930_p2 = (((data_7_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_8_fu_984_p2 = (((data_8_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_9_fu_1038_p2 = (((data_9_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_fu_552_p2 = (((data_0_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign or_ln1495_32_fu_638_p2 = (tmp_100_fu_598_p3 | icmp_ln1494_1_fu_606_p2); + +assign or_ln1495_33_fu_692_p2 = (tmp_103_fu_652_p3 | icmp_ln1494_2_fu_660_p2); + +assign or_ln1495_34_fu_746_p2 = (tmp_106_fu_706_p3 | icmp_ln1494_3_fu_714_p2); + +assign or_ln1495_35_fu_800_p2 = (tmp_109_fu_760_p3 | icmp_ln1494_4_fu_768_p2); + +assign or_ln1495_36_fu_854_p2 = (tmp_112_fu_814_p3 | icmp_ln1494_5_fu_822_p2); + +assign or_ln1495_37_fu_908_p2 = (tmp_115_fu_868_p3 | icmp_ln1494_6_fu_876_p2); + +assign or_ln1495_38_fu_962_p2 = (tmp_118_fu_922_p3 | icmp_ln1494_7_fu_930_p2); + +assign or_ln1495_39_fu_1016_p2 = (tmp_121_fu_976_p3 | icmp_ln1494_8_fu_984_p2); + +assign or_ln1495_40_fu_1070_p2 = (tmp_124_fu_1030_p3 | icmp_ln1494_9_fu_1038_p2); + +assign or_ln1495_41_fu_1124_p2 = (tmp_127_fu_1084_p3 | icmp_ln1494_10_fu_1092_p2); + +assign or_ln1495_42_fu_1178_p2 = (tmp_130_fu_1138_p3 | icmp_ln1494_11_fu_1146_p2); + +assign or_ln1495_43_fu_1232_p2 = (tmp_133_fu_1192_p3 | icmp_ln1494_12_fu_1200_p2); + +assign or_ln1495_44_fu_1286_p2 = (tmp_136_fu_1246_p3 | icmp_ln1494_13_fu_1254_p2); + +assign or_ln1495_45_fu_1340_p2 = (tmp_139_fu_1300_p3 | icmp_ln1494_14_fu_1308_p2); + +assign or_ln1495_46_fu_1394_p2 = (tmp_142_fu_1354_p3 | icmp_ln1494_15_fu_1362_p2); + +assign or_ln1495_47_fu_1448_p2 = (tmp_145_fu_1408_p3 | icmp_ln1494_16_fu_1416_p2); + +assign or_ln1495_48_fu_1502_p2 = (tmp_148_fu_1462_p3 | icmp_ln1494_17_fu_1470_p2); + +assign or_ln1495_49_fu_1556_p2 = (tmp_151_fu_1516_p3 | icmp_ln1494_18_fu_1524_p2); + +assign or_ln1495_50_fu_1610_p2 = (tmp_154_fu_1570_p3 | icmp_ln1494_19_fu_1578_p2); + +assign or_ln1495_51_fu_1664_p2 = (tmp_157_fu_1624_p3 | icmp_ln1494_20_fu_1632_p2); + +assign or_ln1495_52_fu_1718_p2 = (tmp_160_fu_1678_p3 | icmp_ln1494_21_fu_1686_p2); + +assign or_ln1495_53_fu_1772_p2 = (tmp_163_fu_1732_p3 | icmp_ln1494_22_fu_1740_p2); + +assign or_ln1495_54_fu_1826_p2 = (tmp_166_fu_1786_p3 | icmp_ln1494_23_fu_1794_p2); + +assign or_ln1495_55_fu_1880_p2 = (tmp_169_fu_1840_p3 | icmp_ln1494_24_fu_1848_p2); + +assign or_ln1495_56_fu_1934_p2 = (tmp_172_fu_1894_p3 | icmp_ln1494_25_fu_1902_p2); + +assign or_ln1495_57_fu_1988_p2 = (tmp_175_fu_1948_p3 | icmp_ln1494_26_fu_1956_p2); + +assign or_ln1495_58_fu_2042_p2 = (tmp_178_fu_2002_p3 | icmp_ln1494_27_fu_2010_p2); + +assign or_ln1495_59_fu_2096_p2 = (tmp_181_fu_2056_p3 | icmp_ln1494_28_fu_2064_p2); + +assign or_ln1495_60_fu_2150_p2 = (tmp_184_fu_2110_p3 | icmp_ln1494_29_fu_2118_p2); + +assign or_ln1495_61_fu_2204_p2 = (tmp_187_fu_2164_p3 | icmp_ln1494_30_fu_2172_p2); + +assign or_ln1495_62_fu_2258_p2 = (tmp_190_fu_2218_p3 | icmp_ln1494_31_fu_2226_p2); + +assign or_ln1495_63_fu_2312_p2 = (tmp_193_fu_2272_p3 | icmp_ln1494_32_fu_2280_p2); + +assign or_ln1495_64_fu_2366_p2 = (tmp_196_fu_2326_p3 | icmp_ln1494_33_fu_2334_p2); + +assign or_ln1495_65_fu_2420_p2 = (tmp_199_fu_2380_p3 | icmp_ln1494_34_fu_2388_p2); + +assign or_ln1495_66_fu_2474_p2 = (tmp_202_fu_2434_p3 | icmp_ln1494_35_fu_2442_p2); + +assign or_ln1495_67_fu_2528_p2 = (tmp_205_fu_2488_p3 | icmp_ln1494_36_fu_2496_p2); + +assign or_ln1495_68_fu_2582_p2 = (tmp_208_fu_2542_p3 | icmp_ln1494_37_fu_2550_p2); + +assign or_ln1495_69_fu_2636_p2 = (tmp_211_fu_2596_p3 | icmp_ln1494_38_fu_2604_p2); + +assign or_ln1495_70_fu_2690_p2 = (tmp_214_fu_2650_p3 | icmp_ln1494_39_fu_2658_p2); + +assign or_ln1495_71_fu_2744_p2 = (tmp_217_fu_2704_p3 | icmp_ln1494_40_fu_2712_p2); + +assign or_ln1495_72_fu_2798_p2 = (tmp_220_fu_2758_p3 | icmp_ln1494_41_fu_2766_p2); + +assign or_ln1495_73_fu_2852_p2 = (tmp_223_fu_2812_p3 | icmp_ln1494_42_fu_2820_p2); + +assign or_ln1495_74_fu_2906_p2 = (tmp_226_fu_2866_p3 | icmp_ln1494_43_fu_2874_p2); + +assign or_ln1495_75_fu_2960_p2 = (tmp_229_fu_2920_p3 | icmp_ln1494_44_fu_2928_p2); + +assign or_ln1495_76_fu_3014_p2 = (tmp_232_fu_2974_p3 | icmp_ln1494_45_fu_2982_p2); + +assign or_ln1495_77_fu_3068_p2 = (tmp_235_fu_3028_p3 | icmp_ln1494_46_fu_3036_p2); + +assign or_ln1495_78_fu_3122_p2 = (tmp_238_fu_3082_p3 | icmp_ln1494_47_fu_3090_p2); + +assign or_ln1495_79_fu_3176_p2 = (tmp_241_fu_3136_p3 | icmp_ln1494_48_fu_3144_p2); + +assign or_ln1495_80_fu_3230_p2 = (tmp_244_fu_3190_p3 | icmp_ln1494_49_fu_3198_p2); + +assign or_ln1495_81_fu_3284_p2 = (tmp_247_fu_3244_p3 | icmp_ln1494_50_fu_3252_p2); + +assign or_ln1495_82_fu_3338_p2 = (tmp_250_fu_3298_p3 | icmp_ln1494_51_fu_3306_p2); + +assign or_ln1495_83_fu_3392_p2 = (tmp_253_fu_3352_p3 | icmp_ln1494_52_fu_3360_p2); + +assign or_ln1495_84_fu_3446_p2 = (tmp_256_fu_3406_p3 | icmp_ln1494_53_fu_3414_p2); + +assign or_ln1495_85_fu_3500_p2 = (tmp_259_fu_3460_p3 | icmp_ln1494_54_fu_3468_p2); + +assign or_ln1495_86_fu_3554_p2 = (tmp_262_fu_3514_p3 | icmp_ln1494_55_fu_3522_p2); + +assign or_ln1495_87_fu_3608_p2 = (tmp_265_fu_3568_p3 | icmp_ln1494_56_fu_3576_p2); + +assign or_ln1495_88_fu_3662_p2 = (tmp_268_fu_3622_p3 | icmp_ln1494_57_fu_3630_p2); + +assign or_ln1495_89_fu_3716_p2 = (tmp_271_fu_3676_p3 | icmp_ln1494_58_fu_3684_p2); + +assign or_ln1495_90_fu_3770_p2 = (tmp_274_fu_3730_p3 | icmp_ln1494_59_fu_3738_p2); + +assign or_ln1495_91_fu_3824_p2 = (tmp_277_fu_3784_p3 | icmp_ln1494_60_fu_3792_p2); + +assign or_ln1495_92_fu_3878_p2 = (tmp_280_fu_3838_p3 | icmp_ln1494_61_fu_3846_p2); + +assign or_ln1495_93_fu_3932_p2 = (tmp_283_fu_3892_p3 | icmp_ln1494_62_fu_3900_p2); + +assign or_ln1495_94_fu_3986_p2 = (tmp_286_fu_3946_p3 | icmp_ln1494_63_fu_3954_p2); + +assign or_ln1495_fu_584_p2 = (tmp_97_fu_544_p3 | icmp_ln1494_fu_552_p2); + +assign select_ln1495_32_fu_644_p3 = ((or_ln1495_32_fu_638_p2[0:0] == 1'b1) ? zext_ln1495_32_fu_634_p1 : data_1_V_read); + +assign select_ln1495_33_fu_698_p3 = ((or_ln1495_33_fu_692_p2[0:0] == 1'b1) ? zext_ln1495_33_fu_688_p1 : data_2_V_read); + +assign select_ln1495_34_fu_752_p3 = ((or_ln1495_34_fu_746_p2[0:0] == 1'b1) ? zext_ln1495_34_fu_742_p1 : data_3_V_read); + +assign select_ln1495_35_fu_806_p3 = ((or_ln1495_35_fu_800_p2[0:0] == 1'b1) ? zext_ln1495_35_fu_796_p1 : data_4_V_read); + +assign select_ln1495_36_fu_860_p3 = ((or_ln1495_36_fu_854_p2[0:0] == 1'b1) ? zext_ln1495_36_fu_850_p1 : data_5_V_read); + +assign select_ln1495_37_fu_914_p3 = ((or_ln1495_37_fu_908_p2[0:0] == 1'b1) ? zext_ln1495_37_fu_904_p1 : data_6_V_read); + +assign select_ln1495_38_fu_968_p3 = ((or_ln1495_38_fu_962_p2[0:0] == 1'b1) ? zext_ln1495_38_fu_958_p1 : data_7_V_read); + +assign select_ln1495_39_fu_1022_p3 = ((or_ln1495_39_fu_1016_p2[0:0] == 1'b1) ? zext_ln1495_39_fu_1012_p1 : data_8_V_read); + +assign select_ln1495_40_fu_1076_p3 = ((or_ln1495_40_fu_1070_p2[0:0] == 1'b1) ? zext_ln1495_40_fu_1066_p1 : data_9_V_read); + +assign select_ln1495_41_fu_1130_p3 = ((or_ln1495_41_fu_1124_p2[0:0] == 1'b1) ? zext_ln1495_41_fu_1120_p1 : data_10_V_read); + +assign select_ln1495_42_fu_1184_p3 = ((or_ln1495_42_fu_1178_p2[0:0] == 1'b1) ? zext_ln1495_42_fu_1174_p1 : data_11_V_read); + +assign select_ln1495_43_fu_1238_p3 = ((or_ln1495_43_fu_1232_p2[0:0] == 1'b1) ? zext_ln1495_43_fu_1228_p1 : data_12_V_read); + +assign select_ln1495_44_fu_1292_p3 = ((or_ln1495_44_fu_1286_p2[0:0] == 1'b1) ? zext_ln1495_44_fu_1282_p1 : data_13_V_read); + +assign select_ln1495_45_fu_1346_p3 = ((or_ln1495_45_fu_1340_p2[0:0] == 1'b1) ? zext_ln1495_45_fu_1336_p1 : data_14_V_read); + +assign select_ln1495_46_fu_1400_p3 = ((or_ln1495_46_fu_1394_p2[0:0] == 1'b1) ? zext_ln1495_46_fu_1390_p1 : data_15_V_read); + +assign select_ln1495_47_fu_1454_p3 = ((or_ln1495_47_fu_1448_p2[0:0] == 1'b1) ? zext_ln1495_47_fu_1444_p1 : data_16_V_read); + +assign select_ln1495_48_fu_1508_p3 = ((or_ln1495_48_fu_1502_p2[0:0] == 1'b1) ? zext_ln1495_48_fu_1498_p1 : data_17_V_read); + +assign select_ln1495_49_fu_1562_p3 = ((or_ln1495_49_fu_1556_p2[0:0] == 1'b1) ? zext_ln1495_49_fu_1552_p1 : data_18_V_read); + +assign select_ln1495_50_fu_1616_p3 = ((or_ln1495_50_fu_1610_p2[0:0] == 1'b1) ? zext_ln1495_50_fu_1606_p1 : data_19_V_read); + +assign select_ln1495_51_fu_1670_p3 = ((or_ln1495_51_fu_1664_p2[0:0] == 1'b1) ? zext_ln1495_51_fu_1660_p1 : data_20_V_read); + +assign select_ln1495_52_fu_1724_p3 = ((or_ln1495_52_fu_1718_p2[0:0] == 1'b1) ? zext_ln1495_52_fu_1714_p1 : data_21_V_read); + +assign select_ln1495_53_fu_1778_p3 = ((or_ln1495_53_fu_1772_p2[0:0] == 1'b1) ? zext_ln1495_53_fu_1768_p1 : data_22_V_read); + +assign select_ln1495_54_fu_1832_p3 = ((or_ln1495_54_fu_1826_p2[0:0] == 1'b1) ? zext_ln1495_54_fu_1822_p1 : data_23_V_read); + +assign select_ln1495_55_fu_1886_p3 = ((or_ln1495_55_fu_1880_p2[0:0] == 1'b1) ? zext_ln1495_55_fu_1876_p1 : data_24_V_read); + +assign select_ln1495_56_fu_1940_p3 = ((or_ln1495_56_fu_1934_p2[0:0] == 1'b1) ? zext_ln1495_56_fu_1930_p1 : data_25_V_read); + +assign select_ln1495_57_fu_1994_p3 = ((or_ln1495_57_fu_1988_p2[0:0] == 1'b1) ? zext_ln1495_57_fu_1984_p1 : data_26_V_read); + +assign select_ln1495_58_fu_2048_p3 = ((or_ln1495_58_fu_2042_p2[0:0] == 1'b1) ? zext_ln1495_58_fu_2038_p1 : data_27_V_read); + +assign select_ln1495_59_fu_2102_p3 = ((or_ln1495_59_fu_2096_p2[0:0] == 1'b1) ? zext_ln1495_59_fu_2092_p1 : data_28_V_read); + +assign select_ln1495_60_fu_2156_p3 = ((or_ln1495_60_fu_2150_p2[0:0] == 1'b1) ? zext_ln1495_60_fu_2146_p1 : data_29_V_read); + +assign select_ln1495_61_fu_2210_p3 = ((or_ln1495_61_fu_2204_p2[0:0] == 1'b1) ? zext_ln1495_61_fu_2200_p1 : data_30_V_read); + +assign select_ln1495_62_fu_2264_p3 = ((or_ln1495_62_fu_2258_p2[0:0] == 1'b1) ? zext_ln1495_62_fu_2254_p1 : data_31_V_read); + +assign select_ln1495_63_fu_2318_p3 = ((or_ln1495_63_fu_2312_p2[0:0] == 1'b1) ? zext_ln1495_63_fu_2308_p1 : data_32_V_read); + +assign select_ln1495_64_fu_2372_p3 = ((or_ln1495_64_fu_2366_p2[0:0] == 1'b1) ? zext_ln1495_64_fu_2362_p1 : data_33_V_read); + +assign select_ln1495_65_fu_2426_p3 = ((or_ln1495_65_fu_2420_p2[0:0] == 1'b1) ? zext_ln1495_65_fu_2416_p1 : data_34_V_read); + +assign select_ln1495_66_fu_2480_p3 = ((or_ln1495_66_fu_2474_p2[0:0] == 1'b1) ? zext_ln1495_66_fu_2470_p1 : data_35_V_read); + +assign select_ln1495_67_fu_2534_p3 = ((or_ln1495_67_fu_2528_p2[0:0] == 1'b1) ? zext_ln1495_67_fu_2524_p1 : data_36_V_read); + +assign select_ln1495_68_fu_2588_p3 = ((or_ln1495_68_fu_2582_p2[0:0] == 1'b1) ? zext_ln1495_68_fu_2578_p1 : data_37_V_read); + +assign select_ln1495_69_fu_2642_p3 = ((or_ln1495_69_fu_2636_p2[0:0] == 1'b1) ? zext_ln1495_69_fu_2632_p1 : data_38_V_read); + +assign select_ln1495_70_fu_2696_p3 = ((or_ln1495_70_fu_2690_p2[0:0] == 1'b1) ? zext_ln1495_70_fu_2686_p1 : data_39_V_read); + +assign select_ln1495_71_fu_2750_p3 = ((or_ln1495_71_fu_2744_p2[0:0] == 1'b1) ? zext_ln1495_71_fu_2740_p1 : data_40_V_read); + +assign select_ln1495_72_fu_2804_p3 = ((or_ln1495_72_fu_2798_p2[0:0] == 1'b1) ? zext_ln1495_72_fu_2794_p1 : data_41_V_read); + +assign select_ln1495_73_fu_2858_p3 = ((or_ln1495_73_fu_2852_p2[0:0] == 1'b1) ? zext_ln1495_73_fu_2848_p1 : data_42_V_read); + +assign select_ln1495_74_fu_2912_p3 = ((or_ln1495_74_fu_2906_p2[0:0] == 1'b1) ? zext_ln1495_74_fu_2902_p1 : data_43_V_read); + +assign select_ln1495_75_fu_2966_p3 = ((or_ln1495_75_fu_2960_p2[0:0] == 1'b1) ? zext_ln1495_75_fu_2956_p1 : data_44_V_read); + +assign select_ln1495_76_fu_3020_p3 = ((or_ln1495_76_fu_3014_p2[0:0] == 1'b1) ? zext_ln1495_76_fu_3010_p1 : data_45_V_read); + +assign select_ln1495_77_fu_3074_p3 = ((or_ln1495_77_fu_3068_p2[0:0] == 1'b1) ? zext_ln1495_77_fu_3064_p1 : data_46_V_read); + +assign select_ln1495_78_fu_3128_p3 = ((or_ln1495_78_fu_3122_p2[0:0] == 1'b1) ? zext_ln1495_78_fu_3118_p1 : data_47_V_read); + +assign select_ln1495_79_fu_3182_p3 = ((or_ln1495_79_fu_3176_p2[0:0] == 1'b1) ? zext_ln1495_79_fu_3172_p1 : data_48_V_read); + +assign select_ln1495_80_fu_3236_p3 = ((or_ln1495_80_fu_3230_p2[0:0] == 1'b1) ? zext_ln1495_80_fu_3226_p1 : data_49_V_read); + +assign select_ln1495_81_fu_3290_p3 = ((or_ln1495_81_fu_3284_p2[0:0] == 1'b1) ? zext_ln1495_81_fu_3280_p1 : data_50_V_read); + +assign select_ln1495_82_fu_3344_p3 = ((or_ln1495_82_fu_3338_p2[0:0] == 1'b1) ? zext_ln1495_82_fu_3334_p1 : data_51_V_read); + +assign select_ln1495_83_fu_3398_p3 = ((or_ln1495_83_fu_3392_p2[0:0] == 1'b1) ? zext_ln1495_83_fu_3388_p1 : data_52_V_read); + +assign select_ln1495_84_fu_3452_p3 = ((or_ln1495_84_fu_3446_p2[0:0] == 1'b1) ? zext_ln1495_84_fu_3442_p1 : data_53_V_read); + +assign select_ln1495_85_fu_3506_p3 = ((or_ln1495_85_fu_3500_p2[0:0] == 1'b1) ? zext_ln1495_85_fu_3496_p1 : data_54_V_read); + +assign select_ln1495_86_fu_3560_p3 = ((or_ln1495_86_fu_3554_p2[0:0] == 1'b1) ? zext_ln1495_86_fu_3550_p1 : data_55_V_read); + +assign select_ln1495_87_fu_3614_p3 = ((or_ln1495_87_fu_3608_p2[0:0] == 1'b1) ? zext_ln1495_87_fu_3604_p1 : data_56_V_read); + +assign select_ln1495_88_fu_3668_p3 = ((or_ln1495_88_fu_3662_p2[0:0] == 1'b1) ? zext_ln1495_88_fu_3658_p1 : data_57_V_read); + +assign select_ln1495_89_fu_3722_p3 = ((or_ln1495_89_fu_3716_p2[0:0] == 1'b1) ? zext_ln1495_89_fu_3712_p1 : data_58_V_read); + +assign select_ln1495_90_fu_3776_p3 = ((or_ln1495_90_fu_3770_p2[0:0] == 1'b1) ? zext_ln1495_90_fu_3766_p1 : data_59_V_read); + +assign select_ln1495_91_fu_3830_p3 = ((or_ln1495_91_fu_3824_p2[0:0] == 1'b1) ? zext_ln1495_91_fu_3820_p1 : data_60_V_read); + +assign select_ln1495_92_fu_3884_p3 = ((or_ln1495_92_fu_3878_p2[0:0] == 1'b1) ? zext_ln1495_92_fu_3874_p1 : data_61_V_read); + +assign select_ln1495_93_fu_3938_p3 = ((or_ln1495_93_fu_3932_p2[0:0] == 1'b1) ? zext_ln1495_93_fu_3928_p1 : data_62_V_read); + +assign select_ln1495_94_fu_3992_p3 = ((or_ln1495_94_fu_3986_p2[0:0] == 1'b1) ? zext_ln1495_94_fu_3982_p1 : data_63_V_read); + +assign select_ln1495_fu_590_p3 = ((or_ln1495_fu_584_p2[0:0] == 1'b1) ? zext_ln1495_fu_580_p1 : data_0_V_read); + +assign tmp_100_fu_598_p3 = data_1_V_read[32'd15]; + +assign tmp_101_fu_612_p3 = data_1_V_read[32'd15]; + +assign tmp_102_fu_626_p3 = {{xor_ln1495_32_fu_620_p2}, {10'd0}}; + +assign tmp_103_fu_652_p3 = data_2_V_read[32'd15]; + +assign tmp_104_fu_666_p3 = data_2_V_read[32'd15]; + +assign tmp_105_fu_680_p3 = {{xor_ln1495_33_fu_674_p2}, {10'd0}}; + +assign tmp_106_fu_706_p3 = data_3_V_read[32'd15]; + +assign tmp_107_fu_720_p3 = data_3_V_read[32'd15]; + +assign tmp_108_fu_734_p3 = {{xor_ln1495_34_fu_728_p2}, {10'd0}}; + +assign tmp_109_fu_760_p3 = data_4_V_read[32'd15]; + +assign tmp_110_fu_774_p3 = data_4_V_read[32'd15]; + +assign tmp_111_fu_788_p3 = {{xor_ln1495_35_fu_782_p2}, {10'd0}}; + +assign tmp_112_fu_814_p3 = data_5_V_read[32'd15]; + +assign tmp_113_fu_828_p3 = data_5_V_read[32'd15]; + +assign tmp_114_fu_842_p3 = {{xor_ln1495_36_fu_836_p2}, {10'd0}}; + +assign tmp_115_fu_868_p3 = data_6_V_read[32'd15]; + +assign tmp_116_fu_882_p3 = data_6_V_read[32'd15]; + +assign tmp_117_fu_896_p3 = {{xor_ln1495_37_fu_890_p2}, {10'd0}}; + +assign tmp_118_fu_922_p3 = data_7_V_read[32'd15]; + +assign tmp_119_fu_936_p3 = data_7_V_read[32'd15]; + +assign tmp_120_fu_950_p3 = {{xor_ln1495_38_fu_944_p2}, {10'd0}}; + +assign tmp_121_fu_976_p3 = data_8_V_read[32'd15]; + +assign tmp_122_fu_990_p3 = data_8_V_read[32'd15]; + +assign tmp_123_fu_1004_p3 = {{xor_ln1495_39_fu_998_p2}, {10'd0}}; + +assign tmp_124_fu_1030_p3 = data_9_V_read[32'd15]; + +assign tmp_125_fu_1044_p3 = data_9_V_read[32'd15]; + +assign tmp_126_fu_1058_p3 = {{xor_ln1495_40_fu_1052_p2}, {10'd0}}; + +assign tmp_127_fu_1084_p3 = data_10_V_read[32'd15]; + +assign tmp_128_fu_1098_p3 = data_10_V_read[32'd15]; + +assign tmp_129_fu_1112_p3 = {{xor_ln1495_41_fu_1106_p2}, {10'd0}}; + +assign tmp_130_fu_1138_p3 = data_11_V_read[32'd15]; + +assign tmp_131_fu_1152_p3 = data_11_V_read[32'd15]; + +assign tmp_132_fu_1166_p3 = {{xor_ln1495_42_fu_1160_p2}, {10'd0}}; + +assign tmp_133_fu_1192_p3 = data_12_V_read[32'd15]; + +assign tmp_134_fu_1206_p3 = data_12_V_read[32'd15]; + +assign tmp_135_fu_1220_p3 = {{xor_ln1495_43_fu_1214_p2}, {10'd0}}; + +assign tmp_136_fu_1246_p3 = data_13_V_read[32'd15]; + +assign tmp_137_fu_1260_p3 = data_13_V_read[32'd15]; + +assign tmp_138_fu_1274_p3 = {{xor_ln1495_44_fu_1268_p2}, {10'd0}}; + +assign tmp_139_fu_1300_p3 = data_14_V_read[32'd15]; + +assign tmp_140_fu_1314_p3 = data_14_V_read[32'd15]; + +assign tmp_141_fu_1328_p3 = {{xor_ln1495_45_fu_1322_p2}, {10'd0}}; + +assign tmp_142_fu_1354_p3 = data_15_V_read[32'd15]; + +assign tmp_143_fu_1368_p3 = data_15_V_read[32'd15]; + +assign tmp_144_fu_1382_p3 = {{xor_ln1495_46_fu_1376_p2}, {10'd0}}; + +assign tmp_145_fu_1408_p3 = data_16_V_read[32'd15]; + +assign tmp_146_fu_1422_p3 = data_16_V_read[32'd15]; + +assign tmp_147_fu_1436_p3 = {{xor_ln1495_47_fu_1430_p2}, {10'd0}}; + +assign tmp_148_fu_1462_p3 = data_17_V_read[32'd15]; + +assign tmp_149_fu_1476_p3 = data_17_V_read[32'd15]; + +assign tmp_150_fu_1490_p3 = {{xor_ln1495_48_fu_1484_p2}, {10'd0}}; + +assign tmp_151_fu_1516_p3 = data_18_V_read[32'd15]; + +assign tmp_152_fu_1530_p3 = data_18_V_read[32'd15]; + +assign tmp_153_fu_1544_p3 = {{xor_ln1495_49_fu_1538_p2}, {10'd0}}; + +assign tmp_154_fu_1570_p3 = data_19_V_read[32'd15]; + +assign tmp_155_fu_1584_p3 = data_19_V_read[32'd15]; + +assign tmp_156_fu_1598_p3 = {{xor_ln1495_50_fu_1592_p2}, {10'd0}}; + +assign tmp_157_fu_1624_p3 = data_20_V_read[32'd15]; + +assign tmp_158_fu_1638_p3 = data_20_V_read[32'd15]; + +assign tmp_159_fu_1652_p3 = {{xor_ln1495_51_fu_1646_p2}, {10'd0}}; + +assign tmp_160_fu_1678_p3 = data_21_V_read[32'd15]; + +assign tmp_161_fu_1692_p3 = data_21_V_read[32'd15]; + +assign tmp_162_fu_1706_p3 = {{xor_ln1495_52_fu_1700_p2}, {10'd0}}; + +assign tmp_163_fu_1732_p3 = data_22_V_read[32'd15]; + +assign tmp_164_fu_1746_p3 = data_22_V_read[32'd15]; + +assign tmp_165_fu_1760_p3 = {{xor_ln1495_53_fu_1754_p2}, {10'd0}}; + +assign tmp_166_fu_1786_p3 = data_23_V_read[32'd15]; + +assign tmp_167_fu_1800_p3 = data_23_V_read[32'd15]; + +assign tmp_168_fu_1814_p3 = {{xor_ln1495_54_fu_1808_p2}, {10'd0}}; + +assign tmp_169_fu_1840_p3 = data_24_V_read[32'd15]; + +assign tmp_170_fu_1854_p3 = data_24_V_read[32'd15]; + +assign tmp_171_fu_1868_p3 = {{xor_ln1495_55_fu_1862_p2}, {10'd0}}; + +assign tmp_172_fu_1894_p3 = data_25_V_read[32'd15]; + +assign tmp_173_fu_1908_p3 = data_25_V_read[32'd15]; + +assign tmp_174_fu_1922_p3 = {{xor_ln1495_56_fu_1916_p2}, {10'd0}}; + +assign tmp_175_fu_1948_p3 = data_26_V_read[32'd15]; + +assign tmp_176_fu_1962_p3 = data_26_V_read[32'd15]; + +assign tmp_177_fu_1976_p3 = {{xor_ln1495_57_fu_1970_p2}, {10'd0}}; + +assign tmp_178_fu_2002_p3 = data_27_V_read[32'd15]; + +assign tmp_179_fu_2016_p3 = data_27_V_read[32'd15]; + +assign tmp_180_fu_2030_p3 = {{xor_ln1495_58_fu_2024_p2}, {10'd0}}; + +assign tmp_181_fu_2056_p3 = data_28_V_read[32'd15]; + +assign tmp_182_fu_2070_p3 = data_28_V_read[32'd15]; + +assign tmp_183_fu_2084_p3 = {{xor_ln1495_59_fu_2078_p2}, {10'd0}}; + +assign tmp_184_fu_2110_p3 = data_29_V_read[32'd15]; + +assign tmp_185_fu_2124_p3 = data_29_V_read[32'd15]; + +assign tmp_186_fu_2138_p3 = {{xor_ln1495_60_fu_2132_p2}, {10'd0}}; + +assign tmp_187_fu_2164_p3 = data_30_V_read[32'd15]; + +assign tmp_188_fu_2178_p3 = data_30_V_read[32'd15]; + +assign tmp_189_fu_2192_p3 = {{xor_ln1495_61_fu_2186_p2}, {10'd0}}; + +assign tmp_190_fu_2218_p3 = data_31_V_read[32'd15]; + +assign tmp_191_fu_2232_p3 = data_31_V_read[32'd15]; + +assign tmp_192_fu_2246_p3 = {{xor_ln1495_62_fu_2240_p2}, {10'd0}}; + +assign tmp_193_fu_2272_p3 = data_32_V_read[32'd15]; + +assign tmp_194_fu_2286_p3 = data_32_V_read[32'd15]; + +assign tmp_195_fu_2300_p3 = {{xor_ln1495_63_fu_2294_p2}, {10'd0}}; + +assign tmp_196_fu_2326_p3 = data_33_V_read[32'd15]; + +assign tmp_197_fu_2340_p3 = data_33_V_read[32'd15]; + +assign tmp_198_fu_2354_p3 = {{xor_ln1495_64_fu_2348_p2}, {10'd0}}; + +assign tmp_199_fu_2380_p3 = data_34_V_read[32'd15]; + +assign tmp_200_fu_2394_p3 = data_34_V_read[32'd15]; + +assign tmp_201_fu_2408_p3 = {{xor_ln1495_65_fu_2402_p2}, {10'd0}}; + +assign tmp_202_fu_2434_p3 = data_35_V_read[32'd15]; + +assign tmp_203_fu_2448_p3 = data_35_V_read[32'd15]; + +assign tmp_204_fu_2462_p3 = {{xor_ln1495_66_fu_2456_p2}, {10'd0}}; + +assign tmp_205_fu_2488_p3 = data_36_V_read[32'd15]; + +assign tmp_206_fu_2502_p3 = data_36_V_read[32'd15]; + +assign tmp_207_fu_2516_p3 = {{xor_ln1495_67_fu_2510_p2}, {10'd0}}; + +assign tmp_208_fu_2542_p3 = data_37_V_read[32'd15]; + +assign tmp_209_fu_2556_p3 = data_37_V_read[32'd15]; + +assign tmp_210_fu_2570_p3 = {{xor_ln1495_68_fu_2564_p2}, {10'd0}}; + +assign tmp_211_fu_2596_p3 = data_38_V_read[32'd15]; + +assign tmp_212_fu_2610_p3 = data_38_V_read[32'd15]; + +assign tmp_213_fu_2624_p3 = {{xor_ln1495_69_fu_2618_p2}, {10'd0}}; + +assign tmp_214_fu_2650_p3 = data_39_V_read[32'd15]; + +assign tmp_215_fu_2664_p3 = data_39_V_read[32'd15]; + +assign tmp_216_fu_2678_p3 = {{xor_ln1495_70_fu_2672_p2}, {10'd0}}; + +assign tmp_217_fu_2704_p3 = data_40_V_read[32'd15]; + +assign tmp_218_fu_2718_p3 = data_40_V_read[32'd15]; + +assign tmp_219_fu_2732_p3 = {{xor_ln1495_71_fu_2726_p2}, {10'd0}}; + +assign tmp_220_fu_2758_p3 = data_41_V_read[32'd15]; + +assign tmp_221_fu_2772_p3 = data_41_V_read[32'd15]; + +assign tmp_222_fu_2786_p3 = {{xor_ln1495_72_fu_2780_p2}, {10'd0}}; + +assign tmp_223_fu_2812_p3 = data_42_V_read[32'd15]; + +assign tmp_224_fu_2826_p3 = data_42_V_read[32'd15]; + +assign tmp_225_fu_2840_p3 = {{xor_ln1495_73_fu_2834_p2}, {10'd0}}; + +assign tmp_226_fu_2866_p3 = data_43_V_read[32'd15]; + +assign tmp_227_fu_2880_p3 = data_43_V_read[32'd15]; + +assign tmp_228_fu_2894_p3 = {{xor_ln1495_74_fu_2888_p2}, {10'd0}}; + +assign tmp_229_fu_2920_p3 = data_44_V_read[32'd15]; + +assign tmp_230_fu_2934_p3 = data_44_V_read[32'd15]; + +assign tmp_231_fu_2948_p3 = {{xor_ln1495_75_fu_2942_p2}, {10'd0}}; + +assign tmp_232_fu_2974_p3 = data_45_V_read[32'd15]; + +assign tmp_233_fu_2988_p3 = data_45_V_read[32'd15]; + +assign tmp_234_fu_3002_p3 = {{xor_ln1495_76_fu_2996_p2}, {10'd0}}; + +assign tmp_235_fu_3028_p3 = data_46_V_read[32'd15]; + +assign tmp_236_fu_3042_p3 = data_46_V_read[32'd15]; + +assign tmp_237_fu_3056_p3 = {{xor_ln1495_77_fu_3050_p2}, {10'd0}}; + +assign tmp_238_fu_3082_p3 = data_47_V_read[32'd15]; + +assign tmp_239_fu_3096_p3 = data_47_V_read[32'd15]; + +assign tmp_240_fu_3110_p3 = {{xor_ln1495_78_fu_3104_p2}, {10'd0}}; + +assign tmp_241_fu_3136_p3 = data_48_V_read[32'd15]; + +assign tmp_242_fu_3150_p3 = data_48_V_read[32'd15]; + +assign tmp_243_fu_3164_p3 = {{xor_ln1495_79_fu_3158_p2}, {10'd0}}; + +assign tmp_244_fu_3190_p3 = data_49_V_read[32'd15]; + +assign tmp_245_fu_3204_p3 = data_49_V_read[32'd15]; + +assign tmp_246_fu_3218_p3 = {{xor_ln1495_80_fu_3212_p2}, {10'd0}}; + +assign tmp_247_fu_3244_p3 = data_50_V_read[32'd15]; + +assign tmp_248_fu_3258_p3 = data_50_V_read[32'd15]; + +assign tmp_249_fu_3272_p3 = {{xor_ln1495_81_fu_3266_p2}, {10'd0}}; + +assign tmp_250_fu_3298_p3 = data_51_V_read[32'd15]; + +assign tmp_251_fu_3312_p3 = data_51_V_read[32'd15]; + +assign tmp_252_fu_3326_p3 = {{xor_ln1495_82_fu_3320_p2}, {10'd0}}; + +assign tmp_253_fu_3352_p3 = data_52_V_read[32'd15]; + +assign tmp_254_fu_3366_p3 = data_52_V_read[32'd15]; + +assign tmp_255_fu_3380_p3 = {{xor_ln1495_83_fu_3374_p2}, {10'd0}}; + +assign tmp_256_fu_3406_p3 = data_53_V_read[32'd15]; + +assign tmp_257_fu_3420_p3 = data_53_V_read[32'd15]; + +assign tmp_258_fu_3434_p3 = {{xor_ln1495_84_fu_3428_p2}, {10'd0}}; + +assign tmp_259_fu_3460_p3 = data_54_V_read[32'd15]; + +assign tmp_260_fu_3474_p3 = data_54_V_read[32'd15]; + +assign tmp_261_fu_3488_p3 = {{xor_ln1495_85_fu_3482_p2}, {10'd0}}; + +assign tmp_262_fu_3514_p3 = data_55_V_read[32'd15]; + +assign tmp_263_fu_3528_p3 = data_55_V_read[32'd15]; + +assign tmp_264_fu_3542_p3 = {{xor_ln1495_86_fu_3536_p2}, {10'd0}}; + +assign tmp_265_fu_3568_p3 = data_56_V_read[32'd15]; + +assign tmp_266_fu_3582_p3 = data_56_V_read[32'd15]; + +assign tmp_267_fu_3596_p3 = {{xor_ln1495_87_fu_3590_p2}, {10'd0}}; + +assign tmp_268_fu_3622_p3 = data_57_V_read[32'd15]; + +assign tmp_269_fu_3636_p3 = data_57_V_read[32'd15]; + +assign tmp_270_fu_3650_p3 = {{xor_ln1495_88_fu_3644_p2}, {10'd0}}; + +assign tmp_271_fu_3676_p3 = data_58_V_read[32'd15]; + +assign tmp_272_fu_3690_p3 = data_58_V_read[32'd15]; + +assign tmp_273_fu_3704_p3 = {{xor_ln1495_89_fu_3698_p2}, {10'd0}}; + +assign tmp_274_fu_3730_p3 = data_59_V_read[32'd15]; + +assign tmp_275_fu_3744_p3 = data_59_V_read[32'd15]; + +assign tmp_276_fu_3758_p3 = {{xor_ln1495_90_fu_3752_p2}, {10'd0}}; + +assign tmp_277_fu_3784_p3 = data_60_V_read[32'd15]; + +assign tmp_278_fu_3798_p3 = data_60_V_read[32'd15]; + +assign tmp_279_fu_3812_p3 = {{xor_ln1495_91_fu_3806_p2}, {10'd0}}; + +assign tmp_280_fu_3838_p3 = data_61_V_read[32'd15]; + +assign tmp_281_fu_3852_p3 = data_61_V_read[32'd15]; + +assign tmp_282_fu_3866_p3 = {{xor_ln1495_92_fu_3860_p2}, {10'd0}}; + +assign tmp_283_fu_3892_p3 = data_62_V_read[32'd15]; + +assign tmp_284_fu_3906_p3 = data_62_V_read[32'd15]; + +assign tmp_285_fu_3920_p3 = {{xor_ln1495_93_fu_3914_p2}, {10'd0}}; + +assign tmp_286_fu_3946_p3 = data_63_V_read[32'd15]; + +assign tmp_287_fu_3960_p3 = data_63_V_read[32'd15]; + +assign tmp_288_fu_3974_p3 = {{xor_ln1495_94_fu_3968_p2}, {10'd0}}; + +assign tmp_97_fu_544_p3 = data_0_V_read[32'd15]; + +assign tmp_98_fu_558_p3 = data_0_V_read[32'd15]; + +assign tmp_99_fu_572_p3 = {{xor_ln1495_fu_566_p2}, {10'd0}}; + +assign xor_ln1495_32_fu_620_p2 = (tmp_101_fu_612_p3 ^ 1'd1); + +assign xor_ln1495_33_fu_674_p2 = (tmp_104_fu_666_p3 ^ 1'd1); + +assign xor_ln1495_34_fu_728_p2 = (tmp_107_fu_720_p3 ^ 1'd1); + +assign xor_ln1495_35_fu_782_p2 = (tmp_110_fu_774_p3 ^ 1'd1); + +assign xor_ln1495_36_fu_836_p2 = (tmp_113_fu_828_p3 ^ 1'd1); + +assign xor_ln1495_37_fu_890_p2 = (tmp_116_fu_882_p3 ^ 1'd1); + +assign xor_ln1495_38_fu_944_p2 = (tmp_119_fu_936_p3 ^ 1'd1); + +assign xor_ln1495_39_fu_998_p2 = (tmp_122_fu_990_p3 ^ 1'd1); + +assign xor_ln1495_40_fu_1052_p2 = (tmp_125_fu_1044_p3 ^ 1'd1); + +assign xor_ln1495_41_fu_1106_p2 = (tmp_128_fu_1098_p3 ^ 1'd1); + +assign xor_ln1495_42_fu_1160_p2 = (tmp_131_fu_1152_p3 ^ 1'd1); + +assign xor_ln1495_43_fu_1214_p2 = (tmp_134_fu_1206_p3 ^ 1'd1); + +assign xor_ln1495_44_fu_1268_p2 = (tmp_137_fu_1260_p3 ^ 1'd1); + +assign xor_ln1495_45_fu_1322_p2 = (tmp_140_fu_1314_p3 ^ 1'd1); + +assign xor_ln1495_46_fu_1376_p2 = (tmp_143_fu_1368_p3 ^ 1'd1); + +assign xor_ln1495_47_fu_1430_p2 = (tmp_146_fu_1422_p3 ^ 1'd1); + +assign xor_ln1495_48_fu_1484_p2 = (tmp_149_fu_1476_p3 ^ 1'd1); + +assign xor_ln1495_49_fu_1538_p2 = (tmp_152_fu_1530_p3 ^ 1'd1); + +assign xor_ln1495_50_fu_1592_p2 = (tmp_155_fu_1584_p3 ^ 1'd1); + +assign xor_ln1495_51_fu_1646_p2 = (tmp_158_fu_1638_p3 ^ 1'd1); + +assign xor_ln1495_52_fu_1700_p2 = (tmp_161_fu_1692_p3 ^ 1'd1); + +assign xor_ln1495_53_fu_1754_p2 = (tmp_164_fu_1746_p3 ^ 1'd1); + +assign xor_ln1495_54_fu_1808_p2 = (tmp_167_fu_1800_p3 ^ 1'd1); + +assign xor_ln1495_55_fu_1862_p2 = (tmp_170_fu_1854_p3 ^ 1'd1); + +assign xor_ln1495_56_fu_1916_p2 = (tmp_173_fu_1908_p3 ^ 1'd1); + +assign xor_ln1495_57_fu_1970_p2 = (tmp_176_fu_1962_p3 ^ 1'd1); + +assign xor_ln1495_58_fu_2024_p2 = (tmp_179_fu_2016_p3 ^ 1'd1); + +assign xor_ln1495_59_fu_2078_p2 = (tmp_182_fu_2070_p3 ^ 1'd1); + +assign xor_ln1495_60_fu_2132_p2 = (tmp_185_fu_2124_p3 ^ 1'd1); + +assign xor_ln1495_61_fu_2186_p2 = (tmp_188_fu_2178_p3 ^ 1'd1); + +assign xor_ln1495_62_fu_2240_p2 = (tmp_191_fu_2232_p3 ^ 1'd1); + +assign xor_ln1495_63_fu_2294_p2 = (tmp_194_fu_2286_p3 ^ 1'd1); + +assign xor_ln1495_64_fu_2348_p2 = (tmp_197_fu_2340_p3 ^ 1'd1); + +assign xor_ln1495_65_fu_2402_p2 = (tmp_200_fu_2394_p3 ^ 1'd1); + +assign xor_ln1495_66_fu_2456_p2 = (tmp_203_fu_2448_p3 ^ 1'd1); + +assign xor_ln1495_67_fu_2510_p2 = (tmp_206_fu_2502_p3 ^ 1'd1); + +assign xor_ln1495_68_fu_2564_p2 = (tmp_209_fu_2556_p3 ^ 1'd1); + +assign xor_ln1495_69_fu_2618_p2 = (tmp_212_fu_2610_p3 ^ 1'd1); + +assign xor_ln1495_70_fu_2672_p2 = (tmp_215_fu_2664_p3 ^ 1'd1); + +assign xor_ln1495_71_fu_2726_p2 = (tmp_218_fu_2718_p3 ^ 1'd1); + +assign xor_ln1495_72_fu_2780_p2 = (tmp_221_fu_2772_p3 ^ 1'd1); + +assign xor_ln1495_73_fu_2834_p2 = (tmp_224_fu_2826_p3 ^ 1'd1); + +assign xor_ln1495_74_fu_2888_p2 = (tmp_227_fu_2880_p3 ^ 1'd1); + +assign xor_ln1495_75_fu_2942_p2 = (tmp_230_fu_2934_p3 ^ 1'd1); + +assign xor_ln1495_76_fu_2996_p2 = (tmp_233_fu_2988_p3 ^ 1'd1); + +assign xor_ln1495_77_fu_3050_p2 = (tmp_236_fu_3042_p3 ^ 1'd1); + +assign xor_ln1495_78_fu_3104_p2 = (tmp_239_fu_3096_p3 ^ 1'd1); + +assign xor_ln1495_79_fu_3158_p2 = (tmp_242_fu_3150_p3 ^ 1'd1); + +assign xor_ln1495_80_fu_3212_p2 = (tmp_245_fu_3204_p3 ^ 1'd1); + +assign xor_ln1495_81_fu_3266_p2 = (tmp_248_fu_3258_p3 ^ 1'd1); + +assign xor_ln1495_82_fu_3320_p2 = (tmp_251_fu_3312_p3 ^ 1'd1); + +assign xor_ln1495_83_fu_3374_p2 = (tmp_254_fu_3366_p3 ^ 1'd1); + +assign xor_ln1495_84_fu_3428_p2 = (tmp_257_fu_3420_p3 ^ 1'd1); + +assign xor_ln1495_85_fu_3482_p2 = (tmp_260_fu_3474_p3 ^ 1'd1); + +assign xor_ln1495_86_fu_3536_p2 = (tmp_263_fu_3528_p3 ^ 1'd1); + +assign xor_ln1495_87_fu_3590_p2 = (tmp_266_fu_3582_p3 ^ 1'd1); + +assign xor_ln1495_88_fu_3644_p2 = (tmp_269_fu_3636_p3 ^ 1'd1); + +assign xor_ln1495_89_fu_3698_p2 = (tmp_272_fu_3690_p3 ^ 1'd1); + +assign xor_ln1495_90_fu_3752_p2 = (tmp_275_fu_3744_p3 ^ 1'd1); + +assign xor_ln1495_91_fu_3806_p2 = (tmp_278_fu_3798_p3 ^ 1'd1); + +assign xor_ln1495_92_fu_3860_p2 = (tmp_281_fu_3852_p3 ^ 1'd1); + +assign xor_ln1495_93_fu_3914_p2 = (tmp_284_fu_3906_p3 ^ 1'd1); + +assign xor_ln1495_94_fu_3968_p2 = (tmp_287_fu_3960_p3 ^ 1'd1); + +assign xor_ln1495_fu_566_p2 = (tmp_98_fu_558_p3 ^ 1'd1); + +assign zext_ln1495_32_fu_634_p1 = tmp_102_fu_626_p3; + +assign zext_ln1495_33_fu_688_p1 = tmp_105_fu_680_p3; + +assign zext_ln1495_34_fu_742_p1 = tmp_108_fu_734_p3; + +assign zext_ln1495_35_fu_796_p1 = tmp_111_fu_788_p3; + +assign zext_ln1495_36_fu_850_p1 = tmp_114_fu_842_p3; + +assign zext_ln1495_37_fu_904_p1 = tmp_117_fu_896_p3; + +assign zext_ln1495_38_fu_958_p1 = tmp_120_fu_950_p3; + +assign zext_ln1495_39_fu_1012_p1 = tmp_123_fu_1004_p3; + +assign zext_ln1495_40_fu_1066_p1 = tmp_126_fu_1058_p3; + +assign zext_ln1495_41_fu_1120_p1 = tmp_129_fu_1112_p3; + +assign zext_ln1495_42_fu_1174_p1 = tmp_132_fu_1166_p3; + +assign zext_ln1495_43_fu_1228_p1 = tmp_135_fu_1220_p3; + +assign zext_ln1495_44_fu_1282_p1 = tmp_138_fu_1274_p3; + +assign zext_ln1495_45_fu_1336_p1 = tmp_141_fu_1328_p3; + +assign zext_ln1495_46_fu_1390_p1 = tmp_144_fu_1382_p3; + +assign zext_ln1495_47_fu_1444_p1 = tmp_147_fu_1436_p3; + +assign zext_ln1495_48_fu_1498_p1 = tmp_150_fu_1490_p3; + +assign zext_ln1495_49_fu_1552_p1 = tmp_153_fu_1544_p3; + +assign zext_ln1495_50_fu_1606_p1 = tmp_156_fu_1598_p3; + +assign zext_ln1495_51_fu_1660_p1 = tmp_159_fu_1652_p3; + +assign zext_ln1495_52_fu_1714_p1 = tmp_162_fu_1706_p3; + +assign zext_ln1495_53_fu_1768_p1 = tmp_165_fu_1760_p3; + +assign zext_ln1495_54_fu_1822_p1 = tmp_168_fu_1814_p3; + +assign zext_ln1495_55_fu_1876_p1 = tmp_171_fu_1868_p3; + +assign zext_ln1495_56_fu_1930_p1 = tmp_174_fu_1922_p3; + +assign zext_ln1495_57_fu_1984_p1 = tmp_177_fu_1976_p3; + +assign zext_ln1495_58_fu_2038_p1 = tmp_180_fu_2030_p3; + +assign zext_ln1495_59_fu_2092_p1 = tmp_183_fu_2084_p3; + +assign zext_ln1495_60_fu_2146_p1 = tmp_186_fu_2138_p3; + +assign zext_ln1495_61_fu_2200_p1 = tmp_189_fu_2192_p3; + +assign zext_ln1495_62_fu_2254_p1 = tmp_192_fu_2246_p3; + +assign zext_ln1495_63_fu_2308_p1 = tmp_195_fu_2300_p3; + +assign zext_ln1495_64_fu_2362_p1 = tmp_198_fu_2354_p3; + +assign zext_ln1495_65_fu_2416_p1 = tmp_201_fu_2408_p3; + +assign zext_ln1495_66_fu_2470_p1 = tmp_204_fu_2462_p3; + +assign zext_ln1495_67_fu_2524_p1 = tmp_207_fu_2516_p3; + +assign zext_ln1495_68_fu_2578_p1 = tmp_210_fu_2570_p3; + +assign zext_ln1495_69_fu_2632_p1 = tmp_213_fu_2624_p3; + +assign zext_ln1495_70_fu_2686_p1 = tmp_216_fu_2678_p3; + +assign zext_ln1495_71_fu_2740_p1 = tmp_219_fu_2732_p3; + +assign zext_ln1495_72_fu_2794_p1 = tmp_222_fu_2786_p3; + +assign zext_ln1495_73_fu_2848_p1 = tmp_225_fu_2840_p3; + +assign zext_ln1495_74_fu_2902_p1 = tmp_228_fu_2894_p3; + +assign zext_ln1495_75_fu_2956_p1 = tmp_231_fu_2948_p3; + +assign zext_ln1495_76_fu_3010_p1 = tmp_234_fu_3002_p3; + +assign zext_ln1495_77_fu_3064_p1 = tmp_237_fu_3056_p3; + +assign zext_ln1495_78_fu_3118_p1 = tmp_240_fu_3110_p3; + +assign zext_ln1495_79_fu_3172_p1 = tmp_243_fu_3164_p3; + +assign zext_ln1495_80_fu_3226_p1 = tmp_246_fu_3218_p3; + +assign zext_ln1495_81_fu_3280_p1 = tmp_249_fu_3272_p3; + +assign zext_ln1495_82_fu_3334_p1 = tmp_252_fu_3326_p3; + +assign zext_ln1495_83_fu_3388_p1 = tmp_255_fu_3380_p3; + +assign zext_ln1495_84_fu_3442_p1 = tmp_258_fu_3434_p3; + +assign zext_ln1495_85_fu_3496_p1 = tmp_261_fu_3488_p3; + +assign zext_ln1495_86_fu_3550_p1 = tmp_264_fu_3542_p3; + +assign zext_ln1495_87_fu_3604_p1 = tmp_267_fu_3596_p3; + +assign zext_ln1495_88_fu_3658_p1 = tmp_270_fu_3650_p3; + +assign zext_ln1495_89_fu_3712_p1 = tmp_273_fu_3704_p3; + +assign zext_ln1495_90_fu_3766_p1 = tmp_276_fu_3758_p3; + +assign zext_ln1495_91_fu_3820_p1 = tmp_279_fu_3812_p3; + +assign zext_ln1495_92_fu_3874_p1 = tmp_282_fu_3866_p3; + +assign zext_ln1495_93_fu_3928_p1 = tmp_285_fu_3920_p3; + +assign zext_ln1495_94_fu_3982_p1 = tmp_288_fu_3974_p3; + +assign zext_ln1495_fu_580_p1 = tmp_99_fu_572_p3; + +endmodule //relu_max_ap_fixed_ap_fixed_1_relu1_config5_s +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module relu_max_ap_fixed_ap_fixed_1_relu1_config9_s ( + ap_ready, + data_0_V_read, + data_1_V_read, + data_2_V_read, + data_3_V_read, + data_4_V_read, + data_5_V_read, + data_6_V_read, + data_7_V_read, + data_8_V_read, + data_9_V_read, + data_10_V_read, + data_11_V_read, + data_12_V_read, + data_13_V_read, + data_14_V_read, + data_15_V_read, + data_16_V_read, + data_17_V_read, + data_18_V_read, + data_19_V_read, + data_20_V_read, + data_21_V_read, + data_22_V_read, + data_23_V_read, + data_24_V_read, + data_25_V_read, + data_26_V_read, + data_27_V_read, + data_28_V_read, + data_29_V_read, + data_30_V_read, + data_31_V_read, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3, + ap_return_4, + ap_return_5, + ap_return_6, + ap_return_7, + ap_return_8, + ap_return_9, + ap_return_10, + ap_return_11, + ap_return_12, + ap_return_13, + ap_return_14, + ap_return_15, + ap_return_16, + ap_return_17, + ap_return_18, + ap_return_19, + ap_return_20, + ap_return_21, + ap_return_22, + ap_return_23, + ap_return_24, + ap_return_25, + ap_return_26, + ap_return_27, + ap_return_28, + ap_return_29, + ap_return_30, + ap_return_31 +); + + +output ap_ready; +input [15:0] data_0_V_read; +input [15:0] data_1_V_read; +input [15:0] data_2_V_read; +input [15:0] data_3_V_read; +input [15:0] data_4_V_read; +input [15:0] data_5_V_read; +input [15:0] data_6_V_read; +input [15:0] data_7_V_read; +input [15:0] data_8_V_read; +input [15:0] data_9_V_read; +input [15:0] data_10_V_read; +input [15:0] data_11_V_read; +input [15:0] data_12_V_read; +input [15:0] data_13_V_read; +input [15:0] data_14_V_read; +input [15:0] data_15_V_read; +input [15:0] data_16_V_read; +input [15:0] data_17_V_read; +input [15:0] data_18_V_read; +input [15:0] data_19_V_read; +input [15:0] data_20_V_read; +input [15:0] data_21_V_read; +input [15:0] data_22_V_read; +input [15:0] data_23_V_read; +input [15:0] data_24_V_read; +input [15:0] data_25_V_read; +input [15:0] data_26_V_read; +input [15:0] data_27_V_read; +input [15:0] data_28_V_read; +input [15:0] data_29_V_read; +input [15:0] data_30_V_read; +input [15:0] data_31_V_read; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; +output [15:0] ap_return_4; +output [15:0] ap_return_5; +output [15:0] ap_return_6; +output [15:0] ap_return_7; +output [15:0] ap_return_8; +output [15:0] ap_return_9; +output [15:0] ap_return_10; +output [15:0] ap_return_11; +output [15:0] ap_return_12; +output [15:0] ap_return_13; +output [15:0] ap_return_14; +output [15:0] ap_return_15; +output [15:0] ap_return_16; +output [15:0] ap_return_17; +output [15:0] ap_return_18; +output [15:0] ap_return_19; +output [15:0] ap_return_20; +output [15:0] ap_return_21; +output [15:0] ap_return_22; +output [15:0] ap_return_23; +output [15:0] ap_return_24; +output [15:0] ap_return_25; +output [15:0] ap_return_26; +output [15:0] ap_return_27; +output [15:0] ap_return_28; +output [15:0] ap_return_29; +output [15:0] ap_return_30; +output [15:0] ap_return_31; + +wire [0:0] tmp_2_fu_302_p3; +wire [0:0] xor_ln1495_fu_310_p2; +wire [10:0] tmp_3_fu_316_p3; +wire [0:0] tmp_1_fu_288_p3; +wire [0:0] icmp_ln1494_fu_296_p2; +wire [0:0] or_ln1495_fu_328_p2; +wire [15:0] zext_ln1495_fu_324_p1; +wire [0:0] tmp_5_fu_356_p3; +wire [0:0] xor_ln1495_1_fu_364_p2; +wire [10:0] tmp_6_fu_370_p3; +wire [0:0] tmp_4_fu_342_p3; +wire [0:0] icmp_ln1494_1_fu_350_p2; +wire [0:0] or_ln1495_1_fu_382_p2; +wire [15:0] zext_ln1495_1_fu_378_p1; +wire [0:0] tmp_8_fu_410_p3; +wire [0:0] xor_ln1495_2_fu_418_p2; +wire [10:0] tmp_9_fu_424_p3; +wire [0:0] tmp_7_fu_396_p3; +wire [0:0] icmp_ln1494_2_fu_404_p2; +wire [0:0] or_ln1495_2_fu_436_p2; +wire [15:0] zext_ln1495_2_fu_432_p1; +wire [0:0] tmp_11_fu_464_p3; +wire [0:0] xor_ln1495_3_fu_472_p2; +wire [10:0] tmp_12_fu_478_p3; +wire [0:0] tmp_10_fu_450_p3; +wire [0:0] icmp_ln1494_3_fu_458_p2; +wire [0:0] or_ln1495_3_fu_490_p2; +wire [15:0] zext_ln1495_3_fu_486_p1; +wire [0:0] tmp_14_fu_518_p3; +wire [0:0] xor_ln1495_4_fu_526_p2; +wire [10:0] tmp_15_fu_532_p3; +wire [0:0] tmp_13_fu_504_p3; +wire [0:0] icmp_ln1494_4_fu_512_p2; +wire [0:0] or_ln1495_4_fu_544_p2; +wire [15:0] zext_ln1495_4_fu_540_p1; +wire [0:0] tmp_17_fu_572_p3; +wire [0:0] xor_ln1495_5_fu_580_p2; +wire [10:0] tmp_18_fu_586_p3; +wire [0:0] tmp_16_fu_558_p3; +wire [0:0] icmp_ln1494_5_fu_566_p2; +wire [0:0] or_ln1495_5_fu_598_p2; +wire [15:0] zext_ln1495_5_fu_594_p1; +wire [0:0] tmp_20_fu_626_p3; +wire [0:0] xor_ln1495_6_fu_634_p2; +wire [10:0] tmp_21_fu_640_p3; +wire [0:0] tmp_19_fu_612_p3; +wire [0:0] icmp_ln1494_6_fu_620_p2; +wire [0:0] or_ln1495_6_fu_652_p2; +wire [15:0] zext_ln1495_6_fu_648_p1; +wire [0:0] tmp_23_fu_680_p3; +wire [0:0] xor_ln1495_7_fu_688_p2; +wire [10:0] tmp_24_fu_694_p3; +wire [0:0] tmp_22_fu_666_p3; +wire [0:0] icmp_ln1494_7_fu_674_p2; +wire [0:0] or_ln1495_7_fu_706_p2; +wire [15:0] zext_ln1495_7_fu_702_p1; +wire [0:0] tmp_26_fu_734_p3; +wire [0:0] xor_ln1495_8_fu_742_p2; +wire [10:0] tmp_27_fu_748_p3; +wire [0:0] tmp_25_fu_720_p3; +wire [0:0] icmp_ln1494_8_fu_728_p2; +wire [0:0] or_ln1495_8_fu_760_p2; +wire [15:0] zext_ln1495_8_fu_756_p1; +wire [0:0] tmp_29_fu_788_p3; +wire [0:0] xor_ln1495_9_fu_796_p2; +wire [10:0] tmp_30_fu_802_p3; +wire [0:0] tmp_28_fu_774_p3; +wire [0:0] icmp_ln1494_9_fu_782_p2; +wire [0:0] or_ln1495_9_fu_814_p2; +wire [15:0] zext_ln1495_9_fu_810_p1; +wire [0:0] tmp_32_fu_842_p3; +wire [0:0] xor_ln1495_10_fu_850_p2; +wire [10:0] tmp_33_fu_856_p3; +wire [0:0] tmp_31_fu_828_p3; +wire [0:0] icmp_ln1494_10_fu_836_p2; +wire [0:0] or_ln1495_10_fu_868_p2; +wire [15:0] zext_ln1495_10_fu_864_p1; +wire [0:0] tmp_35_fu_896_p3; +wire [0:0] xor_ln1495_11_fu_904_p2; +wire [10:0] tmp_36_fu_910_p3; +wire [0:0] tmp_34_fu_882_p3; +wire [0:0] icmp_ln1494_11_fu_890_p2; +wire [0:0] or_ln1495_11_fu_922_p2; +wire [15:0] zext_ln1495_11_fu_918_p1; +wire [0:0] tmp_38_fu_950_p3; +wire [0:0] xor_ln1495_12_fu_958_p2; +wire [10:0] tmp_39_fu_964_p3; +wire [0:0] tmp_37_fu_936_p3; +wire [0:0] icmp_ln1494_12_fu_944_p2; +wire [0:0] or_ln1495_12_fu_976_p2; +wire [15:0] zext_ln1495_12_fu_972_p1; +wire [0:0] tmp_41_fu_1004_p3; +wire [0:0] xor_ln1495_13_fu_1012_p2; +wire [10:0] tmp_42_fu_1018_p3; +wire [0:0] tmp_40_fu_990_p3; +wire [0:0] icmp_ln1494_13_fu_998_p2; +wire [0:0] or_ln1495_13_fu_1030_p2; +wire [15:0] zext_ln1495_13_fu_1026_p1; +wire [0:0] tmp_44_fu_1058_p3; +wire [0:0] xor_ln1495_14_fu_1066_p2; +wire [10:0] tmp_45_fu_1072_p3; +wire [0:0] tmp_43_fu_1044_p3; +wire [0:0] icmp_ln1494_14_fu_1052_p2; +wire [0:0] or_ln1495_14_fu_1084_p2; +wire [15:0] zext_ln1495_14_fu_1080_p1; +wire [0:0] tmp_47_fu_1112_p3; +wire [0:0] xor_ln1495_15_fu_1120_p2; +wire [10:0] tmp_48_fu_1126_p3; +wire [0:0] tmp_46_fu_1098_p3; +wire [0:0] icmp_ln1494_15_fu_1106_p2; +wire [0:0] or_ln1495_15_fu_1138_p2; +wire [15:0] zext_ln1495_15_fu_1134_p1; +wire [0:0] tmp_50_fu_1166_p3; +wire [0:0] xor_ln1495_16_fu_1174_p2; +wire [10:0] tmp_51_fu_1180_p3; +wire [0:0] tmp_49_fu_1152_p3; +wire [0:0] icmp_ln1494_16_fu_1160_p2; +wire [0:0] or_ln1495_16_fu_1192_p2; +wire [15:0] zext_ln1495_16_fu_1188_p1; +wire [0:0] tmp_53_fu_1220_p3; +wire [0:0] xor_ln1495_17_fu_1228_p2; +wire [10:0] tmp_54_fu_1234_p3; +wire [0:0] tmp_52_fu_1206_p3; +wire [0:0] icmp_ln1494_17_fu_1214_p2; +wire [0:0] or_ln1495_17_fu_1246_p2; +wire [15:0] zext_ln1495_17_fu_1242_p1; +wire [0:0] tmp_56_fu_1274_p3; +wire [0:0] xor_ln1495_18_fu_1282_p2; +wire [10:0] tmp_57_fu_1288_p3; +wire [0:0] tmp_55_fu_1260_p3; +wire [0:0] icmp_ln1494_18_fu_1268_p2; +wire [0:0] or_ln1495_18_fu_1300_p2; +wire [15:0] zext_ln1495_18_fu_1296_p1; +wire [0:0] tmp_59_fu_1328_p3; +wire [0:0] xor_ln1495_19_fu_1336_p2; +wire [10:0] tmp_60_fu_1342_p3; +wire [0:0] tmp_58_fu_1314_p3; +wire [0:0] icmp_ln1494_19_fu_1322_p2; +wire [0:0] or_ln1495_19_fu_1354_p2; +wire [15:0] zext_ln1495_19_fu_1350_p1; +wire [0:0] tmp_62_fu_1382_p3; +wire [0:0] xor_ln1495_20_fu_1390_p2; +wire [10:0] tmp_63_fu_1396_p3; +wire [0:0] tmp_61_fu_1368_p3; +wire [0:0] icmp_ln1494_20_fu_1376_p2; +wire [0:0] or_ln1495_20_fu_1408_p2; +wire [15:0] zext_ln1495_20_fu_1404_p1; +wire [0:0] tmp_65_fu_1436_p3; +wire [0:0] xor_ln1495_21_fu_1444_p2; +wire [10:0] tmp_66_fu_1450_p3; +wire [0:0] tmp_64_fu_1422_p3; +wire [0:0] icmp_ln1494_21_fu_1430_p2; +wire [0:0] or_ln1495_21_fu_1462_p2; +wire [15:0] zext_ln1495_21_fu_1458_p1; +wire [0:0] tmp_68_fu_1490_p3; +wire [0:0] xor_ln1495_22_fu_1498_p2; +wire [10:0] tmp_69_fu_1504_p3; +wire [0:0] tmp_67_fu_1476_p3; +wire [0:0] icmp_ln1494_22_fu_1484_p2; +wire [0:0] or_ln1495_22_fu_1516_p2; +wire [15:0] zext_ln1495_22_fu_1512_p1; +wire [0:0] tmp_71_fu_1544_p3; +wire [0:0] xor_ln1495_23_fu_1552_p2; +wire [10:0] tmp_72_fu_1558_p3; +wire [0:0] tmp_70_fu_1530_p3; +wire [0:0] icmp_ln1494_23_fu_1538_p2; +wire [0:0] or_ln1495_23_fu_1570_p2; +wire [15:0] zext_ln1495_23_fu_1566_p1; +wire [0:0] tmp_74_fu_1598_p3; +wire [0:0] xor_ln1495_24_fu_1606_p2; +wire [10:0] tmp_75_fu_1612_p3; +wire [0:0] tmp_73_fu_1584_p3; +wire [0:0] icmp_ln1494_24_fu_1592_p2; +wire [0:0] or_ln1495_24_fu_1624_p2; +wire [15:0] zext_ln1495_24_fu_1620_p1; +wire [0:0] tmp_77_fu_1652_p3; +wire [0:0] xor_ln1495_25_fu_1660_p2; +wire [10:0] tmp_78_fu_1666_p3; +wire [0:0] tmp_76_fu_1638_p3; +wire [0:0] icmp_ln1494_25_fu_1646_p2; +wire [0:0] or_ln1495_25_fu_1678_p2; +wire [15:0] zext_ln1495_25_fu_1674_p1; +wire [0:0] tmp_80_fu_1706_p3; +wire [0:0] xor_ln1495_26_fu_1714_p2; +wire [10:0] tmp_81_fu_1720_p3; +wire [0:0] tmp_79_fu_1692_p3; +wire [0:0] icmp_ln1494_26_fu_1700_p2; +wire [0:0] or_ln1495_26_fu_1732_p2; +wire [15:0] zext_ln1495_26_fu_1728_p1; +wire [0:0] tmp_83_fu_1760_p3; +wire [0:0] xor_ln1495_27_fu_1768_p2; +wire [10:0] tmp_84_fu_1774_p3; +wire [0:0] tmp_82_fu_1746_p3; +wire [0:0] icmp_ln1494_27_fu_1754_p2; +wire [0:0] or_ln1495_27_fu_1786_p2; +wire [15:0] zext_ln1495_27_fu_1782_p1; +wire [0:0] tmp_86_fu_1814_p3; +wire [0:0] xor_ln1495_28_fu_1822_p2; +wire [10:0] tmp_87_fu_1828_p3; +wire [0:0] tmp_85_fu_1800_p3; +wire [0:0] icmp_ln1494_28_fu_1808_p2; +wire [0:0] or_ln1495_28_fu_1840_p2; +wire [15:0] zext_ln1495_28_fu_1836_p1; +wire [0:0] tmp_89_fu_1868_p3; +wire [0:0] xor_ln1495_29_fu_1876_p2; +wire [10:0] tmp_90_fu_1882_p3; +wire [0:0] tmp_88_fu_1854_p3; +wire [0:0] icmp_ln1494_29_fu_1862_p2; +wire [0:0] or_ln1495_29_fu_1894_p2; +wire [15:0] zext_ln1495_29_fu_1890_p1; +wire [0:0] tmp_92_fu_1922_p3; +wire [0:0] xor_ln1495_30_fu_1930_p2; +wire [10:0] tmp_93_fu_1936_p3; +wire [0:0] tmp_91_fu_1908_p3; +wire [0:0] icmp_ln1494_30_fu_1916_p2; +wire [0:0] or_ln1495_30_fu_1948_p2; +wire [15:0] zext_ln1495_30_fu_1944_p1; +wire [0:0] tmp_95_fu_1976_p3; +wire [0:0] xor_ln1495_31_fu_1984_p2; +wire [10:0] tmp_96_fu_1990_p3; +wire [0:0] tmp_94_fu_1962_p3; +wire [0:0] icmp_ln1494_31_fu_1970_p2; +wire [0:0] or_ln1495_31_fu_2002_p2; +wire [15:0] zext_ln1495_31_fu_1998_p1; +wire [15:0] select_ln1495_fu_334_p3; +wire [15:0] select_ln1495_1_fu_388_p3; +wire [15:0] select_ln1495_2_fu_442_p3; +wire [15:0] select_ln1495_3_fu_496_p3; +wire [15:0] select_ln1495_4_fu_550_p3; +wire [15:0] select_ln1495_5_fu_604_p3; +wire [15:0] select_ln1495_6_fu_658_p3; +wire [15:0] select_ln1495_7_fu_712_p3; +wire [15:0] select_ln1495_8_fu_766_p3; +wire [15:0] select_ln1495_9_fu_820_p3; +wire [15:0] select_ln1495_10_fu_874_p3; +wire [15:0] select_ln1495_11_fu_928_p3; +wire [15:0] select_ln1495_12_fu_982_p3; +wire [15:0] select_ln1495_13_fu_1036_p3; +wire [15:0] select_ln1495_14_fu_1090_p3; +wire [15:0] select_ln1495_15_fu_1144_p3; +wire [15:0] select_ln1495_16_fu_1198_p3; +wire [15:0] select_ln1495_17_fu_1252_p3; +wire [15:0] select_ln1495_18_fu_1306_p3; +wire [15:0] select_ln1495_19_fu_1360_p3; +wire [15:0] select_ln1495_20_fu_1414_p3; +wire [15:0] select_ln1495_21_fu_1468_p3; +wire [15:0] select_ln1495_22_fu_1522_p3; +wire [15:0] select_ln1495_23_fu_1576_p3; +wire [15:0] select_ln1495_24_fu_1630_p3; +wire [15:0] select_ln1495_25_fu_1684_p3; +wire [15:0] select_ln1495_26_fu_1738_p3; +wire [15:0] select_ln1495_27_fu_1792_p3; +wire [15:0] select_ln1495_28_fu_1846_p3; +wire [15:0] select_ln1495_29_fu_1900_p3; +wire [15:0] select_ln1495_30_fu_1954_p3; +wire [15:0] select_ln1495_31_fu_2008_p3; + +assign ap_ready = 1'b1; + +assign ap_return_0 = select_ln1495_fu_334_p3; + +assign ap_return_1 = select_ln1495_1_fu_388_p3; + +assign ap_return_10 = select_ln1495_10_fu_874_p3; + +assign ap_return_11 = select_ln1495_11_fu_928_p3; + +assign ap_return_12 = select_ln1495_12_fu_982_p3; + +assign ap_return_13 = select_ln1495_13_fu_1036_p3; + +assign ap_return_14 = select_ln1495_14_fu_1090_p3; + +assign ap_return_15 = select_ln1495_15_fu_1144_p3; + +assign ap_return_16 = select_ln1495_16_fu_1198_p3; + +assign ap_return_17 = select_ln1495_17_fu_1252_p3; + +assign ap_return_18 = select_ln1495_18_fu_1306_p3; + +assign ap_return_19 = select_ln1495_19_fu_1360_p3; + +assign ap_return_2 = select_ln1495_2_fu_442_p3; + +assign ap_return_20 = select_ln1495_20_fu_1414_p3; + +assign ap_return_21 = select_ln1495_21_fu_1468_p3; + +assign ap_return_22 = select_ln1495_22_fu_1522_p3; + +assign ap_return_23 = select_ln1495_23_fu_1576_p3; + +assign ap_return_24 = select_ln1495_24_fu_1630_p3; + +assign ap_return_25 = select_ln1495_25_fu_1684_p3; + +assign ap_return_26 = select_ln1495_26_fu_1738_p3; + +assign ap_return_27 = select_ln1495_27_fu_1792_p3; + +assign ap_return_28 = select_ln1495_28_fu_1846_p3; + +assign ap_return_29 = select_ln1495_29_fu_1900_p3; + +assign ap_return_3 = select_ln1495_3_fu_496_p3; + +assign ap_return_30 = select_ln1495_30_fu_1954_p3; + +assign ap_return_31 = select_ln1495_31_fu_2008_p3; + +assign ap_return_4 = select_ln1495_4_fu_550_p3; + +assign ap_return_5 = select_ln1495_5_fu_604_p3; + +assign ap_return_6 = select_ln1495_6_fu_658_p3; + +assign ap_return_7 = select_ln1495_7_fu_712_p3; + +assign ap_return_8 = select_ln1495_8_fu_766_p3; + +assign ap_return_9 = select_ln1495_9_fu_820_p3; + +assign icmp_ln1494_10_fu_836_p2 = (((data_10_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_11_fu_890_p2 = (((data_11_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_12_fu_944_p2 = (((data_12_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_13_fu_998_p2 = (((data_13_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_14_fu_1052_p2 = (((data_14_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_15_fu_1106_p2 = (((data_15_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_16_fu_1160_p2 = (((data_16_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_17_fu_1214_p2 = (((data_17_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_18_fu_1268_p2 = (((data_18_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_19_fu_1322_p2 = (((data_19_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_1_fu_350_p2 = (((data_1_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_20_fu_1376_p2 = (((data_20_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_21_fu_1430_p2 = (((data_21_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_22_fu_1484_p2 = (((data_22_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_23_fu_1538_p2 = (((data_23_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_24_fu_1592_p2 = (((data_24_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_25_fu_1646_p2 = (((data_25_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_26_fu_1700_p2 = (((data_26_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_27_fu_1754_p2 = (((data_27_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_28_fu_1808_p2 = (((data_28_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_29_fu_1862_p2 = (((data_29_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_2_fu_404_p2 = (((data_2_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_30_fu_1916_p2 = (((data_30_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_31_fu_1970_p2 = (((data_31_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_3_fu_458_p2 = (((data_3_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_4_fu_512_p2 = (((data_4_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_5_fu_566_p2 = (((data_5_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_6_fu_620_p2 = (((data_6_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_7_fu_674_p2 = (((data_7_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_8_fu_728_p2 = (((data_8_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_9_fu_782_p2 = (((data_9_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign icmp_ln1494_fu_296_p2 = (((data_0_V_read) > (16'd1024)) ? 1'b1 : 1'b0); + +assign or_ln1495_10_fu_868_p2 = (tmp_31_fu_828_p3 | icmp_ln1494_10_fu_836_p2); + +assign or_ln1495_11_fu_922_p2 = (tmp_34_fu_882_p3 | icmp_ln1494_11_fu_890_p2); + +assign or_ln1495_12_fu_976_p2 = (tmp_37_fu_936_p3 | icmp_ln1494_12_fu_944_p2); + +assign or_ln1495_13_fu_1030_p2 = (tmp_40_fu_990_p3 | icmp_ln1494_13_fu_998_p2); + +assign or_ln1495_14_fu_1084_p2 = (tmp_43_fu_1044_p3 | icmp_ln1494_14_fu_1052_p2); + +assign or_ln1495_15_fu_1138_p2 = (tmp_46_fu_1098_p3 | icmp_ln1494_15_fu_1106_p2); + +assign or_ln1495_16_fu_1192_p2 = (tmp_49_fu_1152_p3 | icmp_ln1494_16_fu_1160_p2); + +assign or_ln1495_17_fu_1246_p2 = (tmp_52_fu_1206_p3 | icmp_ln1494_17_fu_1214_p2); + +assign or_ln1495_18_fu_1300_p2 = (tmp_55_fu_1260_p3 | icmp_ln1494_18_fu_1268_p2); + +assign or_ln1495_19_fu_1354_p2 = (tmp_58_fu_1314_p3 | icmp_ln1494_19_fu_1322_p2); + +assign or_ln1495_1_fu_382_p2 = (tmp_4_fu_342_p3 | icmp_ln1494_1_fu_350_p2); + +assign or_ln1495_20_fu_1408_p2 = (tmp_61_fu_1368_p3 | icmp_ln1494_20_fu_1376_p2); + +assign or_ln1495_21_fu_1462_p2 = (tmp_64_fu_1422_p3 | icmp_ln1494_21_fu_1430_p2); + +assign or_ln1495_22_fu_1516_p2 = (tmp_67_fu_1476_p3 | icmp_ln1494_22_fu_1484_p2); + +assign or_ln1495_23_fu_1570_p2 = (tmp_70_fu_1530_p3 | icmp_ln1494_23_fu_1538_p2); + +assign or_ln1495_24_fu_1624_p2 = (tmp_73_fu_1584_p3 | icmp_ln1494_24_fu_1592_p2); + +assign or_ln1495_25_fu_1678_p2 = (tmp_76_fu_1638_p3 | icmp_ln1494_25_fu_1646_p2); + +assign or_ln1495_26_fu_1732_p2 = (tmp_79_fu_1692_p3 | icmp_ln1494_26_fu_1700_p2); + +assign or_ln1495_27_fu_1786_p2 = (tmp_82_fu_1746_p3 | icmp_ln1494_27_fu_1754_p2); + +assign or_ln1495_28_fu_1840_p2 = (tmp_85_fu_1800_p3 | icmp_ln1494_28_fu_1808_p2); + +assign or_ln1495_29_fu_1894_p2 = (tmp_88_fu_1854_p3 | icmp_ln1494_29_fu_1862_p2); + +assign or_ln1495_2_fu_436_p2 = (tmp_7_fu_396_p3 | icmp_ln1494_2_fu_404_p2); + +assign or_ln1495_30_fu_1948_p2 = (tmp_91_fu_1908_p3 | icmp_ln1494_30_fu_1916_p2); + +assign or_ln1495_31_fu_2002_p2 = (tmp_94_fu_1962_p3 | icmp_ln1494_31_fu_1970_p2); + +assign or_ln1495_3_fu_490_p2 = (tmp_10_fu_450_p3 | icmp_ln1494_3_fu_458_p2); + +assign or_ln1495_4_fu_544_p2 = (tmp_13_fu_504_p3 | icmp_ln1494_4_fu_512_p2); + +assign or_ln1495_5_fu_598_p2 = (tmp_16_fu_558_p3 | icmp_ln1494_5_fu_566_p2); + +assign or_ln1495_6_fu_652_p2 = (tmp_19_fu_612_p3 | icmp_ln1494_6_fu_620_p2); + +assign or_ln1495_7_fu_706_p2 = (tmp_22_fu_666_p3 | icmp_ln1494_7_fu_674_p2); + +assign or_ln1495_8_fu_760_p2 = (tmp_25_fu_720_p3 | icmp_ln1494_8_fu_728_p2); + +assign or_ln1495_9_fu_814_p2 = (tmp_28_fu_774_p3 | icmp_ln1494_9_fu_782_p2); + +assign or_ln1495_fu_328_p2 = (tmp_1_fu_288_p3 | icmp_ln1494_fu_296_p2); + +assign select_ln1495_10_fu_874_p3 = ((or_ln1495_10_fu_868_p2[0:0] == 1'b1) ? zext_ln1495_10_fu_864_p1 : data_10_V_read); + +assign select_ln1495_11_fu_928_p3 = ((or_ln1495_11_fu_922_p2[0:0] == 1'b1) ? zext_ln1495_11_fu_918_p1 : data_11_V_read); + +assign select_ln1495_12_fu_982_p3 = ((or_ln1495_12_fu_976_p2[0:0] == 1'b1) ? zext_ln1495_12_fu_972_p1 : data_12_V_read); + +assign select_ln1495_13_fu_1036_p3 = ((or_ln1495_13_fu_1030_p2[0:0] == 1'b1) ? zext_ln1495_13_fu_1026_p1 : data_13_V_read); + +assign select_ln1495_14_fu_1090_p3 = ((or_ln1495_14_fu_1084_p2[0:0] == 1'b1) ? zext_ln1495_14_fu_1080_p1 : data_14_V_read); + +assign select_ln1495_15_fu_1144_p3 = ((or_ln1495_15_fu_1138_p2[0:0] == 1'b1) ? zext_ln1495_15_fu_1134_p1 : data_15_V_read); + +assign select_ln1495_16_fu_1198_p3 = ((or_ln1495_16_fu_1192_p2[0:0] == 1'b1) ? zext_ln1495_16_fu_1188_p1 : data_16_V_read); + +assign select_ln1495_17_fu_1252_p3 = ((or_ln1495_17_fu_1246_p2[0:0] == 1'b1) ? zext_ln1495_17_fu_1242_p1 : data_17_V_read); + +assign select_ln1495_18_fu_1306_p3 = ((or_ln1495_18_fu_1300_p2[0:0] == 1'b1) ? zext_ln1495_18_fu_1296_p1 : data_18_V_read); + +assign select_ln1495_19_fu_1360_p3 = ((or_ln1495_19_fu_1354_p2[0:0] == 1'b1) ? zext_ln1495_19_fu_1350_p1 : data_19_V_read); + +assign select_ln1495_1_fu_388_p3 = ((or_ln1495_1_fu_382_p2[0:0] == 1'b1) ? zext_ln1495_1_fu_378_p1 : data_1_V_read); + +assign select_ln1495_20_fu_1414_p3 = ((or_ln1495_20_fu_1408_p2[0:0] == 1'b1) ? zext_ln1495_20_fu_1404_p1 : data_20_V_read); + +assign select_ln1495_21_fu_1468_p3 = ((or_ln1495_21_fu_1462_p2[0:0] == 1'b1) ? zext_ln1495_21_fu_1458_p1 : data_21_V_read); + +assign select_ln1495_22_fu_1522_p3 = ((or_ln1495_22_fu_1516_p2[0:0] == 1'b1) ? zext_ln1495_22_fu_1512_p1 : data_22_V_read); + +assign select_ln1495_23_fu_1576_p3 = ((or_ln1495_23_fu_1570_p2[0:0] == 1'b1) ? zext_ln1495_23_fu_1566_p1 : data_23_V_read); + +assign select_ln1495_24_fu_1630_p3 = ((or_ln1495_24_fu_1624_p2[0:0] == 1'b1) ? zext_ln1495_24_fu_1620_p1 : data_24_V_read); + +assign select_ln1495_25_fu_1684_p3 = ((or_ln1495_25_fu_1678_p2[0:0] == 1'b1) ? zext_ln1495_25_fu_1674_p1 : data_25_V_read); + +assign select_ln1495_26_fu_1738_p3 = ((or_ln1495_26_fu_1732_p2[0:0] == 1'b1) ? zext_ln1495_26_fu_1728_p1 : data_26_V_read); + +assign select_ln1495_27_fu_1792_p3 = ((or_ln1495_27_fu_1786_p2[0:0] == 1'b1) ? zext_ln1495_27_fu_1782_p1 : data_27_V_read); + +assign select_ln1495_28_fu_1846_p3 = ((or_ln1495_28_fu_1840_p2[0:0] == 1'b1) ? zext_ln1495_28_fu_1836_p1 : data_28_V_read); + +assign select_ln1495_29_fu_1900_p3 = ((or_ln1495_29_fu_1894_p2[0:0] == 1'b1) ? zext_ln1495_29_fu_1890_p1 : data_29_V_read); + +assign select_ln1495_2_fu_442_p3 = ((or_ln1495_2_fu_436_p2[0:0] == 1'b1) ? zext_ln1495_2_fu_432_p1 : data_2_V_read); + +assign select_ln1495_30_fu_1954_p3 = ((or_ln1495_30_fu_1948_p2[0:0] == 1'b1) ? zext_ln1495_30_fu_1944_p1 : data_30_V_read); + +assign select_ln1495_31_fu_2008_p3 = ((or_ln1495_31_fu_2002_p2[0:0] == 1'b1) ? zext_ln1495_31_fu_1998_p1 : data_31_V_read); + +assign select_ln1495_3_fu_496_p3 = ((or_ln1495_3_fu_490_p2[0:0] == 1'b1) ? zext_ln1495_3_fu_486_p1 : data_3_V_read); + +assign select_ln1495_4_fu_550_p3 = ((or_ln1495_4_fu_544_p2[0:0] == 1'b1) ? zext_ln1495_4_fu_540_p1 : data_4_V_read); + +assign select_ln1495_5_fu_604_p3 = ((or_ln1495_5_fu_598_p2[0:0] == 1'b1) ? zext_ln1495_5_fu_594_p1 : data_5_V_read); + +assign select_ln1495_6_fu_658_p3 = ((or_ln1495_6_fu_652_p2[0:0] == 1'b1) ? zext_ln1495_6_fu_648_p1 : data_6_V_read); + +assign select_ln1495_7_fu_712_p3 = ((or_ln1495_7_fu_706_p2[0:0] == 1'b1) ? zext_ln1495_7_fu_702_p1 : data_7_V_read); + +assign select_ln1495_8_fu_766_p3 = ((or_ln1495_8_fu_760_p2[0:0] == 1'b1) ? zext_ln1495_8_fu_756_p1 : data_8_V_read); + +assign select_ln1495_9_fu_820_p3 = ((or_ln1495_9_fu_814_p2[0:0] == 1'b1) ? zext_ln1495_9_fu_810_p1 : data_9_V_read); + +assign select_ln1495_fu_334_p3 = ((or_ln1495_fu_328_p2[0:0] == 1'b1) ? zext_ln1495_fu_324_p1 : data_0_V_read); + +assign tmp_10_fu_450_p3 = data_3_V_read[32'd15]; + +assign tmp_11_fu_464_p3 = data_3_V_read[32'd15]; + +assign tmp_12_fu_478_p3 = {{xor_ln1495_3_fu_472_p2}, {10'd0}}; + +assign tmp_13_fu_504_p3 = data_4_V_read[32'd15]; + +assign tmp_14_fu_518_p3 = data_4_V_read[32'd15]; + +assign tmp_15_fu_532_p3 = {{xor_ln1495_4_fu_526_p2}, {10'd0}}; + +assign tmp_16_fu_558_p3 = data_5_V_read[32'd15]; + +assign tmp_17_fu_572_p3 = data_5_V_read[32'd15]; + +assign tmp_18_fu_586_p3 = {{xor_ln1495_5_fu_580_p2}, {10'd0}}; + +assign tmp_19_fu_612_p3 = data_6_V_read[32'd15]; + +assign tmp_1_fu_288_p3 = data_0_V_read[32'd15]; + +assign tmp_20_fu_626_p3 = data_6_V_read[32'd15]; + +assign tmp_21_fu_640_p3 = {{xor_ln1495_6_fu_634_p2}, {10'd0}}; + +assign tmp_22_fu_666_p3 = data_7_V_read[32'd15]; + +assign tmp_23_fu_680_p3 = data_7_V_read[32'd15]; + +assign tmp_24_fu_694_p3 = {{xor_ln1495_7_fu_688_p2}, {10'd0}}; + +assign tmp_25_fu_720_p3 = data_8_V_read[32'd15]; + +assign tmp_26_fu_734_p3 = data_8_V_read[32'd15]; + +assign tmp_27_fu_748_p3 = {{xor_ln1495_8_fu_742_p2}, {10'd0}}; + +assign tmp_28_fu_774_p3 = data_9_V_read[32'd15]; + +assign tmp_29_fu_788_p3 = data_9_V_read[32'd15]; + +assign tmp_2_fu_302_p3 = data_0_V_read[32'd15]; + +assign tmp_30_fu_802_p3 = {{xor_ln1495_9_fu_796_p2}, {10'd0}}; + +assign tmp_31_fu_828_p3 = data_10_V_read[32'd15]; + +assign tmp_32_fu_842_p3 = data_10_V_read[32'd15]; + +assign tmp_33_fu_856_p3 = {{xor_ln1495_10_fu_850_p2}, {10'd0}}; + +assign tmp_34_fu_882_p3 = data_11_V_read[32'd15]; + +assign tmp_35_fu_896_p3 = data_11_V_read[32'd15]; + +assign tmp_36_fu_910_p3 = {{xor_ln1495_11_fu_904_p2}, {10'd0}}; + +assign tmp_37_fu_936_p3 = data_12_V_read[32'd15]; + +assign tmp_38_fu_950_p3 = data_12_V_read[32'd15]; + +assign tmp_39_fu_964_p3 = {{xor_ln1495_12_fu_958_p2}, {10'd0}}; + +assign tmp_3_fu_316_p3 = {{xor_ln1495_fu_310_p2}, {10'd0}}; + +assign tmp_40_fu_990_p3 = data_13_V_read[32'd15]; + +assign tmp_41_fu_1004_p3 = data_13_V_read[32'd15]; + +assign tmp_42_fu_1018_p3 = {{xor_ln1495_13_fu_1012_p2}, {10'd0}}; + +assign tmp_43_fu_1044_p3 = data_14_V_read[32'd15]; + +assign tmp_44_fu_1058_p3 = data_14_V_read[32'd15]; + +assign tmp_45_fu_1072_p3 = {{xor_ln1495_14_fu_1066_p2}, {10'd0}}; + +assign tmp_46_fu_1098_p3 = data_15_V_read[32'd15]; + +assign tmp_47_fu_1112_p3 = data_15_V_read[32'd15]; + +assign tmp_48_fu_1126_p3 = {{xor_ln1495_15_fu_1120_p2}, {10'd0}}; + +assign tmp_49_fu_1152_p3 = data_16_V_read[32'd15]; + +assign tmp_4_fu_342_p3 = data_1_V_read[32'd15]; + +assign tmp_50_fu_1166_p3 = data_16_V_read[32'd15]; + +assign tmp_51_fu_1180_p3 = {{xor_ln1495_16_fu_1174_p2}, {10'd0}}; + +assign tmp_52_fu_1206_p3 = data_17_V_read[32'd15]; + +assign tmp_53_fu_1220_p3 = data_17_V_read[32'd15]; + +assign tmp_54_fu_1234_p3 = {{xor_ln1495_17_fu_1228_p2}, {10'd0}}; + +assign tmp_55_fu_1260_p3 = data_18_V_read[32'd15]; + +assign tmp_56_fu_1274_p3 = data_18_V_read[32'd15]; + +assign tmp_57_fu_1288_p3 = {{xor_ln1495_18_fu_1282_p2}, {10'd0}}; + +assign tmp_58_fu_1314_p3 = data_19_V_read[32'd15]; + +assign tmp_59_fu_1328_p3 = data_19_V_read[32'd15]; + +assign tmp_5_fu_356_p3 = data_1_V_read[32'd15]; + +assign tmp_60_fu_1342_p3 = {{xor_ln1495_19_fu_1336_p2}, {10'd0}}; + +assign tmp_61_fu_1368_p3 = data_20_V_read[32'd15]; + +assign tmp_62_fu_1382_p3 = data_20_V_read[32'd15]; + +assign tmp_63_fu_1396_p3 = {{xor_ln1495_20_fu_1390_p2}, {10'd0}}; + +assign tmp_64_fu_1422_p3 = data_21_V_read[32'd15]; + +assign tmp_65_fu_1436_p3 = data_21_V_read[32'd15]; + +assign tmp_66_fu_1450_p3 = {{xor_ln1495_21_fu_1444_p2}, {10'd0}}; + +assign tmp_67_fu_1476_p3 = data_22_V_read[32'd15]; + +assign tmp_68_fu_1490_p3 = data_22_V_read[32'd15]; + +assign tmp_69_fu_1504_p3 = {{xor_ln1495_22_fu_1498_p2}, {10'd0}}; + +assign tmp_6_fu_370_p3 = {{xor_ln1495_1_fu_364_p2}, {10'd0}}; + +assign tmp_70_fu_1530_p3 = data_23_V_read[32'd15]; + +assign tmp_71_fu_1544_p3 = data_23_V_read[32'd15]; + +assign tmp_72_fu_1558_p3 = {{xor_ln1495_23_fu_1552_p2}, {10'd0}}; + +assign tmp_73_fu_1584_p3 = data_24_V_read[32'd15]; + +assign tmp_74_fu_1598_p3 = data_24_V_read[32'd15]; + +assign tmp_75_fu_1612_p3 = {{xor_ln1495_24_fu_1606_p2}, {10'd0}}; + +assign tmp_76_fu_1638_p3 = data_25_V_read[32'd15]; + +assign tmp_77_fu_1652_p3 = data_25_V_read[32'd15]; + +assign tmp_78_fu_1666_p3 = {{xor_ln1495_25_fu_1660_p2}, {10'd0}}; + +assign tmp_79_fu_1692_p3 = data_26_V_read[32'd15]; + +assign tmp_7_fu_396_p3 = data_2_V_read[32'd15]; + +assign tmp_80_fu_1706_p3 = data_26_V_read[32'd15]; + +assign tmp_81_fu_1720_p3 = {{xor_ln1495_26_fu_1714_p2}, {10'd0}}; + +assign tmp_82_fu_1746_p3 = data_27_V_read[32'd15]; + +assign tmp_83_fu_1760_p3 = data_27_V_read[32'd15]; + +assign tmp_84_fu_1774_p3 = {{xor_ln1495_27_fu_1768_p2}, {10'd0}}; + +assign tmp_85_fu_1800_p3 = data_28_V_read[32'd15]; + +assign tmp_86_fu_1814_p3 = data_28_V_read[32'd15]; + +assign tmp_87_fu_1828_p3 = {{xor_ln1495_28_fu_1822_p2}, {10'd0}}; + +assign tmp_88_fu_1854_p3 = data_29_V_read[32'd15]; + +assign tmp_89_fu_1868_p3 = data_29_V_read[32'd15]; + +assign tmp_8_fu_410_p3 = data_2_V_read[32'd15]; + +assign tmp_90_fu_1882_p3 = {{xor_ln1495_29_fu_1876_p2}, {10'd0}}; + +assign tmp_91_fu_1908_p3 = data_30_V_read[32'd15]; + +assign tmp_92_fu_1922_p3 = data_30_V_read[32'd15]; + +assign tmp_93_fu_1936_p3 = {{xor_ln1495_30_fu_1930_p2}, {10'd0}}; + +assign tmp_94_fu_1962_p3 = data_31_V_read[32'd15]; + +assign tmp_95_fu_1976_p3 = data_31_V_read[32'd15]; + +assign tmp_96_fu_1990_p3 = {{xor_ln1495_31_fu_1984_p2}, {10'd0}}; + +assign tmp_9_fu_424_p3 = {{xor_ln1495_2_fu_418_p2}, {10'd0}}; + +assign xor_ln1495_10_fu_850_p2 = (tmp_32_fu_842_p3 ^ 1'd1); + +assign xor_ln1495_11_fu_904_p2 = (tmp_35_fu_896_p3 ^ 1'd1); + +assign xor_ln1495_12_fu_958_p2 = (tmp_38_fu_950_p3 ^ 1'd1); + +assign xor_ln1495_13_fu_1012_p2 = (tmp_41_fu_1004_p3 ^ 1'd1); + +assign xor_ln1495_14_fu_1066_p2 = (tmp_44_fu_1058_p3 ^ 1'd1); + +assign xor_ln1495_15_fu_1120_p2 = (tmp_47_fu_1112_p3 ^ 1'd1); + +assign xor_ln1495_16_fu_1174_p2 = (tmp_50_fu_1166_p3 ^ 1'd1); + +assign xor_ln1495_17_fu_1228_p2 = (tmp_53_fu_1220_p3 ^ 1'd1); + +assign xor_ln1495_18_fu_1282_p2 = (tmp_56_fu_1274_p3 ^ 1'd1); + +assign xor_ln1495_19_fu_1336_p2 = (tmp_59_fu_1328_p3 ^ 1'd1); + +assign xor_ln1495_1_fu_364_p2 = (tmp_5_fu_356_p3 ^ 1'd1); + +assign xor_ln1495_20_fu_1390_p2 = (tmp_62_fu_1382_p3 ^ 1'd1); + +assign xor_ln1495_21_fu_1444_p2 = (tmp_65_fu_1436_p3 ^ 1'd1); + +assign xor_ln1495_22_fu_1498_p2 = (tmp_68_fu_1490_p3 ^ 1'd1); + +assign xor_ln1495_23_fu_1552_p2 = (tmp_71_fu_1544_p3 ^ 1'd1); + +assign xor_ln1495_24_fu_1606_p2 = (tmp_74_fu_1598_p3 ^ 1'd1); + +assign xor_ln1495_25_fu_1660_p2 = (tmp_77_fu_1652_p3 ^ 1'd1); + +assign xor_ln1495_26_fu_1714_p2 = (tmp_80_fu_1706_p3 ^ 1'd1); + +assign xor_ln1495_27_fu_1768_p2 = (tmp_83_fu_1760_p3 ^ 1'd1); + +assign xor_ln1495_28_fu_1822_p2 = (tmp_86_fu_1814_p3 ^ 1'd1); + +assign xor_ln1495_29_fu_1876_p2 = (tmp_89_fu_1868_p3 ^ 1'd1); + +assign xor_ln1495_2_fu_418_p2 = (tmp_8_fu_410_p3 ^ 1'd1); + +assign xor_ln1495_30_fu_1930_p2 = (tmp_92_fu_1922_p3 ^ 1'd1); + +assign xor_ln1495_31_fu_1984_p2 = (tmp_95_fu_1976_p3 ^ 1'd1); + +assign xor_ln1495_3_fu_472_p2 = (tmp_11_fu_464_p3 ^ 1'd1); + +assign xor_ln1495_4_fu_526_p2 = (tmp_14_fu_518_p3 ^ 1'd1); + +assign xor_ln1495_5_fu_580_p2 = (tmp_17_fu_572_p3 ^ 1'd1); + +assign xor_ln1495_6_fu_634_p2 = (tmp_20_fu_626_p3 ^ 1'd1); + +assign xor_ln1495_7_fu_688_p2 = (tmp_23_fu_680_p3 ^ 1'd1); + +assign xor_ln1495_8_fu_742_p2 = (tmp_26_fu_734_p3 ^ 1'd1); + +assign xor_ln1495_9_fu_796_p2 = (tmp_29_fu_788_p3 ^ 1'd1); + +assign xor_ln1495_fu_310_p2 = (tmp_2_fu_302_p3 ^ 1'd1); + +assign zext_ln1495_10_fu_864_p1 = tmp_33_fu_856_p3; + +assign zext_ln1495_11_fu_918_p1 = tmp_36_fu_910_p3; + +assign zext_ln1495_12_fu_972_p1 = tmp_39_fu_964_p3; + +assign zext_ln1495_13_fu_1026_p1 = tmp_42_fu_1018_p3; + +assign zext_ln1495_14_fu_1080_p1 = tmp_45_fu_1072_p3; + +assign zext_ln1495_15_fu_1134_p1 = tmp_48_fu_1126_p3; + +assign zext_ln1495_16_fu_1188_p1 = tmp_51_fu_1180_p3; + +assign zext_ln1495_17_fu_1242_p1 = tmp_54_fu_1234_p3; + +assign zext_ln1495_18_fu_1296_p1 = tmp_57_fu_1288_p3; + +assign zext_ln1495_19_fu_1350_p1 = tmp_60_fu_1342_p3; + +assign zext_ln1495_1_fu_378_p1 = tmp_6_fu_370_p3; + +assign zext_ln1495_20_fu_1404_p1 = tmp_63_fu_1396_p3; + +assign zext_ln1495_21_fu_1458_p1 = tmp_66_fu_1450_p3; + +assign zext_ln1495_22_fu_1512_p1 = tmp_69_fu_1504_p3; + +assign zext_ln1495_23_fu_1566_p1 = tmp_72_fu_1558_p3; + +assign zext_ln1495_24_fu_1620_p1 = tmp_75_fu_1612_p3; + +assign zext_ln1495_25_fu_1674_p1 = tmp_78_fu_1666_p3; + +assign zext_ln1495_26_fu_1728_p1 = tmp_81_fu_1720_p3; + +assign zext_ln1495_27_fu_1782_p1 = tmp_84_fu_1774_p3; + +assign zext_ln1495_28_fu_1836_p1 = tmp_87_fu_1828_p3; + +assign zext_ln1495_29_fu_1890_p1 = tmp_90_fu_1882_p3; + +assign zext_ln1495_2_fu_432_p1 = tmp_9_fu_424_p3; + +assign zext_ln1495_30_fu_1944_p1 = tmp_93_fu_1936_p3; + +assign zext_ln1495_31_fu_1998_p1 = tmp_96_fu_1990_p3; + +assign zext_ln1495_3_fu_486_p1 = tmp_12_fu_478_p3; + +assign zext_ln1495_4_fu_540_p1 = tmp_15_fu_532_p3; + +assign zext_ln1495_5_fu_594_p1 = tmp_18_fu_586_p3; + +assign zext_ln1495_6_fu_648_p1 = tmp_21_fu_640_p3; + +assign zext_ln1495_7_fu_702_p1 = tmp_24_fu_694_p3; + +assign zext_ln1495_8_fu_756_p1 = tmp_27_fu_748_p3; + +assign zext_ln1495_9_fu_810_p1 = tmp_30_fu_802_p3; + +assign zext_ln1495_fu_324_p1 = tmp_3_fu_316_p3; + +endmodule //relu_max_ap_fixed_ap_fixed_1_relu1_config9_s + + diff --git a/designs/koios/bnn/bnn_random.sv b/designs/koios/bnn/bnn_random.sv new file mode 100644 index 000000000..40d8d3de3 --- /dev/null +++ b/designs/koios/bnn/bnn_random.sv @@ -0,0 +1,92 @@ +/* + Random inputs for bnn, output selectable +*/ + +`include "../../random_number_generator.sv" + +module bnn_random( + input logic clk, + input logic rst, + input logic ap_ce, + output logic [5:0] addr, + output logic [15:0] data +); + +logic [15:0] ret[63:0]; +assign data = ret[addr]; + +logic [255:0] data_V_read; +RandomNumberGenerator #(256, 255) rng1(clk, rst, data_V_read); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1 bnn( + clk, + rst, + data_V_read, + ret[0], + ret[1], + ret[2], + ret[3], + ret[4], + ret[5], + ret[6], + ret[7], + ret[8], + ret[9], + ret[10], + ret[11], + ret[12], + ret[13], + ret[14], + ret[15], + ret[16], + ret[17], + ret[18], + ret[19], + ret[20], + ret[21], + ret[22], + ret[23], + ret[24], + ret[25], + ret[26], + ret[27], + ret[28], + ret[29], + ret[30], + ret[31], + ret[32], + ret[33], + ret[34], + ret[35], + ret[36], + ret[37], + ret[38], + ret[39], + ret[40], + ret[41], + ret[42], + ret[43], + ret[44], + ret[45], + ret[46], + ret[47], + ret[48], + ret[49], + ret[50], + ret[51], + ret[52], + ret[53], + ret[54], + ret[55], + ret[56], + ret[57], + ret[58], + ret[59], + ret[60], + ret[61], + ret[62], + ret[63] +); + + +endmodule \ No newline at end of file diff --git a/designs/koios/bnn/design.yaml b/designs/koios/bnn/design.yaml new file mode 100644 index 000000000..762d13f63 --- /dev/null +++ b/designs/koios/bnn/design.yaml @@ -0,0 +1 @@ +top: bnn_random diff --git a/designs/koios/bwave_like.fixed.large/bwave_large_random.sv b/designs/koios/bwave_like.fixed.large/bwave_large_random.sv new file mode 100644 index 000000000..3ec320eb3 --- /dev/null +++ b/designs/koios/bwave_like.fixed.large/bwave_large_random.sv @@ -0,0 +1,228 @@ +/* +Randomize input to bwave_large +*/ + +`include "../../random_number_generator.sv" + +`define IN_PRECISION 8 +`define OUT_PRECISION 8 + +`define NUM_TILES 4 + +`define NUM_LDPES 16 +`define DSPS_PER_LDPE 8 +`define DSPS_PER_SUB_LDPE 8 +`define SUB_LDPES_PER_LDPE (`DSPS_PER_LDPE/`DSPS_PER_SUB_LDPE) + +`define MULTS_PER_DSP 2 +`define DSP_X_AVA_INPUT_WIDTH 18 +`define LDPE_X_AVA_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) +`define DSP_Y_AVA_INPUT_WIDTH 19 +`define LDPE_Y_AVA_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) + +`define DSP_AVA_OUTPUT_WIDTH 37 +`define LDPE_AVA_OUTPUT_WIDTH `DSP_AVA_OUTPUT_WIDTH + +`define DSP_USED_INPUT_WIDTH `IN_PRECISION +`define LDPE_USED_INPUT_WIDTH (`DSP_USED_INPUT_WIDTH * `DSPS_PER_LDPE) +`define SUB_LDPE_USED_INPUT_WIDTH (`DSP_USED_INPUT_WIDTH * `DSPS_PER_SUB_LDPE) +`define DSP_X_ZERO_PAD_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) +`define DSP_Y_ZERO_PAD_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) + +`define DSP_USED_OUTPUT_WIDTH 32 +`define LDPE_USED_OUTPUT_WIDTH `DSP_USED_OUTPUT_WIDTH +`define DSP_ZERO_PAD_OUTPUT_WIDTH (`DSP_AVA_OUTPUT_WIDTH - `DSP_USED_OUTPUT_WIDTH) + +`define LDPES_PER_MRF 1 +`define DSPS_PER_MRF (`DSPS_PER_LDPE * `LDPES_PER_MRF) +`define MAT_BRAM_AWIDTH 10 +`define MAT_BRAM_DWIDTH 16 +`define MAT_BRAMS_PER_MRF_SUBSET 8 +`define MRF_AWIDTH (`MAT_BRAM_AWIDTH) +`define MRF_DWIDTH (`MAT_BRAM_DWIDTH * `MAT_BRAMS_PER_MRF_SUBSET) + +`define ORF_DWIDTH 128 //128 + +`define MAX_VRF_DWIDTH 128 +`define DRAM_DWIDTH `VRF_DWIDTH //This is the max of mrf, orf and vrf widths +`define DRAM_AWIDTH `MRF_AWIDTH + +`define LDPES_PER_VRF 1 +`define DSPS_PER_VRF (`DSPS_PER_LDPE * `LDPES_PER_VRF) +`define VEC_BRAM_AWIDTH 10 +`define VEC_BRAM_DWIDTH 16 +`define BRAMS_PER_VRF 8 +`define VRF_AWIDTH `VEC_BRAM_AWIDTH +`define VRF_DWIDTH (`VEC_BRAM_DWIDTH * `BRAMS_PER_VRF) + +`define LDPES_PER_ORF 1 +`define OUTPUTS_PER_LDPE 1 +`define OUT_BRAM_AWIDTH 10 +`define OUT_BRAM_DWIDTH 16 +`define ORF_AWIDTH `OUT_BRAM_AWIDTH +`define OUT_DWIDTH 8 +//`define ORF_DWIDTH `OUT_DWIDTH*`NUM_LDPES + + +`define DESIGN_SIZE `NUM_LDPES +`define DWIDTH `OUT_PRECISION +`define MASK_WIDTH `OUT_PRECISION + +`define ACTIVATION 2'b00 +`define ELT_WISE_MULTIPLY 2'b10 +`define ELT_WISE_ADD 2'b01 +`define BYPASS 2'b11 + +`define ADD_LATENCY 1 +`define LOG_ADD_LATENCY 1 +`define MUL_LATENCY 1 +`define LOG_MUL_LATENCY 1 +`define ACTIVATION_LATENCY 1 +`define TANH_LATENCY `ACTIVATION_LATENCY+1 + + +`define RELU 2'b00 +`define TANH 2'b01 +`define SIGM 2'b10 +//OPCODES + +`define V_RD 0 +`define V_WR 1 +`define M_RD 2 +`define M_WR 3 +`define MV_MUL 4 +`define VV_ADD 5 +`define VV_SUB 6 //QUESTIONED +`define VV_PASS 7 +`define VV_MUL 8 +`define V_RELU 9 +`define V_SIGM 10 +`define V_TANH 11 +`define END_CHAIN 12 + +//MEM_IDS + +`define VRF_0 0 +`define VRF_1 1 +`define VRF_2 2 +`define VRF_3 3 + +`define VRF_4 4 +`define VRF_5 5 +`define VRF_6 6 +`define VRF_7 7 +`define VRF_MUXED 8 +`define DRAM_MEM_ID 9 +`define MFU_0_DSTN_ID 10 +`define MFU_1_DSTN_ID 11 + + +`define MRF_0 0 +`define MRF_1 1 +`define MRF_2 2 +`define MRF_3 3 +`define MRF_4 4 +`define MRF_5 5 +`define MRF_6 6 +`define MRF_7 7 +`define MRF_8 8 +`define MRF_9 9 +`define MRF_10 10 +`define MRF_11 11 +`define MRF_12 12 +`define MRF_13 13 +`define MRF_14 14 +`define MRF_15 15 +`define MRF_16 16 +`define MRF_17 17 +`define MRF_18 18 +`define MRF_19 19 +`define MRF_20 20 +`define MRF_21 21 +`define MRF_22 22 +`define MRF_23 23 +`define MRF_24 24 +`define MRF_25 25 +`define MRF_26 26 +`define MRF_27 27 +`define MRF_28 28 +`define MRF_29 29 +`define MRF_30 30 +`define MRF_31 31 +`define MRF_32 32 +`define MRF_33 33 +`define MRF_34 34 +`define MRF_35 35 +`define MRF_36 36 +`define MRF_37 37 +`define MRF_38 38 +`define MRF_39 39 +`define MRF_40 40 +`define MRF_41 41 +`define MRF_42 42 +`define MRF_43 43 +`define MRF_44 44 +`define MRF_45 45 +`define MRF_46 46 +`define MRF_47 47 +`define MRF_48 48 +`define MRF_49 49 +`define MRF_50 50 +`define MRF_51 51 +`define MRF_52 52 +`define MRF_53 53 +`define MRF_54 54 +`define MRF_55 55 +`define MRF_56 56 +`define MRF_57 57 +`define MRF_58 58 +`define MRF_59 59 +`define MRF_60 60 +`define MRF_61 61 +`define MRF_62 62 +`define MRF_63 63 + +`define MFU_0 0 +`define MFU_1 1 + +`define INSTR_MEM_AWIDTH 10 + +`define NUM_MVM_CYCLES 11 + +`define OPCODE_WIDTH 4 +`define TARGET_OP_WIDTH 7 + +`define INSTR_WIDTH `OPCODE_WIDTH+`TARGET_OP_WIDTH+`DRAM_AWIDTH+`TARGET_OP_WIDTH+`VRF_AWIDTH + `VRF_AWIDTH + +module bwave_large_random ( + input logic clk, + input logic rst, + input logic [`INSTR_WIDTH-1:0] instruction, + output logic [`DRAM_DWIDTH-1:0] output_data_DRAM, + output logic [`DRAM_AWIDTH-1:0] dram_addr, + output logic dram_write_enable, + output logic get_instr, + output logic [`INSTR_MEM_AWIDTH-1:0] get_instr_addr +); + +logic [`DRAM_DWIDTH-1:0] input_data_DRAM; +RandomNumberGenerator #(`DRAM_DWIDTH, 0) rng ( + .clk(clk), + .reset(rst), + .random_number(input_data_DRAM) +); + +NPU npu0( + rst, + instruction, + input_data_DRAM, + output_data_DRAM, + dram_addr, + dram_write_enable, + get_instr, + get_instr_addr, + clk +); + +endmodule + diff --git a/designs/koios/bwave_like.fixed.large/bwave_like.fixed.large.v b/designs/koios/bwave_like.fixed.large/bwave_like.fixed.large.v new file mode 100644 index 000000000..be718c4be --- /dev/null +++ b/designs/koios/bwave_like.fixed.large/bwave_like.fixed.large.v @@ -0,0 +1,8091 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Tanmay Anand +////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////// +// A Microsoft Brainwave Like Design. Uses fixed point precision. +////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM includes.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + +`define IN_PRECISION 8 +`define OUT_PRECISION 8 + +`define NUM_TILES 4 + +`define NUM_LDPES 16 +`define DSPS_PER_LDPE 8 +`define DSPS_PER_SUB_LDPE 8 +`define SUB_LDPES_PER_LDPE (`DSPS_PER_LDPE/`DSPS_PER_SUB_LDPE) + +`define MULTS_PER_DSP 2 +`define DSP_X_AVA_INPUT_WIDTH 18 +`define LDPE_X_AVA_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) +`define DSP_Y_AVA_INPUT_WIDTH 19 +`define LDPE_Y_AVA_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) + +`define DSP_AVA_OUTPUT_WIDTH 37 +`define LDPE_AVA_OUTPUT_WIDTH `DSP_AVA_OUTPUT_WIDTH + +`define DSP_USED_INPUT_WIDTH `IN_PRECISION +`define LDPE_USED_INPUT_WIDTH (`DSP_USED_INPUT_WIDTH * `DSPS_PER_LDPE) +`define SUB_LDPE_USED_INPUT_WIDTH (`DSP_USED_INPUT_WIDTH * `DSPS_PER_SUB_LDPE) +`define DSP_X_ZERO_PAD_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) +`define DSP_Y_ZERO_PAD_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) + +`define DSP_USED_OUTPUT_WIDTH 32 +`define LDPE_USED_OUTPUT_WIDTH `DSP_USED_OUTPUT_WIDTH +`define DSP_ZERO_PAD_OUTPUT_WIDTH (`DSP_AVA_OUTPUT_WIDTH - `DSP_USED_OUTPUT_WIDTH) + +`define LDPES_PER_MRF 1 +`define DSPS_PER_MRF (`DSPS_PER_LDPE * `LDPES_PER_MRF) +`define MAT_BRAM_AWIDTH 10 +`define MAT_BRAM_DWIDTH 16 +`define MAT_BRAMS_PER_MRF_SUBSET 8 +`define MRF_AWIDTH (`MAT_BRAM_AWIDTH) +`define MRF_DWIDTH (`MAT_BRAM_DWIDTH * `MAT_BRAMS_PER_MRF_SUBSET) + +`define ORF_DWIDTH 128 //128 + +`define MAX_VRF_DWIDTH 128 +`define DRAM_DWIDTH `VRF_DWIDTH //This is the max of mrf, orf and vrf widths +`define DRAM_AWIDTH `MRF_AWIDTH + +`define LDPES_PER_VRF 1 +`define DSPS_PER_VRF (`DSPS_PER_LDPE * `LDPES_PER_VRF) +`define VEC_BRAM_AWIDTH 10 +`define VEC_BRAM_DWIDTH 16 +`define BRAMS_PER_VRF 8 +`define VRF_AWIDTH `VEC_BRAM_AWIDTH +`define VRF_DWIDTH (`VEC_BRAM_DWIDTH * `BRAMS_PER_VRF) + +`define LDPES_PER_ORF 1 +`define OUTPUTS_PER_LDPE 1 +`define OUT_BRAM_AWIDTH 10 +`define OUT_BRAM_DWIDTH 16 +`define ORF_AWIDTH `OUT_BRAM_AWIDTH +`define OUT_DWIDTH 8 +//`define ORF_DWIDTH `OUT_DWIDTH*`NUM_LDPES + + +`define DESIGN_SIZE `NUM_LDPES +`define DWIDTH `OUT_PRECISION +`define MASK_WIDTH `OUT_PRECISION + +`define ACTIVATION 2'b00 +`define ELT_WISE_MULTIPLY 2'b10 +`define ELT_WISE_ADD 2'b01 +`define BYPASS 2'b11 + +`define ADD_LATENCY 1 +`define LOG_ADD_LATENCY 1 +`define MUL_LATENCY 1 +`define LOG_MUL_LATENCY 1 +`define ACTIVATION_LATENCY 1 +`define TANH_LATENCY `ACTIVATION_LATENCY+1 + + +`define RELU 2'b00 +`define TANH 2'b01 +`define SIGM 2'b10 +//OPCODES + +`define V_RD 0 +`define V_WR 1 +`define M_RD 2 +`define M_WR 3 +`define MV_MUL 4 +`define VV_ADD 5 +`define VV_SUB 6 //QUESTIONED +`define VV_PASS 7 +`define VV_MUL 8 +`define V_RELU 9 +`define V_SIGM 10 +`define V_TANH 11 +`define END_CHAIN 12 + +//MEM_IDS + +`define VRF_0 0 +`define VRF_1 1 +`define VRF_2 2 +`define VRF_3 3 + +`define VRF_4 4 +`define VRF_5 5 +`define VRF_6 6 +`define VRF_7 7 +`define VRF_MUXED 8 +`define DRAM_MEM_ID 9 +`define MFU_0_DSTN_ID 10 +`define MFU_1_DSTN_ID 11 + + +`define MRF_0 0 +`define MRF_1 1 +`define MRF_2 2 +`define MRF_3 3 +`define MRF_4 4 +`define MRF_5 5 +`define MRF_6 6 +`define MRF_7 7 +`define MRF_8 8 +`define MRF_9 9 +`define MRF_10 10 +`define MRF_11 11 +`define MRF_12 12 +`define MRF_13 13 +`define MRF_14 14 +`define MRF_15 15 +`define MRF_16 16 +`define MRF_17 17 +`define MRF_18 18 +`define MRF_19 19 +`define MRF_20 20 +`define MRF_21 21 +`define MRF_22 22 +`define MRF_23 23 +`define MRF_24 24 +`define MRF_25 25 +`define MRF_26 26 +`define MRF_27 27 +`define MRF_28 28 +`define MRF_29 29 +`define MRF_30 30 +`define MRF_31 31 +`define MRF_32 32 +`define MRF_33 33 +`define MRF_34 34 +`define MRF_35 35 +`define MRF_36 36 +`define MRF_37 37 +`define MRF_38 38 +`define MRF_39 39 +`define MRF_40 40 +`define MRF_41 41 +`define MRF_42 42 +`define MRF_43 43 +`define MRF_44 44 +`define MRF_45 45 +`define MRF_46 46 +`define MRF_47 47 +`define MRF_48 48 +`define MRF_49 49 +`define MRF_50 50 +`define MRF_51 51 +`define MRF_52 52 +`define MRF_53 53 +`define MRF_54 54 +`define MRF_55 55 +`define MRF_56 56 +`define MRF_57 57 +`define MRF_58 58 +`define MRF_59 59 +`define MRF_60 60 +`define MRF_61 61 +`define MRF_62 62 +`define MRF_63 63 + +`define MFU_0 0 +`define MFU_1 1 + +`define INSTR_MEM_AWIDTH 10 + +`define NUM_MVM_CYCLES 11 + +`define OPCODE_WIDTH 4 +`define TARGET_OP_WIDTH 7 + +`define INSTR_WIDTH `OPCODE_WIDTH+`TARGET_OP_WIDTH+`DRAM_AWIDTH+`TARGET_OP_WIDTH+`VRF_AWIDTH + `VRF_AWIDTH +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM npu.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + + +module NPU( + input reset_npu, + input[`INSTR_WIDTH-1:0] instruction, + input[`DRAM_DWIDTH-1:0] input_data_DRAM, + output [`DRAM_DWIDTH-1:0] output_data_DRAM, + output [`DRAM_AWIDTH-1:0] dram_addr, + output dram_write_enable, + output get_instr, + output[`INSTR_MEM_AWIDTH-1:0] get_instr_addr, + //WRITE DOCUMENTATION EXPLAINING HOW MANY PORTS EACH VRF,MRF, ORF HAS and WHERE IS IT CONNECTED TO + input clk +); + wire[`ORF_DWIDTH-1:0] output_final_stage; + + + wire start_mv_mul_signal; + wire start_mfu_0_signal; + wire start_mfu_1_signal; + + + //SAME SIGNAL FOR ALL THE TILES AS PARALLEL EXECUTION OF TILES IS REQUIRED + reg[`NUM_LDPES-1:0] start_tile_with_single_cyc_latency; + reg[`NUM_LDPES-1:0] reset_tile_with_single_cyc_latency; + // + + wire [`MAX_VRF_DWIDTH-1:0] vrf_in_data; + wire[`VRF_AWIDTH-1:0] vrf_addr_wr; + wire[`VRF_AWIDTH-1:0] vrf_addr_read; + wire [`MRF_DWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_in_data; + + + //MRF SIGNALS + wire[`NUM_LDPES*`NUM_TILES-1:0] mrf_we; + wire [`MRF_AWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_addr_wr; + // + + //FINAL STAGE OUTPUT SIGNALS + wire[`ORF_DWIDTH-1:0] result_mvm; + //reg[`ORF_AWIDTH-1:0] result_addr_mvu_orf; + + //wire orf_addr_increment; + + // + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_0; + wire vrf_mvu_wr_enable_0; + wire vrf_mvu_readn_enable_0; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_1; + wire vrf_mvu_wr_enable_1; + wire vrf_mvu_readn_enable_1; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_2; + wire vrf_mvu_wr_enable_2; + wire vrf_mvu_readn_enable_2; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_3; + wire vrf_mvu_wr_enable_3; + wire vrf_mvu_readn_enable_3; + + wire done_mvm; //CHANGES THE REST STATE OF INSTR DECODER + wire out_data_available_mvm; + + wire[`NUM_TILES*`NUM_LDPES-1:0] mrf_we_for_dram; + wire [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram; + wire [`NUM_TILES*`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram; + + MVU mvm_unit ( + .clk(clk), + .start(start_tile_with_single_cyc_latency), + .reset(reset_tile_with_single_cyc_latency), + + .vrf_wr_addr(vrf_addr_wr), + .vrf_read_addr(vrf_addr_read), + .vec(vrf_in_data[`VRF_DWIDTH-1:0]), + .vrf_data_out_tile_0(vrf_mvu_out_0), //WITH TAG + .vrf_wr_enable_tile_0(vrf_mvu_wr_enable_0), //WITH TAG + .vrf_readn_enable_tile_0(vrf_mvu_readn_enable_0), //WITH TAG + .vrf_data_out_tile_1(vrf_mvu_out_1), //WITH TAG + .vrf_wr_enable_tile_1(vrf_mvu_wr_enable_1), //WITH TAG + .vrf_readn_enable_tile_1(vrf_mvu_readn_enable_1), //WITH TAG + .vrf_data_out_tile_2(vrf_mvu_out_2), //WITH TAG + .vrf_wr_enable_tile_2(vrf_mvu_wr_enable_2), //WITH TAG + .vrf_readn_enable_tile_2(vrf_mvu_readn_enable_2), //WITH TAG + .vrf_data_out_tile_3(vrf_mvu_out_3), //WITH TAG + .vrf_wr_enable_tile_3(vrf_mvu_wr_enable_3), //WITH TAG + .vrf_readn_enable_tile_3(vrf_mvu_readn_enable_3), //WITH TAG + + .mrf_in(mrf_in_data), + .mrf_we(mrf_we), //WITH TAG + .mrf_addr(mrf_addr_wr), + + .mrf_we_for_dram(mrf_we_for_dram), + .mrf_addr_for_dram(mrf_addr_for_dram), + .mrf_outa_to_dram(mrf_outa_to_dram), + + .out_data_available(out_data_available_mvm), + .mvm_result(result_mvm) //WITH TAG + ); + + assign done_mvm = out_data_available_mvm; + + reg[3:0] num_cycles_mvm; + + + //******************************************************************************* + + wire in_data_available_mfu_0; + reg reset_mfu_0_with_single_cyc_latency; + wire out_data_available_mfu_0; + wire done_mfu_0; + + wire in_data_available_mfu_1; + reg reset_mfu_1_with_single_cyc_latency; + wire out_data_available_mfu_1; + wire done_mfu_1; + + wire[1:0] activation; + wire[1:0] operation; + + //MFU VRF WIRES **************************************************************** + //wire[`VRF_AWIDTH-1:0] vrf_mfu_addr_read_add_0; + + //MFU - STAGE 0 VRF SIGNALS + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_add_0; + wire vrf_mfu_readn_enable_add_0; + wire vrf_mfu_wr_enable_add_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_add_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_add_0; + + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_mul_0; + wire vrf_mfu_readn_enable_mul_0; + wire vrf_mfu_wr_enable_mul_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_mul_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_mul_0; + + //wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_add_1; + + //MFU - STAGE 1 VRF SIGNALS + + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_add_1; + wire vrf_mfu_readn_enable_add_1; + wire vrf_mfu_wr_enable_add_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_add_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_add_1; + + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_mul_1; + wire vrf_mfu_readn_enable_mul_1; + wire vrf_mfu_wr_enable_mul_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_mul_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_mul_1; + + wire[`TARGET_OP_WIDTH-1:0] dstn_id; + wire[`NUM_LDPES*`OUT_DWIDTH-1:0] output_mvu_stage; + //************************************************************ + + assign output_mvu_stage = result_mvm; + + //************** INTER MFU MVU DATAPATH SIGNALS ************************************************* + reg[`ORF_DWIDTH-1:0] output_mvu_stage_buffer; + reg[`ORF_DWIDTH-1:0] output_mfu_stage_0_buffer; + + wire[`ORF_DWIDTH-1:0] primary_in_data_mfu_stage_0; + wire[`ORF_DWIDTH-1:0] primary_in_data_mfu_stage_1; + + + wire[`NUM_LDPES*`OUT_DWIDTH-1:0] output_mfu_stage_0; + wire[`NUM_LDPES*`OUT_DWIDTH-1:0] output_mfu_stage_1; + + always@(posedge clk) begin + if((dstn_id==`MFU_0_DSTN_ID) && done_mvm==1'b1) begin + output_mvu_stage_buffer <= output_mvu_stage; + end + end + + //CHECK THIS LOGIC CAREFULLY ***************************************************************** + always@(posedge clk) begin //FIRST BYPASS MUXING + //$display("%h", vrf_mvu_wr_addr_0); + if((dstn_id==`MFU_1_DSTN_ID) && (done_mfu_0 || done_mvm)) begin + output_mfu_stage_0_buffer <= (done_mfu_0) ? output_mfu_stage_0 : output_mvu_stage; + end + end + + assign output_final_stage = ((dstn_id!=`MFU_0_DSTN_ID) && (dstn_id!=`MFU_1_DSTN_ID)) ? + (done_mfu_1 ? output_mfu_stage_1 : //SECOND BYPASS MUXING + (done_mfu_0 ? output_mfu_stage_0 : + (done_mvm ? output_mvu_stage : 'd0))) : 'd0; + + //******************************************************************************************** + + + //****************************************************************************************** + wire[`ORF_DWIDTH-1:0] vrf_muxed_in_data_fake; + //************* MUXED MVU-MFU VRF ********************************************************** + + wire[`ORF_AWIDTH-1:0] vrf_muxed_wr_addr_dram; + wire[`ORF_DWIDTH-1:0] vrf_muxed_in_data; + wire vrf_muxed_wr_enable_dram; + wire vrf_muxed_readn_enable; + + wire[`ORF_AWIDTH-1:0] vrf_muxed_read_addr; + wire[`ORF_DWIDTH-1:0] vrf_muxed_out_data_dram; + wire[`ORF_DWIDTH-1:0] vrf_muxed_out_data; + + + VRF #(.VRF_DWIDTH(`ORF_DWIDTH),.VRF_AWIDTH(`ORF_AWIDTH)) vrf_muxed ( + .clk(clk), + + .addra(vrf_muxed_wr_addr_dram), + .ina(vrf_in_data[`ORF_DWIDTH-1:0]), + .wea(vrf_muxed_wr_enable_dram), + .outa(vrf_muxed_out_data_dram), + + .addrb(vrf_muxed_read_addr), + .inb(vrf_muxed_in_data_fake), + .web(vrf_muxed_readn_enable), + .outb(vrf_muxed_out_data) + ); + + wire mvu_or_vrf_mux_select; + assign primary_in_data_mfu_stage_0 = (mvu_or_vrf_mux_select) ? vrf_muxed_out_data : output_mvu_stage_buffer; + + assign primary_in_data_mfu_stage_1 = output_mfu_stage_0_buffer; + + //********************************************************************************************* + + //*********************************CONTROLLER FOR NPU***************************************** + controller controller_for_npu( + .clk(clk), + .reset_npu(reset_npu), + .instruction(instruction), + .get_instr(get_instr), + .get_instr_addr(get_instr_addr), + + .input_data_from_dram(input_data_DRAM), + .dram_addr_wr(dram_addr), + .dram_write_enable(dram_write_enable), + .output_data_to_dram(output_data_DRAM), + + .output_final_stage(output_final_stage), + + .start_mfu_0(start_mfu_0_signal), + .start_mfu_1(start_mfu_1_signal), + .start_mv_mul(start_mv_mul_signal), + .in_data_available_mfu_0(in_data_available_mfu_0), + .in_data_available_mfu_1(in_data_available_mfu_1), + + .activation(activation), + .operation(operation), + + .vrf_addr_read(vrf_addr_read), + .vrf_addr_wr(vrf_addr_wr), + + .vrf_out_data_mvu_0(vrf_mvu_out_0), //MVU TILE VRF + .vrf_readn_enable_mvu_0(vrf_mvu_readn_enable_0), + .vrf_wr_enable_mvu_0(vrf_mvu_wr_enable_0), + .vrf_out_data_mvu_1(vrf_mvu_out_1), //MVU TILE VRF + .vrf_readn_enable_mvu_1(vrf_mvu_readn_enable_1), + .vrf_wr_enable_mvu_1(vrf_mvu_wr_enable_1), + .vrf_out_data_mvu_2(vrf_mvu_out_2), //MVU TILE VRF + .vrf_readn_enable_mvu_2(vrf_mvu_readn_enable_2), + .vrf_wr_enable_mvu_2(vrf_mvu_wr_enable_2), + .vrf_out_data_mvu_3(vrf_mvu_out_3), //MVU TILE VRF + .vrf_readn_enable_mvu_3(vrf_mvu_readn_enable_3), + .vrf_wr_enable_mvu_3(vrf_mvu_wr_enable_3), + + .done_mvm(done_mvm), + .done_mfu_0(done_mfu_0), + .done_mfu_1(done_mfu_1), + //CHANGE INDEXING FOR VRFs-------------------------------------------- + + .vrf_out_data_mfu_add_0(vrf_mfu_out_data_add_0), + .vrf_readn_enable_mfu_add_0(vrf_mfu_readn_enable_add_0), + .vrf_wr_enable_mfu_add_0(vrf_mfu_wr_enable_add_0), //MFU VRF - ADD -0 + .vrf_addr_read_mfu_add_0(vrf_mfu_addr_read_add_0), + .vrf_addr_wr_mfu_add_0(vrf_mfu_addr_wr_add_0), + + + .vrf_out_data_mfu_mul_0(vrf_mfu_out_data_mul_0), //MFU VRF - MUL -0 + .vrf_readn_enable_mfu_mul_0(vrf_mfu_readn_enable_mul_0), + .vrf_wr_enable_mfu_mul_0(vrf_mfu_wr_enable_mul_0), + .vrf_addr_read_mfu_mul_0(vrf_mfu_addr_read_mul_0), + .vrf_addr_wr_mfu_mul_0(vrf_mfu_addr_wr_mul_0), + + .vrf_out_data_mfu_add_1(vrf_mfu_out_data_add_1), + .vrf_readn_enable_mfu_add_1(vrf_mfu_readn_enable_add_1), + .vrf_wr_enable_mfu_add_1(vrf_mfu_wr_enable_add_1), //MFU VRF - ADD - 1 + .vrf_addr_read_mfu_add_1(vrf_mfu_addr_read_add_1), + .vrf_addr_wr_mfu_add_1(vrf_mfu_addr_wr_add_1), + + + .vrf_out_data_mfu_mul_1(vrf_mfu_out_data_mul_1), //MFU VRF - MUL - 1 + .vrf_readn_enable_mfu_mul_1(vrf_mfu_readn_enable_mul_1), + .vrf_wr_enable_mfu_mul_1(vrf_mfu_wr_enable_mul_1), + .vrf_addr_read_mfu_mul_1(vrf_mfu_addr_read_mul_1), + .vrf_addr_wr_mfu_mul_1(vrf_mfu_addr_wr_mul_1), + + //MUXED VRF--------------------------------------- + .vrf_muxed_wr_addr_dram(vrf_muxed_wr_addr_dram), + .vrf_muxed_read_addr(vrf_muxed_read_addr), + .vrf_muxed_out_data_dram(vrf_muxed_out_data_dram), + .vrf_muxed_wr_enable_dram(vrf_muxed_wr_enable_dram), + .vrf_muxed_readn_enable(vrf_muxed_readn_enable), + //---------------------------------------------- + + .mvu_or_vrf_mux_select(mvu_or_vrf_mux_select), + .vrf_in_data(vrf_in_data), //common + + //----------------------------------------------------------------- + + .mrf_addr_wr(mrf_addr_wr), + .mrf_wr_enable(mrf_we), + .mrf_in_data(mrf_in_data), + + .mrf_we_for_dram(mrf_we_for_dram), + .mrf_addr_for_dram(mrf_addr_for_dram), + .mrf_outa_to_dram(mrf_outa_to_dram), + + //.orf_addr_increment(orf_addr_increment), + + .dstn_id(dstn_id) + ); + //*************************************************************************** + + //DELAYS START SIGNALS OF MVU TILE BY ONE CYCLE TO AVOID HIGH FANOUT AND ARITHEMETIC OF DONT CARES *********** + always@(posedge clk) begin + if(start_mv_mul_signal==1'b1) begin + start_tile_with_single_cyc_latency<={`NUM_LDPES{1'b1}}; + reset_tile_with_single_cyc_latency<={`NUM_LDPES{1'b0}}; + end + else begin + start_tile_with_single_cyc_latency<={`NUM_LDPES{1'b0}}; + reset_tile_with_single_cyc_latency<={`NUM_LDPES{1'b1}}; + end + end + + always@(*) begin + if(start_mfu_0_signal==1'b1) begin + reset_mfu_0_with_single_cyc_latency<=1'b0; + end + else begin + reset_mfu_0_with_single_cyc_latency<=1'b1; + end + end + + always@(*) begin + if(start_mfu_1_signal==1'b1) begin + reset_mfu_1_with_single_cyc_latency<=1'b0; + end + else begin + reset_mfu_1_with_single_cyc_latency<=1'b1; + end + end + + + //********************************************************************************************* + wire out_data_available_0; + //assign out_data_available_0 = done_mfu_0; + MFU mfu_stage_0( + .activation_type(activation), + .operation(operation), + .in_data_available(in_data_available_mfu_0), + + .vrf_addr_read_add(vrf_mfu_addr_read_add_0), + .vrf_addr_wr_add(vrf_mfu_addr_wr_add_0), + .vrf_readn_enable_add(vrf_mfu_readn_enable_add_0), + .vrf_wr_enable_add(vrf_mfu_wr_enable_add_0), + + .vrf_addr_read_mul(vrf_mfu_addr_read_mul_1), + .vrf_addr_wr_mul(vrf_mfu_addr_wr_mul_1), + .vrf_readn_enable_mul(vrf_mfu_readn_enable_mul_0), + .vrf_wr_enable_mul(vrf_mfu_wr_enable_mul_0), + + .primary_inp(primary_in_data_mfu_stage_0), + .secondary_inp(vrf_in_data[`ORF_DWIDTH-1:0]), + .out_data(output_mfu_stage_0), + .out_data_available(out_data_available_0), + .done(done_mfu_0), + .clk(clk), + + //VRF OUT SIGNALS + .out_vrf_add(vrf_mfu_out_data_add_0), + .out_vrf_mul(vrf_mfu_out_data_mul_0), + + .reset(reset_mfu_0_with_single_cyc_latency) + ); + + //************************************************************************* + //MFU STAGE - 2 + wire out_data_available_1; + //assign out_data_available_1 = done_mfu_1; + + MFU mfu_stage_1( + .activation_type(activation), + .operation(operation), + .in_data_available(in_data_available_mfu_1), + + //VRF IO SIGNALS FOR ELTWISE-ADD + .vrf_addr_read_add(vrf_mfu_addr_read_add_1), + .vrf_addr_wr_add(vrf_mfu_addr_wr_add_1), + .vrf_readn_enable_add(vrf_mfu_readn_enable_add_1), + .vrf_wr_enable_add(vrf_mfu_wr_enable_add_1), + + .vrf_addr_read_mul(vrf_mfu_addr_read_mul_1), + .vrf_addr_wr_mul(vrf_mfu_addr_wr_mul_1), + .vrf_readn_enable_mul(vrf_mfu_readn_enable_mul_1), + .vrf_wr_enable_mul(vrf_mfu_wr_enable_mul_1), + + //VRF IO SIGNALS FOR ELTWISE-MUL + .primary_inp(primary_in_data_mfu_stage_1), + .secondary_inp(vrf_in_data[`ORF_DWIDTH-1:0]), + .out_data(output_mfu_stage_1), + + .out_data_available(out_data_available_mfu_1), + .done(done_mfu_1), + .clk(clk), + + //VRF OUT SIGNAL + .out_vrf_add(vrf_mfu_out_data_add_1), + .out_vrf_mul(vrf_mfu_out_data_mul_1), + + .reset(reset_mfu_1_with_single_cyc_latency) + ); + + //************************************************************************* + + //************BYPASS MUXING LOGIC ***************************************** + + +endmodule +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM controller.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + + + +module controller( + + input clk, + input reset_npu, + input done_mvm, + input done_mfu_0, + input done_mfu_1, + + + input[`INSTR_WIDTH-1:0] instruction, + output reg get_instr, + output reg[`INSTR_MEM_AWIDTH-1:0] get_instr_addr, + + input[`DRAM_DWIDTH-1:0] input_data_from_dram, + input[`ORF_DWIDTH-1:0] output_final_stage, + output reg[`DRAM_AWIDTH-1:0] dram_addr_wr, + output reg dram_write_enable, + output reg [`DRAM_DWIDTH-1:0] output_data_to_dram, + + //output reg start_mvu, + output reg start_mv_mul, + output reg start_mfu_0, + output reg start_mfu_1, + //output reg reset_mvu, + output reg in_data_available_mfu_0, + output reg in_data_available_mfu_1, + + output reg[1:0] activation, + output reg[1:0] operation, + + //FOR MVU IO + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_0, + output reg vrf_readn_enable_mvu_0, + output reg vrf_wr_enable_mvu_0, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_1, + output reg vrf_readn_enable_mvu_1, + output reg vrf_wr_enable_mvu_1, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_2, + output reg vrf_readn_enable_mvu_2, + output reg vrf_wr_enable_mvu_2, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_3, + output reg vrf_readn_enable_mvu_3, + output reg vrf_wr_enable_mvu_3, + + + output reg[`VRF_AWIDTH-1:0] vrf_addr_read, + output reg[`VRF_AWIDTH-1:0] vrf_addr_wr, //********************* + + //FOR MFU STAGE -0 + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_add_0, + output reg vrf_readn_enable_mfu_add_0, + output reg vrf_wr_enable_mfu_add_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_add_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_add_0, + + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_mul_0, + output reg vrf_readn_enable_mfu_mul_0, + output reg vrf_wr_enable_mfu_mul_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_mul_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_mul_0, + // + + //FOR MFU STAGE -1 + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_add_1, + output reg vrf_readn_enable_mfu_add_1, + output reg vrf_wr_enable_mfu_add_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_add_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_add_1, + + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_mul_1, + output reg vrf_readn_enable_mfu_mul_1, + output reg vrf_wr_enable_mfu_mul_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_mul_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_mul_1, + + //VRF MUXED + input[`ORF_DWIDTH-1:0] vrf_muxed_out_data_dram, + output reg[`ORF_AWIDTH-1:0] vrf_muxed_wr_addr_dram, + output reg[`ORF_AWIDTH-1:0] vrf_muxed_read_addr, + output reg vrf_muxed_wr_enable_dram, + output reg vrf_muxed_readn_enable, + // + + output reg[`MAX_VRF_DWIDTH-1:0] vrf_in_data, + + output mvu_or_vrf_mux_select, + + //MRF IO PORTS + output reg[`MRF_AWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_addr_wr, + output reg[`NUM_LDPES*`NUM_TILES-1:0] mrf_wr_enable, //NOTE: LOG(NUM_LDPES) = TARGET_OP_WIDTH + output reg[`MRF_DWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_in_data, + + output reg[`NUM_TILES*`NUM_LDPES-1:0] mrf_we_for_dram, + output reg [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram, + input [`NUM_TILES*`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram, + // + + //BYPASS SIGNALS + output[`TARGET_OP_WIDTH-1:0] dstn_id +); + + wire[`OPCODE_WIDTH-1:0] opcode; + wire[`VRF_AWIDTH-1:0] op1_address; + wire[`VRF_AWIDTH-1:0] op2_address; + wire[`VRF_AWIDTH-1:0] dstn_address; + wire[`TARGET_OP_WIDTH-1:0] src1_id; + //wire[`TARGET_OP_WIDTH-1:0] dstn_id; + + reg[1:0] state; + + //NOTE - CORRECT NAMING FOR OPERANDS AND EXTRACTION SCHEME FOR YOUR PARTS OF INSTRUCTION + assign op1_address = instruction[3*`VRF_AWIDTH+(`TARGET_OP_WIDTH)-1:(2*`VRF_AWIDTH) +(`TARGET_OP_WIDTH)]; + assign op2_address = instruction[2*`VRF_AWIDTH+`TARGET_OP_WIDTH-1:`VRF_AWIDTH+`TARGET_OP_WIDTH]; + assign dstn_address = instruction[`VRF_AWIDTH-1:0]; + assign opcode = instruction[`INSTR_WIDTH-1:`INSTR_WIDTH-`OPCODE_WIDTH]; + assign src1_id = instruction[3*`VRF_AWIDTH+2*`TARGET_OP_WIDTH-1:3*`VRF_AWIDTH+`TARGET_OP_WIDTH]; //or can be called mem_id + assign dstn_id = instruction[`VRF_AWIDTH+`TARGET_OP_WIDTH-1:`VRF_AWIDTH];//LSB for dram_write bypass + + assign mvu_or_vrf_mux_select = (op2_address!={`VRF_AWIDTH{1'b0}}); //UNUSED BIT FOR MFU OPERATIONS + + + //TODO - MAKE THIS SEQUENTIAL LOGIC - DONE + always@(posedge clk) begin + + if(reset_npu == 1'b1) begin + //reset_mvu<=1'b1; + //start_mvu<=1'b0; + get_instr<=1'b0; + + get_instr_addr<=0; + + start_mv_mul <= 1'b0; + + in_data_available_mfu_0 <= 1'b0; + start_mfu_0 <= 1'b0; + + in_data_available_mfu_1 <= 1'b0; + start_mfu_1 <= 1'b0; + dram_write_enable <= 1'b0; + mrf_wr_enable<='b0; + + + vrf_wr_enable_mvu_0<=1'b0; + vrf_readn_enable_mvu_0 <= 1'b0; + + + vrf_wr_enable_mvu_1<=1'b0; + vrf_readn_enable_mvu_1 <= 1'b0; + + + vrf_wr_enable_mvu_2<=1'b0; + vrf_readn_enable_mvu_2 <= 1'b0; + + + vrf_wr_enable_mvu_3<=1'b0; + vrf_readn_enable_mvu_3 <= 1'b0; + + + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + + dram_addr_wr<=10'd0; + vrf_addr_wr <= 10'd0; + //vrf_addr_wr_mvu_1 <= 0; + vrf_addr_wr_mfu_add_0 <= 10'd0; + vrf_addr_wr_mfu_mul_0 <= 10'd0; + vrf_addr_wr_mfu_add_1 <= 10'd0; + vrf_addr_wr_mfu_mul_1 <= 10'd0; + + vrf_addr_read <= 10'd0; + //vrf_addr_read_mvu_1 <= 0; + vrf_addr_read_mfu_add_0 <= 10'd0; + vrf_addr_read_mfu_mul_0 <= 10'd0; + vrf_addr_read_mfu_add_1 <= 10'd0; + vrf_addr_read_mfu_mul_1 <= 10'd0; + + + //vrf_muxed_wr_addr_dram <= 0; + //vrf_muxed_read_addr <= 0; + vrf_muxed_wr_enable_dram <= 1'b0; + vrf_muxed_readn_enable <= 1'b0; + + // orf_addr_increment<=1'b0; + + mrf_addr_wr <= 1'b0; + + state <= 0; + end + else begin + if(state==0) begin //FETCH + get_instr <= 1'b0; + state <= 1; + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable <= 1'b0; + mrf_wr_enable <= 0; + end + else if(state==1) begin //DECODE + case(opcode) + `V_WR: begin + state <= 2; + get_instr<=0; + //get_instr_addr<=get_instr_addr+1'b1; + case(src1_id) + `VRF_0: begin vrf_wr_enable_mvu_0 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_1: begin vrf_wr_enable_mvu_1 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_2: begin vrf_wr_enable_mvu_2 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_3: begin vrf_wr_enable_mvu_3 <= 1'b0; + vrf_addr_wr <= op1_address; + end + + `VRF_4: begin vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_addr_wr_mfu_add_0 <= op1_address; + end + + `VRF_5: begin vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_addr_wr_mfu_mul_0 <= op1_address; + end + + `VRF_6: begin vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_addr_wr_mfu_add_1 <= op1_address; + end + + `VRF_7: begin + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_addr_wr_mfu_mul_1 <= op1_address; + end + + `VRF_MUXED: begin + vrf_muxed_wr_enable_dram <= 1'b0; + vrf_muxed_wr_addr_dram <= op1_address; + end + + default: begin + vrf_wr_enable_mvu_0 <= 1'bX; + output_data_to_dram <= 'd0; + end + + endcase + + dram_addr_wr <= dstn_address; + dram_write_enable <= 1'b1; + end + `M_WR: begin + state <= 2; + get_instr<=0; + + case(src1_id) + `MRF_0: begin mrf_we_for_dram[0] <= 1'b0; + mrf_addr_for_dram[1*`MRF_AWIDTH-1:0*`MRF_AWIDTH] <= op1_address; + end + `MRF_1: begin mrf_we_for_dram[1] <= 1'b0; + mrf_addr_for_dram[2*`MRF_AWIDTH-1:1*`MRF_AWIDTH] <= op1_address; + end + `MRF_2: begin mrf_we_for_dram[2] <= 1'b0; + mrf_addr_for_dram[3*`MRF_AWIDTH-1:2*`MRF_AWIDTH] <= op1_address; + end + `MRF_3: begin mrf_we_for_dram[3] <= 1'b0; + mrf_addr_for_dram[4*`MRF_AWIDTH-1:3*`MRF_AWIDTH] <= op1_address; + end + `MRF_4: begin mrf_we_for_dram[4] <= 1'b0; + mrf_addr_for_dram[5*`MRF_AWIDTH-1:4*`MRF_AWIDTH] <= op1_address; + end + `MRF_5: begin mrf_we_for_dram[5] <= 1'b0; + mrf_addr_for_dram[6*`MRF_AWIDTH-1:5*`MRF_AWIDTH] <= op1_address; + end + `MRF_6: begin mrf_we_for_dram[6] <= 1'b0; + mrf_addr_for_dram[7*`MRF_AWIDTH-1:6*`MRF_AWIDTH] <= op1_address; + end + `MRF_7: begin mrf_we_for_dram[7] <= 1'b0; + mrf_addr_for_dram[8*`MRF_AWIDTH-1:7*`MRF_AWIDTH] <= op1_address; + end + `MRF_8: begin mrf_we_for_dram[8] <= 1'b0; + mrf_addr_for_dram[9*`MRF_AWIDTH-1:8*`MRF_AWIDTH] <= op1_address; + end + `MRF_9: begin mrf_we_for_dram[9] <= 1'b0; + mrf_addr_for_dram[10*`MRF_AWIDTH-1:9*`MRF_AWIDTH] <= op1_address; + end + `MRF_10: begin mrf_we_for_dram[10] <= 1'b0; + mrf_addr_for_dram[11*`MRF_AWIDTH-1:10*`MRF_AWIDTH] <= op1_address; + end + `MRF_11: begin mrf_we_for_dram[11] <= 1'b0; + mrf_addr_for_dram[12*`MRF_AWIDTH-1:11*`MRF_AWIDTH] <= op1_address; + end + `MRF_12: begin mrf_we_for_dram[12] <= 1'b0; + mrf_addr_for_dram[13*`MRF_AWIDTH-1:12*`MRF_AWIDTH] <= op1_address; + end + `MRF_13: begin mrf_we_for_dram[13] <= 1'b0; + mrf_addr_for_dram[14*`MRF_AWIDTH-1:13*`MRF_AWIDTH] <= op1_address; + end + `MRF_14: begin mrf_we_for_dram[14] <= 1'b0; + mrf_addr_for_dram[15*`MRF_AWIDTH-1:14*`MRF_AWIDTH] <= op1_address; + end + `MRF_15: begin mrf_we_for_dram[15] <= 1'b0; + mrf_addr_for_dram[16*`MRF_AWIDTH-1:15*`MRF_AWIDTH] <= op1_address; + end + `MRF_16: begin mrf_we_for_dram[16] <= 1'b0; + mrf_addr_for_dram[17*`MRF_AWIDTH-1:16*`MRF_AWIDTH] <= op1_address; + end + `MRF_17: begin mrf_we_for_dram[17] <= 1'b0; + mrf_addr_for_dram[18*`MRF_AWIDTH-1:17*`MRF_AWIDTH] <= op1_address; + end + `MRF_18: begin mrf_we_for_dram[18] <= 1'b0; + mrf_addr_for_dram[19*`MRF_AWIDTH-1:18*`MRF_AWIDTH] <= op1_address; + end + `MRF_19: begin mrf_we_for_dram[19] <= 1'b0; + mrf_addr_for_dram[20*`MRF_AWIDTH-1:19*`MRF_AWIDTH] <= op1_address; + end + `MRF_20: begin mrf_we_for_dram[20] <= 1'b0; + mrf_addr_for_dram[21*`MRF_AWIDTH-1:20*`MRF_AWIDTH] <= op1_address; + end + `MRF_21: begin mrf_we_for_dram[21] <= 1'b0; + mrf_addr_for_dram[22*`MRF_AWIDTH-1:21*`MRF_AWIDTH] <= op1_address; + end + `MRF_22: begin mrf_we_for_dram[22] <= 1'b0; + mrf_addr_for_dram[23*`MRF_AWIDTH-1:22*`MRF_AWIDTH] <= op1_address; + end + `MRF_23: begin mrf_we_for_dram[23] <= 1'b0; + mrf_addr_for_dram[24*`MRF_AWIDTH-1:23*`MRF_AWIDTH] <= op1_address; + end + `MRF_24: begin mrf_we_for_dram[24] <= 1'b0; + mrf_addr_for_dram[25*`MRF_AWIDTH-1:24*`MRF_AWIDTH] <= op1_address; + end + `MRF_25: begin mrf_we_for_dram[25] <= 1'b0; + mrf_addr_for_dram[26*`MRF_AWIDTH-1:25*`MRF_AWIDTH] <= op1_address; + end + `MRF_26: begin mrf_we_for_dram[26] <= 1'b0; + mrf_addr_for_dram[27*`MRF_AWIDTH-1:26*`MRF_AWIDTH] <= op1_address; + end + `MRF_27: begin mrf_we_for_dram[27] <= 1'b0; + mrf_addr_for_dram[28*`MRF_AWIDTH-1:27*`MRF_AWIDTH] <= op1_address; + end + `MRF_28: begin mrf_we_for_dram[28] <= 1'b0; + mrf_addr_for_dram[29*`MRF_AWIDTH-1:28*`MRF_AWIDTH] <= op1_address; + end + `MRF_29: begin mrf_we_for_dram[29] <= 1'b0; + mrf_addr_for_dram[30*`MRF_AWIDTH-1:29*`MRF_AWIDTH] <= op1_address; + end + `MRF_30: begin mrf_we_for_dram[30] <= 1'b0; + mrf_addr_for_dram[31*`MRF_AWIDTH-1:30*`MRF_AWIDTH] <= op1_address; + end + `MRF_31: begin mrf_we_for_dram[31] <= 1'b0; + mrf_addr_for_dram[32*`MRF_AWIDTH-1:31*`MRF_AWIDTH] <= op1_address; + end + `MRF_32: begin mrf_we_for_dram[32] <= 1'b0; + mrf_addr_for_dram[33*`MRF_AWIDTH-1:32*`MRF_AWIDTH] <= op1_address; + end + `MRF_33: begin mrf_we_for_dram[33] <= 1'b0; + mrf_addr_for_dram[34*`MRF_AWIDTH-1:33*`MRF_AWIDTH] <= op1_address; + end + `MRF_34: begin mrf_we_for_dram[34] <= 1'b0; + mrf_addr_for_dram[35*`MRF_AWIDTH-1:34*`MRF_AWIDTH] <= op1_address; + end + `MRF_35: begin mrf_we_for_dram[35] <= 1'b0; + mrf_addr_for_dram[36*`MRF_AWIDTH-1:35*`MRF_AWIDTH] <= op1_address; + end + `MRF_36: begin mrf_we_for_dram[36] <= 1'b0; + mrf_addr_for_dram[37*`MRF_AWIDTH-1:36*`MRF_AWIDTH] <= op1_address; + end + `MRF_37: begin mrf_we_for_dram[37] <= 1'b0; + mrf_addr_for_dram[38*`MRF_AWIDTH-1:37*`MRF_AWIDTH] <= op1_address; + end + `MRF_38: begin mrf_we_for_dram[38] <= 1'b0; + mrf_addr_for_dram[39*`MRF_AWIDTH-1:38*`MRF_AWIDTH] <= op1_address; + end + `MRF_39: begin mrf_we_for_dram[39] <= 1'b0; + mrf_addr_for_dram[40*`MRF_AWIDTH-1:39*`MRF_AWIDTH] <= op1_address; + end + `MRF_40: begin mrf_we_for_dram[40] <= 1'b0; + mrf_addr_for_dram[41*`MRF_AWIDTH-1:40*`MRF_AWIDTH] <= op1_address; + end + `MRF_41: begin mrf_we_for_dram[41] <= 1'b0; + mrf_addr_for_dram[42*`MRF_AWIDTH-1:41*`MRF_AWIDTH] <= op1_address; + end + `MRF_42: begin mrf_we_for_dram[42] <= 1'b0; + mrf_addr_for_dram[43*`MRF_AWIDTH-1:42*`MRF_AWIDTH] <= op1_address; + end + `MRF_43: begin mrf_we_for_dram[43] <= 1'b0; + mrf_addr_for_dram[44*`MRF_AWIDTH-1:43*`MRF_AWIDTH] <= op1_address; + end + `MRF_44: begin mrf_we_for_dram[44] <= 1'b0; + mrf_addr_for_dram[45*`MRF_AWIDTH-1:44*`MRF_AWIDTH] <= op1_address; + end + `MRF_45: begin mrf_we_for_dram[45] <= 1'b0; + mrf_addr_for_dram[46*`MRF_AWIDTH-1:45*`MRF_AWIDTH] <= op1_address; + end + `MRF_46: begin mrf_we_for_dram[46] <= 1'b0; + mrf_addr_for_dram[47*`MRF_AWIDTH-1:46*`MRF_AWIDTH] <= op1_address; + end + `MRF_47: begin mrf_we_for_dram[47] <= 1'b0; + mrf_addr_for_dram[48*`MRF_AWIDTH-1:47*`MRF_AWIDTH] <= op1_address; + end + `MRF_48: begin mrf_we_for_dram[48] <= 1'b0; + mrf_addr_for_dram[49*`MRF_AWIDTH-1:48*`MRF_AWIDTH] <= op1_address; + end + `MRF_49: begin mrf_we_for_dram[49] <= 1'b0; + mrf_addr_for_dram[50*`MRF_AWIDTH-1:49*`MRF_AWIDTH] <= op1_address; + end + `MRF_50: begin mrf_we_for_dram[50] <= 1'b0; + mrf_addr_for_dram[51*`MRF_AWIDTH-1:50*`MRF_AWIDTH] <= op1_address; + end + `MRF_51: begin mrf_we_for_dram[51] <= 1'b0; + mrf_addr_for_dram[52*`MRF_AWIDTH-1:51*`MRF_AWIDTH] <= op1_address; + end + `MRF_52: begin mrf_we_for_dram[52] <= 1'b0; + mrf_addr_for_dram[53*`MRF_AWIDTH-1:52*`MRF_AWIDTH] <= op1_address; + end + `MRF_53: begin mrf_we_for_dram[53] <= 1'b0; + mrf_addr_for_dram[54*`MRF_AWIDTH-1:53*`MRF_AWIDTH] <= op1_address; + end + `MRF_54: begin mrf_we_for_dram[54] <= 1'b0; + mrf_addr_for_dram[55*`MRF_AWIDTH-1:54*`MRF_AWIDTH] <= op1_address; + end + `MRF_55: begin mrf_we_for_dram[55] <= 1'b0; + mrf_addr_for_dram[56*`MRF_AWIDTH-1:55*`MRF_AWIDTH] <= op1_address; + end + `MRF_56: begin mrf_we_for_dram[56] <= 1'b0; + mrf_addr_for_dram[57*`MRF_AWIDTH-1:56*`MRF_AWIDTH] <= op1_address; + end + `MRF_57: begin mrf_we_for_dram[57] <= 1'b0; + mrf_addr_for_dram[58*`MRF_AWIDTH-1:57*`MRF_AWIDTH] <= op1_address; + end + `MRF_58: begin mrf_we_for_dram[58] <= 1'b0; + mrf_addr_for_dram[59*`MRF_AWIDTH-1:58*`MRF_AWIDTH] <= op1_address; + end + `MRF_59: begin mrf_we_for_dram[59] <= 1'b0; + mrf_addr_for_dram[60*`MRF_AWIDTH-1:59*`MRF_AWIDTH] <= op1_address; + end + `MRF_60: begin mrf_we_for_dram[60] <= 1'b0; + mrf_addr_for_dram[61*`MRF_AWIDTH-1:60*`MRF_AWIDTH] <= op1_address; + end + `MRF_61: begin mrf_we_for_dram[61] <= 1'b0; + mrf_addr_for_dram[62*`MRF_AWIDTH-1:61*`MRF_AWIDTH] <= op1_address; + end + `MRF_62: begin mrf_we_for_dram[62] <= 1'b0; + mrf_addr_for_dram[63*`MRF_AWIDTH-1:62*`MRF_AWIDTH] <= op1_address; + end + `MRF_63: begin mrf_we_for_dram[63] <= 1'b0; + mrf_addr_for_dram[64*`MRF_AWIDTH-1:63*`MRF_AWIDTH] <= op1_address; + end + default: begin mrf_we_for_dram <= 'd0; + mrf_addr_for_dram <= 'd0; + end + endcase + + dram_addr_wr <= dstn_address; + dram_write_enable <= 1'b1; + end + `V_RD: begin + state <= 2; + get_instr<=0; + dram_addr_wr <= op1_address; + dram_write_enable <= 1'b0; + + end + //CHANGE NAMING CONVENTION FOR WRITE AND READ TO STORE AND LOAD + //ADD COMMENTS FOR SRC AND DESTINATION + `M_RD: begin + state <= 2; + get_instr<=0; + dram_addr_wr <= op1_address; + dram_write_enable <= 1'b0; + end + `MV_MUL: begin + //op1_id is don't care for this instructions + + state <= 2; + get_instr<=1'b0; + start_mv_mul <= 1'b1; + mrf_addr_wr[(1*`MRF_AWIDTH)-1:0*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(2*`MRF_AWIDTH)-1:1*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(3*`MRF_AWIDTH)-1:2*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(4*`MRF_AWIDTH)-1:3*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(5*`MRF_AWIDTH)-1:4*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(6*`MRF_AWIDTH)-1:5*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(7*`MRF_AWIDTH)-1:6*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(8*`MRF_AWIDTH)-1:7*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(9*`MRF_AWIDTH)-1:8*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(10*`MRF_AWIDTH)-1:9*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(11*`MRF_AWIDTH)-1:10*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(12*`MRF_AWIDTH)-1:11*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(13*`MRF_AWIDTH)-1:12*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(14*`MRF_AWIDTH)-1:13*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(15*`MRF_AWIDTH)-1:14*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(16*`MRF_AWIDTH)-1:15*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(17*`MRF_AWIDTH)-1:16*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(18*`MRF_AWIDTH)-1:17*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(19*`MRF_AWIDTH)-1:18*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(20*`MRF_AWIDTH)-1:19*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(21*`MRF_AWIDTH)-1:20*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(22*`MRF_AWIDTH)-1:21*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(23*`MRF_AWIDTH)-1:22*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(24*`MRF_AWIDTH)-1:23*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(25*`MRF_AWIDTH)-1:24*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(26*`MRF_AWIDTH)-1:25*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(27*`MRF_AWIDTH)-1:26*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(28*`MRF_AWIDTH)-1:27*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(29*`MRF_AWIDTH)-1:28*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(30*`MRF_AWIDTH)-1:29*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(31*`MRF_AWIDTH)-1:30*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(32*`MRF_AWIDTH)-1:31*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(33*`MRF_AWIDTH)-1:32*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(34*`MRF_AWIDTH)-1:33*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(35*`MRF_AWIDTH)-1:34*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(36*`MRF_AWIDTH)-1:35*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(37*`MRF_AWIDTH)-1:36*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(38*`MRF_AWIDTH)-1:37*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(39*`MRF_AWIDTH)-1:38*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(40*`MRF_AWIDTH)-1:39*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(41*`MRF_AWIDTH)-1:40*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(42*`MRF_AWIDTH)-1:41*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(43*`MRF_AWIDTH)-1:42*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(44*`MRF_AWIDTH)-1:43*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(45*`MRF_AWIDTH)-1:44*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(46*`MRF_AWIDTH)-1:45*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(47*`MRF_AWIDTH)-1:46*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(48*`MRF_AWIDTH)-1:47*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(49*`MRF_AWIDTH)-1:48*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(50*`MRF_AWIDTH)-1:49*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(51*`MRF_AWIDTH)-1:50*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(52*`MRF_AWIDTH)-1:51*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(53*`MRF_AWIDTH)-1:52*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(54*`MRF_AWIDTH)-1:53*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(55*`MRF_AWIDTH)-1:54*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(56*`MRF_AWIDTH)-1:55*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(57*`MRF_AWIDTH)-1:56*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(58*`MRF_AWIDTH)-1:57*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(59*`MRF_AWIDTH)-1:58*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(60*`MRF_AWIDTH)-1:59*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(61*`MRF_AWIDTH)-1:60*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(62*`MRF_AWIDTH)-1:61*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(63*`MRF_AWIDTH)-1:62*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(64*`MRF_AWIDTH)-1:63*`MRF_AWIDTH] <= op1_address; + vrf_addr_read <= op2_address; + vrf_readn_enable_mvu_0 <= 1'b0; + vrf_readn_enable_mvu_1 <= 1'b0; + vrf_readn_enable_mvu_2 <= 1'b0; + vrf_readn_enable_mvu_3 <= 1'b0; + mrf_wr_enable <= 0; + end + `VV_ADD:begin + + //MFU_STAGE-0 DESIGNATED FOR ELTWISE ADD + state <= 2; + get_instr <= 1'b0; + operation <= `ELT_WISE_ADD; //NOTE - 2nd VRF INDEX IS FOR ADD UNITS ELT WISE + activation <= 0; + + case(src1_id) + + `VRF_4: begin + start_mfu_0 <= 1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + + in_data_available_mfu_0 <= 1'b1; + vrf_addr_read_mfu_add_0 <= op1_address; + vrf_readn_enable_mfu_add_0 <= 1'b0; + end + + + `VRF_6: begin + start_mfu_1 <= 1'b1; + in_data_available_mfu_1 <= 1'b1; + vrf_addr_read_mfu_add_1 <= op1_address; + vrf_readn_enable_mfu_add_1 <= 1'b0; + end + + + default: begin + start_mfu_0 <= 1'bX; + in_data_available_mfu_0 <= 1'b0; + vrf_addr_read_mfu_add_0 <= 10'd0; + vrf_readn_enable_mfu_add_0 <= 1'b0; + vrf_addr_read_mfu_add_1 <= 10'd0; + vrf_readn_enable_mfu_add_1 <= 1'b0; + end + + endcase + + end + `VV_SUB:begin + + //MFU_STAGE-0 DESIGNATED FOR ELTWISE ADD + state <= 2; + get_instr<=1'b0; + operation<=`ELT_WISE_ADD; //NOTE - 2nd VRF INDEX IS FOR ADD UNITS ELT WISE + + activation <= 1; + + case(src1_id) + + `VRF_4: begin + start_mfu_0 <= 1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + + in_data_available_mfu_0 <= 1'b1; + vrf_addr_read_mfu_add_0 <= op1_address; + vrf_readn_enable_mfu_add_0 <= 1'b0; + end + + + `VRF_6: begin + start_mfu_1 <= 1'b1; + in_data_available_mfu_1 <= 1'b1; + vrf_addr_read_mfu_add_1 <= op1_address; + vrf_readn_enable_mfu_add_1 <= 1'b0; + end + + + default: begin + start_mfu_0 <= 1'bX; + in_data_available_mfu_0 <= 1'b0; + vrf_addr_read_mfu_add_0 <= 10'd0; + vrf_readn_enable_mfu_add_0 <= 1'b0; + vrf_addr_read_mfu_add_1 <= 10'd0; + vrf_readn_enable_mfu_add_1 <= 1'b0; + end + + endcase + + end + `VV_MUL:begin + state <= 2; + get_instr<=1'b0; + + operation<=`ELT_WISE_MULTIPLY; //NOTE - 3RD VRF INDEX IS FOR ADD UNITS ELT WISE + case(src1_id) + + `VRF_5: begin + start_mfu_0 <= 1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + + in_data_available_mfu_0 <= 1'b1; + vrf_addr_read_mfu_mul_0 <= op1_address; + vrf_readn_enable_mfu_mul_0 <= 1'b0; + end + + `VRF_7: begin + start_mfu_1 <= 1'b1; + in_data_available_mfu_1 <= 1'b1; + vrf_addr_read_mfu_mul_1 <= op1_address; + vrf_readn_enable_mfu_mul_1 <= 1'b0; + end + + default: begin + start_mfu_0 <= 1'bX; + in_data_available_mfu_0 <= 1'b0; + vrf_addr_read_mfu_mul_0 <= 10'd0; + vrf_readn_enable_mfu_mul_0 <= 1'b0; + vrf_addr_read_mfu_mul_1 <= 10'b0; + vrf_readn_enable_mfu_mul_1 <= 1'b0; + end + + endcase + + end + `V_RELU:begin + + get_instr<=1'b0; + case(src1_id) + + `MFU_0: begin + start_mfu_0<=1'b1; + in_data_available_mfu_0<=1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + end + + `MFU_1: begin + start_mfu_1<=1'b1; + in_data_available_mfu_1<=1'b1; + end + + default: begin + start_mfu_0<=1'bX; + in_data_available_mfu_0<=1'bX; + end + + endcase + operation<=`ACTIVATION; + activation<=`RELU; + state <= 2; + + end + `V_SIGM:begin + + get_instr<=1'b0; + case(src1_id) + + `MFU_0: begin + start_mfu_0<=1'b1; + in_data_available_mfu_0<=1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + end + + `MFU_1: begin + start_mfu_1<=1'b1; + in_data_available_mfu_1<=1'b1; + end + + default: begin + start_mfu_0<=1'bX; + in_data_available_mfu_0<=1'bX; + end + + endcase + operation<=`ACTIVATION; + activation<=`SIGM; + state <= 2; + end + `V_TANH:begin + //dram_write_enable <= bypass_id[0]; + get_instr<=1'b0; + case(src1_id) + + `MFU_0: begin + start_mfu_0<=1'b1; + in_data_available_mfu_0<=1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + end + + `MFU_1: begin + start_mfu_1<=1'b1; + in_data_available_mfu_1<=1'b1; + end + + default: begin + start_mfu_0<=1'bX; + in_data_available_mfu_0<=1'bX; + end + + endcase + operation<=`ACTIVATION; + activation<=`TANH; + state <= 2; + + end + `END_CHAIN :begin + + start_mv_mul<=1'b0; + get_instr<=1'b0; + + in_data_available_mfu_0<=1'b0; + start_mfu_0<=1'b0; + + in_data_available_mfu_1<=1'b0; + start_mfu_1<=1'b0; + + mrf_wr_enable<=0; + + + vrf_wr_enable_mvu_0<='b0; + vrf_readn_enable_mvu_0 <= 'b0; + + + vrf_wr_enable_mvu_1<='b0; + vrf_readn_enable_mvu_1 <= 'b0; + + + vrf_wr_enable_mvu_2<='b0; + vrf_readn_enable_mvu_2 <= 'b0; + + + vrf_wr_enable_mvu_3<='b0; + vrf_readn_enable_mvu_3 <= 'b0; + + + vrf_wr_enable_mfu_add_0 <= 0; + vrf_wr_enable_mfu_mul_0 <= 0; + vrf_wr_enable_mfu_add_1 <= 0; + vrf_wr_enable_mfu_mul_1 <= 0; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_wr_addr_dram <= 1'b0; + + vrf_readn_enable_mfu_add_0 <= 0; + vrf_readn_enable_mfu_mul_0 <= 0; + vrf_readn_enable_mfu_add_1 <= 0; + vrf_readn_enable_mfu_mul_1 <= 0; + + //orf_addr_increment<=1'b0; + mrf_addr_wr <= 0; + dram_write_enable <= 1'b0; + state <= 1; + end + endcase + end + else begin //EXECUTE + + case(opcode) + `V_WR: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(src1_id) + + `VRF_0: begin + output_data_to_dram <= vrf_out_data_mvu_0; + end + `VRF_1: begin + output_data_to_dram <= vrf_out_data_mvu_1; + end + `VRF_2: begin + output_data_to_dram <= vrf_out_data_mvu_2; + end + `VRF_3: begin + output_data_to_dram <= vrf_out_data_mvu_3; + end + + `VRF_4: begin + output_data_to_dram <= vrf_out_data_mfu_add_0; + end + + `VRF_5: begin + output_data_to_dram <= vrf_out_data_mfu_mul_0; + end + + `VRF_6: begin + output_data_to_dram <= vrf_out_data_mfu_add_1; + end + + `VRF_7: begin + output_data_to_dram <= vrf_out_data_mfu_mul_1; + end + + `VRF_MUXED: begin + output_data_to_dram <= vrf_muxed_out_data_dram; + end + default: begin + output_data_to_dram <= 'd0; + end + endcase + + end + `M_WR: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(src1_id) + + `MRF_0: begin + output_data_to_dram <= mrf_outa_to_dram[1*`MRF_DWIDTH-1:0*`MRF_DWIDTH]; + end + `MRF_1: begin + output_data_to_dram <= mrf_outa_to_dram[2*`MRF_DWIDTH-1:1*`MRF_DWIDTH]; + end + `MRF_2: begin + output_data_to_dram <= mrf_outa_to_dram[3*`MRF_DWIDTH-1:2*`MRF_DWIDTH]; + end + `MRF_3: begin + output_data_to_dram <= mrf_outa_to_dram[4*`MRF_DWIDTH-1:3*`MRF_DWIDTH]; + end + `MRF_4: begin + output_data_to_dram <= mrf_outa_to_dram[5*`MRF_DWIDTH-1:4*`MRF_DWIDTH]; + end + `MRF_5: begin + output_data_to_dram <= mrf_outa_to_dram[6*`MRF_DWIDTH-1:5*`MRF_DWIDTH]; + end + `MRF_6: begin + output_data_to_dram <= mrf_outa_to_dram[7*`MRF_DWIDTH-1:6*`MRF_DWIDTH]; + end + `MRF_7: begin + output_data_to_dram <= mrf_outa_to_dram[8*`MRF_DWIDTH-1:7*`MRF_DWIDTH]; + end + `MRF_8: begin + output_data_to_dram <= mrf_outa_to_dram[9*`MRF_DWIDTH-1:8*`MRF_DWIDTH]; + end + `MRF_9: begin + output_data_to_dram <= mrf_outa_to_dram[10*`MRF_DWIDTH-1:9*`MRF_DWIDTH]; + end + `MRF_10: begin + output_data_to_dram <= mrf_outa_to_dram[11*`MRF_DWIDTH-1:10*`MRF_DWIDTH]; + end + `MRF_11: begin + output_data_to_dram <= mrf_outa_to_dram[12*`MRF_DWIDTH-1:11*`MRF_DWIDTH]; + end + `MRF_12: begin + output_data_to_dram <= mrf_outa_to_dram[13*`MRF_DWIDTH-1:12*`MRF_DWIDTH]; + end + `MRF_13: begin + output_data_to_dram <= mrf_outa_to_dram[14*`MRF_DWIDTH-1:13*`MRF_DWIDTH]; + end + `MRF_14: begin + output_data_to_dram <= mrf_outa_to_dram[15*`MRF_DWIDTH-1:14*`MRF_DWIDTH]; + end + `MRF_15: begin + output_data_to_dram <= mrf_outa_to_dram[16*`MRF_DWIDTH-1:15*`MRF_DWIDTH]; + end + `MRF_16: begin + output_data_to_dram <= mrf_outa_to_dram[17*`MRF_DWIDTH-1:16*`MRF_DWIDTH]; + end + `MRF_17: begin + output_data_to_dram <= mrf_outa_to_dram[18*`MRF_DWIDTH-1:17*`MRF_DWIDTH]; + end + `MRF_18: begin + output_data_to_dram <= mrf_outa_to_dram[19*`MRF_DWIDTH-1:18*`MRF_DWIDTH]; + end + `MRF_19: begin + output_data_to_dram <= mrf_outa_to_dram[20*`MRF_DWIDTH-1:19*`MRF_DWIDTH]; + end + `MRF_20: begin + output_data_to_dram <= mrf_outa_to_dram[21*`MRF_DWIDTH-1:20*`MRF_DWIDTH]; + end + `MRF_21: begin + output_data_to_dram <= mrf_outa_to_dram[22*`MRF_DWIDTH-1:21*`MRF_DWIDTH]; + end + `MRF_22: begin + output_data_to_dram <= mrf_outa_to_dram[23*`MRF_DWIDTH-1:22*`MRF_DWIDTH]; + end + `MRF_23: begin + output_data_to_dram <= mrf_outa_to_dram[24*`MRF_DWIDTH-1:23*`MRF_DWIDTH]; + end + `MRF_24: begin + output_data_to_dram <= mrf_outa_to_dram[25*`MRF_DWIDTH-1:24*`MRF_DWIDTH]; + end + `MRF_25: begin + output_data_to_dram <= mrf_outa_to_dram[26*`MRF_DWIDTH-1:25*`MRF_DWIDTH]; + end + `MRF_26: begin + output_data_to_dram <= mrf_outa_to_dram[27*`MRF_DWIDTH-1:26*`MRF_DWIDTH]; + end + `MRF_27: begin + output_data_to_dram <= mrf_outa_to_dram[28*`MRF_DWIDTH-1:27*`MRF_DWIDTH]; + end + `MRF_28: begin + output_data_to_dram <= mrf_outa_to_dram[29*`MRF_DWIDTH-1:28*`MRF_DWIDTH]; + end + `MRF_29: begin + output_data_to_dram <= mrf_outa_to_dram[30*`MRF_DWIDTH-1:29*`MRF_DWIDTH]; + end + `MRF_30: begin + output_data_to_dram <= mrf_outa_to_dram[31*`MRF_DWIDTH-1:30*`MRF_DWIDTH]; + end + `MRF_31: begin + output_data_to_dram <= mrf_outa_to_dram[32*`MRF_DWIDTH-1:31*`MRF_DWIDTH]; + end + `MRF_32: begin + output_data_to_dram <= mrf_outa_to_dram[33*`MRF_DWIDTH-1:32*`MRF_DWIDTH]; + end + `MRF_33: begin + output_data_to_dram <= mrf_outa_to_dram[34*`MRF_DWIDTH-1:33*`MRF_DWIDTH]; + end + `MRF_34: begin + output_data_to_dram <= mrf_outa_to_dram[35*`MRF_DWIDTH-1:34*`MRF_DWIDTH]; + end + `MRF_35: begin + output_data_to_dram <= mrf_outa_to_dram[36*`MRF_DWIDTH-1:35*`MRF_DWIDTH]; + end + `MRF_36: begin + output_data_to_dram <= mrf_outa_to_dram[37*`MRF_DWIDTH-1:36*`MRF_DWIDTH]; + end + `MRF_37: begin + output_data_to_dram <= mrf_outa_to_dram[38*`MRF_DWIDTH-1:37*`MRF_DWIDTH]; + end + `MRF_38: begin + output_data_to_dram <= mrf_outa_to_dram[39*`MRF_DWIDTH-1:38*`MRF_DWIDTH]; + end + `MRF_39: begin + output_data_to_dram <= mrf_outa_to_dram[40*`MRF_DWIDTH-1:39*`MRF_DWIDTH]; + end + `MRF_40: begin + output_data_to_dram <= mrf_outa_to_dram[41*`MRF_DWIDTH-1:40*`MRF_DWIDTH]; + end + `MRF_41: begin + output_data_to_dram <= mrf_outa_to_dram[42*`MRF_DWIDTH-1:41*`MRF_DWIDTH]; + end + `MRF_42: begin + output_data_to_dram <= mrf_outa_to_dram[43*`MRF_DWIDTH-1:42*`MRF_DWIDTH]; + end + `MRF_43: begin + output_data_to_dram <= mrf_outa_to_dram[44*`MRF_DWIDTH-1:43*`MRF_DWIDTH]; + end + `MRF_44: begin + output_data_to_dram <= mrf_outa_to_dram[45*`MRF_DWIDTH-1:44*`MRF_DWIDTH]; + end + `MRF_45: begin + output_data_to_dram <= mrf_outa_to_dram[46*`MRF_DWIDTH-1:45*`MRF_DWIDTH]; + end + `MRF_46: begin + output_data_to_dram <= mrf_outa_to_dram[47*`MRF_DWIDTH-1:46*`MRF_DWIDTH]; + end + `MRF_47: begin + output_data_to_dram <= mrf_outa_to_dram[48*`MRF_DWIDTH-1:47*`MRF_DWIDTH]; + end + `MRF_48: begin + output_data_to_dram <= mrf_outa_to_dram[49*`MRF_DWIDTH-1:48*`MRF_DWIDTH]; + end + `MRF_49: begin + output_data_to_dram <= mrf_outa_to_dram[50*`MRF_DWIDTH-1:49*`MRF_DWIDTH]; + end + `MRF_50: begin + output_data_to_dram <= mrf_outa_to_dram[51*`MRF_DWIDTH-1:50*`MRF_DWIDTH]; + end + `MRF_51: begin + output_data_to_dram <= mrf_outa_to_dram[52*`MRF_DWIDTH-1:51*`MRF_DWIDTH]; + end + `MRF_52: begin + output_data_to_dram <= mrf_outa_to_dram[53*`MRF_DWIDTH-1:52*`MRF_DWIDTH]; + end + `MRF_53: begin + output_data_to_dram <= mrf_outa_to_dram[54*`MRF_DWIDTH-1:53*`MRF_DWIDTH]; + end + `MRF_54: begin + output_data_to_dram <= mrf_outa_to_dram[55*`MRF_DWIDTH-1:54*`MRF_DWIDTH]; + end + `MRF_55: begin + output_data_to_dram <= mrf_outa_to_dram[56*`MRF_DWIDTH-1:55*`MRF_DWIDTH]; + end + `MRF_56: begin + output_data_to_dram <= mrf_outa_to_dram[57*`MRF_DWIDTH-1:56*`MRF_DWIDTH]; + end + `MRF_57: begin + output_data_to_dram <= mrf_outa_to_dram[58*`MRF_DWIDTH-1:57*`MRF_DWIDTH]; + end + `MRF_58: begin + output_data_to_dram <= mrf_outa_to_dram[59*`MRF_DWIDTH-1:58*`MRF_DWIDTH]; + end + `MRF_59: begin + output_data_to_dram <= mrf_outa_to_dram[60*`MRF_DWIDTH-1:59*`MRF_DWIDTH]; + end + `MRF_60: begin + output_data_to_dram <= mrf_outa_to_dram[61*`MRF_DWIDTH-1:60*`MRF_DWIDTH]; + end + `MRF_61: begin + output_data_to_dram <= mrf_outa_to_dram[62*`MRF_DWIDTH-1:61*`MRF_DWIDTH]; + end + `MRF_62: begin + output_data_to_dram <= mrf_outa_to_dram[63*`MRF_DWIDTH-1:62*`MRF_DWIDTH]; + end + `MRF_63: begin + output_data_to_dram <= mrf_outa_to_dram[64*`MRF_DWIDTH-1:63*`MRF_DWIDTH]; + end + default: begin + output_data_to_dram <= 'd0; + end + endcase + + end + `V_RD: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + vrf_in_data <= input_data_from_dram; + case(dstn_id) + `VRF_0: begin + vrf_wr_enable_mvu_0 <= 1'b1; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_1: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b1; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_2: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b1; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_3: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b1; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_4: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b1; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_add_0 <= dstn_address; + + end + + `VRF_5: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b1; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_mul_0 <= dstn_address; + + end + + `VRF_6: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b1; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_add_1 <= dstn_address; + end + + `VRF_7: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b1; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_mul_1 <= dstn_address; + end + + `VRF_MUXED: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b1; + + + vrf_muxed_wr_addr_dram <= dstn_address; + end + + default: begin + vrf_wr_enable_mvu_0 <= 1'bX; + vrf_wr_enable_mvu_1 <= 1'bX; + vrf_wr_enable_mvu_2 <= 1'bX; + vrf_wr_enable_mvu_3 <= 1'bX; + vrf_wr_enable_mfu_add_0 <= 1'bX; + vrf_wr_enable_mfu_mul_0 <= 1'bX; + vrf_wr_enable_mfu_add_1 <= 1'bX; + vrf_wr_enable_mfu_mul_1 <= 1'bX; + vrf_muxed_wr_enable_dram <= 1'bX; + + end + endcase +/* + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; +*/ + + end + `M_RD: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(dstn_id) + `MRF_0: begin + mrf_we_for_dram[0] <= 1; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[1*`MRF_DWIDTH-1:0*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[1*`MRF_AWIDTH-1:0*`MRF_AWIDTH] <= dstn_address; + end + `MRF_1: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 1; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[2*`MRF_DWIDTH-1:1*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[2*`MRF_AWIDTH-1:1*`MRF_AWIDTH] <= dstn_address; + end + `MRF_2: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 1; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[3*`MRF_DWIDTH-1:2*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[3*`MRF_AWIDTH-1:2*`MRF_AWIDTH] <= dstn_address; + end + `MRF_3: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 1; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[4*`MRF_DWIDTH-1:3*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[4*`MRF_AWIDTH-1:3*`MRF_AWIDTH] <= dstn_address; + end + `MRF_4: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 1; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[5*`MRF_DWIDTH-1:4*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[5*`MRF_AWIDTH-1:4*`MRF_AWIDTH] <= dstn_address; + end + `MRF_5: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 1; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[6*`MRF_DWIDTH-1:5*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[6*`MRF_AWIDTH-1:5*`MRF_AWIDTH] <= dstn_address; + end + `MRF_6: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 1; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[7*`MRF_DWIDTH-1:6*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[7*`MRF_AWIDTH-1:6*`MRF_AWIDTH] <= dstn_address; + end + `MRF_7: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 1; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[8*`MRF_DWIDTH-1:7*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[8*`MRF_AWIDTH-1:7*`MRF_AWIDTH] <= dstn_address; + end + `MRF_8: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 1; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[9*`MRF_DWIDTH-1:8*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[9*`MRF_AWIDTH-1:8*`MRF_AWIDTH] <= dstn_address; + end + `MRF_9: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 1; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[10*`MRF_DWIDTH-1:9*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[10*`MRF_AWIDTH-1:9*`MRF_AWIDTH] <= dstn_address; + end + `MRF_10: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 1; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[11*`MRF_DWIDTH-1:10*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[11*`MRF_AWIDTH-1:10*`MRF_AWIDTH] <= dstn_address; + end + `MRF_11: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 1; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[12*`MRF_DWIDTH-1:11*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[12*`MRF_AWIDTH-1:11*`MRF_AWIDTH] <= dstn_address; + end + `MRF_12: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 1; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[13*`MRF_DWIDTH-1:12*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[13*`MRF_AWIDTH-1:12*`MRF_AWIDTH] <= dstn_address; + end + `MRF_13: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 1; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[14*`MRF_DWIDTH-1:13*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[14*`MRF_AWIDTH-1:13*`MRF_AWIDTH] <= dstn_address; + end + `MRF_14: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 1; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[15*`MRF_DWIDTH-1:14*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[15*`MRF_AWIDTH-1:14*`MRF_AWIDTH] <= dstn_address; + end + `MRF_15: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 1; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[16*`MRF_DWIDTH-1:15*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[16*`MRF_AWIDTH-1:15*`MRF_AWIDTH] <= dstn_address; + end + `MRF_16: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 1; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[17*`MRF_DWIDTH-1:16*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[17*`MRF_AWIDTH-1:16*`MRF_AWIDTH] <= dstn_address; + end + `MRF_17: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 1; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[18*`MRF_DWIDTH-1:17*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[18*`MRF_AWIDTH-1:17*`MRF_AWIDTH] <= dstn_address; + end + `MRF_18: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 1; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[19*`MRF_DWIDTH-1:18*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[19*`MRF_AWIDTH-1:18*`MRF_AWIDTH] <= dstn_address; + end + `MRF_19: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 1; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[20*`MRF_DWIDTH-1:19*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[20*`MRF_AWIDTH-1:19*`MRF_AWIDTH] <= dstn_address; + end + `MRF_20: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 1; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[21*`MRF_DWIDTH-1:20*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[21*`MRF_AWIDTH-1:20*`MRF_AWIDTH] <= dstn_address; + end + `MRF_21: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 1; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[22*`MRF_DWIDTH-1:21*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[22*`MRF_AWIDTH-1:21*`MRF_AWIDTH] <= dstn_address; + end + `MRF_22: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 1; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[23*`MRF_DWIDTH-1:22*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[23*`MRF_AWIDTH-1:22*`MRF_AWIDTH] <= dstn_address; + end + `MRF_23: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 1; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[24*`MRF_DWIDTH-1:23*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[24*`MRF_AWIDTH-1:23*`MRF_AWIDTH] <= dstn_address; + end + `MRF_24: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 1; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[25*`MRF_DWIDTH-1:24*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[25*`MRF_AWIDTH-1:24*`MRF_AWIDTH] <= dstn_address; + end + `MRF_25: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 1; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[26*`MRF_DWIDTH-1:25*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[26*`MRF_AWIDTH-1:25*`MRF_AWIDTH] <= dstn_address; + end + `MRF_26: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 1; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[27*`MRF_DWIDTH-1:26*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[27*`MRF_AWIDTH-1:26*`MRF_AWIDTH] <= dstn_address; + end + `MRF_27: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 1; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[28*`MRF_DWIDTH-1:27*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[28*`MRF_AWIDTH-1:27*`MRF_AWIDTH] <= dstn_address; + end + `MRF_28: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 1; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[29*`MRF_DWIDTH-1:28*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[29*`MRF_AWIDTH-1:28*`MRF_AWIDTH] <= dstn_address; + end + `MRF_29: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 1; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[30*`MRF_DWIDTH-1:29*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[30*`MRF_AWIDTH-1:29*`MRF_AWIDTH] <= dstn_address; + end + `MRF_30: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 1; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[31*`MRF_DWIDTH-1:30*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[31*`MRF_AWIDTH-1:30*`MRF_AWIDTH] <= dstn_address; + end + `MRF_31: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 1; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[32*`MRF_DWIDTH-1:31*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[32*`MRF_AWIDTH-1:31*`MRF_AWIDTH] <= dstn_address; + end + `MRF_32: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 1; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[33*`MRF_DWIDTH-1:32*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[33*`MRF_AWIDTH-1:32*`MRF_AWIDTH] <= dstn_address; + end + `MRF_33: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 1; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[34*`MRF_DWIDTH-1:33*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[34*`MRF_AWIDTH-1:33*`MRF_AWIDTH] <= dstn_address; + end + `MRF_34: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 1; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[35*`MRF_DWIDTH-1:34*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[35*`MRF_AWIDTH-1:34*`MRF_AWIDTH] <= dstn_address; + end + `MRF_35: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 1; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[36*`MRF_DWIDTH-1:35*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[36*`MRF_AWIDTH-1:35*`MRF_AWIDTH] <= dstn_address; + end + `MRF_36: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 1; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[37*`MRF_DWIDTH-1:36*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[37*`MRF_AWIDTH-1:36*`MRF_AWIDTH] <= dstn_address; + end + `MRF_37: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 1; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[38*`MRF_DWIDTH-1:37*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[38*`MRF_AWIDTH-1:37*`MRF_AWIDTH] <= dstn_address; + end + `MRF_38: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 1; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[39*`MRF_DWIDTH-1:38*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[39*`MRF_AWIDTH-1:38*`MRF_AWIDTH] <= dstn_address; + end + `MRF_39: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 1; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[40*`MRF_DWIDTH-1:39*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[40*`MRF_AWIDTH-1:39*`MRF_AWIDTH] <= dstn_address; + end + `MRF_40: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 1; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[41*`MRF_DWIDTH-1:40*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[41*`MRF_AWIDTH-1:40*`MRF_AWIDTH] <= dstn_address; + end + `MRF_41: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 1; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[42*`MRF_DWIDTH-1:41*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[42*`MRF_AWIDTH-1:41*`MRF_AWIDTH] <= dstn_address; + end + `MRF_42: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 1; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[43*`MRF_DWIDTH-1:42*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[43*`MRF_AWIDTH-1:42*`MRF_AWIDTH] <= dstn_address; + end + `MRF_43: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 1; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[44*`MRF_DWIDTH-1:43*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[44*`MRF_AWIDTH-1:43*`MRF_AWIDTH] <= dstn_address; + end + `MRF_44: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 1; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[45*`MRF_DWIDTH-1:44*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[45*`MRF_AWIDTH-1:44*`MRF_AWIDTH] <= dstn_address; + end + `MRF_45: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 1; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[46*`MRF_DWIDTH-1:45*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[46*`MRF_AWIDTH-1:45*`MRF_AWIDTH] <= dstn_address; + end + `MRF_46: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 1; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[47*`MRF_DWIDTH-1:46*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[47*`MRF_AWIDTH-1:46*`MRF_AWIDTH] <= dstn_address; + end + `MRF_47: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 1; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[48*`MRF_DWIDTH-1:47*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[48*`MRF_AWIDTH-1:47*`MRF_AWIDTH] <= dstn_address; + end + `MRF_48: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 1; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[49*`MRF_DWIDTH-1:48*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[49*`MRF_AWIDTH-1:48*`MRF_AWIDTH] <= dstn_address; + end + `MRF_49: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 1; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[50*`MRF_DWIDTH-1:49*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[50*`MRF_AWIDTH-1:49*`MRF_AWIDTH] <= dstn_address; + end + `MRF_50: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 1; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[51*`MRF_DWIDTH-1:50*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[51*`MRF_AWIDTH-1:50*`MRF_AWIDTH] <= dstn_address; + end + `MRF_51: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 1; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[52*`MRF_DWIDTH-1:51*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[52*`MRF_AWIDTH-1:51*`MRF_AWIDTH] <= dstn_address; + end + `MRF_52: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 1; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[53*`MRF_DWIDTH-1:52*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[53*`MRF_AWIDTH-1:52*`MRF_AWIDTH] <= dstn_address; + end + `MRF_53: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 1; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[54*`MRF_DWIDTH-1:53*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[54*`MRF_AWIDTH-1:53*`MRF_AWIDTH] <= dstn_address; + end + `MRF_54: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 1; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[55*`MRF_DWIDTH-1:54*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[55*`MRF_AWIDTH-1:54*`MRF_AWIDTH] <= dstn_address; + end + `MRF_55: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 1; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[56*`MRF_DWIDTH-1:55*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[56*`MRF_AWIDTH-1:55*`MRF_AWIDTH] <= dstn_address; + end + `MRF_56: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 1; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[57*`MRF_DWIDTH-1:56*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[57*`MRF_AWIDTH-1:56*`MRF_AWIDTH] <= dstn_address; + end + `MRF_57: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 1; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[58*`MRF_DWIDTH-1:57*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[58*`MRF_AWIDTH-1:57*`MRF_AWIDTH] <= dstn_address; + end + `MRF_58: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 1; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[59*`MRF_DWIDTH-1:58*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[59*`MRF_AWIDTH-1:58*`MRF_AWIDTH] <= dstn_address; + end + `MRF_59: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 1; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[60*`MRF_DWIDTH-1:59*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[60*`MRF_AWIDTH-1:59*`MRF_AWIDTH] <= dstn_address; + end + `MRF_60: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 1; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[61*`MRF_DWIDTH-1:60*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[61*`MRF_AWIDTH-1:60*`MRF_AWIDTH] <= dstn_address; + end + `MRF_61: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 1; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[62*`MRF_DWIDTH-1:61*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[62*`MRF_AWIDTH-1:61*`MRF_AWIDTH] <= dstn_address; + end + `MRF_62: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 1; + mrf_we_for_dram[63] <= 0; + mrf_in_data[63*`MRF_DWIDTH-1:62*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[63*`MRF_AWIDTH-1:62*`MRF_AWIDTH] <= dstn_address; + end + `MRF_63: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 1; + mrf_in_data[64*`MRF_DWIDTH-1:63*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[64*`MRF_AWIDTH-1:63*`MRF_AWIDTH] <= dstn_address; + end + + default: begin + mrf_we_for_dram[0] <= 1'bX; + mrf_we_for_dram[1] <= 1'bX; + mrf_we_for_dram[2] <= 1'bX; + mrf_we_for_dram[3] <= 1'bX; + mrf_we_for_dram[4] <= 1'bX; + mrf_we_for_dram[5] <= 1'bX; + mrf_we_for_dram[6] <= 1'bX; + mrf_we_for_dram[7] <= 1'bX; + mrf_we_for_dram[8] <= 1'bX; + mrf_we_for_dram[9] <= 1'bX; + mrf_we_for_dram[10] <= 1'bX; + mrf_we_for_dram[11] <= 1'bX; + mrf_we_for_dram[12] <= 1'bX; + mrf_we_for_dram[13] <= 1'bX; + mrf_we_for_dram[14] <= 1'bX; + mrf_we_for_dram[15] <= 1'bX; + mrf_we_for_dram[16] <= 1'bX; + mrf_we_for_dram[17] <= 1'bX; + mrf_we_for_dram[18] <= 1'bX; + mrf_we_for_dram[19] <= 1'bX; + mrf_we_for_dram[20] <= 1'bX; + mrf_we_for_dram[21] <= 1'bX; + mrf_we_for_dram[22] <= 1'bX; + mrf_we_for_dram[23] <= 1'bX; + mrf_we_for_dram[24] <= 1'bX; + mrf_we_for_dram[25] <= 1'bX; + mrf_we_for_dram[26] <= 1'bX; + mrf_we_for_dram[27] <= 1'bX; + mrf_we_for_dram[28] <= 1'bX; + mrf_we_for_dram[29] <= 1'bX; + mrf_we_for_dram[30] <= 1'bX; + mrf_we_for_dram[31] <= 1'bX; + mrf_we_for_dram[32] <= 1'bX; + mrf_we_for_dram[33] <= 1'bX; + mrf_we_for_dram[34] <= 1'bX; + mrf_we_for_dram[35] <= 1'bX; + mrf_we_for_dram[36] <= 1'bX; + mrf_we_for_dram[37] <= 1'bX; + mrf_we_for_dram[38] <= 1'bX; + mrf_we_for_dram[39] <= 1'bX; + mrf_we_for_dram[40] <= 1'bX; + mrf_we_for_dram[41] <= 1'bX; + mrf_we_for_dram[42] <= 1'bX; + mrf_we_for_dram[43] <= 1'bX; + mrf_we_for_dram[44] <= 1'bX; + mrf_we_for_dram[45] <= 1'bX; + mrf_we_for_dram[46] <= 1'bX; + mrf_we_for_dram[47] <= 1'bX; + mrf_we_for_dram[48] <= 1'bX; + mrf_we_for_dram[49] <= 1'bX; + mrf_we_for_dram[50] <= 1'bX; + mrf_we_for_dram[51] <= 1'bX; + mrf_we_for_dram[52] <= 1'bX; + mrf_we_for_dram[53] <= 1'bX; + mrf_we_for_dram[54] <= 1'bX; + mrf_we_for_dram[55] <= 1'bX; + mrf_we_for_dram[56] <= 1'bX; + mrf_we_for_dram[57] <= 1'bX; + mrf_we_for_dram[58] <= 1'bX; + mrf_we_for_dram[59] <= 1'bX; + mrf_we_for_dram[60] <= 1'bX; + mrf_we_for_dram[61] <= 1'bX; + mrf_we_for_dram[62] <= 1'bX; + mrf_we_for_dram[63] <= 1'bX; + end + + endcase + end + default: begin + + if(done_mvm || done_mfu_0 || done_mfu_1) begin + start_mv_mul <= 0; + start_mfu_0 <= 0; + start_mfu_1 <= 0; + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(dstn_id) + `VRF_0: begin + vrf_wr_enable_mvu_0 <= 1'b1; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_1: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b1; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_2: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b1; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_3: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b1; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + + `VRF_4: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b1; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_add_0 <= dstn_address; + + end + + `VRF_5: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b1; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_mul_0 <= dstn_address; + + end + + `VRF_6: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b1; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_add_1 <= dstn_address; + end + + `VRF_7: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b1; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_mul_1 <= dstn_address; + end + + `VRF_MUXED: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b1; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_muxed_wr_addr_dram <= dstn_address; + end + + `DRAM_MEM_ID: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b1; + + output_data_to_dram <= output_final_stage; + + dram_addr_wr <= dstn_address; + end + + //MFU_OUT_STAGE IDS USED FOR MUXING + + default: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + end + endcase + end + end + endcase + end + end + end +endmodule +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM mvu.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + + +module MVU ( + input clk, + input[`NUM_LDPES-1:0] start, + input[`NUM_LDPES-1:0] reset, + + input [`VRF_AWIDTH-1:0] vrf_wr_addr, + input [`VRF_AWIDTH-1:0] vrf_read_addr, + input [`VRF_DWIDTH-1:0] vec, + + input vrf_wr_enable_tile_0, + input vrf_readn_enable_tile_0, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_0, + input vrf_wr_enable_tile_1, + input vrf_readn_enable_tile_1, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_1, + input vrf_wr_enable_tile_2, + input vrf_readn_enable_tile_2, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_2, + input vrf_wr_enable_tile_3, + input vrf_readn_enable_tile_3, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_3, + + input [`MRF_DWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_in, + input[`NUM_TILES*`NUM_LDPES-1:0] mrf_we, + input [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr, + + input [`NUM_TILES*`NUM_LDPES-1:0] mrf_we_for_dram, + input [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram, + output [`NUM_TILES*`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram, + + output [`ORF_DWIDTH-1:0] mvm_result, + output out_data_available +); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_0; + wire[`NUM_LDPES-1:0] out_data_available_mvu_tile_0; + + MVU_tile tile_0(.clk(clk), + .start(start), + .reset(reset), + .out_data_available(out_data_available_mvu_tile_0), //WITH TAG + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .vrf_data_out(vrf_data_out_tile_0), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_0), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_0), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .mrf_in(mrf_in[1*`MRF_DWIDTH*`NUM_LDPES-1:0*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[1*`NUM_LDPES-1:0*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[1*`NUM_LDPES*`MRF_AWIDTH-1:0*`NUM_LDPES*`MRF_AWIDTH]), + + .mrf_we_for_dram(mrf_we_for_dram[1*`NUM_LDPES-1:0*`NUM_LDPES]), + .mrf_addr_for_dram(mrf_addr_for_dram[1*`NUM_LDPES*`MRF_AWIDTH-1:0*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[1*`NUM_LDPES*`MRF_DWIDTH-1:0*`NUM_LDPES*`MRF_DWIDTH]), + + .result(result_mvm_0) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_1; + wire[`NUM_LDPES-1:0] out_data_available_mvu_tile_1; + + MVU_tile tile_1(.clk(clk), + .start(start), + .reset(reset), + .out_data_available(out_data_available_mvu_tile_1), //WITH TAG + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .vrf_data_out(vrf_data_out_tile_1), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_1), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_1), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .mrf_in(mrf_in[2*`MRF_DWIDTH*`NUM_LDPES-1:1*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[2*`NUM_LDPES-1:1*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[2*`NUM_LDPES*`MRF_AWIDTH-1:1*`NUM_LDPES*`MRF_AWIDTH]), + + .mrf_we_for_dram(mrf_we_for_dram[2*`NUM_LDPES-1:1*`NUM_LDPES]), + .mrf_addr_for_dram(mrf_addr_for_dram[2*`NUM_LDPES*`MRF_AWIDTH-1:1*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[2*`NUM_LDPES*`MRF_DWIDTH-1:1*`NUM_LDPES*`MRF_DWIDTH]), + + .result(result_mvm_1) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_2; + wire[`NUM_LDPES-1:0] out_data_available_mvu_tile_2; + + MVU_tile tile_2(.clk(clk), + .start(start), + .reset(reset), + .out_data_available(out_data_available_mvu_tile_2), //WITH TAG + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .vrf_data_out(vrf_data_out_tile_2), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_2), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_2), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .mrf_in(mrf_in[3*`MRF_DWIDTH*`NUM_LDPES-1:2*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[3*`NUM_LDPES-1:2*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[3*`NUM_LDPES*`MRF_AWIDTH-1:2*`NUM_LDPES*`MRF_AWIDTH]), + + .mrf_we_for_dram(mrf_we_for_dram[3*`NUM_LDPES-1:2*`NUM_LDPES]), + .mrf_addr_for_dram(mrf_addr_for_dram[3*`NUM_LDPES*`MRF_AWIDTH-1:2*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[3*`NUM_LDPES*`MRF_DWIDTH-1:2*`NUM_LDPES*`MRF_DWIDTH]), + + .result(result_mvm_2) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_3; + wire[`NUM_LDPES-1:0] out_data_available_mvu_tile_3; + + MVU_tile tile_3(.clk(clk), + .start(start), + .reset(reset), + .out_data_available(out_data_available_mvu_tile_3), //WITH TAG + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .vrf_data_out(vrf_data_out_tile_3), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_3), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_3), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .mrf_in(mrf_in[4*`MRF_DWIDTH*`NUM_LDPES-1:3*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[4*`NUM_LDPES-1:3*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[4*`NUM_LDPES*`MRF_AWIDTH-1:3*`NUM_LDPES*`MRF_AWIDTH]), + + .mrf_we_for_dram(mrf_we_for_dram[4*`NUM_LDPES-1:3*`NUM_LDPES]), + .mrf_addr_for_dram(mrf_addr_for_dram[4*`NUM_LDPES*`MRF_AWIDTH-1:3*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[4*`NUM_LDPES*`MRF_DWIDTH-1:3*`NUM_LDPES*`MRF_DWIDTH]), + + .result(result_mvm_3) //WITH TAG + ); + + wire[`NUM_LDPES*`OUT_DWIDTH-1:0] reduction_unit_output; + wire[`NUM_LDPES-1:0] out_data_available_reduction_tree; + + mvm_reduction_unit mvm_reduction( + .clk(clk), + .start(out_data_available_mvu_tile_0), + .reset_reduction_mvm(reset), + .inp0(result_mvm_0), + .inp1(result_mvm_1), + .inp2(result_mvm_2), + .inp3(result_mvm_3), + .result_mvm_final_stage(reduction_unit_output), + .out_data_available(out_data_available_reduction_tree) + ); + + assign mvm_result = reduction_unit_output; + assign out_data_available = out_data_available_reduction_tree[0]; + +endmodule + + +module MVU_tile ( + input clk, + input [`NUM_LDPES-1:0] start, + input [`NUM_LDPES-1:0] reset, + input vrf_wr_enable, + input [`VRF_AWIDTH-1:0] vrf_wr_addr, + input [`VRF_AWIDTH-1:0] vrf_read_addr, + input [`VRF_DWIDTH-1:0] vec, + output[`VRF_DWIDTH-1:0] vrf_data_out, + input [`NUM_LDPES*`MRF_DWIDTH-1:0] mrf_in, + input vrf_readn_enable, + input[`NUM_LDPES-1:0] mrf_we, + input [`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr, + + input[`NUM_LDPES-1:0] mrf_we_for_dram, + input [`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram, + output [`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram, + + output [`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result, + output [`NUM_LDPES-1:0] out_data_available +); + + wire [`VRF_DWIDTH-1:0] ina_fake; + + + wire [`VRF_DWIDTH-1:0] vrf_outa_wire; + + //reg [`VRF_AWIDTH-1:0] vrf_rd_addr; + + // Port A is used to feed LDPE and port B to load vector from DRAM. + VRF vrf ( + .clk(clk), + .addra(vrf_read_addr), + .ina(ina_fake), + .wea(vrf_readn_enable), + .outa(vrf_outa_wire), + .addrb(vrf_wr_addr), + .inb(vec), + .web(vrf_wr_enable), + .outb(vrf_data_out) + ); + + genvar i; + generate + for (i=1; i<=`NUM_LDPES; i=i+1) begin: gen_cus + compute_unit unit ( + .clk(clk), + .start(start[i-1]), + .reset(reset[i-1]), + .out_data_available(out_data_available[i-1]), + .vec(vrf_outa_wire), + .mrf_in(mrf_in[i*`MRF_DWIDTH-1:(i-1)*`MRF_DWIDTH]), + .mrf_we(mrf_we[i-1]), + .mrf_addr(mrf_addr[i*`MRF_AWIDTH-1:(i-1)*`MRF_AWIDTH]), + + .mrf_addr_for_dram(mrf_addr_for_dram[(i)*`MRF_AWIDTH-1:(i-1)*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[(i)*`MRF_DWIDTH-1:(i-1)*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[i-1]), + + .result(result[i*`LDPE_USED_OUTPUT_WIDTH-1:(i-1)*`LDPE_USED_OUTPUT_WIDTH]) + ); + end + endgenerate + +endmodule + +module compute_unit ( + input clk, + input start, + input reset, + input [`VRF_DWIDTH-1:0] vec, + input [`MRF_DWIDTH-1:0] mrf_in, + input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new + input mrf_we, mrf_we_for_dram, //new + input [`MRF_AWIDTH-1:0] mrf_addr, + output [`LDPE_USED_OUTPUT_WIDTH-1:0] result, + output [`MRF_DWIDTH-1:0] mrf_outa_to_dram, //new + output reg out_data_available +); + + // Port A of BRAMs is used for feed DSPs and Port B is used to load matrix from off-chip memory + reg [4:0] num_cycles_mvm; + + always@(posedge clk) begin + if((reset==1'b1) || (start==1'b0)) begin + num_cycles_mvm <= 0; + out_data_available <= 0; + end + else begin + if(num_cycles_mvm==`NUM_MVM_CYCLES-1) begin + out_data_available <= 1; + end + else begin + num_cycles_mvm <= num_cycles_mvm + 1'b1; + end + end + end + + // Port B of BRAMs is used for feed DSPs and Port A is used to interact with DRAM + + + wire [`MRF_DWIDTH-1:0] mrf_outb_wire; + + wire [`LDPE_USED_INPUT_WIDTH-1:0] ax_wire; + wire [`LDPE_USED_INPUT_WIDTH-1:0] ay_wire; + wire [`LDPE_USED_INPUT_WIDTH-1:0] bx_wire; + wire [`LDPE_USED_INPUT_WIDTH-1:0] by_wire; + + // Wire connecting LDPE output to Output BRAM input + wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result; + + wire [`LDPE_USED_OUTPUT_WIDTH-1:0] inb_fake_wire; + + // First 4 BRAM outputs are given to ax of 4 DSPs and next 4 BRAM outputs are given to bx of DSPs + + // Connection MRF and LDPE wires for matrix data + // 'X' pin is used for matrix + /* If there are 4 DSPSs, bit[31:0] of mrf output contain ax values for the 4 DSPs, bit[63:32] contain bx values and so on. With a group of ax values, bit[7:0] contain ax value for DSP1, bit[15:8] contain ax value for DSP2 and so on. */ + assign ax_wire = mrf_outb_wire[1*`LDPE_USED_INPUT_WIDTH-1:0*`LDPE_USED_INPUT_WIDTH]; + assign bx_wire = mrf_outb_wire[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH]; + + // Connection of VRF and LDPE wires for vector data + // 'Y' pin is used for vector + assign ay_wire = vec[`LDPE_USED_INPUT_WIDTH-1:0]; + assign by_wire = vec[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH]; + + wire [`MRF_DWIDTH-1:0] mrf_in_fake; + + MRF mrf ( + .clk(clk), + .addra(mrf_addr_for_dram), + .addrb(mrf_addr), + .ina(mrf_in), + .inb(mrf_in_fake), + .wea(mrf_we_for_dram), + .web(mrf_we), + .outa(mrf_outa_to_dram), + .outb(mrf_outb_wire) + ); + + LDPE ldpe ( + .clk(clk), + .reset(reset), + .ax(ax_wire), + .ay(ay_wire), + .bx(bx_wire), + .by(by_wire), + .ldpe_result(ldpe_result) + ); + assign result = ldpe_result; + +endmodule + +module LDPE ( + input clk, + input reset, + input [`LDPE_USED_INPUT_WIDTH-1:0] ax, + input [`LDPE_USED_INPUT_WIDTH-1:0] ay, + input [`LDPE_USED_INPUT_WIDTH-1:0] bx, + input [`LDPE_USED_INPUT_WIDTH-1:0] by, + output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result +); + + wire [`LDPE_USED_OUTPUT_WIDTH*`SUB_LDPES_PER_LDPE-1:0] sub_ldpe_result; + //wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result; + + SUB_LDPE sub_1( + .clk(clk), + .reset(reset), + .ax(ax[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .ay(ay[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .bx(bx[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .by(by[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .result(sub_ldpe_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH]) + ); + assign ldpe_result = sub_ldpe_result[(0+1)*`DSP_USED_OUTPUT_WIDTH-1:0*`DSP_USED_OUTPUT_WIDTH]; + +endmodule + +module myadder #( + parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH, + parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH +) +( + input [INPUT_WIDTH-1:0] a, + input [INPUT_WIDTH-1:0] b, + input reset, + input start, + input clk, + output reg [OUTPUT_WIDTH-1:0] sum, + output reg out_data_available +); + + always@(posedge clk) begin + if((reset==1) || (start==0)) begin + sum <= 0; + out_data_available <= 0; + end + else begin + out_data_available <= 1; + sum <= a + b; + end + end + +endmodule + +module SUB_LDPE ( + input clk, + input reset, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] ax, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] ay, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] bx, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] by, + output reg [`LDPE_USED_OUTPUT_WIDTH-1:0] result +); + + wire [`DSP_USED_OUTPUT_WIDTH*`DSPS_PER_SUB_LDPE-1:0] chainin, chainout, dsp_result; + + + wire [36:0] chainout_temp_0; + assign chainout_temp_0 = 37'b0; + + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_1; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_1; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_1; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_1; + + assign ax_wire_1 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax[1*`DSP_USED_INPUT_WIDTH-1:(1-1)*`DSP_USED_INPUT_WIDTH]}; + assign ay_wire_1 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay[1*`DSP_USED_INPUT_WIDTH-1:(1-1)*`DSP_USED_INPUT_WIDTH]}; + + assign bx_wire_1 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx[1*`DSP_USED_INPUT_WIDTH-1:(1-1)*`DSP_USED_INPUT_WIDTH]}; + assign by_wire_1 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, by[1*`DSP_USED_INPUT_WIDTH-1:(1-1)*`DSP_USED_INPUT_WIDTH]}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_1; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_1; + + assign dsp_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_1[`DSP_USED_OUTPUT_WIDTH-1:0]; + + dsp_block_18_18_int_sop_2 dsp_1 ( + .clk(clk), + .aclr(reset), + .ax(ax_wire_1), + .ay(ay_wire_1), + .bx(bx_wire_1), + .by(by_wire_1), + .chainin(chainout_temp_0), + .chainout(chainout_temp_1), + .result(result_temp_1) + ); + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_2; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_2; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_2; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_2; + + assign ax_wire_2 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax[2*`DSP_USED_INPUT_WIDTH-1:(2-1)*`DSP_USED_INPUT_WIDTH]}; + assign ay_wire_2 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay[2*`DSP_USED_INPUT_WIDTH-1:(2-1)*`DSP_USED_INPUT_WIDTH]}; + + assign bx_wire_2 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx[2*`DSP_USED_INPUT_WIDTH-1:(2-1)*`DSP_USED_INPUT_WIDTH]}; + assign by_wire_2 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, by[2*`DSP_USED_INPUT_WIDTH-1:(2-1)*`DSP_USED_INPUT_WIDTH]}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_2; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_2; + + assign dsp_result[2*`DSP_USED_OUTPUT_WIDTH-1:(2-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_2[`DSP_USED_OUTPUT_WIDTH-1:0]; + + dsp_block_18_18_int_sop_2 dsp_2 ( + .clk(clk), + .aclr(reset), + .ax(ax_wire_2), + .ay(ay_wire_2), + .bx(bx_wire_2), + .by(by_wire_2), + .chainin(chainout_temp_1), + .chainout(chainout_temp_2), + .result(result_temp_2) + ); + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_3; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_3; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_3; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_3; + + assign ax_wire_3 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax[3*`DSP_USED_INPUT_WIDTH-1:(3-1)*`DSP_USED_INPUT_WIDTH]}; + assign ay_wire_3 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay[3*`DSP_USED_INPUT_WIDTH-1:(3-1)*`DSP_USED_INPUT_WIDTH]}; + + assign bx_wire_3 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx[3*`DSP_USED_INPUT_WIDTH-1:(3-1)*`DSP_USED_INPUT_WIDTH]}; + assign by_wire_3 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, by[3*`DSP_USED_INPUT_WIDTH-1:(3-1)*`DSP_USED_INPUT_WIDTH]}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_3; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_3; + + assign dsp_result[3*`DSP_USED_OUTPUT_WIDTH-1:(3-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_3[`DSP_USED_OUTPUT_WIDTH-1:0]; + + dsp_block_18_18_int_sop_2 dsp_3 ( + .clk(clk), + .aclr(reset), + .ax(ax_wire_3), + .ay(ay_wire_3), + .bx(bx_wire_3), + .by(by_wire_3), + .chainin(chainout_temp_2), + .chainout(chainout_temp_3), + .result(result_temp_3) + ); + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_4; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_4; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_4; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_4; + + assign ax_wire_4 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax[4*`DSP_USED_INPUT_WIDTH-1:(4-1)*`DSP_USED_INPUT_WIDTH]}; + assign ay_wire_4 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay[4*`DSP_USED_INPUT_WIDTH-1:(4-1)*`DSP_USED_INPUT_WIDTH]}; + + assign bx_wire_4 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx[4*`DSP_USED_INPUT_WIDTH-1:(4-1)*`DSP_USED_INPUT_WIDTH]}; + assign by_wire_4 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, by[4*`DSP_USED_INPUT_WIDTH-1:(4-1)*`DSP_USED_INPUT_WIDTH]}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_4; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_4; + + assign dsp_result[4*`DSP_USED_OUTPUT_WIDTH-1:(4-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_4[`DSP_USED_OUTPUT_WIDTH-1:0]; + + dsp_block_18_18_int_sop_2 dsp_4 ( + .clk(clk), + .aclr(reset), + .ax(ax_wire_4), + .ay(ay_wire_4), + .bx(bx_wire_4), + .by(by_wire_4), + .chainin(chainout_temp_3), + .chainout(chainout_temp_4), + .result(result_temp_4) + ); + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_5; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_5; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_5; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_5; + + assign ax_wire_5 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax[5*`DSP_USED_INPUT_WIDTH-1:(5-1)*`DSP_USED_INPUT_WIDTH]}; + assign ay_wire_5 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay[5*`DSP_USED_INPUT_WIDTH-1:(5-1)*`DSP_USED_INPUT_WIDTH]}; + + assign bx_wire_5 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx[5*`DSP_USED_INPUT_WIDTH-1:(5-1)*`DSP_USED_INPUT_WIDTH]}; + assign by_wire_5 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, by[5*`DSP_USED_INPUT_WIDTH-1:(5-1)*`DSP_USED_INPUT_WIDTH]}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_5; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_5; + + assign dsp_result[5*`DSP_USED_OUTPUT_WIDTH-1:(5-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_5[`DSP_USED_OUTPUT_WIDTH-1:0]; + + dsp_block_18_18_int_sop_2 dsp_5 ( + .clk(clk), + .aclr(reset), + .ax(ax_wire_5), + .ay(ay_wire_5), + .bx(bx_wire_5), + .by(by_wire_5), + .chainin(chainout_temp_4), + .chainout(chainout_temp_5), + .result(result_temp_5) + ); + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_6; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_6; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_6; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_6; + + assign ax_wire_6 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax[6*`DSP_USED_INPUT_WIDTH-1:(6-1)*`DSP_USED_INPUT_WIDTH]}; + assign ay_wire_6 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay[6*`DSP_USED_INPUT_WIDTH-1:(6-1)*`DSP_USED_INPUT_WIDTH]}; + + assign bx_wire_6 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx[6*`DSP_USED_INPUT_WIDTH-1:(6-1)*`DSP_USED_INPUT_WIDTH]}; + assign by_wire_6 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, by[6*`DSP_USED_INPUT_WIDTH-1:(6-1)*`DSP_USED_INPUT_WIDTH]}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_6; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_6; + + assign dsp_result[6*`DSP_USED_OUTPUT_WIDTH-1:(6-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_6[`DSP_USED_OUTPUT_WIDTH-1:0]; + + dsp_block_18_18_int_sop_2 dsp_6 ( + .clk(clk), + .aclr(reset), + .ax(ax_wire_6), + .ay(ay_wire_6), + .bx(bx_wire_6), + .by(by_wire_6), + .chainin(chainout_temp_5), + .chainout(chainout_temp_6), + .result(result_temp_6) + ); + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_7; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_7; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_7; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_7; + + assign ax_wire_7 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax[7*`DSP_USED_INPUT_WIDTH-1:(7-1)*`DSP_USED_INPUT_WIDTH]}; + assign ay_wire_7 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay[7*`DSP_USED_INPUT_WIDTH-1:(7-1)*`DSP_USED_INPUT_WIDTH]}; + + assign bx_wire_7 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx[7*`DSP_USED_INPUT_WIDTH-1:(7-1)*`DSP_USED_INPUT_WIDTH]}; + assign by_wire_7 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, by[7*`DSP_USED_INPUT_WIDTH-1:(7-1)*`DSP_USED_INPUT_WIDTH]}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_7; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_7; + + assign dsp_result[7*`DSP_USED_OUTPUT_WIDTH-1:(7-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_7[`DSP_USED_OUTPUT_WIDTH-1:0]; + + dsp_block_18_18_int_sop_2 dsp_7 ( + .clk(clk), + .aclr(reset), + .ax(ax_wire_7), + .ay(ay_wire_7), + .bx(bx_wire_7), + .by(by_wire_7), + .chainin(chainout_temp_6), + .chainout(chainout_temp_7), + .result(result_temp_7) + ); + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_8; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_8; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_8; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_8; + + assign ax_wire_8 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax[8*`DSP_USED_INPUT_WIDTH-1:(8-1)*`DSP_USED_INPUT_WIDTH]}; + assign ay_wire_8 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay[8*`DSP_USED_INPUT_WIDTH-1:(8-1)*`DSP_USED_INPUT_WIDTH]}; + + assign bx_wire_8 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx[8*`DSP_USED_INPUT_WIDTH-1:(8-1)*`DSP_USED_INPUT_WIDTH]}; + assign by_wire_8 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, by[8*`DSP_USED_INPUT_WIDTH-1:(8-1)*`DSP_USED_INPUT_WIDTH]}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_8; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_8; + + assign dsp_result[8*`DSP_USED_OUTPUT_WIDTH-1:(8-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_8[`DSP_USED_OUTPUT_WIDTH-1:0]; + + dsp_block_18_18_int_sop_2 dsp_8 ( + .clk(clk), + .aclr(reset), + .ax(ax_wire_8), + .ay(ay_wire_8), + .bx(bx_wire_8), + .by(by_wire_8), + .chainin(chainout_temp_7), + .chainout(chainout_temp_8), + .result(result_temp_8) + ); + + always @(*) begin + if (reset) begin + result <= {`LDPE_USED_OUTPUT_WIDTH{1'd0}}; + end + else begin + result <= dsp_result[`DSPS_PER_SUB_LDPE*`LDPE_USED_OUTPUT_WIDTH-1:(`DSPS_PER_SUB_LDPE-1)*`LDPE_USED_OUTPUT_WIDTH]; + end + end + +endmodule + +module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) ( + input clk, + input [VRF_AWIDTH-1:0] addra, + input [VRF_AWIDTH-1:0] addrb, + input [VRF_DWIDTH-1:0] ina, + input [VRF_DWIDTH-1:0] inb, + input wea, web, + output [VRF_DWIDTH-1:0] outa, + output [VRF_DWIDTH-1:0] outb +); + + dp_ram # ( + .AWIDTH(VRF_AWIDTH), + .DWIDTH(VRF_DWIDTH) + ) vec_mem ( + .clk(clk), + .addra(addra), + .ina(ina), + .wea(wea), + .outa(outa), + .addrb(addrb), + .inb(inb), + .web(web), + .outb(outb) + ); +endmodule + +module MRF ( + input clk, + input [`MRF_AWIDTH-1:0] addra, + input [`MRF_AWIDTH-1:0] addrb, + input [`MRF_DWIDTH-1:0] ina, + input [`MRF_DWIDTH-1:0] inb, + input wea, web, + output [`MRF_DWIDTH-1:0] outa, + output [`MRF_DWIDTH-1:0] outb +); + + dp_ram # ( + .AWIDTH(`MRF_AWIDTH), + .DWIDTH(`MRF_DWIDTH) + ) vec_mem ( + .clk(clk), + .addra(addra), + .ina(ina), + .wea(wea), + .outa(outa), + .addrb(addrb), + .inb(inb), + .web(web), + .outb(outb) + ); + +endmodule + +module dsp_block_18_18_int_sop_2 ( + input clk, + input aclr, + input [`DSP_X_AVA_INPUT_WIDTH-1:0] ax, + input [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay, + input [`DSP_X_AVA_INPUT_WIDTH-1:0] bx, + input [`DSP_Y_AVA_INPUT_WIDTH-1:0] by, + input [`DSP_AVA_OUTPUT_WIDTH-1:0] chainin, + output [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout, + output [`DSP_AVA_OUTPUT_WIDTH-1:0] result +); + +`ifndef complex_dsp + +reg [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_reg; +reg [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_reg; +reg [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_reg; +reg [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_reg; +reg [`DSP_AVA_OUTPUT_WIDTH-1:0] result_reg; + +always @(posedge clk) begin + if(aclr) begin + result_reg <= 0; + ax_reg <= 0; + ay_reg <= 0; + bx_reg <= 0; + by_reg <= 0; + end + else begin + ax_reg <= ax; + ay_reg <= ay; + bx_reg <= bx; + by_reg <= by; + result_reg <= (ax_reg * ay_reg) + (bx_reg * by_reg) + chainin; + end +end +assign chainout = result_reg; +assign result = result_reg; + +`else + +wire [11:0] mode; +assign mode = 12'b0101_0101_0011; + +int_sop_2 mac_component ( + .mode_sigs(mode), + .clk(clk), + .reset(aclr), + .ax(ax), + .ay(ay), + .bx(bx), + .by(by), + .chainin(chainin), + .result(result), + .chainout(chainout) +); + +`endif + +endmodule + +////////////////////////////////// +// Dual port RAM +////////////////////////////////// + +module dp_ram # ( + parameter AWIDTH = 10, + parameter DWIDTH = 16 +) ( + input clk, + input [AWIDTH-1:0] addra, addrb, + input [DWIDTH-1:0] ina, inb, + input wea, web, + output reg [DWIDTH-1:0] outa, outb +); + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram [((1<=90) begin + address[i*4+:4] = 4'b0000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=39 && (inp_data[i*`DWIDTH +:`DWIDTH])<90) begin + address[i*4+:4] = 4'b0001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=28 && (inp_data[i*`DWIDTH +:`DWIDTH])<39) begin + address[i*4+:4] = 4'b0010; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=16 && (inp_data[i*`DWIDTH +:`DWIDTH])<28) begin + address[i*4+:4] = 4'b0011; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=1 && (inp_data[i*`DWIDTH +:`DWIDTH])<16) begin + address[i*4+:4] = 4'b0100; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])==0) begin + address[i*4+:4] = 4'b0101; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-16 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-1) begin + address[i*4+:4] = 4'b0110; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-28 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-16) begin + address[i*4+:4] = 4'b0111; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-39 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-28) begin + address[i*4+:4] = 4'b1000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-90 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-39) begin + address[i*4+:4] = 4'b1001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])<=-90) begin + address[i*4+:4] = 4'b1010; + end + else begin + address[i*4+:4] = 4'b0101; + end + end +end + +endmodule + + +module elt_wise_add( + input enable_add, + input in_data_available, + input add_or_sub, + input [`NUM_LDPES*`DWIDTH-1:0] primary_inp, + input [`NUM_LDPES*`DWIDTH-1:0] secondary_inp, + output [`NUM_LDPES*`DWIDTH-1:0] out_data, + output reg output_available_add, + input clk +); + wire [(`DWIDTH)-1:0] x_0; + wire [(`DWIDTH)-1:0] y_0; + + add a0(.p(out_data[(1*`DWIDTH)-1:(0*`DWIDTH)]),.x(x_0),.y(y_0), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_1; + wire [(`DWIDTH)-1:0] y_1; + + add a1(.p(out_data[(2*`DWIDTH)-1:(1*`DWIDTH)]),.x(x_1),.y(y_1), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_2; + wire [(`DWIDTH)-1:0] y_2; + + add a2(.p(out_data[(3*`DWIDTH)-1:(2*`DWIDTH)]),.x(x_2),.y(y_2), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_3; + wire [(`DWIDTH)-1:0] y_3; + + add a3(.p(out_data[(4*`DWIDTH)-1:(3*`DWIDTH)]),.x(x_3),.y(y_3), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_4; + wire [(`DWIDTH)-1:0] y_4; + + add a4(.p(out_data[(5*`DWIDTH)-1:(4*`DWIDTH)]),.x(x_4),.y(y_4), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_5; + wire [(`DWIDTH)-1:0] y_5; + + add a5(.p(out_data[(6*`DWIDTH)-1:(5*`DWIDTH)]),.x(x_5),.y(y_5), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_6; + wire [(`DWIDTH)-1:0] y_6; + + add a6(.p(out_data[(7*`DWIDTH)-1:(6*`DWIDTH)]),.x(x_6),.y(y_6), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_7; + wire [(`DWIDTH)-1:0] y_7; + + add a7(.p(out_data[(8*`DWIDTH)-1:(7*`DWIDTH)]),.x(x_7),.y(y_7), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_8; + wire [(`DWIDTH)-1:0] y_8; + + add a8(.p(out_data[(9*`DWIDTH)-1:(8*`DWIDTH)]),.x(x_8),.y(y_8), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_9; + wire [(`DWIDTH)-1:0] y_9; + + add a9(.p(out_data[(10*`DWIDTH)-1:(9*`DWIDTH)]),.x(x_9),.y(y_9), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_10; + wire [(`DWIDTH)-1:0] y_10; + + add a10(.p(out_data[(11*`DWIDTH)-1:(10*`DWIDTH)]),.x(x_10),.y(y_10), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_11; + wire [(`DWIDTH)-1:0] y_11; + + add a11(.p(out_data[(12*`DWIDTH)-1:(11*`DWIDTH)]),.x(x_11),.y(y_11), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_12; + wire [(`DWIDTH)-1:0] y_12; + + add a12(.p(out_data[(13*`DWIDTH)-1:(12*`DWIDTH)]),.x(x_12),.y(y_12), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_13; + wire [(`DWIDTH)-1:0] y_13; + + add a13(.p(out_data[(14*`DWIDTH)-1:(13*`DWIDTH)]),.x(x_13),.y(y_13), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_14; + wire [(`DWIDTH)-1:0] y_14; + + add a14(.p(out_data[(15*`DWIDTH)-1:(14*`DWIDTH)]),.x(x_14),.y(y_14), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_15; + wire [(`DWIDTH)-1:0] y_15; + + add a15(.p(out_data[(16*`DWIDTH)-1:(15*`DWIDTH)]),.x(x_15),.y(y_15), .clk(clk), .reset(~enable_add)); + + assign x_0 = primary_inp[(1*`DWIDTH)-1:(0*`DWIDTH)]; + assign x_1 = primary_inp[(2*`DWIDTH)-1:(1*`DWIDTH)]; + assign x_2 = primary_inp[(3*`DWIDTH)-1:(2*`DWIDTH)]; + assign x_3 = primary_inp[(4*`DWIDTH)-1:(3*`DWIDTH)]; + assign x_4 = primary_inp[(5*`DWIDTH)-1:(4*`DWIDTH)]; + assign x_5 = primary_inp[(6*`DWIDTH)-1:(5*`DWIDTH)]; + assign x_6 = primary_inp[(7*`DWIDTH)-1:(6*`DWIDTH)]; + assign x_7 = primary_inp[(8*`DWIDTH)-1:(7*`DWIDTH)]; + assign x_8 = primary_inp[(9*`DWIDTH)-1:(8*`DWIDTH)]; + assign x_9 = primary_inp[(10*`DWIDTH)-1:(9*`DWIDTH)]; + assign x_10 = primary_inp[(11*`DWIDTH)-1:(10*`DWIDTH)]; + assign x_11 = primary_inp[(12*`DWIDTH)-1:(11*`DWIDTH)]; + assign x_12 = primary_inp[(13*`DWIDTH)-1:(12*`DWIDTH)]; + assign x_13 = primary_inp[(14*`DWIDTH)-1:(13*`DWIDTH)]; + assign x_14 = primary_inp[(15*`DWIDTH)-1:(14*`DWIDTH)]; + assign x_15 = primary_inp[(16*`DWIDTH)-1:(15*`DWIDTH)]; + + assign y_0 = secondary_inp[(1*`DWIDTH)-1:(0*`DWIDTH)]; + assign y_1 = secondary_inp[(2*`DWIDTH)-1:(1*`DWIDTH)]; + assign y_2 = secondary_inp[(3*`DWIDTH)-1:(2*`DWIDTH)]; + assign y_3 = secondary_inp[(4*`DWIDTH)-1:(3*`DWIDTH)]; + assign y_4 = secondary_inp[(5*`DWIDTH)-1:(4*`DWIDTH)]; + assign y_5 = secondary_inp[(6*`DWIDTH)-1:(5*`DWIDTH)]; + assign y_6 = secondary_inp[(7*`DWIDTH)-1:(6*`DWIDTH)]; + assign y_7 = secondary_inp[(8*`DWIDTH)-1:(7*`DWIDTH)]; + assign y_8 = secondary_inp[(9*`DWIDTH)-1:(8*`DWIDTH)]; + assign y_9 = secondary_inp[(10*`DWIDTH)-1:(9*`DWIDTH)]; + assign y_10 = secondary_inp[(11*`DWIDTH)-1:(10*`DWIDTH)]; + assign y_11 = secondary_inp[(12*`DWIDTH)-1:(11*`DWIDTH)]; + assign y_12 = secondary_inp[(13*`DWIDTH)-1:(12*`DWIDTH)]; + assign y_13 = secondary_inp[(14*`DWIDTH)-1:(13*`DWIDTH)]; + assign y_14 = secondary_inp[(15*`DWIDTH)-1:(14*`DWIDTH)]; + assign y_15 = secondary_inp[(16*`DWIDTH)-1:(15*`DWIDTH)]; + + reg[`LOG_ADD_LATENCY-1:0] state; + always @(posedge clk) begin + if((enable_add==1'b1) && (in_data_available==1'b1)) begin + if(state!=`ADD_LATENCY) begin + state<=state+1'b1; + end + else begin + output_available_add<=1; + state<=0; + end + end + else begin + output_available_add<=0; + state<=0; + end + end + +endmodule +module elt_wise_mul( + input enable_mul, + input in_data_available, + input [`DESIGN_SIZE*`DWIDTH-1:0] primary_inp, + input [`DESIGN_SIZE*`DWIDTH-1:0] secondary_inp, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output reg output_available_mul, + input clk +); + wire [(`DWIDTH)-1:0] x_0; + wire [(`DWIDTH)-1:0] y_0; + + mult m0(.p(out_data[(1*`DWIDTH)-1:(0*`DWIDTH)]),.x(x_0),.y(y_0), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_1; + wire [(`DWIDTH)-1:0] y_1; + + mult m1(.p(out_data[(2*`DWIDTH)-1:(1*`DWIDTH)]),.x(x_1),.y(y_1), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_2; + wire [(`DWIDTH)-1:0] y_2; + + mult m2(.p(out_data[(3*`DWIDTH)-1:(2*`DWIDTH)]),.x(x_2),.y(y_2), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_3; + wire [(`DWIDTH)-1:0] y_3; + + mult m3(.p(out_data[(4*`DWIDTH)-1:(3*`DWIDTH)]),.x(x_3),.y(y_3), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_4; + wire [(`DWIDTH)-1:0] y_4; + + mult m4(.p(out_data[(5*`DWIDTH)-1:(4*`DWIDTH)]),.x(x_4),.y(y_4), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_5; + wire [(`DWIDTH)-1:0] y_5; + + mult m5(.p(out_data[(6*`DWIDTH)-1:(5*`DWIDTH)]),.x(x_5),.y(y_5), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_6; + wire [(`DWIDTH)-1:0] y_6; + + mult m6(.p(out_data[(7*`DWIDTH)-1:(6*`DWIDTH)]),.x(x_6),.y(y_6), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_7; + wire [(`DWIDTH)-1:0] y_7; + + mult m7(.p(out_data[(8*`DWIDTH)-1:(7*`DWIDTH)]),.x(x_7),.y(y_7), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_8; + wire [(`DWIDTH)-1:0] y_8; + + mult m8(.p(out_data[(9*`DWIDTH)-1:(8*`DWIDTH)]),.x(x_8),.y(y_8), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_9; + wire [(`DWIDTH)-1:0] y_9; + + mult m9(.p(out_data[(10*`DWIDTH)-1:(9*`DWIDTH)]),.x(x_9),.y(y_9), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_10; + wire [(`DWIDTH)-1:0] y_10; + + mult m10(.p(out_data[(11*`DWIDTH)-1:(10*`DWIDTH)]),.x(x_10),.y(y_10), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_11; + wire [(`DWIDTH)-1:0] y_11; + + mult m11(.p(out_data[(12*`DWIDTH)-1:(11*`DWIDTH)]),.x(x_11),.y(y_11), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_12; + wire [(`DWIDTH)-1:0] y_12; + + mult m12(.p(out_data[(13*`DWIDTH)-1:(12*`DWIDTH)]),.x(x_12),.y(y_12), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_13; + wire [(`DWIDTH)-1:0] y_13; + + mult m13(.p(out_data[(14*`DWIDTH)-1:(13*`DWIDTH)]),.x(x_13),.y(y_13), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_14; + wire [(`DWIDTH)-1:0] y_14; + + mult m14(.p(out_data[(15*`DWIDTH)-1:(14*`DWIDTH)]),.x(x_14),.y(y_14), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_15; + wire [(`DWIDTH)-1:0] y_15; + + mult m15(.p(out_data[(16*`DWIDTH)-1:(15*`DWIDTH)]),.x(x_15),.y(y_15), .clk(clk), .reset(~enable_mul)); + + assign x_0 = primary_inp[(1*`DWIDTH)-1:(0*`DWIDTH)]; + assign x_1 = primary_inp[(2*`DWIDTH)-1:(1*`DWIDTH)]; + assign x_2 = primary_inp[(3*`DWIDTH)-1:(2*`DWIDTH)]; + assign x_3 = primary_inp[(4*`DWIDTH)-1:(3*`DWIDTH)]; + assign x_4 = primary_inp[(5*`DWIDTH)-1:(4*`DWIDTH)]; + assign x_5 = primary_inp[(6*`DWIDTH)-1:(5*`DWIDTH)]; + assign x_6 = primary_inp[(7*`DWIDTH)-1:(6*`DWIDTH)]; + assign x_7 = primary_inp[(8*`DWIDTH)-1:(7*`DWIDTH)]; + assign x_8 = primary_inp[(9*`DWIDTH)-1:(8*`DWIDTH)]; + assign x_9 = primary_inp[(10*`DWIDTH)-1:(9*`DWIDTH)]; + assign x_10 = primary_inp[(11*`DWIDTH)-1:(10*`DWIDTH)]; + assign x_11 = primary_inp[(12*`DWIDTH)-1:(11*`DWIDTH)]; + assign x_12 = primary_inp[(13*`DWIDTH)-1:(12*`DWIDTH)]; + assign x_13 = primary_inp[(14*`DWIDTH)-1:(13*`DWIDTH)]; + assign x_14 = primary_inp[(15*`DWIDTH)-1:(14*`DWIDTH)]; + assign x_15 = primary_inp[(16*`DWIDTH)-1:(15*`DWIDTH)]; + + assign y_0 = secondary_inp[(1*`DWIDTH)-1:(0*`DWIDTH)]; + assign y_1 = secondary_inp[(2*`DWIDTH)-1:(1*`DWIDTH)]; + assign y_2 = secondary_inp[(3*`DWIDTH)-1:(2*`DWIDTH)]; + assign y_3 = secondary_inp[(4*`DWIDTH)-1:(3*`DWIDTH)]; + assign y_4 = secondary_inp[(5*`DWIDTH)-1:(4*`DWIDTH)]; + assign y_5 = secondary_inp[(6*`DWIDTH)-1:(5*`DWIDTH)]; + assign y_6 = secondary_inp[(7*`DWIDTH)-1:(6*`DWIDTH)]; + assign y_7 = secondary_inp[(8*`DWIDTH)-1:(7*`DWIDTH)]; + assign y_8 = secondary_inp[(9*`DWIDTH)-1:(8*`DWIDTH)]; + assign y_9 = secondary_inp[(10*`DWIDTH)-1:(9*`DWIDTH)]; + assign y_10 = secondary_inp[(11*`DWIDTH)-1:(10*`DWIDTH)]; + assign y_11 = secondary_inp[(12*`DWIDTH)-1:(11*`DWIDTH)]; + assign y_12 = secondary_inp[(13*`DWIDTH)-1:(12*`DWIDTH)]; + assign y_13 = secondary_inp[(14*`DWIDTH)-1:(13*`DWIDTH)]; + assign y_14 = secondary_inp[(15*`DWIDTH)-1:(14*`DWIDTH)]; + assign y_15 = secondary_inp[(16*`DWIDTH)-1:(15*`DWIDTH)]; + + reg[`LOG_MUL_LATENCY-1:0] state; + always @(posedge clk) begin + if((enable_mul==1'b1) && (in_data_available==1'b1)) begin + + if(state!=`MUL_LATENCY) begin + state<=state+1'b1; + end + else begin + output_available_mul<=1; + state<=0; + end + end + else begin + output_available_mul<=0; + state<=0; + end + end + +endmodule + diff --git a/designs/koios/bwave_like.fixed.large/design.yaml b/designs/koios/bwave_like.fixed.large/design.yaml new file mode 100644 index 000000000..67c7d1848 --- /dev/null +++ b/designs/koios/bwave_like.fixed.large/design.yaml @@ -0,0 +1 @@ +top: bwave_large_random diff --git a/designs/koios/bwave_like.fixed.small/bwave_like.fixed.small.v b/designs/koios/bwave_like.fixed.small/bwave_like.fixed.small.v new file mode 100644 index 000000000..32eec765a --- /dev/null +++ b/designs/koios/bwave_like.fixed.small/bwave_like.fixed.small.v @@ -0,0 +1,4903 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Tanmay Anand +////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////// +// A Microsoft Brainwave Like Design. Uses fixed point precision. +////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM includes.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + +`define IN_PRECISION 8 +`define OUT_PRECISION 8 + +`define NUM_TILES 8 + +`define NUM_LDPES 4 +`define DSPS_PER_LDPE 4 +`define DSPS_PER_SUB_LDPE 4 +`define SUB_LDPES_PER_LDPE (`DSPS_PER_LDPE/`DSPS_PER_SUB_LDPE) + +`define MULTS_PER_DSP 2 +`define DSP_X_AVA_INPUT_WIDTH 18 +`define LDPE_X_AVA_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) +`define DSP_Y_AVA_INPUT_WIDTH 19 +`define LDPE_Y_AVA_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) + +`define DSP_AVA_OUTPUT_WIDTH 37 +`define LDPE_AVA_OUTPUT_WIDTH `DSP_AVA_OUTPUT_WIDTH + +`define DSP_USED_INPUT_WIDTH `IN_PRECISION +`define LDPE_USED_INPUT_WIDTH (`DSP_USED_INPUT_WIDTH * `DSPS_PER_LDPE) +`define SUB_LDPE_USED_INPUT_WIDTH (`DSP_USED_INPUT_WIDTH * `DSPS_PER_SUB_LDPE) +`define DSP_X_ZERO_PAD_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) +`define DSP_Y_ZERO_PAD_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) + +`define DSP_USED_OUTPUT_WIDTH 32 +`define LDPE_USED_OUTPUT_WIDTH `DSP_USED_OUTPUT_WIDTH +`define DSP_ZERO_PAD_OUTPUT_WIDTH (`DSP_AVA_OUTPUT_WIDTH - `DSP_USED_OUTPUT_WIDTH) + +`define LDPES_PER_MRF 1 +`define DSPS_PER_MRF (`DSPS_PER_LDPE * `LDPES_PER_MRF) +`define MAT_BRAM_AWIDTH 10 +`define MAT_BRAM_DWIDTH 16 +`define MAT_BRAMS_PER_MRF_SUBSET 4 +`define MRF_AWIDTH (`MAT_BRAM_AWIDTH) +`define MRF_DWIDTH (`MAT_BRAM_DWIDTH * `MAT_BRAMS_PER_MRF_SUBSET) + +`define ORF_DWIDTH 32 //64 + +`define MAX_VRF_DWIDTH 64 +`define DRAM_DWIDTH `VRF_DWIDTH //this is the max of mrf, vrf and orf widths +`define DRAM_AWIDTH `MRF_AWIDTH + +`define LDPES_PER_VRF 1 +`define DSPS_PER_VRF (`DSPS_PER_LDPE * `LDPES_PER_VRF) +`define VEC_BRAM_AWIDTH 10 +`define VEC_BRAM_DWIDTH 16 +`define BRAMS_PER_VRF 4 +`define VRF_AWIDTH `VEC_BRAM_AWIDTH +`define VRF_DWIDTH (`VEC_BRAM_DWIDTH * `BRAMS_PER_VRF) + +`define LDPES_PER_ORF 1 +`define OUTPUTS_PER_LDPE 1 +`define OUT_BRAM_AWIDTH 10 +`define OUT_BRAM_DWIDTH 16 +`define ORF_AWIDTH `OUT_BRAM_AWIDTH +`define OUT_DWIDTH 8 +//`define ORF_DWIDTH `OUT_DWIDTH*`NUM_LDPES + + +`define DESIGN_SIZE `NUM_LDPES +`define DWIDTH `OUT_PRECISION +`define MASK_WIDTH `OUT_PRECISION + +`define ACTIVATION 2'b00 +`define ELT_WISE_MULTIPLY 2'b10 +`define ELT_WISE_ADD 2'b01 +`define BYPASS 2'b11 + +`define ADD_LATENCY 1 +`define LOG_ADD_LATENCY 1 +`define MUL_LATENCY 1 +`define LOG_MUL_LATENCY 1 +`define ACTIVATION_LATENCY 1 +`define TANH_LATENCY `ACTIVATION_LATENCY+1 + + +`define RELU 2'b00 +`define TANH 2'b01 +`define SIGM 2'b10 +//OPCODES + +`define V_RD 0 +`define V_WR 1 +`define M_RD 2 +`define M_WR 3 +`define MV_MUL 4 +`define VV_ADD 5 +`define VV_SUB 6 //QUESTIONED +`define VV_PASS 7 +`define VV_MUL 8 +`define V_RELU 9 +`define V_SIGM 10 +`define V_TANH 11 +`define END_CHAIN 12 + +//MEM_IDS + +`define VRF_0 0 +`define VRF_1 1 +`define VRF_2 2 +`define VRF_3 3 +`define VRF_4 4 +`define VRF_5 5 +`define VRF_6 6 +`define VRF_7 7 + +`define VRF_8 8 +`define VRF_9 9 +`define VRF_10 10 +`define VRF_11 11 +`define VRF_MUXED 12 +`define DRAM_MEM_ID 13 +`define MFU_0_DSTN_ID 14 +`define MFU_1_DSTN_ID 15 + + +`define MRF_0 0 +`define MRF_1 1 +`define MRF_2 2 +`define MRF_3 3 +`define MRF_4 4 +`define MRF_5 5 +`define MRF_6 6 +`define MRF_7 7 +`define MRF_8 8 +`define MRF_9 9 +`define MRF_10 10 +`define MRF_11 11 +`define MRF_12 12 +`define MRF_13 13 +`define MRF_14 14 +`define MRF_15 15 +`define MRF_16 16 +`define MRF_17 17 +`define MRF_18 18 +`define MRF_19 19 +`define MRF_20 20 +`define MRF_21 21 +`define MRF_22 22 +`define MRF_23 23 +`define MRF_24 24 +`define MRF_25 25 +`define MRF_26 26 +`define MRF_27 27 +`define MRF_28 28 +`define MRF_29 29 +`define MRF_30 30 +`define MRF_31 31 + +`define MFU_0 0 +`define MFU_1 1 + +`define INSTR_MEM_AWIDTH 10 + +`define NUM_MVM_CYCLES 8 + +`define OPCODE_WIDTH 4 +`define TARGET_OP_WIDTH 6 + +`define INSTR_WIDTH `OPCODE_WIDTH+`TARGET_OP_WIDTH+`DRAM_AWIDTH+`TARGET_OP_WIDTH+`VRF_AWIDTH + `VRF_AWIDTH +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM npu.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + + +module NPU( + input reset_npu, + input[`INSTR_WIDTH-1:0] instruction, + input[`DRAM_DWIDTH-1:0] input_data_DRAM, + output [`DRAM_DWIDTH-1:0] output_data_DRAM, + output [`DRAM_AWIDTH-1:0] dram_addr, + output dram_write_enable, + output get_instr, + output[`INSTR_MEM_AWIDTH-1:0] get_instr_addr, + //WRITE DOCUMENTATION EXPLAINING HOW MANY PORTS EACH VRF,MRF, ORF HAS and WHERE IS IT CONNECTED TO + input clk +); + wire[`ORF_DWIDTH-1:0] output_final_stage; + + + wire start_mv_mul_signal; + wire start_mfu_0_signal; + wire start_mfu_1_signal; + + + //SAME SIGNAL FOR ALL THE TILES AS PARALLEL EXECUTION OF TILES IS REQUIRED + reg[`NUM_LDPES-1:0] start_tile_with_single_cyc_latency; + reg[`NUM_LDPES-1:0] reset_tile_with_single_cyc_latency; + // + + wire [`MAX_VRF_DWIDTH-1:0] vrf_in_data; + wire[`VRF_AWIDTH-1:0] vrf_addr_wr; + wire[`VRF_AWIDTH-1:0] vrf_addr_read; + wire [`MRF_DWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_in_data; + + + //MRF SIGNALS + wire[`NUM_LDPES*`NUM_TILES-1:0] mrf_we; + wire [`MRF_AWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_addr_wr; + // + + //FINAL STAGE OUTPUT SIGNALS + wire[`ORF_DWIDTH-1:0] result_mvm; + //reg[`ORF_AWIDTH-1:0] result_addr_mvu_orf; + + //wire orf_addr_increment; + + // + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_0; + wire vrf_mvu_wr_enable_0; + wire vrf_mvu_readn_enable_0; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_1; + wire vrf_mvu_wr_enable_1; + wire vrf_mvu_readn_enable_1; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_2; + wire vrf_mvu_wr_enable_2; + wire vrf_mvu_readn_enable_2; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_3; + wire vrf_mvu_wr_enable_3; + wire vrf_mvu_readn_enable_3; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_4; + wire vrf_mvu_wr_enable_4; + wire vrf_mvu_readn_enable_4; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_5; + wire vrf_mvu_wr_enable_5; + wire vrf_mvu_readn_enable_5; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_6; + wire vrf_mvu_wr_enable_6; + wire vrf_mvu_readn_enable_6; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_7; + wire vrf_mvu_wr_enable_7; + wire vrf_mvu_readn_enable_7; + + wire done_mvm; //CHANGES THE REST STATE OF INSTR DECODER + wire out_data_available_mvm; + + wire[`NUM_TILES*`NUM_LDPES-1:0] mrf_we_for_dram; + wire [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram; + wire [`NUM_TILES*`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram; + + MVU mvm_unit ( + .clk(clk), + .start(start_tile_with_single_cyc_latency), + .reset(reset_tile_with_single_cyc_latency), + + .vrf_wr_addr(vrf_addr_wr), + .vrf_read_addr(vrf_addr_read), + .vec(vrf_in_data[`VRF_DWIDTH-1:0]), + .vrf_data_out_tile_0(vrf_mvu_out_0), //WITH TAG + .vrf_wr_enable_tile_0(vrf_mvu_wr_enable_0), //WITH TAG + .vrf_readn_enable_tile_0(vrf_mvu_readn_enable_0), //WITH TAG + .vrf_data_out_tile_1(vrf_mvu_out_1), //WITH TAG + .vrf_wr_enable_tile_1(vrf_mvu_wr_enable_1), //WITH TAG + .vrf_readn_enable_tile_1(vrf_mvu_readn_enable_1), //WITH TAG + .vrf_data_out_tile_2(vrf_mvu_out_2), //WITH TAG + .vrf_wr_enable_tile_2(vrf_mvu_wr_enable_2), //WITH TAG + .vrf_readn_enable_tile_2(vrf_mvu_readn_enable_2), //WITH TAG + .vrf_data_out_tile_3(vrf_mvu_out_3), //WITH TAG + .vrf_wr_enable_tile_3(vrf_mvu_wr_enable_3), //WITH TAG + .vrf_readn_enable_tile_3(vrf_mvu_readn_enable_3), //WITH TAG + .vrf_data_out_tile_4(vrf_mvu_out_4), //WITH TAG + .vrf_wr_enable_tile_4(vrf_mvu_wr_enable_4), //WITH TAG + .vrf_readn_enable_tile_4(vrf_mvu_readn_enable_4), //WITH TAG + .vrf_data_out_tile_5(vrf_mvu_out_5), //WITH TAG + .vrf_wr_enable_tile_5(vrf_mvu_wr_enable_5), //WITH TAG + .vrf_readn_enable_tile_5(vrf_mvu_readn_enable_5), //WITH TAG + .vrf_data_out_tile_6(vrf_mvu_out_6), //WITH TAG + .vrf_wr_enable_tile_6(vrf_mvu_wr_enable_6), //WITH TAG + .vrf_readn_enable_tile_6(vrf_mvu_readn_enable_6), //WITH TAG + .vrf_data_out_tile_7(vrf_mvu_out_7), //WITH TAG + .vrf_wr_enable_tile_7(vrf_mvu_wr_enable_7), //WITH TAG + .vrf_readn_enable_tile_7(vrf_mvu_readn_enable_7), //WITH TAG + + .mrf_in(mrf_in_data), + .mrf_we(mrf_we), //WITH TAG + .mrf_addr(mrf_addr_wr), + + .mrf_we_for_dram(mrf_we_for_dram), + .mrf_addr_for_dram(mrf_addr_for_dram), + .mrf_outa_to_dram(mrf_outa_to_dram), + + .out_data_available(out_data_available_mvm), + .mvm_result(result_mvm) //WITH TAG + ); + + assign done_mvm = out_data_available_mvm; + + reg[3:0] num_cycles_mvm; + + + //******************************************************************************* + + wire in_data_available_mfu_0; + reg reset_mfu_0_with_single_cyc_latency; + wire out_data_available_mfu_0; + wire done_mfu_0; + + wire in_data_available_mfu_1; + reg reset_mfu_1_with_single_cyc_latency; + wire out_data_available_mfu_1; + wire done_mfu_1; + + wire[1:0] activation; + wire[1:0] operation; + + //MFU VRF WIRES **************************************************************** + //wire[`VRF_AWIDTH-1:0] vrf_mfu_addr_read_add_0; + + //MFU - STAGE 0 VRF SIGNALS + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_add_0; + wire vrf_mfu_readn_enable_add_0; + wire vrf_mfu_wr_enable_add_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_add_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_add_0; + + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_mul_0; + wire vrf_mfu_readn_enable_mul_0; + wire vrf_mfu_wr_enable_mul_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_mul_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_mul_0; + + //wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_add_1; + + //MFU - STAGE 1 VRF SIGNALS + + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_add_1; + wire vrf_mfu_readn_enable_add_1; + wire vrf_mfu_wr_enable_add_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_add_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_add_1; + + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_mul_1; + wire vrf_mfu_readn_enable_mul_1; + wire vrf_mfu_wr_enable_mul_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_mul_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_mul_1; + + wire[`TARGET_OP_WIDTH-1:0] dstn_id; + wire[`NUM_LDPES*`OUT_DWIDTH-1:0] output_mvu_stage; + //************************************************************ + + assign output_mvu_stage = result_mvm; + + //************** INTER MFU MVU DATAPATH SIGNALS ************************************************* + reg[`ORF_DWIDTH-1:0] output_mvu_stage_buffer; + reg[`ORF_DWIDTH-1:0] output_mfu_stage_0_buffer; + + wire[`ORF_DWIDTH-1:0] primary_in_data_mfu_stage_0; + wire[`ORF_DWIDTH-1:0] primary_in_data_mfu_stage_1; + + + wire[`NUM_LDPES*`OUT_DWIDTH-1:0] output_mfu_stage_0; + wire[`NUM_LDPES*`OUT_DWIDTH-1:0] output_mfu_stage_1; + + always@(posedge clk) begin + if((dstn_id==`MFU_0_DSTN_ID) && done_mvm==1'b1) begin + output_mvu_stage_buffer <= output_mvu_stage; + end + end + + //CHECK THIS LOGIC CAREFULLY ***************************************************************** + always@(posedge clk) begin //FIRST BYPASS MUXING + //$display("%h", vrf_mvu_wr_addr_0); + if((dstn_id==`MFU_1_DSTN_ID) && (done_mfu_0 || done_mvm)) begin + output_mfu_stage_0_buffer <= (done_mfu_0) ? output_mfu_stage_0 : output_mvu_stage; + end + end + + assign output_final_stage = ((dstn_id!=`MFU_0_DSTN_ID) && (dstn_id!=`MFU_1_DSTN_ID)) ? + (done_mfu_1 ? output_mfu_stage_1 : //SECOND BYPASS MUXING + (done_mfu_0 ? output_mfu_stage_0 : + (done_mvm ? output_mvu_stage : 'd0))) : 'd0; + + //******************************************************************************************** + + + //****************************************************************************************** + wire[`ORF_DWIDTH-1:0] vrf_muxed_in_data_fake; + //************* MUXED MVU-MFU VRF ********************************************************** + + wire[`ORF_AWIDTH-1:0] vrf_muxed_wr_addr_dram; + wire[`ORF_DWIDTH-1:0] vrf_muxed_in_data; + wire vrf_muxed_wr_enable_dram; + wire vrf_muxed_readn_enable; + + wire[`ORF_AWIDTH-1:0] vrf_muxed_read_addr; + wire[`ORF_DWIDTH-1:0] vrf_muxed_out_data_dram; + wire[`ORF_DWIDTH-1:0] vrf_muxed_out_data; + + + VRF #(.VRF_DWIDTH(`ORF_DWIDTH),.VRF_AWIDTH(`ORF_AWIDTH)) vrf_muxed ( + .clk(clk), + + .addra(vrf_muxed_wr_addr_dram), + .ina(vrf_in_data[`ORF_DWIDTH-1:0]), + .wea(vrf_muxed_wr_enable_dram), + .outa(vrf_muxed_out_data_dram), + + .addrb(vrf_muxed_read_addr), + .inb(vrf_muxed_in_data_fake), + .web(vrf_muxed_readn_enable), + .outb(vrf_muxed_out_data) + ); + + wire mvu_or_vrf_mux_select; + assign primary_in_data_mfu_stage_0 = (mvu_or_vrf_mux_select) ? vrf_muxed_out_data : output_mvu_stage_buffer; + + assign primary_in_data_mfu_stage_1 = output_mfu_stage_0_buffer; + + //********************************************************************************************* + + //*********************************CONTROLLER FOR NPU***************************************** + controller controller_for_npu( + .clk(clk), + .reset_npu(reset_npu), + .instruction(instruction), + .get_instr(get_instr), + .get_instr_addr(get_instr_addr), + + .input_data_from_dram(input_data_DRAM), + .dram_addr_wr(dram_addr), + .dram_write_enable(dram_write_enable), + .output_data_to_dram(output_data_DRAM), + + .output_final_stage(output_final_stage), + + .start_mfu_0(start_mfu_0_signal), + .start_mfu_1(start_mfu_1_signal), + .start_mv_mul(start_mv_mul_signal), + .in_data_available_mfu_0(in_data_available_mfu_0), + .in_data_available_mfu_1(in_data_available_mfu_1), + + .activation(activation), + .operation(operation), + + .vrf_addr_read(vrf_addr_read), + .vrf_addr_wr(vrf_addr_wr), + + .vrf_out_data_mvu_0(vrf_mvu_out_0), //MVU TILE VRF + .vrf_readn_enable_mvu_0(vrf_mvu_readn_enable_0), + .vrf_wr_enable_mvu_0(vrf_mvu_wr_enable_0), + .vrf_out_data_mvu_1(vrf_mvu_out_1), //MVU TILE VRF + .vrf_readn_enable_mvu_1(vrf_mvu_readn_enable_1), + .vrf_wr_enable_mvu_1(vrf_mvu_wr_enable_1), + .vrf_out_data_mvu_2(vrf_mvu_out_2), //MVU TILE VRF + .vrf_readn_enable_mvu_2(vrf_mvu_readn_enable_2), + .vrf_wr_enable_mvu_2(vrf_mvu_wr_enable_2), + .vrf_out_data_mvu_3(vrf_mvu_out_3), //MVU TILE VRF + .vrf_readn_enable_mvu_3(vrf_mvu_readn_enable_3), + .vrf_wr_enable_mvu_3(vrf_mvu_wr_enable_3), + .vrf_out_data_mvu_4(vrf_mvu_out_4), //MVU TILE VRF + .vrf_readn_enable_mvu_4(vrf_mvu_readn_enable_4), + .vrf_wr_enable_mvu_4(vrf_mvu_wr_enable_4), + .vrf_out_data_mvu_5(vrf_mvu_out_5), //MVU TILE VRF + .vrf_readn_enable_mvu_5(vrf_mvu_readn_enable_5), + .vrf_wr_enable_mvu_5(vrf_mvu_wr_enable_5), + .vrf_out_data_mvu_6(vrf_mvu_out_6), //MVU TILE VRF + .vrf_readn_enable_mvu_6(vrf_mvu_readn_enable_6), + .vrf_wr_enable_mvu_6(vrf_mvu_wr_enable_6), + .vrf_out_data_mvu_7(vrf_mvu_out_7), //MVU TILE VRF + .vrf_readn_enable_mvu_7(vrf_mvu_readn_enable_7), + .vrf_wr_enable_mvu_7(vrf_mvu_wr_enable_7), + + .done_mvm(done_mvm), + .done_mfu_0(done_mfu_0), + .done_mfu_1(done_mfu_1), + //CHANGE INDEXING FOR VRFs-------------------------------------------- + + .vrf_out_data_mfu_add_0(vrf_mfu_out_data_add_0), + .vrf_readn_enable_mfu_add_0(vrf_mfu_readn_enable_add_0), + .vrf_wr_enable_mfu_add_0(vrf_mfu_wr_enable_add_0), //MFU VRF - ADD -0 + .vrf_addr_read_mfu_add_0(vrf_mfu_addr_read_add_0), + .vrf_addr_wr_mfu_add_0(vrf_mfu_addr_wr_add_0), + + + .vrf_out_data_mfu_mul_0(vrf_mfu_out_data_mul_0), //MFU VRF - MUL -0 + .vrf_readn_enable_mfu_mul_0(vrf_mfu_readn_enable_mul_0), + .vrf_wr_enable_mfu_mul_0(vrf_mfu_wr_enable_mul_0), + .vrf_addr_read_mfu_mul_0(vrf_mfu_addr_read_mul_0), + .vrf_addr_wr_mfu_mul_0(vrf_mfu_addr_wr_mul_0), + + .vrf_out_data_mfu_add_1(vrf_mfu_out_data_add_1), + .vrf_readn_enable_mfu_add_1(vrf_mfu_readn_enable_add_1), + .vrf_wr_enable_mfu_add_1(vrf_mfu_wr_enable_add_1), //MFU VRF - ADD - 1 + .vrf_addr_read_mfu_add_1(vrf_mfu_addr_read_add_1), + .vrf_addr_wr_mfu_add_1(vrf_mfu_addr_wr_add_1), + + + .vrf_out_data_mfu_mul_1(vrf_mfu_out_data_mul_1), //MFU VRF - MUL - 1 + .vrf_readn_enable_mfu_mul_1(vrf_mfu_readn_enable_mul_1), + .vrf_wr_enable_mfu_mul_1(vrf_mfu_wr_enable_mul_1), + .vrf_addr_read_mfu_mul_1(vrf_mfu_addr_read_mul_1), + .vrf_addr_wr_mfu_mul_1(vrf_mfu_addr_wr_mul_1), + + //MUXED VRF--------------------------------------- + .vrf_muxed_wr_addr_dram(vrf_muxed_wr_addr_dram), + .vrf_muxed_read_addr(vrf_muxed_read_addr), + .vrf_muxed_out_data_dram(vrf_muxed_out_data_dram), + .vrf_muxed_wr_enable_dram(vrf_muxed_wr_enable_dram), + .vrf_muxed_readn_enable(vrf_muxed_readn_enable), + //---------------------------------------------- + + .mvu_or_vrf_mux_select(mvu_or_vrf_mux_select), + .vrf_in_data(vrf_in_data), //common + + //----------------------------------------------------------------- + + .mrf_addr_wr(mrf_addr_wr), + .mrf_wr_enable(mrf_we), + .mrf_in_data(mrf_in_data), + + .mrf_we_for_dram(mrf_we_for_dram), + .mrf_addr_for_dram(mrf_addr_for_dram), + .mrf_outa_to_dram(mrf_outa_to_dram), + + //.orf_addr_increment(orf_addr_increment), + + .dstn_id(dstn_id) + ); + //*************************************************************************** + + //DELAYS START SIGNALS OF MVU TILE BY ONE CYCLE TO AVOID HIGH FANOUT AND ARITHEMETIC OF DONT CARES *********** + always@(posedge clk) begin + if(start_mv_mul_signal==1'b1) begin + start_tile_with_single_cyc_latency<={`NUM_LDPES{1'b1}}; + reset_tile_with_single_cyc_latency<={`NUM_LDPES{1'b0}}; + end + else begin + start_tile_with_single_cyc_latency<={`NUM_LDPES{1'b0}}; + reset_tile_with_single_cyc_latency<={`NUM_LDPES{1'b1}}; + end + end + + always@(*) begin + if(start_mfu_0_signal==1'b1) begin + reset_mfu_0_with_single_cyc_latency<=1'b0; + end + else begin + reset_mfu_0_with_single_cyc_latency<=1'b1; + end + end + + always@(*) begin + if(start_mfu_1_signal==1'b1) begin + reset_mfu_1_with_single_cyc_latency<=1'b0; + end + else begin + reset_mfu_1_with_single_cyc_latency<=1'b1; + end + end + + + //********************************************************************************************* + wire out_data_available_0; + //assign out_data_available_0 = done_mfu_0; + MFU mfu_stage_0( + .activation_type(activation), + .operation(operation), + .in_data_available(in_data_available_mfu_0), + + .vrf_addr_read_add(vrf_mfu_addr_read_add_0), + .vrf_addr_wr_add(vrf_mfu_addr_wr_add_0), + .vrf_readn_enable_add(vrf_mfu_readn_enable_add_0), + .vrf_wr_enable_add(vrf_mfu_wr_enable_add_0), + + .vrf_addr_read_mul(vrf_mfu_addr_read_mul_1), + .vrf_addr_wr_mul(vrf_mfu_addr_wr_mul_1), + .vrf_readn_enable_mul(vrf_mfu_readn_enable_mul_0), + .vrf_wr_enable_mul(vrf_mfu_wr_enable_mul_0), + + .primary_inp(primary_in_data_mfu_stage_0), + .secondary_inp(vrf_in_data[`ORF_DWIDTH-1:0]), + .out_data(output_mfu_stage_0), + .out_data_available(out_data_available_0), + .done(done_mfu_0), + .clk(clk), + + //VRF OUT SIGNALS + .out_vrf_add(vrf_mfu_out_data_add_0), + .out_vrf_mul(vrf_mfu_out_data_mul_0), + + .reset(reset_mfu_0_with_single_cyc_latency) + ); + + //************************************************************************* + //MFU STAGE - 2 + wire out_data_available_1; + //assign out_data_available_1 = done_mfu_1; + + MFU mfu_stage_1( + .activation_type(activation), + .operation(operation), + .in_data_available(in_data_available_mfu_1), + + //VRF IO SIGNALS FOR ELTWISE-ADD + .vrf_addr_read_add(vrf_mfu_addr_read_add_1), + .vrf_addr_wr_add(vrf_mfu_addr_wr_add_1), + .vrf_readn_enable_add(vrf_mfu_readn_enable_add_1), + .vrf_wr_enable_add(vrf_mfu_wr_enable_add_1), + + .vrf_addr_read_mul(vrf_mfu_addr_read_mul_1), + .vrf_addr_wr_mul(vrf_mfu_addr_wr_mul_1), + .vrf_readn_enable_mul(vrf_mfu_readn_enable_mul_1), + .vrf_wr_enable_mul(vrf_mfu_wr_enable_mul_1), + + //VRF IO SIGNALS FOR ELTWISE-MUL + .primary_inp(primary_in_data_mfu_stage_1), + .secondary_inp(vrf_in_data[`ORF_DWIDTH-1:0]), + .out_data(output_mfu_stage_1), + + .out_data_available(out_data_available_mfu_1), + .done(done_mfu_1), + .clk(clk), + + //VRF OUT SIGNAL + .out_vrf_add(vrf_mfu_out_data_add_1), + .out_vrf_mul(vrf_mfu_out_data_mul_1), + + .reset(reset_mfu_1_with_single_cyc_latency) + ); + + //************************************************************************* + + //************BYPASS MUXING LOGIC ***************************************** + + +endmodule +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM controller.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + + + +module controller( + + input clk, + input reset_npu, + input done_mvm, + input done_mfu_0, + input done_mfu_1, + + + input[`INSTR_WIDTH-1:0] instruction, + output reg get_instr, + output reg[`INSTR_MEM_AWIDTH-1:0] get_instr_addr, + + input[`DRAM_DWIDTH-1:0] input_data_from_dram, + input[`ORF_DWIDTH-1:0] output_final_stage, + output reg[`DRAM_AWIDTH-1:0] dram_addr_wr, + output reg dram_write_enable, + output reg [`DRAM_DWIDTH-1:0] output_data_to_dram, + + //output reg start_mvu, + output reg start_mv_mul, + output reg start_mfu_0, + output reg start_mfu_1, + //output reg reset_mvu, + output reg in_data_available_mfu_0, + output reg in_data_available_mfu_1, + + output reg[1:0] activation, + output reg[1:0] operation, + + //FOR MVU IO + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_0, + output reg vrf_readn_enable_mvu_0, + output reg vrf_wr_enable_mvu_0, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_1, + output reg vrf_readn_enable_mvu_1, + output reg vrf_wr_enable_mvu_1, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_2, + output reg vrf_readn_enable_mvu_2, + output reg vrf_wr_enable_mvu_2, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_3, + output reg vrf_readn_enable_mvu_3, + output reg vrf_wr_enable_mvu_3, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_4, + output reg vrf_readn_enable_mvu_4, + output reg vrf_wr_enable_mvu_4, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_5, + output reg vrf_readn_enable_mvu_5, + output reg vrf_wr_enable_mvu_5, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_6, + output reg vrf_readn_enable_mvu_6, + output reg vrf_wr_enable_mvu_6, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_7, + output reg vrf_readn_enable_mvu_7, + output reg vrf_wr_enable_mvu_7, + + + output reg[`VRF_AWIDTH-1:0] vrf_addr_read, + output reg[`VRF_AWIDTH-1:0] vrf_addr_wr, //********************* + + //FOR MFU STAGE -0 + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_add_0, + output reg vrf_readn_enable_mfu_add_0, + output reg vrf_wr_enable_mfu_add_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_add_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_add_0, + + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_mul_0, + output reg vrf_readn_enable_mfu_mul_0, + output reg vrf_wr_enable_mfu_mul_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_mul_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_mul_0, + // + + //FOR MFU STAGE -1 + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_add_1, + output reg vrf_readn_enable_mfu_add_1, + output reg vrf_wr_enable_mfu_add_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_add_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_add_1, + + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_mul_1, + output reg vrf_readn_enable_mfu_mul_1, + output reg vrf_wr_enable_mfu_mul_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_mul_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_mul_1, + + //VRF MUXED + input[`ORF_DWIDTH-1:0] vrf_muxed_out_data_dram, + output reg[`ORF_AWIDTH-1:0] vrf_muxed_wr_addr_dram, + output reg[`ORF_AWIDTH-1:0] vrf_muxed_read_addr, + output reg vrf_muxed_wr_enable_dram, + output reg vrf_muxed_readn_enable, + // + + output reg[`MAX_VRF_DWIDTH-1:0] vrf_in_data, + + output mvu_or_vrf_mux_select, + + //MRF IO PORTS + output reg[`MRF_AWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_addr_wr, + output reg[`NUM_LDPES*`NUM_TILES-1:0] mrf_wr_enable, //NOTE: LOG(NUM_LDPES) = TARGET_OP_WIDTH + output reg[`MRF_DWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_in_data, + + output reg[`NUM_TILES*`NUM_LDPES-1:0] mrf_we_for_dram, + output reg [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram, + input [`NUM_TILES*`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram, + // + + //BYPASS SIGNALS + output[`TARGET_OP_WIDTH-1:0] dstn_id +); + + wire[`OPCODE_WIDTH-1:0] opcode; + wire[`VRF_AWIDTH-1:0] op1_address; + wire[`VRF_AWIDTH-1:0] op2_address; + wire[`VRF_AWIDTH-1:0] dstn_address; + wire[`TARGET_OP_WIDTH-1:0] src1_id; + //wire[`TARGET_OP_WIDTH-1:0] dstn_id; + + reg[1:0] state; + + //NOTE - CORRECT NAMING FOR OPERANDS AND EXTRACTION SCHEME FOR YOUR PARTS OF INSTRUCTION + assign op1_address = instruction[3*`VRF_AWIDTH+(`TARGET_OP_WIDTH)-1:(2*`VRF_AWIDTH) +(`TARGET_OP_WIDTH)]; + assign op2_address = instruction[2*`VRF_AWIDTH+`TARGET_OP_WIDTH-1:`VRF_AWIDTH+`TARGET_OP_WIDTH]; + assign dstn_address = instruction[`VRF_AWIDTH-1:0]; + assign opcode = instruction[`INSTR_WIDTH-1:`INSTR_WIDTH-`OPCODE_WIDTH]; + assign src1_id = instruction[3*`VRF_AWIDTH+2*`TARGET_OP_WIDTH-1:3*`VRF_AWIDTH+`TARGET_OP_WIDTH]; //or can be called mem_id + assign dstn_id = instruction[`VRF_AWIDTH+`TARGET_OP_WIDTH-1:`VRF_AWIDTH];//LSB for dram_write bypass + + assign mvu_or_vrf_mux_select = (op2_address!={`VRF_AWIDTH{1'b0}}); //UNUSED BIT FOR MFU OPERATIONS + + + //TODO - MAKE THIS SEQUENTIAL LOGIC - DONE + always@(posedge clk) begin + + if(reset_npu == 1'b1) begin + //reset_mvu<=1'b1; + //start_mvu<=1'b0; + get_instr<=1'bX; + + get_instr_addr<=0; + + start_mv_mul <= 1'b0; + + in_data_available_mfu_0 <= 1'b0; + start_mfu_0 <= 1'b0; + + in_data_available_mfu_1 <= 1'b0; + start_mfu_1 <= 1'b0; + dram_write_enable <= 1'b0; + mrf_wr_enable<=1'b0; + + + vrf_wr_enable_mvu_0<=1'b0; + vrf_readn_enable_mvu_0 <= 1'b0; + + + vrf_wr_enable_mvu_1<=1'b0; + vrf_readn_enable_mvu_1 <= 1'b0; + + + vrf_wr_enable_mvu_2<=1'b0; + vrf_readn_enable_mvu_2 <= 1'b0; + + + vrf_wr_enable_mvu_3<=1'b0; + vrf_readn_enable_mvu_3 <= 1'b0; + + + vrf_wr_enable_mvu_4<=1'b0; + vrf_readn_enable_mvu_4 <= 1'b0; + + + vrf_wr_enable_mvu_5<=1'b0; + vrf_readn_enable_mvu_5 <= 1'b0; + + + vrf_wr_enable_mvu_6<=1'b0; + vrf_readn_enable_mvu_6 <= 1'b0; + + + vrf_wr_enable_mvu_7<=1'b0; + vrf_readn_enable_mvu_7 <= 1'b0; + + + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + + dram_addr_wr<=10'd0; + vrf_addr_wr <= 10'd0; + //vrf_addr_wr_mvu_1 <= 0; + vrf_addr_wr_mfu_add_0 <= 10'd0; + vrf_addr_wr_mfu_mul_0 <= 10'd0; + vrf_addr_wr_mfu_add_1 <= 10'd0; + vrf_addr_wr_mfu_mul_1 <= 10'd0; + + vrf_addr_read <= 10'd0; + //vrf_addr_read_mvu_1 <= 0; + vrf_addr_read_mfu_add_0 <= 10'd0; + vrf_addr_read_mfu_mul_0 <= 10'd0; + vrf_addr_read_mfu_add_1 <= 10'd0; + vrf_addr_read_mfu_mul_1 <= 10'd0; + + + //vrf_muxed_wr_addr_dram <= 0; + //vrf_muxed_read_addr <= 0; + vrf_muxed_wr_enable_dram <= 1'b0; + vrf_muxed_readn_enable <= 1'b0; + + // orf_addr_increment<=1'b0; + + mrf_addr_wr <= 10'd0; + + state <= 0; + end + else begin + if(state==0) begin //FETCH + get_instr <= 1'b0; + state <= 1; + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable <= 1'b0; + mrf_wr_enable <= 0; + end + else if(state==1) begin //DECODE + case(opcode) + `V_WR: begin + state <= 2; + get_instr<=0; + //get_instr_addr<=get_instr_addr+1'b1; + case(src1_id) + `VRF_0: begin vrf_wr_enable_mvu_0 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_1: begin vrf_wr_enable_mvu_1 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_2: begin vrf_wr_enable_mvu_2 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_3: begin vrf_wr_enable_mvu_3 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_4: begin vrf_wr_enable_mvu_4 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_5: begin vrf_wr_enable_mvu_5 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_6: begin vrf_wr_enable_mvu_6 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_7: begin vrf_wr_enable_mvu_7 <= 1'b0; + vrf_addr_wr <= op1_address; + end + + `VRF_8: begin vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_addr_wr_mfu_add_0 <= op1_address; + end + + `VRF_9: begin vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_addr_wr_mfu_mul_0 <= op1_address; + end + + `VRF_10: begin vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_addr_wr_mfu_add_1 <= op1_address; + end + + `VRF_11: begin + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_addr_wr_mfu_mul_1 <= op1_address; + end + + `VRF_MUXED: begin + vrf_muxed_wr_enable_dram <= 1'b0; + vrf_muxed_wr_addr_dram <= op1_address; + end + + default: begin + vrf_wr_enable_mvu_0 <= 1'bX; + output_data_to_dram <= 'd0; + end + + endcase + + dram_addr_wr <= dstn_address; + dram_write_enable <= 1'b1; + end + `M_WR: begin + state <= 2; + get_instr<=0; + + case(src1_id) + `MRF_0: begin mrf_we_for_dram[0] <= 1'b0; + mrf_addr_for_dram[1*`MRF_AWIDTH-1:0*`MRF_AWIDTH] <= op1_address; + end + `MRF_1: begin mrf_we_for_dram[1] <= 1'b0; + mrf_addr_for_dram[2*`MRF_AWIDTH-1:1*`MRF_AWIDTH] <= op1_address; + end + `MRF_2: begin mrf_we_for_dram[2] <= 1'b0; + mrf_addr_for_dram[3*`MRF_AWIDTH-1:2*`MRF_AWIDTH] <= op1_address; + end + `MRF_3: begin mrf_we_for_dram[3] <= 1'b0; + mrf_addr_for_dram[4*`MRF_AWIDTH-1:3*`MRF_AWIDTH] <= op1_address; + end + `MRF_4: begin mrf_we_for_dram[4] <= 1'b0; + mrf_addr_for_dram[5*`MRF_AWIDTH-1:4*`MRF_AWIDTH] <= op1_address; + end + `MRF_5: begin mrf_we_for_dram[5] <= 1'b0; + mrf_addr_for_dram[6*`MRF_AWIDTH-1:5*`MRF_AWIDTH] <= op1_address; + end + `MRF_6: begin mrf_we_for_dram[6] <= 1'b0; + mrf_addr_for_dram[7*`MRF_AWIDTH-1:6*`MRF_AWIDTH] <= op1_address; + end + `MRF_7: begin mrf_we_for_dram[7] <= 1'b0; + mrf_addr_for_dram[8*`MRF_AWIDTH-1:7*`MRF_AWIDTH] <= op1_address; + end + `MRF_8: begin mrf_we_for_dram[8] <= 1'b0; + mrf_addr_for_dram[9*`MRF_AWIDTH-1:8*`MRF_AWIDTH] <= op1_address; + end + `MRF_9: begin mrf_we_for_dram[9] <= 1'b0; + mrf_addr_for_dram[10*`MRF_AWIDTH-1:9*`MRF_AWIDTH] <= op1_address; + end + `MRF_10: begin mrf_we_for_dram[10] <= 1'b0; + mrf_addr_for_dram[11*`MRF_AWIDTH-1:10*`MRF_AWIDTH] <= op1_address; + end + `MRF_11: begin mrf_we_for_dram[11] <= 1'b0; + mrf_addr_for_dram[12*`MRF_AWIDTH-1:11*`MRF_AWIDTH] <= op1_address; + end + `MRF_12: begin mrf_we_for_dram[12] <= 1'b0; + mrf_addr_for_dram[13*`MRF_AWIDTH-1:12*`MRF_AWIDTH] <= op1_address; + end + `MRF_13: begin mrf_we_for_dram[13] <= 1'b0; + mrf_addr_for_dram[14*`MRF_AWIDTH-1:13*`MRF_AWIDTH] <= op1_address; + end + `MRF_14: begin mrf_we_for_dram[14] <= 1'b0; + mrf_addr_for_dram[15*`MRF_AWIDTH-1:14*`MRF_AWIDTH] <= op1_address; + end + `MRF_15: begin mrf_we_for_dram[15] <= 1'b0; + mrf_addr_for_dram[16*`MRF_AWIDTH-1:15*`MRF_AWIDTH] <= op1_address; + end + `MRF_16: begin mrf_we_for_dram[16] <= 1'b0; + mrf_addr_for_dram[17*`MRF_AWIDTH-1:16*`MRF_AWIDTH] <= op1_address; + end + `MRF_17: begin mrf_we_for_dram[17] <= 1'b0; + mrf_addr_for_dram[18*`MRF_AWIDTH-1:17*`MRF_AWIDTH] <= op1_address; + end + `MRF_18: begin mrf_we_for_dram[18] <= 1'b0; + mrf_addr_for_dram[19*`MRF_AWIDTH-1:18*`MRF_AWIDTH] <= op1_address; + end + `MRF_19: begin mrf_we_for_dram[19] <= 1'b0; + mrf_addr_for_dram[20*`MRF_AWIDTH-1:19*`MRF_AWIDTH] <= op1_address; + end + `MRF_20: begin mrf_we_for_dram[20] <= 1'b0; + mrf_addr_for_dram[21*`MRF_AWIDTH-1:20*`MRF_AWIDTH] <= op1_address; + end + `MRF_21: begin mrf_we_for_dram[21] <= 1'b0; + mrf_addr_for_dram[22*`MRF_AWIDTH-1:21*`MRF_AWIDTH] <= op1_address; + end + `MRF_22: begin mrf_we_for_dram[22] <= 1'b0; + mrf_addr_for_dram[23*`MRF_AWIDTH-1:22*`MRF_AWIDTH] <= op1_address; + end + `MRF_23: begin mrf_we_for_dram[23] <= 1'b0; + mrf_addr_for_dram[24*`MRF_AWIDTH-1:23*`MRF_AWIDTH] <= op1_address; + end + `MRF_24: begin mrf_we_for_dram[24] <= 1'b0; + mrf_addr_for_dram[25*`MRF_AWIDTH-1:24*`MRF_AWIDTH] <= op1_address; + end + `MRF_25: begin mrf_we_for_dram[25] <= 1'b0; + mrf_addr_for_dram[26*`MRF_AWIDTH-1:25*`MRF_AWIDTH] <= op1_address; + end + `MRF_26: begin mrf_we_for_dram[26] <= 1'b0; + mrf_addr_for_dram[27*`MRF_AWIDTH-1:26*`MRF_AWIDTH] <= op1_address; + end + `MRF_27: begin mrf_we_for_dram[27] <= 1'b0; + mrf_addr_for_dram[28*`MRF_AWIDTH-1:27*`MRF_AWIDTH] <= op1_address; + end + `MRF_28: begin mrf_we_for_dram[28] <= 1'b0; + mrf_addr_for_dram[29*`MRF_AWIDTH-1:28*`MRF_AWIDTH] <= op1_address; + end + `MRF_29: begin mrf_we_for_dram[29] <= 1'b0; + mrf_addr_for_dram[30*`MRF_AWIDTH-1:29*`MRF_AWIDTH] <= op1_address; + end + `MRF_30: begin mrf_we_for_dram[30] <= 1'b0; + mrf_addr_for_dram[31*`MRF_AWIDTH-1:30*`MRF_AWIDTH] <= op1_address; + end + `MRF_31: begin mrf_we_for_dram[31] <= 1'b0; + mrf_addr_for_dram[32*`MRF_AWIDTH-1:31*`MRF_AWIDTH] <= op1_address; + end + default: begin mrf_we_for_dram <= 'd0; + mrf_addr_for_dram <= 'd0; + end + endcase + + dram_addr_wr <= dstn_address; + dram_write_enable <= 1'b1; + end + `V_RD: begin + state <= 2; + get_instr<=0; + dram_addr_wr <= op1_address; + dram_write_enable <= 1'b0; + + end + //CHANGE NAMING CONVENTION FOR WRITE AND READ TO STORE AND LOAD + //ADD COMMENTS FOR SRC AND DESTINATION + `M_RD: begin + state <= 2; + get_instr<=0; + dram_addr_wr <= op1_address; + dram_write_enable <= 1'b0; + end + `MV_MUL: begin + //op1_id is don't care for this instructions + + state <= 2; + get_instr<=1'b0; + start_mv_mul <= 1'b1; + mrf_addr_wr[(1*`MRF_AWIDTH)-1:0*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(2*`MRF_AWIDTH)-1:1*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(3*`MRF_AWIDTH)-1:2*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(4*`MRF_AWIDTH)-1:3*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(5*`MRF_AWIDTH)-1:4*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(6*`MRF_AWIDTH)-1:5*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(7*`MRF_AWIDTH)-1:6*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(8*`MRF_AWIDTH)-1:7*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(9*`MRF_AWIDTH)-1:8*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(10*`MRF_AWIDTH)-1:9*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(11*`MRF_AWIDTH)-1:10*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(12*`MRF_AWIDTH)-1:11*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(13*`MRF_AWIDTH)-1:12*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(14*`MRF_AWIDTH)-1:13*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(15*`MRF_AWIDTH)-1:14*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(16*`MRF_AWIDTH)-1:15*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(17*`MRF_AWIDTH)-1:16*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(18*`MRF_AWIDTH)-1:17*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(19*`MRF_AWIDTH)-1:18*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(20*`MRF_AWIDTH)-1:19*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(21*`MRF_AWIDTH)-1:20*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(22*`MRF_AWIDTH)-1:21*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(23*`MRF_AWIDTH)-1:22*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(24*`MRF_AWIDTH)-1:23*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(25*`MRF_AWIDTH)-1:24*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(26*`MRF_AWIDTH)-1:25*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(27*`MRF_AWIDTH)-1:26*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(28*`MRF_AWIDTH)-1:27*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(29*`MRF_AWIDTH)-1:28*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(30*`MRF_AWIDTH)-1:29*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(31*`MRF_AWIDTH)-1:30*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(32*`MRF_AWIDTH)-1:31*`MRF_AWIDTH] <= op1_address; + vrf_addr_read <= op2_address; + vrf_readn_enable_mvu_0 <= 1'b0; + vrf_readn_enable_mvu_1 <= 1'b0; + vrf_readn_enable_mvu_2 <= 1'b0; + vrf_readn_enable_mvu_3 <= 1'b0; + vrf_readn_enable_mvu_4 <= 1'b0; + vrf_readn_enable_mvu_5 <= 1'b0; + vrf_readn_enable_mvu_6 <= 1'b0; + vrf_readn_enable_mvu_7 <= 1'b0; + mrf_wr_enable <= 0; + end + `VV_ADD:begin + + //MFU_STAGE-0 DESIGNATED FOR ELTWISE ADD + state <= 2; + get_instr <= 1'b0; + operation <= `ELT_WISE_ADD; //NOTE - 2nd VRF INDEX IS FOR ADD UNITS ELT WISE + activation <= 0; + + case(src1_id) + + `VRF_8: begin + start_mfu_0 <= 1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + + in_data_available_mfu_0 <= 1'b1; + vrf_addr_read_mfu_add_0 <= op1_address; + vrf_readn_enable_mfu_add_0 <= 1'b0; + end + + + `VRF_10: begin + start_mfu_1 <= 1'b1; + in_data_available_mfu_1 <= 1'b1; + vrf_addr_read_mfu_add_1 <= op1_address; + vrf_readn_enable_mfu_add_1 <= 1'b0; + end + + + default: begin + start_mfu_0 <= 1'b0; + in_data_available_mfu_0 <= 1'b0; + vrf_addr_read_mfu_add_0 <= 10'd0; + vrf_readn_enable_mfu_add_0 <= 1'b0; + vrf_addr_read_mfu_add_1 <= 10'd0; + vrf_readn_enable_mfu_add_1 <= 1'b0; + end + + endcase + + end + `VV_SUB:begin + + //MFU_STAGE-0 DESIGNATED FOR ELTWISE ADD + state <= 2; + get_instr<=1'b0; + operation<=`ELT_WISE_ADD; //NOTE - 2nd VRF INDEX IS FOR ADD UNITS ELT WISE + + activation <= 1; + + case(src1_id) + + `VRF_8: begin + start_mfu_0 <= 1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + + in_data_available_mfu_0 <= 1'b1; + vrf_addr_read_mfu_add_0 <= op1_address; + vrf_readn_enable_mfu_add_0 <= 1'b0; + end + + + `VRF_10: begin + start_mfu_1 <= 1'b1; + in_data_available_mfu_1 <= 1'b1; + vrf_addr_read_mfu_add_1 <= op1_address; + vrf_readn_enable_mfu_add_1 <= 1'b0; + end + + + default: begin + start_mfu_0 <= 1'b0; + in_data_available_mfu_0 <= 1'b0; + vrf_addr_read_mfu_add_0 <= 10'd0; + vrf_readn_enable_mfu_add_0 <= 1'b0; + vrf_addr_read_mfu_add_1 <= 10'd0; + vrf_readn_enable_mfu_add_1 <= 1'b0; + end + + endcase + + end + `VV_MUL:begin + state <= 2; + get_instr<=1'b0; + + operation<=`ELT_WISE_MULTIPLY; //NOTE - 3RD VRF INDEX IS FOR ADD UNITS ELT WISE + case(src1_id) + + `VRF_9: begin + start_mfu_0 <= 1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + + in_data_available_mfu_0 <= 1'b1; + vrf_addr_read_mfu_mul_0 <= op1_address; + vrf_readn_enable_mfu_mul_0 <= 1'b0; + end + + `VRF_11: begin + start_mfu_1 <= 1'b1; + in_data_available_mfu_1 <= 1'b1; + vrf_addr_read_mfu_mul_1 <= op1_address; + vrf_readn_enable_mfu_mul_1 <= 1'b0; + end + + default: begin + start_mfu_0 <= 1'b0; + in_data_available_mfu_0 <= 1'b0; + vrf_addr_read_mfu_mul_0 <= 10'd0; + vrf_readn_enable_mfu_mul_0 <= 1'b0; + vrf_addr_read_mfu_mul_1 <= 10'd0; + vrf_readn_enable_mfu_mul_1 <= 1'b0; + end + + endcase + + end + `V_RELU:begin + + get_instr<=1'b0; + case(src1_id) + + `MFU_0: begin + start_mfu_0<=1'b1; + in_data_available_mfu_0<=1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + end + + `MFU_1: begin + start_mfu_1<=1'b1; + in_data_available_mfu_1<=1'b1; + end + + default: begin + start_mfu_0<=1'b0; + in_data_available_mfu_0<=1'b0; + end + + endcase + operation<=`ACTIVATION; + activation<=`RELU; + state <= 2; + + end + `V_SIGM:begin + + get_instr<=1'b0; + case(src1_id) + + `MFU_0: begin + start_mfu_0<=1'b1; + in_data_available_mfu_0<=1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + end + + `MFU_1: begin + start_mfu_1<=1'b1; + in_data_available_mfu_1<=1'b1; + end + + default: begin + start_mfu_0<=1'b0; + in_data_available_mfu_0<=1'b0; + end + + endcase + operation<=`ACTIVATION; + activation<=`SIGM; + state <= 2; + end + `V_TANH:begin + //dram_write_enable <= bypass_id[0]; + get_instr<=1'b0; + case(src1_id) + + `MFU_0: begin + start_mfu_0<=1'b1; + in_data_available_mfu_0<=1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + end + + `MFU_1: begin + start_mfu_1<=1'b1; + in_data_available_mfu_1<=1'b1; + end + + default: begin + start_mfu_0<=1'b0; + in_data_available_mfu_0<=1'b0; + end + + endcase + operation<=`ACTIVATION; + activation<=`TANH; + state <= 2; + + end + `END_CHAIN :begin + + start_mv_mul<=1'b0; + get_instr<=1'b0; + + in_data_available_mfu_0<=1'b0; + start_mfu_0<=1'b0; + + in_data_available_mfu_1<=1'b0; + start_mfu_1<=1'b0; + + mrf_wr_enable<=0; + + + vrf_wr_enable_mvu_0<='b0; + vrf_readn_enable_mvu_0 <= 'b0; + + + vrf_wr_enable_mvu_1<='b0; + vrf_readn_enable_mvu_1 <= 'b0; + + + vrf_wr_enable_mvu_2<='b0; + vrf_readn_enable_mvu_2 <= 'b0; + + + vrf_wr_enable_mvu_3<='b0; + vrf_readn_enable_mvu_3 <= 'b0; + + + vrf_wr_enable_mvu_4<='b0; + vrf_readn_enable_mvu_4 <= 'b0; + + + vrf_wr_enable_mvu_5<='b0; + vrf_readn_enable_mvu_5 <= 'b0; + + + vrf_wr_enable_mvu_6<='b0; + vrf_readn_enable_mvu_6 <= 'b0; + + + vrf_wr_enable_mvu_7<='b0; + vrf_readn_enable_mvu_7 <= 'b0; + + + vrf_wr_enable_mfu_add_0 <= 0; + vrf_wr_enable_mfu_mul_0 <= 0; + vrf_wr_enable_mfu_add_1 <= 0; + vrf_wr_enable_mfu_mul_1 <= 0; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_wr_addr_dram <= 1'b0; + + vrf_readn_enable_mfu_add_0 <= 0; + vrf_readn_enable_mfu_mul_0 <= 0; + vrf_readn_enable_mfu_add_1 <= 0; + vrf_readn_enable_mfu_mul_1 <= 0; + + //orf_addr_increment<=1'b0; + mrf_addr_wr <= 0; + dram_write_enable <= 1'b0; + state <= 1; + end + endcase + end + else begin //EXECUTE + + case(opcode) + `V_WR: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(src1_id) + + `VRF_0: begin + output_data_to_dram <= vrf_out_data_mvu_0; + end + `VRF_1: begin + output_data_to_dram <= vrf_out_data_mvu_1; + end + `VRF_2: begin + output_data_to_dram <= vrf_out_data_mvu_2; + end + `VRF_3: begin + output_data_to_dram <= vrf_out_data_mvu_3; + end + `VRF_4: begin + output_data_to_dram <= vrf_out_data_mvu_4; + end + `VRF_5: begin + output_data_to_dram <= vrf_out_data_mvu_5; + end + `VRF_6: begin + output_data_to_dram <= vrf_out_data_mvu_6; + end + `VRF_7: begin + output_data_to_dram <= vrf_out_data_mvu_7; + end + + `VRF_8: begin + output_data_to_dram <= vrf_out_data_mfu_add_0; + end + + `VRF_9: begin + output_data_to_dram <= vrf_out_data_mfu_mul_0; + end + + `VRF_10: begin + output_data_to_dram <= vrf_out_data_mfu_add_1; + end + + `VRF_11: begin + output_data_to_dram <= vrf_out_data_mfu_mul_1; + end + + `VRF_MUXED: begin + output_data_to_dram <= vrf_muxed_out_data_dram; + end + default: begin + output_data_to_dram <= 'd0; + end + endcase + + end + `M_WR: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(src1_id) + + `MRF_0: begin + output_data_to_dram <= mrf_outa_to_dram[1*`MRF_DWIDTH-1:0*`MRF_DWIDTH]; + end + `MRF_1: begin + output_data_to_dram <= mrf_outa_to_dram[2*`MRF_DWIDTH-1:1*`MRF_DWIDTH]; + end + `MRF_2: begin + output_data_to_dram <= mrf_outa_to_dram[3*`MRF_DWIDTH-1:2*`MRF_DWIDTH]; + end + `MRF_3: begin + output_data_to_dram <= mrf_outa_to_dram[4*`MRF_DWIDTH-1:3*`MRF_DWIDTH]; + end + `MRF_4: begin + output_data_to_dram <= mrf_outa_to_dram[5*`MRF_DWIDTH-1:4*`MRF_DWIDTH]; + end + `MRF_5: begin + output_data_to_dram <= mrf_outa_to_dram[6*`MRF_DWIDTH-1:5*`MRF_DWIDTH]; + end + `MRF_6: begin + output_data_to_dram <= mrf_outa_to_dram[7*`MRF_DWIDTH-1:6*`MRF_DWIDTH]; + end + `MRF_7: begin + output_data_to_dram <= mrf_outa_to_dram[8*`MRF_DWIDTH-1:7*`MRF_DWIDTH]; + end + `MRF_8: begin + output_data_to_dram <= mrf_outa_to_dram[9*`MRF_DWIDTH-1:8*`MRF_DWIDTH]; + end + `MRF_9: begin + output_data_to_dram <= mrf_outa_to_dram[10*`MRF_DWIDTH-1:9*`MRF_DWIDTH]; + end + `MRF_10: begin + output_data_to_dram <= mrf_outa_to_dram[11*`MRF_DWIDTH-1:10*`MRF_DWIDTH]; + end + `MRF_11: begin + output_data_to_dram <= mrf_outa_to_dram[12*`MRF_DWIDTH-1:11*`MRF_DWIDTH]; + end + `MRF_12: begin + output_data_to_dram <= mrf_outa_to_dram[13*`MRF_DWIDTH-1:12*`MRF_DWIDTH]; + end + `MRF_13: begin + output_data_to_dram <= mrf_outa_to_dram[14*`MRF_DWIDTH-1:13*`MRF_DWIDTH]; + end + `MRF_14: begin + output_data_to_dram <= mrf_outa_to_dram[15*`MRF_DWIDTH-1:14*`MRF_DWIDTH]; + end + `MRF_15: begin + output_data_to_dram <= mrf_outa_to_dram[16*`MRF_DWIDTH-1:15*`MRF_DWIDTH]; + end + `MRF_16: begin + output_data_to_dram <= mrf_outa_to_dram[17*`MRF_DWIDTH-1:16*`MRF_DWIDTH]; + end + `MRF_17: begin + output_data_to_dram <= mrf_outa_to_dram[18*`MRF_DWIDTH-1:17*`MRF_DWIDTH]; + end + `MRF_18: begin + output_data_to_dram <= mrf_outa_to_dram[19*`MRF_DWIDTH-1:18*`MRF_DWIDTH]; + end + `MRF_19: begin + output_data_to_dram <= mrf_outa_to_dram[20*`MRF_DWIDTH-1:19*`MRF_DWIDTH]; + end + `MRF_20: begin + output_data_to_dram <= mrf_outa_to_dram[21*`MRF_DWIDTH-1:20*`MRF_DWIDTH]; + end + `MRF_21: begin + output_data_to_dram <= mrf_outa_to_dram[22*`MRF_DWIDTH-1:21*`MRF_DWIDTH]; + end + `MRF_22: begin + output_data_to_dram <= mrf_outa_to_dram[23*`MRF_DWIDTH-1:22*`MRF_DWIDTH]; + end + `MRF_23: begin + output_data_to_dram <= mrf_outa_to_dram[24*`MRF_DWIDTH-1:23*`MRF_DWIDTH]; + end + `MRF_24: begin + output_data_to_dram <= mrf_outa_to_dram[25*`MRF_DWIDTH-1:24*`MRF_DWIDTH]; + end + `MRF_25: begin + output_data_to_dram <= mrf_outa_to_dram[26*`MRF_DWIDTH-1:25*`MRF_DWIDTH]; + end + `MRF_26: begin + output_data_to_dram <= mrf_outa_to_dram[27*`MRF_DWIDTH-1:26*`MRF_DWIDTH]; + end + `MRF_27: begin + output_data_to_dram <= mrf_outa_to_dram[28*`MRF_DWIDTH-1:27*`MRF_DWIDTH]; + end + `MRF_28: begin + output_data_to_dram <= mrf_outa_to_dram[29*`MRF_DWIDTH-1:28*`MRF_DWIDTH]; + end + `MRF_29: begin + output_data_to_dram <= mrf_outa_to_dram[30*`MRF_DWIDTH-1:29*`MRF_DWIDTH]; + end + `MRF_30: begin + output_data_to_dram <= mrf_outa_to_dram[31*`MRF_DWIDTH-1:30*`MRF_DWIDTH]; + end + `MRF_31: begin + output_data_to_dram <= mrf_outa_to_dram[32*`MRF_DWIDTH-1:31*`MRF_DWIDTH]; + end + default: begin + output_data_to_dram <= 'd0; + end + endcase + + end + `V_RD: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + vrf_in_data <= input_data_from_dram; + case(dstn_id) + `VRF_0: begin + vrf_wr_enable_mvu_0 <= 1'b1; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_1: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b1; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_2: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b1; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_3: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b1; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_4: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b1; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_5: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b1; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_6: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b1; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_7: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b1; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_8: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b1; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_add_0 <= dstn_address; + + end + + `VRF_9: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b1; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_mul_0 <= dstn_address; + + end + + `VRF_10: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b1; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_add_1 <= dstn_address; + end + + `VRF_11: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b1; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_mul_1 <= dstn_address; + end + + `VRF_MUXED: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b1; + + + vrf_muxed_wr_addr_dram <= dstn_address; + end + + default: begin + vrf_wr_enable_mvu_0 <= 1'bX; + vrf_wr_enable_mvu_1 <= 1'bX; + vrf_wr_enable_mvu_2 <= 1'bX; + vrf_wr_enable_mvu_3 <= 1'bX; + vrf_wr_enable_mvu_4 <= 1'bX; + vrf_wr_enable_mvu_5 <= 1'bX; + vrf_wr_enable_mvu_6 <= 1'bX; + vrf_wr_enable_mvu_7 <= 1'bX; + vrf_wr_enable_mfu_add_0 <= 1'bX; + vrf_wr_enable_mfu_mul_0 <= 1'bX; + vrf_wr_enable_mfu_add_1 <= 1'bX; + vrf_wr_enable_mfu_mul_1 <= 1'bX; + vrf_muxed_wr_enable_dram <= 1'bX; + + end + endcase +/* + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; +*/ + + end + `M_RD: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(dstn_id) + `MRF_0: begin + mrf_we_for_dram[0] <= 1; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[1*`MRF_DWIDTH-1:0*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[1*`MRF_AWIDTH-1:0*`MRF_AWIDTH] <= dstn_address; + end + `MRF_1: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 1; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[2*`MRF_DWIDTH-1:1*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[2*`MRF_AWIDTH-1:1*`MRF_AWIDTH] <= dstn_address; + end + `MRF_2: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 1; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[3*`MRF_DWIDTH-1:2*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[3*`MRF_AWIDTH-1:2*`MRF_AWIDTH] <= dstn_address; + end + `MRF_3: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 1; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[4*`MRF_DWIDTH-1:3*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[4*`MRF_AWIDTH-1:3*`MRF_AWIDTH] <= dstn_address; + end + `MRF_4: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 1; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[5*`MRF_DWIDTH-1:4*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[5*`MRF_AWIDTH-1:4*`MRF_AWIDTH] <= dstn_address; + end + `MRF_5: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 1; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[6*`MRF_DWIDTH-1:5*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[6*`MRF_AWIDTH-1:5*`MRF_AWIDTH] <= dstn_address; + end + `MRF_6: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 1; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[7*`MRF_DWIDTH-1:6*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[7*`MRF_AWIDTH-1:6*`MRF_AWIDTH] <= dstn_address; + end + `MRF_7: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 1; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[8*`MRF_DWIDTH-1:7*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[8*`MRF_AWIDTH-1:7*`MRF_AWIDTH] <= dstn_address; + end + `MRF_8: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 1; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[9*`MRF_DWIDTH-1:8*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[9*`MRF_AWIDTH-1:8*`MRF_AWIDTH] <= dstn_address; + end + `MRF_9: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 1; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[10*`MRF_DWIDTH-1:9*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[10*`MRF_AWIDTH-1:9*`MRF_AWIDTH] <= dstn_address; + end + `MRF_10: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 1; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[11*`MRF_DWIDTH-1:10*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[11*`MRF_AWIDTH-1:10*`MRF_AWIDTH] <= dstn_address; + end + `MRF_11: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 1; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[12*`MRF_DWIDTH-1:11*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[12*`MRF_AWIDTH-1:11*`MRF_AWIDTH] <= dstn_address; + end + `MRF_12: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 1; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[13*`MRF_DWIDTH-1:12*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[13*`MRF_AWIDTH-1:12*`MRF_AWIDTH] <= dstn_address; + end + `MRF_13: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 1; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[14*`MRF_DWIDTH-1:13*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[14*`MRF_AWIDTH-1:13*`MRF_AWIDTH] <= dstn_address; + end + `MRF_14: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 1; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[15*`MRF_DWIDTH-1:14*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[15*`MRF_AWIDTH-1:14*`MRF_AWIDTH] <= dstn_address; + end + `MRF_15: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 1; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[16*`MRF_DWIDTH-1:15*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[16*`MRF_AWIDTH-1:15*`MRF_AWIDTH] <= dstn_address; + end + `MRF_16: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 1; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[17*`MRF_DWIDTH-1:16*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[17*`MRF_AWIDTH-1:16*`MRF_AWIDTH] <= dstn_address; + end + `MRF_17: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 1; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[18*`MRF_DWIDTH-1:17*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[18*`MRF_AWIDTH-1:17*`MRF_AWIDTH] <= dstn_address; + end + `MRF_18: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 1; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[19*`MRF_DWIDTH-1:18*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[19*`MRF_AWIDTH-1:18*`MRF_AWIDTH] <= dstn_address; + end + `MRF_19: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 1; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[20*`MRF_DWIDTH-1:19*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[20*`MRF_AWIDTH-1:19*`MRF_AWIDTH] <= dstn_address; + end + `MRF_20: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 1; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[21*`MRF_DWIDTH-1:20*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[21*`MRF_AWIDTH-1:20*`MRF_AWIDTH] <= dstn_address; + end + `MRF_21: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 1; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[22*`MRF_DWIDTH-1:21*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[22*`MRF_AWIDTH-1:21*`MRF_AWIDTH] <= dstn_address; + end + `MRF_22: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 1; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[23*`MRF_DWIDTH-1:22*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[23*`MRF_AWIDTH-1:22*`MRF_AWIDTH] <= dstn_address; + end + `MRF_23: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 1; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[24*`MRF_DWIDTH-1:23*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[24*`MRF_AWIDTH-1:23*`MRF_AWIDTH] <= dstn_address; + end + `MRF_24: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 1; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[25*`MRF_DWIDTH-1:24*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[25*`MRF_AWIDTH-1:24*`MRF_AWIDTH] <= dstn_address; + end + `MRF_25: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 1; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[26*`MRF_DWIDTH-1:25*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[26*`MRF_AWIDTH-1:25*`MRF_AWIDTH] <= dstn_address; + end + `MRF_26: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 1; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[27*`MRF_DWIDTH-1:26*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[27*`MRF_AWIDTH-1:26*`MRF_AWIDTH] <= dstn_address; + end + `MRF_27: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 1; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[28*`MRF_DWIDTH-1:27*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[28*`MRF_AWIDTH-1:27*`MRF_AWIDTH] <= dstn_address; + end + `MRF_28: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 1; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[29*`MRF_DWIDTH-1:28*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[29*`MRF_AWIDTH-1:28*`MRF_AWIDTH] <= dstn_address; + end + `MRF_29: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 1; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_in_data[30*`MRF_DWIDTH-1:29*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[30*`MRF_AWIDTH-1:29*`MRF_AWIDTH] <= dstn_address; + end + `MRF_30: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 1; + mrf_we_for_dram[31] <= 0; + mrf_in_data[31*`MRF_DWIDTH-1:30*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[31*`MRF_AWIDTH-1:30*`MRF_AWIDTH] <= dstn_address; + end + `MRF_31: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 1; + mrf_in_data[32*`MRF_DWIDTH-1:31*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[32*`MRF_AWIDTH-1:31*`MRF_AWIDTH] <= dstn_address; + end + + default: begin + mrf_we_for_dram[0] <= 1'bX; + mrf_we_for_dram[1] <= 1'bX; + mrf_we_for_dram[2] <= 1'bX; + mrf_we_for_dram[3] <= 1'bX; + mrf_we_for_dram[4] <= 1'bX; + mrf_we_for_dram[5] <= 1'bX; + mrf_we_for_dram[6] <= 1'bX; + mrf_we_for_dram[7] <= 1'bX; + mrf_we_for_dram[8] <= 1'bX; + mrf_we_for_dram[9] <= 1'bX; + mrf_we_for_dram[10] <= 1'bX; + mrf_we_for_dram[11] <= 1'bX; + mrf_we_for_dram[12] <= 1'bX; + mrf_we_for_dram[13] <= 1'bX; + mrf_we_for_dram[14] <= 1'bX; + mrf_we_for_dram[15] <= 1'bX; + mrf_we_for_dram[16] <= 1'bX; + mrf_we_for_dram[17] <= 1'bX; + mrf_we_for_dram[18] <= 1'bX; + mrf_we_for_dram[19] <= 1'bX; + mrf_we_for_dram[20] <= 1'bX; + mrf_we_for_dram[21] <= 1'bX; + mrf_we_for_dram[22] <= 1'bX; + mrf_we_for_dram[23] <= 1'bX; + mrf_we_for_dram[24] <= 1'bX; + mrf_we_for_dram[25] <= 1'bX; + mrf_we_for_dram[26] <= 1'bX; + mrf_we_for_dram[27] <= 1'bX; + mrf_we_for_dram[28] <= 1'bX; + mrf_we_for_dram[29] <= 1'bX; + mrf_we_for_dram[30] <= 1'bX; + mrf_we_for_dram[31] <= 1'bX; + end + + endcase + end + default: begin + + if(done_mvm || done_mfu_0 || done_mfu_1) begin + start_mv_mul <= 0; + start_mfu_0 <= 0; + start_mfu_1 <= 0; + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(dstn_id) + `VRF_0: begin + vrf_wr_enable_mvu_0 <= 1'b1; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_1: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b1; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_2: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b1; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_3: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b1; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_4: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b1; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_5: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b1; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_6: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b1; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_7: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b1; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + + `VRF_8: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b1; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_add_0 <= dstn_address; + + end + + `VRF_9: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b1; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_mul_0 <= dstn_address; + + end + + `VRF_10: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b1; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_add_1 <= dstn_address; + end + + `VRF_11: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b1; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_mul_1 <= dstn_address; + end + + `VRF_MUXED: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b1; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_muxed_wr_addr_dram <= dstn_address; + end + + `DRAM_MEM_ID: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b1; + + output_data_to_dram <= output_final_stage; + + dram_addr_wr <= dstn_address; + end + + //MFU_OUT_STAGE IDS USED FOR MUXING + + default: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + end + endcase + end + end + endcase + end + end + end +endmodule +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM mvu.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + + +module MVU ( + input clk, + input[`NUM_LDPES-1:0] start, + input[`NUM_LDPES-1:0] reset, + + input [`VRF_AWIDTH-1:0] vrf_wr_addr, + input [`VRF_AWIDTH-1:0] vrf_read_addr, + input [`VRF_DWIDTH-1:0] vec, + + input vrf_wr_enable_tile_0, + input vrf_readn_enable_tile_0, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_0, + input vrf_wr_enable_tile_1, + input vrf_readn_enable_tile_1, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_1, + input vrf_wr_enable_tile_2, + input vrf_readn_enable_tile_2, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_2, + input vrf_wr_enable_tile_3, + input vrf_readn_enable_tile_3, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_3, + input vrf_wr_enable_tile_4, + input vrf_readn_enable_tile_4, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_4, + input vrf_wr_enable_tile_5, + input vrf_readn_enable_tile_5, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_5, + input vrf_wr_enable_tile_6, + input vrf_readn_enable_tile_6, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_6, + input vrf_wr_enable_tile_7, + input vrf_readn_enable_tile_7, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_7, + + input [`MRF_DWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_in, + input[`NUM_TILES*`NUM_LDPES-1:0] mrf_we, + input [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr, + + input [`NUM_TILES*`NUM_LDPES-1:0] mrf_we_for_dram, + input [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram, + output [`NUM_TILES*`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram, + + output [`ORF_DWIDTH-1:0] mvm_result, + output out_data_available +); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_0; + wire[`NUM_LDPES-1:0] out_data_available_mvu_tile_0; + + MVU_tile tile_0(.clk(clk), + .start(start), + .reset(reset), + .out_data_available(out_data_available_mvu_tile_0), //WITH TAG + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .vrf_data_out(vrf_data_out_tile_0), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_0), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_0), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .mrf_in(mrf_in[1*`MRF_DWIDTH*`NUM_LDPES-1:0*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[1*`NUM_LDPES-1:0*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[1*`NUM_LDPES*`MRF_AWIDTH-1:0*`NUM_LDPES*`MRF_AWIDTH]), + + .mrf_we_for_dram(mrf_we_for_dram[1*`NUM_LDPES-1:0*`NUM_LDPES]), + .mrf_addr_for_dram(mrf_addr_for_dram[1*`NUM_LDPES*`MRF_AWIDTH-1:0*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[1*`NUM_LDPES*`MRF_DWIDTH-1:0*`NUM_LDPES*`MRF_DWIDTH]), + + .result(result_mvm_0) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_1; + wire[`NUM_LDPES-1:0] out_data_available_mvu_tile_1; + + MVU_tile tile_1(.clk(clk), + .start(start), + .reset(reset), + .out_data_available(out_data_available_mvu_tile_1), //WITH TAG + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .vrf_data_out(vrf_data_out_tile_1), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_1), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_1), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .mrf_in(mrf_in[2*`MRF_DWIDTH*`NUM_LDPES-1:1*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[2*`NUM_LDPES-1:1*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[2*`NUM_LDPES*`MRF_AWIDTH-1:1*`NUM_LDPES*`MRF_AWIDTH]), + + .mrf_we_for_dram(mrf_we_for_dram[2*`NUM_LDPES-1:1*`NUM_LDPES]), + .mrf_addr_for_dram(mrf_addr_for_dram[2*`NUM_LDPES*`MRF_AWIDTH-1:1*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[2*`NUM_LDPES*`MRF_DWIDTH-1:1*`NUM_LDPES*`MRF_DWIDTH]), + + .result(result_mvm_1) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_2; + wire[`NUM_LDPES-1:0] out_data_available_mvu_tile_2; + + MVU_tile tile_2(.clk(clk), + .start(start), + .reset(reset), + .out_data_available(out_data_available_mvu_tile_2), //WITH TAG + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .vrf_data_out(vrf_data_out_tile_2), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_2), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_2), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .mrf_in(mrf_in[3*`MRF_DWIDTH*`NUM_LDPES-1:2*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[3*`NUM_LDPES-1:2*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[3*`NUM_LDPES*`MRF_AWIDTH-1:2*`NUM_LDPES*`MRF_AWIDTH]), + + .mrf_we_for_dram(mrf_we_for_dram[3*`NUM_LDPES-1:2*`NUM_LDPES]), + .mrf_addr_for_dram(mrf_addr_for_dram[3*`NUM_LDPES*`MRF_AWIDTH-1:2*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[3*`NUM_LDPES*`MRF_DWIDTH-1:2*`NUM_LDPES*`MRF_DWIDTH]), + + .result(result_mvm_2) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_3; + wire[`NUM_LDPES-1:0] out_data_available_mvu_tile_3; + + MVU_tile tile_3(.clk(clk), + .start(start), + .reset(reset), + .out_data_available(out_data_available_mvu_tile_3), //WITH TAG + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .vrf_data_out(vrf_data_out_tile_3), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_3), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_3), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .mrf_in(mrf_in[4*`MRF_DWIDTH*`NUM_LDPES-1:3*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[4*`NUM_LDPES-1:3*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[4*`NUM_LDPES*`MRF_AWIDTH-1:3*`NUM_LDPES*`MRF_AWIDTH]), + + .mrf_we_for_dram(mrf_we_for_dram[4*`NUM_LDPES-1:3*`NUM_LDPES]), + .mrf_addr_for_dram(mrf_addr_for_dram[4*`NUM_LDPES*`MRF_AWIDTH-1:3*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[4*`NUM_LDPES*`MRF_DWIDTH-1:3*`NUM_LDPES*`MRF_DWIDTH]), + + .result(result_mvm_3) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_4; + wire[`NUM_LDPES-1:0] out_data_available_mvu_tile_4; + + MVU_tile tile_4(.clk(clk), + .start(start), + .reset(reset), + .out_data_available(out_data_available_mvu_tile_4), //WITH TAG + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .vrf_data_out(vrf_data_out_tile_4), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_4), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_4), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .mrf_in(mrf_in[5*`MRF_DWIDTH*`NUM_LDPES-1:4*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[5*`NUM_LDPES-1:4*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[5*`NUM_LDPES*`MRF_AWIDTH-1:4*`NUM_LDPES*`MRF_AWIDTH]), + + .mrf_we_for_dram(mrf_we_for_dram[5*`NUM_LDPES-1:4*`NUM_LDPES]), + .mrf_addr_for_dram(mrf_addr_for_dram[5*`NUM_LDPES*`MRF_AWIDTH-1:4*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[5*`NUM_LDPES*`MRF_DWIDTH-1:4*`NUM_LDPES*`MRF_DWIDTH]), + + .result(result_mvm_4) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_5; + wire[`NUM_LDPES-1:0] out_data_available_mvu_tile_5; + + MVU_tile tile_5(.clk(clk), + .start(start), + .reset(reset), + .out_data_available(out_data_available_mvu_tile_5), //WITH TAG + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .vrf_data_out(vrf_data_out_tile_5), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_5), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_5), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .mrf_in(mrf_in[6*`MRF_DWIDTH*`NUM_LDPES-1:5*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[6*`NUM_LDPES-1:5*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[6*`NUM_LDPES*`MRF_AWIDTH-1:5*`NUM_LDPES*`MRF_AWIDTH]), + + .mrf_we_for_dram(mrf_we_for_dram[6*`NUM_LDPES-1:5*`NUM_LDPES]), + .mrf_addr_for_dram(mrf_addr_for_dram[6*`NUM_LDPES*`MRF_AWIDTH-1:5*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[6*`NUM_LDPES*`MRF_DWIDTH-1:5*`NUM_LDPES*`MRF_DWIDTH]), + + .result(result_mvm_5) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_6; + wire[`NUM_LDPES-1:0] out_data_available_mvu_tile_6; + + MVU_tile tile_6(.clk(clk), + .start(start), + .reset(reset), + .out_data_available(out_data_available_mvu_tile_6), //WITH TAG + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .vrf_data_out(vrf_data_out_tile_6), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_6), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_6), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .mrf_in(mrf_in[7*`MRF_DWIDTH*`NUM_LDPES-1:6*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[7*`NUM_LDPES-1:6*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[7*`NUM_LDPES*`MRF_AWIDTH-1:6*`NUM_LDPES*`MRF_AWIDTH]), + + .mrf_we_for_dram(mrf_we_for_dram[7*`NUM_LDPES-1:6*`NUM_LDPES]), + .mrf_addr_for_dram(mrf_addr_for_dram[7*`NUM_LDPES*`MRF_AWIDTH-1:6*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[7*`NUM_LDPES*`MRF_DWIDTH-1:6*`NUM_LDPES*`MRF_DWIDTH]), + + .result(result_mvm_6) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_7; + wire[`NUM_LDPES-1:0] out_data_available_mvu_tile_7; + + MVU_tile tile_7(.clk(clk), + .start(start), + .reset(reset), + .out_data_available(out_data_available_mvu_tile_7), //WITH TAG + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .vrf_data_out(vrf_data_out_tile_7), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_7), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_7), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .mrf_in(mrf_in[8*`MRF_DWIDTH*`NUM_LDPES-1:7*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[8*`NUM_LDPES-1:7*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[8*`NUM_LDPES*`MRF_AWIDTH-1:7*`NUM_LDPES*`MRF_AWIDTH]), + + .mrf_we_for_dram(mrf_we_for_dram[8*`NUM_LDPES-1:7*`NUM_LDPES]), + .mrf_addr_for_dram(mrf_addr_for_dram[8*`NUM_LDPES*`MRF_AWIDTH-1:7*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[8*`NUM_LDPES*`MRF_DWIDTH-1:7*`NUM_LDPES*`MRF_DWIDTH]), + + .result(result_mvm_7) //WITH TAG + ); + + wire[`NUM_LDPES*`OUT_DWIDTH-1:0] reduction_unit_output; + wire[`NUM_LDPES-1:0] out_data_available_reduction_tree; + + mvm_reduction_unit mvm_reduction( + .clk(clk), + .start(out_data_available_mvu_tile_0), + .reset_reduction_mvm(reset), + .inp0(result_mvm_0), + .inp1(result_mvm_1), + .inp2(result_mvm_2), + .inp3(result_mvm_3), + .inp4(result_mvm_4), + .inp5(result_mvm_5), + .inp6(result_mvm_6), + .inp7(result_mvm_7), + .result_mvm_final_stage(reduction_unit_output), + .out_data_available(out_data_available_reduction_tree) + ); + + assign mvm_result = reduction_unit_output; + assign out_data_available = out_data_available_reduction_tree[0]; + +endmodule + + +module MVU_tile ( + input clk, + input [`NUM_LDPES-1:0] start, + input [`NUM_LDPES-1:0] reset, + input vrf_wr_enable, + input [`VRF_AWIDTH-1:0] vrf_wr_addr, + input [`VRF_AWIDTH-1:0] vrf_read_addr, + input [`VRF_DWIDTH-1:0] vec, + output[`VRF_DWIDTH-1:0] vrf_data_out, + input [`NUM_LDPES*`MRF_DWIDTH-1:0] mrf_in, + input vrf_readn_enable, + input[`NUM_LDPES-1:0] mrf_we, + input [`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr, + + input[`NUM_LDPES-1:0] mrf_we_for_dram, + input [`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram, + output [`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram, + + output [`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result, + output [`NUM_LDPES-1:0] out_data_available +); + + wire [`VRF_DWIDTH-1:0] ina_fake; + + + wire [`VRF_DWIDTH-1:0] vrf_outa_wire; + + //reg [`VRF_AWIDTH-1:0] vrf_rd_addr; + + // Port A is used to feed LDPE and port B to load vector from DRAM. + VRF vrf ( + .clk(clk), + .addra(vrf_read_addr), + .ina(ina_fake), + .wea(vrf_readn_enable), + .outa(vrf_outa_wire), + .addrb(vrf_wr_addr), + .inb(vec), + .web(vrf_wr_enable), + .outb(vrf_data_out) + ); + + genvar i; + generate +`ifdef QUARTUS + for (i=1; i<=`NUM_LDPES; i=i+1) begin: gen_cus +`else + for (i=1; i<=`NUM_LDPES; i=i+1) begin +`endif + compute_unit unit ( + .clk(clk), + .start(start[i-1]), + .reset(reset[i-1]), + .out_data_available(out_data_available[i-1]), + .vec(vrf_outa_wire), + .mrf_in(mrf_in[i*`MRF_DWIDTH-1:(i-1)*`MRF_DWIDTH]), + .mrf_we(mrf_we[i-1]), + .mrf_addr(mrf_addr[i*`MRF_AWIDTH-1:(i-1)*`MRF_AWIDTH]), + + .mrf_addr_for_dram(mrf_addr_for_dram[(i)*`MRF_AWIDTH-1:(i-1)*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[(i)*`MRF_DWIDTH-1:(i-1)*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[i-1]), + + .result(result[i*`LDPE_USED_OUTPUT_WIDTH-1:(i-1)*`LDPE_USED_OUTPUT_WIDTH]) + ); + end + endgenerate + +endmodule + +module compute_unit ( + input clk, + input start, + input reset, + input [`VRF_DWIDTH-1:0] vec, + input [`MRF_DWIDTH-1:0] mrf_in, + input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new + input mrf_we, mrf_we_for_dram, //new + input [`MRF_AWIDTH-1:0] mrf_addr, + output [`LDPE_USED_OUTPUT_WIDTH-1:0] result, + output [`MRF_DWIDTH-1:0] mrf_outa_to_dram, //new + output reg out_data_available +); + + // Port A of BRAMs is used for feed DSPs and Port B is used to load matrix from off-chip memory + reg [4:0] num_cycles_mvm; + + always@(posedge clk) begin + if((reset==1'b1) || (start==1'b0)) begin + num_cycles_mvm <= 0; + out_data_available <= 0; + end + else begin + if(num_cycles_mvm==`NUM_MVM_CYCLES-1) begin + out_data_available <= 1; + end + else begin + num_cycles_mvm <= num_cycles_mvm + 1'b1; + end + end + end + + // Port B of BRAMs is used for feed DSPs and Port A is used to interact with DRAM + + + wire [`MRF_DWIDTH-1:0] mrf_outb_wire; + + wire [`LDPE_USED_INPUT_WIDTH-1:0] ax_wire; + wire [`LDPE_USED_INPUT_WIDTH-1:0] ay_wire; + wire [`LDPE_USED_INPUT_WIDTH-1:0] bx_wire; + wire [`LDPE_USED_INPUT_WIDTH-1:0] by_wire; + + // Wire connecting LDPE output to Output BRAM input + wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result; + + wire [`LDPE_USED_OUTPUT_WIDTH-1:0] inb_fake_wire; + + // First 4 BRAM outputs are given to ax of 4 DSPs and next 4 BRAM outputs are given to bx of DSPs + + // Connection MRF and LDPE wires for matrix data + // 'X' pin is used for matrix + /* If there are 4 DSPSs, bit[31:0] of mrf output contain ax values for the 4 DSPs, bit[63:32] contain bx values and so on. With a group of ax values, bit[7:0] contain ax value for DSP1, bit[15:8] contain ax value for DSP2 and so on. */ + assign ax_wire = mrf_outb_wire[1*`LDPE_USED_INPUT_WIDTH-1:0*`LDPE_USED_INPUT_WIDTH]; + assign bx_wire = mrf_outb_wire[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH]; + + // Connection of VRF and LDPE wires for vector data + // 'Y' pin is used for vector + assign ay_wire = vec[`LDPE_USED_INPUT_WIDTH-1:0]; + assign by_wire = vec[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH]; + + wire [`MRF_DWIDTH-1:0] mrf_in_fake; + + MRF mrf ( + .clk(clk), + .addra(mrf_addr_for_dram), + .addrb(mrf_addr), + .ina(mrf_in), + .inb(mrf_in_fake), + .wea(mrf_we_for_dram), + .web(mrf_we), + .outa(mrf_outa_to_dram), + .outb(mrf_outb_wire) + ); + + LDPE ldpe ( + .clk(clk), + .reset(reset), + .ax(ax_wire), + .ay(ay_wire), + .bx(bx_wire), + .by(by_wire), + .ldpe_result(ldpe_result) + ); + assign result = ldpe_result; + +endmodule + +module LDPE ( + input clk, + input reset, + input [`LDPE_USED_INPUT_WIDTH-1:0] ax, + input [`LDPE_USED_INPUT_WIDTH-1:0] ay, + input [`LDPE_USED_INPUT_WIDTH-1:0] bx, + input [`LDPE_USED_INPUT_WIDTH-1:0] by, + output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result +); + + wire [`LDPE_USED_OUTPUT_WIDTH*`SUB_LDPES_PER_LDPE-1:0] sub_ldpe_result; + //wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result; + + SUB_LDPE sub_1( + .clk(clk), + .reset(reset), + .ax(ax[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .ay(ay[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .bx(bx[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .by(by[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .result(sub_ldpe_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH]) + ); + assign ldpe_result = sub_ldpe_result[(0+1)*`DSP_USED_OUTPUT_WIDTH-1:0*`DSP_USED_OUTPUT_WIDTH]; + +endmodule + +module myadder #( + parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH, + parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH +) +( + input [INPUT_WIDTH-1:0] a, + input [INPUT_WIDTH-1:0] b, + input reset, + input start, + input clk, + output reg [OUTPUT_WIDTH-1:0] sum, + output reg out_data_available +); + + always@(posedge clk) begin + if((reset==1) || (start==0)) begin + sum <= 0; + out_data_available <= 0; + end + else begin + out_data_available <= 1; + sum <= a + b; + end + end + +endmodule + +module SUB_LDPE ( + input clk, + input reset, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] ax, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] ay, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] bx, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] by, + output reg [`LDPE_USED_OUTPUT_WIDTH-1:0] result +); + + wire [`DSP_USED_OUTPUT_WIDTH*`DSPS_PER_SUB_LDPE-1:0] chainin, chainout, dsp_result; + + + wire [36:0] chainout_temp_0; + assign chainout_temp_0 = 37'b0; + + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_1; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_1; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_1; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_1; + + assign ax_wire_1 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax[1*`DSP_USED_INPUT_WIDTH-1:(1-1)*`DSP_USED_INPUT_WIDTH]}; + assign ay_wire_1 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay[1*`DSP_USED_INPUT_WIDTH-1:(1-1)*`DSP_USED_INPUT_WIDTH]}; + + assign bx_wire_1 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx[1*`DSP_USED_INPUT_WIDTH-1:(1-1)*`DSP_USED_INPUT_WIDTH]}; + assign by_wire_1 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, by[1*`DSP_USED_INPUT_WIDTH-1:(1-1)*`DSP_USED_INPUT_WIDTH]}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_1; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_1; + + assign dsp_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_1[`DSP_USED_OUTPUT_WIDTH-1:0]; + + dsp_block_18_18_int_sop_2 dsp_1 ( + .clk(clk), + .aclr(reset), + .ax(ax_wire_1), + .ay(ay_wire_1), + .bx(bx_wire_1), + .by(by_wire_1), + .chainin(chainout_temp_0), + .chainout(chainout_temp_1), + .result(result_temp_1) + ); + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_2; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_2; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_2; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_2; + + assign ax_wire_2 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax[2*`DSP_USED_INPUT_WIDTH-1:(2-1)*`DSP_USED_INPUT_WIDTH]}; + assign ay_wire_2 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay[2*`DSP_USED_INPUT_WIDTH-1:(2-1)*`DSP_USED_INPUT_WIDTH]}; + + assign bx_wire_2 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx[2*`DSP_USED_INPUT_WIDTH-1:(2-1)*`DSP_USED_INPUT_WIDTH]}; + assign by_wire_2 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, by[2*`DSP_USED_INPUT_WIDTH-1:(2-1)*`DSP_USED_INPUT_WIDTH]}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_2; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_2; + + assign dsp_result[2*`DSP_USED_OUTPUT_WIDTH-1:(2-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_2[`DSP_USED_OUTPUT_WIDTH-1:0]; + + dsp_block_18_18_int_sop_2 dsp_2 ( + .clk(clk), + .aclr(reset), + .ax(ax_wire_2), + .ay(ay_wire_2), + .bx(bx_wire_2), + .by(by_wire_2), + .chainin(chainout_temp_1), + .chainout(chainout_temp_2), + .result(result_temp_2) + ); + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_3; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_3; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_3; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_3; + + assign ax_wire_3 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax[3*`DSP_USED_INPUT_WIDTH-1:(3-1)*`DSP_USED_INPUT_WIDTH]}; + assign ay_wire_3 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay[3*`DSP_USED_INPUT_WIDTH-1:(3-1)*`DSP_USED_INPUT_WIDTH]}; + + assign bx_wire_3 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx[3*`DSP_USED_INPUT_WIDTH-1:(3-1)*`DSP_USED_INPUT_WIDTH]}; + assign by_wire_3 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, by[3*`DSP_USED_INPUT_WIDTH-1:(3-1)*`DSP_USED_INPUT_WIDTH]}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_3; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_3; + + assign dsp_result[3*`DSP_USED_OUTPUT_WIDTH-1:(3-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_3[`DSP_USED_OUTPUT_WIDTH-1:0]; + + dsp_block_18_18_int_sop_2 dsp_3 ( + .clk(clk), + .aclr(reset), + .ax(ax_wire_3), + .ay(ay_wire_3), + .bx(bx_wire_3), + .by(by_wire_3), + .chainin(chainout_temp_2), + .chainout(chainout_temp_3), + .result(result_temp_3) + ); + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_4; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_4; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_4; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_4; + + assign ax_wire_4 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax[4*`DSP_USED_INPUT_WIDTH-1:(4-1)*`DSP_USED_INPUT_WIDTH]}; + assign ay_wire_4 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay[4*`DSP_USED_INPUT_WIDTH-1:(4-1)*`DSP_USED_INPUT_WIDTH]}; + + assign bx_wire_4 = {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx[4*`DSP_USED_INPUT_WIDTH-1:(4-1)*`DSP_USED_INPUT_WIDTH]}; + assign by_wire_4 = {{`DSP_Y_ZERO_PAD_INPUT_WIDTH{1'b0}}, by[4*`DSP_USED_INPUT_WIDTH-1:(4-1)*`DSP_USED_INPUT_WIDTH]}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_4; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_4; + + assign dsp_result[4*`DSP_USED_OUTPUT_WIDTH-1:(4-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_4[`DSP_USED_OUTPUT_WIDTH-1:0]; + + dsp_block_18_18_int_sop_2 dsp_4 ( + .clk(clk), + .aclr(reset), + .ax(ax_wire_4), + .ay(ay_wire_4), + .bx(bx_wire_4), + .by(by_wire_4), + .chainin(chainout_temp_3), + .chainout(chainout_temp_4), + .result(result_temp_4) + ); + + always @(*) begin + if (reset) begin + result <= {`LDPE_USED_OUTPUT_WIDTH{1'd0}}; + end + else begin + result <= dsp_result[`DSPS_PER_SUB_LDPE*`LDPE_USED_OUTPUT_WIDTH-1:(`DSPS_PER_SUB_LDPE-1)*`LDPE_USED_OUTPUT_WIDTH]; + end + end + +endmodule + +module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) ( + input clk, + input [VRF_AWIDTH-1:0] addra, + input [VRF_AWIDTH-1:0] addrb, + input [VRF_DWIDTH-1:0] ina, + input [VRF_DWIDTH-1:0] inb, + input wea, web, + output [VRF_DWIDTH-1:0] outa, + output [VRF_DWIDTH-1:0] outb +); + + dp_ram # ( + .AWIDTH(VRF_AWIDTH), + .DWIDTH(VRF_DWIDTH) + ) vec_mem ( + .clk(clk), + .addra(addra), + .ina(ina), + .wea(wea), + .outa(outa), + .addrb(addrb), + .inb(inb), + .web(web), + .outb(outb) + ); +endmodule + +module MRF ( + input clk, + input [`MRF_AWIDTH-1:0] addra, + input [`MRF_AWIDTH-1:0] addrb, + input [`MRF_DWIDTH-1:0] ina, + input [`MRF_DWIDTH-1:0] inb, + input wea, web, + output [`MRF_DWIDTH-1:0] outa, + output [`MRF_DWIDTH-1:0] outb +); + + dp_ram # ( + .AWIDTH(`MRF_AWIDTH), + .DWIDTH(`MRF_DWIDTH) + ) vec_mem ( + .clk(clk), + .addra(addra), + .ina(ina), + .wea(wea), + .outa(outa), + .addrb(addrb), + .inb(inb), + .web(web), + .outb(outb) + ); + +endmodule + +module dsp_block_18_18_int_sop_2 ( + input clk, + input aclr, + input [`DSP_X_AVA_INPUT_WIDTH-1:0] ax, + input [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay, + input [`DSP_X_AVA_INPUT_WIDTH-1:0] bx, + input [`DSP_Y_AVA_INPUT_WIDTH-1:0] by, + input [`DSP_AVA_OUTPUT_WIDTH-1:0] chainin, + output [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout, + output [`DSP_AVA_OUTPUT_WIDTH-1:0] result +); + +`ifndef complex_dsp + +reg [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_reg; +reg [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_reg; +reg [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_reg; +reg [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_reg; +reg [`DSP_AVA_OUTPUT_WIDTH-1:0] result_reg; + +always @(posedge clk) begin + if(aclr) begin + result_reg <= 0; + ax_reg <= 0; + ay_reg <= 0; + bx_reg <= 0; + by_reg <= 0; + end + else begin + ax_reg <= ax; + ay_reg <= ay; + bx_reg <= bx; + by_reg <= by; + result_reg <= (ax_reg * ay_reg) + (bx_reg * by_reg) + chainin; + end +end +assign chainout = result_reg; +assign result = result_reg; + +`else + +wire [11:0] mode; +assign mode = 12'b0101_0101_0011; + +int_sop_2 mac_component ( + .mode_sigs(mode), + .clk(clk), + .reset(aclr), + .ax(ax), + .ay(ay), + .bx(bx), + .by(by), + .chainin(chainin), + .result(result), + .chainout(chainout) +); + +`endif + +endmodule + +////////////////////////////////// +// Dual port RAM +////////////////////////////////// + +module dp_ram # ( + parameter AWIDTH = 10, + parameter DWIDTH = 16 +) ( + input clk, + input [AWIDTH-1:0] addra, addrb, + input [DWIDTH-1:0] ina, inb, + input wea, web, + output reg [DWIDTH-1:0] outa, outb +); + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram [((1<=90) begin + address[i*4+:4] = 4'b0000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=39 && (inp_data[i*`DWIDTH +:`DWIDTH])<90) begin + address[i*4+:4] = 4'b0001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=28 && (inp_data[i*`DWIDTH +:`DWIDTH])<39) begin + address[i*4+:4] = 4'b0010; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=16 && (inp_data[i*`DWIDTH +:`DWIDTH])<28) begin + address[i*4+:4] = 4'b0011; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=1 && (inp_data[i*`DWIDTH +:`DWIDTH])<16) begin + address[i*4+:4] = 4'b0100; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])==0) begin + address[i*4+:4] = 4'b0101; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-16 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-1) begin + address[i*4+:4] = 4'b0110; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-28 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-16) begin + address[i*4+:4] = 4'b0111; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-39 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-28) begin + address[i*4+:4] = 4'b1000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-90 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-39) begin + address[i*4+:4] = 4'b1001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])<=-90) begin + address[i*4+:4] = 4'b1010; + end + else begin + address[i*4+:4] = 4'b0101; + end + end +end + +endmodule + + +module elt_wise_add( + input enable_add, + input in_data_available, + input add_or_sub, + input [`NUM_LDPES*`DWIDTH-1:0] primary_inp, + input [`NUM_LDPES*`DWIDTH-1:0] secondary_inp, + output [`NUM_LDPES*`DWIDTH-1:0] out_data, + output reg output_available_add, + input clk +); + wire [(`DWIDTH)-1:0] x_0; + wire [(`DWIDTH)-1:0] y_0; + + add a0(.p(out_data[(1*`DWIDTH)-1:(0*`DWIDTH)]),.x(x_0),.y(y_0), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_1; + wire [(`DWIDTH)-1:0] y_1; + + add a1(.p(out_data[(2*`DWIDTH)-1:(1*`DWIDTH)]),.x(x_1),.y(y_1), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_2; + wire [(`DWIDTH)-1:0] y_2; + + add a2(.p(out_data[(3*`DWIDTH)-1:(2*`DWIDTH)]),.x(x_2),.y(y_2), .clk(clk), .reset(~enable_add)); + wire [(`DWIDTH)-1:0] x_3; + wire [(`DWIDTH)-1:0] y_3; + + add a3(.p(out_data[(4*`DWIDTH)-1:(3*`DWIDTH)]),.x(x_3),.y(y_3), .clk(clk), .reset(~enable_add)); + + assign x_0 = primary_inp[(1*`DWIDTH)-1:(0*`DWIDTH)]; + assign x_1 = primary_inp[(2*`DWIDTH)-1:(1*`DWIDTH)]; + assign x_2 = primary_inp[(3*`DWIDTH)-1:(2*`DWIDTH)]; + assign x_3 = primary_inp[(4*`DWIDTH)-1:(3*`DWIDTH)]; + + assign y_0 = secondary_inp[(1*`DWIDTH)-1:(0*`DWIDTH)]; + assign y_1 = secondary_inp[(2*`DWIDTH)-1:(1*`DWIDTH)]; + assign y_2 = secondary_inp[(3*`DWIDTH)-1:(2*`DWIDTH)]; + assign y_3 = secondary_inp[(4*`DWIDTH)-1:(3*`DWIDTH)]; + + reg[`LOG_ADD_LATENCY-1:0] state; + always @(posedge clk) begin + if((enable_add==1'b1) && (in_data_available==1'b1)) begin + if(state!=`ADD_LATENCY) begin + state<=state+1'b1; + end + else begin + output_available_add<=1; + state<=0; + end + end + else begin + output_available_add<=0; + state<=0; + end + end + +endmodule +module elt_wise_mul( + input enable_mul, + input in_data_available, + input [`DESIGN_SIZE*`DWIDTH-1:0] primary_inp, + input [`DESIGN_SIZE*`DWIDTH-1:0] secondary_inp, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output reg output_available_mul, + input clk +); + wire [(`DWIDTH)-1:0] x_0; + wire [(`DWIDTH)-1:0] y_0; + + mult m0(.p(out_data[(1*`DWIDTH)-1:(0*`DWIDTH)]),.x(x_0),.y(y_0), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_1; + wire [(`DWIDTH)-1:0] y_1; + + mult m1(.p(out_data[(2*`DWIDTH)-1:(1*`DWIDTH)]),.x(x_1),.y(y_1), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_2; + wire [(`DWIDTH)-1:0] y_2; + + mult m2(.p(out_data[(3*`DWIDTH)-1:(2*`DWIDTH)]),.x(x_2),.y(y_2), .clk(clk), .reset(~enable_mul)); + wire [(`DWIDTH)-1:0] x_3; + wire [(`DWIDTH)-1:0] y_3; + + mult m3(.p(out_data[(4*`DWIDTH)-1:(3*`DWIDTH)]),.x(x_3),.y(y_3), .clk(clk), .reset(~enable_mul)); + + assign x_0 = primary_inp[(1*`DWIDTH)-1:(0*`DWIDTH)]; + assign x_1 = primary_inp[(2*`DWIDTH)-1:(1*`DWIDTH)]; + assign x_2 = primary_inp[(3*`DWIDTH)-1:(2*`DWIDTH)]; + assign x_3 = primary_inp[(4*`DWIDTH)-1:(3*`DWIDTH)]; + + assign y_0 = secondary_inp[(1*`DWIDTH)-1:(0*`DWIDTH)]; + assign y_1 = secondary_inp[(2*`DWIDTH)-1:(1*`DWIDTH)]; + assign y_2 = secondary_inp[(3*`DWIDTH)-1:(2*`DWIDTH)]; + assign y_3 = secondary_inp[(4*`DWIDTH)-1:(3*`DWIDTH)]; + + reg[`LOG_MUL_LATENCY-1:0] state; + always @(posedge clk) begin + if((enable_mul==1'b1) && (in_data_available==1'b1)) begin + + if(state!=`MUL_LATENCY) begin + state<=state+1'b1; + end + else begin + output_available_mul<=1; + state<=0; + end + end + else begin + output_available_mul<=0; + state<=0; + end + end + +endmodule + diff --git a/designs/koios/bwave_like.fixed.small/bwave_small_random.sv b/designs/koios/bwave_like.fixed.small/bwave_small_random.sv new file mode 100644 index 000000000..8492d5c03 --- /dev/null +++ b/designs/koios/bwave_like.fixed.small/bwave_small_random.sv @@ -0,0 +1,200 @@ +/* +Randomize input to bwave_large +*/ + +`include "../../random_number_generator.sv" + +`define IN_PRECISION 8 +`define OUT_PRECISION 8 + +`define NUM_TILES 8 + +`define NUM_LDPES 4 +`define DSPS_PER_LDPE 4 +`define DSPS_PER_SUB_LDPE 4 +`define SUB_LDPES_PER_LDPE (`DSPS_PER_LDPE/`DSPS_PER_SUB_LDPE) + +`define MULTS_PER_DSP 2 +`define DSP_X_AVA_INPUT_WIDTH 18 +`define LDPE_X_AVA_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) +`define DSP_Y_AVA_INPUT_WIDTH 19 +`define LDPE_Y_AVA_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) + +`define DSP_AVA_OUTPUT_WIDTH 37 +`define LDPE_AVA_OUTPUT_WIDTH `DSP_AVA_OUTPUT_WIDTH + +`define DSP_USED_INPUT_WIDTH `IN_PRECISION +`define LDPE_USED_INPUT_WIDTH (`DSP_USED_INPUT_WIDTH * `DSPS_PER_LDPE) +`define SUB_LDPE_USED_INPUT_WIDTH (`DSP_USED_INPUT_WIDTH * `DSPS_PER_SUB_LDPE) +`define DSP_X_ZERO_PAD_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) +`define DSP_Y_ZERO_PAD_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) + +`define DSP_USED_OUTPUT_WIDTH 32 +`define LDPE_USED_OUTPUT_WIDTH `DSP_USED_OUTPUT_WIDTH +`define DSP_ZERO_PAD_OUTPUT_WIDTH (`DSP_AVA_OUTPUT_WIDTH - `DSP_USED_OUTPUT_WIDTH) + +`define LDPES_PER_MRF 1 +`define DSPS_PER_MRF (`DSPS_PER_LDPE * `LDPES_PER_MRF) +`define MAT_BRAM_AWIDTH 10 +`define MAT_BRAM_DWIDTH 16 +`define MAT_BRAMS_PER_MRF_SUBSET 4 +`define MRF_AWIDTH (`MAT_BRAM_AWIDTH) +`define MRF_DWIDTH (`MAT_BRAM_DWIDTH * `MAT_BRAMS_PER_MRF_SUBSET) + +`define ORF_DWIDTH 32 //64 + +`define MAX_VRF_DWIDTH 64 +`define DRAM_DWIDTH `VRF_DWIDTH //this is the max of mrf, vrf and orf widths +`define DRAM_AWIDTH `MRF_AWIDTH + +`define LDPES_PER_VRF 1 +`define DSPS_PER_VRF (`DSPS_PER_LDPE * `LDPES_PER_VRF) +`define VEC_BRAM_AWIDTH 10 +`define VEC_BRAM_DWIDTH 16 +`define BRAMS_PER_VRF 4 +`define VRF_AWIDTH `VEC_BRAM_AWIDTH +`define VRF_DWIDTH (`VEC_BRAM_DWIDTH * `BRAMS_PER_VRF) + +`define LDPES_PER_ORF 1 +`define OUTPUTS_PER_LDPE 1 +`define OUT_BRAM_AWIDTH 10 +`define OUT_BRAM_DWIDTH 16 +`define ORF_AWIDTH `OUT_BRAM_AWIDTH +`define OUT_DWIDTH 8 +//`define ORF_DWIDTH `OUT_DWIDTH*`NUM_LDPES + + +`define DESIGN_SIZE `NUM_LDPES +`define DWIDTH `OUT_PRECISION +`define MASK_WIDTH `OUT_PRECISION + +`define ACTIVATION 2'b00 +`define ELT_WISE_MULTIPLY 2'b10 +`define ELT_WISE_ADD 2'b01 +`define BYPASS 2'b11 + +`define ADD_LATENCY 1 +`define LOG_ADD_LATENCY 1 +`define MUL_LATENCY 1 +`define LOG_MUL_LATENCY 1 +`define ACTIVATION_LATENCY 1 +`define TANH_LATENCY `ACTIVATION_LATENCY+1 + + +`define RELU 2'b00 +`define TANH 2'b01 +`define SIGM 2'b10 +//OPCODES + +`define V_RD 0 +`define V_WR 1 +`define M_RD 2 +`define M_WR 3 +`define MV_MUL 4 +`define VV_ADD 5 +`define VV_SUB 6 //QUESTIONED +`define VV_PASS 7 +`define VV_MUL 8 +`define V_RELU 9 +`define V_SIGM 10 +`define V_TANH 11 +`define END_CHAIN 12 + +//MEM_IDS + +`define VRF_0 0 +`define VRF_1 1 +`define VRF_2 2 +`define VRF_3 3 +`define VRF_4 4 +`define VRF_5 5 +`define VRF_6 6 +`define VRF_7 7 + +`define VRF_8 8 +`define VRF_9 9 +`define VRF_10 10 +`define VRF_11 11 +`define VRF_MUXED 12 +`define DRAM_MEM_ID 13 +`define MFU_0_DSTN_ID 14 +`define MFU_1_DSTN_ID 15 + + +`define MRF_0 0 +`define MRF_1 1 +`define MRF_2 2 +`define MRF_3 3 +`define MRF_4 4 +`define MRF_5 5 +`define MRF_6 6 +`define MRF_7 7 +`define MRF_8 8 +`define MRF_9 9 +`define MRF_10 10 +`define MRF_11 11 +`define MRF_12 12 +`define MRF_13 13 +`define MRF_14 14 +`define MRF_15 15 +`define MRF_16 16 +`define MRF_17 17 +`define MRF_18 18 +`define MRF_19 19 +`define MRF_20 20 +`define MRF_21 21 +`define MRF_22 22 +`define MRF_23 23 +`define MRF_24 24 +`define MRF_25 25 +`define MRF_26 26 +`define MRF_27 27 +`define MRF_28 28 +`define MRF_29 29 +`define MRF_30 30 +`define MRF_31 31 + +`define MFU_0 0 +`define MFU_1 1 + +`define INSTR_MEM_AWIDTH 10 + +`define NUM_MVM_CYCLES 8 + +`define OPCODE_WIDTH 4 +`define TARGET_OP_WIDTH 6 + +`define INSTR_WIDTH `OPCODE_WIDTH+`TARGET_OP_WIDTH+`DRAM_AWIDTH+`TARGET_OP_WIDTH+`VRF_AWIDTH + `VRF_AWIDTH + +module bwave_small_random ( + input logic clk, + input logic rst, + input logic [`INSTR_WIDTH-1:0] instruction, + output logic [`DRAM_DWIDTH-1:0] output_data_DRAM, + output logic [`DRAM_AWIDTH-1:0] dram_addr, + output logic dram_write_enable, + output logic get_instr, + output logic [`INSTR_MEM_AWIDTH-1:0] get_instr_addr +); + +logic [`DRAM_DWIDTH-1:0] input_data_DRAM; +RandomNumberGenerator #(`DRAM_DWIDTH, 0) rng ( + .clk(clk), + .reset(rst), + .random_number(input_data_DRAM) +); + +NPU npu0( + rst, + instruction, + input_data_DRAM, + output_data_DRAM, + dram_addr, + dram_write_enable, + get_instr, + get_instr_addr, + clk +); + +endmodule + diff --git a/designs/koios/bwave_like.fixed.small/design.yaml b/designs/koios/bwave_like.fixed.small/design.yaml new file mode 100644 index 000000000..b847b55ce --- /dev/null +++ b/designs/koios/bwave_like.fixed.small/design.yaml @@ -0,0 +1 @@ +top: bwave_small_random diff --git a/designs/koios/bwave_like.float.large/bwave_large_random.sv b/designs/koios/bwave_like.float.large/bwave_large_random.sv new file mode 100644 index 000000000..50bb1c535 --- /dev/null +++ b/designs/koios/bwave_like.float.large/bwave_large_random.sv @@ -0,0 +1,315 @@ +/* +Randomize input to bwave_large +*/ + +`include "../../random_number_generator.sv" + +`define NUM_TILES 4 +`define NUM_LDPES 32 +`define DSPS_PER_LDPE 4 + +`define IN_PRECISION 16 +`define OUT_PRECISION 16 + +`define FLOAT_EXP 8 +`define FLOAT_MANTISA 7 +`define FLOAT_DWIDTH (`FLOAT_EXP+`FLOAT_MANTISA + 1) + +`define BFLOAT_EXP 5 +`define BFLOAT_MANTISA 5 +`define BFLOAT_DWIDTH (`BFLOAT_EXP + `BFLOAT_MANTISA + 1) +`define BFLOAT_MANTISA_WITH_LO (`BFLOAT_MANTISA+1) + + +`define DSPS_PER_SUB_LDPE 4 +`define SUB_LDPES_PER_LDPE (`DSPS_PER_LDPE/`DSPS_PER_SUB_LDPE) + +`define MULTS_PER_DSP 2 +`define DSP_X_AVA_INPUT_WIDTH 18 +`define LDPE_X_AVA_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) +`define DSP_Y_AVA_INPUT_WIDTH 19 +`define LDPE_Y_AVA_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) + +`define DSP_AVA_OUTPUT_WIDTH 37 +`define LDPE_AVA_OUTPUT_WIDTH `DSP_AVA_OUTPUT_WIDTH + +`define DSP_USED_INPUT_WIDTH (`BFLOAT_MANTISA+1) + +`define LDPE_USED_INPUT_WIDTH (`FLOAT_DWIDTH * `DSPS_PER_LDPE) +`define SUB_LDPE_USED_INPUT_WIDTH (`BFLOAT_DWIDTH * `DSPS_PER_SUB_LDPE) +`define DSP_X_ZERO_PAD_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) +`define DSP_Y_ZERO_PAD_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) + +`define DSP_USED_OUTPUT_WIDTH 27 +`define LDPE_USED_OUTPUT_WIDTH `DSP_USED_OUTPUT_WIDTH +`define DSP_ZERO_PAD_OUTPUT_WIDTH (`DSP_AVA_OUTPUT_WIDTH - `DSP_USED_OUTPUT_WIDTH) + +`define LDPES_PER_MRF 1 +`define DSPS_PER_MRF (`DSPS_PER_LDPE * `LDPES_PER_MRF) +`define MAT_BRAM_AWIDTH 9 +`define MAT_BRAM_DWIDTH 16 +`define MAT_BRAMS_PER_MRF_SUBSET 8 +`define SUBSETS_PER_MRF 1 +`define BRAMS_PER_MRF (`MAT_BRAMS_PER_MRF_SUBSET * `SUBSETS_PER_MRF) +`define MRF_AWIDTH (`MAT_BRAM_AWIDTH) +`define MRF_DWIDTH (`MAT_BRAM_DWIDTH * `MAT_BRAMS_PER_MRF_SUBSET) + +`define LDPES_PER_VRF 1 +`define DSPS_PER_VRF (`DSPS_PER_LDPE * `LDPES_PER_VRF) +`define VEC_BRAM_AWIDTH 9 +`define VEC_BRAM_DWIDTH 16 +`define BRAMS_PER_VRF 8 +`define VRF_AWIDTH `VEC_BRAM_AWIDTH +`define VRF_DWIDTH (`VEC_BRAM_DWIDTH * `BRAMS_PER_VRF) + +`define LDPES_PER_ORF 1 +`define OUTPUTS_PER_LDPE 1 +`define OUT_BRAM_AWIDTH 9 +`define OUT_BRAM_DWIDTH 16 +`define ORF_AWIDTH `OUT_BRAM_AWIDTH +`define OUT_DWIDTH 16 +`define ORF_DWIDTH 512 //512 + +`define MAX_VRF_DWIDTH 512 +`define DRAM_DWIDTH `ORF_DWIDTH //This is the max of mrf, orf and vrf widths +`define DRAM_AWIDTH `MRF_AWIDTH + +`define OPCODE_WIDTH 4 +`define TARGET_OP_WIDTH 8 + +`define INSTR_WIDTH (`OPCODE_WIDTH+`TARGET_OP_WIDTH+`DRAM_AWIDTH+`TARGET_OP_WIDTH+`VRF_AWIDTH + `VRF_AWIDTH) + +`define ACTIVATION 2'b00 +`define ELT_WISE_MULTIPLY 2'b10 +`define ELT_WISE_ADD 2'b01 +`define BYPASS 2'b11 + +`define RELU 2'b00 +`define TANH 2'b01 +`define SIGM 2'b10 +//OPCODES + +`define V_RD 0 +`define V_WR 1 +`define M_RD 2 +`define M_WR 3 //NEWLY ADDED +`define MV_MUL 4 +`define VV_ADD 5 +`define VV_SUB 6 //QUESTIONED +`define VV_PASS 7 +`define VV_MUL 8 +`define V_RELU 9 +`define V_SIGM 10 +`define V_TANH 11 +`define END_CHAIN 12 +//MEM_IDS + +`define VRF_0 0 +`define VRF_1 1 +`define VRF_2 2 +`define VRF_3 3 + +`define VRF_4 4 +`define VRF_5 5 +`define VRF_6 6 +`define VRF_7 7 +`define VRF_MUXED 8 +`define DRAM_MEM_ID 9 +`define MFU_0_DSTN_ID 10 +`define MFU_1_DSTN_ID 11 + +`define MRF_0 0 +`define MRF_1 1 +`define MRF_2 2 +`define MRF_3 3 +`define MRF_4 4 +`define MRF_5 5 +`define MRF_6 6 +`define MRF_7 7 +`define MRF_8 8 +`define MRF_9 9 +`define MRF_10 10 +`define MRF_11 11 +`define MRF_12 12 +`define MRF_13 13 +`define MRF_14 14 +`define MRF_15 15 +`define MRF_16 16 +`define MRF_17 17 +`define MRF_18 18 +`define MRF_19 19 +`define MRF_20 20 +`define MRF_21 21 +`define MRF_22 22 +`define MRF_23 23 +`define MRF_24 24 +`define MRF_25 25 +`define MRF_26 26 +`define MRF_27 27 +`define MRF_28 28 +`define MRF_29 29 +`define MRF_30 30 +`define MRF_31 31 +`define MRF_32 32 +`define MRF_33 33 +`define MRF_34 34 +`define MRF_35 35 +`define MRF_36 36 +`define MRF_37 37 +`define MRF_38 38 +`define MRF_39 39 +`define MRF_40 40 +`define MRF_41 41 +`define MRF_42 42 +`define MRF_43 43 +`define MRF_44 44 +`define MRF_45 45 +`define MRF_46 46 +`define MRF_47 47 +`define MRF_48 48 +`define MRF_49 49 +`define MRF_50 50 +`define MRF_51 51 +`define MRF_52 52 +`define MRF_53 53 +`define MRF_54 54 +`define MRF_55 55 +`define MRF_56 56 +`define MRF_57 57 +`define MRF_58 58 +`define MRF_59 59 +`define MRF_60 60 +`define MRF_61 61 +`define MRF_62 62 +`define MRF_63 63 +`define MRF_64 64 +`define MRF_65 65 +`define MRF_66 66 +`define MRF_67 67 +`define MRF_68 68 +`define MRF_69 69 +`define MRF_70 70 +`define MRF_71 71 +`define MRF_72 72 +`define MRF_73 73 +`define MRF_74 74 +`define MRF_75 75 +`define MRF_76 76 +`define MRF_77 77 +`define MRF_78 78 +`define MRF_79 79 +`define MRF_80 80 +`define MRF_81 81 +`define MRF_82 82 +`define MRF_83 83 +`define MRF_84 84 +`define MRF_85 85 +`define MRF_86 86 +`define MRF_87 87 +`define MRF_88 88 +`define MRF_89 89 +`define MRF_90 90 +`define MRF_91 91 +`define MRF_92 92 +`define MRF_93 93 +`define MRF_94 94 +`define MRF_95 95 +`define MRF_96 96 +`define MRF_97 97 +`define MRF_98 98 +`define MRF_99 99 +`define MRF_100 100 +`define MRF_101 101 +`define MRF_102 102 +`define MRF_103 103 +`define MRF_104 104 +`define MRF_105 105 +`define MRF_106 106 +`define MRF_107 107 +`define MRF_108 108 +`define MRF_109 109 +`define MRF_110 110 +`define MRF_111 111 +`define MRF_112 112 +`define MRF_113 113 +`define MRF_114 114 +`define MRF_115 115 +`define MRF_116 116 +`define MRF_117 117 +`define MRF_118 118 +`define MRF_119 119 +`define MRF_120 120 +`define MRF_121 121 +`define MRF_122 122 +`define MRF_123 123 +`define MRF_124 124 +`define MRF_125 125 +`define MRF_126 126 +`define MRF_127 127 + +`define MFU_0 0 +`define MFU_1 1 +`define INSTR_MEM_AWIDTH 9 + +`define EXPONENT 5 +`define MANTISSA 10 + +`define SIGN 1 +`define NUM_COMPARATOR_TREE_CYCLES 5 +`define NUM_COMPARATOR_TREE_CYCLES_FOR_TILE 4 +`define NUM_LZD_CYCLES 5 + +`define DESIGN_SIZE `NUM_LDPES +`define DWIDTH `OUT_PRECISION +`define MASK_WIDTH `OUT_PRECISION + +`define ADD_LATENCY 5 +`define LOG_ADD_LATENCY 3 +`define MUL_LATENCY 5 +`define LOG_MUL_LATENCY 3 +`define ACTIVATION_LATENCY 3 +`define TANH_LATENCY (`ACTIVATION_LATENCY+1) +`define SIGMOID_LATENCY (`ACTIVATION_LATENCY+1) + +`define NUM_REDUCTION_CYCLES 2 +`define NUM_MVM_CYCLES 16 +`define NUM_NORMALISE_CYCLES 6 + +module bwave_large_random ( + input logic clk, + input logic rst, + output logic [`DRAM_DWIDTH-1:0] output_data_DRAM, + output logic [`DRAM_AWIDTH-1:0] dram_addr, + output logic dram_write_enable, + output logic get_instr, + output logic [`INSTR_MEM_AWIDTH-1:0] get_instr_addr +); + +logic [`DRAM_DWIDTH-1:0] input_data_DRAM; +RandomNumberGenerator #(`DRAM_DWIDTH, 0) rng ( + .clk(clk), + .reset(rst), + .random_number(input_data_DRAM) +); + +logic [`INSTR_WIDTH-1:0] instruction; +RandomNumberGenerator #(`INSTR_WIDTH, 1) rng_instr ( + .clk(clk), + .reset(rst), + .random_number(instruction) +); + +NPU npu0( + rst, + instruction, + input_data_DRAM, + output_data_DRAM, + dram_addr, + dram_write_enable, + get_instr, + get_instr_addr, + clk +); + +endmodule + diff --git a/designs/koios/bwave_like.float.large/bwave_like.float.large.v b/designs/koios/bwave_like.float.large/bwave_like.float.large.v new file mode 100644 index 000000000..ee7519af3 --- /dev/null +++ b/designs/koios/bwave_like.float.large/bwave_like.float.large.v @@ -0,0 +1,25206 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Tanmay Anand +////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////// +// A Microsoft Brainwave Like Design. Uses block floating point. +////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM includes.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + + +`define NUM_TILES 4 +`define NUM_LDPES 32 +`define DSPS_PER_LDPE 4 + +`define IN_PRECISION 16 +`define OUT_PRECISION 16 + +`define FLOAT_EXP 8 +`define FLOAT_MANTISA 7 +`define FLOAT_DWIDTH (`FLOAT_EXP+`FLOAT_MANTISA + 1) + +`define BFLOAT_EXP 5 +`define BFLOAT_MANTISA 5 +`define BFLOAT_DWIDTH (`BFLOAT_EXP + `BFLOAT_MANTISA + 1) +`define BFLOAT_MANTISA_WITH_LO (`BFLOAT_MANTISA+1) + + +`define DSPS_PER_SUB_LDPE 4 +`define SUB_LDPES_PER_LDPE (`DSPS_PER_LDPE/`DSPS_PER_SUB_LDPE) + +`define MULTS_PER_DSP 2 +`define DSP_X_AVA_INPUT_WIDTH 18 +`define LDPE_X_AVA_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) +`define DSP_Y_AVA_INPUT_WIDTH 19 +`define LDPE_Y_AVA_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) + +`define DSP_AVA_OUTPUT_WIDTH 37 +`define LDPE_AVA_OUTPUT_WIDTH `DSP_AVA_OUTPUT_WIDTH + +`define DSP_USED_INPUT_WIDTH (`BFLOAT_MANTISA+1) + +`define LDPE_USED_INPUT_WIDTH (`FLOAT_DWIDTH * `DSPS_PER_LDPE) +`define SUB_LDPE_USED_INPUT_WIDTH (`BFLOAT_DWIDTH * `DSPS_PER_SUB_LDPE) +`define DSP_X_ZERO_PAD_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) +`define DSP_Y_ZERO_PAD_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) + +`define DSP_USED_OUTPUT_WIDTH 27 +`define LDPE_USED_OUTPUT_WIDTH `DSP_USED_OUTPUT_WIDTH +`define DSP_ZERO_PAD_OUTPUT_WIDTH (`DSP_AVA_OUTPUT_WIDTH - `DSP_USED_OUTPUT_WIDTH) + +`define LDPES_PER_MRF 1 +`define DSPS_PER_MRF (`DSPS_PER_LDPE * `LDPES_PER_MRF) +`define MAT_BRAM_AWIDTH 9 +`define MAT_BRAM_DWIDTH 16 +`define MAT_BRAMS_PER_MRF_SUBSET 8 +`define SUBSETS_PER_MRF 1 +`define BRAMS_PER_MRF (`MAT_BRAMS_PER_MRF_SUBSET * `SUBSETS_PER_MRF) +`define MRF_AWIDTH (`MAT_BRAM_AWIDTH) +`define MRF_DWIDTH (`MAT_BRAM_DWIDTH * `MAT_BRAMS_PER_MRF_SUBSET) + +`define LDPES_PER_VRF 1 +`define DSPS_PER_VRF (`DSPS_PER_LDPE * `LDPES_PER_VRF) +`define VEC_BRAM_AWIDTH 9 +`define VEC_BRAM_DWIDTH 16 +`define BRAMS_PER_VRF 8 +`define VRF_AWIDTH `VEC_BRAM_AWIDTH +`define VRF_DWIDTH (`VEC_BRAM_DWIDTH * `BRAMS_PER_VRF) + +`define LDPES_PER_ORF 1 +`define OUTPUTS_PER_LDPE 1 +`define OUT_BRAM_AWIDTH 9 +`define OUT_BRAM_DWIDTH 16 +`define ORF_AWIDTH `OUT_BRAM_AWIDTH +`define OUT_DWIDTH 16 +`define ORF_DWIDTH 512 //512 + +`define MAX_VRF_DWIDTH 512 +`define DRAM_DWIDTH `ORF_DWIDTH //This is the max of mrf, orf and vrf widths +`define DRAM_AWIDTH `MRF_AWIDTH + +`define OPCODE_WIDTH 4 +`define TARGET_OP_WIDTH 8 + +`define INSTR_WIDTH (`OPCODE_WIDTH+`TARGET_OP_WIDTH+`DRAM_AWIDTH+`TARGET_OP_WIDTH+`VRF_AWIDTH + `VRF_AWIDTH) + +`define ACTIVATION 2'b00 +`define ELT_WISE_MULTIPLY 2'b10 +`define ELT_WISE_ADD 2'b01 +`define BYPASS 2'b11 + +`define RELU 2'b00 +`define TANH 2'b01 +`define SIGM 2'b10 +//OPCODES + +`define V_RD 0 +`define V_WR 1 +`define M_RD 2 +`define M_WR 3 //NEWLY ADDED +`define MV_MUL 4 +`define VV_ADD 5 +`define VV_SUB 6 //QUESTIONED +`define VV_PASS 7 +`define VV_MUL 8 +`define V_RELU 9 +`define V_SIGM 10 +`define V_TANH 11 +`define END_CHAIN 12 +//MEM_IDS + +`define VRF_0 0 +`define VRF_1 1 +`define VRF_2 2 +`define VRF_3 3 + +`define VRF_4 4 +`define VRF_5 5 +`define VRF_6 6 +`define VRF_7 7 +`define VRF_MUXED 8 +`define DRAM_MEM_ID 9 +`define MFU_0_DSTN_ID 10 +`define MFU_1_DSTN_ID 11 + +`define MRF_0 0 +`define MRF_1 1 +`define MRF_2 2 +`define MRF_3 3 +`define MRF_4 4 +`define MRF_5 5 +`define MRF_6 6 +`define MRF_7 7 +`define MRF_8 8 +`define MRF_9 9 +`define MRF_10 10 +`define MRF_11 11 +`define MRF_12 12 +`define MRF_13 13 +`define MRF_14 14 +`define MRF_15 15 +`define MRF_16 16 +`define MRF_17 17 +`define MRF_18 18 +`define MRF_19 19 +`define MRF_20 20 +`define MRF_21 21 +`define MRF_22 22 +`define MRF_23 23 +`define MRF_24 24 +`define MRF_25 25 +`define MRF_26 26 +`define MRF_27 27 +`define MRF_28 28 +`define MRF_29 29 +`define MRF_30 30 +`define MRF_31 31 +`define MRF_32 32 +`define MRF_33 33 +`define MRF_34 34 +`define MRF_35 35 +`define MRF_36 36 +`define MRF_37 37 +`define MRF_38 38 +`define MRF_39 39 +`define MRF_40 40 +`define MRF_41 41 +`define MRF_42 42 +`define MRF_43 43 +`define MRF_44 44 +`define MRF_45 45 +`define MRF_46 46 +`define MRF_47 47 +`define MRF_48 48 +`define MRF_49 49 +`define MRF_50 50 +`define MRF_51 51 +`define MRF_52 52 +`define MRF_53 53 +`define MRF_54 54 +`define MRF_55 55 +`define MRF_56 56 +`define MRF_57 57 +`define MRF_58 58 +`define MRF_59 59 +`define MRF_60 60 +`define MRF_61 61 +`define MRF_62 62 +`define MRF_63 63 +`define MRF_64 64 +`define MRF_65 65 +`define MRF_66 66 +`define MRF_67 67 +`define MRF_68 68 +`define MRF_69 69 +`define MRF_70 70 +`define MRF_71 71 +`define MRF_72 72 +`define MRF_73 73 +`define MRF_74 74 +`define MRF_75 75 +`define MRF_76 76 +`define MRF_77 77 +`define MRF_78 78 +`define MRF_79 79 +`define MRF_80 80 +`define MRF_81 81 +`define MRF_82 82 +`define MRF_83 83 +`define MRF_84 84 +`define MRF_85 85 +`define MRF_86 86 +`define MRF_87 87 +`define MRF_88 88 +`define MRF_89 89 +`define MRF_90 90 +`define MRF_91 91 +`define MRF_92 92 +`define MRF_93 93 +`define MRF_94 94 +`define MRF_95 95 +`define MRF_96 96 +`define MRF_97 97 +`define MRF_98 98 +`define MRF_99 99 +`define MRF_100 100 +`define MRF_101 101 +`define MRF_102 102 +`define MRF_103 103 +`define MRF_104 104 +`define MRF_105 105 +`define MRF_106 106 +`define MRF_107 107 +`define MRF_108 108 +`define MRF_109 109 +`define MRF_110 110 +`define MRF_111 111 +`define MRF_112 112 +`define MRF_113 113 +`define MRF_114 114 +`define MRF_115 115 +`define MRF_116 116 +`define MRF_117 117 +`define MRF_118 118 +`define MRF_119 119 +`define MRF_120 120 +`define MRF_121 121 +`define MRF_122 122 +`define MRF_123 123 +`define MRF_124 124 +`define MRF_125 125 +`define MRF_126 126 +`define MRF_127 127 + +`define MFU_0 0 +`define MFU_1 1 +`define INSTR_MEM_AWIDTH 9 + +`define EXPONENT 5 +`define MANTISSA 10 + +`define SIGN 1 +`define NUM_COMPARATOR_TREE_CYCLES 5 +`define NUM_COMPARATOR_TREE_CYCLES_FOR_TILE 4 +`define NUM_LZD_CYCLES 5 + +`define DESIGN_SIZE `NUM_LDPES +`define DWIDTH `OUT_PRECISION +`define MASK_WIDTH `OUT_PRECISION + +`define ADD_LATENCY 5 +`define LOG_ADD_LATENCY 3 +`define MUL_LATENCY 5 +`define LOG_MUL_LATENCY 3 +`define ACTIVATION_LATENCY 3 +`define TANH_LATENCY (`ACTIVATION_LATENCY+1) +`define SIGMOID_LATENCY (`ACTIVATION_LATENCY+1) + +`define NUM_REDUCTION_CYCLES 2 +`define NUM_MVM_CYCLES 16 +`define NUM_NORMALISE_CYCLES 6 +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM npu.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + + +module NPU( + input reset_npu, + input[`INSTR_WIDTH-1:0] instruction, + input[`DRAM_DWIDTH-1:0] input_data_DRAM, + output [`DRAM_DWIDTH-1:0] output_data_DRAM, + output [`DRAM_AWIDTH-1:0] dram_addr, + output dram_write_enable, + output get_instr, + output[`INSTR_MEM_AWIDTH-1:0] get_instr_addr, + //WRITE DOCUMENTATION EXPLAINING HOW MANY PORTS EACH VRF,MRF, ORF HAS and WHERE IS IT CONNECTED TO + input clk +); + wire[`ORF_DWIDTH-1:0] output_final_stage; + + + wire start_mv_mul_signal; + wire start_mfu_0_signal; + wire start_mfu_1_signal; + + + //SAME SIGNAL FOR ALL THE TILES AS PARALLEL EXECUTION OF TILES IS REQUIRED + reg[`NUM_LDPES-1:0] start_tile_with_single_cyc_latency; + reg[`NUM_LDPES-1:0] reset_tile_with_single_cyc_latency; + // + + wire [`MAX_VRF_DWIDTH-1:0] vrf_in_data; + wire[`VRF_AWIDTH-1:0] vrf_addr_wr; + wire[`VRF_AWIDTH-1:0] vrf_addr_read; + wire [`MRF_DWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_in_data; + + + //MRF SIGNALS + wire[`NUM_LDPES*`NUM_TILES-1:0] mrf_we; + wire [`MRF_AWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_addr_wr; + // + + //FINAL STAGE OUTPUT SIGNALS + wire[`ORF_DWIDTH-1:0] result_mvm; + //reg[`ORF_AWIDTH-1:0] result_addr_mvu_orf; + + //wire orf_addr_increment; + + // + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_0; + wire vrf_mvu_wr_enable_0; + wire vrf_mvu_readn_enable_0; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_1; + wire vrf_mvu_wr_enable_1; + wire vrf_mvu_readn_enable_1; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_2; + wire vrf_mvu_wr_enable_2; + wire vrf_mvu_readn_enable_2; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_3; + wire vrf_mvu_wr_enable_3; + wire vrf_mvu_readn_enable_3; + + wire done_mvm; //CHANGES THE REST STATE OF INSTR DECODER + wire out_data_available_mvm; + + wire[`NUM_TILES*`NUM_LDPES-1:0] mrf_we_for_dram; + wire [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram; + wire [`NUM_TILES*`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram; + + MVU mvm_unit ( + .clk(clk), + .start(start_tile_with_single_cyc_latency), + .reset(reset_tile_with_single_cyc_latency), + + .vrf_wr_addr(vrf_addr_wr), + .vrf_read_addr(vrf_addr_read), + .vec(vrf_in_data[`VRF_DWIDTH-1:0]), + .vrf_data_out_tile_0(vrf_mvu_out_0), //WITH TAG + .vrf_wr_enable_tile_0(vrf_mvu_wr_enable_0), //WITH TAG + .vrf_readn_enable_tile_0(vrf_mvu_readn_enable_0), //WITH TAG + .vrf_data_out_tile_1(vrf_mvu_out_1), //WITH TAG + .vrf_wr_enable_tile_1(vrf_mvu_wr_enable_1), //WITH TAG + .vrf_readn_enable_tile_1(vrf_mvu_readn_enable_1), //WITH TAG + .vrf_data_out_tile_2(vrf_mvu_out_2), //WITH TAG + .vrf_wr_enable_tile_2(vrf_mvu_wr_enable_2), //WITH TAG + .vrf_readn_enable_tile_2(vrf_mvu_readn_enable_2), //WITH TAG + .vrf_data_out_tile_3(vrf_mvu_out_3), //WITH TAG + .vrf_wr_enable_tile_3(vrf_mvu_wr_enable_3), //WITH TAG + .vrf_readn_enable_tile_3(vrf_mvu_readn_enable_3), //WITH TAG + + .mrf_in(mrf_in_data), + .mrf_we(mrf_we), //WITH TAG + .mrf_addr(mrf_addr_wr), + + .mrf_we_for_dram(mrf_we_for_dram), + .mrf_addr_for_dram(mrf_addr_for_dram), + .mrf_outa_to_dram(mrf_outa_to_dram), + + .out_data_available(out_data_available_mvm), + .mvm_result(result_mvm) //WITH TAG + ); + + assign done_mvm = out_data_available_mvm; + + reg[3:0] num_cycles_mvm; + + + //******************************************************************************* + + wire in_data_available_mfu_0; + reg reset_mfu_0_with_single_cyc_latency; + wire out_data_available_mfu_0; + wire done_mfu_0; + + wire in_data_available_mfu_1; + reg reset_mfu_1_with_single_cyc_latency; + wire out_data_available_mfu_1; + wire done_mfu_1; + + wire[1:0] activation; + wire[1:0] operation; + + //MFU VRF WIRES **************************************************************** + //wire[`VRF_AWIDTH-1:0] vrf_mfu_addr_read_add_0; + + //MFU - STAGE 0 VRF SIGNALS + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_add_0; + wire vrf_mfu_readn_enable_add_0; + wire vrf_mfu_wr_enable_add_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_add_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_add_0; + + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_mul_0; + wire vrf_mfu_readn_enable_mul_0; + wire vrf_mfu_wr_enable_mul_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_mul_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_mul_0; + + //wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_add_1; + + //MFU - STAGE 1 VRF SIGNALS + + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_add_1; + wire vrf_mfu_readn_enable_add_1; + wire vrf_mfu_wr_enable_add_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_add_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_add_1; + + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_mul_1; + wire vrf_mfu_readn_enable_mul_1; + wire vrf_mfu_wr_enable_mul_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_mul_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_mul_1; + + wire[`TARGET_OP_WIDTH-1:0] dstn_id; + wire[`NUM_LDPES*`OUT_DWIDTH-1:0] output_mvu_stage; + //************************************************************ + + assign output_mvu_stage = result_mvm; + + //************** INTER MFU MVU DATAPATH SIGNALS ************************************************* + reg[`ORF_DWIDTH-1:0] output_mvu_stage_buffer; + reg[`ORF_DWIDTH-1:0] output_mfu_stage_0_buffer; + + wire[`ORF_DWIDTH-1:0] primary_in_data_mfu_stage_0; + wire[`ORF_DWIDTH-1:0] primary_in_data_mfu_stage_1; + + + wire[`NUM_LDPES*`OUT_DWIDTH-1:0] output_mfu_stage_0; + wire[`NUM_LDPES*`OUT_DWIDTH-1:0] output_mfu_stage_1; + + always@(posedge clk) begin + if((dstn_id==`MFU_0_DSTN_ID) && done_mvm==1'b1) begin + output_mvu_stage_buffer <= output_mvu_stage; + end + end + + //CHECK THIS LOGIC CAREFULLY ***************************************************************** + always@(posedge clk) begin //FIRST BYPASS MUXING + //$display("%h", vrf_mvu_wr_addr_0); + if((dstn_id==`MFU_1_DSTN_ID) && (done_mfu_0 || done_mvm)) begin + output_mfu_stage_0_buffer <= (done_mfu_0) ? output_mfu_stage_0 : output_mvu_stage; + end + end + + assign output_final_stage = ((dstn_id!=`MFU_0_DSTN_ID) && (dstn_id!=`MFU_1_DSTN_ID)) ? + (done_mfu_1 ? output_mfu_stage_1 : //SECOND BYPASS MUXING + (done_mfu_0 ? output_mfu_stage_0 : + (done_mvm ? output_mvu_stage : 'd0))) : 'd0; + + //******************************************************************************************** + + + //****************************************************************************************** + wire[`ORF_DWIDTH-1:0] vrf_muxed_in_data_fake; + //************* MUXED MVU-MFU VRF ********************************************************** + + wire[`ORF_AWIDTH-1:0] vrf_muxed_wr_addr_dram; + wire[`ORF_DWIDTH-1:0] vrf_muxed_in_data; + wire vrf_muxed_wr_enable_dram; + wire vrf_muxed_readn_enable; + + wire[`ORF_AWIDTH-1:0] vrf_muxed_read_addr; + wire[`ORF_DWIDTH-1:0] vrf_muxed_out_data_dram; + wire[`ORF_DWIDTH-1:0] vrf_muxed_out_data; + + + VRF #(.VRF_DWIDTH(`ORF_DWIDTH),.VRF_AWIDTH(`ORF_AWIDTH)) vrf_muxed ( + .clk(clk), + + .addra(vrf_muxed_wr_addr_dram), + .ina(vrf_in_data[`ORF_DWIDTH-1:0]), + .wea(vrf_muxed_wr_enable_dram), + .outa(vrf_muxed_out_data_dram), + + .addrb(vrf_muxed_read_addr), + .inb(vrf_muxed_in_data_fake), + .web(vrf_muxed_readn_enable), + .outb(vrf_muxed_out_data) + ); + + wire mvu_or_vrf_mux_select; + assign primary_in_data_mfu_stage_0 = (mvu_or_vrf_mux_select) ? vrf_muxed_out_data : output_mvu_stage_buffer; + + assign primary_in_data_mfu_stage_1 = output_mfu_stage_0_buffer; + + //********************************************************************************************* + + //*********************************CONTROLLER FOR NPU***************************************** + controller controller_for_npu( + .clk(clk), + .reset_npu(reset_npu), + .instruction(instruction), + .get_instr(get_instr), + .get_instr_addr(get_instr_addr), + + .input_data_from_dram(input_data_DRAM), + .dram_addr_wr(dram_addr), + .dram_write_enable(dram_write_enable), + .output_data_to_dram(output_data_DRAM), + + .output_final_stage(output_final_stage), + + .start_mfu_0(start_mfu_0_signal), + .start_mfu_1(start_mfu_1_signal), + .start_mv_mul(start_mv_mul_signal), + .in_data_available_mfu_0(in_data_available_mfu_0), + .in_data_available_mfu_1(in_data_available_mfu_1), + + .activation(activation), + .operation(operation), + + .vrf_addr_read(vrf_addr_read), + .vrf_addr_wr(vrf_addr_wr), + + .vrf_out_data_mvu_0(vrf_mvu_out_0), //MVU TILE VRF + .vrf_readn_enable_mvu_0(vrf_mvu_readn_enable_0), + .vrf_wr_enable_mvu_0(vrf_mvu_wr_enable_0), + .vrf_out_data_mvu_1(vrf_mvu_out_1), //MVU TILE VRF + .vrf_readn_enable_mvu_1(vrf_mvu_readn_enable_1), + .vrf_wr_enable_mvu_1(vrf_mvu_wr_enable_1), + .vrf_out_data_mvu_2(vrf_mvu_out_2), //MVU TILE VRF + .vrf_readn_enable_mvu_2(vrf_mvu_readn_enable_2), + .vrf_wr_enable_mvu_2(vrf_mvu_wr_enable_2), + .vrf_out_data_mvu_3(vrf_mvu_out_3), //MVU TILE VRF + .vrf_readn_enable_mvu_3(vrf_mvu_readn_enable_3), + .vrf_wr_enable_mvu_3(vrf_mvu_wr_enable_3), + + .done_mvm(done_mvm), + .done_mfu_0(done_mfu_0), + .done_mfu_1(done_mfu_1), + //CHANGE INDEXING FOR VRFs-------------------------------------------- + + .vrf_out_data_mfu_add_0(vrf_mfu_out_data_add_0), + .vrf_readn_enable_mfu_add_0(vrf_mfu_readn_enable_add_0), + .vrf_wr_enable_mfu_add_0(vrf_mfu_wr_enable_add_0), //MFU VRF - ADD -0 + .vrf_addr_read_mfu_add_0(vrf_mfu_addr_read_add_0), + .vrf_addr_wr_mfu_add_0(vrf_mfu_addr_wr_add_0), + + + .vrf_out_data_mfu_mul_0(vrf_mfu_out_data_mul_0), //MFU VRF - MUL -0 + .vrf_readn_enable_mfu_mul_0(vrf_mfu_readn_enable_mul_0), + .vrf_wr_enable_mfu_mul_0(vrf_mfu_wr_enable_mul_0), + .vrf_addr_read_mfu_mul_0(vrf_mfu_addr_read_mul_0), + .vrf_addr_wr_mfu_mul_0(vrf_mfu_addr_wr_mul_0), + + .vrf_out_data_mfu_add_1(vrf_mfu_out_data_add_1), + .vrf_readn_enable_mfu_add_1(vrf_mfu_readn_enable_add_1), + .vrf_wr_enable_mfu_add_1(vrf_mfu_wr_enable_add_1), //MFU VRF - ADD - 1 + .vrf_addr_read_mfu_add_1(vrf_mfu_addr_read_add_1), + .vrf_addr_wr_mfu_add_1(vrf_mfu_addr_wr_add_1), + + + .vrf_out_data_mfu_mul_1(vrf_mfu_out_data_mul_1), //MFU VRF - MUL - 1 + .vrf_readn_enable_mfu_mul_1(vrf_mfu_readn_enable_mul_1), + .vrf_wr_enable_mfu_mul_1(vrf_mfu_wr_enable_mul_1), + .vrf_addr_read_mfu_mul_1(vrf_mfu_addr_read_mul_1), + .vrf_addr_wr_mfu_mul_1(vrf_mfu_addr_wr_mul_1), + + //MUXED VRF--------------------------------------- + .vrf_muxed_wr_addr_dram(vrf_muxed_wr_addr_dram), + .vrf_muxed_read_addr(vrf_muxed_read_addr), + .vrf_muxed_out_data_dram(vrf_muxed_out_data_dram), + .vrf_muxed_wr_enable_dram(vrf_muxed_wr_enable_dram), + .vrf_muxed_readn_enable(vrf_muxed_readn_enable), + //---------------------------------------------- + + .mvu_or_vrf_mux_select(mvu_or_vrf_mux_select), + .vrf_in_data(vrf_in_data), //common + + //----------------------------------------------------------------- + + .mrf_addr_wr(mrf_addr_wr), + .mrf_wr_enable(mrf_we), + .mrf_in_data(mrf_in_data), + + .mrf_we_for_dram(mrf_we_for_dram), + .mrf_addr_for_dram(mrf_addr_for_dram), + .mrf_outa_to_dram(mrf_outa_to_dram), + + //.orf_addr_increment(orf_addr_increment), + + .dstn_id(dstn_id) + ); + //*************************************************************************** + + //DELAYS START SIGNALS OF MVU TILE BY ONE CYCLE TO AVOID HIGH FANOUT AND ARITHEMETIC OF DONT CARES *********** + always@(posedge clk) begin + if(start_mv_mul_signal==1'b1) begin + start_tile_with_single_cyc_latency<={`NUM_LDPES{1'b1}}; + reset_tile_with_single_cyc_latency<={`NUM_LDPES{1'b0}}; + end + else begin + start_tile_with_single_cyc_latency<={`NUM_LDPES{1'b0}}; + reset_tile_with_single_cyc_latency<={`NUM_LDPES{1'b1}}; + end + end + + always@(*) begin + if(start_mfu_0_signal==1'b1) begin + reset_mfu_0_with_single_cyc_latency<=1'b0; + end + else begin + reset_mfu_0_with_single_cyc_latency<=1'b1; + end + end + + always@(*) begin + if(start_mfu_1_signal==1'b1) begin + reset_mfu_1_with_single_cyc_latency<=1'b0; + end + else begin + reset_mfu_1_with_single_cyc_latency<=1'b1; + end + end + + + //********************************************************************************************* + wire out_data_available_0; + //assign out_data_available_0 = done_mfu_0; + MFU mfu_stage_0( + .activation_type(activation), + .operation(operation), + .in_data_available(in_data_available_mfu_0), + + .vrf_addr_read_add(vrf_mfu_addr_read_add_0), + .vrf_addr_wr_add(vrf_mfu_addr_wr_add_0), + .vrf_readn_enable_add(vrf_mfu_readn_enable_add_0), + .vrf_wr_enable_add(vrf_mfu_wr_enable_add_0), + + .vrf_addr_read_mul(vrf_mfu_addr_read_mul_1), + .vrf_addr_wr_mul(vrf_mfu_addr_wr_mul_1), + .vrf_readn_enable_mul(vrf_mfu_readn_enable_mul_0), + .vrf_wr_enable_mul(vrf_mfu_wr_enable_mul_0), + + .primary_inp(primary_in_data_mfu_stage_0), + .secondary_inp(vrf_in_data[`ORF_DWIDTH-1:0]), + .out_data(output_mfu_stage_0), + .out_data_available(out_data_available_0), + .done(done_mfu_0), + .clk(clk), + + //VRF OUT SIGNALS + .out_vrf_add(vrf_mfu_out_data_add_0), + .out_vrf_mul(vrf_mfu_out_data_mul_0), + + .reset(reset_mfu_0_with_single_cyc_latency) + ); + + //************************************************************************* + //MFU STAGE - 2 + wire out_data_available_1; + //assign out_data_available_1 = done_mfu_1; + + MFU mfu_stage_1( + .activation_type(activation), + .operation(operation), + .in_data_available(in_data_available_mfu_1), + + //VRF IO SIGNALS FOR ELTWISE-ADD + .vrf_addr_read_add(vrf_mfu_addr_read_add_1), + .vrf_addr_wr_add(vrf_mfu_addr_wr_add_1), + .vrf_readn_enable_add(vrf_mfu_readn_enable_add_1), + .vrf_wr_enable_add(vrf_mfu_wr_enable_add_1), + + .vrf_addr_read_mul(vrf_mfu_addr_read_mul_1), + .vrf_addr_wr_mul(vrf_mfu_addr_wr_mul_1), + .vrf_readn_enable_mul(vrf_mfu_readn_enable_mul_1), + .vrf_wr_enable_mul(vrf_mfu_wr_enable_mul_1), + + //VRF IO SIGNALS FOR ELTWISE-MUL + .primary_inp(primary_in_data_mfu_stage_1), + .secondary_inp(vrf_in_data[`ORF_DWIDTH-1:0]), + .out_data(output_mfu_stage_1), + + .out_data_available(out_data_available_mfu_1), + .done(done_mfu_1), + .clk(clk), + + //VRF OUT SIGNAL + .out_vrf_add(vrf_mfu_out_data_add_1), + .out_vrf_mul(vrf_mfu_out_data_mul_1), + + .reset(reset_mfu_1_with_single_cyc_latency) + ); + + //************************************************************************* + + //************BYPASS MUXING LOGIC ***************************************** + + +endmodule +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM controller.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + + +//`include "includes_gen.v" + +module controller( + + input clk, + input reset_npu, + input done_mvm, + input done_mfu_0, + input done_mfu_1, + + + input[`INSTR_WIDTH-1:0] instruction, + output reg get_instr, + output reg[`INSTR_MEM_AWIDTH-1:0] get_instr_addr, + + input[`DRAM_DWIDTH-1:0] input_data_from_dram, + input[`ORF_DWIDTH-1:0] output_final_stage, + output reg[`DRAM_AWIDTH-1:0] dram_addr_wr, + output reg dram_write_enable, + output reg [`DRAM_DWIDTH-1:0] output_data_to_dram, + + //output reg start_mvu, + output reg start_mv_mul, + output reg start_mfu_0, + output reg start_mfu_1, + //output reg reset_mvu, + output reg in_data_available_mfu_0, + output reg in_data_available_mfu_1, + + output reg[1:0] activation, + output reg[1:0] operation, + + //FOR MVU IO + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_0, + output reg vrf_readn_enable_mvu_0, + output reg vrf_wr_enable_mvu_0, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_1, + output reg vrf_readn_enable_mvu_1, + output reg vrf_wr_enable_mvu_1, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_2, + output reg vrf_readn_enable_mvu_2, + output reg vrf_wr_enable_mvu_2, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_3, + output reg vrf_readn_enable_mvu_3, + output reg vrf_wr_enable_mvu_3, + + + output reg[`VRF_AWIDTH-1:0] vrf_addr_read, + output reg[`VRF_AWIDTH-1:0] vrf_addr_wr, //********************* + + //FOR MFU STAGE -0 + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_add_0, + output reg vrf_readn_enable_mfu_add_0, + output reg vrf_wr_enable_mfu_add_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_add_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_add_0, + + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_mul_0, + output reg vrf_readn_enable_mfu_mul_0, + output reg vrf_wr_enable_mfu_mul_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_mul_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_mul_0, + // + + //FOR MFU STAGE -1 + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_add_1, + output reg vrf_readn_enable_mfu_add_1, + output reg vrf_wr_enable_mfu_add_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_add_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_add_1, + + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_mul_1, + output reg vrf_readn_enable_mfu_mul_1, + output reg vrf_wr_enable_mfu_mul_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_mul_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_mul_1, + + //VRF MUXED + input[`ORF_DWIDTH-1:0] vrf_muxed_out_data_dram, + output reg[`ORF_AWIDTH-1:0] vrf_muxed_wr_addr_dram, + output reg[`ORF_AWIDTH-1:0] vrf_muxed_read_addr, + output reg vrf_muxed_wr_enable_dram, + output reg vrf_muxed_readn_enable, + // + + output reg[`MAX_VRF_DWIDTH-1:0] vrf_in_data, + + output mvu_or_vrf_mux_select, + + //MRF IO PORTS + output reg[`MRF_AWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_addr_wr, + output reg[`NUM_LDPES*`NUM_TILES-1:0] mrf_wr_enable, //NOTE: LOG(NUM_LDPES) = TARGET_OP_WIDTH + output reg[`MRF_DWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_in_data, + + output reg[`NUM_TILES*`NUM_LDPES-1:0] mrf_we_for_dram, + output reg [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram, + input [`NUM_TILES*`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram, + // + + //BYPASS SIGNALS + output[`TARGET_OP_WIDTH-1:0] dstn_id +); + + wire[`OPCODE_WIDTH-1:0] opcode; + wire[`VRF_AWIDTH-1:0] op1_address; + wire[`VRF_AWIDTH-1:0] op2_address; + wire[`VRF_AWIDTH-1:0] dstn_address; + wire[`TARGET_OP_WIDTH-1:0] src1_id; + //wire[`TARGET_OP_WIDTH-1:0] dstn_id; + + reg[1:0] state; + + //NOTE - CORRECT NAMING FOR OPERANDS AND EXTRACTION SCHEME FOR YOUR PARTS OF INSTRUCTION + assign op1_address = instruction[3*`VRF_AWIDTH+(`TARGET_OP_WIDTH)-1:(2*`VRF_AWIDTH) +(`TARGET_OP_WIDTH)]; + assign op2_address = instruction[2*`VRF_AWIDTH+`TARGET_OP_WIDTH-1:`VRF_AWIDTH+`TARGET_OP_WIDTH]; + assign dstn_address = instruction[`VRF_AWIDTH-1:0]; + assign opcode = instruction[`INSTR_WIDTH-1:`INSTR_WIDTH-`OPCODE_WIDTH]; + assign src1_id = instruction[3*`VRF_AWIDTH+2*`TARGET_OP_WIDTH-1:3*`VRF_AWIDTH+`TARGET_OP_WIDTH]; //or can be called mem_id + assign dstn_id = instruction[`VRF_AWIDTH+`TARGET_OP_WIDTH-1:`VRF_AWIDTH];//LSB for dram_write bypass + + assign mvu_or_vrf_mux_select = (op2_address!={`VRF_AWIDTH{1'b0}}); //UNUSED BIT FOR MFU OPERATIONS + + + //TODO - MAKE THIS SEQUENTIAL LOGIC - DONE + always@(posedge clk) begin + + if(reset_npu == 1'b1) begin + //reset_mvu<=1'b1; + //start_mvu<=1'b0; + get_instr<=1'b0; + + get_instr_addr<=0; + + start_mv_mul <= 1'b0; + + in_data_available_mfu_0 <= 1'b0; + start_mfu_0 <= 1'b0; + + in_data_available_mfu_1 <= 1'b0; + start_mfu_1 <= 1'b0; + dram_write_enable <= 1'b0; + mrf_wr_enable<='d0; + + + vrf_wr_enable_mvu_0<=1'b0; + vrf_readn_enable_mvu_0 <= 1'b0; + + + vrf_wr_enable_mvu_1<=1'b0; + vrf_readn_enable_mvu_1 <= 1'b0; + + + vrf_wr_enable_mvu_2<=1'b0; + vrf_readn_enable_mvu_2 <= 1'b0; + + + vrf_wr_enable_mvu_3<=1'b0; + vrf_readn_enable_mvu_3 <= 1'b0; + + + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + + dram_addr_wr<=9'd0; + vrf_addr_wr <= 9'd0; + //vrf_addr_wr_mvu_1 <= 0; + vrf_addr_wr_mfu_add_0 <= 9'd0; + vrf_addr_wr_mfu_mul_0 <= 9'd0; + vrf_addr_wr_mfu_add_1 <= 9'd0; + vrf_addr_wr_mfu_mul_1 <= 9'd0; + + vrf_addr_read <= 9'd0; + //vrf_addr_read_mvu_1 <= 0; + vrf_addr_read_mfu_add_0 <= 9'd0; + vrf_addr_read_mfu_mul_0 <= 9'd0; + vrf_addr_read_mfu_add_1 <= 9'd0; + vrf_addr_read_mfu_mul_1 <= 9'd0; + + + //vrf_muxed_wr_addr_dram <= 0; + //vrf_muxed_read_addr <= 0; + vrf_muxed_wr_enable_dram <= 1'b0; + vrf_muxed_readn_enable <= 1'b0; + + // orf_addr_increment<=1'b0; + + mrf_addr_wr <= 9'd0; + + state <= 0; + end + else begin + if(state==0) begin //FETCH + get_instr <= 1'b0; + state <= 1; + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable <= 1'b0; + mrf_wr_enable <= 0; + end + else if(state==1) begin //DECODE + case(opcode) + `V_WR: begin + state <= 2; + get_instr<=0; + //get_instr_addr<=get_instr_addr+1'b1; + case(src1_id) + `VRF_0: begin vrf_wr_enable_mvu_0 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_1: begin vrf_wr_enable_mvu_1 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_2: begin vrf_wr_enable_mvu_2 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_3: begin vrf_wr_enable_mvu_3 <= 1'b0; + vrf_addr_wr <= op1_address; + end + + `VRF_4: begin vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_addr_wr_mfu_add_0 <= op1_address; + end + + `VRF_5: begin vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_addr_wr_mfu_mul_0 <= op1_address; + end + + `VRF_6: begin vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_addr_wr_mfu_add_1 <= op1_address; + end + + `VRF_7: begin + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_addr_wr_mfu_mul_1 <= op1_address; + end + + `VRF_MUXED: begin + vrf_muxed_wr_enable_dram <= 1'b0; + vrf_muxed_wr_addr_dram <= op1_address; + end + + default: begin + vrf_wr_enable_mvu_0 <= 1'bX; + output_data_to_dram <= 'd0; + end + + endcase + + dram_addr_wr <= dstn_address; + dram_write_enable <= 1'b1; + end + `M_WR: begin + state <= 2; + get_instr<=0; + + case(src1_id) + `MRF_0: begin mrf_we_for_dram[0] <= 1'b0; + mrf_addr_for_dram[1*`MRF_AWIDTH-1:0*`MRF_AWIDTH] <= op1_address; + end + `MRF_1: begin mrf_we_for_dram[1] <= 1'b0; + mrf_addr_for_dram[2*`MRF_AWIDTH-1:1*`MRF_AWIDTH] <= op1_address; + end + `MRF_2: begin mrf_we_for_dram[2] <= 1'b0; + mrf_addr_for_dram[3*`MRF_AWIDTH-1:2*`MRF_AWIDTH] <= op1_address; + end + `MRF_3: begin mrf_we_for_dram[3] <= 1'b0; + mrf_addr_for_dram[4*`MRF_AWIDTH-1:3*`MRF_AWIDTH] <= op1_address; + end + `MRF_4: begin mrf_we_for_dram[4] <= 1'b0; + mrf_addr_for_dram[5*`MRF_AWIDTH-1:4*`MRF_AWIDTH] <= op1_address; + end + `MRF_5: begin mrf_we_for_dram[5] <= 1'b0; + mrf_addr_for_dram[6*`MRF_AWIDTH-1:5*`MRF_AWIDTH] <= op1_address; + end + `MRF_6: begin mrf_we_for_dram[6] <= 1'b0; + mrf_addr_for_dram[7*`MRF_AWIDTH-1:6*`MRF_AWIDTH] <= op1_address; + end + `MRF_7: begin mrf_we_for_dram[7] <= 1'b0; + mrf_addr_for_dram[8*`MRF_AWIDTH-1:7*`MRF_AWIDTH] <= op1_address; + end + `MRF_8: begin mrf_we_for_dram[8] <= 1'b0; + mrf_addr_for_dram[9*`MRF_AWIDTH-1:8*`MRF_AWIDTH] <= op1_address; + end + `MRF_9: begin mrf_we_for_dram[9] <= 1'b0; + mrf_addr_for_dram[10*`MRF_AWIDTH-1:9*`MRF_AWIDTH] <= op1_address; + end + `MRF_10: begin mrf_we_for_dram[10] <= 1'b0; + mrf_addr_for_dram[11*`MRF_AWIDTH-1:10*`MRF_AWIDTH] <= op1_address; + end + `MRF_11: begin mrf_we_for_dram[11] <= 1'b0; + mrf_addr_for_dram[12*`MRF_AWIDTH-1:11*`MRF_AWIDTH] <= op1_address; + end + `MRF_12: begin mrf_we_for_dram[12] <= 1'b0; + mrf_addr_for_dram[13*`MRF_AWIDTH-1:12*`MRF_AWIDTH] <= op1_address; + end + `MRF_13: begin mrf_we_for_dram[13] <= 1'b0; + mrf_addr_for_dram[14*`MRF_AWIDTH-1:13*`MRF_AWIDTH] <= op1_address; + end + `MRF_14: begin mrf_we_for_dram[14] <= 1'b0; + mrf_addr_for_dram[15*`MRF_AWIDTH-1:14*`MRF_AWIDTH] <= op1_address; + end + `MRF_15: begin mrf_we_for_dram[15] <= 1'b0; + mrf_addr_for_dram[16*`MRF_AWIDTH-1:15*`MRF_AWIDTH] <= op1_address; + end + `MRF_16: begin mrf_we_for_dram[16] <= 1'b0; + mrf_addr_for_dram[17*`MRF_AWIDTH-1:16*`MRF_AWIDTH] <= op1_address; + end + `MRF_17: begin mrf_we_for_dram[17] <= 1'b0; + mrf_addr_for_dram[18*`MRF_AWIDTH-1:17*`MRF_AWIDTH] <= op1_address; + end + `MRF_18: begin mrf_we_for_dram[18] <= 1'b0; + mrf_addr_for_dram[19*`MRF_AWIDTH-1:18*`MRF_AWIDTH] <= op1_address; + end + `MRF_19: begin mrf_we_for_dram[19] <= 1'b0; + mrf_addr_for_dram[20*`MRF_AWIDTH-1:19*`MRF_AWIDTH] <= op1_address; + end + `MRF_20: begin mrf_we_for_dram[20] <= 1'b0; + mrf_addr_for_dram[21*`MRF_AWIDTH-1:20*`MRF_AWIDTH] <= op1_address; + end + `MRF_21: begin mrf_we_for_dram[21] <= 1'b0; + mrf_addr_for_dram[22*`MRF_AWIDTH-1:21*`MRF_AWIDTH] <= op1_address; + end + `MRF_22: begin mrf_we_for_dram[22] <= 1'b0; + mrf_addr_for_dram[23*`MRF_AWIDTH-1:22*`MRF_AWIDTH] <= op1_address; + end + `MRF_23: begin mrf_we_for_dram[23] <= 1'b0; + mrf_addr_for_dram[24*`MRF_AWIDTH-1:23*`MRF_AWIDTH] <= op1_address; + end + `MRF_24: begin mrf_we_for_dram[24] <= 1'b0; + mrf_addr_for_dram[25*`MRF_AWIDTH-1:24*`MRF_AWIDTH] <= op1_address; + end + `MRF_25: begin mrf_we_for_dram[25] <= 1'b0; + mrf_addr_for_dram[26*`MRF_AWIDTH-1:25*`MRF_AWIDTH] <= op1_address; + end + `MRF_26: begin mrf_we_for_dram[26] <= 1'b0; + mrf_addr_for_dram[27*`MRF_AWIDTH-1:26*`MRF_AWIDTH] <= op1_address; + end + `MRF_27: begin mrf_we_for_dram[27] <= 1'b0; + mrf_addr_for_dram[28*`MRF_AWIDTH-1:27*`MRF_AWIDTH] <= op1_address; + end + `MRF_28: begin mrf_we_for_dram[28] <= 1'b0; + mrf_addr_for_dram[29*`MRF_AWIDTH-1:28*`MRF_AWIDTH] <= op1_address; + end + `MRF_29: begin mrf_we_for_dram[29] <= 1'b0; + mrf_addr_for_dram[30*`MRF_AWIDTH-1:29*`MRF_AWIDTH] <= op1_address; + end + `MRF_30: begin mrf_we_for_dram[30] <= 1'b0; + mrf_addr_for_dram[31*`MRF_AWIDTH-1:30*`MRF_AWIDTH] <= op1_address; + end + `MRF_31: begin mrf_we_for_dram[31] <= 1'b0; + mrf_addr_for_dram[32*`MRF_AWIDTH-1:31*`MRF_AWIDTH] <= op1_address; + end + `MRF_32: begin mrf_we_for_dram[32] <= 1'b0; + mrf_addr_for_dram[33*`MRF_AWIDTH-1:32*`MRF_AWIDTH] <= op1_address; + end + `MRF_33: begin mrf_we_for_dram[33] <= 1'b0; + mrf_addr_for_dram[34*`MRF_AWIDTH-1:33*`MRF_AWIDTH] <= op1_address; + end + `MRF_34: begin mrf_we_for_dram[34] <= 1'b0; + mrf_addr_for_dram[35*`MRF_AWIDTH-1:34*`MRF_AWIDTH] <= op1_address; + end + `MRF_35: begin mrf_we_for_dram[35] <= 1'b0; + mrf_addr_for_dram[36*`MRF_AWIDTH-1:35*`MRF_AWIDTH] <= op1_address; + end + `MRF_36: begin mrf_we_for_dram[36] <= 1'b0; + mrf_addr_for_dram[37*`MRF_AWIDTH-1:36*`MRF_AWIDTH] <= op1_address; + end + `MRF_37: begin mrf_we_for_dram[37] <= 1'b0; + mrf_addr_for_dram[38*`MRF_AWIDTH-1:37*`MRF_AWIDTH] <= op1_address; + end + `MRF_38: begin mrf_we_for_dram[38] <= 1'b0; + mrf_addr_for_dram[39*`MRF_AWIDTH-1:38*`MRF_AWIDTH] <= op1_address; + end + `MRF_39: begin mrf_we_for_dram[39] <= 1'b0; + mrf_addr_for_dram[40*`MRF_AWIDTH-1:39*`MRF_AWIDTH] <= op1_address; + end + `MRF_40: begin mrf_we_for_dram[40] <= 1'b0; + mrf_addr_for_dram[41*`MRF_AWIDTH-1:40*`MRF_AWIDTH] <= op1_address; + end + `MRF_41: begin mrf_we_for_dram[41] <= 1'b0; + mrf_addr_for_dram[42*`MRF_AWIDTH-1:41*`MRF_AWIDTH] <= op1_address; + end + `MRF_42: begin mrf_we_for_dram[42] <= 1'b0; + mrf_addr_for_dram[43*`MRF_AWIDTH-1:42*`MRF_AWIDTH] <= op1_address; + end + `MRF_43: begin mrf_we_for_dram[43] <= 1'b0; + mrf_addr_for_dram[44*`MRF_AWIDTH-1:43*`MRF_AWIDTH] <= op1_address; + end + `MRF_44: begin mrf_we_for_dram[44] <= 1'b0; + mrf_addr_for_dram[45*`MRF_AWIDTH-1:44*`MRF_AWIDTH] <= op1_address; + end + `MRF_45: begin mrf_we_for_dram[45] <= 1'b0; + mrf_addr_for_dram[46*`MRF_AWIDTH-1:45*`MRF_AWIDTH] <= op1_address; + end + `MRF_46: begin mrf_we_for_dram[46] <= 1'b0; + mrf_addr_for_dram[47*`MRF_AWIDTH-1:46*`MRF_AWIDTH] <= op1_address; + end + `MRF_47: begin mrf_we_for_dram[47] <= 1'b0; + mrf_addr_for_dram[48*`MRF_AWIDTH-1:47*`MRF_AWIDTH] <= op1_address; + end + `MRF_48: begin mrf_we_for_dram[48] <= 1'b0; + mrf_addr_for_dram[49*`MRF_AWIDTH-1:48*`MRF_AWIDTH] <= op1_address; + end + `MRF_49: begin mrf_we_for_dram[49] <= 1'b0; + mrf_addr_for_dram[50*`MRF_AWIDTH-1:49*`MRF_AWIDTH] <= op1_address; + end + `MRF_50: begin mrf_we_for_dram[50] <= 1'b0; + mrf_addr_for_dram[51*`MRF_AWIDTH-1:50*`MRF_AWIDTH] <= op1_address; + end + `MRF_51: begin mrf_we_for_dram[51] <= 1'b0; + mrf_addr_for_dram[52*`MRF_AWIDTH-1:51*`MRF_AWIDTH] <= op1_address; + end + `MRF_52: begin mrf_we_for_dram[52] <= 1'b0; + mrf_addr_for_dram[53*`MRF_AWIDTH-1:52*`MRF_AWIDTH] <= op1_address; + end + `MRF_53: begin mrf_we_for_dram[53] <= 1'b0; + mrf_addr_for_dram[54*`MRF_AWIDTH-1:53*`MRF_AWIDTH] <= op1_address; + end + `MRF_54: begin mrf_we_for_dram[54] <= 1'b0; + mrf_addr_for_dram[55*`MRF_AWIDTH-1:54*`MRF_AWIDTH] <= op1_address; + end + `MRF_55: begin mrf_we_for_dram[55] <= 1'b0; + mrf_addr_for_dram[56*`MRF_AWIDTH-1:55*`MRF_AWIDTH] <= op1_address; + end + `MRF_56: begin mrf_we_for_dram[56] <= 1'b0; + mrf_addr_for_dram[57*`MRF_AWIDTH-1:56*`MRF_AWIDTH] <= op1_address; + end + `MRF_57: begin mrf_we_for_dram[57] <= 1'b0; + mrf_addr_for_dram[58*`MRF_AWIDTH-1:57*`MRF_AWIDTH] <= op1_address; + end + `MRF_58: begin mrf_we_for_dram[58] <= 1'b0; + mrf_addr_for_dram[59*`MRF_AWIDTH-1:58*`MRF_AWIDTH] <= op1_address; + end + `MRF_59: begin mrf_we_for_dram[59] <= 1'b0; + mrf_addr_for_dram[60*`MRF_AWIDTH-1:59*`MRF_AWIDTH] <= op1_address; + end + `MRF_60: begin mrf_we_for_dram[60] <= 1'b0; + mrf_addr_for_dram[61*`MRF_AWIDTH-1:60*`MRF_AWIDTH] <= op1_address; + end + `MRF_61: begin mrf_we_for_dram[61] <= 1'b0; + mrf_addr_for_dram[62*`MRF_AWIDTH-1:61*`MRF_AWIDTH] <= op1_address; + end + `MRF_62: begin mrf_we_for_dram[62] <= 1'b0; + mrf_addr_for_dram[63*`MRF_AWIDTH-1:62*`MRF_AWIDTH] <= op1_address; + end + `MRF_63: begin mrf_we_for_dram[63] <= 1'b0; + mrf_addr_for_dram[64*`MRF_AWIDTH-1:63*`MRF_AWIDTH] <= op1_address; + end + `MRF_64: begin mrf_we_for_dram[64] <= 1'b0; + mrf_addr_for_dram[65*`MRF_AWIDTH-1:64*`MRF_AWIDTH] <= op1_address; + end + `MRF_65: begin mrf_we_for_dram[65] <= 1'b0; + mrf_addr_for_dram[66*`MRF_AWIDTH-1:65*`MRF_AWIDTH] <= op1_address; + end + `MRF_66: begin mrf_we_for_dram[66] <= 1'b0; + mrf_addr_for_dram[67*`MRF_AWIDTH-1:66*`MRF_AWIDTH] <= op1_address; + end + `MRF_67: begin mrf_we_for_dram[67] <= 1'b0; + mrf_addr_for_dram[68*`MRF_AWIDTH-1:67*`MRF_AWIDTH] <= op1_address; + end + `MRF_68: begin mrf_we_for_dram[68] <= 1'b0; + mrf_addr_for_dram[69*`MRF_AWIDTH-1:68*`MRF_AWIDTH] <= op1_address; + end + `MRF_69: begin mrf_we_for_dram[69] <= 1'b0; + mrf_addr_for_dram[70*`MRF_AWIDTH-1:69*`MRF_AWIDTH] <= op1_address; + end + `MRF_70: begin mrf_we_for_dram[70] <= 1'b0; + mrf_addr_for_dram[71*`MRF_AWIDTH-1:70*`MRF_AWIDTH] <= op1_address; + end + `MRF_71: begin mrf_we_for_dram[71] <= 1'b0; + mrf_addr_for_dram[72*`MRF_AWIDTH-1:71*`MRF_AWIDTH] <= op1_address; + end + `MRF_72: begin mrf_we_for_dram[72] <= 1'b0; + mrf_addr_for_dram[73*`MRF_AWIDTH-1:72*`MRF_AWIDTH] <= op1_address; + end + `MRF_73: begin mrf_we_for_dram[73] <= 1'b0; + mrf_addr_for_dram[74*`MRF_AWIDTH-1:73*`MRF_AWIDTH] <= op1_address; + end + `MRF_74: begin mrf_we_for_dram[74] <= 1'b0; + mrf_addr_for_dram[75*`MRF_AWIDTH-1:74*`MRF_AWIDTH] <= op1_address; + end + `MRF_75: begin mrf_we_for_dram[75] <= 1'b0; + mrf_addr_for_dram[76*`MRF_AWIDTH-1:75*`MRF_AWIDTH] <= op1_address; + end + `MRF_76: begin mrf_we_for_dram[76] <= 1'b0; + mrf_addr_for_dram[77*`MRF_AWIDTH-1:76*`MRF_AWIDTH] <= op1_address; + end + `MRF_77: begin mrf_we_for_dram[77] <= 1'b0; + mrf_addr_for_dram[78*`MRF_AWIDTH-1:77*`MRF_AWIDTH] <= op1_address; + end + `MRF_78: begin mrf_we_for_dram[78] <= 1'b0; + mrf_addr_for_dram[79*`MRF_AWIDTH-1:78*`MRF_AWIDTH] <= op1_address; + end + `MRF_79: begin mrf_we_for_dram[79] <= 1'b0; + mrf_addr_for_dram[80*`MRF_AWIDTH-1:79*`MRF_AWIDTH] <= op1_address; + end + `MRF_80: begin mrf_we_for_dram[80] <= 1'b0; + mrf_addr_for_dram[81*`MRF_AWIDTH-1:80*`MRF_AWIDTH] <= op1_address; + end + `MRF_81: begin mrf_we_for_dram[81] <= 1'b0; + mrf_addr_for_dram[82*`MRF_AWIDTH-1:81*`MRF_AWIDTH] <= op1_address; + end + `MRF_82: begin mrf_we_for_dram[82] <= 1'b0; + mrf_addr_for_dram[83*`MRF_AWIDTH-1:82*`MRF_AWIDTH] <= op1_address; + end + `MRF_83: begin mrf_we_for_dram[83] <= 1'b0; + mrf_addr_for_dram[84*`MRF_AWIDTH-1:83*`MRF_AWIDTH] <= op1_address; + end + `MRF_84: begin mrf_we_for_dram[84] <= 1'b0; + mrf_addr_for_dram[85*`MRF_AWIDTH-1:84*`MRF_AWIDTH] <= op1_address; + end + `MRF_85: begin mrf_we_for_dram[85] <= 1'b0; + mrf_addr_for_dram[86*`MRF_AWIDTH-1:85*`MRF_AWIDTH] <= op1_address; + end + `MRF_86: begin mrf_we_for_dram[86] <= 1'b0; + mrf_addr_for_dram[87*`MRF_AWIDTH-1:86*`MRF_AWIDTH] <= op1_address; + end + `MRF_87: begin mrf_we_for_dram[87] <= 1'b0; + mrf_addr_for_dram[88*`MRF_AWIDTH-1:87*`MRF_AWIDTH] <= op1_address; + end + `MRF_88: begin mrf_we_for_dram[88] <= 1'b0; + mrf_addr_for_dram[89*`MRF_AWIDTH-1:88*`MRF_AWIDTH] <= op1_address; + end + `MRF_89: begin mrf_we_for_dram[89] <= 1'b0; + mrf_addr_for_dram[90*`MRF_AWIDTH-1:89*`MRF_AWIDTH] <= op1_address; + end + `MRF_90: begin mrf_we_for_dram[90] <= 1'b0; + mrf_addr_for_dram[91*`MRF_AWIDTH-1:90*`MRF_AWIDTH] <= op1_address; + end + `MRF_91: begin mrf_we_for_dram[91] <= 1'b0; + mrf_addr_for_dram[92*`MRF_AWIDTH-1:91*`MRF_AWIDTH] <= op1_address; + end + `MRF_92: begin mrf_we_for_dram[92] <= 1'b0; + mrf_addr_for_dram[93*`MRF_AWIDTH-1:92*`MRF_AWIDTH] <= op1_address; + end + `MRF_93: begin mrf_we_for_dram[93] <= 1'b0; + mrf_addr_for_dram[94*`MRF_AWIDTH-1:93*`MRF_AWIDTH] <= op1_address; + end + `MRF_94: begin mrf_we_for_dram[94] <= 1'b0; + mrf_addr_for_dram[95*`MRF_AWIDTH-1:94*`MRF_AWIDTH] <= op1_address; + end + `MRF_95: begin mrf_we_for_dram[95] <= 1'b0; + mrf_addr_for_dram[96*`MRF_AWIDTH-1:95*`MRF_AWIDTH] <= op1_address; + end + `MRF_96: begin mrf_we_for_dram[96] <= 1'b0; + mrf_addr_for_dram[97*`MRF_AWIDTH-1:96*`MRF_AWIDTH] <= op1_address; + end + `MRF_97: begin mrf_we_for_dram[97] <= 1'b0; + mrf_addr_for_dram[98*`MRF_AWIDTH-1:97*`MRF_AWIDTH] <= op1_address; + end + `MRF_98: begin mrf_we_for_dram[98] <= 1'b0; + mrf_addr_for_dram[99*`MRF_AWIDTH-1:98*`MRF_AWIDTH] <= op1_address; + end + `MRF_99: begin mrf_we_for_dram[99] <= 1'b0; + mrf_addr_for_dram[100*`MRF_AWIDTH-1:99*`MRF_AWIDTH] <= op1_address; + end + `MRF_100: begin mrf_we_for_dram[100] <= 1'b0; + mrf_addr_for_dram[101*`MRF_AWIDTH-1:100*`MRF_AWIDTH] <= op1_address; + end + `MRF_101: begin mrf_we_for_dram[101] <= 1'b0; + mrf_addr_for_dram[102*`MRF_AWIDTH-1:101*`MRF_AWIDTH] <= op1_address; + end + `MRF_102: begin mrf_we_for_dram[102] <= 1'b0; + mrf_addr_for_dram[103*`MRF_AWIDTH-1:102*`MRF_AWIDTH] <= op1_address; + end + `MRF_103: begin mrf_we_for_dram[103] <= 1'b0; + mrf_addr_for_dram[104*`MRF_AWIDTH-1:103*`MRF_AWIDTH] <= op1_address; + end + `MRF_104: begin mrf_we_for_dram[104] <= 1'b0; + mrf_addr_for_dram[105*`MRF_AWIDTH-1:104*`MRF_AWIDTH] <= op1_address; + end + `MRF_105: begin mrf_we_for_dram[105] <= 1'b0; + mrf_addr_for_dram[106*`MRF_AWIDTH-1:105*`MRF_AWIDTH] <= op1_address; + end + `MRF_106: begin mrf_we_for_dram[106] <= 1'b0; + mrf_addr_for_dram[107*`MRF_AWIDTH-1:106*`MRF_AWIDTH] <= op1_address; + end + `MRF_107: begin mrf_we_for_dram[107] <= 1'b0; + mrf_addr_for_dram[108*`MRF_AWIDTH-1:107*`MRF_AWIDTH] <= op1_address; + end + `MRF_108: begin mrf_we_for_dram[108] <= 1'b0; + mrf_addr_for_dram[109*`MRF_AWIDTH-1:108*`MRF_AWIDTH] <= op1_address; + end + `MRF_109: begin mrf_we_for_dram[109] <= 1'b0; + mrf_addr_for_dram[110*`MRF_AWIDTH-1:109*`MRF_AWIDTH] <= op1_address; + end + `MRF_110: begin mrf_we_for_dram[110] <= 1'b0; + mrf_addr_for_dram[111*`MRF_AWIDTH-1:110*`MRF_AWIDTH] <= op1_address; + end + `MRF_111: begin mrf_we_for_dram[111] <= 1'b0; + mrf_addr_for_dram[112*`MRF_AWIDTH-1:111*`MRF_AWIDTH] <= op1_address; + end + `MRF_112: begin mrf_we_for_dram[112] <= 1'b0; + mrf_addr_for_dram[113*`MRF_AWIDTH-1:112*`MRF_AWIDTH] <= op1_address; + end + `MRF_113: begin mrf_we_for_dram[113] <= 1'b0; + mrf_addr_for_dram[114*`MRF_AWIDTH-1:113*`MRF_AWIDTH] <= op1_address; + end + `MRF_114: begin mrf_we_for_dram[114] <= 1'b0; + mrf_addr_for_dram[115*`MRF_AWIDTH-1:114*`MRF_AWIDTH] <= op1_address; + end + `MRF_115: begin mrf_we_for_dram[115] <= 1'b0; + mrf_addr_for_dram[116*`MRF_AWIDTH-1:115*`MRF_AWIDTH] <= op1_address; + end + `MRF_116: begin mrf_we_for_dram[116] <= 1'b0; + mrf_addr_for_dram[117*`MRF_AWIDTH-1:116*`MRF_AWIDTH] <= op1_address; + end + `MRF_117: begin mrf_we_for_dram[117] <= 1'b0; + mrf_addr_for_dram[118*`MRF_AWIDTH-1:117*`MRF_AWIDTH] <= op1_address; + end + `MRF_118: begin mrf_we_for_dram[118] <= 1'b0; + mrf_addr_for_dram[119*`MRF_AWIDTH-1:118*`MRF_AWIDTH] <= op1_address; + end + `MRF_119: begin mrf_we_for_dram[119] <= 1'b0; + mrf_addr_for_dram[120*`MRF_AWIDTH-1:119*`MRF_AWIDTH] <= op1_address; + end + `MRF_120: begin mrf_we_for_dram[120] <= 1'b0; + mrf_addr_for_dram[121*`MRF_AWIDTH-1:120*`MRF_AWIDTH] <= op1_address; + end + `MRF_121: begin mrf_we_for_dram[121] <= 1'b0; + mrf_addr_for_dram[122*`MRF_AWIDTH-1:121*`MRF_AWIDTH] <= op1_address; + end + `MRF_122: begin mrf_we_for_dram[122] <= 1'b0; + mrf_addr_for_dram[123*`MRF_AWIDTH-1:122*`MRF_AWIDTH] <= op1_address; + end + `MRF_123: begin mrf_we_for_dram[123] <= 1'b0; + mrf_addr_for_dram[124*`MRF_AWIDTH-1:123*`MRF_AWIDTH] <= op1_address; + end + `MRF_124: begin mrf_we_for_dram[124] <= 1'b0; + mrf_addr_for_dram[125*`MRF_AWIDTH-1:124*`MRF_AWIDTH] <= op1_address; + end + `MRF_125: begin mrf_we_for_dram[125] <= 1'b0; + mrf_addr_for_dram[126*`MRF_AWIDTH-1:125*`MRF_AWIDTH] <= op1_address; + end + `MRF_126: begin mrf_we_for_dram[126] <= 1'b0; + mrf_addr_for_dram[127*`MRF_AWIDTH-1:126*`MRF_AWIDTH] <= op1_address; + end + `MRF_127: begin mrf_we_for_dram[127] <= 1'b0; + mrf_addr_for_dram[128*`MRF_AWIDTH-1:127*`MRF_AWIDTH] <= op1_address; + end + default: begin mrf_we_for_dram <= 'd0; + mrf_addr_for_dram <= 'd0; + end + endcase + + dram_addr_wr <= dstn_address; + dram_write_enable <= 1'b1; + end + `V_RD: begin + state <= 2; + get_instr<=0; + dram_addr_wr <= op1_address; + dram_write_enable <= 1'b0; + + end + //CHANGE NAMING CONVENTION FOR WRITE AND READ TO STORE AND LOAD + //ADD COMMENTS FOR SRC AND DESTINATION + `M_RD: begin + state <= 2; + get_instr<=0; + dram_addr_wr <= op1_address; + dram_write_enable <= 1'b0; + end + `MV_MUL: begin + //op1_id is don't care for this instructions + + state <= 2; + get_instr<=1'b0; + start_mv_mul <= 1'b1; + mrf_addr_wr[(1*`MRF_AWIDTH)-1:0*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(2*`MRF_AWIDTH)-1:1*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(3*`MRF_AWIDTH)-1:2*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(4*`MRF_AWIDTH)-1:3*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(5*`MRF_AWIDTH)-1:4*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(6*`MRF_AWIDTH)-1:5*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(7*`MRF_AWIDTH)-1:6*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(8*`MRF_AWIDTH)-1:7*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(9*`MRF_AWIDTH)-1:8*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(10*`MRF_AWIDTH)-1:9*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(11*`MRF_AWIDTH)-1:10*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(12*`MRF_AWIDTH)-1:11*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(13*`MRF_AWIDTH)-1:12*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(14*`MRF_AWIDTH)-1:13*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(15*`MRF_AWIDTH)-1:14*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(16*`MRF_AWIDTH)-1:15*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(17*`MRF_AWIDTH)-1:16*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(18*`MRF_AWIDTH)-1:17*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(19*`MRF_AWIDTH)-1:18*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(20*`MRF_AWIDTH)-1:19*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(21*`MRF_AWIDTH)-1:20*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(22*`MRF_AWIDTH)-1:21*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(23*`MRF_AWIDTH)-1:22*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(24*`MRF_AWIDTH)-1:23*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(25*`MRF_AWIDTH)-1:24*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(26*`MRF_AWIDTH)-1:25*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(27*`MRF_AWIDTH)-1:26*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(28*`MRF_AWIDTH)-1:27*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(29*`MRF_AWIDTH)-1:28*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(30*`MRF_AWIDTH)-1:29*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(31*`MRF_AWIDTH)-1:30*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(32*`MRF_AWIDTH)-1:31*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(33*`MRF_AWIDTH)-1:32*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(34*`MRF_AWIDTH)-1:33*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(35*`MRF_AWIDTH)-1:34*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(36*`MRF_AWIDTH)-1:35*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(37*`MRF_AWIDTH)-1:36*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(38*`MRF_AWIDTH)-1:37*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(39*`MRF_AWIDTH)-1:38*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(40*`MRF_AWIDTH)-1:39*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(41*`MRF_AWIDTH)-1:40*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(42*`MRF_AWIDTH)-1:41*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(43*`MRF_AWIDTH)-1:42*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(44*`MRF_AWIDTH)-1:43*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(45*`MRF_AWIDTH)-1:44*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(46*`MRF_AWIDTH)-1:45*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(47*`MRF_AWIDTH)-1:46*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(48*`MRF_AWIDTH)-1:47*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(49*`MRF_AWIDTH)-1:48*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(50*`MRF_AWIDTH)-1:49*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(51*`MRF_AWIDTH)-1:50*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(52*`MRF_AWIDTH)-1:51*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(53*`MRF_AWIDTH)-1:52*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(54*`MRF_AWIDTH)-1:53*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(55*`MRF_AWIDTH)-1:54*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(56*`MRF_AWIDTH)-1:55*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(57*`MRF_AWIDTH)-1:56*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(58*`MRF_AWIDTH)-1:57*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(59*`MRF_AWIDTH)-1:58*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(60*`MRF_AWIDTH)-1:59*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(61*`MRF_AWIDTH)-1:60*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(62*`MRF_AWIDTH)-1:61*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(63*`MRF_AWIDTH)-1:62*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(64*`MRF_AWIDTH)-1:63*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(65*`MRF_AWIDTH)-1:64*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(66*`MRF_AWIDTH)-1:65*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(67*`MRF_AWIDTH)-1:66*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(68*`MRF_AWIDTH)-1:67*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(69*`MRF_AWIDTH)-1:68*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(70*`MRF_AWIDTH)-1:69*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(71*`MRF_AWIDTH)-1:70*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(72*`MRF_AWIDTH)-1:71*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(73*`MRF_AWIDTH)-1:72*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(74*`MRF_AWIDTH)-1:73*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(75*`MRF_AWIDTH)-1:74*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(76*`MRF_AWIDTH)-1:75*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(77*`MRF_AWIDTH)-1:76*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(78*`MRF_AWIDTH)-1:77*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(79*`MRF_AWIDTH)-1:78*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(80*`MRF_AWIDTH)-1:79*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(81*`MRF_AWIDTH)-1:80*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(82*`MRF_AWIDTH)-1:81*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(83*`MRF_AWIDTH)-1:82*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(84*`MRF_AWIDTH)-1:83*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(85*`MRF_AWIDTH)-1:84*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(86*`MRF_AWIDTH)-1:85*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(87*`MRF_AWIDTH)-1:86*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(88*`MRF_AWIDTH)-1:87*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(89*`MRF_AWIDTH)-1:88*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(90*`MRF_AWIDTH)-1:89*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(91*`MRF_AWIDTH)-1:90*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(92*`MRF_AWIDTH)-1:91*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(93*`MRF_AWIDTH)-1:92*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(94*`MRF_AWIDTH)-1:93*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(95*`MRF_AWIDTH)-1:94*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(96*`MRF_AWIDTH)-1:95*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(97*`MRF_AWIDTH)-1:96*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(98*`MRF_AWIDTH)-1:97*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(99*`MRF_AWIDTH)-1:98*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(100*`MRF_AWIDTH)-1:99*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(101*`MRF_AWIDTH)-1:100*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(102*`MRF_AWIDTH)-1:101*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(103*`MRF_AWIDTH)-1:102*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(104*`MRF_AWIDTH)-1:103*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(105*`MRF_AWIDTH)-1:104*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(106*`MRF_AWIDTH)-1:105*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(107*`MRF_AWIDTH)-1:106*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(108*`MRF_AWIDTH)-1:107*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(109*`MRF_AWIDTH)-1:108*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(110*`MRF_AWIDTH)-1:109*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(111*`MRF_AWIDTH)-1:110*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(112*`MRF_AWIDTH)-1:111*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(113*`MRF_AWIDTH)-1:112*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(114*`MRF_AWIDTH)-1:113*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(115*`MRF_AWIDTH)-1:114*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(116*`MRF_AWIDTH)-1:115*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(117*`MRF_AWIDTH)-1:116*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(118*`MRF_AWIDTH)-1:117*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(119*`MRF_AWIDTH)-1:118*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(120*`MRF_AWIDTH)-1:119*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(121*`MRF_AWIDTH)-1:120*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(122*`MRF_AWIDTH)-1:121*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(123*`MRF_AWIDTH)-1:122*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(124*`MRF_AWIDTH)-1:123*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(125*`MRF_AWIDTH)-1:124*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(126*`MRF_AWIDTH)-1:125*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(127*`MRF_AWIDTH)-1:126*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(128*`MRF_AWIDTH)-1:127*`MRF_AWIDTH] <= op1_address; + vrf_addr_read <= op2_address; + vrf_readn_enable_mvu_0 <= 1'b0; + vrf_readn_enable_mvu_1 <= 1'b0; + vrf_readn_enable_mvu_2 <= 1'b0; + vrf_readn_enable_mvu_3 <= 1'b0; + mrf_wr_enable <= 0; + end + `VV_ADD:begin + + //MFU_STAGE-0 DESIGNATED FOR ELTWISE ADD + state <= 2; + get_instr <= 1'b0; + operation <= `ELT_WISE_ADD; //NOTE - 2nd VRF INDEX IS FOR ADD UNITS ELT WISE + activation <= 0; + + case(src1_id) + + `VRF_4: begin + start_mfu_0 <= 1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + + in_data_available_mfu_0 <= 1'b1; + vrf_addr_read_mfu_add_0 <= op1_address; + vrf_readn_enable_mfu_add_0 <= 1'b0; + end + + + `VRF_6: begin + start_mfu_1 <= 1'b1; + in_data_available_mfu_1 <= 1'b1; + vrf_addr_read_mfu_add_1 <= op1_address; + vrf_readn_enable_mfu_add_1 <= 1'b0; + end + + + default: begin + start_mfu_0 <= 1'bX; + in_data_available_mfu_0 <= 1'b0; + vrf_addr_read_mfu_add_0 <= 9'd0; + vrf_readn_enable_mfu_add_0 <= 1'b0; + vrf_addr_read_mfu_add_1 <= 9'd0; + vrf_readn_enable_mfu_add_1 <= 1'b0; + end + + endcase + + end + `VV_SUB:begin + + //MFU_STAGE-0 DESIGNATED FOR ELTWISE ADD + state <= 2; + get_instr<=1'b0; + operation<=`ELT_WISE_ADD; //NOTE - 2nd VRF INDEX IS FOR ADD UNITS ELT WISE + + activation <= 1; + + case(src1_id) + + `VRF_4: begin + start_mfu_0 <= 1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + + in_data_available_mfu_0 <= 1'b1; + vrf_addr_read_mfu_add_0 <= op1_address; + vrf_readn_enable_mfu_add_0 <= 1'b0; + end + + + `VRF_6: begin + start_mfu_1 <= 1'b1; + in_data_available_mfu_1 <= 1'b1; + vrf_addr_read_mfu_add_1 <= op1_address; + vrf_readn_enable_mfu_add_1 <= 1'b0; + end + + + default: begin + start_mfu_0 <= 1'b0; + in_data_available_mfu_0 <= 1'b0; + vrf_addr_read_mfu_add_0 <= 9'd0; + vrf_readn_enable_mfu_add_0 <= 1'b0; + vrf_addr_read_mfu_add_1 <= 9'd0; + vrf_readn_enable_mfu_add_1 <= 1'b0; + end + + endcase + + end + `VV_MUL:begin + state <= 2; + get_instr<=1'b0; + + operation<=`ELT_WISE_MULTIPLY; //NOTE - 3RD VRF INDEX IS FOR ADD UNITS ELT WISE + case(src1_id) + + `VRF_5: begin + start_mfu_0 <= 1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + + in_data_available_mfu_0 <= 1'b1; + vrf_addr_read_mfu_mul_0 <= op1_address; + vrf_readn_enable_mfu_mul_0 <= 1'b0; + end + + `VRF_7: begin + start_mfu_1 <= 1'b1; + in_data_available_mfu_1 <= 1'b1; + vrf_addr_read_mfu_mul_1 <= op1_address; + vrf_readn_enable_mfu_mul_1 <= 1'b0; + end + + default: begin + start_mfu_0 <= 1'b0; + in_data_available_mfu_0 <= 1'b0; + vrf_addr_read_mfu_mul_0 <= 9'd0; + vrf_readn_enable_mfu_mul_0 <= 1'b0; + vrf_addr_read_mfu_mul_1 <= 9'd0; + vrf_readn_enable_mfu_mul_1 <= 1'b0; + end + + endcase + + end + `V_RELU:begin + + get_instr<=1'b0; + case(src1_id) + + `MFU_0: begin + start_mfu_0<=1'b1; + in_data_available_mfu_0<=1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + end + + `MFU_1: begin + start_mfu_1<=1'b1; + in_data_available_mfu_1<=1'b1; + end + + default: begin + start_mfu_0<=1'bX; + in_data_available_mfu_0<=1'bX; + end + + endcase + operation<=`ACTIVATION; + activation<=`RELU; + state <= 2; + + end + `V_SIGM:begin + + get_instr<=1'b0; + case(src1_id) + + `MFU_0: begin + start_mfu_0<=1'b1; + in_data_available_mfu_0<=1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + end + + `MFU_1: begin + start_mfu_1<=1'b1; + in_data_available_mfu_1<=1'b1; + end + + default: begin + start_mfu_0<=1'bX; + in_data_available_mfu_0<=1'bX; + end + + endcase + operation<=`ACTIVATION; + activation<=`SIGM; + state <= 2; + end + `V_TANH:begin + //dram_write_enable <= bypass_id[0]; + get_instr<=1'b0; + case(src1_id) + + `MFU_0: begin + start_mfu_0<=1'b1; + in_data_available_mfu_0<=1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + end + + `MFU_1: begin + start_mfu_1<=1'b1; + in_data_available_mfu_1<=1'b1; + end + + default: begin + start_mfu_0<=1'bX; + in_data_available_mfu_0<=1'bX; + end + + endcase + operation<=`ACTIVATION; + activation<=`TANH; + state <= 2; + + end + `END_CHAIN :begin + + start_mv_mul<=1'b0; + get_instr<=1'b0; + + in_data_available_mfu_0<=1'b0; + start_mfu_0<=1'b0; + + in_data_available_mfu_1<=1'b0; + start_mfu_1<=1'b0; + + mrf_wr_enable<=0; + + + vrf_wr_enable_mvu_0<='b0; + vrf_readn_enable_mvu_0 <= 'b0; + + + vrf_wr_enable_mvu_1<='b0; + vrf_readn_enable_mvu_1 <= 'b0; + + + vrf_wr_enable_mvu_2<='b0; + vrf_readn_enable_mvu_2 <= 'b0; + + + vrf_wr_enable_mvu_3<='b0; + vrf_readn_enable_mvu_3 <= 'b0; + + + vrf_wr_enable_mfu_add_0 <= 0; + vrf_wr_enable_mfu_mul_0 <= 0; + vrf_wr_enable_mfu_add_1 <= 0; + vrf_wr_enable_mfu_mul_1 <= 0; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_wr_addr_dram <= 1'b0; + + vrf_readn_enable_mfu_add_0 <= 0; + vrf_readn_enable_mfu_mul_0 <= 0; + vrf_readn_enable_mfu_add_1 <= 0; + vrf_readn_enable_mfu_mul_1 <= 0; + + //orf_addr_increment<=1'b0; + mrf_addr_wr <= 0; + dram_write_enable <= 1'b0; + state <= 1; + end + endcase + end + else begin //EXECUTE + + case(opcode) + `V_WR: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(src1_id) + + `VRF_0: begin + output_data_to_dram <= vrf_out_data_mvu_0; + end + `VRF_1: begin + output_data_to_dram <= vrf_out_data_mvu_1; + end + `VRF_2: begin + output_data_to_dram <= vrf_out_data_mvu_2; + end + `VRF_3: begin + output_data_to_dram <= vrf_out_data_mvu_3; + end + + `VRF_4: begin + output_data_to_dram <= vrf_out_data_mfu_add_0; + end + + `VRF_5: begin + output_data_to_dram <= vrf_out_data_mfu_mul_0; + end + + `VRF_6: begin + output_data_to_dram <= vrf_out_data_mfu_add_1; + end + + `VRF_7: begin + output_data_to_dram <= vrf_out_data_mfu_mul_1; + end + + `VRF_MUXED: begin + output_data_to_dram <= vrf_muxed_out_data_dram; + end + default: begin + output_data_to_dram <= 'd0; + end + endcase + + end + `M_WR: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(src1_id) + + `MRF_0: begin + output_data_to_dram <= mrf_outa_to_dram[1*`MRF_DWIDTH-1:0*`MRF_DWIDTH]; + end + `MRF_1: begin + output_data_to_dram <= mrf_outa_to_dram[2*`MRF_DWIDTH-1:1*`MRF_DWIDTH]; + end + `MRF_2: begin + output_data_to_dram <= mrf_outa_to_dram[3*`MRF_DWIDTH-1:2*`MRF_DWIDTH]; + end + `MRF_3: begin + output_data_to_dram <= mrf_outa_to_dram[4*`MRF_DWIDTH-1:3*`MRF_DWIDTH]; + end + `MRF_4: begin + output_data_to_dram <= mrf_outa_to_dram[5*`MRF_DWIDTH-1:4*`MRF_DWIDTH]; + end + `MRF_5: begin + output_data_to_dram <= mrf_outa_to_dram[6*`MRF_DWIDTH-1:5*`MRF_DWIDTH]; + end + `MRF_6: begin + output_data_to_dram <= mrf_outa_to_dram[7*`MRF_DWIDTH-1:6*`MRF_DWIDTH]; + end + `MRF_7: begin + output_data_to_dram <= mrf_outa_to_dram[8*`MRF_DWIDTH-1:7*`MRF_DWIDTH]; + end + `MRF_8: begin + output_data_to_dram <= mrf_outa_to_dram[9*`MRF_DWIDTH-1:8*`MRF_DWIDTH]; + end + `MRF_9: begin + output_data_to_dram <= mrf_outa_to_dram[10*`MRF_DWIDTH-1:9*`MRF_DWIDTH]; + end + `MRF_10: begin + output_data_to_dram <= mrf_outa_to_dram[11*`MRF_DWIDTH-1:10*`MRF_DWIDTH]; + end + `MRF_11: begin + output_data_to_dram <= mrf_outa_to_dram[12*`MRF_DWIDTH-1:11*`MRF_DWIDTH]; + end + `MRF_12: begin + output_data_to_dram <= mrf_outa_to_dram[13*`MRF_DWIDTH-1:12*`MRF_DWIDTH]; + end + `MRF_13: begin + output_data_to_dram <= mrf_outa_to_dram[14*`MRF_DWIDTH-1:13*`MRF_DWIDTH]; + end + `MRF_14: begin + output_data_to_dram <= mrf_outa_to_dram[15*`MRF_DWIDTH-1:14*`MRF_DWIDTH]; + end + `MRF_15: begin + output_data_to_dram <= mrf_outa_to_dram[16*`MRF_DWIDTH-1:15*`MRF_DWIDTH]; + end + `MRF_16: begin + output_data_to_dram <= mrf_outa_to_dram[17*`MRF_DWIDTH-1:16*`MRF_DWIDTH]; + end + `MRF_17: begin + output_data_to_dram <= mrf_outa_to_dram[18*`MRF_DWIDTH-1:17*`MRF_DWIDTH]; + end + `MRF_18: begin + output_data_to_dram <= mrf_outa_to_dram[19*`MRF_DWIDTH-1:18*`MRF_DWIDTH]; + end + `MRF_19: begin + output_data_to_dram <= mrf_outa_to_dram[20*`MRF_DWIDTH-1:19*`MRF_DWIDTH]; + end + `MRF_20: begin + output_data_to_dram <= mrf_outa_to_dram[21*`MRF_DWIDTH-1:20*`MRF_DWIDTH]; + end + `MRF_21: begin + output_data_to_dram <= mrf_outa_to_dram[22*`MRF_DWIDTH-1:21*`MRF_DWIDTH]; + end + `MRF_22: begin + output_data_to_dram <= mrf_outa_to_dram[23*`MRF_DWIDTH-1:22*`MRF_DWIDTH]; + end + `MRF_23: begin + output_data_to_dram <= mrf_outa_to_dram[24*`MRF_DWIDTH-1:23*`MRF_DWIDTH]; + end + `MRF_24: begin + output_data_to_dram <= mrf_outa_to_dram[25*`MRF_DWIDTH-1:24*`MRF_DWIDTH]; + end + `MRF_25: begin + output_data_to_dram <= mrf_outa_to_dram[26*`MRF_DWIDTH-1:25*`MRF_DWIDTH]; + end + `MRF_26: begin + output_data_to_dram <= mrf_outa_to_dram[27*`MRF_DWIDTH-1:26*`MRF_DWIDTH]; + end + `MRF_27: begin + output_data_to_dram <= mrf_outa_to_dram[28*`MRF_DWIDTH-1:27*`MRF_DWIDTH]; + end + `MRF_28: begin + output_data_to_dram <= mrf_outa_to_dram[29*`MRF_DWIDTH-1:28*`MRF_DWIDTH]; + end + `MRF_29: begin + output_data_to_dram <= mrf_outa_to_dram[30*`MRF_DWIDTH-1:29*`MRF_DWIDTH]; + end + `MRF_30: begin + output_data_to_dram <= mrf_outa_to_dram[31*`MRF_DWIDTH-1:30*`MRF_DWIDTH]; + end + `MRF_31: begin + output_data_to_dram <= mrf_outa_to_dram[32*`MRF_DWIDTH-1:31*`MRF_DWIDTH]; + end + `MRF_32: begin + output_data_to_dram <= mrf_outa_to_dram[33*`MRF_DWIDTH-1:32*`MRF_DWIDTH]; + end + `MRF_33: begin + output_data_to_dram <= mrf_outa_to_dram[34*`MRF_DWIDTH-1:33*`MRF_DWIDTH]; + end + `MRF_34: begin + output_data_to_dram <= mrf_outa_to_dram[35*`MRF_DWIDTH-1:34*`MRF_DWIDTH]; + end + `MRF_35: begin + output_data_to_dram <= mrf_outa_to_dram[36*`MRF_DWIDTH-1:35*`MRF_DWIDTH]; + end + `MRF_36: begin + output_data_to_dram <= mrf_outa_to_dram[37*`MRF_DWIDTH-1:36*`MRF_DWIDTH]; + end + `MRF_37: begin + output_data_to_dram <= mrf_outa_to_dram[38*`MRF_DWIDTH-1:37*`MRF_DWIDTH]; + end + `MRF_38: begin + output_data_to_dram <= mrf_outa_to_dram[39*`MRF_DWIDTH-1:38*`MRF_DWIDTH]; + end + `MRF_39: begin + output_data_to_dram <= mrf_outa_to_dram[40*`MRF_DWIDTH-1:39*`MRF_DWIDTH]; + end + `MRF_40: begin + output_data_to_dram <= mrf_outa_to_dram[41*`MRF_DWIDTH-1:40*`MRF_DWIDTH]; + end + `MRF_41: begin + output_data_to_dram <= mrf_outa_to_dram[42*`MRF_DWIDTH-1:41*`MRF_DWIDTH]; + end + `MRF_42: begin + output_data_to_dram <= mrf_outa_to_dram[43*`MRF_DWIDTH-1:42*`MRF_DWIDTH]; + end + `MRF_43: begin + output_data_to_dram <= mrf_outa_to_dram[44*`MRF_DWIDTH-1:43*`MRF_DWIDTH]; + end + `MRF_44: begin + output_data_to_dram <= mrf_outa_to_dram[45*`MRF_DWIDTH-1:44*`MRF_DWIDTH]; + end + `MRF_45: begin + output_data_to_dram <= mrf_outa_to_dram[46*`MRF_DWIDTH-1:45*`MRF_DWIDTH]; + end + `MRF_46: begin + output_data_to_dram <= mrf_outa_to_dram[47*`MRF_DWIDTH-1:46*`MRF_DWIDTH]; + end + `MRF_47: begin + output_data_to_dram <= mrf_outa_to_dram[48*`MRF_DWIDTH-1:47*`MRF_DWIDTH]; + end + `MRF_48: begin + output_data_to_dram <= mrf_outa_to_dram[49*`MRF_DWIDTH-1:48*`MRF_DWIDTH]; + end + `MRF_49: begin + output_data_to_dram <= mrf_outa_to_dram[50*`MRF_DWIDTH-1:49*`MRF_DWIDTH]; + end + `MRF_50: begin + output_data_to_dram <= mrf_outa_to_dram[51*`MRF_DWIDTH-1:50*`MRF_DWIDTH]; + end + `MRF_51: begin + output_data_to_dram <= mrf_outa_to_dram[52*`MRF_DWIDTH-1:51*`MRF_DWIDTH]; + end + `MRF_52: begin + output_data_to_dram <= mrf_outa_to_dram[53*`MRF_DWIDTH-1:52*`MRF_DWIDTH]; + end + `MRF_53: begin + output_data_to_dram <= mrf_outa_to_dram[54*`MRF_DWIDTH-1:53*`MRF_DWIDTH]; + end + `MRF_54: begin + output_data_to_dram <= mrf_outa_to_dram[55*`MRF_DWIDTH-1:54*`MRF_DWIDTH]; + end + `MRF_55: begin + output_data_to_dram <= mrf_outa_to_dram[56*`MRF_DWIDTH-1:55*`MRF_DWIDTH]; + end + `MRF_56: begin + output_data_to_dram <= mrf_outa_to_dram[57*`MRF_DWIDTH-1:56*`MRF_DWIDTH]; + end + `MRF_57: begin + output_data_to_dram <= mrf_outa_to_dram[58*`MRF_DWIDTH-1:57*`MRF_DWIDTH]; + end + `MRF_58: begin + output_data_to_dram <= mrf_outa_to_dram[59*`MRF_DWIDTH-1:58*`MRF_DWIDTH]; + end + `MRF_59: begin + output_data_to_dram <= mrf_outa_to_dram[60*`MRF_DWIDTH-1:59*`MRF_DWIDTH]; + end + `MRF_60: begin + output_data_to_dram <= mrf_outa_to_dram[61*`MRF_DWIDTH-1:60*`MRF_DWIDTH]; + end + `MRF_61: begin + output_data_to_dram <= mrf_outa_to_dram[62*`MRF_DWIDTH-1:61*`MRF_DWIDTH]; + end + `MRF_62: begin + output_data_to_dram <= mrf_outa_to_dram[63*`MRF_DWIDTH-1:62*`MRF_DWIDTH]; + end + `MRF_63: begin + output_data_to_dram <= mrf_outa_to_dram[64*`MRF_DWIDTH-1:63*`MRF_DWIDTH]; + end + `MRF_64: begin + output_data_to_dram <= mrf_outa_to_dram[65*`MRF_DWIDTH-1:64*`MRF_DWIDTH]; + end + `MRF_65: begin + output_data_to_dram <= mrf_outa_to_dram[66*`MRF_DWIDTH-1:65*`MRF_DWIDTH]; + end + `MRF_66: begin + output_data_to_dram <= mrf_outa_to_dram[67*`MRF_DWIDTH-1:66*`MRF_DWIDTH]; + end + `MRF_67: begin + output_data_to_dram <= mrf_outa_to_dram[68*`MRF_DWIDTH-1:67*`MRF_DWIDTH]; + end + `MRF_68: begin + output_data_to_dram <= mrf_outa_to_dram[69*`MRF_DWIDTH-1:68*`MRF_DWIDTH]; + end + `MRF_69: begin + output_data_to_dram <= mrf_outa_to_dram[70*`MRF_DWIDTH-1:69*`MRF_DWIDTH]; + end + `MRF_70: begin + output_data_to_dram <= mrf_outa_to_dram[71*`MRF_DWIDTH-1:70*`MRF_DWIDTH]; + end + `MRF_71: begin + output_data_to_dram <= mrf_outa_to_dram[72*`MRF_DWIDTH-1:71*`MRF_DWIDTH]; + end + `MRF_72: begin + output_data_to_dram <= mrf_outa_to_dram[73*`MRF_DWIDTH-1:72*`MRF_DWIDTH]; + end + `MRF_73: begin + output_data_to_dram <= mrf_outa_to_dram[74*`MRF_DWIDTH-1:73*`MRF_DWIDTH]; + end + `MRF_74: begin + output_data_to_dram <= mrf_outa_to_dram[75*`MRF_DWIDTH-1:74*`MRF_DWIDTH]; + end + `MRF_75: begin + output_data_to_dram <= mrf_outa_to_dram[76*`MRF_DWIDTH-1:75*`MRF_DWIDTH]; + end + `MRF_76: begin + output_data_to_dram <= mrf_outa_to_dram[77*`MRF_DWIDTH-1:76*`MRF_DWIDTH]; + end + `MRF_77: begin + output_data_to_dram <= mrf_outa_to_dram[78*`MRF_DWIDTH-1:77*`MRF_DWIDTH]; + end + `MRF_78: begin + output_data_to_dram <= mrf_outa_to_dram[79*`MRF_DWIDTH-1:78*`MRF_DWIDTH]; + end + `MRF_79: begin + output_data_to_dram <= mrf_outa_to_dram[80*`MRF_DWIDTH-1:79*`MRF_DWIDTH]; + end + `MRF_80: begin + output_data_to_dram <= mrf_outa_to_dram[81*`MRF_DWIDTH-1:80*`MRF_DWIDTH]; + end + `MRF_81: begin + output_data_to_dram <= mrf_outa_to_dram[82*`MRF_DWIDTH-1:81*`MRF_DWIDTH]; + end + `MRF_82: begin + output_data_to_dram <= mrf_outa_to_dram[83*`MRF_DWIDTH-1:82*`MRF_DWIDTH]; + end + `MRF_83: begin + output_data_to_dram <= mrf_outa_to_dram[84*`MRF_DWIDTH-1:83*`MRF_DWIDTH]; + end + `MRF_84: begin + output_data_to_dram <= mrf_outa_to_dram[85*`MRF_DWIDTH-1:84*`MRF_DWIDTH]; + end + `MRF_85: begin + output_data_to_dram <= mrf_outa_to_dram[86*`MRF_DWIDTH-1:85*`MRF_DWIDTH]; + end + `MRF_86: begin + output_data_to_dram <= mrf_outa_to_dram[87*`MRF_DWIDTH-1:86*`MRF_DWIDTH]; + end + `MRF_87: begin + output_data_to_dram <= mrf_outa_to_dram[88*`MRF_DWIDTH-1:87*`MRF_DWIDTH]; + end + `MRF_88: begin + output_data_to_dram <= mrf_outa_to_dram[89*`MRF_DWIDTH-1:88*`MRF_DWIDTH]; + end + `MRF_89: begin + output_data_to_dram <= mrf_outa_to_dram[90*`MRF_DWIDTH-1:89*`MRF_DWIDTH]; + end + `MRF_90: begin + output_data_to_dram <= mrf_outa_to_dram[91*`MRF_DWIDTH-1:90*`MRF_DWIDTH]; + end + `MRF_91: begin + output_data_to_dram <= mrf_outa_to_dram[92*`MRF_DWIDTH-1:91*`MRF_DWIDTH]; + end + `MRF_92: begin + output_data_to_dram <= mrf_outa_to_dram[93*`MRF_DWIDTH-1:92*`MRF_DWIDTH]; + end + `MRF_93: begin + output_data_to_dram <= mrf_outa_to_dram[94*`MRF_DWIDTH-1:93*`MRF_DWIDTH]; + end + `MRF_94: begin + output_data_to_dram <= mrf_outa_to_dram[95*`MRF_DWIDTH-1:94*`MRF_DWIDTH]; + end + `MRF_95: begin + output_data_to_dram <= mrf_outa_to_dram[96*`MRF_DWIDTH-1:95*`MRF_DWIDTH]; + end + `MRF_96: begin + output_data_to_dram <= mrf_outa_to_dram[97*`MRF_DWIDTH-1:96*`MRF_DWIDTH]; + end + `MRF_97: begin + output_data_to_dram <= mrf_outa_to_dram[98*`MRF_DWIDTH-1:97*`MRF_DWIDTH]; + end + `MRF_98: begin + output_data_to_dram <= mrf_outa_to_dram[99*`MRF_DWIDTH-1:98*`MRF_DWIDTH]; + end + `MRF_99: begin + output_data_to_dram <= mrf_outa_to_dram[100*`MRF_DWIDTH-1:99*`MRF_DWIDTH]; + end + `MRF_100: begin + output_data_to_dram <= mrf_outa_to_dram[101*`MRF_DWIDTH-1:100*`MRF_DWIDTH]; + end + `MRF_101: begin + output_data_to_dram <= mrf_outa_to_dram[102*`MRF_DWIDTH-1:101*`MRF_DWIDTH]; + end + `MRF_102: begin + output_data_to_dram <= mrf_outa_to_dram[103*`MRF_DWIDTH-1:102*`MRF_DWIDTH]; + end + `MRF_103: begin + output_data_to_dram <= mrf_outa_to_dram[104*`MRF_DWIDTH-1:103*`MRF_DWIDTH]; + end + `MRF_104: begin + output_data_to_dram <= mrf_outa_to_dram[105*`MRF_DWIDTH-1:104*`MRF_DWIDTH]; + end + `MRF_105: begin + output_data_to_dram <= mrf_outa_to_dram[106*`MRF_DWIDTH-1:105*`MRF_DWIDTH]; + end + `MRF_106: begin + output_data_to_dram <= mrf_outa_to_dram[107*`MRF_DWIDTH-1:106*`MRF_DWIDTH]; + end + `MRF_107: begin + output_data_to_dram <= mrf_outa_to_dram[108*`MRF_DWIDTH-1:107*`MRF_DWIDTH]; + end + `MRF_108: begin + output_data_to_dram <= mrf_outa_to_dram[109*`MRF_DWIDTH-1:108*`MRF_DWIDTH]; + end + `MRF_109: begin + output_data_to_dram <= mrf_outa_to_dram[110*`MRF_DWIDTH-1:109*`MRF_DWIDTH]; + end + `MRF_110: begin + output_data_to_dram <= mrf_outa_to_dram[111*`MRF_DWIDTH-1:110*`MRF_DWIDTH]; + end + `MRF_111: begin + output_data_to_dram <= mrf_outa_to_dram[112*`MRF_DWIDTH-1:111*`MRF_DWIDTH]; + end + `MRF_112: begin + output_data_to_dram <= mrf_outa_to_dram[113*`MRF_DWIDTH-1:112*`MRF_DWIDTH]; + end + `MRF_113: begin + output_data_to_dram <= mrf_outa_to_dram[114*`MRF_DWIDTH-1:113*`MRF_DWIDTH]; + end + `MRF_114: begin + output_data_to_dram <= mrf_outa_to_dram[115*`MRF_DWIDTH-1:114*`MRF_DWIDTH]; + end + `MRF_115: begin + output_data_to_dram <= mrf_outa_to_dram[116*`MRF_DWIDTH-1:115*`MRF_DWIDTH]; + end + `MRF_116: begin + output_data_to_dram <= mrf_outa_to_dram[117*`MRF_DWIDTH-1:116*`MRF_DWIDTH]; + end + `MRF_117: begin + output_data_to_dram <= mrf_outa_to_dram[118*`MRF_DWIDTH-1:117*`MRF_DWIDTH]; + end + `MRF_118: begin + output_data_to_dram <= mrf_outa_to_dram[119*`MRF_DWIDTH-1:118*`MRF_DWIDTH]; + end + `MRF_119: begin + output_data_to_dram <= mrf_outa_to_dram[120*`MRF_DWIDTH-1:119*`MRF_DWIDTH]; + end + `MRF_120: begin + output_data_to_dram <= mrf_outa_to_dram[121*`MRF_DWIDTH-1:120*`MRF_DWIDTH]; + end + `MRF_121: begin + output_data_to_dram <= mrf_outa_to_dram[122*`MRF_DWIDTH-1:121*`MRF_DWIDTH]; + end + `MRF_122: begin + output_data_to_dram <= mrf_outa_to_dram[123*`MRF_DWIDTH-1:122*`MRF_DWIDTH]; + end + `MRF_123: begin + output_data_to_dram <= mrf_outa_to_dram[124*`MRF_DWIDTH-1:123*`MRF_DWIDTH]; + end + `MRF_124: begin + output_data_to_dram <= mrf_outa_to_dram[125*`MRF_DWIDTH-1:124*`MRF_DWIDTH]; + end + `MRF_125: begin + output_data_to_dram <= mrf_outa_to_dram[126*`MRF_DWIDTH-1:125*`MRF_DWIDTH]; + end + `MRF_126: begin + output_data_to_dram <= mrf_outa_to_dram[127*`MRF_DWIDTH-1:126*`MRF_DWIDTH]; + end + `MRF_127: begin + output_data_to_dram <= mrf_outa_to_dram[128*`MRF_DWIDTH-1:127*`MRF_DWIDTH]; + end + default: begin + output_data_to_dram <= 'd0; + end + endcase + + end + `V_RD: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + vrf_in_data <= input_data_from_dram; + case(dstn_id) + `VRF_0: begin + vrf_wr_enable_mvu_0 <= 1'b1; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_1: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b1; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_2: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b1; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_3: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b1; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_4: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b1; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_add_0 <= dstn_address; + + end + + `VRF_5: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b1; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_mul_0 <= dstn_address; + + end + + `VRF_6: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b1; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_add_1 <= dstn_address; + end + + `VRF_7: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b1; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_mul_1 <= dstn_address; + end + + `VRF_MUXED: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b1; + + + vrf_muxed_wr_addr_dram <= dstn_address; + end + + default: begin + vrf_wr_enable_mvu_0 <= 1'bX; + vrf_wr_enable_mvu_1 <= 1'bX; + vrf_wr_enable_mvu_2 <= 1'bX; + vrf_wr_enable_mvu_3 <= 1'bX; + vrf_wr_enable_mfu_add_0 <= 1'bX; + vrf_wr_enable_mfu_mul_0 <= 1'bX; + vrf_wr_enable_mfu_add_1 <= 1'bX; + vrf_wr_enable_mfu_mul_1 <= 1'bX; + vrf_muxed_wr_enable_dram <= 1'bX; + + end + endcase +/* + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; +*/ + + end + `M_RD: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(dstn_id) + `MRF_0: begin + mrf_we_for_dram[0] <= 1; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[1*`MRF_DWIDTH-1:0*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[1*`MRF_AWIDTH-1:0*`MRF_AWIDTH] <= dstn_address; + end + `MRF_1: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 1; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[2*`MRF_DWIDTH-1:1*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[2*`MRF_AWIDTH-1:1*`MRF_AWIDTH] <= dstn_address; + end + `MRF_2: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 1; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[3*`MRF_DWIDTH-1:2*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[3*`MRF_AWIDTH-1:2*`MRF_AWIDTH] <= dstn_address; + end + `MRF_3: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 1; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[4*`MRF_DWIDTH-1:3*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[4*`MRF_AWIDTH-1:3*`MRF_AWIDTH] <= dstn_address; + end + `MRF_4: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 1; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[5*`MRF_DWIDTH-1:4*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[5*`MRF_AWIDTH-1:4*`MRF_AWIDTH] <= dstn_address; + end + `MRF_5: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 1; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[6*`MRF_DWIDTH-1:5*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[6*`MRF_AWIDTH-1:5*`MRF_AWIDTH] <= dstn_address; + end + `MRF_6: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 1; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[7*`MRF_DWIDTH-1:6*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[7*`MRF_AWIDTH-1:6*`MRF_AWIDTH] <= dstn_address; + end + `MRF_7: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 1; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[8*`MRF_DWIDTH-1:7*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[8*`MRF_AWIDTH-1:7*`MRF_AWIDTH] <= dstn_address; + end + `MRF_8: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 1; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[9*`MRF_DWIDTH-1:8*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[9*`MRF_AWIDTH-1:8*`MRF_AWIDTH] <= dstn_address; + end + `MRF_9: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 1; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[10*`MRF_DWIDTH-1:9*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[10*`MRF_AWIDTH-1:9*`MRF_AWIDTH] <= dstn_address; + end + `MRF_10: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 1; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[11*`MRF_DWIDTH-1:10*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[11*`MRF_AWIDTH-1:10*`MRF_AWIDTH] <= dstn_address; + end + `MRF_11: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 1; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[12*`MRF_DWIDTH-1:11*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[12*`MRF_AWIDTH-1:11*`MRF_AWIDTH] <= dstn_address; + end + `MRF_12: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 1; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[13*`MRF_DWIDTH-1:12*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[13*`MRF_AWIDTH-1:12*`MRF_AWIDTH] <= dstn_address; + end + `MRF_13: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 1; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[14*`MRF_DWIDTH-1:13*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[14*`MRF_AWIDTH-1:13*`MRF_AWIDTH] <= dstn_address; + end + `MRF_14: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 1; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[15*`MRF_DWIDTH-1:14*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[15*`MRF_AWIDTH-1:14*`MRF_AWIDTH] <= dstn_address; + end + `MRF_15: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 1; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[16*`MRF_DWIDTH-1:15*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[16*`MRF_AWIDTH-1:15*`MRF_AWIDTH] <= dstn_address; + end + `MRF_16: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 1; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[17*`MRF_DWIDTH-1:16*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[17*`MRF_AWIDTH-1:16*`MRF_AWIDTH] <= dstn_address; + end + `MRF_17: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 1; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[18*`MRF_DWIDTH-1:17*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[18*`MRF_AWIDTH-1:17*`MRF_AWIDTH] <= dstn_address; + end + `MRF_18: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 1; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[19*`MRF_DWIDTH-1:18*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[19*`MRF_AWIDTH-1:18*`MRF_AWIDTH] <= dstn_address; + end + `MRF_19: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 1; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[20*`MRF_DWIDTH-1:19*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[20*`MRF_AWIDTH-1:19*`MRF_AWIDTH] <= dstn_address; + end + `MRF_20: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 1; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[21*`MRF_DWIDTH-1:20*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[21*`MRF_AWIDTH-1:20*`MRF_AWIDTH] <= dstn_address; + end + `MRF_21: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 1; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[22*`MRF_DWIDTH-1:21*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[22*`MRF_AWIDTH-1:21*`MRF_AWIDTH] <= dstn_address; + end + `MRF_22: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 1; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[23*`MRF_DWIDTH-1:22*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[23*`MRF_AWIDTH-1:22*`MRF_AWIDTH] <= dstn_address; + end + `MRF_23: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 1; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[24*`MRF_DWIDTH-1:23*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[24*`MRF_AWIDTH-1:23*`MRF_AWIDTH] <= dstn_address; + end + `MRF_24: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 1; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[25*`MRF_DWIDTH-1:24*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[25*`MRF_AWIDTH-1:24*`MRF_AWIDTH] <= dstn_address; + end + `MRF_25: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 1; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[26*`MRF_DWIDTH-1:25*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[26*`MRF_AWIDTH-1:25*`MRF_AWIDTH] <= dstn_address; + end + `MRF_26: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 1; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[27*`MRF_DWIDTH-1:26*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[27*`MRF_AWIDTH-1:26*`MRF_AWIDTH] <= dstn_address; + end + `MRF_27: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 1; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[28*`MRF_DWIDTH-1:27*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[28*`MRF_AWIDTH-1:27*`MRF_AWIDTH] <= dstn_address; + end + `MRF_28: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 1; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[29*`MRF_DWIDTH-1:28*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[29*`MRF_AWIDTH-1:28*`MRF_AWIDTH] <= dstn_address; + end + `MRF_29: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 1; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[30*`MRF_DWIDTH-1:29*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[30*`MRF_AWIDTH-1:29*`MRF_AWIDTH] <= dstn_address; + end + `MRF_30: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 1; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[31*`MRF_DWIDTH-1:30*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[31*`MRF_AWIDTH-1:30*`MRF_AWIDTH] <= dstn_address; + end + `MRF_31: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 1; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[32*`MRF_DWIDTH-1:31*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[32*`MRF_AWIDTH-1:31*`MRF_AWIDTH] <= dstn_address; + end + `MRF_32: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 1; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[33*`MRF_DWIDTH-1:32*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[33*`MRF_AWIDTH-1:32*`MRF_AWIDTH] <= dstn_address; + end + `MRF_33: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 1; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[34*`MRF_DWIDTH-1:33*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[34*`MRF_AWIDTH-1:33*`MRF_AWIDTH] <= dstn_address; + end + `MRF_34: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 1; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[35*`MRF_DWIDTH-1:34*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[35*`MRF_AWIDTH-1:34*`MRF_AWIDTH] <= dstn_address; + end + `MRF_35: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 1; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[36*`MRF_DWIDTH-1:35*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[36*`MRF_AWIDTH-1:35*`MRF_AWIDTH] <= dstn_address; + end + `MRF_36: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 1; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[37*`MRF_DWIDTH-1:36*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[37*`MRF_AWIDTH-1:36*`MRF_AWIDTH] <= dstn_address; + end + `MRF_37: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 1; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[38*`MRF_DWIDTH-1:37*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[38*`MRF_AWIDTH-1:37*`MRF_AWIDTH] <= dstn_address; + end + `MRF_38: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 1; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[39*`MRF_DWIDTH-1:38*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[39*`MRF_AWIDTH-1:38*`MRF_AWIDTH] <= dstn_address; + end + `MRF_39: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 1; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[40*`MRF_DWIDTH-1:39*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[40*`MRF_AWIDTH-1:39*`MRF_AWIDTH] <= dstn_address; + end + `MRF_40: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 1; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[41*`MRF_DWIDTH-1:40*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[41*`MRF_AWIDTH-1:40*`MRF_AWIDTH] <= dstn_address; + end + `MRF_41: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 1; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[42*`MRF_DWIDTH-1:41*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[42*`MRF_AWIDTH-1:41*`MRF_AWIDTH] <= dstn_address; + end + `MRF_42: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 1; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[43*`MRF_DWIDTH-1:42*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[43*`MRF_AWIDTH-1:42*`MRF_AWIDTH] <= dstn_address; + end + `MRF_43: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 1; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[44*`MRF_DWIDTH-1:43*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[44*`MRF_AWIDTH-1:43*`MRF_AWIDTH] <= dstn_address; + end + `MRF_44: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 1; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[45*`MRF_DWIDTH-1:44*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[45*`MRF_AWIDTH-1:44*`MRF_AWIDTH] <= dstn_address; + end + `MRF_45: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 1; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[46*`MRF_DWIDTH-1:45*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[46*`MRF_AWIDTH-1:45*`MRF_AWIDTH] <= dstn_address; + end + `MRF_46: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 1; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[47*`MRF_DWIDTH-1:46*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[47*`MRF_AWIDTH-1:46*`MRF_AWIDTH] <= dstn_address; + end + `MRF_47: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 1; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[48*`MRF_DWIDTH-1:47*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[48*`MRF_AWIDTH-1:47*`MRF_AWIDTH] <= dstn_address; + end + `MRF_48: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 1; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[49*`MRF_DWIDTH-1:48*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[49*`MRF_AWIDTH-1:48*`MRF_AWIDTH] <= dstn_address; + end + `MRF_49: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 1; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[50*`MRF_DWIDTH-1:49*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[50*`MRF_AWIDTH-1:49*`MRF_AWIDTH] <= dstn_address; + end + `MRF_50: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 1; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[51*`MRF_DWIDTH-1:50*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[51*`MRF_AWIDTH-1:50*`MRF_AWIDTH] <= dstn_address; + end + `MRF_51: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 1; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[52*`MRF_DWIDTH-1:51*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[52*`MRF_AWIDTH-1:51*`MRF_AWIDTH] <= dstn_address; + end + `MRF_52: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 1; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[53*`MRF_DWIDTH-1:52*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[53*`MRF_AWIDTH-1:52*`MRF_AWIDTH] <= dstn_address; + end + `MRF_53: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 1; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[54*`MRF_DWIDTH-1:53*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[54*`MRF_AWIDTH-1:53*`MRF_AWIDTH] <= dstn_address; + end + `MRF_54: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 1; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[55*`MRF_DWIDTH-1:54*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[55*`MRF_AWIDTH-1:54*`MRF_AWIDTH] <= dstn_address; + end + `MRF_55: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 1; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[56*`MRF_DWIDTH-1:55*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[56*`MRF_AWIDTH-1:55*`MRF_AWIDTH] <= dstn_address; + end + `MRF_56: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 1; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[57*`MRF_DWIDTH-1:56*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[57*`MRF_AWIDTH-1:56*`MRF_AWIDTH] <= dstn_address; + end + `MRF_57: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 1; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[58*`MRF_DWIDTH-1:57*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[58*`MRF_AWIDTH-1:57*`MRF_AWIDTH] <= dstn_address; + end + `MRF_58: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 1; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[59*`MRF_DWIDTH-1:58*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[59*`MRF_AWIDTH-1:58*`MRF_AWIDTH] <= dstn_address; + end + `MRF_59: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 1; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[60*`MRF_DWIDTH-1:59*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[60*`MRF_AWIDTH-1:59*`MRF_AWIDTH] <= dstn_address; + end + `MRF_60: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 1; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[61*`MRF_DWIDTH-1:60*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[61*`MRF_AWIDTH-1:60*`MRF_AWIDTH] <= dstn_address; + end + `MRF_61: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 1; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[62*`MRF_DWIDTH-1:61*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[62*`MRF_AWIDTH-1:61*`MRF_AWIDTH] <= dstn_address; + end + `MRF_62: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 1; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[63*`MRF_DWIDTH-1:62*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[63*`MRF_AWIDTH-1:62*`MRF_AWIDTH] <= dstn_address; + end + `MRF_63: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 1; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[64*`MRF_DWIDTH-1:63*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[64*`MRF_AWIDTH-1:63*`MRF_AWIDTH] <= dstn_address; + end + `MRF_64: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 1; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[65*`MRF_DWIDTH-1:64*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[65*`MRF_AWIDTH-1:64*`MRF_AWIDTH] <= dstn_address; + end + `MRF_65: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 1; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[66*`MRF_DWIDTH-1:65*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[66*`MRF_AWIDTH-1:65*`MRF_AWIDTH] <= dstn_address; + end + `MRF_66: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 1; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[67*`MRF_DWIDTH-1:66*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[67*`MRF_AWIDTH-1:66*`MRF_AWIDTH] <= dstn_address; + end + `MRF_67: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 1; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[68*`MRF_DWIDTH-1:67*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[68*`MRF_AWIDTH-1:67*`MRF_AWIDTH] <= dstn_address; + end + `MRF_68: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 1; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[69*`MRF_DWIDTH-1:68*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[69*`MRF_AWIDTH-1:68*`MRF_AWIDTH] <= dstn_address; + end + `MRF_69: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 1; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[70*`MRF_DWIDTH-1:69*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[70*`MRF_AWIDTH-1:69*`MRF_AWIDTH] <= dstn_address; + end + `MRF_70: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 1; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[71*`MRF_DWIDTH-1:70*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[71*`MRF_AWIDTH-1:70*`MRF_AWIDTH] <= dstn_address; + end + `MRF_71: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 1; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[72*`MRF_DWIDTH-1:71*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[72*`MRF_AWIDTH-1:71*`MRF_AWIDTH] <= dstn_address; + end + `MRF_72: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 1; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[73*`MRF_DWIDTH-1:72*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[73*`MRF_AWIDTH-1:72*`MRF_AWIDTH] <= dstn_address; + end + `MRF_73: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 1; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[74*`MRF_DWIDTH-1:73*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[74*`MRF_AWIDTH-1:73*`MRF_AWIDTH] <= dstn_address; + end + `MRF_74: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 1; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[75*`MRF_DWIDTH-1:74*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[75*`MRF_AWIDTH-1:74*`MRF_AWIDTH] <= dstn_address; + end + `MRF_75: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 1; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[76*`MRF_DWIDTH-1:75*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[76*`MRF_AWIDTH-1:75*`MRF_AWIDTH] <= dstn_address; + end + `MRF_76: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 1; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[77*`MRF_DWIDTH-1:76*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[77*`MRF_AWIDTH-1:76*`MRF_AWIDTH] <= dstn_address; + end + `MRF_77: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 1; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[78*`MRF_DWIDTH-1:77*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[78*`MRF_AWIDTH-1:77*`MRF_AWIDTH] <= dstn_address; + end + `MRF_78: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 1; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[79*`MRF_DWIDTH-1:78*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[79*`MRF_AWIDTH-1:78*`MRF_AWIDTH] <= dstn_address; + end + `MRF_79: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 1; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[80*`MRF_DWIDTH-1:79*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[80*`MRF_AWIDTH-1:79*`MRF_AWIDTH] <= dstn_address; + end + `MRF_80: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 1; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[81*`MRF_DWIDTH-1:80*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[81*`MRF_AWIDTH-1:80*`MRF_AWIDTH] <= dstn_address; + end + `MRF_81: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 1; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[82*`MRF_DWIDTH-1:81*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[82*`MRF_AWIDTH-1:81*`MRF_AWIDTH] <= dstn_address; + end + `MRF_82: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 1; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[83*`MRF_DWIDTH-1:82*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[83*`MRF_AWIDTH-1:82*`MRF_AWIDTH] <= dstn_address; + end + `MRF_83: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 1; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[84*`MRF_DWIDTH-1:83*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[84*`MRF_AWIDTH-1:83*`MRF_AWIDTH] <= dstn_address; + end + `MRF_84: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 1; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[85*`MRF_DWIDTH-1:84*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[85*`MRF_AWIDTH-1:84*`MRF_AWIDTH] <= dstn_address; + end + `MRF_85: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 1; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[86*`MRF_DWIDTH-1:85*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[86*`MRF_AWIDTH-1:85*`MRF_AWIDTH] <= dstn_address; + end + `MRF_86: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 1; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[87*`MRF_DWIDTH-1:86*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[87*`MRF_AWIDTH-1:86*`MRF_AWIDTH] <= dstn_address; + end + `MRF_87: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 1; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[88*`MRF_DWIDTH-1:87*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[88*`MRF_AWIDTH-1:87*`MRF_AWIDTH] <= dstn_address; + end + `MRF_88: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 1; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[89*`MRF_DWIDTH-1:88*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[89*`MRF_AWIDTH-1:88*`MRF_AWIDTH] <= dstn_address; + end + `MRF_89: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 1; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[90*`MRF_DWIDTH-1:89*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[90*`MRF_AWIDTH-1:89*`MRF_AWIDTH] <= dstn_address; + end + `MRF_90: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 1; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[91*`MRF_DWIDTH-1:90*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[91*`MRF_AWIDTH-1:90*`MRF_AWIDTH] <= dstn_address; + end + `MRF_91: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 1; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[92*`MRF_DWIDTH-1:91*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[92*`MRF_AWIDTH-1:91*`MRF_AWIDTH] <= dstn_address; + end + `MRF_92: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 1; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[93*`MRF_DWIDTH-1:92*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[93*`MRF_AWIDTH-1:92*`MRF_AWIDTH] <= dstn_address; + end + `MRF_93: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 1; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[94*`MRF_DWIDTH-1:93*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[94*`MRF_AWIDTH-1:93*`MRF_AWIDTH] <= dstn_address; + end + `MRF_94: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 1; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[95*`MRF_DWIDTH-1:94*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[95*`MRF_AWIDTH-1:94*`MRF_AWIDTH] <= dstn_address; + end + `MRF_95: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 1; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[96*`MRF_DWIDTH-1:95*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[96*`MRF_AWIDTH-1:95*`MRF_AWIDTH] <= dstn_address; + end + `MRF_96: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 1; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[97*`MRF_DWIDTH-1:96*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[97*`MRF_AWIDTH-1:96*`MRF_AWIDTH] <= dstn_address; + end + `MRF_97: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 1; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[98*`MRF_DWIDTH-1:97*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[98*`MRF_AWIDTH-1:97*`MRF_AWIDTH] <= dstn_address; + end + `MRF_98: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 1; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[99*`MRF_DWIDTH-1:98*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[99*`MRF_AWIDTH-1:98*`MRF_AWIDTH] <= dstn_address; + end + `MRF_99: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 1; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[100*`MRF_DWIDTH-1:99*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[100*`MRF_AWIDTH-1:99*`MRF_AWIDTH] <= dstn_address; + end + `MRF_100: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 1; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[101*`MRF_DWIDTH-1:100*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[101*`MRF_AWIDTH-1:100*`MRF_AWIDTH] <= dstn_address; + end + `MRF_101: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 1; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[102*`MRF_DWIDTH-1:101*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[102*`MRF_AWIDTH-1:101*`MRF_AWIDTH] <= dstn_address; + end + `MRF_102: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 1; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[103*`MRF_DWIDTH-1:102*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[103*`MRF_AWIDTH-1:102*`MRF_AWIDTH] <= dstn_address; + end + `MRF_103: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 1; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[104*`MRF_DWIDTH-1:103*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[104*`MRF_AWIDTH-1:103*`MRF_AWIDTH] <= dstn_address; + end + `MRF_104: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 1; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[105*`MRF_DWIDTH-1:104*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[105*`MRF_AWIDTH-1:104*`MRF_AWIDTH] <= dstn_address; + end + `MRF_105: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 1; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[106*`MRF_DWIDTH-1:105*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[106*`MRF_AWIDTH-1:105*`MRF_AWIDTH] <= dstn_address; + end + `MRF_106: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 1; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[107*`MRF_DWIDTH-1:106*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[107*`MRF_AWIDTH-1:106*`MRF_AWIDTH] <= dstn_address; + end + `MRF_107: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 1; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[108*`MRF_DWIDTH-1:107*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[108*`MRF_AWIDTH-1:107*`MRF_AWIDTH] <= dstn_address; + end + `MRF_108: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 1; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[109*`MRF_DWIDTH-1:108*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[109*`MRF_AWIDTH-1:108*`MRF_AWIDTH] <= dstn_address; + end + `MRF_109: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 1; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[110*`MRF_DWIDTH-1:109*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[110*`MRF_AWIDTH-1:109*`MRF_AWIDTH] <= dstn_address; + end + `MRF_110: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 1; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[111*`MRF_DWIDTH-1:110*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[111*`MRF_AWIDTH-1:110*`MRF_AWIDTH] <= dstn_address; + end + `MRF_111: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 1; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[112*`MRF_DWIDTH-1:111*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[112*`MRF_AWIDTH-1:111*`MRF_AWIDTH] <= dstn_address; + end + `MRF_112: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 1; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[113*`MRF_DWIDTH-1:112*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[113*`MRF_AWIDTH-1:112*`MRF_AWIDTH] <= dstn_address; + end + `MRF_113: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 1; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[114*`MRF_DWIDTH-1:113*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[114*`MRF_AWIDTH-1:113*`MRF_AWIDTH] <= dstn_address; + end + `MRF_114: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 1; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[115*`MRF_DWIDTH-1:114*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[115*`MRF_AWIDTH-1:114*`MRF_AWIDTH] <= dstn_address; + end + `MRF_115: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 1; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[116*`MRF_DWIDTH-1:115*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[116*`MRF_AWIDTH-1:115*`MRF_AWIDTH] <= dstn_address; + end + `MRF_116: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 1; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[117*`MRF_DWIDTH-1:116*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[117*`MRF_AWIDTH-1:116*`MRF_AWIDTH] <= dstn_address; + end + `MRF_117: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 1; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[118*`MRF_DWIDTH-1:117*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[118*`MRF_AWIDTH-1:117*`MRF_AWIDTH] <= dstn_address; + end + `MRF_118: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 1; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[119*`MRF_DWIDTH-1:118*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[119*`MRF_AWIDTH-1:118*`MRF_AWIDTH] <= dstn_address; + end + `MRF_119: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 1; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[120*`MRF_DWIDTH-1:119*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[120*`MRF_AWIDTH-1:119*`MRF_AWIDTH] <= dstn_address; + end + `MRF_120: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 1; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[121*`MRF_DWIDTH-1:120*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[121*`MRF_AWIDTH-1:120*`MRF_AWIDTH] <= dstn_address; + end + `MRF_121: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 1; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[122*`MRF_DWIDTH-1:121*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[122*`MRF_AWIDTH-1:121*`MRF_AWIDTH] <= dstn_address; + end + `MRF_122: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 1; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[123*`MRF_DWIDTH-1:122*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[123*`MRF_AWIDTH-1:122*`MRF_AWIDTH] <= dstn_address; + end + `MRF_123: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 1; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[124*`MRF_DWIDTH-1:123*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[124*`MRF_AWIDTH-1:123*`MRF_AWIDTH] <= dstn_address; + end + `MRF_124: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 1; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[125*`MRF_DWIDTH-1:124*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[125*`MRF_AWIDTH-1:124*`MRF_AWIDTH] <= dstn_address; + end + `MRF_125: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 1; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 0; + mrf_in_data[126*`MRF_DWIDTH-1:125*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[126*`MRF_AWIDTH-1:125*`MRF_AWIDTH] <= dstn_address; + end + `MRF_126: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 1; + mrf_we_for_dram[127] <= 0; + mrf_in_data[127*`MRF_DWIDTH-1:126*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[127*`MRF_AWIDTH-1:126*`MRF_AWIDTH] <= dstn_address; + end + `MRF_127: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_we_for_dram[64] <= 0; + mrf_we_for_dram[65] <= 0; + mrf_we_for_dram[66] <= 0; + mrf_we_for_dram[67] <= 0; + mrf_we_for_dram[68] <= 0; + mrf_we_for_dram[69] <= 0; + mrf_we_for_dram[70] <= 0; + mrf_we_for_dram[71] <= 0; + mrf_we_for_dram[72] <= 0; + mrf_we_for_dram[73] <= 0; + mrf_we_for_dram[74] <= 0; + mrf_we_for_dram[75] <= 0; + mrf_we_for_dram[76] <= 0; + mrf_we_for_dram[77] <= 0; + mrf_we_for_dram[78] <= 0; + mrf_we_for_dram[79] <= 0; + mrf_we_for_dram[80] <= 0; + mrf_we_for_dram[81] <= 0; + mrf_we_for_dram[82] <= 0; + mrf_we_for_dram[83] <= 0; + mrf_we_for_dram[84] <= 0; + mrf_we_for_dram[85] <= 0; + mrf_we_for_dram[86] <= 0; + mrf_we_for_dram[87] <= 0; + mrf_we_for_dram[88] <= 0; + mrf_we_for_dram[89] <= 0; + mrf_we_for_dram[90] <= 0; + mrf_we_for_dram[91] <= 0; + mrf_we_for_dram[92] <= 0; + mrf_we_for_dram[93] <= 0; + mrf_we_for_dram[94] <= 0; + mrf_we_for_dram[95] <= 0; + mrf_we_for_dram[96] <= 0; + mrf_we_for_dram[97] <= 0; + mrf_we_for_dram[98] <= 0; + mrf_we_for_dram[99] <= 0; + mrf_we_for_dram[100] <= 0; + mrf_we_for_dram[101] <= 0; + mrf_we_for_dram[102] <= 0; + mrf_we_for_dram[103] <= 0; + mrf_we_for_dram[104] <= 0; + mrf_we_for_dram[105] <= 0; + mrf_we_for_dram[106] <= 0; + mrf_we_for_dram[107] <= 0; + mrf_we_for_dram[108] <= 0; + mrf_we_for_dram[109] <= 0; + mrf_we_for_dram[110] <= 0; + mrf_we_for_dram[111] <= 0; + mrf_we_for_dram[112] <= 0; + mrf_we_for_dram[113] <= 0; + mrf_we_for_dram[114] <= 0; + mrf_we_for_dram[115] <= 0; + mrf_we_for_dram[116] <= 0; + mrf_we_for_dram[117] <= 0; + mrf_we_for_dram[118] <= 0; + mrf_we_for_dram[119] <= 0; + mrf_we_for_dram[120] <= 0; + mrf_we_for_dram[121] <= 0; + mrf_we_for_dram[122] <= 0; + mrf_we_for_dram[123] <= 0; + mrf_we_for_dram[124] <= 0; + mrf_we_for_dram[125] <= 0; + mrf_we_for_dram[126] <= 0; + mrf_we_for_dram[127] <= 1; + mrf_in_data[128*`MRF_DWIDTH-1:127*`MRF_DWIDTH] <= input_data_from_dram[`MRF_DWIDTH-1:0]; + mrf_addr_for_dram[128*`MRF_AWIDTH-1:127*`MRF_AWIDTH] <= dstn_address; + end + + default: begin + mrf_we_for_dram[0] <= 1'bX; + mrf_we_for_dram[1] <= 1'bX; + mrf_we_for_dram[2] <= 1'bX; + mrf_we_for_dram[3] <= 1'bX; + mrf_we_for_dram[4] <= 1'bX; + mrf_we_for_dram[5] <= 1'bX; + mrf_we_for_dram[6] <= 1'bX; + mrf_we_for_dram[7] <= 1'bX; + mrf_we_for_dram[8] <= 1'bX; + mrf_we_for_dram[9] <= 1'bX; + mrf_we_for_dram[10] <= 1'bX; + mrf_we_for_dram[11] <= 1'bX; + mrf_we_for_dram[12] <= 1'bX; + mrf_we_for_dram[13] <= 1'bX; + mrf_we_for_dram[14] <= 1'bX; + mrf_we_for_dram[15] <= 1'bX; + mrf_we_for_dram[16] <= 1'bX; + mrf_we_for_dram[17] <= 1'bX; + mrf_we_for_dram[18] <= 1'bX; + mrf_we_for_dram[19] <= 1'bX; + mrf_we_for_dram[20] <= 1'bX; + mrf_we_for_dram[21] <= 1'bX; + mrf_we_for_dram[22] <= 1'bX; + mrf_we_for_dram[23] <= 1'bX; + mrf_we_for_dram[24] <= 1'bX; + mrf_we_for_dram[25] <= 1'bX; + mrf_we_for_dram[26] <= 1'bX; + mrf_we_for_dram[27] <= 1'bX; + mrf_we_for_dram[28] <= 1'bX; + mrf_we_for_dram[29] <= 1'bX; + mrf_we_for_dram[30] <= 1'bX; + mrf_we_for_dram[31] <= 1'bX; + mrf_we_for_dram[32] <= 1'bX; + mrf_we_for_dram[33] <= 1'bX; + mrf_we_for_dram[34] <= 1'bX; + mrf_we_for_dram[35] <= 1'bX; + mrf_we_for_dram[36] <= 1'bX; + mrf_we_for_dram[37] <= 1'bX; + mrf_we_for_dram[38] <= 1'bX; + mrf_we_for_dram[39] <= 1'bX; + mrf_we_for_dram[40] <= 1'bX; + mrf_we_for_dram[41] <= 1'bX; + mrf_we_for_dram[42] <= 1'bX; + mrf_we_for_dram[43] <= 1'bX; + mrf_we_for_dram[44] <= 1'bX; + mrf_we_for_dram[45] <= 1'bX; + mrf_we_for_dram[46] <= 1'bX; + mrf_we_for_dram[47] <= 1'bX; + mrf_we_for_dram[48] <= 1'bX; + mrf_we_for_dram[49] <= 1'bX; + mrf_we_for_dram[50] <= 1'bX; + mrf_we_for_dram[51] <= 1'bX; + mrf_we_for_dram[52] <= 1'bX; + mrf_we_for_dram[53] <= 1'bX; + mrf_we_for_dram[54] <= 1'bX; + mrf_we_for_dram[55] <= 1'bX; + mrf_we_for_dram[56] <= 1'bX; + mrf_we_for_dram[57] <= 1'bX; + mrf_we_for_dram[58] <= 1'bX; + mrf_we_for_dram[59] <= 1'bX; + mrf_we_for_dram[60] <= 1'bX; + mrf_we_for_dram[61] <= 1'bX; + mrf_we_for_dram[62] <= 1'bX; + mrf_we_for_dram[63] <= 1'bX; + mrf_we_for_dram[64] <= 1'bX; + mrf_we_for_dram[65] <= 1'bX; + mrf_we_for_dram[66] <= 1'bX; + mrf_we_for_dram[67] <= 1'bX; + mrf_we_for_dram[68] <= 1'bX; + mrf_we_for_dram[69] <= 1'bX; + mrf_we_for_dram[70] <= 1'bX; + mrf_we_for_dram[71] <= 1'bX; + mrf_we_for_dram[72] <= 1'bX; + mrf_we_for_dram[73] <= 1'bX; + mrf_we_for_dram[74] <= 1'bX; + mrf_we_for_dram[75] <= 1'bX; + mrf_we_for_dram[76] <= 1'bX; + mrf_we_for_dram[77] <= 1'bX; + mrf_we_for_dram[78] <= 1'bX; + mrf_we_for_dram[79] <= 1'bX; + mrf_we_for_dram[80] <= 1'bX; + mrf_we_for_dram[81] <= 1'bX; + mrf_we_for_dram[82] <= 1'bX; + mrf_we_for_dram[83] <= 1'bX; + mrf_we_for_dram[84] <= 1'bX; + mrf_we_for_dram[85] <= 1'bX; + mrf_we_for_dram[86] <= 1'bX; + mrf_we_for_dram[87] <= 1'bX; + mrf_we_for_dram[88] <= 1'bX; + mrf_we_for_dram[89] <= 1'bX; + mrf_we_for_dram[90] <= 1'bX; + mrf_we_for_dram[91] <= 1'bX; + mrf_we_for_dram[92] <= 1'bX; + mrf_we_for_dram[93] <= 1'bX; + mrf_we_for_dram[94] <= 1'bX; + mrf_we_for_dram[95] <= 1'bX; + mrf_we_for_dram[96] <= 1'bX; + mrf_we_for_dram[97] <= 1'bX; + mrf_we_for_dram[98] <= 1'bX; + mrf_we_for_dram[99] <= 1'bX; + mrf_we_for_dram[100] <= 1'bX; + mrf_we_for_dram[101] <= 1'bX; + mrf_we_for_dram[102] <= 1'bX; + mrf_we_for_dram[103] <= 1'bX; + mrf_we_for_dram[104] <= 1'bX; + mrf_we_for_dram[105] <= 1'bX; + mrf_we_for_dram[106] <= 1'bX; + mrf_we_for_dram[107] <= 1'bX; + mrf_we_for_dram[108] <= 1'bX; + mrf_we_for_dram[109] <= 1'bX; + mrf_we_for_dram[110] <= 1'bX; + mrf_we_for_dram[111] <= 1'bX; + mrf_we_for_dram[112] <= 1'bX; + mrf_we_for_dram[113] <= 1'bX; + mrf_we_for_dram[114] <= 1'bX; + mrf_we_for_dram[115] <= 1'bX; + mrf_we_for_dram[116] <= 1'bX; + mrf_we_for_dram[117] <= 1'bX; + mrf_we_for_dram[118] <= 1'bX; + mrf_we_for_dram[119] <= 1'bX; + mrf_we_for_dram[120] <= 1'bX; + mrf_we_for_dram[121] <= 1'bX; + mrf_we_for_dram[122] <= 1'bX; + mrf_we_for_dram[123] <= 1'bX; + mrf_we_for_dram[124] <= 1'bX; + mrf_we_for_dram[125] <= 1'bX; + mrf_we_for_dram[126] <= 1'bX; + mrf_we_for_dram[127] <= 1'bX; + end + + endcase + end + default: begin + + if(done_mvm || done_mfu_0 || done_mfu_1) begin + start_mv_mul <= 0; + start_mfu_0 <= 0; + start_mfu_1 <= 0; + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(dstn_id) + `VRF_0: begin + vrf_wr_enable_mvu_0 <= 1'b1; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_1: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b1; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_2: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b1; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_3: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b1; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + + `VRF_4: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b1; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_add_0 <= dstn_address; + + end + + `VRF_5: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b1; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_mul_0 <= dstn_address; + + end + + `VRF_6: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b1; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_add_1 <= dstn_address; + end + + `VRF_7: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b1; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_mul_1 <= dstn_address; + end + + `VRF_MUXED: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b1; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_muxed_wr_addr_dram <= dstn_address; + end + + `DRAM_MEM_ID: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b1; + + output_data_to_dram <= output_final_stage; + + dram_addr_wr <= dstn_address; + end + + //MFU_OUT_STAGE IDS USED FOR MUXING + + default: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + end + endcase + end + end + endcase + end + end + end +endmodule +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM mvu.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + + +//`include "includes_gen.v" + +module MVU ( + input clk, + input[`NUM_LDPES-1:0] start, + input[`NUM_LDPES-1:0] reset, + input [`VRF_AWIDTH-1:0] vrf_wr_addr, + input [`VRF_AWIDTH-1:0] vrf_read_addr, + input [`VRF_DWIDTH-1:0] vec, + + input vrf_wr_enable_tile_0, + input vrf_readn_enable_tile_0, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_0, + input vrf_wr_enable_tile_1, + input vrf_readn_enable_tile_1, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_1, + input vrf_wr_enable_tile_2, + input vrf_readn_enable_tile_2, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_2, + input vrf_wr_enable_tile_3, + input vrf_readn_enable_tile_3, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_3, + + input [`MRF_DWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_in, + input[`NUM_TILES*`NUM_LDPES-1:0] mrf_we, + input [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr, + + input[`NUM_TILES*`NUM_LDPES-1:0] mrf_we_for_dram, + input [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram, + output [`NUM_TILES*`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram, + + output [`ORF_DWIDTH-1:0] mvm_result, + output out_data_available +); + + + wire[`NUM_LDPES-1:0] start_external_comparator_tree; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_final; + + wire[`NUM_LDPES-1:0] out_data_available_comparator_tile; + + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_0; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_0; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_0; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_0; + + MVU_tile tile_0(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_0), + .vrf_data_out(vrf_data_out_tile_0), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_0), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_0), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_0), + .out_data_available(out_data_available_mvm_tile_0), + .mrf_in(mrf_in[1*`MRF_DWIDTH*`NUM_LDPES-1:0*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[1*`NUM_LDPES-1:0*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[1*`NUM_LDPES*`MRF_AWIDTH-1:0*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[1*`NUM_LDPES*`MRF_AWIDTH-1:0*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[1*`NUM_LDPES*`MRF_DWIDTH-1:0*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[1*`NUM_LDPES-1:0*`NUM_LDPES]), + .result(result_mvm_0) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_1; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_1; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_1; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_1; + + MVU_tile tile_1(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_1), + .vrf_data_out(vrf_data_out_tile_1), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_1), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_1), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_1), + .out_data_available(out_data_available_mvm_tile_1), + .mrf_in(mrf_in[2*`MRF_DWIDTH*`NUM_LDPES-1:1*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[2*`NUM_LDPES-1:1*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[2*`NUM_LDPES*`MRF_AWIDTH-1:1*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[2*`NUM_LDPES*`MRF_AWIDTH-1:1*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[2*`NUM_LDPES*`MRF_DWIDTH-1:1*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[2*`NUM_LDPES-1:1*`NUM_LDPES]), + .result(result_mvm_1) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_2; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_2; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_2; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_2; + + MVU_tile tile_2(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_2), + .vrf_data_out(vrf_data_out_tile_2), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_2), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_2), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_2), + .out_data_available(out_data_available_mvm_tile_2), + .mrf_in(mrf_in[3*`MRF_DWIDTH*`NUM_LDPES-1:2*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[3*`NUM_LDPES-1:2*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[3*`NUM_LDPES*`MRF_AWIDTH-1:2*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[3*`NUM_LDPES*`MRF_AWIDTH-1:2*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[3*`NUM_LDPES*`MRF_DWIDTH-1:2*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[3*`NUM_LDPES-1:2*`NUM_LDPES]), + .result(result_mvm_2) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_3; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_3; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_3; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_3; + + MVU_tile tile_3(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_3), + .vrf_data_out(vrf_data_out_tile_3), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_3), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_3), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_3), + .out_data_available(out_data_available_mvm_tile_3), + .mrf_in(mrf_in[4*`MRF_DWIDTH*`NUM_LDPES-1:3*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[4*`NUM_LDPES-1:3*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[4*`NUM_LDPES*`MRF_AWIDTH-1:3*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[4*`NUM_LDPES*`MRF_AWIDTH-1:3*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[4*`NUM_LDPES*`MRF_DWIDTH-1:3*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[4*`NUM_LDPES-1:3*`NUM_LDPES]), + .result(result_mvm_3) //WITH TAG + ); + + + +assign start_external_comparator_tree = out_data_available_internal_comparator_tree_0; + +exponent_comparator_tree_tile exp_cmp ( + .clk(clk), + .reset(reset), + .start(start_external_comparator_tree), + .out_data_available(out_data_available_comparator_tile), + .inp0(max_exp_0), + .inp1(max_exp_1), + .inp2(max_exp_2), + .inp3(max_exp_3), + .result_final_stage(max_exp_final) +); + + +wire[`NUM_LDPES*`LDPE_USED_OUTPUT_WIDTH-1:0] reduction_unit_output; +wire[`NUM_LDPES-1:0] out_data_available_reduction; + +wire[`NUM_LDPES-1:0] start_reduction_tree; +assign start_reduction_tree = out_data_available_mvm_tile_0; + + +mvm_reduction_unit mvm_reduction ( + .clk(clk), + .reset_reduction_mvm(reset), + .start(start_reduction_tree), + .out_data_available(out_data_available_reduction), + .inp0(result_mvm_0), + .inp1(result_mvm_1), + .inp2(result_mvm_2), + .inp3(result_mvm_3), + .result_mvm_final_stage(reduction_unit_output) +); + +wire[`BFLOAT_DWIDTH*`NUM_LDPES-1:0] msfp11_out; +wire[`NUM_LDPES-1:0] out_data_available_msfp_gen; + +genvar i; +generate + for(i=1;i<=`NUM_LDPES;i=i+1) begin: gen_msfp_generator + msfp_generator msfp_gen( + .clk(clk), + .exponent(max_exp_final[i*`BFLOAT_EXP-1:(i-1)*`BFLOAT_EXP]), + .mantisa(reduction_unit_output[i*`LDPE_USED_OUTPUT_WIDTH-1:(i-1)*`LDPE_USED_OUTPUT_WIDTH]), + .reset(reset[i-1]), + .start(out_data_available_reduction[i-1]), + .out_data_available(out_data_available_msfp_gen[i-1]), + .msfp11(msfp11_out[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]) + ); + end +endgenerate + +wire[`NUM_LDPES-1:0] out_data_available_msfp11_to_fp16_converter; +wire [`FLOAT_DWIDTH*`NUM_LDPES-1:0] msfp_fp_converter_output; + +generate + for(i=1;i<=`NUM_LDPES;i=i+1) begin: gen_msfp11_to_fp16 + msfp11_to_fp16 msfp_to_fp_converter( + .clk(clk), + .reset(reset[i-1]), + .start(out_data_available_msfp_gen[i-1]), + .out_data_available(out_data_available_msfp11_to_fp16_converter[i-1]), + .a(msfp11_out[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]), + .b(msfp_fp_converter_output[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]) + ); + end +endgenerate + +assign mvm_result = msfp_fp_converter_output; +assign out_data_available = out_data_available_msfp11_to_fp16_converter[0]; + +endmodule + +module msfp_generator( + input[`BFLOAT_EXP-1:0] exponent, + input[`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa, + input clk, + input reset, + input start, + output reg out_data_available, + output reg[`BFLOAT_DWIDTH-1:0] msfp11 +); + + wire sign, is_valid; + wire[2:0] position; + wire[`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa_sign_adjusted; + + + assign sign = mantisa[`LDPE_USED_OUTPUT_WIDTH-1]; + + assign mantisa_sign_adjusted = (sign) ? (-mantisa) : mantisa; + wire out_data_available_lzd; + + leading_zero_detector_6bit ldetector( + .reset(reset), + .start(start), + .clk(clk), + .a(mantisa_sign_adjusted[`BFLOAT_MANTISA_WITH_LO-1:0]), + .is_valid(is_valid), + .position(position), + .out_data_available(out_data_available_lzd) + ); + + + + wire[4:0] normalize_amt; + assign normalize_amt = (is_valid) ? position : 5'd0; + + wire[`BFLOAT_MANTISA_WITH_LO-1:0] significand_to_be_normalised; + assign significand_to_be_normalised = (is_valid) ? mantisa_sign_adjusted[`BFLOAT_MANTISA_WITH_LO-1:0] : 6'd0; + + wire out_data_available_barrel_shifter_left; + + wire[`BFLOAT_MANTISA_WITH_LO-1:0] mantisa_shifted; + barrel_shifter_left bshift_left( + .clk(clk), + .reset(reset), + .start(out_data_available_lzd), + .out_data_available(out_data_available_barrel_shifter_left), + .shift_amt(normalize_amt), + .significand(significand_to_be_normalised), + .shifted_sig(mantisa_shifted) + ); + wire[`BFLOAT_EXP-1:0] normalized_exponent; + + assign normalized_exponent = exponent - normalize_amt; + + always@(posedge clk) begin + if((reset==1) || (start==0)) begin + msfp11 <= 11'd0; + out_data_available <= 0; + end + else begin + out_data_available <= out_data_available_barrel_shifter_left; + msfp11 <= {sign, normalized_exponent, mantisa_shifted[`BFLOAT_MANTISA-1:0]}; + end + end + +endmodule + +module MVU_tile ( + input clk, + input[`NUM_LDPES-1:0] start, + input[`NUM_LDPES-1:0] reset, + input vrf_wr_enable, + input [`VRF_AWIDTH-1:0] vrf_wr_addr, + input [`VRF_AWIDTH-1:0] vrf_read_addr, + input [`VRF_DWIDTH-1:0] vec, + output[`VRF_DWIDTH-1:0] vrf_data_out, + input [`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_in, + input vrf_readn_enable, + input[`NUM_LDPES-1:0] mrf_we, + input[`NUM_LDPES-1:0] mrf_we_for_dram, + input [`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr, + input [`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram, + input [`NUM_LDPES-1:0] out_data_available_external_comparator_tree, + output [`NUM_LDPES-1:0] out_data_available_internal_comparator_tree, + output [`NUM_LDPES-1:0] out_data_available, + output [`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp, + output [`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result, + output [`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram +); + + wire [`VRF_DWIDTH-1:0] ina_fake; + + + wire [`VRF_DWIDTH-1:0] vrf_outa_wire; + + // Port A is used to feed LDPE and port B to load vector from DRAM. + + VRF vrf ( + .clk(clk), + .addra(vrf_read_addr), + .ina(ina_fake), + .wea(vrf_readn_enable), + .outa(vrf_outa_wire), + .addrb(vrf_wr_addr), + .inb(vec), + .web(vrf_wr_enable), + .outb(vrf_data_out) + ); + + genvar i; + generate + for (i=1; i<=`NUM_LDPES; i=i+1) begin: gen_compute_unit + compute_unit unit ( + .clk(clk), + .reset(reset[i-1]), + .start(start[i-1]), + .vec(vrf_outa_wire), + .mrf_in(mrf_in[i*`MRF_DWIDTH-1:(i-1)*`MRF_DWIDTH]), + .mrf_we(mrf_we[i-1]), + .mrf_addr(mrf_addr[i*`MRF_AWIDTH-1:(i-1)*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[i*`MRF_AWIDTH-1:(i-1)*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[i*`MRF_DWIDTH-1:(i-1)*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[i-1]), + .max_exp(max_exp[i*`BFLOAT_EXP-1:(i-1)*`BFLOAT_EXP]), + .out_data_available_external_comparator_tree(out_data_available_external_comparator_tree[i-1]), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree[i-1]), + .out_data_available_dot_prod(out_data_available[i-1]), + .result(result[i*`LDPE_USED_OUTPUT_WIDTH-1:(i-1)*`LDPE_USED_OUTPUT_WIDTH]) + ); + end + endgenerate + +endmodule + +module compute_unit ( + input clk, + input start, + input reset, + input [`VRF_DWIDTH-1:0] vec, + input [`MRF_DWIDTH-1:0] mrf_in, + input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new + input mrf_we, mrf_we_for_dram, //new + input [`MRF_AWIDTH-1:0] mrf_addr, + input out_data_available_external_comparator_tree, + output out_data_available_internal_comparator_tree, + output out_data_available_dot_prod, + output [`LDPE_USED_OUTPUT_WIDTH-1:0] result, + output [`MRF_DWIDTH-1:0] mrf_outa_to_dram, //new + output [`BFLOAT_EXP-1:0] max_exp +); + + // Port B of BRAMs is used for feed DSPs and Port A is used to interact with DRAM + + + wire [`MRF_DWIDTH-1:0] mrf_outb_wire; + + wire [`LDPE_USED_INPUT_WIDTH-1:0] ax_wire; + wire [`LDPE_USED_INPUT_WIDTH-1:0] ay_wire; + wire [`LDPE_USED_INPUT_WIDTH-1:0] bx_wire; + wire [`LDPE_USED_INPUT_WIDTH-1:0] by_wire; + + // Wire connecting LDPE output to Output BRAM input + wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result; + + wire [`LDPE_USED_OUTPUT_WIDTH-1:0] inb_fake_wire; + + // First 4 BRAM outputs are given to ax of 4 DSPs and next 4 BRAM outputs are given to bx of DSPs + + // Connection MRF and LDPE wires for matrix data + // 'X' pin is used for matrix + /* If there are 4 DSPSs, bit[31:0] of mrf output contain ax values for the 4 DSPs, bit[63:32] contain bx values and so on. With a group of ax values, bit[7:0] contain ax value for DSP1, bit[15:8] contain ax value for DSP2 and so on. */ + assign ax_wire = mrf_outb_wire[1*`LDPE_USED_INPUT_WIDTH-1:0*`LDPE_USED_INPUT_WIDTH]; + assign bx_wire = mrf_outb_wire[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH]; + + // Connection of VRF and LDPE wires for vector data + // 'Y' pin is used for vector + assign ay_wire = vec[`LDPE_USED_INPUT_WIDTH-1:0]; + assign by_wire = vec[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH]; + + wire [`MRF_DWIDTH-1:0] mrf_in_fake; + + MRF mrf ( + .clk(clk), + .addra(mrf_addr_for_dram), + .addrb(mrf_addr), + .ina(mrf_in), + .inb(mrf_in_fake), + .wea(mrf_we_for_dram), + .web(mrf_we), + .outa(mrf_outa_to_dram), + .outb(mrf_outb_wire) + ); + + LDPE ldpe ( + .clk(clk), + .reset(reset), + .start(start), + .ax(ax_wire), + .ay(ay_wire), + .bx(bx_wire), + .by(by_wire), + .out_data_available_external_comparator_tree(out_data_available_external_comparator_tree), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree), + .out_data_available_dot_prod(out_data_available_dot_prod), + .ldpe_result(ldpe_result), + .max_exp(max_exp) + ); + assign result = ldpe_result; + +endmodule + +module LDPE ( + input clk, + input reset, + input start, + input [`LDPE_USED_INPUT_WIDTH-1:0] ax, + input [`LDPE_USED_INPUT_WIDTH-1:0] ay, + input [`LDPE_USED_INPUT_WIDTH-1:0] bx, + input [`LDPE_USED_INPUT_WIDTH-1:0] by, + input out_data_available_external_comparator_tree, + output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result, + output out_data_available_internal_comparator_tree, + output out_data_available_dot_prod, + output [`BFLOAT_EXP-1:0] max_exp +); + + + wire[`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] ax_in_sub_ldpe; + wire[`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] ay_in_sub_ldpe; + wire[`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] bx_in_sub_ldpe; + wire[`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] by_in_sub_ldpe; + wire [`LDPE_USED_OUTPUT_WIDTH-1:0] sub_ldpe_result; + wire[`DSPS_PER_LDPE-1:0] out_data_available_ax; + + genvar i; + generate + for (i=1; i<=`DSPS_PER_LDPE; i=i+1) begin: gen_fp16_to_msfp11_1 + fp16_to_msfp11 fp_converter_ax(.rst(reset),.start(start),.a(ax[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),.b(ax_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),.out_data_available(out_data_available_ax[i-1]),.clk(clk)); + end + endgenerate + + wire[`DSPS_PER_LDPE-1:0] out_data_available_ay; + + generate + for (i=1; i<=`DSPS_PER_LDPE; i=i+1) begin: gen_fp16_to_msfp11_2 + fp16_to_msfp11 fp_converter_ay(.rst(reset),.start(start),.a(ay[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),.b(ay_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),.out_data_available(out_data_available_ay[i-1]),.clk(clk)); + end + endgenerate + + wire[`DSPS_PER_LDPE-1:0] out_data_available_bx; + + generate + for (i=1; i<=`DSPS_PER_LDPE; i=i+1) begin: gen_fp16_to_msfp11_3 + fp16_to_msfp11 fp_converter_bx(.rst(reset),.start(start),.a(bx[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),.b(bx_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),.out_data_available(out_data_available_bx[i-1]),.clk(clk)); + end + endgenerate + + wire[`DSPS_PER_LDPE-1:0] out_data_available_by; + + generate + for (i=1; i<=`DSPS_PER_LDPE; i=i+1) begin: gen_fp16_to_msfp11_4 + fp16_to_msfp11 fp_converter_by(.rst(reset),.start(start),.a(by[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),.b(by_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),.out_data_available(out_data_available_by[i-1]),.clk(clk)); + end + endgenerate + wire start_subldpe; + assign start_subldpe = out_data_available_ax[0]; + + SUB_LDPE sub_1( + .clk(clk), + .reset(reset), + .start(start_subldpe), + .ax(ax_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .ay(ay_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .bx(bx_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .by(by_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .out_data_available_external_comparator_tree(out_data_available_external_comparator_tree), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree), + .out_data_available_dot_prod(out_data_available_dot_prod), + .result(sub_ldpe_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH]), + .max_exp(max_exp) + ); + + + assign ldpe_result = (start==1'b0) ? 27'd0 : sub_ldpe_result[(0+1)*`DSP_USED_OUTPUT_WIDTH-1:0*`DSP_USED_OUTPUT_WIDTH]; + + +endmodule + +module myadder #( + parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH, + parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH +) +( + input [INPUT_WIDTH-1:0] a, + input [INPUT_WIDTH-1:0] b, + input reset, + input start, + input clk, + output reg [OUTPUT_WIDTH-1:0] sum, + output reg out_data_available +); + + always@(posedge clk) begin + if((reset==1) || (start==0)) begin + sum <= 0; + out_data_available <= 0; + end + else begin + out_data_available <= 1; + sum <= a + b; + end + end + +endmodule + + +module SUB_LDPE ( + input clk, + input reset, + input start, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] ax, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] ay, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] bx, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] by, + input out_data_available_external_comparator_tree, + output reg [`LDPE_USED_OUTPUT_WIDTH-1:0] result, + output out_data_available_internal_comparator_tree, + output reg out_data_available_dot_prod, + output [`BFLOAT_EXP-1:0] max_exp +); + + + wire [`DSP_USED_OUTPUT_WIDTH*`DSPS_PER_SUB_LDPE-1:0] chainin, chainout, dsp_result; + + wire [36:0] chainout_temp_0; + assign chainout_temp_0 = 37'b0; + + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_1; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_1; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_1; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_1; + + wire [`BFLOAT_DWIDTH-1:0] ax_wire_1_num; + wire [`BFLOAT_DWIDTH-1:0] ay_wire_1_num; + wire [`BFLOAT_DWIDTH-1:0] bx_wire_1_num; + wire [`BFLOAT_DWIDTH-1:0] by_wire_1_num; + + wire [`BFLOAT_MANTISA_WITH_LO-1:0] ax_wire_1_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] ay_wire_1_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] bx_wire_1_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] by_wire_1_mantisa_shifted; + + assign ax_wire_1_num = ax[1*`BFLOAT_DWIDTH-1:(1-1)*`BFLOAT_DWIDTH]; + assign ay_wire_1_num = ay[1*`BFLOAT_DWIDTH-1:(1-1)*`BFLOAT_DWIDTH]; + assign bx_wire_1_num = bx[1*`BFLOAT_DWIDTH-1:(1-1)*`BFLOAT_DWIDTH]; + assign by_wire_1_num = by[1*`BFLOAT_DWIDTH-1:(1-1)*`BFLOAT_DWIDTH]; + + wire[`BFLOAT_EXP-1:0] shift_amt_1_ax; + assign shift_amt_1_ax = max_exp - ax_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + + wire out_data_available_barrel_shifter_ax_1; + wire start_barrel_shifter_ax_1; + + assign start_barrel_shifter_ax_1 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_ax_1( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_ax_1), + .out_data_available(out_data_available_barrel_shifter_ax_1), + .shift_amt(shift_amt_1_ax), + .significand({1'b1,ax_wire_1_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(ax_wire_1_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_1_ay; + assign shift_amt_1_ay = max_exp - ay_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_ay_1; + wire start_barrel_shifter_ay_1; + + assign start_barrel_shifter_ay_1 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_ay_1( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_ay_1), + .out_data_available(out_data_available_barrel_shifter_ay_1), + .shift_amt(shift_amt_1_ay), + .significand({1'b1,ay_wire_1_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(ay_wire_1_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_1_bx; + assign shift_amt_1_bx = max_exp - bx_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_bx_1; + wire start_barrel_shifter_bx_1; + + assign start_barrel_shifter_bx_1 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_bx_1( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_bx_1), + .out_data_available(out_data_available_barrel_shifter_bx_1), + .shift_amt(shift_amt_1_bx), + .significand({1'b1,bx_wire_1_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(bx_wire_1_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_1_by; + assign shift_amt_1_by = max_exp - by_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_by_1; + wire start_barrel_shifter_by_1; + + assign start_barrel_shifter_by_1 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_by_1( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_by_1), + .out_data_available(out_data_available_barrel_shifter_by_1), + .shift_amt(shift_amt_1_by), + .significand({1'b1,by_wire_1_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(by_wire_1_mantisa_shifted) + ); + + assign ax_wire_1 = (ax_wire_1_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax_wire_1_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax_wire_1_mantisa_shifted}; + assign ay_wire_1 = (ay_wire_1_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay_wire_1_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay_wire_1_mantisa_shifted}; + assign bx_wire_1 = (bx_wire_1_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx_wire_1_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx_wire_1_mantisa_shifted}; + assign by_wire_1 = (by_wire_1_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, by_wire_1_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, by_wire_1_mantisa_shifted}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_1; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_1; + + assign dsp_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_1[`DSP_USED_OUTPUT_WIDTH-1:0]; + + wire reset_dsp_1; + assign reset_dsp_1 = ~out_data_available_barrel_shifter_ax_1; + + dsp_block_18_18_int_sop_2 dsp_1 ( + .clk(clk), + .aclr(reset_dsp_1), + .ax(ax_wire_1), + .ay(ay_wire_1), + .bx(bx_wire_1), + .by(by_wire_1), + .chainin(chainout_temp_0), + .chainout(chainout_temp_1), + .result(result_temp_1) + ); + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_2; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_2; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_2; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_2; + + wire [`BFLOAT_DWIDTH-1:0] ax_wire_2_num; + wire [`BFLOAT_DWIDTH-1:0] ay_wire_2_num; + wire [`BFLOAT_DWIDTH-1:0] bx_wire_2_num; + wire [`BFLOAT_DWIDTH-1:0] by_wire_2_num; + + wire [`BFLOAT_MANTISA_WITH_LO-1:0] ax_wire_2_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] ay_wire_2_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] bx_wire_2_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] by_wire_2_mantisa_shifted; + + assign ax_wire_2_num = ax[2*`BFLOAT_DWIDTH-1:(2-1)*`BFLOAT_DWIDTH]; + assign ay_wire_2_num = ay[2*`BFLOAT_DWIDTH-1:(2-1)*`BFLOAT_DWIDTH]; + assign bx_wire_2_num = bx[2*`BFLOAT_DWIDTH-1:(2-1)*`BFLOAT_DWIDTH]; + assign by_wire_2_num = by[2*`BFLOAT_DWIDTH-1:(2-1)*`BFLOAT_DWIDTH]; + + wire[`BFLOAT_EXP-1:0] shift_amt_2_ax; + assign shift_amt_2_ax = max_exp - ax_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + + wire out_data_available_barrel_shifter_ax_2; + wire start_barrel_shifter_ax_2; + + assign start_barrel_shifter_ax_2 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_ax_2( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_ax_2), + .out_data_available(out_data_available_barrel_shifter_ax_2), + .shift_amt(shift_amt_2_ax), + .significand({1'b1,ax_wire_2_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(ax_wire_2_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_2_ay; + assign shift_amt_2_ay = max_exp - ay_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_ay_2; + wire start_barrel_shifter_ay_2; + + assign start_barrel_shifter_ay_2 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_ay_2( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_ay_2), + .out_data_available(out_data_available_barrel_shifter_ay_2), + .shift_amt(shift_amt_2_ay), + .significand({1'b1,ay_wire_2_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(ay_wire_2_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_2_bx; + assign shift_amt_2_bx = max_exp - bx_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_bx_2; + wire start_barrel_shifter_bx_2; + + assign start_barrel_shifter_bx_2 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_bx_2( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_bx_2), + .out_data_available(out_data_available_barrel_shifter_bx_2), + .shift_amt(shift_amt_2_bx), + .significand({1'b1,bx_wire_2_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(bx_wire_2_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_2_by; + assign shift_amt_2_by = max_exp - by_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_by_2; + wire start_barrel_shifter_by_2; + + assign start_barrel_shifter_by_2 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_by_2( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_by_2), + .out_data_available(out_data_available_barrel_shifter_by_2), + .shift_amt(shift_amt_2_by), + .significand({1'b1,by_wire_2_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(by_wire_2_mantisa_shifted) + ); + + assign ax_wire_2 = (ax_wire_2_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax_wire_2_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax_wire_2_mantisa_shifted}; + assign ay_wire_2 = (ay_wire_2_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay_wire_2_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay_wire_2_mantisa_shifted}; + assign bx_wire_2 = (bx_wire_2_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx_wire_2_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx_wire_2_mantisa_shifted}; + assign by_wire_2 = (by_wire_2_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, by_wire_2_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, by_wire_2_mantisa_shifted}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_2; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_2; + + assign dsp_result[2*`DSP_USED_OUTPUT_WIDTH-1:(2-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_2[`DSP_USED_OUTPUT_WIDTH-1:0]; + + wire reset_dsp_2; + assign reset_dsp_2 = ~out_data_available_barrel_shifter_ax_2; + + dsp_block_18_18_int_sop_2 dsp_2 ( + .clk(clk), + .aclr(reset_dsp_2), + .ax(ax_wire_2), + .ay(ay_wire_2), + .bx(bx_wire_2), + .by(by_wire_2), + .chainin(chainout_temp_1), + .chainout(chainout_temp_2), + .result(result_temp_2) + ); + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_3; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_3; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_3; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_3; + + wire [`BFLOAT_DWIDTH-1:0] ax_wire_3_num; + wire [`BFLOAT_DWIDTH-1:0] ay_wire_3_num; + wire [`BFLOAT_DWIDTH-1:0] bx_wire_3_num; + wire [`BFLOAT_DWIDTH-1:0] by_wire_3_num; + + wire [`BFLOAT_MANTISA_WITH_LO-1:0] ax_wire_3_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] ay_wire_3_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] bx_wire_3_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] by_wire_3_mantisa_shifted; + + assign ax_wire_3_num = ax[3*`BFLOAT_DWIDTH-1:(3-1)*`BFLOAT_DWIDTH]; + assign ay_wire_3_num = ay[3*`BFLOAT_DWIDTH-1:(3-1)*`BFLOAT_DWIDTH]; + assign bx_wire_3_num = bx[3*`BFLOAT_DWIDTH-1:(3-1)*`BFLOAT_DWIDTH]; + assign by_wire_3_num = by[3*`BFLOAT_DWIDTH-1:(3-1)*`BFLOAT_DWIDTH]; + + wire[`BFLOAT_EXP-1:0] shift_amt_3_ax; + assign shift_amt_3_ax = max_exp - ax_wire_3_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + + wire out_data_available_barrel_shifter_ax_3; + wire start_barrel_shifter_ax_3; + + assign start_barrel_shifter_ax_3 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_ax_3( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_ax_3), + .out_data_available(out_data_available_barrel_shifter_ax_3), + .shift_amt(shift_amt_3_ax), + .significand({1'b1,ax_wire_3_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(ax_wire_3_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_3_ay; + assign shift_amt_3_ay = max_exp - ay_wire_3_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_ay_3; + wire start_barrel_shifter_ay_3; + + assign start_barrel_shifter_ay_3 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_ay_3( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_ay_3), + .out_data_available(out_data_available_barrel_shifter_ay_3), + .shift_amt(shift_amt_3_ay), + .significand({1'b1,ay_wire_3_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(ay_wire_3_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_3_bx; + assign shift_amt_3_bx = max_exp - bx_wire_3_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_bx_3; + wire start_barrel_shifter_bx_3; + + assign start_barrel_shifter_bx_3 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_bx_3( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_bx_3), + .out_data_available(out_data_available_barrel_shifter_bx_3), + .shift_amt(shift_amt_3_bx), + .significand({1'b1,bx_wire_3_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(bx_wire_3_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_3_by; + assign shift_amt_3_by = max_exp - by_wire_3_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_by_3; + wire start_barrel_shifter_by_3; + + assign start_barrel_shifter_by_3 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_by_3( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_by_3), + .out_data_available(out_data_available_barrel_shifter_by_3), + .shift_amt(shift_amt_3_by), + .significand({1'b1,by_wire_3_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(by_wire_3_mantisa_shifted) + ); + + assign ax_wire_3 = (ax_wire_3_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax_wire_3_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax_wire_3_mantisa_shifted}; + assign ay_wire_3 = (ay_wire_3_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay_wire_3_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay_wire_3_mantisa_shifted}; + assign bx_wire_3 = (bx_wire_3_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx_wire_3_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx_wire_3_mantisa_shifted}; + assign by_wire_3 = (by_wire_3_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, by_wire_3_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, by_wire_3_mantisa_shifted}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_3; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_3; + + assign dsp_result[3*`DSP_USED_OUTPUT_WIDTH-1:(3-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_3[`DSP_USED_OUTPUT_WIDTH-1:0]; + + wire reset_dsp_3; + assign reset_dsp_3 = ~out_data_available_barrel_shifter_ax_3; + + dsp_block_18_18_int_sop_2 dsp_3 ( + .clk(clk), + .aclr(reset_dsp_3), + .ax(ax_wire_3), + .ay(ay_wire_3), + .bx(bx_wire_3), + .by(by_wire_3), + .chainin(chainout_temp_2), + .chainout(chainout_temp_3), + .result(result_temp_3) + ); + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_4; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_4; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_4; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_4; + + wire [`BFLOAT_DWIDTH-1:0] ax_wire_4_num; + wire [`BFLOAT_DWIDTH-1:0] ay_wire_4_num; + wire [`BFLOAT_DWIDTH-1:0] bx_wire_4_num; + wire [`BFLOAT_DWIDTH-1:0] by_wire_4_num; + + wire [`BFLOAT_MANTISA_WITH_LO-1:0] ax_wire_4_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] ay_wire_4_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] bx_wire_4_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] by_wire_4_mantisa_shifted; + + assign ax_wire_4_num = ax[4*`BFLOAT_DWIDTH-1:(4-1)*`BFLOAT_DWIDTH]; + assign ay_wire_4_num = ay[4*`BFLOAT_DWIDTH-1:(4-1)*`BFLOAT_DWIDTH]; + assign bx_wire_4_num = bx[4*`BFLOAT_DWIDTH-1:(4-1)*`BFLOAT_DWIDTH]; + assign by_wire_4_num = by[4*`BFLOAT_DWIDTH-1:(4-1)*`BFLOAT_DWIDTH]; + + wire[`BFLOAT_EXP-1:0] shift_amt_4_ax; + assign shift_amt_4_ax = max_exp - ax_wire_4_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + + wire out_data_available_barrel_shifter_ax_4; + wire start_barrel_shifter_ax_4; + + assign start_barrel_shifter_ax_4 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_ax_4( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_ax_4), + .out_data_available(out_data_available_barrel_shifter_ax_4), + .shift_amt(shift_amt_4_ax), + .significand({1'b1,ax_wire_4_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(ax_wire_4_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_4_ay; + assign shift_amt_4_ay = max_exp - ay_wire_4_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_ay_4; + wire start_barrel_shifter_ay_4; + + assign start_barrel_shifter_ay_4 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_ay_4( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_ay_4), + .out_data_available(out_data_available_barrel_shifter_ay_4), + .shift_amt(shift_amt_4_ay), + .significand({1'b1,ay_wire_4_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(ay_wire_4_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_4_bx; + assign shift_amt_4_bx = max_exp - bx_wire_4_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_bx_4; + wire start_barrel_shifter_bx_4; + + assign start_barrel_shifter_bx_4 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_bx_4( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_bx_4), + .out_data_available(out_data_available_barrel_shifter_bx_4), + .shift_amt(shift_amt_4_bx), + .significand({1'b1,bx_wire_4_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(bx_wire_4_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_4_by; + assign shift_amt_4_by = max_exp - by_wire_4_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_by_4; + wire start_barrel_shifter_by_4; + + assign start_barrel_shifter_by_4 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_by_4( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_by_4), + .out_data_available(out_data_available_barrel_shifter_by_4), + .shift_amt(shift_amt_4_by), + .significand({1'b1,by_wire_4_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(by_wire_4_mantisa_shifted) + ); + + assign ax_wire_4 = (ax_wire_4_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax_wire_4_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax_wire_4_mantisa_shifted}; + assign ay_wire_4 = (ay_wire_4_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay_wire_4_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay_wire_4_mantisa_shifted}; + assign bx_wire_4 = (bx_wire_4_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx_wire_4_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx_wire_4_mantisa_shifted}; + assign by_wire_4 = (by_wire_4_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, by_wire_4_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, by_wire_4_mantisa_shifted}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_4; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_4; + + assign dsp_result[4*`DSP_USED_OUTPUT_WIDTH-1:(4-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_4[`DSP_USED_OUTPUT_WIDTH-1:0]; + + wire reset_dsp_4; + assign reset_dsp_4 = ~out_data_available_barrel_shifter_ax_4; + + dsp_block_18_18_int_sop_2 dsp_4 ( + .clk(clk), + .aclr(reset_dsp_4), + .ax(ax_wire_4), + .ay(ay_wire_4), + .bx(bx_wire_4), + .by(by_wire_4), + .chainin(chainout_temp_3), + .chainout(chainout_temp_4), + .result(result_temp_4) + ); + + +exponent_comparator_tree_ldpe exp_cmp ( + .clk(clk), + .reset(reset), + .start(start), + .out_data_available(out_data_available_internal_comparator_tree), + .inp0(ax_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp1(ax_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp2(ax_wire_3_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp3(ax_wire_4_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp4(ay_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp5(ay_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp6(ay_wire_3_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp7(ay_wire_4_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp8(bx_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp9(bx_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp10(bx_wire_3_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp11(bx_wire_4_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp12(by_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp13(by_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp14(by_wire_3_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp15(by_wire_4_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .result_final_stage(max_exp) +); + + + always @(*) begin + if (reset==1'b1 || start==1'b0) begin + result <= {`LDPE_USED_OUTPUT_WIDTH{1'd0}}; + end + else begin + result <= dsp_result[`DSPS_PER_SUB_LDPE*`LDPE_USED_OUTPUT_WIDTH-1:(`DSPS_PER_SUB_LDPE-1)*`LDPE_USED_OUTPUT_WIDTH]; + end + end + + + reg [4:0] num_cycles_mvm; + + always@(posedge clk) begin + if((reset==1'b1) || (out_data_available_barrel_shifter_ax_1==1'b0)) begin + num_cycles_mvm<=0; + out_data_available_dot_prod<=0; + end + else begin + if(num_cycles_mvm==`NUM_MVM_CYCLES-1) begin + out_data_available_dot_prod <= 1; + end + else begin + num_cycles_mvm <= num_cycles_mvm + 1'b1; + end + end + end + +endmodule + +module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) ( + input clk, + input [VRF_AWIDTH-1:0] addra, addrb, + input [VRF_DWIDTH-1:0] ina, inb, + input wea, web, + output [VRF_DWIDTH-1:0] outa, outb +); + + dp_ram # ( + .AWIDTH(VRF_AWIDTH), + .DWIDTH(VRF_DWIDTH) + ) vec_mem ( + .clk(clk), + .addra(addra), + .ina(ina), + .wea(wea), + .outa(outa), + .addrb(addrb), + .inb(inb), + .web(web), + .outb(outb) + ); + +endmodule + +module MRF ( + input clk, + input [`MRF_AWIDTH-1:0] addra, addrb, + input [`MRF_DWIDTH-1:0] ina, inb, + input wea, web, + output [`MRF_DWIDTH-1:0] outa, outb +); + + dp_ram # ( + .AWIDTH(`MRF_AWIDTH), + .DWIDTH(`MRF_DWIDTH) + ) vec_mem ( + .clk(clk), + .addra(addra), + .ina(ina), + .wea(wea), + .outa(outa), + .addrb(addrb), + .inb(inb), + .web(web), + .outb(outb) + ); + +endmodule + +module dsp_block_18_18_int_sop_2 ( + input clk, + input aclr, + input [`DSP_X_AVA_INPUT_WIDTH-1:0] ax, + input [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay, + input [`DSP_X_AVA_INPUT_WIDTH-1:0] bx, + input [`DSP_Y_AVA_INPUT_WIDTH-1:0] by, + input [`DSP_AVA_OUTPUT_WIDTH-1:0] chainin, + output [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout, + output [`DSP_AVA_OUTPUT_WIDTH-1:0] result +); + +`ifndef complex_dsp + +reg [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_reg; +reg [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_reg; +reg [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_reg; +reg [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_reg; +reg [`DSP_AVA_OUTPUT_WIDTH-1:0] result_reg; + +always @(posedge clk) begin + if(aclr) begin + result_reg <= 0; + ax_reg <= 0; + ay_reg <= 0; + bx_reg <= 0; + by_reg <= 0; + end + else begin + ax_reg <= ax; + ay_reg <= ay; + bx_reg <= bx; + by_reg <= by; + result_reg <= (ax_reg * ay_reg) + (bx_reg * by_reg) + chainin; + end +end +assign chainout = result_reg; +assign result = result_reg; + +`else + +wire [11:0] mode; +assign mode = 12'b0101_0101_0011; + +int_sop_2 mac_component ( + .mode_sigs(mode), + .clk(clk), + .reset(aclr), + .ax(ax), + .ay(ay), + .bx(bx), + .by(by), + .chainin(chainin), + .result(result), + .chainout(chainout) +); + +`endif + +endmodule + +////////////////////////////////// +// Dual port RAM +////////////////////////////////// + +module dp_ram # ( + parameter AWIDTH = 10, + parameter DWIDTH = 16 +) ( + input clk, + input [AWIDTH-1:0] addra, addrb, + input [DWIDTH-1:0] ina, inb, + input wea, web, + output reg [DWIDTH-1:0] outa, outb +); + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram [((1<b) ? a : b; + out_data_available <= 1; + end + end +endmodule + +module fp16_to_msfp11 (input clk, input [15:0] a , input rst, input start, output reg [10:0] b, output reg out_data_available); + +reg [10:0]b_temp; + +always @ (*) begin + +if ( a [14: 0] == 15'b0 ) begin //signed zero + b_temp [10] = a[15]; //sign bit + b_temp [9:0] = 7'b0000000; //EXPONENT AND MANTISSA +end + +else begin + + b_temp [4:0] = a[9:5]; //MANTISSA + b_temp [9:5] = a[14:10]; //EXPONENT NOTE- EXPONENT SIZE IS SAME IN BOTH + b_temp [10] = a[15]; //SIGN + end +end + +always@(posedge clk) begin + if((rst==1'b1) || (start==1'b0)) begin + b <= 11'd0; + out_data_available <= 0; + end + else begin + b <= b_temp; + out_data_available <= 1; + end +end + + +endmodule + + +module msfp11_to_fp16 (input reset, input start, input clk, input [10:0] a , output reg [15:0] b, output reg out_data_available); + +reg [15:0]b_temp; +reg [3:0] j; +reg [2:0] k; +reg [2:0] k_temp; + +always @ (*) begin + +if ( a [9: 0] == 7'b0 ) begin //signed zero + b_temp [15] = a[10]; //sign bit + b_temp[14:0] = 15'b0; +end + +else begin +/* + if ( a[9:5] == 5'b0 ) begin //denormalized (covert to normalized) + + for (j=0; j<=4; j=j+1) begin + if (a[j] == 1'b1) begin + k_temp = j; + end + end + k = 1 - k_temp; + + b_temp [9:0] = ( (a [4:0] << (k+1'b1)) & 5'b11111 ) << 5; + //b_temp [14:10] = 5'd31 - 5'd31 - k; //PROBLEM - DISCUSS THIS ************ SHOULD BE +k + b_temp [14:10] = 5'd31 - 5'd31 + k; + b_temp [15] = a[10]; + end +*/ + if ( a[9:5] == 5'b11111 ) begin //Infinity/ NAN //removed else here + b_temp [9:0] = a [4:0] << 5; + b_temp [14:10] = 5'b11111; + b_temp [15] = a[10]; + end + + else begin //Normalized Number + b_temp [9:0] = a [4:0] << 5; + b_temp [14:10] = 5'd31 - 5'd31 + a[6:2]; + b_temp [15] = a[10]; + end +end +end + +always@(posedge clk) begin + if((reset==1'b1) || (start==1'b0)) begin + out_data_available <= 0; + b <= 16'd0; + end + else begin + b <= b_temp; + out_data_available <= 1; + end +end + +endmodule +module FPAddSub( + //bf16, + clk, + rst, + a, + b, + operation, // 0 add, 1 sub + result, + flags + ); + //input bf16; //1 for Bfloat16, 0 for IEEE half precision + + // Clock and reset + input clk ; // Clock signal + input rst ; // Reset (active high, resets pipeline registers) + + // Input ports + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + input operation ; // Operation select signal + + // Output ports + output [`DWIDTH-1:0] result ; // Result of the operation + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Pipeline Registers + //reg [79:0] pipe_1; // Pipeline register PreAlign->Align1 + reg [2*`EXPONENT + 2*`DWIDTH + 5:0] pipe_1; // Pipeline register PreAlign->Align1 + + //reg [67:0] pipe_2; // Pipeline register Align1->Align3 + //reg [2*`EXPONENT+ 2*`MANTISSA + 8:0] pipe_2; // Pipeline register Align1->Align3 + wire [2*`EXPONENT+ 2*`MANTISSA + 8:0] pipe_2; + + //reg [76:0] pipe_3; 68 // Pipeline register Align1->Align3 + reg [2*`EXPONENT+ 2*`MANTISSA + 9:0] pipe_3; // Pipeline register Align1->Align3 + + //reg [69:0] pipe_4; // Pipeline register Align3->Execute + //reg [2*`EXPONENT+ 2*`MANTISSA + 9:0] pipe_4; // Pipeline register Align3->Execute + wire [2*`EXPONENT+ 2*`MANTISSA + 9:0] pipe_4; + + //reg [51:0] pipe_5; // Pipeline register Execute->Normalize + reg [`DWIDTH+`EXPONENT+11:0] pipe_5; // Pipeline register Execute->Normalize + + //reg [56:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + //reg [`DWIDTH+`EXPONENT+16:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + wire [`DWIDTH+`EXPONENT+16:0] pipe_6; + + //reg [56:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + //reg [`DWIDTH+`EXPONENT+16:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + wire [`DWIDTH+`EXPONENT+16:0] pipe_7; + //reg [54:0] pipe_8; // Pipeline register NormalizeShift3->Round + reg [`EXPONENT*2+`MANTISSA+15:0] pipe_8; // Pipeline register NormalizeShift3->Round + + //reg [40:0] pipe_9; // Pipeline register NormalizeShift3->Round + //reg [`DWIDTH+8:0] pipe_9; // Pipeline register NormalizeShift3->Round + wire [`DWIDTH+8:0] pipe_9; + + // Internal wires between modules + wire [`DWIDTH-2:0] Aout_0 ; // A - sign + wire [`DWIDTH-2:0] Bout_0 ; // B - sign + wire Opout_0 ; // A's sign + wire Sa_0 ; // A's sign + wire Sb_0 ; // B's sign + wire MaxAB_1 ; // Indicates the larger of A and B(0/A, 1/B) + wire [`EXPONENT-1:0] CExp_1 ; // Common Exponent + wire [`EXPONENT-1:0] Shift_1 ; // Number of steps to smaller mantissa shift right (align) + wire [`MANTISSA-1:0] Mmax_1 ; // Larger mantissa + wire [4:0] InputExc_0 ; // Input numbers are exceptions + wire [2*`EXPONENT-1:0] ShiftDet_0 ; + wire [`MANTISSA-1:0] MminS_1 ; // Smaller mantissa after 0/16 shift + wire [`MANTISSA:0] MminS_2 ; // Smaller mantissa after 0/4/8/12 shift + wire [`MANTISSA:0] Mmin_3 ; // Smaller mantissa after 0/1/2/3 shift + wire [`DWIDTH:0] Sum_4 ; + wire PSgn_4 ; + wire Opr_4 ; + wire [`EXPONENT-1:0] Shift_5 ; // Number of steps to shift sum left (normalize) + wire [`DWIDTH:0] SumS_5 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_6 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_7 ; // Sum after 0/16 shift + wire [`MANTISSA-1:0] NormM_8 ; // Normalized mantissa + wire [`EXPONENT:0] NormE_8; // Adjusted exponent + wire ZeroSum_8 ; // Zero flag + wire NegE_8 ; // Flag indicating negative exponent + wire R_8 ; // Round bit + wire S_8 ; // Final sticky bit + wire FG_8 ; // Final sticky bit + wire [`DWIDTH-1:0] P_int ; + wire EOF ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_PrealignModule PrealignModule + ( // Inputs + a, b, operation, + // Outputs + Sa_0, Sb_0, ShiftDet_0[2*`EXPONENT-1:0], InputExc_0[4:0], Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Opout_0) ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_AlignModule AlignModule + ( // Inputs + pipe_1[2*`EXPONENT + 2*`DWIDTH + 4: 2*`EXPONENT +`DWIDTH + 6], pipe_1[2*`EXPONENT +`DWIDTH + 5 : 2*`EXPONENT +7], pipe_1[2*`EXPONENT+4:5], + // Outputs + CExp_1[`EXPONENT-1:0], MaxAB_1, Shift_1[`EXPONENT-1:0], MminS_1[`MANTISSA-1:0], Mmax_1[`MANTISSA-1:0]) ; + + // Alignment Shift Stage 1 + FPAddSub_AlignShift1 AlignShift1 + ( // Inputs + //bf16, + pipe_2[`MANTISSA-1:0], pipe_2[`EXPONENT+ 2*`MANTISSA + 4 : 2*`MANTISSA + 7], + // Outputs + MminS_2[`MANTISSA:0]) ; + + // Alignment Shift Stage 3 and compution of guard and sticky bits + FPAddSub_AlignShift2 AlignShift2 + ( // Inputs + pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+7:2*`MANTISSA+6], + // Outputs + Mmin_3[`MANTISSA:0]) ; + + // Perform mantissa addition + FPAddSub_ExecutionModule ExecutionModule + ( // Inputs + pipe_4[`MANTISSA*2+5:`MANTISSA+6], pipe_4[`MANTISSA:0], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 8], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 7], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 6], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 9], + // Outputs + Sum_4[`DWIDTH:0], PSgn_4, Opr_4) ; + + // Prepare normalization of result + FPAddSub_NormalizeModule NormalizeModule + ( // Inputs + pipe_5[`DWIDTH:0], + // Outputs + SumS_5[`DWIDTH:0], Shift_5[4:0]) ; + + // Normalization Shift Stage 1 + FPAddSub_NormalizeShift1 NormalizeShift1 + ( // Inputs + pipe_6[`DWIDTH:0], pipe_6[`DWIDTH+`EXPONENT+14:`DWIDTH+`EXPONENT+11], + // Outputs + SumS_7[`DWIDTH:0]) ; + + // Normalization Shift Stage 3 and final guard, sticky and round bits + FPAddSub_NormalizeShift2 NormalizeShift2 + ( // Inputs + pipe_7[`DWIDTH:0], pipe_7[`DWIDTH+`EXPONENT+5:`DWIDTH+6], pipe_7[`DWIDTH+`EXPONENT+15:`DWIDTH+`EXPONENT+11], + // Outputs + NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8, FG_8) ; + + // Round and put result together + FPAddSub_RoundModule RoundModule + ( // Inputs + pipe_8[3], pipe_8[4+`EXPONENT:4], pipe_8[`EXPONENT+`MANTISSA+4:5+`EXPONENT], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT*2+`MANTISSA+15], pipe_8[`EXPONENT*2+`MANTISSA+12], pipe_8[`EXPONENT*2+`MANTISSA+11], pipe_8[`EXPONENT*2+`MANTISSA+14], pipe_8[`EXPONENT*2+`MANTISSA+10], + // Outputs + P_int[`DWIDTH-1:0], EOF) ; + + // Check for exceptions + FPAddSub_ExceptionModule Exceptionmodule + ( // Inputs + pipe_9[8+`DWIDTH:9], pipe_9[8], pipe_9[7], pipe_9[6], pipe_9[5:1], pipe_9[0], + // Outputs + result[`DWIDTH-1:0], flags[4:0]) ; + + +assign pipe_2 = {pipe_1[2*`EXPONENT + 2*`DWIDTH + 5], pipe_1[2*`EXPONENT +6:2*`EXPONENT +5], MaxAB_1, CExp_1[`EXPONENT-1:0], Shift_1[`EXPONENT-1:0], Mmax_1[`MANTISSA-1:0], pipe_1[4:0], MminS_1[`MANTISSA-1:0]} ; +assign pipe_4 = {pipe_3[2*`EXPONENT+ 2*`MANTISSA + 9:`MANTISSA+1], Mmin_3[`MANTISSA:0]} ; +assign pipe_6 = {pipe_5[`DWIDTH+`EXPONENT+11], Shift_5[4:0], pipe_5[`DWIDTH+`EXPONENT+10:`DWIDTH+1], SumS_5[`DWIDTH:0]} ; +assign pipe_7 = {pipe_6[`DWIDTH+`EXPONENT+16:`DWIDTH+1], SumS_7[`DWIDTH:0]} ; +assign pipe_9 = {P_int[`DWIDTH-1:0], pipe_8[2], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT+`MANTISSA+9:`EXPONENT+`MANTISSA+5], EOF} ; + + always @ (posedge clk) begin + if(rst) begin + pipe_1 <= 0; + //pipe_2 <= 0; + pipe_3 <= 0; + //pipe_4 <= 0; + pipe_5 <= 0; + //pipe_6 <= 0; + //pipe_7 <= 0; + pipe_8 <= 0; + //pipe_9 <= 0; + end + else begin +/* PIPE_1: + [2*`EXPONENT + 2*`DWIDTH + 5] Opout_0 + [2*`EXPONENT + 2*`DWIDTH + 4: 2*`EXPONENT +`DWIDTH + 6] A_out0 + [2*`EXPONENT +`DWIDTH + 5 : 2*`EXPONENT +7] Bout_0 + [2*`EXPONENT +6] Sa_0 + [2*`EXPONENT +5] Sb_0 + [2*`EXPONENT +4 : 5] ShiftDet_0 + [4:0] Input Exc +*/ + pipe_1 <= {Opout_0, Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Sa_0, Sb_0, ShiftDet_0[2*`EXPONENT -1:0], InputExc_0[4:0]} ; +/* PIPE_2 +[2*`EXPONENT+ 2*`MANTISSA + 8] operation +[2*`EXPONENT+ 2*`MANTISSA + 7] Sa_0 +[2*`EXPONENT+ 2*`MANTISSA + 6] Sb_0 +[2*`EXPONENT+ 2*`MANTISSA + 5] MaxAB_0 +[2*`EXPONENT+ 2*`MANTISSA + 4:`EXPONENT+ 2*`MANTISSA + 5] CExp_0 +[`EXPONENT+ 2*`MANTISSA + 4 : 2*`MANTISSA + 5] Shift_0 +[2*`MANTISSA + 4:`MANTISSA + 5] Mmax_0 +[`MANTISSA + 4 : `MANTISSA] InputExc_0 +[`MANTISSA-1:0] MminS_1 +*/ + //pipe_2 <= {pipe_1[2*`EXPONENT + 2*`DWIDTH + 5], pipe_1[2*`EXPONENT +6:2*`EXPONENT +5], MaxAB_1, CExp_1[`EXPONENT-1:0], Shift_1[`EXPONENT-1:0], Mmax_1[`MANTISSA-1:0], pipe_1[4:0], MminS_1[`MANTISSA-1:0]} ; +/* PIPE_3 +[2*`EXPONENT+ 2*`MANTISSA + 9] operation +[2*`EXPONENT+ 2*`MANTISSA + 8] Sa_0 +[2*`EXPONENT+ 2*`MANTISSA + 7] Sb_0 +[2*`EXPONENT+ 2*`MANTISSA + 6] MaxAB_0 +[2*`EXPONENT+ 2*`MANTISSA + 5:`EXPONENT+ 2*`MANTISSA + 6] CExp_0 +[`EXPONENT+ 2*`MANTISSA + 5 : 2*`MANTISSA + 6] Shift_0 +[2*`MANTISSA + 5:`MANTISSA + 6] Mmax_0 +[`MANTISSA + 5 : `MANTISSA + 1] InputExc_0 +[`MANTISSA:0] MminS_2 +*/ + pipe_3 <= {pipe_2[2*`EXPONENT+ 2*`MANTISSA + 8:`MANTISSA], MminS_2[`MANTISSA:0]} ; +/* PIPE_4 +[2*`EXPONENT+ 2*`MANTISSA + 9] operation +[2*`EXPONENT+ 2*`MANTISSA + 8] Sa_0 +[2*`EXPONENT+ 2*`MANTISSA + 7] Sb_0 +[2*`EXPONENT+ 2*`MANTISSA + 6] MaxAB_0 +[2*`EXPONENT+ 2*`MANTISSA + 5:`EXPONENT+ 2*`MANTISSA + 6] CExp_0 +[`EXPONENT+ 2*`MANTISSA + 5 : 2*`MANTISSA + 6] Shift_0 +[2*`MANTISSA + 5:`MANTISSA + 6] Mmax_0 +[`MANTISSA + 5 : `MANTISSA + 1] InputExc_0 +[`MANTISSA:0] MminS_3 +*/ + //pipe_4 <= {pipe_3[2*`EXPONENT+ 2*`MANTISSA + 9:`MANTISSA+1], Mmin_3[`MANTISSA:0]} ; +/* PIPE_5 : +[`DWIDTH+ `EXPONENT + 11] operation +[`DWIDTH+ `EXPONENT + 10] PSgn_4 +[`DWIDTH+ `EXPONENT + 9] Opr_4 +[`DWIDTH+ `EXPONENT + 8] Sa_0 +[`DWIDTH+ `EXPONENT + 7] Sb_0 +[`DWIDTH+ `EXPONENT + 6] MaxAB_0 +[`DWIDTH+ `EXPONENT + 5 :`DWIDTH+6] CExp_0 +[`DWIDTH+5:`DWIDTH+1] InputExc_0 +[`DWIDTH:0] Sum_4 +*/ + pipe_5 <= {pipe_4[2*`EXPONENT+ 2*`MANTISSA + 9], PSgn_4, Opr_4, pipe_4[2*`EXPONENT+ 2*`MANTISSA + 8:`EXPONENT+ 2*`MANTISSA + 6], pipe_4[`MANTISSA+5:`MANTISSA+1], Sum_4[`DWIDTH:0]} ; +/* PIPE_6 : +[`DWIDTH+ `EXPONENT + 16] operation +[`DWIDTH+ `EXPONENT + 15:`DWIDTH+ `EXPONENT + 11] Shift_5 +[`DWIDTH+ `EXPONENT + 10] PSgn_4 +[`DWIDTH+ `EXPONENT + 9] Opr_4 +[`DWIDTH+ `EXPONENT + 8] Sa_0 +[`DWIDTH+ `EXPONENT + 7] Sb_0 +[`DWIDTH+ `EXPONENT + 6] MaxAB_0 +[`DWIDTH+ `EXPONENT + 5 :`DWIDTH+6] CExp_0 +[`DWIDTH+5:`DWIDTH+1] InputExc_0 +[`DWIDTH:0] Sum_4 +*/ + //pipe_6 <= {pipe_5[`DWIDTH+`EXPONENT+11], Shift_5[4:0], pipe_5[`DWIDTH+`EXPONENT+10:`DWIDTH+1], SumS_5[`DWIDTH:0]} ; +/* PIPE_7 : +[`DWIDTH+ `EXPONENT + 16] operation +[`DWIDTH+ `EXPONENT + 15:`DWIDTH+ `EXPONENT + 11] Shift_5 +[`DWIDTH+ `EXPONENT + 10] PSgn_4 +[`DWIDTH+ `EXPONENT + 9] Opr_4 +[`DWIDTH+ `EXPONENT + 8] Sa_0 +[`DWIDTH+ `EXPONENT + 7] Sb_0 +[`DWIDTH+ `EXPONENT + 6] MaxAB_0 +[`DWIDTH+ `EXPONENT + 5 :`DWIDTH+6] CExp_0 +[`DWIDTH+5:`DWIDTH+1] InputExc_0 +[`DWIDTH:0] Sum_4 +*/ + //pipe_7 <= {pipe_6[`DWIDTH+`EXPONENT+16:`DWIDTH+1], SumS_7[`DWIDTH:0]} ; +/* PIPE_8: +[2*`EXPONENT + `MANTISSA + 15] FG_8 +[2*`EXPONENT + `MANTISSA + 14] operation +[2*`EXPONENT + `MANTISSA + 13] PSgn_4 +[2*`EXPONENT + `MANTISSA + 12] Sa_0 +[2*`EXPONENT + `MANTISSA + 11] Sb_0 +[2*`EXPONENT + `MANTISSA + 10] MaxAB_0 +[2*`EXPONENT + `MANTISSA + 9:`EXPONENT + `MANTISSA + 10] CExp_0 +[`EXPONENT + `MANTISSA + 9:`EXPONENT + `MANTISSA + 5] InputExc_8 +[`EXPONENT + `MANTISSA + 4 :`EXPONENT + 5] NormM_8 +[`EXPONENT + 4 :4] NormE_8 +[3] ZeroSum_8 +[2] NegE_8 +[1] R_8 +[0] S_8 +*/ + pipe_8 <= {FG_8, pipe_7[`DWIDTH+`EXPONENT+16], pipe_7[`DWIDTH+`EXPONENT+10], pipe_7[`DWIDTH+`EXPONENT+8:`DWIDTH+1], NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8} ; +/* pipe_9: +[`DWIDTH + 8 :9] P_int +[8] NegE_8 +[7] R_8 +[6] S_8 +[5:1] InputExc_8 +[0] EOF +*/ + //pipe_9 <= {P_int[`DWIDTH-1:0], pipe_8[2], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT+`MANTISSA+9:`EXPONENT+`MANTISSA+5], EOF} ; + end + end + +endmodule + + +// +// Description: The pre-alignment module is responsible for taking the inputs +// apart and checking the parts for exceptions. +// The exponent difference is also calculated in this module. +// + + +module FPAddSub_PrealignModule( + A, + B, + operation, + Sa, + Sb, + ShiftDet, + InputExc, + Aout, + Bout, + Opout + ); + + // Input ports + input [`DWIDTH-1:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] B ; // Input B, a 32-bit floating point number + input operation ; + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [2*`EXPONENT-1:0] ShiftDet ; + output [4:0] InputExc ; // Input numbers are exceptions + output [`DWIDTH-2:0] Aout ; + output [`DWIDTH-2:0] Bout ; + output Opout ; + + // Internal signals // If signal is high... + wire ANaN ; // A is a NaN (Not-a-Number) + wire BNaN ; // B is a NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`EXPONENT-1:0] DAB ; // ExpA - ExpB + wire [`EXPONENT-1:0] DBA ; // ExpB - ExpA + + assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + + // Put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + + //assign DAB = (A[30:23] - B[30:23]) ; + //assign DBA = (B[30:23] - A[30:23]) ; + assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1'b1) ; + assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1'b1) ; + + assign Sa = A[`DWIDTH-1] ; // A's sign bit + assign Sb = B[`DWIDTH-1] ; // B's sign bit + assign ShiftDet = {DBA[`EXPONENT-1:0], DAB[`EXPONENT-1:0]} ; // Shift data + assign Opout = operation ; + assign Aout = A[`DWIDTH-2:0] ; + assign Bout = B[`DWIDTH-2:0] ; + +endmodule + + +// +// Description: The alignment module determines the larger input operand and +// sets the mantissas, shift and common exponent accordingly. +// + + +module FPAddSub_AlignModule ( + A, + B, + ShiftDet, + CExp, + MaxAB, + Shift, + Mmin, + Mmax + ); + + // Input ports + input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-2:0] B ; // Input B, a 32-bit floating point number + input [2*`EXPONENT-1:0] ShiftDet ; + + // Output ports + output [`EXPONENT-1:0] CExp ; // Common Exponent + output MaxAB ; // Incidates larger of A and B (0/A, 1/B) + output [`EXPONENT-1:0] Shift ; // Number of steps to smaller mantissa shift right + output [`MANTISSA-1:0] Mmin ; // Smaller mantissa + output [`MANTISSA-1:0] Mmax ; // Larger mantissa + + // Internal signals + //wire BOF ; // Check for shifting overflow if B is larger + //wire AOF ; // Check for shifting overflow if A is larger + + assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]) ; + //assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits + //assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits + + // Determine final shift value + //assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ; + + assign Shift = MaxAB ? ShiftDet[2*`EXPONENT-1:`EXPONENT] : ShiftDet[`EXPONENT-1:0] ; + + // Take out smaller mantissa and append shift space + assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0] ; + + // Take out larger mantissa + assign Mmax = MaxAB ? B[`MANTISSA-1:0]: A[`MANTISSA-1:0] ; + + // Common exponent + assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]) ; + +endmodule + + +// Description: Alignment shift stage 1, performs 16|12|8|4 shift +// + + +// ONLY THIS MODULE IS HARDCODED for half precision fp16 and bfloat16 +module FPAddSub_AlignShift1( + //bf16, + MminP, + Shift, + Mmin + ); + + // Input ports + //input bf16; + input [`MANTISSA-1:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bits + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + + wire bf16; + `ifdef BFLOAT16 + assign bf16 = 1'b1; + `else + assign bf16 = 1'b0; + `endif + + // Internal signals + reg [`MANTISSA:0] Lvl1; + reg [`MANTISSA:0] Lvl2; + wire [2*`MANTISSA+1:0] Stage1; + integer i; // Loop variable + + always @(*) begin + if (bf16 == 1'b1) begin +//hardcoding for bfloat16 + //For bfloat16, we can shift the mantissa by a max of 7 bits since mantissa has a width of 7. + //Hence if either, bit[3]/bit[4]/bit[5]/bit[6]/bit[7] is 1, we can make it 0. This corresponds to bits [5:1] in our updated shift which doesn't contain last 2 bits. + //Lvl1 <= (Shift[1]|Shift[2]|Shift[3]|Shift[4]|Shift[5]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width + Lvl1 <= (|Shift[`EXPONENT-3:1]) ? 11'd0 : {1'b1, MminP}; // MANTISSA + 1 width + end + else begin + //for half precision fp16, 10 bits can be shifted. Hence, only shifts till 10 (01010)can be made. + Lvl1 <= Shift[2] ? 11'd0 : {1'b1, MminP}; + end + end + + assign Stage1 = {Lvl1, Lvl1}; //2*MANTISSA + 2 width + + always @(*) begin // Rotate {0 | 4 } bits + if(bf16 == 1'b1) begin + case (Shift[0]) + // Rotate by 0 + 1'b0: Lvl2 <= Stage1[`MANTISSA:0]; + // Rotate by 4 + 1'b1: Lvl2 <= Stage1[`MANTISSA+4:4]; + endcase + end + else begin + case (Shift[1:0]) // Rotate {0 | 4 | 8} bits + // Rotate by 0 + 2'b00: Lvl2 <= Stage1[`MANTISSA:0]; + // Rotate by 4 + 2'b01: Lvl2 <= Stage1[`MANTISSA+4:4]; + // Rotate by 8 + 2'b10: Lvl2 <= Stage1[`MANTISSA+8:8]; + // Rotate by 12 + 2'b11: Lvl2[`MANTISSA: 0] <= 0; + //2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end + endcase + end + end + + // Assign output to next shift stage + assign Mmin = Lvl2; + +endmodule + + +// Description: Alignment shift stage 2, performs 3|2|1 shift +// + + +module FPAddSub_AlignShift2( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`MANTISSA:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [1:0] Shift ; // Shift amount. Last 2 bits + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + // Internal Signal + reg [`MANTISSA:0] Lvl3; + wire [2*`MANTISSA+1:0] Stage2; + integer j; // Loop variable + + assign Stage2 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl3 <= Stage2[`MANTISSA:0]; + // Rotate by 1 + 2'b01: Lvl3 <= Stage2[`MANTISSA+1:1]; + // Rotate by 2 + 2'b10: Lvl3 <= Stage2[`MANTISSA+2:2]; + // Rotate by 3 + 2'b11: Lvl3 <= Stage2[`MANTISSA+3:3]; + default: Lvl3 <= Stage2[`MANTISSA+3:3]; + endcase + end + + // Assign output + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + + +// +// Description: Module that executes the addition or subtraction on mantissas. +// + + +module FPAddSub_ExecutionModule( + Mmax, + Mmin, + Sa, + Sb, + MaxAB, + OpMode, + Sum, + PSgn, + Opr + ); + + // Input ports + input [`MANTISSA-1:0] Mmax ; // The larger mantissa + input [`MANTISSA:0] Mmin ; // The smaller mantissa + input Sa ; // Sign bit of larger number + input Sb ; // Sign bit of smaller number + input MaxAB ; // Indicates the larger number (0/A, 1/B) + input OpMode ; // Operation to be performed (0/Add, 1/Sub) + + // Output ports + output [`DWIDTH:0] Sum ; // The result of the operation + output PSgn ; // The sign for the result + output Opr ; // The effective (performed) operation + + wire [`EXPONENT-1:0]temp_1; + + assign Opr = (OpMode^Sa^Sb); // Resolve sign to determine operation + assign temp_1 = 0; + // Perform effective operation +//SAMIDH_UNSURE 5--> 8 + + assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, temp_1} - {Mmin, temp_1}) : ({1'b1, Mmax, temp_1} + {Mmin, temp_1}) ; + + // Assign result sign + assign PSgn = (MaxAB ? Sb : Sa) ; + +endmodule + + +// +// Description: Determine the normalization shift amount and perform 16-shift +// + + +module FPAddSub_NormalizeModule( + Sum, + Mmin, + Shift + ); + + // Input ports + input [`DWIDTH:0] Sum ; // Mantissa sum including hidden 1 and GRS + + // Output ports + output [`DWIDTH:0] Mmin ; // Mantissa after 16|0 shift + output [4:0] Shift ; // Shift amount + //Changes in this doesn't matter since even Bfloat16 can't go beyond 7 shift to the mantissa (only 3 bits valid here) + // Determine normalization shift amount by finding leading nought + assign Shift = ( + Sum[16] ? 5'b00000 : + Sum[15] ? 5'b00001 : + Sum[14] ? 5'b00010 : + Sum[13] ? 5'b00011 : + Sum[12] ? 5'b00100 : + Sum[11] ? 5'b00101 : + Sum[10] ? 5'b00110 : + Sum[9] ? 5'b00111 : + Sum[8] ? 5'b01000 : + Sum[7] ? 5'b01001 : + Sum[6] ? 5'b01010 : + Sum[5] ? 5'b01011 : + Sum[4] ? 5'b01100 : 5'b01101 + // Sum[19] ? 5'b01101 : + // Sum[18] ? 5'b01110 : + // Sum[17] ? 5'b01111 : + // Sum[16] ? 5'b10000 : + // Sum[15] ? 5'b10001 : + // Sum[14] ? 5'b10010 : + // Sum[13] ? 5'b10011 : + // Sum[12] ? 5'b10100 : + // Sum[11] ? 5'b10101 : + // Sum[10] ? 5'b10110 : + // Sum[9] ? 5'b10111 : + // Sum[8] ? 5'b11000 : + // Sum[7] ? 5'b11001 : 5'b11010 + ); + + reg [`DWIDTH:0] Lvl1; + + always @(*) begin + // Rotate by 16? + Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum; + end + + // Assign outputs + assign Mmin = Lvl1; // Take out smaller mantissa + +endmodule + + +// Description: Normalization shift stage 1, performs 12|8|4|3|2|1|0 shift +// +//Hardcoding loop start and end values of i. To avoid ODIN limitations. i=`DWIDTH*2+1 wasn't working. + + +module FPAddSub_NormalizeShift1( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`DWIDTH:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [3:0] Shift ; // Shift amount + + // Output ports + output [`DWIDTH:0] Mmin ; // The smaller mantissa + + reg [`DWIDTH:0] Lvl2; + wire [2*`DWIDTH+1:0] Stage1; + reg [`DWIDTH:0] Lvl3; + wire [2*`DWIDTH+1:0] Stage2; + integer i; // Loop variable + + assign Stage1 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 4 | 8 | 12} bits + case (Shift[3:2]) + // Rotate by 0 + 2'b00: Lvl2 <= Stage1[`DWIDTH:0]; + // Rotate by 4 + 2'b01: Lvl2[16:0] <= Stage1[28:13]; + // Rotate by 8 + 2'b10: Lvl2[16:0] <= Stage1[24:9]; + // Rotate by 12 + 2'b11: Lvl2[16:0] <= Stage1[20:5]; + default: Lvl2[16:0] <= Stage1[20:5]; + endcase + end + + assign Stage2 = {Lvl2, Lvl2}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl3 <= Stage2[`DWIDTH:0]; + // Rotate by 1 + 2'b01: Lvl3[16:0] <= Stage2[31:16]; + // Rotate by 2 + 2'b10: Lvl3[16:0] <= Stage2[30:15]; + // Rotate by 3 + 2'b11: Lvl3[16:0] <= Stage2[29:14]; + default: Lvl3[16:0] <= Stage2[29:14]; + endcase + end + + // Assign outputs + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + + +// Description: Normalization shift stage 2, calculates post-normalization +// mantissa and exponent, as well as the bits used in rounding +// + + +module FPAddSub_NormalizeShift2( + PSSum, + CExp, + Shift, + NormM, + NormE, + ZeroSum, + NegE, + R, + S, + FG + ); + + // Input ports + input [`DWIDTH:0] PSSum ; // The Pre-Shift-Sum + input [`EXPONENT-1:0] CExp ; + input [4:0] Shift ; // Amount to be shifted + + // Output ports + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output [`EXPONENT:0] NormE ; // Adjusted exponent + output ZeroSum ; // Zero flag + output NegE ; // Flag indicating negative exponent + output R ; // Round bit + output S ; // Final sticky bit + output FG ; + + // Internal signals + wire MSBShift ; // Flag indicating that a second shift is needed + wire [`EXPONENT:0] ExpOF ; // MSB set in sum indicates overflow + wire [`EXPONENT:0] ExpOK ; // MSB not set, no adjustment + + // Calculate normalized exponent and mantissa, check for all-zero sum + assign MSBShift = PSSum[`DWIDTH] ; // Check MSB in unnormalized sum + assign ZeroSum = ~|PSSum ; // Check for all zero sum + assign ExpOK = CExp - Shift ; // Adjust exponent for new normalized mantissa + assign NegE = ExpOK[`EXPONENT] ; // Check for exponent overflow + assign ExpOF = CExp - Shift + 1'b1 ; // If MSB set, add one to exponent(x2) + assign NormE = MSBShift ? ExpOF : ExpOK ; // Check for exponent overflow + assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1] ; // The new, normalized mantissa + + // Also need to compute sticky and round bits for the rounding stage + assign FG = PSSum[`EXPONENT] ; + assign R = PSSum[`EXPONENT-1] ; + assign S = |PSSum[`EXPONENT-2:0] ; + +endmodule + + +// Description: Performs 'Round to nearest, tie to even'-rounding on the +// normalized mantissa according to the G, R, S bits. Calculates +// final result and checks for exponent overflow. +// + + +module FPAddSub_RoundModule( + ZeroSum, + NormE, + NormM, + R, + S, + G, + Sa, + Sb, + Ctrl, + MaxAB, + Z, + EOF + ); + + // Input ports + input ZeroSum ; // Sum is zero + input [`EXPONENT:0] NormE ; // Normalized exponent + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input R ; // Round bit + input S ; // Sticky bit + input G ; + input Sa ; // A's sign bit + input Sb ; // B's sign bit + input Ctrl ; // Control bit (operation) + input MaxAB ; + + // Output ports + output [`DWIDTH-1:0] Z ; // Final result + output EOF ; + + // Internal signals + wire [`MANTISSA:0] RoundUpM ; // Rounded up sum with room for overflow + wire [`MANTISSA-1:0] RoundM ; // The final rounded sum + wire [`EXPONENT:0] RoundE ; // Rounded exponent (note extra bit due to poential overflow ) + wire RoundUp ; // Flag indicating that the sum should be rounded up + wire FSgn; + wire ExpAdd ; // May have to add 1 to compensate for overflow + wire RoundOF ; // Rounding overflow + + wire [`EXPONENT:0]temp_2; + assign temp_2 = 0; + // The cases where we need to round upwards (= adding one) in Round to nearest, tie to even + assign RoundUp = (G & ((R | S) | NormM[0])) ; + + // Note that in the other cases (rounding down), the sum is already 'rounded' + assign RoundUpM = (NormM + 1'b1) ; // The sum, rounded up by 1 + assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM) ; // Compute final mantissa + assign RoundOF = RoundUp & RoundUpM[`MANTISSA] ; // Check for overflow when rounding up + + // Calculate post-rounding exponent + assign ExpAdd = (RoundOF ? 1'b1 : 1'b0) ; // Add 1 to exponent to compensate for overflow + assign RoundE = ZeroSum ? temp_2 : (NormE + ExpAdd) ; // Final exponent + + // If zero, need to determine sign according to rounding + assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ; + + // Assign final result + assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]} ; + + // Indicate exponent overflow + assign EOF = RoundE[`EXPONENT]; + +endmodule + + +// +// Description: Check the final result for exception conditions and set +// flags accordingly. +// + + +module FPAddSub_ExceptionModule( + Z, + NegE, + R, + S, + InputExc, + EOF, + P, + Flags + ); + + // Input ports + input [`DWIDTH-1:0] Z ; // Final product + input NegE ; // Negative exponent? + input R ; // Round bit + input S ; // Sticky bit + input [4:0] InputExc ; // Exceptions in inputs A and B + input EOF ; + + // Output ports + output [`DWIDTH-1:0] P ; // Final result + output [4:0] Flags ; // Exception flags + + // Internal signals + wire Overflow ; // Overflow flag + wire Underflow ; // Underflow flag + wire DivideByZero ; // Divide-by-Zero flag (always 0 in Add/Sub) + wire Invalid ; // Invalid inputs or result + wire Inexact ; // Result is inexact because of rounding + + // Exception flags + + // Result is too big to be represented + assign Overflow = EOF | InputExc[1] | InputExc[0] ; + + // Result is too small to be represented + assign Underflow = NegE & (R | S); + + // Infinite result computed exactly from finite operands + assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0]; + + // Invalid inputs or operation + assign Invalid = |(InputExc[4:2]) ; + + // Inexact answer due to rounding, overflow or underflow + assign Inexact = (R | S) | Overflow | Underflow; + + // Put pieces together to form final result + assign P = Z ; + + // Collect exception flags + assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact} ; + +endmodule +module FPMult_16( + clk, + rst, + a, + b, + result, + flags + ); + + // Input Ports + input clk ; // Clock + input rst ; // Reset signal + input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number + + // Output ports + output [`DWIDTH-1:0] result ; // Product, result of the operation, 32-bit FP number + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Internal signals + wire [`DWIDTH-1:0] Z_int ; // Product, result of the operation, 32-bit FP number + wire [4:0] Flags_int ; // Flags indicating exceptions according to IEEE754 + + wire Sa ; // A's sign + wire Sb ; // B's sign + wire Sp ; // Product sign + wire [`EXPONENT-1:0] Ea ; // A's exponent + wire [`EXPONENT-1:0] Eb ; // B's exponent + wire [2*`MANTISSA+1:0] Mp ; // Product mantissa + wire [4:0] InputExc ; // Exceptions in inputs + wire [`MANTISSA-1:0] NormM ; // Normalized mantissa + wire [`EXPONENT:0] NormE ; // Normalized exponent + wire [`MANTISSA:0] RoundM ; // Normalized mantissa + wire [`EXPONENT:0] RoundE ; // Normalized exponent + wire [`MANTISSA:0] RoundMP ; // Normalized mantissa + wire [`EXPONENT:0] RoundEP ; // Normalized exponent + wire GRS ; + + //reg [63:0] pipe_0; // Pipeline register Input->Prep + reg [2*`DWIDTH-1:0] pipe_0; // Pipeline register Input->Prep + + //reg [92:0] pipe_1; // Pipeline register Prep->Execute + //reg [3*`MANTISSA+2*`EXPONENT+7:0] pipe_1; // Pipeline register Prep->Execute + reg [3*`MANTISSA+2*`EXPONENT+18:0] pipe_1; + + //reg [38:0] pipe_2; // Pipeline register Execute->Normalize + reg [`MANTISSA+`EXPONENT+7:0] pipe_2; // Pipeline register Execute->Normalize + + //reg [72:0] pipe_3; // Pipeline register Normalize->Round + reg [2*`MANTISSA+2*`EXPONENT+10:0] pipe_3; // Pipeline register Normalize->Round + + //reg [36:0] pipe_4; // Pipeline register Round->Output + reg [`DWIDTH+4:0] pipe_4; // Pipeline register Round->Output + + assign result = pipe_4[`DWIDTH+4:5] ; + assign flags = pipe_4[4:0] ; + + // Prepare the operands for alignment and check for exceptions + FPMult_PrepModule PrepModule(clk, rst, pipe_0[2*`DWIDTH-1:`DWIDTH], pipe_0[`DWIDTH-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]) ; + + // Perform (unsigned) mantissa multiplication + FPMult_ExecuteModule ExecuteModule(pipe_1[3*`MANTISSA+`EXPONENT*2+7:2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7:2*`MANTISSA+7], pipe_1[2*`MANTISSA+6:5], pipe_1[2*`MANTISSA+2*`EXPONENT+6:2*`MANTISSA+`EXPONENT+7], pipe_1[2*`MANTISSA+`EXPONENT+6:2*`MANTISSA+7], pipe_1[2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7], Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0], GRS) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + FPMult_NormalizeModule NormalizeModule(pipe_2[`MANTISSA-1:0], pipe_2[`MANTISSA+`EXPONENT:`MANTISSA], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + //FPMult_RoundModule RoundModule(pipe_3[47:24], pipe_3[23:0], pipe_3[65:57], pipe_3[56:48], pipe_3[66], pipe_3[67], pipe_3[72:68], Z_int[31:0], Flags_int[4:0]) ; + FPMult_RoundModule RoundModule(pipe_3[2*`MANTISSA+1:`MANTISSA+1], pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+2*`EXPONENT+3:2*`MANTISSA+`EXPONENT+3], pipe_3[2*`MANTISSA+`EXPONENT+2:2*`MANTISSA+2], pipe_3[2*`MANTISSA+2*`EXPONENT+4], pipe_3[2*`MANTISSA+2*`EXPONENT+5], pipe_3[2*`MANTISSA+2*`EXPONENT+10:2*`MANTISSA+2*`EXPONENT+6], Z_int[`DWIDTH-1:0], Flags_int[4:0]) ; + +//adding always@ (*) instead of posedge clock to make design combinational + always @ (*) begin + if(rst) begin + pipe_0 = 0; + pipe_1 = 0; + pipe_2 = 0; + pipe_3 = 0; + pipe_4 = 0; + end + else begin + /* PIPE 0 + [2*`DWIDTH-1:`DWIDTH] A + [`DWIDTH-1:0] B + */ + pipe_0 = {a, b} ; + + + /* PIPE 1 + [2*`EXPONENT+3*`MANTISSA + 18: 2*`EXPONENT+2*`MANTISSA + 18] //pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH] , mantissa of A + [2*`EXPONENT+2*`MANTISSA + 17 :2*`EXPONENT+2*`MANTISSA + 9] // pipe_0[8:0] + [2*`EXPONENT+2*`MANTISSA + 8] Sa + [2*`EXPONENT+2*`MANTISSA + 7] Sb + [2*`EXPONENT+2*`MANTISSA + 6:`EXPONENT+2*`MANTISSA+7] Ea + [`EXPONENT +2*`MANTISSA+6:2*`MANTISSA+7] Eb + [2*`MANTISSA+1+5:5] Mp + [4:0] InputExc + */ + //pipe_1 <= {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[`MANTISSA_MUL_SPLIT_LSB-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA-1:0], InputExc[4:0]} ; + pipe_1 = {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[8:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]} ; + + /* PIPE 2 + [`EXPONENT + `MANTISSA + 7:`EXPONENT + `MANTISSA + 3] InputExc + [`EXPONENT + `MANTISSA + 2] GRS + [`EXPONENT + `MANTISSA + 1] Sp + [`EXPONENT + `MANTISSA:`MANTISSA] NormE + [`MANTISSA-1:0] NormM + */ + pipe_2 = {pipe_1[4:0], GRS, Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0]} ; + /* PIPE 3 + [2*`EXPONENT+2*`MANTISSA+10:2*`EXPONENT+2*`MANTISSA+6] InputExc + [2*`EXPONENT+2*`MANTISSA+5] GRS + [2*`EXPONENT+2*`MANTISSA+4] Sp + [2*`EXPONENT+2*`MANTISSA+3:`EXPONENT+2*`MANTISSA+3] RoundE + [`EXPONENT+2*`MANTISSA+2:2*`MANTISSA+2] RoundEP + [2*`MANTISSA+1:`MANTISSA+1] RoundM + [`MANTISSA:0] RoundMP + */ + pipe_3 = {pipe_2[`EXPONENT+`MANTISSA+7:`EXPONENT+`MANTISSA+1], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]} ; + /* PIPE 4 + [`DWIDTH+4:5] Z + [4:0] Flags + */ + pipe_4 = {Z_int[`DWIDTH-1:0], Flags_int[4:0]} ; + end + end + +endmodule + + + +module FPMult_PrepModule ( + clk, + rst, + a, + b, + Sa, + Sb, + Ea, + Eb, + Mp, + InputExc + ); + + // Input ports + input clk ; + input rst ; + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [`EXPONENT-1:0] Ea ; // A's exponent + output [`EXPONENT-1:0] Eb ; // B's exponent + output [2*`MANTISSA+1:0] Mp ; // Mantissa product + output [4:0] InputExc ; // Input numbers are exceptions + + // Internal signals // If signal is high... + wire ANaN ; // A is a signalling NaN + wire BNaN ; // B is a signalling NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`MANTISSA-1:0] Ma; + wire [`MANTISSA-1:0] Mb; + + assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + + // Check for any exceptions and put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + //assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ; + + // Take input numbers apart + assign Sa = a[`DWIDTH-1] ; // A's sign + assign Sb = b[`DWIDTH-1] ; // B's sign + assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception + assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception +// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB]; + // assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB]; + + + + //assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ; + assign Mp = ({1'b1,a[`MANTISSA-1:0]}*{1'b1, b[`MANTISSA-1:0]}) ; + + + //We multiply part of the mantissa here + //Full mantissa of A + //Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B + // wire [`ACTUAL_MANTISSA-1:0] inp_A; + // wire [`ACTUAL_MANTISSA-1:0] inp_B; + // assign inp_A = {1'b1, Ma}; + // assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp)); +endmodule + + +module FPMult_ExecuteModule( + a, + b, + MpC, + Ea, + Eb, + Sa, + Sb, + Sp, + NormE, + NormM, + GRS + ); + + // Input ports + input [`MANTISSA-1:0] a ; + input [2*`EXPONENT:0] b ; + input [2*`MANTISSA+1:0] MpC ; + input [`EXPONENT-1:0] Ea ; // A's exponent + input [`EXPONENT-1:0] Eb ; // B's exponent + input Sa ; // A's sign + input Sb ; // B's sign + + // Output ports + output Sp ; // Product sign + output [`EXPONENT:0] NormE ; // Normalized exponent + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output GRS ; + + wire [2*`MANTISSA+1:0] Mp ; + + assign Sp = (Sa ^ Sb) ; // Equal signs give a positive product + + // wire [`ACTUAL_MANTISSA-1:0] inp_a; + // wire [`ACTUAL_MANTISSA-1:0] inp_b; + // assign inp_a = {1'b1, a}; + // assign inp_b = {{(`MANTISSA-`MANTISSA_MUL_SPLIT_LSB){1'b0}}, 1'b0, b}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_a), .B(inp_b), .TC(1'b0), .PRODUCT(Mp_temp)); + // DW01_add #(2*`ACTUAL_MANTISSA) u_add(.A(Mp_temp), .B(MpC<<`MANTISSA_MUL_SPLIT_LSB), .CI(1'b0), .SUM(Mp), .CO()); + + //assign Mp = (MpC<<(2*`EXPONENT+1)) + ({4'b0001, a[`MANTISSA-1:0]}*{1'b0, b[2*`EXPONENT:0]}) ; + assign Mp = MpC; + + + assign NormM = (Mp[2*`MANTISSA+1] ? Mp[2*`MANTISSA:`MANTISSA+1] : Mp[2*`MANTISSA-1:`MANTISSA]); // Check for overflow + assign NormE = (Ea + Eb + Mp[2*`MANTISSA+1]); // If so, increment exponent + + assign GRS = ((Mp[`MANTISSA]&(Mp[`MANTISSA+1]))|(|Mp[`MANTISSA-1:0])) ; + +endmodule + +module FPMult_NormalizeModule( + NormM, + NormE, + RoundE, + RoundEP, + RoundM, + RoundMP + ); + + // Input Ports + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input [`EXPONENT:0] NormE ; // Normalized exponent + + // Output Ports + output [`EXPONENT:0] RoundE ; + output [`EXPONENT:0] RoundEP ; + output [`MANTISSA:0] RoundM ; + output [`MANTISSA:0] RoundMP ; + +// EXPONENT = 5 +// EXPONENT -1 = 4 +// NEED to subtract 2^4 -1 = 15 + +wire [`EXPONENT-1 : 0] bias; + +assign bias = ((1'b1 << (`EXPONENT -1'b1)) -1'b1); + + assign RoundE = NormE - bias ; + assign RoundEP = NormE - bias -1'b1 ; + assign RoundM = NormM ; + assign RoundMP = NormM ; + +endmodule + +module FPMult_RoundModule( + RoundM, + RoundMP, + RoundE, + RoundEP, + Sp, + GRS, + InputExc, + Z, + Flags + ); + + // Input Ports + input [`MANTISSA:0] RoundM ; // Normalized mantissa + input [`MANTISSA:0] RoundMP ; // Normalized exponent + input [`EXPONENT:0] RoundE ; // Normalized mantissa + 1 + input [`EXPONENT:0] RoundEP ; // Normalized exponent + 1 + input Sp ; // Product sign + input GRS ; + input [4:0] InputExc ; + + // Output Ports + output [`DWIDTH-1:0] Z ; // Final product + output [4:0] Flags ; + + // Internal Signals + wire [`EXPONENT:0] FinalE ; // Rounded exponent + wire [`MANTISSA:0] FinalM; + wire [`MANTISSA:0] PreShiftM; + + assign PreShiftM = GRS ? RoundMP : RoundM ; // Round up if R and (G or S) + + // Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow) + assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]) ; + + assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done + + assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]} ; // Putting the pieces together + assign Flags = InputExc[4:0]; + +endmodule + + +module array_mux_2to1 #(parameter size = 10) (clk,reset,start,out,in0,in1,sel,out_data_available); + + input [size-1:0] in0, in1; + input sel,clk; + input reset,start; + output reg [size-1:0] out; + output reg out_data_available; + + always@(posedge clk) begin + if((reset==1'b1) || (start==1'b0)) begin + out <= 7'd0; + out_data_available <= 0; + end + else begin + out <= (sel) ? in1 : in0; + out_data_available <= 1; + end + end + +endmodule + +module barrel_shifter_right ( + input clk, + input reset, + input start, + input [4:0] shift_amt, + input [5:0] significand, + output [5:0] shifted_sig, + output out_data_available +); + + //3-level distributed barrel shifter using 10 2:1 MUX array + + //level 0 + wire [6:0] out0; + wire out_data_available_arr_0; + + array_mux_2to1 #(.size(7)) M0 ( + .clk(clk), + .reset(reset), + .start(start), + .out(out0), + .in0({significand[5:0],1'b0}), + .in1({1'b0,significand[5:0]}), + .sel(shift_amt[0]), + .out_data_available(out_data_available_arr_0) + ); + + //level 1 + wire [8:0] out1; + wire out_data_available_arr_1; + + array_mux_2to1 #(.size(9)) M1 ( + .clk(clk), + .reset(reset), + .start(out_data_available_arr_0), + .out(out1), + .in0({out0[6:0],2'b0}), + .in1({2'b0,out0[6:0]}), + .sel(shift_amt[1]), + .out_data_available(out_data_available_arr_1) + ); + + //level 2 + wire [12:0] out2; + + array_mux_2to1 #(.size(13)) M2 ( + .clk(clk), + .reset(reset), + .start(out_data_available_arr_1), + .out(out2), + .in0({out1[8:0],4'b0}), + .in1({4'b0,out1[8:0]}), + .sel(shift_amt[2]), + .out_data_available(out_data_available) + ); + + //shifted significand + assign shifted_sig = (reset==1'b1) ? 6'd0 : out2[12:7]; + +endmodule + +module barrel_shifter_left ( + input clk, + input reset, + input start, + input [4:0] shift_amt, + input [5:0] significand, + output [5:0] shifted_sig, + output out_data_available +); + + //3-level distributed barrel shifter using 10 2:1 MUX array + + //level 0 + wire [6:0] out0; + wire out_data_available_arr_0; + + array_mux_2to1 #(.size(7)) M0 ( + .clk(clk), + .reset(reset), + .start(start), + .out(out0), + .in0({1'b0,significand[5:0]}), + .in1({significand[5:0],1'b0}), + .sel(shift_amt[0]), + .out_data_available(out_data_available_arr_0) + ); + + //level 1 + wire [8:0] out1; + wire out_data_available_arr_1; + + array_mux_2to1 #(.size(9)) M1 ( + .clk(clk), + .reset(reset), + .start(out_data_available_arr_0), + .out(out1), + .in0({2'b0,out0[6:0]}), + .in1({out0[6:0],2'b0}), + .sel(shift_amt[1]), + .out_data_available(out_data_available_arr_1) + ); + + //level 2 + wire [12:0] out2; + + array_mux_2to1 #(.size(13)) M2 ( + .clk(clk), + .reset(reset), + .start(out_data_available_arr_1), + .out(out2), + .in0({4'b0,out1[8:0]}), + .in1({out1[8:0],4'b0}), + .sel(shift_amt[2]), + .out_data_available(out_data_available) + ); + + //shifted significand + assign shifted_sig = (reset==1'b1) ? 6'd0 : out2[5:0]; + +endmodule + +module leading_zero_detector_6bit( + input clk, + input[5:0] a, + input reset, + input start, + output reg [2:0] position, + output reg is_valid, + output reg out_data_available +); + + wire[1:0] posi_upper, posi_lower; + wire valid_upper, valid_lower; + + reg[3:0] num_cycles; + + always@(posedge clk) begin + if((reset==1'b1) || (start==1'b0)) begin + num_cycles <= 0; + out_data_available <= 0; + end + else begin + if(num_cycles==`NUM_LZD_CYCLES) begin + out_data_available <= 1; + end + else begin + num_cycles <= num_cycles + 1'b1; + end + end + end + + leading_zero_detector_4bit lzd4_upper( + .clk(clk), + .reset(reset), + .start(start), + .a(a[5:2]), + .position(posi_upper), + .is_valid(valid_upper) + ); + + leading_zero_detector_4bit lzd4_lower( + .clk(clk), + .reset(reset), + .start(start), + .a({a[1:0],2'b00}), + .position(posi_lower), + .is_valid(valid_lower) + ); + + always@(posedge clk) begin + if((reset==1'b1) || (start==1'b0)) begin + is_valid <= 0; + position <= 3'd0; + end + else begin + is_valid <= valid_upper | valid_lower; + + position[2] <= ~valid_upper; + position[1] <= valid_upper ? posi_upper[1] : posi_lower[1]; + position[0] <= valid_upper ? posi_upper[0] : posi_lower[0]; + end + end + +endmodule + +module leading_zero_detector_4bit( + input clk, + input[3:0] a, + input reset, + input start, + output reg [1:0] position, + output reg is_valid +); + + wire posi_upper, posi_lower; + wire valid_upper, valid_lower; + + leading_zero_detector_2bit lzd2_upper( + .clk(clk), + .reset(reset), + .start(start), + .a(a[3:2]), + .position(posi_upper), + .is_valid(valid_upper) + ); + + leading_zero_detector_2bit lzd2_lower( + .clk(clk), + .reset(reset), + .start(start), + .a(a[1:0]), + .position(posi_lower), + .is_valid(valid_lower) + ); + + always@(posedge clk) begin + if((reset==1) || (start==0)) begin + is_valid <= 0; + end + else begin + is_valid <= valid_upper | valid_lower; + + position[1] <= ~valid_upper; + position[0] <= valid_upper ? posi_upper : posi_lower; + end + end + +endmodule + +module leading_zero_detector_2bit( + input clk, + input[1:0] a, + input reset, + input start, + output reg position, + output reg is_valid +); + + always@(posedge clk) begin + if((reset==1) || (start==0)) begin + is_valid <= 0; + end + else begin + is_valid <= a[1] | a[0]; + position <= ~a[1]; + end + end +endmodule + diff --git a/designs/koios/bwave_like.float.large/design.yaml b/designs/koios/bwave_like.float.large/design.yaml new file mode 100644 index 000000000..67c7d1848 --- /dev/null +++ b/designs/koios/bwave_like.float.large/design.yaml @@ -0,0 +1 @@ +top: bwave_large_random diff --git a/designs/koios/bwave_like.float.small/bwave_like.float.small.v b/designs/koios/bwave_like.float.small/bwave_like.float.small.v new file mode 100644 index 000000000..dbf830b51 --- /dev/null +++ b/designs/koios/bwave_like.float.small/bwave_like.float.small.v @@ -0,0 +1,12340 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Tanmay Anand +////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////// +// A Microsoft Brainwave Like Design. Uses block floating point. +////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM includes.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + + +`define NUM_TILES 16 +`define NUM_LDPES 4 +`define DSPS_PER_LDPE 2 + +`define IN_PRECISION 16 +`define OUT_PRECISION 16 + +`define FLOAT_EXP 8 +`define FLOAT_MANTISA 7 +`define FLOAT_DWIDTH (`FLOAT_EXP+`FLOAT_MANTISA + 1) + +`define BFLOAT_EXP 5 +`define BFLOAT_MANTISA 5 +`define BFLOAT_DWIDTH (`BFLOAT_EXP + `BFLOAT_MANTISA + 1) +`define BFLOAT_MANTISA_WITH_LO (`BFLOAT_MANTISA+1) + + +`define DSPS_PER_SUB_LDPE 2 +`define SUB_LDPES_PER_LDPE (`DSPS_PER_LDPE/`DSPS_PER_SUB_LDPE) + +`define MULTS_PER_DSP 2 +`define DSP_X_AVA_INPUT_WIDTH 18 +`define LDPE_X_AVA_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) +`define DSP_Y_AVA_INPUT_WIDTH 19 +`define LDPE_Y_AVA_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) + +`define DSP_AVA_OUTPUT_WIDTH 37 +`define LDPE_AVA_OUTPUT_WIDTH `DSP_AVA_OUTPUT_WIDTH + +`define DSP_USED_INPUT_WIDTH (`BFLOAT_MANTISA+1) + +`define LDPE_USED_INPUT_WIDTH (`FLOAT_DWIDTH * `DSPS_PER_LDPE) +`define SUB_LDPE_USED_INPUT_WIDTH (`BFLOAT_DWIDTH * `DSPS_PER_SUB_LDPE) +`define DSP_X_ZERO_PAD_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) +`define DSP_Y_ZERO_PAD_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) + +`define DSP_USED_OUTPUT_WIDTH 27 +`define LDPE_USED_OUTPUT_WIDTH `DSP_USED_OUTPUT_WIDTH +`define DSP_ZERO_PAD_OUTPUT_WIDTH (`DSP_AVA_OUTPUT_WIDTH - `DSP_USED_OUTPUT_WIDTH) + +`define LDPES_PER_MRF 1 +`define DSPS_PER_MRF (`DSPS_PER_LDPE * `LDPES_PER_MRF) +`define MAT_BRAM_AWIDTH 10 +`define MAT_BRAM_DWIDTH 16 +`define MAT_BRAMS_PER_MRF_SUBSET 4 +`define SUBSETS_PER_MRF 1 +`define BRAMS_PER_MRF (`MAT_BRAMS_PER_MRF_SUBSET * `SUBSETS_PER_MRF) +`define MRF_AWIDTH (`MAT_BRAM_AWIDTH) +`define MRF_DWIDTH (`MAT_BRAM_DWIDTH * `MAT_BRAMS_PER_MRF_SUBSET) + +`define LDPES_PER_VRF 1 +`define DSPS_PER_VRF (`DSPS_PER_LDPE * `LDPES_PER_VRF) +`define VEC_BRAM_AWIDTH 10 +`define VEC_BRAM_DWIDTH 16 +`define BRAMS_PER_VRF 4 +`define VRF_AWIDTH `VEC_BRAM_AWIDTH +`define VRF_DWIDTH (`VEC_BRAM_DWIDTH * `BRAMS_PER_VRF) + +`define LDPES_PER_ORF 1 +`define OUTPUTS_PER_LDPE 1 +`define OUT_BRAM_AWIDTH 10 +`define OUT_BRAM_DWIDTH 16 +`define ORF_AWIDTH `OUT_BRAM_AWIDTH +`define OUT_DWIDTH 16 +`define ORF_DWIDTH 64 //64 + +`define MAX_VRF_DWIDTH 64 +`define DRAM_DWIDTH `VRF_DWIDTH //This is the max of mrf, vrf and orf dwidth +`define DRAM_AWIDTH `MRF_AWIDTH + +`define OPCODE_WIDTH 4 +`define TARGET_OP_WIDTH 7 + +`define INSTR_WIDTH (`OPCODE_WIDTH+`TARGET_OP_WIDTH+`DRAM_AWIDTH+`TARGET_OP_WIDTH+`VRF_AWIDTH + `VRF_AWIDTH) + +`define ACTIVATION 2'b00 +`define ELT_WISE_MULTIPLY 2'b10 +`define ELT_WISE_ADD 2'b01 +`define BYPASS 2'b11 + +`define RELU 2'b00 +`define TANH 2'b01 +`define SIGM 2'b10 +//OPCODES + +`define V_RD 0 +`define V_WR 1 +`define M_RD 2 +`define M_WR 3 //NEWLY ADDED +`define MV_MUL 4 +`define VV_ADD 5 +`define VV_SUB 6 //QUESTIONED +`define VV_PASS 7 +`define VV_MUL 8 +`define V_RELU 9 +`define V_SIGM 10 +`define V_TANH 11 +`define END_CHAIN 12 +//MEM_IDS + +`define VRF_0 0 +`define VRF_1 1 +`define VRF_2 2 +`define VRF_3 3 +`define VRF_4 4 +`define VRF_5 5 +`define VRF_6 6 +`define VRF_7 7 +`define VRF_8 8 +`define VRF_9 9 +`define VRF_10 10 +`define VRF_11 11 +`define VRF_12 12 +`define VRF_13 13 +`define VRF_14 14 +`define VRF_15 15 + +`define VRF_16 16 +`define VRF_17 17 +`define VRF_18 18 +`define VRF_19 19 +`define VRF_MUXED 20 +`define DRAM_MEM_ID 21 +`define MFU_0_DSTN_ID 22 +`define MFU_1_DSTN_ID 23 + +`define MRF_0 0 +`define MRF_1 1 +`define MRF_2 2 +`define MRF_3 3 +`define MRF_4 4 +`define MRF_5 5 +`define MRF_6 6 +`define MRF_7 7 +`define MRF_8 8 +`define MRF_9 9 +`define MRF_10 10 +`define MRF_11 11 +`define MRF_12 12 +`define MRF_13 13 +`define MRF_14 14 +`define MRF_15 15 +`define MRF_16 16 +`define MRF_17 17 +`define MRF_18 18 +`define MRF_19 19 +`define MRF_20 20 +`define MRF_21 21 +`define MRF_22 22 +`define MRF_23 23 +`define MRF_24 24 +`define MRF_25 25 +`define MRF_26 26 +`define MRF_27 27 +`define MRF_28 28 +`define MRF_29 29 +`define MRF_30 30 +`define MRF_31 31 +`define MRF_32 32 +`define MRF_33 33 +`define MRF_34 34 +`define MRF_35 35 +`define MRF_36 36 +`define MRF_37 37 +`define MRF_38 38 +`define MRF_39 39 +`define MRF_40 40 +`define MRF_41 41 +`define MRF_42 42 +`define MRF_43 43 +`define MRF_44 44 +`define MRF_45 45 +`define MRF_46 46 +`define MRF_47 47 +`define MRF_48 48 +`define MRF_49 49 +`define MRF_50 50 +`define MRF_51 51 +`define MRF_52 52 +`define MRF_53 53 +`define MRF_54 54 +`define MRF_55 55 +`define MRF_56 56 +`define MRF_57 57 +`define MRF_58 58 +`define MRF_59 59 +`define MRF_60 60 +`define MRF_61 61 +`define MRF_62 62 +`define MRF_63 63 + +`define MFU_0 0 +`define MFU_1 1 +`define INSTR_MEM_AWIDTH 10 + +`define EXPONENT 5 +`define MANTISSA 10 + +`define SIGN 1 +`define NUM_COMPARATOR_TREE_CYCLES 4 +`define NUM_COMPARATOR_TREE_CYCLES_FOR_TILE 6 +`define NUM_LZD_CYCLES 5 + +`define DESIGN_SIZE `NUM_LDPES +`define DWIDTH `OUT_PRECISION +`define MASK_WIDTH `OUT_PRECISION + +`define ADD_LATENCY 5 +`define LOG_ADD_LATENCY 3 +`define MUL_LATENCY 5 +`define LOG_MUL_LATENCY 3 +`define ACTIVATION_LATENCY 3 +`define TANH_LATENCY (`ACTIVATION_LATENCY+1) +`define SIGMOID_LATENCY (`ACTIVATION_LATENCY+1) + +`define NUM_REDUCTION_CYCLES 4 +`define NUM_MVM_CYCLES 14 +`define NUM_NORMALISE_CYCLES 6 +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM npu.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + + +module NPU( + input reset_npu, + input[`INSTR_WIDTH-1:0] instruction, + input[`DRAM_DWIDTH-1:0] input_data_DRAM, + output [`DRAM_DWIDTH-1:0] output_data_DRAM, + output [`DRAM_AWIDTH-1:0] dram_addr, + output dram_write_enable, + output get_instr, + output[`INSTR_MEM_AWIDTH-1:0] get_instr_addr, + //WRITE DOCUMENTATION EXPLAINING HOW MANY PORTS EACH VRF,MRF, ORF HAS and WHERE IS IT CONNECTED TO + input clk +); + wire[`ORF_DWIDTH-1:0] output_final_stage; + + + wire start_mv_mul_signal; + wire start_mfu_0_signal; + wire start_mfu_1_signal; + + + //SAME SIGNAL FOR ALL THE TILES AS PARALLEL EXECUTION OF TILES IS REQUIRED + reg[`NUM_LDPES-1:0] start_tile_with_single_cyc_latency; + reg[`NUM_LDPES-1:0] reset_tile_with_single_cyc_latency; + // + + wire [`MAX_VRF_DWIDTH-1:0] vrf_in_data; + wire[`VRF_AWIDTH-1:0] vrf_addr_wr; + wire[`VRF_AWIDTH-1:0] vrf_addr_read; + wire [`MRF_DWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_in_data; + + + //MRF SIGNALS + wire[`NUM_LDPES*`NUM_TILES-1:0] mrf_we; + wire [`MRF_AWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_addr_wr; + // + + //FINAL STAGE OUTPUT SIGNALS + wire[`ORF_DWIDTH-1:0] result_mvm; + //reg[`ORF_AWIDTH-1:0] result_addr_mvu_orf; + + //wire orf_addr_increment; + + // + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_0; + wire vrf_mvu_wr_enable_0; + wire vrf_mvu_readn_enable_0; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_1; + wire vrf_mvu_wr_enable_1; + wire vrf_mvu_readn_enable_1; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_2; + wire vrf_mvu_wr_enable_2; + wire vrf_mvu_readn_enable_2; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_3; + wire vrf_mvu_wr_enable_3; + wire vrf_mvu_readn_enable_3; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_4; + wire vrf_mvu_wr_enable_4; + wire vrf_mvu_readn_enable_4; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_5; + wire vrf_mvu_wr_enable_5; + wire vrf_mvu_readn_enable_5; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_6; + wire vrf_mvu_wr_enable_6; + wire vrf_mvu_readn_enable_6; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_7; + wire vrf_mvu_wr_enable_7; + wire vrf_mvu_readn_enable_7; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_8; + wire vrf_mvu_wr_enable_8; + wire vrf_mvu_readn_enable_8; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_9; + wire vrf_mvu_wr_enable_9; + wire vrf_mvu_readn_enable_9; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_10; + wire vrf_mvu_wr_enable_10; + wire vrf_mvu_readn_enable_10; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_11; + wire vrf_mvu_wr_enable_11; + wire vrf_mvu_readn_enable_11; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_12; + wire vrf_mvu_wr_enable_12; + wire vrf_mvu_readn_enable_12; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_13; + wire vrf_mvu_wr_enable_13; + wire vrf_mvu_readn_enable_13; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_14; + wire vrf_mvu_wr_enable_14; + wire vrf_mvu_readn_enable_14; + wire[`VRF_DWIDTH-1:0] vrf_mvu_out_15; + wire vrf_mvu_wr_enable_15; + wire vrf_mvu_readn_enable_15; + + wire done_mvm; //CHANGES THE REST STATE OF INSTR DECODER + wire out_data_available_mvm; + + wire[`NUM_TILES*`NUM_LDPES-1:0] mrf_we_for_dram; + wire [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram; + wire [`NUM_TILES*`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram; + + MVU mvm_unit ( + .clk(clk), + .start(start_tile_with_single_cyc_latency), + .reset(reset_tile_with_single_cyc_latency), + + .vrf_wr_addr(vrf_addr_wr), + .vrf_read_addr(vrf_addr_read), + .vec(vrf_in_data[`VRF_DWIDTH-1:0]), + .vrf_data_out_tile_0(vrf_mvu_out_0), //WITH TAG + .vrf_wr_enable_tile_0(vrf_mvu_wr_enable_0), //WITH TAG + .vrf_readn_enable_tile_0(vrf_mvu_readn_enable_0), //WITH TAG + .vrf_data_out_tile_1(vrf_mvu_out_1), //WITH TAG + .vrf_wr_enable_tile_1(vrf_mvu_wr_enable_1), //WITH TAG + .vrf_readn_enable_tile_1(vrf_mvu_readn_enable_1), //WITH TAG + .vrf_data_out_tile_2(vrf_mvu_out_2), //WITH TAG + .vrf_wr_enable_tile_2(vrf_mvu_wr_enable_2), //WITH TAG + .vrf_readn_enable_tile_2(vrf_mvu_readn_enable_2), //WITH TAG + .vrf_data_out_tile_3(vrf_mvu_out_3), //WITH TAG + .vrf_wr_enable_tile_3(vrf_mvu_wr_enable_3), //WITH TAG + .vrf_readn_enable_tile_3(vrf_mvu_readn_enable_3), //WITH TAG + .vrf_data_out_tile_4(vrf_mvu_out_4), //WITH TAG + .vrf_wr_enable_tile_4(vrf_mvu_wr_enable_4), //WITH TAG + .vrf_readn_enable_tile_4(vrf_mvu_readn_enable_4), //WITH TAG + .vrf_data_out_tile_5(vrf_mvu_out_5), //WITH TAG + .vrf_wr_enable_tile_5(vrf_mvu_wr_enable_5), //WITH TAG + .vrf_readn_enable_tile_5(vrf_mvu_readn_enable_5), //WITH TAG + .vrf_data_out_tile_6(vrf_mvu_out_6), //WITH TAG + .vrf_wr_enable_tile_6(vrf_mvu_wr_enable_6), //WITH TAG + .vrf_readn_enable_tile_6(vrf_mvu_readn_enable_6), //WITH TAG + .vrf_data_out_tile_7(vrf_mvu_out_7), //WITH TAG + .vrf_wr_enable_tile_7(vrf_mvu_wr_enable_7), //WITH TAG + .vrf_readn_enable_tile_7(vrf_mvu_readn_enable_7), //WITH TAG + .vrf_data_out_tile_8(vrf_mvu_out_8), //WITH TAG + .vrf_wr_enable_tile_8(vrf_mvu_wr_enable_8), //WITH TAG + .vrf_readn_enable_tile_8(vrf_mvu_readn_enable_8), //WITH TAG + .vrf_data_out_tile_9(vrf_mvu_out_9), //WITH TAG + .vrf_wr_enable_tile_9(vrf_mvu_wr_enable_9), //WITH TAG + .vrf_readn_enable_tile_9(vrf_mvu_readn_enable_9), //WITH TAG + .vrf_data_out_tile_10(vrf_mvu_out_10), //WITH TAG + .vrf_wr_enable_tile_10(vrf_mvu_wr_enable_10), //WITH TAG + .vrf_readn_enable_tile_10(vrf_mvu_readn_enable_10), //WITH TAG + .vrf_data_out_tile_11(vrf_mvu_out_11), //WITH TAG + .vrf_wr_enable_tile_11(vrf_mvu_wr_enable_11), //WITH TAG + .vrf_readn_enable_tile_11(vrf_mvu_readn_enable_11), //WITH TAG + .vrf_data_out_tile_12(vrf_mvu_out_12), //WITH TAG + .vrf_wr_enable_tile_12(vrf_mvu_wr_enable_12), //WITH TAG + .vrf_readn_enable_tile_12(vrf_mvu_readn_enable_12), //WITH TAG + .vrf_data_out_tile_13(vrf_mvu_out_13), //WITH TAG + .vrf_wr_enable_tile_13(vrf_mvu_wr_enable_13), //WITH TAG + .vrf_readn_enable_tile_13(vrf_mvu_readn_enable_13), //WITH TAG + .vrf_data_out_tile_14(vrf_mvu_out_14), //WITH TAG + .vrf_wr_enable_tile_14(vrf_mvu_wr_enable_14), //WITH TAG + .vrf_readn_enable_tile_14(vrf_mvu_readn_enable_14), //WITH TAG + .vrf_data_out_tile_15(vrf_mvu_out_15), //WITH TAG + .vrf_wr_enable_tile_15(vrf_mvu_wr_enable_15), //WITH TAG + .vrf_readn_enable_tile_15(vrf_mvu_readn_enable_15), //WITH TAG + + .mrf_in(mrf_in_data), + .mrf_we(mrf_we), //WITH TAG + .mrf_addr(mrf_addr_wr), + + .mrf_we_for_dram(mrf_we_for_dram), + .mrf_addr_for_dram(mrf_addr_for_dram), + .mrf_outa_to_dram(mrf_outa_to_dram), + + .out_data_available(out_data_available_mvm), + .mvm_result(result_mvm) //WITH TAG + ); + + assign done_mvm = out_data_available_mvm; + + reg[3:0] num_cycles_mvm; + + + //******************************************************************************* + + wire in_data_available_mfu_0; + reg reset_mfu_0_with_single_cyc_latency; + wire out_data_available_mfu_0; + wire done_mfu_0; + + wire in_data_available_mfu_1; + reg reset_mfu_1_with_single_cyc_latency; + wire out_data_available_mfu_1; + wire done_mfu_1; + + wire[1:0] activation; + wire[1:0] operation; + + //MFU VRF WIRES **************************************************************** + //wire[`VRF_AWIDTH-1:0] vrf_mfu_addr_read_add_0; + + //MFU - STAGE 0 VRF SIGNALS + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_add_0; + wire vrf_mfu_readn_enable_add_0; + wire vrf_mfu_wr_enable_add_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_add_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_add_0; + + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_mul_0; + wire vrf_mfu_readn_enable_mul_0; + wire vrf_mfu_wr_enable_mul_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_mul_0; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_mul_0; + + //wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_add_1; + + //MFU - STAGE 1 VRF SIGNALS + + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_add_1; + wire vrf_mfu_readn_enable_add_1; + wire vrf_mfu_wr_enable_add_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_add_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_add_1; + + wire[`ORF_DWIDTH-1:0] vrf_mfu_out_data_mul_1; + wire vrf_mfu_readn_enable_mul_1; + wire vrf_mfu_wr_enable_mul_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_read_mul_1; + wire[`ORF_AWIDTH-1:0] vrf_mfu_addr_wr_mul_1; + + wire[`TARGET_OP_WIDTH-1:0] dstn_id; + wire[`NUM_LDPES*`OUT_DWIDTH-1:0] output_mvu_stage; + //************************************************************ + + assign output_mvu_stage = result_mvm; + + //************** INTER MFU MVU DATAPATH SIGNALS ************************************************* + reg[`ORF_DWIDTH-1:0] output_mvu_stage_buffer; + reg[`ORF_DWIDTH-1:0] output_mfu_stage_0_buffer; + + wire[`ORF_DWIDTH-1:0] primary_in_data_mfu_stage_0; + wire[`ORF_DWIDTH-1:0] primary_in_data_mfu_stage_1; + + + wire[`NUM_LDPES*`OUT_DWIDTH-1:0] output_mfu_stage_0; + wire[`NUM_LDPES*`OUT_DWIDTH-1:0] output_mfu_stage_1; + + always@(posedge clk) begin + if((dstn_id==`MFU_0_DSTN_ID) && done_mvm==1'b1) begin + output_mvu_stage_buffer <= output_mvu_stage; + end + end + + //CHECK THIS LOGIC CAREFULLY ***************************************************************** + always@(posedge clk) begin //FIRST BYPASS MUXING + //$display("%h", vrf_mvu_wr_addr_0); + if((dstn_id==`MFU_1_DSTN_ID) && (done_mfu_0 || done_mvm)) begin + output_mfu_stage_0_buffer <= (done_mfu_0) ? output_mfu_stage_0 : output_mvu_stage; + end + end + + assign output_final_stage = ((dstn_id!=`MFU_0_DSTN_ID) && (dstn_id!=`MFU_1_DSTN_ID)) ? + (done_mfu_1 ? output_mfu_stage_1 : //SECOND BYPASS MUXING + (done_mfu_0 ? output_mfu_stage_0 : + (done_mvm ? output_mvu_stage : 'd0))) : 'd0; + + //******************************************************************************************** + + + //****************************************************************************************** + wire[`ORF_DWIDTH-1:0] vrf_muxed_in_data_fake; + //************* MUXED MVU-MFU VRF ********************************************************** + + wire[`ORF_AWIDTH-1:0] vrf_muxed_wr_addr_dram; + wire[`ORF_DWIDTH-1:0] vrf_muxed_in_data; + wire vrf_muxed_wr_enable_dram; + wire vrf_muxed_readn_enable; + + wire[`ORF_AWIDTH-1:0] vrf_muxed_read_addr; + wire[`ORF_DWIDTH-1:0] vrf_muxed_out_data_dram; + wire[`ORF_DWIDTH-1:0] vrf_muxed_out_data; + + + VRF #(.VRF_DWIDTH(`ORF_DWIDTH),.VRF_AWIDTH(`ORF_AWIDTH)) vrf_muxed ( + .clk(clk), + + .addra(vrf_muxed_wr_addr_dram), + .ina(vrf_in_data[`ORF_DWIDTH-1:0]), + .wea(vrf_muxed_wr_enable_dram), + .outa(vrf_muxed_out_data_dram), + + .addrb(vrf_muxed_read_addr), + .inb(vrf_muxed_in_data_fake), + .web(vrf_muxed_readn_enable), + .outb(vrf_muxed_out_data) + ); + + wire mvu_or_vrf_mux_select; + assign primary_in_data_mfu_stage_0 = (mvu_or_vrf_mux_select) ? vrf_muxed_out_data : output_mvu_stage_buffer; + + assign primary_in_data_mfu_stage_1 = output_mfu_stage_0_buffer; + + //********************************************************************************************* + + //*********************************CONTROLLER FOR NPU***************************************** + controller controller_for_npu( + .clk(clk), + .reset_npu(reset_npu), + .instruction(instruction), + .get_instr(get_instr), + .get_instr_addr(get_instr_addr), + + .input_data_from_dram(input_data_DRAM), + .dram_addr_wr(dram_addr), + .dram_write_enable(dram_write_enable), + .output_data_to_dram(output_data_DRAM), + + .output_final_stage(output_final_stage), + + .start_mfu_0(start_mfu_0_signal), + .start_mfu_1(start_mfu_1_signal), + .start_mv_mul(start_mv_mul_signal), + .in_data_available_mfu_0(in_data_available_mfu_0), + .in_data_available_mfu_1(in_data_available_mfu_1), + + .activation(activation), + .operation(operation), + + .vrf_addr_read(vrf_addr_read), + .vrf_addr_wr(vrf_addr_wr), + + .vrf_out_data_mvu_0(vrf_mvu_out_0), //MVU TILE VRF + .vrf_readn_enable_mvu_0(vrf_mvu_readn_enable_0), + .vrf_wr_enable_mvu_0(vrf_mvu_wr_enable_0), + .vrf_out_data_mvu_1(vrf_mvu_out_1), //MVU TILE VRF + .vrf_readn_enable_mvu_1(vrf_mvu_readn_enable_1), + .vrf_wr_enable_mvu_1(vrf_mvu_wr_enable_1), + .vrf_out_data_mvu_2(vrf_mvu_out_2), //MVU TILE VRF + .vrf_readn_enable_mvu_2(vrf_mvu_readn_enable_2), + .vrf_wr_enable_mvu_2(vrf_mvu_wr_enable_2), + .vrf_out_data_mvu_3(vrf_mvu_out_3), //MVU TILE VRF + .vrf_readn_enable_mvu_3(vrf_mvu_readn_enable_3), + .vrf_wr_enable_mvu_3(vrf_mvu_wr_enable_3), + .vrf_out_data_mvu_4(vrf_mvu_out_4), //MVU TILE VRF + .vrf_readn_enable_mvu_4(vrf_mvu_readn_enable_4), + .vrf_wr_enable_mvu_4(vrf_mvu_wr_enable_4), + .vrf_out_data_mvu_5(vrf_mvu_out_5), //MVU TILE VRF + .vrf_readn_enable_mvu_5(vrf_mvu_readn_enable_5), + .vrf_wr_enable_mvu_5(vrf_mvu_wr_enable_5), + .vrf_out_data_mvu_6(vrf_mvu_out_6), //MVU TILE VRF + .vrf_readn_enable_mvu_6(vrf_mvu_readn_enable_6), + .vrf_wr_enable_mvu_6(vrf_mvu_wr_enable_6), + .vrf_out_data_mvu_7(vrf_mvu_out_7), //MVU TILE VRF + .vrf_readn_enable_mvu_7(vrf_mvu_readn_enable_7), + .vrf_wr_enable_mvu_7(vrf_mvu_wr_enable_7), + .vrf_out_data_mvu_8(vrf_mvu_out_8), //MVU TILE VRF + .vrf_readn_enable_mvu_8(vrf_mvu_readn_enable_8), + .vrf_wr_enable_mvu_8(vrf_mvu_wr_enable_8), + .vrf_out_data_mvu_9(vrf_mvu_out_9), //MVU TILE VRF + .vrf_readn_enable_mvu_9(vrf_mvu_readn_enable_9), + .vrf_wr_enable_mvu_9(vrf_mvu_wr_enable_9), + .vrf_out_data_mvu_10(vrf_mvu_out_10), //MVU TILE VRF + .vrf_readn_enable_mvu_10(vrf_mvu_readn_enable_10), + .vrf_wr_enable_mvu_10(vrf_mvu_wr_enable_10), + .vrf_out_data_mvu_11(vrf_mvu_out_11), //MVU TILE VRF + .vrf_readn_enable_mvu_11(vrf_mvu_readn_enable_11), + .vrf_wr_enable_mvu_11(vrf_mvu_wr_enable_11), + .vrf_out_data_mvu_12(vrf_mvu_out_12), //MVU TILE VRF + .vrf_readn_enable_mvu_12(vrf_mvu_readn_enable_12), + .vrf_wr_enable_mvu_12(vrf_mvu_wr_enable_12), + .vrf_out_data_mvu_13(vrf_mvu_out_13), //MVU TILE VRF + .vrf_readn_enable_mvu_13(vrf_mvu_readn_enable_13), + .vrf_wr_enable_mvu_13(vrf_mvu_wr_enable_13), + .vrf_out_data_mvu_14(vrf_mvu_out_14), //MVU TILE VRF + .vrf_readn_enable_mvu_14(vrf_mvu_readn_enable_14), + .vrf_wr_enable_mvu_14(vrf_mvu_wr_enable_14), + .vrf_out_data_mvu_15(vrf_mvu_out_15), //MVU TILE VRF + .vrf_readn_enable_mvu_15(vrf_mvu_readn_enable_15), + .vrf_wr_enable_mvu_15(vrf_mvu_wr_enable_15), + + .done_mvm(done_mvm), + .done_mfu_0(done_mfu_0), + .done_mfu_1(done_mfu_1), + //CHANGE INDEXING FOR VRFs-------------------------------------------- + + .vrf_out_data_mfu_add_0(vrf_mfu_out_data_add_0), + .vrf_readn_enable_mfu_add_0(vrf_mfu_readn_enable_add_0), + .vrf_wr_enable_mfu_add_0(vrf_mfu_wr_enable_add_0), //MFU VRF - ADD -0 + .vrf_addr_read_mfu_add_0(vrf_mfu_addr_read_add_0), + .vrf_addr_wr_mfu_add_0(vrf_mfu_addr_wr_add_0), + + + .vrf_out_data_mfu_mul_0(vrf_mfu_out_data_mul_0), //MFU VRF - MUL -0 + .vrf_readn_enable_mfu_mul_0(vrf_mfu_readn_enable_mul_0), + .vrf_wr_enable_mfu_mul_0(vrf_mfu_wr_enable_mul_0), + .vrf_addr_read_mfu_mul_0(vrf_mfu_addr_read_mul_0), + .vrf_addr_wr_mfu_mul_0(vrf_mfu_addr_wr_mul_0), + + .vrf_out_data_mfu_add_1(vrf_mfu_out_data_add_1), + .vrf_readn_enable_mfu_add_1(vrf_mfu_readn_enable_add_1), + .vrf_wr_enable_mfu_add_1(vrf_mfu_wr_enable_add_1), //MFU VRF - ADD - 1 + .vrf_addr_read_mfu_add_1(vrf_mfu_addr_read_add_1), + .vrf_addr_wr_mfu_add_1(vrf_mfu_addr_wr_add_1), + + + .vrf_out_data_mfu_mul_1(vrf_mfu_out_data_mul_1), //MFU VRF - MUL - 1 + .vrf_readn_enable_mfu_mul_1(vrf_mfu_readn_enable_mul_1), + .vrf_wr_enable_mfu_mul_1(vrf_mfu_wr_enable_mul_1), + .vrf_addr_read_mfu_mul_1(vrf_mfu_addr_read_mul_1), + .vrf_addr_wr_mfu_mul_1(vrf_mfu_addr_wr_mul_1), + + //MUXED VRF--------------------------------------- + .vrf_muxed_wr_addr_dram(vrf_muxed_wr_addr_dram), + .vrf_muxed_read_addr(vrf_muxed_read_addr), + .vrf_muxed_out_data_dram(vrf_muxed_out_data_dram), + .vrf_muxed_wr_enable_dram(vrf_muxed_wr_enable_dram), + .vrf_muxed_readn_enable(vrf_muxed_readn_enable), + //---------------------------------------------- + + .mvu_or_vrf_mux_select(mvu_or_vrf_mux_select), + .vrf_in_data(vrf_in_data), //common + + //----------------------------------------------------------------- + + .mrf_addr_wr(mrf_addr_wr), + .mrf_wr_enable(mrf_we), + .mrf_in_data(mrf_in_data), + + .mrf_we_for_dram(mrf_we_for_dram), + .mrf_addr_for_dram(mrf_addr_for_dram), + .mrf_outa_to_dram(mrf_outa_to_dram), + + //.orf_addr_increment(orf_addr_increment), + + .dstn_id(dstn_id) + ); + //*************************************************************************** + + //DELAYS START SIGNALS OF MVU TILE BY ONE CYCLE TO AVOID HIGH FANOUT AND ARITHEMETIC OF DONT CARES *********** + always@(posedge clk) begin + if(start_mv_mul_signal==1'b1) begin + start_tile_with_single_cyc_latency<={`NUM_LDPES{1'b1}}; + reset_tile_with_single_cyc_latency<={`NUM_LDPES{1'b0}}; + end + else begin + start_tile_with_single_cyc_latency<={`NUM_LDPES{1'b0}}; + reset_tile_with_single_cyc_latency<={`NUM_LDPES{1'b1}}; + end + end + + always@(*) begin + if(start_mfu_0_signal==1'b1) begin + reset_mfu_0_with_single_cyc_latency<=1'b0; + end + else begin + reset_mfu_0_with_single_cyc_latency<=1'b1; + end + end + + always@(*) begin + if(start_mfu_1_signal==1'b1) begin + reset_mfu_1_with_single_cyc_latency<=1'b0; + end + else begin + reset_mfu_1_with_single_cyc_latency<=1'b1; + end + end + + + //********************************************************************************************* + wire out_data_available_0; + //assign out_data_available_0 = done_mfu_0; + MFU mfu_stage_0( + .activation_type(activation), + .operation(operation), + .in_data_available(in_data_available_mfu_0), + + .vrf_addr_read_add(vrf_mfu_addr_read_add_0), + .vrf_addr_wr_add(vrf_mfu_addr_wr_add_0), + .vrf_readn_enable_add(vrf_mfu_readn_enable_add_0), + .vrf_wr_enable_add(vrf_mfu_wr_enable_add_0), + + .vrf_addr_read_mul(vrf_mfu_addr_read_mul_1), + .vrf_addr_wr_mul(vrf_mfu_addr_wr_mul_1), + .vrf_readn_enable_mul(vrf_mfu_readn_enable_mul_0), + .vrf_wr_enable_mul(vrf_mfu_wr_enable_mul_0), + + .primary_inp(primary_in_data_mfu_stage_0), + .secondary_inp(vrf_in_data[`ORF_DWIDTH-1:0]), + .out_data(output_mfu_stage_0), + .out_data_available(out_data_available_0), + .done(done_mfu_0), + .clk(clk), + + //VRF OUT SIGNALS + .out_vrf_add(vrf_mfu_out_data_add_0), + .out_vrf_mul(vrf_mfu_out_data_mul_0), + + .reset(reset_mfu_0_with_single_cyc_latency) + ); + + //************************************************************************* + //MFU STAGE - 2 + wire out_data_available_1; + //assign out_data_available_1 = done_mfu_1; + + MFU mfu_stage_1( + .activation_type(activation), + .operation(operation), + .in_data_available(in_data_available_mfu_1), + + //VRF IO SIGNALS FOR ELTWISE-ADD + .vrf_addr_read_add(vrf_mfu_addr_read_add_1), + .vrf_addr_wr_add(vrf_mfu_addr_wr_add_1), + .vrf_readn_enable_add(vrf_mfu_readn_enable_add_1), + .vrf_wr_enable_add(vrf_mfu_wr_enable_add_1), + + .vrf_addr_read_mul(vrf_mfu_addr_read_mul_1), + .vrf_addr_wr_mul(vrf_mfu_addr_wr_mul_1), + .vrf_readn_enable_mul(vrf_mfu_readn_enable_mul_1), + .vrf_wr_enable_mul(vrf_mfu_wr_enable_mul_1), + + //VRF IO SIGNALS FOR ELTWISE-MUL + .primary_inp(primary_in_data_mfu_stage_1), + .secondary_inp(vrf_in_data[`ORF_DWIDTH-1:0]), + .out_data(output_mfu_stage_1), + + .out_data_available(out_data_available_mfu_1), + .done(done_mfu_1), + .clk(clk), + + //VRF OUT SIGNAL + .out_vrf_add(vrf_mfu_out_data_add_1), + .out_vrf_mul(vrf_mfu_out_data_mul_1), + + .reset(reset_mfu_1_with_single_cyc_latency) + ); + + //************************************************************************* + + //************BYPASS MUXING LOGIC ***************************************** + + +endmodule +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM controller.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + + +//`include "includes_gen.v" + +module controller( + + input clk, + input reset_npu, + input done_mvm, + input done_mfu_0, + input done_mfu_1, + + + input[`INSTR_WIDTH-1:0] instruction, + output reg get_instr, + output reg[`INSTR_MEM_AWIDTH-1:0] get_instr_addr, + + input[`DRAM_DWIDTH-1:0] input_data_from_dram, + input[`ORF_DWIDTH-1:0] output_final_stage, + output reg[`DRAM_AWIDTH-1:0] dram_addr_wr, + output reg dram_write_enable, + output reg [`DRAM_DWIDTH-1:0] output_data_to_dram, + + //output reg start_mvu, + output reg start_mv_mul, + output reg start_mfu_0, + output reg start_mfu_1, + //output reg reset_mvu, + output reg in_data_available_mfu_0, + output reg in_data_available_mfu_1, + + output reg[1:0] activation, + output reg[1:0] operation, + + //FOR MVU IO + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_0, + output reg vrf_readn_enable_mvu_0, + output reg vrf_wr_enable_mvu_0, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_1, + output reg vrf_readn_enable_mvu_1, + output reg vrf_wr_enable_mvu_1, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_2, + output reg vrf_readn_enable_mvu_2, + output reg vrf_wr_enable_mvu_2, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_3, + output reg vrf_readn_enable_mvu_3, + output reg vrf_wr_enable_mvu_3, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_4, + output reg vrf_readn_enable_mvu_4, + output reg vrf_wr_enable_mvu_4, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_5, + output reg vrf_readn_enable_mvu_5, + output reg vrf_wr_enable_mvu_5, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_6, + output reg vrf_readn_enable_mvu_6, + output reg vrf_wr_enable_mvu_6, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_7, + output reg vrf_readn_enable_mvu_7, + output reg vrf_wr_enable_mvu_7, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_8, + output reg vrf_readn_enable_mvu_8, + output reg vrf_wr_enable_mvu_8, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_9, + output reg vrf_readn_enable_mvu_9, + output reg vrf_wr_enable_mvu_9, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_10, + output reg vrf_readn_enable_mvu_10, + output reg vrf_wr_enable_mvu_10, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_11, + output reg vrf_readn_enable_mvu_11, + output reg vrf_wr_enable_mvu_11, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_12, + output reg vrf_readn_enable_mvu_12, + output reg vrf_wr_enable_mvu_12, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_13, + output reg vrf_readn_enable_mvu_13, + output reg vrf_wr_enable_mvu_13, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_14, + output reg vrf_readn_enable_mvu_14, + output reg vrf_wr_enable_mvu_14, + + + input[`VRF_DWIDTH-1:0] vrf_out_data_mvu_15, + output reg vrf_readn_enable_mvu_15, + output reg vrf_wr_enable_mvu_15, + + + output reg[`VRF_AWIDTH-1:0] vrf_addr_read, + output reg[`VRF_AWIDTH-1:0] vrf_addr_wr, //********************* + + //FOR MFU STAGE -0 + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_add_0, + output reg vrf_readn_enable_mfu_add_0, + output reg vrf_wr_enable_mfu_add_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_add_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_add_0, + + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_mul_0, + output reg vrf_readn_enable_mfu_mul_0, + output reg vrf_wr_enable_mfu_mul_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_mul_0, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_mul_0, + // + + //FOR MFU STAGE -1 + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_add_1, + output reg vrf_readn_enable_mfu_add_1, + output reg vrf_wr_enable_mfu_add_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_add_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_add_1, + + input[`ORF_DWIDTH-1:0] vrf_out_data_mfu_mul_1, + output reg vrf_readn_enable_mfu_mul_1, + output reg vrf_wr_enable_mfu_mul_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_read_mfu_mul_1, + output reg[`ORF_AWIDTH-1:0] vrf_addr_wr_mfu_mul_1, + + //VRF MUXED + input[`ORF_DWIDTH-1:0] vrf_muxed_out_data_dram, + output reg[`ORF_AWIDTH-1:0] vrf_muxed_wr_addr_dram, + output reg[`ORF_AWIDTH-1:0] vrf_muxed_read_addr, + output reg vrf_muxed_wr_enable_dram, + output reg vrf_muxed_readn_enable, + // + + output reg[`MAX_VRF_DWIDTH-1:0] vrf_in_data, + + output mvu_or_vrf_mux_select, + + //MRF IO PORTS + output reg[`MRF_AWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_addr_wr, + output reg[`NUM_LDPES*`NUM_TILES-1:0] mrf_wr_enable, //NOTE: LOG(NUM_LDPES) = TARGET_OP_WIDTH + output reg[`MRF_DWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_in_data, + + output reg[`NUM_TILES*`NUM_LDPES-1:0] mrf_we_for_dram, + output reg [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram, + input [`NUM_TILES*`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram, + // + + //BYPASS SIGNALS + output[`TARGET_OP_WIDTH-1:0] dstn_id +); + + wire[`OPCODE_WIDTH-1:0] opcode; + wire[`VRF_AWIDTH-1:0] op1_address; + wire[`VRF_AWIDTH-1:0] op2_address; + wire[`VRF_AWIDTH-1:0] dstn_address; + wire[`TARGET_OP_WIDTH-1:0] src1_id; + //wire[`TARGET_OP_WIDTH-1:0] dstn_id; + + reg[1:0] state; + + //NOTE - CORRECT NAMING FOR OPERANDS AND EXTRACTION SCHEME FOR YOUR PARTS OF INSTRUCTION + assign op1_address = instruction[3*`VRF_AWIDTH+(`TARGET_OP_WIDTH)-1:(2*`VRF_AWIDTH) +(`TARGET_OP_WIDTH)]; + assign op2_address = instruction[2*`VRF_AWIDTH+`TARGET_OP_WIDTH-1:`VRF_AWIDTH+`TARGET_OP_WIDTH]; + assign dstn_address = instruction[`VRF_AWIDTH-1:0]; + assign opcode = instruction[`INSTR_WIDTH-1:`INSTR_WIDTH-`OPCODE_WIDTH]; + assign src1_id = instruction[3*`VRF_AWIDTH+2*`TARGET_OP_WIDTH-1:3*`VRF_AWIDTH+`TARGET_OP_WIDTH]; //or can be called mem_id + assign dstn_id = instruction[`VRF_AWIDTH+`TARGET_OP_WIDTH-1:`VRF_AWIDTH];//LSB for dram_write bypass + + assign mvu_or_vrf_mux_select = (op2_address!={`VRF_AWIDTH{1'b0}}); //UNUSED BIT FOR MFU OPERATIONS + + + //TODO - MAKE THIS SEQUENTIAL LOGIC - DONE + always@(posedge clk) begin + + if(reset_npu == 1'b1) begin + //reset_mvu<=1'b1; + //start_mvu<=1'b0; + get_instr<=1'bX; + + get_instr_addr<=0; + + start_mv_mul <= 1'b0; + + in_data_available_mfu_0 <= 1'b0; + start_mfu_0 <= 1'b0; + + in_data_available_mfu_1 <= 1'b0; + start_mfu_1 <= 1'b0; + dram_write_enable <= 1'b0; + mrf_wr_enable<='d0; + + + vrf_wr_enable_mvu_0<=1'b0; + vrf_readn_enable_mvu_0 <= 1'b0; + + + vrf_wr_enable_mvu_1<=1'b0; + vrf_readn_enable_mvu_1 <= 1'b0; + + + vrf_wr_enable_mvu_2<=1'b0; + vrf_readn_enable_mvu_2 <= 1'b0; + + + vrf_wr_enable_mvu_3<=1'b0; + vrf_readn_enable_mvu_3 <= 1'b0; + + + vrf_wr_enable_mvu_4<=1'b0; + vrf_readn_enable_mvu_4 <= 1'b0; + + + vrf_wr_enable_mvu_5<=1'b0; + vrf_readn_enable_mvu_5 <= 1'b0; + + + vrf_wr_enable_mvu_6<=1'b0; + vrf_readn_enable_mvu_6 <= 1'b0; + + + vrf_wr_enable_mvu_7<=1'b0; + vrf_readn_enable_mvu_7 <= 1'b0; + + + vrf_wr_enable_mvu_8<=1'b0; + vrf_readn_enable_mvu_8 <= 1'b0; + + + vrf_wr_enable_mvu_9<=1'b0; + vrf_readn_enable_mvu_9 <= 1'b0; + + + vrf_wr_enable_mvu_10<=1'b0; + vrf_readn_enable_mvu_10 <= 1'b0; + + + vrf_wr_enable_mvu_11<=1'b0; + vrf_readn_enable_mvu_11 <= 1'b0; + + + vrf_wr_enable_mvu_12<=1'b0; + vrf_readn_enable_mvu_12 <= 1'b0; + + + vrf_wr_enable_mvu_13<=1'b0; + vrf_readn_enable_mvu_13 <= 1'b0; + + + vrf_wr_enable_mvu_14<=1'b0; + vrf_readn_enable_mvu_14 <= 1'b0; + + + vrf_wr_enable_mvu_15<=1'b0; + vrf_readn_enable_mvu_15 <= 1'b0; + + + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + + dram_addr_wr<=10'd0; + vrf_addr_wr <= 10'd0; + //vrf_addr_wr_mvu_1 <= 0; + vrf_addr_wr_mfu_add_0 <= 10'd0; + vrf_addr_wr_mfu_mul_0 <= 10'd0; + vrf_addr_wr_mfu_add_1 <= 10'd0; + vrf_addr_wr_mfu_mul_1 <= 10'd0; + + vrf_addr_read <= 10'd0; + //vrf_addr_read_mvu_1 <= 0; + vrf_addr_read_mfu_add_0 <= 10'd0; + vrf_addr_read_mfu_mul_0 <= 10'd0; + vrf_addr_read_mfu_add_1 <= 10'd0; + vrf_addr_read_mfu_mul_1 <= 10'd0; + + + //vrf_muxed_wr_addr_dram <= 0; + //vrf_muxed_read_addr <= 0; + vrf_muxed_wr_enable_dram <= 1'b0; + vrf_muxed_readn_enable <= 1'b0; + + // orf_addr_increment<=1'b0; + + mrf_addr_wr <= 10'd0; + + state <= 0; + end + else begin + if(state==0) begin //FETCH + get_instr <= 1'b0; + state <= 1; + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable <= 1'b0; + mrf_wr_enable <= 0; + end + else if(state==1) begin //DECODE + case(opcode) + `V_WR: begin + state <= 2; + get_instr<=0; + //get_instr_addr<=get_instr_addr+1'b1; + case(src1_id) + `VRF_0: begin vrf_wr_enable_mvu_0 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_1: begin vrf_wr_enable_mvu_1 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_2: begin vrf_wr_enable_mvu_2 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_3: begin vrf_wr_enable_mvu_3 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_4: begin vrf_wr_enable_mvu_4 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_5: begin vrf_wr_enable_mvu_5 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_6: begin vrf_wr_enable_mvu_6 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_7: begin vrf_wr_enable_mvu_7 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_8: begin vrf_wr_enable_mvu_8 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_9: begin vrf_wr_enable_mvu_9 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_10: begin vrf_wr_enable_mvu_10 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_11: begin vrf_wr_enable_mvu_11 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_12: begin vrf_wr_enable_mvu_12 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_13: begin vrf_wr_enable_mvu_13 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_14: begin vrf_wr_enable_mvu_14 <= 1'b0; + vrf_addr_wr <= op1_address; + end + `VRF_15: begin vrf_wr_enable_mvu_15 <= 1'b0; + vrf_addr_wr <= op1_address; + end + + `VRF_16: begin vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_addr_wr_mfu_add_0 <= op1_address; + end + + `VRF_17: begin vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_addr_wr_mfu_mul_0 <= op1_address; + end + + `VRF_18: begin vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_addr_wr_mfu_add_1 <= op1_address; + end + + `VRF_19: begin + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_addr_wr_mfu_mul_1 <= op1_address; + end + + `VRF_MUXED: begin + vrf_muxed_wr_enable_dram <= 1'b0; + vrf_muxed_wr_addr_dram <= op1_address; + end + + default: begin + vrf_wr_enable_mvu_0 <= 1'bX; + output_data_to_dram <= 'd0; + end + + endcase + + dram_addr_wr <= dstn_address; + dram_write_enable <= 1'b1; + end + `M_WR: begin + state <= 2; + get_instr<=0; + + case(src1_id) + `MRF_0: begin mrf_we_for_dram[0] <= 1'b0; + mrf_addr_for_dram[1*`MRF_AWIDTH-1:0*`MRF_AWIDTH] <= op1_address; + end + `MRF_1: begin mrf_we_for_dram[1] <= 1'b0; + mrf_addr_for_dram[2*`MRF_AWIDTH-1:1*`MRF_AWIDTH] <= op1_address; + end + `MRF_2: begin mrf_we_for_dram[2] <= 1'b0; + mrf_addr_for_dram[3*`MRF_AWIDTH-1:2*`MRF_AWIDTH] <= op1_address; + end + `MRF_3: begin mrf_we_for_dram[3] <= 1'b0; + mrf_addr_for_dram[4*`MRF_AWIDTH-1:3*`MRF_AWIDTH] <= op1_address; + end + `MRF_4: begin mrf_we_for_dram[4] <= 1'b0; + mrf_addr_for_dram[5*`MRF_AWIDTH-1:4*`MRF_AWIDTH] <= op1_address; + end + `MRF_5: begin mrf_we_for_dram[5] <= 1'b0; + mrf_addr_for_dram[6*`MRF_AWIDTH-1:5*`MRF_AWIDTH] <= op1_address; + end + `MRF_6: begin mrf_we_for_dram[6] <= 1'b0; + mrf_addr_for_dram[7*`MRF_AWIDTH-1:6*`MRF_AWIDTH] <= op1_address; + end + `MRF_7: begin mrf_we_for_dram[7] <= 1'b0; + mrf_addr_for_dram[8*`MRF_AWIDTH-1:7*`MRF_AWIDTH] <= op1_address; + end + `MRF_8: begin mrf_we_for_dram[8] <= 1'b0; + mrf_addr_for_dram[9*`MRF_AWIDTH-1:8*`MRF_AWIDTH] <= op1_address; + end + `MRF_9: begin mrf_we_for_dram[9] <= 1'b0; + mrf_addr_for_dram[10*`MRF_AWIDTH-1:9*`MRF_AWIDTH] <= op1_address; + end + `MRF_10: begin mrf_we_for_dram[10] <= 1'b0; + mrf_addr_for_dram[11*`MRF_AWIDTH-1:10*`MRF_AWIDTH] <= op1_address; + end + `MRF_11: begin mrf_we_for_dram[11] <= 1'b0; + mrf_addr_for_dram[12*`MRF_AWIDTH-1:11*`MRF_AWIDTH] <= op1_address; + end + `MRF_12: begin mrf_we_for_dram[12] <= 1'b0; + mrf_addr_for_dram[13*`MRF_AWIDTH-1:12*`MRF_AWIDTH] <= op1_address; + end + `MRF_13: begin mrf_we_for_dram[13] <= 1'b0; + mrf_addr_for_dram[14*`MRF_AWIDTH-1:13*`MRF_AWIDTH] <= op1_address; + end + `MRF_14: begin mrf_we_for_dram[14] <= 1'b0; + mrf_addr_for_dram[15*`MRF_AWIDTH-1:14*`MRF_AWIDTH] <= op1_address; + end + `MRF_15: begin mrf_we_for_dram[15] <= 1'b0; + mrf_addr_for_dram[16*`MRF_AWIDTH-1:15*`MRF_AWIDTH] <= op1_address; + end + `MRF_16: begin mrf_we_for_dram[16] <= 1'b0; + mrf_addr_for_dram[17*`MRF_AWIDTH-1:16*`MRF_AWIDTH] <= op1_address; + end + `MRF_17: begin mrf_we_for_dram[17] <= 1'b0; + mrf_addr_for_dram[18*`MRF_AWIDTH-1:17*`MRF_AWIDTH] <= op1_address; + end + `MRF_18: begin mrf_we_for_dram[18] <= 1'b0; + mrf_addr_for_dram[19*`MRF_AWIDTH-1:18*`MRF_AWIDTH] <= op1_address; + end + `MRF_19: begin mrf_we_for_dram[19] <= 1'b0; + mrf_addr_for_dram[20*`MRF_AWIDTH-1:19*`MRF_AWIDTH] <= op1_address; + end + `MRF_20: begin mrf_we_for_dram[20] <= 1'b0; + mrf_addr_for_dram[21*`MRF_AWIDTH-1:20*`MRF_AWIDTH] <= op1_address; + end + `MRF_21: begin mrf_we_for_dram[21] <= 1'b0; + mrf_addr_for_dram[22*`MRF_AWIDTH-1:21*`MRF_AWIDTH] <= op1_address; + end + `MRF_22: begin mrf_we_for_dram[22] <= 1'b0; + mrf_addr_for_dram[23*`MRF_AWIDTH-1:22*`MRF_AWIDTH] <= op1_address; + end + `MRF_23: begin mrf_we_for_dram[23] <= 1'b0; + mrf_addr_for_dram[24*`MRF_AWIDTH-1:23*`MRF_AWIDTH] <= op1_address; + end + `MRF_24: begin mrf_we_for_dram[24] <= 1'b0; + mrf_addr_for_dram[25*`MRF_AWIDTH-1:24*`MRF_AWIDTH] <= op1_address; + end + `MRF_25: begin mrf_we_for_dram[25] <= 1'b0; + mrf_addr_for_dram[26*`MRF_AWIDTH-1:25*`MRF_AWIDTH] <= op1_address; + end + `MRF_26: begin mrf_we_for_dram[26] <= 1'b0; + mrf_addr_for_dram[27*`MRF_AWIDTH-1:26*`MRF_AWIDTH] <= op1_address; + end + `MRF_27: begin mrf_we_for_dram[27] <= 1'b0; + mrf_addr_for_dram[28*`MRF_AWIDTH-1:27*`MRF_AWIDTH] <= op1_address; + end + `MRF_28: begin mrf_we_for_dram[28] <= 1'b0; + mrf_addr_for_dram[29*`MRF_AWIDTH-1:28*`MRF_AWIDTH] <= op1_address; + end + `MRF_29: begin mrf_we_for_dram[29] <= 1'b0; + mrf_addr_for_dram[30*`MRF_AWIDTH-1:29*`MRF_AWIDTH] <= op1_address; + end + `MRF_30: begin mrf_we_for_dram[30] <= 1'b0; + mrf_addr_for_dram[31*`MRF_AWIDTH-1:30*`MRF_AWIDTH] <= op1_address; + end + `MRF_31: begin mrf_we_for_dram[31] <= 1'b0; + mrf_addr_for_dram[32*`MRF_AWIDTH-1:31*`MRF_AWIDTH] <= op1_address; + end + `MRF_32: begin mrf_we_for_dram[32] <= 1'b0; + mrf_addr_for_dram[33*`MRF_AWIDTH-1:32*`MRF_AWIDTH] <= op1_address; + end + `MRF_33: begin mrf_we_for_dram[33] <= 1'b0; + mrf_addr_for_dram[34*`MRF_AWIDTH-1:33*`MRF_AWIDTH] <= op1_address; + end + `MRF_34: begin mrf_we_for_dram[34] <= 1'b0; + mrf_addr_for_dram[35*`MRF_AWIDTH-1:34*`MRF_AWIDTH] <= op1_address; + end + `MRF_35: begin mrf_we_for_dram[35] <= 1'b0; + mrf_addr_for_dram[36*`MRF_AWIDTH-1:35*`MRF_AWIDTH] <= op1_address; + end + `MRF_36: begin mrf_we_for_dram[36] <= 1'b0; + mrf_addr_for_dram[37*`MRF_AWIDTH-1:36*`MRF_AWIDTH] <= op1_address; + end + `MRF_37: begin mrf_we_for_dram[37] <= 1'b0; + mrf_addr_for_dram[38*`MRF_AWIDTH-1:37*`MRF_AWIDTH] <= op1_address; + end + `MRF_38: begin mrf_we_for_dram[38] <= 1'b0; + mrf_addr_for_dram[39*`MRF_AWIDTH-1:38*`MRF_AWIDTH] <= op1_address; + end + `MRF_39: begin mrf_we_for_dram[39] <= 1'b0; + mrf_addr_for_dram[40*`MRF_AWIDTH-1:39*`MRF_AWIDTH] <= op1_address; + end + `MRF_40: begin mrf_we_for_dram[40] <= 1'b0; + mrf_addr_for_dram[41*`MRF_AWIDTH-1:40*`MRF_AWIDTH] <= op1_address; + end + `MRF_41: begin mrf_we_for_dram[41] <= 1'b0; + mrf_addr_for_dram[42*`MRF_AWIDTH-1:41*`MRF_AWIDTH] <= op1_address; + end + `MRF_42: begin mrf_we_for_dram[42] <= 1'b0; + mrf_addr_for_dram[43*`MRF_AWIDTH-1:42*`MRF_AWIDTH] <= op1_address; + end + `MRF_43: begin mrf_we_for_dram[43] <= 1'b0; + mrf_addr_for_dram[44*`MRF_AWIDTH-1:43*`MRF_AWIDTH] <= op1_address; + end + `MRF_44: begin mrf_we_for_dram[44] <= 1'b0; + mrf_addr_for_dram[45*`MRF_AWIDTH-1:44*`MRF_AWIDTH] <= op1_address; + end + `MRF_45: begin mrf_we_for_dram[45] <= 1'b0; + mrf_addr_for_dram[46*`MRF_AWIDTH-1:45*`MRF_AWIDTH] <= op1_address; + end + `MRF_46: begin mrf_we_for_dram[46] <= 1'b0; + mrf_addr_for_dram[47*`MRF_AWIDTH-1:46*`MRF_AWIDTH] <= op1_address; + end + `MRF_47: begin mrf_we_for_dram[47] <= 1'b0; + mrf_addr_for_dram[48*`MRF_AWIDTH-1:47*`MRF_AWIDTH] <= op1_address; + end + `MRF_48: begin mrf_we_for_dram[48] <= 1'b0; + mrf_addr_for_dram[49*`MRF_AWIDTH-1:48*`MRF_AWIDTH] <= op1_address; + end + `MRF_49: begin mrf_we_for_dram[49] <= 1'b0; + mrf_addr_for_dram[50*`MRF_AWIDTH-1:49*`MRF_AWIDTH] <= op1_address; + end + `MRF_50: begin mrf_we_for_dram[50] <= 1'b0; + mrf_addr_for_dram[51*`MRF_AWIDTH-1:50*`MRF_AWIDTH] <= op1_address; + end + `MRF_51: begin mrf_we_for_dram[51] <= 1'b0; + mrf_addr_for_dram[52*`MRF_AWIDTH-1:51*`MRF_AWIDTH] <= op1_address; + end + `MRF_52: begin mrf_we_for_dram[52] <= 1'b0; + mrf_addr_for_dram[53*`MRF_AWIDTH-1:52*`MRF_AWIDTH] <= op1_address; + end + `MRF_53: begin mrf_we_for_dram[53] <= 1'b0; + mrf_addr_for_dram[54*`MRF_AWIDTH-1:53*`MRF_AWIDTH] <= op1_address; + end + `MRF_54: begin mrf_we_for_dram[54] <= 1'b0; + mrf_addr_for_dram[55*`MRF_AWIDTH-1:54*`MRF_AWIDTH] <= op1_address; + end + `MRF_55: begin mrf_we_for_dram[55] <= 1'b0; + mrf_addr_for_dram[56*`MRF_AWIDTH-1:55*`MRF_AWIDTH] <= op1_address; + end + `MRF_56: begin mrf_we_for_dram[56] <= 1'b0; + mrf_addr_for_dram[57*`MRF_AWIDTH-1:56*`MRF_AWIDTH] <= op1_address; + end + `MRF_57: begin mrf_we_for_dram[57] <= 1'b0; + mrf_addr_for_dram[58*`MRF_AWIDTH-1:57*`MRF_AWIDTH] <= op1_address; + end + `MRF_58: begin mrf_we_for_dram[58] <= 1'b0; + mrf_addr_for_dram[59*`MRF_AWIDTH-1:58*`MRF_AWIDTH] <= op1_address; + end + `MRF_59: begin mrf_we_for_dram[59] <= 1'b0; + mrf_addr_for_dram[60*`MRF_AWIDTH-1:59*`MRF_AWIDTH] <= op1_address; + end + `MRF_60: begin mrf_we_for_dram[60] <= 1'b0; + mrf_addr_for_dram[61*`MRF_AWIDTH-1:60*`MRF_AWIDTH] <= op1_address; + end + `MRF_61: begin mrf_we_for_dram[61] <= 1'b0; + mrf_addr_for_dram[62*`MRF_AWIDTH-1:61*`MRF_AWIDTH] <= op1_address; + end + `MRF_62: begin mrf_we_for_dram[62] <= 1'b0; + mrf_addr_for_dram[63*`MRF_AWIDTH-1:62*`MRF_AWIDTH] <= op1_address; + end + `MRF_63: begin mrf_we_for_dram[63] <= 1'b0; + mrf_addr_for_dram[64*`MRF_AWIDTH-1:63*`MRF_AWIDTH] <= op1_address; + end + default: begin mrf_we_for_dram <= 'd0; + mrf_addr_for_dram <= 'd0; + end + endcase + + dram_addr_wr <= dstn_address; + dram_write_enable <= 1'b1; + end + `V_RD: begin + state <= 2; + get_instr<=0; + dram_addr_wr <= op1_address; + dram_write_enable <= 1'b0; + + end + //CHANGE NAMING CONVENTION FOR WRITE AND READ TO STORE AND LOAD + //ADD COMMENTS FOR SRC AND DESTINATION + `M_RD: begin + state <= 2; + get_instr<=0; + dram_addr_wr <= op1_address; + dram_write_enable <= 1'b0; + end + `MV_MUL: begin + //op1_id is don't care for this instructions + + state <= 2; + get_instr<=1'b0; + start_mv_mul <= 1'b1; + mrf_addr_wr[(1*`MRF_AWIDTH)-1:0*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(2*`MRF_AWIDTH)-1:1*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(3*`MRF_AWIDTH)-1:2*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(4*`MRF_AWIDTH)-1:3*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(5*`MRF_AWIDTH)-1:4*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(6*`MRF_AWIDTH)-1:5*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(7*`MRF_AWIDTH)-1:6*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(8*`MRF_AWIDTH)-1:7*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(9*`MRF_AWIDTH)-1:8*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(10*`MRF_AWIDTH)-1:9*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(11*`MRF_AWIDTH)-1:10*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(12*`MRF_AWIDTH)-1:11*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(13*`MRF_AWIDTH)-1:12*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(14*`MRF_AWIDTH)-1:13*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(15*`MRF_AWIDTH)-1:14*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(16*`MRF_AWIDTH)-1:15*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(17*`MRF_AWIDTH)-1:16*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(18*`MRF_AWIDTH)-1:17*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(19*`MRF_AWIDTH)-1:18*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(20*`MRF_AWIDTH)-1:19*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(21*`MRF_AWIDTH)-1:20*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(22*`MRF_AWIDTH)-1:21*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(23*`MRF_AWIDTH)-1:22*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(24*`MRF_AWIDTH)-1:23*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(25*`MRF_AWIDTH)-1:24*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(26*`MRF_AWIDTH)-1:25*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(27*`MRF_AWIDTH)-1:26*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(28*`MRF_AWIDTH)-1:27*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(29*`MRF_AWIDTH)-1:28*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(30*`MRF_AWIDTH)-1:29*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(31*`MRF_AWIDTH)-1:30*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(32*`MRF_AWIDTH)-1:31*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(33*`MRF_AWIDTH)-1:32*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(34*`MRF_AWIDTH)-1:33*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(35*`MRF_AWIDTH)-1:34*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(36*`MRF_AWIDTH)-1:35*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(37*`MRF_AWIDTH)-1:36*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(38*`MRF_AWIDTH)-1:37*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(39*`MRF_AWIDTH)-1:38*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(40*`MRF_AWIDTH)-1:39*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(41*`MRF_AWIDTH)-1:40*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(42*`MRF_AWIDTH)-1:41*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(43*`MRF_AWIDTH)-1:42*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(44*`MRF_AWIDTH)-1:43*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(45*`MRF_AWIDTH)-1:44*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(46*`MRF_AWIDTH)-1:45*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(47*`MRF_AWIDTH)-1:46*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(48*`MRF_AWIDTH)-1:47*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(49*`MRF_AWIDTH)-1:48*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(50*`MRF_AWIDTH)-1:49*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(51*`MRF_AWIDTH)-1:50*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(52*`MRF_AWIDTH)-1:51*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(53*`MRF_AWIDTH)-1:52*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(54*`MRF_AWIDTH)-1:53*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(55*`MRF_AWIDTH)-1:54*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(56*`MRF_AWIDTH)-1:55*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(57*`MRF_AWIDTH)-1:56*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(58*`MRF_AWIDTH)-1:57*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(59*`MRF_AWIDTH)-1:58*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(60*`MRF_AWIDTH)-1:59*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(61*`MRF_AWIDTH)-1:60*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(62*`MRF_AWIDTH)-1:61*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(63*`MRF_AWIDTH)-1:62*`MRF_AWIDTH] <= op1_address; + mrf_addr_wr[(64*`MRF_AWIDTH)-1:63*`MRF_AWIDTH] <= op1_address; + vrf_addr_read <= op2_address; + vrf_readn_enable_mvu_0 <= 1'b0; + vrf_readn_enable_mvu_1 <= 1'b0; + vrf_readn_enable_mvu_2 <= 1'b0; + vrf_readn_enable_mvu_3 <= 1'b0; + vrf_readn_enable_mvu_4 <= 1'b0; + vrf_readn_enable_mvu_5 <= 1'b0; + vrf_readn_enable_mvu_6 <= 1'b0; + vrf_readn_enable_mvu_7 <= 1'b0; + vrf_readn_enable_mvu_8 <= 1'b0; + vrf_readn_enable_mvu_9 <= 1'b0; + vrf_readn_enable_mvu_10 <= 1'b0; + vrf_readn_enable_mvu_11 <= 1'b0; + vrf_readn_enable_mvu_12 <= 1'b0; + vrf_readn_enable_mvu_13 <= 1'b0; + vrf_readn_enable_mvu_14 <= 1'b0; + vrf_readn_enable_mvu_15 <= 1'b0; + mrf_wr_enable <= 0; + end + `VV_ADD:begin + + //MFU_STAGE-0 DESIGNATED FOR ELTWISE ADD + state <= 2; + get_instr <= 1'b0; + operation <= `ELT_WISE_ADD; //NOTE - 2nd VRF INDEX IS FOR ADD UNITS ELT WISE + activation <= 0; + + case(src1_id) + + `VRF_16: begin + start_mfu_0 <= 1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + + in_data_available_mfu_0 <= 1'b1; + vrf_addr_read_mfu_add_0 <= op1_address; + vrf_readn_enable_mfu_add_0 <= 1'b0; + end + + + `VRF_18: begin + start_mfu_1 <= 1'b1; + in_data_available_mfu_1 <= 1'b1; + vrf_addr_read_mfu_add_1 <= op1_address; + vrf_readn_enable_mfu_add_1 <= 1'b0; + end + + + default: begin + start_mfu_0 <= 1'b1; + in_data_available_mfu_0 <= 1'b1; + vrf_addr_read_mfu_add_0 <= 10'd0; + vrf_readn_enable_mfu_add_0 <= 1'b1; + vrf_addr_read_mfu_add_1 <= 10'd0; + vrf_readn_enable_mfu_add_1 <= 1'b1; + end + + endcase + + end + `VV_SUB:begin + + //MFU_STAGE-0 DESIGNATED FOR ELTWISE ADD + state <= 2; + get_instr<=1'b0; + operation<=`ELT_WISE_ADD; //NOTE - 2nd VRF INDEX IS FOR ADD UNITS ELT WISE + + activation <= 1; + + case(src1_id) + + `VRF_16: begin + start_mfu_0 <= 1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + + in_data_available_mfu_0 <= 1'b1; + vrf_addr_read_mfu_add_0 <= op1_address; + vrf_readn_enable_mfu_add_0 <= 1'b0; + end + + + `VRF_18: begin + start_mfu_1 <= 1'b1; + in_data_available_mfu_1 <= 1'b1; + vrf_addr_read_mfu_add_1 <= op1_address; + vrf_readn_enable_mfu_add_1 <= 1'b0; + end + + + default: begin + start_mfu_0 <= 1'b0; + in_data_available_mfu_0 <= 1'b0; + vrf_addr_read_mfu_add_0 <= 10'd0; + vrf_readn_enable_mfu_add_0 <= 1'b0; + vrf_addr_read_mfu_add_1 <= 10'd0; + vrf_readn_enable_mfu_add_1 <= 1'b0; + end + + endcase + + end + `VV_MUL:begin + state <= 2; + get_instr<=1'b0; + + operation<=`ELT_WISE_MULTIPLY; //NOTE - 3RD VRF INDEX IS FOR ADD UNITS ELT WISE + case(src1_id) + + `VRF_17: begin + start_mfu_0 <= 1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + + in_data_available_mfu_0 <= 1'b1; + vrf_addr_read_mfu_mul_0 <= op1_address; + vrf_readn_enable_mfu_mul_0 <= 1'b0; + end + + `VRF_19: begin + start_mfu_1 <= 1'b1; + in_data_available_mfu_1 <= 1'b1; + vrf_addr_read_mfu_mul_1 <= op1_address; + vrf_readn_enable_mfu_mul_1 <= 1'b0; + end + + default: begin + start_mfu_0 <= 1'b0; + in_data_available_mfu_0 <= 1'b0; + vrf_addr_read_mfu_mul_0 <= 10'd0; + vrf_readn_enable_mfu_mul_0 <= 1'b0; + vrf_addr_read_mfu_mul_1 <= 10'd0; + vrf_readn_enable_mfu_mul_1 <= 1'b0; + end + + endcase + + end + `V_RELU:begin + + get_instr<=1'b0; + case(src1_id) + + `MFU_0: begin + start_mfu_0<=1'b1; + in_data_available_mfu_0<=1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + end + + `MFU_1: begin + start_mfu_1<=1'b1; + in_data_available_mfu_1<=1'b1; + end + + default: begin + start_mfu_0<=1'bX; + in_data_available_mfu_0<=1'bX; + end + + endcase + operation<=`ACTIVATION; + activation<=`RELU; + state <= 2; + + end + `V_SIGM:begin + + get_instr<=1'b0; + case(src1_id) + + `MFU_0: begin + start_mfu_0<=1'b1; + in_data_available_mfu_0<=1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + end + + `MFU_1: begin + start_mfu_1<=1'b1; + in_data_available_mfu_1<=1'b1; + end + + default: begin + start_mfu_0<=1'bX; + in_data_available_mfu_0<=1'bX; + end + + endcase + operation<=`ACTIVATION; + activation<=`SIGM; + state <= 2; + end + `V_TANH:begin + //dram_write_enable <= bypass_id[0]; + get_instr<=1'b0; + case(src1_id) + + `MFU_0: begin + start_mfu_0<=1'b1; + in_data_available_mfu_0<=1'b1; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_read_addr <= op2_address; + end + + `MFU_1: begin + start_mfu_1<=1'b1; + in_data_available_mfu_1<=1'b1; + end + + default: begin + start_mfu_0<=1'bX; + in_data_available_mfu_0<=1'bX; + end + + endcase + operation<=`ACTIVATION; + activation<=`TANH; + state <= 2; + + end + `END_CHAIN :begin + + start_mv_mul<=1'b0; + get_instr<=1'b0; + + in_data_available_mfu_0<=1'b0; + start_mfu_0<=1'b0; + + in_data_available_mfu_1<=1'b0; + start_mfu_1<=1'b0; + + mrf_wr_enable<=0; + + + vrf_wr_enable_mvu_0<='b0; + vrf_readn_enable_mvu_0 <= 'b0; + + + vrf_wr_enable_mvu_1<='b0; + vrf_readn_enable_mvu_1 <= 'b0; + + + vrf_wr_enable_mvu_2<='b0; + vrf_readn_enable_mvu_2 <= 'b0; + + + vrf_wr_enable_mvu_3<='b0; + vrf_readn_enable_mvu_3 <= 'b0; + + + vrf_wr_enable_mvu_4<='b0; + vrf_readn_enable_mvu_4 <= 'b0; + + + vrf_wr_enable_mvu_5<='b0; + vrf_readn_enable_mvu_5 <= 'b0; + + + vrf_wr_enable_mvu_6<='b0; + vrf_readn_enable_mvu_6 <= 'b0; + + + vrf_wr_enable_mvu_7<='b0; + vrf_readn_enable_mvu_7 <= 'b0; + + + vrf_wr_enable_mvu_8<='b0; + vrf_readn_enable_mvu_8 <= 'b0; + + + vrf_wr_enable_mvu_9<='b0; + vrf_readn_enable_mvu_9 <= 'b0; + + + vrf_wr_enable_mvu_10<='b0; + vrf_readn_enable_mvu_10 <= 'b0; + + + vrf_wr_enable_mvu_11<='b0; + vrf_readn_enable_mvu_11 <= 'b0; + + + vrf_wr_enable_mvu_12<='b0; + vrf_readn_enable_mvu_12 <= 'b0; + + + vrf_wr_enable_mvu_13<='b0; + vrf_readn_enable_mvu_13 <= 'b0; + + + vrf_wr_enable_mvu_14<='b0; + vrf_readn_enable_mvu_14 <= 'b0; + + + vrf_wr_enable_mvu_15<='b0; + vrf_readn_enable_mvu_15 <= 'b0; + + + vrf_wr_enable_mfu_add_0 <= 0; + vrf_wr_enable_mfu_mul_0 <= 0; + vrf_wr_enable_mfu_add_1 <= 0; + vrf_wr_enable_mfu_mul_1 <= 0; + + vrf_muxed_readn_enable <= 1'b0; + vrf_muxed_wr_addr_dram <= 1'b0; + + vrf_readn_enable_mfu_add_0 <= 0; + vrf_readn_enable_mfu_mul_0 <= 0; + vrf_readn_enable_mfu_add_1 <= 0; + vrf_readn_enable_mfu_mul_1 <= 0; + + //orf_addr_increment<=1'b0; + mrf_addr_wr <= 0; + dram_write_enable <= 1'b0; + state <= 1; + end + endcase + end + else begin //EXECUTE + + case(opcode) + `V_WR: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(src1_id) + + `VRF_0: begin + output_data_to_dram <= vrf_out_data_mvu_0; + end + `VRF_1: begin + output_data_to_dram <= vrf_out_data_mvu_1; + end + `VRF_2: begin + output_data_to_dram <= vrf_out_data_mvu_2; + end + `VRF_3: begin + output_data_to_dram <= vrf_out_data_mvu_3; + end + `VRF_4: begin + output_data_to_dram <= vrf_out_data_mvu_4; + end + `VRF_5: begin + output_data_to_dram <= vrf_out_data_mvu_5; + end + `VRF_6: begin + output_data_to_dram <= vrf_out_data_mvu_6; + end + `VRF_7: begin + output_data_to_dram <= vrf_out_data_mvu_7; + end + `VRF_8: begin + output_data_to_dram <= vrf_out_data_mvu_8; + end + `VRF_9: begin + output_data_to_dram <= vrf_out_data_mvu_9; + end + `VRF_10: begin + output_data_to_dram <= vrf_out_data_mvu_10; + end + `VRF_11: begin + output_data_to_dram <= vrf_out_data_mvu_11; + end + `VRF_12: begin + output_data_to_dram <= vrf_out_data_mvu_12; + end + `VRF_13: begin + output_data_to_dram <= vrf_out_data_mvu_13; + end + `VRF_14: begin + output_data_to_dram <= vrf_out_data_mvu_14; + end + `VRF_15: begin + output_data_to_dram <= vrf_out_data_mvu_15; + end + + `VRF_16: begin + output_data_to_dram <= vrf_out_data_mfu_add_0; + end + + `VRF_17: begin + output_data_to_dram <= vrf_out_data_mfu_mul_0; + end + + `VRF_18: begin + output_data_to_dram <= vrf_out_data_mfu_add_1; + end + + `VRF_19: begin + output_data_to_dram <= vrf_out_data_mfu_mul_1; + end + + `VRF_MUXED: begin + output_data_to_dram <= vrf_muxed_out_data_dram; + end + default: begin + output_data_to_dram <= 'd0; + end + endcase + + end + `M_WR: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(src1_id) + + `MRF_0: begin + output_data_to_dram <= mrf_outa_to_dram[1*`MRF_DWIDTH-1:0*`MRF_DWIDTH]; + end + `MRF_1: begin + output_data_to_dram <= mrf_outa_to_dram[2*`MRF_DWIDTH-1:1*`MRF_DWIDTH]; + end + `MRF_2: begin + output_data_to_dram <= mrf_outa_to_dram[3*`MRF_DWIDTH-1:2*`MRF_DWIDTH]; + end + `MRF_3: begin + output_data_to_dram <= mrf_outa_to_dram[4*`MRF_DWIDTH-1:3*`MRF_DWIDTH]; + end + `MRF_4: begin + output_data_to_dram <= mrf_outa_to_dram[5*`MRF_DWIDTH-1:4*`MRF_DWIDTH]; + end + `MRF_5: begin + output_data_to_dram <= mrf_outa_to_dram[6*`MRF_DWIDTH-1:5*`MRF_DWIDTH]; + end + `MRF_6: begin + output_data_to_dram <= mrf_outa_to_dram[7*`MRF_DWIDTH-1:6*`MRF_DWIDTH]; + end + `MRF_7: begin + output_data_to_dram <= mrf_outa_to_dram[8*`MRF_DWIDTH-1:7*`MRF_DWIDTH]; + end + `MRF_8: begin + output_data_to_dram <= mrf_outa_to_dram[9*`MRF_DWIDTH-1:8*`MRF_DWIDTH]; + end + `MRF_9: begin + output_data_to_dram <= mrf_outa_to_dram[10*`MRF_DWIDTH-1:9*`MRF_DWIDTH]; + end + `MRF_10: begin + output_data_to_dram <= mrf_outa_to_dram[11*`MRF_DWIDTH-1:10*`MRF_DWIDTH]; + end + `MRF_11: begin + output_data_to_dram <= mrf_outa_to_dram[12*`MRF_DWIDTH-1:11*`MRF_DWIDTH]; + end + `MRF_12: begin + output_data_to_dram <= mrf_outa_to_dram[13*`MRF_DWIDTH-1:12*`MRF_DWIDTH]; + end + `MRF_13: begin + output_data_to_dram <= mrf_outa_to_dram[14*`MRF_DWIDTH-1:13*`MRF_DWIDTH]; + end + `MRF_14: begin + output_data_to_dram <= mrf_outa_to_dram[15*`MRF_DWIDTH-1:14*`MRF_DWIDTH]; + end + `MRF_15: begin + output_data_to_dram <= mrf_outa_to_dram[16*`MRF_DWIDTH-1:15*`MRF_DWIDTH]; + end + `MRF_16: begin + output_data_to_dram <= mrf_outa_to_dram[17*`MRF_DWIDTH-1:16*`MRF_DWIDTH]; + end + `MRF_17: begin + output_data_to_dram <= mrf_outa_to_dram[18*`MRF_DWIDTH-1:17*`MRF_DWIDTH]; + end + `MRF_18: begin + output_data_to_dram <= mrf_outa_to_dram[19*`MRF_DWIDTH-1:18*`MRF_DWIDTH]; + end + `MRF_19: begin + output_data_to_dram <= mrf_outa_to_dram[20*`MRF_DWIDTH-1:19*`MRF_DWIDTH]; + end + `MRF_20: begin + output_data_to_dram <= mrf_outa_to_dram[21*`MRF_DWIDTH-1:20*`MRF_DWIDTH]; + end + `MRF_21: begin + output_data_to_dram <= mrf_outa_to_dram[22*`MRF_DWIDTH-1:21*`MRF_DWIDTH]; + end + `MRF_22: begin + output_data_to_dram <= mrf_outa_to_dram[23*`MRF_DWIDTH-1:22*`MRF_DWIDTH]; + end + `MRF_23: begin + output_data_to_dram <= mrf_outa_to_dram[24*`MRF_DWIDTH-1:23*`MRF_DWIDTH]; + end + `MRF_24: begin + output_data_to_dram <= mrf_outa_to_dram[25*`MRF_DWIDTH-1:24*`MRF_DWIDTH]; + end + `MRF_25: begin + output_data_to_dram <= mrf_outa_to_dram[26*`MRF_DWIDTH-1:25*`MRF_DWIDTH]; + end + `MRF_26: begin + output_data_to_dram <= mrf_outa_to_dram[27*`MRF_DWIDTH-1:26*`MRF_DWIDTH]; + end + `MRF_27: begin + output_data_to_dram <= mrf_outa_to_dram[28*`MRF_DWIDTH-1:27*`MRF_DWIDTH]; + end + `MRF_28: begin + output_data_to_dram <= mrf_outa_to_dram[29*`MRF_DWIDTH-1:28*`MRF_DWIDTH]; + end + `MRF_29: begin + output_data_to_dram <= mrf_outa_to_dram[30*`MRF_DWIDTH-1:29*`MRF_DWIDTH]; + end + `MRF_30: begin + output_data_to_dram <= mrf_outa_to_dram[31*`MRF_DWIDTH-1:30*`MRF_DWIDTH]; + end + `MRF_31: begin + output_data_to_dram <= mrf_outa_to_dram[32*`MRF_DWIDTH-1:31*`MRF_DWIDTH]; + end + `MRF_32: begin + output_data_to_dram <= mrf_outa_to_dram[33*`MRF_DWIDTH-1:32*`MRF_DWIDTH]; + end + `MRF_33: begin + output_data_to_dram <= mrf_outa_to_dram[34*`MRF_DWIDTH-1:33*`MRF_DWIDTH]; + end + `MRF_34: begin + output_data_to_dram <= mrf_outa_to_dram[35*`MRF_DWIDTH-1:34*`MRF_DWIDTH]; + end + `MRF_35: begin + output_data_to_dram <= mrf_outa_to_dram[36*`MRF_DWIDTH-1:35*`MRF_DWIDTH]; + end + `MRF_36: begin + output_data_to_dram <= mrf_outa_to_dram[37*`MRF_DWIDTH-1:36*`MRF_DWIDTH]; + end + `MRF_37: begin + output_data_to_dram <= mrf_outa_to_dram[38*`MRF_DWIDTH-1:37*`MRF_DWIDTH]; + end + `MRF_38: begin + output_data_to_dram <= mrf_outa_to_dram[39*`MRF_DWIDTH-1:38*`MRF_DWIDTH]; + end + `MRF_39: begin + output_data_to_dram <= mrf_outa_to_dram[40*`MRF_DWIDTH-1:39*`MRF_DWIDTH]; + end + `MRF_40: begin + output_data_to_dram <= mrf_outa_to_dram[41*`MRF_DWIDTH-1:40*`MRF_DWIDTH]; + end + `MRF_41: begin + output_data_to_dram <= mrf_outa_to_dram[42*`MRF_DWIDTH-1:41*`MRF_DWIDTH]; + end + `MRF_42: begin + output_data_to_dram <= mrf_outa_to_dram[43*`MRF_DWIDTH-1:42*`MRF_DWIDTH]; + end + `MRF_43: begin + output_data_to_dram <= mrf_outa_to_dram[44*`MRF_DWIDTH-1:43*`MRF_DWIDTH]; + end + `MRF_44: begin + output_data_to_dram <= mrf_outa_to_dram[45*`MRF_DWIDTH-1:44*`MRF_DWIDTH]; + end + `MRF_45: begin + output_data_to_dram <= mrf_outa_to_dram[46*`MRF_DWIDTH-1:45*`MRF_DWIDTH]; + end + `MRF_46: begin + output_data_to_dram <= mrf_outa_to_dram[47*`MRF_DWIDTH-1:46*`MRF_DWIDTH]; + end + `MRF_47: begin + output_data_to_dram <= mrf_outa_to_dram[48*`MRF_DWIDTH-1:47*`MRF_DWIDTH]; + end + `MRF_48: begin + output_data_to_dram <= mrf_outa_to_dram[49*`MRF_DWIDTH-1:48*`MRF_DWIDTH]; + end + `MRF_49: begin + output_data_to_dram <= mrf_outa_to_dram[50*`MRF_DWIDTH-1:49*`MRF_DWIDTH]; + end + `MRF_50: begin + output_data_to_dram <= mrf_outa_to_dram[51*`MRF_DWIDTH-1:50*`MRF_DWIDTH]; + end + `MRF_51: begin + output_data_to_dram <= mrf_outa_to_dram[52*`MRF_DWIDTH-1:51*`MRF_DWIDTH]; + end + `MRF_52: begin + output_data_to_dram <= mrf_outa_to_dram[53*`MRF_DWIDTH-1:52*`MRF_DWIDTH]; + end + `MRF_53: begin + output_data_to_dram <= mrf_outa_to_dram[54*`MRF_DWIDTH-1:53*`MRF_DWIDTH]; + end + `MRF_54: begin + output_data_to_dram <= mrf_outa_to_dram[55*`MRF_DWIDTH-1:54*`MRF_DWIDTH]; + end + `MRF_55: begin + output_data_to_dram <= mrf_outa_to_dram[56*`MRF_DWIDTH-1:55*`MRF_DWIDTH]; + end + `MRF_56: begin + output_data_to_dram <= mrf_outa_to_dram[57*`MRF_DWIDTH-1:56*`MRF_DWIDTH]; + end + `MRF_57: begin + output_data_to_dram <= mrf_outa_to_dram[58*`MRF_DWIDTH-1:57*`MRF_DWIDTH]; + end + `MRF_58: begin + output_data_to_dram <= mrf_outa_to_dram[59*`MRF_DWIDTH-1:58*`MRF_DWIDTH]; + end + `MRF_59: begin + output_data_to_dram <= mrf_outa_to_dram[60*`MRF_DWIDTH-1:59*`MRF_DWIDTH]; + end + `MRF_60: begin + output_data_to_dram <= mrf_outa_to_dram[61*`MRF_DWIDTH-1:60*`MRF_DWIDTH]; + end + `MRF_61: begin + output_data_to_dram <= mrf_outa_to_dram[62*`MRF_DWIDTH-1:61*`MRF_DWIDTH]; + end + `MRF_62: begin + output_data_to_dram <= mrf_outa_to_dram[63*`MRF_DWIDTH-1:62*`MRF_DWIDTH]; + end + `MRF_63: begin + output_data_to_dram <= mrf_outa_to_dram[64*`MRF_DWIDTH-1:63*`MRF_DWIDTH]; + end + default: begin + output_data_to_dram <= 'd0; + end + endcase + + end + `V_RD: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + vrf_in_data <= input_data_from_dram; + case(dstn_id) + `VRF_0: begin + vrf_wr_enable_mvu_0 <= 1'b1; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_1: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b1; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_2: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b1; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_3: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b1; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_4: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b1; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_5: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b1; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_6: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b1; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_7: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b1; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_8: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b1; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_9: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b1; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_10: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b1; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_11: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b1; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_12: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b1; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_13: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b1; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_14: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b1; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_15: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b1; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr <= dstn_address; + end + `VRF_16: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b1; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_add_0 <= dstn_address; + + end + + `VRF_17: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b1; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_mul_0 <= dstn_address; + + end + + `VRF_18: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b1; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_add_1 <= dstn_address; + end + + `VRF_19: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b1; + vrf_muxed_wr_enable_dram <= 1'b0; + + vrf_addr_wr_mfu_mul_1 <= dstn_address; + end + + `VRF_MUXED: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b1; + + + vrf_muxed_wr_addr_dram <= dstn_address; + end + + default: begin + vrf_wr_enable_mvu_0 <= 1'bX; + vrf_wr_enable_mvu_1 <= 1'bX; + vrf_wr_enable_mvu_2 <= 1'bX; + vrf_wr_enable_mvu_3 <= 1'bX; + vrf_wr_enable_mvu_4 <= 1'bX; + vrf_wr_enable_mvu_5 <= 1'bX; + vrf_wr_enable_mvu_6 <= 1'bX; + vrf_wr_enable_mvu_7 <= 1'bX; + vrf_wr_enable_mvu_8 <= 1'bX; + vrf_wr_enable_mvu_9 <= 1'bX; + vrf_wr_enable_mvu_10 <= 1'bX; + vrf_wr_enable_mvu_11 <= 1'bX; + vrf_wr_enable_mvu_12 <= 1'bX; + vrf_wr_enable_mvu_13 <= 1'bX; + vrf_wr_enable_mvu_14 <= 1'bX; + vrf_wr_enable_mvu_15 <= 1'bX; + vrf_wr_enable_mfu_add_0 <= 1'bX; + vrf_wr_enable_mfu_mul_0 <= 1'bX; + vrf_wr_enable_mfu_add_1 <= 1'bX; + vrf_wr_enable_mfu_mul_1 <= 1'bX; + vrf_muxed_wr_enable_dram <= 1'bX; + + end + endcase +/* + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; +*/ + + end + `M_RD: begin + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(dstn_id) + `MRF_0: begin + mrf_we_for_dram[0] <= 1; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[1*`MRF_DWIDTH-1:0*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[1*`MRF_AWIDTH-1:0*`MRF_AWIDTH] <= dstn_address; + end + `MRF_1: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 1; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[2*`MRF_DWIDTH-1:1*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[2*`MRF_AWIDTH-1:1*`MRF_AWIDTH] <= dstn_address; + end + `MRF_2: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 1; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[3*`MRF_DWIDTH-1:2*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[3*`MRF_AWIDTH-1:2*`MRF_AWIDTH] <= dstn_address; + end + `MRF_3: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 1; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[4*`MRF_DWIDTH-1:3*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[4*`MRF_AWIDTH-1:3*`MRF_AWIDTH] <= dstn_address; + end + `MRF_4: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 1; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[5*`MRF_DWIDTH-1:4*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[5*`MRF_AWIDTH-1:4*`MRF_AWIDTH] <= dstn_address; + end + `MRF_5: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 1; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[6*`MRF_DWIDTH-1:5*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[6*`MRF_AWIDTH-1:5*`MRF_AWIDTH] <= dstn_address; + end + `MRF_6: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 1; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[7*`MRF_DWIDTH-1:6*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[7*`MRF_AWIDTH-1:6*`MRF_AWIDTH] <= dstn_address; + end + `MRF_7: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 1; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[8*`MRF_DWIDTH-1:7*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[8*`MRF_AWIDTH-1:7*`MRF_AWIDTH] <= dstn_address; + end + `MRF_8: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 1; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[9*`MRF_DWIDTH-1:8*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[9*`MRF_AWIDTH-1:8*`MRF_AWIDTH] <= dstn_address; + end + `MRF_9: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 1; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[10*`MRF_DWIDTH-1:9*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[10*`MRF_AWIDTH-1:9*`MRF_AWIDTH] <= dstn_address; + end + `MRF_10: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 1; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[11*`MRF_DWIDTH-1:10*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[11*`MRF_AWIDTH-1:10*`MRF_AWIDTH] <= dstn_address; + end + `MRF_11: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 1; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[12*`MRF_DWIDTH-1:11*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[12*`MRF_AWIDTH-1:11*`MRF_AWIDTH] <= dstn_address; + end + `MRF_12: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 1; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[13*`MRF_DWIDTH-1:12*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[13*`MRF_AWIDTH-1:12*`MRF_AWIDTH] <= dstn_address; + end + `MRF_13: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 1; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[14*`MRF_DWIDTH-1:13*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[14*`MRF_AWIDTH-1:13*`MRF_AWIDTH] <= dstn_address; + end + `MRF_14: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 1; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[15*`MRF_DWIDTH-1:14*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[15*`MRF_AWIDTH-1:14*`MRF_AWIDTH] <= dstn_address; + end + `MRF_15: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 1; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[16*`MRF_DWIDTH-1:15*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[16*`MRF_AWIDTH-1:15*`MRF_AWIDTH] <= dstn_address; + end + `MRF_16: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 1; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[17*`MRF_DWIDTH-1:16*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[17*`MRF_AWIDTH-1:16*`MRF_AWIDTH] <= dstn_address; + end + `MRF_17: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 1; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[18*`MRF_DWIDTH-1:17*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[18*`MRF_AWIDTH-1:17*`MRF_AWIDTH] <= dstn_address; + end + `MRF_18: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 1; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[19*`MRF_DWIDTH-1:18*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[19*`MRF_AWIDTH-1:18*`MRF_AWIDTH] <= dstn_address; + end + `MRF_19: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 1; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[20*`MRF_DWIDTH-1:19*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[20*`MRF_AWIDTH-1:19*`MRF_AWIDTH] <= dstn_address; + end + `MRF_20: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 1; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[21*`MRF_DWIDTH-1:20*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[21*`MRF_AWIDTH-1:20*`MRF_AWIDTH] <= dstn_address; + end + `MRF_21: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 1; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[22*`MRF_DWIDTH-1:21*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[22*`MRF_AWIDTH-1:21*`MRF_AWIDTH] <= dstn_address; + end + `MRF_22: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 1; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[23*`MRF_DWIDTH-1:22*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[23*`MRF_AWIDTH-1:22*`MRF_AWIDTH] <= dstn_address; + end + `MRF_23: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 1; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[24*`MRF_DWIDTH-1:23*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[24*`MRF_AWIDTH-1:23*`MRF_AWIDTH] <= dstn_address; + end + `MRF_24: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 1; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[25*`MRF_DWIDTH-1:24*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[25*`MRF_AWIDTH-1:24*`MRF_AWIDTH] <= dstn_address; + end + `MRF_25: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 1; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[26*`MRF_DWIDTH-1:25*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[26*`MRF_AWIDTH-1:25*`MRF_AWIDTH] <= dstn_address; + end + `MRF_26: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 1; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[27*`MRF_DWIDTH-1:26*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[27*`MRF_AWIDTH-1:26*`MRF_AWIDTH] <= dstn_address; + end + `MRF_27: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 1; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[28*`MRF_DWIDTH-1:27*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[28*`MRF_AWIDTH-1:27*`MRF_AWIDTH] <= dstn_address; + end + `MRF_28: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 1; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[29*`MRF_DWIDTH-1:28*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[29*`MRF_AWIDTH-1:28*`MRF_AWIDTH] <= dstn_address; + end + `MRF_29: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 1; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[30*`MRF_DWIDTH-1:29*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[30*`MRF_AWIDTH-1:29*`MRF_AWIDTH] <= dstn_address; + end + `MRF_30: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 1; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[31*`MRF_DWIDTH-1:30*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[31*`MRF_AWIDTH-1:30*`MRF_AWIDTH] <= dstn_address; + end + `MRF_31: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 1; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[32*`MRF_DWIDTH-1:31*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[32*`MRF_AWIDTH-1:31*`MRF_AWIDTH] <= dstn_address; + end + `MRF_32: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 1; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[33*`MRF_DWIDTH-1:32*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[33*`MRF_AWIDTH-1:32*`MRF_AWIDTH] <= dstn_address; + end + `MRF_33: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 1; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[34*`MRF_DWIDTH-1:33*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[34*`MRF_AWIDTH-1:33*`MRF_AWIDTH] <= dstn_address; + end + `MRF_34: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 1; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[35*`MRF_DWIDTH-1:34*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[35*`MRF_AWIDTH-1:34*`MRF_AWIDTH] <= dstn_address; + end + `MRF_35: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 1; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[36*`MRF_DWIDTH-1:35*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[36*`MRF_AWIDTH-1:35*`MRF_AWIDTH] <= dstn_address; + end + `MRF_36: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 1; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[37*`MRF_DWIDTH-1:36*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[37*`MRF_AWIDTH-1:36*`MRF_AWIDTH] <= dstn_address; + end + `MRF_37: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 1; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[38*`MRF_DWIDTH-1:37*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[38*`MRF_AWIDTH-1:37*`MRF_AWIDTH] <= dstn_address; + end + `MRF_38: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 1; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[39*`MRF_DWIDTH-1:38*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[39*`MRF_AWIDTH-1:38*`MRF_AWIDTH] <= dstn_address; + end + `MRF_39: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 1; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[40*`MRF_DWIDTH-1:39*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[40*`MRF_AWIDTH-1:39*`MRF_AWIDTH] <= dstn_address; + end + `MRF_40: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 1; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[41*`MRF_DWIDTH-1:40*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[41*`MRF_AWIDTH-1:40*`MRF_AWIDTH] <= dstn_address; + end + `MRF_41: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 1; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[42*`MRF_DWIDTH-1:41*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[42*`MRF_AWIDTH-1:41*`MRF_AWIDTH] <= dstn_address; + end + `MRF_42: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 1; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[43*`MRF_DWIDTH-1:42*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[43*`MRF_AWIDTH-1:42*`MRF_AWIDTH] <= dstn_address; + end + `MRF_43: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 1; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[44*`MRF_DWIDTH-1:43*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[44*`MRF_AWIDTH-1:43*`MRF_AWIDTH] <= dstn_address; + end + `MRF_44: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 1; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[45*`MRF_DWIDTH-1:44*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[45*`MRF_AWIDTH-1:44*`MRF_AWIDTH] <= dstn_address; + end + `MRF_45: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 1; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[46*`MRF_DWIDTH-1:45*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[46*`MRF_AWIDTH-1:45*`MRF_AWIDTH] <= dstn_address; + end + `MRF_46: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 1; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[47*`MRF_DWIDTH-1:46*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[47*`MRF_AWIDTH-1:46*`MRF_AWIDTH] <= dstn_address; + end + `MRF_47: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 1; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[48*`MRF_DWIDTH-1:47*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[48*`MRF_AWIDTH-1:47*`MRF_AWIDTH] <= dstn_address; + end + `MRF_48: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 1; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[49*`MRF_DWIDTH-1:48*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[49*`MRF_AWIDTH-1:48*`MRF_AWIDTH] <= dstn_address; + end + `MRF_49: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 1; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[50*`MRF_DWIDTH-1:49*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[50*`MRF_AWIDTH-1:49*`MRF_AWIDTH] <= dstn_address; + end + `MRF_50: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 1; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[51*`MRF_DWIDTH-1:50*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[51*`MRF_AWIDTH-1:50*`MRF_AWIDTH] <= dstn_address; + end + `MRF_51: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 1; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[52*`MRF_DWIDTH-1:51*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[52*`MRF_AWIDTH-1:51*`MRF_AWIDTH] <= dstn_address; + end + `MRF_52: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 1; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[53*`MRF_DWIDTH-1:52*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[53*`MRF_AWIDTH-1:52*`MRF_AWIDTH] <= dstn_address; + end + `MRF_53: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 1; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[54*`MRF_DWIDTH-1:53*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[54*`MRF_AWIDTH-1:53*`MRF_AWIDTH] <= dstn_address; + end + `MRF_54: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 1; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[55*`MRF_DWIDTH-1:54*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[55*`MRF_AWIDTH-1:54*`MRF_AWIDTH] <= dstn_address; + end + `MRF_55: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 1; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[56*`MRF_DWIDTH-1:55*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[56*`MRF_AWIDTH-1:55*`MRF_AWIDTH] <= dstn_address; + end + `MRF_56: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 1; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[57*`MRF_DWIDTH-1:56*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[57*`MRF_AWIDTH-1:56*`MRF_AWIDTH] <= dstn_address; + end + `MRF_57: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 1; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[58*`MRF_DWIDTH-1:57*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[58*`MRF_AWIDTH-1:57*`MRF_AWIDTH] <= dstn_address; + end + `MRF_58: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 1; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[59*`MRF_DWIDTH-1:58*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[59*`MRF_AWIDTH-1:58*`MRF_AWIDTH] <= dstn_address; + end + `MRF_59: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 1; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[60*`MRF_DWIDTH-1:59*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[60*`MRF_AWIDTH-1:59*`MRF_AWIDTH] <= dstn_address; + end + `MRF_60: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 1; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[61*`MRF_DWIDTH-1:60*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[61*`MRF_AWIDTH-1:60*`MRF_AWIDTH] <= dstn_address; + end + `MRF_61: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 1; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 0; + mrf_in_data[62*`MRF_DWIDTH-1:61*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[62*`MRF_AWIDTH-1:61*`MRF_AWIDTH] <= dstn_address; + end + `MRF_62: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 1; + mrf_we_for_dram[63] <= 0; + mrf_in_data[63*`MRF_DWIDTH-1:62*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[63*`MRF_AWIDTH-1:62*`MRF_AWIDTH] <= dstn_address; + end + `MRF_63: begin + mrf_we_for_dram[0] <= 0; + mrf_we_for_dram[1] <= 0; + mrf_we_for_dram[2] <= 0; + mrf_we_for_dram[3] <= 0; + mrf_we_for_dram[4] <= 0; + mrf_we_for_dram[5] <= 0; + mrf_we_for_dram[6] <= 0; + mrf_we_for_dram[7] <= 0; + mrf_we_for_dram[8] <= 0; + mrf_we_for_dram[9] <= 0; + mrf_we_for_dram[10] <= 0; + mrf_we_for_dram[11] <= 0; + mrf_we_for_dram[12] <= 0; + mrf_we_for_dram[13] <= 0; + mrf_we_for_dram[14] <= 0; + mrf_we_for_dram[15] <= 0; + mrf_we_for_dram[16] <= 0; + mrf_we_for_dram[17] <= 0; + mrf_we_for_dram[18] <= 0; + mrf_we_for_dram[19] <= 0; + mrf_we_for_dram[20] <= 0; + mrf_we_for_dram[21] <= 0; + mrf_we_for_dram[22] <= 0; + mrf_we_for_dram[23] <= 0; + mrf_we_for_dram[24] <= 0; + mrf_we_for_dram[25] <= 0; + mrf_we_for_dram[26] <= 0; + mrf_we_for_dram[27] <= 0; + mrf_we_for_dram[28] <= 0; + mrf_we_for_dram[29] <= 0; + mrf_we_for_dram[30] <= 0; + mrf_we_for_dram[31] <= 0; + mrf_we_for_dram[32] <= 0; + mrf_we_for_dram[33] <= 0; + mrf_we_for_dram[34] <= 0; + mrf_we_for_dram[35] <= 0; + mrf_we_for_dram[36] <= 0; + mrf_we_for_dram[37] <= 0; + mrf_we_for_dram[38] <= 0; + mrf_we_for_dram[39] <= 0; + mrf_we_for_dram[40] <= 0; + mrf_we_for_dram[41] <= 0; + mrf_we_for_dram[42] <= 0; + mrf_we_for_dram[43] <= 0; + mrf_we_for_dram[44] <= 0; + mrf_we_for_dram[45] <= 0; + mrf_we_for_dram[46] <= 0; + mrf_we_for_dram[47] <= 0; + mrf_we_for_dram[48] <= 0; + mrf_we_for_dram[49] <= 0; + mrf_we_for_dram[50] <= 0; + mrf_we_for_dram[51] <= 0; + mrf_we_for_dram[52] <= 0; + mrf_we_for_dram[53] <= 0; + mrf_we_for_dram[54] <= 0; + mrf_we_for_dram[55] <= 0; + mrf_we_for_dram[56] <= 0; + mrf_we_for_dram[57] <= 0; + mrf_we_for_dram[58] <= 0; + mrf_we_for_dram[59] <= 0; + mrf_we_for_dram[60] <= 0; + mrf_we_for_dram[61] <= 0; + mrf_we_for_dram[62] <= 0; + mrf_we_for_dram[63] <= 1; + mrf_in_data[64*`MRF_DWIDTH-1:63*`MRF_DWIDTH] <= input_data_from_dram; + mrf_addr_for_dram[64*`MRF_AWIDTH-1:63*`MRF_AWIDTH] <= dstn_address; + end + + default: begin + mrf_we_for_dram[0] <= 1'bX; + mrf_we_for_dram[1] <= 1'bX; + mrf_we_for_dram[2] <= 1'bX; + mrf_we_for_dram[3] <= 1'bX; + mrf_we_for_dram[4] <= 1'bX; + mrf_we_for_dram[5] <= 1'bX; + mrf_we_for_dram[6] <= 1'bX; + mrf_we_for_dram[7] <= 1'bX; + mrf_we_for_dram[8] <= 1'bX; + mrf_we_for_dram[9] <= 1'bX; + mrf_we_for_dram[10] <= 1'bX; + mrf_we_for_dram[11] <= 1'bX; + mrf_we_for_dram[12] <= 1'bX; + mrf_we_for_dram[13] <= 1'bX; + mrf_we_for_dram[14] <= 1'bX; + mrf_we_for_dram[15] <= 1'bX; + mrf_we_for_dram[16] <= 1'bX; + mrf_we_for_dram[17] <= 1'bX; + mrf_we_for_dram[18] <= 1'bX; + mrf_we_for_dram[19] <= 1'bX; + mrf_we_for_dram[20] <= 1'bX; + mrf_we_for_dram[21] <= 1'bX; + mrf_we_for_dram[22] <= 1'bX; + mrf_we_for_dram[23] <= 1'bX; + mrf_we_for_dram[24] <= 1'bX; + mrf_we_for_dram[25] <= 1'bX; + mrf_we_for_dram[26] <= 1'bX; + mrf_we_for_dram[27] <= 1'bX; + mrf_we_for_dram[28] <= 1'bX; + mrf_we_for_dram[29] <= 1'bX; + mrf_we_for_dram[30] <= 1'bX; + mrf_we_for_dram[31] <= 1'bX; + mrf_we_for_dram[32] <= 1'bX; + mrf_we_for_dram[33] <= 1'bX; + mrf_we_for_dram[34] <= 1'bX; + mrf_we_for_dram[35] <= 1'bX; + mrf_we_for_dram[36] <= 1'bX; + mrf_we_for_dram[37] <= 1'bX; + mrf_we_for_dram[38] <= 1'bX; + mrf_we_for_dram[39] <= 1'bX; + mrf_we_for_dram[40] <= 1'bX; + mrf_we_for_dram[41] <= 1'bX; + mrf_we_for_dram[42] <= 1'bX; + mrf_we_for_dram[43] <= 1'bX; + mrf_we_for_dram[44] <= 1'bX; + mrf_we_for_dram[45] <= 1'bX; + mrf_we_for_dram[46] <= 1'bX; + mrf_we_for_dram[47] <= 1'bX; + mrf_we_for_dram[48] <= 1'bX; + mrf_we_for_dram[49] <= 1'bX; + mrf_we_for_dram[50] <= 1'bX; + mrf_we_for_dram[51] <= 1'bX; + mrf_we_for_dram[52] <= 1'bX; + mrf_we_for_dram[53] <= 1'bX; + mrf_we_for_dram[54] <= 1'bX; + mrf_we_for_dram[55] <= 1'bX; + mrf_we_for_dram[56] <= 1'bX; + mrf_we_for_dram[57] <= 1'bX; + mrf_we_for_dram[58] <= 1'bX; + mrf_we_for_dram[59] <= 1'bX; + mrf_we_for_dram[60] <= 1'bX; + mrf_we_for_dram[61] <= 1'bX; + mrf_we_for_dram[62] <= 1'bX; + mrf_we_for_dram[63] <= 1'bX; + end + + endcase + end + default: begin + + if(done_mvm || done_mfu_0 || done_mfu_1) begin + start_mv_mul <= 0; + start_mfu_0 <= 0; + start_mfu_1 <= 0; + state <= 0; + get_instr<=1'b1; + get_instr_addr<=get_instr_addr+1'b1; + + case(dstn_id) + `VRF_0: begin + vrf_wr_enable_mvu_0 <= 1'b1; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_1: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b1; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_2: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b1; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_3: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b1; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_4: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b1; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_5: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b1; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_6: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b1; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_7: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b1; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_8: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b1; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_9: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b1; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_10: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b1; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_11: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b1; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_12: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b1; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_13: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b1; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_14: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b1; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + `VRF_15: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b1; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + vrf_in_data <= output_final_stage; + vrf_addr_wr<=dstn_address; + //vrf_addr_wr_mvu_0 <= dstn_address; + end + + `VRF_16: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b1; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_add_0 <= dstn_address; + + end + + `VRF_17: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b1; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_mul_0 <= dstn_address; + + end + + `VRF_18: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b1; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_add_1 <= dstn_address; + end + + `VRF_19: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b1; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_addr_wr_mfu_mul_1 <= dstn_address; + end + + `VRF_MUXED: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b1; + dram_write_enable<=1'b0; + + vrf_in_data <= output_final_stage; + + vrf_muxed_wr_addr_dram <= dstn_address; + end + + `DRAM_MEM_ID: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b1; + + output_data_to_dram <= output_final_stage; + + dram_addr_wr <= dstn_address; + end + + //MFU_OUT_STAGE IDS USED FOR MUXING + + default: begin + vrf_wr_enable_mvu_0 <= 1'b0; + vrf_wr_enable_mvu_1 <= 1'b0; + vrf_wr_enable_mvu_2 <= 1'b0; + vrf_wr_enable_mvu_3 <= 1'b0; + vrf_wr_enable_mvu_4 <= 1'b0; + vrf_wr_enable_mvu_5 <= 1'b0; + vrf_wr_enable_mvu_6 <= 1'b0; + vrf_wr_enable_mvu_7 <= 1'b0; + vrf_wr_enable_mvu_8 <= 1'b0; + vrf_wr_enable_mvu_9 <= 1'b0; + vrf_wr_enable_mvu_10 <= 1'b0; + vrf_wr_enable_mvu_11 <= 1'b0; + vrf_wr_enable_mvu_12 <= 1'b0; + vrf_wr_enable_mvu_13 <= 1'b0; + vrf_wr_enable_mvu_14 <= 1'b0; + vrf_wr_enable_mvu_15 <= 1'b0; + vrf_wr_enable_mfu_add_0 <= 1'b0; + vrf_wr_enable_mfu_mul_0 <= 1'b0; + vrf_wr_enable_mfu_add_1 <= 1'b0; + vrf_wr_enable_mfu_mul_1 <= 1'b0; + vrf_muxed_wr_enable_dram <= 1'b0; + dram_write_enable<=1'b0; + end + endcase + end + end + endcase + end + end + end +endmodule +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM mvu.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + + +//`include "includes_gen.v" + +module MVU ( + input clk, + input[`NUM_LDPES-1:0] start, + input[`NUM_LDPES-1:0] reset, + input [`VRF_AWIDTH-1:0] vrf_wr_addr, + input [`VRF_AWIDTH-1:0] vrf_read_addr, + input [`VRF_DWIDTH-1:0] vec, + + input vrf_wr_enable_tile_0, + input vrf_readn_enable_tile_0, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_0, + input vrf_wr_enable_tile_1, + input vrf_readn_enable_tile_1, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_1, + input vrf_wr_enable_tile_2, + input vrf_readn_enable_tile_2, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_2, + input vrf_wr_enable_tile_3, + input vrf_readn_enable_tile_3, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_3, + input vrf_wr_enable_tile_4, + input vrf_readn_enable_tile_4, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_4, + input vrf_wr_enable_tile_5, + input vrf_readn_enable_tile_5, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_5, + input vrf_wr_enable_tile_6, + input vrf_readn_enable_tile_6, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_6, + input vrf_wr_enable_tile_7, + input vrf_readn_enable_tile_7, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_7, + input vrf_wr_enable_tile_8, + input vrf_readn_enable_tile_8, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_8, + input vrf_wr_enable_tile_9, + input vrf_readn_enable_tile_9, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_9, + input vrf_wr_enable_tile_10, + input vrf_readn_enable_tile_10, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_10, + input vrf_wr_enable_tile_11, + input vrf_readn_enable_tile_11, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_11, + input vrf_wr_enable_tile_12, + input vrf_readn_enable_tile_12, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_12, + input vrf_wr_enable_tile_13, + input vrf_readn_enable_tile_13, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_13, + input vrf_wr_enable_tile_14, + input vrf_readn_enable_tile_14, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_14, + input vrf_wr_enable_tile_15, + input vrf_readn_enable_tile_15, + output[`VRF_DWIDTH-1:0] vrf_data_out_tile_15, + + input [`MRF_DWIDTH*`NUM_LDPES*`NUM_TILES-1:0] mrf_in, + input[`NUM_TILES*`NUM_LDPES-1:0] mrf_we, + input [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr, + + input[`NUM_TILES*`NUM_LDPES-1:0] mrf_we_for_dram, + input [`NUM_TILES*`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram, + output [`NUM_TILES*`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram, + + output [`ORF_DWIDTH-1:0] mvm_result, + output out_data_available +); + + + wire[`NUM_LDPES-1:0] start_external_comparator_tree; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_final; + + wire[`NUM_LDPES-1:0] out_data_available_comparator_tile; + + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_0; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_0; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_0; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_0; + + MVU_tile tile_0(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_0), + .vrf_data_out(vrf_data_out_tile_0), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_0), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_0), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_0), + .out_data_available(out_data_available_mvm_tile_0), + .mrf_in(mrf_in[1*`MRF_DWIDTH*`NUM_LDPES-1:0*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[1*`NUM_LDPES-1:0*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[1*`NUM_LDPES*`MRF_AWIDTH-1:0*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[1*`NUM_LDPES*`MRF_AWIDTH-1:0*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[1*`NUM_LDPES*`MRF_DWIDTH-1:0*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[1*`NUM_LDPES-1:0*`NUM_LDPES]), + .result(result_mvm_0) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_1; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_1; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_1; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_1; + + MVU_tile tile_1(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_1), + .vrf_data_out(vrf_data_out_tile_1), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_1), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_1), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_1), + .out_data_available(out_data_available_mvm_tile_1), + .mrf_in(mrf_in[2*`MRF_DWIDTH*`NUM_LDPES-1:1*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[2*`NUM_LDPES-1:1*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[2*`NUM_LDPES*`MRF_AWIDTH-1:1*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[2*`NUM_LDPES*`MRF_AWIDTH-1:1*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[2*`NUM_LDPES*`MRF_DWIDTH-1:1*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[2*`NUM_LDPES-1:1*`NUM_LDPES]), + .result(result_mvm_1) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_2; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_2; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_2; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_2; + + MVU_tile tile_2(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_2), + .vrf_data_out(vrf_data_out_tile_2), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_2), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_2), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_2), + .out_data_available(out_data_available_mvm_tile_2), + .mrf_in(mrf_in[3*`MRF_DWIDTH*`NUM_LDPES-1:2*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[3*`NUM_LDPES-1:2*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[3*`NUM_LDPES*`MRF_AWIDTH-1:2*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[3*`NUM_LDPES*`MRF_AWIDTH-1:2*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[3*`NUM_LDPES*`MRF_DWIDTH-1:2*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[3*`NUM_LDPES-1:2*`NUM_LDPES]), + .result(result_mvm_2) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_3; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_3; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_3; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_3; + + MVU_tile tile_3(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_3), + .vrf_data_out(vrf_data_out_tile_3), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_3), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_3), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_3), + .out_data_available(out_data_available_mvm_tile_3), + .mrf_in(mrf_in[4*`MRF_DWIDTH*`NUM_LDPES-1:3*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[4*`NUM_LDPES-1:3*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[4*`NUM_LDPES*`MRF_AWIDTH-1:3*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[4*`NUM_LDPES*`MRF_AWIDTH-1:3*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[4*`NUM_LDPES*`MRF_DWIDTH-1:3*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[4*`NUM_LDPES-1:3*`NUM_LDPES]), + .result(result_mvm_3) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_4; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_4; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_4; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_4; + + MVU_tile tile_4(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_4), + .vrf_data_out(vrf_data_out_tile_4), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_4), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_4), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_4), + .out_data_available(out_data_available_mvm_tile_4), + .mrf_in(mrf_in[5*`MRF_DWIDTH*`NUM_LDPES-1:4*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[5*`NUM_LDPES-1:4*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[5*`NUM_LDPES*`MRF_AWIDTH-1:4*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[5*`NUM_LDPES*`MRF_AWIDTH-1:4*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[5*`NUM_LDPES*`MRF_DWIDTH-1:4*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[5*`NUM_LDPES-1:4*`NUM_LDPES]), + .result(result_mvm_4) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_5; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_5; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_5; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_5; + + MVU_tile tile_5(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_5), + .vrf_data_out(vrf_data_out_tile_5), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_5), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_5), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_5), + .out_data_available(out_data_available_mvm_tile_5), + .mrf_in(mrf_in[6*`MRF_DWIDTH*`NUM_LDPES-1:5*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[6*`NUM_LDPES-1:5*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[6*`NUM_LDPES*`MRF_AWIDTH-1:5*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[6*`NUM_LDPES*`MRF_AWIDTH-1:5*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[6*`NUM_LDPES*`MRF_DWIDTH-1:5*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[6*`NUM_LDPES-1:5*`NUM_LDPES]), + .result(result_mvm_5) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_6; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_6; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_6; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_6; + + MVU_tile tile_6(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_6), + .vrf_data_out(vrf_data_out_tile_6), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_6), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_6), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_6), + .out_data_available(out_data_available_mvm_tile_6), + .mrf_in(mrf_in[7*`MRF_DWIDTH*`NUM_LDPES-1:6*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[7*`NUM_LDPES-1:6*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[7*`NUM_LDPES*`MRF_AWIDTH-1:6*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[7*`NUM_LDPES*`MRF_AWIDTH-1:6*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[7*`NUM_LDPES*`MRF_DWIDTH-1:6*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[7*`NUM_LDPES-1:6*`NUM_LDPES]), + .result(result_mvm_6) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_7; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_7; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_7; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_7; + + MVU_tile tile_7(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_7), + .vrf_data_out(vrf_data_out_tile_7), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_7), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_7), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_7), + .out_data_available(out_data_available_mvm_tile_7), + .mrf_in(mrf_in[8*`MRF_DWIDTH*`NUM_LDPES-1:7*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[8*`NUM_LDPES-1:7*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[8*`NUM_LDPES*`MRF_AWIDTH-1:7*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[8*`NUM_LDPES*`MRF_AWIDTH-1:7*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[8*`NUM_LDPES*`MRF_DWIDTH-1:7*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[8*`NUM_LDPES-1:7*`NUM_LDPES]), + .result(result_mvm_7) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_8; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_8; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_8; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_8; + + MVU_tile tile_8(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_8), + .vrf_data_out(vrf_data_out_tile_8), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_8), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_8), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_8), + .out_data_available(out_data_available_mvm_tile_8), + .mrf_in(mrf_in[9*`MRF_DWIDTH*`NUM_LDPES-1:8*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[9*`NUM_LDPES-1:8*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[9*`NUM_LDPES*`MRF_AWIDTH-1:8*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[9*`NUM_LDPES*`MRF_AWIDTH-1:8*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[9*`NUM_LDPES*`MRF_DWIDTH-1:8*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[9*`NUM_LDPES-1:8*`NUM_LDPES]), + .result(result_mvm_8) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_9; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_9; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_9; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_9; + + MVU_tile tile_9(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_9), + .vrf_data_out(vrf_data_out_tile_9), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_9), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_9), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_9), + .out_data_available(out_data_available_mvm_tile_9), + .mrf_in(mrf_in[10*`MRF_DWIDTH*`NUM_LDPES-1:9*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[10*`NUM_LDPES-1:9*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[10*`NUM_LDPES*`MRF_AWIDTH-1:9*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[10*`NUM_LDPES*`MRF_AWIDTH-1:9*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[10*`NUM_LDPES*`MRF_DWIDTH-1:9*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[10*`NUM_LDPES-1:9*`NUM_LDPES]), + .result(result_mvm_9) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_10; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_10; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_10; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_10; + + MVU_tile tile_10(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_10), + .vrf_data_out(vrf_data_out_tile_10), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_10), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_10), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_10), + .out_data_available(out_data_available_mvm_tile_10), + .mrf_in(mrf_in[11*`MRF_DWIDTH*`NUM_LDPES-1:10*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[11*`NUM_LDPES-1:10*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[11*`NUM_LDPES*`MRF_AWIDTH-1:10*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[11*`NUM_LDPES*`MRF_AWIDTH-1:10*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[11*`NUM_LDPES*`MRF_DWIDTH-1:10*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[11*`NUM_LDPES-1:10*`NUM_LDPES]), + .result(result_mvm_10) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_11; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_11; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_11; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_11; + + MVU_tile tile_11(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_11), + .vrf_data_out(vrf_data_out_tile_11), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_11), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_11), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_11), + .out_data_available(out_data_available_mvm_tile_11), + .mrf_in(mrf_in[12*`MRF_DWIDTH*`NUM_LDPES-1:11*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[12*`NUM_LDPES-1:11*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[12*`NUM_LDPES*`MRF_AWIDTH-1:11*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[12*`NUM_LDPES*`MRF_AWIDTH-1:11*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[12*`NUM_LDPES*`MRF_DWIDTH-1:11*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[12*`NUM_LDPES-1:11*`NUM_LDPES]), + .result(result_mvm_11) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_12; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_12; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_12; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_12; + + MVU_tile tile_12(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_12), + .vrf_data_out(vrf_data_out_tile_12), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_12), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_12), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_12), + .out_data_available(out_data_available_mvm_tile_12), + .mrf_in(mrf_in[13*`MRF_DWIDTH*`NUM_LDPES-1:12*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[13*`NUM_LDPES-1:12*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[13*`NUM_LDPES*`MRF_AWIDTH-1:12*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[13*`NUM_LDPES*`MRF_AWIDTH-1:12*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[13*`NUM_LDPES*`MRF_DWIDTH-1:12*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[13*`NUM_LDPES-1:12*`NUM_LDPES]), + .result(result_mvm_12) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_13; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_13; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_13; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_13; + + MVU_tile tile_13(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_13), + .vrf_data_out(vrf_data_out_tile_13), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_13), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_13), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_13), + .out_data_available(out_data_available_mvm_tile_13), + .mrf_in(mrf_in[14*`MRF_DWIDTH*`NUM_LDPES-1:13*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[14*`NUM_LDPES-1:13*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[14*`NUM_LDPES*`MRF_AWIDTH-1:13*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[14*`NUM_LDPES*`MRF_AWIDTH-1:13*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[14*`NUM_LDPES*`MRF_DWIDTH-1:13*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[14*`NUM_LDPES-1:13*`NUM_LDPES]), + .result(result_mvm_13) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_14; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_14; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_14; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_14; + + MVU_tile tile_14(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_14), + .vrf_data_out(vrf_data_out_tile_14), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_14), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_14), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_14), + .out_data_available(out_data_available_mvm_tile_14), + .mrf_in(mrf_in[15*`MRF_DWIDTH*`NUM_LDPES-1:14*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[15*`NUM_LDPES-1:14*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[15*`NUM_LDPES*`MRF_AWIDTH-1:14*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[15*`NUM_LDPES*`MRF_AWIDTH-1:14*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[15*`NUM_LDPES*`MRF_DWIDTH-1:14*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[15*`NUM_LDPES-1:14*`NUM_LDPES]), + .result(result_mvm_14) //WITH TAG + ); + wire[`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result_mvm_15; + wire[`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp_15; + wire[`NUM_LDPES-1:0] out_data_available_internal_comparator_tree_15; + + wire[`NUM_LDPES-1:0] out_data_available_mvm_tile_15; + + MVU_tile tile_15(.clk(clk), + .start(start), + .reset(reset), + .vrf_wr_addr(vrf_wr_addr), + .vec(vec), + .max_exp(max_exp_15), + .vrf_data_out(vrf_data_out_tile_15), //WITH TAG + .vrf_wr_enable(vrf_wr_enable_tile_15), //WITH TAG + .vrf_readn_enable(vrf_readn_enable_tile_15), //WITH TAG + .vrf_read_addr(vrf_read_addr), + .out_data_available_external_comparator_tree(out_data_available_comparator_tile), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree_15), + .out_data_available(out_data_available_mvm_tile_15), + .mrf_in(mrf_in[16*`MRF_DWIDTH*`NUM_LDPES-1:15*`MRF_DWIDTH*`NUM_LDPES]), + .mrf_we(mrf_we[16*`NUM_LDPES-1:15*`NUM_LDPES]), //WITH TAG + .mrf_addr(mrf_addr[16*`NUM_LDPES*`MRF_AWIDTH-1:15*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[16*`NUM_LDPES*`MRF_AWIDTH-1:15*`NUM_LDPES*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[16*`NUM_LDPES*`MRF_DWIDTH-1:15*`NUM_LDPES*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[16*`NUM_LDPES-1:15*`NUM_LDPES]), + .result(result_mvm_15) //WITH TAG + ); + + + +assign start_external_comparator_tree = out_data_available_internal_comparator_tree_0; + +exponent_comparator_tree_tile exp_cmp ( + .clk(clk), + .reset(reset), + .start(start_external_comparator_tree), + .out_data_available(out_data_available_comparator_tile), + .inp0(max_exp_0), + .inp1(max_exp_1), + .inp2(max_exp_2), + .inp3(max_exp_3), + .inp4(max_exp_4), + .inp5(max_exp_5), + .inp6(max_exp_6), + .inp7(max_exp_7), + .inp8(max_exp_8), + .inp9(max_exp_9), + .inp10(max_exp_10), + .inp11(max_exp_11), + .inp12(max_exp_12), + .inp13(max_exp_13), + .inp14(max_exp_14), + .inp15(max_exp_15), + .result_final_stage(max_exp_final) +); + + +wire[`NUM_LDPES*`LDPE_USED_OUTPUT_WIDTH-1:0] reduction_unit_output; +wire[`NUM_LDPES-1:0] out_data_available_reduction; + +wire[`NUM_LDPES-1:0] start_reduction_tree; +assign start_reduction_tree = out_data_available_mvm_tile_0; + + +mvm_reduction_unit mvm_reduction ( + .clk(clk), + .reset_reduction_mvm(reset), + .start(start_reduction_tree), + .out_data_available(out_data_available_reduction), + .inp0(result_mvm_0), + .inp1(result_mvm_1), + .inp2(result_mvm_2), + .inp3(result_mvm_3), + .inp4(result_mvm_4), + .inp5(result_mvm_5), + .inp6(result_mvm_6), + .inp7(result_mvm_7), + .inp8(result_mvm_8), + .inp9(result_mvm_9), + .inp10(result_mvm_10), + .inp11(result_mvm_11), + .inp12(result_mvm_12), + .inp13(result_mvm_13), + .inp14(result_mvm_14), + .inp15(result_mvm_15), + .result_mvm_final_stage(reduction_unit_output) +); + +wire[`BFLOAT_DWIDTH*`NUM_LDPES-1:0] msfp11_out; +wire[`NUM_LDPES-1:0] out_data_available_msfp_gen; + +genvar i; +generate +`ifdef QUARTUS + for(i=1;i<=`NUM_LDPES;i=i+1) begin: gen_msfp +`else + for(i=1;i<=`NUM_LDPES;i=i+1) begin +`endif + msfp_generator msfp_gen( + .clk(clk), + .exponent(max_exp_final[i*`BFLOAT_EXP-1:(i-1)*`BFLOAT_EXP]), + .mantisa(reduction_unit_output[i*`LDPE_USED_OUTPUT_WIDTH-1:(i-1)*`LDPE_USED_OUTPUT_WIDTH]), + .reset(reset[i-1]), + .start(out_data_available_reduction[i-1]), + .out_data_available(out_data_available_msfp_gen[i-1]), + .msfp11(msfp11_out[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]) + ); + end +endgenerate + +wire[`NUM_LDPES-1:0] out_data_available_msfp11_to_fp16_converter; +wire [`FLOAT_DWIDTH*`NUM_LDPES-1:0] msfp_fp_converter_output; + +generate +`ifdef QUARTUS + for(i=1;i<=`NUM_LDPES;i=i+1) begin: gen_msfp11_fp16_conv +`else + for(i=1;i<=`NUM_LDPES;i=i+1) begin +`endif + msfp11_to_fp16 msfp_to_fp_converter( + .clk(clk), + .reset(reset[i-1]), + .start(out_data_available_msfp_gen[i-1]), + .out_data_available(out_data_available_msfp11_to_fp16_converter[i-1]), + .a(msfp11_out[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]), + .b(msfp_fp_converter_output[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]) + ); + end +endgenerate + +assign mvm_result = msfp_fp_converter_output; +assign out_data_available = out_data_available_msfp11_to_fp16_converter[0]; + +endmodule + +module msfp_generator( + input[`BFLOAT_EXP-1:0] exponent, + input[`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa, + input clk, + input reset, + input start, + output reg out_data_available, + output reg[`BFLOAT_DWIDTH-1:0] msfp11 +); + + wire sign, is_valid; + wire[2:0] position; + wire[`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa_sign_adjusted; + + + assign sign = mantisa[`LDPE_USED_OUTPUT_WIDTH-1]; + + assign mantisa_sign_adjusted = (sign) ? (-mantisa) : mantisa; + wire out_data_available_lzd; + + leading_zero_detector_6bit ldetector( + .reset(reset), + .start(start), + .clk(clk), + .a(mantisa_sign_adjusted[`BFLOAT_MANTISA_WITH_LO-1:0]), + .is_valid(is_valid), + .position(position), + .out_data_available(out_data_available_lzd) + ); + + + + wire[4:0] normalize_amt; + assign normalize_amt = (is_valid) ? position : 5'd0; + + wire[`BFLOAT_MANTISA_WITH_LO-1:0] significand_to_be_normalised; + assign significand_to_be_normalised = (is_valid) ? mantisa_sign_adjusted[`BFLOAT_MANTISA_WITH_LO-1:0] : 6'd0; + + wire out_data_available_barrel_shifter_left; + + wire[`BFLOAT_MANTISA_WITH_LO-1:0] mantisa_shifted; + barrel_shifter_left bshift_left( + .clk(clk), + .reset(reset), + .start(out_data_available_lzd), + .out_data_available(out_data_available_barrel_shifter_left), + .shift_amt(normalize_amt), + .significand(significand_to_be_normalised), + .shifted_sig(mantisa_shifted) + ); + wire[`BFLOAT_EXP-1:0] normalized_exponent; + + assign normalized_exponent = exponent - normalize_amt; + + always@(posedge clk) begin + if((reset==1) || (start==0)) begin + msfp11 <= 11'd0; + out_data_available <= 0; + end + else begin + out_data_available <= out_data_available_barrel_shifter_left; + msfp11 <= {sign, normalized_exponent, mantisa_shifted[`BFLOAT_MANTISA-1:0]}; + end + end + +endmodule + +module MVU_tile ( + input clk, + input[`NUM_LDPES-1:0] start, + input[`NUM_LDPES-1:0] reset, + input vrf_wr_enable, + input [`VRF_AWIDTH-1:0] vrf_wr_addr, + input [`VRF_AWIDTH-1:0] vrf_read_addr, + input [`VRF_DWIDTH-1:0] vec, + output[`VRF_DWIDTH-1:0] vrf_data_out, + input [`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_in, + input vrf_readn_enable, + input[`NUM_LDPES-1:0] mrf_we, + input[`NUM_LDPES-1:0] mrf_we_for_dram, + input [`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr, + input [`MRF_AWIDTH*`NUM_LDPES-1:0] mrf_addr_for_dram, + input [`NUM_LDPES-1:0] out_data_available_external_comparator_tree, + output [`NUM_LDPES-1:0] out_data_available_internal_comparator_tree, + output [`NUM_LDPES-1:0] out_data_available, + output [`BFLOAT_EXP*`NUM_LDPES-1:0] max_exp, + output [`LDPE_USED_OUTPUT_WIDTH*`NUM_LDPES-1:0] result, + output [`MRF_DWIDTH*`NUM_LDPES-1:0] mrf_outa_to_dram +); + + wire [`VRF_DWIDTH-1:0] ina_fake; + + + wire [`VRF_DWIDTH-1:0] vrf_outa_wire; + + // Port A is used to feed LDPE and port B to load vector from DRAM. + + VRF vrf ( + .clk(clk), + .addra(vrf_read_addr), + .ina(ina_fake), + .wea(vrf_readn_enable), + .outa(vrf_outa_wire), + .addrb(vrf_wr_addr), + .inb(vec), + .web(vrf_wr_enable), + .outb(vrf_data_out) + ); + + genvar i; + generate +`ifdef QUARTUS + for (i=1; i<=`NUM_LDPES; i=i+1) begin: gen_cus +`else + for (i=1; i<=`NUM_LDPES; i=i+1) begin +`endif + compute_unit unit ( + .clk(clk), + .reset(reset[i-1]), + .start(start[i-1]), + .vec(vrf_outa_wire), + .mrf_in(mrf_in[i*`MRF_DWIDTH-1:(i-1)*`MRF_DWIDTH]), + .mrf_we(mrf_we[i-1]), + .mrf_addr(mrf_addr[i*`MRF_AWIDTH-1:(i-1)*`MRF_AWIDTH]), + .mrf_addr_for_dram(mrf_addr_for_dram[i*`MRF_AWIDTH-1:(i-1)*`MRF_AWIDTH]), + .mrf_outa_to_dram(mrf_outa_to_dram[i*`MRF_DWIDTH-1:(i-1)*`MRF_DWIDTH]), + .mrf_we_for_dram(mrf_we_for_dram[i-1]), + .max_exp(max_exp[i*`BFLOAT_EXP-1:(i-1)*`BFLOAT_EXP]), + .out_data_available_external_comparator_tree(out_data_available_external_comparator_tree[i-1]), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree[i-1]), + .out_data_available_dot_prod(out_data_available[i-1]), + .result(result[i*`LDPE_USED_OUTPUT_WIDTH-1:(i-1)*`LDPE_USED_OUTPUT_WIDTH]) + ); + end + endgenerate + +endmodule + +module compute_unit ( + input clk, + input start, + input reset, + input [`VRF_DWIDTH-1:0] vec, + input [`MRF_DWIDTH-1:0] mrf_in, + input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new + input mrf_we, mrf_we_for_dram, //new + input [`MRF_AWIDTH-1:0] mrf_addr, + input out_data_available_external_comparator_tree, + output out_data_available_internal_comparator_tree, + output out_data_available_dot_prod, + output [`LDPE_USED_OUTPUT_WIDTH-1:0] result, + output [`MRF_DWIDTH-1:0] mrf_outa_to_dram, //new + output [`BFLOAT_EXP-1:0] max_exp +); + + // Port B of BRAMs is used for feed DSPs and Port A is used to interact with DRAM + + + wire [`MRF_DWIDTH-1:0] mrf_outb_wire; + + wire [`LDPE_USED_INPUT_WIDTH-1:0] ax_wire; + wire [`LDPE_USED_INPUT_WIDTH-1:0] ay_wire; + wire [`LDPE_USED_INPUT_WIDTH-1:0] bx_wire; + wire [`LDPE_USED_INPUT_WIDTH-1:0] by_wire; + + // Wire connecting LDPE output to Output BRAM input + wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result; + + wire [`LDPE_USED_OUTPUT_WIDTH-1:0] inb_fake_wire; + + // First 4 BRAM outputs are given to ax of 4 DSPs and next 4 BRAM outputs are given to bx of DSPs + + // Connection MRF and LDPE wires for matrix data + // 'X' pin is used for matrix + /* If there are 4 DSPSs, bit[31:0] of mrf output contain ax values for the 4 DSPs, bit[63:32] contain bx values and so on. With a group of ax values, bit[7:0] contain ax value for DSP1, bit[15:8] contain ax value for DSP2 and so on. */ + assign ax_wire = mrf_outb_wire[1*`LDPE_USED_INPUT_WIDTH-1:0*`LDPE_USED_INPUT_WIDTH]; + assign bx_wire = mrf_outb_wire[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH]; + + // Connection of VRF and LDPE wires for vector data + // 'Y' pin is used for vector + assign ay_wire = vec[`LDPE_USED_INPUT_WIDTH-1:0]; + assign by_wire = vec[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH]; + + wire [`MRF_DWIDTH-1:0] mrf_in_fake; + + MRF mrf ( + .clk(clk), + .addra(mrf_addr_for_dram), + .addrb(mrf_addr), + .ina(mrf_in), + .inb(mrf_in_fake), + .wea(mrf_we_for_dram), + .web(mrf_we), + .outa(mrf_outa_to_dram), + .outb(mrf_outb_wire) + ); + + LDPE ldpe ( + .clk(clk), + .reset(reset), + .start(start), + .ax(ax_wire), + .ay(ay_wire), + .bx(bx_wire), + .by(by_wire), + .out_data_available_external_comparator_tree(out_data_available_external_comparator_tree), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree), + .out_data_available_dot_prod(out_data_available_dot_prod), + .ldpe_result(ldpe_result), + .max_exp(max_exp) + ); + assign result = ldpe_result; + +endmodule + +module LDPE ( + input clk, + input reset, + input start, + input [`LDPE_USED_INPUT_WIDTH-1:0] ax, + input [`LDPE_USED_INPUT_WIDTH-1:0] ay, + input [`LDPE_USED_INPUT_WIDTH-1:0] bx, + input [`LDPE_USED_INPUT_WIDTH-1:0] by, + input out_data_available_external_comparator_tree, + output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result, + output out_data_available_internal_comparator_tree, + output out_data_available_dot_prod, + output [`BFLOAT_EXP-1:0] max_exp +); + + + wire[`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] ax_in_sub_ldpe; + wire[`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] ay_in_sub_ldpe; + wire[`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] bx_in_sub_ldpe; + wire[`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] by_in_sub_ldpe; + wire [`LDPE_USED_OUTPUT_WIDTH-1:0] sub_ldpe_result; + wire[`DSPS_PER_LDPE-1:0] out_data_available_ax; + + genvar i; + generate +`ifdef QUARTUS + for (i=1; i<=`DSPS_PER_LDPE; i=i+1) begin: gen_fp16_msfp11_conv1 +`else + for (i=1; i<=`DSPS_PER_LDPE; i=i+1) begin +`endif + fp16_to_msfp11 fp_converter_ax(.rst(reset),.start(start),.a(ax[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),.b(ax_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),.out_data_available(out_data_available_ax[i-1]),.clk(clk)); + end + endgenerate + + wire[`DSPS_PER_LDPE-1:0] out_data_available_ay; + + generate +`ifdef QUARTUS + for (i=1; i<=`DSPS_PER_LDPE; i=i+1) begin: gen_fp16_msfp11_conv2 +`else + for (i=1; i<=`DSPS_PER_LDPE; i=i+1) begin +`endif + fp16_to_msfp11 fp_converter_ay(.rst(reset),.start(start),.a(ay[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),.b(ay_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),.out_data_available(out_data_available_ay[i-1]),.clk(clk)); + end + endgenerate + + wire[`DSPS_PER_LDPE-1:0] out_data_available_bx; + + generate +`ifdef QUARTUS + for (i=1; i<=`DSPS_PER_LDPE; i=i+1) begin: gen_fp16_msfp11_conv3 +`else + for (i=1; i<=`DSPS_PER_LDPE; i=i+1) begin +`endif + fp16_to_msfp11 fp_converter_bx(.rst(reset),.start(start),.a(bx[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),.b(bx_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),.out_data_available(out_data_available_bx[i-1]),.clk(clk)); + end + endgenerate + + wire[`DSPS_PER_LDPE-1:0] out_data_available_by; + + generate +`ifdef QUARTUS + for (i=1; i<=`DSPS_PER_LDPE; i=i+1) begin: gen_fp16_msfp11_conv4 +`else + for (i=1; i<=`DSPS_PER_LDPE; i=i+1) begin +`endif + fp16_to_msfp11 fp_converter_by(.rst(reset),.start(start),.a(by[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),.b(by_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),.out_data_available(out_data_available_by[i-1]),.clk(clk)); + end + endgenerate + wire start_subldpe; + assign start_subldpe = out_data_available_ax[0]; + + SUB_LDPE sub_1( + .clk(clk), + .reset(reset), + .start(start_subldpe), + .ax(ax_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .ay(ay_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .bx(bx_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .by(by_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]), + .out_data_available_external_comparator_tree(out_data_available_external_comparator_tree), + .out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree), + .out_data_available_dot_prod(out_data_available_dot_prod), + .result(sub_ldpe_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH]), + .max_exp(max_exp) + ); + + + assign ldpe_result = (start==1'b0) ? 27'd0 : sub_ldpe_result[(0+1)*`DSP_USED_OUTPUT_WIDTH-1:0*`DSP_USED_OUTPUT_WIDTH]; + + +endmodule + +module myadder #( + parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH, + parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH +) +( + input [INPUT_WIDTH-1:0] a, + input [INPUT_WIDTH-1:0] b, + input reset, + input start, + input clk, + output reg [OUTPUT_WIDTH-1:0] sum, + output reg out_data_available +); + + always@(posedge clk) begin + if((reset==1) || (start==0)) begin + sum <= 0; + out_data_available <= 0; + end + else begin + out_data_available <= 1; + sum <= a + b; + end + end + +endmodule + + +module SUB_LDPE ( + input clk, + input reset, + input start, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] ax, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] ay, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] bx, + input [`SUB_LDPE_USED_INPUT_WIDTH-1:0] by, + input out_data_available_external_comparator_tree, + output reg [`LDPE_USED_OUTPUT_WIDTH-1:0] result, + output out_data_available_internal_comparator_tree, + output reg out_data_available_dot_prod, + output [`BFLOAT_EXP-1:0] max_exp +); + + + wire [`DSP_USED_OUTPUT_WIDTH*`DSPS_PER_SUB_LDPE-1:0] chainin, chainout, dsp_result; + + wire [36:0] chainout_temp_0; + assign chainout_temp_0 = 37'b0; + + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_1; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_1; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_1; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_1; + + wire [`BFLOAT_DWIDTH-1:0] ax_wire_1_num; + wire [`BFLOAT_DWIDTH-1:0] ay_wire_1_num; + wire [`BFLOAT_DWIDTH-1:0] bx_wire_1_num; + wire [`BFLOAT_DWIDTH-1:0] by_wire_1_num; + + wire [`BFLOAT_MANTISA_WITH_LO-1:0] ax_wire_1_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] ay_wire_1_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] bx_wire_1_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] by_wire_1_mantisa_shifted; + + assign ax_wire_1_num = ax[1*`BFLOAT_DWIDTH-1:(1-1)*`BFLOAT_DWIDTH]; + assign ay_wire_1_num = ay[1*`BFLOAT_DWIDTH-1:(1-1)*`BFLOAT_DWIDTH]; + assign bx_wire_1_num = bx[1*`BFLOAT_DWIDTH-1:(1-1)*`BFLOAT_DWIDTH]; + assign by_wire_1_num = by[1*`BFLOAT_DWIDTH-1:(1-1)*`BFLOAT_DWIDTH]; + + wire[`BFLOAT_EXP-1:0] shift_amt_1_ax; + assign shift_amt_1_ax = max_exp - ax_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + + wire out_data_available_barrel_shifter_ax_1; + wire start_barrel_shifter_ax_1; + + assign start_barrel_shifter_ax_1 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_ax_1( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_ax_1), + .out_data_available(out_data_available_barrel_shifter_ax_1), + .shift_amt(shift_amt_1_ax), + .significand({1'b1,ax_wire_1_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(ax_wire_1_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_1_ay; + assign shift_amt_1_ay = max_exp - ay_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_ay_1; + wire start_barrel_shifter_ay_1; + + assign start_barrel_shifter_ay_1 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_ay_1( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_ay_1), + .out_data_available(out_data_available_barrel_shifter_ay_1), + .shift_amt(shift_amt_1_ay), + .significand({1'b1,ay_wire_1_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(ay_wire_1_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_1_bx; + assign shift_amt_1_bx = max_exp - bx_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_bx_1; + wire start_barrel_shifter_bx_1; + + assign start_barrel_shifter_bx_1 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_bx_1( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_bx_1), + .out_data_available(out_data_available_barrel_shifter_bx_1), + .shift_amt(shift_amt_1_bx), + .significand({1'b1,bx_wire_1_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(bx_wire_1_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_1_by; + assign shift_amt_1_by = max_exp - by_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_by_1; + wire start_barrel_shifter_by_1; + + assign start_barrel_shifter_by_1 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_by_1( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_by_1), + .out_data_available(out_data_available_barrel_shifter_by_1), + .shift_amt(shift_amt_1_by), + .significand({1'b1,by_wire_1_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(by_wire_1_mantisa_shifted) + ); + + assign ax_wire_1 = (ax_wire_1_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax_wire_1_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax_wire_1_mantisa_shifted}; + assign ay_wire_1 = (ay_wire_1_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay_wire_1_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay_wire_1_mantisa_shifted}; + assign bx_wire_1 = (bx_wire_1_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx_wire_1_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx_wire_1_mantisa_shifted}; + assign by_wire_1 = (by_wire_1_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, by_wire_1_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, by_wire_1_mantisa_shifted}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_1; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_1; + + assign dsp_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_1[`DSP_USED_OUTPUT_WIDTH-1:0]; + + wire reset_dsp_1; + assign reset_dsp_1 = ~out_data_available_barrel_shifter_ax_1; + + dsp_block_18_18_int_sop_2 dsp_1 ( + .clk(clk), + .aclr(reset_dsp_1), + .ax(ax_wire_1), + .ay(ay_wire_1), + .bx(bx_wire_1), + .by(by_wire_1), + .chainin(chainout_temp_0), + .chainout(chainout_temp_1), + .result(result_temp_1) + ); + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_wire_2; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_wire_2; + wire [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_wire_2; + wire [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_wire_2; + + wire [`BFLOAT_DWIDTH-1:0] ax_wire_2_num; + wire [`BFLOAT_DWIDTH-1:0] ay_wire_2_num; + wire [`BFLOAT_DWIDTH-1:0] bx_wire_2_num; + wire [`BFLOAT_DWIDTH-1:0] by_wire_2_num; + + wire [`BFLOAT_MANTISA_WITH_LO-1:0] ax_wire_2_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] ay_wire_2_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] bx_wire_2_mantisa_shifted; + wire [`BFLOAT_MANTISA_WITH_LO-1:0] by_wire_2_mantisa_shifted; + + assign ax_wire_2_num = ax[2*`BFLOAT_DWIDTH-1:(2-1)*`BFLOAT_DWIDTH]; + assign ay_wire_2_num = ay[2*`BFLOAT_DWIDTH-1:(2-1)*`BFLOAT_DWIDTH]; + assign bx_wire_2_num = bx[2*`BFLOAT_DWIDTH-1:(2-1)*`BFLOAT_DWIDTH]; + assign by_wire_2_num = by[2*`BFLOAT_DWIDTH-1:(2-1)*`BFLOAT_DWIDTH]; + + wire[`BFLOAT_EXP-1:0] shift_amt_2_ax; + assign shift_amt_2_ax = max_exp - ax_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + + wire out_data_available_barrel_shifter_ax_2; + wire start_barrel_shifter_ax_2; + + assign start_barrel_shifter_ax_2 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_ax_2( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_ax_2), + .out_data_available(out_data_available_barrel_shifter_ax_2), + .shift_amt(shift_amt_2_ax), + .significand({1'b1,ax_wire_2_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(ax_wire_2_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_2_ay; + assign shift_amt_2_ay = max_exp - ay_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_ay_2; + wire start_barrel_shifter_ay_2; + + assign start_barrel_shifter_ay_2 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_ay_2( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_ay_2), + .out_data_available(out_data_available_barrel_shifter_ay_2), + .shift_amt(shift_amt_2_ay), + .significand({1'b1,ay_wire_2_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(ay_wire_2_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_2_bx; + assign shift_amt_2_bx = max_exp - bx_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_bx_2; + wire start_barrel_shifter_bx_2; + + assign start_barrel_shifter_bx_2 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_bx_2( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_bx_2), + .out_data_available(out_data_available_barrel_shifter_bx_2), + .shift_amt(shift_amt_2_bx), + .significand({1'b1,bx_wire_2_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(bx_wire_2_mantisa_shifted) + ); + + wire[`BFLOAT_EXP-1:0] shift_amt_2_by; + assign shift_amt_2_by = max_exp - by_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]; + wire out_data_available_barrel_shifter_by_2; + wire start_barrel_shifter_by_2; + + assign start_barrel_shifter_by_2 = out_data_available_external_comparator_tree; + + barrel_shifter_right bshift_by_2( + .clk(clk), + .reset(reset), + .start(start_barrel_shifter_by_2), + .out_data_available(out_data_available_barrel_shifter_by_2), + .shift_amt(shift_amt_2_by), + .significand({1'b1,by_wire_2_num[`BFLOAT_MANTISA-1:0]}), + .shifted_sig(by_wire_2_mantisa_shifted) + ); + + assign ax_wire_2 = (ax_wire_2_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax_wire_2_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ax_wire_2_mantisa_shifted}; + assign ay_wire_2 = (ay_wire_2_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay_wire_2_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, ay_wire_2_mantisa_shifted}; + assign bx_wire_2 = (bx_wire_2_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx_wire_2_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, bx_wire_2_mantisa_shifted}; + assign by_wire_2 = (by_wire_2_num[`BFLOAT_DWIDTH-1]==1'b1) ? -{{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, by_wire_2_mantisa_shifted} : {{`DSP_X_ZERO_PAD_INPUT_WIDTH{1'b0}}, by_wire_2_mantisa_shifted}; + + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout_temp_2; + wire [`DSP_AVA_OUTPUT_WIDTH-1:0] result_temp_2; + + assign dsp_result[2*`DSP_USED_OUTPUT_WIDTH-1:(2-1)*`DSP_USED_OUTPUT_WIDTH] = result_temp_2[`DSP_USED_OUTPUT_WIDTH-1:0]; + + wire reset_dsp_2; + assign reset_dsp_2 = ~out_data_available_barrel_shifter_ax_2; + + dsp_block_18_18_int_sop_2 dsp_2 ( + .clk(clk), + .aclr(reset_dsp_2), + .ax(ax_wire_2), + .ay(ay_wire_2), + .bx(bx_wire_2), + .by(by_wire_2), + .chainin(chainout_temp_1), + .chainout(chainout_temp_2), + .result(result_temp_2) + ); + + +exponent_comparator_tree_ldpe exp_cmp ( + .clk(clk), + .reset(reset), + .start(start), + .out_data_available(out_data_available_internal_comparator_tree), + .inp0(ax_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp1(ax_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp2(ay_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp3(ay_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp4(bx_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp5(bx_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp6(by_wire_1_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .inp7(by_wire_2_num[`BFLOAT_EXP+`BFLOAT_MANTISA-1:`BFLOAT_MANTISA]), + .result_final_stage(max_exp) +); + + + always @(*) begin + if (reset==1'b1 || start==1'b0) begin + result <= {`LDPE_USED_OUTPUT_WIDTH{1'd0}}; + end + else begin + result <= dsp_result[`DSPS_PER_SUB_LDPE*`LDPE_USED_OUTPUT_WIDTH-1:(`DSPS_PER_SUB_LDPE-1)*`LDPE_USED_OUTPUT_WIDTH]; + end + end + + + reg [4:0] num_cycles_mvm; + + always@(posedge clk) begin + if((reset==1'b1) || (out_data_available_barrel_shifter_ax_1==1'b0)) begin + num_cycles_mvm<=0; + out_data_available_dot_prod<=0; + end + else begin + if(num_cycles_mvm==`NUM_MVM_CYCLES-1) begin + out_data_available_dot_prod <= 1; + end + else begin + num_cycles_mvm <= num_cycles_mvm + 1'b1; + end + end + end + +endmodule + +module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) ( + input clk, + input [VRF_AWIDTH-1:0] addra, addrb, + input [VRF_DWIDTH-1:0] ina, inb, + input wea, web, + output [VRF_DWIDTH-1:0] outa, outb +); + + dp_ram # ( + .AWIDTH(VRF_AWIDTH), + .DWIDTH(VRF_DWIDTH) + ) vec_mem ( + .clk(clk), + .addra(addra), + .ina(ina), + .wea(wea), + .outa(outa), + .addrb(addrb), + .inb(inb), + .web(web), + .outb(outb) + ); + +endmodule + +module MRF ( + input clk, + input [`MRF_AWIDTH-1:0] addra, addrb, + input [`MRF_DWIDTH-1:0] ina, inb, + input wea, web, + output [`MRF_DWIDTH-1:0] outa, outb +); + + dp_ram # ( + .AWIDTH(`MRF_AWIDTH), + .DWIDTH(`MRF_DWIDTH) + ) vec_mem ( + .clk(clk), + .addra(addra), + .ina(ina), + .wea(wea), + .outa(outa), + .addrb(addrb), + .inb(inb), + .web(web), + .outb(outb) + ); + +endmodule + +module dsp_block_18_18_int_sop_2 ( + input clk, + input aclr, + input [`DSP_X_AVA_INPUT_WIDTH-1:0] ax, + input [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay, + input [`DSP_X_AVA_INPUT_WIDTH-1:0] bx, + input [`DSP_Y_AVA_INPUT_WIDTH-1:0] by, + input [`DSP_AVA_OUTPUT_WIDTH-1:0] chainin, + output [`DSP_AVA_OUTPUT_WIDTH-1:0] chainout, + output [`DSP_AVA_OUTPUT_WIDTH-1:0] result +); + +`ifndef complex_dsp + +reg [`DSP_X_AVA_INPUT_WIDTH-1:0] ax_reg; +reg [`DSP_Y_AVA_INPUT_WIDTH-1:0] ay_reg; +reg [`DSP_X_AVA_INPUT_WIDTH-1:0] bx_reg; +reg [`DSP_Y_AVA_INPUT_WIDTH-1:0] by_reg; +reg [`DSP_AVA_OUTPUT_WIDTH-1:0] result_reg; + +always @(posedge clk) begin + if(aclr) begin + result_reg <= 0; + ax_reg <= 0; + ay_reg <= 0; + bx_reg <= 0; + by_reg <= 0; + end + else begin + ax_reg <= ax; + ay_reg <= ay; + bx_reg <= bx; + by_reg <= by; + result_reg <= (ax_reg * ay_reg) + (bx_reg * by_reg) + chainin; + end +end +assign chainout = result_reg; +assign result = result_reg; + +`else + +wire [11:0] mode; +assign mode = 12'b0101_0101_0011; + +int_sop_2 mac_component ( + .mode_sigs(mode), + .clk(clk), + .reset(aclr), + .ax(ax), + .ay(ay), + .bx(bx), + .by(by), + .chainin(chainin), + .result(result), + .chainout(chainout) +); + +`endif + +endmodule + +////////////////////////////////// +// Dual port RAM +////////////////////////////////// + +module dp_ram # ( + parameter AWIDTH = 10, + parameter DWIDTH = 16 +) ( + input clk, + input [AWIDTH-1:0] addra, addrb, + input [DWIDTH-1:0] ina, inb, + input wea, web, + output reg [DWIDTH-1:0] outa, outb +); + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram [((1<b) ? a : b; + out_data_available <= 1; + end + end +endmodule + +module fp16_to_msfp11 (input clk, input [15:0] a , input rst, input start, output reg [10:0] b, output reg out_data_available); + +reg [10:0]b_temp; + +always @ (*) begin + +if ( a [14: 0] == 15'b0 ) begin //signed zero + b_temp [10] = a[15]; //sign bit + b_temp [9:0] = 7'b0000000; //EXPONENT AND MANTISSA +end + +else begin + + b_temp [4:0] = a[9:5]; //MANTISSA + b_temp [9:5] = a[14:10]; //EXPONENT NOTE- EXPONENT SIZE IS SAME IN BOTH + b_temp [10] = a[15]; //SIGN + end +end + +always@(posedge clk) begin + if((rst==1'b1) || (start==1'b0)) begin + b <= 11'd0; + out_data_available <= 0; + end + else begin + b <= b_temp; + out_data_available <= 1; + end +end + + +endmodule + + +module msfp11_to_fp16 (input reset, input start, input clk, input [10:0] a , output reg [15:0] b, output reg out_data_available); + +reg [15:0]b_temp; +reg [3:0] j; +reg [2:0] k; +reg [2:0] k_temp; + +always @ (*) begin + +if ( a [9: 0] == 7'b0 ) begin //signed zero + b_temp [15] = a[10]; //sign bit + b_temp[14:0] = 15'b0; +end + +else begin +/* + if ( a[9:5] == 5'b0 ) begin //denormalized (covert to normalized) + + for (j=0; j<=4; j=j+1) begin + if (a[j] == 1'b1) begin + k_temp = j; + end + end + k = 1 - k_temp; + + b_temp [9:0] = ( (a [4:0] << (k+1'b1)) & 5'b11111 ) << 5; + //b_temp [14:10] = 5'd31 - 5'd31 - k; //PROBLEM - DISCUSS THIS ************ SHOULD BE +k + b_temp [14:10] = 5'd31 - 5'd31 + k; + b_temp [15] = a[10]; + end +*/ + if ( a[9:5] == 5'b11111 ) begin //Infinity/ NAN //removed else here + b_temp [9:0] = a [4:0] << 5; + b_temp [14:10] = 5'b11111; + b_temp [15] = a[10]; + end + + else begin //Normalized Number + b_temp [9:0] = a [4:0] << 5; + b_temp [14:10] = 5'd31 - 5'd31 + a[6:2]; + b_temp [15] = a[10]; + end +end +end + +always@(posedge clk) begin + if((reset==1'b1) || (start==1'b0)) begin + out_data_available <= 0; + b <= 16'd0; + end + else begin + b <= b_temp; + out_data_available <= 1; + end +end + +endmodule + +`ifndef complex_dsp +module FPAddSub( + //bf16, + clk, + rst, + a, + b, + operation, // 0 add, 1 sub + result, + flags + ); + //input bf16; //1 for Bfloat16, 0 for IEEE half precision + + // Clock and reset + input clk ; // Clock signal + input rst ; // Reset (active high, resets pipeline registers) + + // Input ports + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + input operation ; // Operation select signal + + // Output ports + output [`DWIDTH-1:0] result ; // Result of the operation + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Pipeline Registers + //reg [79:0] pipe_1; // Pipeline register PreAlign->Align1 + reg [2*`EXPONENT + 2*`DWIDTH + 5:0] pipe_1; // Pipeline register PreAlign->Align1 + + //reg [67:0] pipe_2; // Pipeline register Align1->Align3 + //reg [2*`EXPONENT+ 2*`MANTISSA + 8:0] pipe_2; // Pipeline register Align1->Align3 + wire [2*`EXPONENT+ 2*`MANTISSA + 8:0] pipe_2; + + //reg [76:0] pipe_3; 68 // Pipeline register Align1->Align3 + reg [2*`EXPONENT+ 2*`MANTISSA + 9:0] pipe_3; // Pipeline register Align1->Align3 + + //reg [69:0] pipe_4; // Pipeline register Align3->Execute + //reg [2*`EXPONENT+ 2*`MANTISSA + 9:0] pipe_4; // Pipeline register Align3->Execute + wire [2*`EXPONENT+ 2*`MANTISSA + 9:0] pipe_4; + + //reg [51:0] pipe_5; // Pipeline register Execute->Normalize + reg [`DWIDTH+`EXPONENT+11:0] pipe_5; // Pipeline register Execute->Normalize + + //reg [56:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + //reg [`DWIDTH+`EXPONENT+16:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + wire [`DWIDTH+`EXPONENT+16:0] pipe_6; + + //reg [56:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + //reg [`DWIDTH+`EXPONENT+16:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + wire [`DWIDTH+`EXPONENT+16:0] pipe_7; + //reg [54:0] pipe_8; // Pipeline register NormalizeShift3->Round + reg [`EXPONENT*2+`MANTISSA+15:0] pipe_8; // Pipeline register NormalizeShift3->Round + + //reg [40:0] pipe_9; // Pipeline register NormalizeShift3->Round + //reg [`DWIDTH+8:0] pipe_9; // Pipeline register NormalizeShift3->Round + wire [`DWIDTH+8:0] pipe_9; + + // Internal wires between modules + wire [`DWIDTH-2:0] Aout_0 ; // A - sign + wire [`DWIDTH-2:0] Bout_0 ; // B - sign + wire Opout_0 ; // A's sign + wire Sa_0 ; // A's sign + wire Sb_0 ; // B's sign + wire MaxAB_1 ; // Indicates the larger of A and B(0/A, 1/B) + wire [`EXPONENT-1:0] CExp_1 ; // Common Exponent + wire [`EXPONENT-1:0] Shift_1 ; // Number of steps to smaller mantissa shift right (align) + wire [`MANTISSA-1:0] Mmax_1 ; // Larger mantissa + wire [4:0] InputExc_0 ; // Input numbers are exceptions + wire [2*`EXPONENT-1:0] ShiftDet_0 ; + wire [`MANTISSA-1:0] MminS_1 ; // Smaller mantissa after 0/16 shift + wire [`MANTISSA:0] MminS_2 ; // Smaller mantissa after 0/4/8/12 shift + wire [`MANTISSA:0] Mmin_3 ; // Smaller mantissa after 0/1/2/3 shift + wire [`DWIDTH:0] Sum_4 ; + wire PSgn_4 ; + wire Opr_4 ; + wire [`EXPONENT-1:0] Shift_5 ; // Number of steps to shift sum left (normalize) + wire [`DWIDTH:0] SumS_5 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_6 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_7 ; // Sum after 0/16 shift + wire [`MANTISSA-1:0] NormM_8 ; // Normalized mantissa + wire [`EXPONENT:0] NormE_8; // Adjusted exponent + wire ZeroSum_8 ; // Zero flag + wire NegE_8 ; // Flag indicating negative exponent + wire R_8 ; // Round bit + wire S_8 ; // Final sticky bit + wire FG_8 ; // Final sticky bit + wire [`DWIDTH-1:0] P_int ; + wire EOF ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_PrealignModule PrealignModule + ( // Inputs + a, b, operation, + // Outputs + Sa_0, Sb_0, ShiftDet_0[2*`EXPONENT-1:0], InputExc_0[4:0], Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Opout_0) ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_AlignModule AlignModule + ( // Inputs + pipe_1[2*`EXPONENT + 2*`DWIDTH + 4: 2*`EXPONENT +`DWIDTH + 6], pipe_1[2*`EXPONENT +`DWIDTH + 5 : 2*`EXPONENT +7], pipe_1[2*`EXPONENT+4:5], + // Outputs + CExp_1[`EXPONENT-1:0], MaxAB_1, Shift_1[`EXPONENT-1:0], MminS_1[`MANTISSA-1:0], Mmax_1[`MANTISSA-1:0]) ; + + // Alignment Shift Stage 1 + FPAddSub_AlignShift1 AlignShift1 + ( // Inputs + //bf16, + pipe_2[`MANTISSA-1:0], pipe_2[`EXPONENT+ 2*`MANTISSA + 4 : 2*`MANTISSA + 7], + // Outputs + MminS_2[`MANTISSA:0]) ; + + // Alignment Shift Stage 3 and compution of guard and sticky bits + FPAddSub_AlignShift2 AlignShift2 + ( // Inputs + pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+7:2*`MANTISSA+6], + // Outputs + Mmin_3[`MANTISSA:0]) ; + + // Perform mantissa addition + FPAddSub_ExecutionModule ExecutionModule + ( // Inputs + pipe_4[`MANTISSA*2+5:`MANTISSA+6], pipe_4[`MANTISSA:0], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 8], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 7], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 6], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 9], + // Outputs + Sum_4[`DWIDTH:0], PSgn_4, Opr_4) ; + + // Prepare normalization of result + FPAddSub_NormalizeModule NormalizeModule + ( // Inputs + pipe_5[`DWIDTH:0], + // Outputs + SumS_5[`DWIDTH:0], Shift_5[4:0]) ; + + // Normalization Shift Stage 1 + FPAddSub_NormalizeShift1 NormalizeShift1 + ( // Inputs + pipe_6[`DWIDTH:0], pipe_6[`DWIDTH+`EXPONENT+14:`DWIDTH+`EXPONENT+11], + // Outputs + SumS_7[`DWIDTH:0]) ; + + // Normalization Shift Stage 3 and final guard, sticky and round bits + FPAddSub_NormalizeShift2 NormalizeShift2 + ( // Inputs + pipe_7[`DWIDTH:0], pipe_7[`DWIDTH+`EXPONENT+5:`DWIDTH+6], pipe_7[`DWIDTH+`EXPONENT+15:`DWIDTH+`EXPONENT+11], + // Outputs + NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8, FG_8) ; + + // Round and put result together + FPAddSub_RoundModule RoundModule + ( // Inputs + pipe_8[3], pipe_8[4+`EXPONENT:4], pipe_8[`EXPONENT+`MANTISSA+4:5+`EXPONENT], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT*2+`MANTISSA+15], pipe_8[`EXPONENT*2+`MANTISSA+12], pipe_8[`EXPONENT*2+`MANTISSA+11], pipe_8[`EXPONENT*2+`MANTISSA+14], pipe_8[`EXPONENT*2+`MANTISSA+10], + // Outputs + P_int[`DWIDTH-1:0], EOF) ; + + // Check for exceptions + FPAddSub_ExceptionModule Exceptionmodule + ( // Inputs + pipe_9[8+`DWIDTH:9], pipe_9[8], pipe_9[7], pipe_9[6], pipe_9[5:1], pipe_9[0], + // Outputs + result[`DWIDTH-1:0], flags[4:0]) ; + + +assign pipe_2 = {pipe_1[2*`EXPONENT + 2*`DWIDTH + 5], pipe_1[2*`EXPONENT +6:2*`EXPONENT +5], MaxAB_1, CExp_1[`EXPONENT-1:0], Shift_1[`EXPONENT-1:0], Mmax_1[`MANTISSA-1:0], pipe_1[4:0], MminS_1[`MANTISSA-1:0]} ; +assign pipe_4 = {pipe_3[2*`EXPONENT+ 2*`MANTISSA + 9:`MANTISSA+1], Mmin_3[`MANTISSA:0]} ; +assign pipe_6 = {pipe_5[`DWIDTH+`EXPONENT+11], Shift_5[4:0], pipe_5[`DWIDTH+`EXPONENT+10:`DWIDTH+1], SumS_5[`DWIDTH:0]} ; +assign pipe_7 = {pipe_6[`DWIDTH+`EXPONENT+16:`DWIDTH+1], SumS_7[`DWIDTH:0]} ; +assign pipe_9 = {P_int[`DWIDTH-1:0], pipe_8[2], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT+`MANTISSA+9:`EXPONENT+`MANTISSA+5], EOF} ; + + always @ (posedge clk) begin + if(rst) begin + pipe_1 <= 0; + //pipe_2 <= 0; + pipe_3 <= 0; + //pipe_4 <= 0; + pipe_5 <= 0; + //pipe_6 <= 0; + //pipe_7 <= 0; + pipe_8 <= 0; + //pipe_9 <= 0; + end + else begin +/* PIPE_1: + [2*`EXPONENT + 2*`DWIDTH + 5] Opout_0 + [2*`EXPONENT + 2*`DWIDTH + 4: 2*`EXPONENT +`DWIDTH + 6] A_out0 + [2*`EXPONENT +`DWIDTH + 5 : 2*`EXPONENT +7] Bout_0 + [2*`EXPONENT +6] Sa_0 + [2*`EXPONENT +5] Sb_0 + [2*`EXPONENT +4 : 5] ShiftDet_0 + [4:0] Input Exc +*/ + pipe_1 <= {Opout_0, Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Sa_0, Sb_0, ShiftDet_0[2*`EXPONENT -1:0], InputExc_0[4:0]} ; +/* PIPE_2 +[2*`EXPONENT+ 2*`MANTISSA + 8] operation +[2*`EXPONENT+ 2*`MANTISSA + 7] Sa_0 +[2*`EXPONENT+ 2*`MANTISSA + 6] Sb_0 +[2*`EXPONENT+ 2*`MANTISSA + 5] MaxAB_0 +[2*`EXPONENT+ 2*`MANTISSA + 4:`EXPONENT+ 2*`MANTISSA + 5] CExp_0 +[`EXPONENT+ 2*`MANTISSA + 4 : 2*`MANTISSA + 5] Shift_0 +[2*`MANTISSA + 4:`MANTISSA + 5] Mmax_0 +[`MANTISSA + 4 : `MANTISSA] InputExc_0 +[`MANTISSA-1:0] MminS_1 +*/ + //pipe_2 <= {pipe_1[2*`EXPONENT + 2*`DWIDTH + 5], pipe_1[2*`EXPONENT +6:2*`EXPONENT +5], MaxAB_1, CExp_1[`EXPONENT-1:0], Shift_1[`EXPONENT-1:0], Mmax_1[`MANTISSA-1:0], pipe_1[4:0], MminS_1[`MANTISSA-1:0]} ; +/* PIPE_3 +[2*`EXPONENT+ 2*`MANTISSA + 9] operation +[2*`EXPONENT+ 2*`MANTISSA + 8] Sa_0 +[2*`EXPONENT+ 2*`MANTISSA + 7] Sb_0 +[2*`EXPONENT+ 2*`MANTISSA + 6] MaxAB_0 +[2*`EXPONENT+ 2*`MANTISSA + 5:`EXPONENT+ 2*`MANTISSA + 6] CExp_0 +[`EXPONENT+ 2*`MANTISSA + 5 : 2*`MANTISSA + 6] Shift_0 +[2*`MANTISSA + 5:`MANTISSA + 6] Mmax_0 +[`MANTISSA + 5 : `MANTISSA + 1] InputExc_0 +[`MANTISSA:0] MminS_2 +*/ + pipe_3 <= {pipe_2[2*`EXPONENT+ 2*`MANTISSA + 8:`MANTISSA], MminS_2[`MANTISSA:0]} ; +/* PIPE_4 +[2*`EXPONENT+ 2*`MANTISSA + 9] operation +[2*`EXPONENT+ 2*`MANTISSA + 8] Sa_0 +[2*`EXPONENT+ 2*`MANTISSA + 7] Sb_0 +[2*`EXPONENT+ 2*`MANTISSA + 6] MaxAB_0 +[2*`EXPONENT+ 2*`MANTISSA + 5:`EXPONENT+ 2*`MANTISSA + 6] CExp_0 +[`EXPONENT+ 2*`MANTISSA + 5 : 2*`MANTISSA + 6] Shift_0 +[2*`MANTISSA + 5:`MANTISSA + 6] Mmax_0 +[`MANTISSA + 5 : `MANTISSA + 1] InputExc_0 +[`MANTISSA:0] MminS_3 +*/ + //pipe_4 <= {pipe_3[2*`EXPONENT+ 2*`MANTISSA + 9:`MANTISSA+1], Mmin_3[`MANTISSA:0]} ; +/* PIPE_5 : +[`DWIDTH+ `EXPONENT + 11] operation +[`DWIDTH+ `EXPONENT + 10] PSgn_4 +[`DWIDTH+ `EXPONENT + 9] Opr_4 +[`DWIDTH+ `EXPONENT + 8] Sa_0 +[`DWIDTH+ `EXPONENT + 7] Sb_0 +[`DWIDTH+ `EXPONENT + 6] MaxAB_0 +[`DWIDTH+ `EXPONENT + 5 :`DWIDTH+6] CExp_0 +[`DWIDTH+5:`DWIDTH+1] InputExc_0 +[`DWIDTH:0] Sum_4 +*/ + pipe_5 <= {pipe_4[2*`EXPONENT+ 2*`MANTISSA + 9], PSgn_4, Opr_4, pipe_4[2*`EXPONENT+ 2*`MANTISSA + 8:`EXPONENT+ 2*`MANTISSA + 6], pipe_4[`MANTISSA+5:`MANTISSA+1], Sum_4[`DWIDTH:0]} ; +/* PIPE_6 : +[`DWIDTH+ `EXPONENT + 16] operation +[`DWIDTH+ `EXPONENT + 15:`DWIDTH+ `EXPONENT + 11] Shift_5 +[`DWIDTH+ `EXPONENT + 10] PSgn_4 +[`DWIDTH+ `EXPONENT + 9] Opr_4 +[`DWIDTH+ `EXPONENT + 8] Sa_0 +[`DWIDTH+ `EXPONENT + 7] Sb_0 +[`DWIDTH+ `EXPONENT + 6] MaxAB_0 +[`DWIDTH+ `EXPONENT + 5 :`DWIDTH+6] CExp_0 +[`DWIDTH+5:`DWIDTH+1] InputExc_0 +[`DWIDTH:0] Sum_4 +*/ + //pipe_6 <= {pipe_5[`DWIDTH+`EXPONENT+11], Shift_5[4:0], pipe_5[`DWIDTH+`EXPONENT+10:`DWIDTH+1], SumS_5[`DWIDTH:0]} ; +/* PIPE_7 : +[`DWIDTH+ `EXPONENT + 16] operation +[`DWIDTH+ `EXPONENT + 15:`DWIDTH+ `EXPONENT + 11] Shift_5 +[`DWIDTH+ `EXPONENT + 10] PSgn_4 +[`DWIDTH+ `EXPONENT + 9] Opr_4 +[`DWIDTH+ `EXPONENT + 8] Sa_0 +[`DWIDTH+ `EXPONENT + 7] Sb_0 +[`DWIDTH+ `EXPONENT + 6] MaxAB_0 +[`DWIDTH+ `EXPONENT + 5 :`DWIDTH+6] CExp_0 +[`DWIDTH+5:`DWIDTH+1] InputExc_0 +[`DWIDTH:0] Sum_4 +*/ + //pipe_7 <= {pipe_6[`DWIDTH+`EXPONENT+16:`DWIDTH+1], SumS_7[`DWIDTH:0]} ; +/* PIPE_8: +[2*`EXPONENT + `MANTISSA + 15] FG_8 +[2*`EXPONENT + `MANTISSA + 14] operation +[2*`EXPONENT + `MANTISSA + 13] PSgn_4 +[2*`EXPONENT + `MANTISSA + 12] Sa_0 +[2*`EXPONENT + `MANTISSA + 11] Sb_0 +[2*`EXPONENT + `MANTISSA + 10] MaxAB_0 +[2*`EXPONENT + `MANTISSA + 9:`EXPONENT + `MANTISSA + 10] CExp_0 +[`EXPONENT + `MANTISSA + 9:`EXPONENT + `MANTISSA + 5] InputExc_8 +[`EXPONENT + `MANTISSA + 4 :`EXPONENT + 5] NormM_8 +[`EXPONENT + 4 :4] NormE_8 +[3] ZeroSum_8 +[2] NegE_8 +[1] R_8 +[0] S_8 +*/ + pipe_8 <= {FG_8, pipe_7[`DWIDTH+`EXPONENT+16], pipe_7[`DWIDTH+`EXPONENT+10], pipe_7[`DWIDTH+`EXPONENT+8:`DWIDTH+1], NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8} ; +/* pipe_9: +[`DWIDTH + 8 :9] P_int +[8] NegE_8 +[7] R_8 +[6] S_8 +[5:1] InputExc_8 +[0] EOF +*/ + //pipe_9 <= {P_int[`DWIDTH-1:0], pipe_8[2], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT+`MANTISSA+9:`EXPONENT+`MANTISSA+5], EOF} ; + end + end + +endmodule + + +// +// Description: The pre-alignment module is responsible for taking the inputs +// apart and checking the parts for exceptions. +// The exponent difference is also calculated in this module. +// + + +module FPAddSub_PrealignModule( + A, + B, + operation, + Sa, + Sb, + ShiftDet, + InputExc, + Aout, + Bout, + Opout + ); + + // Input ports + input [`DWIDTH-1:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] B ; // Input B, a 32-bit floating point number + input operation ; + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [2*`EXPONENT-1:0] ShiftDet ; + output [4:0] InputExc ; // Input numbers are exceptions + output [`DWIDTH-2:0] Aout ; + output [`DWIDTH-2:0] Bout ; + output Opout ; + + // Internal signals // If signal is high... + wire ANaN ; // A is a NaN (Not-a-Number) + wire BNaN ; // B is a NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`EXPONENT-1:0] DAB ; // ExpA - ExpB + wire [`EXPONENT-1:0] DBA ; // ExpB - ExpA + + assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + + // Put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + + //assign DAB = (A[30:23] - B[30:23]) ; + //assign DBA = (B[30:23] - A[30:23]) ; + assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1'b1) ; + assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1'b1) ; + + assign Sa = A[`DWIDTH-1] ; // A's sign bit + assign Sb = B[`DWIDTH-1] ; // B's sign bit + assign ShiftDet = {DBA[`EXPONENT-1:0], DAB[`EXPONENT-1:0]} ; // Shift data + assign Opout = operation ; + assign Aout = A[`DWIDTH-2:0] ; + assign Bout = B[`DWIDTH-2:0] ; + +endmodule + + +// +// Description: The alignment module determines the larger input operand and +// sets the mantissas, shift and common exponent accordingly. +// + + +module FPAddSub_AlignModule ( + A, + B, + ShiftDet, + CExp, + MaxAB, + Shift, + Mmin, + Mmax + ); + + // Input ports + input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-2:0] B ; // Input B, a 32-bit floating point number + input [2*`EXPONENT-1:0] ShiftDet ; + + // Output ports + output [`EXPONENT-1:0] CExp ; // Common Exponent + output MaxAB ; // Incidates larger of A and B (0/A, 1/B) + output [`EXPONENT-1:0] Shift ; // Number of steps to smaller mantissa shift right + output [`MANTISSA-1:0] Mmin ; // Smaller mantissa + output [`MANTISSA-1:0] Mmax ; // Larger mantissa + + // Internal signals + //wire BOF ; // Check for shifting overflow if B is larger + //wire AOF ; // Check for shifting overflow if A is larger + + assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]) ; + //assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits + //assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits + + // Determine final shift value + //assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ; + + assign Shift = MaxAB ? ShiftDet[2*`EXPONENT-1:`EXPONENT] : ShiftDet[`EXPONENT-1:0] ; + + // Take out smaller mantissa and append shift space + assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0] ; + + // Take out larger mantissa + assign Mmax = MaxAB ? B[`MANTISSA-1:0]: A[`MANTISSA-1:0] ; + + // Common exponent + assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]) ; + +endmodule + + +// Description: Alignment shift stage 1, performs 16|12|8|4 shift +// + + +// ONLY THIS MODULE IS HARDCODED for half precision fp16 and bfloat16 +module FPAddSub_AlignShift1( + //bf16, + MminP, + Shift, + Mmin + ); + + // Input ports + //input bf16; + input [`MANTISSA-1:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bits + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + + wire bf16; + `ifdef BFLOAT16 + assign bf16 = 1'b1; + `else + assign bf16 = 1'b0; + `endif + + // Internal signals + reg [`MANTISSA:0] Lvl1; + reg [`MANTISSA:0] Lvl2; + wire [2*`MANTISSA+1:0] Stage1; + integer i; // Loop variable + + always @(*) begin + if (bf16 == 1'b1) begin +//hardcoding for bfloat16 + //For bfloat16, we can shift the mantissa by a max of 7 bits since mantissa has a width of 7. + //Hence if either, bit[3]/bit[4]/bit[5]/bit[6]/bit[7] is 1, we can make it 0. This corresponds to bits [5:1] in our updated shift which doesn't contain last 2 bits. + //Lvl1 <= (Shift[1]|Shift[2]|Shift[3]|Shift[4]|Shift[5]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width + Lvl1 <= (|Shift[`EXPONENT-3:1]) ? 11'd0 : {1'b1, MminP}; // MANTISSA + 1 width + end + else begin + //for half precision fp16, 10 bits can be shifted. Hence, only shifts till 10 (01010)can be made. + Lvl1 <= Shift[2] ? 11'd0 : {1'b1, MminP}; + end + end + + assign Stage1 = {Lvl1, Lvl1}; //2*MANTISSA + 2 width + + always @(*) begin // Rotate {0 | 4 } bits + if(bf16 == 1'b1) begin + case (Shift[0]) + // Rotate by 0 + 1'b0: Lvl2 <= Stage1[`MANTISSA:0]; + // Rotate by 4 + 1'b1: Lvl2 <= Stage1[`MANTISSA+4:4]; + default: Lvl2 <= Stage1[`MANTISSA+4:4]; + endcase + end + else begin + case (Shift[1:0]) // Rotate {0 | 4 | 8} bits + // Rotate by 0 + 2'b00: Lvl2 <= Stage1[`MANTISSA:0]; + // Rotate by 4 + 2'b01: Lvl2 <= Stage1[`MANTISSA+4:4]; + // Rotate by 8 + 2'b10: Lvl2 <= Stage1[`MANTISSA+8:8]; + // Rotate by 12 + 2'b11: Lvl2[`MANTISSA: 0] <= 0; + default: Lvl2[`MANTISSA: 0] <= 0; + endcase + end + end + + // Assign output to next shift stage + assign Mmin = Lvl2; + +endmodule + + +// Description: Alignment shift stage 2, performs 3|2|1 shift +// + + +module FPAddSub_AlignShift2( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`MANTISSA:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [1:0] Shift ; // Shift amount. Last 2 bits + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + // Internal Signal + reg [`MANTISSA:0] Lvl3; + wire [2*`MANTISSA+1:0] Stage2; + integer j; // Loop variable + + assign Stage2 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl3 <= Stage2[`MANTISSA:0]; + // Rotate by 1 + 2'b01: Lvl3 <= Stage2[`MANTISSA+1:1]; + // Rotate by 2 + 2'b10: Lvl3 <= Stage2[`MANTISSA+2:2]; + // Rotate by 3 + 2'b11: Lvl3 <= Stage2[`MANTISSA+3:3]; + default: Lvl3 <= Stage2[`MANTISSA+3:3]; + endcase + end + + // Assign output + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + + +// +// Description: Module that executes the addition or subtraction on mantissas. +// + + +module FPAddSub_ExecutionModule( + Mmax, + Mmin, + Sa, + Sb, + MaxAB, + OpMode, + Sum, + PSgn, + Opr + ); + + // Input ports + input [`MANTISSA-1:0] Mmax ; // The larger mantissa + input [`MANTISSA:0] Mmin ; // The smaller mantissa + input Sa ; // Sign bit of larger number + input Sb ; // Sign bit of smaller number + input MaxAB ; // Indicates the larger number (0/A, 1/B) + input OpMode ; // Operation to be performed (0/Add, 1/Sub) + + // Output ports + output [`DWIDTH:0] Sum ; // The result of the operation + output PSgn ; // The sign for the result + output Opr ; // The effective (performed) operation + + wire [`EXPONENT-1:0]temp_1; + + assign Opr = (OpMode^Sa^Sb); // Resolve sign to determine operation + assign temp_1 = 0; + // Perform effective operation +//SAMIDH_UNSURE 5--> 8 + + assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, temp_1} - {Mmin, temp_1}) : ({1'b1, Mmax, temp_1} + {Mmin, temp_1}) ; + + // Assign result sign + assign PSgn = (MaxAB ? Sb : Sa) ; + +endmodule + + +// +// Description: Determine the normalization shift amount and perform 16-shift +// + + +module FPAddSub_NormalizeModule( + Sum, + Mmin, + Shift + ); + + // Input ports + input [`DWIDTH:0] Sum ; // Mantissa sum including hidden 1 and GRS + + // Output ports + output [`DWIDTH:0] Mmin ; // Mantissa after 16|0 shift + output [4:0] Shift ; // Shift amount + //Changes in this doesn't matter since even Bfloat16 can't go beyond 7 shift to the mantissa (only 3 bits valid here) + // Determine normalization shift amount by finding leading nought + assign Shift = ( + Sum[16] ? 5'b00000 : + Sum[15] ? 5'b00001 : + Sum[14] ? 5'b00010 : + Sum[13] ? 5'b00011 : + Sum[12] ? 5'b00100 : + Sum[11] ? 5'b00101 : + Sum[10] ? 5'b00110 : + Sum[9] ? 5'b00111 : + Sum[8] ? 5'b01000 : + Sum[7] ? 5'b01001 : + Sum[6] ? 5'b01010 : + Sum[5] ? 5'b01011 : + Sum[4] ? 5'b01100 : 5'b01101 + // Sum[19] ? 5'b01101 : + // Sum[18] ? 5'b01110 : + // Sum[17] ? 5'b01111 : + // Sum[16] ? 5'b10000 : + // Sum[15] ? 5'b10001 : + // Sum[14] ? 5'b10010 : + // Sum[13] ? 5'b10011 : + // Sum[12] ? 5'b10100 : + // Sum[11] ? 5'b10101 : + // Sum[10] ? 5'b10110 : + // Sum[9] ? 5'b10111 : + // Sum[8] ? 5'b11000 : + // Sum[7] ? 5'b11001 : 5'b11010 + ); + + reg [`DWIDTH:0] Lvl1; + + always @(*) begin + // Rotate by 16? + Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum; + end + + // Assign outputs + assign Mmin = Lvl1; // Take out smaller mantissa + +endmodule + + +// Description: Normalization shift stage 1, performs 12|8|4|3|2|1|0 shift +// +//Hardcoding loop start and end values of i. To avoid ODIN limitations. i=`DWIDTH*2+1 wasn't working. + + +module FPAddSub_NormalizeShift1( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`DWIDTH:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [3:0] Shift ; // Shift amount + + // Output ports + output [`DWIDTH:0] Mmin ; // The smaller mantissa + + reg [`DWIDTH:0] Lvl2; + wire [2*`DWIDTH+1:0] Stage1; + reg [`DWIDTH:0] Lvl3; + wire [2*`DWIDTH+1:0] Stage2; + integer i; // Loop variable + + assign Stage1 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 4 | 8 | 12} bits + case (Shift[3:2]) + // Rotate by 0 + 2'b00: Lvl2 <= Stage1[`DWIDTH:0]; + // Rotate by 4 + 2'b01: Lvl2[16:0] <= Stage1[28:13]; + // Rotate by 8 + 2'b10: Lvl2[16:0] <= Stage1[24:9]; + // Rotate by 12 + 2'b11: Lvl2[16:0] <= Stage1[20:5]; + default: Lvl2[16:0] <= Stage1[20:5]; + endcase + end + + assign Stage2 = {Lvl2, Lvl2}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl3 <= Stage2[`DWIDTH:0]; + // Rotate by 1 + 2'b01: Lvl3[16:0] <= Stage2[31:16]; + // Rotate by 2 + 2'b10: Lvl3[16:0] <= Stage2[30:15]; + // Rotate by 3 + 2'b11: Lvl3[16:0] <= Stage2[29:14]; + default: Lvl3[16:0] <= Stage2[29:14]; + endcase + end + + // Assign outputs + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + + +// Description: Normalization shift stage 2, calculates post-normalization +// mantissa and exponent, as well as the bits used in rounding +// + + +module FPAddSub_NormalizeShift2( + PSSum, + CExp, + Shift, + NormM, + NormE, + ZeroSum, + NegE, + R, + S, + FG + ); + + // Input ports + input [`DWIDTH:0] PSSum ; // The Pre-Shift-Sum + input [`EXPONENT-1:0] CExp ; + input [4:0] Shift ; // Amount to be shifted + + // Output ports + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output [`EXPONENT:0] NormE ; // Adjusted exponent + output ZeroSum ; // Zero flag + output NegE ; // Flag indicating negative exponent + output R ; // Round bit + output S ; // Final sticky bit + output FG ; + + // Internal signals + wire MSBShift ; // Flag indicating that a second shift is needed + wire [`EXPONENT:0] ExpOF ; // MSB set in sum indicates overflow + wire [`EXPONENT:0] ExpOK ; // MSB not set, no adjustment + + // Calculate normalized exponent and mantissa, check for all-zero sum + assign MSBShift = PSSum[`DWIDTH] ; // Check MSB in unnormalized sum + assign ZeroSum = ~|PSSum ; // Check for all zero sum + assign ExpOK = CExp - Shift ; // Adjust exponent for new normalized mantissa + assign NegE = ExpOK[`EXPONENT] ; // Check for exponent overflow + assign ExpOF = CExp - Shift + 1'b1 ; // If MSB set, add one to exponent(x2) + assign NormE = MSBShift ? ExpOF : ExpOK ; // Check for exponent overflow + assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1] ; // The new, normalized mantissa + + // Also need to compute sticky and round bits for the rounding stage + assign FG = PSSum[`EXPONENT] ; + assign R = PSSum[`EXPONENT-1] ; + assign S = |PSSum[`EXPONENT-2:0] ; + +endmodule + + +// Description: Performs 'Round to nearest, tie to even'-rounding on the +// normalized mantissa according to the G, R, S bits. Calculates +// final result and checks for exponent overflow. +// + + +module FPAddSub_RoundModule( + ZeroSum, + NormE, + NormM, + R, + S, + G, + Sa, + Sb, + Ctrl, + MaxAB, + Z, + EOF + ); + + // Input ports + input ZeroSum ; // Sum is zero + input [`EXPONENT:0] NormE ; // Normalized exponent + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input R ; // Round bit + input S ; // Sticky bit + input G ; + input Sa ; // A's sign bit + input Sb ; // B's sign bit + input Ctrl ; // Control bit (operation) + input MaxAB ; + + // Output ports + output [`DWIDTH-1:0] Z ; // Final result + output EOF ; + + // Internal signals + wire [`MANTISSA:0] RoundUpM ; // Rounded up sum with room for overflow + wire [`MANTISSA-1:0] RoundM ; // The final rounded sum + wire [`EXPONENT:0] RoundE ; // Rounded exponent (note extra bit due to poential overflow ) + wire RoundUp ; // Flag indicating that the sum should be rounded up + wire FSgn; + wire ExpAdd ; // May have to add 1 to compensate for overflow + wire RoundOF ; // Rounding overflow + + wire [`EXPONENT:0]temp_2; + assign temp_2 = 0; + // The cases where we need to round upwards (= adding one) in Round to nearest, tie to even + assign RoundUp = (G & ((R | S) | NormM[0])) ; + + // Note that in the other cases (rounding down), the sum is already 'rounded' + assign RoundUpM = (NormM + 1'b1) ; // The sum, rounded up by 1 + assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM) ; // Compute final mantissa + assign RoundOF = RoundUp & RoundUpM[`MANTISSA] ; // Check for overflow when rounding up + + // Calculate post-rounding exponent + assign ExpAdd = (RoundOF ? 1'b1 : 1'b0) ; // Add 1 to exponent to compensate for overflow + assign RoundE = ZeroSum ? temp_2 : (NormE + ExpAdd) ; // Final exponent + + // If zero, need to determine sign according to rounding + assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ; + + // Assign final result + assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]} ; + + // Indicate exponent overflow + assign EOF = RoundE[`EXPONENT]; + +endmodule + + +// +// Description: Check the final result for exception conditions and set +// flags accordingly. +// + + +module FPAddSub_ExceptionModule( + Z, + NegE, + R, + S, + InputExc, + EOF, + P, + Flags + ); + + // Input ports + input [`DWIDTH-1:0] Z ; // Final product + input NegE ; // Negative exponent? + input R ; // Round bit + input S ; // Sticky bit + input [4:0] InputExc ; // Exceptions in inputs A and B + input EOF ; + + // Output ports + output [`DWIDTH-1:0] P ; // Final result + output [4:0] Flags ; // Exception flags + + // Internal signals + wire Overflow ; // Overflow flag + wire Underflow ; // Underflow flag + wire DivideByZero ; // Divide-by-Zero flag (always 0 in Add/Sub) + wire Invalid ; // Invalid inputs or result + wire Inexact ; // Result is inexact because of rounding + + // Exception flags + + // Result is too big to be represented + assign Overflow = EOF | InputExc[1] | InputExc[0] ; + + // Result is too small to be represented + assign Underflow = NegE & (R | S); + + // Infinite result computed exactly from finite operands + assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0]; + + // Invalid inputs or operation + assign Invalid = |(InputExc[4:2]) ; + + // Inexact answer due to rounding, overflow or underflow + assign Inexact = (R | S) | Overflow | Underflow; + + // Put pieces together to form final result + assign P = Z ; + + // Collect exception flags + assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact} ; + +endmodule +module FPMult_16( + clk, + rst, + a, + b, + result, + flags + ); + + // Input Ports + input clk ; // Clock + input rst ; // Reset signal + input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number + + // Output ports + output [`DWIDTH-1:0] result ; // Product, result of the operation, 32-bit FP number + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Internal signals + wire [`DWIDTH-1:0] Z_int ; // Product, result of the operation, 32-bit FP number + wire [4:0] Flags_int ; // Flags indicating exceptions according to IEEE754 + + wire Sa ; // A's sign + wire Sb ; // B's sign + wire Sp ; // Product sign + wire [`EXPONENT-1:0] Ea ; // A's exponent + wire [`EXPONENT-1:0] Eb ; // B's exponent + wire [2*`MANTISSA+1:0] Mp ; // Product mantissa + wire [4:0] InputExc ; // Exceptions in inputs + wire [`MANTISSA-1:0] NormM ; // Normalized mantissa + wire [`EXPONENT:0] NormE ; // Normalized exponent + wire [`MANTISSA:0] RoundM ; // Normalized mantissa + wire [`EXPONENT:0] RoundE ; // Normalized exponent + wire [`MANTISSA:0] RoundMP ; // Normalized mantissa + wire [`EXPONENT:0] RoundEP ; // Normalized exponent + wire GRS ; + + //reg [63:0] pipe_0; // Pipeline register Input->Prep + reg [2*`DWIDTH-1:0] pipe_0; // Pipeline register Input->Prep + + //reg [92:0] pipe_1; // Pipeline register Prep->Execute + //reg [3*`MANTISSA+2*`EXPONENT+7:0] pipe_1; // Pipeline register Prep->Execute + reg [3*`MANTISSA+2*`EXPONENT+18:0] pipe_1; + + //reg [38:0] pipe_2; // Pipeline register Execute->Normalize + reg [`MANTISSA+`EXPONENT+7:0] pipe_2; // Pipeline register Execute->Normalize + + //reg [72:0] pipe_3; // Pipeline register Normalize->Round + reg [2*`MANTISSA+2*`EXPONENT+10:0] pipe_3; // Pipeline register Normalize->Round + + //reg [36:0] pipe_4; // Pipeline register Round->Output + reg [`DWIDTH+4:0] pipe_4; // Pipeline register Round->Output + + assign result = pipe_4[`DWIDTH+4:5] ; + assign flags = pipe_4[4:0] ; + + // Prepare the operands for alignment and check for exceptions + FPMult_PrepModule PrepModule(clk, rst, pipe_0[2*`DWIDTH-1:`DWIDTH], pipe_0[`DWIDTH-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]) ; + + // Perform (unsigned) mantissa multiplication + FPMult_ExecuteModule ExecuteModule(pipe_1[3*`MANTISSA+`EXPONENT*2+7:2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7:2*`MANTISSA+7], pipe_1[2*`MANTISSA+6:5], pipe_1[2*`MANTISSA+2*`EXPONENT+6:2*`MANTISSA+`EXPONENT+7], pipe_1[2*`MANTISSA+`EXPONENT+6:2*`MANTISSA+7], pipe_1[2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7], Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0], GRS) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + FPMult_NormalizeModule NormalizeModule(pipe_2[`MANTISSA-1:0], pipe_2[`MANTISSA+`EXPONENT:`MANTISSA], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + //FPMult_RoundModule RoundModule(pipe_3[47:24], pipe_3[23:0], pipe_3[65:57], pipe_3[56:48], pipe_3[66], pipe_3[67], pipe_3[72:68], Z_int[31:0], Flags_int[4:0]) ; + FPMult_RoundModule RoundModule(pipe_3[2*`MANTISSA+1:`MANTISSA+1], pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+2*`EXPONENT+3:2*`MANTISSA+`EXPONENT+3], pipe_3[2*`MANTISSA+`EXPONENT+2:2*`MANTISSA+2], pipe_3[2*`MANTISSA+2*`EXPONENT+4], pipe_3[2*`MANTISSA+2*`EXPONENT+5], pipe_3[2*`MANTISSA+2*`EXPONENT+10:2*`MANTISSA+2*`EXPONENT+6], Z_int[`DWIDTH-1:0], Flags_int[4:0]) ; + +//adding always@ (*) instead of posedge clock to make design combinational + always @ (*) begin + if(rst) begin + pipe_0 = 0; + pipe_1 = 0; + pipe_2 = 0; + pipe_3 = 0; + pipe_4 = 0; + end + else begin + /* PIPE 0 + [2*`DWIDTH-1:`DWIDTH] A + [`DWIDTH-1:0] B + */ + pipe_0 = {a, b} ; + + + /* PIPE 1 + [2*`EXPONENT+3*`MANTISSA + 18: 2*`EXPONENT+2*`MANTISSA + 18] //pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH] , mantissa of A + [2*`EXPONENT+2*`MANTISSA + 17 :2*`EXPONENT+2*`MANTISSA + 9] // pipe_0[8:0] + [2*`EXPONENT+2*`MANTISSA + 8] Sa + [2*`EXPONENT+2*`MANTISSA + 7] Sb + [2*`EXPONENT+2*`MANTISSA + 6:`EXPONENT+2*`MANTISSA+7] Ea + [`EXPONENT +2*`MANTISSA+6:2*`MANTISSA+7] Eb + [2*`MANTISSA+1+5:5] Mp + [4:0] InputExc + */ + //pipe_1 <= {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[`MANTISSA_MUL_SPLIT_LSB-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA-1:0], InputExc[4:0]} ; + pipe_1 = {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[8:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]} ; + + /* PIPE 2 + [`EXPONENT + `MANTISSA + 7:`EXPONENT + `MANTISSA + 3] InputExc + [`EXPONENT + `MANTISSA + 2] GRS + [`EXPONENT + `MANTISSA + 1] Sp + [`EXPONENT + `MANTISSA:`MANTISSA] NormE + [`MANTISSA-1:0] NormM + */ + pipe_2 = {pipe_1[4:0], GRS, Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0]} ; + /* PIPE 3 + [2*`EXPONENT+2*`MANTISSA+10:2*`EXPONENT+2*`MANTISSA+6] InputExc + [2*`EXPONENT+2*`MANTISSA+5] GRS + [2*`EXPONENT+2*`MANTISSA+4] Sp + [2*`EXPONENT+2*`MANTISSA+3:`EXPONENT+2*`MANTISSA+3] RoundE + [`EXPONENT+2*`MANTISSA+2:2*`MANTISSA+2] RoundEP + [2*`MANTISSA+1:`MANTISSA+1] RoundM + [`MANTISSA:0] RoundMP + */ + pipe_3 = {pipe_2[`EXPONENT+`MANTISSA+7:`EXPONENT+`MANTISSA+1], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]} ; + /* PIPE 4 + [`DWIDTH+4:5] Z + [4:0] Flags + */ + pipe_4 = {Z_int[`DWIDTH-1:0], Flags_int[4:0]} ; + end + end + +endmodule + + + +module FPMult_PrepModule ( + clk, + rst, + a, + b, + Sa, + Sb, + Ea, + Eb, + Mp, + InputExc + ); + + // Input ports + input clk ; + input rst ; + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [`EXPONENT-1:0] Ea ; // A's exponent + output [`EXPONENT-1:0] Eb ; // B's exponent + output [2*`MANTISSA+1:0] Mp ; // Mantissa product + output [4:0] InputExc ; // Input numbers are exceptions + + // Internal signals // If signal is high... + wire ANaN ; // A is a signalling NaN + wire BNaN ; // B is a signalling NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`MANTISSA-1:0] Ma; + wire [`MANTISSA-1:0] Mb; + + assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + + // Check for any exceptions and put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + //assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ; + + // Take input numbers apart + assign Sa = a[`DWIDTH-1] ; // A's sign + assign Sb = b[`DWIDTH-1] ; // B's sign + assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception + assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception +// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB]; + // assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB]; + + + + //assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ; + assign Mp = ({1'b1,a[`MANTISSA-1:0]}*{1'b1, b[`MANTISSA-1:0]}) ; + + + //We multiply part of the mantissa here + //Full mantissa of A + //Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B + // wire [`ACTUAL_MANTISSA-1:0] inp_A; + // wire [`ACTUAL_MANTISSA-1:0] inp_B; + // assign inp_A = {1'b1, Ma}; + // assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp)); +endmodule + + +module FPMult_ExecuteModule( + a, + b, + MpC, + Ea, + Eb, + Sa, + Sb, + Sp, + NormE, + NormM, + GRS + ); + + // Input ports + input [`MANTISSA-1:0] a ; + input [2*`EXPONENT:0] b ; + input [2*`MANTISSA+1:0] MpC ; + input [`EXPONENT-1:0] Ea ; // A's exponent + input [`EXPONENT-1:0] Eb ; // B's exponent + input Sa ; // A's sign + input Sb ; // B's sign + + // Output ports + output Sp ; // Product sign + output [`EXPONENT:0] NormE ; // Normalized exponent + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output GRS ; + + wire [2*`MANTISSA+1:0] Mp ; + + assign Sp = (Sa ^ Sb) ; // Equal signs give a positive product + + // wire [`ACTUAL_MANTISSA-1:0] inp_a; + // wire [`ACTUAL_MANTISSA-1:0] inp_b; + // assign inp_a = {1'b1, a}; + // assign inp_b = {{(`MANTISSA-`MANTISSA_MUL_SPLIT_LSB){1'b0}}, 1'b0, b}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_a), .B(inp_b), .TC(1'b0), .PRODUCT(Mp_temp)); + // DW01_add #(2*`ACTUAL_MANTISSA) u_add(.A(Mp_temp), .B(MpC<<`MANTISSA_MUL_SPLIT_LSB), .CI(1'b0), .SUM(Mp), .CO()); + + //assign Mp = (MpC<<(2*`EXPONENT+1)) + ({4'b0001, a[`MANTISSA-1:0]}*{1'b0, b[2*`EXPONENT:0]}) ; + assign Mp = MpC; + + + assign NormM = (Mp[2*`MANTISSA+1] ? Mp[2*`MANTISSA:`MANTISSA+1] : Mp[2*`MANTISSA-1:`MANTISSA]); // Check for overflow + assign NormE = (Ea + Eb + Mp[2*`MANTISSA+1]); // If so, increment exponent + + assign GRS = ((Mp[`MANTISSA]&(Mp[`MANTISSA+1]))|(|Mp[`MANTISSA-1:0])) ; + +endmodule + +module FPMult_NormalizeModule( + NormM, + NormE, + RoundE, + RoundEP, + RoundM, + RoundMP + ); + + // Input Ports + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input [`EXPONENT:0] NormE ; // Normalized exponent + + // Output Ports + output [`EXPONENT:0] RoundE ; + output [`EXPONENT:0] RoundEP ; + output [`MANTISSA:0] RoundM ; + output [`MANTISSA:0] RoundMP ; + +// EXPONENT = 5 +// EXPONENT -1 = 4 +// NEED to subtract 2^4 -1 = 15 + +wire [`EXPONENT-1 : 0] bias; + +assign bias = ((1'b1 << (`EXPONENT -1'b1)) -1'b1); + + assign RoundE = NormE - bias ; + assign RoundEP = NormE - bias -1'b1 ; + assign RoundM = NormM ; + assign RoundMP = NormM ; + +endmodule + +module FPMult_RoundModule( + RoundM, + RoundMP, + RoundE, + RoundEP, + Sp, + GRS, + InputExc, + Z, + Flags + ); + + // Input Ports + input [`MANTISSA:0] RoundM ; // Normalized mantissa + input [`MANTISSA:0] RoundMP ; // Normalized exponent + input [`EXPONENT:0] RoundE ; // Normalized mantissa + 1 + input [`EXPONENT:0] RoundEP ; // Normalized exponent + 1 + input Sp ; // Product sign + input GRS ; + input [4:0] InputExc ; + + // Output Ports + output [`DWIDTH-1:0] Z ; // Final product + output [4:0] Flags ; + + // Internal Signals + wire [`EXPONENT:0] FinalE ; // Rounded exponent + wire [`MANTISSA:0] FinalM; + wire [`MANTISSA:0] PreShiftM; + + assign PreShiftM = GRS ? RoundMP : RoundM ; // Round up if R and (G or S) + + // Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow) + assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]) ; + + assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done + + assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]} ; // Putting the pieces together + assign Flags = InputExc[4:0]; + +endmodule + +`endif + +module array_mux_2to1 #(parameter size = 10) (clk,reset,start,out,in0,in1,sel,out_data_available); + + input [size-1:0] in0, in1; + input sel,clk; + input reset,start; + output reg [size-1:0] out; + output reg out_data_available; + + always@(posedge clk) begin + if((reset==1'b1) || (start==1'b0)) begin + out <= 'd0; + out_data_available <= 0; + end + else begin + out <= (sel) ? in1 : in0; + out_data_available <= 1; + end + end + +endmodule + +module barrel_shifter_right ( + input clk, + input reset, + input start, + input [4:0] shift_amt, + input [5:0] significand, + output [5:0] shifted_sig, + output out_data_available +); + + //3-level distributed barrel shifter using 10 2:1 MUX array + + //level 0 + wire [6:0] out0; + wire out_data_available_arr_0; + + array_mux_2to1 #(.size(7)) M0 ( + .clk(clk), + .reset(reset), + .start(start), + .out(out0), + .in0({significand[5:0],1'b0}), + .in1({1'b0,significand[5:0]}), + .sel(shift_amt[0]), + .out_data_available(out_data_available_arr_0) + ); + + //level 1 + wire [8:0] out1; + wire out_data_available_arr_1; + + array_mux_2to1 #(.size(9)) M1 ( + .clk(clk), + .reset(reset), + .start(out_data_available_arr_0), + .out(out1), + .in0({out0[6:0],2'b0}), + .in1({2'b0,out0[6:0]}), + .sel(shift_amt[1]), + .out_data_available(out_data_available_arr_1) + ); + + //level 2 + wire [12:0] out2; + + array_mux_2to1 #(.size(13)) M2 ( + .clk(clk), + .reset(reset), + .start(out_data_available_arr_1), + .out(out2), + .in0({out1[8:0],4'b0}), + .in1({4'b0,out1[8:0]}), + .sel(shift_amt[2]), + .out_data_available(out_data_available) + ); + + //shifted significand + assign shifted_sig = (reset==1'b1) ? 6'd0 : out2[12:7]; + +endmodule + +module barrel_shifter_left ( + input clk, + input reset, + input start, + input [4:0] shift_amt, + input [5:0] significand, + output [5:0] shifted_sig, + output out_data_available +); + + //3-level distributed barrel shifter using 10 2:1 MUX array + + //level 0 + wire [6:0] out0; + wire out_data_available_arr_0; + + array_mux_2to1 #(.size(7)) M0 ( + .clk(clk), + .reset(reset), + .start(start), + .out(out0), + .in0({1'b0,significand[5:0]}), + .in1({significand[5:0],1'b0}), + .sel(shift_amt[0]), + .out_data_available(out_data_available_arr_0) + ); + + //level 1 + wire [8:0] out1; + wire out_data_available_arr_1; + + array_mux_2to1 #(.size(9)) M1 ( + .clk(clk), + .reset(reset), + .start(out_data_available_arr_0), + .out(out1), + .in0({2'b0,out0[6:0]}), + .in1({out0[6:0],2'b0}), + .sel(shift_amt[1]), + .out_data_available(out_data_available_arr_1) + ); + + //level 2 + wire [12:0] out2; + + array_mux_2to1 #(.size(13)) M2 ( + .clk(clk), + .reset(reset), + .start(out_data_available_arr_1), + .out(out2), + .in0({4'b0,out1[8:0]}), + .in1({out1[8:0],4'b0}), + .sel(shift_amt[2]), + .out_data_available(out_data_available) + ); + + //shifted significand + assign shifted_sig = (reset==1'b1) ? 6'd0 : out2[5:0]; + +endmodule + +module leading_zero_detector_6bit( + input clk, + input[5:0] a, + input reset, + input start, + output reg [2:0] position, + output reg is_valid, + output reg out_data_available +); + + wire[1:0] posi_upper, posi_lower; + wire valid_upper, valid_lower; + + reg[3:0] num_cycles; + + always@(posedge clk) begin + if((reset==1'b1) || (start==1'b0)) begin + num_cycles <= 0; + out_data_available <= 0; + end + else begin + if(num_cycles==`NUM_LZD_CYCLES) begin + out_data_available <= 1; + end + else begin + num_cycles <= num_cycles + 1'b1; + end + end + end + + leading_zero_detector_4bit lzd4_upper( + .clk(clk), + .reset(reset), + .start(start), + .a(a[5:2]), + .position(posi_upper), + .is_valid(valid_upper) + ); + + leading_zero_detector_4bit lzd4_lower( + .clk(clk), + .reset(reset), + .start(start), + .a({a[1:0],2'b00}), + .position(posi_lower), + .is_valid(valid_lower) + ); + + always@(posedge clk) begin + if((reset==1'b1) || (start==1'b0)) begin + is_valid <= 0; + position <= 3'd0; + end + else begin + is_valid <= valid_upper | valid_lower; + + position[2] <= ~valid_upper; + position[1] <= valid_upper ? posi_upper[1] : posi_lower[1]; + position[0] <= valid_upper ? posi_upper[0] : posi_lower[0]; + end + end + +endmodule + +module leading_zero_detector_4bit( + input clk, + input[3:0] a, + input reset, + input start, + output reg [1:0] position, + output reg is_valid +); + + wire posi_upper, posi_lower; + wire valid_upper, valid_lower; + + leading_zero_detector_2bit lzd2_upper( + .clk(clk), + .reset(reset), + .start(start), + .a(a[3:2]), + .position(posi_upper), + .is_valid(valid_upper) + ); + + leading_zero_detector_2bit lzd2_lower( + .clk(clk), + .reset(reset), + .start(start), + .a(a[1:0]), + .position(posi_lower), + .is_valid(valid_lower) + ); + + always@(posedge clk) begin + if((reset==1) || (start==0)) begin + is_valid <= 0; + end + else begin + is_valid <= valid_upper | valid_lower; + + position[1] <= ~valid_upper; + position[0] <= valid_upper ? posi_upper : posi_lower; + end + end + +endmodule + +module leading_zero_detector_2bit( + input clk, + input[1:0] a, + input reset, + input start, + output reg position, + output reg is_valid +); + + always@(posedge clk) begin + if((reset==1) || (start==0)) begin + is_valid <= 0; + end + else begin + is_valid <= a[1] | a[0]; + position <= ~a[1]; + end + end +endmodule + diff --git a/designs/koios/bwave_like.float.small/bwave_small_random.sv b/designs/koios/bwave_like.float.small/bwave_small_random.sv new file mode 100644 index 000000000..ee3e74c81 --- /dev/null +++ b/designs/koios/bwave_like.float.small/bwave_small_random.sv @@ -0,0 +1,257 @@ +/* +Randomize input to bwave_large +*/ + +`include "../../random_number_generator.sv" + +`define NUM_TILES 16 +`define NUM_LDPES 4 +`define DSPS_PER_LDPE 2 + +`define IN_PRECISION 16 +`define OUT_PRECISION 16 + +`define FLOAT_EXP 8 +`define FLOAT_MANTISA 7 +`define FLOAT_DWIDTH (`FLOAT_EXP+`FLOAT_MANTISA + 1) + +`define BFLOAT_EXP 5 +`define BFLOAT_MANTISA 5 +`define BFLOAT_DWIDTH (`BFLOAT_EXP + `BFLOAT_MANTISA + 1) +`define BFLOAT_MANTISA_WITH_LO (`BFLOAT_MANTISA+1) + + +`define DSPS_PER_SUB_LDPE 2 +`define SUB_LDPES_PER_LDPE (`DSPS_PER_LDPE/`DSPS_PER_SUB_LDPE) + +`define MULTS_PER_DSP 2 +`define DSP_X_AVA_INPUT_WIDTH 18 +`define LDPE_X_AVA_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) +`define DSP_Y_AVA_INPUT_WIDTH 19 +`define LDPE_Y_AVA_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH * `DSPS_PER_LDPE) + +`define DSP_AVA_OUTPUT_WIDTH 37 +`define LDPE_AVA_OUTPUT_WIDTH `DSP_AVA_OUTPUT_WIDTH + +`define DSP_USED_INPUT_WIDTH (`BFLOAT_MANTISA+1) + +`define LDPE_USED_INPUT_WIDTH (`FLOAT_DWIDTH * `DSPS_PER_LDPE) +`define SUB_LDPE_USED_INPUT_WIDTH (`BFLOAT_DWIDTH * `DSPS_PER_SUB_LDPE) +`define DSP_X_ZERO_PAD_INPUT_WIDTH (`DSP_X_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) +`define DSP_Y_ZERO_PAD_INPUT_WIDTH (`DSP_Y_AVA_INPUT_WIDTH - `DSP_USED_INPUT_WIDTH) + +`define DSP_USED_OUTPUT_WIDTH 27 +`define LDPE_USED_OUTPUT_WIDTH `DSP_USED_OUTPUT_WIDTH +`define DSP_ZERO_PAD_OUTPUT_WIDTH (`DSP_AVA_OUTPUT_WIDTH - `DSP_USED_OUTPUT_WIDTH) + +`define LDPES_PER_MRF 1 +`define DSPS_PER_MRF (`DSPS_PER_LDPE * `LDPES_PER_MRF) +`define MAT_BRAM_AWIDTH 10 +`define MAT_BRAM_DWIDTH 16 +`define MAT_BRAMS_PER_MRF_SUBSET 4 +`define SUBSETS_PER_MRF 1 +`define BRAMS_PER_MRF (`MAT_BRAMS_PER_MRF_SUBSET * `SUBSETS_PER_MRF) +`define MRF_AWIDTH (`MAT_BRAM_AWIDTH) +`define MRF_DWIDTH (`MAT_BRAM_DWIDTH * `MAT_BRAMS_PER_MRF_SUBSET) + +`define LDPES_PER_VRF 1 +`define DSPS_PER_VRF (`DSPS_PER_LDPE * `LDPES_PER_VRF) +`define VEC_BRAM_AWIDTH 10 +`define VEC_BRAM_DWIDTH 16 +`define BRAMS_PER_VRF 4 +`define VRF_AWIDTH `VEC_BRAM_AWIDTH +`define VRF_DWIDTH (`VEC_BRAM_DWIDTH * `BRAMS_PER_VRF) + +`define LDPES_PER_ORF 1 +`define OUTPUTS_PER_LDPE 1 +`define OUT_BRAM_AWIDTH 10 +`define OUT_BRAM_DWIDTH 16 +`define ORF_AWIDTH `OUT_BRAM_AWIDTH +`define OUT_DWIDTH 16 +`define ORF_DWIDTH 64 //64 + +`define MAX_VRF_DWIDTH 64 +`define DRAM_DWIDTH `VRF_DWIDTH //This is the max of mrf, vrf and orf dwidth +`define DRAM_AWIDTH `MRF_AWIDTH + +`define OPCODE_WIDTH 4 +`define TARGET_OP_WIDTH 7 + +`define INSTR_WIDTH (`OPCODE_WIDTH+`TARGET_OP_WIDTH+`DRAM_AWIDTH+`TARGET_OP_WIDTH+`VRF_AWIDTH + `VRF_AWIDTH) + +`define ACTIVATION 2'b00 +`define ELT_WISE_MULTIPLY 2'b10 +`define ELT_WISE_ADD 2'b01 +`define BYPASS 2'b11 + +`define RELU 2'b00 +`define TANH 2'b01 +`define SIGM 2'b10 +//OPCODES + +`define V_RD 0 +`define V_WR 1 +`define M_RD 2 +`define M_WR 3 //NEWLY ADDED +`define MV_MUL 4 +`define VV_ADD 5 +`define VV_SUB 6 //QUESTIONED +`define VV_PASS 7 +`define VV_MUL 8 +`define V_RELU 9 +`define V_SIGM 10 +`define V_TANH 11 +`define END_CHAIN 12 +//MEM_IDS + +`define VRF_0 0 +`define VRF_1 1 +`define VRF_2 2 +`define VRF_3 3 +`define VRF_4 4 +`define VRF_5 5 +`define VRF_6 6 +`define VRF_7 7 +`define VRF_8 8 +`define VRF_9 9 +`define VRF_10 10 +`define VRF_11 11 +`define VRF_12 12 +`define VRF_13 13 +`define VRF_14 14 +`define VRF_15 15 + +`define VRF_16 16 +`define VRF_17 17 +`define VRF_18 18 +`define VRF_19 19 +`define VRF_MUXED 20 +`define DRAM_MEM_ID 21 +`define MFU_0_DSTN_ID 22 +`define MFU_1_DSTN_ID 23 + +`define MRF_0 0 +`define MRF_1 1 +`define MRF_2 2 +`define MRF_3 3 +`define MRF_4 4 +`define MRF_5 5 +`define MRF_6 6 +`define MRF_7 7 +`define MRF_8 8 +`define MRF_9 9 +`define MRF_10 10 +`define MRF_11 11 +`define MRF_12 12 +`define MRF_13 13 +`define MRF_14 14 +`define MRF_15 15 +`define MRF_16 16 +`define MRF_17 17 +`define MRF_18 18 +`define MRF_19 19 +`define MRF_20 20 +`define MRF_21 21 +`define MRF_22 22 +`define MRF_23 23 +`define MRF_24 24 +`define MRF_25 25 +`define MRF_26 26 +`define MRF_27 27 +`define MRF_28 28 +`define MRF_29 29 +`define MRF_30 30 +`define MRF_31 31 +`define MRF_32 32 +`define MRF_33 33 +`define MRF_34 34 +`define MRF_35 35 +`define MRF_36 36 +`define MRF_37 37 +`define MRF_38 38 +`define MRF_39 39 +`define MRF_40 40 +`define MRF_41 41 +`define MRF_42 42 +`define MRF_43 43 +`define MRF_44 44 +`define MRF_45 45 +`define MRF_46 46 +`define MRF_47 47 +`define MRF_48 48 +`define MRF_49 49 +`define MRF_50 50 +`define MRF_51 51 +`define MRF_52 52 +`define MRF_53 53 +`define MRF_54 54 +`define MRF_55 55 +`define MRF_56 56 +`define MRF_57 57 +`define MRF_58 58 +`define MRF_59 59 +`define MRF_60 60 +`define MRF_61 61 +`define MRF_62 62 +`define MRF_63 63 + +`define MFU_0 0 +`define MFU_1 1 +`define INSTR_MEM_AWIDTH 10 + +`define EXPONENT 5 +`define MANTISSA 10 + +`define SIGN 1 +`define NUM_COMPARATOR_TREE_CYCLES 4 +`define NUM_COMPARATOR_TREE_CYCLES_FOR_TILE 6 +`define NUM_LZD_CYCLES 5 + +`define DESIGN_SIZE `NUM_LDPES +`define DWIDTH `OUT_PRECISION +`define MASK_WIDTH `OUT_PRECISION + +`define ADD_LATENCY 5 +`define LOG_ADD_LATENCY 3 +`define MUL_LATENCY 5 +`define LOG_MUL_LATENCY 3 +`define ACTIVATION_LATENCY 3 +`define TANH_LATENCY (`ACTIVATION_LATENCY+1) +`define SIGMOID_LATENCY (`ACTIVATION_LATENCY+1) + +`define NUM_REDUCTION_CYCLES 4 +`define NUM_MVM_CYCLES 14 +`define NUM_NORMALISE_CYCLES 6 + +module bwave_small_random ( + input logic clk, + input logic rst, + input logic [`INSTR_WIDTH-1:0] instruction, + output logic [`DRAM_DWIDTH-1:0] output_data_DRAM, + output logic [`DRAM_AWIDTH-1:0] dram_addr, + output logic dram_write_enable, + output logic get_instr, + output logic [`INSTR_MEM_AWIDTH-1:0] get_instr_addr +); + +logic [`DRAM_DWIDTH-1:0] input_data_DRAM; +RandomNumberGenerator #(`DRAM_DWIDTH, 0) rng ( + .clk(clk), + .reset(rst), + .random_number(input_data_DRAM) +); + +NPU npu0( + rst, + instruction, + input_data_DRAM, + output_data_DRAM, + dram_addr, + dram_write_enable, + get_instr, + get_instr_addr, + clk +); + +endmodule + diff --git a/designs/koios/bwave_like.float.small/design.yaml b/designs/koios/bwave_like.float.small/design.yaml new file mode 100644 index 000000000..24e5fa849 --- /dev/null +++ b/designs/koios/bwave_like.float.small/design.yaml @@ -0,0 +1 @@ +top: NPU diff --git a/designs/koios/clstm_like.large/clstm_like.large.v b/designs/koios/clstm_like.large/clstm_like.large.v new file mode 100644 index 000000000..657014ba8 --- /dev/null +++ b/designs/koios/clstm_like.large/clstm_like.large.v @@ -0,0 +1,35251 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Andrew Boutros +////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +//An accelerator overlay for LSTMs based on the C-LSTM paper: +//S. Wang et al., “C-LSTM: Enabling Efficient LSTM Using Structured Compression Techniques on FPGAs,” in International Symposium on Field-Programmable Gate Arrays (FPGA), 2018. +//Some properties of the design are: +//1. 18-bit fixed point is used. +//2. FFT based circulant convolution +//3. On-chip weight storage (compressed weights). +//4. Double buffering of intermediate results between stages. +//5. Element-wise addition, multiplication and activation blocks. +/////////////////////////////////////////////////////////////////////////////// + +module C_LSTM_datapath ( + input clk, + input reset, + input [161:0] wdata_stage1, + input [7:0] wen_stage1, + input [287:0] wdata_stage2, + input [6:0] wen_stage2, + input [161:0] wdata_stage3, + input [1:0] wen_stage3, + input [17:0] i_X_data_0, + input [17:0] i_X_data_1, + input [17:0] i_X_data_2, + input [17:0] i_X_data_3, + input [17:0] i_X_data_4, + input [17:0] i_X_data_5, + input [17:0] i_X_data_6, + input [17:0] i_X_data_7, + input [17:0] i_X_data_8, + input [17:0] i_X_data_9, + input [17:0] i_X_data_10, + input [17:0] i_X_data_11, + input [17:0] i_X_data_12, + input [17:0] i_X_data_13, + input [17:0] i_X_data_14, + input [17:0] i_X_data_15, + input i_ready, + input i_valid, + input start_compute, + output o_valid, + output [17:0] o_Yt_0_0, + output [17:0] o_Yt_0_1, + output [17:0] o_Yt_0_2, + output [17:0] o_Yt_0_3, + output [17:0] o_Yt_0_4, + output [17:0] o_Yt_0_5, + output [17:0] o_Yt_0_6, + output [17:0] o_Yt_0_7, + output [17:0] o_Yt_0_8, + output [17:0] o_Yt_0_9, + output [17:0] o_Yt_0_10, + output [17:0] o_Yt_0_11, + output [17:0] o_Yt_0_12, + output [17:0] o_Yt_0_13, + output [17:0] o_Yt_0_14, + output [17:0] o_Yt_0_15, + output [17:0] o_Yt_1_0, + output [17:0] o_Yt_1_1, + output [17:0] o_Yt_1_2, + output [17:0] o_Yt_1_3, + output [17:0] o_Yt_1_4, + output [17:0] o_Yt_1_5, + output [17:0] o_Yt_1_6, + output [17:0] o_Yt_1_7, + output [17:0] o_Yt_1_8, + output [17:0] o_Yt_1_9, + output [17:0] o_Yt_1_10, + output [17:0] o_Yt_1_11, + output [17:0] o_Yt_1_12, + output [17:0] o_Yt_1_13, + output [17:0] o_Yt_1_14, + output [17:0] o_Yt_1_15, + output [17:0] o_Yt_2_0, + output [17:0] o_Yt_2_1, + output [17:0] o_Yt_2_2, + output [17:0] o_Yt_2_3, + output [17:0] o_Yt_2_4, + output [17:0] o_Yt_2_5, + output [17:0] o_Yt_2_6, + output [17:0] o_Yt_2_7, + output [17:0] o_Yt_2_8, + output [17:0] o_Yt_2_9, + output [17:0] o_Yt_2_10, + output [17:0] o_Yt_2_11, + output [17:0] o_Yt_2_12, + output [17:0] o_Yt_2_13, + output [17:0] o_Yt_2_14, + output [17:0] o_Yt_2_15, + output o_ready +); + +// Enable whenever reciever is ready +wire enable; +assign enable = i_ready; + +// Input registers +wire [17:0] i_data_0; +wire [17:0] i_data_1; +wire [17:0] i_data_2; +wire [17:0] i_data_3; +wire [17:0] i_data_4; +wire [17:0] i_data_5; +wire [17:0] i_data_6; +wire [17:0] i_data_7; +wire [17:0] i_data_8; +wire [17:0] i_data_9; +wire [17:0] i_data_10; +wire [17:0] i_data_11; +wire [17:0] i_data_12; +wire [17:0] i_data_13; +wire [17:0] i_data_14; +wire [17:0] i_data_15; +wire [17:0] i_data_hold_0; +wire [17:0] i_data_hold_1; +wire [17:0] i_data_hold_2; +wire [17:0] i_data_hold_3; +wire [17:0] i_data_hold_4; +wire [17:0] i_data_hold_5; +wire [17:0] i_data_hold_6; +wire [17:0] i_data_hold_7; +wire [17:0] i_data_hold_8; +wire [17:0] i_data_hold_9; +wire [17:0] i_data_hold_10; +wire [17:0] i_data_hold_11; +wire [17:0] i_data_hold_12; +wire [17:0] i_data_hold_13; +wire [17:0] i_data_hold_14; +wire [17:0] i_data_hold_15; + +// Inter connections +wire i_valid_hold; +wire stage1_valid, stage1_ready; +wire out_X_Y_buffer_valid; + +// Stage 1 connections and weight buffers +// Input gate parameters +wire [17:0] Wixr_real_0_0; +wire [17:0] Wixr_imag_0_0; +wire [17:0] Wixr_real_0_1; +wire [17:0] Wixr_imag_0_1; +wire [17:0] Wixr_real_0_2; +wire [17:0] Wixr_imag_0_2; +wire [17:0] Wixr_real_0_3; +wire [17:0] Wixr_imag_0_3; +wire [17:0] Wixr_real_0_4; +wire [17:0] Wixr_imag_0_4; +wire [17:0] Wixr_real_0_5; +wire [17:0] Wixr_imag_0_5; +wire [17:0] Wixr_real_0_6; +wire [17:0] Wixr_imag_0_6; +wire [17:0] Wixr_real_0_7; +wire [17:0] Wixr_imag_0_7; +wire [17:0] Wixr_real_0_8; +wire [17:0] Wixr_imag_0_8; +wire [17:0] Wixr_real_1_0; +wire [17:0] Wixr_imag_1_0; +wire [17:0] Wixr_real_1_1; +wire [17:0] Wixr_imag_1_1; +wire [17:0] Wixr_real_1_2; +wire [17:0] Wixr_imag_1_2; +wire [17:0] Wixr_real_1_3; +wire [17:0] Wixr_imag_1_3; +wire [17:0] Wixr_real_1_4; +wire [17:0] Wixr_imag_1_4; +wire [17:0] Wixr_real_1_5; +wire [17:0] Wixr_imag_1_5; +wire [17:0] Wixr_real_1_6; +wire [17:0] Wixr_imag_1_6; +wire [17:0] Wixr_real_1_7; +wire [17:0] Wixr_imag_1_7; +wire [17:0] Wixr_real_1_8; +wire [17:0] Wixr_imag_1_8; +wire [17:0] Wixr_real_2_0; +wire [17:0] Wixr_imag_2_0; +wire [17:0] Wixr_real_2_1; +wire [17:0] Wixr_imag_2_1; +wire [17:0] Wixr_real_2_2; +wire [17:0] Wixr_imag_2_2; +wire [17:0] Wixr_real_2_3; +wire [17:0] Wixr_imag_2_3; +wire [17:0] Wixr_real_2_4; +wire [17:0] Wixr_imag_2_4; +wire [17:0] Wixr_real_2_5; +wire [17:0] Wixr_imag_2_5; +wire [17:0] Wixr_real_2_6; +wire [17:0] Wixr_imag_2_6; +wire [17:0] Wixr_real_2_7; +wire [17:0] Wixr_imag_2_7; +wire [17:0] Wixr_real_2_8; +wire [17:0] Wixr_imag_2_8; + +// Forget gate parameters +wire [17:0] Wfxr_real_0_0; +wire [17:0] Wfxr_imag_0_0; +wire [17:0] Wfxr_real_0_1; +wire [17:0] Wfxr_imag_0_1; +wire [17:0] Wfxr_real_0_2; +wire [17:0] Wfxr_imag_0_2; +wire [17:0] Wfxr_real_0_3; +wire [17:0] Wfxr_imag_0_3; +wire [17:0] Wfxr_real_0_4; +wire [17:0] Wfxr_imag_0_4; +wire [17:0] Wfxr_real_0_5; +wire [17:0] Wfxr_imag_0_5; +wire [17:0] Wfxr_real_0_6; +wire [17:0] Wfxr_imag_0_6; +wire [17:0] Wfxr_real_0_7; +wire [17:0] Wfxr_imag_0_7; +wire [17:0] Wfxr_real_0_8; +wire [17:0] Wfxr_imag_0_8; +wire [17:0] Wfxr_real_1_0; +wire [17:0] Wfxr_imag_1_0; +wire [17:0] Wfxr_real_1_1; +wire [17:0] Wfxr_imag_1_1; +wire [17:0] Wfxr_real_1_2; +wire [17:0] Wfxr_imag_1_2; +wire [17:0] Wfxr_real_1_3; +wire [17:0] Wfxr_imag_1_3; +wire [17:0] Wfxr_real_1_4; +wire [17:0] Wfxr_imag_1_4; +wire [17:0] Wfxr_real_1_5; +wire [17:0] Wfxr_imag_1_5; +wire [17:0] Wfxr_real_1_6; +wire [17:0] Wfxr_imag_1_6; +wire [17:0] Wfxr_real_1_7; +wire [17:0] Wfxr_imag_1_7; +wire [17:0] Wfxr_real_1_8; +wire [17:0] Wfxr_imag_1_8; +wire [17:0] Wfxr_real_2_0; +wire [17:0] Wfxr_imag_2_0; +wire [17:0] Wfxr_real_2_1; +wire [17:0] Wfxr_imag_2_1; +wire [17:0] Wfxr_real_2_2; +wire [17:0] Wfxr_imag_2_2; +wire [17:0] Wfxr_real_2_3; +wire [17:0] Wfxr_imag_2_3; +wire [17:0] Wfxr_real_2_4; +wire [17:0] Wfxr_imag_2_4; +wire [17:0] Wfxr_real_2_5; +wire [17:0] Wfxr_imag_2_5; +wire [17:0] Wfxr_real_2_6; +wire [17:0] Wfxr_imag_2_6; +wire [17:0] Wfxr_real_2_7; +wire [17:0] Wfxr_imag_2_7; +wire [17:0] Wfxr_real_2_8; +wire [17:0] Wfxr_imag_2_8; + +// Output gate parameters +wire [17:0] Woxr_real_0_0; +wire [17:0] Woxr_imag_0_0; +wire [17:0] Woxr_real_0_1; +wire [17:0] Woxr_imag_0_1; +wire [17:0] Woxr_real_0_2; +wire [17:0] Woxr_imag_0_2; +wire [17:0] Woxr_real_0_3; +wire [17:0] Woxr_imag_0_3; +wire [17:0] Woxr_real_0_4; +wire [17:0] Woxr_imag_0_4; +wire [17:0] Woxr_real_0_5; +wire [17:0] Woxr_imag_0_5; +wire [17:0] Woxr_real_0_6; +wire [17:0] Woxr_imag_0_6; +wire [17:0] Woxr_real_0_7; +wire [17:0] Woxr_imag_0_7; +wire [17:0] Woxr_real_0_8; +wire [17:0] Woxr_imag_0_8; +wire [17:0] Woxr_real_1_0; +wire [17:0] Woxr_imag_1_0; +wire [17:0] Woxr_real_1_1; +wire [17:0] Woxr_imag_1_1; +wire [17:0] Woxr_real_1_2; +wire [17:0] Woxr_imag_1_2; +wire [17:0] Woxr_real_1_3; +wire [17:0] Woxr_imag_1_3; +wire [17:0] Woxr_real_1_4; +wire [17:0] Woxr_imag_1_4; +wire [17:0] Woxr_real_1_5; +wire [17:0] Woxr_imag_1_5; +wire [17:0] Woxr_real_1_6; +wire [17:0] Woxr_imag_1_6; +wire [17:0] Woxr_real_1_7; +wire [17:0] Woxr_imag_1_7; +wire [17:0] Woxr_real_1_8; +wire [17:0] Woxr_imag_1_8; +wire [17:0] Woxr_real_2_0; +wire [17:0] Woxr_imag_2_0; +wire [17:0] Woxr_real_2_1; +wire [17:0] Woxr_imag_2_1; +wire [17:0] Woxr_real_2_2; +wire [17:0] Woxr_imag_2_2; +wire [17:0] Woxr_real_2_3; +wire [17:0] Woxr_imag_2_3; +wire [17:0] Woxr_real_2_4; +wire [17:0] Woxr_imag_2_4; +wire [17:0] Woxr_real_2_5; +wire [17:0] Woxr_imag_2_5; +wire [17:0] Woxr_real_2_6; +wire [17:0] Woxr_imag_2_6; +wire [17:0] Woxr_real_2_7; +wire [17:0] Woxr_imag_2_7; +wire [17:0] Woxr_real_2_8; +wire [17:0] Woxr_imag_2_8; + +// Activation gate parameters +wire [17:0] Wcxr_real_0_0; +wire [17:0] Wcxr_imag_0_0; +wire [17:0] Wcxr_real_0_1; +wire [17:0] Wcxr_imag_0_1; +wire [17:0] Wcxr_real_0_2; +wire [17:0] Wcxr_imag_0_2; +wire [17:0] Wcxr_real_0_3; +wire [17:0] Wcxr_imag_0_3; +wire [17:0] Wcxr_real_0_4; +wire [17:0] Wcxr_imag_0_4; +wire [17:0] Wcxr_real_0_5; +wire [17:0] Wcxr_imag_0_5; +wire [17:0] Wcxr_real_0_6; +wire [17:0] Wcxr_imag_0_6; +wire [17:0] Wcxr_real_0_7; +wire [17:0] Wcxr_imag_0_7; +wire [17:0] Wcxr_real_0_8; +wire [17:0] Wcxr_imag_0_8; +wire [17:0] Wcxr_real_1_0; +wire [17:0] Wcxr_imag_1_0; +wire [17:0] Wcxr_real_1_1; +wire [17:0] Wcxr_imag_1_1; +wire [17:0] Wcxr_real_1_2; +wire [17:0] Wcxr_imag_1_2; +wire [17:0] Wcxr_real_1_3; +wire [17:0] Wcxr_imag_1_3; +wire [17:0] Wcxr_real_1_4; +wire [17:0] Wcxr_imag_1_4; +wire [17:0] Wcxr_real_1_5; +wire [17:0] Wcxr_imag_1_5; +wire [17:0] Wcxr_real_1_6; +wire [17:0] Wcxr_imag_1_6; +wire [17:0] Wcxr_real_1_7; +wire [17:0] Wcxr_imag_1_7; +wire [17:0] Wcxr_real_1_8; +wire [17:0] Wcxr_imag_1_8; +wire [17:0] Wcxr_real_2_0; +wire [17:0] Wcxr_imag_2_0; +wire [17:0] Wcxr_real_2_1; +wire [17:0] Wcxr_imag_2_1; +wire [17:0] Wcxr_real_2_2; +wire [17:0] Wcxr_imag_2_2; +wire [17:0] Wcxr_real_2_3; +wire [17:0] Wcxr_imag_2_3; +wire [17:0] Wcxr_real_2_4; +wire [17:0] Wcxr_imag_2_4; +wire [17:0] Wcxr_real_2_5; +wire [17:0] Wcxr_imag_2_5; +wire [17:0] Wcxr_real_2_6; +wire [17:0] Wcxr_imag_2_6; +wire [17:0] Wcxr_real_2_7; +wire [17:0] Wcxr_imag_2_7; +wire [17:0] Wcxr_real_2_8; +wire [17:0] Wcxr_imag_2_8; + +wire [17:0] WixrXtYt_1_0_0; +wire [17:0] WfxrXtYt_1_0_0; +wire [17:0] WoxrXtYt_1_0_0; +wire [17:0] WcxrXtYt_1_0_0; +wire [17:0] WixrXtYt_1_0_1; +wire [17:0] WfxrXtYt_1_0_1; +wire [17:0] WoxrXtYt_1_0_1; +wire [17:0] WcxrXtYt_1_0_1; +wire [17:0] WixrXtYt_1_0_2; +wire [17:0] WfxrXtYt_1_0_2; +wire [17:0] WoxrXtYt_1_0_2; +wire [17:0] WcxrXtYt_1_0_2; +wire [17:0] WixrXtYt_1_0_3; +wire [17:0] WfxrXtYt_1_0_3; +wire [17:0] WoxrXtYt_1_0_3; +wire [17:0] WcxrXtYt_1_0_3; +wire [17:0] WixrXtYt_1_0_4; +wire [17:0] WfxrXtYt_1_0_4; +wire [17:0] WoxrXtYt_1_0_4; +wire [17:0] WcxrXtYt_1_0_4; +wire [17:0] WixrXtYt_1_0_5; +wire [17:0] WfxrXtYt_1_0_5; +wire [17:0] WoxrXtYt_1_0_5; +wire [17:0] WcxrXtYt_1_0_5; +wire [17:0] WixrXtYt_1_0_6; +wire [17:0] WfxrXtYt_1_0_6; +wire [17:0] WoxrXtYt_1_0_6; +wire [17:0] WcxrXtYt_1_0_6; +wire [17:0] WixrXtYt_1_0_7; +wire [17:0] WfxrXtYt_1_0_7; +wire [17:0] WoxrXtYt_1_0_7; +wire [17:0] WcxrXtYt_1_0_7; +wire [17:0] WixrXtYt_1_0_8; +wire [17:0] WfxrXtYt_1_0_8; +wire [17:0] WoxrXtYt_1_0_8; +wire [17:0] WcxrXtYt_1_0_8; +wire [17:0] WixrXtYt_1_0_9; +wire [17:0] WfxrXtYt_1_0_9; +wire [17:0] WoxrXtYt_1_0_9; +wire [17:0] WcxrXtYt_1_0_9; +wire [17:0] WixrXtYt_1_0_10; +wire [17:0] WfxrXtYt_1_0_10; +wire [17:0] WoxrXtYt_1_0_10; +wire [17:0] WcxrXtYt_1_0_10; +wire [17:0] WixrXtYt_1_0_11; +wire [17:0] WfxrXtYt_1_0_11; +wire [17:0] WoxrXtYt_1_0_11; +wire [17:0] WcxrXtYt_1_0_11; +wire [17:0] WixrXtYt_1_0_12; +wire [17:0] WfxrXtYt_1_0_12; +wire [17:0] WoxrXtYt_1_0_12; +wire [17:0] WcxrXtYt_1_0_12; +wire [17:0] WixrXtYt_1_0_13; +wire [17:0] WfxrXtYt_1_0_13; +wire [17:0] WoxrXtYt_1_0_13; +wire [17:0] WcxrXtYt_1_0_13; +wire [17:0] WixrXtYt_1_0_14; +wire [17:0] WfxrXtYt_1_0_14; +wire [17:0] WoxrXtYt_1_0_14; +wire [17:0] WcxrXtYt_1_0_14; +wire [17:0] WixrXtYt_1_0_15; +wire [17:0] WfxrXtYt_1_0_15; +wire [17:0] WoxrXtYt_1_0_15; +wire [17:0] WcxrXtYt_1_0_15; +wire [17:0] WixrXtYt_1_1_0; +wire [17:0] WfxrXtYt_1_1_0; +wire [17:0] WoxrXtYt_1_1_0; +wire [17:0] WcxrXtYt_1_1_0; +wire [17:0] WixrXtYt_1_1_1; +wire [17:0] WfxrXtYt_1_1_1; +wire [17:0] WoxrXtYt_1_1_1; +wire [17:0] WcxrXtYt_1_1_1; +wire [17:0] WixrXtYt_1_1_2; +wire [17:0] WfxrXtYt_1_1_2; +wire [17:0] WoxrXtYt_1_1_2; +wire [17:0] WcxrXtYt_1_1_2; +wire [17:0] WixrXtYt_1_1_3; +wire [17:0] WfxrXtYt_1_1_3; +wire [17:0] WoxrXtYt_1_1_3; +wire [17:0] WcxrXtYt_1_1_3; +wire [17:0] WixrXtYt_1_1_4; +wire [17:0] WfxrXtYt_1_1_4; +wire [17:0] WoxrXtYt_1_1_4; +wire [17:0] WcxrXtYt_1_1_4; +wire [17:0] WixrXtYt_1_1_5; +wire [17:0] WfxrXtYt_1_1_5; +wire [17:0] WoxrXtYt_1_1_5; +wire [17:0] WcxrXtYt_1_1_5; +wire [17:0] WixrXtYt_1_1_6; +wire [17:0] WfxrXtYt_1_1_6; +wire [17:0] WoxrXtYt_1_1_6; +wire [17:0] WcxrXtYt_1_1_6; +wire [17:0] WixrXtYt_1_1_7; +wire [17:0] WfxrXtYt_1_1_7; +wire [17:0] WoxrXtYt_1_1_7; +wire [17:0] WcxrXtYt_1_1_7; +wire [17:0] WixrXtYt_1_1_8; +wire [17:0] WfxrXtYt_1_1_8; +wire [17:0] WoxrXtYt_1_1_8; +wire [17:0] WcxrXtYt_1_1_8; +wire [17:0] WixrXtYt_1_1_9; +wire [17:0] WfxrXtYt_1_1_9; +wire [17:0] WoxrXtYt_1_1_9; +wire [17:0] WcxrXtYt_1_1_9; +wire [17:0] WixrXtYt_1_1_10; +wire [17:0] WfxrXtYt_1_1_10; +wire [17:0] WoxrXtYt_1_1_10; +wire [17:0] WcxrXtYt_1_1_10; +wire [17:0] WixrXtYt_1_1_11; +wire [17:0] WfxrXtYt_1_1_11; +wire [17:0] WoxrXtYt_1_1_11; +wire [17:0] WcxrXtYt_1_1_11; +wire [17:0] WixrXtYt_1_1_12; +wire [17:0] WfxrXtYt_1_1_12; +wire [17:0] WoxrXtYt_1_1_12; +wire [17:0] WcxrXtYt_1_1_12; +wire [17:0] WixrXtYt_1_1_13; +wire [17:0] WfxrXtYt_1_1_13; +wire [17:0] WoxrXtYt_1_1_13; +wire [17:0] WcxrXtYt_1_1_13; +wire [17:0] WixrXtYt_1_1_14; +wire [17:0] WfxrXtYt_1_1_14; +wire [17:0] WoxrXtYt_1_1_14; +wire [17:0] WcxrXtYt_1_1_14; +wire [17:0] WixrXtYt_1_1_15; +wire [17:0] WfxrXtYt_1_1_15; +wire [17:0] WoxrXtYt_1_1_15; +wire [17:0] WcxrXtYt_1_1_15; +wire [17:0] WixrXtYt_1_2_0; +wire [17:0] WfxrXtYt_1_2_0; +wire [17:0] WoxrXtYt_1_2_0; +wire [17:0] WcxrXtYt_1_2_0; +wire [17:0] WixrXtYt_1_2_1; +wire [17:0] WfxrXtYt_1_2_1; +wire [17:0] WoxrXtYt_1_2_1; +wire [17:0] WcxrXtYt_1_2_1; +wire [17:0] WixrXtYt_1_2_2; +wire [17:0] WfxrXtYt_1_2_2; +wire [17:0] WoxrXtYt_1_2_2; +wire [17:0] WcxrXtYt_1_2_2; +wire [17:0] WixrXtYt_1_2_3; +wire [17:0] WfxrXtYt_1_2_3; +wire [17:0] WoxrXtYt_1_2_3; +wire [17:0] WcxrXtYt_1_2_3; +wire [17:0] WixrXtYt_1_2_4; +wire [17:0] WfxrXtYt_1_2_4; +wire [17:0] WoxrXtYt_1_2_4; +wire [17:0] WcxrXtYt_1_2_4; +wire [17:0] WixrXtYt_1_2_5; +wire [17:0] WfxrXtYt_1_2_5; +wire [17:0] WoxrXtYt_1_2_5; +wire [17:0] WcxrXtYt_1_2_5; +wire [17:0] WixrXtYt_1_2_6; +wire [17:0] WfxrXtYt_1_2_6; +wire [17:0] WoxrXtYt_1_2_6; +wire [17:0] WcxrXtYt_1_2_6; +wire [17:0] WixrXtYt_1_2_7; +wire [17:0] WfxrXtYt_1_2_7; +wire [17:0] WoxrXtYt_1_2_7; +wire [17:0] WcxrXtYt_1_2_7; +wire [17:0] WixrXtYt_1_2_8; +wire [17:0] WfxrXtYt_1_2_8; +wire [17:0] WoxrXtYt_1_2_8; +wire [17:0] WcxrXtYt_1_2_8; +wire [17:0] WixrXtYt_1_2_9; +wire [17:0] WfxrXtYt_1_2_9; +wire [17:0] WoxrXtYt_1_2_9; +wire [17:0] WcxrXtYt_1_2_9; +wire [17:0] WixrXtYt_1_2_10; +wire [17:0] WfxrXtYt_1_2_10; +wire [17:0] WoxrXtYt_1_2_10; +wire [17:0] WcxrXtYt_1_2_10; +wire [17:0] WixrXtYt_1_2_11; +wire [17:0] WfxrXtYt_1_2_11; +wire [17:0] WoxrXtYt_1_2_11; +wire [17:0] WcxrXtYt_1_2_11; +wire [17:0] WixrXtYt_1_2_12; +wire [17:0] WfxrXtYt_1_2_12; +wire [17:0] WoxrXtYt_1_2_12; +wire [17:0] WcxrXtYt_1_2_12; +wire [17:0] WixrXtYt_1_2_13; +wire [17:0] WfxrXtYt_1_2_13; +wire [17:0] WoxrXtYt_1_2_13; +wire [17:0] WcxrXtYt_1_2_13; +wire [17:0] WixrXtYt_1_2_14; +wire [17:0] WfxrXtYt_1_2_14; +wire [17:0] WoxrXtYt_1_2_14; +wire [17:0] WcxrXtYt_1_2_14; +wire [17:0] WixrXtYt_1_2_15; +wire [17:0] WfxrXtYt_1_2_15; +wire [17:0] WoxrXtYt_1_2_15; +wire [17:0] WcxrXtYt_1_2_15; + +wire stage_buffer_incr_index; +assign stage_buffer_incr_index = out_X_Y_buffer_valid & enable; +stage1_parameter_buffer_18_3_16_42_2688 stage1_parameter_buffer_18_3_16_42_2688_inst_bxkrerahil ( + .clk(clk), + .reset(reset), + .wdata(wdata_stage1), + .wen(wen_stage1), + .Wixr_real_0_0(Wixr_real_0_0), + .Wixr_imag_0_0(Wixr_imag_0_0), + .Wfxr_real_0_0(Wfxr_real_0_0), + .Wfxr_imag_0_0(Wfxr_imag_0_0), + .Woxr_real_0_0(Woxr_real_0_0), + .Woxr_imag_0_0(Woxr_imag_0_0), + .Wcxr_real_0_0(Wcxr_real_0_0), + .Wcxr_imag_0_0(Wcxr_imag_0_0), + .Wixr_real_0_1(Wixr_real_0_1), + .Wixr_imag_0_1(Wixr_imag_0_1), + .Wfxr_real_0_1(Wfxr_real_0_1), + .Wfxr_imag_0_1(Wfxr_imag_0_1), + .Woxr_real_0_1(Woxr_real_0_1), + .Woxr_imag_0_1(Woxr_imag_0_1), + .Wcxr_real_0_1(Wcxr_real_0_1), + .Wcxr_imag_0_1(Wcxr_imag_0_1), + .Wixr_real_0_2(Wixr_real_0_2), + .Wixr_imag_0_2(Wixr_imag_0_2), + .Wfxr_real_0_2(Wfxr_real_0_2), + .Wfxr_imag_0_2(Wfxr_imag_0_2), + .Woxr_real_0_2(Woxr_real_0_2), + .Woxr_imag_0_2(Woxr_imag_0_2), + .Wcxr_real_0_2(Wcxr_real_0_2), + .Wcxr_imag_0_2(Wcxr_imag_0_2), + .Wixr_real_0_3(Wixr_real_0_3), + .Wixr_imag_0_3(Wixr_imag_0_3), + .Wfxr_real_0_3(Wfxr_real_0_3), + .Wfxr_imag_0_3(Wfxr_imag_0_3), + .Woxr_real_0_3(Woxr_real_0_3), + .Woxr_imag_0_3(Woxr_imag_0_3), + .Wcxr_real_0_3(Wcxr_real_0_3), + .Wcxr_imag_0_3(Wcxr_imag_0_3), + .Wixr_real_0_4(Wixr_real_0_4), + .Wixr_imag_0_4(Wixr_imag_0_4), + .Wfxr_real_0_4(Wfxr_real_0_4), + .Wfxr_imag_0_4(Wfxr_imag_0_4), + .Woxr_real_0_4(Woxr_real_0_4), + .Woxr_imag_0_4(Woxr_imag_0_4), + .Wcxr_real_0_4(Wcxr_real_0_4), + .Wcxr_imag_0_4(Wcxr_imag_0_4), + .Wixr_real_0_5(Wixr_real_0_5), + .Wixr_imag_0_5(Wixr_imag_0_5), + .Wfxr_real_0_5(Wfxr_real_0_5), + .Wfxr_imag_0_5(Wfxr_imag_0_5), + .Woxr_real_0_5(Woxr_real_0_5), + .Woxr_imag_0_5(Woxr_imag_0_5), + .Wcxr_real_0_5(Wcxr_real_0_5), + .Wcxr_imag_0_5(Wcxr_imag_0_5), + .Wixr_real_0_6(Wixr_real_0_6), + .Wixr_imag_0_6(Wixr_imag_0_6), + .Wfxr_real_0_6(Wfxr_real_0_6), + .Wfxr_imag_0_6(Wfxr_imag_0_6), + .Woxr_real_0_6(Woxr_real_0_6), + .Woxr_imag_0_6(Woxr_imag_0_6), + .Wcxr_real_0_6(Wcxr_real_0_6), + .Wcxr_imag_0_6(Wcxr_imag_0_6), + .Wixr_real_0_7(Wixr_real_0_7), + .Wixr_imag_0_7(Wixr_imag_0_7), + .Wfxr_real_0_7(Wfxr_real_0_7), + .Wfxr_imag_0_7(Wfxr_imag_0_7), + .Woxr_real_0_7(Woxr_real_0_7), + .Woxr_imag_0_7(Woxr_imag_0_7), + .Wcxr_real_0_7(Wcxr_real_0_7), + .Wcxr_imag_0_7(Wcxr_imag_0_7), + .Wixr_real_0_8(Wixr_real_0_8), + .Wixr_imag_0_8(Wixr_imag_0_8), + .Wfxr_real_0_8(Wfxr_real_0_8), + .Wfxr_imag_0_8(Wfxr_imag_0_8), + .Woxr_real_0_8(Woxr_real_0_8), + .Woxr_imag_0_8(Woxr_imag_0_8), + .Wcxr_real_0_8(Wcxr_real_0_8), + .Wcxr_imag_0_8(Wcxr_imag_0_8), + .Wixr_real_1_0(Wixr_real_1_0), + .Wixr_imag_1_0(Wixr_imag_1_0), + .Wfxr_real_1_0(Wfxr_real_1_0), + .Wfxr_imag_1_0(Wfxr_imag_1_0), + .Woxr_real_1_0(Woxr_real_1_0), + .Woxr_imag_1_0(Woxr_imag_1_0), + .Wcxr_real_1_0(Wcxr_real_1_0), + .Wcxr_imag_1_0(Wcxr_imag_1_0), + .Wixr_real_1_1(Wixr_real_1_1), + .Wixr_imag_1_1(Wixr_imag_1_1), + .Wfxr_real_1_1(Wfxr_real_1_1), + .Wfxr_imag_1_1(Wfxr_imag_1_1), + .Woxr_real_1_1(Woxr_real_1_1), + .Woxr_imag_1_1(Woxr_imag_1_1), + .Wcxr_real_1_1(Wcxr_real_1_1), + .Wcxr_imag_1_1(Wcxr_imag_1_1), + .Wixr_real_1_2(Wixr_real_1_2), + .Wixr_imag_1_2(Wixr_imag_1_2), + .Wfxr_real_1_2(Wfxr_real_1_2), + .Wfxr_imag_1_2(Wfxr_imag_1_2), + .Woxr_real_1_2(Woxr_real_1_2), + .Woxr_imag_1_2(Woxr_imag_1_2), + .Wcxr_real_1_2(Wcxr_real_1_2), + .Wcxr_imag_1_2(Wcxr_imag_1_2), + .Wixr_real_1_3(Wixr_real_1_3), + .Wixr_imag_1_3(Wixr_imag_1_3), + .Wfxr_real_1_3(Wfxr_real_1_3), + .Wfxr_imag_1_3(Wfxr_imag_1_3), + .Woxr_real_1_3(Woxr_real_1_3), + .Woxr_imag_1_3(Woxr_imag_1_3), + .Wcxr_real_1_3(Wcxr_real_1_3), + .Wcxr_imag_1_3(Wcxr_imag_1_3), + .Wixr_real_1_4(Wixr_real_1_4), + .Wixr_imag_1_4(Wixr_imag_1_4), + .Wfxr_real_1_4(Wfxr_real_1_4), + .Wfxr_imag_1_4(Wfxr_imag_1_4), + .Woxr_real_1_4(Woxr_real_1_4), + .Woxr_imag_1_4(Woxr_imag_1_4), + .Wcxr_real_1_4(Wcxr_real_1_4), + .Wcxr_imag_1_4(Wcxr_imag_1_4), + .Wixr_real_1_5(Wixr_real_1_5), + .Wixr_imag_1_5(Wixr_imag_1_5), + .Wfxr_real_1_5(Wfxr_real_1_5), + .Wfxr_imag_1_5(Wfxr_imag_1_5), + .Woxr_real_1_5(Woxr_real_1_5), + .Woxr_imag_1_5(Woxr_imag_1_5), + .Wcxr_real_1_5(Wcxr_real_1_5), + .Wcxr_imag_1_5(Wcxr_imag_1_5), + .Wixr_real_1_6(Wixr_real_1_6), + .Wixr_imag_1_6(Wixr_imag_1_6), + .Wfxr_real_1_6(Wfxr_real_1_6), + .Wfxr_imag_1_6(Wfxr_imag_1_6), + .Woxr_real_1_6(Woxr_real_1_6), + .Woxr_imag_1_6(Woxr_imag_1_6), + .Wcxr_real_1_6(Wcxr_real_1_6), + .Wcxr_imag_1_6(Wcxr_imag_1_6), + .Wixr_real_1_7(Wixr_real_1_7), + .Wixr_imag_1_7(Wixr_imag_1_7), + .Wfxr_real_1_7(Wfxr_real_1_7), + .Wfxr_imag_1_7(Wfxr_imag_1_7), + .Woxr_real_1_7(Woxr_real_1_7), + .Woxr_imag_1_7(Woxr_imag_1_7), + .Wcxr_real_1_7(Wcxr_real_1_7), + .Wcxr_imag_1_7(Wcxr_imag_1_7), + .Wixr_real_1_8(Wixr_real_1_8), + .Wixr_imag_1_8(Wixr_imag_1_8), + .Wfxr_real_1_8(Wfxr_real_1_8), + .Wfxr_imag_1_8(Wfxr_imag_1_8), + .Woxr_real_1_8(Woxr_real_1_8), + .Woxr_imag_1_8(Woxr_imag_1_8), + .Wcxr_real_1_8(Wcxr_real_1_8), + .Wcxr_imag_1_8(Wcxr_imag_1_8), + .Wixr_real_2_0(Wixr_real_2_0), + .Wixr_imag_2_0(Wixr_imag_2_0), + .Wfxr_real_2_0(Wfxr_real_2_0), + .Wfxr_imag_2_0(Wfxr_imag_2_0), + .Woxr_real_2_0(Woxr_real_2_0), + .Woxr_imag_2_0(Woxr_imag_2_0), + .Wcxr_real_2_0(Wcxr_real_2_0), + .Wcxr_imag_2_0(Wcxr_imag_2_0), + .Wixr_real_2_1(Wixr_real_2_1), + .Wixr_imag_2_1(Wixr_imag_2_1), + .Wfxr_real_2_1(Wfxr_real_2_1), + .Wfxr_imag_2_1(Wfxr_imag_2_1), + .Woxr_real_2_1(Woxr_real_2_1), + .Woxr_imag_2_1(Woxr_imag_2_1), + .Wcxr_real_2_1(Wcxr_real_2_1), + .Wcxr_imag_2_1(Wcxr_imag_2_1), + .Wixr_real_2_2(Wixr_real_2_2), + .Wixr_imag_2_2(Wixr_imag_2_2), + .Wfxr_real_2_2(Wfxr_real_2_2), + .Wfxr_imag_2_2(Wfxr_imag_2_2), + .Woxr_real_2_2(Woxr_real_2_2), + .Woxr_imag_2_2(Woxr_imag_2_2), + .Wcxr_real_2_2(Wcxr_real_2_2), + .Wcxr_imag_2_2(Wcxr_imag_2_2), + .Wixr_real_2_3(Wixr_real_2_3), + .Wixr_imag_2_3(Wixr_imag_2_3), + .Wfxr_real_2_3(Wfxr_real_2_3), + .Wfxr_imag_2_3(Wfxr_imag_2_3), + .Woxr_real_2_3(Woxr_real_2_3), + .Woxr_imag_2_3(Woxr_imag_2_3), + .Wcxr_real_2_3(Wcxr_real_2_3), + .Wcxr_imag_2_3(Wcxr_imag_2_3), + .Wixr_real_2_4(Wixr_real_2_4), + .Wixr_imag_2_4(Wixr_imag_2_4), + .Wfxr_real_2_4(Wfxr_real_2_4), + .Wfxr_imag_2_4(Wfxr_imag_2_4), + .Woxr_real_2_4(Woxr_real_2_4), + .Woxr_imag_2_4(Woxr_imag_2_4), + .Wcxr_real_2_4(Wcxr_real_2_4), + .Wcxr_imag_2_4(Wcxr_imag_2_4), + .Wixr_real_2_5(Wixr_real_2_5), + .Wixr_imag_2_5(Wixr_imag_2_5), + .Wfxr_real_2_5(Wfxr_real_2_5), + .Wfxr_imag_2_5(Wfxr_imag_2_5), + .Woxr_real_2_5(Woxr_real_2_5), + .Woxr_imag_2_5(Woxr_imag_2_5), + .Wcxr_real_2_5(Wcxr_real_2_5), + .Wcxr_imag_2_5(Wcxr_imag_2_5), + .Wixr_real_2_6(Wixr_real_2_6), + .Wixr_imag_2_6(Wixr_imag_2_6), + .Wfxr_real_2_6(Wfxr_real_2_6), + .Wfxr_imag_2_6(Wfxr_imag_2_6), + .Woxr_real_2_6(Woxr_real_2_6), + .Woxr_imag_2_6(Woxr_imag_2_6), + .Wcxr_real_2_6(Wcxr_real_2_6), + .Wcxr_imag_2_6(Wcxr_imag_2_6), + .Wixr_real_2_7(Wixr_real_2_7), + .Wixr_imag_2_7(Wixr_imag_2_7), + .Wfxr_real_2_7(Wfxr_real_2_7), + .Wfxr_imag_2_7(Wfxr_imag_2_7), + .Woxr_real_2_7(Woxr_real_2_7), + .Woxr_imag_2_7(Woxr_imag_2_7), + .Wcxr_real_2_7(Wcxr_real_2_7), + .Wcxr_imag_2_7(Wcxr_imag_2_7), + .Wixr_real_2_8(Wixr_real_2_8), + .Wixr_imag_2_8(Wixr_imag_2_8), + .Wfxr_real_2_8(Wfxr_real_2_8), + .Wfxr_imag_2_8(Wfxr_imag_2_8), + .Woxr_real_2_8(Woxr_real_2_8), + .Woxr_imag_2_8(Woxr_imag_2_8), + .Wcxr_real_2_8(Wcxr_real_2_8), + .Wcxr_imag_2_8(Wcxr_imag_2_8), + .incr_index(stage_buffer_incr_index) +); + +// Pipeline the input data for one more cycle to match the parameter rom +shift_register_group_18_16_3 shift_register_group_18_16_3_inst_aytrqqeayg ( + .clk(clk), + .enable(1'b1), + .in_0(i_data_0), + .out_0(i_data_hold_0), + .in_1(i_data_1), + .out_1(i_data_hold_1), + .in_2(i_data_2), + .out_2(i_data_hold_2), + .in_3(i_data_3), + .out_3(i_data_hold_3), + .in_4(i_data_4), + .out_4(i_data_hold_4), + .in_5(i_data_5), + .out_5(i_data_hold_5), + .in_6(i_data_6), + .out_6(i_data_hold_6), + .in_7(i_data_7), + .out_7(i_data_hold_7), + .in_8(i_data_8), + .out_8(i_data_hold_8), + .in_9(i_data_9), + .out_9(i_data_hold_9), + .in_10(i_data_10), + .out_10(i_data_hold_10), + .in_11(i_data_11), + .out_11(i_data_hold_11), + .in_12(i_data_12), + .out_12(i_data_hold_12), + .in_13(i_data_13), + .out_13(i_data_hold_13), + .in_14(i_data_14), + .out_14(i_data_hold_14), + .in_15(i_data_15), + .out_15(i_data_hold_15), + .reset(reset) +); + +shift_register_unit_1_3 shift_register_unit_1_3_inst_nkhvlvahhu ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(out_X_Y_buffer_valid), + .out(i_valid_hold) +); + +C_LSTM_stage_1_18_10_160_512_3_16_1 C_LSTM_stage_1_18_10_160_512_3_16_1_inst_lotcampywi ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_ready(enable), + .i_Xt_Yt_1_0(i_data_hold_0), + .i_Xt_Yt_1_1(i_data_hold_1), + .i_Xt_Yt_1_2(i_data_hold_2), + .i_Xt_Yt_1_3(i_data_hold_3), + .i_Xt_Yt_1_4(i_data_hold_4), + .i_Xt_Yt_1_5(i_data_hold_5), + .i_Xt_Yt_1_6(i_data_hold_6), + .i_Xt_Yt_1_7(i_data_hold_7), + .i_Xt_Yt_1_8(i_data_hold_8), + .i_Xt_Yt_1_9(i_data_hold_9), + .i_Xt_Yt_1_10(i_data_hold_10), + .i_Xt_Yt_1_11(i_data_hold_11), + .i_Xt_Yt_1_12(i_data_hold_12), + .i_Xt_Yt_1_13(i_data_hold_13), + .i_Xt_Yt_1_14(i_data_hold_14), + .i_Xt_Yt_1_15(i_data_hold_15), + .i_Wixr_real_0_0(Wixr_real_0_0), + .i_Wixr_imag_0_0(Wixr_imag_0_0), + .i_Wfxr_real_0_0(Wfxr_real_0_0), + .i_Wfxr_imag_0_0(Wfxr_imag_0_0), + .i_Woxr_real_0_0(Woxr_real_0_0), + .i_Woxr_imag_0_0(Woxr_imag_0_0), + .i_Wcxr_real_0_0(Wcxr_real_0_0), + .i_Wcxr_imag_0_0(Wcxr_imag_0_0), + .i_Wixr_real_0_1(Wixr_real_0_1), + .i_Wixr_imag_0_1(Wixr_imag_0_1), + .i_Wfxr_real_0_1(Wfxr_real_0_1), + .i_Wfxr_imag_0_1(Wfxr_imag_0_1), + .i_Woxr_real_0_1(Woxr_real_0_1), + .i_Woxr_imag_0_1(Woxr_imag_0_1), + .i_Wcxr_real_0_1(Wcxr_real_0_1), + .i_Wcxr_imag_0_1(Wcxr_imag_0_1), + .i_Wixr_real_0_2(Wixr_real_0_2), + .i_Wixr_imag_0_2(Wixr_imag_0_2), + .i_Wfxr_real_0_2(Wfxr_real_0_2), + .i_Wfxr_imag_0_2(Wfxr_imag_0_2), + .i_Woxr_real_0_2(Woxr_real_0_2), + .i_Woxr_imag_0_2(Woxr_imag_0_2), + .i_Wcxr_real_0_2(Wcxr_real_0_2), + .i_Wcxr_imag_0_2(Wcxr_imag_0_2), + .i_Wixr_real_0_3(Wixr_real_0_3), + .i_Wixr_imag_0_3(Wixr_imag_0_3), + .i_Wfxr_real_0_3(Wfxr_real_0_3), + .i_Wfxr_imag_0_3(Wfxr_imag_0_3), + .i_Woxr_real_0_3(Woxr_real_0_3), + .i_Woxr_imag_0_3(Woxr_imag_0_3), + .i_Wcxr_real_0_3(Wcxr_real_0_3), + .i_Wcxr_imag_0_3(Wcxr_imag_0_3), + .i_Wixr_real_0_4(Wixr_real_0_4), + .i_Wixr_imag_0_4(Wixr_imag_0_4), + .i_Wfxr_real_0_4(Wfxr_real_0_4), + .i_Wfxr_imag_0_4(Wfxr_imag_0_4), + .i_Woxr_real_0_4(Woxr_real_0_4), + .i_Woxr_imag_0_4(Woxr_imag_0_4), + .i_Wcxr_real_0_4(Wcxr_real_0_4), + .i_Wcxr_imag_0_4(Wcxr_imag_0_4), + .i_Wixr_real_0_5(Wixr_real_0_5), + .i_Wixr_imag_0_5(Wixr_imag_0_5), + .i_Wfxr_real_0_5(Wfxr_real_0_5), + .i_Wfxr_imag_0_5(Wfxr_imag_0_5), + .i_Woxr_real_0_5(Woxr_real_0_5), + .i_Woxr_imag_0_5(Woxr_imag_0_5), + .i_Wcxr_real_0_5(Wcxr_real_0_5), + .i_Wcxr_imag_0_5(Wcxr_imag_0_5), + .i_Wixr_real_0_6(Wixr_real_0_6), + .i_Wixr_imag_0_6(Wixr_imag_0_6), + .i_Wfxr_real_0_6(Wfxr_real_0_6), + .i_Wfxr_imag_0_6(Wfxr_imag_0_6), + .i_Woxr_real_0_6(Woxr_real_0_6), + .i_Woxr_imag_0_6(Woxr_imag_0_6), + .i_Wcxr_real_0_6(Wcxr_real_0_6), + .i_Wcxr_imag_0_6(Wcxr_imag_0_6), + .i_Wixr_real_0_7(Wixr_real_0_7), + .i_Wixr_imag_0_7(Wixr_imag_0_7), + .i_Wfxr_real_0_7(Wfxr_real_0_7), + .i_Wfxr_imag_0_7(Wfxr_imag_0_7), + .i_Woxr_real_0_7(Woxr_real_0_7), + .i_Woxr_imag_0_7(Woxr_imag_0_7), + .i_Wcxr_real_0_7(Wcxr_real_0_7), + .i_Wcxr_imag_0_7(Wcxr_imag_0_7), + .i_Wixr_real_0_8(Wixr_real_0_8), + .i_Wixr_imag_0_8(Wixr_imag_0_8), + .i_Wfxr_real_0_8(Wfxr_real_0_8), + .i_Wfxr_imag_0_8(Wfxr_imag_0_8), + .i_Woxr_real_0_8(Woxr_real_0_8), + .i_Woxr_imag_0_8(Woxr_imag_0_8), + .i_Wcxr_real_0_8(Wcxr_real_0_8), + .i_Wcxr_imag_0_8(Wcxr_imag_0_8), + .i_Wixr_real_1_0(Wixr_real_1_0), + .i_Wixr_imag_1_0(Wixr_imag_1_0), + .i_Wfxr_real_1_0(Wfxr_real_1_0), + .i_Wfxr_imag_1_0(Wfxr_imag_1_0), + .i_Woxr_real_1_0(Woxr_real_1_0), + .i_Woxr_imag_1_0(Woxr_imag_1_0), + .i_Wcxr_real_1_0(Wcxr_real_1_0), + .i_Wcxr_imag_1_0(Wcxr_imag_1_0), + .i_Wixr_real_1_1(Wixr_real_1_1), + .i_Wixr_imag_1_1(Wixr_imag_1_1), + .i_Wfxr_real_1_1(Wfxr_real_1_1), + .i_Wfxr_imag_1_1(Wfxr_imag_1_1), + .i_Woxr_real_1_1(Woxr_real_1_1), + .i_Woxr_imag_1_1(Woxr_imag_1_1), + .i_Wcxr_real_1_1(Wcxr_real_1_1), + .i_Wcxr_imag_1_1(Wcxr_imag_1_1), + .i_Wixr_real_1_2(Wixr_real_1_2), + .i_Wixr_imag_1_2(Wixr_imag_1_2), + .i_Wfxr_real_1_2(Wfxr_real_1_2), + .i_Wfxr_imag_1_2(Wfxr_imag_1_2), + .i_Woxr_real_1_2(Woxr_real_1_2), + .i_Woxr_imag_1_2(Woxr_imag_1_2), + .i_Wcxr_real_1_2(Wcxr_real_1_2), + .i_Wcxr_imag_1_2(Wcxr_imag_1_2), + .i_Wixr_real_1_3(Wixr_real_1_3), + .i_Wixr_imag_1_3(Wixr_imag_1_3), + .i_Wfxr_real_1_3(Wfxr_real_1_3), + .i_Wfxr_imag_1_3(Wfxr_imag_1_3), + .i_Woxr_real_1_3(Woxr_real_1_3), + .i_Woxr_imag_1_3(Woxr_imag_1_3), + .i_Wcxr_real_1_3(Wcxr_real_1_3), + .i_Wcxr_imag_1_3(Wcxr_imag_1_3), + .i_Wixr_real_1_4(Wixr_real_1_4), + .i_Wixr_imag_1_4(Wixr_imag_1_4), + .i_Wfxr_real_1_4(Wfxr_real_1_4), + .i_Wfxr_imag_1_4(Wfxr_imag_1_4), + .i_Woxr_real_1_4(Woxr_real_1_4), + .i_Woxr_imag_1_4(Woxr_imag_1_4), + .i_Wcxr_real_1_4(Wcxr_real_1_4), + .i_Wcxr_imag_1_4(Wcxr_imag_1_4), + .i_Wixr_real_1_5(Wixr_real_1_5), + .i_Wixr_imag_1_5(Wixr_imag_1_5), + .i_Wfxr_real_1_5(Wfxr_real_1_5), + .i_Wfxr_imag_1_5(Wfxr_imag_1_5), + .i_Woxr_real_1_5(Woxr_real_1_5), + .i_Woxr_imag_1_5(Woxr_imag_1_5), + .i_Wcxr_real_1_5(Wcxr_real_1_5), + .i_Wcxr_imag_1_5(Wcxr_imag_1_5), + .i_Wixr_real_1_6(Wixr_real_1_6), + .i_Wixr_imag_1_6(Wixr_imag_1_6), + .i_Wfxr_real_1_6(Wfxr_real_1_6), + .i_Wfxr_imag_1_6(Wfxr_imag_1_6), + .i_Woxr_real_1_6(Woxr_real_1_6), + .i_Woxr_imag_1_6(Woxr_imag_1_6), + .i_Wcxr_real_1_6(Wcxr_real_1_6), + .i_Wcxr_imag_1_6(Wcxr_imag_1_6), + .i_Wixr_real_1_7(Wixr_real_1_7), + .i_Wixr_imag_1_7(Wixr_imag_1_7), + .i_Wfxr_real_1_7(Wfxr_real_1_7), + .i_Wfxr_imag_1_7(Wfxr_imag_1_7), + .i_Woxr_real_1_7(Woxr_real_1_7), + .i_Woxr_imag_1_7(Woxr_imag_1_7), + .i_Wcxr_real_1_7(Wcxr_real_1_7), + .i_Wcxr_imag_1_7(Wcxr_imag_1_7), + .i_Wixr_real_1_8(Wixr_real_1_8), + .i_Wixr_imag_1_8(Wixr_imag_1_8), + .i_Wfxr_real_1_8(Wfxr_real_1_8), + .i_Wfxr_imag_1_8(Wfxr_imag_1_8), + .i_Woxr_real_1_8(Woxr_real_1_8), + .i_Woxr_imag_1_8(Woxr_imag_1_8), + .i_Wcxr_real_1_8(Wcxr_real_1_8), + .i_Wcxr_imag_1_8(Wcxr_imag_1_8), + .i_Wixr_real_2_0(Wixr_real_2_0), + .i_Wixr_imag_2_0(Wixr_imag_2_0), + .i_Wfxr_real_2_0(Wfxr_real_2_0), + .i_Wfxr_imag_2_0(Wfxr_imag_2_0), + .i_Woxr_real_2_0(Woxr_real_2_0), + .i_Woxr_imag_2_0(Woxr_imag_2_0), + .i_Wcxr_real_2_0(Wcxr_real_2_0), + .i_Wcxr_imag_2_0(Wcxr_imag_2_0), + .i_Wixr_real_2_1(Wixr_real_2_1), + .i_Wixr_imag_2_1(Wixr_imag_2_1), + .i_Wfxr_real_2_1(Wfxr_real_2_1), + .i_Wfxr_imag_2_1(Wfxr_imag_2_1), + .i_Woxr_real_2_1(Woxr_real_2_1), + .i_Woxr_imag_2_1(Woxr_imag_2_1), + .i_Wcxr_real_2_1(Wcxr_real_2_1), + .i_Wcxr_imag_2_1(Wcxr_imag_2_1), + .i_Wixr_real_2_2(Wixr_real_2_2), + .i_Wixr_imag_2_2(Wixr_imag_2_2), + .i_Wfxr_real_2_2(Wfxr_real_2_2), + .i_Wfxr_imag_2_2(Wfxr_imag_2_2), + .i_Woxr_real_2_2(Woxr_real_2_2), + .i_Woxr_imag_2_2(Woxr_imag_2_2), + .i_Wcxr_real_2_2(Wcxr_real_2_2), + .i_Wcxr_imag_2_2(Wcxr_imag_2_2), + .i_Wixr_real_2_3(Wixr_real_2_3), + .i_Wixr_imag_2_3(Wixr_imag_2_3), + .i_Wfxr_real_2_3(Wfxr_real_2_3), + .i_Wfxr_imag_2_3(Wfxr_imag_2_3), + .i_Woxr_real_2_3(Woxr_real_2_3), + .i_Woxr_imag_2_3(Woxr_imag_2_3), + .i_Wcxr_real_2_3(Wcxr_real_2_3), + .i_Wcxr_imag_2_3(Wcxr_imag_2_3), + .i_Wixr_real_2_4(Wixr_real_2_4), + .i_Wixr_imag_2_4(Wixr_imag_2_4), + .i_Wfxr_real_2_4(Wfxr_real_2_4), + .i_Wfxr_imag_2_4(Wfxr_imag_2_4), + .i_Woxr_real_2_4(Woxr_real_2_4), + .i_Woxr_imag_2_4(Woxr_imag_2_4), + .i_Wcxr_real_2_4(Wcxr_real_2_4), + .i_Wcxr_imag_2_4(Wcxr_imag_2_4), + .i_Wixr_real_2_5(Wixr_real_2_5), + .i_Wixr_imag_2_5(Wixr_imag_2_5), + .i_Wfxr_real_2_5(Wfxr_real_2_5), + .i_Wfxr_imag_2_5(Wfxr_imag_2_5), + .i_Woxr_real_2_5(Woxr_real_2_5), + .i_Woxr_imag_2_5(Woxr_imag_2_5), + .i_Wcxr_real_2_5(Wcxr_real_2_5), + .i_Wcxr_imag_2_5(Wcxr_imag_2_5), + .i_Wixr_real_2_6(Wixr_real_2_6), + .i_Wixr_imag_2_6(Wixr_imag_2_6), + .i_Wfxr_real_2_6(Wfxr_real_2_6), + .i_Wfxr_imag_2_6(Wfxr_imag_2_6), + .i_Woxr_real_2_6(Woxr_real_2_6), + .i_Woxr_imag_2_6(Woxr_imag_2_6), + .i_Wcxr_real_2_6(Wcxr_real_2_6), + .i_Wcxr_imag_2_6(Wcxr_imag_2_6), + .i_Wixr_real_2_7(Wixr_real_2_7), + .i_Wixr_imag_2_7(Wixr_imag_2_7), + .i_Wfxr_real_2_7(Wfxr_real_2_7), + .i_Wfxr_imag_2_7(Wfxr_imag_2_7), + .i_Woxr_real_2_7(Woxr_real_2_7), + .i_Woxr_imag_2_7(Woxr_imag_2_7), + .i_Wcxr_real_2_7(Wcxr_real_2_7), + .i_Wcxr_imag_2_7(Wcxr_imag_2_7), + .i_Wixr_real_2_8(Wixr_real_2_8), + .i_Wixr_imag_2_8(Wixr_imag_2_8), + .i_Wfxr_real_2_8(Wfxr_real_2_8), + .i_Wfxr_imag_2_8(Wfxr_imag_2_8), + .i_Woxr_real_2_8(Woxr_real_2_8), + .i_Woxr_imag_2_8(Woxr_imag_2_8), + .i_Wcxr_real_2_8(Wcxr_real_2_8), + .i_Wcxr_imag_2_8(Wcxr_imag_2_8), + .o_valid(stage1_valid), + .o_ready(stage1_ready), + .o_WixrXtYt_1_0_0(WixrXtYt_1_0_0), + .o_WfxrXtYt_1_0_0(WfxrXtYt_1_0_0), + .o_WoxrXtYt_1_0_0(WoxrXtYt_1_0_0), + .o_WcxrXtYt_1_0_0(WcxrXtYt_1_0_0), + .o_WixrXtYt_1_0_1(WixrXtYt_1_0_1), + .o_WfxrXtYt_1_0_1(WfxrXtYt_1_0_1), + .o_WoxrXtYt_1_0_1(WoxrXtYt_1_0_1), + .o_WcxrXtYt_1_0_1(WcxrXtYt_1_0_1), + .o_WixrXtYt_1_0_2(WixrXtYt_1_0_2), + .o_WfxrXtYt_1_0_2(WfxrXtYt_1_0_2), + .o_WoxrXtYt_1_0_2(WoxrXtYt_1_0_2), + .o_WcxrXtYt_1_0_2(WcxrXtYt_1_0_2), + .o_WixrXtYt_1_0_3(WixrXtYt_1_0_3), + .o_WfxrXtYt_1_0_3(WfxrXtYt_1_0_3), + .o_WoxrXtYt_1_0_3(WoxrXtYt_1_0_3), + .o_WcxrXtYt_1_0_3(WcxrXtYt_1_0_3), + .o_WixrXtYt_1_0_4(WixrXtYt_1_0_4), + .o_WfxrXtYt_1_0_4(WfxrXtYt_1_0_4), + .o_WoxrXtYt_1_0_4(WoxrXtYt_1_0_4), + .o_WcxrXtYt_1_0_4(WcxrXtYt_1_0_4), + .o_WixrXtYt_1_0_5(WixrXtYt_1_0_5), + .o_WfxrXtYt_1_0_5(WfxrXtYt_1_0_5), + .o_WoxrXtYt_1_0_5(WoxrXtYt_1_0_5), + .o_WcxrXtYt_1_0_5(WcxrXtYt_1_0_5), + .o_WixrXtYt_1_0_6(WixrXtYt_1_0_6), + .o_WfxrXtYt_1_0_6(WfxrXtYt_1_0_6), + .o_WoxrXtYt_1_0_6(WoxrXtYt_1_0_6), + .o_WcxrXtYt_1_0_6(WcxrXtYt_1_0_6), + .o_WixrXtYt_1_0_7(WixrXtYt_1_0_7), + .o_WfxrXtYt_1_0_7(WfxrXtYt_1_0_7), + .o_WoxrXtYt_1_0_7(WoxrXtYt_1_0_7), + .o_WcxrXtYt_1_0_7(WcxrXtYt_1_0_7), + .o_WixrXtYt_1_0_8(WixrXtYt_1_0_8), + .o_WfxrXtYt_1_0_8(WfxrXtYt_1_0_8), + .o_WoxrXtYt_1_0_8(WoxrXtYt_1_0_8), + .o_WcxrXtYt_1_0_8(WcxrXtYt_1_0_8), + .o_WixrXtYt_1_0_9(WixrXtYt_1_0_9), + .o_WfxrXtYt_1_0_9(WfxrXtYt_1_0_9), + .o_WoxrXtYt_1_0_9(WoxrXtYt_1_0_9), + .o_WcxrXtYt_1_0_9(WcxrXtYt_1_0_9), + .o_WixrXtYt_1_0_10(WixrXtYt_1_0_10), + .o_WfxrXtYt_1_0_10(WfxrXtYt_1_0_10), + .o_WoxrXtYt_1_0_10(WoxrXtYt_1_0_10), + .o_WcxrXtYt_1_0_10(WcxrXtYt_1_0_10), + .o_WixrXtYt_1_0_11(WixrXtYt_1_0_11), + .o_WfxrXtYt_1_0_11(WfxrXtYt_1_0_11), + .o_WoxrXtYt_1_0_11(WoxrXtYt_1_0_11), + .o_WcxrXtYt_1_0_11(WcxrXtYt_1_0_11), + .o_WixrXtYt_1_0_12(WixrXtYt_1_0_12), + .o_WfxrXtYt_1_0_12(WfxrXtYt_1_0_12), + .o_WoxrXtYt_1_0_12(WoxrXtYt_1_0_12), + .o_WcxrXtYt_1_0_12(WcxrXtYt_1_0_12), + .o_WixrXtYt_1_0_13(WixrXtYt_1_0_13), + .o_WfxrXtYt_1_0_13(WfxrXtYt_1_0_13), + .o_WoxrXtYt_1_0_13(WoxrXtYt_1_0_13), + .o_WcxrXtYt_1_0_13(WcxrXtYt_1_0_13), + .o_WixrXtYt_1_0_14(WixrXtYt_1_0_14), + .o_WfxrXtYt_1_0_14(WfxrXtYt_1_0_14), + .o_WoxrXtYt_1_0_14(WoxrXtYt_1_0_14), + .o_WcxrXtYt_1_0_14(WcxrXtYt_1_0_14), + .o_WixrXtYt_1_0_15(WixrXtYt_1_0_15), + .o_WfxrXtYt_1_0_15(WfxrXtYt_1_0_15), + .o_WoxrXtYt_1_0_15(WoxrXtYt_1_0_15), + .o_WcxrXtYt_1_0_15(WcxrXtYt_1_0_15), + .o_WixrXtYt_1_1_0(WixrXtYt_1_1_0), + .o_WfxrXtYt_1_1_0(WfxrXtYt_1_1_0), + .o_WoxrXtYt_1_1_0(WoxrXtYt_1_1_0), + .o_WcxrXtYt_1_1_0(WcxrXtYt_1_1_0), + .o_WixrXtYt_1_1_1(WixrXtYt_1_1_1), + .o_WfxrXtYt_1_1_1(WfxrXtYt_1_1_1), + .o_WoxrXtYt_1_1_1(WoxrXtYt_1_1_1), + .o_WcxrXtYt_1_1_1(WcxrXtYt_1_1_1), + .o_WixrXtYt_1_1_2(WixrXtYt_1_1_2), + .o_WfxrXtYt_1_1_2(WfxrXtYt_1_1_2), + .o_WoxrXtYt_1_1_2(WoxrXtYt_1_1_2), + .o_WcxrXtYt_1_1_2(WcxrXtYt_1_1_2), + .o_WixrXtYt_1_1_3(WixrXtYt_1_1_3), + .o_WfxrXtYt_1_1_3(WfxrXtYt_1_1_3), + .o_WoxrXtYt_1_1_3(WoxrXtYt_1_1_3), + .o_WcxrXtYt_1_1_3(WcxrXtYt_1_1_3), + .o_WixrXtYt_1_1_4(WixrXtYt_1_1_4), + .o_WfxrXtYt_1_1_4(WfxrXtYt_1_1_4), + .o_WoxrXtYt_1_1_4(WoxrXtYt_1_1_4), + .o_WcxrXtYt_1_1_4(WcxrXtYt_1_1_4), + .o_WixrXtYt_1_1_5(WixrXtYt_1_1_5), + .o_WfxrXtYt_1_1_5(WfxrXtYt_1_1_5), + .o_WoxrXtYt_1_1_5(WoxrXtYt_1_1_5), + .o_WcxrXtYt_1_1_5(WcxrXtYt_1_1_5), + .o_WixrXtYt_1_1_6(WixrXtYt_1_1_6), + .o_WfxrXtYt_1_1_6(WfxrXtYt_1_1_6), + .o_WoxrXtYt_1_1_6(WoxrXtYt_1_1_6), + .o_WcxrXtYt_1_1_6(WcxrXtYt_1_1_6), + .o_WixrXtYt_1_1_7(WixrXtYt_1_1_7), + .o_WfxrXtYt_1_1_7(WfxrXtYt_1_1_7), + .o_WoxrXtYt_1_1_7(WoxrXtYt_1_1_7), + .o_WcxrXtYt_1_1_7(WcxrXtYt_1_1_7), + .o_WixrXtYt_1_1_8(WixrXtYt_1_1_8), + .o_WfxrXtYt_1_1_8(WfxrXtYt_1_1_8), + .o_WoxrXtYt_1_1_8(WoxrXtYt_1_1_8), + .o_WcxrXtYt_1_1_8(WcxrXtYt_1_1_8), + .o_WixrXtYt_1_1_9(WixrXtYt_1_1_9), + .o_WfxrXtYt_1_1_9(WfxrXtYt_1_1_9), + .o_WoxrXtYt_1_1_9(WoxrXtYt_1_1_9), + .o_WcxrXtYt_1_1_9(WcxrXtYt_1_1_9), + .o_WixrXtYt_1_1_10(WixrXtYt_1_1_10), + .o_WfxrXtYt_1_1_10(WfxrXtYt_1_1_10), + .o_WoxrXtYt_1_1_10(WoxrXtYt_1_1_10), + .o_WcxrXtYt_1_1_10(WcxrXtYt_1_1_10), + .o_WixrXtYt_1_1_11(WixrXtYt_1_1_11), + .o_WfxrXtYt_1_1_11(WfxrXtYt_1_1_11), + .o_WoxrXtYt_1_1_11(WoxrXtYt_1_1_11), + .o_WcxrXtYt_1_1_11(WcxrXtYt_1_1_11), + .o_WixrXtYt_1_1_12(WixrXtYt_1_1_12), + .o_WfxrXtYt_1_1_12(WfxrXtYt_1_1_12), + .o_WoxrXtYt_1_1_12(WoxrXtYt_1_1_12), + .o_WcxrXtYt_1_1_12(WcxrXtYt_1_1_12), + .o_WixrXtYt_1_1_13(WixrXtYt_1_1_13), + .o_WfxrXtYt_1_1_13(WfxrXtYt_1_1_13), + .o_WoxrXtYt_1_1_13(WoxrXtYt_1_1_13), + .o_WcxrXtYt_1_1_13(WcxrXtYt_1_1_13), + .o_WixrXtYt_1_1_14(WixrXtYt_1_1_14), + .o_WfxrXtYt_1_1_14(WfxrXtYt_1_1_14), + .o_WoxrXtYt_1_1_14(WoxrXtYt_1_1_14), + .o_WcxrXtYt_1_1_14(WcxrXtYt_1_1_14), + .o_WixrXtYt_1_1_15(WixrXtYt_1_1_15), + .o_WfxrXtYt_1_1_15(WfxrXtYt_1_1_15), + .o_WoxrXtYt_1_1_15(WoxrXtYt_1_1_15), + .o_WcxrXtYt_1_1_15(WcxrXtYt_1_1_15), + .o_WixrXtYt_1_2_0(WixrXtYt_1_2_0), + .o_WfxrXtYt_1_2_0(WfxrXtYt_1_2_0), + .o_WoxrXtYt_1_2_0(WoxrXtYt_1_2_0), + .o_WcxrXtYt_1_2_0(WcxrXtYt_1_2_0), + .o_WixrXtYt_1_2_1(WixrXtYt_1_2_1), + .o_WfxrXtYt_1_2_1(WfxrXtYt_1_2_1), + .o_WoxrXtYt_1_2_1(WoxrXtYt_1_2_1), + .o_WcxrXtYt_1_2_1(WcxrXtYt_1_2_1), + .o_WixrXtYt_1_2_2(WixrXtYt_1_2_2), + .o_WfxrXtYt_1_2_2(WfxrXtYt_1_2_2), + .o_WoxrXtYt_1_2_2(WoxrXtYt_1_2_2), + .o_WcxrXtYt_1_2_2(WcxrXtYt_1_2_2), + .o_WixrXtYt_1_2_3(WixrXtYt_1_2_3), + .o_WfxrXtYt_1_2_3(WfxrXtYt_1_2_3), + .o_WoxrXtYt_1_2_3(WoxrXtYt_1_2_3), + .o_WcxrXtYt_1_2_3(WcxrXtYt_1_2_3), + .o_WixrXtYt_1_2_4(WixrXtYt_1_2_4), + .o_WfxrXtYt_1_2_4(WfxrXtYt_1_2_4), + .o_WoxrXtYt_1_2_4(WoxrXtYt_1_2_4), + .o_WcxrXtYt_1_2_4(WcxrXtYt_1_2_4), + .o_WixrXtYt_1_2_5(WixrXtYt_1_2_5), + .o_WfxrXtYt_1_2_5(WfxrXtYt_1_2_5), + .o_WoxrXtYt_1_2_5(WoxrXtYt_1_2_5), + .o_WcxrXtYt_1_2_5(WcxrXtYt_1_2_5), + .o_WixrXtYt_1_2_6(WixrXtYt_1_2_6), + .o_WfxrXtYt_1_2_6(WfxrXtYt_1_2_6), + .o_WoxrXtYt_1_2_6(WoxrXtYt_1_2_6), + .o_WcxrXtYt_1_2_6(WcxrXtYt_1_2_6), + .o_WixrXtYt_1_2_7(WixrXtYt_1_2_7), + .o_WfxrXtYt_1_2_7(WfxrXtYt_1_2_7), + .o_WoxrXtYt_1_2_7(WoxrXtYt_1_2_7), + .o_WcxrXtYt_1_2_7(WcxrXtYt_1_2_7), + .o_WixrXtYt_1_2_8(WixrXtYt_1_2_8), + .o_WfxrXtYt_1_2_8(WfxrXtYt_1_2_8), + .o_WoxrXtYt_1_2_8(WoxrXtYt_1_2_8), + .o_WcxrXtYt_1_2_8(WcxrXtYt_1_2_8), + .o_WixrXtYt_1_2_9(WixrXtYt_1_2_9), + .o_WfxrXtYt_1_2_9(WfxrXtYt_1_2_9), + .o_WoxrXtYt_1_2_9(WoxrXtYt_1_2_9), + .o_WcxrXtYt_1_2_9(WcxrXtYt_1_2_9), + .o_WixrXtYt_1_2_10(WixrXtYt_1_2_10), + .o_WfxrXtYt_1_2_10(WfxrXtYt_1_2_10), + .o_WoxrXtYt_1_2_10(WoxrXtYt_1_2_10), + .o_WcxrXtYt_1_2_10(WcxrXtYt_1_2_10), + .o_WixrXtYt_1_2_11(WixrXtYt_1_2_11), + .o_WfxrXtYt_1_2_11(WfxrXtYt_1_2_11), + .o_WoxrXtYt_1_2_11(WoxrXtYt_1_2_11), + .o_WcxrXtYt_1_2_11(WcxrXtYt_1_2_11), + .o_WixrXtYt_1_2_12(WixrXtYt_1_2_12), + .o_WfxrXtYt_1_2_12(WfxrXtYt_1_2_12), + .o_WoxrXtYt_1_2_12(WoxrXtYt_1_2_12), + .o_WcxrXtYt_1_2_12(WcxrXtYt_1_2_12), + .o_WixrXtYt_1_2_13(WixrXtYt_1_2_13), + .o_WfxrXtYt_1_2_13(WfxrXtYt_1_2_13), + .o_WoxrXtYt_1_2_13(WoxrXtYt_1_2_13), + .o_WcxrXtYt_1_2_13(WcxrXtYt_1_2_13), + .o_WixrXtYt_1_2_14(WixrXtYt_1_2_14), + .o_WfxrXtYt_1_2_14(WfxrXtYt_1_2_14), + .o_WoxrXtYt_1_2_14(WoxrXtYt_1_2_14), + .o_WcxrXtYt_1_2_14(WcxrXtYt_1_2_14), + .o_WixrXtYt_1_2_15(WixrXtYt_1_2_15), + .o_WfxrXtYt_1_2_15(WfxrXtYt_1_2_15), + .o_WoxrXtYt_1_2_15(WoxrXtYt_1_2_15), + .o_WcxrXtYt_1_2_15(WcxrXtYt_1_2_15), + .i_valid(i_valid_hold) +); + +// Stage 2 connections and parameter buffer +wire stage2_valid, stage2_ready, stage1_valid_hold; +wire [17:0] Ctt_1_0; +wire [17:0] stage2_Ct_0; +wire [17:0] stage2_mt_0; +wire [17:0] WixrXtYt_1_packed_0; +wire [17:0] WfxrXtYt_1_packed_0; +wire [17:0] WoxrXtYt_1_packed_0; +wire [17:0] WcxrXtYt_1_packed_0; +wire [17:0] WixrXtYt_1_hold_0; +wire [17:0] WfxrXtYt_1_hold_0; +wire [17:0] WoxrXtYt_1_hold_0; +wire [17:0] WcxrXtYt_1_hold_0; +wire [17:0] Wic_0; +wire [17:0] bi_0; +wire [17:0] Wfc_0; +wire [17:0] bf_0; +wire [17:0] Woc_0; +wire [17:0] bo_0; +wire [17:0] bc_0; +wire [17:0] Ctt_1_1; +wire [17:0] stage2_Ct_1; +wire [17:0] stage2_mt_1; +wire [17:0] WixrXtYt_1_packed_1; +wire [17:0] WfxrXtYt_1_packed_1; +wire [17:0] WoxrXtYt_1_packed_1; +wire [17:0] WcxrXtYt_1_packed_1; +wire [17:0] WixrXtYt_1_hold_1; +wire [17:0] WfxrXtYt_1_hold_1; +wire [17:0] WoxrXtYt_1_hold_1; +wire [17:0] WcxrXtYt_1_hold_1; +wire [17:0] Wic_1; +wire [17:0] bi_1; +wire [17:0] Wfc_1; +wire [17:0] bf_1; +wire [17:0] Woc_1; +wire [17:0] bo_1; +wire [17:0] bc_1; +wire [17:0] Ctt_1_2; +wire [17:0] stage2_Ct_2; +wire [17:0] stage2_mt_2; +wire [17:0] WixrXtYt_1_packed_2; +wire [17:0] WfxrXtYt_1_packed_2; +wire [17:0] WoxrXtYt_1_packed_2; +wire [17:0] WcxrXtYt_1_packed_2; +wire [17:0] WixrXtYt_1_hold_2; +wire [17:0] WfxrXtYt_1_hold_2; +wire [17:0] WoxrXtYt_1_hold_2; +wire [17:0] WcxrXtYt_1_hold_2; +wire [17:0] Wic_2; +wire [17:0] bi_2; +wire [17:0] Wfc_2; +wire [17:0] bf_2; +wire [17:0] Woc_2; +wire [17:0] bo_2; +wire [17:0] bc_2; +wire [17:0] Ctt_1_3; +wire [17:0] stage2_Ct_3; +wire [17:0] stage2_mt_3; +wire [17:0] WixrXtYt_1_packed_3; +wire [17:0] WfxrXtYt_1_packed_3; +wire [17:0] WoxrXtYt_1_packed_3; +wire [17:0] WcxrXtYt_1_packed_3; +wire [17:0] WixrXtYt_1_hold_3; +wire [17:0] WfxrXtYt_1_hold_3; +wire [17:0] WoxrXtYt_1_hold_3; +wire [17:0] WcxrXtYt_1_hold_3; +wire [17:0] Wic_3; +wire [17:0] bi_3; +wire [17:0] Wfc_3; +wire [17:0] bf_3; +wire [17:0] Woc_3; +wire [17:0] bo_3; +wire [17:0] bc_3; +wire [17:0] Ctt_1_4; +wire [17:0] stage2_Ct_4; +wire [17:0] stage2_mt_4; +wire [17:0] WixrXtYt_1_packed_4; +wire [17:0] WfxrXtYt_1_packed_4; +wire [17:0] WoxrXtYt_1_packed_4; +wire [17:0] WcxrXtYt_1_packed_4; +wire [17:0] WixrXtYt_1_hold_4; +wire [17:0] WfxrXtYt_1_hold_4; +wire [17:0] WoxrXtYt_1_hold_4; +wire [17:0] WcxrXtYt_1_hold_4; +wire [17:0] Wic_4; +wire [17:0] bi_4; +wire [17:0] Wfc_4; +wire [17:0] bf_4; +wire [17:0] Woc_4; +wire [17:0] bo_4; +wire [17:0] bc_4; +wire [17:0] Ctt_1_5; +wire [17:0] stage2_Ct_5; +wire [17:0] stage2_mt_5; +wire [17:0] WixrXtYt_1_packed_5; +wire [17:0] WfxrXtYt_1_packed_5; +wire [17:0] WoxrXtYt_1_packed_5; +wire [17:0] WcxrXtYt_1_packed_5; +wire [17:0] WixrXtYt_1_hold_5; +wire [17:0] WfxrXtYt_1_hold_5; +wire [17:0] WoxrXtYt_1_hold_5; +wire [17:0] WcxrXtYt_1_hold_5; +wire [17:0] Wic_5; +wire [17:0] bi_5; +wire [17:0] Wfc_5; +wire [17:0] bf_5; +wire [17:0] Woc_5; +wire [17:0] bo_5; +wire [17:0] bc_5; +wire [17:0] Ctt_1_6; +wire [17:0] stage2_Ct_6; +wire [17:0] stage2_mt_6; +wire [17:0] WixrXtYt_1_packed_6; +wire [17:0] WfxrXtYt_1_packed_6; +wire [17:0] WoxrXtYt_1_packed_6; +wire [17:0] WcxrXtYt_1_packed_6; +wire [17:0] WixrXtYt_1_hold_6; +wire [17:0] WfxrXtYt_1_hold_6; +wire [17:0] WoxrXtYt_1_hold_6; +wire [17:0] WcxrXtYt_1_hold_6; +wire [17:0] Wic_6; +wire [17:0] bi_6; +wire [17:0] Wfc_6; +wire [17:0] bf_6; +wire [17:0] Woc_6; +wire [17:0] bo_6; +wire [17:0] bc_6; +wire [17:0] Ctt_1_7; +wire [17:0] stage2_Ct_7; +wire [17:0] stage2_mt_7; +wire [17:0] WixrXtYt_1_packed_7; +wire [17:0] WfxrXtYt_1_packed_7; +wire [17:0] WoxrXtYt_1_packed_7; +wire [17:0] WcxrXtYt_1_packed_7; +wire [17:0] WixrXtYt_1_hold_7; +wire [17:0] WfxrXtYt_1_hold_7; +wire [17:0] WoxrXtYt_1_hold_7; +wire [17:0] WcxrXtYt_1_hold_7; +wire [17:0] Wic_7; +wire [17:0] bi_7; +wire [17:0] Wfc_7; +wire [17:0] bf_7; +wire [17:0] Woc_7; +wire [17:0] bo_7; +wire [17:0] bc_7; +wire [17:0] Ctt_1_8; +wire [17:0] stage2_Ct_8; +wire [17:0] stage2_mt_8; +wire [17:0] WixrXtYt_1_packed_8; +wire [17:0] WfxrXtYt_1_packed_8; +wire [17:0] WoxrXtYt_1_packed_8; +wire [17:0] WcxrXtYt_1_packed_8; +wire [17:0] WixrXtYt_1_hold_8; +wire [17:0] WfxrXtYt_1_hold_8; +wire [17:0] WoxrXtYt_1_hold_8; +wire [17:0] WcxrXtYt_1_hold_8; +wire [17:0] Wic_8; +wire [17:0] bi_8; +wire [17:0] Wfc_8; +wire [17:0] bf_8; +wire [17:0] Woc_8; +wire [17:0] bo_8; +wire [17:0] bc_8; +wire [17:0] Ctt_1_9; +wire [17:0] stage2_Ct_9; +wire [17:0] stage2_mt_9; +wire [17:0] WixrXtYt_1_packed_9; +wire [17:0] WfxrXtYt_1_packed_9; +wire [17:0] WoxrXtYt_1_packed_9; +wire [17:0] WcxrXtYt_1_packed_9; +wire [17:0] WixrXtYt_1_hold_9; +wire [17:0] WfxrXtYt_1_hold_9; +wire [17:0] WoxrXtYt_1_hold_9; +wire [17:0] WcxrXtYt_1_hold_9; +wire [17:0] Wic_9; +wire [17:0] bi_9; +wire [17:0] Wfc_9; +wire [17:0] bf_9; +wire [17:0] Woc_9; +wire [17:0] bo_9; +wire [17:0] bc_9; +wire [17:0] Ctt_1_10; +wire [17:0] stage2_Ct_10; +wire [17:0] stage2_mt_10; +wire [17:0] WixrXtYt_1_packed_10; +wire [17:0] WfxrXtYt_1_packed_10; +wire [17:0] WoxrXtYt_1_packed_10; +wire [17:0] WcxrXtYt_1_packed_10; +wire [17:0] WixrXtYt_1_hold_10; +wire [17:0] WfxrXtYt_1_hold_10; +wire [17:0] WoxrXtYt_1_hold_10; +wire [17:0] WcxrXtYt_1_hold_10; +wire [17:0] Wic_10; +wire [17:0] bi_10; +wire [17:0] Wfc_10; +wire [17:0] bf_10; +wire [17:0] Woc_10; +wire [17:0] bo_10; +wire [17:0] bc_10; +wire [17:0] Ctt_1_11; +wire [17:0] stage2_Ct_11; +wire [17:0] stage2_mt_11; +wire [17:0] WixrXtYt_1_packed_11; +wire [17:0] WfxrXtYt_1_packed_11; +wire [17:0] WoxrXtYt_1_packed_11; +wire [17:0] WcxrXtYt_1_packed_11; +wire [17:0] WixrXtYt_1_hold_11; +wire [17:0] WfxrXtYt_1_hold_11; +wire [17:0] WoxrXtYt_1_hold_11; +wire [17:0] WcxrXtYt_1_hold_11; +wire [17:0] Wic_11; +wire [17:0] bi_11; +wire [17:0] Wfc_11; +wire [17:0] bf_11; +wire [17:0] Woc_11; +wire [17:0] bo_11; +wire [17:0] bc_11; +wire [17:0] Ctt_1_12; +wire [17:0] stage2_Ct_12; +wire [17:0] stage2_mt_12; +wire [17:0] WixrXtYt_1_packed_12; +wire [17:0] WfxrXtYt_1_packed_12; +wire [17:0] WoxrXtYt_1_packed_12; +wire [17:0] WcxrXtYt_1_packed_12; +wire [17:0] WixrXtYt_1_hold_12; +wire [17:0] WfxrXtYt_1_hold_12; +wire [17:0] WoxrXtYt_1_hold_12; +wire [17:0] WcxrXtYt_1_hold_12; +wire [17:0] Wic_12; +wire [17:0] bi_12; +wire [17:0] Wfc_12; +wire [17:0] bf_12; +wire [17:0] Woc_12; +wire [17:0] bo_12; +wire [17:0] bc_12; +wire [17:0] Ctt_1_13; +wire [17:0] stage2_Ct_13; +wire [17:0] stage2_mt_13; +wire [17:0] WixrXtYt_1_packed_13; +wire [17:0] WfxrXtYt_1_packed_13; +wire [17:0] WoxrXtYt_1_packed_13; +wire [17:0] WcxrXtYt_1_packed_13; +wire [17:0] WixrXtYt_1_hold_13; +wire [17:0] WfxrXtYt_1_hold_13; +wire [17:0] WoxrXtYt_1_hold_13; +wire [17:0] WcxrXtYt_1_hold_13; +wire [17:0] Wic_13; +wire [17:0] bi_13; +wire [17:0] Wfc_13; +wire [17:0] bf_13; +wire [17:0] Woc_13; +wire [17:0] bo_13; +wire [17:0] bc_13; +wire [17:0] Ctt_1_14; +wire [17:0] stage2_Ct_14; +wire [17:0] stage2_mt_14; +wire [17:0] WixrXtYt_1_packed_14; +wire [17:0] WfxrXtYt_1_packed_14; +wire [17:0] WoxrXtYt_1_packed_14; +wire [17:0] WcxrXtYt_1_packed_14; +wire [17:0] WixrXtYt_1_hold_14; +wire [17:0] WfxrXtYt_1_hold_14; +wire [17:0] WoxrXtYt_1_hold_14; +wire [17:0] WcxrXtYt_1_hold_14; +wire [17:0] Wic_14; +wire [17:0] bi_14; +wire [17:0] Wfc_14; +wire [17:0] bf_14; +wire [17:0] Woc_14; +wire [17:0] bo_14; +wire [17:0] bc_14; +wire [17:0] Ctt_1_15; +wire [17:0] stage2_Ct_15; +wire [17:0] stage2_mt_15; +wire [17:0] WixrXtYt_1_packed_15; +wire [17:0] WfxrXtYt_1_packed_15; +wire [17:0] WoxrXtYt_1_packed_15; +wire [17:0] WcxrXtYt_1_packed_15; +wire [17:0] WixrXtYt_1_hold_15; +wire [17:0] WfxrXtYt_1_hold_15; +wire [17:0] WoxrXtYt_1_hold_15; +wire [17:0] WcxrXtYt_1_hold_15; +wire [17:0] Wic_15; +wire [17:0] bi_15; +wire [17:0] Wfc_15; +wire [17:0] bf_15; +wire [17:0] Woc_15; +wire [17:0] bo_15; +wire [17:0] bc_15; +wire [17:0] Ctt_1_16; +wire [17:0] stage2_Ct_16; +wire [17:0] stage2_mt_16; +wire [17:0] WixrXtYt_1_packed_16; +wire [17:0] WfxrXtYt_1_packed_16; +wire [17:0] WoxrXtYt_1_packed_16; +wire [17:0] WcxrXtYt_1_packed_16; +wire [17:0] WixrXtYt_1_hold_16; +wire [17:0] WfxrXtYt_1_hold_16; +wire [17:0] WoxrXtYt_1_hold_16; +wire [17:0] WcxrXtYt_1_hold_16; +wire [17:0] Wic_16; +wire [17:0] bi_16; +wire [17:0] Wfc_16; +wire [17:0] bf_16; +wire [17:0] Woc_16; +wire [17:0] bo_16; +wire [17:0] bc_16; +wire [17:0] Ctt_1_17; +wire [17:0] stage2_Ct_17; +wire [17:0] stage2_mt_17; +wire [17:0] WixrXtYt_1_packed_17; +wire [17:0] WfxrXtYt_1_packed_17; +wire [17:0] WoxrXtYt_1_packed_17; +wire [17:0] WcxrXtYt_1_packed_17; +wire [17:0] WixrXtYt_1_hold_17; +wire [17:0] WfxrXtYt_1_hold_17; +wire [17:0] WoxrXtYt_1_hold_17; +wire [17:0] WcxrXtYt_1_hold_17; +wire [17:0] Wic_17; +wire [17:0] bi_17; +wire [17:0] Wfc_17; +wire [17:0] bf_17; +wire [17:0] Woc_17; +wire [17:0] bo_17; +wire [17:0] bc_17; +wire [17:0] Ctt_1_18; +wire [17:0] stage2_Ct_18; +wire [17:0] stage2_mt_18; +wire [17:0] WixrXtYt_1_packed_18; +wire [17:0] WfxrXtYt_1_packed_18; +wire [17:0] WoxrXtYt_1_packed_18; +wire [17:0] WcxrXtYt_1_packed_18; +wire [17:0] WixrXtYt_1_hold_18; +wire [17:0] WfxrXtYt_1_hold_18; +wire [17:0] WoxrXtYt_1_hold_18; +wire [17:0] WcxrXtYt_1_hold_18; +wire [17:0] Wic_18; +wire [17:0] bi_18; +wire [17:0] Wfc_18; +wire [17:0] bf_18; +wire [17:0] Woc_18; +wire [17:0] bo_18; +wire [17:0] bc_18; +wire [17:0] Ctt_1_19; +wire [17:0] stage2_Ct_19; +wire [17:0] stage2_mt_19; +wire [17:0] WixrXtYt_1_packed_19; +wire [17:0] WfxrXtYt_1_packed_19; +wire [17:0] WoxrXtYt_1_packed_19; +wire [17:0] WcxrXtYt_1_packed_19; +wire [17:0] WixrXtYt_1_hold_19; +wire [17:0] WfxrXtYt_1_hold_19; +wire [17:0] WoxrXtYt_1_hold_19; +wire [17:0] WcxrXtYt_1_hold_19; +wire [17:0] Wic_19; +wire [17:0] bi_19; +wire [17:0] Wfc_19; +wire [17:0] bf_19; +wire [17:0] Woc_19; +wire [17:0] bo_19; +wire [17:0] bc_19; +wire [17:0] Ctt_1_20; +wire [17:0] stage2_Ct_20; +wire [17:0] stage2_mt_20; +wire [17:0] WixrXtYt_1_packed_20; +wire [17:0] WfxrXtYt_1_packed_20; +wire [17:0] WoxrXtYt_1_packed_20; +wire [17:0] WcxrXtYt_1_packed_20; +wire [17:0] WixrXtYt_1_hold_20; +wire [17:0] WfxrXtYt_1_hold_20; +wire [17:0] WoxrXtYt_1_hold_20; +wire [17:0] WcxrXtYt_1_hold_20; +wire [17:0] Wic_20; +wire [17:0] bi_20; +wire [17:0] Wfc_20; +wire [17:0] bf_20; +wire [17:0] Woc_20; +wire [17:0] bo_20; +wire [17:0] bc_20; +wire [17:0] Ctt_1_21; +wire [17:0] stage2_Ct_21; +wire [17:0] stage2_mt_21; +wire [17:0] WixrXtYt_1_packed_21; +wire [17:0] WfxrXtYt_1_packed_21; +wire [17:0] WoxrXtYt_1_packed_21; +wire [17:0] WcxrXtYt_1_packed_21; +wire [17:0] WixrXtYt_1_hold_21; +wire [17:0] WfxrXtYt_1_hold_21; +wire [17:0] WoxrXtYt_1_hold_21; +wire [17:0] WcxrXtYt_1_hold_21; +wire [17:0] Wic_21; +wire [17:0] bi_21; +wire [17:0] Wfc_21; +wire [17:0] bf_21; +wire [17:0] Woc_21; +wire [17:0] bo_21; +wire [17:0] bc_21; +wire [17:0] Ctt_1_22; +wire [17:0] stage2_Ct_22; +wire [17:0] stage2_mt_22; +wire [17:0] WixrXtYt_1_packed_22; +wire [17:0] WfxrXtYt_1_packed_22; +wire [17:0] WoxrXtYt_1_packed_22; +wire [17:0] WcxrXtYt_1_packed_22; +wire [17:0] WixrXtYt_1_hold_22; +wire [17:0] WfxrXtYt_1_hold_22; +wire [17:0] WoxrXtYt_1_hold_22; +wire [17:0] WcxrXtYt_1_hold_22; +wire [17:0] Wic_22; +wire [17:0] bi_22; +wire [17:0] Wfc_22; +wire [17:0] bf_22; +wire [17:0] Woc_22; +wire [17:0] bo_22; +wire [17:0] bc_22; +wire [17:0] Ctt_1_23; +wire [17:0] stage2_Ct_23; +wire [17:0] stage2_mt_23; +wire [17:0] WixrXtYt_1_packed_23; +wire [17:0] WfxrXtYt_1_packed_23; +wire [17:0] WoxrXtYt_1_packed_23; +wire [17:0] WcxrXtYt_1_packed_23; +wire [17:0] WixrXtYt_1_hold_23; +wire [17:0] WfxrXtYt_1_hold_23; +wire [17:0] WoxrXtYt_1_hold_23; +wire [17:0] WcxrXtYt_1_hold_23; +wire [17:0] Wic_23; +wire [17:0] bi_23; +wire [17:0] Wfc_23; +wire [17:0] bf_23; +wire [17:0] Woc_23; +wire [17:0] bo_23; +wire [17:0] bc_23; +wire [17:0] Ctt_1_24; +wire [17:0] stage2_Ct_24; +wire [17:0] stage2_mt_24; +wire [17:0] WixrXtYt_1_packed_24; +wire [17:0] WfxrXtYt_1_packed_24; +wire [17:0] WoxrXtYt_1_packed_24; +wire [17:0] WcxrXtYt_1_packed_24; +wire [17:0] WixrXtYt_1_hold_24; +wire [17:0] WfxrXtYt_1_hold_24; +wire [17:0] WoxrXtYt_1_hold_24; +wire [17:0] WcxrXtYt_1_hold_24; +wire [17:0] Wic_24; +wire [17:0] bi_24; +wire [17:0] Wfc_24; +wire [17:0] bf_24; +wire [17:0] Woc_24; +wire [17:0] bo_24; +wire [17:0] bc_24; +wire [17:0] Ctt_1_25; +wire [17:0] stage2_Ct_25; +wire [17:0] stage2_mt_25; +wire [17:0] WixrXtYt_1_packed_25; +wire [17:0] WfxrXtYt_1_packed_25; +wire [17:0] WoxrXtYt_1_packed_25; +wire [17:0] WcxrXtYt_1_packed_25; +wire [17:0] WixrXtYt_1_hold_25; +wire [17:0] WfxrXtYt_1_hold_25; +wire [17:0] WoxrXtYt_1_hold_25; +wire [17:0] WcxrXtYt_1_hold_25; +wire [17:0] Wic_25; +wire [17:0] bi_25; +wire [17:0] Wfc_25; +wire [17:0] bf_25; +wire [17:0] Woc_25; +wire [17:0] bo_25; +wire [17:0] bc_25; +wire [17:0] Ctt_1_26; +wire [17:0] stage2_Ct_26; +wire [17:0] stage2_mt_26; +wire [17:0] WixrXtYt_1_packed_26; +wire [17:0] WfxrXtYt_1_packed_26; +wire [17:0] WoxrXtYt_1_packed_26; +wire [17:0] WcxrXtYt_1_packed_26; +wire [17:0] WixrXtYt_1_hold_26; +wire [17:0] WfxrXtYt_1_hold_26; +wire [17:0] WoxrXtYt_1_hold_26; +wire [17:0] WcxrXtYt_1_hold_26; +wire [17:0] Wic_26; +wire [17:0] bi_26; +wire [17:0] Wfc_26; +wire [17:0] bf_26; +wire [17:0] Woc_26; +wire [17:0] bo_26; +wire [17:0] bc_26; +wire [17:0] Ctt_1_27; +wire [17:0] stage2_Ct_27; +wire [17:0] stage2_mt_27; +wire [17:0] WixrXtYt_1_packed_27; +wire [17:0] WfxrXtYt_1_packed_27; +wire [17:0] WoxrXtYt_1_packed_27; +wire [17:0] WcxrXtYt_1_packed_27; +wire [17:0] WixrXtYt_1_hold_27; +wire [17:0] WfxrXtYt_1_hold_27; +wire [17:0] WoxrXtYt_1_hold_27; +wire [17:0] WcxrXtYt_1_hold_27; +wire [17:0] Wic_27; +wire [17:0] bi_27; +wire [17:0] Wfc_27; +wire [17:0] bf_27; +wire [17:0] Woc_27; +wire [17:0] bo_27; +wire [17:0] bc_27; +wire [17:0] Ctt_1_28; +wire [17:0] stage2_Ct_28; +wire [17:0] stage2_mt_28; +wire [17:0] WixrXtYt_1_packed_28; +wire [17:0] WfxrXtYt_1_packed_28; +wire [17:0] WoxrXtYt_1_packed_28; +wire [17:0] WcxrXtYt_1_packed_28; +wire [17:0] WixrXtYt_1_hold_28; +wire [17:0] WfxrXtYt_1_hold_28; +wire [17:0] WoxrXtYt_1_hold_28; +wire [17:0] WcxrXtYt_1_hold_28; +wire [17:0] Wic_28; +wire [17:0] bi_28; +wire [17:0] Wfc_28; +wire [17:0] bf_28; +wire [17:0] Woc_28; +wire [17:0] bo_28; +wire [17:0] bc_28; +wire [17:0] Ctt_1_29; +wire [17:0] stage2_Ct_29; +wire [17:0] stage2_mt_29; +wire [17:0] WixrXtYt_1_packed_29; +wire [17:0] WfxrXtYt_1_packed_29; +wire [17:0] WoxrXtYt_1_packed_29; +wire [17:0] WcxrXtYt_1_packed_29; +wire [17:0] WixrXtYt_1_hold_29; +wire [17:0] WfxrXtYt_1_hold_29; +wire [17:0] WoxrXtYt_1_hold_29; +wire [17:0] WcxrXtYt_1_hold_29; +wire [17:0] Wic_29; +wire [17:0] bi_29; +wire [17:0] Wfc_29; +wire [17:0] bf_29; +wire [17:0] Woc_29; +wire [17:0] bo_29; +wire [17:0] bc_29; +wire [17:0] Ctt_1_30; +wire [17:0] stage2_Ct_30; +wire [17:0] stage2_mt_30; +wire [17:0] WixrXtYt_1_packed_30; +wire [17:0] WfxrXtYt_1_packed_30; +wire [17:0] WoxrXtYt_1_packed_30; +wire [17:0] WcxrXtYt_1_packed_30; +wire [17:0] WixrXtYt_1_hold_30; +wire [17:0] WfxrXtYt_1_hold_30; +wire [17:0] WoxrXtYt_1_hold_30; +wire [17:0] WcxrXtYt_1_hold_30; +wire [17:0] Wic_30; +wire [17:0] bi_30; +wire [17:0] Wfc_30; +wire [17:0] bf_30; +wire [17:0] Woc_30; +wire [17:0] bo_30; +wire [17:0] bc_30; +wire [17:0] Ctt_1_31; +wire [17:0] stage2_Ct_31; +wire [17:0] stage2_mt_31; +wire [17:0] WixrXtYt_1_packed_31; +wire [17:0] WfxrXtYt_1_packed_31; +wire [17:0] WoxrXtYt_1_packed_31; +wire [17:0] WcxrXtYt_1_packed_31; +wire [17:0] WixrXtYt_1_hold_31; +wire [17:0] WfxrXtYt_1_hold_31; +wire [17:0] WoxrXtYt_1_hold_31; +wire [17:0] WcxrXtYt_1_hold_31; +wire [17:0] Wic_31; +wire [17:0] bi_31; +wire [17:0] Wfc_31; +wire [17:0] bf_31; +wire [17:0] Woc_31; +wire [17:0] bo_31; +wire [17:0] bc_31; +wire [17:0] Ctt_1_32; +wire [17:0] stage2_Ct_32; +wire [17:0] stage2_mt_32; +wire [17:0] WixrXtYt_1_packed_32; +wire [17:0] WfxrXtYt_1_packed_32; +wire [17:0] WoxrXtYt_1_packed_32; +wire [17:0] WcxrXtYt_1_packed_32; +wire [17:0] WixrXtYt_1_hold_32; +wire [17:0] WfxrXtYt_1_hold_32; +wire [17:0] WoxrXtYt_1_hold_32; +wire [17:0] WcxrXtYt_1_hold_32; +wire [17:0] Wic_32; +wire [17:0] bi_32; +wire [17:0] Wfc_32; +wire [17:0] bf_32; +wire [17:0] Woc_32; +wire [17:0] bo_32; +wire [17:0] bc_32; +wire [17:0] Ctt_1_33; +wire [17:0] stage2_Ct_33; +wire [17:0] stage2_mt_33; +wire [17:0] WixrXtYt_1_packed_33; +wire [17:0] WfxrXtYt_1_packed_33; +wire [17:0] WoxrXtYt_1_packed_33; +wire [17:0] WcxrXtYt_1_packed_33; +wire [17:0] WixrXtYt_1_hold_33; +wire [17:0] WfxrXtYt_1_hold_33; +wire [17:0] WoxrXtYt_1_hold_33; +wire [17:0] WcxrXtYt_1_hold_33; +wire [17:0] Wic_33; +wire [17:0] bi_33; +wire [17:0] Wfc_33; +wire [17:0] bf_33; +wire [17:0] Woc_33; +wire [17:0] bo_33; +wire [17:0] bc_33; +wire [17:0] Ctt_1_34; +wire [17:0] stage2_Ct_34; +wire [17:0] stage2_mt_34; +wire [17:0] WixrXtYt_1_packed_34; +wire [17:0] WfxrXtYt_1_packed_34; +wire [17:0] WoxrXtYt_1_packed_34; +wire [17:0] WcxrXtYt_1_packed_34; +wire [17:0] WixrXtYt_1_hold_34; +wire [17:0] WfxrXtYt_1_hold_34; +wire [17:0] WoxrXtYt_1_hold_34; +wire [17:0] WcxrXtYt_1_hold_34; +wire [17:0] Wic_34; +wire [17:0] bi_34; +wire [17:0] Wfc_34; +wire [17:0] bf_34; +wire [17:0] Woc_34; +wire [17:0] bo_34; +wire [17:0] bc_34; +wire [17:0] Ctt_1_35; +wire [17:0] stage2_Ct_35; +wire [17:0] stage2_mt_35; +wire [17:0] WixrXtYt_1_packed_35; +wire [17:0] WfxrXtYt_1_packed_35; +wire [17:0] WoxrXtYt_1_packed_35; +wire [17:0] WcxrXtYt_1_packed_35; +wire [17:0] WixrXtYt_1_hold_35; +wire [17:0] WfxrXtYt_1_hold_35; +wire [17:0] WoxrXtYt_1_hold_35; +wire [17:0] WcxrXtYt_1_hold_35; +wire [17:0] Wic_35; +wire [17:0] bi_35; +wire [17:0] Wfc_35; +wire [17:0] bf_35; +wire [17:0] Woc_35; +wire [17:0] bo_35; +wire [17:0] bc_35; +wire [17:0] Ctt_1_36; +wire [17:0] stage2_Ct_36; +wire [17:0] stage2_mt_36; +wire [17:0] WixrXtYt_1_packed_36; +wire [17:0] WfxrXtYt_1_packed_36; +wire [17:0] WoxrXtYt_1_packed_36; +wire [17:0] WcxrXtYt_1_packed_36; +wire [17:0] WixrXtYt_1_hold_36; +wire [17:0] WfxrXtYt_1_hold_36; +wire [17:0] WoxrXtYt_1_hold_36; +wire [17:0] WcxrXtYt_1_hold_36; +wire [17:0] Wic_36; +wire [17:0] bi_36; +wire [17:0] Wfc_36; +wire [17:0] bf_36; +wire [17:0] Woc_36; +wire [17:0] bo_36; +wire [17:0] bc_36; +wire [17:0] Ctt_1_37; +wire [17:0] stage2_Ct_37; +wire [17:0] stage2_mt_37; +wire [17:0] WixrXtYt_1_packed_37; +wire [17:0] WfxrXtYt_1_packed_37; +wire [17:0] WoxrXtYt_1_packed_37; +wire [17:0] WcxrXtYt_1_packed_37; +wire [17:0] WixrXtYt_1_hold_37; +wire [17:0] WfxrXtYt_1_hold_37; +wire [17:0] WoxrXtYt_1_hold_37; +wire [17:0] WcxrXtYt_1_hold_37; +wire [17:0] Wic_37; +wire [17:0] bi_37; +wire [17:0] Wfc_37; +wire [17:0] bf_37; +wire [17:0] Woc_37; +wire [17:0] bo_37; +wire [17:0] bc_37; +wire [17:0] Ctt_1_38; +wire [17:0] stage2_Ct_38; +wire [17:0] stage2_mt_38; +wire [17:0] WixrXtYt_1_packed_38; +wire [17:0] WfxrXtYt_1_packed_38; +wire [17:0] WoxrXtYt_1_packed_38; +wire [17:0] WcxrXtYt_1_packed_38; +wire [17:0] WixrXtYt_1_hold_38; +wire [17:0] WfxrXtYt_1_hold_38; +wire [17:0] WoxrXtYt_1_hold_38; +wire [17:0] WcxrXtYt_1_hold_38; +wire [17:0] Wic_38; +wire [17:0] bi_38; +wire [17:0] Wfc_38; +wire [17:0] bf_38; +wire [17:0] Woc_38; +wire [17:0] bo_38; +wire [17:0] bc_38; +wire [17:0] Ctt_1_39; +wire [17:0] stage2_Ct_39; +wire [17:0] stage2_mt_39; +wire [17:0] WixrXtYt_1_packed_39; +wire [17:0] WfxrXtYt_1_packed_39; +wire [17:0] WoxrXtYt_1_packed_39; +wire [17:0] WcxrXtYt_1_packed_39; +wire [17:0] WixrXtYt_1_hold_39; +wire [17:0] WfxrXtYt_1_hold_39; +wire [17:0] WoxrXtYt_1_hold_39; +wire [17:0] WcxrXtYt_1_hold_39; +wire [17:0] Wic_39; +wire [17:0] bi_39; +wire [17:0] Wfc_39; +wire [17:0] bf_39; +wire [17:0] Woc_39; +wire [17:0] bo_39; +wire [17:0] bc_39; +wire [17:0] Ctt_1_40; +wire [17:0] stage2_Ct_40; +wire [17:0] stage2_mt_40; +wire [17:0] WixrXtYt_1_packed_40; +wire [17:0] WfxrXtYt_1_packed_40; +wire [17:0] WoxrXtYt_1_packed_40; +wire [17:0] WcxrXtYt_1_packed_40; +wire [17:0] WixrXtYt_1_hold_40; +wire [17:0] WfxrXtYt_1_hold_40; +wire [17:0] WoxrXtYt_1_hold_40; +wire [17:0] WcxrXtYt_1_hold_40; +wire [17:0] Wic_40; +wire [17:0] bi_40; +wire [17:0] Wfc_40; +wire [17:0] bf_40; +wire [17:0] Woc_40; +wire [17:0] bo_40; +wire [17:0] bc_40; +wire [17:0] Ctt_1_41; +wire [17:0] stage2_Ct_41; +wire [17:0] stage2_mt_41; +wire [17:0] WixrXtYt_1_packed_41; +wire [17:0] WfxrXtYt_1_packed_41; +wire [17:0] WoxrXtYt_1_packed_41; +wire [17:0] WcxrXtYt_1_packed_41; +wire [17:0] WixrXtYt_1_hold_41; +wire [17:0] WfxrXtYt_1_hold_41; +wire [17:0] WoxrXtYt_1_hold_41; +wire [17:0] WcxrXtYt_1_hold_41; +wire [17:0] Wic_41; +wire [17:0] bi_41; +wire [17:0] Wfc_41; +wire [17:0] bf_41; +wire [17:0] Woc_41; +wire [17:0] bo_41; +wire [17:0] bc_41; +wire [17:0] Ctt_1_42; +wire [17:0] stage2_Ct_42; +wire [17:0] stage2_mt_42; +wire [17:0] WixrXtYt_1_packed_42; +wire [17:0] WfxrXtYt_1_packed_42; +wire [17:0] WoxrXtYt_1_packed_42; +wire [17:0] WcxrXtYt_1_packed_42; +wire [17:0] WixrXtYt_1_hold_42; +wire [17:0] WfxrXtYt_1_hold_42; +wire [17:0] WoxrXtYt_1_hold_42; +wire [17:0] WcxrXtYt_1_hold_42; +wire [17:0] Wic_42; +wire [17:0] bi_42; +wire [17:0] Wfc_42; +wire [17:0] bf_42; +wire [17:0] Woc_42; +wire [17:0] bo_42; +wire [17:0] bc_42; +wire [17:0] Ctt_1_43; +wire [17:0] stage2_Ct_43; +wire [17:0] stage2_mt_43; +wire [17:0] WixrXtYt_1_packed_43; +wire [17:0] WfxrXtYt_1_packed_43; +wire [17:0] WoxrXtYt_1_packed_43; +wire [17:0] WcxrXtYt_1_packed_43; +wire [17:0] WixrXtYt_1_hold_43; +wire [17:0] WfxrXtYt_1_hold_43; +wire [17:0] WoxrXtYt_1_hold_43; +wire [17:0] WcxrXtYt_1_hold_43; +wire [17:0] Wic_43; +wire [17:0] bi_43; +wire [17:0] Wfc_43; +wire [17:0] bf_43; +wire [17:0] Woc_43; +wire [17:0] bo_43; +wire [17:0] bc_43; +wire [17:0] Ctt_1_44; +wire [17:0] stage2_Ct_44; +wire [17:0] stage2_mt_44; +wire [17:0] WixrXtYt_1_packed_44; +wire [17:0] WfxrXtYt_1_packed_44; +wire [17:0] WoxrXtYt_1_packed_44; +wire [17:0] WcxrXtYt_1_packed_44; +wire [17:0] WixrXtYt_1_hold_44; +wire [17:0] WfxrXtYt_1_hold_44; +wire [17:0] WoxrXtYt_1_hold_44; +wire [17:0] WcxrXtYt_1_hold_44; +wire [17:0] Wic_44; +wire [17:0] bi_44; +wire [17:0] Wfc_44; +wire [17:0] bf_44; +wire [17:0] Woc_44; +wire [17:0] bo_44; +wire [17:0] bc_44; +wire [17:0] Ctt_1_45; +wire [17:0] stage2_Ct_45; +wire [17:0] stage2_mt_45; +wire [17:0] WixrXtYt_1_packed_45; +wire [17:0] WfxrXtYt_1_packed_45; +wire [17:0] WoxrXtYt_1_packed_45; +wire [17:0] WcxrXtYt_1_packed_45; +wire [17:0] WixrXtYt_1_hold_45; +wire [17:0] WfxrXtYt_1_hold_45; +wire [17:0] WoxrXtYt_1_hold_45; +wire [17:0] WcxrXtYt_1_hold_45; +wire [17:0] Wic_45; +wire [17:0] bi_45; +wire [17:0] Wfc_45; +wire [17:0] bf_45; +wire [17:0] Woc_45; +wire [17:0] bo_45; +wire [17:0] bc_45; +wire [17:0] Ctt_1_46; +wire [17:0] stage2_Ct_46; +wire [17:0] stage2_mt_46; +wire [17:0] WixrXtYt_1_packed_46; +wire [17:0] WfxrXtYt_1_packed_46; +wire [17:0] WoxrXtYt_1_packed_46; +wire [17:0] WcxrXtYt_1_packed_46; +wire [17:0] WixrXtYt_1_hold_46; +wire [17:0] WfxrXtYt_1_hold_46; +wire [17:0] WoxrXtYt_1_hold_46; +wire [17:0] WcxrXtYt_1_hold_46; +wire [17:0] Wic_46; +wire [17:0] bi_46; +wire [17:0] Wfc_46; +wire [17:0] bf_46; +wire [17:0] Woc_46; +wire [17:0] bo_46; +wire [17:0] bc_46; +wire [17:0] Ctt_1_47; +wire [17:0] stage2_Ct_47; +wire [17:0] stage2_mt_47; +wire [17:0] WixrXtYt_1_packed_47; +wire [17:0] WfxrXtYt_1_packed_47; +wire [17:0] WoxrXtYt_1_packed_47; +wire [17:0] WcxrXtYt_1_packed_47; +wire [17:0] WixrXtYt_1_hold_47; +wire [17:0] WfxrXtYt_1_hold_47; +wire [17:0] WoxrXtYt_1_hold_47; +wire [17:0] WcxrXtYt_1_hold_47; +wire [17:0] Wic_47; +wire [17:0] bi_47; +wire [17:0] Wfc_47; +wire [17:0] bf_47; +wire [17:0] Woc_47; +wire [17:0] bo_47; +wire [17:0] bc_47; + +stage2_parameter_buffer_18_3_16_64 stage2_parameter_buffer_18_3_16_64_inst_dgndfosztp ( + .clk(clk), + .reset(reset), + .wdata(wdata_stage2), + .wen(wen_stage2), + .o_Wic_0(Wic_0), + .o_bi_0(bi_0), + .o_Wfc_0(Wfc_0), + .o_bf_0(bf_0), + .o_Woc_0(Woc_0), + .o_bo_0(bo_0), + .o_bc_0(bc_0), + .o_Wic_1(Wic_1), + .o_bi_1(bi_1), + .o_Wfc_1(Wfc_1), + .o_bf_1(bf_1), + .o_Woc_1(Woc_1), + .o_bo_1(bo_1), + .o_bc_1(bc_1), + .o_Wic_2(Wic_2), + .o_bi_2(bi_2), + .o_Wfc_2(Wfc_2), + .o_bf_2(bf_2), + .o_Woc_2(Woc_2), + .o_bo_2(bo_2), + .o_bc_2(bc_2), + .o_Wic_3(Wic_3), + .o_bi_3(bi_3), + .o_Wfc_3(Wfc_3), + .o_bf_3(bf_3), + .o_Woc_3(Woc_3), + .o_bo_3(bo_3), + .o_bc_3(bc_3), + .o_Wic_4(Wic_4), + .o_bi_4(bi_4), + .o_Wfc_4(Wfc_4), + .o_bf_4(bf_4), + .o_Woc_4(Woc_4), + .o_bo_4(bo_4), + .o_bc_4(bc_4), + .o_Wic_5(Wic_5), + .o_bi_5(bi_5), + .o_Wfc_5(Wfc_5), + .o_bf_5(bf_5), + .o_Woc_5(Woc_5), + .o_bo_5(bo_5), + .o_bc_5(bc_5), + .o_Wic_6(Wic_6), + .o_bi_6(bi_6), + .o_Wfc_6(Wfc_6), + .o_bf_6(bf_6), + .o_Woc_6(Woc_6), + .o_bo_6(bo_6), + .o_bc_6(bc_6), + .o_Wic_7(Wic_7), + .o_bi_7(bi_7), + .o_Wfc_7(Wfc_7), + .o_bf_7(bf_7), + .o_Woc_7(Woc_7), + .o_bo_7(bo_7), + .o_bc_7(bc_7), + .o_Wic_8(Wic_8), + .o_bi_8(bi_8), + .o_Wfc_8(Wfc_8), + .o_bf_8(bf_8), + .o_Woc_8(Woc_8), + .o_bo_8(bo_8), + .o_bc_8(bc_8), + .o_Wic_9(Wic_9), + .o_bi_9(bi_9), + .o_Wfc_9(Wfc_9), + .o_bf_9(bf_9), + .o_Woc_9(Woc_9), + .o_bo_9(bo_9), + .o_bc_9(bc_9), + .o_Wic_10(Wic_10), + .o_bi_10(bi_10), + .o_Wfc_10(Wfc_10), + .o_bf_10(bf_10), + .o_Woc_10(Woc_10), + .o_bo_10(bo_10), + .o_bc_10(bc_10), + .o_Wic_11(Wic_11), + .o_bi_11(bi_11), + .o_Wfc_11(Wfc_11), + .o_bf_11(bf_11), + .o_Woc_11(Woc_11), + .o_bo_11(bo_11), + .o_bc_11(bc_11), + .o_Wic_12(Wic_12), + .o_bi_12(bi_12), + .o_Wfc_12(Wfc_12), + .o_bf_12(bf_12), + .o_Woc_12(Woc_12), + .o_bo_12(bo_12), + .o_bc_12(bc_12), + .o_Wic_13(Wic_13), + .o_bi_13(bi_13), + .o_Wfc_13(Wfc_13), + .o_bf_13(bf_13), + .o_Woc_13(Woc_13), + .o_bo_13(bo_13), + .o_bc_13(bc_13), + .o_Wic_14(Wic_14), + .o_bi_14(bi_14), + .o_Wfc_14(Wfc_14), + .o_bf_14(bf_14), + .o_Woc_14(Woc_14), + .o_bo_14(bo_14), + .o_bc_14(bc_14), + .o_Wic_15(Wic_15), + .o_bi_15(bi_15), + .o_Wfc_15(Wfc_15), + .o_bf_15(bf_15), + .o_Woc_15(Woc_15), + .o_bo_15(bo_15), + .o_bc_15(bc_15), + .o_Wic_16(Wic_16), + .o_bi_16(bi_16), + .o_Wfc_16(Wfc_16), + .o_bf_16(bf_16), + .o_Woc_16(Woc_16), + .o_bo_16(bo_16), + .o_bc_16(bc_16), + .o_Wic_17(Wic_17), + .o_bi_17(bi_17), + .o_Wfc_17(Wfc_17), + .o_bf_17(bf_17), + .o_Woc_17(Woc_17), + .o_bo_17(bo_17), + .o_bc_17(bc_17), + .o_Wic_18(Wic_18), + .o_bi_18(bi_18), + .o_Wfc_18(Wfc_18), + .o_bf_18(bf_18), + .o_Woc_18(Woc_18), + .o_bo_18(bo_18), + .o_bc_18(bc_18), + .o_Wic_19(Wic_19), + .o_bi_19(bi_19), + .o_Wfc_19(Wfc_19), + .o_bf_19(bf_19), + .o_Woc_19(Woc_19), + .o_bo_19(bo_19), + .o_bc_19(bc_19), + .o_Wic_20(Wic_20), + .o_bi_20(bi_20), + .o_Wfc_20(Wfc_20), + .o_bf_20(bf_20), + .o_Woc_20(Woc_20), + .o_bo_20(bo_20), + .o_bc_20(bc_20), + .o_Wic_21(Wic_21), + .o_bi_21(bi_21), + .o_Wfc_21(Wfc_21), + .o_bf_21(bf_21), + .o_Woc_21(Woc_21), + .o_bo_21(bo_21), + .o_bc_21(bc_21), + .o_Wic_22(Wic_22), + .o_bi_22(bi_22), + .o_Wfc_22(Wfc_22), + .o_bf_22(bf_22), + .o_Woc_22(Woc_22), + .o_bo_22(bo_22), + .o_bc_22(bc_22), + .o_Wic_23(Wic_23), + .o_bi_23(bi_23), + .o_Wfc_23(Wfc_23), + .o_bf_23(bf_23), + .o_Woc_23(Woc_23), + .o_bo_23(bo_23), + .o_bc_23(bc_23), + .o_Wic_24(Wic_24), + .o_bi_24(bi_24), + .o_Wfc_24(Wfc_24), + .o_bf_24(bf_24), + .o_Woc_24(Woc_24), + .o_bo_24(bo_24), + .o_bc_24(bc_24), + .o_Wic_25(Wic_25), + .o_bi_25(bi_25), + .o_Wfc_25(Wfc_25), + .o_bf_25(bf_25), + .o_Woc_25(Woc_25), + .o_bo_25(bo_25), + .o_bc_25(bc_25), + .o_Wic_26(Wic_26), + .o_bi_26(bi_26), + .o_Wfc_26(Wfc_26), + .o_bf_26(bf_26), + .o_Woc_26(Woc_26), + .o_bo_26(bo_26), + .o_bc_26(bc_26), + .o_Wic_27(Wic_27), + .o_bi_27(bi_27), + .o_Wfc_27(Wfc_27), + .o_bf_27(bf_27), + .o_Woc_27(Woc_27), + .o_bo_27(bo_27), + .o_bc_27(bc_27), + .o_Wic_28(Wic_28), + .o_bi_28(bi_28), + .o_Wfc_28(Wfc_28), + .o_bf_28(bf_28), + .o_Woc_28(Woc_28), + .o_bo_28(bo_28), + .o_bc_28(bc_28), + .o_Wic_29(Wic_29), + .o_bi_29(bi_29), + .o_Wfc_29(Wfc_29), + .o_bf_29(bf_29), + .o_Woc_29(Woc_29), + .o_bo_29(bo_29), + .o_bc_29(bc_29), + .o_Wic_30(Wic_30), + .o_bi_30(bi_30), + .o_Wfc_30(Wfc_30), + .o_bf_30(bf_30), + .o_Woc_30(Woc_30), + .o_bo_30(bo_30), + .o_bc_30(bc_30), + .o_Wic_31(Wic_31), + .o_bi_31(bi_31), + .o_Wfc_31(Wfc_31), + .o_bf_31(bf_31), + .o_Woc_31(Woc_31), + .o_bo_31(bo_31), + .o_bc_31(bc_31), + .o_Wic_32(Wic_32), + .o_bi_32(bi_32), + .o_Wfc_32(Wfc_32), + .o_bf_32(bf_32), + .o_Woc_32(Woc_32), + .o_bo_32(bo_32), + .o_bc_32(bc_32), + .o_Wic_33(Wic_33), + .o_bi_33(bi_33), + .o_Wfc_33(Wfc_33), + .o_bf_33(bf_33), + .o_Woc_33(Woc_33), + .o_bo_33(bo_33), + .o_bc_33(bc_33), + .o_Wic_34(Wic_34), + .o_bi_34(bi_34), + .o_Wfc_34(Wfc_34), + .o_bf_34(bf_34), + .o_Woc_34(Woc_34), + .o_bo_34(bo_34), + .o_bc_34(bc_34), + .o_Wic_35(Wic_35), + .o_bi_35(bi_35), + .o_Wfc_35(Wfc_35), + .o_bf_35(bf_35), + .o_Woc_35(Woc_35), + .o_bo_35(bo_35), + .o_bc_35(bc_35), + .o_Wic_36(Wic_36), + .o_bi_36(bi_36), + .o_Wfc_36(Wfc_36), + .o_bf_36(bf_36), + .o_Woc_36(Woc_36), + .o_bo_36(bo_36), + .o_bc_36(bc_36), + .o_Wic_37(Wic_37), + .o_bi_37(bi_37), + .o_Wfc_37(Wfc_37), + .o_bf_37(bf_37), + .o_Woc_37(Woc_37), + .o_bo_37(bo_37), + .o_bc_37(bc_37), + .o_Wic_38(Wic_38), + .o_bi_38(bi_38), + .o_Wfc_38(Wfc_38), + .o_bf_38(bf_38), + .o_Woc_38(Woc_38), + .o_bo_38(bo_38), + .o_bc_38(bc_38), + .o_Wic_39(Wic_39), + .o_bi_39(bi_39), + .o_Wfc_39(Wfc_39), + .o_bf_39(bf_39), + .o_Woc_39(Woc_39), + .o_bo_39(bo_39), + .o_bc_39(bc_39), + .o_Wic_40(Wic_40), + .o_bi_40(bi_40), + .o_Wfc_40(Wfc_40), + .o_bf_40(bf_40), + .o_Woc_40(Woc_40), + .o_bo_40(bo_40), + .o_bc_40(bc_40), + .o_Wic_41(Wic_41), + .o_bi_41(bi_41), + .o_Wfc_41(Wfc_41), + .o_bf_41(bf_41), + .o_Woc_41(Woc_41), + .o_bo_41(bo_41), + .o_bc_41(bc_41), + .o_Wic_42(Wic_42), + .o_bi_42(bi_42), + .o_Wfc_42(Wfc_42), + .o_bf_42(bf_42), + .o_Woc_42(Woc_42), + .o_bo_42(bo_42), + .o_bc_42(bc_42), + .o_Wic_43(Wic_43), + .o_bi_43(bi_43), + .o_Wfc_43(Wfc_43), + .o_bf_43(bf_43), + .o_Woc_43(Woc_43), + .o_bo_43(bo_43), + .o_bc_43(bc_43), + .o_Wic_44(Wic_44), + .o_bi_44(bi_44), + .o_Wfc_44(Wfc_44), + .o_bf_44(bf_44), + .o_Woc_44(Woc_44), + .o_bo_44(bo_44), + .o_bc_44(bc_44), + .o_Wic_45(Wic_45), + .o_bi_45(bi_45), + .o_Wfc_45(Wfc_45), + .o_bf_45(bf_45), + .o_Woc_45(Woc_45), + .o_bo_45(bo_45), + .o_bc_45(bc_45), + .o_Wic_46(Wic_46), + .o_bi_46(bi_46), + .o_Wfc_46(Wfc_46), + .o_bf_46(bf_46), + .o_Woc_46(Woc_46), + .o_bo_46(bo_46), + .o_bc_46(bc_46), + .o_Wic_47(Wic_47), + .o_bi_47(bi_47), + .o_Wfc_47(Wfc_47), + .o_bf_47(bf_47), + .o_Woc_47(Woc_47), + .o_bo_47(bo_47), + .o_bc_47(bc_47), + .incr_index(stage1_valid) +); + +assign WixrXtYt_1_packed_0 = WixrXtYt_1_0_0; +assign WfxrXtYt_1_packed_0 = WfxrXtYt_1_0_0; +assign WoxrXtYt_1_packed_0 = WoxrXtYt_1_0_0; +assign WcxrXtYt_1_packed_0 = WcxrXtYt_1_0_0; +assign WixrXtYt_1_packed_1 = WixrXtYt_1_0_1; +assign WfxrXtYt_1_packed_1 = WfxrXtYt_1_0_1; +assign WoxrXtYt_1_packed_1 = WoxrXtYt_1_0_1; +assign WcxrXtYt_1_packed_1 = WcxrXtYt_1_0_1; +assign WixrXtYt_1_packed_2 = WixrXtYt_1_0_2; +assign WfxrXtYt_1_packed_2 = WfxrXtYt_1_0_2; +assign WoxrXtYt_1_packed_2 = WoxrXtYt_1_0_2; +assign WcxrXtYt_1_packed_2 = WcxrXtYt_1_0_2; +assign WixrXtYt_1_packed_3 = WixrXtYt_1_0_3; +assign WfxrXtYt_1_packed_3 = WfxrXtYt_1_0_3; +assign WoxrXtYt_1_packed_3 = WoxrXtYt_1_0_3; +assign WcxrXtYt_1_packed_3 = WcxrXtYt_1_0_3; +assign WixrXtYt_1_packed_4 = WixrXtYt_1_0_4; +assign WfxrXtYt_1_packed_4 = WfxrXtYt_1_0_4; +assign WoxrXtYt_1_packed_4 = WoxrXtYt_1_0_4; +assign WcxrXtYt_1_packed_4 = WcxrXtYt_1_0_4; +assign WixrXtYt_1_packed_5 = WixrXtYt_1_0_5; +assign WfxrXtYt_1_packed_5 = WfxrXtYt_1_0_5; +assign WoxrXtYt_1_packed_5 = WoxrXtYt_1_0_5; +assign WcxrXtYt_1_packed_5 = WcxrXtYt_1_0_5; +assign WixrXtYt_1_packed_6 = WixrXtYt_1_0_6; +assign WfxrXtYt_1_packed_6 = WfxrXtYt_1_0_6; +assign WoxrXtYt_1_packed_6 = WoxrXtYt_1_0_6; +assign WcxrXtYt_1_packed_6 = WcxrXtYt_1_0_6; +assign WixrXtYt_1_packed_7 = WixrXtYt_1_0_7; +assign WfxrXtYt_1_packed_7 = WfxrXtYt_1_0_7; +assign WoxrXtYt_1_packed_7 = WoxrXtYt_1_0_7; +assign WcxrXtYt_1_packed_7 = WcxrXtYt_1_0_7; +assign WixrXtYt_1_packed_8 = WixrXtYt_1_0_8; +assign WfxrXtYt_1_packed_8 = WfxrXtYt_1_0_8; +assign WoxrXtYt_1_packed_8 = WoxrXtYt_1_0_8; +assign WcxrXtYt_1_packed_8 = WcxrXtYt_1_0_8; +assign WixrXtYt_1_packed_9 = WixrXtYt_1_0_9; +assign WfxrXtYt_1_packed_9 = WfxrXtYt_1_0_9; +assign WoxrXtYt_1_packed_9 = WoxrXtYt_1_0_9; +assign WcxrXtYt_1_packed_9 = WcxrXtYt_1_0_9; +assign WixrXtYt_1_packed_10 = WixrXtYt_1_0_10; +assign WfxrXtYt_1_packed_10 = WfxrXtYt_1_0_10; +assign WoxrXtYt_1_packed_10 = WoxrXtYt_1_0_10; +assign WcxrXtYt_1_packed_10 = WcxrXtYt_1_0_10; +assign WixrXtYt_1_packed_11 = WixrXtYt_1_0_11; +assign WfxrXtYt_1_packed_11 = WfxrXtYt_1_0_11; +assign WoxrXtYt_1_packed_11 = WoxrXtYt_1_0_11; +assign WcxrXtYt_1_packed_11 = WcxrXtYt_1_0_11; +assign WixrXtYt_1_packed_12 = WixrXtYt_1_0_12; +assign WfxrXtYt_1_packed_12 = WfxrXtYt_1_0_12; +assign WoxrXtYt_1_packed_12 = WoxrXtYt_1_0_12; +assign WcxrXtYt_1_packed_12 = WcxrXtYt_1_0_12; +assign WixrXtYt_1_packed_13 = WixrXtYt_1_0_13; +assign WfxrXtYt_1_packed_13 = WfxrXtYt_1_0_13; +assign WoxrXtYt_1_packed_13 = WoxrXtYt_1_0_13; +assign WcxrXtYt_1_packed_13 = WcxrXtYt_1_0_13; +assign WixrXtYt_1_packed_14 = WixrXtYt_1_0_14; +assign WfxrXtYt_1_packed_14 = WfxrXtYt_1_0_14; +assign WoxrXtYt_1_packed_14 = WoxrXtYt_1_0_14; +assign WcxrXtYt_1_packed_14 = WcxrXtYt_1_0_14; +assign WixrXtYt_1_packed_15 = WixrXtYt_1_0_15; +assign WfxrXtYt_1_packed_15 = WfxrXtYt_1_0_15; +assign WoxrXtYt_1_packed_15 = WoxrXtYt_1_0_15; +assign WcxrXtYt_1_packed_15 = WcxrXtYt_1_0_15; +assign WixrXtYt_1_packed_16 = WixrXtYt_1_1_0; +assign WfxrXtYt_1_packed_16 = WfxrXtYt_1_1_0; +assign WoxrXtYt_1_packed_16 = WoxrXtYt_1_1_0; +assign WcxrXtYt_1_packed_16 = WcxrXtYt_1_1_0; +assign WixrXtYt_1_packed_17 = WixrXtYt_1_1_1; +assign WfxrXtYt_1_packed_17 = WfxrXtYt_1_1_1; +assign WoxrXtYt_1_packed_17 = WoxrXtYt_1_1_1; +assign WcxrXtYt_1_packed_17 = WcxrXtYt_1_1_1; +assign WixrXtYt_1_packed_18 = WixrXtYt_1_1_2; +assign WfxrXtYt_1_packed_18 = WfxrXtYt_1_1_2; +assign WoxrXtYt_1_packed_18 = WoxrXtYt_1_1_2; +assign WcxrXtYt_1_packed_18 = WcxrXtYt_1_1_2; +assign WixrXtYt_1_packed_19 = WixrXtYt_1_1_3; +assign WfxrXtYt_1_packed_19 = WfxrXtYt_1_1_3; +assign WoxrXtYt_1_packed_19 = WoxrXtYt_1_1_3; +assign WcxrXtYt_1_packed_19 = WcxrXtYt_1_1_3; +assign WixrXtYt_1_packed_20 = WixrXtYt_1_1_4; +assign WfxrXtYt_1_packed_20 = WfxrXtYt_1_1_4; +assign WoxrXtYt_1_packed_20 = WoxrXtYt_1_1_4; +assign WcxrXtYt_1_packed_20 = WcxrXtYt_1_1_4; +assign WixrXtYt_1_packed_21 = WixrXtYt_1_1_5; +assign WfxrXtYt_1_packed_21 = WfxrXtYt_1_1_5; +assign WoxrXtYt_1_packed_21 = WoxrXtYt_1_1_5; +assign WcxrXtYt_1_packed_21 = WcxrXtYt_1_1_5; +assign WixrXtYt_1_packed_22 = WixrXtYt_1_1_6; +assign WfxrXtYt_1_packed_22 = WfxrXtYt_1_1_6; +assign WoxrXtYt_1_packed_22 = WoxrXtYt_1_1_6; +assign WcxrXtYt_1_packed_22 = WcxrXtYt_1_1_6; +assign WixrXtYt_1_packed_23 = WixrXtYt_1_1_7; +assign WfxrXtYt_1_packed_23 = WfxrXtYt_1_1_7; +assign WoxrXtYt_1_packed_23 = WoxrXtYt_1_1_7; +assign WcxrXtYt_1_packed_23 = WcxrXtYt_1_1_7; +assign WixrXtYt_1_packed_24 = WixrXtYt_1_1_8; +assign WfxrXtYt_1_packed_24 = WfxrXtYt_1_1_8; +assign WoxrXtYt_1_packed_24 = WoxrXtYt_1_1_8; +assign WcxrXtYt_1_packed_24 = WcxrXtYt_1_1_8; +assign WixrXtYt_1_packed_25 = WixrXtYt_1_1_9; +assign WfxrXtYt_1_packed_25 = WfxrXtYt_1_1_9; +assign WoxrXtYt_1_packed_25 = WoxrXtYt_1_1_9; +assign WcxrXtYt_1_packed_25 = WcxrXtYt_1_1_9; +assign WixrXtYt_1_packed_26 = WixrXtYt_1_1_10; +assign WfxrXtYt_1_packed_26 = WfxrXtYt_1_1_10; +assign WoxrXtYt_1_packed_26 = WoxrXtYt_1_1_10; +assign WcxrXtYt_1_packed_26 = WcxrXtYt_1_1_10; +assign WixrXtYt_1_packed_27 = WixrXtYt_1_1_11; +assign WfxrXtYt_1_packed_27 = WfxrXtYt_1_1_11; +assign WoxrXtYt_1_packed_27 = WoxrXtYt_1_1_11; +assign WcxrXtYt_1_packed_27 = WcxrXtYt_1_1_11; +assign WixrXtYt_1_packed_28 = WixrXtYt_1_1_12; +assign WfxrXtYt_1_packed_28 = WfxrXtYt_1_1_12; +assign WoxrXtYt_1_packed_28 = WoxrXtYt_1_1_12; +assign WcxrXtYt_1_packed_28 = WcxrXtYt_1_1_12; +assign WixrXtYt_1_packed_29 = WixrXtYt_1_1_13; +assign WfxrXtYt_1_packed_29 = WfxrXtYt_1_1_13; +assign WoxrXtYt_1_packed_29 = WoxrXtYt_1_1_13; +assign WcxrXtYt_1_packed_29 = WcxrXtYt_1_1_13; +assign WixrXtYt_1_packed_30 = WixrXtYt_1_1_14; +assign WfxrXtYt_1_packed_30 = WfxrXtYt_1_1_14; +assign WoxrXtYt_1_packed_30 = WoxrXtYt_1_1_14; +assign WcxrXtYt_1_packed_30 = WcxrXtYt_1_1_14; +assign WixrXtYt_1_packed_31 = WixrXtYt_1_1_15; +assign WfxrXtYt_1_packed_31 = WfxrXtYt_1_1_15; +assign WoxrXtYt_1_packed_31 = WoxrXtYt_1_1_15; +assign WcxrXtYt_1_packed_31 = WcxrXtYt_1_1_15; +assign WixrXtYt_1_packed_32 = WixrXtYt_1_2_0; +assign WfxrXtYt_1_packed_32 = WfxrXtYt_1_2_0; +assign WoxrXtYt_1_packed_32 = WoxrXtYt_1_2_0; +assign WcxrXtYt_1_packed_32 = WcxrXtYt_1_2_0; +assign WixrXtYt_1_packed_33 = WixrXtYt_1_2_1; +assign WfxrXtYt_1_packed_33 = WfxrXtYt_1_2_1; +assign WoxrXtYt_1_packed_33 = WoxrXtYt_1_2_1; +assign WcxrXtYt_1_packed_33 = WcxrXtYt_1_2_1; +assign WixrXtYt_1_packed_34 = WixrXtYt_1_2_2; +assign WfxrXtYt_1_packed_34 = WfxrXtYt_1_2_2; +assign WoxrXtYt_1_packed_34 = WoxrXtYt_1_2_2; +assign WcxrXtYt_1_packed_34 = WcxrXtYt_1_2_2; +assign WixrXtYt_1_packed_35 = WixrXtYt_1_2_3; +assign WfxrXtYt_1_packed_35 = WfxrXtYt_1_2_3; +assign WoxrXtYt_1_packed_35 = WoxrXtYt_1_2_3; +assign WcxrXtYt_1_packed_35 = WcxrXtYt_1_2_3; +assign WixrXtYt_1_packed_36 = WixrXtYt_1_2_4; +assign WfxrXtYt_1_packed_36 = WfxrXtYt_1_2_4; +assign WoxrXtYt_1_packed_36 = WoxrXtYt_1_2_4; +assign WcxrXtYt_1_packed_36 = WcxrXtYt_1_2_4; +assign WixrXtYt_1_packed_37 = WixrXtYt_1_2_5; +assign WfxrXtYt_1_packed_37 = WfxrXtYt_1_2_5; +assign WoxrXtYt_1_packed_37 = WoxrXtYt_1_2_5; +assign WcxrXtYt_1_packed_37 = WcxrXtYt_1_2_5; +assign WixrXtYt_1_packed_38 = WixrXtYt_1_2_6; +assign WfxrXtYt_1_packed_38 = WfxrXtYt_1_2_6; +assign WoxrXtYt_1_packed_38 = WoxrXtYt_1_2_6; +assign WcxrXtYt_1_packed_38 = WcxrXtYt_1_2_6; +assign WixrXtYt_1_packed_39 = WixrXtYt_1_2_7; +assign WfxrXtYt_1_packed_39 = WfxrXtYt_1_2_7; +assign WoxrXtYt_1_packed_39 = WoxrXtYt_1_2_7; +assign WcxrXtYt_1_packed_39 = WcxrXtYt_1_2_7; +assign WixrXtYt_1_packed_40 = WixrXtYt_1_2_8; +assign WfxrXtYt_1_packed_40 = WfxrXtYt_1_2_8; +assign WoxrXtYt_1_packed_40 = WoxrXtYt_1_2_8; +assign WcxrXtYt_1_packed_40 = WcxrXtYt_1_2_8; +assign WixrXtYt_1_packed_41 = WixrXtYt_1_2_9; +assign WfxrXtYt_1_packed_41 = WfxrXtYt_1_2_9; +assign WoxrXtYt_1_packed_41 = WoxrXtYt_1_2_9; +assign WcxrXtYt_1_packed_41 = WcxrXtYt_1_2_9; +assign WixrXtYt_1_packed_42 = WixrXtYt_1_2_10; +assign WfxrXtYt_1_packed_42 = WfxrXtYt_1_2_10; +assign WoxrXtYt_1_packed_42 = WoxrXtYt_1_2_10; +assign WcxrXtYt_1_packed_42 = WcxrXtYt_1_2_10; +assign WixrXtYt_1_packed_43 = WixrXtYt_1_2_11; +assign WfxrXtYt_1_packed_43 = WfxrXtYt_1_2_11; +assign WoxrXtYt_1_packed_43 = WoxrXtYt_1_2_11; +assign WcxrXtYt_1_packed_43 = WcxrXtYt_1_2_11; +assign WixrXtYt_1_packed_44 = WixrXtYt_1_2_12; +assign WfxrXtYt_1_packed_44 = WfxrXtYt_1_2_12; +assign WoxrXtYt_1_packed_44 = WoxrXtYt_1_2_12; +assign WcxrXtYt_1_packed_44 = WcxrXtYt_1_2_12; +assign WixrXtYt_1_packed_45 = WixrXtYt_1_2_13; +assign WfxrXtYt_1_packed_45 = WfxrXtYt_1_2_13; +assign WoxrXtYt_1_packed_45 = WoxrXtYt_1_2_13; +assign WcxrXtYt_1_packed_45 = WcxrXtYt_1_2_13; +assign WixrXtYt_1_packed_46 = WixrXtYt_1_2_14; +assign WfxrXtYt_1_packed_46 = WfxrXtYt_1_2_14; +assign WoxrXtYt_1_packed_46 = WoxrXtYt_1_2_14; +assign WcxrXtYt_1_packed_46 = WcxrXtYt_1_2_14; +assign WixrXtYt_1_packed_47 = WixrXtYt_1_2_15; +assign WfxrXtYt_1_packed_47 = WfxrXtYt_1_2_15; +assign WoxrXtYt_1_packed_47 = WoxrXtYt_1_2_15; +assign WcxrXtYt_1_packed_47 = WcxrXtYt_1_2_15; + +shift_register_group_18_48_3 shift_register_group_18_48_3_inst_Wi ( + .clk(clk), + .enable(enable), + .in_0(WixrXtYt_1_packed_0), + .out_0(WixrXtYt_1_hold_0), + .in_1(WixrXtYt_1_packed_1), + .out_1(WixrXtYt_1_hold_1), + .in_2(WixrXtYt_1_packed_2), + .out_2(WixrXtYt_1_hold_2), + .in_3(WixrXtYt_1_packed_3), + .out_3(WixrXtYt_1_hold_3), + .in_4(WixrXtYt_1_packed_4), + .out_4(WixrXtYt_1_hold_4), + .in_5(WixrXtYt_1_packed_5), + .out_5(WixrXtYt_1_hold_5), + .in_6(WixrXtYt_1_packed_6), + .out_6(WixrXtYt_1_hold_6), + .in_7(WixrXtYt_1_packed_7), + .out_7(WixrXtYt_1_hold_7), + .in_8(WixrXtYt_1_packed_8), + .out_8(WixrXtYt_1_hold_8), + .in_9(WixrXtYt_1_packed_9), + .out_9(WixrXtYt_1_hold_9), + .in_10(WixrXtYt_1_packed_10), + .out_10(WixrXtYt_1_hold_10), + .in_11(WixrXtYt_1_packed_11), + .out_11(WixrXtYt_1_hold_11), + .in_12(WixrXtYt_1_packed_12), + .out_12(WixrXtYt_1_hold_12), + .in_13(WixrXtYt_1_packed_13), + .out_13(WixrXtYt_1_hold_13), + .in_14(WixrXtYt_1_packed_14), + .out_14(WixrXtYt_1_hold_14), + .in_15(WixrXtYt_1_packed_15), + .out_15(WixrXtYt_1_hold_15), + .in_16(WixrXtYt_1_packed_16), + .out_16(WixrXtYt_1_hold_16), + .in_17(WixrXtYt_1_packed_17), + .out_17(WixrXtYt_1_hold_17), + .in_18(WixrXtYt_1_packed_18), + .out_18(WixrXtYt_1_hold_18), + .in_19(WixrXtYt_1_packed_19), + .out_19(WixrXtYt_1_hold_19), + .in_20(WixrXtYt_1_packed_20), + .out_20(WixrXtYt_1_hold_20), + .in_21(WixrXtYt_1_packed_21), + .out_21(WixrXtYt_1_hold_21), + .in_22(WixrXtYt_1_packed_22), + .out_22(WixrXtYt_1_hold_22), + .in_23(WixrXtYt_1_packed_23), + .out_23(WixrXtYt_1_hold_23), + .in_24(WixrXtYt_1_packed_24), + .out_24(WixrXtYt_1_hold_24), + .in_25(WixrXtYt_1_packed_25), + .out_25(WixrXtYt_1_hold_25), + .in_26(WixrXtYt_1_packed_26), + .out_26(WixrXtYt_1_hold_26), + .in_27(WixrXtYt_1_packed_27), + .out_27(WixrXtYt_1_hold_27), + .in_28(WixrXtYt_1_packed_28), + .out_28(WixrXtYt_1_hold_28), + .in_29(WixrXtYt_1_packed_29), + .out_29(WixrXtYt_1_hold_29), + .in_30(WixrXtYt_1_packed_30), + .out_30(WixrXtYt_1_hold_30), + .in_31(WixrXtYt_1_packed_31), + .out_31(WixrXtYt_1_hold_31), + .in_32(WixrXtYt_1_packed_32), + .out_32(WixrXtYt_1_hold_32), + .in_33(WixrXtYt_1_packed_33), + .out_33(WixrXtYt_1_hold_33), + .in_34(WixrXtYt_1_packed_34), + .out_34(WixrXtYt_1_hold_34), + .in_35(WixrXtYt_1_packed_35), + .out_35(WixrXtYt_1_hold_35), + .in_36(WixrXtYt_1_packed_36), + .out_36(WixrXtYt_1_hold_36), + .in_37(WixrXtYt_1_packed_37), + .out_37(WixrXtYt_1_hold_37), + .in_38(WixrXtYt_1_packed_38), + .out_38(WixrXtYt_1_hold_38), + .in_39(WixrXtYt_1_packed_39), + .out_39(WixrXtYt_1_hold_39), + .in_40(WixrXtYt_1_packed_40), + .out_40(WixrXtYt_1_hold_40), + .in_41(WixrXtYt_1_packed_41), + .out_41(WixrXtYt_1_hold_41), + .in_42(WixrXtYt_1_packed_42), + .out_42(WixrXtYt_1_hold_42), + .in_43(WixrXtYt_1_packed_43), + .out_43(WixrXtYt_1_hold_43), + .in_44(WixrXtYt_1_packed_44), + .out_44(WixrXtYt_1_hold_44), + .in_45(WixrXtYt_1_packed_45), + .out_45(WixrXtYt_1_hold_45), + .in_46(WixrXtYt_1_packed_46), + .out_46(WixrXtYt_1_hold_46), + .in_47(WixrXtYt_1_packed_47), + .out_47(WixrXtYt_1_hold_47), + .reset(reset) +); + +shift_register_group_18_48_3 shift_register_group_18_48_3_inst_Wf ( + .clk(clk), + .enable(enable), + .in_0(WfxrXtYt_1_packed_0), + .out_0(WfxrXtYt_1_hold_0), + .in_1(WfxrXtYt_1_packed_1), + .out_1(WfxrXtYt_1_hold_1), + .in_2(WfxrXtYt_1_packed_2), + .out_2(WfxrXtYt_1_hold_2), + .in_3(WfxrXtYt_1_packed_3), + .out_3(WfxrXtYt_1_hold_3), + .in_4(WfxrXtYt_1_packed_4), + .out_4(WfxrXtYt_1_hold_4), + .in_5(WfxrXtYt_1_packed_5), + .out_5(WfxrXtYt_1_hold_5), + .in_6(WfxrXtYt_1_packed_6), + .out_6(WfxrXtYt_1_hold_6), + .in_7(WfxrXtYt_1_packed_7), + .out_7(WfxrXtYt_1_hold_7), + .in_8(WfxrXtYt_1_packed_8), + .out_8(WfxrXtYt_1_hold_8), + .in_9(WfxrXtYt_1_packed_9), + .out_9(WfxrXtYt_1_hold_9), + .in_10(WfxrXtYt_1_packed_10), + .out_10(WfxrXtYt_1_hold_10), + .in_11(WfxrXtYt_1_packed_11), + .out_11(WfxrXtYt_1_hold_11), + .in_12(WfxrXtYt_1_packed_12), + .out_12(WfxrXtYt_1_hold_12), + .in_13(WfxrXtYt_1_packed_13), + .out_13(WfxrXtYt_1_hold_13), + .in_14(WfxrXtYt_1_packed_14), + .out_14(WfxrXtYt_1_hold_14), + .in_15(WfxrXtYt_1_packed_15), + .out_15(WfxrXtYt_1_hold_15), + .in_16(WfxrXtYt_1_packed_16), + .out_16(WfxrXtYt_1_hold_16), + .in_17(WfxrXtYt_1_packed_17), + .out_17(WfxrXtYt_1_hold_17), + .in_18(WfxrXtYt_1_packed_18), + .out_18(WfxrXtYt_1_hold_18), + .in_19(WfxrXtYt_1_packed_19), + .out_19(WfxrXtYt_1_hold_19), + .in_20(WfxrXtYt_1_packed_20), + .out_20(WfxrXtYt_1_hold_20), + .in_21(WfxrXtYt_1_packed_21), + .out_21(WfxrXtYt_1_hold_21), + .in_22(WfxrXtYt_1_packed_22), + .out_22(WfxrXtYt_1_hold_22), + .in_23(WfxrXtYt_1_packed_23), + .out_23(WfxrXtYt_1_hold_23), + .in_24(WfxrXtYt_1_packed_24), + .out_24(WfxrXtYt_1_hold_24), + .in_25(WfxrXtYt_1_packed_25), + .out_25(WfxrXtYt_1_hold_25), + .in_26(WfxrXtYt_1_packed_26), + .out_26(WfxrXtYt_1_hold_26), + .in_27(WfxrXtYt_1_packed_27), + .out_27(WfxrXtYt_1_hold_27), + .in_28(WfxrXtYt_1_packed_28), + .out_28(WfxrXtYt_1_hold_28), + .in_29(WfxrXtYt_1_packed_29), + .out_29(WfxrXtYt_1_hold_29), + .in_30(WfxrXtYt_1_packed_30), + .out_30(WfxrXtYt_1_hold_30), + .in_31(WfxrXtYt_1_packed_31), + .out_31(WfxrXtYt_1_hold_31), + .in_32(WfxrXtYt_1_packed_32), + .out_32(WfxrXtYt_1_hold_32), + .in_33(WfxrXtYt_1_packed_33), + .out_33(WfxrXtYt_1_hold_33), + .in_34(WfxrXtYt_1_packed_34), + .out_34(WfxrXtYt_1_hold_34), + .in_35(WfxrXtYt_1_packed_35), + .out_35(WfxrXtYt_1_hold_35), + .in_36(WfxrXtYt_1_packed_36), + .out_36(WfxrXtYt_1_hold_36), + .in_37(WfxrXtYt_1_packed_37), + .out_37(WfxrXtYt_1_hold_37), + .in_38(WfxrXtYt_1_packed_38), + .out_38(WfxrXtYt_1_hold_38), + .in_39(WfxrXtYt_1_packed_39), + .out_39(WfxrXtYt_1_hold_39), + .in_40(WfxrXtYt_1_packed_40), + .out_40(WfxrXtYt_1_hold_40), + .in_41(WfxrXtYt_1_packed_41), + .out_41(WfxrXtYt_1_hold_41), + .in_42(WfxrXtYt_1_packed_42), + .out_42(WfxrXtYt_1_hold_42), + .in_43(WfxrXtYt_1_packed_43), + .out_43(WfxrXtYt_1_hold_43), + .in_44(WfxrXtYt_1_packed_44), + .out_44(WfxrXtYt_1_hold_44), + .in_45(WfxrXtYt_1_packed_45), + .out_45(WfxrXtYt_1_hold_45), + .in_46(WfxrXtYt_1_packed_46), + .out_46(WfxrXtYt_1_hold_46), + .in_47(WfxrXtYt_1_packed_47), + .out_47(WfxrXtYt_1_hold_47), + .reset(reset) +); + +shift_register_group_18_48_3 shift_register_group_18_48_3_inst_Wo ( + .clk(clk), + .enable(enable), + .in_0(WoxrXtYt_1_packed_0), + .out_0(WoxrXtYt_1_hold_0), + .in_1(WoxrXtYt_1_packed_1), + .out_1(WoxrXtYt_1_hold_1), + .in_2(WoxrXtYt_1_packed_2), + .out_2(WoxrXtYt_1_hold_2), + .in_3(WoxrXtYt_1_packed_3), + .out_3(WoxrXtYt_1_hold_3), + .in_4(WoxrXtYt_1_packed_4), + .out_4(WoxrXtYt_1_hold_4), + .in_5(WoxrXtYt_1_packed_5), + .out_5(WoxrXtYt_1_hold_5), + .in_6(WoxrXtYt_1_packed_6), + .out_6(WoxrXtYt_1_hold_6), + .in_7(WoxrXtYt_1_packed_7), + .out_7(WoxrXtYt_1_hold_7), + .in_8(WoxrXtYt_1_packed_8), + .out_8(WoxrXtYt_1_hold_8), + .in_9(WoxrXtYt_1_packed_9), + .out_9(WoxrXtYt_1_hold_9), + .in_10(WoxrXtYt_1_packed_10), + .out_10(WoxrXtYt_1_hold_10), + .in_11(WoxrXtYt_1_packed_11), + .out_11(WoxrXtYt_1_hold_11), + .in_12(WoxrXtYt_1_packed_12), + .out_12(WoxrXtYt_1_hold_12), + .in_13(WoxrXtYt_1_packed_13), + .out_13(WoxrXtYt_1_hold_13), + .in_14(WoxrXtYt_1_packed_14), + .out_14(WoxrXtYt_1_hold_14), + .in_15(WoxrXtYt_1_packed_15), + .out_15(WoxrXtYt_1_hold_15), + .in_16(WoxrXtYt_1_packed_16), + .out_16(WoxrXtYt_1_hold_16), + .in_17(WoxrXtYt_1_packed_17), + .out_17(WoxrXtYt_1_hold_17), + .in_18(WoxrXtYt_1_packed_18), + .out_18(WoxrXtYt_1_hold_18), + .in_19(WoxrXtYt_1_packed_19), + .out_19(WoxrXtYt_1_hold_19), + .in_20(WoxrXtYt_1_packed_20), + .out_20(WoxrXtYt_1_hold_20), + .in_21(WoxrXtYt_1_packed_21), + .out_21(WoxrXtYt_1_hold_21), + .in_22(WoxrXtYt_1_packed_22), + .out_22(WoxrXtYt_1_hold_22), + .in_23(WoxrXtYt_1_packed_23), + .out_23(WoxrXtYt_1_hold_23), + .in_24(WoxrXtYt_1_packed_24), + .out_24(WoxrXtYt_1_hold_24), + .in_25(WoxrXtYt_1_packed_25), + .out_25(WoxrXtYt_1_hold_25), + .in_26(WoxrXtYt_1_packed_26), + .out_26(WoxrXtYt_1_hold_26), + .in_27(WoxrXtYt_1_packed_27), + .out_27(WoxrXtYt_1_hold_27), + .in_28(WoxrXtYt_1_packed_28), + .out_28(WoxrXtYt_1_hold_28), + .in_29(WoxrXtYt_1_packed_29), + .out_29(WoxrXtYt_1_hold_29), + .in_30(WoxrXtYt_1_packed_30), + .out_30(WoxrXtYt_1_hold_30), + .in_31(WoxrXtYt_1_packed_31), + .out_31(WoxrXtYt_1_hold_31), + .in_32(WoxrXtYt_1_packed_32), + .out_32(WoxrXtYt_1_hold_32), + .in_33(WoxrXtYt_1_packed_33), + .out_33(WoxrXtYt_1_hold_33), + .in_34(WoxrXtYt_1_packed_34), + .out_34(WoxrXtYt_1_hold_34), + .in_35(WoxrXtYt_1_packed_35), + .out_35(WoxrXtYt_1_hold_35), + .in_36(WoxrXtYt_1_packed_36), + .out_36(WoxrXtYt_1_hold_36), + .in_37(WoxrXtYt_1_packed_37), + .out_37(WoxrXtYt_1_hold_37), + .in_38(WoxrXtYt_1_packed_38), + .out_38(WoxrXtYt_1_hold_38), + .in_39(WoxrXtYt_1_packed_39), + .out_39(WoxrXtYt_1_hold_39), + .in_40(WoxrXtYt_1_packed_40), + .out_40(WoxrXtYt_1_hold_40), + .in_41(WoxrXtYt_1_packed_41), + .out_41(WoxrXtYt_1_hold_41), + .in_42(WoxrXtYt_1_packed_42), + .out_42(WoxrXtYt_1_hold_42), + .in_43(WoxrXtYt_1_packed_43), + .out_43(WoxrXtYt_1_hold_43), + .in_44(WoxrXtYt_1_packed_44), + .out_44(WoxrXtYt_1_hold_44), + .in_45(WoxrXtYt_1_packed_45), + .out_45(WoxrXtYt_1_hold_45), + .in_46(WoxrXtYt_1_packed_46), + .out_46(WoxrXtYt_1_hold_46), + .in_47(WoxrXtYt_1_packed_47), + .out_47(WoxrXtYt_1_hold_47), + .reset(reset) +); + +shift_register_group_18_48_3 shift_register_group_18_48_3_inst_Wc ( + .clk(clk), + .enable(enable), + .in_0(WcxrXtYt_1_packed_0), + .out_0(WcxrXtYt_1_hold_0), + .in_1(WcxrXtYt_1_packed_1), + .out_1(WcxrXtYt_1_hold_1), + .in_2(WcxrXtYt_1_packed_2), + .out_2(WcxrXtYt_1_hold_2), + .in_3(WcxrXtYt_1_packed_3), + .out_3(WcxrXtYt_1_hold_3), + .in_4(WcxrXtYt_1_packed_4), + .out_4(WcxrXtYt_1_hold_4), + .in_5(WcxrXtYt_1_packed_5), + .out_5(WcxrXtYt_1_hold_5), + .in_6(WcxrXtYt_1_packed_6), + .out_6(WcxrXtYt_1_hold_6), + .in_7(WcxrXtYt_1_packed_7), + .out_7(WcxrXtYt_1_hold_7), + .in_8(WcxrXtYt_1_packed_8), + .out_8(WcxrXtYt_1_hold_8), + .in_9(WcxrXtYt_1_packed_9), + .out_9(WcxrXtYt_1_hold_9), + .in_10(WcxrXtYt_1_packed_10), + .out_10(WcxrXtYt_1_hold_10), + .in_11(WcxrXtYt_1_packed_11), + .out_11(WcxrXtYt_1_hold_11), + .in_12(WcxrXtYt_1_packed_12), + .out_12(WcxrXtYt_1_hold_12), + .in_13(WcxrXtYt_1_packed_13), + .out_13(WcxrXtYt_1_hold_13), + .in_14(WcxrXtYt_1_packed_14), + .out_14(WcxrXtYt_1_hold_14), + .in_15(WcxrXtYt_1_packed_15), + .out_15(WcxrXtYt_1_hold_15), + .in_16(WcxrXtYt_1_packed_16), + .out_16(WcxrXtYt_1_hold_16), + .in_17(WcxrXtYt_1_packed_17), + .out_17(WcxrXtYt_1_hold_17), + .in_18(WcxrXtYt_1_packed_18), + .out_18(WcxrXtYt_1_hold_18), + .in_19(WcxrXtYt_1_packed_19), + .out_19(WcxrXtYt_1_hold_19), + .in_20(WcxrXtYt_1_packed_20), + .out_20(WcxrXtYt_1_hold_20), + .in_21(WcxrXtYt_1_packed_21), + .out_21(WcxrXtYt_1_hold_21), + .in_22(WcxrXtYt_1_packed_22), + .out_22(WcxrXtYt_1_hold_22), + .in_23(WcxrXtYt_1_packed_23), + .out_23(WcxrXtYt_1_hold_23), + .in_24(WcxrXtYt_1_packed_24), + .out_24(WcxrXtYt_1_hold_24), + .in_25(WcxrXtYt_1_packed_25), + .out_25(WcxrXtYt_1_hold_25), + .in_26(WcxrXtYt_1_packed_26), + .out_26(WcxrXtYt_1_hold_26), + .in_27(WcxrXtYt_1_packed_27), + .out_27(WcxrXtYt_1_hold_27), + .in_28(WcxrXtYt_1_packed_28), + .out_28(WcxrXtYt_1_hold_28), + .in_29(WcxrXtYt_1_packed_29), + .out_29(WcxrXtYt_1_hold_29), + .in_30(WcxrXtYt_1_packed_30), + .out_30(WcxrXtYt_1_hold_30), + .in_31(WcxrXtYt_1_packed_31), + .out_31(WcxrXtYt_1_hold_31), + .in_32(WcxrXtYt_1_packed_32), + .out_32(WcxrXtYt_1_hold_32), + .in_33(WcxrXtYt_1_packed_33), + .out_33(WcxrXtYt_1_hold_33), + .in_34(WcxrXtYt_1_packed_34), + .out_34(WcxrXtYt_1_hold_34), + .in_35(WcxrXtYt_1_packed_35), + .out_35(WcxrXtYt_1_hold_35), + .in_36(WcxrXtYt_1_packed_36), + .out_36(WcxrXtYt_1_hold_36), + .in_37(WcxrXtYt_1_packed_37), + .out_37(WcxrXtYt_1_hold_37), + .in_38(WcxrXtYt_1_packed_38), + .out_38(WcxrXtYt_1_hold_38), + .in_39(WcxrXtYt_1_packed_39), + .out_39(WcxrXtYt_1_hold_39), + .in_40(WcxrXtYt_1_packed_40), + .out_40(WcxrXtYt_1_hold_40), + .in_41(WcxrXtYt_1_packed_41), + .out_41(WcxrXtYt_1_hold_41), + .in_42(WcxrXtYt_1_packed_42), + .out_42(WcxrXtYt_1_hold_42), + .in_43(WcxrXtYt_1_packed_43), + .out_43(WcxrXtYt_1_hold_43), + .in_44(WcxrXtYt_1_packed_44), + .out_44(WcxrXtYt_1_hold_44), + .in_45(WcxrXtYt_1_packed_45), + .out_45(WcxrXtYt_1_hold_45), + .in_46(WcxrXtYt_1_packed_46), + .out_46(WcxrXtYt_1_hold_46), + .in_47(WcxrXtYt_1_packed_47), + .out_47(WcxrXtYt_1_hold_47), + .reset(reset) +); + +shift_register_unit_1_3 shift_register_unit_1_3_inst_s2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(stage1_valid), + .out(stage1_valid_hold) +); + +C_LSTM_stage_2_18_10_48_1 C_LSTM_stage_2_18_10_48_1_inst_poousgrtem ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(stage1_valid_hold), + .Ct_1_0(Ctt_1_0), + .WixrXtYt_1_0(WixrXtYt_1_hold_0), + .Wic_0(Wic_0), + .bi_0(bi_0), + .WfxrXtYt_1_0(WfxrXtYt_1_hold_0), + .Wfc_0(Wfc_0), + .bf_0(bf_0), + .WoxrXtYt_1_0(WoxrXtYt_1_hold_0), + .Woc_0(Woc_0), + .bo_0(bo_0), + .WcxrXtYt_1_0(WcxrXtYt_1_hold_0), + .bc_0(bc_0), + .out_mt_0(stage2_mt_0), + .out_ct_0(stage2_Ct_0), + .Ct_1_1(Ctt_1_1), + .WixrXtYt_1_1(WixrXtYt_1_hold_1), + .Wic_1(Wic_1), + .bi_1(bi_1), + .WfxrXtYt_1_1(WfxrXtYt_1_hold_1), + .Wfc_1(Wfc_1), + .bf_1(bf_1), + .WoxrXtYt_1_1(WoxrXtYt_1_hold_1), + .Woc_1(Woc_1), + .bo_1(bo_1), + .WcxrXtYt_1_1(WcxrXtYt_1_hold_1), + .bc_1(bc_1), + .out_mt_1(stage2_mt_1), + .out_ct_1(stage2_Ct_1), + .Ct_1_2(Ctt_1_2), + .WixrXtYt_1_2(WixrXtYt_1_hold_2), + .Wic_2(Wic_2), + .bi_2(bi_2), + .WfxrXtYt_1_2(WfxrXtYt_1_hold_2), + .Wfc_2(Wfc_2), + .bf_2(bf_2), + .WoxrXtYt_1_2(WoxrXtYt_1_hold_2), + .Woc_2(Woc_2), + .bo_2(bo_2), + .WcxrXtYt_1_2(WcxrXtYt_1_hold_2), + .bc_2(bc_2), + .out_mt_2(stage2_mt_2), + .out_ct_2(stage2_Ct_2), + .Ct_1_3(Ctt_1_3), + .WixrXtYt_1_3(WixrXtYt_1_hold_3), + .Wic_3(Wic_3), + .bi_3(bi_3), + .WfxrXtYt_1_3(WfxrXtYt_1_hold_3), + .Wfc_3(Wfc_3), + .bf_3(bf_3), + .WoxrXtYt_1_3(WoxrXtYt_1_hold_3), + .Woc_3(Woc_3), + .bo_3(bo_3), + .WcxrXtYt_1_3(WcxrXtYt_1_hold_3), + .bc_3(bc_3), + .out_mt_3(stage2_mt_3), + .out_ct_3(stage2_Ct_3), + .Ct_1_4(Ctt_1_4), + .WixrXtYt_1_4(WixrXtYt_1_hold_4), + .Wic_4(Wic_4), + .bi_4(bi_4), + .WfxrXtYt_1_4(WfxrXtYt_1_hold_4), + .Wfc_4(Wfc_4), + .bf_4(bf_4), + .WoxrXtYt_1_4(WoxrXtYt_1_hold_4), + .Woc_4(Woc_4), + .bo_4(bo_4), + .WcxrXtYt_1_4(WcxrXtYt_1_hold_4), + .bc_4(bc_4), + .out_mt_4(stage2_mt_4), + .out_ct_4(stage2_Ct_4), + .Ct_1_5(Ctt_1_5), + .WixrXtYt_1_5(WixrXtYt_1_hold_5), + .Wic_5(Wic_5), + .bi_5(bi_5), + .WfxrXtYt_1_5(WfxrXtYt_1_hold_5), + .Wfc_5(Wfc_5), + .bf_5(bf_5), + .WoxrXtYt_1_5(WoxrXtYt_1_hold_5), + .Woc_5(Woc_5), + .bo_5(bo_5), + .WcxrXtYt_1_5(WcxrXtYt_1_hold_5), + .bc_5(bc_5), + .out_mt_5(stage2_mt_5), + .out_ct_5(stage2_Ct_5), + .Ct_1_6(Ctt_1_6), + .WixrXtYt_1_6(WixrXtYt_1_hold_6), + .Wic_6(Wic_6), + .bi_6(bi_6), + .WfxrXtYt_1_6(WfxrXtYt_1_hold_6), + .Wfc_6(Wfc_6), + .bf_6(bf_6), + .WoxrXtYt_1_6(WoxrXtYt_1_hold_6), + .Woc_6(Woc_6), + .bo_6(bo_6), + .WcxrXtYt_1_6(WcxrXtYt_1_hold_6), + .bc_6(bc_6), + .out_mt_6(stage2_mt_6), + .out_ct_6(stage2_Ct_6), + .Ct_1_7(Ctt_1_7), + .WixrXtYt_1_7(WixrXtYt_1_hold_7), + .Wic_7(Wic_7), + .bi_7(bi_7), + .WfxrXtYt_1_7(WfxrXtYt_1_hold_7), + .Wfc_7(Wfc_7), + .bf_7(bf_7), + .WoxrXtYt_1_7(WoxrXtYt_1_hold_7), + .Woc_7(Woc_7), + .bo_7(bo_7), + .WcxrXtYt_1_7(WcxrXtYt_1_hold_7), + .bc_7(bc_7), + .out_mt_7(stage2_mt_7), + .out_ct_7(stage2_Ct_7), + .Ct_1_8(Ctt_1_8), + .WixrXtYt_1_8(WixrXtYt_1_hold_8), + .Wic_8(Wic_8), + .bi_8(bi_8), + .WfxrXtYt_1_8(WfxrXtYt_1_hold_8), + .Wfc_8(Wfc_8), + .bf_8(bf_8), + .WoxrXtYt_1_8(WoxrXtYt_1_hold_8), + .Woc_8(Woc_8), + .bo_8(bo_8), + .WcxrXtYt_1_8(WcxrXtYt_1_hold_8), + .bc_8(bc_8), + .out_mt_8(stage2_mt_8), + .out_ct_8(stage2_Ct_8), + .Ct_1_9(Ctt_1_9), + .WixrXtYt_1_9(WixrXtYt_1_hold_9), + .Wic_9(Wic_9), + .bi_9(bi_9), + .WfxrXtYt_1_9(WfxrXtYt_1_hold_9), + .Wfc_9(Wfc_9), + .bf_9(bf_9), + .WoxrXtYt_1_9(WoxrXtYt_1_hold_9), + .Woc_9(Woc_9), + .bo_9(bo_9), + .WcxrXtYt_1_9(WcxrXtYt_1_hold_9), + .bc_9(bc_9), + .out_mt_9(stage2_mt_9), + .out_ct_9(stage2_Ct_9), + .Ct_1_10(Ctt_1_10), + .WixrXtYt_1_10(WixrXtYt_1_hold_10), + .Wic_10(Wic_10), + .bi_10(bi_10), + .WfxrXtYt_1_10(WfxrXtYt_1_hold_10), + .Wfc_10(Wfc_10), + .bf_10(bf_10), + .WoxrXtYt_1_10(WoxrXtYt_1_hold_10), + .Woc_10(Woc_10), + .bo_10(bo_10), + .WcxrXtYt_1_10(WcxrXtYt_1_hold_10), + .bc_10(bc_10), + .out_mt_10(stage2_mt_10), + .out_ct_10(stage2_Ct_10), + .Ct_1_11(Ctt_1_11), + .WixrXtYt_1_11(WixrXtYt_1_hold_11), + .Wic_11(Wic_11), + .bi_11(bi_11), + .WfxrXtYt_1_11(WfxrXtYt_1_hold_11), + .Wfc_11(Wfc_11), + .bf_11(bf_11), + .WoxrXtYt_1_11(WoxrXtYt_1_hold_11), + .Woc_11(Woc_11), + .bo_11(bo_11), + .WcxrXtYt_1_11(WcxrXtYt_1_hold_11), + .bc_11(bc_11), + .out_mt_11(stage2_mt_11), + .out_ct_11(stage2_Ct_11), + .Ct_1_12(Ctt_1_12), + .WixrXtYt_1_12(WixrXtYt_1_hold_12), + .Wic_12(Wic_12), + .bi_12(bi_12), + .WfxrXtYt_1_12(WfxrXtYt_1_hold_12), + .Wfc_12(Wfc_12), + .bf_12(bf_12), + .WoxrXtYt_1_12(WoxrXtYt_1_hold_12), + .Woc_12(Woc_12), + .bo_12(bo_12), + .WcxrXtYt_1_12(WcxrXtYt_1_hold_12), + .bc_12(bc_12), + .out_mt_12(stage2_mt_12), + .out_ct_12(stage2_Ct_12), + .Ct_1_13(Ctt_1_13), + .WixrXtYt_1_13(WixrXtYt_1_hold_13), + .Wic_13(Wic_13), + .bi_13(bi_13), + .WfxrXtYt_1_13(WfxrXtYt_1_hold_13), + .Wfc_13(Wfc_13), + .bf_13(bf_13), + .WoxrXtYt_1_13(WoxrXtYt_1_hold_13), + .Woc_13(Woc_13), + .bo_13(bo_13), + .WcxrXtYt_1_13(WcxrXtYt_1_hold_13), + .bc_13(bc_13), + .out_mt_13(stage2_mt_13), + .out_ct_13(stage2_Ct_13), + .Ct_1_14(Ctt_1_14), + .WixrXtYt_1_14(WixrXtYt_1_hold_14), + .Wic_14(Wic_14), + .bi_14(bi_14), + .WfxrXtYt_1_14(WfxrXtYt_1_hold_14), + .Wfc_14(Wfc_14), + .bf_14(bf_14), + .WoxrXtYt_1_14(WoxrXtYt_1_hold_14), + .Woc_14(Woc_14), + .bo_14(bo_14), + .WcxrXtYt_1_14(WcxrXtYt_1_hold_14), + .bc_14(bc_14), + .out_mt_14(stage2_mt_14), + .out_ct_14(stage2_Ct_14), + .Ct_1_15(Ctt_1_15), + .WixrXtYt_1_15(WixrXtYt_1_hold_15), + .Wic_15(Wic_15), + .bi_15(bi_15), + .WfxrXtYt_1_15(WfxrXtYt_1_hold_15), + .Wfc_15(Wfc_15), + .bf_15(bf_15), + .WoxrXtYt_1_15(WoxrXtYt_1_hold_15), + .Woc_15(Woc_15), + .bo_15(bo_15), + .WcxrXtYt_1_15(WcxrXtYt_1_hold_15), + .bc_15(bc_15), + .out_mt_15(stage2_mt_15), + .out_ct_15(stage2_Ct_15), + .Ct_1_16(Ctt_1_16), + .WixrXtYt_1_16(WixrXtYt_1_hold_16), + .Wic_16(Wic_16), + .bi_16(bi_16), + .WfxrXtYt_1_16(WfxrXtYt_1_hold_16), + .Wfc_16(Wfc_16), + .bf_16(bf_16), + .WoxrXtYt_1_16(WoxrXtYt_1_hold_16), + .Woc_16(Woc_16), + .bo_16(bo_16), + .WcxrXtYt_1_16(WcxrXtYt_1_hold_16), + .bc_16(bc_16), + .out_mt_16(stage2_mt_16), + .out_ct_16(stage2_Ct_16), + .Ct_1_17(Ctt_1_17), + .WixrXtYt_1_17(WixrXtYt_1_hold_17), + .Wic_17(Wic_17), + .bi_17(bi_17), + .WfxrXtYt_1_17(WfxrXtYt_1_hold_17), + .Wfc_17(Wfc_17), + .bf_17(bf_17), + .WoxrXtYt_1_17(WoxrXtYt_1_hold_17), + .Woc_17(Woc_17), + .bo_17(bo_17), + .WcxrXtYt_1_17(WcxrXtYt_1_hold_17), + .bc_17(bc_17), + .out_mt_17(stage2_mt_17), + .out_ct_17(stage2_Ct_17), + .Ct_1_18(Ctt_1_18), + .WixrXtYt_1_18(WixrXtYt_1_hold_18), + .Wic_18(Wic_18), + .bi_18(bi_18), + .WfxrXtYt_1_18(WfxrXtYt_1_hold_18), + .Wfc_18(Wfc_18), + .bf_18(bf_18), + .WoxrXtYt_1_18(WoxrXtYt_1_hold_18), + .Woc_18(Woc_18), + .bo_18(bo_18), + .WcxrXtYt_1_18(WcxrXtYt_1_hold_18), + .bc_18(bc_18), + .out_mt_18(stage2_mt_18), + .out_ct_18(stage2_Ct_18), + .Ct_1_19(Ctt_1_19), + .WixrXtYt_1_19(WixrXtYt_1_hold_19), + .Wic_19(Wic_19), + .bi_19(bi_19), + .WfxrXtYt_1_19(WfxrXtYt_1_hold_19), + .Wfc_19(Wfc_19), + .bf_19(bf_19), + .WoxrXtYt_1_19(WoxrXtYt_1_hold_19), + .Woc_19(Woc_19), + .bo_19(bo_19), + .WcxrXtYt_1_19(WcxrXtYt_1_hold_19), + .bc_19(bc_19), + .out_mt_19(stage2_mt_19), + .out_ct_19(stage2_Ct_19), + .Ct_1_20(Ctt_1_20), + .WixrXtYt_1_20(WixrXtYt_1_hold_20), + .Wic_20(Wic_20), + .bi_20(bi_20), + .WfxrXtYt_1_20(WfxrXtYt_1_hold_20), + .Wfc_20(Wfc_20), + .bf_20(bf_20), + .WoxrXtYt_1_20(WoxrXtYt_1_hold_20), + .Woc_20(Woc_20), + .bo_20(bo_20), + .WcxrXtYt_1_20(WcxrXtYt_1_hold_20), + .bc_20(bc_20), + .out_mt_20(stage2_mt_20), + .out_ct_20(stage2_Ct_20), + .Ct_1_21(Ctt_1_21), + .WixrXtYt_1_21(WixrXtYt_1_hold_21), + .Wic_21(Wic_21), + .bi_21(bi_21), + .WfxrXtYt_1_21(WfxrXtYt_1_hold_21), + .Wfc_21(Wfc_21), + .bf_21(bf_21), + .WoxrXtYt_1_21(WoxrXtYt_1_hold_21), + .Woc_21(Woc_21), + .bo_21(bo_21), + .WcxrXtYt_1_21(WcxrXtYt_1_hold_21), + .bc_21(bc_21), + .out_mt_21(stage2_mt_21), + .out_ct_21(stage2_Ct_21), + .Ct_1_22(Ctt_1_22), + .WixrXtYt_1_22(WixrXtYt_1_hold_22), + .Wic_22(Wic_22), + .bi_22(bi_22), + .WfxrXtYt_1_22(WfxrXtYt_1_hold_22), + .Wfc_22(Wfc_22), + .bf_22(bf_22), + .WoxrXtYt_1_22(WoxrXtYt_1_hold_22), + .Woc_22(Woc_22), + .bo_22(bo_22), + .WcxrXtYt_1_22(WcxrXtYt_1_hold_22), + .bc_22(bc_22), + .out_mt_22(stage2_mt_22), + .out_ct_22(stage2_Ct_22), + .Ct_1_23(Ctt_1_23), + .WixrXtYt_1_23(WixrXtYt_1_hold_23), + .Wic_23(Wic_23), + .bi_23(bi_23), + .WfxrXtYt_1_23(WfxrXtYt_1_hold_23), + .Wfc_23(Wfc_23), + .bf_23(bf_23), + .WoxrXtYt_1_23(WoxrXtYt_1_hold_23), + .Woc_23(Woc_23), + .bo_23(bo_23), + .WcxrXtYt_1_23(WcxrXtYt_1_hold_23), + .bc_23(bc_23), + .out_mt_23(stage2_mt_23), + .out_ct_23(stage2_Ct_23), + .Ct_1_24(Ctt_1_24), + .WixrXtYt_1_24(WixrXtYt_1_hold_24), + .Wic_24(Wic_24), + .bi_24(bi_24), + .WfxrXtYt_1_24(WfxrXtYt_1_hold_24), + .Wfc_24(Wfc_24), + .bf_24(bf_24), + .WoxrXtYt_1_24(WoxrXtYt_1_hold_24), + .Woc_24(Woc_24), + .bo_24(bo_24), + .WcxrXtYt_1_24(WcxrXtYt_1_hold_24), + .bc_24(bc_24), + .out_mt_24(stage2_mt_24), + .out_ct_24(stage2_Ct_24), + .Ct_1_25(Ctt_1_25), + .WixrXtYt_1_25(WixrXtYt_1_hold_25), + .Wic_25(Wic_25), + .bi_25(bi_25), + .WfxrXtYt_1_25(WfxrXtYt_1_hold_25), + .Wfc_25(Wfc_25), + .bf_25(bf_25), + .WoxrXtYt_1_25(WoxrXtYt_1_hold_25), + .Woc_25(Woc_25), + .bo_25(bo_25), + .WcxrXtYt_1_25(WcxrXtYt_1_hold_25), + .bc_25(bc_25), + .out_mt_25(stage2_mt_25), + .out_ct_25(stage2_Ct_25), + .Ct_1_26(Ctt_1_26), + .WixrXtYt_1_26(WixrXtYt_1_hold_26), + .Wic_26(Wic_26), + .bi_26(bi_26), + .WfxrXtYt_1_26(WfxrXtYt_1_hold_26), + .Wfc_26(Wfc_26), + .bf_26(bf_26), + .WoxrXtYt_1_26(WoxrXtYt_1_hold_26), + .Woc_26(Woc_26), + .bo_26(bo_26), + .WcxrXtYt_1_26(WcxrXtYt_1_hold_26), + .bc_26(bc_26), + .out_mt_26(stage2_mt_26), + .out_ct_26(stage2_Ct_26), + .Ct_1_27(Ctt_1_27), + .WixrXtYt_1_27(WixrXtYt_1_hold_27), + .Wic_27(Wic_27), + .bi_27(bi_27), + .WfxrXtYt_1_27(WfxrXtYt_1_hold_27), + .Wfc_27(Wfc_27), + .bf_27(bf_27), + .WoxrXtYt_1_27(WoxrXtYt_1_hold_27), + .Woc_27(Woc_27), + .bo_27(bo_27), + .WcxrXtYt_1_27(WcxrXtYt_1_hold_27), + .bc_27(bc_27), + .out_mt_27(stage2_mt_27), + .out_ct_27(stage2_Ct_27), + .Ct_1_28(Ctt_1_28), + .WixrXtYt_1_28(WixrXtYt_1_hold_28), + .Wic_28(Wic_28), + .bi_28(bi_28), + .WfxrXtYt_1_28(WfxrXtYt_1_hold_28), + .Wfc_28(Wfc_28), + .bf_28(bf_28), + .WoxrXtYt_1_28(WoxrXtYt_1_hold_28), + .Woc_28(Woc_28), + .bo_28(bo_28), + .WcxrXtYt_1_28(WcxrXtYt_1_hold_28), + .bc_28(bc_28), + .out_mt_28(stage2_mt_28), + .out_ct_28(stage2_Ct_28), + .Ct_1_29(Ctt_1_29), + .WixrXtYt_1_29(WixrXtYt_1_hold_29), + .Wic_29(Wic_29), + .bi_29(bi_29), + .WfxrXtYt_1_29(WfxrXtYt_1_hold_29), + .Wfc_29(Wfc_29), + .bf_29(bf_29), + .WoxrXtYt_1_29(WoxrXtYt_1_hold_29), + .Woc_29(Woc_29), + .bo_29(bo_29), + .WcxrXtYt_1_29(WcxrXtYt_1_hold_29), + .bc_29(bc_29), + .out_mt_29(stage2_mt_29), + .out_ct_29(stage2_Ct_29), + .Ct_1_30(Ctt_1_30), + .WixrXtYt_1_30(WixrXtYt_1_hold_30), + .Wic_30(Wic_30), + .bi_30(bi_30), + .WfxrXtYt_1_30(WfxrXtYt_1_hold_30), + .Wfc_30(Wfc_30), + .bf_30(bf_30), + .WoxrXtYt_1_30(WoxrXtYt_1_hold_30), + .Woc_30(Woc_30), + .bo_30(bo_30), + .WcxrXtYt_1_30(WcxrXtYt_1_hold_30), + .bc_30(bc_30), + .out_mt_30(stage2_mt_30), + .out_ct_30(stage2_Ct_30), + .Ct_1_31(Ctt_1_31), + .WixrXtYt_1_31(WixrXtYt_1_hold_31), + .Wic_31(Wic_31), + .bi_31(bi_31), + .WfxrXtYt_1_31(WfxrXtYt_1_hold_31), + .Wfc_31(Wfc_31), + .bf_31(bf_31), + .WoxrXtYt_1_31(WoxrXtYt_1_hold_31), + .Woc_31(Woc_31), + .bo_31(bo_31), + .WcxrXtYt_1_31(WcxrXtYt_1_hold_31), + .bc_31(bc_31), + .out_mt_31(stage2_mt_31), + .out_ct_31(stage2_Ct_31), + .Ct_1_32(Ctt_1_32), + .WixrXtYt_1_32(WixrXtYt_1_hold_32), + .Wic_32(Wic_32), + .bi_32(bi_32), + .WfxrXtYt_1_32(WfxrXtYt_1_hold_32), + .Wfc_32(Wfc_32), + .bf_32(bf_32), + .WoxrXtYt_1_32(WoxrXtYt_1_hold_32), + .Woc_32(Woc_32), + .bo_32(bo_32), + .WcxrXtYt_1_32(WcxrXtYt_1_hold_32), + .bc_32(bc_32), + .out_mt_32(stage2_mt_32), + .out_ct_32(stage2_Ct_32), + .Ct_1_33(Ctt_1_33), + .WixrXtYt_1_33(WixrXtYt_1_hold_33), + .Wic_33(Wic_33), + .bi_33(bi_33), + .WfxrXtYt_1_33(WfxrXtYt_1_hold_33), + .Wfc_33(Wfc_33), + .bf_33(bf_33), + .WoxrXtYt_1_33(WoxrXtYt_1_hold_33), + .Woc_33(Woc_33), + .bo_33(bo_33), + .WcxrXtYt_1_33(WcxrXtYt_1_hold_33), + .bc_33(bc_33), + .out_mt_33(stage2_mt_33), + .out_ct_33(stage2_Ct_33), + .Ct_1_34(Ctt_1_34), + .WixrXtYt_1_34(WixrXtYt_1_hold_34), + .Wic_34(Wic_34), + .bi_34(bi_34), + .WfxrXtYt_1_34(WfxrXtYt_1_hold_34), + .Wfc_34(Wfc_34), + .bf_34(bf_34), + .WoxrXtYt_1_34(WoxrXtYt_1_hold_34), + .Woc_34(Woc_34), + .bo_34(bo_34), + .WcxrXtYt_1_34(WcxrXtYt_1_hold_34), + .bc_34(bc_34), + .out_mt_34(stage2_mt_34), + .out_ct_34(stage2_Ct_34), + .Ct_1_35(Ctt_1_35), + .WixrXtYt_1_35(WixrXtYt_1_hold_35), + .Wic_35(Wic_35), + .bi_35(bi_35), + .WfxrXtYt_1_35(WfxrXtYt_1_hold_35), + .Wfc_35(Wfc_35), + .bf_35(bf_35), + .WoxrXtYt_1_35(WoxrXtYt_1_hold_35), + .Woc_35(Woc_35), + .bo_35(bo_35), + .WcxrXtYt_1_35(WcxrXtYt_1_hold_35), + .bc_35(bc_35), + .out_mt_35(stage2_mt_35), + .out_ct_35(stage2_Ct_35), + .Ct_1_36(Ctt_1_36), + .WixrXtYt_1_36(WixrXtYt_1_hold_36), + .Wic_36(Wic_36), + .bi_36(bi_36), + .WfxrXtYt_1_36(WfxrXtYt_1_hold_36), + .Wfc_36(Wfc_36), + .bf_36(bf_36), + .WoxrXtYt_1_36(WoxrXtYt_1_hold_36), + .Woc_36(Woc_36), + .bo_36(bo_36), + .WcxrXtYt_1_36(WcxrXtYt_1_hold_36), + .bc_36(bc_36), + .out_mt_36(stage2_mt_36), + .out_ct_36(stage2_Ct_36), + .Ct_1_37(Ctt_1_37), + .WixrXtYt_1_37(WixrXtYt_1_hold_37), + .Wic_37(Wic_37), + .bi_37(bi_37), + .WfxrXtYt_1_37(WfxrXtYt_1_hold_37), + .Wfc_37(Wfc_37), + .bf_37(bf_37), + .WoxrXtYt_1_37(WoxrXtYt_1_hold_37), + .Woc_37(Woc_37), + .bo_37(bo_37), + .WcxrXtYt_1_37(WcxrXtYt_1_hold_37), + .bc_37(bc_37), + .out_mt_37(stage2_mt_37), + .out_ct_37(stage2_Ct_37), + .Ct_1_38(Ctt_1_38), + .WixrXtYt_1_38(WixrXtYt_1_hold_38), + .Wic_38(Wic_38), + .bi_38(bi_38), + .WfxrXtYt_1_38(WfxrXtYt_1_hold_38), + .Wfc_38(Wfc_38), + .bf_38(bf_38), + .WoxrXtYt_1_38(WoxrXtYt_1_hold_38), + .Woc_38(Woc_38), + .bo_38(bo_38), + .WcxrXtYt_1_38(WcxrXtYt_1_hold_38), + .bc_38(bc_38), + .out_mt_38(stage2_mt_38), + .out_ct_38(stage2_Ct_38), + .Ct_1_39(Ctt_1_39), + .WixrXtYt_1_39(WixrXtYt_1_hold_39), + .Wic_39(Wic_39), + .bi_39(bi_39), + .WfxrXtYt_1_39(WfxrXtYt_1_hold_39), + .Wfc_39(Wfc_39), + .bf_39(bf_39), + .WoxrXtYt_1_39(WoxrXtYt_1_hold_39), + .Woc_39(Woc_39), + .bo_39(bo_39), + .WcxrXtYt_1_39(WcxrXtYt_1_hold_39), + .bc_39(bc_39), + .out_mt_39(stage2_mt_39), + .out_ct_39(stage2_Ct_39), + .Ct_1_40(Ctt_1_40), + .WixrXtYt_1_40(WixrXtYt_1_hold_40), + .Wic_40(Wic_40), + .bi_40(bi_40), + .WfxrXtYt_1_40(WfxrXtYt_1_hold_40), + .Wfc_40(Wfc_40), + .bf_40(bf_40), + .WoxrXtYt_1_40(WoxrXtYt_1_hold_40), + .Woc_40(Woc_40), + .bo_40(bo_40), + .WcxrXtYt_1_40(WcxrXtYt_1_hold_40), + .bc_40(bc_40), + .out_mt_40(stage2_mt_40), + .out_ct_40(stage2_Ct_40), + .Ct_1_41(Ctt_1_41), + .WixrXtYt_1_41(WixrXtYt_1_hold_41), + .Wic_41(Wic_41), + .bi_41(bi_41), + .WfxrXtYt_1_41(WfxrXtYt_1_hold_41), + .Wfc_41(Wfc_41), + .bf_41(bf_41), + .WoxrXtYt_1_41(WoxrXtYt_1_hold_41), + .Woc_41(Woc_41), + .bo_41(bo_41), + .WcxrXtYt_1_41(WcxrXtYt_1_hold_41), + .bc_41(bc_41), + .out_mt_41(stage2_mt_41), + .out_ct_41(stage2_Ct_41), + .Ct_1_42(Ctt_1_42), + .WixrXtYt_1_42(WixrXtYt_1_hold_42), + .Wic_42(Wic_42), + .bi_42(bi_42), + .WfxrXtYt_1_42(WfxrXtYt_1_hold_42), + .Wfc_42(Wfc_42), + .bf_42(bf_42), + .WoxrXtYt_1_42(WoxrXtYt_1_hold_42), + .Woc_42(Woc_42), + .bo_42(bo_42), + .WcxrXtYt_1_42(WcxrXtYt_1_hold_42), + .bc_42(bc_42), + .out_mt_42(stage2_mt_42), + .out_ct_42(stage2_Ct_42), + .Ct_1_43(Ctt_1_43), + .WixrXtYt_1_43(WixrXtYt_1_hold_43), + .Wic_43(Wic_43), + .bi_43(bi_43), + .WfxrXtYt_1_43(WfxrXtYt_1_hold_43), + .Wfc_43(Wfc_43), + .bf_43(bf_43), + .WoxrXtYt_1_43(WoxrXtYt_1_hold_43), + .Woc_43(Woc_43), + .bo_43(bo_43), + .WcxrXtYt_1_43(WcxrXtYt_1_hold_43), + .bc_43(bc_43), + .out_mt_43(stage2_mt_43), + .out_ct_43(stage2_Ct_43), + .Ct_1_44(Ctt_1_44), + .WixrXtYt_1_44(WixrXtYt_1_hold_44), + .Wic_44(Wic_44), + .bi_44(bi_44), + .WfxrXtYt_1_44(WfxrXtYt_1_hold_44), + .Wfc_44(Wfc_44), + .bf_44(bf_44), + .WoxrXtYt_1_44(WoxrXtYt_1_hold_44), + .Woc_44(Woc_44), + .bo_44(bo_44), + .WcxrXtYt_1_44(WcxrXtYt_1_hold_44), + .bc_44(bc_44), + .out_mt_44(stage2_mt_44), + .out_ct_44(stage2_Ct_44), + .Ct_1_45(Ctt_1_45), + .WixrXtYt_1_45(WixrXtYt_1_hold_45), + .Wic_45(Wic_45), + .bi_45(bi_45), + .WfxrXtYt_1_45(WfxrXtYt_1_hold_45), + .Wfc_45(Wfc_45), + .bf_45(bf_45), + .WoxrXtYt_1_45(WoxrXtYt_1_hold_45), + .Woc_45(Woc_45), + .bo_45(bo_45), + .WcxrXtYt_1_45(WcxrXtYt_1_hold_45), + .bc_45(bc_45), + .out_mt_45(stage2_mt_45), + .out_ct_45(stage2_Ct_45), + .Ct_1_46(Ctt_1_46), + .WixrXtYt_1_46(WixrXtYt_1_hold_46), + .Wic_46(Wic_46), + .bi_46(bi_46), + .WfxrXtYt_1_46(WfxrXtYt_1_hold_46), + .Wfc_46(Wfc_46), + .bf_46(bf_46), + .WoxrXtYt_1_46(WoxrXtYt_1_hold_46), + .Woc_46(Woc_46), + .bo_46(bo_46), + .WcxrXtYt_1_46(WcxrXtYt_1_hold_46), + .bc_46(bc_46), + .out_mt_46(stage2_mt_46), + .out_ct_46(stage2_Ct_46), + .Ct_1_47(Ctt_1_47), + .WixrXtYt_1_47(WixrXtYt_1_hold_47), + .Wic_47(Wic_47), + .bi_47(bi_47), + .WfxrXtYt_1_47(WfxrXtYt_1_hold_47), + .Wfc_47(Wfc_47), + .bf_47(bf_47), + .WoxrXtYt_1_47(WoxrXtYt_1_hold_47), + .Woc_47(Woc_47), + .bo_47(bo_47), + .WcxrXtYt_1_47(WcxrXtYt_1_hold_47), + .bc_47(bc_47), + .out_mt_47(stage2_mt_47), + .out_ct_47(stage2_Ct_47), + .o_valid(stage2_valid), + .o_ready(stage2_ready) +); + +wire [17:0] mt_0_0; +wire [17:0] Ct_0_0; +wire [17:0] mt_0_1; +wire [17:0] Ct_0_1; +wire [17:0] mt_0_2; +wire [17:0] Ct_0_2; +wire [17:0] mt_0_3; +wire [17:0] Ct_0_3; +wire [17:0] mt_0_4; +wire [17:0] Ct_0_4; +wire [17:0] mt_0_5; +wire [17:0] Ct_0_5; +wire [17:0] mt_0_6; +wire [17:0] Ct_0_6; +wire [17:0] mt_0_7; +wire [17:0] Ct_0_7; +wire [17:0] mt_0_8; +wire [17:0] Ct_0_8; +wire [17:0] mt_0_9; +wire [17:0] Ct_0_9; +wire [17:0] mt_0_10; +wire [17:0] Ct_0_10; +wire [17:0] mt_0_11; +wire [17:0] Ct_0_11; +wire [17:0] mt_0_12; +wire [17:0] Ct_0_12; +wire [17:0] mt_0_13; +wire [17:0] Ct_0_13; +wire [17:0] mt_0_14; +wire [17:0] Ct_0_14; +wire [17:0] mt_0_15; +wire [17:0] Ct_0_15; +wire [17:0] mt_1_0; +wire [17:0] Ct_1_0; +wire [17:0] mt_1_1; +wire [17:0] Ct_1_1; +wire [17:0] mt_1_2; +wire [17:0] Ct_1_2; +wire [17:0] mt_1_3; +wire [17:0] Ct_1_3; +wire [17:0] mt_1_4; +wire [17:0] Ct_1_4; +wire [17:0] mt_1_5; +wire [17:0] Ct_1_5; +wire [17:0] mt_1_6; +wire [17:0] Ct_1_6; +wire [17:0] mt_1_7; +wire [17:0] Ct_1_7; +wire [17:0] mt_1_8; +wire [17:0] Ct_1_8; +wire [17:0] mt_1_9; +wire [17:0] Ct_1_9; +wire [17:0] mt_1_10; +wire [17:0] Ct_1_10; +wire [17:0] mt_1_11; +wire [17:0] Ct_1_11; +wire [17:0] mt_1_12; +wire [17:0] Ct_1_12; +wire [17:0] mt_1_13; +wire [17:0] Ct_1_13; +wire [17:0] mt_1_14; +wire [17:0] Ct_1_14; +wire [17:0] mt_1_15; +wire [17:0] Ct_1_15; +wire [17:0] mt_2_0; +wire [17:0] Ct_2_0; +wire [17:0] mt_2_1; +wire [17:0] Ct_2_1; +wire [17:0] mt_2_2; +wire [17:0] Ct_2_2; +wire [17:0] mt_2_3; +wire [17:0] Ct_2_3; +wire [17:0] mt_2_4; +wire [17:0] Ct_2_4; +wire [17:0] mt_2_5; +wire [17:0] Ct_2_5; +wire [17:0] mt_2_6; +wire [17:0] Ct_2_6; +wire [17:0] mt_2_7; +wire [17:0] Ct_2_7; +wire [17:0] mt_2_8; +wire [17:0] Ct_2_8; +wire [17:0] mt_2_9; +wire [17:0] Ct_2_9; +wire [17:0] mt_2_10; +wire [17:0] Ct_2_10; +wire [17:0] mt_2_11; +wire [17:0] Ct_2_11; +wire [17:0] mt_2_12; +wire [17:0] Ct_2_12; +wire [17:0] mt_2_13; +wire [17:0] Ct_2_13; +wire [17:0] mt_2_14; +wire [17:0] Ct_2_14; +wire [17:0] mt_2_15; +wire [17:0] Ct_2_15; + +assign Ct_0_0 = stage2_Ct_0; +assign mt_0_0 = stage2_mt_0; +assign Ct_0_1 = stage2_Ct_1; +assign mt_0_1 = stage2_mt_1; +assign Ct_0_2 = stage2_Ct_2; +assign mt_0_2 = stage2_mt_2; +assign Ct_0_3 = stage2_Ct_3; +assign mt_0_3 = stage2_mt_3; +assign Ct_0_4 = stage2_Ct_4; +assign mt_0_4 = stage2_mt_4; +assign Ct_0_5 = stage2_Ct_5; +assign mt_0_5 = stage2_mt_5; +assign Ct_0_6 = stage2_Ct_6; +assign mt_0_6 = stage2_mt_6; +assign Ct_0_7 = stage2_Ct_7; +assign mt_0_7 = stage2_mt_7; +assign Ct_0_8 = stage2_Ct_8; +assign mt_0_8 = stage2_mt_8; +assign Ct_0_9 = stage2_Ct_9; +assign mt_0_9 = stage2_mt_9; +assign Ct_0_10 = stage2_Ct_10; +assign mt_0_10 = stage2_mt_10; +assign Ct_0_11 = stage2_Ct_11; +assign mt_0_11 = stage2_mt_11; +assign Ct_0_12 = stage2_Ct_12; +assign mt_0_12 = stage2_mt_12; +assign Ct_0_13 = stage2_Ct_13; +assign mt_0_13 = stage2_mt_13; +assign Ct_0_14 = stage2_Ct_14; +assign mt_0_14 = stage2_mt_14; +assign Ct_0_15 = stage2_Ct_15; +assign mt_0_15 = stage2_mt_15; +assign Ct_1_0 = stage2_Ct_16; +assign mt_1_0 = stage2_mt_16; +assign Ct_1_1 = stage2_Ct_17; +assign mt_1_1 = stage2_mt_17; +assign Ct_1_2 = stage2_Ct_18; +assign mt_1_2 = stage2_mt_18; +assign Ct_1_3 = stage2_Ct_19; +assign mt_1_3 = stage2_mt_19; +assign Ct_1_4 = stage2_Ct_20; +assign mt_1_4 = stage2_mt_20; +assign Ct_1_5 = stage2_Ct_21; +assign mt_1_5 = stage2_mt_21; +assign Ct_1_6 = stage2_Ct_22; +assign mt_1_6 = stage2_mt_22; +assign Ct_1_7 = stage2_Ct_23; +assign mt_1_7 = stage2_mt_23; +assign Ct_1_8 = stage2_Ct_24; +assign mt_1_8 = stage2_mt_24; +assign Ct_1_9 = stage2_Ct_25; +assign mt_1_9 = stage2_mt_25; +assign Ct_1_10 = stage2_Ct_26; +assign mt_1_10 = stage2_mt_26; +assign Ct_1_11 = stage2_Ct_27; +assign mt_1_11 = stage2_mt_27; +assign Ct_1_12 = stage2_Ct_28; +assign mt_1_12 = stage2_mt_28; +assign Ct_1_13 = stage2_Ct_29; +assign mt_1_13 = stage2_mt_29; +assign Ct_1_14 = stage2_Ct_30; +assign mt_1_14 = stage2_mt_30; +assign Ct_1_15 = stage2_Ct_31; +assign mt_1_15 = stage2_mt_31; +assign Ct_2_0 = stage2_Ct_32; +assign mt_2_0 = stage2_mt_32; +assign Ct_2_1 = stage2_Ct_33; +assign mt_2_1 = stage2_mt_33; +assign Ct_2_2 = stage2_Ct_34; +assign mt_2_2 = stage2_mt_34; +assign Ct_2_3 = stage2_Ct_35; +assign mt_2_3 = stage2_mt_35; +assign Ct_2_4 = stage2_Ct_36; +assign mt_2_4 = stage2_mt_36; +assign Ct_2_5 = stage2_Ct_37; +assign mt_2_5 = stage2_mt_37; +assign Ct_2_6 = stage2_Ct_38; +assign mt_2_6 = stage2_mt_38; +assign Ct_2_7 = stage2_Ct_39; +assign mt_2_7 = stage2_mt_39; +assign Ct_2_8 = stage2_Ct_40; +assign mt_2_8 = stage2_mt_40; +assign Ct_2_9 = stage2_Ct_41; +assign mt_2_9 = stage2_mt_41; +assign Ct_2_10 = stage2_Ct_42; +assign mt_2_10 = stage2_mt_42; +assign Ct_2_11 = stage2_Ct_43; +assign mt_2_11 = stage2_mt_43; +assign Ct_2_12 = stage2_Ct_44; +assign mt_2_12 = stage2_mt_44; +assign Ct_2_13 = stage2_Ct_45; +assign mt_2_13 = stage2_mt_45; +assign Ct_2_14 = stage2_Ct_46; +assign mt_2_14 = stage2_mt_46; +assign Ct_2_15 = stage2_Ct_47; +assign mt_2_15 = stage2_mt_47; + +// C-LSTM buffer between stage2 and stage3 +wire buffer_out_valid, pipelined_mt_valid, pipelined_Ct_valid; +wire [17:0] mt_pipelined_0; +wire [17:0] Ct_pipelined_0; +wire [17:0] out_mt_buffer_0; +wire [17:0] mt_pipelined_1; +wire [17:0] Ct_pipelined_1; +wire [17:0] out_mt_buffer_1; +wire [17:0] mt_pipelined_2; +wire [17:0] Ct_pipelined_2; +wire [17:0] out_mt_buffer_2; +wire [17:0] mt_pipelined_3; +wire [17:0] Ct_pipelined_3; +wire [17:0] out_mt_buffer_3; +wire [17:0] mt_pipelined_4; +wire [17:0] Ct_pipelined_4; +wire [17:0] out_mt_buffer_4; +wire [17:0] mt_pipelined_5; +wire [17:0] Ct_pipelined_5; +wire [17:0] out_mt_buffer_5; +wire [17:0] mt_pipelined_6; +wire [17:0] Ct_pipelined_6; +wire [17:0] out_mt_buffer_6; +wire [17:0] mt_pipelined_7; +wire [17:0] Ct_pipelined_7; +wire [17:0] out_mt_buffer_7; +wire [17:0] mt_pipelined_8; +wire [17:0] Ct_pipelined_8; +wire [17:0] out_mt_buffer_8; +wire [17:0] mt_pipelined_9; +wire [17:0] Ct_pipelined_9; +wire [17:0] out_mt_buffer_9; +wire [17:0] mt_pipelined_10; +wire [17:0] Ct_pipelined_10; +wire [17:0] out_mt_buffer_10; +wire [17:0] mt_pipelined_11; +wire [17:0] Ct_pipelined_11; +wire [17:0] out_mt_buffer_11; +wire [17:0] mt_pipelined_12; +wire [17:0] Ct_pipelined_12; +wire [17:0] out_mt_buffer_12; +wire [17:0] mt_pipelined_13; +wire [17:0] Ct_pipelined_13; +wire [17:0] out_mt_buffer_13; +wire [17:0] mt_pipelined_14; +wire [17:0] Ct_pipelined_14; +wire [17:0] out_mt_buffer_14; +wire [17:0] mt_pipelined_15; +wire [17:0] Ct_pipelined_15; +wire [17:0] out_mt_buffer_15; + +pipelined_input_18_3_16 pipelined_input_18_3_16_inst_mt ( + .clk(clk), + .reset(reset), + .enable(enable), + .load_input(stage2_valid), + .i_data_0_0(mt_0_0), + .i_data_0_1(mt_0_1), + .i_data_0_2(mt_0_2), + .i_data_0_3(mt_0_3), + .i_data_0_4(mt_0_4), + .i_data_0_5(mt_0_5), + .i_data_0_6(mt_0_6), + .i_data_0_7(mt_0_7), + .i_data_0_8(mt_0_8), + .i_data_0_9(mt_0_9), + .i_data_0_10(mt_0_10), + .i_data_0_11(mt_0_11), + .i_data_0_12(mt_0_12), + .i_data_0_13(mt_0_13), + .i_data_0_14(mt_0_14), + .i_data_0_15(mt_0_15), + .i_data_1_0(mt_1_0), + .i_data_1_1(mt_1_1), + .i_data_1_2(mt_1_2), + .i_data_1_3(mt_1_3), + .i_data_1_4(mt_1_4), + .i_data_1_5(mt_1_5), + .i_data_1_6(mt_1_6), + .i_data_1_7(mt_1_7), + .i_data_1_8(mt_1_8), + .i_data_1_9(mt_1_9), + .i_data_1_10(mt_1_10), + .i_data_1_11(mt_1_11), + .i_data_1_12(mt_1_12), + .i_data_1_13(mt_1_13), + .i_data_1_14(mt_1_14), + .i_data_1_15(mt_1_15), + .i_data_2_0(mt_2_0), + .i_data_2_1(mt_2_1), + .i_data_2_2(mt_2_2), + .i_data_2_3(mt_2_3), + .i_data_2_4(mt_2_4), + .i_data_2_5(mt_2_5), + .i_data_2_6(mt_2_6), + .i_data_2_7(mt_2_7), + .i_data_2_8(mt_2_8), + .i_data_2_9(mt_2_9), + .i_data_2_10(mt_2_10), + .i_data_2_11(mt_2_11), + .i_data_2_12(mt_2_12), + .i_data_2_13(mt_2_13), + .i_data_2_14(mt_2_14), + .i_data_2_15(mt_2_15), + .o_data_0(mt_pipelined_0), + .o_data_1(mt_pipelined_1), + .o_data_2(mt_pipelined_2), + .o_data_3(mt_pipelined_3), + .o_data_4(mt_pipelined_4), + .o_data_5(mt_pipelined_5), + .o_data_6(mt_pipelined_6), + .o_data_7(mt_pipelined_7), + .o_data_8(mt_pipelined_8), + .o_data_9(mt_pipelined_9), + .o_data_10(mt_pipelined_10), + .o_data_11(mt_pipelined_11), + .o_data_12(mt_pipelined_12), + .o_data_13(mt_pipelined_13), + .o_data_14(mt_pipelined_14), + .o_data_15(mt_pipelined_15), + .o_valid(pipelined_mt_valid) +); + +pipelined_input_18_3_16 pipelined_input_18_3_16_inst_Ct ( + .clk(clk), + .reset(reset), + .enable(enable), + .load_input(stage2_valid), + .i_data_0_0(Ct_0_0), + .i_data_0_1(Ct_0_1), + .i_data_0_2(Ct_0_2), + .i_data_0_3(Ct_0_3), + .i_data_0_4(Ct_0_4), + .i_data_0_5(Ct_0_5), + .i_data_0_6(Ct_0_6), + .i_data_0_7(Ct_0_7), + .i_data_0_8(Ct_0_8), + .i_data_0_9(Ct_0_9), + .i_data_0_10(Ct_0_10), + .i_data_0_11(Ct_0_11), + .i_data_0_12(Ct_0_12), + .i_data_0_13(Ct_0_13), + .i_data_0_14(Ct_0_14), + .i_data_0_15(Ct_0_15), + .i_data_1_0(Ct_1_0), + .i_data_1_1(Ct_1_1), + .i_data_1_2(Ct_1_2), + .i_data_1_3(Ct_1_3), + .i_data_1_4(Ct_1_4), + .i_data_1_5(Ct_1_5), + .i_data_1_6(Ct_1_6), + .i_data_1_7(Ct_1_7), + .i_data_1_8(Ct_1_8), + .i_data_1_9(Ct_1_9), + .i_data_1_10(Ct_1_10), + .i_data_1_11(Ct_1_11), + .i_data_1_12(Ct_1_12), + .i_data_1_13(Ct_1_13), + .i_data_1_14(Ct_1_14), + .i_data_1_15(Ct_1_15), + .i_data_2_0(Ct_2_0), + .i_data_2_1(Ct_2_1), + .i_data_2_2(Ct_2_2), + .i_data_2_3(Ct_2_3), + .i_data_2_4(Ct_2_4), + .i_data_2_5(Ct_2_5), + .i_data_2_6(Ct_2_6), + .i_data_2_7(Ct_2_7), + .i_data_2_8(Ct_2_8), + .i_data_2_9(Ct_2_9), + .i_data_2_10(Ct_2_10), + .i_data_2_11(Ct_2_11), + .i_data_2_12(Ct_2_12), + .i_data_2_13(Ct_2_13), + .i_data_2_14(Ct_2_14), + .i_data_2_15(Ct_2_15), + .o_data_0(Ct_pipelined_0), + .o_data_1(Ct_pipelined_1), + .o_data_2(Ct_pipelined_2), + .o_data_3(Ct_pipelined_3), + .o_data_4(Ct_pipelined_4), + .o_data_5(Ct_pipelined_5), + .o_data_6(Ct_pipelined_6), + .o_data_7(Ct_pipelined_7), + .o_data_8(Ct_pipelined_8), + .o_data_9(Ct_pipelined_9), + .o_data_10(Ct_pipelined_10), + .o_data_11(Ct_pipelined_11), + .o_data_12(Ct_pipelined_12), + .o_data_13(Ct_pipelined_13), + .o_data_14(Ct_pipelined_14), + .o_data_15(Ct_pipelined_15), + .o_valid(pipelined_Ct_valid) +); + +stage2_Ct_buffer_18_3_16_64 stage2_Ct_buffer_18_3_16_64_inst_kcbgzbafqo ( + .clk(clk), + .reset(reset), + .wen(pipelined_Ct_valid), + .ren(stage1_valid), + .i_Ct_0(Ct_pipelined_0), + .i_Ct_1(Ct_pipelined_1), + .i_Ct_2(Ct_pipelined_2), + .i_Ct_3(Ct_pipelined_3), + .i_Ct_4(Ct_pipelined_4), + .i_Ct_5(Ct_pipelined_5), + .i_Ct_6(Ct_pipelined_6), + .i_Ct_7(Ct_pipelined_7), + .i_Ct_8(Ct_pipelined_8), + .i_Ct_9(Ct_pipelined_9), + .i_Ct_10(Ct_pipelined_10), + .i_Ct_11(Ct_pipelined_11), + .i_Ct_12(Ct_pipelined_12), + .i_Ct_13(Ct_pipelined_13), + .i_Ct_14(Ct_pipelined_14), + .i_Ct_15(Ct_pipelined_15), + .o_Ct_0(Ctt_1_0), + .o_Ct_1(Ctt_1_1), + .o_Ct_2(Ctt_1_2), + .o_Ct_3(Ctt_1_3), + .o_Ct_4(Ctt_1_4), + .o_Ct_5(Ctt_1_5), + .o_Ct_6(Ctt_1_6), + .o_Ct_7(Ctt_1_7), + .o_Ct_8(Ctt_1_8), + .o_Ct_9(Ctt_1_9), + .o_Ct_10(Ctt_1_10), + .o_Ct_11(Ctt_1_11), + .o_Ct_12(Ctt_1_12), + .o_Ct_13(Ctt_1_13), + .o_Ct_14(Ctt_1_14), + .o_Ct_15(Ctt_1_15), + .o_Ct_16(Ctt_1_16), + .o_Ct_17(Ctt_1_17), + .o_Ct_18(Ctt_1_18), + .o_Ct_19(Ctt_1_19), + .o_Ct_20(Ctt_1_20), + .o_Ct_21(Ctt_1_21), + .o_Ct_22(Ctt_1_22), + .o_Ct_23(Ctt_1_23), + .o_Ct_24(Ctt_1_24), + .o_Ct_25(Ctt_1_25), + .o_Ct_26(Ctt_1_26), + .o_Ct_27(Ctt_1_27), + .o_Ct_28(Ctt_1_28), + .o_Ct_29(Ctt_1_29), + .o_Ct_30(Ctt_1_30), + .o_Ct_31(Ctt_1_31), + .o_Ct_32(Ctt_1_32), + .o_Ct_33(Ctt_1_33), + .o_Ct_34(Ctt_1_34), + .o_Ct_35(Ctt_1_35), + .o_Ct_36(Ctt_1_36), + .o_Ct_37(Ctt_1_37), + .o_Ct_38(Ctt_1_38), + .o_Ct_39(Ctt_1_39), + .o_Ct_40(Ctt_1_40), + .o_Ct_41(Ctt_1_41), + .o_Ct_42(Ctt_1_42), + .o_Ct_43(Ctt_1_43), + .o_Ct_44(Ctt_1_44), + .o_Ct_45(Ctt_1_45), + .o_Ct_46(Ctt_1_46), + .o_Ct_47(Ctt_1_47), + .o_valid() +); + +stage2_mt_buffer_18_3_16_64_32 stage2_mt_buffer_18_3_16_64_32_inst_rpxyjpyeiz ( + .clk(clk), + .reset(reset), + .i_valid(pipelined_mt_valid), + .data_0(mt_pipelined_0), + .q_0(out_mt_buffer_0), + .data_1(mt_pipelined_1), + .q_1(out_mt_buffer_1), + .data_2(mt_pipelined_2), + .q_2(out_mt_buffer_2), + .data_3(mt_pipelined_3), + .q_3(out_mt_buffer_3), + .data_4(mt_pipelined_4), + .q_4(out_mt_buffer_4), + .data_5(mt_pipelined_5), + .q_5(out_mt_buffer_5), + .data_6(mt_pipelined_6), + .q_6(out_mt_buffer_6), + .data_7(mt_pipelined_7), + .q_7(out_mt_buffer_7), + .data_8(mt_pipelined_8), + .q_8(out_mt_buffer_8), + .data_9(mt_pipelined_9), + .q_9(out_mt_buffer_9), + .data_10(mt_pipelined_10), + .q_10(out_mt_buffer_10), + .data_11(mt_pipelined_11), + .q_11(out_mt_buffer_11), + .data_12(mt_pipelined_12), + .q_12(out_mt_buffer_12), + .data_13(mt_pipelined_13), + .q_13(out_mt_buffer_13), + .data_14(mt_pipelined_14), + .q_14(out_mt_buffer_14), + .data_15(mt_pipelined_15), + .q_15(out_mt_buffer_15), + .o_valid(buffer_out_valid) +); + +// C-LSTM Stage 3 and inner-connections +wire stage3_valid, stage3_ready; +wire [17:0] new_Yt_0_0; +wire [17:0] new_Yt_0_1; +wire [17:0] new_Yt_0_2; +wire [17:0] new_Yt_0_3; +wire [17:0] new_Yt_0_4; +wire [17:0] new_Yt_0_5; +wire [17:0] new_Yt_0_6; +wire [17:0] new_Yt_0_7; +wire [17:0] new_Yt_0_8; +wire [17:0] new_Yt_0_9; +wire [17:0] new_Yt_0_10; +wire [17:0] new_Yt_0_11; +wire [17:0] new_Yt_0_12; +wire [17:0] new_Yt_0_13; +wire [17:0] new_Yt_0_14; +wire [17:0] new_Yt_0_15; +wire [17:0] new_Yt_1_0; +wire [17:0] new_Yt_1_1; +wire [17:0] new_Yt_1_2; +wire [17:0] new_Yt_1_3; +wire [17:0] new_Yt_1_4; +wire [17:0] new_Yt_1_5; +wire [17:0] new_Yt_1_6; +wire [17:0] new_Yt_1_7; +wire [17:0] new_Yt_1_8; +wire [17:0] new_Yt_1_9; +wire [17:0] new_Yt_1_10; +wire [17:0] new_Yt_1_11; +wire [17:0] new_Yt_1_12; +wire [17:0] new_Yt_1_13; +wire [17:0] new_Yt_1_14; +wire [17:0] new_Yt_1_15; +wire [17:0] new_Yt_2_0; +wire [17:0] new_Yt_2_1; +wire [17:0] new_Yt_2_2; +wire [17:0] new_Yt_2_3; +wire [17:0] new_Yt_2_4; +wire [17:0] new_Yt_2_5; +wire [17:0] new_Yt_2_6; +wire [17:0] new_Yt_2_7; +wire [17:0] new_Yt_2_8; +wire [17:0] new_Yt_2_9; +wire [17:0] new_Yt_2_10; +wire [17:0] new_Yt_2_11; +wire [17:0] new_Yt_2_12; +wire [17:0] new_Yt_2_13; +wire [17:0] new_Yt_2_14; +wire [17:0] new_Yt_2_15; + +C_LSTM_stage_3_18_10_64_2048_3_16_1 C_LSTM_stage_3_18_10_64_2048_3_16_1_inst_siyrhbrrne ( + .clk(clk), + .reset(reset), + .wdata(wdata_stage3), + .wen(wen_stage3), + .i_ready(enable), + .i_valid(buffer_out_valid), + .i_mt_0(out_mt_buffer_0), + .i_mt_1(out_mt_buffer_1), + .i_mt_2(out_mt_buffer_2), + .i_mt_3(out_mt_buffer_3), + .i_mt_4(out_mt_buffer_4), + .i_mt_5(out_mt_buffer_5), + .i_mt_6(out_mt_buffer_6), + .i_mt_7(out_mt_buffer_7), + .i_mt_8(out_mt_buffer_8), + .i_mt_9(out_mt_buffer_9), + .i_mt_10(out_mt_buffer_10), + .i_mt_11(out_mt_buffer_11), + .i_mt_12(out_mt_buffer_12), + .i_mt_13(out_mt_buffer_13), + .i_mt_14(out_mt_buffer_14), + .i_mt_15(out_mt_buffer_15), + .o_Yt_0_0(new_Yt_0_0), + .o_Yt_0_1(new_Yt_0_1), + .o_Yt_0_2(new_Yt_0_2), + .o_Yt_0_3(new_Yt_0_3), + .o_Yt_0_4(new_Yt_0_4), + .o_Yt_0_5(new_Yt_0_5), + .o_Yt_0_6(new_Yt_0_6), + .o_Yt_0_7(new_Yt_0_7), + .o_Yt_0_8(new_Yt_0_8), + .o_Yt_0_9(new_Yt_0_9), + .o_Yt_0_10(new_Yt_0_10), + .o_Yt_0_11(new_Yt_0_11), + .o_Yt_0_12(new_Yt_0_12), + .o_Yt_0_13(new_Yt_0_13), + .o_Yt_0_14(new_Yt_0_14), + .o_Yt_0_15(new_Yt_0_15), + .o_Yt_1_0(new_Yt_1_0), + .o_Yt_1_1(new_Yt_1_1), + .o_Yt_1_2(new_Yt_1_2), + .o_Yt_1_3(new_Yt_1_3), + .o_Yt_1_4(new_Yt_1_4), + .o_Yt_1_5(new_Yt_1_5), + .o_Yt_1_6(new_Yt_1_6), + .o_Yt_1_7(new_Yt_1_7), + .o_Yt_1_8(new_Yt_1_8), + .o_Yt_1_9(new_Yt_1_9), + .o_Yt_1_10(new_Yt_1_10), + .o_Yt_1_11(new_Yt_1_11), + .o_Yt_1_12(new_Yt_1_12), + .o_Yt_1_13(new_Yt_1_13), + .o_Yt_1_14(new_Yt_1_14), + .o_Yt_1_15(new_Yt_1_15), + .o_Yt_2_0(new_Yt_2_0), + .o_Yt_2_1(new_Yt_2_1), + .o_Yt_2_2(new_Yt_2_2), + .o_Yt_2_3(new_Yt_2_3), + .o_Yt_2_4(new_Yt_2_4), + .o_Yt_2_5(new_Yt_2_5), + .o_Yt_2_6(new_Yt_2_6), + .o_Yt_2_7(new_Yt_2_7), + .o_Yt_2_8(new_Yt_2_8), + .o_Yt_2_9(new_Yt_2_9), + .o_Yt_2_10(new_Yt_2_10), + .o_Yt_2_11(new_Yt_2_11), + .o_Yt_2_12(new_Yt_2_12), + .o_Yt_2_13(new_Yt_2_13), + .o_Yt_2_14(new_Yt_2_14), + .o_Yt_2_15(new_Yt_2_15), + .o_valid(stage3_valid), + .o_ready(stage3_ready) +); + +assign o_Yt_0_0 = new_Yt_0_0; +assign o_Yt_0_1 = new_Yt_0_1; +assign o_Yt_0_2 = new_Yt_0_2; +assign o_Yt_0_3 = new_Yt_0_3; +assign o_Yt_0_4 = new_Yt_0_4; +assign o_Yt_0_5 = new_Yt_0_5; +assign o_Yt_0_6 = new_Yt_0_6; +assign o_Yt_0_7 = new_Yt_0_7; +assign o_Yt_0_8 = new_Yt_0_8; +assign o_Yt_0_9 = new_Yt_0_9; +assign o_Yt_0_10 = new_Yt_0_10; +assign o_Yt_0_11 = new_Yt_0_11; +assign o_Yt_0_12 = new_Yt_0_12; +assign o_Yt_0_13 = new_Yt_0_13; +assign o_Yt_0_14 = new_Yt_0_14; +assign o_Yt_0_15 = new_Yt_0_15; +assign o_Yt_1_0 = new_Yt_1_0; +assign o_Yt_1_1 = new_Yt_1_1; +assign o_Yt_1_2 = new_Yt_1_2; +assign o_Yt_1_3 = new_Yt_1_3; +assign o_Yt_1_4 = new_Yt_1_4; +assign o_Yt_1_5 = new_Yt_1_5; +assign o_Yt_1_6 = new_Yt_1_6; +assign o_Yt_1_7 = new_Yt_1_7; +assign o_Yt_1_8 = new_Yt_1_8; +assign o_Yt_1_9 = new_Yt_1_9; +assign o_Yt_1_10 = new_Yt_1_10; +assign o_Yt_1_11 = new_Yt_1_11; +assign o_Yt_1_12 = new_Yt_1_12; +assign o_Yt_1_13 = new_Yt_1_13; +assign o_Yt_1_14 = new_Yt_1_14; +assign o_Yt_1_15 = new_Yt_1_15; +assign o_Yt_2_0 = new_Yt_2_0; +assign o_Yt_2_1 = new_Yt_2_1; +assign o_Yt_2_2 = new_Yt_2_2; +assign o_Yt_2_3 = new_Yt_2_3; +assign o_Yt_2_4 = new_Yt_2_4; +assign o_Yt_2_5 = new_Yt_2_5; +assign o_Yt_2_6 = new_Yt_2_6; +assign o_Yt_2_7 = new_Yt_2_7; +assign o_Yt_2_8 = new_Yt_2_8; +assign o_Yt_2_9 = new_Yt_2_9; +assign o_Yt_2_10 = new_Yt_2_10; +assign o_Yt_2_11 = new_Yt_2_11; +assign o_Yt_2_12 = new_Yt_2_12; +assign o_Yt_2_13 = new_Yt_2_13; +assign o_Yt_2_14 = new_Yt_2_14; +assign o_Yt_2_15 = new_Yt_2_15; + +// Stage 3 buffer and inter-connections +wire [17:0] pipelined_Yt_0; +wire [17:0] pipelined_Yt_1; +wire [17:0] pipelined_Yt_2; +wire [17:0] pipelined_Yt_3; +wire [17:0] pipelined_Yt_4; +wire [17:0] pipelined_Yt_5; +wire [17:0] pipelined_Yt_6; +wire [17:0] pipelined_Yt_7; +wire [17:0] pipelined_Yt_8; +wire [17:0] pipelined_Yt_9; +wire [17:0] pipelined_Yt_10; +wire [17:0] pipelined_Yt_11; +wire [17:0] pipelined_Yt_12; +wire [17:0] pipelined_Yt_13; +wire [17:0] pipelined_Yt_14; +wire [17:0] pipelined_Yt_15; +wire pipelined_Yt_valid; + +pipelined_input_18_3_16 pipelined_input_18_3_16_inst_Y ( + .clk(clk), + .reset(reset), + .enable(enable), + .load_input(stage3_valid), + .i_data_0_0(new_Yt_0_0), + .i_data_0_1(new_Yt_0_1), + .i_data_0_2(new_Yt_0_2), + .i_data_0_3(new_Yt_0_3), + .i_data_0_4(new_Yt_0_4), + .i_data_0_5(new_Yt_0_5), + .i_data_0_6(new_Yt_0_6), + .i_data_0_7(new_Yt_0_7), + .i_data_0_8(new_Yt_0_8), + .i_data_0_9(new_Yt_0_9), + .i_data_0_10(new_Yt_0_10), + .i_data_0_11(new_Yt_0_11), + .i_data_0_12(new_Yt_0_12), + .i_data_0_13(new_Yt_0_13), + .i_data_0_14(new_Yt_0_14), + .i_data_0_15(new_Yt_0_15), + .i_data_1_0(new_Yt_1_0), + .i_data_1_1(new_Yt_1_1), + .i_data_1_2(new_Yt_1_2), + .i_data_1_3(new_Yt_1_3), + .i_data_1_4(new_Yt_1_4), + .i_data_1_5(new_Yt_1_5), + .i_data_1_6(new_Yt_1_6), + .i_data_1_7(new_Yt_1_7), + .i_data_1_8(new_Yt_1_8), + .i_data_1_9(new_Yt_1_9), + .i_data_1_10(new_Yt_1_10), + .i_data_1_11(new_Yt_1_11), + .i_data_1_12(new_Yt_1_12), + .i_data_1_13(new_Yt_1_13), + .i_data_1_14(new_Yt_1_14), + .i_data_1_15(new_Yt_1_15), + .i_data_2_0(new_Yt_2_0), + .i_data_2_1(new_Yt_2_1), + .i_data_2_2(new_Yt_2_2), + .i_data_2_3(new_Yt_2_3), + .i_data_2_4(new_Yt_2_4), + .i_data_2_5(new_Yt_2_5), + .i_data_2_6(new_Yt_2_6), + .i_data_2_7(new_Yt_2_7), + .i_data_2_8(new_Yt_2_8), + .i_data_2_9(new_Yt_2_9), + .i_data_2_10(new_Yt_2_10), + .i_data_2_11(new_Yt_2_11), + .i_data_2_12(new_Yt_2_12), + .i_data_2_13(new_Yt_2_13), + .i_data_2_14(new_Yt_2_14), + .i_data_2_15(new_Yt_2_15), + .o_data_0(pipelined_Yt_0), + .o_data_1(pipelined_Yt_1), + .o_data_2(pipelined_Yt_2), + .o_data_3(pipelined_Yt_3), + .o_data_4(pipelined_Yt_4), + .o_data_5(pipelined_Yt_5), + .o_data_6(pipelined_Yt_6), + .o_data_7(pipelined_Yt_7), + .o_data_8(pipelined_Yt_8), + .o_data_9(pipelined_Yt_9), + .o_data_10(pipelined_Yt_10), + .o_data_11(pipelined_Yt_11), + .o_data_12(pipelined_Yt_12), + .o_data_13(pipelined_Yt_13), + .o_data_14(pipelined_Yt_14), + .o_data_15(pipelined_Yt_15), + .o_valid(pipelined_Yt_valid) +); + +stage3_X_Y_buffer_18_16_3_10_32_64 stage3_X_Y_buffer_18_16_3_10_32_64_inst_tyxhqonnhv ( + .clk(clk), + .reset(reset), + .i_X_valid(i_valid), + .i_Y_valid(pipelined_Yt_valid), + .feed_start(start_compute), + .i_X_data_0(i_X_data_0), + .i_Y_data_0(pipelined_Yt_0), + .o_data_0(i_data_0), + .i_X_data_1(i_X_data_1), + .i_Y_data_1(pipelined_Yt_1), + .o_data_1(i_data_1), + .i_X_data_2(i_X_data_2), + .i_Y_data_2(pipelined_Yt_2), + .o_data_2(i_data_2), + .i_X_data_3(i_X_data_3), + .i_Y_data_3(pipelined_Yt_3), + .o_data_3(i_data_3), + .i_X_data_4(i_X_data_4), + .i_Y_data_4(pipelined_Yt_4), + .o_data_4(i_data_4), + .i_X_data_5(i_X_data_5), + .i_Y_data_5(pipelined_Yt_5), + .o_data_5(i_data_5), + .i_X_data_6(i_X_data_6), + .i_Y_data_6(pipelined_Yt_6), + .o_data_6(i_data_6), + .i_X_data_7(i_X_data_7), + .i_Y_data_7(pipelined_Yt_7), + .o_data_7(i_data_7), + .i_X_data_8(i_X_data_8), + .i_Y_data_8(pipelined_Yt_8), + .o_data_8(i_data_8), + .i_X_data_9(i_X_data_9), + .i_Y_data_9(pipelined_Yt_9), + .o_data_9(i_data_9), + .i_X_data_10(i_X_data_10), + .i_Y_data_10(pipelined_Yt_10), + .o_data_10(i_data_10), + .i_X_data_11(i_X_data_11), + .i_Y_data_11(pipelined_Yt_11), + .o_data_11(i_data_11), + .i_X_data_12(i_X_data_12), + .i_Y_data_12(pipelined_Yt_12), + .o_data_12(i_data_12), + .i_X_data_13(i_X_data_13), + .i_Y_data_13(pipelined_Yt_13), + .o_data_13(i_data_13), + .i_X_data_14(i_X_data_14), + .i_Y_data_14(pipelined_Yt_14), + .o_data_14(i_data_14), + .i_X_data_15(i_X_data_15), + .i_Y_data_15(pipelined_Yt_15), + .o_data_15(i_data_15), + .o_valid(out_X_Y_buffer_valid), + .o_ready(o_ready) +); + +assign o_valid = stage3_valid; + +endmodule + +module spram ( + clk, + addr, + we, + data, + out +); + +parameter AWIDTH=10; +parameter NUM_WORDS=1024; +parameter DWIDTH=32; + +input clk; +input [(AWIDTH-1):0] addr; +input we; +input [(DWIDTH-1):0] data; +output reg [(DWIDTH-1):0] out; + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram[NUM_WORDS-1:0]; +always @ (posedge clk) begin + if (we) begin + ram[addr] <= data; + end + out <= ram[addr]; +end + +`else + +defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; +defparam u_single_port_ram.DATA_WIDTH = DWIDTH; +single_port_ram u_single_port_ram( + .addr(addr), + .we(we), + .data(data), + .out(out), + .clk(clk) +); + +`endif + +endmodule + +module dpram ( + clk, + addr1, + addr2, + we1, + we2, + data1, + data2, + out1, + out2 +); + +parameter AWIDTH=10; +parameter NUM_WORDS=1024; +parameter DWIDTH=32; + +input clk; +input [(AWIDTH-1):0] addr1; +input [(AWIDTH-1):0] addr2; +input we1; +input we2; +input [(DWIDTH-1):0] data1; +input [(DWIDTH-1):0] data2; +output reg [(DWIDTH-1):0] out1; +output reg [(DWIDTH-1):0] out2; + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram[NUM_WORDS-1:0]; +always @ (posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end + out1 <= ram[addr1]; +end + +always @ (posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end + out2 <= ram[addr2]; +end + +`else + +defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; +defparam u_dual_port_ram.DATA_WIDTH = DWIDTH; +dual_port_ram u_dual_port_ram( + .addr1(addr1), + .we1(we1), + .data1(data1), + .out1(out1), + .addr2(addr2), + .we2(we2), + .data2(data2), + .out2(out2), + .clk(clk) +); +`endif + +endmodule + + +module stage1_parameter_buffer_18_3_16_42_2688 ( + input clk, + input reset, + input [161:0] wdata, + input [7:0] wen, + output [17:0] Wixr_real_0_0, + output [17:0] Wixr_imag_0_0, + output [17:0] Wfxr_real_0_0, + output [17:0] Wfxr_imag_0_0, + output [17:0] Woxr_real_0_0, + output [17:0] Woxr_imag_0_0, + output [17:0] Wcxr_real_0_0, + output [17:0] Wcxr_imag_0_0, + output [17:0] Wixr_real_0_1, + output [17:0] Wixr_imag_0_1, + output [17:0] Wfxr_real_0_1, + output [17:0] Wfxr_imag_0_1, + output [17:0] Woxr_real_0_1, + output [17:0] Woxr_imag_0_1, + output [17:0] Wcxr_real_0_1, + output [17:0] Wcxr_imag_0_1, + output [17:0] Wixr_real_0_2, + output [17:0] Wixr_imag_0_2, + output [17:0] Wfxr_real_0_2, + output [17:0] Wfxr_imag_0_2, + output [17:0] Woxr_real_0_2, + output [17:0] Woxr_imag_0_2, + output [17:0] Wcxr_real_0_2, + output [17:0] Wcxr_imag_0_2, + output [17:0] Wixr_real_0_3, + output [17:0] Wixr_imag_0_3, + output [17:0] Wfxr_real_0_3, + output [17:0] Wfxr_imag_0_3, + output [17:0] Woxr_real_0_3, + output [17:0] Woxr_imag_0_3, + output [17:0] Wcxr_real_0_3, + output [17:0] Wcxr_imag_0_3, + output [17:0] Wixr_real_0_4, + output [17:0] Wixr_imag_0_4, + output [17:0] Wfxr_real_0_4, + output [17:0] Wfxr_imag_0_4, + output [17:0] Woxr_real_0_4, + output [17:0] Woxr_imag_0_4, + output [17:0] Wcxr_real_0_4, + output [17:0] Wcxr_imag_0_4, + output [17:0] Wixr_real_0_5, + output [17:0] Wixr_imag_0_5, + output [17:0] Wfxr_real_0_5, + output [17:0] Wfxr_imag_0_5, + output [17:0] Woxr_real_0_5, + output [17:0] Woxr_imag_0_5, + output [17:0] Wcxr_real_0_5, + output [17:0] Wcxr_imag_0_5, + output [17:0] Wixr_real_0_6, + output [17:0] Wixr_imag_0_6, + output [17:0] Wfxr_real_0_6, + output [17:0] Wfxr_imag_0_6, + output [17:0] Woxr_real_0_6, + output [17:0] Woxr_imag_0_6, + output [17:0] Wcxr_real_0_6, + output [17:0] Wcxr_imag_0_6, + output [17:0] Wixr_real_0_7, + output [17:0] Wixr_imag_0_7, + output [17:0] Wfxr_real_0_7, + output [17:0] Wfxr_imag_0_7, + output [17:0] Woxr_real_0_7, + output [17:0] Woxr_imag_0_7, + output [17:0] Wcxr_real_0_7, + output [17:0] Wcxr_imag_0_7, + output [17:0] Wixr_real_0_8, + output [17:0] Wixr_imag_0_8, + output [17:0] Wfxr_real_0_8, + output [17:0] Wfxr_imag_0_8, + output [17:0] Woxr_real_0_8, + output [17:0] Woxr_imag_0_8, + output [17:0] Wcxr_real_0_8, + output [17:0] Wcxr_imag_0_8, + output [17:0] Wixr_real_1_0, + output [17:0] Wixr_imag_1_0, + output [17:0] Wfxr_real_1_0, + output [17:0] Wfxr_imag_1_0, + output [17:0] Woxr_real_1_0, + output [17:0] Woxr_imag_1_0, + output [17:0] Wcxr_real_1_0, + output [17:0] Wcxr_imag_1_0, + output [17:0] Wixr_real_1_1, + output [17:0] Wixr_imag_1_1, + output [17:0] Wfxr_real_1_1, + output [17:0] Wfxr_imag_1_1, + output [17:0] Woxr_real_1_1, + output [17:0] Woxr_imag_1_1, + output [17:0] Wcxr_real_1_1, + output [17:0] Wcxr_imag_1_1, + output [17:0] Wixr_real_1_2, + output [17:0] Wixr_imag_1_2, + output [17:0] Wfxr_real_1_2, + output [17:0] Wfxr_imag_1_2, + output [17:0] Woxr_real_1_2, + output [17:0] Woxr_imag_1_2, + output [17:0] Wcxr_real_1_2, + output [17:0] Wcxr_imag_1_2, + output [17:0] Wixr_real_1_3, + output [17:0] Wixr_imag_1_3, + output [17:0] Wfxr_real_1_3, + output [17:0] Wfxr_imag_1_3, + output [17:0] Woxr_real_1_3, + output [17:0] Woxr_imag_1_3, + output [17:0] Wcxr_real_1_3, + output [17:0] Wcxr_imag_1_3, + output [17:0] Wixr_real_1_4, + output [17:0] Wixr_imag_1_4, + output [17:0] Wfxr_real_1_4, + output [17:0] Wfxr_imag_1_4, + output [17:0] Woxr_real_1_4, + output [17:0] Woxr_imag_1_4, + output [17:0] Wcxr_real_1_4, + output [17:0] Wcxr_imag_1_4, + output [17:0] Wixr_real_1_5, + output [17:0] Wixr_imag_1_5, + output [17:0] Wfxr_real_1_5, + output [17:0] Wfxr_imag_1_5, + output [17:0] Woxr_real_1_5, + output [17:0] Woxr_imag_1_5, + output [17:0] Wcxr_real_1_5, + output [17:0] Wcxr_imag_1_5, + output [17:0] Wixr_real_1_6, + output [17:0] Wixr_imag_1_6, + output [17:0] Wfxr_real_1_6, + output [17:0] Wfxr_imag_1_6, + output [17:0] Woxr_real_1_6, + output [17:0] Woxr_imag_1_6, + output [17:0] Wcxr_real_1_6, + output [17:0] Wcxr_imag_1_6, + output [17:0] Wixr_real_1_7, + output [17:0] Wixr_imag_1_7, + output [17:0] Wfxr_real_1_7, + output [17:0] Wfxr_imag_1_7, + output [17:0] Woxr_real_1_7, + output [17:0] Woxr_imag_1_7, + output [17:0] Wcxr_real_1_7, + output [17:0] Wcxr_imag_1_7, + output [17:0] Wixr_real_1_8, + output [17:0] Wixr_imag_1_8, + output [17:0] Wfxr_real_1_8, + output [17:0] Wfxr_imag_1_8, + output [17:0] Woxr_real_1_8, + output [17:0] Woxr_imag_1_8, + output [17:0] Wcxr_real_1_8, + output [17:0] Wcxr_imag_1_8, + output [17:0] Wixr_real_2_0, + output [17:0] Wixr_imag_2_0, + output [17:0] Wfxr_real_2_0, + output [17:0] Wfxr_imag_2_0, + output [17:0] Woxr_real_2_0, + output [17:0] Woxr_imag_2_0, + output [17:0] Wcxr_real_2_0, + output [17:0] Wcxr_imag_2_0, + output [17:0] Wixr_real_2_1, + output [17:0] Wixr_imag_2_1, + output [17:0] Wfxr_real_2_1, + output [17:0] Wfxr_imag_2_1, + output [17:0] Woxr_real_2_1, + output [17:0] Woxr_imag_2_1, + output [17:0] Wcxr_real_2_1, + output [17:0] Wcxr_imag_2_1, + output [17:0] Wixr_real_2_2, + output [17:0] Wixr_imag_2_2, + output [17:0] Wfxr_real_2_2, + output [17:0] Wfxr_imag_2_2, + output [17:0] Woxr_real_2_2, + output [17:0] Woxr_imag_2_2, + output [17:0] Wcxr_real_2_2, + output [17:0] Wcxr_imag_2_2, + output [17:0] Wixr_real_2_3, + output [17:0] Wixr_imag_2_3, + output [17:0] Wfxr_real_2_3, + output [17:0] Wfxr_imag_2_3, + output [17:0] Woxr_real_2_3, + output [17:0] Woxr_imag_2_3, + output [17:0] Wcxr_real_2_3, + output [17:0] Wcxr_imag_2_3, + output [17:0] Wixr_real_2_4, + output [17:0] Wixr_imag_2_4, + output [17:0] Wfxr_real_2_4, + output [17:0] Wfxr_imag_2_4, + output [17:0] Woxr_real_2_4, + output [17:0] Woxr_imag_2_4, + output [17:0] Wcxr_real_2_4, + output [17:0] Wcxr_imag_2_4, + output [17:0] Wixr_real_2_5, + output [17:0] Wixr_imag_2_5, + output [17:0] Wfxr_real_2_5, + output [17:0] Wfxr_imag_2_5, + output [17:0] Woxr_real_2_5, + output [17:0] Woxr_imag_2_5, + output [17:0] Wcxr_real_2_5, + output [17:0] Wcxr_imag_2_5, + output [17:0] Wixr_real_2_6, + output [17:0] Wixr_imag_2_6, + output [17:0] Wfxr_real_2_6, + output [17:0] Wfxr_imag_2_6, + output [17:0] Woxr_real_2_6, + output [17:0] Woxr_imag_2_6, + output [17:0] Wcxr_real_2_6, + output [17:0] Wcxr_imag_2_6, + output [17:0] Wixr_real_2_7, + output [17:0] Wixr_imag_2_7, + output [17:0] Wfxr_real_2_7, + output [17:0] Wfxr_imag_2_7, + output [17:0] Woxr_real_2_7, + output [17:0] Woxr_imag_2_7, + output [17:0] Wcxr_real_2_7, + output [17:0] Wcxr_imag_2_7, + output [17:0] Wixr_real_2_8, + output [17:0] Wixr_imag_2_8, + output [17:0] Wfxr_real_2_8, + output [17:0] Wfxr_imag_2_8, + output [17:0] Woxr_real_2_8, + output [17:0] Woxr_imag_2_8, + output [17:0] Wcxr_real_2_8, + output [17:0] Wcxr_imag_2_8, + input incr_index +); + +// A counter that counts how many sub blocks we have processed +wire [13:0] input_index_counter; +counter_41_1 counter_41_1_inst_jqbghzchkq ( + .clk(clk), + .reset(reset), + .ena(incr_index), + .count(input_index_counter) +); + +wire incr_row_index; +assign incr_row_index = (input_index_counter == 41); +wire counter_enable_row_index; +assign counter_enable_row_index = (incr_row_index & incr_index); + +// A counter that records which weight portion to use +wire [13:0] weight_row_index_counter; +counter_63_3 counter_63_3_inst_tqsfuicnfv ( + .clk(clk), + .reset(reset), + .ena(counter_enable_row_index), + .count(weight_row_index_counter) +); + +reg [13:0] weight_index; +always @ (*) begin + weight_index = weight_row_index_counter * 14'd42 + input_index_counter; +end + +// Input Gate +weight_buffer_18_9_42_3_2688 Wixr_real_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[0]), + .q_0_0(Wixr_real_0_0), + .q_0_1(Wixr_real_0_1), + .q_0_2(Wixr_real_0_2), + .q_0_3(Wixr_real_0_3), + .q_0_4(Wixr_real_0_4), + .q_0_5(Wixr_real_0_5), + .q_0_6(Wixr_real_0_6), + .q_0_7(Wixr_real_0_7), + .q_0_8(Wixr_real_0_8), + .q_1_0(Wixr_real_1_0), + .q_1_1(Wixr_real_1_1), + .q_1_2(Wixr_real_1_2), + .q_1_3(Wixr_real_1_3), + .q_1_4(Wixr_real_1_4), + .q_1_5(Wixr_real_1_5), + .q_1_6(Wixr_real_1_6), + .q_1_7(Wixr_real_1_7), + .q_1_8(Wixr_real_1_8), + .q_2_0(Wixr_real_2_0), + .q_2_1(Wixr_real_2_1), + .q_2_2(Wixr_real_2_2), + .q_2_3(Wixr_real_2_3), + .q_2_4(Wixr_real_2_4), + .q_2_5(Wixr_real_2_5), + .q_2_6(Wixr_real_2_6), + .q_2_7(Wixr_real_2_7), + .q_2_8(Wixr_real_2_8), + .index(weight_index) +); + +weight_buffer_18_9_42_3_2688 Wixr_imag_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[1]), + .q_0_0(Wixr_imag_0_0), + .q_0_1(Wixr_imag_0_1), + .q_0_2(Wixr_imag_0_2), + .q_0_3(Wixr_imag_0_3), + .q_0_4(Wixr_imag_0_4), + .q_0_5(Wixr_imag_0_5), + .q_0_6(Wixr_imag_0_6), + .q_0_7(Wixr_imag_0_7), + .q_0_8(Wixr_imag_0_8), + .q_1_0(Wixr_imag_1_0), + .q_1_1(Wixr_imag_1_1), + .q_1_2(Wixr_imag_1_2), + .q_1_3(Wixr_imag_1_3), + .q_1_4(Wixr_imag_1_4), + .q_1_5(Wixr_imag_1_5), + .q_1_6(Wixr_imag_1_6), + .q_1_7(Wixr_imag_1_7), + .q_1_8(Wixr_imag_1_8), + .q_2_0(Wixr_imag_2_0), + .q_2_1(Wixr_imag_2_1), + .q_2_2(Wixr_imag_2_2), + .q_2_3(Wixr_imag_2_3), + .q_2_4(Wixr_imag_2_4), + .q_2_5(Wixr_imag_2_5), + .q_2_6(Wixr_imag_2_6), + .q_2_7(Wixr_imag_2_7), + .q_2_8(Wixr_imag_2_8), + .index(weight_index) +); + +// Forget Gate +weight_buffer_18_9_42_3_2688 Wfxr_real_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[2]), + .q_0_0(Wfxr_real_0_0), + .q_0_1(Wfxr_real_0_1), + .q_0_2(Wfxr_real_0_2), + .q_0_3(Wfxr_real_0_3), + .q_0_4(Wfxr_real_0_4), + .q_0_5(Wfxr_real_0_5), + .q_0_6(Wfxr_real_0_6), + .q_0_7(Wfxr_real_0_7), + .q_0_8(Wfxr_real_0_8), + .q_1_0(Wfxr_real_1_0), + .q_1_1(Wfxr_real_1_1), + .q_1_2(Wfxr_real_1_2), + .q_1_3(Wfxr_real_1_3), + .q_1_4(Wfxr_real_1_4), + .q_1_5(Wfxr_real_1_5), + .q_1_6(Wfxr_real_1_6), + .q_1_7(Wfxr_real_1_7), + .q_1_8(Wfxr_real_1_8), + .q_2_0(Wfxr_real_2_0), + .q_2_1(Wfxr_real_2_1), + .q_2_2(Wfxr_real_2_2), + .q_2_3(Wfxr_real_2_3), + .q_2_4(Wfxr_real_2_4), + .q_2_5(Wfxr_real_2_5), + .q_2_6(Wfxr_real_2_6), + .q_2_7(Wfxr_real_2_7), + .q_2_8(Wfxr_real_2_8), + .index(weight_index) +); + +weight_buffer_18_9_42_3_2688 Wfxr_imag_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[7]), + .q_0_0(Wfxr_imag_0_0), + .q_0_1(Wfxr_imag_0_1), + .q_0_2(Wfxr_imag_0_2), + .q_0_3(Wfxr_imag_0_3), + .q_0_4(Wfxr_imag_0_4), + .q_0_5(Wfxr_imag_0_5), + .q_0_6(Wfxr_imag_0_6), + .q_0_7(Wfxr_imag_0_7), + .q_0_8(Wfxr_imag_0_8), + .q_1_0(Wfxr_imag_1_0), + .q_1_1(Wfxr_imag_1_1), + .q_1_2(Wfxr_imag_1_2), + .q_1_3(Wfxr_imag_1_3), + .q_1_4(Wfxr_imag_1_4), + .q_1_5(Wfxr_imag_1_5), + .q_1_6(Wfxr_imag_1_6), + .q_1_7(Wfxr_imag_1_7), + .q_1_8(Wfxr_imag_1_8), + .q_2_0(Wfxr_imag_2_0), + .q_2_1(Wfxr_imag_2_1), + .q_2_2(Wfxr_imag_2_2), + .q_2_3(Wfxr_imag_2_3), + .q_2_4(Wfxr_imag_2_4), + .q_2_5(Wfxr_imag_2_5), + .q_2_6(Wfxr_imag_2_6), + .q_2_7(Wfxr_imag_2_7), + .q_2_8(Wfxr_imag_2_8), + .index(weight_index) +); + +// Output Gate +weight_buffer_18_9_42_3_2688 Woxr_real_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[3]), + .q_0_0(Woxr_real_0_0), + .q_0_1(Woxr_real_0_1), + .q_0_2(Woxr_real_0_2), + .q_0_3(Woxr_real_0_3), + .q_0_4(Woxr_real_0_4), + .q_0_5(Woxr_real_0_5), + .q_0_6(Woxr_real_0_6), + .q_0_7(Woxr_real_0_7), + .q_0_8(Woxr_real_0_8), + .q_1_0(Woxr_real_1_0), + .q_1_1(Woxr_real_1_1), + .q_1_2(Woxr_real_1_2), + .q_1_3(Woxr_real_1_3), + .q_1_4(Woxr_real_1_4), + .q_1_5(Woxr_real_1_5), + .q_1_6(Woxr_real_1_6), + .q_1_7(Woxr_real_1_7), + .q_1_8(Woxr_real_1_8), + .q_2_0(Woxr_real_2_0), + .q_2_1(Woxr_real_2_1), + .q_2_2(Woxr_real_2_2), + .q_2_3(Woxr_real_2_3), + .q_2_4(Woxr_real_2_4), + .q_2_5(Woxr_real_2_5), + .q_2_6(Woxr_real_2_6), + .q_2_7(Woxr_real_2_7), + .q_2_8(Woxr_real_2_8), + .index(weight_index) +); + +weight_buffer_18_9_42_3_2688 Woxr_imag_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[4]), + .q_0_0(Woxr_imag_0_0), + .q_0_1(Woxr_imag_0_1), + .q_0_2(Woxr_imag_0_2), + .q_0_3(Woxr_imag_0_3), + .q_0_4(Woxr_imag_0_4), + .q_0_5(Woxr_imag_0_5), + .q_0_6(Woxr_imag_0_6), + .q_0_7(Woxr_imag_0_7), + .q_0_8(Woxr_imag_0_8), + .q_1_0(Woxr_imag_1_0), + .q_1_1(Woxr_imag_1_1), + .q_1_2(Woxr_imag_1_2), + .q_1_3(Woxr_imag_1_3), + .q_1_4(Woxr_imag_1_4), + .q_1_5(Woxr_imag_1_5), + .q_1_6(Woxr_imag_1_6), + .q_1_7(Woxr_imag_1_7), + .q_1_8(Woxr_imag_1_8), + .q_2_0(Woxr_imag_2_0), + .q_2_1(Woxr_imag_2_1), + .q_2_2(Woxr_imag_2_2), + .q_2_3(Woxr_imag_2_3), + .q_2_4(Woxr_imag_2_4), + .q_2_5(Woxr_imag_2_5), + .q_2_6(Woxr_imag_2_6), + .q_2_7(Woxr_imag_2_7), + .q_2_8(Woxr_imag_2_8), + .index(weight_index) +); + +// Output Activation Gate +weight_buffer_18_9_42_3_2688 Wcxr_real_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[5]), + .q_0_0(Wcxr_real_0_0), + .q_0_1(Wcxr_real_0_1), + .q_0_2(Wcxr_real_0_2), + .q_0_3(Wcxr_real_0_3), + .q_0_4(Wcxr_real_0_4), + .q_0_5(Wcxr_real_0_5), + .q_0_6(Wcxr_real_0_6), + .q_0_7(Wcxr_real_0_7), + .q_0_8(Wcxr_real_0_8), + .q_1_0(Wcxr_real_1_0), + .q_1_1(Wcxr_real_1_1), + .q_1_2(Wcxr_real_1_2), + .q_1_3(Wcxr_real_1_3), + .q_1_4(Wcxr_real_1_4), + .q_1_5(Wcxr_real_1_5), + .q_1_6(Wcxr_real_1_6), + .q_1_7(Wcxr_real_1_7), + .q_1_8(Wcxr_real_1_8), + .q_2_0(Wcxr_real_2_0), + .q_2_1(Wcxr_real_2_1), + .q_2_2(Wcxr_real_2_2), + .q_2_3(Wcxr_real_2_3), + .q_2_4(Wcxr_real_2_4), + .q_2_5(Wcxr_real_2_5), + .q_2_6(Wcxr_real_2_6), + .q_2_7(Wcxr_real_2_7), + .q_2_8(Wcxr_real_2_8), + .index(weight_index) +); + +weight_buffer_18_9_42_3_2688 Wcxr_imag_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[6]), + .q_0_0(Wcxr_imag_0_0), + .q_0_1(Wcxr_imag_0_1), + .q_0_2(Wcxr_imag_0_2), + .q_0_3(Wcxr_imag_0_3), + .q_0_4(Wcxr_imag_0_4), + .q_0_5(Wcxr_imag_0_5), + .q_0_6(Wcxr_imag_0_6), + .q_0_7(Wcxr_imag_0_7), + .q_0_8(Wcxr_imag_0_8), + .q_1_0(Wcxr_imag_1_0), + .q_1_1(Wcxr_imag_1_1), + .q_1_2(Wcxr_imag_1_2), + .q_1_3(Wcxr_imag_1_3), + .q_1_4(Wcxr_imag_1_4), + .q_1_5(Wcxr_imag_1_5), + .q_1_6(Wcxr_imag_1_6), + .q_1_7(Wcxr_imag_1_7), + .q_1_8(Wcxr_imag_1_8), + .q_2_0(Wcxr_imag_2_0), + .q_2_1(Wcxr_imag_2_1), + .q_2_2(Wcxr_imag_2_2), + .q_2_3(Wcxr_imag_2_3), + .q_2_4(Wcxr_imag_2_4), + .q_2_5(Wcxr_imag_2_5), + .q_2_6(Wcxr_imag_2_6), + .q_2_7(Wcxr_imag_2_7), + .q_2_8(Wcxr_imag_2_8), + .index(weight_index) +); + +endmodule + + +module counter_41_1 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd1) <= 41) begin + count <= count + 14'd1; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module counter_63_3 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd3) <= 63) begin + count <= count + 14'd3; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module weight_buffer_18_9_42_3_2688 ( + input clk, + input rst, + input [161:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_2_0, + output [17:0] q_2_1, + output [17:0] q_2_2, + output [17:0] q_2_3, + output [17:0] q_2_4, + output [17:0] q_2_5, + output [17:0] q_2_6, + output [17:0] q_2_7, + output [17:0] q_2_8, + input [10:0] index +); + +wire [161:0] packed_result_0; +reg [10:0] addrs_0; +reg [10:0] addrs_base_0; +wire [161:0] packed_result_1; +reg [10:0] addrs_1; +reg [10:0] addrs_base_1; +wire [161:0] packed_result_2; +reg [10:0] addrs_2; +reg [10:0] addrs_base_2; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 42; + addrs_base_2 <= 84; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + addrs_2 <= index + addrs_base_2; + end +end + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_2 ( + .we(wen), + .addr(addrs_2), + .data(wdata), + .out(packed_result_2), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_2_0 = packed_result_2[17:0]; +assign q_2_1 = packed_result_2[35:18]; +assign q_2_2 = packed_result_2[53:36]; +assign q_2_3 = packed_result_2[71:54]; +assign q_2_4 = packed_result_2[89:72]; +assign q_2_5 = packed_result_2[107:90]; +assign q_2_6 = packed_result_2[125:108]; +assign q_2_7 = packed_result_2[143:126]; +assign q_2_8 = packed_result_2[161:144]; + +endmodule + +module shift_register_group_18_16_3 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input reset +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +endmodule + +module shift_register_unit_18_3 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +reg [17:0] shift_registers_1; +reg [17:0] shift_registers_2; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + shift_registers_1 <= 18'd0; + shift_registers_2 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + end +end + +assign out = shift_registers_2; + +endmodule + +module shift_register_unit_1_3 ( + input clk, + input reset, + input enable, + input [0:0] in, + output [0:0] out +); + +reg [0:0] shift_registers_0; +reg [0:0] shift_registers_1; +reg [0:0] shift_registers_2; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 1'd0; + shift_registers_1 <= 1'd0; + shift_registers_2 <= 1'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + end +end + +assign out = shift_registers_2; + +endmodule + +module C_LSTM_stage_1_18_10_160_512_3_16_1 ( + input clk, + input reset, + input enable, + input i_ready, + input [17:0] i_Xt_Yt_1_0, + input [17:0] i_Xt_Yt_1_1, + input [17:0] i_Xt_Yt_1_2, + input [17:0] i_Xt_Yt_1_3, + input [17:0] i_Xt_Yt_1_4, + input [17:0] i_Xt_Yt_1_5, + input [17:0] i_Xt_Yt_1_6, + input [17:0] i_Xt_Yt_1_7, + input [17:0] i_Xt_Yt_1_8, + input [17:0] i_Xt_Yt_1_9, + input [17:0] i_Xt_Yt_1_10, + input [17:0] i_Xt_Yt_1_11, + input [17:0] i_Xt_Yt_1_12, + input [17:0] i_Xt_Yt_1_13, + input [17:0] i_Xt_Yt_1_14, + input [17:0] i_Xt_Yt_1_15, + input [17:0] i_Wixr_real_0_0, + input [17:0] i_Wixr_imag_0_0, + input [17:0] i_Wfxr_real_0_0, + input [17:0] i_Wfxr_imag_0_0, + input [17:0] i_Woxr_real_0_0, + input [17:0] i_Woxr_imag_0_0, + input [17:0] i_Wcxr_real_0_0, + input [17:0] i_Wcxr_imag_0_0, + input [17:0] i_Wixr_real_0_1, + input [17:0] i_Wixr_imag_0_1, + input [17:0] i_Wfxr_real_0_1, + input [17:0] i_Wfxr_imag_0_1, + input [17:0] i_Woxr_real_0_1, + input [17:0] i_Woxr_imag_0_1, + input [17:0] i_Wcxr_real_0_1, + input [17:0] i_Wcxr_imag_0_1, + input [17:0] i_Wixr_real_0_2, + input [17:0] i_Wixr_imag_0_2, + input [17:0] i_Wfxr_real_0_2, + input [17:0] i_Wfxr_imag_0_2, + input [17:0] i_Woxr_real_0_2, + input [17:0] i_Woxr_imag_0_2, + input [17:0] i_Wcxr_real_0_2, + input [17:0] i_Wcxr_imag_0_2, + input [17:0] i_Wixr_real_0_3, + input [17:0] i_Wixr_imag_0_3, + input [17:0] i_Wfxr_real_0_3, + input [17:0] i_Wfxr_imag_0_3, + input [17:0] i_Woxr_real_0_3, + input [17:0] i_Woxr_imag_0_3, + input [17:0] i_Wcxr_real_0_3, + input [17:0] i_Wcxr_imag_0_3, + input [17:0] i_Wixr_real_0_4, + input [17:0] i_Wixr_imag_0_4, + input [17:0] i_Wfxr_real_0_4, + input [17:0] i_Wfxr_imag_0_4, + input [17:0] i_Woxr_real_0_4, + input [17:0] i_Woxr_imag_0_4, + input [17:0] i_Wcxr_real_0_4, + input [17:0] i_Wcxr_imag_0_4, + input [17:0] i_Wixr_real_0_5, + input [17:0] i_Wixr_imag_0_5, + input [17:0] i_Wfxr_real_0_5, + input [17:0] i_Wfxr_imag_0_5, + input [17:0] i_Woxr_real_0_5, + input [17:0] i_Woxr_imag_0_5, + input [17:0] i_Wcxr_real_0_5, + input [17:0] i_Wcxr_imag_0_5, + input [17:0] i_Wixr_real_0_6, + input [17:0] i_Wixr_imag_0_6, + input [17:0] i_Wfxr_real_0_6, + input [17:0] i_Wfxr_imag_0_6, + input [17:0] i_Woxr_real_0_6, + input [17:0] i_Woxr_imag_0_6, + input [17:0] i_Wcxr_real_0_6, + input [17:0] i_Wcxr_imag_0_6, + input [17:0] i_Wixr_real_0_7, + input [17:0] i_Wixr_imag_0_7, + input [17:0] i_Wfxr_real_0_7, + input [17:0] i_Wfxr_imag_0_7, + input [17:0] i_Woxr_real_0_7, + input [17:0] i_Woxr_imag_0_7, + input [17:0] i_Wcxr_real_0_7, + input [17:0] i_Wcxr_imag_0_7, + input [17:0] i_Wixr_real_0_8, + input [17:0] i_Wixr_imag_0_8, + input [17:0] i_Wfxr_real_0_8, + input [17:0] i_Wfxr_imag_0_8, + input [17:0] i_Woxr_real_0_8, + input [17:0] i_Woxr_imag_0_8, + input [17:0] i_Wcxr_real_0_8, + input [17:0] i_Wcxr_imag_0_8, + input [17:0] i_Wixr_real_1_0, + input [17:0] i_Wixr_imag_1_0, + input [17:0] i_Wfxr_real_1_0, + input [17:0] i_Wfxr_imag_1_0, + input [17:0] i_Woxr_real_1_0, + input [17:0] i_Woxr_imag_1_0, + input [17:0] i_Wcxr_real_1_0, + input [17:0] i_Wcxr_imag_1_0, + input [17:0] i_Wixr_real_1_1, + input [17:0] i_Wixr_imag_1_1, + input [17:0] i_Wfxr_real_1_1, + input [17:0] i_Wfxr_imag_1_1, + input [17:0] i_Woxr_real_1_1, + input [17:0] i_Woxr_imag_1_1, + input [17:0] i_Wcxr_real_1_1, + input [17:0] i_Wcxr_imag_1_1, + input [17:0] i_Wixr_real_1_2, + input [17:0] i_Wixr_imag_1_2, + input [17:0] i_Wfxr_real_1_2, + input [17:0] i_Wfxr_imag_1_2, + input [17:0] i_Woxr_real_1_2, + input [17:0] i_Woxr_imag_1_2, + input [17:0] i_Wcxr_real_1_2, + input [17:0] i_Wcxr_imag_1_2, + input [17:0] i_Wixr_real_1_3, + input [17:0] i_Wixr_imag_1_3, + input [17:0] i_Wfxr_real_1_3, + input [17:0] i_Wfxr_imag_1_3, + input [17:0] i_Woxr_real_1_3, + input [17:0] i_Woxr_imag_1_3, + input [17:0] i_Wcxr_real_1_3, + input [17:0] i_Wcxr_imag_1_3, + input [17:0] i_Wixr_real_1_4, + input [17:0] i_Wixr_imag_1_4, + input [17:0] i_Wfxr_real_1_4, + input [17:0] i_Wfxr_imag_1_4, + input [17:0] i_Woxr_real_1_4, + input [17:0] i_Woxr_imag_1_4, + input [17:0] i_Wcxr_real_1_4, + input [17:0] i_Wcxr_imag_1_4, + input [17:0] i_Wixr_real_1_5, + input [17:0] i_Wixr_imag_1_5, + input [17:0] i_Wfxr_real_1_5, + input [17:0] i_Wfxr_imag_1_5, + input [17:0] i_Woxr_real_1_5, + input [17:0] i_Woxr_imag_1_5, + input [17:0] i_Wcxr_real_1_5, + input [17:0] i_Wcxr_imag_1_5, + input [17:0] i_Wixr_real_1_6, + input [17:0] i_Wixr_imag_1_6, + input [17:0] i_Wfxr_real_1_6, + input [17:0] i_Wfxr_imag_1_6, + input [17:0] i_Woxr_real_1_6, + input [17:0] i_Woxr_imag_1_6, + input [17:0] i_Wcxr_real_1_6, + input [17:0] i_Wcxr_imag_1_6, + input [17:0] i_Wixr_real_1_7, + input [17:0] i_Wixr_imag_1_7, + input [17:0] i_Wfxr_real_1_7, + input [17:0] i_Wfxr_imag_1_7, + input [17:0] i_Woxr_real_1_7, + input [17:0] i_Woxr_imag_1_7, + input [17:0] i_Wcxr_real_1_7, + input [17:0] i_Wcxr_imag_1_7, + input [17:0] i_Wixr_real_1_8, + input [17:0] i_Wixr_imag_1_8, + input [17:0] i_Wfxr_real_1_8, + input [17:0] i_Wfxr_imag_1_8, + input [17:0] i_Woxr_real_1_8, + input [17:0] i_Woxr_imag_1_8, + input [17:0] i_Wcxr_real_1_8, + input [17:0] i_Wcxr_imag_1_8, + input [17:0] i_Wixr_real_2_0, + input [17:0] i_Wixr_imag_2_0, + input [17:0] i_Wfxr_real_2_0, + input [17:0] i_Wfxr_imag_2_0, + input [17:0] i_Woxr_real_2_0, + input [17:0] i_Woxr_imag_2_0, + input [17:0] i_Wcxr_real_2_0, + input [17:0] i_Wcxr_imag_2_0, + input [17:0] i_Wixr_real_2_1, + input [17:0] i_Wixr_imag_2_1, + input [17:0] i_Wfxr_real_2_1, + input [17:0] i_Wfxr_imag_2_1, + input [17:0] i_Woxr_real_2_1, + input [17:0] i_Woxr_imag_2_1, + input [17:0] i_Wcxr_real_2_1, + input [17:0] i_Wcxr_imag_2_1, + input [17:0] i_Wixr_real_2_2, + input [17:0] i_Wixr_imag_2_2, + input [17:0] i_Wfxr_real_2_2, + input [17:0] i_Wfxr_imag_2_2, + input [17:0] i_Woxr_real_2_2, + input [17:0] i_Woxr_imag_2_2, + input [17:0] i_Wcxr_real_2_2, + input [17:0] i_Wcxr_imag_2_2, + input [17:0] i_Wixr_real_2_3, + input [17:0] i_Wixr_imag_2_3, + input [17:0] i_Wfxr_real_2_3, + input [17:0] i_Wfxr_imag_2_3, + input [17:0] i_Woxr_real_2_3, + input [17:0] i_Woxr_imag_2_3, + input [17:0] i_Wcxr_real_2_3, + input [17:0] i_Wcxr_imag_2_3, + input [17:0] i_Wixr_real_2_4, + input [17:0] i_Wixr_imag_2_4, + input [17:0] i_Wfxr_real_2_4, + input [17:0] i_Wfxr_imag_2_4, + input [17:0] i_Woxr_real_2_4, + input [17:0] i_Woxr_imag_2_4, + input [17:0] i_Wcxr_real_2_4, + input [17:0] i_Wcxr_imag_2_4, + input [17:0] i_Wixr_real_2_5, + input [17:0] i_Wixr_imag_2_5, + input [17:0] i_Wfxr_real_2_5, + input [17:0] i_Wfxr_imag_2_5, + input [17:0] i_Woxr_real_2_5, + input [17:0] i_Woxr_imag_2_5, + input [17:0] i_Wcxr_real_2_5, + input [17:0] i_Wcxr_imag_2_5, + input [17:0] i_Wixr_real_2_6, + input [17:0] i_Wixr_imag_2_6, + input [17:0] i_Wfxr_real_2_6, + input [17:0] i_Wfxr_imag_2_6, + input [17:0] i_Woxr_real_2_6, + input [17:0] i_Woxr_imag_2_6, + input [17:0] i_Wcxr_real_2_6, + input [17:0] i_Wcxr_imag_2_6, + input [17:0] i_Wixr_real_2_7, + input [17:0] i_Wixr_imag_2_7, + input [17:0] i_Wfxr_real_2_7, + input [17:0] i_Wfxr_imag_2_7, + input [17:0] i_Woxr_real_2_7, + input [17:0] i_Woxr_imag_2_7, + input [17:0] i_Wcxr_real_2_7, + input [17:0] i_Wcxr_imag_2_7, + input [17:0] i_Wixr_real_2_8, + input [17:0] i_Wixr_imag_2_8, + input [17:0] i_Wfxr_real_2_8, + input [17:0] i_Wfxr_imag_2_8, + input [17:0] i_Woxr_real_2_8, + input [17:0] i_Woxr_imag_2_8, + input [17:0] i_Wcxr_real_2_8, + input [17:0] i_Wcxr_imag_2_8, + output o_valid, + output o_ready, + output [17:0] o_WixrXtYt_1_0_0, + output [17:0] o_WfxrXtYt_1_0_0, + output [17:0] o_WoxrXtYt_1_0_0, + output [17:0] o_WcxrXtYt_1_0_0, + output [17:0] o_WixrXtYt_1_0_1, + output [17:0] o_WfxrXtYt_1_0_1, + output [17:0] o_WoxrXtYt_1_0_1, + output [17:0] o_WcxrXtYt_1_0_1, + output [17:0] o_WixrXtYt_1_0_2, + output [17:0] o_WfxrXtYt_1_0_2, + output [17:0] o_WoxrXtYt_1_0_2, + output [17:0] o_WcxrXtYt_1_0_2, + output [17:0] o_WixrXtYt_1_0_3, + output [17:0] o_WfxrXtYt_1_0_3, + output [17:0] o_WoxrXtYt_1_0_3, + output [17:0] o_WcxrXtYt_1_0_3, + output [17:0] o_WixrXtYt_1_0_4, + output [17:0] o_WfxrXtYt_1_0_4, + output [17:0] o_WoxrXtYt_1_0_4, + output [17:0] o_WcxrXtYt_1_0_4, + output [17:0] o_WixrXtYt_1_0_5, + output [17:0] o_WfxrXtYt_1_0_5, + output [17:0] o_WoxrXtYt_1_0_5, + output [17:0] o_WcxrXtYt_1_0_5, + output [17:0] o_WixrXtYt_1_0_6, + output [17:0] o_WfxrXtYt_1_0_6, + output [17:0] o_WoxrXtYt_1_0_6, + output [17:0] o_WcxrXtYt_1_0_6, + output [17:0] o_WixrXtYt_1_0_7, + output [17:0] o_WfxrXtYt_1_0_7, + output [17:0] o_WoxrXtYt_1_0_7, + output [17:0] o_WcxrXtYt_1_0_7, + output [17:0] o_WixrXtYt_1_0_8, + output [17:0] o_WfxrXtYt_1_0_8, + output [17:0] o_WoxrXtYt_1_0_8, + output [17:0] o_WcxrXtYt_1_0_8, + output [17:0] o_WixrXtYt_1_0_9, + output [17:0] o_WfxrXtYt_1_0_9, + output [17:0] o_WoxrXtYt_1_0_9, + output [17:0] o_WcxrXtYt_1_0_9, + output [17:0] o_WixrXtYt_1_0_10, + output [17:0] o_WfxrXtYt_1_0_10, + output [17:0] o_WoxrXtYt_1_0_10, + output [17:0] o_WcxrXtYt_1_0_10, + output [17:0] o_WixrXtYt_1_0_11, + output [17:0] o_WfxrXtYt_1_0_11, + output [17:0] o_WoxrXtYt_1_0_11, + output [17:0] o_WcxrXtYt_1_0_11, + output [17:0] o_WixrXtYt_1_0_12, + output [17:0] o_WfxrXtYt_1_0_12, + output [17:0] o_WoxrXtYt_1_0_12, + output [17:0] o_WcxrXtYt_1_0_12, + output [17:0] o_WixrXtYt_1_0_13, + output [17:0] o_WfxrXtYt_1_0_13, + output [17:0] o_WoxrXtYt_1_0_13, + output [17:0] o_WcxrXtYt_1_0_13, + output [17:0] o_WixrXtYt_1_0_14, + output [17:0] o_WfxrXtYt_1_0_14, + output [17:0] o_WoxrXtYt_1_0_14, + output [17:0] o_WcxrXtYt_1_0_14, + output [17:0] o_WixrXtYt_1_0_15, + output [17:0] o_WfxrXtYt_1_0_15, + output [17:0] o_WoxrXtYt_1_0_15, + output [17:0] o_WcxrXtYt_1_0_15, + output [17:0] o_WixrXtYt_1_1_0, + output [17:0] o_WfxrXtYt_1_1_0, + output [17:0] o_WoxrXtYt_1_1_0, + output [17:0] o_WcxrXtYt_1_1_0, + output [17:0] o_WixrXtYt_1_1_1, + output [17:0] o_WfxrXtYt_1_1_1, + output [17:0] o_WoxrXtYt_1_1_1, + output [17:0] o_WcxrXtYt_1_1_1, + output [17:0] o_WixrXtYt_1_1_2, + output [17:0] o_WfxrXtYt_1_1_2, + output [17:0] o_WoxrXtYt_1_1_2, + output [17:0] o_WcxrXtYt_1_1_2, + output [17:0] o_WixrXtYt_1_1_3, + output [17:0] o_WfxrXtYt_1_1_3, + output [17:0] o_WoxrXtYt_1_1_3, + output [17:0] o_WcxrXtYt_1_1_3, + output [17:0] o_WixrXtYt_1_1_4, + output [17:0] o_WfxrXtYt_1_1_4, + output [17:0] o_WoxrXtYt_1_1_4, + output [17:0] o_WcxrXtYt_1_1_4, + output [17:0] o_WixrXtYt_1_1_5, + output [17:0] o_WfxrXtYt_1_1_5, + output [17:0] o_WoxrXtYt_1_1_5, + output [17:0] o_WcxrXtYt_1_1_5, + output [17:0] o_WixrXtYt_1_1_6, + output [17:0] o_WfxrXtYt_1_1_6, + output [17:0] o_WoxrXtYt_1_1_6, + output [17:0] o_WcxrXtYt_1_1_6, + output [17:0] o_WixrXtYt_1_1_7, + output [17:0] o_WfxrXtYt_1_1_7, + output [17:0] o_WoxrXtYt_1_1_7, + output [17:0] o_WcxrXtYt_1_1_7, + output [17:0] o_WixrXtYt_1_1_8, + output [17:0] o_WfxrXtYt_1_1_8, + output [17:0] o_WoxrXtYt_1_1_8, + output [17:0] o_WcxrXtYt_1_1_8, + output [17:0] o_WixrXtYt_1_1_9, + output [17:0] o_WfxrXtYt_1_1_9, + output [17:0] o_WoxrXtYt_1_1_9, + output [17:0] o_WcxrXtYt_1_1_9, + output [17:0] o_WixrXtYt_1_1_10, + output [17:0] o_WfxrXtYt_1_1_10, + output [17:0] o_WoxrXtYt_1_1_10, + output [17:0] o_WcxrXtYt_1_1_10, + output [17:0] o_WixrXtYt_1_1_11, + output [17:0] o_WfxrXtYt_1_1_11, + output [17:0] o_WoxrXtYt_1_1_11, + output [17:0] o_WcxrXtYt_1_1_11, + output [17:0] o_WixrXtYt_1_1_12, + output [17:0] o_WfxrXtYt_1_1_12, + output [17:0] o_WoxrXtYt_1_1_12, + output [17:0] o_WcxrXtYt_1_1_12, + output [17:0] o_WixrXtYt_1_1_13, + output [17:0] o_WfxrXtYt_1_1_13, + output [17:0] o_WoxrXtYt_1_1_13, + output [17:0] o_WcxrXtYt_1_1_13, + output [17:0] o_WixrXtYt_1_1_14, + output [17:0] o_WfxrXtYt_1_1_14, + output [17:0] o_WoxrXtYt_1_1_14, + output [17:0] o_WcxrXtYt_1_1_14, + output [17:0] o_WixrXtYt_1_1_15, + output [17:0] o_WfxrXtYt_1_1_15, + output [17:0] o_WoxrXtYt_1_1_15, + output [17:0] o_WcxrXtYt_1_1_15, + output [17:0] o_WixrXtYt_1_2_0, + output [17:0] o_WfxrXtYt_1_2_0, + output [17:0] o_WoxrXtYt_1_2_0, + output [17:0] o_WcxrXtYt_1_2_0, + output [17:0] o_WixrXtYt_1_2_1, + output [17:0] o_WfxrXtYt_1_2_1, + output [17:0] o_WoxrXtYt_1_2_1, + output [17:0] o_WcxrXtYt_1_2_1, + output [17:0] o_WixrXtYt_1_2_2, + output [17:0] o_WfxrXtYt_1_2_2, + output [17:0] o_WoxrXtYt_1_2_2, + output [17:0] o_WcxrXtYt_1_2_2, + output [17:0] o_WixrXtYt_1_2_3, + output [17:0] o_WfxrXtYt_1_2_3, + output [17:0] o_WoxrXtYt_1_2_3, + output [17:0] o_WcxrXtYt_1_2_3, + output [17:0] o_WixrXtYt_1_2_4, + output [17:0] o_WfxrXtYt_1_2_4, + output [17:0] o_WoxrXtYt_1_2_4, + output [17:0] o_WcxrXtYt_1_2_4, + output [17:0] o_WixrXtYt_1_2_5, + output [17:0] o_WfxrXtYt_1_2_5, + output [17:0] o_WoxrXtYt_1_2_5, + output [17:0] o_WcxrXtYt_1_2_5, + output [17:0] o_WixrXtYt_1_2_6, + output [17:0] o_WfxrXtYt_1_2_6, + output [17:0] o_WoxrXtYt_1_2_6, + output [17:0] o_WcxrXtYt_1_2_6, + output [17:0] o_WixrXtYt_1_2_7, + output [17:0] o_WfxrXtYt_1_2_7, + output [17:0] o_WoxrXtYt_1_2_7, + output [17:0] o_WcxrXtYt_1_2_7, + output [17:0] o_WixrXtYt_1_2_8, + output [17:0] o_WfxrXtYt_1_2_8, + output [17:0] o_WoxrXtYt_1_2_8, + output [17:0] o_WcxrXtYt_1_2_8, + output [17:0] o_WixrXtYt_1_2_9, + output [17:0] o_WfxrXtYt_1_2_9, + output [17:0] o_WoxrXtYt_1_2_9, + output [17:0] o_WcxrXtYt_1_2_9, + output [17:0] o_WixrXtYt_1_2_10, + output [17:0] o_WfxrXtYt_1_2_10, + output [17:0] o_WoxrXtYt_1_2_10, + output [17:0] o_WcxrXtYt_1_2_10, + output [17:0] o_WixrXtYt_1_2_11, + output [17:0] o_WfxrXtYt_1_2_11, + output [17:0] o_WoxrXtYt_1_2_11, + output [17:0] o_WcxrXtYt_1_2_11, + output [17:0] o_WixrXtYt_1_2_12, + output [17:0] o_WfxrXtYt_1_2_12, + output [17:0] o_WoxrXtYt_1_2_12, + output [17:0] o_WcxrXtYt_1_2_12, + output [17:0] o_WixrXtYt_1_2_13, + output [17:0] o_WfxrXtYt_1_2_13, + output [17:0] o_WoxrXtYt_1_2_13, + output [17:0] o_WcxrXtYt_1_2_13, + output [17:0] o_WixrXtYt_1_2_14, + output [17:0] o_WfxrXtYt_1_2_14, + output [17:0] o_WoxrXtYt_1_2_14, + output [17:0] o_WcxrXtYt_1_2_14, + output [17:0] o_WixrXtYt_1_2_15, + output [17:0] o_WfxrXtYt_1_2_15, + output [17:0] o_WoxrXtYt_1_2_15, + output [17:0] o_WcxrXtYt_1_2_15, + input i_valid +); + +wire input_gate_mult_valid, forget_gate_mult_valid, output_gate_mult_valid, output_act_mult_valid; +wire input_gate_mult_ready, forget_gate_mult_ready, output_gate_mult_ready, output_act_mult_ready; + +// Input Gate Multiplication +matrix_times_two_vectors_18_10_3_672_16_1 input_gate_mult ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_ready(i_ready), + .i_valid(i_valid), + .i_Xt_Yt_1_0(i_Xt_Yt_1_0), + .i_Xt_Yt_1_1(i_Xt_Yt_1_1), + .i_Xt_Yt_1_2(i_Xt_Yt_1_2), + .i_Xt_Yt_1_3(i_Xt_Yt_1_3), + .i_Xt_Yt_1_4(i_Xt_Yt_1_4), + .i_Xt_Yt_1_5(i_Xt_Yt_1_5), + .i_Xt_Yt_1_6(i_Xt_Yt_1_6), + .i_Xt_Yt_1_7(i_Xt_Yt_1_7), + .i_Xt_Yt_1_8(i_Xt_Yt_1_8), + .i_Xt_Yt_1_9(i_Xt_Yt_1_9), + .i_Xt_Yt_1_10(i_Xt_Yt_1_10), + .i_Xt_Yt_1_11(i_Xt_Yt_1_11), + .i_Xt_Yt_1_12(i_Xt_Yt_1_12), + .i_Xt_Yt_1_13(i_Xt_Yt_1_13), + .i_Xt_Yt_1_14(i_Xt_Yt_1_14), + .i_Xt_Yt_1_15(i_Xt_Yt_1_15), + .i_Wxr_real_0_0(i_Wixr_real_0_0), + .i_Wxr_imag_0_0(i_Wixr_imag_0_0), + .i_Wxr_real_0_1(i_Wixr_real_0_1), + .i_Wxr_imag_0_1(i_Wixr_imag_0_1), + .i_Wxr_real_0_2(i_Wixr_real_0_2), + .i_Wxr_imag_0_2(i_Wixr_imag_0_2), + .i_Wxr_real_0_3(i_Wixr_real_0_3), + .i_Wxr_imag_0_3(i_Wixr_imag_0_3), + .i_Wxr_real_0_4(i_Wixr_real_0_4), + .i_Wxr_imag_0_4(i_Wixr_imag_0_4), + .i_Wxr_real_0_5(i_Wixr_real_0_5), + .i_Wxr_imag_0_5(i_Wixr_imag_0_5), + .i_Wxr_real_0_6(i_Wixr_real_0_6), + .i_Wxr_imag_0_6(i_Wixr_imag_0_6), + .i_Wxr_real_0_7(i_Wixr_real_0_7), + .i_Wxr_imag_0_7(i_Wixr_imag_0_7), + .i_Wxr_real_0_8(i_Wixr_real_0_8), + .i_Wxr_imag_0_8(i_Wixr_imag_0_8), + .i_Wxr_real_1_0(i_Wixr_real_1_0), + .i_Wxr_imag_1_0(i_Wixr_imag_1_0), + .i_Wxr_real_1_1(i_Wixr_real_1_1), + .i_Wxr_imag_1_1(i_Wixr_imag_1_1), + .i_Wxr_real_1_2(i_Wixr_real_1_2), + .i_Wxr_imag_1_2(i_Wixr_imag_1_2), + .i_Wxr_real_1_3(i_Wixr_real_1_3), + .i_Wxr_imag_1_3(i_Wixr_imag_1_3), + .i_Wxr_real_1_4(i_Wixr_real_1_4), + .i_Wxr_imag_1_4(i_Wixr_imag_1_4), + .i_Wxr_real_1_5(i_Wixr_real_1_5), + .i_Wxr_imag_1_5(i_Wixr_imag_1_5), + .i_Wxr_real_1_6(i_Wixr_real_1_6), + .i_Wxr_imag_1_6(i_Wixr_imag_1_6), + .i_Wxr_real_1_7(i_Wixr_real_1_7), + .i_Wxr_imag_1_7(i_Wixr_imag_1_7), + .i_Wxr_real_1_8(i_Wixr_real_1_8), + .i_Wxr_imag_1_8(i_Wixr_imag_1_8), + .i_Wxr_real_2_0(i_Wixr_real_2_0), + .i_Wxr_imag_2_0(i_Wixr_imag_2_0), + .i_Wxr_real_2_1(i_Wixr_real_2_1), + .i_Wxr_imag_2_1(i_Wixr_imag_2_1), + .i_Wxr_real_2_2(i_Wixr_real_2_2), + .i_Wxr_imag_2_2(i_Wixr_imag_2_2), + .i_Wxr_real_2_3(i_Wixr_real_2_3), + .i_Wxr_imag_2_3(i_Wixr_imag_2_3), + .i_Wxr_real_2_4(i_Wixr_real_2_4), + .i_Wxr_imag_2_4(i_Wixr_imag_2_4), + .i_Wxr_real_2_5(i_Wixr_real_2_5), + .i_Wxr_imag_2_5(i_Wixr_imag_2_5), + .i_Wxr_real_2_6(i_Wixr_real_2_6), + .i_Wxr_imag_2_6(i_Wixr_imag_2_6), + .i_Wxr_real_2_7(i_Wixr_real_2_7), + .i_Wxr_imag_2_7(i_Wixr_imag_2_7), + .i_Wxr_real_2_8(i_Wixr_real_2_8), + .i_Wxr_imag_2_8(i_Wixr_imag_2_8), + .o_W_times_X_Y_0_0(o_WixrXtYt_1_0_0), + .o_W_times_X_Y_0_1(o_WixrXtYt_1_0_1), + .o_W_times_X_Y_0_2(o_WixrXtYt_1_0_2), + .o_W_times_X_Y_0_3(o_WixrXtYt_1_0_3), + .o_W_times_X_Y_0_4(o_WixrXtYt_1_0_4), + .o_W_times_X_Y_0_5(o_WixrXtYt_1_0_5), + .o_W_times_X_Y_0_6(o_WixrXtYt_1_0_6), + .o_W_times_X_Y_0_7(o_WixrXtYt_1_0_7), + .o_W_times_X_Y_0_8(o_WixrXtYt_1_0_8), + .o_W_times_X_Y_0_9(o_WixrXtYt_1_0_9), + .o_W_times_X_Y_0_10(o_WixrXtYt_1_0_10), + .o_W_times_X_Y_0_11(o_WixrXtYt_1_0_11), + .o_W_times_X_Y_0_12(o_WixrXtYt_1_0_12), + .o_W_times_X_Y_0_13(o_WixrXtYt_1_0_13), + .o_W_times_X_Y_0_14(o_WixrXtYt_1_0_14), + .o_W_times_X_Y_0_15(o_WixrXtYt_1_0_15), + .o_W_times_X_Y_1_0(o_WixrXtYt_1_1_0), + .o_W_times_X_Y_1_1(o_WixrXtYt_1_1_1), + .o_W_times_X_Y_1_2(o_WixrXtYt_1_1_2), + .o_W_times_X_Y_1_3(o_WixrXtYt_1_1_3), + .o_W_times_X_Y_1_4(o_WixrXtYt_1_1_4), + .o_W_times_X_Y_1_5(o_WixrXtYt_1_1_5), + .o_W_times_X_Y_1_6(o_WixrXtYt_1_1_6), + .o_W_times_X_Y_1_7(o_WixrXtYt_1_1_7), + .o_W_times_X_Y_1_8(o_WixrXtYt_1_1_8), + .o_W_times_X_Y_1_9(o_WixrXtYt_1_1_9), + .o_W_times_X_Y_1_10(o_WixrXtYt_1_1_10), + .o_W_times_X_Y_1_11(o_WixrXtYt_1_1_11), + .o_W_times_X_Y_1_12(o_WixrXtYt_1_1_12), + .o_W_times_X_Y_1_13(o_WixrXtYt_1_1_13), + .o_W_times_X_Y_1_14(o_WixrXtYt_1_1_14), + .o_W_times_X_Y_1_15(o_WixrXtYt_1_1_15), + .o_W_times_X_Y_2_0(o_WixrXtYt_1_2_0), + .o_W_times_X_Y_2_1(o_WixrXtYt_1_2_1), + .o_W_times_X_Y_2_2(o_WixrXtYt_1_2_2), + .o_W_times_X_Y_2_3(o_WixrXtYt_1_2_3), + .o_W_times_X_Y_2_4(o_WixrXtYt_1_2_4), + .o_W_times_X_Y_2_5(o_WixrXtYt_1_2_5), + .o_W_times_X_Y_2_6(o_WixrXtYt_1_2_6), + .o_W_times_X_Y_2_7(o_WixrXtYt_1_2_7), + .o_W_times_X_Y_2_8(o_WixrXtYt_1_2_8), + .o_W_times_X_Y_2_9(o_WixrXtYt_1_2_9), + .o_W_times_X_Y_2_10(o_WixrXtYt_1_2_10), + .o_W_times_X_Y_2_11(o_WixrXtYt_1_2_11), + .o_W_times_X_Y_2_12(o_WixrXtYt_1_2_12), + .o_W_times_X_Y_2_13(o_WixrXtYt_1_2_13), + .o_W_times_X_Y_2_14(o_WixrXtYt_1_2_14), + .o_W_times_X_Y_2_15(o_WixrXtYt_1_2_15), + .o_valid(input_gate_mult_valid), + .o_ready(input_gate_mult_ready) +); + +// Forget Gate Multiplication +matrix_times_two_vectors_18_10_3_672_16_1 forget_gate_mult ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_ready(i_ready), + .i_valid(i_valid), + .i_Xt_Yt_1_0(i_Xt_Yt_1_0), + .i_Xt_Yt_1_1(i_Xt_Yt_1_1), + .i_Xt_Yt_1_2(i_Xt_Yt_1_2), + .i_Xt_Yt_1_3(i_Xt_Yt_1_3), + .i_Xt_Yt_1_4(i_Xt_Yt_1_4), + .i_Xt_Yt_1_5(i_Xt_Yt_1_5), + .i_Xt_Yt_1_6(i_Xt_Yt_1_6), + .i_Xt_Yt_1_7(i_Xt_Yt_1_7), + .i_Xt_Yt_1_8(i_Xt_Yt_1_8), + .i_Xt_Yt_1_9(i_Xt_Yt_1_9), + .i_Xt_Yt_1_10(i_Xt_Yt_1_10), + .i_Xt_Yt_1_11(i_Xt_Yt_1_11), + .i_Xt_Yt_1_12(i_Xt_Yt_1_12), + .i_Xt_Yt_1_13(i_Xt_Yt_1_13), + .i_Xt_Yt_1_14(i_Xt_Yt_1_14), + .i_Xt_Yt_1_15(i_Xt_Yt_1_15), + .i_Wxr_real_0_0(i_Wfxr_real_0_0), + .i_Wxr_imag_0_0(i_Wfxr_imag_0_0), + .i_Wxr_real_0_1(i_Wfxr_real_0_1), + .i_Wxr_imag_0_1(i_Wfxr_imag_0_1), + .i_Wxr_real_0_2(i_Wfxr_real_0_2), + .i_Wxr_imag_0_2(i_Wfxr_imag_0_2), + .i_Wxr_real_0_3(i_Wfxr_real_0_3), + .i_Wxr_imag_0_3(i_Wfxr_imag_0_3), + .i_Wxr_real_0_4(i_Wfxr_real_0_4), + .i_Wxr_imag_0_4(i_Wfxr_imag_0_4), + .i_Wxr_real_0_5(i_Wfxr_real_0_5), + .i_Wxr_imag_0_5(i_Wfxr_imag_0_5), + .i_Wxr_real_0_6(i_Wfxr_real_0_6), + .i_Wxr_imag_0_6(i_Wfxr_imag_0_6), + .i_Wxr_real_0_7(i_Wfxr_real_0_7), + .i_Wxr_imag_0_7(i_Wfxr_imag_0_7), + .i_Wxr_real_0_8(i_Wfxr_real_0_8), + .i_Wxr_imag_0_8(i_Wfxr_imag_0_8), + .i_Wxr_real_1_0(i_Wfxr_real_1_0), + .i_Wxr_imag_1_0(i_Wfxr_imag_1_0), + .i_Wxr_real_1_1(i_Wfxr_real_1_1), + .i_Wxr_imag_1_1(i_Wfxr_imag_1_1), + .i_Wxr_real_1_2(i_Wfxr_real_1_2), + .i_Wxr_imag_1_2(i_Wfxr_imag_1_2), + .i_Wxr_real_1_3(i_Wfxr_real_1_3), + .i_Wxr_imag_1_3(i_Wfxr_imag_1_3), + .i_Wxr_real_1_4(i_Wfxr_real_1_4), + .i_Wxr_imag_1_4(i_Wfxr_imag_1_4), + .i_Wxr_real_1_5(i_Wfxr_real_1_5), + .i_Wxr_imag_1_5(i_Wfxr_imag_1_5), + .i_Wxr_real_1_6(i_Wfxr_real_1_6), + .i_Wxr_imag_1_6(i_Wfxr_imag_1_6), + .i_Wxr_real_1_7(i_Wfxr_real_1_7), + .i_Wxr_imag_1_7(i_Wfxr_imag_1_7), + .i_Wxr_real_1_8(i_Wfxr_real_1_8), + .i_Wxr_imag_1_8(i_Wfxr_imag_1_8), + .i_Wxr_real_2_0(i_Wfxr_real_2_0), + .i_Wxr_imag_2_0(i_Wfxr_imag_2_0), + .i_Wxr_real_2_1(i_Wfxr_real_2_1), + .i_Wxr_imag_2_1(i_Wfxr_imag_2_1), + .i_Wxr_real_2_2(i_Wfxr_real_2_2), + .i_Wxr_imag_2_2(i_Wfxr_imag_2_2), + .i_Wxr_real_2_3(i_Wfxr_real_2_3), + .i_Wxr_imag_2_3(i_Wfxr_imag_2_3), + .i_Wxr_real_2_4(i_Wfxr_real_2_4), + .i_Wxr_imag_2_4(i_Wfxr_imag_2_4), + .i_Wxr_real_2_5(i_Wfxr_real_2_5), + .i_Wxr_imag_2_5(i_Wfxr_imag_2_5), + .i_Wxr_real_2_6(i_Wfxr_real_2_6), + .i_Wxr_imag_2_6(i_Wfxr_imag_2_6), + .i_Wxr_real_2_7(i_Wfxr_real_2_7), + .i_Wxr_imag_2_7(i_Wfxr_imag_2_7), + .i_Wxr_real_2_8(i_Wfxr_real_2_8), + .i_Wxr_imag_2_8(i_Wfxr_imag_2_8), + .o_W_times_X_Y_0_0(o_WfxrXtYt_1_0_0), + .o_W_times_X_Y_0_1(o_WfxrXtYt_1_0_1), + .o_W_times_X_Y_0_2(o_WfxrXtYt_1_0_2), + .o_W_times_X_Y_0_3(o_WfxrXtYt_1_0_3), + .o_W_times_X_Y_0_4(o_WfxrXtYt_1_0_4), + .o_W_times_X_Y_0_5(o_WfxrXtYt_1_0_5), + .o_W_times_X_Y_0_6(o_WfxrXtYt_1_0_6), + .o_W_times_X_Y_0_7(o_WfxrXtYt_1_0_7), + .o_W_times_X_Y_0_8(o_WfxrXtYt_1_0_8), + .o_W_times_X_Y_0_9(o_WfxrXtYt_1_0_9), + .o_W_times_X_Y_0_10(o_WfxrXtYt_1_0_10), + .o_W_times_X_Y_0_11(o_WfxrXtYt_1_0_11), + .o_W_times_X_Y_0_12(o_WfxrXtYt_1_0_12), + .o_W_times_X_Y_0_13(o_WfxrXtYt_1_0_13), + .o_W_times_X_Y_0_14(o_WfxrXtYt_1_0_14), + .o_W_times_X_Y_0_15(o_WfxrXtYt_1_0_15), + .o_W_times_X_Y_1_0(o_WfxrXtYt_1_1_0), + .o_W_times_X_Y_1_1(o_WfxrXtYt_1_1_1), + .o_W_times_X_Y_1_2(o_WfxrXtYt_1_1_2), + .o_W_times_X_Y_1_3(o_WfxrXtYt_1_1_3), + .o_W_times_X_Y_1_4(o_WfxrXtYt_1_1_4), + .o_W_times_X_Y_1_5(o_WfxrXtYt_1_1_5), + .o_W_times_X_Y_1_6(o_WfxrXtYt_1_1_6), + .o_W_times_X_Y_1_7(o_WfxrXtYt_1_1_7), + .o_W_times_X_Y_1_8(o_WfxrXtYt_1_1_8), + .o_W_times_X_Y_1_9(o_WfxrXtYt_1_1_9), + .o_W_times_X_Y_1_10(o_WfxrXtYt_1_1_10), + .o_W_times_X_Y_1_11(o_WfxrXtYt_1_1_11), + .o_W_times_X_Y_1_12(o_WfxrXtYt_1_1_12), + .o_W_times_X_Y_1_13(o_WfxrXtYt_1_1_13), + .o_W_times_X_Y_1_14(o_WfxrXtYt_1_1_14), + .o_W_times_X_Y_1_15(o_WfxrXtYt_1_1_15), + .o_W_times_X_Y_2_0(o_WfxrXtYt_1_2_0), + .o_W_times_X_Y_2_1(o_WfxrXtYt_1_2_1), + .o_W_times_X_Y_2_2(o_WfxrXtYt_1_2_2), + .o_W_times_X_Y_2_3(o_WfxrXtYt_1_2_3), + .o_W_times_X_Y_2_4(o_WfxrXtYt_1_2_4), + .o_W_times_X_Y_2_5(o_WfxrXtYt_1_2_5), + .o_W_times_X_Y_2_6(o_WfxrXtYt_1_2_6), + .o_W_times_X_Y_2_7(o_WfxrXtYt_1_2_7), + .o_W_times_X_Y_2_8(o_WfxrXtYt_1_2_8), + .o_W_times_X_Y_2_9(o_WfxrXtYt_1_2_9), + .o_W_times_X_Y_2_10(o_WfxrXtYt_1_2_10), + .o_W_times_X_Y_2_11(o_WfxrXtYt_1_2_11), + .o_W_times_X_Y_2_12(o_WfxrXtYt_1_2_12), + .o_W_times_X_Y_2_13(o_WfxrXtYt_1_2_13), + .o_W_times_X_Y_2_14(o_WfxrXtYt_1_2_14), + .o_W_times_X_Y_2_15(o_WfxrXtYt_1_2_15), + .o_valid(forget_gate_mult_valid), + .o_ready(forget_gate_mult_ready) +); + +// Output Gate Multiplication +matrix_times_two_vectors_18_10_3_672_16_1 output_gate_mult ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_ready(i_ready), + .i_valid(i_valid), + .i_Xt_Yt_1_0(i_Xt_Yt_1_0), + .i_Xt_Yt_1_1(i_Xt_Yt_1_1), + .i_Xt_Yt_1_2(i_Xt_Yt_1_2), + .i_Xt_Yt_1_3(i_Xt_Yt_1_3), + .i_Xt_Yt_1_4(i_Xt_Yt_1_4), + .i_Xt_Yt_1_5(i_Xt_Yt_1_5), + .i_Xt_Yt_1_6(i_Xt_Yt_1_6), + .i_Xt_Yt_1_7(i_Xt_Yt_1_7), + .i_Xt_Yt_1_8(i_Xt_Yt_1_8), + .i_Xt_Yt_1_9(i_Xt_Yt_1_9), + .i_Xt_Yt_1_10(i_Xt_Yt_1_10), + .i_Xt_Yt_1_11(i_Xt_Yt_1_11), + .i_Xt_Yt_1_12(i_Xt_Yt_1_12), + .i_Xt_Yt_1_13(i_Xt_Yt_1_13), + .i_Xt_Yt_1_14(i_Xt_Yt_1_14), + .i_Xt_Yt_1_15(i_Xt_Yt_1_15), + .i_Wxr_real_0_0(i_Woxr_real_0_0), + .i_Wxr_imag_0_0(i_Woxr_imag_0_0), + .i_Wxr_real_0_1(i_Woxr_real_0_1), + .i_Wxr_imag_0_1(i_Woxr_imag_0_1), + .i_Wxr_real_0_2(i_Woxr_real_0_2), + .i_Wxr_imag_0_2(i_Woxr_imag_0_2), + .i_Wxr_real_0_3(i_Woxr_real_0_3), + .i_Wxr_imag_0_3(i_Woxr_imag_0_3), + .i_Wxr_real_0_4(i_Woxr_real_0_4), + .i_Wxr_imag_0_4(i_Woxr_imag_0_4), + .i_Wxr_real_0_5(i_Woxr_real_0_5), + .i_Wxr_imag_0_5(i_Woxr_imag_0_5), + .i_Wxr_real_0_6(i_Woxr_real_0_6), + .i_Wxr_imag_0_6(i_Woxr_imag_0_6), + .i_Wxr_real_0_7(i_Woxr_real_0_7), + .i_Wxr_imag_0_7(i_Woxr_imag_0_7), + .i_Wxr_real_0_8(i_Woxr_real_0_8), + .i_Wxr_imag_0_8(i_Woxr_imag_0_8), + .i_Wxr_real_1_0(i_Woxr_real_1_0), + .i_Wxr_imag_1_0(i_Woxr_imag_1_0), + .i_Wxr_real_1_1(i_Woxr_real_1_1), + .i_Wxr_imag_1_1(i_Woxr_imag_1_1), + .i_Wxr_real_1_2(i_Woxr_real_1_2), + .i_Wxr_imag_1_2(i_Woxr_imag_1_2), + .i_Wxr_real_1_3(i_Woxr_real_1_3), + .i_Wxr_imag_1_3(i_Woxr_imag_1_3), + .i_Wxr_real_1_4(i_Woxr_real_1_4), + .i_Wxr_imag_1_4(i_Woxr_imag_1_4), + .i_Wxr_real_1_5(i_Woxr_real_1_5), + .i_Wxr_imag_1_5(i_Woxr_imag_1_5), + .i_Wxr_real_1_6(i_Woxr_real_1_6), + .i_Wxr_imag_1_6(i_Woxr_imag_1_6), + .i_Wxr_real_1_7(i_Woxr_real_1_7), + .i_Wxr_imag_1_7(i_Woxr_imag_1_7), + .i_Wxr_real_1_8(i_Woxr_real_1_8), + .i_Wxr_imag_1_8(i_Woxr_imag_1_8), + .i_Wxr_real_2_0(i_Woxr_real_2_0), + .i_Wxr_imag_2_0(i_Woxr_imag_2_0), + .i_Wxr_real_2_1(i_Woxr_real_2_1), + .i_Wxr_imag_2_1(i_Woxr_imag_2_1), + .i_Wxr_real_2_2(i_Woxr_real_2_2), + .i_Wxr_imag_2_2(i_Woxr_imag_2_2), + .i_Wxr_real_2_3(i_Woxr_real_2_3), + .i_Wxr_imag_2_3(i_Woxr_imag_2_3), + .i_Wxr_real_2_4(i_Woxr_real_2_4), + .i_Wxr_imag_2_4(i_Woxr_imag_2_4), + .i_Wxr_real_2_5(i_Woxr_real_2_5), + .i_Wxr_imag_2_5(i_Woxr_imag_2_5), + .i_Wxr_real_2_6(i_Woxr_real_2_6), + .i_Wxr_imag_2_6(i_Woxr_imag_2_6), + .i_Wxr_real_2_7(i_Woxr_real_2_7), + .i_Wxr_imag_2_7(i_Woxr_imag_2_7), + .i_Wxr_real_2_8(i_Woxr_real_2_8), + .i_Wxr_imag_2_8(i_Woxr_imag_2_8), + .o_W_times_X_Y_0_0(o_WoxrXtYt_1_0_0), + .o_W_times_X_Y_0_1(o_WoxrXtYt_1_0_1), + .o_W_times_X_Y_0_2(o_WoxrXtYt_1_0_2), + .o_W_times_X_Y_0_3(o_WoxrXtYt_1_0_3), + .o_W_times_X_Y_0_4(o_WoxrXtYt_1_0_4), + .o_W_times_X_Y_0_5(o_WoxrXtYt_1_0_5), + .o_W_times_X_Y_0_6(o_WoxrXtYt_1_0_6), + .o_W_times_X_Y_0_7(o_WoxrXtYt_1_0_7), + .o_W_times_X_Y_0_8(o_WoxrXtYt_1_0_8), + .o_W_times_X_Y_0_9(o_WoxrXtYt_1_0_9), + .o_W_times_X_Y_0_10(o_WoxrXtYt_1_0_10), + .o_W_times_X_Y_0_11(o_WoxrXtYt_1_0_11), + .o_W_times_X_Y_0_12(o_WoxrXtYt_1_0_12), + .o_W_times_X_Y_0_13(o_WoxrXtYt_1_0_13), + .o_W_times_X_Y_0_14(o_WoxrXtYt_1_0_14), + .o_W_times_X_Y_0_15(o_WoxrXtYt_1_0_15), + .o_W_times_X_Y_1_0(o_WoxrXtYt_1_1_0), + .o_W_times_X_Y_1_1(o_WoxrXtYt_1_1_1), + .o_W_times_X_Y_1_2(o_WoxrXtYt_1_1_2), + .o_W_times_X_Y_1_3(o_WoxrXtYt_1_1_3), + .o_W_times_X_Y_1_4(o_WoxrXtYt_1_1_4), + .o_W_times_X_Y_1_5(o_WoxrXtYt_1_1_5), + .o_W_times_X_Y_1_6(o_WoxrXtYt_1_1_6), + .o_W_times_X_Y_1_7(o_WoxrXtYt_1_1_7), + .o_W_times_X_Y_1_8(o_WoxrXtYt_1_1_8), + .o_W_times_X_Y_1_9(o_WoxrXtYt_1_1_9), + .o_W_times_X_Y_1_10(o_WoxrXtYt_1_1_10), + .o_W_times_X_Y_1_11(o_WoxrXtYt_1_1_11), + .o_W_times_X_Y_1_12(o_WoxrXtYt_1_1_12), + .o_W_times_X_Y_1_13(o_WoxrXtYt_1_1_13), + .o_W_times_X_Y_1_14(o_WoxrXtYt_1_1_14), + .o_W_times_X_Y_1_15(o_WoxrXtYt_1_1_15), + .o_W_times_X_Y_2_0(o_WoxrXtYt_1_2_0), + .o_W_times_X_Y_2_1(o_WoxrXtYt_1_2_1), + .o_W_times_X_Y_2_2(o_WoxrXtYt_1_2_2), + .o_W_times_X_Y_2_3(o_WoxrXtYt_1_2_3), + .o_W_times_X_Y_2_4(o_WoxrXtYt_1_2_4), + .o_W_times_X_Y_2_5(o_WoxrXtYt_1_2_5), + .o_W_times_X_Y_2_6(o_WoxrXtYt_1_2_6), + .o_W_times_X_Y_2_7(o_WoxrXtYt_1_2_7), + .o_W_times_X_Y_2_8(o_WoxrXtYt_1_2_8), + .o_W_times_X_Y_2_9(o_WoxrXtYt_1_2_9), + .o_W_times_X_Y_2_10(o_WoxrXtYt_1_2_10), + .o_W_times_X_Y_2_11(o_WoxrXtYt_1_2_11), + .o_W_times_X_Y_2_12(o_WoxrXtYt_1_2_12), + .o_W_times_X_Y_2_13(o_WoxrXtYt_1_2_13), + .o_W_times_X_Y_2_14(o_WoxrXtYt_1_2_14), + .o_W_times_X_Y_2_15(o_WoxrXtYt_1_2_15), + .o_valid(output_gate_mult_valid), + .o_ready(output_gate_mult_ready) +); + +// Output Activation Multiplication +matrix_times_two_vectors_18_10_3_672_16_1 output_act_gate_mult ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_ready(i_ready), + .i_valid(i_valid), + .i_Xt_Yt_1_0(i_Xt_Yt_1_0), + .i_Xt_Yt_1_1(i_Xt_Yt_1_1), + .i_Xt_Yt_1_2(i_Xt_Yt_1_2), + .i_Xt_Yt_1_3(i_Xt_Yt_1_3), + .i_Xt_Yt_1_4(i_Xt_Yt_1_4), + .i_Xt_Yt_1_5(i_Xt_Yt_1_5), + .i_Xt_Yt_1_6(i_Xt_Yt_1_6), + .i_Xt_Yt_1_7(i_Xt_Yt_1_7), + .i_Xt_Yt_1_8(i_Xt_Yt_1_8), + .i_Xt_Yt_1_9(i_Xt_Yt_1_9), + .i_Xt_Yt_1_10(i_Xt_Yt_1_10), + .i_Xt_Yt_1_11(i_Xt_Yt_1_11), + .i_Xt_Yt_1_12(i_Xt_Yt_1_12), + .i_Xt_Yt_1_13(i_Xt_Yt_1_13), + .i_Xt_Yt_1_14(i_Xt_Yt_1_14), + .i_Xt_Yt_1_15(i_Xt_Yt_1_15), + .i_Wxr_real_0_0(i_Wcxr_real_0_0), + .i_Wxr_imag_0_0(i_Wcxr_imag_0_0), + .i_Wxr_real_0_1(i_Wcxr_real_0_1), + .i_Wxr_imag_0_1(i_Wcxr_imag_0_1), + .i_Wxr_real_0_2(i_Wcxr_real_0_2), + .i_Wxr_imag_0_2(i_Wcxr_imag_0_2), + .i_Wxr_real_0_3(i_Wcxr_real_0_3), + .i_Wxr_imag_0_3(i_Wcxr_imag_0_3), + .i_Wxr_real_0_4(i_Wcxr_real_0_4), + .i_Wxr_imag_0_4(i_Wcxr_imag_0_4), + .i_Wxr_real_0_5(i_Wcxr_real_0_5), + .i_Wxr_imag_0_5(i_Wcxr_imag_0_5), + .i_Wxr_real_0_6(i_Wcxr_real_0_6), + .i_Wxr_imag_0_6(i_Wcxr_imag_0_6), + .i_Wxr_real_0_7(i_Wcxr_real_0_7), + .i_Wxr_imag_0_7(i_Wcxr_imag_0_7), + .i_Wxr_real_0_8(i_Wcxr_real_0_8), + .i_Wxr_imag_0_8(i_Wcxr_imag_0_8), + .i_Wxr_real_1_0(i_Wcxr_real_1_0), + .i_Wxr_imag_1_0(i_Wcxr_imag_1_0), + .i_Wxr_real_1_1(i_Wcxr_real_1_1), + .i_Wxr_imag_1_1(i_Wcxr_imag_1_1), + .i_Wxr_real_1_2(i_Wcxr_real_1_2), + .i_Wxr_imag_1_2(i_Wcxr_imag_1_2), + .i_Wxr_real_1_3(i_Wcxr_real_1_3), + .i_Wxr_imag_1_3(i_Wcxr_imag_1_3), + .i_Wxr_real_1_4(i_Wcxr_real_1_4), + .i_Wxr_imag_1_4(i_Wcxr_imag_1_4), + .i_Wxr_real_1_5(i_Wcxr_real_1_5), + .i_Wxr_imag_1_5(i_Wcxr_imag_1_5), + .i_Wxr_real_1_6(i_Wcxr_real_1_6), + .i_Wxr_imag_1_6(i_Wcxr_imag_1_6), + .i_Wxr_real_1_7(i_Wcxr_real_1_7), + .i_Wxr_imag_1_7(i_Wcxr_imag_1_7), + .i_Wxr_real_1_8(i_Wcxr_real_1_8), + .i_Wxr_imag_1_8(i_Wcxr_imag_1_8), + .i_Wxr_real_2_0(i_Wcxr_real_2_0), + .i_Wxr_imag_2_0(i_Wcxr_imag_2_0), + .i_Wxr_real_2_1(i_Wcxr_real_2_1), + .i_Wxr_imag_2_1(i_Wcxr_imag_2_1), + .i_Wxr_real_2_2(i_Wcxr_real_2_2), + .i_Wxr_imag_2_2(i_Wcxr_imag_2_2), + .i_Wxr_real_2_3(i_Wcxr_real_2_3), + .i_Wxr_imag_2_3(i_Wcxr_imag_2_3), + .i_Wxr_real_2_4(i_Wcxr_real_2_4), + .i_Wxr_imag_2_4(i_Wcxr_imag_2_4), + .i_Wxr_real_2_5(i_Wcxr_real_2_5), + .i_Wxr_imag_2_5(i_Wcxr_imag_2_5), + .i_Wxr_real_2_6(i_Wcxr_real_2_6), + .i_Wxr_imag_2_6(i_Wcxr_imag_2_6), + .i_Wxr_real_2_7(i_Wcxr_real_2_7), + .i_Wxr_imag_2_7(i_Wcxr_imag_2_7), + .i_Wxr_real_2_8(i_Wcxr_real_2_8), + .i_Wxr_imag_2_8(i_Wcxr_imag_2_8), + .o_W_times_X_Y_0_0(o_WcxrXtYt_1_0_0), + .o_W_times_X_Y_0_1(o_WcxrXtYt_1_0_1), + .o_W_times_X_Y_0_2(o_WcxrXtYt_1_0_2), + .o_W_times_X_Y_0_3(o_WcxrXtYt_1_0_3), + .o_W_times_X_Y_0_4(o_WcxrXtYt_1_0_4), + .o_W_times_X_Y_0_5(o_WcxrXtYt_1_0_5), + .o_W_times_X_Y_0_6(o_WcxrXtYt_1_0_6), + .o_W_times_X_Y_0_7(o_WcxrXtYt_1_0_7), + .o_W_times_X_Y_0_8(o_WcxrXtYt_1_0_8), + .o_W_times_X_Y_0_9(o_WcxrXtYt_1_0_9), + .o_W_times_X_Y_0_10(o_WcxrXtYt_1_0_10), + .o_W_times_X_Y_0_11(o_WcxrXtYt_1_0_11), + .o_W_times_X_Y_0_12(o_WcxrXtYt_1_0_12), + .o_W_times_X_Y_0_13(o_WcxrXtYt_1_0_13), + .o_W_times_X_Y_0_14(o_WcxrXtYt_1_0_14), + .o_W_times_X_Y_0_15(o_WcxrXtYt_1_0_15), + .o_W_times_X_Y_1_0(o_WcxrXtYt_1_1_0), + .o_W_times_X_Y_1_1(o_WcxrXtYt_1_1_1), + .o_W_times_X_Y_1_2(o_WcxrXtYt_1_1_2), + .o_W_times_X_Y_1_3(o_WcxrXtYt_1_1_3), + .o_W_times_X_Y_1_4(o_WcxrXtYt_1_1_4), + .o_W_times_X_Y_1_5(o_WcxrXtYt_1_1_5), + .o_W_times_X_Y_1_6(o_WcxrXtYt_1_1_6), + .o_W_times_X_Y_1_7(o_WcxrXtYt_1_1_7), + .o_W_times_X_Y_1_8(o_WcxrXtYt_1_1_8), + .o_W_times_X_Y_1_9(o_WcxrXtYt_1_1_9), + .o_W_times_X_Y_1_10(o_WcxrXtYt_1_1_10), + .o_W_times_X_Y_1_11(o_WcxrXtYt_1_1_11), + .o_W_times_X_Y_1_12(o_WcxrXtYt_1_1_12), + .o_W_times_X_Y_1_13(o_WcxrXtYt_1_1_13), + .o_W_times_X_Y_1_14(o_WcxrXtYt_1_1_14), + .o_W_times_X_Y_1_15(o_WcxrXtYt_1_1_15), + .o_W_times_X_Y_2_0(o_WcxrXtYt_1_2_0), + .o_W_times_X_Y_2_1(o_WcxrXtYt_1_2_1), + .o_W_times_X_Y_2_2(o_WcxrXtYt_1_2_2), + .o_W_times_X_Y_2_3(o_WcxrXtYt_1_2_3), + .o_W_times_X_Y_2_4(o_WcxrXtYt_1_2_4), + .o_W_times_X_Y_2_5(o_WcxrXtYt_1_2_5), + .o_W_times_X_Y_2_6(o_WcxrXtYt_1_2_6), + .o_W_times_X_Y_2_7(o_WcxrXtYt_1_2_7), + .o_W_times_X_Y_2_8(o_WcxrXtYt_1_2_8), + .o_W_times_X_Y_2_9(o_WcxrXtYt_1_2_9), + .o_W_times_X_Y_2_10(o_WcxrXtYt_1_2_10), + .o_W_times_X_Y_2_11(o_WcxrXtYt_1_2_11), + .o_W_times_X_Y_2_12(o_WcxrXtYt_1_2_12), + .o_W_times_X_Y_2_13(o_WcxrXtYt_1_2_13), + .o_W_times_X_Y_2_14(o_WcxrXtYt_1_2_14), + .o_W_times_X_Y_2_15(o_WcxrXtYt_1_2_15), + .o_valid(output_act_mult_valid), + .o_ready(output_act_mult_ready) +); + +assign o_valid = input_gate_mult_valid & forget_gate_mult_valid & output_gate_mult_valid & output_act_mult_valid; +assign o_ready = input_gate_mult_ready & forget_gate_mult_ready & output_gate_mult_ready & output_act_mult_ready; + +endmodule + +module matrix_times_two_vectors_18_10_3_672_16_1 ( + input clk, + input reset, + input enable, + input i_ready, + input i_valid, + input [17:0] i_Xt_Yt_1_0, + input [17:0] i_Xt_Yt_1_1, + input [17:0] i_Xt_Yt_1_2, + input [17:0] i_Xt_Yt_1_3, + input [17:0] i_Xt_Yt_1_4, + input [17:0] i_Xt_Yt_1_5, + input [17:0] i_Xt_Yt_1_6, + input [17:0] i_Xt_Yt_1_7, + input [17:0] i_Xt_Yt_1_8, + input [17:0] i_Xt_Yt_1_9, + input [17:0] i_Xt_Yt_1_10, + input [17:0] i_Xt_Yt_1_11, + input [17:0] i_Xt_Yt_1_12, + input [17:0] i_Xt_Yt_1_13, + input [17:0] i_Xt_Yt_1_14, + input [17:0] i_Xt_Yt_1_15, + input [17:0] i_Wxr_real_0_0, + input [17:0] i_Wxr_imag_0_0, + input [17:0] i_Wxr_real_0_1, + input [17:0] i_Wxr_imag_0_1, + input [17:0] i_Wxr_real_0_2, + input [17:0] i_Wxr_imag_0_2, + input [17:0] i_Wxr_real_0_3, + input [17:0] i_Wxr_imag_0_3, + input [17:0] i_Wxr_real_0_4, + input [17:0] i_Wxr_imag_0_4, + input [17:0] i_Wxr_real_0_5, + input [17:0] i_Wxr_imag_0_5, + input [17:0] i_Wxr_real_0_6, + input [17:0] i_Wxr_imag_0_6, + input [17:0] i_Wxr_real_0_7, + input [17:0] i_Wxr_imag_0_7, + input [17:0] i_Wxr_real_0_8, + input [17:0] i_Wxr_imag_0_8, + input [17:0] i_Wxr_real_1_0, + input [17:0] i_Wxr_imag_1_0, + input [17:0] i_Wxr_real_1_1, + input [17:0] i_Wxr_imag_1_1, + input [17:0] i_Wxr_real_1_2, + input [17:0] i_Wxr_imag_1_2, + input [17:0] i_Wxr_real_1_3, + input [17:0] i_Wxr_imag_1_3, + input [17:0] i_Wxr_real_1_4, + input [17:0] i_Wxr_imag_1_4, + input [17:0] i_Wxr_real_1_5, + input [17:0] i_Wxr_imag_1_5, + input [17:0] i_Wxr_real_1_6, + input [17:0] i_Wxr_imag_1_6, + input [17:0] i_Wxr_real_1_7, + input [17:0] i_Wxr_imag_1_7, + input [17:0] i_Wxr_real_1_8, + input [17:0] i_Wxr_imag_1_8, + input [17:0] i_Wxr_real_2_0, + input [17:0] i_Wxr_imag_2_0, + input [17:0] i_Wxr_real_2_1, + input [17:0] i_Wxr_imag_2_1, + input [17:0] i_Wxr_real_2_2, + input [17:0] i_Wxr_imag_2_2, + input [17:0] i_Wxr_real_2_3, + input [17:0] i_Wxr_imag_2_3, + input [17:0] i_Wxr_real_2_4, + input [17:0] i_Wxr_imag_2_4, + input [17:0] i_Wxr_real_2_5, + input [17:0] i_Wxr_imag_2_5, + input [17:0] i_Wxr_real_2_6, + input [17:0] i_Wxr_imag_2_6, + input [17:0] i_Wxr_real_2_7, + input [17:0] i_Wxr_imag_2_7, + input [17:0] i_Wxr_real_2_8, + input [17:0] i_Wxr_imag_2_8, + output [17:0] o_W_times_X_Y_0_0, + output [17:0] o_W_times_X_Y_0_1, + output [17:0] o_W_times_X_Y_0_2, + output [17:0] o_W_times_X_Y_0_3, + output [17:0] o_W_times_X_Y_0_4, + output [17:0] o_W_times_X_Y_0_5, + output [17:0] o_W_times_X_Y_0_6, + output [17:0] o_W_times_X_Y_0_7, + output [17:0] o_W_times_X_Y_0_8, + output [17:0] o_W_times_X_Y_0_9, + output [17:0] o_W_times_X_Y_0_10, + output [17:0] o_W_times_X_Y_0_11, + output [17:0] o_W_times_X_Y_0_12, + output [17:0] o_W_times_X_Y_0_13, + output [17:0] o_W_times_X_Y_0_14, + output [17:0] o_W_times_X_Y_0_15, + output [17:0] o_W_times_X_Y_1_0, + output [17:0] o_W_times_X_Y_1_1, + output [17:0] o_W_times_X_Y_1_2, + output [17:0] o_W_times_X_Y_1_3, + output [17:0] o_W_times_X_Y_1_4, + output [17:0] o_W_times_X_Y_1_5, + output [17:0] o_W_times_X_Y_1_6, + output [17:0] o_W_times_X_Y_1_7, + output [17:0] o_W_times_X_Y_1_8, + output [17:0] o_W_times_X_Y_1_9, + output [17:0] o_W_times_X_Y_1_10, + output [17:0] o_W_times_X_Y_1_11, + output [17:0] o_W_times_X_Y_1_12, + output [17:0] o_W_times_X_Y_1_13, + output [17:0] o_W_times_X_Y_1_14, + output [17:0] o_W_times_X_Y_1_15, + output [17:0] o_W_times_X_Y_2_0, + output [17:0] o_W_times_X_Y_2_1, + output [17:0] o_W_times_X_Y_2_2, + output [17:0] o_W_times_X_Y_2_3, + output [17:0] o_W_times_X_Y_2_4, + output [17:0] o_W_times_X_Y_2_5, + output [17:0] o_W_times_X_Y_2_6, + output [17:0] o_W_times_X_Y_2_7, + output [17:0] o_W_times_X_Y_2_8, + output [17:0] o_W_times_X_Y_2_9, + output [17:0] o_W_times_X_Y_2_10, + output [17:0] o_W_times_X_Y_2_11, + output [17:0] o_W_times_X_Y_2_12, + output [17:0] o_W_times_X_Y_2_13, + output [17:0] o_W_times_X_Y_2_14, + output [17:0] o_W_times_X_Y_2_15, + output o_valid, + output o_ready +); + +multiple_c_matrix_vec_mult_and_sum_18_10_16_1_3_42 multiple_c_matrix_vec_mult_and_sum_18_10_16_1_3_42_inst_anmtqklnfe ( + .clk(clk), + .reset(reset), + .i_ready(i_ready), + .i_valid(i_valid), + .i_X_0(i_Xt_Yt_1_0), + .i_X_1(i_Xt_Yt_1_1), + .i_X_2(i_Xt_Yt_1_2), + .i_X_3(i_Xt_Yt_1_3), + .i_X_4(i_Xt_Yt_1_4), + .i_X_5(i_Xt_Yt_1_5), + .i_X_6(i_Xt_Yt_1_6), + .i_X_7(i_Xt_Yt_1_7), + .i_X_8(i_Xt_Yt_1_8), + .i_X_9(i_Xt_Yt_1_9), + .i_X_10(i_Xt_Yt_1_10), + .i_X_11(i_Xt_Yt_1_11), + .i_X_12(i_Xt_Yt_1_12), + .i_X_13(i_Xt_Yt_1_13), + .i_X_14(i_Xt_Yt_1_14), + .i_X_15(i_Xt_Yt_1_15), + .i_W_real_0_0(i_Wxr_real_0_0), + .i_W_imag_0_0(i_Wxr_imag_0_0), + .i_W_real_0_1(i_Wxr_real_0_1), + .i_W_imag_0_1(i_Wxr_imag_0_1), + .i_W_real_0_2(i_Wxr_real_0_2), + .i_W_imag_0_2(i_Wxr_imag_0_2), + .i_W_real_0_3(i_Wxr_real_0_3), + .i_W_imag_0_3(i_Wxr_imag_0_3), + .i_W_real_0_4(i_Wxr_real_0_4), + .i_W_imag_0_4(i_Wxr_imag_0_4), + .i_W_real_0_5(i_Wxr_real_0_5), + .i_W_imag_0_5(i_Wxr_imag_0_5), + .i_W_real_0_6(i_Wxr_real_0_6), + .i_W_imag_0_6(i_Wxr_imag_0_6), + .i_W_real_0_7(i_Wxr_real_0_7), + .i_W_imag_0_7(i_Wxr_imag_0_7), + .i_W_real_0_8(i_Wxr_real_0_8), + .i_W_imag_0_8(i_Wxr_imag_0_8), + .i_W_real_1_0(i_Wxr_real_1_0), + .i_W_imag_1_0(i_Wxr_imag_1_0), + .i_W_real_1_1(i_Wxr_real_1_1), + .i_W_imag_1_1(i_Wxr_imag_1_1), + .i_W_real_1_2(i_Wxr_real_1_2), + .i_W_imag_1_2(i_Wxr_imag_1_2), + .i_W_real_1_3(i_Wxr_real_1_3), + .i_W_imag_1_3(i_Wxr_imag_1_3), + .i_W_real_1_4(i_Wxr_real_1_4), + .i_W_imag_1_4(i_Wxr_imag_1_4), + .i_W_real_1_5(i_Wxr_real_1_5), + .i_W_imag_1_5(i_Wxr_imag_1_5), + .i_W_real_1_6(i_Wxr_real_1_6), + .i_W_imag_1_6(i_Wxr_imag_1_6), + .i_W_real_1_7(i_Wxr_real_1_7), + .i_W_imag_1_7(i_Wxr_imag_1_7), + .i_W_real_1_8(i_Wxr_real_1_8), + .i_W_imag_1_8(i_Wxr_imag_1_8), + .i_W_real_2_0(i_Wxr_real_2_0), + .i_W_imag_2_0(i_Wxr_imag_2_0), + .i_W_real_2_1(i_Wxr_real_2_1), + .i_W_imag_2_1(i_Wxr_imag_2_1), + .i_W_real_2_2(i_Wxr_real_2_2), + .i_W_imag_2_2(i_Wxr_imag_2_2), + .i_W_real_2_3(i_Wxr_real_2_3), + .i_W_imag_2_3(i_Wxr_imag_2_3), + .i_W_real_2_4(i_Wxr_real_2_4), + .i_W_imag_2_4(i_Wxr_imag_2_4), + .i_W_real_2_5(i_Wxr_real_2_5), + .i_W_imag_2_5(i_Wxr_imag_2_5), + .i_W_real_2_6(i_Wxr_real_2_6), + .i_W_imag_2_6(i_Wxr_imag_2_6), + .i_W_real_2_7(i_Wxr_real_2_7), + .i_W_imag_2_7(i_Wxr_imag_2_7), + .i_W_real_2_8(i_Wxr_real_2_8), + .i_W_imag_2_8(i_Wxr_imag_2_8), + .o_Y_0_0(o_W_times_X_Y_0_0), + .o_Y_0_1(o_W_times_X_Y_0_1), + .o_Y_0_2(o_W_times_X_Y_0_2), + .o_Y_0_3(o_W_times_X_Y_0_3), + .o_Y_0_4(o_W_times_X_Y_0_4), + .o_Y_0_5(o_W_times_X_Y_0_5), + .o_Y_0_6(o_W_times_X_Y_0_6), + .o_Y_0_7(o_W_times_X_Y_0_7), + .o_Y_0_8(o_W_times_X_Y_0_8), + .o_Y_0_9(o_W_times_X_Y_0_9), + .o_Y_0_10(o_W_times_X_Y_0_10), + .o_Y_0_11(o_W_times_X_Y_0_11), + .o_Y_0_12(o_W_times_X_Y_0_12), + .o_Y_0_13(o_W_times_X_Y_0_13), + .o_Y_0_14(o_W_times_X_Y_0_14), + .o_Y_0_15(o_W_times_X_Y_0_15), + .o_Y_1_0(o_W_times_X_Y_1_0), + .o_Y_1_1(o_W_times_X_Y_1_1), + .o_Y_1_2(o_W_times_X_Y_1_2), + .o_Y_1_3(o_W_times_X_Y_1_3), + .o_Y_1_4(o_W_times_X_Y_1_4), + .o_Y_1_5(o_W_times_X_Y_1_5), + .o_Y_1_6(o_W_times_X_Y_1_6), + .o_Y_1_7(o_W_times_X_Y_1_7), + .o_Y_1_8(o_W_times_X_Y_1_8), + .o_Y_1_9(o_W_times_X_Y_1_9), + .o_Y_1_10(o_W_times_X_Y_1_10), + .o_Y_1_11(o_W_times_X_Y_1_11), + .o_Y_1_12(o_W_times_X_Y_1_12), + .o_Y_1_13(o_W_times_X_Y_1_13), + .o_Y_1_14(o_W_times_X_Y_1_14), + .o_Y_1_15(o_W_times_X_Y_1_15), + .o_Y_2_0(o_W_times_X_Y_2_0), + .o_Y_2_1(o_W_times_X_Y_2_1), + .o_Y_2_2(o_W_times_X_Y_2_2), + .o_Y_2_3(o_W_times_X_Y_2_3), + .o_Y_2_4(o_W_times_X_Y_2_4), + .o_Y_2_5(o_W_times_X_Y_2_5), + .o_Y_2_6(o_W_times_X_Y_2_6), + .o_Y_2_7(o_W_times_X_Y_2_7), + .o_Y_2_8(o_W_times_X_Y_2_8), + .o_Y_2_9(o_W_times_X_Y_2_9), + .o_Y_2_10(o_W_times_X_Y_2_10), + .o_Y_2_11(o_W_times_X_Y_2_11), + .o_Y_2_12(o_W_times_X_Y_2_12), + .o_Y_2_13(o_W_times_X_Y_2_13), + .o_Y_2_14(o_W_times_X_Y_2_14), + .o_Y_2_15(o_W_times_X_Y_2_15), + .o_valid(o_valid), + .o_ready(o_ready) +); + +endmodule + +module multiple_c_matrix_vec_mult_and_sum_18_10_16_1_3_42 ( + input clk, + input reset, + input i_ready, + input i_valid, + input [17:0] i_X_0, + input [17:0] i_X_1, + input [17:0] i_X_2, + input [17:0] i_X_3, + input [17:0] i_X_4, + input [17:0] i_X_5, + input [17:0] i_X_6, + input [17:0] i_X_7, + input [17:0] i_X_8, + input [17:0] i_X_9, + input [17:0] i_X_10, + input [17:0] i_X_11, + input [17:0] i_X_12, + input [17:0] i_X_13, + input [17:0] i_X_14, + input [17:0] i_X_15, + input [17:0] i_W_real_0_0, + input [17:0] i_W_imag_0_0, + input [17:0] i_W_real_0_1, + input [17:0] i_W_imag_0_1, + input [17:0] i_W_real_0_2, + input [17:0] i_W_imag_0_2, + input [17:0] i_W_real_0_3, + input [17:0] i_W_imag_0_3, + input [17:0] i_W_real_0_4, + input [17:0] i_W_imag_0_4, + input [17:0] i_W_real_0_5, + input [17:0] i_W_imag_0_5, + input [17:0] i_W_real_0_6, + input [17:0] i_W_imag_0_6, + input [17:0] i_W_real_0_7, + input [17:0] i_W_imag_0_7, + input [17:0] i_W_real_0_8, + input [17:0] i_W_imag_0_8, + input [17:0] i_W_real_1_0, + input [17:0] i_W_imag_1_0, + input [17:0] i_W_real_1_1, + input [17:0] i_W_imag_1_1, + input [17:0] i_W_real_1_2, + input [17:0] i_W_imag_1_2, + input [17:0] i_W_real_1_3, + input [17:0] i_W_imag_1_3, + input [17:0] i_W_real_1_4, + input [17:0] i_W_imag_1_4, + input [17:0] i_W_real_1_5, + input [17:0] i_W_imag_1_5, + input [17:0] i_W_real_1_6, + input [17:0] i_W_imag_1_6, + input [17:0] i_W_real_1_7, + input [17:0] i_W_imag_1_7, + input [17:0] i_W_real_1_8, + input [17:0] i_W_imag_1_8, + input [17:0] i_W_real_2_0, + input [17:0] i_W_imag_2_0, + input [17:0] i_W_real_2_1, + input [17:0] i_W_imag_2_1, + input [17:0] i_W_real_2_2, + input [17:0] i_W_imag_2_2, + input [17:0] i_W_real_2_3, + input [17:0] i_W_imag_2_3, + input [17:0] i_W_real_2_4, + input [17:0] i_W_imag_2_4, + input [17:0] i_W_real_2_5, + input [17:0] i_W_imag_2_5, + input [17:0] i_W_real_2_6, + input [17:0] i_W_imag_2_6, + input [17:0] i_W_real_2_7, + input [17:0] i_W_imag_2_7, + input [17:0] i_W_real_2_8, + input [17:0] i_W_imag_2_8, + output [17:0] o_Y_0_0, + output [17:0] o_Y_0_1, + output [17:0] o_Y_0_2, + output [17:0] o_Y_0_3, + output [17:0] o_Y_0_4, + output [17:0] o_Y_0_5, + output [17:0] o_Y_0_6, + output [17:0] o_Y_0_7, + output [17:0] o_Y_0_8, + output [17:0] o_Y_0_9, + output [17:0] o_Y_0_10, + output [17:0] o_Y_0_11, + output [17:0] o_Y_0_12, + output [17:0] o_Y_0_13, + output [17:0] o_Y_0_14, + output [17:0] o_Y_0_15, + output [17:0] o_Y_1_0, + output [17:0] o_Y_1_1, + output [17:0] o_Y_1_2, + output [17:0] o_Y_1_3, + output [17:0] o_Y_1_4, + output [17:0] o_Y_1_5, + output [17:0] o_Y_1_6, + output [17:0] o_Y_1_7, + output [17:0] o_Y_1_8, + output [17:0] o_Y_1_9, + output [17:0] o_Y_1_10, + output [17:0] o_Y_1_11, + output [17:0] o_Y_1_12, + output [17:0] o_Y_1_13, + output [17:0] o_Y_1_14, + output [17:0] o_Y_1_15, + output [17:0] o_Y_2_0, + output [17:0] o_Y_2_1, + output [17:0] o_Y_2_2, + output [17:0] o_Y_2_3, + output [17:0] o_Y_2_4, + output [17:0] o_Y_2_5, + output [17:0] o_Y_2_6, + output [17:0] o_Y_2_7, + output [17:0] o_Y_2_8, + output [17:0] o_Y_2_9, + output [17:0] o_Y_2_10, + output [17:0] o_Y_2_11, + output [17:0] o_Y_2_12, + output [17:0] o_Y_2_13, + output [17:0] o_Y_2_14, + output [17:0] o_Y_2_15, + output o_valid, + output o_ready +); + +wire matrix_vec_mult_ready, matrix_vec_mult_valid; +wire accum_valid_0; +wire idft_next_out_0; +wire accum_valid_1; +wire idft_next_out_1; +wire accum_valid_2; +wire idft_next_out_2; +reg idft_out_valid; +wire [17:0] Y_imag_0_0; +wire [17:0] Y_real_0_0; +wire [17:0] sum_Y_real_0_0; +wire [17:0] sum_Y_imag_0_0; +wire [17:0] sum_Y_real_hold_0_0; +wire [17:0] sum_Y_imag_hold_0_0; +wire [17:0] out_Y_idft_0_0; +reg [17:0] reg_Y_0_0; +wire [17:0] Y_imag_0_1; +wire [17:0] Y_real_0_1; +wire [17:0] sum_Y_real_0_1; +wire [17:0] sum_Y_imag_0_1; +wire [17:0] sum_Y_real_hold_0_1; +wire [17:0] sum_Y_imag_hold_0_1; +wire [17:0] out_Y_idft_0_1; +reg [17:0] reg_Y_0_1; +wire [17:0] Y_imag_0_2; +wire [17:0] Y_real_0_2; +wire [17:0] sum_Y_real_0_2; +wire [17:0] sum_Y_imag_0_2; +wire [17:0] sum_Y_real_hold_0_2; +wire [17:0] sum_Y_imag_hold_0_2; +wire [17:0] out_Y_idft_0_2; +reg [17:0] reg_Y_0_2; +wire [17:0] Y_imag_0_3; +wire [17:0] Y_real_0_3; +wire [17:0] sum_Y_real_0_3; +wire [17:0] sum_Y_imag_0_3; +wire [17:0] sum_Y_real_hold_0_3; +wire [17:0] sum_Y_imag_hold_0_3; +wire [17:0] out_Y_idft_0_3; +reg [17:0] reg_Y_0_3; +wire [17:0] Y_imag_0_4; +wire [17:0] Y_real_0_4; +wire [17:0] sum_Y_real_0_4; +wire [17:0] sum_Y_imag_0_4; +wire [17:0] sum_Y_real_hold_0_4; +wire [17:0] sum_Y_imag_hold_0_4; +wire [17:0] out_Y_idft_0_4; +reg [17:0] reg_Y_0_4; +wire [17:0] Y_imag_0_5; +wire [17:0] Y_real_0_5; +wire [17:0] sum_Y_real_0_5; +wire [17:0] sum_Y_imag_0_5; +wire [17:0] sum_Y_real_hold_0_5; +wire [17:0] sum_Y_imag_hold_0_5; +wire [17:0] out_Y_idft_0_5; +reg [17:0] reg_Y_0_5; +wire [17:0] Y_imag_0_6; +wire [17:0] Y_real_0_6; +wire [17:0] sum_Y_real_0_6; +wire [17:0] sum_Y_imag_0_6; +wire [17:0] sum_Y_real_hold_0_6; +wire [17:0] sum_Y_imag_hold_0_6; +wire [17:0] out_Y_idft_0_6; +reg [17:0] reg_Y_0_6; +wire [17:0] Y_imag_0_7; +wire [17:0] Y_real_0_7; +wire [17:0] sum_Y_real_0_7; +wire [17:0] sum_Y_imag_0_7; +wire [17:0] sum_Y_real_hold_0_7; +wire [17:0] sum_Y_imag_hold_0_7; +wire [17:0] out_Y_idft_0_7; +reg [17:0] reg_Y_0_7; +wire [17:0] Y_imag_0_8; +wire [17:0] Y_real_0_8; +wire [17:0] sum_Y_real_0_8; +wire [17:0] sum_Y_imag_0_8; +wire [17:0] sum_Y_real_hold_0_8; +wire [17:0] sum_Y_imag_hold_0_8; +wire [17:0] out_Y_idft_0_8; +reg [17:0] reg_Y_0_8; +wire [17:0] Y_imag_0_9; +wire [17:0] Y_real_0_9; +wire [17:0] sum_Y_real_0_9; +wire [17:0] sum_Y_imag_0_9; +wire [17:0] sum_Y_real_hold_0_9; +wire [17:0] sum_Y_imag_hold_0_9; +wire [17:0] out_Y_idft_0_9; +reg [17:0] reg_Y_0_9; +wire [17:0] Y_imag_0_10; +wire [17:0] Y_real_0_10; +wire [17:0] sum_Y_real_0_10; +wire [17:0] sum_Y_imag_0_10; +wire [17:0] sum_Y_real_hold_0_10; +wire [17:0] sum_Y_imag_hold_0_10; +wire [17:0] out_Y_idft_0_10; +reg [17:0] reg_Y_0_10; +wire [17:0] Y_imag_0_11; +wire [17:0] Y_real_0_11; +wire [17:0] sum_Y_real_0_11; +wire [17:0] sum_Y_imag_0_11; +wire [17:0] sum_Y_real_hold_0_11; +wire [17:0] sum_Y_imag_hold_0_11; +wire [17:0] out_Y_idft_0_11; +reg [17:0] reg_Y_0_11; +wire [17:0] Y_imag_0_12; +wire [17:0] Y_real_0_12; +wire [17:0] sum_Y_real_0_12; +wire [17:0] sum_Y_imag_0_12; +wire [17:0] sum_Y_real_hold_0_12; +wire [17:0] sum_Y_imag_hold_0_12; +wire [17:0] out_Y_idft_0_12; +reg [17:0] reg_Y_0_12; +wire [17:0] Y_imag_0_13; +wire [17:0] Y_real_0_13; +wire [17:0] sum_Y_real_0_13; +wire [17:0] sum_Y_imag_0_13; +wire [17:0] sum_Y_real_hold_0_13; +wire [17:0] sum_Y_imag_hold_0_13; +wire [17:0] out_Y_idft_0_13; +reg [17:0] reg_Y_0_13; +wire [17:0] Y_imag_0_14; +wire [17:0] Y_real_0_14; +wire [17:0] sum_Y_real_0_14; +wire [17:0] sum_Y_imag_0_14; +wire [17:0] sum_Y_real_hold_0_14; +wire [17:0] sum_Y_imag_hold_0_14; +wire [17:0] out_Y_idft_0_14; +reg [17:0] reg_Y_0_14; +wire [17:0] Y_imag_0_15; +wire [17:0] Y_real_0_15; +wire [17:0] sum_Y_real_0_15; +wire [17:0] sum_Y_imag_0_15; +wire [17:0] sum_Y_real_hold_0_15; +wire [17:0] sum_Y_imag_hold_0_15; +wire [17:0] out_Y_idft_0_15; +reg [17:0] reg_Y_0_15; +wire [17:0] Y_imag_1_0; +wire [17:0] Y_real_1_0; +wire [17:0] sum_Y_real_1_0; +wire [17:0] sum_Y_imag_1_0; +wire [17:0] sum_Y_real_hold_1_0; +wire [17:0] sum_Y_imag_hold_1_0; +wire [17:0] out_Y_idft_1_0; +reg [17:0] reg_Y_1_0; +wire [17:0] Y_imag_1_1; +wire [17:0] Y_real_1_1; +wire [17:0] sum_Y_real_1_1; +wire [17:0] sum_Y_imag_1_1; +wire [17:0] sum_Y_real_hold_1_1; +wire [17:0] sum_Y_imag_hold_1_1; +wire [17:0] out_Y_idft_1_1; +reg [17:0] reg_Y_1_1; +wire [17:0] Y_imag_1_2; +wire [17:0] Y_real_1_2; +wire [17:0] sum_Y_real_1_2; +wire [17:0] sum_Y_imag_1_2; +wire [17:0] sum_Y_real_hold_1_2; +wire [17:0] sum_Y_imag_hold_1_2; +wire [17:0] out_Y_idft_1_2; +reg [17:0] reg_Y_1_2; +wire [17:0] Y_imag_1_3; +wire [17:0] Y_real_1_3; +wire [17:0] sum_Y_real_1_3; +wire [17:0] sum_Y_imag_1_3; +wire [17:0] sum_Y_real_hold_1_3; +wire [17:0] sum_Y_imag_hold_1_3; +wire [17:0] out_Y_idft_1_3; +reg [17:0] reg_Y_1_3; +wire [17:0] Y_imag_1_4; +wire [17:0] Y_real_1_4; +wire [17:0] sum_Y_real_1_4; +wire [17:0] sum_Y_imag_1_4; +wire [17:0] sum_Y_real_hold_1_4; +wire [17:0] sum_Y_imag_hold_1_4; +wire [17:0] out_Y_idft_1_4; +reg [17:0] reg_Y_1_4; +wire [17:0] Y_imag_1_5; +wire [17:0] Y_real_1_5; +wire [17:0] sum_Y_real_1_5; +wire [17:0] sum_Y_imag_1_5; +wire [17:0] sum_Y_real_hold_1_5; +wire [17:0] sum_Y_imag_hold_1_5; +wire [17:0] out_Y_idft_1_5; +reg [17:0] reg_Y_1_5; +wire [17:0] Y_imag_1_6; +wire [17:0] Y_real_1_6; +wire [17:0] sum_Y_real_1_6; +wire [17:0] sum_Y_imag_1_6; +wire [17:0] sum_Y_real_hold_1_6; +wire [17:0] sum_Y_imag_hold_1_6; +wire [17:0] out_Y_idft_1_6; +reg [17:0] reg_Y_1_6; +wire [17:0] Y_imag_1_7; +wire [17:0] Y_real_1_7; +wire [17:0] sum_Y_real_1_7; +wire [17:0] sum_Y_imag_1_7; +wire [17:0] sum_Y_real_hold_1_7; +wire [17:0] sum_Y_imag_hold_1_7; +wire [17:0] out_Y_idft_1_7; +reg [17:0] reg_Y_1_7; +wire [17:0] Y_imag_1_8; +wire [17:0] Y_real_1_8; +wire [17:0] sum_Y_real_1_8; +wire [17:0] sum_Y_imag_1_8; +wire [17:0] sum_Y_real_hold_1_8; +wire [17:0] sum_Y_imag_hold_1_8; +wire [17:0] out_Y_idft_1_8; +reg [17:0] reg_Y_1_8; +wire [17:0] Y_imag_1_9; +wire [17:0] Y_real_1_9; +wire [17:0] sum_Y_real_1_9; +wire [17:0] sum_Y_imag_1_9; +wire [17:0] sum_Y_real_hold_1_9; +wire [17:0] sum_Y_imag_hold_1_9; +wire [17:0] out_Y_idft_1_9; +reg [17:0] reg_Y_1_9; +wire [17:0] Y_imag_1_10; +wire [17:0] Y_real_1_10; +wire [17:0] sum_Y_real_1_10; +wire [17:0] sum_Y_imag_1_10; +wire [17:0] sum_Y_real_hold_1_10; +wire [17:0] sum_Y_imag_hold_1_10; +wire [17:0] out_Y_idft_1_10; +reg [17:0] reg_Y_1_10; +wire [17:0] Y_imag_1_11; +wire [17:0] Y_real_1_11; +wire [17:0] sum_Y_real_1_11; +wire [17:0] sum_Y_imag_1_11; +wire [17:0] sum_Y_real_hold_1_11; +wire [17:0] sum_Y_imag_hold_1_11; +wire [17:0] out_Y_idft_1_11; +reg [17:0] reg_Y_1_11; +wire [17:0] Y_imag_1_12; +wire [17:0] Y_real_1_12; +wire [17:0] sum_Y_real_1_12; +wire [17:0] sum_Y_imag_1_12; +wire [17:0] sum_Y_real_hold_1_12; +wire [17:0] sum_Y_imag_hold_1_12; +wire [17:0] out_Y_idft_1_12; +reg [17:0] reg_Y_1_12; +wire [17:0] Y_imag_1_13; +wire [17:0] Y_real_1_13; +wire [17:0] sum_Y_real_1_13; +wire [17:0] sum_Y_imag_1_13; +wire [17:0] sum_Y_real_hold_1_13; +wire [17:0] sum_Y_imag_hold_1_13; +wire [17:0] out_Y_idft_1_13; +reg [17:0] reg_Y_1_13; +wire [17:0] Y_imag_1_14; +wire [17:0] Y_real_1_14; +wire [17:0] sum_Y_real_1_14; +wire [17:0] sum_Y_imag_1_14; +wire [17:0] sum_Y_real_hold_1_14; +wire [17:0] sum_Y_imag_hold_1_14; +wire [17:0] out_Y_idft_1_14; +reg [17:0] reg_Y_1_14; +wire [17:0] Y_imag_1_15; +wire [17:0] Y_real_1_15; +wire [17:0] sum_Y_real_1_15; +wire [17:0] sum_Y_imag_1_15; +wire [17:0] sum_Y_real_hold_1_15; +wire [17:0] sum_Y_imag_hold_1_15; +wire [17:0] out_Y_idft_1_15; +reg [17:0] reg_Y_1_15; +wire [17:0] Y_imag_2_0; +wire [17:0] Y_real_2_0; +wire [17:0] sum_Y_real_2_0; +wire [17:0] sum_Y_imag_2_0; +wire [17:0] sum_Y_real_hold_2_0; +wire [17:0] sum_Y_imag_hold_2_0; +wire [17:0] out_Y_idft_2_0; +reg [17:0] reg_Y_2_0; +wire [17:0] Y_imag_2_1; +wire [17:0] Y_real_2_1; +wire [17:0] sum_Y_real_2_1; +wire [17:0] sum_Y_imag_2_1; +wire [17:0] sum_Y_real_hold_2_1; +wire [17:0] sum_Y_imag_hold_2_1; +wire [17:0] out_Y_idft_2_1; +reg [17:0] reg_Y_2_1; +wire [17:0] Y_imag_2_2; +wire [17:0] Y_real_2_2; +wire [17:0] sum_Y_real_2_2; +wire [17:0] sum_Y_imag_2_2; +wire [17:0] sum_Y_real_hold_2_2; +wire [17:0] sum_Y_imag_hold_2_2; +wire [17:0] out_Y_idft_2_2; +reg [17:0] reg_Y_2_2; +wire [17:0] Y_imag_2_3; +wire [17:0] Y_real_2_3; +wire [17:0] sum_Y_real_2_3; +wire [17:0] sum_Y_imag_2_3; +wire [17:0] sum_Y_real_hold_2_3; +wire [17:0] sum_Y_imag_hold_2_3; +wire [17:0] out_Y_idft_2_3; +reg [17:0] reg_Y_2_3; +wire [17:0] Y_imag_2_4; +wire [17:0] Y_real_2_4; +wire [17:0] sum_Y_real_2_4; +wire [17:0] sum_Y_imag_2_4; +wire [17:0] sum_Y_real_hold_2_4; +wire [17:0] sum_Y_imag_hold_2_4; +wire [17:0] out_Y_idft_2_4; +reg [17:0] reg_Y_2_4; +wire [17:0] Y_imag_2_5; +wire [17:0] Y_real_2_5; +wire [17:0] sum_Y_real_2_5; +wire [17:0] sum_Y_imag_2_5; +wire [17:0] sum_Y_real_hold_2_5; +wire [17:0] sum_Y_imag_hold_2_5; +wire [17:0] out_Y_idft_2_5; +reg [17:0] reg_Y_2_5; +wire [17:0] Y_imag_2_6; +wire [17:0] Y_real_2_6; +wire [17:0] sum_Y_real_2_6; +wire [17:0] sum_Y_imag_2_6; +wire [17:0] sum_Y_real_hold_2_6; +wire [17:0] sum_Y_imag_hold_2_6; +wire [17:0] out_Y_idft_2_6; +reg [17:0] reg_Y_2_6; +wire [17:0] Y_imag_2_7; +wire [17:0] Y_real_2_7; +wire [17:0] sum_Y_real_2_7; +wire [17:0] sum_Y_imag_2_7; +wire [17:0] sum_Y_real_hold_2_7; +wire [17:0] sum_Y_imag_hold_2_7; +wire [17:0] out_Y_idft_2_7; +reg [17:0] reg_Y_2_7; +wire [17:0] Y_imag_2_8; +wire [17:0] Y_real_2_8; +wire [17:0] sum_Y_real_2_8; +wire [17:0] sum_Y_imag_2_8; +wire [17:0] sum_Y_real_hold_2_8; +wire [17:0] sum_Y_imag_hold_2_8; +wire [17:0] out_Y_idft_2_8; +reg [17:0] reg_Y_2_8; +wire [17:0] Y_imag_2_9; +wire [17:0] Y_real_2_9; +wire [17:0] sum_Y_real_2_9; +wire [17:0] sum_Y_imag_2_9; +wire [17:0] sum_Y_real_hold_2_9; +wire [17:0] sum_Y_imag_hold_2_9; +wire [17:0] out_Y_idft_2_9; +reg [17:0] reg_Y_2_9; +wire [17:0] Y_imag_2_10; +wire [17:0] Y_real_2_10; +wire [17:0] sum_Y_real_2_10; +wire [17:0] sum_Y_imag_2_10; +wire [17:0] sum_Y_real_hold_2_10; +wire [17:0] sum_Y_imag_hold_2_10; +wire [17:0] out_Y_idft_2_10; +reg [17:0] reg_Y_2_10; +wire [17:0] Y_imag_2_11; +wire [17:0] Y_real_2_11; +wire [17:0] sum_Y_real_2_11; +wire [17:0] sum_Y_imag_2_11; +wire [17:0] sum_Y_real_hold_2_11; +wire [17:0] sum_Y_imag_hold_2_11; +wire [17:0] out_Y_idft_2_11; +reg [17:0] reg_Y_2_11; +wire [17:0] Y_imag_2_12; +wire [17:0] Y_real_2_12; +wire [17:0] sum_Y_real_2_12; +wire [17:0] sum_Y_imag_2_12; +wire [17:0] sum_Y_real_hold_2_12; +wire [17:0] sum_Y_imag_hold_2_12; +wire [17:0] out_Y_idft_2_12; +reg [17:0] reg_Y_2_12; +wire [17:0] Y_imag_2_13; +wire [17:0] Y_real_2_13; +wire [17:0] sum_Y_real_2_13; +wire [17:0] sum_Y_imag_2_13; +wire [17:0] sum_Y_real_hold_2_13; +wire [17:0] sum_Y_imag_hold_2_13; +wire [17:0] out_Y_idft_2_13; +reg [17:0] reg_Y_2_13; +wire [17:0] Y_imag_2_14; +wire [17:0] Y_real_2_14; +wire [17:0] sum_Y_real_2_14; +wire [17:0] sum_Y_imag_2_14; +wire [17:0] sum_Y_real_hold_2_14; +wire [17:0] sum_Y_imag_hold_2_14; +wire [17:0] out_Y_idft_2_14; +reg [17:0] reg_Y_2_14; +wire [17:0] Y_imag_2_15; +wire [17:0] Y_real_2_15; +wire [17:0] sum_Y_real_2_15; +wire [17:0] sum_Y_imag_2_15; +wire [17:0] sum_Y_real_hold_2_15; +wire [17:0] sum_Y_imag_hold_2_15; +wire [17:0] out_Y_idft_2_15; +reg [17:0] reg_Y_2_15; +reg reg_o_valid; + +// Enable whenever the reciever is ready +wire enable; +assign enable = i_ready; +c_matrix_vec_mult_core_18_10_16_3_1 c_matrix_vec_mult_core_18_10_16_3_1_inst_oeppwbieer ( + .clk(clk), + .reset(reset), + .i_ready(i_ready), + .i_valid(i_valid), + .i_X_0(i_X_0), + .i_X_1(i_X_1), + .i_X_2(i_X_2), + .i_X_3(i_X_3), + .i_X_4(i_X_4), + .i_X_5(i_X_5), + .i_X_6(i_X_6), + .i_X_7(i_X_7), + .i_X_8(i_X_8), + .i_X_9(i_X_9), + .i_X_10(i_X_10), + .i_X_11(i_X_11), + .i_X_12(i_X_12), + .i_X_13(i_X_13), + .i_X_14(i_X_14), + .i_X_15(i_X_15), + .i_W_real_0_0(i_W_real_0_0), + .i_W_imag_0_0(i_W_imag_0_0), + .i_W_real_0_1(i_W_real_0_1), + .i_W_imag_0_1(i_W_imag_0_1), + .i_W_real_0_2(i_W_real_0_2), + .i_W_imag_0_2(i_W_imag_0_2), + .i_W_real_0_3(i_W_real_0_3), + .i_W_imag_0_3(i_W_imag_0_3), + .i_W_real_0_4(i_W_real_0_4), + .i_W_imag_0_4(i_W_imag_0_4), + .i_W_real_0_5(i_W_real_0_5), + .i_W_imag_0_5(i_W_imag_0_5), + .i_W_real_0_6(i_W_real_0_6), + .i_W_imag_0_6(i_W_imag_0_6), + .i_W_real_0_7(i_W_real_0_7), + .i_W_imag_0_7(i_W_imag_0_7), + .i_W_real_0_8(i_W_real_0_8), + .i_W_imag_0_8(i_W_imag_0_8), + .i_W_real_1_0(i_W_real_1_0), + .i_W_imag_1_0(i_W_imag_1_0), + .i_W_real_1_1(i_W_real_1_1), + .i_W_imag_1_1(i_W_imag_1_1), + .i_W_real_1_2(i_W_real_1_2), + .i_W_imag_1_2(i_W_imag_1_2), + .i_W_real_1_3(i_W_real_1_3), + .i_W_imag_1_3(i_W_imag_1_3), + .i_W_real_1_4(i_W_real_1_4), + .i_W_imag_1_4(i_W_imag_1_4), + .i_W_real_1_5(i_W_real_1_5), + .i_W_imag_1_5(i_W_imag_1_5), + .i_W_real_1_6(i_W_real_1_6), + .i_W_imag_1_6(i_W_imag_1_6), + .i_W_real_1_7(i_W_real_1_7), + .i_W_imag_1_7(i_W_imag_1_7), + .i_W_real_1_8(i_W_real_1_8), + .i_W_imag_1_8(i_W_imag_1_8), + .i_W_real_2_0(i_W_real_2_0), + .i_W_imag_2_0(i_W_imag_2_0), + .i_W_real_2_1(i_W_real_2_1), + .i_W_imag_2_1(i_W_imag_2_1), + .i_W_real_2_2(i_W_real_2_2), + .i_W_imag_2_2(i_W_imag_2_2), + .i_W_real_2_3(i_W_real_2_3), + .i_W_imag_2_3(i_W_imag_2_3), + .i_W_real_2_4(i_W_real_2_4), + .i_W_imag_2_4(i_W_imag_2_4), + .i_W_real_2_5(i_W_real_2_5), + .i_W_imag_2_5(i_W_imag_2_5), + .i_W_real_2_6(i_W_real_2_6), + .i_W_imag_2_6(i_W_imag_2_6), + .i_W_real_2_7(i_W_real_2_7), + .i_W_imag_2_7(i_W_imag_2_7), + .i_W_real_2_8(i_W_real_2_8), + .i_W_imag_2_8(i_W_imag_2_8), + .o_Y_real_0_0(Y_real_0_0), + .o_Y_imag_0_0(Y_imag_0_0), + .o_Y_real_0_1(Y_real_0_1), + .o_Y_imag_0_1(Y_imag_0_1), + .o_Y_real_0_2(Y_real_0_2), + .o_Y_imag_0_2(Y_imag_0_2), + .o_Y_real_0_3(Y_real_0_3), + .o_Y_imag_0_3(Y_imag_0_3), + .o_Y_real_0_4(Y_real_0_4), + .o_Y_imag_0_4(Y_imag_0_4), + .o_Y_real_0_5(Y_real_0_5), + .o_Y_imag_0_5(Y_imag_0_5), + .o_Y_real_0_6(Y_real_0_6), + .o_Y_imag_0_6(Y_imag_0_6), + .o_Y_real_0_7(Y_real_0_7), + .o_Y_imag_0_7(Y_imag_0_7), + .o_Y_real_0_8(Y_real_0_8), + .o_Y_imag_0_8(Y_imag_0_8), + .o_Y_real_0_9(Y_real_0_9), + .o_Y_imag_0_9(Y_imag_0_9), + .o_Y_real_0_10(Y_real_0_10), + .o_Y_imag_0_10(Y_imag_0_10), + .o_Y_real_0_11(Y_real_0_11), + .o_Y_imag_0_11(Y_imag_0_11), + .o_Y_real_0_12(Y_real_0_12), + .o_Y_imag_0_12(Y_imag_0_12), + .o_Y_real_0_13(Y_real_0_13), + .o_Y_imag_0_13(Y_imag_0_13), + .o_Y_real_0_14(Y_real_0_14), + .o_Y_imag_0_14(Y_imag_0_14), + .o_Y_real_0_15(Y_real_0_15), + .o_Y_imag_0_15(Y_imag_0_15), + .o_Y_real_1_0(Y_real_1_0), + .o_Y_imag_1_0(Y_imag_1_0), + .o_Y_real_1_1(Y_real_1_1), + .o_Y_imag_1_1(Y_imag_1_1), + .o_Y_real_1_2(Y_real_1_2), + .o_Y_imag_1_2(Y_imag_1_2), + .o_Y_real_1_3(Y_real_1_3), + .o_Y_imag_1_3(Y_imag_1_3), + .o_Y_real_1_4(Y_real_1_4), + .o_Y_imag_1_4(Y_imag_1_4), + .o_Y_real_1_5(Y_real_1_5), + .o_Y_imag_1_5(Y_imag_1_5), + .o_Y_real_1_6(Y_real_1_6), + .o_Y_imag_1_6(Y_imag_1_6), + .o_Y_real_1_7(Y_real_1_7), + .o_Y_imag_1_7(Y_imag_1_7), + .o_Y_real_1_8(Y_real_1_8), + .o_Y_imag_1_8(Y_imag_1_8), + .o_Y_real_1_9(Y_real_1_9), + .o_Y_imag_1_9(Y_imag_1_9), + .o_Y_real_1_10(Y_real_1_10), + .o_Y_imag_1_10(Y_imag_1_10), + .o_Y_real_1_11(Y_real_1_11), + .o_Y_imag_1_11(Y_imag_1_11), + .o_Y_real_1_12(Y_real_1_12), + .o_Y_imag_1_12(Y_imag_1_12), + .o_Y_real_1_13(Y_real_1_13), + .o_Y_imag_1_13(Y_imag_1_13), + .o_Y_real_1_14(Y_real_1_14), + .o_Y_imag_1_14(Y_imag_1_14), + .o_Y_real_1_15(Y_real_1_15), + .o_Y_imag_1_15(Y_imag_1_15), + .o_Y_real_2_0(Y_real_2_0), + .o_Y_imag_2_0(Y_imag_2_0), + .o_Y_real_2_1(Y_real_2_1), + .o_Y_imag_2_1(Y_imag_2_1), + .o_Y_real_2_2(Y_real_2_2), + .o_Y_imag_2_2(Y_imag_2_2), + .o_Y_real_2_3(Y_real_2_3), + .o_Y_imag_2_3(Y_imag_2_3), + .o_Y_real_2_4(Y_real_2_4), + .o_Y_imag_2_4(Y_imag_2_4), + .o_Y_real_2_5(Y_real_2_5), + .o_Y_imag_2_5(Y_imag_2_5), + .o_Y_real_2_6(Y_real_2_6), + .o_Y_imag_2_6(Y_imag_2_6), + .o_Y_real_2_7(Y_real_2_7), + .o_Y_imag_2_7(Y_imag_2_7), + .o_Y_real_2_8(Y_real_2_8), + .o_Y_imag_2_8(Y_imag_2_8), + .o_Y_real_2_9(Y_real_2_9), + .o_Y_imag_2_9(Y_imag_2_9), + .o_Y_real_2_10(Y_real_2_10), + .o_Y_imag_2_10(Y_imag_2_10), + .o_Y_real_2_11(Y_real_2_11), + .o_Y_imag_2_11(Y_imag_2_11), + .o_Y_real_2_12(Y_real_2_12), + .o_Y_imag_2_12(Y_imag_2_12), + .o_Y_real_2_13(Y_real_2_13), + .o_Y_imag_2_13(Y_imag_2_13), + .o_Y_real_2_14(Y_real_2_14), + .o_Y_imag_2_14(Y_imag_2_14), + .o_Y_real_2_15(Y_real_2_15), + .o_Y_imag_2_15(Y_imag_2_15), + .o_ready(matrix_vec_mult_ready), + .o_valid(matrix_vec_mult_valid) +); + +sum_complex_vector_unit_18_18_16_42 sum_complex_vector_unit_18_18_16_42_inst_iymvcryebf ( + .clk(clk), + .clr(reset), + .enable(enable), + .i_valid(matrix_vec_mult_valid), + .i_real_0(Y_real_0_0), + .i_imag_0(Y_imag_0_0), + .o_real_0(sum_Y_real_0_0), + .o_imag_0(sum_Y_imag_0_0), + .i_real_1(Y_real_0_1), + .i_imag_1(Y_imag_0_1), + .o_real_1(sum_Y_real_0_1), + .o_imag_1(sum_Y_imag_0_1), + .i_real_2(Y_real_0_2), + .i_imag_2(Y_imag_0_2), + .o_real_2(sum_Y_real_0_2), + .o_imag_2(sum_Y_imag_0_2), + .i_real_3(Y_real_0_3), + .i_imag_3(Y_imag_0_3), + .o_real_3(sum_Y_real_0_3), + .o_imag_3(sum_Y_imag_0_3), + .i_real_4(Y_real_0_4), + .i_imag_4(Y_imag_0_4), + .o_real_4(sum_Y_real_0_4), + .o_imag_4(sum_Y_imag_0_4), + .i_real_5(Y_real_0_5), + .i_imag_5(Y_imag_0_5), + .o_real_5(sum_Y_real_0_5), + .o_imag_5(sum_Y_imag_0_5), + .i_real_6(Y_real_0_6), + .i_imag_6(Y_imag_0_6), + .o_real_6(sum_Y_real_0_6), + .o_imag_6(sum_Y_imag_0_6), + .i_real_7(Y_real_0_7), + .i_imag_7(Y_imag_0_7), + .o_real_7(sum_Y_real_0_7), + .o_imag_7(sum_Y_imag_0_7), + .i_real_8(Y_real_0_8), + .i_imag_8(Y_imag_0_8), + .o_real_8(sum_Y_real_0_8), + .o_imag_8(sum_Y_imag_0_8), + .i_real_9(Y_real_0_9), + .i_imag_9(Y_imag_0_9), + .o_real_9(sum_Y_real_0_9), + .o_imag_9(sum_Y_imag_0_9), + .i_real_10(Y_real_0_10), + .i_imag_10(Y_imag_0_10), + .o_real_10(sum_Y_real_0_10), + .o_imag_10(sum_Y_imag_0_10), + .i_real_11(Y_real_0_11), + .i_imag_11(Y_imag_0_11), + .o_real_11(sum_Y_real_0_11), + .o_imag_11(sum_Y_imag_0_11), + .i_real_12(Y_real_0_12), + .i_imag_12(Y_imag_0_12), + .o_real_12(sum_Y_real_0_12), + .o_imag_12(sum_Y_imag_0_12), + .i_real_13(Y_real_0_13), + .i_imag_13(Y_imag_0_13), + .o_real_13(sum_Y_real_0_13), + .o_imag_13(sum_Y_imag_0_13), + .i_real_14(Y_real_0_14), + .i_imag_14(Y_imag_0_14), + .o_real_14(sum_Y_real_0_14), + .o_imag_14(sum_Y_imag_0_14), + .i_real_15(Y_real_0_15), + .i_imag_15(Y_imag_0_15), + .o_real_15(sum_Y_real_0_15), + .o_imag_15(sum_Y_imag_0_15), + .o_valid(accum_valid_0) +); + +sum_complex_vector_unit_18_18_16_42 sum_complex_vector_unit_18_18_16_42_inst_dhbuiwnpih ( + .clk(clk), + .clr(reset), + .enable(enable), + .i_valid(matrix_vec_mult_valid), + .i_real_0(Y_real_1_0), + .i_imag_0(Y_imag_1_0), + .o_real_0(sum_Y_real_1_0), + .o_imag_0(sum_Y_imag_1_0), + .i_real_1(Y_real_1_1), + .i_imag_1(Y_imag_1_1), + .o_real_1(sum_Y_real_1_1), + .o_imag_1(sum_Y_imag_1_1), + .i_real_2(Y_real_1_2), + .i_imag_2(Y_imag_1_2), + .o_real_2(sum_Y_real_1_2), + .o_imag_2(sum_Y_imag_1_2), + .i_real_3(Y_real_1_3), + .i_imag_3(Y_imag_1_3), + .o_real_3(sum_Y_real_1_3), + .o_imag_3(sum_Y_imag_1_3), + .i_real_4(Y_real_1_4), + .i_imag_4(Y_imag_1_4), + .o_real_4(sum_Y_real_1_4), + .o_imag_4(sum_Y_imag_1_4), + .i_real_5(Y_real_1_5), + .i_imag_5(Y_imag_1_5), + .o_real_5(sum_Y_real_1_5), + .o_imag_5(sum_Y_imag_1_5), + .i_real_6(Y_real_1_6), + .i_imag_6(Y_imag_1_6), + .o_real_6(sum_Y_real_1_6), + .o_imag_6(sum_Y_imag_1_6), + .i_real_7(Y_real_1_7), + .i_imag_7(Y_imag_1_7), + .o_real_7(sum_Y_real_1_7), + .o_imag_7(sum_Y_imag_1_7), + .i_real_8(Y_real_1_8), + .i_imag_8(Y_imag_1_8), + .o_real_8(sum_Y_real_1_8), + .o_imag_8(sum_Y_imag_1_8), + .i_real_9(Y_real_1_9), + .i_imag_9(Y_imag_1_9), + .o_real_9(sum_Y_real_1_9), + .o_imag_9(sum_Y_imag_1_9), + .i_real_10(Y_real_1_10), + .i_imag_10(Y_imag_1_10), + .o_real_10(sum_Y_real_1_10), + .o_imag_10(sum_Y_imag_1_10), + .i_real_11(Y_real_1_11), + .i_imag_11(Y_imag_1_11), + .o_real_11(sum_Y_real_1_11), + .o_imag_11(sum_Y_imag_1_11), + .i_real_12(Y_real_1_12), + .i_imag_12(Y_imag_1_12), + .o_real_12(sum_Y_real_1_12), + .o_imag_12(sum_Y_imag_1_12), + .i_real_13(Y_real_1_13), + .i_imag_13(Y_imag_1_13), + .o_real_13(sum_Y_real_1_13), + .o_imag_13(sum_Y_imag_1_13), + .i_real_14(Y_real_1_14), + .i_imag_14(Y_imag_1_14), + .o_real_14(sum_Y_real_1_14), + .o_imag_14(sum_Y_imag_1_14), + .i_real_15(Y_real_1_15), + .i_imag_15(Y_imag_1_15), + .o_real_15(sum_Y_real_1_15), + .o_imag_15(sum_Y_imag_1_15), + .o_valid(accum_valid_1) +); + +sum_complex_vector_unit_18_18_16_42 sum_complex_vector_unit_18_18_16_42_inst_eojcazeumb ( + .clk(clk), + .clr(reset), + .enable(enable), + .i_valid(matrix_vec_mult_valid), + .i_real_0(Y_real_2_0), + .i_imag_0(Y_imag_2_0), + .o_real_0(sum_Y_real_2_0), + .o_imag_0(sum_Y_imag_2_0), + .i_real_1(Y_real_2_1), + .i_imag_1(Y_imag_2_1), + .o_real_1(sum_Y_real_2_1), + .o_imag_1(sum_Y_imag_2_1), + .i_real_2(Y_real_2_2), + .i_imag_2(Y_imag_2_2), + .o_real_2(sum_Y_real_2_2), + .o_imag_2(sum_Y_imag_2_2), + .i_real_3(Y_real_2_3), + .i_imag_3(Y_imag_2_3), + .o_real_3(sum_Y_real_2_3), + .o_imag_3(sum_Y_imag_2_3), + .i_real_4(Y_real_2_4), + .i_imag_4(Y_imag_2_4), + .o_real_4(sum_Y_real_2_4), + .o_imag_4(sum_Y_imag_2_4), + .i_real_5(Y_real_2_5), + .i_imag_5(Y_imag_2_5), + .o_real_5(sum_Y_real_2_5), + .o_imag_5(sum_Y_imag_2_5), + .i_real_6(Y_real_2_6), + .i_imag_6(Y_imag_2_6), + .o_real_6(sum_Y_real_2_6), + .o_imag_6(sum_Y_imag_2_6), + .i_real_7(Y_real_2_7), + .i_imag_7(Y_imag_2_7), + .o_real_7(sum_Y_real_2_7), + .o_imag_7(sum_Y_imag_2_7), + .i_real_8(Y_real_2_8), + .i_imag_8(Y_imag_2_8), + .o_real_8(sum_Y_real_2_8), + .o_imag_8(sum_Y_imag_2_8), + .i_real_9(Y_real_2_9), + .i_imag_9(Y_imag_2_9), + .o_real_9(sum_Y_real_2_9), + .o_imag_9(sum_Y_imag_2_9), + .i_real_10(Y_real_2_10), + .i_imag_10(Y_imag_2_10), + .o_real_10(sum_Y_real_2_10), + .o_imag_10(sum_Y_imag_2_10), + .i_real_11(Y_real_2_11), + .i_imag_11(Y_imag_2_11), + .o_real_11(sum_Y_real_2_11), + .o_imag_11(sum_Y_imag_2_11), + .i_real_12(Y_real_2_12), + .i_imag_12(Y_imag_2_12), + .o_real_12(sum_Y_real_2_12), + .o_imag_12(sum_Y_imag_2_12), + .i_real_13(Y_real_2_13), + .i_imag_13(Y_imag_2_13), + .o_real_13(sum_Y_real_2_13), + .o_imag_13(sum_Y_imag_2_13), + .i_real_14(Y_real_2_14), + .i_imag_14(Y_imag_2_14), + .o_real_14(sum_Y_real_2_14), + .o_imag_14(sum_Y_imag_2_14), + .i_real_15(Y_real_2_15), + .i_imag_15(Y_imag_2_15), + .o_real_15(sum_Y_real_2_15), + .o_imag_15(sum_Y_imag_2_15), + .o_valid(accum_valid_2) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_qwsubuofsr_real ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_real_0_0), + .out_0(sum_Y_real_hold_0_0), + .in_1(sum_Y_real_0_1), + .out_1(sum_Y_real_hold_0_1), + .in_2(sum_Y_real_0_2), + .out_2(sum_Y_real_hold_0_2), + .in_3(sum_Y_real_0_3), + .out_3(sum_Y_real_hold_0_3), + .in_4(sum_Y_real_0_4), + .out_4(sum_Y_real_hold_0_4), + .in_5(sum_Y_real_0_5), + .out_5(sum_Y_real_hold_0_5), + .in_6(sum_Y_real_0_6), + .out_6(sum_Y_real_hold_0_6), + .in_7(sum_Y_real_0_7), + .out_7(sum_Y_real_hold_0_7), + .in_8(sum_Y_real_0_8), + .out_8(sum_Y_real_hold_0_8), + .in_9(sum_Y_real_0_9), + .out_9(sum_Y_real_hold_0_9), + .in_10(sum_Y_real_0_10), + .out_10(sum_Y_real_hold_0_10), + .in_11(sum_Y_real_0_11), + .out_11(sum_Y_real_hold_0_11), + .in_12(sum_Y_real_0_12), + .out_12(sum_Y_real_hold_0_12), + .in_13(sum_Y_real_0_13), + .out_13(sum_Y_real_hold_0_13), + .in_14(sum_Y_real_0_14), + .out_14(sum_Y_real_hold_0_14), + .in_15(sum_Y_real_0_15), + .out_15(sum_Y_real_hold_0_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_anmokxpocf_imag ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_imag_0_0), + .out_0(sum_Y_imag_hold_0_0), + .in_1(sum_Y_imag_0_1), + .out_1(sum_Y_imag_hold_0_1), + .in_2(sum_Y_imag_0_2), + .out_2(sum_Y_imag_hold_0_2), + .in_3(sum_Y_imag_0_3), + .out_3(sum_Y_imag_hold_0_3), + .in_4(sum_Y_imag_0_4), + .out_4(sum_Y_imag_hold_0_4), + .in_5(sum_Y_imag_0_5), + .out_5(sum_Y_imag_hold_0_5), + .in_6(sum_Y_imag_0_6), + .out_6(sum_Y_imag_hold_0_6), + .in_7(sum_Y_imag_0_7), + .out_7(sum_Y_imag_hold_0_7), + .in_8(sum_Y_imag_0_8), + .out_8(sum_Y_imag_hold_0_8), + .in_9(sum_Y_imag_0_9), + .out_9(sum_Y_imag_hold_0_9), + .in_10(sum_Y_imag_0_10), + .out_10(sum_Y_imag_hold_0_10), + .in_11(sum_Y_imag_0_11), + .out_11(sum_Y_imag_hold_0_11), + .in_12(sum_Y_imag_0_12), + .out_12(sum_Y_imag_hold_0_12), + .in_13(sum_Y_imag_0_13), + .out_13(sum_Y_imag_hold_0_13), + .in_14(sum_Y_imag_0_14), + .out_14(sum_Y_imag_hold_0_14), + .in_15(sum_Y_imag_0_15), + .out_15(sum_Y_imag_hold_0_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_oxmjcbkovx_real ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_real_1_0), + .out_0(sum_Y_real_hold_1_0), + .in_1(sum_Y_real_1_1), + .out_1(sum_Y_real_hold_1_1), + .in_2(sum_Y_real_1_2), + .out_2(sum_Y_real_hold_1_2), + .in_3(sum_Y_real_1_3), + .out_3(sum_Y_real_hold_1_3), + .in_4(sum_Y_real_1_4), + .out_4(sum_Y_real_hold_1_4), + .in_5(sum_Y_real_1_5), + .out_5(sum_Y_real_hold_1_5), + .in_6(sum_Y_real_1_6), + .out_6(sum_Y_real_hold_1_6), + .in_7(sum_Y_real_1_7), + .out_7(sum_Y_real_hold_1_7), + .in_8(sum_Y_real_1_8), + .out_8(sum_Y_real_hold_1_8), + .in_9(sum_Y_real_1_9), + .out_9(sum_Y_real_hold_1_9), + .in_10(sum_Y_real_1_10), + .out_10(sum_Y_real_hold_1_10), + .in_11(sum_Y_real_1_11), + .out_11(sum_Y_real_hold_1_11), + .in_12(sum_Y_real_1_12), + .out_12(sum_Y_real_hold_1_12), + .in_13(sum_Y_real_1_13), + .out_13(sum_Y_real_hold_1_13), + .in_14(sum_Y_real_1_14), + .out_14(sum_Y_real_hold_1_14), + .in_15(sum_Y_real_1_15), + .out_15(sum_Y_real_hold_1_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_bstyvmgsnp_imag ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_imag_1_0), + .out_0(sum_Y_imag_hold_1_0), + .in_1(sum_Y_imag_1_1), + .out_1(sum_Y_imag_hold_1_1), + .in_2(sum_Y_imag_1_2), + .out_2(sum_Y_imag_hold_1_2), + .in_3(sum_Y_imag_1_3), + .out_3(sum_Y_imag_hold_1_3), + .in_4(sum_Y_imag_1_4), + .out_4(sum_Y_imag_hold_1_4), + .in_5(sum_Y_imag_1_5), + .out_5(sum_Y_imag_hold_1_5), + .in_6(sum_Y_imag_1_6), + .out_6(sum_Y_imag_hold_1_6), + .in_7(sum_Y_imag_1_7), + .out_7(sum_Y_imag_hold_1_7), + .in_8(sum_Y_imag_1_8), + .out_8(sum_Y_imag_hold_1_8), + .in_9(sum_Y_imag_1_9), + .out_9(sum_Y_imag_hold_1_9), + .in_10(sum_Y_imag_1_10), + .out_10(sum_Y_imag_hold_1_10), + .in_11(sum_Y_imag_1_11), + .out_11(sum_Y_imag_hold_1_11), + .in_12(sum_Y_imag_1_12), + .out_12(sum_Y_imag_hold_1_12), + .in_13(sum_Y_imag_1_13), + .out_13(sum_Y_imag_hold_1_13), + .in_14(sum_Y_imag_1_14), + .out_14(sum_Y_imag_hold_1_14), + .in_15(sum_Y_imag_1_15), + .out_15(sum_Y_imag_hold_1_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_sivvrmcuhx_real ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_real_2_0), + .out_0(sum_Y_real_hold_2_0), + .in_1(sum_Y_real_2_1), + .out_1(sum_Y_real_hold_2_1), + .in_2(sum_Y_real_2_2), + .out_2(sum_Y_real_hold_2_2), + .in_3(sum_Y_real_2_3), + .out_3(sum_Y_real_hold_2_3), + .in_4(sum_Y_real_2_4), + .out_4(sum_Y_real_hold_2_4), + .in_5(sum_Y_real_2_5), + .out_5(sum_Y_real_hold_2_5), + .in_6(sum_Y_real_2_6), + .out_6(sum_Y_real_hold_2_6), + .in_7(sum_Y_real_2_7), + .out_7(sum_Y_real_hold_2_7), + .in_8(sum_Y_real_2_8), + .out_8(sum_Y_real_hold_2_8), + .in_9(sum_Y_real_2_9), + .out_9(sum_Y_real_hold_2_9), + .in_10(sum_Y_real_2_10), + .out_10(sum_Y_real_hold_2_10), + .in_11(sum_Y_real_2_11), + .out_11(sum_Y_real_hold_2_11), + .in_12(sum_Y_real_2_12), + .out_12(sum_Y_real_hold_2_12), + .in_13(sum_Y_real_2_13), + .out_13(sum_Y_real_hold_2_13), + .in_14(sum_Y_real_2_14), + .out_14(sum_Y_real_hold_2_14), + .in_15(sum_Y_real_2_15), + .out_15(sum_Y_real_hold_2_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_xsrwvubcqa_imag ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_imag_2_0), + .out_0(sum_Y_imag_hold_2_0), + .in_1(sum_Y_imag_2_1), + .out_1(sum_Y_imag_hold_2_1), + .in_2(sum_Y_imag_2_2), + .out_2(sum_Y_imag_hold_2_2), + .in_3(sum_Y_imag_2_3), + .out_3(sum_Y_imag_hold_2_3), + .in_4(sum_Y_imag_2_4), + .out_4(sum_Y_imag_hold_2_4), + .in_5(sum_Y_imag_2_5), + .out_5(sum_Y_imag_hold_2_5), + .in_6(sum_Y_imag_2_6), + .out_6(sum_Y_imag_hold_2_6), + .in_7(sum_Y_imag_2_7), + .out_7(sum_Y_imag_hold_2_7), + .in_8(sum_Y_imag_2_8), + .out_8(sum_Y_imag_hold_2_8), + .in_9(sum_Y_imag_2_9), + .out_9(sum_Y_imag_hold_2_9), + .in_10(sum_Y_imag_2_10), + .out_10(sum_Y_imag_hold_2_10), + .in_11(sum_Y_imag_2_11), + .out_11(sum_Y_imag_hold_2_11), + .in_12(sum_Y_imag_2_12), + .out_12(sum_Y_imag_hold_2_12), + .in_13(sum_Y_imag_2_13), + .out_13(sum_Y_imag_hold_2_13), + .in_14(sum_Y_imag_2_14), + .out_14(sum_Y_imag_hold_2_14), + .in_15(sum_Y_imag_2_15), + .out_15(sum_Y_imag_hold_2_15), + .reset(reset) +); + +idft_16_top_18 idft_16_top_18_inst_cayjwxjxhl ( + .clk(clk), + .reset(reset), + .next(accum_valid_0), + .X0(sum_Y_real_hold_0_0), + .Y0(out_Y_idft_0_0), + .X1(sum_Y_imag_hold_0_0), + .Y1(), + .X2(sum_Y_real_hold_0_1), + .Y2(out_Y_idft_0_1), + .X3(sum_Y_imag_hold_0_1), + .Y3(), + .X4(sum_Y_real_hold_0_2), + .Y4(out_Y_idft_0_2), + .X5(sum_Y_imag_hold_0_2), + .Y5(), + .X6(sum_Y_real_hold_0_3), + .Y6(out_Y_idft_0_3), + .X7(sum_Y_imag_hold_0_3), + .Y7(), + .X8(sum_Y_real_hold_0_4), + .Y8(out_Y_idft_0_4), + .X9(sum_Y_imag_hold_0_4), + .Y9(), + .X10(sum_Y_real_hold_0_5), + .Y10(out_Y_idft_0_5), + .X11(sum_Y_imag_hold_0_5), + .Y11(), + .X12(sum_Y_real_hold_0_6), + .Y12(out_Y_idft_0_6), + .X13(sum_Y_imag_hold_0_6), + .Y13(), + .X14(sum_Y_real_hold_0_7), + .Y14(out_Y_idft_0_7), + .X15(sum_Y_imag_hold_0_7), + .Y15(), + .X16(sum_Y_real_hold_0_8), + .Y16(out_Y_idft_0_8), + .X17(sum_Y_imag_hold_0_8), + .Y17(), + .X18(sum_Y_real_hold_0_9), + .Y18(out_Y_idft_0_9), + .X19(sum_Y_imag_hold_0_9), + .Y19(), + .X20(sum_Y_real_hold_0_10), + .Y20(out_Y_idft_0_10), + .X21(sum_Y_imag_hold_0_10), + .Y21(), + .X22(sum_Y_real_hold_0_11), + .Y22(out_Y_idft_0_11), + .X23(sum_Y_imag_hold_0_11), + .Y23(), + .X24(sum_Y_real_hold_0_12), + .Y24(out_Y_idft_0_12), + .X25(sum_Y_imag_hold_0_12), + .Y25(), + .X26(sum_Y_real_hold_0_13), + .Y26(out_Y_idft_0_13), + .X27(sum_Y_imag_hold_0_13), + .Y27(), + .X28(sum_Y_real_hold_0_14), + .Y28(out_Y_idft_0_14), + .X29(sum_Y_imag_hold_0_14), + .Y29(), + .X30(sum_Y_real_hold_0_15), + .Y30(out_Y_idft_0_15), + .X31(sum_Y_imag_hold_0_15), + .Y31(), + .next_out(idft_next_out_0) +); + +idft_16_top_18 idft_16_top_18_inst_mpxjranfek ( + .clk(clk), + .reset(reset), + .next(accum_valid_1), + .X0(sum_Y_real_hold_1_0), + .Y0(out_Y_idft_1_0), + .X1(sum_Y_imag_hold_1_0), + .Y1(), + .X2(sum_Y_real_hold_1_1), + .Y2(out_Y_idft_1_1), + .X3(sum_Y_imag_hold_1_1), + .Y3(), + .X4(sum_Y_real_hold_1_2), + .Y4(out_Y_idft_1_2), + .X5(sum_Y_imag_hold_1_2), + .Y5(), + .X6(sum_Y_real_hold_1_3), + .Y6(out_Y_idft_1_3), + .X7(sum_Y_imag_hold_1_3), + .Y7(), + .X8(sum_Y_real_hold_1_4), + .Y8(out_Y_idft_1_4), + .X9(sum_Y_imag_hold_1_4), + .Y9(), + .X10(sum_Y_real_hold_1_5), + .Y10(out_Y_idft_1_5), + .X11(sum_Y_imag_hold_1_5), + .Y11(), + .X12(sum_Y_real_hold_1_6), + .Y12(out_Y_idft_1_6), + .X13(sum_Y_imag_hold_1_6), + .Y13(), + .X14(sum_Y_real_hold_1_7), + .Y14(out_Y_idft_1_7), + .X15(sum_Y_imag_hold_1_7), + .Y15(), + .X16(sum_Y_real_hold_1_8), + .Y16(out_Y_idft_1_8), + .X17(sum_Y_imag_hold_1_8), + .Y17(), + .X18(sum_Y_real_hold_1_9), + .Y18(out_Y_idft_1_9), + .X19(sum_Y_imag_hold_1_9), + .Y19(), + .X20(sum_Y_real_hold_1_10), + .Y20(out_Y_idft_1_10), + .X21(sum_Y_imag_hold_1_10), + .Y21(), + .X22(sum_Y_real_hold_1_11), + .Y22(out_Y_idft_1_11), + .X23(sum_Y_imag_hold_1_11), + .Y23(), + .X24(sum_Y_real_hold_1_12), + .Y24(out_Y_idft_1_12), + .X25(sum_Y_imag_hold_1_12), + .Y25(), + .X26(sum_Y_real_hold_1_13), + .Y26(out_Y_idft_1_13), + .X27(sum_Y_imag_hold_1_13), + .Y27(), + .X28(sum_Y_real_hold_1_14), + .Y28(out_Y_idft_1_14), + .X29(sum_Y_imag_hold_1_14), + .Y29(), + .X30(sum_Y_real_hold_1_15), + .Y30(out_Y_idft_1_15), + .X31(sum_Y_imag_hold_1_15), + .Y31(), + .next_out(idft_next_out_1) +); + +idft_16_top_18 idft_16_top_18_inst_uojowphvri ( + .clk(clk), + .reset(reset), + .next(accum_valid_2), + .X0(sum_Y_real_hold_2_0), + .Y0(out_Y_idft_2_0), + .X1(sum_Y_imag_hold_2_0), + .Y1(), + .X2(sum_Y_real_hold_2_1), + .Y2(out_Y_idft_2_1), + .X3(sum_Y_imag_hold_2_1), + .Y3(), + .X4(sum_Y_real_hold_2_2), + .Y4(out_Y_idft_2_2), + .X5(sum_Y_imag_hold_2_2), + .Y5(), + .X6(sum_Y_real_hold_2_3), + .Y6(out_Y_idft_2_3), + .X7(sum_Y_imag_hold_2_3), + .Y7(), + .X8(sum_Y_real_hold_2_4), + .Y8(out_Y_idft_2_4), + .X9(sum_Y_imag_hold_2_4), + .Y9(), + .X10(sum_Y_real_hold_2_5), + .Y10(out_Y_idft_2_5), + .X11(sum_Y_imag_hold_2_5), + .Y11(), + .X12(sum_Y_real_hold_2_6), + .Y12(out_Y_idft_2_6), + .X13(sum_Y_imag_hold_2_6), + .Y13(), + .X14(sum_Y_real_hold_2_7), + .Y14(out_Y_idft_2_7), + .X15(sum_Y_imag_hold_2_7), + .Y15(), + .X16(sum_Y_real_hold_2_8), + .Y16(out_Y_idft_2_8), + .X17(sum_Y_imag_hold_2_8), + .Y17(), + .X18(sum_Y_real_hold_2_9), + .Y18(out_Y_idft_2_9), + .X19(sum_Y_imag_hold_2_9), + .Y19(), + .X20(sum_Y_real_hold_2_10), + .Y20(out_Y_idft_2_10), + .X21(sum_Y_imag_hold_2_10), + .Y21(), + .X22(sum_Y_real_hold_2_11), + .Y22(out_Y_idft_2_11), + .X23(sum_Y_imag_hold_2_11), + .Y23(), + .X24(sum_Y_real_hold_2_12), + .Y24(out_Y_idft_2_12), + .X25(sum_Y_imag_hold_2_12), + .Y25(), + .X26(sum_Y_real_hold_2_13), + .Y26(out_Y_idft_2_13), + .X27(sum_Y_imag_hold_2_13), + .Y27(), + .X28(sum_Y_real_hold_2_14), + .Y28(out_Y_idft_2_14), + .X29(sum_Y_imag_hold_2_14), + .Y29(), + .X30(sum_Y_real_hold_2_15), + .Y30(out_Y_idft_2_15), + .X31(sum_Y_imag_hold_2_15), + .Y31(), + .next_out(idft_next_out_2) +); + +always @ (posedge clk) begin + if (reset) begin + reg_Y_0_0 <= 0; + reg_Y_0_1 <= 0; + reg_Y_0_2 <= 0; + reg_Y_0_3 <= 0; + reg_Y_0_4 <= 0; + reg_Y_0_5 <= 0; + reg_Y_0_6 <= 0; + reg_Y_0_7 <= 0; + reg_Y_0_8 <= 0; + reg_Y_0_9 <= 0; + reg_Y_0_10 <= 0; + reg_Y_0_11 <= 0; + reg_Y_0_12 <= 0; + reg_Y_0_13 <= 0; + reg_Y_0_14 <= 0; + reg_Y_0_15 <= 0; + reg_Y_1_0 <= 0; + reg_Y_1_1 <= 0; + reg_Y_1_2 <= 0; + reg_Y_1_3 <= 0; + reg_Y_1_4 <= 0; + reg_Y_1_5 <= 0; + reg_Y_1_6 <= 0; + reg_Y_1_7 <= 0; + reg_Y_1_8 <= 0; + reg_Y_1_9 <= 0; + reg_Y_1_10 <= 0; + reg_Y_1_11 <= 0; + reg_Y_1_12 <= 0; + reg_Y_1_13 <= 0; + reg_Y_1_14 <= 0; + reg_Y_1_15 <= 0; + reg_Y_2_0 <= 0; + reg_Y_2_1 <= 0; + reg_Y_2_2 <= 0; + reg_Y_2_3 <= 0; + reg_Y_2_4 <= 0; + reg_Y_2_5 <= 0; + reg_Y_2_6 <= 0; + reg_Y_2_7 <= 0; + reg_Y_2_8 <= 0; + reg_Y_2_9 <= 0; + reg_Y_2_10 <= 0; + reg_Y_2_11 <= 0; + reg_Y_2_12 <= 0; + reg_Y_2_13 <= 0; + reg_Y_2_14 <= 0; + reg_Y_2_15 <= 0; + idft_out_valid <= 1'b0; + reg_o_valid <= 1'b0; + end else if (enable) begin + reg_Y_0_0 <= (out_Y_idft_0_0 >>> 4); + reg_Y_0_1 <= (out_Y_idft_0_1 >>> 4); + reg_Y_0_2 <= (out_Y_idft_0_2 >>> 4); + reg_Y_0_3 <= (out_Y_idft_0_3 >>> 4); + reg_Y_0_4 <= (out_Y_idft_0_4 >>> 4); + reg_Y_0_5 <= (out_Y_idft_0_5 >>> 4); + reg_Y_0_6 <= (out_Y_idft_0_6 >>> 4); + reg_Y_0_7 <= (out_Y_idft_0_7 >>> 4); + reg_Y_0_8 <= (out_Y_idft_0_8 >>> 4); + reg_Y_0_9 <= (out_Y_idft_0_9 >>> 4); + reg_Y_0_10 <= (out_Y_idft_0_10 >>> 4); + reg_Y_0_11 <= (out_Y_idft_0_11 >>> 4); + reg_Y_0_12 <= (out_Y_idft_0_12 >>> 4); + reg_Y_0_13 <= (out_Y_idft_0_13 >>> 4); + reg_Y_0_14 <= (out_Y_idft_0_14 >>> 4); + reg_Y_0_15 <= (out_Y_idft_0_15 >>> 4); + reg_Y_1_0 <= (out_Y_idft_1_0 >>> 4); + reg_Y_1_1 <= (out_Y_idft_1_1 >>> 4); + reg_Y_1_2 <= (out_Y_idft_1_2 >>> 4); + reg_Y_1_3 <= (out_Y_idft_1_3 >>> 4); + reg_Y_1_4 <= (out_Y_idft_1_4 >>> 4); + reg_Y_1_5 <= (out_Y_idft_1_5 >>> 4); + reg_Y_1_6 <= (out_Y_idft_1_6 >>> 4); + reg_Y_1_7 <= (out_Y_idft_1_7 >>> 4); + reg_Y_1_8 <= (out_Y_idft_1_8 >>> 4); + reg_Y_1_9 <= (out_Y_idft_1_9 >>> 4); + reg_Y_1_10 <= (out_Y_idft_1_10 >>> 4); + reg_Y_1_11 <= (out_Y_idft_1_11 >>> 4); + reg_Y_1_12 <= (out_Y_idft_1_12 >>> 4); + reg_Y_1_13 <= (out_Y_idft_1_13 >>> 4); + reg_Y_1_14 <= (out_Y_idft_1_14 >>> 4); + reg_Y_1_15 <= (out_Y_idft_1_15 >>> 4); + reg_Y_2_0 <= (out_Y_idft_2_0 >>> 4); + reg_Y_2_1 <= (out_Y_idft_2_1 >>> 4); + reg_Y_2_2 <= (out_Y_idft_2_2 >>> 4); + reg_Y_2_3 <= (out_Y_idft_2_3 >>> 4); + reg_Y_2_4 <= (out_Y_idft_2_4 >>> 4); + reg_Y_2_5 <= (out_Y_idft_2_5 >>> 4); + reg_Y_2_6 <= (out_Y_idft_2_6 >>> 4); + reg_Y_2_7 <= (out_Y_idft_2_7 >>> 4); + reg_Y_2_8 <= (out_Y_idft_2_8 >>> 4); + reg_Y_2_9 <= (out_Y_idft_2_9 >>> 4); + reg_Y_2_10 <= (out_Y_idft_2_10 >>> 4); + reg_Y_2_11 <= (out_Y_idft_2_11 >>> 4); + reg_Y_2_12 <= (out_Y_idft_2_12 >>> 4); + reg_Y_2_13 <= (out_Y_idft_2_13 >>> 4); + reg_Y_2_14 <= (out_Y_idft_2_14 >>> 4); + reg_Y_2_15 <= (out_Y_idft_2_15 >>> 4); + idft_out_valid <= idft_next_out_0; + reg_o_valid <= idft_out_valid; + end +end + +assign o_valid = enable & reg_o_valid; +assign o_ready = matrix_vec_mult_ready; +assign o_Y_0_0 = reg_Y_0_0; +assign o_Y_0_1 = reg_Y_0_1; +assign o_Y_0_2 = reg_Y_0_2; +assign o_Y_0_3 = reg_Y_0_3; +assign o_Y_0_4 = reg_Y_0_4; +assign o_Y_0_5 = reg_Y_0_5; +assign o_Y_0_6 = reg_Y_0_6; +assign o_Y_0_7 = reg_Y_0_7; +assign o_Y_0_8 = reg_Y_0_8; +assign o_Y_0_9 = reg_Y_0_9; +assign o_Y_0_10 = reg_Y_0_10; +assign o_Y_0_11 = reg_Y_0_11; +assign o_Y_0_12 = reg_Y_0_12; +assign o_Y_0_13 = reg_Y_0_13; +assign o_Y_0_14 = reg_Y_0_14; +assign o_Y_0_15 = reg_Y_0_15; +assign o_Y_1_0 = reg_Y_1_0; +assign o_Y_1_1 = reg_Y_1_1; +assign o_Y_1_2 = reg_Y_1_2; +assign o_Y_1_3 = reg_Y_1_3; +assign o_Y_1_4 = reg_Y_1_4; +assign o_Y_1_5 = reg_Y_1_5; +assign o_Y_1_6 = reg_Y_1_6; +assign o_Y_1_7 = reg_Y_1_7; +assign o_Y_1_8 = reg_Y_1_8; +assign o_Y_1_9 = reg_Y_1_9; +assign o_Y_1_10 = reg_Y_1_10; +assign o_Y_1_11 = reg_Y_1_11; +assign o_Y_1_12 = reg_Y_1_12; +assign o_Y_1_13 = reg_Y_1_13; +assign o_Y_1_14 = reg_Y_1_14; +assign o_Y_1_15 = reg_Y_1_15; +assign o_Y_2_0 = reg_Y_2_0; +assign o_Y_2_1 = reg_Y_2_1; +assign o_Y_2_2 = reg_Y_2_2; +assign o_Y_2_3 = reg_Y_2_3; +assign o_Y_2_4 = reg_Y_2_4; +assign o_Y_2_5 = reg_Y_2_5; +assign o_Y_2_6 = reg_Y_2_6; +assign o_Y_2_7 = reg_Y_2_7; +assign o_Y_2_8 = reg_Y_2_8; +assign o_Y_2_9 = reg_Y_2_9; +assign o_Y_2_10 = reg_Y_2_10; +assign o_Y_2_11 = reg_Y_2_11; +assign o_Y_2_12 = reg_Y_2_12; +assign o_Y_2_13 = reg_Y_2_13; +assign o_Y_2_14 = reg_Y_2_14; +assign o_Y_2_15 = reg_Y_2_15; + +endmodule + +module c_matrix_vec_mult_core_18_10_16_3_1 ( + input clk, + input reset, + input i_ready, + input i_valid, + input [17:0] i_X_0, + input [17:0] i_X_1, + input [17:0] i_X_2, + input [17:0] i_X_3, + input [17:0] i_X_4, + input [17:0] i_X_5, + input [17:0] i_X_6, + input [17:0] i_X_7, + input [17:0] i_X_8, + input [17:0] i_X_9, + input [17:0] i_X_10, + input [17:0] i_X_11, + input [17:0] i_X_12, + input [17:0] i_X_13, + input [17:0] i_X_14, + input [17:0] i_X_15, + input [17:0] i_W_real_0_0, + input [17:0] i_W_imag_0_0, + input [17:0] i_W_real_0_1, + input [17:0] i_W_imag_0_1, + input [17:0] i_W_real_0_2, + input [17:0] i_W_imag_0_2, + input [17:0] i_W_real_0_3, + input [17:0] i_W_imag_0_3, + input [17:0] i_W_real_0_4, + input [17:0] i_W_imag_0_4, + input [17:0] i_W_real_0_5, + input [17:0] i_W_imag_0_5, + input [17:0] i_W_real_0_6, + input [17:0] i_W_imag_0_6, + input [17:0] i_W_real_0_7, + input [17:0] i_W_imag_0_7, + input [17:0] i_W_real_0_8, + input [17:0] i_W_imag_0_8, + input [17:0] i_W_real_1_0, + input [17:0] i_W_imag_1_0, + input [17:0] i_W_real_1_1, + input [17:0] i_W_imag_1_1, + input [17:0] i_W_real_1_2, + input [17:0] i_W_imag_1_2, + input [17:0] i_W_real_1_3, + input [17:0] i_W_imag_1_3, + input [17:0] i_W_real_1_4, + input [17:0] i_W_imag_1_4, + input [17:0] i_W_real_1_5, + input [17:0] i_W_imag_1_5, + input [17:0] i_W_real_1_6, + input [17:0] i_W_imag_1_6, + input [17:0] i_W_real_1_7, + input [17:0] i_W_imag_1_7, + input [17:0] i_W_real_1_8, + input [17:0] i_W_imag_1_8, + input [17:0] i_W_real_2_0, + input [17:0] i_W_imag_2_0, + input [17:0] i_W_real_2_1, + input [17:0] i_W_imag_2_1, + input [17:0] i_W_real_2_2, + input [17:0] i_W_imag_2_2, + input [17:0] i_W_real_2_3, + input [17:0] i_W_imag_2_3, + input [17:0] i_W_real_2_4, + input [17:0] i_W_imag_2_4, + input [17:0] i_W_real_2_5, + input [17:0] i_W_imag_2_5, + input [17:0] i_W_real_2_6, + input [17:0] i_W_imag_2_6, + input [17:0] i_W_real_2_7, + input [17:0] i_W_imag_2_7, + input [17:0] i_W_real_2_8, + input [17:0] i_W_imag_2_8, + output [17:0] o_Y_real_0_0, + output [17:0] o_Y_imag_0_0, + output [17:0] o_Y_real_0_1, + output [17:0] o_Y_imag_0_1, + output [17:0] o_Y_real_0_2, + output [17:0] o_Y_imag_0_2, + output [17:0] o_Y_real_0_3, + output [17:0] o_Y_imag_0_3, + output [17:0] o_Y_real_0_4, + output [17:0] o_Y_imag_0_4, + output [17:0] o_Y_real_0_5, + output [17:0] o_Y_imag_0_5, + output [17:0] o_Y_real_0_6, + output [17:0] o_Y_imag_0_6, + output [17:0] o_Y_real_0_7, + output [17:0] o_Y_imag_0_7, + output [17:0] o_Y_real_0_8, + output [17:0] o_Y_imag_0_8, + output [17:0] o_Y_real_0_9, + output [17:0] o_Y_imag_0_9, + output [17:0] o_Y_real_0_10, + output [17:0] o_Y_imag_0_10, + output [17:0] o_Y_real_0_11, + output [17:0] o_Y_imag_0_11, + output [17:0] o_Y_real_0_12, + output [17:0] o_Y_imag_0_12, + output [17:0] o_Y_real_0_13, + output [17:0] o_Y_imag_0_13, + output [17:0] o_Y_real_0_14, + output [17:0] o_Y_imag_0_14, + output [17:0] o_Y_real_0_15, + output [17:0] o_Y_imag_0_15, + output [17:0] o_Y_real_1_0, + output [17:0] o_Y_imag_1_0, + output [17:0] o_Y_real_1_1, + output [17:0] o_Y_imag_1_1, + output [17:0] o_Y_real_1_2, + output [17:0] o_Y_imag_1_2, + output [17:0] o_Y_real_1_3, + output [17:0] o_Y_imag_1_3, + output [17:0] o_Y_real_1_4, + output [17:0] o_Y_imag_1_4, + output [17:0] o_Y_real_1_5, + output [17:0] o_Y_imag_1_5, + output [17:0] o_Y_real_1_6, + output [17:0] o_Y_imag_1_6, + output [17:0] o_Y_real_1_7, + output [17:0] o_Y_imag_1_7, + output [17:0] o_Y_real_1_8, + output [17:0] o_Y_imag_1_8, + output [17:0] o_Y_real_1_9, + output [17:0] o_Y_imag_1_9, + output [17:0] o_Y_real_1_10, + output [17:0] o_Y_imag_1_10, + output [17:0] o_Y_real_1_11, + output [17:0] o_Y_imag_1_11, + output [17:0] o_Y_real_1_12, + output [17:0] o_Y_imag_1_12, + output [17:0] o_Y_real_1_13, + output [17:0] o_Y_imag_1_13, + output [17:0] o_Y_real_1_14, + output [17:0] o_Y_imag_1_14, + output [17:0] o_Y_real_1_15, + output [17:0] o_Y_imag_1_15, + output [17:0] o_Y_real_2_0, + output [17:0] o_Y_imag_2_0, + output [17:0] o_Y_real_2_1, + output [17:0] o_Y_imag_2_1, + output [17:0] o_Y_real_2_2, + output [17:0] o_Y_imag_2_2, + output [17:0] o_Y_real_2_3, + output [17:0] o_Y_imag_2_3, + output [17:0] o_Y_real_2_4, + output [17:0] o_Y_imag_2_4, + output [17:0] o_Y_real_2_5, + output [17:0] o_Y_imag_2_5, + output [17:0] o_Y_real_2_6, + output [17:0] o_Y_imag_2_6, + output [17:0] o_Y_real_2_7, + output [17:0] o_Y_imag_2_7, + output [17:0] o_Y_real_2_8, + output [17:0] o_Y_imag_2_8, + output [17:0] o_Y_real_2_9, + output [17:0] o_Y_imag_2_9, + output [17:0] o_Y_real_2_10, + output [17:0] o_Y_imag_2_10, + output [17:0] o_Y_real_2_11, + output [17:0] o_Y_imag_2_11, + output [17:0] o_Y_real_2_12, + output [17:0] o_Y_imag_2_12, + output [17:0] o_Y_real_2_13, + output [17:0] o_Y_imag_2_13, + output [17:0] o_Y_real_2_14, + output [17:0] o_Y_imag_2_14, + output [17:0] o_Y_real_2_15, + output [17:0] o_Y_imag_2_15, + output o_ready, + output o_valid +); + +// Enable whenever reciever is ready +wire enable; +assign enable = i_ready; +// Register the inputs +reg [17:0] reg_X_0; +reg [17:0] reg_X_2_0; +reg [17:0] reg_X_1; +reg [17:0] reg_X_2_1; +reg [17:0] reg_X_2; +reg [17:0] reg_X_2_2; +reg [17:0] reg_X_3; +reg [17:0] reg_X_2_3; +reg [17:0] reg_X_4; +reg [17:0] reg_X_2_4; +reg [17:0] reg_X_5; +reg [17:0] reg_X_2_5; +reg [17:0] reg_X_6; +reg [17:0] reg_X_2_6; +reg [17:0] reg_X_7; +reg [17:0] reg_X_2_7; +reg [17:0] reg_X_8; +reg [17:0] reg_X_2_8; +reg [17:0] reg_X_9; +reg [17:0] reg_X_2_9; +reg [17:0] reg_X_10; +reg [17:0] reg_X_2_10; +reg [17:0] reg_X_11; +reg [17:0] reg_X_2_11; +reg [17:0] reg_X_12; +reg [17:0] reg_X_2_12; +reg [17:0] reg_X_13; +reg [17:0] reg_X_2_13; +reg [17:0] reg_X_14; +reg [17:0] reg_X_2_14; +reg [17:0] reg_X_15; +reg [17:0] reg_X_2_15; +reg [17:0] reg_W_real_0_0; +reg [17:0] reg_W_imag_0_0; +reg [17:0] reg_W_real_0_1; +reg [17:0] reg_W_imag_0_1; +reg [17:0] reg_W_real_0_2; +reg [17:0] reg_W_imag_0_2; +reg [17:0] reg_W_real_0_3; +reg [17:0] reg_W_imag_0_3; +reg [17:0] reg_W_real_0_4; +reg [17:0] reg_W_imag_0_4; +reg [17:0] reg_W_real_0_5; +reg [17:0] reg_W_imag_0_5; +reg [17:0] reg_W_real_0_6; +reg [17:0] reg_W_imag_0_6; +reg [17:0] reg_W_real_0_7; +reg [17:0] reg_W_imag_0_7; +reg [17:0] reg_W_real_0_8; +reg [17:0] reg_W_imag_0_8; +reg [17:0] reg_W_real_1_0; +reg [17:0] reg_W_imag_1_0; +reg [17:0] reg_W_real_1_1; +reg [17:0] reg_W_imag_1_1; +reg [17:0] reg_W_real_1_2; +reg [17:0] reg_W_imag_1_2; +reg [17:0] reg_W_real_1_3; +reg [17:0] reg_W_imag_1_3; +reg [17:0] reg_W_real_1_4; +reg [17:0] reg_W_imag_1_4; +reg [17:0] reg_W_real_1_5; +reg [17:0] reg_W_imag_1_5; +reg [17:0] reg_W_real_1_6; +reg [17:0] reg_W_imag_1_6; +reg [17:0] reg_W_real_1_7; +reg [17:0] reg_W_imag_1_7; +reg [17:0] reg_W_real_1_8; +reg [17:0] reg_W_imag_1_8; +reg [17:0] reg_W_real_2_0; +reg [17:0] reg_W_imag_2_0; +reg [17:0] reg_W_real_2_1; +reg [17:0] reg_W_imag_2_1; +reg [17:0] reg_W_real_2_2; +reg [17:0] reg_W_imag_2_2; +reg [17:0] reg_W_real_2_3; +reg [17:0] reg_W_imag_2_3; +reg [17:0] reg_W_real_2_4; +reg [17:0] reg_W_imag_2_4; +reg [17:0] reg_W_real_2_5; +reg [17:0] reg_W_imag_2_5; +reg [17:0] reg_W_real_2_6; +reg [17:0] reg_W_imag_2_6; +reg [17:0] reg_W_real_2_7; +reg [17:0] reg_W_imag_2_7; +reg [17:0] reg_W_real_2_8; +reg [17:0] reg_W_imag_2_8; +reg reg_i_valid; + +// Register the outputs +reg [17:0] reg_Y_real_0_0; +reg [17:0] reg_Y_imag_0_0; +reg [17:0] reg_Y_real_0_1; +reg [17:0] reg_Y_imag_0_1; +reg [17:0] reg_Y_real_0_2; +reg [17:0] reg_Y_imag_0_2; +reg [17:0] reg_Y_real_0_3; +reg [17:0] reg_Y_imag_0_3; +reg [17:0] reg_Y_real_0_4; +reg [17:0] reg_Y_imag_0_4; +reg [17:0] reg_Y_real_0_5; +reg [17:0] reg_Y_imag_0_5; +reg [17:0] reg_Y_real_0_6; +reg [17:0] reg_Y_imag_0_6; +reg [17:0] reg_Y_real_0_7; +reg [17:0] reg_Y_imag_0_7; +reg [17:0] reg_Y_real_0_8; +reg [17:0] reg_Y_imag_0_8; +reg [17:0] reg_Y_real_0_9; +reg [17:0] reg_Y_imag_0_9; +reg [17:0] reg_Y_real_0_10; +reg [17:0] reg_Y_imag_0_10; +reg [17:0] reg_Y_real_0_11; +reg [17:0] reg_Y_imag_0_11; +reg [17:0] reg_Y_real_0_12; +reg [17:0] reg_Y_imag_0_12; +reg [17:0] reg_Y_real_0_13; +reg [17:0] reg_Y_imag_0_13; +reg [17:0] reg_Y_real_0_14; +reg [17:0] reg_Y_imag_0_14; +reg [17:0] reg_Y_real_0_15; +reg [17:0] reg_Y_imag_0_15; +reg [17:0] reg_Y_real_1_0; +reg [17:0] reg_Y_imag_1_0; +reg [17:0] reg_Y_real_1_1; +reg [17:0] reg_Y_imag_1_1; +reg [17:0] reg_Y_real_1_2; +reg [17:0] reg_Y_imag_1_2; +reg [17:0] reg_Y_real_1_3; +reg [17:0] reg_Y_imag_1_3; +reg [17:0] reg_Y_real_1_4; +reg [17:0] reg_Y_imag_1_4; +reg [17:0] reg_Y_real_1_5; +reg [17:0] reg_Y_imag_1_5; +reg [17:0] reg_Y_real_1_6; +reg [17:0] reg_Y_imag_1_6; +reg [17:0] reg_Y_real_1_7; +reg [17:0] reg_Y_imag_1_7; +reg [17:0] reg_Y_real_1_8; +reg [17:0] reg_Y_imag_1_8; +reg [17:0] reg_Y_real_1_9; +reg [17:0] reg_Y_imag_1_9; +reg [17:0] reg_Y_real_1_10; +reg [17:0] reg_Y_imag_1_10; +reg [17:0] reg_Y_real_1_11; +reg [17:0] reg_Y_imag_1_11; +reg [17:0] reg_Y_real_1_12; +reg [17:0] reg_Y_imag_1_12; +reg [17:0] reg_Y_real_1_13; +reg [17:0] reg_Y_imag_1_13; +reg [17:0] reg_Y_real_1_14; +reg [17:0] reg_Y_imag_1_14; +reg [17:0] reg_Y_real_1_15; +reg [17:0] reg_Y_imag_1_15; +reg [17:0] reg_Y_real_2_0; +reg [17:0] reg_Y_imag_2_0; +reg [17:0] reg_Y_real_2_1; +reg [17:0] reg_Y_imag_2_1; +reg [17:0] reg_Y_real_2_2; +reg [17:0] reg_Y_imag_2_2; +reg [17:0] reg_Y_real_2_3; +reg [17:0] reg_Y_imag_2_3; +reg [17:0] reg_Y_real_2_4; +reg [17:0] reg_Y_imag_2_4; +reg [17:0] reg_Y_real_2_5; +reg [17:0] reg_Y_imag_2_5; +reg [17:0] reg_Y_real_2_6; +reg [17:0] reg_Y_imag_2_6; +reg [17:0] reg_Y_real_2_7; +reg [17:0] reg_Y_imag_2_7; +reg [17:0] reg_Y_real_2_8; +reg [17:0] reg_Y_imag_2_8; +reg [17:0] reg_Y_real_2_9; +reg [17:0] reg_Y_imag_2_9; +reg [17:0] reg_Y_real_2_10; +reg [17:0] reg_Y_imag_2_10; +reg [17:0] reg_Y_real_2_11; +reg [17:0] reg_Y_imag_2_11; +reg [17:0] reg_Y_real_2_12; +reg [17:0] reg_Y_imag_2_12; +reg [17:0] reg_Y_real_2_13; +reg [17:0] reg_Y_imag_2_13; +reg [17:0] reg_Y_real_2_14; +reg [17:0] reg_Y_imag_2_14; +reg [17:0] reg_Y_real_2_15; +reg [17:0] reg_Y_imag_2_15; +reg reg_o_valid; + +// Inter-connections +reg fft_valid; +reg reg_o_ready; +wire o_fft_next; +wire mult_X_real_W_real_valid_0; +wire mult_X_imag_W_real_valid_0; +wire mult_X_real_W_imag_valid_0; +wire mult_X_imag_W_imag_valid_0; +wire sub_y_real_valid_0; +wire add_y_imag_valid_0; +wire mult_X_real_W_real_valid_1; +wire mult_X_imag_W_real_valid_1; +wire mult_X_real_W_imag_valid_1; +wire mult_X_imag_W_imag_valid_1; +wire sub_y_real_valid_1; +wire add_y_imag_valid_1; +wire mult_X_real_W_real_valid_2; +wire mult_X_imag_W_real_valid_2; +wire mult_X_real_W_imag_valid_2; +wire mult_X_imag_W_imag_valid_2; +wire sub_y_real_valid_2; +wire add_y_imag_valid_2; + +wire [17:0] W_real_wires_0_0; +wire [17:0] W_imag_wires_0_0; +wire [17:0] W_real_holder_0_0; +wire [17:0] W_imag_holder_0_0; +wire [17:0] o_mult_X_real_W_real_0_0; +wire [17:0] o_mult_X_imag_W_real_0_0; +wire [17:0] o_mult_X_real_W_imag_0_0; +wire [17:0] o_mult_X_imag_W_imag_0_0; +wire [17:0] o_sub_y_real_0_0; +wire [17:0] o_add_y_imag_0_0; +wire [17:0] W_real_wires_0_1; +wire [17:0] W_imag_wires_0_1; +wire [17:0] W_real_holder_0_1; +wire [17:0] W_imag_holder_0_1; +wire [17:0] o_mult_X_real_W_real_0_1; +wire [17:0] o_mult_X_imag_W_real_0_1; +wire [17:0] o_mult_X_real_W_imag_0_1; +wire [17:0] o_mult_X_imag_W_imag_0_1; +wire [17:0] o_sub_y_real_0_1; +wire [17:0] o_add_y_imag_0_1; +wire [17:0] W_real_wires_0_2; +wire [17:0] W_imag_wires_0_2; +wire [17:0] W_real_holder_0_2; +wire [17:0] W_imag_holder_0_2; +wire [17:0] o_mult_X_real_W_real_0_2; +wire [17:0] o_mult_X_imag_W_real_0_2; +wire [17:0] o_mult_X_real_W_imag_0_2; +wire [17:0] o_mult_X_imag_W_imag_0_2; +wire [17:0] o_sub_y_real_0_2; +wire [17:0] o_add_y_imag_0_2; +wire [17:0] W_real_wires_0_3; +wire [17:0] W_imag_wires_0_3; +wire [17:0] W_real_holder_0_3; +wire [17:0] W_imag_holder_0_3; +wire [17:0] o_mult_X_real_W_real_0_3; +wire [17:0] o_mult_X_imag_W_real_0_3; +wire [17:0] o_mult_X_real_W_imag_0_3; +wire [17:0] o_mult_X_imag_W_imag_0_3; +wire [17:0] o_sub_y_real_0_3; +wire [17:0] o_add_y_imag_0_3; +wire [17:0] W_real_wires_0_4; +wire [17:0] W_imag_wires_0_4; +wire [17:0] W_real_holder_0_4; +wire [17:0] W_imag_holder_0_4; +wire [17:0] o_mult_X_real_W_real_0_4; +wire [17:0] o_mult_X_imag_W_real_0_4; +wire [17:0] o_mult_X_real_W_imag_0_4; +wire [17:0] o_mult_X_imag_W_imag_0_4; +wire [17:0] o_sub_y_real_0_4; +wire [17:0] o_add_y_imag_0_4; +wire [17:0] W_real_wires_0_5; +wire [17:0] W_imag_wires_0_5; +wire [17:0] W_real_holder_0_5; +wire [17:0] W_imag_holder_0_5; +wire [17:0] o_mult_X_real_W_real_0_5; +wire [17:0] o_mult_X_imag_W_real_0_5; +wire [17:0] o_mult_X_real_W_imag_0_5; +wire [17:0] o_mult_X_imag_W_imag_0_5; +wire [17:0] o_sub_y_real_0_5; +wire [17:0] o_add_y_imag_0_5; +wire [17:0] W_real_wires_0_6; +wire [17:0] W_imag_wires_0_6; +wire [17:0] W_real_holder_0_6; +wire [17:0] W_imag_holder_0_6; +wire [17:0] o_mult_X_real_W_real_0_6; +wire [17:0] o_mult_X_imag_W_real_0_6; +wire [17:0] o_mult_X_real_W_imag_0_6; +wire [17:0] o_mult_X_imag_W_imag_0_6; +wire [17:0] o_sub_y_real_0_6; +wire [17:0] o_add_y_imag_0_6; +wire [17:0] W_real_wires_0_7; +wire [17:0] W_imag_wires_0_7; +wire [17:0] W_real_holder_0_7; +wire [17:0] W_imag_holder_0_7; +wire [17:0] o_mult_X_real_W_real_0_7; +wire [17:0] o_mult_X_imag_W_real_0_7; +wire [17:0] o_mult_X_real_W_imag_0_7; +wire [17:0] o_mult_X_imag_W_imag_0_7; +wire [17:0] o_sub_y_real_0_7; +wire [17:0] o_add_y_imag_0_7; +wire [17:0] W_real_wires_0_8; +wire [17:0] W_imag_wires_0_8; +wire [17:0] W_real_holder_0_8; +wire [17:0] W_imag_holder_0_8; +wire [17:0] o_mult_X_real_W_real_0_8; +wire [17:0] o_mult_X_imag_W_real_0_8; +wire [17:0] o_mult_X_real_W_imag_0_8; +wire [17:0] o_mult_X_imag_W_imag_0_8; +wire [17:0] o_sub_y_real_0_8; +wire [17:0] o_add_y_imag_0_8; +wire [17:0] W_real_wires_1_0; +wire [17:0] W_imag_wires_1_0; +wire [17:0] W_real_holder_1_0; +wire [17:0] W_imag_holder_1_0; +wire [17:0] o_mult_X_real_W_real_1_0; +wire [17:0] o_mult_X_imag_W_real_1_0; +wire [17:0] o_mult_X_real_W_imag_1_0; +wire [17:0] o_mult_X_imag_W_imag_1_0; +wire [17:0] o_sub_y_real_1_0; +wire [17:0] o_add_y_imag_1_0; +wire [17:0] W_real_wires_1_1; +wire [17:0] W_imag_wires_1_1; +wire [17:0] W_real_holder_1_1; +wire [17:0] W_imag_holder_1_1; +wire [17:0] o_mult_X_real_W_real_1_1; +wire [17:0] o_mult_X_imag_W_real_1_1; +wire [17:0] o_mult_X_real_W_imag_1_1; +wire [17:0] o_mult_X_imag_W_imag_1_1; +wire [17:0] o_sub_y_real_1_1; +wire [17:0] o_add_y_imag_1_1; +wire [17:0] W_real_wires_1_2; +wire [17:0] W_imag_wires_1_2; +wire [17:0] W_real_holder_1_2; +wire [17:0] W_imag_holder_1_2; +wire [17:0] o_mult_X_real_W_real_1_2; +wire [17:0] o_mult_X_imag_W_real_1_2; +wire [17:0] o_mult_X_real_W_imag_1_2; +wire [17:0] o_mult_X_imag_W_imag_1_2; +wire [17:0] o_sub_y_real_1_2; +wire [17:0] o_add_y_imag_1_2; +wire [17:0] W_real_wires_1_3; +wire [17:0] W_imag_wires_1_3; +wire [17:0] W_real_holder_1_3; +wire [17:0] W_imag_holder_1_3; +wire [17:0] o_mult_X_real_W_real_1_3; +wire [17:0] o_mult_X_imag_W_real_1_3; +wire [17:0] o_mult_X_real_W_imag_1_3; +wire [17:0] o_mult_X_imag_W_imag_1_3; +wire [17:0] o_sub_y_real_1_3; +wire [17:0] o_add_y_imag_1_3; +wire [17:0] W_real_wires_1_4; +wire [17:0] W_imag_wires_1_4; +wire [17:0] W_real_holder_1_4; +wire [17:0] W_imag_holder_1_4; +wire [17:0] o_mult_X_real_W_real_1_4; +wire [17:0] o_mult_X_imag_W_real_1_4; +wire [17:0] o_mult_X_real_W_imag_1_4; +wire [17:0] o_mult_X_imag_W_imag_1_4; +wire [17:0] o_sub_y_real_1_4; +wire [17:0] o_add_y_imag_1_4; +wire [17:0] W_real_wires_1_5; +wire [17:0] W_imag_wires_1_5; +wire [17:0] W_real_holder_1_5; +wire [17:0] W_imag_holder_1_5; +wire [17:0] o_mult_X_real_W_real_1_5; +wire [17:0] o_mult_X_imag_W_real_1_5; +wire [17:0] o_mult_X_real_W_imag_1_5; +wire [17:0] o_mult_X_imag_W_imag_1_5; +wire [17:0] o_sub_y_real_1_5; +wire [17:0] o_add_y_imag_1_5; +wire [17:0] W_real_wires_1_6; +wire [17:0] W_imag_wires_1_6; +wire [17:0] W_real_holder_1_6; +wire [17:0] W_imag_holder_1_6; +wire [17:0] o_mult_X_real_W_real_1_6; +wire [17:0] o_mult_X_imag_W_real_1_6; +wire [17:0] o_mult_X_real_W_imag_1_6; +wire [17:0] o_mult_X_imag_W_imag_1_6; +wire [17:0] o_sub_y_real_1_6; +wire [17:0] o_add_y_imag_1_6; +wire [17:0] W_real_wires_1_7; +wire [17:0] W_imag_wires_1_7; +wire [17:0] W_real_holder_1_7; +wire [17:0] W_imag_holder_1_7; +wire [17:0] o_mult_X_real_W_real_1_7; +wire [17:0] o_mult_X_imag_W_real_1_7; +wire [17:0] o_mult_X_real_W_imag_1_7; +wire [17:0] o_mult_X_imag_W_imag_1_7; +wire [17:0] o_sub_y_real_1_7; +wire [17:0] o_add_y_imag_1_7; +wire [17:0] W_real_wires_1_8; +wire [17:0] W_imag_wires_1_8; +wire [17:0] W_real_holder_1_8; +wire [17:0] W_imag_holder_1_8; +wire [17:0] o_mult_X_real_W_real_1_8; +wire [17:0] o_mult_X_imag_W_real_1_8; +wire [17:0] o_mult_X_real_W_imag_1_8; +wire [17:0] o_mult_X_imag_W_imag_1_8; +wire [17:0] o_sub_y_real_1_8; +wire [17:0] o_add_y_imag_1_8; +wire [17:0] W_real_wires_2_0; +wire [17:0] W_imag_wires_2_0; +wire [17:0] W_real_holder_2_0; +wire [17:0] W_imag_holder_2_0; +wire [17:0] o_mult_X_real_W_real_2_0; +wire [17:0] o_mult_X_imag_W_real_2_0; +wire [17:0] o_mult_X_real_W_imag_2_0; +wire [17:0] o_mult_X_imag_W_imag_2_0; +wire [17:0] o_sub_y_real_2_0; +wire [17:0] o_add_y_imag_2_0; +wire [17:0] W_real_wires_2_1; +wire [17:0] W_imag_wires_2_1; +wire [17:0] W_real_holder_2_1; +wire [17:0] W_imag_holder_2_1; +wire [17:0] o_mult_X_real_W_real_2_1; +wire [17:0] o_mult_X_imag_W_real_2_1; +wire [17:0] o_mult_X_real_W_imag_2_1; +wire [17:0] o_mult_X_imag_W_imag_2_1; +wire [17:0] o_sub_y_real_2_1; +wire [17:0] o_add_y_imag_2_1; +wire [17:0] W_real_wires_2_2; +wire [17:0] W_imag_wires_2_2; +wire [17:0] W_real_holder_2_2; +wire [17:0] W_imag_holder_2_2; +wire [17:0] o_mult_X_real_W_real_2_2; +wire [17:0] o_mult_X_imag_W_real_2_2; +wire [17:0] o_mult_X_real_W_imag_2_2; +wire [17:0] o_mult_X_imag_W_imag_2_2; +wire [17:0] o_sub_y_real_2_2; +wire [17:0] o_add_y_imag_2_2; +wire [17:0] W_real_wires_2_3; +wire [17:0] W_imag_wires_2_3; +wire [17:0] W_real_holder_2_3; +wire [17:0] W_imag_holder_2_3; +wire [17:0] o_mult_X_real_W_real_2_3; +wire [17:0] o_mult_X_imag_W_real_2_3; +wire [17:0] o_mult_X_real_W_imag_2_3; +wire [17:0] o_mult_X_imag_W_imag_2_3; +wire [17:0] o_sub_y_real_2_3; +wire [17:0] o_add_y_imag_2_3; +wire [17:0] W_real_wires_2_4; +wire [17:0] W_imag_wires_2_4; +wire [17:0] W_real_holder_2_4; +wire [17:0] W_imag_holder_2_4; +wire [17:0] o_mult_X_real_W_real_2_4; +wire [17:0] o_mult_X_imag_W_real_2_4; +wire [17:0] o_mult_X_real_W_imag_2_4; +wire [17:0] o_mult_X_imag_W_imag_2_4; +wire [17:0] o_sub_y_real_2_4; +wire [17:0] o_add_y_imag_2_4; +wire [17:0] W_real_wires_2_5; +wire [17:0] W_imag_wires_2_5; +wire [17:0] W_real_holder_2_5; +wire [17:0] W_imag_holder_2_5; +wire [17:0] o_mult_X_real_W_real_2_5; +wire [17:0] o_mult_X_imag_W_real_2_5; +wire [17:0] o_mult_X_real_W_imag_2_5; +wire [17:0] o_mult_X_imag_W_imag_2_5; +wire [17:0] o_sub_y_real_2_5; +wire [17:0] o_add_y_imag_2_5; +wire [17:0] W_real_wires_2_6; +wire [17:0] W_imag_wires_2_6; +wire [17:0] W_real_holder_2_6; +wire [17:0] W_imag_holder_2_6; +wire [17:0] o_mult_X_real_W_real_2_6; +wire [17:0] o_mult_X_imag_W_real_2_6; +wire [17:0] o_mult_X_real_W_imag_2_6; +wire [17:0] o_mult_X_imag_W_imag_2_6; +wire [17:0] o_sub_y_real_2_6; +wire [17:0] o_add_y_imag_2_6; +wire [17:0] W_real_wires_2_7; +wire [17:0] W_imag_wires_2_7; +wire [17:0] W_real_holder_2_7; +wire [17:0] W_imag_holder_2_7; +wire [17:0] o_mult_X_real_W_real_2_7; +wire [17:0] o_mult_X_imag_W_real_2_7; +wire [17:0] o_mult_X_real_W_imag_2_7; +wire [17:0] o_mult_X_imag_W_imag_2_7; +wire [17:0] o_sub_y_real_2_7; +wire [17:0] o_add_y_imag_2_7; +wire [17:0] W_real_wires_2_8; +wire [17:0] W_imag_wires_2_8; +wire [17:0] W_real_holder_2_8; +wire [17:0] W_imag_holder_2_8; +wire [17:0] o_mult_X_real_W_real_2_8; +wire [17:0] o_mult_X_imag_W_real_2_8; +wire [17:0] o_mult_X_real_W_imag_2_8; +wire [17:0] o_mult_X_imag_W_imag_2_8; +wire [17:0] o_sub_y_real_2_8; +wire [17:0] o_add_y_imag_2_8; +wire [17:0] o_fft_X_real_0; +wire [17:0] o_fft_X_imag_0; +wire [17:0] o_fft_X_real_1; +wire [17:0] o_fft_X_imag_1; +wire [17:0] o_fft_X_real_2; +wire [17:0] o_fft_X_imag_2; +wire [17:0] o_fft_X_real_3; +wire [17:0] o_fft_X_imag_3; +wire [17:0] o_fft_X_real_4; +wire [17:0] o_fft_X_imag_4; +wire [17:0] o_fft_X_real_5; +wire [17:0] o_fft_X_imag_5; +wire [17:0] o_fft_X_real_6; +wire [17:0] o_fft_X_imag_6; +wire [17:0] o_fft_X_real_7; +wire [17:0] o_fft_X_imag_7; +wire [17:0] o_fft_X_real_8; +wire [17:0] o_fft_X_imag_8; +wire [17:0] o_fft_X_real_9; +wire [17:0] o_fft_X_imag_9; +wire [17:0] o_fft_X_real_10; +wire [17:0] o_fft_X_imag_10; +wire [17:0] o_fft_X_real_11; +wire [17:0] o_fft_X_imag_11; +wire [17:0] o_fft_X_real_12; +wire [17:0] o_fft_X_imag_12; +wire [17:0] o_fft_X_real_13; +wire [17:0] o_fft_X_imag_13; +wire [17:0] o_fft_X_real_14; +wire [17:0] o_fft_X_imag_14; +wire [17:0] o_fft_X_real_15; +wire [17:0] o_fft_X_imag_15; + +// Hold weights value until X_FFT finishes +assign W_real_wires_0_0 = reg_W_real_0_0; +assign W_imag_wires_0_0 = reg_W_imag_0_0; +assign W_real_wires_0_1 = reg_W_real_0_1; +assign W_imag_wires_0_1 = reg_W_imag_0_1; +assign W_real_wires_0_2 = reg_W_real_0_2; +assign W_imag_wires_0_2 = reg_W_imag_0_2; +assign W_real_wires_0_3 = reg_W_real_0_3; +assign W_imag_wires_0_3 = reg_W_imag_0_3; +assign W_real_wires_0_4 = reg_W_real_0_4; +assign W_imag_wires_0_4 = reg_W_imag_0_4; +assign W_real_wires_0_5 = reg_W_real_0_5; +assign W_imag_wires_0_5 = reg_W_imag_0_5; +assign W_real_wires_0_6 = reg_W_real_0_6; +assign W_imag_wires_0_6 = reg_W_imag_0_6; +assign W_real_wires_0_7 = reg_W_real_0_7; +assign W_imag_wires_0_7 = reg_W_imag_0_7; +assign W_real_wires_0_8 = reg_W_real_0_8; +assign W_imag_wires_0_8 = reg_W_imag_0_8; +assign W_real_wires_1_0 = reg_W_real_1_0; +assign W_imag_wires_1_0 = reg_W_imag_1_0; +assign W_real_wires_1_1 = reg_W_real_1_1; +assign W_imag_wires_1_1 = reg_W_imag_1_1; +assign W_real_wires_1_2 = reg_W_real_1_2; +assign W_imag_wires_1_2 = reg_W_imag_1_2; +assign W_real_wires_1_3 = reg_W_real_1_3; +assign W_imag_wires_1_3 = reg_W_imag_1_3; +assign W_real_wires_1_4 = reg_W_real_1_4; +assign W_imag_wires_1_4 = reg_W_imag_1_4; +assign W_real_wires_1_5 = reg_W_real_1_5; +assign W_imag_wires_1_5 = reg_W_imag_1_5; +assign W_real_wires_1_6 = reg_W_real_1_6; +assign W_imag_wires_1_6 = reg_W_imag_1_6; +assign W_real_wires_1_7 = reg_W_real_1_7; +assign W_imag_wires_1_7 = reg_W_imag_1_7; +assign W_real_wires_1_8 = reg_W_real_1_8; +assign W_imag_wires_1_8 = reg_W_imag_1_8; +assign W_real_wires_2_0 = reg_W_real_2_0; +assign W_imag_wires_2_0 = reg_W_imag_2_0; +assign W_real_wires_2_1 = reg_W_real_2_1; +assign W_imag_wires_2_1 = reg_W_imag_2_1; +assign W_real_wires_2_2 = reg_W_real_2_2; +assign W_imag_wires_2_2 = reg_W_imag_2_2; +assign W_real_wires_2_3 = reg_W_real_2_3; +assign W_imag_wires_2_3 = reg_W_imag_2_3; +assign W_real_wires_2_4 = reg_W_real_2_4; +assign W_imag_wires_2_4 = reg_W_imag_2_4; +assign W_real_wires_2_5 = reg_W_real_2_5; +assign W_imag_wires_2_5 = reg_W_imag_2_5; +assign W_real_wires_2_6 = reg_W_real_2_6; +assign W_imag_wires_2_6 = reg_W_imag_2_6; +assign W_real_wires_2_7 = reg_W_real_2_7; +assign W_imag_wires_2_7 = reg_W_imag_2_7; +assign W_real_wires_2_8 = reg_W_real_2_8; +assign W_imag_wires_2_8 = reg_W_imag_2_8; + +shift_register_group_18_910 shift_register_group_18_910_inst_0_real ( + .clk(clk), + .enable(enable), + .in_0(W_real_wires_0_0), + .out_0(W_real_holder_0_0), + .in_1(W_real_wires_0_1), + .out_1(W_real_holder_0_1), + .in_2(W_real_wires_0_2), + .out_2(W_real_holder_0_2), + .in_3(W_real_wires_0_3), + .out_3(W_real_holder_0_3), + .in_4(W_real_wires_0_4), + .out_4(W_real_holder_0_4), + .in_5(W_real_wires_0_5), + .out_5(W_real_holder_0_5), + .in_6(W_real_wires_0_6), + .out_6(W_real_holder_0_6), + .in_7(W_real_wires_0_7), + .out_7(W_real_holder_0_7), + .in_8(W_real_wires_0_8), + .out_8(W_real_holder_0_8), + .reset(reset) +); + +shift_register_group_18_910 shift_register_group_18_910_inst_0_imag ( + .clk(clk), + .enable(enable), + .in_0(W_imag_wires_0_0), + .out_0(W_imag_holder_0_0), + .in_1(W_imag_wires_0_1), + .out_1(W_imag_holder_0_1), + .in_2(W_imag_wires_0_2), + .out_2(W_imag_holder_0_2), + .in_3(W_imag_wires_0_3), + .out_3(W_imag_holder_0_3), + .in_4(W_imag_wires_0_4), + .out_4(W_imag_holder_0_4), + .in_5(W_imag_wires_0_5), + .out_5(W_imag_holder_0_5), + .in_6(W_imag_wires_0_6), + .out_6(W_imag_holder_0_6), + .in_7(W_imag_wires_0_7), + .out_7(W_imag_holder_0_7), + .in_8(W_imag_wires_0_8), + .out_8(W_imag_holder_0_8), + .reset(reset) +); + +shift_register_group_18_910 shift_register_group_18_910_inst_1_real ( + .clk(clk), + .enable(enable), + .in_0(W_real_wires_1_0), + .out_0(W_real_holder_1_0), + .in_1(W_real_wires_1_1), + .out_1(W_real_holder_1_1), + .in_2(W_real_wires_1_2), + .out_2(W_real_holder_1_2), + .in_3(W_real_wires_1_3), + .out_3(W_real_holder_1_3), + .in_4(W_real_wires_1_4), + .out_4(W_real_holder_1_4), + .in_5(W_real_wires_1_5), + .out_5(W_real_holder_1_5), + .in_6(W_real_wires_1_6), + .out_6(W_real_holder_1_6), + .in_7(W_real_wires_1_7), + .out_7(W_real_holder_1_7), + .in_8(W_real_wires_1_8), + .out_8(W_real_holder_1_8), + .reset(reset) +); + +shift_register_group_18_910 shift_register_group_18_910_inst_1_imag ( + .clk(clk), + .enable(enable), + .in_0(W_imag_wires_1_0), + .out_0(W_imag_holder_1_0), + .in_1(W_imag_wires_1_1), + .out_1(W_imag_holder_1_1), + .in_2(W_imag_wires_1_2), + .out_2(W_imag_holder_1_2), + .in_3(W_imag_wires_1_3), + .out_3(W_imag_holder_1_3), + .in_4(W_imag_wires_1_4), + .out_4(W_imag_holder_1_4), + .in_5(W_imag_wires_1_5), + .out_5(W_imag_holder_1_5), + .in_6(W_imag_wires_1_6), + .out_6(W_imag_holder_1_6), + .in_7(W_imag_wires_1_7), + .out_7(W_imag_holder_1_7), + .in_8(W_imag_wires_1_8), + .out_8(W_imag_holder_1_8), + .reset(reset) +); + +shift_register_group_18_910 shift_register_group_18_910_inst_2_real ( + .clk(clk), + .enable(enable), + .in_0(W_real_wires_2_0), + .out_0(W_real_holder_2_0), + .in_1(W_real_wires_2_1), + .out_1(W_real_holder_2_1), + .in_2(W_real_wires_2_2), + .out_2(W_real_holder_2_2), + .in_3(W_real_wires_2_3), + .out_3(W_real_holder_2_3), + .in_4(W_real_wires_2_4), + .out_4(W_real_holder_2_4), + .in_5(W_real_wires_2_5), + .out_5(W_real_holder_2_5), + .in_6(W_real_wires_2_6), + .out_6(W_real_holder_2_6), + .in_7(W_real_wires_2_7), + .out_7(W_real_holder_2_7), + .in_8(W_real_wires_2_8), + .out_8(W_real_holder_2_8), + .reset(reset) +); + +shift_register_group_18_910 shift_register_group_18_910_inst_2_imag ( + .clk(clk), + .enable(enable), + .in_0(W_imag_wires_2_0), + .out_0(W_imag_holder_2_0), + .in_1(W_imag_wires_2_1), + .out_1(W_imag_holder_2_1), + .in_2(W_imag_wires_2_2), + .out_2(W_imag_holder_2_2), + .in_3(W_imag_wires_2_3), + .out_3(W_imag_holder_2_3), + .in_4(W_imag_wires_2_4), + .out_4(W_imag_holder_2_4), + .in_5(W_imag_wires_2_5), + .out_5(W_imag_holder_2_5), + .in_6(W_imag_wires_2_6), + .out_6(W_imag_holder_2_6), + .in_7(W_imag_wires_2_7), + .out_7(W_imag_holder_2_7), + .in_8(W_imag_wires_2_8), + .out_8(W_imag_holder_2_8), + .reset(reset) +); + +dft_16_top_18 dft_16_top_18_inst_spluxgleid ( + .clk(clk), + .reset(reset), + .next(reg_i_valid), + .X0(reg_X_2_0), + .Y0(o_fft_X_real_0), + .X1(18'd0), + .Y1(o_fft_X_imag_0), + .X2(reg_X_2_1), + .Y2(o_fft_X_real_1), + .X3(18'd0), + .Y3(o_fft_X_imag_1), + .X4(reg_X_2_2), + .Y4(o_fft_X_real_2), + .X5(18'd0), + .Y5(o_fft_X_imag_2), + .X6(reg_X_2_3), + .Y6(o_fft_X_real_3), + .X7(18'd0), + .Y7(o_fft_X_imag_3), + .X8(reg_X_2_4), + .Y8(o_fft_X_real_4), + .X9(18'd0), + .Y9(o_fft_X_imag_4), + .X10(reg_X_2_5), + .Y10(o_fft_X_real_5), + .X11(18'd0), + .Y11(o_fft_X_imag_5), + .X12(reg_X_2_6), + .Y12(o_fft_X_real_6), + .X13(18'd0), + .Y13(o_fft_X_imag_6), + .X14(reg_X_2_7), + .Y14(o_fft_X_real_7), + .X15(18'd0), + .Y15(o_fft_X_imag_7), + .X16(reg_X_2_8), + .Y16(o_fft_X_real_8), + .X17(18'd0), + .Y17(o_fft_X_imag_8), + .X18(reg_X_2_9), + .Y18(o_fft_X_real_9), + .X19(18'd0), + .Y19(o_fft_X_imag_9), + .X20(reg_X_2_10), + .Y20(o_fft_X_real_10), + .X21(18'd0), + .Y21(o_fft_X_imag_10), + .X22(reg_X_2_11), + .Y22(o_fft_X_real_11), + .X23(18'd0), + .Y23(o_fft_X_imag_11), + .X24(reg_X_2_12), + .Y24(o_fft_X_real_12), + .X25(18'd0), + .Y25(o_fft_X_imag_12), + .X26(reg_X_2_13), + .Y26(o_fft_X_real_13), + .X27(18'd0), + .Y27(o_fft_X_imag_13), + .X28(reg_X_2_14), + .Y28(o_fft_X_real_14), + .X29(18'd0), + .Y29(o_fft_X_imag_14), + .X30(reg_X_2_15), + .Y30(o_fft_X_real_15), + .X31(18'd0), + .Y31(o_fft_X_imag_15), + .next_out(o_fft_next) +); +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_0_real_real ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(W_real_holder_0_0), + .i_B_0(o_fft_X_real_0), + .o_C_0(o_mult_X_real_W_real_0_0), + .i_A_1(W_real_holder_0_1), + .i_B_1(o_fft_X_real_1), + .o_C_1(o_mult_X_real_W_real_0_1), + .i_A_2(W_real_holder_0_2), + .i_B_2(o_fft_X_real_2), + .o_C_2(o_mult_X_real_W_real_0_2), + .i_A_3(W_real_holder_0_3), + .i_B_3(o_fft_X_real_3), + .o_C_3(o_mult_X_real_W_real_0_3), + .i_A_4(W_real_holder_0_4), + .i_B_4(o_fft_X_real_4), + .o_C_4(o_mult_X_real_W_real_0_4), + .i_A_5(W_real_holder_0_5), + .i_B_5(o_fft_X_real_5), + .o_C_5(o_mult_X_real_W_real_0_5), + .i_A_6(W_real_holder_0_6), + .i_B_6(o_fft_X_real_6), + .o_C_6(o_mult_X_real_W_real_0_6), + .i_A_7(W_real_holder_0_7), + .i_B_7(o_fft_X_real_7), + .o_C_7(o_mult_X_real_W_real_0_7), + .i_A_8(W_real_holder_0_8), + .i_B_8(o_fft_X_real_8), + .o_C_8(o_mult_X_real_W_real_0_8), + .o_valid(mult_X_real_W_real_valid_0), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_0_real_imag ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(W_imag_holder_0_0), + .i_B_0(o_fft_X_real_0), + .o_C_0(o_mult_X_real_W_imag_0_0), + .i_A_1(W_imag_holder_0_1), + .i_B_1(o_fft_X_real_1), + .o_C_1(o_mult_X_real_W_imag_0_1), + .i_A_2(W_imag_holder_0_2), + .i_B_2(o_fft_X_real_2), + .o_C_2(o_mult_X_real_W_imag_0_2), + .i_A_3(W_imag_holder_0_3), + .i_B_3(o_fft_X_real_3), + .o_C_3(o_mult_X_real_W_imag_0_3), + .i_A_4(W_imag_holder_0_4), + .i_B_4(o_fft_X_real_4), + .o_C_4(o_mult_X_real_W_imag_0_4), + .i_A_5(W_imag_holder_0_5), + .i_B_5(o_fft_X_real_5), + .o_C_5(o_mult_X_real_W_imag_0_5), + .i_A_6(W_imag_holder_0_6), + .i_B_6(o_fft_X_real_6), + .o_C_6(o_mult_X_real_W_imag_0_6), + .i_A_7(W_imag_holder_0_7), + .i_B_7(o_fft_X_real_7), + .o_C_7(o_mult_X_real_W_imag_0_7), + .i_A_8(W_imag_holder_0_8), + .i_B_8(o_fft_X_real_8), + .o_C_8(o_mult_X_real_W_imag_0_8), + .o_valid(mult_X_real_W_imag_valid_0), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_0_imag_real ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(o_fft_X_imag_0), + .i_B_0(W_real_holder_0_0), + .o_C_0(o_mult_X_imag_W_real_0_0), + .i_A_1(o_fft_X_imag_1), + .i_B_1(W_real_holder_0_1), + .o_C_1(o_mult_X_imag_W_real_0_1), + .i_A_2(o_fft_X_imag_2), + .i_B_2(W_real_holder_0_2), + .o_C_2(o_mult_X_imag_W_real_0_2), + .i_A_3(o_fft_X_imag_3), + .i_B_3(W_real_holder_0_3), + .o_C_3(o_mult_X_imag_W_real_0_3), + .i_A_4(o_fft_X_imag_4), + .i_B_4(W_real_holder_0_4), + .o_C_4(o_mult_X_imag_W_real_0_4), + .i_A_5(o_fft_X_imag_5), + .i_B_5(W_real_holder_0_5), + .o_C_5(o_mult_X_imag_W_real_0_5), + .i_A_6(o_fft_X_imag_6), + .i_B_6(W_real_holder_0_6), + .o_C_6(o_mult_X_imag_W_real_0_6), + .i_A_7(o_fft_X_imag_7), + .i_B_7(W_real_holder_0_7), + .o_C_7(o_mult_X_imag_W_real_0_7), + .i_A_8(o_fft_X_imag_8), + .i_B_8(W_real_holder_0_8), + .o_C_8(o_mult_X_imag_W_real_0_8), + .o_valid(mult_X_imag_W_real_valid_0), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_0_imag_imag ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(o_fft_X_imag_0), + .i_B_0(W_imag_holder_0_0), + .o_C_0(o_mult_X_imag_W_imag_0_0), + .i_A_1(o_fft_X_imag_1), + .i_B_1(W_imag_holder_0_1), + .o_C_1(o_mult_X_imag_W_imag_0_1), + .i_A_2(o_fft_X_imag_2), + .i_B_2(W_imag_holder_0_2), + .o_C_2(o_mult_X_imag_W_imag_0_2), + .i_A_3(o_fft_X_imag_3), + .i_B_3(W_imag_holder_0_3), + .o_C_3(o_mult_X_imag_W_imag_0_3), + .i_A_4(o_fft_X_imag_4), + .i_B_4(W_imag_holder_0_4), + .o_C_4(o_mult_X_imag_W_imag_0_4), + .i_A_5(o_fft_X_imag_5), + .i_B_5(W_imag_holder_0_5), + .o_C_5(o_mult_X_imag_W_imag_0_5), + .i_A_6(o_fft_X_imag_6), + .i_B_6(W_imag_holder_0_6), + .o_C_6(o_mult_X_imag_W_imag_0_6), + .i_A_7(o_fft_X_imag_7), + .i_B_7(W_imag_holder_0_7), + .o_C_7(o_mult_X_imag_W_imag_0_7), + .i_A_8(o_fft_X_imag_8), + .i_B_8(W_imag_holder_0_8), + .o_C_8(o_mult_X_imag_W_imag_0_8), + .o_valid(mult_X_imag_W_imag_valid_0), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_1_real_real ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(W_real_holder_1_0), + .i_B_0(o_fft_X_real_0), + .o_C_0(o_mult_X_real_W_real_1_0), + .i_A_1(W_real_holder_1_1), + .i_B_1(o_fft_X_real_1), + .o_C_1(o_mult_X_real_W_real_1_1), + .i_A_2(W_real_holder_1_2), + .i_B_2(o_fft_X_real_2), + .o_C_2(o_mult_X_real_W_real_1_2), + .i_A_3(W_real_holder_1_3), + .i_B_3(o_fft_X_real_3), + .o_C_3(o_mult_X_real_W_real_1_3), + .i_A_4(W_real_holder_1_4), + .i_B_4(o_fft_X_real_4), + .o_C_4(o_mult_X_real_W_real_1_4), + .i_A_5(W_real_holder_1_5), + .i_B_5(o_fft_X_real_5), + .o_C_5(o_mult_X_real_W_real_1_5), + .i_A_6(W_real_holder_1_6), + .i_B_6(o_fft_X_real_6), + .o_C_6(o_mult_X_real_W_real_1_6), + .i_A_7(W_real_holder_1_7), + .i_B_7(o_fft_X_real_7), + .o_C_7(o_mult_X_real_W_real_1_7), + .i_A_8(W_real_holder_1_8), + .i_B_8(o_fft_X_real_8), + .o_C_8(o_mult_X_real_W_real_1_8), + .o_valid(mult_X_real_W_real_valid_1), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_1_real_imag ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(W_imag_holder_1_0), + .i_B_0(o_fft_X_real_0), + .o_C_0(o_mult_X_real_W_imag_1_0), + .i_A_1(W_imag_holder_1_1), + .i_B_1(o_fft_X_real_1), + .o_C_1(o_mult_X_real_W_imag_1_1), + .i_A_2(W_imag_holder_1_2), + .i_B_2(o_fft_X_real_2), + .o_C_2(o_mult_X_real_W_imag_1_2), + .i_A_3(W_imag_holder_1_3), + .i_B_3(o_fft_X_real_3), + .o_C_3(o_mult_X_real_W_imag_1_3), + .i_A_4(W_imag_holder_1_4), + .i_B_4(o_fft_X_real_4), + .o_C_4(o_mult_X_real_W_imag_1_4), + .i_A_5(W_imag_holder_1_5), + .i_B_5(o_fft_X_real_5), + .o_C_5(o_mult_X_real_W_imag_1_5), + .i_A_6(W_imag_holder_1_6), + .i_B_6(o_fft_X_real_6), + .o_C_6(o_mult_X_real_W_imag_1_6), + .i_A_7(W_imag_holder_1_7), + .i_B_7(o_fft_X_real_7), + .o_C_7(o_mult_X_real_W_imag_1_7), + .i_A_8(W_imag_holder_1_8), + .i_B_8(o_fft_X_real_8), + .o_C_8(o_mult_X_real_W_imag_1_8), + .o_valid(mult_X_real_W_imag_valid_1), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_1_imag_real ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(o_fft_X_imag_0), + .i_B_0(W_real_holder_1_0), + .o_C_0(o_mult_X_imag_W_real_1_0), + .i_A_1(o_fft_X_imag_1), + .i_B_1(W_real_holder_1_1), + .o_C_1(o_mult_X_imag_W_real_1_1), + .i_A_2(o_fft_X_imag_2), + .i_B_2(W_real_holder_1_2), + .o_C_2(o_mult_X_imag_W_real_1_2), + .i_A_3(o_fft_X_imag_3), + .i_B_3(W_real_holder_1_3), + .o_C_3(o_mult_X_imag_W_real_1_3), + .i_A_4(o_fft_X_imag_4), + .i_B_4(W_real_holder_1_4), + .o_C_4(o_mult_X_imag_W_real_1_4), + .i_A_5(o_fft_X_imag_5), + .i_B_5(W_real_holder_1_5), + .o_C_5(o_mult_X_imag_W_real_1_5), + .i_A_6(o_fft_X_imag_6), + .i_B_6(W_real_holder_1_6), + .o_C_6(o_mult_X_imag_W_real_1_6), + .i_A_7(o_fft_X_imag_7), + .i_B_7(W_real_holder_1_7), + .o_C_7(o_mult_X_imag_W_real_1_7), + .i_A_8(o_fft_X_imag_8), + .i_B_8(W_real_holder_1_8), + .o_C_8(o_mult_X_imag_W_real_1_8), + .o_valid(mult_X_imag_W_real_valid_1), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_1_imag_imag ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(o_fft_X_imag_0), + .i_B_0(W_imag_holder_1_0), + .o_C_0(o_mult_X_imag_W_imag_1_0), + .i_A_1(o_fft_X_imag_1), + .i_B_1(W_imag_holder_1_1), + .o_C_1(o_mult_X_imag_W_imag_1_1), + .i_A_2(o_fft_X_imag_2), + .i_B_2(W_imag_holder_1_2), + .o_C_2(o_mult_X_imag_W_imag_1_2), + .i_A_3(o_fft_X_imag_3), + .i_B_3(W_imag_holder_1_3), + .o_C_3(o_mult_X_imag_W_imag_1_3), + .i_A_4(o_fft_X_imag_4), + .i_B_4(W_imag_holder_1_4), + .o_C_4(o_mult_X_imag_W_imag_1_4), + .i_A_5(o_fft_X_imag_5), + .i_B_5(W_imag_holder_1_5), + .o_C_5(o_mult_X_imag_W_imag_1_5), + .i_A_6(o_fft_X_imag_6), + .i_B_6(W_imag_holder_1_6), + .o_C_6(o_mult_X_imag_W_imag_1_6), + .i_A_7(o_fft_X_imag_7), + .i_B_7(W_imag_holder_1_7), + .o_C_7(o_mult_X_imag_W_imag_1_7), + .i_A_8(o_fft_X_imag_8), + .i_B_8(W_imag_holder_1_8), + .o_C_8(o_mult_X_imag_W_imag_1_8), + .o_valid(mult_X_imag_W_imag_valid_1), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_2_real_real ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(W_real_holder_2_0), + .i_B_0(o_fft_X_real_0), + .o_C_0(o_mult_X_real_W_real_2_0), + .i_A_1(W_real_holder_2_1), + .i_B_1(o_fft_X_real_1), + .o_C_1(o_mult_X_real_W_real_2_1), + .i_A_2(W_real_holder_2_2), + .i_B_2(o_fft_X_real_2), + .o_C_2(o_mult_X_real_W_real_2_2), + .i_A_3(W_real_holder_2_3), + .i_B_3(o_fft_X_real_3), + .o_C_3(o_mult_X_real_W_real_2_3), + .i_A_4(W_real_holder_2_4), + .i_B_4(o_fft_X_real_4), + .o_C_4(o_mult_X_real_W_real_2_4), + .i_A_5(W_real_holder_2_5), + .i_B_5(o_fft_X_real_5), + .o_C_5(o_mult_X_real_W_real_2_5), + .i_A_6(W_real_holder_2_6), + .i_B_6(o_fft_X_real_6), + .o_C_6(o_mult_X_real_W_real_2_6), + .i_A_7(W_real_holder_2_7), + .i_B_7(o_fft_X_real_7), + .o_C_7(o_mult_X_real_W_real_2_7), + .i_A_8(W_real_holder_2_8), + .i_B_8(o_fft_X_real_8), + .o_C_8(o_mult_X_real_W_real_2_8), + .o_valid(mult_X_real_W_real_valid_2), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_2_real_imag ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(W_imag_holder_2_0), + .i_B_0(o_fft_X_real_0), + .o_C_0(o_mult_X_real_W_imag_2_0), + .i_A_1(W_imag_holder_2_1), + .i_B_1(o_fft_X_real_1), + .o_C_1(o_mult_X_real_W_imag_2_1), + .i_A_2(W_imag_holder_2_2), + .i_B_2(o_fft_X_real_2), + .o_C_2(o_mult_X_real_W_imag_2_2), + .i_A_3(W_imag_holder_2_3), + .i_B_3(o_fft_X_real_3), + .o_C_3(o_mult_X_real_W_imag_2_3), + .i_A_4(W_imag_holder_2_4), + .i_B_4(o_fft_X_real_4), + .o_C_4(o_mult_X_real_W_imag_2_4), + .i_A_5(W_imag_holder_2_5), + .i_B_5(o_fft_X_real_5), + .o_C_5(o_mult_X_real_W_imag_2_5), + .i_A_6(W_imag_holder_2_6), + .i_B_6(o_fft_X_real_6), + .o_C_6(o_mult_X_real_W_imag_2_6), + .i_A_7(W_imag_holder_2_7), + .i_B_7(o_fft_X_real_7), + .o_C_7(o_mult_X_real_W_imag_2_7), + .i_A_8(W_imag_holder_2_8), + .i_B_8(o_fft_X_real_8), + .o_C_8(o_mult_X_real_W_imag_2_8), + .o_valid(mult_X_real_W_imag_valid_2), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_2_imag_real ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(o_fft_X_imag_0), + .i_B_0(W_real_holder_2_0), + .o_C_0(o_mult_X_imag_W_real_2_0), + .i_A_1(o_fft_X_imag_1), + .i_B_1(W_real_holder_2_1), + .o_C_1(o_mult_X_imag_W_real_2_1), + .i_A_2(o_fft_X_imag_2), + .i_B_2(W_real_holder_2_2), + .o_C_2(o_mult_X_imag_W_real_2_2), + .i_A_3(o_fft_X_imag_3), + .i_B_3(W_real_holder_2_3), + .o_C_3(o_mult_X_imag_W_real_2_3), + .i_A_4(o_fft_X_imag_4), + .i_B_4(W_real_holder_2_4), + .o_C_4(o_mult_X_imag_W_real_2_4), + .i_A_5(o_fft_X_imag_5), + .i_B_5(W_real_holder_2_5), + .o_C_5(o_mult_X_imag_W_real_2_5), + .i_A_6(o_fft_X_imag_6), + .i_B_6(W_real_holder_2_6), + .o_C_6(o_mult_X_imag_W_real_2_6), + .i_A_7(o_fft_X_imag_7), + .i_B_7(W_real_holder_2_7), + .o_C_7(o_mult_X_imag_W_real_2_7), + .i_A_8(o_fft_X_imag_8), + .i_B_8(W_real_holder_2_8), + .o_C_8(o_mult_X_imag_W_real_2_8), + .o_valid(mult_X_imag_W_real_valid_2), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_2_imag_imag ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(o_fft_X_imag_0), + .i_B_0(W_imag_holder_2_0), + .o_C_0(o_mult_X_imag_W_imag_2_0), + .i_A_1(o_fft_X_imag_1), + .i_B_1(W_imag_holder_2_1), + .o_C_1(o_mult_X_imag_W_imag_2_1), + .i_A_2(o_fft_X_imag_2), + .i_B_2(W_imag_holder_2_2), + .o_C_2(o_mult_X_imag_W_imag_2_2), + .i_A_3(o_fft_X_imag_3), + .i_B_3(W_imag_holder_2_3), + .o_C_3(o_mult_X_imag_W_imag_2_3), + .i_A_4(o_fft_X_imag_4), + .i_B_4(W_imag_holder_2_4), + .o_C_4(o_mult_X_imag_W_imag_2_4), + .i_A_5(o_fft_X_imag_5), + .i_B_5(W_imag_holder_2_5), + .o_C_5(o_mult_X_imag_W_imag_2_5), + .i_A_6(o_fft_X_imag_6), + .i_B_6(W_imag_holder_2_6), + .o_C_6(o_mult_X_imag_W_imag_2_6), + .i_A_7(o_fft_X_imag_7), + .i_B_7(W_imag_holder_2_7), + .o_C_7(o_mult_X_imag_W_imag_2_7), + .i_A_8(o_fft_X_imag_8), + .i_B_8(W_imag_holder_2_8), + .o_C_8(o_mult_X_imag_W_imag_2_8), + .o_valid(mult_X_imag_W_imag_valid_2), + .o_ready() +); + +wire sub_core_valid_0; +assign sub_core_valid_0 = mult_X_real_W_real_valid_0 & mult_X_imag_W_imag_valid_0; + +elementwise_sub_core_18_18_9 elementwise_sub_core_18_18_9_inst_0 ( + .clk(clk), + .reset(reset), + .i_valid(sub_core_valid_0), + .i_ready(enable), + .i_A_0(o_mult_X_real_W_real_0_0), + .i_B_0(o_mult_X_imag_W_imag_0_0), + .o_C_0(o_sub_y_real_0_0), + .i_A_1(o_mult_X_real_W_real_0_1), + .i_B_1(o_mult_X_imag_W_imag_0_1), + .o_C_1(o_sub_y_real_0_1), + .i_A_2(o_mult_X_real_W_real_0_2), + .i_B_2(o_mult_X_imag_W_imag_0_2), + .o_C_2(o_sub_y_real_0_2), + .i_A_3(o_mult_X_real_W_real_0_3), + .i_B_3(o_mult_X_imag_W_imag_0_3), + .o_C_3(o_sub_y_real_0_3), + .i_A_4(o_mult_X_real_W_real_0_4), + .i_B_4(o_mult_X_imag_W_imag_0_4), + .o_C_4(o_sub_y_real_0_4), + .i_A_5(o_mult_X_real_W_real_0_5), + .i_B_5(o_mult_X_imag_W_imag_0_5), + .o_C_5(o_sub_y_real_0_5), + .i_A_6(o_mult_X_real_W_real_0_6), + .i_B_6(o_mult_X_imag_W_imag_0_6), + .o_C_6(o_sub_y_real_0_6), + .i_A_7(o_mult_X_real_W_real_0_7), + .i_B_7(o_mult_X_imag_W_imag_0_7), + .o_C_7(o_sub_y_real_0_7), + .i_A_8(o_mult_X_real_W_real_0_8), + .i_B_8(o_mult_X_imag_W_imag_0_8), + .o_C_8(o_sub_y_real_0_8), + .o_valid(sub_y_real_valid_0), + .o_ready() +); + +wire sub_core_valid_1; +assign sub_core_valid_1 = mult_X_real_W_real_valid_1 & mult_X_imag_W_imag_valid_1; + +elementwise_sub_core_18_18_9 elementwise_sub_core_18_18_9_inst_1 ( + .clk(clk), + .reset(reset), + .i_valid(sub_core_valid_1), + .i_ready(enable), + .i_A_0(o_mult_X_real_W_real_1_0), + .i_B_0(o_mult_X_imag_W_imag_1_0), + .o_C_0(o_sub_y_real_1_0), + .i_A_1(o_mult_X_real_W_real_1_1), + .i_B_1(o_mult_X_imag_W_imag_1_1), + .o_C_1(o_sub_y_real_1_1), + .i_A_2(o_mult_X_real_W_real_1_2), + .i_B_2(o_mult_X_imag_W_imag_1_2), + .o_C_2(o_sub_y_real_1_2), + .i_A_3(o_mult_X_real_W_real_1_3), + .i_B_3(o_mult_X_imag_W_imag_1_3), + .o_C_3(o_sub_y_real_1_3), + .i_A_4(o_mult_X_real_W_real_1_4), + .i_B_4(o_mult_X_imag_W_imag_1_4), + .o_C_4(o_sub_y_real_1_4), + .i_A_5(o_mult_X_real_W_real_1_5), + .i_B_5(o_mult_X_imag_W_imag_1_5), + .o_C_5(o_sub_y_real_1_5), + .i_A_6(o_mult_X_real_W_real_1_6), + .i_B_6(o_mult_X_imag_W_imag_1_6), + .o_C_6(o_sub_y_real_1_6), + .i_A_7(o_mult_X_real_W_real_1_7), + .i_B_7(o_mult_X_imag_W_imag_1_7), + .o_C_7(o_sub_y_real_1_7), + .i_A_8(o_mult_X_real_W_real_1_8), + .i_B_8(o_mult_X_imag_W_imag_1_8), + .o_C_8(o_sub_y_real_1_8), + .o_valid(sub_y_real_valid_1), + .o_ready() +); + +wire sub_core_valid_2; +assign sub_core_valid_2 = mult_X_real_W_real_valid_2 & mult_X_imag_W_imag_valid_2; + +elementwise_sub_core_18_18_9 elementwise_sub_core_18_18_9_inst_2 ( + .clk(clk), + .reset(reset), + .i_valid(sub_core_valid_2), + .i_ready(enable), + .i_A_0(o_mult_X_real_W_real_2_0), + .i_B_0(o_mult_X_imag_W_imag_2_0), + .o_C_0(o_sub_y_real_2_0), + .i_A_1(o_mult_X_real_W_real_2_1), + .i_B_1(o_mult_X_imag_W_imag_2_1), + .o_C_1(o_sub_y_real_2_1), + .i_A_2(o_mult_X_real_W_real_2_2), + .i_B_2(o_mult_X_imag_W_imag_2_2), + .o_C_2(o_sub_y_real_2_2), + .i_A_3(o_mult_X_real_W_real_2_3), + .i_B_3(o_mult_X_imag_W_imag_2_3), + .o_C_3(o_sub_y_real_2_3), + .i_A_4(o_mult_X_real_W_real_2_4), + .i_B_4(o_mult_X_imag_W_imag_2_4), + .o_C_4(o_sub_y_real_2_4), + .i_A_5(o_mult_X_real_W_real_2_5), + .i_B_5(o_mult_X_imag_W_imag_2_5), + .o_C_5(o_sub_y_real_2_5), + .i_A_6(o_mult_X_real_W_real_2_6), + .i_B_6(o_mult_X_imag_W_imag_2_6), + .o_C_6(o_sub_y_real_2_6), + .i_A_7(o_mult_X_real_W_real_2_7), + .i_B_7(o_mult_X_imag_W_imag_2_7), + .o_C_7(o_sub_y_real_2_7), + .i_A_8(o_mult_X_real_W_real_2_8), + .i_B_8(o_mult_X_imag_W_imag_2_8), + .o_C_8(o_sub_y_real_2_8), + .o_valid(sub_y_real_valid_2), + .o_ready() +); + +wire add_core_valid_0; +assign add_core_valid_0 = mult_X_real_W_imag_valid_0 & mult_X_imag_W_real_valid_0; + +elementwise_add_core_18_18_9 elementwise_add_core_18_18_9_inst_0 ( + .clk(clk), + .reset(reset), + .i_valid(add_core_valid_0), + .i_ready(enable), + .i_A_0(o_mult_X_real_W_imag_0_0), + .i_B_0(o_mult_X_imag_W_real_0_0), + .o_C_0(o_add_y_imag_0_0), + .i_A_1(o_mult_X_real_W_imag_0_1), + .i_B_1(o_mult_X_imag_W_real_0_1), + .o_C_1(o_add_y_imag_0_1), + .i_A_2(o_mult_X_real_W_imag_0_2), + .i_B_2(o_mult_X_imag_W_real_0_2), + .o_C_2(o_add_y_imag_0_2), + .i_A_3(o_mult_X_real_W_imag_0_3), + .i_B_3(o_mult_X_imag_W_real_0_3), + .o_C_3(o_add_y_imag_0_3), + .i_A_4(o_mult_X_real_W_imag_0_4), + .i_B_4(o_mult_X_imag_W_real_0_4), + .o_C_4(o_add_y_imag_0_4), + .i_A_5(o_mult_X_real_W_imag_0_5), + .i_B_5(o_mult_X_imag_W_real_0_5), + .o_C_5(o_add_y_imag_0_5), + .i_A_6(o_mult_X_real_W_imag_0_6), + .i_B_6(o_mult_X_imag_W_real_0_6), + .o_C_6(o_add_y_imag_0_6), + .i_A_7(o_mult_X_real_W_imag_0_7), + .i_B_7(o_mult_X_imag_W_real_0_7), + .o_C_7(o_add_y_imag_0_7), + .i_A_8(o_mult_X_real_W_imag_0_8), + .i_B_8(o_mult_X_imag_W_real_0_8), + .o_C_8(o_add_y_imag_0_8), + .o_valid(add_y_imag_valid_0), + .o_ready() +); + +wire add_core_valid_1; +assign add_core_valid_1 = mult_X_real_W_imag_valid_1 & mult_X_imag_W_real_valid_1; + +elementwise_add_core_18_18_9 elementwise_add_core_18_18_9_inst_1 ( + .clk(clk), + .reset(reset), + .i_valid(add_core_valid_1), + .i_ready(enable), + .i_A_0(o_mult_X_real_W_imag_1_0), + .i_B_0(o_mult_X_imag_W_real_1_0), + .o_C_0(o_add_y_imag_1_0), + .i_A_1(o_mult_X_real_W_imag_1_1), + .i_B_1(o_mult_X_imag_W_real_1_1), + .o_C_1(o_add_y_imag_1_1), + .i_A_2(o_mult_X_real_W_imag_1_2), + .i_B_2(o_mult_X_imag_W_real_1_2), + .o_C_2(o_add_y_imag_1_2), + .i_A_3(o_mult_X_real_W_imag_1_3), + .i_B_3(o_mult_X_imag_W_real_1_3), + .o_C_3(o_add_y_imag_1_3), + .i_A_4(o_mult_X_real_W_imag_1_4), + .i_B_4(o_mult_X_imag_W_real_1_4), + .o_C_4(o_add_y_imag_1_4), + .i_A_5(o_mult_X_real_W_imag_1_5), + .i_B_5(o_mult_X_imag_W_real_1_5), + .o_C_5(o_add_y_imag_1_5), + .i_A_6(o_mult_X_real_W_imag_1_6), + .i_B_6(o_mult_X_imag_W_real_1_6), + .o_C_6(o_add_y_imag_1_6), + .i_A_7(o_mult_X_real_W_imag_1_7), + .i_B_7(o_mult_X_imag_W_real_1_7), + .o_C_7(o_add_y_imag_1_7), + .i_A_8(o_mult_X_real_W_imag_1_8), + .i_B_8(o_mult_X_imag_W_real_1_8), + .o_C_8(o_add_y_imag_1_8), + .o_valid(add_y_imag_valid_1), + .o_ready() +); + +wire add_core_valid_2; +assign add_core_valid_2 = mult_X_real_W_imag_valid_2 & mult_X_imag_W_real_valid_2; + +elementwise_add_core_18_18_9 elementwise_add_core_18_18_9_inst_2 ( + .clk(clk), + .reset(reset), + .i_valid(add_core_valid_2), + .i_ready(enable), + .i_A_0(o_mult_X_real_W_imag_2_0), + .i_B_0(o_mult_X_imag_W_real_2_0), + .o_C_0(o_add_y_imag_2_0), + .i_A_1(o_mult_X_real_W_imag_2_1), + .i_B_1(o_mult_X_imag_W_real_2_1), + .o_C_1(o_add_y_imag_2_1), + .i_A_2(o_mult_X_real_W_imag_2_2), + .i_B_2(o_mult_X_imag_W_real_2_2), + .o_C_2(o_add_y_imag_2_2), + .i_A_3(o_mult_X_real_W_imag_2_3), + .i_B_3(o_mult_X_imag_W_real_2_3), + .o_C_3(o_add_y_imag_2_3), + .i_A_4(o_mult_X_real_W_imag_2_4), + .i_B_4(o_mult_X_imag_W_real_2_4), + .o_C_4(o_add_y_imag_2_4), + .i_A_5(o_mult_X_real_W_imag_2_5), + .i_B_5(o_mult_X_imag_W_real_2_5), + .o_C_5(o_add_y_imag_2_5), + .i_A_6(o_mult_X_real_W_imag_2_6), + .i_B_6(o_mult_X_imag_W_real_2_6), + .o_C_6(o_add_y_imag_2_6), + .i_A_7(o_mult_X_real_W_imag_2_7), + .i_B_7(o_mult_X_imag_W_real_2_7), + .o_C_7(o_add_y_imag_2_7), + .i_A_8(o_mult_X_real_W_imag_2_8), + .i_B_8(o_mult_X_imag_W_real_2_8), + .o_C_8(o_add_y_imag_2_8), + .o_valid(add_y_imag_valid_2), + .o_ready() +); + +always @ (posedge clk) begin + if (reset) begin + reg_i_valid <= 1'b0; + fft_valid <= 1'b0; + reg_o_valid <= 1'b0; + reg_o_ready <= 1'b0; + reg_X_0 <= 0; + reg_X_2_0 <= 0; + reg_X_1 <= 0; + reg_X_2_1 <= 0; + reg_X_2 <= 0; + reg_X_2_2 <= 0; + reg_X_3 <= 0; + reg_X_2_3 <= 0; + reg_X_4 <= 0; + reg_X_2_4 <= 0; + reg_X_5 <= 0; + reg_X_2_5 <= 0; + reg_X_6 <= 0; + reg_X_2_6 <= 0; + reg_X_7 <= 0; + reg_X_2_7 <= 0; + reg_X_8 <= 0; + reg_X_2_8 <= 0; + reg_X_9 <= 0; + reg_X_2_9 <= 0; + reg_X_10 <= 0; + reg_X_2_10 <= 0; + reg_X_11 <= 0; + reg_X_2_11 <= 0; + reg_X_12 <= 0; + reg_X_2_12 <= 0; + reg_X_13 <= 0; + reg_X_2_13 <= 0; + reg_X_14 <= 0; + reg_X_2_14 <= 0; + reg_X_15 <= 0; + reg_X_2_15 <= 0; + reg_W_real_0_0 <= 0; + reg_W_imag_0_0 <= 0; + reg_W_real_0_1 <= 0; + reg_W_imag_0_1 <= 0; + reg_W_real_0_2 <= 0; + reg_W_imag_0_2 <= 0; + reg_W_real_0_3 <= 0; + reg_W_imag_0_3 <= 0; + reg_W_real_0_4 <= 0; + reg_W_imag_0_4 <= 0; + reg_W_real_0_5 <= 0; + reg_W_imag_0_5 <= 0; + reg_W_real_0_6 <= 0; + reg_W_imag_0_6 <= 0; + reg_W_real_0_7 <= 0; + reg_W_imag_0_7 <= 0; + reg_W_real_0_8 <= 0; + reg_W_imag_0_8 <= 0; + reg_W_real_1_0 <= 0; + reg_W_imag_1_0 <= 0; + reg_W_real_1_1 <= 0; + reg_W_imag_1_1 <= 0; + reg_W_real_1_2 <= 0; + reg_W_imag_1_2 <= 0; + reg_W_real_1_3 <= 0; + reg_W_imag_1_3 <= 0; + reg_W_real_1_4 <= 0; + reg_W_imag_1_4 <= 0; + reg_W_real_1_5 <= 0; + reg_W_imag_1_5 <= 0; + reg_W_real_1_6 <= 0; + reg_W_imag_1_6 <= 0; + reg_W_real_1_7 <= 0; + reg_W_imag_1_7 <= 0; + reg_W_real_1_8 <= 0; + reg_W_imag_1_8 <= 0; + reg_W_real_2_0 <= 0; + reg_W_imag_2_0 <= 0; + reg_W_real_2_1 <= 0; + reg_W_imag_2_1 <= 0; + reg_W_real_2_2 <= 0; + reg_W_imag_2_2 <= 0; + reg_W_real_2_3 <= 0; + reg_W_imag_2_3 <= 0; + reg_W_real_2_4 <= 0; + reg_W_imag_2_4 <= 0; + reg_W_real_2_5 <= 0; + reg_W_imag_2_5 <= 0; + reg_W_real_2_6 <= 0; + reg_W_imag_2_6 <= 0; + reg_W_real_2_7 <= 0; + reg_W_imag_2_7 <= 0; + reg_W_real_2_8 <= 0; + reg_W_imag_2_8 <= 0; + reg_Y_real_0_0 <= 0; + reg_Y_imag_0_0 <= 0; + reg_Y_real_0_1 <= 0; + reg_Y_imag_0_1 <= 0; + reg_Y_real_0_2 <= 0; + reg_Y_imag_0_2 <= 0; + reg_Y_real_0_3 <= 0; + reg_Y_imag_0_3 <= 0; + reg_Y_real_0_4 <= 0; + reg_Y_imag_0_4 <= 0; + reg_Y_real_0_5 <= 0; + reg_Y_imag_0_5 <= 0; + reg_Y_real_0_6 <= 0; + reg_Y_imag_0_6 <= 0; + reg_Y_real_0_7 <= 0; + reg_Y_imag_0_7 <= 0; + reg_Y_real_0_8 <= 0; + reg_Y_imag_0_8 <= 0; + reg_Y_real_0_9 <= 0; + reg_Y_imag_0_9 <= 0; + reg_Y_real_0_10 <= 0; + reg_Y_imag_0_10 <= 0; + reg_Y_real_0_11 <= 0; + reg_Y_imag_0_11 <= 0; + reg_Y_real_0_12 <= 0; + reg_Y_imag_0_12 <= 0; + reg_Y_real_0_13 <= 0; + reg_Y_imag_0_13 <= 0; + reg_Y_real_0_14 <= 0; + reg_Y_imag_0_14 <= 0; + reg_Y_real_0_15 <= 0; + reg_Y_imag_0_15 <= 0; + reg_Y_real_1_0 <= 0; + reg_Y_imag_1_0 <= 0; + reg_Y_real_1_1 <= 0; + reg_Y_imag_1_1 <= 0; + reg_Y_real_1_2 <= 0; + reg_Y_imag_1_2 <= 0; + reg_Y_real_1_3 <= 0; + reg_Y_imag_1_3 <= 0; + reg_Y_real_1_4 <= 0; + reg_Y_imag_1_4 <= 0; + reg_Y_real_1_5 <= 0; + reg_Y_imag_1_5 <= 0; + reg_Y_real_1_6 <= 0; + reg_Y_imag_1_6 <= 0; + reg_Y_real_1_7 <= 0; + reg_Y_imag_1_7 <= 0; + reg_Y_real_1_8 <= 0; + reg_Y_imag_1_8 <= 0; + reg_Y_real_1_9 <= 0; + reg_Y_imag_1_9 <= 0; + reg_Y_real_1_10 <= 0; + reg_Y_imag_1_10 <= 0; + reg_Y_real_1_11 <= 0; + reg_Y_imag_1_11 <= 0; + reg_Y_real_1_12 <= 0; + reg_Y_imag_1_12 <= 0; + reg_Y_real_1_13 <= 0; + reg_Y_imag_1_13 <= 0; + reg_Y_real_1_14 <= 0; + reg_Y_imag_1_14 <= 0; + reg_Y_real_1_15 <= 0; + reg_Y_imag_1_15 <= 0; + reg_Y_real_2_0 <= 0; + reg_Y_imag_2_0 <= 0; + reg_Y_real_2_1 <= 0; + reg_Y_imag_2_1 <= 0; + reg_Y_real_2_2 <= 0; + reg_Y_imag_2_2 <= 0; + reg_Y_real_2_3 <= 0; + reg_Y_imag_2_3 <= 0; + reg_Y_real_2_4 <= 0; + reg_Y_imag_2_4 <= 0; + reg_Y_real_2_5 <= 0; + reg_Y_imag_2_5 <= 0; + reg_Y_real_2_6 <= 0; + reg_Y_imag_2_6 <= 0; + reg_Y_real_2_7 <= 0; + reg_Y_imag_2_7 <= 0; + reg_Y_real_2_8 <= 0; + reg_Y_imag_2_8 <= 0; + reg_Y_real_2_9 <= 0; + reg_Y_imag_2_9 <= 0; + reg_Y_real_2_10 <= 0; + reg_Y_imag_2_10 <= 0; + reg_Y_real_2_11 <= 0; + reg_Y_imag_2_11 <= 0; + reg_Y_real_2_12 <= 0; + reg_Y_imag_2_12 <= 0; + reg_Y_real_2_13 <= 0; + reg_Y_imag_2_13 <= 0; + reg_Y_real_2_14 <= 0; + reg_Y_imag_2_14 <= 0; + reg_Y_real_2_15 <= 0; + reg_Y_imag_2_15 <= 0; + end else if (enable) begin + reg_i_valid <= i_valid; + fft_valid <= o_fft_next; + reg_o_valid <= add_y_imag_valid_0 & sub_y_real_valid_0; + reg_o_ready <= ~i_valid & enable; + reg_X_0 <= i_X_0; + reg_X_2_0 <= reg_X_0; + reg_X_1 <= i_X_1; + reg_X_2_1 <= reg_X_1; + reg_X_2 <= i_X_2; + reg_X_2_2 <= reg_X_2; + reg_X_3 <= i_X_3; + reg_X_2_3 <= reg_X_3; + reg_X_4 <= i_X_4; + reg_X_2_4 <= reg_X_4; + reg_X_5 <= i_X_5; + reg_X_2_5 <= reg_X_5; + reg_X_6 <= i_X_6; + reg_X_2_6 <= reg_X_6; + reg_X_7 <= i_X_7; + reg_X_2_7 <= reg_X_7; + reg_X_8 <= i_X_8; + reg_X_2_8 <= reg_X_8; + reg_X_9 <= i_X_9; + reg_X_2_9 <= reg_X_9; + reg_X_10 <= i_X_10; + reg_X_2_10 <= reg_X_10; + reg_X_11 <= i_X_11; + reg_X_2_11 <= reg_X_11; + reg_X_12 <= i_X_12; + reg_X_2_12 <= reg_X_12; + reg_X_13 <= i_X_13; + reg_X_2_13 <= reg_X_13; + reg_X_14 <= i_X_14; + reg_X_2_14 <= reg_X_14; + reg_X_15 <= i_X_15; + reg_X_2_15 <= reg_X_15; + reg_W_real_0_0 <= i_W_real_0_0; + reg_W_imag_0_0 <= i_W_imag_0_0; + reg_W_real_0_1 <= i_W_real_0_1; + reg_W_imag_0_1 <= i_W_imag_0_1; + reg_W_real_0_2 <= i_W_real_0_2; + reg_W_imag_0_2 <= i_W_imag_0_2; + reg_W_real_0_3 <= i_W_real_0_3; + reg_W_imag_0_3 <= i_W_imag_0_3; + reg_W_real_0_4 <= i_W_real_0_4; + reg_W_imag_0_4 <= i_W_imag_0_4; + reg_W_real_0_5 <= i_W_real_0_5; + reg_W_imag_0_5 <= i_W_imag_0_5; + reg_W_real_0_6 <= i_W_real_0_6; + reg_W_imag_0_6 <= i_W_imag_0_6; + reg_W_real_0_7 <= i_W_real_0_7; + reg_W_imag_0_7 <= i_W_imag_0_7; + reg_W_real_0_8 <= i_W_real_0_8; + reg_W_imag_0_8 <= i_W_imag_0_8; + reg_W_real_1_0 <= i_W_real_1_0; + reg_W_imag_1_0 <= i_W_imag_1_0; + reg_W_real_1_1 <= i_W_real_1_1; + reg_W_imag_1_1 <= i_W_imag_1_1; + reg_W_real_1_2 <= i_W_real_1_2; + reg_W_imag_1_2 <= i_W_imag_1_2; + reg_W_real_1_3 <= i_W_real_1_3; + reg_W_imag_1_3 <= i_W_imag_1_3; + reg_W_real_1_4 <= i_W_real_1_4; + reg_W_imag_1_4 <= i_W_imag_1_4; + reg_W_real_1_5 <= i_W_real_1_5; + reg_W_imag_1_5 <= i_W_imag_1_5; + reg_W_real_1_6 <= i_W_real_1_6; + reg_W_imag_1_6 <= i_W_imag_1_6; + reg_W_real_1_7 <= i_W_real_1_7; + reg_W_imag_1_7 <= i_W_imag_1_7; + reg_W_real_1_8 <= i_W_real_1_8; + reg_W_imag_1_8 <= i_W_imag_1_8; + reg_W_real_2_0 <= i_W_real_2_0; + reg_W_imag_2_0 <= i_W_imag_2_0; + reg_W_real_2_1 <= i_W_real_2_1; + reg_W_imag_2_1 <= i_W_imag_2_1; + reg_W_real_2_2 <= i_W_real_2_2; + reg_W_imag_2_2 <= i_W_imag_2_2; + reg_W_real_2_3 <= i_W_real_2_3; + reg_W_imag_2_3 <= i_W_imag_2_3; + reg_W_real_2_4 <= i_W_real_2_4; + reg_W_imag_2_4 <= i_W_imag_2_4; + reg_W_real_2_5 <= i_W_real_2_5; + reg_W_imag_2_5 <= i_W_imag_2_5; + reg_W_real_2_6 <= i_W_real_2_6; + reg_W_imag_2_6 <= i_W_imag_2_6; + reg_W_real_2_7 <= i_W_real_2_7; + reg_W_imag_2_7 <= i_W_imag_2_7; + reg_W_real_2_8 <= i_W_real_2_8; + reg_W_imag_2_8 <= i_W_imag_2_8; + reg_Y_real_0_0 <= o_sub_y_real_0_0; + reg_Y_imag_0_0 <= o_add_y_imag_0_0; + reg_Y_real_0_1 <= o_sub_y_real_0_1; + reg_Y_imag_0_1 <= o_add_y_imag_0_1; + reg_Y_real_0_2 <= o_sub_y_real_0_2; + reg_Y_imag_0_2 <= o_add_y_imag_0_2; + reg_Y_real_0_3 <= o_sub_y_real_0_3; + reg_Y_imag_0_3 <= o_add_y_imag_0_3; + reg_Y_real_0_4 <= o_sub_y_real_0_4; + reg_Y_imag_0_4 <= o_add_y_imag_0_4; + reg_Y_real_0_5 <= o_sub_y_real_0_5; + reg_Y_imag_0_5 <= o_add_y_imag_0_5; + reg_Y_real_0_6 <= o_sub_y_real_0_6; + reg_Y_imag_0_6 <= o_add_y_imag_0_6; + reg_Y_real_0_7 <= o_sub_y_real_0_7; + reg_Y_imag_0_7 <= o_add_y_imag_0_7; + reg_Y_real_0_8 <= o_sub_y_real_0_8; + reg_Y_imag_0_8 <= o_add_y_imag_0_8; + reg_Y_real_0_9 <= o_sub_y_real_0_7; + reg_Y_imag_0_9 <= -o_add_y_imag_0_7; + reg_Y_real_0_10 <= o_sub_y_real_0_6; + reg_Y_imag_0_10 <= -o_add_y_imag_0_6; + reg_Y_real_0_11 <= o_sub_y_real_0_5; + reg_Y_imag_0_11 <= -o_add_y_imag_0_5; + reg_Y_real_0_12 <= o_sub_y_real_0_4; + reg_Y_imag_0_12 <= -o_add_y_imag_0_4; + reg_Y_real_0_13 <= o_sub_y_real_0_3; + reg_Y_imag_0_13 <= -o_add_y_imag_0_3; + reg_Y_real_0_14 <= o_sub_y_real_0_2; + reg_Y_imag_0_14 <= -o_add_y_imag_0_2; + reg_Y_real_0_15 <= o_sub_y_real_0_1; + reg_Y_imag_0_15 <= -o_add_y_imag_0_1; + reg_Y_real_1_0 <= o_sub_y_real_1_0; + reg_Y_imag_1_0 <= o_add_y_imag_1_0; + reg_Y_real_1_1 <= o_sub_y_real_1_1; + reg_Y_imag_1_1 <= o_add_y_imag_1_1; + reg_Y_real_1_2 <= o_sub_y_real_1_2; + reg_Y_imag_1_2 <= o_add_y_imag_1_2; + reg_Y_real_1_3 <= o_sub_y_real_1_3; + reg_Y_imag_1_3 <= o_add_y_imag_1_3; + reg_Y_real_1_4 <= o_sub_y_real_1_4; + reg_Y_imag_1_4 <= o_add_y_imag_1_4; + reg_Y_real_1_5 <= o_sub_y_real_1_5; + reg_Y_imag_1_5 <= o_add_y_imag_1_5; + reg_Y_real_1_6 <= o_sub_y_real_1_6; + reg_Y_imag_1_6 <= o_add_y_imag_1_6; + reg_Y_real_1_7 <= o_sub_y_real_1_7; + reg_Y_imag_1_7 <= o_add_y_imag_1_7; + reg_Y_real_1_8 <= o_sub_y_real_1_8; + reg_Y_imag_1_8 <= o_add_y_imag_1_8; + reg_Y_real_1_9 <= o_sub_y_real_1_7; + reg_Y_imag_1_9 <= -o_add_y_imag_1_7; + reg_Y_real_1_10 <= o_sub_y_real_1_6; + reg_Y_imag_1_10 <= -o_add_y_imag_1_6; + reg_Y_real_1_11 <= o_sub_y_real_1_5; + reg_Y_imag_1_11 <= -o_add_y_imag_1_5; + reg_Y_real_1_12 <= o_sub_y_real_1_4; + reg_Y_imag_1_12 <= -o_add_y_imag_1_4; + reg_Y_real_1_13 <= o_sub_y_real_1_3; + reg_Y_imag_1_13 <= -o_add_y_imag_1_3; + reg_Y_real_1_14 <= o_sub_y_real_1_2; + reg_Y_imag_1_14 <= -o_add_y_imag_1_2; + reg_Y_real_1_15 <= o_sub_y_real_1_1; + reg_Y_imag_1_15 <= -o_add_y_imag_1_1; + reg_Y_real_2_0 <= o_sub_y_real_2_0; + reg_Y_imag_2_0 <= o_add_y_imag_2_0; + reg_Y_real_2_1 <= o_sub_y_real_2_1; + reg_Y_imag_2_1 <= o_add_y_imag_2_1; + reg_Y_real_2_2 <= o_sub_y_real_2_2; + reg_Y_imag_2_2 <= o_add_y_imag_2_2; + reg_Y_real_2_3 <= o_sub_y_real_2_3; + reg_Y_imag_2_3 <= o_add_y_imag_2_3; + reg_Y_real_2_4 <= o_sub_y_real_2_4; + reg_Y_imag_2_4 <= o_add_y_imag_2_4; + reg_Y_real_2_5 <= o_sub_y_real_2_5; + reg_Y_imag_2_5 <= o_add_y_imag_2_5; + reg_Y_real_2_6 <= o_sub_y_real_2_6; + reg_Y_imag_2_6 <= o_add_y_imag_2_6; + reg_Y_real_2_7 <= o_sub_y_real_2_7; + reg_Y_imag_2_7 <= o_add_y_imag_2_7; + reg_Y_real_2_8 <= o_sub_y_real_2_8; + reg_Y_imag_2_8 <= o_add_y_imag_2_8; + reg_Y_real_2_9 <= o_sub_y_real_2_7; + reg_Y_imag_2_9 <= -o_add_y_imag_2_7; + reg_Y_real_2_10 <= o_sub_y_real_2_6; + reg_Y_imag_2_10 <= -o_add_y_imag_2_6; + reg_Y_real_2_11 <= o_sub_y_real_2_5; + reg_Y_imag_2_11 <= -o_add_y_imag_2_5; + reg_Y_real_2_12 <= o_sub_y_real_2_4; + reg_Y_imag_2_12 <= -o_add_y_imag_2_4; + reg_Y_real_2_13 <= o_sub_y_real_2_3; + reg_Y_imag_2_13 <= -o_add_y_imag_2_3; + reg_Y_real_2_14 <= o_sub_y_real_2_2; + reg_Y_imag_2_14 <= -o_add_y_imag_2_2; + reg_Y_real_2_15 <= o_sub_y_real_2_1; + reg_Y_imag_2_15 <= -o_add_y_imag_2_1; + end +end + +assign o_ready = reg_o_ready & i_ready; +assign o_valid = reg_o_valid; +assign o_Y_real_0_0 = reg_Y_real_0_0; +assign o_Y_imag_0_0 = reg_Y_imag_0_0; +assign o_Y_real_0_1 = reg_Y_real_0_1; +assign o_Y_imag_0_1 = reg_Y_imag_0_1; +assign o_Y_real_0_2 = reg_Y_real_0_2; +assign o_Y_imag_0_2 = reg_Y_imag_0_2; +assign o_Y_real_0_3 = reg_Y_real_0_3; +assign o_Y_imag_0_3 = reg_Y_imag_0_3; +assign o_Y_real_0_4 = reg_Y_real_0_4; +assign o_Y_imag_0_4 = reg_Y_imag_0_4; +assign o_Y_real_0_5 = reg_Y_real_0_5; +assign o_Y_imag_0_5 = reg_Y_imag_0_5; +assign o_Y_real_0_6 = reg_Y_real_0_6; +assign o_Y_imag_0_6 = reg_Y_imag_0_6; +assign o_Y_real_0_7 = reg_Y_real_0_7; +assign o_Y_imag_0_7 = reg_Y_imag_0_7; +assign o_Y_real_0_8 = reg_Y_real_0_8; +assign o_Y_imag_0_8 = reg_Y_imag_0_8; +assign o_Y_real_0_9 = reg_Y_real_0_9; +assign o_Y_imag_0_9 = reg_Y_imag_0_9; +assign o_Y_real_0_10 = reg_Y_real_0_10; +assign o_Y_imag_0_10 = reg_Y_imag_0_10; +assign o_Y_real_0_11 = reg_Y_real_0_11; +assign o_Y_imag_0_11 = reg_Y_imag_0_11; +assign o_Y_real_0_12 = reg_Y_real_0_12; +assign o_Y_imag_0_12 = reg_Y_imag_0_12; +assign o_Y_real_0_13 = reg_Y_real_0_13; +assign o_Y_imag_0_13 = reg_Y_imag_0_13; +assign o_Y_real_0_14 = reg_Y_real_0_14; +assign o_Y_imag_0_14 = reg_Y_imag_0_14; +assign o_Y_real_0_15 = reg_Y_real_0_15; +assign o_Y_imag_0_15 = reg_Y_imag_0_15; +assign o_Y_real_1_0 = reg_Y_real_1_0; +assign o_Y_imag_1_0 = reg_Y_imag_1_0; +assign o_Y_real_1_1 = reg_Y_real_1_1; +assign o_Y_imag_1_1 = reg_Y_imag_1_1; +assign o_Y_real_1_2 = reg_Y_real_1_2; +assign o_Y_imag_1_2 = reg_Y_imag_1_2; +assign o_Y_real_1_3 = reg_Y_real_1_3; +assign o_Y_imag_1_3 = reg_Y_imag_1_3; +assign o_Y_real_1_4 = reg_Y_real_1_4; +assign o_Y_imag_1_4 = reg_Y_imag_1_4; +assign o_Y_real_1_5 = reg_Y_real_1_5; +assign o_Y_imag_1_5 = reg_Y_imag_1_5; +assign o_Y_real_1_6 = reg_Y_real_1_6; +assign o_Y_imag_1_6 = reg_Y_imag_1_6; +assign o_Y_real_1_7 = reg_Y_real_1_7; +assign o_Y_imag_1_7 = reg_Y_imag_1_7; +assign o_Y_real_1_8 = reg_Y_real_1_8; +assign o_Y_imag_1_8 = reg_Y_imag_1_8; +assign o_Y_real_1_9 = reg_Y_real_1_9; +assign o_Y_imag_1_9 = reg_Y_imag_1_9; +assign o_Y_real_1_10 = reg_Y_real_1_10; +assign o_Y_imag_1_10 = reg_Y_imag_1_10; +assign o_Y_real_1_11 = reg_Y_real_1_11; +assign o_Y_imag_1_11 = reg_Y_imag_1_11; +assign o_Y_real_1_12 = reg_Y_real_1_12; +assign o_Y_imag_1_12 = reg_Y_imag_1_12; +assign o_Y_real_1_13 = reg_Y_real_1_13; +assign o_Y_imag_1_13 = reg_Y_imag_1_13; +assign o_Y_real_1_14 = reg_Y_real_1_14; +assign o_Y_imag_1_14 = reg_Y_imag_1_14; +assign o_Y_real_1_15 = reg_Y_real_1_15; +assign o_Y_imag_1_15 = reg_Y_imag_1_15; +assign o_Y_real_2_0 = reg_Y_real_2_0; +assign o_Y_imag_2_0 = reg_Y_imag_2_0; +assign o_Y_real_2_1 = reg_Y_real_2_1; +assign o_Y_imag_2_1 = reg_Y_imag_2_1; +assign o_Y_real_2_2 = reg_Y_real_2_2; +assign o_Y_imag_2_2 = reg_Y_imag_2_2; +assign o_Y_real_2_3 = reg_Y_real_2_3; +assign o_Y_imag_2_3 = reg_Y_imag_2_3; +assign o_Y_real_2_4 = reg_Y_real_2_4; +assign o_Y_imag_2_4 = reg_Y_imag_2_4; +assign o_Y_real_2_5 = reg_Y_real_2_5; +assign o_Y_imag_2_5 = reg_Y_imag_2_5; +assign o_Y_real_2_6 = reg_Y_real_2_6; +assign o_Y_imag_2_6 = reg_Y_imag_2_6; +assign o_Y_real_2_7 = reg_Y_real_2_7; +assign o_Y_imag_2_7 = reg_Y_imag_2_7; +assign o_Y_real_2_8 = reg_Y_real_2_8; +assign o_Y_imag_2_8 = reg_Y_imag_2_8; +assign o_Y_real_2_9 = reg_Y_real_2_9; +assign o_Y_imag_2_9 = reg_Y_imag_2_9; +assign o_Y_real_2_10 = reg_Y_real_2_10; +assign o_Y_imag_2_10 = reg_Y_imag_2_10; +assign o_Y_real_2_11 = reg_Y_real_2_11; +assign o_Y_imag_2_11 = reg_Y_imag_2_11; +assign o_Y_real_2_12 = reg_Y_real_2_12; +assign o_Y_imag_2_12 = reg_Y_imag_2_12; +assign o_Y_real_2_13 = reg_Y_real_2_13; +assign o_Y_imag_2_13 = reg_Y_imag_2_13; +assign o_Y_real_2_14 = reg_Y_real_2_14; +assign o_Y_imag_2_14 = reg_Y_imag_2_14; +assign o_Y_real_2_15 = reg_Y_real_2_15; +assign o_Y_imag_2_15 = reg_Y_imag_2_15; + +endmodule + +module shift_register_group_18_910 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input reset +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +endmodule + +module shift_register_unit_18_10 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +reg [17:0] shift_registers_1; +reg [17:0] shift_registers_2; +reg [17:0] shift_registers_3; +reg [17:0] shift_registers_4; +reg [17:0] shift_registers_5; +reg [17:0] shift_registers_6; +reg [17:0] shift_registers_7; +reg [17:0] shift_registers_8; +reg [17:0] shift_registers_9; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + shift_registers_1 <= 18'd0; + shift_registers_2 <= 18'd0; + shift_registers_3 <= 18'd0; + shift_registers_4 <= 18'd0; + shift_registers_5 <= 18'd0; + shift_registers_6 <= 18'd0; + shift_registers_7 <= 18'd0; + shift_registers_8 <= 18'd0; + shift_registers_9 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + shift_registers_3 <= shift_registers_2; + shift_registers_4 <= shift_registers_3; + shift_registers_5 <= shift_registers_4; + shift_registers_6 <= shift_registers_5; + shift_registers_7 <= shift_registers_6; + shift_registers_8 <= shift_registers_7; + shift_registers_9 <= shift_registers_8; + end +end + +assign out = shift_registers_9; + +endmodule + +module dft_16_top_18 ( + input clk, + input reset, + input next, + input [17:0] X0, + output [17:0] Y0, + input [17:0] X1, + output [17:0] Y1, + input [17:0] X2, + output [17:0] Y2, + input [17:0] X3, + output [17:0] Y3, + input [17:0] X4, + output [17:0] Y4, + input [17:0] X5, + output [17:0] Y5, + input [17:0] X6, + output [17:0] Y6, + input [17:0] X7, + output [17:0] Y7, + input [17:0] X8, + output [17:0] Y8, + input [17:0] X9, + output [17:0] Y9, + input [17:0] X10, + output [17:0] Y10, + input [17:0] X11, + output [17:0] Y11, + input [17:0] X12, + output [17:0] Y12, + input [17:0] X13, + output [17:0] Y13, + input [17:0] X14, + output [17:0] Y14, + input [17:0] X15, + output [17:0] Y15, + input [17:0] X16, + output [17:0] Y16, + input [17:0] X17, + output [17:0] Y17, + input [17:0] X18, + output [17:0] Y18, + input [17:0] X19, + output [17:0] Y19, + input [17:0] X20, + output [17:0] Y20, + input [17:0] X21, + output [17:0] Y21, + input [17:0] X22, + output [17:0] Y22, + input [17:0] X23, + output [17:0] Y23, + input [17:0] X24, + output [17:0] Y24, + input [17:0] X25, + output [17:0] Y25, + input [17:0] X26, + output [17:0] Y26, + input [17:0] X27, + output [17:0] Y27, + input [17:0] X28, + output [17:0] Y28, + input [17:0] X29, + output [17:0] Y29, + input [17:0] X30, + output [17:0] Y30, + input [17:0] X31, + output [17:0] Y31, + output next_out +); + +wire [17:0] t0_0; +wire [17:0] t0_1; +wire [17:0] t0_2; +wire [17:0] t0_3; +wire [17:0] t0_4; +wire [17:0] t0_5; +wire [17:0] t0_6; +wire [17:0] t0_7; +wire [17:0] t0_8; +wire [17:0] t0_9; +wire [17:0] t0_10; +wire [17:0] t0_11; +wire [17:0] t0_12; +wire [17:0] t0_13; +wire [17:0] t0_14; +wire [17:0] t0_15; +wire [17:0] t0_16; +wire [17:0] t0_17; +wire [17:0] t0_18; +wire [17:0] t0_19; +wire [17:0] t0_20; +wire [17:0] t0_21; +wire [17:0] t0_22; +wire [17:0] t0_23; +wire [17:0] t0_24; +wire [17:0] t0_25; +wire [17:0] t0_26; +wire [17:0] t0_27; +wire [17:0] t0_28; +wire [17:0] t0_29; +wire [17:0] t0_30; +wire [17:0] t0_31; +wire next_0; +wire [17:0] t1_0; +wire [17:0] t1_1; +wire [17:0] t1_2; +wire [17:0] t1_3; +wire [17:0] t1_4; +wire [17:0] t1_5; +wire [17:0] t1_6; +wire [17:0] t1_7; +wire [17:0] t1_8; +wire [17:0] t1_9; +wire [17:0] t1_10; +wire [17:0] t1_11; +wire [17:0] t1_12; +wire [17:0] t1_13; +wire [17:0] t1_14; +wire [17:0] t1_15; +wire [17:0] t1_16; +wire [17:0] t1_17; +wire [17:0] t1_18; +wire [17:0] t1_19; +wire [17:0] t1_20; +wire [17:0] t1_21; +wire [17:0] t1_22; +wire [17:0] t1_23; +wire [17:0] t1_24; +wire [17:0] t1_25; +wire [17:0] t1_26; +wire [17:0] t1_27; +wire [17:0] t1_28; +wire [17:0] t1_29; +wire [17:0] t1_30; +wire [17:0] t1_31; +wire next_1; +wire [17:0] t2_0; +wire [17:0] t2_1; +wire [17:0] t2_2; +wire [17:0] t2_3; +wire [17:0] t2_4; +wire [17:0] t2_5; +wire [17:0] t2_6; +wire [17:0] t2_7; +wire [17:0] t2_8; +wire [17:0] t2_9; +wire [17:0] t2_10; +wire [17:0] t2_11; +wire [17:0] t2_12; +wire [17:0] t2_13; +wire [17:0] t2_14; +wire [17:0] t2_15; +wire [17:0] t2_16; +wire [17:0] t2_17; +wire [17:0] t2_18; +wire [17:0] t2_19; +wire [17:0] t2_20; +wire [17:0] t2_21; +wire [17:0] t2_22; +wire [17:0] t2_23; +wire [17:0] t2_24; +wire [17:0] t2_25; +wire [17:0] t2_26; +wire [17:0] t2_27; +wire [17:0] t2_28; +wire [17:0] t2_29; +wire [17:0] t2_30; +wire [17:0] t2_31; +wire next_2; + +assign t0_0 = X0; +assign Y0 = t2_0; +assign t0_1 = X1; +assign Y1 = t2_1; +assign t0_2 = X2; +assign Y2 = t2_2; +assign t0_3 = X3; +assign Y3 = t2_3; +assign t0_4 = X4; +assign Y4 = t2_4; +assign t0_5 = X5; +assign Y5 = t2_5; +assign t0_6 = X6; +assign Y6 = t2_6; +assign t0_7 = X7; +assign Y7 = t2_7; +assign t0_8 = X8; +assign Y8 = t2_8; +assign t0_9 = X9; +assign Y9 = t2_9; +assign t0_10 = X10; +assign Y10 = t2_10; +assign t0_11 = X11; +assign Y11 = t2_11; +assign t0_12 = X12; +assign Y12 = t2_12; +assign t0_13 = X13; +assign Y13 = t2_13; +assign t0_14 = X14; +assign Y14 = t2_14; +assign t0_15 = X15; +assign Y15 = t2_15; +assign t0_16 = X16; +assign Y16 = t2_16; +assign t0_17 = X17; +assign Y17 = t2_17; +assign t0_18 = X18; +assign Y18 = t2_18; +assign t0_19 = X19; +assign Y19 = t2_19; +assign t0_20 = X20; +assign Y20 = t2_20; +assign t0_21 = X21; +assign Y21 = t2_21; +assign t0_22 = X22; +assign Y22 = t2_22; +assign t0_23 = X23; +assign Y23 = t2_23; +assign t0_24 = X24; +assign Y24 = t2_24; +assign t0_25 = X25; +assign Y25 = t2_25; +assign t0_26 = X26; +assign Y26 = t2_26; +assign t0_27 = X27; +assign Y27 = t2_27; +assign t0_28 = X28; +assign Y28 = t2_28; +assign t0_29 = X29; +assign Y29 = t2_29; +assign t0_30 = X30; +assign Y30 = t2_30; +assign t0_31 = X31; +assign Y31 = t2_31; +assign next_0 = next; +assign next_out = next_2; +codeBlock88206_18 codeBlock88206_18_inst_nmppgtwxed ( + .clk(clk), + .reset(reset), + .next_in(next_0), + .X0_in(t0_0), + .Y0(t1_0), + .X1_in(t0_1), + .Y1(t1_1), + .X2_in(t0_2), + .Y2(t1_2), + .X3_in(t0_3), + .Y3(t1_3), + .X4_in(t0_4), + .Y4(t1_4), + .X5_in(t0_5), + .Y5(t1_5), + .X6_in(t0_6), + .Y6(t1_6), + .X7_in(t0_7), + .Y7(t1_7), + .X8_in(t0_8), + .Y8(t1_8), + .X9_in(t0_9), + .Y9(t1_9), + .X10_in(t0_10), + .Y10(t1_10), + .X11_in(t0_11), + .Y11(t1_11), + .X12_in(t0_12), + .Y12(t1_12), + .X13_in(t0_13), + .Y13(t1_13), + .X14_in(t0_14), + .Y14(t1_14), + .X15_in(t0_15), + .Y15(t1_15), + .X16_in(t0_16), + .Y16(t1_16), + .X17_in(t0_17), + .Y17(t1_17), + .X18_in(t0_18), + .Y18(t1_18), + .X19_in(t0_19), + .Y19(t1_19), + .X20_in(t0_20), + .Y20(t1_20), + .X21_in(t0_21), + .Y21(t1_21), + .X22_in(t0_22), + .Y22(t1_22), + .X23_in(t0_23), + .Y23(t1_23), + .X24_in(t0_24), + .Y24(t1_24), + .X25_in(t0_25), + .Y25(t1_25), + .X26_in(t0_26), + .Y26(t1_26), + .X27_in(t0_27), + .Y27(t1_27), + .X28_in(t0_28), + .Y28(t1_28), + .X29_in(t0_29), + .Y29(t1_29), + .X30_in(t0_30), + .Y30(t1_30), + .X31_in(t0_31), + .Y31(t1_31), + .next_out(next_1) +); + +codeBlock89324_18 codeBlock89324_18_inst_rwaouyiftm ( + .clk(clk), + .reset(reset), + .next_in(next_1), + .X0_in(t1_0), + .Y0(t2_0), + .X1_in(t1_1), + .Y1(t2_1), + .X2_in(t1_2), + .Y2(t2_2), + .X3_in(t1_3), + .Y3(t2_3), + .X4_in(t1_4), + .Y4(t2_4), + .X5_in(t1_5), + .Y5(t2_5), + .X6_in(t1_6), + .Y6(t2_6), + .X7_in(t1_7), + .Y7(t2_7), + .X8_in(t1_8), + .Y8(t2_8), + .X9_in(t1_9), + .Y9(t2_9), + .X10_in(t1_10), + .Y10(t2_10), + .X11_in(t1_11), + .Y11(t2_11), + .X12_in(t1_12), + .Y12(t2_12), + .X13_in(t1_13), + .Y13(t2_13), + .X14_in(t1_14), + .Y14(t2_14), + .X15_in(t1_15), + .Y15(t2_15), + .X16_in(t1_16), + .Y16(t2_16), + .X17_in(t1_17), + .Y17(t2_17), + .X18_in(t1_18), + .Y18(t2_18), + .X19_in(t1_19), + .Y19(t2_19), + .X20_in(t1_20), + .Y20(t2_20), + .X21_in(t1_21), + .Y21(t2_21), + .X22_in(t1_22), + .Y22(t2_22), + .X23_in(t1_23), + .Y23(t2_23), + .X24_in(t1_24), + .Y24(t2_24), + .X25_in(t1_25), + .Y25(t2_25), + .X26_in(t1_26), + .Y26(t2_26), + .X27_in(t1_27), + .Y27(t2_27), + .X28_in(t1_28), + .Y28(t2_28), + .X29_in(t1_29), + .Y29(t2_29), + .X30_in(t1_30), + .Y30(t2_30), + .X31_in(t1_31), + .Y31(t2_31), + .next_out(next_2) +); + +endmodule + +module codeBlock88206_18 ( + input clk, + input reset, + input next_in, + input [17:0] X0_in, + output [17:0] Y0, + input [17:0] X1_in, + output [17:0] Y1, + input [17:0] X2_in, + output [17:0] Y2, + input [17:0] X3_in, + output [17:0] Y3, + input [17:0] X4_in, + output [17:0] Y4, + input [17:0] X5_in, + output [17:0] Y5, + input [17:0] X6_in, + output [17:0] Y6, + input [17:0] X7_in, + output [17:0] Y7, + input [17:0] X8_in, + output [17:0] Y8, + input [17:0] X9_in, + output [17:0] Y9, + input [17:0] X10_in, + output [17:0] Y10, + input [17:0] X11_in, + output [17:0] Y11, + input [17:0] X12_in, + output [17:0] Y12, + input [17:0] X13_in, + output [17:0] Y13, + input [17:0] X14_in, + output [17:0] Y14, + input [17:0] X15_in, + output [17:0] Y15, + input [17:0] X16_in, + output [17:0] Y16, + input [17:0] X17_in, + output [17:0] Y17, + input [17:0] X18_in, + output [17:0] Y18, + input [17:0] X19_in, + output [17:0] Y19, + input [17:0] X20_in, + output [17:0] Y20, + input [17:0] X21_in, + output [17:0] Y21, + input [17:0] X22_in, + output [17:0] Y22, + input [17:0] X23_in, + output [17:0] Y23, + input [17:0] X24_in, + output [17:0] Y24, + input [17:0] X25_in, + output [17:0] Y25, + input [17:0] X26_in, + output [17:0] Y26, + input [17:0] X27_in, + output [17:0] Y27, + input [17:0] X28_in, + output [17:0] Y28, + input [17:0] X29_in, + output [17:0] Y29, + input [17:0] X30_in, + output [17:0] Y30, + input [17:0] X31_in, + output [17:0] Y31, + output next_out +); + +reg next; +reg [17:0] X0; +reg [17:0] X1; +reg [17:0] X2; +reg [17:0] X3; +reg [17:0] X4; +reg [17:0] X5; +reg [17:0] X6; +reg [17:0] X7; +reg [17:0] X8; +reg [17:0] X9; +reg [17:0] X10; +reg [17:0] X11; +reg [17:0] X12; +reg [17:0] X13; +reg [17:0] X14; +reg [17:0] X15; +reg [17:0] X16; +reg [17:0] X17; +reg [17:0] X18; +reg [17:0] X19; +reg [17:0] X20; +reg [17:0] X21; +reg [17:0] X22; +reg [17:0] X23; +reg [17:0] X24; +reg [17:0] X25; +reg [17:0] X26; +reg [17:0] X27; +reg [17:0] X28; +reg [17:0] X29; +reg [17:0] X30; +reg [17:0] X31; +shiftRegFIFO_5_1 shiftRegFIFO_5_1_inst_ogohvqmsqq ( + .X(next), + .Y(next_out), + .reset(reset), + .clk(clk) +); +wire [17:0] a249; + wire [17:0] a250; + wire [17:0] a251; + wire [17:0] a252; + wire [17:0] a257; + wire [17:0] a258; + wire [17:0] a259; + wire [17:0] a260; + wire [17:0] a265; + wire [17:0] a266; + wire [17:0] a267; + wire [17:0] a268; + wire [17:0] a273; + wire [17:0] a274; + wire [17:0] a275; + wire [17:0] a276; + wire [17:0] a281; + wire [17:0] a282; + wire [17:0] a283; + wire [17:0] a284; + wire [17:0] a289; + wire [17:0] a290; + wire [17:0] a291; + wire [17:0] a292; + wire [17:0] a297; + wire [17:0] a298; + wire [17:0] a299; + wire [17:0] a300; + wire [17:0] a305; + wire [17:0] a306; + wire [17:0] a307; + wire [17:0] a308; + wire [17:0] t914; + wire [17:0] t915; + wire [17:0] t916; + wire [17:0] t917; + wire [17:0] t918; + wire [17:0] t919; + wire [17:0] t920; + wire [17:0] t921; + wire [17:0] t930; + wire [17:0] t931; + wire [17:0] t932; + wire [17:0] t933; + wire [17:0] t934; + wire [17:0] t935; + wire [17:0] t936; + wire [17:0] t937; + wire [17:0] t952; + wire [17:0] t953; + wire [17:0] t954; + wire [17:0] t955; + wire [17:0] t956; + wire [17:0] t957; + wire [17:0] t958; + wire [17:0] t959; + wire [17:0] t972; + wire [17:0] t973; + wire [17:0] t974; + wire [17:0] t975; + wire [17:0] t976; + wire [17:0] t977; + wire [17:0] t978; + wire [17:0] t979; + wire [17:0] t922; + wire [17:0] t923; + wire [17:0] t924; + wire [17:0] t925; + wire [17:0] t926; + wire [17:0] t927; + wire [17:0] t928; + wire [17:0] t929; + wire [17:0] t938; + wire [17:0] t939; + wire [17:0] t940; + wire [17:0] t941; + wire [17:0] t944; + wire [17:0] t945; + wire [17:0] t946; + wire [17:0] t947; + wire [17:0] t960; + wire [17:0] t961; + wire [17:0] t962; + wire [17:0] t963; + wire [17:0] t964; + wire [17:0] t965; + wire [17:0] t966; + wire [17:0] t967; + wire [17:0] t980; + wire [17:0] t981; + wire [17:0] t982; + wire [17:0] t983; + wire [17:0] t986; + wire [17:0] t987; + wire [17:0] t988; + wire [17:0] t989; + reg [17:0] tm24; + reg [17:0] tm27; + reg [17:0] tm30; + reg [17:0] tm33; + reg [17:0] tm36; + reg [17:0] tm39; + reg [17:0] tm42; + reg [17:0] tm45; + reg [17:0] tm48; + reg [17:0] tm51; + reg [17:0] tm54; + reg [17:0] tm57; + reg [17:0] tm60; + reg [17:0] tm63; + reg [17:0] tm66; + reg [17:0] tm69; + wire [17:0] a225; + wire [17:0] a226; + wire [17:0] a227; + wire [17:0] a228; + wire [17:0] a229; + wire [17:0] a230; + wire [17:0] a231; + wire [17:0] a232; + wire [17:0] a233; + wire [17:0] a234; + wire [17:0] a235; + wire [17:0] a236; + wire [17:0] a237; + wire [17:0] a238; + wire [17:0] a239; + wire [17:0] a240; + wire [17:0] a241; + wire [17:0] a242; + wire [17:0] a243; + wire [17:0] a244; + wire [17:0] a245; + wire [17:0] a246; + wire [17:0] a247; + wire [17:0] a248; + reg [17:0] tm25; + reg [17:0] tm28; + reg [17:0] tm31; + reg [17:0] tm34; + reg [17:0] tm37; + reg [17:0] tm40; + reg [17:0] tm43; + reg [17:0] tm46; + reg [17:0] tm49; + reg [17:0] tm52; + reg [17:0] tm55; + reg [17:0] tm58; + reg [17:0] tm61; + reg [17:0] tm64; + reg [17:0] tm67; + reg [17:0] tm70; + wire [17:0] t942; + wire [17:0] t943; + wire [17:0] t948; + wire [17:0] t949; + wire [17:0] t950; + wire [17:0] t951; + wire [17:0] t968; + wire [17:0] t969; + wire [17:0] t970; + wire [17:0] t971; + wire [17:0] t984; + wire [17:0] t985; + wire [17:0] t990; + wire [17:0] t991; + wire [17:0] t992; + wire [17:0] t993; + reg [17:0] tm26; + reg [17:0] tm29; + reg [17:0] tm32; + reg [17:0] tm35; + reg [17:0] tm38; + reg [17:0] tm41; + reg [17:0] tm44; + reg [17:0] tm47; + reg [17:0] tm50; + reg [17:0] tm53; + reg [17:0] tm56; + reg [17:0] tm59; + reg [17:0] tm62; + reg [17:0] tm65; + reg [17:0] tm68; + reg [17:0] tm71; + +wire [17:0] tm0; +assign tm0 = (18'hb505 >> (18-18)); +wire [17:0] tm2; +assign tm2 = (18'hec83 >> (18-18)); +wire [17:0] tm3; +assign tm3 = (18'h61f8 >> (18-18)); + +assign a249 = X0; + assign a250 = X16; + assign a251 = X1; + assign a252 = X17; + assign a257 = X8; + assign a258 = X24; + assign a259 = X9; + assign a260 = X25; + assign a265 = X2; + assign a266 = X18; + assign a267 = X3; + assign a268 = X19; + assign a273 = X10; + assign a274 = X26; + assign a275 = X11; + assign a276 = X27; + assign a281 = X4; + assign a282 = X20; + assign a283 = X5; + assign a284 = X21; + assign a289 = X12; + assign a290 = X28; + assign a291 = X13; + assign a292 = X29; + assign a297 = X6; + assign a298 = X22; + assign a299 = X7; + assign a300 = X23; + assign a305 = X14; + assign a306 = X30; + assign a307 = X15; + assign a308 = X31; + assign Y0 = tm26; + assign Y1 = tm29; + assign Y4 = tm32; + assign Y5 = tm35; + assign Y2 = tm38; + assign Y3 = tm41; + assign Y6 = tm44; + assign Y7 = tm47; + assign Y8 = tm50; + assign Y9 = tm53; + assign Y12 = t942; + assign Y13 = t943; + assign Y10 = t948; + assign Y11 = t949; + assign Y14 = t950; + assign Y15 = t951; + assign Y16 = tm56; + assign Y17 = tm59; + assign Y20 = tm62; + assign Y21 = tm65; + assign Y18 = t968; + assign Y19 = t969; + assign Y22 = t970; + assign Y23 = (~(t971)+1'b1); + assign Y24 = tm68; + assign Y25 = tm71; + assign Y28 = t984; + assign Y29 = (~(t985)+1'b1); + assign Y26 = t990; + assign Y27 = t991; + assign Y30 = (~(t992)+1'b1); + assign Y31 = t993; + +addfxp_18_1 add88218(.a(a249), .b(a250), .clk(clk), .q(t914)); + addfxp_18_1 add88233(.a(a251), .b(a252), .clk(clk), .q(t915)); + subfxp_18_1 sub88248(.a(a249), .b(a250), .clk(clk), .q(t916)); + subfxp_18_1 sub88263(.a(a251), .b(a252), .clk(clk), .q(t917)); + addfxp_18_1 add88278(.a(a257), .b(a258), .clk(clk), .q(t918)); + addfxp_18_1 add88293(.a(a259), .b(a260), .clk(clk), .q(t919)); + subfxp_18_1 sub88308(.a(a257), .b(a258), .clk(clk), .q(t920)); + subfxp_18_1 sub88323(.a(a259), .b(a260), .clk(clk), .q(t921)); + addfxp_18_1 add88426(.a(a265), .b(a266), .clk(clk), .q(t930)); + addfxp_18_1 add88441(.a(a267), .b(a268), .clk(clk), .q(t931)); + subfxp_18_1 sub88456(.a(a265), .b(a266), .clk(clk), .q(t932)); + subfxp_18_1 sub88471(.a(a267), .b(a268), .clk(clk), .q(t933)); + addfxp_18_1 add88486(.a(a273), .b(a274), .clk(clk), .q(t934)); + addfxp_18_1 add88501(.a(a275), .b(a276), .clk(clk), .q(t935)); + subfxp_18_1 sub88516(.a(a273), .b(a274), .clk(clk), .q(t936)); + subfxp_18_1 sub88531(.a(a275), .b(a276), .clk(clk), .q(t937)); + addfxp_18_1 add88746(.a(a281), .b(a282), .clk(clk), .q(t952)); + addfxp_18_1 add88761(.a(a283), .b(a284), .clk(clk), .q(t953)); + subfxp_18_1 sub88776(.a(a281), .b(a282), .clk(clk), .q(t954)); + subfxp_18_1 sub88791(.a(a283), .b(a284), .clk(clk), .q(t955)); + addfxp_18_1 add88806(.a(a289), .b(a290), .clk(clk), .q(t956)); + addfxp_18_1 add88821(.a(a291), .b(a292), .clk(clk), .q(t957)); + subfxp_18_1 sub88836(.a(a289), .b(a290), .clk(clk), .q(t958)); + subfxp_18_1 sub88851(.a(a291), .b(a292), .clk(clk), .q(t959)); + addfxp_18_1 add89012(.a(a297), .b(a298), .clk(clk), .q(t972)); + addfxp_18_1 add89027(.a(a299), .b(a300), .clk(clk), .q(t973)); + subfxp_18_1 sub89042(.a(a297), .b(a298), .clk(clk), .q(t974)); + subfxp_18_1 sub89057(.a(a299), .b(a300), .clk(clk), .q(t975)); + addfxp_18_1 add89072(.a(a305), .b(a306), .clk(clk), .q(t976)); + addfxp_18_1 add89087(.a(a307), .b(a308), .clk(clk), .q(t977)); + subfxp_18_1 sub89102(.a(a305), .b(a306), .clk(clk), .q(t978)); + subfxp_18_1 sub89117(.a(a307), .b(a308), .clk(clk), .q(t979)); + addfxp_18_1 add88330(.a(t914), .b(t918), .clk(clk), .q(t922)); + addfxp_18_1 add88337(.a(t915), .b(t919), .clk(clk), .q(t923)); + subfxp_18_1 sub88344(.a(t914), .b(t918), .clk(clk), .q(t924)); + subfxp_18_1 sub88351(.a(t915), .b(t919), .clk(clk), .q(t925)); + addfxp_18_1 add88374(.a(t916), .b(t921), .clk(clk), .q(t926)); + subfxp_18_1 sub88381(.a(t917), .b(t920), .clk(clk), .q(t927)); + subfxp_18_1 sub88388(.a(t916), .b(t921), .clk(clk), .q(t928)); + addfxp_18_1 add88395(.a(t917), .b(t920), .clk(clk), .q(t929)); + addfxp_18_1 add88538(.a(t930), .b(t934), .clk(clk), .q(t938)); + addfxp_18_1 add88545(.a(t931), .b(t935), .clk(clk), .q(t939)); + subfxp_18_1 sub88552(.a(t930), .b(t934), .clk(clk), .q(t940)); + subfxp_18_1 sub88559(.a(t931), .b(t935), .clk(clk), .q(t941)); + addfxp_18_1 add88610(.a(t932), .b(t937), .clk(clk), .q(t944)); + subfxp_18_1 sub88617(.a(t933), .b(t936), .clk(clk), .q(t945)); + subfxp_18_1 sub88624(.a(t932), .b(t937), .clk(clk), .q(t946)); + addfxp_18_1 add88631(.a(t933), .b(t936), .clk(clk), .q(t947)); + addfxp_18_1 add88858(.a(t952), .b(t956), .clk(clk), .q(t960)); + addfxp_18_1 add88865(.a(t953), .b(t957), .clk(clk), .q(t961)); + subfxp_18_1 sub88872(.a(t952), .b(t956), .clk(clk), .q(t962)); + subfxp_18_1 sub88879(.a(t953), .b(t957), .clk(clk), .q(t963)); + addfxp_18_1 add88903(.a(t954), .b(t959), .clk(clk), .q(t964)); + subfxp_18_1 sub88910(.a(t955), .b(t958), .clk(clk), .q(t965)); + subfxp_18_1 sub88917(.a(t954), .b(t959), .clk(clk), .q(t966)); + addfxp_18_1 add88924(.a(t955), .b(t958), .clk(clk), .q(t967)); + addfxp_18_1 add89124(.a(t972), .b(t976), .clk(clk), .q(t980)); + addfxp_18_1 add89131(.a(t973), .b(t977), .clk(clk), .q(t981)); + subfxp_18_1 sub89138(.a(t972), .b(t976), .clk(clk), .q(t982)); + subfxp_18_1 sub89145(.a(t973), .b(t977), .clk(clk), .q(t983)); + addfxp_18_1 add89197(.a(t974), .b(t979), .clk(clk), .q(t986)); + subfxp_18_1 sub89204(.a(t975), .b(t978), .clk(clk), .q(t987)); + subfxp_18_1 sub89211(.a(t974), .b(t979), .clk(clk), .q(t988)); + addfxp_18_1 add89218(.a(t975), .b(t978), .clk(clk), .q(t989)); + +multfix_alt_dsp_18 m88566(.ax(tm0), .ay(t940), .bx(tm0), .by(t941), .clk(clk), .a_q_sc(a225), .a_q_unsc(), .b_q_sc(a226), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88570(.ax(tm2), .ay(t944), .bx(tm3), .by(t945), .clk(clk), .a_q_sc(a227), .a_q_unsc(), .b_q_sc(a228), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88572(.ax(tm2), .ay(t945), .bx(tm3), .by(t944), .clk(clk), .a_q_sc(a229), .a_q_unsc(), .b_q_sc(a230), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88574(.ax(tm3), .ay(t946), .bx(tm2), .by(t947), .clk(clk), .a_q_sc(a231), .a_q_unsc(), .b_q_sc(a232), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88576(.ax(tm3), .ay(t947), .bx(tm2), .by(t946), .clk(clk), .a_q_sc(a233), .a_q_unsc(), .b_q_sc(a234), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88578(.ax(tm0), .ay(t964), .bx(tm0), .by(t965), .clk(clk), .a_q_sc(a235), .a_q_unsc(), .b_q_sc(a236), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88580(.ax(tm0), .ay(t967), .bx(tm0), .by(t966), .clk(clk), .a_q_sc(a237), .a_q_unsc(), .b_q_sc(a238), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88582(.ax(tm0), .ay(t983), .bx(tm0), .by(t982), .clk(clk), .a_q_sc(a239), .a_q_unsc(), .b_q_sc(a240), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88584(.ax(tm3), .ay(t986), .bx(tm2), .by(t987), .clk(clk), .a_q_sc(a241), .a_q_unsc(), .b_q_sc(a242), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88586(.ax(tm3), .ay(t987), .bx(tm2), .by(t986), .clk(clk), .a_q_sc(a243), .a_q_unsc(), .b_q_sc(a244), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88588(.ax(tm2), .ay(t988), .bx(tm3), .by(t989), .clk(clk), .a_q_sc(a245), .a_q_unsc(), .b_q_sc(a246), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88590(.ax(tm3), .ay(t988), .bx(tm2), .by(t989), .clk(clk), .a_q_sc(a247), .a_q_unsc(), .b_q_sc(a248), .b_q_unsc(), .rst(reset)); + +addfxp_18_1 add88580(.a(a225), .b(a226), .clk(clk), .q(t942)); + subfxp_18_1 sub88587(.a(a226), .b(a225), .clk(clk), .q(t943)); + addfxp_18_1 add88652(.a(a227), .b(a228), .clk(clk), .q(t948)); + subfxp_18_1 sub88673(.a(a229), .b(a230), .clk(clk), .q(t949)); + addfxp_18_1 add88694(.a(a231), .b(a232), .clk(clk), .q(t950)); + subfxp_18_1 sub88715(.a(a233), .b(a234), .clk(clk), .q(t951)); + addfxp_18_1 add88945(.a(a235), .b(a236), .clk(clk), .q(t968)); + subfxp_18_1 sub88952(.a(a236), .b(a235), .clk(clk), .q(t969)); + subfxp_18_1 sub88973(.a(a237), .b(a238), .clk(clk), .q(t970)); + addfxp_18_1 add88980(.a(a238), .b(a237), .clk(clk), .q(t971)); + subfxp_18_1 sub89166(.a(a239), .b(a240), .clk(clk), .q(t984)); + addfxp_18_1 add89173(.a(a240), .b(a239), .clk(clk), .q(t985)); + addfxp_18_1 add89239(.a(a241), .b(a242), .clk(clk), .q(t990)); + subfxp_18_1 sub89260(.a(a243), .b(a244), .clk(clk), .q(t991)); + addfxp_18_1 add89281(.a(a245), .b(a246), .clk(clk), .q(t992)); + subfxp_18_1 sub89302(.a(a247), .b(a248), .clk(clk), .q(t993)); + +always @(posedge clk) begin + if (reset == 1) begin + next <= 1'b0; + end else begin + X0 <= X0_in; + X1 <= X1_in; + X2 <= X2_in; + X3 <= X3_in; + X4 <= X4_in; + X5 <= X5_in; + X6 <= X6_in; + X7 <= X7_in; + X8 <= X8_in; + X9 <= X9_in; + X10 <= X10_in; + X11 <= X11_in; + X12 <= X12_in; + X13 <= X13_in; + X14 <= X14_in; + X15 <= X15_in; + X16 <= X16_in; + X17 <= X17_in; + X18 <= X18_in; + X19 <= X19_in; + X20 <= X20_in; + X21 <= X21_in; + X22 <= X22_in; + X23 <= X23_in; + X24 <= X24_in; + X25 <= X25_in; + X26 <= X26_in; + X27 <= X27_in; + X28 <= X28_in; + X29 <= X29_in; + X30 <= X30_in; + X31 <= X31_in; + next <= next_in; + tm24 <= t922; + tm27 <= t923; + tm30 <= t924; + tm33 <= t925; + tm36 <= t926; + tm39 <= t927; + tm42 <= t928; + tm45 <= t929; + tm48 <= t938; + tm51 <= t939; + tm54 <= t960; + tm57 <= t961; + tm60 <= t963; + tm63 <= (~(t962)+1'b1); + tm66 <= t980; + tm69 <= t981; + tm25 <= tm24; + tm28 <= tm27; + tm31 <= tm30; + tm34 <= tm33; + tm37 <= tm36; + tm40 <= tm39; + tm43 <= tm42; + tm46 <= tm45; + tm49 <= tm48; + tm52 <= tm51; + tm55 <= tm54; + tm58 <= tm57; + tm61 <= tm60; + tm64 <= tm63; + tm67 <= tm66; + tm70 <= tm69; + tm26 <= tm25; + tm29 <= tm28; + tm32 <= tm31; + tm35 <= tm34; + tm38 <= tm37; + tm41 <= tm40; + tm44 <= tm43; + tm47 <= tm46; + tm50 <= tm49; + tm53 <= tm52; + tm56 <= tm55; + tm59 <= tm58; + tm62 <= tm61; + tm65 <= tm64; + tm68 <= tm67; + tm71 <= tm70; + end +end + +endmodule + +module shiftRegFIFO_5_1 ( + input [0:0] X, + output [0:0] Y, + input reset, + input clk +); + +reg [0:0] mem_0; +reg [0:0] mem_1; +reg [0:0] mem_2; +reg [0:0] mem_3; +reg [0:0] mem_4; +assign Y = mem_4; + +always @ (posedge clk) begin + if (reset) begin + mem_0 <= 0; + mem_1 <= 0; + mem_2 <= 0; + mem_3 <= 0; + mem_4 <= 0; + end else begin + mem_1 <= mem_0; + mem_2 <= mem_1; + mem_3 <= mem_2; + mem_4 <= mem_3; + mem_0 <= X; + end +end + +endmodule + +module addfxp_18_1 ( + input [17:0] a, + input [17:0] b, + input clk, + output [17:0] q +); + +reg [17:0] res_0; +assign q = res_0; + +always @(posedge clk) begin + res_0 <= a + b; +end + +endmodule + +module subfxp_18_1 ( + input [17:0] a, + input [17:0] b, + input clk, + output [17:0] q +); + +reg [17:0] res_0; +assign q = res_0; + +always @(posedge clk) begin + res_0 <= a + b; +end + +endmodule + +module multfix_alt_dsp_18 ( + input [17:0] ax, + input [17:0] ay, + input [17:0] bx, + input [17:0] by, + input clk, + output [17:0] a_q_sc, + output [17:0] a_q_unsc, + output [17:0] b_q_sc, + output [17:0] b_q_unsc, + input rst +); + +wire [35:0] a_res; +wire [35:0] b_res; + +assign a_q_unsc = a_res[17:0]; +assign a_q_sc = {a_res[35-1], a_res[32 :16]}; +assign b_q_unsc = b_res[17:0]; +assign b_q_sc = {b_res[35-1], b_res[32 :16]}; + +dsp_signed_mult_18x18_unit_18_36_0 dsp_signed_mult_18x18_unit_18_36_0_inst_hhnmjeeeaj ( + .clk(clk), + .ena(1'b1), + .reset(rst), + .i_valid(), + .o_valid(), + .ax(ax), + .ay(ay), + .bx(bx), + .by(by), + .resulta(a_res), + .resultb(b_res) +); + +endmodule + +module dsp_signed_mult_18x18_unit_18_36_0 ( + input clk, + input reset, + input ena, + input i_valid, + input [17:0] ax, + input [17:0] ay, + input [17:0] bx, + input [17:0] by, + output o_valid, + output [35:0] resulta, + output [35:0] resultb +); + +reg [35:0] reg_resa, reg_resb; +reg valid_rr; +always @(posedge clk) begin + if (reset) begin + reg_resa <= 0; + reg_resb <= 0; + valid_rr <= 0; + end else if (ena) begin + reg_resa <= ax * ay; + reg_resb <= bx * by; + valid_rr <= ena; + end +end +assign resulta = reg_resa; +assign resultb = reg_resb; +assign o_valid = valid_rr; +endmodule + +module codeBlock89324_18 ( + input clk, + input reset, + input next_in, + input [17:0] X0_in, + output [17:0] Y0, + input [17:0] X1_in, + output [17:0] Y1, + input [17:0] X2_in, + output [17:0] Y2, + input [17:0] X3_in, + output [17:0] Y3, + input [17:0] X4_in, + output [17:0] Y4, + input [17:0] X5_in, + output [17:0] Y5, + input [17:0] X6_in, + output [17:0] Y6, + input [17:0] X7_in, + output [17:0] Y7, + input [17:0] X8_in, + output [17:0] Y8, + input [17:0] X9_in, + output [17:0] Y9, + input [17:0] X10_in, + output [17:0] Y10, + input [17:0] X11_in, + output [17:0] Y11, + input [17:0] X12_in, + output [17:0] Y12, + input [17:0] X13_in, + output [17:0] Y13, + input [17:0] X14_in, + output [17:0] Y14, + input [17:0] X15_in, + output [17:0] Y15, + input [17:0] X16_in, + output [17:0] Y16, + input [17:0] X17_in, + output [17:0] Y17, + input [17:0] X18_in, + output [17:0] Y18, + input [17:0] X19_in, + output [17:0] Y19, + input [17:0] X20_in, + output [17:0] Y20, + input [17:0] X21_in, + output [17:0] Y21, + input [17:0] X22_in, + output [17:0] Y22, + input [17:0] X23_in, + output [17:0] Y23, + input [17:0] X24_in, + output [17:0] Y24, + input [17:0] X25_in, + output [17:0] Y25, + input [17:0] X26_in, + output [17:0] Y26, + input [17:0] X27_in, + output [17:0] Y27, + input [17:0] X28_in, + output [17:0] Y28, + input [17:0] X29_in, + output [17:0] Y29, + input [17:0] X30_in, + output [17:0] Y30, + input [17:0] X31_in, + output [17:0] Y31, + output next_out +); + +reg next; +reg [17:0] X0; +reg [17:0] X1; +reg [17:0] X2; +reg [17:0] X3; +reg [17:0] X4; +reg [17:0] X5; +reg [17:0] X6; +reg [17:0] X7; +reg [17:0] X8; +reg [17:0] X9; +reg [17:0] X10; +reg [17:0] X11; +reg [17:0] X12; +reg [17:0] X13; +reg [17:0] X14; +reg [17:0] X15; +reg [17:0] X16; +reg [17:0] X17; +reg [17:0] X18; +reg [17:0] X19; +reg [17:0] X20; +reg [17:0] X21; +reg [17:0] X22; +reg [17:0] X23; +reg [17:0] X24; +reg [17:0] X25; +reg [17:0] X26; +reg [17:0] X27; +reg [17:0] X28; +reg [17:0] X29; +reg [17:0] X30; +reg [17:0] X31; + +shiftRegFIFO_2_1 shiftRegFIFO_2_1_inst_itrwkcsijw ( + .X(next), + .Y(next_out), + .reset(reset), + .clk(clk) +); + +wire [17:0] a65; + wire [17:0] a66; + wire [17:0] a67; + wire [17:0] a68; + wire [17:0] a73; + wire [17:0] a74; + wire [17:0] a75; + wire [17:0] a76; + wire [17:0] a81; + wire [17:0] a82; + wire [17:0] a83; + wire [17:0] a84; + wire [17:0] a89; + wire [17:0] a90; + wire [17:0] a91; + wire [17:0] a92; + wire [17:0] a97; + wire [17:0] a98; + wire [17:0] a99; + wire [17:0] a100; + wire [17:0] a105; + wire [17:0] a106; + wire [17:0] a107; + wire [17:0] a108; + wire [17:0] a113; + wire [17:0] a114; + wire [17:0] a115; + wire [17:0] a116; + wire [17:0] a121; + wire [17:0] a122; + wire [17:0] a123; + wire [17:0] a124; + wire [17:0] t402; + wire [17:0] t403; + wire [17:0] t404; + wire [17:0] t405; + wire [17:0] t406; + wire [17:0] t407; + wire [17:0] t408; + wire [17:0] t409; + wire [17:0] t418; + wire [17:0] t419; + wire [17:0] t420; + wire [17:0] t421; + wire [17:0] t422; + wire [17:0] t423; + wire [17:0] t424; + wire [17:0] t425; + wire [17:0] t434; + wire [17:0] t435; + wire [17:0] t436; + wire [17:0] t437; + wire [17:0] t438; + wire [17:0] t439; + wire [17:0] t440; + wire [17:0] t441; + wire [17:0] t450; + wire [17:0] t451; + wire [17:0] t452; + wire [17:0] t453; + wire [17:0] t454; + wire [17:0] t455; + wire [17:0] t456; + wire [17:0] t457; + wire [17:0] t410; + wire [17:0] t411; + wire [17:0] t412; + wire [17:0] t413; + wire [17:0] t414; + wire [17:0] t415; + wire [17:0] t416; + wire [17:0] t417; + wire [17:0] t426; + wire [17:0] t427; + wire [17:0] t428; + wire [17:0] t429; + wire [17:0] t430; + wire [17:0] t431; + wire [17:0] t432; + wire [17:0] t433; + wire [17:0] t442; + wire [17:0] t443; + wire [17:0] t444; + wire [17:0] t445; + wire [17:0] t446; + wire [17:0] t447; + wire [17:0] t448; + wire [17:0] t449; + wire [17:0] t458; + wire [17:0] t459; + wire [17:0] t460; + wire [17:0] t461; + wire [17:0] t462; + wire [17:0] t463; + wire [17:0] t464; + wire [17:0] t465; +assign a65 = X0; + assign a66 = X16; + assign a67 = X1; + assign a68 = X17; + assign a73 = X8; + assign a74 = X24; + assign a75 = X9; + assign a76 = X25; + assign a81 = X2; + assign a82 = X18; + assign a83 = X3; + assign a84 = X19; + assign a89 = X10; + assign a90 = X26; + assign a91 = X11; + assign a92 = X27; + assign a97 = X4; + assign a98 = X20; + assign a99 = X5; + assign a100 = X21; + assign a105 = X12; + assign a106 = X28; + assign a107 = X13; + assign a108 = X29; + assign a113 = X6; + assign a114 = X22; + assign a115 = X7; + assign a116 = X23; + assign a121 = X14; + assign a122 = X30; + assign a123 = X15; + assign a124 = X31; + assign Y0 = t410; + assign Y1 = t411; + assign Y16 = t412; + assign Y17 = t413; + assign Y8 = t414; + assign Y9 = t415; + assign Y24 = t416; + assign Y25 = t417; + assign Y2 = t426; + assign Y3 = t427; + assign Y18 = t428; + assign Y19 = t429; + assign Y10 = t430; + assign Y11 = t431; + assign Y26 = t432; + assign Y27 = t433; + assign Y4 = t442; + assign Y5 = t443; + assign Y20 = t444; + assign Y21 = t445; + assign Y12 = t446; + assign Y13 = t447; + assign Y28 = t448; + assign Y29 = t449; + assign Y6 = t458; + assign Y7 = t459; + assign Y22 = t460; + assign Y23 = t461; + assign Y14 = t462; + assign Y15 = t463; + assign Y30 = t464; + assign Y31 = t465; + +addfxp_18_1 add89336(.a(a65), .b(a66), .clk(clk), .q(t402)); + addfxp_18_1 add89351(.a(a67), .b(a68), .clk(clk), .q(t403)); + subfxp_18_1 sub89366(.a(a65), .b(a66), .clk(clk), .q(t404)); + subfxp_18_1 sub89381(.a(a67), .b(a68), .clk(clk), .q(t405)); + addfxp_18_1 add89396(.a(a73), .b(a74), .clk(clk), .q(t406)); + addfxp_18_1 add89411(.a(a75), .b(a76), .clk(clk), .q(t407)); + subfxp_18_1 sub89426(.a(a73), .b(a74), .clk(clk), .q(t408)); + subfxp_18_1 sub89441(.a(a75), .b(a76), .clk(clk), .q(t409)); + addfxp_18_1 add89544(.a(a81), .b(a82), .clk(clk), .q(t418)); + addfxp_18_1 add89559(.a(a83), .b(a84), .clk(clk), .q(t419)); + subfxp_18_1 sub89574(.a(a81), .b(a82), .clk(clk), .q(t420)); + subfxp_18_1 sub89589(.a(a83), .b(a84), .clk(clk), .q(t421)); + addfxp_18_1 add89604(.a(a89), .b(a90), .clk(clk), .q(t422)); + addfxp_18_1 add89619(.a(a91), .b(a92), .clk(clk), .q(t423)); + subfxp_18_1 sub89634(.a(a89), .b(a90), .clk(clk), .q(t424)); + subfxp_18_1 sub89649(.a(a91), .b(a92), .clk(clk), .q(t425)); + addfxp_18_1 add89752(.a(a97), .b(a98), .clk(clk), .q(t434)); + addfxp_18_1 add89767(.a(a99), .b(a100), .clk(clk), .q(t435)); + subfxp_18_1 sub89782(.a(a97), .b(a98), .clk(clk), .q(t436)); + subfxp_18_1 sub89797(.a(a99), .b(a100), .clk(clk), .q(t437)); + addfxp_18_1 add89812(.a(a105), .b(a106), .clk(clk), .q(t438)); + addfxp_18_1 add89827(.a(a107), .b(a108), .clk(clk), .q(t439)); + subfxp_18_1 sub89842(.a(a105), .b(a106), .clk(clk), .q(t440)); + subfxp_18_1 sub89857(.a(a107), .b(a108), .clk(clk), .q(t441)); + addfxp_18_1 add89960(.a(a113), .b(a114), .clk(clk), .q(t450)); + addfxp_18_1 add89975(.a(a115), .b(a116), .clk(clk), .q(t451)); + subfxp_18_1 sub89990(.a(a113), .b(a114), .clk(clk), .q(t452)); + subfxp_18_1 sub90005(.a(a115), .b(a116), .clk(clk), .q(t453)); + addfxp_18_1 add90020(.a(a121), .b(a122), .clk(clk), .q(t454)); + addfxp_18_1 add90035(.a(a123), .b(a124), .clk(clk), .q(t455)); + subfxp_18_1 sub90050(.a(a121), .b(a122), .clk(clk), .q(t456)); + subfxp_18_1 sub90065(.a(a123), .b(a124), .clk(clk), .q(t457)); + addfxp_18_1 add89448(.a(t402), .b(t406), .clk(clk), .q(t410)); + addfxp_18_1 add89455(.a(t403), .b(t407), .clk(clk), .q(t411)); + subfxp_18_1 sub89462(.a(t402), .b(t406), .clk(clk), .q(t412)); + subfxp_18_1 sub89469(.a(t403), .b(t407), .clk(clk), .q(t413)); + addfxp_18_1 add89492(.a(t404), .b(t409), .clk(clk), .q(t414)); + subfxp_18_1 sub89499(.a(t405), .b(t408), .clk(clk), .q(t415)); + subfxp_18_1 sub89506(.a(t404), .b(t409), .clk(clk), .q(t416)); + addfxp_18_1 add89513(.a(t405), .b(t408), .clk(clk), .q(t417)); + addfxp_18_1 add89656(.a(t418), .b(t422), .clk(clk), .q(t426)); + addfxp_18_1 add89663(.a(t419), .b(t423), .clk(clk), .q(t427)); + subfxp_18_1 sub89670(.a(t418), .b(t422), .clk(clk), .q(t428)); + subfxp_18_1 sub89677(.a(t419), .b(t423), .clk(clk), .q(t429)); + addfxp_18_1 add89700(.a(t420), .b(t425), .clk(clk), .q(t430)); + subfxp_18_1 sub89707(.a(t421), .b(t424), .clk(clk), .q(t431)); + subfxp_18_1 sub89714(.a(t420), .b(t425), .clk(clk), .q(t432)); + addfxp_18_1 add89721(.a(t421), .b(t424), .clk(clk), .q(t433)); + addfxp_18_1 add89864(.a(t434), .b(t438), .clk(clk), .q(t442)); + addfxp_18_1 add89871(.a(t435), .b(t439), .clk(clk), .q(t443)); + subfxp_18_1 sub89878(.a(t434), .b(t438), .clk(clk), .q(t444)); + subfxp_18_1 sub89885(.a(t435), .b(t439), .clk(clk), .q(t445)); + addfxp_18_1 add89908(.a(t436), .b(t441), .clk(clk), .q(t446)); + subfxp_18_1 sub89915(.a(t437), .b(t440), .clk(clk), .q(t447)); + subfxp_18_1 sub89922(.a(t436), .b(t441), .clk(clk), .q(t448)); + addfxp_18_1 add89929(.a(t437), .b(t440), .clk(clk), .q(t449)); + addfxp_18_1 add90072(.a(t450), .b(t454), .clk(clk), .q(t458)); + addfxp_18_1 add90079(.a(t451), .b(t455), .clk(clk), .q(t459)); + subfxp_18_1 sub90086(.a(t450), .b(t454), .clk(clk), .q(t460)); + subfxp_18_1 sub90093(.a(t451), .b(t455), .clk(clk), .q(t461)); + addfxp_18_1 add90116(.a(t452), .b(t457), .clk(clk), .q(t462)); + subfxp_18_1 sub90123(.a(t453), .b(t456), .clk(clk), .q(t463)); + subfxp_18_1 sub90130(.a(t452), .b(t457), .clk(clk), .q(t464)); + addfxp_18_1 add90137(.a(t453), .b(t456), .clk(clk), .q(t465)); + +always @(posedge clk) begin + if (reset == 1) begin + next <= 1'b0; + end else begin + X0 <= X0_in; + X1 <= X1_in; + X2 <= X2_in; + X3 <= X3_in; + X4 <= X4_in; + X5 <= X5_in; + X6 <= X6_in; + X7 <= X7_in; + X8 <= X8_in; + X9 <= X9_in; + X10 <= X10_in; + X11 <= X11_in; + X12 <= X12_in; + X13 <= X13_in; + X14 <= X14_in; + X15 <= X15_in; + X16 <= X16_in; + X17 <= X17_in; + X18 <= X18_in; + X19 <= X19_in; + X20 <= X20_in; + X21 <= X21_in; + X22 <= X22_in; + X23 <= X23_in; + X24 <= X24_in; + X25 <= X25_in; + X26 <= X26_in; + X27 <= X27_in; + X28 <= X28_in; + X29 <= X29_in; + X30 <= X30_in; + X31 <= X31_in; + next <= next_in; + end +end + +endmodule + +module shiftRegFIFO_2_1 ( + input [0:0] X, + output [0:0] Y, + input reset, + input clk +); + +reg [0:0] mem_0; +reg [0:0] mem_1; +reg [0:0] mem_2; +reg [0:0] mem_3; +reg [0:0] mem_4; +assign Y = mem_4; + +always @ (posedge clk) begin + if (reset) begin + mem_0 <= 0; + mem_1 <= 0; + mem_2 <= 0; + mem_3 <= 0; + mem_4 <= 0; + end else begin + mem_1 <= mem_0; + mem_2 <= mem_1; + mem_3 <= mem_2; + mem_4 <= mem_3; + mem_0 <= X; + end +end + +endmodule + +module elementwise_mult_core_18_1810_9_1 ( + input clk, + input reset, + input i_valid, + input i_ready, + input [17:0] i_A_0, + input [17:0] i_B_0, + output [17:0] o_C_0, + input [17:0] i_A_1, + input [17:0] i_B_1, + output [17:0] o_C_1, + input [17:0] i_A_2, + input [17:0] i_B_2, + output [17:0] o_C_2, + input [17:0] i_A_3, + input [17:0] i_B_3, + output [17:0] o_C_3, + input [17:0] i_A_4, + input [17:0] i_B_4, + output [17:0] o_C_4, + input [17:0] i_A_5, + input [17:0] i_B_5, + output [17:0] o_C_5, + input [17:0] i_A_6, + input [17:0] i_B_6, + output [17:0] o_C_6, + input [17:0] i_A_7, + input [17:0] i_B_7, + output [17:0] o_C_7, + input [17:0] i_A_8, + input [17:0] i_B_8, + output [17:0] o_C_8, + output o_valid, + output o_ready +); + +// Store inputs and outputs in registers +reg [17:0] reg_A_0; +reg [17:0] reg_B_0; +wire [17:0] reg_C_0; +reg [17:0] reg_A_1; +reg [17:0] reg_B_1; +wire [17:0] reg_C_1; +reg [17:0] reg_A_2; +reg [17:0] reg_B_2; +wire [17:0] reg_C_2; +reg [17:0] reg_A_3; +reg [17:0] reg_B_3; +wire [17:0] reg_C_3; +reg [17:0] reg_A_4; +reg [17:0] reg_B_4; +wire [17:0] reg_C_4; +reg [17:0] reg_A_5; +reg [17:0] reg_B_5; +wire [17:0] reg_C_5; +reg [17:0] reg_A_6; +reg [17:0] reg_B_6; +wire [17:0] reg_C_6; +reg [17:0] reg_A_7; +reg [17:0] reg_B_7; +wire [17:0] reg_C_7; +reg [17:0] reg_A_8; +reg [17:0] reg_B_8; +wire [17:0] reg_C_8; + +reg valid_A_B; +wire valid_C; +wire enable; +assign enable = i_ready; + +wire mult_valid_0; +wire round_valid_0; +wire [36:0] mult_C_0; +wire [36:0] rounded_C_0; +wire mult_valid_1; +wire round_valid_1; +wire [36:0] mult_C_1; +wire [36:0] rounded_C_1; +wire mult_valid_2; +wire round_valid_2; +wire [36:0] mult_C_2; +wire [36:0] rounded_C_2; +wire mult_valid_3; +wire round_valid_3; +wire [36:0] mult_C_3; +wire [36:0] rounded_C_3; +wire mult_valid_4; +wire round_valid_4; +wire [36:0] mult_C_4; +wire [36:0] rounded_C_4; +wire mult_valid_5; +wire round_valid_5; +wire [36:0] mult_C_5; +wire [36:0] rounded_C_5; +wire mult_valid_6; +wire round_valid_6; +wire [36:0] mult_C_6; +wire [36:0] rounded_C_6; +wire mult_valid_7; +wire round_valid_7; +wire [36:0] mult_C_7; +wire [36:0] rounded_C_7; +wire mult_valid_8; +wire round_valid_8; +wire [36:0] mult_C_8; +wire [36:0] rounded_C_8; + +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst0 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_0), + .ay(reg_B_0), + .bx(reg_A_1), + .by(reg_B_1), + .o_valid(mult_valid_0), + .resulta(mult_C_0), + .resultb(mult_C_1) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst2 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_2), + .ay(reg_B_2), + .bx(reg_A_3), + .by(reg_B_3), + .o_valid(mult_valid_2), + .resulta(mult_C_2), + .resultb(mult_C_3) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst4 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_4), + .ay(reg_B_4), + .bx(reg_A_5), + .by(reg_B_5), + .o_valid(mult_valid_4), + .resulta(mult_C_4), + .resultb(mult_C_5) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst6 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_6), + .ay(reg_B_6), + .bx(reg_A_7), + .by(reg_B_7), + .o_valid(mult_valid_6), + .resulta(mult_C_6), + .resultb(mult_C_7) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst8 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_8), + .ay(reg_B_8), + .bx(), + .by(), + .o_valid(mult_valid_8), + .resulta(mult_C_8), + .resultb() +); +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_0), + .in(mult_C_0), + .o_valid(round_valid_0), + .out(rounded_C_0) +); +assign reg_C_0 = rounded_C_0[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_1), + .in(mult_C_1), + .o_valid(round_valid_1), + .out(rounded_C_1) +); +assign reg_C_1 = rounded_C_1[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_2), + .in(mult_C_2), + .o_valid(round_valid_2), + .out(rounded_C_2) +); +assign reg_C_2 = rounded_C_2[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_3), + .in(mult_C_3), + .o_valid(round_valid_3), + .out(rounded_C_3) +); +assign reg_C_3 = rounded_C_3[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_4), + .in(mult_C_4), + .o_valid(round_valid_4), + .out(rounded_C_4) +); +assign reg_C_4 = rounded_C_4[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_5), + .in(mult_C_5), + .o_valid(round_valid_5), + .out(rounded_C_5) +); +assign reg_C_5 = rounded_C_5[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_6), + .in(mult_C_6), + .o_valid(round_valid_6), + .out(rounded_C_6) +); +assign reg_C_6 = rounded_C_6[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_7), + .in(mult_C_7), + .o_valid(round_valid_7), + .out(rounded_C_7) +); +assign reg_C_7 = rounded_C_7[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_8), + .in(mult_C_8), + .o_valid(round_valid_8), + .out(rounded_C_8) +); +assign reg_C_8 = rounded_C_8[17:0]; +always @ (posedge clk) begin + if (reset) begin + valid_A_B <= 1'b0; + reg_A_0 <= 0; + reg_B_0 <= 0; + reg_A_1 <= 0; + reg_B_1 <= 0; + reg_A_2 <= 0; + reg_B_2 <= 0; + reg_A_3 <= 0; + reg_B_3 <= 0; + reg_A_4 <= 0; + reg_B_4 <= 0; + reg_A_5 <= 0; + reg_B_5 <= 0; + reg_A_6 <= 0; + reg_B_6 <= 0; + reg_A_7 <= 0; + reg_B_7 <= 0; + reg_A_8 <= 0; + reg_B_8 <= 0; + end else if (enable) begin + reg_A_0 <= i_A_0; + reg_B_0 <= i_B_0; + reg_A_1 <= i_A_1; + reg_B_1 <= i_B_1; + reg_A_2 <= i_A_2; + reg_B_2 <= i_B_2; + reg_A_3 <= i_A_3; + reg_B_3 <= i_B_3; + reg_A_4 <= i_A_4; + reg_B_4 <= i_B_4; + reg_A_5 <= i_A_5; + reg_B_5 <= i_B_5; + reg_A_6 <= i_A_6; + reg_B_6 <= i_B_6; + reg_A_7 <= i_A_7; + reg_B_7 <= i_B_7; + reg_A_8 <= i_A_8; + reg_B_8 <= i_B_8; + valid_A_B <= i_valid; + end +end + +assign o_C_0 = reg_C_0; +assign o_C_1 = reg_C_1; +assign o_C_2 = reg_C_2; +assign o_C_3 = reg_C_3; +assign o_C_4 = reg_C_4; +assign o_C_5 = reg_C_5; +assign o_C_6 = reg_C_6; +assign o_C_7 = reg_C_7; +assign o_C_8 = reg_C_8; +assign valid_C = round_valid_0; +assign o_ready = i_ready; +assign o_valid = valid_C & i_ready; + +endmodule + +module dsp_signed_mult_18x18_unit_18_18_1 ( + input clk, + input reset, + input ena, + input i_valid, + input [17:0] ax, + input [17:0] ay, + input [17:0] bx, + input [17:0] by, + output o_valid, + output [36:0] resulta, + output [36:0] resultb +); + +reg [17:0] reg_ax, reg_ay, reg_bx, reg_by; +reg [36:0] reg_resa, reg_resb; +reg valid_r, valid_rr; +always @(posedge clk) begin + if (reset) begin + reg_ax <= 0; + reg_ay <= 0; + reg_bx <= 0; + reg_by <= 0; + reg_resa <= 0; + reg_resb <= 0; + valid_r <= 0; + valid_rr <= 0; + end else begin + reg_ax <= ax; + reg_ay <= ay; + reg_bx <= bx; + reg_by <= by; + reg_resa <= reg_ax * reg_ay; + reg_resb <= reg_bx * reg_by; + valid_r <= ena; + valid_rr <= valid_r; + end +end + +assign resulta = reg_resa; +assign resultb = reg_resb; +assign o_valid = valid_rr; +endmodule + +module fp_rounding_unit_1_37_10 ( + input clk, + input reset, + input enable, + input i_valid, + input [36:0] in, + output [36:0] out, + output o_valid +); + +reg [36:0] rounded_result; +reg [36:0] floor; +reg [36:0] ceil; +reg is_ceil; +reg floor_ceil_valid; + +always @ (*) begin + if (is_ceil) begin + rounded_result = ceil; + end else begin + rounded_result = floor; + end +end + +reg valid_reg; +reg [36:0] out_reg; +always @ (posedge clk) begin + if (reset) begin + is_ceil <= 1'b0; + floor_ceil_valid <= 1'b0; + valid_reg <= 1'b0; + floor <= 0; + ceil <= 0; + out_reg <= 0; + end else if (enable) begin + is_ceil <= in[9]; + floor <= in >>> 10; + ceil <= (in >>> 10) + 1; + floor_ceil_valid <= i_valid; + out_reg <= rounded_result; + valid_reg <= floor_ceil_valid; + end +end + +assign o_valid = valid_reg; + +assign out = out_reg; + +endmodule + +module elementwise_sub_core_18_18_9 ( + input clk, + input reset, + input i_valid, + input i_ready, + input [17:0] i_A_0, + input [17:0] i_B_0, + output [17:0] o_C_0, + input [17:0] i_A_1, + input [17:0] i_B_1, + output [17:0] o_C_1, + input [17:0] i_A_2, + input [17:0] i_B_2, + output [17:0] o_C_2, + input [17:0] i_A_3, + input [17:0] i_B_3, + output [17:0] o_C_3, + input [17:0] i_A_4, + input [17:0] i_B_4, + output [17:0] o_C_4, + input [17:0] i_A_5, + input [17:0] i_B_5, + output [17:0] o_C_5, + input [17:0] i_A_6, + input [17:0] i_B_6, + output [17:0] o_C_6, + input [17:0] i_A_7, + input [17:0] i_B_7, + output [17:0] o_C_7, + input [17:0] i_A_8, + input [17:0] i_B_8, + output [17:0] o_C_8, + output o_valid, + output o_ready +); + +reg [17:0] reg_A_0; +reg [17:0] reg_B_0; +reg [17:0] reg_C_0; +reg [17:0] reg_A_1; +reg [17:0] reg_B_1; +reg [17:0] reg_C_1; +reg [17:0] reg_A_2; +reg [17:0] reg_B_2; +reg [17:0] reg_C_2; +reg [17:0] reg_A_3; +reg [17:0] reg_B_3; +reg [17:0] reg_C_3; +reg [17:0] reg_A_4; +reg [17:0] reg_B_4; +reg [17:0] reg_C_4; +reg [17:0] reg_A_5; +reg [17:0] reg_B_5; +reg [17:0] reg_C_5; +reg [17:0] reg_A_6; +reg [17:0] reg_B_6; +reg [17:0] reg_C_6; +reg [17:0] reg_A_7; +reg [17:0] reg_B_7; +reg [17:0] reg_C_7; +reg [17:0] reg_A_8; +reg [17:0] reg_B_8; +reg [17:0] reg_C_8; + +reg valid_A_B, valid_C; +wire enable; +assign enable = i_ready; + +always @ (posedge clk) begin + if (reset) begin + valid_A_B <= 1'b0; + valid_C <= 1'b0; + reg_A_0 <= 0; + reg_B_0 <= 0; + reg_C_0 <= 0; + reg_A_1 <= 0; + reg_B_1 <= 0; + reg_C_1 <= 0; + reg_A_2 <= 0; + reg_B_2 <= 0; + reg_C_2 <= 0; + reg_A_3 <= 0; + reg_B_3 <= 0; + reg_C_3 <= 0; + reg_A_4 <= 0; + reg_B_4 <= 0; + reg_C_4 <= 0; + reg_A_5 <= 0; + reg_B_5 <= 0; + reg_C_5 <= 0; + reg_A_6 <= 0; + reg_B_6 <= 0; + reg_C_6 <= 0; + reg_A_7 <= 0; + reg_B_7 <= 0; + reg_C_7 <= 0; + reg_A_8 <= 0; + reg_B_8 <= 0; + reg_C_8 <= 0; + end else if (enable) begin + reg_A_0 <= i_A_0; + reg_B_0 <= i_B_0; + reg_C_0 <= reg_A_0 - reg_B_0; + reg_A_1 <= i_A_1; + reg_B_1 <= i_B_1; + reg_C_1 <= reg_A_1 - reg_B_1; + reg_A_2 <= i_A_2; + reg_B_2 <= i_B_2; + reg_C_2 <= reg_A_2 - reg_B_2; + reg_A_3 <= i_A_3; + reg_B_3 <= i_B_3; + reg_C_3 <= reg_A_3 - reg_B_3; + reg_A_4 <= i_A_4; + reg_B_4 <= i_B_4; + reg_C_4 <= reg_A_4 - reg_B_4; + reg_A_5 <= i_A_5; + reg_B_5 <= i_B_5; + reg_C_5 <= reg_A_5 - reg_B_5; + reg_A_6 <= i_A_6; + reg_B_6 <= i_B_6; + reg_C_6 <= reg_A_6 - reg_B_6; + reg_A_7 <= i_A_7; + reg_B_7 <= i_B_7; + reg_C_7 <= reg_A_7 - reg_B_7; + reg_A_8 <= i_A_8; + reg_B_8 <= i_B_8; + reg_C_8 <= reg_A_8 - reg_B_8; + valid_A_B <= i_valid; + valid_C <= valid_A_B; + end +end + +assign o_C_0 = reg_C_0; +assign o_C_1 = reg_C_1; +assign o_C_2 = reg_C_2; +assign o_C_3 = reg_C_3; +assign o_C_4 = reg_C_4; +assign o_C_5 = reg_C_5; +assign o_C_6 = reg_C_6; +assign o_C_7 = reg_C_7; +assign o_C_8 = reg_C_8; +assign o_ready = i_ready; +assign o_valid = valid_C & i_ready; + +endmodule + +module elementwise_add_core_18_18_9 ( + input clk, + input reset, + input i_valid, + input i_ready, + input [17:0] i_A_0, + input [17:0] i_B_0, + output [17:0] o_C_0, + input [17:0] i_A_1, + input [17:0] i_B_1, + output [17:0] o_C_1, + input [17:0] i_A_2, + input [17:0] i_B_2, + output [17:0] o_C_2, + input [17:0] i_A_3, + input [17:0] i_B_3, + output [17:0] o_C_3, + input [17:0] i_A_4, + input [17:0] i_B_4, + output [17:0] o_C_4, + input [17:0] i_A_5, + input [17:0] i_B_5, + output [17:0] o_C_5, + input [17:0] i_A_6, + input [17:0] i_B_6, + output [17:0] o_C_6, + input [17:0] i_A_7, + input [17:0] i_B_7, + output [17:0] o_C_7, + input [17:0] i_A_8, + input [17:0] i_B_8, + output [17:0] o_C_8, + output o_valid, + output o_ready +); + +reg [17:0] reg_A_0; +reg [17:0] reg_B_0; +reg [17:0] reg_C_0; +reg [17:0] reg_A_1; +reg [17:0] reg_B_1; +reg [17:0] reg_C_1; +reg [17:0] reg_A_2; +reg [17:0] reg_B_2; +reg [17:0] reg_C_2; +reg [17:0] reg_A_3; +reg [17:0] reg_B_3; +reg [17:0] reg_C_3; +reg [17:0] reg_A_4; +reg [17:0] reg_B_4; +reg [17:0] reg_C_4; +reg [17:0] reg_A_5; +reg [17:0] reg_B_5; +reg [17:0] reg_C_5; +reg [17:0] reg_A_6; +reg [17:0] reg_B_6; +reg [17:0] reg_C_6; +reg [17:0] reg_A_7; +reg [17:0] reg_B_7; +reg [17:0] reg_C_7; +reg [17:0] reg_A_8; +reg [17:0] reg_B_8; +reg [17:0] reg_C_8; + +reg valid_A_B, valid_C; +wire enable; +assign enable = i_ready; + +always @ (posedge clk) begin + if (reset) begin + valid_A_B <= 1'b0; + valid_C <= 1'b0; + reg_A_0 <= 0; + reg_B_0 <= 0; + reg_C_0 <= 0; + reg_A_1 <= 0; + reg_B_1 <= 0; + reg_C_1 <= 0; + reg_A_2 <= 0; + reg_B_2 <= 0; + reg_C_2 <= 0; + reg_A_3 <= 0; + reg_B_3 <= 0; + reg_C_3 <= 0; + reg_A_4 <= 0; + reg_B_4 <= 0; + reg_C_4 <= 0; + reg_A_5 <= 0; + reg_B_5 <= 0; + reg_C_5 <= 0; + reg_A_6 <= 0; + reg_B_6 <= 0; + reg_C_6 <= 0; + reg_A_7 <= 0; + reg_B_7 <= 0; + reg_C_7 <= 0; + reg_A_8 <= 0; + reg_B_8 <= 0; + reg_C_8 <= 0; + end else if (enable) begin + reg_A_0 <= i_A_0; + reg_B_0 <= i_B_0; + reg_C_0 <= reg_A_0 + reg_B_0; + reg_A_1 <= i_A_1; + reg_B_1 <= i_B_1; + reg_C_1 <= reg_A_1 + reg_B_1; + reg_A_2 <= i_A_2; + reg_B_2 <= i_B_2; + reg_C_2 <= reg_A_2 + reg_B_2; + reg_A_3 <= i_A_3; + reg_B_3 <= i_B_3; + reg_C_3 <= reg_A_3 + reg_B_3; + reg_A_4 <= i_A_4; + reg_B_4 <= i_B_4; + reg_C_4 <= reg_A_4 + reg_B_4; + reg_A_5 <= i_A_5; + reg_B_5 <= i_B_5; + reg_C_5 <= reg_A_5 + reg_B_5; + reg_A_6 <= i_A_6; + reg_B_6 <= i_B_6; + reg_C_6 <= reg_A_6 + reg_B_6; + reg_A_7 <= i_A_7; + reg_B_7 <= i_B_7; + reg_C_7 <= reg_A_7 + reg_B_7; + reg_A_8 <= i_A_8; + reg_B_8 <= i_B_8; + reg_C_8 <= reg_A_8 + reg_B_8; + valid_A_B <= i_valid; + valid_C <= valid_A_B; + end +end + +assign o_C_0 = reg_C_0; +assign o_C_1 = reg_C_1; +assign o_C_2 = reg_C_2; +assign o_C_3 = reg_C_3; +assign o_C_4 = reg_C_4; +assign o_C_5 = reg_C_5; +assign o_C_6 = reg_C_6; +assign o_C_7 = reg_C_7; +assign o_C_8 = reg_C_8; +assign o_ready = i_ready; +assign o_valid = valid_C & i_ready; + +endmodule + +module sum_complex_vector_unit_18_18_16_42 ( + input clk, + input clr, + input i_valid, + input enable, + input [17:0] i_real_0, + input [17:0] i_imag_0, + output [17:0] o_real_0, + output [17:0] o_imag_0, + input [17:0] i_real_1, + input [17:0] i_imag_1, + output [17:0] o_real_1, + output [17:0] o_imag_1, + input [17:0] i_real_2, + input [17:0] i_imag_2, + output [17:0] o_real_2, + output [17:0] o_imag_2, + input [17:0] i_real_3, + input [17:0] i_imag_3, + output [17:0] o_real_3, + output [17:0] o_imag_3, + input [17:0] i_real_4, + input [17:0] i_imag_4, + output [17:0] o_real_4, + output [17:0] o_imag_4, + input [17:0] i_real_5, + input [17:0] i_imag_5, + output [17:0] o_real_5, + output [17:0] o_imag_5, + input [17:0] i_real_6, + input [17:0] i_imag_6, + output [17:0] o_real_6, + output [17:0] o_imag_6, + input [17:0] i_real_7, + input [17:0] i_imag_7, + output [17:0] o_real_7, + output [17:0] o_imag_7, + input [17:0] i_real_8, + input [17:0] i_imag_8, + output [17:0] o_real_8, + output [17:0] o_imag_8, + input [17:0] i_real_9, + input [17:0] i_imag_9, + output [17:0] o_real_9, + output [17:0] o_imag_9, + input [17:0] i_real_10, + input [17:0] i_imag_10, + output [17:0] o_real_10, + output [17:0] o_imag_10, + input [17:0] i_real_11, + input [17:0] i_imag_11, + output [17:0] o_real_11, + output [17:0] o_imag_11, + input [17:0] i_real_12, + input [17:0] i_imag_12, + output [17:0] o_real_12, + output [17:0] o_imag_12, + input [17:0] i_real_13, + input [17:0] i_imag_13, + output [17:0] o_real_13, + output [17:0] o_imag_13, + input [17:0] i_real_14, + input [17:0] i_imag_14, + output [17:0] o_real_14, + output [17:0] o_imag_14, + input [17:0] i_real_15, + input [17:0] i_imag_15, + output [17:0] o_real_15, + output [17:0] o_imag_15, + output o_valid +); + +reg [17:0] sum_real_0; +reg [17:0] sum_imag_0; +reg [17:0] sum_real_1; +reg [17:0] sum_imag_1; +reg [17:0] sum_real_2; +reg [17:0] sum_imag_2; +reg [17:0] sum_real_3; +reg [17:0] sum_imag_3; +reg [17:0] sum_real_4; +reg [17:0] sum_imag_4; +reg [17:0] sum_real_5; +reg [17:0] sum_imag_5; +reg [17:0] sum_real_6; +reg [17:0] sum_imag_6; +reg [17:0] sum_real_7; +reg [17:0] sum_imag_7; +reg [17:0] sum_real_8; +reg [17:0] sum_imag_8; +reg [17:0] sum_real_9; +reg [17:0] sum_imag_9; +reg [17:0] sum_real_10; +reg [17:0] sum_imag_10; +reg [17:0] sum_real_11; +reg [17:0] sum_imag_11; +reg [17:0] sum_real_12; +reg [17:0] sum_imag_12; +reg [17:0] sum_real_13; +reg [17:0] sum_imag_13; +reg [17:0] sum_real_14; +reg [17:0] sum_imag_14; +reg [17:0] sum_real_15; +reg [17:0] sum_imag_15; +reg reg_i_valid; + +// Count the number data in accumulation +reg [13:0] counter; +wire counter_full; +always @ (posedge clk) begin + if (clr) begin + sum_real_0 <= 0; + sum_imag_0 <= 0; + sum_real_1 <= 0; + sum_imag_1 <= 0; + sum_real_2 <= 0; + sum_imag_2 <= 0; + sum_real_3 <= 0; + sum_imag_3 <= 0; + sum_real_4 <= 0; + sum_imag_4 <= 0; + sum_real_5 <= 0; + sum_imag_5 <= 0; + sum_real_6 <= 0; + sum_imag_6 <= 0; + sum_real_7 <= 0; + sum_imag_7 <= 0; + sum_real_8 <= 0; + sum_imag_8 <= 0; + sum_real_9 <= 0; + sum_imag_9 <= 0; + sum_real_10 <= 0; + sum_imag_10 <= 0; + sum_real_11 <= 0; + sum_imag_11 <= 0; + sum_real_12 <= 0; + sum_imag_12 <= 0; + sum_real_13 <= 0; + sum_imag_13 <= 0; + sum_real_14 <= 0; + sum_imag_14 <= 0; + sum_real_15 <= 0; + sum_imag_15 <= 0; + counter <= 14'd0; + reg_i_valid <= 1'b0; + end else if (enable) begin + reg_i_valid <= i_valid; + // Accumulate the number only when data is valid + if (i_valid) begin + if (counter == 42) + counter <= 1; + else + counter <= counter + 1'b1; + + if (counter == 42) begin + sum_real_0 <= i_real_0; + sum_imag_0 <= i_imag_0; + sum_real_1 <= i_real_1; + sum_imag_1 <= i_imag_1; + sum_real_2 <= i_real_2; + sum_imag_2 <= i_imag_2; + sum_real_3 <= i_real_3; + sum_imag_3 <= i_imag_3; + sum_real_4 <= i_real_4; + sum_imag_4 <= i_imag_4; + sum_real_5 <= i_real_5; + sum_imag_5 <= i_imag_5; + sum_real_6 <= i_real_6; + sum_imag_6 <= i_imag_6; + sum_real_7 <= i_real_7; + sum_imag_7 <= i_imag_7; + sum_real_8 <= i_real_8; + sum_imag_8 <= i_imag_8; + sum_real_9 <= i_real_9; + sum_imag_9 <= i_imag_9; + sum_real_10 <= i_real_10; + sum_imag_10 <= i_imag_10; + sum_real_11 <= i_real_11; + sum_imag_11 <= i_imag_11; + sum_real_12 <= i_real_12; + sum_imag_12 <= i_imag_12; + sum_real_13 <= i_real_13; + sum_imag_13 <= i_imag_13; + sum_real_14 <= i_real_14; + sum_imag_14 <= i_imag_14; + sum_real_15 <= i_real_15; + sum_imag_15 <= i_imag_15; + end else begin + sum_real_0 <= sum_real_0 + i_real_0; + sum_imag_0 <= sum_imag_0 + i_imag_0; + sum_real_1 <= sum_real_1 + i_real_1; + sum_imag_1 <= sum_imag_1 + i_imag_1; + sum_real_2 <= sum_real_2 + i_real_2; + sum_imag_2 <= sum_imag_2 + i_imag_2; + sum_real_3 <= sum_real_3 + i_real_3; + sum_imag_3 <= sum_imag_3 + i_imag_3; + sum_real_4 <= sum_real_4 + i_real_4; + sum_imag_4 <= sum_imag_4 + i_imag_4; + sum_real_5 <= sum_real_5 + i_real_5; + sum_imag_5 <= sum_imag_5 + i_imag_5; + sum_real_6 <= sum_real_6 + i_real_6; + sum_imag_6 <= sum_imag_6 + i_imag_6; + sum_real_7 <= sum_real_7 + i_real_7; + sum_imag_7 <= sum_imag_7 + i_imag_7; + sum_real_8 <= sum_real_8 + i_real_8; + sum_imag_8 <= sum_imag_8 + i_imag_8; + sum_real_9 <= sum_real_9 + i_real_9; + sum_imag_9 <= sum_imag_9 + i_imag_9; + sum_real_10 <= sum_real_10 + i_real_10; + sum_imag_10 <= sum_imag_10 + i_imag_10; + sum_real_11 <= sum_real_11 + i_real_11; + sum_imag_11 <= sum_imag_11 + i_imag_11; + sum_real_12 <= sum_real_12 + i_real_12; + sum_imag_12 <= sum_imag_12 + i_imag_12; + sum_real_13 <= sum_real_13 + i_real_13; + sum_imag_13 <= sum_imag_13 + i_imag_13; + sum_real_14 <= sum_real_14 + i_real_14; + sum_imag_14 <= sum_imag_14 + i_imag_14; + sum_real_15 <= sum_real_15 + i_real_15; + sum_imag_15 <= sum_imag_15 + i_imag_15; + end + end + end +end + +assign counter_full = (counter == 42); +assign o_real_0 = sum_real_0; +assign o_imag_0 = sum_imag_0; +assign o_real_1 = sum_real_1; +assign o_imag_1 = sum_imag_1; +assign o_real_2 = sum_real_2; +assign o_imag_2 = sum_imag_2; +assign o_real_3 = sum_real_3; +assign o_imag_3 = sum_imag_3; +assign o_real_4 = sum_real_4; +assign o_imag_4 = sum_imag_4; +assign o_real_5 = sum_real_5; +assign o_imag_5 = sum_imag_5; +assign o_real_6 = sum_real_6; +assign o_imag_6 = sum_imag_6; +assign o_real_7 = sum_real_7; +assign o_imag_7 = sum_imag_7; +assign o_real_8 = sum_real_8; +assign o_imag_8 = sum_imag_8; +assign o_real_9 = sum_real_9; +assign o_imag_9 = sum_imag_9; +assign o_real_10 = sum_real_10; +assign o_imag_10 = sum_imag_10; +assign o_real_11 = sum_real_11; +assign o_imag_11 = sum_imag_11; +assign o_real_12 = sum_real_12; +assign o_imag_12 = sum_imag_12; +assign o_real_13 = sum_real_13; +assign o_imag_13 = sum_imag_13; +assign o_real_14 = sum_real_14; +assign o_imag_14 = sum_imag_14; +assign o_real_15 = sum_real_15; +assign o_imag_15 = sum_imag_15; +assign o_valid = counter_full & reg_i_valid; + +endmodule + +module shift_register_group_18_16_1 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input reset +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +endmodule + +module shift_register_unit_18_1 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + end +end + +assign out = shift_registers_0; + +endmodule + +module idft_16_top_18 ( + input clk, + input reset, + input next, + input [17:0] X0, + output [17:0] Y0, + input [17:0] X1, + output [17:0] Y1, + input [17:0] X2, + output [17:0] Y2, + input [17:0] X3, + output [17:0] Y3, + input [17:0] X4, + output [17:0] Y4, + input [17:0] X5, + output [17:0] Y5, + input [17:0] X6, + output [17:0] Y6, + input [17:0] X7, + output [17:0] Y7, + input [17:0] X8, + output [17:0] Y8, + input [17:0] X9, + output [17:0] Y9, + input [17:0] X10, + output [17:0] Y10, + input [17:0] X11, + output [17:0] Y11, + input [17:0] X12, + output [17:0] Y12, + input [17:0] X13, + output [17:0] Y13, + input [17:0] X14, + output [17:0] Y14, + input [17:0] X15, + output [17:0] Y15, + input [17:0] X16, + output [17:0] Y16, + input [17:0] X17, + output [17:0] Y17, + input [17:0] X18, + output [17:0] Y18, + input [17:0] X19, + output [17:0] Y19, + input [17:0] X20, + output [17:0] Y20, + input [17:0] X21, + output [17:0] Y21, + input [17:0] X22, + output [17:0] Y22, + input [17:0] X23, + output [17:0] Y23, + input [17:0] X24, + output [17:0] Y24, + input [17:0] X25, + output [17:0] Y25, + input [17:0] X26, + output [17:0] Y26, + input [17:0] X27, + output [17:0] Y27, + input [17:0] X28, + output [17:0] Y28, + input [17:0] X29, + output [17:0] Y29, + input [17:0] X30, + output [17:0] Y30, + input [17:0] X31, + output [17:0] Y31, + output next_out +); +wire [17:0] t0_0; +wire [17:0] t0_1; +wire [17:0] t0_2; +wire [17:0] t0_3; +wire [17:0] t0_4; +wire [17:0] t0_5; +wire [17:0] t0_6; +wire [17:0] t0_7; +wire [17:0] t0_8; +wire [17:0] t0_9; +wire [17:0] t0_10; +wire [17:0] t0_11; +wire [17:0] t0_12; +wire [17:0] t0_13; +wire [17:0] t0_14; +wire [17:0] t0_15; +wire [17:0] t0_16; +wire [17:0] t0_17; +wire [17:0] t0_18; +wire [17:0] t0_19; +wire [17:0] t0_20; +wire [17:0] t0_21; +wire [17:0] t0_22; +wire [17:0] t0_23; +wire [17:0] t0_24; +wire [17:0] t0_25; +wire [17:0] t0_26; +wire [17:0] t0_27; +wire [17:0] t0_28; +wire [17:0] t0_29; +wire [17:0] t0_30; +wire [17:0] t0_31; +wire next_0; +wire [17:0] t1_0; +wire [17:0] t1_1; +wire [17:0] t1_2; +wire [17:0] t1_3; +wire [17:0] t1_4; +wire [17:0] t1_5; +wire [17:0] t1_6; +wire [17:0] t1_7; +wire [17:0] t1_8; +wire [17:0] t1_9; +wire [17:0] t1_10; +wire [17:0] t1_11; +wire [17:0] t1_12; +wire [17:0] t1_13; +wire [17:0] t1_14; +wire [17:0] t1_15; +wire [17:0] t1_16; +wire [17:0] t1_17; +wire [17:0] t1_18; +wire [17:0] t1_19; +wire [17:0] t1_20; +wire [17:0] t1_21; +wire [17:0] t1_22; +wire [17:0] t1_23; +wire [17:0] t1_24; +wire [17:0] t1_25; +wire [17:0] t1_26; +wire [17:0] t1_27; +wire [17:0] t1_28; +wire [17:0] t1_29; +wire [17:0] t1_30; +wire [17:0] t1_31; +wire next_1; +wire [17:0] t2_0; +wire [17:0] t2_1; +wire [17:0] t2_2; +wire [17:0] t2_3; +wire [17:0] t2_4; +wire [17:0] t2_5; +wire [17:0] t2_6; +wire [17:0] t2_7; +wire [17:0] t2_8; +wire [17:0] t2_9; +wire [17:0] t2_10; +wire [17:0] t2_11; +wire [17:0] t2_12; +wire [17:0] t2_13; +wire [17:0] t2_14; +wire [17:0] t2_15; +wire [17:0] t2_16; +wire [17:0] t2_17; +wire [17:0] t2_18; +wire [17:0] t2_19; +wire [17:0] t2_20; +wire [17:0] t2_21; +wire [17:0] t2_22; +wire [17:0] t2_23; +wire [17:0] t2_24; +wire [17:0] t2_25; +wire [17:0] t2_26; +wire [17:0] t2_27; +wire [17:0] t2_28; +wire [17:0] t2_29; +wire [17:0] t2_30; +wire [17:0] t2_31; +wire next_2; + +assign t0_0 = X0; +assign Y0 = t2_0; +assign t0_1 = X1; +assign Y1 = t2_1; +assign t0_2 = X2; +assign Y2 = t2_2; +assign t0_3 = X3; +assign Y3 = t2_3; +assign t0_4 = X4; +assign Y4 = t2_4; +assign t0_5 = X5; +assign Y5 = t2_5; +assign t0_6 = X6; +assign Y6 = t2_6; +assign t0_7 = X7; +assign Y7 = t2_7; +assign t0_8 = X8; +assign Y8 = t2_8; +assign t0_9 = X9; +assign Y9 = t2_9; +assign t0_10 = X10; +assign Y10 = t2_10; +assign t0_11 = X11; +assign Y11 = t2_11; +assign t0_12 = X12; +assign Y12 = t2_12; +assign t0_13 = X13; +assign Y13 = t2_13; +assign t0_14 = X14; +assign Y14 = t2_14; +assign t0_15 = X15; +assign Y15 = t2_15; +assign t0_16 = X16; +assign Y16 = t2_16; +assign t0_17 = X17; +assign Y17 = t2_17; +assign t0_18 = X18; +assign Y18 = t2_18; +assign t0_19 = X19; +assign Y19 = t2_19; +assign t0_20 = X20; +assign Y20 = t2_20; +assign t0_21 = X21; +assign Y21 = t2_21; +assign t0_22 = X22; +assign Y22 = t2_22; +assign t0_23 = X23; +assign Y23 = t2_23; +assign t0_24 = X24; +assign Y24 = t2_24; +assign t0_25 = X25; +assign Y25 = t2_25; +assign t0_26 = X26; +assign Y26 = t2_26; +assign t0_27 = X27; +assign Y27 = t2_27; +assign t0_28 = X28; +assign Y28 = t2_28; +assign t0_29 = X29; +assign Y29 = t2_29; +assign t0_30 = X30; +assign Y30 = t2_30; +assign t0_31 = X31; +assign Y31 = t2_31; +assign next_0 = next; +assign next_out = next_2; +codeBlock98050_18 codeBlock98050_18_inst_ogqfpotejt ( + .clk(clk), + .reset(reset), + .next_in(next_0), + .X0_in(t0_0), + .Y0(t1_0), + .X1_in(t0_1), + .Y1(t1_1), + .X2_in(t0_2), + .Y2(t1_2), + .X3_in(t0_3), + .Y3(t1_3), + .X4_in(t0_4), + .Y4(t1_4), + .X5_in(t0_5), + .Y5(t1_5), + .X6_in(t0_6), + .Y6(t1_6), + .X7_in(t0_7), + .Y7(t1_7), + .X8_in(t0_8), + .Y8(t1_8), + .X9_in(t0_9), + .Y9(t1_9), + .X10_in(t0_10), + .Y10(t1_10), + .X11_in(t0_11), + .Y11(t1_11), + .X12_in(t0_12), + .Y12(t1_12), + .X13_in(t0_13), + .Y13(t1_13), + .X14_in(t0_14), + .Y14(t1_14), + .X15_in(t0_15), + .Y15(t1_15), + .X16_in(t0_16), + .Y16(t1_16), + .X17_in(t0_17), + .Y17(t1_17), + .X18_in(t0_18), + .Y18(t1_18), + .X19_in(t0_19), + .Y19(t1_19), + .X20_in(t0_20), + .Y20(t1_20), + .X21_in(t0_21), + .Y21(t1_21), + .X22_in(t0_22), + .Y22(t1_22), + .X23_in(t0_23), + .Y23(t1_23), + .X24_in(t0_24), + .Y24(t1_24), + .X25_in(t0_25), + .Y25(t1_25), + .X26_in(t0_26), + .Y26(t1_26), + .X27_in(t0_27), + .Y27(t1_27), + .X28_in(t0_28), + .Y28(t1_28), + .X29_in(t0_29), + .Y29(t1_29), + .X30_in(t0_30), + .Y30(t1_30), + .X31_in(t0_31), + .Y31(t1_31), + .next_out(next_1) +); + +codeBlock99168_18 codeBlock99168_18_inst_vcnldneeqs ( + .clk(clk), + .reset(reset), + .next_in(next_1), + .X0_in(t1_0), + .Y0(t2_0), + .X1_in(t1_1), + .Y1(t2_1), + .X2_in(t1_2), + .Y2(t2_2), + .X3_in(t1_3), + .Y3(t2_3), + .X4_in(t1_4), + .Y4(t2_4), + .X5_in(t1_5), + .Y5(t2_5), + .X6_in(t1_6), + .Y6(t2_6), + .X7_in(t1_7), + .Y7(t2_7), + .X8_in(t1_8), + .Y8(t2_8), + .X9_in(t1_9), + .Y9(t2_9), + .X10_in(t1_10), + .Y10(t2_10), + .X11_in(t1_11), + .Y11(t2_11), + .X12_in(t1_12), + .Y12(t2_12), + .X13_in(t1_13), + .Y13(t2_13), + .X14_in(t1_14), + .Y14(t2_14), + .X15_in(t1_15), + .Y15(t2_15), + .X16_in(t1_16), + .Y16(t2_16), + .X17_in(t1_17), + .Y17(t2_17), + .X18_in(t1_18), + .Y18(t2_18), + .X19_in(t1_19), + .Y19(t2_19), + .X20_in(t1_20), + .Y20(t2_20), + .X21_in(t1_21), + .Y21(t2_21), + .X22_in(t1_22), + .Y22(t2_22), + .X23_in(t1_23), + .Y23(t2_23), + .X24_in(t1_24), + .Y24(t2_24), + .X25_in(t1_25), + .Y25(t2_25), + .X26_in(t1_26), + .Y26(t2_26), + .X27_in(t1_27), + .Y27(t2_27), + .X28_in(t1_28), + .Y28(t2_28), + .X29_in(t1_29), + .Y29(t2_29), + .X30_in(t1_30), + .Y30(t2_30), + .X31_in(t1_31), + .Y31(t2_31), + .next_out(next_2) +); + +endmodule + +module codeBlock98050_18 ( + input clk, + input reset, + input next_in, + input [17:0] X0_in, + output [17:0] Y0, + input [17:0] X1_in, + output [17:0] Y1, + input [17:0] X2_in, + output [17:0] Y2, + input [17:0] X3_in, + output [17:0] Y3, + input [17:0] X4_in, + output [17:0] Y4, + input [17:0] X5_in, + output [17:0] Y5, + input [17:0] X6_in, + output [17:0] Y6, + input [17:0] X7_in, + output [17:0] Y7, + input [17:0] X8_in, + output [17:0] Y8, + input [17:0] X9_in, + output [17:0] Y9, + input [17:0] X10_in, + output [17:0] Y10, + input [17:0] X11_in, + output [17:0] Y11, + input [17:0] X12_in, + output [17:0] Y12, + input [17:0] X13_in, + output [17:0] Y13, + input [17:0] X14_in, + output [17:0] Y14, + input [17:0] X15_in, + output [17:0] Y15, + input [17:0] X16_in, + output [17:0] Y16, + input [17:0] X17_in, + output [17:0] Y17, + input [17:0] X18_in, + output [17:0] Y18, + input [17:0] X19_in, + output [17:0] Y19, + input [17:0] X20_in, + output [17:0] Y20, + input [17:0] X21_in, + output [17:0] Y21, + input [17:0] X22_in, + output [17:0] Y22, + input [17:0] X23_in, + output [17:0] Y23, + input [17:0] X24_in, + output [17:0] Y24, + input [17:0] X25_in, + output [17:0] Y25, + input [17:0] X26_in, + output [17:0] Y26, + input [17:0] X27_in, + output [17:0] Y27, + input [17:0] X28_in, + output [17:0] Y28, + input [17:0] X29_in, + output [17:0] Y29, + input [17:0] X30_in, + output [17:0] Y30, + input [17:0] X31_in, + output [17:0] Y31, + output next_out +); + +reg next; +reg [17:0] X0; +reg [17:0] X1; +reg [17:0] X2; +reg [17:0] X3; +reg [17:0] X4; +reg [17:0] X5; +reg [17:0] X6; +reg [17:0] X7; +reg [17:0] X8; +reg [17:0] X9; +reg [17:0] X10; +reg [17:0] X11; +reg [17:0] X12; +reg [17:0] X13; +reg [17:0] X14; +reg [17:0] X15; +reg [17:0] X16; +reg [17:0] X17; +reg [17:0] X18; +reg [17:0] X19; +reg [17:0] X20; +reg [17:0] X21; +reg [17:0] X22; +reg [17:0] X23; +reg [17:0] X24; +reg [17:0] X25; +reg [17:0] X26; +reg [17:0] X27; +reg [17:0] X28; +reg [17:0] X29; +reg [17:0] X30; +reg [17:0] X31; +shiftRegFIFO_5_1 shiftRegFIFO_5_1_inst_tyymvlgqgx ( + .X(next), + .Y(next_out), + .reset(reset), + .clk(clk) +); +wire [17:0] a249; + wire [17:0] a250; + wire [17:0] a251; + wire [17:0] a252; + wire [17:0] a257; + wire [17:0] a258; + wire [17:0] a259; + wire [17:0] a260; + wire [17:0] a265; + wire [17:0] a266; + wire [17:0] a267; + wire [17:0] a268; + wire [17:0] a273; + wire [17:0] a274; + wire [17:0] a275; + wire [17:0] a276; + wire [17:0] a281; + wire [17:0] a282; + wire [17:0] a283; + wire [17:0] a284; + wire [17:0] a289; + wire [17:0] a290; + wire [17:0] a291; + wire [17:0] a292; + wire [17:0] a297; + wire [17:0] a298; + wire [17:0] a299; + wire [17:0] a300; + wire [17:0] a305; + wire [17:0] a306; + wire [17:0] a307; + wire [17:0] a308; + wire [17:0] t914; + wire [17:0] t915; + wire [17:0] t916; + wire [17:0] t917; + wire [17:0] t918; + wire [17:0] t919; + wire [17:0] t920; + wire [17:0] t921; + wire [17:0] t930; + wire [17:0] t931; + wire [17:0] t932; + wire [17:0] t933; + wire [17:0] t934; + wire [17:0] t935; + wire [17:0] t936; + wire [17:0] t937; + wire [17:0] t952; + wire [17:0] t953; + wire [17:0] t954; + wire [17:0] t955; + wire [17:0] t956; + wire [17:0] t957; + wire [17:0] t958; + wire [17:0] t959; + wire [17:0] t972; + wire [17:0] t973; + wire [17:0] t974; + wire [17:0] t975; + wire [17:0] t976; + wire [17:0] t977; + wire [17:0] t978; + wire [17:0] t979; + wire [17:0] t922; + wire [17:0] t923; + wire [17:0] t924; + wire [17:0] t925; + wire [17:0] t926; + wire [17:0] t927; + wire [17:0] t928; + wire [17:0] t929; + wire [17:0] t938; + wire [17:0] t939; + wire [17:0] t940; + wire [17:0] t941; + wire [17:0] t944; + wire [17:0] t945; + wire [17:0] t946; + wire [17:0] t947; + wire [17:0] t960; + wire [17:0] t961; + wire [17:0] t962; + wire [17:0] t963; + wire [17:0] t964; + wire [17:0] t965; + wire [17:0] t966; + wire [17:0] t967; + wire [17:0] t980; + wire [17:0] t981; + wire [17:0] t982; + wire [17:0] t983; + wire [17:0] t986; + wire [17:0] t987; + wire [17:0] t988; + wire [17:0] t989; + reg [17:0] tm24; + reg [17:0] tm27; + reg [17:0] tm30; + reg [17:0] tm33; + reg [17:0] tm36; + reg [17:0] tm39; + reg [17:0] tm42; + reg [17:0] tm45; + reg [17:0] tm48; + reg [17:0] tm51; + reg [17:0] tm54; + reg [17:0] tm57; + reg [17:0] tm60; + reg [17:0] tm63; + reg [17:0] tm66; + reg [17:0] tm69; + wire [17:0] a225; + wire [17:0] a226; + wire [17:0] a227; + wire [17:0] a228; + wire [17:0] a229; + wire [17:0] a230; + wire [17:0] a231; + wire [17:0] a232; + wire [17:0] a233; + wire [17:0] a234; + wire [17:0] a235; + wire [17:0] a236; + wire [17:0] a237; + wire [17:0] a238; + wire [17:0] a239; + wire [17:0] a240; + wire [17:0] a241; + wire [17:0] a242; + wire [17:0] a243; + wire [17:0] a244; + wire [17:0] a245; + wire [17:0] a246; + wire [17:0] a247; + wire [17:0] a248; + reg [17:0] tm25; + reg [17:0] tm28; + reg [17:0] tm31; + reg [17:0] tm34; + reg [17:0] tm37; + reg [17:0] tm40; + reg [17:0] tm43; + reg [17:0] tm46; + reg [17:0] tm49; + reg [17:0] tm52; + reg [17:0] tm55; + reg [17:0] tm58; + reg [17:0] tm61; + reg [17:0] tm64; + reg [17:0] tm67; + reg [17:0] tm70; + wire [17:0] t942; + wire [17:0] t943; + wire [17:0] t948; + wire [17:0] t949; + wire [17:0] t950; + wire [17:0] t951; + wire [17:0] t968; + wire [17:0] t969; + wire [17:0] t970; + wire [17:0] t971; + wire [17:0] t984; + wire [17:0] t985; + wire [17:0] t990; + wire [17:0] t991; + wire [17:0] t992; + wire [17:0] t993; + reg [17:0] tm26; + reg [17:0] tm29; + reg [17:0] tm32; + reg [17:0] tm35; + reg [17:0] tm38; + reg [17:0] tm41; + reg [17:0] tm44; + reg [17:0] tm47; + reg [17:0] tm50; + reg [17:0] tm53; + reg [17:0] tm56; + reg [17:0] tm59; + reg [17:0] tm62; + reg [17:0] tm65; + reg [17:0] tm68; + reg [17:0] tm71; + +wire [17:0] tm0; +assign tm0 = (18'hb505 >> (18-18)); +wire [17:0] tm2; +assign tm2 = (18'hec83 >> (18-18)); +wire [17:0] tm3; +assign tm3 = (18'h61f8 >> (18-18)); + +assign a249 = X0; + assign a250 = X16; + assign a251 = X1; + assign a252 = X17; + assign a257 = X8; + assign a258 = X24; + assign a259 = X9; + assign a260 = X25; + assign a265 = X2; + assign a266 = X18; + assign a267 = X3; + assign a268 = X19; + assign a273 = X10; + assign a274 = X26; + assign a275 = X11; + assign a276 = X27; + assign a281 = X4; + assign a282 = X20; + assign a283 = X5; + assign a284 = X21; + assign a289 = X12; + assign a290 = X28; + assign a291 = X13; + assign a292 = X29; + assign a297 = X6; + assign a298 = X22; + assign a299 = X7; + assign a300 = X23; + assign a305 = X14; + assign a306 = X30; + assign a307 = X15; + assign a308 = X31; + assign Y0 = tm26; + assign Y1 = tm29; + assign Y4 = tm32; + assign Y5 = tm35; + assign Y2 = tm38; + assign Y3 = tm41; + assign Y6 = tm44; + assign Y7 = tm47; + assign Y8 = tm50; + assign Y9 = tm53; + assign Y12 = t942; + assign Y13 = t943; + assign Y10 = t948; + assign Y11 = t949; + assign Y14 = t950; + assign Y15 = t951; + assign Y16 = tm56; + assign Y17 = tm59; + assign Y20 = tm62; + assign Y21 = tm65; + assign Y18 = t968; + assign Y19 = t969; + assign Y22 = (~(t970)+1'b1); + assign Y23 = t971; + assign Y24 = tm68; + assign Y25 = tm71; + assign Y28 = (~(t984)+1'b1); + assign Y29 = t985; + assign Y26 = t990; + assign Y27 = t991; + assign Y30 = t992; + assign Y31 = (~(t993)+1'b1); + +addfxp_18_1 add98062(.a(a249), .b(a250), .clk(clk), .q(t914)); + addfxp_18_1 add98077(.a(a251), .b(a252), .clk(clk), .q(t915)); + subfxp_18_1 sub98092(.a(a249), .b(a250), .clk(clk), .q(t916)); + subfxp_18_1 sub98107(.a(a251), .b(a252), .clk(clk), .q(t917)); + addfxp_18_1 add98122(.a(a257), .b(a258), .clk(clk), .q(t918)); + addfxp_18_1 add98137(.a(a259), .b(a260), .clk(clk), .q(t919)); + subfxp_18_1 sub98152(.a(a257), .b(a258), .clk(clk), .q(t920)); + subfxp_18_1 sub98167(.a(a259), .b(a260), .clk(clk), .q(t921)); + addfxp_18_1 add98270(.a(a265), .b(a266), .clk(clk), .q(t930)); + addfxp_18_1 add98285(.a(a267), .b(a268), .clk(clk), .q(t931)); + subfxp_18_1 sub98300(.a(a265), .b(a266), .clk(clk), .q(t932)); + subfxp_18_1 sub98315(.a(a267), .b(a268), .clk(clk), .q(t933)); + addfxp_18_1 add98330(.a(a273), .b(a274), .clk(clk), .q(t934)); + addfxp_18_1 add98345(.a(a275), .b(a276), .clk(clk), .q(t935)); + subfxp_18_1 sub98360(.a(a273), .b(a274), .clk(clk), .q(t936)); + subfxp_18_1 sub98375(.a(a275), .b(a276), .clk(clk), .q(t937)); + addfxp_18_1 add98590(.a(a281), .b(a282), .clk(clk), .q(t952)); + addfxp_18_1 add98605(.a(a283), .b(a284), .clk(clk), .q(t953)); + subfxp_18_1 sub98620(.a(a281), .b(a282), .clk(clk), .q(t954)); + subfxp_18_1 sub98635(.a(a283), .b(a284), .clk(clk), .q(t955)); + addfxp_18_1 add98650(.a(a289), .b(a290), .clk(clk), .q(t956)); + addfxp_18_1 add98665(.a(a291), .b(a292), .clk(clk), .q(t957)); + subfxp_18_1 sub98680(.a(a289), .b(a290), .clk(clk), .q(t958)); + subfxp_18_1 sub98695(.a(a291), .b(a292), .clk(clk), .q(t959)); + addfxp_18_1 add98856(.a(a297), .b(a298), .clk(clk), .q(t972)); + addfxp_18_1 add98871(.a(a299), .b(a300), .clk(clk), .q(t973)); + subfxp_18_1 sub98886(.a(a297), .b(a298), .clk(clk), .q(t974)); + subfxp_18_1 sub98901(.a(a299), .b(a300), .clk(clk), .q(t975)); + addfxp_18_1 add98916(.a(a305), .b(a306), .clk(clk), .q(t976)); + addfxp_18_1 add98931(.a(a307), .b(a308), .clk(clk), .q(t977)); + subfxp_18_1 sub98946(.a(a305), .b(a306), .clk(clk), .q(t978)); + subfxp_18_1 sub98961(.a(a307), .b(a308), .clk(clk), .q(t979)); + addfxp_18_1 add98174(.a(t914), .b(t918), .clk(clk), .q(t922)); + addfxp_18_1 add98181(.a(t915), .b(t919), .clk(clk), .q(t923)); + subfxp_18_1 sub98188(.a(t914), .b(t918), .clk(clk), .q(t924)); + subfxp_18_1 sub98195(.a(t915), .b(t919), .clk(clk), .q(t925)); + subfxp_18_1 sub98218(.a(t916), .b(t921), .clk(clk), .q(t926)); + addfxp_18_1 add98225(.a(t917), .b(t920), .clk(clk), .q(t927)); + addfxp_18_1 add98232(.a(t916), .b(t921), .clk(clk), .q(t928)); + subfxp_18_1 sub98239(.a(t917), .b(t920), .clk(clk), .q(t929)); + addfxp_18_1 add98382(.a(t930), .b(t934), .clk(clk), .q(t938)); + addfxp_18_1 add98389(.a(t931), .b(t935), .clk(clk), .q(t939)); + subfxp_18_1 sub98396(.a(t930), .b(t934), .clk(clk), .q(t940)); + subfxp_18_1 sub98403(.a(t931), .b(t935), .clk(clk), .q(t941)); + subfxp_18_1 sub98454(.a(t932), .b(t937), .clk(clk), .q(t944)); + addfxp_18_1 add98461(.a(t933), .b(t936), .clk(clk), .q(t945)); + addfxp_18_1 add98468(.a(t932), .b(t937), .clk(clk), .q(t946)); + subfxp_18_1 sub98475(.a(t933), .b(t936), .clk(clk), .q(t947)); + addfxp_18_1 add98702(.a(t952), .b(t956), .clk(clk), .q(t960)); + addfxp_18_1 add98709(.a(t953), .b(t957), .clk(clk), .q(t961)); + subfxp_18_1 sub98716(.a(t952), .b(t956), .clk(clk), .q(t962)); + subfxp_18_1 sub98723(.a(t953), .b(t957), .clk(clk), .q(t963)); + subfxp_18_1 sub98747(.a(t954), .b(t959), .clk(clk), .q(t964)); + addfxp_18_1 add98754(.a(t955), .b(t958), .clk(clk), .q(t965)); + addfxp_18_1 add98761(.a(t954), .b(t959), .clk(clk), .q(t966)); + subfxp_18_1 sub98768(.a(t955), .b(t958), .clk(clk), .q(t967)); + addfxp_18_1 add98968(.a(t972), .b(t976), .clk(clk), .q(t980)); + addfxp_18_1 add98975(.a(t973), .b(t977), .clk(clk), .q(t981)); + subfxp_18_1 sub98982(.a(t972), .b(t976), .clk(clk), .q(t982)); + subfxp_18_1 sub98989(.a(t973), .b(t977), .clk(clk), .q(t983)); + subfxp_18_1 sub99041(.a(t974), .b(t979), .clk(clk), .q(t986)); + addfxp_18_1 add99048(.a(t975), .b(t978), .clk(clk), .q(t987)); + addfxp_18_1 add99055(.a(t974), .b(t979), .clk(clk), .q(t988)); + subfxp_18_1 sub99062(.a(t975), .b(t978), .clk(clk), .q(t989)); + +multfix_alt_dsp_18 m88566(.ax(tm0), .ay(t940), .bx(tm0), .by(t941), .clk(clk), .a_q_sc(a225), .a_q_unsc(), .b_q_sc(a226), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88570(.ax(tm2), .ay(t944), .bx(tm3), .by(t945), .clk(clk), .a_q_sc(a227), .a_q_unsc(), .b_q_sc(a228), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88572(.ax(tm3), .ay(t944), .bx(tm2), .by(t945), .clk(clk), .a_q_sc(a229), .a_q_unsc(), .b_q_sc(a230), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88574(.ax(tm3), .ay(t946), .bx(tm2), .by(t947), .clk(clk), .a_q_sc(a231), .a_q_unsc(), .b_q_sc(a232), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88576(.ax(tm2), .ay(t946), .bx(tm3), .by(t947), .clk(clk), .a_q_sc(a233), .a_q_unsc(), .b_q_sc(a234), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88578(.ax(tm0), .ay(t964), .bx(tm0), .by(t965), .clk(clk), .a_q_sc(a235), .a_q_unsc(), .b_q_sc(a236), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88580(.ax(tm0), .ay(t966), .bx(tm0), .by(t967), .clk(clk), .a_q_sc(a237), .a_q_unsc(), .b_q_sc(a238), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88582(.ax(tm0), .ay(t982), .bx(tm0), .by(t983), .clk(clk), .a_q_sc(a239), .a_q_unsc(), .b_q_sc(a240), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88584(.ax(tm3), .ay(t986), .bx(tm2), .by(t987), .clk(clk), .a_q_sc(a241), .a_q_unsc(), .b_q_sc(a242), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88586(.ax(tm2), .ay(t986), .bx(tm3), .by(t987), .clk(clk), .a_q_sc(a243), .a_q_unsc(), .b_q_sc(a244), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88588(.ax(tm3), .ay(t989), .bx(tm2), .by(t988), .clk(clk), .a_q_sc(a245), .a_q_unsc(), .b_q_sc(a246), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88590(.ax(tm3), .ay(t988), .bx(tm2), .by(t989), .clk(clk), .a_q_sc(a247), .a_q_unsc(), .b_q_sc(a248), .b_q_unsc(), .rst(reset)); + +subfxp_18_1 sub98424(.a(a225), .b(a226), .clk(clk), .q(t942)); + addfxp_18_1 add98431(.a(a225), .b(a226), .clk(clk), .q(t943)); + subfxp_18_1 sub98496(.a(a227), .b(a228), .clk(clk), .q(t948)); + addfxp_18_1 add98517(.a(a229), .b(a230), .clk(clk), .q(t949)); + subfxp_18_1 sub98538(.a(a231), .b(a232), .clk(clk), .q(t950)); + addfxp_18_1 add98559(.a(a233), .b(a234), .clk(clk), .q(t951)); + subfxp_18_1 sub98789(.a(a235), .b(a236), .clk(clk), .q(t968)); + addfxp_18_1 add98796(.a(a235), .b(a236), .clk(clk), .q(t969)); + addfxp_18_1 add98817(.a(a237), .b(a238), .clk(clk), .q(t970)); + subfxp_18_1 sub98824(.a(a237), .b(a238), .clk(clk), .q(t971)); + addfxp_18_1 add99010(.a(a239), .b(a240), .clk(clk), .q(t984)); + subfxp_18_1 sub99017(.a(a239), .b(a240), .clk(clk), .q(t985)); + subfxp_18_1 sub99083(.a(a241), .b(a242), .clk(clk), .q(t990)); + addfxp_18_1 add99104(.a(a243), .b(a244), .clk(clk), .q(t991)); + subfxp_18_1 sub99125(.a(a245), .b(a246), .clk(clk), .q(t992)); + addfxp_18_1 add99146(.a(a247), .b(a248), .clk(clk), .q(t993)); + +always @(posedge clk) begin + if (reset == 1) begin + next <= 1'b0; + end else begin + X0 <= X0_in; + X1 <= X1_in; + X2 <= X2_in; + X3 <= X3_in; + X4 <= X4_in; + X5 <= X5_in; + X6 <= X6_in; + X7 <= X7_in; + X8 <= X8_in; + X9 <= X9_in; + X10 <= X10_in; + X11 <= X11_in; + X12 <= X12_in; + X13 <= X13_in; + X14 <= X14_in; + X15 <= X15_in; + X16 <= X16_in; + X17 <= X17_in; + X18 <= X18_in; + X19 <= X19_in; + X20 <= X20_in; + X21 <= X21_in; + X22 <= X22_in; + X23 <= X23_in; + X24 <= X24_in; + X25 <= X25_in; + X26 <= X26_in; + X27 <= X27_in; + X28 <= X28_in; + X29 <= X29_in; + X30 <= X30_in; + X31 <= X31_in; + next <= next_in; + tm24 <= t922; + tm27 <= t923; + tm30 <= t924; + tm33 <= t925; + tm36 <= t926; + tm39 <= t927; + tm42 <= t928; + tm45 <= t929; + tm48 <= t938; + tm51 <= t939; + tm54 <= t960; + tm57 <= t961; + tm60 <= (~(t963)+1'b1); + tm63 <= t962; + tm66 <= t980; + tm69 <= t981; + tm25 <= tm24; + tm28 <= tm27; + tm31 <= tm30; + tm34 <= tm33; + tm37 <= tm36; + tm40 <= tm39; + tm43 <= tm42; + tm46 <= tm45; + tm49 <= tm48; + tm52 <= tm51; + tm55 <= tm54; + tm58 <= tm57; + tm61 <= tm60; + tm64 <= tm63; + tm67 <= tm66; + tm70 <= tm69; + tm26 <= tm25; + tm29 <= tm28; + tm32 <= tm31; + tm35 <= tm34; + tm38 <= tm37; + tm41 <= tm40; + tm44 <= tm43; + tm47 <= tm46; + tm50 <= tm49; + tm53 <= tm52; + tm56 <= tm55; + tm59 <= tm58; + tm62 <= tm61; + tm65 <= tm64; + tm68 <= tm67; + tm71 <= tm70; + end +end + +endmodule + +module codeBlock99168_18 ( + input clk, + input reset, + input next_in, + input [17:0] X0_in, + output [17:0] Y0, + input [17:0] X1_in, + output [17:0] Y1, + input [17:0] X2_in, + output [17:0] Y2, + input [17:0] X3_in, + output [17:0] Y3, + input [17:0] X4_in, + output [17:0] Y4, + input [17:0] X5_in, + output [17:0] Y5, + input [17:0] X6_in, + output [17:0] Y6, + input [17:0] X7_in, + output [17:0] Y7, + input [17:0] X8_in, + output [17:0] Y8, + input [17:0] X9_in, + output [17:0] Y9, + input [17:0] X10_in, + output [17:0] Y10, + input [17:0] X11_in, + output [17:0] Y11, + input [17:0] X12_in, + output [17:0] Y12, + input [17:0] X13_in, + output [17:0] Y13, + input [17:0] X14_in, + output [17:0] Y14, + input [17:0] X15_in, + output [17:0] Y15, + input [17:0] X16_in, + output [17:0] Y16, + input [17:0] X17_in, + output [17:0] Y17, + input [17:0] X18_in, + output [17:0] Y18, + input [17:0] X19_in, + output [17:0] Y19, + input [17:0] X20_in, + output [17:0] Y20, + input [17:0] X21_in, + output [17:0] Y21, + input [17:0] X22_in, + output [17:0] Y22, + input [17:0] X23_in, + output [17:0] Y23, + input [17:0] X24_in, + output [17:0] Y24, + input [17:0] X25_in, + output [17:0] Y25, + input [17:0] X26_in, + output [17:0] Y26, + input [17:0] X27_in, + output [17:0] Y27, + input [17:0] X28_in, + output [17:0] Y28, + input [17:0] X29_in, + output [17:0] Y29, + input [17:0] X30_in, + output [17:0] Y30, + input [17:0] X31_in, + output [17:0] Y31, + output next_out +); + +reg next; +reg [17:0] X0; +reg [17:0] X1; +reg [17:0] X2; +reg [17:0] X3; +reg [17:0] X4; +reg [17:0] X5; +reg [17:0] X6; +reg [17:0] X7; +reg [17:0] X8; +reg [17:0] X9; +reg [17:0] X10; +reg [17:0] X11; +reg [17:0] X12; +reg [17:0] X13; +reg [17:0] X14; +reg [17:0] X15; +reg [17:0] X16; +reg [17:0] X17; +reg [17:0] X18; +reg [17:0] X19; +reg [17:0] X20; +reg [17:0] X21; +reg [17:0] X22; +reg [17:0] X23; +reg [17:0] X24; +reg [17:0] X25; +reg [17:0] X26; +reg [17:0] X27; +reg [17:0] X28; +reg [17:0] X29; +reg [17:0] X30; +reg [17:0] X31; +shiftRegFIFO_2_1 shiftRegFIFO_2_1_inst_fglxnrtrar ( + .X(next), + .Y(next_out), + .reset(reset), + .clk(clk) +); +wire [17:0] a65; + wire [17:0] a66; + wire [17:0] a67; + wire [17:0] a68; + wire [17:0] a73; + wire [17:0] a74; + wire [17:0] a75; + wire [17:0] a76; + wire [17:0] a81; + wire [17:0] a82; + wire [17:0] a83; + wire [17:0] a84; + wire [17:0] a89; + wire [17:0] a90; + wire [17:0] a91; + wire [17:0] a92; + wire [17:0] a97; + wire [17:0] a98; + wire [17:0] a99; + wire [17:0] a100; + wire [17:0] a105; + wire [17:0] a106; + wire [17:0] a107; + wire [17:0] a108; + wire [17:0] a113; + wire [17:0] a114; + wire [17:0] a115; + wire [17:0] a116; + wire [17:0] a121; + wire [17:0] a122; + wire [17:0] a123; + wire [17:0] a124; + wire [17:0] t402; + wire [17:0] t403; + wire [17:0] t404; + wire [17:0] t405; + wire [17:0] t406; + wire [17:0] t407; + wire [17:0] t408; + wire [17:0] t409; + wire [17:0] t418; + wire [17:0] t419; + wire [17:0] t420; + wire [17:0] t421; + wire [17:0] t422; + wire [17:0] t423; + wire [17:0] t424; + wire [17:0] t425; + wire [17:0] t434; + wire [17:0] t435; + wire [17:0] t436; + wire [17:0] t437; + wire [17:0] t438; + wire [17:0] t439; + wire [17:0] t440; + wire [17:0] t441; + wire [17:0] t450; + wire [17:0] t451; + wire [17:0] t452; + wire [17:0] t453; + wire [17:0] t454; + wire [17:0] t455; + wire [17:0] t456; + wire [17:0] t457; + wire [17:0] t410; + wire [17:0] t411; + wire [17:0] t412; + wire [17:0] t413; + wire [17:0] t414; + wire [17:0] t415; + wire [17:0] t416; + wire [17:0] t417; + wire [17:0] t426; + wire [17:0] t427; + wire [17:0] t428; + wire [17:0] t429; + wire [17:0] t430; + wire [17:0] t431; + wire [17:0] t432; + wire [17:0] t433; + wire [17:0] t442; + wire [17:0] t443; + wire [17:0] t444; + wire [17:0] t445; + wire [17:0] t446; + wire [17:0] t447; + wire [17:0] t448; + wire [17:0] t449; + wire [17:0] t458; + wire [17:0] t459; + wire [17:0] t460; + wire [17:0] t461; + wire [17:0] t462; + wire [17:0] t463; + wire [17:0] t464; + wire [17:0] t465; + +assign a65 = X0; + assign a66 = X16; + assign a67 = X1; + assign a68 = X17; + assign a73 = X8; + assign a74 = X24; + assign a75 = X9; + assign a76 = X25; + assign a81 = X2; + assign a82 = X18; + assign a83 = X3; + assign a84 = X19; + assign a89 = X10; + assign a90 = X26; + assign a91 = X11; + assign a92 = X27; + assign a97 = X4; + assign a98 = X20; + assign a99 = X5; + assign a100 = X21; + assign a105 = X12; + assign a106 = X28; + assign a107 = X13; + assign a108 = X29; + assign a113 = X6; + assign a114 = X22; + assign a115 = X7; + assign a116 = X23; + assign a121 = X14; + assign a122 = X30; + assign a123 = X15; + assign a124 = X31; + assign Y0 = t410; + assign Y1 = t411; + assign Y16 = t412; + assign Y17 = t413; + assign Y8 = t414; + assign Y9 = t415; + assign Y24 = t416; + assign Y25 = t417; + assign Y2 = t426; + assign Y3 = t427; + assign Y18 = t428; + assign Y19 = t429; + assign Y10 = t430; + assign Y11 = t431; + assign Y26 = t432; + assign Y27 = t433; + assign Y4 = t442; + assign Y5 = t443; + assign Y20 = t444; + assign Y21 = t445; + assign Y12 = t446; + assign Y13 = t447; + assign Y28 = t448; + assign Y29 = t449; + assign Y6 = t458; + assign Y7 = t459; + assign Y22 = t460; + assign Y23 = t461; + assign Y14 = t462; + assign Y15 = t463; + assign Y30 = t464; + assign Y31 = t465; + +addfxp_18_1 add99180(.a(a65), .b(a66), .clk(clk), .q(t402)); + addfxp_18_1 add99195(.a(a67), .b(a68), .clk(clk), .q(t403)); + subfxp_18_1 sub99210(.a(a65), .b(a66), .clk(clk), .q(t404)); + subfxp_18_1 sub99225(.a(a67), .b(a68), .clk(clk), .q(t405)); + addfxp_18_1 add99240(.a(a73), .b(a74), .clk(clk), .q(t406)); + addfxp_18_1 add99255(.a(a75), .b(a76), .clk(clk), .q(t407)); + subfxp_18_1 sub99270(.a(a73), .b(a74), .clk(clk), .q(t408)); + subfxp_18_1 sub99285(.a(a75), .b(a76), .clk(clk), .q(t409)); + addfxp_18_1 add99388(.a(a81), .b(a82), .clk(clk), .q(t418)); + addfxp_18_1 add99403(.a(a83), .b(a84), .clk(clk), .q(t419)); + subfxp_18_1 sub99418(.a(a81), .b(a82), .clk(clk), .q(t420)); + subfxp_18_1 sub99433(.a(a83), .b(a84), .clk(clk), .q(t421)); + addfxp_18_1 add99448(.a(a89), .b(a90), .clk(clk), .q(t422)); + addfxp_18_1 add99463(.a(a91), .b(a92), .clk(clk), .q(t423)); + subfxp_18_1 sub99478(.a(a89), .b(a90), .clk(clk), .q(t424)); + subfxp_18_1 sub99493(.a(a91), .b(a92), .clk(clk), .q(t425)); + addfxp_18_1 add99596(.a(a97), .b(a98), .clk(clk), .q(t434)); + addfxp_18_1 add99611(.a(a99), .b(a100), .clk(clk), .q(t435)); + subfxp_18_1 sub99626(.a(a97), .b(a98), .clk(clk), .q(t436)); + subfxp_18_1 sub99641(.a(a99), .b(a100), .clk(clk), .q(t437)); + addfxp_18_1 add99656(.a(a105), .b(a106), .clk(clk), .q(t438)); + addfxp_18_1 add99671(.a(a107), .b(a108), .clk(clk), .q(t439)); + subfxp_18_1 sub99686(.a(a105), .b(a106), .clk(clk), .q(t440)); + subfxp_18_1 sub99701(.a(a107), .b(a108), .clk(clk), .q(t441)); + addfxp_18_1 add99804(.a(a113), .b(a114), .clk(clk), .q(t450)); + addfxp_18_1 add99819(.a(a115), .b(a116), .clk(clk), .q(t451)); + subfxp_18_1 sub99834(.a(a113), .b(a114), .clk(clk), .q(t452)); + subfxp_18_1 sub99849(.a(a115), .b(a116), .clk(clk), .q(t453)); + addfxp_18_1 add99864(.a(a121), .b(a122), .clk(clk), .q(t454)); + addfxp_18_1 add99879(.a(a123), .b(a124), .clk(clk), .q(t455)); + subfxp_18_1 sub99894(.a(a121), .b(a122), .clk(clk), .q(t456)); + subfxp_18_1 sub99909(.a(a123), .b(a124), .clk(clk), .q(t457)); + addfxp_18_1 add99292(.a(t402), .b(t406), .clk(clk), .q(t410)); + addfxp_18_1 add99299(.a(t403), .b(t407), .clk(clk), .q(t411)); + subfxp_18_1 sub99306(.a(t402), .b(t406), .clk(clk), .q(t412)); + subfxp_18_1 sub99313(.a(t403), .b(t407), .clk(clk), .q(t413)); + subfxp_18_1 sub99336(.a(t404), .b(t409), .clk(clk), .q(t414)); + addfxp_18_1 add99343(.a(t405), .b(t408), .clk(clk), .q(t415)); + addfxp_18_1 add99350(.a(t404), .b(t409), .clk(clk), .q(t416)); + subfxp_18_1 sub99357(.a(t405), .b(t408), .clk(clk), .q(t417)); + addfxp_18_1 add99500(.a(t418), .b(t422), .clk(clk), .q(t426)); + addfxp_18_1 add99507(.a(t419), .b(t423), .clk(clk), .q(t427)); + subfxp_18_1 sub99514(.a(t418), .b(t422), .clk(clk), .q(t428)); + subfxp_18_1 sub99521(.a(t419), .b(t423), .clk(clk), .q(t429)); + subfxp_18_1 sub99544(.a(t420), .b(t425), .clk(clk), .q(t430)); + addfxp_18_1 add99551(.a(t421), .b(t424), .clk(clk), .q(t431)); + addfxp_18_1 add99558(.a(t420), .b(t425), .clk(clk), .q(t432)); + subfxp_18_1 sub99565(.a(t421), .b(t424), .clk(clk), .q(t433)); + addfxp_18_1 add99708(.a(t434), .b(t438), .clk(clk), .q(t442)); + addfxp_18_1 add99715(.a(t435), .b(t439), .clk(clk), .q(t443)); + subfxp_18_1 sub99722(.a(t434), .b(t438), .clk(clk), .q(t444)); + subfxp_18_1 sub99729(.a(t435), .b(t439), .clk(clk), .q(t445)); + subfxp_18_1 sub99752(.a(t436), .b(t441), .clk(clk), .q(t446)); + addfxp_18_1 add99759(.a(t437), .b(t440), .clk(clk), .q(t447)); + addfxp_18_1 add99766(.a(t436), .b(t441), .clk(clk), .q(t448)); + subfxp_18_1 sub99773(.a(t437), .b(t440), .clk(clk), .q(t449)); + addfxp_18_1 add99916(.a(t450), .b(t454), .clk(clk), .q(t458)); + addfxp_18_1 add99923(.a(t451), .b(t455), .clk(clk), .q(t459)); + subfxp_18_1 sub99930(.a(t450), .b(t454), .clk(clk), .q(t460)); + subfxp_18_1 sub99937(.a(t451), .b(t455), .clk(clk), .q(t461)); + subfxp_18_1 sub99960(.a(t452), .b(t457), .clk(clk), .q(t462)); + addfxp_18_1 add99967(.a(t453), .b(t456), .clk(clk), .q(t463)); + addfxp_18_1 add99974(.a(t452), .b(t457), .clk(clk), .q(t464)); + subfxp_18_1 sub99981(.a(t453), .b(t456), .clk(clk), .q(t465)); + +always @(posedge clk) begin + if (reset == 1) begin + next <= 1'b0; + end else begin + X0 <= X0_in; + X1 <= X1_in; + X2 <= X2_in; + X3 <= X3_in; + X4 <= X4_in; + X5 <= X5_in; + X6 <= X6_in; + X7 <= X7_in; + X8 <= X8_in; + X9 <= X9_in; + X10 <= X10_in; + X11 <= X11_in; + X12 <= X12_in; + X13 <= X13_in; + X14 <= X14_in; + X15 <= X15_in; + X16 <= X16_in; + X17 <= X17_in; + X18 <= X18_in; + X19 <= X19_in; + X20 <= X20_in; + X21 <= X21_in; + X22 <= X22_in; + X23 <= X23_in; + X24 <= X24_in; + X25 <= X25_in; + X26 <= X26_in; + X27 <= X27_in; + X28 <= X28_in; + X29 <= X29_in; + X30 <= X30_in; + X31 <= X31_in; + next <= next_in; + end +end + +endmodule + +module stage2_parameter_buffer_18_3_16_64 ( + input clk, + input reset, + input [287:0] wdata +, input [6:0] wen, + output [17:0] o_Wic_0, + output [17:0] o_bi_0, + output [17:0] o_Wfc_0, + output [17:0] o_bf_0, + output [17:0] o_Woc_0, + output [17:0] o_bo_0, + output [17:0] o_bc_0, + output [17:0] o_Wic_1, + output [17:0] o_bi_1, + output [17:0] o_Wfc_1, + output [17:0] o_bf_1, + output [17:0] o_Woc_1, + output [17:0] o_bo_1, + output [17:0] o_bc_1, + output [17:0] o_Wic_2, + output [17:0] o_bi_2, + output [17:0] o_Wfc_2, + output [17:0] o_bf_2, + output [17:0] o_Woc_2, + output [17:0] o_bo_2, + output [17:0] o_bc_2, + output [17:0] o_Wic_3, + output [17:0] o_bi_3, + output [17:0] o_Wfc_3, + output [17:0] o_bf_3, + output [17:0] o_Woc_3, + output [17:0] o_bo_3, + output [17:0] o_bc_3, + output [17:0] o_Wic_4, + output [17:0] o_bi_4, + output [17:0] o_Wfc_4, + output [17:0] o_bf_4, + output [17:0] o_Woc_4, + output [17:0] o_bo_4, + output [17:0] o_bc_4, + output [17:0] o_Wic_5, + output [17:0] o_bi_5, + output [17:0] o_Wfc_5, + output [17:0] o_bf_5, + output [17:0] o_Woc_5, + output [17:0] o_bo_5, + output [17:0] o_bc_5, + output [17:0] o_Wic_6, + output [17:0] o_bi_6, + output [17:0] o_Wfc_6, + output [17:0] o_bf_6, + output [17:0] o_Woc_6, + output [17:0] o_bo_6, + output [17:0] o_bc_6, + output [17:0] o_Wic_7, + output [17:0] o_bi_7, + output [17:0] o_Wfc_7, + output [17:0] o_bf_7, + output [17:0] o_Woc_7, + output [17:0] o_bo_7, + output [17:0] o_bc_7, + output [17:0] o_Wic_8, + output [17:0] o_bi_8, + output [17:0] o_Wfc_8, + output [17:0] o_bf_8, + output [17:0] o_Woc_8, + output [17:0] o_bo_8, + output [17:0] o_bc_8, + output [17:0] o_Wic_9, + output [17:0] o_bi_9, + output [17:0] o_Wfc_9, + output [17:0] o_bf_9, + output [17:0] o_Woc_9, + output [17:0] o_bo_9, + output [17:0] o_bc_9, + output [17:0] o_Wic_10, + output [17:0] o_bi_10, + output [17:0] o_Wfc_10, + output [17:0] o_bf_10, + output [17:0] o_Woc_10, + output [17:0] o_bo_10, + output [17:0] o_bc_10, + output [17:0] o_Wic_11, + output [17:0] o_bi_11, + output [17:0] o_Wfc_11, + output [17:0] o_bf_11, + output [17:0] o_Woc_11, + output [17:0] o_bo_11, + output [17:0] o_bc_11, + output [17:0] o_Wic_12, + output [17:0] o_bi_12, + output [17:0] o_Wfc_12, + output [17:0] o_bf_12, + output [17:0] o_Woc_12, + output [17:0] o_bo_12, + output [17:0] o_bc_12, + output [17:0] o_Wic_13, + output [17:0] o_bi_13, + output [17:0] o_Wfc_13, + output [17:0] o_bf_13, + output [17:0] o_Woc_13, + output [17:0] o_bo_13, + output [17:0] o_bc_13, + output [17:0] o_Wic_14, + output [17:0] o_bi_14, + output [17:0] o_Wfc_14, + output [17:0] o_bf_14, + output [17:0] o_Woc_14, + output [17:0] o_bo_14, + output [17:0] o_bc_14, + output [17:0] o_Wic_15, + output [17:0] o_bi_15, + output [17:0] o_Wfc_15, + output [17:0] o_bf_15, + output [17:0] o_Woc_15, + output [17:0] o_bo_15, + output [17:0] o_bc_15, + output [17:0] o_Wic_16, + output [17:0] o_bi_16, + output [17:0] o_Wfc_16, + output [17:0] o_bf_16, + output [17:0] o_Woc_16, + output [17:0] o_bo_16, + output [17:0] o_bc_16, + output [17:0] o_Wic_17, + output [17:0] o_bi_17, + output [17:0] o_Wfc_17, + output [17:0] o_bf_17, + output [17:0] o_Woc_17, + output [17:0] o_bo_17, + output [17:0] o_bc_17, + output [17:0] o_Wic_18, + output [17:0] o_bi_18, + output [17:0] o_Wfc_18, + output [17:0] o_bf_18, + output [17:0] o_Woc_18, + output [17:0] o_bo_18, + output [17:0] o_bc_18, + output [17:0] o_Wic_19, + output [17:0] o_bi_19, + output [17:0] o_Wfc_19, + output [17:0] o_bf_19, + output [17:0] o_Woc_19, + output [17:0] o_bo_19, + output [17:0] o_bc_19, + output [17:0] o_Wic_20, + output [17:0] o_bi_20, + output [17:0] o_Wfc_20, + output [17:0] o_bf_20, + output [17:0] o_Woc_20, + output [17:0] o_bo_20, + output [17:0] o_bc_20, + output [17:0] o_Wic_21, + output [17:0] o_bi_21, + output [17:0] o_Wfc_21, + output [17:0] o_bf_21, + output [17:0] o_Woc_21, + output [17:0] o_bo_21, + output [17:0] o_bc_21, + output [17:0] o_Wic_22, + output [17:0] o_bi_22, + output [17:0] o_Wfc_22, + output [17:0] o_bf_22, + output [17:0] o_Woc_22, + output [17:0] o_bo_22, + output [17:0] o_bc_22, + output [17:0] o_Wic_23, + output [17:0] o_bi_23, + output [17:0] o_Wfc_23, + output [17:0] o_bf_23, + output [17:0] o_Woc_23, + output [17:0] o_bo_23, + output [17:0] o_bc_23, + output [17:0] o_Wic_24, + output [17:0] o_bi_24, + output [17:0] o_Wfc_24, + output [17:0] o_bf_24, + output [17:0] o_Woc_24, + output [17:0] o_bo_24, + output [17:0] o_bc_24, + output [17:0] o_Wic_25, + output [17:0] o_bi_25, + output [17:0] o_Wfc_25, + output [17:0] o_bf_25, + output [17:0] o_Woc_25, + output [17:0] o_bo_25, + output [17:0] o_bc_25, + output [17:0] o_Wic_26, + output [17:0] o_bi_26, + output [17:0] o_Wfc_26, + output [17:0] o_bf_26, + output [17:0] o_Woc_26, + output [17:0] o_bo_26, + output [17:0] o_bc_26, + output [17:0] o_Wic_27, + output [17:0] o_bi_27, + output [17:0] o_Wfc_27, + output [17:0] o_bf_27, + output [17:0] o_Woc_27, + output [17:0] o_bo_27, + output [17:0] o_bc_27, + output [17:0] o_Wic_28, + output [17:0] o_bi_28, + output [17:0] o_Wfc_28, + output [17:0] o_bf_28, + output [17:0] o_Woc_28, + output [17:0] o_bo_28, + output [17:0] o_bc_28, + output [17:0] o_Wic_29, + output [17:0] o_bi_29, + output [17:0] o_Wfc_29, + output [17:0] o_bf_29, + output [17:0] o_Woc_29, + output [17:0] o_bo_29, + output [17:0] o_bc_29, + output [17:0] o_Wic_30, + output [17:0] o_bi_30, + output [17:0] o_Wfc_30, + output [17:0] o_bf_30, + output [17:0] o_Woc_30, + output [17:0] o_bo_30, + output [17:0] o_bc_30, + output [17:0] o_Wic_31, + output [17:0] o_bi_31, + output [17:0] o_Wfc_31, + output [17:0] o_bf_31, + output [17:0] o_Woc_31, + output [17:0] o_bo_31, + output [17:0] o_bc_31, + output [17:0] o_Wic_32, + output [17:0] o_bi_32, + output [17:0] o_Wfc_32, + output [17:0] o_bf_32, + output [17:0] o_Woc_32, + output [17:0] o_bo_32, + output [17:0] o_bc_32, + output [17:0] o_Wic_33, + output [17:0] o_bi_33, + output [17:0] o_Wfc_33, + output [17:0] o_bf_33, + output [17:0] o_Woc_33, + output [17:0] o_bo_33, + output [17:0] o_bc_33, + output [17:0] o_Wic_34, + output [17:0] o_bi_34, + output [17:0] o_Wfc_34, + output [17:0] o_bf_34, + output [17:0] o_Woc_34, + output [17:0] o_bo_34, + output [17:0] o_bc_34, + output [17:0] o_Wic_35, + output [17:0] o_bi_35, + output [17:0] o_Wfc_35, + output [17:0] o_bf_35, + output [17:0] o_Woc_35, + output [17:0] o_bo_35, + output [17:0] o_bc_35, + output [17:0] o_Wic_36, + output [17:0] o_bi_36, + output [17:0] o_Wfc_36, + output [17:0] o_bf_36, + output [17:0] o_Woc_36, + output [17:0] o_bo_36, + output [17:0] o_bc_36, + output [17:0] o_Wic_37, + output [17:0] o_bi_37, + output [17:0] o_Wfc_37, + output [17:0] o_bf_37, + output [17:0] o_Woc_37, + output [17:0] o_bo_37, + output [17:0] o_bc_37, + output [17:0] o_Wic_38, + output [17:0] o_bi_38, + output [17:0] o_Wfc_38, + output [17:0] o_bf_38, + output [17:0] o_Woc_38, + output [17:0] o_bo_38, + output [17:0] o_bc_38, + output [17:0] o_Wic_39, + output [17:0] o_bi_39, + output [17:0] o_Wfc_39, + output [17:0] o_bf_39, + output [17:0] o_Woc_39, + output [17:0] o_bo_39, + output [17:0] o_bc_39, + output [17:0] o_Wic_40, + output [17:0] o_bi_40, + output [17:0] o_Wfc_40, + output [17:0] o_bf_40, + output [17:0] o_Woc_40, + output [17:0] o_bo_40, + output [17:0] o_bc_40, + output [17:0] o_Wic_41, + output [17:0] o_bi_41, + output [17:0] o_Wfc_41, + output [17:0] o_bf_41, + output [17:0] o_Woc_41, + output [17:0] o_bo_41, + output [17:0] o_bc_41, + output [17:0] o_Wic_42, + output [17:0] o_bi_42, + output [17:0] o_Wfc_42, + output [17:0] o_bf_42, + output [17:0] o_Woc_42, + output [17:0] o_bo_42, + output [17:0] o_bc_42, + output [17:0] o_Wic_43, + output [17:0] o_bi_43, + output [17:0] o_Wfc_43, + output [17:0] o_bf_43, + output [17:0] o_Woc_43, + output [17:0] o_bo_43, + output [17:0] o_bc_43, + output [17:0] o_Wic_44, + output [17:0] o_bi_44, + output [17:0] o_Wfc_44, + output [17:0] o_bf_44, + output [17:0] o_Woc_44, + output [17:0] o_bo_44, + output [17:0] o_bc_44, + output [17:0] o_Wic_45, + output [17:0] o_bi_45, + output [17:0] o_Wfc_45, + output [17:0] o_bf_45, + output [17:0] o_Woc_45, + output [17:0] o_bo_45, + output [17:0] o_bc_45, + output [17:0] o_Wic_46, + output [17:0] o_bi_46, + output [17:0] o_Wfc_46, + output [17:0] o_bf_46, + output [17:0] o_Woc_46, + output [17:0] o_bo_46, + output [17:0] o_bc_46, + output [17:0] o_Wic_47, + output [17:0] o_bi_47, + output [17:0] o_Wfc_47, + output [17:0] o_bf_47, + output [17:0] o_Woc_47, + output [17:0] o_bo_47, + output [17:0] o_bc_47, + input incr_index +); + +wire [17:0] Wic_0_0; +wire [17:0] bi_0_0; +wire [17:0] Wfc_0_0; +wire [17:0] bf_0_0; +wire [17:0] Woc_0_0; +wire [17:0] bo_0_0; +wire [17:0] bc_0_0; +wire [17:0] Wic_0_1; +wire [17:0] bi_0_1; +wire [17:0] Wfc_0_1; +wire [17:0] bf_0_1; +wire [17:0] Woc_0_1; +wire [17:0] bo_0_1; +wire [17:0] bc_0_1; +wire [17:0] Wic_0_2; +wire [17:0] bi_0_2; +wire [17:0] Wfc_0_2; +wire [17:0] bf_0_2; +wire [17:0] Woc_0_2; +wire [17:0] bo_0_2; +wire [17:0] bc_0_2; +wire [17:0] Wic_0_3; +wire [17:0] bi_0_3; +wire [17:0] Wfc_0_3; +wire [17:0] bf_0_3; +wire [17:0] Woc_0_3; +wire [17:0] bo_0_3; +wire [17:0] bc_0_3; +wire [17:0] Wic_0_4; +wire [17:0] bi_0_4; +wire [17:0] Wfc_0_4; +wire [17:0] bf_0_4; +wire [17:0] Woc_0_4; +wire [17:0] bo_0_4; +wire [17:0] bc_0_4; +wire [17:0] Wic_0_5; +wire [17:0] bi_0_5; +wire [17:0] Wfc_0_5; +wire [17:0] bf_0_5; +wire [17:0] Woc_0_5; +wire [17:0] bo_0_5; +wire [17:0] bc_0_5; +wire [17:0] Wic_0_6; +wire [17:0] bi_0_6; +wire [17:0] Wfc_0_6; +wire [17:0] bf_0_6; +wire [17:0] Woc_0_6; +wire [17:0] bo_0_6; +wire [17:0] bc_0_6; +wire [17:0] Wic_0_7; +wire [17:0] bi_0_7; +wire [17:0] Wfc_0_7; +wire [17:0] bf_0_7; +wire [17:0] Woc_0_7; +wire [17:0] bo_0_7; +wire [17:0] bc_0_7; +wire [17:0] Wic_0_8; +wire [17:0] bi_0_8; +wire [17:0] Wfc_0_8; +wire [17:0] bf_0_8; +wire [17:0] Woc_0_8; +wire [17:0] bo_0_8; +wire [17:0] bc_0_8; +wire [17:0] Wic_0_9; +wire [17:0] bi_0_9; +wire [17:0] Wfc_0_9; +wire [17:0] bf_0_9; +wire [17:0] Woc_0_9; +wire [17:0] bo_0_9; +wire [17:0] bc_0_9; +wire [17:0] Wic_0_10; +wire [17:0] bi_0_10; +wire [17:0] Wfc_0_10; +wire [17:0] bf_0_10; +wire [17:0] Woc_0_10; +wire [17:0] bo_0_10; +wire [17:0] bc_0_10; +wire [17:0] Wic_0_11; +wire [17:0] bi_0_11; +wire [17:0] Wfc_0_11; +wire [17:0] bf_0_11; +wire [17:0] Woc_0_11; +wire [17:0] bo_0_11; +wire [17:0] bc_0_11; +wire [17:0] Wic_0_12; +wire [17:0] bi_0_12; +wire [17:0] Wfc_0_12; +wire [17:0] bf_0_12; +wire [17:0] Woc_0_12; +wire [17:0] bo_0_12; +wire [17:0] bc_0_12; +wire [17:0] Wic_0_13; +wire [17:0] bi_0_13; +wire [17:0] Wfc_0_13; +wire [17:0] bf_0_13; +wire [17:0] Woc_0_13; +wire [17:0] bo_0_13; +wire [17:0] bc_0_13; +wire [17:0] Wic_0_14; +wire [17:0] bi_0_14; +wire [17:0] Wfc_0_14; +wire [17:0] bf_0_14; +wire [17:0] Woc_0_14; +wire [17:0] bo_0_14; +wire [17:0] bc_0_14; +wire [17:0] Wic_0_15; +wire [17:0] bi_0_15; +wire [17:0] Wfc_0_15; +wire [17:0] bf_0_15; +wire [17:0] Woc_0_15; +wire [17:0] bo_0_15; +wire [17:0] bc_0_15; +wire [17:0] Wic_1_0; +wire [17:0] bi_1_0; +wire [17:0] Wfc_1_0; +wire [17:0] bf_1_0; +wire [17:0] Woc_1_0; +wire [17:0] bo_1_0; +wire [17:0] bc_1_0; +wire [17:0] Wic_1_1; +wire [17:0] bi_1_1; +wire [17:0] Wfc_1_1; +wire [17:0] bf_1_1; +wire [17:0] Woc_1_1; +wire [17:0] bo_1_1; +wire [17:0] bc_1_1; +wire [17:0] Wic_1_2; +wire [17:0] bi_1_2; +wire [17:0] Wfc_1_2; +wire [17:0] bf_1_2; +wire [17:0] Woc_1_2; +wire [17:0] bo_1_2; +wire [17:0] bc_1_2; +wire [17:0] Wic_1_3; +wire [17:0] bi_1_3; +wire [17:0] Wfc_1_3; +wire [17:0] bf_1_3; +wire [17:0] Woc_1_3; +wire [17:0] bo_1_3; +wire [17:0] bc_1_3; +wire [17:0] Wic_1_4; +wire [17:0] bi_1_4; +wire [17:0] Wfc_1_4; +wire [17:0] bf_1_4; +wire [17:0] Woc_1_4; +wire [17:0] bo_1_4; +wire [17:0] bc_1_4; +wire [17:0] Wic_1_5; +wire [17:0] bi_1_5; +wire [17:0] Wfc_1_5; +wire [17:0] bf_1_5; +wire [17:0] Woc_1_5; +wire [17:0] bo_1_5; +wire [17:0] bc_1_5; +wire [17:0] Wic_1_6; +wire [17:0] bi_1_6; +wire [17:0] Wfc_1_6; +wire [17:0] bf_1_6; +wire [17:0] Woc_1_6; +wire [17:0] bo_1_6; +wire [17:0] bc_1_6; +wire [17:0] Wic_1_7; +wire [17:0] bi_1_7; +wire [17:0] Wfc_1_7; +wire [17:0] bf_1_7; +wire [17:0] Woc_1_7; +wire [17:0] bo_1_7; +wire [17:0] bc_1_7; +wire [17:0] Wic_1_8; +wire [17:0] bi_1_8; +wire [17:0] Wfc_1_8; +wire [17:0] bf_1_8; +wire [17:0] Woc_1_8; +wire [17:0] bo_1_8; +wire [17:0] bc_1_8; +wire [17:0] Wic_1_9; +wire [17:0] bi_1_9; +wire [17:0] Wfc_1_9; +wire [17:0] bf_1_9; +wire [17:0] Woc_1_9; +wire [17:0] bo_1_9; +wire [17:0] bc_1_9; +wire [17:0] Wic_1_10; +wire [17:0] bi_1_10; +wire [17:0] Wfc_1_10; +wire [17:0] bf_1_10; +wire [17:0] Woc_1_10; +wire [17:0] bo_1_10; +wire [17:0] bc_1_10; +wire [17:0] Wic_1_11; +wire [17:0] bi_1_11; +wire [17:0] Wfc_1_11; +wire [17:0] bf_1_11; +wire [17:0] Woc_1_11; +wire [17:0] bo_1_11; +wire [17:0] bc_1_11; +wire [17:0] Wic_1_12; +wire [17:0] bi_1_12; +wire [17:0] Wfc_1_12; +wire [17:0] bf_1_12; +wire [17:0] Woc_1_12; +wire [17:0] bo_1_12; +wire [17:0] bc_1_12; +wire [17:0] Wic_1_13; +wire [17:0] bi_1_13; +wire [17:0] Wfc_1_13; +wire [17:0] bf_1_13; +wire [17:0] Woc_1_13; +wire [17:0] bo_1_13; +wire [17:0] bc_1_13; +wire [17:0] Wic_1_14; +wire [17:0] bi_1_14; +wire [17:0] Wfc_1_14; +wire [17:0] bf_1_14; +wire [17:0] Woc_1_14; +wire [17:0] bo_1_14; +wire [17:0] bc_1_14; +wire [17:0] Wic_1_15; +wire [17:0] bi_1_15; +wire [17:0] Wfc_1_15; +wire [17:0] bf_1_15; +wire [17:0] Woc_1_15; +wire [17:0] bo_1_15; +wire [17:0] bc_1_15; +wire [17:0] Wic_2_0; +wire [17:0] bi_2_0; +wire [17:0] Wfc_2_0; +wire [17:0] bf_2_0; +wire [17:0] Woc_2_0; +wire [17:0] bo_2_0; +wire [17:0] bc_2_0; +wire [17:0] Wic_2_1; +wire [17:0] bi_2_1; +wire [17:0] Wfc_2_1; +wire [17:0] bf_2_1; +wire [17:0] Woc_2_1; +wire [17:0] bo_2_1; +wire [17:0] bc_2_1; +wire [17:0] Wic_2_2; +wire [17:0] bi_2_2; +wire [17:0] Wfc_2_2; +wire [17:0] bf_2_2; +wire [17:0] Woc_2_2; +wire [17:0] bo_2_2; +wire [17:0] bc_2_2; +wire [17:0] Wic_2_3; +wire [17:0] bi_2_3; +wire [17:0] Wfc_2_3; +wire [17:0] bf_2_3; +wire [17:0] Woc_2_3; +wire [17:0] bo_2_3; +wire [17:0] bc_2_3; +wire [17:0] Wic_2_4; +wire [17:0] bi_2_4; +wire [17:0] Wfc_2_4; +wire [17:0] bf_2_4; +wire [17:0] Woc_2_4; +wire [17:0] bo_2_4; +wire [17:0] bc_2_4; +wire [17:0] Wic_2_5; +wire [17:0] bi_2_5; +wire [17:0] Wfc_2_5; +wire [17:0] bf_2_5; +wire [17:0] Woc_2_5; +wire [17:0] bo_2_5; +wire [17:0] bc_2_5; +wire [17:0] Wic_2_6; +wire [17:0] bi_2_6; +wire [17:0] Wfc_2_6; +wire [17:0] bf_2_6; +wire [17:0] Woc_2_6; +wire [17:0] bo_2_6; +wire [17:0] bc_2_6; +wire [17:0] Wic_2_7; +wire [17:0] bi_2_7; +wire [17:0] Wfc_2_7; +wire [17:0] bf_2_7; +wire [17:0] Woc_2_7; +wire [17:0] bo_2_7; +wire [17:0] bc_2_7; +wire [17:0] Wic_2_8; +wire [17:0] bi_2_8; +wire [17:0] Wfc_2_8; +wire [17:0] bf_2_8; +wire [17:0] Woc_2_8; +wire [17:0] bo_2_8; +wire [17:0] bc_2_8; +wire [17:0] Wic_2_9; +wire [17:0] bi_2_9; +wire [17:0] Wfc_2_9; +wire [17:0] bf_2_9; +wire [17:0] Woc_2_9; +wire [17:0] bo_2_9; +wire [17:0] bc_2_9; +wire [17:0] Wic_2_10; +wire [17:0] bi_2_10; +wire [17:0] Wfc_2_10; +wire [17:0] bf_2_10; +wire [17:0] Woc_2_10; +wire [17:0] bo_2_10; +wire [17:0] bc_2_10; +wire [17:0] Wic_2_11; +wire [17:0] bi_2_11; +wire [17:0] Wfc_2_11; +wire [17:0] bf_2_11; +wire [17:0] Woc_2_11; +wire [17:0] bo_2_11; +wire [17:0] bc_2_11; +wire [17:0] Wic_2_12; +wire [17:0] bi_2_12; +wire [17:0] Wfc_2_12; +wire [17:0] bf_2_12; +wire [17:0] Woc_2_12; +wire [17:0] bo_2_12; +wire [17:0] bc_2_12; +wire [17:0] Wic_2_13; +wire [17:0] bi_2_13; +wire [17:0] Wfc_2_13; +wire [17:0] bf_2_13; +wire [17:0] Woc_2_13; +wire [17:0] bo_2_13; +wire [17:0] bc_2_13; +wire [17:0] Wic_2_14; +wire [17:0] bi_2_14; +wire [17:0] Wfc_2_14; +wire [17:0] bf_2_14; +wire [17:0] Woc_2_14; +wire [17:0] bo_2_14; +wire [17:0] bc_2_14; +wire [17:0] Wic_2_15; +wire [17:0] bi_2_15; +wire [17:0] Wfc_2_15; +wire [17:0] bf_2_15; +wire [17:0] Woc_2_15; +wire [17:0] bo_2_15; +wire [17:0] bc_2_15; + +wire [13:0] input_index_counter; +counter_63_3 counter_63_3_inst_auxysufkcz ( + .clk(clk), + .reset(reset), + .ena(incr_index), + .count(input_index_counter) +); + +weight_buffer_18_16_3_64_Wic_0 weight_buffer_18_16_3_64_Wic_0_inst_pifptqydvx ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[6]), + .q_0_0(Wic_0_0), + .q_0_1(Wic_0_1), + .q_0_2(Wic_0_2), + .q_0_3(Wic_0_3), + .q_0_4(Wic_0_4), + .q_0_5(Wic_0_5), + .q_0_6(Wic_0_6), + .q_0_7(Wic_0_7), + .q_0_8(Wic_0_8), + .q_0_9(Wic_0_9), + .q_0_10(Wic_0_10), + .q_0_11(Wic_0_11), + .q_0_12(Wic_0_12), + .q_0_13(Wic_0_13), + .q_0_14(Wic_0_14), + .q_0_15(Wic_0_15), + .q_1_0(Wic_1_0), + .q_1_1(Wic_1_1), + .q_1_2(Wic_1_2), + .q_1_3(Wic_1_3), + .q_1_4(Wic_1_4), + .q_1_5(Wic_1_5), + .q_1_6(Wic_1_6), + .q_1_7(Wic_1_7), + .q_1_8(Wic_1_8), + .q_1_9(Wic_1_9), + .q_1_10(Wic_1_10), + .q_1_11(Wic_1_11), + .q_1_12(Wic_1_12), + .q_1_13(Wic_1_13), + .q_1_14(Wic_1_14), + .q_1_15(Wic_1_15), + .q_2_0(Wic_2_0), + .q_2_1(Wic_2_1), + .q_2_2(Wic_2_2), + .q_2_3(Wic_2_3), + .q_2_4(Wic_2_4), + .q_2_5(Wic_2_5), + .q_2_6(Wic_2_6), + .q_2_7(Wic_2_7), + .q_2_8(Wic_2_8), + .q_2_9(Wic_2_9), + .q_2_10(Wic_2_10), + .q_2_11(Wic_2_11), + .q_2_12(Wic_2_12), + .q_2_13(Wic_2_13), + .q_2_14(Wic_2_14), + .q_2_15(Wic_2_15), + .index(input_index_counter) +); + +weight_buffer_18_16_3_64_bi_0 weight_buffer_18_16_3_64_bi_0_inst_oiqdntqykl ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[0]), + .q_0_0(bi_0_0), + .q_0_1(bi_0_1), + .q_0_2(bi_0_2), + .q_0_3(bi_0_3), + .q_0_4(bi_0_4), + .q_0_5(bi_0_5), + .q_0_6(bi_0_6), + .q_0_7(bi_0_7), + .q_0_8(bi_0_8), + .q_0_9(bi_0_9), + .q_0_10(bi_0_10), + .q_0_11(bi_0_11), + .q_0_12(bi_0_12), + .q_0_13(bi_0_13), + .q_0_14(bi_0_14), + .q_0_15(bi_0_15), + .q_1_0(bi_1_0), + .q_1_1(bi_1_1), + .q_1_2(bi_1_2), + .q_1_3(bi_1_3), + .q_1_4(bi_1_4), + .q_1_5(bi_1_5), + .q_1_6(bi_1_6), + .q_1_7(bi_1_7), + .q_1_8(bi_1_8), + .q_1_9(bi_1_9), + .q_1_10(bi_1_10), + .q_1_11(bi_1_11), + .q_1_12(bi_1_12), + .q_1_13(bi_1_13), + .q_1_14(bi_1_14), + .q_1_15(bi_1_15), + .q_2_0(bi_2_0), + .q_2_1(bi_2_1), + .q_2_2(bi_2_2), + .q_2_3(bi_2_3), + .q_2_4(bi_2_4), + .q_2_5(bi_2_5), + .q_2_6(bi_2_6), + .q_2_7(bi_2_7), + .q_2_8(bi_2_8), + .q_2_9(bi_2_9), + .q_2_10(bi_2_10), + .q_2_11(bi_2_11), + .q_2_12(bi_2_12), + .q_2_13(bi_2_13), + .q_2_14(bi_2_14), + .q_2_15(bi_2_15), + .index(input_index_counter) +); + +weight_buffer_18_16_3_64_Wfc_0 weight_buffer_18_16_3_64_Wfc_0_inst_uuwxvrzcbu ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[1]), + .q_0_0(Wfc_0_0), + .q_0_1(Wfc_0_1), + .q_0_2(Wfc_0_2), + .q_0_3(Wfc_0_3), + .q_0_4(Wfc_0_4), + .q_0_5(Wfc_0_5), + .q_0_6(Wfc_0_6), + .q_0_7(Wfc_0_7), + .q_0_8(Wfc_0_8), + .q_0_9(Wfc_0_9), + .q_0_10(Wfc_0_10), + .q_0_11(Wfc_0_11), + .q_0_12(Wfc_0_12), + .q_0_13(Wfc_0_13), + .q_0_14(Wfc_0_14), + .q_0_15(Wfc_0_15), + .q_1_0(Wfc_1_0), + .q_1_1(Wfc_1_1), + .q_1_2(Wfc_1_2), + .q_1_3(Wfc_1_3), + .q_1_4(Wfc_1_4), + .q_1_5(Wfc_1_5), + .q_1_6(Wfc_1_6), + .q_1_7(Wfc_1_7), + .q_1_8(Wfc_1_8), + .q_1_9(Wfc_1_9), + .q_1_10(Wfc_1_10), + .q_1_11(Wfc_1_11), + .q_1_12(Wfc_1_12), + .q_1_13(Wfc_1_13), + .q_1_14(Wfc_1_14), + .q_1_15(Wfc_1_15), + .q_2_0(Wfc_2_0), + .q_2_1(Wfc_2_1), + .q_2_2(Wfc_2_2), + .q_2_3(Wfc_2_3), + .q_2_4(Wfc_2_4), + .q_2_5(Wfc_2_5), + .q_2_6(Wfc_2_6), + .q_2_7(Wfc_2_7), + .q_2_8(Wfc_2_8), + .q_2_9(Wfc_2_9), + .q_2_10(Wfc_2_10), + .q_2_11(Wfc_2_11), + .q_2_12(Wfc_2_12), + .q_2_13(Wfc_2_13), + .q_2_14(Wfc_2_14), + .q_2_15(Wfc_2_15), + .index(input_index_counter) +); + +weight_buffer_18_16_3_64_bf_0 weight_buffer_18_16_3_64_bf_0_inst_mykqvzfgdn ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[2]), + .q_0_0(bf_0_0), + .q_0_1(bf_0_1), + .q_0_2(bf_0_2), + .q_0_3(bf_0_3), + .q_0_4(bf_0_4), + .q_0_5(bf_0_5), + .q_0_6(bf_0_6), + .q_0_7(bf_0_7), + .q_0_8(bf_0_8), + .q_0_9(bf_0_9), + .q_0_10(bf_0_10), + .q_0_11(bf_0_11), + .q_0_12(bf_0_12), + .q_0_13(bf_0_13), + .q_0_14(bf_0_14), + .q_0_15(bf_0_15), + .q_1_0(bf_1_0), + .q_1_1(bf_1_1), + .q_1_2(bf_1_2), + .q_1_3(bf_1_3), + .q_1_4(bf_1_4), + .q_1_5(bf_1_5), + .q_1_6(bf_1_6), + .q_1_7(bf_1_7), + .q_1_8(bf_1_8), + .q_1_9(bf_1_9), + .q_1_10(bf_1_10), + .q_1_11(bf_1_11), + .q_1_12(bf_1_12), + .q_1_13(bf_1_13), + .q_1_14(bf_1_14), + .q_1_15(bf_1_15), + .q_2_0(bf_2_0), + .q_2_1(bf_2_1), + .q_2_2(bf_2_2), + .q_2_3(bf_2_3), + .q_2_4(bf_2_4), + .q_2_5(bf_2_5), + .q_2_6(bf_2_6), + .q_2_7(bf_2_7), + .q_2_8(bf_2_8), + .q_2_9(bf_2_9), + .q_2_10(bf_2_10), + .q_2_11(bf_2_11), + .q_2_12(bf_2_12), + .q_2_13(bf_2_13), + .q_2_14(bf_2_14), + .q_2_15(bf_2_15), + .index(input_index_counter) +); + +weight_buffer_18_16_3_64_Woc_0 weight_buffer_18_16_3_64_Woc_0_inst_yjpyusqeht ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[3]), + .q_0_0(Woc_0_0), + .q_0_1(Woc_0_1), + .q_0_2(Woc_0_2), + .q_0_3(Woc_0_3), + .q_0_4(Woc_0_4), + .q_0_5(Woc_0_5), + .q_0_6(Woc_0_6), + .q_0_7(Woc_0_7), + .q_0_8(Woc_0_8), + .q_0_9(Woc_0_9), + .q_0_10(Woc_0_10), + .q_0_11(Woc_0_11), + .q_0_12(Woc_0_12), + .q_0_13(Woc_0_13), + .q_0_14(Woc_0_14), + .q_0_15(Woc_0_15), + .q_1_0(Woc_1_0), + .q_1_1(Woc_1_1), + .q_1_2(Woc_1_2), + .q_1_3(Woc_1_3), + .q_1_4(Woc_1_4), + .q_1_5(Woc_1_5), + .q_1_6(Woc_1_6), + .q_1_7(Woc_1_7), + .q_1_8(Woc_1_8), + .q_1_9(Woc_1_9), + .q_1_10(Woc_1_10), + .q_1_11(Woc_1_11), + .q_1_12(Woc_1_12), + .q_1_13(Woc_1_13), + .q_1_14(Woc_1_14), + .q_1_15(Woc_1_15), + .q_2_0(Woc_2_0), + .q_2_1(Woc_2_1), + .q_2_2(Woc_2_2), + .q_2_3(Woc_2_3), + .q_2_4(Woc_2_4), + .q_2_5(Woc_2_5), + .q_2_6(Woc_2_6), + .q_2_7(Woc_2_7), + .q_2_8(Woc_2_8), + .q_2_9(Woc_2_9), + .q_2_10(Woc_2_10), + .q_2_11(Woc_2_11), + .q_2_12(Woc_2_12), + .q_2_13(Woc_2_13), + .q_2_14(Woc_2_14), + .q_2_15(Woc_2_15), + .index(input_index_counter) +); + +weight_buffer_18_16_3_64_bo_0 weight_buffer_18_16_3_64_bo_0_inst_bcwioexbnr ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[4]), + .q_0_0(bo_0_0), + .q_0_1(bo_0_1), + .q_0_2(bo_0_2), + .q_0_3(bo_0_3), + .q_0_4(bo_0_4), + .q_0_5(bo_0_5), + .q_0_6(bo_0_6), + .q_0_7(bo_0_7), + .q_0_8(bo_0_8), + .q_0_9(bo_0_9), + .q_0_10(bo_0_10), + .q_0_11(bo_0_11), + .q_0_12(bo_0_12), + .q_0_13(bo_0_13), + .q_0_14(bo_0_14), + .q_0_15(bo_0_15), + .q_1_0(bo_1_0), + .q_1_1(bo_1_1), + .q_1_2(bo_1_2), + .q_1_3(bo_1_3), + .q_1_4(bo_1_4), + .q_1_5(bo_1_5), + .q_1_6(bo_1_6), + .q_1_7(bo_1_7), + .q_1_8(bo_1_8), + .q_1_9(bo_1_9), + .q_1_10(bo_1_10), + .q_1_11(bo_1_11), + .q_1_12(bo_1_12), + .q_1_13(bo_1_13), + .q_1_14(bo_1_14), + .q_1_15(bo_1_15), + .q_2_0(bo_2_0), + .q_2_1(bo_2_1), + .q_2_2(bo_2_2), + .q_2_3(bo_2_3), + .q_2_4(bo_2_4), + .q_2_5(bo_2_5), + .q_2_6(bo_2_6), + .q_2_7(bo_2_7), + .q_2_8(bo_2_8), + .q_2_9(bo_2_9), + .q_2_10(bo_2_10), + .q_2_11(bo_2_11), + .q_2_12(bo_2_12), + .q_2_13(bo_2_13), + .q_2_14(bo_2_14), + .q_2_15(bo_2_15), + .index(input_index_counter) +); + +weight_buffer_18_16_3_64_bc_0 weight_buffer_18_16_3_64_bc_0_inst_ypznrhugeu ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[5]), + .q_0_0(bc_0_0), + .q_0_1(bc_0_1), + .q_0_2(bc_0_2), + .q_0_3(bc_0_3), + .q_0_4(bc_0_4), + .q_0_5(bc_0_5), + .q_0_6(bc_0_6), + .q_0_7(bc_0_7), + .q_0_8(bc_0_8), + .q_0_9(bc_0_9), + .q_0_10(bc_0_10), + .q_0_11(bc_0_11), + .q_0_12(bc_0_12), + .q_0_13(bc_0_13), + .q_0_14(bc_0_14), + .q_0_15(bc_0_15), + .q_1_0(bc_1_0), + .q_1_1(bc_1_1), + .q_1_2(bc_1_2), + .q_1_3(bc_1_3), + .q_1_4(bc_1_4), + .q_1_5(bc_1_5), + .q_1_6(bc_1_6), + .q_1_7(bc_1_7), + .q_1_8(bc_1_8), + .q_1_9(bc_1_9), + .q_1_10(bc_1_10), + .q_1_11(bc_1_11), + .q_1_12(bc_1_12), + .q_1_13(bc_1_13), + .q_1_14(bc_1_14), + .q_1_15(bc_1_15), + .q_2_0(bc_2_0), + .q_2_1(bc_2_1), + .q_2_2(bc_2_2), + .q_2_3(bc_2_3), + .q_2_4(bc_2_4), + .q_2_5(bc_2_5), + .q_2_6(bc_2_6), + .q_2_7(bc_2_7), + .q_2_8(bc_2_8), + .q_2_9(bc_2_9), + .q_2_10(bc_2_10), + .q_2_11(bc_2_11), + .q_2_12(bc_2_12), + .q_2_13(bc_2_13), + .q_2_14(bc_2_14), + .q_2_15(bc_2_15), + .index(input_index_counter) +); + +assign o_Wic_0 = Wic_0_0; +assign o_bi_0 = bi_0_0; +assign o_Wfc_0 = Wfc_0_0; +assign o_bf_0 = bf_0_0; +assign o_Woc_0 = Woc_0_0; +assign o_bo_0 = bo_0_0; +assign o_bc_0 = bc_0_0; +assign o_Wic_1 = Wic_0_1; +assign o_bi_1 = bi_0_1; +assign o_Wfc_1 = Wfc_0_1; +assign o_bf_1 = bf_0_1; +assign o_Woc_1 = Woc_0_1; +assign o_bo_1 = bo_0_1; +assign o_bc_1 = bc_0_1; +assign o_Wic_2 = Wic_0_2; +assign o_bi_2 = bi_0_2; +assign o_Wfc_2 = Wfc_0_2; +assign o_bf_2 = bf_0_2; +assign o_Woc_2 = Woc_0_2; +assign o_bo_2 = bo_0_2; +assign o_bc_2 = bc_0_2; +assign o_Wic_3 = Wic_0_3; +assign o_bi_3 = bi_0_3; +assign o_Wfc_3 = Wfc_0_3; +assign o_bf_3 = bf_0_3; +assign o_Woc_3 = Woc_0_3; +assign o_bo_3 = bo_0_3; +assign o_bc_3 = bc_0_3; +assign o_Wic_4 = Wic_0_4; +assign o_bi_4 = bi_0_4; +assign o_Wfc_4 = Wfc_0_4; +assign o_bf_4 = bf_0_4; +assign o_Woc_4 = Woc_0_4; +assign o_bo_4 = bo_0_4; +assign o_bc_4 = bc_0_4; +assign o_Wic_5 = Wic_0_5; +assign o_bi_5 = bi_0_5; +assign o_Wfc_5 = Wfc_0_5; +assign o_bf_5 = bf_0_5; +assign o_Woc_5 = Woc_0_5; +assign o_bo_5 = bo_0_5; +assign o_bc_5 = bc_0_5; +assign o_Wic_6 = Wic_0_6; +assign o_bi_6 = bi_0_6; +assign o_Wfc_6 = Wfc_0_6; +assign o_bf_6 = bf_0_6; +assign o_Woc_6 = Woc_0_6; +assign o_bo_6 = bo_0_6; +assign o_bc_6 = bc_0_6; +assign o_Wic_7 = Wic_0_7; +assign o_bi_7 = bi_0_7; +assign o_Wfc_7 = Wfc_0_7; +assign o_bf_7 = bf_0_7; +assign o_Woc_7 = Woc_0_7; +assign o_bo_7 = bo_0_7; +assign o_bc_7 = bc_0_7; +assign o_Wic_8 = Wic_0_8; +assign o_bi_8 = bi_0_8; +assign o_Wfc_8 = Wfc_0_8; +assign o_bf_8 = bf_0_8; +assign o_Woc_8 = Woc_0_8; +assign o_bo_8 = bo_0_8; +assign o_bc_8 = bc_0_8; +assign o_Wic_9 = Wic_0_9; +assign o_bi_9 = bi_0_9; +assign o_Wfc_9 = Wfc_0_9; +assign o_bf_9 = bf_0_9; +assign o_Woc_9 = Woc_0_9; +assign o_bo_9 = bo_0_9; +assign o_bc_9 = bc_0_9; +assign o_Wic_10 = Wic_0_10; +assign o_bi_10 = bi_0_10; +assign o_Wfc_10 = Wfc_0_10; +assign o_bf_10 = bf_0_10; +assign o_Woc_10 = Woc_0_10; +assign o_bo_10 = bo_0_10; +assign o_bc_10 = bc_0_10; +assign o_Wic_11 = Wic_0_11; +assign o_bi_11 = bi_0_11; +assign o_Wfc_11 = Wfc_0_11; +assign o_bf_11 = bf_0_11; +assign o_Woc_11 = Woc_0_11; +assign o_bo_11 = bo_0_11; +assign o_bc_11 = bc_0_11; +assign o_Wic_12 = Wic_0_12; +assign o_bi_12 = bi_0_12; +assign o_Wfc_12 = Wfc_0_12; +assign o_bf_12 = bf_0_12; +assign o_Woc_12 = Woc_0_12; +assign o_bo_12 = bo_0_12; +assign o_bc_12 = bc_0_12; +assign o_Wic_13 = Wic_0_13; +assign o_bi_13 = bi_0_13; +assign o_Wfc_13 = Wfc_0_13; +assign o_bf_13 = bf_0_13; +assign o_Woc_13 = Woc_0_13; +assign o_bo_13 = bo_0_13; +assign o_bc_13 = bc_0_13; +assign o_Wic_14 = Wic_0_14; +assign o_bi_14 = bi_0_14; +assign o_Wfc_14 = Wfc_0_14; +assign o_bf_14 = bf_0_14; +assign o_Woc_14 = Woc_0_14; +assign o_bo_14 = bo_0_14; +assign o_bc_14 = bc_0_14; +assign o_Wic_15 = Wic_0_15; +assign o_bi_15 = bi_0_15; +assign o_Wfc_15 = Wfc_0_15; +assign o_bf_15 = bf_0_15; +assign o_Woc_15 = Woc_0_15; +assign o_bo_15 = bo_0_15; +assign o_bc_15 = bc_0_15; +assign o_Wic_16 = Wic_1_0; +assign o_bi_16 = bi_1_0; +assign o_Wfc_16 = Wfc_1_0; +assign o_bf_16 = bf_1_0; +assign o_Woc_16 = Woc_1_0; +assign o_bo_16 = bo_1_0; +assign o_bc_16 = bc_1_0; +assign o_Wic_17 = Wic_1_1; +assign o_bi_17 = bi_1_1; +assign o_Wfc_17 = Wfc_1_1; +assign o_bf_17 = bf_1_1; +assign o_Woc_17 = Woc_1_1; +assign o_bo_17 = bo_1_1; +assign o_bc_17 = bc_1_1; +assign o_Wic_18 = Wic_1_2; +assign o_bi_18 = bi_1_2; +assign o_Wfc_18 = Wfc_1_2; +assign o_bf_18 = bf_1_2; +assign o_Woc_18 = Woc_1_2; +assign o_bo_18 = bo_1_2; +assign o_bc_18 = bc_1_2; +assign o_Wic_19 = Wic_1_3; +assign o_bi_19 = bi_1_3; +assign o_Wfc_19 = Wfc_1_3; +assign o_bf_19 = bf_1_3; +assign o_Woc_19 = Woc_1_3; +assign o_bo_19 = bo_1_3; +assign o_bc_19 = bc_1_3; +assign o_Wic_20 = Wic_1_4; +assign o_bi_20 = bi_1_4; +assign o_Wfc_20 = Wfc_1_4; +assign o_bf_20 = bf_1_4; +assign o_Woc_20 = Woc_1_4; +assign o_bo_20 = bo_1_4; +assign o_bc_20 = bc_1_4; +assign o_Wic_21 = Wic_1_5; +assign o_bi_21 = bi_1_5; +assign o_Wfc_21 = Wfc_1_5; +assign o_bf_21 = bf_1_5; +assign o_Woc_21 = Woc_1_5; +assign o_bo_21 = bo_1_5; +assign o_bc_21 = bc_1_5; +assign o_Wic_22 = Wic_1_6; +assign o_bi_22 = bi_1_6; +assign o_Wfc_22 = Wfc_1_6; +assign o_bf_22 = bf_1_6; +assign o_Woc_22 = Woc_1_6; +assign o_bo_22 = bo_1_6; +assign o_bc_22 = bc_1_6; +assign o_Wic_23 = Wic_1_7; +assign o_bi_23 = bi_1_7; +assign o_Wfc_23 = Wfc_1_7; +assign o_bf_23 = bf_1_7; +assign o_Woc_23 = Woc_1_7; +assign o_bo_23 = bo_1_7; +assign o_bc_23 = bc_1_7; +assign o_Wic_24 = Wic_1_8; +assign o_bi_24 = bi_1_8; +assign o_Wfc_24 = Wfc_1_8; +assign o_bf_24 = bf_1_8; +assign o_Woc_24 = Woc_1_8; +assign o_bo_24 = bo_1_8; +assign o_bc_24 = bc_1_8; +assign o_Wic_25 = Wic_1_9; +assign o_bi_25 = bi_1_9; +assign o_Wfc_25 = Wfc_1_9; +assign o_bf_25 = bf_1_9; +assign o_Woc_25 = Woc_1_9; +assign o_bo_25 = bo_1_9; +assign o_bc_25 = bc_1_9; +assign o_Wic_26 = Wic_1_10; +assign o_bi_26 = bi_1_10; +assign o_Wfc_26 = Wfc_1_10; +assign o_bf_26 = bf_1_10; +assign o_Woc_26 = Woc_1_10; +assign o_bo_26 = bo_1_10; +assign o_bc_26 = bc_1_10; +assign o_Wic_27 = Wic_1_11; +assign o_bi_27 = bi_1_11; +assign o_Wfc_27 = Wfc_1_11; +assign o_bf_27 = bf_1_11; +assign o_Woc_27 = Woc_1_11; +assign o_bo_27 = bo_1_11; +assign o_bc_27 = bc_1_11; +assign o_Wic_28 = Wic_1_12; +assign o_bi_28 = bi_1_12; +assign o_Wfc_28 = Wfc_1_12; +assign o_bf_28 = bf_1_12; +assign o_Woc_28 = Woc_1_12; +assign o_bo_28 = bo_1_12; +assign o_bc_28 = bc_1_12; +assign o_Wic_29 = Wic_1_13; +assign o_bi_29 = bi_1_13; +assign o_Wfc_29 = Wfc_1_13; +assign o_bf_29 = bf_1_13; +assign o_Woc_29 = Woc_1_13; +assign o_bo_29 = bo_1_13; +assign o_bc_29 = bc_1_13; +assign o_Wic_30 = Wic_1_14; +assign o_bi_30 = bi_1_14; +assign o_Wfc_30 = Wfc_1_14; +assign o_bf_30 = bf_1_14; +assign o_Woc_30 = Woc_1_14; +assign o_bo_30 = bo_1_14; +assign o_bc_30 = bc_1_14; +assign o_Wic_31 = Wic_1_15; +assign o_bi_31 = bi_1_15; +assign o_Wfc_31 = Wfc_1_15; +assign o_bf_31 = bf_1_15; +assign o_Woc_31 = Woc_1_15; +assign o_bo_31 = bo_1_15; +assign o_bc_31 = bc_1_15; +assign o_Wic_32 = Wic_2_0; +assign o_bi_32 = bi_2_0; +assign o_Wfc_32 = Wfc_2_0; +assign o_bf_32 = bf_2_0; +assign o_Woc_32 = Woc_2_0; +assign o_bo_32 = bo_2_0; +assign o_bc_32 = bc_2_0; +assign o_Wic_33 = Wic_2_1; +assign o_bi_33 = bi_2_1; +assign o_Wfc_33 = Wfc_2_1; +assign o_bf_33 = bf_2_1; +assign o_Woc_33 = Woc_2_1; +assign o_bo_33 = bo_2_1; +assign o_bc_33 = bc_2_1; +assign o_Wic_34 = Wic_2_2; +assign o_bi_34 = bi_2_2; +assign o_Wfc_34 = Wfc_2_2; +assign o_bf_34 = bf_2_2; +assign o_Woc_34 = Woc_2_2; +assign o_bo_34 = bo_2_2; +assign o_bc_34 = bc_2_2; +assign o_Wic_35 = Wic_2_3; +assign o_bi_35 = bi_2_3; +assign o_Wfc_35 = Wfc_2_3; +assign o_bf_35 = bf_2_3; +assign o_Woc_35 = Woc_2_3; +assign o_bo_35 = bo_2_3; +assign o_bc_35 = bc_2_3; +assign o_Wic_36 = Wic_2_4; +assign o_bi_36 = bi_2_4; +assign o_Wfc_36 = Wfc_2_4; +assign o_bf_36 = bf_2_4; +assign o_Woc_36 = Woc_2_4; +assign o_bo_36 = bo_2_4; +assign o_bc_36 = bc_2_4; +assign o_Wic_37 = Wic_2_5; +assign o_bi_37 = bi_2_5; +assign o_Wfc_37 = Wfc_2_5; +assign o_bf_37 = bf_2_5; +assign o_Woc_37 = Woc_2_5; +assign o_bo_37 = bo_2_5; +assign o_bc_37 = bc_2_5; +assign o_Wic_38 = Wic_2_6; +assign o_bi_38 = bi_2_6; +assign o_Wfc_38 = Wfc_2_6; +assign o_bf_38 = bf_2_6; +assign o_Woc_38 = Woc_2_6; +assign o_bo_38 = bo_2_6; +assign o_bc_38 = bc_2_6; +assign o_Wic_39 = Wic_2_7; +assign o_bi_39 = bi_2_7; +assign o_Wfc_39 = Wfc_2_7; +assign o_bf_39 = bf_2_7; +assign o_Woc_39 = Woc_2_7; +assign o_bo_39 = bo_2_7; +assign o_bc_39 = bc_2_7; +assign o_Wic_40 = Wic_2_8; +assign o_bi_40 = bi_2_8; +assign o_Wfc_40 = Wfc_2_8; +assign o_bf_40 = bf_2_8; +assign o_Woc_40 = Woc_2_8; +assign o_bo_40 = bo_2_8; +assign o_bc_40 = bc_2_8; +assign o_Wic_41 = Wic_2_9; +assign o_bi_41 = bi_2_9; +assign o_Wfc_41 = Wfc_2_9; +assign o_bf_41 = bf_2_9; +assign o_Woc_41 = Woc_2_9; +assign o_bo_41 = bo_2_9; +assign o_bc_41 = bc_2_9; +assign o_Wic_42 = Wic_2_10; +assign o_bi_42 = bi_2_10; +assign o_Wfc_42 = Wfc_2_10; +assign o_bf_42 = bf_2_10; +assign o_Woc_42 = Woc_2_10; +assign o_bo_42 = bo_2_10; +assign o_bc_42 = bc_2_10; +assign o_Wic_43 = Wic_2_11; +assign o_bi_43 = bi_2_11; +assign o_Wfc_43 = Wfc_2_11; +assign o_bf_43 = bf_2_11; +assign o_Woc_43 = Woc_2_11; +assign o_bo_43 = bo_2_11; +assign o_bc_43 = bc_2_11; +assign o_Wic_44 = Wic_2_12; +assign o_bi_44 = bi_2_12; +assign o_Wfc_44 = Wfc_2_12; +assign o_bf_44 = bf_2_12; +assign o_Woc_44 = Woc_2_12; +assign o_bo_44 = bo_2_12; +assign o_bc_44 = bc_2_12; +assign o_Wic_45 = Wic_2_13; +assign o_bi_45 = bi_2_13; +assign o_Wfc_45 = Wfc_2_13; +assign o_bf_45 = bf_2_13; +assign o_Woc_45 = Woc_2_13; +assign o_bo_45 = bo_2_13; +assign o_bc_45 = bc_2_13; +assign o_Wic_46 = Wic_2_14; +assign o_bi_46 = bi_2_14; +assign o_Wfc_46 = Wfc_2_14; +assign o_bf_46 = bf_2_14; +assign o_Woc_46 = Woc_2_14; +assign o_bo_46 = bo_2_14; +assign o_bc_46 = bc_2_14; +assign o_Wic_47 = Wic_2_15; +assign o_bi_47 = bi_2_15; +assign o_Wfc_47 = Wfc_2_15; +assign o_bf_47 = bf_2_15; +assign o_Woc_47 = Woc_2_15; +assign o_bo_47 = bo_2_15; +assign o_bc_47 = bc_2_15; + +endmodule + +module weight_buffer_18_16_3_64_Wic_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_1_9, + output [17:0] q_1_10, + output [17:0] q_1_11, + output [17:0] q_1_12, + output [17:0] q_1_13, + output [17:0] q_1_14, + output [17:0] q_1_15, + output [17:0] q_2_0, + output [17:0] q_2_1, + output [17:0] q_2_2, + output [17:0] q_2_3, + output [17:0] q_2_4, + output [17:0] q_2_5, + output [17:0] q_2_6, + output [17:0] q_2_7, + output [17:0] q_2_8, + output [17:0] q_2_9, + output [17:0] q_2_10, + output [17:0] q_2_11, + output [17:0] q_2_12, + output [17:0] q_2_13, + output [17:0] q_2_14, + output [17:0] q_2_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; +wire [287:0] packed_result_1; +reg [5:0] addrs_1; +reg [5:0] addrs_base_1; +wire [287:0] packed_result_2; +reg [5:0] addrs_2; +reg [5:0] addrs_base_2; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 1; + addrs_base_2 <= 2; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + addrs_2 <= index + addrs_base_2; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_2 ( + .we(wen), + .addr(addrs_2), + .data(wdata), + .out(packed_result_2), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_1_9 = packed_result_1[179:162]; +assign q_1_10 = packed_result_1[197:180]; +assign q_1_11 = packed_result_1[215:198]; +assign q_1_12 = packed_result_1[233:216]; +assign q_1_13 = packed_result_1[251:234]; +assign q_1_14 = packed_result_1[269:252]; +assign q_1_15 = packed_result_1[287:270]; +assign q_2_0 = packed_result_2[17:0]; +assign q_2_1 = packed_result_2[35:18]; +assign q_2_2 = packed_result_2[53:36]; +assign q_2_3 = packed_result_2[71:54]; +assign q_2_4 = packed_result_2[89:72]; +assign q_2_5 = packed_result_2[107:90]; +assign q_2_6 = packed_result_2[125:108]; +assign q_2_7 = packed_result_2[143:126]; +assign q_2_8 = packed_result_2[161:144]; +assign q_2_9 = packed_result_2[179:162]; +assign q_2_10 = packed_result_2[197:180]; +assign q_2_11 = packed_result_2[215:198]; +assign q_2_12 = packed_result_2[233:216]; +assign q_2_13 = packed_result_2[251:234]; +assign q_2_14 = packed_result_2[269:252]; +assign q_2_15 = packed_result_2[287:270]; + +endmodule + +module weight_buffer_18_16_3_64_bi_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_1_9, + output [17:0] q_1_10, + output [17:0] q_1_11, + output [17:0] q_1_12, + output [17:0] q_1_13, + output [17:0] q_1_14, + output [17:0] q_1_15, + output [17:0] q_2_0, + output [17:0] q_2_1, + output [17:0] q_2_2, + output [17:0] q_2_3, + output [17:0] q_2_4, + output [17:0] q_2_5, + output [17:0] q_2_6, + output [17:0] q_2_7, + output [17:0] q_2_8, + output [17:0] q_2_9, + output [17:0] q_2_10, + output [17:0] q_2_11, + output [17:0] q_2_12, + output [17:0] q_2_13, + output [17:0] q_2_14, + output [17:0] q_2_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; +wire [287:0] packed_result_1; +reg [5:0] addrs_1; +reg [5:0] addrs_base_1; +wire [287:0] packed_result_2; +reg [5:0] addrs_2; +reg [5:0] addrs_base_2; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 1; + addrs_base_2 <= 2; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + addrs_2 <= index + addrs_base_2; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_2 ( + .we(wen), + .addr(addrs_2), + .data(wdata), + .out(packed_result_2), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_1_9 = packed_result_1[179:162]; +assign q_1_10 = packed_result_1[197:180]; +assign q_1_11 = packed_result_1[215:198]; +assign q_1_12 = packed_result_1[233:216]; +assign q_1_13 = packed_result_1[251:234]; +assign q_1_14 = packed_result_1[269:252]; +assign q_1_15 = packed_result_1[287:270]; +assign q_2_0 = packed_result_2[17:0]; +assign q_2_1 = packed_result_2[35:18]; +assign q_2_2 = packed_result_2[53:36]; +assign q_2_3 = packed_result_2[71:54]; +assign q_2_4 = packed_result_2[89:72]; +assign q_2_5 = packed_result_2[107:90]; +assign q_2_6 = packed_result_2[125:108]; +assign q_2_7 = packed_result_2[143:126]; +assign q_2_8 = packed_result_2[161:144]; +assign q_2_9 = packed_result_2[179:162]; +assign q_2_10 = packed_result_2[197:180]; +assign q_2_11 = packed_result_2[215:198]; +assign q_2_12 = packed_result_2[233:216]; +assign q_2_13 = packed_result_2[251:234]; +assign q_2_14 = packed_result_2[269:252]; +assign q_2_15 = packed_result_2[287:270]; + +endmodule + +module weight_buffer_18_16_3_64_Wfc_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_1_9, + output [17:0] q_1_10, + output [17:0] q_1_11, + output [17:0] q_1_12, + output [17:0] q_1_13, + output [17:0] q_1_14, + output [17:0] q_1_15, + output [17:0] q_2_0, + output [17:0] q_2_1, + output [17:0] q_2_2, + output [17:0] q_2_3, + output [17:0] q_2_4, + output [17:0] q_2_5, + output [17:0] q_2_6, + output [17:0] q_2_7, + output [17:0] q_2_8, + output [17:0] q_2_9, + output [17:0] q_2_10, + output [17:0] q_2_11, + output [17:0] q_2_12, + output [17:0] q_2_13, + output [17:0] q_2_14, + output [17:0] q_2_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; +wire [287:0] packed_result_1; +reg [5:0] addrs_1; +reg [5:0] addrs_base_1; +wire [287:0] packed_result_2; +reg [5:0] addrs_2; +reg [5:0] addrs_base_2; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 1; + addrs_base_2 <= 2; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + addrs_2 <= index + addrs_base_2; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_2 ( + .we(wen), + .addr(addrs_2), + .data(wdata), + .out(packed_result_2), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_1_9 = packed_result_1[179:162]; +assign q_1_10 = packed_result_1[197:180]; +assign q_1_11 = packed_result_1[215:198]; +assign q_1_12 = packed_result_1[233:216]; +assign q_1_13 = packed_result_1[251:234]; +assign q_1_14 = packed_result_1[269:252]; +assign q_1_15 = packed_result_1[287:270]; +assign q_2_0 = packed_result_2[17:0]; +assign q_2_1 = packed_result_2[35:18]; +assign q_2_2 = packed_result_2[53:36]; +assign q_2_3 = packed_result_2[71:54]; +assign q_2_4 = packed_result_2[89:72]; +assign q_2_5 = packed_result_2[107:90]; +assign q_2_6 = packed_result_2[125:108]; +assign q_2_7 = packed_result_2[143:126]; +assign q_2_8 = packed_result_2[161:144]; +assign q_2_9 = packed_result_2[179:162]; +assign q_2_10 = packed_result_2[197:180]; +assign q_2_11 = packed_result_2[215:198]; +assign q_2_12 = packed_result_2[233:216]; +assign q_2_13 = packed_result_2[251:234]; +assign q_2_14 = packed_result_2[269:252]; +assign q_2_15 = packed_result_2[287:270]; + +endmodule + +module weight_buffer_18_16_3_64_bf_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_1_9, + output [17:0] q_1_10, + output [17:0] q_1_11, + output [17:0] q_1_12, + output [17:0] q_1_13, + output [17:0] q_1_14, + output [17:0] q_1_15, + output [17:0] q_2_0, + output [17:0] q_2_1, + output [17:0] q_2_2, + output [17:0] q_2_3, + output [17:0] q_2_4, + output [17:0] q_2_5, + output [17:0] q_2_6, + output [17:0] q_2_7, + output [17:0] q_2_8, + output [17:0] q_2_9, + output [17:0] q_2_10, + output [17:0] q_2_11, + output [17:0] q_2_12, + output [17:0] q_2_13, + output [17:0] q_2_14, + output [17:0] q_2_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; +wire [287:0] packed_result_1; +reg [5:0] addrs_1; +reg [5:0] addrs_base_1; +wire [287:0] packed_result_2; +reg [5:0] addrs_2; +reg [5:0] addrs_base_2; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 1; + addrs_base_2 <= 2; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + addrs_2 <= index + addrs_base_2; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_2 ( + .we(wen), + .addr(addrs_2), + .data(wdata), + .out(packed_result_2), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_1_9 = packed_result_1[179:162]; +assign q_1_10 = packed_result_1[197:180]; +assign q_1_11 = packed_result_1[215:198]; +assign q_1_12 = packed_result_1[233:216]; +assign q_1_13 = packed_result_1[251:234]; +assign q_1_14 = packed_result_1[269:252]; +assign q_1_15 = packed_result_1[287:270]; +assign q_2_0 = packed_result_2[17:0]; +assign q_2_1 = packed_result_2[35:18]; +assign q_2_2 = packed_result_2[53:36]; +assign q_2_3 = packed_result_2[71:54]; +assign q_2_4 = packed_result_2[89:72]; +assign q_2_5 = packed_result_2[107:90]; +assign q_2_6 = packed_result_2[125:108]; +assign q_2_7 = packed_result_2[143:126]; +assign q_2_8 = packed_result_2[161:144]; +assign q_2_9 = packed_result_2[179:162]; +assign q_2_10 = packed_result_2[197:180]; +assign q_2_11 = packed_result_2[215:198]; +assign q_2_12 = packed_result_2[233:216]; +assign q_2_13 = packed_result_2[251:234]; +assign q_2_14 = packed_result_2[269:252]; +assign q_2_15 = packed_result_2[287:270]; + +endmodule + +module weight_buffer_18_16_3_64_Woc_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_1_9, + output [17:0] q_1_10, + output [17:0] q_1_11, + output [17:0] q_1_12, + output [17:0] q_1_13, + output [17:0] q_1_14, + output [17:0] q_1_15, + output [17:0] q_2_0, + output [17:0] q_2_1, + output [17:0] q_2_2, + output [17:0] q_2_3, + output [17:0] q_2_4, + output [17:0] q_2_5, + output [17:0] q_2_6, + output [17:0] q_2_7, + output [17:0] q_2_8, + output [17:0] q_2_9, + output [17:0] q_2_10, + output [17:0] q_2_11, + output [17:0] q_2_12, + output [17:0] q_2_13, + output [17:0] q_2_14, + output [17:0] q_2_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; +wire [287:0] packed_result_1; +reg [5:0] addrs_1; +reg [5:0] addrs_base_1; +wire [287:0] packed_result_2; +reg [5:0] addrs_2; +reg [5:0] addrs_base_2; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 1; + addrs_base_2 <= 2; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + addrs_2 <= index + addrs_base_2; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_2 ( + .we(wen), + .addr(addrs_2), + .data(wdata), + .out(packed_result_2), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_1_9 = packed_result_1[179:162]; +assign q_1_10 = packed_result_1[197:180]; +assign q_1_11 = packed_result_1[215:198]; +assign q_1_12 = packed_result_1[233:216]; +assign q_1_13 = packed_result_1[251:234]; +assign q_1_14 = packed_result_1[269:252]; +assign q_1_15 = packed_result_1[287:270]; +assign q_2_0 = packed_result_2[17:0]; +assign q_2_1 = packed_result_2[35:18]; +assign q_2_2 = packed_result_2[53:36]; +assign q_2_3 = packed_result_2[71:54]; +assign q_2_4 = packed_result_2[89:72]; +assign q_2_5 = packed_result_2[107:90]; +assign q_2_6 = packed_result_2[125:108]; +assign q_2_7 = packed_result_2[143:126]; +assign q_2_8 = packed_result_2[161:144]; +assign q_2_9 = packed_result_2[179:162]; +assign q_2_10 = packed_result_2[197:180]; +assign q_2_11 = packed_result_2[215:198]; +assign q_2_12 = packed_result_2[233:216]; +assign q_2_13 = packed_result_2[251:234]; +assign q_2_14 = packed_result_2[269:252]; +assign q_2_15 = packed_result_2[287:270]; + +endmodule + +module weight_buffer_18_16_3_64_bo_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_1_9, + output [17:0] q_1_10, + output [17:0] q_1_11, + output [17:0] q_1_12, + output [17:0] q_1_13, + output [17:0] q_1_14, + output [17:0] q_1_15, + output [17:0] q_2_0, + output [17:0] q_2_1, + output [17:0] q_2_2, + output [17:0] q_2_3, + output [17:0] q_2_4, + output [17:0] q_2_5, + output [17:0] q_2_6, + output [17:0] q_2_7, + output [17:0] q_2_8, + output [17:0] q_2_9, + output [17:0] q_2_10, + output [17:0] q_2_11, + output [17:0] q_2_12, + output [17:0] q_2_13, + output [17:0] q_2_14, + output [17:0] q_2_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; +wire [287:0] packed_result_1; +reg [5:0] addrs_1; +reg [5:0] addrs_base_1; +wire [287:0] packed_result_2; +reg [5:0] addrs_2; +reg [5:0] addrs_base_2; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 1; + addrs_base_2 <= 2; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + addrs_2 <= index + addrs_base_2; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_2 ( + .we(wen), + .addr(addrs_2), + .data(wdata), + .out(packed_result_2), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_1_9 = packed_result_1[179:162]; +assign q_1_10 = packed_result_1[197:180]; +assign q_1_11 = packed_result_1[215:198]; +assign q_1_12 = packed_result_1[233:216]; +assign q_1_13 = packed_result_1[251:234]; +assign q_1_14 = packed_result_1[269:252]; +assign q_1_15 = packed_result_1[287:270]; +assign q_2_0 = packed_result_2[17:0]; +assign q_2_1 = packed_result_2[35:18]; +assign q_2_2 = packed_result_2[53:36]; +assign q_2_3 = packed_result_2[71:54]; +assign q_2_4 = packed_result_2[89:72]; +assign q_2_5 = packed_result_2[107:90]; +assign q_2_6 = packed_result_2[125:108]; +assign q_2_7 = packed_result_2[143:126]; +assign q_2_8 = packed_result_2[161:144]; +assign q_2_9 = packed_result_2[179:162]; +assign q_2_10 = packed_result_2[197:180]; +assign q_2_11 = packed_result_2[215:198]; +assign q_2_12 = packed_result_2[233:216]; +assign q_2_13 = packed_result_2[251:234]; +assign q_2_14 = packed_result_2[269:252]; +assign q_2_15 = packed_result_2[287:270]; + +endmodule + +module weight_buffer_18_16_3_64_bc_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_1_9, + output [17:0] q_1_10, + output [17:0] q_1_11, + output [17:0] q_1_12, + output [17:0] q_1_13, + output [17:0] q_1_14, + output [17:0] q_1_15, + output [17:0] q_2_0, + output [17:0] q_2_1, + output [17:0] q_2_2, + output [17:0] q_2_3, + output [17:0] q_2_4, + output [17:0] q_2_5, + output [17:0] q_2_6, + output [17:0] q_2_7, + output [17:0] q_2_8, + output [17:0] q_2_9, + output [17:0] q_2_10, + output [17:0] q_2_11, + output [17:0] q_2_12, + output [17:0] q_2_13, + output [17:0] q_2_14, + output [17:0] q_2_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; +wire [287:0] packed_result_1; +reg [5:0] addrs_1; +reg [5:0] addrs_base_1; +wire [287:0] packed_result_2; +reg [5:0] addrs_2; +reg [5:0] addrs_base_2; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 1; + addrs_base_2 <= 2; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + addrs_2 <= index + addrs_base_2; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_2 ( + .we(wen), + .addr(addrs_2), + .data(wdata), + .out(packed_result_2), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_1_9 = packed_result_1[179:162]; +assign q_1_10 = packed_result_1[197:180]; +assign q_1_11 = packed_result_1[215:198]; +assign q_1_12 = packed_result_1[233:216]; +assign q_1_13 = packed_result_1[251:234]; +assign q_1_14 = packed_result_1[269:252]; +assign q_1_15 = packed_result_1[287:270]; +assign q_2_0 = packed_result_2[17:0]; +assign q_2_1 = packed_result_2[35:18]; +assign q_2_2 = packed_result_2[53:36]; +assign q_2_3 = packed_result_2[71:54]; +assign q_2_4 = packed_result_2[89:72]; +assign q_2_5 = packed_result_2[107:90]; +assign q_2_6 = packed_result_2[125:108]; +assign q_2_7 = packed_result_2[143:126]; +assign q_2_8 = packed_result_2[161:144]; +assign q_2_9 = packed_result_2[179:162]; +assign q_2_10 = packed_result_2[197:180]; +assign q_2_11 = packed_result_2[215:198]; +assign q_2_12 = packed_result_2[233:216]; +assign q_2_13 = packed_result_2[251:234]; +assign q_2_14 = packed_result_2[269:252]; +assign q_2_15 = packed_result_2[287:270]; + +endmodule + +module shift_register_group_18_48_3 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input [17:0] in_16, + output [17:0] out_16, + input [17:0] in_17, + output [17:0] out_17, + input [17:0] in_18, + output [17:0] out_18, + input [17:0] in_19, + output [17:0] out_19, + input [17:0] in_20, + output [17:0] out_20, + input [17:0] in_21, + output [17:0] out_21, + input [17:0] in_22, + output [17:0] out_22, + input [17:0] in_23, + output [17:0] out_23, + input [17:0] in_24, + output [17:0] out_24, + input [17:0] in_25, + output [17:0] out_25, + input [17:0] in_26, + output [17:0] out_26, + input [17:0] in_27, + output [17:0] out_27, + input [17:0] in_28, + output [17:0] out_28, + input [17:0] in_29, + output [17:0] out_29, + input [17:0] in_30, + output [17:0] out_30, + input [17:0] in_31, + output [17:0] out_31, + input [17:0] in_32, + output [17:0] out_32, + input [17:0] in_33, + output [17:0] out_33, + input [17:0] in_34, + output [17:0] out_34, + input [17:0] in_35, + output [17:0] out_35, + input [17:0] in_36, + output [17:0] out_36, + input [17:0] in_37, + output [17:0] out_37, + input [17:0] in_38, + output [17:0] out_38, + input [17:0] in_39, + output [17:0] out_39, + input [17:0] in_40, + output [17:0] out_40, + input [17:0] in_41, + output [17:0] out_41, + input [17:0] in_42, + output [17:0] out_42, + input [17:0] in_43, + output [17:0] out_43, + input [17:0] in_44, + output [17:0] out_44, + input [17:0] in_45, + output [17:0] out_45, + input [17:0] in_46, + output [17:0] out_46, + input [17:0] in_47, + output [17:0] out_47, + input reset +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_16 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_16), + .out(out_16) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_17 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_17), + .out(out_17) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_18 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_18), + .out(out_18) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_19 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_19), + .out(out_19) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_20 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_20), + .out(out_20) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_21 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_21), + .out(out_21) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_22 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_22), + .out(out_22) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_23 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_23), + .out(out_23) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_24 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_24), + .out(out_24) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_25 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_25), + .out(out_25) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_26 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_26), + .out(out_26) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_27 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_27), + .out(out_27) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_28 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_28), + .out(out_28) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_29 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_29), + .out(out_29) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_30 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_30), + .out(out_30) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_31 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_31), + .out(out_31) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_32 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_32), + .out(out_32) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_33 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_33), + .out(out_33) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_34 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_34), + .out(out_34) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_35 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_35), + .out(out_35) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_36 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_36), + .out(out_36) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_37 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_37), + .out(out_37) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_38 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_38), + .out(out_38) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_39 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_39), + .out(out_39) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_40 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_40), + .out(out_40) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_41 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_41), + .out(out_41) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_42 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_42), + .out(out_42) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_43 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_43), + .out(out_43) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_44 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_44), + .out(out_44) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_45 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_45), + .out(out_45) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_46 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_46), + .out(out_46) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_47 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_47), + .out(out_47) +); + +endmodule + +module C_LSTM_stage_2_18_10_48_1 ( + input clk, + input reset, + input enable, + input i_valid, + input [17:0] Ct_1_0, + input [17:0] WixrXtYt_1_0, + input [17:0] Wic_0, + input [17:0] bi_0, + input [17:0] WfxrXtYt_1_0, + input [17:0] Wfc_0, + input [17:0] bf_0, + input [17:0] WoxrXtYt_1_0, + input [17:0] Woc_0, + input [17:0] bo_0, + input [17:0] WcxrXtYt_1_0, + input [17:0] bc_0, + output [17:0] out_mt_0, + output [17:0] out_ct_0, + input [17:0] Ct_1_1, + input [17:0] WixrXtYt_1_1, + input [17:0] Wic_1, + input [17:0] bi_1, + input [17:0] WfxrXtYt_1_1, + input [17:0] Wfc_1, + input [17:0] bf_1, + input [17:0] WoxrXtYt_1_1, + input [17:0] Woc_1, + input [17:0] bo_1, + input [17:0] WcxrXtYt_1_1, + input [17:0] bc_1, + output [17:0] out_mt_1, + output [17:0] out_ct_1, + input [17:0] Ct_1_2, + input [17:0] WixrXtYt_1_2, + input [17:0] Wic_2, + input [17:0] bi_2, + input [17:0] WfxrXtYt_1_2, + input [17:0] Wfc_2, + input [17:0] bf_2, + input [17:0] WoxrXtYt_1_2, + input [17:0] Woc_2, + input [17:0] bo_2, + input [17:0] WcxrXtYt_1_2, + input [17:0] bc_2, + output [17:0] out_mt_2, + output [17:0] out_ct_2, + input [17:0] Ct_1_3, + input [17:0] WixrXtYt_1_3, + input [17:0] Wic_3, + input [17:0] bi_3, + input [17:0] WfxrXtYt_1_3, + input [17:0] Wfc_3, + input [17:0] bf_3, + input [17:0] WoxrXtYt_1_3, + input [17:0] Woc_3, + input [17:0] bo_3, + input [17:0] WcxrXtYt_1_3, + input [17:0] bc_3, + output [17:0] out_mt_3, + output [17:0] out_ct_3, + input [17:0] Ct_1_4, + input [17:0] WixrXtYt_1_4, + input [17:0] Wic_4, + input [17:0] bi_4, + input [17:0] WfxrXtYt_1_4, + input [17:0] Wfc_4, + input [17:0] bf_4, + input [17:0] WoxrXtYt_1_4, + input [17:0] Woc_4, + input [17:0] bo_4, + input [17:0] WcxrXtYt_1_4, + input [17:0] bc_4, + output [17:0] out_mt_4, + output [17:0] out_ct_4, + input [17:0] Ct_1_5, + input [17:0] WixrXtYt_1_5, + input [17:0] Wic_5, + input [17:0] bi_5, + input [17:0] WfxrXtYt_1_5, + input [17:0] Wfc_5, + input [17:0] bf_5, + input [17:0] WoxrXtYt_1_5, + input [17:0] Woc_5, + input [17:0] bo_5, + input [17:0] WcxrXtYt_1_5, + input [17:0] bc_5, + output [17:0] out_mt_5, + output [17:0] out_ct_5, + input [17:0] Ct_1_6, + input [17:0] WixrXtYt_1_6, + input [17:0] Wic_6, + input [17:0] bi_6, + input [17:0] WfxrXtYt_1_6, + input [17:0] Wfc_6, + input [17:0] bf_6, + input [17:0] WoxrXtYt_1_6, + input [17:0] Woc_6, + input [17:0] bo_6, + input [17:0] WcxrXtYt_1_6, + input [17:0] bc_6, + output [17:0] out_mt_6, + output [17:0] out_ct_6, + input [17:0] Ct_1_7, + input [17:0] WixrXtYt_1_7, + input [17:0] Wic_7, + input [17:0] bi_7, + input [17:0] WfxrXtYt_1_7, + input [17:0] Wfc_7, + input [17:0] bf_7, + input [17:0] WoxrXtYt_1_7, + input [17:0] Woc_7, + input [17:0] bo_7, + input [17:0] WcxrXtYt_1_7, + input [17:0] bc_7, + output [17:0] out_mt_7, + output [17:0] out_ct_7, + input [17:0] Ct_1_8, + input [17:0] WixrXtYt_1_8, + input [17:0] Wic_8, + input [17:0] bi_8, + input [17:0] WfxrXtYt_1_8, + input [17:0] Wfc_8, + input [17:0] bf_8, + input [17:0] WoxrXtYt_1_8, + input [17:0] Woc_8, + input [17:0] bo_8, + input [17:0] WcxrXtYt_1_8, + input [17:0] bc_8, + output [17:0] out_mt_8, + output [17:0] out_ct_8, + input [17:0] Ct_1_9, + input [17:0] WixrXtYt_1_9, + input [17:0] Wic_9, + input [17:0] bi_9, + input [17:0] WfxrXtYt_1_9, + input [17:0] Wfc_9, + input [17:0] bf_9, + input [17:0] WoxrXtYt_1_9, + input [17:0] Woc_9, + input [17:0] bo_9, + input [17:0] WcxrXtYt_1_9, + input [17:0] bc_9, + output [17:0] out_mt_9, + output [17:0] out_ct_9, + input [17:0] Ct_1_10, + input [17:0] WixrXtYt_1_10, + input [17:0] Wic_10, + input [17:0] bi_10, + input [17:0] WfxrXtYt_1_10, + input [17:0] Wfc_10, + input [17:0] bf_10, + input [17:0] WoxrXtYt_1_10, + input [17:0] Woc_10, + input [17:0] bo_10, + input [17:0] WcxrXtYt_1_10, + input [17:0] bc_10, + output [17:0] out_mt_10, + output [17:0] out_ct_10, + input [17:0] Ct_1_11, + input [17:0] WixrXtYt_1_11, + input [17:0] Wic_11, + input [17:0] bi_11, + input [17:0] WfxrXtYt_1_11, + input [17:0] Wfc_11, + input [17:0] bf_11, + input [17:0] WoxrXtYt_1_11, + input [17:0] Woc_11, + input [17:0] bo_11, + input [17:0] WcxrXtYt_1_11, + input [17:0] bc_11, + output [17:0] out_mt_11, + output [17:0] out_ct_11, + input [17:0] Ct_1_12, + input [17:0] WixrXtYt_1_12, + input [17:0] Wic_12, + input [17:0] bi_12, + input [17:0] WfxrXtYt_1_12, + input [17:0] Wfc_12, + input [17:0] bf_12, + input [17:0] WoxrXtYt_1_12, + input [17:0] Woc_12, + input [17:0] bo_12, + input [17:0] WcxrXtYt_1_12, + input [17:0] bc_12, + output [17:0] out_mt_12, + output [17:0] out_ct_12, + input [17:0] Ct_1_13, + input [17:0] WixrXtYt_1_13, + input [17:0] Wic_13, + input [17:0] bi_13, + input [17:0] WfxrXtYt_1_13, + input [17:0] Wfc_13, + input [17:0] bf_13, + input [17:0] WoxrXtYt_1_13, + input [17:0] Woc_13, + input [17:0] bo_13, + input [17:0] WcxrXtYt_1_13, + input [17:0] bc_13, + output [17:0] out_mt_13, + output [17:0] out_ct_13, + input [17:0] Ct_1_14, + input [17:0] WixrXtYt_1_14, + input [17:0] Wic_14, + input [17:0] bi_14, + input [17:0] WfxrXtYt_1_14, + input [17:0] Wfc_14, + input [17:0] bf_14, + input [17:0] WoxrXtYt_1_14, + input [17:0] Woc_14, + input [17:0] bo_14, + input [17:0] WcxrXtYt_1_14, + input [17:0] bc_14, + output [17:0] out_mt_14, + output [17:0] out_ct_14, + input [17:0] Ct_1_15, + input [17:0] WixrXtYt_1_15, + input [17:0] Wic_15, + input [17:0] bi_15, + input [17:0] WfxrXtYt_1_15, + input [17:0] Wfc_15, + input [17:0] bf_15, + input [17:0] WoxrXtYt_1_15, + input [17:0] Woc_15, + input [17:0] bo_15, + input [17:0] WcxrXtYt_1_15, + input [17:0] bc_15, + output [17:0] out_mt_15, + output [17:0] out_ct_15, + input [17:0] Ct_1_16, + input [17:0] WixrXtYt_1_16, + input [17:0] Wic_16, + input [17:0] bi_16, + input [17:0] WfxrXtYt_1_16, + input [17:0] Wfc_16, + input [17:0] bf_16, + input [17:0] WoxrXtYt_1_16, + input [17:0] Woc_16, + input [17:0] bo_16, + input [17:0] WcxrXtYt_1_16, + input [17:0] bc_16, + output [17:0] out_mt_16, + output [17:0] out_ct_16, + input [17:0] Ct_1_17, + input [17:0] WixrXtYt_1_17, + input [17:0] Wic_17, + input [17:0] bi_17, + input [17:0] WfxrXtYt_1_17, + input [17:0] Wfc_17, + input [17:0] bf_17, + input [17:0] WoxrXtYt_1_17, + input [17:0] Woc_17, + input [17:0] bo_17, + input [17:0] WcxrXtYt_1_17, + input [17:0] bc_17, + output [17:0] out_mt_17, + output [17:0] out_ct_17, + input [17:0] Ct_1_18, + input [17:0] WixrXtYt_1_18, + input [17:0] Wic_18, + input [17:0] bi_18, + input [17:0] WfxrXtYt_1_18, + input [17:0] Wfc_18, + input [17:0] bf_18, + input [17:0] WoxrXtYt_1_18, + input [17:0] Woc_18, + input [17:0] bo_18, + input [17:0] WcxrXtYt_1_18, + input [17:0] bc_18, + output [17:0] out_mt_18, + output [17:0] out_ct_18, + input [17:0] Ct_1_19, + input [17:0] WixrXtYt_1_19, + input [17:0] Wic_19, + input [17:0] bi_19, + input [17:0] WfxrXtYt_1_19, + input [17:0] Wfc_19, + input [17:0] bf_19, + input [17:0] WoxrXtYt_1_19, + input [17:0] Woc_19, + input [17:0] bo_19, + input [17:0] WcxrXtYt_1_19, + input [17:0] bc_19, + output [17:0] out_mt_19, + output [17:0] out_ct_19, + input [17:0] Ct_1_20, + input [17:0] WixrXtYt_1_20, + input [17:0] Wic_20, + input [17:0] bi_20, + input [17:0] WfxrXtYt_1_20, + input [17:0] Wfc_20, + input [17:0] bf_20, + input [17:0] WoxrXtYt_1_20, + input [17:0] Woc_20, + input [17:0] bo_20, + input [17:0] WcxrXtYt_1_20, + input [17:0] bc_20, + output [17:0] out_mt_20, + output [17:0] out_ct_20, + input [17:0] Ct_1_21, + input [17:0] WixrXtYt_1_21, + input [17:0] Wic_21, + input [17:0] bi_21, + input [17:0] WfxrXtYt_1_21, + input [17:0] Wfc_21, + input [17:0] bf_21, + input [17:0] WoxrXtYt_1_21, + input [17:0] Woc_21, + input [17:0] bo_21, + input [17:0] WcxrXtYt_1_21, + input [17:0] bc_21, + output [17:0] out_mt_21, + output [17:0] out_ct_21, + input [17:0] Ct_1_22, + input [17:0] WixrXtYt_1_22, + input [17:0] Wic_22, + input [17:0] bi_22, + input [17:0] WfxrXtYt_1_22, + input [17:0] Wfc_22, + input [17:0] bf_22, + input [17:0] WoxrXtYt_1_22, + input [17:0] Woc_22, + input [17:0] bo_22, + input [17:0] WcxrXtYt_1_22, + input [17:0] bc_22, + output [17:0] out_mt_22, + output [17:0] out_ct_22, + input [17:0] Ct_1_23, + input [17:0] WixrXtYt_1_23, + input [17:0] Wic_23, + input [17:0] bi_23, + input [17:0] WfxrXtYt_1_23, + input [17:0] Wfc_23, + input [17:0] bf_23, + input [17:0] WoxrXtYt_1_23, + input [17:0] Woc_23, + input [17:0] bo_23, + input [17:0] WcxrXtYt_1_23, + input [17:0] bc_23, + output [17:0] out_mt_23, + output [17:0] out_ct_23, + input [17:0] Ct_1_24, + input [17:0] WixrXtYt_1_24, + input [17:0] Wic_24, + input [17:0] bi_24, + input [17:0] WfxrXtYt_1_24, + input [17:0] Wfc_24, + input [17:0] bf_24, + input [17:0] WoxrXtYt_1_24, + input [17:0] Woc_24, + input [17:0] bo_24, + input [17:0] WcxrXtYt_1_24, + input [17:0] bc_24, + output [17:0] out_mt_24, + output [17:0] out_ct_24, + input [17:0] Ct_1_25, + input [17:0] WixrXtYt_1_25, + input [17:0] Wic_25, + input [17:0] bi_25, + input [17:0] WfxrXtYt_1_25, + input [17:0] Wfc_25, + input [17:0] bf_25, + input [17:0] WoxrXtYt_1_25, + input [17:0] Woc_25, + input [17:0] bo_25, + input [17:0] WcxrXtYt_1_25, + input [17:0] bc_25, + output [17:0] out_mt_25, + output [17:0] out_ct_25, + input [17:0] Ct_1_26, + input [17:0] WixrXtYt_1_26, + input [17:0] Wic_26, + input [17:0] bi_26, + input [17:0] WfxrXtYt_1_26, + input [17:0] Wfc_26, + input [17:0] bf_26, + input [17:0] WoxrXtYt_1_26, + input [17:0] Woc_26, + input [17:0] bo_26, + input [17:0] WcxrXtYt_1_26, + input [17:0] bc_26, + output [17:0] out_mt_26, + output [17:0] out_ct_26, + input [17:0] Ct_1_27, + input [17:0] WixrXtYt_1_27, + input [17:0] Wic_27, + input [17:0] bi_27, + input [17:0] WfxrXtYt_1_27, + input [17:0] Wfc_27, + input [17:0] bf_27, + input [17:0] WoxrXtYt_1_27, + input [17:0] Woc_27, + input [17:0] bo_27, + input [17:0] WcxrXtYt_1_27, + input [17:0] bc_27, + output [17:0] out_mt_27, + output [17:0] out_ct_27, + input [17:0] Ct_1_28, + input [17:0] WixrXtYt_1_28, + input [17:0] Wic_28, + input [17:0] bi_28, + input [17:0] WfxrXtYt_1_28, + input [17:0] Wfc_28, + input [17:0] bf_28, + input [17:0] WoxrXtYt_1_28, + input [17:0] Woc_28, + input [17:0] bo_28, + input [17:0] WcxrXtYt_1_28, + input [17:0] bc_28, + output [17:0] out_mt_28, + output [17:0] out_ct_28, + input [17:0] Ct_1_29, + input [17:0] WixrXtYt_1_29, + input [17:0] Wic_29, + input [17:0] bi_29, + input [17:0] WfxrXtYt_1_29, + input [17:0] Wfc_29, + input [17:0] bf_29, + input [17:0] WoxrXtYt_1_29, + input [17:0] Woc_29, + input [17:0] bo_29, + input [17:0] WcxrXtYt_1_29, + input [17:0] bc_29, + output [17:0] out_mt_29, + output [17:0] out_ct_29, + input [17:0] Ct_1_30, + input [17:0] WixrXtYt_1_30, + input [17:0] Wic_30, + input [17:0] bi_30, + input [17:0] WfxrXtYt_1_30, + input [17:0] Wfc_30, + input [17:0] bf_30, + input [17:0] WoxrXtYt_1_30, + input [17:0] Woc_30, + input [17:0] bo_30, + input [17:0] WcxrXtYt_1_30, + input [17:0] bc_30, + output [17:0] out_mt_30, + output [17:0] out_ct_30, + input [17:0] Ct_1_31, + input [17:0] WixrXtYt_1_31, + input [17:0] Wic_31, + input [17:0] bi_31, + input [17:0] WfxrXtYt_1_31, + input [17:0] Wfc_31, + input [17:0] bf_31, + input [17:0] WoxrXtYt_1_31, + input [17:0] Woc_31, + input [17:0] bo_31, + input [17:0] WcxrXtYt_1_31, + input [17:0] bc_31, + output [17:0] out_mt_31, + output [17:0] out_ct_31, + input [17:0] Ct_1_32, + input [17:0] WixrXtYt_1_32, + input [17:0] Wic_32, + input [17:0] bi_32, + input [17:0] WfxrXtYt_1_32, + input [17:0] Wfc_32, + input [17:0] bf_32, + input [17:0] WoxrXtYt_1_32, + input [17:0] Woc_32, + input [17:0] bo_32, + input [17:0] WcxrXtYt_1_32, + input [17:0] bc_32, + output [17:0] out_mt_32, + output [17:0] out_ct_32, + input [17:0] Ct_1_33, + input [17:0] WixrXtYt_1_33, + input [17:0] Wic_33, + input [17:0] bi_33, + input [17:0] WfxrXtYt_1_33, + input [17:0] Wfc_33, + input [17:0] bf_33, + input [17:0] WoxrXtYt_1_33, + input [17:0] Woc_33, + input [17:0] bo_33, + input [17:0] WcxrXtYt_1_33, + input [17:0] bc_33, + output [17:0] out_mt_33, + output [17:0] out_ct_33, + input [17:0] Ct_1_34, + input [17:0] WixrXtYt_1_34, + input [17:0] Wic_34, + input [17:0] bi_34, + input [17:0] WfxrXtYt_1_34, + input [17:0] Wfc_34, + input [17:0] bf_34, + input [17:0] WoxrXtYt_1_34, + input [17:0] Woc_34, + input [17:0] bo_34, + input [17:0] WcxrXtYt_1_34, + input [17:0] bc_34, + output [17:0] out_mt_34, + output [17:0] out_ct_34, + input [17:0] Ct_1_35, + input [17:0] WixrXtYt_1_35, + input [17:0] Wic_35, + input [17:0] bi_35, + input [17:0] WfxrXtYt_1_35, + input [17:0] Wfc_35, + input [17:0] bf_35, + input [17:0] WoxrXtYt_1_35, + input [17:0] Woc_35, + input [17:0] bo_35, + input [17:0] WcxrXtYt_1_35, + input [17:0] bc_35, + output [17:0] out_mt_35, + output [17:0] out_ct_35, + input [17:0] Ct_1_36, + input [17:0] WixrXtYt_1_36, + input [17:0] Wic_36, + input [17:0] bi_36, + input [17:0] WfxrXtYt_1_36, + input [17:0] Wfc_36, + input [17:0] bf_36, + input [17:0] WoxrXtYt_1_36, + input [17:0] Woc_36, + input [17:0] bo_36, + input [17:0] WcxrXtYt_1_36, + input [17:0] bc_36, + output [17:0] out_mt_36, + output [17:0] out_ct_36, + input [17:0] Ct_1_37, + input [17:0] WixrXtYt_1_37, + input [17:0] Wic_37, + input [17:0] bi_37, + input [17:0] WfxrXtYt_1_37, + input [17:0] Wfc_37, + input [17:0] bf_37, + input [17:0] WoxrXtYt_1_37, + input [17:0] Woc_37, + input [17:0] bo_37, + input [17:0] WcxrXtYt_1_37, + input [17:0] bc_37, + output [17:0] out_mt_37, + output [17:0] out_ct_37, + input [17:0] Ct_1_38, + input [17:0] WixrXtYt_1_38, + input [17:0] Wic_38, + input [17:0] bi_38, + input [17:0] WfxrXtYt_1_38, + input [17:0] Wfc_38, + input [17:0] bf_38, + input [17:0] WoxrXtYt_1_38, + input [17:0] Woc_38, + input [17:0] bo_38, + input [17:0] WcxrXtYt_1_38, + input [17:0] bc_38, + output [17:0] out_mt_38, + output [17:0] out_ct_38, + input [17:0] Ct_1_39, + input [17:0] WixrXtYt_1_39, + input [17:0] Wic_39, + input [17:0] bi_39, + input [17:0] WfxrXtYt_1_39, + input [17:0] Wfc_39, + input [17:0] bf_39, + input [17:0] WoxrXtYt_1_39, + input [17:0] Woc_39, + input [17:0] bo_39, + input [17:0] WcxrXtYt_1_39, + input [17:0] bc_39, + output [17:0] out_mt_39, + output [17:0] out_ct_39, + input [17:0] Ct_1_40, + input [17:0] WixrXtYt_1_40, + input [17:0] Wic_40, + input [17:0] bi_40, + input [17:0] WfxrXtYt_1_40, + input [17:0] Wfc_40, + input [17:0] bf_40, + input [17:0] WoxrXtYt_1_40, + input [17:0] Woc_40, + input [17:0] bo_40, + input [17:0] WcxrXtYt_1_40, + input [17:0] bc_40, + output [17:0] out_mt_40, + output [17:0] out_ct_40, + input [17:0] Ct_1_41, + input [17:0] WixrXtYt_1_41, + input [17:0] Wic_41, + input [17:0] bi_41, + input [17:0] WfxrXtYt_1_41, + input [17:0] Wfc_41, + input [17:0] bf_41, + input [17:0] WoxrXtYt_1_41, + input [17:0] Woc_41, + input [17:0] bo_41, + input [17:0] WcxrXtYt_1_41, + input [17:0] bc_41, + output [17:0] out_mt_41, + output [17:0] out_ct_41, + input [17:0] Ct_1_42, + input [17:0] WixrXtYt_1_42, + input [17:0] Wic_42, + input [17:0] bi_42, + input [17:0] WfxrXtYt_1_42, + input [17:0] Wfc_42, + input [17:0] bf_42, + input [17:0] WoxrXtYt_1_42, + input [17:0] Woc_42, + input [17:0] bo_42, + input [17:0] WcxrXtYt_1_42, + input [17:0] bc_42, + output [17:0] out_mt_42, + output [17:0] out_ct_42, + input [17:0] Ct_1_43, + input [17:0] WixrXtYt_1_43, + input [17:0] Wic_43, + input [17:0] bi_43, + input [17:0] WfxrXtYt_1_43, + input [17:0] Wfc_43, + input [17:0] bf_43, + input [17:0] WoxrXtYt_1_43, + input [17:0] Woc_43, + input [17:0] bo_43, + input [17:0] WcxrXtYt_1_43, + input [17:0] bc_43, + output [17:0] out_mt_43, + output [17:0] out_ct_43, + input [17:0] Ct_1_44, + input [17:0] WixrXtYt_1_44, + input [17:0] Wic_44, + input [17:0] bi_44, + input [17:0] WfxrXtYt_1_44, + input [17:0] Wfc_44, + input [17:0] bf_44, + input [17:0] WoxrXtYt_1_44, + input [17:0] Woc_44, + input [17:0] bo_44, + input [17:0] WcxrXtYt_1_44, + input [17:0] bc_44, + output [17:0] out_mt_44, + output [17:0] out_ct_44, + input [17:0] Ct_1_45, + input [17:0] WixrXtYt_1_45, + input [17:0] Wic_45, + input [17:0] bi_45, + input [17:0] WfxrXtYt_1_45, + input [17:0] Wfc_45, + input [17:0] bf_45, + input [17:0] WoxrXtYt_1_45, + input [17:0] Woc_45, + input [17:0] bo_45, + input [17:0] WcxrXtYt_1_45, + input [17:0] bc_45, + output [17:0] out_mt_45, + output [17:0] out_ct_45, + input [17:0] Ct_1_46, + input [17:0] WixrXtYt_1_46, + input [17:0] Wic_46, + input [17:0] bi_46, + input [17:0] WfxrXtYt_1_46, + input [17:0] Wfc_46, + input [17:0] bf_46, + input [17:0] WoxrXtYt_1_46, + input [17:0] Woc_46, + input [17:0] bo_46, + input [17:0] WcxrXtYt_1_46, + input [17:0] bc_46, + output [17:0] out_mt_46, + output [17:0] out_ct_46, + input [17:0] Ct_1_47, + input [17:0] WixrXtYt_1_47, + input [17:0] Wic_47, + input [17:0] bi_47, + input [17:0] WfxrXtYt_1_47, + input [17:0] Wfc_47, + input [17:0] bf_47, + input [17:0] WoxrXtYt_1_47, + input [17:0] Woc_47, + input [17:0] bo_47, + input [17:0] WcxrXtYt_1_47, + input [17:0] bc_47, + output [17:0] out_mt_47, + output [17:0] out_ct_47, + output o_valid, + output o_ready +); + +reg reg_i_valid, reg_o_valid; +reg [17:0] reg_Ct_1_0; +reg [17:0] reg_WixrXtYt_1_0; +reg [17:0] reg_Wic_0; +reg [17:0] reg_bi_0; +reg [17:0] reg_WfxrXtYt_1_0; +reg [17:0] reg_Wfc_0; +reg [17:0] reg_bf_0; +reg [17:0] reg_WoxrXtYt_1_0; +reg [17:0] reg_Woc_0; +reg [17:0] reg_bo_0; +reg [17:0] reg_WcxrXtYt_1_0; +reg [17:0] reg_bc_0; +reg [17:0] reg_out_mt_0; +reg [17:0] reg_out_ct_0; +reg [17:0] reg_Ct_1_1; +reg [17:0] reg_WixrXtYt_1_1; +reg [17:0] reg_Wic_1; +reg [17:0] reg_bi_1; +reg [17:0] reg_WfxrXtYt_1_1; +reg [17:0] reg_Wfc_1; +reg [17:0] reg_bf_1; +reg [17:0] reg_WoxrXtYt_1_1; +reg [17:0] reg_Woc_1; +reg [17:0] reg_bo_1; +reg [17:0] reg_WcxrXtYt_1_1; +reg [17:0] reg_bc_1; +reg [17:0] reg_out_mt_1; +reg [17:0] reg_out_ct_1; +reg [17:0] reg_Ct_1_2; +reg [17:0] reg_WixrXtYt_1_2; +reg [17:0] reg_Wic_2; +reg [17:0] reg_bi_2; +reg [17:0] reg_WfxrXtYt_1_2; +reg [17:0] reg_Wfc_2; +reg [17:0] reg_bf_2; +reg [17:0] reg_WoxrXtYt_1_2; +reg [17:0] reg_Woc_2; +reg [17:0] reg_bo_2; +reg [17:0] reg_WcxrXtYt_1_2; +reg [17:0] reg_bc_2; +reg [17:0] reg_out_mt_2; +reg [17:0] reg_out_ct_2; +reg [17:0] reg_Ct_1_3; +reg [17:0] reg_WixrXtYt_1_3; +reg [17:0] reg_Wic_3; +reg [17:0] reg_bi_3; +reg [17:0] reg_WfxrXtYt_1_3; +reg [17:0] reg_Wfc_3; +reg [17:0] reg_bf_3; +reg [17:0] reg_WoxrXtYt_1_3; +reg [17:0] reg_Woc_3; +reg [17:0] reg_bo_3; +reg [17:0] reg_WcxrXtYt_1_3; +reg [17:0] reg_bc_3; +reg [17:0] reg_out_mt_3; +reg [17:0] reg_out_ct_3; +reg [17:0] reg_Ct_1_4; +reg [17:0] reg_WixrXtYt_1_4; +reg [17:0] reg_Wic_4; +reg [17:0] reg_bi_4; +reg [17:0] reg_WfxrXtYt_1_4; +reg [17:0] reg_Wfc_4; +reg [17:0] reg_bf_4; +reg [17:0] reg_WoxrXtYt_1_4; +reg [17:0] reg_Woc_4; +reg [17:0] reg_bo_4; +reg [17:0] reg_WcxrXtYt_1_4; +reg [17:0] reg_bc_4; +reg [17:0] reg_out_mt_4; +reg [17:0] reg_out_ct_4; +reg [17:0] reg_Ct_1_5; +reg [17:0] reg_WixrXtYt_1_5; +reg [17:0] reg_Wic_5; +reg [17:0] reg_bi_5; +reg [17:0] reg_WfxrXtYt_1_5; +reg [17:0] reg_Wfc_5; +reg [17:0] reg_bf_5; +reg [17:0] reg_WoxrXtYt_1_5; +reg [17:0] reg_Woc_5; +reg [17:0] reg_bo_5; +reg [17:0] reg_WcxrXtYt_1_5; +reg [17:0] reg_bc_5; +reg [17:0] reg_out_mt_5; +reg [17:0] reg_out_ct_5; +reg [17:0] reg_Ct_1_6; +reg [17:0] reg_WixrXtYt_1_6; +reg [17:0] reg_Wic_6; +reg [17:0] reg_bi_6; +reg [17:0] reg_WfxrXtYt_1_6; +reg [17:0] reg_Wfc_6; +reg [17:0] reg_bf_6; +reg [17:0] reg_WoxrXtYt_1_6; +reg [17:0] reg_Woc_6; +reg [17:0] reg_bo_6; +reg [17:0] reg_WcxrXtYt_1_6; +reg [17:0] reg_bc_6; +reg [17:0] reg_out_mt_6; +reg [17:0] reg_out_ct_6; +reg [17:0] reg_Ct_1_7; +reg [17:0] reg_WixrXtYt_1_7; +reg [17:0] reg_Wic_7; +reg [17:0] reg_bi_7; +reg [17:0] reg_WfxrXtYt_1_7; +reg [17:0] reg_Wfc_7; +reg [17:0] reg_bf_7; +reg [17:0] reg_WoxrXtYt_1_7; +reg [17:0] reg_Woc_7; +reg [17:0] reg_bo_7; +reg [17:0] reg_WcxrXtYt_1_7; +reg [17:0] reg_bc_7; +reg [17:0] reg_out_mt_7; +reg [17:0] reg_out_ct_7; +reg [17:0] reg_Ct_1_8; +reg [17:0] reg_WixrXtYt_1_8; +reg [17:0] reg_Wic_8; +reg [17:0] reg_bi_8; +reg [17:0] reg_WfxrXtYt_1_8; +reg [17:0] reg_Wfc_8; +reg [17:0] reg_bf_8; +reg [17:0] reg_WoxrXtYt_1_8; +reg [17:0] reg_Woc_8; +reg [17:0] reg_bo_8; +reg [17:0] reg_WcxrXtYt_1_8; +reg [17:0] reg_bc_8; +reg [17:0] reg_out_mt_8; +reg [17:0] reg_out_ct_8; +reg [17:0] reg_Ct_1_9; +reg [17:0] reg_WixrXtYt_1_9; +reg [17:0] reg_Wic_9; +reg [17:0] reg_bi_9; +reg [17:0] reg_WfxrXtYt_1_9; +reg [17:0] reg_Wfc_9; +reg [17:0] reg_bf_9; +reg [17:0] reg_WoxrXtYt_1_9; +reg [17:0] reg_Woc_9; +reg [17:0] reg_bo_9; +reg [17:0] reg_WcxrXtYt_1_9; +reg [17:0] reg_bc_9; +reg [17:0] reg_out_mt_9; +reg [17:0] reg_out_ct_9; +reg [17:0] reg_Ct_1_10; +reg [17:0] reg_WixrXtYt_1_10; +reg [17:0] reg_Wic_10; +reg [17:0] reg_bi_10; +reg [17:0] reg_WfxrXtYt_1_10; +reg [17:0] reg_Wfc_10; +reg [17:0] reg_bf_10; +reg [17:0] reg_WoxrXtYt_1_10; +reg [17:0] reg_Woc_10; +reg [17:0] reg_bo_10; +reg [17:0] reg_WcxrXtYt_1_10; +reg [17:0] reg_bc_10; +reg [17:0] reg_out_mt_10; +reg [17:0] reg_out_ct_10; +reg [17:0] reg_Ct_1_11; +reg [17:0] reg_WixrXtYt_1_11; +reg [17:0] reg_Wic_11; +reg [17:0] reg_bi_11; +reg [17:0] reg_WfxrXtYt_1_11; +reg [17:0] reg_Wfc_11; +reg [17:0] reg_bf_11; +reg [17:0] reg_WoxrXtYt_1_11; +reg [17:0] reg_Woc_11; +reg [17:0] reg_bo_11; +reg [17:0] reg_WcxrXtYt_1_11; +reg [17:0] reg_bc_11; +reg [17:0] reg_out_mt_11; +reg [17:0] reg_out_ct_11; +reg [17:0] reg_Ct_1_12; +reg [17:0] reg_WixrXtYt_1_12; +reg [17:0] reg_Wic_12; +reg [17:0] reg_bi_12; +reg [17:0] reg_WfxrXtYt_1_12; +reg [17:0] reg_Wfc_12; +reg [17:0] reg_bf_12; +reg [17:0] reg_WoxrXtYt_1_12; +reg [17:0] reg_Woc_12; +reg [17:0] reg_bo_12; +reg [17:0] reg_WcxrXtYt_1_12; +reg [17:0] reg_bc_12; +reg [17:0] reg_out_mt_12; +reg [17:0] reg_out_ct_12; +reg [17:0] reg_Ct_1_13; +reg [17:0] reg_WixrXtYt_1_13; +reg [17:0] reg_Wic_13; +reg [17:0] reg_bi_13; +reg [17:0] reg_WfxrXtYt_1_13; +reg [17:0] reg_Wfc_13; +reg [17:0] reg_bf_13; +reg [17:0] reg_WoxrXtYt_1_13; +reg [17:0] reg_Woc_13; +reg [17:0] reg_bo_13; +reg [17:0] reg_WcxrXtYt_1_13; +reg [17:0] reg_bc_13; +reg [17:0] reg_out_mt_13; +reg [17:0] reg_out_ct_13; +reg [17:0] reg_Ct_1_14; +reg [17:0] reg_WixrXtYt_1_14; +reg [17:0] reg_Wic_14; +reg [17:0] reg_bi_14; +reg [17:0] reg_WfxrXtYt_1_14; +reg [17:0] reg_Wfc_14; +reg [17:0] reg_bf_14; +reg [17:0] reg_WoxrXtYt_1_14; +reg [17:0] reg_Woc_14; +reg [17:0] reg_bo_14; +reg [17:0] reg_WcxrXtYt_1_14; +reg [17:0] reg_bc_14; +reg [17:0] reg_out_mt_14; +reg [17:0] reg_out_ct_14; +reg [17:0] reg_Ct_1_15; +reg [17:0] reg_WixrXtYt_1_15; +reg [17:0] reg_Wic_15; +reg [17:0] reg_bi_15; +reg [17:0] reg_WfxrXtYt_1_15; +reg [17:0] reg_Wfc_15; +reg [17:0] reg_bf_15; +reg [17:0] reg_WoxrXtYt_1_15; +reg [17:0] reg_Woc_15; +reg [17:0] reg_bo_15; +reg [17:0] reg_WcxrXtYt_1_15; +reg [17:0] reg_bc_15; +reg [17:0] reg_out_mt_15; +reg [17:0] reg_out_ct_15; +reg [17:0] reg_Ct_1_16; +reg [17:0] reg_WixrXtYt_1_16; +reg [17:0] reg_Wic_16; +reg [17:0] reg_bi_16; +reg [17:0] reg_WfxrXtYt_1_16; +reg [17:0] reg_Wfc_16; +reg [17:0] reg_bf_16; +reg [17:0] reg_WoxrXtYt_1_16; +reg [17:0] reg_Woc_16; +reg [17:0] reg_bo_16; +reg [17:0] reg_WcxrXtYt_1_16; +reg [17:0] reg_bc_16; +reg [17:0] reg_out_mt_16; +reg [17:0] reg_out_ct_16; +reg [17:0] reg_Ct_1_17; +reg [17:0] reg_WixrXtYt_1_17; +reg [17:0] reg_Wic_17; +reg [17:0] reg_bi_17; +reg [17:0] reg_WfxrXtYt_1_17; +reg [17:0] reg_Wfc_17; +reg [17:0] reg_bf_17; +reg [17:0] reg_WoxrXtYt_1_17; +reg [17:0] reg_Woc_17; +reg [17:0] reg_bo_17; +reg [17:0] reg_WcxrXtYt_1_17; +reg [17:0] reg_bc_17; +reg [17:0] reg_out_mt_17; +reg [17:0] reg_out_ct_17; +reg [17:0] reg_Ct_1_18; +reg [17:0] reg_WixrXtYt_1_18; +reg [17:0] reg_Wic_18; +reg [17:0] reg_bi_18; +reg [17:0] reg_WfxrXtYt_1_18; +reg [17:0] reg_Wfc_18; +reg [17:0] reg_bf_18; +reg [17:0] reg_WoxrXtYt_1_18; +reg [17:0] reg_Woc_18; +reg [17:0] reg_bo_18; +reg [17:0] reg_WcxrXtYt_1_18; +reg [17:0] reg_bc_18; +reg [17:0] reg_out_mt_18; +reg [17:0] reg_out_ct_18; +reg [17:0] reg_Ct_1_19; +reg [17:0] reg_WixrXtYt_1_19; +reg [17:0] reg_Wic_19; +reg [17:0] reg_bi_19; +reg [17:0] reg_WfxrXtYt_1_19; +reg [17:0] reg_Wfc_19; +reg [17:0] reg_bf_19; +reg [17:0] reg_WoxrXtYt_1_19; +reg [17:0] reg_Woc_19; +reg [17:0] reg_bo_19; +reg [17:0] reg_WcxrXtYt_1_19; +reg [17:0] reg_bc_19; +reg [17:0] reg_out_mt_19; +reg [17:0] reg_out_ct_19; +reg [17:0] reg_Ct_1_20; +reg [17:0] reg_WixrXtYt_1_20; +reg [17:0] reg_Wic_20; +reg [17:0] reg_bi_20; +reg [17:0] reg_WfxrXtYt_1_20; +reg [17:0] reg_Wfc_20; +reg [17:0] reg_bf_20; +reg [17:0] reg_WoxrXtYt_1_20; +reg [17:0] reg_Woc_20; +reg [17:0] reg_bo_20; +reg [17:0] reg_WcxrXtYt_1_20; +reg [17:0] reg_bc_20; +reg [17:0] reg_out_mt_20; +reg [17:0] reg_out_ct_20; +reg [17:0] reg_Ct_1_21; +reg [17:0] reg_WixrXtYt_1_21; +reg [17:0] reg_Wic_21; +reg [17:0] reg_bi_21; +reg [17:0] reg_WfxrXtYt_1_21; +reg [17:0] reg_Wfc_21; +reg [17:0] reg_bf_21; +reg [17:0] reg_WoxrXtYt_1_21; +reg [17:0] reg_Woc_21; +reg [17:0] reg_bo_21; +reg [17:0] reg_WcxrXtYt_1_21; +reg [17:0] reg_bc_21; +reg [17:0] reg_out_mt_21; +reg [17:0] reg_out_ct_21; +reg [17:0] reg_Ct_1_22; +reg [17:0] reg_WixrXtYt_1_22; +reg [17:0] reg_Wic_22; +reg [17:0] reg_bi_22; +reg [17:0] reg_WfxrXtYt_1_22; +reg [17:0] reg_Wfc_22; +reg [17:0] reg_bf_22; +reg [17:0] reg_WoxrXtYt_1_22; +reg [17:0] reg_Woc_22; +reg [17:0] reg_bo_22; +reg [17:0] reg_WcxrXtYt_1_22; +reg [17:0] reg_bc_22; +reg [17:0] reg_out_mt_22; +reg [17:0] reg_out_ct_22; +reg [17:0] reg_Ct_1_23; +reg [17:0] reg_WixrXtYt_1_23; +reg [17:0] reg_Wic_23; +reg [17:0] reg_bi_23; +reg [17:0] reg_WfxrXtYt_1_23; +reg [17:0] reg_Wfc_23; +reg [17:0] reg_bf_23; +reg [17:0] reg_WoxrXtYt_1_23; +reg [17:0] reg_Woc_23; +reg [17:0] reg_bo_23; +reg [17:0] reg_WcxrXtYt_1_23; +reg [17:0] reg_bc_23; +reg [17:0] reg_out_mt_23; +reg [17:0] reg_out_ct_23; +reg [17:0] reg_Ct_1_24; +reg [17:0] reg_WixrXtYt_1_24; +reg [17:0] reg_Wic_24; +reg [17:0] reg_bi_24; +reg [17:0] reg_WfxrXtYt_1_24; +reg [17:0] reg_Wfc_24; +reg [17:0] reg_bf_24; +reg [17:0] reg_WoxrXtYt_1_24; +reg [17:0] reg_Woc_24; +reg [17:0] reg_bo_24; +reg [17:0] reg_WcxrXtYt_1_24; +reg [17:0] reg_bc_24; +reg [17:0] reg_out_mt_24; +reg [17:0] reg_out_ct_24; +reg [17:0] reg_Ct_1_25; +reg [17:0] reg_WixrXtYt_1_25; +reg [17:0] reg_Wic_25; +reg [17:0] reg_bi_25; +reg [17:0] reg_WfxrXtYt_1_25; +reg [17:0] reg_Wfc_25; +reg [17:0] reg_bf_25; +reg [17:0] reg_WoxrXtYt_1_25; +reg [17:0] reg_Woc_25; +reg [17:0] reg_bo_25; +reg [17:0] reg_WcxrXtYt_1_25; +reg [17:0] reg_bc_25; +reg [17:0] reg_out_mt_25; +reg [17:0] reg_out_ct_25; +reg [17:0] reg_Ct_1_26; +reg [17:0] reg_WixrXtYt_1_26; +reg [17:0] reg_Wic_26; +reg [17:0] reg_bi_26; +reg [17:0] reg_WfxrXtYt_1_26; +reg [17:0] reg_Wfc_26; +reg [17:0] reg_bf_26; +reg [17:0] reg_WoxrXtYt_1_26; +reg [17:0] reg_Woc_26; +reg [17:0] reg_bo_26; +reg [17:0] reg_WcxrXtYt_1_26; +reg [17:0] reg_bc_26; +reg [17:0] reg_out_mt_26; +reg [17:0] reg_out_ct_26; +reg [17:0] reg_Ct_1_27; +reg [17:0] reg_WixrXtYt_1_27; +reg [17:0] reg_Wic_27; +reg [17:0] reg_bi_27; +reg [17:0] reg_WfxrXtYt_1_27; +reg [17:0] reg_Wfc_27; +reg [17:0] reg_bf_27; +reg [17:0] reg_WoxrXtYt_1_27; +reg [17:0] reg_Woc_27; +reg [17:0] reg_bo_27; +reg [17:0] reg_WcxrXtYt_1_27; +reg [17:0] reg_bc_27; +reg [17:0] reg_out_mt_27; +reg [17:0] reg_out_ct_27; +reg [17:0] reg_Ct_1_28; +reg [17:0] reg_WixrXtYt_1_28; +reg [17:0] reg_Wic_28; +reg [17:0] reg_bi_28; +reg [17:0] reg_WfxrXtYt_1_28; +reg [17:0] reg_Wfc_28; +reg [17:0] reg_bf_28; +reg [17:0] reg_WoxrXtYt_1_28; +reg [17:0] reg_Woc_28; +reg [17:0] reg_bo_28; +reg [17:0] reg_WcxrXtYt_1_28; +reg [17:0] reg_bc_28; +reg [17:0] reg_out_mt_28; +reg [17:0] reg_out_ct_28; +reg [17:0] reg_Ct_1_29; +reg [17:0] reg_WixrXtYt_1_29; +reg [17:0] reg_Wic_29; +reg [17:0] reg_bi_29; +reg [17:0] reg_WfxrXtYt_1_29; +reg [17:0] reg_Wfc_29; +reg [17:0] reg_bf_29; +reg [17:0] reg_WoxrXtYt_1_29; +reg [17:0] reg_Woc_29; +reg [17:0] reg_bo_29; +reg [17:0] reg_WcxrXtYt_1_29; +reg [17:0] reg_bc_29; +reg [17:0] reg_out_mt_29; +reg [17:0] reg_out_ct_29; +reg [17:0] reg_Ct_1_30; +reg [17:0] reg_WixrXtYt_1_30; +reg [17:0] reg_Wic_30; +reg [17:0] reg_bi_30; +reg [17:0] reg_WfxrXtYt_1_30; +reg [17:0] reg_Wfc_30; +reg [17:0] reg_bf_30; +reg [17:0] reg_WoxrXtYt_1_30; +reg [17:0] reg_Woc_30; +reg [17:0] reg_bo_30; +reg [17:0] reg_WcxrXtYt_1_30; +reg [17:0] reg_bc_30; +reg [17:0] reg_out_mt_30; +reg [17:0] reg_out_ct_30; +reg [17:0] reg_Ct_1_31; +reg [17:0] reg_WixrXtYt_1_31; +reg [17:0] reg_Wic_31; +reg [17:0] reg_bi_31; +reg [17:0] reg_WfxrXtYt_1_31; +reg [17:0] reg_Wfc_31; +reg [17:0] reg_bf_31; +reg [17:0] reg_WoxrXtYt_1_31; +reg [17:0] reg_Woc_31; +reg [17:0] reg_bo_31; +reg [17:0] reg_WcxrXtYt_1_31; +reg [17:0] reg_bc_31; +reg [17:0] reg_out_mt_31; +reg [17:0] reg_out_ct_31; +reg [17:0] reg_Ct_1_32; +reg [17:0] reg_WixrXtYt_1_32; +reg [17:0] reg_Wic_32; +reg [17:0] reg_bi_32; +reg [17:0] reg_WfxrXtYt_1_32; +reg [17:0] reg_Wfc_32; +reg [17:0] reg_bf_32; +reg [17:0] reg_WoxrXtYt_1_32; +reg [17:0] reg_Woc_32; +reg [17:0] reg_bo_32; +reg [17:0] reg_WcxrXtYt_1_32; +reg [17:0] reg_bc_32; +reg [17:0] reg_out_mt_32; +reg [17:0] reg_out_ct_32; +reg [17:0] reg_Ct_1_33; +reg [17:0] reg_WixrXtYt_1_33; +reg [17:0] reg_Wic_33; +reg [17:0] reg_bi_33; +reg [17:0] reg_WfxrXtYt_1_33; +reg [17:0] reg_Wfc_33; +reg [17:0] reg_bf_33; +reg [17:0] reg_WoxrXtYt_1_33; +reg [17:0] reg_Woc_33; +reg [17:0] reg_bo_33; +reg [17:0] reg_WcxrXtYt_1_33; +reg [17:0] reg_bc_33; +reg [17:0] reg_out_mt_33; +reg [17:0] reg_out_ct_33; +reg [17:0] reg_Ct_1_34; +reg [17:0] reg_WixrXtYt_1_34; +reg [17:0] reg_Wic_34; +reg [17:0] reg_bi_34; +reg [17:0] reg_WfxrXtYt_1_34; +reg [17:0] reg_Wfc_34; +reg [17:0] reg_bf_34; +reg [17:0] reg_WoxrXtYt_1_34; +reg [17:0] reg_Woc_34; +reg [17:0] reg_bo_34; +reg [17:0] reg_WcxrXtYt_1_34; +reg [17:0] reg_bc_34; +reg [17:0] reg_out_mt_34; +reg [17:0] reg_out_ct_34; +reg [17:0] reg_Ct_1_35; +reg [17:0] reg_WixrXtYt_1_35; +reg [17:0] reg_Wic_35; +reg [17:0] reg_bi_35; +reg [17:0] reg_WfxrXtYt_1_35; +reg [17:0] reg_Wfc_35; +reg [17:0] reg_bf_35; +reg [17:0] reg_WoxrXtYt_1_35; +reg [17:0] reg_Woc_35; +reg [17:0] reg_bo_35; +reg [17:0] reg_WcxrXtYt_1_35; +reg [17:0] reg_bc_35; +reg [17:0] reg_out_mt_35; +reg [17:0] reg_out_ct_35; +reg [17:0] reg_Ct_1_36; +reg [17:0] reg_WixrXtYt_1_36; +reg [17:0] reg_Wic_36; +reg [17:0] reg_bi_36; +reg [17:0] reg_WfxrXtYt_1_36; +reg [17:0] reg_Wfc_36; +reg [17:0] reg_bf_36; +reg [17:0] reg_WoxrXtYt_1_36; +reg [17:0] reg_Woc_36; +reg [17:0] reg_bo_36; +reg [17:0] reg_WcxrXtYt_1_36; +reg [17:0] reg_bc_36; +reg [17:0] reg_out_mt_36; +reg [17:0] reg_out_ct_36; +reg [17:0] reg_Ct_1_37; +reg [17:0] reg_WixrXtYt_1_37; +reg [17:0] reg_Wic_37; +reg [17:0] reg_bi_37; +reg [17:0] reg_WfxrXtYt_1_37; +reg [17:0] reg_Wfc_37; +reg [17:0] reg_bf_37; +reg [17:0] reg_WoxrXtYt_1_37; +reg [17:0] reg_Woc_37; +reg [17:0] reg_bo_37; +reg [17:0] reg_WcxrXtYt_1_37; +reg [17:0] reg_bc_37; +reg [17:0] reg_out_mt_37; +reg [17:0] reg_out_ct_37; +reg [17:0] reg_Ct_1_38; +reg [17:0] reg_WixrXtYt_1_38; +reg [17:0] reg_Wic_38; +reg [17:0] reg_bi_38; +reg [17:0] reg_WfxrXtYt_1_38; +reg [17:0] reg_Wfc_38; +reg [17:0] reg_bf_38; +reg [17:0] reg_WoxrXtYt_1_38; +reg [17:0] reg_Woc_38; +reg [17:0] reg_bo_38; +reg [17:0] reg_WcxrXtYt_1_38; +reg [17:0] reg_bc_38; +reg [17:0] reg_out_mt_38; +reg [17:0] reg_out_ct_38; +reg [17:0] reg_Ct_1_39; +reg [17:0] reg_WixrXtYt_1_39; +reg [17:0] reg_Wic_39; +reg [17:0] reg_bi_39; +reg [17:0] reg_WfxrXtYt_1_39; +reg [17:0] reg_Wfc_39; +reg [17:0] reg_bf_39; +reg [17:0] reg_WoxrXtYt_1_39; +reg [17:0] reg_Woc_39; +reg [17:0] reg_bo_39; +reg [17:0] reg_WcxrXtYt_1_39; +reg [17:0] reg_bc_39; +reg [17:0] reg_out_mt_39; +reg [17:0] reg_out_ct_39; +reg [17:0] reg_Ct_1_40; +reg [17:0] reg_WixrXtYt_1_40; +reg [17:0] reg_Wic_40; +reg [17:0] reg_bi_40; +reg [17:0] reg_WfxrXtYt_1_40; +reg [17:0] reg_Wfc_40; +reg [17:0] reg_bf_40; +reg [17:0] reg_WoxrXtYt_1_40; +reg [17:0] reg_Woc_40; +reg [17:0] reg_bo_40; +reg [17:0] reg_WcxrXtYt_1_40; +reg [17:0] reg_bc_40; +reg [17:0] reg_out_mt_40; +reg [17:0] reg_out_ct_40; +reg [17:0] reg_Ct_1_41; +reg [17:0] reg_WixrXtYt_1_41; +reg [17:0] reg_Wic_41; +reg [17:0] reg_bi_41; +reg [17:0] reg_WfxrXtYt_1_41; +reg [17:0] reg_Wfc_41; +reg [17:0] reg_bf_41; +reg [17:0] reg_WoxrXtYt_1_41; +reg [17:0] reg_Woc_41; +reg [17:0] reg_bo_41; +reg [17:0] reg_WcxrXtYt_1_41; +reg [17:0] reg_bc_41; +reg [17:0] reg_out_mt_41; +reg [17:0] reg_out_ct_41; +reg [17:0] reg_Ct_1_42; +reg [17:0] reg_WixrXtYt_1_42; +reg [17:0] reg_Wic_42; +reg [17:0] reg_bi_42; +reg [17:0] reg_WfxrXtYt_1_42; +reg [17:0] reg_Wfc_42; +reg [17:0] reg_bf_42; +reg [17:0] reg_WoxrXtYt_1_42; +reg [17:0] reg_Woc_42; +reg [17:0] reg_bo_42; +reg [17:0] reg_WcxrXtYt_1_42; +reg [17:0] reg_bc_42; +reg [17:0] reg_out_mt_42; +reg [17:0] reg_out_ct_42; +reg [17:0] reg_Ct_1_43; +reg [17:0] reg_WixrXtYt_1_43; +reg [17:0] reg_Wic_43; +reg [17:0] reg_bi_43; +reg [17:0] reg_WfxrXtYt_1_43; +reg [17:0] reg_Wfc_43; +reg [17:0] reg_bf_43; +reg [17:0] reg_WoxrXtYt_1_43; +reg [17:0] reg_Woc_43; +reg [17:0] reg_bo_43; +reg [17:0] reg_WcxrXtYt_1_43; +reg [17:0] reg_bc_43; +reg [17:0] reg_out_mt_43; +reg [17:0] reg_out_ct_43; +reg [17:0] reg_Ct_1_44; +reg [17:0] reg_WixrXtYt_1_44; +reg [17:0] reg_Wic_44; +reg [17:0] reg_bi_44; +reg [17:0] reg_WfxrXtYt_1_44; +reg [17:0] reg_Wfc_44; +reg [17:0] reg_bf_44; +reg [17:0] reg_WoxrXtYt_1_44; +reg [17:0] reg_Woc_44; +reg [17:0] reg_bo_44; +reg [17:0] reg_WcxrXtYt_1_44; +reg [17:0] reg_bc_44; +reg [17:0] reg_out_mt_44; +reg [17:0] reg_out_ct_44; +reg [17:0] reg_Ct_1_45; +reg [17:0] reg_WixrXtYt_1_45; +reg [17:0] reg_Wic_45; +reg [17:0] reg_bi_45; +reg [17:0] reg_WfxrXtYt_1_45; +reg [17:0] reg_Wfc_45; +reg [17:0] reg_bf_45; +reg [17:0] reg_WoxrXtYt_1_45; +reg [17:0] reg_Woc_45; +reg [17:0] reg_bo_45; +reg [17:0] reg_WcxrXtYt_1_45; +reg [17:0] reg_bc_45; +reg [17:0] reg_out_mt_45; +reg [17:0] reg_out_ct_45; +reg [17:0] reg_Ct_1_46; +reg [17:0] reg_WixrXtYt_1_46; +reg [17:0] reg_Wic_46; +reg [17:0] reg_bi_46; +reg [17:0] reg_WfxrXtYt_1_46; +reg [17:0] reg_Wfc_46; +reg [17:0] reg_bf_46; +reg [17:0] reg_WoxrXtYt_1_46; +reg [17:0] reg_Woc_46; +reg [17:0] reg_bo_46; +reg [17:0] reg_WcxrXtYt_1_46; +reg [17:0] reg_bc_46; +reg [17:0] reg_out_mt_46; +reg [17:0] reg_out_ct_46; +reg [17:0] reg_Ct_1_47; +reg [17:0] reg_WixrXtYt_1_47; +reg [17:0] reg_Wic_47; +reg [17:0] reg_bi_47; +reg [17:0] reg_WfxrXtYt_1_47; +reg [17:0] reg_Wfc_47; +reg [17:0] reg_bf_47; +reg [17:0] reg_WoxrXtYt_1_47; +reg [17:0] reg_Woc_47; +reg [17:0] reg_bo_47; +reg [17:0] reg_WcxrXtYt_1_47; +reg [17:0] reg_bc_47; +reg [17:0] reg_out_mt_47; +reg [17:0] reg_out_ct_47; + +wire input_gate_valid, forget_gate_valid, output_gate_valid, gt_valid; +wire it_gt_mult_valid, ft_Ct_1_mult_valid; +wire ct_valid; +wire tanh_valid_0; +wire [17:0] o_Ct_1_0; +wire [17:0] Ct_1_hold_0; +wire [17:0] o_input_gate_0; +wire [17:0] o_forget_gate_0; +wire [17:0] o_output_gate_0; +wire [17:0] ot_hold_0; +wire [17:0] o_gt_0; +wire [17:0] gt_hold_0; +wire [17:0] o_it_gt_mult_0; +wire [17:0] o_ft_Ct_1_mult_0; +wire [17:0] o_ct_0; +wire [17:0] ct_hold_0; +wire [17:0] o_tanh_0; +wire [17:0] o_mt_0; +wire tanh_valid_1; +wire [17:0] o_Ct_1_1; +wire [17:0] Ct_1_hold_1; +wire [17:0] o_input_gate_1; +wire [17:0] o_forget_gate_1; +wire [17:0] o_output_gate_1; +wire [17:0] ot_hold_1; +wire [17:0] o_gt_1; +wire [17:0] gt_hold_1; +wire [17:0] o_it_gt_mult_1; +wire [17:0] o_ft_Ct_1_mult_1; +wire [17:0] o_ct_1; +wire [17:0] ct_hold_1; +wire [17:0] o_tanh_1; +wire [17:0] o_mt_1; +wire tanh_valid_2; +wire [17:0] o_Ct_1_2; +wire [17:0] Ct_1_hold_2; +wire [17:0] o_input_gate_2; +wire [17:0] o_forget_gate_2; +wire [17:0] o_output_gate_2; +wire [17:0] ot_hold_2; +wire [17:0] o_gt_2; +wire [17:0] gt_hold_2; +wire [17:0] o_it_gt_mult_2; +wire [17:0] o_ft_Ct_1_mult_2; +wire [17:0] o_ct_2; +wire [17:0] ct_hold_2; +wire [17:0] o_tanh_2; +wire [17:0] o_mt_2; +wire tanh_valid_3; +wire [17:0] o_Ct_1_3; +wire [17:0] Ct_1_hold_3; +wire [17:0] o_input_gate_3; +wire [17:0] o_forget_gate_3; +wire [17:0] o_output_gate_3; +wire [17:0] ot_hold_3; +wire [17:0] o_gt_3; +wire [17:0] gt_hold_3; +wire [17:0] o_it_gt_mult_3; +wire [17:0] o_ft_Ct_1_mult_3; +wire [17:0] o_ct_3; +wire [17:0] ct_hold_3; +wire [17:0] o_tanh_3; +wire [17:0] o_mt_3; +wire tanh_valid_4; +wire [17:0] o_Ct_1_4; +wire [17:0] Ct_1_hold_4; +wire [17:0] o_input_gate_4; +wire [17:0] o_forget_gate_4; +wire [17:0] o_output_gate_4; +wire [17:0] ot_hold_4; +wire [17:0] o_gt_4; +wire [17:0] gt_hold_4; +wire [17:0] o_it_gt_mult_4; +wire [17:0] o_ft_Ct_1_mult_4; +wire [17:0] o_ct_4; +wire [17:0] ct_hold_4; +wire [17:0] o_tanh_4; +wire [17:0] o_mt_4; +wire tanh_valid_5; +wire [17:0] o_Ct_1_5; +wire [17:0] Ct_1_hold_5; +wire [17:0] o_input_gate_5; +wire [17:0] o_forget_gate_5; +wire [17:0] o_output_gate_5; +wire [17:0] ot_hold_5; +wire [17:0] o_gt_5; +wire [17:0] gt_hold_5; +wire [17:0] o_it_gt_mult_5; +wire [17:0] o_ft_Ct_1_mult_5; +wire [17:0] o_ct_5; +wire [17:0] ct_hold_5; +wire [17:0] o_tanh_5; +wire [17:0] o_mt_5; +wire tanh_valid_6; +wire [17:0] o_Ct_1_6; +wire [17:0] Ct_1_hold_6; +wire [17:0] o_input_gate_6; +wire [17:0] o_forget_gate_6; +wire [17:0] o_output_gate_6; +wire [17:0] ot_hold_6; +wire [17:0] o_gt_6; +wire [17:0] gt_hold_6; +wire [17:0] o_it_gt_mult_6; +wire [17:0] o_ft_Ct_1_mult_6; +wire [17:0] o_ct_6; +wire [17:0] ct_hold_6; +wire [17:0] o_tanh_6; +wire [17:0] o_mt_6; +wire tanh_valid_7; +wire [17:0] o_Ct_1_7; +wire [17:0] Ct_1_hold_7; +wire [17:0] o_input_gate_7; +wire [17:0] o_forget_gate_7; +wire [17:0] o_output_gate_7; +wire [17:0] ot_hold_7; +wire [17:0] o_gt_7; +wire [17:0] gt_hold_7; +wire [17:0] o_it_gt_mult_7; +wire [17:0] o_ft_Ct_1_mult_7; +wire [17:0] o_ct_7; +wire [17:0] ct_hold_7; +wire [17:0] o_tanh_7; +wire [17:0] o_mt_7; +wire tanh_valid_8; +wire [17:0] o_Ct_1_8; +wire [17:0] Ct_1_hold_8; +wire [17:0] o_input_gate_8; +wire [17:0] o_forget_gate_8; +wire [17:0] o_output_gate_8; +wire [17:0] ot_hold_8; +wire [17:0] o_gt_8; +wire [17:0] gt_hold_8; +wire [17:0] o_it_gt_mult_8; +wire [17:0] o_ft_Ct_1_mult_8; +wire [17:0] o_ct_8; +wire [17:0] ct_hold_8; +wire [17:0] o_tanh_8; +wire [17:0] o_mt_8; +wire tanh_valid_9; +wire [17:0] o_Ct_1_9; +wire [17:0] Ct_1_hold_9; +wire [17:0] o_input_gate_9; +wire [17:0] o_forget_gate_9; +wire [17:0] o_output_gate_9; +wire [17:0] ot_hold_9; +wire [17:0] o_gt_9; +wire [17:0] gt_hold_9; +wire [17:0] o_it_gt_mult_9; +wire [17:0] o_ft_Ct_1_mult_9; +wire [17:0] o_ct_9; +wire [17:0] ct_hold_9; +wire [17:0] o_tanh_9; +wire [17:0] o_mt_9; +wire tanh_valid_10; +wire [17:0] o_Ct_1_10; +wire [17:0] Ct_1_hold_10; +wire [17:0] o_input_gate_10; +wire [17:0] o_forget_gate_10; +wire [17:0] o_output_gate_10; +wire [17:0] ot_hold_10; +wire [17:0] o_gt_10; +wire [17:0] gt_hold_10; +wire [17:0] o_it_gt_mult_10; +wire [17:0] o_ft_Ct_1_mult_10; +wire [17:0] o_ct_10; +wire [17:0] ct_hold_10; +wire [17:0] o_tanh_10; +wire [17:0] o_mt_10; +wire tanh_valid_11; +wire [17:0] o_Ct_1_11; +wire [17:0] Ct_1_hold_11; +wire [17:0] o_input_gate_11; +wire [17:0] o_forget_gate_11; +wire [17:0] o_output_gate_11; +wire [17:0] ot_hold_11; +wire [17:0] o_gt_11; +wire [17:0] gt_hold_11; +wire [17:0] o_it_gt_mult_11; +wire [17:0] o_ft_Ct_1_mult_11; +wire [17:0] o_ct_11; +wire [17:0] ct_hold_11; +wire [17:0] o_tanh_11; +wire [17:0] o_mt_11; +wire tanh_valid_12; +wire [17:0] o_Ct_1_12; +wire [17:0] Ct_1_hold_12; +wire [17:0] o_input_gate_12; +wire [17:0] o_forget_gate_12; +wire [17:0] o_output_gate_12; +wire [17:0] ot_hold_12; +wire [17:0] o_gt_12; +wire [17:0] gt_hold_12; +wire [17:0] o_it_gt_mult_12; +wire [17:0] o_ft_Ct_1_mult_12; +wire [17:0] o_ct_12; +wire [17:0] ct_hold_12; +wire [17:0] o_tanh_12; +wire [17:0] o_mt_12; +wire tanh_valid_13; +wire [17:0] o_Ct_1_13; +wire [17:0] Ct_1_hold_13; +wire [17:0] o_input_gate_13; +wire [17:0] o_forget_gate_13; +wire [17:0] o_output_gate_13; +wire [17:0] ot_hold_13; +wire [17:0] o_gt_13; +wire [17:0] gt_hold_13; +wire [17:0] o_it_gt_mult_13; +wire [17:0] o_ft_Ct_1_mult_13; +wire [17:0] o_ct_13; +wire [17:0] ct_hold_13; +wire [17:0] o_tanh_13; +wire [17:0] o_mt_13; +wire tanh_valid_14; +wire [17:0] o_Ct_1_14; +wire [17:0] Ct_1_hold_14; +wire [17:0] o_input_gate_14; +wire [17:0] o_forget_gate_14; +wire [17:0] o_output_gate_14; +wire [17:0] ot_hold_14; +wire [17:0] o_gt_14; +wire [17:0] gt_hold_14; +wire [17:0] o_it_gt_mult_14; +wire [17:0] o_ft_Ct_1_mult_14; +wire [17:0] o_ct_14; +wire [17:0] ct_hold_14; +wire [17:0] o_tanh_14; +wire [17:0] o_mt_14; +wire tanh_valid_15; +wire [17:0] o_Ct_1_15; +wire [17:0] Ct_1_hold_15; +wire [17:0] o_input_gate_15; +wire [17:0] o_forget_gate_15; +wire [17:0] o_output_gate_15; +wire [17:0] ot_hold_15; +wire [17:0] o_gt_15; +wire [17:0] gt_hold_15; +wire [17:0] o_it_gt_mult_15; +wire [17:0] o_ft_Ct_1_mult_15; +wire [17:0] o_ct_15; +wire [17:0] ct_hold_15; +wire [17:0] o_tanh_15; +wire [17:0] o_mt_15; +wire tanh_valid_16; +wire [17:0] o_Ct_1_16; +wire [17:0] Ct_1_hold_16; +wire [17:0] o_input_gate_16; +wire [17:0] o_forget_gate_16; +wire [17:0] o_output_gate_16; +wire [17:0] ot_hold_16; +wire [17:0] o_gt_16; +wire [17:0] gt_hold_16; +wire [17:0] o_it_gt_mult_16; +wire [17:0] o_ft_Ct_1_mult_16; +wire [17:0] o_ct_16; +wire [17:0] ct_hold_16; +wire [17:0] o_tanh_16; +wire [17:0] o_mt_16; +wire tanh_valid_17; +wire [17:0] o_Ct_1_17; +wire [17:0] Ct_1_hold_17; +wire [17:0] o_input_gate_17; +wire [17:0] o_forget_gate_17; +wire [17:0] o_output_gate_17; +wire [17:0] ot_hold_17; +wire [17:0] o_gt_17; +wire [17:0] gt_hold_17; +wire [17:0] o_it_gt_mult_17; +wire [17:0] o_ft_Ct_1_mult_17; +wire [17:0] o_ct_17; +wire [17:0] ct_hold_17; +wire [17:0] o_tanh_17; +wire [17:0] o_mt_17; +wire tanh_valid_18; +wire [17:0] o_Ct_1_18; +wire [17:0] Ct_1_hold_18; +wire [17:0] o_input_gate_18; +wire [17:0] o_forget_gate_18; +wire [17:0] o_output_gate_18; +wire [17:0] ot_hold_18; +wire [17:0] o_gt_18; +wire [17:0] gt_hold_18; +wire [17:0] o_it_gt_mult_18; +wire [17:0] o_ft_Ct_1_mult_18; +wire [17:0] o_ct_18; +wire [17:0] ct_hold_18; +wire [17:0] o_tanh_18; +wire [17:0] o_mt_18; +wire tanh_valid_19; +wire [17:0] o_Ct_1_19; +wire [17:0] Ct_1_hold_19; +wire [17:0] o_input_gate_19; +wire [17:0] o_forget_gate_19; +wire [17:0] o_output_gate_19; +wire [17:0] ot_hold_19; +wire [17:0] o_gt_19; +wire [17:0] gt_hold_19; +wire [17:0] o_it_gt_mult_19; +wire [17:0] o_ft_Ct_1_mult_19; +wire [17:0] o_ct_19; +wire [17:0] ct_hold_19; +wire [17:0] o_tanh_19; +wire [17:0] o_mt_19; +wire tanh_valid_20; +wire [17:0] o_Ct_1_20; +wire [17:0] Ct_1_hold_20; +wire [17:0] o_input_gate_20; +wire [17:0] o_forget_gate_20; +wire [17:0] o_output_gate_20; +wire [17:0] ot_hold_20; +wire [17:0] o_gt_20; +wire [17:0] gt_hold_20; +wire [17:0] o_it_gt_mult_20; +wire [17:0] o_ft_Ct_1_mult_20; +wire [17:0] o_ct_20; +wire [17:0] ct_hold_20; +wire [17:0] o_tanh_20; +wire [17:0] o_mt_20; +wire tanh_valid_21; +wire [17:0] o_Ct_1_21; +wire [17:0] Ct_1_hold_21; +wire [17:0] o_input_gate_21; +wire [17:0] o_forget_gate_21; +wire [17:0] o_output_gate_21; +wire [17:0] ot_hold_21; +wire [17:0] o_gt_21; +wire [17:0] gt_hold_21; +wire [17:0] o_it_gt_mult_21; +wire [17:0] o_ft_Ct_1_mult_21; +wire [17:0] o_ct_21; +wire [17:0] ct_hold_21; +wire [17:0] o_tanh_21; +wire [17:0] o_mt_21; +wire tanh_valid_22; +wire [17:0] o_Ct_1_22; +wire [17:0] Ct_1_hold_22; +wire [17:0] o_input_gate_22; +wire [17:0] o_forget_gate_22; +wire [17:0] o_output_gate_22; +wire [17:0] ot_hold_22; +wire [17:0] o_gt_22; +wire [17:0] gt_hold_22; +wire [17:0] o_it_gt_mult_22; +wire [17:0] o_ft_Ct_1_mult_22; +wire [17:0] o_ct_22; +wire [17:0] ct_hold_22; +wire [17:0] o_tanh_22; +wire [17:0] o_mt_22; +wire tanh_valid_23; +wire [17:0] o_Ct_1_23; +wire [17:0] Ct_1_hold_23; +wire [17:0] o_input_gate_23; +wire [17:0] o_forget_gate_23; +wire [17:0] o_output_gate_23; +wire [17:0] ot_hold_23; +wire [17:0] o_gt_23; +wire [17:0] gt_hold_23; +wire [17:0] o_it_gt_mult_23; +wire [17:0] o_ft_Ct_1_mult_23; +wire [17:0] o_ct_23; +wire [17:0] ct_hold_23; +wire [17:0] o_tanh_23; +wire [17:0] o_mt_23; +wire tanh_valid_24; +wire [17:0] o_Ct_1_24; +wire [17:0] Ct_1_hold_24; +wire [17:0] o_input_gate_24; +wire [17:0] o_forget_gate_24; +wire [17:0] o_output_gate_24; +wire [17:0] ot_hold_24; +wire [17:0] o_gt_24; +wire [17:0] gt_hold_24; +wire [17:0] o_it_gt_mult_24; +wire [17:0] o_ft_Ct_1_mult_24; +wire [17:0] o_ct_24; +wire [17:0] ct_hold_24; +wire [17:0] o_tanh_24; +wire [17:0] o_mt_24; +wire tanh_valid_25; +wire [17:0] o_Ct_1_25; +wire [17:0] Ct_1_hold_25; +wire [17:0] o_input_gate_25; +wire [17:0] o_forget_gate_25; +wire [17:0] o_output_gate_25; +wire [17:0] ot_hold_25; +wire [17:0] o_gt_25; +wire [17:0] gt_hold_25; +wire [17:0] o_it_gt_mult_25; +wire [17:0] o_ft_Ct_1_mult_25; +wire [17:0] o_ct_25; +wire [17:0] ct_hold_25; +wire [17:0] o_tanh_25; +wire [17:0] o_mt_25; +wire tanh_valid_26; +wire [17:0] o_Ct_1_26; +wire [17:0] Ct_1_hold_26; +wire [17:0] o_input_gate_26; +wire [17:0] o_forget_gate_26; +wire [17:0] o_output_gate_26; +wire [17:0] ot_hold_26; +wire [17:0] o_gt_26; +wire [17:0] gt_hold_26; +wire [17:0] o_it_gt_mult_26; +wire [17:0] o_ft_Ct_1_mult_26; +wire [17:0] o_ct_26; +wire [17:0] ct_hold_26; +wire [17:0] o_tanh_26; +wire [17:0] o_mt_26; +wire tanh_valid_27; +wire [17:0] o_Ct_1_27; +wire [17:0] Ct_1_hold_27; +wire [17:0] o_input_gate_27; +wire [17:0] o_forget_gate_27; +wire [17:0] o_output_gate_27; +wire [17:0] ot_hold_27; +wire [17:0] o_gt_27; +wire [17:0] gt_hold_27; +wire [17:0] o_it_gt_mult_27; +wire [17:0] o_ft_Ct_1_mult_27; +wire [17:0] o_ct_27; +wire [17:0] ct_hold_27; +wire [17:0] o_tanh_27; +wire [17:0] o_mt_27; +wire tanh_valid_28; +wire [17:0] o_Ct_1_28; +wire [17:0] Ct_1_hold_28; +wire [17:0] o_input_gate_28; +wire [17:0] o_forget_gate_28; +wire [17:0] o_output_gate_28; +wire [17:0] ot_hold_28; +wire [17:0] o_gt_28; +wire [17:0] gt_hold_28; +wire [17:0] o_it_gt_mult_28; +wire [17:0] o_ft_Ct_1_mult_28; +wire [17:0] o_ct_28; +wire [17:0] ct_hold_28; +wire [17:0] o_tanh_28; +wire [17:0] o_mt_28; +wire tanh_valid_29; +wire [17:0] o_Ct_1_29; +wire [17:0] Ct_1_hold_29; +wire [17:0] o_input_gate_29; +wire [17:0] o_forget_gate_29; +wire [17:0] o_output_gate_29; +wire [17:0] ot_hold_29; +wire [17:0] o_gt_29; +wire [17:0] gt_hold_29; +wire [17:0] o_it_gt_mult_29; +wire [17:0] o_ft_Ct_1_mult_29; +wire [17:0] o_ct_29; +wire [17:0] ct_hold_29; +wire [17:0] o_tanh_29; +wire [17:0] o_mt_29; +wire tanh_valid_30; +wire [17:0] o_Ct_1_30; +wire [17:0] Ct_1_hold_30; +wire [17:0] o_input_gate_30; +wire [17:0] o_forget_gate_30; +wire [17:0] o_output_gate_30; +wire [17:0] ot_hold_30; +wire [17:0] o_gt_30; +wire [17:0] gt_hold_30; +wire [17:0] o_it_gt_mult_30; +wire [17:0] o_ft_Ct_1_mult_30; +wire [17:0] o_ct_30; +wire [17:0] ct_hold_30; +wire [17:0] o_tanh_30; +wire [17:0] o_mt_30; +wire tanh_valid_31; +wire [17:0] o_Ct_1_31; +wire [17:0] Ct_1_hold_31; +wire [17:0] o_input_gate_31; +wire [17:0] o_forget_gate_31; +wire [17:0] o_output_gate_31; +wire [17:0] ot_hold_31; +wire [17:0] o_gt_31; +wire [17:0] gt_hold_31; +wire [17:0] o_it_gt_mult_31; +wire [17:0] o_ft_Ct_1_mult_31; +wire [17:0] o_ct_31; +wire [17:0] ct_hold_31; +wire [17:0] o_tanh_31; +wire [17:0] o_mt_31; +wire tanh_valid_32; +wire [17:0] o_Ct_1_32; +wire [17:0] Ct_1_hold_32; +wire [17:0] o_input_gate_32; +wire [17:0] o_forget_gate_32; +wire [17:0] o_output_gate_32; +wire [17:0] ot_hold_32; +wire [17:0] o_gt_32; +wire [17:0] gt_hold_32; +wire [17:0] o_it_gt_mult_32; +wire [17:0] o_ft_Ct_1_mult_32; +wire [17:0] o_ct_32; +wire [17:0] ct_hold_32; +wire [17:0] o_tanh_32; +wire [17:0] o_mt_32; +wire tanh_valid_33; +wire [17:0] o_Ct_1_33; +wire [17:0] Ct_1_hold_33; +wire [17:0] o_input_gate_33; +wire [17:0] o_forget_gate_33; +wire [17:0] o_output_gate_33; +wire [17:0] ot_hold_33; +wire [17:0] o_gt_33; +wire [17:0] gt_hold_33; +wire [17:0] o_it_gt_mult_33; +wire [17:0] o_ft_Ct_1_mult_33; +wire [17:0] o_ct_33; +wire [17:0] ct_hold_33; +wire [17:0] o_tanh_33; +wire [17:0] o_mt_33; +wire tanh_valid_34; +wire [17:0] o_Ct_1_34; +wire [17:0] Ct_1_hold_34; +wire [17:0] o_input_gate_34; +wire [17:0] o_forget_gate_34; +wire [17:0] o_output_gate_34; +wire [17:0] ot_hold_34; +wire [17:0] o_gt_34; +wire [17:0] gt_hold_34; +wire [17:0] o_it_gt_mult_34; +wire [17:0] o_ft_Ct_1_mult_34; +wire [17:0] o_ct_34; +wire [17:0] ct_hold_34; +wire [17:0] o_tanh_34; +wire [17:0] o_mt_34; +wire tanh_valid_35; +wire [17:0] o_Ct_1_35; +wire [17:0] Ct_1_hold_35; +wire [17:0] o_input_gate_35; +wire [17:0] o_forget_gate_35; +wire [17:0] o_output_gate_35; +wire [17:0] ot_hold_35; +wire [17:0] o_gt_35; +wire [17:0] gt_hold_35; +wire [17:0] o_it_gt_mult_35; +wire [17:0] o_ft_Ct_1_mult_35; +wire [17:0] o_ct_35; +wire [17:0] ct_hold_35; +wire [17:0] o_tanh_35; +wire [17:0] o_mt_35; +wire tanh_valid_36; +wire [17:0] o_Ct_1_36; +wire [17:0] Ct_1_hold_36; +wire [17:0] o_input_gate_36; +wire [17:0] o_forget_gate_36; +wire [17:0] o_output_gate_36; +wire [17:0] ot_hold_36; +wire [17:0] o_gt_36; +wire [17:0] gt_hold_36; +wire [17:0] o_it_gt_mult_36; +wire [17:0] o_ft_Ct_1_mult_36; +wire [17:0] o_ct_36; +wire [17:0] ct_hold_36; +wire [17:0] o_tanh_36; +wire [17:0] o_mt_36; +wire tanh_valid_37; +wire [17:0] o_Ct_1_37; +wire [17:0] Ct_1_hold_37; +wire [17:0] o_input_gate_37; +wire [17:0] o_forget_gate_37; +wire [17:0] o_output_gate_37; +wire [17:0] ot_hold_37; +wire [17:0] o_gt_37; +wire [17:0] gt_hold_37; +wire [17:0] o_it_gt_mult_37; +wire [17:0] o_ft_Ct_1_mult_37; +wire [17:0] o_ct_37; +wire [17:0] ct_hold_37; +wire [17:0] o_tanh_37; +wire [17:0] o_mt_37; +wire tanh_valid_38; +wire [17:0] o_Ct_1_38; +wire [17:0] Ct_1_hold_38; +wire [17:0] o_input_gate_38; +wire [17:0] o_forget_gate_38; +wire [17:0] o_output_gate_38; +wire [17:0] ot_hold_38; +wire [17:0] o_gt_38; +wire [17:0] gt_hold_38; +wire [17:0] o_it_gt_mult_38; +wire [17:0] o_ft_Ct_1_mult_38; +wire [17:0] o_ct_38; +wire [17:0] ct_hold_38; +wire [17:0] o_tanh_38; +wire [17:0] o_mt_38; +wire tanh_valid_39; +wire [17:0] o_Ct_1_39; +wire [17:0] Ct_1_hold_39; +wire [17:0] o_input_gate_39; +wire [17:0] o_forget_gate_39; +wire [17:0] o_output_gate_39; +wire [17:0] ot_hold_39; +wire [17:0] o_gt_39; +wire [17:0] gt_hold_39; +wire [17:0] o_it_gt_mult_39; +wire [17:0] o_ft_Ct_1_mult_39; +wire [17:0] o_ct_39; +wire [17:0] ct_hold_39; +wire [17:0] o_tanh_39; +wire [17:0] o_mt_39; +wire tanh_valid_40; +wire [17:0] o_Ct_1_40; +wire [17:0] Ct_1_hold_40; +wire [17:0] o_input_gate_40; +wire [17:0] o_forget_gate_40; +wire [17:0] o_output_gate_40; +wire [17:0] ot_hold_40; +wire [17:0] o_gt_40; +wire [17:0] gt_hold_40; +wire [17:0] o_it_gt_mult_40; +wire [17:0] o_ft_Ct_1_mult_40; +wire [17:0] o_ct_40; +wire [17:0] ct_hold_40; +wire [17:0] o_tanh_40; +wire [17:0] o_mt_40; +wire tanh_valid_41; +wire [17:0] o_Ct_1_41; +wire [17:0] Ct_1_hold_41; +wire [17:0] o_input_gate_41; +wire [17:0] o_forget_gate_41; +wire [17:0] o_output_gate_41; +wire [17:0] ot_hold_41; +wire [17:0] o_gt_41; +wire [17:0] gt_hold_41; +wire [17:0] o_it_gt_mult_41; +wire [17:0] o_ft_Ct_1_mult_41; +wire [17:0] o_ct_41; +wire [17:0] ct_hold_41; +wire [17:0] o_tanh_41; +wire [17:0] o_mt_41; +wire tanh_valid_42; +wire [17:0] o_Ct_1_42; +wire [17:0] Ct_1_hold_42; +wire [17:0] o_input_gate_42; +wire [17:0] o_forget_gate_42; +wire [17:0] o_output_gate_42; +wire [17:0] ot_hold_42; +wire [17:0] o_gt_42; +wire [17:0] gt_hold_42; +wire [17:0] o_it_gt_mult_42; +wire [17:0] o_ft_Ct_1_mult_42; +wire [17:0] o_ct_42; +wire [17:0] ct_hold_42; +wire [17:0] o_tanh_42; +wire [17:0] o_mt_42; +wire tanh_valid_43; +wire [17:0] o_Ct_1_43; +wire [17:0] Ct_1_hold_43; +wire [17:0] o_input_gate_43; +wire [17:0] o_forget_gate_43; +wire [17:0] o_output_gate_43; +wire [17:0] ot_hold_43; +wire [17:0] o_gt_43; +wire [17:0] gt_hold_43; +wire [17:0] o_it_gt_mult_43; +wire [17:0] o_ft_Ct_1_mult_43; +wire [17:0] o_ct_43; +wire [17:0] ct_hold_43; +wire [17:0] o_tanh_43; +wire [17:0] o_mt_43; +wire tanh_valid_44; +wire [17:0] o_Ct_1_44; +wire [17:0] Ct_1_hold_44; +wire [17:0] o_input_gate_44; +wire [17:0] o_forget_gate_44; +wire [17:0] o_output_gate_44; +wire [17:0] ot_hold_44; +wire [17:0] o_gt_44; +wire [17:0] gt_hold_44; +wire [17:0] o_it_gt_mult_44; +wire [17:0] o_ft_Ct_1_mult_44; +wire [17:0] o_ct_44; +wire [17:0] ct_hold_44; +wire [17:0] o_tanh_44; +wire [17:0] o_mt_44; +wire tanh_valid_45; +wire [17:0] o_Ct_1_45; +wire [17:0] Ct_1_hold_45; +wire [17:0] o_input_gate_45; +wire [17:0] o_forget_gate_45; +wire [17:0] o_output_gate_45; +wire [17:0] ot_hold_45; +wire [17:0] o_gt_45; +wire [17:0] gt_hold_45; +wire [17:0] o_it_gt_mult_45; +wire [17:0] o_ft_Ct_1_mult_45; +wire [17:0] o_ct_45; +wire [17:0] ct_hold_45; +wire [17:0] o_tanh_45; +wire [17:0] o_mt_45; +wire tanh_valid_46; +wire [17:0] o_Ct_1_46; +wire [17:0] Ct_1_hold_46; +wire [17:0] o_input_gate_46; +wire [17:0] o_forget_gate_46; +wire [17:0] o_output_gate_46; +wire [17:0] ot_hold_46; +wire [17:0] o_gt_46; +wire [17:0] gt_hold_46; +wire [17:0] o_it_gt_mult_46; +wire [17:0] o_ft_Ct_1_mult_46; +wire [17:0] o_ct_46; +wire [17:0] ct_hold_46; +wire [17:0] o_tanh_46; +wire [17:0] o_mt_46; +wire tanh_valid_47; +wire [17:0] o_Ct_1_47; +wire [17:0] Ct_1_hold_47; +wire [17:0] o_input_gate_47; +wire [17:0] o_forget_gate_47; +wire [17:0] o_output_gate_47; +wire [17:0] ot_hold_47; +wire [17:0] o_gt_47; +wire [17:0] gt_hold_47; +wire [17:0] o_it_gt_mult_47; +wire [17:0] o_ft_Ct_1_mult_47; +wire [17:0] o_ct_47; +wire [17:0] ct_hold_47; +wire [17:0] o_tanh_47; +wire [17:0] o_mt_47; +wire mt_valid; + +assign o_Ct_1_0 = reg_Ct_1_0; +assign o_Ct_1_1 = reg_Ct_1_1; +assign o_Ct_1_2 = reg_Ct_1_2; +assign o_Ct_1_3 = reg_Ct_1_3; +assign o_Ct_1_4 = reg_Ct_1_4; +assign o_Ct_1_5 = reg_Ct_1_5; +assign o_Ct_1_6 = reg_Ct_1_6; +assign o_Ct_1_7 = reg_Ct_1_7; +assign o_Ct_1_8 = reg_Ct_1_8; +assign o_Ct_1_9 = reg_Ct_1_9; +assign o_Ct_1_10 = reg_Ct_1_10; +assign o_Ct_1_11 = reg_Ct_1_11; +assign o_Ct_1_12 = reg_Ct_1_12; +assign o_Ct_1_13 = reg_Ct_1_13; +assign o_Ct_1_14 = reg_Ct_1_14; +assign o_Ct_1_15 = reg_Ct_1_15; +assign o_Ct_1_16 = reg_Ct_1_16; +assign o_Ct_1_17 = reg_Ct_1_17; +assign o_Ct_1_18 = reg_Ct_1_18; +assign o_Ct_1_19 = reg_Ct_1_19; +assign o_Ct_1_20 = reg_Ct_1_20; +assign o_Ct_1_21 = reg_Ct_1_21; +assign o_Ct_1_22 = reg_Ct_1_22; +assign o_Ct_1_23 = reg_Ct_1_23; +assign o_Ct_1_24 = reg_Ct_1_24; +assign o_Ct_1_25 = reg_Ct_1_25; +assign o_Ct_1_26 = reg_Ct_1_26; +assign o_Ct_1_27 = reg_Ct_1_27; +assign o_Ct_1_28 = reg_Ct_1_28; +assign o_Ct_1_29 = reg_Ct_1_29; +assign o_Ct_1_30 = reg_Ct_1_30; +assign o_Ct_1_31 = reg_Ct_1_31; +assign o_Ct_1_32 = reg_Ct_1_32; +assign o_Ct_1_33 = reg_Ct_1_33; +assign o_Ct_1_34 = reg_Ct_1_34; +assign o_Ct_1_35 = reg_Ct_1_35; +assign o_Ct_1_36 = reg_Ct_1_36; +assign o_Ct_1_37 = reg_Ct_1_37; +assign o_Ct_1_38 = reg_Ct_1_38; +assign o_Ct_1_39 = reg_Ct_1_39; +assign o_Ct_1_40 = reg_Ct_1_40; +assign o_Ct_1_41 = reg_Ct_1_41; +assign o_Ct_1_42 = reg_Ct_1_42; +assign o_Ct_1_43 = reg_Ct_1_43; +assign o_Ct_1_44 = reg_Ct_1_44; +assign o_Ct_1_45 = reg_Ct_1_45; +assign o_Ct_1_46 = reg_Ct_1_46; +assign o_Ct_1_47 = reg_Ct_1_47; +lstm_gate_18_10_48_1 lstm_gate_18_10_48_1_input ( + .clk(clk), + .reset(reset), + .i_ready(enable), + .i_valid(reg_i_valid), + .stage1_result_0(reg_WixrXtYt_1_0), + .weight_0(reg_Wic_0), + .Ct_1_0(reg_Ct_1_0), + .bias_0(reg_bi_0), + .gate_output_0(o_input_gate_0), + .stage1_result_1(reg_WixrXtYt_1_1), + .weight_1(reg_Wic_1), + .Ct_1_1(reg_Ct_1_1), + .bias_1(reg_bi_1), + .gate_output_1(o_input_gate_1), + .stage1_result_2(reg_WixrXtYt_1_2), + .weight_2(reg_Wic_2), + .Ct_1_2(reg_Ct_1_2), + .bias_2(reg_bi_2), + .gate_output_2(o_input_gate_2), + .stage1_result_3(reg_WixrXtYt_1_3), + .weight_3(reg_Wic_3), + .Ct_1_3(reg_Ct_1_3), + .bias_3(reg_bi_3), + .gate_output_3(o_input_gate_3), + .stage1_result_4(reg_WixrXtYt_1_4), + .weight_4(reg_Wic_4), + .Ct_1_4(reg_Ct_1_4), + .bias_4(reg_bi_4), + .gate_output_4(o_input_gate_4), + .stage1_result_5(reg_WixrXtYt_1_5), + .weight_5(reg_Wic_5), + .Ct_1_5(reg_Ct_1_5), + .bias_5(reg_bi_5), + .gate_output_5(o_input_gate_5), + .stage1_result_6(reg_WixrXtYt_1_6), + .weight_6(reg_Wic_6), + .Ct_1_6(reg_Ct_1_6), + .bias_6(reg_bi_6), + .gate_output_6(o_input_gate_6), + .stage1_result_7(reg_WixrXtYt_1_7), + .weight_7(reg_Wic_7), + .Ct_1_7(reg_Ct_1_7), + .bias_7(reg_bi_7), + .gate_output_7(o_input_gate_7), + .stage1_result_8(reg_WixrXtYt_1_8), + .weight_8(reg_Wic_8), + .Ct_1_8(reg_Ct_1_8), + .bias_8(reg_bi_8), + .gate_output_8(o_input_gate_8), + .stage1_result_9(reg_WixrXtYt_1_9), + .weight_9(reg_Wic_9), + .Ct_1_9(reg_Ct_1_9), + .bias_9(reg_bi_9), + .gate_output_9(o_input_gate_9), + .stage1_result_10(reg_WixrXtYt_1_10), + .weight_10(reg_Wic_10), + .Ct_1_10(reg_Ct_1_10), + .bias_10(reg_bi_10), + .gate_output_10(o_input_gate_10), + .stage1_result_11(reg_WixrXtYt_1_11), + .weight_11(reg_Wic_11), + .Ct_1_11(reg_Ct_1_11), + .bias_11(reg_bi_11), + .gate_output_11(o_input_gate_11), + .stage1_result_12(reg_WixrXtYt_1_12), + .weight_12(reg_Wic_12), + .Ct_1_12(reg_Ct_1_12), + .bias_12(reg_bi_12), + .gate_output_12(o_input_gate_12), + .stage1_result_13(reg_WixrXtYt_1_13), + .weight_13(reg_Wic_13), + .Ct_1_13(reg_Ct_1_13), + .bias_13(reg_bi_13), + .gate_output_13(o_input_gate_13), + .stage1_result_14(reg_WixrXtYt_1_14), + .weight_14(reg_Wic_14), + .Ct_1_14(reg_Ct_1_14), + .bias_14(reg_bi_14), + .gate_output_14(o_input_gate_14), + .stage1_result_15(reg_WixrXtYt_1_15), + .weight_15(reg_Wic_15), + .Ct_1_15(reg_Ct_1_15), + .bias_15(reg_bi_15), + .gate_output_15(o_input_gate_15), + .stage1_result_16(reg_WixrXtYt_1_16), + .weight_16(reg_Wic_16), + .Ct_1_16(reg_Ct_1_16), + .bias_16(reg_bi_16), + .gate_output_16(o_input_gate_16), + .stage1_result_17(reg_WixrXtYt_1_17), + .weight_17(reg_Wic_17), + .Ct_1_17(reg_Ct_1_17), + .bias_17(reg_bi_17), + .gate_output_17(o_input_gate_17), + .stage1_result_18(reg_WixrXtYt_1_18), + .weight_18(reg_Wic_18), + .Ct_1_18(reg_Ct_1_18), + .bias_18(reg_bi_18), + .gate_output_18(o_input_gate_18), + .stage1_result_19(reg_WixrXtYt_1_19), + .weight_19(reg_Wic_19), + .Ct_1_19(reg_Ct_1_19), + .bias_19(reg_bi_19), + .gate_output_19(o_input_gate_19), + .stage1_result_20(reg_WixrXtYt_1_20), + .weight_20(reg_Wic_20), + .Ct_1_20(reg_Ct_1_20), + .bias_20(reg_bi_20), + .gate_output_20(o_input_gate_20), + .stage1_result_21(reg_WixrXtYt_1_21), + .weight_21(reg_Wic_21), + .Ct_1_21(reg_Ct_1_21), + .bias_21(reg_bi_21), + .gate_output_21(o_input_gate_21), + .stage1_result_22(reg_WixrXtYt_1_22), + .weight_22(reg_Wic_22), + .Ct_1_22(reg_Ct_1_22), + .bias_22(reg_bi_22), + .gate_output_22(o_input_gate_22), + .stage1_result_23(reg_WixrXtYt_1_23), + .weight_23(reg_Wic_23), + .Ct_1_23(reg_Ct_1_23), + .bias_23(reg_bi_23), + .gate_output_23(o_input_gate_23), + .stage1_result_24(reg_WixrXtYt_1_24), + .weight_24(reg_Wic_24), + .Ct_1_24(reg_Ct_1_24), + .bias_24(reg_bi_24), + .gate_output_24(o_input_gate_24), + .stage1_result_25(reg_WixrXtYt_1_25), + .weight_25(reg_Wic_25), + .Ct_1_25(reg_Ct_1_25), + .bias_25(reg_bi_25), + .gate_output_25(o_input_gate_25), + .stage1_result_26(reg_WixrXtYt_1_26), + .weight_26(reg_Wic_26), + .Ct_1_26(reg_Ct_1_26), + .bias_26(reg_bi_26), + .gate_output_26(o_input_gate_26), + .stage1_result_27(reg_WixrXtYt_1_27), + .weight_27(reg_Wic_27), + .Ct_1_27(reg_Ct_1_27), + .bias_27(reg_bi_27), + .gate_output_27(o_input_gate_27), + .stage1_result_28(reg_WixrXtYt_1_28), + .weight_28(reg_Wic_28), + .Ct_1_28(reg_Ct_1_28), + .bias_28(reg_bi_28), + .gate_output_28(o_input_gate_28), + .stage1_result_29(reg_WixrXtYt_1_29), + .weight_29(reg_Wic_29), + .Ct_1_29(reg_Ct_1_29), + .bias_29(reg_bi_29), + .gate_output_29(o_input_gate_29), + .stage1_result_30(reg_WixrXtYt_1_30), + .weight_30(reg_Wic_30), + .Ct_1_30(reg_Ct_1_30), + .bias_30(reg_bi_30), + .gate_output_30(o_input_gate_30), + .stage1_result_31(reg_WixrXtYt_1_31), + .weight_31(reg_Wic_31), + .Ct_1_31(reg_Ct_1_31), + .bias_31(reg_bi_31), + .gate_output_31(o_input_gate_31), + .stage1_result_32(reg_WixrXtYt_1_32), + .weight_32(reg_Wic_32), + .Ct_1_32(reg_Ct_1_32), + .bias_32(reg_bi_32), + .gate_output_32(o_input_gate_32), + .stage1_result_33(reg_WixrXtYt_1_33), + .weight_33(reg_Wic_33), + .Ct_1_33(reg_Ct_1_33), + .bias_33(reg_bi_33), + .gate_output_33(o_input_gate_33), + .stage1_result_34(reg_WixrXtYt_1_34), + .weight_34(reg_Wic_34), + .Ct_1_34(reg_Ct_1_34), + .bias_34(reg_bi_34), + .gate_output_34(o_input_gate_34), + .stage1_result_35(reg_WixrXtYt_1_35), + .weight_35(reg_Wic_35), + .Ct_1_35(reg_Ct_1_35), + .bias_35(reg_bi_35), + .gate_output_35(o_input_gate_35), + .stage1_result_36(reg_WixrXtYt_1_36), + .weight_36(reg_Wic_36), + .Ct_1_36(reg_Ct_1_36), + .bias_36(reg_bi_36), + .gate_output_36(o_input_gate_36), + .stage1_result_37(reg_WixrXtYt_1_37), + .weight_37(reg_Wic_37), + .Ct_1_37(reg_Ct_1_37), + .bias_37(reg_bi_37), + .gate_output_37(o_input_gate_37), + .stage1_result_38(reg_WixrXtYt_1_38), + .weight_38(reg_Wic_38), + .Ct_1_38(reg_Ct_1_38), + .bias_38(reg_bi_38), + .gate_output_38(o_input_gate_38), + .stage1_result_39(reg_WixrXtYt_1_39), + .weight_39(reg_Wic_39), + .Ct_1_39(reg_Ct_1_39), + .bias_39(reg_bi_39), + .gate_output_39(o_input_gate_39), + .stage1_result_40(reg_WixrXtYt_1_40), + .weight_40(reg_Wic_40), + .Ct_1_40(reg_Ct_1_40), + .bias_40(reg_bi_40), + .gate_output_40(o_input_gate_40), + .stage1_result_41(reg_WixrXtYt_1_41), + .weight_41(reg_Wic_41), + .Ct_1_41(reg_Ct_1_41), + .bias_41(reg_bi_41), + .gate_output_41(o_input_gate_41), + .stage1_result_42(reg_WixrXtYt_1_42), + .weight_42(reg_Wic_42), + .Ct_1_42(reg_Ct_1_42), + .bias_42(reg_bi_42), + .gate_output_42(o_input_gate_42), + .stage1_result_43(reg_WixrXtYt_1_43), + .weight_43(reg_Wic_43), + .Ct_1_43(reg_Ct_1_43), + .bias_43(reg_bi_43), + .gate_output_43(o_input_gate_43), + .stage1_result_44(reg_WixrXtYt_1_44), + .weight_44(reg_Wic_44), + .Ct_1_44(reg_Ct_1_44), + .bias_44(reg_bi_44), + .gate_output_44(o_input_gate_44), + .stage1_result_45(reg_WixrXtYt_1_45), + .weight_45(reg_Wic_45), + .Ct_1_45(reg_Ct_1_45), + .bias_45(reg_bi_45), + .gate_output_45(o_input_gate_45), + .stage1_result_46(reg_WixrXtYt_1_46), + .weight_46(reg_Wic_46), + .Ct_1_46(reg_Ct_1_46), + .bias_46(reg_bi_46), + .gate_output_46(o_input_gate_46), + .stage1_result_47(reg_WixrXtYt_1_47), + .weight_47(reg_Wic_47), + .Ct_1_47(reg_Ct_1_47), + .bias_47(reg_bi_47), + .gate_output_47(o_input_gate_47), + .o_valid(input_gate_valid), + .o_ready() +); + +lstm_gate_18_10_48_1 lstm_gate_18_10_48_1_forget ( + .clk(clk), + .reset(reset), + .i_ready(enable), + .i_valid(reg_i_valid), + .stage1_result_0(reg_WfxrXtYt_1_0), + .weight_0(reg_Wfc_0), + .Ct_1_0(reg_Ct_1_0), + .bias_0(reg_bf_0), + .gate_output_0(o_forget_gate_0), + .stage1_result_1(reg_WfxrXtYt_1_1), + .weight_1(reg_Wfc_1), + .Ct_1_1(reg_Ct_1_1), + .bias_1(reg_bf_1), + .gate_output_1(o_forget_gate_1), + .stage1_result_2(reg_WfxrXtYt_1_2), + .weight_2(reg_Wfc_2), + .Ct_1_2(reg_Ct_1_2), + .bias_2(reg_bf_2), + .gate_output_2(o_forget_gate_2), + .stage1_result_3(reg_WfxrXtYt_1_3), + .weight_3(reg_Wfc_3), + .Ct_1_3(reg_Ct_1_3), + .bias_3(reg_bf_3), + .gate_output_3(o_forget_gate_3), + .stage1_result_4(reg_WfxrXtYt_1_4), + .weight_4(reg_Wfc_4), + .Ct_1_4(reg_Ct_1_4), + .bias_4(reg_bf_4), + .gate_output_4(o_forget_gate_4), + .stage1_result_5(reg_WfxrXtYt_1_5), + .weight_5(reg_Wfc_5), + .Ct_1_5(reg_Ct_1_5), + .bias_5(reg_bf_5), + .gate_output_5(o_forget_gate_5), + .stage1_result_6(reg_WfxrXtYt_1_6), + .weight_6(reg_Wfc_6), + .Ct_1_6(reg_Ct_1_6), + .bias_6(reg_bf_6), + .gate_output_6(o_forget_gate_6), + .stage1_result_7(reg_WfxrXtYt_1_7), + .weight_7(reg_Wfc_7), + .Ct_1_7(reg_Ct_1_7), + .bias_7(reg_bf_7), + .gate_output_7(o_forget_gate_7), + .stage1_result_8(reg_WfxrXtYt_1_8), + .weight_8(reg_Wfc_8), + .Ct_1_8(reg_Ct_1_8), + .bias_8(reg_bf_8), + .gate_output_8(o_forget_gate_8), + .stage1_result_9(reg_WfxrXtYt_1_9), + .weight_9(reg_Wfc_9), + .Ct_1_9(reg_Ct_1_9), + .bias_9(reg_bf_9), + .gate_output_9(o_forget_gate_9), + .stage1_result_10(reg_WfxrXtYt_1_10), + .weight_10(reg_Wfc_10), + .Ct_1_10(reg_Ct_1_10), + .bias_10(reg_bf_10), + .gate_output_10(o_forget_gate_10), + .stage1_result_11(reg_WfxrXtYt_1_11), + .weight_11(reg_Wfc_11), + .Ct_1_11(reg_Ct_1_11), + .bias_11(reg_bf_11), + .gate_output_11(o_forget_gate_11), + .stage1_result_12(reg_WfxrXtYt_1_12), + .weight_12(reg_Wfc_12), + .Ct_1_12(reg_Ct_1_12), + .bias_12(reg_bf_12), + .gate_output_12(o_forget_gate_12), + .stage1_result_13(reg_WfxrXtYt_1_13), + .weight_13(reg_Wfc_13), + .Ct_1_13(reg_Ct_1_13), + .bias_13(reg_bf_13), + .gate_output_13(o_forget_gate_13), + .stage1_result_14(reg_WfxrXtYt_1_14), + .weight_14(reg_Wfc_14), + .Ct_1_14(reg_Ct_1_14), + .bias_14(reg_bf_14), + .gate_output_14(o_forget_gate_14), + .stage1_result_15(reg_WfxrXtYt_1_15), + .weight_15(reg_Wfc_15), + .Ct_1_15(reg_Ct_1_15), + .bias_15(reg_bf_15), + .gate_output_15(o_forget_gate_15), + .stage1_result_16(reg_WfxrXtYt_1_16), + .weight_16(reg_Wfc_16), + .Ct_1_16(reg_Ct_1_16), + .bias_16(reg_bf_16), + .gate_output_16(o_forget_gate_16), + .stage1_result_17(reg_WfxrXtYt_1_17), + .weight_17(reg_Wfc_17), + .Ct_1_17(reg_Ct_1_17), + .bias_17(reg_bf_17), + .gate_output_17(o_forget_gate_17), + .stage1_result_18(reg_WfxrXtYt_1_18), + .weight_18(reg_Wfc_18), + .Ct_1_18(reg_Ct_1_18), + .bias_18(reg_bf_18), + .gate_output_18(o_forget_gate_18), + .stage1_result_19(reg_WfxrXtYt_1_19), + .weight_19(reg_Wfc_19), + .Ct_1_19(reg_Ct_1_19), + .bias_19(reg_bf_19), + .gate_output_19(o_forget_gate_19), + .stage1_result_20(reg_WfxrXtYt_1_20), + .weight_20(reg_Wfc_20), + .Ct_1_20(reg_Ct_1_20), + .bias_20(reg_bf_20), + .gate_output_20(o_forget_gate_20), + .stage1_result_21(reg_WfxrXtYt_1_21), + .weight_21(reg_Wfc_21), + .Ct_1_21(reg_Ct_1_21), + .bias_21(reg_bf_21), + .gate_output_21(o_forget_gate_21), + .stage1_result_22(reg_WfxrXtYt_1_22), + .weight_22(reg_Wfc_22), + .Ct_1_22(reg_Ct_1_22), + .bias_22(reg_bf_22), + .gate_output_22(o_forget_gate_22), + .stage1_result_23(reg_WfxrXtYt_1_23), + .weight_23(reg_Wfc_23), + .Ct_1_23(reg_Ct_1_23), + .bias_23(reg_bf_23), + .gate_output_23(o_forget_gate_23), + .stage1_result_24(reg_WfxrXtYt_1_24), + .weight_24(reg_Wfc_24), + .Ct_1_24(reg_Ct_1_24), + .bias_24(reg_bf_24), + .gate_output_24(o_forget_gate_24), + .stage1_result_25(reg_WfxrXtYt_1_25), + .weight_25(reg_Wfc_25), + .Ct_1_25(reg_Ct_1_25), + .bias_25(reg_bf_25), + .gate_output_25(o_forget_gate_25), + .stage1_result_26(reg_WfxrXtYt_1_26), + .weight_26(reg_Wfc_26), + .Ct_1_26(reg_Ct_1_26), + .bias_26(reg_bf_26), + .gate_output_26(o_forget_gate_26), + .stage1_result_27(reg_WfxrXtYt_1_27), + .weight_27(reg_Wfc_27), + .Ct_1_27(reg_Ct_1_27), + .bias_27(reg_bf_27), + .gate_output_27(o_forget_gate_27), + .stage1_result_28(reg_WfxrXtYt_1_28), + .weight_28(reg_Wfc_28), + .Ct_1_28(reg_Ct_1_28), + .bias_28(reg_bf_28), + .gate_output_28(o_forget_gate_28), + .stage1_result_29(reg_WfxrXtYt_1_29), + .weight_29(reg_Wfc_29), + .Ct_1_29(reg_Ct_1_29), + .bias_29(reg_bf_29), + .gate_output_29(o_forget_gate_29), + .stage1_result_30(reg_WfxrXtYt_1_30), + .weight_30(reg_Wfc_30), + .Ct_1_30(reg_Ct_1_30), + .bias_30(reg_bf_30), + .gate_output_30(o_forget_gate_30), + .stage1_result_31(reg_WfxrXtYt_1_31), + .weight_31(reg_Wfc_31), + .Ct_1_31(reg_Ct_1_31), + .bias_31(reg_bf_31), + .gate_output_31(o_forget_gate_31), + .stage1_result_32(reg_WfxrXtYt_1_32), + .weight_32(reg_Wfc_32), + .Ct_1_32(reg_Ct_1_32), + .bias_32(reg_bf_32), + .gate_output_32(o_forget_gate_32), + .stage1_result_33(reg_WfxrXtYt_1_33), + .weight_33(reg_Wfc_33), + .Ct_1_33(reg_Ct_1_33), + .bias_33(reg_bf_33), + .gate_output_33(o_forget_gate_33), + .stage1_result_34(reg_WfxrXtYt_1_34), + .weight_34(reg_Wfc_34), + .Ct_1_34(reg_Ct_1_34), + .bias_34(reg_bf_34), + .gate_output_34(o_forget_gate_34), + .stage1_result_35(reg_WfxrXtYt_1_35), + .weight_35(reg_Wfc_35), + .Ct_1_35(reg_Ct_1_35), + .bias_35(reg_bf_35), + .gate_output_35(o_forget_gate_35), + .stage1_result_36(reg_WfxrXtYt_1_36), + .weight_36(reg_Wfc_36), + .Ct_1_36(reg_Ct_1_36), + .bias_36(reg_bf_36), + .gate_output_36(o_forget_gate_36), + .stage1_result_37(reg_WfxrXtYt_1_37), + .weight_37(reg_Wfc_37), + .Ct_1_37(reg_Ct_1_37), + .bias_37(reg_bf_37), + .gate_output_37(o_forget_gate_37), + .stage1_result_38(reg_WfxrXtYt_1_38), + .weight_38(reg_Wfc_38), + .Ct_1_38(reg_Ct_1_38), + .bias_38(reg_bf_38), + .gate_output_38(o_forget_gate_38), + .stage1_result_39(reg_WfxrXtYt_1_39), + .weight_39(reg_Wfc_39), + .Ct_1_39(reg_Ct_1_39), + .bias_39(reg_bf_39), + .gate_output_39(o_forget_gate_39), + .stage1_result_40(reg_WfxrXtYt_1_40), + .weight_40(reg_Wfc_40), + .Ct_1_40(reg_Ct_1_40), + .bias_40(reg_bf_40), + .gate_output_40(o_forget_gate_40), + .stage1_result_41(reg_WfxrXtYt_1_41), + .weight_41(reg_Wfc_41), + .Ct_1_41(reg_Ct_1_41), + .bias_41(reg_bf_41), + .gate_output_41(o_forget_gate_41), + .stage1_result_42(reg_WfxrXtYt_1_42), + .weight_42(reg_Wfc_42), + .Ct_1_42(reg_Ct_1_42), + .bias_42(reg_bf_42), + .gate_output_42(o_forget_gate_42), + .stage1_result_43(reg_WfxrXtYt_1_43), + .weight_43(reg_Wfc_43), + .Ct_1_43(reg_Ct_1_43), + .bias_43(reg_bf_43), + .gate_output_43(o_forget_gate_43), + .stage1_result_44(reg_WfxrXtYt_1_44), + .weight_44(reg_Wfc_44), + .Ct_1_44(reg_Ct_1_44), + .bias_44(reg_bf_44), + .gate_output_44(o_forget_gate_44), + .stage1_result_45(reg_WfxrXtYt_1_45), + .weight_45(reg_Wfc_45), + .Ct_1_45(reg_Ct_1_45), + .bias_45(reg_bf_45), + .gate_output_45(o_forget_gate_45), + .stage1_result_46(reg_WfxrXtYt_1_46), + .weight_46(reg_Wfc_46), + .Ct_1_46(reg_Ct_1_46), + .bias_46(reg_bf_46), + .gate_output_46(o_forget_gate_46), + .stage1_result_47(reg_WfxrXtYt_1_47), + .weight_47(reg_Wfc_47), + .Ct_1_47(reg_Ct_1_47), + .bias_47(reg_bf_47), + .gate_output_47(o_forget_gate_47), + .o_valid(forget_gate_valid), + .o_ready() +); + +lstm_gate_18_10_48_1 lstm_gate_18_10_48_1_output ( + .clk(clk), + .reset(reset), + .i_ready(enable), + .i_valid(reg_i_valid), + .stage1_result_0(reg_WoxrXtYt_1_0), + .weight_0(reg_Woc_0), + .Ct_1_0(reg_Ct_1_0), + .bias_0(reg_bo_0), + .gate_output_0(o_output_gate_0), + .stage1_result_1(reg_WoxrXtYt_1_1), + .weight_1(reg_Woc_1), + .Ct_1_1(reg_Ct_1_1), + .bias_1(reg_bo_1), + .gate_output_1(o_output_gate_1), + .stage1_result_2(reg_WoxrXtYt_1_2), + .weight_2(reg_Woc_2), + .Ct_1_2(reg_Ct_1_2), + .bias_2(reg_bo_2), + .gate_output_2(o_output_gate_2), + .stage1_result_3(reg_WoxrXtYt_1_3), + .weight_3(reg_Woc_3), + .Ct_1_3(reg_Ct_1_3), + .bias_3(reg_bo_3), + .gate_output_3(o_output_gate_3), + .stage1_result_4(reg_WoxrXtYt_1_4), + .weight_4(reg_Woc_4), + .Ct_1_4(reg_Ct_1_4), + .bias_4(reg_bo_4), + .gate_output_4(o_output_gate_4), + .stage1_result_5(reg_WoxrXtYt_1_5), + .weight_5(reg_Woc_5), + .Ct_1_5(reg_Ct_1_5), + .bias_5(reg_bo_5), + .gate_output_5(o_output_gate_5), + .stage1_result_6(reg_WoxrXtYt_1_6), + .weight_6(reg_Woc_6), + .Ct_1_6(reg_Ct_1_6), + .bias_6(reg_bo_6), + .gate_output_6(o_output_gate_6), + .stage1_result_7(reg_WoxrXtYt_1_7), + .weight_7(reg_Woc_7), + .Ct_1_7(reg_Ct_1_7), + .bias_7(reg_bo_7), + .gate_output_7(o_output_gate_7), + .stage1_result_8(reg_WoxrXtYt_1_8), + .weight_8(reg_Woc_8), + .Ct_1_8(reg_Ct_1_8), + .bias_8(reg_bo_8), + .gate_output_8(o_output_gate_8), + .stage1_result_9(reg_WoxrXtYt_1_9), + .weight_9(reg_Woc_9), + .Ct_1_9(reg_Ct_1_9), + .bias_9(reg_bo_9), + .gate_output_9(o_output_gate_9), + .stage1_result_10(reg_WoxrXtYt_1_10), + .weight_10(reg_Woc_10), + .Ct_1_10(reg_Ct_1_10), + .bias_10(reg_bo_10), + .gate_output_10(o_output_gate_10), + .stage1_result_11(reg_WoxrXtYt_1_11), + .weight_11(reg_Woc_11), + .Ct_1_11(reg_Ct_1_11), + .bias_11(reg_bo_11), + .gate_output_11(o_output_gate_11), + .stage1_result_12(reg_WoxrXtYt_1_12), + .weight_12(reg_Woc_12), + .Ct_1_12(reg_Ct_1_12), + .bias_12(reg_bo_12), + .gate_output_12(o_output_gate_12), + .stage1_result_13(reg_WoxrXtYt_1_13), + .weight_13(reg_Woc_13), + .Ct_1_13(reg_Ct_1_13), + .bias_13(reg_bo_13), + .gate_output_13(o_output_gate_13), + .stage1_result_14(reg_WoxrXtYt_1_14), + .weight_14(reg_Woc_14), + .Ct_1_14(reg_Ct_1_14), + .bias_14(reg_bo_14), + .gate_output_14(o_output_gate_14), + .stage1_result_15(reg_WoxrXtYt_1_15), + .weight_15(reg_Woc_15), + .Ct_1_15(reg_Ct_1_15), + .bias_15(reg_bo_15), + .gate_output_15(o_output_gate_15), + .stage1_result_16(reg_WoxrXtYt_1_16), + .weight_16(reg_Woc_16), + .Ct_1_16(reg_Ct_1_16), + .bias_16(reg_bo_16), + .gate_output_16(o_output_gate_16), + .stage1_result_17(reg_WoxrXtYt_1_17), + .weight_17(reg_Woc_17), + .Ct_1_17(reg_Ct_1_17), + .bias_17(reg_bo_17), + .gate_output_17(o_output_gate_17), + .stage1_result_18(reg_WoxrXtYt_1_18), + .weight_18(reg_Woc_18), + .Ct_1_18(reg_Ct_1_18), + .bias_18(reg_bo_18), + .gate_output_18(o_output_gate_18), + .stage1_result_19(reg_WoxrXtYt_1_19), + .weight_19(reg_Woc_19), + .Ct_1_19(reg_Ct_1_19), + .bias_19(reg_bo_19), + .gate_output_19(o_output_gate_19), + .stage1_result_20(reg_WoxrXtYt_1_20), + .weight_20(reg_Woc_20), + .Ct_1_20(reg_Ct_1_20), + .bias_20(reg_bo_20), + .gate_output_20(o_output_gate_20), + .stage1_result_21(reg_WoxrXtYt_1_21), + .weight_21(reg_Woc_21), + .Ct_1_21(reg_Ct_1_21), + .bias_21(reg_bo_21), + .gate_output_21(o_output_gate_21), + .stage1_result_22(reg_WoxrXtYt_1_22), + .weight_22(reg_Woc_22), + .Ct_1_22(reg_Ct_1_22), + .bias_22(reg_bo_22), + .gate_output_22(o_output_gate_22), + .stage1_result_23(reg_WoxrXtYt_1_23), + .weight_23(reg_Woc_23), + .Ct_1_23(reg_Ct_1_23), + .bias_23(reg_bo_23), + .gate_output_23(o_output_gate_23), + .stage1_result_24(reg_WoxrXtYt_1_24), + .weight_24(reg_Woc_24), + .Ct_1_24(reg_Ct_1_24), + .bias_24(reg_bo_24), + .gate_output_24(o_output_gate_24), + .stage1_result_25(reg_WoxrXtYt_1_25), + .weight_25(reg_Woc_25), + .Ct_1_25(reg_Ct_1_25), + .bias_25(reg_bo_25), + .gate_output_25(o_output_gate_25), + .stage1_result_26(reg_WoxrXtYt_1_26), + .weight_26(reg_Woc_26), + .Ct_1_26(reg_Ct_1_26), + .bias_26(reg_bo_26), + .gate_output_26(o_output_gate_26), + .stage1_result_27(reg_WoxrXtYt_1_27), + .weight_27(reg_Woc_27), + .Ct_1_27(reg_Ct_1_27), + .bias_27(reg_bo_27), + .gate_output_27(o_output_gate_27), + .stage1_result_28(reg_WoxrXtYt_1_28), + .weight_28(reg_Woc_28), + .Ct_1_28(reg_Ct_1_28), + .bias_28(reg_bo_28), + .gate_output_28(o_output_gate_28), + .stage1_result_29(reg_WoxrXtYt_1_29), + .weight_29(reg_Woc_29), + .Ct_1_29(reg_Ct_1_29), + .bias_29(reg_bo_29), + .gate_output_29(o_output_gate_29), + .stage1_result_30(reg_WoxrXtYt_1_30), + .weight_30(reg_Woc_30), + .Ct_1_30(reg_Ct_1_30), + .bias_30(reg_bo_30), + .gate_output_30(o_output_gate_30), + .stage1_result_31(reg_WoxrXtYt_1_31), + .weight_31(reg_Woc_31), + .Ct_1_31(reg_Ct_1_31), + .bias_31(reg_bo_31), + .gate_output_31(o_output_gate_31), + .stage1_result_32(reg_WoxrXtYt_1_32), + .weight_32(reg_Woc_32), + .Ct_1_32(reg_Ct_1_32), + .bias_32(reg_bo_32), + .gate_output_32(o_output_gate_32), + .stage1_result_33(reg_WoxrXtYt_1_33), + .weight_33(reg_Woc_33), + .Ct_1_33(reg_Ct_1_33), + .bias_33(reg_bo_33), + .gate_output_33(o_output_gate_33), + .stage1_result_34(reg_WoxrXtYt_1_34), + .weight_34(reg_Woc_34), + .Ct_1_34(reg_Ct_1_34), + .bias_34(reg_bo_34), + .gate_output_34(o_output_gate_34), + .stage1_result_35(reg_WoxrXtYt_1_35), + .weight_35(reg_Woc_35), + .Ct_1_35(reg_Ct_1_35), + .bias_35(reg_bo_35), + .gate_output_35(o_output_gate_35), + .stage1_result_36(reg_WoxrXtYt_1_36), + .weight_36(reg_Woc_36), + .Ct_1_36(reg_Ct_1_36), + .bias_36(reg_bo_36), + .gate_output_36(o_output_gate_36), + .stage1_result_37(reg_WoxrXtYt_1_37), + .weight_37(reg_Woc_37), + .Ct_1_37(reg_Ct_1_37), + .bias_37(reg_bo_37), + .gate_output_37(o_output_gate_37), + .stage1_result_38(reg_WoxrXtYt_1_38), + .weight_38(reg_Woc_38), + .Ct_1_38(reg_Ct_1_38), + .bias_38(reg_bo_38), + .gate_output_38(o_output_gate_38), + .stage1_result_39(reg_WoxrXtYt_1_39), + .weight_39(reg_Woc_39), + .Ct_1_39(reg_Ct_1_39), + .bias_39(reg_bo_39), + .gate_output_39(o_output_gate_39), + .stage1_result_40(reg_WoxrXtYt_1_40), + .weight_40(reg_Woc_40), + .Ct_1_40(reg_Ct_1_40), + .bias_40(reg_bo_40), + .gate_output_40(o_output_gate_40), + .stage1_result_41(reg_WoxrXtYt_1_41), + .weight_41(reg_Woc_41), + .Ct_1_41(reg_Ct_1_41), + .bias_41(reg_bo_41), + .gate_output_41(o_output_gate_41), + .stage1_result_42(reg_WoxrXtYt_1_42), + .weight_42(reg_Woc_42), + .Ct_1_42(reg_Ct_1_42), + .bias_42(reg_bo_42), + .gate_output_42(o_output_gate_42), + .stage1_result_43(reg_WoxrXtYt_1_43), + .weight_43(reg_Woc_43), + .Ct_1_43(reg_Ct_1_43), + .bias_43(reg_bo_43), + .gate_output_43(o_output_gate_43), + .stage1_result_44(reg_WoxrXtYt_1_44), + .weight_44(reg_Woc_44), + .Ct_1_44(reg_Ct_1_44), + .bias_44(reg_bo_44), + .gate_output_44(o_output_gate_44), + .stage1_result_45(reg_WoxrXtYt_1_45), + .weight_45(reg_Woc_45), + .Ct_1_45(reg_Ct_1_45), + .bias_45(reg_bo_45), + .gate_output_45(o_output_gate_45), + .stage1_result_46(reg_WoxrXtYt_1_46), + .weight_46(reg_Woc_46), + .Ct_1_46(reg_Ct_1_46), + .bias_46(reg_bo_46), + .gate_output_46(o_output_gate_46), + .stage1_result_47(reg_WoxrXtYt_1_47), + .weight_47(reg_Woc_47), + .Ct_1_47(reg_Ct_1_47), + .bias_47(reg_bo_47), + .gate_output_47(o_output_gate_47), + .o_valid(output_gate_valid), + .o_ready() +); + +output_activation_18_10_48_1 output_activation_18_10_48_1_inst_rvjwnsyybt ( + .clk(clk), + .reset(reset), + .i_ready(enable), + .i_valid(reg_i_valid), + .stage1_result_0(reg_WcxrXtYt_1_0), + .bias_0(reg_bc_0), + .output_value_0(o_gt_0), + .stage1_result_1(reg_WcxrXtYt_1_1), + .bias_1(reg_bc_1), + .output_value_1(o_gt_1), + .stage1_result_2(reg_WcxrXtYt_1_2), + .bias_2(reg_bc_2), + .output_value_2(o_gt_2), + .stage1_result_3(reg_WcxrXtYt_1_3), + .bias_3(reg_bc_3), + .output_value_3(o_gt_3), + .stage1_result_4(reg_WcxrXtYt_1_4), + .bias_4(reg_bc_4), + .output_value_4(o_gt_4), + .stage1_result_5(reg_WcxrXtYt_1_5), + .bias_5(reg_bc_5), + .output_value_5(o_gt_5), + .stage1_result_6(reg_WcxrXtYt_1_6), + .bias_6(reg_bc_6), + .output_value_6(o_gt_6), + .stage1_result_7(reg_WcxrXtYt_1_7), + .bias_7(reg_bc_7), + .output_value_7(o_gt_7), + .stage1_result_8(reg_WcxrXtYt_1_8), + .bias_8(reg_bc_8), + .output_value_8(o_gt_8), + .stage1_result_9(reg_WcxrXtYt_1_9), + .bias_9(reg_bc_9), + .output_value_9(o_gt_9), + .stage1_result_10(reg_WcxrXtYt_1_10), + .bias_10(reg_bc_10), + .output_value_10(o_gt_10), + .stage1_result_11(reg_WcxrXtYt_1_11), + .bias_11(reg_bc_11), + .output_value_11(o_gt_11), + .stage1_result_12(reg_WcxrXtYt_1_12), + .bias_12(reg_bc_12), + .output_value_12(o_gt_12), + .stage1_result_13(reg_WcxrXtYt_1_13), + .bias_13(reg_bc_13), + .output_value_13(o_gt_13), + .stage1_result_14(reg_WcxrXtYt_1_14), + .bias_14(reg_bc_14), + .output_value_14(o_gt_14), + .stage1_result_15(reg_WcxrXtYt_1_15), + .bias_15(reg_bc_15), + .output_value_15(o_gt_15), + .stage1_result_16(reg_WcxrXtYt_1_16), + .bias_16(reg_bc_16), + .output_value_16(o_gt_16), + .stage1_result_17(reg_WcxrXtYt_1_17), + .bias_17(reg_bc_17), + .output_value_17(o_gt_17), + .stage1_result_18(reg_WcxrXtYt_1_18), + .bias_18(reg_bc_18), + .output_value_18(o_gt_18), + .stage1_result_19(reg_WcxrXtYt_1_19), + .bias_19(reg_bc_19), + .output_value_19(o_gt_19), + .stage1_result_20(reg_WcxrXtYt_1_20), + .bias_20(reg_bc_20), + .output_value_20(o_gt_20), + .stage1_result_21(reg_WcxrXtYt_1_21), + .bias_21(reg_bc_21), + .output_value_21(o_gt_21), + .stage1_result_22(reg_WcxrXtYt_1_22), + .bias_22(reg_bc_22), + .output_value_22(o_gt_22), + .stage1_result_23(reg_WcxrXtYt_1_23), + .bias_23(reg_bc_23), + .output_value_23(o_gt_23), + .stage1_result_24(reg_WcxrXtYt_1_24), + .bias_24(reg_bc_24), + .output_value_24(o_gt_24), + .stage1_result_25(reg_WcxrXtYt_1_25), + .bias_25(reg_bc_25), + .output_value_25(o_gt_25), + .stage1_result_26(reg_WcxrXtYt_1_26), + .bias_26(reg_bc_26), + .output_value_26(o_gt_26), + .stage1_result_27(reg_WcxrXtYt_1_27), + .bias_27(reg_bc_27), + .output_value_27(o_gt_27), + .stage1_result_28(reg_WcxrXtYt_1_28), + .bias_28(reg_bc_28), + .output_value_28(o_gt_28), + .stage1_result_29(reg_WcxrXtYt_1_29), + .bias_29(reg_bc_29), + .output_value_29(o_gt_29), + .stage1_result_30(reg_WcxrXtYt_1_30), + .bias_30(reg_bc_30), + .output_value_30(o_gt_30), + .stage1_result_31(reg_WcxrXtYt_1_31), + .bias_31(reg_bc_31), + .output_value_31(o_gt_31), + .stage1_result_32(reg_WcxrXtYt_1_32), + .bias_32(reg_bc_32), + .output_value_32(o_gt_32), + .stage1_result_33(reg_WcxrXtYt_1_33), + .bias_33(reg_bc_33), + .output_value_33(o_gt_33), + .stage1_result_34(reg_WcxrXtYt_1_34), + .bias_34(reg_bc_34), + .output_value_34(o_gt_34), + .stage1_result_35(reg_WcxrXtYt_1_35), + .bias_35(reg_bc_35), + .output_value_35(o_gt_35), + .stage1_result_36(reg_WcxrXtYt_1_36), + .bias_36(reg_bc_36), + .output_value_36(o_gt_36), + .stage1_result_37(reg_WcxrXtYt_1_37), + .bias_37(reg_bc_37), + .output_value_37(o_gt_37), + .stage1_result_38(reg_WcxrXtYt_1_38), + .bias_38(reg_bc_38), + .output_value_38(o_gt_38), + .stage1_result_39(reg_WcxrXtYt_1_39), + .bias_39(reg_bc_39), + .output_value_39(o_gt_39), + .stage1_result_40(reg_WcxrXtYt_1_40), + .bias_40(reg_bc_40), + .output_value_40(o_gt_40), + .stage1_result_41(reg_WcxrXtYt_1_41), + .bias_41(reg_bc_41), + .output_value_41(o_gt_41), + .stage1_result_42(reg_WcxrXtYt_1_42), + .bias_42(reg_bc_42), + .output_value_42(o_gt_42), + .stage1_result_43(reg_WcxrXtYt_1_43), + .bias_43(reg_bc_43), + .output_value_43(o_gt_43), + .stage1_result_44(reg_WcxrXtYt_1_44), + .bias_44(reg_bc_44), + .output_value_44(o_gt_44), + .stage1_result_45(reg_WcxrXtYt_1_45), + .bias_45(reg_bc_45), + .output_value_45(o_gt_45), + .stage1_result_46(reg_WcxrXtYt_1_46), + .bias_46(reg_bc_46), + .output_value_46(o_gt_46), + .stage1_result_47(reg_WcxrXtYt_1_47), + .bias_47(reg_bc_47), + .output_value_47(o_gt_47), + .o_valid(gt_valid), + .o_ready() +); + +shift_register_group_18_48_6 shift_register_group_18_48_6_eltwisemult ( + .clk(clk), + .enable(enable), + .in_0(o_gt_0), + .out_0(gt_hold_0), + .in_1(o_gt_1), + .out_1(gt_hold_1), + .in_2(o_gt_2), + .out_2(gt_hold_2), + .in_3(o_gt_3), + .out_3(gt_hold_3), + .in_4(o_gt_4), + .out_4(gt_hold_4), + .in_5(o_gt_5), + .out_5(gt_hold_5), + .in_6(o_gt_6), + .out_6(gt_hold_6), + .in_7(o_gt_7), + .out_7(gt_hold_7), + .in_8(o_gt_8), + .out_8(gt_hold_8), + .in_9(o_gt_9), + .out_9(gt_hold_9), + .in_10(o_gt_10), + .out_10(gt_hold_10), + .in_11(o_gt_11), + .out_11(gt_hold_11), + .in_12(o_gt_12), + .out_12(gt_hold_12), + .in_13(o_gt_13), + .out_13(gt_hold_13), + .in_14(o_gt_14), + .out_14(gt_hold_14), + .in_15(o_gt_15), + .out_15(gt_hold_15), + .in_16(o_gt_16), + .out_16(gt_hold_16), + .in_17(o_gt_17), + .out_17(gt_hold_17), + .in_18(o_gt_18), + .out_18(gt_hold_18), + .in_19(o_gt_19), + .out_19(gt_hold_19), + .in_20(o_gt_20), + .out_20(gt_hold_20), + .in_21(o_gt_21), + .out_21(gt_hold_21), + .in_22(o_gt_22), + .out_22(gt_hold_22), + .in_23(o_gt_23), + .out_23(gt_hold_23), + .in_24(o_gt_24), + .out_24(gt_hold_24), + .in_25(o_gt_25), + .out_25(gt_hold_25), + .in_26(o_gt_26), + .out_26(gt_hold_26), + .in_27(o_gt_27), + .out_27(gt_hold_27), + .in_28(o_gt_28), + .out_28(gt_hold_28), + .in_29(o_gt_29), + .out_29(gt_hold_29), + .in_30(o_gt_30), + .out_30(gt_hold_30), + .in_31(o_gt_31), + .out_31(gt_hold_31), + .in_32(o_gt_32), + .out_32(gt_hold_32), + .in_33(o_gt_33), + .out_33(gt_hold_33), + .in_34(o_gt_34), + .out_34(gt_hold_34), + .in_35(o_gt_35), + .out_35(gt_hold_35), + .in_36(o_gt_36), + .out_36(gt_hold_36), + .in_37(o_gt_37), + .out_37(gt_hold_37), + .in_38(o_gt_38), + .out_38(gt_hold_38), + .in_39(o_gt_39), + .out_39(gt_hold_39), + .in_40(o_gt_40), + .out_40(gt_hold_40), + .in_41(o_gt_41), + .out_41(gt_hold_41), + .in_42(o_gt_42), + .out_42(gt_hold_42), + .in_43(o_gt_43), + .out_43(gt_hold_43), + .in_44(o_gt_44), + .out_44(gt_hold_44), + .in_45(o_gt_45), + .out_45(gt_hold_45), + .in_46(o_gt_46), + .out_46(gt_hold_46), + .in_47(o_gt_47), + .out_47(gt_hold_47), + .reset(reset) +); + +elementwise_mult_core_18_18_10_48_1 elementwise_mult_core_18_18_10_48_1_it_gt_mult ( + .clk(clk), + .reset(reset), + .i_valid(forget_gate_valid), + .i_ready(enable), + .i_A_0(o_input_gate_0), + .i_B_0(gt_hold_0), + .o_C_0(o_it_gt_mult_0), + .i_A_1(o_input_gate_1), + .i_B_1(gt_hold_1), + .o_C_1(o_it_gt_mult_1), + .i_A_2(o_input_gate_2), + .i_B_2(gt_hold_2), + .o_C_2(o_it_gt_mult_2), + .i_A_3(o_input_gate_3), + .i_B_3(gt_hold_3), + .o_C_3(o_it_gt_mult_3), + .i_A_4(o_input_gate_4), + .i_B_4(gt_hold_4), + .o_C_4(o_it_gt_mult_4), + .i_A_5(o_input_gate_5), + .i_B_5(gt_hold_5), + .o_C_5(o_it_gt_mult_5), + .i_A_6(o_input_gate_6), + .i_B_6(gt_hold_6), + .o_C_6(o_it_gt_mult_6), + .i_A_7(o_input_gate_7), + .i_B_7(gt_hold_7), + .o_C_7(o_it_gt_mult_7), + .i_A_8(o_input_gate_8), + .i_B_8(gt_hold_8), + .o_C_8(o_it_gt_mult_8), + .i_A_9(o_input_gate_9), + .i_B_9(gt_hold_9), + .o_C_9(o_it_gt_mult_9), + .i_A_10(o_input_gate_10), + .i_B_10(gt_hold_10), + .o_C_10(o_it_gt_mult_10), + .i_A_11(o_input_gate_11), + .i_B_11(gt_hold_11), + .o_C_11(o_it_gt_mult_11), + .i_A_12(o_input_gate_12), + .i_B_12(gt_hold_12), + .o_C_12(o_it_gt_mult_12), + .i_A_13(o_input_gate_13), + .i_B_13(gt_hold_13), + .o_C_13(o_it_gt_mult_13), + .i_A_14(o_input_gate_14), + .i_B_14(gt_hold_14), + .o_C_14(o_it_gt_mult_14), + .i_A_15(o_input_gate_15), + .i_B_15(gt_hold_15), + .o_C_15(o_it_gt_mult_15), + .i_A_16(o_input_gate_16), + .i_B_16(gt_hold_16), + .o_C_16(o_it_gt_mult_16), + .i_A_17(o_input_gate_17), + .i_B_17(gt_hold_17), + .o_C_17(o_it_gt_mult_17), + .i_A_18(o_input_gate_18), + .i_B_18(gt_hold_18), + .o_C_18(o_it_gt_mult_18), + .i_A_19(o_input_gate_19), + .i_B_19(gt_hold_19), + .o_C_19(o_it_gt_mult_19), + .i_A_20(o_input_gate_20), + .i_B_20(gt_hold_20), + .o_C_20(o_it_gt_mult_20), + .i_A_21(o_input_gate_21), + .i_B_21(gt_hold_21), + .o_C_21(o_it_gt_mult_21), + .i_A_22(o_input_gate_22), + .i_B_22(gt_hold_22), + .o_C_22(o_it_gt_mult_22), + .i_A_23(o_input_gate_23), + .i_B_23(gt_hold_23), + .o_C_23(o_it_gt_mult_23), + .i_A_24(o_input_gate_24), + .i_B_24(gt_hold_24), + .o_C_24(o_it_gt_mult_24), + .i_A_25(o_input_gate_25), + .i_B_25(gt_hold_25), + .o_C_25(o_it_gt_mult_25), + .i_A_26(o_input_gate_26), + .i_B_26(gt_hold_26), + .o_C_26(o_it_gt_mult_26), + .i_A_27(o_input_gate_27), + .i_B_27(gt_hold_27), + .o_C_27(o_it_gt_mult_27), + .i_A_28(o_input_gate_28), + .i_B_28(gt_hold_28), + .o_C_28(o_it_gt_mult_28), + .i_A_29(o_input_gate_29), + .i_B_29(gt_hold_29), + .o_C_29(o_it_gt_mult_29), + .i_A_30(o_input_gate_30), + .i_B_30(gt_hold_30), + .o_C_30(o_it_gt_mult_30), + .i_A_31(o_input_gate_31), + .i_B_31(gt_hold_31), + .o_C_31(o_it_gt_mult_31), + .i_A_32(o_input_gate_32), + .i_B_32(gt_hold_32), + .o_C_32(o_it_gt_mult_32), + .i_A_33(o_input_gate_33), + .i_B_33(gt_hold_33), + .o_C_33(o_it_gt_mult_33), + .i_A_34(o_input_gate_34), + .i_B_34(gt_hold_34), + .o_C_34(o_it_gt_mult_34), + .i_A_35(o_input_gate_35), + .i_B_35(gt_hold_35), + .o_C_35(o_it_gt_mult_35), + .i_A_36(o_input_gate_36), + .i_B_36(gt_hold_36), + .o_C_36(o_it_gt_mult_36), + .i_A_37(o_input_gate_37), + .i_B_37(gt_hold_37), + .o_C_37(o_it_gt_mult_37), + .i_A_38(o_input_gate_38), + .i_B_38(gt_hold_38), + .o_C_38(o_it_gt_mult_38), + .i_A_39(o_input_gate_39), + .i_B_39(gt_hold_39), + .o_C_39(o_it_gt_mult_39), + .i_A_40(o_input_gate_40), + .i_B_40(gt_hold_40), + .o_C_40(o_it_gt_mult_40), + .i_A_41(o_input_gate_41), + .i_B_41(gt_hold_41), + .o_C_41(o_it_gt_mult_41), + .i_A_42(o_input_gate_42), + .i_B_42(gt_hold_42), + .o_C_42(o_it_gt_mult_42), + .i_A_43(o_input_gate_43), + .i_B_43(gt_hold_43), + .o_C_43(o_it_gt_mult_43), + .i_A_44(o_input_gate_44), + .i_B_44(gt_hold_44), + .o_C_44(o_it_gt_mult_44), + .i_A_45(o_input_gate_45), + .i_B_45(gt_hold_45), + .o_C_45(o_it_gt_mult_45), + .i_A_46(o_input_gate_46), + .i_B_46(gt_hold_46), + .o_C_46(o_it_gt_mult_46), + .i_A_47(o_input_gate_47), + .i_B_47(gt_hold_47), + .o_C_47(o_it_gt_mult_47), + .o_valid(it_gt_mult_valid), + .o_ready() +); + +shift_register_group_18_48_18 shift_register_group_18_48_18_lstm_gate ( + .clk(clk), + .enable(enable), + .in_0(o_Ct_1_0), + .out_0(Ct_1_hold_0), + .in_1(o_Ct_1_1), + .out_1(Ct_1_hold_1), + .in_2(o_Ct_1_2), + .out_2(Ct_1_hold_2), + .in_3(o_Ct_1_3), + .out_3(Ct_1_hold_3), + .in_4(o_Ct_1_4), + .out_4(Ct_1_hold_4), + .in_5(o_Ct_1_5), + .out_5(Ct_1_hold_5), + .in_6(o_Ct_1_6), + .out_6(Ct_1_hold_6), + .in_7(o_Ct_1_7), + .out_7(Ct_1_hold_7), + .in_8(o_Ct_1_8), + .out_8(Ct_1_hold_8), + .in_9(o_Ct_1_9), + .out_9(Ct_1_hold_9), + .in_10(o_Ct_1_10), + .out_10(Ct_1_hold_10), + .in_11(o_Ct_1_11), + .out_11(Ct_1_hold_11), + .in_12(o_Ct_1_12), + .out_12(Ct_1_hold_12), + .in_13(o_Ct_1_13), + .out_13(Ct_1_hold_13), + .in_14(o_Ct_1_14), + .out_14(Ct_1_hold_14), + .in_15(o_Ct_1_15), + .out_15(Ct_1_hold_15), + .in_16(o_Ct_1_16), + .out_16(Ct_1_hold_16), + .in_17(o_Ct_1_17), + .out_17(Ct_1_hold_17), + .in_18(o_Ct_1_18), + .out_18(Ct_1_hold_18), + .in_19(o_Ct_1_19), + .out_19(Ct_1_hold_19), + .in_20(o_Ct_1_20), + .out_20(Ct_1_hold_20), + .in_21(o_Ct_1_21), + .out_21(Ct_1_hold_21), + .in_22(o_Ct_1_22), + .out_22(Ct_1_hold_22), + .in_23(o_Ct_1_23), + .out_23(Ct_1_hold_23), + .in_24(o_Ct_1_24), + .out_24(Ct_1_hold_24), + .in_25(o_Ct_1_25), + .out_25(Ct_1_hold_25), + .in_26(o_Ct_1_26), + .out_26(Ct_1_hold_26), + .in_27(o_Ct_1_27), + .out_27(Ct_1_hold_27), + .in_28(o_Ct_1_28), + .out_28(Ct_1_hold_28), + .in_29(o_Ct_1_29), + .out_29(Ct_1_hold_29), + .in_30(o_Ct_1_30), + .out_30(Ct_1_hold_30), + .in_31(o_Ct_1_31), + .out_31(Ct_1_hold_31), + .in_32(o_Ct_1_32), + .out_32(Ct_1_hold_32), + .in_33(o_Ct_1_33), + .out_33(Ct_1_hold_33), + .in_34(o_Ct_1_34), + .out_34(Ct_1_hold_34), + .in_35(o_Ct_1_35), + .out_35(Ct_1_hold_35), + .in_36(o_Ct_1_36), + .out_36(Ct_1_hold_36), + .in_37(o_Ct_1_37), + .out_37(Ct_1_hold_37), + .in_38(o_Ct_1_38), + .out_38(Ct_1_hold_38), + .in_39(o_Ct_1_39), + .out_39(Ct_1_hold_39), + .in_40(o_Ct_1_40), + .out_40(Ct_1_hold_40), + .in_41(o_Ct_1_41), + .out_41(Ct_1_hold_41), + .in_42(o_Ct_1_42), + .out_42(Ct_1_hold_42), + .in_43(o_Ct_1_43), + .out_43(Ct_1_hold_43), + .in_44(o_Ct_1_44), + .out_44(Ct_1_hold_44), + .in_45(o_Ct_1_45), + .out_45(Ct_1_hold_45), + .in_46(o_Ct_1_46), + .out_46(Ct_1_hold_46), + .in_47(o_Ct_1_47), + .out_47(Ct_1_hold_47), + .reset(reset) +); + +elementwise_mult_core_18_18_10_48_1 elementwise_mult_core_18_18_10_48_1_ft_Ct_1_mult ( + .clk(clk), + .reset(reset), + .i_valid(forget_gate_valid), + .i_ready(enable), + .i_A_0(Ct_1_hold_0), + .i_B_0(o_forget_gate_0), + .o_C_0(o_ft_Ct_1_mult_0), + .i_A_1(Ct_1_hold_1), + .i_B_1(o_forget_gate_1), + .o_C_1(o_ft_Ct_1_mult_1), + .i_A_2(Ct_1_hold_2), + .i_B_2(o_forget_gate_2), + .o_C_2(o_ft_Ct_1_mult_2), + .i_A_3(Ct_1_hold_3), + .i_B_3(o_forget_gate_3), + .o_C_3(o_ft_Ct_1_mult_3), + .i_A_4(Ct_1_hold_4), + .i_B_4(o_forget_gate_4), + .o_C_4(o_ft_Ct_1_mult_4), + .i_A_5(Ct_1_hold_5), + .i_B_5(o_forget_gate_5), + .o_C_5(o_ft_Ct_1_mult_5), + .i_A_6(Ct_1_hold_6), + .i_B_6(o_forget_gate_6), + .o_C_6(o_ft_Ct_1_mult_6), + .i_A_7(Ct_1_hold_7), + .i_B_7(o_forget_gate_7), + .o_C_7(o_ft_Ct_1_mult_7), + .i_A_8(Ct_1_hold_8), + .i_B_8(o_forget_gate_8), + .o_C_8(o_ft_Ct_1_mult_8), + .i_A_9(Ct_1_hold_9), + .i_B_9(o_forget_gate_9), + .o_C_9(o_ft_Ct_1_mult_9), + .i_A_10(Ct_1_hold_10), + .i_B_10(o_forget_gate_10), + .o_C_10(o_ft_Ct_1_mult_10), + .i_A_11(Ct_1_hold_11), + .i_B_11(o_forget_gate_11), + .o_C_11(o_ft_Ct_1_mult_11), + .i_A_12(Ct_1_hold_12), + .i_B_12(o_forget_gate_12), + .o_C_12(o_ft_Ct_1_mult_12), + .i_A_13(Ct_1_hold_13), + .i_B_13(o_forget_gate_13), + .o_C_13(o_ft_Ct_1_mult_13), + .i_A_14(Ct_1_hold_14), + .i_B_14(o_forget_gate_14), + .o_C_14(o_ft_Ct_1_mult_14), + .i_A_15(Ct_1_hold_15), + .i_B_15(o_forget_gate_15), + .o_C_15(o_ft_Ct_1_mult_15), + .i_A_16(Ct_1_hold_16), + .i_B_16(o_forget_gate_16), + .o_C_16(o_ft_Ct_1_mult_16), + .i_A_17(Ct_1_hold_17), + .i_B_17(o_forget_gate_17), + .o_C_17(o_ft_Ct_1_mult_17), + .i_A_18(Ct_1_hold_18), + .i_B_18(o_forget_gate_18), + .o_C_18(o_ft_Ct_1_mult_18), + .i_A_19(Ct_1_hold_19), + .i_B_19(o_forget_gate_19), + .o_C_19(o_ft_Ct_1_mult_19), + .i_A_20(Ct_1_hold_20), + .i_B_20(o_forget_gate_20), + .o_C_20(o_ft_Ct_1_mult_20), + .i_A_21(Ct_1_hold_21), + .i_B_21(o_forget_gate_21), + .o_C_21(o_ft_Ct_1_mult_21), + .i_A_22(Ct_1_hold_22), + .i_B_22(o_forget_gate_22), + .o_C_22(o_ft_Ct_1_mult_22), + .i_A_23(Ct_1_hold_23), + .i_B_23(o_forget_gate_23), + .o_C_23(o_ft_Ct_1_mult_23), + .i_A_24(Ct_1_hold_24), + .i_B_24(o_forget_gate_24), + .o_C_24(o_ft_Ct_1_mult_24), + .i_A_25(Ct_1_hold_25), + .i_B_25(o_forget_gate_25), + .o_C_25(o_ft_Ct_1_mult_25), + .i_A_26(Ct_1_hold_26), + .i_B_26(o_forget_gate_26), + .o_C_26(o_ft_Ct_1_mult_26), + .i_A_27(Ct_1_hold_27), + .i_B_27(o_forget_gate_27), + .o_C_27(o_ft_Ct_1_mult_27), + .i_A_28(Ct_1_hold_28), + .i_B_28(o_forget_gate_28), + .o_C_28(o_ft_Ct_1_mult_28), + .i_A_29(Ct_1_hold_29), + .i_B_29(o_forget_gate_29), + .o_C_29(o_ft_Ct_1_mult_29), + .i_A_30(Ct_1_hold_30), + .i_B_30(o_forget_gate_30), + .o_C_30(o_ft_Ct_1_mult_30), + .i_A_31(Ct_1_hold_31), + .i_B_31(o_forget_gate_31), + .o_C_31(o_ft_Ct_1_mult_31), + .i_A_32(Ct_1_hold_32), + .i_B_32(o_forget_gate_32), + .o_C_32(o_ft_Ct_1_mult_32), + .i_A_33(Ct_1_hold_33), + .i_B_33(o_forget_gate_33), + .o_C_33(o_ft_Ct_1_mult_33), + .i_A_34(Ct_1_hold_34), + .i_B_34(o_forget_gate_34), + .o_C_34(o_ft_Ct_1_mult_34), + .i_A_35(Ct_1_hold_35), + .i_B_35(o_forget_gate_35), + .o_C_35(o_ft_Ct_1_mult_35), + .i_A_36(Ct_1_hold_36), + .i_B_36(o_forget_gate_36), + .o_C_36(o_ft_Ct_1_mult_36), + .i_A_37(Ct_1_hold_37), + .i_B_37(o_forget_gate_37), + .o_C_37(o_ft_Ct_1_mult_37), + .i_A_38(Ct_1_hold_38), + .i_B_38(o_forget_gate_38), + .o_C_38(o_ft_Ct_1_mult_38), + .i_A_39(Ct_1_hold_39), + .i_B_39(o_forget_gate_39), + .o_C_39(o_ft_Ct_1_mult_39), + .i_A_40(Ct_1_hold_40), + .i_B_40(o_forget_gate_40), + .o_C_40(o_ft_Ct_1_mult_40), + .i_A_41(Ct_1_hold_41), + .i_B_41(o_forget_gate_41), + .o_C_41(o_ft_Ct_1_mult_41), + .i_A_42(Ct_1_hold_42), + .i_B_42(o_forget_gate_42), + .o_C_42(o_ft_Ct_1_mult_42), + .i_A_43(Ct_1_hold_43), + .i_B_43(o_forget_gate_43), + .o_C_43(o_ft_Ct_1_mult_43), + .i_A_44(Ct_1_hold_44), + .i_B_44(o_forget_gate_44), + .o_C_44(o_ft_Ct_1_mult_44), + .i_A_45(Ct_1_hold_45), + .i_B_45(o_forget_gate_45), + .o_C_45(o_ft_Ct_1_mult_45), + .i_A_46(Ct_1_hold_46), + .i_B_46(o_forget_gate_46), + .o_C_46(o_ft_Ct_1_mult_46), + .i_A_47(Ct_1_hold_47), + .i_B_47(o_forget_gate_47), + .o_C_47(o_ft_Ct_1_mult_47), + .o_valid(ft_Ct_1_mult_valid), + .o_ready() +); + +wire eltwise_add_core_valid; +assign eltwise_add_core_valid = ft_Ct_1_mult_valid & it_gt_mult_valid; + +elementwise_add_core_18_18_48 elementwise_add_core_18_18_48_inst_unfcofcxas ( + .clk(clk), + .reset(reset), + .i_valid(eltwise_add_core_valid), + .i_ready(enable), + .i_A_0(o_it_gt_mult_0), + .i_B_0(o_ft_Ct_1_mult_0), + .o_C_0(o_ct_0), + .i_A_1(o_it_gt_mult_1), + .i_B_1(o_ft_Ct_1_mult_1), + .o_C_1(o_ct_1), + .i_A_2(o_it_gt_mult_2), + .i_B_2(o_ft_Ct_1_mult_2), + .o_C_2(o_ct_2), + .i_A_3(o_it_gt_mult_3), + .i_B_3(o_ft_Ct_1_mult_3), + .o_C_3(o_ct_3), + .i_A_4(o_it_gt_mult_4), + .i_B_4(o_ft_Ct_1_mult_4), + .o_C_4(o_ct_4), + .i_A_5(o_it_gt_mult_5), + .i_B_5(o_ft_Ct_1_mult_5), + .o_C_5(o_ct_5), + .i_A_6(o_it_gt_mult_6), + .i_B_6(o_ft_Ct_1_mult_6), + .o_C_6(o_ct_6), + .i_A_7(o_it_gt_mult_7), + .i_B_7(o_ft_Ct_1_mult_7), + .o_C_7(o_ct_7), + .i_A_8(o_it_gt_mult_8), + .i_B_8(o_ft_Ct_1_mult_8), + .o_C_8(o_ct_8), + .i_A_9(o_it_gt_mult_9), + .i_B_9(o_ft_Ct_1_mult_9), + .o_C_9(o_ct_9), + .i_A_10(o_it_gt_mult_10), + .i_B_10(o_ft_Ct_1_mult_10), + .o_C_10(o_ct_10), + .i_A_11(o_it_gt_mult_11), + .i_B_11(o_ft_Ct_1_mult_11), + .o_C_11(o_ct_11), + .i_A_12(o_it_gt_mult_12), + .i_B_12(o_ft_Ct_1_mult_12), + .o_C_12(o_ct_12), + .i_A_13(o_it_gt_mult_13), + .i_B_13(o_ft_Ct_1_mult_13), + .o_C_13(o_ct_13), + .i_A_14(o_it_gt_mult_14), + .i_B_14(o_ft_Ct_1_mult_14), + .o_C_14(o_ct_14), + .i_A_15(o_it_gt_mult_15), + .i_B_15(o_ft_Ct_1_mult_15), + .o_C_15(o_ct_15), + .i_A_16(o_it_gt_mult_16), + .i_B_16(o_ft_Ct_1_mult_16), + .o_C_16(o_ct_16), + .i_A_17(o_it_gt_mult_17), + .i_B_17(o_ft_Ct_1_mult_17), + .o_C_17(o_ct_17), + .i_A_18(o_it_gt_mult_18), + .i_B_18(o_ft_Ct_1_mult_18), + .o_C_18(o_ct_18), + .i_A_19(o_it_gt_mult_19), + .i_B_19(o_ft_Ct_1_mult_19), + .o_C_19(o_ct_19), + .i_A_20(o_it_gt_mult_20), + .i_B_20(o_ft_Ct_1_mult_20), + .o_C_20(o_ct_20), + .i_A_21(o_it_gt_mult_21), + .i_B_21(o_ft_Ct_1_mult_21), + .o_C_21(o_ct_21), + .i_A_22(o_it_gt_mult_22), + .i_B_22(o_ft_Ct_1_mult_22), + .o_C_22(o_ct_22), + .i_A_23(o_it_gt_mult_23), + .i_B_23(o_ft_Ct_1_mult_23), + .o_C_23(o_ct_23), + .i_A_24(o_it_gt_mult_24), + .i_B_24(o_ft_Ct_1_mult_24), + .o_C_24(o_ct_24), + .i_A_25(o_it_gt_mult_25), + .i_B_25(o_ft_Ct_1_mult_25), + .o_C_25(o_ct_25), + .i_A_26(o_it_gt_mult_26), + .i_B_26(o_ft_Ct_1_mult_26), + .o_C_26(o_ct_26), + .i_A_27(o_it_gt_mult_27), + .i_B_27(o_ft_Ct_1_mult_27), + .o_C_27(o_ct_27), + .i_A_28(o_it_gt_mult_28), + .i_B_28(o_ft_Ct_1_mult_28), + .o_C_28(o_ct_28), + .i_A_29(o_it_gt_mult_29), + .i_B_29(o_ft_Ct_1_mult_29), + .o_C_29(o_ct_29), + .i_A_30(o_it_gt_mult_30), + .i_B_30(o_ft_Ct_1_mult_30), + .o_C_30(o_ct_30), + .i_A_31(o_it_gt_mult_31), + .i_B_31(o_ft_Ct_1_mult_31), + .o_C_31(o_ct_31), + .i_A_32(o_it_gt_mult_32), + .i_B_32(o_ft_Ct_1_mult_32), + .o_C_32(o_ct_32), + .i_A_33(o_it_gt_mult_33), + .i_B_33(o_ft_Ct_1_mult_33), + .o_C_33(o_ct_33), + .i_A_34(o_it_gt_mult_34), + .i_B_34(o_ft_Ct_1_mult_34), + .o_C_34(o_ct_34), + .i_A_35(o_it_gt_mult_35), + .i_B_35(o_ft_Ct_1_mult_35), + .o_C_35(o_ct_35), + .i_A_36(o_it_gt_mult_36), + .i_B_36(o_ft_Ct_1_mult_36), + .o_C_36(o_ct_36), + .i_A_37(o_it_gt_mult_37), + .i_B_37(o_ft_Ct_1_mult_37), + .o_C_37(o_ct_37), + .i_A_38(o_it_gt_mult_38), + .i_B_38(o_ft_Ct_1_mult_38), + .o_C_38(o_ct_38), + .i_A_39(o_it_gt_mult_39), + .i_B_39(o_ft_Ct_1_mult_39), + .o_C_39(o_ct_39), + .i_A_40(o_it_gt_mult_40), + .i_B_40(o_ft_Ct_1_mult_40), + .o_C_40(o_ct_40), + .i_A_41(o_it_gt_mult_41), + .i_B_41(o_ft_Ct_1_mult_41), + .o_C_41(o_ct_41), + .i_A_42(o_it_gt_mult_42), + .i_B_42(o_ft_Ct_1_mult_42), + .o_C_42(o_ct_42), + .i_A_43(o_it_gt_mult_43), + .i_B_43(o_ft_Ct_1_mult_43), + .o_C_43(o_ct_43), + .i_A_44(o_it_gt_mult_44), + .i_B_44(o_ft_Ct_1_mult_44), + .o_C_44(o_ct_44), + .i_A_45(o_it_gt_mult_45), + .i_B_45(o_ft_Ct_1_mult_45), + .o_C_45(o_ct_45), + .i_A_46(o_it_gt_mult_46), + .i_B_46(o_ft_Ct_1_mult_46), + .o_C_46(o_ct_46), + .i_A_47(o_it_gt_mult_47), + .i_B_47(o_ft_Ct_1_mult_47), + .o_C_47(o_ct_47), + .o_valid(ct_valid), + .o_ready() +); + +shift_register_group_18_48_14 shift_register_group_18_48_14_Ct ( + .clk(clk), + .enable(enable), + .in_0(o_ct_0), + .out_0(ct_hold_0), + .in_1(o_ct_1), + .out_1(ct_hold_1), + .in_2(o_ct_2), + .out_2(ct_hold_2), + .in_3(o_ct_3), + .out_3(ct_hold_3), + .in_4(o_ct_4), + .out_4(ct_hold_4), + .in_5(o_ct_5), + .out_5(ct_hold_5), + .in_6(o_ct_6), + .out_6(ct_hold_6), + .in_7(o_ct_7), + .out_7(ct_hold_7), + .in_8(o_ct_8), + .out_8(ct_hold_8), + .in_9(o_ct_9), + .out_9(ct_hold_9), + .in_10(o_ct_10), + .out_10(ct_hold_10), + .in_11(o_ct_11), + .out_11(ct_hold_11), + .in_12(o_ct_12), + .out_12(ct_hold_12), + .in_13(o_ct_13), + .out_13(ct_hold_13), + .in_14(o_ct_14), + .out_14(ct_hold_14), + .in_15(o_ct_15), + .out_15(ct_hold_15), + .in_16(o_ct_16), + .out_16(ct_hold_16), + .in_17(o_ct_17), + .out_17(ct_hold_17), + .in_18(o_ct_18), + .out_18(ct_hold_18), + .in_19(o_ct_19), + .out_19(ct_hold_19), + .in_20(o_ct_20), + .out_20(ct_hold_20), + .in_21(o_ct_21), + .out_21(ct_hold_21), + .in_22(o_ct_22), + .out_22(ct_hold_22), + .in_23(o_ct_23), + .out_23(ct_hold_23), + .in_24(o_ct_24), + .out_24(ct_hold_24), + .in_25(o_ct_25), + .out_25(ct_hold_25), + .in_26(o_ct_26), + .out_26(ct_hold_26), + .in_27(o_ct_27), + .out_27(ct_hold_27), + .in_28(o_ct_28), + .out_28(ct_hold_28), + .in_29(o_ct_29), + .out_29(ct_hold_29), + .in_30(o_ct_30), + .out_30(ct_hold_30), + .in_31(o_ct_31), + .out_31(ct_hold_31), + .in_32(o_ct_32), + .out_32(ct_hold_32), + .in_33(o_ct_33), + .out_33(ct_hold_33), + .in_34(o_ct_34), + .out_34(ct_hold_34), + .in_35(o_ct_35), + .out_35(ct_hold_35), + .in_36(o_ct_36), + .out_36(ct_hold_36), + .in_37(o_ct_37), + .out_37(ct_hold_37), + .in_38(o_ct_38), + .out_38(ct_hold_38), + .in_39(o_ct_39), + .out_39(ct_hold_39), + .in_40(o_ct_40), + .out_40(ct_hold_40), + .in_41(o_ct_41), + .out_41(ct_hold_41), + .in_42(o_ct_42), + .out_42(ct_hold_42), + .in_43(o_ct_43), + .out_43(ct_hold_43), + .in_44(o_ct_44), + .out_44(ct_hold_44), + .in_45(o_ct_45), + .out_45(ct_hold_45), + .in_46(o_ct_46), + .out_46(ct_hold_46), + .in_47(o_ct_47), + .out_47(ct_hold_47), + .reset(reset) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_0 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_0), + .i_x(o_ct_0), + .o_y(o_tanh_0) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_1 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_1), + .i_x(o_ct_1), + .o_y(o_tanh_1) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_2 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_2), + .i_x(o_ct_2), + .o_y(o_tanh_2) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_3 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_3), + .i_x(o_ct_3), + .o_y(o_tanh_3) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_4 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_4), + .i_x(o_ct_4), + .o_y(o_tanh_4) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_5 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_5), + .i_x(o_ct_5), + .o_y(o_tanh_5) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_6 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_6), + .i_x(o_ct_6), + .o_y(o_tanh_6) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_7 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_7), + .i_x(o_ct_7), + .o_y(o_tanh_7) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_8 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_8), + .i_x(o_ct_8), + .o_y(o_tanh_8) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_9 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_9), + .i_x(o_ct_9), + .o_y(o_tanh_9) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_10 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_10), + .i_x(o_ct_10), + .o_y(o_tanh_10) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_11 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_11), + .i_x(o_ct_11), + .o_y(o_tanh_11) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_12 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_12), + .i_x(o_ct_12), + .o_y(o_tanh_12) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_13 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_13), + .i_x(o_ct_13), + .o_y(o_tanh_13) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_14 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_14), + .i_x(o_ct_14), + .o_y(o_tanh_14) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_15 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_15), + .i_x(o_ct_15), + .o_y(o_tanh_15) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_16 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_16), + .i_x(o_ct_16), + .o_y(o_tanh_16) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_17 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_17), + .i_x(o_ct_17), + .o_y(o_tanh_17) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_18 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_18), + .i_x(o_ct_18), + .o_y(o_tanh_18) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_19 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_19), + .i_x(o_ct_19), + .o_y(o_tanh_19) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_20 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_20), + .i_x(o_ct_20), + .o_y(o_tanh_20) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_21 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_21), + .i_x(o_ct_21), + .o_y(o_tanh_21) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_22 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_22), + .i_x(o_ct_22), + .o_y(o_tanh_22) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_23 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_23), + .i_x(o_ct_23), + .o_y(o_tanh_23) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_24 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_24), + .i_x(o_ct_24), + .o_y(o_tanh_24) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_25 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_25), + .i_x(o_ct_25), + .o_y(o_tanh_25) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_26 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_26), + .i_x(o_ct_26), + .o_y(o_tanh_26) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_27 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_27), + .i_x(o_ct_27), + .o_y(o_tanh_27) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_28 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_28), + .i_x(o_ct_28), + .o_y(o_tanh_28) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_29 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_29), + .i_x(o_ct_29), + .o_y(o_tanh_29) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_30 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_30), + .i_x(o_ct_30), + .o_y(o_tanh_30) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_31 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_31), + .i_x(o_ct_31), + .o_y(o_tanh_31) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_32 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_32), + .i_x(o_ct_32), + .o_y(o_tanh_32) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_33 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_33), + .i_x(o_ct_33), + .o_y(o_tanh_33) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_34 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_34), + .i_x(o_ct_34), + .o_y(o_tanh_34) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_35 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_35), + .i_x(o_ct_35), + .o_y(o_tanh_35) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_36 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_36), + .i_x(o_ct_36), + .o_y(o_tanh_36) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_37 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_37), + .i_x(o_ct_37), + .o_y(o_tanh_37) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_38 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_38), + .i_x(o_ct_38), + .o_y(o_tanh_38) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_39 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_39), + .i_x(o_ct_39), + .o_y(o_tanh_39) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_40 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_40), + .i_x(o_ct_40), + .o_y(o_tanh_40) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_41 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_41), + .i_x(o_ct_41), + .o_y(o_tanh_41) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_42 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_42), + .i_x(o_ct_42), + .o_y(o_tanh_42) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_43 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_43), + .i_x(o_ct_43), + .o_y(o_tanh_43) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_44 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_44), + .i_x(o_ct_44), + .o_y(o_tanh_44) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_45 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_45), + .i_x(o_ct_45), + .o_y(o_tanh_45) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_46 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_46), + .i_x(o_ct_46), + .o_y(o_tanh_46) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_47 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_47), + .i_x(o_ct_47), + .o_y(o_tanh_47) +); + +shift_register_group_18_48_18 shift_register_group_18_48_18_Ct ( + .clk(clk), + .enable(enable), + .in_0(o_output_gate_0), + .out_0(ot_hold_0), + .in_1(o_output_gate_1), + .out_1(ot_hold_1), + .in_2(o_output_gate_2), + .out_2(ot_hold_2), + .in_3(o_output_gate_3), + .out_3(ot_hold_3), + .in_4(o_output_gate_4), + .out_4(ot_hold_4), + .in_5(o_output_gate_5), + .out_5(ot_hold_5), + .in_6(o_output_gate_6), + .out_6(ot_hold_6), + .in_7(o_output_gate_7), + .out_7(ot_hold_7), + .in_8(o_output_gate_8), + .out_8(ot_hold_8), + .in_9(o_output_gate_9), + .out_9(ot_hold_9), + .in_10(o_output_gate_10), + .out_10(ot_hold_10), + .in_11(o_output_gate_11), + .out_11(ot_hold_11), + .in_12(o_output_gate_12), + .out_12(ot_hold_12), + .in_13(o_output_gate_13), + .out_13(ot_hold_13), + .in_14(o_output_gate_14), + .out_14(ot_hold_14), + .in_15(o_output_gate_15), + .out_15(ot_hold_15), + .in_16(o_output_gate_16), + .out_16(ot_hold_16), + .in_17(o_output_gate_17), + .out_17(ot_hold_17), + .in_18(o_output_gate_18), + .out_18(ot_hold_18), + .in_19(o_output_gate_19), + .out_19(ot_hold_19), + .in_20(o_output_gate_20), + .out_20(ot_hold_20), + .in_21(o_output_gate_21), + .out_21(ot_hold_21), + .in_22(o_output_gate_22), + .out_22(ot_hold_22), + .in_23(o_output_gate_23), + .out_23(ot_hold_23), + .in_24(o_output_gate_24), + .out_24(ot_hold_24), + .in_25(o_output_gate_25), + .out_25(ot_hold_25), + .in_26(o_output_gate_26), + .out_26(ot_hold_26), + .in_27(o_output_gate_27), + .out_27(ot_hold_27), + .in_28(o_output_gate_28), + .out_28(ot_hold_28), + .in_29(o_output_gate_29), + .out_29(ot_hold_29), + .in_30(o_output_gate_30), + .out_30(ot_hold_30), + .in_31(o_output_gate_31), + .out_31(ot_hold_31), + .in_32(o_output_gate_32), + .out_32(ot_hold_32), + .in_33(o_output_gate_33), + .out_33(ot_hold_33), + .in_34(o_output_gate_34), + .out_34(ot_hold_34), + .in_35(o_output_gate_35), + .out_35(ot_hold_35), + .in_36(o_output_gate_36), + .out_36(ot_hold_36), + .in_37(o_output_gate_37), + .out_37(ot_hold_37), + .in_38(o_output_gate_38), + .out_38(ot_hold_38), + .in_39(o_output_gate_39), + .out_39(ot_hold_39), + .in_40(o_output_gate_40), + .out_40(ot_hold_40), + .in_41(o_output_gate_41), + .out_41(ot_hold_41), + .in_42(o_output_gate_42), + .out_42(ot_hold_42), + .in_43(o_output_gate_43), + .out_43(ot_hold_43), + .in_44(o_output_gate_44), + .out_44(ot_hold_44), + .in_45(o_output_gate_45), + .out_45(ot_hold_45), + .in_46(o_output_gate_46), + .out_46(ot_hold_46), + .in_47(o_output_gate_47), + .out_47(ot_hold_47), + .reset(reset) +); + +elementwise_mult_core_18_18_10_48_1 elementwise_mult_core_18_18_10_48_1_ot_tanh_mult ( + .clk(clk), + .reset(reset), + .i_valid(tanh_valid_0), + .i_ready(enable), + .i_A_0(o_tanh_0), + .i_B_0(ot_hold_0), + .o_C_0(o_mt_0), + .i_A_1(o_tanh_1), + .i_B_1(ot_hold_1), + .o_C_1(o_mt_1), + .i_A_2(o_tanh_2), + .i_B_2(ot_hold_2), + .o_C_2(o_mt_2), + .i_A_3(o_tanh_3), + .i_B_3(ot_hold_3), + .o_C_3(o_mt_3), + .i_A_4(o_tanh_4), + .i_B_4(ot_hold_4), + .o_C_4(o_mt_4), + .i_A_5(o_tanh_5), + .i_B_5(ot_hold_5), + .o_C_5(o_mt_5), + .i_A_6(o_tanh_6), + .i_B_6(ot_hold_6), + .o_C_6(o_mt_6), + .i_A_7(o_tanh_7), + .i_B_7(ot_hold_7), + .o_C_7(o_mt_7), + .i_A_8(o_tanh_8), + .i_B_8(ot_hold_8), + .o_C_8(o_mt_8), + .i_A_9(o_tanh_9), + .i_B_9(ot_hold_9), + .o_C_9(o_mt_9), + .i_A_10(o_tanh_10), + .i_B_10(ot_hold_10), + .o_C_10(o_mt_10), + .i_A_11(o_tanh_11), + .i_B_11(ot_hold_11), + .o_C_11(o_mt_11), + .i_A_12(o_tanh_12), + .i_B_12(ot_hold_12), + .o_C_12(o_mt_12), + .i_A_13(o_tanh_13), + .i_B_13(ot_hold_13), + .o_C_13(o_mt_13), + .i_A_14(o_tanh_14), + .i_B_14(ot_hold_14), + .o_C_14(o_mt_14), + .i_A_15(o_tanh_15), + .i_B_15(ot_hold_15), + .o_C_15(o_mt_15), + .i_A_16(o_tanh_16), + .i_B_16(ot_hold_16), + .o_C_16(o_mt_16), + .i_A_17(o_tanh_17), + .i_B_17(ot_hold_17), + .o_C_17(o_mt_17), + .i_A_18(o_tanh_18), + .i_B_18(ot_hold_18), + .o_C_18(o_mt_18), + .i_A_19(o_tanh_19), + .i_B_19(ot_hold_19), + .o_C_19(o_mt_19), + .i_A_20(o_tanh_20), + .i_B_20(ot_hold_20), + .o_C_20(o_mt_20), + .i_A_21(o_tanh_21), + .i_B_21(ot_hold_21), + .o_C_21(o_mt_21), + .i_A_22(o_tanh_22), + .i_B_22(ot_hold_22), + .o_C_22(o_mt_22), + .i_A_23(o_tanh_23), + .i_B_23(ot_hold_23), + .o_C_23(o_mt_23), + .i_A_24(o_tanh_24), + .i_B_24(ot_hold_24), + .o_C_24(o_mt_24), + .i_A_25(o_tanh_25), + .i_B_25(ot_hold_25), + .o_C_25(o_mt_25), + .i_A_26(o_tanh_26), + .i_B_26(ot_hold_26), + .o_C_26(o_mt_26), + .i_A_27(o_tanh_27), + .i_B_27(ot_hold_27), + .o_C_27(o_mt_27), + .i_A_28(o_tanh_28), + .i_B_28(ot_hold_28), + .o_C_28(o_mt_28), + .i_A_29(o_tanh_29), + .i_B_29(ot_hold_29), + .o_C_29(o_mt_29), + .i_A_30(o_tanh_30), + .i_B_30(ot_hold_30), + .o_C_30(o_mt_30), + .i_A_31(o_tanh_31), + .i_B_31(ot_hold_31), + .o_C_31(o_mt_31), + .i_A_32(o_tanh_32), + .i_B_32(ot_hold_32), + .o_C_32(o_mt_32), + .i_A_33(o_tanh_33), + .i_B_33(ot_hold_33), + .o_C_33(o_mt_33), + .i_A_34(o_tanh_34), + .i_B_34(ot_hold_34), + .o_C_34(o_mt_34), + .i_A_35(o_tanh_35), + .i_B_35(ot_hold_35), + .o_C_35(o_mt_35), + .i_A_36(o_tanh_36), + .i_B_36(ot_hold_36), + .o_C_36(o_mt_36), + .i_A_37(o_tanh_37), + .i_B_37(ot_hold_37), + .o_C_37(o_mt_37), + .i_A_38(o_tanh_38), + .i_B_38(ot_hold_38), + .o_C_38(o_mt_38), + .i_A_39(o_tanh_39), + .i_B_39(ot_hold_39), + .o_C_39(o_mt_39), + .i_A_40(o_tanh_40), + .i_B_40(ot_hold_40), + .o_C_40(o_mt_40), + .i_A_41(o_tanh_41), + .i_B_41(ot_hold_41), + .o_C_41(o_mt_41), + .i_A_42(o_tanh_42), + .i_B_42(ot_hold_42), + .o_C_42(o_mt_42), + .i_A_43(o_tanh_43), + .i_B_43(ot_hold_43), + .o_C_43(o_mt_43), + .i_A_44(o_tanh_44), + .i_B_44(ot_hold_44), + .o_C_44(o_mt_44), + .i_A_45(o_tanh_45), + .i_B_45(ot_hold_45), + .o_C_45(o_mt_45), + .i_A_46(o_tanh_46), + .i_B_46(ot_hold_46), + .o_C_46(o_mt_46), + .i_A_47(o_tanh_47), + .i_B_47(ot_hold_47), + .o_C_47(o_mt_47), + .o_valid(mt_valid), + .o_ready() +); + +always @ (posedge clk) begin + if(reset) begin + reg_i_valid <= 1'b0; + reg_o_valid <= 1'b0; + reg_Ct_1_0 <= 0; + reg_WixrXtYt_1_0 <= 0; + reg_Wic_0 <= 0; + reg_bi_0 <= 0; + reg_WfxrXtYt_1_0 <= 0; + reg_Wfc_0 <= 0; + reg_bf_0 <= 0; + reg_WoxrXtYt_1_0 <= 0; + reg_Woc_0 <= 0; + reg_bo_0 <= 0; + reg_WcxrXtYt_1_0 <= 0; + reg_bc_0 <= 0; + reg_out_mt_0 <= 0; + reg_out_ct_0 <= 0; + reg_Ct_1_1 <= 0; + reg_WixrXtYt_1_1 <= 0; + reg_Wic_1 <= 0; + reg_bi_1 <= 0; + reg_WfxrXtYt_1_1 <= 0; + reg_Wfc_1 <= 0; + reg_bf_1 <= 0; + reg_WoxrXtYt_1_1 <= 0; + reg_Woc_1 <= 0; + reg_bo_1 <= 0; + reg_WcxrXtYt_1_1 <= 0; + reg_bc_1 <= 0; + reg_out_mt_1 <= 0; + reg_out_ct_1 <= 0; + reg_Ct_1_2 <= 0; + reg_WixrXtYt_1_2 <= 0; + reg_Wic_2 <= 0; + reg_bi_2 <= 0; + reg_WfxrXtYt_1_2 <= 0; + reg_Wfc_2 <= 0; + reg_bf_2 <= 0; + reg_WoxrXtYt_1_2 <= 0; + reg_Woc_2 <= 0; + reg_bo_2 <= 0; + reg_WcxrXtYt_1_2 <= 0; + reg_bc_2 <= 0; + reg_out_mt_2 <= 0; + reg_out_ct_2 <= 0; + reg_Ct_1_3 <= 0; + reg_WixrXtYt_1_3 <= 0; + reg_Wic_3 <= 0; + reg_bi_3 <= 0; + reg_WfxrXtYt_1_3 <= 0; + reg_Wfc_3 <= 0; + reg_bf_3 <= 0; + reg_WoxrXtYt_1_3 <= 0; + reg_Woc_3 <= 0; + reg_bo_3 <= 0; + reg_WcxrXtYt_1_3 <= 0; + reg_bc_3 <= 0; + reg_out_mt_3 <= 0; + reg_out_ct_3 <= 0; + reg_Ct_1_4 <= 0; + reg_WixrXtYt_1_4 <= 0; + reg_Wic_4 <= 0; + reg_bi_4 <= 0; + reg_WfxrXtYt_1_4 <= 0; + reg_Wfc_4 <= 0; + reg_bf_4 <= 0; + reg_WoxrXtYt_1_4 <= 0; + reg_Woc_4 <= 0; + reg_bo_4 <= 0; + reg_WcxrXtYt_1_4 <= 0; + reg_bc_4 <= 0; + reg_out_mt_4 <= 0; + reg_out_ct_4 <= 0; + reg_Ct_1_5 <= 0; + reg_WixrXtYt_1_5 <= 0; + reg_Wic_5 <= 0; + reg_bi_5 <= 0; + reg_WfxrXtYt_1_5 <= 0; + reg_Wfc_5 <= 0; + reg_bf_5 <= 0; + reg_WoxrXtYt_1_5 <= 0; + reg_Woc_5 <= 0; + reg_bo_5 <= 0; + reg_WcxrXtYt_1_5 <= 0; + reg_bc_5 <= 0; + reg_out_mt_5 <= 0; + reg_out_ct_5 <= 0; + reg_Ct_1_6 <= 0; + reg_WixrXtYt_1_6 <= 0; + reg_Wic_6 <= 0; + reg_bi_6 <= 0; + reg_WfxrXtYt_1_6 <= 0; + reg_Wfc_6 <= 0; + reg_bf_6 <= 0; + reg_WoxrXtYt_1_6 <= 0; + reg_Woc_6 <= 0; + reg_bo_6 <= 0; + reg_WcxrXtYt_1_6 <= 0; + reg_bc_6 <= 0; + reg_out_mt_6 <= 0; + reg_out_ct_6 <= 0; + reg_Ct_1_7 <= 0; + reg_WixrXtYt_1_7 <= 0; + reg_Wic_7 <= 0; + reg_bi_7 <= 0; + reg_WfxrXtYt_1_7 <= 0; + reg_Wfc_7 <= 0; + reg_bf_7 <= 0; + reg_WoxrXtYt_1_7 <= 0; + reg_Woc_7 <= 0; + reg_bo_7 <= 0; + reg_WcxrXtYt_1_7 <= 0; + reg_bc_7 <= 0; + reg_out_mt_7 <= 0; + reg_out_ct_7 <= 0; + reg_Ct_1_8 <= 0; + reg_WixrXtYt_1_8 <= 0; + reg_Wic_8 <= 0; + reg_bi_8 <= 0; + reg_WfxrXtYt_1_8 <= 0; + reg_Wfc_8 <= 0; + reg_bf_8 <= 0; + reg_WoxrXtYt_1_8 <= 0; + reg_Woc_8 <= 0; + reg_bo_8 <= 0; + reg_WcxrXtYt_1_8 <= 0; + reg_bc_8 <= 0; + reg_out_mt_8 <= 0; + reg_out_ct_8 <= 0; + reg_Ct_1_9 <= 0; + reg_WixrXtYt_1_9 <= 0; + reg_Wic_9 <= 0; + reg_bi_9 <= 0; + reg_WfxrXtYt_1_9 <= 0; + reg_Wfc_9 <= 0; + reg_bf_9 <= 0; + reg_WoxrXtYt_1_9 <= 0; + reg_Woc_9 <= 0; + reg_bo_9 <= 0; + reg_WcxrXtYt_1_9 <= 0; + reg_bc_9 <= 0; + reg_out_mt_9 <= 0; + reg_out_ct_9 <= 0; + reg_Ct_1_10 <= 0; + reg_WixrXtYt_1_10 <= 0; + reg_Wic_10 <= 0; + reg_bi_10 <= 0; + reg_WfxrXtYt_1_10 <= 0; + reg_Wfc_10 <= 0; + reg_bf_10 <= 0; + reg_WoxrXtYt_1_10 <= 0; + reg_Woc_10 <= 0; + reg_bo_10 <= 0; + reg_WcxrXtYt_1_10 <= 0; + reg_bc_10 <= 0; + reg_out_mt_10 <= 0; + reg_out_ct_10 <= 0; + reg_Ct_1_11 <= 0; + reg_WixrXtYt_1_11 <= 0; + reg_Wic_11 <= 0; + reg_bi_11 <= 0; + reg_WfxrXtYt_1_11 <= 0; + reg_Wfc_11 <= 0; + reg_bf_11 <= 0; + reg_WoxrXtYt_1_11 <= 0; + reg_Woc_11 <= 0; + reg_bo_11 <= 0; + reg_WcxrXtYt_1_11 <= 0; + reg_bc_11 <= 0; + reg_out_mt_11 <= 0; + reg_out_ct_11 <= 0; + reg_Ct_1_12 <= 0; + reg_WixrXtYt_1_12 <= 0; + reg_Wic_12 <= 0; + reg_bi_12 <= 0; + reg_WfxrXtYt_1_12 <= 0; + reg_Wfc_12 <= 0; + reg_bf_12 <= 0; + reg_WoxrXtYt_1_12 <= 0; + reg_Woc_12 <= 0; + reg_bo_12 <= 0; + reg_WcxrXtYt_1_12 <= 0; + reg_bc_12 <= 0; + reg_out_mt_12 <= 0; + reg_out_ct_12 <= 0; + reg_Ct_1_13 <= 0; + reg_WixrXtYt_1_13 <= 0; + reg_Wic_13 <= 0; + reg_bi_13 <= 0; + reg_WfxrXtYt_1_13 <= 0; + reg_Wfc_13 <= 0; + reg_bf_13 <= 0; + reg_WoxrXtYt_1_13 <= 0; + reg_Woc_13 <= 0; + reg_bo_13 <= 0; + reg_WcxrXtYt_1_13 <= 0; + reg_bc_13 <= 0; + reg_out_mt_13 <= 0; + reg_out_ct_13 <= 0; + reg_Ct_1_14 <= 0; + reg_WixrXtYt_1_14 <= 0; + reg_Wic_14 <= 0; + reg_bi_14 <= 0; + reg_WfxrXtYt_1_14 <= 0; + reg_Wfc_14 <= 0; + reg_bf_14 <= 0; + reg_WoxrXtYt_1_14 <= 0; + reg_Woc_14 <= 0; + reg_bo_14 <= 0; + reg_WcxrXtYt_1_14 <= 0; + reg_bc_14 <= 0; + reg_out_mt_14 <= 0; + reg_out_ct_14 <= 0; + reg_Ct_1_15 <= 0; + reg_WixrXtYt_1_15 <= 0; + reg_Wic_15 <= 0; + reg_bi_15 <= 0; + reg_WfxrXtYt_1_15 <= 0; + reg_Wfc_15 <= 0; + reg_bf_15 <= 0; + reg_WoxrXtYt_1_15 <= 0; + reg_Woc_15 <= 0; + reg_bo_15 <= 0; + reg_WcxrXtYt_1_15 <= 0; + reg_bc_15 <= 0; + reg_out_mt_15 <= 0; + reg_out_ct_15 <= 0; + reg_Ct_1_16 <= 0; + reg_WixrXtYt_1_16 <= 0; + reg_Wic_16 <= 0; + reg_bi_16 <= 0; + reg_WfxrXtYt_1_16 <= 0; + reg_Wfc_16 <= 0; + reg_bf_16 <= 0; + reg_WoxrXtYt_1_16 <= 0; + reg_Woc_16 <= 0; + reg_bo_16 <= 0; + reg_WcxrXtYt_1_16 <= 0; + reg_bc_16 <= 0; + reg_out_mt_16 <= 0; + reg_out_ct_16 <= 0; + reg_Ct_1_17 <= 0; + reg_WixrXtYt_1_17 <= 0; + reg_Wic_17 <= 0; + reg_bi_17 <= 0; + reg_WfxrXtYt_1_17 <= 0; + reg_Wfc_17 <= 0; + reg_bf_17 <= 0; + reg_WoxrXtYt_1_17 <= 0; + reg_Woc_17 <= 0; + reg_bo_17 <= 0; + reg_WcxrXtYt_1_17 <= 0; + reg_bc_17 <= 0; + reg_out_mt_17 <= 0; + reg_out_ct_17 <= 0; + reg_Ct_1_18 <= 0; + reg_WixrXtYt_1_18 <= 0; + reg_Wic_18 <= 0; + reg_bi_18 <= 0; + reg_WfxrXtYt_1_18 <= 0; + reg_Wfc_18 <= 0; + reg_bf_18 <= 0; + reg_WoxrXtYt_1_18 <= 0; + reg_Woc_18 <= 0; + reg_bo_18 <= 0; + reg_WcxrXtYt_1_18 <= 0; + reg_bc_18 <= 0; + reg_out_mt_18 <= 0; + reg_out_ct_18 <= 0; + reg_Ct_1_19 <= 0; + reg_WixrXtYt_1_19 <= 0; + reg_Wic_19 <= 0; + reg_bi_19 <= 0; + reg_WfxrXtYt_1_19 <= 0; + reg_Wfc_19 <= 0; + reg_bf_19 <= 0; + reg_WoxrXtYt_1_19 <= 0; + reg_Woc_19 <= 0; + reg_bo_19 <= 0; + reg_WcxrXtYt_1_19 <= 0; + reg_bc_19 <= 0; + reg_out_mt_19 <= 0; + reg_out_ct_19 <= 0; + reg_Ct_1_20 <= 0; + reg_WixrXtYt_1_20 <= 0; + reg_Wic_20 <= 0; + reg_bi_20 <= 0; + reg_WfxrXtYt_1_20 <= 0; + reg_Wfc_20 <= 0; + reg_bf_20 <= 0; + reg_WoxrXtYt_1_20 <= 0; + reg_Woc_20 <= 0; + reg_bo_20 <= 0; + reg_WcxrXtYt_1_20 <= 0; + reg_bc_20 <= 0; + reg_out_mt_20 <= 0; + reg_out_ct_20 <= 0; + reg_Ct_1_21 <= 0; + reg_WixrXtYt_1_21 <= 0; + reg_Wic_21 <= 0; + reg_bi_21 <= 0; + reg_WfxrXtYt_1_21 <= 0; + reg_Wfc_21 <= 0; + reg_bf_21 <= 0; + reg_WoxrXtYt_1_21 <= 0; + reg_Woc_21 <= 0; + reg_bo_21 <= 0; + reg_WcxrXtYt_1_21 <= 0; + reg_bc_21 <= 0; + reg_out_mt_21 <= 0; + reg_out_ct_21 <= 0; + reg_Ct_1_22 <= 0; + reg_WixrXtYt_1_22 <= 0; + reg_Wic_22 <= 0; + reg_bi_22 <= 0; + reg_WfxrXtYt_1_22 <= 0; + reg_Wfc_22 <= 0; + reg_bf_22 <= 0; + reg_WoxrXtYt_1_22 <= 0; + reg_Woc_22 <= 0; + reg_bo_22 <= 0; + reg_WcxrXtYt_1_22 <= 0; + reg_bc_22 <= 0; + reg_out_mt_22 <= 0; + reg_out_ct_22 <= 0; + reg_Ct_1_23 <= 0; + reg_WixrXtYt_1_23 <= 0; + reg_Wic_23 <= 0; + reg_bi_23 <= 0; + reg_WfxrXtYt_1_23 <= 0; + reg_Wfc_23 <= 0; + reg_bf_23 <= 0; + reg_WoxrXtYt_1_23 <= 0; + reg_Woc_23 <= 0; + reg_bo_23 <= 0; + reg_WcxrXtYt_1_23 <= 0; + reg_bc_23 <= 0; + reg_out_mt_23 <= 0; + reg_out_ct_23 <= 0; + reg_Ct_1_24 <= 0; + reg_WixrXtYt_1_24 <= 0; + reg_Wic_24 <= 0; + reg_bi_24 <= 0; + reg_WfxrXtYt_1_24 <= 0; + reg_Wfc_24 <= 0; + reg_bf_24 <= 0; + reg_WoxrXtYt_1_24 <= 0; + reg_Woc_24 <= 0; + reg_bo_24 <= 0; + reg_WcxrXtYt_1_24 <= 0; + reg_bc_24 <= 0; + reg_out_mt_24 <= 0; + reg_out_ct_24 <= 0; + reg_Ct_1_25 <= 0; + reg_WixrXtYt_1_25 <= 0; + reg_Wic_25 <= 0; + reg_bi_25 <= 0; + reg_WfxrXtYt_1_25 <= 0; + reg_Wfc_25 <= 0; + reg_bf_25 <= 0; + reg_WoxrXtYt_1_25 <= 0; + reg_Woc_25 <= 0; + reg_bo_25 <= 0; + reg_WcxrXtYt_1_25 <= 0; + reg_bc_25 <= 0; + reg_out_mt_25 <= 0; + reg_out_ct_25 <= 0; + reg_Ct_1_26 <= 0; + reg_WixrXtYt_1_26 <= 0; + reg_Wic_26 <= 0; + reg_bi_26 <= 0; + reg_WfxrXtYt_1_26 <= 0; + reg_Wfc_26 <= 0; + reg_bf_26 <= 0; + reg_WoxrXtYt_1_26 <= 0; + reg_Woc_26 <= 0; + reg_bo_26 <= 0; + reg_WcxrXtYt_1_26 <= 0; + reg_bc_26 <= 0; + reg_out_mt_26 <= 0; + reg_out_ct_26 <= 0; + reg_Ct_1_27 <= 0; + reg_WixrXtYt_1_27 <= 0; + reg_Wic_27 <= 0; + reg_bi_27 <= 0; + reg_WfxrXtYt_1_27 <= 0; + reg_Wfc_27 <= 0; + reg_bf_27 <= 0; + reg_WoxrXtYt_1_27 <= 0; + reg_Woc_27 <= 0; + reg_bo_27 <= 0; + reg_WcxrXtYt_1_27 <= 0; + reg_bc_27 <= 0; + reg_out_mt_27 <= 0; + reg_out_ct_27 <= 0; + reg_Ct_1_28 <= 0; + reg_WixrXtYt_1_28 <= 0; + reg_Wic_28 <= 0; + reg_bi_28 <= 0; + reg_WfxrXtYt_1_28 <= 0; + reg_Wfc_28 <= 0; + reg_bf_28 <= 0; + reg_WoxrXtYt_1_28 <= 0; + reg_Woc_28 <= 0; + reg_bo_28 <= 0; + reg_WcxrXtYt_1_28 <= 0; + reg_bc_28 <= 0; + reg_out_mt_28 <= 0; + reg_out_ct_28 <= 0; + reg_Ct_1_29 <= 0; + reg_WixrXtYt_1_29 <= 0; + reg_Wic_29 <= 0; + reg_bi_29 <= 0; + reg_WfxrXtYt_1_29 <= 0; + reg_Wfc_29 <= 0; + reg_bf_29 <= 0; + reg_WoxrXtYt_1_29 <= 0; + reg_Woc_29 <= 0; + reg_bo_29 <= 0; + reg_WcxrXtYt_1_29 <= 0; + reg_bc_29 <= 0; + reg_out_mt_29 <= 0; + reg_out_ct_29 <= 0; + reg_Ct_1_30 <= 0; + reg_WixrXtYt_1_30 <= 0; + reg_Wic_30 <= 0; + reg_bi_30 <= 0; + reg_WfxrXtYt_1_30 <= 0; + reg_Wfc_30 <= 0; + reg_bf_30 <= 0; + reg_WoxrXtYt_1_30 <= 0; + reg_Woc_30 <= 0; + reg_bo_30 <= 0; + reg_WcxrXtYt_1_30 <= 0; + reg_bc_30 <= 0; + reg_out_mt_30 <= 0; + reg_out_ct_30 <= 0; + reg_Ct_1_31 <= 0; + reg_WixrXtYt_1_31 <= 0; + reg_Wic_31 <= 0; + reg_bi_31 <= 0; + reg_WfxrXtYt_1_31 <= 0; + reg_Wfc_31 <= 0; + reg_bf_31 <= 0; + reg_WoxrXtYt_1_31 <= 0; + reg_Woc_31 <= 0; + reg_bo_31 <= 0; + reg_WcxrXtYt_1_31 <= 0; + reg_bc_31 <= 0; + reg_out_mt_31 <= 0; + reg_out_ct_31 <= 0; + reg_Ct_1_32 <= 0; + reg_WixrXtYt_1_32 <= 0; + reg_Wic_32 <= 0; + reg_bi_32 <= 0; + reg_WfxrXtYt_1_32 <= 0; + reg_Wfc_32 <= 0; + reg_bf_32 <= 0; + reg_WoxrXtYt_1_32 <= 0; + reg_Woc_32 <= 0; + reg_bo_32 <= 0; + reg_WcxrXtYt_1_32 <= 0; + reg_bc_32 <= 0; + reg_out_mt_32 <= 0; + reg_out_ct_32 <= 0; + reg_Ct_1_33 <= 0; + reg_WixrXtYt_1_33 <= 0; + reg_Wic_33 <= 0; + reg_bi_33 <= 0; + reg_WfxrXtYt_1_33 <= 0; + reg_Wfc_33 <= 0; + reg_bf_33 <= 0; + reg_WoxrXtYt_1_33 <= 0; + reg_Woc_33 <= 0; + reg_bo_33 <= 0; + reg_WcxrXtYt_1_33 <= 0; + reg_bc_33 <= 0; + reg_out_mt_33 <= 0; + reg_out_ct_33 <= 0; + reg_Ct_1_34 <= 0; + reg_WixrXtYt_1_34 <= 0; + reg_Wic_34 <= 0; + reg_bi_34 <= 0; + reg_WfxrXtYt_1_34 <= 0; + reg_Wfc_34 <= 0; + reg_bf_34 <= 0; + reg_WoxrXtYt_1_34 <= 0; + reg_Woc_34 <= 0; + reg_bo_34 <= 0; + reg_WcxrXtYt_1_34 <= 0; + reg_bc_34 <= 0; + reg_out_mt_34 <= 0; + reg_out_ct_34 <= 0; + reg_Ct_1_35 <= 0; + reg_WixrXtYt_1_35 <= 0; + reg_Wic_35 <= 0; + reg_bi_35 <= 0; + reg_WfxrXtYt_1_35 <= 0; + reg_Wfc_35 <= 0; + reg_bf_35 <= 0; + reg_WoxrXtYt_1_35 <= 0; + reg_Woc_35 <= 0; + reg_bo_35 <= 0; + reg_WcxrXtYt_1_35 <= 0; + reg_bc_35 <= 0; + reg_out_mt_35 <= 0; + reg_out_ct_35 <= 0; + reg_Ct_1_36 <= 0; + reg_WixrXtYt_1_36 <= 0; + reg_Wic_36 <= 0; + reg_bi_36 <= 0; + reg_WfxrXtYt_1_36 <= 0; + reg_Wfc_36 <= 0; + reg_bf_36 <= 0; + reg_WoxrXtYt_1_36 <= 0; + reg_Woc_36 <= 0; + reg_bo_36 <= 0; + reg_WcxrXtYt_1_36 <= 0; + reg_bc_36 <= 0; + reg_out_mt_36 <= 0; + reg_out_ct_36 <= 0; + reg_Ct_1_37 <= 0; + reg_WixrXtYt_1_37 <= 0; + reg_Wic_37 <= 0; + reg_bi_37 <= 0; + reg_WfxrXtYt_1_37 <= 0; + reg_Wfc_37 <= 0; + reg_bf_37 <= 0; + reg_WoxrXtYt_1_37 <= 0; + reg_Woc_37 <= 0; + reg_bo_37 <= 0; + reg_WcxrXtYt_1_37 <= 0; + reg_bc_37 <= 0; + reg_out_mt_37 <= 0; + reg_out_ct_37 <= 0; + reg_Ct_1_38 <= 0; + reg_WixrXtYt_1_38 <= 0; + reg_Wic_38 <= 0; + reg_bi_38 <= 0; + reg_WfxrXtYt_1_38 <= 0; + reg_Wfc_38 <= 0; + reg_bf_38 <= 0; + reg_WoxrXtYt_1_38 <= 0; + reg_Woc_38 <= 0; + reg_bo_38 <= 0; + reg_WcxrXtYt_1_38 <= 0; + reg_bc_38 <= 0; + reg_out_mt_38 <= 0; + reg_out_ct_38 <= 0; + reg_Ct_1_39 <= 0; + reg_WixrXtYt_1_39 <= 0; + reg_Wic_39 <= 0; + reg_bi_39 <= 0; + reg_WfxrXtYt_1_39 <= 0; + reg_Wfc_39 <= 0; + reg_bf_39 <= 0; + reg_WoxrXtYt_1_39 <= 0; + reg_Woc_39 <= 0; + reg_bo_39 <= 0; + reg_WcxrXtYt_1_39 <= 0; + reg_bc_39 <= 0; + reg_out_mt_39 <= 0; + reg_out_ct_39 <= 0; + reg_Ct_1_40 <= 0; + reg_WixrXtYt_1_40 <= 0; + reg_Wic_40 <= 0; + reg_bi_40 <= 0; + reg_WfxrXtYt_1_40 <= 0; + reg_Wfc_40 <= 0; + reg_bf_40 <= 0; + reg_WoxrXtYt_1_40 <= 0; + reg_Woc_40 <= 0; + reg_bo_40 <= 0; + reg_WcxrXtYt_1_40 <= 0; + reg_bc_40 <= 0; + reg_out_mt_40 <= 0; + reg_out_ct_40 <= 0; + reg_Ct_1_41 <= 0; + reg_WixrXtYt_1_41 <= 0; + reg_Wic_41 <= 0; + reg_bi_41 <= 0; + reg_WfxrXtYt_1_41 <= 0; + reg_Wfc_41 <= 0; + reg_bf_41 <= 0; + reg_WoxrXtYt_1_41 <= 0; + reg_Woc_41 <= 0; + reg_bo_41 <= 0; + reg_WcxrXtYt_1_41 <= 0; + reg_bc_41 <= 0; + reg_out_mt_41 <= 0; + reg_out_ct_41 <= 0; + reg_Ct_1_42 <= 0; + reg_WixrXtYt_1_42 <= 0; + reg_Wic_42 <= 0; + reg_bi_42 <= 0; + reg_WfxrXtYt_1_42 <= 0; + reg_Wfc_42 <= 0; + reg_bf_42 <= 0; + reg_WoxrXtYt_1_42 <= 0; + reg_Woc_42 <= 0; + reg_bo_42 <= 0; + reg_WcxrXtYt_1_42 <= 0; + reg_bc_42 <= 0; + reg_out_mt_42 <= 0; + reg_out_ct_42 <= 0; + reg_Ct_1_43 <= 0; + reg_WixrXtYt_1_43 <= 0; + reg_Wic_43 <= 0; + reg_bi_43 <= 0; + reg_WfxrXtYt_1_43 <= 0; + reg_Wfc_43 <= 0; + reg_bf_43 <= 0; + reg_WoxrXtYt_1_43 <= 0; + reg_Woc_43 <= 0; + reg_bo_43 <= 0; + reg_WcxrXtYt_1_43 <= 0; + reg_bc_43 <= 0; + reg_out_mt_43 <= 0; + reg_out_ct_43 <= 0; + reg_Ct_1_44 <= 0; + reg_WixrXtYt_1_44 <= 0; + reg_Wic_44 <= 0; + reg_bi_44 <= 0; + reg_WfxrXtYt_1_44 <= 0; + reg_Wfc_44 <= 0; + reg_bf_44 <= 0; + reg_WoxrXtYt_1_44 <= 0; + reg_Woc_44 <= 0; + reg_bo_44 <= 0; + reg_WcxrXtYt_1_44 <= 0; + reg_bc_44 <= 0; + reg_out_mt_44 <= 0; + reg_out_ct_44 <= 0; + reg_Ct_1_45 <= 0; + reg_WixrXtYt_1_45 <= 0; + reg_Wic_45 <= 0; + reg_bi_45 <= 0; + reg_WfxrXtYt_1_45 <= 0; + reg_Wfc_45 <= 0; + reg_bf_45 <= 0; + reg_WoxrXtYt_1_45 <= 0; + reg_Woc_45 <= 0; + reg_bo_45 <= 0; + reg_WcxrXtYt_1_45 <= 0; + reg_bc_45 <= 0; + reg_out_mt_45 <= 0; + reg_out_ct_45 <= 0; + reg_Ct_1_46 <= 0; + reg_WixrXtYt_1_46 <= 0; + reg_Wic_46 <= 0; + reg_bi_46 <= 0; + reg_WfxrXtYt_1_46 <= 0; + reg_Wfc_46 <= 0; + reg_bf_46 <= 0; + reg_WoxrXtYt_1_46 <= 0; + reg_Woc_46 <= 0; + reg_bo_46 <= 0; + reg_WcxrXtYt_1_46 <= 0; + reg_bc_46 <= 0; + reg_out_mt_46 <= 0; + reg_out_ct_46 <= 0; + reg_Ct_1_47 <= 0; + reg_WixrXtYt_1_47 <= 0; + reg_Wic_47 <= 0; + reg_bi_47 <= 0; + reg_WfxrXtYt_1_47 <= 0; + reg_Wfc_47 <= 0; + reg_bf_47 <= 0; + reg_WoxrXtYt_1_47 <= 0; + reg_Woc_47 <= 0; + reg_bo_47 <= 0; + reg_WcxrXtYt_1_47 <= 0; + reg_bc_47 <= 0; + reg_out_mt_47 <= 0; + reg_out_ct_47 <= 0; + end else if (enable) begin + reg_i_valid <= i_valid; + reg_o_valid <= mt_valid; + reg_Ct_1_0 <= Ct_1_0; + reg_WixrXtYt_1_0 <= WixrXtYt_1_0; + reg_Wic_0 <= Wic_0; + reg_bi_0 <= bi_0; + reg_WfxrXtYt_1_0 <= WfxrXtYt_1_0; + reg_Wfc_0 <= Wfc_0; + reg_bf_0 <= bf_0; + reg_WoxrXtYt_1_0 <= WoxrXtYt_1_0; + reg_Woc_0 <= Woc_0; + reg_bo_0 <= bo_0; + reg_WcxrXtYt_1_0 <= WcxrXtYt_1_0; + reg_bc_0 <= bc_0; + reg_out_mt_0 <= o_mt_0; + reg_out_ct_0 <= ct_hold_0; + reg_Ct_1_1 <= Ct_1_1; + reg_WixrXtYt_1_1 <= WixrXtYt_1_1; + reg_Wic_1 <= Wic_1; + reg_bi_1 <= bi_1; + reg_WfxrXtYt_1_1 <= WfxrXtYt_1_1; + reg_Wfc_1 <= Wfc_1; + reg_bf_1 <= bf_1; + reg_WoxrXtYt_1_1 <= WoxrXtYt_1_1; + reg_Woc_1 <= Woc_1; + reg_bo_1 <= bo_1; + reg_WcxrXtYt_1_1 <= WcxrXtYt_1_1; + reg_bc_1 <= bc_1; + reg_out_mt_1 <= o_mt_1; + reg_out_ct_1 <= ct_hold_1; + reg_Ct_1_2 <= Ct_1_2; + reg_WixrXtYt_1_2 <= WixrXtYt_1_2; + reg_Wic_2 <= Wic_2; + reg_bi_2 <= bi_2; + reg_WfxrXtYt_1_2 <= WfxrXtYt_1_2; + reg_Wfc_2 <= Wfc_2; + reg_bf_2 <= bf_2; + reg_WoxrXtYt_1_2 <= WoxrXtYt_1_2; + reg_Woc_2 <= Woc_2; + reg_bo_2 <= bo_2; + reg_WcxrXtYt_1_2 <= WcxrXtYt_1_2; + reg_bc_2 <= bc_2; + reg_out_mt_2 <= o_mt_2; + reg_out_ct_2 <= ct_hold_2; + reg_Ct_1_3 <= Ct_1_3; + reg_WixrXtYt_1_3 <= WixrXtYt_1_3; + reg_Wic_3 <= Wic_3; + reg_bi_3 <= bi_3; + reg_WfxrXtYt_1_3 <= WfxrXtYt_1_3; + reg_Wfc_3 <= Wfc_3; + reg_bf_3 <= bf_3; + reg_WoxrXtYt_1_3 <= WoxrXtYt_1_3; + reg_Woc_3 <= Woc_3; + reg_bo_3 <= bo_3; + reg_WcxrXtYt_1_3 <= WcxrXtYt_1_3; + reg_bc_3 <= bc_3; + reg_out_mt_3 <= o_mt_3; + reg_out_ct_3 <= ct_hold_3; + reg_Ct_1_4 <= Ct_1_4; + reg_WixrXtYt_1_4 <= WixrXtYt_1_4; + reg_Wic_4 <= Wic_4; + reg_bi_4 <= bi_4; + reg_WfxrXtYt_1_4 <= WfxrXtYt_1_4; + reg_Wfc_4 <= Wfc_4; + reg_bf_4 <= bf_4; + reg_WoxrXtYt_1_4 <= WoxrXtYt_1_4; + reg_Woc_4 <= Woc_4; + reg_bo_4 <= bo_4; + reg_WcxrXtYt_1_4 <= WcxrXtYt_1_4; + reg_bc_4 <= bc_4; + reg_out_mt_4 <= o_mt_4; + reg_out_ct_4 <= ct_hold_4; + reg_Ct_1_5 <= Ct_1_5; + reg_WixrXtYt_1_5 <= WixrXtYt_1_5; + reg_Wic_5 <= Wic_5; + reg_bi_5 <= bi_5; + reg_WfxrXtYt_1_5 <= WfxrXtYt_1_5; + reg_Wfc_5 <= Wfc_5; + reg_bf_5 <= bf_5; + reg_WoxrXtYt_1_5 <= WoxrXtYt_1_5; + reg_Woc_5 <= Woc_5; + reg_bo_5 <= bo_5; + reg_WcxrXtYt_1_5 <= WcxrXtYt_1_5; + reg_bc_5 <= bc_5; + reg_out_mt_5 <= o_mt_5; + reg_out_ct_5 <= ct_hold_5; + reg_Ct_1_6 <= Ct_1_6; + reg_WixrXtYt_1_6 <= WixrXtYt_1_6; + reg_Wic_6 <= Wic_6; + reg_bi_6 <= bi_6; + reg_WfxrXtYt_1_6 <= WfxrXtYt_1_6; + reg_Wfc_6 <= Wfc_6; + reg_bf_6 <= bf_6; + reg_WoxrXtYt_1_6 <= WoxrXtYt_1_6; + reg_Woc_6 <= Woc_6; + reg_bo_6 <= bo_6; + reg_WcxrXtYt_1_6 <= WcxrXtYt_1_6; + reg_bc_6 <= bc_6; + reg_out_mt_6 <= o_mt_6; + reg_out_ct_6 <= ct_hold_6; + reg_Ct_1_7 <= Ct_1_7; + reg_WixrXtYt_1_7 <= WixrXtYt_1_7; + reg_Wic_7 <= Wic_7; + reg_bi_7 <= bi_7; + reg_WfxrXtYt_1_7 <= WfxrXtYt_1_7; + reg_Wfc_7 <= Wfc_7; + reg_bf_7 <= bf_7; + reg_WoxrXtYt_1_7 <= WoxrXtYt_1_7; + reg_Woc_7 <= Woc_7; + reg_bo_7 <= bo_7; + reg_WcxrXtYt_1_7 <= WcxrXtYt_1_7; + reg_bc_7 <= bc_7; + reg_out_mt_7 <= o_mt_7; + reg_out_ct_7 <= ct_hold_7; + reg_Ct_1_8 <= Ct_1_8; + reg_WixrXtYt_1_8 <= WixrXtYt_1_8; + reg_Wic_8 <= Wic_8; + reg_bi_8 <= bi_8; + reg_WfxrXtYt_1_8 <= WfxrXtYt_1_8; + reg_Wfc_8 <= Wfc_8; + reg_bf_8 <= bf_8; + reg_WoxrXtYt_1_8 <= WoxrXtYt_1_8; + reg_Woc_8 <= Woc_8; + reg_bo_8 <= bo_8; + reg_WcxrXtYt_1_8 <= WcxrXtYt_1_8; + reg_bc_8 <= bc_8; + reg_out_mt_8 <= o_mt_8; + reg_out_ct_8 <= ct_hold_8; + reg_Ct_1_9 <= Ct_1_9; + reg_WixrXtYt_1_9 <= WixrXtYt_1_9; + reg_Wic_9 <= Wic_9; + reg_bi_9 <= bi_9; + reg_WfxrXtYt_1_9 <= WfxrXtYt_1_9; + reg_Wfc_9 <= Wfc_9; + reg_bf_9 <= bf_9; + reg_WoxrXtYt_1_9 <= WoxrXtYt_1_9; + reg_Woc_9 <= Woc_9; + reg_bo_9 <= bo_9; + reg_WcxrXtYt_1_9 <= WcxrXtYt_1_9; + reg_bc_9 <= bc_9; + reg_out_mt_9 <= o_mt_9; + reg_out_ct_9 <= ct_hold_9; + reg_Ct_1_10 <= Ct_1_10; + reg_WixrXtYt_1_10 <= WixrXtYt_1_10; + reg_Wic_10 <= Wic_10; + reg_bi_10 <= bi_10; + reg_WfxrXtYt_1_10 <= WfxrXtYt_1_10; + reg_Wfc_10 <= Wfc_10; + reg_bf_10 <= bf_10; + reg_WoxrXtYt_1_10 <= WoxrXtYt_1_10; + reg_Woc_10 <= Woc_10; + reg_bo_10 <= bo_10; + reg_WcxrXtYt_1_10 <= WcxrXtYt_1_10; + reg_bc_10 <= bc_10; + reg_out_mt_10 <= o_mt_10; + reg_out_ct_10 <= ct_hold_10; + reg_Ct_1_11 <= Ct_1_11; + reg_WixrXtYt_1_11 <= WixrXtYt_1_11; + reg_Wic_11 <= Wic_11; + reg_bi_11 <= bi_11; + reg_WfxrXtYt_1_11 <= WfxrXtYt_1_11; + reg_Wfc_11 <= Wfc_11; + reg_bf_11 <= bf_11; + reg_WoxrXtYt_1_11 <= WoxrXtYt_1_11; + reg_Woc_11 <= Woc_11; + reg_bo_11 <= bo_11; + reg_WcxrXtYt_1_11 <= WcxrXtYt_1_11; + reg_bc_11 <= bc_11; + reg_out_mt_11 <= o_mt_11; + reg_out_ct_11 <= ct_hold_11; + reg_Ct_1_12 <= Ct_1_12; + reg_WixrXtYt_1_12 <= WixrXtYt_1_12; + reg_Wic_12 <= Wic_12; + reg_bi_12 <= bi_12; + reg_WfxrXtYt_1_12 <= WfxrXtYt_1_12; + reg_Wfc_12 <= Wfc_12; + reg_bf_12 <= bf_12; + reg_WoxrXtYt_1_12 <= WoxrXtYt_1_12; + reg_Woc_12 <= Woc_12; + reg_bo_12 <= bo_12; + reg_WcxrXtYt_1_12 <= WcxrXtYt_1_12; + reg_bc_12 <= bc_12; + reg_out_mt_12 <= o_mt_12; + reg_out_ct_12 <= ct_hold_12; + reg_Ct_1_13 <= Ct_1_13; + reg_WixrXtYt_1_13 <= WixrXtYt_1_13; + reg_Wic_13 <= Wic_13; + reg_bi_13 <= bi_13; + reg_WfxrXtYt_1_13 <= WfxrXtYt_1_13; + reg_Wfc_13 <= Wfc_13; + reg_bf_13 <= bf_13; + reg_WoxrXtYt_1_13 <= WoxrXtYt_1_13; + reg_Woc_13 <= Woc_13; + reg_bo_13 <= bo_13; + reg_WcxrXtYt_1_13 <= WcxrXtYt_1_13; + reg_bc_13 <= bc_13; + reg_out_mt_13 <= o_mt_13; + reg_out_ct_13 <= ct_hold_13; + reg_Ct_1_14 <= Ct_1_14; + reg_WixrXtYt_1_14 <= WixrXtYt_1_14; + reg_Wic_14 <= Wic_14; + reg_bi_14 <= bi_14; + reg_WfxrXtYt_1_14 <= WfxrXtYt_1_14; + reg_Wfc_14 <= Wfc_14; + reg_bf_14 <= bf_14; + reg_WoxrXtYt_1_14 <= WoxrXtYt_1_14; + reg_Woc_14 <= Woc_14; + reg_bo_14 <= bo_14; + reg_WcxrXtYt_1_14 <= WcxrXtYt_1_14; + reg_bc_14 <= bc_14; + reg_out_mt_14 <= o_mt_14; + reg_out_ct_14 <= ct_hold_14; + reg_Ct_1_15 <= Ct_1_15; + reg_WixrXtYt_1_15 <= WixrXtYt_1_15; + reg_Wic_15 <= Wic_15; + reg_bi_15 <= bi_15; + reg_WfxrXtYt_1_15 <= WfxrXtYt_1_15; + reg_Wfc_15 <= Wfc_15; + reg_bf_15 <= bf_15; + reg_WoxrXtYt_1_15 <= WoxrXtYt_1_15; + reg_Woc_15 <= Woc_15; + reg_bo_15 <= bo_15; + reg_WcxrXtYt_1_15 <= WcxrXtYt_1_15; + reg_bc_15 <= bc_15; + reg_out_mt_15 <= o_mt_15; + reg_out_ct_15 <= ct_hold_15; + reg_Ct_1_16 <= Ct_1_16; + reg_WixrXtYt_1_16 <= WixrXtYt_1_16; + reg_Wic_16 <= Wic_16; + reg_bi_16 <= bi_16; + reg_WfxrXtYt_1_16 <= WfxrXtYt_1_16; + reg_Wfc_16 <= Wfc_16; + reg_bf_16 <= bf_16; + reg_WoxrXtYt_1_16 <= WoxrXtYt_1_16; + reg_Woc_16 <= Woc_16; + reg_bo_16 <= bo_16; + reg_WcxrXtYt_1_16 <= WcxrXtYt_1_16; + reg_bc_16 <= bc_16; + reg_out_mt_16 <= o_mt_16; + reg_out_ct_16 <= ct_hold_16; + reg_Ct_1_17 <= Ct_1_17; + reg_WixrXtYt_1_17 <= WixrXtYt_1_17; + reg_Wic_17 <= Wic_17; + reg_bi_17 <= bi_17; + reg_WfxrXtYt_1_17 <= WfxrXtYt_1_17; + reg_Wfc_17 <= Wfc_17; + reg_bf_17 <= bf_17; + reg_WoxrXtYt_1_17 <= WoxrXtYt_1_17; + reg_Woc_17 <= Woc_17; + reg_bo_17 <= bo_17; + reg_WcxrXtYt_1_17 <= WcxrXtYt_1_17; + reg_bc_17 <= bc_17; + reg_out_mt_17 <= o_mt_17; + reg_out_ct_17 <= ct_hold_17; + reg_Ct_1_18 <= Ct_1_18; + reg_WixrXtYt_1_18 <= WixrXtYt_1_18; + reg_Wic_18 <= Wic_18; + reg_bi_18 <= bi_18; + reg_WfxrXtYt_1_18 <= WfxrXtYt_1_18; + reg_Wfc_18 <= Wfc_18; + reg_bf_18 <= bf_18; + reg_WoxrXtYt_1_18 <= WoxrXtYt_1_18; + reg_Woc_18 <= Woc_18; + reg_bo_18 <= bo_18; + reg_WcxrXtYt_1_18 <= WcxrXtYt_1_18; + reg_bc_18 <= bc_18; + reg_out_mt_18 <= o_mt_18; + reg_out_ct_18 <= ct_hold_18; + reg_Ct_1_19 <= Ct_1_19; + reg_WixrXtYt_1_19 <= WixrXtYt_1_19; + reg_Wic_19 <= Wic_19; + reg_bi_19 <= bi_19; + reg_WfxrXtYt_1_19 <= WfxrXtYt_1_19; + reg_Wfc_19 <= Wfc_19; + reg_bf_19 <= bf_19; + reg_WoxrXtYt_1_19 <= WoxrXtYt_1_19; + reg_Woc_19 <= Woc_19; + reg_bo_19 <= bo_19; + reg_WcxrXtYt_1_19 <= WcxrXtYt_1_19; + reg_bc_19 <= bc_19; + reg_out_mt_19 <= o_mt_19; + reg_out_ct_19 <= ct_hold_19; + reg_Ct_1_20 <= Ct_1_20; + reg_WixrXtYt_1_20 <= WixrXtYt_1_20; + reg_Wic_20 <= Wic_20; + reg_bi_20 <= bi_20; + reg_WfxrXtYt_1_20 <= WfxrXtYt_1_20; + reg_Wfc_20 <= Wfc_20; + reg_bf_20 <= bf_20; + reg_WoxrXtYt_1_20 <= WoxrXtYt_1_20; + reg_Woc_20 <= Woc_20; + reg_bo_20 <= bo_20; + reg_WcxrXtYt_1_20 <= WcxrXtYt_1_20; + reg_bc_20 <= bc_20; + reg_out_mt_20 <= o_mt_20; + reg_out_ct_20 <= ct_hold_20; + reg_Ct_1_21 <= Ct_1_21; + reg_WixrXtYt_1_21 <= WixrXtYt_1_21; + reg_Wic_21 <= Wic_21; + reg_bi_21 <= bi_21; + reg_WfxrXtYt_1_21 <= WfxrXtYt_1_21; + reg_Wfc_21 <= Wfc_21; + reg_bf_21 <= bf_21; + reg_WoxrXtYt_1_21 <= WoxrXtYt_1_21; + reg_Woc_21 <= Woc_21; + reg_bo_21 <= bo_21; + reg_WcxrXtYt_1_21 <= WcxrXtYt_1_21; + reg_bc_21 <= bc_21; + reg_out_mt_21 <= o_mt_21; + reg_out_ct_21 <= ct_hold_21; + reg_Ct_1_22 <= Ct_1_22; + reg_WixrXtYt_1_22 <= WixrXtYt_1_22; + reg_Wic_22 <= Wic_22; + reg_bi_22 <= bi_22; + reg_WfxrXtYt_1_22 <= WfxrXtYt_1_22; + reg_Wfc_22 <= Wfc_22; + reg_bf_22 <= bf_22; + reg_WoxrXtYt_1_22 <= WoxrXtYt_1_22; + reg_Woc_22 <= Woc_22; + reg_bo_22 <= bo_22; + reg_WcxrXtYt_1_22 <= WcxrXtYt_1_22; + reg_bc_22 <= bc_22; + reg_out_mt_22 <= o_mt_22; + reg_out_ct_22 <= ct_hold_22; + reg_Ct_1_23 <= Ct_1_23; + reg_WixrXtYt_1_23 <= WixrXtYt_1_23; + reg_Wic_23 <= Wic_23; + reg_bi_23 <= bi_23; + reg_WfxrXtYt_1_23 <= WfxrXtYt_1_23; + reg_Wfc_23 <= Wfc_23; + reg_bf_23 <= bf_23; + reg_WoxrXtYt_1_23 <= WoxrXtYt_1_23; + reg_Woc_23 <= Woc_23; + reg_bo_23 <= bo_23; + reg_WcxrXtYt_1_23 <= WcxrXtYt_1_23; + reg_bc_23 <= bc_23; + reg_out_mt_23 <= o_mt_23; + reg_out_ct_23 <= ct_hold_23; + reg_Ct_1_24 <= Ct_1_24; + reg_WixrXtYt_1_24 <= WixrXtYt_1_24; + reg_Wic_24 <= Wic_24; + reg_bi_24 <= bi_24; + reg_WfxrXtYt_1_24 <= WfxrXtYt_1_24; + reg_Wfc_24 <= Wfc_24; + reg_bf_24 <= bf_24; + reg_WoxrXtYt_1_24 <= WoxrXtYt_1_24; + reg_Woc_24 <= Woc_24; + reg_bo_24 <= bo_24; + reg_WcxrXtYt_1_24 <= WcxrXtYt_1_24; + reg_bc_24 <= bc_24; + reg_out_mt_24 <= o_mt_24; + reg_out_ct_24 <= ct_hold_24; + reg_Ct_1_25 <= Ct_1_25; + reg_WixrXtYt_1_25 <= WixrXtYt_1_25; + reg_Wic_25 <= Wic_25; + reg_bi_25 <= bi_25; + reg_WfxrXtYt_1_25 <= WfxrXtYt_1_25; + reg_Wfc_25 <= Wfc_25; + reg_bf_25 <= bf_25; + reg_WoxrXtYt_1_25 <= WoxrXtYt_1_25; + reg_Woc_25 <= Woc_25; + reg_bo_25 <= bo_25; + reg_WcxrXtYt_1_25 <= WcxrXtYt_1_25; + reg_bc_25 <= bc_25; + reg_out_mt_25 <= o_mt_25; + reg_out_ct_25 <= ct_hold_25; + reg_Ct_1_26 <= Ct_1_26; + reg_WixrXtYt_1_26 <= WixrXtYt_1_26; + reg_Wic_26 <= Wic_26; + reg_bi_26 <= bi_26; + reg_WfxrXtYt_1_26 <= WfxrXtYt_1_26; + reg_Wfc_26 <= Wfc_26; + reg_bf_26 <= bf_26; + reg_WoxrXtYt_1_26 <= WoxrXtYt_1_26; + reg_Woc_26 <= Woc_26; + reg_bo_26 <= bo_26; + reg_WcxrXtYt_1_26 <= WcxrXtYt_1_26; + reg_bc_26 <= bc_26; + reg_out_mt_26 <= o_mt_26; + reg_out_ct_26 <= ct_hold_26; + reg_Ct_1_27 <= Ct_1_27; + reg_WixrXtYt_1_27 <= WixrXtYt_1_27; + reg_Wic_27 <= Wic_27; + reg_bi_27 <= bi_27; + reg_WfxrXtYt_1_27 <= WfxrXtYt_1_27; + reg_Wfc_27 <= Wfc_27; + reg_bf_27 <= bf_27; + reg_WoxrXtYt_1_27 <= WoxrXtYt_1_27; + reg_Woc_27 <= Woc_27; + reg_bo_27 <= bo_27; + reg_WcxrXtYt_1_27 <= WcxrXtYt_1_27; + reg_bc_27 <= bc_27; + reg_out_mt_27 <= o_mt_27; + reg_out_ct_27 <= ct_hold_27; + reg_Ct_1_28 <= Ct_1_28; + reg_WixrXtYt_1_28 <= WixrXtYt_1_28; + reg_Wic_28 <= Wic_28; + reg_bi_28 <= bi_28; + reg_WfxrXtYt_1_28 <= WfxrXtYt_1_28; + reg_Wfc_28 <= Wfc_28; + reg_bf_28 <= bf_28; + reg_WoxrXtYt_1_28 <= WoxrXtYt_1_28; + reg_Woc_28 <= Woc_28; + reg_bo_28 <= bo_28; + reg_WcxrXtYt_1_28 <= WcxrXtYt_1_28; + reg_bc_28 <= bc_28; + reg_out_mt_28 <= o_mt_28; + reg_out_ct_28 <= ct_hold_28; + reg_Ct_1_29 <= Ct_1_29; + reg_WixrXtYt_1_29 <= WixrXtYt_1_29; + reg_Wic_29 <= Wic_29; + reg_bi_29 <= bi_29; + reg_WfxrXtYt_1_29 <= WfxrXtYt_1_29; + reg_Wfc_29 <= Wfc_29; + reg_bf_29 <= bf_29; + reg_WoxrXtYt_1_29 <= WoxrXtYt_1_29; + reg_Woc_29 <= Woc_29; + reg_bo_29 <= bo_29; + reg_WcxrXtYt_1_29 <= WcxrXtYt_1_29; + reg_bc_29 <= bc_29; + reg_out_mt_29 <= o_mt_29; + reg_out_ct_29 <= ct_hold_29; + reg_Ct_1_30 <= Ct_1_30; + reg_WixrXtYt_1_30 <= WixrXtYt_1_30; + reg_Wic_30 <= Wic_30; + reg_bi_30 <= bi_30; + reg_WfxrXtYt_1_30 <= WfxrXtYt_1_30; + reg_Wfc_30 <= Wfc_30; + reg_bf_30 <= bf_30; + reg_WoxrXtYt_1_30 <= WoxrXtYt_1_30; + reg_Woc_30 <= Woc_30; + reg_bo_30 <= bo_30; + reg_WcxrXtYt_1_30 <= WcxrXtYt_1_30; + reg_bc_30 <= bc_30; + reg_out_mt_30 <= o_mt_30; + reg_out_ct_30 <= ct_hold_30; + reg_Ct_1_31 <= Ct_1_31; + reg_WixrXtYt_1_31 <= WixrXtYt_1_31; + reg_Wic_31 <= Wic_31; + reg_bi_31 <= bi_31; + reg_WfxrXtYt_1_31 <= WfxrXtYt_1_31; + reg_Wfc_31 <= Wfc_31; + reg_bf_31 <= bf_31; + reg_WoxrXtYt_1_31 <= WoxrXtYt_1_31; + reg_Woc_31 <= Woc_31; + reg_bo_31 <= bo_31; + reg_WcxrXtYt_1_31 <= WcxrXtYt_1_31; + reg_bc_31 <= bc_31; + reg_out_mt_31 <= o_mt_31; + reg_out_ct_31 <= ct_hold_31; + reg_Ct_1_32 <= Ct_1_32; + reg_WixrXtYt_1_32 <= WixrXtYt_1_32; + reg_Wic_32 <= Wic_32; + reg_bi_32 <= bi_32; + reg_WfxrXtYt_1_32 <= WfxrXtYt_1_32; + reg_Wfc_32 <= Wfc_32; + reg_bf_32 <= bf_32; + reg_WoxrXtYt_1_32 <= WoxrXtYt_1_32; + reg_Woc_32 <= Woc_32; + reg_bo_32 <= bo_32; + reg_WcxrXtYt_1_32 <= WcxrXtYt_1_32; + reg_bc_32 <= bc_32; + reg_out_mt_32 <= o_mt_32; + reg_out_ct_32 <= ct_hold_32; + reg_Ct_1_33 <= Ct_1_33; + reg_WixrXtYt_1_33 <= WixrXtYt_1_33; + reg_Wic_33 <= Wic_33; + reg_bi_33 <= bi_33; + reg_WfxrXtYt_1_33 <= WfxrXtYt_1_33; + reg_Wfc_33 <= Wfc_33; + reg_bf_33 <= bf_33; + reg_WoxrXtYt_1_33 <= WoxrXtYt_1_33; + reg_Woc_33 <= Woc_33; + reg_bo_33 <= bo_33; + reg_WcxrXtYt_1_33 <= WcxrXtYt_1_33; + reg_bc_33 <= bc_33; + reg_out_mt_33 <= o_mt_33; + reg_out_ct_33 <= ct_hold_33; + reg_Ct_1_34 <= Ct_1_34; + reg_WixrXtYt_1_34 <= WixrXtYt_1_34; + reg_Wic_34 <= Wic_34; + reg_bi_34 <= bi_34; + reg_WfxrXtYt_1_34 <= WfxrXtYt_1_34; + reg_Wfc_34 <= Wfc_34; + reg_bf_34 <= bf_34; + reg_WoxrXtYt_1_34 <= WoxrXtYt_1_34; + reg_Woc_34 <= Woc_34; + reg_bo_34 <= bo_34; + reg_WcxrXtYt_1_34 <= WcxrXtYt_1_34; + reg_bc_34 <= bc_34; + reg_out_mt_34 <= o_mt_34; + reg_out_ct_34 <= ct_hold_34; + reg_Ct_1_35 <= Ct_1_35; + reg_WixrXtYt_1_35 <= WixrXtYt_1_35; + reg_Wic_35 <= Wic_35; + reg_bi_35 <= bi_35; + reg_WfxrXtYt_1_35 <= WfxrXtYt_1_35; + reg_Wfc_35 <= Wfc_35; + reg_bf_35 <= bf_35; + reg_WoxrXtYt_1_35 <= WoxrXtYt_1_35; + reg_Woc_35 <= Woc_35; + reg_bo_35 <= bo_35; + reg_WcxrXtYt_1_35 <= WcxrXtYt_1_35; + reg_bc_35 <= bc_35; + reg_out_mt_35 <= o_mt_35; + reg_out_ct_35 <= ct_hold_35; + reg_Ct_1_36 <= Ct_1_36; + reg_WixrXtYt_1_36 <= WixrXtYt_1_36; + reg_Wic_36 <= Wic_36; + reg_bi_36 <= bi_36; + reg_WfxrXtYt_1_36 <= WfxrXtYt_1_36; + reg_Wfc_36 <= Wfc_36; + reg_bf_36 <= bf_36; + reg_WoxrXtYt_1_36 <= WoxrXtYt_1_36; + reg_Woc_36 <= Woc_36; + reg_bo_36 <= bo_36; + reg_WcxrXtYt_1_36 <= WcxrXtYt_1_36; + reg_bc_36 <= bc_36; + reg_out_mt_36 <= o_mt_36; + reg_out_ct_36 <= ct_hold_36; + reg_Ct_1_37 <= Ct_1_37; + reg_WixrXtYt_1_37 <= WixrXtYt_1_37; + reg_Wic_37 <= Wic_37; + reg_bi_37 <= bi_37; + reg_WfxrXtYt_1_37 <= WfxrXtYt_1_37; + reg_Wfc_37 <= Wfc_37; + reg_bf_37 <= bf_37; + reg_WoxrXtYt_1_37 <= WoxrXtYt_1_37; + reg_Woc_37 <= Woc_37; + reg_bo_37 <= bo_37; + reg_WcxrXtYt_1_37 <= WcxrXtYt_1_37; + reg_bc_37 <= bc_37; + reg_out_mt_37 <= o_mt_37; + reg_out_ct_37 <= ct_hold_37; + reg_Ct_1_38 <= Ct_1_38; + reg_WixrXtYt_1_38 <= WixrXtYt_1_38; + reg_Wic_38 <= Wic_38; + reg_bi_38 <= bi_38; + reg_WfxrXtYt_1_38 <= WfxrXtYt_1_38; + reg_Wfc_38 <= Wfc_38; + reg_bf_38 <= bf_38; + reg_WoxrXtYt_1_38 <= WoxrXtYt_1_38; + reg_Woc_38 <= Woc_38; + reg_bo_38 <= bo_38; + reg_WcxrXtYt_1_38 <= WcxrXtYt_1_38; + reg_bc_38 <= bc_38; + reg_out_mt_38 <= o_mt_38; + reg_out_ct_38 <= ct_hold_38; + reg_Ct_1_39 <= Ct_1_39; + reg_WixrXtYt_1_39 <= WixrXtYt_1_39; + reg_Wic_39 <= Wic_39; + reg_bi_39 <= bi_39; + reg_WfxrXtYt_1_39 <= WfxrXtYt_1_39; + reg_Wfc_39 <= Wfc_39; + reg_bf_39 <= bf_39; + reg_WoxrXtYt_1_39 <= WoxrXtYt_1_39; + reg_Woc_39 <= Woc_39; + reg_bo_39 <= bo_39; + reg_WcxrXtYt_1_39 <= WcxrXtYt_1_39; + reg_bc_39 <= bc_39; + reg_out_mt_39 <= o_mt_39; + reg_out_ct_39 <= ct_hold_39; + reg_Ct_1_40 <= Ct_1_40; + reg_WixrXtYt_1_40 <= WixrXtYt_1_40; + reg_Wic_40 <= Wic_40; + reg_bi_40 <= bi_40; + reg_WfxrXtYt_1_40 <= WfxrXtYt_1_40; + reg_Wfc_40 <= Wfc_40; + reg_bf_40 <= bf_40; + reg_WoxrXtYt_1_40 <= WoxrXtYt_1_40; + reg_Woc_40 <= Woc_40; + reg_bo_40 <= bo_40; + reg_WcxrXtYt_1_40 <= WcxrXtYt_1_40; + reg_bc_40 <= bc_40; + reg_out_mt_40 <= o_mt_40; + reg_out_ct_40 <= ct_hold_40; + reg_Ct_1_41 <= Ct_1_41; + reg_WixrXtYt_1_41 <= WixrXtYt_1_41; + reg_Wic_41 <= Wic_41; + reg_bi_41 <= bi_41; + reg_WfxrXtYt_1_41 <= WfxrXtYt_1_41; + reg_Wfc_41 <= Wfc_41; + reg_bf_41 <= bf_41; + reg_WoxrXtYt_1_41 <= WoxrXtYt_1_41; + reg_Woc_41 <= Woc_41; + reg_bo_41 <= bo_41; + reg_WcxrXtYt_1_41 <= WcxrXtYt_1_41; + reg_bc_41 <= bc_41; + reg_out_mt_41 <= o_mt_41; + reg_out_ct_41 <= ct_hold_41; + reg_Ct_1_42 <= Ct_1_42; + reg_WixrXtYt_1_42 <= WixrXtYt_1_42; + reg_Wic_42 <= Wic_42; + reg_bi_42 <= bi_42; + reg_WfxrXtYt_1_42 <= WfxrXtYt_1_42; + reg_Wfc_42 <= Wfc_42; + reg_bf_42 <= bf_42; + reg_WoxrXtYt_1_42 <= WoxrXtYt_1_42; + reg_Woc_42 <= Woc_42; + reg_bo_42 <= bo_42; + reg_WcxrXtYt_1_42 <= WcxrXtYt_1_42; + reg_bc_42 <= bc_42; + reg_out_mt_42 <= o_mt_42; + reg_out_ct_42 <= ct_hold_42; + reg_Ct_1_43 <= Ct_1_43; + reg_WixrXtYt_1_43 <= WixrXtYt_1_43; + reg_Wic_43 <= Wic_43; + reg_bi_43 <= bi_43; + reg_WfxrXtYt_1_43 <= WfxrXtYt_1_43; + reg_Wfc_43 <= Wfc_43; + reg_bf_43 <= bf_43; + reg_WoxrXtYt_1_43 <= WoxrXtYt_1_43; + reg_Woc_43 <= Woc_43; + reg_bo_43 <= bo_43; + reg_WcxrXtYt_1_43 <= WcxrXtYt_1_43; + reg_bc_43 <= bc_43; + reg_out_mt_43 <= o_mt_43; + reg_out_ct_43 <= ct_hold_43; + reg_Ct_1_44 <= Ct_1_44; + reg_WixrXtYt_1_44 <= WixrXtYt_1_44; + reg_Wic_44 <= Wic_44; + reg_bi_44 <= bi_44; + reg_WfxrXtYt_1_44 <= WfxrXtYt_1_44; + reg_Wfc_44 <= Wfc_44; + reg_bf_44 <= bf_44; + reg_WoxrXtYt_1_44 <= WoxrXtYt_1_44; + reg_Woc_44 <= Woc_44; + reg_bo_44 <= bo_44; + reg_WcxrXtYt_1_44 <= WcxrXtYt_1_44; + reg_bc_44 <= bc_44; + reg_out_mt_44 <= o_mt_44; + reg_out_ct_44 <= ct_hold_44; + reg_Ct_1_45 <= Ct_1_45; + reg_WixrXtYt_1_45 <= WixrXtYt_1_45; + reg_Wic_45 <= Wic_45; + reg_bi_45 <= bi_45; + reg_WfxrXtYt_1_45 <= WfxrXtYt_1_45; + reg_Wfc_45 <= Wfc_45; + reg_bf_45 <= bf_45; + reg_WoxrXtYt_1_45 <= WoxrXtYt_1_45; + reg_Woc_45 <= Woc_45; + reg_bo_45 <= bo_45; + reg_WcxrXtYt_1_45 <= WcxrXtYt_1_45; + reg_bc_45 <= bc_45; + reg_out_mt_45 <= o_mt_45; + reg_out_ct_45 <= ct_hold_45; + reg_Ct_1_46 <= Ct_1_46; + reg_WixrXtYt_1_46 <= WixrXtYt_1_46; + reg_Wic_46 <= Wic_46; + reg_bi_46 <= bi_46; + reg_WfxrXtYt_1_46 <= WfxrXtYt_1_46; + reg_Wfc_46 <= Wfc_46; + reg_bf_46 <= bf_46; + reg_WoxrXtYt_1_46 <= WoxrXtYt_1_46; + reg_Woc_46 <= Woc_46; + reg_bo_46 <= bo_46; + reg_WcxrXtYt_1_46 <= WcxrXtYt_1_46; + reg_bc_46 <= bc_46; + reg_out_mt_46 <= o_mt_46; + reg_out_ct_46 <= ct_hold_46; + reg_Ct_1_47 <= Ct_1_47; + reg_WixrXtYt_1_47 <= WixrXtYt_1_47; + reg_Wic_47 <= Wic_47; + reg_bi_47 <= bi_47; + reg_WfxrXtYt_1_47 <= WfxrXtYt_1_47; + reg_Wfc_47 <= Wfc_47; + reg_bf_47 <= bf_47; + reg_WoxrXtYt_1_47 <= WoxrXtYt_1_47; + reg_Woc_47 <= Woc_47; + reg_bo_47 <= bo_47; + reg_WcxrXtYt_1_47 <= WcxrXtYt_1_47; + reg_bc_47 <= bc_47; + reg_out_mt_47 <= o_mt_47; + reg_out_ct_47 <= ct_hold_47; + end +end +assign out_mt_0 = reg_out_mt_0; +assign out_ct_0 = reg_out_ct_0; +assign out_mt_1 = reg_out_mt_1; +assign out_ct_1 = reg_out_ct_1; +assign out_mt_2 = reg_out_mt_2; +assign out_ct_2 = reg_out_ct_2; +assign out_mt_3 = reg_out_mt_3; +assign out_ct_3 = reg_out_ct_3; +assign out_mt_4 = reg_out_mt_4; +assign out_ct_4 = reg_out_ct_4; +assign out_mt_5 = reg_out_mt_5; +assign out_ct_5 = reg_out_ct_5; +assign out_mt_6 = reg_out_mt_6; +assign out_ct_6 = reg_out_ct_6; +assign out_mt_7 = reg_out_mt_7; +assign out_ct_7 = reg_out_ct_7; +assign out_mt_8 = reg_out_mt_8; +assign out_ct_8 = reg_out_ct_8; +assign out_mt_9 = reg_out_mt_9; +assign out_ct_9 = reg_out_ct_9; +assign out_mt_10 = reg_out_mt_10; +assign out_ct_10 = reg_out_ct_10; +assign out_mt_11 = reg_out_mt_11; +assign out_ct_11 = reg_out_ct_11; +assign out_mt_12 = reg_out_mt_12; +assign out_ct_12 = reg_out_ct_12; +assign out_mt_13 = reg_out_mt_13; +assign out_ct_13 = reg_out_ct_13; +assign out_mt_14 = reg_out_mt_14; +assign out_ct_14 = reg_out_ct_14; +assign out_mt_15 = reg_out_mt_15; +assign out_ct_15 = reg_out_ct_15; +assign out_mt_16 = reg_out_mt_16; +assign out_ct_16 = reg_out_ct_16; +assign out_mt_17 = reg_out_mt_17; +assign out_ct_17 = reg_out_ct_17; +assign out_mt_18 = reg_out_mt_18; +assign out_ct_18 = reg_out_ct_18; +assign out_mt_19 = reg_out_mt_19; +assign out_ct_19 = reg_out_ct_19; +assign out_mt_20 = reg_out_mt_20; +assign out_ct_20 = reg_out_ct_20; +assign out_mt_21 = reg_out_mt_21; +assign out_ct_21 = reg_out_ct_21; +assign out_mt_22 = reg_out_mt_22; +assign out_ct_22 = reg_out_ct_22; +assign out_mt_23 = reg_out_mt_23; +assign out_ct_23 = reg_out_ct_23; +assign out_mt_24 = reg_out_mt_24; +assign out_ct_24 = reg_out_ct_24; +assign out_mt_25 = reg_out_mt_25; +assign out_ct_25 = reg_out_ct_25; +assign out_mt_26 = reg_out_mt_26; +assign out_ct_26 = reg_out_ct_26; +assign out_mt_27 = reg_out_mt_27; +assign out_ct_27 = reg_out_ct_27; +assign out_mt_28 = reg_out_mt_28; +assign out_ct_28 = reg_out_ct_28; +assign out_mt_29 = reg_out_mt_29; +assign out_ct_29 = reg_out_ct_29; +assign out_mt_30 = reg_out_mt_30; +assign out_ct_30 = reg_out_ct_30; +assign out_mt_31 = reg_out_mt_31; +assign out_ct_31 = reg_out_ct_31; +assign out_mt_32 = reg_out_mt_32; +assign out_ct_32 = reg_out_ct_32; +assign out_mt_33 = reg_out_mt_33; +assign out_ct_33 = reg_out_ct_33; +assign out_mt_34 = reg_out_mt_34; +assign out_ct_34 = reg_out_ct_34; +assign out_mt_35 = reg_out_mt_35; +assign out_ct_35 = reg_out_ct_35; +assign out_mt_36 = reg_out_mt_36; +assign out_ct_36 = reg_out_ct_36; +assign out_mt_37 = reg_out_mt_37; +assign out_ct_37 = reg_out_ct_37; +assign out_mt_38 = reg_out_mt_38; +assign out_ct_38 = reg_out_ct_38; +assign out_mt_39 = reg_out_mt_39; +assign out_ct_39 = reg_out_ct_39; +assign out_mt_40 = reg_out_mt_40; +assign out_ct_40 = reg_out_ct_40; +assign out_mt_41 = reg_out_mt_41; +assign out_ct_41 = reg_out_ct_41; +assign out_mt_42 = reg_out_mt_42; +assign out_ct_42 = reg_out_ct_42; +assign out_mt_43 = reg_out_mt_43; +assign out_ct_43 = reg_out_ct_43; +assign out_mt_44 = reg_out_mt_44; +assign out_ct_44 = reg_out_ct_44; +assign out_mt_45 = reg_out_mt_45; +assign out_ct_45 = reg_out_ct_45; +assign out_mt_46 = reg_out_mt_46; +assign out_ct_46 = reg_out_ct_46; +assign out_mt_47 = reg_out_mt_47; +assign out_ct_47 = reg_out_ct_47; +assign o_valid = reg_o_valid; +assign o_ready = enable; +endmodule + +module lstm_gate_18_10_48_1 ( + input clk, + input reset, + input i_ready, + input i_valid, + input [17:0] stage1_result_0, + input [17:0] weight_0, + input [17:0] Ct_1_0, + input [17:0] bias_0, + output [17:0] gate_output_0, + input [17:0] stage1_result_1, + input [17:0] weight_1, + input [17:0] Ct_1_1, + input [17:0] bias_1, + output [17:0] gate_output_1, + input [17:0] stage1_result_2, + input [17:0] weight_2, + input [17:0] Ct_1_2, + input [17:0] bias_2, + output [17:0] gate_output_2, + input [17:0] stage1_result_3, + input [17:0] weight_3, + input [17:0] Ct_1_3, + input [17:0] bias_3, + output [17:0] gate_output_3, + input [17:0] stage1_result_4, + input [17:0] weight_4, + input [17:0] Ct_1_4, + input [17:0] bias_4, + output [17:0] gate_output_4, + input [17:0] stage1_result_5, + input [17:0] weight_5, + input [17:0] Ct_1_5, + input [17:0] bias_5, + output [17:0] gate_output_5, + input [17:0] stage1_result_6, + input [17:0] weight_6, + input [17:0] Ct_1_6, + input [17:0] bias_6, + output [17:0] gate_output_6, + input [17:0] stage1_result_7, + input [17:0] weight_7, + input [17:0] Ct_1_7, + input [17:0] bias_7, + output [17:0] gate_output_7, + input [17:0] stage1_result_8, + input [17:0] weight_8, + input [17:0] Ct_1_8, + input [17:0] bias_8, + output [17:0] gate_output_8, + input [17:0] stage1_result_9, + input [17:0] weight_9, + input [17:0] Ct_1_9, + input [17:0] bias_9, + output [17:0] gate_output_9, + input [17:0] stage1_result_10, + input [17:0] weight_10, + input [17:0] Ct_1_10, + input [17:0] bias_10, + output [17:0] gate_output_10, + input [17:0] stage1_result_11, + input [17:0] weight_11, + input [17:0] Ct_1_11, + input [17:0] bias_11, + output [17:0] gate_output_11, + input [17:0] stage1_result_12, + input [17:0] weight_12, + input [17:0] Ct_1_12, + input [17:0] bias_12, + output [17:0] gate_output_12, + input [17:0] stage1_result_13, + input [17:0] weight_13, + input [17:0] Ct_1_13, + input [17:0] bias_13, + output [17:0] gate_output_13, + input [17:0] stage1_result_14, + input [17:0] weight_14, + input [17:0] Ct_1_14, + input [17:0] bias_14, + output [17:0] gate_output_14, + input [17:0] stage1_result_15, + input [17:0] weight_15, + input [17:0] Ct_1_15, + input [17:0] bias_15, + output [17:0] gate_output_15, + input [17:0] stage1_result_16, + input [17:0] weight_16, + input [17:0] Ct_1_16, + input [17:0] bias_16, + output [17:0] gate_output_16, + input [17:0] stage1_result_17, + input [17:0] weight_17, + input [17:0] Ct_1_17, + input [17:0] bias_17, + output [17:0] gate_output_17, + input [17:0] stage1_result_18, + input [17:0] weight_18, + input [17:0] Ct_1_18, + input [17:0] bias_18, + output [17:0] gate_output_18, + input [17:0] stage1_result_19, + input [17:0] weight_19, + input [17:0] Ct_1_19, + input [17:0] bias_19, + output [17:0] gate_output_19, + input [17:0] stage1_result_20, + input [17:0] weight_20, + input [17:0] Ct_1_20, + input [17:0] bias_20, + output [17:0] gate_output_20, + input [17:0] stage1_result_21, + input [17:0] weight_21, + input [17:0] Ct_1_21, + input [17:0] bias_21, + output [17:0] gate_output_21, + input [17:0] stage1_result_22, + input [17:0] weight_22, + input [17:0] Ct_1_22, + input [17:0] bias_22, + output [17:0] gate_output_22, + input [17:0] stage1_result_23, + input [17:0] weight_23, + input [17:0] Ct_1_23, + input [17:0] bias_23, + output [17:0] gate_output_23, + input [17:0] stage1_result_24, + input [17:0] weight_24, + input [17:0] Ct_1_24, + input [17:0] bias_24, + output [17:0] gate_output_24, + input [17:0] stage1_result_25, + input [17:0] weight_25, + input [17:0] Ct_1_25, + input [17:0] bias_25, + output [17:0] gate_output_25, + input [17:0] stage1_result_26, + input [17:0] weight_26, + input [17:0] Ct_1_26, + input [17:0] bias_26, + output [17:0] gate_output_26, + input [17:0] stage1_result_27, + input [17:0] weight_27, + input [17:0] Ct_1_27, + input [17:0] bias_27, + output [17:0] gate_output_27, + input [17:0] stage1_result_28, + input [17:0] weight_28, + input [17:0] Ct_1_28, + input [17:0] bias_28, + output [17:0] gate_output_28, + input [17:0] stage1_result_29, + input [17:0] weight_29, + input [17:0] Ct_1_29, + input [17:0] bias_29, + output [17:0] gate_output_29, + input [17:0] stage1_result_30, + input [17:0] weight_30, + input [17:0] Ct_1_30, + input [17:0] bias_30, + output [17:0] gate_output_30, + input [17:0] stage1_result_31, + input [17:0] weight_31, + input [17:0] Ct_1_31, + input [17:0] bias_31, + output [17:0] gate_output_31, + input [17:0] stage1_result_32, + input [17:0] weight_32, + input [17:0] Ct_1_32, + input [17:0] bias_32, + output [17:0] gate_output_32, + input [17:0] stage1_result_33, + input [17:0] weight_33, + input [17:0] Ct_1_33, + input [17:0] bias_33, + output [17:0] gate_output_33, + input [17:0] stage1_result_34, + input [17:0] weight_34, + input [17:0] Ct_1_34, + input [17:0] bias_34, + output [17:0] gate_output_34, + input [17:0] stage1_result_35, + input [17:0] weight_35, + input [17:0] Ct_1_35, + input [17:0] bias_35, + output [17:0] gate_output_35, + input [17:0] stage1_result_36, + input [17:0] weight_36, + input [17:0] Ct_1_36, + input [17:0] bias_36, + output [17:0] gate_output_36, + input [17:0] stage1_result_37, + input [17:0] weight_37, + input [17:0] Ct_1_37, + input [17:0] bias_37, + output [17:0] gate_output_37, + input [17:0] stage1_result_38, + input [17:0] weight_38, + input [17:0] Ct_1_38, + input [17:0] bias_38, + output [17:0] gate_output_38, + input [17:0] stage1_result_39, + input [17:0] weight_39, + input [17:0] Ct_1_39, + input [17:0] bias_39, + output [17:0] gate_output_39, + input [17:0] stage1_result_40, + input [17:0] weight_40, + input [17:0] Ct_1_40, + input [17:0] bias_40, + output [17:0] gate_output_40, + input [17:0] stage1_result_41, + input [17:0] weight_41, + input [17:0] Ct_1_41, + input [17:0] bias_41, + output [17:0] gate_output_41, + input [17:0] stage1_result_42, + input [17:0] weight_42, + input [17:0] Ct_1_42, + input [17:0] bias_42, + output [17:0] gate_output_42, + input [17:0] stage1_result_43, + input [17:0] weight_43, + input [17:0] Ct_1_43, + input [17:0] bias_43, + output [17:0] gate_output_43, + input [17:0] stage1_result_44, + input [17:0] weight_44, + input [17:0] Ct_1_44, + input [17:0] bias_44, + output [17:0] gate_output_44, + input [17:0] stage1_result_45, + input [17:0] weight_45, + input [17:0] Ct_1_45, + input [17:0] bias_45, + output [17:0] gate_output_45, + input [17:0] stage1_result_46, + input [17:0] weight_46, + input [17:0] Ct_1_46, + input [17:0] bias_46, + output [17:0] gate_output_46, + input [17:0] stage1_result_47, + input [17:0] weight_47, + input [17:0] Ct_1_47, + input [17:0] bias_47, + output [17:0] gate_output_47, + output o_valid, + output o_ready +); + +wire mult_valid, add0_valid, add1_valid, add2_valid; +wire mult_ready, add0_ready, add1_ready, add2_ready; +wire sigmoid_valid_0, sigmoid_ready_0; +wire [17:0] o_mult_0; +wire [17:0] o_add0_0; +wire [17:0] o_add1_0; +wire [17:0] add1_hold_0; +wire [17:0] o_add2_0; +wire [17:0] o_sigmoid_0; +wire sigmoid_valid_1, sigmoid_ready_1; +wire [17:0] o_mult_1; +wire [17:0] o_add0_1; +wire [17:0] o_add1_1; +wire [17:0] add1_hold_1; +wire [17:0] o_add2_1; +wire [17:0] o_sigmoid_1; +wire sigmoid_valid_2, sigmoid_ready_2; +wire [17:0] o_mult_2; +wire [17:0] o_add0_2; +wire [17:0] o_add1_2; +wire [17:0] add1_hold_2; +wire [17:0] o_add2_2; +wire [17:0] o_sigmoid_2; +wire sigmoid_valid_3, sigmoid_ready_3; +wire [17:0] o_mult_3; +wire [17:0] o_add0_3; +wire [17:0] o_add1_3; +wire [17:0] add1_hold_3; +wire [17:0] o_add2_3; +wire [17:0] o_sigmoid_3; +wire sigmoid_valid_4, sigmoid_ready_4; +wire [17:0] o_mult_4; +wire [17:0] o_add0_4; +wire [17:0] o_add1_4; +wire [17:0] add1_hold_4; +wire [17:0] o_add2_4; +wire [17:0] o_sigmoid_4; +wire sigmoid_valid_5, sigmoid_ready_5; +wire [17:0] o_mult_5; +wire [17:0] o_add0_5; +wire [17:0] o_add1_5; +wire [17:0] add1_hold_5; +wire [17:0] o_add2_5; +wire [17:0] o_sigmoid_5; +wire sigmoid_valid_6, sigmoid_ready_6; +wire [17:0] o_mult_6; +wire [17:0] o_add0_6; +wire [17:0] o_add1_6; +wire [17:0] add1_hold_6; +wire [17:0] o_add2_6; +wire [17:0] o_sigmoid_6; +wire sigmoid_valid_7, sigmoid_ready_7; +wire [17:0] o_mult_7; +wire [17:0] o_add0_7; +wire [17:0] o_add1_7; +wire [17:0] add1_hold_7; +wire [17:0] o_add2_7; +wire [17:0] o_sigmoid_7; +wire sigmoid_valid_8, sigmoid_ready_8; +wire [17:0] o_mult_8; +wire [17:0] o_add0_8; +wire [17:0] o_add1_8; +wire [17:0] add1_hold_8; +wire [17:0] o_add2_8; +wire [17:0] o_sigmoid_8; +wire sigmoid_valid_9, sigmoid_ready_9; +wire [17:0] o_mult_9; +wire [17:0] o_add0_9; +wire [17:0] o_add1_9; +wire [17:0] add1_hold_9; +wire [17:0] o_add2_9; +wire [17:0] o_sigmoid_9; +wire sigmoid_valid_10, sigmoid_ready_10; +wire [17:0] o_mult_10; +wire [17:0] o_add0_10; +wire [17:0] o_add1_10; +wire [17:0] add1_hold_10; +wire [17:0] o_add2_10; +wire [17:0] o_sigmoid_10; +wire sigmoid_valid_11, sigmoid_ready_11; +wire [17:0] o_mult_11; +wire [17:0] o_add0_11; +wire [17:0] o_add1_11; +wire [17:0] add1_hold_11; +wire [17:0] o_add2_11; +wire [17:0] o_sigmoid_11; +wire sigmoid_valid_12, sigmoid_ready_12; +wire [17:0] o_mult_12; +wire [17:0] o_add0_12; +wire [17:0] o_add1_12; +wire [17:0] add1_hold_12; +wire [17:0] o_add2_12; +wire [17:0] o_sigmoid_12; +wire sigmoid_valid_13, sigmoid_ready_13; +wire [17:0] o_mult_13; +wire [17:0] o_add0_13; +wire [17:0] o_add1_13; +wire [17:0] add1_hold_13; +wire [17:0] o_add2_13; +wire [17:0] o_sigmoid_13; +wire sigmoid_valid_14, sigmoid_ready_14; +wire [17:0] o_mult_14; +wire [17:0] o_add0_14; +wire [17:0] o_add1_14; +wire [17:0] add1_hold_14; +wire [17:0] o_add2_14; +wire [17:0] o_sigmoid_14; +wire sigmoid_valid_15, sigmoid_ready_15; +wire [17:0] o_mult_15; +wire [17:0] o_add0_15; +wire [17:0] o_add1_15; +wire [17:0] add1_hold_15; +wire [17:0] o_add2_15; +wire [17:0] o_sigmoid_15; +wire sigmoid_valid_16, sigmoid_ready_16; +wire [17:0] o_mult_16; +wire [17:0] o_add0_16; +wire [17:0] o_add1_16; +wire [17:0] add1_hold_16; +wire [17:0] o_add2_16; +wire [17:0] o_sigmoid_16; +wire sigmoid_valid_17, sigmoid_ready_17; +wire [17:0] o_mult_17; +wire [17:0] o_add0_17; +wire [17:0] o_add1_17; +wire [17:0] add1_hold_17; +wire [17:0] o_add2_17; +wire [17:0] o_sigmoid_17; +wire sigmoid_valid_18, sigmoid_ready_18; +wire [17:0] o_mult_18; +wire [17:0] o_add0_18; +wire [17:0] o_add1_18; +wire [17:0] add1_hold_18; +wire [17:0] o_add2_18; +wire [17:0] o_sigmoid_18; +wire sigmoid_valid_19, sigmoid_ready_19; +wire [17:0] o_mult_19; +wire [17:0] o_add0_19; +wire [17:0] o_add1_19; +wire [17:0] add1_hold_19; +wire [17:0] o_add2_19; +wire [17:0] o_sigmoid_19; +wire sigmoid_valid_20, sigmoid_ready_20; +wire [17:0] o_mult_20; +wire [17:0] o_add0_20; +wire [17:0] o_add1_20; +wire [17:0] add1_hold_20; +wire [17:0] o_add2_20; +wire [17:0] o_sigmoid_20; +wire sigmoid_valid_21, sigmoid_ready_21; +wire [17:0] o_mult_21; +wire [17:0] o_add0_21; +wire [17:0] o_add1_21; +wire [17:0] add1_hold_21; +wire [17:0] o_add2_21; +wire [17:0] o_sigmoid_21; +wire sigmoid_valid_22, sigmoid_ready_22; +wire [17:0] o_mult_22; +wire [17:0] o_add0_22; +wire [17:0] o_add1_22; +wire [17:0] add1_hold_22; +wire [17:0] o_add2_22; +wire [17:0] o_sigmoid_22; +wire sigmoid_valid_23, sigmoid_ready_23; +wire [17:0] o_mult_23; +wire [17:0] o_add0_23; +wire [17:0] o_add1_23; +wire [17:0] add1_hold_23; +wire [17:0] o_add2_23; +wire [17:0] o_sigmoid_23; +wire sigmoid_valid_24, sigmoid_ready_24; +wire [17:0] o_mult_24; +wire [17:0] o_add0_24; +wire [17:0] o_add1_24; +wire [17:0] add1_hold_24; +wire [17:0] o_add2_24; +wire [17:0] o_sigmoid_24; +wire sigmoid_valid_25, sigmoid_ready_25; +wire [17:0] o_mult_25; +wire [17:0] o_add0_25; +wire [17:0] o_add1_25; +wire [17:0] add1_hold_25; +wire [17:0] o_add2_25; +wire [17:0] o_sigmoid_25; +wire sigmoid_valid_26, sigmoid_ready_26; +wire [17:0] o_mult_26; +wire [17:0] o_add0_26; +wire [17:0] o_add1_26; +wire [17:0] add1_hold_26; +wire [17:0] o_add2_26; +wire [17:0] o_sigmoid_26; +wire sigmoid_valid_27, sigmoid_ready_27; +wire [17:0] o_mult_27; +wire [17:0] o_add0_27; +wire [17:0] o_add1_27; +wire [17:0] add1_hold_27; +wire [17:0] o_add2_27; +wire [17:0] o_sigmoid_27; +wire sigmoid_valid_28, sigmoid_ready_28; +wire [17:0] o_mult_28; +wire [17:0] o_add0_28; +wire [17:0] o_add1_28; +wire [17:0] add1_hold_28; +wire [17:0] o_add2_28; +wire [17:0] o_sigmoid_28; +wire sigmoid_valid_29, sigmoid_ready_29; +wire [17:0] o_mult_29; +wire [17:0] o_add0_29; +wire [17:0] o_add1_29; +wire [17:0] add1_hold_29; +wire [17:0] o_add2_29; +wire [17:0] o_sigmoid_29; +wire sigmoid_valid_30, sigmoid_ready_30; +wire [17:0] o_mult_30; +wire [17:0] o_add0_30; +wire [17:0] o_add1_30; +wire [17:0] add1_hold_30; +wire [17:0] o_add2_30; +wire [17:0] o_sigmoid_30; +wire sigmoid_valid_31, sigmoid_ready_31; +wire [17:0] o_mult_31; +wire [17:0] o_add0_31; +wire [17:0] o_add1_31; +wire [17:0] add1_hold_31; +wire [17:0] o_add2_31; +wire [17:0] o_sigmoid_31; +wire sigmoid_valid_32, sigmoid_ready_32; +wire [17:0] o_mult_32; +wire [17:0] o_add0_32; +wire [17:0] o_add1_32; +wire [17:0] add1_hold_32; +wire [17:0] o_add2_32; +wire [17:0] o_sigmoid_32; +wire sigmoid_valid_33, sigmoid_ready_33; +wire [17:0] o_mult_33; +wire [17:0] o_add0_33; +wire [17:0] o_add1_33; +wire [17:0] add1_hold_33; +wire [17:0] o_add2_33; +wire [17:0] o_sigmoid_33; +wire sigmoid_valid_34, sigmoid_ready_34; +wire [17:0] o_mult_34; +wire [17:0] o_add0_34; +wire [17:0] o_add1_34; +wire [17:0] add1_hold_34; +wire [17:0] o_add2_34; +wire [17:0] o_sigmoid_34; +wire sigmoid_valid_35, sigmoid_ready_35; +wire [17:0] o_mult_35; +wire [17:0] o_add0_35; +wire [17:0] o_add1_35; +wire [17:0] add1_hold_35; +wire [17:0] o_add2_35; +wire [17:0] o_sigmoid_35; +wire sigmoid_valid_36, sigmoid_ready_36; +wire [17:0] o_mult_36; +wire [17:0] o_add0_36; +wire [17:0] o_add1_36; +wire [17:0] add1_hold_36; +wire [17:0] o_add2_36; +wire [17:0] o_sigmoid_36; +wire sigmoid_valid_37, sigmoid_ready_37; +wire [17:0] o_mult_37; +wire [17:0] o_add0_37; +wire [17:0] o_add1_37; +wire [17:0] add1_hold_37; +wire [17:0] o_add2_37; +wire [17:0] o_sigmoid_37; +wire sigmoid_valid_38, sigmoid_ready_38; +wire [17:0] o_mult_38; +wire [17:0] o_add0_38; +wire [17:0] o_add1_38; +wire [17:0] add1_hold_38; +wire [17:0] o_add2_38; +wire [17:0] o_sigmoid_38; +wire sigmoid_valid_39, sigmoid_ready_39; +wire [17:0] o_mult_39; +wire [17:0] o_add0_39; +wire [17:0] o_add1_39; +wire [17:0] add1_hold_39; +wire [17:0] o_add2_39; +wire [17:0] o_sigmoid_39; +wire sigmoid_valid_40, sigmoid_ready_40; +wire [17:0] o_mult_40; +wire [17:0] o_add0_40; +wire [17:0] o_add1_40; +wire [17:0] add1_hold_40; +wire [17:0] o_add2_40; +wire [17:0] o_sigmoid_40; +wire sigmoid_valid_41, sigmoid_ready_41; +wire [17:0] o_mult_41; +wire [17:0] o_add0_41; +wire [17:0] o_add1_41; +wire [17:0] add1_hold_41; +wire [17:0] o_add2_41; +wire [17:0] o_sigmoid_41; +wire sigmoid_valid_42, sigmoid_ready_42; +wire [17:0] o_mult_42; +wire [17:0] o_add0_42; +wire [17:0] o_add1_42; +wire [17:0] add1_hold_42; +wire [17:0] o_add2_42; +wire [17:0] o_sigmoid_42; +wire sigmoid_valid_43, sigmoid_ready_43; +wire [17:0] o_mult_43; +wire [17:0] o_add0_43; +wire [17:0] o_add1_43; +wire [17:0] add1_hold_43; +wire [17:0] o_add2_43; +wire [17:0] o_sigmoid_43; +wire sigmoid_valid_44, sigmoid_ready_44; +wire [17:0] o_mult_44; +wire [17:0] o_add0_44; +wire [17:0] o_add1_44; +wire [17:0] add1_hold_44; +wire [17:0] o_add2_44; +wire [17:0] o_sigmoid_44; +wire sigmoid_valid_45, sigmoid_ready_45; +wire [17:0] o_mult_45; +wire [17:0] o_add0_45; +wire [17:0] o_add1_45; +wire [17:0] add1_hold_45; +wire [17:0] o_add2_45; +wire [17:0] o_sigmoid_45; +wire sigmoid_valid_46, sigmoid_ready_46; +wire [17:0] o_mult_46; +wire [17:0] o_add0_46; +wire [17:0] o_add1_46; +wire [17:0] add1_hold_46; +wire [17:0] o_add2_46; +wire [17:0] o_sigmoid_46; +wire sigmoid_valid_47, sigmoid_ready_47; +wire [17:0] o_mult_47; +wire [17:0] o_add0_47; +wire [17:0] o_add1_47; +wire [17:0] add1_hold_47; +wire [17:0] o_add2_47; +wire [17:0] o_sigmoid_47; +wire enable; +assign enable = i_ready; + +elementwise_mult_core_18_18_10_48_1 elementwise_mult_core_18_18_10_48_1_mult ( + .clk(clk), + .reset(reset), + .i_valid(i_valid), + .i_ready(add2_ready), + .i_A_0(weight_0), + .i_B_0(Ct_1_0), + .o_C_0(o_mult_0), + .i_A_1(weight_1), + .i_B_1(Ct_1_1), + .o_C_1(o_mult_1), + .i_A_2(weight_2), + .i_B_2(Ct_1_2), + .o_C_2(o_mult_2), + .i_A_3(weight_3), + .i_B_3(Ct_1_3), + .o_C_3(o_mult_3), + .i_A_4(weight_4), + .i_B_4(Ct_1_4), + .o_C_4(o_mult_4), + .i_A_5(weight_5), + .i_B_5(Ct_1_5), + .o_C_5(o_mult_5), + .i_A_6(weight_6), + .i_B_6(Ct_1_6), + .o_C_6(o_mult_6), + .i_A_7(weight_7), + .i_B_7(Ct_1_7), + .o_C_7(o_mult_7), + .i_A_8(weight_8), + .i_B_8(Ct_1_8), + .o_C_8(o_mult_8), + .i_A_9(weight_9), + .i_B_9(Ct_1_9), + .o_C_9(o_mult_9), + .i_A_10(weight_10), + .i_B_10(Ct_1_10), + .o_C_10(o_mult_10), + .i_A_11(weight_11), + .i_B_11(Ct_1_11), + .o_C_11(o_mult_11), + .i_A_12(weight_12), + .i_B_12(Ct_1_12), + .o_C_12(o_mult_12), + .i_A_13(weight_13), + .i_B_13(Ct_1_13), + .o_C_13(o_mult_13), + .i_A_14(weight_14), + .i_B_14(Ct_1_14), + .o_C_14(o_mult_14), + .i_A_15(weight_15), + .i_B_15(Ct_1_15), + .o_C_15(o_mult_15), + .i_A_16(weight_16), + .i_B_16(Ct_1_16), + .o_C_16(o_mult_16), + .i_A_17(weight_17), + .i_B_17(Ct_1_17), + .o_C_17(o_mult_17), + .i_A_18(weight_18), + .i_B_18(Ct_1_18), + .o_C_18(o_mult_18), + .i_A_19(weight_19), + .i_B_19(Ct_1_19), + .o_C_19(o_mult_19), + .i_A_20(weight_20), + .i_B_20(Ct_1_20), + .o_C_20(o_mult_20), + .i_A_21(weight_21), + .i_B_21(Ct_1_21), + .o_C_21(o_mult_21), + .i_A_22(weight_22), + .i_B_22(Ct_1_22), + .o_C_22(o_mult_22), + .i_A_23(weight_23), + .i_B_23(Ct_1_23), + .o_C_23(o_mult_23), + .i_A_24(weight_24), + .i_B_24(Ct_1_24), + .o_C_24(o_mult_24), + .i_A_25(weight_25), + .i_B_25(Ct_1_25), + .o_C_25(o_mult_25), + .i_A_26(weight_26), + .i_B_26(Ct_1_26), + .o_C_26(o_mult_26), + .i_A_27(weight_27), + .i_B_27(Ct_1_27), + .o_C_27(o_mult_27), + .i_A_28(weight_28), + .i_B_28(Ct_1_28), + .o_C_28(o_mult_28), + .i_A_29(weight_29), + .i_B_29(Ct_1_29), + .o_C_29(o_mult_29), + .i_A_30(weight_30), + .i_B_30(Ct_1_30), + .o_C_30(o_mult_30), + .i_A_31(weight_31), + .i_B_31(Ct_1_31), + .o_C_31(o_mult_31), + .i_A_32(weight_32), + .i_B_32(Ct_1_32), + .o_C_32(o_mult_32), + .i_A_33(weight_33), + .i_B_33(Ct_1_33), + .o_C_33(o_mult_33), + .i_A_34(weight_34), + .i_B_34(Ct_1_34), + .o_C_34(o_mult_34), + .i_A_35(weight_35), + .i_B_35(Ct_1_35), + .o_C_35(o_mult_35), + .i_A_36(weight_36), + .i_B_36(Ct_1_36), + .o_C_36(o_mult_36), + .i_A_37(weight_37), + .i_B_37(Ct_1_37), + .o_C_37(o_mult_37), + .i_A_38(weight_38), + .i_B_38(Ct_1_38), + .o_C_38(o_mult_38), + .i_A_39(weight_39), + .i_B_39(Ct_1_39), + .o_C_39(o_mult_39), + .i_A_40(weight_40), + .i_B_40(Ct_1_40), + .o_C_40(o_mult_40), + .i_A_41(weight_41), + .i_B_41(Ct_1_41), + .o_C_41(o_mult_41), + .i_A_42(weight_42), + .i_B_42(Ct_1_42), + .o_C_42(o_mult_42), + .i_A_43(weight_43), + .i_B_43(Ct_1_43), + .o_C_43(o_mult_43), + .i_A_44(weight_44), + .i_B_44(Ct_1_44), + .o_C_44(o_mult_44), + .i_A_45(weight_45), + .i_B_45(Ct_1_45), + .o_C_45(o_mult_45), + .i_A_46(weight_46), + .i_B_46(Ct_1_46), + .o_C_46(o_mult_46), + .i_A_47(weight_47), + .i_B_47(Ct_1_47), + .o_C_47(o_mult_47), + .o_valid(mult_valid), + .o_ready(mult_ready) +); + +elementwise_add_core_18_18_48 elementwise_add_core_18_18_48_add_1 ( + .clk(clk), + .reset(reset), + .i_valid(i_valid), + .i_ready(add2_ready), + .i_A_0(stage1_result_0), + .i_B_0(bias_0), + .o_C_0(o_add1_0), + .i_A_1(stage1_result_1), + .i_B_1(bias_1), + .o_C_1(o_add1_1), + .i_A_2(stage1_result_2), + .i_B_2(bias_2), + .o_C_2(o_add1_2), + .i_A_3(stage1_result_3), + .i_B_3(bias_3), + .o_C_3(o_add1_3), + .i_A_4(stage1_result_4), + .i_B_4(bias_4), + .o_C_4(o_add1_4), + .i_A_5(stage1_result_5), + .i_B_5(bias_5), + .o_C_5(o_add1_5), + .i_A_6(stage1_result_6), + .i_B_6(bias_6), + .o_C_6(o_add1_6), + .i_A_7(stage1_result_7), + .i_B_7(bias_7), + .o_C_7(o_add1_7), + .i_A_8(stage1_result_8), + .i_B_8(bias_8), + .o_C_8(o_add1_8), + .i_A_9(stage1_result_9), + .i_B_9(bias_9), + .o_C_9(o_add1_9), + .i_A_10(stage1_result_10), + .i_B_10(bias_10), + .o_C_10(o_add1_10), + .i_A_11(stage1_result_11), + .i_B_11(bias_11), + .o_C_11(o_add1_11), + .i_A_12(stage1_result_12), + .i_B_12(bias_12), + .o_C_12(o_add1_12), + .i_A_13(stage1_result_13), + .i_B_13(bias_13), + .o_C_13(o_add1_13), + .i_A_14(stage1_result_14), + .i_B_14(bias_14), + .o_C_14(o_add1_14), + .i_A_15(stage1_result_15), + .i_B_15(bias_15), + .o_C_15(o_add1_15), + .i_A_16(stage1_result_16), + .i_B_16(bias_16), + .o_C_16(o_add1_16), + .i_A_17(stage1_result_17), + .i_B_17(bias_17), + .o_C_17(o_add1_17), + .i_A_18(stage1_result_18), + .i_B_18(bias_18), + .o_C_18(o_add1_18), + .i_A_19(stage1_result_19), + .i_B_19(bias_19), + .o_C_19(o_add1_19), + .i_A_20(stage1_result_20), + .i_B_20(bias_20), + .o_C_20(o_add1_20), + .i_A_21(stage1_result_21), + .i_B_21(bias_21), + .o_C_21(o_add1_21), + .i_A_22(stage1_result_22), + .i_B_22(bias_22), + .o_C_22(o_add1_22), + .i_A_23(stage1_result_23), + .i_B_23(bias_23), + .o_C_23(o_add1_23), + .i_A_24(stage1_result_24), + .i_B_24(bias_24), + .o_C_24(o_add1_24), + .i_A_25(stage1_result_25), + .i_B_25(bias_25), + .o_C_25(o_add1_25), + .i_A_26(stage1_result_26), + .i_B_26(bias_26), + .o_C_26(o_add1_26), + .i_A_27(stage1_result_27), + .i_B_27(bias_27), + .o_C_27(o_add1_27), + .i_A_28(stage1_result_28), + .i_B_28(bias_28), + .o_C_28(o_add1_28), + .i_A_29(stage1_result_29), + .i_B_29(bias_29), + .o_C_29(o_add1_29), + .i_A_30(stage1_result_30), + .i_B_30(bias_30), + .o_C_30(o_add1_30), + .i_A_31(stage1_result_31), + .i_B_31(bias_31), + .o_C_31(o_add1_31), + .i_A_32(stage1_result_32), + .i_B_32(bias_32), + .o_C_32(o_add1_32), + .i_A_33(stage1_result_33), + .i_B_33(bias_33), + .o_C_33(o_add1_33), + .i_A_34(stage1_result_34), + .i_B_34(bias_34), + .o_C_34(o_add1_34), + .i_A_35(stage1_result_35), + .i_B_35(bias_35), + .o_C_35(o_add1_35), + .i_A_36(stage1_result_36), + .i_B_36(bias_36), + .o_C_36(o_add1_36), + .i_A_37(stage1_result_37), + .i_B_37(bias_37), + .o_C_37(o_add1_37), + .i_A_38(stage1_result_38), + .i_B_38(bias_38), + .o_C_38(o_add1_38), + .i_A_39(stage1_result_39), + .i_B_39(bias_39), + .o_C_39(o_add1_39), + .i_A_40(stage1_result_40), + .i_B_40(bias_40), + .o_C_40(o_add1_40), + .i_A_41(stage1_result_41), + .i_B_41(bias_41), + .o_C_41(o_add1_41), + .i_A_42(stage1_result_42), + .i_B_42(bias_42), + .o_C_42(o_add1_42), + .i_A_43(stage1_result_43), + .i_B_43(bias_43), + .o_C_43(o_add1_43), + .i_A_44(stage1_result_44), + .i_B_44(bias_44), + .o_C_44(o_add1_44), + .i_A_45(stage1_result_45), + .i_B_45(bias_45), + .o_C_45(o_add1_45), + .i_A_46(stage1_result_46), + .i_B_46(bias_46), + .o_C_46(o_add1_46), + .i_A_47(stage1_result_47), + .i_B_47(bias_47), + .o_C_47(o_add1_47), + .o_valid(add1_valid), + .o_ready(add1_ready) +); + +shift_register_group_18_48_10 shift_register_group_18_48_10_Ct ( + .clk(clk), + .enable(enable), + .in_0(o_add1_0), + .out_0(add1_hold_0), + .in_1(o_add1_1), + .out_1(add1_hold_1), + .in_2(o_add1_2), + .out_2(add1_hold_2), + .in_3(o_add1_3), + .out_3(add1_hold_3), + .in_4(o_add1_4), + .out_4(add1_hold_4), + .in_5(o_add1_5), + .out_5(add1_hold_5), + .in_6(o_add1_6), + .out_6(add1_hold_6), + .in_7(o_add1_7), + .out_7(add1_hold_7), + .in_8(o_add1_8), + .out_8(add1_hold_8), + .in_9(o_add1_9), + .out_9(add1_hold_9), + .in_10(o_add1_10), + .out_10(add1_hold_10), + .in_11(o_add1_11), + .out_11(add1_hold_11), + .in_12(o_add1_12), + .out_12(add1_hold_12), + .in_13(o_add1_13), + .out_13(add1_hold_13), + .in_14(o_add1_14), + .out_14(add1_hold_14), + .in_15(o_add1_15), + .out_15(add1_hold_15), + .in_16(o_add1_16), + .out_16(add1_hold_16), + .in_17(o_add1_17), + .out_17(add1_hold_17), + .in_18(o_add1_18), + .out_18(add1_hold_18), + .in_19(o_add1_19), + .out_19(add1_hold_19), + .in_20(o_add1_20), + .out_20(add1_hold_20), + .in_21(o_add1_21), + .out_21(add1_hold_21), + .in_22(o_add1_22), + .out_22(add1_hold_22), + .in_23(o_add1_23), + .out_23(add1_hold_23), + .in_24(o_add1_24), + .out_24(add1_hold_24), + .in_25(o_add1_25), + .out_25(add1_hold_25), + .in_26(o_add1_26), + .out_26(add1_hold_26), + .in_27(o_add1_27), + .out_27(add1_hold_27), + .in_28(o_add1_28), + .out_28(add1_hold_28), + .in_29(o_add1_29), + .out_29(add1_hold_29), + .in_30(o_add1_30), + .out_30(add1_hold_30), + .in_31(o_add1_31), + .out_31(add1_hold_31), + .in_32(o_add1_32), + .out_32(add1_hold_32), + .in_33(o_add1_33), + .out_33(add1_hold_33), + .in_34(o_add1_34), + .out_34(add1_hold_34), + .in_35(o_add1_35), + .out_35(add1_hold_35), + .in_36(o_add1_36), + .out_36(add1_hold_36), + .in_37(o_add1_37), + .out_37(add1_hold_37), + .in_38(o_add1_38), + .out_38(add1_hold_38), + .in_39(o_add1_39), + .out_39(add1_hold_39), + .in_40(o_add1_40), + .out_40(add1_hold_40), + .in_41(o_add1_41), + .out_41(add1_hold_41), + .in_42(o_add1_42), + .out_42(add1_hold_42), + .in_43(o_add1_43), + .out_43(add1_hold_43), + .in_44(o_add1_44), + .out_44(add1_hold_44), + .in_45(o_add1_45), + .out_45(add1_hold_45), + .in_46(o_add1_46), + .out_46(add1_hold_46), + .in_47(o_add1_47), + .out_47(add1_hold_47), + .reset(reset) +); + +elementwise_add_core_18_18_48 elementwise_add_core_18_18_48_add_2 ( + .clk(clk), + .reset(reset), + .i_valid(mult_valid), + .i_ready(sigmoid_ready_0), + .i_A_0(add1_hold_0), + .i_B_0(o_mult_0), + .o_C_0(o_add2_0), + .i_A_1(add1_hold_1), + .i_B_1(o_mult_1), + .o_C_1(o_add2_1), + .i_A_2(add1_hold_2), + .i_B_2(o_mult_2), + .o_C_2(o_add2_2), + .i_A_3(add1_hold_3), + .i_B_3(o_mult_3), + .o_C_3(o_add2_3), + .i_A_4(add1_hold_4), + .i_B_4(o_mult_4), + .o_C_4(o_add2_4), + .i_A_5(add1_hold_5), + .i_B_5(o_mult_5), + .o_C_5(o_add2_5), + .i_A_6(add1_hold_6), + .i_B_6(o_mult_6), + .o_C_6(o_add2_6), + .i_A_7(add1_hold_7), + .i_B_7(o_mult_7), + .o_C_7(o_add2_7), + .i_A_8(add1_hold_8), + .i_B_8(o_mult_8), + .o_C_8(o_add2_8), + .i_A_9(add1_hold_9), + .i_B_9(o_mult_9), + .o_C_9(o_add2_9), + .i_A_10(add1_hold_10), + .i_B_10(o_mult_10), + .o_C_10(o_add2_10), + .i_A_11(add1_hold_11), + .i_B_11(o_mult_11), + .o_C_11(o_add2_11), + .i_A_12(add1_hold_12), + .i_B_12(o_mult_12), + .o_C_12(o_add2_12), + .i_A_13(add1_hold_13), + .i_B_13(o_mult_13), + .o_C_13(o_add2_13), + .i_A_14(add1_hold_14), + .i_B_14(o_mult_14), + .o_C_14(o_add2_14), + .i_A_15(add1_hold_15), + .i_B_15(o_mult_15), + .o_C_15(o_add2_15), + .i_A_16(add1_hold_16), + .i_B_16(o_mult_16), + .o_C_16(o_add2_16), + .i_A_17(add1_hold_17), + .i_B_17(o_mult_17), + .o_C_17(o_add2_17), + .i_A_18(add1_hold_18), + .i_B_18(o_mult_18), + .o_C_18(o_add2_18), + .i_A_19(add1_hold_19), + .i_B_19(o_mult_19), + .o_C_19(o_add2_19), + .i_A_20(add1_hold_20), + .i_B_20(o_mult_20), + .o_C_20(o_add2_20), + .i_A_21(add1_hold_21), + .i_B_21(o_mult_21), + .o_C_21(o_add2_21), + .i_A_22(add1_hold_22), + .i_B_22(o_mult_22), + .o_C_22(o_add2_22), + .i_A_23(add1_hold_23), + .i_B_23(o_mult_23), + .o_C_23(o_add2_23), + .i_A_24(add1_hold_24), + .i_B_24(o_mult_24), + .o_C_24(o_add2_24), + .i_A_25(add1_hold_25), + .i_B_25(o_mult_25), + .o_C_25(o_add2_25), + .i_A_26(add1_hold_26), + .i_B_26(o_mult_26), + .o_C_26(o_add2_26), + .i_A_27(add1_hold_27), + .i_B_27(o_mult_27), + .o_C_27(o_add2_27), + .i_A_28(add1_hold_28), + .i_B_28(o_mult_28), + .o_C_28(o_add2_28), + .i_A_29(add1_hold_29), + .i_B_29(o_mult_29), + .o_C_29(o_add2_29), + .i_A_30(add1_hold_30), + .i_B_30(o_mult_30), + .o_C_30(o_add2_30), + .i_A_31(add1_hold_31), + .i_B_31(o_mult_31), + .o_C_31(o_add2_31), + .i_A_32(add1_hold_32), + .i_B_32(o_mult_32), + .o_C_32(o_add2_32), + .i_A_33(add1_hold_33), + .i_B_33(o_mult_33), + .o_C_33(o_add2_33), + .i_A_34(add1_hold_34), + .i_B_34(o_mult_34), + .o_C_34(o_add2_34), + .i_A_35(add1_hold_35), + .i_B_35(o_mult_35), + .o_C_35(o_add2_35), + .i_A_36(add1_hold_36), + .i_B_36(o_mult_36), + .o_C_36(o_add2_36), + .i_A_37(add1_hold_37), + .i_B_37(o_mult_37), + .o_C_37(o_add2_37), + .i_A_38(add1_hold_38), + .i_B_38(o_mult_38), + .o_C_38(o_add2_38), + .i_A_39(add1_hold_39), + .i_B_39(o_mult_39), + .o_C_39(o_add2_39), + .i_A_40(add1_hold_40), + .i_B_40(o_mult_40), + .o_C_40(o_add2_40), + .i_A_41(add1_hold_41), + .i_B_41(o_mult_41), + .o_C_41(o_add2_41), + .i_A_42(add1_hold_42), + .i_B_42(o_mult_42), + .o_C_42(o_add2_42), + .i_A_43(add1_hold_43), + .i_B_43(o_mult_43), + .o_C_43(o_add2_43), + .i_A_44(add1_hold_44), + .i_B_44(o_mult_44), + .o_C_44(o_add2_44), + .i_A_45(add1_hold_45), + .i_B_45(o_mult_45), + .o_C_45(o_add2_45), + .i_A_46(add1_hold_46), + .i_B_46(o_mult_46), + .o_C_46(o_add2_46), + .i_A_47(add1_hold_47), + .i_B_47(o_mult_47), + .o_C_47(o_add2_47), + .o_valid(add2_valid), + .o_ready(add2_ready) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_0 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_0), + .o_valid(sigmoid_valid_0), + .i_x(o_add2_0), + .o_y(o_sigmoid_0) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_1 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_1), + .o_valid(sigmoid_valid_1), + .i_x(o_add2_1), + .o_y(o_sigmoid_1) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_2 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_2), + .o_valid(sigmoid_valid_2), + .i_x(o_add2_2), + .o_y(o_sigmoid_2) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_3 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_3), + .o_valid(sigmoid_valid_3), + .i_x(o_add2_3), + .o_y(o_sigmoid_3) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_4 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_4), + .o_valid(sigmoid_valid_4), + .i_x(o_add2_4), + .o_y(o_sigmoid_4) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_5 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_5), + .o_valid(sigmoid_valid_5), + .i_x(o_add2_5), + .o_y(o_sigmoid_5) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_6 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_6), + .o_valid(sigmoid_valid_6), + .i_x(o_add2_6), + .o_y(o_sigmoid_6) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_7 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_7), + .o_valid(sigmoid_valid_7), + .i_x(o_add2_7), + .o_y(o_sigmoid_7) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_8 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_8), + .o_valid(sigmoid_valid_8), + .i_x(o_add2_8), + .o_y(o_sigmoid_8) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_9 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_9), + .o_valid(sigmoid_valid_9), + .i_x(o_add2_9), + .o_y(o_sigmoid_9) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_10 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_10), + .o_valid(sigmoid_valid_10), + .i_x(o_add2_10), + .o_y(o_sigmoid_10) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_11 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_11), + .o_valid(sigmoid_valid_11), + .i_x(o_add2_11), + .o_y(o_sigmoid_11) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_12 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_12), + .o_valid(sigmoid_valid_12), + .i_x(o_add2_12), + .o_y(o_sigmoid_12) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_13 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_13), + .o_valid(sigmoid_valid_13), + .i_x(o_add2_13), + .o_y(o_sigmoid_13) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_14 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_14), + .o_valid(sigmoid_valid_14), + .i_x(o_add2_14), + .o_y(o_sigmoid_14) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_15 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_15), + .o_valid(sigmoid_valid_15), + .i_x(o_add2_15), + .o_y(o_sigmoid_15) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_16 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_16), + .o_valid(sigmoid_valid_16), + .i_x(o_add2_16), + .o_y(o_sigmoid_16) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_17 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_17), + .o_valid(sigmoid_valid_17), + .i_x(o_add2_17), + .o_y(o_sigmoid_17) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_18 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_18), + .o_valid(sigmoid_valid_18), + .i_x(o_add2_18), + .o_y(o_sigmoid_18) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_19 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_19), + .o_valid(sigmoid_valid_19), + .i_x(o_add2_19), + .o_y(o_sigmoid_19) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_20 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_20), + .o_valid(sigmoid_valid_20), + .i_x(o_add2_20), + .o_y(o_sigmoid_20) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_21 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_21), + .o_valid(sigmoid_valid_21), + .i_x(o_add2_21), + .o_y(o_sigmoid_21) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_22 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_22), + .o_valid(sigmoid_valid_22), + .i_x(o_add2_22), + .o_y(o_sigmoid_22) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_23 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_23), + .o_valid(sigmoid_valid_23), + .i_x(o_add2_23), + .o_y(o_sigmoid_23) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_24 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_24), + .o_valid(sigmoid_valid_24), + .i_x(o_add2_24), + .o_y(o_sigmoid_24) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_25 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_25), + .o_valid(sigmoid_valid_25), + .i_x(o_add2_25), + .o_y(o_sigmoid_25) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_26 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_26), + .o_valid(sigmoid_valid_26), + .i_x(o_add2_26), + .o_y(o_sigmoid_26) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_27 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_27), + .o_valid(sigmoid_valid_27), + .i_x(o_add2_27), + .o_y(o_sigmoid_27) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_28 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_28), + .o_valid(sigmoid_valid_28), + .i_x(o_add2_28), + .o_y(o_sigmoid_28) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_29 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_29), + .o_valid(sigmoid_valid_29), + .i_x(o_add2_29), + .o_y(o_sigmoid_29) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_30 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_30), + .o_valid(sigmoid_valid_30), + .i_x(o_add2_30), + .o_y(o_sigmoid_30) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_31 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_31), + .o_valid(sigmoid_valid_31), + .i_x(o_add2_31), + .o_y(o_sigmoid_31) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_32 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_32), + .o_valid(sigmoid_valid_32), + .i_x(o_add2_32), + .o_y(o_sigmoid_32) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_33 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_33), + .o_valid(sigmoid_valid_33), + .i_x(o_add2_33), + .o_y(o_sigmoid_33) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_34 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_34), + .o_valid(sigmoid_valid_34), + .i_x(o_add2_34), + .o_y(o_sigmoid_34) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_35 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_35), + .o_valid(sigmoid_valid_35), + .i_x(o_add2_35), + .o_y(o_sigmoid_35) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_36 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_36), + .o_valid(sigmoid_valid_36), + .i_x(o_add2_36), + .o_y(o_sigmoid_36) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_37 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_37), + .o_valid(sigmoid_valid_37), + .i_x(o_add2_37), + .o_y(o_sigmoid_37) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_38 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_38), + .o_valid(sigmoid_valid_38), + .i_x(o_add2_38), + .o_y(o_sigmoid_38) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_39 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_39), + .o_valid(sigmoid_valid_39), + .i_x(o_add2_39), + .o_y(o_sigmoid_39) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_40 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_40), + .o_valid(sigmoid_valid_40), + .i_x(o_add2_40), + .o_y(o_sigmoid_40) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_41 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_41), + .o_valid(sigmoid_valid_41), + .i_x(o_add2_41), + .o_y(o_sigmoid_41) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_42 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_42), + .o_valid(sigmoid_valid_42), + .i_x(o_add2_42), + .o_y(o_sigmoid_42) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_43 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_43), + .o_valid(sigmoid_valid_43), + .i_x(o_add2_43), + .o_y(o_sigmoid_43) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_44 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_44), + .o_valid(sigmoid_valid_44), + .i_x(o_add2_44), + .o_y(o_sigmoid_44) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_45 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_45), + .o_valid(sigmoid_valid_45), + .i_x(o_add2_45), + .o_y(o_sigmoid_45) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_46 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_46), + .o_valid(sigmoid_valid_46), + .i_x(o_add2_46), + .o_y(o_sigmoid_46) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_47 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_47), + .o_valid(sigmoid_valid_47), + .i_x(o_add2_47), + .o_y(o_sigmoid_47) +); + +assign o_ready = mult_ready; +assign o_valid = sigmoid_valid_0 & i_ready; +assign gate_output_0 = o_sigmoid_0; +assign gate_output_1 = o_sigmoid_1; +assign gate_output_2 = o_sigmoid_2; +assign gate_output_3 = o_sigmoid_3; +assign gate_output_4 = o_sigmoid_4; +assign gate_output_5 = o_sigmoid_5; +assign gate_output_6 = o_sigmoid_6; +assign gate_output_7 = o_sigmoid_7; +assign gate_output_8 = o_sigmoid_8; +assign gate_output_9 = o_sigmoid_9; +assign gate_output_10 = o_sigmoid_10; +assign gate_output_11 = o_sigmoid_11; +assign gate_output_12 = o_sigmoid_12; +assign gate_output_13 = o_sigmoid_13; +assign gate_output_14 = o_sigmoid_14; +assign gate_output_15 = o_sigmoid_15; +assign gate_output_16 = o_sigmoid_16; +assign gate_output_17 = o_sigmoid_17; +assign gate_output_18 = o_sigmoid_18; +assign gate_output_19 = o_sigmoid_19; +assign gate_output_20 = o_sigmoid_20; +assign gate_output_21 = o_sigmoid_21; +assign gate_output_22 = o_sigmoid_22; +assign gate_output_23 = o_sigmoid_23; +assign gate_output_24 = o_sigmoid_24; +assign gate_output_25 = o_sigmoid_25; +assign gate_output_26 = o_sigmoid_26; +assign gate_output_27 = o_sigmoid_27; +assign gate_output_28 = o_sigmoid_28; +assign gate_output_29 = o_sigmoid_29; +assign gate_output_30 = o_sigmoid_30; +assign gate_output_31 = o_sigmoid_31; +assign gate_output_32 = o_sigmoid_32; +assign gate_output_33 = o_sigmoid_33; +assign gate_output_34 = o_sigmoid_34; +assign gate_output_35 = o_sigmoid_35; +assign gate_output_36 = o_sigmoid_36; +assign gate_output_37 = o_sigmoid_37; +assign gate_output_38 = o_sigmoid_38; +assign gate_output_39 = o_sigmoid_39; +assign gate_output_40 = o_sigmoid_40; +assign gate_output_41 = o_sigmoid_41; +assign gate_output_42 = o_sigmoid_42; +assign gate_output_43 = o_sigmoid_43; +assign gate_output_44 = o_sigmoid_44; +assign gate_output_45 = o_sigmoid_45; +assign gate_output_46 = o_sigmoid_46; +assign gate_output_47 = o_sigmoid_47; + +endmodule + +module shift_register_group_18_48_10 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input [17:0] in_16, + output [17:0] out_16, + input [17:0] in_17, + output [17:0] out_17, + input [17:0] in_18, + output [17:0] out_18, + input [17:0] in_19, + output [17:0] out_19, + input [17:0] in_20, + output [17:0] out_20, + input [17:0] in_21, + output [17:0] out_21, + input [17:0] in_22, + output [17:0] out_22, + input [17:0] in_23, + output [17:0] out_23, + input [17:0] in_24, + output [17:0] out_24, + input [17:0] in_25, + output [17:0] out_25, + input [17:0] in_26, + output [17:0] out_26, + input [17:0] in_27, + output [17:0] out_27, + input [17:0] in_28, + output [17:0] out_28, + input [17:0] in_29, + output [17:0] out_29, + input [17:0] in_30, + output [17:0] out_30, + input [17:0] in_31, + output [17:0] out_31, + input [17:0] in_32, + output [17:0] out_32, + input [17:0] in_33, + output [17:0] out_33, + input [17:0] in_34, + output [17:0] out_34, + input [17:0] in_35, + output [17:0] out_35, + input [17:0] in_36, + output [17:0] out_36, + input [17:0] in_37, + output [17:0] out_37, + input [17:0] in_38, + output [17:0] out_38, + input [17:0] in_39, + output [17:0] out_39, + input [17:0] in_40, + output [17:0] out_40, + input [17:0] in_41, + output [17:0] out_41, + input [17:0] in_42, + output [17:0] out_42, + input [17:0] in_43, + output [17:0] out_43, + input [17:0] in_44, + output [17:0] out_44, + input [17:0] in_45, + output [17:0] out_45, + input [17:0] in_46, + output [17:0] out_46, + input [17:0] in_47, + output [17:0] out_47, + input reset +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_16 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_16), + .out(out_16) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_17 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_17), + .out(out_17) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_18 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_18), + .out(out_18) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_19 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_19), + .out(out_19) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_20 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_20), + .out(out_20) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_21 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_21), + .out(out_21) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_22 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_22), + .out(out_22) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_23 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_23), + .out(out_23) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_24 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_24), + .out(out_24) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_25 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_25), + .out(out_25) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_26 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_26), + .out(out_26) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_27 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_27), + .out(out_27) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_28 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_28), + .out(out_28) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_29 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_29), + .out(out_29) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_30 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_30), + .out(out_30) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_31 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_31), + .out(out_31) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_32 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_32), + .out(out_32) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_33 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_33), + .out(out_33) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_34 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_34), + .out(out_34) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_35 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_35), + .out(out_35) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_36 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_36), + .out(out_36) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_37 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_37), + .out(out_37) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_38 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_38), + .out(out_38) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_39 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_39), + .out(out_39) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_40 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_40), + .out(out_40) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_41 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_41), + .out(out_41) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_42 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_42), + .out(out_42) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_43 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_43), + .out(out_43) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_44 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_44), + .out(out_44) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_45 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_45), + .out(out_45) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_46 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_46), + .out(out_46) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_47 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_47), + .out(out_47) +); + +endmodule + +module shift_register_unit_18_18 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +reg [17:0] shift_registers_1; +reg [17:0] shift_registers_2; +reg [17:0] shift_registers_3; +reg [17:0] shift_registers_4; +reg [17:0] shift_registers_5; +reg [17:0] shift_registers_6; +reg [17:0] shift_registers_7; +reg [17:0] shift_registers_8; +reg [17:0] shift_registers_9; +reg [17:0] shift_registers_10; +reg [17:0] shift_registers_11; +reg [17:0] shift_registers_12; +reg [17:0] shift_registers_13; +reg [17:0] shift_registers_14; +reg [17:0] shift_registers_15; +reg [17:0] shift_registers_16; +reg [17:0] shift_registers_17; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + shift_registers_1 <= 18'd0; + shift_registers_2 <= 18'd0; + shift_registers_3 <= 18'd0; + shift_registers_4 <= 18'd0; + shift_registers_5 <= 18'd0; + shift_registers_6 <= 18'd0; + shift_registers_7 <= 18'd0; + shift_registers_8 <= 18'd0; + shift_registers_9 <= 18'd0; + shift_registers_10 <= 18'd0; + shift_registers_11 <= 18'd0; + shift_registers_12 <= 18'd0; + shift_registers_13 <= 18'd0; + shift_registers_14 <= 18'd0; + shift_registers_15 <= 18'd0; + shift_registers_16 <= 18'd0; + shift_registers_17 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + shift_registers_3 <= shift_registers_2; + shift_registers_4 <= shift_registers_3; + shift_registers_5 <= shift_registers_4; + shift_registers_6 <= shift_registers_5; + shift_registers_7 <= shift_registers_6; + shift_registers_8 <= shift_registers_7; + shift_registers_9 <= shift_registers_8; + shift_registers_10 <= shift_registers_9; + shift_registers_11 <= shift_registers_10; + shift_registers_12 <= shift_registers_11; + shift_registers_13 <= shift_registers_12; + shift_registers_14 <= shift_registers_13; + shift_registers_15 <= shift_registers_14; + shift_registers_16 <= shift_registers_15; + shift_registers_17 <= shift_registers_16; + end +end + +assign out = shift_registers_17; + +endmodule + +module sigmoid_core_18_18_10_32_1 ( + input clk, + input reset, + input i_valid, + input i_ready, + output o_ready, + output o_valid, + input [17:0] i_x, + output [17:0] o_y +); + +reg [12:0] k_list_0; +reg [12:0] b_list_0; +reg [12:0] k_list_1; +reg [12:0] b_list_1; +reg [12:0] k_list_2; +reg [12:0] b_list_2; +reg [12:0] k_list_3; +reg [12:0] b_list_3; +reg [12:0] k_list_4; +reg [12:0] b_list_4; +reg [12:0] k_list_5; +reg [12:0] b_list_5; +reg [12:0] k_list_6; +reg [12:0] b_list_6; +reg [12:0] k_list_7; +reg [12:0] b_list_7; +reg [12:0] k_list_8; +reg [12:0] b_list_8; +reg [12:0] k_list_9; +reg [12:0] b_list_9; +reg [12:0] k_list_10; +reg [12:0] b_list_10; +reg [12:0] k_list_11; +reg [12:0] b_list_11; +reg [12:0] k_list_12; +reg [12:0] b_list_12; +reg [12:0] k_list_13; +reg [12:0] b_list_13; +reg [12:0] k_list_14; +reg [12:0] b_list_14; +reg [12:0] k_list_15; +reg [12:0] b_list_15; +reg [12:0] k_list_16; +reg [12:0] b_list_16; +reg [12:0] k_list_17; +reg [12:0] b_list_17; +reg [12:0] k_list_18; +reg [12:0] b_list_18; +reg [12:0] k_list_19; +reg [12:0] b_list_19; +reg [12:0] k_list_20; +reg [12:0] b_list_20; +reg [12:0] k_list_21; +reg [12:0] b_list_21; +reg [12:0] k_list_22; +reg [12:0] b_list_22; +reg [12:0] k_list_23; +reg [12:0] b_list_23; +reg [12:0] k_list_24; +reg [12:0] b_list_24; +reg [12:0] k_list_25; +reg [12:0] b_list_25; +reg [12:0] k_list_26; +reg [12:0] b_list_26; +reg [12:0] k_list_27; +reg [12:0] b_list_27; +reg [12:0] k_list_28; +reg [12:0] b_list_28; +reg [12:0] k_list_29; +reg [12:0] b_list_29; +reg [12:0] k_list_30; +reg [12:0] b_list_30; +reg [12:0] k_list_31; +reg [12:0] b_list_31; + +always @ (posedge clk) begin + k_list_0 <= 13'b0000111111101; + k_list_1 <= 13'b0000111101110; + k_list_2 <= 13'b0000111010001; + k_list_3 <= 13'b0000110101001; + k_list_4 <= 13'b0000101111011; + k_list_5 <= 13'b0000101001010; + k_list_6 <= 13'b0000100011010; + k_list_7 <= 13'b0000011101100; + k_list_8 <= 13'b0000011000011; + k_list_9 <= 13'b0000010100000; + k_list_10 <= 13'b0000010000001; + k_list_11 <= 13'b0000001101000; + k_list_12 <= 13'b0000001010011; + k_list_13 <= 13'b0000001000010; + k_list_14 <= 13'b0000000110100; + k_list_15 <= 13'b0000000101001; + k_list_16 <= 13'b0000000100000; + k_list_17 <= 13'b0000000011001; + k_list_18 <= 13'b0000000010100; + k_list_19 <= 13'b0000000001111; + k_list_20 <= 13'b0000000001100; + k_list_21 <= 13'b0000000001001; + k_list_22 <= 13'b0000000000111; + k_list_23 <= 13'b0000000000110; + k_list_24 <= 13'b0000000000100; + k_list_25 <= 13'b0000000000011; + k_list_26 <= 13'b0000000000011; + k_list_27 <= 13'b0000000000010; + k_list_28 <= 13'b0000000000010; + k_list_29 <= 13'b0000000000001; + k_list_30 <= 13'b0000000000001; + k_list_31 <= 13'b0000000000001; + b_list_0 <= 13'b0010000000000; + b_list_1 <= 13'b0010000000100; + b_list_2 <= 13'b0010000010010; + b_list_3 <= 13'b0010000110000; + b_list_4 <= 13'b0010001011110; + b_list_5 <= 13'b0010010011011; + b_list_6 <= 13'b0010011100100; + b_list_7 <= 13'b0010100110011; + b_list_8 <= 13'b0010110000101; + b_list_9 <= 13'b0010111010101; + b_list_10 <= 13'b0011000100010; + b_list_11 <= 13'b0011001101000; + b_list_12 <= 13'b0011010100111; + b_list_13 <= 13'b0011011011110; + b_list_14 <= 13'b0011100001110; + b_list_15 <= 13'b0011100111000; + b_list_16 <= 13'b0011101011011; + b_list_17 <= 13'b0011101111000; + b_list_18 <= 13'b0011110010001; + b_list_19 <= 13'b0011110100101; + b_list_20 <= 13'b0011110110110; + b_list_21 <= 13'b0011111000100; + b_list_22 <= 13'b0011111001111; + b_list_23 <= 13'b0011111011001; + b_list_24 <= 13'b0011111100000; + b_list_25 <= 13'b0011111100110; + b_list_26 <= 13'b0011111101011; + b_list_27 <= 13'b0011111101111; + b_list_28 <= 13'b0011111110011; + b_list_29 <= 13'b0011111110101; + b_list_30 <= 13'b0011111110111; + b_list_31 <= 13'b0011111111001; +end +reg [17:0] x; +reg [17:0] y; +reg valid_x, valid_y, enable; +wire [4:0] sel_k_b; + +wire abs_valid, round_valid, mult_valid, compute_valid; +reg [12:0] mac_ay, mac_az; +reg is_x_negative; +wire is_x_negative_hold; +wire [17:0] abs_x; +wire [17:0] x_partial; +reg [31:0] y_compute; +wire [31:0] x_k_plus_b; +wire [31:0] y_rounded; + +assign x_partial = (abs_x >> 8); +assign sel_k_b = x_partial [4:0]; + +reg [12:0] selected_k, selected_b; +always @ (*) begin + if (sel_k_b == 0) begin + selected_k <= k_list_0; + selected_b <= b_list_0; + end else if (sel_k_b == 1) begin + selected_k <= k_list_1; + selected_b <= b_list_1; + end else if (sel_k_b == 2) begin + selected_k <= k_list_2; + selected_b <= b_list_2; + end else if (sel_k_b == 3) begin + selected_k <= k_list_3; + selected_b <= b_list_3; + end else if (sel_k_b == 4) begin + selected_k <= k_list_4; + selected_b <= b_list_4; + end else if (sel_k_b == 5) begin + selected_k <= k_list_5; + selected_b <= b_list_5; + end else if (sel_k_b == 6) begin + selected_k <= k_list_6; + selected_b <= b_list_6; + end else if (sel_k_b == 7) begin + selected_k <= k_list_7; + selected_b <= b_list_7; + end else if (sel_k_b == 8) begin + selected_k <= k_list_8; + selected_b <= b_list_8; + end else if (sel_k_b == 9) begin + selected_k <= k_list_9; + selected_b <= b_list_9; + end else if (sel_k_b == 10) begin + selected_k <= k_list_10; + selected_b <= b_list_10; + end else if (sel_k_b == 11) begin + selected_k <= k_list_11; + selected_b <= b_list_11; + end else if (sel_k_b == 12) begin + selected_k <= k_list_12; + selected_b <= b_list_12; + end else if (sel_k_b == 13) begin + selected_k <= k_list_13; + selected_b <= b_list_13; + end else if (sel_k_b == 14) begin + selected_k <= k_list_14; + selected_b <= b_list_14; + end else if (sel_k_b == 15) begin + selected_k <= k_list_15; + selected_b <= b_list_15; + end else if (sel_k_b == 16) begin + selected_k <= k_list_16; + selected_b <= b_list_16; + end else if (sel_k_b == 17) begin + selected_k <= k_list_17; + selected_b <= b_list_17; + end else if (sel_k_b == 18) begin + selected_k <= k_list_18; + selected_b <= b_list_18; + end else if (sel_k_b == 19) begin + selected_k <= k_list_19; + selected_b <= b_list_19; + end else if (sel_k_b == 20) begin + selected_k <= k_list_20; + selected_b <= b_list_20; + end else if (sel_k_b == 21) begin + selected_k <= k_list_21; + selected_b <= b_list_21; + end else if (sel_k_b == 22) begin + selected_k <= k_list_22; + selected_b <= b_list_22; + end else if (sel_k_b == 23) begin + selected_k <= k_list_23; + selected_b <= b_list_23; + end else if (sel_k_b == 24) begin + selected_k <= k_list_24; + selected_b <= b_list_24; + end else if (sel_k_b == 25) begin + selected_k <= k_list_25; + selected_b <= b_list_25; + end else if (sel_k_b == 26) begin + selected_k <= k_list_26; + selected_b <= b_list_26; + end else if (sel_k_b == 27) begin + selected_k <= k_list_27; + selected_b <= b_list_27; + end else if (sel_k_b == 28) begin + selected_k <= k_list_28; + selected_b <= b_list_28; + end else if (sel_k_b == 29) begin + selected_k <= k_list_29; + selected_b <= b_list_29; + end else if (sel_k_b == 30) begin + selected_k <= k_list_30; + selected_b <= b_list_30; + end else begin + selected_k <= k_list_31; + selected_b <= b_list_31; + end +end +always @ (*) begin + if (abs_x >= 8192) begin + mac_ay <= 0; + mac_az <= 12'd2048; + end else begin + mac_ay <= selected_k; + mac_az <= (selected_b << 10); + end +end +dsp_signed_mac_18_13_23_32 dsp_signed_mac_18_13_23_32_inst_ctjfayzihs ( + .clk(clk), + .reset(reset), + .ena(enable), + .ax(abs_x), + .ay(mac_ay), + .az(mac_az), + .i_valid(abs_valid), + .o_valid(compute_valid), + .resulta(x_k_plus_b) +); + +shift_register_unit_1_3 shift_register_unit_1_3_inst_wxgredhrnz ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(is_x_negative), + .out(is_x_negative_hold) +); + +abs_unit_18 abs_unit_18_inst_inufptfdlj ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(valid_x), + .in(x), + .o_valid(abs_valid), + .out(abs_x) +); + +fp_rounding_unit_1_32_11 fp_rounding_unit_1_32_11_inst_snhhioqleu ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(compute_valid), + .in(y_compute), + .o_valid(round_valid), + .out(y_rounded) +); + +always @ (*) begin + if (is_x_negative_hold) + y_compute = 2048 - x_k_plus_b; + else + y_compute = x_k_plus_b; + enable = i_ready; +end +always @ (posedge clk) begin + if (reset) begin + valid_x <= 1'b0; + valid_y <= 1'b0; + x <= 0; + y <= 0; + end else if (enable) begin + valid_x <= i_valid; + valid_y <= round_valid; + x <= i_x; + if (x[17] == 1'b1) + is_x_negative <= 1'b1; + else + is_x_negative <= 1'b0; + y <= y_rounded[17:0]; + end +end + +assign o_y = y; +assign o_ready = i_ready; +assign o_valid = valid_y & i_ready; + +endmodule + +module dsp_signed_mac_18_13_23_32 ( + input clk, + input reset, + input ena, + input i_valid, + input [17:0] ax, + input [12:0] ay, + input [12:0] az, + output o_valid, + output [31:0] resulta +); + +reg [17:0] reg_ax; +reg [12:0] reg_ay; +reg [12:0] reg_az; +reg [31:0] reg_res; +reg valid_r, valid_rr; +always @ (posedge clk) begin + if (reset) begin + reg_ax <= 0; + reg_ay <= 0; + reg_az <= 0; + reg_res <= 0; + valid_r <= 0; + valid_rr <= 0; + end else begin + reg_ax <= ax; + reg_ay <= ay; + reg_az <= az; + reg_res <= (reg_ax * reg_ay) + reg_az; + valid_r <= ena; + valid_rr <= valid_r; + end +end + +assign resulta = reg_res; +assign o_valid = valid_rr; +endmodule + +module abs_unit_18 ( + input clk, + input reset, + input enable, + input i_valid, + input [17:0] in, + output o_valid, + output [17:0] out +); + +reg [17:0] abs_result; + +always @ (*) begin + if (in[17] == 1'b1) + abs_result = -in; + else + abs_result = in; +end + +reg valid_reg; +reg [17:0] out_reg; +always @ (posedge clk) begin + if (reset) begin + valid_reg <= 1'b0; + out_reg <= 0; + end else if (enable) begin + valid_reg <= i_valid; + out_reg <= abs_result; + end +end +assign out = out_reg; +assign o_valid = valid_reg; +endmodule + +module fp_rounding_unit_1_32_11 ( + input clk, + input reset, + input enable, + input i_valid, + input [31:0] in, + output [31:0] out, + output o_valid +); + +reg [31:0] rounded_result; +reg [31:0] floor; +reg [31:0] ceil; +reg is_ceil; +reg floor_ceil_valid; + +always @ (*) begin + if (is_ceil) begin + rounded_result = ceil; + end else begin + rounded_result = floor; + end +end + +reg valid_reg; +reg [31:0] out_reg; +always @ (posedge clk) begin + if (reset) begin + is_ceil <= 1'b0; + floor_ceil_valid <= 1'b0; + valid_reg <= 1'b0; + floor <= 0; + ceil <= 0; + out_reg <= 0; + end else if (enable) begin + is_ceil <= in[10]; + floor <= in >>> 11; + ceil <= (in >>> 11) + 1; + floor_ceil_valid <= i_valid; + out_reg <= rounded_result; + valid_reg <= floor_ceil_valid; + end +end + +assign o_valid = valid_reg; + +assign out = out_reg; + +endmodule + +module output_activation_18_10_48_1 ( + input clk, + input reset, + input i_ready, + input i_valid, + input [17:0] stage1_result_0, + input [17:0] bias_0, + output [17:0] output_value_0, + input [17:0] stage1_result_1, + input [17:0] bias_1, + output [17:0] output_value_1, + input [17:0] stage1_result_2, + input [17:0] bias_2, + output [17:0] output_value_2, + input [17:0] stage1_result_3, + input [17:0] bias_3, + output [17:0] output_value_3, + input [17:0] stage1_result_4, + input [17:0] bias_4, + output [17:0] output_value_4, + input [17:0] stage1_result_5, + input [17:0] bias_5, + output [17:0] output_value_5, + input [17:0] stage1_result_6, + input [17:0] bias_6, + output [17:0] output_value_6, + input [17:0] stage1_result_7, + input [17:0] bias_7, + output [17:0] output_value_7, + input [17:0] stage1_result_8, + input [17:0] bias_8, + output [17:0] output_value_8, + input [17:0] stage1_result_9, + input [17:0] bias_9, + output [17:0] output_value_9, + input [17:0] stage1_result_10, + input [17:0] bias_10, + output [17:0] output_value_10, + input [17:0] stage1_result_11, + input [17:0] bias_11, + output [17:0] output_value_11, + input [17:0] stage1_result_12, + input [17:0] bias_12, + output [17:0] output_value_12, + input [17:0] stage1_result_13, + input [17:0] bias_13, + output [17:0] output_value_13, + input [17:0] stage1_result_14, + input [17:0] bias_14, + output [17:0] output_value_14, + input [17:0] stage1_result_15, + input [17:0] bias_15, + output [17:0] output_value_15, + input [17:0] stage1_result_16, + input [17:0] bias_16, + output [17:0] output_value_16, + input [17:0] stage1_result_17, + input [17:0] bias_17, + output [17:0] output_value_17, + input [17:0] stage1_result_18, + input [17:0] bias_18, + output [17:0] output_value_18, + input [17:0] stage1_result_19, + input [17:0] bias_19, + output [17:0] output_value_19, + input [17:0] stage1_result_20, + input [17:0] bias_20, + output [17:0] output_value_20, + input [17:0] stage1_result_21, + input [17:0] bias_21, + output [17:0] output_value_21, + input [17:0] stage1_result_22, + input [17:0] bias_22, + output [17:0] output_value_22, + input [17:0] stage1_result_23, + input [17:0] bias_23, + output [17:0] output_value_23, + input [17:0] stage1_result_24, + input [17:0] bias_24, + output [17:0] output_value_24, + input [17:0] stage1_result_25, + input [17:0] bias_25, + output [17:0] output_value_25, + input [17:0] stage1_result_26, + input [17:0] bias_26, + output [17:0] output_value_26, + input [17:0] stage1_result_27, + input [17:0] bias_27, + output [17:0] output_value_27, + input [17:0] stage1_result_28, + input [17:0] bias_28, + output [17:0] output_value_28, + input [17:0] stage1_result_29, + input [17:0] bias_29, + output [17:0] output_value_29, + input [17:0] stage1_result_30, + input [17:0] bias_30, + output [17:0] output_value_30, + input [17:0] stage1_result_31, + input [17:0] bias_31, + output [17:0] output_value_31, + input [17:0] stage1_result_32, + input [17:0] bias_32, + output [17:0] output_value_32, + input [17:0] stage1_result_33, + input [17:0] bias_33, + output [17:0] output_value_33, + input [17:0] stage1_result_34, + input [17:0] bias_34, + output [17:0] output_value_34, + input [17:0] stage1_result_35, + input [17:0] bias_35, + output [17:0] output_value_35, + input [17:0] stage1_result_36, + input [17:0] bias_36, + output [17:0] output_value_36, + input [17:0] stage1_result_37, + input [17:0] bias_37, + output [17:0] output_value_37, + input [17:0] stage1_result_38, + input [17:0] bias_38, + output [17:0] output_value_38, + input [17:0] stage1_result_39, + input [17:0] bias_39, + output [17:0] output_value_39, + input [17:0] stage1_result_40, + input [17:0] bias_40, + output [17:0] output_value_40, + input [17:0] stage1_result_41, + input [17:0] bias_41, + output [17:0] output_value_41, + input [17:0] stage1_result_42, + input [17:0] bias_42, + output [17:0] output_value_42, + input [17:0] stage1_result_43, + input [17:0] bias_43, + output [17:0] output_value_43, + input [17:0] stage1_result_44, + input [17:0] bias_44, + output [17:0] output_value_44, + input [17:0] stage1_result_45, + input [17:0] bias_45, + output [17:0] output_value_45, + input [17:0] stage1_result_46, + input [17:0] bias_46, + output [17:0] output_value_46, + input [17:0] stage1_result_47, + input [17:0] bias_47, + output [17:0] output_value_47, + output o_valid, + output o_ready +); + +wire adder1_valid, adder2_valid, adder1_ready, adder2_ready; +wire sigmoid_valid_0, sigmoid_ready_0; +wire [17:0] o_add2_0; +wire [17:0] o_sigmoid_0; +wire sigmoid_valid_1, sigmoid_ready_1; +wire [17:0] o_add2_1; +wire [17:0] o_sigmoid_1; +wire sigmoid_valid_2, sigmoid_ready_2; +wire [17:0] o_add2_2; +wire [17:0] o_sigmoid_2; +wire sigmoid_valid_3, sigmoid_ready_3; +wire [17:0] o_add2_3; +wire [17:0] o_sigmoid_3; +wire sigmoid_valid_4, sigmoid_ready_4; +wire [17:0] o_add2_4; +wire [17:0] o_sigmoid_4; +wire sigmoid_valid_5, sigmoid_ready_5; +wire [17:0] o_add2_5; +wire [17:0] o_sigmoid_5; +wire sigmoid_valid_6, sigmoid_ready_6; +wire [17:0] o_add2_6; +wire [17:0] o_sigmoid_6; +wire sigmoid_valid_7, sigmoid_ready_7; +wire [17:0] o_add2_7; +wire [17:0] o_sigmoid_7; +wire sigmoid_valid_8, sigmoid_ready_8; +wire [17:0] o_add2_8; +wire [17:0] o_sigmoid_8; +wire sigmoid_valid_9, sigmoid_ready_9; +wire [17:0] o_add2_9; +wire [17:0] o_sigmoid_9; +wire sigmoid_valid_10, sigmoid_ready_10; +wire [17:0] o_add2_10; +wire [17:0] o_sigmoid_10; +wire sigmoid_valid_11, sigmoid_ready_11; +wire [17:0] o_add2_11; +wire [17:0] o_sigmoid_11; +wire sigmoid_valid_12, sigmoid_ready_12; +wire [17:0] o_add2_12; +wire [17:0] o_sigmoid_12; +wire sigmoid_valid_13, sigmoid_ready_13; +wire [17:0] o_add2_13; +wire [17:0] o_sigmoid_13; +wire sigmoid_valid_14, sigmoid_ready_14; +wire [17:0] o_add2_14; +wire [17:0] o_sigmoid_14; +wire sigmoid_valid_15, sigmoid_ready_15; +wire [17:0] o_add2_15; +wire [17:0] o_sigmoid_15; +wire sigmoid_valid_16, sigmoid_ready_16; +wire [17:0] o_add2_16; +wire [17:0] o_sigmoid_16; +wire sigmoid_valid_17, sigmoid_ready_17; +wire [17:0] o_add2_17; +wire [17:0] o_sigmoid_17; +wire sigmoid_valid_18, sigmoid_ready_18; +wire [17:0] o_add2_18; +wire [17:0] o_sigmoid_18; +wire sigmoid_valid_19, sigmoid_ready_19; +wire [17:0] o_add2_19; +wire [17:0] o_sigmoid_19; +wire sigmoid_valid_20, sigmoid_ready_20; +wire [17:0] o_add2_20; +wire [17:0] o_sigmoid_20; +wire sigmoid_valid_21, sigmoid_ready_21; +wire [17:0] o_add2_21; +wire [17:0] o_sigmoid_21; +wire sigmoid_valid_22, sigmoid_ready_22; +wire [17:0] o_add2_22; +wire [17:0] o_sigmoid_22; +wire sigmoid_valid_23, sigmoid_ready_23; +wire [17:0] o_add2_23; +wire [17:0] o_sigmoid_23; +wire sigmoid_valid_24, sigmoid_ready_24; +wire [17:0] o_add2_24; +wire [17:0] o_sigmoid_24; +wire sigmoid_valid_25, sigmoid_ready_25; +wire [17:0] o_add2_25; +wire [17:0] o_sigmoid_25; +wire sigmoid_valid_26, sigmoid_ready_26; +wire [17:0] o_add2_26; +wire [17:0] o_sigmoid_26; +wire sigmoid_valid_27, sigmoid_ready_27; +wire [17:0] o_add2_27; +wire [17:0] o_sigmoid_27; +wire sigmoid_valid_28, sigmoid_ready_28; +wire [17:0] o_add2_28; +wire [17:0] o_sigmoid_28; +wire sigmoid_valid_29, sigmoid_ready_29; +wire [17:0] o_add2_29; +wire [17:0] o_sigmoid_29; +wire sigmoid_valid_30, sigmoid_ready_30; +wire [17:0] o_add2_30; +wire [17:0] o_sigmoid_30; +wire sigmoid_valid_31, sigmoid_ready_31; +wire [17:0] o_add2_31; +wire [17:0] o_sigmoid_31; +wire sigmoid_valid_32, sigmoid_ready_32; +wire [17:0] o_add2_32; +wire [17:0] o_sigmoid_32; +wire sigmoid_valid_33, sigmoid_ready_33; +wire [17:0] o_add2_33; +wire [17:0] o_sigmoid_33; +wire sigmoid_valid_34, sigmoid_ready_34; +wire [17:0] o_add2_34; +wire [17:0] o_sigmoid_34; +wire sigmoid_valid_35, sigmoid_ready_35; +wire [17:0] o_add2_35; +wire [17:0] o_sigmoid_35; +wire sigmoid_valid_36, sigmoid_ready_36; +wire [17:0] o_add2_36; +wire [17:0] o_sigmoid_36; +wire sigmoid_valid_37, sigmoid_ready_37; +wire [17:0] o_add2_37; +wire [17:0] o_sigmoid_37; +wire sigmoid_valid_38, sigmoid_ready_38; +wire [17:0] o_add2_38; +wire [17:0] o_sigmoid_38; +wire sigmoid_valid_39, sigmoid_ready_39; +wire [17:0] o_add2_39; +wire [17:0] o_sigmoid_39; +wire sigmoid_valid_40, sigmoid_ready_40; +wire [17:0] o_add2_40; +wire [17:0] o_sigmoid_40; +wire sigmoid_valid_41, sigmoid_ready_41; +wire [17:0] o_add2_41; +wire [17:0] o_sigmoid_41; +wire sigmoid_valid_42, sigmoid_ready_42; +wire [17:0] o_add2_42; +wire [17:0] o_sigmoid_42; +wire sigmoid_valid_43, sigmoid_ready_43; +wire [17:0] o_add2_43; +wire [17:0] o_sigmoid_43; +wire sigmoid_valid_44, sigmoid_ready_44; +wire [17:0] o_add2_44; +wire [17:0] o_sigmoid_44; +wire sigmoid_valid_45, sigmoid_ready_45; +wire [17:0] o_add2_45; +wire [17:0] o_sigmoid_45; +wire sigmoid_valid_46, sigmoid_ready_46; +wire [17:0] o_add2_46; +wire [17:0] o_sigmoid_46; +wire sigmoid_valid_47, sigmoid_ready_47; +wire [17:0] o_add2_47; +wire [17:0] o_sigmoid_47; +elementwise_add_core_18_18_48 elementwise_add_core_18_18_48_inst_sarxyteszd ( + .clk(clk), + .reset(reset), + .i_valid(i_valid), + .i_ready(sigmoid_ready_0), + .i_A_0(stage1_result_0), + .i_B_0(bias_0), + .o_C_0(o_add2_0), + .i_A_1(stage1_result_1), + .i_B_1(bias_1), + .o_C_1(o_add2_1), + .i_A_2(stage1_result_2), + .i_B_2(bias_2), + .o_C_2(o_add2_2), + .i_A_3(stage1_result_3), + .i_B_3(bias_3), + .o_C_3(o_add2_3), + .i_A_4(stage1_result_4), + .i_B_4(bias_4), + .o_C_4(o_add2_4), + .i_A_5(stage1_result_5), + .i_B_5(bias_5), + .o_C_5(o_add2_5), + .i_A_6(stage1_result_6), + .i_B_6(bias_6), + .o_C_6(o_add2_6), + .i_A_7(stage1_result_7), + .i_B_7(bias_7), + .o_C_7(o_add2_7), + .i_A_8(stage1_result_8), + .i_B_8(bias_8), + .o_C_8(o_add2_8), + .i_A_9(stage1_result_9), + .i_B_9(bias_9), + .o_C_9(o_add2_9), + .i_A_10(stage1_result_10), + .i_B_10(bias_10), + .o_C_10(o_add2_10), + .i_A_11(stage1_result_11), + .i_B_11(bias_11), + .o_C_11(o_add2_11), + .i_A_12(stage1_result_12), + .i_B_12(bias_12), + .o_C_12(o_add2_12), + .i_A_13(stage1_result_13), + .i_B_13(bias_13), + .o_C_13(o_add2_13), + .i_A_14(stage1_result_14), + .i_B_14(bias_14), + .o_C_14(o_add2_14), + .i_A_15(stage1_result_15), + .i_B_15(bias_15), + .o_C_15(o_add2_15), + .i_A_16(stage1_result_16), + .i_B_16(bias_16), + .o_C_16(o_add2_16), + .i_A_17(stage1_result_17), + .i_B_17(bias_17), + .o_C_17(o_add2_17), + .i_A_18(stage1_result_18), + .i_B_18(bias_18), + .o_C_18(o_add2_18), + .i_A_19(stage1_result_19), + .i_B_19(bias_19), + .o_C_19(o_add2_19), + .i_A_20(stage1_result_20), + .i_B_20(bias_20), + .o_C_20(o_add2_20), + .i_A_21(stage1_result_21), + .i_B_21(bias_21), + .o_C_21(o_add2_21), + .i_A_22(stage1_result_22), + .i_B_22(bias_22), + .o_C_22(o_add2_22), + .i_A_23(stage1_result_23), + .i_B_23(bias_23), + .o_C_23(o_add2_23), + .i_A_24(stage1_result_24), + .i_B_24(bias_24), + .o_C_24(o_add2_24), + .i_A_25(stage1_result_25), + .i_B_25(bias_25), + .o_C_25(o_add2_25), + .i_A_26(stage1_result_26), + .i_B_26(bias_26), + .o_C_26(o_add2_26), + .i_A_27(stage1_result_27), + .i_B_27(bias_27), + .o_C_27(o_add2_27), + .i_A_28(stage1_result_28), + .i_B_28(bias_28), + .o_C_28(o_add2_28), + .i_A_29(stage1_result_29), + .i_B_29(bias_29), + .o_C_29(o_add2_29), + .i_A_30(stage1_result_30), + .i_B_30(bias_30), + .o_C_30(o_add2_30), + .i_A_31(stage1_result_31), + .i_B_31(bias_31), + .o_C_31(o_add2_31), + .i_A_32(stage1_result_32), + .i_B_32(bias_32), + .o_C_32(o_add2_32), + .i_A_33(stage1_result_33), + .i_B_33(bias_33), + .o_C_33(o_add2_33), + .i_A_34(stage1_result_34), + .i_B_34(bias_34), + .o_C_34(o_add2_34), + .i_A_35(stage1_result_35), + .i_B_35(bias_35), + .o_C_35(o_add2_35), + .i_A_36(stage1_result_36), + .i_B_36(bias_36), + .o_C_36(o_add2_36), + .i_A_37(stage1_result_37), + .i_B_37(bias_37), + .o_C_37(o_add2_37), + .i_A_38(stage1_result_38), + .i_B_38(bias_38), + .o_C_38(o_add2_38), + .i_A_39(stage1_result_39), + .i_B_39(bias_39), + .o_C_39(o_add2_39), + .i_A_40(stage1_result_40), + .i_B_40(bias_40), + .o_C_40(o_add2_40), + .i_A_41(stage1_result_41), + .i_B_41(bias_41), + .o_C_41(o_add2_41), + .i_A_42(stage1_result_42), + .i_B_42(bias_42), + .o_C_42(o_add2_42), + .i_A_43(stage1_result_43), + .i_B_43(bias_43), + .o_C_43(o_add2_43), + .i_A_44(stage1_result_44), + .i_B_44(bias_44), + .o_C_44(o_add2_44), + .i_A_45(stage1_result_45), + .i_B_45(bias_45), + .o_C_45(o_add2_45), + .i_A_46(stage1_result_46), + .i_B_46(bias_46), + .o_C_46(o_add2_46), + .i_A_47(stage1_result_47), + .i_B_47(bias_47), + .o_C_47(o_add2_47), + .o_valid(adder2_valid), + .o_ready(adder2_ready) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_0 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_0), + .o_valid(sigmoid_valid_0), + .i_x(o_add2_0), + .o_y(o_sigmoid_0) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_1 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_1), + .o_valid(sigmoid_valid_1), + .i_x(o_add2_1), + .o_y(o_sigmoid_1) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_2 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_2), + .o_valid(sigmoid_valid_2), + .i_x(o_add2_2), + .o_y(o_sigmoid_2) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_3 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_3), + .o_valid(sigmoid_valid_3), + .i_x(o_add2_3), + .o_y(o_sigmoid_3) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_4 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_4), + .o_valid(sigmoid_valid_4), + .i_x(o_add2_4), + .o_y(o_sigmoid_4) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_5 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_5), + .o_valid(sigmoid_valid_5), + .i_x(o_add2_5), + .o_y(o_sigmoid_5) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_6 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_6), + .o_valid(sigmoid_valid_6), + .i_x(o_add2_6), + .o_y(o_sigmoid_6) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_7 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_7), + .o_valid(sigmoid_valid_7), + .i_x(o_add2_7), + .o_y(o_sigmoid_7) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_8 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_8), + .o_valid(sigmoid_valid_8), + .i_x(o_add2_8), + .o_y(o_sigmoid_8) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_9 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_9), + .o_valid(sigmoid_valid_9), + .i_x(o_add2_9), + .o_y(o_sigmoid_9) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_10 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_10), + .o_valid(sigmoid_valid_10), + .i_x(o_add2_10), + .o_y(o_sigmoid_10) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_11 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_11), + .o_valid(sigmoid_valid_11), + .i_x(o_add2_11), + .o_y(o_sigmoid_11) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_12 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_12), + .o_valid(sigmoid_valid_12), + .i_x(o_add2_12), + .o_y(o_sigmoid_12) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_13 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_13), + .o_valid(sigmoid_valid_13), + .i_x(o_add2_13), + .o_y(o_sigmoid_13) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_14 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_14), + .o_valid(sigmoid_valid_14), + .i_x(o_add2_14), + .o_y(o_sigmoid_14) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_15 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_15), + .o_valid(sigmoid_valid_15), + .i_x(o_add2_15), + .o_y(o_sigmoid_15) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_16 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_16), + .o_valid(sigmoid_valid_16), + .i_x(o_add2_16), + .o_y(o_sigmoid_16) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_17 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_17), + .o_valid(sigmoid_valid_17), + .i_x(o_add2_17), + .o_y(o_sigmoid_17) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_18 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_18), + .o_valid(sigmoid_valid_18), + .i_x(o_add2_18), + .o_y(o_sigmoid_18) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_19 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_19), + .o_valid(sigmoid_valid_19), + .i_x(o_add2_19), + .o_y(o_sigmoid_19) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_20 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_20), + .o_valid(sigmoid_valid_20), + .i_x(o_add2_20), + .o_y(o_sigmoid_20) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_21 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_21), + .o_valid(sigmoid_valid_21), + .i_x(o_add2_21), + .o_y(o_sigmoid_21) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_22 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_22), + .o_valid(sigmoid_valid_22), + .i_x(o_add2_22), + .o_y(o_sigmoid_22) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_23 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_23), + .o_valid(sigmoid_valid_23), + .i_x(o_add2_23), + .o_y(o_sigmoid_23) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_24 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_24), + .o_valid(sigmoid_valid_24), + .i_x(o_add2_24), + .o_y(o_sigmoid_24) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_25 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_25), + .o_valid(sigmoid_valid_25), + .i_x(o_add2_25), + .o_y(o_sigmoid_25) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_26 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_26), + .o_valid(sigmoid_valid_26), + .i_x(o_add2_26), + .o_y(o_sigmoid_26) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_27 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_27), + .o_valid(sigmoid_valid_27), + .i_x(o_add2_27), + .o_y(o_sigmoid_27) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_28 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_28), + .o_valid(sigmoid_valid_28), + .i_x(o_add2_28), + .o_y(o_sigmoid_28) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_29 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_29), + .o_valid(sigmoid_valid_29), + .i_x(o_add2_29), + .o_y(o_sigmoid_29) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_30 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_30), + .o_valid(sigmoid_valid_30), + .i_x(o_add2_30), + .o_y(o_sigmoid_30) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_31 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_31), + .o_valid(sigmoid_valid_31), + .i_x(o_add2_31), + .o_y(o_sigmoid_31) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_32 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_32), + .o_valid(sigmoid_valid_32), + .i_x(o_add2_32), + .o_y(o_sigmoid_32) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_33 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_33), + .o_valid(sigmoid_valid_33), + .i_x(o_add2_33), + .o_y(o_sigmoid_33) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_34 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_34), + .o_valid(sigmoid_valid_34), + .i_x(o_add2_34), + .o_y(o_sigmoid_34) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_35 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_35), + .o_valid(sigmoid_valid_35), + .i_x(o_add2_35), + .o_y(o_sigmoid_35) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_36 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_36), + .o_valid(sigmoid_valid_36), + .i_x(o_add2_36), + .o_y(o_sigmoid_36) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_37 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_37), + .o_valid(sigmoid_valid_37), + .i_x(o_add2_37), + .o_y(o_sigmoid_37) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_38 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_38), + .o_valid(sigmoid_valid_38), + .i_x(o_add2_38), + .o_y(o_sigmoid_38) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_39 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_39), + .o_valid(sigmoid_valid_39), + .i_x(o_add2_39), + .o_y(o_sigmoid_39) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_40 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_40), + .o_valid(sigmoid_valid_40), + .i_x(o_add2_40), + .o_y(o_sigmoid_40) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_41 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_41), + .o_valid(sigmoid_valid_41), + .i_x(o_add2_41), + .o_y(o_sigmoid_41) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_42 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_42), + .o_valid(sigmoid_valid_42), + .i_x(o_add2_42), + .o_y(o_sigmoid_42) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_43 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_43), + .o_valid(sigmoid_valid_43), + .i_x(o_add2_43), + .o_y(o_sigmoid_43) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_44 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_44), + .o_valid(sigmoid_valid_44), + .i_x(o_add2_44), + .o_y(o_sigmoid_44) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_45 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_45), + .o_valid(sigmoid_valid_45), + .i_x(o_add2_45), + .o_y(o_sigmoid_45) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_46 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_46), + .o_valid(sigmoid_valid_46), + .i_x(o_add2_46), + .o_y(o_sigmoid_46) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_47 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_47), + .o_valid(sigmoid_valid_47), + .i_x(o_add2_47), + .o_y(o_sigmoid_47) +); + +assign o_ready = adder2_ready; +assign o_valid = sigmoid_valid_0 & i_ready; +assign output_value_0 = o_sigmoid_0; +assign output_value_1 = o_sigmoid_1; +assign output_value_2 = o_sigmoid_2; +assign output_value_3 = o_sigmoid_3; +assign output_value_4 = o_sigmoid_4; +assign output_value_5 = o_sigmoid_5; +assign output_value_6 = o_sigmoid_6; +assign output_value_7 = o_sigmoid_7; +assign output_value_8 = o_sigmoid_8; +assign output_value_9 = o_sigmoid_9; +assign output_value_10 = o_sigmoid_10; +assign output_value_11 = o_sigmoid_11; +assign output_value_12 = o_sigmoid_12; +assign output_value_13 = o_sigmoid_13; +assign output_value_14 = o_sigmoid_14; +assign output_value_15 = o_sigmoid_15; +assign output_value_16 = o_sigmoid_16; +assign output_value_17 = o_sigmoid_17; +assign output_value_18 = o_sigmoid_18; +assign output_value_19 = o_sigmoid_19; +assign output_value_20 = o_sigmoid_20; +assign output_value_21 = o_sigmoid_21; +assign output_value_22 = o_sigmoid_22; +assign output_value_23 = o_sigmoid_23; +assign output_value_24 = o_sigmoid_24; +assign output_value_25 = o_sigmoid_25; +assign output_value_26 = o_sigmoid_26; +assign output_value_27 = o_sigmoid_27; +assign output_value_28 = o_sigmoid_28; +assign output_value_29 = o_sigmoid_29; +assign output_value_30 = o_sigmoid_30; +assign output_value_31 = o_sigmoid_31; +assign output_value_32 = o_sigmoid_32; +assign output_value_33 = o_sigmoid_33; +assign output_value_34 = o_sigmoid_34; +assign output_value_35 = o_sigmoid_35; +assign output_value_36 = o_sigmoid_36; +assign output_value_37 = o_sigmoid_37; +assign output_value_38 = o_sigmoid_38; +assign output_value_39 = o_sigmoid_39; +assign output_value_40 = o_sigmoid_40; +assign output_value_41 = o_sigmoid_41; +assign output_value_42 = o_sigmoid_42; +assign output_value_43 = o_sigmoid_43; +assign output_value_44 = o_sigmoid_44; +assign output_value_45 = o_sigmoid_45; +assign output_value_46 = o_sigmoid_46; +assign output_value_47 = o_sigmoid_47; + +endmodule + +module shift_register_group_18_48_6 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input [17:0] in_16, + output [17:0] out_16, + input [17:0] in_17, + output [17:0] out_17, + input [17:0] in_18, + output [17:0] out_18, + input [17:0] in_19, + output [17:0] out_19, + input [17:0] in_20, + output [17:0] out_20, + input [17:0] in_21, + output [17:0] out_21, + input [17:0] in_22, + output [17:0] out_22, + input [17:0] in_23, + output [17:0] out_23, + input [17:0] in_24, + output [17:0] out_24, + input [17:0] in_25, + output [17:0] out_25, + input [17:0] in_26, + output [17:0] out_26, + input [17:0] in_27, + output [17:0] out_27, + input [17:0] in_28, + output [17:0] out_28, + input [17:0] in_29, + output [17:0] out_29, + input [17:0] in_30, + output [17:0] out_30, + input [17:0] in_31, + output [17:0] out_31, + input [17:0] in_32, + output [17:0] out_32, + input [17:0] in_33, + output [17:0] out_33, + input [17:0] in_34, + output [17:0] out_34, + input [17:0] in_35, + output [17:0] out_35, + input [17:0] in_36, + output [17:0] out_36, + input [17:0] in_37, + output [17:0] out_37, + input [17:0] in_38, + output [17:0] out_38, + input [17:0] in_39, + output [17:0] out_39, + input [17:0] in_40, + output [17:0] out_40, + input [17:0] in_41, + output [17:0] out_41, + input [17:0] in_42, + output [17:0] out_42, + input [17:0] in_43, + output [17:0] out_43, + input [17:0] in_44, + output [17:0] out_44, + input [17:0] in_45, + output [17:0] out_45, + input [17:0] in_46, + output [17:0] out_46, + input [17:0] in_47, + output [17:0] out_47, + input reset +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_16 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_16), + .out(out_16) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_17 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_17), + .out(out_17) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_18 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_18), + .out(out_18) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_19 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_19), + .out(out_19) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_20 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_20), + .out(out_20) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_21 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_21), + .out(out_21) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_22 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_22), + .out(out_22) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_23 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_23), + .out(out_23) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_24 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_24), + .out(out_24) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_25 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_25), + .out(out_25) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_26 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_26), + .out(out_26) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_27 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_27), + .out(out_27) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_28 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_28), + .out(out_28) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_29 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_29), + .out(out_29) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_30 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_30), + .out(out_30) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_31 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_31), + .out(out_31) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_32 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_32), + .out(out_32) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_33 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_33), + .out(out_33) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_34 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_34), + .out(out_34) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_35 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_35), + .out(out_35) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_36 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_36), + .out(out_36) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_37 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_37), + .out(out_37) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_38 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_38), + .out(out_38) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_39 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_39), + .out(out_39) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_40 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_40), + .out(out_40) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_41 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_41), + .out(out_41) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_42 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_42), + .out(out_42) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_43 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_43), + .out(out_43) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_44 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_44), + .out(out_44) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_45 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_45), + .out(out_45) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_46 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_46), + .out(out_46) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_47 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_47), + .out(out_47) +); + +endmodule + +module shift_register_unit_18_6 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +reg [17:0] shift_registers_1; +reg [17:0] shift_registers_2; +reg [17:0] shift_registers_3; +reg [17:0] shift_registers_4; +reg [17:0] shift_registers_5; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + shift_registers_1 <= 18'd0; + shift_registers_2 <= 18'd0; + shift_registers_3 <= 18'd0; + shift_registers_4 <= 18'd0; + shift_registers_5 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + shift_registers_3 <= shift_registers_2; + shift_registers_4 <= shift_registers_3; + shift_registers_5 <= shift_registers_4; + end +end + +assign out = shift_registers_5; + +endmodule + +module elementwise_mult_core_18_18_10_48_1 ( + input clk, + input reset, + input i_valid, + input i_ready, + input [17:0] i_A_0, + input [17:0] i_B_0, + output [17:0] o_C_0, + input [17:0] i_A_1, + input [17:0] i_B_1, + output [17:0] o_C_1, + input [17:0] i_A_2, + input [17:0] i_B_2, + output [17:0] o_C_2, + input [17:0] i_A_3, + input [17:0] i_B_3, + output [17:0] o_C_3, + input [17:0] i_A_4, + input [17:0] i_B_4, + output [17:0] o_C_4, + input [17:0] i_A_5, + input [17:0] i_B_5, + output [17:0] o_C_5, + input [17:0] i_A_6, + input [17:0] i_B_6, + output [17:0] o_C_6, + input [17:0] i_A_7, + input [17:0] i_B_7, + output [17:0] o_C_7, + input [17:0] i_A_8, + input [17:0] i_B_8, + output [17:0] o_C_8, + input [17:0] i_A_9, + input [17:0] i_B_9, + output [17:0] o_C_9, + input [17:0] i_A_10, + input [17:0] i_B_10, + output [17:0] o_C_10, + input [17:0] i_A_11, + input [17:0] i_B_11, + output [17:0] o_C_11, + input [17:0] i_A_12, + input [17:0] i_B_12, + output [17:0] o_C_12, + input [17:0] i_A_13, + input [17:0] i_B_13, + output [17:0] o_C_13, + input [17:0] i_A_14, + input [17:0] i_B_14, + output [17:0] o_C_14, + input [17:0] i_A_15, + input [17:0] i_B_15, + output [17:0] o_C_15, + input [17:0] i_A_16, + input [17:0] i_B_16, + output [17:0] o_C_16, + input [17:0] i_A_17, + input [17:0] i_B_17, + output [17:0] o_C_17, + input [17:0] i_A_18, + input [17:0] i_B_18, + output [17:0] o_C_18, + input [17:0] i_A_19, + input [17:0] i_B_19, + output [17:0] o_C_19, + input [17:0] i_A_20, + input [17:0] i_B_20, + output [17:0] o_C_20, + input [17:0] i_A_21, + input [17:0] i_B_21, + output [17:0] o_C_21, + input [17:0] i_A_22, + input [17:0] i_B_22, + output [17:0] o_C_22, + input [17:0] i_A_23, + input [17:0] i_B_23, + output [17:0] o_C_23, + input [17:0] i_A_24, + input [17:0] i_B_24, + output [17:0] o_C_24, + input [17:0] i_A_25, + input [17:0] i_B_25, + output [17:0] o_C_25, + input [17:0] i_A_26, + input [17:0] i_B_26, + output [17:0] o_C_26, + input [17:0] i_A_27, + input [17:0] i_B_27, + output [17:0] o_C_27, + input [17:0] i_A_28, + input [17:0] i_B_28, + output [17:0] o_C_28, + input [17:0] i_A_29, + input [17:0] i_B_29, + output [17:0] o_C_29, + input [17:0] i_A_30, + input [17:0] i_B_30, + output [17:0] o_C_30, + input [17:0] i_A_31, + input [17:0] i_B_31, + output [17:0] o_C_31, + input [17:0] i_A_32, + input [17:0] i_B_32, + output [17:0] o_C_32, + input [17:0] i_A_33, + input [17:0] i_B_33, + output [17:0] o_C_33, + input [17:0] i_A_34, + input [17:0] i_B_34, + output [17:0] o_C_34, + input [17:0] i_A_35, + input [17:0] i_B_35, + output [17:0] o_C_35, + input [17:0] i_A_36, + input [17:0] i_B_36, + output [17:0] o_C_36, + input [17:0] i_A_37, + input [17:0] i_B_37, + output [17:0] o_C_37, + input [17:0] i_A_38, + input [17:0] i_B_38, + output [17:0] o_C_38, + input [17:0] i_A_39, + input [17:0] i_B_39, + output [17:0] o_C_39, + input [17:0] i_A_40, + input [17:0] i_B_40, + output [17:0] o_C_40, + input [17:0] i_A_41, + input [17:0] i_B_41, + output [17:0] o_C_41, + input [17:0] i_A_42, + input [17:0] i_B_42, + output [17:0] o_C_42, + input [17:0] i_A_43, + input [17:0] i_B_43, + output [17:0] o_C_43, + input [17:0] i_A_44, + input [17:0] i_B_44, + output [17:0] o_C_44, + input [17:0] i_A_45, + input [17:0] i_B_45, + output [17:0] o_C_45, + input [17:0] i_A_46, + input [17:0] i_B_46, + output [17:0] o_C_46, + input [17:0] i_A_47, + input [17:0] i_B_47, + output [17:0] o_C_47, + output o_valid, + output o_ready +); + +// Store inputs and outputs in registers +reg [17:0] reg_A_0; +reg [17:0] reg_B_0; +wire [17:0] reg_C_0; +reg [17:0] reg_A_1; +reg [17:0] reg_B_1; +wire [17:0] reg_C_1; +reg [17:0] reg_A_2; +reg [17:0] reg_B_2; +wire [17:0] reg_C_2; +reg [17:0] reg_A_3; +reg [17:0] reg_B_3; +wire [17:0] reg_C_3; +reg [17:0] reg_A_4; +reg [17:0] reg_B_4; +wire [17:0] reg_C_4; +reg [17:0] reg_A_5; +reg [17:0] reg_B_5; +wire [17:0] reg_C_5; +reg [17:0] reg_A_6; +reg [17:0] reg_B_6; +wire [17:0] reg_C_6; +reg [17:0] reg_A_7; +reg [17:0] reg_B_7; +wire [17:0] reg_C_7; +reg [17:0] reg_A_8; +reg [17:0] reg_B_8; +wire [17:0] reg_C_8; +reg [17:0] reg_A_9; +reg [17:0] reg_B_9; +wire [17:0] reg_C_9; +reg [17:0] reg_A_10; +reg [17:0] reg_B_10; +wire [17:0] reg_C_10; +reg [17:0] reg_A_11; +reg [17:0] reg_B_11; +wire [17:0] reg_C_11; +reg [17:0] reg_A_12; +reg [17:0] reg_B_12; +wire [17:0] reg_C_12; +reg [17:0] reg_A_13; +reg [17:0] reg_B_13; +wire [17:0] reg_C_13; +reg [17:0] reg_A_14; +reg [17:0] reg_B_14; +wire [17:0] reg_C_14; +reg [17:0] reg_A_15; +reg [17:0] reg_B_15; +wire [17:0] reg_C_15; +reg [17:0] reg_A_16; +reg [17:0] reg_B_16; +wire [17:0] reg_C_16; +reg [17:0] reg_A_17; +reg [17:0] reg_B_17; +wire [17:0] reg_C_17; +reg [17:0] reg_A_18; +reg [17:0] reg_B_18; +wire [17:0] reg_C_18; +reg [17:0] reg_A_19; +reg [17:0] reg_B_19; +wire [17:0] reg_C_19; +reg [17:0] reg_A_20; +reg [17:0] reg_B_20; +wire [17:0] reg_C_20; +reg [17:0] reg_A_21; +reg [17:0] reg_B_21; +wire [17:0] reg_C_21; +reg [17:0] reg_A_22; +reg [17:0] reg_B_22; +wire [17:0] reg_C_22; +reg [17:0] reg_A_23; +reg [17:0] reg_B_23; +wire [17:0] reg_C_23; +reg [17:0] reg_A_24; +reg [17:0] reg_B_24; +wire [17:0] reg_C_24; +reg [17:0] reg_A_25; +reg [17:0] reg_B_25; +wire [17:0] reg_C_25; +reg [17:0] reg_A_26; +reg [17:0] reg_B_26; +wire [17:0] reg_C_26; +reg [17:0] reg_A_27; +reg [17:0] reg_B_27; +wire [17:0] reg_C_27; +reg [17:0] reg_A_28; +reg [17:0] reg_B_28; +wire [17:0] reg_C_28; +reg [17:0] reg_A_29; +reg [17:0] reg_B_29; +wire [17:0] reg_C_29; +reg [17:0] reg_A_30; +reg [17:0] reg_B_30; +wire [17:0] reg_C_30; +reg [17:0] reg_A_31; +reg [17:0] reg_B_31; +wire [17:0] reg_C_31; +reg [17:0] reg_A_32; +reg [17:0] reg_B_32; +wire [17:0] reg_C_32; +reg [17:0] reg_A_33; +reg [17:0] reg_B_33; +wire [17:0] reg_C_33; +reg [17:0] reg_A_34; +reg [17:0] reg_B_34; +wire [17:0] reg_C_34; +reg [17:0] reg_A_35; +reg [17:0] reg_B_35; +wire [17:0] reg_C_35; +reg [17:0] reg_A_36; +reg [17:0] reg_B_36; +wire [17:0] reg_C_36; +reg [17:0] reg_A_37; +reg [17:0] reg_B_37; +wire [17:0] reg_C_37; +reg [17:0] reg_A_38; +reg [17:0] reg_B_38; +wire [17:0] reg_C_38; +reg [17:0] reg_A_39; +reg [17:0] reg_B_39; +wire [17:0] reg_C_39; +reg [17:0] reg_A_40; +reg [17:0] reg_B_40; +wire [17:0] reg_C_40; +reg [17:0] reg_A_41; +reg [17:0] reg_B_41; +wire [17:0] reg_C_41; +reg [17:0] reg_A_42; +reg [17:0] reg_B_42; +wire [17:0] reg_C_42; +reg [17:0] reg_A_43; +reg [17:0] reg_B_43; +wire [17:0] reg_C_43; +reg [17:0] reg_A_44; +reg [17:0] reg_B_44; +wire [17:0] reg_C_44; +reg [17:0] reg_A_45; +reg [17:0] reg_B_45; +wire [17:0] reg_C_45; +reg [17:0] reg_A_46; +reg [17:0] reg_B_46; +wire [17:0] reg_C_46; +reg [17:0] reg_A_47; +reg [17:0] reg_B_47; +wire [17:0] reg_C_47; + +reg valid_A_B; +wire valid_C; +wire enable; +assign enable = i_ready; + +wire mult_valid_0; +wire round_valid_0; +wire [36:0] mult_C_0; +wire [36:0] rounded_C_0; +wire mult_valid_1; +wire round_valid_1; +wire [36:0] mult_C_1; +wire [36:0] rounded_C_1; +wire mult_valid_2; +wire round_valid_2; +wire [36:0] mult_C_2; +wire [36:0] rounded_C_2; +wire mult_valid_3; +wire round_valid_3; +wire [36:0] mult_C_3; +wire [36:0] rounded_C_3; +wire mult_valid_4; +wire round_valid_4; +wire [36:0] mult_C_4; +wire [36:0] rounded_C_4; +wire mult_valid_5; +wire round_valid_5; +wire [36:0] mult_C_5; +wire [36:0] rounded_C_5; +wire mult_valid_6; +wire round_valid_6; +wire [36:0] mult_C_6; +wire [36:0] rounded_C_6; +wire mult_valid_7; +wire round_valid_7; +wire [36:0] mult_C_7; +wire [36:0] rounded_C_7; +wire mult_valid_8; +wire round_valid_8; +wire [36:0] mult_C_8; +wire [36:0] rounded_C_8; +wire mult_valid_9; +wire round_valid_9; +wire [36:0] mult_C_9; +wire [36:0] rounded_C_9; +wire mult_valid_10; +wire round_valid_10; +wire [36:0] mult_C_10; +wire [36:0] rounded_C_10; +wire mult_valid_11; +wire round_valid_11; +wire [36:0] mult_C_11; +wire [36:0] rounded_C_11; +wire mult_valid_12; +wire round_valid_12; +wire [36:0] mult_C_12; +wire [36:0] rounded_C_12; +wire mult_valid_13; +wire round_valid_13; +wire [36:0] mult_C_13; +wire [36:0] rounded_C_13; +wire mult_valid_14; +wire round_valid_14; +wire [36:0] mult_C_14; +wire [36:0] rounded_C_14; +wire mult_valid_15; +wire round_valid_15; +wire [36:0] mult_C_15; +wire [36:0] rounded_C_15; +wire mult_valid_16; +wire round_valid_16; +wire [36:0] mult_C_16; +wire [36:0] rounded_C_16; +wire mult_valid_17; +wire round_valid_17; +wire [36:0] mult_C_17; +wire [36:0] rounded_C_17; +wire mult_valid_18; +wire round_valid_18; +wire [36:0] mult_C_18; +wire [36:0] rounded_C_18; +wire mult_valid_19; +wire round_valid_19; +wire [36:0] mult_C_19; +wire [36:0] rounded_C_19; +wire mult_valid_20; +wire round_valid_20; +wire [36:0] mult_C_20; +wire [36:0] rounded_C_20; +wire mult_valid_21; +wire round_valid_21; +wire [36:0] mult_C_21; +wire [36:0] rounded_C_21; +wire mult_valid_22; +wire round_valid_22; +wire [36:0] mult_C_22; +wire [36:0] rounded_C_22; +wire mult_valid_23; +wire round_valid_23; +wire [36:0] mult_C_23; +wire [36:0] rounded_C_23; +wire mult_valid_24; +wire round_valid_24; +wire [36:0] mult_C_24; +wire [36:0] rounded_C_24; +wire mult_valid_25; +wire round_valid_25; +wire [36:0] mult_C_25; +wire [36:0] rounded_C_25; +wire mult_valid_26; +wire round_valid_26; +wire [36:0] mult_C_26; +wire [36:0] rounded_C_26; +wire mult_valid_27; +wire round_valid_27; +wire [36:0] mult_C_27; +wire [36:0] rounded_C_27; +wire mult_valid_28; +wire round_valid_28; +wire [36:0] mult_C_28; +wire [36:0] rounded_C_28; +wire mult_valid_29; +wire round_valid_29; +wire [36:0] mult_C_29; +wire [36:0] rounded_C_29; +wire mult_valid_30; +wire round_valid_30; +wire [36:0] mult_C_30; +wire [36:0] rounded_C_30; +wire mult_valid_31; +wire round_valid_31; +wire [36:0] mult_C_31; +wire [36:0] rounded_C_31; +wire mult_valid_32; +wire round_valid_32; +wire [36:0] mult_C_32; +wire [36:0] rounded_C_32; +wire mult_valid_33; +wire round_valid_33; +wire [36:0] mult_C_33; +wire [36:0] rounded_C_33; +wire mult_valid_34; +wire round_valid_34; +wire [36:0] mult_C_34; +wire [36:0] rounded_C_34; +wire mult_valid_35; +wire round_valid_35; +wire [36:0] mult_C_35; +wire [36:0] rounded_C_35; +wire mult_valid_36; +wire round_valid_36; +wire [36:0] mult_C_36; +wire [36:0] rounded_C_36; +wire mult_valid_37; +wire round_valid_37; +wire [36:0] mult_C_37; +wire [36:0] rounded_C_37; +wire mult_valid_38; +wire round_valid_38; +wire [36:0] mult_C_38; +wire [36:0] rounded_C_38; +wire mult_valid_39; +wire round_valid_39; +wire [36:0] mult_C_39; +wire [36:0] rounded_C_39; +wire mult_valid_40; +wire round_valid_40; +wire [36:0] mult_C_40; +wire [36:0] rounded_C_40; +wire mult_valid_41; +wire round_valid_41; +wire [36:0] mult_C_41; +wire [36:0] rounded_C_41; +wire mult_valid_42; +wire round_valid_42; +wire [36:0] mult_C_42; +wire [36:0] rounded_C_42; +wire mult_valid_43; +wire round_valid_43; +wire [36:0] mult_C_43; +wire [36:0] rounded_C_43; +wire mult_valid_44; +wire round_valid_44; +wire [36:0] mult_C_44; +wire [36:0] rounded_C_44; +wire mult_valid_45; +wire round_valid_45; +wire [36:0] mult_C_45; +wire [36:0] rounded_C_45; +wire mult_valid_46; +wire round_valid_46; +wire [36:0] mult_C_46; +wire [36:0] rounded_C_46; +wire mult_valid_47; +wire round_valid_47; +wire [36:0] mult_C_47; +wire [36:0] rounded_C_47; + +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst0 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_0), + .ay(reg_B_0), + .bx(reg_A_1), + .by(reg_B_1), + .o_valid(mult_valid_0), + .resulta(mult_C_0), + .resultb(mult_C_1) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst2 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_2), + .ay(reg_B_2), + .bx(reg_A_3), + .by(reg_B_3), + .o_valid(mult_valid_2), + .resulta(mult_C_2), + .resultb(mult_C_3) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst4 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_4), + .ay(reg_B_4), + .bx(reg_A_5), + .by(reg_B_5), + .o_valid(mult_valid_4), + .resulta(mult_C_4), + .resultb(mult_C_5) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst6 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_6), + .ay(reg_B_6), + .bx(reg_A_7), + .by(reg_B_7), + .o_valid(mult_valid_6), + .resulta(mult_C_6), + .resultb(mult_C_7) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst8 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_8), + .ay(reg_B_8), + .bx(reg_A_9), + .by(reg_B_9), + .o_valid(mult_valid_8), + .resulta(mult_C_8), + .resultb(mult_C_9) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst10 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_10), + .ay(reg_B_10), + .bx(reg_A_11), + .by(reg_B_11), + .o_valid(mult_valid_10), + .resulta(mult_C_10), + .resultb(mult_C_11) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst12 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_12), + .ay(reg_B_12), + .bx(reg_A_13), + .by(reg_B_13), + .o_valid(mult_valid_12), + .resulta(mult_C_12), + .resultb(mult_C_13) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst14 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_14), + .ay(reg_B_14), + .bx(reg_A_15), + .by(reg_B_15), + .o_valid(mult_valid_14), + .resulta(mult_C_14), + .resultb(mult_C_15) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst16 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_16), + .ay(reg_B_16), + .bx(reg_A_17), + .by(reg_B_17), + .o_valid(mult_valid_16), + .resulta(mult_C_16), + .resultb(mult_C_17) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst18 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_18), + .ay(reg_B_18), + .bx(reg_A_19), + .by(reg_B_19), + .o_valid(mult_valid_18), + .resulta(mult_C_18), + .resultb(mult_C_19) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst20 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_20), + .ay(reg_B_20), + .bx(reg_A_21), + .by(reg_B_21), + .o_valid(mult_valid_20), + .resulta(mult_C_20), + .resultb(mult_C_21) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst22 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_22), + .ay(reg_B_22), + .bx(reg_A_23), + .by(reg_B_23), + .o_valid(mult_valid_22), + .resulta(mult_C_22), + .resultb(mult_C_23) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst24 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_24), + .ay(reg_B_24), + .bx(reg_A_25), + .by(reg_B_25), + .o_valid(mult_valid_24), + .resulta(mult_C_24), + .resultb(mult_C_25) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst26 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_26), + .ay(reg_B_26), + .bx(reg_A_27), + .by(reg_B_27), + .o_valid(mult_valid_26), + .resulta(mult_C_26), + .resultb(mult_C_27) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst28 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_28), + .ay(reg_B_28), + .bx(reg_A_29), + .by(reg_B_29), + .o_valid(mult_valid_28), + .resulta(mult_C_28), + .resultb(mult_C_29) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst30 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_30), + .ay(reg_B_30), + .bx(reg_A_31), + .by(reg_B_31), + .o_valid(mult_valid_30), + .resulta(mult_C_30), + .resultb(mult_C_31) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst32 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_32), + .ay(reg_B_32), + .bx(reg_A_33), + .by(reg_B_33), + .o_valid(mult_valid_32), + .resulta(mult_C_32), + .resultb(mult_C_33) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst34 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_34), + .ay(reg_B_34), + .bx(reg_A_35), + .by(reg_B_35), + .o_valid(mult_valid_34), + .resulta(mult_C_34), + .resultb(mult_C_35) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst36 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_36), + .ay(reg_B_36), + .bx(reg_A_37), + .by(reg_B_37), + .o_valid(mult_valid_36), + .resulta(mult_C_36), + .resultb(mult_C_37) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst38 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_38), + .ay(reg_B_38), + .bx(reg_A_39), + .by(reg_B_39), + .o_valid(mult_valid_38), + .resulta(mult_C_38), + .resultb(mult_C_39) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst40 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_40), + .ay(reg_B_40), + .bx(reg_A_41), + .by(reg_B_41), + .o_valid(mult_valid_40), + .resulta(mult_C_40), + .resultb(mult_C_41) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst42 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_42), + .ay(reg_B_42), + .bx(reg_A_43), + .by(reg_B_43), + .o_valid(mult_valid_42), + .resulta(mult_C_42), + .resultb(mult_C_43) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst44 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_44), + .ay(reg_B_44), + .bx(reg_A_45), + .by(reg_B_45), + .o_valid(mult_valid_44), + .resulta(mult_C_44), + .resultb(mult_C_45) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst46 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_46), + .ay(reg_B_46), + .bx(reg_A_47), + .by(reg_B_47), + .o_valid(mult_valid_46), + .resulta(mult_C_46), + .resultb(mult_C_47) +); +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_0), + .in(mult_C_0), + .o_valid(round_valid_0), + .out(rounded_C_0) +); +assign reg_C_0 = rounded_C_0[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_1), + .in(mult_C_1), + .o_valid(round_valid_1), + .out(rounded_C_1) +); +assign reg_C_1 = rounded_C_1[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_2), + .in(mult_C_2), + .o_valid(round_valid_2), + .out(rounded_C_2) +); +assign reg_C_2 = rounded_C_2[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_3), + .in(mult_C_3), + .o_valid(round_valid_3), + .out(rounded_C_3) +); +assign reg_C_3 = rounded_C_3[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_4), + .in(mult_C_4), + .o_valid(round_valid_4), + .out(rounded_C_4) +); +assign reg_C_4 = rounded_C_4[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_5), + .in(mult_C_5), + .o_valid(round_valid_5), + .out(rounded_C_5) +); +assign reg_C_5 = rounded_C_5[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_6), + .in(mult_C_6), + .o_valid(round_valid_6), + .out(rounded_C_6) +); +assign reg_C_6 = rounded_C_6[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_7), + .in(mult_C_7), + .o_valid(round_valid_7), + .out(rounded_C_7) +); +assign reg_C_7 = rounded_C_7[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_8), + .in(mult_C_8), + .o_valid(round_valid_8), + .out(rounded_C_8) +); +assign reg_C_8 = rounded_C_8[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_9), + .in(mult_C_9), + .o_valid(round_valid_9), + .out(rounded_C_9) +); +assign reg_C_9 = rounded_C_9[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_10), + .in(mult_C_10), + .o_valid(round_valid_10), + .out(rounded_C_10) +); +assign reg_C_10 = rounded_C_10[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_11), + .in(mult_C_11), + .o_valid(round_valid_11), + .out(rounded_C_11) +); +assign reg_C_11 = rounded_C_11[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_12), + .in(mult_C_12), + .o_valid(round_valid_12), + .out(rounded_C_12) +); +assign reg_C_12 = rounded_C_12[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_13), + .in(mult_C_13), + .o_valid(round_valid_13), + .out(rounded_C_13) +); +assign reg_C_13 = rounded_C_13[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_14), + .in(mult_C_14), + .o_valid(round_valid_14), + .out(rounded_C_14) +); +assign reg_C_14 = rounded_C_14[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_15), + .in(mult_C_15), + .o_valid(round_valid_15), + .out(rounded_C_15) +); +assign reg_C_15 = rounded_C_15[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst16 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_16), + .in(mult_C_16), + .o_valid(round_valid_16), + .out(rounded_C_16) +); +assign reg_C_16 = rounded_C_16[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst17 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_17), + .in(mult_C_17), + .o_valid(round_valid_17), + .out(rounded_C_17) +); +assign reg_C_17 = rounded_C_17[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst18 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_18), + .in(mult_C_18), + .o_valid(round_valid_18), + .out(rounded_C_18) +); +assign reg_C_18 = rounded_C_18[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst19 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_19), + .in(mult_C_19), + .o_valid(round_valid_19), + .out(rounded_C_19) +); +assign reg_C_19 = rounded_C_19[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst20 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_20), + .in(mult_C_20), + .o_valid(round_valid_20), + .out(rounded_C_20) +); +assign reg_C_20 = rounded_C_20[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst21 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_21), + .in(mult_C_21), + .o_valid(round_valid_21), + .out(rounded_C_21) +); +assign reg_C_21 = rounded_C_21[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst22 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_22), + .in(mult_C_22), + .o_valid(round_valid_22), + .out(rounded_C_22) +); +assign reg_C_22 = rounded_C_22[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst23 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_23), + .in(mult_C_23), + .o_valid(round_valid_23), + .out(rounded_C_23) +); +assign reg_C_23 = rounded_C_23[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst24 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_24), + .in(mult_C_24), + .o_valid(round_valid_24), + .out(rounded_C_24) +); +assign reg_C_24 = rounded_C_24[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst25 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_25), + .in(mult_C_25), + .o_valid(round_valid_25), + .out(rounded_C_25) +); +assign reg_C_25 = rounded_C_25[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst26 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_26), + .in(mult_C_26), + .o_valid(round_valid_26), + .out(rounded_C_26) +); +assign reg_C_26 = rounded_C_26[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst27 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_27), + .in(mult_C_27), + .o_valid(round_valid_27), + .out(rounded_C_27) +); +assign reg_C_27 = rounded_C_27[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst28 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_28), + .in(mult_C_28), + .o_valid(round_valid_28), + .out(rounded_C_28) +); +assign reg_C_28 = rounded_C_28[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst29 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_29), + .in(mult_C_29), + .o_valid(round_valid_29), + .out(rounded_C_29) +); +assign reg_C_29 = rounded_C_29[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst30 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_30), + .in(mult_C_30), + .o_valid(round_valid_30), + .out(rounded_C_30) +); +assign reg_C_30 = rounded_C_30[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst31 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_31), + .in(mult_C_31), + .o_valid(round_valid_31), + .out(rounded_C_31) +); +assign reg_C_31 = rounded_C_31[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst32 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_32), + .in(mult_C_32), + .o_valid(round_valid_32), + .out(rounded_C_32) +); +assign reg_C_32 = rounded_C_32[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst33 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_33), + .in(mult_C_33), + .o_valid(round_valid_33), + .out(rounded_C_33) +); +assign reg_C_33 = rounded_C_33[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst34 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_34), + .in(mult_C_34), + .o_valid(round_valid_34), + .out(rounded_C_34) +); +assign reg_C_34 = rounded_C_34[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst35 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_35), + .in(mult_C_35), + .o_valid(round_valid_35), + .out(rounded_C_35) +); +assign reg_C_35 = rounded_C_35[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst36 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_36), + .in(mult_C_36), + .o_valid(round_valid_36), + .out(rounded_C_36) +); +assign reg_C_36 = rounded_C_36[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst37 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_37), + .in(mult_C_37), + .o_valid(round_valid_37), + .out(rounded_C_37) +); +assign reg_C_37 = rounded_C_37[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst38 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_38), + .in(mult_C_38), + .o_valid(round_valid_38), + .out(rounded_C_38) +); +assign reg_C_38 = rounded_C_38[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst39 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_39), + .in(mult_C_39), + .o_valid(round_valid_39), + .out(rounded_C_39) +); +assign reg_C_39 = rounded_C_39[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst40 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_40), + .in(mult_C_40), + .o_valid(round_valid_40), + .out(rounded_C_40) +); +assign reg_C_40 = rounded_C_40[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst41 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_41), + .in(mult_C_41), + .o_valid(round_valid_41), + .out(rounded_C_41) +); +assign reg_C_41 = rounded_C_41[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst42 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_42), + .in(mult_C_42), + .o_valid(round_valid_42), + .out(rounded_C_42) +); +assign reg_C_42 = rounded_C_42[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst43 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_43), + .in(mult_C_43), + .o_valid(round_valid_43), + .out(rounded_C_43) +); +assign reg_C_43 = rounded_C_43[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst44 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_44), + .in(mult_C_44), + .o_valid(round_valid_44), + .out(rounded_C_44) +); +assign reg_C_44 = rounded_C_44[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst45 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_45), + .in(mult_C_45), + .o_valid(round_valid_45), + .out(rounded_C_45) +); +assign reg_C_45 = rounded_C_45[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst46 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_46), + .in(mult_C_46), + .o_valid(round_valid_46), + .out(rounded_C_46) +); +assign reg_C_46 = rounded_C_46[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst47 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_47), + .in(mult_C_47), + .o_valid(round_valid_47), + .out(rounded_C_47) +); +assign reg_C_47 = rounded_C_47[17:0]; +always @ (posedge clk) begin + if (reset) begin + valid_A_B <= 1'b0; + reg_A_0 <= 0; + reg_B_0 <= 0; + reg_A_1 <= 0; + reg_B_1 <= 0; + reg_A_2 <= 0; + reg_B_2 <= 0; + reg_A_3 <= 0; + reg_B_3 <= 0; + reg_A_4 <= 0; + reg_B_4 <= 0; + reg_A_5 <= 0; + reg_B_5 <= 0; + reg_A_6 <= 0; + reg_B_6 <= 0; + reg_A_7 <= 0; + reg_B_7 <= 0; + reg_A_8 <= 0; + reg_B_8 <= 0; + reg_A_9 <= 0; + reg_B_9 <= 0; + reg_A_10 <= 0; + reg_B_10 <= 0; + reg_A_11 <= 0; + reg_B_11 <= 0; + reg_A_12 <= 0; + reg_B_12 <= 0; + reg_A_13 <= 0; + reg_B_13 <= 0; + reg_A_14 <= 0; + reg_B_14 <= 0; + reg_A_15 <= 0; + reg_B_15 <= 0; + reg_A_16 <= 0; + reg_B_16 <= 0; + reg_A_17 <= 0; + reg_B_17 <= 0; + reg_A_18 <= 0; + reg_B_18 <= 0; + reg_A_19 <= 0; + reg_B_19 <= 0; + reg_A_20 <= 0; + reg_B_20 <= 0; + reg_A_21 <= 0; + reg_B_21 <= 0; + reg_A_22 <= 0; + reg_B_22 <= 0; + reg_A_23 <= 0; + reg_B_23 <= 0; + reg_A_24 <= 0; + reg_B_24 <= 0; + reg_A_25 <= 0; + reg_B_25 <= 0; + reg_A_26 <= 0; + reg_B_26 <= 0; + reg_A_27 <= 0; + reg_B_27 <= 0; + reg_A_28 <= 0; + reg_B_28 <= 0; + reg_A_29 <= 0; + reg_B_29 <= 0; + reg_A_30 <= 0; + reg_B_30 <= 0; + reg_A_31 <= 0; + reg_B_31 <= 0; + reg_A_32 <= 0; + reg_B_32 <= 0; + reg_A_33 <= 0; + reg_B_33 <= 0; + reg_A_34 <= 0; + reg_B_34 <= 0; + reg_A_35 <= 0; + reg_B_35 <= 0; + reg_A_36 <= 0; + reg_B_36 <= 0; + reg_A_37 <= 0; + reg_B_37 <= 0; + reg_A_38 <= 0; + reg_B_38 <= 0; + reg_A_39 <= 0; + reg_B_39 <= 0; + reg_A_40 <= 0; + reg_B_40 <= 0; + reg_A_41 <= 0; + reg_B_41 <= 0; + reg_A_42 <= 0; + reg_B_42 <= 0; + reg_A_43 <= 0; + reg_B_43 <= 0; + reg_A_44 <= 0; + reg_B_44 <= 0; + reg_A_45 <= 0; + reg_B_45 <= 0; + reg_A_46 <= 0; + reg_B_46 <= 0; + reg_A_47 <= 0; + reg_B_47 <= 0; + end else if (enable) begin + reg_A_0 <= i_A_0; + reg_B_0 <= i_B_0; + reg_A_1 <= i_A_1; + reg_B_1 <= i_B_1; + reg_A_2 <= i_A_2; + reg_B_2 <= i_B_2; + reg_A_3 <= i_A_3; + reg_B_3 <= i_B_3; + reg_A_4 <= i_A_4; + reg_B_4 <= i_B_4; + reg_A_5 <= i_A_5; + reg_B_5 <= i_B_5; + reg_A_6 <= i_A_6; + reg_B_6 <= i_B_6; + reg_A_7 <= i_A_7; + reg_B_7 <= i_B_7; + reg_A_8 <= i_A_8; + reg_B_8 <= i_B_8; + reg_A_9 <= i_A_9; + reg_B_9 <= i_B_9; + reg_A_10 <= i_A_10; + reg_B_10 <= i_B_10; + reg_A_11 <= i_A_11; + reg_B_11 <= i_B_11; + reg_A_12 <= i_A_12; + reg_B_12 <= i_B_12; + reg_A_13 <= i_A_13; + reg_B_13 <= i_B_13; + reg_A_14 <= i_A_14; + reg_B_14 <= i_B_14; + reg_A_15 <= i_A_15; + reg_B_15 <= i_B_15; + reg_A_16 <= i_A_16; + reg_B_16 <= i_B_16; + reg_A_17 <= i_A_17; + reg_B_17 <= i_B_17; + reg_A_18 <= i_A_18; + reg_B_18 <= i_B_18; + reg_A_19 <= i_A_19; + reg_B_19 <= i_B_19; + reg_A_20 <= i_A_20; + reg_B_20 <= i_B_20; + reg_A_21 <= i_A_21; + reg_B_21 <= i_B_21; + reg_A_22 <= i_A_22; + reg_B_22 <= i_B_22; + reg_A_23 <= i_A_23; + reg_B_23 <= i_B_23; + reg_A_24 <= i_A_24; + reg_B_24 <= i_B_24; + reg_A_25 <= i_A_25; + reg_B_25 <= i_B_25; + reg_A_26 <= i_A_26; + reg_B_26 <= i_B_26; + reg_A_27 <= i_A_27; + reg_B_27 <= i_B_27; + reg_A_28 <= i_A_28; + reg_B_28 <= i_B_28; + reg_A_29 <= i_A_29; + reg_B_29 <= i_B_29; + reg_A_30 <= i_A_30; + reg_B_30 <= i_B_30; + reg_A_31 <= i_A_31; + reg_B_31 <= i_B_31; + reg_A_32 <= i_A_32; + reg_B_32 <= i_B_32; + reg_A_33 <= i_A_33; + reg_B_33 <= i_B_33; + reg_A_34 <= i_A_34; + reg_B_34 <= i_B_34; + reg_A_35 <= i_A_35; + reg_B_35 <= i_B_35; + reg_A_36 <= i_A_36; + reg_B_36 <= i_B_36; + reg_A_37 <= i_A_37; + reg_B_37 <= i_B_37; + reg_A_38 <= i_A_38; + reg_B_38 <= i_B_38; + reg_A_39 <= i_A_39; + reg_B_39 <= i_B_39; + reg_A_40 <= i_A_40; + reg_B_40 <= i_B_40; + reg_A_41 <= i_A_41; + reg_B_41 <= i_B_41; + reg_A_42 <= i_A_42; + reg_B_42 <= i_B_42; + reg_A_43 <= i_A_43; + reg_B_43 <= i_B_43; + reg_A_44 <= i_A_44; + reg_B_44 <= i_B_44; + reg_A_45 <= i_A_45; + reg_B_45 <= i_B_45; + reg_A_46 <= i_A_46; + reg_B_46 <= i_B_46; + reg_A_47 <= i_A_47; + reg_B_47 <= i_B_47; + valid_A_B <= i_valid; + end +end + +assign o_C_0 = reg_C_0; +assign o_C_1 = reg_C_1; +assign o_C_2 = reg_C_2; +assign o_C_3 = reg_C_3; +assign o_C_4 = reg_C_4; +assign o_C_5 = reg_C_5; +assign o_C_6 = reg_C_6; +assign o_C_7 = reg_C_7; +assign o_C_8 = reg_C_8; +assign o_C_9 = reg_C_9; +assign o_C_10 = reg_C_10; +assign o_C_11 = reg_C_11; +assign o_C_12 = reg_C_12; +assign o_C_13 = reg_C_13; +assign o_C_14 = reg_C_14; +assign o_C_15 = reg_C_15; +assign o_C_16 = reg_C_16; +assign o_C_17 = reg_C_17; +assign o_C_18 = reg_C_18; +assign o_C_19 = reg_C_19; +assign o_C_20 = reg_C_20; +assign o_C_21 = reg_C_21; +assign o_C_22 = reg_C_22; +assign o_C_23 = reg_C_23; +assign o_C_24 = reg_C_24; +assign o_C_25 = reg_C_25; +assign o_C_26 = reg_C_26; +assign o_C_27 = reg_C_27; +assign o_C_28 = reg_C_28; +assign o_C_29 = reg_C_29; +assign o_C_30 = reg_C_30; +assign o_C_31 = reg_C_31; +assign o_C_32 = reg_C_32; +assign o_C_33 = reg_C_33; +assign o_C_34 = reg_C_34; +assign o_C_35 = reg_C_35; +assign o_C_36 = reg_C_36; +assign o_C_37 = reg_C_37; +assign o_C_38 = reg_C_38; +assign o_C_39 = reg_C_39; +assign o_C_40 = reg_C_40; +assign o_C_41 = reg_C_41; +assign o_C_42 = reg_C_42; +assign o_C_43 = reg_C_43; +assign o_C_44 = reg_C_44; +assign o_C_45 = reg_C_45; +assign o_C_46 = reg_C_46; +assign o_C_47 = reg_C_47; +assign valid_C = round_valid_0; +assign o_ready = i_ready; +assign o_valid = valid_C & i_ready; + +endmodule + +module shift_register_group_18_48_18 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input [17:0] in_16, + output [17:0] out_16, + input [17:0] in_17, + output [17:0] out_17, + input [17:0] in_18, + output [17:0] out_18, + input [17:0] in_19, + output [17:0] out_19, + input [17:0] in_20, + output [17:0] out_20, + input [17:0] in_21, + output [17:0] out_21, + input [17:0] in_22, + output [17:0] out_22, + input [17:0] in_23, + output [17:0] out_23, + input [17:0] in_24, + output [17:0] out_24, + input [17:0] in_25, + output [17:0] out_25, + input [17:0] in_26, + output [17:0] out_26, + input [17:0] in_27, + output [17:0] out_27, + input [17:0] in_28, + output [17:0] out_28, + input [17:0] in_29, + output [17:0] out_29, + input [17:0] in_30, + output [17:0] out_30, + input [17:0] in_31, + output [17:0] out_31, + input [17:0] in_32, + output [17:0] out_32, + input [17:0] in_33, + output [17:0] out_33, + input [17:0] in_34, + output [17:0] out_34, + input [17:0] in_35, + output [17:0] out_35, + input [17:0] in_36, + output [17:0] out_36, + input [17:0] in_37, + output [17:0] out_37, + input [17:0] in_38, + output [17:0] out_38, + input [17:0] in_39, + output [17:0] out_39, + input [17:0] in_40, + output [17:0] out_40, + input [17:0] in_41, + output [17:0] out_41, + input [17:0] in_42, + output [17:0] out_42, + input [17:0] in_43, + output [17:0] out_43, + input [17:0] in_44, + output [17:0] out_44, + input [17:0] in_45, + output [17:0] out_45, + input [17:0] in_46, + output [17:0] out_46, + input [17:0] in_47, + output [17:0] out_47, + input reset +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_16 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_16), + .out(out_16) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_17 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_17), + .out(out_17) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_18 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_18), + .out(out_18) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_19 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_19), + .out(out_19) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_20 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_20), + .out(out_20) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_21 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_21), + .out(out_21) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_22 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_22), + .out(out_22) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_23 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_23), + .out(out_23) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_24 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_24), + .out(out_24) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_25 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_25), + .out(out_25) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_26 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_26), + .out(out_26) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_27 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_27), + .out(out_27) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_28 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_28), + .out(out_28) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_29 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_29), + .out(out_29) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_30 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_30), + .out(out_30) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_31 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_31), + .out(out_31) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_32 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_32), + .out(out_32) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_33 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_33), + .out(out_33) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_34 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_34), + .out(out_34) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_35 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_35), + .out(out_35) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_36 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_36), + .out(out_36) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_37 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_37), + .out(out_37) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_38 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_38), + .out(out_38) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_39 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_39), + .out(out_39) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_40 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_40), + .out(out_40) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_41 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_41), + .out(out_41) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_42 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_42), + .out(out_42) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_43 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_43), + .out(out_43) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_44 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_44), + .out(out_44) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_45 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_45), + .out(out_45) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_46 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_46), + .out(out_46) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_47 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_47), + .out(out_47) +); + +endmodule + +module elementwise_add_core_18_18_48 ( + input clk, + input reset, + input i_valid, + input i_ready, + input [17:0] i_A_0, + input [17:0] i_B_0, + output [17:0] o_C_0, + input [17:0] i_A_1, + input [17:0] i_B_1, + output [17:0] o_C_1, + input [17:0] i_A_2, + input [17:0] i_B_2, + output [17:0] o_C_2, + input [17:0] i_A_3, + input [17:0] i_B_3, + output [17:0] o_C_3, + input [17:0] i_A_4, + input [17:0] i_B_4, + output [17:0] o_C_4, + input [17:0] i_A_5, + input [17:0] i_B_5, + output [17:0] o_C_5, + input [17:0] i_A_6, + input [17:0] i_B_6, + output [17:0] o_C_6, + input [17:0] i_A_7, + input [17:0] i_B_7, + output [17:0] o_C_7, + input [17:0] i_A_8, + input [17:0] i_B_8, + output [17:0] o_C_8, + input [17:0] i_A_9, + input [17:0] i_B_9, + output [17:0] o_C_9, + input [17:0] i_A_10, + input [17:0] i_B_10, + output [17:0] o_C_10, + input [17:0] i_A_11, + input [17:0] i_B_11, + output [17:0] o_C_11, + input [17:0] i_A_12, + input [17:0] i_B_12, + output [17:0] o_C_12, + input [17:0] i_A_13, + input [17:0] i_B_13, + output [17:0] o_C_13, + input [17:0] i_A_14, + input [17:0] i_B_14, + output [17:0] o_C_14, + input [17:0] i_A_15, + input [17:0] i_B_15, + output [17:0] o_C_15, + input [17:0] i_A_16, + input [17:0] i_B_16, + output [17:0] o_C_16, + input [17:0] i_A_17, + input [17:0] i_B_17, + output [17:0] o_C_17, + input [17:0] i_A_18, + input [17:0] i_B_18, + output [17:0] o_C_18, + input [17:0] i_A_19, + input [17:0] i_B_19, + output [17:0] o_C_19, + input [17:0] i_A_20, + input [17:0] i_B_20, + output [17:0] o_C_20, + input [17:0] i_A_21, + input [17:0] i_B_21, + output [17:0] o_C_21, + input [17:0] i_A_22, + input [17:0] i_B_22, + output [17:0] o_C_22, + input [17:0] i_A_23, + input [17:0] i_B_23, + output [17:0] o_C_23, + input [17:0] i_A_24, + input [17:0] i_B_24, + output [17:0] o_C_24, + input [17:0] i_A_25, + input [17:0] i_B_25, + output [17:0] o_C_25, + input [17:0] i_A_26, + input [17:0] i_B_26, + output [17:0] o_C_26, + input [17:0] i_A_27, + input [17:0] i_B_27, + output [17:0] o_C_27, + input [17:0] i_A_28, + input [17:0] i_B_28, + output [17:0] o_C_28, + input [17:0] i_A_29, + input [17:0] i_B_29, + output [17:0] o_C_29, + input [17:0] i_A_30, + input [17:0] i_B_30, + output [17:0] o_C_30, + input [17:0] i_A_31, + input [17:0] i_B_31, + output [17:0] o_C_31, + input [17:0] i_A_32, + input [17:0] i_B_32, + output [17:0] o_C_32, + input [17:0] i_A_33, + input [17:0] i_B_33, + output [17:0] o_C_33, + input [17:0] i_A_34, + input [17:0] i_B_34, + output [17:0] o_C_34, + input [17:0] i_A_35, + input [17:0] i_B_35, + output [17:0] o_C_35, + input [17:0] i_A_36, + input [17:0] i_B_36, + output [17:0] o_C_36, + input [17:0] i_A_37, + input [17:0] i_B_37, + output [17:0] o_C_37, + input [17:0] i_A_38, + input [17:0] i_B_38, + output [17:0] o_C_38, + input [17:0] i_A_39, + input [17:0] i_B_39, + output [17:0] o_C_39, + input [17:0] i_A_40, + input [17:0] i_B_40, + output [17:0] o_C_40, + input [17:0] i_A_41, + input [17:0] i_B_41, + output [17:0] o_C_41, + input [17:0] i_A_42, + input [17:0] i_B_42, + output [17:0] o_C_42, + input [17:0] i_A_43, + input [17:0] i_B_43, + output [17:0] o_C_43, + input [17:0] i_A_44, + input [17:0] i_B_44, + output [17:0] o_C_44, + input [17:0] i_A_45, + input [17:0] i_B_45, + output [17:0] o_C_45, + input [17:0] i_A_46, + input [17:0] i_B_46, + output [17:0] o_C_46, + input [17:0] i_A_47, + input [17:0] i_B_47, + output [17:0] o_C_47, + output o_valid, + output o_ready +); + +reg [17:0] reg_A_0; +reg [17:0] reg_B_0; +reg [17:0] reg_C_0; +reg [17:0] reg_A_1; +reg [17:0] reg_B_1; +reg [17:0] reg_C_1; +reg [17:0] reg_A_2; +reg [17:0] reg_B_2; +reg [17:0] reg_C_2; +reg [17:0] reg_A_3; +reg [17:0] reg_B_3; +reg [17:0] reg_C_3; +reg [17:0] reg_A_4; +reg [17:0] reg_B_4; +reg [17:0] reg_C_4; +reg [17:0] reg_A_5; +reg [17:0] reg_B_5; +reg [17:0] reg_C_5; +reg [17:0] reg_A_6; +reg [17:0] reg_B_6; +reg [17:0] reg_C_6; +reg [17:0] reg_A_7; +reg [17:0] reg_B_7; +reg [17:0] reg_C_7; +reg [17:0] reg_A_8; +reg [17:0] reg_B_8; +reg [17:0] reg_C_8; +reg [17:0] reg_A_9; +reg [17:0] reg_B_9; +reg [17:0] reg_C_9; +reg [17:0] reg_A_10; +reg [17:0] reg_B_10; +reg [17:0] reg_C_10; +reg [17:0] reg_A_11; +reg [17:0] reg_B_11; +reg [17:0] reg_C_11; +reg [17:0] reg_A_12; +reg [17:0] reg_B_12; +reg [17:0] reg_C_12; +reg [17:0] reg_A_13; +reg [17:0] reg_B_13; +reg [17:0] reg_C_13; +reg [17:0] reg_A_14; +reg [17:0] reg_B_14; +reg [17:0] reg_C_14; +reg [17:0] reg_A_15; +reg [17:0] reg_B_15; +reg [17:0] reg_C_15; +reg [17:0] reg_A_16; +reg [17:0] reg_B_16; +reg [17:0] reg_C_16; +reg [17:0] reg_A_17; +reg [17:0] reg_B_17; +reg [17:0] reg_C_17; +reg [17:0] reg_A_18; +reg [17:0] reg_B_18; +reg [17:0] reg_C_18; +reg [17:0] reg_A_19; +reg [17:0] reg_B_19; +reg [17:0] reg_C_19; +reg [17:0] reg_A_20; +reg [17:0] reg_B_20; +reg [17:0] reg_C_20; +reg [17:0] reg_A_21; +reg [17:0] reg_B_21; +reg [17:0] reg_C_21; +reg [17:0] reg_A_22; +reg [17:0] reg_B_22; +reg [17:0] reg_C_22; +reg [17:0] reg_A_23; +reg [17:0] reg_B_23; +reg [17:0] reg_C_23; +reg [17:0] reg_A_24; +reg [17:0] reg_B_24; +reg [17:0] reg_C_24; +reg [17:0] reg_A_25; +reg [17:0] reg_B_25; +reg [17:0] reg_C_25; +reg [17:0] reg_A_26; +reg [17:0] reg_B_26; +reg [17:0] reg_C_26; +reg [17:0] reg_A_27; +reg [17:0] reg_B_27; +reg [17:0] reg_C_27; +reg [17:0] reg_A_28; +reg [17:0] reg_B_28; +reg [17:0] reg_C_28; +reg [17:0] reg_A_29; +reg [17:0] reg_B_29; +reg [17:0] reg_C_29; +reg [17:0] reg_A_30; +reg [17:0] reg_B_30; +reg [17:0] reg_C_30; +reg [17:0] reg_A_31; +reg [17:0] reg_B_31; +reg [17:0] reg_C_31; +reg [17:0] reg_A_32; +reg [17:0] reg_B_32; +reg [17:0] reg_C_32; +reg [17:0] reg_A_33; +reg [17:0] reg_B_33; +reg [17:0] reg_C_33; +reg [17:0] reg_A_34; +reg [17:0] reg_B_34; +reg [17:0] reg_C_34; +reg [17:0] reg_A_35; +reg [17:0] reg_B_35; +reg [17:0] reg_C_35; +reg [17:0] reg_A_36; +reg [17:0] reg_B_36; +reg [17:0] reg_C_36; +reg [17:0] reg_A_37; +reg [17:0] reg_B_37; +reg [17:0] reg_C_37; +reg [17:0] reg_A_38; +reg [17:0] reg_B_38; +reg [17:0] reg_C_38; +reg [17:0] reg_A_39; +reg [17:0] reg_B_39; +reg [17:0] reg_C_39; +reg [17:0] reg_A_40; +reg [17:0] reg_B_40; +reg [17:0] reg_C_40; +reg [17:0] reg_A_41; +reg [17:0] reg_B_41; +reg [17:0] reg_C_41; +reg [17:0] reg_A_42; +reg [17:0] reg_B_42; +reg [17:0] reg_C_42; +reg [17:0] reg_A_43; +reg [17:0] reg_B_43; +reg [17:0] reg_C_43; +reg [17:0] reg_A_44; +reg [17:0] reg_B_44; +reg [17:0] reg_C_44; +reg [17:0] reg_A_45; +reg [17:0] reg_B_45; +reg [17:0] reg_C_45; +reg [17:0] reg_A_46; +reg [17:0] reg_B_46; +reg [17:0] reg_C_46; +reg [17:0] reg_A_47; +reg [17:0] reg_B_47; +reg [17:0] reg_C_47; + +reg valid_A_B, valid_C; +wire enable; +assign enable = i_ready; + +always @ (posedge clk) begin + if (reset) begin + valid_A_B <= 1'b0; + valid_C <= 1'b0; + reg_A_0 <= 0; + reg_B_0 <= 0; + reg_C_0 <= 0; + reg_A_1 <= 0; + reg_B_1 <= 0; + reg_C_1 <= 0; + reg_A_2 <= 0; + reg_B_2 <= 0; + reg_C_2 <= 0; + reg_A_3 <= 0; + reg_B_3 <= 0; + reg_C_3 <= 0; + reg_A_4 <= 0; + reg_B_4 <= 0; + reg_C_4 <= 0; + reg_A_5 <= 0; + reg_B_5 <= 0; + reg_C_5 <= 0; + reg_A_6 <= 0; + reg_B_6 <= 0; + reg_C_6 <= 0; + reg_A_7 <= 0; + reg_B_7 <= 0; + reg_C_7 <= 0; + reg_A_8 <= 0; + reg_B_8 <= 0; + reg_C_8 <= 0; + reg_A_9 <= 0; + reg_B_9 <= 0; + reg_C_9 <= 0; + reg_A_10 <= 0; + reg_B_10 <= 0; + reg_C_10 <= 0; + reg_A_11 <= 0; + reg_B_11 <= 0; + reg_C_11 <= 0; + reg_A_12 <= 0; + reg_B_12 <= 0; + reg_C_12 <= 0; + reg_A_13 <= 0; + reg_B_13 <= 0; + reg_C_13 <= 0; + reg_A_14 <= 0; + reg_B_14 <= 0; + reg_C_14 <= 0; + reg_A_15 <= 0; + reg_B_15 <= 0; + reg_C_15 <= 0; + reg_A_16 <= 0; + reg_B_16 <= 0; + reg_C_16 <= 0; + reg_A_17 <= 0; + reg_B_17 <= 0; + reg_C_17 <= 0; + reg_A_18 <= 0; + reg_B_18 <= 0; + reg_C_18 <= 0; + reg_A_19 <= 0; + reg_B_19 <= 0; + reg_C_19 <= 0; + reg_A_20 <= 0; + reg_B_20 <= 0; + reg_C_20 <= 0; + reg_A_21 <= 0; + reg_B_21 <= 0; + reg_C_21 <= 0; + reg_A_22 <= 0; + reg_B_22 <= 0; + reg_C_22 <= 0; + reg_A_23 <= 0; + reg_B_23 <= 0; + reg_C_23 <= 0; + reg_A_24 <= 0; + reg_B_24 <= 0; + reg_C_24 <= 0; + reg_A_25 <= 0; + reg_B_25 <= 0; + reg_C_25 <= 0; + reg_A_26 <= 0; + reg_B_26 <= 0; + reg_C_26 <= 0; + reg_A_27 <= 0; + reg_B_27 <= 0; + reg_C_27 <= 0; + reg_A_28 <= 0; + reg_B_28 <= 0; + reg_C_28 <= 0; + reg_A_29 <= 0; + reg_B_29 <= 0; + reg_C_29 <= 0; + reg_A_30 <= 0; + reg_B_30 <= 0; + reg_C_30 <= 0; + reg_A_31 <= 0; + reg_B_31 <= 0; + reg_C_31 <= 0; + reg_A_32 <= 0; + reg_B_32 <= 0; + reg_C_32 <= 0; + reg_A_33 <= 0; + reg_B_33 <= 0; + reg_C_33 <= 0; + reg_A_34 <= 0; + reg_B_34 <= 0; + reg_C_34 <= 0; + reg_A_35 <= 0; + reg_B_35 <= 0; + reg_C_35 <= 0; + reg_A_36 <= 0; + reg_B_36 <= 0; + reg_C_36 <= 0; + reg_A_37 <= 0; + reg_B_37 <= 0; + reg_C_37 <= 0; + reg_A_38 <= 0; + reg_B_38 <= 0; + reg_C_38 <= 0; + reg_A_39 <= 0; + reg_B_39 <= 0; + reg_C_39 <= 0; + reg_A_40 <= 0; + reg_B_40 <= 0; + reg_C_40 <= 0; + reg_A_41 <= 0; + reg_B_41 <= 0; + reg_C_41 <= 0; + reg_A_42 <= 0; + reg_B_42 <= 0; + reg_C_42 <= 0; + reg_A_43 <= 0; + reg_B_43 <= 0; + reg_C_43 <= 0; + reg_A_44 <= 0; + reg_B_44 <= 0; + reg_C_44 <= 0; + reg_A_45 <= 0; + reg_B_45 <= 0; + reg_C_45 <= 0; + reg_A_46 <= 0; + reg_B_46 <= 0; + reg_C_46 <= 0; + reg_A_47 <= 0; + reg_B_47 <= 0; + reg_C_47 <= 0; + end else if (enable) begin + reg_A_0 <= i_A_0; + reg_B_0 <= i_B_0; + reg_C_0 <= reg_A_0 + reg_B_0; + reg_A_1 <= i_A_1; + reg_B_1 <= i_B_1; + reg_C_1 <= reg_A_1 + reg_B_1; + reg_A_2 <= i_A_2; + reg_B_2 <= i_B_2; + reg_C_2 <= reg_A_2 + reg_B_2; + reg_A_3 <= i_A_3; + reg_B_3 <= i_B_3; + reg_C_3 <= reg_A_3 + reg_B_3; + reg_A_4 <= i_A_4; + reg_B_4 <= i_B_4; + reg_C_4 <= reg_A_4 + reg_B_4; + reg_A_5 <= i_A_5; + reg_B_5 <= i_B_5; + reg_C_5 <= reg_A_5 + reg_B_5; + reg_A_6 <= i_A_6; + reg_B_6 <= i_B_6; + reg_C_6 <= reg_A_6 + reg_B_6; + reg_A_7 <= i_A_7; + reg_B_7 <= i_B_7; + reg_C_7 <= reg_A_7 + reg_B_7; + reg_A_8 <= i_A_8; + reg_B_8 <= i_B_8; + reg_C_8 <= reg_A_8 + reg_B_8; + reg_A_9 <= i_A_9; + reg_B_9 <= i_B_9; + reg_C_9 <= reg_A_9 + reg_B_9; + reg_A_10 <= i_A_10; + reg_B_10 <= i_B_10; + reg_C_10 <= reg_A_10 + reg_B_10; + reg_A_11 <= i_A_11; + reg_B_11 <= i_B_11; + reg_C_11 <= reg_A_11 + reg_B_11; + reg_A_12 <= i_A_12; + reg_B_12 <= i_B_12; + reg_C_12 <= reg_A_12 + reg_B_12; + reg_A_13 <= i_A_13; + reg_B_13 <= i_B_13; + reg_C_13 <= reg_A_13 + reg_B_13; + reg_A_14 <= i_A_14; + reg_B_14 <= i_B_14; + reg_C_14 <= reg_A_14 + reg_B_14; + reg_A_15 <= i_A_15; + reg_B_15 <= i_B_15; + reg_C_15 <= reg_A_15 + reg_B_15; + reg_A_16 <= i_A_16; + reg_B_16 <= i_B_16; + reg_C_16 <= reg_A_16 + reg_B_16; + reg_A_17 <= i_A_17; + reg_B_17 <= i_B_17; + reg_C_17 <= reg_A_17 + reg_B_17; + reg_A_18 <= i_A_18; + reg_B_18 <= i_B_18; + reg_C_18 <= reg_A_18 + reg_B_18; + reg_A_19 <= i_A_19; + reg_B_19 <= i_B_19; + reg_C_19 <= reg_A_19 + reg_B_19; + reg_A_20 <= i_A_20; + reg_B_20 <= i_B_20; + reg_C_20 <= reg_A_20 + reg_B_20; + reg_A_21 <= i_A_21; + reg_B_21 <= i_B_21; + reg_C_21 <= reg_A_21 + reg_B_21; + reg_A_22 <= i_A_22; + reg_B_22 <= i_B_22; + reg_C_22 <= reg_A_22 + reg_B_22; + reg_A_23 <= i_A_23; + reg_B_23 <= i_B_23; + reg_C_23 <= reg_A_23 + reg_B_23; + reg_A_24 <= i_A_24; + reg_B_24 <= i_B_24; + reg_C_24 <= reg_A_24 + reg_B_24; + reg_A_25 <= i_A_25; + reg_B_25 <= i_B_25; + reg_C_25 <= reg_A_25 + reg_B_25; + reg_A_26 <= i_A_26; + reg_B_26 <= i_B_26; + reg_C_26 <= reg_A_26 + reg_B_26; + reg_A_27 <= i_A_27; + reg_B_27 <= i_B_27; + reg_C_27 <= reg_A_27 + reg_B_27; + reg_A_28 <= i_A_28; + reg_B_28 <= i_B_28; + reg_C_28 <= reg_A_28 + reg_B_28; + reg_A_29 <= i_A_29; + reg_B_29 <= i_B_29; + reg_C_29 <= reg_A_29 + reg_B_29; + reg_A_30 <= i_A_30; + reg_B_30 <= i_B_30; + reg_C_30 <= reg_A_30 + reg_B_30; + reg_A_31 <= i_A_31; + reg_B_31 <= i_B_31; + reg_C_31 <= reg_A_31 + reg_B_31; + reg_A_32 <= i_A_32; + reg_B_32 <= i_B_32; + reg_C_32 <= reg_A_32 + reg_B_32; + reg_A_33 <= i_A_33; + reg_B_33 <= i_B_33; + reg_C_33 <= reg_A_33 + reg_B_33; + reg_A_34 <= i_A_34; + reg_B_34 <= i_B_34; + reg_C_34 <= reg_A_34 + reg_B_34; + reg_A_35 <= i_A_35; + reg_B_35 <= i_B_35; + reg_C_35 <= reg_A_35 + reg_B_35; + reg_A_36 <= i_A_36; + reg_B_36 <= i_B_36; + reg_C_36 <= reg_A_36 + reg_B_36; + reg_A_37 <= i_A_37; + reg_B_37 <= i_B_37; + reg_C_37 <= reg_A_37 + reg_B_37; + reg_A_38 <= i_A_38; + reg_B_38 <= i_B_38; + reg_C_38 <= reg_A_38 + reg_B_38; + reg_A_39 <= i_A_39; + reg_B_39 <= i_B_39; + reg_C_39 <= reg_A_39 + reg_B_39; + reg_A_40 <= i_A_40; + reg_B_40 <= i_B_40; + reg_C_40 <= reg_A_40 + reg_B_40; + reg_A_41 <= i_A_41; + reg_B_41 <= i_B_41; + reg_C_41 <= reg_A_41 + reg_B_41; + reg_A_42 <= i_A_42; + reg_B_42 <= i_B_42; + reg_C_42 <= reg_A_42 + reg_B_42; + reg_A_43 <= i_A_43; + reg_B_43 <= i_B_43; + reg_C_43 <= reg_A_43 + reg_B_43; + reg_A_44 <= i_A_44; + reg_B_44 <= i_B_44; + reg_C_44 <= reg_A_44 + reg_B_44; + reg_A_45 <= i_A_45; + reg_B_45 <= i_B_45; + reg_C_45 <= reg_A_45 + reg_B_45; + reg_A_46 <= i_A_46; + reg_B_46 <= i_B_46; + reg_C_46 <= reg_A_46 + reg_B_46; + reg_A_47 <= i_A_47; + reg_B_47 <= i_B_47; + reg_C_47 <= reg_A_47 + reg_B_47; + valid_A_B <= i_valid; + valid_C <= valid_A_B; + end +end + +assign o_C_0 = reg_C_0; +assign o_C_1 = reg_C_1; +assign o_C_2 = reg_C_2; +assign o_C_3 = reg_C_3; +assign o_C_4 = reg_C_4; +assign o_C_5 = reg_C_5; +assign o_C_6 = reg_C_6; +assign o_C_7 = reg_C_7; +assign o_C_8 = reg_C_8; +assign o_C_9 = reg_C_9; +assign o_C_10 = reg_C_10; +assign o_C_11 = reg_C_11; +assign o_C_12 = reg_C_12; +assign o_C_13 = reg_C_13; +assign o_C_14 = reg_C_14; +assign o_C_15 = reg_C_15; +assign o_C_16 = reg_C_16; +assign o_C_17 = reg_C_17; +assign o_C_18 = reg_C_18; +assign o_C_19 = reg_C_19; +assign o_C_20 = reg_C_20; +assign o_C_21 = reg_C_21; +assign o_C_22 = reg_C_22; +assign o_C_23 = reg_C_23; +assign o_C_24 = reg_C_24; +assign o_C_25 = reg_C_25; +assign o_C_26 = reg_C_26; +assign o_C_27 = reg_C_27; +assign o_C_28 = reg_C_28; +assign o_C_29 = reg_C_29; +assign o_C_30 = reg_C_30; +assign o_C_31 = reg_C_31; +assign o_C_32 = reg_C_32; +assign o_C_33 = reg_C_33; +assign o_C_34 = reg_C_34; +assign o_C_35 = reg_C_35; +assign o_C_36 = reg_C_36; +assign o_C_37 = reg_C_37; +assign o_C_38 = reg_C_38; +assign o_C_39 = reg_C_39; +assign o_C_40 = reg_C_40; +assign o_C_41 = reg_C_41; +assign o_C_42 = reg_C_42; +assign o_C_43 = reg_C_43; +assign o_C_44 = reg_C_44; +assign o_C_45 = reg_C_45; +assign o_C_46 = reg_C_46; +assign o_C_47 = reg_C_47; +assign o_ready = i_ready; +assign o_valid = valid_C & i_ready; + +endmodule + +module shift_register_group_18_48_14 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input [17:0] in_16, + output [17:0] out_16, + input [17:0] in_17, + output [17:0] out_17, + input [17:0] in_18, + output [17:0] out_18, + input [17:0] in_19, + output [17:0] out_19, + input [17:0] in_20, + output [17:0] out_20, + input [17:0] in_21, + output [17:0] out_21, + input [17:0] in_22, + output [17:0] out_22, + input [17:0] in_23, + output [17:0] out_23, + input [17:0] in_24, + output [17:0] out_24, + input [17:0] in_25, + output [17:0] out_25, + input [17:0] in_26, + output [17:0] out_26, + input [17:0] in_27, + output [17:0] out_27, + input [17:0] in_28, + output [17:0] out_28, + input [17:0] in_29, + output [17:0] out_29, + input [17:0] in_30, + output [17:0] out_30, + input [17:0] in_31, + output [17:0] out_31, + input [17:0] in_32, + output [17:0] out_32, + input [17:0] in_33, + output [17:0] out_33, + input [17:0] in_34, + output [17:0] out_34, + input [17:0] in_35, + output [17:0] out_35, + input [17:0] in_36, + output [17:0] out_36, + input [17:0] in_37, + output [17:0] out_37, + input [17:0] in_38, + output [17:0] out_38, + input [17:0] in_39, + output [17:0] out_39, + input [17:0] in_40, + output [17:0] out_40, + input [17:0] in_41, + output [17:0] out_41, + input [17:0] in_42, + output [17:0] out_42, + input [17:0] in_43, + output [17:0] out_43, + input [17:0] in_44, + output [17:0] out_44, + input [17:0] in_45, + output [17:0] out_45, + input [17:0] in_46, + output [17:0] out_46, + input [17:0] in_47, + output [17:0] out_47, + input reset +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_16 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_16), + .out(out_16) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_17 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_17), + .out(out_17) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_18 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_18), + .out(out_18) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_19 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_19), + .out(out_19) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_20 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_20), + .out(out_20) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_21 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_21), + .out(out_21) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_22 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_22), + .out(out_22) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_23 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_23), + .out(out_23) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_24 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_24), + .out(out_24) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_25 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_25), + .out(out_25) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_26 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_26), + .out(out_26) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_27 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_27), + .out(out_27) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_28 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_28), + .out(out_28) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_29 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_29), + .out(out_29) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_30 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_30), + .out(out_30) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_31 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_31), + .out(out_31) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_32 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_32), + .out(out_32) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_33 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_33), + .out(out_33) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_34 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_34), + .out(out_34) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_35 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_35), + .out(out_35) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_36 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_36), + .out(out_36) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_37 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_37), + .out(out_37) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_38 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_38), + .out(out_38) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_39 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_39), + .out(out_39) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_40 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_40), + .out(out_40) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_41 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_41), + .out(out_41) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_42 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_42), + .out(out_42) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_43 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_43), + .out(out_43) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_44 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_44), + .out(out_44) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_45 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_45), + .out(out_45) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_46 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_46), + .out(out_46) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_47 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_47), + .out(out_47) +); + +endmodule + +module shift_register_unit_18_14 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +reg [17:0] shift_registers_1; +reg [17:0] shift_registers_2; +reg [17:0] shift_registers_3; +reg [17:0] shift_registers_4; +reg [17:0] shift_registers_5; +reg [17:0] shift_registers_6; +reg [17:0] shift_registers_7; +reg [17:0] shift_registers_8; +reg [17:0] shift_registers_9; +reg [17:0] shift_registers_10; +reg [17:0] shift_registers_11; +reg [17:0] shift_registers_12; +reg [17:0] shift_registers_13; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + shift_registers_1 <= 18'd0; + shift_registers_2 <= 18'd0; + shift_registers_3 <= 18'd0; + shift_registers_4 <= 18'd0; + shift_registers_5 <= 18'd0; + shift_registers_6 <= 18'd0; + shift_registers_7 <= 18'd0; + shift_registers_8 <= 18'd0; + shift_registers_9 <= 18'd0; + shift_registers_10 <= 18'd0; + shift_registers_11 <= 18'd0; + shift_registers_12 <= 18'd0; + shift_registers_13 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + shift_registers_3 <= shift_registers_2; + shift_registers_4 <= shift_registers_3; + shift_registers_5 <= shift_registers_4; + shift_registers_6 <= shift_registers_5; + shift_registers_7 <= shift_registers_6; + shift_registers_8 <= shift_registers_7; + shift_registers_9 <= shift_registers_8; + shift_registers_10 <= shift_registers_9; + shift_registers_11 <= shift_registers_10; + shift_registers_12 <= shift_registers_11; + shift_registers_13 <= shift_registers_12; + end +end + +assign out = shift_registers_13; + +endmodule + +module tanh_core_18_18_10_32_1 ( + input clk, + input reset, + input i_valid, + input i_ready, + output o_ready, + output o_valid, + input [17:0] i_x, + output [17:0] o_y +); + +reg [12:0] k_list_0; +reg [12:0] b_list_0; +reg [12:0] k_list_1; +reg [12:0] b_list_1; +reg [12:0] k_list_2; +reg [12:0] b_list_2; +reg [12:0] k_list_3; +reg [12:0] b_list_3; +reg [12:0] k_list_4; +reg [12:0] b_list_4; +reg [12:0] k_list_5; +reg [12:0] b_list_5; +reg [12:0] k_list_6; +reg [12:0] b_list_6; +reg [12:0] k_list_7; +reg [12:0] b_list_7; +reg [12:0] k_list_8; +reg [12:0] b_list_8; +reg [12:0] k_list_9; +reg [12:0] b_list_9; +reg [12:0] k_list_10; +reg [12:0] b_list_10; +reg [12:0] k_list_11; +reg [12:0] b_list_11; +reg [12:0] k_list_12; +reg [12:0] b_list_12; +reg [12:0] k_list_13; +reg [12:0] b_list_13; +reg [12:0] k_list_14; +reg [12:0] b_list_14; +reg [12:0] k_list_15; +reg [12:0] b_list_15; +reg [12:0] k_list_16; +reg [12:0] b_list_16; +reg [12:0] k_list_17; +reg [12:0] b_list_17; +reg [12:0] k_list_18; +reg [12:0] b_list_18; +reg [12:0] k_list_19; +reg [12:0] b_list_19; +reg [12:0] k_list_20; +reg [12:0] b_list_20; +reg [12:0] k_list_21; +reg [12:0] b_list_21; +reg [12:0] k_list_22; +reg [12:0] b_list_22; +reg [12:0] k_list_23; +reg [12:0] b_list_23; +reg [12:0] k_list_24; +reg [12:0] b_list_24; +reg [12:0] k_list_25; +reg [12:0] b_list_25; +reg [12:0] k_list_26; +reg [12:0] b_list_26; +reg [12:0] k_list_27; +reg [12:0] b_list_27; +reg [12:0] k_list_28; +reg [12:0] b_list_28; +reg [12:0] k_list_29; +reg [12:0] b_list_29; +reg [12:0] k_list_30; +reg [12:0] b_list_30; +reg [12:0] k_list_31; +reg [12:0] b_list_31; + +always @ (posedge clk) begin + k_list_0 <= 13'b0011111110101; + k_list_1 <= 13'b0011110110111; + k_list_2 <= 13'b0011101000011; + k_list_3 <= 13'b0011010100100; + k_list_4 <= 13'b0010111101011; + k_list_5 <= 13'b0010100101000; + k_list_6 <= 13'b0010001100111; + k_list_7 <= 13'b0001110110001; + k_list_8 <= 13'b0001100001110; + k_list_9 <= 13'b0001001111111; + k_list_10 <= 13'b0001000000101; + k_list_11 <= 13'b0000110011111; + k_list_12 <= 13'b0000101001011; + k_list_13 <= 13'b0000100000111; + k_list_14 <= 13'b0000011010000; + k_list_15 <= 13'b0000010100100; + k_list_16 <= 13'b0000010000001; + k_list_17 <= 13'b0000001100101; + k_list_18 <= 13'b0000001001111; + k_list_19 <= 13'b0000000111110; + k_list_20 <= 13'b0000000110000; + k_list_21 <= 13'b0000000100110; + k_list_22 <= 13'b0000000011101; + k_list_23 <= 13'b0000000010111; + k_list_24 <= 13'b0000000010010; + k_list_25 <= 13'b0000000001110; + k_list_26 <= 13'b0000000001011; + k_list_27 <= 13'b0000000001000; + k_list_28 <= 13'b0000000000111; + k_list_29 <= 13'b0000000000101; + k_list_30 <= 13'b0000000000100; + k_list_31 <= 13'b0000000000011; + b_list_0 <= 13'b0000000000000; + b_list_1 <= 13'b0000000001000; + b_list_2 <= 13'b0000000100101; + b_list_3 <= 13'b0000001100000; + b_list_4 <= 13'b0000010111101; + b_list_5 <= 13'b0000100110111; + b_list_6 <= 13'b0000111001000; + b_list_7 <= 13'b0001001100111; + b_list_8 <= 13'b0001100001010; + b_list_9 <= 13'b0001110101011; + b_list_10 <= 13'b0010001000011; + b_list_11 <= 13'b0010011001111; + b_list_12 <= 13'b0010101001101; + b_list_13 <= 13'b0010110111100; + b_list_14 <= 13'b0011000011101; + b_list_15 <= 13'b0011001101111; + b_list_16 <= 13'b0011010110101; + b_list_17 <= 13'b0011011110000; + b_list_18 <= 13'b0011100100001; + b_list_19 <= 13'b0011101001010; + b_list_20 <= 13'b0011101101100; + b_list_21 <= 13'b0011110001000; + b_list_22 <= 13'b0011110011110; + b_list_23 <= 13'b0011110110001; + b_list_24 <= 13'b0011111000000; + b_list_25 <= 13'b0011111001101; + b_list_26 <= 13'b0011111010111; + b_list_27 <= 13'b0011111011111; + b_list_28 <= 13'b0011111100101; + b_list_29 <= 13'b0011111101010; + b_list_30 <= 13'b0011111101111; + b_list_31 <= 13'b0011111110010; +end +reg [17:0] x; +reg [17:0] y; +reg valid_x, valid_y, enable; +wire [4:0] sel_k_b; + +wire abs_valid, round_valid, mult_valid, compute_valid; +reg [12:0] mac_ay, mac_az; +reg is_x_negative; +wire is_x_negative_hold; +wire [17:0] abs_x; +wire [17:0] x_partial; +reg [31:0] y_compute; +wire [31:0] x_k_plus_b; +wire [31:0] y_rounded; + +assign x_partial = (abs_x >> 7); +assign sel_k_b = x_partial [4:0]; + +reg [12:0] selected_k, selected_b; +always @ (*) begin + if (sel_k_b == 0) begin + selected_k <= k_list_0; + selected_b <= b_list_0; + end else if (sel_k_b == 1) begin + selected_k <= k_list_1; + selected_b <= b_list_1; + end else if (sel_k_b == 2) begin + selected_k <= k_list_2; + selected_b <= b_list_2; + end else if (sel_k_b == 3) begin + selected_k <= k_list_3; + selected_b <= b_list_3; + end else if (sel_k_b == 4) begin + selected_k <= k_list_4; + selected_b <= b_list_4; + end else if (sel_k_b == 5) begin + selected_k <= k_list_5; + selected_b <= b_list_5; + end else if (sel_k_b == 6) begin + selected_k <= k_list_6; + selected_b <= b_list_6; + end else if (sel_k_b == 7) begin + selected_k <= k_list_7; + selected_b <= b_list_7; + end else if (sel_k_b == 8) begin + selected_k <= k_list_8; + selected_b <= b_list_8; + end else if (sel_k_b == 9) begin + selected_k <= k_list_9; + selected_b <= b_list_9; + end else if (sel_k_b == 10) begin + selected_k <= k_list_10; + selected_b <= b_list_10; + end else if (sel_k_b == 11) begin + selected_k <= k_list_11; + selected_b <= b_list_11; + end else if (sel_k_b == 12) begin + selected_k <= k_list_12; + selected_b <= b_list_12; + end else if (sel_k_b == 13) begin + selected_k <= k_list_13; + selected_b <= b_list_13; + end else if (sel_k_b == 14) begin + selected_k <= k_list_14; + selected_b <= b_list_14; + end else if (sel_k_b == 15) begin + selected_k <= k_list_15; + selected_b <= b_list_15; + end else if (sel_k_b == 16) begin + selected_k <= k_list_16; + selected_b <= b_list_16; + end else if (sel_k_b == 17) begin + selected_k <= k_list_17; + selected_b <= b_list_17; + end else if (sel_k_b == 18) begin + selected_k <= k_list_18; + selected_b <= b_list_18; + end else if (sel_k_b == 19) begin + selected_k <= k_list_19; + selected_b <= b_list_19; + end else if (sel_k_b == 20) begin + selected_k <= k_list_20; + selected_b <= b_list_20; + end else if (sel_k_b == 21) begin + selected_k <= k_list_21; + selected_b <= b_list_21; + end else if (sel_k_b == 22) begin + selected_k <= k_list_22; + selected_b <= b_list_22; + end else if (sel_k_b == 23) begin + selected_k <= k_list_23; + selected_b <= b_list_23; + end else if (sel_k_b == 24) begin + selected_k <= k_list_24; + selected_b <= b_list_24; + end else if (sel_k_b == 25) begin + selected_k <= k_list_25; + selected_b <= b_list_25; + end else if (sel_k_b == 26) begin + selected_k <= k_list_26; + selected_b <= b_list_26; + end else if (sel_k_b == 27) begin + selected_k <= k_list_27; + selected_b <= b_list_27; + end else if (sel_k_b == 28) begin + selected_k <= k_list_28; + selected_b <= b_list_28; + end else if (sel_k_b == 29) begin + selected_k <= k_list_29; + selected_b <= b_list_29; + end else if (sel_k_b == 30) begin + selected_k <= k_list_30; + selected_b <= b_list_30; + end else begin + selected_k <= k_list_31; + selected_b <= b_list_31; + end +end +always @ (*) begin + if (abs_x >= 4096) begin + mac_ay <= 0; + mac_az <= 12'd2048; + end else begin + mac_ay <= selected_k; + mac_az <= (selected_b << 10); + end +end +dsp_signed_mac_18_13_23_32 dsp_signed_mac_18_13_23_32_inst_wbotclxiuu ( + .clk(clk), + .reset(reset), + .ena(enable), + .ax(abs_x), + .ay(mac_ay), + .az(mac_az), + .i_valid(abs_valid), + .o_valid(compute_valid), + .resulta(x_k_plus_b) +); + +shift_register_unit_1_3 shift_register_unit_1_3_inst_lqptbjqopf ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(is_x_negative), + .out(is_x_negative_hold) +); + +abs_unit_18 abs_unit_18_inst_kcspttsdbs ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(valid_x), + .in(x), + .o_valid(abs_valid), + .out(abs_x) +); + +fp_rounding_unit_1_32_11 fp_rounding_unit_1_32_11_inst_ncpzmvqarv ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(compute_valid), + .in(y_compute), + .o_valid(round_valid), + .out(y_rounded) +); + +always @ (*) begin + if (is_x_negative_hold) + y_compute = 2048 - x_k_plus_b; + else + y_compute = x_k_plus_b; + enable = i_ready; +end +always @ (posedge clk) begin + if (reset) begin + valid_x <= 1'b0; + valid_y <= 1'b0; + x <= 0; + y <= 0; + end else if (enable) begin + valid_x <= i_valid; + valid_y <= round_valid; + x <= i_x; + if (x[17] == 1'b1) + is_x_negative <= 1'b1; + else + is_x_negative <= 1'b0; + y <= y_rounded[17:0]; + end +end + +assign o_y = y; +assign o_ready = i_ready; +assign o_valid = valid_y & i_ready; + +endmodule + +module pipelined_input_18_3_16 ( + input clk, + input reset, + input enable, + input load_input, + input [17:0] i_data_0_0, + input [17:0] i_data_0_1, + input [17:0] i_data_0_2, + input [17:0] i_data_0_3, + input [17:0] i_data_0_4, + input [17:0] i_data_0_5, + input [17:0] i_data_0_6, + input [17:0] i_data_0_7, + input [17:0] i_data_0_8, + input [17:0] i_data_0_9, + input [17:0] i_data_0_10, + input [17:0] i_data_0_11, + input [17:0] i_data_0_12, + input [17:0] i_data_0_13, + input [17:0] i_data_0_14, + input [17:0] i_data_0_15, + input [17:0] i_data_1_0, + input [17:0] i_data_1_1, + input [17:0] i_data_1_2, + input [17:0] i_data_1_3, + input [17:0] i_data_1_4, + input [17:0] i_data_1_5, + input [17:0] i_data_1_6, + input [17:0] i_data_1_7, + input [17:0] i_data_1_8, + input [17:0] i_data_1_9, + input [17:0] i_data_1_10, + input [17:0] i_data_1_11, + input [17:0] i_data_1_12, + input [17:0] i_data_1_13, + input [17:0] i_data_1_14, + input [17:0] i_data_1_15, + input [17:0] i_data_2_0, + input [17:0] i_data_2_1, + input [17:0] i_data_2_2, + input [17:0] i_data_2_3, + input [17:0] i_data_2_4, + input [17:0] i_data_2_5, + input [17:0] i_data_2_6, + input [17:0] i_data_2_7, + input [17:0] i_data_2_8, + input [17:0] i_data_2_9, + input [17:0] i_data_2_10, + input [17:0] i_data_2_11, + input [17:0] i_data_2_12, + input [17:0] i_data_2_13, + input [17:0] i_data_2_14, + input [17:0] i_data_2_15, + output [17:0] o_data_0, + output [17:0] o_data_1, + output [17:0] o_data_2, + output [17:0] o_data_3, + output [17:0] o_data_4, + output [17:0] o_data_5, + output [17:0] o_data_6, + output [17:0] o_data_7, + output [17:0] o_data_8, + output [17:0] o_data_9, + output [17:0] o_data_10, + output [17:0] o_data_11, + output [17:0] o_data_12, + output [17:0] o_data_13, + output [17:0] o_data_14, + output [17:0] o_data_15, + output o_valid +); + +reg [17:0] pipeline_0_0; +reg [17:0] pipeline_0_1; +reg [17:0] pipeline_0_2; +reg [17:0] pipeline_0_3; +reg [17:0] pipeline_0_4; +reg [17:0] pipeline_0_5; +reg [17:0] pipeline_0_6; +reg [17:0] pipeline_0_7; +reg [17:0] pipeline_0_8; +reg [17:0] pipeline_0_9; +reg [17:0] pipeline_0_10; +reg [17:0] pipeline_0_11; +reg [17:0] pipeline_0_12; +reg [17:0] pipeline_0_13; +reg [17:0] pipeline_0_14; +reg [17:0] pipeline_0_15; +reg [17:0] pipeline_1_0; +reg [17:0] pipeline_1_1; +reg [17:0] pipeline_1_2; +reg [17:0] pipeline_1_3; +reg [17:0] pipeline_1_4; +reg [17:0] pipeline_1_5; +reg [17:0] pipeline_1_6; +reg [17:0] pipeline_1_7; +reg [17:0] pipeline_1_8; +reg [17:0] pipeline_1_9; +reg [17:0] pipeline_1_10; +reg [17:0] pipeline_1_11; +reg [17:0] pipeline_1_12; +reg [17:0] pipeline_1_13; +reg [17:0] pipeline_1_14; +reg [17:0] pipeline_1_15; +reg [17:0] pipeline_2_0; +reg [17:0] pipeline_2_1; +reg [17:0] pipeline_2_2; +reg [17:0] pipeline_2_3; +reg [17:0] pipeline_2_4; +reg [17:0] pipeline_2_5; +reg [17:0] pipeline_2_6; +reg [17:0] pipeline_2_7; +reg [17:0] pipeline_2_8; +reg [17:0] pipeline_2_9; +reg [17:0] pipeline_2_10; +reg [17:0] pipeline_2_11; +reg [17:0] pipeline_2_12; +reg [17:0] pipeline_2_13; +reg [17:0] pipeline_2_14; +reg [17:0] pipeline_2_15; +reg [17:0] pipeline_3_0; +reg [17:0] pipeline_3_1; +reg [17:0] pipeline_3_2; +reg [17:0] pipeline_3_3; +reg [17:0] pipeline_3_4; +reg [17:0] pipeline_3_5; +reg [17:0] pipeline_3_6; +reg [17:0] pipeline_3_7; +reg [17:0] pipeline_3_8; +reg [17:0] pipeline_3_9; +reg [17:0] pipeline_3_10; +reg [17:0] pipeline_3_11; +reg [17:0] pipeline_3_12; +reg [17:0] pipeline_3_13; +reg [17:0] pipeline_3_14; +reg [17:0] pipeline_3_15; +reg [17:0] pipeline_4_0; +reg [17:0] pipeline_4_1; +reg [17:0] pipeline_4_2; +reg [17:0] pipeline_4_3; +reg [17:0] pipeline_4_4; +reg [17:0] pipeline_4_5; +reg [17:0] pipeline_4_6; +reg [17:0] pipeline_4_7; +reg [17:0] pipeline_4_8; +reg [17:0] pipeline_4_9; +reg [17:0] pipeline_4_10; +reg [17:0] pipeline_4_11; +reg [17:0] pipeline_4_12; +reg [17:0] pipeline_4_13; +reg [17:0] pipeline_4_14; +reg [17:0] pipeline_4_15; +reg pipeline_valid_0; +reg pipeline_valid_1; +reg pipeline_valid_2; +reg pipeline_valid_3; +reg pipeline_valid_4; + +always @ (posedge clk) begin + if (reset) begin + pipeline_0_0 <= 0; + pipeline_0_1 <= 0; + pipeline_0_2 <= 0; + pipeline_0_3 <= 0; + pipeline_0_4 <= 0; + pipeline_0_5 <= 0; + pipeline_0_6 <= 0; + pipeline_0_7 <= 0; + pipeline_0_8 <= 0; + pipeline_0_9 <= 0; + pipeline_0_10 <= 0; + pipeline_0_11 <= 0; + pipeline_0_12 <= 0; + pipeline_0_13 <= 0; + pipeline_0_14 <= 0; + pipeline_0_15 <= 0; + pipeline_1_0 <= 0; + pipeline_1_1 <= 0; + pipeline_1_2 <= 0; + pipeline_1_3 <= 0; + pipeline_1_4 <= 0; + pipeline_1_5 <= 0; + pipeline_1_6 <= 0; + pipeline_1_7 <= 0; + pipeline_1_8 <= 0; + pipeline_1_9 <= 0; + pipeline_1_10 <= 0; + pipeline_1_11 <= 0; + pipeline_1_12 <= 0; + pipeline_1_13 <= 0; + pipeline_1_14 <= 0; + pipeline_1_15 <= 0; + pipeline_2_0 <= 0; + pipeline_2_1 <= 0; + pipeline_2_2 <= 0; + pipeline_2_3 <= 0; + pipeline_2_4 <= 0; + pipeline_2_5 <= 0; + pipeline_2_6 <= 0; + pipeline_2_7 <= 0; + pipeline_2_8 <= 0; + pipeline_2_9 <= 0; + pipeline_2_10 <= 0; + pipeline_2_11 <= 0; + pipeline_2_12 <= 0; + pipeline_2_13 <= 0; + pipeline_2_14 <= 0; + pipeline_2_15 <= 0; + pipeline_3_0 <= 0; + pipeline_3_1 <= 0; + pipeline_3_2 <= 0; + pipeline_3_3 <= 0; + pipeline_3_4 <= 0; + pipeline_3_5 <= 0; + pipeline_3_6 <= 0; + pipeline_3_7 <= 0; + pipeline_3_8 <= 0; + pipeline_3_9 <= 0; + pipeline_3_10 <= 0; + pipeline_3_11 <= 0; + pipeline_3_12 <= 0; + pipeline_3_13 <= 0; + pipeline_3_14 <= 0; + pipeline_3_15 <= 0; + pipeline_4_0 <= 0; + pipeline_4_1 <= 0; + pipeline_4_2 <= 0; + pipeline_4_3 <= 0; + pipeline_4_4 <= 0; + pipeline_4_5 <= 0; + pipeline_4_6 <= 0; + pipeline_4_7 <= 0; + pipeline_4_8 <= 0; + pipeline_4_9 <= 0; + pipeline_4_10 <= 0; + pipeline_4_11 <= 0; + pipeline_4_12 <= 0; + pipeline_4_13 <= 0; + pipeline_4_14 <= 0; + pipeline_4_15 <= 0; + pipeline_valid_0 <= 0; + pipeline_valid_1 <= 0; + pipeline_valid_2 <= 0; + pipeline_valid_3 <= 0; + pipeline_valid_4 <= 0; + end else if (enable) begin + if (load_input) begin + pipeline_0_0 <= i_data_0_0; + pipeline_0_1 <= i_data_0_1; + pipeline_0_2 <= i_data_0_2; + pipeline_0_3 <= i_data_0_3; + pipeline_0_4 <= i_data_0_4; + pipeline_0_5 <= i_data_0_5; + pipeline_0_6 <= i_data_0_6; + pipeline_0_7 <= i_data_0_7; + pipeline_0_8 <= i_data_0_8; + pipeline_0_9 <= i_data_0_9; + pipeline_0_10 <= i_data_0_10; + pipeline_0_11 <= i_data_0_11; + pipeline_0_12 <= i_data_0_12; + pipeline_0_13 <= i_data_0_13; + pipeline_0_14 <= i_data_0_14; + pipeline_0_15 <= i_data_0_15; + pipeline_valid_0 <= 1'b1; + pipeline_2_0 <= i_data_1_0; + pipeline_2_1 <= i_data_1_1; + pipeline_2_2 <= i_data_1_2; + pipeline_2_3 <= i_data_1_3; + pipeline_2_4 <= i_data_1_4; + pipeline_2_5 <= i_data_1_5; + pipeline_2_6 <= i_data_1_6; + pipeline_2_7 <= i_data_1_7; + pipeline_2_8 <= i_data_1_8; + pipeline_2_9 <= i_data_1_9; + pipeline_2_10 <= i_data_1_10; + pipeline_2_11 <= i_data_1_11; + pipeline_2_12 <= i_data_1_12; + pipeline_2_13 <= i_data_1_13; + pipeline_2_14 <= i_data_1_14; + pipeline_2_15 <= i_data_1_15; + pipeline_valid_2 <= 1'b1; + pipeline_4_0 <= i_data_2_0; + pipeline_4_1 <= i_data_2_1; + pipeline_4_2 <= i_data_2_2; + pipeline_4_3 <= i_data_2_3; + pipeline_4_4 <= i_data_2_4; + pipeline_4_5 <= i_data_2_5; + pipeline_4_6 <= i_data_2_6; + pipeline_4_7 <= i_data_2_7; + pipeline_4_8 <= i_data_2_8; + pipeline_4_9 <= i_data_2_9; + pipeline_4_10 <= i_data_2_10; + pipeline_4_11 <= i_data_2_11; + pipeline_4_12 <= i_data_2_12; + pipeline_4_13 <= i_data_2_13; + pipeline_4_14 <= i_data_2_14; + pipeline_4_15 <= i_data_2_15; + pipeline_valid_4 <= 1'b1; + pipeline_1_0 <= i_data_1_0; + pipeline_1_1 <= i_data_1_1; + pipeline_1_2 <= i_data_1_2; + pipeline_1_3 <= i_data_1_3; + pipeline_1_4 <= i_data_1_4; + pipeline_1_5 <= i_data_1_5; + pipeline_1_6 <= i_data_1_6; + pipeline_1_7 <= i_data_1_7; + pipeline_1_8 <= i_data_1_8; + pipeline_1_9 <= i_data_1_9; + pipeline_1_10 <= i_data_1_10; + pipeline_1_11 <= i_data_1_11; + pipeline_1_12 <= i_data_1_12; + pipeline_1_13 <= i_data_1_13; + pipeline_1_14 <= i_data_1_14; + pipeline_1_15 <= i_data_1_15; + pipeline_valid_1 <= 1'b0; + pipeline_3_0 <= i_data_2_0; + pipeline_3_1 <= i_data_2_1; + pipeline_3_2 <= i_data_2_2; + pipeline_3_3 <= i_data_2_3; + pipeline_3_4 <= i_data_2_4; + pipeline_3_5 <= i_data_2_5; + pipeline_3_6 <= i_data_2_6; + pipeline_3_7 <= i_data_2_7; + pipeline_3_8 <= i_data_2_8; + pipeline_3_9 <= i_data_2_9; + pipeline_3_10 <= i_data_2_10; + pipeline_3_11 <= i_data_2_11; + pipeline_3_12 <= i_data_2_12; + pipeline_3_13 <= i_data_2_13; + pipeline_3_14 <= i_data_2_14; + pipeline_3_15 <= i_data_2_15; + pipeline_valid_3 <= 1'b0; + end else begin + pipeline_4_0 <= 0; + pipeline_4_1 <= 0; + pipeline_4_2 <= 0; + pipeline_4_3 <= 0; + pipeline_4_4 <= 0; + pipeline_4_5 <= 0; + pipeline_4_6 <= 0; + pipeline_4_7 <= 0; + pipeline_4_8 <= 0; + pipeline_4_9 <= 0; + pipeline_4_10 <= 0; + pipeline_4_11 <= 0; + pipeline_4_12 <= 0; + pipeline_4_13 <= 0; + pipeline_4_14 <= 0; + pipeline_4_15 <= 0; + pipeline_valid_4 <= 1'b0; + pipeline_0_0 <= pipeline_1_0; + pipeline_0_1 <= pipeline_1_1; + pipeline_0_2 <= pipeline_1_2; + pipeline_0_3 <= pipeline_1_3; + pipeline_0_4 <= pipeline_1_4; + pipeline_0_5 <= pipeline_1_5; + pipeline_0_6 <= pipeline_1_6; + pipeline_0_7 <= pipeline_1_7; + pipeline_0_8 <= pipeline_1_8; + pipeline_0_9 <= pipeline_1_9; + pipeline_0_10 <= pipeline_1_10; + pipeline_0_11 <= pipeline_1_11; + pipeline_0_12 <= pipeline_1_12; + pipeline_0_13 <= pipeline_1_13; + pipeline_0_14 <= pipeline_1_14; + pipeline_0_15 <= pipeline_1_15; + pipeline_valid_0 <= pipeline_valid_1; + pipeline_1_0 <= pipeline_2_0; + pipeline_1_1 <= pipeline_2_1; + pipeline_1_2 <= pipeline_2_2; + pipeline_1_3 <= pipeline_2_3; + pipeline_1_4 <= pipeline_2_4; + pipeline_1_5 <= pipeline_2_5; + pipeline_1_6 <= pipeline_2_6; + pipeline_1_7 <= pipeline_2_7; + pipeline_1_8 <= pipeline_2_8; + pipeline_1_9 <= pipeline_2_9; + pipeline_1_10 <= pipeline_2_10; + pipeline_1_11 <= pipeline_2_11; + pipeline_1_12 <= pipeline_2_12; + pipeline_1_13 <= pipeline_2_13; + pipeline_1_14 <= pipeline_2_14; + pipeline_1_15 <= pipeline_2_15; + pipeline_valid_1 <= pipeline_valid_2; + pipeline_2_0 <= pipeline_3_0; + pipeline_2_1 <= pipeline_3_1; + pipeline_2_2 <= pipeline_3_2; + pipeline_2_3 <= pipeline_3_3; + pipeline_2_4 <= pipeline_3_4; + pipeline_2_5 <= pipeline_3_5; + pipeline_2_6 <= pipeline_3_6; + pipeline_2_7 <= pipeline_3_7; + pipeline_2_8 <= pipeline_3_8; + pipeline_2_9 <= pipeline_3_9; + pipeline_2_10 <= pipeline_3_10; + pipeline_2_11 <= pipeline_3_11; + pipeline_2_12 <= pipeline_3_12; + pipeline_2_13 <= pipeline_3_13; + pipeline_2_14 <= pipeline_3_14; + pipeline_2_15 <= pipeline_3_15; + pipeline_valid_2 <= pipeline_valid_3; + pipeline_3_0 <= pipeline_4_0; + pipeline_3_1 <= pipeline_4_1; + pipeline_3_2 <= pipeline_4_2; + pipeline_3_3 <= pipeline_4_3; + pipeline_3_4 <= pipeline_4_4; + pipeline_3_5 <= pipeline_4_5; + pipeline_3_6 <= pipeline_4_6; + pipeline_3_7 <= pipeline_4_7; + pipeline_3_8 <= pipeline_4_8; + pipeline_3_9 <= pipeline_4_9; + pipeline_3_10 <= pipeline_4_10; + pipeline_3_11 <= pipeline_4_11; + pipeline_3_12 <= pipeline_4_12; + pipeline_3_13 <= pipeline_4_13; + pipeline_3_14 <= pipeline_4_14; + pipeline_3_15 <= pipeline_4_15; + pipeline_valid_3 <= pipeline_valid_4; + end + end +end + +assign o_data_0 = pipeline_0_0; +assign o_data_1 = pipeline_0_1; +assign o_data_2 = pipeline_0_2; +assign o_data_3 = pipeline_0_3; +assign o_data_4 = pipeline_0_4; +assign o_data_5 = pipeline_0_5; +assign o_data_6 = pipeline_0_6; +assign o_data_7 = pipeline_0_7; +assign o_data_8 = pipeline_0_8; +assign o_data_9 = pipeline_0_9; +assign o_data_10 = pipeline_0_10; +assign o_data_11 = pipeline_0_11; +assign o_data_12 = pipeline_0_12; +assign o_data_13 = pipeline_0_13; +assign o_data_14 = pipeline_0_14; +assign o_data_15 = pipeline_0_15; +assign o_valid = pipeline_valid_0; + +endmodule + +module stage2_Ct_buffer_18_3_16_64 ( + input clk, + input reset, + input wen, + input ren, + input [17:0] i_Ct_0, + input [17:0] i_Ct_1, + input [17:0] i_Ct_2, + input [17:0] i_Ct_3, + input [17:0] i_Ct_4, + input [17:0] i_Ct_5, + input [17:0] i_Ct_6, + input [17:0] i_Ct_7, + input [17:0] i_Ct_8, + input [17:0] i_Ct_9, + input [17:0] i_Ct_10, + input [17:0] i_Ct_11, + input [17:0] i_Ct_12, + input [17:0] i_Ct_13, + input [17:0] i_Ct_14, + input [17:0] i_Ct_15, + output [17:0] o_Ct_0, + output [17:0] o_Ct_1, + output [17:0] o_Ct_2, + output [17:0] o_Ct_3, + output [17:0] o_Ct_4, + output [17:0] o_Ct_5, + output [17:0] o_Ct_6, + output [17:0] o_Ct_7, + output [17:0] o_Ct_8, + output [17:0] o_Ct_9, + output [17:0] o_Ct_10, + output [17:0] o_Ct_11, + output [17:0] o_Ct_12, + output [17:0] o_Ct_13, + output [17:0] o_Ct_14, + output [17:0] o_Ct_15, + output [17:0] o_Ct_16, + output [17:0] o_Ct_17, + output [17:0] o_Ct_18, + output [17:0] o_Ct_19, + output [17:0] o_Ct_20, + output [17:0] o_Ct_21, + output [17:0] o_Ct_22, + output [17:0] o_Ct_23, + output [17:0] o_Ct_24, + output [17:0] o_Ct_25, + output [17:0] o_Ct_26, + output [17:0] o_Ct_27, + output [17:0] o_Ct_28, + output [17:0] o_Ct_29, + output [17:0] o_Ct_30, + output [17:0] o_Ct_31, + output [17:0] o_Ct_32, + output [17:0] o_Ct_33, + output [17:0] o_Ct_34, + output [17:0] o_Ct_35, + output [17:0] o_Ct_36, + output [17:0] o_Ct_37, + output [17:0] o_Ct_38, + output [17:0] o_Ct_39, + output [17:0] o_Ct_40, + output [17:0] o_Ct_41, + output [17:0] o_Ct_42, + output [17:0] o_Ct_43, + output [17:0] o_Ct_44, + output [17:0] o_Ct_45, + output [17:0] o_Ct_46, + output [17:0] o_Ct_47, + output o_valid +); + +wire [287:0] packed_o_Ct_0; +reg [5:0] raddrs_0; +wire [287:0] packed_o_Ct_1; +reg [5:0] raddrs_1; +wire [287:0] packed_o_Ct_2; +reg [5:0] raddrs_2; +wire [287:0] packed_Ct; + +reg r_valid; + +wire [13:0] input_index_counter; +counter_63_1 counter_63_1_inst_in ( + .clk(clk), + .reset(reset), + .ena(wen), + .count(input_index_counter) +); + +wire [13:0] output_index_counter; +counter_63_1 counter_63_1_inst_out ( + .clk(clk), + .reset(reset), + .ena(ren), + .count(output_index_counter) +); + +always @ (posedge clk) begin + r_valid <= ren; + if ((input_index_counter + 14'd0) < 64) + raddrs_0 <= input_index_counter[5:0] + 6'd0; + else + raddrs_0 <= 6'd63; + if ((input_index_counter + 14'd1) < 64) + raddrs_1 <= input_index_counter[5:0] + 6'd1; + else + raddrs_1 <= 6'd63; + if ((input_index_counter + 14'd2) < 64) + raddrs_2 <= input_index_counter[5:0] + 6'd2; + else + raddrs_2 <= 6'd63; +end + +assign packed_Ct[17:0] = i_Ct_0; +assign packed_Ct[35:18] = i_Ct_1; +assign packed_Ct[53:36] = i_Ct_2; +assign packed_Ct[71:54] = i_Ct_3; +assign packed_Ct[89:72] = i_Ct_4; +assign packed_Ct[107:90] = i_Ct_5; +assign packed_Ct[125:108] = i_Ct_6; +assign packed_Ct[143:126] = i_Ct_7; +assign packed_Ct[161:144] = i_Ct_8; +assign packed_Ct[179:162] = i_Ct_9; +assign packed_Ct[197:180] = i_Ct_10; +assign packed_Ct[215:198] = i_Ct_11; +assign packed_Ct[233:216] = i_Ct_12; +assign packed_Ct[251:234] = i_Ct_13; +assign packed_Ct[269:252] = i_Ct_14; +assign packed_Ct[287:270] = i_Ct_15; + +ram_288_0_64 ram_288_0_64_inst_0 ( + .clk(clk), + .waddr(input_index_counter), + .wdata(packed_Ct), + .wen(wen), + .raddr(raddrs_0), + .q(packed_o_Ct_0) +); + +ram_288_0_64 ram_288_0_64_inst_1 ( + .clk(clk), + .waddr(input_index_counter), + .wdata(packed_Ct), + .wen(wen), + .raddr(raddrs_1), + .q(packed_o_Ct_1) +); + +ram_288_0_64 ram_288_0_64_inst_2 ( + .clk(clk), + .waddr(input_index_counter), + .wdata(packed_Ct), + .wen(wen), + .raddr(raddrs_2), + .q(packed_o_Ct_2) +); + +assign o_Ct_0 = packed_o_Ct_0[17:0]; +assign o_Ct_1 = packed_o_Ct_0[35:18]; +assign o_Ct_2 = packed_o_Ct_0[53:36]; +assign o_Ct_3 = packed_o_Ct_0[71:54]; +assign o_Ct_4 = packed_o_Ct_0[89:72]; +assign o_Ct_5 = packed_o_Ct_0[107:90]; +assign o_Ct_6 = packed_o_Ct_0[125:108]; +assign o_Ct_7 = packed_o_Ct_0[143:126]; +assign o_Ct_8 = packed_o_Ct_0[161:144]; +assign o_Ct_9 = packed_o_Ct_0[179:162]; +assign o_Ct_10 = packed_o_Ct_0[197:180]; +assign o_Ct_11 = packed_o_Ct_0[215:198]; +assign o_Ct_12 = packed_o_Ct_0[233:216]; +assign o_Ct_13 = packed_o_Ct_0[251:234]; +assign o_Ct_14 = packed_o_Ct_0[269:252]; +assign o_Ct_15 = packed_o_Ct_0[287:270]; +assign o_Ct_16 = packed_o_Ct_1[17:0]; +assign o_Ct_17 = packed_o_Ct_1[35:18]; +assign o_Ct_18 = packed_o_Ct_1[53:36]; +assign o_Ct_19 = packed_o_Ct_1[71:54]; +assign o_Ct_20 = packed_o_Ct_1[89:72]; +assign o_Ct_21 = packed_o_Ct_1[107:90]; +assign o_Ct_22 = packed_o_Ct_1[125:108]; +assign o_Ct_23 = packed_o_Ct_1[143:126]; +assign o_Ct_24 = packed_o_Ct_1[161:144]; +assign o_Ct_25 = packed_o_Ct_1[179:162]; +assign o_Ct_26 = packed_o_Ct_1[197:180]; +assign o_Ct_27 = packed_o_Ct_1[215:198]; +assign o_Ct_28 = packed_o_Ct_1[233:216]; +assign o_Ct_29 = packed_o_Ct_1[251:234]; +assign o_Ct_30 = packed_o_Ct_1[269:252]; +assign o_Ct_31 = packed_o_Ct_1[287:270]; +assign o_Ct_32 = packed_o_Ct_2[17:0]; +assign o_Ct_33 = packed_o_Ct_2[35:18]; +assign o_Ct_34 = packed_o_Ct_2[53:36]; +assign o_Ct_35 = packed_o_Ct_2[71:54]; +assign o_Ct_36 = packed_o_Ct_2[89:72]; +assign o_Ct_37 = packed_o_Ct_2[107:90]; +assign o_Ct_38 = packed_o_Ct_2[125:108]; +assign o_Ct_39 = packed_o_Ct_2[143:126]; +assign o_Ct_40 = packed_o_Ct_2[161:144]; +assign o_Ct_41 = packed_o_Ct_2[179:162]; +assign o_Ct_42 = packed_o_Ct_2[197:180]; +assign o_Ct_43 = packed_o_Ct_2[215:198]; +assign o_Ct_44 = packed_o_Ct_2[233:216]; +assign o_Ct_45 = packed_o_Ct_2[251:234]; +assign o_Ct_46 = packed_o_Ct_2[269:252]; +assign o_Ct_47 = packed_o_Ct_2[287:270]; +assign o_valid = r_valid; +endmodule + +module counter_63_1 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd1) <= 63) begin + count <= count + 14'd1; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module ram_288_0_64 ( + input clk, + input [5:0] waddr, + input [287:0] wdata, + input wen, + input [5:0] raddr, + output [287:0] q +); + +wire [287:0] rd_dummy_signal; +wire [287:0] wr_dummy_signal; +assign rd_dummy_signal = 0; + +dpram # (.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(q), + .clk(clk) +); +endmodule + +module stage2_mt_buffer_18_3_16_64_32 ( + input clk, + input reset, + input i_valid, + input [17:0] data_0, + output [17:0] q_0, + input [17:0] data_1, + output [17:0] q_1, + input [17:0] data_2, + output [17:0] q_2, + input [17:0] data_3, + output [17:0] q_3, + input [17:0] data_4, + output [17:0] q_4, + input [17:0] data_5, + output [17:0] q_5, + input [17:0] data_6, + output [17:0] q_6, + input [17:0] data_7, + output [17:0] q_7, + input [17:0] data_8, + output [17:0] q_8, + input [17:0] data_9, + output [17:0] q_9, + input [17:0] data_10, + output [17:0] q_10, + input [17:0] data_11, + output [17:0] q_11, + input [17:0] data_12, + output [17:0] q_12, + input [17:0] data_13, + output [17:0] q_13, + input [17:0] data_14, + output [17:0] q_14, + input [17:0] data_15, + output [17:0] q_15, + output o_valid +); + +wire [287:0] packed_result; +wire [287:0] packed_data; + +wire [13:0] input_index_counter; +reg is_buffer_full; +counter_63_1 counter_63_1_inst_in ( + .clk(clk), + .reset(reset), + .ena(i_valid), + .count(input_index_counter) +); + +reg en_output_counter; +wire [13:0] output_index_counter; +counter_63_1 counter_63_1_inst_out_count ( + .clk(clk), + .reset(reset), + .ena(en_output_counter), + .count(output_index_counter) +); + +reg [5:0] raddr; +always @ (*) begin + if (is_buffer_full) + raddr <= output_index_counter[5:0]; + else + raddr <= input_index_counter[5:0]; +end + +wire incr_loop_index; +assign incr_loop_index = (output_index_counter == (63) && en_output_counter); + +reg is_output_enough; +wire [13:0] loop_counter; +counter_8_1 counter_8_1_inst_out_enough ( + .clk(clk), + .reset(reset), + .ena(incr_loop_index), + .count(loop_counter) +); + +ram_288_0_64 ram_288_0_64_inst_yssnqshgbs ( + .clk(clk), + .waddr(input_index_counter), + .wdata(packed_data), + .wen(i_valid), + .raddr(raddr), + .q(packed_result) +); + +assign q_0 = packed_result[17:0]; +assign packed_data[17:0] = data_0; +assign q_1 = packed_result[35:18]; +assign packed_data[35:18] = data_1; +assign q_2 = packed_result[53:36]; +assign packed_data[53:36] = data_2; +assign q_3 = packed_result[71:54]; +assign packed_data[71:54] = data_3; +assign q_4 = packed_result[89:72]; +assign packed_data[89:72] = data_4; +assign q_5 = packed_result[107:90]; +assign packed_data[107:90] = data_5; +assign q_6 = packed_result[125:108]; +assign packed_data[125:108] = data_6; +assign q_7 = packed_result[143:126]; +assign packed_data[143:126] = data_7; +assign q_8 = packed_result[161:144]; +assign packed_data[161:144] = data_8; +assign q_9 = packed_result[179:162]; +assign packed_data[179:162] = data_9; +assign q_10 = packed_result[197:180]; +assign packed_data[197:180] = data_10; +assign q_11 = packed_result[215:198]; +assign packed_data[215:198] = data_11; +assign q_12 = packed_result[233:216]; +assign packed_data[233:216] = data_12; +assign q_13 = packed_result[251:234]; +assign packed_data[251:234] = data_13; +assign q_14 = packed_result[269:252]; +assign packed_data[269:252] = data_14; +assign q_15 = packed_result[287:270]; +assign packed_data[287:270] = data_15; + +always @ (posedge clk) begin + if (reset) begin + en_output_counter <= 1'b0; + is_buffer_full <= 1'b0; + is_output_enough <= 1'b0; + end else begin + en_output_counter <= (is_buffer_full && ~en_output_counter && ~is_output_enough); + if (input_index_counter == 63 && i_valid) + is_buffer_full <= 1'b1; + else if (input_index_counter == 0 && output_index_counter == 0 && is_output_enough) + is_buffer_full <= 1'b0; + if ((loop_counter == (8)) + &&(output_index_counter == 63) + && en_output_counter) + is_output_enough <= 1'b1; + else if (loop_counter == 0 && i_valid) + is_output_enough <= 1'b0; + end +end + +wire valid_1, valid_2, is_buffer_full_hold; +shift_register_unit_12 shift_register_unit_12_inst_is_buffer_full ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .in(is_buffer_full), + .out(is_buffer_full_hold) +); + +shift_register_unit_12 shift_register_unit_12_inst_valid1 ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .in(i_valid), + .out(valid_1) +); + +shift_register_unit_12 shift_register_unit_12_inst_valid2 ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .in(en_output_counter), + .out(valid_2) +); + +reg output_valid; +always @ (*) begin + if (is_buffer_full_hold) + output_valid <= valid_2; + else + output_valid <= valid_1; +end +assign o_valid = output_valid; + +endmodule + +module counter_8_1 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd1) <= 8) begin + count <= count + 14'd1; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module shift_register_unit_12 ( + input clk, + input reset, + input enable, + input [0:0] in, + output [0:0] out +); + +reg [0:0] shift_registers_0; +reg [0:0] shift_registers_1; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 1'd0; + shift_registers_1 <= 1'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + end +end + +assign out = shift_registers_1; + +endmodule + +module C_LSTM_stage_3_18_10_64_2048_3_16_1 ( + input clk, + input reset, + input [287:0] wdata, + input [1:0] wen, + input i_ready, + input i_valid, + input [17:0] i_mt_0, + input [17:0] i_mt_1, + input [17:0] i_mt_2, + input [17:0] i_mt_3, + input [17:0] i_mt_4, + input [17:0] i_mt_5, + input [17:0] i_mt_6, + input [17:0] i_mt_7, + input [17:0] i_mt_8, + input [17:0] i_mt_9, + input [17:0] i_mt_10, + input [17:0] i_mt_11, + input [17:0] i_mt_12, + input [17:0] i_mt_13, + input [17:0] i_mt_14, + input [17:0] i_mt_15, + output [17:0] o_Yt_0_0, + output [17:0] o_Yt_0_1, + output [17:0] o_Yt_0_2, + output [17:0] o_Yt_0_3, + output [17:0] o_Yt_0_4, + output [17:0] o_Yt_0_5, + output [17:0] o_Yt_0_6, + output [17:0] o_Yt_0_7, + output [17:0] o_Yt_0_8, + output [17:0] o_Yt_0_9, + output [17:0] o_Yt_0_10, + output [17:0] o_Yt_0_11, + output [17:0] o_Yt_0_12, + output [17:0] o_Yt_0_13, + output [17:0] o_Yt_0_14, + output [17:0] o_Yt_0_15, + output [17:0] o_Yt_1_0, + output [17:0] o_Yt_1_1, + output [17:0] o_Yt_1_2, + output [17:0] o_Yt_1_3, + output [17:0] o_Yt_1_4, + output [17:0] o_Yt_1_5, + output [17:0] o_Yt_1_6, + output [17:0] o_Yt_1_7, + output [17:0] o_Yt_1_8, + output [17:0] o_Yt_1_9, + output [17:0] o_Yt_1_10, + output [17:0] o_Yt_1_11, + output [17:0] o_Yt_1_12, + output [17:0] o_Yt_1_13, + output [17:0] o_Yt_1_14, + output [17:0] o_Yt_1_15, + output [17:0] o_Yt_2_0, + output [17:0] o_Yt_2_1, + output [17:0] o_Yt_2_2, + output [17:0] o_Yt_2_3, + output [17:0] o_Yt_2_4, + output [17:0] o_Yt_2_5, + output [17:0] o_Yt_2_6, + output [17:0] o_Yt_2_7, + output [17:0] o_Yt_2_8, + output [17:0] o_Yt_2_9, + output [17:0] o_Yt_2_10, + output [17:0] o_Yt_2_11, + output [17:0] o_Yt_2_12, + output [17:0] o_Yt_2_13, + output [17:0] o_Yt_2_14, + output [17:0] o_Yt_2_15, + output o_valid, + output o_ready +); + +wire enable; +assign enable = i_ready; +wire [17:0] mt_hold_0; +wire [17:0] mt_hold_1; +wire [17:0] mt_hold_2; +wire [17:0] mt_hold_3; +wire [17:0] mt_hold_4; +wire [17:0] mt_hold_5; +wire [17:0] mt_hold_6; +wire [17:0] mt_hold_7; +wire [17:0] mt_hold_8; +wire [17:0] mt_hold_9; +wire [17:0] mt_hold_10; +wire [17:0] mt_hold_11; +wire [17:0] mt_hold_12; +wire [17:0] mt_hold_13; +wire [17:0] mt_hold_14; +wire [17:0] mt_hold_15; +wire [17:0] Wym_real_0_0; +wire [17:0] Wym_imag_0_0; +wire [17:0] Wym_real_0_1; +wire [17:0] Wym_imag_0_1; +wire [17:0] Wym_real_0_2; +wire [17:0] Wym_imag_0_2; +wire [17:0] Wym_real_0_3; +wire [17:0] Wym_imag_0_3; +wire [17:0] Wym_real_0_4; +wire [17:0] Wym_imag_0_4; +wire [17:0] Wym_real_0_5; +wire [17:0] Wym_imag_0_5; +wire [17:0] Wym_real_0_6; +wire [17:0] Wym_imag_0_6; +wire [17:0] Wym_real_0_7; +wire [17:0] Wym_imag_0_7; +wire [17:0] Wym_real_0_8; +wire [17:0] Wym_imag_0_8; +wire [17:0] Wym_real_1_0; +wire [17:0] Wym_imag_1_0; +wire [17:0] Wym_real_1_1; +wire [17:0] Wym_imag_1_1; +wire [17:0] Wym_real_1_2; +wire [17:0] Wym_imag_1_2; +wire [17:0] Wym_real_1_3; +wire [17:0] Wym_imag_1_3; +wire [17:0] Wym_real_1_4; +wire [17:0] Wym_imag_1_4; +wire [17:0] Wym_real_1_5; +wire [17:0] Wym_imag_1_5; +wire [17:0] Wym_real_1_6; +wire [17:0] Wym_imag_1_6; +wire [17:0] Wym_real_1_7; +wire [17:0] Wym_imag_1_7; +wire [17:0] Wym_real_1_8; +wire [17:0] Wym_imag_1_8; +wire [17:0] Wym_real_2_0; +wire [17:0] Wym_imag_2_0; +wire [17:0] Wym_real_2_1; +wire [17:0] Wym_imag_2_1; +wire [17:0] Wym_real_2_2; +wire [17:0] Wym_imag_2_2; +wire [17:0] Wym_real_2_3; +wire [17:0] Wym_imag_2_3; +wire [17:0] Wym_real_2_4; +wire [17:0] Wym_imag_2_4; +wire [17:0] Wym_real_2_5; +wire [17:0] Wym_imag_2_5; +wire [17:0] Wym_real_2_6; +wire [17:0] Wym_imag_2_6; +wire [17:0] Wym_real_2_7; +wire [17:0] Wym_imag_2_7; +wire [17:0] Wym_real_2_8; +wire [17:0] Wym_imag_2_8; +wire reg_i_valid; +reg reg_i_ready; + +shift_register_group_18_16_3 shift_register_group_18_16_3_mt_holder ( + .clk(clk), + .enable(enable), + .in_0(i_mt_0), + .out_0(mt_hold_0), + .in_1(i_mt_1), + .out_1(mt_hold_1), + .in_2(i_mt_2), + .out_2(mt_hold_2), + .in_3(i_mt_3), + .out_3(mt_hold_3), + .in_4(i_mt_4), + .out_4(mt_hold_4), + .in_5(i_mt_5), + .out_5(mt_hold_5), + .in_6(i_mt_6), + .out_6(mt_hold_6), + .in_7(i_mt_7), + .out_7(mt_hold_7), + .in_8(i_mt_8), + .out_8(mt_hold_8), + .in_9(i_mt_9), + .out_9(mt_hold_9), + .in_10(i_mt_10), + .out_10(mt_hold_10), + .in_11(i_mt_11), + .out_11(mt_hold_11), + .in_12(i_mt_12), + .out_12(mt_hold_12), + .in_13(i_mt_13), + .out_13(mt_hold_13), + .in_14(i_mt_14), + .out_14(mt_hold_14), + .in_15(i_mt_15), + .out_15(mt_hold_15), + .reset(reset) +); + +shift_register_unit_18_3 shift_register_unit_18_3_valid_holder ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(i_valid), + .out(reg_i_valid) +); + +stage3_parameter_buffer_18_3_16_64_2048 stage3_parameter_buffer_18_3_16_64_2048_inst_cysdmwxqvl ( + .clk(clk), + .reset(reset), + .wdata(wdata), + .wen(wen), + .Wym_real_0_0(Wym_real_0_0), + .Wym_imag_0_0(Wym_imag_0_0), + .Wym_real_0_1(Wym_real_0_1), + .Wym_imag_0_1(Wym_imag_0_1), + .Wym_real_0_2(Wym_real_0_2), + .Wym_imag_0_2(Wym_imag_0_2), + .Wym_real_0_3(Wym_real_0_3), + .Wym_imag_0_3(Wym_imag_0_3), + .Wym_real_0_4(Wym_real_0_4), + .Wym_imag_0_4(Wym_imag_0_4), + .Wym_real_0_5(Wym_real_0_5), + .Wym_imag_0_5(Wym_imag_0_5), + .Wym_real_0_6(Wym_real_0_6), + .Wym_imag_0_6(Wym_imag_0_6), + .Wym_real_0_7(Wym_real_0_7), + .Wym_imag_0_7(Wym_imag_0_7), + .Wym_real_0_8(Wym_real_0_8), + .Wym_imag_0_8(Wym_imag_0_8), + .Wym_real_1_0(Wym_real_1_0), + .Wym_imag_1_0(Wym_imag_1_0), + .Wym_real_1_1(Wym_real_1_1), + .Wym_imag_1_1(Wym_imag_1_1), + .Wym_real_1_2(Wym_real_1_2), + .Wym_imag_1_2(Wym_imag_1_2), + .Wym_real_1_3(Wym_real_1_3), + .Wym_imag_1_3(Wym_imag_1_3), + .Wym_real_1_4(Wym_real_1_4), + .Wym_imag_1_4(Wym_imag_1_4), + .Wym_real_1_5(Wym_real_1_5), + .Wym_imag_1_5(Wym_imag_1_5), + .Wym_real_1_6(Wym_real_1_6), + .Wym_imag_1_6(Wym_imag_1_6), + .Wym_real_1_7(Wym_real_1_7), + .Wym_imag_1_7(Wym_imag_1_7), + .Wym_real_1_8(Wym_real_1_8), + .Wym_imag_1_8(Wym_imag_1_8), + .Wym_real_2_0(Wym_real_2_0), + .Wym_imag_2_0(Wym_imag_2_0), + .Wym_real_2_1(Wym_real_2_1), + .Wym_imag_2_1(Wym_imag_2_1), + .Wym_real_2_2(Wym_real_2_2), + .Wym_imag_2_2(Wym_imag_2_2), + .Wym_real_2_3(Wym_real_2_3), + .Wym_imag_2_3(Wym_imag_2_3), + .Wym_real_2_4(Wym_real_2_4), + .Wym_imag_2_4(Wym_imag_2_4), + .Wym_real_2_5(Wym_real_2_5), + .Wym_imag_2_5(Wym_imag_2_5), + .Wym_real_2_6(Wym_real_2_6), + .Wym_imag_2_6(Wym_imag_2_6), + .Wym_real_2_7(Wym_real_2_7), + .Wym_imag_2_7(Wym_imag_2_7), + .Wym_real_2_8(Wym_real_2_8), + .Wym_imag_2_8(Wym_imag_2_8), + .incr_index(i_valid) +); + +multiple_c_matrix_vec_mult_and_sum_18_10_16_1_3_64 multiple_c_matrix_vec_mult_and_sum_18_10_16_1_3_64_inst_pjagftcbsq ( + .clk(clk), + .reset(reset), + .i_ready(reg_i_ready), + .i_valid(reg_i_valid), + .i_X_0(mt_hold_0), + .i_X_1(mt_hold_1), + .i_X_2(mt_hold_2), + .i_X_3(mt_hold_3), + .i_X_4(mt_hold_4), + .i_X_5(mt_hold_5), + .i_X_6(mt_hold_6), + .i_X_7(mt_hold_7), + .i_X_8(mt_hold_8), + .i_X_9(mt_hold_9), + .i_X_10(mt_hold_10), + .i_X_11(mt_hold_11), + .i_X_12(mt_hold_12), + .i_X_13(mt_hold_13), + .i_X_14(mt_hold_14), + .i_X_15(mt_hold_15), + .i_W_real_0_0(Wym_real_0_0), + .i_W_imag_0_0(Wym_imag_0_0), + .i_W_real_0_1(Wym_real_0_1), + .i_W_imag_0_1(Wym_imag_0_1), + .i_W_real_0_2(Wym_real_0_2), + .i_W_imag_0_2(Wym_imag_0_2), + .i_W_real_0_3(Wym_real_0_3), + .i_W_imag_0_3(Wym_imag_0_3), + .i_W_real_0_4(Wym_real_0_4), + .i_W_imag_0_4(Wym_imag_0_4), + .i_W_real_0_5(Wym_real_0_5), + .i_W_imag_0_5(Wym_imag_0_5), + .i_W_real_0_6(Wym_real_0_6), + .i_W_imag_0_6(Wym_imag_0_6), + .i_W_real_0_7(Wym_real_0_7), + .i_W_imag_0_7(Wym_imag_0_7), + .i_W_real_0_8(Wym_real_0_8), + .i_W_imag_0_8(Wym_imag_0_8), + .i_W_real_1_0(Wym_real_1_0), + .i_W_imag_1_0(Wym_imag_1_0), + .i_W_real_1_1(Wym_real_1_1), + .i_W_imag_1_1(Wym_imag_1_1), + .i_W_real_1_2(Wym_real_1_2), + .i_W_imag_1_2(Wym_imag_1_2), + .i_W_real_1_3(Wym_real_1_3), + .i_W_imag_1_3(Wym_imag_1_3), + .i_W_real_1_4(Wym_real_1_4), + .i_W_imag_1_4(Wym_imag_1_4), + .i_W_real_1_5(Wym_real_1_5), + .i_W_imag_1_5(Wym_imag_1_5), + .i_W_real_1_6(Wym_real_1_6), + .i_W_imag_1_6(Wym_imag_1_6), + .i_W_real_1_7(Wym_real_1_7), + .i_W_imag_1_7(Wym_imag_1_7), + .i_W_real_1_8(Wym_real_1_8), + .i_W_imag_1_8(Wym_imag_1_8), + .i_W_real_2_0(Wym_real_2_0), + .i_W_imag_2_0(Wym_imag_2_0), + .i_W_real_2_1(Wym_real_2_1), + .i_W_imag_2_1(Wym_imag_2_1), + .i_W_real_2_2(Wym_real_2_2), + .i_W_imag_2_2(Wym_imag_2_2), + .i_W_real_2_3(Wym_real_2_3), + .i_W_imag_2_3(Wym_imag_2_3), + .i_W_real_2_4(Wym_real_2_4), + .i_W_imag_2_4(Wym_imag_2_4), + .i_W_real_2_5(Wym_real_2_5), + .i_W_imag_2_5(Wym_imag_2_5), + .i_W_real_2_6(Wym_real_2_6), + .i_W_imag_2_6(Wym_imag_2_6), + .i_W_real_2_7(Wym_real_2_7), + .i_W_imag_2_7(Wym_imag_2_7), + .i_W_real_2_8(Wym_real_2_8), + .i_W_imag_2_8(Wym_imag_2_8), + .o_Y_0_0(o_Yt_0_0), + .o_Y_0_1(o_Yt_0_1), + .o_Y_0_2(o_Yt_0_2), + .o_Y_0_3(o_Yt_0_3), + .o_Y_0_4(o_Yt_0_4), + .o_Y_0_5(o_Yt_0_5), + .o_Y_0_6(o_Yt_0_6), + .o_Y_0_7(o_Yt_0_7), + .o_Y_0_8(o_Yt_0_8), + .o_Y_0_9(o_Yt_0_9), + .o_Y_0_10(o_Yt_0_10), + .o_Y_0_11(o_Yt_0_11), + .o_Y_0_12(o_Yt_0_12), + .o_Y_0_13(o_Yt_0_13), + .o_Y_0_14(o_Yt_0_14), + .o_Y_0_15(o_Yt_0_15), + .o_Y_1_0(o_Yt_1_0), + .o_Y_1_1(o_Yt_1_1), + .o_Y_1_2(o_Yt_1_2), + .o_Y_1_3(o_Yt_1_3), + .o_Y_1_4(o_Yt_1_4), + .o_Y_1_5(o_Yt_1_5), + .o_Y_1_6(o_Yt_1_6), + .o_Y_1_7(o_Yt_1_7), + .o_Y_1_8(o_Yt_1_8), + .o_Y_1_9(o_Yt_1_9), + .o_Y_1_10(o_Yt_1_10), + .o_Y_1_11(o_Yt_1_11), + .o_Y_1_12(o_Yt_1_12), + .o_Y_1_13(o_Yt_1_13), + .o_Y_1_14(o_Yt_1_14), + .o_Y_1_15(o_Yt_1_15), + .o_Y_2_0(o_Yt_2_0), + .o_Y_2_1(o_Yt_2_1), + .o_Y_2_2(o_Yt_2_2), + .o_Y_2_3(o_Yt_2_3), + .o_Y_2_4(o_Yt_2_4), + .o_Y_2_5(o_Yt_2_5), + .o_Y_2_6(o_Yt_2_6), + .o_Y_2_7(o_Yt_2_7), + .o_Y_2_8(o_Yt_2_8), + .o_Y_2_9(o_Yt_2_9), + .o_Y_2_10(o_Yt_2_10), + .o_Y_2_11(o_Yt_2_11), + .o_Y_2_12(o_Yt_2_12), + .o_Y_2_13(o_Yt_2_13), + .o_Y_2_14(o_Yt_2_14), + .o_Y_2_15(o_Yt_2_15), + .o_valid(o_valid), + .o_ready(o_ready) +); + +always @ (posedge clk) begin + if (reset) begin + reg_i_ready <= 1'b0; + end else begin + reg_i_ready <= i_ready; + end +end + +endmodule + +module stage3_parameter_buffer_18_3_16_64_2048 ( + input clk, + input reset, + input [161:0] wdata, + input [1:0] wen, + output [17:0] Wym_real_0_0, + output [17:0] Wym_imag_0_0, + output [17:0] Wym_real_0_1, + output [17:0] Wym_imag_0_1, + output [17:0] Wym_real_0_2, + output [17:0] Wym_imag_0_2, + output [17:0] Wym_real_0_3, + output [17:0] Wym_imag_0_3, + output [17:0] Wym_real_0_4, + output [17:0] Wym_imag_0_4, + output [17:0] Wym_real_0_5, + output [17:0] Wym_imag_0_5, + output [17:0] Wym_real_0_6, + output [17:0] Wym_imag_0_6, + output [17:0] Wym_real_0_7, + output [17:0] Wym_imag_0_7, + output [17:0] Wym_real_0_8, + output [17:0] Wym_imag_0_8, + output [17:0] Wym_real_1_0, + output [17:0] Wym_imag_1_0, + output [17:0] Wym_real_1_1, + output [17:0] Wym_imag_1_1, + output [17:0] Wym_real_1_2, + output [17:0] Wym_imag_1_2, + output [17:0] Wym_real_1_3, + output [17:0] Wym_imag_1_3, + output [17:0] Wym_real_1_4, + output [17:0] Wym_imag_1_4, + output [17:0] Wym_real_1_5, + output [17:0] Wym_imag_1_5, + output [17:0] Wym_real_1_6, + output [17:0] Wym_imag_1_6, + output [17:0] Wym_real_1_7, + output [17:0] Wym_imag_1_7, + output [17:0] Wym_real_1_8, + output [17:0] Wym_imag_1_8, + output [17:0] Wym_real_2_0, + output [17:0] Wym_imag_2_0, + output [17:0] Wym_real_2_1, + output [17:0] Wym_imag_2_1, + output [17:0] Wym_real_2_2, + output [17:0] Wym_imag_2_2, + output [17:0] Wym_real_2_3, + output [17:0] Wym_imag_2_3, + output [17:0] Wym_real_2_4, + output [17:0] Wym_imag_2_4, + output [17:0] Wym_real_2_5, + output [17:0] Wym_imag_2_5, + output [17:0] Wym_real_2_6, + output [17:0] Wym_imag_2_6, + output [17:0] Wym_real_2_7, + output [17:0] Wym_imag_2_7, + output [17:0] Wym_real_2_8, + output [17:0] Wym_imag_2_8, + input incr_index +); + +wire [13:0] input_index_counter; +counter_63_1 counter_63_1_inst_input ( + .clk(clk), + .reset(reset), + .ena(incr_index), + .count(input_index_counter) +); + +wire incr_row_index; +assign incr_row_index = (input_index_counter == 63 & incr_index); +wire [13:0] weight_row_index_counter; +counter_31_3 counter_31_3_inst_weight ( + .clk(clk), + .reset(reset), + .ena(incr_row_index), + .count(weight_row_index_counter) +); + +reg [13:0] weight_index; +always @ (*) begin + weight_index = weight_row_index_counter * 14'd64 + input_index_counter; +end +weight_buffer_18_9_3_64_2048_Wym_real_half_0 weight_buffer_18_9_3_64_2048_Wym_real_half_0_inst_iesopogdvk_real ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[0]), + .q_0_0(Wym_real_0_0), + .q_0_1(Wym_real_0_1), + .q_0_2(Wym_real_0_2), + .q_0_3(Wym_real_0_3), + .q_0_4(Wym_real_0_4), + .q_0_5(Wym_real_0_5), + .q_0_6(Wym_real_0_6), + .q_0_7(Wym_real_0_7), + .q_0_8(Wym_real_0_8), + .q_1_0(Wym_real_1_0), + .q_1_1(Wym_real_1_1), + .q_1_2(Wym_real_1_2), + .q_1_3(Wym_real_1_3), + .q_1_4(Wym_real_1_4), + .q_1_5(Wym_real_1_5), + .q_1_6(Wym_real_1_6), + .q_1_7(Wym_real_1_7), + .q_1_8(Wym_real_1_8), + .q_2_0(Wym_real_2_0), + .q_2_1(Wym_real_2_1), + .q_2_2(Wym_real_2_2), + .q_2_3(Wym_real_2_3), + .q_2_4(Wym_real_2_4), + .q_2_5(Wym_real_2_5), + .q_2_6(Wym_real_2_6), + .q_2_7(Wym_real_2_7), + .q_2_8(Wym_real_2_8), + .index(weight_index) +); + +weight_buffer_18_9_3_64_2048_Wym_imag_half_0 weight_buffer_18_9_3_64_2048_Wym_imag_half_0_inst_lbzuazhzae_imag ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[1]), + .q_0_0(Wym_imag_0_0), + .q_0_1(Wym_imag_0_1), + .q_0_2(Wym_imag_0_2), + .q_0_3(Wym_imag_0_3), + .q_0_4(Wym_imag_0_4), + .q_0_5(Wym_imag_0_5), + .q_0_6(Wym_imag_0_6), + .q_0_7(Wym_imag_0_7), + .q_0_8(Wym_imag_0_8), + .q_1_0(Wym_imag_1_0), + .q_1_1(Wym_imag_1_1), + .q_1_2(Wym_imag_1_2), + .q_1_3(Wym_imag_1_3), + .q_1_4(Wym_imag_1_4), + .q_1_5(Wym_imag_1_5), + .q_1_6(Wym_imag_1_6), + .q_1_7(Wym_imag_1_7), + .q_1_8(Wym_imag_1_8), + .q_2_0(Wym_imag_2_0), + .q_2_1(Wym_imag_2_1), + .q_2_2(Wym_imag_2_2), + .q_2_3(Wym_imag_2_3), + .q_2_4(Wym_imag_2_4), + .q_2_5(Wym_imag_2_5), + .q_2_6(Wym_imag_2_6), + .q_2_7(Wym_imag_2_7), + .q_2_8(Wym_imag_2_8), + .index(weight_index) +); + +endmodule + +module counter_31_3 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd3) <= 31) begin + count <= count + 14'd3; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module weight_buffer_18_9_3_64_2048_Wym_real_half_0 ( + input clk, + input rst, + input [161:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_2_0, + output [17:0] q_2_1, + output [17:0] q_2_2, + output [17:0] q_2_3, + output [17:0] q_2_4, + output [17:0] q_2_5, + output [17:0] q_2_6, + output [17:0] q_2_7, + output [17:0] q_2_8, + input [10:0] index +); + +wire [161:0] packed_result_0; +reg [10:0] addrs_0; +reg [10:0] addrs_base_0; +wire [161:0] packed_result_1; +reg [10:0] addrs_1; +reg [10:0] addrs_base_1; +wire [161:0] packed_result_2; +reg [10:0] addrs_2; +reg [10:0] addrs_base_2; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 64; + addrs_base_2 <= 128; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + addrs_2 <= index + addrs_base_2; + end +end + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_2 ( + .we(wen), + .addr(addrs_2), + .data(wdata), + .out(packed_result_2), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_2_0 = packed_result_2[17:0]; +assign q_2_1 = packed_result_2[35:18]; +assign q_2_2 = packed_result_2[53:36]; +assign q_2_3 = packed_result_2[71:54]; +assign q_2_4 = packed_result_2[89:72]; +assign q_2_5 = packed_result_2[107:90]; +assign q_2_6 = packed_result_2[125:108]; +assign q_2_7 = packed_result_2[143:126]; +assign q_2_8 = packed_result_2[161:144]; + +endmodule + +module weight_buffer_18_9_3_64_2048_Wym_imag_half_0 ( + input clk, + input rst, + input [161:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_2_0, + output [17:0] q_2_1, + output [17:0] q_2_2, + output [17:0] q_2_3, + output [17:0] q_2_4, + output [17:0] q_2_5, + output [17:0] q_2_6, + output [17:0] q_2_7, + output [17:0] q_2_8, + input [10:0] index +); + +wire [161:0] packed_result_0; +reg [10:0] addrs_0; +reg [10:0] addrs_base_0; +wire [161:0] packed_result_1; +reg [10:0] addrs_1; +reg [10:0] addrs_base_1; +wire [161:0] packed_result_2; +reg [10:0] addrs_2; +reg [10:0] addrs_base_2; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 64; + addrs_base_2 <= 128; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + addrs_2 <= index + addrs_base_2; + end +end + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_2 ( + .we(wen), + .addr(addrs_2), + .data(wdata), + .out(packed_result_2), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_2_0 = packed_result_2[17:0]; +assign q_2_1 = packed_result_2[35:18]; +assign q_2_2 = packed_result_2[53:36]; +assign q_2_3 = packed_result_2[71:54]; +assign q_2_4 = packed_result_2[89:72]; +assign q_2_5 = packed_result_2[107:90]; +assign q_2_6 = packed_result_2[125:108]; +assign q_2_7 = packed_result_2[143:126]; +assign q_2_8 = packed_result_2[161:144]; + +endmodule + +module multiple_c_matrix_vec_mult_and_sum_18_10_16_1_3_64 ( + input clk, + input reset, + input i_ready, + input i_valid, + input [17:0] i_X_0, + input [17:0] i_X_1, + input [17:0] i_X_2, + input [17:0] i_X_3, + input [17:0] i_X_4, + input [17:0] i_X_5, + input [17:0] i_X_6, + input [17:0] i_X_7, + input [17:0] i_X_8, + input [17:0] i_X_9, + input [17:0] i_X_10, + input [17:0] i_X_11, + input [17:0] i_X_12, + input [17:0] i_X_13, + input [17:0] i_X_14, + input [17:0] i_X_15, + input [17:0] i_W_real_0_0, + input [17:0] i_W_imag_0_0, + input [17:0] i_W_real_0_1, + input [17:0] i_W_imag_0_1, + input [17:0] i_W_real_0_2, + input [17:0] i_W_imag_0_2, + input [17:0] i_W_real_0_3, + input [17:0] i_W_imag_0_3, + input [17:0] i_W_real_0_4, + input [17:0] i_W_imag_0_4, + input [17:0] i_W_real_0_5, + input [17:0] i_W_imag_0_5, + input [17:0] i_W_real_0_6, + input [17:0] i_W_imag_0_6, + input [17:0] i_W_real_0_7, + input [17:0] i_W_imag_0_7, + input [17:0] i_W_real_0_8, + input [17:0] i_W_imag_0_8, + input [17:0] i_W_real_1_0, + input [17:0] i_W_imag_1_0, + input [17:0] i_W_real_1_1, + input [17:0] i_W_imag_1_1, + input [17:0] i_W_real_1_2, + input [17:0] i_W_imag_1_2, + input [17:0] i_W_real_1_3, + input [17:0] i_W_imag_1_3, + input [17:0] i_W_real_1_4, + input [17:0] i_W_imag_1_4, + input [17:0] i_W_real_1_5, + input [17:0] i_W_imag_1_5, + input [17:0] i_W_real_1_6, + input [17:0] i_W_imag_1_6, + input [17:0] i_W_real_1_7, + input [17:0] i_W_imag_1_7, + input [17:0] i_W_real_1_8, + input [17:0] i_W_imag_1_8, + input [17:0] i_W_real_2_0, + input [17:0] i_W_imag_2_0, + input [17:0] i_W_real_2_1, + input [17:0] i_W_imag_2_1, + input [17:0] i_W_real_2_2, + input [17:0] i_W_imag_2_2, + input [17:0] i_W_real_2_3, + input [17:0] i_W_imag_2_3, + input [17:0] i_W_real_2_4, + input [17:0] i_W_imag_2_4, + input [17:0] i_W_real_2_5, + input [17:0] i_W_imag_2_5, + input [17:0] i_W_real_2_6, + input [17:0] i_W_imag_2_6, + input [17:0] i_W_real_2_7, + input [17:0] i_W_imag_2_7, + input [17:0] i_W_real_2_8, + input [17:0] i_W_imag_2_8, + output [17:0] o_Y_0_0, + output [17:0] o_Y_0_1, + output [17:0] o_Y_0_2, + output [17:0] o_Y_0_3, + output [17:0] o_Y_0_4, + output [17:0] o_Y_0_5, + output [17:0] o_Y_0_6, + output [17:0] o_Y_0_7, + output [17:0] o_Y_0_8, + output [17:0] o_Y_0_9, + output [17:0] o_Y_0_10, + output [17:0] o_Y_0_11, + output [17:0] o_Y_0_12, + output [17:0] o_Y_0_13, + output [17:0] o_Y_0_14, + output [17:0] o_Y_0_15, + output [17:0] o_Y_1_0, + output [17:0] o_Y_1_1, + output [17:0] o_Y_1_2, + output [17:0] o_Y_1_3, + output [17:0] o_Y_1_4, + output [17:0] o_Y_1_5, + output [17:0] o_Y_1_6, + output [17:0] o_Y_1_7, + output [17:0] o_Y_1_8, + output [17:0] o_Y_1_9, + output [17:0] o_Y_1_10, + output [17:0] o_Y_1_11, + output [17:0] o_Y_1_12, + output [17:0] o_Y_1_13, + output [17:0] o_Y_1_14, + output [17:0] o_Y_1_15, + output [17:0] o_Y_2_0, + output [17:0] o_Y_2_1, + output [17:0] o_Y_2_2, + output [17:0] o_Y_2_3, + output [17:0] o_Y_2_4, + output [17:0] o_Y_2_5, + output [17:0] o_Y_2_6, + output [17:0] o_Y_2_7, + output [17:0] o_Y_2_8, + output [17:0] o_Y_2_9, + output [17:0] o_Y_2_10, + output [17:0] o_Y_2_11, + output [17:0] o_Y_2_12, + output [17:0] o_Y_2_13, + output [17:0] o_Y_2_14, + output [17:0] o_Y_2_15, + output o_valid, + output o_ready +); + +wire matrix_vec_mult_ready, matrix_vec_mult_valid; +wire accum_valid_0; +wire idft_next_out_0; +wire accum_valid_1; +wire idft_next_out_1; +wire accum_valid_2; +wire idft_next_out_2; +reg idft_out_valid; +wire [17:0] Y_imag_0_0; +wire [17:0] Y_real_0_0; +wire [17:0] sum_Y_real_0_0; +wire [17:0] sum_Y_imag_0_0; +wire [17:0] sum_Y_real_hold_0_0; +wire [17:0] sum_Y_imag_hold_0_0; +wire [17:0] out_Y_idft_0_0; +reg [17:0] reg_Y_0_0; +wire [17:0] Y_imag_0_1; +wire [17:0] Y_real_0_1; +wire [17:0] sum_Y_real_0_1; +wire [17:0] sum_Y_imag_0_1; +wire [17:0] sum_Y_real_hold_0_1; +wire [17:0] sum_Y_imag_hold_0_1; +wire [17:0] out_Y_idft_0_1; +reg [17:0] reg_Y_0_1; +wire [17:0] Y_imag_0_2; +wire [17:0] Y_real_0_2; +wire [17:0] sum_Y_real_0_2; +wire [17:0] sum_Y_imag_0_2; +wire [17:0] sum_Y_real_hold_0_2; +wire [17:0] sum_Y_imag_hold_0_2; +wire [17:0] out_Y_idft_0_2; +reg [17:0] reg_Y_0_2; +wire [17:0] Y_imag_0_3; +wire [17:0] Y_real_0_3; +wire [17:0] sum_Y_real_0_3; +wire [17:0] sum_Y_imag_0_3; +wire [17:0] sum_Y_real_hold_0_3; +wire [17:0] sum_Y_imag_hold_0_3; +wire [17:0] out_Y_idft_0_3; +reg [17:0] reg_Y_0_3; +wire [17:0] Y_imag_0_4; +wire [17:0] Y_real_0_4; +wire [17:0] sum_Y_real_0_4; +wire [17:0] sum_Y_imag_0_4; +wire [17:0] sum_Y_real_hold_0_4; +wire [17:0] sum_Y_imag_hold_0_4; +wire [17:0] out_Y_idft_0_4; +reg [17:0] reg_Y_0_4; +wire [17:0] Y_imag_0_5; +wire [17:0] Y_real_0_5; +wire [17:0] sum_Y_real_0_5; +wire [17:0] sum_Y_imag_0_5; +wire [17:0] sum_Y_real_hold_0_5; +wire [17:0] sum_Y_imag_hold_0_5; +wire [17:0] out_Y_idft_0_5; +reg [17:0] reg_Y_0_5; +wire [17:0] Y_imag_0_6; +wire [17:0] Y_real_0_6; +wire [17:0] sum_Y_real_0_6; +wire [17:0] sum_Y_imag_0_6; +wire [17:0] sum_Y_real_hold_0_6; +wire [17:0] sum_Y_imag_hold_0_6; +wire [17:0] out_Y_idft_0_6; +reg [17:0] reg_Y_0_6; +wire [17:0] Y_imag_0_7; +wire [17:0] Y_real_0_7; +wire [17:0] sum_Y_real_0_7; +wire [17:0] sum_Y_imag_0_7; +wire [17:0] sum_Y_real_hold_0_7; +wire [17:0] sum_Y_imag_hold_0_7; +wire [17:0] out_Y_idft_0_7; +reg [17:0] reg_Y_0_7; +wire [17:0] Y_imag_0_8; +wire [17:0] Y_real_0_8; +wire [17:0] sum_Y_real_0_8; +wire [17:0] sum_Y_imag_0_8; +wire [17:0] sum_Y_real_hold_0_8; +wire [17:0] sum_Y_imag_hold_0_8; +wire [17:0] out_Y_idft_0_8; +reg [17:0] reg_Y_0_8; +wire [17:0] Y_imag_0_9; +wire [17:0] Y_real_0_9; +wire [17:0] sum_Y_real_0_9; +wire [17:0] sum_Y_imag_0_9; +wire [17:0] sum_Y_real_hold_0_9; +wire [17:0] sum_Y_imag_hold_0_9; +wire [17:0] out_Y_idft_0_9; +reg [17:0] reg_Y_0_9; +wire [17:0] Y_imag_0_10; +wire [17:0] Y_real_0_10; +wire [17:0] sum_Y_real_0_10; +wire [17:0] sum_Y_imag_0_10; +wire [17:0] sum_Y_real_hold_0_10; +wire [17:0] sum_Y_imag_hold_0_10; +wire [17:0] out_Y_idft_0_10; +reg [17:0] reg_Y_0_10; +wire [17:0] Y_imag_0_11; +wire [17:0] Y_real_0_11; +wire [17:0] sum_Y_real_0_11; +wire [17:0] sum_Y_imag_0_11; +wire [17:0] sum_Y_real_hold_0_11; +wire [17:0] sum_Y_imag_hold_0_11; +wire [17:0] out_Y_idft_0_11; +reg [17:0] reg_Y_0_11; +wire [17:0] Y_imag_0_12; +wire [17:0] Y_real_0_12; +wire [17:0] sum_Y_real_0_12; +wire [17:0] sum_Y_imag_0_12; +wire [17:0] sum_Y_real_hold_0_12; +wire [17:0] sum_Y_imag_hold_0_12; +wire [17:0] out_Y_idft_0_12; +reg [17:0] reg_Y_0_12; +wire [17:0] Y_imag_0_13; +wire [17:0] Y_real_0_13; +wire [17:0] sum_Y_real_0_13; +wire [17:0] sum_Y_imag_0_13; +wire [17:0] sum_Y_real_hold_0_13; +wire [17:0] sum_Y_imag_hold_0_13; +wire [17:0] out_Y_idft_0_13; +reg [17:0] reg_Y_0_13; +wire [17:0] Y_imag_0_14; +wire [17:0] Y_real_0_14; +wire [17:0] sum_Y_real_0_14; +wire [17:0] sum_Y_imag_0_14; +wire [17:0] sum_Y_real_hold_0_14; +wire [17:0] sum_Y_imag_hold_0_14; +wire [17:0] out_Y_idft_0_14; +reg [17:0] reg_Y_0_14; +wire [17:0] Y_imag_0_15; +wire [17:0] Y_real_0_15; +wire [17:0] sum_Y_real_0_15; +wire [17:0] sum_Y_imag_0_15; +wire [17:0] sum_Y_real_hold_0_15; +wire [17:0] sum_Y_imag_hold_0_15; +wire [17:0] out_Y_idft_0_15; +reg [17:0] reg_Y_0_15; +wire [17:0] Y_imag_1_0; +wire [17:0] Y_real_1_0; +wire [17:0] sum_Y_real_1_0; +wire [17:0] sum_Y_imag_1_0; +wire [17:0] sum_Y_real_hold_1_0; +wire [17:0] sum_Y_imag_hold_1_0; +wire [17:0] out_Y_idft_1_0; +reg [17:0] reg_Y_1_0; +wire [17:0] Y_imag_1_1; +wire [17:0] Y_real_1_1; +wire [17:0] sum_Y_real_1_1; +wire [17:0] sum_Y_imag_1_1; +wire [17:0] sum_Y_real_hold_1_1; +wire [17:0] sum_Y_imag_hold_1_1; +wire [17:0] out_Y_idft_1_1; +reg [17:0] reg_Y_1_1; +wire [17:0] Y_imag_1_2; +wire [17:0] Y_real_1_2; +wire [17:0] sum_Y_real_1_2; +wire [17:0] sum_Y_imag_1_2; +wire [17:0] sum_Y_real_hold_1_2; +wire [17:0] sum_Y_imag_hold_1_2; +wire [17:0] out_Y_idft_1_2; +reg [17:0] reg_Y_1_2; +wire [17:0] Y_imag_1_3; +wire [17:0] Y_real_1_3; +wire [17:0] sum_Y_real_1_3; +wire [17:0] sum_Y_imag_1_3; +wire [17:0] sum_Y_real_hold_1_3; +wire [17:0] sum_Y_imag_hold_1_3; +wire [17:0] out_Y_idft_1_3; +reg [17:0] reg_Y_1_3; +wire [17:0] Y_imag_1_4; +wire [17:0] Y_real_1_4; +wire [17:0] sum_Y_real_1_4; +wire [17:0] sum_Y_imag_1_4; +wire [17:0] sum_Y_real_hold_1_4; +wire [17:0] sum_Y_imag_hold_1_4; +wire [17:0] out_Y_idft_1_4; +reg [17:0] reg_Y_1_4; +wire [17:0] Y_imag_1_5; +wire [17:0] Y_real_1_5; +wire [17:0] sum_Y_real_1_5; +wire [17:0] sum_Y_imag_1_5; +wire [17:0] sum_Y_real_hold_1_5; +wire [17:0] sum_Y_imag_hold_1_5; +wire [17:0] out_Y_idft_1_5; +reg [17:0] reg_Y_1_5; +wire [17:0] Y_imag_1_6; +wire [17:0] Y_real_1_6; +wire [17:0] sum_Y_real_1_6; +wire [17:0] sum_Y_imag_1_6; +wire [17:0] sum_Y_real_hold_1_6; +wire [17:0] sum_Y_imag_hold_1_6; +wire [17:0] out_Y_idft_1_6; +reg [17:0] reg_Y_1_6; +wire [17:0] Y_imag_1_7; +wire [17:0] Y_real_1_7; +wire [17:0] sum_Y_real_1_7; +wire [17:0] sum_Y_imag_1_7; +wire [17:0] sum_Y_real_hold_1_7; +wire [17:0] sum_Y_imag_hold_1_7; +wire [17:0] out_Y_idft_1_7; +reg [17:0] reg_Y_1_7; +wire [17:0] Y_imag_1_8; +wire [17:0] Y_real_1_8; +wire [17:0] sum_Y_real_1_8; +wire [17:0] sum_Y_imag_1_8; +wire [17:0] sum_Y_real_hold_1_8; +wire [17:0] sum_Y_imag_hold_1_8; +wire [17:0] out_Y_idft_1_8; +reg [17:0] reg_Y_1_8; +wire [17:0] Y_imag_1_9; +wire [17:0] Y_real_1_9; +wire [17:0] sum_Y_real_1_9; +wire [17:0] sum_Y_imag_1_9; +wire [17:0] sum_Y_real_hold_1_9; +wire [17:0] sum_Y_imag_hold_1_9; +wire [17:0] out_Y_idft_1_9; +reg [17:0] reg_Y_1_9; +wire [17:0] Y_imag_1_10; +wire [17:0] Y_real_1_10; +wire [17:0] sum_Y_real_1_10; +wire [17:0] sum_Y_imag_1_10; +wire [17:0] sum_Y_real_hold_1_10; +wire [17:0] sum_Y_imag_hold_1_10; +wire [17:0] out_Y_idft_1_10; +reg [17:0] reg_Y_1_10; +wire [17:0] Y_imag_1_11; +wire [17:0] Y_real_1_11; +wire [17:0] sum_Y_real_1_11; +wire [17:0] sum_Y_imag_1_11; +wire [17:0] sum_Y_real_hold_1_11; +wire [17:0] sum_Y_imag_hold_1_11; +wire [17:0] out_Y_idft_1_11; +reg [17:0] reg_Y_1_11; +wire [17:0] Y_imag_1_12; +wire [17:0] Y_real_1_12; +wire [17:0] sum_Y_real_1_12; +wire [17:0] sum_Y_imag_1_12; +wire [17:0] sum_Y_real_hold_1_12; +wire [17:0] sum_Y_imag_hold_1_12; +wire [17:0] out_Y_idft_1_12; +reg [17:0] reg_Y_1_12; +wire [17:0] Y_imag_1_13; +wire [17:0] Y_real_1_13; +wire [17:0] sum_Y_real_1_13; +wire [17:0] sum_Y_imag_1_13; +wire [17:0] sum_Y_real_hold_1_13; +wire [17:0] sum_Y_imag_hold_1_13; +wire [17:0] out_Y_idft_1_13; +reg [17:0] reg_Y_1_13; +wire [17:0] Y_imag_1_14; +wire [17:0] Y_real_1_14; +wire [17:0] sum_Y_real_1_14; +wire [17:0] sum_Y_imag_1_14; +wire [17:0] sum_Y_real_hold_1_14; +wire [17:0] sum_Y_imag_hold_1_14; +wire [17:0] out_Y_idft_1_14; +reg [17:0] reg_Y_1_14; +wire [17:0] Y_imag_1_15; +wire [17:0] Y_real_1_15; +wire [17:0] sum_Y_real_1_15; +wire [17:0] sum_Y_imag_1_15; +wire [17:0] sum_Y_real_hold_1_15; +wire [17:0] sum_Y_imag_hold_1_15; +wire [17:0] out_Y_idft_1_15; +reg [17:0] reg_Y_1_15; +wire [17:0] Y_imag_2_0; +wire [17:0] Y_real_2_0; +wire [17:0] sum_Y_real_2_0; +wire [17:0] sum_Y_imag_2_0; +wire [17:0] sum_Y_real_hold_2_0; +wire [17:0] sum_Y_imag_hold_2_0; +wire [17:0] out_Y_idft_2_0; +reg [17:0] reg_Y_2_0; +wire [17:0] Y_imag_2_1; +wire [17:0] Y_real_2_1; +wire [17:0] sum_Y_real_2_1; +wire [17:0] sum_Y_imag_2_1; +wire [17:0] sum_Y_real_hold_2_1; +wire [17:0] sum_Y_imag_hold_2_1; +wire [17:0] out_Y_idft_2_1; +reg [17:0] reg_Y_2_1; +wire [17:0] Y_imag_2_2; +wire [17:0] Y_real_2_2; +wire [17:0] sum_Y_real_2_2; +wire [17:0] sum_Y_imag_2_2; +wire [17:0] sum_Y_real_hold_2_2; +wire [17:0] sum_Y_imag_hold_2_2; +wire [17:0] out_Y_idft_2_2; +reg [17:0] reg_Y_2_2; +wire [17:0] Y_imag_2_3; +wire [17:0] Y_real_2_3; +wire [17:0] sum_Y_real_2_3; +wire [17:0] sum_Y_imag_2_3; +wire [17:0] sum_Y_real_hold_2_3; +wire [17:0] sum_Y_imag_hold_2_3; +wire [17:0] out_Y_idft_2_3; +reg [17:0] reg_Y_2_3; +wire [17:0] Y_imag_2_4; +wire [17:0] Y_real_2_4; +wire [17:0] sum_Y_real_2_4; +wire [17:0] sum_Y_imag_2_4; +wire [17:0] sum_Y_real_hold_2_4; +wire [17:0] sum_Y_imag_hold_2_4; +wire [17:0] out_Y_idft_2_4; +reg [17:0] reg_Y_2_4; +wire [17:0] Y_imag_2_5; +wire [17:0] Y_real_2_5; +wire [17:0] sum_Y_real_2_5; +wire [17:0] sum_Y_imag_2_5; +wire [17:0] sum_Y_real_hold_2_5; +wire [17:0] sum_Y_imag_hold_2_5; +wire [17:0] out_Y_idft_2_5; +reg [17:0] reg_Y_2_5; +wire [17:0] Y_imag_2_6; +wire [17:0] Y_real_2_6; +wire [17:0] sum_Y_real_2_6; +wire [17:0] sum_Y_imag_2_6; +wire [17:0] sum_Y_real_hold_2_6; +wire [17:0] sum_Y_imag_hold_2_6; +wire [17:0] out_Y_idft_2_6; +reg [17:0] reg_Y_2_6; +wire [17:0] Y_imag_2_7; +wire [17:0] Y_real_2_7; +wire [17:0] sum_Y_real_2_7; +wire [17:0] sum_Y_imag_2_7; +wire [17:0] sum_Y_real_hold_2_7; +wire [17:0] sum_Y_imag_hold_2_7; +wire [17:0] out_Y_idft_2_7; +reg [17:0] reg_Y_2_7; +wire [17:0] Y_imag_2_8; +wire [17:0] Y_real_2_8; +wire [17:0] sum_Y_real_2_8; +wire [17:0] sum_Y_imag_2_8; +wire [17:0] sum_Y_real_hold_2_8; +wire [17:0] sum_Y_imag_hold_2_8; +wire [17:0] out_Y_idft_2_8; +reg [17:0] reg_Y_2_8; +wire [17:0] Y_imag_2_9; +wire [17:0] Y_real_2_9; +wire [17:0] sum_Y_real_2_9; +wire [17:0] sum_Y_imag_2_9; +wire [17:0] sum_Y_real_hold_2_9; +wire [17:0] sum_Y_imag_hold_2_9; +wire [17:0] out_Y_idft_2_9; +reg [17:0] reg_Y_2_9; +wire [17:0] Y_imag_2_10; +wire [17:0] Y_real_2_10; +wire [17:0] sum_Y_real_2_10; +wire [17:0] sum_Y_imag_2_10; +wire [17:0] sum_Y_real_hold_2_10; +wire [17:0] sum_Y_imag_hold_2_10; +wire [17:0] out_Y_idft_2_10; +reg [17:0] reg_Y_2_10; +wire [17:0] Y_imag_2_11; +wire [17:0] Y_real_2_11; +wire [17:0] sum_Y_real_2_11; +wire [17:0] sum_Y_imag_2_11; +wire [17:0] sum_Y_real_hold_2_11; +wire [17:0] sum_Y_imag_hold_2_11; +wire [17:0] out_Y_idft_2_11; +reg [17:0] reg_Y_2_11; +wire [17:0] Y_imag_2_12; +wire [17:0] Y_real_2_12; +wire [17:0] sum_Y_real_2_12; +wire [17:0] sum_Y_imag_2_12; +wire [17:0] sum_Y_real_hold_2_12; +wire [17:0] sum_Y_imag_hold_2_12; +wire [17:0] out_Y_idft_2_12; +reg [17:0] reg_Y_2_12; +wire [17:0] Y_imag_2_13; +wire [17:0] Y_real_2_13; +wire [17:0] sum_Y_real_2_13; +wire [17:0] sum_Y_imag_2_13; +wire [17:0] sum_Y_real_hold_2_13; +wire [17:0] sum_Y_imag_hold_2_13; +wire [17:0] out_Y_idft_2_13; +reg [17:0] reg_Y_2_13; +wire [17:0] Y_imag_2_14; +wire [17:0] Y_real_2_14; +wire [17:0] sum_Y_real_2_14; +wire [17:0] sum_Y_imag_2_14; +wire [17:0] sum_Y_real_hold_2_14; +wire [17:0] sum_Y_imag_hold_2_14; +wire [17:0] out_Y_idft_2_14; +reg [17:0] reg_Y_2_14; +wire [17:0] Y_imag_2_15; +wire [17:0] Y_real_2_15; +wire [17:0] sum_Y_real_2_15; +wire [17:0] sum_Y_imag_2_15; +wire [17:0] sum_Y_real_hold_2_15; +wire [17:0] sum_Y_imag_hold_2_15; +wire [17:0] out_Y_idft_2_15; +reg [17:0] reg_Y_2_15; +reg reg_o_valid; + +// Enable whenever the reciever is ready +wire enable; +assign enable = i_ready; +c_matrix_vec_mult_core_18_10_16_3_1 c_matrix_vec_mult_core_18_10_16_3_1_inst_riaxdnjetr ( + .clk(clk), + .reset(reset), + .i_ready(i_ready), + .i_valid(i_valid), + .i_X_0(i_X_0), + .i_X_1(i_X_1), + .i_X_2(i_X_2), + .i_X_3(i_X_3), + .i_X_4(i_X_4), + .i_X_5(i_X_5), + .i_X_6(i_X_6), + .i_X_7(i_X_7), + .i_X_8(i_X_8), + .i_X_9(i_X_9), + .i_X_10(i_X_10), + .i_X_11(i_X_11), + .i_X_12(i_X_12), + .i_X_13(i_X_13), + .i_X_14(i_X_14), + .i_X_15(i_X_15), + .i_W_real_0_0(i_W_real_0_0), + .i_W_imag_0_0(i_W_imag_0_0), + .i_W_real_0_1(i_W_real_0_1), + .i_W_imag_0_1(i_W_imag_0_1), + .i_W_real_0_2(i_W_real_0_2), + .i_W_imag_0_2(i_W_imag_0_2), + .i_W_real_0_3(i_W_real_0_3), + .i_W_imag_0_3(i_W_imag_0_3), + .i_W_real_0_4(i_W_real_0_4), + .i_W_imag_0_4(i_W_imag_0_4), + .i_W_real_0_5(i_W_real_0_5), + .i_W_imag_0_5(i_W_imag_0_5), + .i_W_real_0_6(i_W_real_0_6), + .i_W_imag_0_6(i_W_imag_0_6), + .i_W_real_0_7(i_W_real_0_7), + .i_W_imag_0_7(i_W_imag_0_7), + .i_W_real_0_8(i_W_real_0_8), + .i_W_imag_0_8(i_W_imag_0_8), + .i_W_real_1_0(i_W_real_1_0), + .i_W_imag_1_0(i_W_imag_1_0), + .i_W_real_1_1(i_W_real_1_1), + .i_W_imag_1_1(i_W_imag_1_1), + .i_W_real_1_2(i_W_real_1_2), + .i_W_imag_1_2(i_W_imag_1_2), + .i_W_real_1_3(i_W_real_1_3), + .i_W_imag_1_3(i_W_imag_1_3), + .i_W_real_1_4(i_W_real_1_4), + .i_W_imag_1_4(i_W_imag_1_4), + .i_W_real_1_5(i_W_real_1_5), + .i_W_imag_1_5(i_W_imag_1_5), + .i_W_real_1_6(i_W_real_1_6), + .i_W_imag_1_6(i_W_imag_1_6), + .i_W_real_1_7(i_W_real_1_7), + .i_W_imag_1_7(i_W_imag_1_7), + .i_W_real_1_8(i_W_real_1_8), + .i_W_imag_1_8(i_W_imag_1_8), + .i_W_real_2_0(i_W_real_2_0), + .i_W_imag_2_0(i_W_imag_2_0), + .i_W_real_2_1(i_W_real_2_1), + .i_W_imag_2_1(i_W_imag_2_1), + .i_W_real_2_2(i_W_real_2_2), + .i_W_imag_2_2(i_W_imag_2_2), + .i_W_real_2_3(i_W_real_2_3), + .i_W_imag_2_3(i_W_imag_2_3), + .i_W_real_2_4(i_W_real_2_4), + .i_W_imag_2_4(i_W_imag_2_4), + .i_W_real_2_5(i_W_real_2_5), + .i_W_imag_2_5(i_W_imag_2_5), + .i_W_real_2_6(i_W_real_2_6), + .i_W_imag_2_6(i_W_imag_2_6), + .i_W_real_2_7(i_W_real_2_7), + .i_W_imag_2_7(i_W_imag_2_7), + .i_W_real_2_8(i_W_real_2_8), + .i_W_imag_2_8(i_W_imag_2_8), + .o_Y_real_0_0(Y_real_0_0), + .o_Y_imag_0_0(Y_imag_0_0), + .o_Y_real_0_1(Y_real_0_1), + .o_Y_imag_0_1(Y_imag_0_1), + .o_Y_real_0_2(Y_real_0_2), + .o_Y_imag_0_2(Y_imag_0_2), + .o_Y_real_0_3(Y_real_0_3), + .o_Y_imag_0_3(Y_imag_0_3), + .o_Y_real_0_4(Y_real_0_4), + .o_Y_imag_0_4(Y_imag_0_4), + .o_Y_real_0_5(Y_real_0_5), + .o_Y_imag_0_5(Y_imag_0_5), + .o_Y_real_0_6(Y_real_0_6), + .o_Y_imag_0_6(Y_imag_0_6), + .o_Y_real_0_7(Y_real_0_7), + .o_Y_imag_0_7(Y_imag_0_7), + .o_Y_real_0_8(Y_real_0_8), + .o_Y_imag_0_8(Y_imag_0_8), + .o_Y_real_0_9(Y_real_0_9), + .o_Y_imag_0_9(Y_imag_0_9), + .o_Y_real_0_10(Y_real_0_10), + .o_Y_imag_0_10(Y_imag_0_10), + .o_Y_real_0_11(Y_real_0_11), + .o_Y_imag_0_11(Y_imag_0_11), + .o_Y_real_0_12(Y_real_0_12), + .o_Y_imag_0_12(Y_imag_0_12), + .o_Y_real_0_13(Y_real_0_13), + .o_Y_imag_0_13(Y_imag_0_13), + .o_Y_real_0_14(Y_real_0_14), + .o_Y_imag_0_14(Y_imag_0_14), + .o_Y_real_0_15(Y_real_0_15), + .o_Y_imag_0_15(Y_imag_0_15), + .o_Y_real_1_0(Y_real_1_0), + .o_Y_imag_1_0(Y_imag_1_0), + .o_Y_real_1_1(Y_real_1_1), + .o_Y_imag_1_1(Y_imag_1_1), + .o_Y_real_1_2(Y_real_1_2), + .o_Y_imag_1_2(Y_imag_1_2), + .o_Y_real_1_3(Y_real_1_3), + .o_Y_imag_1_3(Y_imag_1_3), + .o_Y_real_1_4(Y_real_1_4), + .o_Y_imag_1_4(Y_imag_1_4), + .o_Y_real_1_5(Y_real_1_5), + .o_Y_imag_1_5(Y_imag_1_5), + .o_Y_real_1_6(Y_real_1_6), + .o_Y_imag_1_6(Y_imag_1_6), + .o_Y_real_1_7(Y_real_1_7), + .o_Y_imag_1_7(Y_imag_1_7), + .o_Y_real_1_8(Y_real_1_8), + .o_Y_imag_1_8(Y_imag_1_8), + .o_Y_real_1_9(Y_real_1_9), + .o_Y_imag_1_9(Y_imag_1_9), + .o_Y_real_1_10(Y_real_1_10), + .o_Y_imag_1_10(Y_imag_1_10), + .o_Y_real_1_11(Y_real_1_11), + .o_Y_imag_1_11(Y_imag_1_11), + .o_Y_real_1_12(Y_real_1_12), + .o_Y_imag_1_12(Y_imag_1_12), + .o_Y_real_1_13(Y_real_1_13), + .o_Y_imag_1_13(Y_imag_1_13), + .o_Y_real_1_14(Y_real_1_14), + .o_Y_imag_1_14(Y_imag_1_14), + .o_Y_real_1_15(Y_real_1_15), + .o_Y_imag_1_15(Y_imag_1_15), + .o_Y_real_2_0(Y_real_2_0), + .o_Y_imag_2_0(Y_imag_2_0), + .o_Y_real_2_1(Y_real_2_1), + .o_Y_imag_2_1(Y_imag_2_1), + .o_Y_real_2_2(Y_real_2_2), + .o_Y_imag_2_2(Y_imag_2_2), + .o_Y_real_2_3(Y_real_2_3), + .o_Y_imag_2_3(Y_imag_2_3), + .o_Y_real_2_4(Y_real_2_4), + .o_Y_imag_2_4(Y_imag_2_4), + .o_Y_real_2_5(Y_real_2_5), + .o_Y_imag_2_5(Y_imag_2_5), + .o_Y_real_2_6(Y_real_2_6), + .o_Y_imag_2_6(Y_imag_2_6), + .o_Y_real_2_7(Y_real_2_7), + .o_Y_imag_2_7(Y_imag_2_7), + .o_Y_real_2_8(Y_real_2_8), + .o_Y_imag_2_8(Y_imag_2_8), + .o_Y_real_2_9(Y_real_2_9), + .o_Y_imag_2_9(Y_imag_2_9), + .o_Y_real_2_10(Y_real_2_10), + .o_Y_imag_2_10(Y_imag_2_10), + .o_Y_real_2_11(Y_real_2_11), + .o_Y_imag_2_11(Y_imag_2_11), + .o_Y_real_2_12(Y_real_2_12), + .o_Y_imag_2_12(Y_imag_2_12), + .o_Y_real_2_13(Y_real_2_13), + .o_Y_imag_2_13(Y_imag_2_13), + .o_Y_real_2_14(Y_real_2_14), + .o_Y_imag_2_14(Y_imag_2_14), + .o_Y_real_2_15(Y_real_2_15), + .o_Y_imag_2_15(Y_imag_2_15), + .o_ready(matrix_vec_mult_ready), + .o_valid(matrix_vec_mult_valid) +); + +sum_complex_vector_unit_18_18_16_64 sum_complex_vector_unit_18_18_16_64_inst_xeplqcwkms ( + .clk(clk), + .clr(reset), + .enable(enable), + .i_valid(matrix_vec_mult_valid), + .i_real_0(Y_real_0_0), + .i_imag_0(Y_imag_0_0), + .o_real_0(sum_Y_real_0_0), + .o_imag_0(sum_Y_imag_0_0), + .i_real_1(Y_real_0_1), + .i_imag_1(Y_imag_0_1), + .o_real_1(sum_Y_real_0_1), + .o_imag_1(sum_Y_imag_0_1), + .i_real_2(Y_real_0_2), + .i_imag_2(Y_imag_0_2), + .o_real_2(sum_Y_real_0_2), + .o_imag_2(sum_Y_imag_0_2), + .i_real_3(Y_real_0_3), + .i_imag_3(Y_imag_0_3), + .o_real_3(sum_Y_real_0_3), + .o_imag_3(sum_Y_imag_0_3), + .i_real_4(Y_real_0_4), + .i_imag_4(Y_imag_0_4), + .o_real_4(sum_Y_real_0_4), + .o_imag_4(sum_Y_imag_0_4), + .i_real_5(Y_real_0_5), + .i_imag_5(Y_imag_0_5), + .o_real_5(sum_Y_real_0_5), + .o_imag_5(sum_Y_imag_0_5), + .i_real_6(Y_real_0_6), + .i_imag_6(Y_imag_0_6), + .o_real_6(sum_Y_real_0_6), + .o_imag_6(sum_Y_imag_0_6), + .i_real_7(Y_real_0_7), + .i_imag_7(Y_imag_0_7), + .o_real_7(sum_Y_real_0_7), + .o_imag_7(sum_Y_imag_0_7), + .i_real_8(Y_real_0_8), + .i_imag_8(Y_imag_0_8), + .o_real_8(sum_Y_real_0_8), + .o_imag_8(sum_Y_imag_0_8), + .i_real_9(Y_real_0_9), + .i_imag_9(Y_imag_0_9), + .o_real_9(sum_Y_real_0_9), + .o_imag_9(sum_Y_imag_0_9), + .i_real_10(Y_real_0_10), + .i_imag_10(Y_imag_0_10), + .o_real_10(sum_Y_real_0_10), + .o_imag_10(sum_Y_imag_0_10), + .i_real_11(Y_real_0_11), + .i_imag_11(Y_imag_0_11), + .o_real_11(sum_Y_real_0_11), + .o_imag_11(sum_Y_imag_0_11), + .i_real_12(Y_real_0_12), + .i_imag_12(Y_imag_0_12), + .o_real_12(sum_Y_real_0_12), + .o_imag_12(sum_Y_imag_0_12), + .i_real_13(Y_real_0_13), + .i_imag_13(Y_imag_0_13), + .o_real_13(sum_Y_real_0_13), + .o_imag_13(sum_Y_imag_0_13), + .i_real_14(Y_real_0_14), + .i_imag_14(Y_imag_0_14), + .o_real_14(sum_Y_real_0_14), + .o_imag_14(sum_Y_imag_0_14), + .i_real_15(Y_real_0_15), + .i_imag_15(Y_imag_0_15), + .o_real_15(sum_Y_real_0_15), + .o_imag_15(sum_Y_imag_0_15), + .o_valid(accum_valid_0) +); + +sum_complex_vector_unit_18_18_16_64 sum_complex_vector_unit_18_18_16_64_inst_dzexxizude ( + .clk(clk), + .clr(reset), + .enable(enable), + .i_valid(matrix_vec_mult_valid), + .i_real_0(Y_real_1_0), + .i_imag_0(Y_imag_1_0), + .o_real_0(sum_Y_real_1_0), + .o_imag_0(sum_Y_imag_1_0), + .i_real_1(Y_real_1_1), + .i_imag_1(Y_imag_1_1), + .o_real_1(sum_Y_real_1_1), + .o_imag_1(sum_Y_imag_1_1), + .i_real_2(Y_real_1_2), + .i_imag_2(Y_imag_1_2), + .o_real_2(sum_Y_real_1_2), + .o_imag_2(sum_Y_imag_1_2), + .i_real_3(Y_real_1_3), + .i_imag_3(Y_imag_1_3), + .o_real_3(sum_Y_real_1_3), + .o_imag_3(sum_Y_imag_1_3), + .i_real_4(Y_real_1_4), + .i_imag_4(Y_imag_1_4), + .o_real_4(sum_Y_real_1_4), + .o_imag_4(sum_Y_imag_1_4), + .i_real_5(Y_real_1_5), + .i_imag_5(Y_imag_1_5), + .o_real_5(sum_Y_real_1_5), + .o_imag_5(sum_Y_imag_1_5), + .i_real_6(Y_real_1_6), + .i_imag_6(Y_imag_1_6), + .o_real_6(sum_Y_real_1_6), + .o_imag_6(sum_Y_imag_1_6), + .i_real_7(Y_real_1_7), + .i_imag_7(Y_imag_1_7), + .o_real_7(sum_Y_real_1_7), + .o_imag_7(sum_Y_imag_1_7), + .i_real_8(Y_real_1_8), + .i_imag_8(Y_imag_1_8), + .o_real_8(sum_Y_real_1_8), + .o_imag_8(sum_Y_imag_1_8), + .i_real_9(Y_real_1_9), + .i_imag_9(Y_imag_1_9), + .o_real_9(sum_Y_real_1_9), + .o_imag_9(sum_Y_imag_1_9), + .i_real_10(Y_real_1_10), + .i_imag_10(Y_imag_1_10), + .o_real_10(sum_Y_real_1_10), + .o_imag_10(sum_Y_imag_1_10), + .i_real_11(Y_real_1_11), + .i_imag_11(Y_imag_1_11), + .o_real_11(sum_Y_real_1_11), + .o_imag_11(sum_Y_imag_1_11), + .i_real_12(Y_real_1_12), + .i_imag_12(Y_imag_1_12), + .o_real_12(sum_Y_real_1_12), + .o_imag_12(sum_Y_imag_1_12), + .i_real_13(Y_real_1_13), + .i_imag_13(Y_imag_1_13), + .o_real_13(sum_Y_real_1_13), + .o_imag_13(sum_Y_imag_1_13), + .i_real_14(Y_real_1_14), + .i_imag_14(Y_imag_1_14), + .o_real_14(sum_Y_real_1_14), + .o_imag_14(sum_Y_imag_1_14), + .i_real_15(Y_real_1_15), + .i_imag_15(Y_imag_1_15), + .o_real_15(sum_Y_real_1_15), + .o_imag_15(sum_Y_imag_1_15), + .o_valid(accum_valid_1) +); + +sum_complex_vector_unit_18_18_16_64 sum_complex_vector_unit_18_18_16_64_inst_qhbttgtaye ( + .clk(clk), + .clr(reset), + .enable(enable), + .i_valid(matrix_vec_mult_valid), + .i_real_0(Y_real_2_0), + .i_imag_0(Y_imag_2_0), + .o_real_0(sum_Y_real_2_0), + .o_imag_0(sum_Y_imag_2_0), + .i_real_1(Y_real_2_1), + .i_imag_1(Y_imag_2_1), + .o_real_1(sum_Y_real_2_1), + .o_imag_1(sum_Y_imag_2_1), + .i_real_2(Y_real_2_2), + .i_imag_2(Y_imag_2_2), + .o_real_2(sum_Y_real_2_2), + .o_imag_2(sum_Y_imag_2_2), + .i_real_3(Y_real_2_3), + .i_imag_3(Y_imag_2_3), + .o_real_3(sum_Y_real_2_3), + .o_imag_3(sum_Y_imag_2_3), + .i_real_4(Y_real_2_4), + .i_imag_4(Y_imag_2_4), + .o_real_4(sum_Y_real_2_4), + .o_imag_4(sum_Y_imag_2_4), + .i_real_5(Y_real_2_5), + .i_imag_5(Y_imag_2_5), + .o_real_5(sum_Y_real_2_5), + .o_imag_5(sum_Y_imag_2_5), + .i_real_6(Y_real_2_6), + .i_imag_6(Y_imag_2_6), + .o_real_6(sum_Y_real_2_6), + .o_imag_6(sum_Y_imag_2_6), + .i_real_7(Y_real_2_7), + .i_imag_7(Y_imag_2_7), + .o_real_7(sum_Y_real_2_7), + .o_imag_7(sum_Y_imag_2_7), + .i_real_8(Y_real_2_8), + .i_imag_8(Y_imag_2_8), + .o_real_8(sum_Y_real_2_8), + .o_imag_8(sum_Y_imag_2_8), + .i_real_9(Y_real_2_9), + .i_imag_9(Y_imag_2_9), + .o_real_9(sum_Y_real_2_9), + .o_imag_9(sum_Y_imag_2_9), + .i_real_10(Y_real_2_10), + .i_imag_10(Y_imag_2_10), + .o_real_10(sum_Y_real_2_10), + .o_imag_10(sum_Y_imag_2_10), + .i_real_11(Y_real_2_11), + .i_imag_11(Y_imag_2_11), + .o_real_11(sum_Y_real_2_11), + .o_imag_11(sum_Y_imag_2_11), + .i_real_12(Y_real_2_12), + .i_imag_12(Y_imag_2_12), + .o_real_12(sum_Y_real_2_12), + .o_imag_12(sum_Y_imag_2_12), + .i_real_13(Y_real_2_13), + .i_imag_13(Y_imag_2_13), + .o_real_13(sum_Y_real_2_13), + .o_imag_13(sum_Y_imag_2_13), + .i_real_14(Y_real_2_14), + .i_imag_14(Y_imag_2_14), + .o_real_14(sum_Y_real_2_14), + .o_imag_14(sum_Y_imag_2_14), + .i_real_15(Y_real_2_15), + .i_imag_15(Y_imag_2_15), + .o_real_15(sum_Y_real_2_15), + .o_imag_15(sum_Y_imag_2_15), + .o_valid(accum_valid_2) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_dyycdczrrf_real ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_real_0_0), + .out_0(sum_Y_real_hold_0_0), + .in_1(sum_Y_real_0_1), + .out_1(sum_Y_real_hold_0_1), + .in_2(sum_Y_real_0_2), + .out_2(sum_Y_real_hold_0_2), + .in_3(sum_Y_real_0_3), + .out_3(sum_Y_real_hold_0_3), + .in_4(sum_Y_real_0_4), + .out_4(sum_Y_real_hold_0_4), + .in_5(sum_Y_real_0_5), + .out_5(sum_Y_real_hold_0_5), + .in_6(sum_Y_real_0_6), + .out_6(sum_Y_real_hold_0_6), + .in_7(sum_Y_real_0_7), + .out_7(sum_Y_real_hold_0_7), + .in_8(sum_Y_real_0_8), + .out_8(sum_Y_real_hold_0_8), + .in_9(sum_Y_real_0_9), + .out_9(sum_Y_real_hold_0_9), + .in_10(sum_Y_real_0_10), + .out_10(sum_Y_real_hold_0_10), + .in_11(sum_Y_real_0_11), + .out_11(sum_Y_real_hold_0_11), + .in_12(sum_Y_real_0_12), + .out_12(sum_Y_real_hold_0_12), + .in_13(sum_Y_real_0_13), + .out_13(sum_Y_real_hold_0_13), + .in_14(sum_Y_real_0_14), + .out_14(sum_Y_real_hold_0_14), + .in_15(sum_Y_real_0_15), + .out_15(sum_Y_real_hold_0_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_bjsanofyjj_imag ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_imag_0_0), + .out_0(sum_Y_imag_hold_0_0), + .in_1(sum_Y_imag_0_1), + .out_1(sum_Y_imag_hold_0_1), + .in_2(sum_Y_imag_0_2), + .out_2(sum_Y_imag_hold_0_2), + .in_3(sum_Y_imag_0_3), + .out_3(sum_Y_imag_hold_0_3), + .in_4(sum_Y_imag_0_4), + .out_4(sum_Y_imag_hold_0_4), + .in_5(sum_Y_imag_0_5), + .out_5(sum_Y_imag_hold_0_5), + .in_6(sum_Y_imag_0_6), + .out_6(sum_Y_imag_hold_0_6), + .in_7(sum_Y_imag_0_7), + .out_7(sum_Y_imag_hold_0_7), + .in_8(sum_Y_imag_0_8), + .out_8(sum_Y_imag_hold_0_8), + .in_9(sum_Y_imag_0_9), + .out_9(sum_Y_imag_hold_0_9), + .in_10(sum_Y_imag_0_10), + .out_10(sum_Y_imag_hold_0_10), + .in_11(sum_Y_imag_0_11), + .out_11(sum_Y_imag_hold_0_11), + .in_12(sum_Y_imag_0_12), + .out_12(sum_Y_imag_hold_0_12), + .in_13(sum_Y_imag_0_13), + .out_13(sum_Y_imag_hold_0_13), + .in_14(sum_Y_imag_0_14), + .out_14(sum_Y_imag_hold_0_14), + .in_15(sum_Y_imag_0_15), + .out_15(sum_Y_imag_hold_0_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_idsywuobhw_real ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_real_1_0), + .out_0(sum_Y_real_hold_1_0), + .in_1(sum_Y_real_1_1), + .out_1(sum_Y_real_hold_1_1), + .in_2(sum_Y_real_1_2), + .out_2(sum_Y_real_hold_1_2), + .in_3(sum_Y_real_1_3), + .out_3(sum_Y_real_hold_1_3), + .in_4(sum_Y_real_1_4), + .out_4(sum_Y_real_hold_1_4), + .in_5(sum_Y_real_1_5), + .out_5(sum_Y_real_hold_1_5), + .in_6(sum_Y_real_1_6), + .out_6(sum_Y_real_hold_1_6), + .in_7(sum_Y_real_1_7), + .out_7(sum_Y_real_hold_1_7), + .in_8(sum_Y_real_1_8), + .out_8(sum_Y_real_hold_1_8), + .in_9(sum_Y_real_1_9), + .out_9(sum_Y_real_hold_1_9), + .in_10(sum_Y_real_1_10), + .out_10(sum_Y_real_hold_1_10), + .in_11(sum_Y_real_1_11), + .out_11(sum_Y_real_hold_1_11), + .in_12(sum_Y_real_1_12), + .out_12(sum_Y_real_hold_1_12), + .in_13(sum_Y_real_1_13), + .out_13(sum_Y_real_hold_1_13), + .in_14(sum_Y_real_1_14), + .out_14(sum_Y_real_hold_1_14), + .in_15(sum_Y_real_1_15), + .out_15(sum_Y_real_hold_1_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_bjennfercu_imag ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_imag_1_0), + .out_0(sum_Y_imag_hold_1_0), + .in_1(sum_Y_imag_1_1), + .out_1(sum_Y_imag_hold_1_1), + .in_2(sum_Y_imag_1_2), + .out_2(sum_Y_imag_hold_1_2), + .in_3(sum_Y_imag_1_3), + .out_3(sum_Y_imag_hold_1_3), + .in_4(sum_Y_imag_1_4), + .out_4(sum_Y_imag_hold_1_4), + .in_5(sum_Y_imag_1_5), + .out_5(sum_Y_imag_hold_1_5), + .in_6(sum_Y_imag_1_6), + .out_6(sum_Y_imag_hold_1_6), + .in_7(sum_Y_imag_1_7), + .out_7(sum_Y_imag_hold_1_7), + .in_8(sum_Y_imag_1_8), + .out_8(sum_Y_imag_hold_1_8), + .in_9(sum_Y_imag_1_9), + .out_9(sum_Y_imag_hold_1_9), + .in_10(sum_Y_imag_1_10), + .out_10(sum_Y_imag_hold_1_10), + .in_11(sum_Y_imag_1_11), + .out_11(sum_Y_imag_hold_1_11), + .in_12(sum_Y_imag_1_12), + .out_12(sum_Y_imag_hold_1_12), + .in_13(sum_Y_imag_1_13), + .out_13(sum_Y_imag_hold_1_13), + .in_14(sum_Y_imag_1_14), + .out_14(sum_Y_imag_hold_1_14), + .in_15(sum_Y_imag_1_15), + .out_15(sum_Y_imag_hold_1_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_rmsxbfewiw_real ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_real_2_0), + .out_0(sum_Y_real_hold_2_0), + .in_1(sum_Y_real_2_1), + .out_1(sum_Y_real_hold_2_1), + .in_2(sum_Y_real_2_2), + .out_2(sum_Y_real_hold_2_2), + .in_3(sum_Y_real_2_3), + .out_3(sum_Y_real_hold_2_3), + .in_4(sum_Y_real_2_4), + .out_4(sum_Y_real_hold_2_4), + .in_5(sum_Y_real_2_5), + .out_5(sum_Y_real_hold_2_5), + .in_6(sum_Y_real_2_6), + .out_6(sum_Y_real_hold_2_6), + .in_7(sum_Y_real_2_7), + .out_7(sum_Y_real_hold_2_7), + .in_8(sum_Y_real_2_8), + .out_8(sum_Y_real_hold_2_8), + .in_9(sum_Y_real_2_9), + .out_9(sum_Y_real_hold_2_9), + .in_10(sum_Y_real_2_10), + .out_10(sum_Y_real_hold_2_10), + .in_11(sum_Y_real_2_11), + .out_11(sum_Y_real_hold_2_11), + .in_12(sum_Y_real_2_12), + .out_12(sum_Y_real_hold_2_12), + .in_13(sum_Y_real_2_13), + .out_13(sum_Y_real_hold_2_13), + .in_14(sum_Y_real_2_14), + .out_14(sum_Y_real_hold_2_14), + .in_15(sum_Y_real_2_15), + .out_15(sum_Y_real_hold_2_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_mlaijwihgm_imag ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_imag_2_0), + .out_0(sum_Y_imag_hold_2_0), + .in_1(sum_Y_imag_2_1), + .out_1(sum_Y_imag_hold_2_1), + .in_2(sum_Y_imag_2_2), + .out_2(sum_Y_imag_hold_2_2), + .in_3(sum_Y_imag_2_3), + .out_3(sum_Y_imag_hold_2_3), + .in_4(sum_Y_imag_2_4), + .out_4(sum_Y_imag_hold_2_4), + .in_5(sum_Y_imag_2_5), + .out_5(sum_Y_imag_hold_2_5), + .in_6(sum_Y_imag_2_6), + .out_6(sum_Y_imag_hold_2_6), + .in_7(sum_Y_imag_2_7), + .out_7(sum_Y_imag_hold_2_7), + .in_8(sum_Y_imag_2_8), + .out_8(sum_Y_imag_hold_2_8), + .in_9(sum_Y_imag_2_9), + .out_9(sum_Y_imag_hold_2_9), + .in_10(sum_Y_imag_2_10), + .out_10(sum_Y_imag_hold_2_10), + .in_11(sum_Y_imag_2_11), + .out_11(sum_Y_imag_hold_2_11), + .in_12(sum_Y_imag_2_12), + .out_12(sum_Y_imag_hold_2_12), + .in_13(sum_Y_imag_2_13), + .out_13(sum_Y_imag_hold_2_13), + .in_14(sum_Y_imag_2_14), + .out_14(sum_Y_imag_hold_2_14), + .in_15(sum_Y_imag_2_15), + .out_15(sum_Y_imag_hold_2_15), + .reset(reset) +); + +idft_16_top_18 idft_16_top_18_inst_fjgpixgnmh ( + .clk(clk), + .reset(reset), + .next(accum_valid_0), + .X0(sum_Y_real_hold_0_0), + .Y0(out_Y_idft_0_0), + .X1(sum_Y_imag_hold_0_0), + .Y1(), + .X2(sum_Y_real_hold_0_1), + .Y2(out_Y_idft_0_1), + .X3(sum_Y_imag_hold_0_1), + .Y3(), + .X4(sum_Y_real_hold_0_2), + .Y4(out_Y_idft_0_2), + .X5(sum_Y_imag_hold_0_2), + .Y5(), + .X6(sum_Y_real_hold_0_3), + .Y6(out_Y_idft_0_3), + .X7(sum_Y_imag_hold_0_3), + .Y7(), + .X8(sum_Y_real_hold_0_4), + .Y8(out_Y_idft_0_4), + .X9(sum_Y_imag_hold_0_4), + .Y9(), + .X10(sum_Y_real_hold_0_5), + .Y10(out_Y_idft_0_5), + .X11(sum_Y_imag_hold_0_5), + .Y11(), + .X12(sum_Y_real_hold_0_6), + .Y12(out_Y_idft_0_6), + .X13(sum_Y_imag_hold_0_6), + .Y13(), + .X14(sum_Y_real_hold_0_7), + .Y14(out_Y_idft_0_7), + .X15(sum_Y_imag_hold_0_7), + .Y15(), + .X16(sum_Y_real_hold_0_8), + .Y16(out_Y_idft_0_8), + .X17(sum_Y_imag_hold_0_8), + .Y17(), + .X18(sum_Y_real_hold_0_9), + .Y18(out_Y_idft_0_9), + .X19(sum_Y_imag_hold_0_9), + .Y19(), + .X20(sum_Y_real_hold_0_10), + .Y20(out_Y_idft_0_10), + .X21(sum_Y_imag_hold_0_10), + .Y21(), + .X22(sum_Y_real_hold_0_11), + .Y22(out_Y_idft_0_11), + .X23(sum_Y_imag_hold_0_11), + .Y23(), + .X24(sum_Y_real_hold_0_12), + .Y24(out_Y_idft_0_12), + .X25(sum_Y_imag_hold_0_12), + .Y25(), + .X26(sum_Y_real_hold_0_13), + .Y26(out_Y_idft_0_13), + .X27(sum_Y_imag_hold_0_13), + .Y27(), + .X28(sum_Y_real_hold_0_14), + .Y28(out_Y_idft_0_14), + .X29(sum_Y_imag_hold_0_14), + .Y29(), + .X30(sum_Y_real_hold_0_15), + .Y30(out_Y_idft_0_15), + .X31(sum_Y_imag_hold_0_15), + .Y31(), + .next_out(idft_next_out_0) +); + +idft_16_top_18 idft_16_top_18_inst_dlorkailpz ( + .clk(clk), + .reset(reset), + .next(accum_valid_1), + .X0(sum_Y_real_hold_1_0), + .Y0(out_Y_idft_1_0), + .X1(sum_Y_imag_hold_1_0), + .Y1(), + .X2(sum_Y_real_hold_1_1), + .Y2(out_Y_idft_1_1), + .X3(sum_Y_imag_hold_1_1), + .Y3(), + .X4(sum_Y_real_hold_1_2), + .Y4(out_Y_idft_1_2), + .X5(sum_Y_imag_hold_1_2), + .Y5(), + .X6(sum_Y_real_hold_1_3), + .Y6(out_Y_idft_1_3), + .X7(sum_Y_imag_hold_1_3), + .Y7(), + .X8(sum_Y_real_hold_1_4), + .Y8(out_Y_idft_1_4), + .X9(sum_Y_imag_hold_1_4), + .Y9(), + .X10(sum_Y_real_hold_1_5), + .Y10(out_Y_idft_1_5), + .X11(sum_Y_imag_hold_1_5), + .Y11(), + .X12(sum_Y_real_hold_1_6), + .Y12(out_Y_idft_1_6), + .X13(sum_Y_imag_hold_1_6), + .Y13(), + .X14(sum_Y_real_hold_1_7), + .Y14(out_Y_idft_1_7), + .X15(sum_Y_imag_hold_1_7), + .Y15(), + .X16(sum_Y_real_hold_1_8), + .Y16(out_Y_idft_1_8), + .X17(sum_Y_imag_hold_1_8), + .Y17(), + .X18(sum_Y_real_hold_1_9), + .Y18(out_Y_idft_1_9), + .X19(sum_Y_imag_hold_1_9), + .Y19(), + .X20(sum_Y_real_hold_1_10), + .Y20(out_Y_idft_1_10), + .X21(sum_Y_imag_hold_1_10), + .Y21(), + .X22(sum_Y_real_hold_1_11), + .Y22(out_Y_idft_1_11), + .X23(sum_Y_imag_hold_1_11), + .Y23(), + .X24(sum_Y_real_hold_1_12), + .Y24(out_Y_idft_1_12), + .X25(sum_Y_imag_hold_1_12), + .Y25(), + .X26(sum_Y_real_hold_1_13), + .Y26(out_Y_idft_1_13), + .X27(sum_Y_imag_hold_1_13), + .Y27(), + .X28(sum_Y_real_hold_1_14), + .Y28(out_Y_idft_1_14), + .X29(sum_Y_imag_hold_1_14), + .Y29(), + .X30(sum_Y_real_hold_1_15), + .Y30(out_Y_idft_1_15), + .X31(sum_Y_imag_hold_1_15), + .Y31(), + .next_out(idft_next_out_1) +); + +idft_16_top_18 idft_16_top_18_inst_ihwtukovcz ( + .clk(clk), + .reset(reset), + .next(accum_valid_2), + .X0(sum_Y_real_hold_2_0), + .Y0(out_Y_idft_2_0), + .X1(sum_Y_imag_hold_2_0), + .Y1(), + .X2(sum_Y_real_hold_2_1), + .Y2(out_Y_idft_2_1), + .X3(sum_Y_imag_hold_2_1), + .Y3(), + .X4(sum_Y_real_hold_2_2), + .Y4(out_Y_idft_2_2), + .X5(sum_Y_imag_hold_2_2), + .Y5(), + .X6(sum_Y_real_hold_2_3), + .Y6(out_Y_idft_2_3), + .X7(sum_Y_imag_hold_2_3), + .Y7(), + .X8(sum_Y_real_hold_2_4), + .Y8(out_Y_idft_2_4), + .X9(sum_Y_imag_hold_2_4), + .Y9(), + .X10(sum_Y_real_hold_2_5), + .Y10(out_Y_idft_2_5), + .X11(sum_Y_imag_hold_2_5), + .Y11(), + .X12(sum_Y_real_hold_2_6), + .Y12(out_Y_idft_2_6), + .X13(sum_Y_imag_hold_2_6), + .Y13(), + .X14(sum_Y_real_hold_2_7), + .Y14(out_Y_idft_2_7), + .X15(sum_Y_imag_hold_2_7), + .Y15(), + .X16(sum_Y_real_hold_2_8), + .Y16(out_Y_idft_2_8), + .X17(sum_Y_imag_hold_2_8), + .Y17(), + .X18(sum_Y_real_hold_2_9), + .Y18(out_Y_idft_2_9), + .X19(sum_Y_imag_hold_2_9), + .Y19(), + .X20(sum_Y_real_hold_2_10), + .Y20(out_Y_idft_2_10), + .X21(sum_Y_imag_hold_2_10), + .Y21(), + .X22(sum_Y_real_hold_2_11), + .Y22(out_Y_idft_2_11), + .X23(sum_Y_imag_hold_2_11), + .Y23(), + .X24(sum_Y_real_hold_2_12), + .Y24(out_Y_idft_2_12), + .X25(sum_Y_imag_hold_2_12), + .Y25(), + .X26(sum_Y_real_hold_2_13), + .Y26(out_Y_idft_2_13), + .X27(sum_Y_imag_hold_2_13), + .Y27(), + .X28(sum_Y_real_hold_2_14), + .Y28(out_Y_idft_2_14), + .X29(sum_Y_imag_hold_2_14), + .Y29(), + .X30(sum_Y_real_hold_2_15), + .Y30(out_Y_idft_2_15), + .X31(sum_Y_imag_hold_2_15), + .Y31(), + .next_out(idft_next_out_2) +); + +always @ (posedge clk) begin + if (reset) begin + reg_Y_0_0 <= 0; + reg_Y_0_1 <= 0; + reg_Y_0_2 <= 0; + reg_Y_0_3 <= 0; + reg_Y_0_4 <= 0; + reg_Y_0_5 <= 0; + reg_Y_0_6 <= 0; + reg_Y_0_7 <= 0; + reg_Y_0_8 <= 0; + reg_Y_0_9 <= 0; + reg_Y_0_10 <= 0; + reg_Y_0_11 <= 0; + reg_Y_0_12 <= 0; + reg_Y_0_13 <= 0; + reg_Y_0_14 <= 0; + reg_Y_0_15 <= 0; + reg_Y_1_0 <= 0; + reg_Y_1_1 <= 0; + reg_Y_1_2 <= 0; + reg_Y_1_3 <= 0; + reg_Y_1_4 <= 0; + reg_Y_1_5 <= 0; + reg_Y_1_6 <= 0; + reg_Y_1_7 <= 0; + reg_Y_1_8 <= 0; + reg_Y_1_9 <= 0; + reg_Y_1_10 <= 0; + reg_Y_1_11 <= 0; + reg_Y_1_12 <= 0; + reg_Y_1_13 <= 0; + reg_Y_1_14 <= 0; + reg_Y_1_15 <= 0; + reg_Y_2_0 <= 0; + reg_Y_2_1 <= 0; + reg_Y_2_2 <= 0; + reg_Y_2_3 <= 0; + reg_Y_2_4 <= 0; + reg_Y_2_5 <= 0; + reg_Y_2_6 <= 0; + reg_Y_2_7 <= 0; + reg_Y_2_8 <= 0; + reg_Y_2_9 <= 0; + reg_Y_2_10 <= 0; + reg_Y_2_11 <= 0; + reg_Y_2_12 <= 0; + reg_Y_2_13 <= 0; + reg_Y_2_14 <= 0; + reg_Y_2_15 <= 0; + idft_out_valid <= 1'b0; + reg_o_valid <= 1'b0; + end else if (enable) begin + reg_Y_0_0 <= (out_Y_idft_0_0 >>> 4); + reg_Y_0_1 <= (out_Y_idft_0_1 >>> 4); + reg_Y_0_2 <= (out_Y_idft_0_2 >>> 4); + reg_Y_0_3 <= (out_Y_idft_0_3 >>> 4); + reg_Y_0_4 <= (out_Y_idft_0_4 >>> 4); + reg_Y_0_5 <= (out_Y_idft_0_5 >>> 4); + reg_Y_0_6 <= (out_Y_idft_0_6 >>> 4); + reg_Y_0_7 <= (out_Y_idft_0_7 >>> 4); + reg_Y_0_8 <= (out_Y_idft_0_8 >>> 4); + reg_Y_0_9 <= (out_Y_idft_0_9 >>> 4); + reg_Y_0_10 <= (out_Y_idft_0_10 >>> 4); + reg_Y_0_11 <= (out_Y_idft_0_11 >>> 4); + reg_Y_0_12 <= (out_Y_idft_0_12 >>> 4); + reg_Y_0_13 <= (out_Y_idft_0_13 >>> 4); + reg_Y_0_14 <= (out_Y_idft_0_14 >>> 4); + reg_Y_0_15 <= (out_Y_idft_0_15 >>> 4); + reg_Y_1_0 <= (out_Y_idft_1_0 >>> 4); + reg_Y_1_1 <= (out_Y_idft_1_1 >>> 4); + reg_Y_1_2 <= (out_Y_idft_1_2 >>> 4); + reg_Y_1_3 <= (out_Y_idft_1_3 >>> 4); + reg_Y_1_4 <= (out_Y_idft_1_4 >>> 4); + reg_Y_1_5 <= (out_Y_idft_1_5 >>> 4); + reg_Y_1_6 <= (out_Y_idft_1_6 >>> 4); + reg_Y_1_7 <= (out_Y_idft_1_7 >>> 4); + reg_Y_1_8 <= (out_Y_idft_1_8 >>> 4); + reg_Y_1_9 <= (out_Y_idft_1_9 >>> 4); + reg_Y_1_10 <= (out_Y_idft_1_10 >>> 4); + reg_Y_1_11 <= (out_Y_idft_1_11 >>> 4); + reg_Y_1_12 <= (out_Y_idft_1_12 >>> 4); + reg_Y_1_13 <= (out_Y_idft_1_13 >>> 4); + reg_Y_1_14 <= (out_Y_idft_1_14 >>> 4); + reg_Y_1_15 <= (out_Y_idft_1_15 >>> 4); + reg_Y_2_0 <= (out_Y_idft_2_0 >>> 4); + reg_Y_2_1 <= (out_Y_idft_2_1 >>> 4); + reg_Y_2_2 <= (out_Y_idft_2_2 >>> 4); + reg_Y_2_3 <= (out_Y_idft_2_3 >>> 4); + reg_Y_2_4 <= (out_Y_idft_2_4 >>> 4); + reg_Y_2_5 <= (out_Y_idft_2_5 >>> 4); + reg_Y_2_6 <= (out_Y_idft_2_6 >>> 4); + reg_Y_2_7 <= (out_Y_idft_2_7 >>> 4); + reg_Y_2_8 <= (out_Y_idft_2_8 >>> 4); + reg_Y_2_9 <= (out_Y_idft_2_9 >>> 4); + reg_Y_2_10 <= (out_Y_idft_2_10 >>> 4); + reg_Y_2_11 <= (out_Y_idft_2_11 >>> 4); + reg_Y_2_12 <= (out_Y_idft_2_12 >>> 4); + reg_Y_2_13 <= (out_Y_idft_2_13 >>> 4); + reg_Y_2_14 <= (out_Y_idft_2_14 >>> 4); + reg_Y_2_15 <= (out_Y_idft_2_15 >>> 4); + idft_out_valid <= idft_next_out_0; + reg_o_valid <= idft_out_valid; + end +end + +assign o_valid = enable & reg_o_valid; +assign o_ready = matrix_vec_mult_ready; +assign o_Y_0_0 = reg_Y_0_0; +assign o_Y_0_1 = reg_Y_0_1; +assign o_Y_0_2 = reg_Y_0_2; +assign o_Y_0_3 = reg_Y_0_3; +assign o_Y_0_4 = reg_Y_0_4; +assign o_Y_0_5 = reg_Y_0_5; +assign o_Y_0_6 = reg_Y_0_6; +assign o_Y_0_7 = reg_Y_0_7; +assign o_Y_0_8 = reg_Y_0_8; +assign o_Y_0_9 = reg_Y_0_9; +assign o_Y_0_10 = reg_Y_0_10; +assign o_Y_0_11 = reg_Y_0_11; +assign o_Y_0_12 = reg_Y_0_12; +assign o_Y_0_13 = reg_Y_0_13; +assign o_Y_0_14 = reg_Y_0_14; +assign o_Y_0_15 = reg_Y_0_15; +assign o_Y_1_0 = reg_Y_1_0; +assign o_Y_1_1 = reg_Y_1_1; +assign o_Y_1_2 = reg_Y_1_2; +assign o_Y_1_3 = reg_Y_1_3; +assign o_Y_1_4 = reg_Y_1_4; +assign o_Y_1_5 = reg_Y_1_5; +assign o_Y_1_6 = reg_Y_1_6; +assign o_Y_1_7 = reg_Y_1_7; +assign o_Y_1_8 = reg_Y_1_8; +assign o_Y_1_9 = reg_Y_1_9; +assign o_Y_1_10 = reg_Y_1_10; +assign o_Y_1_11 = reg_Y_1_11; +assign o_Y_1_12 = reg_Y_1_12; +assign o_Y_1_13 = reg_Y_1_13; +assign o_Y_1_14 = reg_Y_1_14; +assign o_Y_1_15 = reg_Y_1_15; +assign o_Y_2_0 = reg_Y_2_0; +assign o_Y_2_1 = reg_Y_2_1; +assign o_Y_2_2 = reg_Y_2_2; +assign o_Y_2_3 = reg_Y_2_3; +assign o_Y_2_4 = reg_Y_2_4; +assign o_Y_2_5 = reg_Y_2_5; +assign o_Y_2_6 = reg_Y_2_6; +assign o_Y_2_7 = reg_Y_2_7; +assign o_Y_2_8 = reg_Y_2_8; +assign o_Y_2_9 = reg_Y_2_9; +assign o_Y_2_10 = reg_Y_2_10; +assign o_Y_2_11 = reg_Y_2_11; +assign o_Y_2_12 = reg_Y_2_12; +assign o_Y_2_13 = reg_Y_2_13; +assign o_Y_2_14 = reg_Y_2_14; +assign o_Y_2_15 = reg_Y_2_15; + +endmodule + +module sum_complex_vector_unit_18_18_16_64 ( + input clk, + input clr, + input i_valid, + input enable, + input [17:0] i_real_0, + input [17:0] i_imag_0, + output [17:0] o_real_0, + output [17:0] o_imag_0, + input [17:0] i_real_1, + input [17:0] i_imag_1, + output [17:0] o_real_1, + output [17:0] o_imag_1, + input [17:0] i_real_2, + input [17:0] i_imag_2, + output [17:0] o_real_2, + output [17:0] o_imag_2, + input [17:0] i_real_3, + input [17:0] i_imag_3, + output [17:0] o_real_3, + output [17:0] o_imag_3, + input [17:0] i_real_4, + input [17:0] i_imag_4, + output [17:0] o_real_4, + output [17:0] o_imag_4, + input [17:0] i_real_5, + input [17:0] i_imag_5, + output [17:0] o_real_5, + output [17:0] o_imag_5, + input [17:0] i_real_6, + input [17:0] i_imag_6, + output [17:0] o_real_6, + output [17:0] o_imag_6, + input [17:0] i_real_7, + input [17:0] i_imag_7, + output [17:0] o_real_7, + output [17:0] o_imag_7, + input [17:0] i_real_8, + input [17:0] i_imag_8, + output [17:0] o_real_8, + output [17:0] o_imag_8, + input [17:0] i_real_9, + input [17:0] i_imag_9, + output [17:0] o_real_9, + output [17:0] o_imag_9, + input [17:0] i_real_10, + input [17:0] i_imag_10, + output [17:0] o_real_10, + output [17:0] o_imag_10, + input [17:0] i_real_11, + input [17:0] i_imag_11, + output [17:0] o_real_11, + output [17:0] o_imag_11, + input [17:0] i_real_12, + input [17:0] i_imag_12, + output [17:0] o_real_12, + output [17:0] o_imag_12, + input [17:0] i_real_13, + input [17:0] i_imag_13, + output [17:0] o_real_13, + output [17:0] o_imag_13, + input [17:0] i_real_14, + input [17:0] i_imag_14, + output [17:0] o_real_14, + output [17:0] o_imag_14, + input [17:0] i_real_15, + input [17:0] i_imag_15, + output [17:0] o_real_15, + output [17:0] o_imag_15, + output o_valid +); + +reg [17:0] sum_real_0; +reg [17:0] sum_imag_0; +reg [17:0] sum_real_1; +reg [17:0] sum_imag_1; +reg [17:0] sum_real_2; +reg [17:0] sum_imag_2; +reg [17:0] sum_real_3; +reg [17:0] sum_imag_3; +reg [17:0] sum_real_4; +reg [17:0] sum_imag_4; +reg [17:0] sum_real_5; +reg [17:0] sum_imag_5; +reg [17:0] sum_real_6; +reg [17:0] sum_imag_6; +reg [17:0] sum_real_7; +reg [17:0] sum_imag_7; +reg [17:0] sum_real_8; +reg [17:0] sum_imag_8; +reg [17:0] sum_real_9; +reg [17:0] sum_imag_9; +reg [17:0] sum_real_10; +reg [17:0] sum_imag_10; +reg [17:0] sum_real_11; +reg [17:0] sum_imag_11; +reg [17:0] sum_real_12; +reg [17:0] sum_imag_12; +reg [17:0] sum_real_13; +reg [17:0] sum_imag_13; +reg [17:0] sum_real_14; +reg [17:0] sum_imag_14; +reg [17:0] sum_real_15; +reg [17:0] sum_imag_15; +reg reg_i_valid; + +// Count the number data in accumulation +reg [13:0] counter; +wire counter_full; +always @ (posedge clk) begin + if (clr) begin + sum_real_0 <= 0; + sum_imag_0 <= 0; + sum_real_1 <= 0; + sum_imag_1 <= 0; + sum_real_2 <= 0; + sum_imag_2 <= 0; + sum_real_3 <= 0; + sum_imag_3 <= 0; + sum_real_4 <= 0; + sum_imag_4 <= 0; + sum_real_5 <= 0; + sum_imag_5 <= 0; + sum_real_6 <= 0; + sum_imag_6 <= 0; + sum_real_7 <= 0; + sum_imag_7 <= 0; + sum_real_8 <= 0; + sum_imag_8 <= 0; + sum_real_9 <= 0; + sum_imag_9 <= 0; + sum_real_10 <= 0; + sum_imag_10 <= 0; + sum_real_11 <= 0; + sum_imag_11 <= 0; + sum_real_12 <= 0; + sum_imag_12 <= 0; + sum_real_13 <= 0; + sum_imag_13 <= 0; + sum_real_14 <= 0; + sum_imag_14 <= 0; + sum_real_15 <= 0; + sum_imag_15 <= 0; + counter <= 14'd0; + reg_i_valid <= 1'b0; + end else if (enable) begin + reg_i_valid <= i_valid; + // Accumulate the number only when data is valid + if (i_valid) begin + if (counter == 64) + counter <= 1; + else + counter <= counter + 1'b1; + + if (counter == 64) begin + sum_real_0 <= i_real_0; + sum_imag_0 <= i_imag_0; + sum_real_1 <= i_real_1; + sum_imag_1 <= i_imag_1; + sum_real_2 <= i_real_2; + sum_imag_2 <= i_imag_2; + sum_real_3 <= i_real_3; + sum_imag_3 <= i_imag_3; + sum_real_4 <= i_real_4; + sum_imag_4 <= i_imag_4; + sum_real_5 <= i_real_5; + sum_imag_5 <= i_imag_5; + sum_real_6 <= i_real_6; + sum_imag_6 <= i_imag_6; + sum_real_7 <= i_real_7; + sum_imag_7 <= i_imag_7; + sum_real_8 <= i_real_8; + sum_imag_8 <= i_imag_8; + sum_real_9 <= i_real_9; + sum_imag_9 <= i_imag_9; + sum_real_10 <= i_real_10; + sum_imag_10 <= i_imag_10; + sum_real_11 <= i_real_11; + sum_imag_11 <= i_imag_11; + sum_real_12 <= i_real_12; + sum_imag_12 <= i_imag_12; + sum_real_13 <= i_real_13; + sum_imag_13 <= i_imag_13; + sum_real_14 <= i_real_14; + sum_imag_14 <= i_imag_14; + sum_real_15 <= i_real_15; + sum_imag_15 <= i_imag_15; + end else begin + sum_real_0 <= sum_real_0 + i_real_0; + sum_imag_0 <= sum_imag_0 + i_imag_0; + sum_real_1 <= sum_real_1 + i_real_1; + sum_imag_1 <= sum_imag_1 + i_imag_1; + sum_real_2 <= sum_real_2 + i_real_2; + sum_imag_2 <= sum_imag_2 + i_imag_2; + sum_real_3 <= sum_real_3 + i_real_3; + sum_imag_3 <= sum_imag_3 + i_imag_3; + sum_real_4 <= sum_real_4 + i_real_4; + sum_imag_4 <= sum_imag_4 + i_imag_4; + sum_real_5 <= sum_real_5 + i_real_5; + sum_imag_5 <= sum_imag_5 + i_imag_5; + sum_real_6 <= sum_real_6 + i_real_6; + sum_imag_6 <= sum_imag_6 + i_imag_6; + sum_real_7 <= sum_real_7 + i_real_7; + sum_imag_7 <= sum_imag_7 + i_imag_7; + sum_real_8 <= sum_real_8 + i_real_8; + sum_imag_8 <= sum_imag_8 + i_imag_8; + sum_real_9 <= sum_real_9 + i_real_9; + sum_imag_9 <= sum_imag_9 + i_imag_9; + sum_real_10 <= sum_real_10 + i_real_10; + sum_imag_10 <= sum_imag_10 + i_imag_10; + sum_real_11 <= sum_real_11 + i_real_11; + sum_imag_11 <= sum_imag_11 + i_imag_11; + sum_real_12 <= sum_real_12 + i_real_12; + sum_imag_12 <= sum_imag_12 + i_imag_12; + sum_real_13 <= sum_real_13 + i_real_13; + sum_imag_13 <= sum_imag_13 + i_imag_13; + sum_real_14 <= sum_real_14 + i_real_14; + sum_imag_14 <= sum_imag_14 + i_imag_14; + sum_real_15 <= sum_real_15 + i_real_15; + sum_imag_15 <= sum_imag_15 + i_imag_15; + end + end + end +end + +assign counter_full = (counter == 64); +assign o_real_0 = sum_real_0; +assign o_imag_0 = sum_imag_0; +assign o_real_1 = sum_real_1; +assign o_imag_1 = sum_imag_1; +assign o_real_2 = sum_real_2; +assign o_imag_2 = sum_imag_2; +assign o_real_3 = sum_real_3; +assign o_imag_3 = sum_imag_3; +assign o_real_4 = sum_real_4; +assign o_imag_4 = sum_imag_4; +assign o_real_5 = sum_real_5; +assign o_imag_5 = sum_imag_5; +assign o_real_6 = sum_real_6; +assign o_imag_6 = sum_imag_6; +assign o_real_7 = sum_real_7; +assign o_imag_7 = sum_imag_7; +assign o_real_8 = sum_real_8; +assign o_imag_8 = sum_imag_8; +assign o_real_9 = sum_real_9; +assign o_imag_9 = sum_imag_9; +assign o_real_10 = sum_real_10; +assign o_imag_10 = sum_imag_10; +assign o_real_11 = sum_real_11; +assign o_imag_11 = sum_imag_11; +assign o_real_12 = sum_real_12; +assign o_imag_12 = sum_imag_12; +assign o_real_13 = sum_real_13; +assign o_imag_13 = sum_imag_13; +assign o_real_14 = sum_real_14; +assign o_imag_14 = sum_imag_14; +assign o_real_15 = sum_real_15; +assign o_imag_15 = sum_imag_15; +assign o_valid = counter_full & reg_i_valid; + +endmodule + +module stage3_X_Y_buffer_18_16_3_10_32_64 ( + input clk, + input reset, + input i_X_valid, + input i_Y_valid, + input feed_start, + input [17:0] i_X_data_0, + input [17:0] i_Y_data_0, + output [17:0] o_data_0, + input [17:0] i_X_data_1, + input [17:0] i_Y_data_1, + output [17:0] o_data_1, + input [17:0] i_X_data_2, + input [17:0] i_Y_data_2, + output [17:0] o_data_2, + input [17:0] i_X_data_3, + input [17:0] i_Y_data_3, + output [17:0] o_data_3, + input [17:0] i_X_data_4, + input [17:0] i_Y_data_4, + output [17:0] o_data_4, + input [17:0] i_X_data_5, + input [17:0] i_Y_data_5, + output [17:0] o_data_5, + input [17:0] i_X_data_6, + input [17:0] i_Y_data_6, + output [17:0] o_data_6, + input [17:0] i_X_data_7, + input [17:0] i_Y_data_7, + output [17:0] o_data_7, + input [17:0] i_X_data_8, + input [17:0] i_Y_data_8, + output [17:0] o_data_8, + input [17:0] i_X_data_9, + input [17:0] i_Y_data_9, + output [17:0] o_data_9, + input [17:0] i_X_data_10, + input [17:0] i_Y_data_10, + output [17:0] o_data_10, + input [17:0] i_X_data_11, + input [17:0] i_Y_data_11, + output [17:0] o_data_11, + input [17:0] i_X_data_12, + input [17:0] i_Y_data_12, + output [17:0] o_data_12, + input [17:0] i_X_data_13, + input [17:0] i_Y_data_13, + output [17:0] o_data_13, + input [17:0] i_X_data_14, + input [17:0] i_Y_data_14, + output [17:0] o_data_14, + input [17:0] i_X_data_15, + input [17:0] i_Y_data_15, + output [17:0] o_data_15, + output o_valid, + output o_ready +); + +reg reg_feed_start; +reg [17:0] i_data_0; +reg [17:0] i_data_1; +reg [17:0] i_data_2; +reg [17:0] i_data_3; +reg [17:0] i_data_4; +reg [17:0] i_data_5; +reg [17:0] i_data_6; +reg [17:0] i_data_7; +reg [17:0] i_data_8; +reg [17:0] i_data_9; +reg [17:0] i_data_10; +reg [17:0] i_data_11; +reg [17:0] i_data_12; +reg [17:0] i_data_13; +reg [17:0] i_data_14; +reg [17:0] i_data_15; +wire [287:0] packed_o_data; +wire [287:0] packed_data; +reg wen; +wire ready_to_accept_new_X; +wire [13:0] input_index_counter; +assign ready_to_accept_new_X = (input_index_counter >= 32); +assign o_ready = ready_to_accept_new_X; +always @ (*) begin + if(ready_to_accept_new_X) begin + wen <= i_X_valid; + i_data_0 <= i_X_data_0; + i_data_1 <= i_X_data_1; + i_data_2 <= i_X_data_2; + i_data_3 <= i_X_data_3; + i_data_4 <= i_X_data_4; + i_data_5 <= i_X_data_5; + i_data_6 <= i_X_data_6; + i_data_7 <= i_X_data_7; + i_data_8 <= i_X_data_8; + i_data_9 <= i_X_data_9; + i_data_10 <= i_X_data_10; + i_data_11 <= i_X_data_11; + i_data_12 <= i_X_data_12; + i_data_13 <= i_X_data_13; + i_data_14 <= i_X_data_14; + i_data_15 <= i_X_data_15; + end else begin + wen <= i_Y_valid; + i_data_0 <= i_Y_data_0; + i_data_1 <= i_Y_data_1; + i_data_2 <= i_Y_data_2; + i_data_3 <= i_Y_data_3; + i_data_4 <= i_Y_data_4; + i_data_5 <= i_Y_data_5; + i_data_6 <= i_Y_data_6; + i_data_7 <= i_Y_data_7; + i_data_8 <= i_Y_data_8; + i_data_9 <= i_Y_data_9; + i_data_10 <= i_Y_data_10; + i_data_11 <= i_Y_data_11; + i_data_12 <= i_Y_data_12; + i_data_13 <= i_Y_data_13; + i_data_14 <= i_Y_data_14; + i_data_15 <= i_Y_data_15; + end +end + +assign o_data_0 = packed_o_data[17:0]; +assign packed_data[17:0] = i_data_0; +assign o_data_1 = packed_o_data[35:18]; +assign packed_data[35:18] = i_data_1; +assign o_data_2 = packed_o_data[53:36]; +assign packed_data[53:36] = i_data_2; +assign o_data_3 = packed_o_data[71:54]; +assign packed_data[71:54] = i_data_3; +assign o_data_4 = packed_o_data[89:72]; +assign packed_data[89:72] = i_data_4; +assign o_data_5 = packed_o_data[107:90]; +assign packed_data[107:90] = i_data_5; +assign o_data_6 = packed_o_data[125:108]; +assign packed_data[125:108] = i_data_6; +assign o_data_7 = packed_o_data[143:126]; +assign packed_data[143:126] = i_data_7; +assign o_data_8 = packed_o_data[161:144]; +assign packed_data[161:144] = i_data_8; +assign o_data_9 = packed_o_data[179:162]; +assign packed_data[179:162] = i_data_9; +assign o_data_10 = packed_o_data[197:180]; +assign packed_data[197:180] = i_data_10; +assign o_data_11 = packed_o_data[215:198]; +assign packed_data[215:198] = i_data_11; +assign o_data_12 = packed_o_data[233:216]; +assign packed_data[233:216] = i_data_12; +assign o_data_13 = packed_o_data[251:234]; +assign packed_data[251:234] = i_data_13; +assign o_data_14 = packed_o_data[269:252]; +assign packed_data[269:252] = i_data_14; +assign o_data_15 = packed_o_data[287:270]; +assign packed_data[287:270] = i_data_15; +counter_41_1_32 counter_41_1_32_inst_gzjqjyasxg ( + .clk(clk), + .reset(reset), + .ena(wen), + .count(input_index_counter) +); + +wire [13:0] output_index_counter; +reg en_output_counter; +counter_41_1 counter_41_1_inst_zzxtvtladl ( + .clk(clk), + .reset(reset), + .ena(en_output_counter), + .count(output_index_counter) +); + +wire incr_loop_index; +assign incr_loop_index = (output_index_counter == 41 && en_output_counter); +reg output_finish; +wire [13:0] loop_counter; +counter_20_1 counter_20_1_inst_loop ( + .clk(clk), + .reset(reset), + .ena(incr_loop_index), + .count(loop_counter) +); + +ram_18_0_42 ram_18_0_42_inst_qacrybgazt ( + .clk(clk), + .waddr(input_index_counter), + .wdata(packed_data), + .wen(wen), + .raddr(output_index_counter), + .q(packed_o_data) +); + +shift_register_unit_1_2 shift_register_unit_1_2_inst_jtjuegkgjy ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .in(en_output_counter), + .out(o_valid) +); + +always @ (posedge clk) begin + if (reset) begin + en_output_counter <= 1'b0; + output_finish <= 1'b0; + reg_feed_start <= 1'b0; + end else begin + en_output_counter <= (reg_feed_start && ~en_output_counter && ~output_finish); + if(feed_start) + reg_feed_start <= 1'b1; + else if (output_finish) + reg_feed_start <= 1'b0; + if ((loop_counter == 20) + &&(output_index_counter == 41) + && en_output_counter) + output_finish <= 1'b1; + else if (loop_counter == 0 && wen) + output_finish <= 1'b0; + end +end + +endmodule + +module counter_41_1_32 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 32; + end else if (ena) begin + if((count + 14'd1) <= 41) begin + count <= count + 14'd1; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module counter_20_1 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd1) <= 20) begin + count <= count + 14'd1; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module ram_18_0_42 ( + input clk, + input [4:0] waddr, + input [17:0] wdata, + input wen, + input [4:0] raddr, + output [17:0] q +); + +wire [17:0] rd_dummy_signal; +wire [17:0] wr_dummy_signal; +assign rd_dummy_signal = 0; + +dpram # (.AWIDTH(5), .DWIDTH(18), .NUM_WORDS(1<<5)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(q), + .clk(clk) +); +endmodule + +module shift_register_unit_1_2 ( + input clk, + input reset, + input enable, + input [0:0] in, + output [0:0] out +); + +reg [0:0] shift_registers_0; +reg [0:0] shift_registers_1; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 1'd0; + shift_registers_1 <= 1'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + end +end + +assign out = shift_registers_1; + +endmodule + diff --git a/designs/koios/clstm_like.large/clstm_random.sv b/designs/koios/clstm_like.large/clstm_random.sv new file mode 100644 index 000000000..6e70c8d66 --- /dev/null +++ b/designs/koios/clstm_like.large/clstm_random.sv @@ -0,0 +1,135 @@ +/* +Random inputs to clstm +*/ + +`include "../../random_number_generator.sv" + +module clstm_random( + input logic clk, + input logic rst, + input logic [7:0] wen_stage1, + input logic [6:0] wen_stage2, + input logic [1:0] wen_stage3, + input logic i_ready, + input logic i_valid, + input logic start_compute, + output logic o_valid, + output logic o_ready, + output logic [17:0] data, + input logic [2:0] data_sel0, + input logic [3:0] data_sel1 +); + +logic [161:0] wdata_stage1; +RandomNumberGenerator #(162, 0) rng1 ( + .clk(clk), + .reset(rst), + .random_number(wdata_stage1) +); + +logic [287:0] wdata_stage2; +RandomNumberGenerator #(288, 1) rng2 ( + .clk(clk), + .reset(rst), + .random_number(wdata_stage2) +); + +logic [161:0] wdata_stage3; +RandomNumberGenerator #(162, 3) rng3 ( + .clk(clk), + .reset(rst), + .random_number(wdata_stage3) +); + +logic [17:0] i_X_data [15:0]; +generate + genvar i; + for (i = 0; i < 16; i = i + 1) begin: gen_X_data + RandomNumberGenerator #(18, i) rng_X_data ( + .clk(clk), + .reset(rst), + .random_number(i_X_data[i]) + ); + end +endgenerate + +logic [17:0] o_sel [2:0][15:0]; +assign data = o_sel[data_sel0][data_sel1[3:0]]; + +C_LSTM_datapath ( + clk, + rst, + wdata_stage1, + wen_stage1, + wdata_stage2, + wen_stage2, + wdata_stage3, + wen_stage3, + i_X_data[0], + i_X_data[1], + i_X_data[2], + i_X_data[3], + i_X_data[4], + i_X_data[5], + i_X_data[6], + i_X_data[7], + i_X_data[8], + i_X_data[9], + i_X_data[10], + i_X_data[11], + i_X_data[12], + i_X_data[13], + i_X_data[14], + i_X_data[15], + o_sel[0][0], + o_sel[0][1], + o_sel[0][2], + o_sel[0][3], + o_sel[0][4], + o_sel[0][5], + o_sel[0][6], + o_sel[0][7], + o_sel[0][8], + o_sel[0][9], + o_sel[0][10], + o_sel[0][11], + o_sel[0][12], + o_sel[0][13], + o_sel[0][14], + o_sel[0][15], + o_sel[1][0], + o_sel[1][1], + o_sel[1][2], + o_sel[1][3], + o_sel[1][4], + o_sel[1][5], + o_sel[1][6], + o_sel[1][7], + o_sel[1][8], + o_sel[1][9], + o_sel[1][10], + o_sel[1][11], + o_sel[1][12], + o_sel[1][13], + o_sel[1][14], + o_sel[1][15], + o_sel[2][0], + o_sel[2][1], + o_sel[2][2], + o_sel[2][3], + o_sel[2][4], + o_sel[2][5], + o_sel[2][6], + o_sel[2][7], + o_sel[2][8], + o_sel[2][9], + o_sel[2][10], + o_sel[2][11], + o_sel[2][12], + o_sel[2][13], + o_sel[2][14], + o_sel[2][15] +); + + +endmodule \ No newline at end of file diff --git a/designs/koios/clstm_like.large/design.yaml b/designs/koios/clstm_like.large/design.yaml new file mode 100644 index 000000000..4b726b0fb --- /dev/null +++ b/designs/koios/clstm_like.large/design.yaml @@ -0,0 +1 @@ +top: clstm_random diff --git a/designs/koios/clstm_like.medium/clstm_like.medium.v b/designs/koios/clstm_like.medium/clstm_like.medium.v new file mode 100644 index 000000000..c11c9d83f --- /dev/null +++ b/designs/koios/clstm_like.medium/clstm_like.medium.v @@ -0,0 +1,26284 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Andrew Boutros +////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +//An accelerator overlay for LSTMs based on the C-LSTM paper: +//S. Wang et al., “C-LSTM: Enabling Efficient LSTM Using Structured Compression Techniques on FPGAs,” in International Symposium on Field-Programmable Gate Arrays (FPGA), 2018. +//Some properties of the design are: +//1. 18-bit fixed point is used. +//2. FFT based circulant convolution +//3. On-chip weight storage (compressed weights). +//4. Double buffering of intermediate results between stages. +//5. Element-wise addition, multiplication and activation blocks. +/////////////////////////////////////////////////////////////////////////////// + +module C_LSTM_datapath ( + input clk, + input reset, + input [161:0] wdata_stage1, + input [7:0] wen_stage1, + input [287:0] wdata_stage2, + input [6:0] wen_stage2, + input [161:0] wdata_stage3, + input [1:0] wen_stage3, + input [17:0] i_X_data_0, + input [17:0] i_X_data_1, + input [17:0] i_X_data_2, + input [17:0] i_X_data_3, + input [17:0] i_X_data_4, + input [17:0] i_X_data_5, + input [17:0] i_X_data_6, + input [17:0] i_X_data_7, + input [17:0] i_X_data_8, + input [17:0] i_X_data_9, + input [17:0] i_X_data_10, + input [17:0] i_X_data_11, + input [17:0] i_X_data_12, + input [17:0] i_X_data_13, + input [17:0] i_X_data_14, + input [17:0] i_X_data_15, + input i_ready, + input i_valid, + input start_compute, + output o_valid, + output [17:0] o_Yt_0_0, + output [17:0] o_Yt_0_1, + output [17:0] o_Yt_0_2, + output [17:0] o_Yt_0_3, + output [17:0] o_Yt_0_4, + output [17:0] o_Yt_0_5, + output [17:0] o_Yt_0_6, + output [17:0] o_Yt_0_7, + output [17:0] o_Yt_0_8, + output [17:0] o_Yt_0_9, + output [17:0] o_Yt_0_10, + output [17:0] o_Yt_0_11, + output [17:0] o_Yt_0_12, + output [17:0] o_Yt_0_13, + output [17:0] o_Yt_0_14, + output [17:0] o_Yt_0_15, + output [17:0] o_Yt_1_0, + output [17:0] o_Yt_1_1, + output [17:0] o_Yt_1_2, + output [17:0] o_Yt_1_3, + output [17:0] o_Yt_1_4, + output [17:0] o_Yt_1_5, + output [17:0] o_Yt_1_6, + output [17:0] o_Yt_1_7, + output [17:0] o_Yt_1_8, + output [17:0] o_Yt_1_9, + output [17:0] o_Yt_1_10, + output [17:0] o_Yt_1_11, + output [17:0] o_Yt_1_12, + output [17:0] o_Yt_1_13, + output [17:0] o_Yt_1_14, + output [17:0] o_Yt_1_15, + output o_ready +); + +// Enable whenever reciever is ready +wire enable; +assign enable = i_ready; + +// Input registers +wire [17:0] i_data_0; +wire [17:0] i_data_1; +wire [17:0] i_data_2; +wire [17:0] i_data_3; +wire [17:0] i_data_4; +wire [17:0] i_data_5; +wire [17:0] i_data_6; +wire [17:0] i_data_7; +wire [17:0] i_data_8; +wire [17:0] i_data_9; +wire [17:0] i_data_10; +wire [17:0] i_data_11; +wire [17:0] i_data_12; +wire [17:0] i_data_13; +wire [17:0] i_data_14; +wire [17:0] i_data_15; +wire [17:0] i_data_hold_0; +wire [17:0] i_data_hold_1; +wire [17:0] i_data_hold_2; +wire [17:0] i_data_hold_3; +wire [17:0] i_data_hold_4; +wire [17:0] i_data_hold_5; +wire [17:0] i_data_hold_6; +wire [17:0] i_data_hold_7; +wire [17:0] i_data_hold_8; +wire [17:0] i_data_hold_9; +wire [17:0] i_data_hold_10; +wire [17:0] i_data_hold_11; +wire [17:0] i_data_hold_12; +wire [17:0] i_data_hold_13; +wire [17:0] i_data_hold_14; +wire [17:0] i_data_hold_15; + +// Inter connections +wire i_valid_hold; +wire stage1_valid, stage1_ready; +wire out_X_Y_buffer_valid; + +// Stage 1 connections and weight buffers +// Input gate parameters +wire [17:0] Wixr_real_0_0; +wire [17:0] Wixr_imag_0_0; +wire [17:0] Wixr_real_0_1; +wire [17:0] Wixr_imag_0_1; +wire [17:0] Wixr_real_0_2; +wire [17:0] Wixr_imag_0_2; +wire [17:0] Wixr_real_0_3; +wire [17:0] Wixr_imag_0_3; +wire [17:0] Wixr_real_0_4; +wire [17:0] Wixr_imag_0_4; +wire [17:0] Wixr_real_0_5; +wire [17:0] Wixr_imag_0_5; +wire [17:0] Wixr_real_0_6; +wire [17:0] Wixr_imag_0_6; +wire [17:0] Wixr_real_0_7; +wire [17:0] Wixr_imag_0_7; +wire [17:0] Wixr_real_0_8; +wire [17:0] Wixr_imag_0_8; +wire [17:0] Wixr_real_1_0; +wire [17:0] Wixr_imag_1_0; +wire [17:0] Wixr_real_1_1; +wire [17:0] Wixr_imag_1_1; +wire [17:0] Wixr_real_1_2; +wire [17:0] Wixr_imag_1_2; +wire [17:0] Wixr_real_1_3; +wire [17:0] Wixr_imag_1_3; +wire [17:0] Wixr_real_1_4; +wire [17:0] Wixr_imag_1_4; +wire [17:0] Wixr_real_1_5; +wire [17:0] Wixr_imag_1_5; +wire [17:0] Wixr_real_1_6; +wire [17:0] Wixr_imag_1_6; +wire [17:0] Wixr_real_1_7; +wire [17:0] Wixr_imag_1_7; +wire [17:0] Wixr_real_1_8; +wire [17:0] Wixr_imag_1_8; + +// Forget gate parameters +wire [17:0] Wfxr_real_0_0; +wire [17:0] Wfxr_imag_0_0; +wire [17:0] Wfxr_real_0_1; +wire [17:0] Wfxr_imag_0_1; +wire [17:0] Wfxr_real_0_2; +wire [17:0] Wfxr_imag_0_2; +wire [17:0] Wfxr_real_0_3; +wire [17:0] Wfxr_imag_0_3; +wire [17:0] Wfxr_real_0_4; +wire [17:0] Wfxr_imag_0_4; +wire [17:0] Wfxr_real_0_5; +wire [17:0] Wfxr_imag_0_5; +wire [17:0] Wfxr_real_0_6; +wire [17:0] Wfxr_imag_0_6; +wire [17:0] Wfxr_real_0_7; +wire [17:0] Wfxr_imag_0_7; +wire [17:0] Wfxr_real_0_8; +wire [17:0] Wfxr_imag_0_8; +wire [17:0] Wfxr_real_1_0; +wire [17:0] Wfxr_imag_1_0; +wire [17:0] Wfxr_real_1_1; +wire [17:0] Wfxr_imag_1_1; +wire [17:0] Wfxr_real_1_2; +wire [17:0] Wfxr_imag_1_2; +wire [17:0] Wfxr_real_1_3; +wire [17:0] Wfxr_imag_1_3; +wire [17:0] Wfxr_real_1_4; +wire [17:0] Wfxr_imag_1_4; +wire [17:0] Wfxr_real_1_5; +wire [17:0] Wfxr_imag_1_5; +wire [17:0] Wfxr_real_1_6; +wire [17:0] Wfxr_imag_1_6; +wire [17:0] Wfxr_real_1_7; +wire [17:0] Wfxr_imag_1_7; +wire [17:0] Wfxr_real_1_8; +wire [17:0] Wfxr_imag_1_8; + +// Output gate parameters +wire [17:0] Woxr_real_0_0; +wire [17:0] Woxr_imag_0_0; +wire [17:0] Woxr_real_0_1; +wire [17:0] Woxr_imag_0_1; +wire [17:0] Woxr_real_0_2; +wire [17:0] Woxr_imag_0_2; +wire [17:0] Woxr_real_0_3; +wire [17:0] Woxr_imag_0_3; +wire [17:0] Woxr_real_0_4; +wire [17:0] Woxr_imag_0_4; +wire [17:0] Woxr_real_0_5; +wire [17:0] Woxr_imag_0_5; +wire [17:0] Woxr_real_0_6; +wire [17:0] Woxr_imag_0_6; +wire [17:0] Woxr_real_0_7; +wire [17:0] Woxr_imag_0_7; +wire [17:0] Woxr_real_0_8; +wire [17:0] Woxr_imag_0_8; +wire [17:0] Woxr_real_1_0; +wire [17:0] Woxr_imag_1_0; +wire [17:0] Woxr_real_1_1; +wire [17:0] Woxr_imag_1_1; +wire [17:0] Woxr_real_1_2; +wire [17:0] Woxr_imag_1_2; +wire [17:0] Woxr_real_1_3; +wire [17:0] Woxr_imag_1_3; +wire [17:0] Woxr_real_1_4; +wire [17:0] Woxr_imag_1_4; +wire [17:0] Woxr_real_1_5; +wire [17:0] Woxr_imag_1_5; +wire [17:0] Woxr_real_1_6; +wire [17:0] Woxr_imag_1_6; +wire [17:0] Woxr_real_1_7; +wire [17:0] Woxr_imag_1_7; +wire [17:0] Woxr_real_1_8; +wire [17:0] Woxr_imag_1_8; + +// Activation gate parameters +wire [17:0] Wcxr_real_0_0; +wire [17:0] Wcxr_imag_0_0; +wire [17:0] Wcxr_real_0_1; +wire [17:0] Wcxr_imag_0_1; +wire [17:0] Wcxr_real_0_2; +wire [17:0] Wcxr_imag_0_2; +wire [17:0] Wcxr_real_0_3; +wire [17:0] Wcxr_imag_0_3; +wire [17:0] Wcxr_real_0_4; +wire [17:0] Wcxr_imag_0_4; +wire [17:0] Wcxr_real_0_5; +wire [17:0] Wcxr_imag_0_5; +wire [17:0] Wcxr_real_0_6; +wire [17:0] Wcxr_imag_0_6; +wire [17:0] Wcxr_real_0_7; +wire [17:0] Wcxr_imag_0_7; +wire [17:0] Wcxr_real_0_8; +wire [17:0] Wcxr_imag_0_8; +wire [17:0] Wcxr_real_1_0; +wire [17:0] Wcxr_imag_1_0; +wire [17:0] Wcxr_real_1_1; +wire [17:0] Wcxr_imag_1_1; +wire [17:0] Wcxr_real_1_2; +wire [17:0] Wcxr_imag_1_2; +wire [17:0] Wcxr_real_1_3; +wire [17:0] Wcxr_imag_1_3; +wire [17:0] Wcxr_real_1_4; +wire [17:0] Wcxr_imag_1_4; +wire [17:0] Wcxr_real_1_5; +wire [17:0] Wcxr_imag_1_5; +wire [17:0] Wcxr_real_1_6; +wire [17:0] Wcxr_imag_1_6; +wire [17:0] Wcxr_real_1_7; +wire [17:0] Wcxr_imag_1_7; +wire [17:0] Wcxr_real_1_8; +wire [17:0] Wcxr_imag_1_8; + +wire [17:0] WixrXtYt_1_0_0; +wire [17:0] WfxrXtYt_1_0_0; +wire [17:0] WoxrXtYt_1_0_0; +wire [17:0] WcxrXtYt_1_0_0; +wire [17:0] WixrXtYt_1_0_1; +wire [17:0] WfxrXtYt_1_0_1; +wire [17:0] WoxrXtYt_1_0_1; +wire [17:0] WcxrXtYt_1_0_1; +wire [17:0] WixrXtYt_1_0_2; +wire [17:0] WfxrXtYt_1_0_2; +wire [17:0] WoxrXtYt_1_0_2; +wire [17:0] WcxrXtYt_1_0_2; +wire [17:0] WixrXtYt_1_0_3; +wire [17:0] WfxrXtYt_1_0_3; +wire [17:0] WoxrXtYt_1_0_3; +wire [17:0] WcxrXtYt_1_0_3; +wire [17:0] WixrXtYt_1_0_4; +wire [17:0] WfxrXtYt_1_0_4; +wire [17:0] WoxrXtYt_1_0_4; +wire [17:0] WcxrXtYt_1_0_4; +wire [17:0] WixrXtYt_1_0_5; +wire [17:0] WfxrXtYt_1_0_5; +wire [17:0] WoxrXtYt_1_0_5; +wire [17:0] WcxrXtYt_1_0_5; +wire [17:0] WixrXtYt_1_0_6; +wire [17:0] WfxrXtYt_1_0_6; +wire [17:0] WoxrXtYt_1_0_6; +wire [17:0] WcxrXtYt_1_0_6; +wire [17:0] WixrXtYt_1_0_7; +wire [17:0] WfxrXtYt_1_0_7; +wire [17:0] WoxrXtYt_1_0_7; +wire [17:0] WcxrXtYt_1_0_7; +wire [17:0] WixrXtYt_1_0_8; +wire [17:0] WfxrXtYt_1_0_8; +wire [17:0] WoxrXtYt_1_0_8; +wire [17:0] WcxrXtYt_1_0_8; +wire [17:0] WixrXtYt_1_0_9; +wire [17:0] WfxrXtYt_1_0_9; +wire [17:0] WoxrXtYt_1_0_9; +wire [17:0] WcxrXtYt_1_0_9; +wire [17:0] WixrXtYt_1_0_10; +wire [17:0] WfxrXtYt_1_0_10; +wire [17:0] WoxrXtYt_1_0_10; +wire [17:0] WcxrXtYt_1_0_10; +wire [17:0] WixrXtYt_1_0_11; +wire [17:0] WfxrXtYt_1_0_11; +wire [17:0] WoxrXtYt_1_0_11; +wire [17:0] WcxrXtYt_1_0_11; +wire [17:0] WixrXtYt_1_0_12; +wire [17:0] WfxrXtYt_1_0_12; +wire [17:0] WoxrXtYt_1_0_12; +wire [17:0] WcxrXtYt_1_0_12; +wire [17:0] WixrXtYt_1_0_13; +wire [17:0] WfxrXtYt_1_0_13; +wire [17:0] WoxrXtYt_1_0_13; +wire [17:0] WcxrXtYt_1_0_13; +wire [17:0] WixrXtYt_1_0_14; +wire [17:0] WfxrXtYt_1_0_14; +wire [17:0] WoxrXtYt_1_0_14; +wire [17:0] WcxrXtYt_1_0_14; +wire [17:0] WixrXtYt_1_0_15; +wire [17:0] WfxrXtYt_1_0_15; +wire [17:0] WoxrXtYt_1_0_15; +wire [17:0] WcxrXtYt_1_0_15; +wire [17:0] WixrXtYt_1_1_0; +wire [17:0] WfxrXtYt_1_1_0; +wire [17:0] WoxrXtYt_1_1_0; +wire [17:0] WcxrXtYt_1_1_0; +wire [17:0] WixrXtYt_1_1_1; +wire [17:0] WfxrXtYt_1_1_1; +wire [17:0] WoxrXtYt_1_1_1; +wire [17:0] WcxrXtYt_1_1_1; +wire [17:0] WixrXtYt_1_1_2; +wire [17:0] WfxrXtYt_1_1_2; +wire [17:0] WoxrXtYt_1_1_2; +wire [17:0] WcxrXtYt_1_1_2; +wire [17:0] WixrXtYt_1_1_3; +wire [17:0] WfxrXtYt_1_1_3; +wire [17:0] WoxrXtYt_1_1_3; +wire [17:0] WcxrXtYt_1_1_3; +wire [17:0] WixrXtYt_1_1_4; +wire [17:0] WfxrXtYt_1_1_4; +wire [17:0] WoxrXtYt_1_1_4; +wire [17:0] WcxrXtYt_1_1_4; +wire [17:0] WixrXtYt_1_1_5; +wire [17:0] WfxrXtYt_1_1_5; +wire [17:0] WoxrXtYt_1_1_5; +wire [17:0] WcxrXtYt_1_1_5; +wire [17:0] WixrXtYt_1_1_6; +wire [17:0] WfxrXtYt_1_1_6; +wire [17:0] WoxrXtYt_1_1_6; +wire [17:0] WcxrXtYt_1_1_6; +wire [17:0] WixrXtYt_1_1_7; +wire [17:0] WfxrXtYt_1_1_7; +wire [17:0] WoxrXtYt_1_1_7; +wire [17:0] WcxrXtYt_1_1_7; +wire [17:0] WixrXtYt_1_1_8; +wire [17:0] WfxrXtYt_1_1_8; +wire [17:0] WoxrXtYt_1_1_8; +wire [17:0] WcxrXtYt_1_1_8; +wire [17:0] WixrXtYt_1_1_9; +wire [17:0] WfxrXtYt_1_1_9; +wire [17:0] WoxrXtYt_1_1_9; +wire [17:0] WcxrXtYt_1_1_9; +wire [17:0] WixrXtYt_1_1_10; +wire [17:0] WfxrXtYt_1_1_10; +wire [17:0] WoxrXtYt_1_1_10; +wire [17:0] WcxrXtYt_1_1_10; +wire [17:0] WixrXtYt_1_1_11; +wire [17:0] WfxrXtYt_1_1_11; +wire [17:0] WoxrXtYt_1_1_11; +wire [17:0] WcxrXtYt_1_1_11; +wire [17:0] WixrXtYt_1_1_12; +wire [17:0] WfxrXtYt_1_1_12; +wire [17:0] WoxrXtYt_1_1_12; +wire [17:0] WcxrXtYt_1_1_12; +wire [17:0] WixrXtYt_1_1_13; +wire [17:0] WfxrXtYt_1_1_13; +wire [17:0] WoxrXtYt_1_1_13; +wire [17:0] WcxrXtYt_1_1_13; +wire [17:0] WixrXtYt_1_1_14; +wire [17:0] WfxrXtYt_1_1_14; +wire [17:0] WoxrXtYt_1_1_14; +wire [17:0] WcxrXtYt_1_1_14; +wire [17:0] WixrXtYt_1_1_15; +wire [17:0] WfxrXtYt_1_1_15; +wire [17:0] WoxrXtYt_1_1_15; +wire [17:0] WcxrXtYt_1_1_15; + +wire stage_buffer_incr_index; +assign stage_buffer_incr_index = out_X_Y_buffer_valid & enable; +stage1_parameter_buffer_18_2_16_42_2688 stage1_parameter_buffer_18_2_16_42_2688_inst_qugkkfgach ( + .clk(clk), + .reset(reset), + .wdata(wdata_stage1), + .wen(wen_stage1), + .Wixr_real_0_0(Wixr_real_0_0), + .Wixr_imag_0_0(Wixr_imag_0_0), + .Wfxr_real_0_0(Wfxr_real_0_0), + .Wfxr_imag_0_0(Wfxr_imag_0_0), + .Woxr_real_0_0(Woxr_real_0_0), + .Woxr_imag_0_0(Woxr_imag_0_0), + .Wcxr_real_0_0(Wcxr_real_0_0), + .Wcxr_imag_0_0(Wcxr_imag_0_0), + .Wixr_real_0_1(Wixr_real_0_1), + .Wixr_imag_0_1(Wixr_imag_0_1), + .Wfxr_real_0_1(Wfxr_real_0_1), + .Wfxr_imag_0_1(Wfxr_imag_0_1), + .Woxr_real_0_1(Woxr_real_0_1), + .Woxr_imag_0_1(Woxr_imag_0_1), + .Wcxr_real_0_1(Wcxr_real_0_1), + .Wcxr_imag_0_1(Wcxr_imag_0_1), + .Wixr_real_0_2(Wixr_real_0_2), + .Wixr_imag_0_2(Wixr_imag_0_2), + .Wfxr_real_0_2(Wfxr_real_0_2), + .Wfxr_imag_0_2(Wfxr_imag_0_2), + .Woxr_real_0_2(Woxr_real_0_2), + .Woxr_imag_0_2(Woxr_imag_0_2), + .Wcxr_real_0_2(Wcxr_real_0_2), + .Wcxr_imag_0_2(Wcxr_imag_0_2), + .Wixr_real_0_3(Wixr_real_0_3), + .Wixr_imag_0_3(Wixr_imag_0_3), + .Wfxr_real_0_3(Wfxr_real_0_3), + .Wfxr_imag_0_3(Wfxr_imag_0_3), + .Woxr_real_0_3(Woxr_real_0_3), + .Woxr_imag_0_3(Woxr_imag_0_3), + .Wcxr_real_0_3(Wcxr_real_0_3), + .Wcxr_imag_0_3(Wcxr_imag_0_3), + .Wixr_real_0_4(Wixr_real_0_4), + .Wixr_imag_0_4(Wixr_imag_0_4), + .Wfxr_real_0_4(Wfxr_real_0_4), + .Wfxr_imag_0_4(Wfxr_imag_0_4), + .Woxr_real_0_4(Woxr_real_0_4), + .Woxr_imag_0_4(Woxr_imag_0_4), + .Wcxr_real_0_4(Wcxr_real_0_4), + .Wcxr_imag_0_4(Wcxr_imag_0_4), + .Wixr_real_0_5(Wixr_real_0_5), + .Wixr_imag_0_5(Wixr_imag_0_5), + .Wfxr_real_0_5(Wfxr_real_0_5), + .Wfxr_imag_0_5(Wfxr_imag_0_5), + .Woxr_real_0_5(Woxr_real_0_5), + .Woxr_imag_0_5(Woxr_imag_0_5), + .Wcxr_real_0_5(Wcxr_real_0_5), + .Wcxr_imag_0_5(Wcxr_imag_0_5), + .Wixr_real_0_6(Wixr_real_0_6), + .Wixr_imag_0_6(Wixr_imag_0_6), + .Wfxr_real_0_6(Wfxr_real_0_6), + .Wfxr_imag_0_6(Wfxr_imag_0_6), + .Woxr_real_0_6(Woxr_real_0_6), + .Woxr_imag_0_6(Woxr_imag_0_6), + .Wcxr_real_0_6(Wcxr_real_0_6), + .Wcxr_imag_0_6(Wcxr_imag_0_6), + .Wixr_real_0_7(Wixr_real_0_7), + .Wixr_imag_0_7(Wixr_imag_0_7), + .Wfxr_real_0_7(Wfxr_real_0_7), + .Wfxr_imag_0_7(Wfxr_imag_0_7), + .Woxr_real_0_7(Woxr_real_0_7), + .Woxr_imag_0_7(Woxr_imag_0_7), + .Wcxr_real_0_7(Wcxr_real_0_7), + .Wcxr_imag_0_7(Wcxr_imag_0_7), + .Wixr_real_0_8(Wixr_real_0_8), + .Wixr_imag_0_8(Wixr_imag_0_8), + .Wfxr_real_0_8(Wfxr_real_0_8), + .Wfxr_imag_0_8(Wfxr_imag_0_8), + .Woxr_real_0_8(Woxr_real_0_8), + .Woxr_imag_0_8(Woxr_imag_0_8), + .Wcxr_real_0_8(Wcxr_real_0_8), + .Wcxr_imag_0_8(Wcxr_imag_0_8), + .Wixr_real_1_0(Wixr_real_1_0), + .Wixr_imag_1_0(Wixr_imag_1_0), + .Wfxr_real_1_0(Wfxr_real_1_0), + .Wfxr_imag_1_0(Wfxr_imag_1_0), + .Woxr_real_1_0(Woxr_real_1_0), + .Woxr_imag_1_0(Woxr_imag_1_0), + .Wcxr_real_1_0(Wcxr_real_1_0), + .Wcxr_imag_1_0(Wcxr_imag_1_0), + .Wixr_real_1_1(Wixr_real_1_1), + .Wixr_imag_1_1(Wixr_imag_1_1), + .Wfxr_real_1_1(Wfxr_real_1_1), + .Wfxr_imag_1_1(Wfxr_imag_1_1), + .Woxr_real_1_1(Woxr_real_1_1), + .Woxr_imag_1_1(Woxr_imag_1_1), + .Wcxr_real_1_1(Wcxr_real_1_1), + .Wcxr_imag_1_1(Wcxr_imag_1_1), + .Wixr_real_1_2(Wixr_real_1_2), + .Wixr_imag_1_2(Wixr_imag_1_2), + .Wfxr_real_1_2(Wfxr_real_1_2), + .Wfxr_imag_1_2(Wfxr_imag_1_2), + .Woxr_real_1_2(Woxr_real_1_2), + .Woxr_imag_1_2(Woxr_imag_1_2), + .Wcxr_real_1_2(Wcxr_real_1_2), + .Wcxr_imag_1_2(Wcxr_imag_1_2), + .Wixr_real_1_3(Wixr_real_1_3), + .Wixr_imag_1_3(Wixr_imag_1_3), + .Wfxr_real_1_3(Wfxr_real_1_3), + .Wfxr_imag_1_3(Wfxr_imag_1_3), + .Woxr_real_1_3(Woxr_real_1_3), + .Woxr_imag_1_3(Woxr_imag_1_3), + .Wcxr_real_1_3(Wcxr_real_1_3), + .Wcxr_imag_1_3(Wcxr_imag_1_3), + .Wixr_real_1_4(Wixr_real_1_4), + .Wixr_imag_1_4(Wixr_imag_1_4), + .Wfxr_real_1_4(Wfxr_real_1_4), + .Wfxr_imag_1_4(Wfxr_imag_1_4), + .Woxr_real_1_4(Woxr_real_1_4), + .Woxr_imag_1_4(Woxr_imag_1_4), + .Wcxr_real_1_4(Wcxr_real_1_4), + .Wcxr_imag_1_4(Wcxr_imag_1_4), + .Wixr_real_1_5(Wixr_real_1_5), + .Wixr_imag_1_5(Wixr_imag_1_5), + .Wfxr_real_1_5(Wfxr_real_1_5), + .Wfxr_imag_1_5(Wfxr_imag_1_5), + .Woxr_real_1_5(Woxr_real_1_5), + .Woxr_imag_1_5(Woxr_imag_1_5), + .Wcxr_real_1_5(Wcxr_real_1_5), + .Wcxr_imag_1_5(Wcxr_imag_1_5), + .Wixr_real_1_6(Wixr_real_1_6), + .Wixr_imag_1_6(Wixr_imag_1_6), + .Wfxr_real_1_6(Wfxr_real_1_6), + .Wfxr_imag_1_6(Wfxr_imag_1_6), + .Woxr_real_1_6(Woxr_real_1_6), + .Woxr_imag_1_6(Woxr_imag_1_6), + .Wcxr_real_1_6(Wcxr_real_1_6), + .Wcxr_imag_1_6(Wcxr_imag_1_6), + .Wixr_real_1_7(Wixr_real_1_7), + .Wixr_imag_1_7(Wixr_imag_1_7), + .Wfxr_real_1_7(Wfxr_real_1_7), + .Wfxr_imag_1_7(Wfxr_imag_1_7), + .Woxr_real_1_7(Woxr_real_1_7), + .Woxr_imag_1_7(Woxr_imag_1_7), + .Wcxr_real_1_7(Wcxr_real_1_7), + .Wcxr_imag_1_7(Wcxr_imag_1_7), + .Wixr_real_1_8(Wixr_real_1_8), + .Wixr_imag_1_8(Wixr_imag_1_8), + .Wfxr_real_1_8(Wfxr_real_1_8), + .Wfxr_imag_1_8(Wfxr_imag_1_8), + .Woxr_real_1_8(Woxr_real_1_8), + .Woxr_imag_1_8(Woxr_imag_1_8), + .Wcxr_real_1_8(Wcxr_real_1_8), + .Wcxr_imag_1_8(Wcxr_imag_1_8), + .incr_index(stage_buffer_incr_index) +); + +// Pipeline the input data for one more cycle to match the parameter rom +shift_register_group_18_16_3 shift_register_group_18_16_3_inst_dzyqjacupq ( + .clk(clk), + .enable(1'b1), + .in_0(i_data_0), + .out_0(i_data_hold_0), + .in_1(i_data_1), + .out_1(i_data_hold_1), + .in_2(i_data_2), + .out_2(i_data_hold_2), + .in_3(i_data_3), + .out_3(i_data_hold_3), + .in_4(i_data_4), + .out_4(i_data_hold_4), + .in_5(i_data_5), + .out_5(i_data_hold_5), + .in_6(i_data_6), + .out_6(i_data_hold_6), + .in_7(i_data_7), + .out_7(i_data_hold_7), + .in_8(i_data_8), + .out_8(i_data_hold_8), + .in_9(i_data_9), + .out_9(i_data_hold_9), + .in_10(i_data_10), + .out_10(i_data_hold_10), + .in_11(i_data_11), + .out_11(i_data_hold_11), + .in_12(i_data_12), + .out_12(i_data_hold_12), + .in_13(i_data_13), + .out_13(i_data_hold_13), + .in_14(i_data_14), + .out_14(i_data_hold_14), + .in_15(i_data_15), + .out_15(i_data_hold_15), + .reset(reset) +); + +shift_register_unit_1_3 shift_register_unit_1_3_inst_qzxsjjaikk ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(out_X_Y_buffer_valid), + .out(i_valid_hold) +); + +C_LSTM_stage_1_18_10_160_512_2_16_1 C_LSTM_stage_1_18_10_160_512_2_16_1_inst_goywnnjgcr ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_ready(enable), + .i_Xt_Yt_1_0(i_data_hold_0), + .i_Xt_Yt_1_1(i_data_hold_1), + .i_Xt_Yt_1_2(i_data_hold_2), + .i_Xt_Yt_1_3(i_data_hold_3), + .i_Xt_Yt_1_4(i_data_hold_4), + .i_Xt_Yt_1_5(i_data_hold_5), + .i_Xt_Yt_1_6(i_data_hold_6), + .i_Xt_Yt_1_7(i_data_hold_7), + .i_Xt_Yt_1_8(i_data_hold_8), + .i_Xt_Yt_1_9(i_data_hold_9), + .i_Xt_Yt_1_10(i_data_hold_10), + .i_Xt_Yt_1_11(i_data_hold_11), + .i_Xt_Yt_1_12(i_data_hold_12), + .i_Xt_Yt_1_13(i_data_hold_13), + .i_Xt_Yt_1_14(i_data_hold_14), + .i_Xt_Yt_1_15(i_data_hold_15), + .i_Wixr_real_0_0(Wixr_real_0_0), + .i_Wixr_imag_0_0(Wixr_imag_0_0), + .i_Wfxr_real_0_0(Wfxr_real_0_0), + .i_Wfxr_imag_0_0(Wfxr_imag_0_0), + .i_Woxr_real_0_0(Woxr_real_0_0), + .i_Woxr_imag_0_0(Woxr_imag_0_0), + .i_Wcxr_real_0_0(Wcxr_real_0_0), + .i_Wcxr_imag_0_0(Wcxr_imag_0_0), + .i_Wixr_real_0_1(Wixr_real_0_1), + .i_Wixr_imag_0_1(Wixr_imag_0_1), + .i_Wfxr_real_0_1(Wfxr_real_0_1), + .i_Wfxr_imag_0_1(Wfxr_imag_0_1), + .i_Woxr_real_0_1(Woxr_real_0_1), + .i_Woxr_imag_0_1(Woxr_imag_0_1), + .i_Wcxr_real_0_1(Wcxr_real_0_1), + .i_Wcxr_imag_0_1(Wcxr_imag_0_1), + .i_Wixr_real_0_2(Wixr_real_0_2), + .i_Wixr_imag_0_2(Wixr_imag_0_2), + .i_Wfxr_real_0_2(Wfxr_real_0_2), + .i_Wfxr_imag_0_2(Wfxr_imag_0_2), + .i_Woxr_real_0_2(Woxr_real_0_2), + .i_Woxr_imag_0_2(Woxr_imag_0_2), + .i_Wcxr_real_0_2(Wcxr_real_0_2), + .i_Wcxr_imag_0_2(Wcxr_imag_0_2), + .i_Wixr_real_0_3(Wixr_real_0_3), + .i_Wixr_imag_0_3(Wixr_imag_0_3), + .i_Wfxr_real_0_3(Wfxr_real_0_3), + .i_Wfxr_imag_0_3(Wfxr_imag_0_3), + .i_Woxr_real_0_3(Woxr_real_0_3), + .i_Woxr_imag_0_3(Woxr_imag_0_3), + .i_Wcxr_real_0_3(Wcxr_real_0_3), + .i_Wcxr_imag_0_3(Wcxr_imag_0_3), + .i_Wixr_real_0_4(Wixr_real_0_4), + .i_Wixr_imag_0_4(Wixr_imag_0_4), + .i_Wfxr_real_0_4(Wfxr_real_0_4), + .i_Wfxr_imag_0_4(Wfxr_imag_0_4), + .i_Woxr_real_0_4(Woxr_real_0_4), + .i_Woxr_imag_0_4(Woxr_imag_0_4), + .i_Wcxr_real_0_4(Wcxr_real_0_4), + .i_Wcxr_imag_0_4(Wcxr_imag_0_4), + .i_Wixr_real_0_5(Wixr_real_0_5), + .i_Wixr_imag_0_5(Wixr_imag_0_5), + .i_Wfxr_real_0_5(Wfxr_real_0_5), + .i_Wfxr_imag_0_5(Wfxr_imag_0_5), + .i_Woxr_real_0_5(Woxr_real_0_5), + .i_Woxr_imag_0_5(Woxr_imag_0_5), + .i_Wcxr_real_0_5(Wcxr_real_0_5), + .i_Wcxr_imag_0_5(Wcxr_imag_0_5), + .i_Wixr_real_0_6(Wixr_real_0_6), + .i_Wixr_imag_0_6(Wixr_imag_0_6), + .i_Wfxr_real_0_6(Wfxr_real_0_6), + .i_Wfxr_imag_0_6(Wfxr_imag_0_6), + .i_Woxr_real_0_6(Woxr_real_0_6), + .i_Woxr_imag_0_6(Woxr_imag_0_6), + .i_Wcxr_real_0_6(Wcxr_real_0_6), + .i_Wcxr_imag_0_6(Wcxr_imag_0_6), + .i_Wixr_real_0_7(Wixr_real_0_7), + .i_Wixr_imag_0_7(Wixr_imag_0_7), + .i_Wfxr_real_0_7(Wfxr_real_0_7), + .i_Wfxr_imag_0_7(Wfxr_imag_0_7), + .i_Woxr_real_0_7(Woxr_real_0_7), + .i_Woxr_imag_0_7(Woxr_imag_0_7), + .i_Wcxr_real_0_7(Wcxr_real_0_7), + .i_Wcxr_imag_0_7(Wcxr_imag_0_7), + .i_Wixr_real_0_8(Wixr_real_0_8), + .i_Wixr_imag_0_8(Wixr_imag_0_8), + .i_Wfxr_real_0_8(Wfxr_real_0_8), + .i_Wfxr_imag_0_8(Wfxr_imag_0_8), + .i_Woxr_real_0_8(Woxr_real_0_8), + .i_Woxr_imag_0_8(Woxr_imag_0_8), + .i_Wcxr_real_0_8(Wcxr_real_0_8), + .i_Wcxr_imag_0_8(Wcxr_imag_0_8), + .i_Wixr_real_1_0(Wixr_real_1_0), + .i_Wixr_imag_1_0(Wixr_imag_1_0), + .i_Wfxr_real_1_0(Wfxr_real_1_0), + .i_Wfxr_imag_1_0(Wfxr_imag_1_0), + .i_Woxr_real_1_0(Woxr_real_1_0), + .i_Woxr_imag_1_0(Woxr_imag_1_0), + .i_Wcxr_real_1_0(Wcxr_real_1_0), + .i_Wcxr_imag_1_0(Wcxr_imag_1_0), + .i_Wixr_real_1_1(Wixr_real_1_1), + .i_Wixr_imag_1_1(Wixr_imag_1_1), + .i_Wfxr_real_1_1(Wfxr_real_1_1), + .i_Wfxr_imag_1_1(Wfxr_imag_1_1), + .i_Woxr_real_1_1(Woxr_real_1_1), + .i_Woxr_imag_1_1(Woxr_imag_1_1), + .i_Wcxr_real_1_1(Wcxr_real_1_1), + .i_Wcxr_imag_1_1(Wcxr_imag_1_1), + .i_Wixr_real_1_2(Wixr_real_1_2), + .i_Wixr_imag_1_2(Wixr_imag_1_2), + .i_Wfxr_real_1_2(Wfxr_real_1_2), + .i_Wfxr_imag_1_2(Wfxr_imag_1_2), + .i_Woxr_real_1_2(Woxr_real_1_2), + .i_Woxr_imag_1_2(Woxr_imag_1_2), + .i_Wcxr_real_1_2(Wcxr_real_1_2), + .i_Wcxr_imag_1_2(Wcxr_imag_1_2), + .i_Wixr_real_1_3(Wixr_real_1_3), + .i_Wixr_imag_1_3(Wixr_imag_1_3), + .i_Wfxr_real_1_3(Wfxr_real_1_3), + .i_Wfxr_imag_1_3(Wfxr_imag_1_3), + .i_Woxr_real_1_3(Woxr_real_1_3), + .i_Woxr_imag_1_3(Woxr_imag_1_3), + .i_Wcxr_real_1_3(Wcxr_real_1_3), + .i_Wcxr_imag_1_3(Wcxr_imag_1_3), + .i_Wixr_real_1_4(Wixr_real_1_4), + .i_Wixr_imag_1_4(Wixr_imag_1_4), + .i_Wfxr_real_1_4(Wfxr_real_1_4), + .i_Wfxr_imag_1_4(Wfxr_imag_1_4), + .i_Woxr_real_1_4(Woxr_real_1_4), + .i_Woxr_imag_1_4(Woxr_imag_1_4), + .i_Wcxr_real_1_4(Wcxr_real_1_4), + .i_Wcxr_imag_1_4(Wcxr_imag_1_4), + .i_Wixr_real_1_5(Wixr_real_1_5), + .i_Wixr_imag_1_5(Wixr_imag_1_5), + .i_Wfxr_real_1_5(Wfxr_real_1_5), + .i_Wfxr_imag_1_5(Wfxr_imag_1_5), + .i_Woxr_real_1_5(Woxr_real_1_5), + .i_Woxr_imag_1_5(Woxr_imag_1_5), + .i_Wcxr_real_1_5(Wcxr_real_1_5), + .i_Wcxr_imag_1_5(Wcxr_imag_1_5), + .i_Wixr_real_1_6(Wixr_real_1_6), + .i_Wixr_imag_1_6(Wixr_imag_1_6), + .i_Wfxr_real_1_6(Wfxr_real_1_6), + .i_Wfxr_imag_1_6(Wfxr_imag_1_6), + .i_Woxr_real_1_6(Woxr_real_1_6), + .i_Woxr_imag_1_6(Woxr_imag_1_6), + .i_Wcxr_real_1_6(Wcxr_real_1_6), + .i_Wcxr_imag_1_6(Wcxr_imag_1_6), + .i_Wixr_real_1_7(Wixr_real_1_7), + .i_Wixr_imag_1_7(Wixr_imag_1_7), + .i_Wfxr_real_1_7(Wfxr_real_1_7), + .i_Wfxr_imag_1_7(Wfxr_imag_1_7), + .i_Woxr_real_1_7(Woxr_real_1_7), + .i_Woxr_imag_1_7(Woxr_imag_1_7), + .i_Wcxr_real_1_7(Wcxr_real_1_7), + .i_Wcxr_imag_1_7(Wcxr_imag_1_7), + .i_Wixr_real_1_8(Wixr_real_1_8), + .i_Wixr_imag_1_8(Wixr_imag_1_8), + .i_Wfxr_real_1_8(Wfxr_real_1_8), + .i_Wfxr_imag_1_8(Wfxr_imag_1_8), + .i_Woxr_real_1_8(Woxr_real_1_8), + .i_Woxr_imag_1_8(Woxr_imag_1_8), + .i_Wcxr_real_1_8(Wcxr_real_1_8), + .i_Wcxr_imag_1_8(Wcxr_imag_1_8), + .o_valid(stage1_valid), + .o_ready(stage1_ready), + .o_WixrXtYt_1_0_0(WixrXtYt_1_0_0), + .o_WfxrXtYt_1_0_0(WfxrXtYt_1_0_0), + .o_WoxrXtYt_1_0_0(WoxrXtYt_1_0_0), + .o_WcxrXtYt_1_0_0(WcxrXtYt_1_0_0), + .o_WixrXtYt_1_0_1(WixrXtYt_1_0_1), + .o_WfxrXtYt_1_0_1(WfxrXtYt_1_0_1), + .o_WoxrXtYt_1_0_1(WoxrXtYt_1_0_1), + .o_WcxrXtYt_1_0_1(WcxrXtYt_1_0_1), + .o_WixrXtYt_1_0_2(WixrXtYt_1_0_2), + .o_WfxrXtYt_1_0_2(WfxrXtYt_1_0_2), + .o_WoxrXtYt_1_0_2(WoxrXtYt_1_0_2), + .o_WcxrXtYt_1_0_2(WcxrXtYt_1_0_2), + .o_WixrXtYt_1_0_3(WixrXtYt_1_0_3), + .o_WfxrXtYt_1_0_3(WfxrXtYt_1_0_3), + .o_WoxrXtYt_1_0_3(WoxrXtYt_1_0_3), + .o_WcxrXtYt_1_0_3(WcxrXtYt_1_0_3), + .o_WixrXtYt_1_0_4(WixrXtYt_1_0_4), + .o_WfxrXtYt_1_0_4(WfxrXtYt_1_0_4), + .o_WoxrXtYt_1_0_4(WoxrXtYt_1_0_4), + .o_WcxrXtYt_1_0_4(WcxrXtYt_1_0_4), + .o_WixrXtYt_1_0_5(WixrXtYt_1_0_5), + .o_WfxrXtYt_1_0_5(WfxrXtYt_1_0_5), + .o_WoxrXtYt_1_0_5(WoxrXtYt_1_0_5), + .o_WcxrXtYt_1_0_5(WcxrXtYt_1_0_5), + .o_WixrXtYt_1_0_6(WixrXtYt_1_0_6), + .o_WfxrXtYt_1_0_6(WfxrXtYt_1_0_6), + .o_WoxrXtYt_1_0_6(WoxrXtYt_1_0_6), + .o_WcxrXtYt_1_0_6(WcxrXtYt_1_0_6), + .o_WixrXtYt_1_0_7(WixrXtYt_1_0_7), + .o_WfxrXtYt_1_0_7(WfxrXtYt_1_0_7), + .o_WoxrXtYt_1_0_7(WoxrXtYt_1_0_7), + .o_WcxrXtYt_1_0_7(WcxrXtYt_1_0_7), + .o_WixrXtYt_1_0_8(WixrXtYt_1_0_8), + .o_WfxrXtYt_1_0_8(WfxrXtYt_1_0_8), + .o_WoxrXtYt_1_0_8(WoxrXtYt_1_0_8), + .o_WcxrXtYt_1_0_8(WcxrXtYt_1_0_8), + .o_WixrXtYt_1_0_9(WixrXtYt_1_0_9), + .o_WfxrXtYt_1_0_9(WfxrXtYt_1_0_9), + .o_WoxrXtYt_1_0_9(WoxrXtYt_1_0_9), + .o_WcxrXtYt_1_0_9(WcxrXtYt_1_0_9), + .o_WixrXtYt_1_0_10(WixrXtYt_1_0_10), + .o_WfxrXtYt_1_0_10(WfxrXtYt_1_0_10), + .o_WoxrXtYt_1_0_10(WoxrXtYt_1_0_10), + .o_WcxrXtYt_1_0_10(WcxrXtYt_1_0_10), + .o_WixrXtYt_1_0_11(WixrXtYt_1_0_11), + .o_WfxrXtYt_1_0_11(WfxrXtYt_1_0_11), + .o_WoxrXtYt_1_0_11(WoxrXtYt_1_0_11), + .o_WcxrXtYt_1_0_11(WcxrXtYt_1_0_11), + .o_WixrXtYt_1_0_12(WixrXtYt_1_0_12), + .o_WfxrXtYt_1_0_12(WfxrXtYt_1_0_12), + .o_WoxrXtYt_1_0_12(WoxrXtYt_1_0_12), + .o_WcxrXtYt_1_0_12(WcxrXtYt_1_0_12), + .o_WixrXtYt_1_0_13(WixrXtYt_1_0_13), + .o_WfxrXtYt_1_0_13(WfxrXtYt_1_0_13), + .o_WoxrXtYt_1_0_13(WoxrXtYt_1_0_13), + .o_WcxrXtYt_1_0_13(WcxrXtYt_1_0_13), + .o_WixrXtYt_1_0_14(WixrXtYt_1_0_14), + .o_WfxrXtYt_1_0_14(WfxrXtYt_1_0_14), + .o_WoxrXtYt_1_0_14(WoxrXtYt_1_0_14), + .o_WcxrXtYt_1_0_14(WcxrXtYt_1_0_14), + .o_WixrXtYt_1_0_15(WixrXtYt_1_0_15), + .o_WfxrXtYt_1_0_15(WfxrXtYt_1_0_15), + .o_WoxrXtYt_1_0_15(WoxrXtYt_1_0_15), + .o_WcxrXtYt_1_0_15(WcxrXtYt_1_0_15), + .o_WixrXtYt_1_1_0(WixrXtYt_1_1_0), + .o_WfxrXtYt_1_1_0(WfxrXtYt_1_1_0), + .o_WoxrXtYt_1_1_0(WoxrXtYt_1_1_0), + .o_WcxrXtYt_1_1_0(WcxrXtYt_1_1_0), + .o_WixrXtYt_1_1_1(WixrXtYt_1_1_1), + .o_WfxrXtYt_1_1_1(WfxrXtYt_1_1_1), + .o_WoxrXtYt_1_1_1(WoxrXtYt_1_1_1), + .o_WcxrXtYt_1_1_1(WcxrXtYt_1_1_1), + .o_WixrXtYt_1_1_2(WixrXtYt_1_1_2), + .o_WfxrXtYt_1_1_2(WfxrXtYt_1_1_2), + .o_WoxrXtYt_1_1_2(WoxrXtYt_1_1_2), + .o_WcxrXtYt_1_1_2(WcxrXtYt_1_1_2), + .o_WixrXtYt_1_1_3(WixrXtYt_1_1_3), + .o_WfxrXtYt_1_1_3(WfxrXtYt_1_1_3), + .o_WoxrXtYt_1_1_3(WoxrXtYt_1_1_3), + .o_WcxrXtYt_1_1_3(WcxrXtYt_1_1_3), + .o_WixrXtYt_1_1_4(WixrXtYt_1_1_4), + .o_WfxrXtYt_1_1_4(WfxrXtYt_1_1_4), + .o_WoxrXtYt_1_1_4(WoxrXtYt_1_1_4), + .o_WcxrXtYt_1_1_4(WcxrXtYt_1_1_4), + .o_WixrXtYt_1_1_5(WixrXtYt_1_1_5), + .o_WfxrXtYt_1_1_5(WfxrXtYt_1_1_5), + .o_WoxrXtYt_1_1_5(WoxrXtYt_1_1_5), + .o_WcxrXtYt_1_1_5(WcxrXtYt_1_1_5), + .o_WixrXtYt_1_1_6(WixrXtYt_1_1_6), + .o_WfxrXtYt_1_1_6(WfxrXtYt_1_1_6), + .o_WoxrXtYt_1_1_6(WoxrXtYt_1_1_6), + .o_WcxrXtYt_1_1_6(WcxrXtYt_1_1_6), + .o_WixrXtYt_1_1_7(WixrXtYt_1_1_7), + .o_WfxrXtYt_1_1_7(WfxrXtYt_1_1_7), + .o_WoxrXtYt_1_1_7(WoxrXtYt_1_1_7), + .o_WcxrXtYt_1_1_7(WcxrXtYt_1_1_7), + .o_WixrXtYt_1_1_8(WixrXtYt_1_1_8), + .o_WfxrXtYt_1_1_8(WfxrXtYt_1_1_8), + .o_WoxrXtYt_1_1_8(WoxrXtYt_1_1_8), + .o_WcxrXtYt_1_1_8(WcxrXtYt_1_1_8), + .o_WixrXtYt_1_1_9(WixrXtYt_1_1_9), + .o_WfxrXtYt_1_1_9(WfxrXtYt_1_1_9), + .o_WoxrXtYt_1_1_9(WoxrXtYt_1_1_9), + .o_WcxrXtYt_1_1_9(WcxrXtYt_1_1_9), + .o_WixrXtYt_1_1_10(WixrXtYt_1_1_10), + .o_WfxrXtYt_1_1_10(WfxrXtYt_1_1_10), + .o_WoxrXtYt_1_1_10(WoxrXtYt_1_1_10), + .o_WcxrXtYt_1_1_10(WcxrXtYt_1_1_10), + .o_WixrXtYt_1_1_11(WixrXtYt_1_1_11), + .o_WfxrXtYt_1_1_11(WfxrXtYt_1_1_11), + .o_WoxrXtYt_1_1_11(WoxrXtYt_1_1_11), + .o_WcxrXtYt_1_1_11(WcxrXtYt_1_1_11), + .o_WixrXtYt_1_1_12(WixrXtYt_1_1_12), + .o_WfxrXtYt_1_1_12(WfxrXtYt_1_1_12), + .o_WoxrXtYt_1_1_12(WoxrXtYt_1_1_12), + .o_WcxrXtYt_1_1_12(WcxrXtYt_1_1_12), + .o_WixrXtYt_1_1_13(WixrXtYt_1_1_13), + .o_WfxrXtYt_1_1_13(WfxrXtYt_1_1_13), + .o_WoxrXtYt_1_1_13(WoxrXtYt_1_1_13), + .o_WcxrXtYt_1_1_13(WcxrXtYt_1_1_13), + .o_WixrXtYt_1_1_14(WixrXtYt_1_1_14), + .o_WfxrXtYt_1_1_14(WfxrXtYt_1_1_14), + .o_WoxrXtYt_1_1_14(WoxrXtYt_1_1_14), + .o_WcxrXtYt_1_1_14(WcxrXtYt_1_1_14), + .o_WixrXtYt_1_1_15(WixrXtYt_1_1_15), + .o_WfxrXtYt_1_1_15(WfxrXtYt_1_1_15), + .o_WoxrXtYt_1_1_15(WoxrXtYt_1_1_15), + .o_WcxrXtYt_1_1_15(WcxrXtYt_1_1_15), + .i_valid(i_valid_hold) +); + +// Stage 2 connections and parameter buffer +wire stage2_valid, stage2_ready, stage1_valid_hold; +wire [17:0] Ctt_1_0; +wire [17:0] stage2_Ct_0; +wire [17:0] stage2_mt_0; +wire [17:0] WixrXtYt_1_packed_0; +wire [17:0] WfxrXtYt_1_packed_0; +wire [17:0] WoxrXtYt_1_packed_0; +wire [17:0] WcxrXtYt_1_packed_0; +wire [17:0] WixrXtYt_1_hold_0; +wire [17:0] WfxrXtYt_1_hold_0; +wire [17:0] WoxrXtYt_1_hold_0; +wire [17:0] WcxrXtYt_1_hold_0; +wire [17:0] Wic_0; +wire [17:0] bi_0; +wire [17:0] Wfc_0; +wire [17:0] bf_0; +wire [17:0] Woc_0; +wire [17:0] bo_0; +wire [17:0] bc_0; +wire [17:0] Ctt_1_1; +wire [17:0] stage2_Ct_1; +wire [17:0] stage2_mt_1; +wire [17:0] WixrXtYt_1_packed_1; +wire [17:0] WfxrXtYt_1_packed_1; +wire [17:0] WoxrXtYt_1_packed_1; +wire [17:0] WcxrXtYt_1_packed_1; +wire [17:0] WixrXtYt_1_hold_1; +wire [17:0] WfxrXtYt_1_hold_1; +wire [17:0] WoxrXtYt_1_hold_1; +wire [17:0] WcxrXtYt_1_hold_1; +wire [17:0] Wic_1; +wire [17:0] bi_1; +wire [17:0] Wfc_1; +wire [17:0] bf_1; +wire [17:0] Woc_1; +wire [17:0] bo_1; +wire [17:0] bc_1; +wire [17:0] Ctt_1_2; +wire [17:0] stage2_Ct_2; +wire [17:0] stage2_mt_2; +wire [17:0] WixrXtYt_1_packed_2; +wire [17:0] WfxrXtYt_1_packed_2; +wire [17:0] WoxrXtYt_1_packed_2; +wire [17:0] WcxrXtYt_1_packed_2; +wire [17:0] WixrXtYt_1_hold_2; +wire [17:0] WfxrXtYt_1_hold_2; +wire [17:0] WoxrXtYt_1_hold_2; +wire [17:0] WcxrXtYt_1_hold_2; +wire [17:0] Wic_2; +wire [17:0] bi_2; +wire [17:0] Wfc_2; +wire [17:0] bf_2; +wire [17:0] Woc_2; +wire [17:0] bo_2; +wire [17:0] bc_2; +wire [17:0] Ctt_1_3; +wire [17:0] stage2_Ct_3; +wire [17:0] stage2_mt_3; +wire [17:0] WixrXtYt_1_packed_3; +wire [17:0] WfxrXtYt_1_packed_3; +wire [17:0] WoxrXtYt_1_packed_3; +wire [17:0] WcxrXtYt_1_packed_3; +wire [17:0] WixrXtYt_1_hold_3; +wire [17:0] WfxrXtYt_1_hold_3; +wire [17:0] WoxrXtYt_1_hold_3; +wire [17:0] WcxrXtYt_1_hold_3; +wire [17:0] Wic_3; +wire [17:0] bi_3; +wire [17:0] Wfc_3; +wire [17:0] bf_3; +wire [17:0] Woc_3; +wire [17:0] bo_3; +wire [17:0] bc_3; +wire [17:0] Ctt_1_4; +wire [17:0] stage2_Ct_4; +wire [17:0] stage2_mt_4; +wire [17:0] WixrXtYt_1_packed_4; +wire [17:0] WfxrXtYt_1_packed_4; +wire [17:0] WoxrXtYt_1_packed_4; +wire [17:0] WcxrXtYt_1_packed_4; +wire [17:0] WixrXtYt_1_hold_4; +wire [17:0] WfxrXtYt_1_hold_4; +wire [17:0] WoxrXtYt_1_hold_4; +wire [17:0] WcxrXtYt_1_hold_4; +wire [17:0] Wic_4; +wire [17:0] bi_4; +wire [17:0] Wfc_4; +wire [17:0] bf_4; +wire [17:0] Woc_4; +wire [17:0] bo_4; +wire [17:0] bc_4; +wire [17:0] Ctt_1_5; +wire [17:0] stage2_Ct_5; +wire [17:0] stage2_mt_5; +wire [17:0] WixrXtYt_1_packed_5; +wire [17:0] WfxrXtYt_1_packed_5; +wire [17:0] WoxrXtYt_1_packed_5; +wire [17:0] WcxrXtYt_1_packed_5; +wire [17:0] WixrXtYt_1_hold_5; +wire [17:0] WfxrXtYt_1_hold_5; +wire [17:0] WoxrXtYt_1_hold_5; +wire [17:0] WcxrXtYt_1_hold_5; +wire [17:0] Wic_5; +wire [17:0] bi_5; +wire [17:0] Wfc_5; +wire [17:0] bf_5; +wire [17:0] Woc_5; +wire [17:0] bo_5; +wire [17:0] bc_5; +wire [17:0] Ctt_1_6; +wire [17:0] stage2_Ct_6; +wire [17:0] stage2_mt_6; +wire [17:0] WixrXtYt_1_packed_6; +wire [17:0] WfxrXtYt_1_packed_6; +wire [17:0] WoxrXtYt_1_packed_6; +wire [17:0] WcxrXtYt_1_packed_6; +wire [17:0] WixrXtYt_1_hold_6; +wire [17:0] WfxrXtYt_1_hold_6; +wire [17:0] WoxrXtYt_1_hold_6; +wire [17:0] WcxrXtYt_1_hold_6; +wire [17:0] Wic_6; +wire [17:0] bi_6; +wire [17:0] Wfc_6; +wire [17:0] bf_6; +wire [17:0] Woc_6; +wire [17:0] bo_6; +wire [17:0] bc_6; +wire [17:0] Ctt_1_7; +wire [17:0] stage2_Ct_7; +wire [17:0] stage2_mt_7; +wire [17:0] WixrXtYt_1_packed_7; +wire [17:0] WfxrXtYt_1_packed_7; +wire [17:0] WoxrXtYt_1_packed_7; +wire [17:0] WcxrXtYt_1_packed_7; +wire [17:0] WixrXtYt_1_hold_7; +wire [17:0] WfxrXtYt_1_hold_7; +wire [17:0] WoxrXtYt_1_hold_7; +wire [17:0] WcxrXtYt_1_hold_7; +wire [17:0] Wic_7; +wire [17:0] bi_7; +wire [17:0] Wfc_7; +wire [17:0] bf_7; +wire [17:0] Woc_7; +wire [17:0] bo_7; +wire [17:0] bc_7; +wire [17:0] Ctt_1_8; +wire [17:0] stage2_Ct_8; +wire [17:0] stage2_mt_8; +wire [17:0] WixrXtYt_1_packed_8; +wire [17:0] WfxrXtYt_1_packed_8; +wire [17:0] WoxrXtYt_1_packed_8; +wire [17:0] WcxrXtYt_1_packed_8; +wire [17:0] WixrXtYt_1_hold_8; +wire [17:0] WfxrXtYt_1_hold_8; +wire [17:0] WoxrXtYt_1_hold_8; +wire [17:0] WcxrXtYt_1_hold_8; +wire [17:0] Wic_8; +wire [17:0] bi_8; +wire [17:0] Wfc_8; +wire [17:0] bf_8; +wire [17:0] Woc_8; +wire [17:0] bo_8; +wire [17:0] bc_8; +wire [17:0] Ctt_1_9; +wire [17:0] stage2_Ct_9; +wire [17:0] stage2_mt_9; +wire [17:0] WixrXtYt_1_packed_9; +wire [17:0] WfxrXtYt_1_packed_9; +wire [17:0] WoxrXtYt_1_packed_9; +wire [17:0] WcxrXtYt_1_packed_9; +wire [17:0] WixrXtYt_1_hold_9; +wire [17:0] WfxrXtYt_1_hold_9; +wire [17:0] WoxrXtYt_1_hold_9; +wire [17:0] WcxrXtYt_1_hold_9; +wire [17:0] Wic_9; +wire [17:0] bi_9; +wire [17:0] Wfc_9; +wire [17:0] bf_9; +wire [17:0] Woc_9; +wire [17:0] bo_9; +wire [17:0] bc_9; +wire [17:0] Ctt_1_10; +wire [17:0] stage2_Ct_10; +wire [17:0] stage2_mt_10; +wire [17:0] WixrXtYt_1_packed_10; +wire [17:0] WfxrXtYt_1_packed_10; +wire [17:0] WoxrXtYt_1_packed_10; +wire [17:0] WcxrXtYt_1_packed_10; +wire [17:0] WixrXtYt_1_hold_10; +wire [17:0] WfxrXtYt_1_hold_10; +wire [17:0] WoxrXtYt_1_hold_10; +wire [17:0] WcxrXtYt_1_hold_10; +wire [17:0] Wic_10; +wire [17:0] bi_10; +wire [17:0] Wfc_10; +wire [17:0] bf_10; +wire [17:0] Woc_10; +wire [17:0] bo_10; +wire [17:0] bc_10; +wire [17:0] Ctt_1_11; +wire [17:0] stage2_Ct_11; +wire [17:0] stage2_mt_11; +wire [17:0] WixrXtYt_1_packed_11; +wire [17:0] WfxrXtYt_1_packed_11; +wire [17:0] WoxrXtYt_1_packed_11; +wire [17:0] WcxrXtYt_1_packed_11; +wire [17:0] WixrXtYt_1_hold_11; +wire [17:0] WfxrXtYt_1_hold_11; +wire [17:0] WoxrXtYt_1_hold_11; +wire [17:0] WcxrXtYt_1_hold_11; +wire [17:0] Wic_11; +wire [17:0] bi_11; +wire [17:0] Wfc_11; +wire [17:0] bf_11; +wire [17:0] Woc_11; +wire [17:0] bo_11; +wire [17:0] bc_11; +wire [17:0] Ctt_1_12; +wire [17:0] stage2_Ct_12; +wire [17:0] stage2_mt_12; +wire [17:0] WixrXtYt_1_packed_12; +wire [17:0] WfxrXtYt_1_packed_12; +wire [17:0] WoxrXtYt_1_packed_12; +wire [17:0] WcxrXtYt_1_packed_12; +wire [17:0] WixrXtYt_1_hold_12; +wire [17:0] WfxrXtYt_1_hold_12; +wire [17:0] WoxrXtYt_1_hold_12; +wire [17:0] WcxrXtYt_1_hold_12; +wire [17:0] Wic_12; +wire [17:0] bi_12; +wire [17:0] Wfc_12; +wire [17:0] bf_12; +wire [17:0] Woc_12; +wire [17:0] bo_12; +wire [17:0] bc_12; +wire [17:0] Ctt_1_13; +wire [17:0] stage2_Ct_13; +wire [17:0] stage2_mt_13; +wire [17:0] WixrXtYt_1_packed_13; +wire [17:0] WfxrXtYt_1_packed_13; +wire [17:0] WoxrXtYt_1_packed_13; +wire [17:0] WcxrXtYt_1_packed_13; +wire [17:0] WixrXtYt_1_hold_13; +wire [17:0] WfxrXtYt_1_hold_13; +wire [17:0] WoxrXtYt_1_hold_13; +wire [17:0] WcxrXtYt_1_hold_13; +wire [17:0] Wic_13; +wire [17:0] bi_13; +wire [17:0] Wfc_13; +wire [17:0] bf_13; +wire [17:0] Woc_13; +wire [17:0] bo_13; +wire [17:0] bc_13; +wire [17:0] Ctt_1_14; +wire [17:0] stage2_Ct_14; +wire [17:0] stage2_mt_14; +wire [17:0] WixrXtYt_1_packed_14; +wire [17:0] WfxrXtYt_1_packed_14; +wire [17:0] WoxrXtYt_1_packed_14; +wire [17:0] WcxrXtYt_1_packed_14; +wire [17:0] WixrXtYt_1_hold_14; +wire [17:0] WfxrXtYt_1_hold_14; +wire [17:0] WoxrXtYt_1_hold_14; +wire [17:0] WcxrXtYt_1_hold_14; +wire [17:0] Wic_14; +wire [17:0] bi_14; +wire [17:0] Wfc_14; +wire [17:0] bf_14; +wire [17:0] Woc_14; +wire [17:0] bo_14; +wire [17:0] bc_14; +wire [17:0] Ctt_1_15; +wire [17:0] stage2_Ct_15; +wire [17:0] stage2_mt_15; +wire [17:0] WixrXtYt_1_packed_15; +wire [17:0] WfxrXtYt_1_packed_15; +wire [17:0] WoxrXtYt_1_packed_15; +wire [17:0] WcxrXtYt_1_packed_15; +wire [17:0] WixrXtYt_1_hold_15; +wire [17:0] WfxrXtYt_1_hold_15; +wire [17:0] WoxrXtYt_1_hold_15; +wire [17:0] WcxrXtYt_1_hold_15; +wire [17:0] Wic_15; +wire [17:0] bi_15; +wire [17:0] Wfc_15; +wire [17:0] bf_15; +wire [17:0] Woc_15; +wire [17:0] bo_15; +wire [17:0] bc_15; +wire [17:0] Ctt_1_16; +wire [17:0] stage2_Ct_16; +wire [17:0] stage2_mt_16; +wire [17:0] WixrXtYt_1_packed_16; +wire [17:0] WfxrXtYt_1_packed_16; +wire [17:0] WoxrXtYt_1_packed_16; +wire [17:0] WcxrXtYt_1_packed_16; +wire [17:0] WixrXtYt_1_hold_16; +wire [17:0] WfxrXtYt_1_hold_16; +wire [17:0] WoxrXtYt_1_hold_16; +wire [17:0] WcxrXtYt_1_hold_16; +wire [17:0] Wic_16; +wire [17:0] bi_16; +wire [17:0] Wfc_16; +wire [17:0] bf_16; +wire [17:0] Woc_16; +wire [17:0] bo_16; +wire [17:0] bc_16; +wire [17:0] Ctt_1_17; +wire [17:0] stage2_Ct_17; +wire [17:0] stage2_mt_17; +wire [17:0] WixrXtYt_1_packed_17; +wire [17:0] WfxrXtYt_1_packed_17; +wire [17:0] WoxrXtYt_1_packed_17; +wire [17:0] WcxrXtYt_1_packed_17; +wire [17:0] WixrXtYt_1_hold_17; +wire [17:0] WfxrXtYt_1_hold_17; +wire [17:0] WoxrXtYt_1_hold_17; +wire [17:0] WcxrXtYt_1_hold_17; +wire [17:0] Wic_17; +wire [17:0] bi_17; +wire [17:0] Wfc_17; +wire [17:0] bf_17; +wire [17:0] Woc_17; +wire [17:0] bo_17; +wire [17:0] bc_17; +wire [17:0] Ctt_1_18; +wire [17:0] stage2_Ct_18; +wire [17:0] stage2_mt_18; +wire [17:0] WixrXtYt_1_packed_18; +wire [17:0] WfxrXtYt_1_packed_18; +wire [17:0] WoxrXtYt_1_packed_18; +wire [17:0] WcxrXtYt_1_packed_18; +wire [17:0] WixrXtYt_1_hold_18; +wire [17:0] WfxrXtYt_1_hold_18; +wire [17:0] WoxrXtYt_1_hold_18; +wire [17:0] WcxrXtYt_1_hold_18; +wire [17:0] Wic_18; +wire [17:0] bi_18; +wire [17:0] Wfc_18; +wire [17:0] bf_18; +wire [17:0] Woc_18; +wire [17:0] bo_18; +wire [17:0] bc_18; +wire [17:0] Ctt_1_19; +wire [17:0] stage2_Ct_19; +wire [17:0] stage2_mt_19; +wire [17:0] WixrXtYt_1_packed_19; +wire [17:0] WfxrXtYt_1_packed_19; +wire [17:0] WoxrXtYt_1_packed_19; +wire [17:0] WcxrXtYt_1_packed_19; +wire [17:0] WixrXtYt_1_hold_19; +wire [17:0] WfxrXtYt_1_hold_19; +wire [17:0] WoxrXtYt_1_hold_19; +wire [17:0] WcxrXtYt_1_hold_19; +wire [17:0] Wic_19; +wire [17:0] bi_19; +wire [17:0] Wfc_19; +wire [17:0] bf_19; +wire [17:0] Woc_19; +wire [17:0] bo_19; +wire [17:0] bc_19; +wire [17:0] Ctt_1_20; +wire [17:0] stage2_Ct_20; +wire [17:0] stage2_mt_20; +wire [17:0] WixrXtYt_1_packed_20; +wire [17:0] WfxrXtYt_1_packed_20; +wire [17:0] WoxrXtYt_1_packed_20; +wire [17:0] WcxrXtYt_1_packed_20; +wire [17:0] WixrXtYt_1_hold_20; +wire [17:0] WfxrXtYt_1_hold_20; +wire [17:0] WoxrXtYt_1_hold_20; +wire [17:0] WcxrXtYt_1_hold_20; +wire [17:0] Wic_20; +wire [17:0] bi_20; +wire [17:0] Wfc_20; +wire [17:0] bf_20; +wire [17:0] Woc_20; +wire [17:0] bo_20; +wire [17:0] bc_20; +wire [17:0] Ctt_1_21; +wire [17:0] stage2_Ct_21; +wire [17:0] stage2_mt_21; +wire [17:0] WixrXtYt_1_packed_21; +wire [17:0] WfxrXtYt_1_packed_21; +wire [17:0] WoxrXtYt_1_packed_21; +wire [17:0] WcxrXtYt_1_packed_21; +wire [17:0] WixrXtYt_1_hold_21; +wire [17:0] WfxrXtYt_1_hold_21; +wire [17:0] WoxrXtYt_1_hold_21; +wire [17:0] WcxrXtYt_1_hold_21; +wire [17:0] Wic_21; +wire [17:0] bi_21; +wire [17:0] Wfc_21; +wire [17:0] bf_21; +wire [17:0] Woc_21; +wire [17:0] bo_21; +wire [17:0] bc_21; +wire [17:0] Ctt_1_22; +wire [17:0] stage2_Ct_22; +wire [17:0] stage2_mt_22; +wire [17:0] WixrXtYt_1_packed_22; +wire [17:0] WfxrXtYt_1_packed_22; +wire [17:0] WoxrXtYt_1_packed_22; +wire [17:0] WcxrXtYt_1_packed_22; +wire [17:0] WixrXtYt_1_hold_22; +wire [17:0] WfxrXtYt_1_hold_22; +wire [17:0] WoxrXtYt_1_hold_22; +wire [17:0] WcxrXtYt_1_hold_22; +wire [17:0] Wic_22; +wire [17:0] bi_22; +wire [17:0] Wfc_22; +wire [17:0] bf_22; +wire [17:0] Woc_22; +wire [17:0] bo_22; +wire [17:0] bc_22; +wire [17:0] Ctt_1_23; +wire [17:0] stage2_Ct_23; +wire [17:0] stage2_mt_23; +wire [17:0] WixrXtYt_1_packed_23; +wire [17:0] WfxrXtYt_1_packed_23; +wire [17:0] WoxrXtYt_1_packed_23; +wire [17:0] WcxrXtYt_1_packed_23; +wire [17:0] WixrXtYt_1_hold_23; +wire [17:0] WfxrXtYt_1_hold_23; +wire [17:0] WoxrXtYt_1_hold_23; +wire [17:0] WcxrXtYt_1_hold_23; +wire [17:0] Wic_23; +wire [17:0] bi_23; +wire [17:0] Wfc_23; +wire [17:0] bf_23; +wire [17:0] Woc_23; +wire [17:0] bo_23; +wire [17:0] bc_23; +wire [17:0] Ctt_1_24; +wire [17:0] stage2_Ct_24; +wire [17:0] stage2_mt_24; +wire [17:0] WixrXtYt_1_packed_24; +wire [17:0] WfxrXtYt_1_packed_24; +wire [17:0] WoxrXtYt_1_packed_24; +wire [17:0] WcxrXtYt_1_packed_24; +wire [17:0] WixrXtYt_1_hold_24; +wire [17:0] WfxrXtYt_1_hold_24; +wire [17:0] WoxrXtYt_1_hold_24; +wire [17:0] WcxrXtYt_1_hold_24; +wire [17:0] Wic_24; +wire [17:0] bi_24; +wire [17:0] Wfc_24; +wire [17:0] bf_24; +wire [17:0] Woc_24; +wire [17:0] bo_24; +wire [17:0] bc_24; +wire [17:0] Ctt_1_25; +wire [17:0] stage2_Ct_25; +wire [17:0] stage2_mt_25; +wire [17:0] WixrXtYt_1_packed_25; +wire [17:0] WfxrXtYt_1_packed_25; +wire [17:0] WoxrXtYt_1_packed_25; +wire [17:0] WcxrXtYt_1_packed_25; +wire [17:0] WixrXtYt_1_hold_25; +wire [17:0] WfxrXtYt_1_hold_25; +wire [17:0] WoxrXtYt_1_hold_25; +wire [17:0] WcxrXtYt_1_hold_25; +wire [17:0] Wic_25; +wire [17:0] bi_25; +wire [17:0] Wfc_25; +wire [17:0] bf_25; +wire [17:0] Woc_25; +wire [17:0] bo_25; +wire [17:0] bc_25; +wire [17:0] Ctt_1_26; +wire [17:0] stage2_Ct_26; +wire [17:0] stage2_mt_26; +wire [17:0] WixrXtYt_1_packed_26; +wire [17:0] WfxrXtYt_1_packed_26; +wire [17:0] WoxrXtYt_1_packed_26; +wire [17:0] WcxrXtYt_1_packed_26; +wire [17:0] WixrXtYt_1_hold_26; +wire [17:0] WfxrXtYt_1_hold_26; +wire [17:0] WoxrXtYt_1_hold_26; +wire [17:0] WcxrXtYt_1_hold_26; +wire [17:0] Wic_26; +wire [17:0] bi_26; +wire [17:0] Wfc_26; +wire [17:0] bf_26; +wire [17:0] Woc_26; +wire [17:0] bo_26; +wire [17:0] bc_26; +wire [17:0] Ctt_1_27; +wire [17:0] stage2_Ct_27; +wire [17:0] stage2_mt_27; +wire [17:0] WixrXtYt_1_packed_27; +wire [17:0] WfxrXtYt_1_packed_27; +wire [17:0] WoxrXtYt_1_packed_27; +wire [17:0] WcxrXtYt_1_packed_27; +wire [17:0] WixrXtYt_1_hold_27; +wire [17:0] WfxrXtYt_1_hold_27; +wire [17:0] WoxrXtYt_1_hold_27; +wire [17:0] WcxrXtYt_1_hold_27; +wire [17:0] Wic_27; +wire [17:0] bi_27; +wire [17:0] Wfc_27; +wire [17:0] bf_27; +wire [17:0] Woc_27; +wire [17:0] bo_27; +wire [17:0] bc_27; +wire [17:0] Ctt_1_28; +wire [17:0] stage2_Ct_28; +wire [17:0] stage2_mt_28; +wire [17:0] WixrXtYt_1_packed_28; +wire [17:0] WfxrXtYt_1_packed_28; +wire [17:0] WoxrXtYt_1_packed_28; +wire [17:0] WcxrXtYt_1_packed_28; +wire [17:0] WixrXtYt_1_hold_28; +wire [17:0] WfxrXtYt_1_hold_28; +wire [17:0] WoxrXtYt_1_hold_28; +wire [17:0] WcxrXtYt_1_hold_28; +wire [17:0] Wic_28; +wire [17:0] bi_28; +wire [17:0] Wfc_28; +wire [17:0] bf_28; +wire [17:0] Woc_28; +wire [17:0] bo_28; +wire [17:0] bc_28; +wire [17:0] Ctt_1_29; +wire [17:0] stage2_Ct_29; +wire [17:0] stage2_mt_29; +wire [17:0] WixrXtYt_1_packed_29; +wire [17:0] WfxrXtYt_1_packed_29; +wire [17:0] WoxrXtYt_1_packed_29; +wire [17:0] WcxrXtYt_1_packed_29; +wire [17:0] WixrXtYt_1_hold_29; +wire [17:0] WfxrXtYt_1_hold_29; +wire [17:0] WoxrXtYt_1_hold_29; +wire [17:0] WcxrXtYt_1_hold_29; +wire [17:0] Wic_29; +wire [17:0] bi_29; +wire [17:0] Wfc_29; +wire [17:0] bf_29; +wire [17:0] Woc_29; +wire [17:0] bo_29; +wire [17:0] bc_29; +wire [17:0] Ctt_1_30; +wire [17:0] stage2_Ct_30; +wire [17:0] stage2_mt_30; +wire [17:0] WixrXtYt_1_packed_30; +wire [17:0] WfxrXtYt_1_packed_30; +wire [17:0] WoxrXtYt_1_packed_30; +wire [17:0] WcxrXtYt_1_packed_30; +wire [17:0] WixrXtYt_1_hold_30; +wire [17:0] WfxrXtYt_1_hold_30; +wire [17:0] WoxrXtYt_1_hold_30; +wire [17:0] WcxrXtYt_1_hold_30; +wire [17:0] Wic_30; +wire [17:0] bi_30; +wire [17:0] Wfc_30; +wire [17:0] bf_30; +wire [17:0] Woc_30; +wire [17:0] bo_30; +wire [17:0] bc_30; +wire [17:0] Ctt_1_31; +wire [17:0] stage2_Ct_31; +wire [17:0] stage2_mt_31; +wire [17:0] WixrXtYt_1_packed_31; +wire [17:0] WfxrXtYt_1_packed_31; +wire [17:0] WoxrXtYt_1_packed_31; +wire [17:0] WcxrXtYt_1_packed_31; +wire [17:0] WixrXtYt_1_hold_31; +wire [17:0] WfxrXtYt_1_hold_31; +wire [17:0] WoxrXtYt_1_hold_31; +wire [17:0] WcxrXtYt_1_hold_31; +wire [17:0] Wic_31; +wire [17:0] bi_31; +wire [17:0] Wfc_31; +wire [17:0] bf_31; +wire [17:0] Woc_31; +wire [17:0] bo_31; +wire [17:0] bc_31; + +stage2_parameter_buffer_18_2_16_64 stage2_parameter_buffer_18_2_16_64_inst_grbpsoaxnv ( + .clk(clk), + .reset(reset), + .wdata(wdata_stage2), + .wen(wen_stage2), + .o_Wic_0(Wic_0), + .o_bi_0(bi_0), + .o_Wfc_0(Wfc_0), + .o_bf_0(bf_0), + .o_Woc_0(Woc_0), + .o_bo_0(bo_0), + .o_bc_0(bc_0), + .o_Wic_1(Wic_1), + .o_bi_1(bi_1), + .o_Wfc_1(Wfc_1), + .o_bf_1(bf_1), + .o_Woc_1(Woc_1), + .o_bo_1(bo_1), + .o_bc_1(bc_1), + .o_Wic_2(Wic_2), + .o_bi_2(bi_2), + .o_Wfc_2(Wfc_2), + .o_bf_2(bf_2), + .o_Woc_2(Woc_2), + .o_bo_2(bo_2), + .o_bc_2(bc_2), + .o_Wic_3(Wic_3), + .o_bi_3(bi_3), + .o_Wfc_3(Wfc_3), + .o_bf_3(bf_3), + .o_Woc_3(Woc_3), + .o_bo_3(bo_3), + .o_bc_3(bc_3), + .o_Wic_4(Wic_4), + .o_bi_4(bi_4), + .o_Wfc_4(Wfc_4), + .o_bf_4(bf_4), + .o_Woc_4(Woc_4), + .o_bo_4(bo_4), + .o_bc_4(bc_4), + .o_Wic_5(Wic_5), + .o_bi_5(bi_5), + .o_Wfc_5(Wfc_5), + .o_bf_5(bf_5), + .o_Woc_5(Woc_5), + .o_bo_5(bo_5), + .o_bc_5(bc_5), + .o_Wic_6(Wic_6), + .o_bi_6(bi_6), + .o_Wfc_6(Wfc_6), + .o_bf_6(bf_6), + .o_Woc_6(Woc_6), + .o_bo_6(bo_6), + .o_bc_6(bc_6), + .o_Wic_7(Wic_7), + .o_bi_7(bi_7), + .o_Wfc_7(Wfc_7), + .o_bf_7(bf_7), + .o_Woc_7(Woc_7), + .o_bo_7(bo_7), + .o_bc_7(bc_7), + .o_Wic_8(Wic_8), + .o_bi_8(bi_8), + .o_Wfc_8(Wfc_8), + .o_bf_8(bf_8), + .o_Woc_8(Woc_8), + .o_bo_8(bo_8), + .o_bc_8(bc_8), + .o_Wic_9(Wic_9), + .o_bi_9(bi_9), + .o_Wfc_9(Wfc_9), + .o_bf_9(bf_9), + .o_Woc_9(Woc_9), + .o_bo_9(bo_9), + .o_bc_9(bc_9), + .o_Wic_10(Wic_10), + .o_bi_10(bi_10), + .o_Wfc_10(Wfc_10), + .o_bf_10(bf_10), + .o_Woc_10(Woc_10), + .o_bo_10(bo_10), + .o_bc_10(bc_10), + .o_Wic_11(Wic_11), + .o_bi_11(bi_11), + .o_Wfc_11(Wfc_11), + .o_bf_11(bf_11), + .o_Woc_11(Woc_11), + .o_bo_11(bo_11), + .o_bc_11(bc_11), + .o_Wic_12(Wic_12), + .o_bi_12(bi_12), + .o_Wfc_12(Wfc_12), + .o_bf_12(bf_12), + .o_Woc_12(Woc_12), + .o_bo_12(bo_12), + .o_bc_12(bc_12), + .o_Wic_13(Wic_13), + .o_bi_13(bi_13), + .o_Wfc_13(Wfc_13), + .o_bf_13(bf_13), + .o_Woc_13(Woc_13), + .o_bo_13(bo_13), + .o_bc_13(bc_13), + .o_Wic_14(Wic_14), + .o_bi_14(bi_14), + .o_Wfc_14(Wfc_14), + .o_bf_14(bf_14), + .o_Woc_14(Woc_14), + .o_bo_14(bo_14), + .o_bc_14(bc_14), + .o_Wic_15(Wic_15), + .o_bi_15(bi_15), + .o_Wfc_15(Wfc_15), + .o_bf_15(bf_15), + .o_Woc_15(Woc_15), + .o_bo_15(bo_15), + .o_bc_15(bc_15), + .o_Wic_16(Wic_16), + .o_bi_16(bi_16), + .o_Wfc_16(Wfc_16), + .o_bf_16(bf_16), + .o_Woc_16(Woc_16), + .o_bo_16(bo_16), + .o_bc_16(bc_16), + .o_Wic_17(Wic_17), + .o_bi_17(bi_17), + .o_Wfc_17(Wfc_17), + .o_bf_17(bf_17), + .o_Woc_17(Woc_17), + .o_bo_17(bo_17), + .o_bc_17(bc_17), + .o_Wic_18(Wic_18), + .o_bi_18(bi_18), + .o_Wfc_18(Wfc_18), + .o_bf_18(bf_18), + .o_Woc_18(Woc_18), + .o_bo_18(bo_18), + .o_bc_18(bc_18), + .o_Wic_19(Wic_19), + .o_bi_19(bi_19), + .o_Wfc_19(Wfc_19), + .o_bf_19(bf_19), + .o_Woc_19(Woc_19), + .o_bo_19(bo_19), + .o_bc_19(bc_19), + .o_Wic_20(Wic_20), + .o_bi_20(bi_20), + .o_Wfc_20(Wfc_20), + .o_bf_20(bf_20), + .o_Woc_20(Woc_20), + .o_bo_20(bo_20), + .o_bc_20(bc_20), + .o_Wic_21(Wic_21), + .o_bi_21(bi_21), + .o_Wfc_21(Wfc_21), + .o_bf_21(bf_21), + .o_Woc_21(Woc_21), + .o_bo_21(bo_21), + .o_bc_21(bc_21), + .o_Wic_22(Wic_22), + .o_bi_22(bi_22), + .o_Wfc_22(Wfc_22), + .o_bf_22(bf_22), + .o_Woc_22(Woc_22), + .o_bo_22(bo_22), + .o_bc_22(bc_22), + .o_Wic_23(Wic_23), + .o_bi_23(bi_23), + .o_Wfc_23(Wfc_23), + .o_bf_23(bf_23), + .o_Woc_23(Woc_23), + .o_bo_23(bo_23), + .o_bc_23(bc_23), + .o_Wic_24(Wic_24), + .o_bi_24(bi_24), + .o_Wfc_24(Wfc_24), + .o_bf_24(bf_24), + .o_Woc_24(Woc_24), + .o_bo_24(bo_24), + .o_bc_24(bc_24), + .o_Wic_25(Wic_25), + .o_bi_25(bi_25), + .o_Wfc_25(Wfc_25), + .o_bf_25(bf_25), + .o_Woc_25(Woc_25), + .o_bo_25(bo_25), + .o_bc_25(bc_25), + .o_Wic_26(Wic_26), + .o_bi_26(bi_26), + .o_Wfc_26(Wfc_26), + .o_bf_26(bf_26), + .o_Woc_26(Woc_26), + .o_bo_26(bo_26), + .o_bc_26(bc_26), + .o_Wic_27(Wic_27), + .o_bi_27(bi_27), + .o_Wfc_27(Wfc_27), + .o_bf_27(bf_27), + .o_Woc_27(Woc_27), + .o_bo_27(bo_27), + .o_bc_27(bc_27), + .o_Wic_28(Wic_28), + .o_bi_28(bi_28), + .o_Wfc_28(Wfc_28), + .o_bf_28(bf_28), + .o_Woc_28(Woc_28), + .o_bo_28(bo_28), + .o_bc_28(bc_28), + .o_Wic_29(Wic_29), + .o_bi_29(bi_29), + .o_Wfc_29(Wfc_29), + .o_bf_29(bf_29), + .o_Woc_29(Woc_29), + .o_bo_29(bo_29), + .o_bc_29(bc_29), + .o_Wic_30(Wic_30), + .o_bi_30(bi_30), + .o_Wfc_30(Wfc_30), + .o_bf_30(bf_30), + .o_Woc_30(Woc_30), + .o_bo_30(bo_30), + .o_bc_30(bc_30), + .o_Wic_31(Wic_31), + .o_bi_31(bi_31), + .o_Wfc_31(Wfc_31), + .o_bf_31(bf_31), + .o_Woc_31(Woc_31), + .o_bo_31(bo_31), + .o_bc_31(bc_31), + .incr_index(stage1_valid) +); + +assign WixrXtYt_1_packed_0 = WixrXtYt_1_0_0; +assign WfxrXtYt_1_packed_0 = WfxrXtYt_1_0_0; +assign WoxrXtYt_1_packed_0 = WoxrXtYt_1_0_0; +assign WcxrXtYt_1_packed_0 = WcxrXtYt_1_0_0; +assign WixrXtYt_1_packed_1 = WixrXtYt_1_0_1; +assign WfxrXtYt_1_packed_1 = WfxrXtYt_1_0_1; +assign WoxrXtYt_1_packed_1 = WoxrXtYt_1_0_1; +assign WcxrXtYt_1_packed_1 = WcxrXtYt_1_0_1; +assign WixrXtYt_1_packed_2 = WixrXtYt_1_0_2; +assign WfxrXtYt_1_packed_2 = WfxrXtYt_1_0_2; +assign WoxrXtYt_1_packed_2 = WoxrXtYt_1_0_2; +assign WcxrXtYt_1_packed_2 = WcxrXtYt_1_0_2; +assign WixrXtYt_1_packed_3 = WixrXtYt_1_0_3; +assign WfxrXtYt_1_packed_3 = WfxrXtYt_1_0_3; +assign WoxrXtYt_1_packed_3 = WoxrXtYt_1_0_3; +assign WcxrXtYt_1_packed_3 = WcxrXtYt_1_0_3; +assign WixrXtYt_1_packed_4 = WixrXtYt_1_0_4; +assign WfxrXtYt_1_packed_4 = WfxrXtYt_1_0_4; +assign WoxrXtYt_1_packed_4 = WoxrXtYt_1_0_4; +assign WcxrXtYt_1_packed_4 = WcxrXtYt_1_0_4; +assign WixrXtYt_1_packed_5 = WixrXtYt_1_0_5; +assign WfxrXtYt_1_packed_5 = WfxrXtYt_1_0_5; +assign WoxrXtYt_1_packed_5 = WoxrXtYt_1_0_5; +assign WcxrXtYt_1_packed_5 = WcxrXtYt_1_0_5; +assign WixrXtYt_1_packed_6 = WixrXtYt_1_0_6; +assign WfxrXtYt_1_packed_6 = WfxrXtYt_1_0_6; +assign WoxrXtYt_1_packed_6 = WoxrXtYt_1_0_6; +assign WcxrXtYt_1_packed_6 = WcxrXtYt_1_0_6; +assign WixrXtYt_1_packed_7 = WixrXtYt_1_0_7; +assign WfxrXtYt_1_packed_7 = WfxrXtYt_1_0_7; +assign WoxrXtYt_1_packed_7 = WoxrXtYt_1_0_7; +assign WcxrXtYt_1_packed_7 = WcxrXtYt_1_0_7; +assign WixrXtYt_1_packed_8 = WixrXtYt_1_0_8; +assign WfxrXtYt_1_packed_8 = WfxrXtYt_1_0_8; +assign WoxrXtYt_1_packed_8 = WoxrXtYt_1_0_8; +assign WcxrXtYt_1_packed_8 = WcxrXtYt_1_0_8; +assign WixrXtYt_1_packed_9 = WixrXtYt_1_0_9; +assign WfxrXtYt_1_packed_9 = WfxrXtYt_1_0_9; +assign WoxrXtYt_1_packed_9 = WoxrXtYt_1_0_9; +assign WcxrXtYt_1_packed_9 = WcxrXtYt_1_0_9; +assign WixrXtYt_1_packed_10 = WixrXtYt_1_0_10; +assign WfxrXtYt_1_packed_10 = WfxrXtYt_1_0_10; +assign WoxrXtYt_1_packed_10 = WoxrXtYt_1_0_10; +assign WcxrXtYt_1_packed_10 = WcxrXtYt_1_0_10; +assign WixrXtYt_1_packed_11 = WixrXtYt_1_0_11; +assign WfxrXtYt_1_packed_11 = WfxrXtYt_1_0_11; +assign WoxrXtYt_1_packed_11 = WoxrXtYt_1_0_11; +assign WcxrXtYt_1_packed_11 = WcxrXtYt_1_0_11; +assign WixrXtYt_1_packed_12 = WixrXtYt_1_0_12; +assign WfxrXtYt_1_packed_12 = WfxrXtYt_1_0_12; +assign WoxrXtYt_1_packed_12 = WoxrXtYt_1_0_12; +assign WcxrXtYt_1_packed_12 = WcxrXtYt_1_0_12; +assign WixrXtYt_1_packed_13 = WixrXtYt_1_0_13; +assign WfxrXtYt_1_packed_13 = WfxrXtYt_1_0_13; +assign WoxrXtYt_1_packed_13 = WoxrXtYt_1_0_13; +assign WcxrXtYt_1_packed_13 = WcxrXtYt_1_0_13; +assign WixrXtYt_1_packed_14 = WixrXtYt_1_0_14; +assign WfxrXtYt_1_packed_14 = WfxrXtYt_1_0_14; +assign WoxrXtYt_1_packed_14 = WoxrXtYt_1_0_14; +assign WcxrXtYt_1_packed_14 = WcxrXtYt_1_0_14; +assign WixrXtYt_1_packed_15 = WixrXtYt_1_0_15; +assign WfxrXtYt_1_packed_15 = WfxrXtYt_1_0_15; +assign WoxrXtYt_1_packed_15 = WoxrXtYt_1_0_15; +assign WcxrXtYt_1_packed_15 = WcxrXtYt_1_0_15; +assign WixrXtYt_1_packed_16 = WixrXtYt_1_1_0; +assign WfxrXtYt_1_packed_16 = WfxrXtYt_1_1_0; +assign WoxrXtYt_1_packed_16 = WoxrXtYt_1_1_0; +assign WcxrXtYt_1_packed_16 = WcxrXtYt_1_1_0; +assign WixrXtYt_1_packed_17 = WixrXtYt_1_1_1; +assign WfxrXtYt_1_packed_17 = WfxrXtYt_1_1_1; +assign WoxrXtYt_1_packed_17 = WoxrXtYt_1_1_1; +assign WcxrXtYt_1_packed_17 = WcxrXtYt_1_1_1; +assign WixrXtYt_1_packed_18 = WixrXtYt_1_1_2; +assign WfxrXtYt_1_packed_18 = WfxrXtYt_1_1_2; +assign WoxrXtYt_1_packed_18 = WoxrXtYt_1_1_2; +assign WcxrXtYt_1_packed_18 = WcxrXtYt_1_1_2; +assign WixrXtYt_1_packed_19 = WixrXtYt_1_1_3; +assign WfxrXtYt_1_packed_19 = WfxrXtYt_1_1_3; +assign WoxrXtYt_1_packed_19 = WoxrXtYt_1_1_3; +assign WcxrXtYt_1_packed_19 = WcxrXtYt_1_1_3; +assign WixrXtYt_1_packed_20 = WixrXtYt_1_1_4; +assign WfxrXtYt_1_packed_20 = WfxrXtYt_1_1_4; +assign WoxrXtYt_1_packed_20 = WoxrXtYt_1_1_4; +assign WcxrXtYt_1_packed_20 = WcxrXtYt_1_1_4; +assign WixrXtYt_1_packed_21 = WixrXtYt_1_1_5; +assign WfxrXtYt_1_packed_21 = WfxrXtYt_1_1_5; +assign WoxrXtYt_1_packed_21 = WoxrXtYt_1_1_5; +assign WcxrXtYt_1_packed_21 = WcxrXtYt_1_1_5; +assign WixrXtYt_1_packed_22 = WixrXtYt_1_1_6; +assign WfxrXtYt_1_packed_22 = WfxrXtYt_1_1_6; +assign WoxrXtYt_1_packed_22 = WoxrXtYt_1_1_6; +assign WcxrXtYt_1_packed_22 = WcxrXtYt_1_1_6; +assign WixrXtYt_1_packed_23 = WixrXtYt_1_1_7; +assign WfxrXtYt_1_packed_23 = WfxrXtYt_1_1_7; +assign WoxrXtYt_1_packed_23 = WoxrXtYt_1_1_7; +assign WcxrXtYt_1_packed_23 = WcxrXtYt_1_1_7; +assign WixrXtYt_1_packed_24 = WixrXtYt_1_1_8; +assign WfxrXtYt_1_packed_24 = WfxrXtYt_1_1_8; +assign WoxrXtYt_1_packed_24 = WoxrXtYt_1_1_8; +assign WcxrXtYt_1_packed_24 = WcxrXtYt_1_1_8; +assign WixrXtYt_1_packed_25 = WixrXtYt_1_1_9; +assign WfxrXtYt_1_packed_25 = WfxrXtYt_1_1_9; +assign WoxrXtYt_1_packed_25 = WoxrXtYt_1_1_9; +assign WcxrXtYt_1_packed_25 = WcxrXtYt_1_1_9; +assign WixrXtYt_1_packed_26 = WixrXtYt_1_1_10; +assign WfxrXtYt_1_packed_26 = WfxrXtYt_1_1_10; +assign WoxrXtYt_1_packed_26 = WoxrXtYt_1_1_10; +assign WcxrXtYt_1_packed_26 = WcxrXtYt_1_1_10; +assign WixrXtYt_1_packed_27 = WixrXtYt_1_1_11; +assign WfxrXtYt_1_packed_27 = WfxrXtYt_1_1_11; +assign WoxrXtYt_1_packed_27 = WoxrXtYt_1_1_11; +assign WcxrXtYt_1_packed_27 = WcxrXtYt_1_1_11; +assign WixrXtYt_1_packed_28 = WixrXtYt_1_1_12; +assign WfxrXtYt_1_packed_28 = WfxrXtYt_1_1_12; +assign WoxrXtYt_1_packed_28 = WoxrXtYt_1_1_12; +assign WcxrXtYt_1_packed_28 = WcxrXtYt_1_1_12; +assign WixrXtYt_1_packed_29 = WixrXtYt_1_1_13; +assign WfxrXtYt_1_packed_29 = WfxrXtYt_1_1_13; +assign WoxrXtYt_1_packed_29 = WoxrXtYt_1_1_13; +assign WcxrXtYt_1_packed_29 = WcxrXtYt_1_1_13; +assign WixrXtYt_1_packed_30 = WixrXtYt_1_1_14; +assign WfxrXtYt_1_packed_30 = WfxrXtYt_1_1_14; +assign WoxrXtYt_1_packed_30 = WoxrXtYt_1_1_14; +assign WcxrXtYt_1_packed_30 = WcxrXtYt_1_1_14; +assign WixrXtYt_1_packed_31 = WixrXtYt_1_1_15; +assign WfxrXtYt_1_packed_31 = WfxrXtYt_1_1_15; +assign WoxrXtYt_1_packed_31 = WoxrXtYt_1_1_15; +assign WcxrXtYt_1_packed_31 = WcxrXtYt_1_1_15; + +shift_register_group_18_32_3 shift_register_group_18_32_3_inst_Wi ( + .clk(clk), + .enable(enable), + .in_0(WixrXtYt_1_packed_0), + .out_0(WixrXtYt_1_hold_0), + .in_1(WixrXtYt_1_packed_1), + .out_1(WixrXtYt_1_hold_1), + .in_2(WixrXtYt_1_packed_2), + .out_2(WixrXtYt_1_hold_2), + .in_3(WixrXtYt_1_packed_3), + .out_3(WixrXtYt_1_hold_3), + .in_4(WixrXtYt_1_packed_4), + .out_4(WixrXtYt_1_hold_4), + .in_5(WixrXtYt_1_packed_5), + .out_5(WixrXtYt_1_hold_5), + .in_6(WixrXtYt_1_packed_6), + .out_6(WixrXtYt_1_hold_6), + .in_7(WixrXtYt_1_packed_7), + .out_7(WixrXtYt_1_hold_7), + .in_8(WixrXtYt_1_packed_8), + .out_8(WixrXtYt_1_hold_8), + .in_9(WixrXtYt_1_packed_9), + .out_9(WixrXtYt_1_hold_9), + .in_10(WixrXtYt_1_packed_10), + .out_10(WixrXtYt_1_hold_10), + .in_11(WixrXtYt_1_packed_11), + .out_11(WixrXtYt_1_hold_11), + .in_12(WixrXtYt_1_packed_12), + .out_12(WixrXtYt_1_hold_12), + .in_13(WixrXtYt_1_packed_13), + .out_13(WixrXtYt_1_hold_13), + .in_14(WixrXtYt_1_packed_14), + .out_14(WixrXtYt_1_hold_14), + .in_15(WixrXtYt_1_packed_15), + .out_15(WixrXtYt_1_hold_15), + .in_16(WixrXtYt_1_packed_16), + .out_16(WixrXtYt_1_hold_16), + .in_17(WixrXtYt_1_packed_17), + .out_17(WixrXtYt_1_hold_17), + .in_18(WixrXtYt_1_packed_18), + .out_18(WixrXtYt_1_hold_18), + .in_19(WixrXtYt_1_packed_19), + .out_19(WixrXtYt_1_hold_19), + .in_20(WixrXtYt_1_packed_20), + .out_20(WixrXtYt_1_hold_20), + .in_21(WixrXtYt_1_packed_21), + .out_21(WixrXtYt_1_hold_21), + .in_22(WixrXtYt_1_packed_22), + .out_22(WixrXtYt_1_hold_22), + .in_23(WixrXtYt_1_packed_23), + .out_23(WixrXtYt_1_hold_23), + .in_24(WixrXtYt_1_packed_24), + .out_24(WixrXtYt_1_hold_24), + .in_25(WixrXtYt_1_packed_25), + .out_25(WixrXtYt_1_hold_25), + .in_26(WixrXtYt_1_packed_26), + .out_26(WixrXtYt_1_hold_26), + .in_27(WixrXtYt_1_packed_27), + .out_27(WixrXtYt_1_hold_27), + .in_28(WixrXtYt_1_packed_28), + .out_28(WixrXtYt_1_hold_28), + .in_29(WixrXtYt_1_packed_29), + .out_29(WixrXtYt_1_hold_29), + .in_30(WixrXtYt_1_packed_30), + .out_30(WixrXtYt_1_hold_30), + .in_31(WixrXtYt_1_packed_31), + .out_31(WixrXtYt_1_hold_31), + .reset(reset) +); + +shift_register_group_18_32_3 shift_register_group_18_32_3_inst_Wf ( + .clk(clk), + .enable(enable), + .in_0(WfxrXtYt_1_packed_0), + .out_0(WfxrXtYt_1_hold_0), + .in_1(WfxrXtYt_1_packed_1), + .out_1(WfxrXtYt_1_hold_1), + .in_2(WfxrXtYt_1_packed_2), + .out_2(WfxrXtYt_1_hold_2), + .in_3(WfxrXtYt_1_packed_3), + .out_3(WfxrXtYt_1_hold_3), + .in_4(WfxrXtYt_1_packed_4), + .out_4(WfxrXtYt_1_hold_4), + .in_5(WfxrXtYt_1_packed_5), + .out_5(WfxrXtYt_1_hold_5), + .in_6(WfxrXtYt_1_packed_6), + .out_6(WfxrXtYt_1_hold_6), + .in_7(WfxrXtYt_1_packed_7), + .out_7(WfxrXtYt_1_hold_7), + .in_8(WfxrXtYt_1_packed_8), + .out_8(WfxrXtYt_1_hold_8), + .in_9(WfxrXtYt_1_packed_9), + .out_9(WfxrXtYt_1_hold_9), + .in_10(WfxrXtYt_1_packed_10), + .out_10(WfxrXtYt_1_hold_10), + .in_11(WfxrXtYt_1_packed_11), + .out_11(WfxrXtYt_1_hold_11), + .in_12(WfxrXtYt_1_packed_12), + .out_12(WfxrXtYt_1_hold_12), + .in_13(WfxrXtYt_1_packed_13), + .out_13(WfxrXtYt_1_hold_13), + .in_14(WfxrXtYt_1_packed_14), + .out_14(WfxrXtYt_1_hold_14), + .in_15(WfxrXtYt_1_packed_15), + .out_15(WfxrXtYt_1_hold_15), + .in_16(WfxrXtYt_1_packed_16), + .out_16(WfxrXtYt_1_hold_16), + .in_17(WfxrXtYt_1_packed_17), + .out_17(WfxrXtYt_1_hold_17), + .in_18(WfxrXtYt_1_packed_18), + .out_18(WfxrXtYt_1_hold_18), + .in_19(WfxrXtYt_1_packed_19), + .out_19(WfxrXtYt_1_hold_19), + .in_20(WfxrXtYt_1_packed_20), + .out_20(WfxrXtYt_1_hold_20), + .in_21(WfxrXtYt_1_packed_21), + .out_21(WfxrXtYt_1_hold_21), + .in_22(WfxrXtYt_1_packed_22), + .out_22(WfxrXtYt_1_hold_22), + .in_23(WfxrXtYt_1_packed_23), + .out_23(WfxrXtYt_1_hold_23), + .in_24(WfxrXtYt_1_packed_24), + .out_24(WfxrXtYt_1_hold_24), + .in_25(WfxrXtYt_1_packed_25), + .out_25(WfxrXtYt_1_hold_25), + .in_26(WfxrXtYt_1_packed_26), + .out_26(WfxrXtYt_1_hold_26), + .in_27(WfxrXtYt_1_packed_27), + .out_27(WfxrXtYt_1_hold_27), + .in_28(WfxrXtYt_1_packed_28), + .out_28(WfxrXtYt_1_hold_28), + .in_29(WfxrXtYt_1_packed_29), + .out_29(WfxrXtYt_1_hold_29), + .in_30(WfxrXtYt_1_packed_30), + .out_30(WfxrXtYt_1_hold_30), + .in_31(WfxrXtYt_1_packed_31), + .out_31(WfxrXtYt_1_hold_31), + .reset(reset) +); + +shift_register_group_18_32_3 shift_register_group_18_32_3_inst_Wo ( + .clk(clk), + .enable(enable), + .in_0(WoxrXtYt_1_packed_0), + .out_0(WoxrXtYt_1_hold_0), + .in_1(WoxrXtYt_1_packed_1), + .out_1(WoxrXtYt_1_hold_1), + .in_2(WoxrXtYt_1_packed_2), + .out_2(WoxrXtYt_1_hold_2), + .in_3(WoxrXtYt_1_packed_3), + .out_3(WoxrXtYt_1_hold_3), + .in_4(WoxrXtYt_1_packed_4), + .out_4(WoxrXtYt_1_hold_4), + .in_5(WoxrXtYt_1_packed_5), + .out_5(WoxrXtYt_1_hold_5), + .in_6(WoxrXtYt_1_packed_6), + .out_6(WoxrXtYt_1_hold_6), + .in_7(WoxrXtYt_1_packed_7), + .out_7(WoxrXtYt_1_hold_7), + .in_8(WoxrXtYt_1_packed_8), + .out_8(WoxrXtYt_1_hold_8), + .in_9(WoxrXtYt_1_packed_9), + .out_9(WoxrXtYt_1_hold_9), + .in_10(WoxrXtYt_1_packed_10), + .out_10(WoxrXtYt_1_hold_10), + .in_11(WoxrXtYt_1_packed_11), + .out_11(WoxrXtYt_1_hold_11), + .in_12(WoxrXtYt_1_packed_12), + .out_12(WoxrXtYt_1_hold_12), + .in_13(WoxrXtYt_1_packed_13), + .out_13(WoxrXtYt_1_hold_13), + .in_14(WoxrXtYt_1_packed_14), + .out_14(WoxrXtYt_1_hold_14), + .in_15(WoxrXtYt_1_packed_15), + .out_15(WoxrXtYt_1_hold_15), + .in_16(WoxrXtYt_1_packed_16), + .out_16(WoxrXtYt_1_hold_16), + .in_17(WoxrXtYt_1_packed_17), + .out_17(WoxrXtYt_1_hold_17), + .in_18(WoxrXtYt_1_packed_18), + .out_18(WoxrXtYt_1_hold_18), + .in_19(WoxrXtYt_1_packed_19), + .out_19(WoxrXtYt_1_hold_19), + .in_20(WoxrXtYt_1_packed_20), + .out_20(WoxrXtYt_1_hold_20), + .in_21(WoxrXtYt_1_packed_21), + .out_21(WoxrXtYt_1_hold_21), + .in_22(WoxrXtYt_1_packed_22), + .out_22(WoxrXtYt_1_hold_22), + .in_23(WoxrXtYt_1_packed_23), + .out_23(WoxrXtYt_1_hold_23), + .in_24(WoxrXtYt_1_packed_24), + .out_24(WoxrXtYt_1_hold_24), + .in_25(WoxrXtYt_1_packed_25), + .out_25(WoxrXtYt_1_hold_25), + .in_26(WoxrXtYt_1_packed_26), + .out_26(WoxrXtYt_1_hold_26), + .in_27(WoxrXtYt_1_packed_27), + .out_27(WoxrXtYt_1_hold_27), + .in_28(WoxrXtYt_1_packed_28), + .out_28(WoxrXtYt_1_hold_28), + .in_29(WoxrXtYt_1_packed_29), + .out_29(WoxrXtYt_1_hold_29), + .in_30(WoxrXtYt_1_packed_30), + .out_30(WoxrXtYt_1_hold_30), + .in_31(WoxrXtYt_1_packed_31), + .out_31(WoxrXtYt_1_hold_31), + .reset(reset) +); + +shift_register_group_18_32_3 shift_register_group_18_32_3_inst_Wc ( + .clk(clk), + .enable(enable), + .in_0(WcxrXtYt_1_packed_0), + .out_0(WcxrXtYt_1_hold_0), + .in_1(WcxrXtYt_1_packed_1), + .out_1(WcxrXtYt_1_hold_1), + .in_2(WcxrXtYt_1_packed_2), + .out_2(WcxrXtYt_1_hold_2), + .in_3(WcxrXtYt_1_packed_3), + .out_3(WcxrXtYt_1_hold_3), + .in_4(WcxrXtYt_1_packed_4), + .out_4(WcxrXtYt_1_hold_4), + .in_5(WcxrXtYt_1_packed_5), + .out_5(WcxrXtYt_1_hold_5), + .in_6(WcxrXtYt_1_packed_6), + .out_6(WcxrXtYt_1_hold_6), + .in_7(WcxrXtYt_1_packed_7), + .out_7(WcxrXtYt_1_hold_7), + .in_8(WcxrXtYt_1_packed_8), + .out_8(WcxrXtYt_1_hold_8), + .in_9(WcxrXtYt_1_packed_9), + .out_9(WcxrXtYt_1_hold_9), + .in_10(WcxrXtYt_1_packed_10), + .out_10(WcxrXtYt_1_hold_10), + .in_11(WcxrXtYt_1_packed_11), + .out_11(WcxrXtYt_1_hold_11), + .in_12(WcxrXtYt_1_packed_12), + .out_12(WcxrXtYt_1_hold_12), + .in_13(WcxrXtYt_1_packed_13), + .out_13(WcxrXtYt_1_hold_13), + .in_14(WcxrXtYt_1_packed_14), + .out_14(WcxrXtYt_1_hold_14), + .in_15(WcxrXtYt_1_packed_15), + .out_15(WcxrXtYt_1_hold_15), + .in_16(WcxrXtYt_1_packed_16), + .out_16(WcxrXtYt_1_hold_16), + .in_17(WcxrXtYt_1_packed_17), + .out_17(WcxrXtYt_1_hold_17), + .in_18(WcxrXtYt_1_packed_18), + .out_18(WcxrXtYt_1_hold_18), + .in_19(WcxrXtYt_1_packed_19), + .out_19(WcxrXtYt_1_hold_19), + .in_20(WcxrXtYt_1_packed_20), + .out_20(WcxrXtYt_1_hold_20), + .in_21(WcxrXtYt_1_packed_21), + .out_21(WcxrXtYt_1_hold_21), + .in_22(WcxrXtYt_1_packed_22), + .out_22(WcxrXtYt_1_hold_22), + .in_23(WcxrXtYt_1_packed_23), + .out_23(WcxrXtYt_1_hold_23), + .in_24(WcxrXtYt_1_packed_24), + .out_24(WcxrXtYt_1_hold_24), + .in_25(WcxrXtYt_1_packed_25), + .out_25(WcxrXtYt_1_hold_25), + .in_26(WcxrXtYt_1_packed_26), + .out_26(WcxrXtYt_1_hold_26), + .in_27(WcxrXtYt_1_packed_27), + .out_27(WcxrXtYt_1_hold_27), + .in_28(WcxrXtYt_1_packed_28), + .out_28(WcxrXtYt_1_hold_28), + .in_29(WcxrXtYt_1_packed_29), + .out_29(WcxrXtYt_1_hold_29), + .in_30(WcxrXtYt_1_packed_30), + .out_30(WcxrXtYt_1_hold_30), + .in_31(WcxrXtYt_1_packed_31), + .out_31(WcxrXtYt_1_hold_31), + .reset(reset) +); + +shift_register_unit_1_3 shift_register_unit_1_3_inst_s2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(stage1_valid), + .out(stage1_valid_hold) +); + +C_LSTM_stage_2_18_10_32_1 C_LSTM_stage_2_18_10_32_1_inst_feuaolvlol ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(stage1_valid_hold), + .Ct_1_0(Ctt_1_0), + .WixrXtYt_1_0(WixrXtYt_1_hold_0), + .Wic_0(Wic_0), + .bi_0(bi_0), + .WfxrXtYt_1_0(WfxrXtYt_1_hold_0), + .Wfc_0(Wfc_0), + .bf_0(bf_0), + .WoxrXtYt_1_0(WoxrXtYt_1_hold_0), + .Woc_0(Woc_0), + .bo_0(bo_0), + .WcxrXtYt_1_0(WcxrXtYt_1_hold_0), + .bc_0(bc_0), + .out_mt_0(stage2_mt_0), + .out_ct_0(stage2_Ct_0), + .Ct_1_1(Ctt_1_1), + .WixrXtYt_1_1(WixrXtYt_1_hold_1), + .Wic_1(Wic_1), + .bi_1(bi_1), + .WfxrXtYt_1_1(WfxrXtYt_1_hold_1), + .Wfc_1(Wfc_1), + .bf_1(bf_1), + .WoxrXtYt_1_1(WoxrXtYt_1_hold_1), + .Woc_1(Woc_1), + .bo_1(bo_1), + .WcxrXtYt_1_1(WcxrXtYt_1_hold_1), + .bc_1(bc_1), + .out_mt_1(stage2_mt_1), + .out_ct_1(stage2_Ct_1), + .Ct_1_2(Ctt_1_2), + .WixrXtYt_1_2(WixrXtYt_1_hold_2), + .Wic_2(Wic_2), + .bi_2(bi_2), + .WfxrXtYt_1_2(WfxrXtYt_1_hold_2), + .Wfc_2(Wfc_2), + .bf_2(bf_2), + .WoxrXtYt_1_2(WoxrXtYt_1_hold_2), + .Woc_2(Woc_2), + .bo_2(bo_2), + .WcxrXtYt_1_2(WcxrXtYt_1_hold_2), + .bc_2(bc_2), + .out_mt_2(stage2_mt_2), + .out_ct_2(stage2_Ct_2), + .Ct_1_3(Ctt_1_3), + .WixrXtYt_1_3(WixrXtYt_1_hold_3), + .Wic_3(Wic_3), + .bi_3(bi_3), + .WfxrXtYt_1_3(WfxrXtYt_1_hold_3), + .Wfc_3(Wfc_3), + .bf_3(bf_3), + .WoxrXtYt_1_3(WoxrXtYt_1_hold_3), + .Woc_3(Woc_3), + .bo_3(bo_3), + .WcxrXtYt_1_3(WcxrXtYt_1_hold_3), + .bc_3(bc_3), + .out_mt_3(stage2_mt_3), + .out_ct_3(stage2_Ct_3), + .Ct_1_4(Ctt_1_4), + .WixrXtYt_1_4(WixrXtYt_1_hold_4), + .Wic_4(Wic_4), + .bi_4(bi_4), + .WfxrXtYt_1_4(WfxrXtYt_1_hold_4), + .Wfc_4(Wfc_4), + .bf_4(bf_4), + .WoxrXtYt_1_4(WoxrXtYt_1_hold_4), + .Woc_4(Woc_4), + .bo_4(bo_4), + .WcxrXtYt_1_4(WcxrXtYt_1_hold_4), + .bc_4(bc_4), + .out_mt_4(stage2_mt_4), + .out_ct_4(stage2_Ct_4), + .Ct_1_5(Ctt_1_5), + .WixrXtYt_1_5(WixrXtYt_1_hold_5), + .Wic_5(Wic_5), + .bi_5(bi_5), + .WfxrXtYt_1_5(WfxrXtYt_1_hold_5), + .Wfc_5(Wfc_5), + .bf_5(bf_5), + .WoxrXtYt_1_5(WoxrXtYt_1_hold_5), + .Woc_5(Woc_5), + .bo_5(bo_5), + .WcxrXtYt_1_5(WcxrXtYt_1_hold_5), + .bc_5(bc_5), + .out_mt_5(stage2_mt_5), + .out_ct_5(stage2_Ct_5), + .Ct_1_6(Ctt_1_6), + .WixrXtYt_1_6(WixrXtYt_1_hold_6), + .Wic_6(Wic_6), + .bi_6(bi_6), + .WfxrXtYt_1_6(WfxrXtYt_1_hold_6), + .Wfc_6(Wfc_6), + .bf_6(bf_6), + .WoxrXtYt_1_6(WoxrXtYt_1_hold_6), + .Woc_6(Woc_6), + .bo_6(bo_6), + .WcxrXtYt_1_6(WcxrXtYt_1_hold_6), + .bc_6(bc_6), + .out_mt_6(stage2_mt_6), + .out_ct_6(stage2_Ct_6), + .Ct_1_7(Ctt_1_7), + .WixrXtYt_1_7(WixrXtYt_1_hold_7), + .Wic_7(Wic_7), + .bi_7(bi_7), + .WfxrXtYt_1_7(WfxrXtYt_1_hold_7), + .Wfc_7(Wfc_7), + .bf_7(bf_7), + .WoxrXtYt_1_7(WoxrXtYt_1_hold_7), + .Woc_7(Woc_7), + .bo_7(bo_7), + .WcxrXtYt_1_7(WcxrXtYt_1_hold_7), + .bc_7(bc_7), + .out_mt_7(stage2_mt_7), + .out_ct_7(stage2_Ct_7), + .Ct_1_8(Ctt_1_8), + .WixrXtYt_1_8(WixrXtYt_1_hold_8), + .Wic_8(Wic_8), + .bi_8(bi_8), + .WfxrXtYt_1_8(WfxrXtYt_1_hold_8), + .Wfc_8(Wfc_8), + .bf_8(bf_8), + .WoxrXtYt_1_8(WoxrXtYt_1_hold_8), + .Woc_8(Woc_8), + .bo_8(bo_8), + .WcxrXtYt_1_8(WcxrXtYt_1_hold_8), + .bc_8(bc_8), + .out_mt_8(stage2_mt_8), + .out_ct_8(stage2_Ct_8), + .Ct_1_9(Ctt_1_9), + .WixrXtYt_1_9(WixrXtYt_1_hold_9), + .Wic_9(Wic_9), + .bi_9(bi_9), + .WfxrXtYt_1_9(WfxrXtYt_1_hold_9), + .Wfc_9(Wfc_9), + .bf_9(bf_9), + .WoxrXtYt_1_9(WoxrXtYt_1_hold_9), + .Woc_9(Woc_9), + .bo_9(bo_9), + .WcxrXtYt_1_9(WcxrXtYt_1_hold_9), + .bc_9(bc_9), + .out_mt_9(stage2_mt_9), + .out_ct_9(stage2_Ct_9), + .Ct_1_10(Ctt_1_10), + .WixrXtYt_1_10(WixrXtYt_1_hold_10), + .Wic_10(Wic_10), + .bi_10(bi_10), + .WfxrXtYt_1_10(WfxrXtYt_1_hold_10), + .Wfc_10(Wfc_10), + .bf_10(bf_10), + .WoxrXtYt_1_10(WoxrXtYt_1_hold_10), + .Woc_10(Woc_10), + .bo_10(bo_10), + .WcxrXtYt_1_10(WcxrXtYt_1_hold_10), + .bc_10(bc_10), + .out_mt_10(stage2_mt_10), + .out_ct_10(stage2_Ct_10), + .Ct_1_11(Ctt_1_11), + .WixrXtYt_1_11(WixrXtYt_1_hold_11), + .Wic_11(Wic_11), + .bi_11(bi_11), + .WfxrXtYt_1_11(WfxrXtYt_1_hold_11), + .Wfc_11(Wfc_11), + .bf_11(bf_11), + .WoxrXtYt_1_11(WoxrXtYt_1_hold_11), + .Woc_11(Woc_11), + .bo_11(bo_11), + .WcxrXtYt_1_11(WcxrXtYt_1_hold_11), + .bc_11(bc_11), + .out_mt_11(stage2_mt_11), + .out_ct_11(stage2_Ct_11), + .Ct_1_12(Ctt_1_12), + .WixrXtYt_1_12(WixrXtYt_1_hold_12), + .Wic_12(Wic_12), + .bi_12(bi_12), + .WfxrXtYt_1_12(WfxrXtYt_1_hold_12), + .Wfc_12(Wfc_12), + .bf_12(bf_12), + .WoxrXtYt_1_12(WoxrXtYt_1_hold_12), + .Woc_12(Woc_12), + .bo_12(bo_12), + .WcxrXtYt_1_12(WcxrXtYt_1_hold_12), + .bc_12(bc_12), + .out_mt_12(stage2_mt_12), + .out_ct_12(stage2_Ct_12), + .Ct_1_13(Ctt_1_13), + .WixrXtYt_1_13(WixrXtYt_1_hold_13), + .Wic_13(Wic_13), + .bi_13(bi_13), + .WfxrXtYt_1_13(WfxrXtYt_1_hold_13), + .Wfc_13(Wfc_13), + .bf_13(bf_13), + .WoxrXtYt_1_13(WoxrXtYt_1_hold_13), + .Woc_13(Woc_13), + .bo_13(bo_13), + .WcxrXtYt_1_13(WcxrXtYt_1_hold_13), + .bc_13(bc_13), + .out_mt_13(stage2_mt_13), + .out_ct_13(stage2_Ct_13), + .Ct_1_14(Ctt_1_14), + .WixrXtYt_1_14(WixrXtYt_1_hold_14), + .Wic_14(Wic_14), + .bi_14(bi_14), + .WfxrXtYt_1_14(WfxrXtYt_1_hold_14), + .Wfc_14(Wfc_14), + .bf_14(bf_14), + .WoxrXtYt_1_14(WoxrXtYt_1_hold_14), + .Woc_14(Woc_14), + .bo_14(bo_14), + .WcxrXtYt_1_14(WcxrXtYt_1_hold_14), + .bc_14(bc_14), + .out_mt_14(stage2_mt_14), + .out_ct_14(stage2_Ct_14), + .Ct_1_15(Ctt_1_15), + .WixrXtYt_1_15(WixrXtYt_1_hold_15), + .Wic_15(Wic_15), + .bi_15(bi_15), + .WfxrXtYt_1_15(WfxrXtYt_1_hold_15), + .Wfc_15(Wfc_15), + .bf_15(bf_15), + .WoxrXtYt_1_15(WoxrXtYt_1_hold_15), + .Woc_15(Woc_15), + .bo_15(bo_15), + .WcxrXtYt_1_15(WcxrXtYt_1_hold_15), + .bc_15(bc_15), + .out_mt_15(stage2_mt_15), + .out_ct_15(stage2_Ct_15), + .Ct_1_16(Ctt_1_16), + .WixrXtYt_1_16(WixrXtYt_1_hold_16), + .Wic_16(Wic_16), + .bi_16(bi_16), + .WfxrXtYt_1_16(WfxrXtYt_1_hold_16), + .Wfc_16(Wfc_16), + .bf_16(bf_16), + .WoxrXtYt_1_16(WoxrXtYt_1_hold_16), + .Woc_16(Woc_16), + .bo_16(bo_16), + .WcxrXtYt_1_16(WcxrXtYt_1_hold_16), + .bc_16(bc_16), + .out_mt_16(stage2_mt_16), + .out_ct_16(stage2_Ct_16), + .Ct_1_17(Ctt_1_17), + .WixrXtYt_1_17(WixrXtYt_1_hold_17), + .Wic_17(Wic_17), + .bi_17(bi_17), + .WfxrXtYt_1_17(WfxrXtYt_1_hold_17), + .Wfc_17(Wfc_17), + .bf_17(bf_17), + .WoxrXtYt_1_17(WoxrXtYt_1_hold_17), + .Woc_17(Woc_17), + .bo_17(bo_17), + .WcxrXtYt_1_17(WcxrXtYt_1_hold_17), + .bc_17(bc_17), + .out_mt_17(stage2_mt_17), + .out_ct_17(stage2_Ct_17), + .Ct_1_18(Ctt_1_18), + .WixrXtYt_1_18(WixrXtYt_1_hold_18), + .Wic_18(Wic_18), + .bi_18(bi_18), + .WfxrXtYt_1_18(WfxrXtYt_1_hold_18), + .Wfc_18(Wfc_18), + .bf_18(bf_18), + .WoxrXtYt_1_18(WoxrXtYt_1_hold_18), + .Woc_18(Woc_18), + .bo_18(bo_18), + .WcxrXtYt_1_18(WcxrXtYt_1_hold_18), + .bc_18(bc_18), + .out_mt_18(stage2_mt_18), + .out_ct_18(stage2_Ct_18), + .Ct_1_19(Ctt_1_19), + .WixrXtYt_1_19(WixrXtYt_1_hold_19), + .Wic_19(Wic_19), + .bi_19(bi_19), + .WfxrXtYt_1_19(WfxrXtYt_1_hold_19), + .Wfc_19(Wfc_19), + .bf_19(bf_19), + .WoxrXtYt_1_19(WoxrXtYt_1_hold_19), + .Woc_19(Woc_19), + .bo_19(bo_19), + .WcxrXtYt_1_19(WcxrXtYt_1_hold_19), + .bc_19(bc_19), + .out_mt_19(stage2_mt_19), + .out_ct_19(stage2_Ct_19), + .Ct_1_20(Ctt_1_20), + .WixrXtYt_1_20(WixrXtYt_1_hold_20), + .Wic_20(Wic_20), + .bi_20(bi_20), + .WfxrXtYt_1_20(WfxrXtYt_1_hold_20), + .Wfc_20(Wfc_20), + .bf_20(bf_20), + .WoxrXtYt_1_20(WoxrXtYt_1_hold_20), + .Woc_20(Woc_20), + .bo_20(bo_20), + .WcxrXtYt_1_20(WcxrXtYt_1_hold_20), + .bc_20(bc_20), + .out_mt_20(stage2_mt_20), + .out_ct_20(stage2_Ct_20), + .Ct_1_21(Ctt_1_21), + .WixrXtYt_1_21(WixrXtYt_1_hold_21), + .Wic_21(Wic_21), + .bi_21(bi_21), + .WfxrXtYt_1_21(WfxrXtYt_1_hold_21), + .Wfc_21(Wfc_21), + .bf_21(bf_21), + .WoxrXtYt_1_21(WoxrXtYt_1_hold_21), + .Woc_21(Woc_21), + .bo_21(bo_21), + .WcxrXtYt_1_21(WcxrXtYt_1_hold_21), + .bc_21(bc_21), + .out_mt_21(stage2_mt_21), + .out_ct_21(stage2_Ct_21), + .Ct_1_22(Ctt_1_22), + .WixrXtYt_1_22(WixrXtYt_1_hold_22), + .Wic_22(Wic_22), + .bi_22(bi_22), + .WfxrXtYt_1_22(WfxrXtYt_1_hold_22), + .Wfc_22(Wfc_22), + .bf_22(bf_22), + .WoxrXtYt_1_22(WoxrXtYt_1_hold_22), + .Woc_22(Woc_22), + .bo_22(bo_22), + .WcxrXtYt_1_22(WcxrXtYt_1_hold_22), + .bc_22(bc_22), + .out_mt_22(stage2_mt_22), + .out_ct_22(stage2_Ct_22), + .Ct_1_23(Ctt_1_23), + .WixrXtYt_1_23(WixrXtYt_1_hold_23), + .Wic_23(Wic_23), + .bi_23(bi_23), + .WfxrXtYt_1_23(WfxrXtYt_1_hold_23), + .Wfc_23(Wfc_23), + .bf_23(bf_23), + .WoxrXtYt_1_23(WoxrXtYt_1_hold_23), + .Woc_23(Woc_23), + .bo_23(bo_23), + .WcxrXtYt_1_23(WcxrXtYt_1_hold_23), + .bc_23(bc_23), + .out_mt_23(stage2_mt_23), + .out_ct_23(stage2_Ct_23), + .Ct_1_24(Ctt_1_24), + .WixrXtYt_1_24(WixrXtYt_1_hold_24), + .Wic_24(Wic_24), + .bi_24(bi_24), + .WfxrXtYt_1_24(WfxrXtYt_1_hold_24), + .Wfc_24(Wfc_24), + .bf_24(bf_24), + .WoxrXtYt_1_24(WoxrXtYt_1_hold_24), + .Woc_24(Woc_24), + .bo_24(bo_24), + .WcxrXtYt_1_24(WcxrXtYt_1_hold_24), + .bc_24(bc_24), + .out_mt_24(stage2_mt_24), + .out_ct_24(stage2_Ct_24), + .Ct_1_25(Ctt_1_25), + .WixrXtYt_1_25(WixrXtYt_1_hold_25), + .Wic_25(Wic_25), + .bi_25(bi_25), + .WfxrXtYt_1_25(WfxrXtYt_1_hold_25), + .Wfc_25(Wfc_25), + .bf_25(bf_25), + .WoxrXtYt_1_25(WoxrXtYt_1_hold_25), + .Woc_25(Woc_25), + .bo_25(bo_25), + .WcxrXtYt_1_25(WcxrXtYt_1_hold_25), + .bc_25(bc_25), + .out_mt_25(stage2_mt_25), + .out_ct_25(stage2_Ct_25), + .Ct_1_26(Ctt_1_26), + .WixrXtYt_1_26(WixrXtYt_1_hold_26), + .Wic_26(Wic_26), + .bi_26(bi_26), + .WfxrXtYt_1_26(WfxrXtYt_1_hold_26), + .Wfc_26(Wfc_26), + .bf_26(bf_26), + .WoxrXtYt_1_26(WoxrXtYt_1_hold_26), + .Woc_26(Woc_26), + .bo_26(bo_26), + .WcxrXtYt_1_26(WcxrXtYt_1_hold_26), + .bc_26(bc_26), + .out_mt_26(stage2_mt_26), + .out_ct_26(stage2_Ct_26), + .Ct_1_27(Ctt_1_27), + .WixrXtYt_1_27(WixrXtYt_1_hold_27), + .Wic_27(Wic_27), + .bi_27(bi_27), + .WfxrXtYt_1_27(WfxrXtYt_1_hold_27), + .Wfc_27(Wfc_27), + .bf_27(bf_27), + .WoxrXtYt_1_27(WoxrXtYt_1_hold_27), + .Woc_27(Woc_27), + .bo_27(bo_27), + .WcxrXtYt_1_27(WcxrXtYt_1_hold_27), + .bc_27(bc_27), + .out_mt_27(stage2_mt_27), + .out_ct_27(stage2_Ct_27), + .Ct_1_28(Ctt_1_28), + .WixrXtYt_1_28(WixrXtYt_1_hold_28), + .Wic_28(Wic_28), + .bi_28(bi_28), + .WfxrXtYt_1_28(WfxrXtYt_1_hold_28), + .Wfc_28(Wfc_28), + .bf_28(bf_28), + .WoxrXtYt_1_28(WoxrXtYt_1_hold_28), + .Woc_28(Woc_28), + .bo_28(bo_28), + .WcxrXtYt_1_28(WcxrXtYt_1_hold_28), + .bc_28(bc_28), + .out_mt_28(stage2_mt_28), + .out_ct_28(stage2_Ct_28), + .Ct_1_29(Ctt_1_29), + .WixrXtYt_1_29(WixrXtYt_1_hold_29), + .Wic_29(Wic_29), + .bi_29(bi_29), + .WfxrXtYt_1_29(WfxrXtYt_1_hold_29), + .Wfc_29(Wfc_29), + .bf_29(bf_29), + .WoxrXtYt_1_29(WoxrXtYt_1_hold_29), + .Woc_29(Woc_29), + .bo_29(bo_29), + .WcxrXtYt_1_29(WcxrXtYt_1_hold_29), + .bc_29(bc_29), + .out_mt_29(stage2_mt_29), + .out_ct_29(stage2_Ct_29), + .Ct_1_30(Ctt_1_30), + .WixrXtYt_1_30(WixrXtYt_1_hold_30), + .Wic_30(Wic_30), + .bi_30(bi_30), + .WfxrXtYt_1_30(WfxrXtYt_1_hold_30), + .Wfc_30(Wfc_30), + .bf_30(bf_30), + .WoxrXtYt_1_30(WoxrXtYt_1_hold_30), + .Woc_30(Woc_30), + .bo_30(bo_30), + .WcxrXtYt_1_30(WcxrXtYt_1_hold_30), + .bc_30(bc_30), + .out_mt_30(stage2_mt_30), + .out_ct_30(stage2_Ct_30), + .Ct_1_31(Ctt_1_31), + .WixrXtYt_1_31(WixrXtYt_1_hold_31), + .Wic_31(Wic_31), + .bi_31(bi_31), + .WfxrXtYt_1_31(WfxrXtYt_1_hold_31), + .Wfc_31(Wfc_31), + .bf_31(bf_31), + .WoxrXtYt_1_31(WoxrXtYt_1_hold_31), + .Woc_31(Woc_31), + .bo_31(bo_31), + .WcxrXtYt_1_31(WcxrXtYt_1_hold_31), + .bc_31(bc_31), + .out_mt_31(stage2_mt_31), + .out_ct_31(stage2_Ct_31), + .o_valid(stage2_valid), + .o_ready(stage2_ready) +); + +wire [17:0] mt_0_0; +wire [17:0] Ct_0_0; +wire [17:0] mt_0_1; +wire [17:0] Ct_0_1; +wire [17:0] mt_0_2; +wire [17:0] Ct_0_2; +wire [17:0] mt_0_3; +wire [17:0] Ct_0_3; +wire [17:0] mt_0_4; +wire [17:0] Ct_0_4; +wire [17:0] mt_0_5; +wire [17:0] Ct_0_5; +wire [17:0] mt_0_6; +wire [17:0] Ct_0_6; +wire [17:0] mt_0_7; +wire [17:0] Ct_0_7; +wire [17:0] mt_0_8; +wire [17:0] Ct_0_8; +wire [17:0] mt_0_9; +wire [17:0] Ct_0_9; +wire [17:0] mt_0_10; +wire [17:0] Ct_0_10; +wire [17:0] mt_0_11; +wire [17:0] Ct_0_11; +wire [17:0] mt_0_12; +wire [17:0] Ct_0_12; +wire [17:0] mt_0_13; +wire [17:0] Ct_0_13; +wire [17:0] mt_0_14; +wire [17:0] Ct_0_14; +wire [17:0] mt_0_15; +wire [17:0] Ct_0_15; +wire [17:0] mt_1_0; +wire [17:0] Ct_1_0; +wire [17:0] mt_1_1; +wire [17:0] Ct_1_1; +wire [17:0] mt_1_2; +wire [17:0] Ct_1_2; +wire [17:0] mt_1_3; +wire [17:0] Ct_1_3; +wire [17:0] mt_1_4; +wire [17:0] Ct_1_4; +wire [17:0] mt_1_5; +wire [17:0] Ct_1_5; +wire [17:0] mt_1_6; +wire [17:0] Ct_1_6; +wire [17:0] mt_1_7; +wire [17:0] Ct_1_7; +wire [17:0] mt_1_8; +wire [17:0] Ct_1_8; +wire [17:0] mt_1_9; +wire [17:0] Ct_1_9; +wire [17:0] mt_1_10; +wire [17:0] Ct_1_10; +wire [17:0] mt_1_11; +wire [17:0] Ct_1_11; +wire [17:0] mt_1_12; +wire [17:0] Ct_1_12; +wire [17:0] mt_1_13; +wire [17:0] Ct_1_13; +wire [17:0] mt_1_14; +wire [17:0] Ct_1_14; +wire [17:0] mt_1_15; +wire [17:0] Ct_1_15; + +assign Ct_0_0 = stage2_Ct_0; +assign mt_0_0 = stage2_mt_0; +assign Ct_0_1 = stage2_Ct_1; +assign mt_0_1 = stage2_mt_1; +assign Ct_0_2 = stage2_Ct_2; +assign mt_0_2 = stage2_mt_2; +assign Ct_0_3 = stage2_Ct_3; +assign mt_0_3 = stage2_mt_3; +assign Ct_0_4 = stage2_Ct_4; +assign mt_0_4 = stage2_mt_4; +assign Ct_0_5 = stage2_Ct_5; +assign mt_0_5 = stage2_mt_5; +assign Ct_0_6 = stage2_Ct_6; +assign mt_0_6 = stage2_mt_6; +assign Ct_0_7 = stage2_Ct_7; +assign mt_0_7 = stage2_mt_7; +assign Ct_0_8 = stage2_Ct_8; +assign mt_0_8 = stage2_mt_8; +assign Ct_0_9 = stage2_Ct_9; +assign mt_0_9 = stage2_mt_9; +assign Ct_0_10 = stage2_Ct_10; +assign mt_0_10 = stage2_mt_10; +assign Ct_0_11 = stage2_Ct_11; +assign mt_0_11 = stage2_mt_11; +assign Ct_0_12 = stage2_Ct_12; +assign mt_0_12 = stage2_mt_12; +assign Ct_0_13 = stage2_Ct_13; +assign mt_0_13 = stage2_mt_13; +assign Ct_0_14 = stage2_Ct_14; +assign mt_0_14 = stage2_mt_14; +assign Ct_0_15 = stage2_Ct_15; +assign mt_0_15 = stage2_mt_15; +assign Ct_1_0 = stage2_Ct_16; +assign mt_1_0 = stage2_mt_16; +assign Ct_1_1 = stage2_Ct_17; +assign mt_1_1 = stage2_mt_17; +assign Ct_1_2 = stage2_Ct_18; +assign mt_1_2 = stage2_mt_18; +assign Ct_1_3 = stage2_Ct_19; +assign mt_1_3 = stage2_mt_19; +assign Ct_1_4 = stage2_Ct_20; +assign mt_1_4 = stage2_mt_20; +assign Ct_1_5 = stage2_Ct_21; +assign mt_1_5 = stage2_mt_21; +assign Ct_1_6 = stage2_Ct_22; +assign mt_1_6 = stage2_mt_22; +assign Ct_1_7 = stage2_Ct_23; +assign mt_1_7 = stage2_mt_23; +assign Ct_1_8 = stage2_Ct_24; +assign mt_1_8 = stage2_mt_24; +assign Ct_1_9 = stage2_Ct_25; +assign mt_1_9 = stage2_mt_25; +assign Ct_1_10 = stage2_Ct_26; +assign mt_1_10 = stage2_mt_26; +assign Ct_1_11 = stage2_Ct_27; +assign mt_1_11 = stage2_mt_27; +assign Ct_1_12 = stage2_Ct_28; +assign mt_1_12 = stage2_mt_28; +assign Ct_1_13 = stage2_Ct_29; +assign mt_1_13 = stage2_mt_29; +assign Ct_1_14 = stage2_Ct_30; +assign mt_1_14 = stage2_mt_30; +assign Ct_1_15 = stage2_Ct_31; +assign mt_1_15 = stage2_mt_31; + +// C-LSTM buffer between stage2 and stage3 +wire buffer_out_valid, pipelined_mt_valid, pipelined_Ct_valid; +wire [17:0] mt_pipelined_0; +wire [17:0] Ct_pipelined_0; +wire [17:0] out_mt_buffer_0; +wire [17:0] mt_pipelined_1; +wire [17:0] Ct_pipelined_1; +wire [17:0] out_mt_buffer_1; +wire [17:0] mt_pipelined_2; +wire [17:0] Ct_pipelined_2; +wire [17:0] out_mt_buffer_2; +wire [17:0] mt_pipelined_3; +wire [17:0] Ct_pipelined_3; +wire [17:0] out_mt_buffer_3; +wire [17:0] mt_pipelined_4; +wire [17:0] Ct_pipelined_4; +wire [17:0] out_mt_buffer_4; +wire [17:0] mt_pipelined_5; +wire [17:0] Ct_pipelined_5; +wire [17:0] out_mt_buffer_5; +wire [17:0] mt_pipelined_6; +wire [17:0] Ct_pipelined_6; +wire [17:0] out_mt_buffer_6; +wire [17:0] mt_pipelined_7; +wire [17:0] Ct_pipelined_7; +wire [17:0] out_mt_buffer_7; +wire [17:0] mt_pipelined_8; +wire [17:0] Ct_pipelined_8; +wire [17:0] out_mt_buffer_8; +wire [17:0] mt_pipelined_9; +wire [17:0] Ct_pipelined_9; +wire [17:0] out_mt_buffer_9; +wire [17:0] mt_pipelined_10; +wire [17:0] Ct_pipelined_10; +wire [17:0] out_mt_buffer_10; +wire [17:0] mt_pipelined_11; +wire [17:0] Ct_pipelined_11; +wire [17:0] out_mt_buffer_11; +wire [17:0] mt_pipelined_12; +wire [17:0] Ct_pipelined_12; +wire [17:0] out_mt_buffer_12; +wire [17:0] mt_pipelined_13; +wire [17:0] Ct_pipelined_13; +wire [17:0] out_mt_buffer_13; +wire [17:0] mt_pipelined_14; +wire [17:0] Ct_pipelined_14; +wire [17:0] out_mt_buffer_14; +wire [17:0] mt_pipelined_15; +wire [17:0] Ct_pipelined_15; +wire [17:0] out_mt_buffer_15; + +pipelined_input_18_2_16 pipelined_input_18_2_16_inst_mt ( + .clk(clk), + .reset(reset), + .enable(enable), + .load_input(stage2_valid), + .i_data_0_0(mt_0_0), + .i_data_0_1(mt_0_1), + .i_data_0_2(mt_0_2), + .i_data_0_3(mt_0_3), + .i_data_0_4(mt_0_4), + .i_data_0_5(mt_0_5), + .i_data_0_6(mt_0_6), + .i_data_0_7(mt_0_7), + .i_data_0_8(mt_0_8), + .i_data_0_9(mt_0_9), + .i_data_0_10(mt_0_10), + .i_data_0_11(mt_0_11), + .i_data_0_12(mt_0_12), + .i_data_0_13(mt_0_13), + .i_data_0_14(mt_0_14), + .i_data_0_15(mt_0_15), + .i_data_1_0(mt_1_0), + .i_data_1_1(mt_1_1), + .i_data_1_2(mt_1_2), + .i_data_1_3(mt_1_3), + .i_data_1_4(mt_1_4), + .i_data_1_5(mt_1_5), + .i_data_1_6(mt_1_6), + .i_data_1_7(mt_1_7), + .i_data_1_8(mt_1_8), + .i_data_1_9(mt_1_9), + .i_data_1_10(mt_1_10), + .i_data_1_11(mt_1_11), + .i_data_1_12(mt_1_12), + .i_data_1_13(mt_1_13), + .i_data_1_14(mt_1_14), + .i_data_1_15(mt_1_15), + .o_data_0(mt_pipelined_0), + .o_data_1(mt_pipelined_1), + .o_data_2(mt_pipelined_2), + .o_data_3(mt_pipelined_3), + .o_data_4(mt_pipelined_4), + .o_data_5(mt_pipelined_5), + .o_data_6(mt_pipelined_6), + .o_data_7(mt_pipelined_7), + .o_data_8(mt_pipelined_8), + .o_data_9(mt_pipelined_9), + .o_data_10(mt_pipelined_10), + .o_data_11(mt_pipelined_11), + .o_data_12(mt_pipelined_12), + .o_data_13(mt_pipelined_13), + .o_data_14(mt_pipelined_14), + .o_data_15(mt_pipelined_15), + .o_valid(pipelined_mt_valid) +); + +pipelined_input_18_2_16 pipelined_input_18_2_16_inst_Ct ( + .clk(clk), + .reset(reset), + .enable(enable), + .load_input(stage2_valid), + .i_data_0_0(Ct_0_0), + .i_data_0_1(Ct_0_1), + .i_data_0_2(Ct_0_2), + .i_data_0_3(Ct_0_3), + .i_data_0_4(Ct_0_4), + .i_data_0_5(Ct_0_5), + .i_data_0_6(Ct_0_6), + .i_data_0_7(Ct_0_7), + .i_data_0_8(Ct_0_8), + .i_data_0_9(Ct_0_9), + .i_data_0_10(Ct_0_10), + .i_data_0_11(Ct_0_11), + .i_data_0_12(Ct_0_12), + .i_data_0_13(Ct_0_13), + .i_data_0_14(Ct_0_14), + .i_data_0_15(Ct_0_15), + .i_data_1_0(Ct_1_0), + .i_data_1_1(Ct_1_1), + .i_data_1_2(Ct_1_2), + .i_data_1_3(Ct_1_3), + .i_data_1_4(Ct_1_4), + .i_data_1_5(Ct_1_5), + .i_data_1_6(Ct_1_6), + .i_data_1_7(Ct_1_7), + .i_data_1_8(Ct_1_8), + .i_data_1_9(Ct_1_9), + .i_data_1_10(Ct_1_10), + .i_data_1_11(Ct_1_11), + .i_data_1_12(Ct_1_12), + .i_data_1_13(Ct_1_13), + .i_data_1_14(Ct_1_14), + .i_data_1_15(Ct_1_15), + .o_data_0(Ct_pipelined_0), + .o_data_1(Ct_pipelined_1), + .o_data_2(Ct_pipelined_2), + .o_data_3(Ct_pipelined_3), + .o_data_4(Ct_pipelined_4), + .o_data_5(Ct_pipelined_5), + .o_data_6(Ct_pipelined_6), + .o_data_7(Ct_pipelined_7), + .o_data_8(Ct_pipelined_8), + .o_data_9(Ct_pipelined_9), + .o_data_10(Ct_pipelined_10), + .o_data_11(Ct_pipelined_11), + .o_data_12(Ct_pipelined_12), + .o_data_13(Ct_pipelined_13), + .o_data_14(Ct_pipelined_14), + .o_data_15(Ct_pipelined_15), + .o_valid(pipelined_Ct_valid) +); + +stage2_Ct_buffer_18_2_16_64 stage2_Ct_buffer_18_2_16_64_inst_cptozfmpvd ( + .clk(clk), + .reset(reset), + .wen(pipelined_Ct_valid), + .ren(stage1_valid), + .i_Ct_0(Ct_pipelined_0), + .i_Ct_1(Ct_pipelined_1), + .i_Ct_2(Ct_pipelined_2), + .i_Ct_3(Ct_pipelined_3), + .i_Ct_4(Ct_pipelined_4), + .i_Ct_5(Ct_pipelined_5), + .i_Ct_6(Ct_pipelined_6), + .i_Ct_7(Ct_pipelined_7), + .i_Ct_8(Ct_pipelined_8), + .i_Ct_9(Ct_pipelined_9), + .i_Ct_10(Ct_pipelined_10), + .i_Ct_11(Ct_pipelined_11), + .i_Ct_12(Ct_pipelined_12), + .i_Ct_13(Ct_pipelined_13), + .i_Ct_14(Ct_pipelined_14), + .i_Ct_15(Ct_pipelined_15), + .o_Ct_0(Ctt_1_0), + .o_Ct_1(Ctt_1_1), + .o_Ct_2(Ctt_1_2), + .o_Ct_3(Ctt_1_3), + .o_Ct_4(Ctt_1_4), + .o_Ct_5(Ctt_1_5), + .o_Ct_6(Ctt_1_6), + .o_Ct_7(Ctt_1_7), + .o_Ct_8(Ctt_1_8), + .o_Ct_9(Ctt_1_9), + .o_Ct_10(Ctt_1_10), + .o_Ct_11(Ctt_1_11), + .o_Ct_12(Ctt_1_12), + .o_Ct_13(Ctt_1_13), + .o_Ct_14(Ctt_1_14), + .o_Ct_15(Ctt_1_15), + .o_Ct_16(Ctt_1_16), + .o_Ct_17(Ctt_1_17), + .o_Ct_18(Ctt_1_18), + .o_Ct_19(Ctt_1_19), + .o_Ct_20(Ctt_1_20), + .o_Ct_21(Ctt_1_21), + .o_Ct_22(Ctt_1_22), + .o_Ct_23(Ctt_1_23), + .o_Ct_24(Ctt_1_24), + .o_Ct_25(Ctt_1_25), + .o_Ct_26(Ctt_1_26), + .o_Ct_27(Ctt_1_27), + .o_Ct_28(Ctt_1_28), + .o_Ct_29(Ctt_1_29), + .o_Ct_30(Ctt_1_30), + .o_Ct_31(Ctt_1_31), + .o_valid() +); + +stage2_mt_buffer_18_2_16_64_32 stage2_mt_buffer_18_2_16_64_32_inst_zdoghtseky ( + .clk(clk), + .reset(reset), + .i_valid(pipelined_mt_valid), + .data_0(mt_pipelined_0), + .q_0(out_mt_buffer_0), + .data_1(mt_pipelined_1), + .q_1(out_mt_buffer_1), + .data_2(mt_pipelined_2), + .q_2(out_mt_buffer_2), + .data_3(mt_pipelined_3), + .q_3(out_mt_buffer_3), + .data_4(mt_pipelined_4), + .q_4(out_mt_buffer_4), + .data_5(mt_pipelined_5), + .q_5(out_mt_buffer_5), + .data_6(mt_pipelined_6), + .q_6(out_mt_buffer_6), + .data_7(mt_pipelined_7), + .q_7(out_mt_buffer_7), + .data_8(mt_pipelined_8), + .q_8(out_mt_buffer_8), + .data_9(mt_pipelined_9), + .q_9(out_mt_buffer_9), + .data_10(mt_pipelined_10), + .q_10(out_mt_buffer_10), + .data_11(mt_pipelined_11), + .q_11(out_mt_buffer_11), + .data_12(mt_pipelined_12), + .q_12(out_mt_buffer_12), + .data_13(mt_pipelined_13), + .q_13(out_mt_buffer_13), + .data_14(mt_pipelined_14), + .q_14(out_mt_buffer_14), + .data_15(mt_pipelined_15), + .q_15(out_mt_buffer_15), + .o_valid(buffer_out_valid) +); + +// C-LSTM Stage 3 and inner-connections +wire stage3_valid, stage3_ready; +wire [17:0] new_Yt_0_0; +wire [17:0] new_Yt_0_1; +wire [17:0] new_Yt_0_2; +wire [17:0] new_Yt_0_3; +wire [17:0] new_Yt_0_4; +wire [17:0] new_Yt_0_5; +wire [17:0] new_Yt_0_6; +wire [17:0] new_Yt_0_7; +wire [17:0] new_Yt_0_8; +wire [17:0] new_Yt_0_9; +wire [17:0] new_Yt_0_10; +wire [17:0] new_Yt_0_11; +wire [17:0] new_Yt_0_12; +wire [17:0] new_Yt_0_13; +wire [17:0] new_Yt_0_14; +wire [17:0] new_Yt_0_15; +wire [17:0] new_Yt_1_0; +wire [17:0] new_Yt_1_1; +wire [17:0] new_Yt_1_2; +wire [17:0] new_Yt_1_3; +wire [17:0] new_Yt_1_4; +wire [17:0] new_Yt_1_5; +wire [17:0] new_Yt_1_6; +wire [17:0] new_Yt_1_7; +wire [17:0] new_Yt_1_8; +wire [17:0] new_Yt_1_9; +wire [17:0] new_Yt_1_10; +wire [17:0] new_Yt_1_11; +wire [17:0] new_Yt_1_12; +wire [17:0] new_Yt_1_13; +wire [17:0] new_Yt_1_14; +wire [17:0] new_Yt_1_15; + +C_LSTM_stage_3_18_10_64_2048_2_16_1 C_LSTM_stage_3_18_10_64_2048_2_16_1_inst_ubtlqrbnyf ( + .clk(clk), + .reset(reset), + .wdata(wdata_stage3), + .wen(wen_stage3), + .i_ready(enable), + .i_valid(buffer_out_valid), + .i_mt_0(out_mt_buffer_0), + .i_mt_1(out_mt_buffer_1), + .i_mt_2(out_mt_buffer_2), + .i_mt_3(out_mt_buffer_3), + .i_mt_4(out_mt_buffer_4), + .i_mt_5(out_mt_buffer_5), + .i_mt_6(out_mt_buffer_6), + .i_mt_7(out_mt_buffer_7), + .i_mt_8(out_mt_buffer_8), + .i_mt_9(out_mt_buffer_9), + .i_mt_10(out_mt_buffer_10), + .i_mt_11(out_mt_buffer_11), + .i_mt_12(out_mt_buffer_12), + .i_mt_13(out_mt_buffer_13), + .i_mt_14(out_mt_buffer_14), + .i_mt_15(out_mt_buffer_15), + .o_Yt_0_0(new_Yt_0_0), + .o_Yt_0_1(new_Yt_0_1), + .o_Yt_0_2(new_Yt_0_2), + .o_Yt_0_3(new_Yt_0_3), + .o_Yt_0_4(new_Yt_0_4), + .o_Yt_0_5(new_Yt_0_5), + .o_Yt_0_6(new_Yt_0_6), + .o_Yt_0_7(new_Yt_0_7), + .o_Yt_0_8(new_Yt_0_8), + .o_Yt_0_9(new_Yt_0_9), + .o_Yt_0_10(new_Yt_0_10), + .o_Yt_0_11(new_Yt_0_11), + .o_Yt_0_12(new_Yt_0_12), + .o_Yt_0_13(new_Yt_0_13), + .o_Yt_0_14(new_Yt_0_14), + .o_Yt_0_15(new_Yt_0_15), + .o_Yt_1_0(new_Yt_1_0), + .o_Yt_1_1(new_Yt_1_1), + .o_Yt_1_2(new_Yt_1_2), + .o_Yt_1_3(new_Yt_1_3), + .o_Yt_1_4(new_Yt_1_4), + .o_Yt_1_5(new_Yt_1_5), + .o_Yt_1_6(new_Yt_1_6), + .o_Yt_1_7(new_Yt_1_7), + .o_Yt_1_8(new_Yt_1_8), + .o_Yt_1_9(new_Yt_1_9), + .o_Yt_1_10(new_Yt_1_10), + .o_Yt_1_11(new_Yt_1_11), + .o_Yt_1_12(new_Yt_1_12), + .o_Yt_1_13(new_Yt_1_13), + .o_Yt_1_14(new_Yt_1_14), + .o_Yt_1_15(new_Yt_1_15), + .o_valid(stage3_valid), + .o_ready(stage3_ready) +); + +assign o_Yt_0_0 = new_Yt_0_0; +assign o_Yt_0_1 = new_Yt_0_1; +assign o_Yt_0_2 = new_Yt_0_2; +assign o_Yt_0_3 = new_Yt_0_3; +assign o_Yt_0_4 = new_Yt_0_4; +assign o_Yt_0_5 = new_Yt_0_5; +assign o_Yt_0_6 = new_Yt_0_6; +assign o_Yt_0_7 = new_Yt_0_7; +assign o_Yt_0_8 = new_Yt_0_8; +assign o_Yt_0_9 = new_Yt_0_9; +assign o_Yt_0_10 = new_Yt_0_10; +assign o_Yt_0_11 = new_Yt_0_11; +assign o_Yt_0_12 = new_Yt_0_12; +assign o_Yt_0_13 = new_Yt_0_13; +assign o_Yt_0_14 = new_Yt_0_14; +assign o_Yt_0_15 = new_Yt_0_15; +assign o_Yt_1_0 = new_Yt_1_0; +assign o_Yt_1_1 = new_Yt_1_1; +assign o_Yt_1_2 = new_Yt_1_2; +assign o_Yt_1_3 = new_Yt_1_3; +assign o_Yt_1_4 = new_Yt_1_4; +assign o_Yt_1_5 = new_Yt_1_5; +assign o_Yt_1_6 = new_Yt_1_6; +assign o_Yt_1_7 = new_Yt_1_7; +assign o_Yt_1_8 = new_Yt_1_8; +assign o_Yt_1_9 = new_Yt_1_9; +assign o_Yt_1_10 = new_Yt_1_10; +assign o_Yt_1_11 = new_Yt_1_11; +assign o_Yt_1_12 = new_Yt_1_12; +assign o_Yt_1_13 = new_Yt_1_13; +assign o_Yt_1_14 = new_Yt_1_14; +assign o_Yt_1_15 = new_Yt_1_15; + +// Stage 3 buffer and inter-connections +wire [17:0] pipelined_Yt_0; +wire [17:0] pipelined_Yt_1; +wire [17:0] pipelined_Yt_2; +wire [17:0] pipelined_Yt_3; +wire [17:0] pipelined_Yt_4; +wire [17:0] pipelined_Yt_5; +wire [17:0] pipelined_Yt_6; +wire [17:0] pipelined_Yt_7; +wire [17:0] pipelined_Yt_8; +wire [17:0] pipelined_Yt_9; +wire [17:0] pipelined_Yt_10; +wire [17:0] pipelined_Yt_11; +wire [17:0] pipelined_Yt_12; +wire [17:0] pipelined_Yt_13; +wire [17:0] pipelined_Yt_14; +wire [17:0] pipelined_Yt_15; +wire pipelined_Yt_valid; + +pipelined_input_18_2_16 pipelined_input_18_2_16_inst_Y ( + .clk(clk), + .reset(reset), + .enable(enable), + .load_input(stage3_valid), + .i_data_0_0(new_Yt_0_0), + .i_data_0_1(new_Yt_0_1), + .i_data_0_2(new_Yt_0_2), + .i_data_0_3(new_Yt_0_3), + .i_data_0_4(new_Yt_0_4), + .i_data_0_5(new_Yt_0_5), + .i_data_0_6(new_Yt_0_6), + .i_data_0_7(new_Yt_0_7), + .i_data_0_8(new_Yt_0_8), + .i_data_0_9(new_Yt_0_9), + .i_data_0_10(new_Yt_0_10), + .i_data_0_11(new_Yt_0_11), + .i_data_0_12(new_Yt_0_12), + .i_data_0_13(new_Yt_0_13), + .i_data_0_14(new_Yt_0_14), + .i_data_0_15(new_Yt_0_15), + .i_data_1_0(new_Yt_1_0), + .i_data_1_1(new_Yt_1_1), + .i_data_1_2(new_Yt_1_2), + .i_data_1_3(new_Yt_1_3), + .i_data_1_4(new_Yt_1_4), + .i_data_1_5(new_Yt_1_5), + .i_data_1_6(new_Yt_1_6), + .i_data_1_7(new_Yt_1_7), + .i_data_1_8(new_Yt_1_8), + .i_data_1_9(new_Yt_1_9), + .i_data_1_10(new_Yt_1_10), + .i_data_1_11(new_Yt_1_11), + .i_data_1_12(new_Yt_1_12), + .i_data_1_13(new_Yt_1_13), + .i_data_1_14(new_Yt_1_14), + .i_data_1_15(new_Yt_1_15), + .o_data_0(pipelined_Yt_0), + .o_data_1(pipelined_Yt_1), + .o_data_2(pipelined_Yt_2), + .o_data_3(pipelined_Yt_3), + .o_data_4(pipelined_Yt_4), + .o_data_5(pipelined_Yt_5), + .o_data_6(pipelined_Yt_6), + .o_data_7(pipelined_Yt_7), + .o_data_8(pipelined_Yt_8), + .o_data_9(pipelined_Yt_9), + .o_data_10(pipelined_Yt_10), + .o_data_11(pipelined_Yt_11), + .o_data_12(pipelined_Yt_12), + .o_data_13(pipelined_Yt_13), + .o_data_14(pipelined_Yt_14), + .o_data_15(pipelined_Yt_15), + .o_valid(pipelined_Yt_valid) +); + +stage3_X_Y_buffer_18_16_2_10_32_64 stage3_X_Y_buffer_18_16_2_10_32_64_inst_tpfdnhkool ( + .clk(clk), + .reset(reset), + .i_X_valid(i_valid), + .i_Y_valid(pipelined_Yt_valid), + .feed_start(start_compute), + .i_X_data_0(i_X_data_0), + .i_Y_data_0(pipelined_Yt_0), + .o_data_0(i_data_0), + .i_X_data_1(i_X_data_1), + .i_Y_data_1(pipelined_Yt_1), + .o_data_1(i_data_1), + .i_X_data_2(i_X_data_2), + .i_Y_data_2(pipelined_Yt_2), + .o_data_2(i_data_2), + .i_X_data_3(i_X_data_3), + .i_Y_data_3(pipelined_Yt_3), + .o_data_3(i_data_3), + .i_X_data_4(i_X_data_4), + .i_Y_data_4(pipelined_Yt_4), + .o_data_4(i_data_4), + .i_X_data_5(i_X_data_5), + .i_Y_data_5(pipelined_Yt_5), + .o_data_5(i_data_5), + .i_X_data_6(i_X_data_6), + .i_Y_data_6(pipelined_Yt_6), + .o_data_6(i_data_6), + .i_X_data_7(i_X_data_7), + .i_Y_data_7(pipelined_Yt_7), + .o_data_7(i_data_7), + .i_X_data_8(i_X_data_8), + .i_Y_data_8(pipelined_Yt_8), + .o_data_8(i_data_8), + .i_X_data_9(i_X_data_9), + .i_Y_data_9(pipelined_Yt_9), + .o_data_9(i_data_9), + .i_X_data_10(i_X_data_10), + .i_Y_data_10(pipelined_Yt_10), + .o_data_10(i_data_10), + .i_X_data_11(i_X_data_11), + .i_Y_data_11(pipelined_Yt_11), + .o_data_11(i_data_11), + .i_X_data_12(i_X_data_12), + .i_Y_data_12(pipelined_Yt_12), + .o_data_12(i_data_12), + .i_X_data_13(i_X_data_13), + .i_Y_data_13(pipelined_Yt_13), + .o_data_13(i_data_13), + .i_X_data_14(i_X_data_14), + .i_Y_data_14(pipelined_Yt_14), + .o_data_14(i_data_14), + .i_X_data_15(i_X_data_15), + .i_Y_data_15(pipelined_Yt_15), + .o_data_15(i_data_15), + .o_valid(out_X_Y_buffer_valid), + .o_ready(o_ready) +); + +assign o_valid = stage3_valid; + +endmodule + +module spram ( + clk, + addr, + we, + data, + out +); + +parameter AWIDTH=10; +parameter NUM_WORDS=1024; +parameter DWIDTH=32; + +input clk; +input [(AWIDTH-1):0] addr; +input we; +input [(DWIDTH-1):0] data; +output reg [(DWIDTH-1):0] out; + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram[NUM_WORDS-1:0]; +always @ (posedge clk) begin + if (we) begin + ram[addr] <= data; + end + out <= ram[addr]; +end + +`else + +defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; +defparam u_single_port_ram.DATA_WIDTH = DWIDTH; +single_port_ram u_single_port_ram( + .addr(addr), + .we(we), + .data(data), + .out(out), + .clk(clk) +); + +`endif + +endmodule + +module dpram ( + clk, + addr1, + addr2, + we1, + we2, + data1, + data2, + out1, + out2 +); + +parameter AWIDTH=10; +parameter NUM_WORDS=1024; +parameter DWIDTH=32; + +input clk; +input [(AWIDTH-1):0] addr1; +input [(AWIDTH-1):0] addr2; +input we1; +input we2; +input [(DWIDTH-1):0] data1; +input [(DWIDTH-1):0] data2; +output reg [(DWIDTH-1):0] out1; +output reg [(DWIDTH-1):0] out2; + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram[NUM_WORDS-1:0]; +always @ (posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end + out1 <= ram[addr1]; +end + +always @ (posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end + out2 <= ram[addr2]; +end + +`else + +defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; +defparam u_dual_port_ram.DATA_WIDTH = DWIDTH; +dual_port_ram u_dual_port_ram( + .addr1(addr1), + .we1(we1), + .data1(data1), + .out1(out1), + .addr2(addr2), + .we2(we2), + .data2(data2), + .out2(out2), + .clk(clk) +); +`endif + +endmodule + + +module stage1_parameter_buffer_18_2_16_42_2688 ( + input clk, + input reset, + input [161:0] wdata, + input [7:0] wen, + output [17:0] Wixr_real_0_0, + output [17:0] Wixr_imag_0_0, + output [17:0] Wfxr_real_0_0, + output [17:0] Wfxr_imag_0_0, + output [17:0] Woxr_real_0_0, + output [17:0] Woxr_imag_0_0, + output [17:0] Wcxr_real_0_0, + output [17:0] Wcxr_imag_0_0, + output [17:0] Wixr_real_0_1, + output [17:0] Wixr_imag_0_1, + output [17:0] Wfxr_real_0_1, + output [17:0] Wfxr_imag_0_1, + output [17:0] Woxr_real_0_1, + output [17:0] Woxr_imag_0_1, + output [17:0] Wcxr_real_0_1, + output [17:0] Wcxr_imag_0_1, + output [17:0] Wixr_real_0_2, + output [17:0] Wixr_imag_0_2, + output [17:0] Wfxr_real_0_2, + output [17:0] Wfxr_imag_0_2, + output [17:0] Woxr_real_0_2, + output [17:0] Woxr_imag_0_2, + output [17:0] Wcxr_real_0_2, + output [17:0] Wcxr_imag_0_2, + output [17:0] Wixr_real_0_3, + output [17:0] Wixr_imag_0_3, + output [17:0] Wfxr_real_0_3, + output [17:0] Wfxr_imag_0_3, + output [17:0] Woxr_real_0_3, + output [17:0] Woxr_imag_0_3, + output [17:0] Wcxr_real_0_3, + output [17:0] Wcxr_imag_0_3, + output [17:0] Wixr_real_0_4, + output [17:0] Wixr_imag_0_4, + output [17:0] Wfxr_real_0_4, + output [17:0] Wfxr_imag_0_4, + output [17:0] Woxr_real_0_4, + output [17:0] Woxr_imag_0_4, + output [17:0] Wcxr_real_0_4, + output [17:0] Wcxr_imag_0_4, + output [17:0] Wixr_real_0_5, + output [17:0] Wixr_imag_0_5, + output [17:0] Wfxr_real_0_5, + output [17:0] Wfxr_imag_0_5, + output [17:0] Woxr_real_0_5, + output [17:0] Woxr_imag_0_5, + output [17:0] Wcxr_real_0_5, + output [17:0] Wcxr_imag_0_5, + output [17:0] Wixr_real_0_6, + output [17:0] Wixr_imag_0_6, + output [17:0] Wfxr_real_0_6, + output [17:0] Wfxr_imag_0_6, + output [17:0] Woxr_real_0_6, + output [17:0] Woxr_imag_0_6, + output [17:0] Wcxr_real_0_6, + output [17:0] Wcxr_imag_0_6, + output [17:0] Wixr_real_0_7, + output [17:0] Wixr_imag_0_7, + output [17:0] Wfxr_real_0_7, + output [17:0] Wfxr_imag_0_7, + output [17:0] Woxr_real_0_7, + output [17:0] Woxr_imag_0_7, + output [17:0] Wcxr_real_0_7, + output [17:0] Wcxr_imag_0_7, + output [17:0] Wixr_real_0_8, + output [17:0] Wixr_imag_0_8, + output [17:0] Wfxr_real_0_8, + output [17:0] Wfxr_imag_0_8, + output [17:0] Woxr_real_0_8, + output [17:0] Woxr_imag_0_8, + output [17:0] Wcxr_real_0_8, + output [17:0] Wcxr_imag_0_8, + output [17:0] Wixr_real_1_0, + output [17:0] Wixr_imag_1_0, + output [17:0] Wfxr_real_1_0, + output [17:0] Wfxr_imag_1_0, + output [17:0] Woxr_real_1_0, + output [17:0] Woxr_imag_1_0, + output [17:0] Wcxr_real_1_0, + output [17:0] Wcxr_imag_1_0, + output [17:0] Wixr_real_1_1, + output [17:0] Wixr_imag_1_1, + output [17:0] Wfxr_real_1_1, + output [17:0] Wfxr_imag_1_1, + output [17:0] Woxr_real_1_1, + output [17:0] Woxr_imag_1_1, + output [17:0] Wcxr_real_1_1, + output [17:0] Wcxr_imag_1_1, + output [17:0] Wixr_real_1_2, + output [17:0] Wixr_imag_1_2, + output [17:0] Wfxr_real_1_2, + output [17:0] Wfxr_imag_1_2, + output [17:0] Woxr_real_1_2, + output [17:0] Woxr_imag_1_2, + output [17:0] Wcxr_real_1_2, + output [17:0] Wcxr_imag_1_2, + output [17:0] Wixr_real_1_3, + output [17:0] Wixr_imag_1_3, + output [17:0] Wfxr_real_1_3, + output [17:0] Wfxr_imag_1_3, + output [17:0] Woxr_real_1_3, + output [17:0] Woxr_imag_1_3, + output [17:0] Wcxr_real_1_3, + output [17:0] Wcxr_imag_1_3, + output [17:0] Wixr_real_1_4, + output [17:0] Wixr_imag_1_4, + output [17:0] Wfxr_real_1_4, + output [17:0] Wfxr_imag_1_4, + output [17:0] Woxr_real_1_4, + output [17:0] Woxr_imag_1_4, + output [17:0] Wcxr_real_1_4, + output [17:0] Wcxr_imag_1_4, + output [17:0] Wixr_real_1_5, + output [17:0] Wixr_imag_1_5, + output [17:0] Wfxr_real_1_5, + output [17:0] Wfxr_imag_1_5, + output [17:0] Woxr_real_1_5, + output [17:0] Woxr_imag_1_5, + output [17:0] Wcxr_real_1_5, + output [17:0] Wcxr_imag_1_5, + output [17:0] Wixr_real_1_6, + output [17:0] Wixr_imag_1_6, + output [17:0] Wfxr_real_1_6, + output [17:0] Wfxr_imag_1_6, + output [17:0] Woxr_real_1_6, + output [17:0] Woxr_imag_1_6, + output [17:0] Wcxr_real_1_6, + output [17:0] Wcxr_imag_1_6, + output [17:0] Wixr_real_1_7, + output [17:0] Wixr_imag_1_7, + output [17:0] Wfxr_real_1_7, + output [17:0] Wfxr_imag_1_7, + output [17:0] Woxr_real_1_7, + output [17:0] Woxr_imag_1_7, + output [17:0] Wcxr_real_1_7, + output [17:0] Wcxr_imag_1_7, + output [17:0] Wixr_real_1_8, + output [17:0] Wixr_imag_1_8, + output [17:0] Wfxr_real_1_8, + output [17:0] Wfxr_imag_1_8, + output [17:0] Woxr_real_1_8, + output [17:0] Woxr_imag_1_8, + output [17:0] Wcxr_real_1_8, + output [17:0] Wcxr_imag_1_8, + input incr_index +); + +// A counter that counts how many sub blocks we have processed +wire [13:0] input_index_counter; +counter_41_1 counter_41_1_inst_bhicwfpdjq ( + .clk(clk), + .reset(reset), + .ena(incr_index), + .count(input_index_counter) +); + +wire incr_row_index; +assign incr_row_index = (input_index_counter == 41); +wire counter_enable_row_index; +assign counter_enable_row_index = (incr_row_index & incr_index); + +// A counter that records which weight portion to use +wire [13:0] weight_row_index_counter; +counter_63_2 counter_63_2_inst_ckqeyeersx ( + .clk(clk), + .reset(reset), + .ena(counter_enable_row_index), + .count(weight_row_index_counter) +); + +reg [13:0] weight_index; +always @ (*) begin + weight_index = weight_row_index_counter * 14'd42 + input_index_counter; +end + +// Input Gate +weight_buffer_18_9_42_2_2688 Wixr_real_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[0]), + .q_0_0(Wixr_real_0_0), + .q_0_1(Wixr_real_0_1), + .q_0_2(Wixr_real_0_2), + .q_0_3(Wixr_real_0_3), + .q_0_4(Wixr_real_0_4), + .q_0_5(Wixr_real_0_5), + .q_0_6(Wixr_real_0_6), + .q_0_7(Wixr_real_0_7), + .q_0_8(Wixr_real_0_8), + .q_1_0(Wixr_real_1_0), + .q_1_1(Wixr_real_1_1), + .q_1_2(Wixr_real_1_2), + .q_1_3(Wixr_real_1_3), + .q_1_4(Wixr_real_1_4), + .q_1_5(Wixr_real_1_5), + .q_1_6(Wixr_real_1_6), + .q_1_7(Wixr_real_1_7), + .q_1_8(Wixr_real_1_8), + .index(weight_index) +); + +weight_buffer_18_9_42_2_2688 Wixr_imag_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[1]), + .q_0_0(Wixr_imag_0_0), + .q_0_1(Wixr_imag_0_1), + .q_0_2(Wixr_imag_0_2), + .q_0_3(Wixr_imag_0_3), + .q_0_4(Wixr_imag_0_4), + .q_0_5(Wixr_imag_0_5), + .q_0_6(Wixr_imag_0_6), + .q_0_7(Wixr_imag_0_7), + .q_0_8(Wixr_imag_0_8), + .q_1_0(Wixr_imag_1_0), + .q_1_1(Wixr_imag_1_1), + .q_1_2(Wixr_imag_1_2), + .q_1_3(Wixr_imag_1_3), + .q_1_4(Wixr_imag_1_4), + .q_1_5(Wixr_imag_1_5), + .q_1_6(Wixr_imag_1_6), + .q_1_7(Wixr_imag_1_7), + .q_1_8(Wixr_imag_1_8), + .index(weight_index) +); + +// Forget Gate +weight_buffer_18_9_42_2_2688 Wfxr_real_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[2]), + .q_0_0(Wfxr_real_0_0), + .q_0_1(Wfxr_real_0_1), + .q_0_2(Wfxr_real_0_2), + .q_0_3(Wfxr_real_0_3), + .q_0_4(Wfxr_real_0_4), + .q_0_5(Wfxr_real_0_5), + .q_0_6(Wfxr_real_0_6), + .q_0_7(Wfxr_real_0_7), + .q_0_8(Wfxr_real_0_8), + .q_1_0(Wfxr_real_1_0), + .q_1_1(Wfxr_real_1_1), + .q_1_2(Wfxr_real_1_2), + .q_1_3(Wfxr_real_1_3), + .q_1_4(Wfxr_real_1_4), + .q_1_5(Wfxr_real_1_5), + .q_1_6(Wfxr_real_1_6), + .q_1_7(Wfxr_real_1_7), + .q_1_8(Wfxr_real_1_8), + .index(weight_index) +); + +weight_buffer_18_9_42_2_2688 Wfxr_imag_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[7]), + .q_0_0(Wfxr_imag_0_0), + .q_0_1(Wfxr_imag_0_1), + .q_0_2(Wfxr_imag_0_2), + .q_0_3(Wfxr_imag_0_3), + .q_0_4(Wfxr_imag_0_4), + .q_0_5(Wfxr_imag_0_5), + .q_0_6(Wfxr_imag_0_6), + .q_0_7(Wfxr_imag_0_7), + .q_0_8(Wfxr_imag_0_8), + .q_1_0(Wfxr_imag_1_0), + .q_1_1(Wfxr_imag_1_1), + .q_1_2(Wfxr_imag_1_2), + .q_1_3(Wfxr_imag_1_3), + .q_1_4(Wfxr_imag_1_4), + .q_1_5(Wfxr_imag_1_5), + .q_1_6(Wfxr_imag_1_6), + .q_1_7(Wfxr_imag_1_7), + .q_1_8(Wfxr_imag_1_8), + .index(weight_index) +); + +// Output Gate +weight_buffer_18_9_42_2_2688 Woxr_real_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[3]), + .q_0_0(Woxr_real_0_0), + .q_0_1(Woxr_real_0_1), + .q_0_2(Woxr_real_0_2), + .q_0_3(Woxr_real_0_3), + .q_0_4(Woxr_real_0_4), + .q_0_5(Woxr_real_0_5), + .q_0_6(Woxr_real_0_6), + .q_0_7(Woxr_real_0_7), + .q_0_8(Woxr_real_0_8), + .q_1_0(Woxr_real_1_0), + .q_1_1(Woxr_real_1_1), + .q_1_2(Woxr_real_1_2), + .q_1_3(Woxr_real_1_3), + .q_1_4(Woxr_real_1_4), + .q_1_5(Woxr_real_1_5), + .q_1_6(Woxr_real_1_6), + .q_1_7(Woxr_real_1_7), + .q_1_8(Woxr_real_1_8), + .index(weight_index) +); + +weight_buffer_18_9_42_2_2688 Woxr_imag_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[4]), + .q_0_0(Woxr_imag_0_0), + .q_0_1(Woxr_imag_0_1), + .q_0_2(Woxr_imag_0_2), + .q_0_3(Woxr_imag_0_3), + .q_0_4(Woxr_imag_0_4), + .q_0_5(Woxr_imag_0_5), + .q_0_6(Woxr_imag_0_6), + .q_0_7(Woxr_imag_0_7), + .q_0_8(Woxr_imag_0_8), + .q_1_0(Woxr_imag_1_0), + .q_1_1(Woxr_imag_1_1), + .q_1_2(Woxr_imag_1_2), + .q_1_3(Woxr_imag_1_3), + .q_1_4(Woxr_imag_1_4), + .q_1_5(Woxr_imag_1_5), + .q_1_6(Woxr_imag_1_6), + .q_1_7(Woxr_imag_1_7), + .q_1_8(Woxr_imag_1_8), + .index(weight_index) +); + +// Output Activation Gate +weight_buffer_18_9_42_2_2688 Wcxr_real_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[5]), + .q_0_0(Wcxr_real_0_0), + .q_0_1(Wcxr_real_0_1), + .q_0_2(Wcxr_real_0_2), + .q_0_3(Wcxr_real_0_3), + .q_0_4(Wcxr_real_0_4), + .q_0_5(Wcxr_real_0_5), + .q_0_6(Wcxr_real_0_6), + .q_0_7(Wcxr_real_0_7), + .q_0_8(Wcxr_real_0_8), + .q_1_0(Wcxr_real_1_0), + .q_1_1(Wcxr_real_1_1), + .q_1_2(Wcxr_real_1_2), + .q_1_3(Wcxr_real_1_3), + .q_1_4(Wcxr_real_1_4), + .q_1_5(Wcxr_real_1_5), + .q_1_6(Wcxr_real_1_6), + .q_1_7(Wcxr_real_1_7), + .q_1_8(Wcxr_real_1_8), + .index(weight_index) +); + +weight_buffer_18_9_42_2_2688 Wcxr_imag_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[6]), + .q_0_0(Wcxr_imag_0_0), + .q_0_1(Wcxr_imag_0_1), + .q_0_2(Wcxr_imag_0_2), + .q_0_3(Wcxr_imag_0_3), + .q_0_4(Wcxr_imag_0_4), + .q_0_5(Wcxr_imag_0_5), + .q_0_6(Wcxr_imag_0_6), + .q_0_7(Wcxr_imag_0_7), + .q_0_8(Wcxr_imag_0_8), + .q_1_0(Wcxr_imag_1_0), + .q_1_1(Wcxr_imag_1_1), + .q_1_2(Wcxr_imag_1_2), + .q_1_3(Wcxr_imag_1_3), + .q_1_4(Wcxr_imag_1_4), + .q_1_5(Wcxr_imag_1_5), + .q_1_6(Wcxr_imag_1_6), + .q_1_7(Wcxr_imag_1_7), + .q_1_8(Wcxr_imag_1_8), + .index(weight_index) +); + +endmodule + + +module counter_41_1 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd1) <= 41) begin + count <= count + 14'd1; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module counter_63_2 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd2) <= 63) begin + count <= count + 14'd2; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module weight_buffer_18_9_42_2_2688 ( + input clk, + input rst, + input [161:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + input [10:0] index +); + +wire [161:0] packed_result_0; +reg [10:0] addrs_0; +reg [10:0] addrs_base_0; +wire [161:0] packed_result_1; +reg [10:0] addrs_1; +reg [10:0] addrs_base_1; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 42; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + end +end + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; + +endmodule + +module shift_register_group_18_16_3 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input reset +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +endmodule + +module shift_register_unit_18_3 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +reg [17:0] shift_registers_1; +reg [17:0] shift_registers_2; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + shift_registers_1 <= 18'd0; + shift_registers_2 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + end +end + +assign out = shift_registers_2; + +endmodule + +module shift_register_unit_1_3 ( + input clk, + input reset, + input enable, + input [0:0] in, + output [0:0] out +); + +reg [0:0] shift_registers_0; +reg [0:0] shift_registers_1; +reg [0:0] shift_registers_2; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 1'd0; + shift_registers_1 <= 1'd0; + shift_registers_2 <= 1'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + end +end + +assign out = shift_registers_2; + +endmodule + +module C_LSTM_stage_1_18_10_160_512_2_16_1 ( + input clk, + input reset, + input enable, + input i_ready, + input [17:0] i_Xt_Yt_1_0, + input [17:0] i_Xt_Yt_1_1, + input [17:0] i_Xt_Yt_1_2, + input [17:0] i_Xt_Yt_1_3, + input [17:0] i_Xt_Yt_1_4, + input [17:0] i_Xt_Yt_1_5, + input [17:0] i_Xt_Yt_1_6, + input [17:0] i_Xt_Yt_1_7, + input [17:0] i_Xt_Yt_1_8, + input [17:0] i_Xt_Yt_1_9, + input [17:0] i_Xt_Yt_1_10, + input [17:0] i_Xt_Yt_1_11, + input [17:0] i_Xt_Yt_1_12, + input [17:0] i_Xt_Yt_1_13, + input [17:0] i_Xt_Yt_1_14, + input [17:0] i_Xt_Yt_1_15, + input [17:0] i_Wixr_real_0_0, + input [17:0] i_Wixr_imag_0_0, + input [17:0] i_Wfxr_real_0_0, + input [17:0] i_Wfxr_imag_0_0, + input [17:0] i_Woxr_real_0_0, + input [17:0] i_Woxr_imag_0_0, + input [17:0] i_Wcxr_real_0_0, + input [17:0] i_Wcxr_imag_0_0, + input [17:0] i_Wixr_real_0_1, + input [17:0] i_Wixr_imag_0_1, + input [17:0] i_Wfxr_real_0_1, + input [17:0] i_Wfxr_imag_0_1, + input [17:0] i_Woxr_real_0_1, + input [17:0] i_Woxr_imag_0_1, + input [17:0] i_Wcxr_real_0_1, + input [17:0] i_Wcxr_imag_0_1, + input [17:0] i_Wixr_real_0_2, + input [17:0] i_Wixr_imag_0_2, + input [17:0] i_Wfxr_real_0_2, + input [17:0] i_Wfxr_imag_0_2, + input [17:0] i_Woxr_real_0_2, + input [17:0] i_Woxr_imag_0_2, + input [17:0] i_Wcxr_real_0_2, + input [17:0] i_Wcxr_imag_0_2, + input [17:0] i_Wixr_real_0_3, + input [17:0] i_Wixr_imag_0_3, + input [17:0] i_Wfxr_real_0_3, + input [17:0] i_Wfxr_imag_0_3, + input [17:0] i_Woxr_real_0_3, + input [17:0] i_Woxr_imag_0_3, + input [17:0] i_Wcxr_real_0_3, + input [17:0] i_Wcxr_imag_0_3, + input [17:0] i_Wixr_real_0_4, + input [17:0] i_Wixr_imag_0_4, + input [17:0] i_Wfxr_real_0_4, + input [17:0] i_Wfxr_imag_0_4, + input [17:0] i_Woxr_real_0_4, + input [17:0] i_Woxr_imag_0_4, + input [17:0] i_Wcxr_real_0_4, + input [17:0] i_Wcxr_imag_0_4, + input [17:0] i_Wixr_real_0_5, + input [17:0] i_Wixr_imag_0_5, + input [17:0] i_Wfxr_real_0_5, + input [17:0] i_Wfxr_imag_0_5, + input [17:0] i_Woxr_real_0_5, + input [17:0] i_Woxr_imag_0_5, + input [17:0] i_Wcxr_real_0_5, + input [17:0] i_Wcxr_imag_0_5, + input [17:0] i_Wixr_real_0_6, + input [17:0] i_Wixr_imag_0_6, + input [17:0] i_Wfxr_real_0_6, + input [17:0] i_Wfxr_imag_0_6, + input [17:0] i_Woxr_real_0_6, + input [17:0] i_Woxr_imag_0_6, + input [17:0] i_Wcxr_real_0_6, + input [17:0] i_Wcxr_imag_0_6, + input [17:0] i_Wixr_real_0_7, + input [17:0] i_Wixr_imag_0_7, + input [17:0] i_Wfxr_real_0_7, + input [17:0] i_Wfxr_imag_0_7, + input [17:0] i_Woxr_real_0_7, + input [17:0] i_Woxr_imag_0_7, + input [17:0] i_Wcxr_real_0_7, + input [17:0] i_Wcxr_imag_0_7, + input [17:0] i_Wixr_real_0_8, + input [17:0] i_Wixr_imag_0_8, + input [17:0] i_Wfxr_real_0_8, + input [17:0] i_Wfxr_imag_0_8, + input [17:0] i_Woxr_real_0_8, + input [17:0] i_Woxr_imag_0_8, + input [17:0] i_Wcxr_real_0_8, + input [17:0] i_Wcxr_imag_0_8, + input [17:0] i_Wixr_real_1_0, + input [17:0] i_Wixr_imag_1_0, + input [17:0] i_Wfxr_real_1_0, + input [17:0] i_Wfxr_imag_1_0, + input [17:0] i_Woxr_real_1_0, + input [17:0] i_Woxr_imag_1_0, + input [17:0] i_Wcxr_real_1_0, + input [17:0] i_Wcxr_imag_1_0, + input [17:0] i_Wixr_real_1_1, + input [17:0] i_Wixr_imag_1_1, + input [17:0] i_Wfxr_real_1_1, + input [17:0] i_Wfxr_imag_1_1, + input [17:0] i_Woxr_real_1_1, + input [17:0] i_Woxr_imag_1_1, + input [17:0] i_Wcxr_real_1_1, + input [17:0] i_Wcxr_imag_1_1, + input [17:0] i_Wixr_real_1_2, + input [17:0] i_Wixr_imag_1_2, + input [17:0] i_Wfxr_real_1_2, + input [17:0] i_Wfxr_imag_1_2, + input [17:0] i_Woxr_real_1_2, + input [17:0] i_Woxr_imag_1_2, + input [17:0] i_Wcxr_real_1_2, + input [17:0] i_Wcxr_imag_1_2, + input [17:0] i_Wixr_real_1_3, + input [17:0] i_Wixr_imag_1_3, + input [17:0] i_Wfxr_real_1_3, + input [17:0] i_Wfxr_imag_1_3, + input [17:0] i_Woxr_real_1_3, + input [17:0] i_Woxr_imag_1_3, + input [17:0] i_Wcxr_real_1_3, + input [17:0] i_Wcxr_imag_1_3, + input [17:0] i_Wixr_real_1_4, + input [17:0] i_Wixr_imag_1_4, + input [17:0] i_Wfxr_real_1_4, + input [17:0] i_Wfxr_imag_1_4, + input [17:0] i_Woxr_real_1_4, + input [17:0] i_Woxr_imag_1_4, + input [17:0] i_Wcxr_real_1_4, + input [17:0] i_Wcxr_imag_1_4, + input [17:0] i_Wixr_real_1_5, + input [17:0] i_Wixr_imag_1_5, + input [17:0] i_Wfxr_real_1_5, + input [17:0] i_Wfxr_imag_1_5, + input [17:0] i_Woxr_real_1_5, + input [17:0] i_Woxr_imag_1_5, + input [17:0] i_Wcxr_real_1_5, + input [17:0] i_Wcxr_imag_1_5, + input [17:0] i_Wixr_real_1_6, + input [17:0] i_Wixr_imag_1_6, + input [17:0] i_Wfxr_real_1_6, + input [17:0] i_Wfxr_imag_1_6, + input [17:0] i_Woxr_real_1_6, + input [17:0] i_Woxr_imag_1_6, + input [17:0] i_Wcxr_real_1_6, + input [17:0] i_Wcxr_imag_1_6, + input [17:0] i_Wixr_real_1_7, + input [17:0] i_Wixr_imag_1_7, + input [17:0] i_Wfxr_real_1_7, + input [17:0] i_Wfxr_imag_1_7, + input [17:0] i_Woxr_real_1_7, + input [17:0] i_Woxr_imag_1_7, + input [17:0] i_Wcxr_real_1_7, + input [17:0] i_Wcxr_imag_1_7, + input [17:0] i_Wixr_real_1_8, + input [17:0] i_Wixr_imag_1_8, + input [17:0] i_Wfxr_real_1_8, + input [17:0] i_Wfxr_imag_1_8, + input [17:0] i_Woxr_real_1_8, + input [17:0] i_Woxr_imag_1_8, + input [17:0] i_Wcxr_real_1_8, + input [17:0] i_Wcxr_imag_1_8, + output o_valid, + output o_ready, + output [17:0] o_WixrXtYt_1_0_0, + output [17:0] o_WfxrXtYt_1_0_0, + output [17:0] o_WoxrXtYt_1_0_0, + output [17:0] o_WcxrXtYt_1_0_0, + output [17:0] o_WixrXtYt_1_0_1, + output [17:0] o_WfxrXtYt_1_0_1, + output [17:0] o_WoxrXtYt_1_0_1, + output [17:0] o_WcxrXtYt_1_0_1, + output [17:0] o_WixrXtYt_1_0_2, + output [17:0] o_WfxrXtYt_1_0_2, + output [17:0] o_WoxrXtYt_1_0_2, + output [17:0] o_WcxrXtYt_1_0_2, + output [17:0] o_WixrXtYt_1_0_3, + output [17:0] o_WfxrXtYt_1_0_3, + output [17:0] o_WoxrXtYt_1_0_3, + output [17:0] o_WcxrXtYt_1_0_3, + output [17:0] o_WixrXtYt_1_0_4, + output [17:0] o_WfxrXtYt_1_0_4, + output [17:0] o_WoxrXtYt_1_0_4, + output [17:0] o_WcxrXtYt_1_0_4, + output [17:0] o_WixrXtYt_1_0_5, + output [17:0] o_WfxrXtYt_1_0_5, + output [17:0] o_WoxrXtYt_1_0_5, + output [17:0] o_WcxrXtYt_1_0_5, + output [17:0] o_WixrXtYt_1_0_6, + output [17:0] o_WfxrXtYt_1_0_6, + output [17:0] o_WoxrXtYt_1_0_6, + output [17:0] o_WcxrXtYt_1_0_6, + output [17:0] o_WixrXtYt_1_0_7, + output [17:0] o_WfxrXtYt_1_0_7, + output [17:0] o_WoxrXtYt_1_0_7, + output [17:0] o_WcxrXtYt_1_0_7, + output [17:0] o_WixrXtYt_1_0_8, + output [17:0] o_WfxrXtYt_1_0_8, + output [17:0] o_WoxrXtYt_1_0_8, + output [17:0] o_WcxrXtYt_1_0_8, + output [17:0] o_WixrXtYt_1_0_9, + output [17:0] o_WfxrXtYt_1_0_9, + output [17:0] o_WoxrXtYt_1_0_9, + output [17:0] o_WcxrXtYt_1_0_9, + output [17:0] o_WixrXtYt_1_0_10, + output [17:0] o_WfxrXtYt_1_0_10, + output [17:0] o_WoxrXtYt_1_0_10, + output [17:0] o_WcxrXtYt_1_0_10, + output [17:0] o_WixrXtYt_1_0_11, + output [17:0] o_WfxrXtYt_1_0_11, + output [17:0] o_WoxrXtYt_1_0_11, + output [17:0] o_WcxrXtYt_1_0_11, + output [17:0] o_WixrXtYt_1_0_12, + output [17:0] o_WfxrXtYt_1_0_12, + output [17:0] o_WoxrXtYt_1_0_12, + output [17:0] o_WcxrXtYt_1_0_12, + output [17:0] o_WixrXtYt_1_0_13, + output [17:0] o_WfxrXtYt_1_0_13, + output [17:0] o_WoxrXtYt_1_0_13, + output [17:0] o_WcxrXtYt_1_0_13, + output [17:0] o_WixrXtYt_1_0_14, + output [17:0] o_WfxrXtYt_1_0_14, + output [17:0] o_WoxrXtYt_1_0_14, + output [17:0] o_WcxrXtYt_1_0_14, + output [17:0] o_WixrXtYt_1_0_15, + output [17:0] o_WfxrXtYt_1_0_15, + output [17:0] o_WoxrXtYt_1_0_15, + output [17:0] o_WcxrXtYt_1_0_15, + output [17:0] o_WixrXtYt_1_1_0, + output [17:0] o_WfxrXtYt_1_1_0, + output [17:0] o_WoxrXtYt_1_1_0, + output [17:0] o_WcxrXtYt_1_1_0, + output [17:0] o_WixrXtYt_1_1_1, + output [17:0] o_WfxrXtYt_1_1_1, + output [17:0] o_WoxrXtYt_1_1_1, + output [17:0] o_WcxrXtYt_1_1_1, + output [17:0] o_WixrXtYt_1_1_2, + output [17:0] o_WfxrXtYt_1_1_2, + output [17:0] o_WoxrXtYt_1_1_2, + output [17:0] o_WcxrXtYt_1_1_2, + output [17:0] o_WixrXtYt_1_1_3, + output [17:0] o_WfxrXtYt_1_1_3, + output [17:0] o_WoxrXtYt_1_1_3, + output [17:0] o_WcxrXtYt_1_1_3, + output [17:0] o_WixrXtYt_1_1_4, + output [17:0] o_WfxrXtYt_1_1_4, + output [17:0] o_WoxrXtYt_1_1_4, + output [17:0] o_WcxrXtYt_1_1_4, + output [17:0] o_WixrXtYt_1_1_5, + output [17:0] o_WfxrXtYt_1_1_5, + output [17:0] o_WoxrXtYt_1_1_5, + output [17:0] o_WcxrXtYt_1_1_5, + output [17:0] o_WixrXtYt_1_1_6, + output [17:0] o_WfxrXtYt_1_1_6, + output [17:0] o_WoxrXtYt_1_1_6, + output [17:0] o_WcxrXtYt_1_1_6, + output [17:0] o_WixrXtYt_1_1_7, + output [17:0] o_WfxrXtYt_1_1_7, + output [17:0] o_WoxrXtYt_1_1_7, + output [17:0] o_WcxrXtYt_1_1_7, + output [17:0] o_WixrXtYt_1_1_8, + output [17:0] o_WfxrXtYt_1_1_8, + output [17:0] o_WoxrXtYt_1_1_8, + output [17:0] o_WcxrXtYt_1_1_8, + output [17:0] o_WixrXtYt_1_1_9, + output [17:0] o_WfxrXtYt_1_1_9, + output [17:0] o_WoxrXtYt_1_1_9, + output [17:0] o_WcxrXtYt_1_1_9, + output [17:0] o_WixrXtYt_1_1_10, + output [17:0] o_WfxrXtYt_1_1_10, + output [17:0] o_WoxrXtYt_1_1_10, + output [17:0] o_WcxrXtYt_1_1_10, + output [17:0] o_WixrXtYt_1_1_11, + output [17:0] o_WfxrXtYt_1_1_11, + output [17:0] o_WoxrXtYt_1_1_11, + output [17:0] o_WcxrXtYt_1_1_11, + output [17:0] o_WixrXtYt_1_1_12, + output [17:0] o_WfxrXtYt_1_1_12, + output [17:0] o_WoxrXtYt_1_1_12, + output [17:0] o_WcxrXtYt_1_1_12, + output [17:0] o_WixrXtYt_1_1_13, + output [17:0] o_WfxrXtYt_1_1_13, + output [17:0] o_WoxrXtYt_1_1_13, + output [17:0] o_WcxrXtYt_1_1_13, + output [17:0] o_WixrXtYt_1_1_14, + output [17:0] o_WfxrXtYt_1_1_14, + output [17:0] o_WoxrXtYt_1_1_14, + output [17:0] o_WcxrXtYt_1_1_14, + output [17:0] o_WixrXtYt_1_1_15, + output [17:0] o_WfxrXtYt_1_1_15, + output [17:0] o_WoxrXtYt_1_1_15, + output [17:0] o_WcxrXtYt_1_1_15, + input i_valid +); + +wire input_gate_mult_valid, forget_gate_mult_valid, output_gate_mult_valid, output_act_mult_valid; +wire input_gate_mult_ready, forget_gate_mult_ready, output_gate_mult_ready, output_act_mult_ready; + +// Input Gate Multiplication +matrix_times_two_vectors_18_10_2_672_16_1 input_gate_mult ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_ready(i_ready), + .i_valid(i_valid), + .i_Xt_Yt_1_0(i_Xt_Yt_1_0), + .i_Xt_Yt_1_1(i_Xt_Yt_1_1), + .i_Xt_Yt_1_2(i_Xt_Yt_1_2), + .i_Xt_Yt_1_3(i_Xt_Yt_1_3), + .i_Xt_Yt_1_4(i_Xt_Yt_1_4), + .i_Xt_Yt_1_5(i_Xt_Yt_1_5), + .i_Xt_Yt_1_6(i_Xt_Yt_1_6), + .i_Xt_Yt_1_7(i_Xt_Yt_1_7), + .i_Xt_Yt_1_8(i_Xt_Yt_1_8), + .i_Xt_Yt_1_9(i_Xt_Yt_1_9), + .i_Xt_Yt_1_10(i_Xt_Yt_1_10), + .i_Xt_Yt_1_11(i_Xt_Yt_1_11), + .i_Xt_Yt_1_12(i_Xt_Yt_1_12), + .i_Xt_Yt_1_13(i_Xt_Yt_1_13), + .i_Xt_Yt_1_14(i_Xt_Yt_1_14), + .i_Xt_Yt_1_15(i_Xt_Yt_1_15), + .i_Wxr_real_0_0(i_Wixr_real_0_0), + .i_Wxr_imag_0_0(i_Wixr_imag_0_0), + .i_Wxr_real_0_1(i_Wixr_real_0_1), + .i_Wxr_imag_0_1(i_Wixr_imag_0_1), + .i_Wxr_real_0_2(i_Wixr_real_0_2), + .i_Wxr_imag_0_2(i_Wixr_imag_0_2), + .i_Wxr_real_0_3(i_Wixr_real_0_3), + .i_Wxr_imag_0_3(i_Wixr_imag_0_3), + .i_Wxr_real_0_4(i_Wixr_real_0_4), + .i_Wxr_imag_0_4(i_Wixr_imag_0_4), + .i_Wxr_real_0_5(i_Wixr_real_0_5), + .i_Wxr_imag_0_5(i_Wixr_imag_0_5), + .i_Wxr_real_0_6(i_Wixr_real_0_6), + .i_Wxr_imag_0_6(i_Wixr_imag_0_6), + .i_Wxr_real_0_7(i_Wixr_real_0_7), + .i_Wxr_imag_0_7(i_Wixr_imag_0_7), + .i_Wxr_real_0_8(i_Wixr_real_0_8), + .i_Wxr_imag_0_8(i_Wixr_imag_0_8), + .i_Wxr_real_1_0(i_Wixr_real_1_0), + .i_Wxr_imag_1_0(i_Wixr_imag_1_0), + .i_Wxr_real_1_1(i_Wixr_real_1_1), + .i_Wxr_imag_1_1(i_Wixr_imag_1_1), + .i_Wxr_real_1_2(i_Wixr_real_1_2), + .i_Wxr_imag_1_2(i_Wixr_imag_1_2), + .i_Wxr_real_1_3(i_Wixr_real_1_3), + .i_Wxr_imag_1_3(i_Wixr_imag_1_3), + .i_Wxr_real_1_4(i_Wixr_real_1_4), + .i_Wxr_imag_1_4(i_Wixr_imag_1_4), + .i_Wxr_real_1_5(i_Wixr_real_1_5), + .i_Wxr_imag_1_5(i_Wixr_imag_1_5), + .i_Wxr_real_1_6(i_Wixr_real_1_6), + .i_Wxr_imag_1_6(i_Wixr_imag_1_6), + .i_Wxr_real_1_7(i_Wixr_real_1_7), + .i_Wxr_imag_1_7(i_Wixr_imag_1_7), + .i_Wxr_real_1_8(i_Wixr_real_1_8), + .i_Wxr_imag_1_8(i_Wixr_imag_1_8), + .o_W_times_X_Y_0_0(o_WixrXtYt_1_0_0), + .o_W_times_X_Y_0_1(o_WixrXtYt_1_0_1), + .o_W_times_X_Y_0_2(o_WixrXtYt_1_0_2), + .o_W_times_X_Y_0_3(o_WixrXtYt_1_0_3), + .o_W_times_X_Y_0_4(o_WixrXtYt_1_0_4), + .o_W_times_X_Y_0_5(o_WixrXtYt_1_0_5), + .o_W_times_X_Y_0_6(o_WixrXtYt_1_0_6), + .o_W_times_X_Y_0_7(o_WixrXtYt_1_0_7), + .o_W_times_X_Y_0_8(o_WixrXtYt_1_0_8), + .o_W_times_X_Y_0_9(o_WixrXtYt_1_0_9), + .o_W_times_X_Y_0_10(o_WixrXtYt_1_0_10), + .o_W_times_X_Y_0_11(o_WixrXtYt_1_0_11), + .o_W_times_X_Y_0_12(o_WixrXtYt_1_0_12), + .o_W_times_X_Y_0_13(o_WixrXtYt_1_0_13), + .o_W_times_X_Y_0_14(o_WixrXtYt_1_0_14), + .o_W_times_X_Y_0_15(o_WixrXtYt_1_0_15), + .o_W_times_X_Y_1_0(o_WixrXtYt_1_1_0), + .o_W_times_X_Y_1_1(o_WixrXtYt_1_1_1), + .o_W_times_X_Y_1_2(o_WixrXtYt_1_1_2), + .o_W_times_X_Y_1_3(o_WixrXtYt_1_1_3), + .o_W_times_X_Y_1_4(o_WixrXtYt_1_1_4), + .o_W_times_X_Y_1_5(o_WixrXtYt_1_1_5), + .o_W_times_X_Y_1_6(o_WixrXtYt_1_1_6), + .o_W_times_X_Y_1_7(o_WixrXtYt_1_1_7), + .o_W_times_X_Y_1_8(o_WixrXtYt_1_1_8), + .o_W_times_X_Y_1_9(o_WixrXtYt_1_1_9), + .o_W_times_X_Y_1_10(o_WixrXtYt_1_1_10), + .o_W_times_X_Y_1_11(o_WixrXtYt_1_1_11), + .o_W_times_X_Y_1_12(o_WixrXtYt_1_1_12), + .o_W_times_X_Y_1_13(o_WixrXtYt_1_1_13), + .o_W_times_X_Y_1_14(o_WixrXtYt_1_1_14), + .o_W_times_X_Y_1_15(o_WixrXtYt_1_1_15), + .o_valid(input_gate_mult_valid), + .o_ready(input_gate_mult_ready) +); + +// Forget Gate Multiplication +matrix_times_two_vectors_18_10_2_672_16_1 forget_gate_mult ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_ready(i_ready), + .i_valid(i_valid), + .i_Xt_Yt_1_0(i_Xt_Yt_1_0), + .i_Xt_Yt_1_1(i_Xt_Yt_1_1), + .i_Xt_Yt_1_2(i_Xt_Yt_1_2), + .i_Xt_Yt_1_3(i_Xt_Yt_1_3), + .i_Xt_Yt_1_4(i_Xt_Yt_1_4), + .i_Xt_Yt_1_5(i_Xt_Yt_1_5), + .i_Xt_Yt_1_6(i_Xt_Yt_1_6), + .i_Xt_Yt_1_7(i_Xt_Yt_1_7), + .i_Xt_Yt_1_8(i_Xt_Yt_1_8), + .i_Xt_Yt_1_9(i_Xt_Yt_1_9), + .i_Xt_Yt_1_10(i_Xt_Yt_1_10), + .i_Xt_Yt_1_11(i_Xt_Yt_1_11), + .i_Xt_Yt_1_12(i_Xt_Yt_1_12), + .i_Xt_Yt_1_13(i_Xt_Yt_1_13), + .i_Xt_Yt_1_14(i_Xt_Yt_1_14), + .i_Xt_Yt_1_15(i_Xt_Yt_1_15), + .i_Wxr_real_0_0(i_Wfxr_real_0_0), + .i_Wxr_imag_0_0(i_Wfxr_imag_0_0), + .i_Wxr_real_0_1(i_Wfxr_real_0_1), + .i_Wxr_imag_0_1(i_Wfxr_imag_0_1), + .i_Wxr_real_0_2(i_Wfxr_real_0_2), + .i_Wxr_imag_0_2(i_Wfxr_imag_0_2), + .i_Wxr_real_0_3(i_Wfxr_real_0_3), + .i_Wxr_imag_0_3(i_Wfxr_imag_0_3), + .i_Wxr_real_0_4(i_Wfxr_real_0_4), + .i_Wxr_imag_0_4(i_Wfxr_imag_0_4), + .i_Wxr_real_0_5(i_Wfxr_real_0_5), + .i_Wxr_imag_0_5(i_Wfxr_imag_0_5), + .i_Wxr_real_0_6(i_Wfxr_real_0_6), + .i_Wxr_imag_0_6(i_Wfxr_imag_0_6), + .i_Wxr_real_0_7(i_Wfxr_real_0_7), + .i_Wxr_imag_0_7(i_Wfxr_imag_0_7), + .i_Wxr_real_0_8(i_Wfxr_real_0_8), + .i_Wxr_imag_0_8(i_Wfxr_imag_0_8), + .i_Wxr_real_1_0(i_Wfxr_real_1_0), + .i_Wxr_imag_1_0(i_Wfxr_imag_1_0), + .i_Wxr_real_1_1(i_Wfxr_real_1_1), + .i_Wxr_imag_1_1(i_Wfxr_imag_1_1), + .i_Wxr_real_1_2(i_Wfxr_real_1_2), + .i_Wxr_imag_1_2(i_Wfxr_imag_1_2), + .i_Wxr_real_1_3(i_Wfxr_real_1_3), + .i_Wxr_imag_1_3(i_Wfxr_imag_1_3), + .i_Wxr_real_1_4(i_Wfxr_real_1_4), + .i_Wxr_imag_1_4(i_Wfxr_imag_1_4), + .i_Wxr_real_1_5(i_Wfxr_real_1_5), + .i_Wxr_imag_1_5(i_Wfxr_imag_1_5), + .i_Wxr_real_1_6(i_Wfxr_real_1_6), + .i_Wxr_imag_1_6(i_Wfxr_imag_1_6), + .i_Wxr_real_1_7(i_Wfxr_real_1_7), + .i_Wxr_imag_1_7(i_Wfxr_imag_1_7), + .i_Wxr_real_1_8(i_Wfxr_real_1_8), + .i_Wxr_imag_1_8(i_Wfxr_imag_1_8), + .o_W_times_X_Y_0_0(o_WfxrXtYt_1_0_0), + .o_W_times_X_Y_0_1(o_WfxrXtYt_1_0_1), + .o_W_times_X_Y_0_2(o_WfxrXtYt_1_0_2), + .o_W_times_X_Y_0_3(o_WfxrXtYt_1_0_3), + .o_W_times_X_Y_0_4(o_WfxrXtYt_1_0_4), + .o_W_times_X_Y_0_5(o_WfxrXtYt_1_0_5), + .o_W_times_X_Y_0_6(o_WfxrXtYt_1_0_6), + .o_W_times_X_Y_0_7(o_WfxrXtYt_1_0_7), + .o_W_times_X_Y_0_8(o_WfxrXtYt_1_0_8), + .o_W_times_X_Y_0_9(o_WfxrXtYt_1_0_9), + .o_W_times_X_Y_0_10(o_WfxrXtYt_1_0_10), + .o_W_times_X_Y_0_11(o_WfxrXtYt_1_0_11), + .o_W_times_X_Y_0_12(o_WfxrXtYt_1_0_12), + .o_W_times_X_Y_0_13(o_WfxrXtYt_1_0_13), + .o_W_times_X_Y_0_14(o_WfxrXtYt_1_0_14), + .o_W_times_X_Y_0_15(o_WfxrXtYt_1_0_15), + .o_W_times_X_Y_1_0(o_WfxrXtYt_1_1_0), + .o_W_times_X_Y_1_1(o_WfxrXtYt_1_1_1), + .o_W_times_X_Y_1_2(o_WfxrXtYt_1_1_2), + .o_W_times_X_Y_1_3(o_WfxrXtYt_1_1_3), + .o_W_times_X_Y_1_4(o_WfxrXtYt_1_1_4), + .o_W_times_X_Y_1_5(o_WfxrXtYt_1_1_5), + .o_W_times_X_Y_1_6(o_WfxrXtYt_1_1_6), + .o_W_times_X_Y_1_7(o_WfxrXtYt_1_1_7), + .o_W_times_X_Y_1_8(o_WfxrXtYt_1_1_8), + .o_W_times_X_Y_1_9(o_WfxrXtYt_1_1_9), + .o_W_times_X_Y_1_10(o_WfxrXtYt_1_1_10), + .o_W_times_X_Y_1_11(o_WfxrXtYt_1_1_11), + .o_W_times_X_Y_1_12(o_WfxrXtYt_1_1_12), + .o_W_times_X_Y_1_13(o_WfxrXtYt_1_1_13), + .o_W_times_X_Y_1_14(o_WfxrXtYt_1_1_14), + .o_W_times_X_Y_1_15(o_WfxrXtYt_1_1_15), + .o_valid(forget_gate_mult_valid), + .o_ready(forget_gate_mult_ready) +); + +// Output Gate Multiplication +matrix_times_two_vectors_18_10_2_672_16_1 output_gate_mult ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_ready(i_ready), + .i_valid(i_valid), + .i_Xt_Yt_1_0(i_Xt_Yt_1_0), + .i_Xt_Yt_1_1(i_Xt_Yt_1_1), + .i_Xt_Yt_1_2(i_Xt_Yt_1_2), + .i_Xt_Yt_1_3(i_Xt_Yt_1_3), + .i_Xt_Yt_1_4(i_Xt_Yt_1_4), + .i_Xt_Yt_1_5(i_Xt_Yt_1_5), + .i_Xt_Yt_1_6(i_Xt_Yt_1_6), + .i_Xt_Yt_1_7(i_Xt_Yt_1_7), + .i_Xt_Yt_1_8(i_Xt_Yt_1_8), + .i_Xt_Yt_1_9(i_Xt_Yt_1_9), + .i_Xt_Yt_1_10(i_Xt_Yt_1_10), + .i_Xt_Yt_1_11(i_Xt_Yt_1_11), + .i_Xt_Yt_1_12(i_Xt_Yt_1_12), + .i_Xt_Yt_1_13(i_Xt_Yt_1_13), + .i_Xt_Yt_1_14(i_Xt_Yt_1_14), + .i_Xt_Yt_1_15(i_Xt_Yt_1_15), + .i_Wxr_real_0_0(i_Woxr_real_0_0), + .i_Wxr_imag_0_0(i_Woxr_imag_0_0), + .i_Wxr_real_0_1(i_Woxr_real_0_1), + .i_Wxr_imag_0_1(i_Woxr_imag_0_1), + .i_Wxr_real_0_2(i_Woxr_real_0_2), + .i_Wxr_imag_0_2(i_Woxr_imag_0_2), + .i_Wxr_real_0_3(i_Woxr_real_0_3), + .i_Wxr_imag_0_3(i_Woxr_imag_0_3), + .i_Wxr_real_0_4(i_Woxr_real_0_4), + .i_Wxr_imag_0_4(i_Woxr_imag_0_4), + .i_Wxr_real_0_5(i_Woxr_real_0_5), + .i_Wxr_imag_0_5(i_Woxr_imag_0_5), + .i_Wxr_real_0_6(i_Woxr_real_0_6), + .i_Wxr_imag_0_6(i_Woxr_imag_0_6), + .i_Wxr_real_0_7(i_Woxr_real_0_7), + .i_Wxr_imag_0_7(i_Woxr_imag_0_7), + .i_Wxr_real_0_8(i_Woxr_real_0_8), + .i_Wxr_imag_0_8(i_Woxr_imag_0_8), + .i_Wxr_real_1_0(i_Woxr_real_1_0), + .i_Wxr_imag_1_0(i_Woxr_imag_1_0), + .i_Wxr_real_1_1(i_Woxr_real_1_1), + .i_Wxr_imag_1_1(i_Woxr_imag_1_1), + .i_Wxr_real_1_2(i_Woxr_real_1_2), + .i_Wxr_imag_1_2(i_Woxr_imag_1_2), + .i_Wxr_real_1_3(i_Woxr_real_1_3), + .i_Wxr_imag_1_3(i_Woxr_imag_1_3), + .i_Wxr_real_1_4(i_Woxr_real_1_4), + .i_Wxr_imag_1_4(i_Woxr_imag_1_4), + .i_Wxr_real_1_5(i_Woxr_real_1_5), + .i_Wxr_imag_1_5(i_Woxr_imag_1_5), + .i_Wxr_real_1_6(i_Woxr_real_1_6), + .i_Wxr_imag_1_6(i_Woxr_imag_1_6), + .i_Wxr_real_1_7(i_Woxr_real_1_7), + .i_Wxr_imag_1_7(i_Woxr_imag_1_7), + .i_Wxr_real_1_8(i_Woxr_real_1_8), + .i_Wxr_imag_1_8(i_Woxr_imag_1_8), + .o_W_times_X_Y_0_0(o_WoxrXtYt_1_0_0), + .o_W_times_X_Y_0_1(o_WoxrXtYt_1_0_1), + .o_W_times_X_Y_0_2(o_WoxrXtYt_1_0_2), + .o_W_times_X_Y_0_3(o_WoxrXtYt_1_0_3), + .o_W_times_X_Y_0_4(o_WoxrXtYt_1_0_4), + .o_W_times_X_Y_0_5(o_WoxrXtYt_1_0_5), + .o_W_times_X_Y_0_6(o_WoxrXtYt_1_0_6), + .o_W_times_X_Y_0_7(o_WoxrXtYt_1_0_7), + .o_W_times_X_Y_0_8(o_WoxrXtYt_1_0_8), + .o_W_times_X_Y_0_9(o_WoxrXtYt_1_0_9), + .o_W_times_X_Y_0_10(o_WoxrXtYt_1_0_10), + .o_W_times_X_Y_0_11(o_WoxrXtYt_1_0_11), + .o_W_times_X_Y_0_12(o_WoxrXtYt_1_0_12), + .o_W_times_X_Y_0_13(o_WoxrXtYt_1_0_13), + .o_W_times_X_Y_0_14(o_WoxrXtYt_1_0_14), + .o_W_times_X_Y_0_15(o_WoxrXtYt_1_0_15), + .o_W_times_X_Y_1_0(o_WoxrXtYt_1_1_0), + .o_W_times_X_Y_1_1(o_WoxrXtYt_1_1_1), + .o_W_times_X_Y_1_2(o_WoxrXtYt_1_1_2), + .o_W_times_X_Y_1_3(o_WoxrXtYt_1_1_3), + .o_W_times_X_Y_1_4(o_WoxrXtYt_1_1_4), + .o_W_times_X_Y_1_5(o_WoxrXtYt_1_1_5), + .o_W_times_X_Y_1_6(o_WoxrXtYt_1_1_6), + .o_W_times_X_Y_1_7(o_WoxrXtYt_1_1_7), + .o_W_times_X_Y_1_8(o_WoxrXtYt_1_1_8), + .o_W_times_X_Y_1_9(o_WoxrXtYt_1_1_9), + .o_W_times_X_Y_1_10(o_WoxrXtYt_1_1_10), + .o_W_times_X_Y_1_11(o_WoxrXtYt_1_1_11), + .o_W_times_X_Y_1_12(o_WoxrXtYt_1_1_12), + .o_W_times_X_Y_1_13(o_WoxrXtYt_1_1_13), + .o_W_times_X_Y_1_14(o_WoxrXtYt_1_1_14), + .o_W_times_X_Y_1_15(o_WoxrXtYt_1_1_15), + .o_valid(output_gate_mult_valid), + .o_ready(output_gate_mult_ready) +); + +// Output Activation Multiplication +matrix_times_two_vectors_18_10_2_672_16_1 output_act_gate_mult ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_ready(i_ready), + .i_valid(i_valid), + .i_Xt_Yt_1_0(i_Xt_Yt_1_0), + .i_Xt_Yt_1_1(i_Xt_Yt_1_1), + .i_Xt_Yt_1_2(i_Xt_Yt_1_2), + .i_Xt_Yt_1_3(i_Xt_Yt_1_3), + .i_Xt_Yt_1_4(i_Xt_Yt_1_4), + .i_Xt_Yt_1_5(i_Xt_Yt_1_5), + .i_Xt_Yt_1_6(i_Xt_Yt_1_6), + .i_Xt_Yt_1_7(i_Xt_Yt_1_7), + .i_Xt_Yt_1_8(i_Xt_Yt_1_8), + .i_Xt_Yt_1_9(i_Xt_Yt_1_9), + .i_Xt_Yt_1_10(i_Xt_Yt_1_10), + .i_Xt_Yt_1_11(i_Xt_Yt_1_11), + .i_Xt_Yt_1_12(i_Xt_Yt_1_12), + .i_Xt_Yt_1_13(i_Xt_Yt_1_13), + .i_Xt_Yt_1_14(i_Xt_Yt_1_14), + .i_Xt_Yt_1_15(i_Xt_Yt_1_15), + .i_Wxr_real_0_0(i_Wcxr_real_0_0), + .i_Wxr_imag_0_0(i_Wcxr_imag_0_0), + .i_Wxr_real_0_1(i_Wcxr_real_0_1), + .i_Wxr_imag_0_1(i_Wcxr_imag_0_1), + .i_Wxr_real_0_2(i_Wcxr_real_0_2), + .i_Wxr_imag_0_2(i_Wcxr_imag_0_2), + .i_Wxr_real_0_3(i_Wcxr_real_0_3), + .i_Wxr_imag_0_3(i_Wcxr_imag_0_3), + .i_Wxr_real_0_4(i_Wcxr_real_0_4), + .i_Wxr_imag_0_4(i_Wcxr_imag_0_4), + .i_Wxr_real_0_5(i_Wcxr_real_0_5), + .i_Wxr_imag_0_5(i_Wcxr_imag_0_5), + .i_Wxr_real_0_6(i_Wcxr_real_0_6), + .i_Wxr_imag_0_6(i_Wcxr_imag_0_6), + .i_Wxr_real_0_7(i_Wcxr_real_0_7), + .i_Wxr_imag_0_7(i_Wcxr_imag_0_7), + .i_Wxr_real_0_8(i_Wcxr_real_0_8), + .i_Wxr_imag_0_8(i_Wcxr_imag_0_8), + .i_Wxr_real_1_0(i_Wcxr_real_1_0), + .i_Wxr_imag_1_0(i_Wcxr_imag_1_0), + .i_Wxr_real_1_1(i_Wcxr_real_1_1), + .i_Wxr_imag_1_1(i_Wcxr_imag_1_1), + .i_Wxr_real_1_2(i_Wcxr_real_1_2), + .i_Wxr_imag_1_2(i_Wcxr_imag_1_2), + .i_Wxr_real_1_3(i_Wcxr_real_1_3), + .i_Wxr_imag_1_3(i_Wcxr_imag_1_3), + .i_Wxr_real_1_4(i_Wcxr_real_1_4), + .i_Wxr_imag_1_4(i_Wcxr_imag_1_4), + .i_Wxr_real_1_5(i_Wcxr_real_1_5), + .i_Wxr_imag_1_5(i_Wcxr_imag_1_5), + .i_Wxr_real_1_6(i_Wcxr_real_1_6), + .i_Wxr_imag_1_6(i_Wcxr_imag_1_6), + .i_Wxr_real_1_7(i_Wcxr_real_1_7), + .i_Wxr_imag_1_7(i_Wcxr_imag_1_7), + .i_Wxr_real_1_8(i_Wcxr_real_1_8), + .i_Wxr_imag_1_8(i_Wcxr_imag_1_8), + .o_W_times_X_Y_0_0(o_WcxrXtYt_1_0_0), + .o_W_times_X_Y_0_1(o_WcxrXtYt_1_0_1), + .o_W_times_X_Y_0_2(o_WcxrXtYt_1_0_2), + .o_W_times_X_Y_0_3(o_WcxrXtYt_1_0_3), + .o_W_times_X_Y_0_4(o_WcxrXtYt_1_0_4), + .o_W_times_X_Y_0_5(o_WcxrXtYt_1_0_5), + .o_W_times_X_Y_0_6(o_WcxrXtYt_1_0_6), + .o_W_times_X_Y_0_7(o_WcxrXtYt_1_0_7), + .o_W_times_X_Y_0_8(o_WcxrXtYt_1_0_8), + .o_W_times_X_Y_0_9(o_WcxrXtYt_1_0_9), + .o_W_times_X_Y_0_10(o_WcxrXtYt_1_0_10), + .o_W_times_X_Y_0_11(o_WcxrXtYt_1_0_11), + .o_W_times_X_Y_0_12(o_WcxrXtYt_1_0_12), + .o_W_times_X_Y_0_13(o_WcxrXtYt_1_0_13), + .o_W_times_X_Y_0_14(o_WcxrXtYt_1_0_14), + .o_W_times_X_Y_0_15(o_WcxrXtYt_1_0_15), + .o_W_times_X_Y_1_0(o_WcxrXtYt_1_1_0), + .o_W_times_X_Y_1_1(o_WcxrXtYt_1_1_1), + .o_W_times_X_Y_1_2(o_WcxrXtYt_1_1_2), + .o_W_times_X_Y_1_3(o_WcxrXtYt_1_1_3), + .o_W_times_X_Y_1_4(o_WcxrXtYt_1_1_4), + .o_W_times_X_Y_1_5(o_WcxrXtYt_1_1_5), + .o_W_times_X_Y_1_6(o_WcxrXtYt_1_1_6), + .o_W_times_X_Y_1_7(o_WcxrXtYt_1_1_7), + .o_W_times_X_Y_1_8(o_WcxrXtYt_1_1_8), + .o_W_times_X_Y_1_9(o_WcxrXtYt_1_1_9), + .o_W_times_X_Y_1_10(o_WcxrXtYt_1_1_10), + .o_W_times_X_Y_1_11(o_WcxrXtYt_1_1_11), + .o_W_times_X_Y_1_12(o_WcxrXtYt_1_1_12), + .o_W_times_X_Y_1_13(o_WcxrXtYt_1_1_13), + .o_W_times_X_Y_1_14(o_WcxrXtYt_1_1_14), + .o_W_times_X_Y_1_15(o_WcxrXtYt_1_1_15), + .o_valid(output_act_mult_valid), + .o_ready(output_act_mult_ready) +); + +assign o_valid = input_gate_mult_valid & forget_gate_mult_valid & output_gate_mult_valid & output_act_mult_valid; +assign o_ready = input_gate_mult_ready & forget_gate_mult_ready & output_gate_mult_ready & output_act_mult_ready; + +endmodule + +module matrix_times_two_vectors_18_10_2_672_16_1 ( + input clk, + input reset, + input enable, + input i_ready, + input i_valid, + input [17:0] i_Xt_Yt_1_0, + input [17:0] i_Xt_Yt_1_1, + input [17:0] i_Xt_Yt_1_2, + input [17:0] i_Xt_Yt_1_3, + input [17:0] i_Xt_Yt_1_4, + input [17:0] i_Xt_Yt_1_5, + input [17:0] i_Xt_Yt_1_6, + input [17:0] i_Xt_Yt_1_7, + input [17:0] i_Xt_Yt_1_8, + input [17:0] i_Xt_Yt_1_9, + input [17:0] i_Xt_Yt_1_10, + input [17:0] i_Xt_Yt_1_11, + input [17:0] i_Xt_Yt_1_12, + input [17:0] i_Xt_Yt_1_13, + input [17:0] i_Xt_Yt_1_14, + input [17:0] i_Xt_Yt_1_15, + input [17:0] i_Wxr_real_0_0, + input [17:0] i_Wxr_imag_0_0, + input [17:0] i_Wxr_real_0_1, + input [17:0] i_Wxr_imag_0_1, + input [17:0] i_Wxr_real_0_2, + input [17:0] i_Wxr_imag_0_2, + input [17:0] i_Wxr_real_0_3, + input [17:0] i_Wxr_imag_0_3, + input [17:0] i_Wxr_real_0_4, + input [17:0] i_Wxr_imag_0_4, + input [17:0] i_Wxr_real_0_5, + input [17:0] i_Wxr_imag_0_5, + input [17:0] i_Wxr_real_0_6, + input [17:0] i_Wxr_imag_0_6, + input [17:0] i_Wxr_real_0_7, + input [17:0] i_Wxr_imag_0_7, + input [17:0] i_Wxr_real_0_8, + input [17:0] i_Wxr_imag_0_8, + input [17:0] i_Wxr_real_1_0, + input [17:0] i_Wxr_imag_1_0, + input [17:0] i_Wxr_real_1_1, + input [17:0] i_Wxr_imag_1_1, + input [17:0] i_Wxr_real_1_2, + input [17:0] i_Wxr_imag_1_2, + input [17:0] i_Wxr_real_1_3, + input [17:0] i_Wxr_imag_1_3, + input [17:0] i_Wxr_real_1_4, + input [17:0] i_Wxr_imag_1_4, + input [17:0] i_Wxr_real_1_5, + input [17:0] i_Wxr_imag_1_5, + input [17:0] i_Wxr_real_1_6, + input [17:0] i_Wxr_imag_1_6, + input [17:0] i_Wxr_real_1_7, + input [17:0] i_Wxr_imag_1_7, + input [17:0] i_Wxr_real_1_8, + input [17:0] i_Wxr_imag_1_8, + output [17:0] o_W_times_X_Y_0_0, + output [17:0] o_W_times_X_Y_0_1, + output [17:0] o_W_times_X_Y_0_2, + output [17:0] o_W_times_X_Y_0_3, + output [17:0] o_W_times_X_Y_0_4, + output [17:0] o_W_times_X_Y_0_5, + output [17:0] o_W_times_X_Y_0_6, + output [17:0] o_W_times_X_Y_0_7, + output [17:0] o_W_times_X_Y_0_8, + output [17:0] o_W_times_X_Y_0_9, + output [17:0] o_W_times_X_Y_0_10, + output [17:0] o_W_times_X_Y_0_11, + output [17:0] o_W_times_X_Y_0_12, + output [17:0] o_W_times_X_Y_0_13, + output [17:0] o_W_times_X_Y_0_14, + output [17:0] o_W_times_X_Y_0_15, + output [17:0] o_W_times_X_Y_1_0, + output [17:0] o_W_times_X_Y_1_1, + output [17:0] o_W_times_X_Y_1_2, + output [17:0] o_W_times_X_Y_1_3, + output [17:0] o_W_times_X_Y_1_4, + output [17:0] o_W_times_X_Y_1_5, + output [17:0] o_W_times_X_Y_1_6, + output [17:0] o_W_times_X_Y_1_7, + output [17:0] o_W_times_X_Y_1_8, + output [17:0] o_W_times_X_Y_1_9, + output [17:0] o_W_times_X_Y_1_10, + output [17:0] o_W_times_X_Y_1_11, + output [17:0] o_W_times_X_Y_1_12, + output [17:0] o_W_times_X_Y_1_13, + output [17:0] o_W_times_X_Y_1_14, + output [17:0] o_W_times_X_Y_1_15, + output o_valid, + output o_ready +); + +multiple_c_matrix_vec_mult_and_sum_18_10_16_1_2_42 multiple_c_matrix_vec_mult_and_sum_18_10_16_1_2_42_inst_dzuiykhfmx ( + .clk(clk), + .reset(reset), + .i_ready(i_ready), + .i_valid(i_valid), + .i_X_0(i_Xt_Yt_1_0), + .i_X_1(i_Xt_Yt_1_1), + .i_X_2(i_Xt_Yt_1_2), + .i_X_3(i_Xt_Yt_1_3), + .i_X_4(i_Xt_Yt_1_4), + .i_X_5(i_Xt_Yt_1_5), + .i_X_6(i_Xt_Yt_1_6), + .i_X_7(i_Xt_Yt_1_7), + .i_X_8(i_Xt_Yt_1_8), + .i_X_9(i_Xt_Yt_1_9), + .i_X_10(i_Xt_Yt_1_10), + .i_X_11(i_Xt_Yt_1_11), + .i_X_12(i_Xt_Yt_1_12), + .i_X_13(i_Xt_Yt_1_13), + .i_X_14(i_Xt_Yt_1_14), + .i_X_15(i_Xt_Yt_1_15), + .i_W_real_0_0(i_Wxr_real_0_0), + .i_W_imag_0_0(i_Wxr_imag_0_0), + .i_W_real_0_1(i_Wxr_real_0_1), + .i_W_imag_0_1(i_Wxr_imag_0_1), + .i_W_real_0_2(i_Wxr_real_0_2), + .i_W_imag_0_2(i_Wxr_imag_0_2), + .i_W_real_0_3(i_Wxr_real_0_3), + .i_W_imag_0_3(i_Wxr_imag_0_3), + .i_W_real_0_4(i_Wxr_real_0_4), + .i_W_imag_0_4(i_Wxr_imag_0_4), + .i_W_real_0_5(i_Wxr_real_0_5), + .i_W_imag_0_5(i_Wxr_imag_0_5), + .i_W_real_0_6(i_Wxr_real_0_6), + .i_W_imag_0_6(i_Wxr_imag_0_6), + .i_W_real_0_7(i_Wxr_real_0_7), + .i_W_imag_0_7(i_Wxr_imag_0_7), + .i_W_real_0_8(i_Wxr_real_0_8), + .i_W_imag_0_8(i_Wxr_imag_0_8), + .i_W_real_1_0(i_Wxr_real_1_0), + .i_W_imag_1_0(i_Wxr_imag_1_0), + .i_W_real_1_1(i_Wxr_real_1_1), + .i_W_imag_1_1(i_Wxr_imag_1_1), + .i_W_real_1_2(i_Wxr_real_1_2), + .i_W_imag_1_2(i_Wxr_imag_1_2), + .i_W_real_1_3(i_Wxr_real_1_3), + .i_W_imag_1_3(i_Wxr_imag_1_3), + .i_W_real_1_4(i_Wxr_real_1_4), + .i_W_imag_1_4(i_Wxr_imag_1_4), + .i_W_real_1_5(i_Wxr_real_1_5), + .i_W_imag_1_5(i_Wxr_imag_1_5), + .i_W_real_1_6(i_Wxr_real_1_6), + .i_W_imag_1_6(i_Wxr_imag_1_6), + .i_W_real_1_7(i_Wxr_real_1_7), + .i_W_imag_1_7(i_Wxr_imag_1_7), + .i_W_real_1_8(i_Wxr_real_1_8), + .i_W_imag_1_8(i_Wxr_imag_1_8), + .o_Y_0_0(o_W_times_X_Y_0_0), + .o_Y_0_1(o_W_times_X_Y_0_1), + .o_Y_0_2(o_W_times_X_Y_0_2), + .o_Y_0_3(o_W_times_X_Y_0_3), + .o_Y_0_4(o_W_times_X_Y_0_4), + .o_Y_0_5(o_W_times_X_Y_0_5), + .o_Y_0_6(o_W_times_X_Y_0_6), + .o_Y_0_7(o_W_times_X_Y_0_7), + .o_Y_0_8(o_W_times_X_Y_0_8), + .o_Y_0_9(o_W_times_X_Y_0_9), + .o_Y_0_10(o_W_times_X_Y_0_10), + .o_Y_0_11(o_W_times_X_Y_0_11), + .o_Y_0_12(o_W_times_X_Y_0_12), + .o_Y_0_13(o_W_times_X_Y_0_13), + .o_Y_0_14(o_W_times_X_Y_0_14), + .o_Y_0_15(o_W_times_X_Y_0_15), + .o_Y_1_0(o_W_times_X_Y_1_0), + .o_Y_1_1(o_W_times_X_Y_1_1), + .o_Y_1_2(o_W_times_X_Y_1_2), + .o_Y_1_3(o_W_times_X_Y_1_3), + .o_Y_1_4(o_W_times_X_Y_1_4), + .o_Y_1_5(o_W_times_X_Y_1_5), + .o_Y_1_6(o_W_times_X_Y_1_6), + .o_Y_1_7(o_W_times_X_Y_1_7), + .o_Y_1_8(o_W_times_X_Y_1_8), + .o_Y_1_9(o_W_times_X_Y_1_9), + .o_Y_1_10(o_W_times_X_Y_1_10), + .o_Y_1_11(o_W_times_X_Y_1_11), + .o_Y_1_12(o_W_times_X_Y_1_12), + .o_Y_1_13(o_W_times_X_Y_1_13), + .o_Y_1_14(o_W_times_X_Y_1_14), + .o_Y_1_15(o_W_times_X_Y_1_15), + .o_valid(o_valid), + .o_ready(o_ready) +); + +endmodule + +module multiple_c_matrix_vec_mult_and_sum_18_10_16_1_2_42 ( + input clk, + input reset, + input i_ready, + input i_valid, + input [17:0] i_X_0, + input [17:0] i_X_1, + input [17:0] i_X_2, + input [17:0] i_X_3, + input [17:0] i_X_4, + input [17:0] i_X_5, + input [17:0] i_X_6, + input [17:0] i_X_7, + input [17:0] i_X_8, + input [17:0] i_X_9, + input [17:0] i_X_10, + input [17:0] i_X_11, + input [17:0] i_X_12, + input [17:0] i_X_13, + input [17:0] i_X_14, + input [17:0] i_X_15, + input [17:0] i_W_real_0_0, + input [17:0] i_W_imag_0_0, + input [17:0] i_W_real_0_1, + input [17:0] i_W_imag_0_1, + input [17:0] i_W_real_0_2, + input [17:0] i_W_imag_0_2, + input [17:0] i_W_real_0_3, + input [17:0] i_W_imag_0_3, + input [17:0] i_W_real_0_4, + input [17:0] i_W_imag_0_4, + input [17:0] i_W_real_0_5, + input [17:0] i_W_imag_0_5, + input [17:0] i_W_real_0_6, + input [17:0] i_W_imag_0_6, + input [17:0] i_W_real_0_7, + input [17:0] i_W_imag_0_7, + input [17:0] i_W_real_0_8, + input [17:0] i_W_imag_0_8, + input [17:0] i_W_real_1_0, + input [17:0] i_W_imag_1_0, + input [17:0] i_W_real_1_1, + input [17:0] i_W_imag_1_1, + input [17:0] i_W_real_1_2, + input [17:0] i_W_imag_1_2, + input [17:0] i_W_real_1_3, + input [17:0] i_W_imag_1_3, + input [17:0] i_W_real_1_4, + input [17:0] i_W_imag_1_4, + input [17:0] i_W_real_1_5, + input [17:0] i_W_imag_1_5, + input [17:0] i_W_real_1_6, + input [17:0] i_W_imag_1_6, + input [17:0] i_W_real_1_7, + input [17:0] i_W_imag_1_7, + input [17:0] i_W_real_1_8, + input [17:0] i_W_imag_1_8, + output [17:0] o_Y_0_0, + output [17:0] o_Y_0_1, + output [17:0] o_Y_0_2, + output [17:0] o_Y_0_3, + output [17:0] o_Y_0_4, + output [17:0] o_Y_0_5, + output [17:0] o_Y_0_6, + output [17:0] o_Y_0_7, + output [17:0] o_Y_0_8, + output [17:0] o_Y_0_9, + output [17:0] o_Y_0_10, + output [17:0] o_Y_0_11, + output [17:0] o_Y_0_12, + output [17:0] o_Y_0_13, + output [17:0] o_Y_0_14, + output [17:0] o_Y_0_15, + output [17:0] o_Y_1_0, + output [17:0] o_Y_1_1, + output [17:0] o_Y_1_2, + output [17:0] o_Y_1_3, + output [17:0] o_Y_1_4, + output [17:0] o_Y_1_5, + output [17:0] o_Y_1_6, + output [17:0] o_Y_1_7, + output [17:0] o_Y_1_8, + output [17:0] o_Y_1_9, + output [17:0] o_Y_1_10, + output [17:0] o_Y_1_11, + output [17:0] o_Y_1_12, + output [17:0] o_Y_1_13, + output [17:0] o_Y_1_14, + output [17:0] o_Y_1_15, + output o_valid, + output o_ready +); + +wire matrix_vec_mult_ready, matrix_vec_mult_valid; +wire accum_valid_0; +wire idft_next_out_0; +wire accum_valid_1; +wire idft_next_out_1; +reg idft_out_valid; +wire [17:0] Y_imag_0_0; +wire [17:0] Y_real_0_0; +wire [17:0] sum_Y_real_0_0; +wire [17:0] sum_Y_imag_0_0; +wire [17:0] sum_Y_real_hold_0_0; +wire [17:0] sum_Y_imag_hold_0_0; +wire [17:0] out_Y_idft_0_0; +reg [17:0] reg_Y_0_0; +wire [17:0] Y_imag_0_1; +wire [17:0] Y_real_0_1; +wire [17:0] sum_Y_real_0_1; +wire [17:0] sum_Y_imag_0_1; +wire [17:0] sum_Y_real_hold_0_1; +wire [17:0] sum_Y_imag_hold_0_1; +wire [17:0] out_Y_idft_0_1; +reg [17:0] reg_Y_0_1; +wire [17:0] Y_imag_0_2; +wire [17:0] Y_real_0_2; +wire [17:0] sum_Y_real_0_2; +wire [17:0] sum_Y_imag_0_2; +wire [17:0] sum_Y_real_hold_0_2; +wire [17:0] sum_Y_imag_hold_0_2; +wire [17:0] out_Y_idft_0_2; +reg [17:0] reg_Y_0_2; +wire [17:0] Y_imag_0_3; +wire [17:0] Y_real_0_3; +wire [17:0] sum_Y_real_0_3; +wire [17:0] sum_Y_imag_0_3; +wire [17:0] sum_Y_real_hold_0_3; +wire [17:0] sum_Y_imag_hold_0_3; +wire [17:0] out_Y_idft_0_3; +reg [17:0] reg_Y_0_3; +wire [17:0] Y_imag_0_4; +wire [17:0] Y_real_0_4; +wire [17:0] sum_Y_real_0_4; +wire [17:0] sum_Y_imag_0_4; +wire [17:0] sum_Y_real_hold_0_4; +wire [17:0] sum_Y_imag_hold_0_4; +wire [17:0] out_Y_idft_0_4; +reg [17:0] reg_Y_0_4; +wire [17:0] Y_imag_0_5; +wire [17:0] Y_real_0_5; +wire [17:0] sum_Y_real_0_5; +wire [17:0] sum_Y_imag_0_5; +wire [17:0] sum_Y_real_hold_0_5; +wire [17:0] sum_Y_imag_hold_0_5; +wire [17:0] out_Y_idft_0_5; +reg [17:0] reg_Y_0_5; +wire [17:0] Y_imag_0_6; +wire [17:0] Y_real_0_6; +wire [17:0] sum_Y_real_0_6; +wire [17:0] sum_Y_imag_0_6; +wire [17:0] sum_Y_real_hold_0_6; +wire [17:0] sum_Y_imag_hold_0_6; +wire [17:0] out_Y_idft_0_6; +reg [17:0] reg_Y_0_6; +wire [17:0] Y_imag_0_7; +wire [17:0] Y_real_0_7; +wire [17:0] sum_Y_real_0_7; +wire [17:0] sum_Y_imag_0_7; +wire [17:0] sum_Y_real_hold_0_7; +wire [17:0] sum_Y_imag_hold_0_7; +wire [17:0] out_Y_idft_0_7; +reg [17:0] reg_Y_0_7; +wire [17:0] Y_imag_0_8; +wire [17:0] Y_real_0_8; +wire [17:0] sum_Y_real_0_8; +wire [17:0] sum_Y_imag_0_8; +wire [17:0] sum_Y_real_hold_0_8; +wire [17:0] sum_Y_imag_hold_0_8; +wire [17:0] out_Y_idft_0_8; +reg [17:0] reg_Y_0_8; +wire [17:0] Y_imag_0_9; +wire [17:0] Y_real_0_9; +wire [17:0] sum_Y_real_0_9; +wire [17:0] sum_Y_imag_0_9; +wire [17:0] sum_Y_real_hold_0_9; +wire [17:0] sum_Y_imag_hold_0_9; +wire [17:0] out_Y_idft_0_9; +reg [17:0] reg_Y_0_9; +wire [17:0] Y_imag_0_10; +wire [17:0] Y_real_0_10; +wire [17:0] sum_Y_real_0_10; +wire [17:0] sum_Y_imag_0_10; +wire [17:0] sum_Y_real_hold_0_10; +wire [17:0] sum_Y_imag_hold_0_10; +wire [17:0] out_Y_idft_0_10; +reg [17:0] reg_Y_0_10; +wire [17:0] Y_imag_0_11; +wire [17:0] Y_real_0_11; +wire [17:0] sum_Y_real_0_11; +wire [17:0] sum_Y_imag_0_11; +wire [17:0] sum_Y_real_hold_0_11; +wire [17:0] sum_Y_imag_hold_0_11; +wire [17:0] out_Y_idft_0_11; +reg [17:0] reg_Y_0_11; +wire [17:0] Y_imag_0_12; +wire [17:0] Y_real_0_12; +wire [17:0] sum_Y_real_0_12; +wire [17:0] sum_Y_imag_0_12; +wire [17:0] sum_Y_real_hold_0_12; +wire [17:0] sum_Y_imag_hold_0_12; +wire [17:0] out_Y_idft_0_12; +reg [17:0] reg_Y_0_12; +wire [17:0] Y_imag_0_13; +wire [17:0] Y_real_0_13; +wire [17:0] sum_Y_real_0_13; +wire [17:0] sum_Y_imag_0_13; +wire [17:0] sum_Y_real_hold_0_13; +wire [17:0] sum_Y_imag_hold_0_13; +wire [17:0] out_Y_idft_0_13; +reg [17:0] reg_Y_0_13; +wire [17:0] Y_imag_0_14; +wire [17:0] Y_real_0_14; +wire [17:0] sum_Y_real_0_14; +wire [17:0] sum_Y_imag_0_14; +wire [17:0] sum_Y_real_hold_0_14; +wire [17:0] sum_Y_imag_hold_0_14; +wire [17:0] out_Y_idft_0_14; +reg [17:0] reg_Y_0_14; +wire [17:0] Y_imag_0_15; +wire [17:0] Y_real_0_15; +wire [17:0] sum_Y_real_0_15; +wire [17:0] sum_Y_imag_0_15; +wire [17:0] sum_Y_real_hold_0_15; +wire [17:0] sum_Y_imag_hold_0_15; +wire [17:0] out_Y_idft_0_15; +reg [17:0] reg_Y_0_15; +wire [17:0] Y_imag_1_0; +wire [17:0] Y_real_1_0; +wire [17:0] sum_Y_real_1_0; +wire [17:0] sum_Y_imag_1_0; +wire [17:0] sum_Y_real_hold_1_0; +wire [17:0] sum_Y_imag_hold_1_0; +wire [17:0] out_Y_idft_1_0; +reg [17:0] reg_Y_1_0; +wire [17:0] Y_imag_1_1; +wire [17:0] Y_real_1_1; +wire [17:0] sum_Y_real_1_1; +wire [17:0] sum_Y_imag_1_1; +wire [17:0] sum_Y_real_hold_1_1; +wire [17:0] sum_Y_imag_hold_1_1; +wire [17:0] out_Y_idft_1_1; +reg [17:0] reg_Y_1_1; +wire [17:0] Y_imag_1_2; +wire [17:0] Y_real_1_2; +wire [17:0] sum_Y_real_1_2; +wire [17:0] sum_Y_imag_1_2; +wire [17:0] sum_Y_real_hold_1_2; +wire [17:0] sum_Y_imag_hold_1_2; +wire [17:0] out_Y_idft_1_2; +reg [17:0] reg_Y_1_2; +wire [17:0] Y_imag_1_3; +wire [17:0] Y_real_1_3; +wire [17:0] sum_Y_real_1_3; +wire [17:0] sum_Y_imag_1_3; +wire [17:0] sum_Y_real_hold_1_3; +wire [17:0] sum_Y_imag_hold_1_3; +wire [17:0] out_Y_idft_1_3; +reg [17:0] reg_Y_1_3; +wire [17:0] Y_imag_1_4; +wire [17:0] Y_real_1_4; +wire [17:0] sum_Y_real_1_4; +wire [17:0] sum_Y_imag_1_4; +wire [17:0] sum_Y_real_hold_1_4; +wire [17:0] sum_Y_imag_hold_1_4; +wire [17:0] out_Y_idft_1_4; +reg [17:0] reg_Y_1_4; +wire [17:0] Y_imag_1_5; +wire [17:0] Y_real_1_5; +wire [17:0] sum_Y_real_1_5; +wire [17:0] sum_Y_imag_1_5; +wire [17:0] sum_Y_real_hold_1_5; +wire [17:0] sum_Y_imag_hold_1_5; +wire [17:0] out_Y_idft_1_5; +reg [17:0] reg_Y_1_5; +wire [17:0] Y_imag_1_6; +wire [17:0] Y_real_1_6; +wire [17:0] sum_Y_real_1_6; +wire [17:0] sum_Y_imag_1_6; +wire [17:0] sum_Y_real_hold_1_6; +wire [17:0] sum_Y_imag_hold_1_6; +wire [17:0] out_Y_idft_1_6; +reg [17:0] reg_Y_1_6; +wire [17:0] Y_imag_1_7; +wire [17:0] Y_real_1_7; +wire [17:0] sum_Y_real_1_7; +wire [17:0] sum_Y_imag_1_7; +wire [17:0] sum_Y_real_hold_1_7; +wire [17:0] sum_Y_imag_hold_1_7; +wire [17:0] out_Y_idft_1_7; +reg [17:0] reg_Y_1_7; +wire [17:0] Y_imag_1_8; +wire [17:0] Y_real_1_8; +wire [17:0] sum_Y_real_1_8; +wire [17:0] sum_Y_imag_1_8; +wire [17:0] sum_Y_real_hold_1_8; +wire [17:0] sum_Y_imag_hold_1_8; +wire [17:0] out_Y_idft_1_8; +reg [17:0] reg_Y_1_8; +wire [17:0] Y_imag_1_9; +wire [17:0] Y_real_1_9; +wire [17:0] sum_Y_real_1_9; +wire [17:0] sum_Y_imag_1_9; +wire [17:0] sum_Y_real_hold_1_9; +wire [17:0] sum_Y_imag_hold_1_9; +wire [17:0] out_Y_idft_1_9; +reg [17:0] reg_Y_1_9; +wire [17:0] Y_imag_1_10; +wire [17:0] Y_real_1_10; +wire [17:0] sum_Y_real_1_10; +wire [17:0] sum_Y_imag_1_10; +wire [17:0] sum_Y_real_hold_1_10; +wire [17:0] sum_Y_imag_hold_1_10; +wire [17:0] out_Y_idft_1_10; +reg [17:0] reg_Y_1_10; +wire [17:0] Y_imag_1_11; +wire [17:0] Y_real_1_11; +wire [17:0] sum_Y_real_1_11; +wire [17:0] sum_Y_imag_1_11; +wire [17:0] sum_Y_real_hold_1_11; +wire [17:0] sum_Y_imag_hold_1_11; +wire [17:0] out_Y_idft_1_11; +reg [17:0] reg_Y_1_11; +wire [17:0] Y_imag_1_12; +wire [17:0] Y_real_1_12; +wire [17:0] sum_Y_real_1_12; +wire [17:0] sum_Y_imag_1_12; +wire [17:0] sum_Y_real_hold_1_12; +wire [17:0] sum_Y_imag_hold_1_12; +wire [17:0] out_Y_idft_1_12; +reg [17:0] reg_Y_1_12; +wire [17:0] Y_imag_1_13; +wire [17:0] Y_real_1_13; +wire [17:0] sum_Y_real_1_13; +wire [17:0] sum_Y_imag_1_13; +wire [17:0] sum_Y_real_hold_1_13; +wire [17:0] sum_Y_imag_hold_1_13; +wire [17:0] out_Y_idft_1_13; +reg [17:0] reg_Y_1_13; +wire [17:0] Y_imag_1_14; +wire [17:0] Y_real_1_14; +wire [17:0] sum_Y_real_1_14; +wire [17:0] sum_Y_imag_1_14; +wire [17:0] sum_Y_real_hold_1_14; +wire [17:0] sum_Y_imag_hold_1_14; +wire [17:0] out_Y_idft_1_14; +reg [17:0] reg_Y_1_14; +wire [17:0] Y_imag_1_15; +wire [17:0] Y_real_1_15; +wire [17:0] sum_Y_real_1_15; +wire [17:0] sum_Y_imag_1_15; +wire [17:0] sum_Y_real_hold_1_15; +wire [17:0] sum_Y_imag_hold_1_15; +wire [17:0] out_Y_idft_1_15; +reg [17:0] reg_Y_1_15; +reg reg_o_valid; + +// Enable whenever the reciever is ready +wire enable; +assign enable = i_ready; +c_matrix_vec_mult_core_18_10_16_2_1 c_matrix_vec_mult_core_18_10_16_2_1_inst_tdpssbybvy ( + .clk(clk), + .reset(reset), + .i_ready(i_ready), + .i_valid(i_valid), + .i_X_0(i_X_0), + .i_X_1(i_X_1), + .i_X_2(i_X_2), + .i_X_3(i_X_3), + .i_X_4(i_X_4), + .i_X_5(i_X_5), + .i_X_6(i_X_6), + .i_X_7(i_X_7), + .i_X_8(i_X_8), + .i_X_9(i_X_9), + .i_X_10(i_X_10), + .i_X_11(i_X_11), + .i_X_12(i_X_12), + .i_X_13(i_X_13), + .i_X_14(i_X_14), + .i_X_15(i_X_15), + .i_W_real_0_0(i_W_real_0_0), + .i_W_imag_0_0(i_W_imag_0_0), + .i_W_real_0_1(i_W_real_0_1), + .i_W_imag_0_1(i_W_imag_0_1), + .i_W_real_0_2(i_W_real_0_2), + .i_W_imag_0_2(i_W_imag_0_2), + .i_W_real_0_3(i_W_real_0_3), + .i_W_imag_0_3(i_W_imag_0_3), + .i_W_real_0_4(i_W_real_0_4), + .i_W_imag_0_4(i_W_imag_0_4), + .i_W_real_0_5(i_W_real_0_5), + .i_W_imag_0_5(i_W_imag_0_5), + .i_W_real_0_6(i_W_real_0_6), + .i_W_imag_0_6(i_W_imag_0_6), + .i_W_real_0_7(i_W_real_0_7), + .i_W_imag_0_7(i_W_imag_0_7), + .i_W_real_0_8(i_W_real_0_8), + .i_W_imag_0_8(i_W_imag_0_8), + .i_W_real_1_0(i_W_real_1_0), + .i_W_imag_1_0(i_W_imag_1_0), + .i_W_real_1_1(i_W_real_1_1), + .i_W_imag_1_1(i_W_imag_1_1), + .i_W_real_1_2(i_W_real_1_2), + .i_W_imag_1_2(i_W_imag_1_2), + .i_W_real_1_3(i_W_real_1_3), + .i_W_imag_1_3(i_W_imag_1_3), + .i_W_real_1_4(i_W_real_1_4), + .i_W_imag_1_4(i_W_imag_1_4), + .i_W_real_1_5(i_W_real_1_5), + .i_W_imag_1_5(i_W_imag_1_5), + .i_W_real_1_6(i_W_real_1_6), + .i_W_imag_1_6(i_W_imag_1_6), + .i_W_real_1_7(i_W_real_1_7), + .i_W_imag_1_7(i_W_imag_1_7), + .i_W_real_1_8(i_W_real_1_8), + .i_W_imag_1_8(i_W_imag_1_8), + .o_Y_real_0_0(Y_real_0_0), + .o_Y_imag_0_0(Y_imag_0_0), + .o_Y_real_0_1(Y_real_0_1), + .o_Y_imag_0_1(Y_imag_0_1), + .o_Y_real_0_2(Y_real_0_2), + .o_Y_imag_0_2(Y_imag_0_2), + .o_Y_real_0_3(Y_real_0_3), + .o_Y_imag_0_3(Y_imag_0_3), + .o_Y_real_0_4(Y_real_0_4), + .o_Y_imag_0_4(Y_imag_0_4), + .o_Y_real_0_5(Y_real_0_5), + .o_Y_imag_0_5(Y_imag_0_5), + .o_Y_real_0_6(Y_real_0_6), + .o_Y_imag_0_6(Y_imag_0_6), + .o_Y_real_0_7(Y_real_0_7), + .o_Y_imag_0_7(Y_imag_0_7), + .o_Y_real_0_8(Y_real_0_8), + .o_Y_imag_0_8(Y_imag_0_8), + .o_Y_real_0_9(Y_real_0_9), + .o_Y_imag_0_9(Y_imag_0_9), + .o_Y_real_0_10(Y_real_0_10), + .o_Y_imag_0_10(Y_imag_0_10), + .o_Y_real_0_11(Y_real_0_11), + .o_Y_imag_0_11(Y_imag_0_11), + .o_Y_real_0_12(Y_real_0_12), + .o_Y_imag_0_12(Y_imag_0_12), + .o_Y_real_0_13(Y_real_0_13), + .o_Y_imag_0_13(Y_imag_0_13), + .o_Y_real_0_14(Y_real_0_14), + .o_Y_imag_0_14(Y_imag_0_14), + .o_Y_real_0_15(Y_real_0_15), + .o_Y_imag_0_15(Y_imag_0_15), + .o_Y_real_1_0(Y_real_1_0), + .o_Y_imag_1_0(Y_imag_1_0), + .o_Y_real_1_1(Y_real_1_1), + .o_Y_imag_1_1(Y_imag_1_1), + .o_Y_real_1_2(Y_real_1_2), + .o_Y_imag_1_2(Y_imag_1_2), + .o_Y_real_1_3(Y_real_1_3), + .o_Y_imag_1_3(Y_imag_1_3), + .o_Y_real_1_4(Y_real_1_4), + .o_Y_imag_1_4(Y_imag_1_4), + .o_Y_real_1_5(Y_real_1_5), + .o_Y_imag_1_5(Y_imag_1_5), + .o_Y_real_1_6(Y_real_1_6), + .o_Y_imag_1_6(Y_imag_1_6), + .o_Y_real_1_7(Y_real_1_7), + .o_Y_imag_1_7(Y_imag_1_7), + .o_Y_real_1_8(Y_real_1_8), + .o_Y_imag_1_8(Y_imag_1_8), + .o_Y_real_1_9(Y_real_1_9), + .o_Y_imag_1_9(Y_imag_1_9), + .o_Y_real_1_10(Y_real_1_10), + .o_Y_imag_1_10(Y_imag_1_10), + .o_Y_real_1_11(Y_real_1_11), + .o_Y_imag_1_11(Y_imag_1_11), + .o_Y_real_1_12(Y_real_1_12), + .o_Y_imag_1_12(Y_imag_1_12), + .o_Y_real_1_13(Y_real_1_13), + .o_Y_imag_1_13(Y_imag_1_13), + .o_Y_real_1_14(Y_real_1_14), + .o_Y_imag_1_14(Y_imag_1_14), + .o_Y_real_1_15(Y_real_1_15), + .o_Y_imag_1_15(Y_imag_1_15), + .o_ready(matrix_vec_mult_ready), + .o_valid(matrix_vec_mult_valid) +); + +sum_complex_vector_unit_18_18_16_42 sum_complex_vector_unit_18_18_16_42_inst_suelqikfyn ( + .clk(clk), + .clr(reset), + .enable(enable), + .i_valid(matrix_vec_mult_valid), + .i_real_0(Y_real_0_0), + .i_imag_0(Y_imag_0_0), + .o_real_0(sum_Y_real_0_0), + .o_imag_0(sum_Y_imag_0_0), + .i_real_1(Y_real_0_1), + .i_imag_1(Y_imag_0_1), + .o_real_1(sum_Y_real_0_1), + .o_imag_1(sum_Y_imag_0_1), + .i_real_2(Y_real_0_2), + .i_imag_2(Y_imag_0_2), + .o_real_2(sum_Y_real_0_2), + .o_imag_2(sum_Y_imag_0_2), + .i_real_3(Y_real_0_3), + .i_imag_3(Y_imag_0_3), + .o_real_3(sum_Y_real_0_3), + .o_imag_3(sum_Y_imag_0_3), + .i_real_4(Y_real_0_4), + .i_imag_4(Y_imag_0_4), + .o_real_4(sum_Y_real_0_4), + .o_imag_4(sum_Y_imag_0_4), + .i_real_5(Y_real_0_5), + .i_imag_5(Y_imag_0_5), + .o_real_5(sum_Y_real_0_5), + .o_imag_5(sum_Y_imag_0_5), + .i_real_6(Y_real_0_6), + .i_imag_6(Y_imag_0_6), + .o_real_6(sum_Y_real_0_6), + .o_imag_6(sum_Y_imag_0_6), + .i_real_7(Y_real_0_7), + .i_imag_7(Y_imag_0_7), + .o_real_7(sum_Y_real_0_7), + .o_imag_7(sum_Y_imag_0_7), + .i_real_8(Y_real_0_8), + .i_imag_8(Y_imag_0_8), + .o_real_8(sum_Y_real_0_8), + .o_imag_8(sum_Y_imag_0_8), + .i_real_9(Y_real_0_9), + .i_imag_9(Y_imag_0_9), + .o_real_9(sum_Y_real_0_9), + .o_imag_9(sum_Y_imag_0_9), + .i_real_10(Y_real_0_10), + .i_imag_10(Y_imag_0_10), + .o_real_10(sum_Y_real_0_10), + .o_imag_10(sum_Y_imag_0_10), + .i_real_11(Y_real_0_11), + .i_imag_11(Y_imag_0_11), + .o_real_11(sum_Y_real_0_11), + .o_imag_11(sum_Y_imag_0_11), + .i_real_12(Y_real_0_12), + .i_imag_12(Y_imag_0_12), + .o_real_12(sum_Y_real_0_12), + .o_imag_12(sum_Y_imag_0_12), + .i_real_13(Y_real_0_13), + .i_imag_13(Y_imag_0_13), + .o_real_13(sum_Y_real_0_13), + .o_imag_13(sum_Y_imag_0_13), + .i_real_14(Y_real_0_14), + .i_imag_14(Y_imag_0_14), + .o_real_14(sum_Y_real_0_14), + .o_imag_14(sum_Y_imag_0_14), + .i_real_15(Y_real_0_15), + .i_imag_15(Y_imag_0_15), + .o_real_15(sum_Y_real_0_15), + .o_imag_15(sum_Y_imag_0_15), + .o_valid(accum_valid_0) +); + +sum_complex_vector_unit_18_18_16_42 sum_complex_vector_unit_18_18_16_42_inst_eilmbsxloj ( + .clk(clk), + .clr(reset), + .enable(enable), + .i_valid(matrix_vec_mult_valid), + .i_real_0(Y_real_1_0), + .i_imag_0(Y_imag_1_0), + .o_real_0(sum_Y_real_1_0), + .o_imag_0(sum_Y_imag_1_0), + .i_real_1(Y_real_1_1), + .i_imag_1(Y_imag_1_1), + .o_real_1(sum_Y_real_1_1), + .o_imag_1(sum_Y_imag_1_1), + .i_real_2(Y_real_1_2), + .i_imag_2(Y_imag_1_2), + .o_real_2(sum_Y_real_1_2), + .o_imag_2(sum_Y_imag_1_2), + .i_real_3(Y_real_1_3), + .i_imag_3(Y_imag_1_3), + .o_real_3(sum_Y_real_1_3), + .o_imag_3(sum_Y_imag_1_3), + .i_real_4(Y_real_1_4), + .i_imag_4(Y_imag_1_4), + .o_real_4(sum_Y_real_1_4), + .o_imag_4(sum_Y_imag_1_4), + .i_real_5(Y_real_1_5), + .i_imag_5(Y_imag_1_5), + .o_real_5(sum_Y_real_1_5), + .o_imag_5(sum_Y_imag_1_5), + .i_real_6(Y_real_1_6), + .i_imag_6(Y_imag_1_6), + .o_real_6(sum_Y_real_1_6), + .o_imag_6(sum_Y_imag_1_6), + .i_real_7(Y_real_1_7), + .i_imag_7(Y_imag_1_7), + .o_real_7(sum_Y_real_1_7), + .o_imag_7(sum_Y_imag_1_7), + .i_real_8(Y_real_1_8), + .i_imag_8(Y_imag_1_8), + .o_real_8(sum_Y_real_1_8), + .o_imag_8(sum_Y_imag_1_8), + .i_real_9(Y_real_1_9), + .i_imag_9(Y_imag_1_9), + .o_real_9(sum_Y_real_1_9), + .o_imag_9(sum_Y_imag_1_9), + .i_real_10(Y_real_1_10), + .i_imag_10(Y_imag_1_10), + .o_real_10(sum_Y_real_1_10), + .o_imag_10(sum_Y_imag_1_10), + .i_real_11(Y_real_1_11), + .i_imag_11(Y_imag_1_11), + .o_real_11(sum_Y_real_1_11), + .o_imag_11(sum_Y_imag_1_11), + .i_real_12(Y_real_1_12), + .i_imag_12(Y_imag_1_12), + .o_real_12(sum_Y_real_1_12), + .o_imag_12(sum_Y_imag_1_12), + .i_real_13(Y_real_1_13), + .i_imag_13(Y_imag_1_13), + .o_real_13(sum_Y_real_1_13), + .o_imag_13(sum_Y_imag_1_13), + .i_real_14(Y_real_1_14), + .i_imag_14(Y_imag_1_14), + .o_real_14(sum_Y_real_1_14), + .o_imag_14(sum_Y_imag_1_14), + .i_real_15(Y_real_1_15), + .i_imag_15(Y_imag_1_15), + .o_real_15(sum_Y_real_1_15), + .o_imag_15(sum_Y_imag_1_15), + .o_valid(accum_valid_1) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_mptgqtubfg_real ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_real_0_0), + .out_0(sum_Y_real_hold_0_0), + .in_1(sum_Y_real_0_1), + .out_1(sum_Y_real_hold_0_1), + .in_2(sum_Y_real_0_2), + .out_2(sum_Y_real_hold_0_2), + .in_3(sum_Y_real_0_3), + .out_3(sum_Y_real_hold_0_3), + .in_4(sum_Y_real_0_4), + .out_4(sum_Y_real_hold_0_4), + .in_5(sum_Y_real_0_5), + .out_5(sum_Y_real_hold_0_5), + .in_6(sum_Y_real_0_6), + .out_6(sum_Y_real_hold_0_6), + .in_7(sum_Y_real_0_7), + .out_7(sum_Y_real_hold_0_7), + .in_8(sum_Y_real_0_8), + .out_8(sum_Y_real_hold_0_8), + .in_9(sum_Y_real_0_9), + .out_9(sum_Y_real_hold_0_9), + .in_10(sum_Y_real_0_10), + .out_10(sum_Y_real_hold_0_10), + .in_11(sum_Y_real_0_11), + .out_11(sum_Y_real_hold_0_11), + .in_12(sum_Y_real_0_12), + .out_12(sum_Y_real_hold_0_12), + .in_13(sum_Y_real_0_13), + .out_13(sum_Y_real_hold_0_13), + .in_14(sum_Y_real_0_14), + .out_14(sum_Y_real_hold_0_14), + .in_15(sum_Y_real_0_15), + .out_15(sum_Y_real_hold_0_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_adbtcnzjuz_imag ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_imag_0_0), + .out_0(sum_Y_imag_hold_0_0), + .in_1(sum_Y_imag_0_1), + .out_1(sum_Y_imag_hold_0_1), + .in_2(sum_Y_imag_0_2), + .out_2(sum_Y_imag_hold_0_2), + .in_3(sum_Y_imag_0_3), + .out_3(sum_Y_imag_hold_0_3), + .in_4(sum_Y_imag_0_4), + .out_4(sum_Y_imag_hold_0_4), + .in_5(sum_Y_imag_0_5), + .out_5(sum_Y_imag_hold_0_5), + .in_6(sum_Y_imag_0_6), + .out_6(sum_Y_imag_hold_0_6), + .in_7(sum_Y_imag_0_7), + .out_7(sum_Y_imag_hold_0_7), + .in_8(sum_Y_imag_0_8), + .out_8(sum_Y_imag_hold_0_8), + .in_9(sum_Y_imag_0_9), + .out_9(sum_Y_imag_hold_0_9), + .in_10(sum_Y_imag_0_10), + .out_10(sum_Y_imag_hold_0_10), + .in_11(sum_Y_imag_0_11), + .out_11(sum_Y_imag_hold_0_11), + .in_12(sum_Y_imag_0_12), + .out_12(sum_Y_imag_hold_0_12), + .in_13(sum_Y_imag_0_13), + .out_13(sum_Y_imag_hold_0_13), + .in_14(sum_Y_imag_0_14), + .out_14(sum_Y_imag_hold_0_14), + .in_15(sum_Y_imag_0_15), + .out_15(sum_Y_imag_hold_0_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_wzhywhnoad_real ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_real_1_0), + .out_0(sum_Y_real_hold_1_0), + .in_1(sum_Y_real_1_1), + .out_1(sum_Y_real_hold_1_1), + .in_2(sum_Y_real_1_2), + .out_2(sum_Y_real_hold_1_2), + .in_3(sum_Y_real_1_3), + .out_3(sum_Y_real_hold_1_3), + .in_4(sum_Y_real_1_4), + .out_4(sum_Y_real_hold_1_4), + .in_5(sum_Y_real_1_5), + .out_5(sum_Y_real_hold_1_5), + .in_6(sum_Y_real_1_6), + .out_6(sum_Y_real_hold_1_6), + .in_7(sum_Y_real_1_7), + .out_7(sum_Y_real_hold_1_7), + .in_8(sum_Y_real_1_8), + .out_8(sum_Y_real_hold_1_8), + .in_9(sum_Y_real_1_9), + .out_9(sum_Y_real_hold_1_9), + .in_10(sum_Y_real_1_10), + .out_10(sum_Y_real_hold_1_10), + .in_11(sum_Y_real_1_11), + .out_11(sum_Y_real_hold_1_11), + .in_12(sum_Y_real_1_12), + .out_12(sum_Y_real_hold_1_12), + .in_13(sum_Y_real_1_13), + .out_13(sum_Y_real_hold_1_13), + .in_14(sum_Y_real_1_14), + .out_14(sum_Y_real_hold_1_14), + .in_15(sum_Y_real_1_15), + .out_15(sum_Y_real_hold_1_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_ngnfpoodyv_imag ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_imag_1_0), + .out_0(sum_Y_imag_hold_1_0), + .in_1(sum_Y_imag_1_1), + .out_1(sum_Y_imag_hold_1_1), + .in_2(sum_Y_imag_1_2), + .out_2(sum_Y_imag_hold_1_2), + .in_3(sum_Y_imag_1_3), + .out_3(sum_Y_imag_hold_1_3), + .in_4(sum_Y_imag_1_4), + .out_4(sum_Y_imag_hold_1_4), + .in_5(sum_Y_imag_1_5), + .out_5(sum_Y_imag_hold_1_5), + .in_6(sum_Y_imag_1_6), + .out_6(sum_Y_imag_hold_1_6), + .in_7(sum_Y_imag_1_7), + .out_7(sum_Y_imag_hold_1_7), + .in_8(sum_Y_imag_1_8), + .out_8(sum_Y_imag_hold_1_8), + .in_9(sum_Y_imag_1_9), + .out_9(sum_Y_imag_hold_1_9), + .in_10(sum_Y_imag_1_10), + .out_10(sum_Y_imag_hold_1_10), + .in_11(sum_Y_imag_1_11), + .out_11(sum_Y_imag_hold_1_11), + .in_12(sum_Y_imag_1_12), + .out_12(sum_Y_imag_hold_1_12), + .in_13(sum_Y_imag_1_13), + .out_13(sum_Y_imag_hold_1_13), + .in_14(sum_Y_imag_1_14), + .out_14(sum_Y_imag_hold_1_14), + .in_15(sum_Y_imag_1_15), + .out_15(sum_Y_imag_hold_1_15), + .reset(reset) +); + +idft_16_top_18 idft_16_top_18_inst_bxqwvwmyhz ( + .clk(clk), + .reset(reset), + .next(accum_valid_0), + .X0(sum_Y_real_hold_0_0), + .Y0(out_Y_idft_0_0), + .X1(sum_Y_imag_hold_0_0), + .Y1(), + .X2(sum_Y_real_hold_0_1), + .Y2(out_Y_idft_0_1), + .X3(sum_Y_imag_hold_0_1), + .Y3(), + .X4(sum_Y_real_hold_0_2), + .Y4(out_Y_idft_0_2), + .X5(sum_Y_imag_hold_0_2), + .Y5(), + .X6(sum_Y_real_hold_0_3), + .Y6(out_Y_idft_0_3), + .X7(sum_Y_imag_hold_0_3), + .Y7(), + .X8(sum_Y_real_hold_0_4), + .Y8(out_Y_idft_0_4), + .X9(sum_Y_imag_hold_0_4), + .Y9(), + .X10(sum_Y_real_hold_0_5), + .Y10(out_Y_idft_0_5), + .X11(sum_Y_imag_hold_0_5), + .Y11(), + .X12(sum_Y_real_hold_0_6), + .Y12(out_Y_idft_0_6), + .X13(sum_Y_imag_hold_0_6), + .Y13(), + .X14(sum_Y_real_hold_0_7), + .Y14(out_Y_idft_0_7), + .X15(sum_Y_imag_hold_0_7), + .Y15(), + .X16(sum_Y_real_hold_0_8), + .Y16(out_Y_idft_0_8), + .X17(sum_Y_imag_hold_0_8), + .Y17(), + .X18(sum_Y_real_hold_0_9), + .Y18(out_Y_idft_0_9), + .X19(sum_Y_imag_hold_0_9), + .Y19(), + .X20(sum_Y_real_hold_0_10), + .Y20(out_Y_idft_0_10), + .X21(sum_Y_imag_hold_0_10), + .Y21(), + .X22(sum_Y_real_hold_0_11), + .Y22(out_Y_idft_0_11), + .X23(sum_Y_imag_hold_0_11), + .Y23(), + .X24(sum_Y_real_hold_0_12), + .Y24(out_Y_idft_0_12), + .X25(sum_Y_imag_hold_0_12), + .Y25(), + .X26(sum_Y_real_hold_0_13), + .Y26(out_Y_idft_0_13), + .X27(sum_Y_imag_hold_0_13), + .Y27(), + .X28(sum_Y_real_hold_0_14), + .Y28(out_Y_idft_0_14), + .X29(sum_Y_imag_hold_0_14), + .Y29(), + .X30(sum_Y_real_hold_0_15), + .Y30(out_Y_idft_0_15), + .X31(sum_Y_imag_hold_0_15), + .Y31(), + .next_out(idft_next_out_0) +); + +idft_16_top_18 idft_16_top_18_inst_ddfupduscl ( + .clk(clk), + .reset(reset), + .next(accum_valid_1), + .X0(sum_Y_real_hold_1_0), + .Y0(out_Y_idft_1_0), + .X1(sum_Y_imag_hold_1_0), + .Y1(), + .X2(sum_Y_real_hold_1_1), + .Y2(out_Y_idft_1_1), + .X3(sum_Y_imag_hold_1_1), + .Y3(), + .X4(sum_Y_real_hold_1_2), + .Y4(out_Y_idft_1_2), + .X5(sum_Y_imag_hold_1_2), + .Y5(), + .X6(sum_Y_real_hold_1_3), + .Y6(out_Y_idft_1_3), + .X7(sum_Y_imag_hold_1_3), + .Y7(), + .X8(sum_Y_real_hold_1_4), + .Y8(out_Y_idft_1_4), + .X9(sum_Y_imag_hold_1_4), + .Y9(), + .X10(sum_Y_real_hold_1_5), + .Y10(out_Y_idft_1_5), + .X11(sum_Y_imag_hold_1_5), + .Y11(), + .X12(sum_Y_real_hold_1_6), + .Y12(out_Y_idft_1_6), + .X13(sum_Y_imag_hold_1_6), + .Y13(), + .X14(sum_Y_real_hold_1_7), + .Y14(out_Y_idft_1_7), + .X15(sum_Y_imag_hold_1_7), + .Y15(), + .X16(sum_Y_real_hold_1_8), + .Y16(out_Y_idft_1_8), + .X17(sum_Y_imag_hold_1_8), + .Y17(), + .X18(sum_Y_real_hold_1_9), + .Y18(out_Y_idft_1_9), + .X19(sum_Y_imag_hold_1_9), + .Y19(), + .X20(sum_Y_real_hold_1_10), + .Y20(out_Y_idft_1_10), + .X21(sum_Y_imag_hold_1_10), + .Y21(), + .X22(sum_Y_real_hold_1_11), + .Y22(out_Y_idft_1_11), + .X23(sum_Y_imag_hold_1_11), + .Y23(), + .X24(sum_Y_real_hold_1_12), + .Y24(out_Y_idft_1_12), + .X25(sum_Y_imag_hold_1_12), + .Y25(), + .X26(sum_Y_real_hold_1_13), + .Y26(out_Y_idft_1_13), + .X27(sum_Y_imag_hold_1_13), + .Y27(), + .X28(sum_Y_real_hold_1_14), + .Y28(out_Y_idft_1_14), + .X29(sum_Y_imag_hold_1_14), + .Y29(), + .X30(sum_Y_real_hold_1_15), + .Y30(out_Y_idft_1_15), + .X31(sum_Y_imag_hold_1_15), + .Y31(), + .next_out(idft_next_out_1) +); + +always @ (posedge clk) begin + if (reset) begin + reg_Y_0_0 <= 0; + reg_Y_0_1 <= 0; + reg_Y_0_2 <= 0; + reg_Y_0_3 <= 0; + reg_Y_0_4 <= 0; + reg_Y_0_5 <= 0; + reg_Y_0_6 <= 0; + reg_Y_0_7 <= 0; + reg_Y_0_8 <= 0; + reg_Y_0_9 <= 0; + reg_Y_0_10 <= 0; + reg_Y_0_11 <= 0; + reg_Y_0_12 <= 0; + reg_Y_0_13 <= 0; + reg_Y_0_14 <= 0; + reg_Y_0_15 <= 0; + reg_Y_1_0 <= 0; + reg_Y_1_1 <= 0; + reg_Y_1_2 <= 0; + reg_Y_1_3 <= 0; + reg_Y_1_4 <= 0; + reg_Y_1_5 <= 0; + reg_Y_1_6 <= 0; + reg_Y_1_7 <= 0; + reg_Y_1_8 <= 0; + reg_Y_1_9 <= 0; + reg_Y_1_10 <= 0; + reg_Y_1_11 <= 0; + reg_Y_1_12 <= 0; + reg_Y_1_13 <= 0; + reg_Y_1_14 <= 0; + reg_Y_1_15 <= 0; + idft_out_valid <= 1'b0; + reg_o_valid <= 1'b0; + end else if (enable) begin + reg_Y_0_0 <= (out_Y_idft_0_0 >>> 4); + reg_Y_0_1 <= (out_Y_idft_0_1 >>> 4); + reg_Y_0_2 <= (out_Y_idft_0_2 >>> 4); + reg_Y_0_3 <= (out_Y_idft_0_3 >>> 4); + reg_Y_0_4 <= (out_Y_idft_0_4 >>> 4); + reg_Y_0_5 <= (out_Y_idft_0_5 >>> 4); + reg_Y_0_6 <= (out_Y_idft_0_6 >>> 4); + reg_Y_0_7 <= (out_Y_idft_0_7 >>> 4); + reg_Y_0_8 <= (out_Y_idft_0_8 >>> 4); + reg_Y_0_9 <= (out_Y_idft_0_9 >>> 4); + reg_Y_0_10 <= (out_Y_idft_0_10 >>> 4); + reg_Y_0_11 <= (out_Y_idft_0_11 >>> 4); + reg_Y_0_12 <= (out_Y_idft_0_12 >>> 4); + reg_Y_0_13 <= (out_Y_idft_0_13 >>> 4); + reg_Y_0_14 <= (out_Y_idft_0_14 >>> 4); + reg_Y_0_15 <= (out_Y_idft_0_15 >>> 4); + reg_Y_1_0 <= (out_Y_idft_1_0 >>> 4); + reg_Y_1_1 <= (out_Y_idft_1_1 >>> 4); + reg_Y_1_2 <= (out_Y_idft_1_2 >>> 4); + reg_Y_1_3 <= (out_Y_idft_1_3 >>> 4); + reg_Y_1_4 <= (out_Y_idft_1_4 >>> 4); + reg_Y_1_5 <= (out_Y_idft_1_5 >>> 4); + reg_Y_1_6 <= (out_Y_idft_1_6 >>> 4); + reg_Y_1_7 <= (out_Y_idft_1_7 >>> 4); + reg_Y_1_8 <= (out_Y_idft_1_8 >>> 4); + reg_Y_1_9 <= (out_Y_idft_1_9 >>> 4); + reg_Y_1_10 <= (out_Y_idft_1_10 >>> 4); + reg_Y_1_11 <= (out_Y_idft_1_11 >>> 4); + reg_Y_1_12 <= (out_Y_idft_1_12 >>> 4); + reg_Y_1_13 <= (out_Y_idft_1_13 >>> 4); + reg_Y_1_14 <= (out_Y_idft_1_14 >>> 4); + reg_Y_1_15 <= (out_Y_idft_1_15 >>> 4); + idft_out_valid <= idft_next_out_0; + reg_o_valid <= idft_out_valid; + end +end + +assign o_valid = enable & reg_o_valid; +assign o_ready = matrix_vec_mult_ready; +assign o_Y_0_0 = reg_Y_0_0; +assign o_Y_0_1 = reg_Y_0_1; +assign o_Y_0_2 = reg_Y_0_2; +assign o_Y_0_3 = reg_Y_0_3; +assign o_Y_0_4 = reg_Y_0_4; +assign o_Y_0_5 = reg_Y_0_5; +assign o_Y_0_6 = reg_Y_0_6; +assign o_Y_0_7 = reg_Y_0_7; +assign o_Y_0_8 = reg_Y_0_8; +assign o_Y_0_9 = reg_Y_0_9; +assign o_Y_0_10 = reg_Y_0_10; +assign o_Y_0_11 = reg_Y_0_11; +assign o_Y_0_12 = reg_Y_0_12; +assign o_Y_0_13 = reg_Y_0_13; +assign o_Y_0_14 = reg_Y_0_14; +assign o_Y_0_15 = reg_Y_0_15; +assign o_Y_1_0 = reg_Y_1_0; +assign o_Y_1_1 = reg_Y_1_1; +assign o_Y_1_2 = reg_Y_1_2; +assign o_Y_1_3 = reg_Y_1_3; +assign o_Y_1_4 = reg_Y_1_4; +assign o_Y_1_5 = reg_Y_1_5; +assign o_Y_1_6 = reg_Y_1_6; +assign o_Y_1_7 = reg_Y_1_7; +assign o_Y_1_8 = reg_Y_1_8; +assign o_Y_1_9 = reg_Y_1_9; +assign o_Y_1_10 = reg_Y_1_10; +assign o_Y_1_11 = reg_Y_1_11; +assign o_Y_1_12 = reg_Y_1_12; +assign o_Y_1_13 = reg_Y_1_13; +assign o_Y_1_14 = reg_Y_1_14; +assign o_Y_1_15 = reg_Y_1_15; + +endmodule + +module c_matrix_vec_mult_core_18_10_16_2_1 ( + input clk, + input reset, + input i_ready, + input i_valid, + input [17:0] i_X_0, + input [17:0] i_X_1, + input [17:0] i_X_2, + input [17:0] i_X_3, + input [17:0] i_X_4, + input [17:0] i_X_5, + input [17:0] i_X_6, + input [17:0] i_X_7, + input [17:0] i_X_8, + input [17:0] i_X_9, + input [17:0] i_X_10, + input [17:0] i_X_11, + input [17:0] i_X_12, + input [17:0] i_X_13, + input [17:0] i_X_14, + input [17:0] i_X_15, + input [17:0] i_W_real_0_0, + input [17:0] i_W_imag_0_0, + input [17:0] i_W_real_0_1, + input [17:0] i_W_imag_0_1, + input [17:0] i_W_real_0_2, + input [17:0] i_W_imag_0_2, + input [17:0] i_W_real_0_3, + input [17:0] i_W_imag_0_3, + input [17:0] i_W_real_0_4, + input [17:0] i_W_imag_0_4, + input [17:0] i_W_real_0_5, + input [17:0] i_W_imag_0_5, + input [17:0] i_W_real_0_6, + input [17:0] i_W_imag_0_6, + input [17:0] i_W_real_0_7, + input [17:0] i_W_imag_0_7, + input [17:0] i_W_real_0_8, + input [17:0] i_W_imag_0_8, + input [17:0] i_W_real_1_0, + input [17:0] i_W_imag_1_0, + input [17:0] i_W_real_1_1, + input [17:0] i_W_imag_1_1, + input [17:0] i_W_real_1_2, + input [17:0] i_W_imag_1_2, + input [17:0] i_W_real_1_3, + input [17:0] i_W_imag_1_3, + input [17:0] i_W_real_1_4, + input [17:0] i_W_imag_1_4, + input [17:0] i_W_real_1_5, + input [17:0] i_W_imag_1_5, + input [17:0] i_W_real_1_6, + input [17:0] i_W_imag_1_6, + input [17:0] i_W_real_1_7, + input [17:0] i_W_imag_1_7, + input [17:0] i_W_real_1_8, + input [17:0] i_W_imag_1_8, + output [17:0] o_Y_real_0_0, + output [17:0] o_Y_imag_0_0, + output [17:0] o_Y_real_0_1, + output [17:0] o_Y_imag_0_1, + output [17:0] o_Y_real_0_2, + output [17:0] o_Y_imag_0_2, + output [17:0] o_Y_real_0_3, + output [17:0] o_Y_imag_0_3, + output [17:0] o_Y_real_0_4, + output [17:0] o_Y_imag_0_4, + output [17:0] o_Y_real_0_5, + output [17:0] o_Y_imag_0_5, + output [17:0] o_Y_real_0_6, + output [17:0] o_Y_imag_0_6, + output [17:0] o_Y_real_0_7, + output [17:0] o_Y_imag_0_7, + output [17:0] o_Y_real_0_8, + output [17:0] o_Y_imag_0_8, + output [17:0] o_Y_real_0_9, + output [17:0] o_Y_imag_0_9, + output [17:0] o_Y_real_0_10, + output [17:0] o_Y_imag_0_10, + output [17:0] o_Y_real_0_11, + output [17:0] o_Y_imag_0_11, + output [17:0] o_Y_real_0_12, + output [17:0] o_Y_imag_0_12, + output [17:0] o_Y_real_0_13, + output [17:0] o_Y_imag_0_13, + output [17:0] o_Y_real_0_14, + output [17:0] o_Y_imag_0_14, + output [17:0] o_Y_real_0_15, + output [17:0] o_Y_imag_0_15, + output [17:0] o_Y_real_1_0, + output [17:0] o_Y_imag_1_0, + output [17:0] o_Y_real_1_1, + output [17:0] o_Y_imag_1_1, + output [17:0] o_Y_real_1_2, + output [17:0] o_Y_imag_1_2, + output [17:0] o_Y_real_1_3, + output [17:0] o_Y_imag_1_3, + output [17:0] o_Y_real_1_4, + output [17:0] o_Y_imag_1_4, + output [17:0] o_Y_real_1_5, + output [17:0] o_Y_imag_1_5, + output [17:0] o_Y_real_1_6, + output [17:0] o_Y_imag_1_6, + output [17:0] o_Y_real_1_7, + output [17:0] o_Y_imag_1_7, + output [17:0] o_Y_real_1_8, + output [17:0] o_Y_imag_1_8, + output [17:0] o_Y_real_1_9, + output [17:0] o_Y_imag_1_9, + output [17:0] o_Y_real_1_10, + output [17:0] o_Y_imag_1_10, + output [17:0] o_Y_real_1_11, + output [17:0] o_Y_imag_1_11, + output [17:0] o_Y_real_1_12, + output [17:0] o_Y_imag_1_12, + output [17:0] o_Y_real_1_13, + output [17:0] o_Y_imag_1_13, + output [17:0] o_Y_real_1_14, + output [17:0] o_Y_imag_1_14, + output [17:0] o_Y_real_1_15, + output [17:0] o_Y_imag_1_15, + output o_ready, + output o_valid +); + +// Enable whenever reciever is ready +wire enable; +assign enable = i_ready; +// Register the inputs +reg [17:0] reg_X_0; +reg [17:0] reg_X_2_0; +reg [17:0] reg_X_1; +reg [17:0] reg_X_2_1; +reg [17:0] reg_X_2; +reg [17:0] reg_X_2_2; +reg [17:0] reg_X_3; +reg [17:0] reg_X_2_3; +reg [17:0] reg_X_4; +reg [17:0] reg_X_2_4; +reg [17:0] reg_X_5; +reg [17:0] reg_X_2_5; +reg [17:0] reg_X_6; +reg [17:0] reg_X_2_6; +reg [17:0] reg_X_7; +reg [17:0] reg_X_2_7; +reg [17:0] reg_X_8; +reg [17:0] reg_X_2_8; +reg [17:0] reg_X_9; +reg [17:0] reg_X_2_9; +reg [17:0] reg_X_10; +reg [17:0] reg_X_2_10; +reg [17:0] reg_X_11; +reg [17:0] reg_X_2_11; +reg [17:0] reg_X_12; +reg [17:0] reg_X_2_12; +reg [17:0] reg_X_13; +reg [17:0] reg_X_2_13; +reg [17:0] reg_X_14; +reg [17:0] reg_X_2_14; +reg [17:0] reg_X_15; +reg [17:0] reg_X_2_15; +reg [17:0] reg_W_real_0_0; +reg [17:0] reg_W_imag_0_0; +reg [17:0] reg_W_real_0_1; +reg [17:0] reg_W_imag_0_1; +reg [17:0] reg_W_real_0_2; +reg [17:0] reg_W_imag_0_2; +reg [17:0] reg_W_real_0_3; +reg [17:0] reg_W_imag_0_3; +reg [17:0] reg_W_real_0_4; +reg [17:0] reg_W_imag_0_4; +reg [17:0] reg_W_real_0_5; +reg [17:0] reg_W_imag_0_5; +reg [17:0] reg_W_real_0_6; +reg [17:0] reg_W_imag_0_6; +reg [17:0] reg_W_real_0_7; +reg [17:0] reg_W_imag_0_7; +reg [17:0] reg_W_real_0_8; +reg [17:0] reg_W_imag_0_8; +reg [17:0] reg_W_real_1_0; +reg [17:0] reg_W_imag_1_0; +reg [17:0] reg_W_real_1_1; +reg [17:0] reg_W_imag_1_1; +reg [17:0] reg_W_real_1_2; +reg [17:0] reg_W_imag_1_2; +reg [17:0] reg_W_real_1_3; +reg [17:0] reg_W_imag_1_3; +reg [17:0] reg_W_real_1_4; +reg [17:0] reg_W_imag_1_4; +reg [17:0] reg_W_real_1_5; +reg [17:0] reg_W_imag_1_5; +reg [17:0] reg_W_real_1_6; +reg [17:0] reg_W_imag_1_6; +reg [17:0] reg_W_real_1_7; +reg [17:0] reg_W_imag_1_7; +reg [17:0] reg_W_real_1_8; +reg [17:0] reg_W_imag_1_8; +reg reg_i_valid; + +// Register the outputs +reg [17:0] reg_Y_real_0_0; +reg [17:0] reg_Y_imag_0_0; +reg [17:0] reg_Y_real_0_1; +reg [17:0] reg_Y_imag_0_1; +reg [17:0] reg_Y_real_0_2; +reg [17:0] reg_Y_imag_0_2; +reg [17:0] reg_Y_real_0_3; +reg [17:0] reg_Y_imag_0_3; +reg [17:0] reg_Y_real_0_4; +reg [17:0] reg_Y_imag_0_4; +reg [17:0] reg_Y_real_0_5; +reg [17:0] reg_Y_imag_0_5; +reg [17:0] reg_Y_real_0_6; +reg [17:0] reg_Y_imag_0_6; +reg [17:0] reg_Y_real_0_7; +reg [17:0] reg_Y_imag_0_7; +reg [17:0] reg_Y_real_0_8; +reg [17:0] reg_Y_imag_0_8; +reg [17:0] reg_Y_real_0_9; +reg [17:0] reg_Y_imag_0_9; +reg [17:0] reg_Y_real_0_10; +reg [17:0] reg_Y_imag_0_10; +reg [17:0] reg_Y_real_0_11; +reg [17:0] reg_Y_imag_0_11; +reg [17:0] reg_Y_real_0_12; +reg [17:0] reg_Y_imag_0_12; +reg [17:0] reg_Y_real_0_13; +reg [17:0] reg_Y_imag_0_13; +reg [17:0] reg_Y_real_0_14; +reg [17:0] reg_Y_imag_0_14; +reg [17:0] reg_Y_real_0_15; +reg [17:0] reg_Y_imag_0_15; +reg [17:0] reg_Y_real_1_0; +reg [17:0] reg_Y_imag_1_0; +reg [17:0] reg_Y_real_1_1; +reg [17:0] reg_Y_imag_1_1; +reg [17:0] reg_Y_real_1_2; +reg [17:0] reg_Y_imag_1_2; +reg [17:0] reg_Y_real_1_3; +reg [17:0] reg_Y_imag_1_3; +reg [17:0] reg_Y_real_1_4; +reg [17:0] reg_Y_imag_1_4; +reg [17:0] reg_Y_real_1_5; +reg [17:0] reg_Y_imag_1_5; +reg [17:0] reg_Y_real_1_6; +reg [17:0] reg_Y_imag_1_6; +reg [17:0] reg_Y_real_1_7; +reg [17:0] reg_Y_imag_1_7; +reg [17:0] reg_Y_real_1_8; +reg [17:0] reg_Y_imag_1_8; +reg [17:0] reg_Y_real_1_9; +reg [17:0] reg_Y_imag_1_9; +reg [17:0] reg_Y_real_1_10; +reg [17:0] reg_Y_imag_1_10; +reg [17:0] reg_Y_real_1_11; +reg [17:0] reg_Y_imag_1_11; +reg [17:0] reg_Y_real_1_12; +reg [17:0] reg_Y_imag_1_12; +reg [17:0] reg_Y_real_1_13; +reg [17:0] reg_Y_imag_1_13; +reg [17:0] reg_Y_real_1_14; +reg [17:0] reg_Y_imag_1_14; +reg [17:0] reg_Y_real_1_15; +reg [17:0] reg_Y_imag_1_15; +reg reg_o_valid; + +// Inter-connections +reg fft_valid; +reg reg_o_ready; +wire o_fft_next; +wire mult_X_real_W_real_valid_0; +wire mult_X_imag_W_real_valid_0; +wire mult_X_real_W_imag_valid_0; +wire mult_X_imag_W_imag_valid_0; +wire sub_y_real_valid_0; +wire add_y_imag_valid_0; +wire mult_X_real_W_real_valid_1; +wire mult_X_imag_W_real_valid_1; +wire mult_X_real_W_imag_valid_1; +wire mult_X_imag_W_imag_valid_1; +wire sub_y_real_valid_1; +wire add_y_imag_valid_1; + +wire [17:0] W_real_wires_0_0; +wire [17:0] W_imag_wires_0_0; +wire [17:0] W_real_holder_0_0; +wire [17:0] W_imag_holder_0_0; +wire [17:0] o_mult_X_real_W_real_0_0; +wire [17:0] o_mult_X_imag_W_real_0_0; +wire [17:0] o_mult_X_real_W_imag_0_0; +wire [17:0] o_mult_X_imag_W_imag_0_0; +wire [17:0] o_sub_y_real_0_0; +wire [17:0] o_add_y_imag_0_0; +wire [17:0] W_real_wires_0_1; +wire [17:0] W_imag_wires_0_1; +wire [17:0] W_real_holder_0_1; +wire [17:0] W_imag_holder_0_1; +wire [17:0] o_mult_X_real_W_real_0_1; +wire [17:0] o_mult_X_imag_W_real_0_1; +wire [17:0] o_mult_X_real_W_imag_0_1; +wire [17:0] o_mult_X_imag_W_imag_0_1; +wire [17:0] o_sub_y_real_0_1; +wire [17:0] o_add_y_imag_0_1; +wire [17:0] W_real_wires_0_2; +wire [17:0] W_imag_wires_0_2; +wire [17:0] W_real_holder_0_2; +wire [17:0] W_imag_holder_0_2; +wire [17:0] o_mult_X_real_W_real_0_2; +wire [17:0] o_mult_X_imag_W_real_0_2; +wire [17:0] o_mult_X_real_W_imag_0_2; +wire [17:0] o_mult_X_imag_W_imag_0_2; +wire [17:0] o_sub_y_real_0_2; +wire [17:0] o_add_y_imag_0_2; +wire [17:0] W_real_wires_0_3; +wire [17:0] W_imag_wires_0_3; +wire [17:0] W_real_holder_0_3; +wire [17:0] W_imag_holder_0_3; +wire [17:0] o_mult_X_real_W_real_0_3; +wire [17:0] o_mult_X_imag_W_real_0_3; +wire [17:0] o_mult_X_real_W_imag_0_3; +wire [17:0] o_mult_X_imag_W_imag_0_3; +wire [17:0] o_sub_y_real_0_3; +wire [17:0] o_add_y_imag_0_3; +wire [17:0] W_real_wires_0_4; +wire [17:0] W_imag_wires_0_4; +wire [17:0] W_real_holder_0_4; +wire [17:0] W_imag_holder_0_4; +wire [17:0] o_mult_X_real_W_real_0_4; +wire [17:0] o_mult_X_imag_W_real_0_4; +wire [17:0] o_mult_X_real_W_imag_0_4; +wire [17:0] o_mult_X_imag_W_imag_0_4; +wire [17:0] o_sub_y_real_0_4; +wire [17:0] o_add_y_imag_0_4; +wire [17:0] W_real_wires_0_5; +wire [17:0] W_imag_wires_0_5; +wire [17:0] W_real_holder_0_5; +wire [17:0] W_imag_holder_0_5; +wire [17:0] o_mult_X_real_W_real_0_5; +wire [17:0] o_mult_X_imag_W_real_0_5; +wire [17:0] o_mult_X_real_W_imag_0_5; +wire [17:0] o_mult_X_imag_W_imag_0_5; +wire [17:0] o_sub_y_real_0_5; +wire [17:0] o_add_y_imag_0_5; +wire [17:0] W_real_wires_0_6; +wire [17:0] W_imag_wires_0_6; +wire [17:0] W_real_holder_0_6; +wire [17:0] W_imag_holder_0_6; +wire [17:0] o_mult_X_real_W_real_0_6; +wire [17:0] o_mult_X_imag_W_real_0_6; +wire [17:0] o_mult_X_real_W_imag_0_6; +wire [17:0] o_mult_X_imag_W_imag_0_6; +wire [17:0] o_sub_y_real_0_6; +wire [17:0] o_add_y_imag_0_6; +wire [17:0] W_real_wires_0_7; +wire [17:0] W_imag_wires_0_7; +wire [17:0] W_real_holder_0_7; +wire [17:0] W_imag_holder_0_7; +wire [17:0] o_mult_X_real_W_real_0_7; +wire [17:0] o_mult_X_imag_W_real_0_7; +wire [17:0] o_mult_X_real_W_imag_0_7; +wire [17:0] o_mult_X_imag_W_imag_0_7; +wire [17:0] o_sub_y_real_0_7; +wire [17:0] o_add_y_imag_0_7; +wire [17:0] W_real_wires_0_8; +wire [17:0] W_imag_wires_0_8; +wire [17:0] W_real_holder_0_8; +wire [17:0] W_imag_holder_0_8; +wire [17:0] o_mult_X_real_W_real_0_8; +wire [17:0] o_mult_X_imag_W_real_0_8; +wire [17:0] o_mult_X_real_W_imag_0_8; +wire [17:0] o_mult_X_imag_W_imag_0_8; +wire [17:0] o_sub_y_real_0_8; +wire [17:0] o_add_y_imag_0_8; +wire [17:0] W_real_wires_1_0; +wire [17:0] W_imag_wires_1_0; +wire [17:0] W_real_holder_1_0; +wire [17:0] W_imag_holder_1_0; +wire [17:0] o_mult_X_real_W_real_1_0; +wire [17:0] o_mult_X_imag_W_real_1_0; +wire [17:0] o_mult_X_real_W_imag_1_0; +wire [17:0] o_mult_X_imag_W_imag_1_0; +wire [17:0] o_sub_y_real_1_0; +wire [17:0] o_add_y_imag_1_0; +wire [17:0] W_real_wires_1_1; +wire [17:0] W_imag_wires_1_1; +wire [17:0] W_real_holder_1_1; +wire [17:0] W_imag_holder_1_1; +wire [17:0] o_mult_X_real_W_real_1_1; +wire [17:0] o_mult_X_imag_W_real_1_1; +wire [17:0] o_mult_X_real_W_imag_1_1; +wire [17:0] o_mult_X_imag_W_imag_1_1; +wire [17:0] o_sub_y_real_1_1; +wire [17:0] o_add_y_imag_1_1; +wire [17:0] W_real_wires_1_2; +wire [17:0] W_imag_wires_1_2; +wire [17:0] W_real_holder_1_2; +wire [17:0] W_imag_holder_1_2; +wire [17:0] o_mult_X_real_W_real_1_2; +wire [17:0] o_mult_X_imag_W_real_1_2; +wire [17:0] o_mult_X_real_W_imag_1_2; +wire [17:0] o_mult_X_imag_W_imag_1_2; +wire [17:0] o_sub_y_real_1_2; +wire [17:0] o_add_y_imag_1_2; +wire [17:0] W_real_wires_1_3; +wire [17:0] W_imag_wires_1_3; +wire [17:0] W_real_holder_1_3; +wire [17:0] W_imag_holder_1_3; +wire [17:0] o_mult_X_real_W_real_1_3; +wire [17:0] o_mult_X_imag_W_real_1_3; +wire [17:0] o_mult_X_real_W_imag_1_3; +wire [17:0] o_mult_X_imag_W_imag_1_3; +wire [17:0] o_sub_y_real_1_3; +wire [17:0] o_add_y_imag_1_3; +wire [17:0] W_real_wires_1_4; +wire [17:0] W_imag_wires_1_4; +wire [17:0] W_real_holder_1_4; +wire [17:0] W_imag_holder_1_4; +wire [17:0] o_mult_X_real_W_real_1_4; +wire [17:0] o_mult_X_imag_W_real_1_4; +wire [17:0] o_mult_X_real_W_imag_1_4; +wire [17:0] o_mult_X_imag_W_imag_1_4; +wire [17:0] o_sub_y_real_1_4; +wire [17:0] o_add_y_imag_1_4; +wire [17:0] W_real_wires_1_5; +wire [17:0] W_imag_wires_1_5; +wire [17:0] W_real_holder_1_5; +wire [17:0] W_imag_holder_1_5; +wire [17:0] o_mult_X_real_W_real_1_5; +wire [17:0] o_mult_X_imag_W_real_1_5; +wire [17:0] o_mult_X_real_W_imag_1_5; +wire [17:0] o_mult_X_imag_W_imag_1_5; +wire [17:0] o_sub_y_real_1_5; +wire [17:0] o_add_y_imag_1_5; +wire [17:0] W_real_wires_1_6; +wire [17:0] W_imag_wires_1_6; +wire [17:0] W_real_holder_1_6; +wire [17:0] W_imag_holder_1_6; +wire [17:0] o_mult_X_real_W_real_1_6; +wire [17:0] o_mult_X_imag_W_real_1_6; +wire [17:0] o_mult_X_real_W_imag_1_6; +wire [17:0] o_mult_X_imag_W_imag_1_6; +wire [17:0] o_sub_y_real_1_6; +wire [17:0] o_add_y_imag_1_6; +wire [17:0] W_real_wires_1_7; +wire [17:0] W_imag_wires_1_7; +wire [17:0] W_real_holder_1_7; +wire [17:0] W_imag_holder_1_7; +wire [17:0] o_mult_X_real_W_real_1_7; +wire [17:0] o_mult_X_imag_W_real_1_7; +wire [17:0] o_mult_X_real_W_imag_1_7; +wire [17:0] o_mult_X_imag_W_imag_1_7; +wire [17:0] o_sub_y_real_1_7; +wire [17:0] o_add_y_imag_1_7; +wire [17:0] W_real_wires_1_8; +wire [17:0] W_imag_wires_1_8; +wire [17:0] W_real_holder_1_8; +wire [17:0] W_imag_holder_1_8; +wire [17:0] o_mult_X_real_W_real_1_8; +wire [17:0] o_mult_X_imag_W_real_1_8; +wire [17:0] o_mult_X_real_W_imag_1_8; +wire [17:0] o_mult_X_imag_W_imag_1_8; +wire [17:0] o_sub_y_real_1_8; +wire [17:0] o_add_y_imag_1_8; +wire [17:0] o_fft_X_real_0; +wire [17:0] o_fft_X_imag_0; +wire [17:0] o_fft_X_real_1; +wire [17:0] o_fft_X_imag_1; +wire [17:0] o_fft_X_real_2; +wire [17:0] o_fft_X_imag_2; +wire [17:0] o_fft_X_real_3; +wire [17:0] o_fft_X_imag_3; +wire [17:0] o_fft_X_real_4; +wire [17:0] o_fft_X_imag_4; +wire [17:0] o_fft_X_real_5; +wire [17:0] o_fft_X_imag_5; +wire [17:0] o_fft_X_real_6; +wire [17:0] o_fft_X_imag_6; +wire [17:0] o_fft_X_real_7; +wire [17:0] o_fft_X_imag_7; +wire [17:0] o_fft_X_real_8; +wire [17:0] o_fft_X_imag_8; +wire [17:0] o_fft_X_real_9; +wire [17:0] o_fft_X_imag_9; +wire [17:0] o_fft_X_real_10; +wire [17:0] o_fft_X_imag_10; +wire [17:0] o_fft_X_real_11; +wire [17:0] o_fft_X_imag_11; +wire [17:0] o_fft_X_real_12; +wire [17:0] o_fft_X_imag_12; +wire [17:0] o_fft_X_real_13; +wire [17:0] o_fft_X_imag_13; +wire [17:0] o_fft_X_real_14; +wire [17:0] o_fft_X_imag_14; +wire [17:0] o_fft_X_real_15; +wire [17:0] o_fft_X_imag_15; + +// Hold weights value until X_FFT finishes +assign W_real_wires_0_0 = reg_W_real_0_0; +assign W_imag_wires_0_0 = reg_W_imag_0_0; +assign W_real_wires_0_1 = reg_W_real_0_1; +assign W_imag_wires_0_1 = reg_W_imag_0_1; +assign W_real_wires_0_2 = reg_W_real_0_2; +assign W_imag_wires_0_2 = reg_W_imag_0_2; +assign W_real_wires_0_3 = reg_W_real_0_3; +assign W_imag_wires_0_3 = reg_W_imag_0_3; +assign W_real_wires_0_4 = reg_W_real_0_4; +assign W_imag_wires_0_4 = reg_W_imag_0_4; +assign W_real_wires_0_5 = reg_W_real_0_5; +assign W_imag_wires_0_5 = reg_W_imag_0_5; +assign W_real_wires_0_6 = reg_W_real_0_6; +assign W_imag_wires_0_6 = reg_W_imag_0_6; +assign W_real_wires_0_7 = reg_W_real_0_7; +assign W_imag_wires_0_7 = reg_W_imag_0_7; +assign W_real_wires_0_8 = reg_W_real_0_8; +assign W_imag_wires_0_8 = reg_W_imag_0_8; +assign W_real_wires_1_0 = reg_W_real_1_0; +assign W_imag_wires_1_0 = reg_W_imag_1_0; +assign W_real_wires_1_1 = reg_W_real_1_1; +assign W_imag_wires_1_1 = reg_W_imag_1_1; +assign W_real_wires_1_2 = reg_W_real_1_2; +assign W_imag_wires_1_2 = reg_W_imag_1_2; +assign W_real_wires_1_3 = reg_W_real_1_3; +assign W_imag_wires_1_3 = reg_W_imag_1_3; +assign W_real_wires_1_4 = reg_W_real_1_4; +assign W_imag_wires_1_4 = reg_W_imag_1_4; +assign W_real_wires_1_5 = reg_W_real_1_5; +assign W_imag_wires_1_5 = reg_W_imag_1_5; +assign W_real_wires_1_6 = reg_W_real_1_6; +assign W_imag_wires_1_6 = reg_W_imag_1_6; +assign W_real_wires_1_7 = reg_W_real_1_7; +assign W_imag_wires_1_7 = reg_W_imag_1_7; +assign W_real_wires_1_8 = reg_W_real_1_8; +assign W_imag_wires_1_8 = reg_W_imag_1_8; + +shift_register_group_18_910 shift_register_group_18_910_inst_0_real ( + .clk(clk), + .enable(enable), + .in_0(W_real_wires_0_0), + .out_0(W_real_holder_0_0), + .in_1(W_real_wires_0_1), + .out_1(W_real_holder_0_1), + .in_2(W_real_wires_0_2), + .out_2(W_real_holder_0_2), + .in_3(W_real_wires_0_3), + .out_3(W_real_holder_0_3), + .in_4(W_real_wires_0_4), + .out_4(W_real_holder_0_4), + .in_5(W_real_wires_0_5), + .out_5(W_real_holder_0_5), + .in_6(W_real_wires_0_6), + .out_6(W_real_holder_0_6), + .in_7(W_real_wires_0_7), + .out_7(W_real_holder_0_7), + .in_8(W_real_wires_0_8), + .out_8(W_real_holder_0_8), + .reset(reset) +); + +shift_register_group_18_910 shift_register_group_18_910_inst_0_imag ( + .clk(clk), + .enable(enable), + .in_0(W_imag_wires_0_0), + .out_0(W_imag_holder_0_0), + .in_1(W_imag_wires_0_1), + .out_1(W_imag_holder_0_1), + .in_2(W_imag_wires_0_2), + .out_2(W_imag_holder_0_2), + .in_3(W_imag_wires_0_3), + .out_3(W_imag_holder_0_3), + .in_4(W_imag_wires_0_4), + .out_4(W_imag_holder_0_4), + .in_5(W_imag_wires_0_5), + .out_5(W_imag_holder_0_5), + .in_6(W_imag_wires_0_6), + .out_6(W_imag_holder_0_6), + .in_7(W_imag_wires_0_7), + .out_7(W_imag_holder_0_7), + .in_8(W_imag_wires_0_8), + .out_8(W_imag_holder_0_8), + .reset(reset) +); + +shift_register_group_18_910 shift_register_group_18_910_inst_1_real ( + .clk(clk), + .enable(enable), + .in_0(W_real_wires_1_0), + .out_0(W_real_holder_1_0), + .in_1(W_real_wires_1_1), + .out_1(W_real_holder_1_1), + .in_2(W_real_wires_1_2), + .out_2(W_real_holder_1_2), + .in_3(W_real_wires_1_3), + .out_3(W_real_holder_1_3), + .in_4(W_real_wires_1_4), + .out_4(W_real_holder_1_4), + .in_5(W_real_wires_1_5), + .out_5(W_real_holder_1_5), + .in_6(W_real_wires_1_6), + .out_6(W_real_holder_1_6), + .in_7(W_real_wires_1_7), + .out_7(W_real_holder_1_7), + .in_8(W_real_wires_1_8), + .out_8(W_real_holder_1_8), + .reset(reset) +); + +shift_register_group_18_910 shift_register_group_18_910_inst_1_imag ( + .clk(clk), + .enable(enable), + .in_0(W_imag_wires_1_0), + .out_0(W_imag_holder_1_0), + .in_1(W_imag_wires_1_1), + .out_1(W_imag_holder_1_1), + .in_2(W_imag_wires_1_2), + .out_2(W_imag_holder_1_2), + .in_3(W_imag_wires_1_3), + .out_3(W_imag_holder_1_3), + .in_4(W_imag_wires_1_4), + .out_4(W_imag_holder_1_4), + .in_5(W_imag_wires_1_5), + .out_5(W_imag_holder_1_5), + .in_6(W_imag_wires_1_6), + .out_6(W_imag_holder_1_6), + .in_7(W_imag_wires_1_7), + .out_7(W_imag_holder_1_7), + .in_8(W_imag_wires_1_8), + .out_8(W_imag_holder_1_8), + .reset(reset) +); + +dft_16_top_18 dft_16_top_18_inst_koqqnhvdwe ( + .clk(clk), + .reset(reset), + .next(reg_i_valid), + .X0(reg_X_2_0), + .Y0(o_fft_X_real_0), + .X1(18'd0), + .Y1(o_fft_X_imag_0), + .X2(reg_X_2_1), + .Y2(o_fft_X_real_1), + .X3(18'd0), + .Y3(o_fft_X_imag_1), + .X4(reg_X_2_2), + .Y4(o_fft_X_real_2), + .X5(18'd0), + .Y5(o_fft_X_imag_2), + .X6(reg_X_2_3), + .Y6(o_fft_X_real_3), + .X7(18'd0), + .Y7(o_fft_X_imag_3), + .X8(reg_X_2_4), + .Y8(o_fft_X_real_4), + .X9(18'd0), + .Y9(o_fft_X_imag_4), + .X10(reg_X_2_5), + .Y10(o_fft_X_real_5), + .X11(18'd0), + .Y11(o_fft_X_imag_5), + .X12(reg_X_2_6), + .Y12(o_fft_X_real_6), + .X13(18'd0), + .Y13(o_fft_X_imag_6), + .X14(reg_X_2_7), + .Y14(o_fft_X_real_7), + .X15(18'd0), + .Y15(o_fft_X_imag_7), + .X16(reg_X_2_8), + .Y16(o_fft_X_real_8), + .X17(18'd0), + .Y17(o_fft_X_imag_8), + .X18(reg_X_2_9), + .Y18(o_fft_X_real_9), + .X19(18'd0), + .Y19(o_fft_X_imag_9), + .X20(reg_X_2_10), + .Y20(o_fft_X_real_10), + .X21(18'd0), + .Y21(o_fft_X_imag_10), + .X22(reg_X_2_11), + .Y22(o_fft_X_real_11), + .X23(18'd0), + .Y23(o_fft_X_imag_11), + .X24(reg_X_2_12), + .Y24(o_fft_X_real_12), + .X25(18'd0), + .Y25(o_fft_X_imag_12), + .X26(reg_X_2_13), + .Y26(o_fft_X_real_13), + .X27(18'd0), + .Y27(o_fft_X_imag_13), + .X28(reg_X_2_14), + .Y28(o_fft_X_real_14), + .X29(18'd0), + .Y29(o_fft_X_imag_14), + .X30(reg_X_2_15), + .Y30(o_fft_X_real_15), + .X31(18'd0), + .Y31(o_fft_X_imag_15), + .next_out(o_fft_next) +); +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_0_real_real ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(W_real_holder_0_0), + .i_B_0(o_fft_X_real_0), + .o_C_0(o_mult_X_real_W_real_0_0), + .i_A_1(W_real_holder_0_1), + .i_B_1(o_fft_X_real_1), + .o_C_1(o_mult_X_real_W_real_0_1), + .i_A_2(W_real_holder_0_2), + .i_B_2(o_fft_X_real_2), + .o_C_2(o_mult_X_real_W_real_0_2), + .i_A_3(W_real_holder_0_3), + .i_B_3(o_fft_X_real_3), + .o_C_3(o_mult_X_real_W_real_0_3), + .i_A_4(W_real_holder_0_4), + .i_B_4(o_fft_X_real_4), + .o_C_4(o_mult_X_real_W_real_0_4), + .i_A_5(W_real_holder_0_5), + .i_B_5(o_fft_X_real_5), + .o_C_5(o_mult_X_real_W_real_0_5), + .i_A_6(W_real_holder_0_6), + .i_B_6(o_fft_X_real_6), + .o_C_6(o_mult_X_real_W_real_0_6), + .i_A_7(W_real_holder_0_7), + .i_B_7(o_fft_X_real_7), + .o_C_7(o_mult_X_real_W_real_0_7), + .i_A_8(W_real_holder_0_8), + .i_B_8(o_fft_X_real_8), + .o_C_8(o_mult_X_real_W_real_0_8), + .o_valid(mult_X_real_W_real_valid_0), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_0_real_imag ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(W_imag_holder_0_0), + .i_B_0(o_fft_X_real_0), + .o_C_0(o_mult_X_real_W_imag_0_0), + .i_A_1(W_imag_holder_0_1), + .i_B_1(o_fft_X_real_1), + .o_C_1(o_mult_X_real_W_imag_0_1), + .i_A_2(W_imag_holder_0_2), + .i_B_2(o_fft_X_real_2), + .o_C_2(o_mult_X_real_W_imag_0_2), + .i_A_3(W_imag_holder_0_3), + .i_B_3(o_fft_X_real_3), + .o_C_3(o_mult_X_real_W_imag_0_3), + .i_A_4(W_imag_holder_0_4), + .i_B_4(o_fft_X_real_4), + .o_C_4(o_mult_X_real_W_imag_0_4), + .i_A_5(W_imag_holder_0_5), + .i_B_5(o_fft_X_real_5), + .o_C_5(o_mult_X_real_W_imag_0_5), + .i_A_6(W_imag_holder_0_6), + .i_B_6(o_fft_X_real_6), + .o_C_6(o_mult_X_real_W_imag_0_6), + .i_A_7(W_imag_holder_0_7), + .i_B_7(o_fft_X_real_7), + .o_C_7(o_mult_X_real_W_imag_0_7), + .i_A_8(W_imag_holder_0_8), + .i_B_8(o_fft_X_real_8), + .o_C_8(o_mult_X_real_W_imag_0_8), + .o_valid(mult_X_real_W_imag_valid_0), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_0_imag_real ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(o_fft_X_imag_0), + .i_B_0(W_real_holder_0_0), + .o_C_0(o_mult_X_imag_W_real_0_0), + .i_A_1(o_fft_X_imag_1), + .i_B_1(W_real_holder_0_1), + .o_C_1(o_mult_X_imag_W_real_0_1), + .i_A_2(o_fft_X_imag_2), + .i_B_2(W_real_holder_0_2), + .o_C_2(o_mult_X_imag_W_real_0_2), + .i_A_3(o_fft_X_imag_3), + .i_B_3(W_real_holder_0_3), + .o_C_3(o_mult_X_imag_W_real_0_3), + .i_A_4(o_fft_X_imag_4), + .i_B_4(W_real_holder_0_4), + .o_C_4(o_mult_X_imag_W_real_0_4), + .i_A_5(o_fft_X_imag_5), + .i_B_5(W_real_holder_0_5), + .o_C_5(o_mult_X_imag_W_real_0_5), + .i_A_6(o_fft_X_imag_6), + .i_B_6(W_real_holder_0_6), + .o_C_6(o_mult_X_imag_W_real_0_6), + .i_A_7(o_fft_X_imag_7), + .i_B_7(W_real_holder_0_7), + .o_C_7(o_mult_X_imag_W_real_0_7), + .i_A_8(o_fft_X_imag_8), + .i_B_8(W_real_holder_0_8), + .o_C_8(o_mult_X_imag_W_real_0_8), + .o_valid(mult_X_imag_W_real_valid_0), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_0_imag_imag ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(o_fft_X_imag_0), + .i_B_0(W_imag_holder_0_0), + .o_C_0(o_mult_X_imag_W_imag_0_0), + .i_A_1(o_fft_X_imag_1), + .i_B_1(W_imag_holder_0_1), + .o_C_1(o_mult_X_imag_W_imag_0_1), + .i_A_2(o_fft_X_imag_2), + .i_B_2(W_imag_holder_0_2), + .o_C_2(o_mult_X_imag_W_imag_0_2), + .i_A_3(o_fft_X_imag_3), + .i_B_3(W_imag_holder_0_3), + .o_C_3(o_mult_X_imag_W_imag_0_3), + .i_A_4(o_fft_X_imag_4), + .i_B_4(W_imag_holder_0_4), + .o_C_4(o_mult_X_imag_W_imag_0_4), + .i_A_5(o_fft_X_imag_5), + .i_B_5(W_imag_holder_0_5), + .o_C_5(o_mult_X_imag_W_imag_0_5), + .i_A_6(o_fft_X_imag_6), + .i_B_6(W_imag_holder_0_6), + .o_C_6(o_mult_X_imag_W_imag_0_6), + .i_A_7(o_fft_X_imag_7), + .i_B_7(W_imag_holder_0_7), + .o_C_7(o_mult_X_imag_W_imag_0_7), + .i_A_8(o_fft_X_imag_8), + .i_B_8(W_imag_holder_0_8), + .o_C_8(o_mult_X_imag_W_imag_0_8), + .o_valid(mult_X_imag_W_imag_valid_0), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_1_real_real ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(W_real_holder_1_0), + .i_B_0(o_fft_X_real_0), + .o_C_0(o_mult_X_real_W_real_1_0), + .i_A_1(W_real_holder_1_1), + .i_B_1(o_fft_X_real_1), + .o_C_1(o_mult_X_real_W_real_1_1), + .i_A_2(W_real_holder_1_2), + .i_B_2(o_fft_X_real_2), + .o_C_2(o_mult_X_real_W_real_1_2), + .i_A_3(W_real_holder_1_3), + .i_B_3(o_fft_X_real_3), + .o_C_3(o_mult_X_real_W_real_1_3), + .i_A_4(W_real_holder_1_4), + .i_B_4(o_fft_X_real_4), + .o_C_4(o_mult_X_real_W_real_1_4), + .i_A_5(W_real_holder_1_5), + .i_B_5(o_fft_X_real_5), + .o_C_5(o_mult_X_real_W_real_1_5), + .i_A_6(W_real_holder_1_6), + .i_B_6(o_fft_X_real_6), + .o_C_6(o_mult_X_real_W_real_1_6), + .i_A_7(W_real_holder_1_7), + .i_B_7(o_fft_X_real_7), + .o_C_7(o_mult_X_real_W_real_1_7), + .i_A_8(W_real_holder_1_8), + .i_B_8(o_fft_X_real_8), + .o_C_8(o_mult_X_real_W_real_1_8), + .o_valid(mult_X_real_W_real_valid_1), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_1_real_imag ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(W_imag_holder_1_0), + .i_B_0(o_fft_X_real_0), + .o_C_0(o_mult_X_real_W_imag_1_0), + .i_A_1(W_imag_holder_1_1), + .i_B_1(o_fft_X_real_1), + .o_C_1(o_mult_X_real_W_imag_1_1), + .i_A_2(W_imag_holder_1_2), + .i_B_2(o_fft_X_real_2), + .o_C_2(o_mult_X_real_W_imag_1_2), + .i_A_3(W_imag_holder_1_3), + .i_B_3(o_fft_X_real_3), + .o_C_3(o_mult_X_real_W_imag_1_3), + .i_A_4(W_imag_holder_1_4), + .i_B_4(o_fft_X_real_4), + .o_C_4(o_mult_X_real_W_imag_1_4), + .i_A_5(W_imag_holder_1_5), + .i_B_5(o_fft_X_real_5), + .o_C_5(o_mult_X_real_W_imag_1_5), + .i_A_6(W_imag_holder_1_6), + .i_B_6(o_fft_X_real_6), + .o_C_6(o_mult_X_real_W_imag_1_6), + .i_A_7(W_imag_holder_1_7), + .i_B_7(o_fft_X_real_7), + .o_C_7(o_mult_X_real_W_imag_1_7), + .i_A_8(W_imag_holder_1_8), + .i_B_8(o_fft_X_real_8), + .o_C_8(o_mult_X_real_W_imag_1_8), + .o_valid(mult_X_real_W_imag_valid_1), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_1_imag_real ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(o_fft_X_imag_0), + .i_B_0(W_real_holder_1_0), + .o_C_0(o_mult_X_imag_W_real_1_0), + .i_A_1(o_fft_X_imag_1), + .i_B_1(W_real_holder_1_1), + .o_C_1(o_mult_X_imag_W_real_1_1), + .i_A_2(o_fft_X_imag_2), + .i_B_2(W_real_holder_1_2), + .o_C_2(o_mult_X_imag_W_real_1_2), + .i_A_3(o_fft_X_imag_3), + .i_B_3(W_real_holder_1_3), + .o_C_3(o_mult_X_imag_W_real_1_3), + .i_A_4(o_fft_X_imag_4), + .i_B_4(W_real_holder_1_4), + .o_C_4(o_mult_X_imag_W_real_1_4), + .i_A_5(o_fft_X_imag_5), + .i_B_5(W_real_holder_1_5), + .o_C_5(o_mult_X_imag_W_real_1_5), + .i_A_6(o_fft_X_imag_6), + .i_B_6(W_real_holder_1_6), + .o_C_6(o_mult_X_imag_W_real_1_6), + .i_A_7(o_fft_X_imag_7), + .i_B_7(W_real_holder_1_7), + .o_C_7(o_mult_X_imag_W_real_1_7), + .i_A_8(o_fft_X_imag_8), + .i_B_8(W_real_holder_1_8), + .o_C_8(o_mult_X_imag_W_real_1_8), + .o_valid(mult_X_imag_W_real_valid_1), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_1_imag_imag ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(o_fft_X_imag_0), + .i_B_0(W_imag_holder_1_0), + .o_C_0(o_mult_X_imag_W_imag_1_0), + .i_A_1(o_fft_X_imag_1), + .i_B_1(W_imag_holder_1_1), + .o_C_1(o_mult_X_imag_W_imag_1_1), + .i_A_2(o_fft_X_imag_2), + .i_B_2(W_imag_holder_1_2), + .o_C_2(o_mult_X_imag_W_imag_1_2), + .i_A_3(o_fft_X_imag_3), + .i_B_3(W_imag_holder_1_3), + .o_C_3(o_mult_X_imag_W_imag_1_3), + .i_A_4(o_fft_X_imag_4), + .i_B_4(W_imag_holder_1_4), + .o_C_4(o_mult_X_imag_W_imag_1_4), + .i_A_5(o_fft_X_imag_5), + .i_B_5(W_imag_holder_1_5), + .o_C_5(o_mult_X_imag_W_imag_1_5), + .i_A_6(o_fft_X_imag_6), + .i_B_6(W_imag_holder_1_6), + .o_C_6(o_mult_X_imag_W_imag_1_6), + .i_A_7(o_fft_X_imag_7), + .i_B_7(W_imag_holder_1_7), + .o_C_7(o_mult_X_imag_W_imag_1_7), + .i_A_8(o_fft_X_imag_8), + .i_B_8(W_imag_holder_1_8), + .o_C_8(o_mult_X_imag_W_imag_1_8), + .o_valid(mult_X_imag_W_imag_valid_1), + .o_ready() +); + +wire sub_core_valid_0; +assign sub_core_valid_0 = mult_X_real_W_real_valid_0 & mult_X_imag_W_imag_valid_0; + +elementwise_sub_core_18_18_9 elementwise_sub_core_18_18_9_inst_0 ( + .clk(clk), + .reset(reset), + .i_valid(sub_core_valid_0), + .i_ready(enable), + .i_A_0(o_mult_X_real_W_real_0_0), + .i_B_0(o_mult_X_imag_W_imag_0_0), + .o_C_0(o_sub_y_real_0_0), + .i_A_1(o_mult_X_real_W_real_0_1), + .i_B_1(o_mult_X_imag_W_imag_0_1), + .o_C_1(o_sub_y_real_0_1), + .i_A_2(o_mult_X_real_W_real_0_2), + .i_B_2(o_mult_X_imag_W_imag_0_2), + .o_C_2(o_sub_y_real_0_2), + .i_A_3(o_mult_X_real_W_real_0_3), + .i_B_3(o_mult_X_imag_W_imag_0_3), + .o_C_3(o_sub_y_real_0_3), + .i_A_4(o_mult_X_real_W_real_0_4), + .i_B_4(o_mult_X_imag_W_imag_0_4), + .o_C_4(o_sub_y_real_0_4), + .i_A_5(o_mult_X_real_W_real_0_5), + .i_B_5(o_mult_X_imag_W_imag_0_5), + .o_C_5(o_sub_y_real_0_5), + .i_A_6(o_mult_X_real_W_real_0_6), + .i_B_6(o_mult_X_imag_W_imag_0_6), + .o_C_6(o_sub_y_real_0_6), + .i_A_7(o_mult_X_real_W_real_0_7), + .i_B_7(o_mult_X_imag_W_imag_0_7), + .o_C_7(o_sub_y_real_0_7), + .i_A_8(o_mult_X_real_W_real_0_8), + .i_B_8(o_mult_X_imag_W_imag_0_8), + .o_C_8(o_sub_y_real_0_8), + .o_valid(sub_y_real_valid_0), + .o_ready() +); + +wire sub_core_valid_1; +assign sub_core_valid_1 = mult_X_real_W_real_valid_1 & mult_X_imag_W_imag_valid_1; + +elementwise_sub_core_18_18_9 elementwise_sub_core_18_18_9_inst_1 ( + .clk(clk), + .reset(reset), + .i_valid(sub_core_valid_1), + .i_ready(enable), + .i_A_0(o_mult_X_real_W_real_1_0), + .i_B_0(o_mult_X_imag_W_imag_1_0), + .o_C_0(o_sub_y_real_1_0), + .i_A_1(o_mult_X_real_W_real_1_1), + .i_B_1(o_mult_X_imag_W_imag_1_1), + .o_C_1(o_sub_y_real_1_1), + .i_A_2(o_mult_X_real_W_real_1_2), + .i_B_2(o_mult_X_imag_W_imag_1_2), + .o_C_2(o_sub_y_real_1_2), + .i_A_3(o_mult_X_real_W_real_1_3), + .i_B_3(o_mult_X_imag_W_imag_1_3), + .o_C_3(o_sub_y_real_1_3), + .i_A_4(o_mult_X_real_W_real_1_4), + .i_B_4(o_mult_X_imag_W_imag_1_4), + .o_C_4(o_sub_y_real_1_4), + .i_A_5(o_mult_X_real_W_real_1_5), + .i_B_5(o_mult_X_imag_W_imag_1_5), + .o_C_5(o_sub_y_real_1_5), + .i_A_6(o_mult_X_real_W_real_1_6), + .i_B_6(o_mult_X_imag_W_imag_1_6), + .o_C_6(o_sub_y_real_1_6), + .i_A_7(o_mult_X_real_W_real_1_7), + .i_B_7(o_mult_X_imag_W_imag_1_7), + .o_C_7(o_sub_y_real_1_7), + .i_A_8(o_mult_X_real_W_real_1_8), + .i_B_8(o_mult_X_imag_W_imag_1_8), + .o_C_8(o_sub_y_real_1_8), + .o_valid(sub_y_real_valid_1), + .o_ready() +); + +wire add_core_valid_0; +assign add_core_valid_0 = mult_X_real_W_imag_valid_0 & mult_X_imag_W_real_valid_0; + +elementwise_add_core_18_18_9 elementwise_add_core_18_18_9_inst_0 ( + .clk(clk), + .reset(reset), + .i_valid(add_core_valid_0), + .i_ready(enable), + .i_A_0(o_mult_X_real_W_imag_0_0), + .i_B_0(o_mult_X_imag_W_real_0_0), + .o_C_0(o_add_y_imag_0_0), + .i_A_1(o_mult_X_real_W_imag_0_1), + .i_B_1(o_mult_X_imag_W_real_0_1), + .o_C_1(o_add_y_imag_0_1), + .i_A_2(o_mult_X_real_W_imag_0_2), + .i_B_2(o_mult_X_imag_W_real_0_2), + .o_C_2(o_add_y_imag_0_2), + .i_A_3(o_mult_X_real_W_imag_0_3), + .i_B_3(o_mult_X_imag_W_real_0_3), + .o_C_3(o_add_y_imag_0_3), + .i_A_4(o_mult_X_real_W_imag_0_4), + .i_B_4(o_mult_X_imag_W_real_0_4), + .o_C_4(o_add_y_imag_0_4), + .i_A_5(o_mult_X_real_W_imag_0_5), + .i_B_5(o_mult_X_imag_W_real_0_5), + .o_C_5(o_add_y_imag_0_5), + .i_A_6(o_mult_X_real_W_imag_0_6), + .i_B_6(o_mult_X_imag_W_real_0_6), + .o_C_6(o_add_y_imag_0_6), + .i_A_7(o_mult_X_real_W_imag_0_7), + .i_B_7(o_mult_X_imag_W_real_0_7), + .o_C_7(o_add_y_imag_0_7), + .i_A_8(o_mult_X_real_W_imag_0_8), + .i_B_8(o_mult_X_imag_W_real_0_8), + .o_C_8(o_add_y_imag_0_8), + .o_valid(add_y_imag_valid_0), + .o_ready() +); + +wire add_core_valid_1; +assign add_core_valid_1 = mult_X_real_W_imag_valid_1 & mult_X_imag_W_real_valid_1; + +elementwise_add_core_18_18_9 elementwise_add_core_18_18_9_inst_1 ( + .clk(clk), + .reset(reset), + .i_valid(add_core_valid_1), + .i_ready(enable), + .i_A_0(o_mult_X_real_W_imag_1_0), + .i_B_0(o_mult_X_imag_W_real_1_0), + .o_C_0(o_add_y_imag_1_0), + .i_A_1(o_mult_X_real_W_imag_1_1), + .i_B_1(o_mult_X_imag_W_real_1_1), + .o_C_1(o_add_y_imag_1_1), + .i_A_2(o_mult_X_real_W_imag_1_2), + .i_B_2(o_mult_X_imag_W_real_1_2), + .o_C_2(o_add_y_imag_1_2), + .i_A_3(o_mult_X_real_W_imag_1_3), + .i_B_3(o_mult_X_imag_W_real_1_3), + .o_C_3(o_add_y_imag_1_3), + .i_A_4(o_mult_X_real_W_imag_1_4), + .i_B_4(o_mult_X_imag_W_real_1_4), + .o_C_4(o_add_y_imag_1_4), + .i_A_5(o_mult_X_real_W_imag_1_5), + .i_B_5(o_mult_X_imag_W_real_1_5), + .o_C_5(o_add_y_imag_1_5), + .i_A_6(o_mult_X_real_W_imag_1_6), + .i_B_6(o_mult_X_imag_W_real_1_6), + .o_C_6(o_add_y_imag_1_6), + .i_A_7(o_mult_X_real_W_imag_1_7), + .i_B_7(o_mult_X_imag_W_real_1_7), + .o_C_7(o_add_y_imag_1_7), + .i_A_8(o_mult_X_real_W_imag_1_8), + .i_B_8(o_mult_X_imag_W_real_1_8), + .o_C_8(o_add_y_imag_1_8), + .o_valid(add_y_imag_valid_1), + .o_ready() +); + +always @ (posedge clk) begin + if (reset) begin + reg_i_valid <= 1'b0; + fft_valid <= 1'b0; + reg_o_valid <= 1'b0; + reg_o_ready <= 1'b0; + reg_X_0 <= 0; + reg_X_2_0 <= 0; + reg_X_1 <= 0; + reg_X_2_1 <= 0; + reg_X_2 <= 0; + reg_X_2_2 <= 0; + reg_X_3 <= 0; + reg_X_2_3 <= 0; + reg_X_4 <= 0; + reg_X_2_4 <= 0; + reg_X_5 <= 0; + reg_X_2_5 <= 0; + reg_X_6 <= 0; + reg_X_2_6 <= 0; + reg_X_7 <= 0; + reg_X_2_7 <= 0; + reg_X_8 <= 0; + reg_X_2_8 <= 0; + reg_X_9 <= 0; + reg_X_2_9 <= 0; + reg_X_10 <= 0; + reg_X_2_10 <= 0; + reg_X_11 <= 0; + reg_X_2_11 <= 0; + reg_X_12 <= 0; + reg_X_2_12 <= 0; + reg_X_13 <= 0; + reg_X_2_13 <= 0; + reg_X_14 <= 0; + reg_X_2_14 <= 0; + reg_X_15 <= 0; + reg_X_2_15 <= 0; + reg_W_real_0_0 <= 0; + reg_W_imag_0_0 <= 0; + reg_W_real_0_1 <= 0; + reg_W_imag_0_1 <= 0; + reg_W_real_0_2 <= 0; + reg_W_imag_0_2 <= 0; + reg_W_real_0_3 <= 0; + reg_W_imag_0_3 <= 0; + reg_W_real_0_4 <= 0; + reg_W_imag_0_4 <= 0; + reg_W_real_0_5 <= 0; + reg_W_imag_0_5 <= 0; + reg_W_real_0_6 <= 0; + reg_W_imag_0_6 <= 0; + reg_W_real_0_7 <= 0; + reg_W_imag_0_7 <= 0; + reg_W_real_0_8 <= 0; + reg_W_imag_0_8 <= 0; + reg_W_real_1_0 <= 0; + reg_W_imag_1_0 <= 0; + reg_W_real_1_1 <= 0; + reg_W_imag_1_1 <= 0; + reg_W_real_1_2 <= 0; + reg_W_imag_1_2 <= 0; + reg_W_real_1_3 <= 0; + reg_W_imag_1_3 <= 0; + reg_W_real_1_4 <= 0; + reg_W_imag_1_4 <= 0; + reg_W_real_1_5 <= 0; + reg_W_imag_1_5 <= 0; + reg_W_real_1_6 <= 0; + reg_W_imag_1_6 <= 0; + reg_W_real_1_7 <= 0; + reg_W_imag_1_7 <= 0; + reg_W_real_1_8 <= 0; + reg_W_imag_1_8 <= 0; + reg_Y_real_0_0 <= 0; + reg_Y_imag_0_0 <= 0; + reg_Y_real_0_1 <= 0; + reg_Y_imag_0_1 <= 0; + reg_Y_real_0_2 <= 0; + reg_Y_imag_0_2 <= 0; + reg_Y_real_0_3 <= 0; + reg_Y_imag_0_3 <= 0; + reg_Y_real_0_4 <= 0; + reg_Y_imag_0_4 <= 0; + reg_Y_real_0_5 <= 0; + reg_Y_imag_0_5 <= 0; + reg_Y_real_0_6 <= 0; + reg_Y_imag_0_6 <= 0; + reg_Y_real_0_7 <= 0; + reg_Y_imag_0_7 <= 0; + reg_Y_real_0_8 <= 0; + reg_Y_imag_0_8 <= 0; + reg_Y_real_0_9 <= 0; + reg_Y_imag_0_9 <= 0; + reg_Y_real_0_10 <= 0; + reg_Y_imag_0_10 <= 0; + reg_Y_real_0_11 <= 0; + reg_Y_imag_0_11 <= 0; + reg_Y_real_0_12 <= 0; + reg_Y_imag_0_12 <= 0; + reg_Y_real_0_13 <= 0; + reg_Y_imag_0_13 <= 0; + reg_Y_real_0_14 <= 0; + reg_Y_imag_0_14 <= 0; + reg_Y_real_0_15 <= 0; + reg_Y_imag_0_15 <= 0; + reg_Y_real_1_0 <= 0; + reg_Y_imag_1_0 <= 0; + reg_Y_real_1_1 <= 0; + reg_Y_imag_1_1 <= 0; + reg_Y_real_1_2 <= 0; + reg_Y_imag_1_2 <= 0; + reg_Y_real_1_3 <= 0; + reg_Y_imag_1_3 <= 0; + reg_Y_real_1_4 <= 0; + reg_Y_imag_1_4 <= 0; + reg_Y_real_1_5 <= 0; + reg_Y_imag_1_5 <= 0; + reg_Y_real_1_6 <= 0; + reg_Y_imag_1_6 <= 0; + reg_Y_real_1_7 <= 0; + reg_Y_imag_1_7 <= 0; + reg_Y_real_1_8 <= 0; + reg_Y_imag_1_8 <= 0; + reg_Y_real_1_9 <= 0; + reg_Y_imag_1_9 <= 0; + reg_Y_real_1_10 <= 0; + reg_Y_imag_1_10 <= 0; + reg_Y_real_1_11 <= 0; + reg_Y_imag_1_11 <= 0; + reg_Y_real_1_12 <= 0; + reg_Y_imag_1_12 <= 0; + reg_Y_real_1_13 <= 0; + reg_Y_imag_1_13 <= 0; + reg_Y_real_1_14 <= 0; + reg_Y_imag_1_14 <= 0; + reg_Y_real_1_15 <= 0; + reg_Y_imag_1_15 <= 0; + end else if (enable) begin + reg_i_valid <= i_valid; + fft_valid <= o_fft_next; + reg_o_valid <= add_y_imag_valid_0 & sub_y_real_valid_0; + reg_o_ready <= ~i_valid & enable; + reg_X_0 <= i_X_0; + reg_X_2_0 <= reg_X_0; + reg_X_1 <= i_X_1; + reg_X_2_1 <= reg_X_1; + reg_X_2 <= i_X_2; + reg_X_2_2 <= reg_X_2; + reg_X_3 <= i_X_3; + reg_X_2_3 <= reg_X_3; + reg_X_4 <= i_X_4; + reg_X_2_4 <= reg_X_4; + reg_X_5 <= i_X_5; + reg_X_2_5 <= reg_X_5; + reg_X_6 <= i_X_6; + reg_X_2_6 <= reg_X_6; + reg_X_7 <= i_X_7; + reg_X_2_7 <= reg_X_7; + reg_X_8 <= i_X_8; + reg_X_2_8 <= reg_X_8; + reg_X_9 <= i_X_9; + reg_X_2_9 <= reg_X_9; + reg_X_10 <= i_X_10; + reg_X_2_10 <= reg_X_10; + reg_X_11 <= i_X_11; + reg_X_2_11 <= reg_X_11; + reg_X_12 <= i_X_12; + reg_X_2_12 <= reg_X_12; + reg_X_13 <= i_X_13; + reg_X_2_13 <= reg_X_13; + reg_X_14 <= i_X_14; + reg_X_2_14 <= reg_X_14; + reg_X_15 <= i_X_15; + reg_X_2_15 <= reg_X_15; + reg_W_real_0_0 <= i_W_real_0_0; + reg_W_imag_0_0 <= i_W_imag_0_0; + reg_W_real_0_1 <= i_W_real_0_1; + reg_W_imag_0_1 <= i_W_imag_0_1; + reg_W_real_0_2 <= i_W_real_0_2; + reg_W_imag_0_2 <= i_W_imag_0_2; + reg_W_real_0_3 <= i_W_real_0_3; + reg_W_imag_0_3 <= i_W_imag_0_3; + reg_W_real_0_4 <= i_W_real_0_4; + reg_W_imag_0_4 <= i_W_imag_0_4; + reg_W_real_0_5 <= i_W_real_0_5; + reg_W_imag_0_5 <= i_W_imag_0_5; + reg_W_real_0_6 <= i_W_real_0_6; + reg_W_imag_0_6 <= i_W_imag_0_6; + reg_W_real_0_7 <= i_W_real_0_7; + reg_W_imag_0_7 <= i_W_imag_0_7; + reg_W_real_0_8 <= i_W_real_0_8; + reg_W_imag_0_8 <= i_W_imag_0_8; + reg_W_real_1_0 <= i_W_real_1_0; + reg_W_imag_1_0 <= i_W_imag_1_0; + reg_W_real_1_1 <= i_W_real_1_1; + reg_W_imag_1_1 <= i_W_imag_1_1; + reg_W_real_1_2 <= i_W_real_1_2; + reg_W_imag_1_2 <= i_W_imag_1_2; + reg_W_real_1_3 <= i_W_real_1_3; + reg_W_imag_1_3 <= i_W_imag_1_3; + reg_W_real_1_4 <= i_W_real_1_4; + reg_W_imag_1_4 <= i_W_imag_1_4; + reg_W_real_1_5 <= i_W_real_1_5; + reg_W_imag_1_5 <= i_W_imag_1_5; + reg_W_real_1_6 <= i_W_real_1_6; + reg_W_imag_1_6 <= i_W_imag_1_6; + reg_W_real_1_7 <= i_W_real_1_7; + reg_W_imag_1_7 <= i_W_imag_1_7; + reg_W_real_1_8 <= i_W_real_1_8; + reg_W_imag_1_8 <= i_W_imag_1_8; + reg_Y_real_0_0 <= o_sub_y_real_0_0; + reg_Y_imag_0_0 <= o_add_y_imag_0_0; + reg_Y_real_0_1 <= o_sub_y_real_0_1; + reg_Y_imag_0_1 <= o_add_y_imag_0_1; + reg_Y_real_0_2 <= o_sub_y_real_0_2; + reg_Y_imag_0_2 <= o_add_y_imag_0_2; + reg_Y_real_0_3 <= o_sub_y_real_0_3; + reg_Y_imag_0_3 <= o_add_y_imag_0_3; + reg_Y_real_0_4 <= o_sub_y_real_0_4; + reg_Y_imag_0_4 <= o_add_y_imag_0_4; + reg_Y_real_0_5 <= o_sub_y_real_0_5; + reg_Y_imag_0_5 <= o_add_y_imag_0_5; + reg_Y_real_0_6 <= o_sub_y_real_0_6; + reg_Y_imag_0_6 <= o_add_y_imag_0_6; + reg_Y_real_0_7 <= o_sub_y_real_0_7; + reg_Y_imag_0_7 <= o_add_y_imag_0_7; + reg_Y_real_0_8 <= o_sub_y_real_0_8; + reg_Y_imag_0_8 <= o_add_y_imag_0_8; + reg_Y_real_0_9 <= o_sub_y_real_0_7; + reg_Y_imag_0_9 <= -o_add_y_imag_0_7; + reg_Y_real_0_10 <= o_sub_y_real_0_6; + reg_Y_imag_0_10 <= -o_add_y_imag_0_6; + reg_Y_real_0_11 <= o_sub_y_real_0_5; + reg_Y_imag_0_11 <= -o_add_y_imag_0_5; + reg_Y_real_0_12 <= o_sub_y_real_0_4; + reg_Y_imag_0_12 <= -o_add_y_imag_0_4; + reg_Y_real_0_13 <= o_sub_y_real_0_3; + reg_Y_imag_0_13 <= -o_add_y_imag_0_3; + reg_Y_real_0_14 <= o_sub_y_real_0_2; + reg_Y_imag_0_14 <= -o_add_y_imag_0_2; + reg_Y_real_0_15 <= o_sub_y_real_0_1; + reg_Y_imag_0_15 <= -o_add_y_imag_0_1; + reg_Y_real_1_0 <= o_sub_y_real_1_0; + reg_Y_imag_1_0 <= o_add_y_imag_1_0; + reg_Y_real_1_1 <= o_sub_y_real_1_1; + reg_Y_imag_1_1 <= o_add_y_imag_1_1; + reg_Y_real_1_2 <= o_sub_y_real_1_2; + reg_Y_imag_1_2 <= o_add_y_imag_1_2; + reg_Y_real_1_3 <= o_sub_y_real_1_3; + reg_Y_imag_1_3 <= o_add_y_imag_1_3; + reg_Y_real_1_4 <= o_sub_y_real_1_4; + reg_Y_imag_1_4 <= o_add_y_imag_1_4; + reg_Y_real_1_5 <= o_sub_y_real_1_5; + reg_Y_imag_1_5 <= o_add_y_imag_1_5; + reg_Y_real_1_6 <= o_sub_y_real_1_6; + reg_Y_imag_1_6 <= o_add_y_imag_1_6; + reg_Y_real_1_7 <= o_sub_y_real_1_7; + reg_Y_imag_1_7 <= o_add_y_imag_1_7; + reg_Y_real_1_8 <= o_sub_y_real_1_8; + reg_Y_imag_1_8 <= o_add_y_imag_1_8; + reg_Y_real_1_9 <= o_sub_y_real_1_7; + reg_Y_imag_1_9 <= -o_add_y_imag_1_7; + reg_Y_real_1_10 <= o_sub_y_real_1_6; + reg_Y_imag_1_10 <= -o_add_y_imag_1_6; + reg_Y_real_1_11 <= o_sub_y_real_1_5; + reg_Y_imag_1_11 <= -o_add_y_imag_1_5; + reg_Y_real_1_12 <= o_sub_y_real_1_4; + reg_Y_imag_1_12 <= -o_add_y_imag_1_4; + reg_Y_real_1_13 <= o_sub_y_real_1_3; + reg_Y_imag_1_13 <= -o_add_y_imag_1_3; + reg_Y_real_1_14 <= o_sub_y_real_1_2; + reg_Y_imag_1_14 <= -o_add_y_imag_1_2; + reg_Y_real_1_15 <= o_sub_y_real_1_1; + reg_Y_imag_1_15 <= -o_add_y_imag_1_1; + end +end + +assign o_ready = reg_o_ready & i_ready; +assign o_valid = reg_o_valid; +assign o_Y_real_0_0 = reg_Y_real_0_0; +assign o_Y_imag_0_0 = reg_Y_imag_0_0; +assign o_Y_real_0_1 = reg_Y_real_0_1; +assign o_Y_imag_0_1 = reg_Y_imag_0_1; +assign o_Y_real_0_2 = reg_Y_real_0_2; +assign o_Y_imag_0_2 = reg_Y_imag_0_2; +assign o_Y_real_0_3 = reg_Y_real_0_3; +assign o_Y_imag_0_3 = reg_Y_imag_0_3; +assign o_Y_real_0_4 = reg_Y_real_0_4; +assign o_Y_imag_0_4 = reg_Y_imag_0_4; +assign o_Y_real_0_5 = reg_Y_real_0_5; +assign o_Y_imag_0_5 = reg_Y_imag_0_5; +assign o_Y_real_0_6 = reg_Y_real_0_6; +assign o_Y_imag_0_6 = reg_Y_imag_0_6; +assign o_Y_real_0_7 = reg_Y_real_0_7; +assign o_Y_imag_0_7 = reg_Y_imag_0_7; +assign o_Y_real_0_8 = reg_Y_real_0_8; +assign o_Y_imag_0_8 = reg_Y_imag_0_8; +assign o_Y_real_0_9 = reg_Y_real_0_9; +assign o_Y_imag_0_9 = reg_Y_imag_0_9; +assign o_Y_real_0_10 = reg_Y_real_0_10; +assign o_Y_imag_0_10 = reg_Y_imag_0_10; +assign o_Y_real_0_11 = reg_Y_real_0_11; +assign o_Y_imag_0_11 = reg_Y_imag_0_11; +assign o_Y_real_0_12 = reg_Y_real_0_12; +assign o_Y_imag_0_12 = reg_Y_imag_0_12; +assign o_Y_real_0_13 = reg_Y_real_0_13; +assign o_Y_imag_0_13 = reg_Y_imag_0_13; +assign o_Y_real_0_14 = reg_Y_real_0_14; +assign o_Y_imag_0_14 = reg_Y_imag_0_14; +assign o_Y_real_0_15 = reg_Y_real_0_15; +assign o_Y_imag_0_15 = reg_Y_imag_0_15; +assign o_Y_real_1_0 = reg_Y_real_1_0; +assign o_Y_imag_1_0 = reg_Y_imag_1_0; +assign o_Y_real_1_1 = reg_Y_real_1_1; +assign o_Y_imag_1_1 = reg_Y_imag_1_1; +assign o_Y_real_1_2 = reg_Y_real_1_2; +assign o_Y_imag_1_2 = reg_Y_imag_1_2; +assign o_Y_real_1_3 = reg_Y_real_1_3; +assign o_Y_imag_1_3 = reg_Y_imag_1_3; +assign o_Y_real_1_4 = reg_Y_real_1_4; +assign o_Y_imag_1_4 = reg_Y_imag_1_4; +assign o_Y_real_1_5 = reg_Y_real_1_5; +assign o_Y_imag_1_5 = reg_Y_imag_1_5; +assign o_Y_real_1_6 = reg_Y_real_1_6; +assign o_Y_imag_1_6 = reg_Y_imag_1_6; +assign o_Y_real_1_7 = reg_Y_real_1_7; +assign o_Y_imag_1_7 = reg_Y_imag_1_7; +assign o_Y_real_1_8 = reg_Y_real_1_8; +assign o_Y_imag_1_8 = reg_Y_imag_1_8; +assign o_Y_real_1_9 = reg_Y_real_1_9; +assign o_Y_imag_1_9 = reg_Y_imag_1_9; +assign o_Y_real_1_10 = reg_Y_real_1_10; +assign o_Y_imag_1_10 = reg_Y_imag_1_10; +assign o_Y_real_1_11 = reg_Y_real_1_11; +assign o_Y_imag_1_11 = reg_Y_imag_1_11; +assign o_Y_real_1_12 = reg_Y_real_1_12; +assign o_Y_imag_1_12 = reg_Y_imag_1_12; +assign o_Y_real_1_13 = reg_Y_real_1_13; +assign o_Y_imag_1_13 = reg_Y_imag_1_13; +assign o_Y_real_1_14 = reg_Y_real_1_14; +assign o_Y_imag_1_14 = reg_Y_imag_1_14; +assign o_Y_real_1_15 = reg_Y_real_1_15; +assign o_Y_imag_1_15 = reg_Y_imag_1_15; + +endmodule + +module shift_register_group_18_910 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input reset +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +endmodule + +module shift_register_unit_18_10 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +reg [17:0] shift_registers_1; +reg [17:0] shift_registers_2; +reg [17:0] shift_registers_3; +reg [17:0] shift_registers_4; +reg [17:0] shift_registers_5; +reg [17:0] shift_registers_6; +reg [17:0] shift_registers_7; +reg [17:0] shift_registers_8; +reg [17:0] shift_registers_9; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + shift_registers_1 <= 18'd0; + shift_registers_2 <= 18'd0; + shift_registers_3 <= 18'd0; + shift_registers_4 <= 18'd0; + shift_registers_5 <= 18'd0; + shift_registers_6 <= 18'd0; + shift_registers_7 <= 18'd0; + shift_registers_8 <= 18'd0; + shift_registers_9 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + shift_registers_3 <= shift_registers_2; + shift_registers_4 <= shift_registers_3; + shift_registers_5 <= shift_registers_4; + shift_registers_6 <= shift_registers_5; + shift_registers_7 <= shift_registers_6; + shift_registers_8 <= shift_registers_7; + shift_registers_9 <= shift_registers_8; + end +end + +assign out = shift_registers_9; + +endmodule + +module dft_16_top_18 ( + input clk, + input reset, + input next, + input [17:0] X0, + output [17:0] Y0, + input [17:0] X1, + output [17:0] Y1, + input [17:0] X2, + output [17:0] Y2, + input [17:0] X3, + output [17:0] Y3, + input [17:0] X4, + output [17:0] Y4, + input [17:0] X5, + output [17:0] Y5, + input [17:0] X6, + output [17:0] Y6, + input [17:0] X7, + output [17:0] Y7, + input [17:0] X8, + output [17:0] Y8, + input [17:0] X9, + output [17:0] Y9, + input [17:0] X10, + output [17:0] Y10, + input [17:0] X11, + output [17:0] Y11, + input [17:0] X12, + output [17:0] Y12, + input [17:0] X13, + output [17:0] Y13, + input [17:0] X14, + output [17:0] Y14, + input [17:0] X15, + output [17:0] Y15, + input [17:0] X16, + output [17:0] Y16, + input [17:0] X17, + output [17:0] Y17, + input [17:0] X18, + output [17:0] Y18, + input [17:0] X19, + output [17:0] Y19, + input [17:0] X20, + output [17:0] Y20, + input [17:0] X21, + output [17:0] Y21, + input [17:0] X22, + output [17:0] Y22, + input [17:0] X23, + output [17:0] Y23, + input [17:0] X24, + output [17:0] Y24, + input [17:0] X25, + output [17:0] Y25, + input [17:0] X26, + output [17:0] Y26, + input [17:0] X27, + output [17:0] Y27, + input [17:0] X28, + output [17:0] Y28, + input [17:0] X29, + output [17:0] Y29, + input [17:0] X30, + output [17:0] Y30, + input [17:0] X31, + output [17:0] Y31, + output next_out +); + +wire [17:0] t0_0; +wire [17:0] t0_1; +wire [17:0] t0_2; +wire [17:0] t0_3; +wire [17:0] t0_4; +wire [17:0] t0_5; +wire [17:0] t0_6; +wire [17:0] t0_7; +wire [17:0] t0_8; +wire [17:0] t0_9; +wire [17:0] t0_10; +wire [17:0] t0_11; +wire [17:0] t0_12; +wire [17:0] t0_13; +wire [17:0] t0_14; +wire [17:0] t0_15; +wire [17:0] t0_16; +wire [17:0] t0_17; +wire [17:0] t0_18; +wire [17:0] t0_19; +wire [17:0] t0_20; +wire [17:0] t0_21; +wire [17:0] t0_22; +wire [17:0] t0_23; +wire [17:0] t0_24; +wire [17:0] t0_25; +wire [17:0] t0_26; +wire [17:0] t0_27; +wire [17:0] t0_28; +wire [17:0] t0_29; +wire [17:0] t0_30; +wire [17:0] t0_31; +wire next_0; +wire [17:0] t1_0; +wire [17:0] t1_1; +wire [17:0] t1_2; +wire [17:0] t1_3; +wire [17:0] t1_4; +wire [17:0] t1_5; +wire [17:0] t1_6; +wire [17:0] t1_7; +wire [17:0] t1_8; +wire [17:0] t1_9; +wire [17:0] t1_10; +wire [17:0] t1_11; +wire [17:0] t1_12; +wire [17:0] t1_13; +wire [17:0] t1_14; +wire [17:0] t1_15; +wire [17:0] t1_16; +wire [17:0] t1_17; +wire [17:0] t1_18; +wire [17:0] t1_19; +wire [17:0] t1_20; +wire [17:0] t1_21; +wire [17:0] t1_22; +wire [17:0] t1_23; +wire [17:0] t1_24; +wire [17:0] t1_25; +wire [17:0] t1_26; +wire [17:0] t1_27; +wire [17:0] t1_28; +wire [17:0] t1_29; +wire [17:0] t1_30; +wire [17:0] t1_31; +wire next_1; +wire [17:0] t2_0; +wire [17:0] t2_1; +wire [17:0] t2_2; +wire [17:0] t2_3; +wire [17:0] t2_4; +wire [17:0] t2_5; +wire [17:0] t2_6; +wire [17:0] t2_7; +wire [17:0] t2_8; +wire [17:0] t2_9; +wire [17:0] t2_10; +wire [17:0] t2_11; +wire [17:0] t2_12; +wire [17:0] t2_13; +wire [17:0] t2_14; +wire [17:0] t2_15; +wire [17:0] t2_16; +wire [17:0] t2_17; +wire [17:0] t2_18; +wire [17:0] t2_19; +wire [17:0] t2_20; +wire [17:0] t2_21; +wire [17:0] t2_22; +wire [17:0] t2_23; +wire [17:0] t2_24; +wire [17:0] t2_25; +wire [17:0] t2_26; +wire [17:0] t2_27; +wire [17:0] t2_28; +wire [17:0] t2_29; +wire [17:0] t2_30; +wire [17:0] t2_31; +wire next_2; + +assign t0_0 = X0; +assign Y0 = t2_0; +assign t0_1 = X1; +assign Y1 = t2_1; +assign t0_2 = X2; +assign Y2 = t2_2; +assign t0_3 = X3; +assign Y3 = t2_3; +assign t0_4 = X4; +assign Y4 = t2_4; +assign t0_5 = X5; +assign Y5 = t2_5; +assign t0_6 = X6; +assign Y6 = t2_6; +assign t0_7 = X7; +assign Y7 = t2_7; +assign t0_8 = X8; +assign Y8 = t2_8; +assign t0_9 = X9; +assign Y9 = t2_9; +assign t0_10 = X10; +assign Y10 = t2_10; +assign t0_11 = X11; +assign Y11 = t2_11; +assign t0_12 = X12; +assign Y12 = t2_12; +assign t0_13 = X13; +assign Y13 = t2_13; +assign t0_14 = X14; +assign Y14 = t2_14; +assign t0_15 = X15; +assign Y15 = t2_15; +assign t0_16 = X16; +assign Y16 = t2_16; +assign t0_17 = X17; +assign Y17 = t2_17; +assign t0_18 = X18; +assign Y18 = t2_18; +assign t0_19 = X19; +assign Y19 = t2_19; +assign t0_20 = X20; +assign Y20 = t2_20; +assign t0_21 = X21; +assign Y21 = t2_21; +assign t0_22 = X22; +assign Y22 = t2_22; +assign t0_23 = X23; +assign Y23 = t2_23; +assign t0_24 = X24; +assign Y24 = t2_24; +assign t0_25 = X25; +assign Y25 = t2_25; +assign t0_26 = X26; +assign Y26 = t2_26; +assign t0_27 = X27; +assign Y27 = t2_27; +assign t0_28 = X28; +assign Y28 = t2_28; +assign t0_29 = X29; +assign Y29 = t2_29; +assign t0_30 = X30; +assign Y30 = t2_30; +assign t0_31 = X31; +assign Y31 = t2_31; +assign next_0 = next; +assign next_out = next_2; +codeBlock88206_18 codeBlock88206_18_inst_qztoliuzhz ( + .clk(clk), + .reset(reset), + .next_in(next_0), + .X0_in(t0_0), + .Y0(t1_0), + .X1_in(t0_1), + .Y1(t1_1), + .X2_in(t0_2), + .Y2(t1_2), + .X3_in(t0_3), + .Y3(t1_3), + .X4_in(t0_4), + .Y4(t1_4), + .X5_in(t0_5), + .Y5(t1_5), + .X6_in(t0_6), + .Y6(t1_6), + .X7_in(t0_7), + .Y7(t1_7), + .X8_in(t0_8), + .Y8(t1_8), + .X9_in(t0_9), + .Y9(t1_9), + .X10_in(t0_10), + .Y10(t1_10), + .X11_in(t0_11), + .Y11(t1_11), + .X12_in(t0_12), + .Y12(t1_12), + .X13_in(t0_13), + .Y13(t1_13), + .X14_in(t0_14), + .Y14(t1_14), + .X15_in(t0_15), + .Y15(t1_15), + .X16_in(t0_16), + .Y16(t1_16), + .X17_in(t0_17), + .Y17(t1_17), + .X18_in(t0_18), + .Y18(t1_18), + .X19_in(t0_19), + .Y19(t1_19), + .X20_in(t0_20), + .Y20(t1_20), + .X21_in(t0_21), + .Y21(t1_21), + .X22_in(t0_22), + .Y22(t1_22), + .X23_in(t0_23), + .Y23(t1_23), + .X24_in(t0_24), + .Y24(t1_24), + .X25_in(t0_25), + .Y25(t1_25), + .X26_in(t0_26), + .Y26(t1_26), + .X27_in(t0_27), + .Y27(t1_27), + .X28_in(t0_28), + .Y28(t1_28), + .X29_in(t0_29), + .Y29(t1_29), + .X30_in(t0_30), + .Y30(t1_30), + .X31_in(t0_31), + .Y31(t1_31), + .next_out(next_1) +); + +codeBlock89324_18 codeBlock89324_18_inst_pzfnbinkcf ( + .clk(clk), + .reset(reset), + .next_in(next_1), + .X0_in(t1_0), + .Y0(t2_0), + .X1_in(t1_1), + .Y1(t2_1), + .X2_in(t1_2), + .Y2(t2_2), + .X3_in(t1_3), + .Y3(t2_3), + .X4_in(t1_4), + .Y4(t2_4), + .X5_in(t1_5), + .Y5(t2_5), + .X6_in(t1_6), + .Y6(t2_6), + .X7_in(t1_7), + .Y7(t2_7), + .X8_in(t1_8), + .Y8(t2_8), + .X9_in(t1_9), + .Y9(t2_9), + .X10_in(t1_10), + .Y10(t2_10), + .X11_in(t1_11), + .Y11(t2_11), + .X12_in(t1_12), + .Y12(t2_12), + .X13_in(t1_13), + .Y13(t2_13), + .X14_in(t1_14), + .Y14(t2_14), + .X15_in(t1_15), + .Y15(t2_15), + .X16_in(t1_16), + .Y16(t2_16), + .X17_in(t1_17), + .Y17(t2_17), + .X18_in(t1_18), + .Y18(t2_18), + .X19_in(t1_19), + .Y19(t2_19), + .X20_in(t1_20), + .Y20(t2_20), + .X21_in(t1_21), + .Y21(t2_21), + .X22_in(t1_22), + .Y22(t2_22), + .X23_in(t1_23), + .Y23(t2_23), + .X24_in(t1_24), + .Y24(t2_24), + .X25_in(t1_25), + .Y25(t2_25), + .X26_in(t1_26), + .Y26(t2_26), + .X27_in(t1_27), + .Y27(t2_27), + .X28_in(t1_28), + .Y28(t2_28), + .X29_in(t1_29), + .Y29(t2_29), + .X30_in(t1_30), + .Y30(t2_30), + .X31_in(t1_31), + .Y31(t2_31), + .next_out(next_2) +); + +endmodule + +module codeBlock88206_18 ( + input clk, + input reset, + input next_in, + input [17:0] X0_in, + output [17:0] Y0, + input [17:0] X1_in, + output [17:0] Y1, + input [17:0] X2_in, + output [17:0] Y2, + input [17:0] X3_in, + output [17:0] Y3, + input [17:0] X4_in, + output [17:0] Y4, + input [17:0] X5_in, + output [17:0] Y5, + input [17:0] X6_in, + output [17:0] Y6, + input [17:0] X7_in, + output [17:0] Y7, + input [17:0] X8_in, + output [17:0] Y8, + input [17:0] X9_in, + output [17:0] Y9, + input [17:0] X10_in, + output [17:0] Y10, + input [17:0] X11_in, + output [17:0] Y11, + input [17:0] X12_in, + output [17:0] Y12, + input [17:0] X13_in, + output [17:0] Y13, + input [17:0] X14_in, + output [17:0] Y14, + input [17:0] X15_in, + output [17:0] Y15, + input [17:0] X16_in, + output [17:0] Y16, + input [17:0] X17_in, + output [17:0] Y17, + input [17:0] X18_in, + output [17:0] Y18, + input [17:0] X19_in, + output [17:0] Y19, + input [17:0] X20_in, + output [17:0] Y20, + input [17:0] X21_in, + output [17:0] Y21, + input [17:0] X22_in, + output [17:0] Y22, + input [17:0] X23_in, + output [17:0] Y23, + input [17:0] X24_in, + output [17:0] Y24, + input [17:0] X25_in, + output [17:0] Y25, + input [17:0] X26_in, + output [17:0] Y26, + input [17:0] X27_in, + output [17:0] Y27, + input [17:0] X28_in, + output [17:0] Y28, + input [17:0] X29_in, + output [17:0] Y29, + input [17:0] X30_in, + output [17:0] Y30, + input [17:0] X31_in, + output [17:0] Y31, + output next_out +); + +reg next; +reg [17:0] X0; +reg [17:0] X1; +reg [17:0] X2; +reg [17:0] X3; +reg [17:0] X4; +reg [17:0] X5; +reg [17:0] X6; +reg [17:0] X7; +reg [17:0] X8; +reg [17:0] X9; +reg [17:0] X10; +reg [17:0] X11; +reg [17:0] X12; +reg [17:0] X13; +reg [17:0] X14; +reg [17:0] X15; +reg [17:0] X16; +reg [17:0] X17; +reg [17:0] X18; +reg [17:0] X19; +reg [17:0] X20; +reg [17:0] X21; +reg [17:0] X22; +reg [17:0] X23; +reg [17:0] X24; +reg [17:0] X25; +reg [17:0] X26; +reg [17:0] X27; +reg [17:0] X28; +reg [17:0] X29; +reg [17:0] X30; +reg [17:0] X31; +shiftRegFIFO_5_1 shiftRegFIFO_5_1_inst_rwqvyiplic ( + .X(next), + .Y(next_out), + .reset(reset), + .clk(clk) +); +wire [17:0] a249; + wire [17:0] a250; + wire [17:0] a251; + wire [17:0] a252; + wire [17:0] a257; + wire [17:0] a258; + wire [17:0] a259; + wire [17:0] a260; + wire [17:0] a265; + wire [17:0] a266; + wire [17:0] a267; + wire [17:0] a268; + wire [17:0] a273; + wire [17:0] a274; + wire [17:0] a275; + wire [17:0] a276; + wire [17:0] a281; + wire [17:0] a282; + wire [17:0] a283; + wire [17:0] a284; + wire [17:0] a289; + wire [17:0] a290; + wire [17:0] a291; + wire [17:0] a292; + wire [17:0] a297; + wire [17:0] a298; + wire [17:0] a299; + wire [17:0] a300; + wire [17:0] a305; + wire [17:0] a306; + wire [17:0] a307; + wire [17:0] a308; + wire [17:0] t914; + wire [17:0] t915; + wire [17:0] t916; + wire [17:0] t917; + wire [17:0] t918; + wire [17:0] t919; + wire [17:0] t920; + wire [17:0] t921; + wire [17:0] t930; + wire [17:0] t931; + wire [17:0] t932; + wire [17:0] t933; + wire [17:0] t934; + wire [17:0] t935; + wire [17:0] t936; + wire [17:0] t937; + wire [17:0] t952; + wire [17:0] t953; + wire [17:0] t954; + wire [17:0] t955; + wire [17:0] t956; + wire [17:0] t957; + wire [17:0] t958; + wire [17:0] t959; + wire [17:0] t972; + wire [17:0] t973; + wire [17:0] t974; + wire [17:0] t975; + wire [17:0] t976; + wire [17:0] t977; + wire [17:0] t978; + wire [17:0] t979; + wire [17:0] t922; + wire [17:0] t923; + wire [17:0] t924; + wire [17:0] t925; + wire [17:0] t926; + wire [17:0] t927; + wire [17:0] t928; + wire [17:0] t929; + wire [17:0] t938; + wire [17:0] t939; + wire [17:0] t940; + wire [17:0] t941; + wire [17:0] t944; + wire [17:0] t945; + wire [17:0] t946; + wire [17:0] t947; + wire [17:0] t960; + wire [17:0] t961; + wire [17:0] t962; + wire [17:0] t963; + wire [17:0] t964; + wire [17:0] t965; + wire [17:0] t966; + wire [17:0] t967; + wire [17:0] t980; + wire [17:0] t981; + wire [17:0] t982; + wire [17:0] t983; + wire [17:0] t986; + wire [17:0] t987; + wire [17:0] t988; + wire [17:0] t989; + reg [17:0] tm24; + reg [17:0] tm27; + reg [17:0] tm30; + reg [17:0] tm33; + reg [17:0] tm36; + reg [17:0] tm39; + reg [17:0] tm42; + reg [17:0] tm45; + reg [17:0] tm48; + reg [17:0] tm51; + reg [17:0] tm54; + reg [17:0] tm57; + reg [17:0] tm60; + reg [17:0] tm63; + reg [17:0] tm66; + reg [17:0] tm69; + wire [17:0] a225; + wire [17:0] a226; + wire [17:0] a227; + wire [17:0] a228; + wire [17:0] a229; + wire [17:0] a230; + wire [17:0] a231; + wire [17:0] a232; + wire [17:0] a233; + wire [17:0] a234; + wire [17:0] a235; + wire [17:0] a236; + wire [17:0] a237; + wire [17:0] a238; + wire [17:0] a239; + wire [17:0] a240; + wire [17:0] a241; + wire [17:0] a242; + wire [17:0] a243; + wire [17:0] a244; + wire [17:0] a245; + wire [17:0] a246; + wire [17:0] a247; + wire [17:0] a248; + reg [17:0] tm25; + reg [17:0] tm28; + reg [17:0] tm31; + reg [17:0] tm34; + reg [17:0] tm37; + reg [17:0] tm40; + reg [17:0] tm43; + reg [17:0] tm46; + reg [17:0] tm49; + reg [17:0] tm52; + reg [17:0] tm55; + reg [17:0] tm58; + reg [17:0] tm61; + reg [17:0] tm64; + reg [17:0] tm67; + reg [17:0] tm70; + wire [17:0] t942; + wire [17:0] t943; + wire [17:0] t948; + wire [17:0] t949; + wire [17:0] t950; + wire [17:0] t951; + wire [17:0] t968; + wire [17:0] t969; + wire [17:0] t970; + wire [17:0] t971; + wire [17:0] t984; + wire [17:0] t985; + wire [17:0] t990; + wire [17:0] t991; + wire [17:0] t992; + wire [17:0] t993; + reg [17:0] tm26; + reg [17:0] tm29; + reg [17:0] tm32; + reg [17:0] tm35; + reg [17:0] tm38; + reg [17:0] tm41; + reg [17:0] tm44; + reg [17:0] tm47; + reg [17:0] tm50; + reg [17:0] tm53; + reg [17:0] tm56; + reg [17:0] tm59; + reg [17:0] tm62; + reg [17:0] tm65; + reg [17:0] tm68; + reg [17:0] tm71; + +wire [17:0] tm0; +assign tm0 = (18'hb505 >> (18-18)); +wire [17:0] tm2; +assign tm2 = (18'hec83 >> (18-18)); +wire [17:0] tm3; +assign tm3 = (18'h61f8 >> (18-18)); + +assign a249 = X0; + assign a250 = X16; + assign a251 = X1; + assign a252 = X17; + assign a257 = X8; + assign a258 = X24; + assign a259 = X9; + assign a260 = X25; + assign a265 = X2; + assign a266 = X18; + assign a267 = X3; + assign a268 = X19; + assign a273 = X10; + assign a274 = X26; + assign a275 = X11; + assign a276 = X27; + assign a281 = X4; + assign a282 = X20; + assign a283 = X5; + assign a284 = X21; + assign a289 = X12; + assign a290 = X28; + assign a291 = X13; + assign a292 = X29; + assign a297 = X6; + assign a298 = X22; + assign a299 = X7; + assign a300 = X23; + assign a305 = X14; + assign a306 = X30; + assign a307 = X15; + assign a308 = X31; + assign Y0 = tm26; + assign Y1 = tm29; + assign Y4 = tm32; + assign Y5 = tm35; + assign Y2 = tm38; + assign Y3 = tm41; + assign Y6 = tm44; + assign Y7 = tm47; + assign Y8 = tm50; + assign Y9 = tm53; + assign Y12 = t942; + assign Y13 = t943; + assign Y10 = t948; + assign Y11 = t949; + assign Y14 = t950; + assign Y15 = t951; + assign Y16 = tm56; + assign Y17 = tm59; + assign Y20 = tm62; + assign Y21 = tm65; + assign Y18 = t968; + assign Y19 = t969; + assign Y22 = t970; + assign Y23 = (~(t971)+1'b1); + assign Y24 = tm68; + assign Y25 = tm71; + assign Y28 = t984; + assign Y29 = (~(t985)+1'b1); + assign Y26 = t990; + assign Y27 = t991; + assign Y30 = (~(t992)+1'b1); + assign Y31 = t993; + +addfxp_18_1 add88218(.a(a249), .b(a250), .clk(clk), .q(t914)); + addfxp_18_1 add88233(.a(a251), .b(a252), .clk(clk), .q(t915)); + subfxp_18_1 sub88248(.a(a249), .b(a250), .clk(clk), .q(t916)); + subfxp_18_1 sub88263(.a(a251), .b(a252), .clk(clk), .q(t917)); + addfxp_18_1 add88278(.a(a257), .b(a258), .clk(clk), .q(t918)); + addfxp_18_1 add88293(.a(a259), .b(a260), .clk(clk), .q(t919)); + subfxp_18_1 sub88308(.a(a257), .b(a258), .clk(clk), .q(t920)); + subfxp_18_1 sub88323(.a(a259), .b(a260), .clk(clk), .q(t921)); + addfxp_18_1 add88426(.a(a265), .b(a266), .clk(clk), .q(t930)); + addfxp_18_1 add88441(.a(a267), .b(a268), .clk(clk), .q(t931)); + subfxp_18_1 sub88456(.a(a265), .b(a266), .clk(clk), .q(t932)); + subfxp_18_1 sub88471(.a(a267), .b(a268), .clk(clk), .q(t933)); + addfxp_18_1 add88486(.a(a273), .b(a274), .clk(clk), .q(t934)); + addfxp_18_1 add88501(.a(a275), .b(a276), .clk(clk), .q(t935)); + subfxp_18_1 sub88516(.a(a273), .b(a274), .clk(clk), .q(t936)); + subfxp_18_1 sub88531(.a(a275), .b(a276), .clk(clk), .q(t937)); + addfxp_18_1 add88746(.a(a281), .b(a282), .clk(clk), .q(t952)); + addfxp_18_1 add88761(.a(a283), .b(a284), .clk(clk), .q(t953)); + subfxp_18_1 sub88776(.a(a281), .b(a282), .clk(clk), .q(t954)); + subfxp_18_1 sub88791(.a(a283), .b(a284), .clk(clk), .q(t955)); + addfxp_18_1 add88806(.a(a289), .b(a290), .clk(clk), .q(t956)); + addfxp_18_1 add88821(.a(a291), .b(a292), .clk(clk), .q(t957)); + subfxp_18_1 sub88836(.a(a289), .b(a290), .clk(clk), .q(t958)); + subfxp_18_1 sub88851(.a(a291), .b(a292), .clk(clk), .q(t959)); + addfxp_18_1 add89012(.a(a297), .b(a298), .clk(clk), .q(t972)); + addfxp_18_1 add89027(.a(a299), .b(a300), .clk(clk), .q(t973)); + subfxp_18_1 sub89042(.a(a297), .b(a298), .clk(clk), .q(t974)); + subfxp_18_1 sub89057(.a(a299), .b(a300), .clk(clk), .q(t975)); + addfxp_18_1 add89072(.a(a305), .b(a306), .clk(clk), .q(t976)); + addfxp_18_1 add89087(.a(a307), .b(a308), .clk(clk), .q(t977)); + subfxp_18_1 sub89102(.a(a305), .b(a306), .clk(clk), .q(t978)); + subfxp_18_1 sub89117(.a(a307), .b(a308), .clk(clk), .q(t979)); + addfxp_18_1 add88330(.a(t914), .b(t918), .clk(clk), .q(t922)); + addfxp_18_1 add88337(.a(t915), .b(t919), .clk(clk), .q(t923)); + subfxp_18_1 sub88344(.a(t914), .b(t918), .clk(clk), .q(t924)); + subfxp_18_1 sub88351(.a(t915), .b(t919), .clk(clk), .q(t925)); + addfxp_18_1 add88374(.a(t916), .b(t921), .clk(clk), .q(t926)); + subfxp_18_1 sub88381(.a(t917), .b(t920), .clk(clk), .q(t927)); + subfxp_18_1 sub88388(.a(t916), .b(t921), .clk(clk), .q(t928)); + addfxp_18_1 add88395(.a(t917), .b(t920), .clk(clk), .q(t929)); + addfxp_18_1 add88538(.a(t930), .b(t934), .clk(clk), .q(t938)); + addfxp_18_1 add88545(.a(t931), .b(t935), .clk(clk), .q(t939)); + subfxp_18_1 sub88552(.a(t930), .b(t934), .clk(clk), .q(t940)); + subfxp_18_1 sub88559(.a(t931), .b(t935), .clk(clk), .q(t941)); + addfxp_18_1 add88610(.a(t932), .b(t937), .clk(clk), .q(t944)); + subfxp_18_1 sub88617(.a(t933), .b(t936), .clk(clk), .q(t945)); + subfxp_18_1 sub88624(.a(t932), .b(t937), .clk(clk), .q(t946)); + addfxp_18_1 add88631(.a(t933), .b(t936), .clk(clk), .q(t947)); + addfxp_18_1 add88858(.a(t952), .b(t956), .clk(clk), .q(t960)); + addfxp_18_1 add88865(.a(t953), .b(t957), .clk(clk), .q(t961)); + subfxp_18_1 sub88872(.a(t952), .b(t956), .clk(clk), .q(t962)); + subfxp_18_1 sub88879(.a(t953), .b(t957), .clk(clk), .q(t963)); + addfxp_18_1 add88903(.a(t954), .b(t959), .clk(clk), .q(t964)); + subfxp_18_1 sub88910(.a(t955), .b(t958), .clk(clk), .q(t965)); + subfxp_18_1 sub88917(.a(t954), .b(t959), .clk(clk), .q(t966)); + addfxp_18_1 add88924(.a(t955), .b(t958), .clk(clk), .q(t967)); + addfxp_18_1 add89124(.a(t972), .b(t976), .clk(clk), .q(t980)); + addfxp_18_1 add89131(.a(t973), .b(t977), .clk(clk), .q(t981)); + subfxp_18_1 sub89138(.a(t972), .b(t976), .clk(clk), .q(t982)); + subfxp_18_1 sub89145(.a(t973), .b(t977), .clk(clk), .q(t983)); + addfxp_18_1 add89197(.a(t974), .b(t979), .clk(clk), .q(t986)); + subfxp_18_1 sub89204(.a(t975), .b(t978), .clk(clk), .q(t987)); + subfxp_18_1 sub89211(.a(t974), .b(t979), .clk(clk), .q(t988)); + addfxp_18_1 add89218(.a(t975), .b(t978), .clk(clk), .q(t989)); + +multfix_alt_dsp_18 m88566(.ax(tm0), .ay(t940), .bx(tm0), .by(t941), .clk(clk), .a_q_sc(a225), .a_q_unsc(), .b_q_sc(a226), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88570(.ax(tm2), .ay(t944), .bx(tm3), .by(t945), .clk(clk), .a_q_sc(a227), .a_q_unsc(), .b_q_sc(a228), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88572(.ax(tm2), .ay(t945), .bx(tm3), .by(t944), .clk(clk), .a_q_sc(a229), .a_q_unsc(), .b_q_sc(a230), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88574(.ax(tm3), .ay(t946), .bx(tm2), .by(t947), .clk(clk), .a_q_sc(a231), .a_q_unsc(), .b_q_sc(a232), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88576(.ax(tm3), .ay(t947), .bx(tm2), .by(t946), .clk(clk), .a_q_sc(a233), .a_q_unsc(), .b_q_sc(a234), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88578(.ax(tm0), .ay(t964), .bx(tm0), .by(t965), .clk(clk), .a_q_sc(a235), .a_q_unsc(), .b_q_sc(a236), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88580(.ax(tm0), .ay(t967), .bx(tm0), .by(t966), .clk(clk), .a_q_sc(a237), .a_q_unsc(), .b_q_sc(a238), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88582(.ax(tm0), .ay(t983), .bx(tm0), .by(t982), .clk(clk), .a_q_sc(a239), .a_q_unsc(), .b_q_sc(a240), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88584(.ax(tm3), .ay(t986), .bx(tm2), .by(t987), .clk(clk), .a_q_sc(a241), .a_q_unsc(), .b_q_sc(a242), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88586(.ax(tm3), .ay(t987), .bx(tm2), .by(t986), .clk(clk), .a_q_sc(a243), .a_q_unsc(), .b_q_sc(a244), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88588(.ax(tm2), .ay(t988), .bx(tm3), .by(t989), .clk(clk), .a_q_sc(a245), .a_q_unsc(), .b_q_sc(a246), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88590(.ax(tm3), .ay(t988), .bx(tm2), .by(t989), .clk(clk), .a_q_sc(a247), .a_q_unsc(), .b_q_sc(a248), .b_q_unsc(), .rst(reset)); + +addfxp_18_1 add88580(.a(a225), .b(a226), .clk(clk), .q(t942)); + subfxp_18_1 sub88587(.a(a226), .b(a225), .clk(clk), .q(t943)); + addfxp_18_1 add88652(.a(a227), .b(a228), .clk(clk), .q(t948)); + subfxp_18_1 sub88673(.a(a229), .b(a230), .clk(clk), .q(t949)); + addfxp_18_1 add88694(.a(a231), .b(a232), .clk(clk), .q(t950)); + subfxp_18_1 sub88715(.a(a233), .b(a234), .clk(clk), .q(t951)); + addfxp_18_1 add88945(.a(a235), .b(a236), .clk(clk), .q(t968)); + subfxp_18_1 sub88952(.a(a236), .b(a235), .clk(clk), .q(t969)); + subfxp_18_1 sub88973(.a(a237), .b(a238), .clk(clk), .q(t970)); + addfxp_18_1 add88980(.a(a238), .b(a237), .clk(clk), .q(t971)); + subfxp_18_1 sub89166(.a(a239), .b(a240), .clk(clk), .q(t984)); + addfxp_18_1 add89173(.a(a240), .b(a239), .clk(clk), .q(t985)); + addfxp_18_1 add89239(.a(a241), .b(a242), .clk(clk), .q(t990)); + subfxp_18_1 sub89260(.a(a243), .b(a244), .clk(clk), .q(t991)); + addfxp_18_1 add89281(.a(a245), .b(a246), .clk(clk), .q(t992)); + subfxp_18_1 sub89302(.a(a247), .b(a248), .clk(clk), .q(t993)); + +always @(posedge clk) begin + if (reset == 1) begin + next <= 1'b0; + end else begin + X0 <= X0_in; + X1 <= X1_in; + X2 <= X2_in; + X3 <= X3_in; + X4 <= X4_in; + X5 <= X5_in; + X6 <= X6_in; + X7 <= X7_in; + X8 <= X8_in; + X9 <= X9_in; + X10 <= X10_in; + X11 <= X11_in; + X12 <= X12_in; + X13 <= X13_in; + X14 <= X14_in; + X15 <= X15_in; + X16 <= X16_in; + X17 <= X17_in; + X18 <= X18_in; + X19 <= X19_in; + X20 <= X20_in; + X21 <= X21_in; + X22 <= X22_in; + X23 <= X23_in; + X24 <= X24_in; + X25 <= X25_in; + X26 <= X26_in; + X27 <= X27_in; + X28 <= X28_in; + X29 <= X29_in; + X30 <= X30_in; + X31 <= X31_in; + next <= next_in; + tm24 <= t922; + tm27 <= t923; + tm30 <= t924; + tm33 <= t925; + tm36 <= t926; + tm39 <= t927; + tm42 <= t928; + tm45 <= t929; + tm48 <= t938; + tm51 <= t939; + tm54 <= t960; + tm57 <= t961; + tm60 <= t963; + tm63 <= (~(t962)+1'b1); + tm66 <= t980; + tm69 <= t981; + tm25 <= tm24; + tm28 <= tm27; + tm31 <= tm30; + tm34 <= tm33; + tm37 <= tm36; + tm40 <= tm39; + tm43 <= tm42; + tm46 <= tm45; + tm49 <= tm48; + tm52 <= tm51; + tm55 <= tm54; + tm58 <= tm57; + tm61 <= tm60; + tm64 <= tm63; + tm67 <= tm66; + tm70 <= tm69; + tm26 <= tm25; + tm29 <= tm28; + tm32 <= tm31; + tm35 <= tm34; + tm38 <= tm37; + tm41 <= tm40; + tm44 <= tm43; + tm47 <= tm46; + tm50 <= tm49; + tm53 <= tm52; + tm56 <= tm55; + tm59 <= tm58; + tm62 <= tm61; + tm65 <= tm64; + tm68 <= tm67; + tm71 <= tm70; + end +end + +endmodule + +module shiftRegFIFO_5_1 ( + input [0:0] X, + output [0:0] Y, + input reset, + input clk +); + +reg [0:0] mem_0; +reg [0:0] mem_1; +reg [0:0] mem_2; +reg [0:0] mem_3; +reg [0:0] mem_4; +assign Y = mem_4; + +always @ (posedge clk) begin + if (reset) begin + mem_0 <= 0; + mem_1 <= 0; + mem_2 <= 0; + mem_3 <= 0; + mem_4 <= 0; + end else begin + mem_1 <= mem_0; + mem_2 <= mem_1; + mem_3 <= mem_2; + mem_4 <= mem_3; + mem_0 <= X; + end +end + +endmodule + +module addfxp_18_1 ( + input [17:0] a, + input [17:0] b, + input clk, + output [17:0] q +); + +reg [17:0] res_0; +assign q = res_0; + +always @(posedge clk) begin + res_0 <= a + b; +end + +endmodule + +module subfxp_18_1 ( + input [17:0] a, + input [17:0] b, + input clk, + output [17:0] q +); + +reg [17:0] res_0; +assign q = res_0; + +always @(posedge clk) begin + res_0 <= a + b; +end + +endmodule + +module multfix_alt_dsp_18 ( + input [17:0] ax, + input [17:0] ay, + input [17:0] bx, + input [17:0] by, + input clk, + output [17:0] a_q_sc, + output [17:0] a_q_unsc, + output [17:0] b_q_sc, + output [17:0] b_q_unsc, + input rst +); + +wire [35:0] a_res; +wire [35:0] b_res; + +assign a_q_unsc = a_res[17:0]; +assign a_q_sc = {a_res[35-1], a_res[32 :16]}; +assign b_q_unsc = b_res[17:0]; +assign b_q_sc = {b_res[35-1], b_res[32 :16]}; + +dsp_signed_mult_18x18_unit_18_36_0 dsp_signed_mult_18x18_unit_18_36_0_inst_kmtggxwauz ( + .clk(clk), + .ena(1'b1), + .reset(rst), + .i_valid(), + .o_valid(), + .ax(ax), + .ay(ay), + .bx(bx), + .by(by), + .resulta(a_res), + .resultb(b_res) +); + +endmodule + +module dsp_signed_mult_18x18_unit_18_36_0 ( + input clk, + input reset, + input ena, + input i_valid, + input [17:0] ax, + input [17:0] ay, + input [17:0] bx, + input [17:0] by, + output o_valid, + output [35:0] resulta, + output [35:0] resultb +); + +reg [35:0] reg_resa, reg_resb; +reg valid_rr; +always @(posedge clk) begin + if (reset) begin + reg_resa <= 0; + reg_resb <= 0; + valid_rr <= 0; + end else if (ena) begin + reg_resa <= ax * ay; + reg_resb <= bx * by; + valid_rr <= ena; + end +end +assign resulta = reg_resa; +assign resultb = reg_resb; +assign o_valid = valid_rr; +endmodule + +module codeBlock89324_18 ( + input clk, + input reset, + input next_in, + input [17:0] X0_in, + output [17:0] Y0, + input [17:0] X1_in, + output [17:0] Y1, + input [17:0] X2_in, + output [17:0] Y2, + input [17:0] X3_in, + output [17:0] Y3, + input [17:0] X4_in, + output [17:0] Y4, + input [17:0] X5_in, + output [17:0] Y5, + input [17:0] X6_in, + output [17:0] Y6, + input [17:0] X7_in, + output [17:0] Y7, + input [17:0] X8_in, + output [17:0] Y8, + input [17:0] X9_in, + output [17:0] Y9, + input [17:0] X10_in, + output [17:0] Y10, + input [17:0] X11_in, + output [17:0] Y11, + input [17:0] X12_in, + output [17:0] Y12, + input [17:0] X13_in, + output [17:0] Y13, + input [17:0] X14_in, + output [17:0] Y14, + input [17:0] X15_in, + output [17:0] Y15, + input [17:0] X16_in, + output [17:0] Y16, + input [17:0] X17_in, + output [17:0] Y17, + input [17:0] X18_in, + output [17:0] Y18, + input [17:0] X19_in, + output [17:0] Y19, + input [17:0] X20_in, + output [17:0] Y20, + input [17:0] X21_in, + output [17:0] Y21, + input [17:0] X22_in, + output [17:0] Y22, + input [17:0] X23_in, + output [17:0] Y23, + input [17:0] X24_in, + output [17:0] Y24, + input [17:0] X25_in, + output [17:0] Y25, + input [17:0] X26_in, + output [17:0] Y26, + input [17:0] X27_in, + output [17:0] Y27, + input [17:0] X28_in, + output [17:0] Y28, + input [17:0] X29_in, + output [17:0] Y29, + input [17:0] X30_in, + output [17:0] Y30, + input [17:0] X31_in, + output [17:0] Y31, + output next_out +); + +reg next; +reg [17:0] X0; +reg [17:0] X1; +reg [17:0] X2; +reg [17:0] X3; +reg [17:0] X4; +reg [17:0] X5; +reg [17:0] X6; +reg [17:0] X7; +reg [17:0] X8; +reg [17:0] X9; +reg [17:0] X10; +reg [17:0] X11; +reg [17:0] X12; +reg [17:0] X13; +reg [17:0] X14; +reg [17:0] X15; +reg [17:0] X16; +reg [17:0] X17; +reg [17:0] X18; +reg [17:0] X19; +reg [17:0] X20; +reg [17:0] X21; +reg [17:0] X22; +reg [17:0] X23; +reg [17:0] X24; +reg [17:0] X25; +reg [17:0] X26; +reg [17:0] X27; +reg [17:0] X28; +reg [17:0] X29; +reg [17:0] X30; +reg [17:0] X31; + +shiftRegFIFO_2_1 shiftRegFIFO_2_1_inst_oxmjrpwtgg ( + .X(next), + .Y(next_out), + .reset(reset), + .clk(clk) +); + +wire [17:0] a65; + wire [17:0] a66; + wire [17:0] a67; + wire [17:0] a68; + wire [17:0] a73; + wire [17:0] a74; + wire [17:0] a75; + wire [17:0] a76; + wire [17:0] a81; + wire [17:0] a82; + wire [17:0] a83; + wire [17:0] a84; + wire [17:0] a89; + wire [17:0] a90; + wire [17:0] a91; + wire [17:0] a92; + wire [17:0] a97; + wire [17:0] a98; + wire [17:0] a99; + wire [17:0] a100; + wire [17:0] a105; + wire [17:0] a106; + wire [17:0] a107; + wire [17:0] a108; + wire [17:0] a113; + wire [17:0] a114; + wire [17:0] a115; + wire [17:0] a116; + wire [17:0] a121; + wire [17:0] a122; + wire [17:0] a123; + wire [17:0] a124; + wire [17:0] t402; + wire [17:0] t403; + wire [17:0] t404; + wire [17:0] t405; + wire [17:0] t406; + wire [17:0] t407; + wire [17:0] t408; + wire [17:0] t409; + wire [17:0] t418; + wire [17:0] t419; + wire [17:0] t420; + wire [17:0] t421; + wire [17:0] t422; + wire [17:0] t423; + wire [17:0] t424; + wire [17:0] t425; + wire [17:0] t434; + wire [17:0] t435; + wire [17:0] t436; + wire [17:0] t437; + wire [17:0] t438; + wire [17:0] t439; + wire [17:0] t440; + wire [17:0] t441; + wire [17:0] t450; + wire [17:0] t451; + wire [17:0] t452; + wire [17:0] t453; + wire [17:0] t454; + wire [17:0] t455; + wire [17:0] t456; + wire [17:0] t457; + wire [17:0] t410; + wire [17:0] t411; + wire [17:0] t412; + wire [17:0] t413; + wire [17:0] t414; + wire [17:0] t415; + wire [17:0] t416; + wire [17:0] t417; + wire [17:0] t426; + wire [17:0] t427; + wire [17:0] t428; + wire [17:0] t429; + wire [17:0] t430; + wire [17:0] t431; + wire [17:0] t432; + wire [17:0] t433; + wire [17:0] t442; + wire [17:0] t443; + wire [17:0] t444; + wire [17:0] t445; + wire [17:0] t446; + wire [17:0] t447; + wire [17:0] t448; + wire [17:0] t449; + wire [17:0] t458; + wire [17:0] t459; + wire [17:0] t460; + wire [17:0] t461; + wire [17:0] t462; + wire [17:0] t463; + wire [17:0] t464; + wire [17:0] t465; +assign a65 = X0; + assign a66 = X16; + assign a67 = X1; + assign a68 = X17; + assign a73 = X8; + assign a74 = X24; + assign a75 = X9; + assign a76 = X25; + assign a81 = X2; + assign a82 = X18; + assign a83 = X3; + assign a84 = X19; + assign a89 = X10; + assign a90 = X26; + assign a91 = X11; + assign a92 = X27; + assign a97 = X4; + assign a98 = X20; + assign a99 = X5; + assign a100 = X21; + assign a105 = X12; + assign a106 = X28; + assign a107 = X13; + assign a108 = X29; + assign a113 = X6; + assign a114 = X22; + assign a115 = X7; + assign a116 = X23; + assign a121 = X14; + assign a122 = X30; + assign a123 = X15; + assign a124 = X31; + assign Y0 = t410; + assign Y1 = t411; + assign Y16 = t412; + assign Y17 = t413; + assign Y8 = t414; + assign Y9 = t415; + assign Y24 = t416; + assign Y25 = t417; + assign Y2 = t426; + assign Y3 = t427; + assign Y18 = t428; + assign Y19 = t429; + assign Y10 = t430; + assign Y11 = t431; + assign Y26 = t432; + assign Y27 = t433; + assign Y4 = t442; + assign Y5 = t443; + assign Y20 = t444; + assign Y21 = t445; + assign Y12 = t446; + assign Y13 = t447; + assign Y28 = t448; + assign Y29 = t449; + assign Y6 = t458; + assign Y7 = t459; + assign Y22 = t460; + assign Y23 = t461; + assign Y14 = t462; + assign Y15 = t463; + assign Y30 = t464; + assign Y31 = t465; + +addfxp_18_1 add89336(.a(a65), .b(a66), .clk(clk), .q(t402)); + addfxp_18_1 add89351(.a(a67), .b(a68), .clk(clk), .q(t403)); + subfxp_18_1 sub89366(.a(a65), .b(a66), .clk(clk), .q(t404)); + subfxp_18_1 sub89381(.a(a67), .b(a68), .clk(clk), .q(t405)); + addfxp_18_1 add89396(.a(a73), .b(a74), .clk(clk), .q(t406)); + addfxp_18_1 add89411(.a(a75), .b(a76), .clk(clk), .q(t407)); + subfxp_18_1 sub89426(.a(a73), .b(a74), .clk(clk), .q(t408)); + subfxp_18_1 sub89441(.a(a75), .b(a76), .clk(clk), .q(t409)); + addfxp_18_1 add89544(.a(a81), .b(a82), .clk(clk), .q(t418)); + addfxp_18_1 add89559(.a(a83), .b(a84), .clk(clk), .q(t419)); + subfxp_18_1 sub89574(.a(a81), .b(a82), .clk(clk), .q(t420)); + subfxp_18_1 sub89589(.a(a83), .b(a84), .clk(clk), .q(t421)); + addfxp_18_1 add89604(.a(a89), .b(a90), .clk(clk), .q(t422)); + addfxp_18_1 add89619(.a(a91), .b(a92), .clk(clk), .q(t423)); + subfxp_18_1 sub89634(.a(a89), .b(a90), .clk(clk), .q(t424)); + subfxp_18_1 sub89649(.a(a91), .b(a92), .clk(clk), .q(t425)); + addfxp_18_1 add89752(.a(a97), .b(a98), .clk(clk), .q(t434)); + addfxp_18_1 add89767(.a(a99), .b(a100), .clk(clk), .q(t435)); + subfxp_18_1 sub89782(.a(a97), .b(a98), .clk(clk), .q(t436)); + subfxp_18_1 sub89797(.a(a99), .b(a100), .clk(clk), .q(t437)); + addfxp_18_1 add89812(.a(a105), .b(a106), .clk(clk), .q(t438)); + addfxp_18_1 add89827(.a(a107), .b(a108), .clk(clk), .q(t439)); + subfxp_18_1 sub89842(.a(a105), .b(a106), .clk(clk), .q(t440)); + subfxp_18_1 sub89857(.a(a107), .b(a108), .clk(clk), .q(t441)); + addfxp_18_1 add89960(.a(a113), .b(a114), .clk(clk), .q(t450)); + addfxp_18_1 add89975(.a(a115), .b(a116), .clk(clk), .q(t451)); + subfxp_18_1 sub89990(.a(a113), .b(a114), .clk(clk), .q(t452)); + subfxp_18_1 sub90005(.a(a115), .b(a116), .clk(clk), .q(t453)); + addfxp_18_1 add90020(.a(a121), .b(a122), .clk(clk), .q(t454)); + addfxp_18_1 add90035(.a(a123), .b(a124), .clk(clk), .q(t455)); + subfxp_18_1 sub90050(.a(a121), .b(a122), .clk(clk), .q(t456)); + subfxp_18_1 sub90065(.a(a123), .b(a124), .clk(clk), .q(t457)); + addfxp_18_1 add89448(.a(t402), .b(t406), .clk(clk), .q(t410)); + addfxp_18_1 add89455(.a(t403), .b(t407), .clk(clk), .q(t411)); + subfxp_18_1 sub89462(.a(t402), .b(t406), .clk(clk), .q(t412)); + subfxp_18_1 sub89469(.a(t403), .b(t407), .clk(clk), .q(t413)); + addfxp_18_1 add89492(.a(t404), .b(t409), .clk(clk), .q(t414)); + subfxp_18_1 sub89499(.a(t405), .b(t408), .clk(clk), .q(t415)); + subfxp_18_1 sub89506(.a(t404), .b(t409), .clk(clk), .q(t416)); + addfxp_18_1 add89513(.a(t405), .b(t408), .clk(clk), .q(t417)); + addfxp_18_1 add89656(.a(t418), .b(t422), .clk(clk), .q(t426)); + addfxp_18_1 add89663(.a(t419), .b(t423), .clk(clk), .q(t427)); + subfxp_18_1 sub89670(.a(t418), .b(t422), .clk(clk), .q(t428)); + subfxp_18_1 sub89677(.a(t419), .b(t423), .clk(clk), .q(t429)); + addfxp_18_1 add89700(.a(t420), .b(t425), .clk(clk), .q(t430)); + subfxp_18_1 sub89707(.a(t421), .b(t424), .clk(clk), .q(t431)); + subfxp_18_1 sub89714(.a(t420), .b(t425), .clk(clk), .q(t432)); + addfxp_18_1 add89721(.a(t421), .b(t424), .clk(clk), .q(t433)); + addfxp_18_1 add89864(.a(t434), .b(t438), .clk(clk), .q(t442)); + addfxp_18_1 add89871(.a(t435), .b(t439), .clk(clk), .q(t443)); + subfxp_18_1 sub89878(.a(t434), .b(t438), .clk(clk), .q(t444)); + subfxp_18_1 sub89885(.a(t435), .b(t439), .clk(clk), .q(t445)); + addfxp_18_1 add89908(.a(t436), .b(t441), .clk(clk), .q(t446)); + subfxp_18_1 sub89915(.a(t437), .b(t440), .clk(clk), .q(t447)); + subfxp_18_1 sub89922(.a(t436), .b(t441), .clk(clk), .q(t448)); + addfxp_18_1 add89929(.a(t437), .b(t440), .clk(clk), .q(t449)); + addfxp_18_1 add90072(.a(t450), .b(t454), .clk(clk), .q(t458)); + addfxp_18_1 add90079(.a(t451), .b(t455), .clk(clk), .q(t459)); + subfxp_18_1 sub90086(.a(t450), .b(t454), .clk(clk), .q(t460)); + subfxp_18_1 sub90093(.a(t451), .b(t455), .clk(clk), .q(t461)); + addfxp_18_1 add90116(.a(t452), .b(t457), .clk(clk), .q(t462)); + subfxp_18_1 sub90123(.a(t453), .b(t456), .clk(clk), .q(t463)); + subfxp_18_1 sub90130(.a(t452), .b(t457), .clk(clk), .q(t464)); + addfxp_18_1 add90137(.a(t453), .b(t456), .clk(clk), .q(t465)); + +always @(posedge clk) begin + if (reset == 1) begin + next <= 1'b0; + end else begin + X0 <= X0_in; + X1 <= X1_in; + X2 <= X2_in; + X3 <= X3_in; + X4 <= X4_in; + X5 <= X5_in; + X6 <= X6_in; + X7 <= X7_in; + X8 <= X8_in; + X9 <= X9_in; + X10 <= X10_in; + X11 <= X11_in; + X12 <= X12_in; + X13 <= X13_in; + X14 <= X14_in; + X15 <= X15_in; + X16 <= X16_in; + X17 <= X17_in; + X18 <= X18_in; + X19 <= X19_in; + X20 <= X20_in; + X21 <= X21_in; + X22 <= X22_in; + X23 <= X23_in; + X24 <= X24_in; + X25 <= X25_in; + X26 <= X26_in; + X27 <= X27_in; + X28 <= X28_in; + X29 <= X29_in; + X30 <= X30_in; + X31 <= X31_in; + next <= next_in; + end +end + +endmodule + +module shiftRegFIFO_2_1 ( + input [0:0] X, + output [0:0] Y, + input reset, + input clk +); + +reg [0:0] mem_0; +reg [0:0] mem_1; +reg [0:0] mem_2; +reg [0:0] mem_3; +reg [0:0] mem_4; +assign Y = mem_4; + +always @ (posedge clk) begin + if (reset) begin + mem_0 <= 0; + mem_1 <= 0; + mem_2 <= 0; + mem_3 <= 0; + mem_4 <= 0; + end else begin + mem_1 <= mem_0; + mem_2 <= mem_1; + mem_3 <= mem_2; + mem_4 <= mem_3; + mem_0 <= X; + end +end + +endmodule + +module elementwise_mult_core_18_1810_9_1 ( + input clk, + input reset, + input i_valid, + input i_ready, + input [17:0] i_A_0, + input [17:0] i_B_0, + output [17:0] o_C_0, + input [17:0] i_A_1, + input [17:0] i_B_1, + output [17:0] o_C_1, + input [17:0] i_A_2, + input [17:0] i_B_2, + output [17:0] o_C_2, + input [17:0] i_A_3, + input [17:0] i_B_3, + output [17:0] o_C_3, + input [17:0] i_A_4, + input [17:0] i_B_4, + output [17:0] o_C_4, + input [17:0] i_A_5, + input [17:0] i_B_5, + output [17:0] o_C_5, + input [17:0] i_A_6, + input [17:0] i_B_6, + output [17:0] o_C_6, + input [17:0] i_A_7, + input [17:0] i_B_7, + output [17:0] o_C_7, + input [17:0] i_A_8, + input [17:0] i_B_8, + output [17:0] o_C_8, + output o_valid, + output o_ready +); + +// Store inputs and outputs in registers +reg [17:0] reg_A_0; +reg [17:0] reg_B_0; +wire [17:0] reg_C_0; +reg [17:0] reg_A_1; +reg [17:0] reg_B_1; +wire [17:0] reg_C_1; +reg [17:0] reg_A_2; +reg [17:0] reg_B_2; +wire [17:0] reg_C_2; +reg [17:0] reg_A_3; +reg [17:0] reg_B_3; +wire [17:0] reg_C_3; +reg [17:0] reg_A_4; +reg [17:0] reg_B_4; +wire [17:0] reg_C_4; +reg [17:0] reg_A_5; +reg [17:0] reg_B_5; +wire [17:0] reg_C_5; +reg [17:0] reg_A_6; +reg [17:0] reg_B_6; +wire [17:0] reg_C_6; +reg [17:0] reg_A_7; +reg [17:0] reg_B_7; +wire [17:0] reg_C_7; +reg [17:0] reg_A_8; +reg [17:0] reg_B_8; +wire [17:0] reg_C_8; + +reg valid_A_B; +wire valid_C; +wire enable; +assign enable = i_ready; + +wire mult_valid_0; +wire round_valid_0; +wire [36:0] mult_C_0; +wire [36:0] rounded_C_0; +wire mult_valid_1; +wire round_valid_1; +wire [36:0] mult_C_1; +wire [36:0] rounded_C_1; +wire mult_valid_2; +wire round_valid_2; +wire [36:0] mult_C_2; +wire [36:0] rounded_C_2; +wire mult_valid_3; +wire round_valid_3; +wire [36:0] mult_C_3; +wire [36:0] rounded_C_3; +wire mult_valid_4; +wire round_valid_4; +wire [36:0] mult_C_4; +wire [36:0] rounded_C_4; +wire mult_valid_5; +wire round_valid_5; +wire [36:0] mult_C_5; +wire [36:0] rounded_C_5; +wire mult_valid_6; +wire round_valid_6; +wire [36:0] mult_C_6; +wire [36:0] rounded_C_6; +wire mult_valid_7; +wire round_valid_7; +wire [36:0] mult_C_7; +wire [36:0] rounded_C_7; +wire mult_valid_8; +wire round_valid_8; +wire [36:0] mult_C_8; +wire [36:0] rounded_C_8; + +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst0 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_0), + .ay(reg_B_0), + .bx(reg_A_1), + .by(reg_B_1), + .o_valid(mult_valid_0), + .resulta(mult_C_0), + .resultb(mult_C_1) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst2 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_2), + .ay(reg_B_2), + .bx(reg_A_3), + .by(reg_B_3), + .o_valid(mult_valid_2), + .resulta(mult_C_2), + .resultb(mult_C_3) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst4 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_4), + .ay(reg_B_4), + .bx(reg_A_5), + .by(reg_B_5), + .o_valid(mult_valid_4), + .resulta(mult_C_4), + .resultb(mult_C_5) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst6 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_6), + .ay(reg_B_6), + .bx(reg_A_7), + .by(reg_B_7), + .o_valid(mult_valid_6), + .resulta(mult_C_6), + .resultb(mult_C_7) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst8 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_8), + .ay(reg_B_8), + .bx(), + .by(), + .o_valid(mult_valid_8), + .resulta(mult_C_8), + .resultb() +); +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_0), + .in(mult_C_0), + .o_valid(round_valid_0), + .out(rounded_C_0) +); +assign reg_C_0 = rounded_C_0[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_1), + .in(mult_C_1), + .o_valid(round_valid_1), + .out(rounded_C_1) +); +assign reg_C_1 = rounded_C_1[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_2), + .in(mult_C_2), + .o_valid(round_valid_2), + .out(rounded_C_2) +); +assign reg_C_2 = rounded_C_2[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_3), + .in(mult_C_3), + .o_valid(round_valid_3), + .out(rounded_C_3) +); +assign reg_C_3 = rounded_C_3[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_4), + .in(mult_C_4), + .o_valid(round_valid_4), + .out(rounded_C_4) +); +assign reg_C_4 = rounded_C_4[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_5), + .in(mult_C_5), + .o_valid(round_valid_5), + .out(rounded_C_5) +); +assign reg_C_5 = rounded_C_5[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_6), + .in(mult_C_6), + .o_valid(round_valid_6), + .out(rounded_C_6) +); +assign reg_C_6 = rounded_C_6[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_7), + .in(mult_C_7), + .o_valid(round_valid_7), + .out(rounded_C_7) +); +assign reg_C_7 = rounded_C_7[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_8), + .in(mult_C_8), + .o_valid(round_valid_8), + .out(rounded_C_8) +); +assign reg_C_8 = rounded_C_8[17:0]; +always @ (posedge clk) begin + if (reset) begin + valid_A_B <= 1'b0; + reg_A_0 <= 0; + reg_B_0 <= 0; + reg_A_1 <= 0; + reg_B_1 <= 0; + reg_A_2 <= 0; + reg_B_2 <= 0; + reg_A_3 <= 0; + reg_B_3 <= 0; + reg_A_4 <= 0; + reg_B_4 <= 0; + reg_A_5 <= 0; + reg_B_5 <= 0; + reg_A_6 <= 0; + reg_B_6 <= 0; + reg_A_7 <= 0; + reg_B_7 <= 0; + reg_A_8 <= 0; + reg_B_8 <= 0; + end else if (enable) begin + reg_A_0 <= i_A_0; + reg_B_0 <= i_B_0; + reg_A_1 <= i_A_1; + reg_B_1 <= i_B_1; + reg_A_2 <= i_A_2; + reg_B_2 <= i_B_2; + reg_A_3 <= i_A_3; + reg_B_3 <= i_B_3; + reg_A_4 <= i_A_4; + reg_B_4 <= i_B_4; + reg_A_5 <= i_A_5; + reg_B_5 <= i_B_5; + reg_A_6 <= i_A_6; + reg_B_6 <= i_B_6; + reg_A_7 <= i_A_7; + reg_B_7 <= i_B_7; + reg_A_8 <= i_A_8; + reg_B_8 <= i_B_8; + valid_A_B <= i_valid; + end +end + +assign o_C_0 = reg_C_0; +assign o_C_1 = reg_C_1; +assign o_C_2 = reg_C_2; +assign o_C_3 = reg_C_3; +assign o_C_4 = reg_C_4; +assign o_C_5 = reg_C_5; +assign o_C_6 = reg_C_6; +assign o_C_7 = reg_C_7; +assign o_C_8 = reg_C_8; +assign valid_C = round_valid_0; +assign o_ready = i_ready; +assign o_valid = valid_C & i_ready; + +endmodule + +module dsp_signed_mult_18x18_unit_18_18_1 ( + input clk, + input reset, + input ena, + input i_valid, + input [17:0] ax, + input [17:0] ay, + input [17:0] bx, + input [17:0] by, + output o_valid, + output [36:0] resulta, + output [36:0] resultb +); + +reg [17:0] reg_ax, reg_ay, reg_bx, reg_by; +reg [36:0] reg_resa, reg_resb; +reg valid_r, valid_rr; +always @(posedge clk) begin + if (reset) begin + reg_ax <= 0; + reg_ay <= 0; + reg_bx <= 0; + reg_by <= 0; + reg_resa <= 0; + reg_resb <= 0; + valid_r <= 0; + valid_rr <= 0; + end else begin + reg_ax <= ax; + reg_ay <= ay; + reg_bx <= bx; + reg_by <= by; + reg_resa <= reg_ax * reg_ay; + reg_resb <= reg_bx * reg_by; + valid_r <= ena; + valid_rr <= valid_r; + end +end + +assign resulta = reg_resa; +assign resultb = reg_resb; +assign o_valid = valid_rr; +endmodule + +module fp_rounding_unit_1_37_10 ( + input clk, + input reset, + input enable, + input i_valid, + input [36:0] in, + output [36:0] out, + output o_valid +); + +reg [36:0] rounded_result; +reg [36:0] floor; +reg [36:0] ceil; +reg is_ceil; +reg floor_ceil_valid; + +always @ (*) begin + if (is_ceil) begin + rounded_result = ceil; + end else begin + rounded_result = floor; + end +end + +reg valid_reg; +reg [36:0] out_reg; +always @ (posedge clk) begin + if (reset) begin + is_ceil <= 1'b0; + floor_ceil_valid <= 1'b0; + valid_reg <= 1'b0; + floor <= 0; + ceil <= 0; + out_reg <= 0; + end else if (enable) begin + is_ceil <= in[9]; + floor <= in >>> 10; + ceil <= (in >>> 10) + 1; + floor_ceil_valid <= i_valid; + out_reg <= rounded_result; + valid_reg <= floor_ceil_valid; + end +end + +assign o_valid = valid_reg; + +assign out = out_reg; + +endmodule + +module elementwise_sub_core_18_18_9 ( + input clk, + input reset, + input i_valid, + input i_ready, + input [17:0] i_A_0, + input [17:0] i_B_0, + output [17:0] o_C_0, + input [17:0] i_A_1, + input [17:0] i_B_1, + output [17:0] o_C_1, + input [17:0] i_A_2, + input [17:0] i_B_2, + output [17:0] o_C_2, + input [17:0] i_A_3, + input [17:0] i_B_3, + output [17:0] o_C_3, + input [17:0] i_A_4, + input [17:0] i_B_4, + output [17:0] o_C_4, + input [17:0] i_A_5, + input [17:0] i_B_5, + output [17:0] o_C_5, + input [17:0] i_A_6, + input [17:0] i_B_6, + output [17:0] o_C_6, + input [17:0] i_A_7, + input [17:0] i_B_7, + output [17:0] o_C_7, + input [17:0] i_A_8, + input [17:0] i_B_8, + output [17:0] o_C_8, + output o_valid, + output o_ready +); + +reg [17:0] reg_A_0; +reg [17:0] reg_B_0; +reg [17:0] reg_C_0; +reg [17:0] reg_A_1; +reg [17:0] reg_B_1; +reg [17:0] reg_C_1; +reg [17:0] reg_A_2; +reg [17:0] reg_B_2; +reg [17:0] reg_C_2; +reg [17:0] reg_A_3; +reg [17:0] reg_B_3; +reg [17:0] reg_C_3; +reg [17:0] reg_A_4; +reg [17:0] reg_B_4; +reg [17:0] reg_C_4; +reg [17:0] reg_A_5; +reg [17:0] reg_B_5; +reg [17:0] reg_C_5; +reg [17:0] reg_A_6; +reg [17:0] reg_B_6; +reg [17:0] reg_C_6; +reg [17:0] reg_A_7; +reg [17:0] reg_B_7; +reg [17:0] reg_C_7; +reg [17:0] reg_A_8; +reg [17:0] reg_B_8; +reg [17:0] reg_C_8; + +reg valid_A_B, valid_C; +wire enable; +assign enable = i_ready; + +always @ (posedge clk) begin + if (reset) begin + valid_A_B <= 1'b0; + valid_C <= 1'b0; + reg_A_0 <= 0; + reg_B_0 <= 0; + reg_C_0 <= 0; + reg_A_1 <= 0; + reg_B_1 <= 0; + reg_C_1 <= 0; + reg_A_2 <= 0; + reg_B_2 <= 0; + reg_C_2 <= 0; + reg_A_3 <= 0; + reg_B_3 <= 0; + reg_C_3 <= 0; + reg_A_4 <= 0; + reg_B_4 <= 0; + reg_C_4 <= 0; + reg_A_5 <= 0; + reg_B_5 <= 0; + reg_C_5 <= 0; + reg_A_6 <= 0; + reg_B_6 <= 0; + reg_C_6 <= 0; + reg_A_7 <= 0; + reg_B_7 <= 0; + reg_C_7 <= 0; + reg_A_8 <= 0; + reg_B_8 <= 0; + reg_C_8 <= 0; + end else if (enable) begin + reg_A_0 <= i_A_0; + reg_B_0 <= i_B_0; + reg_C_0 <= reg_A_0 - reg_B_0; + reg_A_1 <= i_A_1; + reg_B_1 <= i_B_1; + reg_C_1 <= reg_A_1 - reg_B_1; + reg_A_2 <= i_A_2; + reg_B_2 <= i_B_2; + reg_C_2 <= reg_A_2 - reg_B_2; + reg_A_3 <= i_A_3; + reg_B_3 <= i_B_3; + reg_C_3 <= reg_A_3 - reg_B_3; + reg_A_4 <= i_A_4; + reg_B_4 <= i_B_4; + reg_C_4 <= reg_A_4 - reg_B_4; + reg_A_5 <= i_A_5; + reg_B_5 <= i_B_5; + reg_C_5 <= reg_A_5 - reg_B_5; + reg_A_6 <= i_A_6; + reg_B_6 <= i_B_6; + reg_C_6 <= reg_A_6 - reg_B_6; + reg_A_7 <= i_A_7; + reg_B_7 <= i_B_7; + reg_C_7 <= reg_A_7 - reg_B_7; + reg_A_8 <= i_A_8; + reg_B_8 <= i_B_8; + reg_C_8 <= reg_A_8 - reg_B_8; + valid_A_B <= i_valid; + valid_C <= valid_A_B; + end +end + +assign o_C_0 = reg_C_0; +assign o_C_1 = reg_C_1; +assign o_C_2 = reg_C_2; +assign o_C_3 = reg_C_3; +assign o_C_4 = reg_C_4; +assign o_C_5 = reg_C_5; +assign o_C_6 = reg_C_6; +assign o_C_7 = reg_C_7; +assign o_C_8 = reg_C_8; +assign o_ready = i_ready; +assign o_valid = valid_C & i_ready; + +endmodule + +module elementwise_add_core_18_18_9 ( + input clk, + input reset, + input i_valid, + input i_ready, + input [17:0] i_A_0, + input [17:0] i_B_0, + output [17:0] o_C_0, + input [17:0] i_A_1, + input [17:0] i_B_1, + output [17:0] o_C_1, + input [17:0] i_A_2, + input [17:0] i_B_2, + output [17:0] o_C_2, + input [17:0] i_A_3, + input [17:0] i_B_3, + output [17:0] o_C_3, + input [17:0] i_A_4, + input [17:0] i_B_4, + output [17:0] o_C_4, + input [17:0] i_A_5, + input [17:0] i_B_5, + output [17:0] o_C_5, + input [17:0] i_A_6, + input [17:0] i_B_6, + output [17:0] o_C_6, + input [17:0] i_A_7, + input [17:0] i_B_7, + output [17:0] o_C_7, + input [17:0] i_A_8, + input [17:0] i_B_8, + output [17:0] o_C_8, + output o_valid, + output o_ready +); + +reg [17:0] reg_A_0; +reg [17:0] reg_B_0; +reg [17:0] reg_C_0; +reg [17:0] reg_A_1; +reg [17:0] reg_B_1; +reg [17:0] reg_C_1; +reg [17:0] reg_A_2; +reg [17:0] reg_B_2; +reg [17:0] reg_C_2; +reg [17:0] reg_A_3; +reg [17:0] reg_B_3; +reg [17:0] reg_C_3; +reg [17:0] reg_A_4; +reg [17:0] reg_B_4; +reg [17:0] reg_C_4; +reg [17:0] reg_A_5; +reg [17:0] reg_B_5; +reg [17:0] reg_C_5; +reg [17:0] reg_A_6; +reg [17:0] reg_B_6; +reg [17:0] reg_C_6; +reg [17:0] reg_A_7; +reg [17:0] reg_B_7; +reg [17:0] reg_C_7; +reg [17:0] reg_A_8; +reg [17:0] reg_B_8; +reg [17:0] reg_C_8; + +reg valid_A_B, valid_C; +wire enable; +assign enable = i_ready; + +always @ (posedge clk) begin + if (reset) begin + valid_A_B <= 1'b0; + valid_C <= 1'b0; + reg_A_0 <= 0; + reg_B_0 <= 0; + reg_C_0 <= 0; + reg_A_1 <= 0; + reg_B_1 <= 0; + reg_C_1 <= 0; + reg_A_2 <= 0; + reg_B_2 <= 0; + reg_C_2 <= 0; + reg_A_3 <= 0; + reg_B_3 <= 0; + reg_C_3 <= 0; + reg_A_4 <= 0; + reg_B_4 <= 0; + reg_C_4 <= 0; + reg_A_5 <= 0; + reg_B_5 <= 0; + reg_C_5 <= 0; + reg_A_6 <= 0; + reg_B_6 <= 0; + reg_C_6 <= 0; + reg_A_7 <= 0; + reg_B_7 <= 0; + reg_C_7 <= 0; + reg_A_8 <= 0; + reg_B_8 <= 0; + reg_C_8 <= 0; + end else if (enable) begin + reg_A_0 <= i_A_0; + reg_B_0 <= i_B_0; + reg_C_0 <= reg_A_0 + reg_B_0; + reg_A_1 <= i_A_1; + reg_B_1 <= i_B_1; + reg_C_1 <= reg_A_1 + reg_B_1; + reg_A_2 <= i_A_2; + reg_B_2 <= i_B_2; + reg_C_2 <= reg_A_2 + reg_B_2; + reg_A_3 <= i_A_3; + reg_B_3 <= i_B_3; + reg_C_3 <= reg_A_3 + reg_B_3; + reg_A_4 <= i_A_4; + reg_B_4 <= i_B_4; + reg_C_4 <= reg_A_4 + reg_B_4; + reg_A_5 <= i_A_5; + reg_B_5 <= i_B_5; + reg_C_5 <= reg_A_5 + reg_B_5; + reg_A_6 <= i_A_6; + reg_B_6 <= i_B_6; + reg_C_6 <= reg_A_6 + reg_B_6; + reg_A_7 <= i_A_7; + reg_B_7 <= i_B_7; + reg_C_7 <= reg_A_7 + reg_B_7; + reg_A_8 <= i_A_8; + reg_B_8 <= i_B_8; + reg_C_8 <= reg_A_8 + reg_B_8; + valid_A_B <= i_valid; + valid_C <= valid_A_B; + end +end + +assign o_C_0 = reg_C_0; +assign o_C_1 = reg_C_1; +assign o_C_2 = reg_C_2; +assign o_C_3 = reg_C_3; +assign o_C_4 = reg_C_4; +assign o_C_5 = reg_C_5; +assign o_C_6 = reg_C_6; +assign o_C_7 = reg_C_7; +assign o_C_8 = reg_C_8; +assign o_ready = i_ready; +assign o_valid = valid_C & i_ready; + +endmodule + +module sum_complex_vector_unit_18_18_16_42 ( + input clk, + input clr, + input i_valid, + input enable, + input [17:0] i_real_0, + input [17:0] i_imag_0, + output [17:0] o_real_0, + output [17:0] o_imag_0, + input [17:0] i_real_1, + input [17:0] i_imag_1, + output [17:0] o_real_1, + output [17:0] o_imag_1, + input [17:0] i_real_2, + input [17:0] i_imag_2, + output [17:0] o_real_2, + output [17:0] o_imag_2, + input [17:0] i_real_3, + input [17:0] i_imag_3, + output [17:0] o_real_3, + output [17:0] o_imag_3, + input [17:0] i_real_4, + input [17:0] i_imag_4, + output [17:0] o_real_4, + output [17:0] o_imag_4, + input [17:0] i_real_5, + input [17:0] i_imag_5, + output [17:0] o_real_5, + output [17:0] o_imag_5, + input [17:0] i_real_6, + input [17:0] i_imag_6, + output [17:0] o_real_6, + output [17:0] o_imag_6, + input [17:0] i_real_7, + input [17:0] i_imag_7, + output [17:0] o_real_7, + output [17:0] o_imag_7, + input [17:0] i_real_8, + input [17:0] i_imag_8, + output [17:0] o_real_8, + output [17:0] o_imag_8, + input [17:0] i_real_9, + input [17:0] i_imag_9, + output [17:0] o_real_9, + output [17:0] o_imag_9, + input [17:0] i_real_10, + input [17:0] i_imag_10, + output [17:0] o_real_10, + output [17:0] o_imag_10, + input [17:0] i_real_11, + input [17:0] i_imag_11, + output [17:0] o_real_11, + output [17:0] o_imag_11, + input [17:0] i_real_12, + input [17:0] i_imag_12, + output [17:0] o_real_12, + output [17:0] o_imag_12, + input [17:0] i_real_13, + input [17:0] i_imag_13, + output [17:0] o_real_13, + output [17:0] o_imag_13, + input [17:0] i_real_14, + input [17:0] i_imag_14, + output [17:0] o_real_14, + output [17:0] o_imag_14, + input [17:0] i_real_15, + input [17:0] i_imag_15, + output [17:0] o_real_15, + output [17:0] o_imag_15, + output o_valid +); + +reg [17:0] sum_real_0; +reg [17:0] sum_imag_0; +reg [17:0] sum_real_1; +reg [17:0] sum_imag_1; +reg [17:0] sum_real_2; +reg [17:0] sum_imag_2; +reg [17:0] sum_real_3; +reg [17:0] sum_imag_3; +reg [17:0] sum_real_4; +reg [17:0] sum_imag_4; +reg [17:0] sum_real_5; +reg [17:0] sum_imag_5; +reg [17:0] sum_real_6; +reg [17:0] sum_imag_6; +reg [17:0] sum_real_7; +reg [17:0] sum_imag_7; +reg [17:0] sum_real_8; +reg [17:0] sum_imag_8; +reg [17:0] sum_real_9; +reg [17:0] sum_imag_9; +reg [17:0] sum_real_10; +reg [17:0] sum_imag_10; +reg [17:0] sum_real_11; +reg [17:0] sum_imag_11; +reg [17:0] sum_real_12; +reg [17:0] sum_imag_12; +reg [17:0] sum_real_13; +reg [17:0] sum_imag_13; +reg [17:0] sum_real_14; +reg [17:0] sum_imag_14; +reg [17:0] sum_real_15; +reg [17:0] sum_imag_15; +reg reg_i_valid; + +// Count the number data in accumulation +reg [13:0] counter; +wire counter_full; +always @ (posedge clk) begin + if (clr) begin + sum_real_0 <= 0; + sum_imag_0 <= 0; + sum_real_1 <= 0; + sum_imag_1 <= 0; + sum_real_2 <= 0; + sum_imag_2 <= 0; + sum_real_3 <= 0; + sum_imag_3 <= 0; + sum_real_4 <= 0; + sum_imag_4 <= 0; + sum_real_5 <= 0; + sum_imag_5 <= 0; + sum_real_6 <= 0; + sum_imag_6 <= 0; + sum_real_7 <= 0; + sum_imag_7 <= 0; + sum_real_8 <= 0; + sum_imag_8 <= 0; + sum_real_9 <= 0; + sum_imag_9 <= 0; + sum_real_10 <= 0; + sum_imag_10 <= 0; + sum_real_11 <= 0; + sum_imag_11 <= 0; + sum_real_12 <= 0; + sum_imag_12 <= 0; + sum_real_13 <= 0; + sum_imag_13 <= 0; + sum_real_14 <= 0; + sum_imag_14 <= 0; + sum_real_15 <= 0; + sum_imag_15 <= 0; + counter <= 14'd0; + reg_i_valid <= 1'b0; + end else if (enable) begin + reg_i_valid <= i_valid; + // Accumulate the number only when data is valid + if (i_valid) begin + if (counter == 42) + counter <= 1; + else + counter <= counter + 1'b1; + + if (counter == 42) begin + sum_real_0 <= i_real_0; + sum_imag_0 <= i_imag_0; + sum_real_1 <= i_real_1; + sum_imag_1 <= i_imag_1; + sum_real_2 <= i_real_2; + sum_imag_2 <= i_imag_2; + sum_real_3 <= i_real_3; + sum_imag_3 <= i_imag_3; + sum_real_4 <= i_real_4; + sum_imag_4 <= i_imag_4; + sum_real_5 <= i_real_5; + sum_imag_5 <= i_imag_5; + sum_real_6 <= i_real_6; + sum_imag_6 <= i_imag_6; + sum_real_7 <= i_real_7; + sum_imag_7 <= i_imag_7; + sum_real_8 <= i_real_8; + sum_imag_8 <= i_imag_8; + sum_real_9 <= i_real_9; + sum_imag_9 <= i_imag_9; + sum_real_10 <= i_real_10; + sum_imag_10 <= i_imag_10; + sum_real_11 <= i_real_11; + sum_imag_11 <= i_imag_11; + sum_real_12 <= i_real_12; + sum_imag_12 <= i_imag_12; + sum_real_13 <= i_real_13; + sum_imag_13 <= i_imag_13; + sum_real_14 <= i_real_14; + sum_imag_14 <= i_imag_14; + sum_real_15 <= i_real_15; + sum_imag_15 <= i_imag_15; + end else begin + sum_real_0 <= sum_real_0 + i_real_0; + sum_imag_0 <= sum_imag_0 + i_imag_0; + sum_real_1 <= sum_real_1 + i_real_1; + sum_imag_1 <= sum_imag_1 + i_imag_1; + sum_real_2 <= sum_real_2 + i_real_2; + sum_imag_2 <= sum_imag_2 + i_imag_2; + sum_real_3 <= sum_real_3 + i_real_3; + sum_imag_3 <= sum_imag_3 + i_imag_3; + sum_real_4 <= sum_real_4 + i_real_4; + sum_imag_4 <= sum_imag_4 + i_imag_4; + sum_real_5 <= sum_real_5 + i_real_5; + sum_imag_5 <= sum_imag_5 + i_imag_5; + sum_real_6 <= sum_real_6 + i_real_6; + sum_imag_6 <= sum_imag_6 + i_imag_6; + sum_real_7 <= sum_real_7 + i_real_7; + sum_imag_7 <= sum_imag_7 + i_imag_7; + sum_real_8 <= sum_real_8 + i_real_8; + sum_imag_8 <= sum_imag_8 + i_imag_8; + sum_real_9 <= sum_real_9 + i_real_9; + sum_imag_9 <= sum_imag_9 + i_imag_9; + sum_real_10 <= sum_real_10 + i_real_10; + sum_imag_10 <= sum_imag_10 + i_imag_10; + sum_real_11 <= sum_real_11 + i_real_11; + sum_imag_11 <= sum_imag_11 + i_imag_11; + sum_real_12 <= sum_real_12 + i_real_12; + sum_imag_12 <= sum_imag_12 + i_imag_12; + sum_real_13 <= sum_real_13 + i_real_13; + sum_imag_13 <= sum_imag_13 + i_imag_13; + sum_real_14 <= sum_real_14 + i_real_14; + sum_imag_14 <= sum_imag_14 + i_imag_14; + sum_real_15 <= sum_real_15 + i_real_15; + sum_imag_15 <= sum_imag_15 + i_imag_15; + end + end + end +end + +assign counter_full = (counter == 42); +assign o_real_0 = sum_real_0; +assign o_imag_0 = sum_imag_0; +assign o_real_1 = sum_real_1; +assign o_imag_1 = sum_imag_1; +assign o_real_2 = sum_real_2; +assign o_imag_2 = sum_imag_2; +assign o_real_3 = sum_real_3; +assign o_imag_3 = sum_imag_3; +assign o_real_4 = sum_real_4; +assign o_imag_4 = sum_imag_4; +assign o_real_5 = sum_real_5; +assign o_imag_5 = sum_imag_5; +assign o_real_6 = sum_real_6; +assign o_imag_6 = sum_imag_6; +assign o_real_7 = sum_real_7; +assign o_imag_7 = sum_imag_7; +assign o_real_8 = sum_real_8; +assign o_imag_8 = sum_imag_8; +assign o_real_9 = sum_real_9; +assign o_imag_9 = sum_imag_9; +assign o_real_10 = sum_real_10; +assign o_imag_10 = sum_imag_10; +assign o_real_11 = sum_real_11; +assign o_imag_11 = sum_imag_11; +assign o_real_12 = sum_real_12; +assign o_imag_12 = sum_imag_12; +assign o_real_13 = sum_real_13; +assign o_imag_13 = sum_imag_13; +assign o_real_14 = sum_real_14; +assign o_imag_14 = sum_imag_14; +assign o_real_15 = sum_real_15; +assign o_imag_15 = sum_imag_15; +assign o_valid = counter_full & reg_i_valid; + +endmodule + +module shift_register_group_18_16_1 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input reset +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +endmodule + +module shift_register_unit_18_1 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + end +end + +assign out = shift_registers_0; + +endmodule + +module idft_16_top_18 ( + input clk, + input reset, + input next, + input [17:0] X0, + output [17:0] Y0, + input [17:0] X1, + output [17:0] Y1, + input [17:0] X2, + output [17:0] Y2, + input [17:0] X3, + output [17:0] Y3, + input [17:0] X4, + output [17:0] Y4, + input [17:0] X5, + output [17:0] Y5, + input [17:0] X6, + output [17:0] Y6, + input [17:0] X7, + output [17:0] Y7, + input [17:0] X8, + output [17:0] Y8, + input [17:0] X9, + output [17:0] Y9, + input [17:0] X10, + output [17:0] Y10, + input [17:0] X11, + output [17:0] Y11, + input [17:0] X12, + output [17:0] Y12, + input [17:0] X13, + output [17:0] Y13, + input [17:0] X14, + output [17:0] Y14, + input [17:0] X15, + output [17:0] Y15, + input [17:0] X16, + output [17:0] Y16, + input [17:0] X17, + output [17:0] Y17, + input [17:0] X18, + output [17:0] Y18, + input [17:0] X19, + output [17:0] Y19, + input [17:0] X20, + output [17:0] Y20, + input [17:0] X21, + output [17:0] Y21, + input [17:0] X22, + output [17:0] Y22, + input [17:0] X23, + output [17:0] Y23, + input [17:0] X24, + output [17:0] Y24, + input [17:0] X25, + output [17:0] Y25, + input [17:0] X26, + output [17:0] Y26, + input [17:0] X27, + output [17:0] Y27, + input [17:0] X28, + output [17:0] Y28, + input [17:0] X29, + output [17:0] Y29, + input [17:0] X30, + output [17:0] Y30, + input [17:0] X31, + output [17:0] Y31, + output next_out +); +wire [17:0] t0_0; +wire [17:0] t0_1; +wire [17:0] t0_2; +wire [17:0] t0_3; +wire [17:0] t0_4; +wire [17:0] t0_5; +wire [17:0] t0_6; +wire [17:0] t0_7; +wire [17:0] t0_8; +wire [17:0] t0_9; +wire [17:0] t0_10; +wire [17:0] t0_11; +wire [17:0] t0_12; +wire [17:0] t0_13; +wire [17:0] t0_14; +wire [17:0] t0_15; +wire [17:0] t0_16; +wire [17:0] t0_17; +wire [17:0] t0_18; +wire [17:0] t0_19; +wire [17:0] t0_20; +wire [17:0] t0_21; +wire [17:0] t0_22; +wire [17:0] t0_23; +wire [17:0] t0_24; +wire [17:0] t0_25; +wire [17:0] t0_26; +wire [17:0] t0_27; +wire [17:0] t0_28; +wire [17:0] t0_29; +wire [17:0] t0_30; +wire [17:0] t0_31; +wire next_0; +wire [17:0] t1_0; +wire [17:0] t1_1; +wire [17:0] t1_2; +wire [17:0] t1_3; +wire [17:0] t1_4; +wire [17:0] t1_5; +wire [17:0] t1_6; +wire [17:0] t1_7; +wire [17:0] t1_8; +wire [17:0] t1_9; +wire [17:0] t1_10; +wire [17:0] t1_11; +wire [17:0] t1_12; +wire [17:0] t1_13; +wire [17:0] t1_14; +wire [17:0] t1_15; +wire [17:0] t1_16; +wire [17:0] t1_17; +wire [17:0] t1_18; +wire [17:0] t1_19; +wire [17:0] t1_20; +wire [17:0] t1_21; +wire [17:0] t1_22; +wire [17:0] t1_23; +wire [17:0] t1_24; +wire [17:0] t1_25; +wire [17:0] t1_26; +wire [17:0] t1_27; +wire [17:0] t1_28; +wire [17:0] t1_29; +wire [17:0] t1_30; +wire [17:0] t1_31; +wire next_1; +wire [17:0] t2_0; +wire [17:0] t2_1; +wire [17:0] t2_2; +wire [17:0] t2_3; +wire [17:0] t2_4; +wire [17:0] t2_5; +wire [17:0] t2_6; +wire [17:0] t2_7; +wire [17:0] t2_8; +wire [17:0] t2_9; +wire [17:0] t2_10; +wire [17:0] t2_11; +wire [17:0] t2_12; +wire [17:0] t2_13; +wire [17:0] t2_14; +wire [17:0] t2_15; +wire [17:0] t2_16; +wire [17:0] t2_17; +wire [17:0] t2_18; +wire [17:0] t2_19; +wire [17:0] t2_20; +wire [17:0] t2_21; +wire [17:0] t2_22; +wire [17:0] t2_23; +wire [17:0] t2_24; +wire [17:0] t2_25; +wire [17:0] t2_26; +wire [17:0] t2_27; +wire [17:0] t2_28; +wire [17:0] t2_29; +wire [17:0] t2_30; +wire [17:0] t2_31; +wire next_2; + +assign t0_0 = X0; +assign Y0 = t2_0; +assign t0_1 = X1; +assign Y1 = t2_1; +assign t0_2 = X2; +assign Y2 = t2_2; +assign t0_3 = X3; +assign Y3 = t2_3; +assign t0_4 = X4; +assign Y4 = t2_4; +assign t0_5 = X5; +assign Y5 = t2_5; +assign t0_6 = X6; +assign Y6 = t2_6; +assign t0_7 = X7; +assign Y7 = t2_7; +assign t0_8 = X8; +assign Y8 = t2_8; +assign t0_9 = X9; +assign Y9 = t2_9; +assign t0_10 = X10; +assign Y10 = t2_10; +assign t0_11 = X11; +assign Y11 = t2_11; +assign t0_12 = X12; +assign Y12 = t2_12; +assign t0_13 = X13; +assign Y13 = t2_13; +assign t0_14 = X14; +assign Y14 = t2_14; +assign t0_15 = X15; +assign Y15 = t2_15; +assign t0_16 = X16; +assign Y16 = t2_16; +assign t0_17 = X17; +assign Y17 = t2_17; +assign t0_18 = X18; +assign Y18 = t2_18; +assign t0_19 = X19; +assign Y19 = t2_19; +assign t0_20 = X20; +assign Y20 = t2_20; +assign t0_21 = X21; +assign Y21 = t2_21; +assign t0_22 = X22; +assign Y22 = t2_22; +assign t0_23 = X23; +assign Y23 = t2_23; +assign t0_24 = X24; +assign Y24 = t2_24; +assign t0_25 = X25; +assign Y25 = t2_25; +assign t0_26 = X26; +assign Y26 = t2_26; +assign t0_27 = X27; +assign Y27 = t2_27; +assign t0_28 = X28; +assign Y28 = t2_28; +assign t0_29 = X29; +assign Y29 = t2_29; +assign t0_30 = X30; +assign Y30 = t2_30; +assign t0_31 = X31; +assign Y31 = t2_31; +assign next_0 = next; +assign next_out = next_2; +codeBlock98050_18 codeBlock98050_18_inst_otyhxefhqp ( + .clk(clk), + .reset(reset), + .next_in(next_0), + .X0_in(t0_0), + .Y0(t1_0), + .X1_in(t0_1), + .Y1(t1_1), + .X2_in(t0_2), + .Y2(t1_2), + .X3_in(t0_3), + .Y3(t1_3), + .X4_in(t0_4), + .Y4(t1_4), + .X5_in(t0_5), + .Y5(t1_5), + .X6_in(t0_6), + .Y6(t1_6), + .X7_in(t0_7), + .Y7(t1_7), + .X8_in(t0_8), + .Y8(t1_8), + .X9_in(t0_9), + .Y9(t1_9), + .X10_in(t0_10), + .Y10(t1_10), + .X11_in(t0_11), + .Y11(t1_11), + .X12_in(t0_12), + .Y12(t1_12), + .X13_in(t0_13), + .Y13(t1_13), + .X14_in(t0_14), + .Y14(t1_14), + .X15_in(t0_15), + .Y15(t1_15), + .X16_in(t0_16), + .Y16(t1_16), + .X17_in(t0_17), + .Y17(t1_17), + .X18_in(t0_18), + .Y18(t1_18), + .X19_in(t0_19), + .Y19(t1_19), + .X20_in(t0_20), + .Y20(t1_20), + .X21_in(t0_21), + .Y21(t1_21), + .X22_in(t0_22), + .Y22(t1_22), + .X23_in(t0_23), + .Y23(t1_23), + .X24_in(t0_24), + .Y24(t1_24), + .X25_in(t0_25), + .Y25(t1_25), + .X26_in(t0_26), + .Y26(t1_26), + .X27_in(t0_27), + .Y27(t1_27), + .X28_in(t0_28), + .Y28(t1_28), + .X29_in(t0_29), + .Y29(t1_29), + .X30_in(t0_30), + .Y30(t1_30), + .X31_in(t0_31), + .Y31(t1_31), + .next_out(next_1) +); + +codeBlock99168_18 codeBlock99168_18_inst_ubfqmbealj ( + .clk(clk), + .reset(reset), + .next_in(next_1), + .X0_in(t1_0), + .Y0(t2_0), + .X1_in(t1_1), + .Y1(t2_1), + .X2_in(t1_2), + .Y2(t2_2), + .X3_in(t1_3), + .Y3(t2_3), + .X4_in(t1_4), + .Y4(t2_4), + .X5_in(t1_5), + .Y5(t2_5), + .X6_in(t1_6), + .Y6(t2_6), + .X7_in(t1_7), + .Y7(t2_7), + .X8_in(t1_8), + .Y8(t2_8), + .X9_in(t1_9), + .Y9(t2_9), + .X10_in(t1_10), + .Y10(t2_10), + .X11_in(t1_11), + .Y11(t2_11), + .X12_in(t1_12), + .Y12(t2_12), + .X13_in(t1_13), + .Y13(t2_13), + .X14_in(t1_14), + .Y14(t2_14), + .X15_in(t1_15), + .Y15(t2_15), + .X16_in(t1_16), + .Y16(t2_16), + .X17_in(t1_17), + .Y17(t2_17), + .X18_in(t1_18), + .Y18(t2_18), + .X19_in(t1_19), + .Y19(t2_19), + .X20_in(t1_20), + .Y20(t2_20), + .X21_in(t1_21), + .Y21(t2_21), + .X22_in(t1_22), + .Y22(t2_22), + .X23_in(t1_23), + .Y23(t2_23), + .X24_in(t1_24), + .Y24(t2_24), + .X25_in(t1_25), + .Y25(t2_25), + .X26_in(t1_26), + .Y26(t2_26), + .X27_in(t1_27), + .Y27(t2_27), + .X28_in(t1_28), + .Y28(t2_28), + .X29_in(t1_29), + .Y29(t2_29), + .X30_in(t1_30), + .Y30(t2_30), + .X31_in(t1_31), + .Y31(t2_31), + .next_out(next_2) +); + +endmodule + +module codeBlock98050_18 ( + input clk, + input reset, + input next_in, + input [17:0] X0_in, + output [17:0] Y0, + input [17:0] X1_in, + output [17:0] Y1, + input [17:0] X2_in, + output [17:0] Y2, + input [17:0] X3_in, + output [17:0] Y3, + input [17:0] X4_in, + output [17:0] Y4, + input [17:0] X5_in, + output [17:0] Y5, + input [17:0] X6_in, + output [17:0] Y6, + input [17:0] X7_in, + output [17:0] Y7, + input [17:0] X8_in, + output [17:0] Y8, + input [17:0] X9_in, + output [17:0] Y9, + input [17:0] X10_in, + output [17:0] Y10, + input [17:0] X11_in, + output [17:0] Y11, + input [17:0] X12_in, + output [17:0] Y12, + input [17:0] X13_in, + output [17:0] Y13, + input [17:0] X14_in, + output [17:0] Y14, + input [17:0] X15_in, + output [17:0] Y15, + input [17:0] X16_in, + output [17:0] Y16, + input [17:0] X17_in, + output [17:0] Y17, + input [17:0] X18_in, + output [17:0] Y18, + input [17:0] X19_in, + output [17:0] Y19, + input [17:0] X20_in, + output [17:0] Y20, + input [17:0] X21_in, + output [17:0] Y21, + input [17:0] X22_in, + output [17:0] Y22, + input [17:0] X23_in, + output [17:0] Y23, + input [17:0] X24_in, + output [17:0] Y24, + input [17:0] X25_in, + output [17:0] Y25, + input [17:0] X26_in, + output [17:0] Y26, + input [17:0] X27_in, + output [17:0] Y27, + input [17:0] X28_in, + output [17:0] Y28, + input [17:0] X29_in, + output [17:0] Y29, + input [17:0] X30_in, + output [17:0] Y30, + input [17:0] X31_in, + output [17:0] Y31, + output next_out +); + +reg next; +reg [17:0] X0; +reg [17:0] X1; +reg [17:0] X2; +reg [17:0] X3; +reg [17:0] X4; +reg [17:0] X5; +reg [17:0] X6; +reg [17:0] X7; +reg [17:0] X8; +reg [17:0] X9; +reg [17:0] X10; +reg [17:0] X11; +reg [17:0] X12; +reg [17:0] X13; +reg [17:0] X14; +reg [17:0] X15; +reg [17:0] X16; +reg [17:0] X17; +reg [17:0] X18; +reg [17:0] X19; +reg [17:0] X20; +reg [17:0] X21; +reg [17:0] X22; +reg [17:0] X23; +reg [17:0] X24; +reg [17:0] X25; +reg [17:0] X26; +reg [17:0] X27; +reg [17:0] X28; +reg [17:0] X29; +reg [17:0] X30; +reg [17:0] X31; +shiftRegFIFO_5_1 shiftRegFIFO_5_1_inst_oparppsimb ( + .X(next), + .Y(next_out), + .reset(reset), + .clk(clk) +); +wire [17:0] a249; + wire [17:0] a250; + wire [17:0] a251; + wire [17:0] a252; + wire [17:0] a257; + wire [17:0] a258; + wire [17:0] a259; + wire [17:0] a260; + wire [17:0] a265; + wire [17:0] a266; + wire [17:0] a267; + wire [17:0] a268; + wire [17:0] a273; + wire [17:0] a274; + wire [17:0] a275; + wire [17:0] a276; + wire [17:0] a281; + wire [17:0] a282; + wire [17:0] a283; + wire [17:0] a284; + wire [17:0] a289; + wire [17:0] a290; + wire [17:0] a291; + wire [17:0] a292; + wire [17:0] a297; + wire [17:0] a298; + wire [17:0] a299; + wire [17:0] a300; + wire [17:0] a305; + wire [17:0] a306; + wire [17:0] a307; + wire [17:0] a308; + wire [17:0] t914; + wire [17:0] t915; + wire [17:0] t916; + wire [17:0] t917; + wire [17:0] t918; + wire [17:0] t919; + wire [17:0] t920; + wire [17:0] t921; + wire [17:0] t930; + wire [17:0] t931; + wire [17:0] t932; + wire [17:0] t933; + wire [17:0] t934; + wire [17:0] t935; + wire [17:0] t936; + wire [17:0] t937; + wire [17:0] t952; + wire [17:0] t953; + wire [17:0] t954; + wire [17:0] t955; + wire [17:0] t956; + wire [17:0] t957; + wire [17:0] t958; + wire [17:0] t959; + wire [17:0] t972; + wire [17:0] t973; + wire [17:0] t974; + wire [17:0] t975; + wire [17:0] t976; + wire [17:0] t977; + wire [17:0] t978; + wire [17:0] t979; + wire [17:0] t922; + wire [17:0] t923; + wire [17:0] t924; + wire [17:0] t925; + wire [17:0] t926; + wire [17:0] t927; + wire [17:0] t928; + wire [17:0] t929; + wire [17:0] t938; + wire [17:0] t939; + wire [17:0] t940; + wire [17:0] t941; + wire [17:0] t944; + wire [17:0] t945; + wire [17:0] t946; + wire [17:0] t947; + wire [17:0] t960; + wire [17:0] t961; + wire [17:0] t962; + wire [17:0] t963; + wire [17:0] t964; + wire [17:0] t965; + wire [17:0] t966; + wire [17:0] t967; + wire [17:0] t980; + wire [17:0] t981; + wire [17:0] t982; + wire [17:0] t983; + wire [17:0] t986; + wire [17:0] t987; + wire [17:0] t988; + wire [17:0] t989; + reg [17:0] tm24; + reg [17:0] tm27; + reg [17:0] tm30; + reg [17:0] tm33; + reg [17:0] tm36; + reg [17:0] tm39; + reg [17:0] tm42; + reg [17:0] tm45; + reg [17:0] tm48; + reg [17:0] tm51; + reg [17:0] tm54; + reg [17:0] tm57; + reg [17:0] tm60; + reg [17:0] tm63; + reg [17:0] tm66; + reg [17:0] tm69; + wire [17:0] a225; + wire [17:0] a226; + wire [17:0] a227; + wire [17:0] a228; + wire [17:0] a229; + wire [17:0] a230; + wire [17:0] a231; + wire [17:0] a232; + wire [17:0] a233; + wire [17:0] a234; + wire [17:0] a235; + wire [17:0] a236; + wire [17:0] a237; + wire [17:0] a238; + wire [17:0] a239; + wire [17:0] a240; + wire [17:0] a241; + wire [17:0] a242; + wire [17:0] a243; + wire [17:0] a244; + wire [17:0] a245; + wire [17:0] a246; + wire [17:0] a247; + wire [17:0] a248; + reg [17:0] tm25; + reg [17:0] tm28; + reg [17:0] tm31; + reg [17:0] tm34; + reg [17:0] tm37; + reg [17:0] tm40; + reg [17:0] tm43; + reg [17:0] tm46; + reg [17:0] tm49; + reg [17:0] tm52; + reg [17:0] tm55; + reg [17:0] tm58; + reg [17:0] tm61; + reg [17:0] tm64; + reg [17:0] tm67; + reg [17:0] tm70; + wire [17:0] t942; + wire [17:0] t943; + wire [17:0] t948; + wire [17:0] t949; + wire [17:0] t950; + wire [17:0] t951; + wire [17:0] t968; + wire [17:0] t969; + wire [17:0] t970; + wire [17:0] t971; + wire [17:0] t984; + wire [17:0] t985; + wire [17:0] t990; + wire [17:0] t991; + wire [17:0] t992; + wire [17:0] t993; + reg [17:0] tm26; + reg [17:0] tm29; + reg [17:0] tm32; + reg [17:0] tm35; + reg [17:0] tm38; + reg [17:0] tm41; + reg [17:0] tm44; + reg [17:0] tm47; + reg [17:0] tm50; + reg [17:0] tm53; + reg [17:0] tm56; + reg [17:0] tm59; + reg [17:0] tm62; + reg [17:0] tm65; + reg [17:0] tm68; + reg [17:0] tm71; + +wire [17:0] tm0; +assign tm0 = (18'hb505 >> (18-18)); +wire [17:0] tm2; +assign tm2 = (18'hec83 >> (18-18)); +wire [17:0] tm3; +assign tm3 = (18'h61f8 >> (18-18)); + +assign a249 = X0; + assign a250 = X16; + assign a251 = X1; + assign a252 = X17; + assign a257 = X8; + assign a258 = X24; + assign a259 = X9; + assign a260 = X25; + assign a265 = X2; + assign a266 = X18; + assign a267 = X3; + assign a268 = X19; + assign a273 = X10; + assign a274 = X26; + assign a275 = X11; + assign a276 = X27; + assign a281 = X4; + assign a282 = X20; + assign a283 = X5; + assign a284 = X21; + assign a289 = X12; + assign a290 = X28; + assign a291 = X13; + assign a292 = X29; + assign a297 = X6; + assign a298 = X22; + assign a299 = X7; + assign a300 = X23; + assign a305 = X14; + assign a306 = X30; + assign a307 = X15; + assign a308 = X31; + assign Y0 = tm26; + assign Y1 = tm29; + assign Y4 = tm32; + assign Y5 = tm35; + assign Y2 = tm38; + assign Y3 = tm41; + assign Y6 = tm44; + assign Y7 = tm47; + assign Y8 = tm50; + assign Y9 = tm53; + assign Y12 = t942; + assign Y13 = t943; + assign Y10 = t948; + assign Y11 = t949; + assign Y14 = t950; + assign Y15 = t951; + assign Y16 = tm56; + assign Y17 = tm59; + assign Y20 = tm62; + assign Y21 = tm65; + assign Y18 = t968; + assign Y19 = t969; + assign Y22 = (~(t970)+1'b1); + assign Y23 = t971; + assign Y24 = tm68; + assign Y25 = tm71; + assign Y28 = (~(t984)+1'b1); + assign Y29 = t985; + assign Y26 = t990; + assign Y27 = t991; + assign Y30 = t992; + assign Y31 = (~(t993)+1'b1); + +addfxp_18_1 add98062(.a(a249), .b(a250), .clk(clk), .q(t914)); + addfxp_18_1 add98077(.a(a251), .b(a252), .clk(clk), .q(t915)); + subfxp_18_1 sub98092(.a(a249), .b(a250), .clk(clk), .q(t916)); + subfxp_18_1 sub98107(.a(a251), .b(a252), .clk(clk), .q(t917)); + addfxp_18_1 add98122(.a(a257), .b(a258), .clk(clk), .q(t918)); + addfxp_18_1 add98137(.a(a259), .b(a260), .clk(clk), .q(t919)); + subfxp_18_1 sub98152(.a(a257), .b(a258), .clk(clk), .q(t920)); + subfxp_18_1 sub98167(.a(a259), .b(a260), .clk(clk), .q(t921)); + addfxp_18_1 add98270(.a(a265), .b(a266), .clk(clk), .q(t930)); + addfxp_18_1 add98285(.a(a267), .b(a268), .clk(clk), .q(t931)); + subfxp_18_1 sub98300(.a(a265), .b(a266), .clk(clk), .q(t932)); + subfxp_18_1 sub98315(.a(a267), .b(a268), .clk(clk), .q(t933)); + addfxp_18_1 add98330(.a(a273), .b(a274), .clk(clk), .q(t934)); + addfxp_18_1 add98345(.a(a275), .b(a276), .clk(clk), .q(t935)); + subfxp_18_1 sub98360(.a(a273), .b(a274), .clk(clk), .q(t936)); + subfxp_18_1 sub98375(.a(a275), .b(a276), .clk(clk), .q(t937)); + addfxp_18_1 add98590(.a(a281), .b(a282), .clk(clk), .q(t952)); + addfxp_18_1 add98605(.a(a283), .b(a284), .clk(clk), .q(t953)); + subfxp_18_1 sub98620(.a(a281), .b(a282), .clk(clk), .q(t954)); + subfxp_18_1 sub98635(.a(a283), .b(a284), .clk(clk), .q(t955)); + addfxp_18_1 add98650(.a(a289), .b(a290), .clk(clk), .q(t956)); + addfxp_18_1 add98665(.a(a291), .b(a292), .clk(clk), .q(t957)); + subfxp_18_1 sub98680(.a(a289), .b(a290), .clk(clk), .q(t958)); + subfxp_18_1 sub98695(.a(a291), .b(a292), .clk(clk), .q(t959)); + addfxp_18_1 add98856(.a(a297), .b(a298), .clk(clk), .q(t972)); + addfxp_18_1 add98871(.a(a299), .b(a300), .clk(clk), .q(t973)); + subfxp_18_1 sub98886(.a(a297), .b(a298), .clk(clk), .q(t974)); + subfxp_18_1 sub98901(.a(a299), .b(a300), .clk(clk), .q(t975)); + addfxp_18_1 add98916(.a(a305), .b(a306), .clk(clk), .q(t976)); + addfxp_18_1 add98931(.a(a307), .b(a308), .clk(clk), .q(t977)); + subfxp_18_1 sub98946(.a(a305), .b(a306), .clk(clk), .q(t978)); + subfxp_18_1 sub98961(.a(a307), .b(a308), .clk(clk), .q(t979)); + addfxp_18_1 add98174(.a(t914), .b(t918), .clk(clk), .q(t922)); + addfxp_18_1 add98181(.a(t915), .b(t919), .clk(clk), .q(t923)); + subfxp_18_1 sub98188(.a(t914), .b(t918), .clk(clk), .q(t924)); + subfxp_18_1 sub98195(.a(t915), .b(t919), .clk(clk), .q(t925)); + subfxp_18_1 sub98218(.a(t916), .b(t921), .clk(clk), .q(t926)); + addfxp_18_1 add98225(.a(t917), .b(t920), .clk(clk), .q(t927)); + addfxp_18_1 add98232(.a(t916), .b(t921), .clk(clk), .q(t928)); + subfxp_18_1 sub98239(.a(t917), .b(t920), .clk(clk), .q(t929)); + addfxp_18_1 add98382(.a(t930), .b(t934), .clk(clk), .q(t938)); + addfxp_18_1 add98389(.a(t931), .b(t935), .clk(clk), .q(t939)); + subfxp_18_1 sub98396(.a(t930), .b(t934), .clk(clk), .q(t940)); + subfxp_18_1 sub98403(.a(t931), .b(t935), .clk(clk), .q(t941)); + subfxp_18_1 sub98454(.a(t932), .b(t937), .clk(clk), .q(t944)); + addfxp_18_1 add98461(.a(t933), .b(t936), .clk(clk), .q(t945)); + addfxp_18_1 add98468(.a(t932), .b(t937), .clk(clk), .q(t946)); + subfxp_18_1 sub98475(.a(t933), .b(t936), .clk(clk), .q(t947)); + addfxp_18_1 add98702(.a(t952), .b(t956), .clk(clk), .q(t960)); + addfxp_18_1 add98709(.a(t953), .b(t957), .clk(clk), .q(t961)); + subfxp_18_1 sub98716(.a(t952), .b(t956), .clk(clk), .q(t962)); + subfxp_18_1 sub98723(.a(t953), .b(t957), .clk(clk), .q(t963)); + subfxp_18_1 sub98747(.a(t954), .b(t959), .clk(clk), .q(t964)); + addfxp_18_1 add98754(.a(t955), .b(t958), .clk(clk), .q(t965)); + addfxp_18_1 add98761(.a(t954), .b(t959), .clk(clk), .q(t966)); + subfxp_18_1 sub98768(.a(t955), .b(t958), .clk(clk), .q(t967)); + addfxp_18_1 add98968(.a(t972), .b(t976), .clk(clk), .q(t980)); + addfxp_18_1 add98975(.a(t973), .b(t977), .clk(clk), .q(t981)); + subfxp_18_1 sub98982(.a(t972), .b(t976), .clk(clk), .q(t982)); + subfxp_18_1 sub98989(.a(t973), .b(t977), .clk(clk), .q(t983)); + subfxp_18_1 sub99041(.a(t974), .b(t979), .clk(clk), .q(t986)); + addfxp_18_1 add99048(.a(t975), .b(t978), .clk(clk), .q(t987)); + addfxp_18_1 add99055(.a(t974), .b(t979), .clk(clk), .q(t988)); + subfxp_18_1 sub99062(.a(t975), .b(t978), .clk(clk), .q(t989)); + +multfix_alt_dsp_18 m88566(.ax(tm0), .ay(t940), .bx(tm0), .by(t941), .clk(clk), .a_q_sc(a225), .a_q_unsc(), .b_q_sc(a226), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88570(.ax(tm2), .ay(t944), .bx(tm3), .by(t945), .clk(clk), .a_q_sc(a227), .a_q_unsc(), .b_q_sc(a228), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88572(.ax(tm3), .ay(t944), .bx(tm2), .by(t945), .clk(clk), .a_q_sc(a229), .a_q_unsc(), .b_q_sc(a230), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88574(.ax(tm3), .ay(t946), .bx(tm2), .by(t947), .clk(clk), .a_q_sc(a231), .a_q_unsc(), .b_q_sc(a232), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88576(.ax(tm2), .ay(t946), .bx(tm3), .by(t947), .clk(clk), .a_q_sc(a233), .a_q_unsc(), .b_q_sc(a234), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88578(.ax(tm0), .ay(t964), .bx(tm0), .by(t965), .clk(clk), .a_q_sc(a235), .a_q_unsc(), .b_q_sc(a236), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88580(.ax(tm0), .ay(t966), .bx(tm0), .by(t967), .clk(clk), .a_q_sc(a237), .a_q_unsc(), .b_q_sc(a238), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88582(.ax(tm0), .ay(t982), .bx(tm0), .by(t983), .clk(clk), .a_q_sc(a239), .a_q_unsc(), .b_q_sc(a240), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88584(.ax(tm3), .ay(t986), .bx(tm2), .by(t987), .clk(clk), .a_q_sc(a241), .a_q_unsc(), .b_q_sc(a242), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88586(.ax(tm2), .ay(t986), .bx(tm3), .by(t987), .clk(clk), .a_q_sc(a243), .a_q_unsc(), .b_q_sc(a244), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88588(.ax(tm3), .ay(t989), .bx(tm2), .by(t988), .clk(clk), .a_q_sc(a245), .a_q_unsc(), .b_q_sc(a246), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88590(.ax(tm3), .ay(t988), .bx(tm2), .by(t989), .clk(clk), .a_q_sc(a247), .a_q_unsc(), .b_q_sc(a248), .b_q_unsc(), .rst(reset)); + +subfxp_18_1 sub98424(.a(a225), .b(a226), .clk(clk), .q(t942)); + addfxp_18_1 add98431(.a(a225), .b(a226), .clk(clk), .q(t943)); + subfxp_18_1 sub98496(.a(a227), .b(a228), .clk(clk), .q(t948)); + addfxp_18_1 add98517(.a(a229), .b(a230), .clk(clk), .q(t949)); + subfxp_18_1 sub98538(.a(a231), .b(a232), .clk(clk), .q(t950)); + addfxp_18_1 add98559(.a(a233), .b(a234), .clk(clk), .q(t951)); + subfxp_18_1 sub98789(.a(a235), .b(a236), .clk(clk), .q(t968)); + addfxp_18_1 add98796(.a(a235), .b(a236), .clk(clk), .q(t969)); + addfxp_18_1 add98817(.a(a237), .b(a238), .clk(clk), .q(t970)); + subfxp_18_1 sub98824(.a(a237), .b(a238), .clk(clk), .q(t971)); + addfxp_18_1 add99010(.a(a239), .b(a240), .clk(clk), .q(t984)); + subfxp_18_1 sub99017(.a(a239), .b(a240), .clk(clk), .q(t985)); + subfxp_18_1 sub99083(.a(a241), .b(a242), .clk(clk), .q(t990)); + addfxp_18_1 add99104(.a(a243), .b(a244), .clk(clk), .q(t991)); + subfxp_18_1 sub99125(.a(a245), .b(a246), .clk(clk), .q(t992)); + addfxp_18_1 add99146(.a(a247), .b(a248), .clk(clk), .q(t993)); + +always @(posedge clk) begin + if (reset == 1) begin + next <= 1'b0; + end else begin + X0 <= X0_in; + X1 <= X1_in; + X2 <= X2_in; + X3 <= X3_in; + X4 <= X4_in; + X5 <= X5_in; + X6 <= X6_in; + X7 <= X7_in; + X8 <= X8_in; + X9 <= X9_in; + X10 <= X10_in; + X11 <= X11_in; + X12 <= X12_in; + X13 <= X13_in; + X14 <= X14_in; + X15 <= X15_in; + X16 <= X16_in; + X17 <= X17_in; + X18 <= X18_in; + X19 <= X19_in; + X20 <= X20_in; + X21 <= X21_in; + X22 <= X22_in; + X23 <= X23_in; + X24 <= X24_in; + X25 <= X25_in; + X26 <= X26_in; + X27 <= X27_in; + X28 <= X28_in; + X29 <= X29_in; + X30 <= X30_in; + X31 <= X31_in; + next <= next_in; + tm24 <= t922; + tm27 <= t923; + tm30 <= t924; + tm33 <= t925; + tm36 <= t926; + tm39 <= t927; + tm42 <= t928; + tm45 <= t929; + tm48 <= t938; + tm51 <= t939; + tm54 <= t960; + tm57 <= t961; + tm60 <= (~(t963)+1'b1); + tm63 <= t962; + tm66 <= t980; + tm69 <= t981; + tm25 <= tm24; + tm28 <= tm27; + tm31 <= tm30; + tm34 <= tm33; + tm37 <= tm36; + tm40 <= tm39; + tm43 <= tm42; + tm46 <= tm45; + tm49 <= tm48; + tm52 <= tm51; + tm55 <= tm54; + tm58 <= tm57; + tm61 <= tm60; + tm64 <= tm63; + tm67 <= tm66; + tm70 <= tm69; + tm26 <= tm25; + tm29 <= tm28; + tm32 <= tm31; + tm35 <= tm34; + tm38 <= tm37; + tm41 <= tm40; + tm44 <= tm43; + tm47 <= tm46; + tm50 <= tm49; + tm53 <= tm52; + tm56 <= tm55; + tm59 <= tm58; + tm62 <= tm61; + tm65 <= tm64; + tm68 <= tm67; + tm71 <= tm70; + end +end + +endmodule + +module codeBlock99168_18 ( + input clk, + input reset, + input next_in, + input [17:0] X0_in, + output [17:0] Y0, + input [17:0] X1_in, + output [17:0] Y1, + input [17:0] X2_in, + output [17:0] Y2, + input [17:0] X3_in, + output [17:0] Y3, + input [17:0] X4_in, + output [17:0] Y4, + input [17:0] X5_in, + output [17:0] Y5, + input [17:0] X6_in, + output [17:0] Y6, + input [17:0] X7_in, + output [17:0] Y7, + input [17:0] X8_in, + output [17:0] Y8, + input [17:0] X9_in, + output [17:0] Y9, + input [17:0] X10_in, + output [17:0] Y10, + input [17:0] X11_in, + output [17:0] Y11, + input [17:0] X12_in, + output [17:0] Y12, + input [17:0] X13_in, + output [17:0] Y13, + input [17:0] X14_in, + output [17:0] Y14, + input [17:0] X15_in, + output [17:0] Y15, + input [17:0] X16_in, + output [17:0] Y16, + input [17:0] X17_in, + output [17:0] Y17, + input [17:0] X18_in, + output [17:0] Y18, + input [17:0] X19_in, + output [17:0] Y19, + input [17:0] X20_in, + output [17:0] Y20, + input [17:0] X21_in, + output [17:0] Y21, + input [17:0] X22_in, + output [17:0] Y22, + input [17:0] X23_in, + output [17:0] Y23, + input [17:0] X24_in, + output [17:0] Y24, + input [17:0] X25_in, + output [17:0] Y25, + input [17:0] X26_in, + output [17:0] Y26, + input [17:0] X27_in, + output [17:0] Y27, + input [17:0] X28_in, + output [17:0] Y28, + input [17:0] X29_in, + output [17:0] Y29, + input [17:0] X30_in, + output [17:0] Y30, + input [17:0] X31_in, + output [17:0] Y31, + output next_out +); + +reg next; +reg [17:0] X0; +reg [17:0] X1; +reg [17:0] X2; +reg [17:0] X3; +reg [17:0] X4; +reg [17:0] X5; +reg [17:0] X6; +reg [17:0] X7; +reg [17:0] X8; +reg [17:0] X9; +reg [17:0] X10; +reg [17:0] X11; +reg [17:0] X12; +reg [17:0] X13; +reg [17:0] X14; +reg [17:0] X15; +reg [17:0] X16; +reg [17:0] X17; +reg [17:0] X18; +reg [17:0] X19; +reg [17:0] X20; +reg [17:0] X21; +reg [17:0] X22; +reg [17:0] X23; +reg [17:0] X24; +reg [17:0] X25; +reg [17:0] X26; +reg [17:0] X27; +reg [17:0] X28; +reg [17:0] X29; +reg [17:0] X30; +reg [17:0] X31; +shiftRegFIFO_2_1 shiftRegFIFO_2_1_inst_sbuimtstsu ( + .X(next), + .Y(next_out), + .reset(reset), + .clk(clk) +); +wire [17:0] a65; + wire [17:0] a66; + wire [17:0] a67; + wire [17:0] a68; + wire [17:0] a73; + wire [17:0] a74; + wire [17:0] a75; + wire [17:0] a76; + wire [17:0] a81; + wire [17:0] a82; + wire [17:0] a83; + wire [17:0] a84; + wire [17:0] a89; + wire [17:0] a90; + wire [17:0] a91; + wire [17:0] a92; + wire [17:0] a97; + wire [17:0] a98; + wire [17:0] a99; + wire [17:0] a100; + wire [17:0] a105; + wire [17:0] a106; + wire [17:0] a107; + wire [17:0] a108; + wire [17:0] a113; + wire [17:0] a114; + wire [17:0] a115; + wire [17:0] a116; + wire [17:0] a121; + wire [17:0] a122; + wire [17:0] a123; + wire [17:0] a124; + wire [17:0] t402; + wire [17:0] t403; + wire [17:0] t404; + wire [17:0] t405; + wire [17:0] t406; + wire [17:0] t407; + wire [17:0] t408; + wire [17:0] t409; + wire [17:0] t418; + wire [17:0] t419; + wire [17:0] t420; + wire [17:0] t421; + wire [17:0] t422; + wire [17:0] t423; + wire [17:0] t424; + wire [17:0] t425; + wire [17:0] t434; + wire [17:0] t435; + wire [17:0] t436; + wire [17:0] t437; + wire [17:0] t438; + wire [17:0] t439; + wire [17:0] t440; + wire [17:0] t441; + wire [17:0] t450; + wire [17:0] t451; + wire [17:0] t452; + wire [17:0] t453; + wire [17:0] t454; + wire [17:0] t455; + wire [17:0] t456; + wire [17:0] t457; + wire [17:0] t410; + wire [17:0] t411; + wire [17:0] t412; + wire [17:0] t413; + wire [17:0] t414; + wire [17:0] t415; + wire [17:0] t416; + wire [17:0] t417; + wire [17:0] t426; + wire [17:0] t427; + wire [17:0] t428; + wire [17:0] t429; + wire [17:0] t430; + wire [17:0] t431; + wire [17:0] t432; + wire [17:0] t433; + wire [17:0] t442; + wire [17:0] t443; + wire [17:0] t444; + wire [17:0] t445; + wire [17:0] t446; + wire [17:0] t447; + wire [17:0] t448; + wire [17:0] t449; + wire [17:0] t458; + wire [17:0] t459; + wire [17:0] t460; + wire [17:0] t461; + wire [17:0] t462; + wire [17:0] t463; + wire [17:0] t464; + wire [17:0] t465; + +assign a65 = X0; + assign a66 = X16; + assign a67 = X1; + assign a68 = X17; + assign a73 = X8; + assign a74 = X24; + assign a75 = X9; + assign a76 = X25; + assign a81 = X2; + assign a82 = X18; + assign a83 = X3; + assign a84 = X19; + assign a89 = X10; + assign a90 = X26; + assign a91 = X11; + assign a92 = X27; + assign a97 = X4; + assign a98 = X20; + assign a99 = X5; + assign a100 = X21; + assign a105 = X12; + assign a106 = X28; + assign a107 = X13; + assign a108 = X29; + assign a113 = X6; + assign a114 = X22; + assign a115 = X7; + assign a116 = X23; + assign a121 = X14; + assign a122 = X30; + assign a123 = X15; + assign a124 = X31; + assign Y0 = t410; + assign Y1 = t411; + assign Y16 = t412; + assign Y17 = t413; + assign Y8 = t414; + assign Y9 = t415; + assign Y24 = t416; + assign Y25 = t417; + assign Y2 = t426; + assign Y3 = t427; + assign Y18 = t428; + assign Y19 = t429; + assign Y10 = t430; + assign Y11 = t431; + assign Y26 = t432; + assign Y27 = t433; + assign Y4 = t442; + assign Y5 = t443; + assign Y20 = t444; + assign Y21 = t445; + assign Y12 = t446; + assign Y13 = t447; + assign Y28 = t448; + assign Y29 = t449; + assign Y6 = t458; + assign Y7 = t459; + assign Y22 = t460; + assign Y23 = t461; + assign Y14 = t462; + assign Y15 = t463; + assign Y30 = t464; + assign Y31 = t465; + +addfxp_18_1 add99180(.a(a65), .b(a66), .clk(clk), .q(t402)); + addfxp_18_1 add99195(.a(a67), .b(a68), .clk(clk), .q(t403)); + subfxp_18_1 sub99210(.a(a65), .b(a66), .clk(clk), .q(t404)); + subfxp_18_1 sub99225(.a(a67), .b(a68), .clk(clk), .q(t405)); + addfxp_18_1 add99240(.a(a73), .b(a74), .clk(clk), .q(t406)); + addfxp_18_1 add99255(.a(a75), .b(a76), .clk(clk), .q(t407)); + subfxp_18_1 sub99270(.a(a73), .b(a74), .clk(clk), .q(t408)); + subfxp_18_1 sub99285(.a(a75), .b(a76), .clk(clk), .q(t409)); + addfxp_18_1 add99388(.a(a81), .b(a82), .clk(clk), .q(t418)); + addfxp_18_1 add99403(.a(a83), .b(a84), .clk(clk), .q(t419)); + subfxp_18_1 sub99418(.a(a81), .b(a82), .clk(clk), .q(t420)); + subfxp_18_1 sub99433(.a(a83), .b(a84), .clk(clk), .q(t421)); + addfxp_18_1 add99448(.a(a89), .b(a90), .clk(clk), .q(t422)); + addfxp_18_1 add99463(.a(a91), .b(a92), .clk(clk), .q(t423)); + subfxp_18_1 sub99478(.a(a89), .b(a90), .clk(clk), .q(t424)); + subfxp_18_1 sub99493(.a(a91), .b(a92), .clk(clk), .q(t425)); + addfxp_18_1 add99596(.a(a97), .b(a98), .clk(clk), .q(t434)); + addfxp_18_1 add99611(.a(a99), .b(a100), .clk(clk), .q(t435)); + subfxp_18_1 sub99626(.a(a97), .b(a98), .clk(clk), .q(t436)); + subfxp_18_1 sub99641(.a(a99), .b(a100), .clk(clk), .q(t437)); + addfxp_18_1 add99656(.a(a105), .b(a106), .clk(clk), .q(t438)); + addfxp_18_1 add99671(.a(a107), .b(a108), .clk(clk), .q(t439)); + subfxp_18_1 sub99686(.a(a105), .b(a106), .clk(clk), .q(t440)); + subfxp_18_1 sub99701(.a(a107), .b(a108), .clk(clk), .q(t441)); + addfxp_18_1 add99804(.a(a113), .b(a114), .clk(clk), .q(t450)); + addfxp_18_1 add99819(.a(a115), .b(a116), .clk(clk), .q(t451)); + subfxp_18_1 sub99834(.a(a113), .b(a114), .clk(clk), .q(t452)); + subfxp_18_1 sub99849(.a(a115), .b(a116), .clk(clk), .q(t453)); + addfxp_18_1 add99864(.a(a121), .b(a122), .clk(clk), .q(t454)); + addfxp_18_1 add99879(.a(a123), .b(a124), .clk(clk), .q(t455)); + subfxp_18_1 sub99894(.a(a121), .b(a122), .clk(clk), .q(t456)); + subfxp_18_1 sub99909(.a(a123), .b(a124), .clk(clk), .q(t457)); + addfxp_18_1 add99292(.a(t402), .b(t406), .clk(clk), .q(t410)); + addfxp_18_1 add99299(.a(t403), .b(t407), .clk(clk), .q(t411)); + subfxp_18_1 sub99306(.a(t402), .b(t406), .clk(clk), .q(t412)); + subfxp_18_1 sub99313(.a(t403), .b(t407), .clk(clk), .q(t413)); + subfxp_18_1 sub99336(.a(t404), .b(t409), .clk(clk), .q(t414)); + addfxp_18_1 add99343(.a(t405), .b(t408), .clk(clk), .q(t415)); + addfxp_18_1 add99350(.a(t404), .b(t409), .clk(clk), .q(t416)); + subfxp_18_1 sub99357(.a(t405), .b(t408), .clk(clk), .q(t417)); + addfxp_18_1 add99500(.a(t418), .b(t422), .clk(clk), .q(t426)); + addfxp_18_1 add99507(.a(t419), .b(t423), .clk(clk), .q(t427)); + subfxp_18_1 sub99514(.a(t418), .b(t422), .clk(clk), .q(t428)); + subfxp_18_1 sub99521(.a(t419), .b(t423), .clk(clk), .q(t429)); + subfxp_18_1 sub99544(.a(t420), .b(t425), .clk(clk), .q(t430)); + addfxp_18_1 add99551(.a(t421), .b(t424), .clk(clk), .q(t431)); + addfxp_18_1 add99558(.a(t420), .b(t425), .clk(clk), .q(t432)); + subfxp_18_1 sub99565(.a(t421), .b(t424), .clk(clk), .q(t433)); + addfxp_18_1 add99708(.a(t434), .b(t438), .clk(clk), .q(t442)); + addfxp_18_1 add99715(.a(t435), .b(t439), .clk(clk), .q(t443)); + subfxp_18_1 sub99722(.a(t434), .b(t438), .clk(clk), .q(t444)); + subfxp_18_1 sub99729(.a(t435), .b(t439), .clk(clk), .q(t445)); + subfxp_18_1 sub99752(.a(t436), .b(t441), .clk(clk), .q(t446)); + addfxp_18_1 add99759(.a(t437), .b(t440), .clk(clk), .q(t447)); + addfxp_18_1 add99766(.a(t436), .b(t441), .clk(clk), .q(t448)); + subfxp_18_1 sub99773(.a(t437), .b(t440), .clk(clk), .q(t449)); + addfxp_18_1 add99916(.a(t450), .b(t454), .clk(clk), .q(t458)); + addfxp_18_1 add99923(.a(t451), .b(t455), .clk(clk), .q(t459)); + subfxp_18_1 sub99930(.a(t450), .b(t454), .clk(clk), .q(t460)); + subfxp_18_1 sub99937(.a(t451), .b(t455), .clk(clk), .q(t461)); + subfxp_18_1 sub99960(.a(t452), .b(t457), .clk(clk), .q(t462)); + addfxp_18_1 add99967(.a(t453), .b(t456), .clk(clk), .q(t463)); + addfxp_18_1 add99974(.a(t452), .b(t457), .clk(clk), .q(t464)); + subfxp_18_1 sub99981(.a(t453), .b(t456), .clk(clk), .q(t465)); + +always @(posedge clk) begin + if (reset == 1) begin + next <= 1'b0; + end else begin + X0 <= X0_in; + X1 <= X1_in; + X2 <= X2_in; + X3 <= X3_in; + X4 <= X4_in; + X5 <= X5_in; + X6 <= X6_in; + X7 <= X7_in; + X8 <= X8_in; + X9 <= X9_in; + X10 <= X10_in; + X11 <= X11_in; + X12 <= X12_in; + X13 <= X13_in; + X14 <= X14_in; + X15 <= X15_in; + X16 <= X16_in; + X17 <= X17_in; + X18 <= X18_in; + X19 <= X19_in; + X20 <= X20_in; + X21 <= X21_in; + X22 <= X22_in; + X23 <= X23_in; + X24 <= X24_in; + X25 <= X25_in; + X26 <= X26_in; + X27 <= X27_in; + X28 <= X28_in; + X29 <= X29_in; + X30 <= X30_in; + X31 <= X31_in; + next <= next_in; + end +end + +endmodule + +module stage2_parameter_buffer_18_2_16_64 ( + input clk, + input reset, + input [287:0] wdata +, input [6:0] wen, + output [17:0] o_Wic_0, + output [17:0] o_bi_0, + output [17:0] o_Wfc_0, + output [17:0] o_bf_0, + output [17:0] o_Woc_0, + output [17:0] o_bo_0, + output [17:0] o_bc_0, + output [17:0] o_Wic_1, + output [17:0] o_bi_1, + output [17:0] o_Wfc_1, + output [17:0] o_bf_1, + output [17:0] o_Woc_1, + output [17:0] o_bo_1, + output [17:0] o_bc_1, + output [17:0] o_Wic_2, + output [17:0] o_bi_2, + output [17:0] o_Wfc_2, + output [17:0] o_bf_2, + output [17:0] o_Woc_2, + output [17:0] o_bo_2, + output [17:0] o_bc_2, + output [17:0] o_Wic_3, + output [17:0] o_bi_3, + output [17:0] o_Wfc_3, + output [17:0] o_bf_3, + output [17:0] o_Woc_3, + output [17:0] o_bo_3, + output [17:0] o_bc_3, + output [17:0] o_Wic_4, + output [17:0] o_bi_4, + output [17:0] o_Wfc_4, + output [17:0] o_bf_4, + output [17:0] o_Woc_4, + output [17:0] o_bo_4, + output [17:0] o_bc_4, + output [17:0] o_Wic_5, + output [17:0] o_bi_5, + output [17:0] o_Wfc_5, + output [17:0] o_bf_5, + output [17:0] o_Woc_5, + output [17:0] o_bo_5, + output [17:0] o_bc_5, + output [17:0] o_Wic_6, + output [17:0] o_bi_6, + output [17:0] o_Wfc_6, + output [17:0] o_bf_6, + output [17:0] o_Woc_6, + output [17:0] o_bo_6, + output [17:0] o_bc_6, + output [17:0] o_Wic_7, + output [17:0] o_bi_7, + output [17:0] o_Wfc_7, + output [17:0] o_bf_7, + output [17:0] o_Woc_7, + output [17:0] o_bo_7, + output [17:0] o_bc_7, + output [17:0] o_Wic_8, + output [17:0] o_bi_8, + output [17:0] o_Wfc_8, + output [17:0] o_bf_8, + output [17:0] o_Woc_8, + output [17:0] o_bo_8, + output [17:0] o_bc_8, + output [17:0] o_Wic_9, + output [17:0] o_bi_9, + output [17:0] o_Wfc_9, + output [17:0] o_bf_9, + output [17:0] o_Woc_9, + output [17:0] o_bo_9, + output [17:0] o_bc_9, + output [17:0] o_Wic_10, + output [17:0] o_bi_10, + output [17:0] o_Wfc_10, + output [17:0] o_bf_10, + output [17:0] o_Woc_10, + output [17:0] o_bo_10, + output [17:0] o_bc_10, + output [17:0] o_Wic_11, + output [17:0] o_bi_11, + output [17:0] o_Wfc_11, + output [17:0] o_bf_11, + output [17:0] o_Woc_11, + output [17:0] o_bo_11, + output [17:0] o_bc_11, + output [17:0] o_Wic_12, + output [17:0] o_bi_12, + output [17:0] o_Wfc_12, + output [17:0] o_bf_12, + output [17:0] o_Woc_12, + output [17:0] o_bo_12, + output [17:0] o_bc_12, + output [17:0] o_Wic_13, + output [17:0] o_bi_13, + output [17:0] o_Wfc_13, + output [17:0] o_bf_13, + output [17:0] o_Woc_13, + output [17:0] o_bo_13, + output [17:0] o_bc_13, + output [17:0] o_Wic_14, + output [17:0] o_bi_14, + output [17:0] o_Wfc_14, + output [17:0] o_bf_14, + output [17:0] o_Woc_14, + output [17:0] o_bo_14, + output [17:0] o_bc_14, + output [17:0] o_Wic_15, + output [17:0] o_bi_15, + output [17:0] o_Wfc_15, + output [17:0] o_bf_15, + output [17:0] o_Woc_15, + output [17:0] o_bo_15, + output [17:0] o_bc_15, + output [17:0] o_Wic_16, + output [17:0] o_bi_16, + output [17:0] o_Wfc_16, + output [17:0] o_bf_16, + output [17:0] o_Woc_16, + output [17:0] o_bo_16, + output [17:0] o_bc_16, + output [17:0] o_Wic_17, + output [17:0] o_bi_17, + output [17:0] o_Wfc_17, + output [17:0] o_bf_17, + output [17:0] o_Woc_17, + output [17:0] o_bo_17, + output [17:0] o_bc_17, + output [17:0] o_Wic_18, + output [17:0] o_bi_18, + output [17:0] o_Wfc_18, + output [17:0] o_bf_18, + output [17:0] o_Woc_18, + output [17:0] o_bo_18, + output [17:0] o_bc_18, + output [17:0] o_Wic_19, + output [17:0] o_bi_19, + output [17:0] o_Wfc_19, + output [17:0] o_bf_19, + output [17:0] o_Woc_19, + output [17:0] o_bo_19, + output [17:0] o_bc_19, + output [17:0] o_Wic_20, + output [17:0] o_bi_20, + output [17:0] o_Wfc_20, + output [17:0] o_bf_20, + output [17:0] o_Woc_20, + output [17:0] o_bo_20, + output [17:0] o_bc_20, + output [17:0] o_Wic_21, + output [17:0] o_bi_21, + output [17:0] o_Wfc_21, + output [17:0] o_bf_21, + output [17:0] o_Woc_21, + output [17:0] o_bo_21, + output [17:0] o_bc_21, + output [17:0] o_Wic_22, + output [17:0] o_bi_22, + output [17:0] o_Wfc_22, + output [17:0] o_bf_22, + output [17:0] o_Woc_22, + output [17:0] o_bo_22, + output [17:0] o_bc_22, + output [17:0] o_Wic_23, + output [17:0] o_bi_23, + output [17:0] o_Wfc_23, + output [17:0] o_bf_23, + output [17:0] o_Woc_23, + output [17:0] o_bo_23, + output [17:0] o_bc_23, + output [17:0] o_Wic_24, + output [17:0] o_bi_24, + output [17:0] o_Wfc_24, + output [17:0] o_bf_24, + output [17:0] o_Woc_24, + output [17:0] o_bo_24, + output [17:0] o_bc_24, + output [17:0] o_Wic_25, + output [17:0] o_bi_25, + output [17:0] o_Wfc_25, + output [17:0] o_bf_25, + output [17:0] o_Woc_25, + output [17:0] o_bo_25, + output [17:0] o_bc_25, + output [17:0] o_Wic_26, + output [17:0] o_bi_26, + output [17:0] o_Wfc_26, + output [17:0] o_bf_26, + output [17:0] o_Woc_26, + output [17:0] o_bo_26, + output [17:0] o_bc_26, + output [17:0] o_Wic_27, + output [17:0] o_bi_27, + output [17:0] o_Wfc_27, + output [17:0] o_bf_27, + output [17:0] o_Woc_27, + output [17:0] o_bo_27, + output [17:0] o_bc_27, + output [17:0] o_Wic_28, + output [17:0] o_bi_28, + output [17:0] o_Wfc_28, + output [17:0] o_bf_28, + output [17:0] o_Woc_28, + output [17:0] o_bo_28, + output [17:0] o_bc_28, + output [17:0] o_Wic_29, + output [17:0] o_bi_29, + output [17:0] o_Wfc_29, + output [17:0] o_bf_29, + output [17:0] o_Woc_29, + output [17:0] o_bo_29, + output [17:0] o_bc_29, + output [17:0] o_Wic_30, + output [17:0] o_bi_30, + output [17:0] o_Wfc_30, + output [17:0] o_bf_30, + output [17:0] o_Woc_30, + output [17:0] o_bo_30, + output [17:0] o_bc_30, + output [17:0] o_Wic_31, + output [17:0] o_bi_31, + output [17:0] o_Wfc_31, + output [17:0] o_bf_31, + output [17:0] o_Woc_31, + output [17:0] o_bo_31, + output [17:0] o_bc_31, + input incr_index +); + +wire [17:0] Wic_0_0; +wire [17:0] bi_0_0; +wire [17:0] Wfc_0_0; +wire [17:0] bf_0_0; +wire [17:0] Woc_0_0; +wire [17:0] bo_0_0; +wire [17:0] bc_0_0; +wire [17:0] Wic_0_1; +wire [17:0] bi_0_1; +wire [17:0] Wfc_0_1; +wire [17:0] bf_0_1; +wire [17:0] Woc_0_1; +wire [17:0] bo_0_1; +wire [17:0] bc_0_1; +wire [17:0] Wic_0_2; +wire [17:0] bi_0_2; +wire [17:0] Wfc_0_2; +wire [17:0] bf_0_2; +wire [17:0] Woc_0_2; +wire [17:0] bo_0_2; +wire [17:0] bc_0_2; +wire [17:0] Wic_0_3; +wire [17:0] bi_0_3; +wire [17:0] Wfc_0_3; +wire [17:0] bf_0_3; +wire [17:0] Woc_0_3; +wire [17:0] bo_0_3; +wire [17:0] bc_0_3; +wire [17:0] Wic_0_4; +wire [17:0] bi_0_4; +wire [17:0] Wfc_0_4; +wire [17:0] bf_0_4; +wire [17:0] Woc_0_4; +wire [17:0] bo_0_4; +wire [17:0] bc_0_4; +wire [17:0] Wic_0_5; +wire [17:0] bi_0_5; +wire [17:0] Wfc_0_5; +wire [17:0] bf_0_5; +wire [17:0] Woc_0_5; +wire [17:0] bo_0_5; +wire [17:0] bc_0_5; +wire [17:0] Wic_0_6; +wire [17:0] bi_0_6; +wire [17:0] Wfc_0_6; +wire [17:0] bf_0_6; +wire [17:0] Woc_0_6; +wire [17:0] bo_0_6; +wire [17:0] bc_0_6; +wire [17:0] Wic_0_7; +wire [17:0] bi_0_7; +wire [17:0] Wfc_0_7; +wire [17:0] bf_0_7; +wire [17:0] Woc_0_7; +wire [17:0] bo_0_7; +wire [17:0] bc_0_7; +wire [17:0] Wic_0_8; +wire [17:0] bi_0_8; +wire [17:0] Wfc_0_8; +wire [17:0] bf_0_8; +wire [17:0] Woc_0_8; +wire [17:0] bo_0_8; +wire [17:0] bc_0_8; +wire [17:0] Wic_0_9; +wire [17:0] bi_0_9; +wire [17:0] Wfc_0_9; +wire [17:0] bf_0_9; +wire [17:0] Woc_0_9; +wire [17:0] bo_0_9; +wire [17:0] bc_0_9; +wire [17:0] Wic_0_10; +wire [17:0] bi_0_10; +wire [17:0] Wfc_0_10; +wire [17:0] bf_0_10; +wire [17:0] Woc_0_10; +wire [17:0] bo_0_10; +wire [17:0] bc_0_10; +wire [17:0] Wic_0_11; +wire [17:0] bi_0_11; +wire [17:0] Wfc_0_11; +wire [17:0] bf_0_11; +wire [17:0] Woc_0_11; +wire [17:0] bo_0_11; +wire [17:0] bc_0_11; +wire [17:0] Wic_0_12; +wire [17:0] bi_0_12; +wire [17:0] Wfc_0_12; +wire [17:0] bf_0_12; +wire [17:0] Woc_0_12; +wire [17:0] bo_0_12; +wire [17:0] bc_0_12; +wire [17:0] Wic_0_13; +wire [17:0] bi_0_13; +wire [17:0] Wfc_0_13; +wire [17:0] bf_0_13; +wire [17:0] Woc_0_13; +wire [17:0] bo_0_13; +wire [17:0] bc_0_13; +wire [17:0] Wic_0_14; +wire [17:0] bi_0_14; +wire [17:0] Wfc_0_14; +wire [17:0] bf_0_14; +wire [17:0] Woc_0_14; +wire [17:0] bo_0_14; +wire [17:0] bc_0_14; +wire [17:0] Wic_0_15; +wire [17:0] bi_0_15; +wire [17:0] Wfc_0_15; +wire [17:0] bf_0_15; +wire [17:0] Woc_0_15; +wire [17:0] bo_0_15; +wire [17:0] bc_0_15; +wire [17:0] Wic_1_0; +wire [17:0] bi_1_0; +wire [17:0] Wfc_1_0; +wire [17:0] bf_1_0; +wire [17:0] Woc_1_0; +wire [17:0] bo_1_0; +wire [17:0] bc_1_0; +wire [17:0] Wic_1_1; +wire [17:0] bi_1_1; +wire [17:0] Wfc_1_1; +wire [17:0] bf_1_1; +wire [17:0] Woc_1_1; +wire [17:0] bo_1_1; +wire [17:0] bc_1_1; +wire [17:0] Wic_1_2; +wire [17:0] bi_1_2; +wire [17:0] Wfc_1_2; +wire [17:0] bf_1_2; +wire [17:0] Woc_1_2; +wire [17:0] bo_1_2; +wire [17:0] bc_1_2; +wire [17:0] Wic_1_3; +wire [17:0] bi_1_3; +wire [17:0] Wfc_1_3; +wire [17:0] bf_1_3; +wire [17:0] Woc_1_3; +wire [17:0] bo_1_3; +wire [17:0] bc_1_3; +wire [17:0] Wic_1_4; +wire [17:0] bi_1_4; +wire [17:0] Wfc_1_4; +wire [17:0] bf_1_4; +wire [17:0] Woc_1_4; +wire [17:0] bo_1_4; +wire [17:0] bc_1_4; +wire [17:0] Wic_1_5; +wire [17:0] bi_1_5; +wire [17:0] Wfc_1_5; +wire [17:0] bf_1_5; +wire [17:0] Woc_1_5; +wire [17:0] bo_1_5; +wire [17:0] bc_1_5; +wire [17:0] Wic_1_6; +wire [17:0] bi_1_6; +wire [17:0] Wfc_1_6; +wire [17:0] bf_1_6; +wire [17:0] Woc_1_6; +wire [17:0] bo_1_6; +wire [17:0] bc_1_6; +wire [17:0] Wic_1_7; +wire [17:0] bi_1_7; +wire [17:0] Wfc_1_7; +wire [17:0] bf_1_7; +wire [17:0] Woc_1_7; +wire [17:0] bo_1_7; +wire [17:0] bc_1_7; +wire [17:0] Wic_1_8; +wire [17:0] bi_1_8; +wire [17:0] Wfc_1_8; +wire [17:0] bf_1_8; +wire [17:0] Woc_1_8; +wire [17:0] bo_1_8; +wire [17:0] bc_1_8; +wire [17:0] Wic_1_9; +wire [17:0] bi_1_9; +wire [17:0] Wfc_1_9; +wire [17:0] bf_1_9; +wire [17:0] Woc_1_9; +wire [17:0] bo_1_9; +wire [17:0] bc_1_9; +wire [17:0] Wic_1_10; +wire [17:0] bi_1_10; +wire [17:0] Wfc_1_10; +wire [17:0] bf_1_10; +wire [17:0] Woc_1_10; +wire [17:0] bo_1_10; +wire [17:0] bc_1_10; +wire [17:0] Wic_1_11; +wire [17:0] bi_1_11; +wire [17:0] Wfc_1_11; +wire [17:0] bf_1_11; +wire [17:0] Woc_1_11; +wire [17:0] bo_1_11; +wire [17:0] bc_1_11; +wire [17:0] Wic_1_12; +wire [17:0] bi_1_12; +wire [17:0] Wfc_1_12; +wire [17:0] bf_1_12; +wire [17:0] Woc_1_12; +wire [17:0] bo_1_12; +wire [17:0] bc_1_12; +wire [17:0] Wic_1_13; +wire [17:0] bi_1_13; +wire [17:0] Wfc_1_13; +wire [17:0] bf_1_13; +wire [17:0] Woc_1_13; +wire [17:0] bo_1_13; +wire [17:0] bc_1_13; +wire [17:0] Wic_1_14; +wire [17:0] bi_1_14; +wire [17:0] Wfc_1_14; +wire [17:0] bf_1_14; +wire [17:0] Woc_1_14; +wire [17:0] bo_1_14; +wire [17:0] bc_1_14; +wire [17:0] Wic_1_15; +wire [17:0] bi_1_15; +wire [17:0] Wfc_1_15; +wire [17:0] bf_1_15; +wire [17:0] Woc_1_15; +wire [17:0] bo_1_15; +wire [17:0] bc_1_15; + +wire [13:0] input_index_counter; +counter_63_2 counter_63_2_inst_okwnwjfocm ( + .clk(clk), + .reset(reset), + .ena(incr_index), + .count(input_index_counter) +); + +weight_buffer_18_16_2_64_Wic_0 weight_buffer_18_16_2_64_Wic_0_inst_oqmbxlvldw ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[6]), + .q_0_0(Wic_0_0), + .q_0_1(Wic_0_1), + .q_0_2(Wic_0_2), + .q_0_3(Wic_0_3), + .q_0_4(Wic_0_4), + .q_0_5(Wic_0_5), + .q_0_6(Wic_0_6), + .q_0_7(Wic_0_7), + .q_0_8(Wic_0_8), + .q_0_9(Wic_0_9), + .q_0_10(Wic_0_10), + .q_0_11(Wic_0_11), + .q_0_12(Wic_0_12), + .q_0_13(Wic_0_13), + .q_0_14(Wic_0_14), + .q_0_15(Wic_0_15), + .q_1_0(Wic_1_0), + .q_1_1(Wic_1_1), + .q_1_2(Wic_1_2), + .q_1_3(Wic_1_3), + .q_1_4(Wic_1_4), + .q_1_5(Wic_1_5), + .q_1_6(Wic_1_6), + .q_1_7(Wic_1_7), + .q_1_8(Wic_1_8), + .q_1_9(Wic_1_9), + .q_1_10(Wic_1_10), + .q_1_11(Wic_1_11), + .q_1_12(Wic_1_12), + .q_1_13(Wic_1_13), + .q_1_14(Wic_1_14), + .q_1_15(Wic_1_15), + .index(input_index_counter) +); + +weight_buffer_18_16_2_64_bi_0 weight_buffer_18_16_2_64_bi_0_inst_qzbjueedsp ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[0]), + .q_0_0(bi_0_0), + .q_0_1(bi_0_1), + .q_0_2(bi_0_2), + .q_0_3(bi_0_3), + .q_0_4(bi_0_4), + .q_0_5(bi_0_5), + .q_0_6(bi_0_6), + .q_0_7(bi_0_7), + .q_0_8(bi_0_8), + .q_0_9(bi_0_9), + .q_0_10(bi_0_10), + .q_0_11(bi_0_11), + .q_0_12(bi_0_12), + .q_0_13(bi_0_13), + .q_0_14(bi_0_14), + .q_0_15(bi_0_15), + .q_1_0(bi_1_0), + .q_1_1(bi_1_1), + .q_1_2(bi_1_2), + .q_1_3(bi_1_3), + .q_1_4(bi_1_4), + .q_1_5(bi_1_5), + .q_1_6(bi_1_6), + .q_1_7(bi_1_7), + .q_1_8(bi_1_8), + .q_1_9(bi_1_9), + .q_1_10(bi_1_10), + .q_1_11(bi_1_11), + .q_1_12(bi_1_12), + .q_1_13(bi_1_13), + .q_1_14(bi_1_14), + .q_1_15(bi_1_15), + .index(input_index_counter) +); + +weight_buffer_18_16_2_64_Wfc_0 weight_buffer_18_16_2_64_Wfc_0_inst_vduhscivzb ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[1]), + .q_0_0(Wfc_0_0), + .q_0_1(Wfc_0_1), + .q_0_2(Wfc_0_2), + .q_0_3(Wfc_0_3), + .q_0_4(Wfc_0_4), + .q_0_5(Wfc_0_5), + .q_0_6(Wfc_0_6), + .q_0_7(Wfc_0_7), + .q_0_8(Wfc_0_8), + .q_0_9(Wfc_0_9), + .q_0_10(Wfc_0_10), + .q_0_11(Wfc_0_11), + .q_0_12(Wfc_0_12), + .q_0_13(Wfc_0_13), + .q_0_14(Wfc_0_14), + .q_0_15(Wfc_0_15), + .q_1_0(Wfc_1_0), + .q_1_1(Wfc_1_1), + .q_1_2(Wfc_1_2), + .q_1_3(Wfc_1_3), + .q_1_4(Wfc_1_4), + .q_1_5(Wfc_1_5), + .q_1_6(Wfc_1_6), + .q_1_7(Wfc_1_7), + .q_1_8(Wfc_1_8), + .q_1_9(Wfc_1_9), + .q_1_10(Wfc_1_10), + .q_1_11(Wfc_1_11), + .q_1_12(Wfc_1_12), + .q_1_13(Wfc_1_13), + .q_1_14(Wfc_1_14), + .q_1_15(Wfc_1_15), + .index(input_index_counter) +); + +weight_buffer_18_16_2_64_bf_0 weight_buffer_18_16_2_64_bf_0_inst_ydlitoxlgy ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[2]), + .q_0_0(bf_0_0), + .q_0_1(bf_0_1), + .q_0_2(bf_0_2), + .q_0_3(bf_0_3), + .q_0_4(bf_0_4), + .q_0_5(bf_0_5), + .q_0_6(bf_0_6), + .q_0_7(bf_0_7), + .q_0_8(bf_0_8), + .q_0_9(bf_0_9), + .q_0_10(bf_0_10), + .q_0_11(bf_0_11), + .q_0_12(bf_0_12), + .q_0_13(bf_0_13), + .q_0_14(bf_0_14), + .q_0_15(bf_0_15), + .q_1_0(bf_1_0), + .q_1_1(bf_1_1), + .q_1_2(bf_1_2), + .q_1_3(bf_1_3), + .q_1_4(bf_1_4), + .q_1_5(bf_1_5), + .q_1_6(bf_1_6), + .q_1_7(bf_1_7), + .q_1_8(bf_1_8), + .q_1_9(bf_1_9), + .q_1_10(bf_1_10), + .q_1_11(bf_1_11), + .q_1_12(bf_1_12), + .q_1_13(bf_1_13), + .q_1_14(bf_1_14), + .q_1_15(bf_1_15), + .index(input_index_counter) +); + +weight_buffer_18_16_2_64_Woc_0 weight_buffer_18_16_2_64_Woc_0_inst_gkrdgtigod ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[3]), + .q_0_0(Woc_0_0), + .q_0_1(Woc_0_1), + .q_0_2(Woc_0_2), + .q_0_3(Woc_0_3), + .q_0_4(Woc_0_4), + .q_0_5(Woc_0_5), + .q_0_6(Woc_0_6), + .q_0_7(Woc_0_7), + .q_0_8(Woc_0_8), + .q_0_9(Woc_0_9), + .q_0_10(Woc_0_10), + .q_0_11(Woc_0_11), + .q_0_12(Woc_0_12), + .q_0_13(Woc_0_13), + .q_0_14(Woc_0_14), + .q_0_15(Woc_0_15), + .q_1_0(Woc_1_0), + .q_1_1(Woc_1_1), + .q_1_2(Woc_1_2), + .q_1_3(Woc_1_3), + .q_1_4(Woc_1_4), + .q_1_5(Woc_1_5), + .q_1_6(Woc_1_6), + .q_1_7(Woc_1_7), + .q_1_8(Woc_1_8), + .q_1_9(Woc_1_9), + .q_1_10(Woc_1_10), + .q_1_11(Woc_1_11), + .q_1_12(Woc_1_12), + .q_1_13(Woc_1_13), + .q_1_14(Woc_1_14), + .q_1_15(Woc_1_15), + .index(input_index_counter) +); + +weight_buffer_18_16_2_64_bo_0 weight_buffer_18_16_2_64_bo_0_inst_rqzystxkto ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[4]), + .q_0_0(bo_0_0), + .q_0_1(bo_0_1), + .q_0_2(bo_0_2), + .q_0_3(bo_0_3), + .q_0_4(bo_0_4), + .q_0_5(bo_0_5), + .q_0_6(bo_0_6), + .q_0_7(bo_0_7), + .q_0_8(bo_0_8), + .q_0_9(bo_0_9), + .q_0_10(bo_0_10), + .q_0_11(bo_0_11), + .q_0_12(bo_0_12), + .q_0_13(bo_0_13), + .q_0_14(bo_0_14), + .q_0_15(bo_0_15), + .q_1_0(bo_1_0), + .q_1_1(bo_1_1), + .q_1_2(bo_1_2), + .q_1_3(bo_1_3), + .q_1_4(bo_1_4), + .q_1_5(bo_1_5), + .q_1_6(bo_1_6), + .q_1_7(bo_1_7), + .q_1_8(bo_1_8), + .q_1_9(bo_1_9), + .q_1_10(bo_1_10), + .q_1_11(bo_1_11), + .q_1_12(bo_1_12), + .q_1_13(bo_1_13), + .q_1_14(bo_1_14), + .q_1_15(bo_1_15), + .index(input_index_counter) +); + +weight_buffer_18_16_2_64_bc_0 weight_buffer_18_16_2_64_bc_0_inst_qosugyojir ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[5]), + .q_0_0(bc_0_0), + .q_0_1(bc_0_1), + .q_0_2(bc_0_2), + .q_0_3(bc_0_3), + .q_0_4(bc_0_4), + .q_0_5(bc_0_5), + .q_0_6(bc_0_6), + .q_0_7(bc_0_7), + .q_0_8(bc_0_8), + .q_0_9(bc_0_9), + .q_0_10(bc_0_10), + .q_0_11(bc_0_11), + .q_0_12(bc_0_12), + .q_0_13(bc_0_13), + .q_0_14(bc_0_14), + .q_0_15(bc_0_15), + .q_1_0(bc_1_0), + .q_1_1(bc_1_1), + .q_1_2(bc_1_2), + .q_1_3(bc_1_3), + .q_1_4(bc_1_4), + .q_1_5(bc_1_5), + .q_1_6(bc_1_6), + .q_1_7(bc_1_7), + .q_1_8(bc_1_8), + .q_1_9(bc_1_9), + .q_1_10(bc_1_10), + .q_1_11(bc_1_11), + .q_1_12(bc_1_12), + .q_1_13(bc_1_13), + .q_1_14(bc_1_14), + .q_1_15(bc_1_15), + .index(input_index_counter) +); + +assign o_Wic_0 = Wic_0_0; +assign o_bi_0 = bi_0_0; +assign o_Wfc_0 = Wfc_0_0; +assign o_bf_0 = bf_0_0; +assign o_Woc_0 = Woc_0_0; +assign o_bo_0 = bo_0_0; +assign o_bc_0 = bc_0_0; +assign o_Wic_1 = Wic_0_1; +assign o_bi_1 = bi_0_1; +assign o_Wfc_1 = Wfc_0_1; +assign o_bf_1 = bf_0_1; +assign o_Woc_1 = Woc_0_1; +assign o_bo_1 = bo_0_1; +assign o_bc_1 = bc_0_1; +assign o_Wic_2 = Wic_0_2; +assign o_bi_2 = bi_0_2; +assign o_Wfc_2 = Wfc_0_2; +assign o_bf_2 = bf_0_2; +assign o_Woc_2 = Woc_0_2; +assign o_bo_2 = bo_0_2; +assign o_bc_2 = bc_0_2; +assign o_Wic_3 = Wic_0_3; +assign o_bi_3 = bi_0_3; +assign o_Wfc_3 = Wfc_0_3; +assign o_bf_3 = bf_0_3; +assign o_Woc_3 = Woc_0_3; +assign o_bo_3 = bo_0_3; +assign o_bc_3 = bc_0_3; +assign o_Wic_4 = Wic_0_4; +assign o_bi_4 = bi_0_4; +assign o_Wfc_4 = Wfc_0_4; +assign o_bf_4 = bf_0_4; +assign o_Woc_4 = Woc_0_4; +assign o_bo_4 = bo_0_4; +assign o_bc_4 = bc_0_4; +assign o_Wic_5 = Wic_0_5; +assign o_bi_5 = bi_0_5; +assign o_Wfc_5 = Wfc_0_5; +assign o_bf_5 = bf_0_5; +assign o_Woc_5 = Woc_0_5; +assign o_bo_5 = bo_0_5; +assign o_bc_5 = bc_0_5; +assign o_Wic_6 = Wic_0_6; +assign o_bi_6 = bi_0_6; +assign o_Wfc_6 = Wfc_0_6; +assign o_bf_6 = bf_0_6; +assign o_Woc_6 = Woc_0_6; +assign o_bo_6 = bo_0_6; +assign o_bc_6 = bc_0_6; +assign o_Wic_7 = Wic_0_7; +assign o_bi_7 = bi_0_7; +assign o_Wfc_7 = Wfc_0_7; +assign o_bf_7 = bf_0_7; +assign o_Woc_7 = Woc_0_7; +assign o_bo_7 = bo_0_7; +assign o_bc_7 = bc_0_7; +assign o_Wic_8 = Wic_0_8; +assign o_bi_8 = bi_0_8; +assign o_Wfc_8 = Wfc_0_8; +assign o_bf_8 = bf_0_8; +assign o_Woc_8 = Woc_0_8; +assign o_bo_8 = bo_0_8; +assign o_bc_8 = bc_0_8; +assign o_Wic_9 = Wic_0_9; +assign o_bi_9 = bi_0_9; +assign o_Wfc_9 = Wfc_0_9; +assign o_bf_9 = bf_0_9; +assign o_Woc_9 = Woc_0_9; +assign o_bo_9 = bo_0_9; +assign o_bc_9 = bc_0_9; +assign o_Wic_10 = Wic_0_10; +assign o_bi_10 = bi_0_10; +assign o_Wfc_10 = Wfc_0_10; +assign o_bf_10 = bf_0_10; +assign o_Woc_10 = Woc_0_10; +assign o_bo_10 = bo_0_10; +assign o_bc_10 = bc_0_10; +assign o_Wic_11 = Wic_0_11; +assign o_bi_11 = bi_0_11; +assign o_Wfc_11 = Wfc_0_11; +assign o_bf_11 = bf_0_11; +assign o_Woc_11 = Woc_0_11; +assign o_bo_11 = bo_0_11; +assign o_bc_11 = bc_0_11; +assign o_Wic_12 = Wic_0_12; +assign o_bi_12 = bi_0_12; +assign o_Wfc_12 = Wfc_0_12; +assign o_bf_12 = bf_0_12; +assign o_Woc_12 = Woc_0_12; +assign o_bo_12 = bo_0_12; +assign o_bc_12 = bc_0_12; +assign o_Wic_13 = Wic_0_13; +assign o_bi_13 = bi_0_13; +assign o_Wfc_13 = Wfc_0_13; +assign o_bf_13 = bf_0_13; +assign o_Woc_13 = Woc_0_13; +assign o_bo_13 = bo_0_13; +assign o_bc_13 = bc_0_13; +assign o_Wic_14 = Wic_0_14; +assign o_bi_14 = bi_0_14; +assign o_Wfc_14 = Wfc_0_14; +assign o_bf_14 = bf_0_14; +assign o_Woc_14 = Woc_0_14; +assign o_bo_14 = bo_0_14; +assign o_bc_14 = bc_0_14; +assign o_Wic_15 = Wic_0_15; +assign o_bi_15 = bi_0_15; +assign o_Wfc_15 = Wfc_0_15; +assign o_bf_15 = bf_0_15; +assign o_Woc_15 = Woc_0_15; +assign o_bo_15 = bo_0_15; +assign o_bc_15 = bc_0_15; +assign o_Wic_16 = Wic_1_0; +assign o_bi_16 = bi_1_0; +assign o_Wfc_16 = Wfc_1_0; +assign o_bf_16 = bf_1_0; +assign o_Woc_16 = Woc_1_0; +assign o_bo_16 = bo_1_0; +assign o_bc_16 = bc_1_0; +assign o_Wic_17 = Wic_1_1; +assign o_bi_17 = bi_1_1; +assign o_Wfc_17 = Wfc_1_1; +assign o_bf_17 = bf_1_1; +assign o_Woc_17 = Woc_1_1; +assign o_bo_17 = bo_1_1; +assign o_bc_17 = bc_1_1; +assign o_Wic_18 = Wic_1_2; +assign o_bi_18 = bi_1_2; +assign o_Wfc_18 = Wfc_1_2; +assign o_bf_18 = bf_1_2; +assign o_Woc_18 = Woc_1_2; +assign o_bo_18 = bo_1_2; +assign o_bc_18 = bc_1_2; +assign o_Wic_19 = Wic_1_3; +assign o_bi_19 = bi_1_3; +assign o_Wfc_19 = Wfc_1_3; +assign o_bf_19 = bf_1_3; +assign o_Woc_19 = Woc_1_3; +assign o_bo_19 = bo_1_3; +assign o_bc_19 = bc_1_3; +assign o_Wic_20 = Wic_1_4; +assign o_bi_20 = bi_1_4; +assign o_Wfc_20 = Wfc_1_4; +assign o_bf_20 = bf_1_4; +assign o_Woc_20 = Woc_1_4; +assign o_bo_20 = bo_1_4; +assign o_bc_20 = bc_1_4; +assign o_Wic_21 = Wic_1_5; +assign o_bi_21 = bi_1_5; +assign o_Wfc_21 = Wfc_1_5; +assign o_bf_21 = bf_1_5; +assign o_Woc_21 = Woc_1_5; +assign o_bo_21 = bo_1_5; +assign o_bc_21 = bc_1_5; +assign o_Wic_22 = Wic_1_6; +assign o_bi_22 = bi_1_6; +assign o_Wfc_22 = Wfc_1_6; +assign o_bf_22 = bf_1_6; +assign o_Woc_22 = Woc_1_6; +assign o_bo_22 = bo_1_6; +assign o_bc_22 = bc_1_6; +assign o_Wic_23 = Wic_1_7; +assign o_bi_23 = bi_1_7; +assign o_Wfc_23 = Wfc_1_7; +assign o_bf_23 = bf_1_7; +assign o_Woc_23 = Woc_1_7; +assign o_bo_23 = bo_1_7; +assign o_bc_23 = bc_1_7; +assign o_Wic_24 = Wic_1_8; +assign o_bi_24 = bi_1_8; +assign o_Wfc_24 = Wfc_1_8; +assign o_bf_24 = bf_1_8; +assign o_Woc_24 = Woc_1_8; +assign o_bo_24 = bo_1_8; +assign o_bc_24 = bc_1_8; +assign o_Wic_25 = Wic_1_9; +assign o_bi_25 = bi_1_9; +assign o_Wfc_25 = Wfc_1_9; +assign o_bf_25 = bf_1_9; +assign o_Woc_25 = Woc_1_9; +assign o_bo_25 = bo_1_9; +assign o_bc_25 = bc_1_9; +assign o_Wic_26 = Wic_1_10; +assign o_bi_26 = bi_1_10; +assign o_Wfc_26 = Wfc_1_10; +assign o_bf_26 = bf_1_10; +assign o_Woc_26 = Woc_1_10; +assign o_bo_26 = bo_1_10; +assign o_bc_26 = bc_1_10; +assign o_Wic_27 = Wic_1_11; +assign o_bi_27 = bi_1_11; +assign o_Wfc_27 = Wfc_1_11; +assign o_bf_27 = bf_1_11; +assign o_Woc_27 = Woc_1_11; +assign o_bo_27 = bo_1_11; +assign o_bc_27 = bc_1_11; +assign o_Wic_28 = Wic_1_12; +assign o_bi_28 = bi_1_12; +assign o_Wfc_28 = Wfc_1_12; +assign o_bf_28 = bf_1_12; +assign o_Woc_28 = Woc_1_12; +assign o_bo_28 = bo_1_12; +assign o_bc_28 = bc_1_12; +assign o_Wic_29 = Wic_1_13; +assign o_bi_29 = bi_1_13; +assign o_Wfc_29 = Wfc_1_13; +assign o_bf_29 = bf_1_13; +assign o_Woc_29 = Woc_1_13; +assign o_bo_29 = bo_1_13; +assign o_bc_29 = bc_1_13; +assign o_Wic_30 = Wic_1_14; +assign o_bi_30 = bi_1_14; +assign o_Wfc_30 = Wfc_1_14; +assign o_bf_30 = bf_1_14; +assign o_Woc_30 = Woc_1_14; +assign o_bo_30 = bo_1_14; +assign o_bc_30 = bc_1_14; +assign o_Wic_31 = Wic_1_15; +assign o_bi_31 = bi_1_15; +assign o_Wfc_31 = Wfc_1_15; +assign o_bf_31 = bf_1_15; +assign o_Woc_31 = Woc_1_15; +assign o_bo_31 = bo_1_15; +assign o_bc_31 = bc_1_15; + +endmodule + +module weight_buffer_18_16_2_64_Wic_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_1_9, + output [17:0] q_1_10, + output [17:0] q_1_11, + output [17:0] q_1_12, + output [17:0] q_1_13, + output [17:0] q_1_14, + output [17:0] q_1_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; +wire [287:0] packed_result_1; +reg [5:0] addrs_1; +reg [5:0] addrs_base_1; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 1; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_1_9 = packed_result_1[179:162]; +assign q_1_10 = packed_result_1[197:180]; +assign q_1_11 = packed_result_1[215:198]; +assign q_1_12 = packed_result_1[233:216]; +assign q_1_13 = packed_result_1[251:234]; +assign q_1_14 = packed_result_1[269:252]; +assign q_1_15 = packed_result_1[287:270]; + +endmodule + +module weight_buffer_18_16_2_64_bi_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_1_9, + output [17:0] q_1_10, + output [17:0] q_1_11, + output [17:0] q_1_12, + output [17:0] q_1_13, + output [17:0] q_1_14, + output [17:0] q_1_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; +wire [287:0] packed_result_1; +reg [5:0] addrs_1; +reg [5:0] addrs_base_1; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 1; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_1_9 = packed_result_1[179:162]; +assign q_1_10 = packed_result_1[197:180]; +assign q_1_11 = packed_result_1[215:198]; +assign q_1_12 = packed_result_1[233:216]; +assign q_1_13 = packed_result_1[251:234]; +assign q_1_14 = packed_result_1[269:252]; +assign q_1_15 = packed_result_1[287:270]; + +endmodule + +module weight_buffer_18_16_2_64_Wfc_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_1_9, + output [17:0] q_1_10, + output [17:0] q_1_11, + output [17:0] q_1_12, + output [17:0] q_1_13, + output [17:0] q_1_14, + output [17:0] q_1_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; +wire [287:0] packed_result_1; +reg [5:0] addrs_1; +reg [5:0] addrs_base_1; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 1; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_1_9 = packed_result_1[179:162]; +assign q_1_10 = packed_result_1[197:180]; +assign q_1_11 = packed_result_1[215:198]; +assign q_1_12 = packed_result_1[233:216]; +assign q_1_13 = packed_result_1[251:234]; +assign q_1_14 = packed_result_1[269:252]; +assign q_1_15 = packed_result_1[287:270]; + +endmodule + +module weight_buffer_18_16_2_64_bf_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_1_9, + output [17:0] q_1_10, + output [17:0] q_1_11, + output [17:0] q_1_12, + output [17:0] q_1_13, + output [17:0] q_1_14, + output [17:0] q_1_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; +wire [287:0] packed_result_1; +reg [5:0] addrs_1; +reg [5:0] addrs_base_1; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 1; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_1_9 = packed_result_1[179:162]; +assign q_1_10 = packed_result_1[197:180]; +assign q_1_11 = packed_result_1[215:198]; +assign q_1_12 = packed_result_1[233:216]; +assign q_1_13 = packed_result_1[251:234]; +assign q_1_14 = packed_result_1[269:252]; +assign q_1_15 = packed_result_1[287:270]; + +endmodule + +module weight_buffer_18_16_2_64_Woc_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_1_9, + output [17:0] q_1_10, + output [17:0] q_1_11, + output [17:0] q_1_12, + output [17:0] q_1_13, + output [17:0] q_1_14, + output [17:0] q_1_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; +wire [287:0] packed_result_1; +reg [5:0] addrs_1; +reg [5:0] addrs_base_1; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 1; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_1_9 = packed_result_1[179:162]; +assign q_1_10 = packed_result_1[197:180]; +assign q_1_11 = packed_result_1[215:198]; +assign q_1_12 = packed_result_1[233:216]; +assign q_1_13 = packed_result_1[251:234]; +assign q_1_14 = packed_result_1[269:252]; +assign q_1_15 = packed_result_1[287:270]; + +endmodule + +module weight_buffer_18_16_2_64_bo_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_1_9, + output [17:0] q_1_10, + output [17:0] q_1_11, + output [17:0] q_1_12, + output [17:0] q_1_13, + output [17:0] q_1_14, + output [17:0] q_1_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; +wire [287:0] packed_result_1; +reg [5:0] addrs_1; +reg [5:0] addrs_base_1; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 1; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_1_9 = packed_result_1[179:162]; +assign q_1_10 = packed_result_1[197:180]; +assign q_1_11 = packed_result_1[215:198]; +assign q_1_12 = packed_result_1[233:216]; +assign q_1_13 = packed_result_1[251:234]; +assign q_1_14 = packed_result_1[269:252]; +assign q_1_15 = packed_result_1[287:270]; + +endmodule + +module weight_buffer_18_16_2_64_bc_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + output [17:0] q_1_9, + output [17:0] q_1_10, + output [17:0] q_1_11, + output [17:0] q_1_12, + output [17:0] q_1_13, + output [17:0] q_1_14, + output [17:0] q_1_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; +wire [287:0] packed_result_1; +reg [5:0] addrs_1; +reg [5:0] addrs_base_1; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 1; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; +assign q_1_9 = packed_result_1[179:162]; +assign q_1_10 = packed_result_1[197:180]; +assign q_1_11 = packed_result_1[215:198]; +assign q_1_12 = packed_result_1[233:216]; +assign q_1_13 = packed_result_1[251:234]; +assign q_1_14 = packed_result_1[269:252]; +assign q_1_15 = packed_result_1[287:270]; + +endmodule + +module shift_register_group_18_32_3 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input [17:0] in_16, + output [17:0] out_16, + input [17:0] in_17, + output [17:0] out_17, + input [17:0] in_18, + output [17:0] out_18, + input [17:0] in_19, + output [17:0] out_19, + input [17:0] in_20, + output [17:0] out_20, + input [17:0] in_21, + output [17:0] out_21, + input [17:0] in_22, + output [17:0] out_22, + input [17:0] in_23, + output [17:0] out_23, + input [17:0] in_24, + output [17:0] out_24, + input [17:0] in_25, + output [17:0] out_25, + input [17:0] in_26, + output [17:0] out_26, + input [17:0] in_27, + output [17:0] out_27, + input [17:0] in_28, + output [17:0] out_28, + input [17:0] in_29, + output [17:0] out_29, + input [17:0] in_30, + output [17:0] out_30, + input [17:0] in_31, + output [17:0] out_31, + input reset +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_16 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_16), + .out(out_16) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_17 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_17), + .out(out_17) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_18 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_18), + .out(out_18) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_19 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_19), + .out(out_19) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_20 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_20), + .out(out_20) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_21 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_21), + .out(out_21) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_22 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_22), + .out(out_22) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_23 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_23), + .out(out_23) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_24 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_24), + .out(out_24) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_25 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_25), + .out(out_25) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_26 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_26), + .out(out_26) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_27 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_27), + .out(out_27) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_28 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_28), + .out(out_28) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_29 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_29), + .out(out_29) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_30 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_30), + .out(out_30) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_31 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_31), + .out(out_31) +); + +endmodule + +module C_LSTM_stage_2_18_10_32_1 ( + input clk, + input reset, + input enable, + input i_valid, + input [17:0] Ct_1_0, + input [17:0] WixrXtYt_1_0, + input [17:0] Wic_0, + input [17:0] bi_0, + input [17:0] WfxrXtYt_1_0, + input [17:0] Wfc_0, + input [17:0] bf_0, + input [17:0] WoxrXtYt_1_0, + input [17:0] Woc_0, + input [17:0] bo_0, + input [17:0] WcxrXtYt_1_0, + input [17:0] bc_0, + output [17:0] out_mt_0, + output [17:0] out_ct_0, + input [17:0] Ct_1_1, + input [17:0] WixrXtYt_1_1, + input [17:0] Wic_1, + input [17:0] bi_1, + input [17:0] WfxrXtYt_1_1, + input [17:0] Wfc_1, + input [17:0] bf_1, + input [17:0] WoxrXtYt_1_1, + input [17:0] Woc_1, + input [17:0] bo_1, + input [17:0] WcxrXtYt_1_1, + input [17:0] bc_1, + output [17:0] out_mt_1, + output [17:0] out_ct_1, + input [17:0] Ct_1_2, + input [17:0] WixrXtYt_1_2, + input [17:0] Wic_2, + input [17:0] bi_2, + input [17:0] WfxrXtYt_1_2, + input [17:0] Wfc_2, + input [17:0] bf_2, + input [17:0] WoxrXtYt_1_2, + input [17:0] Woc_2, + input [17:0] bo_2, + input [17:0] WcxrXtYt_1_2, + input [17:0] bc_2, + output [17:0] out_mt_2, + output [17:0] out_ct_2, + input [17:0] Ct_1_3, + input [17:0] WixrXtYt_1_3, + input [17:0] Wic_3, + input [17:0] bi_3, + input [17:0] WfxrXtYt_1_3, + input [17:0] Wfc_3, + input [17:0] bf_3, + input [17:0] WoxrXtYt_1_3, + input [17:0] Woc_3, + input [17:0] bo_3, + input [17:0] WcxrXtYt_1_3, + input [17:0] bc_3, + output [17:0] out_mt_3, + output [17:0] out_ct_3, + input [17:0] Ct_1_4, + input [17:0] WixrXtYt_1_4, + input [17:0] Wic_4, + input [17:0] bi_4, + input [17:0] WfxrXtYt_1_4, + input [17:0] Wfc_4, + input [17:0] bf_4, + input [17:0] WoxrXtYt_1_4, + input [17:0] Woc_4, + input [17:0] bo_4, + input [17:0] WcxrXtYt_1_4, + input [17:0] bc_4, + output [17:0] out_mt_4, + output [17:0] out_ct_4, + input [17:0] Ct_1_5, + input [17:0] WixrXtYt_1_5, + input [17:0] Wic_5, + input [17:0] bi_5, + input [17:0] WfxrXtYt_1_5, + input [17:0] Wfc_5, + input [17:0] bf_5, + input [17:0] WoxrXtYt_1_5, + input [17:0] Woc_5, + input [17:0] bo_5, + input [17:0] WcxrXtYt_1_5, + input [17:0] bc_5, + output [17:0] out_mt_5, + output [17:0] out_ct_5, + input [17:0] Ct_1_6, + input [17:0] WixrXtYt_1_6, + input [17:0] Wic_6, + input [17:0] bi_6, + input [17:0] WfxrXtYt_1_6, + input [17:0] Wfc_6, + input [17:0] bf_6, + input [17:0] WoxrXtYt_1_6, + input [17:0] Woc_6, + input [17:0] bo_6, + input [17:0] WcxrXtYt_1_6, + input [17:0] bc_6, + output [17:0] out_mt_6, + output [17:0] out_ct_6, + input [17:0] Ct_1_7, + input [17:0] WixrXtYt_1_7, + input [17:0] Wic_7, + input [17:0] bi_7, + input [17:0] WfxrXtYt_1_7, + input [17:0] Wfc_7, + input [17:0] bf_7, + input [17:0] WoxrXtYt_1_7, + input [17:0] Woc_7, + input [17:0] bo_7, + input [17:0] WcxrXtYt_1_7, + input [17:0] bc_7, + output [17:0] out_mt_7, + output [17:0] out_ct_7, + input [17:0] Ct_1_8, + input [17:0] WixrXtYt_1_8, + input [17:0] Wic_8, + input [17:0] bi_8, + input [17:0] WfxrXtYt_1_8, + input [17:0] Wfc_8, + input [17:0] bf_8, + input [17:0] WoxrXtYt_1_8, + input [17:0] Woc_8, + input [17:0] bo_8, + input [17:0] WcxrXtYt_1_8, + input [17:0] bc_8, + output [17:0] out_mt_8, + output [17:0] out_ct_8, + input [17:0] Ct_1_9, + input [17:0] WixrXtYt_1_9, + input [17:0] Wic_9, + input [17:0] bi_9, + input [17:0] WfxrXtYt_1_9, + input [17:0] Wfc_9, + input [17:0] bf_9, + input [17:0] WoxrXtYt_1_9, + input [17:0] Woc_9, + input [17:0] bo_9, + input [17:0] WcxrXtYt_1_9, + input [17:0] bc_9, + output [17:0] out_mt_9, + output [17:0] out_ct_9, + input [17:0] Ct_1_10, + input [17:0] WixrXtYt_1_10, + input [17:0] Wic_10, + input [17:0] bi_10, + input [17:0] WfxrXtYt_1_10, + input [17:0] Wfc_10, + input [17:0] bf_10, + input [17:0] WoxrXtYt_1_10, + input [17:0] Woc_10, + input [17:0] bo_10, + input [17:0] WcxrXtYt_1_10, + input [17:0] bc_10, + output [17:0] out_mt_10, + output [17:0] out_ct_10, + input [17:0] Ct_1_11, + input [17:0] WixrXtYt_1_11, + input [17:0] Wic_11, + input [17:0] bi_11, + input [17:0] WfxrXtYt_1_11, + input [17:0] Wfc_11, + input [17:0] bf_11, + input [17:0] WoxrXtYt_1_11, + input [17:0] Woc_11, + input [17:0] bo_11, + input [17:0] WcxrXtYt_1_11, + input [17:0] bc_11, + output [17:0] out_mt_11, + output [17:0] out_ct_11, + input [17:0] Ct_1_12, + input [17:0] WixrXtYt_1_12, + input [17:0] Wic_12, + input [17:0] bi_12, + input [17:0] WfxrXtYt_1_12, + input [17:0] Wfc_12, + input [17:0] bf_12, + input [17:0] WoxrXtYt_1_12, + input [17:0] Woc_12, + input [17:0] bo_12, + input [17:0] WcxrXtYt_1_12, + input [17:0] bc_12, + output [17:0] out_mt_12, + output [17:0] out_ct_12, + input [17:0] Ct_1_13, + input [17:0] WixrXtYt_1_13, + input [17:0] Wic_13, + input [17:0] bi_13, + input [17:0] WfxrXtYt_1_13, + input [17:0] Wfc_13, + input [17:0] bf_13, + input [17:0] WoxrXtYt_1_13, + input [17:0] Woc_13, + input [17:0] bo_13, + input [17:0] WcxrXtYt_1_13, + input [17:0] bc_13, + output [17:0] out_mt_13, + output [17:0] out_ct_13, + input [17:0] Ct_1_14, + input [17:0] WixrXtYt_1_14, + input [17:0] Wic_14, + input [17:0] bi_14, + input [17:0] WfxrXtYt_1_14, + input [17:0] Wfc_14, + input [17:0] bf_14, + input [17:0] WoxrXtYt_1_14, + input [17:0] Woc_14, + input [17:0] bo_14, + input [17:0] WcxrXtYt_1_14, + input [17:0] bc_14, + output [17:0] out_mt_14, + output [17:0] out_ct_14, + input [17:0] Ct_1_15, + input [17:0] WixrXtYt_1_15, + input [17:0] Wic_15, + input [17:0] bi_15, + input [17:0] WfxrXtYt_1_15, + input [17:0] Wfc_15, + input [17:0] bf_15, + input [17:0] WoxrXtYt_1_15, + input [17:0] Woc_15, + input [17:0] bo_15, + input [17:0] WcxrXtYt_1_15, + input [17:0] bc_15, + output [17:0] out_mt_15, + output [17:0] out_ct_15, + input [17:0] Ct_1_16, + input [17:0] WixrXtYt_1_16, + input [17:0] Wic_16, + input [17:0] bi_16, + input [17:0] WfxrXtYt_1_16, + input [17:0] Wfc_16, + input [17:0] bf_16, + input [17:0] WoxrXtYt_1_16, + input [17:0] Woc_16, + input [17:0] bo_16, + input [17:0] WcxrXtYt_1_16, + input [17:0] bc_16, + output [17:0] out_mt_16, + output [17:0] out_ct_16, + input [17:0] Ct_1_17, + input [17:0] WixrXtYt_1_17, + input [17:0] Wic_17, + input [17:0] bi_17, + input [17:0] WfxrXtYt_1_17, + input [17:0] Wfc_17, + input [17:0] bf_17, + input [17:0] WoxrXtYt_1_17, + input [17:0] Woc_17, + input [17:0] bo_17, + input [17:0] WcxrXtYt_1_17, + input [17:0] bc_17, + output [17:0] out_mt_17, + output [17:0] out_ct_17, + input [17:0] Ct_1_18, + input [17:0] WixrXtYt_1_18, + input [17:0] Wic_18, + input [17:0] bi_18, + input [17:0] WfxrXtYt_1_18, + input [17:0] Wfc_18, + input [17:0] bf_18, + input [17:0] WoxrXtYt_1_18, + input [17:0] Woc_18, + input [17:0] bo_18, + input [17:0] WcxrXtYt_1_18, + input [17:0] bc_18, + output [17:0] out_mt_18, + output [17:0] out_ct_18, + input [17:0] Ct_1_19, + input [17:0] WixrXtYt_1_19, + input [17:0] Wic_19, + input [17:0] bi_19, + input [17:0] WfxrXtYt_1_19, + input [17:0] Wfc_19, + input [17:0] bf_19, + input [17:0] WoxrXtYt_1_19, + input [17:0] Woc_19, + input [17:0] bo_19, + input [17:0] WcxrXtYt_1_19, + input [17:0] bc_19, + output [17:0] out_mt_19, + output [17:0] out_ct_19, + input [17:0] Ct_1_20, + input [17:0] WixrXtYt_1_20, + input [17:0] Wic_20, + input [17:0] bi_20, + input [17:0] WfxrXtYt_1_20, + input [17:0] Wfc_20, + input [17:0] bf_20, + input [17:0] WoxrXtYt_1_20, + input [17:0] Woc_20, + input [17:0] bo_20, + input [17:0] WcxrXtYt_1_20, + input [17:0] bc_20, + output [17:0] out_mt_20, + output [17:0] out_ct_20, + input [17:0] Ct_1_21, + input [17:0] WixrXtYt_1_21, + input [17:0] Wic_21, + input [17:0] bi_21, + input [17:0] WfxrXtYt_1_21, + input [17:0] Wfc_21, + input [17:0] bf_21, + input [17:0] WoxrXtYt_1_21, + input [17:0] Woc_21, + input [17:0] bo_21, + input [17:0] WcxrXtYt_1_21, + input [17:0] bc_21, + output [17:0] out_mt_21, + output [17:0] out_ct_21, + input [17:0] Ct_1_22, + input [17:0] WixrXtYt_1_22, + input [17:0] Wic_22, + input [17:0] bi_22, + input [17:0] WfxrXtYt_1_22, + input [17:0] Wfc_22, + input [17:0] bf_22, + input [17:0] WoxrXtYt_1_22, + input [17:0] Woc_22, + input [17:0] bo_22, + input [17:0] WcxrXtYt_1_22, + input [17:0] bc_22, + output [17:0] out_mt_22, + output [17:0] out_ct_22, + input [17:0] Ct_1_23, + input [17:0] WixrXtYt_1_23, + input [17:0] Wic_23, + input [17:0] bi_23, + input [17:0] WfxrXtYt_1_23, + input [17:0] Wfc_23, + input [17:0] bf_23, + input [17:0] WoxrXtYt_1_23, + input [17:0] Woc_23, + input [17:0] bo_23, + input [17:0] WcxrXtYt_1_23, + input [17:0] bc_23, + output [17:0] out_mt_23, + output [17:0] out_ct_23, + input [17:0] Ct_1_24, + input [17:0] WixrXtYt_1_24, + input [17:0] Wic_24, + input [17:0] bi_24, + input [17:0] WfxrXtYt_1_24, + input [17:0] Wfc_24, + input [17:0] bf_24, + input [17:0] WoxrXtYt_1_24, + input [17:0] Woc_24, + input [17:0] bo_24, + input [17:0] WcxrXtYt_1_24, + input [17:0] bc_24, + output [17:0] out_mt_24, + output [17:0] out_ct_24, + input [17:0] Ct_1_25, + input [17:0] WixrXtYt_1_25, + input [17:0] Wic_25, + input [17:0] bi_25, + input [17:0] WfxrXtYt_1_25, + input [17:0] Wfc_25, + input [17:0] bf_25, + input [17:0] WoxrXtYt_1_25, + input [17:0] Woc_25, + input [17:0] bo_25, + input [17:0] WcxrXtYt_1_25, + input [17:0] bc_25, + output [17:0] out_mt_25, + output [17:0] out_ct_25, + input [17:0] Ct_1_26, + input [17:0] WixrXtYt_1_26, + input [17:0] Wic_26, + input [17:0] bi_26, + input [17:0] WfxrXtYt_1_26, + input [17:0] Wfc_26, + input [17:0] bf_26, + input [17:0] WoxrXtYt_1_26, + input [17:0] Woc_26, + input [17:0] bo_26, + input [17:0] WcxrXtYt_1_26, + input [17:0] bc_26, + output [17:0] out_mt_26, + output [17:0] out_ct_26, + input [17:0] Ct_1_27, + input [17:0] WixrXtYt_1_27, + input [17:0] Wic_27, + input [17:0] bi_27, + input [17:0] WfxrXtYt_1_27, + input [17:0] Wfc_27, + input [17:0] bf_27, + input [17:0] WoxrXtYt_1_27, + input [17:0] Woc_27, + input [17:0] bo_27, + input [17:0] WcxrXtYt_1_27, + input [17:0] bc_27, + output [17:0] out_mt_27, + output [17:0] out_ct_27, + input [17:0] Ct_1_28, + input [17:0] WixrXtYt_1_28, + input [17:0] Wic_28, + input [17:0] bi_28, + input [17:0] WfxrXtYt_1_28, + input [17:0] Wfc_28, + input [17:0] bf_28, + input [17:0] WoxrXtYt_1_28, + input [17:0] Woc_28, + input [17:0] bo_28, + input [17:0] WcxrXtYt_1_28, + input [17:0] bc_28, + output [17:0] out_mt_28, + output [17:0] out_ct_28, + input [17:0] Ct_1_29, + input [17:0] WixrXtYt_1_29, + input [17:0] Wic_29, + input [17:0] bi_29, + input [17:0] WfxrXtYt_1_29, + input [17:0] Wfc_29, + input [17:0] bf_29, + input [17:0] WoxrXtYt_1_29, + input [17:0] Woc_29, + input [17:0] bo_29, + input [17:0] WcxrXtYt_1_29, + input [17:0] bc_29, + output [17:0] out_mt_29, + output [17:0] out_ct_29, + input [17:0] Ct_1_30, + input [17:0] WixrXtYt_1_30, + input [17:0] Wic_30, + input [17:0] bi_30, + input [17:0] WfxrXtYt_1_30, + input [17:0] Wfc_30, + input [17:0] bf_30, + input [17:0] WoxrXtYt_1_30, + input [17:0] Woc_30, + input [17:0] bo_30, + input [17:0] WcxrXtYt_1_30, + input [17:0] bc_30, + output [17:0] out_mt_30, + output [17:0] out_ct_30, + input [17:0] Ct_1_31, + input [17:0] WixrXtYt_1_31, + input [17:0] Wic_31, + input [17:0] bi_31, + input [17:0] WfxrXtYt_1_31, + input [17:0] Wfc_31, + input [17:0] bf_31, + input [17:0] WoxrXtYt_1_31, + input [17:0] Woc_31, + input [17:0] bo_31, + input [17:0] WcxrXtYt_1_31, + input [17:0] bc_31, + output [17:0] out_mt_31, + output [17:0] out_ct_31, + output o_valid, + output o_ready +); + +reg reg_i_valid, reg_o_valid; +reg [17:0] reg_Ct_1_0; +reg [17:0] reg_WixrXtYt_1_0; +reg [17:0] reg_Wic_0; +reg [17:0] reg_bi_0; +reg [17:0] reg_WfxrXtYt_1_0; +reg [17:0] reg_Wfc_0; +reg [17:0] reg_bf_0; +reg [17:0] reg_WoxrXtYt_1_0; +reg [17:0] reg_Woc_0; +reg [17:0] reg_bo_0; +reg [17:0] reg_WcxrXtYt_1_0; +reg [17:0] reg_bc_0; +reg [17:0] reg_out_mt_0; +reg [17:0] reg_out_ct_0; +reg [17:0] reg_Ct_1_1; +reg [17:0] reg_WixrXtYt_1_1; +reg [17:0] reg_Wic_1; +reg [17:0] reg_bi_1; +reg [17:0] reg_WfxrXtYt_1_1; +reg [17:0] reg_Wfc_1; +reg [17:0] reg_bf_1; +reg [17:0] reg_WoxrXtYt_1_1; +reg [17:0] reg_Woc_1; +reg [17:0] reg_bo_1; +reg [17:0] reg_WcxrXtYt_1_1; +reg [17:0] reg_bc_1; +reg [17:0] reg_out_mt_1; +reg [17:0] reg_out_ct_1; +reg [17:0] reg_Ct_1_2; +reg [17:0] reg_WixrXtYt_1_2; +reg [17:0] reg_Wic_2; +reg [17:0] reg_bi_2; +reg [17:0] reg_WfxrXtYt_1_2; +reg [17:0] reg_Wfc_2; +reg [17:0] reg_bf_2; +reg [17:0] reg_WoxrXtYt_1_2; +reg [17:0] reg_Woc_2; +reg [17:0] reg_bo_2; +reg [17:0] reg_WcxrXtYt_1_2; +reg [17:0] reg_bc_2; +reg [17:0] reg_out_mt_2; +reg [17:0] reg_out_ct_2; +reg [17:0] reg_Ct_1_3; +reg [17:0] reg_WixrXtYt_1_3; +reg [17:0] reg_Wic_3; +reg [17:0] reg_bi_3; +reg [17:0] reg_WfxrXtYt_1_3; +reg [17:0] reg_Wfc_3; +reg [17:0] reg_bf_3; +reg [17:0] reg_WoxrXtYt_1_3; +reg [17:0] reg_Woc_3; +reg [17:0] reg_bo_3; +reg [17:0] reg_WcxrXtYt_1_3; +reg [17:0] reg_bc_3; +reg [17:0] reg_out_mt_3; +reg [17:0] reg_out_ct_3; +reg [17:0] reg_Ct_1_4; +reg [17:0] reg_WixrXtYt_1_4; +reg [17:0] reg_Wic_4; +reg [17:0] reg_bi_4; +reg [17:0] reg_WfxrXtYt_1_4; +reg [17:0] reg_Wfc_4; +reg [17:0] reg_bf_4; +reg [17:0] reg_WoxrXtYt_1_4; +reg [17:0] reg_Woc_4; +reg [17:0] reg_bo_4; +reg [17:0] reg_WcxrXtYt_1_4; +reg [17:0] reg_bc_4; +reg [17:0] reg_out_mt_4; +reg [17:0] reg_out_ct_4; +reg [17:0] reg_Ct_1_5; +reg [17:0] reg_WixrXtYt_1_5; +reg [17:0] reg_Wic_5; +reg [17:0] reg_bi_5; +reg [17:0] reg_WfxrXtYt_1_5; +reg [17:0] reg_Wfc_5; +reg [17:0] reg_bf_5; +reg [17:0] reg_WoxrXtYt_1_5; +reg [17:0] reg_Woc_5; +reg [17:0] reg_bo_5; +reg [17:0] reg_WcxrXtYt_1_5; +reg [17:0] reg_bc_5; +reg [17:0] reg_out_mt_5; +reg [17:0] reg_out_ct_5; +reg [17:0] reg_Ct_1_6; +reg [17:0] reg_WixrXtYt_1_6; +reg [17:0] reg_Wic_6; +reg [17:0] reg_bi_6; +reg [17:0] reg_WfxrXtYt_1_6; +reg [17:0] reg_Wfc_6; +reg [17:0] reg_bf_6; +reg [17:0] reg_WoxrXtYt_1_6; +reg [17:0] reg_Woc_6; +reg [17:0] reg_bo_6; +reg [17:0] reg_WcxrXtYt_1_6; +reg [17:0] reg_bc_6; +reg [17:0] reg_out_mt_6; +reg [17:0] reg_out_ct_6; +reg [17:0] reg_Ct_1_7; +reg [17:0] reg_WixrXtYt_1_7; +reg [17:0] reg_Wic_7; +reg [17:0] reg_bi_7; +reg [17:0] reg_WfxrXtYt_1_7; +reg [17:0] reg_Wfc_7; +reg [17:0] reg_bf_7; +reg [17:0] reg_WoxrXtYt_1_7; +reg [17:0] reg_Woc_7; +reg [17:0] reg_bo_7; +reg [17:0] reg_WcxrXtYt_1_7; +reg [17:0] reg_bc_7; +reg [17:0] reg_out_mt_7; +reg [17:0] reg_out_ct_7; +reg [17:0] reg_Ct_1_8; +reg [17:0] reg_WixrXtYt_1_8; +reg [17:0] reg_Wic_8; +reg [17:0] reg_bi_8; +reg [17:0] reg_WfxrXtYt_1_8; +reg [17:0] reg_Wfc_8; +reg [17:0] reg_bf_8; +reg [17:0] reg_WoxrXtYt_1_8; +reg [17:0] reg_Woc_8; +reg [17:0] reg_bo_8; +reg [17:0] reg_WcxrXtYt_1_8; +reg [17:0] reg_bc_8; +reg [17:0] reg_out_mt_8; +reg [17:0] reg_out_ct_8; +reg [17:0] reg_Ct_1_9; +reg [17:0] reg_WixrXtYt_1_9; +reg [17:0] reg_Wic_9; +reg [17:0] reg_bi_9; +reg [17:0] reg_WfxrXtYt_1_9; +reg [17:0] reg_Wfc_9; +reg [17:0] reg_bf_9; +reg [17:0] reg_WoxrXtYt_1_9; +reg [17:0] reg_Woc_9; +reg [17:0] reg_bo_9; +reg [17:0] reg_WcxrXtYt_1_9; +reg [17:0] reg_bc_9; +reg [17:0] reg_out_mt_9; +reg [17:0] reg_out_ct_9; +reg [17:0] reg_Ct_1_10; +reg [17:0] reg_WixrXtYt_1_10; +reg [17:0] reg_Wic_10; +reg [17:0] reg_bi_10; +reg [17:0] reg_WfxrXtYt_1_10; +reg [17:0] reg_Wfc_10; +reg [17:0] reg_bf_10; +reg [17:0] reg_WoxrXtYt_1_10; +reg [17:0] reg_Woc_10; +reg [17:0] reg_bo_10; +reg [17:0] reg_WcxrXtYt_1_10; +reg [17:0] reg_bc_10; +reg [17:0] reg_out_mt_10; +reg [17:0] reg_out_ct_10; +reg [17:0] reg_Ct_1_11; +reg [17:0] reg_WixrXtYt_1_11; +reg [17:0] reg_Wic_11; +reg [17:0] reg_bi_11; +reg [17:0] reg_WfxrXtYt_1_11; +reg [17:0] reg_Wfc_11; +reg [17:0] reg_bf_11; +reg [17:0] reg_WoxrXtYt_1_11; +reg [17:0] reg_Woc_11; +reg [17:0] reg_bo_11; +reg [17:0] reg_WcxrXtYt_1_11; +reg [17:0] reg_bc_11; +reg [17:0] reg_out_mt_11; +reg [17:0] reg_out_ct_11; +reg [17:0] reg_Ct_1_12; +reg [17:0] reg_WixrXtYt_1_12; +reg [17:0] reg_Wic_12; +reg [17:0] reg_bi_12; +reg [17:0] reg_WfxrXtYt_1_12; +reg [17:0] reg_Wfc_12; +reg [17:0] reg_bf_12; +reg [17:0] reg_WoxrXtYt_1_12; +reg [17:0] reg_Woc_12; +reg [17:0] reg_bo_12; +reg [17:0] reg_WcxrXtYt_1_12; +reg [17:0] reg_bc_12; +reg [17:0] reg_out_mt_12; +reg [17:0] reg_out_ct_12; +reg [17:0] reg_Ct_1_13; +reg [17:0] reg_WixrXtYt_1_13; +reg [17:0] reg_Wic_13; +reg [17:0] reg_bi_13; +reg [17:0] reg_WfxrXtYt_1_13; +reg [17:0] reg_Wfc_13; +reg [17:0] reg_bf_13; +reg [17:0] reg_WoxrXtYt_1_13; +reg [17:0] reg_Woc_13; +reg [17:0] reg_bo_13; +reg [17:0] reg_WcxrXtYt_1_13; +reg [17:0] reg_bc_13; +reg [17:0] reg_out_mt_13; +reg [17:0] reg_out_ct_13; +reg [17:0] reg_Ct_1_14; +reg [17:0] reg_WixrXtYt_1_14; +reg [17:0] reg_Wic_14; +reg [17:0] reg_bi_14; +reg [17:0] reg_WfxrXtYt_1_14; +reg [17:0] reg_Wfc_14; +reg [17:0] reg_bf_14; +reg [17:0] reg_WoxrXtYt_1_14; +reg [17:0] reg_Woc_14; +reg [17:0] reg_bo_14; +reg [17:0] reg_WcxrXtYt_1_14; +reg [17:0] reg_bc_14; +reg [17:0] reg_out_mt_14; +reg [17:0] reg_out_ct_14; +reg [17:0] reg_Ct_1_15; +reg [17:0] reg_WixrXtYt_1_15; +reg [17:0] reg_Wic_15; +reg [17:0] reg_bi_15; +reg [17:0] reg_WfxrXtYt_1_15; +reg [17:0] reg_Wfc_15; +reg [17:0] reg_bf_15; +reg [17:0] reg_WoxrXtYt_1_15; +reg [17:0] reg_Woc_15; +reg [17:0] reg_bo_15; +reg [17:0] reg_WcxrXtYt_1_15; +reg [17:0] reg_bc_15; +reg [17:0] reg_out_mt_15; +reg [17:0] reg_out_ct_15; +reg [17:0] reg_Ct_1_16; +reg [17:0] reg_WixrXtYt_1_16; +reg [17:0] reg_Wic_16; +reg [17:0] reg_bi_16; +reg [17:0] reg_WfxrXtYt_1_16; +reg [17:0] reg_Wfc_16; +reg [17:0] reg_bf_16; +reg [17:0] reg_WoxrXtYt_1_16; +reg [17:0] reg_Woc_16; +reg [17:0] reg_bo_16; +reg [17:0] reg_WcxrXtYt_1_16; +reg [17:0] reg_bc_16; +reg [17:0] reg_out_mt_16; +reg [17:0] reg_out_ct_16; +reg [17:0] reg_Ct_1_17; +reg [17:0] reg_WixrXtYt_1_17; +reg [17:0] reg_Wic_17; +reg [17:0] reg_bi_17; +reg [17:0] reg_WfxrXtYt_1_17; +reg [17:0] reg_Wfc_17; +reg [17:0] reg_bf_17; +reg [17:0] reg_WoxrXtYt_1_17; +reg [17:0] reg_Woc_17; +reg [17:0] reg_bo_17; +reg [17:0] reg_WcxrXtYt_1_17; +reg [17:0] reg_bc_17; +reg [17:0] reg_out_mt_17; +reg [17:0] reg_out_ct_17; +reg [17:0] reg_Ct_1_18; +reg [17:0] reg_WixrXtYt_1_18; +reg [17:0] reg_Wic_18; +reg [17:0] reg_bi_18; +reg [17:0] reg_WfxrXtYt_1_18; +reg [17:0] reg_Wfc_18; +reg [17:0] reg_bf_18; +reg [17:0] reg_WoxrXtYt_1_18; +reg [17:0] reg_Woc_18; +reg [17:0] reg_bo_18; +reg [17:0] reg_WcxrXtYt_1_18; +reg [17:0] reg_bc_18; +reg [17:0] reg_out_mt_18; +reg [17:0] reg_out_ct_18; +reg [17:0] reg_Ct_1_19; +reg [17:0] reg_WixrXtYt_1_19; +reg [17:0] reg_Wic_19; +reg [17:0] reg_bi_19; +reg [17:0] reg_WfxrXtYt_1_19; +reg [17:0] reg_Wfc_19; +reg [17:0] reg_bf_19; +reg [17:0] reg_WoxrXtYt_1_19; +reg [17:0] reg_Woc_19; +reg [17:0] reg_bo_19; +reg [17:0] reg_WcxrXtYt_1_19; +reg [17:0] reg_bc_19; +reg [17:0] reg_out_mt_19; +reg [17:0] reg_out_ct_19; +reg [17:0] reg_Ct_1_20; +reg [17:0] reg_WixrXtYt_1_20; +reg [17:0] reg_Wic_20; +reg [17:0] reg_bi_20; +reg [17:0] reg_WfxrXtYt_1_20; +reg [17:0] reg_Wfc_20; +reg [17:0] reg_bf_20; +reg [17:0] reg_WoxrXtYt_1_20; +reg [17:0] reg_Woc_20; +reg [17:0] reg_bo_20; +reg [17:0] reg_WcxrXtYt_1_20; +reg [17:0] reg_bc_20; +reg [17:0] reg_out_mt_20; +reg [17:0] reg_out_ct_20; +reg [17:0] reg_Ct_1_21; +reg [17:0] reg_WixrXtYt_1_21; +reg [17:0] reg_Wic_21; +reg [17:0] reg_bi_21; +reg [17:0] reg_WfxrXtYt_1_21; +reg [17:0] reg_Wfc_21; +reg [17:0] reg_bf_21; +reg [17:0] reg_WoxrXtYt_1_21; +reg [17:0] reg_Woc_21; +reg [17:0] reg_bo_21; +reg [17:0] reg_WcxrXtYt_1_21; +reg [17:0] reg_bc_21; +reg [17:0] reg_out_mt_21; +reg [17:0] reg_out_ct_21; +reg [17:0] reg_Ct_1_22; +reg [17:0] reg_WixrXtYt_1_22; +reg [17:0] reg_Wic_22; +reg [17:0] reg_bi_22; +reg [17:0] reg_WfxrXtYt_1_22; +reg [17:0] reg_Wfc_22; +reg [17:0] reg_bf_22; +reg [17:0] reg_WoxrXtYt_1_22; +reg [17:0] reg_Woc_22; +reg [17:0] reg_bo_22; +reg [17:0] reg_WcxrXtYt_1_22; +reg [17:0] reg_bc_22; +reg [17:0] reg_out_mt_22; +reg [17:0] reg_out_ct_22; +reg [17:0] reg_Ct_1_23; +reg [17:0] reg_WixrXtYt_1_23; +reg [17:0] reg_Wic_23; +reg [17:0] reg_bi_23; +reg [17:0] reg_WfxrXtYt_1_23; +reg [17:0] reg_Wfc_23; +reg [17:0] reg_bf_23; +reg [17:0] reg_WoxrXtYt_1_23; +reg [17:0] reg_Woc_23; +reg [17:0] reg_bo_23; +reg [17:0] reg_WcxrXtYt_1_23; +reg [17:0] reg_bc_23; +reg [17:0] reg_out_mt_23; +reg [17:0] reg_out_ct_23; +reg [17:0] reg_Ct_1_24; +reg [17:0] reg_WixrXtYt_1_24; +reg [17:0] reg_Wic_24; +reg [17:0] reg_bi_24; +reg [17:0] reg_WfxrXtYt_1_24; +reg [17:0] reg_Wfc_24; +reg [17:0] reg_bf_24; +reg [17:0] reg_WoxrXtYt_1_24; +reg [17:0] reg_Woc_24; +reg [17:0] reg_bo_24; +reg [17:0] reg_WcxrXtYt_1_24; +reg [17:0] reg_bc_24; +reg [17:0] reg_out_mt_24; +reg [17:0] reg_out_ct_24; +reg [17:0] reg_Ct_1_25; +reg [17:0] reg_WixrXtYt_1_25; +reg [17:0] reg_Wic_25; +reg [17:0] reg_bi_25; +reg [17:0] reg_WfxrXtYt_1_25; +reg [17:0] reg_Wfc_25; +reg [17:0] reg_bf_25; +reg [17:0] reg_WoxrXtYt_1_25; +reg [17:0] reg_Woc_25; +reg [17:0] reg_bo_25; +reg [17:0] reg_WcxrXtYt_1_25; +reg [17:0] reg_bc_25; +reg [17:0] reg_out_mt_25; +reg [17:0] reg_out_ct_25; +reg [17:0] reg_Ct_1_26; +reg [17:0] reg_WixrXtYt_1_26; +reg [17:0] reg_Wic_26; +reg [17:0] reg_bi_26; +reg [17:0] reg_WfxrXtYt_1_26; +reg [17:0] reg_Wfc_26; +reg [17:0] reg_bf_26; +reg [17:0] reg_WoxrXtYt_1_26; +reg [17:0] reg_Woc_26; +reg [17:0] reg_bo_26; +reg [17:0] reg_WcxrXtYt_1_26; +reg [17:0] reg_bc_26; +reg [17:0] reg_out_mt_26; +reg [17:0] reg_out_ct_26; +reg [17:0] reg_Ct_1_27; +reg [17:0] reg_WixrXtYt_1_27; +reg [17:0] reg_Wic_27; +reg [17:0] reg_bi_27; +reg [17:0] reg_WfxrXtYt_1_27; +reg [17:0] reg_Wfc_27; +reg [17:0] reg_bf_27; +reg [17:0] reg_WoxrXtYt_1_27; +reg [17:0] reg_Woc_27; +reg [17:0] reg_bo_27; +reg [17:0] reg_WcxrXtYt_1_27; +reg [17:0] reg_bc_27; +reg [17:0] reg_out_mt_27; +reg [17:0] reg_out_ct_27; +reg [17:0] reg_Ct_1_28; +reg [17:0] reg_WixrXtYt_1_28; +reg [17:0] reg_Wic_28; +reg [17:0] reg_bi_28; +reg [17:0] reg_WfxrXtYt_1_28; +reg [17:0] reg_Wfc_28; +reg [17:0] reg_bf_28; +reg [17:0] reg_WoxrXtYt_1_28; +reg [17:0] reg_Woc_28; +reg [17:0] reg_bo_28; +reg [17:0] reg_WcxrXtYt_1_28; +reg [17:0] reg_bc_28; +reg [17:0] reg_out_mt_28; +reg [17:0] reg_out_ct_28; +reg [17:0] reg_Ct_1_29; +reg [17:0] reg_WixrXtYt_1_29; +reg [17:0] reg_Wic_29; +reg [17:0] reg_bi_29; +reg [17:0] reg_WfxrXtYt_1_29; +reg [17:0] reg_Wfc_29; +reg [17:0] reg_bf_29; +reg [17:0] reg_WoxrXtYt_1_29; +reg [17:0] reg_Woc_29; +reg [17:0] reg_bo_29; +reg [17:0] reg_WcxrXtYt_1_29; +reg [17:0] reg_bc_29; +reg [17:0] reg_out_mt_29; +reg [17:0] reg_out_ct_29; +reg [17:0] reg_Ct_1_30; +reg [17:0] reg_WixrXtYt_1_30; +reg [17:0] reg_Wic_30; +reg [17:0] reg_bi_30; +reg [17:0] reg_WfxrXtYt_1_30; +reg [17:0] reg_Wfc_30; +reg [17:0] reg_bf_30; +reg [17:0] reg_WoxrXtYt_1_30; +reg [17:0] reg_Woc_30; +reg [17:0] reg_bo_30; +reg [17:0] reg_WcxrXtYt_1_30; +reg [17:0] reg_bc_30; +reg [17:0] reg_out_mt_30; +reg [17:0] reg_out_ct_30; +reg [17:0] reg_Ct_1_31; +reg [17:0] reg_WixrXtYt_1_31; +reg [17:0] reg_Wic_31; +reg [17:0] reg_bi_31; +reg [17:0] reg_WfxrXtYt_1_31; +reg [17:0] reg_Wfc_31; +reg [17:0] reg_bf_31; +reg [17:0] reg_WoxrXtYt_1_31; +reg [17:0] reg_Woc_31; +reg [17:0] reg_bo_31; +reg [17:0] reg_WcxrXtYt_1_31; +reg [17:0] reg_bc_31; +reg [17:0] reg_out_mt_31; +reg [17:0] reg_out_ct_31; + +wire input_gate_valid, forget_gate_valid, output_gate_valid, gt_valid; +wire it_gt_mult_valid, ft_Ct_1_mult_valid; +wire ct_valid; +wire tanh_valid_0; +wire [17:0] o_Ct_1_0; +wire [17:0] Ct_1_hold_0; +wire [17:0] o_input_gate_0; +wire [17:0] o_forget_gate_0; +wire [17:0] o_output_gate_0; +wire [17:0] ot_hold_0; +wire [17:0] o_gt_0; +wire [17:0] gt_hold_0; +wire [17:0] o_it_gt_mult_0; +wire [17:0] o_ft_Ct_1_mult_0; +wire [17:0] o_ct_0; +wire [17:0] ct_hold_0; +wire [17:0] o_tanh_0; +wire [17:0] o_mt_0; +wire tanh_valid_1; +wire [17:0] o_Ct_1_1; +wire [17:0] Ct_1_hold_1; +wire [17:0] o_input_gate_1; +wire [17:0] o_forget_gate_1; +wire [17:0] o_output_gate_1; +wire [17:0] ot_hold_1; +wire [17:0] o_gt_1; +wire [17:0] gt_hold_1; +wire [17:0] o_it_gt_mult_1; +wire [17:0] o_ft_Ct_1_mult_1; +wire [17:0] o_ct_1; +wire [17:0] ct_hold_1; +wire [17:0] o_tanh_1; +wire [17:0] o_mt_1; +wire tanh_valid_2; +wire [17:0] o_Ct_1_2; +wire [17:0] Ct_1_hold_2; +wire [17:0] o_input_gate_2; +wire [17:0] o_forget_gate_2; +wire [17:0] o_output_gate_2; +wire [17:0] ot_hold_2; +wire [17:0] o_gt_2; +wire [17:0] gt_hold_2; +wire [17:0] o_it_gt_mult_2; +wire [17:0] o_ft_Ct_1_mult_2; +wire [17:0] o_ct_2; +wire [17:0] ct_hold_2; +wire [17:0] o_tanh_2; +wire [17:0] o_mt_2; +wire tanh_valid_3; +wire [17:0] o_Ct_1_3; +wire [17:0] Ct_1_hold_3; +wire [17:0] o_input_gate_3; +wire [17:0] o_forget_gate_3; +wire [17:0] o_output_gate_3; +wire [17:0] ot_hold_3; +wire [17:0] o_gt_3; +wire [17:0] gt_hold_3; +wire [17:0] o_it_gt_mult_3; +wire [17:0] o_ft_Ct_1_mult_3; +wire [17:0] o_ct_3; +wire [17:0] ct_hold_3; +wire [17:0] o_tanh_3; +wire [17:0] o_mt_3; +wire tanh_valid_4; +wire [17:0] o_Ct_1_4; +wire [17:0] Ct_1_hold_4; +wire [17:0] o_input_gate_4; +wire [17:0] o_forget_gate_4; +wire [17:0] o_output_gate_4; +wire [17:0] ot_hold_4; +wire [17:0] o_gt_4; +wire [17:0] gt_hold_4; +wire [17:0] o_it_gt_mult_4; +wire [17:0] o_ft_Ct_1_mult_4; +wire [17:0] o_ct_4; +wire [17:0] ct_hold_4; +wire [17:0] o_tanh_4; +wire [17:0] o_mt_4; +wire tanh_valid_5; +wire [17:0] o_Ct_1_5; +wire [17:0] Ct_1_hold_5; +wire [17:0] o_input_gate_5; +wire [17:0] o_forget_gate_5; +wire [17:0] o_output_gate_5; +wire [17:0] ot_hold_5; +wire [17:0] o_gt_5; +wire [17:0] gt_hold_5; +wire [17:0] o_it_gt_mult_5; +wire [17:0] o_ft_Ct_1_mult_5; +wire [17:0] o_ct_5; +wire [17:0] ct_hold_5; +wire [17:0] o_tanh_5; +wire [17:0] o_mt_5; +wire tanh_valid_6; +wire [17:0] o_Ct_1_6; +wire [17:0] Ct_1_hold_6; +wire [17:0] o_input_gate_6; +wire [17:0] o_forget_gate_6; +wire [17:0] o_output_gate_6; +wire [17:0] ot_hold_6; +wire [17:0] o_gt_6; +wire [17:0] gt_hold_6; +wire [17:0] o_it_gt_mult_6; +wire [17:0] o_ft_Ct_1_mult_6; +wire [17:0] o_ct_6; +wire [17:0] ct_hold_6; +wire [17:0] o_tanh_6; +wire [17:0] o_mt_6; +wire tanh_valid_7; +wire [17:0] o_Ct_1_7; +wire [17:0] Ct_1_hold_7; +wire [17:0] o_input_gate_7; +wire [17:0] o_forget_gate_7; +wire [17:0] o_output_gate_7; +wire [17:0] ot_hold_7; +wire [17:0] o_gt_7; +wire [17:0] gt_hold_7; +wire [17:0] o_it_gt_mult_7; +wire [17:0] o_ft_Ct_1_mult_7; +wire [17:0] o_ct_7; +wire [17:0] ct_hold_7; +wire [17:0] o_tanh_7; +wire [17:0] o_mt_7; +wire tanh_valid_8; +wire [17:0] o_Ct_1_8; +wire [17:0] Ct_1_hold_8; +wire [17:0] o_input_gate_8; +wire [17:0] o_forget_gate_8; +wire [17:0] o_output_gate_8; +wire [17:0] ot_hold_8; +wire [17:0] o_gt_8; +wire [17:0] gt_hold_8; +wire [17:0] o_it_gt_mult_8; +wire [17:0] o_ft_Ct_1_mult_8; +wire [17:0] o_ct_8; +wire [17:0] ct_hold_8; +wire [17:0] o_tanh_8; +wire [17:0] o_mt_8; +wire tanh_valid_9; +wire [17:0] o_Ct_1_9; +wire [17:0] Ct_1_hold_9; +wire [17:0] o_input_gate_9; +wire [17:0] o_forget_gate_9; +wire [17:0] o_output_gate_9; +wire [17:0] ot_hold_9; +wire [17:0] o_gt_9; +wire [17:0] gt_hold_9; +wire [17:0] o_it_gt_mult_9; +wire [17:0] o_ft_Ct_1_mult_9; +wire [17:0] o_ct_9; +wire [17:0] ct_hold_9; +wire [17:0] o_tanh_9; +wire [17:0] o_mt_9; +wire tanh_valid_10; +wire [17:0] o_Ct_1_10; +wire [17:0] Ct_1_hold_10; +wire [17:0] o_input_gate_10; +wire [17:0] o_forget_gate_10; +wire [17:0] o_output_gate_10; +wire [17:0] ot_hold_10; +wire [17:0] o_gt_10; +wire [17:0] gt_hold_10; +wire [17:0] o_it_gt_mult_10; +wire [17:0] o_ft_Ct_1_mult_10; +wire [17:0] o_ct_10; +wire [17:0] ct_hold_10; +wire [17:0] o_tanh_10; +wire [17:0] o_mt_10; +wire tanh_valid_11; +wire [17:0] o_Ct_1_11; +wire [17:0] Ct_1_hold_11; +wire [17:0] o_input_gate_11; +wire [17:0] o_forget_gate_11; +wire [17:0] o_output_gate_11; +wire [17:0] ot_hold_11; +wire [17:0] o_gt_11; +wire [17:0] gt_hold_11; +wire [17:0] o_it_gt_mult_11; +wire [17:0] o_ft_Ct_1_mult_11; +wire [17:0] o_ct_11; +wire [17:0] ct_hold_11; +wire [17:0] o_tanh_11; +wire [17:0] o_mt_11; +wire tanh_valid_12; +wire [17:0] o_Ct_1_12; +wire [17:0] Ct_1_hold_12; +wire [17:0] o_input_gate_12; +wire [17:0] o_forget_gate_12; +wire [17:0] o_output_gate_12; +wire [17:0] ot_hold_12; +wire [17:0] o_gt_12; +wire [17:0] gt_hold_12; +wire [17:0] o_it_gt_mult_12; +wire [17:0] o_ft_Ct_1_mult_12; +wire [17:0] o_ct_12; +wire [17:0] ct_hold_12; +wire [17:0] o_tanh_12; +wire [17:0] o_mt_12; +wire tanh_valid_13; +wire [17:0] o_Ct_1_13; +wire [17:0] Ct_1_hold_13; +wire [17:0] o_input_gate_13; +wire [17:0] o_forget_gate_13; +wire [17:0] o_output_gate_13; +wire [17:0] ot_hold_13; +wire [17:0] o_gt_13; +wire [17:0] gt_hold_13; +wire [17:0] o_it_gt_mult_13; +wire [17:0] o_ft_Ct_1_mult_13; +wire [17:0] o_ct_13; +wire [17:0] ct_hold_13; +wire [17:0] o_tanh_13; +wire [17:0] o_mt_13; +wire tanh_valid_14; +wire [17:0] o_Ct_1_14; +wire [17:0] Ct_1_hold_14; +wire [17:0] o_input_gate_14; +wire [17:0] o_forget_gate_14; +wire [17:0] o_output_gate_14; +wire [17:0] ot_hold_14; +wire [17:0] o_gt_14; +wire [17:0] gt_hold_14; +wire [17:0] o_it_gt_mult_14; +wire [17:0] o_ft_Ct_1_mult_14; +wire [17:0] o_ct_14; +wire [17:0] ct_hold_14; +wire [17:0] o_tanh_14; +wire [17:0] o_mt_14; +wire tanh_valid_15; +wire [17:0] o_Ct_1_15; +wire [17:0] Ct_1_hold_15; +wire [17:0] o_input_gate_15; +wire [17:0] o_forget_gate_15; +wire [17:0] o_output_gate_15; +wire [17:0] ot_hold_15; +wire [17:0] o_gt_15; +wire [17:0] gt_hold_15; +wire [17:0] o_it_gt_mult_15; +wire [17:0] o_ft_Ct_1_mult_15; +wire [17:0] o_ct_15; +wire [17:0] ct_hold_15; +wire [17:0] o_tanh_15; +wire [17:0] o_mt_15; +wire tanh_valid_16; +wire [17:0] o_Ct_1_16; +wire [17:0] Ct_1_hold_16; +wire [17:0] o_input_gate_16; +wire [17:0] o_forget_gate_16; +wire [17:0] o_output_gate_16; +wire [17:0] ot_hold_16; +wire [17:0] o_gt_16; +wire [17:0] gt_hold_16; +wire [17:0] o_it_gt_mult_16; +wire [17:0] o_ft_Ct_1_mult_16; +wire [17:0] o_ct_16; +wire [17:0] ct_hold_16; +wire [17:0] o_tanh_16; +wire [17:0] o_mt_16; +wire tanh_valid_17; +wire [17:0] o_Ct_1_17; +wire [17:0] Ct_1_hold_17; +wire [17:0] o_input_gate_17; +wire [17:0] o_forget_gate_17; +wire [17:0] o_output_gate_17; +wire [17:0] ot_hold_17; +wire [17:0] o_gt_17; +wire [17:0] gt_hold_17; +wire [17:0] o_it_gt_mult_17; +wire [17:0] o_ft_Ct_1_mult_17; +wire [17:0] o_ct_17; +wire [17:0] ct_hold_17; +wire [17:0] o_tanh_17; +wire [17:0] o_mt_17; +wire tanh_valid_18; +wire [17:0] o_Ct_1_18; +wire [17:0] Ct_1_hold_18; +wire [17:0] o_input_gate_18; +wire [17:0] o_forget_gate_18; +wire [17:0] o_output_gate_18; +wire [17:0] ot_hold_18; +wire [17:0] o_gt_18; +wire [17:0] gt_hold_18; +wire [17:0] o_it_gt_mult_18; +wire [17:0] o_ft_Ct_1_mult_18; +wire [17:0] o_ct_18; +wire [17:0] ct_hold_18; +wire [17:0] o_tanh_18; +wire [17:0] o_mt_18; +wire tanh_valid_19; +wire [17:0] o_Ct_1_19; +wire [17:0] Ct_1_hold_19; +wire [17:0] o_input_gate_19; +wire [17:0] o_forget_gate_19; +wire [17:0] o_output_gate_19; +wire [17:0] ot_hold_19; +wire [17:0] o_gt_19; +wire [17:0] gt_hold_19; +wire [17:0] o_it_gt_mult_19; +wire [17:0] o_ft_Ct_1_mult_19; +wire [17:0] o_ct_19; +wire [17:0] ct_hold_19; +wire [17:0] o_tanh_19; +wire [17:0] o_mt_19; +wire tanh_valid_20; +wire [17:0] o_Ct_1_20; +wire [17:0] Ct_1_hold_20; +wire [17:0] o_input_gate_20; +wire [17:0] o_forget_gate_20; +wire [17:0] o_output_gate_20; +wire [17:0] ot_hold_20; +wire [17:0] o_gt_20; +wire [17:0] gt_hold_20; +wire [17:0] o_it_gt_mult_20; +wire [17:0] o_ft_Ct_1_mult_20; +wire [17:0] o_ct_20; +wire [17:0] ct_hold_20; +wire [17:0] o_tanh_20; +wire [17:0] o_mt_20; +wire tanh_valid_21; +wire [17:0] o_Ct_1_21; +wire [17:0] Ct_1_hold_21; +wire [17:0] o_input_gate_21; +wire [17:0] o_forget_gate_21; +wire [17:0] o_output_gate_21; +wire [17:0] ot_hold_21; +wire [17:0] o_gt_21; +wire [17:0] gt_hold_21; +wire [17:0] o_it_gt_mult_21; +wire [17:0] o_ft_Ct_1_mult_21; +wire [17:0] o_ct_21; +wire [17:0] ct_hold_21; +wire [17:0] o_tanh_21; +wire [17:0] o_mt_21; +wire tanh_valid_22; +wire [17:0] o_Ct_1_22; +wire [17:0] Ct_1_hold_22; +wire [17:0] o_input_gate_22; +wire [17:0] o_forget_gate_22; +wire [17:0] o_output_gate_22; +wire [17:0] ot_hold_22; +wire [17:0] o_gt_22; +wire [17:0] gt_hold_22; +wire [17:0] o_it_gt_mult_22; +wire [17:0] o_ft_Ct_1_mult_22; +wire [17:0] o_ct_22; +wire [17:0] ct_hold_22; +wire [17:0] o_tanh_22; +wire [17:0] o_mt_22; +wire tanh_valid_23; +wire [17:0] o_Ct_1_23; +wire [17:0] Ct_1_hold_23; +wire [17:0] o_input_gate_23; +wire [17:0] o_forget_gate_23; +wire [17:0] o_output_gate_23; +wire [17:0] ot_hold_23; +wire [17:0] o_gt_23; +wire [17:0] gt_hold_23; +wire [17:0] o_it_gt_mult_23; +wire [17:0] o_ft_Ct_1_mult_23; +wire [17:0] o_ct_23; +wire [17:0] ct_hold_23; +wire [17:0] o_tanh_23; +wire [17:0] o_mt_23; +wire tanh_valid_24; +wire [17:0] o_Ct_1_24; +wire [17:0] Ct_1_hold_24; +wire [17:0] o_input_gate_24; +wire [17:0] o_forget_gate_24; +wire [17:0] o_output_gate_24; +wire [17:0] ot_hold_24; +wire [17:0] o_gt_24; +wire [17:0] gt_hold_24; +wire [17:0] o_it_gt_mult_24; +wire [17:0] o_ft_Ct_1_mult_24; +wire [17:0] o_ct_24; +wire [17:0] ct_hold_24; +wire [17:0] o_tanh_24; +wire [17:0] o_mt_24; +wire tanh_valid_25; +wire [17:0] o_Ct_1_25; +wire [17:0] Ct_1_hold_25; +wire [17:0] o_input_gate_25; +wire [17:0] o_forget_gate_25; +wire [17:0] o_output_gate_25; +wire [17:0] ot_hold_25; +wire [17:0] o_gt_25; +wire [17:0] gt_hold_25; +wire [17:0] o_it_gt_mult_25; +wire [17:0] o_ft_Ct_1_mult_25; +wire [17:0] o_ct_25; +wire [17:0] ct_hold_25; +wire [17:0] o_tanh_25; +wire [17:0] o_mt_25; +wire tanh_valid_26; +wire [17:0] o_Ct_1_26; +wire [17:0] Ct_1_hold_26; +wire [17:0] o_input_gate_26; +wire [17:0] o_forget_gate_26; +wire [17:0] o_output_gate_26; +wire [17:0] ot_hold_26; +wire [17:0] o_gt_26; +wire [17:0] gt_hold_26; +wire [17:0] o_it_gt_mult_26; +wire [17:0] o_ft_Ct_1_mult_26; +wire [17:0] o_ct_26; +wire [17:0] ct_hold_26; +wire [17:0] o_tanh_26; +wire [17:0] o_mt_26; +wire tanh_valid_27; +wire [17:0] o_Ct_1_27; +wire [17:0] Ct_1_hold_27; +wire [17:0] o_input_gate_27; +wire [17:0] o_forget_gate_27; +wire [17:0] o_output_gate_27; +wire [17:0] ot_hold_27; +wire [17:0] o_gt_27; +wire [17:0] gt_hold_27; +wire [17:0] o_it_gt_mult_27; +wire [17:0] o_ft_Ct_1_mult_27; +wire [17:0] o_ct_27; +wire [17:0] ct_hold_27; +wire [17:0] o_tanh_27; +wire [17:0] o_mt_27; +wire tanh_valid_28; +wire [17:0] o_Ct_1_28; +wire [17:0] Ct_1_hold_28; +wire [17:0] o_input_gate_28; +wire [17:0] o_forget_gate_28; +wire [17:0] o_output_gate_28; +wire [17:0] ot_hold_28; +wire [17:0] o_gt_28; +wire [17:0] gt_hold_28; +wire [17:0] o_it_gt_mult_28; +wire [17:0] o_ft_Ct_1_mult_28; +wire [17:0] o_ct_28; +wire [17:0] ct_hold_28; +wire [17:0] o_tanh_28; +wire [17:0] o_mt_28; +wire tanh_valid_29; +wire [17:0] o_Ct_1_29; +wire [17:0] Ct_1_hold_29; +wire [17:0] o_input_gate_29; +wire [17:0] o_forget_gate_29; +wire [17:0] o_output_gate_29; +wire [17:0] ot_hold_29; +wire [17:0] o_gt_29; +wire [17:0] gt_hold_29; +wire [17:0] o_it_gt_mult_29; +wire [17:0] o_ft_Ct_1_mult_29; +wire [17:0] o_ct_29; +wire [17:0] ct_hold_29; +wire [17:0] o_tanh_29; +wire [17:0] o_mt_29; +wire tanh_valid_30; +wire [17:0] o_Ct_1_30; +wire [17:0] Ct_1_hold_30; +wire [17:0] o_input_gate_30; +wire [17:0] o_forget_gate_30; +wire [17:0] o_output_gate_30; +wire [17:0] ot_hold_30; +wire [17:0] o_gt_30; +wire [17:0] gt_hold_30; +wire [17:0] o_it_gt_mult_30; +wire [17:0] o_ft_Ct_1_mult_30; +wire [17:0] o_ct_30; +wire [17:0] ct_hold_30; +wire [17:0] o_tanh_30; +wire [17:0] o_mt_30; +wire tanh_valid_31; +wire [17:0] o_Ct_1_31; +wire [17:0] Ct_1_hold_31; +wire [17:0] o_input_gate_31; +wire [17:0] o_forget_gate_31; +wire [17:0] o_output_gate_31; +wire [17:0] ot_hold_31; +wire [17:0] o_gt_31; +wire [17:0] gt_hold_31; +wire [17:0] o_it_gt_mult_31; +wire [17:0] o_ft_Ct_1_mult_31; +wire [17:0] o_ct_31; +wire [17:0] ct_hold_31; +wire [17:0] o_tanh_31; +wire [17:0] o_mt_31; +wire mt_valid; + +assign o_Ct_1_0 = reg_Ct_1_0; +assign o_Ct_1_1 = reg_Ct_1_1; +assign o_Ct_1_2 = reg_Ct_1_2; +assign o_Ct_1_3 = reg_Ct_1_3; +assign o_Ct_1_4 = reg_Ct_1_4; +assign o_Ct_1_5 = reg_Ct_1_5; +assign o_Ct_1_6 = reg_Ct_1_6; +assign o_Ct_1_7 = reg_Ct_1_7; +assign o_Ct_1_8 = reg_Ct_1_8; +assign o_Ct_1_9 = reg_Ct_1_9; +assign o_Ct_1_10 = reg_Ct_1_10; +assign o_Ct_1_11 = reg_Ct_1_11; +assign o_Ct_1_12 = reg_Ct_1_12; +assign o_Ct_1_13 = reg_Ct_1_13; +assign o_Ct_1_14 = reg_Ct_1_14; +assign o_Ct_1_15 = reg_Ct_1_15; +assign o_Ct_1_16 = reg_Ct_1_16; +assign o_Ct_1_17 = reg_Ct_1_17; +assign o_Ct_1_18 = reg_Ct_1_18; +assign o_Ct_1_19 = reg_Ct_1_19; +assign o_Ct_1_20 = reg_Ct_1_20; +assign o_Ct_1_21 = reg_Ct_1_21; +assign o_Ct_1_22 = reg_Ct_1_22; +assign o_Ct_1_23 = reg_Ct_1_23; +assign o_Ct_1_24 = reg_Ct_1_24; +assign o_Ct_1_25 = reg_Ct_1_25; +assign o_Ct_1_26 = reg_Ct_1_26; +assign o_Ct_1_27 = reg_Ct_1_27; +assign o_Ct_1_28 = reg_Ct_1_28; +assign o_Ct_1_29 = reg_Ct_1_29; +assign o_Ct_1_30 = reg_Ct_1_30; +assign o_Ct_1_31 = reg_Ct_1_31; +lstm_gate_18_10_32_1 lstm_gate_18_10_32_1_input ( + .clk(clk), + .reset(reset), + .i_ready(enable), + .i_valid(reg_i_valid), + .stage1_result_0(reg_WixrXtYt_1_0), + .weight_0(reg_Wic_0), + .Ct_1_0(reg_Ct_1_0), + .bias_0(reg_bi_0), + .gate_output_0(o_input_gate_0), + .stage1_result_1(reg_WixrXtYt_1_1), + .weight_1(reg_Wic_1), + .Ct_1_1(reg_Ct_1_1), + .bias_1(reg_bi_1), + .gate_output_1(o_input_gate_1), + .stage1_result_2(reg_WixrXtYt_1_2), + .weight_2(reg_Wic_2), + .Ct_1_2(reg_Ct_1_2), + .bias_2(reg_bi_2), + .gate_output_2(o_input_gate_2), + .stage1_result_3(reg_WixrXtYt_1_3), + .weight_3(reg_Wic_3), + .Ct_1_3(reg_Ct_1_3), + .bias_3(reg_bi_3), + .gate_output_3(o_input_gate_3), + .stage1_result_4(reg_WixrXtYt_1_4), + .weight_4(reg_Wic_4), + .Ct_1_4(reg_Ct_1_4), + .bias_4(reg_bi_4), + .gate_output_4(o_input_gate_4), + .stage1_result_5(reg_WixrXtYt_1_5), + .weight_5(reg_Wic_5), + .Ct_1_5(reg_Ct_1_5), + .bias_5(reg_bi_5), + .gate_output_5(o_input_gate_5), + .stage1_result_6(reg_WixrXtYt_1_6), + .weight_6(reg_Wic_6), + .Ct_1_6(reg_Ct_1_6), + .bias_6(reg_bi_6), + .gate_output_6(o_input_gate_6), + .stage1_result_7(reg_WixrXtYt_1_7), + .weight_7(reg_Wic_7), + .Ct_1_7(reg_Ct_1_7), + .bias_7(reg_bi_7), + .gate_output_7(o_input_gate_7), + .stage1_result_8(reg_WixrXtYt_1_8), + .weight_8(reg_Wic_8), + .Ct_1_8(reg_Ct_1_8), + .bias_8(reg_bi_8), + .gate_output_8(o_input_gate_8), + .stage1_result_9(reg_WixrXtYt_1_9), + .weight_9(reg_Wic_9), + .Ct_1_9(reg_Ct_1_9), + .bias_9(reg_bi_9), + .gate_output_9(o_input_gate_9), + .stage1_result_10(reg_WixrXtYt_1_10), + .weight_10(reg_Wic_10), + .Ct_1_10(reg_Ct_1_10), + .bias_10(reg_bi_10), + .gate_output_10(o_input_gate_10), + .stage1_result_11(reg_WixrXtYt_1_11), + .weight_11(reg_Wic_11), + .Ct_1_11(reg_Ct_1_11), + .bias_11(reg_bi_11), + .gate_output_11(o_input_gate_11), + .stage1_result_12(reg_WixrXtYt_1_12), + .weight_12(reg_Wic_12), + .Ct_1_12(reg_Ct_1_12), + .bias_12(reg_bi_12), + .gate_output_12(o_input_gate_12), + .stage1_result_13(reg_WixrXtYt_1_13), + .weight_13(reg_Wic_13), + .Ct_1_13(reg_Ct_1_13), + .bias_13(reg_bi_13), + .gate_output_13(o_input_gate_13), + .stage1_result_14(reg_WixrXtYt_1_14), + .weight_14(reg_Wic_14), + .Ct_1_14(reg_Ct_1_14), + .bias_14(reg_bi_14), + .gate_output_14(o_input_gate_14), + .stage1_result_15(reg_WixrXtYt_1_15), + .weight_15(reg_Wic_15), + .Ct_1_15(reg_Ct_1_15), + .bias_15(reg_bi_15), + .gate_output_15(o_input_gate_15), + .stage1_result_16(reg_WixrXtYt_1_16), + .weight_16(reg_Wic_16), + .Ct_1_16(reg_Ct_1_16), + .bias_16(reg_bi_16), + .gate_output_16(o_input_gate_16), + .stage1_result_17(reg_WixrXtYt_1_17), + .weight_17(reg_Wic_17), + .Ct_1_17(reg_Ct_1_17), + .bias_17(reg_bi_17), + .gate_output_17(o_input_gate_17), + .stage1_result_18(reg_WixrXtYt_1_18), + .weight_18(reg_Wic_18), + .Ct_1_18(reg_Ct_1_18), + .bias_18(reg_bi_18), + .gate_output_18(o_input_gate_18), + .stage1_result_19(reg_WixrXtYt_1_19), + .weight_19(reg_Wic_19), + .Ct_1_19(reg_Ct_1_19), + .bias_19(reg_bi_19), + .gate_output_19(o_input_gate_19), + .stage1_result_20(reg_WixrXtYt_1_20), + .weight_20(reg_Wic_20), + .Ct_1_20(reg_Ct_1_20), + .bias_20(reg_bi_20), + .gate_output_20(o_input_gate_20), + .stage1_result_21(reg_WixrXtYt_1_21), + .weight_21(reg_Wic_21), + .Ct_1_21(reg_Ct_1_21), + .bias_21(reg_bi_21), + .gate_output_21(o_input_gate_21), + .stage1_result_22(reg_WixrXtYt_1_22), + .weight_22(reg_Wic_22), + .Ct_1_22(reg_Ct_1_22), + .bias_22(reg_bi_22), + .gate_output_22(o_input_gate_22), + .stage1_result_23(reg_WixrXtYt_1_23), + .weight_23(reg_Wic_23), + .Ct_1_23(reg_Ct_1_23), + .bias_23(reg_bi_23), + .gate_output_23(o_input_gate_23), + .stage1_result_24(reg_WixrXtYt_1_24), + .weight_24(reg_Wic_24), + .Ct_1_24(reg_Ct_1_24), + .bias_24(reg_bi_24), + .gate_output_24(o_input_gate_24), + .stage1_result_25(reg_WixrXtYt_1_25), + .weight_25(reg_Wic_25), + .Ct_1_25(reg_Ct_1_25), + .bias_25(reg_bi_25), + .gate_output_25(o_input_gate_25), + .stage1_result_26(reg_WixrXtYt_1_26), + .weight_26(reg_Wic_26), + .Ct_1_26(reg_Ct_1_26), + .bias_26(reg_bi_26), + .gate_output_26(o_input_gate_26), + .stage1_result_27(reg_WixrXtYt_1_27), + .weight_27(reg_Wic_27), + .Ct_1_27(reg_Ct_1_27), + .bias_27(reg_bi_27), + .gate_output_27(o_input_gate_27), + .stage1_result_28(reg_WixrXtYt_1_28), + .weight_28(reg_Wic_28), + .Ct_1_28(reg_Ct_1_28), + .bias_28(reg_bi_28), + .gate_output_28(o_input_gate_28), + .stage1_result_29(reg_WixrXtYt_1_29), + .weight_29(reg_Wic_29), + .Ct_1_29(reg_Ct_1_29), + .bias_29(reg_bi_29), + .gate_output_29(o_input_gate_29), + .stage1_result_30(reg_WixrXtYt_1_30), + .weight_30(reg_Wic_30), + .Ct_1_30(reg_Ct_1_30), + .bias_30(reg_bi_30), + .gate_output_30(o_input_gate_30), + .stage1_result_31(reg_WixrXtYt_1_31), + .weight_31(reg_Wic_31), + .Ct_1_31(reg_Ct_1_31), + .bias_31(reg_bi_31), + .gate_output_31(o_input_gate_31), + .o_valid(input_gate_valid), + .o_ready() +); + +lstm_gate_18_10_32_1 lstm_gate_18_10_32_1_forget ( + .clk(clk), + .reset(reset), + .i_ready(enable), + .i_valid(reg_i_valid), + .stage1_result_0(reg_WfxrXtYt_1_0), + .weight_0(reg_Wfc_0), + .Ct_1_0(reg_Ct_1_0), + .bias_0(reg_bf_0), + .gate_output_0(o_forget_gate_0), + .stage1_result_1(reg_WfxrXtYt_1_1), + .weight_1(reg_Wfc_1), + .Ct_1_1(reg_Ct_1_1), + .bias_1(reg_bf_1), + .gate_output_1(o_forget_gate_1), + .stage1_result_2(reg_WfxrXtYt_1_2), + .weight_2(reg_Wfc_2), + .Ct_1_2(reg_Ct_1_2), + .bias_2(reg_bf_2), + .gate_output_2(o_forget_gate_2), + .stage1_result_3(reg_WfxrXtYt_1_3), + .weight_3(reg_Wfc_3), + .Ct_1_3(reg_Ct_1_3), + .bias_3(reg_bf_3), + .gate_output_3(o_forget_gate_3), + .stage1_result_4(reg_WfxrXtYt_1_4), + .weight_4(reg_Wfc_4), + .Ct_1_4(reg_Ct_1_4), + .bias_4(reg_bf_4), + .gate_output_4(o_forget_gate_4), + .stage1_result_5(reg_WfxrXtYt_1_5), + .weight_5(reg_Wfc_5), + .Ct_1_5(reg_Ct_1_5), + .bias_5(reg_bf_5), + .gate_output_5(o_forget_gate_5), + .stage1_result_6(reg_WfxrXtYt_1_6), + .weight_6(reg_Wfc_6), + .Ct_1_6(reg_Ct_1_6), + .bias_6(reg_bf_6), + .gate_output_6(o_forget_gate_6), + .stage1_result_7(reg_WfxrXtYt_1_7), + .weight_7(reg_Wfc_7), + .Ct_1_7(reg_Ct_1_7), + .bias_7(reg_bf_7), + .gate_output_7(o_forget_gate_7), + .stage1_result_8(reg_WfxrXtYt_1_8), + .weight_8(reg_Wfc_8), + .Ct_1_8(reg_Ct_1_8), + .bias_8(reg_bf_8), + .gate_output_8(o_forget_gate_8), + .stage1_result_9(reg_WfxrXtYt_1_9), + .weight_9(reg_Wfc_9), + .Ct_1_9(reg_Ct_1_9), + .bias_9(reg_bf_9), + .gate_output_9(o_forget_gate_9), + .stage1_result_10(reg_WfxrXtYt_1_10), + .weight_10(reg_Wfc_10), + .Ct_1_10(reg_Ct_1_10), + .bias_10(reg_bf_10), + .gate_output_10(o_forget_gate_10), + .stage1_result_11(reg_WfxrXtYt_1_11), + .weight_11(reg_Wfc_11), + .Ct_1_11(reg_Ct_1_11), + .bias_11(reg_bf_11), + .gate_output_11(o_forget_gate_11), + .stage1_result_12(reg_WfxrXtYt_1_12), + .weight_12(reg_Wfc_12), + .Ct_1_12(reg_Ct_1_12), + .bias_12(reg_bf_12), + .gate_output_12(o_forget_gate_12), + .stage1_result_13(reg_WfxrXtYt_1_13), + .weight_13(reg_Wfc_13), + .Ct_1_13(reg_Ct_1_13), + .bias_13(reg_bf_13), + .gate_output_13(o_forget_gate_13), + .stage1_result_14(reg_WfxrXtYt_1_14), + .weight_14(reg_Wfc_14), + .Ct_1_14(reg_Ct_1_14), + .bias_14(reg_bf_14), + .gate_output_14(o_forget_gate_14), + .stage1_result_15(reg_WfxrXtYt_1_15), + .weight_15(reg_Wfc_15), + .Ct_1_15(reg_Ct_1_15), + .bias_15(reg_bf_15), + .gate_output_15(o_forget_gate_15), + .stage1_result_16(reg_WfxrXtYt_1_16), + .weight_16(reg_Wfc_16), + .Ct_1_16(reg_Ct_1_16), + .bias_16(reg_bf_16), + .gate_output_16(o_forget_gate_16), + .stage1_result_17(reg_WfxrXtYt_1_17), + .weight_17(reg_Wfc_17), + .Ct_1_17(reg_Ct_1_17), + .bias_17(reg_bf_17), + .gate_output_17(o_forget_gate_17), + .stage1_result_18(reg_WfxrXtYt_1_18), + .weight_18(reg_Wfc_18), + .Ct_1_18(reg_Ct_1_18), + .bias_18(reg_bf_18), + .gate_output_18(o_forget_gate_18), + .stage1_result_19(reg_WfxrXtYt_1_19), + .weight_19(reg_Wfc_19), + .Ct_1_19(reg_Ct_1_19), + .bias_19(reg_bf_19), + .gate_output_19(o_forget_gate_19), + .stage1_result_20(reg_WfxrXtYt_1_20), + .weight_20(reg_Wfc_20), + .Ct_1_20(reg_Ct_1_20), + .bias_20(reg_bf_20), + .gate_output_20(o_forget_gate_20), + .stage1_result_21(reg_WfxrXtYt_1_21), + .weight_21(reg_Wfc_21), + .Ct_1_21(reg_Ct_1_21), + .bias_21(reg_bf_21), + .gate_output_21(o_forget_gate_21), + .stage1_result_22(reg_WfxrXtYt_1_22), + .weight_22(reg_Wfc_22), + .Ct_1_22(reg_Ct_1_22), + .bias_22(reg_bf_22), + .gate_output_22(o_forget_gate_22), + .stage1_result_23(reg_WfxrXtYt_1_23), + .weight_23(reg_Wfc_23), + .Ct_1_23(reg_Ct_1_23), + .bias_23(reg_bf_23), + .gate_output_23(o_forget_gate_23), + .stage1_result_24(reg_WfxrXtYt_1_24), + .weight_24(reg_Wfc_24), + .Ct_1_24(reg_Ct_1_24), + .bias_24(reg_bf_24), + .gate_output_24(o_forget_gate_24), + .stage1_result_25(reg_WfxrXtYt_1_25), + .weight_25(reg_Wfc_25), + .Ct_1_25(reg_Ct_1_25), + .bias_25(reg_bf_25), + .gate_output_25(o_forget_gate_25), + .stage1_result_26(reg_WfxrXtYt_1_26), + .weight_26(reg_Wfc_26), + .Ct_1_26(reg_Ct_1_26), + .bias_26(reg_bf_26), + .gate_output_26(o_forget_gate_26), + .stage1_result_27(reg_WfxrXtYt_1_27), + .weight_27(reg_Wfc_27), + .Ct_1_27(reg_Ct_1_27), + .bias_27(reg_bf_27), + .gate_output_27(o_forget_gate_27), + .stage1_result_28(reg_WfxrXtYt_1_28), + .weight_28(reg_Wfc_28), + .Ct_1_28(reg_Ct_1_28), + .bias_28(reg_bf_28), + .gate_output_28(o_forget_gate_28), + .stage1_result_29(reg_WfxrXtYt_1_29), + .weight_29(reg_Wfc_29), + .Ct_1_29(reg_Ct_1_29), + .bias_29(reg_bf_29), + .gate_output_29(o_forget_gate_29), + .stage1_result_30(reg_WfxrXtYt_1_30), + .weight_30(reg_Wfc_30), + .Ct_1_30(reg_Ct_1_30), + .bias_30(reg_bf_30), + .gate_output_30(o_forget_gate_30), + .stage1_result_31(reg_WfxrXtYt_1_31), + .weight_31(reg_Wfc_31), + .Ct_1_31(reg_Ct_1_31), + .bias_31(reg_bf_31), + .gate_output_31(o_forget_gate_31), + .o_valid(forget_gate_valid), + .o_ready() +); + +lstm_gate_18_10_32_1 lstm_gate_18_10_32_1_output ( + .clk(clk), + .reset(reset), + .i_ready(enable), + .i_valid(reg_i_valid), + .stage1_result_0(reg_WoxrXtYt_1_0), + .weight_0(reg_Woc_0), + .Ct_1_0(reg_Ct_1_0), + .bias_0(reg_bo_0), + .gate_output_0(o_output_gate_0), + .stage1_result_1(reg_WoxrXtYt_1_1), + .weight_1(reg_Woc_1), + .Ct_1_1(reg_Ct_1_1), + .bias_1(reg_bo_1), + .gate_output_1(o_output_gate_1), + .stage1_result_2(reg_WoxrXtYt_1_2), + .weight_2(reg_Woc_2), + .Ct_1_2(reg_Ct_1_2), + .bias_2(reg_bo_2), + .gate_output_2(o_output_gate_2), + .stage1_result_3(reg_WoxrXtYt_1_3), + .weight_3(reg_Woc_3), + .Ct_1_3(reg_Ct_1_3), + .bias_3(reg_bo_3), + .gate_output_3(o_output_gate_3), + .stage1_result_4(reg_WoxrXtYt_1_4), + .weight_4(reg_Woc_4), + .Ct_1_4(reg_Ct_1_4), + .bias_4(reg_bo_4), + .gate_output_4(o_output_gate_4), + .stage1_result_5(reg_WoxrXtYt_1_5), + .weight_5(reg_Woc_5), + .Ct_1_5(reg_Ct_1_5), + .bias_5(reg_bo_5), + .gate_output_5(o_output_gate_5), + .stage1_result_6(reg_WoxrXtYt_1_6), + .weight_6(reg_Woc_6), + .Ct_1_6(reg_Ct_1_6), + .bias_6(reg_bo_6), + .gate_output_6(o_output_gate_6), + .stage1_result_7(reg_WoxrXtYt_1_7), + .weight_7(reg_Woc_7), + .Ct_1_7(reg_Ct_1_7), + .bias_7(reg_bo_7), + .gate_output_7(o_output_gate_7), + .stage1_result_8(reg_WoxrXtYt_1_8), + .weight_8(reg_Woc_8), + .Ct_1_8(reg_Ct_1_8), + .bias_8(reg_bo_8), + .gate_output_8(o_output_gate_8), + .stage1_result_9(reg_WoxrXtYt_1_9), + .weight_9(reg_Woc_9), + .Ct_1_9(reg_Ct_1_9), + .bias_9(reg_bo_9), + .gate_output_9(o_output_gate_9), + .stage1_result_10(reg_WoxrXtYt_1_10), + .weight_10(reg_Woc_10), + .Ct_1_10(reg_Ct_1_10), + .bias_10(reg_bo_10), + .gate_output_10(o_output_gate_10), + .stage1_result_11(reg_WoxrXtYt_1_11), + .weight_11(reg_Woc_11), + .Ct_1_11(reg_Ct_1_11), + .bias_11(reg_bo_11), + .gate_output_11(o_output_gate_11), + .stage1_result_12(reg_WoxrXtYt_1_12), + .weight_12(reg_Woc_12), + .Ct_1_12(reg_Ct_1_12), + .bias_12(reg_bo_12), + .gate_output_12(o_output_gate_12), + .stage1_result_13(reg_WoxrXtYt_1_13), + .weight_13(reg_Woc_13), + .Ct_1_13(reg_Ct_1_13), + .bias_13(reg_bo_13), + .gate_output_13(o_output_gate_13), + .stage1_result_14(reg_WoxrXtYt_1_14), + .weight_14(reg_Woc_14), + .Ct_1_14(reg_Ct_1_14), + .bias_14(reg_bo_14), + .gate_output_14(o_output_gate_14), + .stage1_result_15(reg_WoxrXtYt_1_15), + .weight_15(reg_Woc_15), + .Ct_1_15(reg_Ct_1_15), + .bias_15(reg_bo_15), + .gate_output_15(o_output_gate_15), + .stage1_result_16(reg_WoxrXtYt_1_16), + .weight_16(reg_Woc_16), + .Ct_1_16(reg_Ct_1_16), + .bias_16(reg_bo_16), + .gate_output_16(o_output_gate_16), + .stage1_result_17(reg_WoxrXtYt_1_17), + .weight_17(reg_Woc_17), + .Ct_1_17(reg_Ct_1_17), + .bias_17(reg_bo_17), + .gate_output_17(o_output_gate_17), + .stage1_result_18(reg_WoxrXtYt_1_18), + .weight_18(reg_Woc_18), + .Ct_1_18(reg_Ct_1_18), + .bias_18(reg_bo_18), + .gate_output_18(o_output_gate_18), + .stage1_result_19(reg_WoxrXtYt_1_19), + .weight_19(reg_Woc_19), + .Ct_1_19(reg_Ct_1_19), + .bias_19(reg_bo_19), + .gate_output_19(o_output_gate_19), + .stage1_result_20(reg_WoxrXtYt_1_20), + .weight_20(reg_Woc_20), + .Ct_1_20(reg_Ct_1_20), + .bias_20(reg_bo_20), + .gate_output_20(o_output_gate_20), + .stage1_result_21(reg_WoxrXtYt_1_21), + .weight_21(reg_Woc_21), + .Ct_1_21(reg_Ct_1_21), + .bias_21(reg_bo_21), + .gate_output_21(o_output_gate_21), + .stage1_result_22(reg_WoxrXtYt_1_22), + .weight_22(reg_Woc_22), + .Ct_1_22(reg_Ct_1_22), + .bias_22(reg_bo_22), + .gate_output_22(o_output_gate_22), + .stage1_result_23(reg_WoxrXtYt_1_23), + .weight_23(reg_Woc_23), + .Ct_1_23(reg_Ct_1_23), + .bias_23(reg_bo_23), + .gate_output_23(o_output_gate_23), + .stage1_result_24(reg_WoxrXtYt_1_24), + .weight_24(reg_Woc_24), + .Ct_1_24(reg_Ct_1_24), + .bias_24(reg_bo_24), + .gate_output_24(o_output_gate_24), + .stage1_result_25(reg_WoxrXtYt_1_25), + .weight_25(reg_Woc_25), + .Ct_1_25(reg_Ct_1_25), + .bias_25(reg_bo_25), + .gate_output_25(o_output_gate_25), + .stage1_result_26(reg_WoxrXtYt_1_26), + .weight_26(reg_Woc_26), + .Ct_1_26(reg_Ct_1_26), + .bias_26(reg_bo_26), + .gate_output_26(o_output_gate_26), + .stage1_result_27(reg_WoxrXtYt_1_27), + .weight_27(reg_Woc_27), + .Ct_1_27(reg_Ct_1_27), + .bias_27(reg_bo_27), + .gate_output_27(o_output_gate_27), + .stage1_result_28(reg_WoxrXtYt_1_28), + .weight_28(reg_Woc_28), + .Ct_1_28(reg_Ct_1_28), + .bias_28(reg_bo_28), + .gate_output_28(o_output_gate_28), + .stage1_result_29(reg_WoxrXtYt_1_29), + .weight_29(reg_Woc_29), + .Ct_1_29(reg_Ct_1_29), + .bias_29(reg_bo_29), + .gate_output_29(o_output_gate_29), + .stage1_result_30(reg_WoxrXtYt_1_30), + .weight_30(reg_Woc_30), + .Ct_1_30(reg_Ct_1_30), + .bias_30(reg_bo_30), + .gate_output_30(o_output_gate_30), + .stage1_result_31(reg_WoxrXtYt_1_31), + .weight_31(reg_Woc_31), + .Ct_1_31(reg_Ct_1_31), + .bias_31(reg_bo_31), + .gate_output_31(o_output_gate_31), + .o_valid(output_gate_valid), + .o_ready() +); + +output_activation_18_10_32_1 output_activation_18_10_32_1_inst_zcolfnwaom ( + .clk(clk), + .reset(reset), + .i_ready(enable), + .i_valid(reg_i_valid), + .stage1_result_0(reg_WcxrXtYt_1_0), + .bias_0(reg_bc_0), + .output_value_0(o_gt_0), + .stage1_result_1(reg_WcxrXtYt_1_1), + .bias_1(reg_bc_1), + .output_value_1(o_gt_1), + .stage1_result_2(reg_WcxrXtYt_1_2), + .bias_2(reg_bc_2), + .output_value_2(o_gt_2), + .stage1_result_3(reg_WcxrXtYt_1_3), + .bias_3(reg_bc_3), + .output_value_3(o_gt_3), + .stage1_result_4(reg_WcxrXtYt_1_4), + .bias_4(reg_bc_4), + .output_value_4(o_gt_4), + .stage1_result_5(reg_WcxrXtYt_1_5), + .bias_5(reg_bc_5), + .output_value_5(o_gt_5), + .stage1_result_6(reg_WcxrXtYt_1_6), + .bias_6(reg_bc_6), + .output_value_6(o_gt_6), + .stage1_result_7(reg_WcxrXtYt_1_7), + .bias_7(reg_bc_7), + .output_value_7(o_gt_7), + .stage1_result_8(reg_WcxrXtYt_1_8), + .bias_8(reg_bc_8), + .output_value_8(o_gt_8), + .stage1_result_9(reg_WcxrXtYt_1_9), + .bias_9(reg_bc_9), + .output_value_9(o_gt_9), + .stage1_result_10(reg_WcxrXtYt_1_10), + .bias_10(reg_bc_10), + .output_value_10(o_gt_10), + .stage1_result_11(reg_WcxrXtYt_1_11), + .bias_11(reg_bc_11), + .output_value_11(o_gt_11), + .stage1_result_12(reg_WcxrXtYt_1_12), + .bias_12(reg_bc_12), + .output_value_12(o_gt_12), + .stage1_result_13(reg_WcxrXtYt_1_13), + .bias_13(reg_bc_13), + .output_value_13(o_gt_13), + .stage1_result_14(reg_WcxrXtYt_1_14), + .bias_14(reg_bc_14), + .output_value_14(o_gt_14), + .stage1_result_15(reg_WcxrXtYt_1_15), + .bias_15(reg_bc_15), + .output_value_15(o_gt_15), + .stage1_result_16(reg_WcxrXtYt_1_16), + .bias_16(reg_bc_16), + .output_value_16(o_gt_16), + .stage1_result_17(reg_WcxrXtYt_1_17), + .bias_17(reg_bc_17), + .output_value_17(o_gt_17), + .stage1_result_18(reg_WcxrXtYt_1_18), + .bias_18(reg_bc_18), + .output_value_18(o_gt_18), + .stage1_result_19(reg_WcxrXtYt_1_19), + .bias_19(reg_bc_19), + .output_value_19(o_gt_19), + .stage1_result_20(reg_WcxrXtYt_1_20), + .bias_20(reg_bc_20), + .output_value_20(o_gt_20), + .stage1_result_21(reg_WcxrXtYt_1_21), + .bias_21(reg_bc_21), + .output_value_21(o_gt_21), + .stage1_result_22(reg_WcxrXtYt_1_22), + .bias_22(reg_bc_22), + .output_value_22(o_gt_22), + .stage1_result_23(reg_WcxrXtYt_1_23), + .bias_23(reg_bc_23), + .output_value_23(o_gt_23), + .stage1_result_24(reg_WcxrXtYt_1_24), + .bias_24(reg_bc_24), + .output_value_24(o_gt_24), + .stage1_result_25(reg_WcxrXtYt_1_25), + .bias_25(reg_bc_25), + .output_value_25(o_gt_25), + .stage1_result_26(reg_WcxrXtYt_1_26), + .bias_26(reg_bc_26), + .output_value_26(o_gt_26), + .stage1_result_27(reg_WcxrXtYt_1_27), + .bias_27(reg_bc_27), + .output_value_27(o_gt_27), + .stage1_result_28(reg_WcxrXtYt_1_28), + .bias_28(reg_bc_28), + .output_value_28(o_gt_28), + .stage1_result_29(reg_WcxrXtYt_1_29), + .bias_29(reg_bc_29), + .output_value_29(o_gt_29), + .stage1_result_30(reg_WcxrXtYt_1_30), + .bias_30(reg_bc_30), + .output_value_30(o_gt_30), + .stage1_result_31(reg_WcxrXtYt_1_31), + .bias_31(reg_bc_31), + .output_value_31(o_gt_31), + .o_valid(gt_valid), + .o_ready() +); + +shift_register_group_18_32_6 shift_register_group_18_32_6_eltwisemult ( + .clk(clk), + .enable(enable), + .in_0(o_gt_0), + .out_0(gt_hold_0), + .in_1(o_gt_1), + .out_1(gt_hold_1), + .in_2(o_gt_2), + .out_2(gt_hold_2), + .in_3(o_gt_3), + .out_3(gt_hold_3), + .in_4(o_gt_4), + .out_4(gt_hold_4), + .in_5(o_gt_5), + .out_5(gt_hold_5), + .in_6(o_gt_6), + .out_6(gt_hold_6), + .in_7(o_gt_7), + .out_7(gt_hold_7), + .in_8(o_gt_8), + .out_8(gt_hold_8), + .in_9(o_gt_9), + .out_9(gt_hold_9), + .in_10(o_gt_10), + .out_10(gt_hold_10), + .in_11(o_gt_11), + .out_11(gt_hold_11), + .in_12(o_gt_12), + .out_12(gt_hold_12), + .in_13(o_gt_13), + .out_13(gt_hold_13), + .in_14(o_gt_14), + .out_14(gt_hold_14), + .in_15(o_gt_15), + .out_15(gt_hold_15), + .in_16(o_gt_16), + .out_16(gt_hold_16), + .in_17(o_gt_17), + .out_17(gt_hold_17), + .in_18(o_gt_18), + .out_18(gt_hold_18), + .in_19(o_gt_19), + .out_19(gt_hold_19), + .in_20(o_gt_20), + .out_20(gt_hold_20), + .in_21(o_gt_21), + .out_21(gt_hold_21), + .in_22(o_gt_22), + .out_22(gt_hold_22), + .in_23(o_gt_23), + .out_23(gt_hold_23), + .in_24(o_gt_24), + .out_24(gt_hold_24), + .in_25(o_gt_25), + .out_25(gt_hold_25), + .in_26(o_gt_26), + .out_26(gt_hold_26), + .in_27(o_gt_27), + .out_27(gt_hold_27), + .in_28(o_gt_28), + .out_28(gt_hold_28), + .in_29(o_gt_29), + .out_29(gt_hold_29), + .in_30(o_gt_30), + .out_30(gt_hold_30), + .in_31(o_gt_31), + .out_31(gt_hold_31), + .reset(reset) +); + +elementwise_mult_core_18_18_10_32_1 elementwise_mult_core_18_18_10_32_1_it_gt_mult ( + .clk(clk), + .reset(reset), + .i_valid(forget_gate_valid), + .i_ready(enable), + .i_A_0(o_input_gate_0), + .i_B_0(gt_hold_0), + .o_C_0(o_it_gt_mult_0), + .i_A_1(o_input_gate_1), + .i_B_1(gt_hold_1), + .o_C_1(o_it_gt_mult_1), + .i_A_2(o_input_gate_2), + .i_B_2(gt_hold_2), + .o_C_2(o_it_gt_mult_2), + .i_A_3(o_input_gate_3), + .i_B_3(gt_hold_3), + .o_C_3(o_it_gt_mult_3), + .i_A_4(o_input_gate_4), + .i_B_4(gt_hold_4), + .o_C_4(o_it_gt_mult_4), + .i_A_5(o_input_gate_5), + .i_B_5(gt_hold_5), + .o_C_5(o_it_gt_mult_5), + .i_A_6(o_input_gate_6), + .i_B_6(gt_hold_6), + .o_C_6(o_it_gt_mult_6), + .i_A_7(o_input_gate_7), + .i_B_7(gt_hold_7), + .o_C_7(o_it_gt_mult_7), + .i_A_8(o_input_gate_8), + .i_B_8(gt_hold_8), + .o_C_8(o_it_gt_mult_8), + .i_A_9(o_input_gate_9), + .i_B_9(gt_hold_9), + .o_C_9(o_it_gt_mult_9), + .i_A_10(o_input_gate_10), + .i_B_10(gt_hold_10), + .o_C_10(o_it_gt_mult_10), + .i_A_11(o_input_gate_11), + .i_B_11(gt_hold_11), + .o_C_11(o_it_gt_mult_11), + .i_A_12(o_input_gate_12), + .i_B_12(gt_hold_12), + .o_C_12(o_it_gt_mult_12), + .i_A_13(o_input_gate_13), + .i_B_13(gt_hold_13), + .o_C_13(o_it_gt_mult_13), + .i_A_14(o_input_gate_14), + .i_B_14(gt_hold_14), + .o_C_14(o_it_gt_mult_14), + .i_A_15(o_input_gate_15), + .i_B_15(gt_hold_15), + .o_C_15(o_it_gt_mult_15), + .i_A_16(o_input_gate_16), + .i_B_16(gt_hold_16), + .o_C_16(o_it_gt_mult_16), + .i_A_17(o_input_gate_17), + .i_B_17(gt_hold_17), + .o_C_17(o_it_gt_mult_17), + .i_A_18(o_input_gate_18), + .i_B_18(gt_hold_18), + .o_C_18(o_it_gt_mult_18), + .i_A_19(o_input_gate_19), + .i_B_19(gt_hold_19), + .o_C_19(o_it_gt_mult_19), + .i_A_20(o_input_gate_20), + .i_B_20(gt_hold_20), + .o_C_20(o_it_gt_mult_20), + .i_A_21(o_input_gate_21), + .i_B_21(gt_hold_21), + .o_C_21(o_it_gt_mult_21), + .i_A_22(o_input_gate_22), + .i_B_22(gt_hold_22), + .o_C_22(o_it_gt_mult_22), + .i_A_23(o_input_gate_23), + .i_B_23(gt_hold_23), + .o_C_23(o_it_gt_mult_23), + .i_A_24(o_input_gate_24), + .i_B_24(gt_hold_24), + .o_C_24(o_it_gt_mult_24), + .i_A_25(o_input_gate_25), + .i_B_25(gt_hold_25), + .o_C_25(o_it_gt_mult_25), + .i_A_26(o_input_gate_26), + .i_B_26(gt_hold_26), + .o_C_26(o_it_gt_mult_26), + .i_A_27(o_input_gate_27), + .i_B_27(gt_hold_27), + .o_C_27(o_it_gt_mult_27), + .i_A_28(o_input_gate_28), + .i_B_28(gt_hold_28), + .o_C_28(o_it_gt_mult_28), + .i_A_29(o_input_gate_29), + .i_B_29(gt_hold_29), + .o_C_29(o_it_gt_mult_29), + .i_A_30(o_input_gate_30), + .i_B_30(gt_hold_30), + .o_C_30(o_it_gt_mult_30), + .i_A_31(o_input_gate_31), + .i_B_31(gt_hold_31), + .o_C_31(o_it_gt_mult_31), + .o_valid(it_gt_mult_valid), + .o_ready() +); + +shift_register_group_18_32_18 shift_register_group_18_32_18_lstm_gate ( + .clk(clk), + .enable(enable), + .in_0(o_Ct_1_0), + .out_0(Ct_1_hold_0), + .in_1(o_Ct_1_1), + .out_1(Ct_1_hold_1), + .in_2(o_Ct_1_2), + .out_2(Ct_1_hold_2), + .in_3(o_Ct_1_3), + .out_3(Ct_1_hold_3), + .in_4(o_Ct_1_4), + .out_4(Ct_1_hold_4), + .in_5(o_Ct_1_5), + .out_5(Ct_1_hold_5), + .in_6(o_Ct_1_6), + .out_6(Ct_1_hold_6), + .in_7(o_Ct_1_7), + .out_7(Ct_1_hold_7), + .in_8(o_Ct_1_8), + .out_8(Ct_1_hold_8), + .in_9(o_Ct_1_9), + .out_9(Ct_1_hold_9), + .in_10(o_Ct_1_10), + .out_10(Ct_1_hold_10), + .in_11(o_Ct_1_11), + .out_11(Ct_1_hold_11), + .in_12(o_Ct_1_12), + .out_12(Ct_1_hold_12), + .in_13(o_Ct_1_13), + .out_13(Ct_1_hold_13), + .in_14(o_Ct_1_14), + .out_14(Ct_1_hold_14), + .in_15(o_Ct_1_15), + .out_15(Ct_1_hold_15), + .in_16(o_Ct_1_16), + .out_16(Ct_1_hold_16), + .in_17(o_Ct_1_17), + .out_17(Ct_1_hold_17), + .in_18(o_Ct_1_18), + .out_18(Ct_1_hold_18), + .in_19(o_Ct_1_19), + .out_19(Ct_1_hold_19), + .in_20(o_Ct_1_20), + .out_20(Ct_1_hold_20), + .in_21(o_Ct_1_21), + .out_21(Ct_1_hold_21), + .in_22(o_Ct_1_22), + .out_22(Ct_1_hold_22), + .in_23(o_Ct_1_23), + .out_23(Ct_1_hold_23), + .in_24(o_Ct_1_24), + .out_24(Ct_1_hold_24), + .in_25(o_Ct_1_25), + .out_25(Ct_1_hold_25), + .in_26(o_Ct_1_26), + .out_26(Ct_1_hold_26), + .in_27(o_Ct_1_27), + .out_27(Ct_1_hold_27), + .in_28(o_Ct_1_28), + .out_28(Ct_1_hold_28), + .in_29(o_Ct_1_29), + .out_29(Ct_1_hold_29), + .in_30(o_Ct_1_30), + .out_30(Ct_1_hold_30), + .in_31(o_Ct_1_31), + .out_31(Ct_1_hold_31), + .reset(reset) +); + +elementwise_mult_core_18_18_10_32_1 elementwise_mult_core_18_18_10_32_1_ft_Ct_1_mult ( + .clk(clk), + .reset(reset), + .i_valid(forget_gate_valid), + .i_ready(enable), + .i_A_0(Ct_1_hold_0), + .i_B_0(o_forget_gate_0), + .o_C_0(o_ft_Ct_1_mult_0), + .i_A_1(Ct_1_hold_1), + .i_B_1(o_forget_gate_1), + .o_C_1(o_ft_Ct_1_mult_1), + .i_A_2(Ct_1_hold_2), + .i_B_2(o_forget_gate_2), + .o_C_2(o_ft_Ct_1_mult_2), + .i_A_3(Ct_1_hold_3), + .i_B_3(o_forget_gate_3), + .o_C_3(o_ft_Ct_1_mult_3), + .i_A_4(Ct_1_hold_4), + .i_B_4(o_forget_gate_4), + .o_C_4(o_ft_Ct_1_mult_4), + .i_A_5(Ct_1_hold_5), + .i_B_5(o_forget_gate_5), + .o_C_5(o_ft_Ct_1_mult_5), + .i_A_6(Ct_1_hold_6), + .i_B_6(o_forget_gate_6), + .o_C_6(o_ft_Ct_1_mult_6), + .i_A_7(Ct_1_hold_7), + .i_B_7(o_forget_gate_7), + .o_C_7(o_ft_Ct_1_mult_7), + .i_A_8(Ct_1_hold_8), + .i_B_8(o_forget_gate_8), + .o_C_8(o_ft_Ct_1_mult_8), + .i_A_9(Ct_1_hold_9), + .i_B_9(o_forget_gate_9), + .o_C_9(o_ft_Ct_1_mult_9), + .i_A_10(Ct_1_hold_10), + .i_B_10(o_forget_gate_10), + .o_C_10(o_ft_Ct_1_mult_10), + .i_A_11(Ct_1_hold_11), + .i_B_11(o_forget_gate_11), + .o_C_11(o_ft_Ct_1_mult_11), + .i_A_12(Ct_1_hold_12), + .i_B_12(o_forget_gate_12), + .o_C_12(o_ft_Ct_1_mult_12), + .i_A_13(Ct_1_hold_13), + .i_B_13(o_forget_gate_13), + .o_C_13(o_ft_Ct_1_mult_13), + .i_A_14(Ct_1_hold_14), + .i_B_14(o_forget_gate_14), + .o_C_14(o_ft_Ct_1_mult_14), + .i_A_15(Ct_1_hold_15), + .i_B_15(o_forget_gate_15), + .o_C_15(o_ft_Ct_1_mult_15), + .i_A_16(Ct_1_hold_16), + .i_B_16(o_forget_gate_16), + .o_C_16(o_ft_Ct_1_mult_16), + .i_A_17(Ct_1_hold_17), + .i_B_17(o_forget_gate_17), + .o_C_17(o_ft_Ct_1_mult_17), + .i_A_18(Ct_1_hold_18), + .i_B_18(o_forget_gate_18), + .o_C_18(o_ft_Ct_1_mult_18), + .i_A_19(Ct_1_hold_19), + .i_B_19(o_forget_gate_19), + .o_C_19(o_ft_Ct_1_mult_19), + .i_A_20(Ct_1_hold_20), + .i_B_20(o_forget_gate_20), + .o_C_20(o_ft_Ct_1_mult_20), + .i_A_21(Ct_1_hold_21), + .i_B_21(o_forget_gate_21), + .o_C_21(o_ft_Ct_1_mult_21), + .i_A_22(Ct_1_hold_22), + .i_B_22(o_forget_gate_22), + .o_C_22(o_ft_Ct_1_mult_22), + .i_A_23(Ct_1_hold_23), + .i_B_23(o_forget_gate_23), + .o_C_23(o_ft_Ct_1_mult_23), + .i_A_24(Ct_1_hold_24), + .i_B_24(o_forget_gate_24), + .o_C_24(o_ft_Ct_1_mult_24), + .i_A_25(Ct_1_hold_25), + .i_B_25(o_forget_gate_25), + .o_C_25(o_ft_Ct_1_mult_25), + .i_A_26(Ct_1_hold_26), + .i_B_26(o_forget_gate_26), + .o_C_26(o_ft_Ct_1_mult_26), + .i_A_27(Ct_1_hold_27), + .i_B_27(o_forget_gate_27), + .o_C_27(o_ft_Ct_1_mult_27), + .i_A_28(Ct_1_hold_28), + .i_B_28(o_forget_gate_28), + .o_C_28(o_ft_Ct_1_mult_28), + .i_A_29(Ct_1_hold_29), + .i_B_29(o_forget_gate_29), + .o_C_29(o_ft_Ct_1_mult_29), + .i_A_30(Ct_1_hold_30), + .i_B_30(o_forget_gate_30), + .o_C_30(o_ft_Ct_1_mult_30), + .i_A_31(Ct_1_hold_31), + .i_B_31(o_forget_gate_31), + .o_C_31(o_ft_Ct_1_mult_31), + .o_valid(ft_Ct_1_mult_valid), + .o_ready() +); + +wire eltwise_add_core_valid; +assign eltwise_add_core_valid = ft_Ct_1_mult_valid & it_gt_mult_valid; + +elementwise_add_core_18_18_32 elementwise_add_core_18_18_32_inst_jyeotjcadr ( + .clk(clk), + .reset(reset), + .i_valid(eltwise_add_core_valid), + .i_ready(enable), + .i_A_0(o_it_gt_mult_0), + .i_B_0(o_ft_Ct_1_mult_0), + .o_C_0(o_ct_0), + .i_A_1(o_it_gt_mult_1), + .i_B_1(o_ft_Ct_1_mult_1), + .o_C_1(o_ct_1), + .i_A_2(o_it_gt_mult_2), + .i_B_2(o_ft_Ct_1_mult_2), + .o_C_2(o_ct_2), + .i_A_3(o_it_gt_mult_3), + .i_B_3(o_ft_Ct_1_mult_3), + .o_C_3(o_ct_3), + .i_A_4(o_it_gt_mult_4), + .i_B_4(o_ft_Ct_1_mult_4), + .o_C_4(o_ct_4), + .i_A_5(o_it_gt_mult_5), + .i_B_5(o_ft_Ct_1_mult_5), + .o_C_5(o_ct_5), + .i_A_6(o_it_gt_mult_6), + .i_B_6(o_ft_Ct_1_mult_6), + .o_C_6(o_ct_6), + .i_A_7(o_it_gt_mult_7), + .i_B_7(o_ft_Ct_1_mult_7), + .o_C_7(o_ct_7), + .i_A_8(o_it_gt_mult_8), + .i_B_8(o_ft_Ct_1_mult_8), + .o_C_8(o_ct_8), + .i_A_9(o_it_gt_mult_9), + .i_B_9(o_ft_Ct_1_mult_9), + .o_C_9(o_ct_9), + .i_A_10(o_it_gt_mult_10), + .i_B_10(o_ft_Ct_1_mult_10), + .o_C_10(o_ct_10), + .i_A_11(o_it_gt_mult_11), + .i_B_11(o_ft_Ct_1_mult_11), + .o_C_11(o_ct_11), + .i_A_12(o_it_gt_mult_12), + .i_B_12(o_ft_Ct_1_mult_12), + .o_C_12(o_ct_12), + .i_A_13(o_it_gt_mult_13), + .i_B_13(o_ft_Ct_1_mult_13), + .o_C_13(o_ct_13), + .i_A_14(o_it_gt_mult_14), + .i_B_14(o_ft_Ct_1_mult_14), + .o_C_14(o_ct_14), + .i_A_15(o_it_gt_mult_15), + .i_B_15(o_ft_Ct_1_mult_15), + .o_C_15(o_ct_15), + .i_A_16(o_it_gt_mult_16), + .i_B_16(o_ft_Ct_1_mult_16), + .o_C_16(o_ct_16), + .i_A_17(o_it_gt_mult_17), + .i_B_17(o_ft_Ct_1_mult_17), + .o_C_17(o_ct_17), + .i_A_18(o_it_gt_mult_18), + .i_B_18(o_ft_Ct_1_mult_18), + .o_C_18(o_ct_18), + .i_A_19(o_it_gt_mult_19), + .i_B_19(o_ft_Ct_1_mult_19), + .o_C_19(o_ct_19), + .i_A_20(o_it_gt_mult_20), + .i_B_20(o_ft_Ct_1_mult_20), + .o_C_20(o_ct_20), + .i_A_21(o_it_gt_mult_21), + .i_B_21(o_ft_Ct_1_mult_21), + .o_C_21(o_ct_21), + .i_A_22(o_it_gt_mult_22), + .i_B_22(o_ft_Ct_1_mult_22), + .o_C_22(o_ct_22), + .i_A_23(o_it_gt_mult_23), + .i_B_23(o_ft_Ct_1_mult_23), + .o_C_23(o_ct_23), + .i_A_24(o_it_gt_mult_24), + .i_B_24(o_ft_Ct_1_mult_24), + .o_C_24(o_ct_24), + .i_A_25(o_it_gt_mult_25), + .i_B_25(o_ft_Ct_1_mult_25), + .o_C_25(o_ct_25), + .i_A_26(o_it_gt_mult_26), + .i_B_26(o_ft_Ct_1_mult_26), + .o_C_26(o_ct_26), + .i_A_27(o_it_gt_mult_27), + .i_B_27(o_ft_Ct_1_mult_27), + .o_C_27(o_ct_27), + .i_A_28(o_it_gt_mult_28), + .i_B_28(o_ft_Ct_1_mult_28), + .o_C_28(o_ct_28), + .i_A_29(o_it_gt_mult_29), + .i_B_29(o_ft_Ct_1_mult_29), + .o_C_29(o_ct_29), + .i_A_30(o_it_gt_mult_30), + .i_B_30(o_ft_Ct_1_mult_30), + .o_C_30(o_ct_30), + .i_A_31(o_it_gt_mult_31), + .i_B_31(o_ft_Ct_1_mult_31), + .o_C_31(o_ct_31), + .o_valid(ct_valid), + .o_ready() +); + +shift_register_group_18_32_14 shift_register_group_18_32_14_Ct ( + .clk(clk), + .enable(enable), + .in_0(o_ct_0), + .out_0(ct_hold_0), + .in_1(o_ct_1), + .out_1(ct_hold_1), + .in_2(o_ct_2), + .out_2(ct_hold_2), + .in_3(o_ct_3), + .out_3(ct_hold_3), + .in_4(o_ct_4), + .out_4(ct_hold_4), + .in_5(o_ct_5), + .out_5(ct_hold_5), + .in_6(o_ct_6), + .out_6(ct_hold_6), + .in_7(o_ct_7), + .out_7(ct_hold_7), + .in_8(o_ct_8), + .out_8(ct_hold_8), + .in_9(o_ct_9), + .out_9(ct_hold_9), + .in_10(o_ct_10), + .out_10(ct_hold_10), + .in_11(o_ct_11), + .out_11(ct_hold_11), + .in_12(o_ct_12), + .out_12(ct_hold_12), + .in_13(o_ct_13), + .out_13(ct_hold_13), + .in_14(o_ct_14), + .out_14(ct_hold_14), + .in_15(o_ct_15), + .out_15(ct_hold_15), + .in_16(o_ct_16), + .out_16(ct_hold_16), + .in_17(o_ct_17), + .out_17(ct_hold_17), + .in_18(o_ct_18), + .out_18(ct_hold_18), + .in_19(o_ct_19), + .out_19(ct_hold_19), + .in_20(o_ct_20), + .out_20(ct_hold_20), + .in_21(o_ct_21), + .out_21(ct_hold_21), + .in_22(o_ct_22), + .out_22(ct_hold_22), + .in_23(o_ct_23), + .out_23(ct_hold_23), + .in_24(o_ct_24), + .out_24(ct_hold_24), + .in_25(o_ct_25), + .out_25(ct_hold_25), + .in_26(o_ct_26), + .out_26(ct_hold_26), + .in_27(o_ct_27), + .out_27(ct_hold_27), + .in_28(o_ct_28), + .out_28(ct_hold_28), + .in_29(o_ct_29), + .out_29(ct_hold_29), + .in_30(o_ct_30), + .out_30(ct_hold_30), + .in_31(o_ct_31), + .out_31(ct_hold_31), + .reset(reset) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_0 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_0), + .i_x(o_ct_0), + .o_y(o_tanh_0) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_1 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_1), + .i_x(o_ct_1), + .o_y(o_tanh_1) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_2 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_2), + .i_x(o_ct_2), + .o_y(o_tanh_2) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_3 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_3), + .i_x(o_ct_3), + .o_y(o_tanh_3) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_4 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_4), + .i_x(o_ct_4), + .o_y(o_tanh_4) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_5 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_5), + .i_x(o_ct_5), + .o_y(o_tanh_5) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_6 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_6), + .i_x(o_ct_6), + .o_y(o_tanh_6) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_7 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_7), + .i_x(o_ct_7), + .o_y(o_tanh_7) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_8 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_8), + .i_x(o_ct_8), + .o_y(o_tanh_8) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_9 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_9), + .i_x(o_ct_9), + .o_y(o_tanh_9) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_10 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_10), + .i_x(o_ct_10), + .o_y(o_tanh_10) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_11 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_11), + .i_x(o_ct_11), + .o_y(o_tanh_11) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_12 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_12), + .i_x(o_ct_12), + .o_y(o_tanh_12) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_13 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_13), + .i_x(o_ct_13), + .o_y(o_tanh_13) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_14 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_14), + .i_x(o_ct_14), + .o_y(o_tanh_14) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_15 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_15), + .i_x(o_ct_15), + .o_y(o_tanh_15) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_16 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_16), + .i_x(o_ct_16), + .o_y(o_tanh_16) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_17 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_17), + .i_x(o_ct_17), + .o_y(o_tanh_17) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_18 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_18), + .i_x(o_ct_18), + .o_y(o_tanh_18) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_19 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_19), + .i_x(o_ct_19), + .o_y(o_tanh_19) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_20 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_20), + .i_x(o_ct_20), + .o_y(o_tanh_20) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_21 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_21), + .i_x(o_ct_21), + .o_y(o_tanh_21) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_22 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_22), + .i_x(o_ct_22), + .o_y(o_tanh_22) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_23 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_23), + .i_x(o_ct_23), + .o_y(o_tanh_23) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_24 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_24), + .i_x(o_ct_24), + .o_y(o_tanh_24) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_25 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_25), + .i_x(o_ct_25), + .o_y(o_tanh_25) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_26 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_26), + .i_x(o_ct_26), + .o_y(o_tanh_26) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_27 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_27), + .i_x(o_ct_27), + .o_y(o_tanh_27) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_28 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_28), + .i_x(o_ct_28), + .o_y(o_tanh_28) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_29 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_29), + .i_x(o_ct_29), + .o_y(o_tanh_29) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_30 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_30), + .i_x(o_ct_30), + .o_y(o_tanh_30) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_31 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_31), + .i_x(o_ct_31), + .o_y(o_tanh_31) +); + +shift_register_group_18_32_18 shift_register_group_18_32_18_Ct ( + .clk(clk), + .enable(enable), + .in_0(o_output_gate_0), + .out_0(ot_hold_0), + .in_1(o_output_gate_1), + .out_1(ot_hold_1), + .in_2(o_output_gate_2), + .out_2(ot_hold_2), + .in_3(o_output_gate_3), + .out_3(ot_hold_3), + .in_4(o_output_gate_4), + .out_4(ot_hold_4), + .in_5(o_output_gate_5), + .out_5(ot_hold_5), + .in_6(o_output_gate_6), + .out_6(ot_hold_6), + .in_7(o_output_gate_7), + .out_7(ot_hold_7), + .in_8(o_output_gate_8), + .out_8(ot_hold_8), + .in_9(o_output_gate_9), + .out_9(ot_hold_9), + .in_10(o_output_gate_10), + .out_10(ot_hold_10), + .in_11(o_output_gate_11), + .out_11(ot_hold_11), + .in_12(o_output_gate_12), + .out_12(ot_hold_12), + .in_13(o_output_gate_13), + .out_13(ot_hold_13), + .in_14(o_output_gate_14), + .out_14(ot_hold_14), + .in_15(o_output_gate_15), + .out_15(ot_hold_15), + .in_16(o_output_gate_16), + .out_16(ot_hold_16), + .in_17(o_output_gate_17), + .out_17(ot_hold_17), + .in_18(o_output_gate_18), + .out_18(ot_hold_18), + .in_19(o_output_gate_19), + .out_19(ot_hold_19), + .in_20(o_output_gate_20), + .out_20(ot_hold_20), + .in_21(o_output_gate_21), + .out_21(ot_hold_21), + .in_22(o_output_gate_22), + .out_22(ot_hold_22), + .in_23(o_output_gate_23), + .out_23(ot_hold_23), + .in_24(o_output_gate_24), + .out_24(ot_hold_24), + .in_25(o_output_gate_25), + .out_25(ot_hold_25), + .in_26(o_output_gate_26), + .out_26(ot_hold_26), + .in_27(o_output_gate_27), + .out_27(ot_hold_27), + .in_28(o_output_gate_28), + .out_28(ot_hold_28), + .in_29(o_output_gate_29), + .out_29(ot_hold_29), + .in_30(o_output_gate_30), + .out_30(ot_hold_30), + .in_31(o_output_gate_31), + .out_31(ot_hold_31), + .reset(reset) +); + +elementwise_mult_core_18_18_10_32_1 elementwise_mult_core_18_18_10_32_1_ot_tanh_mult ( + .clk(clk), + .reset(reset), + .i_valid(tanh_valid_0), + .i_ready(enable), + .i_A_0(o_tanh_0), + .i_B_0(ot_hold_0), + .o_C_0(o_mt_0), + .i_A_1(o_tanh_1), + .i_B_1(ot_hold_1), + .o_C_1(o_mt_1), + .i_A_2(o_tanh_2), + .i_B_2(ot_hold_2), + .o_C_2(o_mt_2), + .i_A_3(o_tanh_3), + .i_B_3(ot_hold_3), + .o_C_3(o_mt_3), + .i_A_4(o_tanh_4), + .i_B_4(ot_hold_4), + .o_C_4(o_mt_4), + .i_A_5(o_tanh_5), + .i_B_5(ot_hold_5), + .o_C_5(o_mt_5), + .i_A_6(o_tanh_6), + .i_B_6(ot_hold_6), + .o_C_6(o_mt_6), + .i_A_7(o_tanh_7), + .i_B_7(ot_hold_7), + .o_C_7(o_mt_7), + .i_A_8(o_tanh_8), + .i_B_8(ot_hold_8), + .o_C_8(o_mt_8), + .i_A_9(o_tanh_9), + .i_B_9(ot_hold_9), + .o_C_9(o_mt_9), + .i_A_10(o_tanh_10), + .i_B_10(ot_hold_10), + .o_C_10(o_mt_10), + .i_A_11(o_tanh_11), + .i_B_11(ot_hold_11), + .o_C_11(o_mt_11), + .i_A_12(o_tanh_12), + .i_B_12(ot_hold_12), + .o_C_12(o_mt_12), + .i_A_13(o_tanh_13), + .i_B_13(ot_hold_13), + .o_C_13(o_mt_13), + .i_A_14(o_tanh_14), + .i_B_14(ot_hold_14), + .o_C_14(o_mt_14), + .i_A_15(o_tanh_15), + .i_B_15(ot_hold_15), + .o_C_15(o_mt_15), + .i_A_16(o_tanh_16), + .i_B_16(ot_hold_16), + .o_C_16(o_mt_16), + .i_A_17(o_tanh_17), + .i_B_17(ot_hold_17), + .o_C_17(o_mt_17), + .i_A_18(o_tanh_18), + .i_B_18(ot_hold_18), + .o_C_18(o_mt_18), + .i_A_19(o_tanh_19), + .i_B_19(ot_hold_19), + .o_C_19(o_mt_19), + .i_A_20(o_tanh_20), + .i_B_20(ot_hold_20), + .o_C_20(o_mt_20), + .i_A_21(o_tanh_21), + .i_B_21(ot_hold_21), + .o_C_21(o_mt_21), + .i_A_22(o_tanh_22), + .i_B_22(ot_hold_22), + .o_C_22(o_mt_22), + .i_A_23(o_tanh_23), + .i_B_23(ot_hold_23), + .o_C_23(o_mt_23), + .i_A_24(o_tanh_24), + .i_B_24(ot_hold_24), + .o_C_24(o_mt_24), + .i_A_25(o_tanh_25), + .i_B_25(ot_hold_25), + .o_C_25(o_mt_25), + .i_A_26(o_tanh_26), + .i_B_26(ot_hold_26), + .o_C_26(o_mt_26), + .i_A_27(o_tanh_27), + .i_B_27(ot_hold_27), + .o_C_27(o_mt_27), + .i_A_28(o_tanh_28), + .i_B_28(ot_hold_28), + .o_C_28(o_mt_28), + .i_A_29(o_tanh_29), + .i_B_29(ot_hold_29), + .o_C_29(o_mt_29), + .i_A_30(o_tanh_30), + .i_B_30(ot_hold_30), + .o_C_30(o_mt_30), + .i_A_31(o_tanh_31), + .i_B_31(ot_hold_31), + .o_C_31(o_mt_31), + .o_valid(mt_valid), + .o_ready() +); + +always @ (posedge clk) begin + if(reset) begin + reg_i_valid <= 1'b0; + reg_o_valid <= 1'b0; + reg_Ct_1_0 <= 0; + reg_WixrXtYt_1_0 <= 0; + reg_Wic_0 <= 0; + reg_bi_0 <= 0; + reg_WfxrXtYt_1_0 <= 0; + reg_Wfc_0 <= 0; + reg_bf_0 <= 0; + reg_WoxrXtYt_1_0 <= 0; + reg_Woc_0 <= 0; + reg_bo_0 <= 0; + reg_WcxrXtYt_1_0 <= 0; + reg_bc_0 <= 0; + reg_out_mt_0 <= 0; + reg_out_ct_0 <= 0; + reg_Ct_1_1 <= 0; + reg_WixrXtYt_1_1 <= 0; + reg_Wic_1 <= 0; + reg_bi_1 <= 0; + reg_WfxrXtYt_1_1 <= 0; + reg_Wfc_1 <= 0; + reg_bf_1 <= 0; + reg_WoxrXtYt_1_1 <= 0; + reg_Woc_1 <= 0; + reg_bo_1 <= 0; + reg_WcxrXtYt_1_1 <= 0; + reg_bc_1 <= 0; + reg_out_mt_1 <= 0; + reg_out_ct_1 <= 0; + reg_Ct_1_2 <= 0; + reg_WixrXtYt_1_2 <= 0; + reg_Wic_2 <= 0; + reg_bi_2 <= 0; + reg_WfxrXtYt_1_2 <= 0; + reg_Wfc_2 <= 0; + reg_bf_2 <= 0; + reg_WoxrXtYt_1_2 <= 0; + reg_Woc_2 <= 0; + reg_bo_2 <= 0; + reg_WcxrXtYt_1_2 <= 0; + reg_bc_2 <= 0; + reg_out_mt_2 <= 0; + reg_out_ct_2 <= 0; + reg_Ct_1_3 <= 0; + reg_WixrXtYt_1_3 <= 0; + reg_Wic_3 <= 0; + reg_bi_3 <= 0; + reg_WfxrXtYt_1_3 <= 0; + reg_Wfc_3 <= 0; + reg_bf_3 <= 0; + reg_WoxrXtYt_1_3 <= 0; + reg_Woc_3 <= 0; + reg_bo_3 <= 0; + reg_WcxrXtYt_1_3 <= 0; + reg_bc_3 <= 0; + reg_out_mt_3 <= 0; + reg_out_ct_3 <= 0; + reg_Ct_1_4 <= 0; + reg_WixrXtYt_1_4 <= 0; + reg_Wic_4 <= 0; + reg_bi_4 <= 0; + reg_WfxrXtYt_1_4 <= 0; + reg_Wfc_4 <= 0; + reg_bf_4 <= 0; + reg_WoxrXtYt_1_4 <= 0; + reg_Woc_4 <= 0; + reg_bo_4 <= 0; + reg_WcxrXtYt_1_4 <= 0; + reg_bc_4 <= 0; + reg_out_mt_4 <= 0; + reg_out_ct_4 <= 0; + reg_Ct_1_5 <= 0; + reg_WixrXtYt_1_5 <= 0; + reg_Wic_5 <= 0; + reg_bi_5 <= 0; + reg_WfxrXtYt_1_5 <= 0; + reg_Wfc_5 <= 0; + reg_bf_5 <= 0; + reg_WoxrXtYt_1_5 <= 0; + reg_Woc_5 <= 0; + reg_bo_5 <= 0; + reg_WcxrXtYt_1_5 <= 0; + reg_bc_5 <= 0; + reg_out_mt_5 <= 0; + reg_out_ct_5 <= 0; + reg_Ct_1_6 <= 0; + reg_WixrXtYt_1_6 <= 0; + reg_Wic_6 <= 0; + reg_bi_6 <= 0; + reg_WfxrXtYt_1_6 <= 0; + reg_Wfc_6 <= 0; + reg_bf_6 <= 0; + reg_WoxrXtYt_1_6 <= 0; + reg_Woc_6 <= 0; + reg_bo_6 <= 0; + reg_WcxrXtYt_1_6 <= 0; + reg_bc_6 <= 0; + reg_out_mt_6 <= 0; + reg_out_ct_6 <= 0; + reg_Ct_1_7 <= 0; + reg_WixrXtYt_1_7 <= 0; + reg_Wic_7 <= 0; + reg_bi_7 <= 0; + reg_WfxrXtYt_1_7 <= 0; + reg_Wfc_7 <= 0; + reg_bf_7 <= 0; + reg_WoxrXtYt_1_7 <= 0; + reg_Woc_7 <= 0; + reg_bo_7 <= 0; + reg_WcxrXtYt_1_7 <= 0; + reg_bc_7 <= 0; + reg_out_mt_7 <= 0; + reg_out_ct_7 <= 0; + reg_Ct_1_8 <= 0; + reg_WixrXtYt_1_8 <= 0; + reg_Wic_8 <= 0; + reg_bi_8 <= 0; + reg_WfxrXtYt_1_8 <= 0; + reg_Wfc_8 <= 0; + reg_bf_8 <= 0; + reg_WoxrXtYt_1_8 <= 0; + reg_Woc_8 <= 0; + reg_bo_8 <= 0; + reg_WcxrXtYt_1_8 <= 0; + reg_bc_8 <= 0; + reg_out_mt_8 <= 0; + reg_out_ct_8 <= 0; + reg_Ct_1_9 <= 0; + reg_WixrXtYt_1_9 <= 0; + reg_Wic_9 <= 0; + reg_bi_9 <= 0; + reg_WfxrXtYt_1_9 <= 0; + reg_Wfc_9 <= 0; + reg_bf_9 <= 0; + reg_WoxrXtYt_1_9 <= 0; + reg_Woc_9 <= 0; + reg_bo_9 <= 0; + reg_WcxrXtYt_1_9 <= 0; + reg_bc_9 <= 0; + reg_out_mt_9 <= 0; + reg_out_ct_9 <= 0; + reg_Ct_1_10 <= 0; + reg_WixrXtYt_1_10 <= 0; + reg_Wic_10 <= 0; + reg_bi_10 <= 0; + reg_WfxrXtYt_1_10 <= 0; + reg_Wfc_10 <= 0; + reg_bf_10 <= 0; + reg_WoxrXtYt_1_10 <= 0; + reg_Woc_10 <= 0; + reg_bo_10 <= 0; + reg_WcxrXtYt_1_10 <= 0; + reg_bc_10 <= 0; + reg_out_mt_10 <= 0; + reg_out_ct_10 <= 0; + reg_Ct_1_11 <= 0; + reg_WixrXtYt_1_11 <= 0; + reg_Wic_11 <= 0; + reg_bi_11 <= 0; + reg_WfxrXtYt_1_11 <= 0; + reg_Wfc_11 <= 0; + reg_bf_11 <= 0; + reg_WoxrXtYt_1_11 <= 0; + reg_Woc_11 <= 0; + reg_bo_11 <= 0; + reg_WcxrXtYt_1_11 <= 0; + reg_bc_11 <= 0; + reg_out_mt_11 <= 0; + reg_out_ct_11 <= 0; + reg_Ct_1_12 <= 0; + reg_WixrXtYt_1_12 <= 0; + reg_Wic_12 <= 0; + reg_bi_12 <= 0; + reg_WfxrXtYt_1_12 <= 0; + reg_Wfc_12 <= 0; + reg_bf_12 <= 0; + reg_WoxrXtYt_1_12 <= 0; + reg_Woc_12 <= 0; + reg_bo_12 <= 0; + reg_WcxrXtYt_1_12 <= 0; + reg_bc_12 <= 0; + reg_out_mt_12 <= 0; + reg_out_ct_12 <= 0; + reg_Ct_1_13 <= 0; + reg_WixrXtYt_1_13 <= 0; + reg_Wic_13 <= 0; + reg_bi_13 <= 0; + reg_WfxrXtYt_1_13 <= 0; + reg_Wfc_13 <= 0; + reg_bf_13 <= 0; + reg_WoxrXtYt_1_13 <= 0; + reg_Woc_13 <= 0; + reg_bo_13 <= 0; + reg_WcxrXtYt_1_13 <= 0; + reg_bc_13 <= 0; + reg_out_mt_13 <= 0; + reg_out_ct_13 <= 0; + reg_Ct_1_14 <= 0; + reg_WixrXtYt_1_14 <= 0; + reg_Wic_14 <= 0; + reg_bi_14 <= 0; + reg_WfxrXtYt_1_14 <= 0; + reg_Wfc_14 <= 0; + reg_bf_14 <= 0; + reg_WoxrXtYt_1_14 <= 0; + reg_Woc_14 <= 0; + reg_bo_14 <= 0; + reg_WcxrXtYt_1_14 <= 0; + reg_bc_14 <= 0; + reg_out_mt_14 <= 0; + reg_out_ct_14 <= 0; + reg_Ct_1_15 <= 0; + reg_WixrXtYt_1_15 <= 0; + reg_Wic_15 <= 0; + reg_bi_15 <= 0; + reg_WfxrXtYt_1_15 <= 0; + reg_Wfc_15 <= 0; + reg_bf_15 <= 0; + reg_WoxrXtYt_1_15 <= 0; + reg_Woc_15 <= 0; + reg_bo_15 <= 0; + reg_WcxrXtYt_1_15 <= 0; + reg_bc_15 <= 0; + reg_out_mt_15 <= 0; + reg_out_ct_15 <= 0; + reg_Ct_1_16 <= 0; + reg_WixrXtYt_1_16 <= 0; + reg_Wic_16 <= 0; + reg_bi_16 <= 0; + reg_WfxrXtYt_1_16 <= 0; + reg_Wfc_16 <= 0; + reg_bf_16 <= 0; + reg_WoxrXtYt_1_16 <= 0; + reg_Woc_16 <= 0; + reg_bo_16 <= 0; + reg_WcxrXtYt_1_16 <= 0; + reg_bc_16 <= 0; + reg_out_mt_16 <= 0; + reg_out_ct_16 <= 0; + reg_Ct_1_17 <= 0; + reg_WixrXtYt_1_17 <= 0; + reg_Wic_17 <= 0; + reg_bi_17 <= 0; + reg_WfxrXtYt_1_17 <= 0; + reg_Wfc_17 <= 0; + reg_bf_17 <= 0; + reg_WoxrXtYt_1_17 <= 0; + reg_Woc_17 <= 0; + reg_bo_17 <= 0; + reg_WcxrXtYt_1_17 <= 0; + reg_bc_17 <= 0; + reg_out_mt_17 <= 0; + reg_out_ct_17 <= 0; + reg_Ct_1_18 <= 0; + reg_WixrXtYt_1_18 <= 0; + reg_Wic_18 <= 0; + reg_bi_18 <= 0; + reg_WfxrXtYt_1_18 <= 0; + reg_Wfc_18 <= 0; + reg_bf_18 <= 0; + reg_WoxrXtYt_1_18 <= 0; + reg_Woc_18 <= 0; + reg_bo_18 <= 0; + reg_WcxrXtYt_1_18 <= 0; + reg_bc_18 <= 0; + reg_out_mt_18 <= 0; + reg_out_ct_18 <= 0; + reg_Ct_1_19 <= 0; + reg_WixrXtYt_1_19 <= 0; + reg_Wic_19 <= 0; + reg_bi_19 <= 0; + reg_WfxrXtYt_1_19 <= 0; + reg_Wfc_19 <= 0; + reg_bf_19 <= 0; + reg_WoxrXtYt_1_19 <= 0; + reg_Woc_19 <= 0; + reg_bo_19 <= 0; + reg_WcxrXtYt_1_19 <= 0; + reg_bc_19 <= 0; + reg_out_mt_19 <= 0; + reg_out_ct_19 <= 0; + reg_Ct_1_20 <= 0; + reg_WixrXtYt_1_20 <= 0; + reg_Wic_20 <= 0; + reg_bi_20 <= 0; + reg_WfxrXtYt_1_20 <= 0; + reg_Wfc_20 <= 0; + reg_bf_20 <= 0; + reg_WoxrXtYt_1_20 <= 0; + reg_Woc_20 <= 0; + reg_bo_20 <= 0; + reg_WcxrXtYt_1_20 <= 0; + reg_bc_20 <= 0; + reg_out_mt_20 <= 0; + reg_out_ct_20 <= 0; + reg_Ct_1_21 <= 0; + reg_WixrXtYt_1_21 <= 0; + reg_Wic_21 <= 0; + reg_bi_21 <= 0; + reg_WfxrXtYt_1_21 <= 0; + reg_Wfc_21 <= 0; + reg_bf_21 <= 0; + reg_WoxrXtYt_1_21 <= 0; + reg_Woc_21 <= 0; + reg_bo_21 <= 0; + reg_WcxrXtYt_1_21 <= 0; + reg_bc_21 <= 0; + reg_out_mt_21 <= 0; + reg_out_ct_21 <= 0; + reg_Ct_1_22 <= 0; + reg_WixrXtYt_1_22 <= 0; + reg_Wic_22 <= 0; + reg_bi_22 <= 0; + reg_WfxrXtYt_1_22 <= 0; + reg_Wfc_22 <= 0; + reg_bf_22 <= 0; + reg_WoxrXtYt_1_22 <= 0; + reg_Woc_22 <= 0; + reg_bo_22 <= 0; + reg_WcxrXtYt_1_22 <= 0; + reg_bc_22 <= 0; + reg_out_mt_22 <= 0; + reg_out_ct_22 <= 0; + reg_Ct_1_23 <= 0; + reg_WixrXtYt_1_23 <= 0; + reg_Wic_23 <= 0; + reg_bi_23 <= 0; + reg_WfxrXtYt_1_23 <= 0; + reg_Wfc_23 <= 0; + reg_bf_23 <= 0; + reg_WoxrXtYt_1_23 <= 0; + reg_Woc_23 <= 0; + reg_bo_23 <= 0; + reg_WcxrXtYt_1_23 <= 0; + reg_bc_23 <= 0; + reg_out_mt_23 <= 0; + reg_out_ct_23 <= 0; + reg_Ct_1_24 <= 0; + reg_WixrXtYt_1_24 <= 0; + reg_Wic_24 <= 0; + reg_bi_24 <= 0; + reg_WfxrXtYt_1_24 <= 0; + reg_Wfc_24 <= 0; + reg_bf_24 <= 0; + reg_WoxrXtYt_1_24 <= 0; + reg_Woc_24 <= 0; + reg_bo_24 <= 0; + reg_WcxrXtYt_1_24 <= 0; + reg_bc_24 <= 0; + reg_out_mt_24 <= 0; + reg_out_ct_24 <= 0; + reg_Ct_1_25 <= 0; + reg_WixrXtYt_1_25 <= 0; + reg_Wic_25 <= 0; + reg_bi_25 <= 0; + reg_WfxrXtYt_1_25 <= 0; + reg_Wfc_25 <= 0; + reg_bf_25 <= 0; + reg_WoxrXtYt_1_25 <= 0; + reg_Woc_25 <= 0; + reg_bo_25 <= 0; + reg_WcxrXtYt_1_25 <= 0; + reg_bc_25 <= 0; + reg_out_mt_25 <= 0; + reg_out_ct_25 <= 0; + reg_Ct_1_26 <= 0; + reg_WixrXtYt_1_26 <= 0; + reg_Wic_26 <= 0; + reg_bi_26 <= 0; + reg_WfxrXtYt_1_26 <= 0; + reg_Wfc_26 <= 0; + reg_bf_26 <= 0; + reg_WoxrXtYt_1_26 <= 0; + reg_Woc_26 <= 0; + reg_bo_26 <= 0; + reg_WcxrXtYt_1_26 <= 0; + reg_bc_26 <= 0; + reg_out_mt_26 <= 0; + reg_out_ct_26 <= 0; + reg_Ct_1_27 <= 0; + reg_WixrXtYt_1_27 <= 0; + reg_Wic_27 <= 0; + reg_bi_27 <= 0; + reg_WfxrXtYt_1_27 <= 0; + reg_Wfc_27 <= 0; + reg_bf_27 <= 0; + reg_WoxrXtYt_1_27 <= 0; + reg_Woc_27 <= 0; + reg_bo_27 <= 0; + reg_WcxrXtYt_1_27 <= 0; + reg_bc_27 <= 0; + reg_out_mt_27 <= 0; + reg_out_ct_27 <= 0; + reg_Ct_1_28 <= 0; + reg_WixrXtYt_1_28 <= 0; + reg_Wic_28 <= 0; + reg_bi_28 <= 0; + reg_WfxrXtYt_1_28 <= 0; + reg_Wfc_28 <= 0; + reg_bf_28 <= 0; + reg_WoxrXtYt_1_28 <= 0; + reg_Woc_28 <= 0; + reg_bo_28 <= 0; + reg_WcxrXtYt_1_28 <= 0; + reg_bc_28 <= 0; + reg_out_mt_28 <= 0; + reg_out_ct_28 <= 0; + reg_Ct_1_29 <= 0; + reg_WixrXtYt_1_29 <= 0; + reg_Wic_29 <= 0; + reg_bi_29 <= 0; + reg_WfxrXtYt_1_29 <= 0; + reg_Wfc_29 <= 0; + reg_bf_29 <= 0; + reg_WoxrXtYt_1_29 <= 0; + reg_Woc_29 <= 0; + reg_bo_29 <= 0; + reg_WcxrXtYt_1_29 <= 0; + reg_bc_29 <= 0; + reg_out_mt_29 <= 0; + reg_out_ct_29 <= 0; + reg_Ct_1_30 <= 0; + reg_WixrXtYt_1_30 <= 0; + reg_Wic_30 <= 0; + reg_bi_30 <= 0; + reg_WfxrXtYt_1_30 <= 0; + reg_Wfc_30 <= 0; + reg_bf_30 <= 0; + reg_WoxrXtYt_1_30 <= 0; + reg_Woc_30 <= 0; + reg_bo_30 <= 0; + reg_WcxrXtYt_1_30 <= 0; + reg_bc_30 <= 0; + reg_out_mt_30 <= 0; + reg_out_ct_30 <= 0; + reg_Ct_1_31 <= 0; + reg_WixrXtYt_1_31 <= 0; + reg_Wic_31 <= 0; + reg_bi_31 <= 0; + reg_WfxrXtYt_1_31 <= 0; + reg_Wfc_31 <= 0; + reg_bf_31 <= 0; + reg_WoxrXtYt_1_31 <= 0; + reg_Woc_31 <= 0; + reg_bo_31 <= 0; + reg_WcxrXtYt_1_31 <= 0; + reg_bc_31 <= 0; + reg_out_mt_31 <= 0; + reg_out_ct_31 <= 0; + end else if (enable) begin + reg_i_valid <= i_valid; + reg_o_valid <= mt_valid; + reg_Ct_1_0 <= Ct_1_0; + reg_WixrXtYt_1_0 <= WixrXtYt_1_0; + reg_Wic_0 <= Wic_0; + reg_bi_0 <= bi_0; + reg_WfxrXtYt_1_0 <= WfxrXtYt_1_0; + reg_Wfc_0 <= Wfc_0; + reg_bf_0 <= bf_0; + reg_WoxrXtYt_1_0 <= WoxrXtYt_1_0; + reg_Woc_0 <= Woc_0; + reg_bo_0 <= bo_0; + reg_WcxrXtYt_1_0 <= WcxrXtYt_1_0; + reg_bc_0 <= bc_0; + reg_out_mt_0 <= o_mt_0; + reg_out_ct_0 <= ct_hold_0; + reg_Ct_1_1 <= Ct_1_1; + reg_WixrXtYt_1_1 <= WixrXtYt_1_1; + reg_Wic_1 <= Wic_1; + reg_bi_1 <= bi_1; + reg_WfxrXtYt_1_1 <= WfxrXtYt_1_1; + reg_Wfc_1 <= Wfc_1; + reg_bf_1 <= bf_1; + reg_WoxrXtYt_1_1 <= WoxrXtYt_1_1; + reg_Woc_1 <= Woc_1; + reg_bo_1 <= bo_1; + reg_WcxrXtYt_1_1 <= WcxrXtYt_1_1; + reg_bc_1 <= bc_1; + reg_out_mt_1 <= o_mt_1; + reg_out_ct_1 <= ct_hold_1; + reg_Ct_1_2 <= Ct_1_2; + reg_WixrXtYt_1_2 <= WixrXtYt_1_2; + reg_Wic_2 <= Wic_2; + reg_bi_2 <= bi_2; + reg_WfxrXtYt_1_2 <= WfxrXtYt_1_2; + reg_Wfc_2 <= Wfc_2; + reg_bf_2 <= bf_2; + reg_WoxrXtYt_1_2 <= WoxrXtYt_1_2; + reg_Woc_2 <= Woc_2; + reg_bo_2 <= bo_2; + reg_WcxrXtYt_1_2 <= WcxrXtYt_1_2; + reg_bc_2 <= bc_2; + reg_out_mt_2 <= o_mt_2; + reg_out_ct_2 <= ct_hold_2; + reg_Ct_1_3 <= Ct_1_3; + reg_WixrXtYt_1_3 <= WixrXtYt_1_3; + reg_Wic_3 <= Wic_3; + reg_bi_3 <= bi_3; + reg_WfxrXtYt_1_3 <= WfxrXtYt_1_3; + reg_Wfc_3 <= Wfc_3; + reg_bf_3 <= bf_3; + reg_WoxrXtYt_1_3 <= WoxrXtYt_1_3; + reg_Woc_3 <= Woc_3; + reg_bo_3 <= bo_3; + reg_WcxrXtYt_1_3 <= WcxrXtYt_1_3; + reg_bc_3 <= bc_3; + reg_out_mt_3 <= o_mt_3; + reg_out_ct_3 <= ct_hold_3; + reg_Ct_1_4 <= Ct_1_4; + reg_WixrXtYt_1_4 <= WixrXtYt_1_4; + reg_Wic_4 <= Wic_4; + reg_bi_4 <= bi_4; + reg_WfxrXtYt_1_4 <= WfxrXtYt_1_4; + reg_Wfc_4 <= Wfc_4; + reg_bf_4 <= bf_4; + reg_WoxrXtYt_1_4 <= WoxrXtYt_1_4; + reg_Woc_4 <= Woc_4; + reg_bo_4 <= bo_4; + reg_WcxrXtYt_1_4 <= WcxrXtYt_1_4; + reg_bc_4 <= bc_4; + reg_out_mt_4 <= o_mt_4; + reg_out_ct_4 <= ct_hold_4; + reg_Ct_1_5 <= Ct_1_5; + reg_WixrXtYt_1_5 <= WixrXtYt_1_5; + reg_Wic_5 <= Wic_5; + reg_bi_5 <= bi_5; + reg_WfxrXtYt_1_5 <= WfxrXtYt_1_5; + reg_Wfc_5 <= Wfc_5; + reg_bf_5 <= bf_5; + reg_WoxrXtYt_1_5 <= WoxrXtYt_1_5; + reg_Woc_5 <= Woc_5; + reg_bo_5 <= bo_5; + reg_WcxrXtYt_1_5 <= WcxrXtYt_1_5; + reg_bc_5 <= bc_5; + reg_out_mt_5 <= o_mt_5; + reg_out_ct_5 <= ct_hold_5; + reg_Ct_1_6 <= Ct_1_6; + reg_WixrXtYt_1_6 <= WixrXtYt_1_6; + reg_Wic_6 <= Wic_6; + reg_bi_6 <= bi_6; + reg_WfxrXtYt_1_6 <= WfxrXtYt_1_6; + reg_Wfc_6 <= Wfc_6; + reg_bf_6 <= bf_6; + reg_WoxrXtYt_1_6 <= WoxrXtYt_1_6; + reg_Woc_6 <= Woc_6; + reg_bo_6 <= bo_6; + reg_WcxrXtYt_1_6 <= WcxrXtYt_1_6; + reg_bc_6 <= bc_6; + reg_out_mt_6 <= o_mt_6; + reg_out_ct_6 <= ct_hold_6; + reg_Ct_1_7 <= Ct_1_7; + reg_WixrXtYt_1_7 <= WixrXtYt_1_7; + reg_Wic_7 <= Wic_7; + reg_bi_7 <= bi_7; + reg_WfxrXtYt_1_7 <= WfxrXtYt_1_7; + reg_Wfc_7 <= Wfc_7; + reg_bf_7 <= bf_7; + reg_WoxrXtYt_1_7 <= WoxrXtYt_1_7; + reg_Woc_7 <= Woc_7; + reg_bo_7 <= bo_7; + reg_WcxrXtYt_1_7 <= WcxrXtYt_1_7; + reg_bc_7 <= bc_7; + reg_out_mt_7 <= o_mt_7; + reg_out_ct_7 <= ct_hold_7; + reg_Ct_1_8 <= Ct_1_8; + reg_WixrXtYt_1_8 <= WixrXtYt_1_8; + reg_Wic_8 <= Wic_8; + reg_bi_8 <= bi_8; + reg_WfxrXtYt_1_8 <= WfxrXtYt_1_8; + reg_Wfc_8 <= Wfc_8; + reg_bf_8 <= bf_8; + reg_WoxrXtYt_1_8 <= WoxrXtYt_1_8; + reg_Woc_8 <= Woc_8; + reg_bo_8 <= bo_8; + reg_WcxrXtYt_1_8 <= WcxrXtYt_1_8; + reg_bc_8 <= bc_8; + reg_out_mt_8 <= o_mt_8; + reg_out_ct_8 <= ct_hold_8; + reg_Ct_1_9 <= Ct_1_9; + reg_WixrXtYt_1_9 <= WixrXtYt_1_9; + reg_Wic_9 <= Wic_9; + reg_bi_9 <= bi_9; + reg_WfxrXtYt_1_9 <= WfxrXtYt_1_9; + reg_Wfc_9 <= Wfc_9; + reg_bf_9 <= bf_9; + reg_WoxrXtYt_1_9 <= WoxrXtYt_1_9; + reg_Woc_9 <= Woc_9; + reg_bo_9 <= bo_9; + reg_WcxrXtYt_1_9 <= WcxrXtYt_1_9; + reg_bc_9 <= bc_9; + reg_out_mt_9 <= o_mt_9; + reg_out_ct_9 <= ct_hold_9; + reg_Ct_1_10 <= Ct_1_10; + reg_WixrXtYt_1_10 <= WixrXtYt_1_10; + reg_Wic_10 <= Wic_10; + reg_bi_10 <= bi_10; + reg_WfxrXtYt_1_10 <= WfxrXtYt_1_10; + reg_Wfc_10 <= Wfc_10; + reg_bf_10 <= bf_10; + reg_WoxrXtYt_1_10 <= WoxrXtYt_1_10; + reg_Woc_10 <= Woc_10; + reg_bo_10 <= bo_10; + reg_WcxrXtYt_1_10 <= WcxrXtYt_1_10; + reg_bc_10 <= bc_10; + reg_out_mt_10 <= o_mt_10; + reg_out_ct_10 <= ct_hold_10; + reg_Ct_1_11 <= Ct_1_11; + reg_WixrXtYt_1_11 <= WixrXtYt_1_11; + reg_Wic_11 <= Wic_11; + reg_bi_11 <= bi_11; + reg_WfxrXtYt_1_11 <= WfxrXtYt_1_11; + reg_Wfc_11 <= Wfc_11; + reg_bf_11 <= bf_11; + reg_WoxrXtYt_1_11 <= WoxrXtYt_1_11; + reg_Woc_11 <= Woc_11; + reg_bo_11 <= bo_11; + reg_WcxrXtYt_1_11 <= WcxrXtYt_1_11; + reg_bc_11 <= bc_11; + reg_out_mt_11 <= o_mt_11; + reg_out_ct_11 <= ct_hold_11; + reg_Ct_1_12 <= Ct_1_12; + reg_WixrXtYt_1_12 <= WixrXtYt_1_12; + reg_Wic_12 <= Wic_12; + reg_bi_12 <= bi_12; + reg_WfxrXtYt_1_12 <= WfxrXtYt_1_12; + reg_Wfc_12 <= Wfc_12; + reg_bf_12 <= bf_12; + reg_WoxrXtYt_1_12 <= WoxrXtYt_1_12; + reg_Woc_12 <= Woc_12; + reg_bo_12 <= bo_12; + reg_WcxrXtYt_1_12 <= WcxrXtYt_1_12; + reg_bc_12 <= bc_12; + reg_out_mt_12 <= o_mt_12; + reg_out_ct_12 <= ct_hold_12; + reg_Ct_1_13 <= Ct_1_13; + reg_WixrXtYt_1_13 <= WixrXtYt_1_13; + reg_Wic_13 <= Wic_13; + reg_bi_13 <= bi_13; + reg_WfxrXtYt_1_13 <= WfxrXtYt_1_13; + reg_Wfc_13 <= Wfc_13; + reg_bf_13 <= bf_13; + reg_WoxrXtYt_1_13 <= WoxrXtYt_1_13; + reg_Woc_13 <= Woc_13; + reg_bo_13 <= bo_13; + reg_WcxrXtYt_1_13 <= WcxrXtYt_1_13; + reg_bc_13 <= bc_13; + reg_out_mt_13 <= o_mt_13; + reg_out_ct_13 <= ct_hold_13; + reg_Ct_1_14 <= Ct_1_14; + reg_WixrXtYt_1_14 <= WixrXtYt_1_14; + reg_Wic_14 <= Wic_14; + reg_bi_14 <= bi_14; + reg_WfxrXtYt_1_14 <= WfxrXtYt_1_14; + reg_Wfc_14 <= Wfc_14; + reg_bf_14 <= bf_14; + reg_WoxrXtYt_1_14 <= WoxrXtYt_1_14; + reg_Woc_14 <= Woc_14; + reg_bo_14 <= bo_14; + reg_WcxrXtYt_1_14 <= WcxrXtYt_1_14; + reg_bc_14 <= bc_14; + reg_out_mt_14 <= o_mt_14; + reg_out_ct_14 <= ct_hold_14; + reg_Ct_1_15 <= Ct_1_15; + reg_WixrXtYt_1_15 <= WixrXtYt_1_15; + reg_Wic_15 <= Wic_15; + reg_bi_15 <= bi_15; + reg_WfxrXtYt_1_15 <= WfxrXtYt_1_15; + reg_Wfc_15 <= Wfc_15; + reg_bf_15 <= bf_15; + reg_WoxrXtYt_1_15 <= WoxrXtYt_1_15; + reg_Woc_15 <= Woc_15; + reg_bo_15 <= bo_15; + reg_WcxrXtYt_1_15 <= WcxrXtYt_1_15; + reg_bc_15 <= bc_15; + reg_out_mt_15 <= o_mt_15; + reg_out_ct_15 <= ct_hold_15; + reg_Ct_1_16 <= Ct_1_16; + reg_WixrXtYt_1_16 <= WixrXtYt_1_16; + reg_Wic_16 <= Wic_16; + reg_bi_16 <= bi_16; + reg_WfxrXtYt_1_16 <= WfxrXtYt_1_16; + reg_Wfc_16 <= Wfc_16; + reg_bf_16 <= bf_16; + reg_WoxrXtYt_1_16 <= WoxrXtYt_1_16; + reg_Woc_16 <= Woc_16; + reg_bo_16 <= bo_16; + reg_WcxrXtYt_1_16 <= WcxrXtYt_1_16; + reg_bc_16 <= bc_16; + reg_out_mt_16 <= o_mt_16; + reg_out_ct_16 <= ct_hold_16; + reg_Ct_1_17 <= Ct_1_17; + reg_WixrXtYt_1_17 <= WixrXtYt_1_17; + reg_Wic_17 <= Wic_17; + reg_bi_17 <= bi_17; + reg_WfxrXtYt_1_17 <= WfxrXtYt_1_17; + reg_Wfc_17 <= Wfc_17; + reg_bf_17 <= bf_17; + reg_WoxrXtYt_1_17 <= WoxrXtYt_1_17; + reg_Woc_17 <= Woc_17; + reg_bo_17 <= bo_17; + reg_WcxrXtYt_1_17 <= WcxrXtYt_1_17; + reg_bc_17 <= bc_17; + reg_out_mt_17 <= o_mt_17; + reg_out_ct_17 <= ct_hold_17; + reg_Ct_1_18 <= Ct_1_18; + reg_WixrXtYt_1_18 <= WixrXtYt_1_18; + reg_Wic_18 <= Wic_18; + reg_bi_18 <= bi_18; + reg_WfxrXtYt_1_18 <= WfxrXtYt_1_18; + reg_Wfc_18 <= Wfc_18; + reg_bf_18 <= bf_18; + reg_WoxrXtYt_1_18 <= WoxrXtYt_1_18; + reg_Woc_18 <= Woc_18; + reg_bo_18 <= bo_18; + reg_WcxrXtYt_1_18 <= WcxrXtYt_1_18; + reg_bc_18 <= bc_18; + reg_out_mt_18 <= o_mt_18; + reg_out_ct_18 <= ct_hold_18; + reg_Ct_1_19 <= Ct_1_19; + reg_WixrXtYt_1_19 <= WixrXtYt_1_19; + reg_Wic_19 <= Wic_19; + reg_bi_19 <= bi_19; + reg_WfxrXtYt_1_19 <= WfxrXtYt_1_19; + reg_Wfc_19 <= Wfc_19; + reg_bf_19 <= bf_19; + reg_WoxrXtYt_1_19 <= WoxrXtYt_1_19; + reg_Woc_19 <= Woc_19; + reg_bo_19 <= bo_19; + reg_WcxrXtYt_1_19 <= WcxrXtYt_1_19; + reg_bc_19 <= bc_19; + reg_out_mt_19 <= o_mt_19; + reg_out_ct_19 <= ct_hold_19; + reg_Ct_1_20 <= Ct_1_20; + reg_WixrXtYt_1_20 <= WixrXtYt_1_20; + reg_Wic_20 <= Wic_20; + reg_bi_20 <= bi_20; + reg_WfxrXtYt_1_20 <= WfxrXtYt_1_20; + reg_Wfc_20 <= Wfc_20; + reg_bf_20 <= bf_20; + reg_WoxrXtYt_1_20 <= WoxrXtYt_1_20; + reg_Woc_20 <= Woc_20; + reg_bo_20 <= bo_20; + reg_WcxrXtYt_1_20 <= WcxrXtYt_1_20; + reg_bc_20 <= bc_20; + reg_out_mt_20 <= o_mt_20; + reg_out_ct_20 <= ct_hold_20; + reg_Ct_1_21 <= Ct_1_21; + reg_WixrXtYt_1_21 <= WixrXtYt_1_21; + reg_Wic_21 <= Wic_21; + reg_bi_21 <= bi_21; + reg_WfxrXtYt_1_21 <= WfxrXtYt_1_21; + reg_Wfc_21 <= Wfc_21; + reg_bf_21 <= bf_21; + reg_WoxrXtYt_1_21 <= WoxrXtYt_1_21; + reg_Woc_21 <= Woc_21; + reg_bo_21 <= bo_21; + reg_WcxrXtYt_1_21 <= WcxrXtYt_1_21; + reg_bc_21 <= bc_21; + reg_out_mt_21 <= o_mt_21; + reg_out_ct_21 <= ct_hold_21; + reg_Ct_1_22 <= Ct_1_22; + reg_WixrXtYt_1_22 <= WixrXtYt_1_22; + reg_Wic_22 <= Wic_22; + reg_bi_22 <= bi_22; + reg_WfxrXtYt_1_22 <= WfxrXtYt_1_22; + reg_Wfc_22 <= Wfc_22; + reg_bf_22 <= bf_22; + reg_WoxrXtYt_1_22 <= WoxrXtYt_1_22; + reg_Woc_22 <= Woc_22; + reg_bo_22 <= bo_22; + reg_WcxrXtYt_1_22 <= WcxrXtYt_1_22; + reg_bc_22 <= bc_22; + reg_out_mt_22 <= o_mt_22; + reg_out_ct_22 <= ct_hold_22; + reg_Ct_1_23 <= Ct_1_23; + reg_WixrXtYt_1_23 <= WixrXtYt_1_23; + reg_Wic_23 <= Wic_23; + reg_bi_23 <= bi_23; + reg_WfxrXtYt_1_23 <= WfxrXtYt_1_23; + reg_Wfc_23 <= Wfc_23; + reg_bf_23 <= bf_23; + reg_WoxrXtYt_1_23 <= WoxrXtYt_1_23; + reg_Woc_23 <= Woc_23; + reg_bo_23 <= bo_23; + reg_WcxrXtYt_1_23 <= WcxrXtYt_1_23; + reg_bc_23 <= bc_23; + reg_out_mt_23 <= o_mt_23; + reg_out_ct_23 <= ct_hold_23; + reg_Ct_1_24 <= Ct_1_24; + reg_WixrXtYt_1_24 <= WixrXtYt_1_24; + reg_Wic_24 <= Wic_24; + reg_bi_24 <= bi_24; + reg_WfxrXtYt_1_24 <= WfxrXtYt_1_24; + reg_Wfc_24 <= Wfc_24; + reg_bf_24 <= bf_24; + reg_WoxrXtYt_1_24 <= WoxrXtYt_1_24; + reg_Woc_24 <= Woc_24; + reg_bo_24 <= bo_24; + reg_WcxrXtYt_1_24 <= WcxrXtYt_1_24; + reg_bc_24 <= bc_24; + reg_out_mt_24 <= o_mt_24; + reg_out_ct_24 <= ct_hold_24; + reg_Ct_1_25 <= Ct_1_25; + reg_WixrXtYt_1_25 <= WixrXtYt_1_25; + reg_Wic_25 <= Wic_25; + reg_bi_25 <= bi_25; + reg_WfxrXtYt_1_25 <= WfxrXtYt_1_25; + reg_Wfc_25 <= Wfc_25; + reg_bf_25 <= bf_25; + reg_WoxrXtYt_1_25 <= WoxrXtYt_1_25; + reg_Woc_25 <= Woc_25; + reg_bo_25 <= bo_25; + reg_WcxrXtYt_1_25 <= WcxrXtYt_1_25; + reg_bc_25 <= bc_25; + reg_out_mt_25 <= o_mt_25; + reg_out_ct_25 <= ct_hold_25; + reg_Ct_1_26 <= Ct_1_26; + reg_WixrXtYt_1_26 <= WixrXtYt_1_26; + reg_Wic_26 <= Wic_26; + reg_bi_26 <= bi_26; + reg_WfxrXtYt_1_26 <= WfxrXtYt_1_26; + reg_Wfc_26 <= Wfc_26; + reg_bf_26 <= bf_26; + reg_WoxrXtYt_1_26 <= WoxrXtYt_1_26; + reg_Woc_26 <= Woc_26; + reg_bo_26 <= bo_26; + reg_WcxrXtYt_1_26 <= WcxrXtYt_1_26; + reg_bc_26 <= bc_26; + reg_out_mt_26 <= o_mt_26; + reg_out_ct_26 <= ct_hold_26; + reg_Ct_1_27 <= Ct_1_27; + reg_WixrXtYt_1_27 <= WixrXtYt_1_27; + reg_Wic_27 <= Wic_27; + reg_bi_27 <= bi_27; + reg_WfxrXtYt_1_27 <= WfxrXtYt_1_27; + reg_Wfc_27 <= Wfc_27; + reg_bf_27 <= bf_27; + reg_WoxrXtYt_1_27 <= WoxrXtYt_1_27; + reg_Woc_27 <= Woc_27; + reg_bo_27 <= bo_27; + reg_WcxrXtYt_1_27 <= WcxrXtYt_1_27; + reg_bc_27 <= bc_27; + reg_out_mt_27 <= o_mt_27; + reg_out_ct_27 <= ct_hold_27; + reg_Ct_1_28 <= Ct_1_28; + reg_WixrXtYt_1_28 <= WixrXtYt_1_28; + reg_Wic_28 <= Wic_28; + reg_bi_28 <= bi_28; + reg_WfxrXtYt_1_28 <= WfxrXtYt_1_28; + reg_Wfc_28 <= Wfc_28; + reg_bf_28 <= bf_28; + reg_WoxrXtYt_1_28 <= WoxrXtYt_1_28; + reg_Woc_28 <= Woc_28; + reg_bo_28 <= bo_28; + reg_WcxrXtYt_1_28 <= WcxrXtYt_1_28; + reg_bc_28 <= bc_28; + reg_out_mt_28 <= o_mt_28; + reg_out_ct_28 <= ct_hold_28; + reg_Ct_1_29 <= Ct_1_29; + reg_WixrXtYt_1_29 <= WixrXtYt_1_29; + reg_Wic_29 <= Wic_29; + reg_bi_29 <= bi_29; + reg_WfxrXtYt_1_29 <= WfxrXtYt_1_29; + reg_Wfc_29 <= Wfc_29; + reg_bf_29 <= bf_29; + reg_WoxrXtYt_1_29 <= WoxrXtYt_1_29; + reg_Woc_29 <= Woc_29; + reg_bo_29 <= bo_29; + reg_WcxrXtYt_1_29 <= WcxrXtYt_1_29; + reg_bc_29 <= bc_29; + reg_out_mt_29 <= o_mt_29; + reg_out_ct_29 <= ct_hold_29; + reg_Ct_1_30 <= Ct_1_30; + reg_WixrXtYt_1_30 <= WixrXtYt_1_30; + reg_Wic_30 <= Wic_30; + reg_bi_30 <= bi_30; + reg_WfxrXtYt_1_30 <= WfxrXtYt_1_30; + reg_Wfc_30 <= Wfc_30; + reg_bf_30 <= bf_30; + reg_WoxrXtYt_1_30 <= WoxrXtYt_1_30; + reg_Woc_30 <= Woc_30; + reg_bo_30 <= bo_30; + reg_WcxrXtYt_1_30 <= WcxrXtYt_1_30; + reg_bc_30 <= bc_30; + reg_out_mt_30 <= o_mt_30; + reg_out_ct_30 <= ct_hold_30; + reg_Ct_1_31 <= Ct_1_31; + reg_WixrXtYt_1_31 <= WixrXtYt_1_31; + reg_Wic_31 <= Wic_31; + reg_bi_31 <= bi_31; + reg_WfxrXtYt_1_31 <= WfxrXtYt_1_31; + reg_Wfc_31 <= Wfc_31; + reg_bf_31 <= bf_31; + reg_WoxrXtYt_1_31 <= WoxrXtYt_1_31; + reg_Woc_31 <= Woc_31; + reg_bo_31 <= bo_31; + reg_WcxrXtYt_1_31 <= WcxrXtYt_1_31; + reg_bc_31 <= bc_31; + reg_out_mt_31 <= o_mt_31; + reg_out_ct_31 <= ct_hold_31; + end +end +assign out_mt_0 = reg_out_mt_0; +assign out_ct_0 = reg_out_ct_0; +assign out_mt_1 = reg_out_mt_1; +assign out_ct_1 = reg_out_ct_1; +assign out_mt_2 = reg_out_mt_2; +assign out_ct_2 = reg_out_ct_2; +assign out_mt_3 = reg_out_mt_3; +assign out_ct_3 = reg_out_ct_3; +assign out_mt_4 = reg_out_mt_4; +assign out_ct_4 = reg_out_ct_4; +assign out_mt_5 = reg_out_mt_5; +assign out_ct_5 = reg_out_ct_5; +assign out_mt_6 = reg_out_mt_6; +assign out_ct_6 = reg_out_ct_6; +assign out_mt_7 = reg_out_mt_7; +assign out_ct_7 = reg_out_ct_7; +assign out_mt_8 = reg_out_mt_8; +assign out_ct_8 = reg_out_ct_8; +assign out_mt_9 = reg_out_mt_9; +assign out_ct_9 = reg_out_ct_9; +assign out_mt_10 = reg_out_mt_10; +assign out_ct_10 = reg_out_ct_10; +assign out_mt_11 = reg_out_mt_11; +assign out_ct_11 = reg_out_ct_11; +assign out_mt_12 = reg_out_mt_12; +assign out_ct_12 = reg_out_ct_12; +assign out_mt_13 = reg_out_mt_13; +assign out_ct_13 = reg_out_ct_13; +assign out_mt_14 = reg_out_mt_14; +assign out_ct_14 = reg_out_ct_14; +assign out_mt_15 = reg_out_mt_15; +assign out_ct_15 = reg_out_ct_15; +assign out_mt_16 = reg_out_mt_16; +assign out_ct_16 = reg_out_ct_16; +assign out_mt_17 = reg_out_mt_17; +assign out_ct_17 = reg_out_ct_17; +assign out_mt_18 = reg_out_mt_18; +assign out_ct_18 = reg_out_ct_18; +assign out_mt_19 = reg_out_mt_19; +assign out_ct_19 = reg_out_ct_19; +assign out_mt_20 = reg_out_mt_20; +assign out_ct_20 = reg_out_ct_20; +assign out_mt_21 = reg_out_mt_21; +assign out_ct_21 = reg_out_ct_21; +assign out_mt_22 = reg_out_mt_22; +assign out_ct_22 = reg_out_ct_22; +assign out_mt_23 = reg_out_mt_23; +assign out_ct_23 = reg_out_ct_23; +assign out_mt_24 = reg_out_mt_24; +assign out_ct_24 = reg_out_ct_24; +assign out_mt_25 = reg_out_mt_25; +assign out_ct_25 = reg_out_ct_25; +assign out_mt_26 = reg_out_mt_26; +assign out_ct_26 = reg_out_ct_26; +assign out_mt_27 = reg_out_mt_27; +assign out_ct_27 = reg_out_ct_27; +assign out_mt_28 = reg_out_mt_28; +assign out_ct_28 = reg_out_ct_28; +assign out_mt_29 = reg_out_mt_29; +assign out_ct_29 = reg_out_ct_29; +assign out_mt_30 = reg_out_mt_30; +assign out_ct_30 = reg_out_ct_30; +assign out_mt_31 = reg_out_mt_31; +assign out_ct_31 = reg_out_ct_31; +assign o_valid = reg_o_valid; +assign o_ready = enable; +endmodule + +module lstm_gate_18_10_32_1 ( + input clk, + input reset, + input i_ready, + input i_valid, + input [17:0] stage1_result_0, + input [17:0] weight_0, + input [17:0] Ct_1_0, + input [17:0] bias_0, + output [17:0] gate_output_0, + input [17:0] stage1_result_1, + input [17:0] weight_1, + input [17:0] Ct_1_1, + input [17:0] bias_1, + output [17:0] gate_output_1, + input [17:0] stage1_result_2, + input [17:0] weight_2, + input [17:0] Ct_1_2, + input [17:0] bias_2, + output [17:0] gate_output_2, + input [17:0] stage1_result_3, + input [17:0] weight_3, + input [17:0] Ct_1_3, + input [17:0] bias_3, + output [17:0] gate_output_3, + input [17:0] stage1_result_4, + input [17:0] weight_4, + input [17:0] Ct_1_4, + input [17:0] bias_4, + output [17:0] gate_output_4, + input [17:0] stage1_result_5, + input [17:0] weight_5, + input [17:0] Ct_1_5, + input [17:0] bias_5, + output [17:0] gate_output_5, + input [17:0] stage1_result_6, + input [17:0] weight_6, + input [17:0] Ct_1_6, + input [17:0] bias_6, + output [17:0] gate_output_6, + input [17:0] stage1_result_7, + input [17:0] weight_7, + input [17:0] Ct_1_7, + input [17:0] bias_7, + output [17:0] gate_output_7, + input [17:0] stage1_result_8, + input [17:0] weight_8, + input [17:0] Ct_1_8, + input [17:0] bias_8, + output [17:0] gate_output_8, + input [17:0] stage1_result_9, + input [17:0] weight_9, + input [17:0] Ct_1_9, + input [17:0] bias_9, + output [17:0] gate_output_9, + input [17:0] stage1_result_10, + input [17:0] weight_10, + input [17:0] Ct_1_10, + input [17:0] bias_10, + output [17:0] gate_output_10, + input [17:0] stage1_result_11, + input [17:0] weight_11, + input [17:0] Ct_1_11, + input [17:0] bias_11, + output [17:0] gate_output_11, + input [17:0] stage1_result_12, + input [17:0] weight_12, + input [17:0] Ct_1_12, + input [17:0] bias_12, + output [17:0] gate_output_12, + input [17:0] stage1_result_13, + input [17:0] weight_13, + input [17:0] Ct_1_13, + input [17:0] bias_13, + output [17:0] gate_output_13, + input [17:0] stage1_result_14, + input [17:0] weight_14, + input [17:0] Ct_1_14, + input [17:0] bias_14, + output [17:0] gate_output_14, + input [17:0] stage1_result_15, + input [17:0] weight_15, + input [17:0] Ct_1_15, + input [17:0] bias_15, + output [17:0] gate_output_15, + input [17:0] stage1_result_16, + input [17:0] weight_16, + input [17:0] Ct_1_16, + input [17:0] bias_16, + output [17:0] gate_output_16, + input [17:0] stage1_result_17, + input [17:0] weight_17, + input [17:0] Ct_1_17, + input [17:0] bias_17, + output [17:0] gate_output_17, + input [17:0] stage1_result_18, + input [17:0] weight_18, + input [17:0] Ct_1_18, + input [17:0] bias_18, + output [17:0] gate_output_18, + input [17:0] stage1_result_19, + input [17:0] weight_19, + input [17:0] Ct_1_19, + input [17:0] bias_19, + output [17:0] gate_output_19, + input [17:0] stage1_result_20, + input [17:0] weight_20, + input [17:0] Ct_1_20, + input [17:0] bias_20, + output [17:0] gate_output_20, + input [17:0] stage1_result_21, + input [17:0] weight_21, + input [17:0] Ct_1_21, + input [17:0] bias_21, + output [17:0] gate_output_21, + input [17:0] stage1_result_22, + input [17:0] weight_22, + input [17:0] Ct_1_22, + input [17:0] bias_22, + output [17:0] gate_output_22, + input [17:0] stage1_result_23, + input [17:0] weight_23, + input [17:0] Ct_1_23, + input [17:0] bias_23, + output [17:0] gate_output_23, + input [17:0] stage1_result_24, + input [17:0] weight_24, + input [17:0] Ct_1_24, + input [17:0] bias_24, + output [17:0] gate_output_24, + input [17:0] stage1_result_25, + input [17:0] weight_25, + input [17:0] Ct_1_25, + input [17:0] bias_25, + output [17:0] gate_output_25, + input [17:0] stage1_result_26, + input [17:0] weight_26, + input [17:0] Ct_1_26, + input [17:0] bias_26, + output [17:0] gate_output_26, + input [17:0] stage1_result_27, + input [17:0] weight_27, + input [17:0] Ct_1_27, + input [17:0] bias_27, + output [17:0] gate_output_27, + input [17:0] stage1_result_28, + input [17:0] weight_28, + input [17:0] Ct_1_28, + input [17:0] bias_28, + output [17:0] gate_output_28, + input [17:0] stage1_result_29, + input [17:0] weight_29, + input [17:0] Ct_1_29, + input [17:0] bias_29, + output [17:0] gate_output_29, + input [17:0] stage1_result_30, + input [17:0] weight_30, + input [17:0] Ct_1_30, + input [17:0] bias_30, + output [17:0] gate_output_30, + input [17:0] stage1_result_31, + input [17:0] weight_31, + input [17:0] Ct_1_31, + input [17:0] bias_31, + output [17:0] gate_output_31, + output o_valid, + output o_ready +); + +wire mult_valid, add0_valid, add1_valid, add2_valid; +wire mult_ready, add0_ready, add1_ready, add2_ready; +wire sigmoid_valid_0, sigmoid_ready_0; +wire [17:0] o_mult_0; +wire [17:0] o_add0_0; +wire [17:0] o_add1_0; +wire [17:0] add1_hold_0; +wire [17:0] o_add2_0; +wire [17:0] o_sigmoid_0; +wire sigmoid_valid_1, sigmoid_ready_1; +wire [17:0] o_mult_1; +wire [17:0] o_add0_1; +wire [17:0] o_add1_1; +wire [17:0] add1_hold_1; +wire [17:0] o_add2_1; +wire [17:0] o_sigmoid_1; +wire sigmoid_valid_2, sigmoid_ready_2; +wire [17:0] o_mult_2; +wire [17:0] o_add0_2; +wire [17:0] o_add1_2; +wire [17:0] add1_hold_2; +wire [17:0] o_add2_2; +wire [17:0] o_sigmoid_2; +wire sigmoid_valid_3, sigmoid_ready_3; +wire [17:0] o_mult_3; +wire [17:0] o_add0_3; +wire [17:0] o_add1_3; +wire [17:0] add1_hold_3; +wire [17:0] o_add2_3; +wire [17:0] o_sigmoid_3; +wire sigmoid_valid_4, sigmoid_ready_4; +wire [17:0] o_mult_4; +wire [17:0] o_add0_4; +wire [17:0] o_add1_4; +wire [17:0] add1_hold_4; +wire [17:0] o_add2_4; +wire [17:0] o_sigmoid_4; +wire sigmoid_valid_5, sigmoid_ready_5; +wire [17:0] o_mult_5; +wire [17:0] o_add0_5; +wire [17:0] o_add1_5; +wire [17:0] add1_hold_5; +wire [17:0] o_add2_5; +wire [17:0] o_sigmoid_5; +wire sigmoid_valid_6, sigmoid_ready_6; +wire [17:0] o_mult_6; +wire [17:0] o_add0_6; +wire [17:0] o_add1_6; +wire [17:0] add1_hold_6; +wire [17:0] o_add2_6; +wire [17:0] o_sigmoid_6; +wire sigmoid_valid_7, sigmoid_ready_7; +wire [17:0] o_mult_7; +wire [17:0] o_add0_7; +wire [17:0] o_add1_7; +wire [17:0] add1_hold_7; +wire [17:0] o_add2_7; +wire [17:0] o_sigmoid_7; +wire sigmoid_valid_8, sigmoid_ready_8; +wire [17:0] o_mult_8; +wire [17:0] o_add0_8; +wire [17:0] o_add1_8; +wire [17:0] add1_hold_8; +wire [17:0] o_add2_8; +wire [17:0] o_sigmoid_8; +wire sigmoid_valid_9, sigmoid_ready_9; +wire [17:0] o_mult_9; +wire [17:0] o_add0_9; +wire [17:0] o_add1_9; +wire [17:0] add1_hold_9; +wire [17:0] o_add2_9; +wire [17:0] o_sigmoid_9; +wire sigmoid_valid_10, sigmoid_ready_10; +wire [17:0] o_mult_10; +wire [17:0] o_add0_10; +wire [17:0] o_add1_10; +wire [17:0] add1_hold_10; +wire [17:0] o_add2_10; +wire [17:0] o_sigmoid_10; +wire sigmoid_valid_11, sigmoid_ready_11; +wire [17:0] o_mult_11; +wire [17:0] o_add0_11; +wire [17:0] o_add1_11; +wire [17:0] add1_hold_11; +wire [17:0] o_add2_11; +wire [17:0] o_sigmoid_11; +wire sigmoid_valid_12, sigmoid_ready_12; +wire [17:0] o_mult_12; +wire [17:0] o_add0_12; +wire [17:0] o_add1_12; +wire [17:0] add1_hold_12; +wire [17:0] o_add2_12; +wire [17:0] o_sigmoid_12; +wire sigmoid_valid_13, sigmoid_ready_13; +wire [17:0] o_mult_13; +wire [17:0] o_add0_13; +wire [17:0] o_add1_13; +wire [17:0] add1_hold_13; +wire [17:0] o_add2_13; +wire [17:0] o_sigmoid_13; +wire sigmoid_valid_14, sigmoid_ready_14; +wire [17:0] o_mult_14; +wire [17:0] o_add0_14; +wire [17:0] o_add1_14; +wire [17:0] add1_hold_14; +wire [17:0] o_add2_14; +wire [17:0] o_sigmoid_14; +wire sigmoid_valid_15, sigmoid_ready_15; +wire [17:0] o_mult_15; +wire [17:0] o_add0_15; +wire [17:0] o_add1_15; +wire [17:0] add1_hold_15; +wire [17:0] o_add2_15; +wire [17:0] o_sigmoid_15; +wire sigmoid_valid_16, sigmoid_ready_16; +wire [17:0] o_mult_16; +wire [17:0] o_add0_16; +wire [17:0] o_add1_16; +wire [17:0] add1_hold_16; +wire [17:0] o_add2_16; +wire [17:0] o_sigmoid_16; +wire sigmoid_valid_17, sigmoid_ready_17; +wire [17:0] o_mult_17; +wire [17:0] o_add0_17; +wire [17:0] o_add1_17; +wire [17:0] add1_hold_17; +wire [17:0] o_add2_17; +wire [17:0] o_sigmoid_17; +wire sigmoid_valid_18, sigmoid_ready_18; +wire [17:0] o_mult_18; +wire [17:0] o_add0_18; +wire [17:0] o_add1_18; +wire [17:0] add1_hold_18; +wire [17:0] o_add2_18; +wire [17:0] o_sigmoid_18; +wire sigmoid_valid_19, sigmoid_ready_19; +wire [17:0] o_mult_19; +wire [17:0] o_add0_19; +wire [17:0] o_add1_19; +wire [17:0] add1_hold_19; +wire [17:0] o_add2_19; +wire [17:0] o_sigmoid_19; +wire sigmoid_valid_20, sigmoid_ready_20; +wire [17:0] o_mult_20; +wire [17:0] o_add0_20; +wire [17:0] o_add1_20; +wire [17:0] add1_hold_20; +wire [17:0] o_add2_20; +wire [17:0] o_sigmoid_20; +wire sigmoid_valid_21, sigmoid_ready_21; +wire [17:0] o_mult_21; +wire [17:0] o_add0_21; +wire [17:0] o_add1_21; +wire [17:0] add1_hold_21; +wire [17:0] o_add2_21; +wire [17:0] o_sigmoid_21; +wire sigmoid_valid_22, sigmoid_ready_22; +wire [17:0] o_mult_22; +wire [17:0] o_add0_22; +wire [17:0] o_add1_22; +wire [17:0] add1_hold_22; +wire [17:0] o_add2_22; +wire [17:0] o_sigmoid_22; +wire sigmoid_valid_23, sigmoid_ready_23; +wire [17:0] o_mult_23; +wire [17:0] o_add0_23; +wire [17:0] o_add1_23; +wire [17:0] add1_hold_23; +wire [17:0] o_add2_23; +wire [17:0] o_sigmoid_23; +wire sigmoid_valid_24, sigmoid_ready_24; +wire [17:0] o_mult_24; +wire [17:0] o_add0_24; +wire [17:0] o_add1_24; +wire [17:0] add1_hold_24; +wire [17:0] o_add2_24; +wire [17:0] o_sigmoid_24; +wire sigmoid_valid_25, sigmoid_ready_25; +wire [17:0] o_mult_25; +wire [17:0] o_add0_25; +wire [17:0] o_add1_25; +wire [17:0] add1_hold_25; +wire [17:0] o_add2_25; +wire [17:0] o_sigmoid_25; +wire sigmoid_valid_26, sigmoid_ready_26; +wire [17:0] o_mult_26; +wire [17:0] o_add0_26; +wire [17:0] o_add1_26; +wire [17:0] add1_hold_26; +wire [17:0] o_add2_26; +wire [17:0] o_sigmoid_26; +wire sigmoid_valid_27, sigmoid_ready_27; +wire [17:0] o_mult_27; +wire [17:0] o_add0_27; +wire [17:0] o_add1_27; +wire [17:0] add1_hold_27; +wire [17:0] o_add2_27; +wire [17:0] o_sigmoid_27; +wire sigmoid_valid_28, sigmoid_ready_28; +wire [17:0] o_mult_28; +wire [17:0] o_add0_28; +wire [17:0] o_add1_28; +wire [17:0] add1_hold_28; +wire [17:0] o_add2_28; +wire [17:0] o_sigmoid_28; +wire sigmoid_valid_29, sigmoid_ready_29; +wire [17:0] o_mult_29; +wire [17:0] o_add0_29; +wire [17:0] o_add1_29; +wire [17:0] add1_hold_29; +wire [17:0] o_add2_29; +wire [17:0] o_sigmoid_29; +wire sigmoid_valid_30, sigmoid_ready_30; +wire [17:0] o_mult_30; +wire [17:0] o_add0_30; +wire [17:0] o_add1_30; +wire [17:0] add1_hold_30; +wire [17:0] o_add2_30; +wire [17:0] o_sigmoid_30; +wire sigmoid_valid_31, sigmoid_ready_31; +wire [17:0] o_mult_31; +wire [17:0] o_add0_31; +wire [17:0] o_add1_31; +wire [17:0] add1_hold_31; +wire [17:0] o_add2_31; +wire [17:0] o_sigmoid_31; +wire enable; +assign enable = i_ready; + +elementwise_mult_core_18_18_10_32_1 elementwise_mult_core_18_18_10_32_1_mult ( + .clk(clk), + .reset(reset), + .i_valid(i_valid), + .i_ready(add2_ready), + .i_A_0(weight_0), + .i_B_0(Ct_1_0), + .o_C_0(o_mult_0), + .i_A_1(weight_1), + .i_B_1(Ct_1_1), + .o_C_1(o_mult_1), + .i_A_2(weight_2), + .i_B_2(Ct_1_2), + .o_C_2(o_mult_2), + .i_A_3(weight_3), + .i_B_3(Ct_1_3), + .o_C_3(o_mult_3), + .i_A_4(weight_4), + .i_B_4(Ct_1_4), + .o_C_4(o_mult_4), + .i_A_5(weight_5), + .i_B_5(Ct_1_5), + .o_C_5(o_mult_5), + .i_A_6(weight_6), + .i_B_6(Ct_1_6), + .o_C_6(o_mult_6), + .i_A_7(weight_7), + .i_B_7(Ct_1_7), + .o_C_7(o_mult_7), + .i_A_8(weight_8), + .i_B_8(Ct_1_8), + .o_C_8(o_mult_8), + .i_A_9(weight_9), + .i_B_9(Ct_1_9), + .o_C_9(o_mult_9), + .i_A_10(weight_10), + .i_B_10(Ct_1_10), + .o_C_10(o_mult_10), + .i_A_11(weight_11), + .i_B_11(Ct_1_11), + .o_C_11(o_mult_11), + .i_A_12(weight_12), + .i_B_12(Ct_1_12), + .o_C_12(o_mult_12), + .i_A_13(weight_13), + .i_B_13(Ct_1_13), + .o_C_13(o_mult_13), + .i_A_14(weight_14), + .i_B_14(Ct_1_14), + .o_C_14(o_mult_14), + .i_A_15(weight_15), + .i_B_15(Ct_1_15), + .o_C_15(o_mult_15), + .i_A_16(weight_16), + .i_B_16(Ct_1_16), + .o_C_16(o_mult_16), + .i_A_17(weight_17), + .i_B_17(Ct_1_17), + .o_C_17(o_mult_17), + .i_A_18(weight_18), + .i_B_18(Ct_1_18), + .o_C_18(o_mult_18), + .i_A_19(weight_19), + .i_B_19(Ct_1_19), + .o_C_19(o_mult_19), + .i_A_20(weight_20), + .i_B_20(Ct_1_20), + .o_C_20(o_mult_20), + .i_A_21(weight_21), + .i_B_21(Ct_1_21), + .o_C_21(o_mult_21), + .i_A_22(weight_22), + .i_B_22(Ct_1_22), + .o_C_22(o_mult_22), + .i_A_23(weight_23), + .i_B_23(Ct_1_23), + .o_C_23(o_mult_23), + .i_A_24(weight_24), + .i_B_24(Ct_1_24), + .o_C_24(o_mult_24), + .i_A_25(weight_25), + .i_B_25(Ct_1_25), + .o_C_25(o_mult_25), + .i_A_26(weight_26), + .i_B_26(Ct_1_26), + .o_C_26(o_mult_26), + .i_A_27(weight_27), + .i_B_27(Ct_1_27), + .o_C_27(o_mult_27), + .i_A_28(weight_28), + .i_B_28(Ct_1_28), + .o_C_28(o_mult_28), + .i_A_29(weight_29), + .i_B_29(Ct_1_29), + .o_C_29(o_mult_29), + .i_A_30(weight_30), + .i_B_30(Ct_1_30), + .o_C_30(o_mult_30), + .i_A_31(weight_31), + .i_B_31(Ct_1_31), + .o_C_31(o_mult_31), + .o_valid(mult_valid), + .o_ready(mult_ready) +); + +elementwise_add_core_18_18_32 elementwise_add_core_18_18_32_add_1 ( + .clk(clk), + .reset(reset), + .i_valid(i_valid), + .i_ready(add2_ready), + .i_A_0(stage1_result_0), + .i_B_0(bias_0), + .o_C_0(o_add1_0), + .i_A_1(stage1_result_1), + .i_B_1(bias_1), + .o_C_1(o_add1_1), + .i_A_2(stage1_result_2), + .i_B_2(bias_2), + .o_C_2(o_add1_2), + .i_A_3(stage1_result_3), + .i_B_3(bias_3), + .o_C_3(o_add1_3), + .i_A_4(stage1_result_4), + .i_B_4(bias_4), + .o_C_4(o_add1_4), + .i_A_5(stage1_result_5), + .i_B_5(bias_5), + .o_C_5(o_add1_5), + .i_A_6(stage1_result_6), + .i_B_6(bias_6), + .o_C_6(o_add1_6), + .i_A_7(stage1_result_7), + .i_B_7(bias_7), + .o_C_7(o_add1_7), + .i_A_8(stage1_result_8), + .i_B_8(bias_8), + .o_C_8(o_add1_8), + .i_A_9(stage1_result_9), + .i_B_9(bias_9), + .o_C_9(o_add1_9), + .i_A_10(stage1_result_10), + .i_B_10(bias_10), + .o_C_10(o_add1_10), + .i_A_11(stage1_result_11), + .i_B_11(bias_11), + .o_C_11(o_add1_11), + .i_A_12(stage1_result_12), + .i_B_12(bias_12), + .o_C_12(o_add1_12), + .i_A_13(stage1_result_13), + .i_B_13(bias_13), + .o_C_13(o_add1_13), + .i_A_14(stage1_result_14), + .i_B_14(bias_14), + .o_C_14(o_add1_14), + .i_A_15(stage1_result_15), + .i_B_15(bias_15), + .o_C_15(o_add1_15), + .i_A_16(stage1_result_16), + .i_B_16(bias_16), + .o_C_16(o_add1_16), + .i_A_17(stage1_result_17), + .i_B_17(bias_17), + .o_C_17(o_add1_17), + .i_A_18(stage1_result_18), + .i_B_18(bias_18), + .o_C_18(o_add1_18), + .i_A_19(stage1_result_19), + .i_B_19(bias_19), + .o_C_19(o_add1_19), + .i_A_20(stage1_result_20), + .i_B_20(bias_20), + .o_C_20(o_add1_20), + .i_A_21(stage1_result_21), + .i_B_21(bias_21), + .o_C_21(o_add1_21), + .i_A_22(stage1_result_22), + .i_B_22(bias_22), + .o_C_22(o_add1_22), + .i_A_23(stage1_result_23), + .i_B_23(bias_23), + .o_C_23(o_add1_23), + .i_A_24(stage1_result_24), + .i_B_24(bias_24), + .o_C_24(o_add1_24), + .i_A_25(stage1_result_25), + .i_B_25(bias_25), + .o_C_25(o_add1_25), + .i_A_26(stage1_result_26), + .i_B_26(bias_26), + .o_C_26(o_add1_26), + .i_A_27(stage1_result_27), + .i_B_27(bias_27), + .o_C_27(o_add1_27), + .i_A_28(stage1_result_28), + .i_B_28(bias_28), + .o_C_28(o_add1_28), + .i_A_29(stage1_result_29), + .i_B_29(bias_29), + .o_C_29(o_add1_29), + .i_A_30(stage1_result_30), + .i_B_30(bias_30), + .o_C_30(o_add1_30), + .i_A_31(stage1_result_31), + .i_B_31(bias_31), + .o_C_31(o_add1_31), + .o_valid(add1_valid), + .o_ready(add1_ready) +); + +shift_register_group_18_32_10 shift_register_group_18_32_10_Ct ( + .clk(clk), + .enable(enable), + .in_0(o_add1_0), + .out_0(add1_hold_0), + .in_1(o_add1_1), + .out_1(add1_hold_1), + .in_2(o_add1_2), + .out_2(add1_hold_2), + .in_3(o_add1_3), + .out_3(add1_hold_3), + .in_4(o_add1_4), + .out_4(add1_hold_4), + .in_5(o_add1_5), + .out_5(add1_hold_5), + .in_6(o_add1_6), + .out_6(add1_hold_6), + .in_7(o_add1_7), + .out_7(add1_hold_7), + .in_8(o_add1_8), + .out_8(add1_hold_8), + .in_9(o_add1_9), + .out_9(add1_hold_9), + .in_10(o_add1_10), + .out_10(add1_hold_10), + .in_11(o_add1_11), + .out_11(add1_hold_11), + .in_12(o_add1_12), + .out_12(add1_hold_12), + .in_13(o_add1_13), + .out_13(add1_hold_13), + .in_14(o_add1_14), + .out_14(add1_hold_14), + .in_15(o_add1_15), + .out_15(add1_hold_15), + .in_16(o_add1_16), + .out_16(add1_hold_16), + .in_17(o_add1_17), + .out_17(add1_hold_17), + .in_18(o_add1_18), + .out_18(add1_hold_18), + .in_19(o_add1_19), + .out_19(add1_hold_19), + .in_20(o_add1_20), + .out_20(add1_hold_20), + .in_21(o_add1_21), + .out_21(add1_hold_21), + .in_22(o_add1_22), + .out_22(add1_hold_22), + .in_23(o_add1_23), + .out_23(add1_hold_23), + .in_24(o_add1_24), + .out_24(add1_hold_24), + .in_25(o_add1_25), + .out_25(add1_hold_25), + .in_26(o_add1_26), + .out_26(add1_hold_26), + .in_27(o_add1_27), + .out_27(add1_hold_27), + .in_28(o_add1_28), + .out_28(add1_hold_28), + .in_29(o_add1_29), + .out_29(add1_hold_29), + .in_30(o_add1_30), + .out_30(add1_hold_30), + .in_31(o_add1_31), + .out_31(add1_hold_31), + .reset(reset) +); + +elementwise_add_core_18_18_32 elementwise_add_core_18_18_32_add_2 ( + .clk(clk), + .reset(reset), + .i_valid(mult_valid), + .i_ready(sigmoid_ready_0), + .i_A_0(add1_hold_0), + .i_B_0(o_mult_0), + .o_C_0(o_add2_0), + .i_A_1(add1_hold_1), + .i_B_1(o_mult_1), + .o_C_1(o_add2_1), + .i_A_2(add1_hold_2), + .i_B_2(o_mult_2), + .o_C_2(o_add2_2), + .i_A_3(add1_hold_3), + .i_B_3(o_mult_3), + .o_C_3(o_add2_3), + .i_A_4(add1_hold_4), + .i_B_4(o_mult_4), + .o_C_4(o_add2_4), + .i_A_5(add1_hold_5), + .i_B_5(o_mult_5), + .o_C_5(o_add2_5), + .i_A_6(add1_hold_6), + .i_B_6(o_mult_6), + .o_C_6(o_add2_6), + .i_A_7(add1_hold_7), + .i_B_7(o_mult_7), + .o_C_7(o_add2_7), + .i_A_8(add1_hold_8), + .i_B_8(o_mult_8), + .o_C_8(o_add2_8), + .i_A_9(add1_hold_9), + .i_B_9(o_mult_9), + .o_C_9(o_add2_9), + .i_A_10(add1_hold_10), + .i_B_10(o_mult_10), + .o_C_10(o_add2_10), + .i_A_11(add1_hold_11), + .i_B_11(o_mult_11), + .o_C_11(o_add2_11), + .i_A_12(add1_hold_12), + .i_B_12(o_mult_12), + .o_C_12(o_add2_12), + .i_A_13(add1_hold_13), + .i_B_13(o_mult_13), + .o_C_13(o_add2_13), + .i_A_14(add1_hold_14), + .i_B_14(o_mult_14), + .o_C_14(o_add2_14), + .i_A_15(add1_hold_15), + .i_B_15(o_mult_15), + .o_C_15(o_add2_15), + .i_A_16(add1_hold_16), + .i_B_16(o_mult_16), + .o_C_16(o_add2_16), + .i_A_17(add1_hold_17), + .i_B_17(o_mult_17), + .o_C_17(o_add2_17), + .i_A_18(add1_hold_18), + .i_B_18(o_mult_18), + .o_C_18(o_add2_18), + .i_A_19(add1_hold_19), + .i_B_19(o_mult_19), + .o_C_19(o_add2_19), + .i_A_20(add1_hold_20), + .i_B_20(o_mult_20), + .o_C_20(o_add2_20), + .i_A_21(add1_hold_21), + .i_B_21(o_mult_21), + .o_C_21(o_add2_21), + .i_A_22(add1_hold_22), + .i_B_22(o_mult_22), + .o_C_22(o_add2_22), + .i_A_23(add1_hold_23), + .i_B_23(o_mult_23), + .o_C_23(o_add2_23), + .i_A_24(add1_hold_24), + .i_B_24(o_mult_24), + .o_C_24(o_add2_24), + .i_A_25(add1_hold_25), + .i_B_25(o_mult_25), + .o_C_25(o_add2_25), + .i_A_26(add1_hold_26), + .i_B_26(o_mult_26), + .o_C_26(o_add2_26), + .i_A_27(add1_hold_27), + .i_B_27(o_mult_27), + .o_C_27(o_add2_27), + .i_A_28(add1_hold_28), + .i_B_28(o_mult_28), + .o_C_28(o_add2_28), + .i_A_29(add1_hold_29), + .i_B_29(o_mult_29), + .o_C_29(o_add2_29), + .i_A_30(add1_hold_30), + .i_B_30(o_mult_30), + .o_C_30(o_add2_30), + .i_A_31(add1_hold_31), + .i_B_31(o_mult_31), + .o_C_31(o_add2_31), + .o_valid(add2_valid), + .o_ready(add2_ready) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_0 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_0), + .o_valid(sigmoid_valid_0), + .i_x(o_add2_0), + .o_y(o_sigmoid_0) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_1 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_1), + .o_valid(sigmoid_valid_1), + .i_x(o_add2_1), + .o_y(o_sigmoid_1) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_2 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_2), + .o_valid(sigmoid_valid_2), + .i_x(o_add2_2), + .o_y(o_sigmoid_2) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_3 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_3), + .o_valid(sigmoid_valid_3), + .i_x(o_add2_3), + .o_y(o_sigmoid_3) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_4 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_4), + .o_valid(sigmoid_valid_4), + .i_x(o_add2_4), + .o_y(o_sigmoid_4) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_5 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_5), + .o_valid(sigmoid_valid_5), + .i_x(o_add2_5), + .o_y(o_sigmoid_5) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_6 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_6), + .o_valid(sigmoid_valid_6), + .i_x(o_add2_6), + .o_y(o_sigmoid_6) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_7 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_7), + .o_valid(sigmoid_valid_7), + .i_x(o_add2_7), + .o_y(o_sigmoid_7) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_8 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_8), + .o_valid(sigmoid_valid_8), + .i_x(o_add2_8), + .o_y(o_sigmoid_8) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_9 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_9), + .o_valid(sigmoid_valid_9), + .i_x(o_add2_9), + .o_y(o_sigmoid_9) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_10 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_10), + .o_valid(sigmoid_valid_10), + .i_x(o_add2_10), + .o_y(o_sigmoid_10) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_11 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_11), + .o_valid(sigmoid_valid_11), + .i_x(o_add2_11), + .o_y(o_sigmoid_11) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_12 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_12), + .o_valid(sigmoid_valid_12), + .i_x(o_add2_12), + .o_y(o_sigmoid_12) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_13 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_13), + .o_valid(sigmoid_valid_13), + .i_x(o_add2_13), + .o_y(o_sigmoid_13) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_14 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_14), + .o_valid(sigmoid_valid_14), + .i_x(o_add2_14), + .o_y(o_sigmoid_14) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_15 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_15), + .o_valid(sigmoid_valid_15), + .i_x(o_add2_15), + .o_y(o_sigmoid_15) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_16 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_16), + .o_valid(sigmoid_valid_16), + .i_x(o_add2_16), + .o_y(o_sigmoid_16) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_17 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_17), + .o_valid(sigmoid_valid_17), + .i_x(o_add2_17), + .o_y(o_sigmoid_17) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_18 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_18), + .o_valid(sigmoid_valid_18), + .i_x(o_add2_18), + .o_y(o_sigmoid_18) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_19 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_19), + .o_valid(sigmoid_valid_19), + .i_x(o_add2_19), + .o_y(o_sigmoid_19) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_20 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_20), + .o_valid(sigmoid_valid_20), + .i_x(o_add2_20), + .o_y(o_sigmoid_20) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_21 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_21), + .o_valid(sigmoid_valid_21), + .i_x(o_add2_21), + .o_y(o_sigmoid_21) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_22 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_22), + .o_valid(sigmoid_valid_22), + .i_x(o_add2_22), + .o_y(o_sigmoid_22) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_23 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_23), + .o_valid(sigmoid_valid_23), + .i_x(o_add2_23), + .o_y(o_sigmoid_23) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_24 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_24), + .o_valid(sigmoid_valid_24), + .i_x(o_add2_24), + .o_y(o_sigmoid_24) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_25 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_25), + .o_valid(sigmoid_valid_25), + .i_x(o_add2_25), + .o_y(o_sigmoid_25) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_26 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_26), + .o_valid(sigmoid_valid_26), + .i_x(o_add2_26), + .o_y(o_sigmoid_26) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_27 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_27), + .o_valid(sigmoid_valid_27), + .i_x(o_add2_27), + .o_y(o_sigmoid_27) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_28 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_28), + .o_valid(sigmoid_valid_28), + .i_x(o_add2_28), + .o_y(o_sigmoid_28) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_29 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_29), + .o_valid(sigmoid_valid_29), + .i_x(o_add2_29), + .o_y(o_sigmoid_29) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_30 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_30), + .o_valid(sigmoid_valid_30), + .i_x(o_add2_30), + .o_y(o_sigmoid_30) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_31 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_31), + .o_valid(sigmoid_valid_31), + .i_x(o_add2_31), + .o_y(o_sigmoid_31) +); + +assign o_ready = mult_ready; +assign o_valid = sigmoid_valid_0 & i_ready; +assign gate_output_0 = o_sigmoid_0; +assign gate_output_1 = o_sigmoid_1; +assign gate_output_2 = o_sigmoid_2; +assign gate_output_3 = o_sigmoid_3; +assign gate_output_4 = o_sigmoid_4; +assign gate_output_5 = o_sigmoid_5; +assign gate_output_6 = o_sigmoid_6; +assign gate_output_7 = o_sigmoid_7; +assign gate_output_8 = o_sigmoid_8; +assign gate_output_9 = o_sigmoid_9; +assign gate_output_10 = o_sigmoid_10; +assign gate_output_11 = o_sigmoid_11; +assign gate_output_12 = o_sigmoid_12; +assign gate_output_13 = o_sigmoid_13; +assign gate_output_14 = o_sigmoid_14; +assign gate_output_15 = o_sigmoid_15; +assign gate_output_16 = o_sigmoid_16; +assign gate_output_17 = o_sigmoid_17; +assign gate_output_18 = o_sigmoid_18; +assign gate_output_19 = o_sigmoid_19; +assign gate_output_20 = o_sigmoid_20; +assign gate_output_21 = o_sigmoid_21; +assign gate_output_22 = o_sigmoid_22; +assign gate_output_23 = o_sigmoid_23; +assign gate_output_24 = o_sigmoid_24; +assign gate_output_25 = o_sigmoid_25; +assign gate_output_26 = o_sigmoid_26; +assign gate_output_27 = o_sigmoid_27; +assign gate_output_28 = o_sigmoid_28; +assign gate_output_29 = o_sigmoid_29; +assign gate_output_30 = o_sigmoid_30; +assign gate_output_31 = o_sigmoid_31; + +endmodule + +module shift_register_group_18_32_10 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input [17:0] in_16, + output [17:0] out_16, + input [17:0] in_17, + output [17:0] out_17, + input [17:0] in_18, + output [17:0] out_18, + input [17:0] in_19, + output [17:0] out_19, + input [17:0] in_20, + output [17:0] out_20, + input [17:0] in_21, + output [17:0] out_21, + input [17:0] in_22, + output [17:0] out_22, + input [17:0] in_23, + output [17:0] out_23, + input [17:0] in_24, + output [17:0] out_24, + input [17:0] in_25, + output [17:0] out_25, + input [17:0] in_26, + output [17:0] out_26, + input [17:0] in_27, + output [17:0] out_27, + input [17:0] in_28, + output [17:0] out_28, + input [17:0] in_29, + output [17:0] out_29, + input [17:0] in_30, + output [17:0] out_30, + input [17:0] in_31, + output [17:0] out_31, + input reset +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_16 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_16), + .out(out_16) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_17 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_17), + .out(out_17) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_18 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_18), + .out(out_18) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_19 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_19), + .out(out_19) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_20 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_20), + .out(out_20) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_21 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_21), + .out(out_21) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_22 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_22), + .out(out_22) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_23 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_23), + .out(out_23) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_24 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_24), + .out(out_24) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_25 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_25), + .out(out_25) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_26 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_26), + .out(out_26) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_27 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_27), + .out(out_27) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_28 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_28), + .out(out_28) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_29 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_29), + .out(out_29) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_30 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_30), + .out(out_30) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_31 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_31), + .out(out_31) +); + +endmodule + +module shift_register_unit_18_18 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +reg [17:0] shift_registers_1; +reg [17:0] shift_registers_2; +reg [17:0] shift_registers_3; +reg [17:0] shift_registers_4; +reg [17:0] shift_registers_5; +reg [17:0] shift_registers_6; +reg [17:0] shift_registers_7; +reg [17:0] shift_registers_8; +reg [17:0] shift_registers_9; +reg [17:0] shift_registers_10; +reg [17:0] shift_registers_11; +reg [17:0] shift_registers_12; +reg [17:0] shift_registers_13; +reg [17:0] shift_registers_14; +reg [17:0] shift_registers_15; +reg [17:0] shift_registers_16; +reg [17:0] shift_registers_17; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + shift_registers_1 <= 18'd0; + shift_registers_2 <= 18'd0; + shift_registers_3 <= 18'd0; + shift_registers_4 <= 18'd0; + shift_registers_5 <= 18'd0; + shift_registers_6 <= 18'd0; + shift_registers_7 <= 18'd0; + shift_registers_8 <= 18'd0; + shift_registers_9 <= 18'd0; + shift_registers_10 <= 18'd0; + shift_registers_11 <= 18'd0; + shift_registers_12 <= 18'd0; + shift_registers_13 <= 18'd0; + shift_registers_14 <= 18'd0; + shift_registers_15 <= 18'd0; + shift_registers_16 <= 18'd0; + shift_registers_17 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + shift_registers_3 <= shift_registers_2; + shift_registers_4 <= shift_registers_3; + shift_registers_5 <= shift_registers_4; + shift_registers_6 <= shift_registers_5; + shift_registers_7 <= shift_registers_6; + shift_registers_8 <= shift_registers_7; + shift_registers_9 <= shift_registers_8; + shift_registers_10 <= shift_registers_9; + shift_registers_11 <= shift_registers_10; + shift_registers_12 <= shift_registers_11; + shift_registers_13 <= shift_registers_12; + shift_registers_14 <= shift_registers_13; + shift_registers_15 <= shift_registers_14; + shift_registers_16 <= shift_registers_15; + shift_registers_17 <= shift_registers_16; + end +end + +assign out = shift_registers_17; + +endmodule + +module sigmoid_core_18_18_10_32_1 ( + input clk, + input reset, + input i_valid, + input i_ready, + output o_ready, + output o_valid, + input [17:0] i_x, + output [17:0] o_y +); + +reg [12:0] k_list_0; +reg [12:0] b_list_0; +reg [12:0] k_list_1; +reg [12:0] b_list_1; +reg [12:0] k_list_2; +reg [12:0] b_list_2; +reg [12:0] k_list_3; +reg [12:0] b_list_3; +reg [12:0] k_list_4; +reg [12:0] b_list_4; +reg [12:0] k_list_5; +reg [12:0] b_list_5; +reg [12:0] k_list_6; +reg [12:0] b_list_6; +reg [12:0] k_list_7; +reg [12:0] b_list_7; +reg [12:0] k_list_8; +reg [12:0] b_list_8; +reg [12:0] k_list_9; +reg [12:0] b_list_9; +reg [12:0] k_list_10; +reg [12:0] b_list_10; +reg [12:0] k_list_11; +reg [12:0] b_list_11; +reg [12:0] k_list_12; +reg [12:0] b_list_12; +reg [12:0] k_list_13; +reg [12:0] b_list_13; +reg [12:0] k_list_14; +reg [12:0] b_list_14; +reg [12:0] k_list_15; +reg [12:0] b_list_15; +reg [12:0] k_list_16; +reg [12:0] b_list_16; +reg [12:0] k_list_17; +reg [12:0] b_list_17; +reg [12:0] k_list_18; +reg [12:0] b_list_18; +reg [12:0] k_list_19; +reg [12:0] b_list_19; +reg [12:0] k_list_20; +reg [12:0] b_list_20; +reg [12:0] k_list_21; +reg [12:0] b_list_21; +reg [12:0] k_list_22; +reg [12:0] b_list_22; +reg [12:0] k_list_23; +reg [12:0] b_list_23; +reg [12:0] k_list_24; +reg [12:0] b_list_24; +reg [12:0] k_list_25; +reg [12:0] b_list_25; +reg [12:0] k_list_26; +reg [12:0] b_list_26; +reg [12:0] k_list_27; +reg [12:0] b_list_27; +reg [12:0] k_list_28; +reg [12:0] b_list_28; +reg [12:0] k_list_29; +reg [12:0] b_list_29; +reg [12:0] k_list_30; +reg [12:0] b_list_30; +reg [12:0] k_list_31; +reg [12:0] b_list_31; + +always @ (posedge clk) begin + k_list_0 <= 13'b0000111111101; + k_list_1 <= 13'b0000111101110; + k_list_2 <= 13'b0000111010001; + k_list_3 <= 13'b0000110101001; + k_list_4 <= 13'b0000101111011; + k_list_5 <= 13'b0000101001010; + k_list_6 <= 13'b0000100011010; + k_list_7 <= 13'b0000011101100; + k_list_8 <= 13'b0000011000011; + k_list_9 <= 13'b0000010100000; + k_list_10 <= 13'b0000010000001; + k_list_11 <= 13'b0000001101000; + k_list_12 <= 13'b0000001010011; + k_list_13 <= 13'b0000001000010; + k_list_14 <= 13'b0000000110100; + k_list_15 <= 13'b0000000101001; + k_list_16 <= 13'b0000000100000; + k_list_17 <= 13'b0000000011001; + k_list_18 <= 13'b0000000010100; + k_list_19 <= 13'b0000000001111; + k_list_20 <= 13'b0000000001100; + k_list_21 <= 13'b0000000001001; + k_list_22 <= 13'b0000000000111; + k_list_23 <= 13'b0000000000110; + k_list_24 <= 13'b0000000000100; + k_list_25 <= 13'b0000000000011; + k_list_26 <= 13'b0000000000011; + k_list_27 <= 13'b0000000000010; + k_list_28 <= 13'b0000000000010; + k_list_29 <= 13'b0000000000001; + k_list_30 <= 13'b0000000000001; + k_list_31 <= 13'b0000000000001; + b_list_0 <= 13'b0010000000000; + b_list_1 <= 13'b0010000000100; + b_list_2 <= 13'b0010000010010; + b_list_3 <= 13'b0010000110000; + b_list_4 <= 13'b0010001011110; + b_list_5 <= 13'b0010010011011; + b_list_6 <= 13'b0010011100100; + b_list_7 <= 13'b0010100110011; + b_list_8 <= 13'b0010110000101; + b_list_9 <= 13'b0010111010101; + b_list_10 <= 13'b0011000100010; + b_list_11 <= 13'b0011001101000; + b_list_12 <= 13'b0011010100111; + b_list_13 <= 13'b0011011011110; + b_list_14 <= 13'b0011100001110; + b_list_15 <= 13'b0011100111000; + b_list_16 <= 13'b0011101011011; + b_list_17 <= 13'b0011101111000; + b_list_18 <= 13'b0011110010001; + b_list_19 <= 13'b0011110100101; + b_list_20 <= 13'b0011110110110; + b_list_21 <= 13'b0011111000100; + b_list_22 <= 13'b0011111001111; + b_list_23 <= 13'b0011111011001; + b_list_24 <= 13'b0011111100000; + b_list_25 <= 13'b0011111100110; + b_list_26 <= 13'b0011111101011; + b_list_27 <= 13'b0011111101111; + b_list_28 <= 13'b0011111110011; + b_list_29 <= 13'b0011111110101; + b_list_30 <= 13'b0011111110111; + b_list_31 <= 13'b0011111111001; +end +reg [17:0] x; +reg [17:0] y; +reg valid_x, valid_y, enable; +wire [4:0] sel_k_b; + +wire abs_valid, round_valid, mult_valid, compute_valid; +reg [12:0] mac_ay, mac_az; +reg is_x_negative; +wire is_x_negative_hold; +wire [17:0] abs_x; +wire [17:0] x_partial; +reg [31:0] y_compute; +wire [31:0] x_k_plus_b; +wire [31:0] y_rounded; + +assign x_partial = (abs_x >> 8); +assign sel_k_b = x_partial [4:0]; + +reg [12:0] selected_k, selected_b; +always @ (*) begin + if (sel_k_b == 0) begin + selected_k <= k_list_0; + selected_b <= b_list_0; + end else if (sel_k_b == 1) begin + selected_k <= k_list_1; + selected_b <= b_list_1; + end else if (sel_k_b == 2) begin + selected_k <= k_list_2; + selected_b <= b_list_2; + end else if (sel_k_b == 3) begin + selected_k <= k_list_3; + selected_b <= b_list_3; + end else if (sel_k_b == 4) begin + selected_k <= k_list_4; + selected_b <= b_list_4; + end else if (sel_k_b == 5) begin + selected_k <= k_list_5; + selected_b <= b_list_5; + end else if (sel_k_b == 6) begin + selected_k <= k_list_6; + selected_b <= b_list_6; + end else if (sel_k_b == 7) begin + selected_k <= k_list_7; + selected_b <= b_list_7; + end else if (sel_k_b == 8) begin + selected_k <= k_list_8; + selected_b <= b_list_8; + end else if (sel_k_b == 9) begin + selected_k <= k_list_9; + selected_b <= b_list_9; + end else if (sel_k_b == 10) begin + selected_k <= k_list_10; + selected_b <= b_list_10; + end else if (sel_k_b == 11) begin + selected_k <= k_list_11; + selected_b <= b_list_11; + end else if (sel_k_b == 12) begin + selected_k <= k_list_12; + selected_b <= b_list_12; + end else if (sel_k_b == 13) begin + selected_k <= k_list_13; + selected_b <= b_list_13; + end else if (sel_k_b == 14) begin + selected_k <= k_list_14; + selected_b <= b_list_14; + end else if (sel_k_b == 15) begin + selected_k <= k_list_15; + selected_b <= b_list_15; + end else if (sel_k_b == 16) begin + selected_k <= k_list_16; + selected_b <= b_list_16; + end else if (sel_k_b == 17) begin + selected_k <= k_list_17; + selected_b <= b_list_17; + end else if (sel_k_b == 18) begin + selected_k <= k_list_18; + selected_b <= b_list_18; + end else if (sel_k_b == 19) begin + selected_k <= k_list_19; + selected_b <= b_list_19; + end else if (sel_k_b == 20) begin + selected_k <= k_list_20; + selected_b <= b_list_20; + end else if (sel_k_b == 21) begin + selected_k <= k_list_21; + selected_b <= b_list_21; + end else if (sel_k_b == 22) begin + selected_k <= k_list_22; + selected_b <= b_list_22; + end else if (sel_k_b == 23) begin + selected_k <= k_list_23; + selected_b <= b_list_23; + end else if (sel_k_b == 24) begin + selected_k <= k_list_24; + selected_b <= b_list_24; + end else if (sel_k_b == 25) begin + selected_k <= k_list_25; + selected_b <= b_list_25; + end else if (sel_k_b == 26) begin + selected_k <= k_list_26; + selected_b <= b_list_26; + end else if (sel_k_b == 27) begin + selected_k <= k_list_27; + selected_b <= b_list_27; + end else if (sel_k_b == 28) begin + selected_k <= k_list_28; + selected_b <= b_list_28; + end else if (sel_k_b == 29) begin + selected_k <= k_list_29; + selected_b <= b_list_29; + end else if (sel_k_b == 30) begin + selected_k <= k_list_30; + selected_b <= b_list_30; + end else begin + selected_k <= k_list_31; + selected_b <= b_list_31; + end +end +always @ (*) begin + if (abs_x >= 8192) begin + mac_ay <= 0; + mac_az <= 12'd2048; + end else begin + mac_ay <= selected_k; + mac_az <= (selected_b << 10); + end +end +dsp_signed_mac_18_13_23_32 dsp_signed_mac_18_13_23_32_inst_mfthifsaks ( + .clk(clk), + .reset(reset), + .ena(enable), + .ax(abs_x), + .ay(mac_ay), + .az(mac_az), + .i_valid(abs_valid), + .o_valid(compute_valid), + .resulta(x_k_plus_b) +); + +shift_register_unit_1_3 shift_register_unit_1_3_inst_uwdbvloqiu ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(is_x_negative), + .out(is_x_negative_hold) +); + +abs_unit_18 abs_unit_18_inst_ffffulacmi ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(valid_x), + .in(x), + .o_valid(abs_valid), + .out(abs_x) +); + +fp_rounding_unit_1_32_11 fp_rounding_unit_1_32_11_inst_lskukfobjl ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(compute_valid), + .in(y_compute), + .o_valid(round_valid), + .out(y_rounded) +); + +always @ (*) begin + if (is_x_negative_hold) + y_compute = 2048 - x_k_plus_b; + else + y_compute = x_k_plus_b; + enable = i_ready; +end +always @ (posedge clk) begin + if (reset) begin + valid_x <= 1'b0; + valid_y <= 1'b0; + x <= 0; + y <= 0; + end else if (enable) begin + valid_x <= i_valid; + valid_y <= round_valid; + x <= i_x; + if (x[17] == 1'b1) + is_x_negative <= 1'b1; + else + is_x_negative <= 1'b0; + y <= y_rounded[17:0]; + end +end + +assign o_y = y; +assign o_ready = i_ready; +assign o_valid = valid_y & i_ready; + +endmodule + +module dsp_signed_mac_18_13_23_32 ( + input clk, + input reset, + input ena, + input i_valid, + input [17:0] ax, + input [12:0] ay, + input [12:0] az, + output o_valid, + output [31:0] resulta +); + +reg [17:0] reg_ax; +reg [12:0] reg_ay; +reg [12:0] reg_az; +reg [31:0] reg_res; +reg valid_r, valid_rr; +always @ (posedge clk) begin + if (reset) begin + reg_ax <= 0; + reg_ay <= 0; + reg_az <= 0; + reg_res <= 0; + valid_r <= 0; + valid_rr <= 0; + end else begin + reg_ax <= ax; + reg_ay <= ay; + reg_az <= az; + reg_res <= (reg_ax * reg_ay) + reg_az; + valid_r <= ena; + valid_rr <= valid_r; + end +end + +assign resulta = reg_res; +assign o_valid = valid_rr; +endmodule + +module abs_unit_18 ( + input clk, + input reset, + input enable, + input i_valid, + input [17:0] in, + output o_valid, + output [17:0] out +); + +reg [17:0] abs_result; + +always @ (*) begin + if (in[17] == 1'b1) + abs_result = -in; + else + abs_result = in; +end + +reg valid_reg; +reg [17:0] out_reg; +always @ (posedge clk) begin + if (reset) begin + valid_reg <= 1'b0; + out_reg <= 0; + end else if (enable) begin + valid_reg <= i_valid; + out_reg <= abs_result; + end +end +assign out = out_reg; +assign o_valid = valid_reg; +endmodule + +module fp_rounding_unit_1_32_11 ( + input clk, + input reset, + input enable, + input i_valid, + input [31:0] in, + output [31:0] out, + output o_valid +); + +reg [31:0] rounded_result; +reg [31:0] floor; +reg [31:0] ceil; +reg is_ceil; +reg floor_ceil_valid; + +always @ (*) begin + if (is_ceil) begin + rounded_result = ceil; + end else begin + rounded_result = floor; + end +end + +reg valid_reg; +reg [31:0] out_reg; +always @ (posedge clk) begin + if (reset) begin + is_ceil <= 1'b0; + floor_ceil_valid <= 1'b0; + valid_reg <= 1'b0; + floor <= 0; + ceil <= 0; + out_reg <= 0; + end else if (enable) begin + is_ceil <= in[10]; + floor <= in >>> 11; + ceil <= (in >>> 11) + 1; + floor_ceil_valid <= i_valid; + out_reg <= rounded_result; + valid_reg <= floor_ceil_valid; + end +end + +assign o_valid = valid_reg; + +assign out = out_reg; + +endmodule + +module output_activation_18_10_32_1 ( + input clk, + input reset, + input i_ready, + input i_valid, + input [17:0] stage1_result_0, + input [17:0] bias_0, + output [17:0] output_value_0, + input [17:0] stage1_result_1, + input [17:0] bias_1, + output [17:0] output_value_1, + input [17:0] stage1_result_2, + input [17:0] bias_2, + output [17:0] output_value_2, + input [17:0] stage1_result_3, + input [17:0] bias_3, + output [17:0] output_value_3, + input [17:0] stage1_result_4, + input [17:0] bias_4, + output [17:0] output_value_4, + input [17:0] stage1_result_5, + input [17:0] bias_5, + output [17:0] output_value_5, + input [17:0] stage1_result_6, + input [17:0] bias_6, + output [17:0] output_value_6, + input [17:0] stage1_result_7, + input [17:0] bias_7, + output [17:0] output_value_7, + input [17:0] stage1_result_8, + input [17:0] bias_8, + output [17:0] output_value_8, + input [17:0] stage1_result_9, + input [17:0] bias_9, + output [17:0] output_value_9, + input [17:0] stage1_result_10, + input [17:0] bias_10, + output [17:0] output_value_10, + input [17:0] stage1_result_11, + input [17:0] bias_11, + output [17:0] output_value_11, + input [17:0] stage1_result_12, + input [17:0] bias_12, + output [17:0] output_value_12, + input [17:0] stage1_result_13, + input [17:0] bias_13, + output [17:0] output_value_13, + input [17:0] stage1_result_14, + input [17:0] bias_14, + output [17:0] output_value_14, + input [17:0] stage1_result_15, + input [17:0] bias_15, + output [17:0] output_value_15, + input [17:0] stage1_result_16, + input [17:0] bias_16, + output [17:0] output_value_16, + input [17:0] stage1_result_17, + input [17:0] bias_17, + output [17:0] output_value_17, + input [17:0] stage1_result_18, + input [17:0] bias_18, + output [17:0] output_value_18, + input [17:0] stage1_result_19, + input [17:0] bias_19, + output [17:0] output_value_19, + input [17:0] stage1_result_20, + input [17:0] bias_20, + output [17:0] output_value_20, + input [17:0] stage1_result_21, + input [17:0] bias_21, + output [17:0] output_value_21, + input [17:0] stage1_result_22, + input [17:0] bias_22, + output [17:0] output_value_22, + input [17:0] stage1_result_23, + input [17:0] bias_23, + output [17:0] output_value_23, + input [17:0] stage1_result_24, + input [17:0] bias_24, + output [17:0] output_value_24, + input [17:0] stage1_result_25, + input [17:0] bias_25, + output [17:0] output_value_25, + input [17:0] stage1_result_26, + input [17:0] bias_26, + output [17:0] output_value_26, + input [17:0] stage1_result_27, + input [17:0] bias_27, + output [17:0] output_value_27, + input [17:0] stage1_result_28, + input [17:0] bias_28, + output [17:0] output_value_28, + input [17:0] stage1_result_29, + input [17:0] bias_29, + output [17:0] output_value_29, + input [17:0] stage1_result_30, + input [17:0] bias_30, + output [17:0] output_value_30, + input [17:0] stage1_result_31, + input [17:0] bias_31, + output [17:0] output_value_31, + output o_valid, + output o_ready +); + +wire adder1_valid, adder2_valid, adder1_ready, adder2_ready; +wire sigmoid_valid_0, sigmoid_ready_0; +wire [17:0] o_add2_0; +wire [17:0] o_sigmoid_0; +wire sigmoid_valid_1, sigmoid_ready_1; +wire [17:0] o_add2_1; +wire [17:0] o_sigmoid_1; +wire sigmoid_valid_2, sigmoid_ready_2; +wire [17:0] o_add2_2; +wire [17:0] o_sigmoid_2; +wire sigmoid_valid_3, sigmoid_ready_3; +wire [17:0] o_add2_3; +wire [17:0] o_sigmoid_3; +wire sigmoid_valid_4, sigmoid_ready_4; +wire [17:0] o_add2_4; +wire [17:0] o_sigmoid_4; +wire sigmoid_valid_5, sigmoid_ready_5; +wire [17:0] o_add2_5; +wire [17:0] o_sigmoid_5; +wire sigmoid_valid_6, sigmoid_ready_6; +wire [17:0] o_add2_6; +wire [17:0] o_sigmoid_6; +wire sigmoid_valid_7, sigmoid_ready_7; +wire [17:0] o_add2_7; +wire [17:0] o_sigmoid_7; +wire sigmoid_valid_8, sigmoid_ready_8; +wire [17:0] o_add2_8; +wire [17:0] o_sigmoid_8; +wire sigmoid_valid_9, sigmoid_ready_9; +wire [17:0] o_add2_9; +wire [17:0] o_sigmoid_9; +wire sigmoid_valid_10, sigmoid_ready_10; +wire [17:0] o_add2_10; +wire [17:0] o_sigmoid_10; +wire sigmoid_valid_11, sigmoid_ready_11; +wire [17:0] o_add2_11; +wire [17:0] o_sigmoid_11; +wire sigmoid_valid_12, sigmoid_ready_12; +wire [17:0] o_add2_12; +wire [17:0] o_sigmoid_12; +wire sigmoid_valid_13, sigmoid_ready_13; +wire [17:0] o_add2_13; +wire [17:0] o_sigmoid_13; +wire sigmoid_valid_14, sigmoid_ready_14; +wire [17:0] o_add2_14; +wire [17:0] o_sigmoid_14; +wire sigmoid_valid_15, sigmoid_ready_15; +wire [17:0] o_add2_15; +wire [17:0] o_sigmoid_15; +wire sigmoid_valid_16, sigmoid_ready_16; +wire [17:0] o_add2_16; +wire [17:0] o_sigmoid_16; +wire sigmoid_valid_17, sigmoid_ready_17; +wire [17:0] o_add2_17; +wire [17:0] o_sigmoid_17; +wire sigmoid_valid_18, sigmoid_ready_18; +wire [17:0] o_add2_18; +wire [17:0] o_sigmoid_18; +wire sigmoid_valid_19, sigmoid_ready_19; +wire [17:0] o_add2_19; +wire [17:0] o_sigmoid_19; +wire sigmoid_valid_20, sigmoid_ready_20; +wire [17:0] o_add2_20; +wire [17:0] o_sigmoid_20; +wire sigmoid_valid_21, sigmoid_ready_21; +wire [17:0] o_add2_21; +wire [17:0] o_sigmoid_21; +wire sigmoid_valid_22, sigmoid_ready_22; +wire [17:0] o_add2_22; +wire [17:0] o_sigmoid_22; +wire sigmoid_valid_23, sigmoid_ready_23; +wire [17:0] o_add2_23; +wire [17:0] o_sigmoid_23; +wire sigmoid_valid_24, sigmoid_ready_24; +wire [17:0] o_add2_24; +wire [17:0] o_sigmoid_24; +wire sigmoid_valid_25, sigmoid_ready_25; +wire [17:0] o_add2_25; +wire [17:0] o_sigmoid_25; +wire sigmoid_valid_26, sigmoid_ready_26; +wire [17:0] o_add2_26; +wire [17:0] o_sigmoid_26; +wire sigmoid_valid_27, sigmoid_ready_27; +wire [17:0] o_add2_27; +wire [17:0] o_sigmoid_27; +wire sigmoid_valid_28, sigmoid_ready_28; +wire [17:0] o_add2_28; +wire [17:0] o_sigmoid_28; +wire sigmoid_valid_29, sigmoid_ready_29; +wire [17:0] o_add2_29; +wire [17:0] o_sigmoid_29; +wire sigmoid_valid_30, sigmoid_ready_30; +wire [17:0] o_add2_30; +wire [17:0] o_sigmoid_30; +wire sigmoid_valid_31, sigmoid_ready_31; +wire [17:0] o_add2_31; +wire [17:0] o_sigmoid_31; +elementwise_add_core_18_18_32 elementwise_add_core_18_18_32_inst_elfxxneced ( + .clk(clk), + .reset(reset), + .i_valid(i_valid), + .i_ready(sigmoid_ready_0), + .i_A_0(stage1_result_0), + .i_B_0(bias_0), + .o_C_0(o_add2_0), + .i_A_1(stage1_result_1), + .i_B_1(bias_1), + .o_C_1(o_add2_1), + .i_A_2(stage1_result_2), + .i_B_2(bias_2), + .o_C_2(o_add2_2), + .i_A_3(stage1_result_3), + .i_B_3(bias_3), + .o_C_3(o_add2_3), + .i_A_4(stage1_result_4), + .i_B_4(bias_4), + .o_C_4(o_add2_4), + .i_A_5(stage1_result_5), + .i_B_5(bias_5), + .o_C_5(o_add2_5), + .i_A_6(stage1_result_6), + .i_B_6(bias_6), + .o_C_6(o_add2_6), + .i_A_7(stage1_result_7), + .i_B_7(bias_7), + .o_C_7(o_add2_7), + .i_A_8(stage1_result_8), + .i_B_8(bias_8), + .o_C_8(o_add2_8), + .i_A_9(stage1_result_9), + .i_B_9(bias_9), + .o_C_9(o_add2_9), + .i_A_10(stage1_result_10), + .i_B_10(bias_10), + .o_C_10(o_add2_10), + .i_A_11(stage1_result_11), + .i_B_11(bias_11), + .o_C_11(o_add2_11), + .i_A_12(stage1_result_12), + .i_B_12(bias_12), + .o_C_12(o_add2_12), + .i_A_13(stage1_result_13), + .i_B_13(bias_13), + .o_C_13(o_add2_13), + .i_A_14(stage1_result_14), + .i_B_14(bias_14), + .o_C_14(o_add2_14), + .i_A_15(stage1_result_15), + .i_B_15(bias_15), + .o_C_15(o_add2_15), + .i_A_16(stage1_result_16), + .i_B_16(bias_16), + .o_C_16(o_add2_16), + .i_A_17(stage1_result_17), + .i_B_17(bias_17), + .o_C_17(o_add2_17), + .i_A_18(stage1_result_18), + .i_B_18(bias_18), + .o_C_18(o_add2_18), + .i_A_19(stage1_result_19), + .i_B_19(bias_19), + .o_C_19(o_add2_19), + .i_A_20(stage1_result_20), + .i_B_20(bias_20), + .o_C_20(o_add2_20), + .i_A_21(stage1_result_21), + .i_B_21(bias_21), + .o_C_21(o_add2_21), + .i_A_22(stage1_result_22), + .i_B_22(bias_22), + .o_C_22(o_add2_22), + .i_A_23(stage1_result_23), + .i_B_23(bias_23), + .o_C_23(o_add2_23), + .i_A_24(stage1_result_24), + .i_B_24(bias_24), + .o_C_24(o_add2_24), + .i_A_25(stage1_result_25), + .i_B_25(bias_25), + .o_C_25(o_add2_25), + .i_A_26(stage1_result_26), + .i_B_26(bias_26), + .o_C_26(o_add2_26), + .i_A_27(stage1_result_27), + .i_B_27(bias_27), + .o_C_27(o_add2_27), + .i_A_28(stage1_result_28), + .i_B_28(bias_28), + .o_C_28(o_add2_28), + .i_A_29(stage1_result_29), + .i_B_29(bias_29), + .o_C_29(o_add2_29), + .i_A_30(stage1_result_30), + .i_B_30(bias_30), + .o_C_30(o_add2_30), + .i_A_31(stage1_result_31), + .i_B_31(bias_31), + .o_C_31(o_add2_31), + .o_valid(adder2_valid), + .o_ready(adder2_ready) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_0 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_0), + .o_valid(sigmoid_valid_0), + .i_x(o_add2_0), + .o_y(o_sigmoid_0) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_1 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_1), + .o_valid(sigmoid_valid_1), + .i_x(o_add2_1), + .o_y(o_sigmoid_1) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_2 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_2), + .o_valid(sigmoid_valid_2), + .i_x(o_add2_2), + .o_y(o_sigmoid_2) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_3 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_3), + .o_valid(sigmoid_valid_3), + .i_x(o_add2_3), + .o_y(o_sigmoid_3) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_4 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_4), + .o_valid(sigmoid_valid_4), + .i_x(o_add2_4), + .o_y(o_sigmoid_4) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_5 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_5), + .o_valid(sigmoid_valid_5), + .i_x(o_add2_5), + .o_y(o_sigmoid_5) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_6 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_6), + .o_valid(sigmoid_valid_6), + .i_x(o_add2_6), + .o_y(o_sigmoid_6) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_7 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_7), + .o_valid(sigmoid_valid_7), + .i_x(o_add2_7), + .o_y(o_sigmoid_7) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_8 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_8), + .o_valid(sigmoid_valid_8), + .i_x(o_add2_8), + .o_y(o_sigmoid_8) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_9 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_9), + .o_valid(sigmoid_valid_9), + .i_x(o_add2_9), + .o_y(o_sigmoid_9) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_10 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_10), + .o_valid(sigmoid_valid_10), + .i_x(o_add2_10), + .o_y(o_sigmoid_10) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_11 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_11), + .o_valid(sigmoid_valid_11), + .i_x(o_add2_11), + .o_y(o_sigmoid_11) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_12 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_12), + .o_valid(sigmoid_valid_12), + .i_x(o_add2_12), + .o_y(o_sigmoid_12) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_13 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_13), + .o_valid(sigmoid_valid_13), + .i_x(o_add2_13), + .o_y(o_sigmoid_13) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_14 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_14), + .o_valid(sigmoid_valid_14), + .i_x(o_add2_14), + .o_y(o_sigmoid_14) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_15 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_15), + .o_valid(sigmoid_valid_15), + .i_x(o_add2_15), + .o_y(o_sigmoid_15) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_16 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_16), + .o_valid(sigmoid_valid_16), + .i_x(o_add2_16), + .o_y(o_sigmoid_16) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_17 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_17), + .o_valid(sigmoid_valid_17), + .i_x(o_add2_17), + .o_y(o_sigmoid_17) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_18 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_18), + .o_valid(sigmoid_valid_18), + .i_x(o_add2_18), + .o_y(o_sigmoid_18) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_19 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_19), + .o_valid(sigmoid_valid_19), + .i_x(o_add2_19), + .o_y(o_sigmoid_19) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_20 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_20), + .o_valid(sigmoid_valid_20), + .i_x(o_add2_20), + .o_y(o_sigmoid_20) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_21 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_21), + .o_valid(sigmoid_valid_21), + .i_x(o_add2_21), + .o_y(o_sigmoid_21) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_22 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_22), + .o_valid(sigmoid_valid_22), + .i_x(o_add2_22), + .o_y(o_sigmoid_22) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_23 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_23), + .o_valid(sigmoid_valid_23), + .i_x(o_add2_23), + .o_y(o_sigmoid_23) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_24 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_24), + .o_valid(sigmoid_valid_24), + .i_x(o_add2_24), + .o_y(o_sigmoid_24) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_25 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_25), + .o_valid(sigmoid_valid_25), + .i_x(o_add2_25), + .o_y(o_sigmoid_25) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_26 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_26), + .o_valid(sigmoid_valid_26), + .i_x(o_add2_26), + .o_y(o_sigmoid_26) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_27 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_27), + .o_valid(sigmoid_valid_27), + .i_x(o_add2_27), + .o_y(o_sigmoid_27) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_28 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_28), + .o_valid(sigmoid_valid_28), + .i_x(o_add2_28), + .o_y(o_sigmoid_28) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_29 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_29), + .o_valid(sigmoid_valid_29), + .i_x(o_add2_29), + .o_y(o_sigmoid_29) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_30 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_30), + .o_valid(sigmoid_valid_30), + .i_x(o_add2_30), + .o_y(o_sigmoid_30) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_31 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_31), + .o_valid(sigmoid_valid_31), + .i_x(o_add2_31), + .o_y(o_sigmoid_31) +); + +assign o_ready = adder2_ready; +assign o_valid = sigmoid_valid_0 & i_ready; +assign output_value_0 = o_sigmoid_0; +assign output_value_1 = o_sigmoid_1; +assign output_value_2 = o_sigmoid_2; +assign output_value_3 = o_sigmoid_3; +assign output_value_4 = o_sigmoid_4; +assign output_value_5 = o_sigmoid_5; +assign output_value_6 = o_sigmoid_6; +assign output_value_7 = o_sigmoid_7; +assign output_value_8 = o_sigmoid_8; +assign output_value_9 = o_sigmoid_9; +assign output_value_10 = o_sigmoid_10; +assign output_value_11 = o_sigmoid_11; +assign output_value_12 = o_sigmoid_12; +assign output_value_13 = o_sigmoid_13; +assign output_value_14 = o_sigmoid_14; +assign output_value_15 = o_sigmoid_15; +assign output_value_16 = o_sigmoid_16; +assign output_value_17 = o_sigmoid_17; +assign output_value_18 = o_sigmoid_18; +assign output_value_19 = o_sigmoid_19; +assign output_value_20 = o_sigmoid_20; +assign output_value_21 = o_sigmoid_21; +assign output_value_22 = o_sigmoid_22; +assign output_value_23 = o_sigmoid_23; +assign output_value_24 = o_sigmoid_24; +assign output_value_25 = o_sigmoid_25; +assign output_value_26 = o_sigmoid_26; +assign output_value_27 = o_sigmoid_27; +assign output_value_28 = o_sigmoid_28; +assign output_value_29 = o_sigmoid_29; +assign output_value_30 = o_sigmoid_30; +assign output_value_31 = o_sigmoid_31; + +endmodule + +module shift_register_group_18_32_6 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input [17:0] in_16, + output [17:0] out_16, + input [17:0] in_17, + output [17:0] out_17, + input [17:0] in_18, + output [17:0] out_18, + input [17:0] in_19, + output [17:0] out_19, + input [17:0] in_20, + output [17:0] out_20, + input [17:0] in_21, + output [17:0] out_21, + input [17:0] in_22, + output [17:0] out_22, + input [17:0] in_23, + output [17:0] out_23, + input [17:0] in_24, + output [17:0] out_24, + input [17:0] in_25, + output [17:0] out_25, + input [17:0] in_26, + output [17:0] out_26, + input [17:0] in_27, + output [17:0] out_27, + input [17:0] in_28, + output [17:0] out_28, + input [17:0] in_29, + output [17:0] out_29, + input [17:0] in_30, + output [17:0] out_30, + input [17:0] in_31, + output [17:0] out_31, + input reset +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_16 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_16), + .out(out_16) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_17 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_17), + .out(out_17) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_18 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_18), + .out(out_18) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_19 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_19), + .out(out_19) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_20 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_20), + .out(out_20) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_21 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_21), + .out(out_21) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_22 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_22), + .out(out_22) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_23 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_23), + .out(out_23) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_24 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_24), + .out(out_24) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_25 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_25), + .out(out_25) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_26 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_26), + .out(out_26) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_27 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_27), + .out(out_27) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_28 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_28), + .out(out_28) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_29 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_29), + .out(out_29) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_30 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_30), + .out(out_30) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_31 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_31), + .out(out_31) +); + +endmodule + +module shift_register_unit_18_6 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +reg [17:0] shift_registers_1; +reg [17:0] shift_registers_2; +reg [17:0] shift_registers_3; +reg [17:0] shift_registers_4; +reg [17:0] shift_registers_5; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + shift_registers_1 <= 18'd0; + shift_registers_2 <= 18'd0; + shift_registers_3 <= 18'd0; + shift_registers_4 <= 18'd0; + shift_registers_5 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + shift_registers_3 <= shift_registers_2; + shift_registers_4 <= shift_registers_3; + shift_registers_5 <= shift_registers_4; + end +end + +assign out = shift_registers_5; + +endmodule + +module elementwise_mult_core_18_18_10_32_1 ( + input clk, + input reset, + input i_valid, + input i_ready, + input [17:0] i_A_0, + input [17:0] i_B_0, + output [17:0] o_C_0, + input [17:0] i_A_1, + input [17:0] i_B_1, + output [17:0] o_C_1, + input [17:0] i_A_2, + input [17:0] i_B_2, + output [17:0] o_C_2, + input [17:0] i_A_3, + input [17:0] i_B_3, + output [17:0] o_C_3, + input [17:0] i_A_4, + input [17:0] i_B_4, + output [17:0] o_C_4, + input [17:0] i_A_5, + input [17:0] i_B_5, + output [17:0] o_C_5, + input [17:0] i_A_6, + input [17:0] i_B_6, + output [17:0] o_C_6, + input [17:0] i_A_7, + input [17:0] i_B_7, + output [17:0] o_C_7, + input [17:0] i_A_8, + input [17:0] i_B_8, + output [17:0] o_C_8, + input [17:0] i_A_9, + input [17:0] i_B_9, + output [17:0] o_C_9, + input [17:0] i_A_10, + input [17:0] i_B_10, + output [17:0] o_C_10, + input [17:0] i_A_11, + input [17:0] i_B_11, + output [17:0] o_C_11, + input [17:0] i_A_12, + input [17:0] i_B_12, + output [17:0] o_C_12, + input [17:0] i_A_13, + input [17:0] i_B_13, + output [17:0] o_C_13, + input [17:0] i_A_14, + input [17:0] i_B_14, + output [17:0] o_C_14, + input [17:0] i_A_15, + input [17:0] i_B_15, + output [17:0] o_C_15, + input [17:0] i_A_16, + input [17:0] i_B_16, + output [17:0] o_C_16, + input [17:0] i_A_17, + input [17:0] i_B_17, + output [17:0] o_C_17, + input [17:0] i_A_18, + input [17:0] i_B_18, + output [17:0] o_C_18, + input [17:0] i_A_19, + input [17:0] i_B_19, + output [17:0] o_C_19, + input [17:0] i_A_20, + input [17:0] i_B_20, + output [17:0] o_C_20, + input [17:0] i_A_21, + input [17:0] i_B_21, + output [17:0] o_C_21, + input [17:0] i_A_22, + input [17:0] i_B_22, + output [17:0] o_C_22, + input [17:0] i_A_23, + input [17:0] i_B_23, + output [17:0] o_C_23, + input [17:0] i_A_24, + input [17:0] i_B_24, + output [17:0] o_C_24, + input [17:0] i_A_25, + input [17:0] i_B_25, + output [17:0] o_C_25, + input [17:0] i_A_26, + input [17:0] i_B_26, + output [17:0] o_C_26, + input [17:0] i_A_27, + input [17:0] i_B_27, + output [17:0] o_C_27, + input [17:0] i_A_28, + input [17:0] i_B_28, + output [17:0] o_C_28, + input [17:0] i_A_29, + input [17:0] i_B_29, + output [17:0] o_C_29, + input [17:0] i_A_30, + input [17:0] i_B_30, + output [17:0] o_C_30, + input [17:0] i_A_31, + input [17:0] i_B_31, + output [17:0] o_C_31, + output o_valid, + output o_ready +); + +// Store inputs and outputs in registers +reg [17:0] reg_A_0; +reg [17:0] reg_B_0; +wire [17:0] reg_C_0; +reg [17:0] reg_A_1; +reg [17:0] reg_B_1; +wire [17:0] reg_C_1; +reg [17:0] reg_A_2; +reg [17:0] reg_B_2; +wire [17:0] reg_C_2; +reg [17:0] reg_A_3; +reg [17:0] reg_B_3; +wire [17:0] reg_C_3; +reg [17:0] reg_A_4; +reg [17:0] reg_B_4; +wire [17:0] reg_C_4; +reg [17:0] reg_A_5; +reg [17:0] reg_B_5; +wire [17:0] reg_C_5; +reg [17:0] reg_A_6; +reg [17:0] reg_B_6; +wire [17:0] reg_C_6; +reg [17:0] reg_A_7; +reg [17:0] reg_B_7; +wire [17:0] reg_C_7; +reg [17:0] reg_A_8; +reg [17:0] reg_B_8; +wire [17:0] reg_C_8; +reg [17:0] reg_A_9; +reg [17:0] reg_B_9; +wire [17:0] reg_C_9; +reg [17:0] reg_A_10; +reg [17:0] reg_B_10; +wire [17:0] reg_C_10; +reg [17:0] reg_A_11; +reg [17:0] reg_B_11; +wire [17:0] reg_C_11; +reg [17:0] reg_A_12; +reg [17:0] reg_B_12; +wire [17:0] reg_C_12; +reg [17:0] reg_A_13; +reg [17:0] reg_B_13; +wire [17:0] reg_C_13; +reg [17:0] reg_A_14; +reg [17:0] reg_B_14; +wire [17:0] reg_C_14; +reg [17:0] reg_A_15; +reg [17:0] reg_B_15; +wire [17:0] reg_C_15; +reg [17:0] reg_A_16; +reg [17:0] reg_B_16; +wire [17:0] reg_C_16; +reg [17:0] reg_A_17; +reg [17:0] reg_B_17; +wire [17:0] reg_C_17; +reg [17:0] reg_A_18; +reg [17:0] reg_B_18; +wire [17:0] reg_C_18; +reg [17:0] reg_A_19; +reg [17:0] reg_B_19; +wire [17:0] reg_C_19; +reg [17:0] reg_A_20; +reg [17:0] reg_B_20; +wire [17:0] reg_C_20; +reg [17:0] reg_A_21; +reg [17:0] reg_B_21; +wire [17:0] reg_C_21; +reg [17:0] reg_A_22; +reg [17:0] reg_B_22; +wire [17:0] reg_C_22; +reg [17:0] reg_A_23; +reg [17:0] reg_B_23; +wire [17:0] reg_C_23; +reg [17:0] reg_A_24; +reg [17:0] reg_B_24; +wire [17:0] reg_C_24; +reg [17:0] reg_A_25; +reg [17:0] reg_B_25; +wire [17:0] reg_C_25; +reg [17:0] reg_A_26; +reg [17:0] reg_B_26; +wire [17:0] reg_C_26; +reg [17:0] reg_A_27; +reg [17:0] reg_B_27; +wire [17:0] reg_C_27; +reg [17:0] reg_A_28; +reg [17:0] reg_B_28; +wire [17:0] reg_C_28; +reg [17:0] reg_A_29; +reg [17:0] reg_B_29; +wire [17:0] reg_C_29; +reg [17:0] reg_A_30; +reg [17:0] reg_B_30; +wire [17:0] reg_C_30; +reg [17:0] reg_A_31; +reg [17:0] reg_B_31; +wire [17:0] reg_C_31; + +reg valid_A_B; +wire valid_C; +wire enable; +assign enable = i_ready; + +wire mult_valid_0; +wire round_valid_0; +wire [36:0] mult_C_0; +wire [36:0] rounded_C_0; +wire mult_valid_1; +wire round_valid_1; +wire [36:0] mult_C_1; +wire [36:0] rounded_C_1; +wire mult_valid_2; +wire round_valid_2; +wire [36:0] mult_C_2; +wire [36:0] rounded_C_2; +wire mult_valid_3; +wire round_valid_3; +wire [36:0] mult_C_3; +wire [36:0] rounded_C_3; +wire mult_valid_4; +wire round_valid_4; +wire [36:0] mult_C_4; +wire [36:0] rounded_C_4; +wire mult_valid_5; +wire round_valid_5; +wire [36:0] mult_C_5; +wire [36:0] rounded_C_5; +wire mult_valid_6; +wire round_valid_6; +wire [36:0] mult_C_6; +wire [36:0] rounded_C_6; +wire mult_valid_7; +wire round_valid_7; +wire [36:0] mult_C_7; +wire [36:0] rounded_C_7; +wire mult_valid_8; +wire round_valid_8; +wire [36:0] mult_C_8; +wire [36:0] rounded_C_8; +wire mult_valid_9; +wire round_valid_9; +wire [36:0] mult_C_9; +wire [36:0] rounded_C_9; +wire mult_valid_10; +wire round_valid_10; +wire [36:0] mult_C_10; +wire [36:0] rounded_C_10; +wire mult_valid_11; +wire round_valid_11; +wire [36:0] mult_C_11; +wire [36:0] rounded_C_11; +wire mult_valid_12; +wire round_valid_12; +wire [36:0] mult_C_12; +wire [36:0] rounded_C_12; +wire mult_valid_13; +wire round_valid_13; +wire [36:0] mult_C_13; +wire [36:0] rounded_C_13; +wire mult_valid_14; +wire round_valid_14; +wire [36:0] mult_C_14; +wire [36:0] rounded_C_14; +wire mult_valid_15; +wire round_valid_15; +wire [36:0] mult_C_15; +wire [36:0] rounded_C_15; +wire mult_valid_16; +wire round_valid_16; +wire [36:0] mult_C_16; +wire [36:0] rounded_C_16; +wire mult_valid_17; +wire round_valid_17; +wire [36:0] mult_C_17; +wire [36:0] rounded_C_17; +wire mult_valid_18; +wire round_valid_18; +wire [36:0] mult_C_18; +wire [36:0] rounded_C_18; +wire mult_valid_19; +wire round_valid_19; +wire [36:0] mult_C_19; +wire [36:0] rounded_C_19; +wire mult_valid_20; +wire round_valid_20; +wire [36:0] mult_C_20; +wire [36:0] rounded_C_20; +wire mult_valid_21; +wire round_valid_21; +wire [36:0] mult_C_21; +wire [36:0] rounded_C_21; +wire mult_valid_22; +wire round_valid_22; +wire [36:0] mult_C_22; +wire [36:0] rounded_C_22; +wire mult_valid_23; +wire round_valid_23; +wire [36:0] mult_C_23; +wire [36:0] rounded_C_23; +wire mult_valid_24; +wire round_valid_24; +wire [36:0] mult_C_24; +wire [36:0] rounded_C_24; +wire mult_valid_25; +wire round_valid_25; +wire [36:0] mult_C_25; +wire [36:0] rounded_C_25; +wire mult_valid_26; +wire round_valid_26; +wire [36:0] mult_C_26; +wire [36:0] rounded_C_26; +wire mult_valid_27; +wire round_valid_27; +wire [36:0] mult_C_27; +wire [36:0] rounded_C_27; +wire mult_valid_28; +wire round_valid_28; +wire [36:0] mult_C_28; +wire [36:0] rounded_C_28; +wire mult_valid_29; +wire round_valid_29; +wire [36:0] mult_C_29; +wire [36:0] rounded_C_29; +wire mult_valid_30; +wire round_valid_30; +wire [36:0] mult_C_30; +wire [36:0] rounded_C_30; +wire mult_valid_31; +wire round_valid_31; +wire [36:0] mult_C_31; +wire [36:0] rounded_C_31; + +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst0 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_0), + .ay(reg_B_0), + .bx(reg_A_1), + .by(reg_B_1), + .o_valid(mult_valid_0), + .resulta(mult_C_0), + .resultb(mult_C_1) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst2 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_2), + .ay(reg_B_2), + .bx(reg_A_3), + .by(reg_B_3), + .o_valid(mult_valid_2), + .resulta(mult_C_2), + .resultb(mult_C_3) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst4 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_4), + .ay(reg_B_4), + .bx(reg_A_5), + .by(reg_B_5), + .o_valid(mult_valid_4), + .resulta(mult_C_4), + .resultb(mult_C_5) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst6 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_6), + .ay(reg_B_6), + .bx(reg_A_7), + .by(reg_B_7), + .o_valid(mult_valid_6), + .resulta(mult_C_6), + .resultb(mult_C_7) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst8 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_8), + .ay(reg_B_8), + .bx(reg_A_9), + .by(reg_B_9), + .o_valid(mult_valid_8), + .resulta(mult_C_8), + .resultb(mult_C_9) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst10 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_10), + .ay(reg_B_10), + .bx(reg_A_11), + .by(reg_B_11), + .o_valid(mult_valid_10), + .resulta(mult_C_10), + .resultb(mult_C_11) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst12 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_12), + .ay(reg_B_12), + .bx(reg_A_13), + .by(reg_B_13), + .o_valid(mult_valid_12), + .resulta(mult_C_12), + .resultb(mult_C_13) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst14 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_14), + .ay(reg_B_14), + .bx(reg_A_15), + .by(reg_B_15), + .o_valid(mult_valid_14), + .resulta(mult_C_14), + .resultb(mult_C_15) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst16 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_16), + .ay(reg_B_16), + .bx(reg_A_17), + .by(reg_B_17), + .o_valid(mult_valid_16), + .resulta(mult_C_16), + .resultb(mult_C_17) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst18 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_18), + .ay(reg_B_18), + .bx(reg_A_19), + .by(reg_B_19), + .o_valid(mult_valid_18), + .resulta(mult_C_18), + .resultb(mult_C_19) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst20 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_20), + .ay(reg_B_20), + .bx(reg_A_21), + .by(reg_B_21), + .o_valid(mult_valid_20), + .resulta(mult_C_20), + .resultb(mult_C_21) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst22 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_22), + .ay(reg_B_22), + .bx(reg_A_23), + .by(reg_B_23), + .o_valid(mult_valid_22), + .resulta(mult_C_22), + .resultb(mult_C_23) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst24 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_24), + .ay(reg_B_24), + .bx(reg_A_25), + .by(reg_B_25), + .o_valid(mult_valid_24), + .resulta(mult_C_24), + .resultb(mult_C_25) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst26 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_26), + .ay(reg_B_26), + .bx(reg_A_27), + .by(reg_B_27), + .o_valid(mult_valid_26), + .resulta(mult_C_26), + .resultb(mult_C_27) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst28 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_28), + .ay(reg_B_28), + .bx(reg_A_29), + .by(reg_B_29), + .o_valid(mult_valid_28), + .resulta(mult_C_28), + .resultb(mult_C_29) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst30 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_30), + .ay(reg_B_30), + .bx(reg_A_31), + .by(reg_B_31), + .o_valid(mult_valid_30), + .resulta(mult_C_30), + .resultb(mult_C_31) +); +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_0), + .in(mult_C_0), + .o_valid(round_valid_0), + .out(rounded_C_0) +); +assign reg_C_0 = rounded_C_0[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_1), + .in(mult_C_1), + .o_valid(round_valid_1), + .out(rounded_C_1) +); +assign reg_C_1 = rounded_C_1[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_2), + .in(mult_C_2), + .o_valid(round_valid_2), + .out(rounded_C_2) +); +assign reg_C_2 = rounded_C_2[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_3), + .in(mult_C_3), + .o_valid(round_valid_3), + .out(rounded_C_3) +); +assign reg_C_3 = rounded_C_3[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_4), + .in(mult_C_4), + .o_valid(round_valid_4), + .out(rounded_C_4) +); +assign reg_C_4 = rounded_C_4[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_5), + .in(mult_C_5), + .o_valid(round_valid_5), + .out(rounded_C_5) +); +assign reg_C_5 = rounded_C_5[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_6), + .in(mult_C_6), + .o_valid(round_valid_6), + .out(rounded_C_6) +); +assign reg_C_6 = rounded_C_6[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_7), + .in(mult_C_7), + .o_valid(round_valid_7), + .out(rounded_C_7) +); +assign reg_C_7 = rounded_C_7[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_8), + .in(mult_C_8), + .o_valid(round_valid_8), + .out(rounded_C_8) +); +assign reg_C_8 = rounded_C_8[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_9), + .in(mult_C_9), + .o_valid(round_valid_9), + .out(rounded_C_9) +); +assign reg_C_9 = rounded_C_9[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_10), + .in(mult_C_10), + .o_valid(round_valid_10), + .out(rounded_C_10) +); +assign reg_C_10 = rounded_C_10[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_11), + .in(mult_C_11), + .o_valid(round_valid_11), + .out(rounded_C_11) +); +assign reg_C_11 = rounded_C_11[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_12), + .in(mult_C_12), + .o_valid(round_valid_12), + .out(rounded_C_12) +); +assign reg_C_12 = rounded_C_12[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_13), + .in(mult_C_13), + .o_valid(round_valid_13), + .out(rounded_C_13) +); +assign reg_C_13 = rounded_C_13[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_14), + .in(mult_C_14), + .o_valid(round_valid_14), + .out(rounded_C_14) +); +assign reg_C_14 = rounded_C_14[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_15), + .in(mult_C_15), + .o_valid(round_valid_15), + .out(rounded_C_15) +); +assign reg_C_15 = rounded_C_15[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst16 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_16), + .in(mult_C_16), + .o_valid(round_valid_16), + .out(rounded_C_16) +); +assign reg_C_16 = rounded_C_16[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst17 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_17), + .in(mult_C_17), + .o_valid(round_valid_17), + .out(rounded_C_17) +); +assign reg_C_17 = rounded_C_17[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst18 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_18), + .in(mult_C_18), + .o_valid(round_valid_18), + .out(rounded_C_18) +); +assign reg_C_18 = rounded_C_18[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst19 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_19), + .in(mult_C_19), + .o_valid(round_valid_19), + .out(rounded_C_19) +); +assign reg_C_19 = rounded_C_19[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst20 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_20), + .in(mult_C_20), + .o_valid(round_valid_20), + .out(rounded_C_20) +); +assign reg_C_20 = rounded_C_20[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst21 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_21), + .in(mult_C_21), + .o_valid(round_valid_21), + .out(rounded_C_21) +); +assign reg_C_21 = rounded_C_21[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst22 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_22), + .in(mult_C_22), + .o_valid(round_valid_22), + .out(rounded_C_22) +); +assign reg_C_22 = rounded_C_22[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst23 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_23), + .in(mult_C_23), + .o_valid(round_valid_23), + .out(rounded_C_23) +); +assign reg_C_23 = rounded_C_23[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst24 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_24), + .in(mult_C_24), + .o_valid(round_valid_24), + .out(rounded_C_24) +); +assign reg_C_24 = rounded_C_24[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst25 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_25), + .in(mult_C_25), + .o_valid(round_valid_25), + .out(rounded_C_25) +); +assign reg_C_25 = rounded_C_25[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst26 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_26), + .in(mult_C_26), + .o_valid(round_valid_26), + .out(rounded_C_26) +); +assign reg_C_26 = rounded_C_26[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst27 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_27), + .in(mult_C_27), + .o_valid(round_valid_27), + .out(rounded_C_27) +); +assign reg_C_27 = rounded_C_27[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst28 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_28), + .in(mult_C_28), + .o_valid(round_valid_28), + .out(rounded_C_28) +); +assign reg_C_28 = rounded_C_28[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst29 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_29), + .in(mult_C_29), + .o_valid(round_valid_29), + .out(rounded_C_29) +); +assign reg_C_29 = rounded_C_29[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst30 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_30), + .in(mult_C_30), + .o_valid(round_valid_30), + .out(rounded_C_30) +); +assign reg_C_30 = rounded_C_30[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst31 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_31), + .in(mult_C_31), + .o_valid(round_valid_31), + .out(rounded_C_31) +); +assign reg_C_31 = rounded_C_31[17:0]; +always @ (posedge clk) begin + if (reset) begin + valid_A_B <= 1'b0; + reg_A_0 <= 0; + reg_B_0 <= 0; + reg_A_1 <= 0; + reg_B_1 <= 0; + reg_A_2 <= 0; + reg_B_2 <= 0; + reg_A_3 <= 0; + reg_B_3 <= 0; + reg_A_4 <= 0; + reg_B_4 <= 0; + reg_A_5 <= 0; + reg_B_5 <= 0; + reg_A_6 <= 0; + reg_B_6 <= 0; + reg_A_7 <= 0; + reg_B_7 <= 0; + reg_A_8 <= 0; + reg_B_8 <= 0; + reg_A_9 <= 0; + reg_B_9 <= 0; + reg_A_10 <= 0; + reg_B_10 <= 0; + reg_A_11 <= 0; + reg_B_11 <= 0; + reg_A_12 <= 0; + reg_B_12 <= 0; + reg_A_13 <= 0; + reg_B_13 <= 0; + reg_A_14 <= 0; + reg_B_14 <= 0; + reg_A_15 <= 0; + reg_B_15 <= 0; + reg_A_16 <= 0; + reg_B_16 <= 0; + reg_A_17 <= 0; + reg_B_17 <= 0; + reg_A_18 <= 0; + reg_B_18 <= 0; + reg_A_19 <= 0; + reg_B_19 <= 0; + reg_A_20 <= 0; + reg_B_20 <= 0; + reg_A_21 <= 0; + reg_B_21 <= 0; + reg_A_22 <= 0; + reg_B_22 <= 0; + reg_A_23 <= 0; + reg_B_23 <= 0; + reg_A_24 <= 0; + reg_B_24 <= 0; + reg_A_25 <= 0; + reg_B_25 <= 0; + reg_A_26 <= 0; + reg_B_26 <= 0; + reg_A_27 <= 0; + reg_B_27 <= 0; + reg_A_28 <= 0; + reg_B_28 <= 0; + reg_A_29 <= 0; + reg_B_29 <= 0; + reg_A_30 <= 0; + reg_B_30 <= 0; + reg_A_31 <= 0; + reg_B_31 <= 0; + end else if (enable) begin + reg_A_0 <= i_A_0; + reg_B_0 <= i_B_0; + reg_A_1 <= i_A_1; + reg_B_1 <= i_B_1; + reg_A_2 <= i_A_2; + reg_B_2 <= i_B_2; + reg_A_3 <= i_A_3; + reg_B_3 <= i_B_3; + reg_A_4 <= i_A_4; + reg_B_4 <= i_B_4; + reg_A_5 <= i_A_5; + reg_B_5 <= i_B_5; + reg_A_6 <= i_A_6; + reg_B_6 <= i_B_6; + reg_A_7 <= i_A_7; + reg_B_7 <= i_B_7; + reg_A_8 <= i_A_8; + reg_B_8 <= i_B_8; + reg_A_9 <= i_A_9; + reg_B_9 <= i_B_9; + reg_A_10 <= i_A_10; + reg_B_10 <= i_B_10; + reg_A_11 <= i_A_11; + reg_B_11 <= i_B_11; + reg_A_12 <= i_A_12; + reg_B_12 <= i_B_12; + reg_A_13 <= i_A_13; + reg_B_13 <= i_B_13; + reg_A_14 <= i_A_14; + reg_B_14 <= i_B_14; + reg_A_15 <= i_A_15; + reg_B_15 <= i_B_15; + reg_A_16 <= i_A_16; + reg_B_16 <= i_B_16; + reg_A_17 <= i_A_17; + reg_B_17 <= i_B_17; + reg_A_18 <= i_A_18; + reg_B_18 <= i_B_18; + reg_A_19 <= i_A_19; + reg_B_19 <= i_B_19; + reg_A_20 <= i_A_20; + reg_B_20 <= i_B_20; + reg_A_21 <= i_A_21; + reg_B_21 <= i_B_21; + reg_A_22 <= i_A_22; + reg_B_22 <= i_B_22; + reg_A_23 <= i_A_23; + reg_B_23 <= i_B_23; + reg_A_24 <= i_A_24; + reg_B_24 <= i_B_24; + reg_A_25 <= i_A_25; + reg_B_25 <= i_B_25; + reg_A_26 <= i_A_26; + reg_B_26 <= i_B_26; + reg_A_27 <= i_A_27; + reg_B_27 <= i_B_27; + reg_A_28 <= i_A_28; + reg_B_28 <= i_B_28; + reg_A_29 <= i_A_29; + reg_B_29 <= i_B_29; + reg_A_30 <= i_A_30; + reg_B_30 <= i_B_30; + reg_A_31 <= i_A_31; + reg_B_31 <= i_B_31; + valid_A_B <= i_valid; + end +end + +assign o_C_0 = reg_C_0; +assign o_C_1 = reg_C_1; +assign o_C_2 = reg_C_2; +assign o_C_3 = reg_C_3; +assign o_C_4 = reg_C_4; +assign o_C_5 = reg_C_5; +assign o_C_6 = reg_C_6; +assign o_C_7 = reg_C_7; +assign o_C_8 = reg_C_8; +assign o_C_9 = reg_C_9; +assign o_C_10 = reg_C_10; +assign o_C_11 = reg_C_11; +assign o_C_12 = reg_C_12; +assign o_C_13 = reg_C_13; +assign o_C_14 = reg_C_14; +assign o_C_15 = reg_C_15; +assign o_C_16 = reg_C_16; +assign o_C_17 = reg_C_17; +assign o_C_18 = reg_C_18; +assign o_C_19 = reg_C_19; +assign o_C_20 = reg_C_20; +assign o_C_21 = reg_C_21; +assign o_C_22 = reg_C_22; +assign o_C_23 = reg_C_23; +assign o_C_24 = reg_C_24; +assign o_C_25 = reg_C_25; +assign o_C_26 = reg_C_26; +assign o_C_27 = reg_C_27; +assign o_C_28 = reg_C_28; +assign o_C_29 = reg_C_29; +assign o_C_30 = reg_C_30; +assign o_C_31 = reg_C_31; +assign valid_C = round_valid_0; +assign o_ready = i_ready; +assign o_valid = valid_C & i_ready; + +endmodule + +module shift_register_group_18_32_18 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input [17:0] in_16, + output [17:0] out_16, + input [17:0] in_17, + output [17:0] out_17, + input [17:0] in_18, + output [17:0] out_18, + input [17:0] in_19, + output [17:0] out_19, + input [17:0] in_20, + output [17:0] out_20, + input [17:0] in_21, + output [17:0] out_21, + input [17:0] in_22, + output [17:0] out_22, + input [17:0] in_23, + output [17:0] out_23, + input [17:0] in_24, + output [17:0] out_24, + input [17:0] in_25, + output [17:0] out_25, + input [17:0] in_26, + output [17:0] out_26, + input [17:0] in_27, + output [17:0] out_27, + input [17:0] in_28, + output [17:0] out_28, + input [17:0] in_29, + output [17:0] out_29, + input [17:0] in_30, + output [17:0] out_30, + input [17:0] in_31, + output [17:0] out_31, + input reset +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_16 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_16), + .out(out_16) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_17 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_17), + .out(out_17) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_18 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_18), + .out(out_18) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_19 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_19), + .out(out_19) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_20 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_20), + .out(out_20) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_21 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_21), + .out(out_21) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_22 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_22), + .out(out_22) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_23 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_23), + .out(out_23) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_24 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_24), + .out(out_24) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_25 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_25), + .out(out_25) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_26 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_26), + .out(out_26) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_27 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_27), + .out(out_27) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_28 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_28), + .out(out_28) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_29 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_29), + .out(out_29) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_30 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_30), + .out(out_30) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_31 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_31), + .out(out_31) +); + +endmodule + +module elementwise_add_core_18_18_32 ( + input clk, + input reset, + input i_valid, + input i_ready, + input [17:0] i_A_0, + input [17:0] i_B_0, + output [17:0] o_C_0, + input [17:0] i_A_1, + input [17:0] i_B_1, + output [17:0] o_C_1, + input [17:0] i_A_2, + input [17:0] i_B_2, + output [17:0] o_C_2, + input [17:0] i_A_3, + input [17:0] i_B_3, + output [17:0] o_C_3, + input [17:0] i_A_4, + input [17:0] i_B_4, + output [17:0] o_C_4, + input [17:0] i_A_5, + input [17:0] i_B_5, + output [17:0] o_C_5, + input [17:0] i_A_6, + input [17:0] i_B_6, + output [17:0] o_C_6, + input [17:0] i_A_7, + input [17:0] i_B_7, + output [17:0] o_C_7, + input [17:0] i_A_8, + input [17:0] i_B_8, + output [17:0] o_C_8, + input [17:0] i_A_9, + input [17:0] i_B_9, + output [17:0] o_C_9, + input [17:0] i_A_10, + input [17:0] i_B_10, + output [17:0] o_C_10, + input [17:0] i_A_11, + input [17:0] i_B_11, + output [17:0] o_C_11, + input [17:0] i_A_12, + input [17:0] i_B_12, + output [17:0] o_C_12, + input [17:0] i_A_13, + input [17:0] i_B_13, + output [17:0] o_C_13, + input [17:0] i_A_14, + input [17:0] i_B_14, + output [17:0] o_C_14, + input [17:0] i_A_15, + input [17:0] i_B_15, + output [17:0] o_C_15, + input [17:0] i_A_16, + input [17:0] i_B_16, + output [17:0] o_C_16, + input [17:0] i_A_17, + input [17:0] i_B_17, + output [17:0] o_C_17, + input [17:0] i_A_18, + input [17:0] i_B_18, + output [17:0] o_C_18, + input [17:0] i_A_19, + input [17:0] i_B_19, + output [17:0] o_C_19, + input [17:0] i_A_20, + input [17:0] i_B_20, + output [17:0] o_C_20, + input [17:0] i_A_21, + input [17:0] i_B_21, + output [17:0] o_C_21, + input [17:0] i_A_22, + input [17:0] i_B_22, + output [17:0] o_C_22, + input [17:0] i_A_23, + input [17:0] i_B_23, + output [17:0] o_C_23, + input [17:0] i_A_24, + input [17:0] i_B_24, + output [17:0] o_C_24, + input [17:0] i_A_25, + input [17:0] i_B_25, + output [17:0] o_C_25, + input [17:0] i_A_26, + input [17:0] i_B_26, + output [17:0] o_C_26, + input [17:0] i_A_27, + input [17:0] i_B_27, + output [17:0] o_C_27, + input [17:0] i_A_28, + input [17:0] i_B_28, + output [17:0] o_C_28, + input [17:0] i_A_29, + input [17:0] i_B_29, + output [17:0] o_C_29, + input [17:0] i_A_30, + input [17:0] i_B_30, + output [17:0] o_C_30, + input [17:0] i_A_31, + input [17:0] i_B_31, + output [17:0] o_C_31, + output o_valid, + output o_ready +); + +reg [17:0] reg_A_0; +reg [17:0] reg_B_0; +reg [17:0] reg_C_0; +reg [17:0] reg_A_1; +reg [17:0] reg_B_1; +reg [17:0] reg_C_1; +reg [17:0] reg_A_2; +reg [17:0] reg_B_2; +reg [17:0] reg_C_2; +reg [17:0] reg_A_3; +reg [17:0] reg_B_3; +reg [17:0] reg_C_3; +reg [17:0] reg_A_4; +reg [17:0] reg_B_4; +reg [17:0] reg_C_4; +reg [17:0] reg_A_5; +reg [17:0] reg_B_5; +reg [17:0] reg_C_5; +reg [17:0] reg_A_6; +reg [17:0] reg_B_6; +reg [17:0] reg_C_6; +reg [17:0] reg_A_7; +reg [17:0] reg_B_7; +reg [17:0] reg_C_7; +reg [17:0] reg_A_8; +reg [17:0] reg_B_8; +reg [17:0] reg_C_8; +reg [17:0] reg_A_9; +reg [17:0] reg_B_9; +reg [17:0] reg_C_9; +reg [17:0] reg_A_10; +reg [17:0] reg_B_10; +reg [17:0] reg_C_10; +reg [17:0] reg_A_11; +reg [17:0] reg_B_11; +reg [17:0] reg_C_11; +reg [17:0] reg_A_12; +reg [17:0] reg_B_12; +reg [17:0] reg_C_12; +reg [17:0] reg_A_13; +reg [17:0] reg_B_13; +reg [17:0] reg_C_13; +reg [17:0] reg_A_14; +reg [17:0] reg_B_14; +reg [17:0] reg_C_14; +reg [17:0] reg_A_15; +reg [17:0] reg_B_15; +reg [17:0] reg_C_15; +reg [17:0] reg_A_16; +reg [17:0] reg_B_16; +reg [17:0] reg_C_16; +reg [17:0] reg_A_17; +reg [17:0] reg_B_17; +reg [17:0] reg_C_17; +reg [17:0] reg_A_18; +reg [17:0] reg_B_18; +reg [17:0] reg_C_18; +reg [17:0] reg_A_19; +reg [17:0] reg_B_19; +reg [17:0] reg_C_19; +reg [17:0] reg_A_20; +reg [17:0] reg_B_20; +reg [17:0] reg_C_20; +reg [17:0] reg_A_21; +reg [17:0] reg_B_21; +reg [17:0] reg_C_21; +reg [17:0] reg_A_22; +reg [17:0] reg_B_22; +reg [17:0] reg_C_22; +reg [17:0] reg_A_23; +reg [17:0] reg_B_23; +reg [17:0] reg_C_23; +reg [17:0] reg_A_24; +reg [17:0] reg_B_24; +reg [17:0] reg_C_24; +reg [17:0] reg_A_25; +reg [17:0] reg_B_25; +reg [17:0] reg_C_25; +reg [17:0] reg_A_26; +reg [17:0] reg_B_26; +reg [17:0] reg_C_26; +reg [17:0] reg_A_27; +reg [17:0] reg_B_27; +reg [17:0] reg_C_27; +reg [17:0] reg_A_28; +reg [17:0] reg_B_28; +reg [17:0] reg_C_28; +reg [17:0] reg_A_29; +reg [17:0] reg_B_29; +reg [17:0] reg_C_29; +reg [17:0] reg_A_30; +reg [17:0] reg_B_30; +reg [17:0] reg_C_30; +reg [17:0] reg_A_31; +reg [17:0] reg_B_31; +reg [17:0] reg_C_31; + +reg valid_A_B, valid_C; +wire enable; +assign enable = i_ready; + +always @ (posedge clk) begin + if (reset) begin + valid_A_B <= 1'b0; + valid_C <= 1'b0; + reg_A_0 <= 0; + reg_B_0 <= 0; + reg_C_0 <= 0; + reg_A_1 <= 0; + reg_B_1 <= 0; + reg_C_1 <= 0; + reg_A_2 <= 0; + reg_B_2 <= 0; + reg_C_2 <= 0; + reg_A_3 <= 0; + reg_B_3 <= 0; + reg_C_3 <= 0; + reg_A_4 <= 0; + reg_B_4 <= 0; + reg_C_4 <= 0; + reg_A_5 <= 0; + reg_B_5 <= 0; + reg_C_5 <= 0; + reg_A_6 <= 0; + reg_B_6 <= 0; + reg_C_6 <= 0; + reg_A_7 <= 0; + reg_B_7 <= 0; + reg_C_7 <= 0; + reg_A_8 <= 0; + reg_B_8 <= 0; + reg_C_8 <= 0; + reg_A_9 <= 0; + reg_B_9 <= 0; + reg_C_9 <= 0; + reg_A_10 <= 0; + reg_B_10 <= 0; + reg_C_10 <= 0; + reg_A_11 <= 0; + reg_B_11 <= 0; + reg_C_11 <= 0; + reg_A_12 <= 0; + reg_B_12 <= 0; + reg_C_12 <= 0; + reg_A_13 <= 0; + reg_B_13 <= 0; + reg_C_13 <= 0; + reg_A_14 <= 0; + reg_B_14 <= 0; + reg_C_14 <= 0; + reg_A_15 <= 0; + reg_B_15 <= 0; + reg_C_15 <= 0; + reg_A_16 <= 0; + reg_B_16 <= 0; + reg_C_16 <= 0; + reg_A_17 <= 0; + reg_B_17 <= 0; + reg_C_17 <= 0; + reg_A_18 <= 0; + reg_B_18 <= 0; + reg_C_18 <= 0; + reg_A_19 <= 0; + reg_B_19 <= 0; + reg_C_19 <= 0; + reg_A_20 <= 0; + reg_B_20 <= 0; + reg_C_20 <= 0; + reg_A_21 <= 0; + reg_B_21 <= 0; + reg_C_21 <= 0; + reg_A_22 <= 0; + reg_B_22 <= 0; + reg_C_22 <= 0; + reg_A_23 <= 0; + reg_B_23 <= 0; + reg_C_23 <= 0; + reg_A_24 <= 0; + reg_B_24 <= 0; + reg_C_24 <= 0; + reg_A_25 <= 0; + reg_B_25 <= 0; + reg_C_25 <= 0; + reg_A_26 <= 0; + reg_B_26 <= 0; + reg_C_26 <= 0; + reg_A_27 <= 0; + reg_B_27 <= 0; + reg_C_27 <= 0; + reg_A_28 <= 0; + reg_B_28 <= 0; + reg_C_28 <= 0; + reg_A_29 <= 0; + reg_B_29 <= 0; + reg_C_29 <= 0; + reg_A_30 <= 0; + reg_B_30 <= 0; + reg_C_30 <= 0; + reg_A_31 <= 0; + reg_B_31 <= 0; + reg_C_31 <= 0; + end else if (enable) begin + reg_A_0 <= i_A_0; + reg_B_0 <= i_B_0; + reg_C_0 <= reg_A_0 + reg_B_0; + reg_A_1 <= i_A_1; + reg_B_1 <= i_B_1; + reg_C_1 <= reg_A_1 + reg_B_1; + reg_A_2 <= i_A_2; + reg_B_2 <= i_B_2; + reg_C_2 <= reg_A_2 + reg_B_2; + reg_A_3 <= i_A_3; + reg_B_3 <= i_B_3; + reg_C_3 <= reg_A_3 + reg_B_3; + reg_A_4 <= i_A_4; + reg_B_4 <= i_B_4; + reg_C_4 <= reg_A_4 + reg_B_4; + reg_A_5 <= i_A_5; + reg_B_5 <= i_B_5; + reg_C_5 <= reg_A_5 + reg_B_5; + reg_A_6 <= i_A_6; + reg_B_6 <= i_B_6; + reg_C_6 <= reg_A_6 + reg_B_6; + reg_A_7 <= i_A_7; + reg_B_7 <= i_B_7; + reg_C_7 <= reg_A_7 + reg_B_7; + reg_A_8 <= i_A_8; + reg_B_8 <= i_B_8; + reg_C_8 <= reg_A_8 + reg_B_8; + reg_A_9 <= i_A_9; + reg_B_9 <= i_B_9; + reg_C_9 <= reg_A_9 + reg_B_9; + reg_A_10 <= i_A_10; + reg_B_10 <= i_B_10; + reg_C_10 <= reg_A_10 + reg_B_10; + reg_A_11 <= i_A_11; + reg_B_11 <= i_B_11; + reg_C_11 <= reg_A_11 + reg_B_11; + reg_A_12 <= i_A_12; + reg_B_12 <= i_B_12; + reg_C_12 <= reg_A_12 + reg_B_12; + reg_A_13 <= i_A_13; + reg_B_13 <= i_B_13; + reg_C_13 <= reg_A_13 + reg_B_13; + reg_A_14 <= i_A_14; + reg_B_14 <= i_B_14; + reg_C_14 <= reg_A_14 + reg_B_14; + reg_A_15 <= i_A_15; + reg_B_15 <= i_B_15; + reg_C_15 <= reg_A_15 + reg_B_15; + reg_A_16 <= i_A_16; + reg_B_16 <= i_B_16; + reg_C_16 <= reg_A_16 + reg_B_16; + reg_A_17 <= i_A_17; + reg_B_17 <= i_B_17; + reg_C_17 <= reg_A_17 + reg_B_17; + reg_A_18 <= i_A_18; + reg_B_18 <= i_B_18; + reg_C_18 <= reg_A_18 + reg_B_18; + reg_A_19 <= i_A_19; + reg_B_19 <= i_B_19; + reg_C_19 <= reg_A_19 + reg_B_19; + reg_A_20 <= i_A_20; + reg_B_20 <= i_B_20; + reg_C_20 <= reg_A_20 + reg_B_20; + reg_A_21 <= i_A_21; + reg_B_21 <= i_B_21; + reg_C_21 <= reg_A_21 + reg_B_21; + reg_A_22 <= i_A_22; + reg_B_22 <= i_B_22; + reg_C_22 <= reg_A_22 + reg_B_22; + reg_A_23 <= i_A_23; + reg_B_23 <= i_B_23; + reg_C_23 <= reg_A_23 + reg_B_23; + reg_A_24 <= i_A_24; + reg_B_24 <= i_B_24; + reg_C_24 <= reg_A_24 + reg_B_24; + reg_A_25 <= i_A_25; + reg_B_25 <= i_B_25; + reg_C_25 <= reg_A_25 + reg_B_25; + reg_A_26 <= i_A_26; + reg_B_26 <= i_B_26; + reg_C_26 <= reg_A_26 + reg_B_26; + reg_A_27 <= i_A_27; + reg_B_27 <= i_B_27; + reg_C_27 <= reg_A_27 + reg_B_27; + reg_A_28 <= i_A_28; + reg_B_28 <= i_B_28; + reg_C_28 <= reg_A_28 + reg_B_28; + reg_A_29 <= i_A_29; + reg_B_29 <= i_B_29; + reg_C_29 <= reg_A_29 + reg_B_29; + reg_A_30 <= i_A_30; + reg_B_30 <= i_B_30; + reg_C_30 <= reg_A_30 + reg_B_30; + reg_A_31 <= i_A_31; + reg_B_31 <= i_B_31; + reg_C_31 <= reg_A_31 + reg_B_31; + valid_A_B <= i_valid; + valid_C <= valid_A_B; + end +end + +assign o_C_0 = reg_C_0; +assign o_C_1 = reg_C_1; +assign o_C_2 = reg_C_2; +assign o_C_3 = reg_C_3; +assign o_C_4 = reg_C_4; +assign o_C_5 = reg_C_5; +assign o_C_6 = reg_C_6; +assign o_C_7 = reg_C_7; +assign o_C_8 = reg_C_8; +assign o_C_9 = reg_C_9; +assign o_C_10 = reg_C_10; +assign o_C_11 = reg_C_11; +assign o_C_12 = reg_C_12; +assign o_C_13 = reg_C_13; +assign o_C_14 = reg_C_14; +assign o_C_15 = reg_C_15; +assign o_C_16 = reg_C_16; +assign o_C_17 = reg_C_17; +assign o_C_18 = reg_C_18; +assign o_C_19 = reg_C_19; +assign o_C_20 = reg_C_20; +assign o_C_21 = reg_C_21; +assign o_C_22 = reg_C_22; +assign o_C_23 = reg_C_23; +assign o_C_24 = reg_C_24; +assign o_C_25 = reg_C_25; +assign o_C_26 = reg_C_26; +assign o_C_27 = reg_C_27; +assign o_C_28 = reg_C_28; +assign o_C_29 = reg_C_29; +assign o_C_30 = reg_C_30; +assign o_C_31 = reg_C_31; +assign o_ready = i_ready; +assign o_valid = valid_C & i_ready; + +endmodule + +module shift_register_group_18_32_14 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input [17:0] in_16, + output [17:0] out_16, + input [17:0] in_17, + output [17:0] out_17, + input [17:0] in_18, + output [17:0] out_18, + input [17:0] in_19, + output [17:0] out_19, + input [17:0] in_20, + output [17:0] out_20, + input [17:0] in_21, + output [17:0] out_21, + input [17:0] in_22, + output [17:0] out_22, + input [17:0] in_23, + output [17:0] out_23, + input [17:0] in_24, + output [17:0] out_24, + input [17:0] in_25, + output [17:0] out_25, + input [17:0] in_26, + output [17:0] out_26, + input [17:0] in_27, + output [17:0] out_27, + input [17:0] in_28, + output [17:0] out_28, + input [17:0] in_29, + output [17:0] out_29, + input [17:0] in_30, + output [17:0] out_30, + input [17:0] in_31, + output [17:0] out_31, + input reset +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_16 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_16), + .out(out_16) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_17 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_17), + .out(out_17) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_18 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_18), + .out(out_18) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_19 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_19), + .out(out_19) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_20 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_20), + .out(out_20) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_21 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_21), + .out(out_21) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_22 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_22), + .out(out_22) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_23 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_23), + .out(out_23) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_24 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_24), + .out(out_24) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_25 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_25), + .out(out_25) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_26 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_26), + .out(out_26) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_27 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_27), + .out(out_27) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_28 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_28), + .out(out_28) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_29 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_29), + .out(out_29) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_30 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_30), + .out(out_30) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_31 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_31), + .out(out_31) +); + +endmodule + +module shift_register_unit_18_14 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +reg [17:0] shift_registers_1; +reg [17:0] shift_registers_2; +reg [17:0] shift_registers_3; +reg [17:0] shift_registers_4; +reg [17:0] shift_registers_5; +reg [17:0] shift_registers_6; +reg [17:0] shift_registers_7; +reg [17:0] shift_registers_8; +reg [17:0] shift_registers_9; +reg [17:0] shift_registers_10; +reg [17:0] shift_registers_11; +reg [17:0] shift_registers_12; +reg [17:0] shift_registers_13; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + shift_registers_1 <= 18'd0; + shift_registers_2 <= 18'd0; + shift_registers_3 <= 18'd0; + shift_registers_4 <= 18'd0; + shift_registers_5 <= 18'd0; + shift_registers_6 <= 18'd0; + shift_registers_7 <= 18'd0; + shift_registers_8 <= 18'd0; + shift_registers_9 <= 18'd0; + shift_registers_10 <= 18'd0; + shift_registers_11 <= 18'd0; + shift_registers_12 <= 18'd0; + shift_registers_13 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + shift_registers_3 <= shift_registers_2; + shift_registers_4 <= shift_registers_3; + shift_registers_5 <= shift_registers_4; + shift_registers_6 <= shift_registers_5; + shift_registers_7 <= shift_registers_6; + shift_registers_8 <= shift_registers_7; + shift_registers_9 <= shift_registers_8; + shift_registers_10 <= shift_registers_9; + shift_registers_11 <= shift_registers_10; + shift_registers_12 <= shift_registers_11; + shift_registers_13 <= shift_registers_12; + end +end + +assign out = shift_registers_13; + +endmodule + +module tanh_core_18_18_10_32_1 ( + input clk, + input reset, + input i_valid, + input i_ready, + output o_ready, + output o_valid, + input [17:0] i_x, + output [17:0] o_y +); + +reg [12:0] k_list_0; +reg [12:0] b_list_0; +reg [12:0] k_list_1; +reg [12:0] b_list_1; +reg [12:0] k_list_2; +reg [12:0] b_list_2; +reg [12:0] k_list_3; +reg [12:0] b_list_3; +reg [12:0] k_list_4; +reg [12:0] b_list_4; +reg [12:0] k_list_5; +reg [12:0] b_list_5; +reg [12:0] k_list_6; +reg [12:0] b_list_6; +reg [12:0] k_list_7; +reg [12:0] b_list_7; +reg [12:0] k_list_8; +reg [12:0] b_list_8; +reg [12:0] k_list_9; +reg [12:0] b_list_9; +reg [12:0] k_list_10; +reg [12:0] b_list_10; +reg [12:0] k_list_11; +reg [12:0] b_list_11; +reg [12:0] k_list_12; +reg [12:0] b_list_12; +reg [12:0] k_list_13; +reg [12:0] b_list_13; +reg [12:0] k_list_14; +reg [12:0] b_list_14; +reg [12:0] k_list_15; +reg [12:0] b_list_15; +reg [12:0] k_list_16; +reg [12:0] b_list_16; +reg [12:0] k_list_17; +reg [12:0] b_list_17; +reg [12:0] k_list_18; +reg [12:0] b_list_18; +reg [12:0] k_list_19; +reg [12:0] b_list_19; +reg [12:0] k_list_20; +reg [12:0] b_list_20; +reg [12:0] k_list_21; +reg [12:0] b_list_21; +reg [12:0] k_list_22; +reg [12:0] b_list_22; +reg [12:0] k_list_23; +reg [12:0] b_list_23; +reg [12:0] k_list_24; +reg [12:0] b_list_24; +reg [12:0] k_list_25; +reg [12:0] b_list_25; +reg [12:0] k_list_26; +reg [12:0] b_list_26; +reg [12:0] k_list_27; +reg [12:0] b_list_27; +reg [12:0] k_list_28; +reg [12:0] b_list_28; +reg [12:0] k_list_29; +reg [12:0] b_list_29; +reg [12:0] k_list_30; +reg [12:0] b_list_30; +reg [12:0] k_list_31; +reg [12:0] b_list_31; + +always @ (posedge clk) begin + k_list_0 <= 13'b0011111110101; + k_list_1 <= 13'b0011110110111; + k_list_2 <= 13'b0011101000011; + k_list_3 <= 13'b0011010100100; + k_list_4 <= 13'b0010111101011; + k_list_5 <= 13'b0010100101000; + k_list_6 <= 13'b0010001100111; + k_list_7 <= 13'b0001110110001; + k_list_8 <= 13'b0001100001110; + k_list_9 <= 13'b0001001111111; + k_list_10 <= 13'b0001000000101; + k_list_11 <= 13'b0000110011111; + k_list_12 <= 13'b0000101001011; + k_list_13 <= 13'b0000100000111; + k_list_14 <= 13'b0000011010000; + k_list_15 <= 13'b0000010100100; + k_list_16 <= 13'b0000010000001; + k_list_17 <= 13'b0000001100101; + k_list_18 <= 13'b0000001001111; + k_list_19 <= 13'b0000000111110; + k_list_20 <= 13'b0000000110000; + k_list_21 <= 13'b0000000100110; + k_list_22 <= 13'b0000000011101; + k_list_23 <= 13'b0000000010111; + k_list_24 <= 13'b0000000010010; + k_list_25 <= 13'b0000000001110; + k_list_26 <= 13'b0000000001011; + k_list_27 <= 13'b0000000001000; + k_list_28 <= 13'b0000000000111; + k_list_29 <= 13'b0000000000101; + k_list_30 <= 13'b0000000000100; + k_list_31 <= 13'b0000000000011; + b_list_0 <= 13'b0000000000000; + b_list_1 <= 13'b0000000001000; + b_list_2 <= 13'b0000000100101; + b_list_3 <= 13'b0000001100000; + b_list_4 <= 13'b0000010111101; + b_list_5 <= 13'b0000100110111; + b_list_6 <= 13'b0000111001000; + b_list_7 <= 13'b0001001100111; + b_list_8 <= 13'b0001100001010; + b_list_9 <= 13'b0001110101011; + b_list_10 <= 13'b0010001000011; + b_list_11 <= 13'b0010011001111; + b_list_12 <= 13'b0010101001101; + b_list_13 <= 13'b0010110111100; + b_list_14 <= 13'b0011000011101; + b_list_15 <= 13'b0011001101111; + b_list_16 <= 13'b0011010110101; + b_list_17 <= 13'b0011011110000; + b_list_18 <= 13'b0011100100001; + b_list_19 <= 13'b0011101001010; + b_list_20 <= 13'b0011101101100; + b_list_21 <= 13'b0011110001000; + b_list_22 <= 13'b0011110011110; + b_list_23 <= 13'b0011110110001; + b_list_24 <= 13'b0011111000000; + b_list_25 <= 13'b0011111001101; + b_list_26 <= 13'b0011111010111; + b_list_27 <= 13'b0011111011111; + b_list_28 <= 13'b0011111100101; + b_list_29 <= 13'b0011111101010; + b_list_30 <= 13'b0011111101111; + b_list_31 <= 13'b0011111110010; +end +reg [17:0] x; +reg [17:0] y; +reg valid_x, valid_y, enable; +wire [4:0] sel_k_b; + +wire abs_valid, round_valid, mult_valid, compute_valid; +reg [12:0] mac_ay, mac_az; +reg is_x_negative; +wire is_x_negative_hold; +wire [17:0] abs_x; +wire [17:0] x_partial; +reg [31:0] y_compute; +wire [31:0] x_k_plus_b; +wire [31:0] y_rounded; + +assign x_partial = (abs_x >> 7); +assign sel_k_b = x_partial [4:0]; + +reg [12:0] selected_k, selected_b; +always @ (*) begin + if (sel_k_b == 0) begin + selected_k <= k_list_0; + selected_b <= b_list_0; + end else if (sel_k_b == 1) begin + selected_k <= k_list_1; + selected_b <= b_list_1; + end else if (sel_k_b == 2) begin + selected_k <= k_list_2; + selected_b <= b_list_2; + end else if (sel_k_b == 3) begin + selected_k <= k_list_3; + selected_b <= b_list_3; + end else if (sel_k_b == 4) begin + selected_k <= k_list_4; + selected_b <= b_list_4; + end else if (sel_k_b == 5) begin + selected_k <= k_list_5; + selected_b <= b_list_5; + end else if (sel_k_b == 6) begin + selected_k <= k_list_6; + selected_b <= b_list_6; + end else if (sel_k_b == 7) begin + selected_k <= k_list_7; + selected_b <= b_list_7; + end else if (sel_k_b == 8) begin + selected_k <= k_list_8; + selected_b <= b_list_8; + end else if (sel_k_b == 9) begin + selected_k <= k_list_9; + selected_b <= b_list_9; + end else if (sel_k_b == 10) begin + selected_k <= k_list_10; + selected_b <= b_list_10; + end else if (sel_k_b == 11) begin + selected_k <= k_list_11; + selected_b <= b_list_11; + end else if (sel_k_b == 12) begin + selected_k <= k_list_12; + selected_b <= b_list_12; + end else if (sel_k_b == 13) begin + selected_k <= k_list_13; + selected_b <= b_list_13; + end else if (sel_k_b == 14) begin + selected_k <= k_list_14; + selected_b <= b_list_14; + end else if (sel_k_b == 15) begin + selected_k <= k_list_15; + selected_b <= b_list_15; + end else if (sel_k_b == 16) begin + selected_k <= k_list_16; + selected_b <= b_list_16; + end else if (sel_k_b == 17) begin + selected_k <= k_list_17; + selected_b <= b_list_17; + end else if (sel_k_b == 18) begin + selected_k <= k_list_18; + selected_b <= b_list_18; + end else if (sel_k_b == 19) begin + selected_k <= k_list_19; + selected_b <= b_list_19; + end else if (sel_k_b == 20) begin + selected_k <= k_list_20; + selected_b <= b_list_20; + end else if (sel_k_b == 21) begin + selected_k <= k_list_21; + selected_b <= b_list_21; + end else if (sel_k_b == 22) begin + selected_k <= k_list_22; + selected_b <= b_list_22; + end else if (sel_k_b == 23) begin + selected_k <= k_list_23; + selected_b <= b_list_23; + end else if (sel_k_b == 24) begin + selected_k <= k_list_24; + selected_b <= b_list_24; + end else if (sel_k_b == 25) begin + selected_k <= k_list_25; + selected_b <= b_list_25; + end else if (sel_k_b == 26) begin + selected_k <= k_list_26; + selected_b <= b_list_26; + end else if (sel_k_b == 27) begin + selected_k <= k_list_27; + selected_b <= b_list_27; + end else if (sel_k_b == 28) begin + selected_k <= k_list_28; + selected_b <= b_list_28; + end else if (sel_k_b == 29) begin + selected_k <= k_list_29; + selected_b <= b_list_29; + end else if (sel_k_b == 30) begin + selected_k <= k_list_30; + selected_b <= b_list_30; + end else begin + selected_k <= k_list_31; + selected_b <= b_list_31; + end +end +always @ (*) begin + if (abs_x >= 4096) begin + mac_ay <= 0; + mac_az <= 12'd2048; + end else begin + mac_ay <= selected_k; + mac_az <= (selected_b << 10); + end +end +dsp_signed_mac_18_13_23_32 dsp_signed_mac_18_13_23_32_inst_uzabrtzkbz ( + .clk(clk), + .reset(reset), + .ena(enable), + .ax(abs_x), + .ay(mac_ay), + .az(mac_az), + .i_valid(abs_valid), + .o_valid(compute_valid), + .resulta(x_k_plus_b) +); + +shift_register_unit_1_3 shift_register_unit_1_3_inst_umtqzeurkj ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(is_x_negative), + .out(is_x_negative_hold) +); + +abs_unit_18 abs_unit_18_inst_tvodynuarl ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(valid_x), + .in(x), + .o_valid(abs_valid), + .out(abs_x) +); + +fp_rounding_unit_1_32_11 fp_rounding_unit_1_32_11_inst_oobxasnzfa ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(compute_valid), + .in(y_compute), + .o_valid(round_valid), + .out(y_rounded) +); + +always @ (*) begin + if (is_x_negative_hold) + y_compute = 2048 - x_k_plus_b; + else + y_compute = x_k_plus_b; + enable = i_ready; +end +always @ (posedge clk) begin + if (reset) begin + valid_x <= 1'b0; + valid_y <= 1'b0; + x <= 0; + y <= 0; + end else if (enable) begin + valid_x <= i_valid; + valid_y <= round_valid; + x <= i_x; + if (x[17] == 1'b1) + is_x_negative <= 1'b1; + else + is_x_negative <= 1'b0; + y <= y_rounded[17:0]; + end +end + +assign o_y = y; +assign o_ready = i_ready; +assign o_valid = valid_y & i_ready; + +endmodule + +module pipelined_input_18_2_16 ( + input clk, + input reset, + input enable, + input load_input, + input [17:0] i_data_0_0, + input [17:0] i_data_0_1, + input [17:0] i_data_0_2, + input [17:0] i_data_0_3, + input [17:0] i_data_0_4, + input [17:0] i_data_0_5, + input [17:0] i_data_0_6, + input [17:0] i_data_0_7, + input [17:0] i_data_0_8, + input [17:0] i_data_0_9, + input [17:0] i_data_0_10, + input [17:0] i_data_0_11, + input [17:0] i_data_0_12, + input [17:0] i_data_0_13, + input [17:0] i_data_0_14, + input [17:0] i_data_0_15, + input [17:0] i_data_1_0, + input [17:0] i_data_1_1, + input [17:0] i_data_1_2, + input [17:0] i_data_1_3, + input [17:0] i_data_1_4, + input [17:0] i_data_1_5, + input [17:0] i_data_1_6, + input [17:0] i_data_1_7, + input [17:0] i_data_1_8, + input [17:0] i_data_1_9, + input [17:0] i_data_1_10, + input [17:0] i_data_1_11, + input [17:0] i_data_1_12, + input [17:0] i_data_1_13, + input [17:0] i_data_1_14, + input [17:0] i_data_1_15, + output [17:0] o_data_0, + output [17:0] o_data_1, + output [17:0] o_data_2, + output [17:0] o_data_3, + output [17:0] o_data_4, + output [17:0] o_data_5, + output [17:0] o_data_6, + output [17:0] o_data_7, + output [17:0] o_data_8, + output [17:0] o_data_9, + output [17:0] o_data_10, + output [17:0] o_data_11, + output [17:0] o_data_12, + output [17:0] o_data_13, + output [17:0] o_data_14, + output [17:0] o_data_15, + output o_valid +); + +reg [17:0] pipeline_0_0; +reg [17:0] pipeline_0_1; +reg [17:0] pipeline_0_2; +reg [17:0] pipeline_0_3; +reg [17:0] pipeline_0_4; +reg [17:0] pipeline_0_5; +reg [17:0] pipeline_0_6; +reg [17:0] pipeline_0_7; +reg [17:0] pipeline_0_8; +reg [17:0] pipeline_0_9; +reg [17:0] pipeline_0_10; +reg [17:0] pipeline_0_11; +reg [17:0] pipeline_0_12; +reg [17:0] pipeline_0_13; +reg [17:0] pipeline_0_14; +reg [17:0] pipeline_0_15; +reg [17:0] pipeline_1_0; +reg [17:0] pipeline_1_1; +reg [17:0] pipeline_1_2; +reg [17:0] pipeline_1_3; +reg [17:0] pipeline_1_4; +reg [17:0] pipeline_1_5; +reg [17:0] pipeline_1_6; +reg [17:0] pipeline_1_7; +reg [17:0] pipeline_1_8; +reg [17:0] pipeline_1_9; +reg [17:0] pipeline_1_10; +reg [17:0] pipeline_1_11; +reg [17:0] pipeline_1_12; +reg [17:0] pipeline_1_13; +reg [17:0] pipeline_1_14; +reg [17:0] pipeline_1_15; +reg [17:0] pipeline_2_0; +reg [17:0] pipeline_2_1; +reg [17:0] pipeline_2_2; +reg [17:0] pipeline_2_3; +reg [17:0] pipeline_2_4; +reg [17:0] pipeline_2_5; +reg [17:0] pipeline_2_6; +reg [17:0] pipeline_2_7; +reg [17:0] pipeline_2_8; +reg [17:0] pipeline_2_9; +reg [17:0] pipeline_2_10; +reg [17:0] pipeline_2_11; +reg [17:0] pipeline_2_12; +reg [17:0] pipeline_2_13; +reg [17:0] pipeline_2_14; +reg [17:0] pipeline_2_15; +reg pipeline_valid_0; +reg pipeline_valid_1; +reg pipeline_valid_2; + +always @ (posedge clk) begin + if (reset) begin + pipeline_0_0 <= 0; + pipeline_0_1 <= 0; + pipeline_0_2 <= 0; + pipeline_0_3 <= 0; + pipeline_0_4 <= 0; + pipeline_0_5 <= 0; + pipeline_0_6 <= 0; + pipeline_0_7 <= 0; + pipeline_0_8 <= 0; + pipeline_0_9 <= 0; + pipeline_0_10 <= 0; + pipeline_0_11 <= 0; + pipeline_0_12 <= 0; + pipeline_0_13 <= 0; + pipeline_0_14 <= 0; + pipeline_0_15 <= 0; + pipeline_1_0 <= 0; + pipeline_1_1 <= 0; + pipeline_1_2 <= 0; + pipeline_1_3 <= 0; + pipeline_1_4 <= 0; + pipeline_1_5 <= 0; + pipeline_1_6 <= 0; + pipeline_1_7 <= 0; + pipeline_1_8 <= 0; + pipeline_1_9 <= 0; + pipeline_1_10 <= 0; + pipeline_1_11 <= 0; + pipeline_1_12 <= 0; + pipeline_1_13 <= 0; + pipeline_1_14 <= 0; + pipeline_1_15 <= 0; + pipeline_2_0 <= 0; + pipeline_2_1 <= 0; + pipeline_2_2 <= 0; + pipeline_2_3 <= 0; + pipeline_2_4 <= 0; + pipeline_2_5 <= 0; + pipeline_2_6 <= 0; + pipeline_2_7 <= 0; + pipeline_2_8 <= 0; + pipeline_2_9 <= 0; + pipeline_2_10 <= 0; + pipeline_2_11 <= 0; + pipeline_2_12 <= 0; + pipeline_2_13 <= 0; + pipeline_2_14 <= 0; + pipeline_2_15 <= 0; + pipeline_valid_0 <= 0; + pipeline_valid_1 <= 0; + pipeline_valid_2 <= 0; + end else if (enable) begin + if (load_input) begin + pipeline_0_0 <= i_data_0_0; + pipeline_0_1 <= i_data_0_1; + pipeline_0_2 <= i_data_0_2; + pipeline_0_3 <= i_data_0_3; + pipeline_0_4 <= i_data_0_4; + pipeline_0_5 <= i_data_0_5; + pipeline_0_6 <= i_data_0_6; + pipeline_0_7 <= i_data_0_7; + pipeline_0_8 <= i_data_0_8; + pipeline_0_9 <= i_data_0_9; + pipeline_0_10 <= i_data_0_10; + pipeline_0_11 <= i_data_0_11; + pipeline_0_12 <= i_data_0_12; + pipeline_0_13 <= i_data_0_13; + pipeline_0_14 <= i_data_0_14; + pipeline_0_15 <= i_data_0_15; + pipeline_valid_0 <= 1'b1; + pipeline_2_0 <= i_data_1_0; + pipeline_2_1 <= i_data_1_1; + pipeline_2_2 <= i_data_1_2; + pipeline_2_3 <= i_data_1_3; + pipeline_2_4 <= i_data_1_4; + pipeline_2_5 <= i_data_1_5; + pipeline_2_6 <= i_data_1_6; + pipeline_2_7 <= i_data_1_7; + pipeline_2_8 <= i_data_1_8; + pipeline_2_9 <= i_data_1_9; + pipeline_2_10 <= i_data_1_10; + pipeline_2_11 <= i_data_1_11; + pipeline_2_12 <= i_data_1_12; + pipeline_2_13 <= i_data_1_13; + pipeline_2_14 <= i_data_1_14; + pipeline_2_15 <= i_data_1_15; + pipeline_valid_2 <= 1'b1; + pipeline_1_0 <= i_data_1_0; + pipeline_1_1 <= i_data_1_1; + pipeline_1_2 <= i_data_1_2; + pipeline_1_3 <= i_data_1_3; + pipeline_1_4 <= i_data_1_4; + pipeline_1_5 <= i_data_1_5; + pipeline_1_6 <= i_data_1_6; + pipeline_1_7 <= i_data_1_7; + pipeline_1_8 <= i_data_1_8; + pipeline_1_9 <= i_data_1_9; + pipeline_1_10 <= i_data_1_10; + pipeline_1_11 <= i_data_1_11; + pipeline_1_12 <= i_data_1_12; + pipeline_1_13 <= i_data_1_13; + pipeline_1_14 <= i_data_1_14; + pipeline_1_15 <= i_data_1_15; + pipeline_valid_1 <= 1'b0; + end else begin + pipeline_2_0 <= 0; + pipeline_2_1 <= 0; + pipeline_2_2 <= 0; + pipeline_2_3 <= 0; + pipeline_2_4 <= 0; + pipeline_2_5 <= 0; + pipeline_2_6 <= 0; + pipeline_2_7 <= 0; + pipeline_2_8 <= 0; + pipeline_2_9 <= 0; + pipeline_2_10 <= 0; + pipeline_2_11 <= 0; + pipeline_2_12 <= 0; + pipeline_2_13 <= 0; + pipeline_2_14 <= 0; + pipeline_2_15 <= 0; + pipeline_valid_2 <= 1'b0; + pipeline_0_0 <= pipeline_1_0; + pipeline_0_1 <= pipeline_1_1; + pipeline_0_2 <= pipeline_1_2; + pipeline_0_3 <= pipeline_1_3; + pipeline_0_4 <= pipeline_1_4; + pipeline_0_5 <= pipeline_1_5; + pipeline_0_6 <= pipeline_1_6; + pipeline_0_7 <= pipeline_1_7; + pipeline_0_8 <= pipeline_1_8; + pipeline_0_9 <= pipeline_1_9; + pipeline_0_10 <= pipeline_1_10; + pipeline_0_11 <= pipeline_1_11; + pipeline_0_12 <= pipeline_1_12; + pipeline_0_13 <= pipeline_1_13; + pipeline_0_14 <= pipeline_1_14; + pipeline_0_15 <= pipeline_1_15; + pipeline_valid_0 <= pipeline_valid_1; + pipeline_1_0 <= pipeline_2_0; + pipeline_1_1 <= pipeline_2_1; + pipeline_1_2 <= pipeline_2_2; + pipeline_1_3 <= pipeline_2_3; + pipeline_1_4 <= pipeline_2_4; + pipeline_1_5 <= pipeline_2_5; + pipeline_1_6 <= pipeline_2_6; + pipeline_1_7 <= pipeline_2_7; + pipeline_1_8 <= pipeline_2_8; + pipeline_1_9 <= pipeline_2_9; + pipeline_1_10 <= pipeline_2_10; + pipeline_1_11 <= pipeline_2_11; + pipeline_1_12 <= pipeline_2_12; + pipeline_1_13 <= pipeline_2_13; + pipeline_1_14 <= pipeline_2_14; + pipeline_1_15 <= pipeline_2_15; + pipeline_valid_1 <= pipeline_valid_2; + end + end +end + +assign o_data_0 = pipeline_0_0; +assign o_data_1 = pipeline_0_1; +assign o_data_2 = pipeline_0_2; +assign o_data_3 = pipeline_0_3; +assign o_data_4 = pipeline_0_4; +assign o_data_5 = pipeline_0_5; +assign o_data_6 = pipeline_0_6; +assign o_data_7 = pipeline_0_7; +assign o_data_8 = pipeline_0_8; +assign o_data_9 = pipeline_0_9; +assign o_data_10 = pipeline_0_10; +assign o_data_11 = pipeline_0_11; +assign o_data_12 = pipeline_0_12; +assign o_data_13 = pipeline_0_13; +assign o_data_14 = pipeline_0_14; +assign o_data_15 = pipeline_0_15; +assign o_valid = pipeline_valid_0; + +endmodule + +module stage2_Ct_buffer_18_2_16_64 ( + input clk, + input reset, + input wen, + input ren, + input [17:0] i_Ct_0, + input [17:0] i_Ct_1, + input [17:0] i_Ct_2, + input [17:0] i_Ct_3, + input [17:0] i_Ct_4, + input [17:0] i_Ct_5, + input [17:0] i_Ct_6, + input [17:0] i_Ct_7, + input [17:0] i_Ct_8, + input [17:0] i_Ct_9, + input [17:0] i_Ct_10, + input [17:0] i_Ct_11, + input [17:0] i_Ct_12, + input [17:0] i_Ct_13, + input [17:0] i_Ct_14, + input [17:0] i_Ct_15, + output [17:0] o_Ct_0, + output [17:0] o_Ct_1, + output [17:0] o_Ct_2, + output [17:0] o_Ct_3, + output [17:0] o_Ct_4, + output [17:0] o_Ct_5, + output [17:0] o_Ct_6, + output [17:0] o_Ct_7, + output [17:0] o_Ct_8, + output [17:0] o_Ct_9, + output [17:0] o_Ct_10, + output [17:0] o_Ct_11, + output [17:0] o_Ct_12, + output [17:0] o_Ct_13, + output [17:0] o_Ct_14, + output [17:0] o_Ct_15, + output [17:0] o_Ct_16, + output [17:0] o_Ct_17, + output [17:0] o_Ct_18, + output [17:0] o_Ct_19, + output [17:0] o_Ct_20, + output [17:0] o_Ct_21, + output [17:0] o_Ct_22, + output [17:0] o_Ct_23, + output [17:0] o_Ct_24, + output [17:0] o_Ct_25, + output [17:0] o_Ct_26, + output [17:0] o_Ct_27, + output [17:0] o_Ct_28, + output [17:0] o_Ct_29, + output [17:0] o_Ct_30, + output [17:0] o_Ct_31, + output o_valid +); + +wire [287:0] packed_o_Ct_0; +reg [5:0] raddrs_0; +wire [287:0] packed_o_Ct_1; +reg [5:0] raddrs_1; +wire [287:0] packed_Ct; + +reg r_valid; + +wire [13:0] input_index_counter; +counter_63_1 counter_63_1_inst_in ( + .clk(clk), + .reset(reset), + .ena(wen), + .count(input_index_counter) +); + +wire [13:0] output_index_counter; +counter_63_1 counter_63_1_inst_out ( + .clk(clk), + .reset(reset), + .ena(ren), + .count(output_index_counter) +); + +always @ (posedge clk) begin + r_valid <= ren; + if ((input_index_counter + 14'd0) < 64) + raddrs_0 <= input_index_counter[5:0] + 6'd0; + else + raddrs_0 <= 6'd63; + if ((input_index_counter + 14'd1) < 64) + raddrs_1 <= input_index_counter[5:0] + 6'd1; + else + raddrs_1 <= 6'd63; +end + +assign packed_Ct[17:0] = i_Ct_0; +assign packed_Ct[35:18] = i_Ct_1; +assign packed_Ct[53:36] = i_Ct_2; +assign packed_Ct[71:54] = i_Ct_3; +assign packed_Ct[89:72] = i_Ct_4; +assign packed_Ct[107:90] = i_Ct_5; +assign packed_Ct[125:108] = i_Ct_6; +assign packed_Ct[143:126] = i_Ct_7; +assign packed_Ct[161:144] = i_Ct_8; +assign packed_Ct[179:162] = i_Ct_9; +assign packed_Ct[197:180] = i_Ct_10; +assign packed_Ct[215:198] = i_Ct_11; +assign packed_Ct[233:216] = i_Ct_12; +assign packed_Ct[251:234] = i_Ct_13; +assign packed_Ct[269:252] = i_Ct_14; +assign packed_Ct[287:270] = i_Ct_15; + +ram_288_0_64 ram_288_0_64_inst_0 ( + .clk(clk), + .waddr(input_index_counter), + .wdata(packed_Ct), + .wen(wen), + .raddr(raddrs_0), + .q(packed_o_Ct_0) +); + +ram_288_0_64 ram_288_0_64_inst_1 ( + .clk(clk), + .waddr(input_index_counter), + .wdata(packed_Ct), + .wen(wen), + .raddr(raddrs_1), + .q(packed_o_Ct_1) +); + +assign o_Ct_0 = packed_o_Ct_0[17:0]; +assign o_Ct_1 = packed_o_Ct_0[35:18]; +assign o_Ct_2 = packed_o_Ct_0[53:36]; +assign o_Ct_3 = packed_o_Ct_0[71:54]; +assign o_Ct_4 = packed_o_Ct_0[89:72]; +assign o_Ct_5 = packed_o_Ct_0[107:90]; +assign o_Ct_6 = packed_o_Ct_0[125:108]; +assign o_Ct_7 = packed_o_Ct_0[143:126]; +assign o_Ct_8 = packed_o_Ct_0[161:144]; +assign o_Ct_9 = packed_o_Ct_0[179:162]; +assign o_Ct_10 = packed_o_Ct_0[197:180]; +assign o_Ct_11 = packed_o_Ct_0[215:198]; +assign o_Ct_12 = packed_o_Ct_0[233:216]; +assign o_Ct_13 = packed_o_Ct_0[251:234]; +assign o_Ct_14 = packed_o_Ct_0[269:252]; +assign o_Ct_15 = packed_o_Ct_0[287:270]; +assign o_Ct_16 = packed_o_Ct_1[17:0]; +assign o_Ct_17 = packed_o_Ct_1[35:18]; +assign o_Ct_18 = packed_o_Ct_1[53:36]; +assign o_Ct_19 = packed_o_Ct_1[71:54]; +assign o_Ct_20 = packed_o_Ct_1[89:72]; +assign o_Ct_21 = packed_o_Ct_1[107:90]; +assign o_Ct_22 = packed_o_Ct_1[125:108]; +assign o_Ct_23 = packed_o_Ct_1[143:126]; +assign o_Ct_24 = packed_o_Ct_1[161:144]; +assign o_Ct_25 = packed_o_Ct_1[179:162]; +assign o_Ct_26 = packed_o_Ct_1[197:180]; +assign o_Ct_27 = packed_o_Ct_1[215:198]; +assign o_Ct_28 = packed_o_Ct_1[233:216]; +assign o_Ct_29 = packed_o_Ct_1[251:234]; +assign o_Ct_30 = packed_o_Ct_1[269:252]; +assign o_Ct_31 = packed_o_Ct_1[287:270]; +assign o_valid = r_valid; +endmodule + +module counter_63_1 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd1) <= 63) begin + count <= count + 14'd1; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module ram_288_0_64 ( + input clk, + input [5:0] waddr, + input [287:0] wdata, + input wen, + input [5:0] raddr, + output [287:0] q +); + +wire [287:0] rd_dummy_signal; +wire [287:0] wr_dummy_signal; +assign rd_dummy_signal = 0; + +dpram # (.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(q), + .clk(clk) +); +endmodule + +module stage2_mt_buffer_18_2_16_64_32 ( + input clk, + input reset, + input i_valid, + input [17:0] data_0, + output [17:0] q_0, + input [17:0] data_1, + output [17:0] q_1, + input [17:0] data_2, + output [17:0] q_2, + input [17:0] data_3, + output [17:0] q_3, + input [17:0] data_4, + output [17:0] q_4, + input [17:0] data_5, + output [17:0] q_5, + input [17:0] data_6, + output [17:0] q_6, + input [17:0] data_7, + output [17:0] q_7, + input [17:0] data_8, + output [17:0] q_8, + input [17:0] data_9, + output [17:0] q_9, + input [17:0] data_10, + output [17:0] q_10, + input [17:0] data_11, + output [17:0] q_11, + input [17:0] data_12, + output [17:0] q_12, + input [17:0] data_13, + output [17:0] q_13, + input [17:0] data_14, + output [17:0] q_14, + input [17:0] data_15, + output [17:0] q_15, + output o_valid +); + +wire [287:0] packed_result; +wire [287:0] packed_data; + +wire [13:0] input_index_counter; +reg is_buffer_full; +counter_63_1 counter_63_1_inst_in ( + .clk(clk), + .reset(reset), + .ena(i_valid), + .count(input_index_counter) +); + +reg en_output_counter; +wire [13:0] output_index_counter; +counter_63_1 counter_63_1_inst_out_count ( + .clk(clk), + .reset(reset), + .ena(en_output_counter), + .count(output_index_counter) +); + +reg [5:0] raddr; +always @ (*) begin + if (is_buffer_full) + raddr <= output_index_counter[5:0]; + else + raddr <= input_index_counter[5:0]; +end + +wire incr_loop_index; +assign incr_loop_index = (output_index_counter == (63) && en_output_counter); + +reg is_output_enough; +wire [13:0] loop_counter; +counter_14_1 counter_14_1_inst_out_enough ( + .clk(clk), + .reset(reset), + .ena(incr_loop_index), + .count(loop_counter) +); + +ram_288_0_64 ram_288_0_64_inst_lapzsbetrr ( + .clk(clk), + .waddr(input_index_counter), + .wdata(packed_data), + .wen(i_valid), + .raddr(raddr), + .q(packed_result) +); + +assign q_0 = packed_result[17:0]; +assign packed_data[17:0] = data_0; +assign q_1 = packed_result[35:18]; +assign packed_data[35:18] = data_1; +assign q_2 = packed_result[53:36]; +assign packed_data[53:36] = data_2; +assign q_3 = packed_result[71:54]; +assign packed_data[71:54] = data_3; +assign q_4 = packed_result[89:72]; +assign packed_data[89:72] = data_4; +assign q_5 = packed_result[107:90]; +assign packed_data[107:90] = data_5; +assign q_6 = packed_result[125:108]; +assign packed_data[125:108] = data_6; +assign q_7 = packed_result[143:126]; +assign packed_data[143:126] = data_7; +assign q_8 = packed_result[161:144]; +assign packed_data[161:144] = data_8; +assign q_9 = packed_result[179:162]; +assign packed_data[179:162] = data_9; +assign q_10 = packed_result[197:180]; +assign packed_data[197:180] = data_10; +assign q_11 = packed_result[215:198]; +assign packed_data[215:198] = data_11; +assign q_12 = packed_result[233:216]; +assign packed_data[233:216] = data_12; +assign q_13 = packed_result[251:234]; +assign packed_data[251:234] = data_13; +assign q_14 = packed_result[269:252]; +assign packed_data[269:252] = data_14; +assign q_15 = packed_result[287:270]; +assign packed_data[287:270] = data_15; + +always @ (posedge clk) begin + if (reset) begin + en_output_counter <= 1'b0; + is_buffer_full <= 1'b0; + is_output_enough <= 1'b0; + end else begin + en_output_counter <= (is_buffer_full && ~en_output_counter && ~is_output_enough); + if (input_index_counter == 63 && i_valid) + is_buffer_full <= 1'b1; + else if (input_index_counter == 0 && output_index_counter == 0 && is_output_enough) + is_buffer_full <= 1'b0; + if ((loop_counter == (14)) + &&(output_index_counter == 63) + && en_output_counter) + is_output_enough <= 1'b1; + else if (loop_counter == 0 && i_valid) + is_output_enough <= 1'b0; + end +end + +wire valid_1, valid_2, is_buffer_full_hold; +shift_register_unit_12 shift_register_unit_12_inst_is_buffer_full ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .in(is_buffer_full), + .out(is_buffer_full_hold) +); + +shift_register_unit_12 shift_register_unit_12_inst_valid1 ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .in(i_valid), + .out(valid_1) +); + +shift_register_unit_12 shift_register_unit_12_inst_valid2 ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .in(en_output_counter), + .out(valid_2) +); + +reg output_valid; +always @ (*) begin + if (is_buffer_full_hold) + output_valid <= valid_2; + else + output_valid <= valid_1; +end +assign o_valid = output_valid; + +endmodule + +module counter_14_1 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd1) <= 14) begin + count <= count + 14'd1; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module shift_register_unit_12 ( + input clk, + input reset, + input enable, + input [0:0] in, + output [0:0] out +); + +reg [0:0] shift_registers_0; +reg [0:0] shift_registers_1; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 1'd0; + shift_registers_1 <= 1'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + end +end + +assign out = shift_registers_1; + +endmodule + +module C_LSTM_stage_3_18_10_64_2048_2_16_1 ( + input clk, + input reset, + input [287:0] wdata, + input [1:0] wen, + input i_ready, + input i_valid, + input [17:0] i_mt_0, + input [17:0] i_mt_1, + input [17:0] i_mt_2, + input [17:0] i_mt_3, + input [17:0] i_mt_4, + input [17:0] i_mt_5, + input [17:0] i_mt_6, + input [17:0] i_mt_7, + input [17:0] i_mt_8, + input [17:0] i_mt_9, + input [17:0] i_mt_10, + input [17:0] i_mt_11, + input [17:0] i_mt_12, + input [17:0] i_mt_13, + input [17:0] i_mt_14, + input [17:0] i_mt_15, + output [17:0] o_Yt_0_0, + output [17:0] o_Yt_0_1, + output [17:0] o_Yt_0_2, + output [17:0] o_Yt_0_3, + output [17:0] o_Yt_0_4, + output [17:0] o_Yt_0_5, + output [17:0] o_Yt_0_6, + output [17:0] o_Yt_0_7, + output [17:0] o_Yt_0_8, + output [17:0] o_Yt_0_9, + output [17:0] o_Yt_0_10, + output [17:0] o_Yt_0_11, + output [17:0] o_Yt_0_12, + output [17:0] o_Yt_0_13, + output [17:0] o_Yt_0_14, + output [17:0] o_Yt_0_15, + output [17:0] o_Yt_1_0, + output [17:0] o_Yt_1_1, + output [17:0] o_Yt_1_2, + output [17:0] o_Yt_1_3, + output [17:0] o_Yt_1_4, + output [17:0] o_Yt_1_5, + output [17:0] o_Yt_1_6, + output [17:0] o_Yt_1_7, + output [17:0] o_Yt_1_8, + output [17:0] o_Yt_1_9, + output [17:0] o_Yt_1_10, + output [17:0] o_Yt_1_11, + output [17:0] o_Yt_1_12, + output [17:0] o_Yt_1_13, + output [17:0] o_Yt_1_14, + output [17:0] o_Yt_1_15, + output o_valid, + output o_ready +); + +wire enable; +assign enable = i_ready; +wire [17:0] mt_hold_0; +wire [17:0] mt_hold_1; +wire [17:0] mt_hold_2; +wire [17:0] mt_hold_3; +wire [17:0] mt_hold_4; +wire [17:0] mt_hold_5; +wire [17:0] mt_hold_6; +wire [17:0] mt_hold_7; +wire [17:0] mt_hold_8; +wire [17:0] mt_hold_9; +wire [17:0] mt_hold_10; +wire [17:0] mt_hold_11; +wire [17:0] mt_hold_12; +wire [17:0] mt_hold_13; +wire [17:0] mt_hold_14; +wire [17:0] mt_hold_15; +wire [17:0] Wym_real_0_0; +wire [17:0] Wym_imag_0_0; +wire [17:0] Wym_real_0_1; +wire [17:0] Wym_imag_0_1; +wire [17:0] Wym_real_0_2; +wire [17:0] Wym_imag_0_2; +wire [17:0] Wym_real_0_3; +wire [17:0] Wym_imag_0_3; +wire [17:0] Wym_real_0_4; +wire [17:0] Wym_imag_0_4; +wire [17:0] Wym_real_0_5; +wire [17:0] Wym_imag_0_5; +wire [17:0] Wym_real_0_6; +wire [17:0] Wym_imag_0_6; +wire [17:0] Wym_real_0_7; +wire [17:0] Wym_imag_0_7; +wire [17:0] Wym_real_0_8; +wire [17:0] Wym_imag_0_8; +wire [17:0] Wym_real_1_0; +wire [17:0] Wym_imag_1_0; +wire [17:0] Wym_real_1_1; +wire [17:0] Wym_imag_1_1; +wire [17:0] Wym_real_1_2; +wire [17:0] Wym_imag_1_2; +wire [17:0] Wym_real_1_3; +wire [17:0] Wym_imag_1_3; +wire [17:0] Wym_real_1_4; +wire [17:0] Wym_imag_1_4; +wire [17:0] Wym_real_1_5; +wire [17:0] Wym_imag_1_5; +wire [17:0] Wym_real_1_6; +wire [17:0] Wym_imag_1_6; +wire [17:0] Wym_real_1_7; +wire [17:0] Wym_imag_1_7; +wire [17:0] Wym_real_1_8; +wire [17:0] Wym_imag_1_8; +wire reg_i_valid; +reg reg_i_ready; + +shift_register_group_18_16_3 shift_register_group_18_16_3_mt_holder ( + .clk(clk), + .enable(enable), + .in_0(i_mt_0), + .out_0(mt_hold_0), + .in_1(i_mt_1), + .out_1(mt_hold_1), + .in_2(i_mt_2), + .out_2(mt_hold_2), + .in_3(i_mt_3), + .out_3(mt_hold_3), + .in_4(i_mt_4), + .out_4(mt_hold_4), + .in_5(i_mt_5), + .out_5(mt_hold_5), + .in_6(i_mt_6), + .out_6(mt_hold_6), + .in_7(i_mt_7), + .out_7(mt_hold_7), + .in_8(i_mt_8), + .out_8(mt_hold_8), + .in_9(i_mt_9), + .out_9(mt_hold_9), + .in_10(i_mt_10), + .out_10(mt_hold_10), + .in_11(i_mt_11), + .out_11(mt_hold_11), + .in_12(i_mt_12), + .out_12(mt_hold_12), + .in_13(i_mt_13), + .out_13(mt_hold_13), + .in_14(i_mt_14), + .out_14(mt_hold_14), + .in_15(i_mt_15), + .out_15(mt_hold_15), + .reset(reset) +); + +shift_register_unit_18_3 shift_register_unit_18_3_valid_holder ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(i_valid), + .out(reg_i_valid) +); + +stage3_parameter_buffer_18_2_16_64_2048 stage3_parameter_buffer_18_2_16_64_2048_inst_uexvzvnils ( + .clk(clk), + .reset(reset), + .wdata(wdata), + .wen(wen), + .Wym_real_0_0(Wym_real_0_0), + .Wym_imag_0_0(Wym_imag_0_0), + .Wym_real_0_1(Wym_real_0_1), + .Wym_imag_0_1(Wym_imag_0_1), + .Wym_real_0_2(Wym_real_0_2), + .Wym_imag_0_2(Wym_imag_0_2), + .Wym_real_0_3(Wym_real_0_3), + .Wym_imag_0_3(Wym_imag_0_3), + .Wym_real_0_4(Wym_real_0_4), + .Wym_imag_0_4(Wym_imag_0_4), + .Wym_real_0_5(Wym_real_0_5), + .Wym_imag_0_5(Wym_imag_0_5), + .Wym_real_0_6(Wym_real_0_6), + .Wym_imag_0_6(Wym_imag_0_6), + .Wym_real_0_7(Wym_real_0_7), + .Wym_imag_0_7(Wym_imag_0_7), + .Wym_real_0_8(Wym_real_0_8), + .Wym_imag_0_8(Wym_imag_0_8), + .Wym_real_1_0(Wym_real_1_0), + .Wym_imag_1_0(Wym_imag_1_0), + .Wym_real_1_1(Wym_real_1_1), + .Wym_imag_1_1(Wym_imag_1_1), + .Wym_real_1_2(Wym_real_1_2), + .Wym_imag_1_2(Wym_imag_1_2), + .Wym_real_1_3(Wym_real_1_3), + .Wym_imag_1_3(Wym_imag_1_3), + .Wym_real_1_4(Wym_real_1_4), + .Wym_imag_1_4(Wym_imag_1_4), + .Wym_real_1_5(Wym_real_1_5), + .Wym_imag_1_5(Wym_imag_1_5), + .Wym_real_1_6(Wym_real_1_6), + .Wym_imag_1_6(Wym_imag_1_6), + .Wym_real_1_7(Wym_real_1_7), + .Wym_imag_1_7(Wym_imag_1_7), + .Wym_real_1_8(Wym_real_1_8), + .Wym_imag_1_8(Wym_imag_1_8), + .incr_index(i_valid) +); + +multiple_c_matrix_vec_mult_and_sum_18_10_16_1_2_64 multiple_c_matrix_vec_mult_and_sum_18_10_16_1_2_64_inst_ilwsakkywf ( + .clk(clk), + .reset(reset), + .i_ready(reg_i_ready), + .i_valid(reg_i_valid), + .i_X_0(mt_hold_0), + .i_X_1(mt_hold_1), + .i_X_2(mt_hold_2), + .i_X_3(mt_hold_3), + .i_X_4(mt_hold_4), + .i_X_5(mt_hold_5), + .i_X_6(mt_hold_6), + .i_X_7(mt_hold_7), + .i_X_8(mt_hold_8), + .i_X_9(mt_hold_9), + .i_X_10(mt_hold_10), + .i_X_11(mt_hold_11), + .i_X_12(mt_hold_12), + .i_X_13(mt_hold_13), + .i_X_14(mt_hold_14), + .i_X_15(mt_hold_15), + .i_W_real_0_0(Wym_real_0_0), + .i_W_imag_0_0(Wym_imag_0_0), + .i_W_real_0_1(Wym_real_0_1), + .i_W_imag_0_1(Wym_imag_0_1), + .i_W_real_0_2(Wym_real_0_2), + .i_W_imag_0_2(Wym_imag_0_2), + .i_W_real_0_3(Wym_real_0_3), + .i_W_imag_0_3(Wym_imag_0_3), + .i_W_real_0_4(Wym_real_0_4), + .i_W_imag_0_4(Wym_imag_0_4), + .i_W_real_0_5(Wym_real_0_5), + .i_W_imag_0_5(Wym_imag_0_5), + .i_W_real_0_6(Wym_real_0_6), + .i_W_imag_0_6(Wym_imag_0_6), + .i_W_real_0_7(Wym_real_0_7), + .i_W_imag_0_7(Wym_imag_0_7), + .i_W_real_0_8(Wym_real_0_8), + .i_W_imag_0_8(Wym_imag_0_8), + .i_W_real_1_0(Wym_real_1_0), + .i_W_imag_1_0(Wym_imag_1_0), + .i_W_real_1_1(Wym_real_1_1), + .i_W_imag_1_1(Wym_imag_1_1), + .i_W_real_1_2(Wym_real_1_2), + .i_W_imag_1_2(Wym_imag_1_2), + .i_W_real_1_3(Wym_real_1_3), + .i_W_imag_1_3(Wym_imag_1_3), + .i_W_real_1_4(Wym_real_1_4), + .i_W_imag_1_4(Wym_imag_1_4), + .i_W_real_1_5(Wym_real_1_5), + .i_W_imag_1_5(Wym_imag_1_5), + .i_W_real_1_6(Wym_real_1_6), + .i_W_imag_1_6(Wym_imag_1_6), + .i_W_real_1_7(Wym_real_1_7), + .i_W_imag_1_7(Wym_imag_1_7), + .i_W_real_1_8(Wym_real_1_8), + .i_W_imag_1_8(Wym_imag_1_8), + .o_Y_0_0(o_Yt_0_0), + .o_Y_0_1(o_Yt_0_1), + .o_Y_0_2(o_Yt_0_2), + .o_Y_0_3(o_Yt_0_3), + .o_Y_0_4(o_Yt_0_4), + .o_Y_0_5(o_Yt_0_5), + .o_Y_0_6(o_Yt_0_6), + .o_Y_0_7(o_Yt_0_7), + .o_Y_0_8(o_Yt_0_8), + .o_Y_0_9(o_Yt_0_9), + .o_Y_0_10(o_Yt_0_10), + .o_Y_0_11(o_Yt_0_11), + .o_Y_0_12(o_Yt_0_12), + .o_Y_0_13(o_Yt_0_13), + .o_Y_0_14(o_Yt_0_14), + .o_Y_0_15(o_Yt_0_15), + .o_Y_1_0(o_Yt_1_0), + .o_Y_1_1(o_Yt_1_1), + .o_Y_1_2(o_Yt_1_2), + .o_Y_1_3(o_Yt_1_3), + .o_Y_1_4(o_Yt_1_4), + .o_Y_1_5(o_Yt_1_5), + .o_Y_1_6(o_Yt_1_6), + .o_Y_1_7(o_Yt_1_7), + .o_Y_1_8(o_Yt_1_8), + .o_Y_1_9(o_Yt_1_9), + .o_Y_1_10(o_Yt_1_10), + .o_Y_1_11(o_Yt_1_11), + .o_Y_1_12(o_Yt_1_12), + .o_Y_1_13(o_Yt_1_13), + .o_Y_1_14(o_Yt_1_14), + .o_Y_1_15(o_Yt_1_15), + .o_valid(o_valid), + .o_ready(o_ready) +); + +always @ (posedge clk) begin + if (reset) begin + reg_i_ready <= 1'b0; + end else begin + reg_i_ready <= i_ready; + end +end + +endmodule + +module stage3_parameter_buffer_18_2_16_64_2048 ( + input clk, + input reset, + input [161:0] wdata, + input [1:0] wen, + output [17:0] Wym_real_0_0, + output [17:0] Wym_imag_0_0, + output [17:0] Wym_real_0_1, + output [17:0] Wym_imag_0_1, + output [17:0] Wym_real_0_2, + output [17:0] Wym_imag_0_2, + output [17:0] Wym_real_0_3, + output [17:0] Wym_imag_0_3, + output [17:0] Wym_real_0_4, + output [17:0] Wym_imag_0_4, + output [17:0] Wym_real_0_5, + output [17:0] Wym_imag_0_5, + output [17:0] Wym_real_0_6, + output [17:0] Wym_imag_0_6, + output [17:0] Wym_real_0_7, + output [17:0] Wym_imag_0_7, + output [17:0] Wym_real_0_8, + output [17:0] Wym_imag_0_8, + output [17:0] Wym_real_1_0, + output [17:0] Wym_imag_1_0, + output [17:0] Wym_real_1_1, + output [17:0] Wym_imag_1_1, + output [17:0] Wym_real_1_2, + output [17:0] Wym_imag_1_2, + output [17:0] Wym_real_1_3, + output [17:0] Wym_imag_1_3, + output [17:0] Wym_real_1_4, + output [17:0] Wym_imag_1_4, + output [17:0] Wym_real_1_5, + output [17:0] Wym_imag_1_5, + output [17:0] Wym_real_1_6, + output [17:0] Wym_imag_1_6, + output [17:0] Wym_real_1_7, + output [17:0] Wym_imag_1_7, + output [17:0] Wym_real_1_8, + output [17:0] Wym_imag_1_8, + input incr_index +); + +wire [13:0] input_index_counter; +counter_63_1 counter_63_1_inst_input ( + .clk(clk), + .reset(reset), + .ena(incr_index), + .count(input_index_counter) +); + +wire incr_row_index; +assign incr_row_index = (input_index_counter == 63 & incr_index); +wire [13:0] weight_row_index_counter; +counter_31_2 counter_31_2_inst_weight ( + .clk(clk), + .reset(reset), + .ena(incr_row_index), + .count(weight_row_index_counter) +); + +reg [13:0] weight_index; +always @ (*) begin + weight_index = weight_row_index_counter * 14'd64 + input_index_counter; +end +weight_buffer_18_9_2_64_2048_Wym_real_half_0 weight_buffer_18_9_2_64_2048_Wym_real_half_0_inst_gmisucamog_real ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[0]), + .q_0_0(Wym_real_0_0), + .q_0_1(Wym_real_0_1), + .q_0_2(Wym_real_0_2), + .q_0_3(Wym_real_0_3), + .q_0_4(Wym_real_0_4), + .q_0_5(Wym_real_0_5), + .q_0_6(Wym_real_0_6), + .q_0_7(Wym_real_0_7), + .q_0_8(Wym_real_0_8), + .q_1_0(Wym_real_1_0), + .q_1_1(Wym_real_1_1), + .q_1_2(Wym_real_1_2), + .q_1_3(Wym_real_1_3), + .q_1_4(Wym_real_1_4), + .q_1_5(Wym_real_1_5), + .q_1_6(Wym_real_1_6), + .q_1_7(Wym_real_1_7), + .q_1_8(Wym_real_1_8), + .index(weight_index) +); + +weight_buffer_18_9_2_64_2048_Wym_imag_half_0 weight_buffer_18_9_2_64_2048_Wym_imag_half_0_inst_qntsfjhatw_imag ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[1]), + .q_0_0(Wym_imag_0_0), + .q_0_1(Wym_imag_0_1), + .q_0_2(Wym_imag_0_2), + .q_0_3(Wym_imag_0_3), + .q_0_4(Wym_imag_0_4), + .q_0_5(Wym_imag_0_5), + .q_0_6(Wym_imag_0_6), + .q_0_7(Wym_imag_0_7), + .q_0_8(Wym_imag_0_8), + .q_1_0(Wym_imag_1_0), + .q_1_1(Wym_imag_1_1), + .q_1_2(Wym_imag_1_2), + .q_1_3(Wym_imag_1_3), + .q_1_4(Wym_imag_1_4), + .q_1_5(Wym_imag_1_5), + .q_1_6(Wym_imag_1_6), + .q_1_7(Wym_imag_1_7), + .q_1_8(Wym_imag_1_8), + .index(weight_index) +); + +endmodule + +module counter_31_2 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd2) <= 31) begin + count <= count + 14'd2; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module weight_buffer_18_9_2_64_2048_Wym_real_half_0 ( + input clk, + input rst, + input [161:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + input [10:0] index +); + +wire [161:0] packed_result_0; +reg [10:0] addrs_0; +reg [10:0] addrs_base_0; +wire [161:0] packed_result_1; +reg [10:0] addrs_1; +reg [10:0] addrs_base_1; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 64; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + end +end + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; + +endmodule + +module weight_buffer_18_9_2_64_2048_Wym_imag_half_0 ( + input clk, + input rst, + input [161:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_1_0, + output [17:0] q_1_1, + output [17:0] q_1_2, + output [17:0] q_1_3, + output [17:0] q_1_4, + output [17:0] q_1_5, + output [17:0] q_1_6, + output [17:0] q_1_7, + output [17:0] q_1_8, + input [10:0] index +); + +wire [161:0] packed_result_0; +reg [10:0] addrs_0; +reg [10:0] addrs_base_0; +wire [161:0] packed_result_1; +reg [10:0] addrs_1; +reg [10:0] addrs_base_1; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + addrs_base_1 <= 64; + end else begin + addrs_0 <= index + addrs_base_0; + addrs_1 <= index + addrs_base_1; + end +end + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_1 ( + .we(wen), + .addr(addrs_1), + .data(wdata), + .out(packed_result_1), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_1_0 = packed_result_1[17:0]; +assign q_1_1 = packed_result_1[35:18]; +assign q_1_2 = packed_result_1[53:36]; +assign q_1_3 = packed_result_1[71:54]; +assign q_1_4 = packed_result_1[89:72]; +assign q_1_5 = packed_result_1[107:90]; +assign q_1_6 = packed_result_1[125:108]; +assign q_1_7 = packed_result_1[143:126]; +assign q_1_8 = packed_result_1[161:144]; + +endmodule + +module multiple_c_matrix_vec_mult_and_sum_18_10_16_1_2_64 ( + input clk, + input reset, + input i_ready, + input i_valid, + input [17:0] i_X_0, + input [17:0] i_X_1, + input [17:0] i_X_2, + input [17:0] i_X_3, + input [17:0] i_X_4, + input [17:0] i_X_5, + input [17:0] i_X_6, + input [17:0] i_X_7, + input [17:0] i_X_8, + input [17:0] i_X_9, + input [17:0] i_X_10, + input [17:0] i_X_11, + input [17:0] i_X_12, + input [17:0] i_X_13, + input [17:0] i_X_14, + input [17:0] i_X_15, + input [17:0] i_W_real_0_0, + input [17:0] i_W_imag_0_0, + input [17:0] i_W_real_0_1, + input [17:0] i_W_imag_0_1, + input [17:0] i_W_real_0_2, + input [17:0] i_W_imag_0_2, + input [17:0] i_W_real_0_3, + input [17:0] i_W_imag_0_3, + input [17:0] i_W_real_0_4, + input [17:0] i_W_imag_0_4, + input [17:0] i_W_real_0_5, + input [17:0] i_W_imag_0_5, + input [17:0] i_W_real_0_6, + input [17:0] i_W_imag_0_6, + input [17:0] i_W_real_0_7, + input [17:0] i_W_imag_0_7, + input [17:0] i_W_real_0_8, + input [17:0] i_W_imag_0_8, + input [17:0] i_W_real_1_0, + input [17:0] i_W_imag_1_0, + input [17:0] i_W_real_1_1, + input [17:0] i_W_imag_1_1, + input [17:0] i_W_real_1_2, + input [17:0] i_W_imag_1_2, + input [17:0] i_W_real_1_3, + input [17:0] i_W_imag_1_3, + input [17:0] i_W_real_1_4, + input [17:0] i_W_imag_1_4, + input [17:0] i_W_real_1_5, + input [17:0] i_W_imag_1_5, + input [17:0] i_W_real_1_6, + input [17:0] i_W_imag_1_6, + input [17:0] i_W_real_1_7, + input [17:0] i_W_imag_1_7, + input [17:0] i_W_real_1_8, + input [17:0] i_W_imag_1_8, + output [17:0] o_Y_0_0, + output [17:0] o_Y_0_1, + output [17:0] o_Y_0_2, + output [17:0] o_Y_0_3, + output [17:0] o_Y_0_4, + output [17:0] o_Y_0_5, + output [17:0] o_Y_0_6, + output [17:0] o_Y_0_7, + output [17:0] o_Y_0_8, + output [17:0] o_Y_0_9, + output [17:0] o_Y_0_10, + output [17:0] o_Y_0_11, + output [17:0] o_Y_0_12, + output [17:0] o_Y_0_13, + output [17:0] o_Y_0_14, + output [17:0] o_Y_0_15, + output [17:0] o_Y_1_0, + output [17:0] o_Y_1_1, + output [17:0] o_Y_1_2, + output [17:0] o_Y_1_3, + output [17:0] o_Y_1_4, + output [17:0] o_Y_1_5, + output [17:0] o_Y_1_6, + output [17:0] o_Y_1_7, + output [17:0] o_Y_1_8, + output [17:0] o_Y_1_9, + output [17:0] o_Y_1_10, + output [17:0] o_Y_1_11, + output [17:0] o_Y_1_12, + output [17:0] o_Y_1_13, + output [17:0] o_Y_1_14, + output [17:0] o_Y_1_15, + output o_valid, + output o_ready +); + +wire matrix_vec_mult_ready, matrix_vec_mult_valid; +wire accum_valid_0; +wire idft_next_out_0; +wire accum_valid_1; +wire idft_next_out_1; +reg idft_out_valid; +wire [17:0] Y_imag_0_0; +wire [17:0] Y_real_0_0; +wire [17:0] sum_Y_real_0_0; +wire [17:0] sum_Y_imag_0_0; +wire [17:0] sum_Y_real_hold_0_0; +wire [17:0] sum_Y_imag_hold_0_0; +wire [17:0] out_Y_idft_0_0; +reg [17:0] reg_Y_0_0; +wire [17:0] Y_imag_0_1; +wire [17:0] Y_real_0_1; +wire [17:0] sum_Y_real_0_1; +wire [17:0] sum_Y_imag_0_1; +wire [17:0] sum_Y_real_hold_0_1; +wire [17:0] sum_Y_imag_hold_0_1; +wire [17:0] out_Y_idft_0_1; +reg [17:0] reg_Y_0_1; +wire [17:0] Y_imag_0_2; +wire [17:0] Y_real_0_2; +wire [17:0] sum_Y_real_0_2; +wire [17:0] sum_Y_imag_0_2; +wire [17:0] sum_Y_real_hold_0_2; +wire [17:0] sum_Y_imag_hold_0_2; +wire [17:0] out_Y_idft_0_2; +reg [17:0] reg_Y_0_2; +wire [17:0] Y_imag_0_3; +wire [17:0] Y_real_0_3; +wire [17:0] sum_Y_real_0_3; +wire [17:0] sum_Y_imag_0_3; +wire [17:0] sum_Y_real_hold_0_3; +wire [17:0] sum_Y_imag_hold_0_3; +wire [17:0] out_Y_idft_0_3; +reg [17:0] reg_Y_0_3; +wire [17:0] Y_imag_0_4; +wire [17:0] Y_real_0_4; +wire [17:0] sum_Y_real_0_4; +wire [17:0] sum_Y_imag_0_4; +wire [17:0] sum_Y_real_hold_0_4; +wire [17:0] sum_Y_imag_hold_0_4; +wire [17:0] out_Y_idft_0_4; +reg [17:0] reg_Y_0_4; +wire [17:0] Y_imag_0_5; +wire [17:0] Y_real_0_5; +wire [17:0] sum_Y_real_0_5; +wire [17:0] sum_Y_imag_0_5; +wire [17:0] sum_Y_real_hold_0_5; +wire [17:0] sum_Y_imag_hold_0_5; +wire [17:0] out_Y_idft_0_5; +reg [17:0] reg_Y_0_5; +wire [17:0] Y_imag_0_6; +wire [17:0] Y_real_0_6; +wire [17:0] sum_Y_real_0_6; +wire [17:0] sum_Y_imag_0_6; +wire [17:0] sum_Y_real_hold_0_6; +wire [17:0] sum_Y_imag_hold_0_6; +wire [17:0] out_Y_idft_0_6; +reg [17:0] reg_Y_0_6; +wire [17:0] Y_imag_0_7; +wire [17:0] Y_real_0_7; +wire [17:0] sum_Y_real_0_7; +wire [17:0] sum_Y_imag_0_7; +wire [17:0] sum_Y_real_hold_0_7; +wire [17:0] sum_Y_imag_hold_0_7; +wire [17:0] out_Y_idft_0_7; +reg [17:0] reg_Y_0_7; +wire [17:0] Y_imag_0_8; +wire [17:0] Y_real_0_8; +wire [17:0] sum_Y_real_0_8; +wire [17:0] sum_Y_imag_0_8; +wire [17:0] sum_Y_real_hold_0_8; +wire [17:0] sum_Y_imag_hold_0_8; +wire [17:0] out_Y_idft_0_8; +reg [17:0] reg_Y_0_8; +wire [17:0] Y_imag_0_9; +wire [17:0] Y_real_0_9; +wire [17:0] sum_Y_real_0_9; +wire [17:0] sum_Y_imag_0_9; +wire [17:0] sum_Y_real_hold_0_9; +wire [17:0] sum_Y_imag_hold_0_9; +wire [17:0] out_Y_idft_0_9; +reg [17:0] reg_Y_0_9; +wire [17:0] Y_imag_0_10; +wire [17:0] Y_real_0_10; +wire [17:0] sum_Y_real_0_10; +wire [17:0] sum_Y_imag_0_10; +wire [17:0] sum_Y_real_hold_0_10; +wire [17:0] sum_Y_imag_hold_0_10; +wire [17:0] out_Y_idft_0_10; +reg [17:0] reg_Y_0_10; +wire [17:0] Y_imag_0_11; +wire [17:0] Y_real_0_11; +wire [17:0] sum_Y_real_0_11; +wire [17:0] sum_Y_imag_0_11; +wire [17:0] sum_Y_real_hold_0_11; +wire [17:0] sum_Y_imag_hold_0_11; +wire [17:0] out_Y_idft_0_11; +reg [17:0] reg_Y_0_11; +wire [17:0] Y_imag_0_12; +wire [17:0] Y_real_0_12; +wire [17:0] sum_Y_real_0_12; +wire [17:0] sum_Y_imag_0_12; +wire [17:0] sum_Y_real_hold_0_12; +wire [17:0] sum_Y_imag_hold_0_12; +wire [17:0] out_Y_idft_0_12; +reg [17:0] reg_Y_0_12; +wire [17:0] Y_imag_0_13; +wire [17:0] Y_real_0_13; +wire [17:0] sum_Y_real_0_13; +wire [17:0] sum_Y_imag_0_13; +wire [17:0] sum_Y_real_hold_0_13; +wire [17:0] sum_Y_imag_hold_0_13; +wire [17:0] out_Y_idft_0_13; +reg [17:0] reg_Y_0_13; +wire [17:0] Y_imag_0_14; +wire [17:0] Y_real_0_14; +wire [17:0] sum_Y_real_0_14; +wire [17:0] sum_Y_imag_0_14; +wire [17:0] sum_Y_real_hold_0_14; +wire [17:0] sum_Y_imag_hold_0_14; +wire [17:0] out_Y_idft_0_14; +reg [17:0] reg_Y_0_14; +wire [17:0] Y_imag_0_15; +wire [17:0] Y_real_0_15; +wire [17:0] sum_Y_real_0_15; +wire [17:0] sum_Y_imag_0_15; +wire [17:0] sum_Y_real_hold_0_15; +wire [17:0] sum_Y_imag_hold_0_15; +wire [17:0] out_Y_idft_0_15; +reg [17:0] reg_Y_0_15; +wire [17:0] Y_imag_1_0; +wire [17:0] Y_real_1_0; +wire [17:0] sum_Y_real_1_0; +wire [17:0] sum_Y_imag_1_0; +wire [17:0] sum_Y_real_hold_1_0; +wire [17:0] sum_Y_imag_hold_1_0; +wire [17:0] out_Y_idft_1_0; +reg [17:0] reg_Y_1_0; +wire [17:0] Y_imag_1_1; +wire [17:0] Y_real_1_1; +wire [17:0] sum_Y_real_1_1; +wire [17:0] sum_Y_imag_1_1; +wire [17:0] sum_Y_real_hold_1_1; +wire [17:0] sum_Y_imag_hold_1_1; +wire [17:0] out_Y_idft_1_1; +reg [17:0] reg_Y_1_1; +wire [17:0] Y_imag_1_2; +wire [17:0] Y_real_1_2; +wire [17:0] sum_Y_real_1_2; +wire [17:0] sum_Y_imag_1_2; +wire [17:0] sum_Y_real_hold_1_2; +wire [17:0] sum_Y_imag_hold_1_2; +wire [17:0] out_Y_idft_1_2; +reg [17:0] reg_Y_1_2; +wire [17:0] Y_imag_1_3; +wire [17:0] Y_real_1_3; +wire [17:0] sum_Y_real_1_3; +wire [17:0] sum_Y_imag_1_3; +wire [17:0] sum_Y_real_hold_1_3; +wire [17:0] sum_Y_imag_hold_1_3; +wire [17:0] out_Y_idft_1_3; +reg [17:0] reg_Y_1_3; +wire [17:0] Y_imag_1_4; +wire [17:0] Y_real_1_4; +wire [17:0] sum_Y_real_1_4; +wire [17:0] sum_Y_imag_1_4; +wire [17:0] sum_Y_real_hold_1_4; +wire [17:0] sum_Y_imag_hold_1_4; +wire [17:0] out_Y_idft_1_4; +reg [17:0] reg_Y_1_4; +wire [17:0] Y_imag_1_5; +wire [17:0] Y_real_1_5; +wire [17:0] sum_Y_real_1_5; +wire [17:0] sum_Y_imag_1_5; +wire [17:0] sum_Y_real_hold_1_5; +wire [17:0] sum_Y_imag_hold_1_5; +wire [17:0] out_Y_idft_1_5; +reg [17:0] reg_Y_1_5; +wire [17:0] Y_imag_1_6; +wire [17:0] Y_real_1_6; +wire [17:0] sum_Y_real_1_6; +wire [17:0] sum_Y_imag_1_6; +wire [17:0] sum_Y_real_hold_1_6; +wire [17:0] sum_Y_imag_hold_1_6; +wire [17:0] out_Y_idft_1_6; +reg [17:0] reg_Y_1_6; +wire [17:0] Y_imag_1_7; +wire [17:0] Y_real_1_7; +wire [17:0] sum_Y_real_1_7; +wire [17:0] sum_Y_imag_1_7; +wire [17:0] sum_Y_real_hold_1_7; +wire [17:0] sum_Y_imag_hold_1_7; +wire [17:0] out_Y_idft_1_7; +reg [17:0] reg_Y_1_7; +wire [17:0] Y_imag_1_8; +wire [17:0] Y_real_1_8; +wire [17:0] sum_Y_real_1_8; +wire [17:0] sum_Y_imag_1_8; +wire [17:0] sum_Y_real_hold_1_8; +wire [17:0] sum_Y_imag_hold_1_8; +wire [17:0] out_Y_idft_1_8; +reg [17:0] reg_Y_1_8; +wire [17:0] Y_imag_1_9; +wire [17:0] Y_real_1_9; +wire [17:0] sum_Y_real_1_9; +wire [17:0] sum_Y_imag_1_9; +wire [17:0] sum_Y_real_hold_1_9; +wire [17:0] sum_Y_imag_hold_1_9; +wire [17:0] out_Y_idft_1_9; +reg [17:0] reg_Y_1_9; +wire [17:0] Y_imag_1_10; +wire [17:0] Y_real_1_10; +wire [17:0] sum_Y_real_1_10; +wire [17:0] sum_Y_imag_1_10; +wire [17:0] sum_Y_real_hold_1_10; +wire [17:0] sum_Y_imag_hold_1_10; +wire [17:0] out_Y_idft_1_10; +reg [17:0] reg_Y_1_10; +wire [17:0] Y_imag_1_11; +wire [17:0] Y_real_1_11; +wire [17:0] sum_Y_real_1_11; +wire [17:0] sum_Y_imag_1_11; +wire [17:0] sum_Y_real_hold_1_11; +wire [17:0] sum_Y_imag_hold_1_11; +wire [17:0] out_Y_idft_1_11; +reg [17:0] reg_Y_1_11; +wire [17:0] Y_imag_1_12; +wire [17:0] Y_real_1_12; +wire [17:0] sum_Y_real_1_12; +wire [17:0] sum_Y_imag_1_12; +wire [17:0] sum_Y_real_hold_1_12; +wire [17:0] sum_Y_imag_hold_1_12; +wire [17:0] out_Y_idft_1_12; +reg [17:0] reg_Y_1_12; +wire [17:0] Y_imag_1_13; +wire [17:0] Y_real_1_13; +wire [17:0] sum_Y_real_1_13; +wire [17:0] sum_Y_imag_1_13; +wire [17:0] sum_Y_real_hold_1_13; +wire [17:0] sum_Y_imag_hold_1_13; +wire [17:0] out_Y_idft_1_13; +reg [17:0] reg_Y_1_13; +wire [17:0] Y_imag_1_14; +wire [17:0] Y_real_1_14; +wire [17:0] sum_Y_real_1_14; +wire [17:0] sum_Y_imag_1_14; +wire [17:0] sum_Y_real_hold_1_14; +wire [17:0] sum_Y_imag_hold_1_14; +wire [17:0] out_Y_idft_1_14; +reg [17:0] reg_Y_1_14; +wire [17:0] Y_imag_1_15; +wire [17:0] Y_real_1_15; +wire [17:0] sum_Y_real_1_15; +wire [17:0] sum_Y_imag_1_15; +wire [17:0] sum_Y_real_hold_1_15; +wire [17:0] sum_Y_imag_hold_1_15; +wire [17:0] out_Y_idft_1_15; +reg [17:0] reg_Y_1_15; +reg reg_o_valid; + +// Enable whenever the reciever is ready +wire enable; +assign enable = i_ready; +c_matrix_vec_mult_core_18_10_16_2_1 c_matrix_vec_mult_core_18_10_16_2_1_inst_bewcfwotsm ( + .clk(clk), + .reset(reset), + .i_ready(i_ready), + .i_valid(i_valid), + .i_X_0(i_X_0), + .i_X_1(i_X_1), + .i_X_2(i_X_2), + .i_X_3(i_X_3), + .i_X_4(i_X_4), + .i_X_5(i_X_5), + .i_X_6(i_X_6), + .i_X_7(i_X_7), + .i_X_8(i_X_8), + .i_X_9(i_X_9), + .i_X_10(i_X_10), + .i_X_11(i_X_11), + .i_X_12(i_X_12), + .i_X_13(i_X_13), + .i_X_14(i_X_14), + .i_X_15(i_X_15), + .i_W_real_0_0(i_W_real_0_0), + .i_W_imag_0_0(i_W_imag_0_0), + .i_W_real_0_1(i_W_real_0_1), + .i_W_imag_0_1(i_W_imag_0_1), + .i_W_real_0_2(i_W_real_0_2), + .i_W_imag_0_2(i_W_imag_0_2), + .i_W_real_0_3(i_W_real_0_3), + .i_W_imag_0_3(i_W_imag_0_3), + .i_W_real_0_4(i_W_real_0_4), + .i_W_imag_0_4(i_W_imag_0_4), + .i_W_real_0_5(i_W_real_0_5), + .i_W_imag_0_5(i_W_imag_0_5), + .i_W_real_0_6(i_W_real_0_6), + .i_W_imag_0_6(i_W_imag_0_6), + .i_W_real_0_7(i_W_real_0_7), + .i_W_imag_0_7(i_W_imag_0_7), + .i_W_real_0_8(i_W_real_0_8), + .i_W_imag_0_8(i_W_imag_0_8), + .i_W_real_1_0(i_W_real_1_0), + .i_W_imag_1_0(i_W_imag_1_0), + .i_W_real_1_1(i_W_real_1_1), + .i_W_imag_1_1(i_W_imag_1_1), + .i_W_real_1_2(i_W_real_1_2), + .i_W_imag_1_2(i_W_imag_1_2), + .i_W_real_1_3(i_W_real_1_3), + .i_W_imag_1_3(i_W_imag_1_3), + .i_W_real_1_4(i_W_real_1_4), + .i_W_imag_1_4(i_W_imag_1_4), + .i_W_real_1_5(i_W_real_1_5), + .i_W_imag_1_5(i_W_imag_1_5), + .i_W_real_1_6(i_W_real_1_6), + .i_W_imag_1_6(i_W_imag_1_6), + .i_W_real_1_7(i_W_real_1_7), + .i_W_imag_1_7(i_W_imag_1_7), + .i_W_real_1_8(i_W_real_1_8), + .i_W_imag_1_8(i_W_imag_1_8), + .o_Y_real_0_0(Y_real_0_0), + .o_Y_imag_0_0(Y_imag_0_0), + .o_Y_real_0_1(Y_real_0_1), + .o_Y_imag_0_1(Y_imag_0_1), + .o_Y_real_0_2(Y_real_0_2), + .o_Y_imag_0_2(Y_imag_0_2), + .o_Y_real_0_3(Y_real_0_3), + .o_Y_imag_0_3(Y_imag_0_3), + .o_Y_real_0_4(Y_real_0_4), + .o_Y_imag_0_4(Y_imag_0_4), + .o_Y_real_0_5(Y_real_0_5), + .o_Y_imag_0_5(Y_imag_0_5), + .o_Y_real_0_6(Y_real_0_6), + .o_Y_imag_0_6(Y_imag_0_6), + .o_Y_real_0_7(Y_real_0_7), + .o_Y_imag_0_7(Y_imag_0_7), + .o_Y_real_0_8(Y_real_0_8), + .o_Y_imag_0_8(Y_imag_0_8), + .o_Y_real_0_9(Y_real_0_9), + .o_Y_imag_0_9(Y_imag_0_9), + .o_Y_real_0_10(Y_real_0_10), + .o_Y_imag_0_10(Y_imag_0_10), + .o_Y_real_0_11(Y_real_0_11), + .o_Y_imag_0_11(Y_imag_0_11), + .o_Y_real_0_12(Y_real_0_12), + .o_Y_imag_0_12(Y_imag_0_12), + .o_Y_real_0_13(Y_real_0_13), + .o_Y_imag_0_13(Y_imag_0_13), + .o_Y_real_0_14(Y_real_0_14), + .o_Y_imag_0_14(Y_imag_0_14), + .o_Y_real_0_15(Y_real_0_15), + .o_Y_imag_0_15(Y_imag_0_15), + .o_Y_real_1_0(Y_real_1_0), + .o_Y_imag_1_0(Y_imag_1_0), + .o_Y_real_1_1(Y_real_1_1), + .o_Y_imag_1_1(Y_imag_1_1), + .o_Y_real_1_2(Y_real_1_2), + .o_Y_imag_1_2(Y_imag_1_2), + .o_Y_real_1_3(Y_real_1_3), + .o_Y_imag_1_3(Y_imag_1_3), + .o_Y_real_1_4(Y_real_1_4), + .o_Y_imag_1_4(Y_imag_1_4), + .o_Y_real_1_5(Y_real_1_5), + .o_Y_imag_1_5(Y_imag_1_5), + .o_Y_real_1_6(Y_real_1_6), + .o_Y_imag_1_6(Y_imag_1_6), + .o_Y_real_1_7(Y_real_1_7), + .o_Y_imag_1_7(Y_imag_1_7), + .o_Y_real_1_8(Y_real_1_8), + .o_Y_imag_1_8(Y_imag_1_8), + .o_Y_real_1_9(Y_real_1_9), + .o_Y_imag_1_9(Y_imag_1_9), + .o_Y_real_1_10(Y_real_1_10), + .o_Y_imag_1_10(Y_imag_1_10), + .o_Y_real_1_11(Y_real_1_11), + .o_Y_imag_1_11(Y_imag_1_11), + .o_Y_real_1_12(Y_real_1_12), + .o_Y_imag_1_12(Y_imag_1_12), + .o_Y_real_1_13(Y_real_1_13), + .o_Y_imag_1_13(Y_imag_1_13), + .o_Y_real_1_14(Y_real_1_14), + .o_Y_imag_1_14(Y_imag_1_14), + .o_Y_real_1_15(Y_real_1_15), + .o_Y_imag_1_15(Y_imag_1_15), + .o_ready(matrix_vec_mult_ready), + .o_valid(matrix_vec_mult_valid) +); + +sum_complex_vector_unit_18_18_16_64 sum_complex_vector_unit_18_18_16_64_inst_ocjmzucwmw ( + .clk(clk), + .clr(reset), + .enable(enable), + .i_valid(matrix_vec_mult_valid), + .i_real_0(Y_real_0_0), + .i_imag_0(Y_imag_0_0), + .o_real_0(sum_Y_real_0_0), + .o_imag_0(sum_Y_imag_0_0), + .i_real_1(Y_real_0_1), + .i_imag_1(Y_imag_0_1), + .o_real_1(sum_Y_real_0_1), + .o_imag_1(sum_Y_imag_0_1), + .i_real_2(Y_real_0_2), + .i_imag_2(Y_imag_0_2), + .o_real_2(sum_Y_real_0_2), + .o_imag_2(sum_Y_imag_0_2), + .i_real_3(Y_real_0_3), + .i_imag_3(Y_imag_0_3), + .o_real_3(sum_Y_real_0_3), + .o_imag_3(sum_Y_imag_0_3), + .i_real_4(Y_real_0_4), + .i_imag_4(Y_imag_0_4), + .o_real_4(sum_Y_real_0_4), + .o_imag_4(sum_Y_imag_0_4), + .i_real_5(Y_real_0_5), + .i_imag_5(Y_imag_0_5), + .o_real_5(sum_Y_real_0_5), + .o_imag_5(sum_Y_imag_0_5), + .i_real_6(Y_real_0_6), + .i_imag_6(Y_imag_0_6), + .o_real_6(sum_Y_real_0_6), + .o_imag_6(sum_Y_imag_0_6), + .i_real_7(Y_real_0_7), + .i_imag_7(Y_imag_0_7), + .o_real_7(sum_Y_real_0_7), + .o_imag_7(sum_Y_imag_0_7), + .i_real_8(Y_real_0_8), + .i_imag_8(Y_imag_0_8), + .o_real_8(sum_Y_real_0_8), + .o_imag_8(sum_Y_imag_0_8), + .i_real_9(Y_real_0_9), + .i_imag_9(Y_imag_0_9), + .o_real_9(sum_Y_real_0_9), + .o_imag_9(sum_Y_imag_0_9), + .i_real_10(Y_real_0_10), + .i_imag_10(Y_imag_0_10), + .o_real_10(sum_Y_real_0_10), + .o_imag_10(sum_Y_imag_0_10), + .i_real_11(Y_real_0_11), + .i_imag_11(Y_imag_0_11), + .o_real_11(sum_Y_real_0_11), + .o_imag_11(sum_Y_imag_0_11), + .i_real_12(Y_real_0_12), + .i_imag_12(Y_imag_0_12), + .o_real_12(sum_Y_real_0_12), + .o_imag_12(sum_Y_imag_0_12), + .i_real_13(Y_real_0_13), + .i_imag_13(Y_imag_0_13), + .o_real_13(sum_Y_real_0_13), + .o_imag_13(sum_Y_imag_0_13), + .i_real_14(Y_real_0_14), + .i_imag_14(Y_imag_0_14), + .o_real_14(sum_Y_real_0_14), + .o_imag_14(sum_Y_imag_0_14), + .i_real_15(Y_real_0_15), + .i_imag_15(Y_imag_0_15), + .o_real_15(sum_Y_real_0_15), + .o_imag_15(sum_Y_imag_0_15), + .o_valid(accum_valid_0) +); + +sum_complex_vector_unit_18_18_16_64 sum_complex_vector_unit_18_18_16_64_inst_bvsgwvhnph ( + .clk(clk), + .clr(reset), + .enable(enable), + .i_valid(matrix_vec_mult_valid), + .i_real_0(Y_real_1_0), + .i_imag_0(Y_imag_1_0), + .o_real_0(sum_Y_real_1_0), + .o_imag_0(sum_Y_imag_1_0), + .i_real_1(Y_real_1_1), + .i_imag_1(Y_imag_1_1), + .o_real_1(sum_Y_real_1_1), + .o_imag_1(sum_Y_imag_1_1), + .i_real_2(Y_real_1_2), + .i_imag_2(Y_imag_1_2), + .o_real_2(sum_Y_real_1_2), + .o_imag_2(sum_Y_imag_1_2), + .i_real_3(Y_real_1_3), + .i_imag_3(Y_imag_1_3), + .o_real_3(sum_Y_real_1_3), + .o_imag_3(sum_Y_imag_1_3), + .i_real_4(Y_real_1_4), + .i_imag_4(Y_imag_1_4), + .o_real_4(sum_Y_real_1_4), + .o_imag_4(sum_Y_imag_1_4), + .i_real_5(Y_real_1_5), + .i_imag_5(Y_imag_1_5), + .o_real_5(sum_Y_real_1_5), + .o_imag_5(sum_Y_imag_1_5), + .i_real_6(Y_real_1_6), + .i_imag_6(Y_imag_1_6), + .o_real_6(sum_Y_real_1_6), + .o_imag_6(sum_Y_imag_1_6), + .i_real_7(Y_real_1_7), + .i_imag_7(Y_imag_1_7), + .o_real_7(sum_Y_real_1_7), + .o_imag_7(sum_Y_imag_1_7), + .i_real_8(Y_real_1_8), + .i_imag_8(Y_imag_1_8), + .o_real_8(sum_Y_real_1_8), + .o_imag_8(sum_Y_imag_1_8), + .i_real_9(Y_real_1_9), + .i_imag_9(Y_imag_1_9), + .o_real_9(sum_Y_real_1_9), + .o_imag_9(sum_Y_imag_1_9), + .i_real_10(Y_real_1_10), + .i_imag_10(Y_imag_1_10), + .o_real_10(sum_Y_real_1_10), + .o_imag_10(sum_Y_imag_1_10), + .i_real_11(Y_real_1_11), + .i_imag_11(Y_imag_1_11), + .o_real_11(sum_Y_real_1_11), + .o_imag_11(sum_Y_imag_1_11), + .i_real_12(Y_real_1_12), + .i_imag_12(Y_imag_1_12), + .o_real_12(sum_Y_real_1_12), + .o_imag_12(sum_Y_imag_1_12), + .i_real_13(Y_real_1_13), + .i_imag_13(Y_imag_1_13), + .o_real_13(sum_Y_real_1_13), + .o_imag_13(sum_Y_imag_1_13), + .i_real_14(Y_real_1_14), + .i_imag_14(Y_imag_1_14), + .o_real_14(sum_Y_real_1_14), + .o_imag_14(sum_Y_imag_1_14), + .i_real_15(Y_real_1_15), + .i_imag_15(Y_imag_1_15), + .o_real_15(sum_Y_real_1_15), + .o_imag_15(sum_Y_imag_1_15), + .o_valid(accum_valid_1) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_ruinxcmmbp_real ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_real_0_0), + .out_0(sum_Y_real_hold_0_0), + .in_1(sum_Y_real_0_1), + .out_1(sum_Y_real_hold_0_1), + .in_2(sum_Y_real_0_2), + .out_2(sum_Y_real_hold_0_2), + .in_3(sum_Y_real_0_3), + .out_3(sum_Y_real_hold_0_3), + .in_4(sum_Y_real_0_4), + .out_4(sum_Y_real_hold_0_4), + .in_5(sum_Y_real_0_5), + .out_5(sum_Y_real_hold_0_5), + .in_6(sum_Y_real_0_6), + .out_6(sum_Y_real_hold_0_6), + .in_7(sum_Y_real_0_7), + .out_7(sum_Y_real_hold_0_7), + .in_8(sum_Y_real_0_8), + .out_8(sum_Y_real_hold_0_8), + .in_9(sum_Y_real_0_9), + .out_9(sum_Y_real_hold_0_9), + .in_10(sum_Y_real_0_10), + .out_10(sum_Y_real_hold_0_10), + .in_11(sum_Y_real_0_11), + .out_11(sum_Y_real_hold_0_11), + .in_12(sum_Y_real_0_12), + .out_12(sum_Y_real_hold_0_12), + .in_13(sum_Y_real_0_13), + .out_13(sum_Y_real_hold_0_13), + .in_14(sum_Y_real_0_14), + .out_14(sum_Y_real_hold_0_14), + .in_15(sum_Y_real_0_15), + .out_15(sum_Y_real_hold_0_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_jfqoyhtwog_imag ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_imag_0_0), + .out_0(sum_Y_imag_hold_0_0), + .in_1(sum_Y_imag_0_1), + .out_1(sum_Y_imag_hold_0_1), + .in_2(sum_Y_imag_0_2), + .out_2(sum_Y_imag_hold_0_2), + .in_3(sum_Y_imag_0_3), + .out_3(sum_Y_imag_hold_0_3), + .in_4(sum_Y_imag_0_4), + .out_4(sum_Y_imag_hold_0_4), + .in_5(sum_Y_imag_0_5), + .out_5(sum_Y_imag_hold_0_5), + .in_6(sum_Y_imag_0_6), + .out_6(sum_Y_imag_hold_0_6), + .in_7(sum_Y_imag_0_7), + .out_7(sum_Y_imag_hold_0_7), + .in_8(sum_Y_imag_0_8), + .out_8(sum_Y_imag_hold_0_8), + .in_9(sum_Y_imag_0_9), + .out_9(sum_Y_imag_hold_0_9), + .in_10(sum_Y_imag_0_10), + .out_10(sum_Y_imag_hold_0_10), + .in_11(sum_Y_imag_0_11), + .out_11(sum_Y_imag_hold_0_11), + .in_12(sum_Y_imag_0_12), + .out_12(sum_Y_imag_hold_0_12), + .in_13(sum_Y_imag_0_13), + .out_13(sum_Y_imag_hold_0_13), + .in_14(sum_Y_imag_0_14), + .out_14(sum_Y_imag_hold_0_14), + .in_15(sum_Y_imag_0_15), + .out_15(sum_Y_imag_hold_0_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_swwkwhakzq_real ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_real_1_0), + .out_0(sum_Y_real_hold_1_0), + .in_1(sum_Y_real_1_1), + .out_1(sum_Y_real_hold_1_1), + .in_2(sum_Y_real_1_2), + .out_2(sum_Y_real_hold_1_2), + .in_3(sum_Y_real_1_3), + .out_3(sum_Y_real_hold_1_3), + .in_4(sum_Y_real_1_4), + .out_4(sum_Y_real_hold_1_4), + .in_5(sum_Y_real_1_5), + .out_5(sum_Y_real_hold_1_5), + .in_6(sum_Y_real_1_6), + .out_6(sum_Y_real_hold_1_6), + .in_7(sum_Y_real_1_7), + .out_7(sum_Y_real_hold_1_7), + .in_8(sum_Y_real_1_8), + .out_8(sum_Y_real_hold_1_8), + .in_9(sum_Y_real_1_9), + .out_9(sum_Y_real_hold_1_9), + .in_10(sum_Y_real_1_10), + .out_10(sum_Y_real_hold_1_10), + .in_11(sum_Y_real_1_11), + .out_11(sum_Y_real_hold_1_11), + .in_12(sum_Y_real_1_12), + .out_12(sum_Y_real_hold_1_12), + .in_13(sum_Y_real_1_13), + .out_13(sum_Y_real_hold_1_13), + .in_14(sum_Y_real_1_14), + .out_14(sum_Y_real_hold_1_14), + .in_15(sum_Y_real_1_15), + .out_15(sum_Y_real_hold_1_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_jdsdwwrskw_imag ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_imag_1_0), + .out_0(sum_Y_imag_hold_1_0), + .in_1(sum_Y_imag_1_1), + .out_1(sum_Y_imag_hold_1_1), + .in_2(sum_Y_imag_1_2), + .out_2(sum_Y_imag_hold_1_2), + .in_3(sum_Y_imag_1_3), + .out_3(sum_Y_imag_hold_1_3), + .in_4(sum_Y_imag_1_4), + .out_4(sum_Y_imag_hold_1_4), + .in_5(sum_Y_imag_1_5), + .out_5(sum_Y_imag_hold_1_5), + .in_6(sum_Y_imag_1_6), + .out_6(sum_Y_imag_hold_1_6), + .in_7(sum_Y_imag_1_7), + .out_7(sum_Y_imag_hold_1_7), + .in_8(sum_Y_imag_1_8), + .out_8(sum_Y_imag_hold_1_8), + .in_9(sum_Y_imag_1_9), + .out_9(sum_Y_imag_hold_1_9), + .in_10(sum_Y_imag_1_10), + .out_10(sum_Y_imag_hold_1_10), + .in_11(sum_Y_imag_1_11), + .out_11(sum_Y_imag_hold_1_11), + .in_12(sum_Y_imag_1_12), + .out_12(sum_Y_imag_hold_1_12), + .in_13(sum_Y_imag_1_13), + .out_13(sum_Y_imag_hold_1_13), + .in_14(sum_Y_imag_1_14), + .out_14(sum_Y_imag_hold_1_14), + .in_15(sum_Y_imag_1_15), + .out_15(sum_Y_imag_hold_1_15), + .reset(reset) +); + +idft_16_top_18 idft_16_top_18_inst_sdazdboemb ( + .clk(clk), + .reset(reset), + .next(accum_valid_0), + .X0(sum_Y_real_hold_0_0), + .Y0(out_Y_idft_0_0), + .X1(sum_Y_imag_hold_0_0), + .Y1(), + .X2(sum_Y_real_hold_0_1), + .Y2(out_Y_idft_0_1), + .X3(sum_Y_imag_hold_0_1), + .Y3(), + .X4(sum_Y_real_hold_0_2), + .Y4(out_Y_idft_0_2), + .X5(sum_Y_imag_hold_0_2), + .Y5(), + .X6(sum_Y_real_hold_0_3), + .Y6(out_Y_idft_0_3), + .X7(sum_Y_imag_hold_0_3), + .Y7(), + .X8(sum_Y_real_hold_0_4), + .Y8(out_Y_idft_0_4), + .X9(sum_Y_imag_hold_0_4), + .Y9(), + .X10(sum_Y_real_hold_0_5), + .Y10(out_Y_idft_0_5), + .X11(sum_Y_imag_hold_0_5), + .Y11(), + .X12(sum_Y_real_hold_0_6), + .Y12(out_Y_idft_0_6), + .X13(sum_Y_imag_hold_0_6), + .Y13(), + .X14(sum_Y_real_hold_0_7), + .Y14(out_Y_idft_0_7), + .X15(sum_Y_imag_hold_0_7), + .Y15(), + .X16(sum_Y_real_hold_0_8), + .Y16(out_Y_idft_0_8), + .X17(sum_Y_imag_hold_0_8), + .Y17(), + .X18(sum_Y_real_hold_0_9), + .Y18(out_Y_idft_0_9), + .X19(sum_Y_imag_hold_0_9), + .Y19(), + .X20(sum_Y_real_hold_0_10), + .Y20(out_Y_idft_0_10), + .X21(sum_Y_imag_hold_0_10), + .Y21(), + .X22(sum_Y_real_hold_0_11), + .Y22(out_Y_idft_0_11), + .X23(sum_Y_imag_hold_0_11), + .Y23(), + .X24(sum_Y_real_hold_0_12), + .Y24(out_Y_idft_0_12), + .X25(sum_Y_imag_hold_0_12), + .Y25(), + .X26(sum_Y_real_hold_0_13), + .Y26(out_Y_idft_0_13), + .X27(sum_Y_imag_hold_0_13), + .Y27(), + .X28(sum_Y_real_hold_0_14), + .Y28(out_Y_idft_0_14), + .X29(sum_Y_imag_hold_0_14), + .Y29(), + .X30(sum_Y_real_hold_0_15), + .Y30(out_Y_idft_0_15), + .X31(sum_Y_imag_hold_0_15), + .Y31(), + .next_out(idft_next_out_0) +); + +idft_16_top_18 idft_16_top_18_inst_nelovmsmkg ( + .clk(clk), + .reset(reset), + .next(accum_valid_1), + .X0(sum_Y_real_hold_1_0), + .Y0(out_Y_idft_1_0), + .X1(sum_Y_imag_hold_1_0), + .Y1(), + .X2(sum_Y_real_hold_1_1), + .Y2(out_Y_idft_1_1), + .X3(sum_Y_imag_hold_1_1), + .Y3(), + .X4(sum_Y_real_hold_1_2), + .Y4(out_Y_idft_1_2), + .X5(sum_Y_imag_hold_1_2), + .Y5(), + .X6(sum_Y_real_hold_1_3), + .Y6(out_Y_idft_1_3), + .X7(sum_Y_imag_hold_1_3), + .Y7(), + .X8(sum_Y_real_hold_1_4), + .Y8(out_Y_idft_1_4), + .X9(sum_Y_imag_hold_1_4), + .Y9(), + .X10(sum_Y_real_hold_1_5), + .Y10(out_Y_idft_1_5), + .X11(sum_Y_imag_hold_1_5), + .Y11(), + .X12(sum_Y_real_hold_1_6), + .Y12(out_Y_idft_1_6), + .X13(sum_Y_imag_hold_1_6), + .Y13(), + .X14(sum_Y_real_hold_1_7), + .Y14(out_Y_idft_1_7), + .X15(sum_Y_imag_hold_1_7), + .Y15(), + .X16(sum_Y_real_hold_1_8), + .Y16(out_Y_idft_1_8), + .X17(sum_Y_imag_hold_1_8), + .Y17(), + .X18(sum_Y_real_hold_1_9), + .Y18(out_Y_idft_1_9), + .X19(sum_Y_imag_hold_1_9), + .Y19(), + .X20(sum_Y_real_hold_1_10), + .Y20(out_Y_idft_1_10), + .X21(sum_Y_imag_hold_1_10), + .Y21(), + .X22(sum_Y_real_hold_1_11), + .Y22(out_Y_idft_1_11), + .X23(sum_Y_imag_hold_1_11), + .Y23(), + .X24(sum_Y_real_hold_1_12), + .Y24(out_Y_idft_1_12), + .X25(sum_Y_imag_hold_1_12), + .Y25(), + .X26(sum_Y_real_hold_1_13), + .Y26(out_Y_idft_1_13), + .X27(sum_Y_imag_hold_1_13), + .Y27(), + .X28(sum_Y_real_hold_1_14), + .Y28(out_Y_idft_1_14), + .X29(sum_Y_imag_hold_1_14), + .Y29(), + .X30(sum_Y_real_hold_1_15), + .Y30(out_Y_idft_1_15), + .X31(sum_Y_imag_hold_1_15), + .Y31(), + .next_out(idft_next_out_1) +); + +always @ (posedge clk) begin + if (reset) begin + reg_Y_0_0 <= 0; + reg_Y_0_1 <= 0; + reg_Y_0_2 <= 0; + reg_Y_0_3 <= 0; + reg_Y_0_4 <= 0; + reg_Y_0_5 <= 0; + reg_Y_0_6 <= 0; + reg_Y_0_7 <= 0; + reg_Y_0_8 <= 0; + reg_Y_0_9 <= 0; + reg_Y_0_10 <= 0; + reg_Y_0_11 <= 0; + reg_Y_0_12 <= 0; + reg_Y_0_13 <= 0; + reg_Y_0_14 <= 0; + reg_Y_0_15 <= 0; + reg_Y_1_0 <= 0; + reg_Y_1_1 <= 0; + reg_Y_1_2 <= 0; + reg_Y_1_3 <= 0; + reg_Y_1_4 <= 0; + reg_Y_1_5 <= 0; + reg_Y_1_6 <= 0; + reg_Y_1_7 <= 0; + reg_Y_1_8 <= 0; + reg_Y_1_9 <= 0; + reg_Y_1_10 <= 0; + reg_Y_1_11 <= 0; + reg_Y_1_12 <= 0; + reg_Y_1_13 <= 0; + reg_Y_1_14 <= 0; + reg_Y_1_15 <= 0; + idft_out_valid <= 1'b0; + reg_o_valid <= 1'b0; + end else if (enable) begin + reg_Y_0_0 <= (out_Y_idft_0_0 >>> 4); + reg_Y_0_1 <= (out_Y_idft_0_1 >>> 4); + reg_Y_0_2 <= (out_Y_idft_0_2 >>> 4); + reg_Y_0_3 <= (out_Y_idft_0_3 >>> 4); + reg_Y_0_4 <= (out_Y_idft_0_4 >>> 4); + reg_Y_0_5 <= (out_Y_idft_0_5 >>> 4); + reg_Y_0_6 <= (out_Y_idft_0_6 >>> 4); + reg_Y_0_7 <= (out_Y_idft_0_7 >>> 4); + reg_Y_0_8 <= (out_Y_idft_0_8 >>> 4); + reg_Y_0_9 <= (out_Y_idft_0_9 >>> 4); + reg_Y_0_10 <= (out_Y_idft_0_10 >>> 4); + reg_Y_0_11 <= (out_Y_idft_0_11 >>> 4); + reg_Y_0_12 <= (out_Y_idft_0_12 >>> 4); + reg_Y_0_13 <= (out_Y_idft_0_13 >>> 4); + reg_Y_0_14 <= (out_Y_idft_0_14 >>> 4); + reg_Y_0_15 <= (out_Y_idft_0_15 >>> 4); + reg_Y_1_0 <= (out_Y_idft_1_0 >>> 4); + reg_Y_1_1 <= (out_Y_idft_1_1 >>> 4); + reg_Y_1_2 <= (out_Y_idft_1_2 >>> 4); + reg_Y_1_3 <= (out_Y_idft_1_3 >>> 4); + reg_Y_1_4 <= (out_Y_idft_1_4 >>> 4); + reg_Y_1_5 <= (out_Y_idft_1_5 >>> 4); + reg_Y_1_6 <= (out_Y_idft_1_6 >>> 4); + reg_Y_1_7 <= (out_Y_idft_1_7 >>> 4); + reg_Y_1_8 <= (out_Y_idft_1_8 >>> 4); + reg_Y_1_9 <= (out_Y_idft_1_9 >>> 4); + reg_Y_1_10 <= (out_Y_idft_1_10 >>> 4); + reg_Y_1_11 <= (out_Y_idft_1_11 >>> 4); + reg_Y_1_12 <= (out_Y_idft_1_12 >>> 4); + reg_Y_1_13 <= (out_Y_idft_1_13 >>> 4); + reg_Y_1_14 <= (out_Y_idft_1_14 >>> 4); + reg_Y_1_15 <= (out_Y_idft_1_15 >>> 4); + idft_out_valid <= idft_next_out_0; + reg_o_valid <= idft_out_valid; + end +end + +assign o_valid = enable & reg_o_valid; +assign o_ready = matrix_vec_mult_ready; +assign o_Y_0_0 = reg_Y_0_0; +assign o_Y_0_1 = reg_Y_0_1; +assign o_Y_0_2 = reg_Y_0_2; +assign o_Y_0_3 = reg_Y_0_3; +assign o_Y_0_4 = reg_Y_0_4; +assign o_Y_0_5 = reg_Y_0_5; +assign o_Y_0_6 = reg_Y_0_6; +assign o_Y_0_7 = reg_Y_0_7; +assign o_Y_0_8 = reg_Y_0_8; +assign o_Y_0_9 = reg_Y_0_9; +assign o_Y_0_10 = reg_Y_0_10; +assign o_Y_0_11 = reg_Y_0_11; +assign o_Y_0_12 = reg_Y_0_12; +assign o_Y_0_13 = reg_Y_0_13; +assign o_Y_0_14 = reg_Y_0_14; +assign o_Y_0_15 = reg_Y_0_15; +assign o_Y_1_0 = reg_Y_1_0; +assign o_Y_1_1 = reg_Y_1_1; +assign o_Y_1_2 = reg_Y_1_2; +assign o_Y_1_3 = reg_Y_1_3; +assign o_Y_1_4 = reg_Y_1_4; +assign o_Y_1_5 = reg_Y_1_5; +assign o_Y_1_6 = reg_Y_1_6; +assign o_Y_1_7 = reg_Y_1_7; +assign o_Y_1_8 = reg_Y_1_8; +assign o_Y_1_9 = reg_Y_1_9; +assign o_Y_1_10 = reg_Y_1_10; +assign o_Y_1_11 = reg_Y_1_11; +assign o_Y_1_12 = reg_Y_1_12; +assign o_Y_1_13 = reg_Y_1_13; +assign o_Y_1_14 = reg_Y_1_14; +assign o_Y_1_15 = reg_Y_1_15; + +endmodule + +module sum_complex_vector_unit_18_18_16_64 ( + input clk, + input clr, + input i_valid, + input enable, + input [17:0] i_real_0, + input [17:0] i_imag_0, + output [17:0] o_real_0, + output [17:0] o_imag_0, + input [17:0] i_real_1, + input [17:0] i_imag_1, + output [17:0] o_real_1, + output [17:0] o_imag_1, + input [17:0] i_real_2, + input [17:0] i_imag_2, + output [17:0] o_real_2, + output [17:0] o_imag_2, + input [17:0] i_real_3, + input [17:0] i_imag_3, + output [17:0] o_real_3, + output [17:0] o_imag_3, + input [17:0] i_real_4, + input [17:0] i_imag_4, + output [17:0] o_real_4, + output [17:0] o_imag_4, + input [17:0] i_real_5, + input [17:0] i_imag_5, + output [17:0] o_real_5, + output [17:0] o_imag_5, + input [17:0] i_real_6, + input [17:0] i_imag_6, + output [17:0] o_real_6, + output [17:0] o_imag_6, + input [17:0] i_real_7, + input [17:0] i_imag_7, + output [17:0] o_real_7, + output [17:0] o_imag_7, + input [17:0] i_real_8, + input [17:0] i_imag_8, + output [17:0] o_real_8, + output [17:0] o_imag_8, + input [17:0] i_real_9, + input [17:0] i_imag_9, + output [17:0] o_real_9, + output [17:0] o_imag_9, + input [17:0] i_real_10, + input [17:0] i_imag_10, + output [17:0] o_real_10, + output [17:0] o_imag_10, + input [17:0] i_real_11, + input [17:0] i_imag_11, + output [17:0] o_real_11, + output [17:0] o_imag_11, + input [17:0] i_real_12, + input [17:0] i_imag_12, + output [17:0] o_real_12, + output [17:0] o_imag_12, + input [17:0] i_real_13, + input [17:0] i_imag_13, + output [17:0] o_real_13, + output [17:0] o_imag_13, + input [17:0] i_real_14, + input [17:0] i_imag_14, + output [17:0] o_real_14, + output [17:0] o_imag_14, + input [17:0] i_real_15, + input [17:0] i_imag_15, + output [17:0] o_real_15, + output [17:0] o_imag_15, + output o_valid +); + +reg [17:0] sum_real_0; +reg [17:0] sum_imag_0; +reg [17:0] sum_real_1; +reg [17:0] sum_imag_1; +reg [17:0] sum_real_2; +reg [17:0] sum_imag_2; +reg [17:0] sum_real_3; +reg [17:0] sum_imag_3; +reg [17:0] sum_real_4; +reg [17:0] sum_imag_4; +reg [17:0] sum_real_5; +reg [17:0] sum_imag_5; +reg [17:0] sum_real_6; +reg [17:0] sum_imag_6; +reg [17:0] sum_real_7; +reg [17:0] sum_imag_7; +reg [17:0] sum_real_8; +reg [17:0] sum_imag_8; +reg [17:0] sum_real_9; +reg [17:0] sum_imag_9; +reg [17:0] sum_real_10; +reg [17:0] sum_imag_10; +reg [17:0] sum_real_11; +reg [17:0] sum_imag_11; +reg [17:0] sum_real_12; +reg [17:0] sum_imag_12; +reg [17:0] sum_real_13; +reg [17:0] sum_imag_13; +reg [17:0] sum_real_14; +reg [17:0] sum_imag_14; +reg [17:0] sum_real_15; +reg [17:0] sum_imag_15; +reg reg_i_valid; + +// Count the number data in accumulation +reg [13:0] counter; +wire counter_full; +always @ (posedge clk) begin + if (clr) begin + sum_real_0 <= 0; + sum_imag_0 <= 0; + sum_real_1 <= 0; + sum_imag_1 <= 0; + sum_real_2 <= 0; + sum_imag_2 <= 0; + sum_real_3 <= 0; + sum_imag_3 <= 0; + sum_real_4 <= 0; + sum_imag_4 <= 0; + sum_real_5 <= 0; + sum_imag_5 <= 0; + sum_real_6 <= 0; + sum_imag_6 <= 0; + sum_real_7 <= 0; + sum_imag_7 <= 0; + sum_real_8 <= 0; + sum_imag_8 <= 0; + sum_real_9 <= 0; + sum_imag_9 <= 0; + sum_real_10 <= 0; + sum_imag_10 <= 0; + sum_real_11 <= 0; + sum_imag_11 <= 0; + sum_real_12 <= 0; + sum_imag_12 <= 0; + sum_real_13 <= 0; + sum_imag_13 <= 0; + sum_real_14 <= 0; + sum_imag_14 <= 0; + sum_real_15 <= 0; + sum_imag_15 <= 0; + counter <= 14'd0; + reg_i_valid <= 1'b0; + end else if (enable) begin + reg_i_valid <= i_valid; + // Accumulate the number only when data is valid + if (i_valid) begin + if (counter == 64) + counter <= 1; + else + counter <= counter + 1'b1; + + if (counter == 64) begin + sum_real_0 <= i_real_0; + sum_imag_0 <= i_imag_0; + sum_real_1 <= i_real_1; + sum_imag_1 <= i_imag_1; + sum_real_2 <= i_real_2; + sum_imag_2 <= i_imag_2; + sum_real_3 <= i_real_3; + sum_imag_3 <= i_imag_3; + sum_real_4 <= i_real_4; + sum_imag_4 <= i_imag_4; + sum_real_5 <= i_real_5; + sum_imag_5 <= i_imag_5; + sum_real_6 <= i_real_6; + sum_imag_6 <= i_imag_6; + sum_real_7 <= i_real_7; + sum_imag_7 <= i_imag_7; + sum_real_8 <= i_real_8; + sum_imag_8 <= i_imag_8; + sum_real_9 <= i_real_9; + sum_imag_9 <= i_imag_9; + sum_real_10 <= i_real_10; + sum_imag_10 <= i_imag_10; + sum_real_11 <= i_real_11; + sum_imag_11 <= i_imag_11; + sum_real_12 <= i_real_12; + sum_imag_12 <= i_imag_12; + sum_real_13 <= i_real_13; + sum_imag_13 <= i_imag_13; + sum_real_14 <= i_real_14; + sum_imag_14 <= i_imag_14; + sum_real_15 <= i_real_15; + sum_imag_15 <= i_imag_15; + end else begin + sum_real_0 <= sum_real_0 + i_real_0; + sum_imag_0 <= sum_imag_0 + i_imag_0; + sum_real_1 <= sum_real_1 + i_real_1; + sum_imag_1 <= sum_imag_1 + i_imag_1; + sum_real_2 <= sum_real_2 + i_real_2; + sum_imag_2 <= sum_imag_2 + i_imag_2; + sum_real_3 <= sum_real_3 + i_real_3; + sum_imag_3 <= sum_imag_3 + i_imag_3; + sum_real_4 <= sum_real_4 + i_real_4; + sum_imag_4 <= sum_imag_4 + i_imag_4; + sum_real_5 <= sum_real_5 + i_real_5; + sum_imag_5 <= sum_imag_5 + i_imag_5; + sum_real_6 <= sum_real_6 + i_real_6; + sum_imag_6 <= sum_imag_6 + i_imag_6; + sum_real_7 <= sum_real_7 + i_real_7; + sum_imag_7 <= sum_imag_7 + i_imag_7; + sum_real_8 <= sum_real_8 + i_real_8; + sum_imag_8 <= sum_imag_8 + i_imag_8; + sum_real_9 <= sum_real_9 + i_real_9; + sum_imag_9 <= sum_imag_9 + i_imag_9; + sum_real_10 <= sum_real_10 + i_real_10; + sum_imag_10 <= sum_imag_10 + i_imag_10; + sum_real_11 <= sum_real_11 + i_real_11; + sum_imag_11 <= sum_imag_11 + i_imag_11; + sum_real_12 <= sum_real_12 + i_real_12; + sum_imag_12 <= sum_imag_12 + i_imag_12; + sum_real_13 <= sum_real_13 + i_real_13; + sum_imag_13 <= sum_imag_13 + i_imag_13; + sum_real_14 <= sum_real_14 + i_real_14; + sum_imag_14 <= sum_imag_14 + i_imag_14; + sum_real_15 <= sum_real_15 + i_real_15; + sum_imag_15 <= sum_imag_15 + i_imag_15; + end + end + end +end + +assign counter_full = (counter == 64); +assign o_real_0 = sum_real_0; +assign o_imag_0 = sum_imag_0; +assign o_real_1 = sum_real_1; +assign o_imag_1 = sum_imag_1; +assign o_real_2 = sum_real_2; +assign o_imag_2 = sum_imag_2; +assign o_real_3 = sum_real_3; +assign o_imag_3 = sum_imag_3; +assign o_real_4 = sum_real_4; +assign o_imag_4 = sum_imag_4; +assign o_real_5 = sum_real_5; +assign o_imag_5 = sum_imag_5; +assign o_real_6 = sum_real_6; +assign o_imag_6 = sum_imag_6; +assign o_real_7 = sum_real_7; +assign o_imag_7 = sum_imag_7; +assign o_real_8 = sum_real_8; +assign o_imag_8 = sum_imag_8; +assign o_real_9 = sum_real_9; +assign o_imag_9 = sum_imag_9; +assign o_real_10 = sum_real_10; +assign o_imag_10 = sum_imag_10; +assign o_real_11 = sum_real_11; +assign o_imag_11 = sum_imag_11; +assign o_real_12 = sum_real_12; +assign o_imag_12 = sum_imag_12; +assign o_real_13 = sum_real_13; +assign o_imag_13 = sum_imag_13; +assign o_real_14 = sum_real_14; +assign o_imag_14 = sum_imag_14; +assign o_real_15 = sum_real_15; +assign o_imag_15 = sum_imag_15; +assign o_valid = counter_full & reg_i_valid; + +endmodule + +module stage3_X_Y_buffer_18_16_2_10_32_64 ( + input clk, + input reset, + input i_X_valid, + input i_Y_valid, + input feed_start, + input [17:0] i_X_data_0, + input [17:0] i_Y_data_0, + output [17:0] o_data_0, + input [17:0] i_X_data_1, + input [17:0] i_Y_data_1, + output [17:0] o_data_1, + input [17:0] i_X_data_2, + input [17:0] i_Y_data_2, + output [17:0] o_data_2, + input [17:0] i_X_data_3, + input [17:0] i_Y_data_3, + output [17:0] o_data_3, + input [17:0] i_X_data_4, + input [17:0] i_Y_data_4, + output [17:0] o_data_4, + input [17:0] i_X_data_5, + input [17:0] i_Y_data_5, + output [17:0] o_data_5, + input [17:0] i_X_data_6, + input [17:0] i_Y_data_6, + output [17:0] o_data_6, + input [17:0] i_X_data_7, + input [17:0] i_Y_data_7, + output [17:0] o_data_7, + input [17:0] i_X_data_8, + input [17:0] i_Y_data_8, + output [17:0] o_data_8, + input [17:0] i_X_data_9, + input [17:0] i_Y_data_9, + output [17:0] o_data_9, + input [17:0] i_X_data_10, + input [17:0] i_Y_data_10, + output [17:0] o_data_10, + input [17:0] i_X_data_11, + input [17:0] i_Y_data_11, + output [17:0] o_data_11, + input [17:0] i_X_data_12, + input [17:0] i_Y_data_12, + output [17:0] o_data_12, + input [17:0] i_X_data_13, + input [17:0] i_Y_data_13, + output [17:0] o_data_13, + input [17:0] i_X_data_14, + input [17:0] i_Y_data_14, + output [17:0] o_data_14, + input [17:0] i_X_data_15, + input [17:0] i_Y_data_15, + output [17:0] o_data_15, + output o_valid, + output o_ready +); + +reg reg_feed_start; +reg [17:0] i_data_0; +reg [17:0] i_data_1; +reg [17:0] i_data_2; +reg [17:0] i_data_3; +reg [17:0] i_data_4; +reg [17:0] i_data_5; +reg [17:0] i_data_6; +reg [17:0] i_data_7; +reg [17:0] i_data_8; +reg [17:0] i_data_9; +reg [17:0] i_data_10; +reg [17:0] i_data_11; +reg [17:0] i_data_12; +reg [17:0] i_data_13; +reg [17:0] i_data_14; +reg [17:0] i_data_15; +wire [287:0] packed_o_data; +wire [287:0] packed_data; +reg wen; +wire ready_to_accept_new_X; +wire [13:0] input_index_counter; +assign ready_to_accept_new_X = (input_index_counter >= 32); +assign o_ready = ready_to_accept_new_X; +always @ (*) begin + if(ready_to_accept_new_X) begin + wen <= i_X_valid; + i_data_0 <= i_X_data_0; + i_data_1 <= i_X_data_1; + i_data_2 <= i_X_data_2; + i_data_3 <= i_X_data_3; + i_data_4 <= i_X_data_4; + i_data_5 <= i_X_data_5; + i_data_6 <= i_X_data_6; + i_data_7 <= i_X_data_7; + i_data_8 <= i_X_data_8; + i_data_9 <= i_X_data_9; + i_data_10 <= i_X_data_10; + i_data_11 <= i_X_data_11; + i_data_12 <= i_X_data_12; + i_data_13 <= i_X_data_13; + i_data_14 <= i_X_data_14; + i_data_15 <= i_X_data_15; + end else begin + wen <= i_Y_valid; + i_data_0 <= i_Y_data_0; + i_data_1 <= i_Y_data_1; + i_data_2 <= i_Y_data_2; + i_data_3 <= i_Y_data_3; + i_data_4 <= i_Y_data_4; + i_data_5 <= i_Y_data_5; + i_data_6 <= i_Y_data_6; + i_data_7 <= i_Y_data_7; + i_data_8 <= i_Y_data_8; + i_data_9 <= i_Y_data_9; + i_data_10 <= i_Y_data_10; + i_data_11 <= i_Y_data_11; + i_data_12 <= i_Y_data_12; + i_data_13 <= i_Y_data_13; + i_data_14 <= i_Y_data_14; + i_data_15 <= i_Y_data_15; + end +end + +assign o_data_0 = packed_o_data[17:0]; +assign packed_data[17:0] = i_data_0; +assign o_data_1 = packed_o_data[35:18]; +assign packed_data[35:18] = i_data_1; +assign o_data_2 = packed_o_data[53:36]; +assign packed_data[53:36] = i_data_2; +assign o_data_3 = packed_o_data[71:54]; +assign packed_data[71:54] = i_data_3; +assign o_data_4 = packed_o_data[89:72]; +assign packed_data[89:72] = i_data_4; +assign o_data_5 = packed_o_data[107:90]; +assign packed_data[107:90] = i_data_5; +assign o_data_6 = packed_o_data[125:108]; +assign packed_data[125:108] = i_data_6; +assign o_data_7 = packed_o_data[143:126]; +assign packed_data[143:126] = i_data_7; +assign o_data_8 = packed_o_data[161:144]; +assign packed_data[161:144] = i_data_8; +assign o_data_9 = packed_o_data[179:162]; +assign packed_data[179:162] = i_data_9; +assign o_data_10 = packed_o_data[197:180]; +assign packed_data[197:180] = i_data_10; +assign o_data_11 = packed_o_data[215:198]; +assign packed_data[215:198] = i_data_11; +assign o_data_12 = packed_o_data[233:216]; +assign packed_data[233:216] = i_data_12; +assign o_data_13 = packed_o_data[251:234]; +assign packed_data[251:234] = i_data_13; +assign o_data_14 = packed_o_data[269:252]; +assign packed_data[269:252] = i_data_14; +assign o_data_15 = packed_o_data[287:270]; +assign packed_data[287:270] = i_data_15; +counter_41_1_32 counter_41_1_32_inst_buxhkmtxka ( + .clk(clk), + .reset(reset), + .ena(wen), + .count(input_index_counter) +); + +wire [13:0] output_index_counter; +reg en_output_counter; +counter_41_1 counter_41_1_inst_kkhevwiism ( + .clk(clk), + .reset(reset), + .ena(en_output_counter), + .count(output_index_counter) +); + +wire incr_loop_index; +assign incr_loop_index = (output_index_counter == 41 && en_output_counter); +reg output_finish; +wire [13:0] loop_counter; +counter_31_1 counter_31_1_inst_loop ( + .clk(clk), + .reset(reset), + .ena(incr_loop_index), + .count(loop_counter) +); + +ram_18_0_42 ram_18_0_42_inst_bpgzqfbuxt ( + .clk(clk), + .waddr(input_index_counter), + .wdata(packed_data), + .wen(wen), + .raddr(output_index_counter), + .q(packed_o_data) +); + +shift_register_unit_1_2 shift_register_unit_1_2_inst_saguvbckyr ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .in(en_output_counter), + .out(o_valid) +); + +always @ (posedge clk) begin + if (reset) begin + en_output_counter <= 1'b0; + output_finish <= 1'b0; + reg_feed_start <= 1'b0; + end else begin + en_output_counter <= (reg_feed_start && ~en_output_counter && ~output_finish); + if(feed_start) + reg_feed_start <= 1'b1; + else if (output_finish) + reg_feed_start <= 1'b0; + if ((loop_counter == 31) + &&(output_index_counter == 41) + && en_output_counter) + output_finish <= 1'b1; + else if (loop_counter == 0 && wen) + output_finish <= 1'b0; + end +end + +endmodule + +module counter_41_1_32 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 32; + end else if (ena) begin + if((count + 14'd1) <= 41) begin + count <= count + 14'd1; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module counter_31_1 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd1) <= 31) begin + count <= count + 14'd1; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module ram_18_0_42 ( + input clk, + input [4:0] waddr, + input [17:0] wdata, + input wen, + input [4:0] raddr, + output [17:0] q +); + +wire [17:0] rd_dummy_signal; +wire [17:0] wr_dummy_signal; +assign rd_dummy_signal = 0; + +dpram # (.AWIDTH(5), .DWIDTH(18), .NUM_WORDS(1<<5)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(q), + .clk(clk) +); +endmodule + +module shift_register_unit_1_2 ( + input clk, + input reset, + input enable, + input [0:0] in, + output [0:0] out +); + +reg [0:0] shift_registers_0; +reg [0:0] shift_registers_1; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 1'd0; + shift_registers_1 <= 1'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + end +end + +assign out = shift_registers_1; + +endmodule + diff --git a/designs/koios/clstm_like.medium/clstm_random.sv b/designs/koios/clstm_like.medium/clstm_random.sv new file mode 100644 index 000000000..5a62d5b27 --- /dev/null +++ b/designs/koios/clstm_like.medium/clstm_random.sv @@ -0,0 +1,119 @@ +/* +Random inputs to clstm +*/ + +`include "../../random_number_generator.sv" + +module clstm_random( + input logic clk, + input logic rst, + input logic [7:0] wen_stage1, + input logic [6:0] wen_stage2, + input logic [1:0] wen_stage3, + input logic i_ready, + input logic i_valid, + input logic start_compute, + output logic o_valid, + output logic o_ready, + output logic [17:0] data, + input logic [1:0] data_sel0, + input logic [3:0] data_sel1 +); + +logic [161:0] wdata_stage1; +RandomNumberGenerator #(162, 0) rng1 ( + .clk(clk), + .reset(rst), + .random_number(wdata_stage1) +); + +logic [287:0] wdata_stage2; +RandomNumberGenerator #(288, 1) rng2 ( + .clk(clk), + .reset(rst), + .random_number(wdata_stage2) +); + +logic [161:0] wdata_stage3; +RandomNumberGenerator #(162, 3) rng3 ( + .clk(clk), + .reset(rst), + .random_number(wdata_stage3) +); + +logic [17:0] i_X_data [15:0]; +generate + genvar i; + for (i = 0; i < 16; i = i + 1) begin: gen_X_data + RandomNumberGenerator #(18, i) rng_X_data ( + .clk(clk), + .reset(rst), + .random_number(i_X_data[i]) + ); + end +endgenerate + +logic [17:0] o_sel [1:0][15:0]; +assign data = o_sel[data_sel0][data_sel1[3:0]]; + +C_LSTM_datapath ( + clk, + rst, + wdata_stage1, + wen_stage1, + wdata_stage2, + wen_stage2, + wdata_stage3, + wen_stage3, + i_X_data[0], + i_X_data[1], + i_X_data[2], + i_X_data[3], + i_X_data[4], + i_X_data[5], + i_X_data[6], + i_X_data[7], + i_X_data[8], + i_X_data[9], + i_X_data[10], + i_X_data[11], + i_X_data[12], + i_X_data[13], + i_X_data[14], + i_X_data[15], + o_sel[0][0], + o_sel[0][1], + o_sel[0][2], + o_sel[0][3], + o_sel[0][4], + o_sel[0][5], + o_sel[0][6], + o_sel[0][7], + o_sel[0][8], + o_sel[0][9], + o_sel[0][10], + o_sel[0][11], + o_sel[0][12], + o_sel[0][13], + o_sel[0][14], + o_sel[0][15], + o_sel[1][0], + o_sel[1][1], + o_sel[1][2], + o_sel[1][3], + o_sel[1][4], + o_sel[1][5], + o_sel[1][6], + o_sel[1][7], + o_sel[1][8], + o_sel[1][9], + o_sel[1][10], + o_sel[1][11], + o_sel[1][12], + o_sel[1][13], + o_sel[1][14], + o_sel[1][15] +); + + +endmodule \ No newline at end of file diff --git a/designs/koios/clstm_like.medium/design.yaml b/designs/koios/clstm_like.medium/design.yaml new file mode 100644 index 000000000..d77f8a1d3 --- /dev/null +++ b/designs/koios/clstm_like.medium/design.yaml @@ -0,0 +1 @@ +top: clstm_random \ No newline at end of file diff --git a/designs/koios/clstm_like.small/clstm_like.small.v b/designs/koios/clstm_like.small/clstm_like.small.v new file mode 100644 index 000000000..6602f723a --- /dev/null +++ b/designs/koios/clstm_like.small/clstm_like.small.v @@ -0,0 +1,17107 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Andrew Boutros +////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +//An accelerator overlay for LSTMs based on the C-LSTM paper: +//S. Wang et al., “C-LSTM: Enabling Efficient LSTM Using Structured Compression Techniques on FPGAs,” in International Symposium on Field-Programmable Gate Arrays (FPGA), 2018. +//Some properties of the design are: +//1. 18-bit fixed point is used. +//2. FFT based circulant convolution +//3. On-chip weight storage (compressed weights). +//4. Double buffering of intermediate results between stages. +//5. Element-wise addition, multiplication and activation blocks. +/////////////////////////////////////////////////////////////////////////////// + +module C_LSTM_datapath ( + input clk, + input reset, + input [161:0] wdata_stage1, + input [7:0] wen_stage1, + input [287:0] wdata_stage2, + input [6:0] wen_stage2, + input [161:0] wdata_stage3, + input [1:0] wen_stage3, + input [17:0] i_X_data_0, + input [17:0] i_X_data_1, + input [17:0] i_X_data_2, + input [17:0] i_X_data_3, + input [17:0] i_X_data_4, + input [17:0] i_X_data_5, + input [17:0] i_X_data_6, + input [17:0] i_X_data_7, + input [17:0] i_X_data_8, + input [17:0] i_X_data_9, + input [17:0] i_X_data_10, + input [17:0] i_X_data_11, + input [17:0] i_X_data_12, + input [17:0] i_X_data_13, + input [17:0] i_X_data_14, + input [17:0] i_X_data_15, + input i_ready, + input i_valid, + input start_compute, + output o_valid, + output [17:0] o_Yt_0_0, + output [17:0] o_Yt_0_1, + output [17:0] o_Yt_0_2, + output [17:0] o_Yt_0_3, + output [17:0] o_Yt_0_4, + output [17:0] o_Yt_0_5, + output [17:0] o_Yt_0_6, + output [17:0] o_Yt_0_7, + output [17:0] o_Yt_0_8, + output [17:0] o_Yt_0_9, + output [17:0] o_Yt_0_10, + output [17:0] o_Yt_0_11, + output [17:0] o_Yt_0_12, + output [17:0] o_Yt_0_13, + output [17:0] o_Yt_0_14, + output [17:0] o_Yt_0_15, + output o_ready +); + +// Enable whenever reciever is ready +wire enable; +assign enable = i_ready; + +// Input registers +wire [17:0] i_data_0; +wire [17:0] i_data_1; +wire [17:0] i_data_2; +wire [17:0] i_data_3; +wire [17:0] i_data_4; +wire [17:0] i_data_5; +wire [17:0] i_data_6; +wire [17:0] i_data_7; +wire [17:0] i_data_8; +wire [17:0] i_data_9; +wire [17:0] i_data_10; +wire [17:0] i_data_11; +wire [17:0] i_data_12; +wire [17:0] i_data_13; +wire [17:0] i_data_14; +wire [17:0] i_data_15; +wire [17:0] i_data_hold_0; +wire [17:0] i_data_hold_1; +wire [17:0] i_data_hold_2; +wire [17:0] i_data_hold_3; +wire [17:0] i_data_hold_4; +wire [17:0] i_data_hold_5; +wire [17:0] i_data_hold_6; +wire [17:0] i_data_hold_7; +wire [17:0] i_data_hold_8; +wire [17:0] i_data_hold_9; +wire [17:0] i_data_hold_10; +wire [17:0] i_data_hold_11; +wire [17:0] i_data_hold_12; +wire [17:0] i_data_hold_13; +wire [17:0] i_data_hold_14; +wire [17:0] i_data_hold_15; + +// Inter connections +wire i_valid_hold; +wire stage1_valid, stage1_ready; +wire out_X_Y_buffer_valid; + +// Stage 1 connections and weight buffers +// Input gate parameters +wire [17:0] Wixr_real_0_0; +wire [17:0] Wixr_imag_0_0; +wire [17:0] Wixr_real_0_1; +wire [17:0] Wixr_imag_0_1; +wire [17:0] Wixr_real_0_2; +wire [17:0] Wixr_imag_0_2; +wire [17:0] Wixr_real_0_3; +wire [17:0] Wixr_imag_0_3; +wire [17:0] Wixr_real_0_4; +wire [17:0] Wixr_imag_0_4; +wire [17:0] Wixr_real_0_5; +wire [17:0] Wixr_imag_0_5; +wire [17:0] Wixr_real_0_6; +wire [17:0] Wixr_imag_0_6; +wire [17:0] Wixr_real_0_7; +wire [17:0] Wixr_imag_0_7; +wire [17:0] Wixr_real_0_8; +wire [17:0] Wixr_imag_0_8; + +// Forget gate parameters +wire [17:0] Wfxr_real_0_0; +wire [17:0] Wfxr_imag_0_0; +wire [17:0] Wfxr_real_0_1; +wire [17:0] Wfxr_imag_0_1; +wire [17:0] Wfxr_real_0_2; +wire [17:0] Wfxr_imag_0_2; +wire [17:0] Wfxr_real_0_3; +wire [17:0] Wfxr_imag_0_3; +wire [17:0] Wfxr_real_0_4; +wire [17:0] Wfxr_imag_0_4; +wire [17:0] Wfxr_real_0_5; +wire [17:0] Wfxr_imag_0_5; +wire [17:0] Wfxr_real_0_6; +wire [17:0] Wfxr_imag_0_6; +wire [17:0] Wfxr_real_0_7; +wire [17:0] Wfxr_imag_0_7; +wire [17:0] Wfxr_real_0_8; +wire [17:0] Wfxr_imag_0_8; + +// Output gate parameters +wire [17:0] Woxr_real_0_0; +wire [17:0] Woxr_imag_0_0; +wire [17:0] Woxr_real_0_1; +wire [17:0] Woxr_imag_0_1; +wire [17:0] Woxr_real_0_2; +wire [17:0] Woxr_imag_0_2; +wire [17:0] Woxr_real_0_3; +wire [17:0] Woxr_imag_0_3; +wire [17:0] Woxr_real_0_4; +wire [17:0] Woxr_imag_0_4; +wire [17:0] Woxr_real_0_5; +wire [17:0] Woxr_imag_0_5; +wire [17:0] Woxr_real_0_6; +wire [17:0] Woxr_imag_0_6; +wire [17:0] Woxr_real_0_7; +wire [17:0] Woxr_imag_0_7; +wire [17:0] Woxr_real_0_8; +wire [17:0] Woxr_imag_0_8; + +// Activation gate parameters +wire [17:0] Wcxr_real_0_0; +wire [17:0] Wcxr_imag_0_0; +wire [17:0] Wcxr_real_0_1; +wire [17:0] Wcxr_imag_0_1; +wire [17:0] Wcxr_real_0_2; +wire [17:0] Wcxr_imag_0_2; +wire [17:0] Wcxr_real_0_3; +wire [17:0] Wcxr_imag_0_3; +wire [17:0] Wcxr_real_0_4; +wire [17:0] Wcxr_imag_0_4; +wire [17:0] Wcxr_real_0_5; +wire [17:0] Wcxr_imag_0_5; +wire [17:0] Wcxr_real_0_6; +wire [17:0] Wcxr_imag_0_6; +wire [17:0] Wcxr_real_0_7; +wire [17:0] Wcxr_imag_0_7; +wire [17:0] Wcxr_real_0_8; +wire [17:0] Wcxr_imag_0_8; + +wire [17:0] WixrXtYt_1_0_0; +wire [17:0] WfxrXtYt_1_0_0; +wire [17:0] WoxrXtYt_1_0_0; +wire [17:0] WcxrXtYt_1_0_0; +wire [17:0] WixrXtYt_1_0_1; +wire [17:0] WfxrXtYt_1_0_1; +wire [17:0] WoxrXtYt_1_0_1; +wire [17:0] WcxrXtYt_1_0_1; +wire [17:0] WixrXtYt_1_0_2; +wire [17:0] WfxrXtYt_1_0_2; +wire [17:0] WoxrXtYt_1_0_2; +wire [17:0] WcxrXtYt_1_0_2; +wire [17:0] WixrXtYt_1_0_3; +wire [17:0] WfxrXtYt_1_0_3; +wire [17:0] WoxrXtYt_1_0_3; +wire [17:0] WcxrXtYt_1_0_3; +wire [17:0] WixrXtYt_1_0_4; +wire [17:0] WfxrXtYt_1_0_4; +wire [17:0] WoxrXtYt_1_0_4; +wire [17:0] WcxrXtYt_1_0_4; +wire [17:0] WixrXtYt_1_0_5; +wire [17:0] WfxrXtYt_1_0_5; +wire [17:0] WoxrXtYt_1_0_5; +wire [17:0] WcxrXtYt_1_0_5; +wire [17:0] WixrXtYt_1_0_6; +wire [17:0] WfxrXtYt_1_0_6; +wire [17:0] WoxrXtYt_1_0_6; +wire [17:0] WcxrXtYt_1_0_6; +wire [17:0] WixrXtYt_1_0_7; +wire [17:0] WfxrXtYt_1_0_7; +wire [17:0] WoxrXtYt_1_0_7; +wire [17:0] WcxrXtYt_1_0_7; +wire [17:0] WixrXtYt_1_0_8; +wire [17:0] WfxrXtYt_1_0_8; +wire [17:0] WoxrXtYt_1_0_8; +wire [17:0] WcxrXtYt_1_0_8; +wire [17:0] WixrXtYt_1_0_9; +wire [17:0] WfxrXtYt_1_0_9; +wire [17:0] WoxrXtYt_1_0_9; +wire [17:0] WcxrXtYt_1_0_9; +wire [17:0] WixrXtYt_1_0_10; +wire [17:0] WfxrXtYt_1_0_10; +wire [17:0] WoxrXtYt_1_0_10; +wire [17:0] WcxrXtYt_1_0_10; +wire [17:0] WixrXtYt_1_0_11; +wire [17:0] WfxrXtYt_1_0_11; +wire [17:0] WoxrXtYt_1_0_11; +wire [17:0] WcxrXtYt_1_0_11; +wire [17:0] WixrXtYt_1_0_12; +wire [17:0] WfxrXtYt_1_0_12; +wire [17:0] WoxrXtYt_1_0_12; +wire [17:0] WcxrXtYt_1_0_12; +wire [17:0] WixrXtYt_1_0_13; +wire [17:0] WfxrXtYt_1_0_13; +wire [17:0] WoxrXtYt_1_0_13; +wire [17:0] WcxrXtYt_1_0_13; +wire [17:0] WixrXtYt_1_0_14; +wire [17:0] WfxrXtYt_1_0_14; +wire [17:0] WoxrXtYt_1_0_14; +wire [17:0] WcxrXtYt_1_0_14; +wire [17:0] WixrXtYt_1_0_15; +wire [17:0] WfxrXtYt_1_0_15; +wire [17:0] WoxrXtYt_1_0_15; +wire [17:0] WcxrXtYt_1_0_15; + +wire stage_buffer_incr_index; +assign stage_buffer_incr_index = out_X_Y_buffer_valid & enable; +stage1_parameter_buffer_18_1_16_42_2688 stage1_parameter_buffer_18_1_16_42_2688_inst_gevdfdvele ( + .clk(clk), + .reset(reset), + .wdata(wdata_stage1), + .wen(wen_stage1), + .Wixr_real_0_0(Wixr_real_0_0), + .Wixr_imag_0_0(Wixr_imag_0_0), + .Wfxr_real_0_0(Wfxr_real_0_0), + .Wfxr_imag_0_0(Wfxr_imag_0_0), + .Woxr_real_0_0(Woxr_real_0_0), + .Woxr_imag_0_0(Woxr_imag_0_0), + .Wcxr_real_0_0(Wcxr_real_0_0), + .Wcxr_imag_0_0(Wcxr_imag_0_0), + .Wixr_real_0_1(Wixr_real_0_1), + .Wixr_imag_0_1(Wixr_imag_0_1), + .Wfxr_real_0_1(Wfxr_real_0_1), + .Wfxr_imag_0_1(Wfxr_imag_0_1), + .Woxr_real_0_1(Woxr_real_0_1), + .Woxr_imag_0_1(Woxr_imag_0_1), + .Wcxr_real_0_1(Wcxr_real_0_1), + .Wcxr_imag_0_1(Wcxr_imag_0_1), + .Wixr_real_0_2(Wixr_real_0_2), + .Wixr_imag_0_2(Wixr_imag_0_2), + .Wfxr_real_0_2(Wfxr_real_0_2), + .Wfxr_imag_0_2(Wfxr_imag_0_2), + .Woxr_real_0_2(Woxr_real_0_2), + .Woxr_imag_0_2(Woxr_imag_0_2), + .Wcxr_real_0_2(Wcxr_real_0_2), + .Wcxr_imag_0_2(Wcxr_imag_0_2), + .Wixr_real_0_3(Wixr_real_0_3), + .Wixr_imag_0_3(Wixr_imag_0_3), + .Wfxr_real_0_3(Wfxr_real_0_3), + .Wfxr_imag_0_3(Wfxr_imag_0_3), + .Woxr_real_0_3(Woxr_real_0_3), + .Woxr_imag_0_3(Woxr_imag_0_3), + .Wcxr_real_0_3(Wcxr_real_0_3), + .Wcxr_imag_0_3(Wcxr_imag_0_3), + .Wixr_real_0_4(Wixr_real_0_4), + .Wixr_imag_0_4(Wixr_imag_0_4), + .Wfxr_real_0_4(Wfxr_real_0_4), + .Wfxr_imag_0_4(Wfxr_imag_0_4), + .Woxr_real_0_4(Woxr_real_0_4), + .Woxr_imag_0_4(Woxr_imag_0_4), + .Wcxr_real_0_4(Wcxr_real_0_4), + .Wcxr_imag_0_4(Wcxr_imag_0_4), + .Wixr_real_0_5(Wixr_real_0_5), + .Wixr_imag_0_5(Wixr_imag_0_5), + .Wfxr_real_0_5(Wfxr_real_0_5), + .Wfxr_imag_0_5(Wfxr_imag_0_5), + .Woxr_real_0_5(Woxr_real_0_5), + .Woxr_imag_0_5(Woxr_imag_0_5), + .Wcxr_real_0_5(Wcxr_real_0_5), + .Wcxr_imag_0_5(Wcxr_imag_0_5), + .Wixr_real_0_6(Wixr_real_0_6), + .Wixr_imag_0_6(Wixr_imag_0_6), + .Wfxr_real_0_6(Wfxr_real_0_6), + .Wfxr_imag_0_6(Wfxr_imag_0_6), + .Woxr_real_0_6(Woxr_real_0_6), + .Woxr_imag_0_6(Woxr_imag_0_6), + .Wcxr_real_0_6(Wcxr_real_0_6), + .Wcxr_imag_0_6(Wcxr_imag_0_6), + .Wixr_real_0_7(Wixr_real_0_7), + .Wixr_imag_0_7(Wixr_imag_0_7), + .Wfxr_real_0_7(Wfxr_real_0_7), + .Wfxr_imag_0_7(Wfxr_imag_0_7), + .Woxr_real_0_7(Woxr_real_0_7), + .Woxr_imag_0_7(Woxr_imag_0_7), + .Wcxr_real_0_7(Wcxr_real_0_7), + .Wcxr_imag_0_7(Wcxr_imag_0_7), + .Wixr_real_0_8(Wixr_real_0_8), + .Wixr_imag_0_8(Wixr_imag_0_8), + .Wfxr_real_0_8(Wfxr_real_0_8), + .Wfxr_imag_0_8(Wfxr_imag_0_8), + .Woxr_real_0_8(Woxr_real_0_8), + .Woxr_imag_0_8(Woxr_imag_0_8), + .Wcxr_real_0_8(Wcxr_real_0_8), + .Wcxr_imag_0_8(Wcxr_imag_0_8), + .incr_index(stage_buffer_incr_index) +); + +// Pipeline the input data for one more cycle to match the parameter rom +shift_register_group_18_16_3 shift_register_group_18_16_3_inst_blfhlyqwso ( + .clk(clk), + .enable(1'b1), + .in_0(i_data_0), + .out_0(i_data_hold_0), + .in_1(i_data_1), + .out_1(i_data_hold_1), + .in_2(i_data_2), + .out_2(i_data_hold_2), + .in_3(i_data_3), + .out_3(i_data_hold_3), + .in_4(i_data_4), + .out_4(i_data_hold_4), + .in_5(i_data_5), + .out_5(i_data_hold_5), + .in_6(i_data_6), + .out_6(i_data_hold_6), + .in_7(i_data_7), + .out_7(i_data_hold_7), + .in_8(i_data_8), + .out_8(i_data_hold_8), + .in_9(i_data_9), + .out_9(i_data_hold_9), + .in_10(i_data_10), + .out_10(i_data_hold_10), + .in_11(i_data_11), + .out_11(i_data_hold_11), + .in_12(i_data_12), + .out_12(i_data_hold_12), + .in_13(i_data_13), + .out_13(i_data_hold_13), + .in_14(i_data_14), + .out_14(i_data_hold_14), + .in_15(i_data_15), + .out_15(i_data_hold_15), + .reset(reset) +); + +shift_register_unit_1_3 shift_register_unit_1_3_inst_bcdmmgrjlp ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(out_X_Y_buffer_valid), + .out(i_valid_hold) +); + +C_LSTM_stage_1_18_10_160_512_1_16_1 C_LSTM_stage_1_18_10_160_512_1_16_1_inst_xwpeawoplv ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_ready(enable), + .i_Xt_Yt_1_0(i_data_hold_0), + .i_Xt_Yt_1_1(i_data_hold_1), + .i_Xt_Yt_1_2(i_data_hold_2), + .i_Xt_Yt_1_3(i_data_hold_3), + .i_Xt_Yt_1_4(i_data_hold_4), + .i_Xt_Yt_1_5(i_data_hold_5), + .i_Xt_Yt_1_6(i_data_hold_6), + .i_Xt_Yt_1_7(i_data_hold_7), + .i_Xt_Yt_1_8(i_data_hold_8), + .i_Xt_Yt_1_9(i_data_hold_9), + .i_Xt_Yt_1_10(i_data_hold_10), + .i_Xt_Yt_1_11(i_data_hold_11), + .i_Xt_Yt_1_12(i_data_hold_12), + .i_Xt_Yt_1_13(i_data_hold_13), + .i_Xt_Yt_1_14(i_data_hold_14), + .i_Xt_Yt_1_15(i_data_hold_15), + .i_Wixr_real_0_0(Wixr_real_0_0), + .i_Wixr_imag_0_0(Wixr_imag_0_0), + .i_Wfxr_real_0_0(Wfxr_real_0_0), + .i_Wfxr_imag_0_0(Wfxr_imag_0_0), + .i_Woxr_real_0_0(Woxr_real_0_0), + .i_Woxr_imag_0_0(Woxr_imag_0_0), + .i_Wcxr_real_0_0(Wcxr_real_0_0), + .i_Wcxr_imag_0_0(Wcxr_imag_0_0), + .i_Wixr_real_0_1(Wixr_real_0_1), + .i_Wixr_imag_0_1(Wixr_imag_0_1), + .i_Wfxr_real_0_1(Wfxr_real_0_1), + .i_Wfxr_imag_0_1(Wfxr_imag_0_1), + .i_Woxr_real_0_1(Woxr_real_0_1), + .i_Woxr_imag_0_1(Woxr_imag_0_1), + .i_Wcxr_real_0_1(Wcxr_real_0_1), + .i_Wcxr_imag_0_1(Wcxr_imag_0_1), + .i_Wixr_real_0_2(Wixr_real_0_2), + .i_Wixr_imag_0_2(Wixr_imag_0_2), + .i_Wfxr_real_0_2(Wfxr_real_0_2), + .i_Wfxr_imag_0_2(Wfxr_imag_0_2), + .i_Woxr_real_0_2(Woxr_real_0_2), + .i_Woxr_imag_0_2(Woxr_imag_0_2), + .i_Wcxr_real_0_2(Wcxr_real_0_2), + .i_Wcxr_imag_0_2(Wcxr_imag_0_2), + .i_Wixr_real_0_3(Wixr_real_0_3), + .i_Wixr_imag_0_3(Wixr_imag_0_3), + .i_Wfxr_real_0_3(Wfxr_real_0_3), + .i_Wfxr_imag_0_3(Wfxr_imag_0_3), + .i_Woxr_real_0_3(Woxr_real_0_3), + .i_Woxr_imag_0_3(Woxr_imag_0_3), + .i_Wcxr_real_0_3(Wcxr_real_0_3), + .i_Wcxr_imag_0_3(Wcxr_imag_0_3), + .i_Wixr_real_0_4(Wixr_real_0_4), + .i_Wixr_imag_0_4(Wixr_imag_0_4), + .i_Wfxr_real_0_4(Wfxr_real_0_4), + .i_Wfxr_imag_0_4(Wfxr_imag_0_4), + .i_Woxr_real_0_4(Woxr_real_0_4), + .i_Woxr_imag_0_4(Woxr_imag_0_4), + .i_Wcxr_real_0_4(Wcxr_real_0_4), + .i_Wcxr_imag_0_4(Wcxr_imag_0_4), + .i_Wixr_real_0_5(Wixr_real_0_5), + .i_Wixr_imag_0_5(Wixr_imag_0_5), + .i_Wfxr_real_0_5(Wfxr_real_0_5), + .i_Wfxr_imag_0_5(Wfxr_imag_0_5), + .i_Woxr_real_0_5(Woxr_real_0_5), + .i_Woxr_imag_0_5(Woxr_imag_0_5), + .i_Wcxr_real_0_5(Wcxr_real_0_5), + .i_Wcxr_imag_0_5(Wcxr_imag_0_5), + .i_Wixr_real_0_6(Wixr_real_0_6), + .i_Wixr_imag_0_6(Wixr_imag_0_6), + .i_Wfxr_real_0_6(Wfxr_real_0_6), + .i_Wfxr_imag_0_6(Wfxr_imag_0_6), + .i_Woxr_real_0_6(Woxr_real_0_6), + .i_Woxr_imag_0_6(Woxr_imag_0_6), + .i_Wcxr_real_0_6(Wcxr_real_0_6), + .i_Wcxr_imag_0_6(Wcxr_imag_0_6), + .i_Wixr_real_0_7(Wixr_real_0_7), + .i_Wixr_imag_0_7(Wixr_imag_0_7), + .i_Wfxr_real_0_7(Wfxr_real_0_7), + .i_Wfxr_imag_0_7(Wfxr_imag_0_7), + .i_Woxr_real_0_7(Woxr_real_0_7), + .i_Woxr_imag_0_7(Woxr_imag_0_7), + .i_Wcxr_real_0_7(Wcxr_real_0_7), + .i_Wcxr_imag_0_7(Wcxr_imag_0_7), + .i_Wixr_real_0_8(Wixr_real_0_8), + .i_Wixr_imag_0_8(Wixr_imag_0_8), + .i_Wfxr_real_0_8(Wfxr_real_0_8), + .i_Wfxr_imag_0_8(Wfxr_imag_0_8), + .i_Woxr_real_0_8(Woxr_real_0_8), + .i_Woxr_imag_0_8(Woxr_imag_0_8), + .i_Wcxr_real_0_8(Wcxr_real_0_8), + .i_Wcxr_imag_0_8(Wcxr_imag_0_8), + .o_valid(stage1_valid), + .o_ready(stage1_ready), + .o_WixrXtYt_1_0_0(WixrXtYt_1_0_0), + .o_WfxrXtYt_1_0_0(WfxrXtYt_1_0_0), + .o_WoxrXtYt_1_0_0(WoxrXtYt_1_0_0), + .o_WcxrXtYt_1_0_0(WcxrXtYt_1_0_0), + .o_WixrXtYt_1_0_1(WixrXtYt_1_0_1), + .o_WfxrXtYt_1_0_1(WfxrXtYt_1_0_1), + .o_WoxrXtYt_1_0_1(WoxrXtYt_1_0_1), + .o_WcxrXtYt_1_0_1(WcxrXtYt_1_0_1), + .o_WixrXtYt_1_0_2(WixrXtYt_1_0_2), + .o_WfxrXtYt_1_0_2(WfxrXtYt_1_0_2), + .o_WoxrXtYt_1_0_2(WoxrXtYt_1_0_2), + .o_WcxrXtYt_1_0_2(WcxrXtYt_1_0_2), + .o_WixrXtYt_1_0_3(WixrXtYt_1_0_3), + .o_WfxrXtYt_1_0_3(WfxrXtYt_1_0_3), + .o_WoxrXtYt_1_0_3(WoxrXtYt_1_0_3), + .o_WcxrXtYt_1_0_3(WcxrXtYt_1_0_3), + .o_WixrXtYt_1_0_4(WixrXtYt_1_0_4), + .o_WfxrXtYt_1_0_4(WfxrXtYt_1_0_4), + .o_WoxrXtYt_1_0_4(WoxrXtYt_1_0_4), + .o_WcxrXtYt_1_0_4(WcxrXtYt_1_0_4), + .o_WixrXtYt_1_0_5(WixrXtYt_1_0_5), + .o_WfxrXtYt_1_0_5(WfxrXtYt_1_0_5), + .o_WoxrXtYt_1_0_5(WoxrXtYt_1_0_5), + .o_WcxrXtYt_1_0_5(WcxrXtYt_1_0_5), + .o_WixrXtYt_1_0_6(WixrXtYt_1_0_6), + .o_WfxrXtYt_1_0_6(WfxrXtYt_1_0_6), + .o_WoxrXtYt_1_0_6(WoxrXtYt_1_0_6), + .o_WcxrXtYt_1_0_6(WcxrXtYt_1_0_6), + .o_WixrXtYt_1_0_7(WixrXtYt_1_0_7), + .o_WfxrXtYt_1_0_7(WfxrXtYt_1_0_7), + .o_WoxrXtYt_1_0_7(WoxrXtYt_1_0_7), + .o_WcxrXtYt_1_0_7(WcxrXtYt_1_0_7), + .o_WixrXtYt_1_0_8(WixrXtYt_1_0_8), + .o_WfxrXtYt_1_0_8(WfxrXtYt_1_0_8), + .o_WoxrXtYt_1_0_8(WoxrXtYt_1_0_8), + .o_WcxrXtYt_1_0_8(WcxrXtYt_1_0_8), + .o_WixrXtYt_1_0_9(WixrXtYt_1_0_9), + .o_WfxrXtYt_1_0_9(WfxrXtYt_1_0_9), + .o_WoxrXtYt_1_0_9(WoxrXtYt_1_0_9), + .o_WcxrXtYt_1_0_9(WcxrXtYt_1_0_9), + .o_WixrXtYt_1_0_10(WixrXtYt_1_0_10), + .o_WfxrXtYt_1_0_10(WfxrXtYt_1_0_10), + .o_WoxrXtYt_1_0_10(WoxrXtYt_1_0_10), + .o_WcxrXtYt_1_0_10(WcxrXtYt_1_0_10), + .o_WixrXtYt_1_0_11(WixrXtYt_1_0_11), + .o_WfxrXtYt_1_0_11(WfxrXtYt_1_0_11), + .o_WoxrXtYt_1_0_11(WoxrXtYt_1_0_11), + .o_WcxrXtYt_1_0_11(WcxrXtYt_1_0_11), + .o_WixrXtYt_1_0_12(WixrXtYt_1_0_12), + .o_WfxrXtYt_1_0_12(WfxrXtYt_1_0_12), + .o_WoxrXtYt_1_0_12(WoxrXtYt_1_0_12), + .o_WcxrXtYt_1_0_12(WcxrXtYt_1_0_12), + .o_WixrXtYt_1_0_13(WixrXtYt_1_0_13), + .o_WfxrXtYt_1_0_13(WfxrXtYt_1_0_13), + .o_WoxrXtYt_1_0_13(WoxrXtYt_1_0_13), + .o_WcxrXtYt_1_0_13(WcxrXtYt_1_0_13), + .o_WixrXtYt_1_0_14(WixrXtYt_1_0_14), + .o_WfxrXtYt_1_0_14(WfxrXtYt_1_0_14), + .o_WoxrXtYt_1_0_14(WoxrXtYt_1_0_14), + .o_WcxrXtYt_1_0_14(WcxrXtYt_1_0_14), + .o_WixrXtYt_1_0_15(WixrXtYt_1_0_15), + .o_WfxrXtYt_1_0_15(WfxrXtYt_1_0_15), + .o_WoxrXtYt_1_0_15(WoxrXtYt_1_0_15), + .o_WcxrXtYt_1_0_15(WcxrXtYt_1_0_15), + .i_valid(i_valid_hold) +); + +// Stage 2 connections and parameter buffer +wire stage2_valid, stage2_ready, stage1_valid_hold; +wire [17:0] Ctt_1_0; +wire [17:0] stage2_Ct_0; +wire [17:0] stage2_mt_0; +wire [17:0] WixrXtYt_1_packed_0; +wire [17:0] WfxrXtYt_1_packed_0; +wire [17:0] WoxrXtYt_1_packed_0; +wire [17:0] WcxrXtYt_1_packed_0; +wire [17:0] WixrXtYt_1_hold_0; +wire [17:0] WfxrXtYt_1_hold_0; +wire [17:0] WoxrXtYt_1_hold_0; +wire [17:0] WcxrXtYt_1_hold_0; +wire [17:0] Wic_0; +wire [17:0] bi_0; +wire [17:0] Wfc_0; +wire [17:0] bf_0; +wire [17:0] Woc_0; +wire [17:0] bo_0; +wire [17:0] bc_0; +wire [17:0] Ctt_1_1; +wire [17:0] stage2_Ct_1; +wire [17:0] stage2_mt_1; +wire [17:0] WixrXtYt_1_packed_1; +wire [17:0] WfxrXtYt_1_packed_1; +wire [17:0] WoxrXtYt_1_packed_1; +wire [17:0] WcxrXtYt_1_packed_1; +wire [17:0] WixrXtYt_1_hold_1; +wire [17:0] WfxrXtYt_1_hold_1; +wire [17:0] WoxrXtYt_1_hold_1; +wire [17:0] WcxrXtYt_1_hold_1; +wire [17:0] Wic_1; +wire [17:0] bi_1; +wire [17:0] Wfc_1; +wire [17:0] bf_1; +wire [17:0] Woc_1; +wire [17:0] bo_1; +wire [17:0] bc_1; +wire [17:0] Ctt_1_2; +wire [17:0] stage2_Ct_2; +wire [17:0] stage2_mt_2; +wire [17:0] WixrXtYt_1_packed_2; +wire [17:0] WfxrXtYt_1_packed_2; +wire [17:0] WoxrXtYt_1_packed_2; +wire [17:0] WcxrXtYt_1_packed_2; +wire [17:0] WixrXtYt_1_hold_2; +wire [17:0] WfxrXtYt_1_hold_2; +wire [17:0] WoxrXtYt_1_hold_2; +wire [17:0] WcxrXtYt_1_hold_2; +wire [17:0] Wic_2; +wire [17:0] bi_2; +wire [17:0] Wfc_2; +wire [17:0] bf_2; +wire [17:0] Woc_2; +wire [17:0] bo_2; +wire [17:0] bc_2; +wire [17:0] Ctt_1_3; +wire [17:0] stage2_Ct_3; +wire [17:0] stage2_mt_3; +wire [17:0] WixrXtYt_1_packed_3; +wire [17:0] WfxrXtYt_1_packed_3; +wire [17:0] WoxrXtYt_1_packed_3; +wire [17:0] WcxrXtYt_1_packed_3; +wire [17:0] WixrXtYt_1_hold_3; +wire [17:0] WfxrXtYt_1_hold_3; +wire [17:0] WoxrXtYt_1_hold_3; +wire [17:0] WcxrXtYt_1_hold_3; +wire [17:0] Wic_3; +wire [17:0] bi_3; +wire [17:0] Wfc_3; +wire [17:0] bf_3; +wire [17:0] Woc_3; +wire [17:0] bo_3; +wire [17:0] bc_3; +wire [17:0] Ctt_1_4; +wire [17:0] stage2_Ct_4; +wire [17:0] stage2_mt_4; +wire [17:0] WixrXtYt_1_packed_4; +wire [17:0] WfxrXtYt_1_packed_4; +wire [17:0] WoxrXtYt_1_packed_4; +wire [17:0] WcxrXtYt_1_packed_4; +wire [17:0] WixrXtYt_1_hold_4; +wire [17:0] WfxrXtYt_1_hold_4; +wire [17:0] WoxrXtYt_1_hold_4; +wire [17:0] WcxrXtYt_1_hold_4; +wire [17:0] Wic_4; +wire [17:0] bi_4; +wire [17:0] Wfc_4; +wire [17:0] bf_4; +wire [17:0] Woc_4; +wire [17:0] bo_4; +wire [17:0] bc_4; +wire [17:0] Ctt_1_5; +wire [17:0] stage2_Ct_5; +wire [17:0] stage2_mt_5; +wire [17:0] WixrXtYt_1_packed_5; +wire [17:0] WfxrXtYt_1_packed_5; +wire [17:0] WoxrXtYt_1_packed_5; +wire [17:0] WcxrXtYt_1_packed_5; +wire [17:0] WixrXtYt_1_hold_5; +wire [17:0] WfxrXtYt_1_hold_5; +wire [17:0] WoxrXtYt_1_hold_5; +wire [17:0] WcxrXtYt_1_hold_5; +wire [17:0] Wic_5; +wire [17:0] bi_5; +wire [17:0] Wfc_5; +wire [17:0] bf_5; +wire [17:0] Woc_5; +wire [17:0] bo_5; +wire [17:0] bc_5; +wire [17:0] Ctt_1_6; +wire [17:0] stage2_Ct_6; +wire [17:0] stage2_mt_6; +wire [17:0] WixrXtYt_1_packed_6; +wire [17:0] WfxrXtYt_1_packed_6; +wire [17:0] WoxrXtYt_1_packed_6; +wire [17:0] WcxrXtYt_1_packed_6; +wire [17:0] WixrXtYt_1_hold_6; +wire [17:0] WfxrXtYt_1_hold_6; +wire [17:0] WoxrXtYt_1_hold_6; +wire [17:0] WcxrXtYt_1_hold_6; +wire [17:0] Wic_6; +wire [17:0] bi_6; +wire [17:0] Wfc_6; +wire [17:0] bf_6; +wire [17:0] Woc_6; +wire [17:0] bo_6; +wire [17:0] bc_6; +wire [17:0] Ctt_1_7; +wire [17:0] stage2_Ct_7; +wire [17:0] stage2_mt_7; +wire [17:0] WixrXtYt_1_packed_7; +wire [17:0] WfxrXtYt_1_packed_7; +wire [17:0] WoxrXtYt_1_packed_7; +wire [17:0] WcxrXtYt_1_packed_7; +wire [17:0] WixrXtYt_1_hold_7; +wire [17:0] WfxrXtYt_1_hold_7; +wire [17:0] WoxrXtYt_1_hold_7; +wire [17:0] WcxrXtYt_1_hold_7; +wire [17:0] Wic_7; +wire [17:0] bi_7; +wire [17:0] Wfc_7; +wire [17:0] bf_7; +wire [17:0] Woc_7; +wire [17:0] bo_7; +wire [17:0] bc_7; +wire [17:0] Ctt_1_8; +wire [17:0] stage2_Ct_8; +wire [17:0] stage2_mt_8; +wire [17:0] WixrXtYt_1_packed_8; +wire [17:0] WfxrXtYt_1_packed_8; +wire [17:0] WoxrXtYt_1_packed_8; +wire [17:0] WcxrXtYt_1_packed_8; +wire [17:0] WixrXtYt_1_hold_8; +wire [17:0] WfxrXtYt_1_hold_8; +wire [17:0] WoxrXtYt_1_hold_8; +wire [17:0] WcxrXtYt_1_hold_8; +wire [17:0] Wic_8; +wire [17:0] bi_8; +wire [17:0] Wfc_8; +wire [17:0] bf_8; +wire [17:0] Woc_8; +wire [17:0] bo_8; +wire [17:0] bc_8; +wire [17:0] Ctt_1_9; +wire [17:0] stage2_Ct_9; +wire [17:0] stage2_mt_9; +wire [17:0] WixrXtYt_1_packed_9; +wire [17:0] WfxrXtYt_1_packed_9; +wire [17:0] WoxrXtYt_1_packed_9; +wire [17:0] WcxrXtYt_1_packed_9; +wire [17:0] WixrXtYt_1_hold_9; +wire [17:0] WfxrXtYt_1_hold_9; +wire [17:0] WoxrXtYt_1_hold_9; +wire [17:0] WcxrXtYt_1_hold_9; +wire [17:0] Wic_9; +wire [17:0] bi_9; +wire [17:0] Wfc_9; +wire [17:0] bf_9; +wire [17:0] Woc_9; +wire [17:0] bo_9; +wire [17:0] bc_9; +wire [17:0] Ctt_1_10; +wire [17:0] stage2_Ct_10; +wire [17:0] stage2_mt_10; +wire [17:0] WixrXtYt_1_packed_10; +wire [17:0] WfxrXtYt_1_packed_10; +wire [17:0] WoxrXtYt_1_packed_10; +wire [17:0] WcxrXtYt_1_packed_10; +wire [17:0] WixrXtYt_1_hold_10; +wire [17:0] WfxrXtYt_1_hold_10; +wire [17:0] WoxrXtYt_1_hold_10; +wire [17:0] WcxrXtYt_1_hold_10; +wire [17:0] Wic_10; +wire [17:0] bi_10; +wire [17:0] Wfc_10; +wire [17:0] bf_10; +wire [17:0] Woc_10; +wire [17:0] bo_10; +wire [17:0] bc_10; +wire [17:0] Ctt_1_11; +wire [17:0] stage2_Ct_11; +wire [17:0] stage2_mt_11; +wire [17:0] WixrXtYt_1_packed_11; +wire [17:0] WfxrXtYt_1_packed_11; +wire [17:0] WoxrXtYt_1_packed_11; +wire [17:0] WcxrXtYt_1_packed_11; +wire [17:0] WixrXtYt_1_hold_11; +wire [17:0] WfxrXtYt_1_hold_11; +wire [17:0] WoxrXtYt_1_hold_11; +wire [17:0] WcxrXtYt_1_hold_11; +wire [17:0] Wic_11; +wire [17:0] bi_11; +wire [17:0] Wfc_11; +wire [17:0] bf_11; +wire [17:0] Woc_11; +wire [17:0] bo_11; +wire [17:0] bc_11; +wire [17:0] Ctt_1_12; +wire [17:0] stage2_Ct_12; +wire [17:0] stage2_mt_12; +wire [17:0] WixrXtYt_1_packed_12; +wire [17:0] WfxrXtYt_1_packed_12; +wire [17:0] WoxrXtYt_1_packed_12; +wire [17:0] WcxrXtYt_1_packed_12; +wire [17:0] WixrXtYt_1_hold_12; +wire [17:0] WfxrXtYt_1_hold_12; +wire [17:0] WoxrXtYt_1_hold_12; +wire [17:0] WcxrXtYt_1_hold_12; +wire [17:0] Wic_12; +wire [17:0] bi_12; +wire [17:0] Wfc_12; +wire [17:0] bf_12; +wire [17:0] Woc_12; +wire [17:0] bo_12; +wire [17:0] bc_12; +wire [17:0] Ctt_1_13; +wire [17:0] stage2_Ct_13; +wire [17:0] stage2_mt_13; +wire [17:0] WixrXtYt_1_packed_13; +wire [17:0] WfxrXtYt_1_packed_13; +wire [17:0] WoxrXtYt_1_packed_13; +wire [17:0] WcxrXtYt_1_packed_13; +wire [17:0] WixrXtYt_1_hold_13; +wire [17:0] WfxrXtYt_1_hold_13; +wire [17:0] WoxrXtYt_1_hold_13; +wire [17:0] WcxrXtYt_1_hold_13; +wire [17:0] Wic_13; +wire [17:0] bi_13; +wire [17:0] Wfc_13; +wire [17:0] bf_13; +wire [17:0] Woc_13; +wire [17:0] bo_13; +wire [17:0] bc_13; +wire [17:0] Ctt_1_14; +wire [17:0] stage2_Ct_14; +wire [17:0] stage2_mt_14; +wire [17:0] WixrXtYt_1_packed_14; +wire [17:0] WfxrXtYt_1_packed_14; +wire [17:0] WoxrXtYt_1_packed_14; +wire [17:0] WcxrXtYt_1_packed_14; +wire [17:0] WixrXtYt_1_hold_14; +wire [17:0] WfxrXtYt_1_hold_14; +wire [17:0] WoxrXtYt_1_hold_14; +wire [17:0] WcxrXtYt_1_hold_14; +wire [17:0] Wic_14; +wire [17:0] bi_14; +wire [17:0] Wfc_14; +wire [17:0] bf_14; +wire [17:0] Woc_14; +wire [17:0] bo_14; +wire [17:0] bc_14; +wire [17:0] Ctt_1_15; +wire [17:0] stage2_Ct_15; +wire [17:0] stage2_mt_15; +wire [17:0] WixrXtYt_1_packed_15; +wire [17:0] WfxrXtYt_1_packed_15; +wire [17:0] WoxrXtYt_1_packed_15; +wire [17:0] WcxrXtYt_1_packed_15; +wire [17:0] WixrXtYt_1_hold_15; +wire [17:0] WfxrXtYt_1_hold_15; +wire [17:0] WoxrXtYt_1_hold_15; +wire [17:0] WcxrXtYt_1_hold_15; +wire [17:0] Wic_15; +wire [17:0] bi_15; +wire [17:0] Wfc_15; +wire [17:0] bf_15; +wire [17:0] Woc_15; +wire [17:0] bo_15; +wire [17:0] bc_15; + +stage2_parameter_buffer_18_1_16_64 stage2_parameter_buffer_18_1_16_64_inst_fvuxtfiavp ( + .clk(clk), + .reset(reset), + .wdata(wdata_stage2), + .wen(wen_stage2), + .o_Wic_0(Wic_0), + .o_bi_0(bi_0), + .o_Wfc_0(Wfc_0), + .o_bf_0(bf_0), + .o_Woc_0(Woc_0), + .o_bo_0(bo_0), + .o_bc_0(bc_0), + .o_Wic_1(Wic_1), + .o_bi_1(bi_1), + .o_Wfc_1(Wfc_1), + .o_bf_1(bf_1), + .o_Woc_1(Woc_1), + .o_bo_1(bo_1), + .o_bc_1(bc_1), + .o_Wic_2(Wic_2), + .o_bi_2(bi_2), + .o_Wfc_2(Wfc_2), + .o_bf_2(bf_2), + .o_Woc_2(Woc_2), + .o_bo_2(bo_2), + .o_bc_2(bc_2), + .o_Wic_3(Wic_3), + .o_bi_3(bi_3), + .o_Wfc_3(Wfc_3), + .o_bf_3(bf_3), + .o_Woc_3(Woc_3), + .o_bo_3(bo_3), + .o_bc_3(bc_3), + .o_Wic_4(Wic_4), + .o_bi_4(bi_4), + .o_Wfc_4(Wfc_4), + .o_bf_4(bf_4), + .o_Woc_4(Woc_4), + .o_bo_4(bo_4), + .o_bc_4(bc_4), + .o_Wic_5(Wic_5), + .o_bi_5(bi_5), + .o_Wfc_5(Wfc_5), + .o_bf_5(bf_5), + .o_Woc_5(Woc_5), + .o_bo_5(bo_5), + .o_bc_5(bc_5), + .o_Wic_6(Wic_6), + .o_bi_6(bi_6), + .o_Wfc_6(Wfc_6), + .o_bf_6(bf_6), + .o_Woc_6(Woc_6), + .o_bo_6(bo_6), + .o_bc_6(bc_6), + .o_Wic_7(Wic_7), + .o_bi_7(bi_7), + .o_Wfc_7(Wfc_7), + .o_bf_7(bf_7), + .o_Woc_7(Woc_7), + .o_bo_7(bo_7), + .o_bc_7(bc_7), + .o_Wic_8(Wic_8), + .o_bi_8(bi_8), + .o_Wfc_8(Wfc_8), + .o_bf_8(bf_8), + .o_Woc_8(Woc_8), + .o_bo_8(bo_8), + .o_bc_8(bc_8), + .o_Wic_9(Wic_9), + .o_bi_9(bi_9), + .o_Wfc_9(Wfc_9), + .o_bf_9(bf_9), + .o_Woc_9(Woc_9), + .o_bo_9(bo_9), + .o_bc_9(bc_9), + .o_Wic_10(Wic_10), + .o_bi_10(bi_10), + .o_Wfc_10(Wfc_10), + .o_bf_10(bf_10), + .o_Woc_10(Woc_10), + .o_bo_10(bo_10), + .o_bc_10(bc_10), + .o_Wic_11(Wic_11), + .o_bi_11(bi_11), + .o_Wfc_11(Wfc_11), + .o_bf_11(bf_11), + .o_Woc_11(Woc_11), + .o_bo_11(bo_11), + .o_bc_11(bc_11), + .o_Wic_12(Wic_12), + .o_bi_12(bi_12), + .o_Wfc_12(Wfc_12), + .o_bf_12(bf_12), + .o_Woc_12(Woc_12), + .o_bo_12(bo_12), + .o_bc_12(bc_12), + .o_Wic_13(Wic_13), + .o_bi_13(bi_13), + .o_Wfc_13(Wfc_13), + .o_bf_13(bf_13), + .o_Woc_13(Woc_13), + .o_bo_13(bo_13), + .o_bc_13(bc_13), + .o_Wic_14(Wic_14), + .o_bi_14(bi_14), + .o_Wfc_14(Wfc_14), + .o_bf_14(bf_14), + .o_Woc_14(Woc_14), + .o_bo_14(bo_14), + .o_bc_14(bc_14), + .o_Wic_15(Wic_15), + .o_bi_15(bi_15), + .o_Wfc_15(Wfc_15), + .o_bf_15(bf_15), + .o_Woc_15(Woc_15), + .o_bo_15(bo_15), + .o_bc_15(bc_15), + .incr_index(stage1_valid) +); + +assign WixrXtYt_1_packed_0 = WixrXtYt_1_0_0; +assign WfxrXtYt_1_packed_0 = WfxrXtYt_1_0_0; +assign WoxrXtYt_1_packed_0 = WoxrXtYt_1_0_0; +assign WcxrXtYt_1_packed_0 = WcxrXtYt_1_0_0; +assign WixrXtYt_1_packed_1 = WixrXtYt_1_0_1; +assign WfxrXtYt_1_packed_1 = WfxrXtYt_1_0_1; +assign WoxrXtYt_1_packed_1 = WoxrXtYt_1_0_1; +assign WcxrXtYt_1_packed_1 = WcxrXtYt_1_0_1; +assign WixrXtYt_1_packed_2 = WixrXtYt_1_0_2; +assign WfxrXtYt_1_packed_2 = WfxrXtYt_1_0_2; +assign WoxrXtYt_1_packed_2 = WoxrXtYt_1_0_2; +assign WcxrXtYt_1_packed_2 = WcxrXtYt_1_0_2; +assign WixrXtYt_1_packed_3 = WixrXtYt_1_0_3; +assign WfxrXtYt_1_packed_3 = WfxrXtYt_1_0_3; +assign WoxrXtYt_1_packed_3 = WoxrXtYt_1_0_3; +assign WcxrXtYt_1_packed_3 = WcxrXtYt_1_0_3; +assign WixrXtYt_1_packed_4 = WixrXtYt_1_0_4; +assign WfxrXtYt_1_packed_4 = WfxrXtYt_1_0_4; +assign WoxrXtYt_1_packed_4 = WoxrXtYt_1_0_4; +assign WcxrXtYt_1_packed_4 = WcxrXtYt_1_0_4; +assign WixrXtYt_1_packed_5 = WixrXtYt_1_0_5; +assign WfxrXtYt_1_packed_5 = WfxrXtYt_1_0_5; +assign WoxrXtYt_1_packed_5 = WoxrXtYt_1_0_5; +assign WcxrXtYt_1_packed_5 = WcxrXtYt_1_0_5; +assign WixrXtYt_1_packed_6 = WixrXtYt_1_0_6; +assign WfxrXtYt_1_packed_6 = WfxrXtYt_1_0_6; +assign WoxrXtYt_1_packed_6 = WoxrXtYt_1_0_6; +assign WcxrXtYt_1_packed_6 = WcxrXtYt_1_0_6; +assign WixrXtYt_1_packed_7 = WixrXtYt_1_0_7; +assign WfxrXtYt_1_packed_7 = WfxrXtYt_1_0_7; +assign WoxrXtYt_1_packed_7 = WoxrXtYt_1_0_7; +assign WcxrXtYt_1_packed_7 = WcxrXtYt_1_0_7; +assign WixrXtYt_1_packed_8 = WixrXtYt_1_0_8; +assign WfxrXtYt_1_packed_8 = WfxrXtYt_1_0_8; +assign WoxrXtYt_1_packed_8 = WoxrXtYt_1_0_8; +assign WcxrXtYt_1_packed_8 = WcxrXtYt_1_0_8; +assign WixrXtYt_1_packed_9 = WixrXtYt_1_0_9; +assign WfxrXtYt_1_packed_9 = WfxrXtYt_1_0_9; +assign WoxrXtYt_1_packed_9 = WoxrXtYt_1_0_9; +assign WcxrXtYt_1_packed_9 = WcxrXtYt_1_0_9; +assign WixrXtYt_1_packed_10 = WixrXtYt_1_0_10; +assign WfxrXtYt_1_packed_10 = WfxrXtYt_1_0_10; +assign WoxrXtYt_1_packed_10 = WoxrXtYt_1_0_10; +assign WcxrXtYt_1_packed_10 = WcxrXtYt_1_0_10; +assign WixrXtYt_1_packed_11 = WixrXtYt_1_0_11; +assign WfxrXtYt_1_packed_11 = WfxrXtYt_1_0_11; +assign WoxrXtYt_1_packed_11 = WoxrXtYt_1_0_11; +assign WcxrXtYt_1_packed_11 = WcxrXtYt_1_0_11; +assign WixrXtYt_1_packed_12 = WixrXtYt_1_0_12; +assign WfxrXtYt_1_packed_12 = WfxrXtYt_1_0_12; +assign WoxrXtYt_1_packed_12 = WoxrXtYt_1_0_12; +assign WcxrXtYt_1_packed_12 = WcxrXtYt_1_0_12; +assign WixrXtYt_1_packed_13 = WixrXtYt_1_0_13; +assign WfxrXtYt_1_packed_13 = WfxrXtYt_1_0_13; +assign WoxrXtYt_1_packed_13 = WoxrXtYt_1_0_13; +assign WcxrXtYt_1_packed_13 = WcxrXtYt_1_0_13; +assign WixrXtYt_1_packed_14 = WixrXtYt_1_0_14; +assign WfxrXtYt_1_packed_14 = WfxrXtYt_1_0_14; +assign WoxrXtYt_1_packed_14 = WoxrXtYt_1_0_14; +assign WcxrXtYt_1_packed_14 = WcxrXtYt_1_0_14; +assign WixrXtYt_1_packed_15 = WixrXtYt_1_0_15; +assign WfxrXtYt_1_packed_15 = WfxrXtYt_1_0_15; +assign WoxrXtYt_1_packed_15 = WoxrXtYt_1_0_15; +assign WcxrXtYt_1_packed_15 = WcxrXtYt_1_0_15; + +shift_register_group_18_16_3 shift_register_group_18_16_3_inst_Wi ( + .clk(clk), + .enable(enable), + .in_0(WixrXtYt_1_packed_0), + .out_0(WixrXtYt_1_hold_0), + .in_1(WixrXtYt_1_packed_1), + .out_1(WixrXtYt_1_hold_1), + .in_2(WixrXtYt_1_packed_2), + .out_2(WixrXtYt_1_hold_2), + .in_3(WixrXtYt_1_packed_3), + .out_3(WixrXtYt_1_hold_3), + .in_4(WixrXtYt_1_packed_4), + .out_4(WixrXtYt_1_hold_4), + .in_5(WixrXtYt_1_packed_5), + .out_5(WixrXtYt_1_hold_5), + .in_6(WixrXtYt_1_packed_6), + .out_6(WixrXtYt_1_hold_6), + .in_7(WixrXtYt_1_packed_7), + .out_7(WixrXtYt_1_hold_7), + .in_8(WixrXtYt_1_packed_8), + .out_8(WixrXtYt_1_hold_8), + .in_9(WixrXtYt_1_packed_9), + .out_9(WixrXtYt_1_hold_9), + .in_10(WixrXtYt_1_packed_10), + .out_10(WixrXtYt_1_hold_10), + .in_11(WixrXtYt_1_packed_11), + .out_11(WixrXtYt_1_hold_11), + .in_12(WixrXtYt_1_packed_12), + .out_12(WixrXtYt_1_hold_12), + .in_13(WixrXtYt_1_packed_13), + .out_13(WixrXtYt_1_hold_13), + .in_14(WixrXtYt_1_packed_14), + .out_14(WixrXtYt_1_hold_14), + .in_15(WixrXtYt_1_packed_15), + .out_15(WixrXtYt_1_hold_15), + .reset(reset) +); + +shift_register_group_18_16_3 shift_register_group_18_16_3_inst_Wf ( + .clk(clk), + .enable(enable), + .in_0(WfxrXtYt_1_packed_0), + .out_0(WfxrXtYt_1_hold_0), + .in_1(WfxrXtYt_1_packed_1), + .out_1(WfxrXtYt_1_hold_1), + .in_2(WfxrXtYt_1_packed_2), + .out_2(WfxrXtYt_1_hold_2), + .in_3(WfxrXtYt_1_packed_3), + .out_3(WfxrXtYt_1_hold_3), + .in_4(WfxrXtYt_1_packed_4), + .out_4(WfxrXtYt_1_hold_4), + .in_5(WfxrXtYt_1_packed_5), + .out_5(WfxrXtYt_1_hold_5), + .in_6(WfxrXtYt_1_packed_6), + .out_6(WfxrXtYt_1_hold_6), + .in_7(WfxrXtYt_1_packed_7), + .out_7(WfxrXtYt_1_hold_7), + .in_8(WfxrXtYt_1_packed_8), + .out_8(WfxrXtYt_1_hold_8), + .in_9(WfxrXtYt_1_packed_9), + .out_9(WfxrXtYt_1_hold_9), + .in_10(WfxrXtYt_1_packed_10), + .out_10(WfxrXtYt_1_hold_10), + .in_11(WfxrXtYt_1_packed_11), + .out_11(WfxrXtYt_1_hold_11), + .in_12(WfxrXtYt_1_packed_12), + .out_12(WfxrXtYt_1_hold_12), + .in_13(WfxrXtYt_1_packed_13), + .out_13(WfxrXtYt_1_hold_13), + .in_14(WfxrXtYt_1_packed_14), + .out_14(WfxrXtYt_1_hold_14), + .in_15(WfxrXtYt_1_packed_15), + .out_15(WfxrXtYt_1_hold_15), + .reset(reset) +); + +shift_register_group_18_16_3 shift_register_group_18_16_3_inst_Wo ( + .clk(clk), + .enable(enable), + .in_0(WoxrXtYt_1_packed_0), + .out_0(WoxrXtYt_1_hold_0), + .in_1(WoxrXtYt_1_packed_1), + .out_1(WoxrXtYt_1_hold_1), + .in_2(WoxrXtYt_1_packed_2), + .out_2(WoxrXtYt_1_hold_2), + .in_3(WoxrXtYt_1_packed_3), + .out_3(WoxrXtYt_1_hold_3), + .in_4(WoxrXtYt_1_packed_4), + .out_4(WoxrXtYt_1_hold_4), + .in_5(WoxrXtYt_1_packed_5), + .out_5(WoxrXtYt_1_hold_5), + .in_6(WoxrXtYt_1_packed_6), + .out_6(WoxrXtYt_1_hold_6), + .in_7(WoxrXtYt_1_packed_7), + .out_7(WoxrXtYt_1_hold_7), + .in_8(WoxrXtYt_1_packed_8), + .out_8(WoxrXtYt_1_hold_8), + .in_9(WoxrXtYt_1_packed_9), + .out_9(WoxrXtYt_1_hold_9), + .in_10(WoxrXtYt_1_packed_10), + .out_10(WoxrXtYt_1_hold_10), + .in_11(WoxrXtYt_1_packed_11), + .out_11(WoxrXtYt_1_hold_11), + .in_12(WoxrXtYt_1_packed_12), + .out_12(WoxrXtYt_1_hold_12), + .in_13(WoxrXtYt_1_packed_13), + .out_13(WoxrXtYt_1_hold_13), + .in_14(WoxrXtYt_1_packed_14), + .out_14(WoxrXtYt_1_hold_14), + .in_15(WoxrXtYt_1_packed_15), + .out_15(WoxrXtYt_1_hold_15), + .reset(reset) +); + +shift_register_group_18_16_3 shift_register_group_18_16_3_inst_Wc ( + .clk(clk), + .enable(enable), + .in_0(WcxrXtYt_1_packed_0), + .out_0(WcxrXtYt_1_hold_0), + .in_1(WcxrXtYt_1_packed_1), + .out_1(WcxrXtYt_1_hold_1), + .in_2(WcxrXtYt_1_packed_2), + .out_2(WcxrXtYt_1_hold_2), + .in_3(WcxrXtYt_1_packed_3), + .out_3(WcxrXtYt_1_hold_3), + .in_4(WcxrXtYt_1_packed_4), + .out_4(WcxrXtYt_1_hold_4), + .in_5(WcxrXtYt_1_packed_5), + .out_5(WcxrXtYt_1_hold_5), + .in_6(WcxrXtYt_1_packed_6), + .out_6(WcxrXtYt_1_hold_6), + .in_7(WcxrXtYt_1_packed_7), + .out_7(WcxrXtYt_1_hold_7), + .in_8(WcxrXtYt_1_packed_8), + .out_8(WcxrXtYt_1_hold_8), + .in_9(WcxrXtYt_1_packed_9), + .out_9(WcxrXtYt_1_hold_9), + .in_10(WcxrXtYt_1_packed_10), + .out_10(WcxrXtYt_1_hold_10), + .in_11(WcxrXtYt_1_packed_11), + .out_11(WcxrXtYt_1_hold_11), + .in_12(WcxrXtYt_1_packed_12), + .out_12(WcxrXtYt_1_hold_12), + .in_13(WcxrXtYt_1_packed_13), + .out_13(WcxrXtYt_1_hold_13), + .in_14(WcxrXtYt_1_packed_14), + .out_14(WcxrXtYt_1_hold_14), + .in_15(WcxrXtYt_1_packed_15), + .out_15(WcxrXtYt_1_hold_15), + .reset(reset) +); + +shift_register_unit_1_3 shift_register_unit_1_3_inst_s2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(stage1_valid), + .out(stage1_valid_hold) +); + +C_LSTM_stage_2_18_10_16_1 C_LSTM_stage_2_18_10_16_1_inst_zumzzzfdoh ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(stage1_valid_hold), + .Ct_1_0(Ctt_1_0), + .WixrXtYt_1_0(WixrXtYt_1_hold_0), + .Wic_0(Wic_0), + .bi_0(bi_0), + .WfxrXtYt_1_0(WfxrXtYt_1_hold_0), + .Wfc_0(Wfc_0), + .bf_0(bf_0), + .WoxrXtYt_1_0(WoxrXtYt_1_hold_0), + .Woc_0(Woc_0), + .bo_0(bo_0), + .WcxrXtYt_1_0(WcxrXtYt_1_hold_0), + .bc_0(bc_0), + .out_mt_0(stage2_mt_0), + .out_ct_0(stage2_Ct_0), + .Ct_1_1(Ctt_1_1), + .WixrXtYt_1_1(WixrXtYt_1_hold_1), + .Wic_1(Wic_1), + .bi_1(bi_1), + .WfxrXtYt_1_1(WfxrXtYt_1_hold_1), + .Wfc_1(Wfc_1), + .bf_1(bf_1), + .WoxrXtYt_1_1(WoxrXtYt_1_hold_1), + .Woc_1(Woc_1), + .bo_1(bo_1), + .WcxrXtYt_1_1(WcxrXtYt_1_hold_1), + .bc_1(bc_1), + .out_mt_1(stage2_mt_1), + .out_ct_1(stage2_Ct_1), + .Ct_1_2(Ctt_1_2), + .WixrXtYt_1_2(WixrXtYt_1_hold_2), + .Wic_2(Wic_2), + .bi_2(bi_2), + .WfxrXtYt_1_2(WfxrXtYt_1_hold_2), + .Wfc_2(Wfc_2), + .bf_2(bf_2), + .WoxrXtYt_1_2(WoxrXtYt_1_hold_2), + .Woc_2(Woc_2), + .bo_2(bo_2), + .WcxrXtYt_1_2(WcxrXtYt_1_hold_2), + .bc_2(bc_2), + .out_mt_2(stage2_mt_2), + .out_ct_2(stage2_Ct_2), + .Ct_1_3(Ctt_1_3), + .WixrXtYt_1_3(WixrXtYt_1_hold_3), + .Wic_3(Wic_3), + .bi_3(bi_3), + .WfxrXtYt_1_3(WfxrXtYt_1_hold_3), + .Wfc_3(Wfc_3), + .bf_3(bf_3), + .WoxrXtYt_1_3(WoxrXtYt_1_hold_3), + .Woc_3(Woc_3), + .bo_3(bo_3), + .WcxrXtYt_1_3(WcxrXtYt_1_hold_3), + .bc_3(bc_3), + .out_mt_3(stage2_mt_3), + .out_ct_3(stage2_Ct_3), + .Ct_1_4(Ctt_1_4), + .WixrXtYt_1_4(WixrXtYt_1_hold_4), + .Wic_4(Wic_4), + .bi_4(bi_4), + .WfxrXtYt_1_4(WfxrXtYt_1_hold_4), + .Wfc_4(Wfc_4), + .bf_4(bf_4), + .WoxrXtYt_1_4(WoxrXtYt_1_hold_4), + .Woc_4(Woc_4), + .bo_4(bo_4), + .WcxrXtYt_1_4(WcxrXtYt_1_hold_4), + .bc_4(bc_4), + .out_mt_4(stage2_mt_4), + .out_ct_4(stage2_Ct_4), + .Ct_1_5(Ctt_1_5), + .WixrXtYt_1_5(WixrXtYt_1_hold_5), + .Wic_5(Wic_5), + .bi_5(bi_5), + .WfxrXtYt_1_5(WfxrXtYt_1_hold_5), + .Wfc_5(Wfc_5), + .bf_5(bf_5), + .WoxrXtYt_1_5(WoxrXtYt_1_hold_5), + .Woc_5(Woc_5), + .bo_5(bo_5), + .WcxrXtYt_1_5(WcxrXtYt_1_hold_5), + .bc_5(bc_5), + .out_mt_5(stage2_mt_5), + .out_ct_5(stage2_Ct_5), + .Ct_1_6(Ctt_1_6), + .WixrXtYt_1_6(WixrXtYt_1_hold_6), + .Wic_6(Wic_6), + .bi_6(bi_6), + .WfxrXtYt_1_6(WfxrXtYt_1_hold_6), + .Wfc_6(Wfc_6), + .bf_6(bf_6), + .WoxrXtYt_1_6(WoxrXtYt_1_hold_6), + .Woc_6(Woc_6), + .bo_6(bo_6), + .WcxrXtYt_1_6(WcxrXtYt_1_hold_6), + .bc_6(bc_6), + .out_mt_6(stage2_mt_6), + .out_ct_6(stage2_Ct_6), + .Ct_1_7(Ctt_1_7), + .WixrXtYt_1_7(WixrXtYt_1_hold_7), + .Wic_7(Wic_7), + .bi_7(bi_7), + .WfxrXtYt_1_7(WfxrXtYt_1_hold_7), + .Wfc_7(Wfc_7), + .bf_7(bf_7), + .WoxrXtYt_1_7(WoxrXtYt_1_hold_7), + .Woc_7(Woc_7), + .bo_7(bo_7), + .WcxrXtYt_1_7(WcxrXtYt_1_hold_7), + .bc_7(bc_7), + .out_mt_7(stage2_mt_7), + .out_ct_7(stage2_Ct_7), + .Ct_1_8(Ctt_1_8), + .WixrXtYt_1_8(WixrXtYt_1_hold_8), + .Wic_8(Wic_8), + .bi_8(bi_8), + .WfxrXtYt_1_8(WfxrXtYt_1_hold_8), + .Wfc_8(Wfc_8), + .bf_8(bf_8), + .WoxrXtYt_1_8(WoxrXtYt_1_hold_8), + .Woc_8(Woc_8), + .bo_8(bo_8), + .WcxrXtYt_1_8(WcxrXtYt_1_hold_8), + .bc_8(bc_8), + .out_mt_8(stage2_mt_8), + .out_ct_8(stage2_Ct_8), + .Ct_1_9(Ctt_1_9), + .WixrXtYt_1_9(WixrXtYt_1_hold_9), + .Wic_9(Wic_9), + .bi_9(bi_9), + .WfxrXtYt_1_9(WfxrXtYt_1_hold_9), + .Wfc_9(Wfc_9), + .bf_9(bf_9), + .WoxrXtYt_1_9(WoxrXtYt_1_hold_9), + .Woc_9(Woc_9), + .bo_9(bo_9), + .WcxrXtYt_1_9(WcxrXtYt_1_hold_9), + .bc_9(bc_9), + .out_mt_9(stage2_mt_9), + .out_ct_9(stage2_Ct_9), + .Ct_1_10(Ctt_1_10), + .WixrXtYt_1_10(WixrXtYt_1_hold_10), + .Wic_10(Wic_10), + .bi_10(bi_10), + .WfxrXtYt_1_10(WfxrXtYt_1_hold_10), + .Wfc_10(Wfc_10), + .bf_10(bf_10), + .WoxrXtYt_1_10(WoxrXtYt_1_hold_10), + .Woc_10(Woc_10), + .bo_10(bo_10), + .WcxrXtYt_1_10(WcxrXtYt_1_hold_10), + .bc_10(bc_10), + .out_mt_10(stage2_mt_10), + .out_ct_10(stage2_Ct_10), + .Ct_1_11(Ctt_1_11), + .WixrXtYt_1_11(WixrXtYt_1_hold_11), + .Wic_11(Wic_11), + .bi_11(bi_11), + .WfxrXtYt_1_11(WfxrXtYt_1_hold_11), + .Wfc_11(Wfc_11), + .bf_11(bf_11), + .WoxrXtYt_1_11(WoxrXtYt_1_hold_11), + .Woc_11(Woc_11), + .bo_11(bo_11), + .WcxrXtYt_1_11(WcxrXtYt_1_hold_11), + .bc_11(bc_11), + .out_mt_11(stage2_mt_11), + .out_ct_11(stage2_Ct_11), + .Ct_1_12(Ctt_1_12), + .WixrXtYt_1_12(WixrXtYt_1_hold_12), + .Wic_12(Wic_12), + .bi_12(bi_12), + .WfxrXtYt_1_12(WfxrXtYt_1_hold_12), + .Wfc_12(Wfc_12), + .bf_12(bf_12), + .WoxrXtYt_1_12(WoxrXtYt_1_hold_12), + .Woc_12(Woc_12), + .bo_12(bo_12), + .WcxrXtYt_1_12(WcxrXtYt_1_hold_12), + .bc_12(bc_12), + .out_mt_12(stage2_mt_12), + .out_ct_12(stage2_Ct_12), + .Ct_1_13(Ctt_1_13), + .WixrXtYt_1_13(WixrXtYt_1_hold_13), + .Wic_13(Wic_13), + .bi_13(bi_13), + .WfxrXtYt_1_13(WfxrXtYt_1_hold_13), + .Wfc_13(Wfc_13), + .bf_13(bf_13), + .WoxrXtYt_1_13(WoxrXtYt_1_hold_13), + .Woc_13(Woc_13), + .bo_13(bo_13), + .WcxrXtYt_1_13(WcxrXtYt_1_hold_13), + .bc_13(bc_13), + .out_mt_13(stage2_mt_13), + .out_ct_13(stage2_Ct_13), + .Ct_1_14(Ctt_1_14), + .WixrXtYt_1_14(WixrXtYt_1_hold_14), + .Wic_14(Wic_14), + .bi_14(bi_14), + .WfxrXtYt_1_14(WfxrXtYt_1_hold_14), + .Wfc_14(Wfc_14), + .bf_14(bf_14), + .WoxrXtYt_1_14(WoxrXtYt_1_hold_14), + .Woc_14(Woc_14), + .bo_14(bo_14), + .WcxrXtYt_1_14(WcxrXtYt_1_hold_14), + .bc_14(bc_14), + .out_mt_14(stage2_mt_14), + .out_ct_14(stage2_Ct_14), + .Ct_1_15(Ctt_1_15), + .WixrXtYt_1_15(WixrXtYt_1_hold_15), + .Wic_15(Wic_15), + .bi_15(bi_15), + .WfxrXtYt_1_15(WfxrXtYt_1_hold_15), + .Wfc_15(Wfc_15), + .bf_15(bf_15), + .WoxrXtYt_1_15(WoxrXtYt_1_hold_15), + .Woc_15(Woc_15), + .bo_15(bo_15), + .WcxrXtYt_1_15(WcxrXtYt_1_hold_15), + .bc_15(bc_15), + .out_mt_15(stage2_mt_15), + .out_ct_15(stage2_Ct_15), + .o_valid(stage2_valid), + .o_ready(stage2_ready) +); + +wire [17:0] mt_0_0; +wire [17:0] Ct_0_0; +wire [17:0] mt_0_1; +wire [17:0] Ct_0_1; +wire [17:0] mt_0_2; +wire [17:0] Ct_0_2; +wire [17:0] mt_0_3; +wire [17:0] Ct_0_3; +wire [17:0] mt_0_4; +wire [17:0] Ct_0_4; +wire [17:0] mt_0_5; +wire [17:0] Ct_0_5; +wire [17:0] mt_0_6; +wire [17:0] Ct_0_6; +wire [17:0] mt_0_7; +wire [17:0] Ct_0_7; +wire [17:0] mt_0_8; +wire [17:0] Ct_0_8; +wire [17:0] mt_0_9; +wire [17:0] Ct_0_9; +wire [17:0] mt_0_10; +wire [17:0] Ct_0_10; +wire [17:0] mt_0_11; +wire [17:0] Ct_0_11; +wire [17:0] mt_0_12; +wire [17:0] Ct_0_12; +wire [17:0] mt_0_13; +wire [17:0] Ct_0_13; +wire [17:0] mt_0_14; +wire [17:0] Ct_0_14; +wire [17:0] mt_0_15; +wire [17:0] Ct_0_15; + +assign Ct_0_0 = stage2_Ct_0; +assign mt_0_0 = stage2_mt_0; +assign Ct_0_1 = stage2_Ct_1; +assign mt_0_1 = stage2_mt_1; +assign Ct_0_2 = stage2_Ct_2; +assign mt_0_2 = stage2_mt_2; +assign Ct_0_3 = stage2_Ct_3; +assign mt_0_3 = stage2_mt_3; +assign Ct_0_4 = stage2_Ct_4; +assign mt_0_4 = stage2_mt_4; +assign Ct_0_5 = stage2_Ct_5; +assign mt_0_5 = stage2_mt_5; +assign Ct_0_6 = stage2_Ct_6; +assign mt_0_6 = stage2_mt_6; +assign Ct_0_7 = stage2_Ct_7; +assign mt_0_7 = stage2_mt_7; +assign Ct_0_8 = stage2_Ct_8; +assign mt_0_8 = stage2_mt_8; +assign Ct_0_9 = stage2_Ct_9; +assign mt_0_9 = stage2_mt_9; +assign Ct_0_10 = stage2_Ct_10; +assign mt_0_10 = stage2_mt_10; +assign Ct_0_11 = stage2_Ct_11; +assign mt_0_11 = stage2_mt_11; +assign Ct_0_12 = stage2_Ct_12; +assign mt_0_12 = stage2_mt_12; +assign Ct_0_13 = stage2_Ct_13; +assign mt_0_13 = stage2_mt_13; +assign Ct_0_14 = stage2_Ct_14; +assign mt_0_14 = stage2_mt_14; +assign Ct_0_15 = stage2_Ct_15; +assign mt_0_15 = stage2_mt_15; + +// C-LSTM buffer between stage2 and stage3 +wire buffer_out_valid, pipelined_mt_valid, pipelined_Ct_valid; +wire [17:0] mt_pipelined_0; +wire [17:0] Ct_pipelined_0; +wire [17:0] out_mt_buffer_0; +wire [17:0] mt_pipelined_1; +wire [17:0] Ct_pipelined_1; +wire [17:0] out_mt_buffer_1; +wire [17:0] mt_pipelined_2; +wire [17:0] Ct_pipelined_2; +wire [17:0] out_mt_buffer_2; +wire [17:0] mt_pipelined_3; +wire [17:0] Ct_pipelined_3; +wire [17:0] out_mt_buffer_3; +wire [17:0] mt_pipelined_4; +wire [17:0] Ct_pipelined_4; +wire [17:0] out_mt_buffer_4; +wire [17:0] mt_pipelined_5; +wire [17:0] Ct_pipelined_5; +wire [17:0] out_mt_buffer_5; +wire [17:0] mt_pipelined_6; +wire [17:0] Ct_pipelined_6; +wire [17:0] out_mt_buffer_6; +wire [17:0] mt_pipelined_7; +wire [17:0] Ct_pipelined_7; +wire [17:0] out_mt_buffer_7; +wire [17:0] mt_pipelined_8; +wire [17:0] Ct_pipelined_8; +wire [17:0] out_mt_buffer_8; +wire [17:0] mt_pipelined_9; +wire [17:0] Ct_pipelined_9; +wire [17:0] out_mt_buffer_9; +wire [17:0] mt_pipelined_10; +wire [17:0] Ct_pipelined_10; +wire [17:0] out_mt_buffer_10; +wire [17:0] mt_pipelined_11; +wire [17:0] Ct_pipelined_11; +wire [17:0] out_mt_buffer_11; +wire [17:0] mt_pipelined_12; +wire [17:0] Ct_pipelined_12; +wire [17:0] out_mt_buffer_12; +wire [17:0] mt_pipelined_13; +wire [17:0] Ct_pipelined_13; +wire [17:0] out_mt_buffer_13; +wire [17:0] mt_pipelined_14; +wire [17:0] Ct_pipelined_14; +wire [17:0] out_mt_buffer_14; +wire [17:0] mt_pipelined_15; +wire [17:0] Ct_pipelined_15; +wire [17:0] out_mt_buffer_15; + +pipelined_input_18_1_16 pipelined_input_18_1_16_inst_mt ( + .clk(clk), + .reset(reset), + .enable(enable), + .load_input(stage2_valid), + .i_data_0_0(mt_0_0), + .i_data_0_1(mt_0_1), + .i_data_0_2(mt_0_2), + .i_data_0_3(mt_0_3), + .i_data_0_4(mt_0_4), + .i_data_0_5(mt_0_5), + .i_data_0_6(mt_0_6), + .i_data_0_7(mt_0_7), + .i_data_0_8(mt_0_8), + .i_data_0_9(mt_0_9), + .i_data_0_10(mt_0_10), + .i_data_0_11(mt_0_11), + .i_data_0_12(mt_0_12), + .i_data_0_13(mt_0_13), + .i_data_0_14(mt_0_14), + .i_data_0_15(mt_0_15), + .o_data_0(mt_pipelined_0), + .o_data_1(mt_pipelined_1), + .o_data_2(mt_pipelined_2), + .o_data_3(mt_pipelined_3), + .o_data_4(mt_pipelined_4), + .o_data_5(mt_pipelined_5), + .o_data_6(mt_pipelined_6), + .o_data_7(mt_pipelined_7), + .o_data_8(mt_pipelined_8), + .o_data_9(mt_pipelined_9), + .o_data_10(mt_pipelined_10), + .o_data_11(mt_pipelined_11), + .o_data_12(mt_pipelined_12), + .o_data_13(mt_pipelined_13), + .o_data_14(mt_pipelined_14), + .o_data_15(mt_pipelined_15), + .o_valid(pipelined_mt_valid) +); + +pipelined_input_18_1_16 pipelined_input_18_1_16_inst_Ct ( + .clk(clk), + .reset(reset), + .enable(enable), + .load_input(stage2_valid), + .i_data_0_0(Ct_0_0), + .i_data_0_1(Ct_0_1), + .i_data_0_2(Ct_0_2), + .i_data_0_3(Ct_0_3), + .i_data_0_4(Ct_0_4), + .i_data_0_5(Ct_0_5), + .i_data_0_6(Ct_0_6), + .i_data_0_7(Ct_0_7), + .i_data_0_8(Ct_0_8), + .i_data_0_9(Ct_0_9), + .i_data_0_10(Ct_0_10), + .i_data_0_11(Ct_0_11), + .i_data_0_12(Ct_0_12), + .i_data_0_13(Ct_0_13), + .i_data_0_14(Ct_0_14), + .i_data_0_15(Ct_0_15), + .o_data_0(Ct_pipelined_0), + .o_data_1(Ct_pipelined_1), + .o_data_2(Ct_pipelined_2), + .o_data_3(Ct_pipelined_3), + .o_data_4(Ct_pipelined_4), + .o_data_5(Ct_pipelined_5), + .o_data_6(Ct_pipelined_6), + .o_data_7(Ct_pipelined_7), + .o_data_8(Ct_pipelined_8), + .o_data_9(Ct_pipelined_9), + .o_data_10(Ct_pipelined_10), + .o_data_11(Ct_pipelined_11), + .o_data_12(Ct_pipelined_12), + .o_data_13(Ct_pipelined_13), + .o_data_14(Ct_pipelined_14), + .o_data_15(Ct_pipelined_15), + .o_valid(pipelined_Ct_valid) +); + +stage2_Ct_buffer_18_1_16_64 stage2_Ct_buffer_18_1_16_64_inst_nqkdbpzhek ( + .clk(clk), + .reset(reset), + .wen(pipelined_Ct_valid), + .ren(stage1_valid), + .i_Ct_0(Ct_pipelined_0), + .i_Ct_1(Ct_pipelined_1), + .i_Ct_2(Ct_pipelined_2), + .i_Ct_3(Ct_pipelined_3), + .i_Ct_4(Ct_pipelined_4), + .i_Ct_5(Ct_pipelined_5), + .i_Ct_6(Ct_pipelined_6), + .i_Ct_7(Ct_pipelined_7), + .i_Ct_8(Ct_pipelined_8), + .i_Ct_9(Ct_pipelined_9), + .i_Ct_10(Ct_pipelined_10), + .i_Ct_11(Ct_pipelined_11), + .i_Ct_12(Ct_pipelined_12), + .i_Ct_13(Ct_pipelined_13), + .i_Ct_14(Ct_pipelined_14), + .i_Ct_15(Ct_pipelined_15), + .o_Ct_0(Ctt_1_0), + .o_Ct_1(Ctt_1_1), + .o_Ct_2(Ctt_1_2), + .o_Ct_3(Ctt_1_3), + .o_Ct_4(Ctt_1_4), + .o_Ct_5(Ctt_1_5), + .o_Ct_6(Ctt_1_6), + .o_Ct_7(Ctt_1_7), + .o_Ct_8(Ctt_1_8), + .o_Ct_9(Ctt_1_9), + .o_Ct_10(Ctt_1_10), + .o_Ct_11(Ctt_1_11), + .o_Ct_12(Ctt_1_12), + .o_Ct_13(Ctt_1_13), + .o_Ct_14(Ctt_1_14), + .o_Ct_15(Ctt_1_15), + .o_valid() +); + +stage2_mt_buffer_18_1_16_64_32 stage2_mt_buffer_18_1_16_64_32_inst_ypoopgizlv ( + .clk(clk), + .reset(reset), + .i_valid(pipelined_mt_valid), + .data_0(mt_pipelined_0), + .q_0(out_mt_buffer_0), + .data_1(mt_pipelined_1), + .q_1(out_mt_buffer_1), + .data_2(mt_pipelined_2), + .q_2(out_mt_buffer_2), + .data_3(mt_pipelined_3), + .q_3(out_mt_buffer_3), + .data_4(mt_pipelined_4), + .q_4(out_mt_buffer_4), + .data_5(mt_pipelined_5), + .q_5(out_mt_buffer_5), + .data_6(mt_pipelined_6), + .q_6(out_mt_buffer_6), + .data_7(mt_pipelined_7), + .q_7(out_mt_buffer_7), + .data_8(mt_pipelined_8), + .q_8(out_mt_buffer_8), + .data_9(mt_pipelined_9), + .q_9(out_mt_buffer_9), + .data_10(mt_pipelined_10), + .q_10(out_mt_buffer_10), + .data_11(mt_pipelined_11), + .q_11(out_mt_buffer_11), + .data_12(mt_pipelined_12), + .q_12(out_mt_buffer_12), + .data_13(mt_pipelined_13), + .q_13(out_mt_buffer_13), + .data_14(mt_pipelined_14), + .q_14(out_mt_buffer_14), + .data_15(mt_pipelined_15), + .q_15(out_mt_buffer_15), + .o_valid(buffer_out_valid) +); + +// C-LSTM Stage 3 and inner-connections +wire stage3_valid, stage3_ready; +wire [17:0] new_Yt_0_0; +wire [17:0] new_Yt_0_1; +wire [17:0] new_Yt_0_2; +wire [17:0] new_Yt_0_3; +wire [17:0] new_Yt_0_4; +wire [17:0] new_Yt_0_5; +wire [17:0] new_Yt_0_6; +wire [17:0] new_Yt_0_7; +wire [17:0] new_Yt_0_8; +wire [17:0] new_Yt_0_9; +wire [17:0] new_Yt_0_10; +wire [17:0] new_Yt_0_11; +wire [17:0] new_Yt_0_12; +wire [17:0] new_Yt_0_13; +wire [17:0] new_Yt_0_14; +wire [17:0] new_Yt_0_15; + +C_LSTM_stage_3_18_10_64_2048_1_16_1 C_LSTM_stage_3_18_10_64_2048_1_16_1_inst_skqzqwirvv ( + .clk(clk), + .reset(reset), + .wdata(wdata_stage3), + .wen(wen_stage3), + .i_ready(enable), + .i_valid(buffer_out_valid), + .i_mt_0(out_mt_buffer_0), + .i_mt_1(out_mt_buffer_1), + .i_mt_2(out_mt_buffer_2), + .i_mt_3(out_mt_buffer_3), + .i_mt_4(out_mt_buffer_4), + .i_mt_5(out_mt_buffer_5), + .i_mt_6(out_mt_buffer_6), + .i_mt_7(out_mt_buffer_7), + .i_mt_8(out_mt_buffer_8), + .i_mt_9(out_mt_buffer_9), + .i_mt_10(out_mt_buffer_10), + .i_mt_11(out_mt_buffer_11), + .i_mt_12(out_mt_buffer_12), + .i_mt_13(out_mt_buffer_13), + .i_mt_14(out_mt_buffer_14), + .i_mt_15(out_mt_buffer_15), + .o_Yt_0_0(new_Yt_0_0), + .o_Yt_0_1(new_Yt_0_1), + .o_Yt_0_2(new_Yt_0_2), + .o_Yt_0_3(new_Yt_0_3), + .o_Yt_0_4(new_Yt_0_4), + .o_Yt_0_5(new_Yt_0_5), + .o_Yt_0_6(new_Yt_0_6), + .o_Yt_0_7(new_Yt_0_7), + .o_Yt_0_8(new_Yt_0_8), + .o_Yt_0_9(new_Yt_0_9), + .o_Yt_0_10(new_Yt_0_10), + .o_Yt_0_11(new_Yt_0_11), + .o_Yt_0_12(new_Yt_0_12), + .o_Yt_0_13(new_Yt_0_13), + .o_Yt_0_14(new_Yt_0_14), + .o_Yt_0_15(new_Yt_0_15), + .o_valid(stage3_valid), + .o_ready(stage3_ready) +); + +assign o_Yt_0_0 = new_Yt_0_0; +assign o_Yt_0_1 = new_Yt_0_1; +assign o_Yt_0_2 = new_Yt_0_2; +assign o_Yt_0_3 = new_Yt_0_3; +assign o_Yt_0_4 = new_Yt_0_4; +assign o_Yt_0_5 = new_Yt_0_5; +assign o_Yt_0_6 = new_Yt_0_6; +assign o_Yt_0_7 = new_Yt_0_7; +assign o_Yt_0_8 = new_Yt_0_8; +assign o_Yt_0_9 = new_Yt_0_9; +assign o_Yt_0_10 = new_Yt_0_10; +assign o_Yt_0_11 = new_Yt_0_11; +assign o_Yt_0_12 = new_Yt_0_12; +assign o_Yt_0_13 = new_Yt_0_13; +assign o_Yt_0_14 = new_Yt_0_14; +assign o_Yt_0_15 = new_Yt_0_15; + +// Stage 3 buffer and inter-connections +wire [17:0] pipelined_Yt_0; +wire [17:0] pipelined_Yt_1; +wire [17:0] pipelined_Yt_2; +wire [17:0] pipelined_Yt_3; +wire [17:0] pipelined_Yt_4; +wire [17:0] pipelined_Yt_5; +wire [17:0] pipelined_Yt_6; +wire [17:0] pipelined_Yt_7; +wire [17:0] pipelined_Yt_8; +wire [17:0] pipelined_Yt_9; +wire [17:0] pipelined_Yt_10; +wire [17:0] pipelined_Yt_11; +wire [17:0] pipelined_Yt_12; +wire [17:0] pipelined_Yt_13; +wire [17:0] pipelined_Yt_14; +wire [17:0] pipelined_Yt_15; +wire pipelined_Yt_valid; + +pipelined_input_18_1_16 pipelined_input_18_1_16_inst_Y ( + .clk(clk), + .reset(reset), + .enable(enable), + .load_input(stage3_valid), + .i_data_0_0(new_Yt_0_0), + .i_data_0_1(new_Yt_0_1), + .i_data_0_2(new_Yt_0_2), + .i_data_0_3(new_Yt_0_3), + .i_data_0_4(new_Yt_0_4), + .i_data_0_5(new_Yt_0_5), + .i_data_0_6(new_Yt_0_6), + .i_data_0_7(new_Yt_0_7), + .i_data_0_8(new_Yt_0_8), + .i_data_0_9(new_Yt_0_9), + .i_data_0_10(new_Yt_0_10), + .i_data_0_11(new_Yt_0_11), + .i_data_0_12(new_Yt_0_12), + .i_data_0_13(new_Yt_0_13), + .i_data_0_14(new_Yt_0_14), + .i_data_0_15(new_Yt_0_15), + .o_data_0(pipelined_Yt_0), + .o_data_1(pipelined_Yt_1), + .o_data_2(pipelined_Yt_2), + .o_data_3(pipelined_Yt_3), + .o_data_4(pipelined_Yt_4), + .o_data_5(pipelined_Yt_5), + .o_data_6(pipelined_Yt_6), + .o_data_7(pipelined_Yt_7), + .o_data_8(pipelined_Yt_8), + .o_data_9(pipelined_Yt_9), + .o_data_10(pipelined_Yt_10), + .o_data_11(pipelined_Yt_11), + .o_data_12(pipelined_Yt_12), + .o_data_13(pipelined_Yt_13), + .o_data_14(pipelined_Yt_14), + .o_data_15(pipelined_Yt_15), + .o_valid(pipelined_Yt_valid) +); + +stage3_X_Y_buffer_18_16_1_10_32_64 stage3_X_Y_buffer_18_16_1_10_32_64_inst_knbkoairvn ( + .clk(clk), + .reset(reset), + .i_X_valid(i_valid), + .i_Y_valid(pipelined_Yt_valid), + .feed_start(start_compute), + .i_X_data_0(i_X_data_0), + .i_Y_data_0(pipelined_Yt_0), + .o_data_0(i_data_0), + .i_X_data_1(i_X_data_1), + .i_Y_data_1(pipelined_Yt_1), + .o_data_1(i_data_1), + .i_X_data_2(i_X_data_2), + .i_Y_data_2(pipelined_Yt_2), + .o_data_2(i_data_2), + .i_X_data_3(i_X_data_3), + .i_Y_data_3(pipelined_Yt_3), + .o_data_3(i_data_3), + .i_X_data_4(i_X_data_4), + .i_Y_data_4(pipelined_Yt_4), + .o_data_4(i_data_4), + .i_X_data_5(i_X_data_5), + .i_Y_data_5(pipelined_Yt_5), + .o_data_5(i_data_5), + .i_X_data_6(i_X_data_6), + .i_Y_data_6(pipelined_Yt_6), + .o_data_6(i_data_6), + .i_X_data_7(i_X_data_7), + .i_Y_data_7(pipelined_Yt_7), + .o_data_7(i_data_7), + .i_X_data_8(i_X_data_8), + .i_Y_data_8(pipelined_Yt_8), + .o_data_8(i_data_8), + .i_X_data_9(i_X_data_9), + .i_Y_data_9(pipelined_Yt_9), + .o_data_9(i_data_9), + .i_X_data_10(i_X_data_10), + .i_Y_data_10(pipelined_Yt_10), + .o_data_10(i_data_10), + .i_X_data_11(i_X_data_11), + .i_Y_data_11(pipelined_Yt_11), + .o_data_11(i_data_11), + .i_X_data_12(i_X_data_12), + .i_Y_data_12(pipelined_Yt_12), + .o_data_12(i_data_12), + .i_X_data_13(i_X_data_13), + .i_Y_data_13(pipelined_Yt_13), + .o_data_13(i_data_13), + .i_X_data_14(i_X_data_14), + .i_Y_data_14(pipelined_Yt_14), + .o_data_14(i_data_14), + .i_X_data_15(i_X_data_15), + .i_Y_data_15(pipelined_Yt_15), + .o_data_15(i_data_15), + .o_valid(out_X_Y_buffer_valid), + .o_ready(o_ready) +); + +assign o_valid = stage3_valid; + +endmodule + +module spram ( + clk, + addr, + we, + data, + out +); + +parameter AWIDTH=10; +parameter NUM_WORDS=1024; +parameter DWIDTH=32; + +input clk; +input [(AWIDTH-1):0] addr; +input we; +input [(DWIDTH-1):0] data; +output reg [(DWIDTH-1):0] out; + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram[NUM_WORDS-1:0]; +always @ (posedge clk) begin + if (we) begin + ram[addr] <= data; + end + out <= ram[addr]; +end + +`else + +defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; +defparam u_single_port_ram.DATA_WIDTH = DWIDTH; +single_port_ram u_single_port_ram( + .addr(addr), + .we(we), + .data(data), + .out(out), + .clk(clk) +); + +`endif + +endmodule + +module dpram ( + clk, + addr1, + addr2, + we1, + we2, + data1, + data2, + out1, + out2 +); + +parameter AWIDTH=10; +parameter NUM_WORDS=1024; +parameter DWIDTH=32; + +input clk; +input [(AWIDTH-1):0] addr1; +input [(AWIDTH-1):0] addr2; +input we1; +input we2; +input [(DWIDTH-1):0] data1; +input [(DWIDTH-1):0] data2; +output reg [(DWIDTH-1):0] out1; +output reg [(DWIDTH-1):0] out2; + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram[NUM_WORDS-1:0]; +always @ (posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end + out1 <= ram[addr1]; +end + +always @ (posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end + out2 <= ram[addr2]; +end + +`else + +defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; +defparam u_dual_port_ram.DATA_WIDTH = DWIDTH; +dual_port_ram u_dual_port_ram( + .addr1(addr1), + .we1(we1), + .data1(data1), + .out1(out1), + .addr2(addr2), + .we2(we2), + .data2(data2), + .out2(out2), + .clk(clk) +); +`endif + +endmodule + + +module stage1_parameter_buffer_18_1_16_42_2688 ( + input clk, + input reset, + input [161:0] wdata, + input [7:0] wen, + output [17:0] Wixr_real_0_0, + output [17:0] Wixr_imag_0_0, + output [17:0] Wfxr_real_0_0, + output [17:0] Wfxr_imag_0_0, + output [17:0] Woxr_real_0_0, + output [17:0] Woxr_imag_0_0, + output [17:0] Wcxr_real_0_0, + output [17:0] Wcxr_imag_0_0, + output [17:0] Wixr_real_0_1, + output [17:0] Wixr_imag_0_1, + output [17:0] Wfxr_real_0_1, + output [17:0] Wfxr_imag_0_1, + output [17:0] Woxr_real_0_1, + output [17:0] Woxr_imag_0_1, + output [17:0] Wcxr_real_0_1, + output [17:0] Wcxr_imag_0_1, + output [17:0] Wixr_real_0_2, + output [17:0] Wixr_imag_0_2, + output [17:0] Wfxr_real_0_2, + output [17:0] Wfxr_imag_0_2, + output [17:0] Woxr_real_0_2, + output [17:0] Woxr_imag_0_2, + output [17:0] Wcxr_real_0_2, + output [17:0] Wcxr_imag_0_2, + output [17:0] Wixr_real_0_3, + output [17:0] Wixr_imag_0_3, + output [17:0] Wfxr_real_0_3, + output [17:0] Wfxr_imag_0_3, + output [17:0] Woxr_real_0_3, + output [17:0] Woxr_imag_0_3, + output [17:0] Wcxr_real_0_3, + output [17:0] Wcxr_imag_0_3, + output [17:0] Wixr_real_0_4, + output [17:0] Wixr_imag_0_4, + output [17:0] Wfxr_real_0_4, + output [17:0] Wfxr_imag_0_4, + output [17:0] Woxr_real_0_4, + output [17:0] Woxr_imag_0_4, + output [17:0] Wcxr_real_0_4, + output [17:0] Wcxr_imag_0_4, + output [17:0] Wixr_real_0_5, + output [17:0] Wixr_imag_0_5, + output [17:0] Wfxr_real_0_5, + output [17:0] Wfxr_imag_0_5, + output [17:0] Woxr_real_0_5, + output [17:0] Woxr_imag_0_5, + output [17:0] Wcxr_real_0_5, + output [17:0] Wcxr_imag_0_5, + output [17:0] Wixr_real_0_6, + output [17:0] Wixr_imag_0_6, + output [17:0] Wfxr_real_0_6, + output [17:0] Wfxr_imag_0_6, + output [17:0] Woxr_real_0_6, + output [17:0] Woxr_imag_0_6, + output [17:0] Wcxr_real_0_6, + output [17:0] Wcxr_imag_0_6, + output [17:0] Wixr_real_0_7, + output [17:0] Wixr_imag_0_7, + output [17:0] Wfxr_real_0_7, + output [17:0] Wfxr_imag_0_7, + output [17:0] Woxr_real_0_7, + output [17:0] Woxr_imag_0_7, + output [17:0] Wcxr_real_0_7, + output [17:0] Wcxr_imag_0_7, + output [17:0] Wixr_real_0_8, + output [17:0] Wixr_imag_0_8, + output [17:0] Wfxr_real_0_8, + output [17:0] Wfxr_imag_0_8, + output [17:0] Woxr_real_0_8, + output [17:0] Woxr_imag_0_8, + output [17:0] Wcxr_real_0_8, + output [17:0] Wcxr_imag_0_8, + input incr_index +); + +// A counter that counts how many sub blocks we have processed +wire [13:0] input_index_counter; +counter_41_1 counter_41_1_inst_irsyluobvo ( + .clk(clk), + .reset(reset), + .ena(incr_index), + .count(input_index_counter) +); + +wire incr_row_index; +assign incr_row_index = (input_index_counter == 41); +wire counter_enable_row_index; +assign counter_enable_row_index = (incr_row_index & incr_index); + +// A counter that records which weight portion to use +wire [13:0] weight_row_index_counter; +counter_63_1 counter_63_1_inst_rgewntpept ( + .clk(clk), + .reset(reset), + .ena(counter_enable_row_index), + .count(weight_row_index_counter) +); + +reg [13:0] weight_index; +always @ (*) begin + weight_index = weight_row_index_counter * 14'd42 + input_index_counter; +end + +// Input Gate +weight_buffer_18_9_42_1_2688 Wixr_real_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[0]), + .q_0_0(Wixr_real_0_0), + .q_0_1(Wixr_real_0_1), + .q_0_2(Wixr_real_0_2), + .q_0_3(Wixr_real_0_3), + .q_0_4(Wixr_real_0_4), + .q_0_5(Wixr_real_0_5), + .q_0_6(Wixr_real_0_6), + .q_0_7(Wixr_real_0_7), + .q_0_8(Wixr_real_0_8), + .index(weight_index) +); + +weight_buffer_18_9_42_1_2688 Wixr_imag_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[1]), + .q_0_0(Wixr_imag_0_0), + .q_0_1(Wixr_imag_0_1), + .q_0_2(Wixr_imag_0_2), + .q_0_3(Wixr_imag_0_3), + .q_0_4(Wixr_imag_0_4), + .q_0_5(Wixr_imag_0_5), + .q_0_6(Wixr_imag_0_6), + .q_0_7(Wixr_imag_0_7), + .q_0_8(Wixr_imag_0_8), + .index(weight_index) +); + +// Forget Gate +weight_buffer_18_9_42_1_2688 Wfxr_real_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[2]), + .q_0_0(Wfxr_real_0_0), + .q_0_1(Wfxr_real_0_1), + .q_0_2(Wfxr_real_0_2), + .q_0_3(Wfxr_real_0_3), + .q_0_4(Wfxr_real_0_4), + .q_0_5(Wfxr_real_0_5), + .q_0_6(Wfxr_real_0_6), + .q_0_7(Wfxr_real_0_7), + .q_0_8(Wfxr_real_0_8), + .index(weight_index) +); + +weight_buffer_18_9_42_1_2688 Wfxr_imag_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[7]), + .q_0_0(Wfxr_imag_0_0), + .q_0_1(Wfxr_imag_0_1), + .q_0_2(Wfxr_imag_0_2), + .q_0_3(Wfxr_imag_0_3), + .q_0_4(Wfxr_imag_0_4), + .q_0_5(Wfxr_imag_0_5), + .q_0_6(Wfxr_imag_0_6), + .q_0_7(Wfxr_imag_0_7), + .q_0_8(Wfxr_imag_0_8), + .index(weight_index) +); + +// Output Gate +weight_buffer_18_9_42_1_2688 Woxr_real_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[3]), + .q_0_0(Woxr_real_0_0), + .q_0_1(Woxr_real_0_1), + .q_0_2(Woxr_real_0_2), + .q_0_3(Woxr_real_0_3), + .q_0_4(Woxr_real_0_4), + .q_0_5(Woxr_real_0_5), + .q_0_6(Woxr_real_0_6), + .q_0_7(Woxr_real_0_7), + .q_0_8(Woxr_real_0_8), + .index(weight_index) +); + +weight_buffer_18_9_42_1_2688 Woxr_imag_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[4]), + .q_0_0(Woxr_imag_0_0), + .q_0_1(Woxr_imag_0_1), + .q_0_2(Woxr_imag_0_2), + .q_0_3(Woxr_imag_0_3), + .q_0_4(Woxr_imag_0_4), + .q_0_5(Woxr_imag_0_5), + .q_0_6(Woxr_imag_0_6), + .q_0_7(Woxr_imag_0_7), + .q_0_8(Woxr_imag_0_8), + .index(weight_index) +); + +// Output Activation Gate +weight_buffer_18_9_42_1_2688 Wcxr_real_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[5]), + .q_0_0(Wcxr_real_0_0), + .q_0_1(Wcxr_real_0_1), + .q_0_2(Wcxr_real_0_2), + .q_0_3(Wcxr_real_0_3), + .q_0_4(Wcxr_real_0_4), + .q_0_5(Wcxr_real_0_5), + .q_0_6(Wcxr_real_0_6), + .q_0_7(Wcxr_real_0_7), + .q_0_8(Wcxr_real_0_8), + .index(weight_index) +); + +weight_buffer_18_9_42_1_2688 Wcxr_imag_buffer ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[6]), + .q_0_0(Wcxr_imag_0_0), + .q_0_1(Wcxr_imag_0_1), + .q_0_2(Wcxr_imag_0_2), + .q_0_3(Wcxr_imag_0_3), + .q_0_4(Wcxr_imag_0_4), + .q_0_5(Wcxr_imag_0_5), + .q_0_6(Wcxr_imag_0_6), + .q_0_7(Wcxr_imag_0_7), + .q_0_8(Wcxr_imag_0_8), + .index(weight_index) +); + +endmodule + + +module counter_41_1 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd1) <= 41) begin + count <= count + 14'd1; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module counter_63_1 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd1) <= 63) begin + count <= count + 14'd1; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module weight_buffer_18_9_42_1_2688 ( + input clk, + input rst, + input [161:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + input [10:0] index +); + +wire [161:0] packed_result_0; +reg [10:0] addrs_0; +reg [10:0] addrs_base_0; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + end else begin + addrs_0 <= index + addrs_base_0; + end +end + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; + +endmodule + +module shift_register_group_18_16_3 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input reset +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_3 shift_register_unit_18_3_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +endmodule + +module shift_register_unit_18_3 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +reg [17:0] shift_registers_1; +reg [17:0] shift_registers_2; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + shift_registers_1 <= 18'd0; + shift_registers_2 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + end +end + +assign out = shift_registers_2; + +endmodule + +module shift_register_unit_1_3 ( + input clk, + input reset, + input enable, + input [0:0] in, + output [0:0] out +); + +reg [0:0] shift_registers_0; +reg [0:0] shift_registers_1; +reg [0:0] shift_registers_2; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 1'd0; + shift_registers_1 <= 1'd0; + shift_registers_2 <= 1'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + end +end + +assign out = shift_registers_2; + +endmodule + +module C_LSTM_stage_1_18_10_160_512_1_16_1 ( + input clk, + input reset, + input enable, + input i_ready, + input [17:0] i_Xt_Yt_1_0, + input [17:0] i_Xt_Yt_1_1, + input [17:0] i_Xt_Yt_1_2, + input [17:0] i_Xt_Yt_1_3, + input [17:0] i_Xt_Yt_1_4, + input [17:0] i_Xt_Yt_1_5, + input [17:0] i_Xt_Yt_1_6, + input [17:0] i_Xt_Yt_1_7, + input [17:0] i_Xt_Yt_1_8, + input [17:0] i_Xt_Yt_1_9, + input [17:0] i_Xt_Yt_1_10, + input [17:0] i_Xt_Yt_1_11, + input [17:0] i_Xt_Yt_1_12, + input [17:0] i_Xt_Yt_1_13, + input [17:0] i_Xt_Yt_1_14, + input [17:0] i_Xt_Yt_1_15, + input [17:0] i_Wixr_real_0_0, + input [17:0] i_Wixr_imag_0_0, + input [17:0] i_Wfxr_real_0_0, + input [17:0] i_Wfxr_imag_0_0, + input [17:0] i_Woxr_real_0_0, + input [17:0] i_Woxr_imag_0_0, + input [17:0] i_Wcxr_real_0_0, + input [17:0] i_Wcxr_imag_0_0, + input [17:0] i_Wixr_real_0_1, + input [17:0] i_Wixr_imag_0_1, + input [17:0] i_Wfxr_real_0_1, + input [17:0] i_Wfxr_imag_0_1, + input [17:0] i_Woxr_real_0_1, + input [17:0] i_Woxr_imag_0_1, + input [17:0] i_Wcxr_real_0_1, + input [17:0] i_Wcxr_imag_0_1, + input [17:0] i_Wixr_real_0_2, + input [17:0] i_Wixr_imag_0_2, + input [17:0] i_Wfxr_real_0_2, + input [17:0] i_Wfxr_imag_0_2, + input [17:0] i_Woxr_real_0_2, + input [17:0] i_Woxr_imag_0_2, + input [17:0] i_Wcxr_real_0_2, + input [17:0] i_Wcxr_imag_0_2, + input [17:0] i_Wixr_real_0_3, + input [17:0] i_Wixr_imag_0_3, + input [17:0] i_Wfxr_real_0_3, + input [17:0] i_Wfxr_imag_0_3, + input [17:0] i_Woxr_real_0_3, + input [17:0] i_Woxr_imag_0_3, + input [17:0] i_Wcxr_real_0_3, + input [17:0] i_Wcxr_imag_0_3, + input [17:0] i_Wixr_real_0_4, + input [17:0] i_Wixr_imag_0_4, + input [17:0] i_Wfxr_real_0_4, + input [17:0] i_Wfxr_imag_0_4, + input [17:0] i_Woxr_real_0_4, + input [17:0] i_Woxr_imag_0_4, + input [17:0] i_Wcxr_real_0_4, + input [17:0] i_Wcxr_imag_0_4, + input [17:0] i_Wixr_real_0_5, + input [17:0] i_Wixr_imag_0_5, + input [17:0] i_Wfxr_real_0_5, + input [17:0] i_Wfxr_imag_0_5, + input [17:0] i_Woxr_real_0_5, + input [17:0] i_Woxr_imag_0_5, + input [17:0] i_Wcxr_real_0_5, + input [17:0] i_Wcxr_imag_0_5, + input [17:0] i_Wixr_real_0_6, + input [17:0] i_Wixr_imag_0_6, + input [17:0] i_Wfxr_real_0_6, + input [17:0] i_Wfxr_imag_0_6, + input [17:0] i_Woxr_real_0_6, + input [17:0] i_Woxr_imag_0_6, + input [17:0] i_Wcxr_real_0_6, + input [17:0] i_Wcxr_imag_0_6, + input [17:0] i_Wixr_real_0_7, + input [17:0] i_Wixr_imag_0_7, + input [17:0] i_Wfxr_real_0_7, + input [17:0] i_Wfxr_imag_0_7, + input [17:0] i_Woxr_real_0_7, + input [17:0] i_Woxr_imag_0_7, + input [17:0] i_Wcxr_real_0_7, + input [17:0] i_Wcxr_imag_0_7, + input [17:0] i_Wixr_real_0_8, + input [17:0] i_Wixr_imag_0_8, + input [17:0] i_Wfxr_real_0_8, + input [17:0] i_Wfxr_imag_0_8, + input [17:0] i_Woxr_real_0_8, + input [17:0] i_Woxr_imag_0_8, + input [17:0] i_Wcxr_real_0_8, + input [17:0] i_Wcxr_imag_0_8, + output o_valid, + output o_ready, + output [17:0] o_WixrXtYt_1_0_0, + output [17:0] o_WfxrXtYt_1_0_0, + output [17:0] o_WoxrXtYt_1_0_0, + output [17:0] o_WcxrXtYt_1_0_0, + output [17:0] o_WixrXtYt_1_0_1, + output [17:0] o_WfxrXtYt_1_0_1, + output [17:0] o_WoxrXtYt_1_0_1, + output [17:0] o_WcxrXtYt_1_0_1, + output [17:0] o_WixrXtYt_1_0_2, + output [17:0] o_WfxrXtYt_1_0_2, + output [17:0] o_WoxrXtYt_1_0_2, + output [17:0] o_WcxrXtYt_1_0_2, + output [17:0] o_WixrXtYt_1_0_3, + output [17:0] o_WfxrXtYt_1_0_3, + output [17:0] o_WoxrXtYt_1_0_3, + output [17:0] o_WcxrXtYt_1_0_3, + output [17:0] o_WixrXtYt_1_0_4, + output [17:0] o_WfxrXtYt_1_0_4, + output [17:0] o_WoxrXtYt_1_0_4, + output [17:0] o_WcxrXtYt_1_0_4, + output [17:0] o_WixrXtYt_1_0_5, + output [17:0] o_WfxrXtYt_1_0_5, + output [17:0] o_WoxrXtYt_1_0_5, + output [17:0] o_WcxrXtYt_1_0_5, + output [17:0] o_WixrXtYt_1_0_6, + output [17:0] o_WfxrXtYt_1_0_6, + output [17:0] o_WoxrXtYt_1_0_6, + output [17:0] o_WcxrXtYt_1_0_6, + output [17:0] o_WixrXtYt_1_0_7, + output [17:0] o_WfxrXtYt_1_0_7, + output [17:0] o_WoxrXtYt_1_0_7, + output [17:0] o_WcxrXtYt_1_0_7, + output [17:0] o_WixrXtYt_1_0_8, + output [17:0] o_WfxrXtYt_1_0_8, + output [17:0] o_WoxrXtYt_1_0_8, + output [17:0] o_WcxrXtYt_1_0_8, + output [17:0] o_WixrXtYt_1_0_9, + output [17:0] o_WfxrXtYt_1_0_9, + output [17:0] o_WoxrXtYt_1_0_9, + output [17:0] o_WcxrXtYt_1_0_9, + output [17:0] o_WixrXtYt_1_0_10, + output [17:0] o_WfxrXtYt_1_0_10, + output [17:0] o_WoxrXtYt_1_0_10, + output [17:0] o_WcxrXtYt_1_0_10, + output [17:0] o_WixrXtYt_1_0_11, + output [17:0] o_WfxrXtYt_1_0_11, + output [17:0] o_WoxrXtYt_1_0_11, + output [17:0] o_WcxrXtYt_1_0_11, + output [17:0] o_WixrXtYt_1_0_12, + output [17:0] o_WfxrXtYt_1_0_12, + output [17:0] o_WoxrXtYt_1_0_12, + output [17:0] o_WcxrXtYt_1_0_12, + output [17:0] o_WixrXtYt_1_0_13, + output [17:0] o_WfxrXtYt_1_0_13, + output [17:0] o_WoxrXtYt_1_0_13, + output [17:0] o_WcxrXtYt_1_0_13, + output [17:0] o_WixrXtYt_1_0_14, + output [17:0] o_WfxrXtYt_1_0_14, + output [17:0] o_WoxrXtYt_1_0_14, + output [17:0] o_WcxrXtYt_1_0_14, + output [17:0] o_WixrXtYt_1_0_15, + output [17:0] o_WfxrXtYt_1_0_15, + output [17:0] o_WoxrXtYt_1_0_15, + output [17:0] o_WcxrXtYt_1_0_15, + input i_valid +); + +wire input_gate_mult_valid, forget_gate_mult_valid, output_gate_mult_valid, output_act_mult_valid; +wire input_gate_mult_ready, forget_gate_mult_ready, output_gate_mult_ready, output_act_mult_ready; + +// Input Gate Multiplication +matrix_times_two_vectors_18_10_1_672_16_1 input_gate_mult ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_ready(i_ready), + .i_valid(i_valid), + .i_Xt_Yt_1_0(i_Xt_Yt_1_0), + .i_Xt_Yt_1_1(i_Xt_Yt_1_1), + .i_Xt_Yt_1_2(i_Xt_Yt_1_2), + .i_Xt_Yt_1_3(i_Xt_Yt_1_3), + .i_Xt_Yt_1_4(i_Xt_Yt_1_4), + .i_Xt_Yt_1_5(i_Xt_Yt_1_5), + .i_Xt_Yt_1_6(i_Xt_Yt_1_6), + .i_Xt_Yt_1_7(i_Xt_Yt_1_7), + .i_Xt_Yt_1_8(i_Xt_Yt_1_8), + .i_Xt_Yt_1_9(i_Xt_Yt_1_9), + .i_Xt_Yt_1_10(i_Xt_Yt_1_10), + .i_Xt_Yt_1_11(i_Xt_Yt_1_11), + .i_Xt_Yt_1_12(i_Xt_Yt_1_12), + .i_Xt_Yt_1_13(i_Xt_Yt_1_13), + .i_Xt_Yt_1_14(i_Xt_Yt_1_14), + .i_Xt_Yt_1_15(i_Xt_Yt_1_15), + .i_Wxr_real_0_0(i_Wixr_real_0_0), + .i_Wxr_imag_0_0(i_Wixr_imag_0_0), + .i_Wxr_real_0_1(i_Wixr_real_0_1), + .i_Wxr_imag_0_1(i_Wixr_imag_0_1), + .i_Wxr_real_0_2(i_Wixr_real_0_2), + .i_Wxr_imag_0_2(i_Wixr_imag_0_2), + .i_Wxr_real_0_3(i_Wixr_real_0_3), + .i_Wxr_imag_0_3(i_Wixr_imag_0_3), + .i_Wxr_real_0_4(i_Wixr_real_0_4), + .i_Wxr_imag_0_4(i_Wixr_imag_0_4), + .i_Wxr_real_0_5(i_Wixr_real_0_5), + .i_Wxr_imag_0_5(i_Wixr_imag_0_5), + .i_Wxr_real_0_6(i_Wixr_real_0_6), + .i_Wxr_imag_0_6(i_Wixr_imag_0_6), + .i_Wxr_real_0_7(i_Wixr_real_0_7), + .i_Wxr_imag_0_7(i_Wixr_imag_0_7), + .i_Wxr_real_0_8(i_Wixr_real_0_8), + .i_Wxr_imag_0_8(i_Wixr_imag_0_8), + .o_W_times_X_Y_0_0(o_WixrXtYt_1_0_0), + .o_W_times_X_Y_0_1(o_WixrXtYt_1_0_1), + .o_W_times_X_Y_0_2(o_WixrXtYt_1_0_2), + .o_W_times_X_Y_0_3(o_WixrXtYt_1_0_3), + .o_W_times_X_Y_0_4(o_WixrXtYt_1_0_4), + .o_W_times_X_Y_0_5(o_WixrXtYt_1_0_5), + .o_W_times_X_Y_0_6(o_WixrXtYt_1_0_6), + .o_W_times_X_Y_0_7(o_WixrXtYt_1_0_7), + .o_W_times_X_Y_0_8(o_WixrXtYt_1_0_8), + .o_W_times_X_Y_0_9(o_WixrXtYt_1_0_9), + .o_W_times_X_Y_0_10(o_WixrXtYt_1_0_10), + .o_W_times_X_Y_0_11(o_WixrXtYt_1_0_11), + .o_W_times_X_Y_0_12(o_WixrXtYt_1_0_12), + .o_W_times_X_Y_0_13(o_WixrXtYt_1_0_13), + .o_W_times_X_Y_0_14(o_WixrXtYt_1_0_14), + .o_W_times_X_Y_0_15(o_WixrXtYt_1_0_15), + .o_valid(input_gate_mult_valid), + .o_ready(input_gate_mult_ready) +); + +// Forget Gate Multiplication +matrix_times_two_vectors_18_10_1_672_16_1 forget_gate_mult ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_ready(i_ready), + .i_valid(i_valid), + .i_Xt_Yt_1_0(i_Xt_Yt_1_0), + .i_Xt_Yt_1_1(i_Xt_Yt_1_1), + .i_Xt_Yt_1_2(i_Xt_Yt_1_2), + .i_Xt_Yt_1_3(i_Xt_Yt_1_3), + .i_Xt_Yt_1_4(i_Xt_Yt_1_4), + .i_Xt_Yt_1_5(i_Xt_Yt_1_5), + .i_Xt_Yt_1_6(i_Xt_Yt_1_6), + .i_Xt_Yt_1_7(i_Xt_Yt_1_7), + .i_Xt_Yt_1_8(i_Xt_Yt_1_8), + .i_Xt_Yt_1_9(i_Xt_Yt_1_9), + .i_Xt_Yt_1_10(i_Xt_Yt_1_10), + .i_Xt_Yt_1_11(i_Xt_Yt_1_11), + .i_Xt_Yt_1_12(i_Xt_Yt_1_12), + .i_Xt_Yt_1_13(i_Xt_Yt_1_13), + .i_Xt_Yt_1_14(i_Xt_Yt_1_14), + .i_Xt_Yt_1_15(i_Xt_Yt_1_15), + .i_Wxr_real_0_0(i_Wfxr_real_0_0), + .i_Wxr_imag_0_0(i_Wfxr_imag_0_0), + .i_Wxr_real_0_1(i_Wfxr_real_0_1), + .i_Wxr_imag_0_1(i_Wfxr_imag_0_1), + .i_Wxr_real_0_2(i_Wfxr_real_0_2), + .i_Wxr_imag_0_2(i_Wfxr_imag_0_2), + .i_Wxr_real_0_3(i_Wfxr_real_0_3), + .i_Wxr_imag_0_3(i_Wfxr_imag_0_3), + .i_Wxr_real_0_4(i_Wfxr_real_0_4), + .i_Wxr_imag_0_4(i_Wfxr_imag_0_4), + .i_Wxr_real_0_5(i_Wfxr_real_0_5), + .i_Wxr_imag_0_5(i_Wfxr_imag_0_5), + .i_Wxr_real_0_6(i_Wfxr_real_0_6), + .i_Wxr_imag_0_6(i_Wfxr_imag_0_6), + .i_Wxr_real_0_7(i_Wfxr_real_0_7), + .i_Wxr_imag_0_7(i_Wfxr_imag_0_7), + .i_Wxr_real_0_8(i_Wfxr_real_0_8), + .i_Wxr_imag_0_8(i_Wfxr_imag_0_8), + .o_W_times_X_Y_0_0(o_WfxrXtYt_1_0_0), + .o_W_times_X_Y_0_1(o_WfxrXtYt_1_0_1), + .o_W_times_X_Y_0_2(o_WfxrXtYt_1_0_2), + .o_W_times_X_Y_0_3(o_WfxrXtYt_1_0_3), + .o_W_times_X_Y_0_4(o_WfxrXtYt_1_0_4), + .o_W_times_X_Y_0_5(o_WfxrXtYt_1_0_5), + .o_W_times_X_Y_0_6(o_WfxrXtYt_1_0_6), + .o_W_times_X_Y_0_7(o_WfxrXtYt_1_0_7), + .o_W_times_X_Y_0_8(o_WfxrXtYt_1_0_8), + .o_W_times_X_Y_0_9(o_WfxrXtYt_1_0_9), + .o_W_times_X_Y_0_10(o_WfxrXtYt_1_0_10), + .o_W_times_X_Y_0_11(o_WfxrXtYt_1_0_11), + .o_W_times_X_Y_0_12(o_WfxrXtYt_1_0_12), + .o_W_times_X_Y_0_13(o_WfxrXtYt_1_0_13), + .o_W_times_X_Y_0_14(o_WfxrXtYt_1_0_14), + .o_W_times_X_Y_0_15(o_WfxrXtYt_1_0_15), + .o_valid(forget_gate_mult_valid), + .o_ready(forget_gate_mult_ready) +); + +// Output Gate Multiplication +matrix_times_two_vectors_18_10_1_672_16_1 output_gate_mult ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_ready(i_ready), + .i_valid(i_valid), + .i_Xt_Yt_1_0(i_Xt_Yt_1_0), + .i_Xt_Yt_1_1(i_Xt_Yt_1_1), + .i_Xt_Yt_1_2(i_Xt_Yt_1_2), + .i_Xt_Yt_1_3(i_Xt_Yt_1_3), + .i_Xt_Yt_1_4(i_Xt_Yt_1_4), + .i_Xt_Yt_1_5(i_Xt_Yt_1_5), + .i_Xt_Yt_1_6(i_Xt_Yt_1_6), + .i_Xt_Yt_1_7(i_Xt_Yt_1_7), + .i_Xt_Yt_1_8(i_Xt_Yt_1_8), + .i_Xt_Yt_1_9(i_Xt_Yt_1_9), + .i_Xt_Yt_1_10(i_Xt_Yt_1_10), + .i_Xt_Yt_1_11(i_Xt_Yt_1_11), + .i_Xt_Yt_1_12(i_Xt_Yt_1_12), + .i_Xt_Yt_1_13(i_Xt_Yt_1_13), + .i_Xt_Yt_1_14(i_Xt_Yt_1_14), + .i_Xt_Yt_1_15(i_Xt_Yt_1_15), + .i_Wxr_real_0_0(i_Woxr_real_0_0), + .i_Wxr_imag_0_0(i_Woxr_imag_0_0), + .i_Wxr_real_0_1(i_Woxr_real_0_1), + .i_Wxr_imag_0_1(i_Woxr_imag_0_1), + .i_Wxr_real_0_2(i_Woxr_real_0_2), + .i_Wxr_imag_0_2(i_Woxr_imag_0_2), + .i_Wxr_real_0_3(i_Woxr_real_0_3), + .i_Wxr_imag_0_3(i_Woxr_imag_0_3), + .i_Wxr_real_0_4(i_Woxr_real_0_4), + .i_Wxr_imag_0_4(i_Woxr_imag_0_4), + .i_Wxr_real_0_5(i_Woxr_real_0_5), + .i_Wxr_imag_0_5(i_Woxr_imag_0_5), + .i_Wxr_real_0_6(i_Woxr_real_0_6), + .i_Wxr_imag_0_6(i_Woxr_imag_0_6), + .i_Wxr_real_0_7(i_Woxr_real_0_7), + .i_Wxr_imag_0_7(i_Woxr_imag_0_7), + .i_Wxr_real_0_8(i_Woxr_real_0_8), + .i_Wxr_imag_0_8(i_Woxr_imag_0_8), + .o_W_times_X_Y_0_0(o_WoxrXtYt_1_0_0), + .o_W_times_X_Y_0_1(o_WoxrXtYt_1_0_1), + .o_W_times_X_Y_0_2(o_WoxrXtYt_1_0_2), + .o_W_times_X_Y_0_3(o_WoxrXtYt_1_0_3), + .o_W_times_X_Y_0_4(o_WoxrXtYt_1_0_4), + .o_W_times_X_Y_0_5(o_WoxrXtYt_1_0_5), + .o_W_times_X_Y_0_6(o_WoxrXtYt_1_0_6), + .o_W_times_X_Y_0_7(o_WoxrXtYt_1_0_7), + .o_W_times_X_Y_0_8(o_WoxrXtYt_1_0_8), + .o_W_times_X_Y_0_9(o_WoxrXtYt_1_0_9), + .o_W_times_X_Y_0_10(o_WoxrXtYt_1_0_10), + .o_W_times_X_Y_0_11(o_WoxrXtYt_1_0_11), + .o_W_times_X_Y_0_12(o_WoxrXtYt_1_0_12), + .o_W_times_X_Y_0_13(o_WoxrXtYt_1_0_13), + .o_W_times_X_Y_0_14(o_WoxrXtYt_1_0_14), + .o_W_times_X_Y_0_15(o_WoxrXtYt_1_0_15), + .o_valid(output_gate_mult_valid), + .o_ready(output_gate_mult_ready) +); + +// Output Activation Multiplication +matrix_times_two_vectors_18_10_1_672_16_1 output_act_gate_mult ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_ready(i_ready), + .i_valid(i_valid), + .i_Xt_Yt_1_0(i_Xt_Yt_1_0), + .i_Xt_Yt_1_1(i_Xt_Yt_1_1), + .i_Xt_Yt_1_2(i_Xt_Yt_1_2), + .i_Xt_Yt_1_3(i_Xt_Yt_1_3), + .i_Xt_Yt_1_4(i_Xt_Yt_1_4), + .i_Xt_Yt_1_5(i_Xt_Yt_1_5), + .i_Xt_Yt_1_6(i_Xt_Yt_1_6), + .i_Xt_Yt_1_7(i_Xt_Yt_1_7), + .i_Xt_Yt_1_8(i_Xt_Yt_1_8), + .i_Xt_Yt_1_9(i_Xt_Yt_1_9), + .i_Xt_Yt_1_10(i_Xt_Yt_1_10), + .i_Xt_Yt_1_11(i_Xt_Yt_1_11), + .i_Xt_Yt_1_12(i_Xt_Yt_1_12), + .i_Xt_Yt_1_13(i_Xt_Yt_1_13), + .i_Xt_Yt_1_14(i_Xt_Yt_1_14), + .i_Xt_Yt_1_15(i_Xt_Yt_1_15), + .i_Wxr_real_0_0(i_Wcxr_real_0_0), + .i_Wxr_imag_0_0(i_Wcxr_imag_0_0), + .i_Wxr_real_0_1(i_Wcxr_real_0_1), + .i_Wxr_imag_0_1(i_Wcxr_imag_0_1), + .i_Wxr_real_0_2(i_Wcxr_real_0_2), + .i_Wxr_imag_0_2(i_Wcxr_imag_0_2), + .i_Wxr_real_0_3(i_Wcxr_real_0_3), + .i_Wxr_imag_0_3(i_Wcxr_imag_0_3), + .i_Wxr_real_0_4(i_Wcxr_real_0_4), + .i_Wxr_imag_0_4(i_Wcxr_imag_0_4), + .i_Wxr_real_0_5(i_Wcxr_real_0_5), + .i_Wxr_imag_0_5(i_Wcxr_imag_0_5), + .i_Wxr_real_0_6(i_Wcxr_real_0_6), + .i_Wxr_imag_0_6(i_Wcxr_imag_0_6), + .i_Wxr_real_0_7(i_Wcxr_real_0_7), + .i_Wxr_imag_0_7(i_Wcxr_imag_0_7), + .i_Wxr_real_0_8(i_Wcxr_real_0_8), + .i_Wxr_imag_0_8(i_Wcxr_imag_0_8), + .o_W_times_X_Y_0_0(o_WcxrXtYt_1_0_0), + .o_W_times_X_Y_0_1(o_WcxrXtYt_1_0_1), + .o_W_times_X_Y_0_2(o_WcxrXtYt_1_0_2), + .o_W_times_X_Y_0_3(o_WcxrXtYt_1_0_3), + .o_W_times_X_Y_0_4(o_WcxrXtYt_1_0_4), + .o_W_times_X_Y_0_5(o_WcxrXtYt_1_0_5), + .o_W_times_X_Y_0_6(o_WcxrXtYt_1_0_6), + .o_W_times_X_Y_0_7(o_WcxrXtYt_1_0_7), + .o_W_times_X_Y_0_8(o_WcxrXtYt_1_0_8), + .o_W_times_X_Y_0_9(o_WcxrXtYt_1_0_9), + .o_W_times_X_Y_0_10(o_WcxrXtYt_1_0_10), + .o_W_times_X_Y_0_11(o_WcxrXtYt_1_0_11), + .o_W_times_X_Y_0_12(o_WcxrXtYt_1_0_12), + .o_W_times_X_Y_0_13(o_WcxrXtYt_1_0_13), + .o_W_times_X_Y_0_14(o_WcxrXtYt_1_0_14), + .o_W_times_X_Y_0_15(o_WcxrXtYt_1_0_15), + .o_valid(output_act_mult_valid), + .o_ready(output_act_mult_ready) +); + +assign o_valid = input_gate_mult_valid & forget_gate_mult_valid & output_gate_mult_valid & output_act_mult_valid; +assign o_ready = input_gate_mult_ready & forget_gate_mult_ready & output_gate_mult_ready & output_act_mult_ready; + +endmodule + +module matrix_times_two_vectors_18_10_1_672_16_1 ( + input clk, + input reset, + input enable, + input i_ready, + input i_valid, + input [17:0] i_Xt_Yt_1_0, + input [17:0] i_Xt_Yt_1_1, + input [17:0] i_Xt_Yt_1_2, + input [17:0] i_Xt_Yt_1_3, + input [17:0] i_Xt_Yt_1_4, + input [17:0] i_Xt_Yt_1_5, + input [17:0] i_Xt_Yt_1_6, + input [17:0] i_Xt_Yt_1_7, + input [17:0] i_Xt_Yt_1_8, + input [17:0] i_Xt_Yt_1_9, + input [17:0] i_Xt_Yt_1_10, + input [17:0] i_Xt_Yt_1_11, + input [17:0] i_Xt_Yt_1_12, + input [17:0] i_Xt_Yt_1_13, + input [17:0] i_Xt_Yt_1_14, + input [17:0] i_Xt_Yt_1_15, + input [17:0] i_Wxr_real_0_0, + input [17:0] i_Wxr_imag_0_0, + input [17:0] i_Wxr_real_0_1, + input [17:0] i_Wxr_imag_0_1, + input [17:0] i_Wxr_real_0_2, + input [17:0] i_Wxr_imag_0_2, + input [17:0] i_Wxr_real_0_3, + input [17:0] i_Wxr_imag_0_3, + input [17:0] i_Wxr_real_0_4, + input [17:0] i_Wxr_imag_0_4, + input [17:0] i_Wxr_real_0_5, + input [17:0] i_Wxr_imag_0_5, + input [17:0] i_Wxr_real_0_6, + input [17:0] i_Wxr_imag_0_6, + input [17:0] i_Wxr_real_0_7, + input [17:0] i_Wxr_imag_0_7, + input [17:0] i_Wxr_real_0_8, + input [17:0] i_Wxr_imag_0_8, + output [17:0] o_W_times_X_Y_0_0, + output [17:0] o_W_times_X_Y_0_1, + output [17:0] o_W_times_X_Y_0_2, + output [17:0] o_W_times_X_Y_0_3, + output [17:0] o_W_times_X_Y_0_4, + output [17:0] o_W_times_X_Y_0_5, + output [17:0] o_W_times_X_Y_0_6, + output [17:0] o_W_times_X_Y_0_7, + output [17:0] o_W_times_X_Y_0_8, + output [17:0] o_W_times_X_Y_0_9, + output [17:0] o_W_times_X_Y_0_10, + output [17:0] o_W_times_X_Y_0_11, + output [17:0] o_W_times_X_Y_0_12, + output [17:0] o_W_times_X_Y_0_13, + output [17:0] o_W_times_X_Y_0_14, + output [17:0] o_W_times_X_Y_0_15, + output o_valid, + output o_ready +); + +multiple_c_matrix_vec_mult_and_sum_18_10_16_1_1_42 multiple_c_matrix_vec_mult_and_sum_18_10_16_1_1_42_inst_kcupbbtthc ( + .clk(clk), + .reset(reset), + .i_ready(i_ready), + .i_valid(i_valid), + .i_X_0(i_Xt_Yt_1_0), + .i_X_1(i_Xt_Yt_1_1), + .i_X_2(i_Xt_Yt_1_2), + .i_X_3(i_Xt_Yt_1_3), + .i_X_4(i_Xt_Yt_1_4), + .i_X_5(i_Xt_Yt_1_5), + .i_X_6(i_Xt_Yt_1_6), + .i_X_7(i_Xt_Yt_1_7), + .i_X_8(i_Xt_Yt_1_8), + .i_X_9(i_Xt_Yt_1_9), + .i_X_10(i_Xt_Yt_1_10), + .i_X_11(i_Xt_Yt_1_11), + .i_X_12(i_Xt_Yt_1_12), + .i_X_13(i_Xt_Yt_1_13), + .i_X_14(i_Xt_Yt_1_14), + .i_X_15(i_Xt_Yt_1_15), + .i_W_real_0_0(i_Wxr_real_0_0), + .i_W_imag_0_0(i_Wxr_imag_0_0), + .i_W_real_0_1(i_Wxr_real_0_1), + .i_W_imag_0_1(i_Wxr_imag_0_1), + .i_W_real_0_2(i_Wxr_real_0_2), + .i_W_imag_0_2(i_Wxr_imag_0_2), + .i_W_real_0_3(i_Wxr_real_0_3), + .i_W_imag_0_3(i_Wxr_imag_0_3), + .i_W_real_0_4(i_Wxr_real_0_4), + .i_W_imag_0_4(i_Wxr_imag_0_4), + .i_W_real_0_5(i_Wxr_real_0_5), + .i_W_imag_0_5(i_Wxr_imag_0_5), + .i_W_real_0_6(i_Wxr_real_0_6), + .i_W_imag_0_6(i_Wxr_imag_0_6), + .i_W_real_0_7(i_Wxr_real_0_7), + .i_W_imag_0_7(i_Wxr_imag_0_7), + .i_W_real_0_8(i_Wxr_real_0_8), + .i_W_imag_0_8(i_Wxr_imag_0_8), + .o_Y_0_0(o_W_times_X_Y_0_0), + .o_Y_0_1(o_W_times_X_Y_0_1), + .o_Y_0_2(o_W_times_X_Y_0_2), + .o_Y_0_3(o_W_times_X_Y_0_3), + .o_Y_0_4(o_W_times_X_Y_0_4), + .o_Y_0_5(o_W_times_X_Y_0_5), + .o_Y_0_6(o_W_times_X_Y_0_6), + .o_Y_0_7(o_W_times_X_Y_0_7), + .o_Y_0_8(o_W_times_X_Y_0_8), + .o_Y_0_9(o_W_times_X_Y_0_9), + .o_Y_0_10(o_W_times_X_Y_0_10), + .o_Y_0_11(o_W_times_X_Y_0_11), + .o_Y_0_12(o_W_times_X_Y_0_12), + .o_Y_0_13(o_W_times_X_Y_0_13), + .o_Y_0_14(o_W_times_X_Y_0_14), + .o_Y_0_15(o_W_times_X_Y_0_15), + .o_valid(o_valid), + .o_ready(o_ready) +); + +endmodule + +module multiple_c_matrix_vec_mult_and_sum_18_10_16_1_1_42 ( + input clk, + input reset, + input i_ready, + input i_valid, + input [17:0] i_X_0, + input [17:0] i_X_1, + input [17:0] i_X_2, + input [17:0] i_X_3, + input [17:0] i_X_4, + input [17:0] i_X_5, + input [17:0] i_X_6, + input [17:0] i_X_7, + input [17:0] i_X_8, + input [17:0] i_X_9, + input [17:0] i_X_10, + input [17:0] i_X_11, + input [17:0] i_X_12, + input [17:0] i_X_13, + input [17:0] i_X_14, + input [17:0] i_X_15, + input [17:0] i_W_real_0_0, + input [17:0] i_W_imag_0_0, + input [17:0] i_W_real_0_1, + input [17:0] i_W_imag_0_1, + input [17:0] i_W_real_0_2, + input [17:0] i_W_imag_0_2, + input [17:0] i_W_real_0_3, + input [17:0] i_W_imag_0_3, + input [17:0] i_W_real_0_4, + input [17:0] i_W_imag_0_4, + input [17:0] i_W_real_0_5, + input [17:0] i_W_imag_0_5, + input [17:0] i_W_real_0_6, + input [17:0] i_W_imag_0_6, + input [17:0] i_W_real_0_7, + input [17:0] i_W_imag_0_7, + input [17:0] i_W_real_0_8, + input [17:0] i_W_imag_0_8, + output [17:0] o_Y_0_0, + output [17:0] o_Y_0_1, + output [17:0] o_Y_0_2, + output [17:0] o_Y_0_3, + output [17:0] o_Y_0_4, + output [17:0] o_Y_0_5, + output [17:0] o_Y_0_6, + output [17:0] o_Y_0_7, + output [17:0] o_Y_0_8, + output [17:0] o_Y_0_9, + output [17:0] o_Y_0_10, + output [17:0] o_Y_0_11, + output [17:0] o_Y_0_12, + output [17:0] o_Y_0_13, + output [17:0] o_Y_0_14, + output [17:0] o_Y_0_15, + output o_valid, + output o_ready +); + +wire matrix_vec_mult_ready, matrix_vec_mult_valid; +wire accum_valid_0; +wire idft_next_out_0; +reg idft_out_valid; +wire [17:0] Y_imag_0_0; +wire [17:0] Y_real_0_0; +wire [17:0] sum_Y_real_0_0; +wire [17:0] sum_Y_imag_0_0; +wire [17:0] sum_Y_real_hold_0_0; +wire [17:0] sum_Y_imag_hold_0_0; +wire [17:0] out_Y_idft_0_0; +reg [17:0] reg_Y_0_0; +wire [17:0] Y_imag_0_1; +wire [17:0] Y_real_0_1; +wire [17:0] sum_Y_real_0_1; +wire [17:0] sum_Y_imag_0_1; +wire [17:0] sum_Y_real_hold_0_1; +wire [17:0] sum_Y_imag_hold_0_1; +wire [17:0] out_Y_idft_0_1; +reg [17:0] reg_Y_0_1; +wire [17:0] Y_imag_0_2; +wire [17:0] Y_real_0_2; +wire [17:0] sum_Y_real_0_2; +wire [17:0] sum_Y_imag_0_2; +wire [17:0] sum_Y_real_hold_0_2; +wire [17:0] sum_Y_imag_hold_0_2; +wire [17:0] out_Y_idft_0_2; +reg [17:0] reg_Y_0_2; +wire [17:0] Y_imag_0_3; +wire [17:0] Y_real_0_3; +wire [17:0] sum_Y_real_0_3; +wire [17:0] sum_Y_imag_0_3; +wire [17:0] sum_Y_real_hold_0_3; +wire [17:0] sum_Y_imag_hold_0_3; +wire [17:0] out_Y_idft_0_3; +reg [17:0] reg_Y_0_3; +wire [17:0] Y_imag_0_4; +wire [17:0] Y_real_0_4; +wire [17:0] sum_Y_real_0_4; +wire [17:0] sum_Y_imag_0_4; +wire [17:0] sum_Y_real_hold_0_4; +wire [17:0] sum_Y_imag_hold_0_4; +wire [17:0] out_Y_idft_0_4; +reg [17:0] reg_Y_0_4; +wire [17:0] Y_imag_0_5; +wire [17:0] Y_real_0_5; +wire [17:0] sum_Y_real_0_5; +wire [17:0] sum_Y_imag_0_5; +wire [17:0] sum_Y_real_hold_0_5; +wire [17:0] sum_Y_imag_hold_0_5; +wire [17:0] out_Y_idft_0_5; +reg [17:0] reg_Y_0_5; +wire [17:0] Y_imag_0_6; +wire [17:0] Y_real_0_6; +wire [17:0] sum_Y_real_0_6; +wire [17:0] sum_Y_imag_0_6; +wire [17:0] sum_Y_real_hold_0_6; +wire [17:0] sum_Y_imag_hold_0_6; +wire [17:0] out_Y_idft_0_6; +reg [17:0] reg_Y_0_6; +wire [17:0] Y_imag_0_7; +wire [17:0] Y_real_0_7; +wire [17:0] sum_Y_real_0_7; +wire [17:0] sum_Y_imag_0_7; +wire [17:0] sum_Y_real_hold_0_7; +wire [17:0] sum_Y_imag_hold_0_7; +wire [17:0] out_Y_idft_0_7; +reg [17:0] reg_Y_0_7; +wire [17:0] Y_imag_0_8; +wire [17:0] Y_real_0_8; +wire [17:0] sum_Y_real_0_8; +wire [17:0] sum_Y_imag_0_8; +wire [17:0] sum_Y_real_hold_0_8; +wire [17:0] sum_Y_imag_hold_0_8; +wire [17:0] out_Y_idft_0_8; +reg [17:0] reg_Y_0_8; +wire [17:0] Y_imag_0_9; +wire [17:0] Y_real_0_9; +wire [17:0] sum_Y_real_0_9; +wire [17:0] sum_Y_imag_0_9; +wire [17:0] sum_Y_real_hold_0_9; +wire [17:0] sum_Y_imag_hold_0_9; +wire [17:0] out_Y_idft_0_9; +reg [17:0] reg_Y_0_9; +wire [17:0] Y_imag_0_10; +wire [17:0] Y_real_0_10; +wire [17:0] sum_Y_real_0_10; +wire [17:0] sum_Y_imag_0_10; +wire [17:0] sum_Y_real_hold_0_10; +wire [17:0] sum_Y_imag_hold_0_10; +wire [17:0] out_Y_idft_0_10; +reg [17:0] reg_Y_0_10; +wire [17:0] Y_imag_0_11; +wire [17:0] Y_real_0_11; +wire [17:0] sum_Y_real_0_11; +wire [17:0] sum_Y_imag_0_11; +wire [17:0] sum_Y_real_hold_0_11; +wire [17:0] sum_Y_imag_hold_0_11; +wire [17:0] out_Y_idft_0_11; +reg [17:0] reg_Y_0_11; +wire [17:0] Y_imag_0_12; +wire [17:0] Y_real_0_12; +wire [17:0] sum_Y_real_0_12; +wire [17:0] sum_Y_imag_0_12; +wire [17:0] sum_Y_real_hold_0_12; +wire [17:0] sum_Y_imag_hold_0_12; +wire [17:0] out_Y_idft_0_12; +reg [17:0] reg_Y_0_12; +wire [17:0] Y_imag_0_13; +wire [17:0] Y_real_0_13; +wire [17:0] sum_Y_real_0_13; +wire [17:0] sum_Y_imag_0_13; +wire [17:0] sum_Y_real_hold_0_13; +wire [17:0] sum_Y_imag_hold_0_13; +wire [17:0] out_Y_idft_0_13; +reg [17:0] reg_Y_0_13; +wire [17:0] Y_imag_0_14; +wire [17:0] Y_real_0_14; +wire [17:0] sum_Y_real_0_14; +wire [17:0] sum_Y_imag_0_14; +wire [17:0] sum_Y_real_hold_0_14; +wire [17:0] sum_Y_imag_hold_0_14; +wire [17:0] out_Y_idft_0_14; +reg [17:0] reg_Y_0_14; +wire [17:0] Y_imag_0_15; +wire [17:0] Y_real_0_15; +wire [17:0] sum_Y_real_0_15; +wire [17:0] sum_Y_imag_0_15; +wire [17:0] sum_Y_real_hold_0_15; +wire [17:0] sum_Y_imag_hold_0_15; +wire [17:0] out_Y_idft_0_15; +reg [17:0] reg_Y_0_15; +reg reg_o_valid; + +// Enable whenever the reciever is ready +wire enable; +assign enable = i_ready; +c_matrix_vec_mult_core_18_10_16_1_1 c_matrix_vec_mult_core_18_10_16_1_1_inst_wwwukppgxr ( + .clk(clk), + .reset(reset), + .i_ready(i_ready), + .i_valid(i_valid), + .i_X_0(i_X_0), + .i_X_1(i_X_1), + .i_X_2(i_X_2), + .i_X_3(i_X_3), + .i_X_4(i_X_4), + .i_X_5(i_X_5), + .i_X_6(i_X_6), + .i_X_7(i_X_7), + .i_X_8(i_X_8), + .i_X_9(i_X_9), + .i_X_10(i_X_10), + .i_X_11(i_X_11), + .i_X_12(i_X_12), + .i_X_13(i_X_13), + .i_X_14(i_X_14), + .i_X_15(i_X_15), + .i_W_real_0_0(i_W_real_0_0), + .i_W_imag_0_0(i_W_imag_0_0), + .i_W_real_0_1(i_W_real_0_1), + .i_W_imag_0_1(i_W_imag_0_1), + .i_W_real_0_2(i_W_real_0_2), + .i_W_imag_0_2(i_W_imag_0_2), + .i_W_real_0_3(i_W_real_0_3), + .i_W_imag_0_3(i_W_imag_0_3), + .i_W_real_0_4(i_W_real_0_4), + .i_W_imag_0_4(i_W_imag_0_4), + .i_W_real_0_5(i_W_real_0_5), + .i_W_imag_0_5(i_W_imag_0_5), + .i_W_real_0_6(i_W_real_0_6), + .i_W_imag_0_6(i_W_imag_0_6), + .i_W_real_0_7(i_W_real_0_7), + .i_W_imag_0_7(i_W_imag_0_7), + .i_W_real_0_8(i_W_real_0_8), + .i_W_imag_0_8(i_W_imag_0_8), + .o_Y_real_0_0(Y_real_0_0), + .o_Y_imag_0_0(Y_imag_0_0), + .o_Y_real_0_1(Y_real_0_1), + .o_Y_imag_0_1(Y_imag_0_1), + .o_Y_real_0_2(Y_real_0_2), + .o_Y_imag_0_2(Y_imag_0_2), + .o_Y_real_0_3(Y_real_0_3), + .o_Y_imag_0_3(Y_imag_0_3), + .o_Y_real_0_4(Y_real_0_4), + .o_Y_imag_0_4(Y_imag_0_4), + .o_Y_real_0_5(Y_real_0_5), + .o_Y_imag_0_5(Y_imag_0_5), + .o_Y_real_0_6(Y_real_0_6), + .o_Y_imag_0_6(Y_imag_0_6), + .o_Y_real_0_7(Y_real_0_7), + .o_Y_imag_0_7(Y_imag_0_7), + .o_Y_real_0_8(Y_real_0_8), + .o_Y_imag_0_8(Y_imag_0_8), + .o_Y_real_0_9(Y_real_0_9), + .o_Y_imag_0_9(Y_imag_0_9), + .o_Y_real_0_10(Y_real_0_10), + .o_Y_imag_0_10(Y_imag_0_10), + .o_Y_real_0_11(Y_real_0_11), + .o_Y_imag_0_11(Y_imag_0_11), + .o_Y_real_0_12(Y_real_0_12), + .o_Y_imag_0_12(Y_imag_0_12), + .o_Y_real_0_13(Y_real_0_13), + .o_Y_imag_0_13(Y_imag_0_13), + .o_Y_real_0_14(Y_real_0_14), + .o_Y_imag_0_14(Y_imag_0_14), + .o_Y_real_0_15(Y_real_0_15), + .o_Y_imag_0_15(Y_imag_0_15), + .o_ready(matrix_vec_mult_ready), + .o_valid(matrix_vec_mult_valid) +); + +sum_complex_vector_unit_18_18_16_42 sum_complex_vector_unit_18_18_16_42_inst_uhhpplnemw ( + .clk(clk), + .clr(reset), + .enable(enable), + .i_valid(matrix_vec_mult_valid), + .i_real_0(Y_real_0_0), + .i_imag_0(Y_imag_0_0), + .o_real_0(sum_Y_real_0_0), + .o_imag_0(sum_Y_imag_0_0), + .i_real_1(Y_real_0_1), + .i_imag_1(Y_imag_0_1), + .o_real_1(sum_Y_real_0_1), + .o_imag_1(sum_Y_imag_0_1), + .i_real_2(Y_real_0_2), + .i_imag_2(Y_imag_0_2), + .o_real_2(sum_Y_real_0_2), + .o_imag_2(sum_Y_imag_0_2), + .i_real_3(Y_real_0_3), + .i_imag_3(Y_imag_0_3), + .o_real_3(sum_Y_real_0_3), + .o_imag_3(sum_Y_imag_0_3), + .i_real_4(Y_real_0_4), + .i_imag_4(Y_imag_0_4), + .o_real_4(sum_Y_real_0_4), + .o_imag_4(sum_Y_imag_0_4), + .i_real_5(Y_real_0_5), + .i_imag_5(Y_imag_0_5), + .o_real_5(sum_Y_real_0_5), + .o_imag_5(sum_Y_imag_0_5), + .i_real_6(Y_real_0_6), + .i_imag_6(Y_imag_0_6), + .o_real_6(sum_Y_real_0_6), + .o_imag_6(sum_Y_imag_0_6), + .i_real_7(Y_real_0_7), + .i_imag_7(Y_imag_0_7), + .o_real_7(sum_Y_real_0_7), + .o_imag_7(sum_Y_imag_0_7), + .i_real_8(Y_real_0_8), + .i_imag_8(Y_imag_0_8), + .o_real_8(sum_Y_real_0_8), + .o_imag_8(sum_Y_imag_0_8), + .i_real_9(Y_real_0_9), + .i_imag_9(Y_imag_0_9), + .o_real_9(sum_Y_real_0_9), + .o_imag_9(sum_Y_imag_0_9), + .i_real_10(Y_real_0_10), + .i_imag_10(Y_imag_0_10), + .o_real_10(sum_Y_real_0_10), + .o_imag_10(sum_Y_imag_0_10), + .i_real_11(Y_real_0_11), + .i_imag_11(Y_imag_0_11), + .o_real_11(sum_Y_real_0_11), + .o_imag_11(sum_Y_imag_0_11), + .i_real_12(Y_real_0_12), + .i_imag_12(Y_imag_0_12), + .o_real_12(sum_Y_real_0_12), + .o_imag_12(sum_Y_imag_0_12), + .i_real_13(Y_real_0_13), + .i_imag_13(Y_imag_0_13), + .o_real_13(sum_Y_real_0_13), + .o_imag_13(sum_Y_imag_0_13), + .i_real_14(Y_real_0_14), + .i_imag_14(Y_imag_0_14), + .o_real_14(sum_Y_real_0_14), + .o_imag_14(sum_Y_imag_0_14), + .i_real_15(Y_real_0_15), + .i_imag_15(Y_imag_0_15), + .o_real_15(sum_Y_real_0_15), + .o_imag_15(sum_Y_imag_0_15), + .o_valid(accum_valid_0) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_zajomeqidi_real ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_real_0_0), + .out_0(sum_Y_real_hold_0_0), + .in_1(sum_Y_real_0_1), + .out_1(sum_Y_real_hold_0_1), + .in_2(sum_Y_real_0_2), + .out_2(sum_Y_real_hold_0_2), + .in_3(sum_Y_real_0_3), + .out_3(sum_Y_real_hold_0_3), + .in_4(sum_Y_real_0_4), + .out_4(sum_Y_real_hold_0_4), + .in_5(sum_Y_real_0_5), + .out_5(sum_Y_real_hold_0_5), + .in_6(sum_Y_real_0_6), + .out_6(sum_Y_real_hold_0_6), + .in_7(sum_Y_real_0_7), + .out_7(sum_Y_real_hold_0_7), + .in_8(sum_Y_real_0_8), + .out_8(sum_Y_real_hold_0_8), + .in_9(sum_Y_real_0_9), + .out_9(sum_Y_real_hold_0_9), + .in_10(sum_Y_real_0_10), + .out_10(sum_Y_real_hold_0_10), + .in_11(sum_Y_real_0_11), + .out_11(sum_Y_real_hold_0_11), + .in_12(sum_Y_real_0_12), + .out_12(sum_Y_real_hold_0_12), + .in_13(sum_Y_real_0_13), + .out_13(sum_Y_real_hold_0_13), + .in_14(sum_Y_real_0_14), + .out_14(sum_Y_real_hold_0_14), + .in_15(sum_Y_real_0_15), + .out_15(sum_Y_real_hold_0_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_nnsglohnyc_imag ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_imag_0_0), + .out_0(sum_Y_imag_hold_0_0), + .in_1(sum_Y_imag_0_1), + .out_1(sum_Y_imag_hold_0_1), + .in_2(sum_Y_imag_0_2), + .out_2(sum_Y_imag_hold_0_2), + .in_3(sum_Y_imag_0_3), + .out_3(sum_Y_imag_hold_0_3), + .in_4(sum_Y_imag_0_4), + .out_4(sum_Y_imag_hold_0_4), + .in_5(sum_Y_imag_0_5), + .out_5(sum_Y_imag_hold_0_5), + .in_6(sum_Y_imag_0_6), + .out_6(sum_Y_imag_hold_0_6), + .in_7(sum_Y_imag_0_7), + .out_7(sum_Y_imag_hold_0_7), + .in_8(sum_Y_imag_0_8), + .out_8(sum_Y_imag_hold_0_8), + .in_9(sum_Y_imag_0_9), + .out_9(sum_Y_imag_hold_0_9), + .in_10(sum_Y_imag_0_10), + .out_10(sum_Y_imag_hold_0_10), + .in_11(sum_Y_imag_0_11), + .out_11(sum_Y_imag_hold_0_11), + .in_12(sum_Y_imag_0_12), + .out_12(sum_Y_imag_hold_0_12), + .in_13(sum_Y_imag_0_13), + .out_13(sum_Y_imag_hold_0_13), + .in_14(sum_Y_imag_0_14), + .out_14(sum_Y_imag_hold_0_14), + .in_15(sum_Y_imag_0_15), + .out_15(sum_Y_imag_hold_0_15), + .reset(reset) +); + +idft_16_top_18 idft_16_top_18_inst_jdwvwswnmw ( + .clk(clk), + .reset(reset), + .next(accum_valid_0), + .X0(sum_Y_real_hold_0_0), + .Y0(out_Y_idft_0_0), + .X1(sum_Y_imag_hold_0_0), + .Y1(), + .X2(sum_Y_real_hold_0_1), + .Y2(out_Y_idft_0_1), + .X3(sum_Y_imag_hold_0_1), + .Y3(), + .X4(sum_Y_real_hold_0_2), + .Y4(out_Y_idft_0_2), + .X5(sum_Y_imag_hold_0_2), + .Y5(), + .X6(sum_Y_real_hold_0_3), + .Y6(out_Y_idft_0_3), + .X7(sum_Y_imag_hold_0_3), + .Y7(), + .X8(sum_Y_real_hold_0_4), + .Y8(out_Y_idft_0_4), + .X9(sum_Y_imag_hold_0_4), + .Y9(), + .X10(sum_Y_real_hold_0_5), + .Y10(out_Y_idft_0_5), + .X11(sum_Y_imag_hold_0_5), + .Y11(), + .X12(sum_Y_real_hold_0_6), + .Y12(out_Y_idft_0_6), + .X13(sum_Y_imag_hold_0_6), + .Y13(), + .X14(sum_Y_real_hold_0_7), + .Y14(out_Y_idft_0_7), + .X15(sum_Y_imag_hold_0_7), + .Y15(), + .X16(sum_Y_real_hold_0_8), + .Y16(out_Y_idft_0_8), + .X17(sum_Y_imag_hold_0_8), + .Y17(), + .X18(sum_Y_real_hold_0_9), + .Y18(out_Y_idft_0_9), + .X19(sum_Y_imag_hold_0_9), + .Y19(), + .X20(sum_Y_real_hold_0_10), + .Y20(out_Y_idft_0_10), + .X21(sum_Y_imag_hold_0_10), + .Y21(), + .X22(sum_Y_real_hold_0_11), + .Y22(out_Y_idft_0_11), + .X23(sum_Y_imag_hold_0_11), + .Y23(), + .X24(sum_Y_real_hold_0_12), + .Y24(out_Y_idft_0_12), + .X25(sum_Y_imag_hold_0_12), + .Y25(), + .X26(sum_Y_real_hold_0_13), + .Y26(out_Y_idft_0_13), + .X27(sum_Y_imag_hold_0_13), + .Y27(), + .X28(sum_Y_real_hold_0_14), + .Y28(out_Y_idft_0_14), + .X29(sum_Y_imag_hold_0_14), + .Y29(), + .X30(sum_Y_real_hold_0_15), + .Y30(out_Y_idft_0_15), + .X31(sum_Y_imag_hold_0_15), + .Y31(), + .next_out(idft_next_out_0) +); + +always @ (posedge clk) begin + if (reset) begin + reg_Y_0_0 <= 0; + reg_Y_0_1 <= 0; + reg_Y_0_2 <= 0; + reg_Y_0_3 <= 0; + reg_Y_0_4 <= 0; + reg_Y_0_5 <= 0; + reg_Y_0_6 <= 0; + reg_Y_0_7 <= 0; + reg_Y_0_8 <= 0; + reg_Y_0_9 <= 0; + reg_Y_0_10 <= 0; + reg_Y_0_11 <= 0; + reg_Y_0_12 <= 0; + reg_Y_0_13 <= 0; + reg_Y_0_14 <= 0; + reg_Y_0_15 <= 0; + idft_out_valid <= 1'b0; + reg_o_valid <= 1'b0; + end else if (enable) begin + reg_Y_0_0 <= (out_Y_idft_0_0 >>> 4); + reg_Y_0_1 <= (out_Y_idft_0_1 >>> 4); + reg_Y_0_2 <= (out_Y_idft_0_2 >>> 4); + reg_Y_0_3 <= (out_Y_idft_0_3 >>> 4); + reg_Y_0_4 <= (out_Y_idft_0_4 >>> 4); + reg_Y_0_5 <= (out_Y_idft_0_5 >>> 4); + reg_Y_0_6 <= (out_Y_idft_0_6 >>> 4); + reg_Y_0_7 <= (out_Y_idft_0_7 >>> 4); + reg_Y_0_8 <= (out_Y_idft_0_8 >>> 4); + reg_Y_0_9 <= (out_Y_idft_0_9 >>> 4); + reg_Y_0_10 <= (out_Y_idft_0_10 >>> 4); + reg_Y_0_11 <= (out_Y_idft_0_11 >>> 4); + reg_Y_0_12 <= (out_Y_idft_0_12 >>> 4); + reg_Y_0_13 <= (out_Y_idft_0_13 >>> 4); + reg_Y_0_14 <= (out_Y_idft_0_14 >>> 4); + reg_Y_0_15 <= (out_Y_idft_0_15 >>> 4); + idft_out_valid <= idft_next_out_0; + reg_o_valid <= idft_out_valid; + end +end + +assign o_valid = enable & reg_o_valid; +assign o_ready = matrix_vec_mult_ready; +assign o_Y_0_0 = reg_Y_0_0; +assign o_Y_0_1 = reg_Y_0_1; +assign o_Y_0_2 = reg_Y_0_2; +assign o_Y_0_3 = reg_Y_0_3; +assign o_Y_0_4 = reg_Y_0_4; +assign o_Y_0_5 = reg_Y_0_5; +assign o_Y_0_6 = reg_Y_0_6; +assign o_Y_0_7 = reg_Y_0_7; +assign o_Y_0_8 = reg_Y_0_8; +assign o_Y_0_9 = reg_Y_0_9; +assign o_Y_0_10 = reg_Y_0_10; +assign o_Y_0_11 = reg_Y_0_11; +assign o_Y_0_12 = reg_Y_0_12; +assign o_Y_0_13 = reg_Y_0_13; +assign o_Y_0_14 = reg_Y_0_14; +assign o_Y_0_15 = reg_Y_0_15; + +endmodule + +module c_matrix_vec_mult_core_18_10_16_1_1 ( + input clk, + input reset, + input i_ready, + input i_valid, + input [17:0] i_X_0, + input [17:0] i_X_1, + input [17:0] i_X_2, + input [17:0] i_X_3, + input [17:0] i_X_4, + input [17:0] i_X_5, + input [17:0] i_X_6, + input [17:0] i_X_7, + input [17:0] i_X_8, + input [17:0] i_X_9, + input [17:0] i_X_10, + input [17:0] i_X_11, + input [17:0] i_X_12, + input [17:0] i_X_13, + input [17:0] i_X_14, + input [17:0] i_X_15, + input [17:0] i_W_real_0_0, + input [17:0] i_W_imag_0_0, + input [17:0] i_W_real_0_1, + input [17:0] i_W_imag_0_1, + input [17:0] i_W_real_0_2, + input [17:0] i_W_imag_0_2, + input [17:0] i_W_real_0_3, + input [17:0] i_W_imag_0_3, + input [17:0] i_W_real_0_4, + input [17:0] i_W_imag_0_4, + input [17:0] i_W_real_0_5, + input [17:0] i_W_imag_0_5, + input [17:0] i_W_real_0_6, + input [17:0] i_W_imag_0_6, + input [17:0] i_W_real_0_7, + input [17:0] i_W_imag_0_7, + input [17:0] i_W_real_0_8, + input [17:0] i_W_imag_0_8, + output [17:0] o_Y_real_0_0, + output [17:0] o_Y_imag_0_0, + output [17:0] o_Y_real_0_1, + output [17:0] o_Y_imag_0_1, + output [17:0] o_Y_real_0_2, + output [17:0] o_Y_imag_0_2, + output [17:0] o_Y_real_0_3, + output [17:0] o_Y_imag_0_3, + output [17:0] o_Y_real_0_4, + output [17:0] o_Y_imag_0_4, + output [17:0] o_Y_real_0_5, + output [17:0] o_Y_imag_0_5, + output [17:0] o_Y_real_0_6, + output [17:0] o_Y_imag_0_6, + output [17:0] o_Y_real_0_7, + output [17:0] o_Y_imag_0_7, + output [17:0] o_Y_real_0_8, + output [17:0] o_Y_imag_0_8, + output [17:0] o_Y_real_0_9, + output [17:0] o_Y_imag_0_9, + output [17:0] o_Y_real_0_10, + output [17:0] o_Y_imag_0_10, + output [17:0] o_Y_real_0_11, + output [17:0] o_Y_imag_0_11, + output [17:0] o_Y_real_0_12, + output [17:0] o_Y_imag_0_12, + output [17:0] o_Y_real_0_13, + output [17:0] o_Y_imag_0_13, + output [17:0] o_Y_real_0_14, + output [17:0] o_Y_imag_0_14, + output [17:0] o_Y_real_0_15, + output [17:0] o_Y_imag_0_15, + output o_ready, + output o_valid +); + +// Enable whenever reciever is ready +wire enable; +assign enable = i_ready; +// Register the inputs +reg [17:0] reg_X_0; +reg [17:0] reg_X_2_0; +reg [17:0] reg_X_1; +reg [17:0] reg_X_2_1; +reg [17:0] reg_X_2; +reg [17:0] reg_X_2_2; +reg [17:0] reg_X_3; +reg [17:0] reg_X_2_3; +reg [17:0] reg_X_4; +reg [17:0] reg_X_2_4; +reg [17:0] reg_X_5; +reg [17:0] reg_X_2_5; +reg [17:0] reg_X_6; +reg [17:0] reg_X_2_6; +reg [17:0] reg_X_7; +reg [17:0] reg_X_2_7; +reg [17:0] reg_X_8; +reg [17:0] reg_X_2_8; +reg [17:0] reg_X_9; +reg [17:0] reg_X_2_9; +reg [17:0] reg_X_10; +reg [17:0] reg_X_2_10; +reg [17:0] reg_X_11; +reg [17:0] reg_X_2_11; +reg [17:0] reg_X_12; +reg [17:0] reg_X_2_12; +reg [17:0] reg_X_13; +reg [17:0] reg_X_2_13; +reg [17:0] reg_X_14; +reg [17:0] reg_X_2_14; +reg [17:0] reg_X_15; +reg [17:0] reg_X_2_15; +reg [17:0] reg_W_real_0_0; +reg [17:0] reg_W_imag_0_0; +reg [17:0] reg_W_real_0_1; +reg [17:0] reg_W_imag_0_1; +reg [17:0] reg_W_real_0_2; +reg [17:0] reg_W_imag_0_2; +reg [17:0] reg_W_real_0_3; +reg [17:0] reg_W_imag_0_3; +reg [17:0] reg_W_real_0_4; +reg [17:0] reg_W_imag_0_4; +reg [17:0] reg_W_real_0_5; +reg [17:0] reg_W_imag_0_5; +reg [17:0] reg_W_real_0_6; +reg [17:0] reg_W_imag_0_6; +reg [17:0] reg_W_real_0_7; +reg [17:0] reg_W_imag_0_7; +reg [17:0] reg_W_real_0_8; +reg [17:0] reg_W_imag_0_8; +reg reg_i_valid; + +// Register the outputs +reg [17:0] reg_Y_real_0_0; +reg [17:0] reg_Y_imag_0_0; +reg [17:0] reg_Y_real_0_1; +reg [17:0] reg_Y_imag_0_1; +reg [17:0] reg_Y_real_0_2; +reg [17:0] reg_Y_imag_0_2; +reg [17:0] reg_Y_real_0_3; +reg [17:0] reg_Y_imag_0_3; +reg [17:0] reg_Y_real_0_4; +reg [17:0] reg_Y_imag_0_4; +reg [17:0] reg_Y_real_0_5; +reg [17:0] reg_Y_imag_0_5; +reg [17:0] reg_Y_real_0_6; +reg [17:0] reg_Y_imag_0_6; +reg [17:0] reg_Y_real_0_7; +reg [17:0] reg_Y_imag_0_7; +reg [17:0] reg_Y_real_0_8; +reg [17:0] reg_Y_imag_0_8; +reg [17:0] reg_Y_real_0_9; +reg [17:0] reg_Y_imag_0_9; +reg [17:0] reg_Y_real_0_10; +reg [17:0] reg_Y_imag_0_10; +reg [17:0] reg_Y_real_0_11; +reg [17:0] reg_Y_imag_0_11; +reg [17:0] reg_Y_real_0_12; +reg [17:0] reg_Y_imag_0_12; +reg [17:0] reg_Y_real_0_13; +reg [17:0] reg_Y_imag_0_13; +reg [17:0] reg_Y_real_0_14; +reg [17:0] reg_Y_imag_0_14; +reg [17:0] reg_Y_real_0_15; +reg [17:0] reg_Y_imag_0_15; +reg reg_o_valid; + +// Inter-connections +reg fft_valid; +reg reg_o_ready; +wire o_fft_next; +wire mult_X_real_W_real_valid_0; +wire mult_X_imag_W_real_valid_0; +wire mult_X_real_W_imag_valid_0; +wire mult_X_imag_W_imag_valid_0; +wire sub_y_real_valid_0; +wire add_y_imag_valid_0; + +wire [17:0] W_real_wires_0_0; +wire [17:0] W_imag_wires_0_0; +wire [17:0] W_real_holder_0_0; +wire [17:0] W_imag_holder_0_0; +wire [17:0] o_mult_X_real_W_real_0_0; +wire [17:0] o_mult_X_imag_W_real_0_0; +wire [17:0] o_mult_X_real_W_imag_0_0; +wire [17:0] o_mult_X_imag_W_imag_0_0; +wire [17:0] o_sub_y_real_0_0; +wire [17:0] o_add_y_imag_0_0; +wire [17:0] W_real_wires_0_1; +wire [17:0] W_imag_wires_0_1; +wire [17:0] W_real_holder_0_1; +wire [17:0] W_imag_holder_0_1; +wire [17:0] o_mult_X_real_W_real_0_1; +wire [17:0] o_mult_X_imag_W_real_0_1; +wire [17:0] o_mult_X_real_W_imag_0_1; +wire [17:0] o_mult_X_imag_W_imag_0_1; +wire [17:0] o_sub_y_real_0_1; +wire [17:0] o_add_y_imag_0_1; +wire [17:0] W_real_wires_0_2; +wire [17:0] W_imag_wires_0_2; +wire [17:0] W_real_holder_0_2; +wire [17:0] W_imag_holder_0_2; +wire [17:0] o_mult_X_real_W_real_0_2; +wire [17:0] o_mult_X_imag_W_real_0_2; +wire [17:0] o_mult_X_real_W_imag_0_2; +wire [17:0] o_mult_X_imag_W_imag_0_2; +wire [17:0] o_sub_y_real_0_2; +wire [17:0] o_add_y_imag_0_2; +wire [17:0] W_real_wires_0_3; +wire [17:0] W_imag_wires_0_3; +wire [17:0] W_real_holder_0_3; +wire [17:0] W_imag_holder_0_3; +wire [17:0] o_mult_X_real_W_real_0_3; +wire [17:0] o_mult_X_imag_W_real_0_3; +wire [17:0] o_mult_X_real_W_imag_0_3; +wire [17:0] o_mult_X_imag_W_imag_0_3; +wire [17:0] o_sub_y_real_0_3; +wire [17:0] o_add_y_imag_0_3; +wire [17:0] W_real_wires_0_4; +wire [17:0] W_imag_wires_0_4; +wire [17:0] W_real_holder_0_4; +wire [17:0] W_imag_holder_0_4; +wire [17:0] o_mult_X_real_W_real_0_4; +wire [17:0] o_mult_X_imag_W_real_0_4; +wire [17:0] o_mult_X_real_W_imag_0_4; +wire [17:0] o_mult_X_imag_W_imag_0_4; +wire [17:0] o_sub_y_real_0_4; +wire [17:0] o_add_y_imag_0_4; +wire [17:0] W_real_wires_0_5; +wire [17:0] W_imag_wires_0_5; +wire [17:0] W_real_holder_0_5; +wire [17:0] W_imag_holder_0_5; +wire [17:0] o_mult_X_real_W_real_0_5; +wire [17:0] o_mult_X_imag_W_real_0_5; +wire [17:0] o_mult_X_real_W_imag_0_5; +wire [17:0] o_mult_X_imag_W_imag_0_5; +wire [17:0] o_sub_y_real_0_5; +wire [17:0] o_add_y_imag_0_5; +wire [17:0] W_real_wires_0_6; +wire [17:0] W_imag_wires_0_6; +wire [17:0] W_real_holder_0_6; +wire [17:0] W_imag_holder_0_6; +wire [17:0] o_mult_X_real_W_real_0_6; +wire [17:0] o_mult_X_imag_W_real_0_6; +wire [17:0] o_mult_X_real_W_imag_0_6; +wire [17:0] o_mult_X_imag_W_imag_0_6; +wire [17:0] o_sub_y_real_0_6; +wire [17:0] o_add_y_imag_0_6; +wire [17:0] W_real_wires_0_7; +wire [17:0] W_imag_wires_0_7; +wire [17:0] W_real_holder_0_7; +wire [17:0] W_imag_holder_0_7; +wire [17:0] o_mult_X_real_W_real_0_7; +wire [17:0] o_mult_X_imag_W_real_0_7; +wire [17:0] o_mult_X_real_W_imag_0_7; +wire [17:0] o_mult_X_imag_W_imag_0_7; +wire [17:0] o_sub_y_real_0_7; +wire [17:0] o_add_y_imag_0_7; +wire [17:0] W_real_wires_0_8; +wire [17:0] W_imag_wires_0_8; +wire [17:0] W_real_holder_0_8; +wire [17:0] W_imag_holder_0_8; +wire [17:0] o_mult_X_real_W_real_0_8; +wire [17:0] o_mult_X_imag_W_real_0_8; +wire [17:0] o_mult_X_real_W_imag_0_8; +wire [17:0] o_mult_X_imag_W_imag_0_8; +wire [17:0] o_sub_y_real_0_8; +wire [17:0] o_add_y_imag_0_8; +wire [17:0] o_fft_X_real_0; +wire [17:0] o_fft_X_imag_0; +wire [17:0] o_fft_X_real_1; +wire [17:0] o_fft_X_imag_1; +wire [17:0] o_fft_X_real_2; +wire [17:0] o_fft_X_imag_2; +wire [17:0] o_fft_X_real_3; +wire [17:0] o_fft_X_imag_3; +wire [17:0] o_fft_X_real_4; +wire [17:0] o_fft_X_imag_4; +wire [17:0] o_fft_X_real_5; +wire [17:0] o_fft_X_imag_5; +wire [17:0] o_fft_X_real_6; +wire [17:0] o_fft_X_imag_6; +wire [17:0] o_fft_X_real_7; +wire [17:0] o_fft_X_imag_7; +wire [17:0] o_fft_X_real_8; +wire [17:0] o_fft_X_imag_8; +wire [17:0] o_fft_X_real_9; +wire [17:0] o_fft_X_imag_9; +wire [17:0] o_fft_X_real_10; +wire [17:0] o_fft_X_imag_10; +wire [17:0] o_fft_X_real_11; +wire [17:0] o_fft_X_imag_11; +wire [17:0] o_fft_X_real_12; +wire [17:0] o_fft_X_imag_12; +wire [17:0] o_fft_X_real_13; +wire [17:0] o_fft_X_imag_13; +wire [17:0] o_fft_X_real_14; +wire [17:0] o_fft_X_imag_14; +wire [17:0] o_fft_X_real_15; +wire [17:0] o_fft_X_imag_15; + +// Hold weights value until X_FFT finishes +assign W_real_wires_0_0 = reg_W_real_0_0; +assign W_imag_wires_0_0 = reg_W_imag_0_0; +assign W_real_wires_0_1 = reg_W_real_0_1; +assign W_imag_wires_0_1 = reg_W_imag_0_1; +assign W_real_wires_0_2 = reg_W_real_0_2; +assign W_imag_wires_0_2 = reg_W_imag_0_2; +assign W_real_wires_0_3 = reg_W_real_0_3; +assign W_imag_wires_0_3 = reg_W_imag_0_3; +assign W_real_wires_0_4 = reg_W_real_0_4; +assign W_imag_wires_0_4 = reg_W_imag_0_4; +assign W_real_wires_0_5 = reg_W_real_0_5; +assign W_imag_wires_0_5 = reg_W_imag_0_5; +assign W_real_wires_0_6 = reg_W_real_0_6; +assign W_imag_wires_0_6 = reg_W_imag_0_6; +assign W_real_wires_0_7 = reg_W_real_0_7; +assign W_imag_wires_0_7 = reg_W_imag_0_7; +assign W_real_wires_0_8 = reg_W_real_0_8; +assign W_imag_wires_0_8 = reg_W_imag_0_8; + +shift_register_group_18_910 shift_register_group_18_910_inst_0_real ( + .clk(clk), + .enable(enable), + .in_0(W_real_wires_0_0), + .out_0(W_real_holder_0_0), + .in_1(W_real_wires_0_1), + .out_1(W_real_holder_0_1), + .in_2(W_real_wires_0_2), + .out_2(W_real_holder_0_2), + .in_3(W_real_wires_0_3), + .out_3(W_real_holder_0_3), + .in_4(W_real_wires_0_4), + .out_4(W_real_holder_0_4), + .in_5(W_real_wires_0_5), + .out_5(W_real_holder_0_5), + .in_6(W_real_wires_0_6), + .out_6(W_real_holder_0_6), + .in_7(W_real_wires_0_7), + .out_7(W_real_holder_0_7), + .in_8(W_real_wires_0_8), + .out_8(W_real_holder_0_8), + .reset(reset) +); + +shift_register_group_18_910 shift_register_group_18_910_inst_0_imag ( + .clk(clk), + .enable(enable), + .in_0(W_imag_wires_0_0), + .out_0(W_imag_holder_0_0), + .in_1(W_imag_wires_0_1), + .out_1(W_imag_holder_0_1), + .in_2(W_imag_wires_0_2), + .out_2(W_imag_holder_0_2), + .in_3(W_imag_wires_0_3), + .out_3(W_imag_holder_0_3), + .in_4(W_imag_wires_0_4), + .out_4(W_imag_holder_0_4), + .in_5(W_imag_wires_0_5), + .out_5(W_imag_holder_0_5), + .in_6(W_imag_wires_0_6), + .out_6(W_imag_holder_0_6), + .in_7(W_imag_wires_0_7), + .out_7(W_imag_holder_0_7), + .in_8(W_imag_wires_0_8), + .out_8(W_imag_holder_0_8), + .reset(reset) +); + +dft_16_top_18 dft_16_top_18_inst_pjmnmgldmq ( + .clk(clk), + .reset(reset), + .next(reg_i_valid), + .X0(reg_X_2_0), + .Y0(o_fft_X_real_0), + .X1(18'd0), + .Y1(o_fft_X_imag_0), + .X2(reg_X_2_1), + .Y2(o_fft_X_real_1), + .X3(18'd0), + .Y3(o_fft_X_imag_1), + .X4(reg_X_2_2), + .Y4(o_fft_X_real_2), + .X5(18'd0), + .Y5(o_fft_X_imag_2), + .X6(reg_X_2_3), + .Y6(o_fft_X_real_3), + .X7(18'd0), + .Y7(o_fft_X_imag_3), + .X8(reg_X_2_4), + .Y8(o_fft_X_real_4), + .X9(18'd0), + .Y9(o_fft_X_imag_4), + .X10(reg_X_2_5), + .Y10(o_fft_X_real_5), + .X11(18'd0), + .Y11(o_fft_X_imag_5), + .X12(reg_X_2_6), + .Y12(o_fft_X_real_6), + .X13(18'd0), + .Y13(o_fft_X_imag_6), + .X14(reg_X_2_7), + .Y14(o_fft_X_real_7), + .X15(18'd0), + .Y15(o_fft_X_imag_7), + .X16(reg_X_2_8), + .Y16(o_fft_X_real_8), + .X17(18'd0), + .Y17(o_fft_X_imag_8), + .X18(reg_X_2_9), + .Y18(o_fft_X_real_9), + .X19(18'd0), + .Y19(o_fft_X_imag_9), + .X20(reg_X_2_10), + .Y20(o_fft_X_real_10), + .X21(18'd0), + .Y21(o_fft_X_imag_10), + .X22(reg_X_2_11), + .Y22(o_fft_X_real_11), + .X23(18'd0), + .Y23(o_fft_X_imag_11), + .X24(reg_X_2_12), + .Y24(o_fft_X_real_12), + .X25(18'd0), + .Y25(o_fft_X_imag_12), + .X26(reg_X_2_13), + .Y26(o_fft_X_real_13), + .X27(18'd0), + .Y27(o_fft_X_imag_13), + .X28(reg_X_2_14), + .Y28(o_fft_X_real_14), + .X29(18'd0), + .Y29(o_fft_X_imag_14), + .X30(reg_X_2_15), + .Y30(o_fft_X_real_15), + .X31(18'd0), + .Y31(o_fft_X_imag_15), + .next_out(o_fft_next) +); +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_0_real_real ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(W_real_holder_0_0), + .i_B_0(o_fft_X_real_0), + .o_C_0(o_mult_X_real_W_real_0_0), + .i_A_1(W_real_holder_0_1), + .i_B_1(o_fft_X_real_1), + .o_C_1(o_mult_X_real_W_real_0_1), + .i_A_2(W_real_holder_0_2), + .i_B_2(o_fft_X_real_2), + .o_C_2(o_mult_X_real_W_real_0_2), + .i_A_3(W_real_holder_0_3), + .i_B_3(o_fft_X_real_3), + .o_C_3(o_mult_X_real_W_real_0_3), + .i_A_4(W_real_holder_0_4), + .i_B_4(o_fft_X_real_4), + .o_C_4(o_mult_X_real_W_real_0_4), + .i_A_5(W_real_holder_0_5), + .i_B_5(o_fft_X_real_5), + .o_C_5(o_mult_X_real_W_real_0_5), + .i_A_6(W_real_holder_0_6), + .i_B_6(o_fft_X_real_6), + .o_C_6(o_mult_X_real_W_real_0_6), + .i_A_7(W_real_holder_0_7), + .i_B_7(o_fft_X_real_7), + .o_C_7(o_mult_X_real_W_real_0_7), + .i_A_8(W_real_holder_0_8), + .i_B_8(o_fft_X_real_8), + .o_C_8(o_mult_X_real_W_real_0_8), + .o_valid(mult_X_real_W_real_valid_0), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_0_real_imag ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(W_imag_holder_0_0), + .i_B_0(o_fft_X_real_0), + .o_C_0(o_mult_X_real_W_imag_0_0), + .i_A_1(W_imag_holder_0_1), + .i_B_1(o_fft_X_real_1), + .o_C_1(o_mult_X_real_W_imag_0_1), + .i_A_2(W_imag_holder_0_2), + .i_B_2(o_fft_X_real_2), + .o_C_2(o_mult_X_real_W_imag_0_2), + .i_A_3(W_imag_holder_0_3), + .i_B_3(o_fft_X_real_3), + .o_C_3(o_mult_X_real_W_imag_0_3), + .i_A_4(W_imag_holder_0_4), + .i_B_4(o_fft_X_real_4), + .o_C_4(o_mult_X_real_W_imag_0_4), + .i_A_5(W_imag_holder_0_5), + .i_B_5(o_fft_X_real_5), + .o_C_5(o_mult_X_real_W_imag_0_5), + .i_A_6(W_imag_holder_0_6), + .i_B_6(o_fft_X_real_6), + .o_C_6(o_mult_X_real_W_imag_0_6), + .i_A_7(W_imag_holder_0_7), + .i_B_7(o_fft_X_real_7), + .o_C_7(o_mult_X_real_W_imag_0_7), + .i_A_8(W_imag_holder_0_8), + .i_B_8(o_fft_X_real_8), + .o_C_8(o_mult_X_real_W_imag_0_8), + .o_valid(mult_X_real_W_imag_valid_0), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_0_imag_real ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(o_fft_X_imag_0), + .i_B_0(W_real_holder_0_0), + .o_C_0(o_mult_X_imag_W_real_0_0), + .i_A_1(o_fft_X_imag_1), + .i_B_1(W_real_holder_0_1), + .o_C_1(o_mult_X_imag_W_real_0_1), + .i_A_2(o_fft_X_imag_2), + .i_B_2(W_real_holder_0_2), + .o_C_2(o_mult_X_imag_W_real_0_2), + .i_A_3(o_fft_X_imag_3), + .i_B_3(W_real_holder_0_3), + .o_C_3(o_mult_X_imag_W_real_0_3), + .i_A_4(o_fft_X_imag_4), + .i_B_4(W_real_holder_0_4), + .o_C_4(o_mult_X_imag_W_real_0_4), + .i_A_5(o_fft_X_imag_5), + .i_B_5(W_real_holder_0_5), + .o_C_5(o_mult_X_imag_W_real_0_5), + .i_A_6(o_fft_X_imag_6), + .i_B_6(W_real_holder_0_6), + .o_C_6(o_mult_X_imag_W_real_0_6), + .i_A_7(o_fft_X_imag_7), + .i_B_7(W_real_holder_0_7), + .o_C_7(o_mult_X_imag_W_real_0_7), + .i_A_8(o_fft_X_imag_8), + .i_B_8(W_real_holder_0_8), + .o_C_8(o_mult_X_imag_W_real_0_8), + .o_valid(mult_X_imag_W_real_valid_0), + .o_ready() +); + +elementwise_mult_core_18_1810_9_1 elementwise_mult_core_18_1810_9_1_inst_0_imag_imag ( + .clk(clk), + .reset(reset), + .i_valid(fft_valid), + .i_ready(enable), + .i_A_0(o_fft_X_imag_0), + .i_B_0(W_imag_holder_0_0), + .o_C_0(o_mult_X_imag_W_imag_0_0), + .i_A_1(o_fft_X_imag_1), + .i_B_1(W_imag_holder_0_1), + .o_C_1(o_mult_X_imag_W_imag_0_1), + .i_A_2(o_fft_X_imag_2), + .i_B_2(W_imag_holder_0_2), + .o_C_2(o_mult_X_imag_W_imag_0_2), + .i_A_3(o_fft_X_imag_3), + .i_B_3(W_imag_holder_0_3), + .o_C_3(o_mult_X_imag_W_imag_0_3), + .i_A_4(o_fft_X_imag_4), + .i_B_4(W_imag_holder_0_4), + .o_C_4(o_mult_X_imag_W_imag_0_4), + .i_A_5(o_fft_X_imag_5), + .i_B_5(W_imag_holder_0_5), + .o_C_5(o_mult_X_imag_W_imag_0_5), + .i_A_6(o_fft_X_imag_6), + .i_B_6(W_imag_holder_0_6), + .o_C_6(o_mult_X_imag_W_imag_0_6), + .i_A_7(o_fft_X_imag_7), + .i_B_7(W_imag_holder_0_7), + .o_C_7(o_mult_X_imag_W_imag_0_7), + .i_A_8(o_fft_X_imag_8), + .i_B_8(W_imag_holder_0_8), + .o_C_8(o_mult_X_imag_W_imag_0_8), + .o_valid(mult_X_imag_W_imag_valid_0), + .o_ready() +); + +wire sub_core_valid_0; +assign sub_core_valid_0 = mult_X_real_W_real_valid_0 & mult_X_imag_W_imag_valid_0; + +elementwise_sub_core_18_18_9 elementwise_sub_core_18_18_9_inst_0 ( + .clk(clk), + .reset(reset), + .i_valid(sub_core_valid_0), + .i_ready(enable), + .i_A_0(o_mult_X_real_W_real_0_0), + .i_B_0(o_mult_X_imag_W_imag_0_0), + .o_C_0(o_sub_y_real_0_0), + .i_A_1(o_mult_X_real_W_real_0_1), + .i_B_1(o_mult_X_imag_W_imag_0_1), + .o_C_1(o_sub_y_real_0_1), + .i_A_2(o_mult_X_real_W_real_0_2), + .i_B_2(o_mult_X_imag_W_imag_0_2), + .o_C_2(o_sub_y_real_0_2), + .i_A_3(o_mult_X_real_W_real_0_3), + .i_B_3(o_mult_X_imag_W_imag_0_3), + .o_C_3(o_sub_y_real_0_3), + .i_A_4(o_mult_X_real_W_real_0_4), + .i_B_4(o_mult_X_imag_W_imag_0_4), + .o_C_4(o_sub_y_real_0_4), + .i_A_5(o_mult_X_real_W_real_0_5), + .i_B_5(o_mult_X_imag_W_imag_0_5), + .o_C_5(o_sub_y_real_0_5), + .i_A_6(o_mult_X_real_W_real_0_6), + .i_B_6(o_mult_X_imag_W_imag_0_6), + .o_C_6(o_sub_y_real_0_6), + .i_A_7(o_mult_X_real_W_real_0_7), + .i_B_7(o_mult_X_imag_W_imag_0_7), + .o_C_7(o_sub_y_real_0_7), + .i_A_8(o_mult_X_real_W_real_0_8), + .i_B_8(o_mult_X_imag_W_imag_0_8), + .o_C_8(o_sub_y_real_0_8), + .o_valid(sub_y_real_valid_0), + .o_ready() +); + +wire add_core_valid_0; +assign add_core_valid_0 = mult_X_real_W_imag_valid_0 & mult_X_imag_W_real_valid_0; + +elementwise_add_core_18_18_9 elementwise_add_core_18_18_9_inst_0 ( + .clk(clk), + .reset(reset), + .i_valid(add_core_valid_0), + .i_ready(enable), + .i_A_0(o_mult_X_real_W_imag_0_0), + .i_B_0(o_mult_X_imag_W_real_0_0), + .o_C_0(o_add_y_imag_0_0), + .i_A_1(o_mult_X_real_W_imag_0_1), + .i_B_1(o_mult_X_imag_W_real_0_1), + .o_C_1(o_add_y_imag_0_1), + .i_A_2(o_mult_X_real_W_imag_0_2), + .i_B_2(o_mult_X_imag_W_real_0_2), + .o_C_2(o_add_y_imag_0_2), + .i_A_3(o_mult_X_real_W_imag_0_3), + .i_B_3(o_mult_X_imag_W_real_0_3), + .o_C_3(o_add_y_imag_0_3), + .i_A_4(o_mult_X_real_W_imag_0_4), + .i_B_4(o_mult_X_imag_W_real_0_4), + .o_C_4(o_add_y_imag_0_4), + .i_A_5(o_mult_X_real_W_imag_0_5), + .i_B_5(o_mult_X_imag_W_real_0_5), + .o_C_5(o_add_y_imag_0_5), + .i_A_6(o_mult_X_real_W_imag_0_6), + .i_B_6(o_mult_X_imag_W_real_0_6), + .o_C_6(o_add_y_imag_0_6), + .i_A_7(o_mult_X_real_W_imag_0_7), + .i_B_7(o_mult_X_imag_W_real_0_7), + .o_C_7(o_add_y_imag_0_7), + .i_A_8(o_mult_X_real_W_imag_0_8), + .i_B_8(o_mult_X_imag_W_real_0_8), + .o_C_8(o_add_y_imag_0_8), + .o_valid(add_y_imag_valid_0), + .o_ready() +); + +always @ (posedge clk) begin + if (reset) begin + reg_i_valid <= 1'b0; + fft_valid <= 1'b0; + reg_o_valid <= 1'b0; + reg_o_ready <= 1'b0; + reg_X_0 <= 0; + reg_X_2_0 <= 0; + reg_X_1 <= 0; + reg_X_2_1 <= 0; + reg_X_2 <= 0; + reg_X_2_2 <= 0; + reg_X_3 <= 0; + reg_X_2_3 <= 0; + reg_X_4 <= 0; + reg_X_2_4 <= 0; + reg_X_5 <= 0; + reg_X_2_5 <= 0; + reg_X_6 <= 0; + reg_X_2_6 <= 0; + reg_X_7 <= 0; + reg_X_2_7 <= 0; + reg_X_8 <= 0; + reg_X_2_8 <= 0; + reg_X_9 <= 0; + reg_X_2_9 <= 0; + reg_X_10 <= 0; + reg_X_2_10 <= 0; + reg_X_11 <= 0; + reg_X_2_11 <= 0; + reg_X_12 <= 0; + reg_X_2_12 <= 0; + reg_X_13 <= 0; + reg_X_2_13 <= 0; + reg_X_14 <= 0; + reg_X_2_14 <= 0; + reg_X_15 <= 0; + reg_X_2_15 <= 0; + reg_W_real_0_0 <= 0; + reg_W_imag_0_0 <= 0; + reg_W_real_0_1 <= 0; + reg_W_imag_0_1 <= 0; + reg_W_real_0_2 <= 0; + reg_W_imag_0_2 <= 0; + reg_W_real_0_3 <= 0; + reg_W_imag_0_3 <= 0; + reg_W_real_0_4 <= 0; + reg_W_imag_0_4 <= 0; + reg_W_real_0_5 <= 0; + reg_W_imag_0_5 <= 0; + reg_W_real_0_6 <= 0; + reg_W_imag_0_6 <= 0; + reg_W_real_0_7 <= 0; + reg_W_imag_0_7 <= 0; + reg_W_real_0_8 <= 0; + reg_W_imag_0_8 <= 0; + reg_Y_real_0_0 <= 0; + reg_Y_imag_0_0 <= 0; + reg_Y_real_0_1 <= 0; + reg_Y_imag_0_1 <= 0; + reg_Y_real_0_2 <= 0; + reg_Y_imag_0_2 <= 0; + reg_Y_real_0_3 <= 0; + reg_Y_imag_0_3 <= 0; + reg_Y_real_0_4 <= 0; + reg_Y_imag_0_4 <= 0; + reg_Y_real_0_5 <= 0; + reg_Y_imag_0_5 <= 0; + reg_Y_real_0_6 <= 0; + reg_Y_imag_0_6 <= 0; + reg_Y_real_0_7 <= 0; + reg_Y_imag_0_7 <= 0; + reg_Y_real_0_8 <= 0; + reg_Y_imag_0_8 <= 0; + reg_Y_real_0_9 <= 0; + reg_Y_imag_0_9 <= 0; + reg_Y_real_0_10 <= 0; + reg_Y_imag_0_10 <= 0; + reg_Y_real_0_11 <= 0; + reg_Y_imag_0_11 <= 0; + reg_Y_real_0_12 <= 0; + reg_Y_imag_0_12 <= 0; + reg_Y_real_0_13 <= 0; + reg_Y_imag_0_13 <= 0; + reg_Y_real_0_14 <= 0; + reg_Y_imag_0_14 <= 0; + reg_Y_real_0_15 <= 0; + reg_Y_imag_0_15 <= 0; + end else if (enable) begin + reg_i_valid <= i_valid; + fft_valid <= o_fft_next; + reg_o_valid <= add_y_imag_valid_0 & sub_y_real_valid_0; + reg_o_ready <= ~i_valid & enable; + reg_X_0 <= i_X_0; + reg_X_2_0 <= reg_X_0; + reg_X_1 <= i_X_1; + reg_X_2_1 <= reg_X_1; + reg_X_2 <= i_X_2; + reg_X_2_2 <= reg_X_2; + reg_X_3 <= i_X_3; + reg_X_2_3 <= reg_X_3; + reg_X_4 <= i_X_4; + reg_X_2_4 <= reg_X_4; + reg_X_5 <= i_X_5; + reg_X_2_5 <= reg_X_5; + reg_X_6 <= i_X_6; + reg_X_2_6 <= reg_X_6; + reg_X_7 <= i_X_7; + reg_X_2_7 <= reg_X_7; + reg_X_8 <= i_X_8; + reg_X_2_8 <= reg_X_8; + reg_X_9 <= i_X_9; + reg_X_2_9 <= reg_X_9; + reg_X_10 <= i_X_10; + reg_X_2_10 <= reg_X_10; + reg_X_11 <= i_X_11; + reg_X_2_11 <= reg_X_11; + reg_X_12 <= i_X_12; + reg_X_2_12 <= reg_X_12; + reg_X_13 <= i_X_13; + reg_X_2_13 <= reg_X_13; + reg_X_14 <= i_X_14; + reg_X_2_14 <= reg_X_14; + reg_X_15 <= i_X_15; + reg_X_2_15 <= reg_X_15; + reg_W_real_0_0 <= i_W_real_0_0; + reg_W_imag_0_0 <= i_W_imag_0_0; + reg_W_real_0_1 <= i_W_real_0_1; + reg_W_imag_0_1 <= i_W_imag_0_1; + reg_W_real_0_2 <= i_W_real_0_2; + reg_W_imag_0_2 <= i_W_imag_0_2; + reg_W_real_0_3 <= i_W_real_0_3; + reg_W_imag_0_3 <= i_W_imag_0_3; + reg_W_real_0_4 <= i_W_real_0_4; + reg_W_imag_0_4 <= i_W_imag_0_4; + reg_W_real_0_5 <= i_W_real_0_5; + reg_W_imag_0_5 <= i_W_imag_0_5; + reg_W_real_0_6 <= i_W_real_0_6; + reg_W_imag_0_6 <= i_W_imag_0_6; + reg_W_real_0_7 <= i_W_real_0_7; + reg_W_imag_0_7 <= i_W_imag_0_7; + reg_W_real_0_8 <= i_W_real_0_8; + reg_W_imag_0_8 <= i_W_imag_0_8; + reg_Y_real_0_0 <= o_sub_y_real_0_0; + reg_Y_imag_0_0 <= o_add_y_imag_0_0; + reg_Y_real_0_1 <= o_sub_y_real_0_1; + reg_Y_imag_0_1 <= o_add_y_imag_0_1; + reg_Y_real_0_2 <= o_sub_y_real_0_2; + reg_Y_imag_0_2 <= o_add_y_imag_0_2; + reg_Y_real_0_3 <= o_sub_y_real_0_3; + reg_Y_imag_0_3 <= o_add_y_imag_0_3; + reg_Y_real_0_4 <= o_sub_y_real_0_4; + reg_Y_imag_0_4 <= o_add_y_imag_0_4; + reg_Y_real_0_5 <= o_sub_y_real_0_5; + reg_Y_imag_0_5 <= o_add_y_imag_0_5; + reg_Y_real_0_6 <= o_sub_y_real_0_6; + reg_Y_imag_0_6 <= o_add_y_imag_0_6; + reg_Y_real_0_7 <= o_sub_y_real_0_7; + reg_Y_imag_0_7 <= o_add_y_imag_0_7; + reg_Y_real_0_8 <= o_sub_y_real_0_8; + reg_Y_imag_0_8 <= o_add_y_imag_0_8; + reg_Y_real_0_9 <= o_sub_y_real_0_7; + reg_Y_imag_0_9 <= -o_add_y_imag_0_7; + reg_Y_real_0_10 <= o_sub_y_real_0_6; + reg_Y_imag_0_10 <= -o_add_y_imag_0_6; + reg_Y_real_0_11 <= o_sub_y_real_0_5; + reg_Y_imag_0_11 <= -o_add_y_imag_0_5; + reg_Y_real_0_12 <= o_sub_y_real_0_4; + reg_Y_imag_0_12 <= -o_add_y_imag_0_4; + reg_Y_real_0_13 <= o_sub_y_real_0_3; + reg_Y_imag_0_13 <= -o_add_y_imag_0_3; + reg_Y_real_0_14 <= o_sub_y_real_0_2; + reg_Y_imag_0_14 <= -o_add_y_imag_0_2; + reg_Y_real_0_15 <= o_sub_y_real_0_1; + reg_Y_imag_0_15 <= -o_add_y_imag_0_1; + end +end + +assign o_ready = reg_o_ready & i_ready; +assign o_valid = reg_o_valid; +assign o_Y_real_0_0 = reg_Y_real_0_0; +assign o_Y_imag_0_0 = reg_Y_imag_0_0; +assign o_Y_real_0_1 = reg_Y_real_0_1; +assign o_Y_imag_0_1 = reg_Y_imag_0_1; +assign o_Y_real_0_2 = reg_Y_real_0_2; +assign o_Y_imag_0_2 = reg_Y_imag_0_2; +assign o_Y_real_0_3 = reg_Y_real_0_3; +assign o_Y_imag_0_3 = reg_Y_imag_0_3; +assign o_Y_real_0_4 = reg_Y_real_0_4; +assign o_Y_imag_0_4 = reg_Y_imag_0_4; +assign o_Y_real_0_5 = reg_Y_real_0_5; +assign o_Y_imag_0_5 = reg_Y_imag_0_5; +assign o_Y_real_0_6 = reg_Y_real_0_6; +assign o_Y_imag_0_6 = reg_Y_imag_0_6; +assign o_Y_real_0_7 = reg_Y_real_0_7; +assign o_Y_imag_0_7 = reg_Y_imag_0_7; +assign o_Y_real_0_8 = reg_Y_real_0_8; +assign o_Y_imag_0_8 = reg_Y_imag_0_8; +assign o_Y_real_0_9 = reg_Y_real_0_9; +assign o_Y_imag_0_9 = reg_Y_imag_0_9; +assign o_Y_real_0_10 = reg_Y_real_0_10; +assign o_Y_imag_0_10 = reg_Y_imag_0_10; +assign o_Y_real_0_11 = reg_Y_real_0_11; +assign o_Y_imag_0_11 = reg_Y_imag_0_11; +assign o_Y_real_0_12 = reg_Y_real_0_12; +assign o_Y_imag_0_12 = reg_Y_imag_0_12; +assign o_Y_real_0_13 = reg_Y_real_0_13; +assign o_Y_imag_0_13 = reg_Y_imag_0_13; +assign o_Y_real_0_14 = reg_Y_real_0_14; +assign o_Y_imag_0_14 = reg_Y_imag_0_14; +assign o_Y_real_0_15 = reg_Y_real_0_15; +assign o_Y_imag_0_15 = reg_Y_imag_0_15; + +endmodule + +module shift_register_group_18_910 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input reset +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_10 shift_register_unit_18_10_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +endmodule + +module shift_register_unit_18_10 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +reg [17:0] shift_registers_1; +reg [17:0] shift_registers_2; +reg [17:0] shift_registers_3; +reg [17:0] shift_registers_4; +reg [17:0] shift_registers_5; +reg [17:0] shift_registers_6; +reg [17:0] shift_registers_7; +reg [17:0] shift_registers_8; +reg [17:0] shift_registers_9; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + shift_registers_1 <= 18'd0; + shift_registers_2 <= 18'd0; + shift_registers_3 <= 18'd0; + shift_registers_4 <= 18'd0; + shift_registers_5 <= 18'd0; + shift_registers_6 <= 18'd0; + shift_registers_7 <= 18'd0; + shift_registers_8 <= 18'd0; + shift_registers_9 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + shift_registers_3 <= shift_registers_2; + shift_registers_4 <= shift_registers_3; + shift_registers_5 <= shift_registers_4; + shift_registers_6 <= shift_registers_5; + shift_registers_7 <= shift_registers_6; + shift_registers_8 <= shift_registers_7; + shift_registers_9 <= shift_registers_8; + end +end + +assign out = shift_registers_9; + +endmodule + +module dft_16_top_18 ( + input clk, + input reset, + input next, + input [17:0] X0, + output [17:0] Y0, + input [17:0] X1, + output [17:0] Y1, + input [17:0] X2, + output [17:0] Y2, + input [17:0] X3, + output [17:0] Y3, + input [17:0] X4, + output [17:0] Y4, + input [17:0] X5, + output [17:0] Y5, + input [17:0] X6, + output [17:0] Y6, + input [17:0] X7, + output [17:0] Y7, + input [17:0] X8, + output [17:0] Y8, + input [17:0] X9, + output [17:0] Y9, + input [17:0] X10, + output [17:0] Y10, + input [17:0] X11, + output [17:0] Y11, + input [17:0] X12, + output [17:0] Y12, + input [17:0] X13, + output [17:0] Y13, + input [17:0] X14, + output [17:0] Y14, + input [17:0] X15, + output [17:0] Y15, + input [17:0] X16, + output [17:0] Y16, + input [17:0] X17, + output [17:0] Y17, + input [17:0] X18, + output [17:0] Y18, + input [17:0] X19, + output [17:0] Y19, + input [17:0] X20, + output [17:0] Y20, + input [17:0] X21, + output [17:0] Y21, + input [17:0] X22, + output [17:0] Y22, + input [17:0] X23, + output [17:0] Y23, + input [17:0] X24, + output [17:0] Y24, + input [17:0] X25, + output [17:0] Y25, + input [17:0] X26, + output [17:0] Y26, + input [17:0] X27, + output [17:0] Y27, + input [17:0] X28, + output [17:0] Y28, + input [17:0] X29, + output [17:0] Y29, + input [17:0] X30, + output [17:0] Y30, + input [17:0] X31, + output [17:0] Y31, + output next_out +); + +wire [17:0] t0_0; +wire [17:0] t0_1; +wire [17:0] t0_2; +wire [17:0] t0_3; +wire [17:0] t0_4; +wire [17:0] t0_5; +wire [17:0] t0_6; +wire [17:0] t0_7; +wire [17:0] t0_8; +wire [17:0] t0_9; +wire [17:0] t0_10; +wire [17:0] t0_11; +wire [17:0] t0_12; +wire [17:0] t0_13; +wire [17:0] t0_14; +wire [17:0] t0_15; +wire [17:0] t0_16; +wire [17:0] t0_17; +wire [17:0] t0_18; +wire [17:0] t0_19; +wire [17:0] t0_20; +wire [17:0] t0_21; +wire [17:0] t0_22; +wire [17:0] t0_23; +wire [17:0] t0_24; +wire [17:0] t0_25; +wire [17:0] t0_26; +wire [17:0] t0_27; +wire [17:0] t0_28; +wire [17:0] t0_29; +wire [17:0] t0_30; +wire [17:0] t0_31; +wire next_0; +wire [17:0] t1_0; +wire [17:0] t1_1; +wire [17:0] t1_2; +wire [17:0] t1_3; +wire [17:0] t1_4; +wire [17:0] t1_5; +wire [17:0] t1_6; +wire [17:0] t1_7; +wire [17:0] t1_8; +wire [17:0] t1_9; +wire [17:0] t1_10; +wire [17:0] t1_11; +wire [17:0] t1_12; +wire [17:0] t1_13; +wire [17:0] t1_14; +wire [17:0] t1_15; +wire [17:0] t1_16; +wire [17:0] t1_17; +wire [17:0] t1_18; +wire [17:0] t1_19; +wire [17:0] t1_20; +wire [17:0] t1_21; +wire [17:0] t1_22; +wire [17:0] t1_23; +wire [17:0] t1_24; +wire [17:0] t1_25; +wire [17:0] t1_26; +wire [17:0] t1_27; +wire [17:0] t1_28; +wire [17:0] t1_29; +wire [17:0] t1_30; +wire [17:0] t1_31; +wire next_1; +wire [17:0] t2_0; +wire [17:0] t2_1; +wire [17:0] t2_2; +wire [17:0] t2_3; +wire [17:0] t2_4; +wire [17:0] t2_5; +wire [17:0] t2_6; +wire [17:0] t2_7; +wire [17:0] t2_8; +wire [17:0] t2_9; +wire [17:0] t2_10; +wire [17:0] t2_11; +wire [17:0] t2_12; +wire [17:0] t2_13; +wire [17:0] t2_14; +wire [17:0] t2_15; +wire [17:0] t2_16; +wire [17:0] t2_17; +wire [17:0] t2_18; +wire [17:0] t2_19; +wire [17:0] t2_20; +wire [17:0] t2_21; +wire [17:0] t2_22; +wire [17:0] t2_23; +wire [17:0] t2_24; +wire [17:0] t2_25; +wire [17:0] t2_26; +wire [17:0] t2_27; +wire [17:0] t2_28; +wire [17:0] t2_29; +wire [17:0] t2_30; +wire [17:0] t2_31; +wire next_2; + +assign t0_0 = X0; +assign Y0 = t2_0; +assign t0_1 = X1; +assign Y1 = t2_1; +assign t0_2 = X2; +assign Y2 = t2_2; +assign t0_3 = X3; +assign Y3 = t2_3; +assign t0_4 = X4; +assign Y4 = t2_4; +assign t0_5 = X5; +assign Y5 = t2_5; +assign t0_6 = X6; +assign Y6 = t2_6; +assign t0_7 = X7; +assign Y7 = t2_7; +assign t0_8 = X8; +assign Y8 = t2_8; +assign t0_9 = X9; +assign Y9 = t2_9; +assign t0_10 = X10; +assign Y10 = t2_10; +assign t0_11 = X11; +assign Y11 = t2_11; +assign t0_12 = X12; +assign Y12 = t2_12; +assign t0_13 = X13; +assign Y13 = t2_13; +assign t0_14 = X14; +assign Y14 = t2_14; +assign t0_15 = X15; +assign Y15 = t2_15; +assign t0_16 = X16; +assign Y16 = t2_16; +assign t0_17 = X17; +assign Y17 = t2_17; +assign t0_18 = X18; +assign Y18 = t2_18; +assign t0_19 = X19; +assign Y19 = t2_19; +assign t0_20 = X20; +assign Y20 = t2_20; +assign t0_21 = X21; +assign Y21 = t2_21; +assign t0_22 = X22; +assign Y22 = t2_22; +assign t0_23 = X23; +assign Y23 = t2_23; +assign t0_24 = X24; +assign Y24 = t2_24; +assign t0_25 = X25; +assign Y25 = t2_25; +assign t0_26 = X26; +assign Y26 = t2_26; +assign t0_27 = X27; +assign Y27 = t2_27; +assign t0_28 = X28; +assign Y28 = t2_28; +assign t0_29 = X29; +assign Y29 = t2_29; +assign t0_30 = X30; +assign Y30 = t2_30; +assign t0_31 = X31; +assign Y31 = t2_31; +assign next_0 = next; +assign next_out = next_2; +codeBlock88206_18 codeBlock88206_18_inst_khhlufntpz ( + .clk(clk), + .reset(reset), + .next_in(next_0), + .X0_in(t0_0), + .Y0(t1_0), + .X1_in(t0_1), + .Y1(t1_1), + .X2_in(t0_2), + .Y2(t1_2), + .X3_in(t0_3), + .Y3(t1_3), + .X4_in(t0_4), + .Y4(t1_4), + .X5_in(t0_5), + .Y5(t1_5), + .X6_in(t0_6), + .Y6(t1_6), + .X7_in(t0_7), + .Y7(t1_7), + .X8_in(t0_8), + .Y8(t1_8), + .X9_in(t0_9), + .Y9(t1_9), + .X10_in(t0_10), + .Y10(t1_10), + .X11_in(t0_11), + .Y11(t1_11), + .X12_in(t0_12), + .Y12(t1_12), + .X13_in(t0_13), + .Y13(t1_13), + .X14_in(t0_14), + .Y14(t1_14), + .X15_in(t0_15), + .Y15(t1_15), + .X16_in(t0_16), + .Y16(t1_16), + .X17_in(t0_17), + .Y17(t1_17), + .X18_in(t0_18), + .Y18(t1_18), + .X19_in(t0_19), + .Y19(t1_19), + .X20_in(t0_20), + .Y20(t1_20), + .X21_in(t0_21), + .Y21(t1_21), + .X22_in(t0_22), + .Y22(t1_22), + .X23_in(t0_23), + .Y23(t1_23), + .X24_in(t0_24), + .Y24(t1_24), + .X25_in(t0_25), + .Y25(t1_25), + .X26_in(t0_26), + .Y26(t1_26), + .X27_in(t0_27), + .Y27(t1_27), + .X28_in(t0_28), + .Y28(t1_28), + .X29_in(t0_29), + .Y29(t1_29), + .X30_in(t0_30), + .Y30(t1_30), + .X31_in(t0_31), + .Y31(t1_31), + .next_out(next_1) +); + +codeBlock89324_18 codeBlock89324_18_inst_wkywadjwfn ( + .clk(clk), + .reset(reset), + .next_in(next_1), + .X0_in(t1_0), + .Y0(t2_0), + .X1_in(t1_1), + .Y1(t2_1), + .X2_in(t1_2), + .Y2(t2_2), + .X3_in(t1_3), + .Y3(t2_3), + .X4_in(t1_4), + .Y4(t2_4), + .X5_in(t1_5), + .Y5(t2_5), + .X6_in(t1_6), + .Y6(t2_6), + .X7_in(t1_7), + .Y7(t2_7), + .X8_in(t1_8), + .Y8(t2_8), + .X9_in(t1_9), + .Y9(t2_9), + .X10_in(t1_10), + .Y10(t2_10), + .X11_in(t1_11), + .Y11(t2_11), + .X12_in(t1_12), + .Y12(t2_12), + .X13_in(t1_13), + .Y13(t2_13), + .X14_in(t1_14), + .Y14(t2_14), + .X15_in(t1_15), + .Y15(t2_15), + .X16_in(t1_16), + .Y16(t2_16), + .X17_in(t1_17), + .Y17(t2_17), + .X18_in(t1_18), + .Y18(t2_18), + .X19_in(t1_19), + .Y19(t2_19), + .X20_in(t1_20), + .Y20(t2_20), + .X21_in(t1_21), + .Y21(t2_21), + .X22_in(t1_22), + .Y22(t2_22), + .X23_in(t1_23), + .Y23(t2_23), + .X24_in(t1_24), + .Y24(t2_24), + .X25_in(t1_25), + .Y25(t2_25), + .X26_in(t1_26), + .Y26(t2_26), + .X27_in(t1_27), + .Y27(t2_27), + .X28_in(t1_28), + .Y28(t2_28), + .X29_in(t1_29), + .Y29(t2_29), + .X30_in(t1_30), + .Y30(t2_30), + .X31_in(t1_31), + .Y31(t2_31), + .next_out(next_2) +); + +endmodule + +module codeBlock88206_18 ( + input clk, + input reset, + input next_in, + input [17:0] X0_in, + output [17:0] Y0, + input [17:0] X1_in, + output [17:0] Y1, + input [17:0] X2_in, + output [17:0] Y2, + input [17:0] X3_in, + output [17:0] Y3, + input [17:0] X4_in, + output [17:0] Y4, + input [17:0] X5_in, + output [17:0] Y5, + input [17:0] X6_in, + output [17:0] Y6, + input [17:0] X7_in, + output [17:0] Y7, + input [17:0] X8_in, + output [17:0] Y8, + input [17:0] X9_in, + output [17:0] Y9, + input [17:0] X10_in, + output [17:0] Y10, + input [17:0] X11_in, + output [17:0] Y11, + input [17:0] X12_in, + output [17:0] Y12, + input [17:0] X13_in, + output [17:0] Y13, + input [17:0] X14_in, + output [17:0] Y14, + input [17:0] X15_in, + output [17:0] Y15, + input [17:0] X16_in, + output [17:0] Y16, + input [17:0] X17_in, + output [17:0] Y17, + input [17:0] X18_in, + output [17:0] Y18, + input [17:0] X19_in, + output [17:0] Y19, + input [17:0] X20_in, + output [17:0] Y20, + input [17:0] X21_in, + output [17:0] Y21, + input [17:0] X22_in, + output [17:0] Y22, + input [17:0] X23_in, + output [17:0] Y23, + input [17:0] X24_in, + output [17:0] Y24, + input [17:0] X25_in, + output [17:0] Y25, + input [17:0] X26_in, + output [17:0] Y26, + input [17:0] X27_in, + output [17:0] Y27, + input [17:0] X28_in, + output [17:0] Y28, + input [17:0] X29_in, + output [17:0] Y29, + input [17:0] X30_in, + output [17:0] Y30, + input [17:0] X31_in, + output [17:0] Y31, + output next_out +); + +reg next; +reg [17:0] X0; +reg [17:0] X1; +reg [17:0] X2; +reg [17:0] X3; +reg [17:0] X4; +reg [17:0] X5; +reg [17:0] X6; +reg [17:0] X7; +reg [17:0] X8; +reg [17:0] X9; +reg [17:0] X10; +reg [17:0] X11; +reg [17:0] X12; +reg [17:0] X13; +reg [17:0] X14; +reg [17:0] X15; +reg [17:0] X16; +reg [17:0] X17; +reg [17:0] X18; +reg [17:0] X19; +reg [17:0] X20; +reg [17:0] X21; +reg [17:0] X22; +reg [17:0] X23; +reg [17:0] X24; +reg [17:0] X25; +reg [17:0] X26; +reg [17:0] X27; +reg [17:0] X28; +reg [17:0] X29; +reg [17:0] X30; +reg [17:0] X31; +shiftRegFIFO_5_1 shiftRegFIFO_5_1_inst_qfpyulleag ( + .X(next), + .Y(next_out), + .reset(reset), + .clk(clk) +); +wire [17:0] a249; + wire [17:0] a250; + wire [17:0] a251; + wire [17:0] a252; + wire [17:0] a257; + wire [17:0] a258; + wire [17:0] a259; + wire [17:0] a260; + wire [17:0] a265; + wire [17:0] a266; + wire [17:0] a267; + wire [17:0] a268; + wire [17:0] a273; + wire [17:0] a274; + wire [17:0] a275; + wire [17:0] a276; + wire [17:0] a281; + wire [17:0] a282; + wire [17:0] a283; + wire [17:0] a284; + wire [17:0] a289; + wire [17:0] a290; + wire [17:0] a291; + wire [17:0] a292; + wire [17:0] a297; + wire [17:0] a298; + wire [17:0] a299; + wire [17:0] a300; + wire [17:0] a305; + wire [17:0] a306; + wire [17:0] a307; + wire [17:0] a308; + wire [17:0] t914; + wire [17:0] t915; + wire [17:0] t916; + wire [17:0] t917; + wire [17:0] t918; + wire [17:0] t919; + wire [17:0] t920; + wire [17:0] t921; + wire [17:0] t930; + wire [17:0] t931; + wire [17:0] t932; + wire [17:0] t933; + wire [17:0] t934; + wire [17:0] t935; + wire [17:0] t936; + wire [17:0] t937; + wire [17:0] t952; + wire [17:0] t953; + wire [17:0] t954; + wire [17:0] t955; + wire [17:0] t956; + wire [17:0] t957; + wire [17:0] t958; + wire [17:0] t959; + wire [17:0] t972; + wire [17:0] t973; + wire [17:0] t974; + wire [17:0] t975; + wire [17:0] t976; + wire [17:0] t977; + wire [17:0] t978; + wire [17:0] t979; + wire [17:0] t922; + wire [17:0] t923; + wire [17:0] t924; + wire [17:0] t925; + wire [17:0] t926; + wire [17:0] t927; + wire [17:0] t928; + wire [17:0] t929; + wire [17:0] t938; + wire [17:0] t939; + wire [17:0] t940; + wire [17:0] t941; + wire [17:0] t944; + wire [17:0] t945; + wire [17:0] t946; + wire [17:0] t947; + wire [17:0] t960; + wire [17:0] t961; + wire [17:0] t962; + wire [17:0] t963; + wire [17:0] t964; + wire [17:0] t965; + wire [17:0] t966; + wire [17:0] t967; + wire [17:0] t980; + wire [17:0] t981; + wire [17:0] t982; + wire [17:0] t983; + wire [17:0] t986; + wire [17:0] t987; + wire [17:0] t988; + wire [17:0] t989; + reg [17:0] tm24; + reg [17:0] tm27; + reg [17:0] tm30; + reg [17:0] tm33; + reg [17:0] tm36; + reg [17:0] tm39; + reg [17:0] tm42; + reg [17:0] tm45; + reg [17:0] tm48; + reg [17:0] tm51; + reg [17:0] tm54; + reg [17:0] tm57; + reg [17:0] tm60; + reg [17:0] tm63; + reg [17:0] tm66; + reg [17:0] tm69; + wire [17:0] a225; + wire [17:0] a226; + wire [17:0] a227; + wire [17:0] a228; + wire [17:0] a229; + wire [17:0] a230; + wire [17:0] a231; + wire [17:0] a232; + wire [17:0] a233; + wire [17:0] a234; + wire [17:0] a235; + wire [17:0] a236; + wire [17:0] a237; + wire [17:0] a238; + wire [17:0] a239; + wire [17:0] a240; + wire [17:0] a241; + wire [17:0] a242; + wire [17:0] a243; + wire [17:0] a244; + wire [17:0] a245; + wire [17:0] a246; + wire [17:0] a247; + wire [17:0] a248; + reg [17:0] tm25; + reg [17:0] tm28; + reg [17:0] tm31; + reg [17:0] tm34; + reg [17:0] tm37; + reg [17:0] tm40; + reg [17:0] tm43; + reg [17:0] tm46; + reg [17:0] tm49; + reg [17:0] tm52; + reg [17:0] tm55; + reg [17:0] tm58; + reg [17:0] tm61; + reg [17:0] tm64; + reg [17:0] tm67; + reg [17:0] tm70; + wire [17:0] t942; + wire [17:0] t943; + wire [17:0] t948; + wire [17:0] t949; + wire [17:0] t950; + wire [17:0] t951; + wire [17:0] t968; + wire [17:0] t969; + wire [17:0] t970; + wire [17:0] t971; + wire [17:0] t984; + wire [17:0] t985; + wire [17:0] t990; + wire [17:0] t991; + wire [17:0] t992; + wire [17:0] t993; + reg [17:0] tm26; + reg [17:0] tm29; + reg [17:0] tm32; + reg [17:0] tm35; + reg [17:0] tm38; + reg [17:0] tm41; + reg [17:0] tm44; + reg [17:0] tm47; + reg [17:0] tm50; + reg [17:0] tm53; + reg [17:0] tm56; + reg [17:0] tm59; + reg [17:0] tm62; + reg [17:0] tm65; + reg [17:0] tm68; + reg [17:0] tm71; + +wire [17:0] tm0; +assign tm0 = (18'hb505 >> (18-18)); +wire [17:0] tm2; +assign tm2 = (18'hec83 >> (18-18)); +wire [17:0] tm3; +assign tm3 = (18'h61f8 >> (18-18)); + +assign a249 = X0; + assign a250 = X16; + assign a251 = X1; + assign a252 = X17; + assign a257 = X8; + assign a258 = X24; + assign a259 = X9; + assign a260 = X25; + assign a265 = X2; + assign a266 = X18; + assign a267 = X3; + assign a268 = X19; + assign a273 = X10; + assign a274 = X26; + assign a275 = X11; + assign a276 = X27; + assign a281 = X4; + assign a282 = X20; + assign a283 = X5; + assign a284 = X21; + assign a289 = X12; + assign a290 = X28; + assign a291 = X13; + assign a292 = X29; + assign a297 = X6; + assign a298 = X22; + assign a299 = X7; + assign a300 = X23; + assign a305 = X14; + assign a306 = X30; + assign a307 = X15; + assign a308 = X31; + assign Y0 = tm26; + assign Y1 = tm29; + assign Y4 = tm32; + assign Y5 = tm35; + assign Y2 = tm38; + assign Y3 = tm41; + assign Y6 = tm44; + assign Y7 = tm47; + assign Y8 = tm50; + assign Y9 = tm53; + assign Y12 = t942; + assign Y13 = t943; + assign Y10 = t948; + assign Y11 = t949; + assign Y14 = t950; + assign Y15 = t951; + assign Y16 = tm56; + assign Y17 = tm59; + assign Y20 = tm62; + assign Y21 = tm65; + assign Y18 = t968; + assign Y19 = t969; + assign Y22 = t970; + assign Y23 = (~(t971)+1'b1); + assign Y24 = tm68; + assign Y25 = tm71; + assign Y28 = t984; + assign Y29 = (~(t985)+1'b1); + assign Y26 = t990; + assign Y27 = t991; + assign Y30 = (~(t992)+1'b1); + assign Y31 = t993; + +addfxp_18_1 add88218(.a(a249), .b(a250), .clk(clk), .q(t914)); + addfxp_18_1 add88233(.a(a251), .b(a252), .clk(clk), .q(t915)); + subfxp_18_1 sub88248(.a(a249), .b(a250), .clk(clk), .q(t916)); + subfxp_18_1 sub88263(.a(a251), .b(a252), .clk(clk), .q(t917)); + addfxp_18_1 add88278(.a(a257), .b(a258), .clk(clk), .q(t918)); + addfxp_18_1 add88293(.a(a259), .b(a260), .clk(clk), .q(t919)); + subfxp_18_1 sub88308(.a(a257), .b(a258), .clk(clk), .q(t920)); + subfxp_18_1 sub88323(.a(a259), .b(a260), .clk(clk), .q(t921)); + addfxp_18_1 add88426(.a(a265), .b(a266), .clk(clk), .q(t930)); + addfxp_18_1 add88441(.a(a267), .b(a268), .clk(clk), .q(t931)); + subfxp_18_1 sub88456(.a(a265), .b(a266), .clk(clk), .q(t932)); + subfxp_18_1 sub88471(.a(a267), .b(a268), .clk(clk), .q(t933)); + addfxp_18_1 add88486(.a(a273), .b(a274), .clk(clk), .q(t934)); + addfxp_18_1 add88501(.a(a275), .b(a276), .clk(clk), .q(t935)); + subfxp_18_1 sub88516(.a(a273), .b(a274), .clk(clk), .q(t936)); + subfxp_18_1 sub88531(.a(a275), .b(a276), .clk(clk), .q(t937)); + addfxp_18_1 add88746(.a(a281), .b(a282), .clk(clk), .q(t952)); + addfxp_18_1 add88761(.a(a283), .b(a284), .clk(clk), .q(t953)); + subfxp_18_1 sub88776(.a(a281), .b(a282), .clk(clk), .q(t954)); + subfxp_18_1 sub88791(.a(a283), .b(a284), .clk(clk), .q(t955)); + addfxp_18_1 add88806(.a(a289), .b(a290), .clk(clk), .q(t956)); + addfxp_18_1 add88821(.a(a291), .b(a292), .clk(clk), .q(t957)); + subfxp_18_1 sub88836(.a(a289), .b(a290), .clk(clk), .q(t958)); + subfxp_18_1 sub88851(.a(a291), .b(a292), .clk(clk), .q(t959)); + addfxp_18_1 add89012(.a(a297), .b(a298), .clk(clk), .q(t972)); + addfxp_18_1 add89027(.a(a299), .b(a300), .clk(clk), .q(t973)); + subfxp_18_1 sub89042(.a(a297), .b(a298), .clk(clk), .q(t974)); + subfxp_18_1 sub89057(.a(a299), .b(a300), .clk(clk), .q(t975)); + addfxp_18_1 add89072(.a(a305), .b(a306), .clk(clk), .q(t976)); + addfxp_18_1 add89087(.a(a307), .b(a308), .clk(clk), .q(t977)); + subfxp_18_1 sub89102(.a(a305), .b(a306), .clk(clk), .q(t978)); + subfxp_18_1 sub89117(.a(a307), .b(a308), .clk(clk), .q(t979)); + addfxp_18_1 add88330(.a(t914), .b(t918), .clk(clk), .q(t922)); + addfxp_18_1 add88337(.a(t915), .b(t919), .clk(clk), .q(t923)); + subfxp_18_1 sub88344(.a(t914), .b(t918), .clk(clk), .q(t924)); + subfxp_18_1 sub88351(.a(t915), .b(t919), .clk(clk), .q(t925)); + addfxp_18_1 add88374(.a(t916), .b(t921), .clk(clk), .q(t926)); + subfxp_18_1 sub88381(.a(t917), .b(t920), .clk(clk), .q(t927)); + subfxp_18_1 sub88388(.a(t916), .b(t921), .clk(clk), .q(t928)); + addfxp_18_1 add88395(.a(t917), .b(t920), .clk(clk), .q(t929)); + addfxp_18_1 add88538(.a(t930), .b(t934), .clk(clk), .q(t938)); + addfxp_18_1 add88545(.a(t931), .b(t935), .clk(clk), .q(t939)); + subfxp_18_1 sub88552(.a(t930), .b(t934), .clk(clk), .q(t940)); + subfxp_18_1 sub88559(.a(t931), .b(t935), .clk(clk), .q(t941)); + addfxp_18_1 add88610(.a(t932), .b(t937), .clk(clk), .q(t944)); + subfxp_18_1 sub88617(.a(t933), .b(t936), .clk(clk), .q(t945)); + subfxp_18_1 sub88624(.a(t932), .b(t937), .clk(clk), .q(t946)); + addfxp_18_1 add88631(.a(t933), .b(t936), .clk(clk), .q(t947)); + addfxp_18_1 add88858(.a(t952), .b(t956), .clk(clk), .q(t960)); + addfxp_18_1 add88865(.a(t953), .b(t957), .clk(clk), .q(t961)); + subfxp_18_1 sub88872(.a(t952), .b(t956), .clk(clk), .q(t962)); + subfxp_18_1 sub88879(.a(t953), .b(t957), .clk(clk), .q(t963)); + addfxp_18_1 add88903(.a(t954), .b(t959), .clk(clk), .q(t964)); + subfxp_18_1 sub88910(.a(t955), .b(t958), .clk(clk), .q(t965)); + subfxp_18_1 sub88917(.a(t954), .b(t959), .clk(clk), .q(t966)); + addfxp_18_1 add88924(.a(t955), .b(t958), .clk(clk), .q(t967)); + addfxp_18_1 add89124(.a(t972), .b(t976), .clk(clk), .q(t980)); + addfxp_18_1 add89131(.a(t973), .b(t977), .clk(clk), .q(t981)); + subfxp_18_1 sub89138(.a(t972), .b(t976), .clk(clk), .q(t982)); + subfxp_18_1 sub89145(.a(t973), .b(t977), .clk(clk), .q(t983)); + addfxp_18_1 add89197(.a(t974), .b(t979), .clk(clk), .q(t986)); + subfxp_18_1 sub89204(.a(t975), .b(t978), .clk(clk), .q(t987)); + subfxp_18_1 sub89211(.a(t974), .b(t979), .clk(clk), .q(t988)); + addfxp_18_1 add89218(.a(t975), .b(t978), .clk(clk), .q(t989)); + +multfix_alt_dsp_18 m88566(.ax(tm0), .ay(t940), .bx(tm0), .by(t941), .clk(clk), .a_q_sc(a225), .a_q_unsc(), .b_q_sc(a226), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88570(.ax(tm2), .ay(t944), .bx(tm3), .by(t945), .clk(clk), .a_q_sc(a227), .a_q_unsc(), .b_q_sc(a228), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88572(.ax(tm2), .ay(t945), .bx(tm3), .by(t944), .clk(clk), .a_q_sc(a229), .a_q_unsc(), .b_q_sc(a230), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88574(.ax(tm3), .ay(t946), .bx(tm2), .by(t947), .clk(clk), .a_q_sc(a231), .a_q_unsc(), .b_q_sc(a232), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88576(.ax(tm3), .ay(t947), .bx(tm2), .by(t946), .clk(clk), .a_q_sc(a233), .a_q_unsc(), .b_q_sc(a234), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88578(.ax(tm0), .ay(t964), .bx(tm0), .by(t965), .clk(clk), .a_q_sc(a235), .a_q_unsc(), .b_q_sc(a236), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88580(.ax(tm0), .ay(t967), .bx(tm0), .by(t966), .clk(clk), .a_q_sc(a237), .a_q_unsc(), .b_q_sc(a238), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88582(.ax(tm0), .ay(t983), .bx(tm0), .by(t982), .clk(clk), .a_q_sc(a239), .a_q_unsc(), .b_q_sc(a240), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88584(.ax(tm3), .ay(t986), .bx(tm2), .by(t987), .clk(clk), .a_q_sc(a241), .a_q_unsc(), .b_q_sc(a242), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88586(.ax(tm3), .ay(t987), .bx(tm2), .by(t986), .clk(clk), .a_q_sc(a243), .a_q_unsc(), .b_q_sc(a244), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88588(.ax(tm2), .ay(t988), .bx(tm3), .by(t989), .clk(clk), .a_q_sc(a245), .a_q_unsc(), .b_q_sc(a246), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88590(.ax(tm3), .ay(t988), .bx(tm2), .by(t989), .clk(clk), .a_q_sc(a247), .a_q_unsc(), .b_q_sc(a248), .b_q_unsc(), .rst(reset)); + +addfxp_18_1 add88580(.a(a225), .b(a226), .clk(clk), .q(t942)); + subfxp_18_1 sub88587(.a(a226), .b(a225), .clk(clk), .q(t943)); + addfxp_18_1 add88652(.a(a227), .b(a228), .clk(clk), .q(t948)); + subfxp_18_1 sub88673(.a(a229), .b(a230), .clk(clk), .q(t949)); + addfxp_18_1 add88694(.a(a231), .b(a232), .clk(clk), .q(t950)); + subfxp_18_1 sub88715(.a(a233), .b(a234), .clk(clk), .q(t951)); + addfxp_18_1 add88945(.a(a235), .b(a236), .clk(clk), .q(t968)); + subfxp_18_1 sub88952(.a(a236), .b(a235), .clk(clk), .q(t969)); + subfxp_18_1 sub88973(.a(a237), .b(a238), .clk(clk), .q(t970)); + addfxp_18_1 add88980(.a(a238), .b(a237), .clk(clk), .q(t971)); + subfxp_18_1 sub89166(.a(a239), .b(a240), .clk(clk), .q(t984)); + addfxp_18_1 add89173(.a(a240), .b(a239), .clk(clk), .q(t985)); + addfxp_18_1 add89239(.a(a241), .b(a242), .clk(clk), .q(t990)); + subfxp_18_1 sub89260(.a(a243), .b(a244), .clk(clk), .q(t991)); + addfxp_18_1 add89281(.a(a245), .b(a246), .clk(clk), .q(t992)); + subfxp_18_1 sub89302(.a(a247), .b(a248), .clk(clk), .q(t993)); + +always @(posedge clk) begin + if (reset == 1) begin + next <= 1'b0; + end else begin + X0 <= X0_in; + X1 <= X1_in; + X2 <= X2_in; + X3 <= X3_in; + X4 <= X4_in; + X5 <= X5_in; + X6 <= X6_in; + X7 <= X7_in; + X8 <= X8_in; + X9 <= X9_in; + X10 <= X10_in; + X11 <= X11_in; + X12 <= X12_in; + X13 <= X13_in; + X14 <= X14_in; + X15 <= X15_in; + X16 <= X16_in; + X17 <= X17_in; + X18 <= X18_in; + X19 <= X19_in; + X20 <= X20_in; + X21 <= X21_in; + X22 <= X22_in; + X23 <= X23_in; + X24 <= X24_in; + X25 <= X25_in; + X26 <= X26_in; + X27 <= X27_in; + X28 <= X28_in; + X29 <= X29_in; + X30 <= X30_in; + X31 <= X31_in; + next <= next_in; + tm24 <= t922; + tm27 <= t923; + tm30 <= t924; + tm33 <= t925; + tm36 <= t926; + tm39 <= t927; + tm42 <= t928; + tm45 <= t929; + tm48 <= t938; + tm51 <= t939; + tm54 <= t960; + tm57 <= t961; + tm60 <= t963; + tm63 <= (~(t962)+1'b1); + tm66 <= t980; + tm69 <= t981; + tm25 <= tm24; + tm28 <= tm27; + tm31 <= tm30; + tm34 <= tm33; + tm37 <= tm36; + tm40 <= tm39; + tm43 <= tm42; + tm46 <= tm45; + tm49 <= tm48; + tm52 <= tm51; + tm55 <= tm54; + tm58 <= tm57; + tm61 <= tm60; + tm64 <= tm63; + tm67 <= tm66; + tm70 <= tm69; + tm26 <= tm25; + tm29 <= tm28; + tm32 <= tm31; + tm35 <= tm34; + tm38 <= tm37; + tm41 <= tm40; + tm44 <= tm43; + tm47 <= tm46; + tm50 <= tm49; + tm53 <= tm52; + tm56 <= tm55; + tm59 <= tm58; + tm62 <= tm61; + tm65 <= tm64; + tm68 <= tm67; + tm71 <= tm70; + end +end + +endmodule + +module shiftRegFIFO_5_1 ( + input [0:0] X, + output [0:0] Y, + input reset, + input clk +); + +reg [0:0] mem_0; +reg [0:0] mem_1; +reg [0:0] mem_2; +reg [0:0] mem_3; +reg [0:0] mem_4; +assign Y = mem_4; + +always @ (posedge clk) begin + if (reset) begin + mem_0 <= 0; + mem_1 <= 0; + mem_2 <= 0; + mem_3 <= 0; + mem_4 <= 0; + end else begin + mem_1 <= mem_0; + mem_2 <= mem_1; + mem_3 <= mem_2; + mem_4 <= mem_3; + mem_0 <= X; + end +end + +endmodule + +module addfxp_18_1 ( + input [17:0] a, + input [17:0] b, + input clk, + output [17:0] q +); + +reg [17:0] res_0; +assign q = res_0; + +always @(posedge clk) begin + res_0 <= a + b; +end + +endmodule + +module subfxp_18_1 ( + input [17:0] a, + input [17:0] b, + input clk, + output [17:0] q +); + +reg [17:0] res_0; +assign q = res_0; + +always @(posedge clk) begin + res_0 <= a + b; +end + +endmodule + +module multfix_alt_dsp_18 ( + input [17:0] ax, + input [17:0] ay, + input [17:0] bx, + input [17:0] by, + input clk, + output [17:0] a_q_sc, + output [17:0] a_q_unsc, + output [17:0] b_q_sc, + output [17:0] b_q_unsc, + input rst +); + +wire [35:0] a_res; +wire [35:0] b_res; + +assign a_q_unsc = a_res[17:0]; +assign a_q_sc = {a_res[35-1], a_res[32 :16]}; +assign b_q_unsc = b_res[17:0]; +assign b_q_sc = {b_res[35-1], b_res[32 :16]}; + +dsp_signed_mult_18x18_unit_18_36_0 dsp_signed_mult_18x18_unit_18_36_0_inst_pudzznssfz ( + .clk(clk), + .ena(1'b1), + .reset(rst), + .i_valid(), + .o_valid(), + .ax(ax), + .ay(ay), + .bx(bx), + .by(by), + .resulta(a_res), + .resultb(b_res) +); + +endmodule + +module dsp_signed_mult_18x18_unit_18_36_0 ( + input clk, + input reset, + input ena, + input i_valid, + input [17:0] ax, + input [17:0] ay, + input [17:0] bx, + input [17:0] by, + output o_valid, + output [35:0] resulta, + output [35:0] resultb +); + +reg [35:0] reg_resa, reg_resb; +reg valid_rr; +always @(posedge clk) begin + if (reset) begin + reg_resa <= 0; + reg_resb <= 0; + valid_rr <= 0; + end else if (ena) begin + reg_resa <= ax * ay; + reg_resb <= bx * by; + valid_rr <= ena; + end +end +assign resulta = reg_resa; +assign resultb = reg_resb; +assign o_valid = valid_rr; +endmodule + +module codeBlock89324_18 ( + input clk, + input reset, + input next_in, + input [17:0] X0_in, + output [17:0] Y0, + input [17:0] X1_in, + output [17:0] Y1, + input [17:0] X2_in, + output [17:0] Y2, + input [17:0] X3_in, + output [17:0] Y3, + input [17:0] X4_in, + output [17:0] Y4, + input [17:0] X5_in, + output [17:0] Y5, + input [17:0] X6_in, + output [17:0] Y6, + input [17:0] X7_in, + output [17:0] Y7, + input [17:0] X8_in, + output [17:0] Y8, + input [17:0] X9_in, + output [17:0] Y9, + input [17:0] X10_in, + output [17:0] Y10, + input [17:0] X11_in, + output [17:0] Y11, + input [17:0] X12_in, + output [17:0] Y12, + input [17:0] X13_in, + output [17:0] Y13, + input [17:0] X14_in, + output [17:0] Y14, + input [17:0] X15_in, + output [17:0] Y15, + input [17:0] X16_in, + output [17:0] Y16, + input [17:0] X17_in, + output [17:0] Y17, + input [17:0] X18_in, + output [17:0] Y18, + input [17:0] X19_in, + output [17:0] Y19, + input [17:0] X20_in, + output [17:0] Y20, + input [17:0] X21_in, + output [17:0] Y21, + input [17:0] X22_in, + output [17:0] Y22, + input [17:0] X23_in, + output [17:0] Y23, + input [17:0] X24_in, + output [17:0] Y24, + input [17:0] X25_in, + output [17:0] Y25, + input [17:0] X26_in, + output [17:0] Y26, + input [17:0] X27_in, + output [17:0] Y27, + input [17:0] X28_in, + output [17:0] Y28, + input [17:0] X29_in, + output [17:0] Y29, + input [17:0] X30_in, + output [17:0] Y30, + input [17:0] X31_in, + output [17:0] Y31, + output next_out +); + +reg next; +reg [17:0] X0; +reg [17:0] X1; +reg [17:0] X2; +reg [17:0] X3; +reg [17:0] X4; +reg [17:0] X5; +reg [17:0] X6; +reg [17:0] X7; +reg [17:0] X8; +reg [17:0] X9; +reg [17:0] X10; +reg [17:0] X11; +reg [17:0] X12; +reg [17:0] X13; +reg [17:0] X14; +reg [17:0] X15; +reg [17:0] X16; +reg [17:0] X17; +reg [17:0] X18; +reg [17:0] X19; +reg [17:0] X20; +reg [17:0] X21; +reg [17:0] X22; +reg [17:0] X23; +reg [17:0] X24; +reg [17:0] X25; +reg [17:0] X26; +reg [17:0] X27; +reg [17:0] X28; +reg [17:0] X29; +reg [17:0] X30; +reg [17:0] X31; + +shiftRegFIFO_2_1 shiftRegFIFO_2_1_inst_bcfmufnbgb ( + .X(next), + .Y(next_out), + .reset(reset), + .clk(clk) +); + +wire [17:0] a65; + wire [17:0] a66; + wire [17:0] a67; + wire [17:0] a68; + wire [17:0] a73; + wire [17:0] a74; + wire [17:0] a75; + wire [17:0] a76; + wire [17:0] a81; + wire [17:0] a82; + wire [17:0] a83; + wire [17:0] a84; + wire [17:0] a89; + wire [17:0] a90; + wire [17:0] a91; + wire [17:0] a92; + wire [17:0] a97; + wire [17:0] a98; + wire [17:0] a99; + wire [17:0] a100; + wire [17:0] a105; + wire [17:0] a106; + wire [17:0] a107; + wire [17:0] a108; + wire [17:0] a113; + wire [17:0] a114; + wire [17:0] a115; + wire [17:0] a116; + wire [17:0] a121; + wire [17:0] a122; + wire [17:0] a123; + wire [17:0] a124; + wire [17:0] t402; + wire [17:0] t403; + wire [17:0] t404; + wire [17:0] t405; + wire [17:0] t406; + wire [17:0] t407; + wire [17:0] t408; + wire [17:0] t409; + wire [17:0] t418; + wire [17:0] t419; + wire [17:0] t420; + wire [17:0] t421; + wire [17:0] t422; + wire [17:0] t423; + wire [17:0] t424; + wire [17:0] t425; + wire [17:0] t434; + wire [17:0] t435; + wire [17:0] t436; + wire [17:0] t437; + wire [17:0] t438; + wire [17:0] t439; + wire [17:0] t440; + wire [17:0] t441; + wire [17:0] t450; + wire [17:0] t451; + wire [17:0] t452; + wire [17:0] t453; + wire [17:0] t454; + wire [17:0] t455; + wire [17:0] t456; + wire [17:0] t457; + wire [17:0] t410; + wire [17:0] t411; + wire [17:0] t412; + wire [17:0] t413; + wire [17:0] t414; + wire [17:0] t415; + wire [17:0] t416; + wire [17:0] t417; + wire [17:0] t426; + wire [17:0] t427; + wire [17:0] t428; + wire [17:0] t429; + wire [17:0] t430; + wire [17:0] t431; + wire [17:0] t432; + wire [17:0] t433; + wire [17:0] t442; + wire [17:0] t443; + wire [17:0] t444; + wire [17:0] t445; + wire [17:0] t446; + wire [17:0] t447; + wire [17:0] t448; + wire [17:0] t449; + wire [17:0] t458; + wire [17:0] t459; + wire [17:0] t460; + wire [17:0] t461; + wire [17:0] t462; + wire [17:0] t463; + wire [17:0] t464; + wire [17:0] t465; +assign a65 = X0; + assign a66 = X16; + assign a67 = X1; + assign a68 = X17; + assign a73 = X8; + assign a74 = X24; + assign a75 = X9; + assign a76 = X25; + assign a81 = X2; + assign a82 = X18; + assign a83 = X3; + assign a84 = X19; + assign a89 = X10; + assign a90 = X26; + assign a91 = X11; + assign a92 = X27; + assign a97 = X4; + assign a98 = X20; + assign a99 = X5; + assign a100 = X21; + assign a105 = X12; + assign a106 = X28; + assign a107 = X13; + assign a108 = X29; + assign a113 = X6; + assign a114 = X22; + assign a115 = X7; + assign a116 = X23; + assign a121 = X14; + assign a122 = X30; + assign a123 = X15; + assign a124 = X31; + assign Y0 = t410; + assign Y1 = t411; + assign Y16 = t412; + assign Y17 = t413; + assign Y8 = t414; + assign Y9 = t415; + assign Y24 = t416; + assign Y25 = t417; + assign Y2 = t426; + assign Y3 = t427; + assign Y18 = t428; + assign Y19 = t429; + assign Y10 = t430; + assign Y11 = t431; + assign Y26 = t432; + assign Y27 = t433; + assign Y4 = t442; + assign Y5 = t443; + assign Y20 = t444; + assign Y21 = t445; + assign Y12 = t446; + assign Y13 = t447; + assign Y28 = t448; + assign Y29 = t449; + assign Y6 = t458; + assign Y7 = t459; + assign Y22 = t460; + assign Y23 = t461; + assign Y14 = t462; + assign Y15 = t463; + assign Y30 = t464; + assign Y31 = t465; + +addfxp_18_1 add89336(.a(a65), .b(a66), .clk(clk), .q(t402)); + addfxp_18_1 add89351(.a(a67), .b(a68), .clk(clk), .q(t403)); + subfxp_18_1 sub89366(.a(a65), .b(a66), .clk(clk), .q(t404)); + subfxp_18_1 sub89381(.a(a67), .b(a68), .clk(clk), .q(t405)); + addfxp_18_1 add89396(.a(a73), .b(a74), .clk(clk), .q(t406)); + addfxp_18_1 add89411(.a(a75), .b(a76), .clk(clk), .q(t407)); + subfxp_18_1 sub89426(.a(a73), .b(a74), .clk(clk), .q(t408)); + subfxp_18_1 sub89441(.a(a75), .b(a76), .clk(clk), .q(t409)); + addfxp_18_1 add89544(.a(a81), .b(a82), .clk(clk), .q(t418)); + addfxp_18_1 add89559(.a(a83), .b(a84), .clk(clk), .q(t419)); + subfxp_18_1 sub89574(.a(a81), .b(a82), .clk(clk), .q(t420)); + subfxp_18_1 sub89589(.a(a83), .b(a84), .clk(clk), .q(t421)); + addfxp_18_1 add89604(.a(a89), .b(a90), .clk(clk), .q(t422)); + addfxp_18_1 add89619(.a(a91), .b(a92), .clk(clk), .q(t423)); + subfxp_18_1 sub89634(.a(a89), .b(a90), .clk(clk), .q(t424)); + subfxp_18_1 sub89649(.a(a91), .b(a92), .clk(clk), .q(t425)); + addfxp_18_1 add89752(.a(a97), .b(a98), .clk(clk), .q(t434)); + addfxp_18_1 add89767(.a(a99), .b(a100), .clk(clk), .q(t435)); + subfxp_18_1 sub89782(.a(a97), .b(a98), .clk(clk), .q(t436)); + subfxp_18_1 sub89797(.a(a99), .b(a100), .clk(clk), .q(t437)); + addfxp_18_1 add89812(.a(a105), .b(a106), .clk(clk), .q(t438)); + addfxp_18_1 add89827(.a(a107), .b(a108), .clk(clk), .q(t439)); + subfxp_18_1 sub89842(.a(a105), .b(a106), .clk(clk), .q(t440)); + subfxp_18_1 sub89857(.a(a107), .b(a108), .clk(clk), .q(t441)); + addfxp_18_1 add89960(.a(a113), .b(a114), .clk(clk), .q(t450)); + addfxp_18_1 add89975(.a(a115), .b(a116), .clk(clk), .q(t451)); + subfxp_18_1 sub89990(.a(a113), .b(a114), .clk(clk), .q(t452)); + subfxp_18_1 sub90005(.a(a115), .b(a116), .clk(clk), .q(t453)); + addfxp_18_1 add90020(.a(a121), .b(a122), .clk(clk), .q(t454)); + addfxp_18_1 add90035(.a(a123), .b(a124), .clk(clk), .q(t455)); + subfxp_18_1 sub90050(.a(a121), .b(a122), .clk(clk), .q(t456)); + subfxp_18_1 sub90065(.a(a123), .b(a124), .clk(clk), .q(t457)); + addfxp_18_1 add89448(.a(t402), .b(t406), .clk(clk), .q(t410)); + addfxp_18_1 add89455(.a(t403), .b(t407), .clk(clk), .q(t411)); + subfxp_18_1 sub89462(.a(t402), .b(t406), .clk(clk), .q(t412)); + subfxp_18_1 sub89469(.a(t403), .b(t407), .clk(clk), .q(t413)); + addfxp_18_1 add89492(.a(t404), .b(t409), .clk(clk), .q(t414)); + subfxp_18_1 sub89499(.a(t405), .b(t408), .clk(clk), .q(t415)); + subfxp_18_1 sub89506(.a(t404), .b(t409), .clk(clk), .q(t416)); + addfxp_18_1 add89513(.a(t405), .b(t408), .clk(clk), .q(t417)); + addfxp_18_1 add89656(.a(t418), .b(t422), .clk(clk), .q(t426)); + addfxp_18_1 add89663(.a(t419), .b(t423), .clk(clk), .q(t427)); + subfxp_18_1 sub89670(.a(t418), .b(t422), .clk(clk), .q(t428)); + subfxp_18_1 sub89677(.a(t419), .b(t423), .clk(clk), .q(t429)); + addfxp_18_1 add89700(.a(t420), .b(t425), .clk(clk), .q(t430)); + subfxp_18_1 sub89707(.a(t421), .b(t424), .clk(clk), .q(t431)); + subfxp_18_1 sub89714(.a(t420), .b(t425), .clk(clk), .q(t432)); + addfxp_18_1 add89721(.a(t421), .b(t424), .clk(clk), .q(t433)); + addfxp_18_1 add89864(.a(t434), .b(t438), .clk(clk), .q(t442)); + addfxp_18_1 add89871(.a(t435), .b(t439), .clk(clk), .q(t443)); + subfxp_18_1 sub89878(.a(t434), .b(t438), .clk(clk), .q(t444)); + subfxp_18_1 sub89885(.a(t435), .b(t439), .clk(clk), .q(t445)); + addfxp_18_1 add89908(.a(t436), .b(t441), .clk(clk), .q(t446)); + subfxp_18_1 sub89915(.a(t437), .b(t440), .clk(clk), .q(t447)); + subfxp_18_1 sub89922(.a(t436), .b(t441), .clk(clk), .q(t448)); + addfxp_18_1 add89929(.a(t437), .b(t440), .clk(clk), .q(t449)); + addfxp_18_1 add90072(.a(t450), .b(t454), .clk(clk), .q(t458)); + addfxp_18_1 add90079(.a(t451), .b(t455), .clk(clk), .q(t459)); + subfxp_18_1 sub90086(.a(t450), .b(t454), .clk(clk), .q(t460)); + subfxp_18_1 sub90093(.a(t451), .b(t455), .clk(clk), .q(t461)); + addfxp_18_1 add90116(.a(t452), .b(t457), .clk(clk), .q(t462)); + subfxp_18_1 sub90123(.a(t453), .b(t456), .clk(clk), .q(t463)); + subfxp_18_1 sub90130(.a(t452), .b(t457), .clk(clk), .q(t464)); + addfxp_18_1 add90137(.a(t453), .b(t456), .clk(clk), .q(t465)); + +always @(posedge clk) begin + if (reset == 1) begin + next <= 1'b0; + end else begin + X0 <= X0_in; + X1 <= X1_in; + X2 <= X2_in; + X3 <= X3_in; + X4 <= X4_in; + X5 <= X5_in; + X6 <= X6_in; + X7 <= X7_in; + X8 <= X8_in; + X9 <= X9_in; + X10 <= X10_in; + X11 <= X11_in; + X12 <= X12_in; + X13 <= X13_in; + X14 <= X14_in; + X15 <= X15_in; + X16 <= X16_in; + X17 <= X17_in; + X18 <= X18_in; + X19 <= X19_in; + X20 <= X20_in; + X21 <= X21_in; + X22 <= X22_in; + X23 <= X23_in; + X24 <= X24_in; + X25 <= X25_in; + X26 <= X26_in; + X27 <= X27_in; + X28 <= X28_in; + X29 <= X29_in; + X30 <= X30_in; + X31 <= X31_in; + next <= next_in; + end +end + +endmodule + +module shiftRegFIFO_2_1 ( + input [0:0] X, + output [0:0] Y, + input reset, + input clk +); + +reg [0:0] mem_0; +reg [0:0] mem_1; +reg [0:0] mem_2; +reg [0:0] mem_3; +reg [0:0] mem_4; +assign Y = mem_4; + +always @ (posedge clk) begin + if (reset) begin + mem_0 <= 0; + mem_1 <= 0; + mem_2 <= 0; + mem_3 <= 0; + mem_4 <= 0; + end else begin + mem_1 <= mem_0; + mem_2 <= mem_1; + mem_3 <= mem_2; + mem_4 <= mem_3; + mem_0 <= X; + end +end + +endmodule + +module elementwise_mult_core_18_1810_9_1 ( + input clk, + input reset, + input i_valid, + input i_ready, + input [17:0] i_A_0, + input [17:0] i_B_0, + output [17:0] o_C_0, + input [17:0] i_A_1, + input [17:0] i_B_1, + output [17:0] o_C_1, + input [17:0] i_A_2, + input [17:0] i_B_2, + output [17:0] o_C_2, + input [17:0] i_A_3, + input [17:0] i_B_3, + output [17:0] o_C_3, + input [17:0] i_A_4, + input [17:0] i_B_4, + output [17:0] o_C_4, + input [17:0] i_A_5, + input [17:0] i_B_5, + output [17:0] o_C_5, + input [17:0] i_A_6, + input [17:0] i_B_6, + output [17:0] o_C_6, + input [17:0] i_A_7, + input [17:0] i_B_7, + output [17:0] o_C_7, + input [17:0] i_A_8, + input [17:0] i_B_8, + output [17:0] o_C_8, + output o_valid, + output o_ready +); + +// Store inputs and outputs in registers +reg [17:0] reg_A_0; +reg [17:0] reg_B_0; +wire [17:0] reg_C_0; +reg [17:0] reg_A_1; +reg [17:0] reg_B_1; +wire [17:0] reg_C_1; +reg [17:0] reg_A_2; +reg [17:0] reg_B_2; +wire [17:0] reg_C_2; +reg [17:0] reg_A_3; +reg [17:0] reg_B_3; +wire [17:0] reg_C_3; +reg [17:0] reg_A_4; +reg [17:0] reg_B_4; +wire [17:0] reg_C_4; +reg [17:0] reg_A_5; +reg [17:0] reg_B_5; +wire [17:0] reg_C_5; +reg [17:0] reg_A_6; +reg [17:0] reg_B_6; +wire [17:0] reg_C_6; +reg [17:0] reg_A_7; +reg [17:0] reg_B_7; +wire [17:0] reg_C_7; +reg [17:0] reg_A_8; +reg [17:0] reg_B_8; +wire [17:0] reg_C_8; + +reg valid_A_B; +wire valid_C; +wire enable; +assign enable = i_ready; + +wire mult_valid_0; +wire round_valid_0; +wire [36:0] mult_C_0; +wire [36:0] rounded_C_0; +wire mult_valid_1; +wire round_valid_1; +wire [36:0] mult_C_1; +wire [36:0] rounded_C_1; +wire mult_valid_2; +wire round_valid_2; +wire [36:0] mult_C_2; +wire [36:0] rounded_C_2; +wire mult_valid_3; +wire round_valid_3; +wire [36:0] mult_C_3; +wire [36:0] rounded_C_3; +wire mult_valid_4; +wire round_valid_4; +wire [36:0] mult_C_4; +wire [36:0] rounded_C_4; +wire mult_valid_5; +wire round_valid_5; +wire [36:0] mult_C_5; +wire [36:0] rounded_C_5; +wire mult_valid_6; +wire round_valid_6; +wire [36:0] mult_C_6; +wire [36:0] rounded_C_6; +wire mult_valid_7; +wire round_valid_7; +wire [36:0] mult_C_7; +wire [36:0] rounded_C_7; +wire mult_valid_8; +wire round_valid_8; +wire [36:0] mult_C_8; +wire [36:0] rounded_C_8; + +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst0 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_0), + .ay(reg_B_0), + .bx(reg_A_1), + .by(reg_B_1), + .o_valid(mult_valid_0), + .resulta(mult_C_0), + .resultb(mult_C_1) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst2 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_2), + .ay(reg_B_2), + .bx(reg_A_3), + .by(reg_B_3), + .o_valid(mult_valid_2), + .resulta(mult_C_2), + .resultb(mult_C_3) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst4 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_4), + .ay(reg_B_4), + .bx(reg_A_5), + .by(reg_B_5), + .o_valid(mult_valid_4), + .resulta(mult_C_4), + .resultb(mult_C_5) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst6 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_6), + .ay(reg_B_6), + .bx(reg_A_7), + .by(reg_B_7), + .o_valid(mult_valid_6), + .resulta(mult_C_6), + .resultb(mult_C_7) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst8 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_8), + .ay(reg_B_8), + .bx(), + .by(), + .o_valid(mult_valid_8), + .resulta(mult_C_8), + .resultb() +); +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_0), + .in(mult_C_0), + .o_valid(round_valid_0), + .out(rounded_C_0) +); +assign reg_C_0 = rounded_C_0[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_1), + .in(mult_C_1), + .o_valid(round_valid_1), + .out(rounded_C_1) +); +assign reg_C_1 = rounded_C_1[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_2), + .in(mult_C_2), + .o_valid(round_valid_2), + .out(rounded_C_2) +); +assign reg_C_2 = rounded_C_2[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_3), + .in(mult_C_3), + .o_valid(round_valid_3), + .out(rounded_C_3) +); +assign reg_C_3 = rounded_C_3[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_4), + .in(mult_C_4), + .o_valid(round_valid_4), + .out(rounded_C_4) +); +assign reg_C_4 = rounded_C_4[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_5), + .in(mult_C_5), + .o_valid(round_valid_5), + .out(rounded_C_5) +); +assign reg_C_5 = rounded_C_5[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_6), + .in(mult_C_6), + .o_valid(round_valid_6), + .out(rounded_C_6) +); +assign reg_C_6 = rounded_C_6[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_7), + .in(mult_C_7), + .o_valid(round_valid_7), + .out(rounded_C_7) +); +assign reg_C_7 = rounded_C_7[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_8), + .in(mult_C_8), + .o_valid(round_valid_8), + .out(rounded_C_8) +); +assign reg_C_8 = rounded_C_8[17:0]; +always @ (posedge clk) begin + if (reset) begin + valid_A_B <= 1'b0; + reg_A_0 <= 0; + reg_B_0 <= 0; + reg_A_1 <= 0; + reg_B_1 <= 0; + reg_A_2 <= 0; + reg_B_2 <= 0; + reg_A_3 <= 0; + reg_B_3 <= 0; + reg_A_4 <= 0; + reg_B_4 <= 0; + reg_A_5 <= 0; + reg_B_5 <= 0; + reg_A_6 <= 0; + reg_B_6 <= 0; + reg_A_7 <= 0; + reg_B_7 <= 0; + reg_A_8 <= 0; + reg_B_8 <= 0; + end else if (enable) begin + reg_A_0 <= i_A_0; + reg_B_0 <= i_B_0; + reg_A_1 <= i_A_1; + reg_B_1 <= i_B_1; + reg_A_2 <= i_A_2; + reg_B_2 <= i_B_2; + reg_A_3 <= i_A_3; + reg_B_3 <= i_B_3; + reg_A_4 <= i_A_4; + reg_B_4 <= i_B_4; + reg_A_5 <= i_A_5; + reg_B_5 <= i_B_5; + reg_A_6 <= i_A_6; + reg_B_6 <= i_B_6; + reg_A_7 <= i_A_7; + reg_B_7 <= i_B_7; + reg_A_8 <= i_A_8; + reg_B_8 <= i_B_8; + valid_A_B <= i_valid; + end +end + +assign o_C_0 = reg_C_0; +assign o_C_1 = reg_C_1; +assign o_C_2 = reg_C_2; +assign o_C_3 = reg_C_3; +assign o_C_4 = reg_C_4; +assign o_C_5 = reg_C_5; +assign o_C_6 = reg_C_6; +assign o_C_7 = reg_C_7; +assign o_C_8 = reg_C_8; +assign valid_C = round_valid_0; +assign o_ready = i_ready; +assign o_valid = valid_C & i_ready; + +endmodule + +module dsp_signed_mult_18x18_unit_18_18_1 ( + input clk, + input reset, + input ena, + input i_valid, + input [17:0] ax, + input [17:0] ay, + input [17:0] bx, + input [17:0] by, + output o_valid, + output [36:0] resulta, + output [36:0] resultb +); + +reg [17:0] reg_ax, reg_ay, reg_bx, reg_by; +reg [36:0] reg_resa, reg_resb; +reg valid_r, valid_rr; +always @(posedge clk) begin + if (reset) begin + reg_ax <= 0; + reg_ay <= 0; + reg_bx <= 0; + reg_by <= 0; + reg_resa <= 0; + reg_resb <= 0; + valid_r <= 0; + valid_rr <= 0; + end else begin + reg_ax <= ax; + reg_ay <= ay; + reg_bx <= bx; + reg_by <= by; + reg_resa <= reg_ax * reg_ay; + reg_resb <= reg_bx * reg_by; + valid_r <= ena; + valid_rr <= valid_r; + end +end + +assign resulta = reg_resa; +assign resultb = reg_resb; +assign o_valid = valid_rr; +endmodule + +module fp_rounding_unit_1_37_10 ( + input clk, + input reset, + input enable, + input i_valid, + input [36:0] in, + output [36:0] out, + output o_valid +); + +reg [36:0] rounded_result; +reg [36:0] floor; +reg [36:0] ceil; +reg is_ceil; +reg floor_ceil_valid; + +always @ (*) begin + if (is_ceil) begin + rounded_result = ceil; + end else begin + rounded_result = floor; + end +end + +reg valid_reg; +reg [36:0] out_reg; +always @ (posedge clk) begin + if (reset) begin + is_ceil <= 1'b0; + floor_ceil_valid <= 1'b0; + valid_reg <= 1'b0; + floor <= 0; + ceil <= 0; + out_reg <= 0; + end else if (enable) begin + is_ceil <= in[9]; + floor <= in >>> 10; + ceil <= (in >>> 10) + 1; + floor_ceil_valid <= i_valid; + out_reg <= rounded_result; + valid_reg <= floor_ceil_valid; + end +end + +assign o_valid = valid_reg; + +assign out = out_reg; + +endmodule + +module elementwise_sub_core_18_18_9 ( + input clk, + input reset, + input i_valid, + input i_ready, + input [17:0] i_A_0, + input [17:0] i_B_0, + output [17:0] o_C_0, + input [17:0] i_A_1, + input [17:0] i_B_1, + output [17:0] o_C_1, + input [17:0] i_A_2, + input [17:0] i_B_2, + output [17:0] o_C_2, + input [17:0] i_A_3, + input [17:0] i_B_3, + output [17:0] o_C_3, + input [17:0] i_A_4, + input [17:0] i_B_4, + output [17:0] o_C_4, + input [17:0] i_A_5, + input [17:0] i_B_5, + output [17:0] o_C_5, + input [17:0] i_A_6, + input [17:0] i_B_6, + output [17:0] o_C_6, + input [17:0] i_A_7, + input [17:0] i_B_7, + output [17:0] o_C_7, + input [17:0] i_A_8, + input [17:0] i_B_8, + output [17:0] o_C_8, + output o_valid, + output o_ready +); + +reg [17:0] reg_A_0; +reg [17:0] reg_B_0; +reg [17:0] reg_C_0; +reg [17:0] reg_A_1; +reg [17:0] reg_B_1; +reg [17:0] reg_C_1; +reg [17:0] reg_A_2; +reg [17:0] reg_B_2; +reg [17:0] reg_C_2; +reg [17:0] reg_A_3; +reg [17:0] reg_B_3; +reg [17:0] reg_C_3; +reg [17:0] reg_A_4; +reg [17:0] reg_B_4; +reg [17:0] reg_C_4; +reg [17:0] reg_A_5; +reg [17:0] reg_B_5; +reg [17:0] reg_C_5; +reg [17:0] reg_A_6; +reg [17:0] reg_B_6; +reg [17:0] reg_C_6; +reg [17:0] reg_A_7; +reg [17:0] reg_B_7; +reg [17:0] reg_C_7; +reg [17:0] reg_A_8; +reg [17:0] reg_B_8; +reg [17:0] reg_C_8; + +reg valid_A_B, valid_C; +wire enable; +assign enable = i_ready; + +always @ (posedge clk) begin + if (reset) begin + valid_A_B <= 1'b0; + valid_C <= 1'b0; + reg_A_0 <= 0; + reg_B_0 <= 0; + reg_C_0 <= 0; + reg_A_1 <= 0; + reg_B_1 <= 0; + reg_C_1 <= 0; + reg_A_2 <= 0; + reg_B_2 <= 0; + reg_C_2 <= 0; + reg_A_3 <= 0; + reg_B_3 <= 0; + reg_C_3 <= 0; + reg_A_4 <= 0; + reg_B_4 <= 0; + reg_C_4 <= 0; + reg_A_5 <= 0; + reg_B_5 <= 0; + reg_C_5 <= 0; + reg_A_6 <= 0; + reg_B_6 <= 0; + reg_C_6 <= 0; + reg_A_7 <= 0; + reg_B_7 <= 0; + reg_C_7 <= 0; + reg_A_8 <= 0; + reg_B_8 <= 0; + reg_C_8 <= 0; + end else if (enable) begin + reg_A_0 <= i_A_0; + reg_B_0 <= i_B_0; + reg_C_0 <= reg_A_0 - reg_B_0; + reg_A_1 <= i_A_1; + reg_B_1 <= i_B_1; + reg_C_1 <= reg_A_1 - reg_B_1; + reg_A_2 <= i_A_2; + reg_B_2 <= i_B_2; + reg_C_2 <= reg_A_2 - reg_B_2; + reg_A_3 <= i_A_3; + reg_B_3 <= i_B_3; + reg_C_3 <= reg_A_3 - reg_B_3; + reg_A_4 <= i_A_4; + reg_B_4 <= i_B_4; + reg_C_4 <= reg_A_4 - reg_B_4; + reg_A_5 <= i_A_5; + reg_B_5 <= i_B_5; + reg_C_5 <= reg_A_5 - reg_B_5; + reg_A_6 <= i_A_6; + reg_B_6 <= i_B_6; + reg_C_6 <= reg_A_6 - reg_B_6; + reg_A_7 <= i_A_7; + reg_B_7 <= i_B_7; + reg_C_7 <= reg_A_7 - reg_B_7; + reg_A_8 <= i_A_8; + reg_B_8 <= i_B_8; + reg_C_8 <= reg_A_8 - reg_B_8; + valid_A_B <= i_valid; + valid_C <= valid_A_B; + end +end + +assign o_C_0 = reg_C_0; +assign o_C_1 = reg_C_1; +assign o_C_2 = reg_C_2; +assign o_C_3 = reg_C_3; +assign o_C_4 = reg_C_4; +assign o_C_5 = reg_C_5; +assign o_C_6 = reg_C_6; +assign o_C_7 = reg_C_7; +assign o_C_8 = reg_C_8; +assign o_ready = i_ready; +assign o_valid = valid_C & i_ready; + +endmodule + +module elementwise_add_core_18_18_9 ( + input clk, + input reset, + input i_valid, + input i_ready, + input [17:0] i_A_0, + input [17:0] i_B_0, + output [17:0] o_C_0, + input [17:0] i_A_1, + input [17:0] i_B_1, + output [17:0] o_C_1, + input [17:0] i_A_2, + input [17:0] i_B_2, + output [17:0] o_C_2, + input [17:0] i_A_3, + input [17:0] i_B_3, + output [17:0] o_C_3, + input [17:0] i_A_4, + input [17:0] i_B_4, + output [17:0] o_C_4, + input [17:0] i_A_5, + input [17:0] i_B_5, + output [17:0] o_C_5, + input [17:0] i_A_6, + input [17:0] i_B_6, + output [17:0] o_C_6, + input [17:0] i_A_7, + input [17:0] i_B_7, + output [17:0] o_C_7, + input [17:0] i_A_8, + input [17:0] i_B_8, + output [17:0] o_C_8, + output o_valid, + output o_ready +); + +reg [17:0] reg_A_0; +reg [17:0] reg_B_0; +reg [17:0] reg_C_0; +reg [17:0] reg_A_1; +reg [17:0] reg_B_1; +reg [17:0] reg_C_1; +reg [17:0] reg_A_2; +reg [17:0] reg_B_2; +reg [17:0] reg_C_2; +reg [17:0] reg_A_3; +reg [17:0] reg_B_3; +reg [17:0] reg_C_3; +reg [17:0] reg_A_4; +reg [17:0] reg_B_4; +reg [17:0] reg_C_4; +reg [17:0] reg_A_5; +reg [17:0] reg_B_5; +reg [17:0] reg_C_5; +reg [17:0] reg_A_6; +reg [17:0] reg_B_6; +reg [17:0] reg_C_6; +reg [17:0] reg_A_7; +reg [17:0] reg_B_7; +reg [17:0] reg_C_7; +reg [17:0] reg_A_8; +reg [17:0] reg_B_8; +reg [17:0] reg_C_8; + +reg valid_A_B, valid_C; +wire enable; +assign enable = i_ready; + +always @ (posedge clk) begin + if (reset) begin + valid_A_B <= 1'b0; + valid_C <= 1'b0; + reg_A_0 <= 0; + reg_B_0 <= 0; + reg_C_0 <= 0; + reg_A_1 <= 0; + reg_B_1 <= 0; + reg_C_1 <= 0; + reg_A_2 <= 0; + reg_B_2 <= 0; + reg_C_2 <= 0; + reg_A_3 <= 0; + reg_B_3 <= 0; + reg_C_3 <= 0; + reg_A_4 <= 0; + reg_B_4 <= 0; + reg_C_4 <= 0; + reg_A_5 <= 0; + reg_B_5 <= 0; + reg_C_5 <= 0; + reg_A_6 <= 0; + reg_B_6 <= 0; + reg_C_6 <= 0; + reg_A_7 <= 0; + reg_B_7 <= 0; + reg_C_7 <= 0; + reg_A_8 <= 0; + reg_B_8 <= 0; + reg_C_8 <= 0; + end else if (enable) begin + reg_A_0 <= i_A_0; + reg_B_0 <= i_B_0; + reg_C_0 <= reg_A_0 + reg_B_0; + reg_A_1 <= i_A_1; + reg_B_1 <= i_B_1; + reg_C_1 <= reg_A_1 + reg_B_1; + reg_A_2 <= i_A_2; + reg_B_2 <= i_B_2; + reg_C_2 <= reg_A_2 + reg_B_2; + reg_A_3 <= i_A_3; + reg_B_3 <= i_B_3; + reg_C_3 <= reg_A_3 + reg_B_3; + reg_A_4 <= i_A_4; + reg_B_4 <= i_B_4; + reg_C_4 <= reg_A_4 + reg_B_4; + reg_A_5 <= i_A_5; + reg_B_5 <= i_B_5; + reg_C_5 <= reg_A_5 + reg_B_5; + reg_A_6 <= i_A_6; + reg_B_6 <= i_B_6; + reg_C_6 <= reg_A_6 + reg_B_6; + reg_A_7 <= i_A_7; + reg_B_7 <= i_B_7; + reg_C_7 <= reg_A_7 + reg_B_7; + reg_A_8 <= i_A_8; + reg_B_8 <= i_B_8; + reg_C_8 <= reg_A_8 + reg_B_8; + valid_A_B <= i_valid; + valid_C <= valid_A_B; + end +end + +assign o_C_0 = reg_C_0; +assign o_C_1 = reg_C_1; +assign o_C_2 = reg_C_2; +assign o_C_3 = reg_C_3; +assign o_C_4 = reg_C_4; +assign o_C_5 = reg_C_5; +assign o_C_6 = reg_C_6; +assign o_C_7 = reg_C_7; +assign o_C_8 = reg_C_8; +assign o_ready = i_ready; +assign o_valid = valid_C & i_ready; + +endmodule + +module sum_complex_vector_unit_18_18_16_42 ( + input clk, + input clr, + input i_valid, + input enable, + input [17:0] i_real_0, + input [17:0] i_imag_0, + output [17:0] o_real_0, + output [17:0] o_imag_0, + input [17:0] i_real_1, + input [17:0] i_imag_1, + output [17:0] o_real_1, + output [17:0] o_imag_1, + input [17:0] i_real_2, + input [17:0] i_imag_2, + output [17:0] o_real_2, + output [17:0] o_imag_2, + input [17:0] i_real_3, + input [17:0] i_imag_3, + output [17:0] o_real_3, + output [17:0] o_imag_3, + input [17:0] i_real_4, + input [17:0] i_imag_4, + output [17:0] o_real_4, + output [17:0] o_imag_4, + input [17:0] i_real_5, + input [17:0] i_imag_5, + output [17:0] o_real_5, + output [17:0] o_imag_5, + input [17:0] i_real_6, + input [17:0] i_imag_6, + output [17:0] o_real_6, + output [17:0] o_imag_6, + input [17:0] i_real_7, + input [17:0] i_imag_7, + output [17:0] o_real_7, + output [17:0] o_imag_7, + input [17:0] i_real_8, + input [17:0] i_imag_8, + output [17:0] o_real_8, + output [17:0] o_imag_8, + input [17:0] i_real_9, + input [17:0] i_imag_9, + output [17:0] o_real_9, + output [17:0] o_imag_9, + input [17:0] i_real_10, + input [17:0] i_imag_10, + output [17:0] o_real_10, + output [17:0] o_imag_10, + input [17:0] i_real_11, + input [17:0] i_imag_11, + output [17:0] o_real_11, + output [17:0] o_imag_11, + input [17:0] i_real_12, + input [17:0] i_imag_12, + output [17:0] o_real_12, + output [17:0] o_imag_12, + input [17:0] i_real_13, + input [17:0] i_imag_13, + output [17:0] o_real_13, + output [17:0] o_imag_13, + input [17:0] i_real_14, + input [17:0] i_imag_14, + output [17:0] o_real_14, + output [17:0] o_imag_14, + input [17:0] i_real_15, + input [17:0] i_imag_15, + output [17:0] o_real_15, + output [17:0] o_imag_15, + output o_valid +); + +reg [17:0] sum_real_0; +reg [17:0] sum_imag_0; +reg [17:0] sum_real_1; +reg [17:0] sum_imag_1; +reg [17:0] sum_real_2; +reg [17:0] sum_imag_2; +reg [17:0] sum_real_3; +reg [17:0] sum_imag_3; +reg [17:0] sum_real_4; +reg [17:0] sum_imag_4; +reg [17:0] sum_real_5; +reg [17:0] sum_imag_5; +reg [17:0] sum_real_6; +reg [17:0] sum_imag_6; +reg [17:0] sum_real_7; +reg [17:0] sum_imag_7; +reg [17:0] sum_real_8; +reg [17:0] sum_imag_8; +reg [17:0] sum_real_9; +reg [17:0] sum_imag_9; +reg [17:0] sum_real_10; +reg [17:0] sum_imag_10; +reg [17:0] sum_real_11; +reg [17:0] sum_imag_11; +reg [17:0] sum_real_12; +reg [17:0] sum_imag_12; +reg [17:0] sum_real_13; +reg [17:0] sum_imag_13; +reg [17:0] sum_real_14; +reg [17:0] sum_imag_14; +reg [17:0] sum_real_15; +reg [17:0] sum_imag_15; +reg reg_i_valid; + +// Count the number data in accumulation +reg [13:0] counter; +wire counter_full; +always @ (posedge clk) begin + if (clr) begin + sum_real_0 <= 0; + sum_imag_0 <= 0; + sum_real_1 <= 0; + sum_imag_1 <= 0; + sum_real_2 <= 0; + sum_imag_2 <= 0; + sum_real_3 <= 0; + sum_imag_3 <= 0; + sum_real_4 <= 0; + sum_imag_4 <= 0; + sum_real_5 <= 0; + sum_imag_5 <= 0; + sum_real_6 <= 0; + sum_imag_6 <= 0; + sum_real_7 <= 0; + sum_imag_7 <= 0; + sum_real_8 <= 0; + sum_imag_8 <= 0; + sum_real_9 <= 0; + sum_imag_9 <= 0; + sum_real_10 <= 0; + sum_imag_10 <= 0; + sum_real_11 <= 0; + sum_imag_11 <= 0; + sum_real_12 <= 0; + sum_imag_12 <= 0; + sum_real_13 <= 0; + sum_imag_13 <= 0; + sum_real_14 <= 0; + sum_imag_14 <= 0; + sum_real_15 <= 0; + sum_imag_15 <= 0; + counter <= 14'd0; + reg_i_valid <= 1'b0; + end else if (enable) begin + reg_i_valid <= i_valid; + // Accumulate the number only when data is valid + if (i_valid) begin + if (counter == 42) + counter <= 1; + else + counter <= counter + 1'b1; + + if (counter == 42) begin + sum_real_0 <= i_real_0; + sum_imag_0 <= i_imag_0; + sum_real_1 <= i_real_1; + sum_imag_1 <= i_imag_1; + sum_real_2 <= i_real_2; + sum_imag_2 <= i_imag_2; + sum_real_3 <= i_real_3; + sum_imag_3 <= i_imag_3; + sum_real_4 <= i_real_4; + sum_imag_4 <= i_imag_4; + sum_real_5 <= i_real_5; + sum_imag_5 <= i_imag_5; + sum_real_6 <= i_real_6; + sum_imag_6 <= i_imag_6; + sum_real_7 <= i_real_7; + sum_imag_7 <= i_imag_7; + sum_real_8 <= i_real_8; + sum_imag_8 <= i_imag_8; + sum_real_9 <= i_real_9; + sum_imag_9 <= i_imag_9; + sum_real_10 <= i_real_10; + sum_imag_10 <= i_imag_10; + sum_real_11 <= i_real_11; + sum_imag_11 <= i_imag_11; + sum_real_12 <= i_real_12; + sum_imag_12 <= i_imag_12; + sum_real_13 <= i_real_13; + sum_imag_13 <= i_imag_13; + sum_real_14 <= i_real_14; + sum_imag_14 <= i_imag_14; + sum_real_15 <= i_real_15; + sum_imag_15 <= i_imag_15; + end else begin + sum_real_0 <= sum_real_0 + i_real_0; + sum_imag_0 <= sum_imag_0 + i_imag_0; + sum_real_1 <= sum_real_1 + i_real_1; + sum_imag_1 <= sum_imag_1 + i_imag_1; + sum_real_2 <= sum_real_2 + i_real_2; + sum_imag_2 <= sum_imag_2 + i_imag_2; + sum_real_3 <= sum_real_3 + i_real_3; + sum_imag_3 <= sum_imag_3 + i_imag_3; + sum_real_4 <= sum_real_4 + i_real_4; + sum_imag_4 <= sum_imag_4 + i_imag_4; + sum_real_5 <= sum_real_5 + i_real_5; + sum_imag_5 <= sum_imag_5 + i_imag_5; + sum_real_6 <= sum_real_6 + i_real_6; + sum_imag_6 <= sum_imag_6 + i_imag_6; + sum_real_7 <= sum_real_7 + i_real_7; + sum_imag_7 <= sum_imag_7 + i_imag_7; + sum_real_8 <= sum_real_8 + i_real_8; + sum_imag_8 <= sum_imag_8 + i_imag_8; + sum_real_9 <= sum_real_9 + i_real_9; + sum_imag_9 <= sum_imag_9 + i_imag_9; + sum_real_10 <= sum_real_10 + i_real_10; + sum_imag_10 <= sum_imag_10 + i_imag_10; + sum_real_11 <= sum_real_11 + i_real_11; + sum_imag_11 <= sum_imag_11 + i_imag_11; + sum_real_12 <= sum_real_12 + i_real_12; + sum_imag_12 <= sum_imag_12 + i_imag_12; + sum_real_13 <= sum_real_13 + i_real_13; + sum_imag_13 <= sum_imag_13 + i_imag_13; + sum_real_14 <= sum_real_14 + i_real_14; + sum_imag_14 <= sum_imag_14 + i_imag_14; + sum_real_15 <= sum_real_15 + i_real_15; + sum_imag_15 <= sum_imag_15 + i_imag_15; + end + end + end +end + +assign counter_full = (counter == 42); +assign o_real_0 = sum_real_0; +assign o_imag_0 = sum_imag_0; +assign o_real_1 = sum_real_1; +assign o_imag_1 = sum_imag_1; +assign o_real_2 = sum_real_2; +assign o_imag_2 = sum_imag_2; +assign o_real_3 = sum_real_3; +assign o_imag_3 = sum_imag_3; +assign o_real_4 = sum_real_4; +assign o_imag_4 = sum_imag_4; +assign o_real_5 = sum_real_5; +assign o_imag_5 = sum_imag_5; +assign o_real_6 = sum_real_6; +assign o_imag_6 = sum_imag_6; +assign o_real_7 = sum_real_7; +assign o_imag_7 = sum_imag_7; +assign o_real_8 = sum_real_8; +assign o_imag_8 = sum_imag_8; +assign o_real_9 = sum_real_9; +assign o_imag_9 = sum_imag_9; +assign o_real_10 = sum_real_10; +assign o_imag_10 = sum_imag_10; +assign o_real_11 = sum_real_11; +assign o_imag_11 = sum_imag_11; +assign o_real_12 = sum_real_12; +assign o_imag_12 = sum_imag_12; +assign o_real_13 = sum_real_13; +assign o_imag_13 = sum_imag_13; +assign o_real_14 = sum_real_14; +assign o_imag_14 = sum_imag_14; +assign o_real_15 = sum_real_15; +assign o_imag_15 = sum_imag_15; +assign o_valid = counter_full & reg_i_valid; + +endmodule + +module shift_register_group_18_16_1 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input reset +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_1 shift_register_unit_18_1_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +endmodule + +module shift_register_unit_18_1 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + end +end + +assign out = shift_registers_0; + +endmodule + +module idft_16_top_18 ( + input clk, + input reset, + input next, + input [17:0] X0, + output [17:0] Y0, + input [17:0] X1, + output [17:0] Y1, + input [17:0] X2, + output [17:0] Y2, + input [17:0] X3, + output [17:0] Y3, + input [17:0] X4, + output [17:0] Y4, + input [17:0] X5, + output [17:0] Y5, + input [17:0] X6, + output [17:0] Y6, + input [17:0] X7, + output [17:0] Y7, + input [17:0] X8, + output [17:0] Y8, + input [17:0] X9, + output [17:0] Y9, + input [17:0] X10, + output [17:0] Y10, + input [17:0] X11, + output [17:0] Y11, + input [17:0] X12, + output [17:0] Y12, + input [17:0] X13, + output [17:0] Y13, + input [17:0] X14, + output [17:0] Y14, + input [17:0] X15, + output [17:0] Y15, + input [17:0] X16, + output [17:0] Y16, + input [17:0] X17, + output [17:0] Y17, + input [17:0] X18, + output [17:0] Y18, + input [17:0] X19, + output [17:0] Y19, + input [17:0] X20, + output [17:0] Y20, + input [17:0] X21, + output [17:0] Y21, + input [17:0] X22, + output [17:0] Y22, + input [17:0] X23, + output [17:0] Y23, + input [17:0] X24, + output [17:0] Y24, + input [17:0] X25, + output [17:0] Y25, + input [17:0] X26, + output [17:0] Y26, + input [17:0] X27, + output [17:0] Y27, + input [17:0] X28, + output [17:0] Y28, + input [17:0] X29, + output [17:0] Y29, + input [17:0] X30, + output [17:0] Y30, + input [17:0] X31, + output [17:0] Y31, + output next_out +); +wire [17:0] t0_0; +wire [17:0] t0_1; +wire [17:0] t0_2; +wire [17:0] t0_3; +wire [17:0] t0_4; +wire [17:0] t0_5; +wire [17:0] t0_6; +wire [17:0] t0_7; +wire [17:0] t0_8; +wire [17:0] t0_9; +wire [17:0] t0_10; +wire [17:0] t0_11; +wire [17:0] t0_12; +wire [17:0] t0_13; +wire [17:0] t0_14; +wire [17:0] t0_15; +wire [17:0] t0_16; +wire [17:0] t0_17; +wire [17:0] t0_18; +wire [17:0] t0_19; +wire [17:0] t0_20; +wire [17:0] t0_21; +wire [17:0] t0_22; +wire [17:0] t0_23; +wire [17:0] t0_24; +wire [17:0] t0_25; +wire [17:0] t0_26; +wire [17:0] t0_27; +wire [17:0] t0_28; +wire [17:0] t0_29; +wire [17:0] t0_30; +wire [17:0] t0_31; +wire next_0; +wire [17:0] t1_0; +wire [17:0] t1_1; +wire [17:0] t1_2; +wire [17:0] t1_3; +wire [17:0] t1_4; +wire [17:0] t1_5; +wire [17:0] t1_6; +wire [17:0] t1_7; +wire [17:0] t1_8; +wire [17:0] t1_9; +wire [17:0] t1_10; +wire [17:0] t1_11; +wire [17:0] t1_12; +wire [17:0] t1_13; +wire [17:0] t1_14; +wire [17:0] t1_15; +wire [17:0] t1_16; +wire [17:0] t1_17; +wire [17:0] t1_18; +wire [17:0] t1_19; +wire [17:0] t1_20; +wire [17:0] t1_21; +wire [17:0] t1_22; +wire [17:0] t1_23; +wire [17:0] t1_24; +wire [17:0] t1_25; +wire [17:0] t1_26; +wire [17:0] t1_27; +wire [17:0] t1_28; +wire [17:0] t1_29; +wire [17:0] t1_30; +wire [17:0] t1_31; +wire next_1; +wire [17:0] t2_0; +wire [17:0] t2_1; +wire [17:0] t2_2; +wire [17:0] t2_3; +wire [17:0] t2_4; +wire [17:0] t2_5; +wire [17:0] t2_6; +wire [17:0] t2_7; +wire [17:0] t2_8; +wire [17:0] t2_9; +wire [17:0] t2_10; +wire [17:0] t2_11; +wire [17:0] t2_12; +wire [17:0] t2_13; +wire [17:0] t2_14; +wire [17:0] t2_15; +wire [17:0] t2_16; +wire [17:0] t2_17; +wire [17:0] t2_18; +wire [17:0] t2_19; +wire [17:0] t2_20; +wire [17:0] t2_21; +wire [17:0] t2_22; +wire [17:0] t2_23; +wire [17:0] t2_24; +wire [17:0] t2_25; +wire [17:0] t2_26; +wire [17:0] t2_27; +wire [17:0] t2_28; +wire [17:0] t2_29; +wire [17:0] t2_30; +wire [17:0] t2_31; +wire next_2; + +assign t0_0 = X0; +assign Y0 = t2_0; +assign t0_1 = X1; +assign Y1 = t2_1; +assign t0_2 = X2; +assign Y2 = t2_2; +assign t0_3 = X3; +assign Y3 = t2_3; +assign t0_4 = X4; +assign Y4 = t2_4; +assign t0_5 = X5; +assign Y5 = t2_5; +assign t0_6 = X6; +assign Y6 = t2_6; +assign t0_7 = X7; +assign Y7 = t2_7; +assign t0_8 = X8; +assign Y8 = t2_8; +assign t0_9 = X9; +assign Y9 = t2_9; +assign t0_10 = X10; +assign Y10 = t2_10; +assign t0_11 = X11; +assign Y11 = t2_11; +assign t0_12 = X12; +assign Y12 = t2_12; +assign t0_13 = X13; +assign Y13 = t2_13; +assign t0_14 = X14; +assign Y14 = t2_14; +assign t0_15 = X15; +assign Y15 = t2_15; +assign t0_16 = X16; +assign Y16 = t2_16; +assign t0_17 = X17; +assign Y17 = t2_17; +assign t0_18 = X18; +assign Y18 = t2_18; +assign t0_19 = X19; +assign Y19 = t2_19; +assign t0_20 = X20; +assign Y20 = t2_20; +assign t0_21 = X21; +assign Y21 = t2_21; +assign t0_22 = X22; +assign Y22 = t2_22; +assign t0_23 = X23; +assign Y23 = t2_23; +assign t0_24 = X24; +assign Y24 = t2_24; +assign t0_25 = X25; +assign Y25 = t2_25; +assign t0_26 = X26; +assign Y26 = t2_26; +assign t0_27 = X27; +assign Y27 = t2_27; +assign t0_28 = X28; +assign Y28 = t2_28; +assign t0_29 = X29; +assign Y29 = t2_29; +assign t0_30 = X30; +assign Y30 = t2_30; +assign t0_31 = X31; +assign Y31 = t2_31; +assign next_0 = next; +assign next_out = next_2; +codeBlock98050_18 codeBlock98050_18_inst_apzkvgqore ( + .clk(clk), + .reset(reset), + .next_in(next_0), + .X0_in(t0_0), + .Y0(t1_0), + .X1_in(t0_1), + .Y1(t1_1), + .X2_in(t0_2), + .Y2(t1_2), + .X3_in(t0_3), + .Y3(t1_3), + .X4_in(t0_4), + .Y4(t1_4), + .X5_in(t0_5), + .Y5(t1_5), + .X6_in(t0_6), + .Y6(t1_6), + .X7_in(t0_7), + .Y7(t1_7), + .X8_in(t0_8), + .Y8(t1_8), + .X9_in(t0_9), + .Y9(t1_9), + .X10_in(t0_10), + .Y10(t1_10), + .X11_in(t0_11), + .Y11(t1_11), + .X12_in(t0_12), + .Y12(t1_12), + .X13_in(t0_13), + .Y13(t1_13), + .X14_in(t0_14), + .Y14(t1_14), + .X15_in(t0_15), + .Y15(t1_15), + .X16_in(t0_16), + .Y16(t1_16), + .X17_in(t0_17), + .Y17(t1_17), + .X18_in(t0_18), + .Y18(t1_18), + .X19_in(t0_19), + .Y19(t1_19), + .X20_in(t0_20), + .Y20(t1_20), + .X21_in(t0_21), + .Y21(t1_21), + .X22_in(t0_22), + .Y22(t1_22), + .X23_in(t0_23), + .Y23(t1_23), + .X24_in(t0_24), + .Y24(t1_24), + .X25_in(t0_25), + .Y25(t1_25), + .X26_in(t0_26), + .Y26(t1_26), + .X27_in(t0_27), + .Y27(t1_27), + .X28_in(t0_28), + .Y28(t1_28), + .X29_in(t0_29), + .Y29(t1_29), + .X30_in(t0_30), + .Y30(t1_30), + .X31_in(t0_31), + .Y31(t1_31), + .next_out(next_1) +); + +codeBlock99168_18 codeBlock99168_18_inst_icjzgvrntd ( + .clk(clk), + .reset(reset), + .next_in(next_1), + .X0_in(t1_0), + .Y0(t2_0), + .X1_in(t1_1), + .Y1(t2_1), + .X2_in(t1_2), + .Y2(t2_2), + .X3_in(t1_3), + .Y3(t2_3), + .X4_in(t1_4), + .Y4(t2_4), + .X5_in(t1_5), + .Y5(t2_5), + .X6_in(t1_6), + .Y6(t2_6), + .X7_in(t1_7), + .Y7(t2_7), + .X8_in(t1_8), + .Y8(t2_8), + .X9_in(t1_9), + .Y9(t2_9), + .X10_in(t1_10), + .Y10(t2_10), + .X11_in(t1_11), + .Y11(t2_11), + .X12_in(t1_12), + .Y12(t2_12), + .X13_in(t1_13), + .Y13(t2_13), + .X14_in(t1_14), + .Y14(t2_14), + .X15_in(t1_15), + .Y15(t2_15), + .X16_in(t1_16), + .Y16(t2_16), + .X17_in(t1_17), + .Y17(t2_17), + .X18_in(t1_18), + .Y18(t2_18), + .X19_in(t1_19), + .Y19(t2_19), + .X20_in(t1_20), + .Y20(t2_20), + .X21_in(t1_21), + .Y21(t2_21), + .X22_in(t1_22), + .Y22(t2_22), + .X23_in(t1_23), + .Y23(t2_23), + .X24_in(t1_24), + .Y24(t2_24), + .X25_in(t1_25), + .Y25(t2_25), + .X26_in(t1_26), + .Y26(t2_26), + .X27_in(t1_27), + .Y27(t2_27), + .X28_in(t1_28), + .Y28(t2_28), + .X29_in(t1_29), + .Y29(t2_29), + .X30_in(t1_30), + .Y30(t2_30), + .X31_in(t1_31), + .Y31(t2_31), + .next_out(next_2) +); + +endmodule + +module codeBlock98050_18 ( + input clk, + input reset, + input next_in, + input [17:0] X0_in, + output [17:0] Y0, + input [17:0] X1_in, + output [17:0] Y1, + input [17:0] X2_in, + output [17:0] Y2, + input [17:0] X3_in, + output [17:0] Y3, + input [17:0] X4_in, + output [17:0] Y4, + input [17:0] X5_in, + output [17:0] Y5, + input [17:0] X6_in, + output [17:0] Y6, + input [17:0] X7_in, + output [17:0] Y7, + input [17:0] X8_in, + output [17:0] Y8, + input [17:0] X9_in, + output [17:0] Y9, + input [17:0] X10_in, + output [17:0] Y10, + input [17:0] X11_in, + output [17:0] Y11, + input [17:0] X12_in, + output [17:0] Y12, + input [17:0] X13_in, + output [17:0] Y13, + input [17:0] X14_in, + output [17:0] Y14, + input [17:0] X15_in, + output [17:0] Y15, + input [17:0] X16_in, + output [17:0] Y16, + input [17:0] X17_in, + output [17:0] Y17, + input [17:0] X18_in, + output [17:0] Y18, + input [17:0] X19_in, + output [17:0] Y19, + input [17:0] X20_in, + output [17:0] Y20, + input [17:0] X21_in, + output [17:0] Y21, + input [17:0] X22_in, + output [17:0] Y22, + input [17:0] X23_in, + output [17:0] Y23, + input [17:0] X24_in, + output [17:0] Y24, + input [17:0] X25_in, + output [17:0] Y25, + input [17:0] X26_in, + output [17:0] Y26, + input [17:0] X27_in, + output [17:0] Y27, + input [17:0] X28_in, + output [17:0] Y28, + input [17:0] X29_in, + output [17:0] Y29, + input [17:0] X30_in, + output [17:0] Y30, + input [17:0] X31_in, + output [17:0] Y31, + output next_out +); + +reg next; +reg [17:0] X0; +reg [17:0] X1; +reg [17:0] X2; +reg [17:0] X3; +reg [17:0] X4; +reg [17:0] X5; +reg [17:0] X6; +reg [17:0] X7; +reg [17:0] X8; +reg [17:0] X9; +reg [17:0] X10; +reg [17:0] X11; +reg [17:0] X12; +reg [17:0] X13; +reg [17:0] X14; +reg [17:0] X15; +reg [17:0] X16; +reg [17:0] X17; +reg [17:0] X18; +reg [17:0] X19; +reg [17:0] X20; +reg [17:0] X21; +reg [17:0] X22; +reg [17:0] X23; +reg [17:0] X24; +reg [17:0] X25; +reg [17:0] X26; +reg [17:0] X27; +reg [17:0] X28; +reg [17:0] X29; +reg [17:0] X30; +reg [17:0] X31; +shiftRegFIFO_5_1 shiftRegFIFO_5_1_inst_hoctnqxblx ( + .X(next), + .Y(next_out), + .reset(reset), + .clk(clk) +); +wire [17:0] a249; + wire [17:0] a250; + wire [17:0] a251; + wire [17:0] a252; + wire [17:0] a257; + wire [17:0] a258; + wire [17:0] a259; + wire [17:0] a260; + wire [17:0] a265; + wire [17:0] a266; + wire [17:0] a267; + wire [17:0] a268; + wire [17:0] a273; + wire [17:0] a274; + wire [17:0] a275; + wire [17:0] a276; + wire [17:0] a281; + wire [17:0] a282; + wire [17:0] a283; + wire [17:0] a284; + wire [17:0] a289; + wire [17:0] a290; + wire [17:0] a291; + wire [17:0] a292; + wire [17:0] a297; + wire [17:0] a298; + wire [17:0] a299; + wire [17:0] a300; + wire [17:0] a305; + wire [17:0] a306; + wire [17:0] a307; + wire [17:0] a308; + wire [17:0] t914; + wire [17:0] t915; + wire [17:0] t916; + wire [17:0] t917; + wire [17:0] t918; + wire [17:0] t919; + wire [17:0] t920; + wire [17:0] t921; + wire [17:0] t930; + wire [17:0] t931; + wire [17:0] t932; + wire [17:0] t933; + wire [17:0] t934; + wire [17:0] t935; + wire [17:0] t936; + wire [17:0] t937; + wire [17:0] t952; + wire [17:0] t953; + wire [17:0] t954; + wire [17:0] t955; + wire [17:0] t956; + wire [17:0] t957; + wire [17:0] t958; + wire [17:0] t959; + wire [17:0] t972; + wire [17:0] t973; + wire [17:0] t974; + wire [17:0] t975; + wire [17:0] t976; + wire [17:0] t977; + wire [17:0] t978; + wire [17:0] t979; + wire [17:0] t922; + wire [17:0] t923; + wire [17:0] t924; + wire [17:0] t925; + wire [17:0] t926; + wire [17:0] t927; + wire [17:0] t928; + wire [17:0] t929; + wire [17:0] t938; + wire [17:0] t939; + wire [17:0] t940; + wire [17:0] t941; + wire [17:0] t944; + wire [17:0] t945; + wire [17:0] t946; + wire [17:0] t947; + wire [17:0] t960; + wire [17:0] t961; + wire [17:0] t962; + wire [17:0] t963; + wire [17:0] t964; + wire [17:0] t965; + wire [17:0] t966; + wire [17:0] t967; + wire [17:0] t980; + wire [17:0] t981; + wire [17:0] t982; + wire [17:0] t983; + wire [17:0] t986; + wire [17:0] t987; + wire [17:0] t988; + wire [17:0] t989; + reg [17:0] tm24; + reg [17:0] tm27; + reg [17:0] tm30; + reg [17:0] tm33; + reg [17:0] tm36; + reg [17:0] tm39; + reg [17:0] tm42; + reg [17:0] tm45; + reg [17:0] tm48; + reg [17:0] tm51; + reg [17:0] tm54; + reg [17:0] tm57; + reg [17:0] tm60; + reg [17:0] tm63; + reg [17:0] tm66; + reg [17:0] tm69; + wire [17:0] a225; + wire [17:0] a226; + wire [17:0] a227; + wire [17:0] a228; + wire [17:0] a229; + wire [17:0] a230; + wire [17:0] a231; + wire [17:0] a232; + wire [17:0] a233; + wire [17:0] a234; + wire [17:0] a235; + wire [17:0] a236; + wire [17:0] a237; + wire [17:0] a238; + wire [17:0] a239; + wire [17:0] a240; + wire [17:0] a241; + wire [17:0] a242; + wire [17:0] a243; + wire [17:0] a244; + wire [17:0] a245; + wire [17:0] a246; + wire [17:0] a247; + wire [17:0] a248; + reg [17:0] tm25; + reg [17:0] tm28; + reg [17:0] tm31; + reg [17:0] tm34; + reg [17:0] tm37; + reg [17:0] tm40; + reg [17:0] tm43; + reg [17:0] tm46; + reg [17:0] tm49; + reg [17:0] tm52; + reg [17:0] tm55; + reg [17:0] tm58; + reg [17:0] tm61; + reg [17:0] tm64; + reg [17:0] tm67; + reg [17:0] tm70; + wire [17:0] t942; + wire [17:0] t943; + wire [17:0] t948; + wire [17:0] t949; + wire [17:0] t950; + wire [17:0] t951; + wire [17:0] t968; + wire [17:0] t969; + wire [17:0] t970; + wire [17:0] t971; + wire [17:0] t984; + wire [17:0] t985; + wire [17:0] t990; + wire [17:0] t991; + wire [17:0] t992; + wire [17:0] t993; + reg [17:0] tm26; + reg [17:0] tm29; + reg [17:0] tm32; + reg [17:0] tm35; + reg [17:0] tm38; + reg [17:0] tm41; + reg [17:0] tm44; + reg [17:0] tm47; + reg [17:0] tm50; + reg [17:0] tm53; + reg [17:0] tm56; + reg [17:0] tm59; + reg [17:0] tm62; + reg [17:0] tm65; + reg [17:0] tm68; + reg [17:0] tm71; + +wire [17:0] tm0; +assign tm0 = (18'hb505 >> (18-18)); +wire [17:0] tm2; +assign tm2 = (18'hec83 >> (18-18)); +wire [17:0] tm3; +assign tm3 = (18'h61f8 >> (18-18)); + +assign a249 = X0; + assign a250 = X16; + assign a251 = X1; + assign a252 = X17; + assign a257 = X8; + assign a258 = X24; + assign a259 = X9; + assign a260 = X25; + assign a265 = X2; + assign a266 = X18; + assign a267 = X3; + assign a268 = X19; + assign a273 = X10; + assign a274 = X26; + assign a275 = X11; + assign a276 = X27; + assign a281 = X4; + assign a282 = X20; + assign a283 = X5; + assign a284 = X21; + assign a289 = X12; + assign a290 = X28; + assign a291 = X13; + assign a292 = X29; + assign a297 = X6; + assign a298 = X22; + assign a299 = X7; + assign a300 = X23; + assign a305 = X14; + assign a306 = X30; + assign a307 = X15; + assign a308 = X31; + assign Y0 = tm26; + assign Y1 = tm29; + assign Y4 = tm32; + assign Y5 = tm35; + assign Y2 = tm38; + assign Y3 = tm41; + assign Y6 = tm44; + assign Y7 = tm47; + assign Y8 = tm50; + assign Y9 = tm53; + assign Y12 = t942; + assign Y13 = t943; + assign Y10 = t948; + assign Y11 = t949; + assign Y14 = t950; + assign Y15 = t951; + assign Y16 = tm56; + assign Y17 = tm59; + assign Y20 = tm62; + assign Y21 = tm65; + assign Y18 = t968; + assign Y19 = t969; + assign Y22 = (~(t970)+1'b1); + assign Y23 = t971; + assign Y24 = tm68; + assign Y25 = tm71; + assign Y28 = (~(t984)+1'b1); + assign Y29 = t985; + assign Y26 = t990; + assign Y27 = t991; + assign Y30 = t992; + assign Y31 = (~(t993)+1'b1); + +addfxp_18_1 add98062(.a(a249), .b(a250), .clk(clk), .q(t914)); + addfxp_18_1 add98077(.a(a251), .b(a252), .clk(clk), .q(t915)); + subfxp_18_1 sub98092(.a(a249), .b(a250), .clk(clk), .q(t916)); + subfxp_18_1 sub98107(.a(a251), .b(a252), .clk(clk), .q(t917)); + addfxp_18_1 add98122(.a(a257), .b(a258), .clk(clk), .q(t918)); + addfxp_18_1 add98137(.a(a259), .b(a260), .clk(clk), .q(t919)); + subfxp_18_1 sub98152(.a(a257), .b(a258), .clk(clk), .q(t920)); + subfxp_18_1 sub98167(.a(a259), .b(a260), .clk(clk), .q(t921)); + addfxp_18_1 add98270(.a(a265), .b(a266), .clk(clk), .q(t930)); + addfxp_18_1 add98285(.a(a267), .b(a268), .clk(clk), .q(t931)); + subfxp_18_1 sub98300(.a(a265), .b(a266), .clk(clk), .q(t932)); + subfxp_18_1 sub98315(.a(a267), .b(a268), .clk(clk), .q(t933)); + addfxp_18_1 add98330(.a(a273), .b(a274), .clk(clk), .q(t934)); + addfxp_18_1 add98345(.a(a275), .b(a276), .clk(clk), .q(t935)); + subfxp_18_1 sub98360(.a(a273), .b(a274), .clk(clk), .q(t936)); + subfxp_18_1 sub98375(.a(a275), .b(a276), .clk(clk), .q(t937)); + addfxp_18_1 add98590(.a(a281), .b(a282), .clk(clk), .q(t952)); + addfxp_18_1 add98605(.a(a283), .b(a284), .clk(clk), .q(t953)); + subfxp_18_1 sub98620(.a(a281), .b(a282), .clk(clk), .q(t954)); + subfxp_18_1 sub98635(.a(a283), .b(a284), .clk(clk), .q(t955)); + addfxp_18_1 add98650(.a(a289), .b(a290), .clk(clk), .q(t956)); + addfxp_18_1 add98665(.a(a291), .b(a292), .clk(clk), .q(t957)); + subfxp_18_1 sub98680(.a(a289), .b(a290), .clk(clk), .q(t958)); + subfxp_18_1 sub98695(.a(a291), .b(a292), .clk(clk), .q(t959)); + addfxp_18_1 add98856(.a(a297), .b(a298), .clk(clk), .q(t972)); + addfxp_18_1 add98871(.a(a299), .b(a300), .clk(clk), .q(t973)); + subfxp_18_1 sub98886(.a(a297), .b(a298), .clk(clk), .q(t974)); + subfxp_18_1 sub98901(.a(a299), .b(a300), .clk(clk), .q(t975)); + addfxp_18_1 add98916(.a(a305), .b(a306), .clk(clk), .q(t976)); + addfxp_18_1 add98931(.a(a307), .b(a308), .clk(clk), .q(t977)); + subfxp_18_1 sub98946(.a(a305), .b(a306), .clk(clk), .q(t978)); + subfxp_18_1 sub98961(.a(a307), .b(a308), .clk(clk), .q(t979)); + addfxp_18_1 add98174(.a(t914), .b(t918), .clk(clk), .q(t922)); + addfxp_18_1 add98181(.a(t915), .b(t919), .clk(clk), .q(t923)); + subfxp_18_1 sub98188(.a(t914), .b(t918), .clk(clk), .q(t924)); + subfxp_18_1 sub98195(.a(t915), .b(t919), .clk(clk), .q(t925)); + subfxp_18_1 sub98218(.a(t916), .b(t921), .clk(clk), .q(t926)); + addfxp_18_1 add98225(.a(t917), .b(t920), .clk(clk), .q(t927)); + addfxp_18_1 add98232(.a(t916), .b(t921), .clk(clk), .q(t928)); + subfxp_18_1 sub98239(.a(t917), .b(t920), .clk(clk), .q(t929)); + addfxp_18_1 add98382(.a(t930), .b(t934), .clk(clk), .q(t938)); + addfxp_18_1 add98389(.a(t931), .b(t935), .clk(clk), .q(t939)); + subfxp_18_1 sub98396(.a(t930), .b(t934), .clk(clk), .q(t940)); + subfxp_18_1 sub98403(.a(t931), .b(t935), .clk(clk), .q(t941)); + subfxp_18_1 sub98454(.a(t932), .b(t937), .clk(clk), .q(t944)); + addfxp_18_1 add98461(.a(t933), .b(t936), .clk(clk), .q(t945)); + addfxp_18_1 add98468(.a(t932), .b(t937), .clk(clk), .q(t946)); + subfxp_18_1 sub98475(.a(t933), .b(t936), .clk(clk), .q(t947)); + addfxp_18_1 add98702(.a(t952), .b(t956), .clk(clk), .q(t960)); + addfxp_18_1 add98709(.a(t953), .b(t957), .clk(clk), .q(t961)); + subfxp_18_1 sub98716(.a(t952), .b(t956), .clk(clk), .q(t962)); + subfxp_18_1 sub98723(.a(t953), .b(t957), .clk(clk), .q(t963)); + subfxp_18_1 sub98747(.a(t954), .b(t959), .clk(clk), .q(t964)); + addfxp_18_1 add98754(.a(t955), .b(t958), .clk(clk), .q(t965)); + addfxp_18_1 add98761(.a(t954), .b(t959), .clk(clk), .q(t966)); + subfxp_18_1 sub98768(.a(t955), .b(t958), .clk(clk), .q(t967)); + addfxp_18_1 add98968(.a(t972), .b(t976), .clk(clk), .q(t980)); + addfxp_18_1 add98975(.a(t973), .b(t977), .clk(clk), .q(t981)); + subfxp_18_1 sub98982(.a(t972), .b(t976), .clk(clk), .q(t982)); + subfxp_18_1 sub98989(.a(t973), .b(t977), .clk(clk), .q(t983)); + subfxp_18_1 sub99041(.a(t974), .b(t979), .clk(clk), .q(t986)); + addfxp_18_1 add99048(.a(t975), .b(t978), .clk(clk), .q(t987)); + addfxp_18_1 add99055(.a(t974), .b(t979), .clk(clk), .q(t988)); + subfxp_18_1 sub99062(.a(t975), .b(t978), .clk(clk), .q(t989)); + +multfix_alt_dsp_18 m88566(.ax(tm0), .ay(t940), .bx(tm0), .by(t941), .clk(clk), .a_q_sc(a225), .a_q_unsc(), .b_q_sc(a226), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88570(.ax(tm2), .ay(t944), .bx(tm3), .by(t945), .clk(clk), .a_q_sc(a227), .a_q_unsc(), .b_q_sc(a228), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88572(.ax(tm3), .ay(t944), .bx(tm2), .by(t945), .clk(clk), .a_q_sc(a229), .a_q_unsc(), .b_q_sc(a230), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88574(.ax(tm3), .ay(t946), .bx(tm2), .by(t947), .clk(clk), .a_q_sc(a231), .a_q_unsc(), .b_q_sc(a232), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88576(.ax(tm2), .ay(t946), .bx(tm3), .by(t947), .clk(clk), .a_q_sc(a233), .a_q_unsc(), .b_q_sc(a234), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88578(.ax(tm0), .ay(t964), .bx(tm0), .by(t965), .clk(clk), .a_q_sc(a235), .a_q_unsc(), .b_q_sc(a236), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88580(.ax(tm0), .ay(t966), .bx(tm0), .by(t967), .clk(clk), .a_q_sc(a237), .a_q_unsc(), .b_q_sc(a238), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88582(.ax(tm0), .ay(t982), .bx(tm0), .by(t983), .clk(clk), .a_q_sc(a239), .a_q_unsc(), .b_q_sc(a240), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88584(.ax(tm3), .ay(t986), .bx(tm2), .by(t987), .clk(clk), .a_q_sc(a241), .a_q_unsc(), .b_q_sc(a242), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88586(.ax(tm2), .ay(t986), .bx(tm3), .by(t987), .clk(clk), .a_q_sc(a243), .a_q_unsc(), .b_q_sc(a244), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88588(.ax(tm3), .ay(t989), .bx(tm2), .by(t988), .clk(clk), .a_q_sc(a245), .a_q_unsc(), .b_q_sc(a246), .b_q_unsc(), .rst(reset)); + multfix_alt_dsp_18 m88590(.ax(tm3), .ay(t988), .bx(tm2), .by(t989), .clk(clk), .a_q_sc(a247), .a_q_unsc(), .b_q_sc(a248), .b_q_unsc(), .rst(reset)); + +subfxp_18_1 sub98424(.a(a225), .b(a226), .clk(clk), .q(t942)); + addfxp_18_1 add98431(.a(a225), .b(a226), .clk(clk), .q(t943)); + subfxp_18_1 sub98496(.a(a227), .b(a228), .clk(clk), .q(t948)); + addfxp_18_1 add98517(.a(a229), .b(a230), .clk(clk), .q(t949)); + subfxp_18_1 sub98538(.a(a231), .b(a232), .clk(clk), .q(t950)); + addfxp_18_1 add98559(.a(a233), .b(a234), .clk(clk), .q(t951)); + subfxp_18_1 sub98789(.a(a235), .b(a236), .clk(clk), .q(t968)); + addfxp_18_1 add98796(.a(a235), .b(a236), .clk(clk), .q(t969)); + addfxp_18_1 add98817(.a(a237), .b(a238), .clk(clk), .q(t970)); + subfxp_18_1 sub98824(.a(a237), .b(a238), .clk(clk), .q(t971)); + addfxp_18_1 add99010(.a(a239), .b(a240), .clk(clk), .q(t984)); + subfxp_18_1 sub99017(.a(a239), .b(a240), .clk(clk), .q(t985)); + subfxp_18_1 sub99083(.a(a241), .b(a242), .clk(clk), .q(t990)); + addfxp_18_1 add99104(.a(a243), .b(a244), .clk(clk), .q(t991)); + subfxp_18_1 sub99125(.a(a245), .b(a246), .clk(clk), .q(t992)); + addfxp_18_1 add99146(.a(a247), .b(a248), .clk(clk), .q(t993)); + +always @(posedge clk) begin + if (reset == 1) begin + next <= 1'b0; + end else begin + X0 <= X0_in; + X1 <= X1_in; + X2 <= X2_in; + X3 <= X3_in; + X4 <= X4_in; + X5 <= X5_in; + X6 <= X6_in; + X7 <= X7_in; + X8 <= X8_in; + X9 <= X9_in; + X10 <= X10_in; + X11 <= X11_in; + X12 <= X12_in; + X13 <= X13_in; + X14 <= X14_in; + X15 <= X15_in; + X16 <= X16_in; + X17 <= X17_in; + X18 <= X18_in; + X19 <= X19_in; + X20 <= X20_in; + X21 <= X21_in; + X22 <= X22_in; + X23 <= X23_in; + X24 <= X24_in; + X25 <= X25_in; + X26 <= X26_in; + X27 <= X27_in; + X28 <= X28_in; + X29 <= X29_in; + X30 <= X30_in; + X31 <= X31_in; + next <= next_in; + tm24 <= t922; + tm27 <= t923; + tm30 <= t924; + tm33 <= t925; + tm36 <= t926; + tm39 <= t927; + tm42 <= t928; + tm45 <= t929; + tm48 <= t938; + tm51 <= t939; + tm54 <= t960; + tm57 <= t961; + tm60 <= (~(t963)+1'b1); + tm63 <= t962; + tm66 <= t980; + tm69 <= t981; + tm25 <= tm24; + tm28 <= tm27; + tm31 <= tm30; + tm34 <= tm33; + tm37 <= tm36; + tm40 <= tm39; + tm43 <= tm42; + tm46 <= tm45; + tm49 <= tm48; + tm52 <= tm51; + tm55 <= tm54; + tm58 <= tm57; + tm61 <= tm60; + tm64 <= tm63; + tm67 <= tm66; + tm70 <= tm69; + tm26 <= tm25; + tm29 <= tm28; + tm32 <= tm31; + tm35 <= tm34; + tm38 <= tm37; + tm41 <= tm40; + tm44 <= tm43; + tm47 <= tm46; + tm50 <= tm49; + tm53 <= tm52; + tm56 <= tm55; + tm59 <= tm58; + tm62 <= tm61; + tm65 <= tm64; + tm68 <= tm67; + tm71 <= tm70; + end +end + +endmodule + +module codeBlock99168_18 ( + input clk, + input reset, + input next_in, + input [17:0] X0_in, + output [17:0] Y0, + input [17:0] X1_in, + output [17:0] Y1, + input [17:0] X2_in, + output [17:0] Y2, + input [17:0] X3_in, + output [17:0] Y3, + input [17:0] X4_in, + output [17:0] Y4, + input [17:0] X5_in, + output [17:0] Y5, + input [17:0] X6_in, + output [17:0] Y6, + input [17:0] X7_in, + output [17:0] Y7, + input [17:0] X8_in, + output [17:0] Y8, + input [17:0] X9_in, + output [17:0] Y9, + input [17:0] X10_in, + output [17:0] Y10, + input [17:0] X11_in, + output [17:0] Y11, + input [17:0] X12_in, + output [17:0] Y12, + input [17:0] X13_in, + output [17:0] Y13, + input [17:0] X14_in, + output [17:0] Y14, + input [17:0] X15_in, + output [17:0] Y15, + input [17:0] X16_in, + output [17:0] Y16, + input [17:0] X17_in, + output [17:0] Y17, + input [17:0] X18_in, + output [17:0] Y18, + input [17:0] X19_in, + output [17:0] Y19, + input [17:0] X20_in, + output [17:0] Y20, + input [17:0] X21_in, + output [17:0] Y21, + input [17:0] X22_in, + output [17:0] Y22, + input [17:0] X23_in, + output [17:0] Y23, + input [17:0] X24_in, + output [17:0] Y24, + input [17:0] X25_in, + output [17:0] Y25, + input [17:0] X26_in, + output [17:0] Y26, + input [17:0] X27_in, + output [17:0] Y27, + input [17:0] X28_in, + output [17:0] Y28, + input [17:0] X29_in, + output [17:0] Y29, + input [17:0] X30_in, + output [17:0] Y30, + input [17:0] X31_in, + output [17:0] Y31, + output next_out +); + +reg next; +reg [17:0] X0; +reg [17:0] X1; +reg [17:0] X2; +reg [17:0] X3; +reg [17:0] X4; +reg [17:0] X5; +reg [17:0] X6; +reg [17:0] X7; +reg [17:0] X8; +reg [17:0] X9; +reg [17:0] X10; +reg [17:0] X11; +reg [17:0] X12; +reg [17:0] X13; +reg [17:0] X14; +reg [17:0] X15; +reg [17:0] X16; +reg [17:0] X17; +reg [17:0] X18; +reg [17:0] X19; +reg [17:0] X20; +reg [17:0] X21; +reg [17:0] X22; +reg [17:0] X23; +reg [17:0] X24; +reg [17:0] X25; +reg [17:0] X26; +reg [17:0] X27; +reg [17:0] X28; +reg [17:0] X29; +reg [17:0] X30; +reg [17:0] X31; +shiftRegFIFO_2_1 shiftRegFIFO_2_1_inst_zwdeesbmlx ( + .X(next), + .Y(next_out), + .reset(reset), + .clk(clk) +); +wire [17:0] a65; + wire [17:0] a66; + wire [17:0] a67; + wire [17:0] a68; + wire [17:0] a73; + wire [17:0] a74; + wire [17:0] a75; + wire [17:0] a76; + wire [17:0] a81; + wire [17:0] a82; + wire [17:0] a83; + wire [17:0] a84; + wire [17:0] a89; + wire [17:0] a90; + wire [17:0] a91; + wire [17:0] a92; + wire [17:0] a97; + wire [17:0] a98; + wire [17:0] a99; + wire [17:0] a100; + wire [17:0] a105; + wire [17:0] a106; + wire [17:0] a107; + wire [17:0] a108; + wire [17:0] a113; + wire [17:0] a114; + wire [17:0] a115; + wire [17:0] a116; + wire [17:0] a121; + wire [17:0] a122; + wire [17:0] a123; + wire [17:0] a124; + wire [17:0] t402; + wire [17:0] t403; + wire [17:0] t404; + wire [17:0] t405; + wire [17:0] t406; + wire [17:0] t407; + wire [17:0] t408; + wire [17:0] t409; + wire [17:0] t418; + wire [17:0] t419; + wire [17:0] t420; + wire [17:0] t421; + wire [17:0] t422; + wire [17:0] t423; + wire [17:0] t424; + wire [17:0] t425; + wire [17:0] t434; + wire [17:0] t435; + wire [17:0] t436; + wire [17:0] t437; + wire [17:0] t438; + wire [17:0] t439; + wire [17:0] t440; + wire [17:0] t441; + wire [17:0] t450; + wire [17:0] t451; + wire [17:0] t452; + wire [17:0] t453; + wire [17:0] t454; + wire [17:0] t455; + wire [17:0] t456; + wire [17:0] t457; + wire [17:0] t410; + wire [17:0] t411; + wire [17:0] t412; + wire [17:0] t413; + wire [17:0] t414; + wire [17:0] t415; + wire [17:0] t416; + wire [17:0] t417; + wire [17:0] t426; + wire [17:0] t427; + wire [17:0] t428; + wire [17:0] t429; + wire [17:0] t430; + wire [17:0] t431; + wire [17:0] t432; + wire [17:0] t433; + wire [17:0] t442; + wire [17:0] t443; + wire [17:0] t444; + wire [17:0] t445; + wire [17:0] t446; + wire [17:0] t447; + wire [17:0] t448; + wire [17:0] t449; + wire [17:0] t458; + wire [17:0] t459; + wire [17:0] t460; + wire [17:0] t461; + wire [17:0] t462; + wire [17:0] t463; + wire [17:0] t464; + wire [17:0] t465; + +assign a65 = X0; + assign a66 = X16; + assign a67 = X1; + assign a68 = X17; + assign a73 = X8; + assign a74 = X24; + assign a75 = X9; + assign a76 = X25; + assign a81 = X2; + assign a82 = X18; + assign a83 = X3; + assign a84 = X19; + assign a89 = X10; + assign a90 = X26; + assign a91 = X11; + assign a92 = X27; + assign a97 = X4; + assign a98 = X20; + assign a99 = X5; + assign a100 = X21; + assign a105 = X12; + assign a106 = X28; + assign a107 = X13; + assign a108 = X29; + assign a113 = X6; + assign a114 = X22; + assign a115 = X7; + assign a116 = X23; + assign a121 = X14; + assign a122 = X30; + assign a123 = X15; + assign a124 = X31; + assign Y0 = t410; + assign Y1 = t411; + assign Y16 = t412; + assign Y17 = t413; + assign Y8 = t414; + assign Y9 = t415; + assign Y24 = t416; + assign Y25 = t417; + assign Y2 = t426; + assign Y3 = t427; + assign Y18 = t428; + assign Y19 = t429; + assign Y10 = t430; + assign Y11 = t431; + assign Y26 = t432; + assign Y27 = t433; + assign Y4 = t442; + assign Y5 = t443; + assign Y20 = t444; + assign Y21 = t445; + assign Y12 = t446; + assign Y13 = t447; + assign Y28 = t448; + assign Y29 = t449; + assign Y6 = t458; + assign Y7 = t459; + assign Y22 = t460; + assign Y23 = t461; + assign Y14 = t462; + assign Y15 = t463; + assign Y30 = t464; + assign Y31 = t465; + +addfxp_18_1 add99180(.a(a65), .b(a66), .clk(clk), .q(t402)); + addfxp_18_1 add99195(.a(a67), .b(a68), .clk(clk), .q(t403)); + subfxp_18_1 sub99210(.a(a65), .b(a66), .clk(clk), .q(t404)); + subfxp_18_1 sub99225(.a(a67), .b(a68), .clk(clk), .q(t405)); + addfxp_18_1 add99240(.a(a73), .b(a74), .clk(clk), .q(t406)); + addfxp_18_1 add99255(.a(a75), .b(a76), .clk(clk), .q(t407)); + subfxp_18_1 sub99270(.a(a73), .b(a74), .clk(clk), .q(t408)); + subfxp_18_1 sub99285(.a(a75), .b(a76), .clk(clk), .q(t409)); + addfxp_18_1 add99388(.a(a81), .b(a82), .clk(clk), .q(t418)); + addfxp_18_1 add99403(.a(a83), .b(a84), .clk(clk), .q(t419)); + subfxp_18_1 sub99418(.a(a81), .b(a82), .clk(clk), .q(t420)); + subfxp_18_1 sub99433(.a(a83), .b(a84), .clk(clk), .q(t421)); + addfxp_18_1 add99448(.a(a89), .b(a90), .clk(clk), .q(t422)); + addfxp_18_1 add99463(.a(a91), .b(a92), .clk(clk), .q(t423)); + subfxp_18_1 sub99478(.a(a89), .b(a90), .clk(clk), .q(t424)); + subfxp_18_1 sub99493(.a(a91), .b(a92), .clk(clk), .q(t425)); + addfxp_18_1 add99596(.a(a97), .b(a98), .clk(clk), .q(t434)); + addfxp_18_1 add99611(.a(a99), .b(a100), .clk(clk), .q(t435)); + subfxp_18_1 sub99626(.a(a97), .b(a98), .clk(clk), .q(t436)); + subfxp_18_1 sub99641(.a(a99), .b(a100), .clk(clk), .q(t437)); + addfxp_18_1 add99656(.a(a105), .b(a106), .clk(clk), .q(t438)); + addfxp_18_1 add99671(.a(a107), .b(a108), .clk(clk), .q(t439)); + subfxp_18_1 sub99686(.a(a105), .b(a106), .clk(clk), .q(t440)); + subfxp_18_1 sub99701(.a(a107), .b(a108), .clk(clk), .q(t441)); + addfxp_18_1 add99804(.a(a113), .b(a114), .clk(clk), .q(t450)); + addfxp_18_1 add99819(.a(a115), .b(a116), .clk(clk), .q(t451)); + subfxp_18_1 sub99834(.a(a113), .b(a114), .clk(clk), .q(t452)); + subfxp_18_1 sub99849(.a(a115), .b(a116), .clk(clk), .q(t453)); + addfxp_18_1 add99864(.a(a121), .b(a122), .clk(clk), .q(t454)); + addfxp_18_1 add99879(.a(a123), .b(a124), .clk(clk), .q(t455)); + subfxp_18_1 sub99894(.a(a121), .b(a122), .clk(clk), .q(t456)); + subfxp_18_1 sub99909(.a(a123), .b(a124), .clk(clk), .q(t457)); + addfxp_18_1 add99292(.a(t402), .b(t406), .clk(clk), .q(t410)); + addfxp_18_1 add99299(.a(t403), .b(t407), .clk(clk), .q(t411)); + subfxp_18_1 sub99306(.a(t402), .b(t406), .clk(clk), .q(t412)); + subfxp_18_1 sub99313(.a(t403), .b(t407), .clk(clk), .q(t413)); + subfxp_18_1 sub99336(.a(t404), .b(t409), .clk(clk), .q(t414)); + addfxp_18_1 add99343(.a(t405), .b(t408), .clk(clk), .q(t415)); + addfxp_18_1 add99350(.a(t404), .b(t409), .clk(clk), .q(t416)); + subfxp_18_1 sub99357(.a(t405), .b(t408), .clk(clk), .q(t417)); + addfxp_18_1 add99500(.a(t418), .b(t422), .clk(clk), .q(t426)); + addfxp_18_1 add99507(.a(t419), .b(t423), .clk(clk), .q(t427)); + subfxp_18_1 sub99514(.a(t418), .b(t422), .clk(clk), .q(t428)); + subfxp_18_1 sub99521(.a(t419), .b(t423), .clk(clk), .q(t429)); + subfxp_18_1 sub99544(.a(t420), .b(t425), .clk(clk), .q(t430)); + addfxp_18_1 add99551(.a(t421), .b(t424), .clk(clk), .q(t431)); + addfxp_18_1 add99558(.a(t420), .b(t425), .clk(clk), .q(t432)); + subfxp_18_1 sub99565(.a(t421), .b(t424), .clk(clk), .q(t433)); + addfxp_18_1 add99708(.a(t434), .b(t438), .clk(clk), .q(t442)); + addfxp_18_1 add99715(.a(t435), .b(t439), .clk(clk), .q(t443)); + subfxp_18_1 sub99722(.a(t434), .b(t438), .clk(clk), .q(t444)); + subfxp_18_1 sub99729(.a(t435), .b(t439), .clk(clk), .q(t445)); + subfxp_18_1 sub99752(.a(t436), .b(t441), .clk(clk), .q(t446)); + addfxp_18_1 add99759(.a(t437), .b(t440), .clk(clk), .q(t447)); + addfxp_18_1 add99766(.a(t436), .b(t441), .clk(clk), .q(t448)); + subfxp_18_1 sub99773(.a(t437), .b(t440), .clk(clk), .q(t449)); + addfxp_18_1 add99916(.a(t450), .b(t454), .clk(clk), .q(t458)); + addfxp_18_1 add99923(.a(t451), .b(t455), .clk(clk), .q(t459)); + subfxp_18_1 sub99930(.a(t450), .b(t454), .clk(clk), .q(t460)); + subfxp_18_1 sub99937(.a(t451), .b(t455), .clk(clk), .q(t461)); + subfxp_18_1 sub99960(.a(t452), .b(t457), .clk(clk), .q(t462)); + addfxp_18_1 add99967(.a(t453), .b(t456), .clk(clk), .q(t463)); + addfxp_18_1 add99974(.a(t452), .b(t457), .clk(clk), .q(t464)); + subfxp_18_1 sub99981(.a(t453), .b(t456), .clk(clk), .q(t465)); + +always @(posedge clk) begin + if (reset == 1) begin + next <= 1'b0; + end else begin + X0 <= X0_in; + X1 <= X1_in; + X2 <= X2_in; + X3 <= X3_in; + X4 <= X4_in; + X5 <= X5_in; + X6 <= X6_in; + X7 <= X7_in; + X8 <= X8_in; + X9 <= X9_in; + X10 <= X10_in; + X11 <= X11_in; + X12 <= X12_in; + X13 <= X13_in; + X14 <= X14_in; + X15 <= X15_in; + X16 <= X16_in; + X17 <= X17_in; + X18 <= X18_in; + X19 <= X19_in; + X20 <= X20_in; + X21 <= X21_in; + X22 <= X22_in; + X23 <= X23_in; + X24 <= X24_in; + X25 <= X25_in; + X26 <= X26_in; + X27 <= X27_in; + X28 <= X28_in; + X29 <= X29_in; + X30 <= X30_in; + X31 <= X31_in; + next <= next_in; + end +end + +endmodule + +module stage2_parameter_buffer_18_1_16_64 ( + input clk, + input reset, + input [287:0] wdata +, input [6:0] wen, + output [17:0] o_Wic_0, + output [17:0] o_bi_0, + output [17:0] o_Wfc_0, + output [17:0] o_bf_0, + output [17:0] o_Woc_0, + output [17:0] o_bo_0, + output [17:0] o_bc_0, + output [17:0] o_Wic_1, + output [17:0] o_bi_1, + output [17:0] o_Wfc_1, + output [17:0] o_bf_1, + output [17:0] o_Woc_1, + output [17:0] o_bo_1, + output [17:0] o_bc_1, + output [17:0] o_Wic_2, + output [17:0] o_bi_2, + output [17:0] o_Wfc_2, + output [17:0] o_bf_2, + output [17:0] o_Woc_2, + output [17:0] o_bo_2, + output [17:0] o_bc_2, + output [17:0] o_Wic_3, + output [17:0] o_bi_3, + output [17:0] o_Wfc_3, + output [17:0] o_bf_3, + output [17:0] o_Woc_3, + output [17:0] o_bo_3, + output [17:0] o_bc_3, + output [17:0] o_Wic_4, + output [17:0] o_bi_4, + output [17:0] o_Wfc_4, + output [17:0] o_bf_4, + output [17:0] o_Woc_4, + output [17:0] o_bo_4, + output [17:0] o_bc_4, + output [17:0] o_Wic_5, + output [17:0] o_bi_5, + output [17:0] o_Wfc_5, + output [17:0] o_bf_5, + output [17:0] o_Woc_5, + output [17:0] o_bo_5, + output [17:0] o_bc_5, + output [17:0] o_Wic_6, + output [17:0] o_bi_6, + output [17:0] o_Wfc_6, + output [17:0] o_bf_6, + output [17:0] o_Woc_6, + output [17:0] o_bo_6, + output [17:0] o_bc_6, + output [17:0] o_Wic_7, + output [17:0] o_bi_7, + output [17:0] o_Wfc_7, + output [17:0] o_bf_7, + output [17:0] o_Woc_7, + output [17:0] o_bo_7, + output [17:0] o_bc_7, + output [17:0] o_Wic_8, + output [17:0] o_bi_8, + output [17:0] o_Wfc_8, + output [17:0] o_bf_8, + output [17:0] o_Woc_8, + output [17:0] o_bo_8, + output [17:0] o_bc_8, + output [17:0] o_Wic_9, + output [17:0] o_bi_9, + output [17:0] o_Wfc_9, + output [17:0] o_bf_9, + output [17:0] o_Woc_9, + output [17:0] o_bo_9, + output [17:0] o_bc_9, + output [17:0] o_Wic_10, + output [17:0] o_bi_10, + output [17:0] o_Wfc_10, + output [17:0] o_bf_10, + output [17:0] o_Woc_10, + output [17:0] o_bo_10, + output [17:0] o_bc_10, + output [17:0] o_Wic_11, + output [17:0] o_bi_11, + output [17:0] o_Wfc_11, + output [17:0] o_bf_11, + output [17:0] o_Woc_11, + output [17:0] o_bo_11, + output [17:0] o_bc_11, + output [17:0] o_Wic_12, + output [17:0] o_bi_12, + output [17:0] o_Wfc_12, + output [17:0] o_bf_12, + output [17:0] o_Woc_12, + output [17:0] o_bo_12, + output [17:0] o_bc_12, + output [17:0] o_Wic_13, + output [17:0] o_bi_13, + output [17:0] o_Wfc_13, + output [17:0] o_bf_13, + output [17:0] o_Woc_13, + output [17:0] o_bo_13, + output [17:0] o_bc_13, + output [17:0] o_Wic_14, + output [17:0] o_bi_14, + output [17:0] o_Wfc_14, + output [17:0] o_bf_14, + output [17:0] o_Woc_14, + output [17:0] o_bo_14, + output [17:0] o_bc_14, + output [17:0] o_Wic_15, + output [17:0] o_bi_15, + output [17:0] o_Wfc_15, + output [17:0] o_bf_15, + output [17:0] o_Woc_15, + output [17:0] o_bo_15, + output [17:0] o_bc_15, + input incr_index +); + +wire [17:0] Wic_0_0; +wire [17:0] bi_0_0; +wire [17:0] Wfc_0_0; +wire [17:0] bf_0_0; +wire [17:0] Woc_0_0; +wire [17:0] bo_0_0; +wire [17:0] bc_0_0; +wire [17:0] Wic_0_1; +wire [17:0] bi_0_1; +wire [17:0] Wfc_0_1; +wire [17:0] bf_0_1; +wire [17:0] Woc_0_1; +wire [17:0] bo_0_1; +wire [17:0] bc_0_1; +wire [17:0] Wic_0_2; +wire [17:0] bi_0_2; +wire [17:0] Wfc_0_2; +wire [17:0] bf_0_2; +wire [17:0] Woc_0_2; +wire [17:0] bo_0_2; +wire [17:0] bc_0_2; +wire [17:0] Wic_0_3; +wire [17:0] bi_0_3; +wire [17:0] Wfc_0_3; +wire [17:0] bf_0_3; +wire [17:0] Woc_0_3; +wire [17:0] bo_0_3; +wire [17:0] bc_0_3; +wire [17:0] Wic_0_4; +wire [17:0] bi_0_4; +wire [17:0] Wfc_0_4; +wire [17:0] bf_0_4; +wire [17:0] Woc_0_4; +wire [17:0] bo_0_4; +wire [17:0] bc_0_4; +wire [17:0] Wic_0_5; +wire [17:0] bi_0_5; +wire [17:0] Wfc_0_5; +wire [17:0] bf_0_5; +wire [17:0] Woc_0_5; +wire [17:0] bo_0_5; +wire [17:0] bc_0_5; +wire [17:0] Wic_0_6; +wire [17:0] bi_0_6; +wire [17:0] Wfc_0_6; +wire [17:0] bf_0_6; +wire [17:0] Woc_0_6; +wire [17:0] bo_0_6; +wire [17:0] bc_0_6; +wire [17:0] Wic_0_7; +wire [17:0] bi_0_7; +wire [17:0] Wfc_0_7; +wire [17:0] bf_0_7; +wire [17:0] Woc_0_7; +wire [17:0] bo_0_7; +wire [17:0] bc_0_7; +wire [17:0] Wic_0_8; +wire [17:0] bi_0_8; +wire [17:0] Wfc_0_8; +wire [17:0] bf_0_8; +wire [17:0] Woc_0_8; +wire [17:0] bo_0_8; +wire [17:0] bc_0_8; +wire [17:0] Wic_0_9; +wire [17:0] bi_0_9; +wire [17:0] Wfc_0_9; +wire [17:0] bf_0_9; +wire [17:0] Woc_0_9; +wire [17:0] bo_0_9; +wire [17:0] bc_0_9; +wire [17:0] Wic_0_10; +wire [17:0] bi_0_10; +wire [17:0] Wfc_0_10; +wire [17:0] bf_0_10; +wire [17:0] Woc_0_10; +wire [17:0] bo_0_10; +wire [17:0] bc_0_10; +wire [17:0] Wic_0_11; +wire [17:0] bi_0_11; +wire [17:0] Wfc_0_11; +wire [17:0] bf_0_11; +wire [17:0] Woc_0_11; +wire [17:0] bo_0_11; +wire [17:0] bc_0_11; +wire [17:0] Wic_0_12; +wire [17:0] bi_0_12; +wire [17:0] Wfc_0_12; +wire [17:0] bf_0_12; +wire [17:0] Woc_0_12; +wire [17:0] bo_0_12; +wire [17:0] bc_0_12; +wire [17:0] Wic_0_13; +wire [17:0] bi_0_13; +wire [17:0] Wfc_0_13; +wire [17:0] bf_0_13; +wire [17:0] Woc_0_13; +wire [17:0] bo_0_13; +wire [17:0] bc_0_13; +wire [17:0] Wic_0_14; +wire [17:0] bi_0_14; +wire [17:0] Wfc_0_14; +wire [17:0] bf_0_14; +wire [17:0] Woc_0_14; +wire [17:0] bo_0_14; +wire [17:0] bc_0_14; +wire [17:0] Wic_0_15; +wire [17:0] bi_0_15; +wire [17:0] Wfc_0_15; +wire [17:0] bf_0_15; +wire [17:0] Woc_0_15; +wire [17:0] bo_0_15; +wire [17:0] bc_0_15; + +wire [13:0] input_index_counter; +counter_63_1 counter_63_1_inst_eaylkfnfsd ( + .clk(clk), + .reset(reset), + .ena(incr_index), + .count(input_index_counter) +); + +weight_buffer_18_16_1_64_Wic_0 weight_buffer_18_16_1_64_Wic_0_inst_qwoaacifoe ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[6]), + .q_0_0(Wic_0_0), + .q_0_1(Wic_0_1), + .q_0_2(Wic_0_2), + .q_0_3(Wic_0_3), + .q_0_4(Wic_0_4), + .q_0_5(Wic_0_5), + .q_0_6(Wic_0_6), + .q_0_7(Wic_0_7), + .q_0_8(Wic_0_8), + .q_0_9(Wic_0_9), + .q_0_10(Wic_0_10), + .q_0_11(Wic_0_11), + .q_0_12(Wic_0_12), + .q_0_13(Wic_0_13), + .q_0_14(Wic_0_14), + .q_0_15(Wic_0_15), + .index(input_index_counter) +); + +weight_buffer_18_16_1_64_bi_0 weight_buffer_18_16_1_64_bi_0_inst_xtyygtgqis ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[0]), + .q_0_0(bi_0_0), + .q_0_1(bi_0_1), + .q_0_2(bi_0_2), + .q_0_3(bi_0_3), + .q_0_4(bi_0_4), + .q_0_5(bi_0_5), + .q_0_6(bi_0_6), + .q_0_7(bi_0_7), + .q_0_8(bi_0_8), + .q_0_9(bi_0_9), + .q_0_10(bi_0_10), + .q_0_11(bi_0_11), + .q_0_12(bi_0_12), + .q_0_13(bi_0_13), + .q_0_14(bi_0_14), + .q_0_15(bi_0_15), + .index(input_index_counter) +); + +weight_buffer_18_16_1_64_Wfc_0 weight_buffer_18_16_1_64_Wfc_0_inst_shdadciaqe ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[1]), + .q_0_0(Wfc_0_0), + .q_0_1(Wfc_0_1), + .q_0_2(Wfc_0_2), + .q_0_3(Wfc_0_3), + .q_0_4(Wfc_0_4), + .q_0_5(Wfc_0_5), + .q_0_6(Wfc_0_6), + .q_0_7(Wfc_0_7), + .q_0_8(Wfc_0_8), + .q_0_9(Wfc_0_9), + .q_0_10(Wfc_0_10), + .q_0_11(Wfc_0_11), + .q_0_12(Wfc_0_12), + .q_0_13(Wfc_0_13), + .q_0_14(Wfc_0_14), + .q_0_15(Wfc_0_15), + .index(input_index_counter) +); + +weight_buffer_18_16_1_64_bf_0 weight_buffer_18_16_1_64_bf_0_inst_fbtuwvrini ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[2]), + .q_0_0(bf_0_0), + .q_0_1(bf_0_1), + .q_0_2(bf_0_2), + .q_0_3(bf_0_3), + .q_0_4(bf_0_4), + .q_0_5(bf_0_5), + .q_0_6(bf_0_6), + .q_0_7(bf_0_7), + .q_0_8(bf_0_8), + .q_0_9(bf_0_9), + .q_0_10(bf_0_10), + .q_0_11(bf_0_11), + .q_0_12(bf_0_12), + .q_0_13(bf_0_13), + .q_0_14(bf_0_14), + .q_0_15(bf_0_15), + .index(input_index_counter) +); + +weight_buffer_18_16_1_64_Woc_0 weight_buffer_18_16_1_64_Woc_0_inst_cuodpphary ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[3]), + .q_0_0(Woc_0_0), + .q_0_1(Woc_0_1), + .q_0_2(Woc_0_2), + .q_0_3(Woc_0_3), + .q_0_4(Woc_0_4), + .q_0_5(Woc_0_5), + .q_0_6(Woc_0_6), + .q_0_7(Woc_0_7), + .q_0_8(Woc_0_8), + .q_0_9(Woc_0_9), + .q_0_10(Woc_0_10), + .q_0_11(Woc_0_11), + .q_0_12(Woc_0_12), + .q_0_13(Woc_0_13), + .q_0_14(Woc_0_14), + .q_0_15(Woc_0_15), + .index(input_index_counter) +); + +weight_buffer_18_16_1_64_bo_0 weight_buffer_18_16_1_64_bo_0_inst_pyhaiemzeb ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[4]), + .q_0_0(bo_0_0), + .q_0_1(bo_0_1), + .q_0_2(bo_0_2), + .q_0_3(bo_0_3), + .q_0_4(bo_0_4), + .q_0_5(bo_0_5), + .q_0_6(bo_0_6), + .q_0_7(bo_0_7), + .q_0_8(bo_0_8), + .q_0_9(bo_0_9), + .q_0_10(bo_0_10), + .q_0_11(bo_0_11), + .q_0_12(bo_0_12), + .q_0_13(bo_0_13), + .q_0_14(bo_0_14), + .q_0_15(bo_0_15), + .index(input_index_counter) +); + +weight_buffer_18_16_1_64_bc_0 weight_buffer_18_16_1_64_bc_0_inst_tdhhhtnvbk ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[5]), + .q_0_0(bc_0_0), + .q_0_1(bc_0_1), + .q_0_2(bc_0_2), + .q_0_3(bc_0_3), + .q_0_4(bc_0_4), + .q_0_5(bc_0_5), + .q_0_6(bc_0_6), + .q_0_7(bc_0_7), + .q_0_8(bc_0_8), + .q_0_9(bc_0_9), + .q_0_10(bc_0_10), + .q_0_11(bc_0_11), + .q_0_12(bc_0_12), + .q_0_13(bc_0_13), + .q_0_14(bc_0_14), + .q_0_15(bc_0_15), + .index(input_index_counter) +); + +assign o_Wic_0 = Wic_0_0; +assign o_bi_0 = bi_0_0; +assign o_Wfc_0 = Wfc_0_0; +assign o_bf_0 = bf_0_0; +assign o_Woc_0 = Woc_0_0; +assign o_bo_0 = bo_0_0; +assign o_bc_0 = bc_0_0; +assign o_Wic_1 = Wic_0_1; +assign o_bi_1 = bi_0_1; +assign o_Wfc_1 = Wfc_0_1; +assign o_bf_1 = bf_0_1; +assign o_Woc_1 = Woc_0_1; +assign o_bo_1 = bo_0_1; +assign o_bc_1 = bc_0_1; +assign o_Wic_2 = Wic_0_2; +assign o_bi_2 = bi_0_2; +assign o_Wfc_2 = Wfc_0_2; +assign o_bf_2 = bf_0_2; +assign o_Woc_2 = Woc_0_2; +assign o_bo_2 = bo_0_2; +assign o_bc_2 = bc_0_2; +assign o_Wic_3 = Wic_0_3; +assign o_bi_3 = bi_0_3; +assign o_Wfc_3 = Wfc_0_3; +assign o_bf_3 = bf_0_3; +assign o_Woc_3 = Woc_0_3; +assign o_bo_3 = bo_0_3; +assign o_bc_3 = bc_0_3; +assign o_Wic_4 = Wic_0_4; +assign o_bi_4 = bi_0_4; +assign o_Wfc_4 = Wfc_0_4; +assign o_bf_4 = bf_0_4; +assign o_Woc_4 = Woc_0_4; +assign o_bo_4 = bo_0_4; +assign o_bc_4 = bc_0_4; +assign o_Wic_5 = Wic_0_5; +assign o_bi_5 = bi_0_5; +assign o_Wfc_5 = Wfc_0_5; +assign o_bf_5 = bf_0_5; +assign o_Woc_5 = Woc_0_5; +assign o_bo_5 = bo_0_5; +assign o_bc_5 = bc_0_5; +assign o_Wic_6 = Wic_0_6; +assign o_bi_6 = bi_0_6; +assign o_Wfc_6 = Wfc_0_6; +assign o_bf_6 = bf_0_6; +assign o_Woc_6 = Woc_0_6; +assign o_bo_6 = bo_0_6; +assign o_bc_6 = bc_0_6; +assign o_Wic_7 = Wic_0_7; +assign o_bi_7 = bi_0_7; +assign o_Wfc_7 = Wfc_0_7; +assign o_bf_7 = bf_0_7; +assign o_Woc_7 = Woc_0_7; +assign o_bo_7 = bo_0_7; +assign o_bc_7 = bc_0_7; +assign o_Wic_8 = Wic_0_8; +assign o_bi_8 = bi_0_8; +assign o_Wfc_8 = Wfc_0_8; +assign o_bf_8 = bf_0_8; +assign o_Woc_8 = Woc_0_8; +assign o_bo_8 = bo_0_8; +assign o_bc_8 = bc_0_8; +assign o_Wic_9 = Wic_0_9; +assign o_bi_9 = bi_0_9; +assign o_Wfc_9 = Wfc_0_9; +assign o_bf_9 = bf_0_9; +assign o_Woc_9 = Woc_0_9; +assign o_bo_9 = bo_0_9; +assign o_bc_9 = bc_0_9; +assign o_Wic_10 = Wic_0_10; +assign o_bi_10 = bi_0_10; +assign o_Wfc_10 = Wfc_0_10; +assign o_bf_10 = bf_0_10; +assign o_Woc_10 = Woc_0_10; +assign o_bo_10 = bo_0_10; +assign o_bc_10 = bc_0_10; +assign o_Wic_11 = Wic_0_11; +assign o_bi_11 = bi_0_11; +assign o_Wfc_11 = Wfc_0_11; +assign o_bf_11 = bf_0_11; +assign o_Woc_11 = Woc_0_11; +assign o_bo_11 = bo_0_11; +assign o_bc_11 = bc_0_11; +assign o_Wic_12 = Wic_0_12; +assign o_bi_12 = bi_0_12; +assign o_Wfc_12 = Wfc_0_12; +assign o_bf_12 = bf_0_12; +assign o_Woc_12 = Woc_0_12; +assign o_bo_12 = bo_0_12; +assign o_bc_12 = bc_0_12; +assign o_Wic_13 = Wic_0_13; +assign o_bi_13 = bi_0_13; +assign o_Wfc_13 = Wfc_0_13; +assign o_bf_13 = bf_0_13; +assign o_Woc_13 = Woc_0_13; +assign o_bo_13 = bo_0_13; +assign o_bc_13 = bc_0_13; +assign o_Wic_14 = Wic_0_14; +assign o_bi_14 = bi_0_14; +assign o_Wfc_14 = Wfc_0_14; +assign o_bf_14 = bf_0_14; +assign o_Woc_14 = Woc_0_14; +assign o_bo_14 = bo_0_14; +assign o_bc_14 = bc_0_14; +assign o_Wic_15 = Wic_0_15; +assign o_bi_15 = bi_0_15; +assign o_Wfc_15 = Wfc_0_15; +assign o_bf_15 = bf_0_15; +assign o_Woc_15 = Woc_0_15; +assign o_bo_15 = bo_0_15; +assign o_bc_15 = bc_0_15; + +endmodule + +module weight_buffer_18_16_1_64_Wic_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + end else begin + addrs_0 <= index + addrs_base_0; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; + +endmodule + +module weight_buffer_18_16_1_64_bi_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + end else begin + addrs_0 <= index + addrs_base_0; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; + +endmodule + +module weight_buffer_18_16_1_64_Wfc_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + end else begin + addrs_0 <= index + addrs_base_0; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; + +endmodule + +module weight_buffer_18_16_1_64_bf_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + end else begin + addrs_0 <= index + addrs_base_0; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; + +endmodule + +module weight_buffer_18_16_1_64_Woc_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + end else begin + addrs_0 <= index + addrs_base_0; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; + +endmodule + +module weight_buffer_18_16_1_64_bo_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + end else begin + addrs_0 <= index + addrs_base_0; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; + +endmodule + +module weight_buffer_18_16_1_64_bc_0 ( + input clk, + input rst, + input [287:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + output [17:0] q_0_9, + output [17:0] q_0_10, + output [17:0] q_0_11, + output [17:0] q_0_12, + output [17:0] q_0_13, + output [17:0] q_0_14, + output [17:0] q_0_15, + input [5:0] index +); + +wire [287:0] packed_result_0; +reg [5:0] addrs_0; +reg [5:0] addrs_base_0; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + end else begin + addrs_0 <= index + addrs_base_0; + end +end + +spram #(.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; +assign q_0_9 = packed_result_0[179:162]; +assign q_0_10 = packed_result_0[197:180]; +assign q_0_11 = packed_result_0[215:198]; +assign q_0_12 = packed_result_0[233:216]; +assign q_0_13 = packed_result_0[251:234]; +assign q_0_14 = packed_result_0[269:252]; +assign q_0_15 = packed_result_0[287:270]; + +endmodule + +module C_LSTM_stage_2_18_10_16_1 ( + input clk, + input reset, + input enable, + input i_valid, + input [17:0] Ct_1_0, + input [17:0] WixrXtYt_1_0, + input [17:0] Wic_0, + input [17:0] bi_0, + input [17:0] WfxrXtYt_1_0, + input [17:0] Wfc_0, + input [17:0] bf_0, + input [17:0] WoxrXtYt_1_0, + input [17:0] Woc_0, + input [17:0] bo_0, + input [17:0] WcxrXtYt_1_0, + input [17:0] bc_0, + output [17:0] out_mt_0, + output [17:0] out_ct_0, + input [17:0] Ct_1_1, + input [17:0] WixrXtYt_1_1, + input [17:0] Wic_1, + input [17:0] bi_1, + input [17:0] WfxrXtYt_1_1, + input [17:0] Wfc_1, + input [17:0] bf_1, + input [17:0] WoxrXtYt_1_1, + input [17:0] Woc_1, + input [17:0] bo_1, + input [17:0] WcxrXtYt_1_1, + input [17:0] bc_1, + output [17:0] out_mt_1, + output [17:0] out_ct_1, + input [17:0] Ct_1_2, + input [17:0] WixrXtYt_1_2, + input [17:0] Wic_2, + input [17:0] bi_2, + input [17:0] WfxrXtYt_1_2, + input [17:0] Wfc_2, + input [17:0] bf_2, + input [17:0] WoxrXtYt_1_2, + input [17:0] Woc_2, + input [17:0] bo_2, + input [17:0] WcxrXtYt_1_2, + input [17:0] bc_2, + output [17:0] out_mt_2, + output [17:0] out_ct_2, + input [17:0] Ct_1_3, + input [17:0] WixrXtYt_1_3, + input [17:0] Wic_3, + input [17:0] bi_3, + input [17:0] WfxrXtYt_1_3, + input [17:0] Wfc_3, + input [17:0] bf_3, + input [17:0] WoxrXtYt_1_3, + input [17:0] Woc_3, + input [17:0] bo_3, + input [17:0] WcxrXtYt_1_3, + input [17:0] bc_3, + output [17:0] out_mt_3, + output [17:0] out_ct_3, + input [17:0] Ct_1_4, + input [17:0] WixrXtYt_1_4, + input [17:0] Wic_4, + input [17:0] bi_4, + input [17:0] WfxrXtYt_1_4, + input [17:0] Wfc_4, + input [17:0] bf_4, + input [17:0] WoxrXtYt_1_4, + input [17:0] Woc_4, + input [17:0] bo_4, + input [17:0] WcxrXtYt_1_4, + input [17:0] bc_4, + output [17:0] out_mt_4, + output [17:0] out_ct_4, + input [17:0] Ct_1_5, + input [17:0] WixrXtYt_1_5, + input [17:0] Wic_5, + input [17:0] bi_5, + input [17:0] WfxrXtYt_1_5, + input [17:0] Wfc_5, + input [17:0] bf_5, + input [17:0] WoxrXtYt_1_5, + input [17:0] Woc_5, + input [17:0] bo_5, + input [17:0] WcxrXtYt_1_5, + input [17:0] bc_5, + output [17:0] out_mt_5, + output [17:0] out_ct_5, + input [17:0] Ct_1_6, + input [17:0] WixrXtYt_1_6, + input [17:0] Wic_6, + input [17:0] bi_6, + input [17:0] WfxrXtYt_1_6, + input [17:0] Wfc_6, + input [17:0] bf_6, + input [17:0] WoxrXtYt_1_6, + input [17:0] Woc_6, + input [17:0] bo_6, + input [17:0] WcxrXtYt_1_6, + input [17:0] bc_6, + output [17:0] out_mt_6, + output [17:0] out_ct_6, + input [17:0] Ct_1_7, + input [17:0] WixrXtYt_1_7, + input [17:0] Wic_7, + input [17:0] bi_7, + input [17:0] WfxrXtYt_1_7, + input [17:0] Wfc_7, + input [17:0] bf_7, + input [17:0] WoxrXtYt_1_7, + input [17:0] Woc_7, + input [17:0] bo_7, + input [17:0] WcxrXtYt_1_7, + input [17:0] bc_7, + output [17:0] out_mt_7, + output [17:0] out_ct_7, + input [17:0] Ct_1_8, + input [17:0] WixrXtYt_1_8, + input [17:0] Wic_8, + input [17:0] bi_8, + input [17:0] WfxrXtYt_1_8, + input [17:0] Wfc_8, + input [17:0] bf_8, + input [17:0] WoxrXtYt_1_8, + input [17:0] Woc_8, + input [17:0] bo_8, + input [17:0] WcxrXtYt_1_8, + input [17:0] bc_8, + output [17:0] out_mt_8, + output [17:0] out_ct_8, + input [17:0] Ct_1_9, + input [17:0] WixrXtYt_1_9, + input [17:0] Wic_9, + input [17:0] bi_9, + input [17:0] WfxrXtYt_1_9, + input [17:0] Wfc_9, + input [17:0] bf_9, + input [17:0] WoxrXtYt_1_9, + input [17:0] Woc_9, + input [17:0] bo_9, + input [17:0] WcxrXtYt_1_9, + input [17:0] bc_9, + output [17:0] out_mt_9, + output [17:0] out_ct_9, + input [17:0] Ct_1_10, + input [17:0] WixrXtYt_1_10, + input [17:0] Wic_10, + input [17:0] bi_10, + input [17:0] WfxrXtYt_1_10, + input [17:0] Wfc_10, + input [17:0] bf_10, + input [17:0] WoxrXtYt_1_10, + input [17:0] Woc_10, + input [17:0] bo_10, + input [17:0] WcxrXtYt_1_10, + input [17:0] bc_10, + output [17:0] out_mt_10, + output [17:0] out_ct_10, + input [17:0] Ct_1_11, + input [17:0] WixrXtYt_1_11, + input [17:0] Wic_11, + input [17:0] bi_11, + input [17:0] WfxrXtYt_1_11, + input [17:0] Wfc_11, + input [17:0] bf_11, + input [17:0] WoxrXtYt_1_11, + input [17:0] Woc_11, + input [17:0] bo_11, + input [17:0] WcxrXtYt_1_11, + input [17:0] bc_11, + output [17:0] out_mt_11, + output [17:0] out_ct_11, + input [17:0] Ct_1_12, + input [17:0] WixrXtYt_1_12, + input [17:0] Wic_12, + input [17:0] bi_12, + input [17:0] WfxrXtYt_1_12, + input [17:0] Wfc_12, + input [17:0] bf_12, + input [17:0] WoxrXtYt_1_12, + input [17:0] Woc_12, + input [17:0] bo_12, + input [17:0] WcxrXtYt_1_12, + input [17:0] bc_12, + output [17:0] out_mt_12, + output [17:0] out_ct_12, + input [17:0] Ct_1_13, + input [17:0] WixrXtYt_1_13, + input [17:0] Wic_13, + input [17:0] bi_13, + input [17:0] WfxrXtYt_1_13, + input [17:0] Wfc_13, + input [17:0] bf_13, + input [17:0] WoxrXtYt_1_13, + input [17:0] Woc_13, + input [17:0] bo_13, + input [17:0] WcxrXtYt_1_13, + input [17:0] bc_13, + output [17:0] out_mt_13, + output [17:0] out_ct_13, + input [17:0] Ct_1_14, + input [17:0] WixrXtYt_1_14, + input [17:0] Wic_14, + input [17:0] bi_14, + input [17:0] WfxrXtYt_1_14, + input [17:0] Wfc_14, + input [17:0] bf_14, + input [17:0] WoxrXtYt_1_14, + input [17:0] Woc_14, + input [17:0] bo_14, + input [17:0] WcxrXtYt_1_14, + input [17:0] bc_14, + output [17:0] out_mt_14, + output [17:0] out_ct_14, + input [17:0] Ct_1_15, + input [17:0] WixrXtYt_1_15, + input [17:0] Wic_15, + input [17:0] bi_15, + input [17:0] WfxrXtYt_1_15, + input [17:0] Wfc_15, + input [17:0] bf_15, + input [17:0] WoxrXtYt_1_15, + input [17:0] Woc_15, + input [17:0] bo_15, + input [17:0] WcxrXtYt_1_15, + input [17:0] bc_15, + output [17:0] out_mt_15, + output [17:0] out_ct_15, + output o_valid, + output o_ready +); + +reg reg_i_valid, reg_o_valid; +reg [17:0] reg_Ct_1_0; +reg [17:0] reg_WixrXtYt_1_0; +reg [17:0] reg_Wic_0; +reg [17:0] reg_bi_0; +reg [17:0] reg_WfxrXtYt_1_0; +reg [17:0] reg_Wfc_0; +reg [17:0] reg_bf_0; +reg [17:0] reg_WoxrXtYt_1_0; +reg [17:0] reg_Woc_0; +reg [17:0] reg_bo_0; +reg [17:0] reg_WcxrXtYt_1_0; +reg [17:0] reg_bc_0; +reg [17:0] reg_out_mt_0; +reg [17:0] reg_out_ct_0; +reg [17:0] reg_Ct_1_1; +reg [17:0] reg_WixrXtYt_1_1; +reg [17:0] reg_Wic_1; +reg [17:0] reg_bi_1; +reg [17:0] reg_WfxrXtYt_1_1; +reg [17:0] reg_Wfc_1; +reg [17:0] reg_bf_1; +reg [17:0] reg_WoxrXtYt_1_1; +reg [17:0] reg_Woc_1; +reg [17:0] reg_bo_1; +reg [17:0] reg_WcxrXtYt_1_1; +reg [17:0] reg_bc_1; +reg [17:0] reg_out_mt_1; +reg [17:0] reg_out_ct_1; +reg [17:0] reg_Ct_1_2; +reg [17:0] reg_WixrXtYt_1_2; +reg [17:0] reg_Wic_2; +reg [17:0] reg_bi_2; +reg [17:0] reg_WfxrXtYt_1_2; +reg [17:0] reg_Wfc_2; +reg [17:0] reg_bf_2; +reg [17:0] reg_WoxrXtYt_1_2; +reg [17:0] reg_Woc_2; +reg [17:0] reg_bo_2; +reg [17:0] reg_WcxrXtYt_1_2; +reg [17:0] reg_bc_2; +reg [17:0] reg_out_mt_2; +reg [17:0] reg_out_ct_2; +reg [17:0] reg_Ct_1_3; +reg [17:0] reg_WixrXtYt_1_3; +reg [17:0] reg_Wic_3; +reg [17:0] reg_bi_3; +reg [17:0] reg_WfxrXtYt_1_3; +reg [17:0] reg_Wfc_3; +reg [17:0] reg_bf_3; +reg [17:0] reg_WoxrXtYt_1_3; +reg [17:0] reg_Woc_3; +reg [17:0] reg_bo_3; +reg [17:0] reg_WcxrXtYt_1_3; +reg [17:0] reg_bc_3; +reg [17:0] reg_out_mt_3; +reg [17:0] reg_out_ct_3; +reg [17:0] reg_Ct_1_4; +reg [17:0] reg_WixrXtYt_1_4; +reg [17:0] reg_Wic_4; +reg [17:0] reg_bi_4; +reg [17:0] reg_WfxrXtYt_1_4; +reg [17:0] reg_Wfc_4; +reg [17:0] reg_bf_4; +reg [17:0] reg_WoxrXtYt_1_4; +reg [17:0] reg_Woc_4; +reg [17:0] reg_bo_4; +reg [17:0] reg_WcxrXtYt_1_4; +reg [17:0] reg_bc_4; +reg [17:0] reg_out_mt_4; +reg [17:0] reg_out_ct_4; +reg [17:0] reg_Ct_1_5; +reg [17:0] reg_WixrXtYt_1_5; +reg [17:0] reg_Wic_5; +reg [17:0] reg_bi_5; +reg [17:0] reg_WfxrXtYt_1_5; +reg [17:0] reg_Wfc_5; +reg [17:0] reg_bf_5; +reg [17:0] reg_WoxrXtYt_1_5; +reg [17:0] reg_Woc_5; +reg [17:0] reg_bo_5; +reg [17:0] reg_WcxrXtYt_1_5; +reg [17:0] reg_bc_5; +reg [17:0] reg_out_mt_5; +reg [17:0] reg_out_ct_5; +reg [17:0] reg_Ct_1_6; +reg [17:0] reg_WixrXtYt_1_6; +reg [17:0] reg_Wic_6; +reg [17:0] reg_bi_6; +reg [17:0] reg_WfxrXtYt_1_6; +reg [17:0] reg_Wfc_6; +reg [17:0] reg_bf_6; +reg [17:0] reg_WoxrXtYt_1_6; +reg [17:0] reg_Woc_6; +reg [17:0] reg_bo_6; +reg [17:0] reg_WcxrXtYt_1_6; +reg [17:0] reg_bc_6; +reg [17:0] reg_out_mt_6; +reg [17:0] reg_out_ct_6; +reg [17:0] reg_Ct_1_7; +reg [17:0] reg_WixrXtYt_1_7; +reg [17:0] reg_Wic_7; +reg [17:0] reg_bi_7; +reg [17:0] reg_WfxrXtYt_1_7; +reg [17:0] reg_Wfc_7; +reg [17:0] reg_bf_7; +reg [17:0] reg_WoxrXtYt_1_7; +reg [17:0] reg_Woc_7; +reg [17:0] reg_bo_7; +reg [17:0] reg_WcxrXtYt_1_7; +reg [17:0] reg_bc_7; +reg [17:0] reg_out_mt_7; +reg [17:0] reg_out_ct_7; +reg [17:0] reg_Ct_1_8; +reg [17:0] reg_WixrXtYt_1_8; +reg [17:0] reg_Wic_8; +reg [17:0] reg_bi_8; +reg [17:0] reg_WfxrXtYt_1_8; +reg [17:0] reg_Wfc_8; +reg [17:0] reg_bf_8; +reg [17:0] reg_WoxrXtYt_1_8; +reg [17:0] reg_Woc_8; +reg [17:0] reg_bo_8; +reg [17:0] reg_WcxrXtYt_1_8; +reg [17:0] reg_bc_8; +reg [17:0] reg_out_mt_8; +reg [17:0] reg_out_ct_8; +reg [17:0] reg_Ct_1_9; +reg [17:0] reg_WixrXtYt_1_9; +reg [17:0] reg_Wic_9; +reg [17:0] reg_bi_9; +reg [17:0] reg_WfxrXtYt_1_9; +reg [17:0] reg_Wfc_9; +reg [17:0] reg_bf_9; +reg [17:0] reg_WoxrXtYt_1_9; +reg [17:0] reg_Woc_9; +reg [17:0] reg_bo_9; +reg [17:0] reg_WcxrXtYt_1_9; +reg [17:0] reg_bc_9; +reg [17:0] reg_out_mt_9; +reg [17:0] reg_out_ct_9; +reg [17:0] reg_Ct_1_10; +reg [17:0] reg_WixrXtYt_1_10; +reg [17:0] reg_Wic_10; +reg [17:0] reg_bi_10; +reg [17:0] reg_WfxrXtYt_1_10; +reg [17:0] reg_Wfc_10; +reg [17:0] reg_bf_10; +reg [17:0] reg_WoxrXtYt_1_10; +reg [17:0] reg_Woc_10; +reg [17:0] reg_bo_10; +reg [17:0] reg_WcxrXtYt_1_10; +reg [17:0] reg_bc_10; +reg [17:0] reg_out_mt_10; +reg [17:0] reg_out_ct_10; +reg [17:0] reg_Ct_1_11; +reg [17:0] reg_WixrXtYt_1_11; +reg [17:0] reg_Wic_11; +reg [17:0] reg_bi_11; +reg [17:0] reg_WfxrXtYt_1_11; +reg [17:0] reg_Wfc_11; +reg [17:0] reg_bf_11; +reg [17:0] reg_WoxrXtYt_1_11; +reg [17:0] reg_Woc_11; +reg [17:0] reg_bo_11; +reg [17:0] reg_WcxrXtYt_1_11; +reg [17:0] reg_bc_11; +reg [17:0] reg_out_mt_11; +reg [17:0] reg_out_ct_11; +reg [17:0] reg_Ct_1_12; +reg [17:0] reg_WixrXtYt_1_12; +reg [17:0] reg_Wic_12; +reg [17:0] reg_bi_12; +reg [17:0] reg_WfxrXtYt_1_12; +reg [17:0] reg_Wfc_12; +reg [17:0] reg_bf_12; +reg [17:0] reg_WoxrXtYt_1_12; +reg [17:0] reg_Woc_12; +reg [17:0] reg_bo_12; +reg [17:0] reg_WcxrXtYt_1_12; +reg [17:0] reg_bc_12; +reg [17:0] reg_out_mt_12; +reg [17:0] reg_out_ct_12; +reg [17:0] reg_Ct_1_13; +reg [17:0] reg_WixrXtYt_1_13; +reg [17:0] reg_Wic_13; +reg [17:0] reg_bi_13; +reg [17:0] reg_WfxrXtYt_1_13; +reg [17:0] reg_Wfc_13; +reg [17:0] reg_bf_13; +reg [17:0] reg_WoxrXtYt_1_13; +reg [17:0] reg_Woc_13; +reg [17:0] reg_bo_13; +reg [17:0] reg_WcxrXtYt_1_13; +reg [17:0] reg_bc_13; +reg [17:0] reg_out_mt_13; +reg [17:0] reg_out_ct_13; +reg [17:0] reg_Ct_1_14; +reg [17:0] reg_WixrXtYt_1_14; +reg [17:0] reg_Wic_14; +reg [17:0] reg_bi_14; +reg [17:0] reg_WfxrXtYt_1_14; +reg [17:0] reg_Wfc_14; +reg [17:0] reg_bf_14; +reg [17:0] reg_WoxrXtYt_1_14; +reg [17:0] reg_Woc_14; +reg [17:0] reg_bo_14; +reg [17:0] reg_WcxrXtYt_1_14; +reg [17:0] reg_bc_14; +reg [17:0] reg_out_mt_14; +reg [17:0] reg_out_ct_14; +reg [17:0] reg_Ct_1_15; +reg [17:0] reg_WixrXtYt_1_15; +reg [17:0] reg_Wic_15; +reg [17:0] reg_bi_15; +reg [17:0] reg_WfxrXtYt_1_15; +reg [17:0] reg_Wfc_15; +reg [17:0] reg_bf_15; +reg [17:0] reg_WoxrXtYt_1_15; +reg [17:0] reg_Woc_15; +reg [17:0] reg_bo_15; +reg [17:0] reg_WcxrXtYt_1_15; +reg [17:0] reg_bc_15; +reg [17:0] reg_out_mt_15; +reg [17:0] reg_out_ct_15; + +wire input_gate_valid, forget_gate_valid, output_gate_valid, gt_valid; +wire it_gt_mult_valid, ft_Ct_1_mult_valid; +wire ct_valid; +wire tanh_valid_0; +wire [17:0] o_Ct_1_0; +wire [17:0] Ct_1_hold_0; +wire [17:0] o_input_gate_0; +wire [17:0] o_forget_gate_0; +wire [17:0] o_output_gate_0; +wire [17:0] ot_hold_0; +wire [17:0] o_gt_0; +wire [17:0] gt_hold_0; +wire [17:0] o_it_gt_mult_0; +wire [17:0] o_ft_Ct_1_mult_0; +wire [17:0] o_ct_0; +wire [17:0] ct_hold_0; +wire [17:0] o_tanh_0; +wire [17:0] o_mt_0; +wire tanh_valid_1; +wire [17:0] o_Ct_1_1; +wire [17:0] Ct_1_hold_1; +wire [17:0] o_input_gate_1; +wire [17:0] o_forget_gate_1; +wire [17:0] o_output_gate_1; +wire [17:0] ot_hold_1; +wire [17:0] o_gt_1; +wire [17:0] gt_hold_1; +wire [17:0] o_it_gt_mult_1; +wire [17:0] o_ft_Ct_1_mult_1; +wire [17:0] o_ct_1; +wire [17:0] ct_hold_1; +wire [17:0] o_tanh_1; +wire [17:0] o_mt_1; +wire tanh_valid_2; +wire [17:0] o_Ct_1_2; +wire [17:0] Ct_1_hold_2; +wire [17:0] o_input_gate_2; +wire [17:0] o_forget_gate_2; +wire [17:0] o_output_gate_2; +wire [17:0] ot_hold_2; +wire [17:0] o_gt_2; +wire [17:0] gt_hold_2; +wire [17:0] o_it_gt_mult_2; +wire [17:0] o_ft_Ct_1_mult_2; +wire [17:0] o_ct_2; +wire [17:0] ct_hold_2; +wire [17:0] o_tanh_2; +wire [17:0] o_mt_2; +wire tanh_valid_3; +wire [17:0] o_Ct_1_3; +wire [17:0] Ct_1_hold_3; +wire [17:0] o_input_gate_3; +wire [17:0] o_forget_gate_3; +wire [17:0] o_output_gate_3; +wire [17:0] ot_hold_3; +wire [17:0] o_gt_3; +wire [17:0] gt_hold_3; +wire [17:0] o_it_gt_mult_3; +wire [17:0] o_ft_Ct_1_mult_3; +wire [17:0] o_ct_3; +wire [17:0] ct_hold_3; +wire [17:0] o_tanh_3; +wire [17:0] o_mt_3; +wire tanh_valid_4; +wire [17:0] o_Ct_1_4; +wire [17:0] Ct_1_hold_4; +wire [17:0] o_input_gate_4; +wire [17:0] o_forget_gate_4; +wire [17:0] o_output_gate_4; +wire [17:0] ot_hold_4; +wire [17:0] o_gt_4; +wire [17:0] gt_hold_4; +wire [17:0] o_it_gt_mult_4; +wire [17:0] o_ft_Ct_1_mult_4; +wire [17:0] o_ct_4; +wire [17:0] ct_hold_4; +wire [17:0] o_tanh_4; +wire [17:0] o_mt_4; +wire tanh_valid_5; +wire [17:0] o_Ct_1_5; +wire [17:0] Ct_1_hold_5; +wire [17:0] o_input_gate_5; +wire [17:0] o_forget_gate_5; +wire [17:0] o_output_gate_5; +wire [17:0] ot_hold_5; +wire [17:0] o_gt_5; +wire [17:0] gt_hold_5; +wire [17:0] o_it_gt_mult_5; +wire [17:0] o_ft_Ct_1_mult_5; +wire [17:0] o_ct_5; +wire [17:0] ct_hold_5; +wire [17:0] o_tanh_5; +wire [17:0] o_mt_5; +wire tanh_valid_6; +wire [17:0] o_Ct_1_6; +wire [17:0] Ct_1_hold_6; +wire [17:0] o_input_gate_6; +wire [17:0] o_forget_gate_6; +wire [17:0] o_output_gate_6; +wire [17:0] ot_hold_6; +wire [17:0] o_gt_6; +wire [17:0] gt_hold_6; +wire [17:0] o_it_gt_mult_6; +wire [17:0] o_ft_Ct_1_mult_6; +wire [17:0] o_ct_6; +wire [17:0] ct_hold_6; +wire [17:0] o_tanh_6; +wire [17:0] o_mt_6; +wire tanh_valid_7; +wire [17:0] o_Ct_1_7; +wire [17:0] Ct_1_hold_7; +wire [17:0] o_input_gate_7; +wire [17:0] o_forget_gate_7; +wire [17:0] o_output_gate_7; +wire [17:0] ot_hold_7; +wire [17:0] o_gt_7; +wire [17:0] gt_hold_7; +wire [17:0] o_it_gt_mult_7; +wire [17:0] o_ft_Ct_1_mult_7; +wire [17:0] o_ct_7; +wire [17:0] ct_hold_7; +wire [17:0] o_tanh_7; +wire [17:0] o_mt_7; +wire tanh_valid_8; +wire [17:0] o_Ct_1_8; +wire [17:0] Ct_1_hold_8; +wire [17:0] o_input_gate_8; +wire [17:0] o_forget_gate_8; +wire [17:0] o_output_gate_8; +wire [17:0] ot_hold_8; +wire [17:0] o_gt_8; +wire [17:0] gt_hold_8; +wire [17:0] o_it_gt_mult_8; +wire [17:0] o_ft_Ct_1_mult_8; +wire [17:0] o_ct_8; +wire [17:0] ct_hold_8; +wire [17:0] o_tanh_8; +wire [17:0] o_mt_8; +wire tanh_valid_9; +wire [17:0] o_Ct_1_9; +wire [17:0] Ct_1_hold_9; +wire [17:0] o_input_gate_9; +wire [17:0] o_forget_gate_9; +wire [17:0] o_output_gate_9; +wire [17:0] ot_hold_9; +wire [17:0] o_gt_9; +wire [17:0] gt_hold_9; +wire [17:0] o_it_gt_mult_9; +wire [17:0] o_ft_Ct_1_mult_9; +wire [17:0] o_ct_9; +wire [17:0] ct_hold_9; +wire [17:0] o_tanh_9; +wire [17:0] o_mt_9; +wire tanh_valid_10; +wire [17:0] o_Ct_1_10; +wire [17:0] Ct_1_hold_10; +wire [17:0] o_input_gate_10; +wire [17:0] o_forget_gate_10; +wire [17:0] o_output_gate_10; +wire [17:0] ot_hold_10; +wire [17:0] o_gt_10; +wire [17:0] gt_hold_10; +wire [17:0] o_it_gt_mult_10; +wire [17:0] o_ft_Ct_1_mult_10; +wire [17:0] o_ct_10; +wire [17:0] ct_hold_10; +wire [17:0] o_tanh_10; +wire [17:0] o_mt_10; +wire tanh_valid_11; +wire [17:0] o_Ct_1_11; +wire [17:0] Ct_1_hold_11; +wire [17:0] o_input_gate_11; +wire [17:0] o_forget_gate_11; +wire [17:0] o_output_gate_11; +wire [17:0] ot_hold_11; +wire [17:0] o_gt_11; +wire [17:0] gt_hold_11; +wire [17:0] o_it_gt_mult_11; +wire [17:0] o_ft_Ct_1_mult_11; +wire [17:0] o_ct_11; +wire [17:0] ct_hold_11; +wire [17:0] o_tanh_11; +wire [17:0] o_mt_11; +wire tanh_valid_12; +wire [17:0] o_Ct_1_12; +wire [17:0] Ct_1_hold_12; +wire [17:0] o_input_gate_12; +wire [17:0] o_forget_gate_12; +wire [17:0] o_output_gate_12; +wire [17:0] ot_hold_12; +wire [17:0] o_gt_12; +wire [17:0] gt_hold_12; +wire [17:0] o_it_gt_mult_12; +wire [17:0] o_ft_Ct_1_mult_12; +wire [17:0] o_ct_12; +wire [17:0] ct_hold_12; +wire [17:0] o_tanh_12; +wire [17:0] o_mt_12; +wire tanh_valid_13; +wire [17:0] o_Ct_1_13; +wire [17:0] Ct_1_hold_13; +wire [17:0] o_input_gate_13; +wire [17:0] o_forget_gate_13; +wire [17:0] o_output_gate_13; +wire [17:0] ot_hold_13; +wire [17:0] o_gt_13; +wire [17:0] gt_hold_13; +wire [17:0] o_it_gt_mult_13; +wire [17:0] o_ft_Ct_1_mult_13; +wire [17:0] o_ct_13; +wire [17:0] ct_hold_13; +wire [17:0] o_tanh_13; +wire [17:0] o_mt_13; +wire tanh_valid_14; +wire [17:0] o_Ct_1_14; +wire [17:0] Ct_1_hold_14; +wire [17:0] o_input_gate_14; +wire [17:0] o_forget_gate_14; +wire [17:0] o_output_gate_14; +wire [17:0] ot_hold_14; +wire [17:0] o_gt_14; +wire [17:0] gt_hold_14; +wire [17:0] o_it_gt_mult_14; +wire [17:0] o_ft_Ct_1_mult_14; +wire [17:0] o_ct_14; +wire [17:0] ct_hold_14; +wire [17:0] o_tanh_14; +wire [17:0] o_mt_14; +wire tanh_valid_15; +wire [17:0] o_Ct_1_15; +wire [17:0] Ct_1_hold_15; +wire [17:0] o_input_gate_15; +wire [17:0] o_forget_gate_15; +wire [17:0] o_output_gate_15; +wire [17:0] ot_hold_15; +wire [17:0] o_gt_15; +wire [17:0] gt_hold_15; +wire [17:0] o_it_gt_mult_15; +wire [17:0] o_ft_Ct_1_mult_15; +wire [17:0] o_ct_15; +wire [17:0] ct_hold_15; +wire [17:0] o_tanh_15; +wire [17:0] o_mt_15; +wire mt_valid; + +assign o_Ct_1_0 = reg_Ct_1_0; +assign o_Ct_1_1 = reg_Ct_1_1; +assign o_Ct_1_2 = reg_Ct_1_2; +assign o_Ct_1_3 = reg_Ct_1_3; +assign o_Ct_1_4 = reg_Ct_1_4; +assign o_Ct_1_5 = reg_Ct_1_5; +assign o_Ct_1_6 = reg_Ct_1_6; +assign o_Ct_1_7 = reg_Ct_1_7; +assign o_Ct_1_8 = reg_Ct_1_8; +assign o_Ct_1_9 = reg_Ct_1_9; +assign o_Ct_1_10 = reg_Ct_1_10; +assign o_Ct_1_11 = reg_Ct_1_11; +assign o_Ct_1_12 = reg_Ct_1_12; +assign o_Ct_1_13 = reg_Ct_1_13; +assign o_Ct_1_14 = reg_Ct_1_14; +assign o_Ct_1_15 = reg_Ct_1_15; +lstm_gate_18_10_16_1 lstm_gate_18_10_16_1_input ( + .clk(clk), + .reset(reset), + .i_ready(enable), + .i_valid(reg_i_valid), + .stage1_result_0(reg_WixrXtYt_1_0), + .weight_0(reg_Wic_0), + .Ct_1_0(reg_Ct_1_0), + .bias_0(reg_bi_0), + .gate_output_0(o_input_gate_0), + .stage1_result_1(reg_WixrXtYt_1_1), + .weight_1(reg_Wic_1), + .Ct_1_1(reg_Ct_1_1), + .bias_1(reg_bi_1), + .gate_output_1(o_input_gate_1), + .stage1_result_2(reg_WixrXtYt_1_2), + .weight_2(reg_Wic_2), + .Ct_1_2(reg_Ct_1_2), + .bias_2(reg_bi_2), + .gate_output_2(o_input_gate_2), + .stage1_result_3(reg_WixrXtYt_1_3), + .weight_3(reg_Wic_3), + .Ct_1_3(reg_Ct_1_3), + .bias_3(reg_bi_3), + .gate_output_3(o_input_gate_3), + .stage1_result_4(reg_WixrXtYt_1_4), + .weight_4(reg_Wic_4), + .Ct_1_4(reg_Ct_1_4), + .bias_4(reg_bi_4), + .gate_output_4(o_input_gate_4), + .stage1_result_5(reg_WixrXtYt_1_5), + .weight_5(reg_Wic_5), + .Ct_1_5(reg_Ct_1_5), + .bias_5(reg_bi_5), + .gate_output_5(o_input_gate_5), + .stage1_result_6(reg_WixrXtYt_1_6), + .weight_6(reg_Wic_6), + .Ct_1_6(reg_Ct_1_6), + .bias_6(reg_bi_6), + .gate_output_6(o_input_gate_6), + .stage1_result_7(reg_WixrXtYt_1_7), + .weight_7(reg_Wic_7), + .Ct_1_7(reg_Ct_1_7), + .bias_7(reg_bi_7), + .gate_output_7(o_input_gate_7), + .stage1_result_8(reg_WixrXtYt_1_8), + .weight_8(reg_Wic_8), + .Ct_1_8(reg_Ct_1_8), + .bias_8(reg_bi_8), + .gate_output_8(o_input_gate_8), + .stage1_result_9(reg_WixrXtYt_1_9), + .weight_9(reg_Wic_9), + .Ct_1_9(reg_Ct_1_9), + .bias_9(reg_bi_9), + .gate_output_9(o_input_gate_9), + .stage1_result_10(reg_WixrXtYt_1_10), + .weight_10(reg_Wic_10), + .Ct_1_10(reg_Ct_1_10), + .bias_10(reg_bi_10), + .gate_output_10(o_input_gate_10), + .stage1_result_11(reg_WixrXtYt_1_11), + .weight_11(reg_Wic_11), + .Ct_1_11(reg_Ct_1_11), + .bias_11(reg_bi_11), + .gate_output_11(o_input_gate_11), + .stage1_result_12(reg_WixrXtYt_1_12), + .weight_12(reg_Wic_12), + .Ct_1_12(reg_Ct_1_12), + .bias_12(reg_bi_12), + .gate_output_12(o_input_gate_12), + .stage1_result_13(reg_WixrXtYt_1_13), + .weight_13(reg_Wic_13), + .Ct_1_13(reg_Ct_1_13), + .bias_13(reg_bi_13), + .gate_output_13(o_input_gate_13), + .stage1_result_14(reg_WixrXtYt_1_14), + .weight_14(reg_Wic_14), + .Ct_1_14(reg_Ct_1_14), + .bias_14(reg_bi_14), + .gate_output_14(o_input_gate_14), + .stage1_result_15(reg_WixrXtYt_1_15), + .weight_15(reg_Wic_15), + .Ct_1_15(reg_Ct_1_15), + .bias_15(reg_bi_15), + .gate_output_15(o_input_gate_15), + .o_valid(input_gate_valid), + .o_ready() +); + +lstm_gate_18_10_16_1 lstm_gate_18_10_16_1_forget ( + .clk(clk), + .reset(reset), + .i_ready(enable), + .i_valid(reg_i_valid), + .stage1_result_0(reg_WfxrXtYt_1_0), + .weight_0(reg_Wfc_0), + .Ct_1_0(reg_Ct_1_0), + .bias_0(reg_bf_0), + .gate_output_0(o_forget_gate_0), + .stage1_result_1(reg_WfxrXtYt_1_1), + .weight_1(reg_Wfc_1), + .Ct_1_1(reg_Ct_1_1), + .bias_1(reg_bf_1), + .gate_output_1(o_forget_gate_1), + .stage1_result_2(reg_WfxrXtYt_1_2), + .weight_2(reg_Wfc_2), + .Ct_1_2(reg_Ct_1_2), + .bias_2(reg_bf_2), + .gate_output_2(o_forget_gate_2), + .stage1_result_3(reg_WfxrXtYt_1_3), + .weight_3(reg_Wfc_3), + .Ct_1_3(reg_Ct_1_3), + .bias_3(reg_bf_3), + .gate_output_3(o_forget_gate_3), + .stage1_result_4(reg_WfxrXtYt_1_4), + .weight_4(reg_Wfc_4), + .Ct_1_4(reg_Ct_1_4), + .bias_4(reg_bf_4), + .gate_output_4(o_forget_gate_4), + .stage1_result_5(reg_WfxrXtYt_1_5), + .weight_5(reg_Wfc_5), + .Ct_1_5(reg_Ct_1_5), + .bias_5(reg_bf_5), + .gate_output_5(o_forget_gate_5), + .stage1_result_6(reg_WfxrXtYt_1_6), + .weight_6(reg_Wfc_6), + .Ct_1_6(reg_Ct_1_6), + .bias_6(reg_bf_6), + .gate_output_6(o_forget_gate_6), + .stage1_result_7(reg_WfxrXtYt_1_7), + .weight_7(reg_Wfc_7), + .Ct_1_7(reg_Ct_1_7), + .bias_7(reg_bf_7), + .gate_output_7(o_forget_gate_7), + .stage1_result_8(reg_WfxrXtYt_1_8), + .weight_8(reg_Wfc_8), + .Ct_1_8(reg_Ct_1_8), + .bias_8(reg_bf_8), + .gate_output_8(o_forget_gate_8), + .stage1_result_9(reg_WfxrXtYt_1_9), + .weight_9(reg_Wfc_9), + .Ct_1_9(reg_Ct_1_9), + .bias_9(reg_bf_9), + .gate_output_9(o_forget_gate_9), + .stage1_result_10(reg_WfxrXtYt_1_10), + .weight_10(reg_Wfc_10), + .Ct_1_10(reg_Ct_1_10), + .bias_10(reg_bf_10), + .gate_output_10(o_forget_gate_10), + .stage1_result_11(reg_WfxrXtYt_1_11), + .weight_11(reg_Wfc_11), + .Ct_1_11(reg_Ct_1_11), + .bias_11(reg_bf_11), + .gate_output_11(o_forget_gate_11), + .stage1_result_12(reg_WfxrXtYt_1_12), + .weight_12(reg_Wfc_12), + .Ct_1_12(reg_Ct_1_12), + .bias_12(reg_bf_12), + .gate_output_12(o_forget_gate_12), + .stage1_result_13(reg_WfxrXtYt_1_13), + .weight_13(reg_Wfc_13), + .Ct_1_13(reg_Ct_1_13), + .bias_13(reg_bf_13), + .gate_output_13(o_forget_gate_13), + .stage1_result_14(reg_WfxrXtYt_1_14), + .weight_14(reg_Wfc_14), + .Ct_1_14(reg_Ct_1_14), + .bias_14(reg_bf_14), + .gate_output_14(o_forget_gate_14), + .stage1_result_15(reg_WfxrXtYt_1_15), + .weight_15(reg_Wfc_15), + .Ct_1_15(reg_Ct_1_15), + .bias_15(reg_bf_15), + .gate_output_15(o_forget_gate_15), + .o_valid(forget_gate_valid), + .o_ready() +); + +lstm_gate_18_10_16_1 lstm_gate_18_10_16_1_output ( + .clk(clk), + .reset(reset), + .i_ready(enable), + .i_valid(reg_i_valid), + .stage1_result_0(reg_WoxrXtYt_1_0), + .weight_0(reg_Woc_0), + .Ct_1_0(reg_Ct_1_0), + .bias_0(reg_bo_0), + .gate_output_0(o_output_gate_0), + .stage1_result_1(reg_WoxrXtYt_1_1), + .weight_1(reg_Woc_1), + .Ct_1_1(reg_Ct_1_1), + .bias_1(reg_bo_1), + .gate_output_1(o_output_gate_1), + .stage1_result_2(reg_WoxrXtYt_1_2), + .weight_2(reg_Woc_2), + .Ct_1_2(reg_Ct_1_2), + .bias_2(reg_bo_2), + .gate_output_2(o_output_gate_2), + .stage1_result_3(reg_WoxrXtYt_1_3), + .weight_3(reg_Woc_3), + .Ct_1_3(reg_Ct_1_3), + .bias_3(reg_bo_3), + .gate_output_3(o_output_gate_3), + .stage1_result_4(reg_WoxrXtYt_1_4), + .weight_4(reg_Woc_4), + .Ct_1_4(reg_Ct_1_4), + .bias_4(reg_bo_4), + .gate_output_4(o_output_gate_4), + .stage1_result_5(reg_WoxrXtYt_1_5), + .weight_5(reg_Woc_5), + .Ct_1_5(reg_Ct_1_5), + .bias_5(reg_bo_5), + .gate_output_5(o_output_gate_5), + .stage1_result_6(reg_WoxrXtYt_1_6), + .weight_6(reg_Woc_6), + .Ct_1_6(reg_Ct_1_6), + .bias_6(reg_bo_6), + .gate_output_6(o_output_gate_6), + .stage1_result_7(reg_WoxrXtYt_1_7), + .weight_7(reg_Woc_7), + .Ct_1_7(reg_Ct_1_7), + .bias_7(reg_bo_7), + .gate_output_7(o_output_gate_7), + .stage1_result_8(reg_WoxrXtYt_1_8), + .weight_8(reg_Woc_8), + .Ct_1_8(reg_Ct_1_8), + .bias_8(reg_bo_8), + .gate_output_8(o_output_gate_8), + .stage1_result_9(reg_WoxrXtYt_1_9), + .weight_9(reg_Woc_9), + .Ct_1_9(reg_Ct_1_9), + .bias_9(reg_bo_9), + .gate_output_9(o_output_gate_9), + .stage1_result_10(reg_WoxrXtYt_1_10), + .weight_10(reg_Woc_10), + .Ct_1_10(reg_Ct_1_10), + .bias_10(reg_bo_10), + .gate_output_10(o_output_gate_10), + .stage1_result_11(reg_WoxrXtYt_1_11), + .weight_11(reg_Woc_11), + .Ct_1_11(reg_Ct_1_11), + .bias_11(reg_bo_11), + .gate_output_11(o_output_gate_11), + .stage1_result_12(reg_WoxrXtYt_1_12), + .weight_12(reg_Woc_12), + .Ct_1_12(reg_Ct_1_12), + .bias_12(reg_bo_12), + .gate_output_12(o_output_gate_12), + .stage1_result_13(reg_WoxrXtYt_1_13), + .weight_13(reg_Woc_13), + .Ct_1_13(reg_Ct_1_13), + .bias_13(reg_bo_13), + .gate_output_13(o_output_gate_13), + .stage1_result_14(reg_WoxrXtYt_1_14), + .weight_14(reg_Woc_14), + .Ct_1_14(reg_Ct_1_14), + .bias_14(reg_bo_14), + .gate_output_14(o_output_gate_14), + .stage1_result_15(reg_WoxrXtYt_1_15), + .weight_15(reg_Woc_15), + .Ct_1_15(reg_Ct_1_15), + .bias_15(reg_bo_15), + .gate_output_15(o_output_gate_15), + .o_valid(output_gate_valid), + .o_ready() +); + +output_activation_18_10_16_1 output_activation_18_10_16_1_inst_hsfhmqluwy ( + .clk(clk), + .reset(reset), + .i_ready(enable), + .i_valid(reg_i_valid), + .stage1_result_0(reg_WcxrXtYt_1_0), + .bias_0(reg_bc_0), + .output_value_0(o_gt_0), + .stage1_result_1(reg_WcxrXtYt_1_1), + .bias_1(reg_bc_1), + .output_value_1(o_gt_1), + .stage1_result_2(reg_WcxrXtYt_1_2), + .bias_2(reg_bc_2), + .output_value_2(o_gt_2), + .stage1_result_3(reg_WcxrXtYt_1_3), + .bias_3(reg_bc_3), + .output_value_3(o_gt_3), + .stage1_result_4(reg_WcxrXtYt_1_4), + .bias_4(reg_bc_4), + .output_value_4(o_gt_4), + .stage1_result_5(reg_WcxrXtYt_1_5), + .bias_5(reg_bc_5), + .output_value_5(o_gt_5), + .stage1_result_6(reg_WcxrXtYt_1_6), + .bias_6(reg_bc_6), + .output_value_6(o_gt_6), + .stage1_result_7(reg_WcxrXtYt_1_7), + .bias_7(reg_bc_7), + .output_value_7(o_gt_7), + .stage1_result_8(reg_WcxrXtYt_1_8), + .bias_8(reg_bc_8), + .output_value_8(o_gt_8), + .stage1_result_9(reg_WcxrXtYt_1_9), + .bias_9(reg_bc_9), + .output_value_9(o_gt_9), + .stage1_result_10(reg_WcxrXtYt_1_10), + .bias_10(reg_bc_10), + .output_value_10(o_gt_10), + .stage1_result_11(reg_WcxrXtYt_1_11), + .bias_11(reg_bc_11), + .output_value_11(o_gt_11), + .stage1_result_12(reg_WcxrXtYt_1_12), + .bias_12(reg_bc_12), + .output_value_12(o_gt_12), + .stage1_result_13(reg_WcxrXtYt_1_13), + .bias_13(reg_bc_13), + .output_value_13(o_gt_13), + .stage1_result_14(reg_WcxrXtYt_1_14), + .bias_14(reg_bc_14), + .output_value_14(o_gt_14), + .stage1_result_15(reg_WcxrXtYt_1_15), + .bias_15(reg_bc_15), + .output_value_15(o_gt_15), + .o_valid(gt_valid), + .o_ready() +); + +shift_register_group_18_16_6 shift_register_group_18_16_6_eltwisemult ( + .clk(clk), + .enable(enable), + .in_0(o_gt_0), + .out_0(gt_hold_0), + .in_1(o_gt_1), + .out_1(gt_hold_1), + .in_2(o_gt_2), + .out_2(gt_hold_2), + .in_3(o_gt_3), + .out_3(gt_hold_3), + .in_4(o_gt_4), + .out_4(gt_hold_4), + .in_5(o_gt_5), + .out_5(gt_hold_5), + .in_6(o_gt_6), + .out_6(gt_hold_6), + .in_7(o_gt_7), + .out_7(gt_hold_7), + .in_8(o_gt_8), + .out_8(gt_hold_8), + .in_9(o_gt_9), + .out_9(gt_hold_9), + .in_10(o_gt_10), + .out_10(gt_hold_10), + .in_11(o_gt_11), + .out_11(gt_hold_11), + .in_12(o_gt_12), + .out_12(gt_hold_12), + .in_13(o_gt_13), + .out_13(gt_hold_13), + .in_14(o_gt_14), + .out_14(gt_hold_14), + .in_15(o_gt_15), + .out_15(gt_hold_15), + .reset(reset) +); + +elementwise_mult_core_18_18_10_16_1 elementwise_mult_core_18_18_10_16_1_it_gt_mult ( + .clk(clk), + .reset(reset), + .i_valid(forget_gate_valid), + .i_ready(enable), + .i_A_0(o_input_gate_0), + .i_B_0(gt_hold_0), + .o_C_0(o_it_gt_mult_0), + .i_A_1(o_input_gate_1), + .i_B_1(gt_hold_1), + .o_C_1(o_it_gt_mult_1), + .i_A_2(o_input_gate_2), + .i_B_2(gt_hold_2), + .o_C_2(o_it_gt_mult_2), + .i_A_3(o_input_gate_3), + .i_B_3(gt_hold_3), + .o_C_3(o_it_gt_mult_3), + .i_A_4(o_input_gate_4), + .i_B_4(gt_hold_4), + .o_C_4(o_it_gt_mult_4), + .i_A_5(o_input_gate_5), + .i_B_5(gt_hold_5), + .o_C_5(o_it_gt_mult_5), + .i_A_6(o_input_gate_6), + .i_B_6(gt_hold_6), + .o_C_6(o_it_gt_mult_6), + .i_A_7(o_input_gate_7), + .i_B_7(gt_hold_7), + .o_C_7(o_it_gt_mult_7), + .i_A_8(o_input_gate_8), + .i_B_8(gt_hold_8), + .o_C_8(o_it_gt_mult_8), + .i_A_9(o_input_gate_9), + .i_B_9(gt_hold_9), + .o_C_9(o_it_gt_mult_9), + .i_A_10(o_input_gate_10), + .i_B_10(gt_hold_10), + .o_C_10(o_it_gt_mult_10), + .i_A_11(o_input_gate_11), + .i_B_11(gt_hold_11), + .o_C_11(o_it_gt_mult_11), + .i_A_12(o_input_gate_12), + .i_B_12(gt_hold_12), + .o_C_12(o_it_gt_mult_12), + .i_A_13(o_input_gate_13), + .i_B_13(gt_hold_13), + .o_C_13(o_it_gt_mult_13), + .i_A_14(o_input_gate_14), + .i_B_14(gt_hold_14), + .o_C_14(o_it_gt_mult_14), + .i_A_15(o_input_gate_15), + .i_B_15(gt_hold_15), + .o_C_15(o_it_gt_mult_15), + .o_valid(it_gt_mult_valid), + .o_ready() +); + +shift_register_group_18_16_18 shift_register_group_18_16_18_lstm_gate ( + .clk(clk), + .enable(enable), + .in_0(o_Ct_1_0), + .out_0(Ct_1_hold_0), + .in_1(o_Ct_1_1), + .out_1(Ct_1_hold_1), + .in_2(o_Ct_1_2), + .out_2(Ct_1_hold_2), + .in_3(o_Ct_1_3), + .out_3(Ct_1_hold_3), + .in_4(o_Ct_1_4), + .out_4(Ct_1_hold_4), + .in_5(o_Ct_1_5), + .out_5(Ct_1_hold_5), + .in_6(o_Ct_1_6), + .out_6(Ct_1_hold_6), + .in_7(o_Ct_1_7), + .out_7(Ct_1_hold_7), + .in_8(o_Ct_1_8), + .out_8(Ct_1_hold_8), + .in_9(o_Ct_1_9), + .out_9(Ct_1_hold_9), + .in_10(o_Ct_1_10), + .out_10(Ct_1_hold_10), + .in_11(o_Ct_1_11), + .out_11(Ct_1_hold_11), + .in_12(o_Ct_1_12), + .out_12(Ct_1_hold_12), + .in_13(o_Ct_1_13), + .out_13(Ct_1_hold_13), + .in_14(o_Ct_1_14), + .out_14(Ct_1_hold_14), + .in_15(o_Ct_1_15), + .out_15(Ct_1_hold_15), + .reset(reset) +); + +elementwise_mult_core_18_18_10_16_1 elementwise_mult_core_18_18_10_16_1_ft_Ct_1_mult ( + .clk(clk), + .reset(reset), + .i_valid(forget_gate_valid), + .i_ready(enable), + .i_A_0(Ct_1_hold_0), + .i_B_0(o_forget_gate_0), + .o_C_0(o_ft_Ct_1_mult_0), + .i_A_1(Ct_1_hold_1), + .i_B_1(o_forget_gate_1), + .o_C_1(o_ft_Ct_1_mult_1), + .i_A_2(Ct_1_hold_2), + .i_B_2(o_forget_gate_2), + .o_C_2(o_ft_Ct_1_mult_2), + .i_A_3(Ct_1_hold_3), + .i_B_3(o_forget_gate_3), + .o_C_3(o_ft_Ct_1_mult_3), + .i_A_4(Ct_1_hold_4), + .i_B_4(o_forget_gate_4), + .o_C_4(o_ft_Ct_1_mult_4), + .i_A_5(Ct_1_hold_5), + .i_B_5(o_forget_gate_5), + .o_C_5(o_ft_Ct_1_mult_5), + .i_A_6(Ct_1_hold_6), + .i_B_6(o_forget_gate_6), + .o_C_6(o_ft_Ct_1_mult_6), + .i_A_7(Ct_1_hold_7), + .i_B_7(o_forget_gate_7), + .o_C_7(o_ft_Ct_1_mult_7), + .i_A_8(Ct_1_hold_8), + .i_B_8(o_forget_gate_8), + .o_C_8(o_ft_Ct_1_mult_8), + .i_A_9(Ct_1_hold_9), + .i_B_9(o_forget_gate_9), + .o_C_9(o_ft_Ct_1_mult_9), + .i_A_10(Ct_1_hold_10), + .i_B_10(o_forget_gate_10), + .o_C_10(o_ft_Ct_1_mult_10), + .i_A_11(Ct_1_hold_11), + .i_B_11(o_forget_gate_11), + .o_C_11(o_ft_Ct_1_mult_11), + .i_A_12(Ct_1_hold_12), + .i_B_12(o_forget_gate_12), + .o_C_12(o_ft_Ct_1_mult_12), + .i_A_13(Ct_1_hold_13), + .i_B_13(o_forget_gate_13), + .o_C_13(o_ft_Ct_1_mult_13), + .i_A_14(Ct_1_hold_14), + .i_B_14(o_forget_gate_14), + .o_C_14(o_ft_Ct_1_mult_14), + .i_A_15(Ct_1_hold_15), + .i_B_15(o_forget_gate_15), + .o_C_15(o_ft_Ct_1_mult_15), + .o_valid(ft_Ct_1_mult_valid), + .o_ready() +); + +wire eltwise_add_core_valid; +assign eltwise_add_core_valid = ft_Ct_1_mult_valid & it_gt_mult_valid; + +elementwise_add_core_18_18_16 elementwise_add_core_18_18_16_inst_fwydsgmpxu ( + .clk(clk), + .reset(reset), + .i_valid(eltwise_add_core_valid), + .i_ready(enable), + .i_A_0(o_it_gt_mult_0), + .i_B_0(o_ft_Ct_1_mult_0), + .o_C_0(o_ct_0), + .i_A_1(o_it_gt_mult_1), + .i_B_1(o_ft_Ct_1_mult_1), + .o_C_1(o_ct_1), + .i_A_2(o_it_gt_mult_2), + .i_B_2(o_ft_Ct_1_mult_2), + .o_C_2(o_ct_2), + .i_A_3(o_it_gt_mult_3), + .i_B_3(o_ft_Ct_1_mult_3), + .o_C_3(o_ct_3), + .i_A_4(o_it_gt_mult_4), + .i_B_4(o_ft_Ct_1_mult_4), + .o_C_4(o_ct_4), + .i_A_5(o_it_gt_mult_5), + .i_B_5(o_ft_Ct_1_mult_5), + .o_C_5(o_ct_5), + .i_A_6(o_it_gt_mult_6), + .i_B_6(o_ft_Ct_1_mult_6), + .o_C_6(o_ct_6), + .i_A_7(o_it_gt_mult_7), + .i_B_7(o_ft_Ct_1_mult_7), + .o_C_7(o_ct_7), + .i_A_8(o_it_gt_mult_8), + .i_B_8(o_ft_Ct_1_mult_8), + .o_C_8(o_ct_8), + .i_A_9(o_it_gt_mult_9), + .i_B_9(o_ft_Ct_1_mult_9), + .o_C_9(o_ct_9), + .i_A_10(o_it_gt_mult_10), + .i_B_10(o_ft_Ct_1_mult_10), + .o_C_10(o_ct_10), + .i_A_11(o_it_gt_mult_11), + .i_B_11(o_ft_Ct_1_mult_11), + .o_C_11(o_ct_11), + .i_A_12(o_it_gt_mult_12), + .i_B_12(o_ft_Ct_1_mult_12), + .o_C_12(o_ct_12), + .i_A_13(o_it_gt_mult_13), + .i_B_13(o_ft_Ct_1_mult_13), + .o_C_13(o_ct_13), + .i_A_14(o_it_gt_mult_14), + .i_B_14(o_ft_Ct_1_mult_14), + .o_C_14(o_ct_14), + .i_A_15(o_it_gt_mult_15), + .i_B_15(o_ft_Ct_1_mult_15), + .o_C_15(o_ct_15), + .o_valid(ct_valid), + .o_ready() +); + +shift_register_group_18_16_14 shift_register_group_18_16_14_Ct ( + .clk(clk), + .enable(enable), + .in_0(o_ct_0), + .out_0(ct_hold_0), + .in_1(o_ct_1), + .out_1(ct_hold_1), + .in_2(o_ct_2), + .out_2(ct_hold_2), + .in_3(o_ct_3), + .out_3(ct_hold_3), + .in_4(o_ct_4), + .out_4(ct_hold_4), + .in_5(o_ct_5), + .out_5(ct_hold_5), + .in_6(o_ct_6), + .out_6(ct_hold_6), + .in_7(o_ct_7), + .out_7(ct_hold_7), + .in_8(o_ct_8), + .out_8(ct_hold_8), + .in_9(o_ct_9), + .out_9(ct_hold_9), + .in_10(o_ct_10), + .out_10(ct_hold_10), + .in_11(o_ct_11), + .out_11(ct_hold_11), + .in_12(o_ct_12), + .out_12(ct_hold_12), + .in_13(o_ct_13), + .out_13(ct_hold_13), + .in_14(o_ct_14), + .out_14(ct_hold_14), + .in_15(o_ct_15), + .out_15(ct_hold_15), + .reset(reset) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_0 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_0), + .i_x(o_ct_0), + .o_y(o_tanh_0) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_1 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_1), + .i_x(o_ct_1), + .o_y(o_tanh_1) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_2 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_2), + .i_x(o_ct_2), + .o_y(o_tanh_2) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_3 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_3), + .i_x(o_ct_3), + .o_y(o_tanh_3) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_4 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_4), + .i_x(o_ct_4), + .o_y(o_tanh_4) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_5 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_5), + .i_x(o_ct_5), + .o_y(o_tanh_5) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_6 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_6), + .i_x(o_ct_6), + .o_y(o_tanh_6) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_7 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_7), + .i_x(o_ct_7), + .o_y(o_tanh_7) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_8 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_8), + .i_x(o_ct_8), + .o_y(o_tanh_8) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_9 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_9), + .i_x(o_ct_9), + .o_y(o_tanh_9) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_10 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_10), + .i_x(o_ct_10), + .o_y(o_tanh_10) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_11 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_11), + .i_x(o_ct_11), + .o_y(o_tanh_11) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_12 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_12), + .i_x(o_ct_12), + .o_y(o_tanh_12) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_13 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_13), + .i_x(o_ct_13), + .o_y(o_tanh_13) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_14 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_14), + .i_x(o_ct_14), + .o_y(o_tanh_14) +); + +tanh_core_18_18_10_32_1 tanh_core_18_18_10_32_1_inst_15 ( + .clk(clk), + .reset(reset), + .i_valid(ct_valid), + .i_ready(enable), + .o_ready(), + .o_valid(tanh_valid_15), + .i_x(o_ct_15), + .o_y(o_tanh_15) +); + +shift_register_group_18_16_18 shift_register_group_18_16_18_Ct ( + .clk(clk), + .enable(enable), + .in_0(o_output_gate_0), + .out_0(ot_hold_0), + .in_1(o_output_gate_1), + .out_1(ot_hold_1), + .in_2(o_output_gate_2), + .out_2(ot_hold_2), + .in_3(o_output_gate_3), + .out_3(ot_hold_3), + .in_4(o_output_gate_4), + .out_4(ot_hold_4), + .in_5(o_output_gate_5), + .out_5(ot_hold_5), + .in_6(o_output_gate_6), + .out_6(ot_hold_6), + .in_7(o_output_gate_7), + .out_7(ot_hold_7), + .in_8(o_output_gate_8), + .out_8(ot_hold_8), + .in_9(o_output_gate_9), + .out_9(ot_hold_9), + .in_10(o_output_gate_10), + .out_10(ot_hold_10), + .in_11(o_output_gate_11), + .out_11(ot_hold_11), + .in_12(o_output_gate_12), + .out_12(ot_hold_12), + .in_13(o_output_gate_13), + .out_13(ot_hold_13), + .in_14(o_output_gate_14), + .out_14(ot_hold_14), + .in_15(o_output_gate_15), + .out_15(ot_hold_15), + .reset(reset) +); + +elementwise_mult_core_18_18_10_16_1 elementwise_mult_core_18_18_10_16_1_ot_tanh_mult ( + .clk(clk), + .reset(reset), + .i_valid(tanh_valid_0), + .i_ready(enable), + .i_A_0(o_tanh_0), + .i_B_0(ot_hold_0), + .o_C_0(o_mt_0), + .i_A_1(o_tanh_1), + .i_B_1(ot_hold_1), + .o_C_1(o_mt_1), + .i_A_2(o_tanh_2), + .i_B_2(ot_hold_2), + .o_C_2(o_mt_2), + .i_A_3(o_tanh_3), + .i_B_3(ot_hold_3), + .o_C_3(o_mt_3), + .i_A_4(o_tanh_4), + .i_B_4(ot_hold_4), + .o_C_4(o_mt_4), + .i_A_5(o_tanh_5), + .i_B_5(ot_hold_5), + .o_C_5(o_mt_5), + .i_A_6(o_tanh_6), + .i_B_6(ot_hold_6), + .o_C_6(o_mt_6), + .i_A_7(o_tanh_7), + .i_B_7(ot_hold_7), + .o_C_7(o_mt_7), + .i_A_8(o_tanh_8), + .i_B_8(ot_hold_8), + .o_C_8(o_mt_8), + .i_A_9(o_tanh_9), + .i_B_9(ot_hold_9), + .o_C_9(o_mt_9), + .i_A_10(o_tanh_10), + .i_B_10(ot_hold_10), + .o_C_10(o_mt_10), + .i_A_11(o_tanh_11), + .i_B_11(ot_hold_11), + .o_C_11(o_mt_11), + .i_A_12(o_tanh_12), + .i_B_12(ot_hold_12), + .o_C_12(o_mt_12), + .i_A_13(o_tanh_13), + .i_B_13(ot_hold_13), + .o_C_13(o_mt_13), + .i_A_14(o_tanh_14), + .i_B_14(ot_hold_14), + .o_C_14(o_mt_14), + .i_A_15(o_tanh_15), + .i_B_15(ot_hold_15), + .o_C_15(o_mt_15), + .o_valid(mt_valid), + .o_ready() +); + +always @ (posedge clk) begin + if(reset) begin + reg_i_valid <= 1'b0; + reg_o_valid <= 1'b0; + reg_Ct_1_0 <= 0; + reg_WixrXtYt_1_0 <= 0; + reg_Wic_0 <= 0; + reg_bi_0 <= 0; + reg_WfxrXtYt_1_0 <= 0; + reg_Wfc_0 <= 0; + reg_bf_0 <= 0; + reg_WoxrXtYt_1_0 <= 0; + reg_Woc_0 <= 0; + reg_bo_0 <= 0; + reg_WcxrXtYt_1_0 <= 0; + reg_bc_0 <= 0; + reg_out_mt_0 <= 0; + reg_out_ct_0 <= 0; + reg_Ct_1_1 <= 0; + reg_WixrXtYt_1_1 <= 0; + reg_Wic_1 <= 0; + reg_bi_1 <= 0; + reg_WfxrXtYt_1_1 <= 0; + reg_Wfc_1 <= 0; + reg_bf_1 <= 0; + reg_WoxrXtYt_1_1 <= 0; + reg_Woc_1 <= 0; + reg_bo_1 <= 0; + reg_WcxrXtYt_1_1 <= 0; + reg_bc_1 <= 0; + reg_out_mt_1 <= 0; + reg_out_ct_1 <= 0; + reg_Ct_1_2 <= 0; + reg_WixrXtYt_1_2 <= 0; + reg_Wic_2 <= 0; + reg_bi_2 <= 0; + reg_WfxrXtYt_1_2 <= 0; + reg_Wfc_2 <= 0; + reg_bf_2 <= 0; + reg_WoxrXtYt_1_2 <= 0; + reg_Woc_2 <= 0; + reg_bo_2 <= 0; + reg_WcxrXtYt_1_2 <= 0; + reg_bc_2 <= 0; + reg_out_mt_2 <= 0; + reg_out_ct_2 <= 0; + reg_Ct_1_3 <= 0; + reg_WixrXtYt_1_3 <= 0; + reg_Wic_3 <= 0; + reg_bi_3 <= 0; + reg_WfxrXtYt_1_3 <= 0; + reg_Wfc_3 <= 0; + reg_bf_3 <= 0; + reg_WoxrXtYt_1_3 <= 0; + reg_Woc_3 <= 0; + reg_bo_3 <= 0; + reg_WcxrXtYt_1_3 <= 0; + reg_bc_3 <= 0; + reg_out_mt_3 <= 0; + reg_out_ct_3 <= 0; + reg_Ct_1_4 <= 0; + reg_WixrXtYt_1_4 <= 0; + reg_Wic_4 <= 0; + reg_bi_4 <= 0; + reg_WfxrXtYt_1_4 <= 0; + reg_Wfc_4 <= 0; + reg_bf_4 <= 0; + reg_WoxrXtYt_1_4 <= 0; + reg_Woc_4 <= 0; + reg_bo_4 <= 0; + reg_WcxrXtYt_1_4 <= 0; + reg_bc_4 <= 0; + reg_out_mt_4 <= 0; + reg_out_ct_4 <= 0; + reg_Ct_1_5 <= 0; + reg_WixrXtYt_1_5 <= 0; + reg_Wic_5 <= 0; + reg_bi_5 <= 0; + reg_WfxrXtYt_1_5 <= 0; + reg_Wfc_5 <= 0; + reg_bf_5 <= 0; + reg_WoxrXtYt_1_5 <= 0; + reg_Woc_5 <= 0; + reg_bo_5 <= 0; + reg_WcxrXtYt_1_5 <= 0; + reg_bc_5 <= 0; + reg_out_mt_5 <= 0; + reg_out_ct_5 <= 0; + reg_Ct_1_6 <= 0; + reg_WixrXtYt_1_6 <= 0; + reg_Wic_6 <= 0; + reg_bi_6 <= 0; + reg_WfxrXtYt_1_6 <= 0; + reg_Wfc_6 <= 0; + reg_bf_6 <= 0; + reg_WoxrXtYt_1_6 <= 0; + reg_Woc_6 <= 0; + reg_bo_6 <= 0; + reg_WcxrXtYt_1_6 <= 0; + reg_bc_6 <= 0; + reg_out_mt_6 <= 0; + reg_out_ct_6 <= 0; + reg_Ct_1_7 <= 0; + reg_WixrXtYt_1_7 <= 0; + reg_Wic_7 <= 0; + reg_bi_7 <= 0; + reg_WfxrXtYt_1_7 <= 0; + reg_Wfc_7 <= 0; + reg_bf_7 <= 0; + reg_WoxrXtYt_1_7 <= 0; + reg_Woc_7 <= 0; + reg_bo_7 <= 0; + reg_WcxrXtYt_1_7 <= 0; + reg_bc_7 <= 0; + reg_out_mt_7 <= 0; + reg_out_ct_7 <= 0; + reg_Ct_1_8 <= 0; + reg_WixrXtYt_1_8 <= 0; + reg_Wic_8 <= 0; + reg_bi_8 <= 0; + reg_WfxrXtYt_1_8 <= 0; + reg_Wfc_8 <= 0; + reg_bf_8 <= 0; + reg_WoxrXtYt_1_8 <= 0; + reg_Woc_8 <= 0; + reg_bo_8 <= 0; + reg_WcxrXtYt_1_8 <= 0; + reg_bc_8 <= 0; + reg_out_mt_8 <= 0; + reg_out_ct_8 <= 0; + reg_Ct_1_9 <= 0; + reg_WixrXtYt_1_9 <= 0; + reg_Wic_9 <= 0; + reg_bi_9 <= 0; + reg_WfxrXtYt_1_9 <= 0; + reg_Wfc_9 <= 0; + reg_bf_9 <= 0; + reg_WoxrXtYt_1_9 <= 0; + reg_Woc_9 <= 0; + reg_bo_9 <= 0; + reg_WcxrXtYt_1_9 <= 0; + reg_bc_9 <= 0; + reg_out_mt_9 <= 0; + reg_out_ct_9 <= 0; + reg_Ct_1_10 <= 0; + reg_WixrXtYt_1_10 <= 0; + reg_Wic_10 <= 0; + reg_bi_10 <= 0; + reg_WfxrXtYt_1_10 <= 0; + reg_Wfc_10 <= 0; + reg_bf_10 <= 0; + reg_WoxrXtYt_1_10 <= 0; + reg_Woc_10 <= 0; + reg_bo_10 <= 0; + reg_WcxrXtYt_1_10 <= 0; + reg_bc_10 <= 0; + reg_out_mt_10 <= 0; + reg_out_ct_10 <= 0; + reg_Ct_1_11 <= 0; + reg_WixrXtYt_1_11 <= 0; + reg_Wic_11 <= 0; + reg_bi_11 <= 0; + reg_WfxrXtYt_1_11 <= 0; + reg_Wfc_11 <= 0; + reg_bf_11 <= 0; + reg_WoxrXtYt_1_11 <= 0; + reg_Woc_11 <= 0; + reg_bo_11 <= 0; + reg_WcxrXtYt_1_11 <= 0; + reg_bc_11 <= 0; + reg_out_mt_11 <= 0; + reg_out_ct_11 <= 0; + reg_Ct_1_12 <= 0; + reg_WixrXtYt_1_12 <= 0; + reg_Wic_12 <= 0; + reg_bi_12 <= 0; + reg_WfxrXtYt_1_12 <= 0; + reg_Wfc_12 <= 0; + reg_bf_12 <= 0; + reg_WoxrXtYt_1_12 <= 0; + reg_Woc_12 <= 0; + reg_bo_12 <= 0; + reg_WcxrXtYt_1_12 <= 0; + reg_bc_12 <= 0; + reg_out_mt_12 <= 0; + reg_out_ct_12 <= 0; + reg_Ct_1_13 <= 0; + reg_WixrXtYt_1_13 <= 0; + reg_Wic_13 <= 0; + reg_bi_13 <= 0; + reg_WfxrXtYt_1_13 <= 0; + reg_Wfc_13 <= 0; + reg_bf_13 <= 0; + reg_WoxrXtYt_1_13 <= 0; + reg_Woc_13 <= 0; + reg_bo_13 <= 0; + reg_WcxrXtYt_1_13 <= 0; + reg_bc_13 <= 0; + reg_out_mt_13 <= 0; + reg_out_ct_13 <= 0; + reg_Ct_1_14 <= 0; + reg_WixrXtYt_1_14 <= 0; + reg_Wic_14 <= 0; + reg_bi_14 <= 0; + reg_WfxrXtYt_1_14 <= 0; + reg_Wfc_14 <= 0; + reg_bf_14 <= 0; + reg_WoxrXtYt_1_14 <= 0; + reg_Woc_14 <= 0; + reg_bo_14 <= 0; + reg_WcxrXtYt_1_14 <= 0; + reg_bc_14 <= 0; + reg_out_mt_14 <= 0; + reg_out_ct_14 <= 0; + reg_Ct_1_15 <= 0; + reg_WixrXtYt_1_15 <= 0; + reg_Wic_15 <= 0; + reg_bi_15 <= 0; + reg_WfxrXtYt_1_15 <= 0; + reg_Wfc_15 <= 0; + reg_bf_15 <= 0; + reg_WoxrXtYt_1_15 <= 0; + reg_Woc_15 <= 0; + reg_bo_15 <= 0; + reg_WcxrXtYt_1_15 <= 0; + reg_bc_15 <= 0; + reg_out_mt_15 <= 0; + reg_out_ct_15 <= 0; + end else if (enable) begin + reg_i_valid <= i_valid; + reg_o_valid <= mt_valid; + reg_Ct_1_0 <= Ct_1_0; + reg_WixrXtYt_1_0 <= WixrXtYt_1_0; + reg_Wic_0 <= Wic_0; + reg_bi_0 <= bi_0; + reg_WfxrXtYt_1_0 <= WfxrXtYt_1_0; + reg_Wfc_0 <= Wfc_0; + reg_bf_0 <= bf_0; + reg_WoxrXtYt_1_0 <= WoxrXtYt_1_0; + reg_Woc_0 <= Woc_0; + reg_bo_0 <= bo_0; + reg_WcxrXtYt_1_0 <= WcxrXtYt_1_0; + reg_bc_0 <= bc_0; + reg_out_mt_0 <= o_mt_0; + reg_out_ct_0 <= ct_hold_0; + reg_Ct_1_1 <= Ct_1_1; + reg_WixrXtYt_1_1 <= WixrXtYt_1_1; + reg_Wic_1 <= Wic_1; + reg_bi_1 <= bi_1; + reg_WfxrXtYt_1_1 <= WfxrXtYt_1_1; + reg_Wfc_1 <= Wfc_1; + reg_bf_1 <= bf_1; + reg_WoxrXtYt_1_1 <= WoxrXtYt_1_1; + reg_Woc_1 <= Woc_1; + reg_bo_1 <= bo_1; + reg_WcxrXtYt_1_1 <= WcxrXtYt_1_1; + reg_bc_1 <= bc_1; + reg_out_mt_1 <= o_mt_1; + reg_out_ct_1 <= ct_hold_1; + reg_Ct_1_2 <= Ct_1_2; + reg_WixrXtYt_1_2 <= WixrXtYt_1_2; + reg_Wic_2 <= Wic_2; + reg_bi_2 <= bi_2; + reg_WfxrXtYt_1_2 <= WfxrXtYt_1_2; + reg_Wfc_2 <= Wfc_2; + reg_bf_2 <= bf_2; + reg_WoxrXtYt_1_2 <= WoxrXtYt_1_2; + reg_Woc_2 <= Woc_2; + reg_bo_2 <= bo_2; + reg_WcxrXtYt_1_2 <= WcxrXtYt_1_2; + reg_bc_2 <= bc_2; + reg_out_mt_2 <= o_mt_2; + reg_out_ct_2 <= ct_hold_2; + reg_Ct_1_3 <= Ct_1_3; + reg_WixrXtYt_1_3 <= WixrXtYt_1_3; + reg_Wic_3 <= Wic_3; + reg_bi_3 <= bi_3; + reg_WfxrXtYt_1_3 <= WfxrXtYt_1_3; + reg_Wfc_3 <= Wfc_3; + reg_bf_3 <= bf_3; + reg_WoxrXtYt_1_3 <= WoxrXtYt_1_3; + reg_Woc_3 <= Woc_3; + reg_bo_3 <= bo_3; + reg_WcxrXtYt_1_3 <= WcxrXtYt_1_3; + reg_bc_3 <= bc_3; + reg_out_mt_3 <= o_mt_3; + reg_out_ct_3 <= ct_hold_3; + reg_Ct_1_4 <= Ct_1_4; + reg_WixrXtYt_1_4 <= WixrXtYt_1_4; + reg_Wic_4 <= Wic_4; + reg_bi_4 <= bi_4; + reg_WfxrXtYt_1_4 <= WfxrXtYt_1_4; + reg_Wfc_4 <= Wfc_4; + reg_bf_4 <= bf_4; + reg_WoxrXtYt_1_4 <= WoxrXtYt_1_4; + reg_Woc_4 <= Woc_4; + reg_bo_4 <= bo_4; + reg_WcxrXtYt_1_4 <= WcxrXtYt_1_4; + reg_bc_4 <= bc_4; + reg_out_mt_4 <= o_mt_4; + reg_out_ct_4 <= ct_hold_4; + reg_Ct_1_5 <= Ct_1_5; + reg_WixrXtYt_1_5 <= WixrXtYt_1_5; + reg_Wic_5 <= Wic_5; + reg_bi_5 <= bi_5; + reg_WfxrXtYt_1_5 <= WfxrXtYt_1_5; + reg_Wfc_5 <= Wfc_5; + reg_bf_5 <= bf_5; + reg_WoxrXtYt_1_5 <= WoxrXtYt_1_5; + reg_Woc_5 <= Woc_5; + reg_bo_5 <= bo_5; + reg_WcxrXtYt_1_5 <= WcxrXtYt_1_5; + reg_bc_5 <= bc_5; + reg_out_mt_5 <= o_mt_5; + reg_out_ct_5 <= ct_hold_5; + reg_Ct_1_6 <= Ct_1_6; + reg_WixrXtYt_1_6 <= WixrXtYt_1_6; + reg_Wic_6 <= Wic_6; + reg_bi_6 <= bi_6; + reg_WfxrXtYt_1_6 <= WfxrXtYt_1_6; + reg_Wfc_6 <= Wfc_6; + reg_bf_6 <= bf_6; + reg_WoxrXtYt_1_6 <= WoxrXtYt_1_6; + reg_Woc_6 <= Woc_6; + reg_bo_6 <= bo_6; + reg_WcxrXtYt_1_6 <= WcxrXtYt_1_6; + reg_bc_6 <= bc_6; + reg_out_mt_6 <= o_mt_6; + reg_out_ct_6 <= ct_hold_6; + reg_Ct_1_7 <= Ct_1_7; + reg_WixrXtYt_1_7 <= WixrXtYt_1_7; + reg_Wic_7 <= Wic_7; + reg_bi_7 <= bi_7; + reg_WfxrXtYt_1_7 <= WfxrXtYt_1_7; + reg_Wfc_7 <= Wfc_7; + reg_bf_7 <= bf_7; + reg_WoxrXtYt_1_7 <= WoxrXtYt_1_7; + reg_Woc_7 <= Woc_7; + reg_bo_7 <= bo_7; + reg_WcxrXtYt_1_7 <= WcxrXtYt_1_7; + reg_bc_7 <= bc_7; + reg_out_mt_7 <= o_mt_7; + reg_out_ct_7 <= ct_hold_7; + reg_Ct_1_8 <= Ct_1_8; + reg_WixrXtYt_1_8 <= WixrXtYt_1_8; + reg_Wic_8 <= Wic_8; + reg_bi_8 <= bi_8; + reg_WfxrXtYt_1_8 <= WfxrXtYt_1_8; + reg_Wfc_8 <= Wfc_8; + reg_bf_8 <= bf_8; + reg_WoxrXtYt_1_8 <= WoxrXtYt_1_8; + reg_Woc_8 <= Woc_8; + reg_bo_8 <= bo_8; + reg_WcxrXtYt_1_8 <= WcxrXtYt_1_8; + reg_bc_8 <= bc_8; + reg_out_mt_8 <= o_mt_8; + reg_out_ct_8 <= ct_hold_8; + reg_Ct_1_9 <= Ct_1_9; + reg_WixrXtYt_1_9 <= WixrXtYt_1_9; + reg_Wic_9 <= Wic_9; + reg_bi_9 <= bi_9; + reg_WfxrXtYt_1_9 <= WfxrXtYt_1_9; + reg_Wfc_9 <= Wfc_9; + reg_bf_9 <= bf_9; + reg_WoxrXtYt_1_9 <= WoxrXtYt_1_9; + reg_Woc_9 <= Woc_9; + reg_bo_9 <= bo_9; + reg_WcxrXtYt_1_9 <= WcxrXtYt_1_9; + reg_bc_9 <= bc_9; + reg_out_mt_9 <= o_mt_9; + reg_out_ct_9 <= ct_hold_9; + reg_Ct_1_10 <= Ct_1_10; + reg_WixrXtYt_1_10 <= WixrXtYt_1_10; + reg_Wic_10 <= Wic_10; + reg_bi_10 <= bi_10; + reg_WfxrXtYt_1_10 <= WfxrXtYt_1_10; + reg_Wfc_10 <= Wfc_10; + reg_bf_10 <= bf_10; + reg_WoxrXtYt_1_10 <= WoxrXtYt_1_10; + reg_Woc_10 <= Woc_10; + reg_bo_10 <= bo_10; + reg_WcxrXtYt_1_10 <= WcxrXtYt_1_10; + reg_bc_10 <= bc_10; + reg_out_mt_10 <= o_mt_10; + reg_out_ct_10 <= ct_hold_10; + reg_Ct_1_11 <= Ct_1_11; + reg_WixrXtYt_1_11 <= WixrXtYt_1_11; + reg_Wic_11 <= Wic_11; + reg_bi_11 <= bi_11; + reg_WfxrXtYt_1_11 <= WfxrXtYt_1_11; + reg_Wfc_11 <= Wfc_11; + reg_bf_11 <= bf_11; + reg_WoxrXtYt_1_11 <= WoxrXtYt_1_11; + reg_Woc_11 <= Woc_11; + reg_bo_11 <= bo_11; + reg_WcxrXtYt_1_11 <= WcxrXtYt_1_11; + reg_bc_11 <= bc_11; + reg_out_mt_11 <= o_mt_11; + reg_out_ct_11 <= ct_hold_11; + reg_Ct_1_12 <= Ct_1_12; + reg_WixrXtYt_1_12 <= WixrXtYt_1_12; + reg_Wic_12 <= Wic_12; + reg_bi_12 <= bi_12; + reg_WfxrXtYt_1_12 <= WfxrXtYt_1_12; + reg_Wfc_12 <= Wfc_12; + reg_bf_12 <= bf_12; + reg_WoxrXtYt_1_12 <= WoxrXtYt_1_12; + reg_Woc_12 <= Woc_12; + reg_bo_12 <= bo_12; + reg_WcxrXtYt_1_12 <= WcxrXtYt_1_12; + reg_bc_12 <= bc_12; + reg_out_mt_12 <= o_mt_12; + reg_out_ct_12 <= ct_hold_12; + reg_Ct_1_13 <= Ct_1_13; + reg_WixrXtYt_1_13 <= WixrXtYt_1_13; + reg_Wic_13 <= Wic_13; + reg_bi_13 <= bi_13; + reg_WfxrXtYt_1_13 <= WfxrXtYt_1_13; + reg_Wfc_13 <= Wfc_13; + reg_bf_13 <= bf_13; + reg_WoxrXtYt_1_13 <= WoxrXtYt_1_13; + reg_Woc_13 <= Woc_13; + reg_bo_13 <= bo_13; + reg_WcxrXtYt_1_13 <= WcxrXtYt_1_13; + reg_bc_13 <= bc_13; + reg_out_mt_13 <= o_mt_13; + reg_out_ct_13 <= ct_hold_13; + reg_Ct_1_14 <= Ct_1_14; + reg_WixrXtYt_1_14 <= WixrXtYt_1_14; + reg_Wic_14 <= Wic_14; + reg_bi_14 <= bi_14; + reg_WfxrXtYt_1_14 <= WfxrXtYt_1_14; + reg_Wfc_14 <= Wfc_14; + reg_bf_14 <= bf_14; + reg_WoxrXtYt_1_14 <= WoxrXtYt_1_14; + reg_Woc_14 <= Woc_14; + reg_bo_14 <= bo_14; + reg_WcxrXtYt_1_14 <= WcxrXtYt_1_14; + reg_bc_14 <= bc_14; + reg_out_mt_14 <= o_mt_14; + reg_out_ct_14 <= ct_hold_14; + reg_Ct_1_15 <= Ct_1_15; + reg_WixrXtYt_1_15 <= WixrXtYt_1_15; + reg_Wic_15 <= Wic_15; + reg_bi_15 <= bi_15; + reg_WfxrXtYt_1_15 <= WfxrXtYt_1_15; + reg_Wfc_15 <= Wfc_15; + reg_bf_15 <= bf_15; + reg_WoxrXtYt_1_15 <= WoxrXtYt_1_15; + reg_Woc_15 <= Woc_15; + reg_bo_15 <= bo_15; + reg_WcxrXtYt_1_15 <= WcxrXtYt_1_15; + reg_bc_15 <= bc_15; + reg_out_mt_15 <= o_mt_15; + reg_out_ct_15 <= ct_hold_15; + end +end +assign out_mt_0 = reg_out_mt_0; +assign out_ct_0 = reg_out_ct_0; +assign out_mt_1 = reg_out_mt_1; +assign out_ct_1 = reg_out_ct_1; +assign out_mt_2 = reg_out_mt_2; +assign out_ct_2 = reg_out_ct_2; +assign out_mt_3 = reg_out_mt_3; +assign out_ct_3 = reg_out_ct_3; +assign out_mt_4 = reg_out_mt_4; +assign out_ct_4 = reg_out_ct_4; +assign out_mt_5 = reg_out_mt_5; +assign out_ct_5 = reg_out_ct_5; +assign out_mt_6 = reg_out_mt_6; +assign out_ct_6 = reg_out_ct_6; +assign out_mt_7 = reg_out_mt_7; +assign out_ct_7 = reg_out_ct_7; +assign out_mt_8 = reg_out_mt_8; +assign out_ct_8 = reg_out_ct_8; +assign out_mt_9 = reg_out_mt_9; +assign out_ct_9 = reg_out_ct_9; +assign out_mt_10 = reg_out_mt_10; +assign out_ct_10 = reg_out_ct_10; +assign out_mt_11 = reg_out_mt_11; +assign out_ct_11 = reg_out_ct_11; +assign out_mt_12 = reg_out_mt_12; +assign out_ct_12 = reg_out_ct_12; +assign out_mt_13 = reg_out_mt_13; +assign out_ct_13 = reg_out_ct_13; +assign out_mt_14 = reg_out_mt_14; +assign out_ct_14 = reg_out_ct_14; +assign out_mt_15 = reg_out_mt_15; +assign out_ct_15 = reg_out_ct_15; +assign o_valid = reg_o_valid; +assign o_ready = enable; +endmodule + +module lstm_gate_18_10_16_1 ( + input clk, + input reset, + input i_ready, + input i_valid, + input [17:0] stage1_result_0, + input [17:0] weight_0, + input [17:0] Ct_1_0, + input [17:0] bias_0, + output [17:0] gate_output_0, + input [17:0] stage1_result_1, + input [17:0] weight_1, + input [17:0] Ct_1_1, + input [17:0] bias_1, + output [17:0] gate_output_1, + input [17:0] stage1_result_2, + input [17:0] weight_2, + input [17:0] Ct_1_2, + input [17:0] bias_2, + output [17:0] gate_output_2, + input [17:0] stage1_result_3, + input [17:0] weight_3, + input [17:0] Ct_1_3, + input [17:0] bias_3, + output [17:0] gate_output_3, + input [17:0] stage1_result_4, + input [17:0] weight_4, + input [17:0] Ct_1_4, + input [17:0] bias_4, + output [17:0] gate_output_4, + input [17:0] stage1_result_5, + input [17:0] weight_5, + input [17:0] Ct_1_5, + input [17:0] bias_5, + output [17:0] gate_output_5, + input [17:0] stage1_result_6, + input [17:0] weight_6, + input [17:0] Ct_1_6, + input [17:0] bias_6, + output [17:0] gate_output_6, + input [17:0] stage1_result_7, + input [17:0] weight_7, + input [17:0] Ct_1_7, + input [17:0] bias_7, + output [17:0] gate_output_7, + input [17:0] stage1_result_8, + input [17:0] weight_8, + input [17:0] Ct_1_8, + input [17:0] bias_8, + output [17:0] gate_output_8, + input [17:0] stage1_result_9, + input [17:0] weight_9, + input [17:0] Ct_1_9, + input [17:0] bias_9, + output [17:0] gate_output_9, + input [17:0] stage1_result_10, + input [17:0] weight_10, + input [17:0] Ct_1_10, + input [17:0] bias_10, + output [17:0] gate_output_10, + input [17:0] stage1_result_11, + input [17:0] weight_11, + input [17:0] Ct_1_11, + input [17:0] bias_11, + output [17:0] gate_output_11, + input [17:0] stage1_result_12, + input [17:0] weight_12, + input [17:0] Ct_1_12, + input [17:0] bias_12, + output [17:0] gate_output_12, + input [17:0] stage1_result_13, + input [17:0] weight_13, + input [17:0] Ct_1_13, + input [17:0] bias_13, + output [17:0] gate_output_13, + input [17:0] stage1_result_14, + input [17:0] weight_14, + input [17:0] Ct_1_14, + input [17:0] bias_14, + output [17:0] gate_output_14, + input [17:0] stage1_result_15, + input [17:0] weight_15, + input [17:0] Ct_1_15, + input [17:0] bias_15, + output [17:0] gate_output_15, + output o_valid, + output o_ready +); + +wire mult_valid, add0_valid, add1_valid, add2_valid; +wire mult_ready, add0_ready, add1_ready, add2_ready; +wire sigmoid_valid_0, sigmoid_ready_0; +wire [17:0] o_mult_0; +wire [17:0] o_add0_0; +wire [17:0] o_add1_0; +wire [17:0] add1_hold_0; +wire [17:0] o_add2_0; +wire [17:0] o_sigmoid_0; +wire sigmoid_valid_1, sigmoid_ready_1; +wire [17:0] o_mult_1; +wire [17:0] o_add0_1; +wire [17:0] o_add1_1; +wire [17:0] add1_hold_1; +wire [17:0] o_add2_1; +wire [17:0] o_sigmoid_1; +wire sigmoid_valid_2, sigmoid_ready_2; +wire [17:0] o_mult_2; +wire [17:0] o_add0_2; +wire [17:0] o_add1_2; +wire [17:0] add1_hold_2; +wire [17:0] o_add2_2; +wire [17:0] o_sigmoid_2; +wire sigmoid_valid_3, sigmoid_ready_3; +wire [17:0] o_mult_3; +wire [17:0] o_add0_3; +wire [17:0] o_add1_3; +wire [17:0] add1_hold_3; +wire [17:0] o_add2_3; +wire [17:0] o_sigmoid_3; +wire sigmoid_valid_4, sigmoid_ready_4; +wire [17:0] o_mult_4; +wire [17:0] o_add0_4; +wire [17:0] o_add1_4; +wire [17:0] add1_hold_4; +wire [17:0] o_add2_4; +wire [17:0] o_sigmoid_4; +wire sigmoid_valid_5, sigmoid_ready_5; +wire [17:0] o_mult_5; +wire [17:0] o_add0_5; +wire [17:0] o_add1_5; +wire [17:0] add1_hold_5; +wire [17:0] o_add2_5; +wire [17:0] o_sigmoid_5; +wire sigmoid_valid_6, sigmoid_ready_6; +wire [17:0] o_mult_6; +wire [17:0] o_add0_6; +wire [17:0] o_add1_6; +wire [17:0] add1_hold_6; +wire [17:0] o_add2_6; +wire [17:0] o_sigmoid_6; +wire sigmoid_valid_7, sigmoid_ready_7; +wire [17:0] o_mult_7; +wire [17:0] o_add0_7; +wire [17:0] o_add1_7; +wire [17:0] add1_hold_7; +wire [17:0] o_add2_7; +wire [17:0] o_sigmoid_7; +wire sigmoid_valid_8, sigmoid_ready_8; +wire [17:0] o_mult_8; +wire [17:0] o_add0_8; +wire [17:0] o_add1_8; +wire [17:0] add1_hold_8; +wire [17:0] o_add2_8; +wire [17:0] o_sigmoid_8; +wire sigmoid_valid_9, sigmoid_ready_9; +wire [17:0] o_mult_9; +wire [17:0] o_add0_9; +wire [17:0] o_add1_9; +wire [17:0] add1_hold_9; +wire [17:0] o_add2_9; +wire [17:0] o_sigmoid_9; +wire sigmoid_valid_10, sigmoid_ready_10; +wire [17:0] o_mult_10; +wire [17:0] o_add0_10; +wire [17:0] o_add1_10; +wire [17:0] add1_hold_10; +wire [17:0] o_add2_10; +wire [17:0] o_sigmoid_10; +wire sigmoid_valid_11, sigmoid_ready_11; +wire [17:0] o_mult_11; +wire [17:0] o_add0_11; +wire [17:0] o_add1_11; +wire [17:0] add1_hold_11; +wire [17:0] o_add2_11; +wire [17:0] o_sigmoid_11; +wire sigmoid_valid_12, sigmoid_ready_12; +wire [17:0] o_mult_12; +wire [17:0] o_add0_12; +wire [17:0] o_add1_12; +wire [17:0] add1_hold_12; +wire [17:0] o_add2_12; +wire [17:0] o_sigmoid_12; +wire sigmoid_valid_13, sigmoid_ready_13; +wire [17:0] o_mult_13; +wire [17:0] o_add0_13; +wire [17:0] o_add1_13; +wire [17:0] add1_hold_13; +wire [17:0] o_add2_13; +wire [17:0] o_sigmoid_13; +wire sigmoid_valid_14, sigmoid_ready_14; +wire [17:0] o_mult_14; +wire [17:0] o_add0_14; +wire [17:0] o_add1_14; +wire [17:0] add1_hold_14; +wire [17:0] o_add2_14; +wire [17:0] o_sigmoid_14; +wire sigmoid_valid_15, sigmoid_ready_15; +wire [17:0] o_mult_15; +wire [17:0] o_add0_15; +wire [17:0] o_add1_15; +wire [17:0] add1_hold_15; +wire [17:0] o_add2_15; +wire [17:0] o_sigmoid_15; +wire enable; +assign enable = i_ready; + +elementwise_mult_core_18_18_10_16_1 elementwise_mult_core_18_18_10_16_1_mult ( + .clk(clk), + .reset(reset), + .i_valid(i_valid), + .i_ready(add2_ready), + .i_A_0(weight_0), + .i_B_0(Ct_1_0), + .o_C_0(o_mult_0), + .i_A_1(weight_1), + .i_B_1(Ct_1_1), + .o_C_1(o_mult_1), + .i_A_2(weight_2), + .i_B_2(Ct_1_2), + .o_C_2(o_mult_2), + .i_A_3(weight_3), + .i_B_3(Ct_1_3), + .o_C_3(o_mult_3), + .i_A_4(weight_4), + .i_B_4(Ct_1_4), + .o_C_4(o_mult_4), + .i_A_5(weight_5), + .i_B_5(Ct_1_5), + .o_C_5(o_mult_5), + .i_A_6(weight_6), + .i_B_6(Ct_1_6), + .o_C_6(o_mult_6), + .i_A_7(weight_7), + .i_B_7(Ct_1_7), + .o_C_7(o_mult_7), + .i_A_8(weight_8), + .i_B_8(Ct_1_8), + .o_C_8(o_mult_8), + .i_A_9(weight_9), + .i_B_9(Ct_1_9), + .o_C_9(o_mult_9), + .i_A_10(weight_10), + .i_B_10(Ct_1_10), + .o_C_10(o_mult_10), + .i_A_11(weight_11), + .i_B_11(Ct_1_11), + .o_C_11(o_mult_11), + .i_A_12(weight_12), + .i_B_12(Ct_1_12), + .o_C_12(o_mult_12), + .i_A_13(weight_13), + .i_B_13(Ct_1_13), + .o_C_13(o_mult_13), + .i_A_14(weight_14), + .i_B_14(Ct_1_14), + .o_C_14(o_mult_14), + .i_A_15(weight_15), + .i_B_15(Ct_1_15), + .o_C_15(o_mult_15), + .o_valid(mult_valid), + .o_ready(mult_ready) +); + +elementwise_add_core_18_18_16 elementwise_add_core_18_18_16_add_1 ( + .clk(clk), + .reset(reset), + .i_valid(i_valid), + .i_ready(add2_ready), + .i_A_0(stage1_result_0), + .i_B_0(bias_0), + .o_C_0(o_add1_0), + .i_A_1(stage1_result_1), + .i_B_1(bias_1), + .o_C_1(o_add1_1), + .i_A_2(stage1_result_2), + .i_B_2(bias_2), + .o_C_2(o_add1_2), + .i_A_3(stage1_result_3), + .i_B_3(bias_3), + .o_C_3(o_add1_3), + .i_A_4(stage1_result_4), + .i_B_4(bias_4), + .o_C_4(o_add1_4), + .i_A_5(stage1_result_5), + .i_B_5(bias_5), + .o_C_5(o_add1_5), + .i_A_6(stage1_result_6), + .i_B_6(bias_6), + .o_C_6(o_add1_6), + .i_A_7(stage1_result_7), + .i_B_7(bias_7), + .o_C_7(o_add1_7), + .i_A_8(stage1_result_8), + .i_B_8(bias_8), + .o_C_8(o_add1_8), + .i_A_9(stage1_result_9), + .i_B_9(bias_9), + .o_C_9(o_add1_9), + .i_A_10(stage1_result_10), + .i_B_10(bias_10), + .o_C_10(o_add1_10), + .i_A_11(stage1_result_11), + .i_B_11(bias_11), + .o_C_11(o_add1_11), + .i_A_12(stage1_result_12), + .i_B_12(bias_12), + .o_C_12(o_add1_12), + .i_A_13(stage1_result_13), + .i_B_13(bias_13), + .o_C_13(o_add1_13), + .i_A_14(stage1_result_14), + .i_B_14(bias_14), + .o_C_14(o_add1_14), + .i_A_15(stage1_result_15), + .i_B_15(bias_15), + .o_C_15(o_add1_15), + .o_valid(add1_valid), + .o_ready(add1_ready) +); + +shift_register_group_18_16_10 shift_register_group_18_16_10_Ct ( + .clk(clk), + .enable(enable), + .in_0(o_add1_0), + .out_0(add1_hold_0), + .in_1(o_add1_1), + .out_1(add1_hold_1), + .in_2(o_add1_2), + .out_2(add1_hold_2), + .in_3(o_add1_3), + .out_3(add1_hold_3), + .in_4(o_add1_4), + .out_4(add1_hold_4), + .in_5(o_add1_5), + .out_5(add1_hold_5), + .in_6(o_add1_6), + .out_6(add1_hold_6), + .in_7(o_add1_7), + .out_7(add1_hold_7), + .in_8(o_add1_8), + .out_8(add1_hold_8), + .in_9(o_add1_9), + .out_9(add1_hold_9), + .in_10(o_add1_10), + .out_10(add1_hold_10), + .in_11(o_add1_11), + .out_11(add1_hold_11), + .in_12(o_add1_12), + .out_12(add1_hold_12), + .in_13(o_add1_13), + .out_13(add1_hold_13), + .in_14(o_add1_14), + .out_14(add1_hold_14), + .in_15(o_add1_15), + .out_15(add1_hold_15), + .reset(reset) +); + +elementwise_add_core_18_18_16 elementwise_add_core_18_18_16_add_2 ( + .clk(clk), + .reset(reset), + .i_valid(mult_valid), + .i_ready(sigmoid_ready_0), + .i_A_0(add1_hold_0), + .i_B_0(o_mult_0), + .o_C_0(o_add2_0), + .i_A_1(add1_hold_1), + .i_B_1(o_mult_1), + .o_C_1(o_add2_1), + .i_A_2(add1_hold_2), + .i_B_2(o_mult_2), + .o_C_2(o_add2_2), + .i_A_3(add1_hold_3), + .i_B_3(o_mult_3), + .o_C_3(o_add2_3), + .i_A_4(add1_hold_4), + .i_B_4(o_mult_4), + .o_C_4(o_add2_4), + .i_A_5(add1_hold_5), + .i_B_5(o_mult_5), + .o_C_5(o_add2_5), + .i_A_6(add1_hold_6), + .i_B_6(o_mult_6), + .o_C_6(o_add2_6), + .i_A_7(add1_hold_7), + .i_B_7(o_mult_7), + .o_C_7(o_add2_7), + .i_A_8(add1_hold_8), + .i_B_8(o_mult_8), + .o_C_8(o_add2_8), + .i_A_9(add1_hold_9), + .i_B_9(o_mult_9), + .o_C_9(o_add2_9), + .i_A_10(add1_hold_10), + .i_B_10(o_mult_10), + .o_C_10(o_add2_10), + .i_A_11(add1_hold_11), + .i_B_11(o_mult_11), + .o_C_11(o_add2_11), + .i_A_12(add1_hold_12), + .i_B_12(o_mult_12), + .o_C_12(o_add2_12), + .i_A_13(add1_hold_13), + .i_B_13(o_mult_13), + .o_C_13(o_add2_13), + .i_A_14(add1_hold_14), + .i_B_14(o_mult_14), + .o_C_14(o_add2_14), + .i_A_15(add1_hold_15), + .i_B_15(o_mult_15), + .o_C_15(o_add2_15), + .o_valid(add2_valid), + .o_ready(add2_ready) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_0 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_0), + .o_valid(sigmoid_valid_0), + .i_x(o_add2_0), + .o_y(o_sigmoid_0) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_1 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_1), + .o_valid(sigmoid_valid_1), + .i_x(o_add2_1), + .o_y(o_sigmoid_1) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_2 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_2), + .o_valid(sigmoid_valid_2), + .i_x(o_add2_2), + .o_y(o_sigmoid_2) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_3 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_3), + .o_valid(sigmoid_valid_3), + .i_x(o_add2_3), + .o_y(o_sigmoid_3) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_4 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_4), + .o_valid(sigmoid_valid_4), + .i_x(o_add2_4), + .o_y(o_sigmoid_4) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_5 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_5), + .o_valid(sigmoid_valid_5), + .i_x(o_add2_5), + .o_y(o_sigmoid_5) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_6 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_6), + .o_valid(sigmoid_valid_6), + .i_x(o_add2_6), + .o_y(o_sigmoid_6) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_7 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_7), + .o_valid(sigmoid_valid_7), + .i_x(o_add2_7), + .o_y(o_sigmoid_7) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_8 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_8), + .o_valid(sigmoid_valid_8), + .i_x(o_add2_8), + .o_y(o_sigmoid_8) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_9 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_9), + .o_valid(sigmoid_valid_9), + .i_x(o_add2_9), + .o_y(o_sigmoid_9) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_10 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_10), + .o_valid(sigmoid_valid_10), + .i_x(o_add2_10), + .o_y(o_sigmoid_10) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_11 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_11), + .o_valid(sigmoid_valid_11), + .i_x(o_add2_11), + .o_y(o_sigmoid_11) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_12 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_12), + .o_valid(sigmoid_valid_12), + .i_x(o_add2_12), + .o_y(o_sigmoid_12) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_13 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_13), + .o_valid(sigmoid_valid_13), + .i_x(o_add2_13), + .o_y(o_sigmoid_13) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_14 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_14), + .o_valid(sigmoid_valid_14), + .i_x(o_add2_14), + .o_y(o_sigmoid_14) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_15 ( + .clk(clk), + .reset(reset), + .i_valid(add2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_15), + .o_valid(sigmoid_valid_15), + .i_x(o_add2_15), + .o_y(o_sigmoid_15) +); + +assign o_ready = mult_ready; +assign o_valid = sigmoid_valid_0 & i_ready; +assign gate_output_0 = o_sigmoid_0; +assign gate_output_1 = o_sigmoid_1; +assign gate_output_2 = o_sigmoid_2; +assign gate_output_3 = o_sigmoid_3; +assign gate_output_4 = o_sigmoid_4; +assign gate_output_5 = o_sigmoid_5; +assign gate_output_6 = o_sigmoid_6; +assign gate_output_7 = o_sigmoid_7; +assign gate_output_8 = o_sigmoid_8; +assign gate_output_9 = o_sigmoid_9; +assign gate_output_10 = o_sigmoid_10; +assign gate_output_11 = o_sigmoid_11; +assign gate_output_12 = o_sigmoid_12; +assign gate_output_13 = o_sigmoid_13; +assign gate_output_14 = o_sigmoid_14; +assign gate_output_15 = o_sigmoid_15; + +endmodule + +module shift_register_group_18_16_10 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input reset +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +endmodule + +module shift_register_unit_18_18 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +reg [17:0] shift_registers_1; +reg [17:0] shift_registers_2; +reg [17:0] shift_registers_3; +reg [17:0] shift_registers_4; +reg [17:0] shift_registers_5; +reg [17:0] shift_registers_6; +reg [17:0] shift_registers_7; +reg [17:0] shift_registers_8; +reg [17:0] shift_registers_9; +reg [17:0] shift_registers_10; +reg [17:0] shift_registers_11; +reg [17:0] shift_registers_12; +reg [17:0] shift_registers_13; +reg [17:0] shift_registers_14; +reg [17:0] shift_registers_15; +reg [17:0] shift_registers_16; +reg [17:0] shift_registers_17; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + shift_registers_1 <= 18'd0; + shift_registers_2 <= 18'd0; + shift_registers_3 <= 18'd0; + shift_registers_4 <= 18'd0; + shift_registers_5 <= 18'd0; + shift_registers_6 <= 18'd0; + shift_registers_7 <= 18'd0; + shift_registers_8 <= 18'd0; + shift_registers_9 <= 18'd0; + shift_registers_10 <= 18'd0; + shift_registers_11 <= 18'd0; + shift_registers_12 <= 18'd0; + shift_registers_13 <= 18'd0; + shift_registers_14 <= 18'd0; + shift_registers_15 <= 18'd0; + shift_registers_16 <= 18'd0; + shift_registers_17 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + shift_registers_3 <= shift_registers_2; + shift_registers_4 <= shift_registers_3; + shift_registers_5 <= shift_registers_4; + shift_registers_6 <= shift_registers_5; + shift_registers_7 <= shift_registers_6; + shift_registers_8 <= shift_registers_7; + shift_registers_9 <= shift_registers_8; + shift_registers_10 <= shift_registers_9; + shift_registers_11 <= shift_registers_10; + shift_registers_12 <= shift_registers_11; + shift_registers_13 <= shift_registers_12; + shift_registers_14 <= shift_registers_13; + shift_registers_15 <= shift_registers_14; + shift_registers_16 <= shift_registers_15; + shift_registers_17 <= shift_registers_16; + end +end + +assign out = shift_registers_17; + +endmodule + +module sigmoid_core_18_18_10_32_1 ( + input clk, + input reset, + input i_valid, + input i_ready, + output o_ready, + output o_valid, + input [17:0] i_x, + output [17:0] o_y +); + +reg [12:0] k_list_0; +reg [12:0] b_list_0; +reg [12:0] k_list_1; +reg [12:0] b_list_1; +reg [12:0] k_list_2; +reg [12:0] b_list_2; +reg [12:0] k_list_3; +reg [12:0] b_list_3; +reg [12:0] k_list_4; +reg [12:0] b_list_4; +reg [12:0] k_list_5; +reg [12:0] b_list_5; +reg [12:0] k_list_6; +reg [12:0] b_list_6; +reg [12:0] k_list_7; +reg [12:0] b_list_7; +reg [12:0] k_list_8; +reg [12:0] b_list_8; +reg [12:0] k_list_9; +reg [12:0] b_list_9; +reg [12:0] k_list_10; +reg [12:0] b_list_10; +reg [12:0] k_list_11; +reg [12:0] b_list_11; +reg [12:0] k_list_12; +reg [12:0] b_list_12; +reg [12:0] k_list_13; +reg [12:0] b_list_13; +reg [12:0] k_list_14; +reg [12:0] b_list_14; +reg [12:0] k_list_15; +reg [12:0] b_list_15; +reg [12:0] k_list_16; +reg [12:0] b_list_16; +reg [12:0] k_list_17; +reg [12:0] b_list_17; +reg [12:0] k_list_18; +reg [12:0] b_list_18; +reg [12:0] k_list_19; +reg [12:0] b_list_19; +reg [12:0] k_list_20; +reg [12:0] b_list_20; +reg [12:0] k_list_21; +reg [12:0] b_list_21; +reg [12:0] k_list_22; +reg [12:0] b_list_22; +reg [12:0] k_list_23; +reg [12:0] b_list_23; +reg [12:0] k_list_24; +reg [12:0] b_list_24; +reg [12:0] k_list_25; +reg [12:0] b_list_25; +reg [12:0] k_list_26; +reg [12:0] b_list_26; +reg [12:0] k_list_27; +reg [12:0] b_list_27; +reg [12:0] k_list_28; +reg [12:0] b_list_28; +reg [12:0] k_list_29; +reg [12:0] b_list_29; +reg [12:0] k_list_30; +reg [12:0] b_list_30; +reg [12:0] k_list_31; +reg [12:0] b_list_31; + +always @ (posedge clk) begin + k_list_0 <= 13'b0000111111101; + k_list_1 <= 13'b0000111101110; + k_list_2 <= 13'b0000111010001; + k_list_3 <= 13'b0000110101001; + k_list_4 <= 13'b0000101111011; + k_list_5 <= 13'b0000101001010; + k_list_6 <= 13'b0000100011010; + k_list_7 <= 13'b0000011101100; + k_list_8 <= 13'b0000011000011; + k_list_9 <= 13'b0000010100000; + k_list_10 <= 13'b0000010000001; + k_list_11 <= 13'b0000001101000; + k_list_12 <= 13'b0000001010011; + k_list_13 <= 13'b0000001000010; + k_list_14 <= 13'b0000000110100; + k_list_15 <= 13'b0000000101001; + k_list_16 <= 13'b0000000100000; + k_list_17 <= 13'b0000000011001; + k_list_18 <= 13'b0000000010100; + k_list_19 <= 13'b0000000001111; + k_list_20 <= 13'b0000000001100; + k_list_21 <= 13'b0000000001001; + k_list_22 <= 13'b0000000000111; + k_list_23 <= 13'b0000000000110; + k_list_24 <= 13'b0000000000100; + k_list_25 <= 13'b0000000000011; + k_list_26 <= 13'b0000000000011; + k_list_27 <= 13'b0000000000010; + k_list_28 <= 13'b0000000000010; + k_list_29 <= 13'b0000000000001; + k_list_30 <= 13'b0000000000001; + k_list_31 <= 13'b0000000000001; + b_list_0 <= 13'b0010000000000; + b_list_1 <= 13'b0010000000100; + b_list_2 <= 13'b0010000010010; + b_list_3 <= 13'b0010000110000; + b_list_4 <= 13'b0010001011110; + b_list_5 <= 13'b0010010011011; + b_list_6 <= 13'b0010011100100; + b_list_7 <= 13'b0010100110011; + b_list_8 <= 13'b0010110000101; + b_list_9 <= 13'b0010111010101; + b_list_10 <= 13'b0011000100010; + b_list_11 <= 13'b0011001101000; + b_list_12 <= 13'b0011010100111; + b_list_13 <= 13'b0011011011110; + b_list_14 <= 13'b0011100001110; + b_list_15 <= 13'b0011100111000; + b_list_16 <= 13'b0011101011011; + b_list_17 <= 13'b0011101111000; + b_list_18 <= 13'b0011110010001; + b_list_19 <= 13'b0011110100101; + b_list_20 <= 13'b0011110110110; + b_list_21 <= 13'b0011111000100; + b_list_22 <= 13'b0011111001111; + b_list_23 <= 13'b0011111011001; + b_list_24 <= 13'b0011111100000; + b_list_25 <= 13'b0011111100110; + b_list_26 <= 13'b0011111101011; + b_list_27 <= 13'b0011111101111; + b_list_28 <= 13'b0011111110011; + b_list_29 <= 13'b0011111110101; + b_list_30 <= 13'b0011111110111; + b_list_31 <= 13'b0011111111001; +end +reg [17:0] x; +reg [17:0] y; +reg valid_x, valid_y, enable; +wire [4:0] sel_k_b; + +wire abs_valid, round_valid, mult_valid, compute_valid; +reg [12:0] mac_ay, mac_az; +reg is_x_negative; +wire is_x_negative_hold; +wire [17:0] abs_x; +wire [17:0] x_partial; +reg [31:0] y_compute; +wire [31:0] x_k_plus_b; +wire [31:0] y_rounded; + +assign x_partial = (abs_x >> 8); +assign sel_k_b = x_partial [4:0]; + +reg [12:0] selected_k, selected_b; +always @ (*) begin + if (sel_k_b == 0) begin + selected_k <= k_list_0; + selected_b <= b_list_0; + end else if (sel_k_b == 1) begin + selected_k <= k_list_1; + selected_b <= b_list_1; + end else if (sel_k_b == 2) begin + selected_k <= k_list_2; + selected_b <= b_list_2; + end else if (sel_k_b == 3) begin + selected_k <= k_list_3; + selected_b <= b_list_3; + end else if (sel_k_b == 4) begin + selected_k <= k_list_4; + selected_b <= b_list_4; + end else if (sel_k_b == 5) begin + selected_k <= k_list_5; + selected_b <= b_list_5; + end else if (sel_k_b == 6) begin + selected_k <= k_list_6; + selected_b <= b_list_6; + end else if (sel_k_b == 7) begin + selected_k <= k_list_7; + selected_b <= b_list_7; + end else if (sel_k_b == 8) begin + selected_k <= k_list_8; + selected_b <= b_list_8; + end else if (sel_k_b == 9) begin + selected_k <= k_list_9; + selected_b <= b_list_9; + end else if (sel_k_b == 10) begin + selected_k <= k_list_10; + selected_b <= b_list_10; + end else if (sel_k_b == 11) begin + selected_k <= k_list_11; + selected_b <= b_list_11; + end else if (sel_k_b == 12) begin + selected_k <= k_list_12; + selected_b <= b_list_12; + end else if (sel_k_b == 13) begin + selected_k <= k_list_13; + selected_b <= b_list_13; + end else if (sel_k_b == 14) begin + selected_k <= k_list_14; + selected_b <= b_list_14; + end else if (sel_k_b == 15) begin + selected_k <= k_list_15; + selected_b <= b_list_15; + end else if (sel_k_b == 16) begin + selected_k <= k_list_16; + selected_b <= b_list_16; + end else if (sel_k_b == 17) begin + selected_k <= k_list_17; + selected_b <= b_list_17; + end else if (sel_k_b == 18) begin + selected_k <= k_list_18; + selected_b <= b_list_18; + end else if (sel_k_b == 19) begin + selected_k <= k_list_19; + selected_b <= b_list_19; + end else if (sel_k_b == 20) begin + selected_k <= k_list_20; + selected_b <= b_list_20; + end else if (sel_k_b == 21) begin + selected_k <= k_list_21; + selected_b <= b_list_21; + end else if (sel_k_b == 22) begin + selected_k <= k_list_22; + selected_b <= b_list_22; + end else if (sel_k_b == 23) begin + selected_k <= k_list_23; + selected_b <= b_list_23; + end else if (sel_k_b == 24) begin + selected_k <= k_list_24; + selected_b <= b_list_24; + end else if (sel_k_b == 25) begin + selected_k <= k_list_25; + selected_b <= b_list_25; + end else if (sel_k_b == 26) begin + selected_k <= k_list_26; + selected_b <= b_list_26; + end else if (sel_k_b == 27) begin + selected_k <= k_list_27; + selected_b <= b_list_27; + end else if (sel_k_b == 28) begin + selected_k <= k_list_28; + selected_b <= b_list_28; + end else if (sel_k_b == 29) begin + selected_k <= k_list_29; + selected_b <= b_list_29; + end else if (sel_k_b == 30) begin + selected_k <= k_list_30; + selected_b <= b_list_30; + end else begin + selected_k <= k_list_31; + selected_b <= b_list_31; + end +end +always @ (*) begin + if (abs_x >= 8192) begin + mac_ay <= 0; + mac_az <= 12'd2048; + end else begin + mac_ay <= selected_k; + mac_az <= (selected_b << 10); + end +end +dsp_signed_mac_18_13_23_32 dsp_signed_mac_18_13_23_32_inst_gkywjkcsad ( + .clk(clk), + .reset(reset), + .ena(enable), + .ax(abs_x), + .ay(mac_ay), + .az(mac_az), + .i_valid(abs_valid), + .o_valid(compute_valid), + .resulta(x_k_plus_b) +); + +shift_register_unit_1_3 shift_register_unit_1_3_inst_icexwwdsai ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(is_x_negative), + .out(is_x_negative_hold) +); + +abs_unit_18 abs_unit_18_inst_dzithtowcp ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(valid_x), + .in(x), + .o_valid(abs_valid), + .out(abs_x) +); + +fp_rounding_unit_1_32_11 fp_rounding_unit_1_32_11_inst_tyjhjdnwdm ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(compute_valid), + .in(y_compute), + .o_valid(round_valid), + .out(y_rounded) +); + +always @ (*) begin + if (is_x_negative_hold) + y_compute = 2048 - x_k_plus_b; + else + y_compute = x_k_plus_b; + enable = i_ready; +end +always @ (posedge clk) begin + if (reset) begin + valid_x <= 1'b0; + valid_y <= 1'b0; + x <= 0; + y <= 0; + end else if (enable) begin + valid_x <= i_valid; + valid_y <= round_valid; + x <= i_x; + if (x[17] == 1'b1) + is_x_negative <= 1'b1; + else + is_x_negative <= 1'b0; + y <= y_rounded[17:0]; + end +end + +assign o_y = y; +assign o_ready = i_ready; +assign o_valid = valid_y & i_ready; + +endmodule + +module dsp_signed_mac_18_13_23_32 ( + input clk, + input reset, + input ena, + input i_valid, + input [17:0] ax, + input [12:0] ay, + input [12:0] az, + output o_valid, + output [31:0] resulta +); + +reg [17:0] reg_ax; +reg [12:0] reg_ay; +reg [12:0] reg_az; +reg [31:0] reg_res; +reg valid_r, valid_rr; +always @ (posedge clk) begin + if (reset) begin + reg_ax <= 0; + reg_ay <= 0; + reg_az <= 0; + reg_res <= 0; + valid_r <= 0; + valid_rr <= 0; + end else begin + reg_ax <= ax; + reg_ay <= ay; + reg_az <= az; + reg_res <= (reg_ax * reg_ay) + reg_az; + valid_r <= ena; + valid_rr <= valid_r; + end +end + +assign resulta = reg_res; +assign o_valid = valid_rr; +endmodule + +module abs_unit_18 ( + input clk, + input reset, + input enable, + input i_valid, + input [17:0] in, + output o_valid, + output [17:0] out +); + +reg [17:0] abs_result; + +always @ (*) begin + if (in[17] == 1'b1) + abs_result = -in; + else + abs_result = in; +end + +reg valid_reg; +reg [17:0] out_reg; +always @ (posedge clk) begin + if (reset) begin + valid_reg <= 1'b0; + out_reg <= 0; + end else if (enable) begin + valid_reg <= i_valid; + out_reg <= abs_result; + end +end +assign out = out_reg; +assign o_valid = valid_reg; +endmodule + +module fp_rounding_unit_1_32_11 ( + input clk, + input reset, + input enable, + input i_valid, + input [31:0] in, + output [31:0] out, + output o_valid +); + +reg [31:0] rounded_result; +reg [31:0] floor; +reg [31:0] ceil; +reg is_ceil; +reg floor_ceil_valid; + +always @ (*) begin + if (is_ceil) begin + rounded_result = ceil; + end else begin + rounded_result = floor; + end +end + +reg valid_reg; +reg [31:0] out_reg; +always @ (posedge clk) begin + if (reset) begin + is_ceil <= 1'b0; + floor_ceil_valid <= 1'b0; + valid_reg <= 1'b0; + floor <= 0; + ceil <= 0; + out_reg <= 0; + end else if (enable) begin + is_ceil <= in[10]; + floor <= in >>> 11; + ceil <= (in >>> 11) + 1; + floor_ceil_valid <= i_valid; + out_reg <= rounded_result; + valid_reg <= floor_ceil_valid; + end +end + +assign o_valid = valid_reg; + +assign out = out_reg; + +endmodule + +module output_activation_18_10_16_1 ( + input clk, + input reset, + input i_ready, + input i_valid, + input [17:0] stage1_result_0, + input [17:0] bias_0, + output [17:0] output_value_0, + input [17:0] stage1_result_1, + input [17:0] bias_1, + output [17:0] output_value_1, + input [17:0] stage1_result_2, + input [17:0] bias_2, + output [17:0] output_value_2, + input [17:0] stage1_result_3, + input [17:0] bias_3, + output [17:0] output_value_3, + input [17:0] stage1_result_4, + input [17:0] bias_4, + output [17:0] output_value_4, + input [17:0] stage1_result_5, + input [17:0] bias_5, + output [17:0] output_value_5, + input [17:0] stage1_result_6, + input [17:0] bias_6, + output [17:0] output_value_6, + input [17:0] stage1_result_7, + input [17:0] bias_7, + output [17:0] output_value_7, + input [17:0] stage1_result_8, + input [17:0] bias_8, + output [17:0] output_value_8, + input [17:0] stage1_result_9, + input [17:0] bias_9, + output [17:0] output_value_9, + input [17:0] stage1_result_10, + input [17:0] bias_10, + output [17:0] output_value_10, + input [17:0] stage1_result_11, + input [17:0] bias_11, + output [17:0] output_value_11, + input [17:0] stage1_result_12, + input [17:0] bias_12, + output [17:0] output_value_12, + input [17:0] stage1_result_13, + input [17:0] bias_13, + output [17:0] output_value_13, + input [17:0] stage1_result_14, + input [17:0] bias_14, + output [17:0] output_value_14, + input [17:0] stage1_result_15, + input [17:0] bias_15, + output [17:0] output_value_15, + output o_valid, + output o_ready +); + +wire adder1_valid, adder2_valid, adder1_ready, adder2_ready; +wire sigmoid_valid_0, sigmoid_ready_0; +wire [17:0] o_add2_0; +wire [17:0] o_sigmoid_0; +wire sigmoid_valid_1, sigmoid_ready_1; +wire [17:0] o_add2_1; +wire [17:0] o_sigmoid_1; +wire sigmoid_valid_2, sigmoid_ready_2; +wire [17:0] o_add2_2; +wire [17:0] o_sigmoid_2; +wire sigmoid_valid_3, sigmoid_ready_3; +wire [17:0] o_add2_3; +wire [17:0] o_sigmoid_3; +wire sigmoid_valid_4, sigmoid_ready_4; +wire [17:0] o_add2_4; +wire [17:0] o_sigmoid_4; +wire sigmoid_valid_5, sigmoid_ready_5; +wire [17:0] o_add2_5; +wire [17:0] o_sigmoid_5; +wire sigmoid_valid_6, sigmoid_ready_6; +wire [17:0] o_add2_6; +wire [17:0] o_sigmoid_6; +wire sigmoid_valid_7, sigmoid_ready_7; +wire [17:0] o_add2_7; +wire [17:0] o_sigmoid_7; +wire sigmoid_valid_8, sigmoid_ready_8; +wire [17:0] o_add2_8; +wire [17:0] o_sigmoid_8; +wire sigmoid_valid_9, sigmoid_ready_9; +wire [17:0] o_add2_9; +wire [17:0] o_sigmoid_9; +wire sigmoid_valid_10, sigmoid_ready_10; +wire [17:0] o_add2_10; +wire [17:0] o_sigmoid_10; +wire sigmoid_valid_11, sigmoid_ready_11; +wire [17:0] o_add2_11; +wire [17:0] o_sigmoid_11; +wire sigmoid_valid_12, sigmoid_ready_12; +wire [17:0] o_add2_12; +wire [17:0] o_sigmoid_12; +wire sigmoid_valid_13, sigmoid_ready_13; +wire [17:0] o_add2_13; +wire [17:0] o_sigmoid_13; +wire sigmoid_valid_14, sigmoid_ready_14; +wire [17:0] o_add2_14; +wire [17:0] o_sigmoid_14; +wire sigmoid_valid_15, sigmoid_ready_15; +wire [17:0] o_add2_15; +wire [17:0] o_sigmoid_15; +elementwise_add_core_18_18_16 elementwise_add_core_18_18_16_inst_tpinscevyj ( + .clk(clk), + .reset(reset), + .i_valid(i_valid), + .i_ready(sigmoid_ready_0), + .i_A_0(stage1_result_0), + .i_B_0(bias_0), + .o_C_0(o_add2_0), + .i_A_1(stage1_result_1), + .i_B_1(bias_1), + .o_C_1(o_add2_1), + .i_A_2(stage1_result_2), + .i_B_2(bias_2), + .o_C_2(o_add2_2), + .i_A_3(stage1_result_3), + .i_B_3(bias_3), + .o_C_3(o_add2_3), + .i_A_4(stage1_result_4), + .i_B_4(bias_4), + .o_C_4(o_add2_4), + .i_A_5(stage1_result_5), + .i_B_5(bias_5), + .o_C_5(o_add2_5), + .i_A_6(stage1_result_6), + .i_B_6(bias_6), + .o_C_6(o_add2_6), + .i_A_7(stage1_result_7), + .i_B_7(bias_7), + .o_C_7(o_add2_7), + .i_A_8(stage1_result_8), + .i_B_8(bias_8), + .o_C_8(o_add2_8), + .i_A_9(stage1_result_9), + .i_B_9(bias_9), + .o_C_9(o_add2_9), + .i_A_10(stage1_result_10), + .i_B_10(bias_10), + .o_C_10(o_add2_10), + .i_A_11(stage1_result_11), + .i_B_11(bias_11), + .o_C_11(o_add2_11), + .i_A_12(stage1_result_12), + .i_B_12(bias_12), + .o_C_12(o_add2_12), + .i_A_13(stage1_result_13), + .i_B_13(bias_13), + .o_C_13(o_add2_13), + .i_A_14(stage1_result_14), + .i_B_14(bias_14), + .o_C_14(o_add2_14), + .i_A_15(stage1_result_15), + .i_B_15(bias_15), + .o_C_15(o_add2_15), + .o_valid(adder2_valid), + .o_ready(adder2_ready) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_0 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_0), + .o_valid(sigmoid_valid_0), + .i_x(o_add2_0), + .o_y(o_sigmoid_0) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_1 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_1), + .o_valid(sigmoid_valid_1), + .i_x(o_add2_1), + .o_y(o_sigmoid_1) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_2 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_2), + .o_valid(sigmoid_valid_2), + .i_x(o_add2_2), + .o_y(o_sigmoid_2) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_3 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_3), + .o_valid(sigmoid_valid_3), + .i_x(o_add2_3), + .o_y(o_sigmoid_3) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_4 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_4), + .o_valid(sigmoid_valid_4), + .i_x(o_add2_4), + .o_y(o_sigmoid_4) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_5 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_5), + .o_valid(sigmoid_valid_5), + .i_x(o_add2_5), + .o_y(o_sigmoid_5) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_6 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_6), + .o_valid(sigmoid_valid_6), + .i_x(o_add2_6), + .o_y(o_sigmoid_6) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_7 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_7), + .o_valid(sigmoid_valid_7), + .i_x(o_add2_7), + .o_y(o_sigmoid_7) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_8 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_8), + .o_valid(sigmoid_valid_8), + .i_x(o_add2_8), + .o_y(o_sigmoid_8) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_9 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_9), + .o_valid(sigmoid_valid_9), + .i_x(o_add2_9), + .o_y(o_sigmoid_9) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_10 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_10), + .o_valid(sigmoid_valid_10), + .i_x(o_add2_10), + .o_y(o_sigmoid_10) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_11 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_11), + .o_valid(sigmoid_valid_11), + .i_x(o_add2_11), + .o_y(o_sigmoid_11) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_12 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_12), + .o_valid(sigmoid_valid_12), + .i_x(o_add2_12), + .o_y(o_sigmoid_12) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_13 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_13), + .o_valid(sigmoid_valid_13), + .i_x(o_add2_13), + .o_y(o_sigmoid_13) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_14 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_14), + .o_valid(sigmoid_valid_14), + .i_x(o_add2_14), + .o_y(o_sigmoid_14) +); + +sigmoid_core_18_18_10_32_1 sigmoid_core_18_18_10_32_1_inst_15 ( + .clk(clk), + .reset(reset), + .i_valid(adder2_valid), + .i_ready(i_ready), + .o_ready(sigmoid_ready_15), + .o_valid(sigmoid_valid_15), + .i_x(o_add2_15), + .o_y(o_sigmoid_15) +); + +assign o_ready = adder2_ready; +assign o_valid = sigmoid_valid_0 & i_ready; +assign output_value_0 = o_sigmoid_0; +assign output_value_1 = o_sigmoid_1; +assign output_value_2 = o_sigmoid_2; +assign output_value_3 = o_sigmoid_3; +assign output_value_4 = o_sigmoid_4; +assign output_value_5 = o_sigmoid_5; +assign output_value_6 = o_sigmoid_6; +assign output_value_7 = o_sigmoid_7; +assign output_value_8 = o_sigmoid_8; +assign output_value_9 = o_sigmoid_9; +assign output_value_10 = o_sigmoid_10; +assign output_value_11 = o_sigmoid_11; +assign output_value_12 = o_sigmoid_12; +assign output_value_13 = o_sigmoid_13; +assign output_value_14 = o_sigmoid_14; +assign output_value_15 = o_sigmoid_15; + +endmodule + +module shift_register_group_18_16_6 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input reset +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_6 shift_register_unit_18_6_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +endmodule + +module shift_register_unit_18_6 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +reg [17:0] shift_registers_1; +reg [17:0] shift_registers_2; +reg [17:0] shift_registers_3; +reg [17:0] shift_registers_4; +reg [17:0] shift_registers_5; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + shift_registers_1 <= 18'd0; + shift_registers_2 <= 18'd0; + shift_registers_3 <= 18'd0; + shift_registers_4 <= 18'd0; + shift_registers_5 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + shift_registers_3 <= shift_registers_2; + shift_registers_4 <= shift_registers_3; + shift_registers_5 <= shift_registers_4; + end +end + +assign out = shift_registers_5; + +endmodule + +module elementwise_mult_core_18_18_10_16_1 ( + input clk, + input reset, + input i_valid, + input i_ready, + input [17:0] i_A_0, + input [17:0] i_B_0, + output [17:0] o_C_0, + input [17:0] i_A_1, + input [17:0] i_B_1, + output [17:0] o_C_1, + input [17:0] i_A_2, + input [17:0] i_B_2, + output [17:0] o_C_2, + input [17:0] i_A_3, + input [17:0] i_B_3, + output [17:0] o_C_3, + input [17:0] i_A_4, + input [17:0] i_B_4, + output [17:0] o_C_4, + input [17:0] i_A_5, + input [17:0] i_B_5, + output [17:0] o_C_5, + input [17:0] i_A_6, + input [17:0] i_B_6, + output [17:0] o_C_6, + input [17:0] i_A_7, + input [17:0] i_B_7, + output [17:0] o_C_7, + input [17:0] i_A_8, + input [17:0] i_B_8, + output [17:0] o_C_8, + input [17:0] i_A_9, + input [17:0] i_B_9, + output [17:0] o_C_9, + input [17:0] i_A_10, + input [17:0] i_B_10, + output [17:0] o_C_10, + input [17:0] i_A_11, + input [17:0] i_B_11, + output [17:0] o_C_11, + input [17:0] i_A_12, + input [17:0] i_B_12, + output [17:0] o_C_12, + input [17:0] i_A_13, + input [17:0] i_B_13, + output [17:0] o_C_13, + input [17:0] i_A_14, + input [17:0] i_B_14, + output [17:0] o_C_14, + input [17:0] i_A_15, + input [17:0] i_B_15, + output [17:0] o_C_15, + output o_valid, + output o_ready +); + +// Store inputs and outputs in registers +reg [17:0] reg_A_0; +reg [17:0] reg_B_0; +wire [17:0] reg_C_0; +reg [17:0] reg_A_1; +reg [17:0] reg_B_1; +wire [17:0] reg_C_1; +reg [17:0] reg_A_2; +reg [17:0] reg_B_2; +wire [17:0] reg_C_2; +reg [17:0] reg_A_3; +reg [17:0] reg_B_3; +wire [17:0] reg_C_3; +reg [17:0] reg_A_4; +reg [17:0] reg_B_4; +wire [17:0] reg_C_4; +reg [17:0] reg_A_5; +reg [17:0] reg_B_5; +wire [17:0] reg_C_5; +reg [17:0] reg_A_6; +reg [17:0] reg_B_6; +wire [17:0] reg_C_6; +reg [17:0] reg_A_7; +reg [17:0] reg_B_7; +wire [17:0] reg_C_7; +reg [17:0] reg_A_8; +reg [17:0] reg_B_8; +wire [17:0] reg_C_8; +reg [17:0] reg_A_9; +reg [17:0] reg_B_9; +wire [17:0] reg_C_9; +reg [17:0] reg_A_10; +reg [17:0] reg_B_10; +wire [17:0] reg_C_10; +reg [17:0] reg_A_11; +reg [17:0] reg_B_11; +wire [17:0] reg_C_11; +reg [17:0] reg_A_12; +reg [17:0] reg_B_12; +wire [17:0] reg_C_12; +reg [17:0] reg_A_13; +reg [17:0] reg_B_13; +wire [17:0] reg_C_13; +reg [17:0] reg_A_14; +reg [17:0] reg_B_14; +wire [17:0] reg_C_14; +reg [17:0] reg_A_15; +reg [17:0] reg_B_15; +wire [17:0] reg_C_15; + +reg valid_A_B; +wire valid_C; +wire enable; +assign enable = i_ready; + +wire mult_valid_0; +wire round_valid_0; +wire [36:0] mult_C_0; +wire [36:0] rounded_C_0; +wire mult_valid_1; +wire round_valid_1; +wire [36:0] mult_C_1; +wire [36:0] rounded_C_1; +wire mult_valid_2; +wire round_valid_2; +wire [36:0] mult_C_2; +wire [36:0] rounded_C_2; +wire mult_valid_3; +wire round_valid_3; +wire [36:0] mult_C_3; +wire [36:0] rounded_C_3; +wire mult_valid_4; +wire round_valid_4; +wire [36:0] mult_C_4; +wire [36:0] rounded_C_4; +wire mult_valid_5; +wire round_valid_5; +wire [36:0] mult_C_5; +wire [36:0] rounded_C_5; +wire mult_valid_6; +wire round_valid_6; +wire [36:0] mult_C_6; +wire [36:0] rounded_C_6; +wire mult_valid_7; +wire round_valid_7; +wire [36:0] mult_C_7; +wire [36:0] rounded_C_7; +wire mult_valid_8; +wire round_valid_8; +wire [36:0] mult_C_8; +wire [36:0] rounded_C_8; +wire mult_valid_9; +wire round_valid_9; +wire [36:0] mult_C_9; +wire [36:0] rounded_C_9; +wire mult_valid_10; +wire round_valid_10; +wire [36:0] mult_C_10; +wire [36:0] rounded_C_10; +wire mult_valid_11; +wire round_valid_11; +wire [36:0] mult_C_11; +wire [36:0] rounded_C_11; +wire mult_valid_12; +wire round_valid_12; +wire [36:0] mult_C_12; +wire [36:0] rounded_C_12; +wire mult_valid_13; +wire round_valid_13; +wire [36:0] mult_C_13; +wire [36:0] rounded_C_13; +wire mult_valid_14; +wire round_valid_14; +wire [36:0] mult_C_14; +wire [36:0] rounded_C_14; +wire mult_valid_15; +wire round_valid_15; +wire [36:0] mult_C_15; +wire [36:0] rounded_C_15; + +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst0 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_0), + .ay(reg_B_0), + .bx(reg_A_1), + .by(reg_B_1), + .o_valid(mult_valid_0), + .resulta(mult_C_0), + .resultb(mult_C_1) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst2 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_2), + .ay(reg_B_2), + .bx(reg_A_3), + .by(reg_B_3), + .o_valid(mult_valid_2), + .resulta(mult_C_2), + .resultb(mult_C_3) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst4 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_4), + .ay(reg_B_4), + .bx(reg_A_5), + .by(reg_B_5), + .o_valid(mult_valid_4), + .resulta(mult_C_4), + .resultb(mult_C_5) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst6 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_6), + .ay(reg_B_6), + .bx(reg_A_7), + .by(reg_B_7), + .o_valid(mult_valid_6), + .resulta(mult_C_6), + .resultb(mult_C_7) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst8 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_8), + .ay(reg_B_8), + .bx(reg_A_9), + .by(reg_B_9), + .o_valid(mult_valid_8), + .resulta(mult_C_8), + .resultb(mult_C_9) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst10 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_10), + .ay(reg_B_10), + .bx(reg_A_11), + .by(reg_B_11), + .o_valid(mult_valid_10), + .resulta(mult_C_10), + .resultb(mult_C_11) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst12 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_12), + .ay(reg_B_12), + .bx(reg_A_13), + .by(reg_B_13), + .o_valid(mult_valid_12), + .resulta(mult_C_12), + .resultb(mult_C_13) +); +dsp_signed_mult_18x18_unit_18_18_1 dsp_signed_mult_18x18_unit_18_18_1_inst14 ( + .clk(clk), + .reset(reset), + .ena(enable), + .i_valid(valid_A_B), + .ax(reg_A_14), + .ay(reg_B_14), + .bx(reg_A_15), + .by(reg_B_15), + .o_valid(mult_valid_14), + .resulta(mult_C_14), + .resultb(mult_C_15) +); +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_0), + .in(mult_C_0), + .o_valid(round_valid_0), + .out(rounded_C_0) +); +assign reg_C_0 = rounded_C_0[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_1), + .in(mult_C_1), + .o_valid(round_valid_1), + .out(rounded_C_1) +); +assign reg_C_1 = rounded_C_1[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_2), + .in(mult_C_2), + .o_valid(round_valid_2), + .out(rounded_C_2) +); +assign reg_C_2 = rounded_C_2[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_3), + .in(mult_C_3), + .o_valid(round_valid_3), + .out(rounded_C_3) +); +assign reg_C_3 = rounded_C_3[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_4), + .in(mult_C_4), + .o_valid(round_valid_4), + .out(rounded_C_4) +); +assign reg_C_4 = rounded_C_4[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_5), + .in(mult_C_5), + .o_valid(round_valid_5), + .out(rounded_C_5) +); +assign reg_C_5 = rounded_C_5[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_6), + .in(mult_C_6), + .o_valid(round_valid_6), + .out(rounded_C_6) +); +assign reg_C_6 = rounded_C_6[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_7), + .in(mult_C_7), + .o_valid(round_valid_7), + .out(rounded_C_7) +); +assign reg_C_7 = rounded_C_7[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_8), + .in(mult_C_8), + .o_valid(round_valid_8), + .out(rounded_C_8) +); +assign reg_C_8 = rounded_C_8[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_9), + .in(mult_C_9), + .o_valid(round_valid_9), + .out(rounded_C_9) +); +assign reg_C_9 = rounded_C_9[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_10), + .in(mult_C_10), + .o_valid(round_valid_10), + .out(rounded_C_10) +); +assign reg_C_10 = rounded_C_10[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_11), + .in(mult_C_11), + .o_valid(round_valid_11), + .out(rounded_C_11) +); +assign reg_C_11 = rounded_C_11[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_12), + .in(mult_C_12), + .o_valid(round_valid_12), + .out(rounded_C_12) +); +assign reg_C_12 = rounded_C_12[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_13), + .in(mult_C_13), + .o_valid(round_valid_13), + .out(rounded_C_13) +); +assign reg_C_13 = rounded_C_13[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_14), + .in(mult_C_14), + .o_valid(round_valid_14), + .out(rounded_C_14) +); +assign reg_C_14 = rounded_C_14[17:0]; +fp_rounding_unit_1_37_10 fp_rounding_unit_1_37_10_inst15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(mult_valid_15), + .in(mult_C_15), + .o_valid(round_valid_15), + .out(rounded_C_15) +); +assign reg_C_15 = rounded_C_15[17:0]; +always @ (posedge clk) begin + if (reset) begin + valid_A_B <= 1'b0; + reg_A_0 <= 0; + reg_B_0 <= 0; + reg_A_1 <= 0; + reg_B_1 <= 0; + reg_A_2 <= 0; + reg_B_2 <= 0; + reg_A_3 <= 0; + reg_B_3 <= 0; + reg_A_4 <= 0; + reg_B_4 <= 0; + reg_A_5 <= 0; + reg_B_5 <= 0; + reg_A_6 <= 0; + reg_B_6 <= 0; + reg_A_7 <= 0; + reg_B_7 <= 0; + reg_A_8 <= 0; + reg_B_8 <= 0; + reg_A_9 <= 0; + reg_B_9 <= 0; + reg_A_10 <= 0; + reg_B_10 <= 0; + reg_A_11 <= 0; + reg_B_11 <= 0; + reg_A_12 <= 0; + reg_B_12 <= 0; + reg_A_13 <= 0; + reg_B_13 <= 0; + reg_A_14 <= 0; + reg_B_14 <= 0; + reg_A_15 <= 0; + reg_B_15 <= 0; + end else if (enable) begin + reg_A_0 <= i_A_0; + reg_B_0 <= i_B_0; + reg_A_1 <= i_A_1; + reg_B_1 <= i_B_1; + reg_A_2 <= i_A_2; + reg_B_2 <= i_B_2; + reg_A_3 <= i_A_3; + reg_B_3 <= i_B_3; + reg_A_4 <= i_A_4; + reg_B_4 <= i_B_4; + reg_A_5 <= i_A_5; + reg_B_5 <= i_B_5; + reg_A_6 <= i_A_6; + reg_B_6 <= i_B_6; + reg_A_7 <= i_A_7; + reg_B_7 <= i_B_7; + reg_A_8 <= i_A_8; + reg_B_8 <= i_B_8; + reg_A_9 <= i_A_9; + reg_B_9 <= i_B_9; + reg_A_10 <= i_A_10; + reg_B_10 <= i_B_10; + reg_A_11 <= i_A_11; + reg_B_11 <= i_B_11; + reg_A_12 <= i_A_12; + reg_B_12 <= i_B_12; + reg_A_13 <= i_A_13; + reg_B_13 <= i_B_13; + reg_A_14 <= i_A_14; + reg_B_14 <= i_B_14; + reg_A_15 <= i_A_15; + reg_B_15 <= i_B_15; + valid_A_B <= i_valid; + end +end + +assign o_C_0 = reg_C_0; +assign o_C_1 = reg_C_1; +assign o_C_2 = reg_C_2; +assign o_C_3 = reg_C_3; +assign o_C_4 = reg_C_4; +assign o_C_5 = reg_C_5; +assign o_C_6 = reg_C_6; +assign o_C_7 = reg_C_7; +assign o_C_8 = reg_C_8; +assign o_C_9 = reg_C_9; +assign o_C_10 = reg_C_10; +assign o_C_11 = reg_C_11; +assign o_C_12 = reg_C_12; +assign o_C_13 = reg_C_13; +assign o_C_14 = reg_C_14; +assign o_C_15 = reg_C_15; +assign valid_C = round_valid_0; +assign o_ready = i_ready; +assign o_valid = valid_C & i_ready; + +endmodule + +module shift_register_group_18_16_18 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input reset +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_18 shift_register_unit_18_18_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +endmodule + +module elementwise_add_core_18_18_16 ( + input clk, + input reset, + input i_valid, + input i_ready, + input [17:0] i_A_0, + input [17:0] i_B_0, + output [17:0] o_C_0, + input [17:0] i_A_1, + input [17:0] i_B_1, + output [17:0] o_C_1, + input [17:0] i_A_2, + input [17:0] i_B_2, + output [17:0] o_C_2, + input [17:0] i_A_3, + input [17:0] i_B_3, + output [17:0] o_C_3, + input [17:0] i_A_4, + input [17:0] i_B_4, + output [17:0] o_C_4, + input [17:0] i_A_5, + input [17:0] i_B_5, + output [17:0] o_C_5, + input [17:0] i_A_6, + input [17:0] i_B_6, + output [17:0] o_C_6, + input [17:0] i_A_7, + input [17:0] i_B_7, + output [17:0] o_C_7, + input [17:0] i_A_8, + input [17:0] i_B_8, + output [17:0] o_C_8, + input [17:0] i_A_9, + input [17:0] i_B_9, + output [17:0] o_C_9, + input [17:0] i_A_10, + input [17:0] i_B_10, + output [17:0] o_C_10, + input [17:0] i_A_11, + input [17:0] i_B_11, + output [17:0] o_C_11, + input [17:0] i_A_12, + input [17:0] i_B_12, + output [17:0] o_C_12, + input [17:0] i_A_13, + input [17:0] i_B_13, + output [17:0] o_C_13, + input [17:0] i_A_14, + input [17:0] i_B_14, + output [17:0] o_C_14, + input [17:0] i_A_15, + input [17:0] i_B_15, + output [17:0] o_C_15, + output o_valid, + output o_ready +); + +reg [17:0] reg_A_0; +reg [17:0] reg_B_0; +reg [17:0] reg_C_0; +reg [17:0] reg_A_1; +reg [17:0] reg_B_1; +reg [17:0] reg_C_1; +reg [17:0] reg_A_2; +reg [17:0] reg_B_2; +reg [17:0] reg_C_2; +reg [17:0] reg_A_3; +reg [17:0] reg_B_3; +reg [17:0] reg_C_3; +reg [17:0] reg_A_4; +reg [17:0] reg_B_4; +reg [17:0] reg_C_4; +reg [17:0] reg_A_5; +reg [17:0] reg_B_5; +reg [17:0] reg_C_5; +reg [17:0] reg_A_6; +reg [17:0] reg_B_6; +reg [17:0] reg_C_6; +reg [17:0] reg_A_7; +reg [17:0] reg_B_7; +reg [17:0] reg_C_7; +reg [17:0] reg_A_8; +reg [17:0] reg_B_8; +reg [17:0] reg_C_8; +reg [17:0] reg_A_9; +reg [17:0] reg_B_9; +reg [17:0] reg_C_9; +reg [17:0] reg_A_10; +reg [17:0] reg_B_10; +reg [17:0] reg_C_10; +reg [17:0] reg_A_11; +reg [17:0] reg_B_11; +reg [17:0] reg_C_11; +reg [17:0] reg_A_12; +reg [17:0] reg_B_12; +reg [17:0] reg_C_12; +reg [17:0] reg_A_13; +reg [17:0] reg_B_13; +reg [17:0] reg_C_13; +reg [17:0] reg_A_14; +reg [17:0] reg_B_14; +reg [17:0] reg_C_14; +reg [17:0] reg_A_15; +reg [17:0] reg_B_15; +reg [17:0] reg_C_15; + +reg valid_A_B, valid_C; +wire enable; +assign enable = i_ready; + +always @ (posedge clk) begin + if (reset) begin + valid_A_B <= 1'b0; + valid_C <= 1'b0; + reg_A_0 <= 0; + reg_B_0 <= 0; + reg_C_0 <= 0; + reg_A_1 <= 0; + reg_B_1 <= 0; + reg_C_1 <= 0; + reg_A_2 <= 0; + reg_B_2 <= 0; + reg_C_2 <= 0; + reg_A_3 <= 0; + reg_B_3 <= 0; + reg_C_3 <= 0; + reg_A_4 <= 0; + reg_B_4 <= 0; + reg_C_4 <= 0; + reg_A_5 <= 0; + reg_B_5 <= 0; + reg_C_5 <= 0; + reg_A_6 <= 0; + reg_B_6 <= 0; + reg_C_6 <= 0; + reg_A_7 <= 0; + reg_B_7 <= 0; + reg_C_7 <= 0; + reg_A_8 <= 0; + reg_B_8 <= 0; + reg_C_8 <= 0; + reg_A_9 <= 0; + reg_B_9 <= 0; + reg_C_9 <= 0; + reg_A_10 <= 0; + reg_B_10 <= 0; + reg_C_10 <= 0; + reg_A_11 <= 0; + reg_B_11 <= 0; + reg_C_11 <= 0; + reg_A_12 <= 0; + reg_B_12 <= 0; + reg_C_12 <= 0; + reg_A_13 <= 0; + reg_B_13 <= 0; + reg_C_13 <= 0; + reg_A_14 <= 0; + reg_B_14 <= 0; + reg_C_14 <= 0; + reg_A_15 <= 0; + reg_B_15 <= 0; + reg_C_15 <= 0; + end else if (enable) begin + reg_A_0 <= i_A_0; + reg_B_0 <= i_B_0; + reg_C_0 <= reg_A_0 + reg_B_0; + reg_A_1 <= i_A_1; + reg_B_1 <= i_B_1; + reg_C_1 <= reg_A_1 + reg_B_1; + reg_A_2 <= i_A_2; + reg_B_2 <= i_B_2; + reg_C_2 <= reg_A_2 + reg_B_2; + reg_A_3 <= i_A_3; + reg_B_3 <= i_B_3; + reg_C_3 <= reg_A_3 + reg_B_3; + reg_A_4 <= i_A_4; + reg_B_4 <= i_B_4; + reg_C_4 <= reg_A_4 + reg_B_4; + reg_A_5 <= i_A_5; + reg_B_5 <= i_B_5; + reg_C_5 <= reg_A_5 + reg_B_5; + reg_A_6 <= i_A_6; + reg_B_6 <= i_B_6; + reg_C_6 <= reg_A_6 + reg_B_6; + reg_A_7 <= i_A_7; + reg_B_7 <= i_B_7; + reg_C_7 <= reg_A_7 + reg_B_7; + reg_A_8 <= i_A_8; + reg_B_8 <= i_B_8; + reg_C_8 <= reg_A_8 + reg_B_8; + reg_A_9 <= i_A_9; + reg_B_9 <= i_B_9; + reg_C_9 <= reg_A_9 + reg_B_9; + reg_A_10 <= i_A_10; + reg_B_10 <= i_B_10; + reg_C_10 <= reg_A_10 + reg_B_10; + reg_A_11 <= i_A_11; + reg_B_11 <= i_B_11; + reg_C_11 <= reg_A_11 + reg_B_11; + reg_A_12 <= i_A_12; + reg_B_12 <= i_B_12; + reg_C_12 <= reg_A_12 + reg_B_12; + reg_A_13 <= i_A_13; + reg_B_13 <= i_B_13; + reg_C_13 <= reg_A_13 + reg_B_13; + reg_A_14 <= i_A_14; + reg_B_14 <= i_B_14; + reg_C_14 <= reg_A_14 + reg_B_14; + reg_A_15 <= i_A_15; + reg_B_15 <= i_B_15; + reg_C_15 <= reg_A_15 + reg_B_15; + valid_A_B <= i_valid; + valid_C <= valid_A_B; + end +end + +assign o_C_0 = reg_C_0; +assign o_C_1 = reg_C_1; +assign o_C_2 = reg_C_2; +assign o_C_3 = reg_C_3; +assign o_C_4 = reg_C_4; +assign o_C_5 = reg_C_5; +assign o_C_6 = reg_C_6; +assign o_C_7 = reg_C_7; +assign o_C_8 = reg_C_8; +assign o_C_9 = reg_C_9; +assign o_C_10 = reg_C_10; +assign o_C_11 = reg_C_11; +assign o_C_12 = reg_C_12; +assign o_C_13 = reg_C_13; +assign o_C_14 = reg_C_14; +assign o_C_15 = reg_C_15; +assign o_ready = i_ready; +assign o_valid = valid_C & i_ready; + +endmodule + +module shift_register_group_18_16_14 ( + input clk, + input enable, + input [17:0] in_0, + output [17:0] out_0, + input [17:0] in_1, + output [17:0] out_1, + input [17:0] in_2, + output [17:0] out_2, + input [17:0] in_3, + output [17:0] out_3, + input [17:0] in_4, + output [17:0] out_4, + input [17:0] in_5, + output [17:0] out_5, + input [17:0] in_6, + output [17:0] out_6, + input [17:0] in_7, + output [17:0] out_7, + input [17:0] in_8, + output [17:0] out_8, + input [17:0] in_9, + output [17:0] out_9, + input [17:0] in_10, + output [17:0] out_10, + input [17:0] in_11, + output [17:0] out_11, + input [17:0] in_12, + output [17:0] out_12, + input [17:0] in_13, + output [17:0] out_13, + input [17:0] in_14, + output [17:0] out_14, + input [17:0] in_15, + output [17:0] out_15, + input reset +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_0), + .out(out_0) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_1), + .out(out_1) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_2 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_2), + .out(out_2) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_3 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_3), + .out(out_3) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_4 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_4), + .out(out_4) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_5 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_5), + .out(out_5) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_6 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_6), + .out(out_6) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_7 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_7), + .out(out_7) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_8 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_8), + .out(out_8) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_9 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_9), + .out(out_9) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_10 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_10), + .out(out_10) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_11 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_11), + .out(out_11) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_12 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_12), + .out(out_12) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_13 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_13), + .out(out_13) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_14 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_14), + .out(out_14) +); + +shift_register_unit_18_14 shift_register_unit_18_14_inst_15 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(in_15), + .out(out_15) +); + +endmodule + +module shift_register_unit_18_14 ( + input clk, + input reset, + input enable, + input [17:0] in, + output [17:0] out +); + +reg [17:0] shift_registers_0; +reg [17:0] shift_registers_1; +reg [17:0] shift_registers_2; +reg [17:0] shift_registers_3; +reg [17:0] shift_registers_4; +reg [17:0] shift_registers_5; +reg [17:0] shift_registers_6; +reg [17:0] shift_registers_7; +reg [17:0] shift_registers_8; +reg [17:0] shift_registers_9; +reg [17:0] shift_registers_10; +reg [17:0] shift_registers_11; +reg [17:0] shift_registers_12; +reg [17:0] shift_registers_13; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 18'd0; + shift_registers_1 <= 18'd0; + shift_registers_2 <= 18'd0; + shift_registers_3 <= 18'd0; + shift_registers_4 <= 18'd0; + shift_registers_5 <= 18'd0; + shift_registers_6 <= 18'd0; + shift_registers_7 <= 18'd0; + shift_registers_8 <= 18'd0; + shift_registers_9 <= 18'd0; + shift_registers_10 <= 18'd0; + shift_registers_11 <= 18'd0; + shift_registers_12 <= 18'd0; + shift_registers_13 <= 18'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + shift_registers_2 <= shift_registers_1; + shift_registers_3 <= shift_registers_2; + shift_registers_4 <= shift_registers_3; + shift_registers_5 <= shift_registers_4; + shift_registers_6 <= shift_registers_5; + shift_registers_7 <= shift_registers_6; + shift_registers_8 <= shift_registers_7; + shift_registers_9 <= shift_registers_8; + shift_registers_10 <= shift_registers_9; + shift_registers_11 <= shift_registers_10; + shift_registers_12 <= shift_registers_11; + shift_registers_13 <= shift_registers_12; + end +end + +assign out = shift_registers_13; + +endmodule + +module tanh_core_18_18_10_32_1 ( + input clk, + input reset, + input i_valid, + input i_ready, + output o_ready, + output o_valid, + input [17:0] i_x, + output [17:0] o_y +); + +reg [12:0] k_list_0; +reg [12:0] b_list_0; +reg [12:0] k_list_1; +reg [12:0] b_list_1; +reg [12:0] k_list_2; +reg [12:0] b_list_2; +reg [12:0] k_list_3; +reg [12:0] b_list_3; +reg [12:0] k_list_4; +reg [12:0] b_list_4; +reg [12:0] k_list_5; +reg [12:0] b_list_5; +reg [12:0] k_list_6; +reg [12:0] b_list_6; +reg [12:0] k_list_7; +reg [12:0] b_list_7; +reg [12:0] k_list_8; +reg [12:0] b_list_8; +reg [12:0] k_list_9; +reg [12:0] b_list_9; +reg [12:0] k_list_10; +reg [12:0] b_list_10; +reg [12:0] k_list_11; +reg [12:0] b_list_11; +reg [12:0] k_list_12; +reg [12:0] b_list_12; +reg [12:0] k_list_13; +reg [12:0] b_list_13; +reg [12:0] k_list_14; +reg [12:0] b_list_14; +reg [12:0] k_list_15; +reg [12:0] b_list_15; +reg [12:0] k_list_16; +reg [12:0] b_list_16; +reg [12:0] k_list_17; +reg [12:0] b_list_17; +reg [12:0] k_list_18; +reg [12:0] b_list_18; +reg [12:0] k_list_19; +reg [12:0] b_list_19; +reg [12:0] k_list_20; +reg [12:0] b_list_20; +reg [12:0] k_list_21; +reg [12:0] b_list_21; +reg [12:0] k_list_22; +reg [12:0] b_list_22; +reg [12:0] k_list_23; +reg [12:0] b_list_23; +reg [12:0] k_list_24; +reg [12:0] b_list_24; +reg [12:0] k_list_25; +reg [12:0] b_list_25; +reg [12:0] k_list_26; +reg [12:0] b_list_26; +reg [12:0] k_list_27; +reg [12:0] b_list_27; +reg [12:0] k_list_28; +reg [12:0] b_list_28; +reg [12:0] k_list_29; +reg [12:0] b_list_29; +reg [12:0] k_list_30; +reg [12:0] b_list_30; +reg [12:0] k_list_31; +reg [12:0] b_list_31; + +always @ (posedge clk) begin + k_list_0 <= 13'b0011111110101; + k_list_1 <= 13'b0011110110111; + k_list_2 <= 13'b0011101000011; + k_list_3 <= 13'b0011010100100; + k_list_4 <= 13'b0010111101011; + k_list_5 <= 13'b0010100101000; + k_list_6 <= 13'b0010001100111; + k_list_7 <= 13'b0001110110001; + k_list_8 <= 13'b0001100001110; + k_list_9 <= 13'b0001001111111; + k_list_10 <= 13'b0001000000101; + k_list_11 <= 13'b0000110011111; + k_list_12 <= 13'b0000101001011; + k_list_13 <= 13'b0000100000111; + k_list_14 <= 13'b0000011010000; + k_list_15 <= 13'b0000010100100; + k_list_16 <= 13'b0000010000001; + k_list_17 <= 13'b0000001100101; + k_list_18 <= 13'b0000001001111; + k_list_19 <= 13'b0000000111110; + k_list_20 <= 13'b0000000110000; + k_list_21 <= 13'b0000000100110; + k_list_22 <= 13'b0000000011101; + k_list_23 <= 13'b0000000010111; + k_list_24 <= 13'b0000000010010; + k_list_25 <= 13'b0000000001110; + k_list_26 <= 13'b0000000001011; + k_list_27 <= 13'b0000000001000; + k_list_28 <= 13'b0000000000111; + k_list_29 <= 13'b0000000000101; + k_list_30 <= 13'b0000000000100; + k_list_31 <= 13'b0000000000011; + b_list_0 <= 13'b0000000000000; + b_list_1 <= 13'b0000000001000; + b_list_2 <= 13'b0000000100101; + b_list_3 <= 13'b0000001100000; + b_list_4 <= 13'b0000010111101; + b_list_5 <= 13'b0000100110111; + b_list_6 <= 13'b0000111001000; + b_list_7 <= 13'b0001001100111; + b_list_8 <= 13'b0001100001010; + b_list_9 <= 13'b0001110101011; + b_list_10 <= 13'b0010001000011; + b_list_11 <= 13'b0010011001111; + b_list_12 <= 13'b0010101001101; + b_list_13 <= 13'b0010110111100; + b_list_14 <= 13'b0011000011101; + b_list_15 <= 13'b0011001101111; + b_list_16 <= 13'b0011010110101; + b_list_17 <= 13'b0011011110000; + b_list_18 <= 13'b0011100100001; + b_list_19 <= 13'b0011101001010; + b_list_20 <= 13'b0011101101100; + b_list_21 <= 13'b0011110001000; + b_list_22 <= 13'b0011110011110; + b_list_23 <= 13'b0011110110001; + b_list_24 <= 13'b0011111000000; + b_list_25 <= 13'b0011111001101; + b_list_26 <= 13'b0011111010111; + b_list_27 <= 13'b0011111011111; + b_list_28 <= 13'b0011111100101; + b_list_29 <= 13'b0011111101010; + b_list_30 <= 13'b0011111101111; + b_list_31 <= 13'b0011111110010; +end +reg [17:0] x; +reg [17:0] y; +reg valid_x, valid_y, enable; +wire [4:0] sel_k_b; + +wire abs_valid, round_valid, mult_valid, compute_valid; +reg [12:0] mac_ay, mac_az; +reg is_x_negative; +wire is_x_negative_hold; +wire [17:0] abs_x; +wire [17:0] x_partial; +reg [31:0] y_compute; +wire [31:0] x_k_plus_b; +wire [31:0] y_rounded; + +assign x_partial = (abs_x >> 7); +assign sel_k_b = x_partial [4:0]; + +reg [12:0] selected_k, selected_b; +always @ (*) begin + if (sel_k_b == 0) begin + selected_k <= k_list_0; + selected_b <= b_list_0; + end else if (sel_k_b == 1) begin + selected_k <= k_list_1; + selected_b <= b_list_1; + end else if (sel_k_b == 2) begin + selected_k <= k_list_2; + selected_b <= b_list_2; + end else if (sel_k_b == 3) begin + selected_k <= k_list_3; + selected_b <= b_list_3; + end else if (sel_k_b == 4) begin + selected_k <= k_list_4; + selected_b <= b_list_4; + end else if (sel_k_b == 5) begin + selected_k <= k_list_5; + selected_b <= b_list_5; + end else if (sel_k_b == 6) begin + selected_k <= k_list_6; + selected_b <= b_list_6; + end else if (sel_k_b == 7) begin + selected_k <= k_list_7; + selected_b <= b_list_7; + end else if (sel_k_b == 8) begin + selected_k <= k_list_8; + selected_b <= b_list_8; + end else if (sel_k_b == 9) begin + selected_k <= k_list_9; + selected_b <= b_list_9; + end else if (sel_k_b == 10) begin + selected_k <= k_list_10; + selected_b <= b_list_10; + end else if (sel_k_b == 11) begin + selected_k <= k_list_11; + selected_b <= b_list_11; + end else if (sel_k_b == 12) begin + selected_k <= k_list_12; + selected_b <= b_list_12; + end else if (sel_k_b == 13) begin + selected_k <= k_list_13; + selected_b <= b_list_13; + end else if (sel_k_b == 14) begin + selected_k <= k_list_14; + selected_b <= b_list_14; + end else if (sel_k_b == 15) begin + selected_k <= k_list_15; + selected_b <= b_list_15; + end else if (sel_k_b == 16) begin + selected_k <= k_list_16; + selected_b <= b_list_16; + end else if (sel_k_b == 17) begin + selected_k <= k_list_17; + selected_b <= b_list_17; + end else if (sel_k_b == 18) begin + selected_k <= k_list_18; + selected_b <= b_list_18; + end else if (sel_k_b == 19) begin + selected_k <= k_list_19; + selected_b <= b_list_19; + end else if (sel_k_b == 20) begin + selected_k <= k_list_20; + selected_b <= b_list_20; + end else if (sel_k_b == 21) begin + selected_k <= k_list_21; + selected_b <= b_list_21; + end else if (sel_k_b == 22) begin + selected_k <= k_list_22; + selected_b <= b_list_22; + end else if (sel_k_b == 23) begin + selected_k <= k_list_23; + selected_b <= b_list_23; + end else if (sel_k_b == 24) begin + selected_k <= k_list_24; + selected_b <= b_list_24; + end else if (sel_k_b == 25) begin + selected_k <= k_list_25; + selected_b <= b_list_25; + end else if (sel_k_b == 26) begin + selected_k <= k_list_26; + selected_b <= b_list_26; + end else if (sel_k_b == 27) begin + selected_k <= k_list_27; + selected_b <= b_list_27; + end else if (sel_k_b == 28) begin + selected_k <= k_list_28; + selected_b <= b_list_28; + end else if (sel_k_b == 29) begin + selected_k <= k_list_29; + selected_b <= b_list_29; + end else if (sel_k_b == 30) begin + selected_k <= k_list_30; + selected_b <= b_list_30; + end else begin + selected_k <= k_list_31; + selected_b <= b_list_31; + end +end +always @ (*) begin + if (abs_x >= 4096) begin + mac_ay <= 0; + mac_az <= 12'd2048; + end else begin + mac_ay <= selected_k; + mac_az <= (selected_b << 10); + end +end +dsp_signed_mac_18_13_23_32 dsp_signed_mac_18_13_23_32_inst_lzpbobgnsr ( + .clk(clk), + .reset(reset), + .ena(enable), + .ax(abs_x), + .ay(mac_ay), + .az(mac_az), + .i_valid(abs_valid), + .o_valid(compute_valid), + .resulta(x_k_plus_b) +); + +shift_register_unit_1_3 shift_register_unit_1_3_inst_xudpcwywtj ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(is_x_negative), + .out(is_x_negative_hold) +); + +abs_unit_18 abs_unit_18_inst_qrcawcdbmv ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(valid_x), + .in(x), + .o_valid(abs_valid), + .out(abs_x) +); + +fp_rounding_unit_1_32_11 fp_rounding_unit_1_32_11_inst_tgqjdwkqtv ( + .clk(clk), + .reset(reset), + .enable(enable), + .i_valid(compute_valid), + .in(y_compute), + .o_valid(round_valid), + .out(y_rounded) +); + +always @ (*) begin + if (is_x_negative_hold) + y_compute = 2048 - x_k_plus_b; + else + y_compute = x_k_plus_b; + enable = i_ready; +end +always @ (posedge clk) begin + if (reset) begin + valid_x <= 1'b0; + valid_y <= 1'b0; + x <= 0; + y <= 0; + end else if (enable) begin + valid_x <= i_valid; + valid_y <= round_valid; + x <= i_x; + if (x[17] == 1'b1) + is_x_negative <= 1'b1; + else + is_x_negative <= 1'b0; + y <= y_rounded[17:0]; + end +end + +assign o_y = y; +assign o_ready = i_ready; +assign o_valid = valid_y & i_ready; + +endmodule + +module pipelined_input_18_1_16 ( + input clk, + input reset, + input enable, + input load_input, + input [17:0] i_data_0_0, + input [17:0] i_data_0_1, + input [17:0] i_data_0_2, + input [17:0] i_data_0_3, + input [17:0] i_data_0_4, + input [17:0] i_data_0_5, + input [17:0] i_data_0_6, + input [17:0] i_data_0_7, + input [17:0] i_data_0_8, + input [17:0] i_data_0_9, + input [17:0] i_data_0_10, + input [17:0] i_data_0_11, + input [17:0] i_data_0_12, + input [17:0] i_data_0_13, + input [17:0] i_data_0_14, + input [17:0] i_data_0_15, + output [17:0] o_data_0, + output [17:0] o_data_1, + output [17:0] o_data_2, + output [17:0] o_data_3, + output [17:0] o_data_4, + output [17:0] o_data_5, + output [17:0] o_data_6, + output [17:0] o_data_7, + output [17:0] o_data_8, + output [17:0] o_data_9, + output [17:0] o_data_10, + output [17:0] o_data_11, + output [17:0] o_data_12, + output [17:0] o_data_13, + output [17:0] o_data_14, + output [17:0] o_data_15, + output o_valid +); + +reg [17:0] pipeline_0_0; +reg [17:0] pipeline_0_1; +reg [17:0] pipeline_0_2; +reg [17:0] pipeline_0_3; +reg [17:0] pipeline_0_4; +reg [17:0] pipeline_0_5; +reg [17:0] pipeline_0_6; +reg [17:0] pipeline_0_7; +reg [17:0] pipeline_0_8; +reg [17:0] pipeline_0_9; +reg [17:0] pipeline_0_10; +reg [17:0] pipeline_0_11; +reg [17:0] pipeline_0_12; +reg [17:0] pipeline_0_13; +reg [17:0] pipeline_0_14; +reg [17:0] pipeline_0_15; +reg pipeline_valid_0; + +always @ (posedge clk) begin + if (reset) begin + pipeline_0_0 <= 0; + pipeline_0_1 <= 0; + pipeline_0_2 <= 0; + pipeline_0_3 <= 0; + pipeline_0_4 <= 0; + pipeline_0_5 <= 0; + pipeline_0_6 <= 0; + pipeline_0_7 <= 0; + pipeline_0_8 <= 0; + pipeline_0_9 <= 0; + pipeline_0_10 <= 0; + pipeline_0_11 <= 0; + pipeline_0_12 <= 0; + pipeline_0_13 <= 0; + pipeline_0_14 <= 0; + pipeline_0_15 <= 0; + pipeline_valid_0 <= 0; + end else if (enable) begin + if (load_input) begin + pipeline_0_0 <= i_data_0_0; + pipeline_0_1 <= i_data_0_1; + pipeline_0_2 <= i_data_0_2; + pipeline_0_3 <= i_data_0_3; + pipeline_0_4 <= i_data_0_4; + pipeline_0_5 <= i_data_0_5; + pipeline_0_6 <= i_data_0_6; + pipeline_0_7 <= i_data_0_7; + pipeline_0_8 <= i_data_0_8; + pipeline_0_9 <= i_data_0_9; + pipeline_0_10 <= i_data_0_10; + pipeline_0_11 <= i_data_0_11; + pipeline_0_12 <= i_data_0_12; + pipeline_0_13 <= i_data_0_13; + pipeline_0_14 <= i_data_0_14; + pipeline_0_15 <= i_data_0_15; + pipeline_valid_0 <= 1'b1; + end else begin + pipeline_0_0 <= 0; + pipeline_0_1 <= 0; + pipeline_0_2 <= 0; + pipeline_0_3 <= 0; + pipeline_0_4 <= 0; + pipeline_0_5 <= 0; + pipeline_0_6 <= 0; + pipeline_0_7 <= 0; + pipeline_0_8 <= 0; + pipeline_0_9 <= 0; + pipeline_0_10 <= 0; + pipeline_0_11 <= 0; + pipeline_0_12 <= 0; + pipeline_0_13 <= 0; + pipeline_0_14 <= 0; + pipeline_0_15 <= 0; + pipeline_valid_0 <= 1'b0; + end + end +end + +assign o_data_0 = pipeline_0_0; +assign o_data_1 = pipeline_0_1; +assign o_data_2 = pipeline_0_2; +assign o_data_3 = pipeline_0_3; +assign o_data_4 = pipeline_0_4; +assign o_data_5 = pipeline_0_5; +assign o_data_6 = pipeline_0_6; +assign o_data_7 = pipeline_0_7; +assign o_data_8 = pipeline_0_8; +assign o_data_9 = pipeline_0_9; +assign o_data_10 = pipeline_0_10; +assign o_data_11 = pipeline_0_11; +assign o_data_12 = pipeline_0_12; +assign o_data_13 = pipeline_0_13; +assign o_data_14 = pipeline_0_14; +assign o_data_15 = pipeline_0_15; +assign o_valid = pipeline_valid_0; + +endmodule + +module stage2_Ct_buffer_18_1_16_64 ( + input clk, + input reset, + input wen, + input ren, + input [17:0] i_Ct_0, + input [17:0] i_Ct_1, + input [17:0] i_Ct_2, + input [17:0] i_Ct_3, + input [17:0] i_Ct_4, + input [17:0] i_Ct_5, + input [17:0] i_Ct_6, + input [17:0] i_Ct_7, + input [17:0] i_Ct_8, + input [17:0] i_Ct_9, + input [17:0] i_Ct_10, + input [17:0] i_Ct_11, + input [17:0] i_Ct_12, + input [17:0] i_Ct_13, + input [17:0] i_Ct_14, + input [17:0] i_Ct_15, + output [17:0] o_Ct_0, + output [17:0] o_Ct_1, + output [17:0] o_Ct_2, + output [17:0] o_Ct_3, + output [17:0] o_Ct_4, + output [17:0] o_Ct_5, + output [17:0] o_Ct_6, + output [17:0] o_Ct_7, + output [17:0] o_Ct_8, + output [17:0] o_Ct_9, + output [17:0] o_Ct_10, + output [17:0] o_Ct_11, + output [17:0] o_Ct_12, + output [17:0] o_Ct_13, + output [17:0] o_Ct_14, + output [17:0] o_Ct_15, + output o_valid +); + +wire [287:0] packed_o_Ct_0; +reg [5:0] raddrs_0; +wire [287:0] packed_Ct; + +reg r_valid; + +wire [13:0] input_index_counter; +counter_63_1 counter_63_1_inst_in ( + .clk(clk), + .reset(reset), + .ena(wen), + .count(input_index_counter) +); + +wire [13:0] output_index_counter; +counter_63_1 counter_63_1_inst_out ( + .clk(clk), + .reset(reset), + .ena(ren), + .count(output_index_counter) +); + +always @ (posedge clk) begin + r_valid <= ren; + if ((input_index_counter + 14'd0) < 64) + raddrs_0 <= input_index_counter[5:0] + 6'd0; + else + raddrs_0 <= 6'd63; +end + +assign packed_Ct[17:0] = i_Ct_0; +assign packed_Ct[35:18] = i_Ct_1; +assign packed_Ct[53:36] = i_Ct_2; +assign packed_Ct[71:54] = i_Ct_3; +assign packed_Ct[89:72] = i_Ct_4; +assign packed_Ct[107:90] = i_Ct_5; +assign packed_Ct[125:108] = i_Ct_6; +assign packed_Ct[143:126] = i_Ct_7; +assign packed_Ct[161:144] = i_Ct_8; +assign packed_Ct[179:162] = i_Ct_9; +assign packed_Ct[197:180] = i_Ct_10; +assign packed_Ct[215:198] = i_Ct_11; +assign packed_Ct[233:216] = i_Ct_12; +assign packed_Ct[251:234] = i_Ct_13; +assign packed_Ct[269:252] = i_Ct_14; +assign packed_Ct[287:270] = i_Ct_15; + +ram_288_0_64 ram_288_0_64_inst_0 ( + .clk(clk), + .waddr(input_index_counter), + .wdata(packed_Ct), + .wen(wen), + .raddr(raddrs_0), + .q(packed_o_Ct_0) +); + +assign o_Ct_0 = packed_o_Ct_0[17:0]; +assign o_Ct_1 = packed_o_Ct_0[35:18]; +assign o_Ct_2 = packed_o_Ct_0[53:36]; +assign o_Ct_3 = packed_o_Ct_0[71:54]; +assign o_Ct_4 = packed_o_Ct_0[89:72]; +assign o_Ct_5 = packed_o_Ct_0[107:90]; +assign o_Ct_6 = packed_o_Ct_0[125:108]; +assign o_Ct_7 = packed_o_Ct_0[143:126]; +assign o_Ct_8 = packed_o_Ct_0[161:144]; +assign o_Ct_9 = packed_o_Ct_0[179:162]; +assign o_Ct_10 = packed_o_Ct_0[197:180]; +assign o_Ct_11 = packed_o_Ct_0[215:198]; +assign o_Ct_12 = packed_o_Ct_0[233:216]; +assign o_Ct_13 = packed_o_Ct_0[251:234]; +assign o_Ct_14 = packed_o_Ct_0[269:252]; +assign o_Ct_15 = packed_o_Ct_0[287:270]; +assign o_valid = r_valid; +endmodule + +module ram_288_0_64 ( + input clk, + input [5:0] waddr, + input [287:0] wdata, + input wen, + input [5:0] raddr, + output [287:0] q +); + +wire [287:0] rd_dummy_signal; +wire [287:0] wr_dummy_signal; +assign rd_dummy_signal = 0; + +dpram # (.AWIDTH(6), .DWIDTH(288), .NUM_WORDS(1<<6)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(q), + .clk(clk) +); +endmodule + +module stage2_mt_buffer_18_1_16_64_32 ( + input clk, + input reset, + input i_valid, + input [17:0] data_0, + output [17:0] q_0, + input [17:0] data_1, + output [17:0] q_1, + input [17:0] data_2, + output [17:0] q_2, + input [17:0] data_3, + output [17:0] q_3, + input [17:0] data_4, + output [17:0] q_4, + input [17:0] data_5, + output [17:0] q_5, + input [17:0] data_6, + output [17:0] q_6, + input [17:0] data_7, + output [17:0] q_7, + input [17:0] data_8, + output [17:0] q_8, + input [17:0] data_9, + output [17:0] q_9, + input [17:0] data_10, + output [17:0] q_10, + input [17:0] data_11, + output [17:0] q_11, + input [17:0] data_12, + output [17:0] q_12, + input [17:0] data_13, + output [17:0] q_13, + input [17:0] data_14, + output [17:0] q_14, + input [17:0] data_15, + output [17:0] q_15, + output o_valid +); + +wire [287:0] packed_result; +wire [287:0] packed_data; + +wire [13:0] input_index_counter; +reg is_buffer_full; +counter_63_1 counter_63_1_inst_in ( + .clk(clk), + .reset(reset), + .ena(i_valid), + .count(input_index_counter) +); + +reg en_output_counter; +wire [13:0] output_index_counter; +counter_63_1 counter_63_1_inst_out_count ( + .clk(clk), + .reset(reset), + .ena(en_output_counter), + .count(output_index_counter) +); + +reg [5:0] raddr; +always @ (*) begin + if (is_buffer_full) + raddr <= output_index_counter[5:0]; + else + raddr <= input_index_counter[5:0]; +end + +wire incr_loop_index; +assign incr_loop_index = (output_index_counter == (63) && en_output_counter); + +reg is_output_enough; +wire [13:0] loop_counter; +counter_30_1 counter_30_1_inst_out_enough ( + .clk(clk), + .reset(reset), + .ena(incr_loop_index), + .count(loop_counter) +); + +ram_288_0_64 ram_288_0_64_inst_ygusiekazw ( + .clk(clk), + .waddr(input_index_counter), + .wdata(packed_data), + .wen(i_valid), + .raddr(raddr), + .q(packed_result) +); + +assign q_0 = packed_result[17:0]; +assign packed_data[17:0] = data_0; +assign q_1 = packed_result[35:18]; +assign packed_data[35:18] = data_1; +assign q_2 = packed_result[53:36]; +assign packed_data[53:36] = data_2; +assign q_3 = packed_result[71:54]; +assign packed_data[71:54] = data_3; +assign q_4 = packed_result[89:72]; +assign packed_data[89:72] = data_4; +assign q_5 = packed_result[107:90]; +assign packed_data[107:90] = data_5; +assign q_6 = packed_result[125:108]; +assign packed_data[125:108] = data_6; +assign q_7 = packed_result[143:126]; +assign packed_data[143:126] = data_7; +assign q_8 = packed_result[161:144]; +assign packed_data[161:144] = data_8; +assign q_9 = packed_result[179:162]; +assign packed_data[179:162] = data_9; +assign q_10 = packed_result[197:180]; +assign packed_data[197:180] = data_10; +assign q_11 = packed_result[215:198]; +assign packed_data[215:198] = data_11; +assign q_12 = packed_result[233:216]; +assign packed_data[233:216] = data_12; +assign q_13 = packed_result[251:234]; +assign packed_data[251:234] = data_13; +assign q_14 = packed_result[269:252]; +assign packed_data[269:252] = data_14; +assign q_15 = packed_result[287:270]; +assign packed_data[287:270] = data_15; + +always @ (posedge clk) begin + if (reset) begin + en_output_counter <= 1'b0; + is_buffer_full <= 1'b0; + is_output_enough <= 1'b0; + end else begin + en_output_counter <= (is_buffer_full && ~en_output_counter && ~is_output_enough); + if (input_index_counter == 63 && i_valid) + is_buffer_full <= 1'b1; + else if (input_index_counter == 0 && output_index_counter == 0 && is_output_enough) + is_buffer_full <= 1'b0; + if ((loop_counter == (30)) + &&(output_index_counter == 63) + && en_output_counter) + is_output_enough <= 1'b1; + else if (loop_counter == 0 && i_valid) + is_output_enough <= 1'b0; + end +end + +wire valid_1, valid_2, is_buffer_full_hold; +shift_register_unit_12 shift_register_unit_12_inst_is_buffer_full ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .in(is_buffer_full), + .out(is_buffer_full_hold) +); + +shift_register_unit_12 shift_register_unit_12_inst_valid1 ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .in(i_valid), + .out(valid_1) +); + +shift_register_unit_12 shift_register_unit_12_inst_valid2 ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .in(en_output_counter), + .out(valid_2) +); + +reg output_valid; +always @ (*) begin + if (is_buffer_full_hold) + output_valid <= valid_2; + else + output_valid <= valid_1; +end +assign o_valid = output_valid; + +endmodule + +module counter_30_1 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd1) <= 30) begin + count <= count + 14'd1; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module shift_register_unit_12 ( + input clk, + input reset, + input enable, + input [0:0] in, + output [0:0] out +); + +reg [0:0] shift_registers_0; +reg [0:0] shift_registers_1; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 1'd0; + shift_registers_1 <= 1'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + end +end + +assign out = shift_registers_1; + +endmodule + +module C_LSTM_stage_3_18_10_64_2048_1_16_1 ( + input clk, + input reset, + input [287:0] wdata, + input [1:0] wen, + input i_ready, + input i_valid, + input [17:0] i_mt_0, + input [17:0] i_mt_1, + input [17:0] i_mt_2, + input [17:0] i_mt_3, + input [17:0] i_mt_4, + input [17:0] i_mt_5, + input [17:0] i_mt_6, + input [17:0] i_mt_7, + input [17:0] i_mt_8, + input [17:0] i_mt_9, + input [17:0] i_mt_10, + input [17:0] i_mt_11, + input [17:0] i_mt_12, + input [17:0] i_mt_13, + input [17:0] i_mt_14, + input [17:0] i_mt_15, + output [17:0] o_Yt_0_0, + output [17:0] o_Yt_0_1, + output [17:0] o_Yt_0_2, + output [17:0] o_Yt_0_3, + output [17:0] o_Yt_0_4, + output [17:0] o_Yt_0_5, + output [17:0] o_Yt_0_6, + output [17:0] o_Yt_0_7, + output [17:0] o_Yt_0_8, + output [17:0] o_Yt_0_9, + output [17:0] o_Yt_0_10, + output [17:0] o_Yt_0_11, + output [17:0] o_Yt_0_12, + output [17:0] o_Yt_0_13, + output [17:0] o_Yt_0_14, + output [17:0] o_Yt_0_15, + output o_valid, + output o_ready +); + +wire enable; +assign enable = i_ready; +wire [17:0] mt_hold_0; +wire [17:0] mt_hold_1; +wire [17:0] mt_hold_2; +wire [17:0] mt_hold_3; +wire [17:0] mt_hold_4; +wire [17:0] mt_hold_5; +wire [17:0] mt_hold_6; +wire [17:0] mt_hold_7; +wire [17:0] mt_hold_8; +wire [17:0] mt_hold_9; +wire [17:0] mt_hold_10; +wire [17:0] mt_hold_11; +wire [17:0] mt_hold_12; +wire [17:0] mt_hold_13; +wire [17:0] mt_hold_14; +wire [17:0] mt_hold_15; +wire [17:0] Wym_real_0_0; +wire [17:0] Wym_imag_0_0; +wire [17:0] Wym_real_0_1; +wire [17:0] Wym_imag_0_1; +wire [17:0] Wym_real_0_2; +wire [17:0] Wym_imag_0_2; +wire [17:0] Wym_real_0_3; +wire [17:0] Wym_imag_0_3; +wire [17:0] Wym_real_0_4; +wire [17:0] Wym_imag_0_4; +wire [17:0] Wym_real_0_5; +wire [17:0] Wym_imag_0_5; +wire [17:0] Wym_real_0_6; +wire [17:0] Wym_imag_0_6; +wire [17:0] Wym_real_0_7; +wire [17:0] Wym_imag_0_7; +wire [17:0] Wym_real_0_8; +wire [17:0] Wym_imag_0_8; +wire reg_i_valid; +reg reg_i_ready; + +shift_register_group_18_16_3 shift_register_group_18_16_3_mt_holder ( + .clk(clk), + .enable(enable), + .in_0(i_mt_0), + .out_0(mt_hold_0), + .in_1(i_mt_1), + .out_1(mt_hold_1), + .in_2(i_mt_2), + .out_2(mt_hold_2), + .in_3(i_mt_3), + .out_3(mt_hold_3), + .in_4(i_mt_4), + .out_4(mt_hold_4), + .in_5(i_mt_5), + .out_5(mt_hold_5), + .in_6(i_mt_6), + .out_6(mt_hold_6), + .in_7(i_mt_7), + .out_7(mt_hold_7), + .in_8(i_mt_8), + .out_8(mt_hold_8), + .in_9(i_mt_9), + .out_9(mt_hold_9), + .in_10(i_mt_10), + .out_10(mt_hold_10), + .in_11(i_mt_11), + .out_11(mt_hold_11), + .in_12(i_mt_12), + .out_12(mt_hold_12), + .in_13(i_mt_13), + .out_13(mt_hold_13), + .in_14(i_mt_14), + .out_14(mt_hold_14), + .in_15(i_mt_15), + .out_15(mt_hold_15), + .reset(reset) +); + +shift_register_unit_18_3 shift_register_unit_18_3_valid_holder ( + .clk(clk), + .reset(reset), + .enable(enable), + .in(i_valid), + .out(reg_i_valid) +); + +stage3_parameter_buffer_18_1_16_64_2048 stage3_parameter_buffer_18_1_16_64_2048_inst_apsfeypufr ( + .clk(clk), + .reset(reset), + .wdata(wdata), + .wen(wen), + .Wym_real_0_0(Wym_real_0_0), + .Wym_imag_0_0(Wym_imag_0_0), + .Wym_real_0_1(Wym_real_0_1), + .Wym_imag_0_1(Wym_imag_0_1), + .Wym_real_0_2(Wym_real_0_2), + .Wym_imag_0_2(Wym_imag_0_2), + .Wym_real_0_3(Wym_real_0_3), + .Wym_imag_0_3(Wym_imag_0_3), + .Wym_real_0_4(Wym_real_0_4), + .Wym_imag_0_4(Wym_imag_0_4), + .Wym_real_0_5(Wym_real_0_5), + .Wym_imag_0_5(Wym_imag_0_5), + .Wym_real_0_6(Wym_real_0_6), + .Wym_imag_0_6(Wym_imag_0_6), + .Wym_real_0_7(Wym_real_0_7), + .Wym_imag_0_7(Wym_imag_0_7), + .Wym_real_0_8(Wym_real_0_8), + .Wym_imag_0_8(Wym_imag_0_8), + .incr_index(i_valid) +); + +multiple_c_matrix_vec_mult_and_sum_18_10_16_1_1_64 multiple_c_matrix_vec_mult_and_sum_18_10_16_1_1_64_inst_gwxvknsryv ( + .clk(clk), + .reset(reset), + .i_ready(reg_i_ready), + .i_valid(reg_i_valid), + .i_X_0(mt_hold_0), + .i_X_1(mt_hold_1), + .i_X_2(mt_hold_2), + .i_X_3(mt_hold_3), + .i_X_4(mt_hold_4), + .i_X_5(mt_hold_5), + .i_X_6(mt_hold_6), + .i_X_7(mt_hold_7), + .i_X_8(mt_hold_8), + .i_X_9(mt_hold_9), + .i_X_10(mt_hold_10), + .i_X_11(mt_hold_11), + .i_X_12(mt_hold_12), + .i_X_13(mt_hold_13), + .i_X_14(mt_hold_14), + .i_X_15(mt_hold_15), + .i_W_real_0_0(Wym_real_0_0), + .i_W_imag_0_0(Wym_imag_0_0), + .i_W_real_0_1(Wym_real_0_1), + .i_W_imag_0_1(Wym_imag_0_1), + .i_W_real_0_2(Wym_real_0_2), + .i_W_imag_0_2(Wym_imag_0_2), + .i_W_real_0_3(Wym_real_0_3), + .i_W_imag_0_3(Wym_imag_0_3), + .i_W_real_0_4(Wym_real_0_4), + .i_W_imag_0_4(Wym_imag_0_4), + .i_W_real_0_5(Wym_real_0_5), + .i_W_imag_0_5(Wym_imag_0_5), + .i_W_real_0_6(Wym_real_0_6), + .i_W_imag_0_6(Wym_imag_0_6), + .i_W_real_0_7(Wym_real_0_7), + .i_W_imag_0_7(Wym_imag_0_7), + .i_W_real_0_8(Wym_real_0_8), + .i_W_imag_0_8(Wym_imag_0_8), + .o_Y_0_0(o_Yt_0_0), + .o_Y_0_1(o_Yt_0_1), + .o_Y_0_2(o_Yt_0_2), + .o_Y_0_3(o_Yt_0_3), + .o_Y_0_4(o_Yt_0_4), + .o_Y_0_5(o_Yt_0_5), + .o_Y_0_6(o_Yt_0_6), + .o_Y_0_7(o_Yt_0_7), + .o_Y_0_8(o_Yt_0_8), + .o_Y_0_9(o_Yt_0_9), + .o_Y_0_10(o_Yt_0_10), + .o_Y_0_11(o_Yt_0_11), + .o_Y_0_12(o_Yt_0_12), + .o_Y_0_13(o_Yt_0_13), + .o_Y_0_14(o_Yt_0_14), + .o_Y_0_15(o_Yt_0_15), + .o_valid(o_valid), + .o_ready(o_ready) +); + +always @ (posedge clk) begin + if (reset) begin + reg_i_ready <= 1'b0; + end else begin + reg_i_ready <= i_ready; + end +end + +endmodule + +module stage3_parameter_buffer_18_1_16_64_2048 ( + input clk, + input reset, + input [161:0] wdata, + input [1:0] wen, + output [17:0] Wym_real_0_0, + output [17:0] Wym_imag_0_0, + output [17:0] Wym_real_0_1, + output [17:0] Wym_imag_0_1, + output [17:0] Wym_real_0_2, + output [17:0] Wym_imag_0_2, + output [17:0] Wym_real_0_3, + output [17:0] Wym_imag_0_3, + output [17:0] Wym_real_0_4, + output [17:0] Wym_imag_0_4, + output [17:0] Wym_real_0_5, + output [17:0] Wym_imag_0_5, + output [17:0] Wym_real_0_6, + output [17:0] Wym_imag_0_6, + output [17:0] Wym_real_0_7, + output [17:0] Wym_imag_0_7, + output [17:0] Wym_real_0_8, + output [17:0] Wym_imag_0_8, + input incr_index +); + +wire [13:0] input_index_counter; +counter_63_1 counter_63_1_inst_input ( + .clk(clk), + .reset(reset), + .ena(incr_index), + .count(input_index_counter) +); + +wire incr_row_index; +assign incr_row_index = (input_index_counter == 63 & incr_index); +wire [13:0] weight_row_index_counter; +counter_31_1 counter_31_1_inst_weight ( + .clk(clk), + .reset(reset), + .ena(incr_row_index), + .count(weight_row_index_counter) +); + +reg [13:0] weight_index; +always @ (*) begin + weight_index = weight_row_index_counter * 14'd64 + input_index_counter; +end +weight_buffer_18_9_1_64_2048_Wym_real_half_0 weight_buffer_18_9_1_64_2048_Wym_real_half_0_inst_gmjuexiqqp_real ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[0]), + .q_0_0(Wym_real_0_0), + .q_0_1(Wym_real_0_1), + .q_0_2(Wym_real_0_2), + .q_0_3(Wym_real_0_3), + .q_0_4(Wym_real_0_4), + .q_0_5(Wym_real_0_5), + .q_0_6(Wym_real_0_6), + .q_0_7(Wym_real_0_7), + .q_0_8(Wym_real_0_8), + .index(weight_index) +); + +weight_buffer_18_9_1_64_2048_Wym_imag_half_0 weight_buffer_18_9_1_64_2048_Wym_imag_half_0_inst_mloniuqjkh_imag ( + .clk(clk), + .rst(reset), + .wdata(wdata), + .wen(wen[1]), + .q_0_0(Wym_imag_0_0), + .q_0_1(Wym_imag_0_1), + .q_0_2(Wym_imag_0_2), + .q_0_3(Wym_imag_0_3), + .q_0_4(Wym_imag_0_4), + .q_0_5(Wym_imag_0_5), + .q_0_6(Wym_imag_0_6), + .q_0_7(Wym_imag_0_7), + .q_0_8(Wym_imag_0_8), + .index(weight_index) +); + +endmodule + +module counter_31_1 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 0; + end else if (ena) begin + if((count + 14'd1) <= 31) begin + count <= count + 14'd1; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module weight_buffer_18_9_1_64_2048_Wym_real_half_0 ( + input clk, + input rst, + input [161:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + input [10:0] index +); + +wire [161:0] packed_result_0; +reg [10:0] addrs_0; +reg [10:0] addrs_base_0; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + end else begin + addrs_0 <= index + addrs_base_0; + end +end + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; + +endmodule + +module weight_buffer_18_9_1_64_2048_Wym_imag_half_0 ( + input clk, + input rst, + input [161:0] wdata, + input wen, + output [17:0] q_0_0, + output [17:0] q_0_1, + output [17:0] q_0_2, + output [17:0] q_0_3, + output [17:0] q_0_4, + output [17:0] q_0_5, + output [17:0] q_0_6, + output [17:0] q_0_7, + output [17:0] q_0_8, + input [10:0] index +); + +wire [161:0] packed_result_0; +reg [10:0] addrs_0; +reg [10:0] addrs_base_0; + +always @ (posedge clk) begin + if (rst) begin + addrs_base_0 <= 0; + end else begin + addrs_0 <= index + addrs_base_0; + end +end + +spram #(.AWIDTH(11), .DWIDTH(162), .NUM_WORDS(1<<11)) ram_inst_0 ( + .we(wen), + .addr(addrs_0), + .data(wdata), + .out(packed_result_0), + .clk(clk) +); + +// Unpack result +assign q_0_0 = packed_result_0[17:0]; +assign q_0_1 = packed_result_0[35:18]; +assign q_0_2 = packed_result_0[53:36]; +assign q_0_3 = packed_result_0[71:54]; +assign q_0_4 = packed_result_0[89:72]; +assign q_0_5 = packed_result_0[107:90]; +assign q_0_6 = packed_result_0[125:108]; +assign q_0_7 = packed_result_0[143:126]; +assign q_0_8 = packed_result_0[161:144]; + +endmodule + +module multiple_c_matrix_vec_mult_and_sum_18_10_16_1_1_64 ( + input clk, + input reset, + input i_ready, + input i_valid, + input [17:0] i_X_0, + input [17:0] i_X_1, + input [17:0] i_X_2, + input [17:0] i_X_3, + input [17:0] i_X_4, + input [17:0] i_X_5, + input [17:0] i_X_6, + input [17:0] i_X_7, + input [17:0] i_X_8, + input [17:0] i_X_9, + input [17:0] i_X_10, + input [17:0] i_X_11, + input [17:0] i_X_12, + input [17:0] i_X_13, + input [17:0] i_X_14, + input [17:0] i_X_15, + input [17:0] i_W_real_0_0, + input [17:0] i_W_imag_0_0, + input [17:0] i_W_real_0_1, + input [17:0] i_W_imag_0_1, + input [17:0] i_W_real_0_2, + input [17:0] i_W_imag_0_2, + input [17:0] i_W_real_0_3, + input [17:0] i_W_imag_0_3, + input [17:0] i_W_real_0_4, + input [17:0] i_W_imag_0_4, + input [17:0] i_W_real_0_5, + input [17:0] i_W_imag_0_5, + input [17:0] i_W_real_0_6, + input [17:0] i_W_imag_0_6, + input [17:0] i_W_real_0_7, + input [17:0] i_W_imag_0_7, + input [17:0] i_W_real_0_8, + input [17:0] i_W_imag_0_8, + output [17:0] o_Y_0_0, + output [17:0] o_Y_0_1, + output [17:0] o_Y_0_2, + output [17:0] o_Y_0_3, + output [17:0] o_Y_0_4, + output [17:0] o_Y_0_5, + output [17:0] o_Y_0_6, + output [17:0] o_Y_0_7, + output [17:0] o_Y_0_8, + output [17:0] o_Y_0_9, + output [17:0] o_Y_0_10, + output [17:0] o_Y_0_11, + output [17:0] o_Y_0_12, + output [17:0] o_Y_0_13, + output [17:0] o_Y_0_14, + output [17:0] o_Y_0_15, + output o_valid, + output o_ready +); + +wire matrix_vec_mult_ready, matrix_vec_mult_valid; +wire accum_valid_0; +wire idft_next_out_0; +reg idft_out_valid; +wire [17:0] Y_imag_0_0; +wire [17:0] Y_real_0_0; +wire [17:0] sum_Y_real_0_0; +wire [17:0] sum_Y_imag_0_0; +wire [17:0] sum_Y_real_hold_0_0; +wire [17:0] sum_Y_imag_hold_0_0; +wire [17:0] out_Y_idft_0_0; +reg [17:0] reg_Y_0_0; +wire [17:0] Y_imag_0_1; +wire [17:0] Y_real_0_1; +wire [17:0] sum_Y_real_0_1; +wire [17:0] sum_Y_imag_0_1; +wire [17:0] sum_Y_real_hold_0_1; +wire [17:0] sum_Y_imag_hold_0_1; +wire [17:0] out_Y_idft_0_1; +reg [17:0] reg_Y_0_1; +wire [17:0] Y_imag_0_2; +wire [17:0] Y_real_0_2; +wire [17:0] sum_Y_real_0_2; +wire [17:0] sum_Y_imag_0_2; +wire [17:0] sum_Y_real_hold_0_2; +wire [17:0] sum_Y_imag_hold_0_2; +wire [17:0] out_Y_idft_0_2; +reg [17:0] reg_Y_0_2; +wire [17:0] Y_imag_0_3; +wire [17:0] Y_real_0_3; +wire [17:0] sum_Y_real_0_3; +wire [17:0] sum_Y_imag_0_3; +wire [17:0] sum_Y_real_hold_0_3; +wire [17:0] sum_Y_imag_hold_0_3; +wire [17:0] out_Y_idft_0_3; +reg [17:0] reg_Y_0_3; +wire [17:0] Y_imag_0_4; +wire [17:0] Y_real_0_4; +wire [17:0] sum_Y_real_0_4; +wire [17:0] sum_Y_imag_0_4; +wire [17:0] sum_Y_real_hold_0_4; +wire [17:0] sum_Y_imag_hold_0_4; +wire [17:0] out_Y_idft_0_4; +reg [17:0] reg_Y_0_4; +wire [17:0] Y_imag_0_5; +wire [17:0] Y_real_0_5; +wire [17:0] sum_Y_real_0_5; +wire [17:0] sum_Y_imag_0_5; +wire [17:0] sum_Y_real_hold_0_5; +wire [17:0] sum_Y_imag_hold_0_5; +wire [17:0] out_Y_idft_0_5; +reg [17:0] reg_Y_0_5; +wire [17:0] Y_imag_0_6; +wire [17:0] Y_real_0_6; +wire [17:0] sum_Y_real_0_6; +wire [17:0] sum_Y_imag_0_6; +wire [17:0] sum_Y_real_hold_0_6; +wire [17:0] sum_Y_imag_hold_0_6; +wire [17:0] out_Y_idft_0_6; +reg [17:0] reg_Y_0_6; +wire [17:0] Y_imag_0_7; +wire [17:0] Y_real_0_7; +wire [17:0] sum_Y_real_0_7; +wire [17:0] sum_Y_imag_0_7; +wire [17:0] sum_Y_real_hold_0_7; +wire [17:0] sum_Y_imag_hold_0_7; +wire [17:0] out_Y_idft_0_7; +reg [17:0] reg_Y_0_7; +wire [17:0] Y_imag_0_8; +wire [17:0] Y_real_0_8; +wire [17:0] sum_Y_real_0_8; +wire [17:0] sum_Y_imag_0_8; +wire [17:0] sum_Y_real_hold_0_8; +wire [17:0] sum_Y_imag_hold_0_8; +wire [17:0] out_Y_idft_0_8; +reg [17:0] reg_Y_0_8; +wire [17:0] Y_imag_0_9; +wire [17:0] Y_real_0_9; +wire [17:0] sum_Y_real_0_9; +wire [17:0] sum_Y_imag_0_9; +wire [17:0] sum_Y_real_hold_0_9; +wire [17:0] sum_Y_imag_hold_0_9; +wire [17:0] out_Y_idft_0_9; +reg [17:0] reg_Y_0_9; +wire [17:0] Y_imag_0_10; +wire [17:0] Y_real_0_10; +wire [17:0] sum_Y_real_0_10; +wire [17:0] sum_Y_imag_0_10; +wire [17:0] sum_Y_real_hold_0_10; +wire [17:0] sum_Y_imag_hold_0_10; +wire [17:0] out_Y_idft_0_10; +reg [17:0] reg_Y_0_10; +wire [17:0] Y_imag_0_11; +wire [17:0] Y_real_0_11; +wire [17:0] sum_Y_real_0_11; +wire [17:0] sum_Y_imag_0_11; +wire [17:0] sum_Y_real_hold_0_11; +wire [17:0] sum_Y_imag_hold_0_11; +wire [17:0] out_Y_idft_0_11; +reg [17:0] reg_Y_0_11; +wire [17:0] Y_imag_0_12; +wire [17:0] Y_real_0_12; +wire [17:0] sum_Y_real_0_12; +wire [17:0] sum_Y_imag_0_12; +wire [17:0] sum_Y_real_hold_0_12; +wire [17:0] sum_Y_imag_hold_0_12; +wire [17:0] out_Y_idft_0_12; +reg [17:0] reg_Y_0_12; +wire [17:0] Y_imag_0_13; +wire [17:0] Y_real_0_13; +wire [17:0] sum_Y_real_0_13; +wire [17:0] sum_Y_imag_0_13; +wire [17:0] sum_Y_real_hold_0_13; +wire [17:0] sum_Y_imag_hold_0_13; +wire [17:0] out_Y_idft_0_13; +reg [17:0] reg_Y_0_13; +wire [17:0] Y_imag_0_14; +wire [17:0] Y_real_0_14; +wire [17:0] sum_Y_real_0_14; +wire [17:0] sum_Y_imag_0_14; +wire [17:0] sum_Y_real_hold_0_14; +wire [17:0] sum_Y_imag_hold_0_14; +wire [17:0] out_Y_idft_0_14; +reg [17:0] reg_Y_0_14; +wire [17:0] Y_imag_0_15; +wire [17:0] Y_real_0_15; +wire [17:0] sum_Y_real_0_15; +wire [17:0] sum_Y_imag_0_15; +wire [17:0] sum_Y_real_hold_0_15; +wire [17:0] sum_Y_imag_hold_0_15; +wire [17:0] out_Y_idft_0_15; +reg [17:0] reg_Y_0_15; +reg reg_o_valid; + +// Enable whenever the reciever is ready +wire enable; +assign enable = i_ready; +c_matrix_vec_mult_core_18_10_16_1_1 c_matrix_vec_mult_core_18_10_16_1_1_inst_onagqdrvym ( + .clk(clk), + .reset(reset), + .i_ready(i_ready), + .i_valid(i_valid), + .i_X_0(i_X_0), + .i_X_1(i_X_1), + .i_X_2(i_X_2), + .i_X_3(i_X_3), + .i_X_4(i_X_4), + .i_X_5(i_X_5), + .i_X_6(i_X_6), + .i_X_7(i_X_7), + .i_X_8(i_X_8), + .i_X_9(i_X_9), + .i_X_10(i_X_10), + .i_X_11(i_X_11), + .i_X_12(i_X_12), + .i_X_13(i_X_13), + .i_X_14(i_X_14), + .i_X_15(i_X_15), + .i_W_real_0_0(i_W_real_0_0), + .i_W_imag_0_0(i_W_imag_0_0), + .i_W_real_0_1(i_W_real_0_1), + .i_W_imag_0_1(i_W_imag_0_1), + .i_W_real_0_2(i_W_real_0_2), + .i_W_imag_0_2(i_W_imag_0_2), + .i_W_real_0_3(i_W_real_0_3), + .i_W_imag_0_3(i_W_imag_0_3), + .i_W_real_0_4(i_W_real_0_4), + .i_W_imag_0_4(i_W_imag_0_4), + .i_W_real_0_5(i_W_real_0_5), + .i_W_imag_0_5(i_W_imag_0_5), + .i_W_real_0_6(i_W_real_0_6), + .i_W_imag_0_6(i_W_imag_0_6), + .i_W_real_0_7(i_W_real_0_7), + .i_W_imag_0_7(i_W_imag_0_7), + .i_W_real_0_8(i_W_real_0_8), + .i_W_imag_0_8(i_W_imag_0_8), + .o_Y_real_0_0(Y_real_0_0), + .o_Y_imag_0_0(Y_imag_0_0), + .o_Y_real_0_1(Y_real_0_1), + .o_Y_imag_0_1(Y_imag_0_1), + .o_Y_real_0_2(Y_real_0_2), + .o_Y_imag_0_2(Y_imag_0_2), + .o_Y_real_0_3(Y_real_0_3), + .o_Y_imag_0_3(Y_imag_0_3), + .o_Y_real_0_4(Y_real_0_4), + .o_Y_imag_0_4(Y_imag_0_4), + .o_Y_real_0_5(Y_real_0_5), + .o_Y_imag_0_5(Y_imag_0_5), + .o_Y_real_0_6(Y_real_0_6), + .o_Y_imag_0_6(Y_imag_0_6), + .o_Y_real_0_7(Y_real_0_7), + .o_Y_imag_0_7(Y_imag_0_7), + .o_Y_real_0_8(Y_real_0_8), + .o_Y_imag_0_8(Y_imag_0_8), + .o_Y_real_0_9(Y_real_0_9), + .o_Y_imag_0_9(Y_imag_0_9), + .o_Y_real_0_10(Y_real_0_10), + .o_Y_imag_0_10(Y_imag_0_10), + .o_Y_real_0_11(Y_real_0_11), + .o_Y_imag_0_11(Y_imag_0_11), + .o_Y_real_0_12(Y_real_0_12), + .o_Y_imag_0_12(Y_imag_0_12), + .o_Y_real_0_13(Y_real_0_13), + .o_Y_imag_0_13(Y_imag_0_13), + .o_Y_real_0_14(Y_real_0_14), + .o_Y_imag_0_14(Y_imag_0_14), + .o_Y_real_0_15(Y_real_0_15), + .o_Y_imag_0_15(Y_imag_0_15), + .o_ready(matrix_vec_mult_ready), + .o_valid(matrix_vec_mult_valid) +); + +sum_complex_vector_unit_18_18_16_64 sum_complex_vector_unit_18_18_16_64_inst_zveoqrdgbj ( + .clk(clk), + .clr(reset), + .enable(enable), + .i_valid(matrix_vec_mult_valid), + .i_real_0(Y_real_0_0), + .i_imag_0(Y_imag_0_0), + .o_real_0(sum_Y_real_0_0), + .o_imag_0(sum_Y_imag_0_0), + .i_real_1(Y_real_0_1), + .i_imag_1(Y_imag_0_1), + .o_real_1(sum_Y_real_0_1), + .o_imag_1(sum_Y_imag_0_1), + .i_real_2(Y_real_0_2), + .i_imag_2(Y_imag_0_2), + .o_real_2(sum_Y_real_0_2), + .o_imag_2(sum_Y_imag_0_2), + .i_real_3(Y_real_0_3), + .i_imag_3(Y_imag_0_3), + .o_real_3(sum_Y_real_0_3), + .o_imag_3(sum_Y_imag_0_3), + .i_real_4(Y_real_0_4), + .i_imag_4(Y_imag_0_4), + .o_real_4(sum_Y_real_0_4), + .o_imag_4(sum_Y_imag_0_4), + .i_real_5(Y_real_0_5), + .i_imag_5(Y_imag_0_5), + .o_real_5(sum_Y_real_0_5), + .o_imag_5(sum_Y_imag_0_5), + .i_real_6(Y_real_0_6), + .i_imag_6(Y_imag_0_6), + .o_real_6(sum_Y_real_0_6), + .o_imag_6(sum_Y_imag_0_6), + .i_real_7(Y_real_0_7), + .i_imag_7(Y_imag_0_7), + .o_real_7(sum_Y_real_0_7), + .o_imag_7(sum_Y_imag_0_7), + .i_real_8(Y_real_0_8), + .i_imag_8(Y_imag_0_8), + .o_real_8(sum_Y_real_0_8), + .o_imag_8(sum_Y_imag_0_8), + .i_real_9(Y_real_0_9), + .i_imag_9(Y_imag_0_9), + .o_real_9(sum_Y_real_0_9), + .o_imag_9(sum_Y_imag_0_9), + .i_real_10(Y_real_0_10), + .i_imag_10(Y_imag_0_10), + .o_real_10(sum_Y_real_0_10), + .o_imag_10(sum_Y_imag_0_10), + .i_real_11(Y_real_0_11), + .i_imag_11(Y_imag_0_11), + .o_real_11(sum_Y_real_0_11), + .o_imag_11(sum_Y_imag_0_11), + .i_real_12(Y_real_0_12), + .i_imag_12(Y_imag_0_12), + .o_real_12(sum_Y_real_0_12), + .o_imag_12(sum_Y_imag_0_12), + .i_real_13(Y_real_0_13), + .i_imag_13(Y_imag_0_13), + .o_real_13(sum_Y_real_0_13), + .o_imag_13(sum_Y_imag_0_13), + .i_real_14(Y_real_0_14), + .i_imag_14(Y_imag_0_14), + .o_real_14(sum_Y_real_0_14), + .o_imag_14(sum_Y_imag_0_14), + .i_real_15(Y_real_0_15), + .i_imag_15(Y_imag_0_15), + .o_real_15(sum_Y_real_0_15), + .o_imag_15(sum_Y_imag_0_15), + .o_valid(accum_valid_0) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_oectpttmgb_real ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_real_0_0), + .out_0(sum_Y_real_hold_0_0), + .in_1(sum_Y_real_0_1), + .out_1(sum_Y_real_hold_0_1), + .in_2(sum_Y_real_0_2), + .out_2(sum_Y_real_hold_0_2), + .in_3(sum_Y_real_0_3), + .out_3(sum_Y_real_hold_0_3), + .in_4(sum_Y_real_0_4), + .out_4(sum_Y_real_hold_0_4), + .in_5(sum_Y_real_0_5), + .out_5(sum_Y_real_hold_0_5), + .in_6(sum_Y_real_0_6), + .out_6(sum_Y_real_hold_0_6), + .in_7(sum_Y_real_0_7), + .out_7(sum_Y_real_hold_0_7), + .in_8(sum_Y_real_0_8), + .out_8(sum_Y_real_hold_0_8), + .in_9(sum_Y_real_0_9), + .out_9(sum_Y_real_hold_0_9), + .in_10(sum_Y_real_0_10), + .out_10(sum_Y_real_hold_0_10), + .in_11(sum_Y_real_0_11), + .out_11(sum_Y_real_hold_0_11), + .in_12(sum_Y_real_0_12), + .out_12(sum_Y_real_hold_0_12), + .in_13(sum_Y_real_0_13), + .out_13(sum_Y_real_hold_0_13), + .in_14(sum_Y_real_0_14), + .out_14(sum_Y_real_hold_0_14), + .in_15(sum_Y_real_0_15), + .out_15(sum_Y_real_hold_0_15), + .reset(reset) +); + +shift_register_group_18_16_1 shift_register_group_18_16_1_inst_vcffnsbnfx_imag ( + .clk(clk), + .enable(enable), + .in_0(sum_Y_imag_0_0), + .out_0(sum_Y_imag_hold_0_0), + .in_1(sum_Y_imag_0_1), + .out_1(sum_Y_imag_hold_0_1), + .in_2(sum_Y_imag_0_2), + .out_2(sum_Y_imag_hold_0_2), + .in_3(sum_Y_imag_0_3), + .out_3(sum_Y_imag_hold_0_3), + .in_4(sum_Y_imag_0_4), + .out_4(sum_Y_imag_hold_0_4), + .in_5(sum_Y_imag_0_5), + .out_5(sum_Y_imag_hold_0_5), + .in_6(sum_Y_imag_0_6), + .out_6(sum_Y_imag_hold_0_6), + .in_7(sum_Y_imag_0_7), + .out_7(sum_Y_imag_hold_0_7), + .in_8(sum_Y_imag_0_8), + .out_8(sum_Y_imag_hold_0_8), + .in_9(sum_Y_imag_0_9), + .out_9(sum_Y_imag_hold_0_9), + .in_10(sum_Y_imag_0_10), + .out_10(sum_Y_imag_hold_0_10), + .in_11(sum_Y_imag_0_11), + .out_11(sum_Y_imag_hold_0_11), + .in_12(sum_Y_imag_0_12), + .out_12(sum_Y_imag_hold_0_12), + .in_13(sum_Y_imag_0_13), + .out_13(sum_Y_imag_hold_0_13), + .in_14(sum_Y_imag_0_14), + .out_14(sum_Y_imag_hold_0_14), + .in_15(sum_Y_imag_0_15), + .out_15(sum_Y_imag_hold_0_15), + .reset(reset) +); + +idft_16_top_18 idft_16_top_18_inst_odzdqwqjpl ( + .clk(clk), + .reset(reset), + .next(accum_valid_0), + .X0(sum_Y_real_hold_0_0), + .Y0(out_Y_idft_0_0), + .X1(sum_Y_imag_hold_0_0), + .Y1(), + .X2(sum_Y_real_hold_0_1), + .Y2(out_Y_idft_0_1), + .X3(sum_Y_imag_hold_0_1), + .Y3(), + .X4(sum_Y_real_hold_0_2), + .Y4(out_Y_idft_0_2), + .X5(sum_Y_imag_hold_0_2), + .Y5(), + .X6(sum_Y_real_hold_0_3), + .Y6(out_Y_idft_0_3), + .X7(sum_Y_imag_hold_0_3), + .Y7(), + .X8(sum_Y_real_hold_0_4), + .Y8(out_Y_idft_0_4), + .X9(sum_Y_imag_hold_0_4), + .Y9(), + .X10(sum_Y_real_hold_0_5), + .Y10(out_Y_idft_0_5), + .X11(sum_Y_imag_hold_0_5), + .Y11(), + .X12(sum_Y_real_hold_0_6), + .Y12(out_Y_idft_0_6), + .X13(sum_Y_imag_hold_0_6), + .Y13(), + .X14(sum_Y_real_hold_0_7), + .Y14(out_Y_idft_0_7), + .X15(sum_Y_imag_hold_0_7), + .Y15(), + .X16(sum_Y_real_hold_0_8), + .Y16(out_Y_idft_0_8), + .X17(sum_Y_imag_hold_0_8), + .Y17(), + .X18(sum_Y_real_hold_0_9), + .Y18(out_Y_idft_0_9), + .X19(sum_Y_imag_hold_0_9), + .Y19(), + .X20(sum_Y_real_hold_0_10), + .Y20(out_Y_idft_0_10), + .X21(sum_Y_imag_hold_0_10), + .Y21(), + .X22(sum_Y_real_hold_0_11), + .Y22(out_Y_idft_0_11), + .X23(sum_Y_imag_hold_0_11), + .Y23(), + .X24(sum_Y_real_hold_0_12), + .Y24(out_Y_idft_0_12), + .X25(sum_Y_imag_hold_0_12), + .Y25(), + .X26(sum_Y_real_hold_0_13), + .Y26(out_Y_idft_0_13), + .X27(sum_Y_imag_hold_0_13), + .Y27(), + .X28(sum_Y_real_hold_0_14), + .Y28(out_Y_idft_0_14), + .X29(sum_Y_imag_hold_0_14), + .Y29(), + .X30(sum_Y_real_hold_0_15), + .Y30(out_Y_idft_0_15), + .X31(sum_Y_imag_hold_0_15), + .Y31(), + .next_out(idft_next_out_0) +); + +always @ (posedge clk) begin + if (reset) begin + reg_Y_0_0 <= 0; + reg_Y_0_1 <= 0; + reg_Y_0_2 <= 0; + reg_Y_0_3 <= 0; + reg_Y_0_4 <= 0; + reg_Y_0_5 <= 0; + reg_Y_0_6 <= 0; + reg_Y_0_7 <= 0; + reg_Y_0_8 <= 0; + reg_Y_0_9 <= 0; + reg_Y_0_10 <= 0; + reg_Y_0_11 <= 0; + reg_Y_0_12 <= 0; + reg_Y_0_13 <= 0; + reg_Y_0_14 <= 0; + reg_Y_0_15 <= 0; + idft_out_valid <= 1'b0; + reg_o_valid <= 1'b0; + end else if (enable) begin + reg_Y_0_0 <= (out_Y_idft_0_0 >>> 4); + reg_Y_0_1 <= (out_Y_idft_0_1 >>> 4); + reg_Y_0_2 <= (out_Y_idft_0_2 >>> 4); + reg_Y_0_3 <= (out_Y_idft_0_3 >>> 4); + reg_Y_0_4 <= (out_Y_idft_0_4 >>> 4); + reg_Y_0_5 <= (out_Y_idft_0_5 >>> 4); + reg_Y_0_6 <= (out_Y_idft_0_6 >>> 4); + reg_Y_0_7 <= (out_Y_idft_0_7 >>> 4); + reg_Y_0_8 <= (out_Y_idft_0_8 >>> 4); + reg_Y_0_9 <= (out_Y_idft_0_9 >>> 4); + reg_Y_0_10 <= (out_Y_idft_0_10 >>> 4); + reg_Y_0_11 <= (out_Y_idft_0_11 >>> 4); + reg_Y_0_12 <= (out_Y_idft_0_12 >>> 4); + reg_Y_0_13 <= (out_Y_idft_0_13 >>> 4); + reg_Y_0_14 <= (out_Y_idft_0_14 >>> 4); + reg_Y_0_15 <= (out_Y_idft_0_15 >>> 4); + idft_out_valid <= idft_next_out_0; + reg_o_valid <= idft_out_valid; + end +end + +assign o_valid = enable & reg_o_valid; +assign o_ready = matrix_vec_mult_ready; +assign o_Y_0_0 = reg_Y_0_0; +assign o_Y_0_1 = reg_Y_0_1; +assign o_Y_0_2 = reg_Y_0_2; +assign o_Y_0_3 = reg_Y_0_3; +assign o_Y_0_4 = reg_Y_0_4; +assign o_Y_0_5 = reg_Y_0_5; +assign o_Y_0_6 = reg_Y_0_6; +assign o_Y_0_7 = reg_Y_0_7; +assign o_Y_0_8 = reg_Y_0_8; +assign o_Y_0_9 = reg_Y_0_9; +assign o_Y_0_10 = reg_Y_0_10; +assign o_Y_0_11 = reg_Y_0_11; +assign o_Y_0_12 = reg_Y_0_12; +assign o_Y_0_13 = reg_Y_0_13; +assign o_Y_0_14 = reg_Y_0_14; +assign o_Y_0_15 = reg_Y_0_15; + +endmodule + +module sum_complex_vector_unit_18_18_16_64 ( + input clk, + input clr, + input i_valid, + input enable, + input [17:0] i_real_0, + input [17:0] i_imag_0, + output [17:0] o_real_0, + output [17:0] o_imag_0, + input [17:0] i_real_1, + input [17:0] i_imag_1, + output [17:0] o_real_1, + output [17:0] o_imag_1, + input [17:0] i_real_2, + input [17:0] i_imag_2, + output [17:0] o_real_2, + output [17:0] o_imag_2, + input [17:0] i_real_3, + input [17:0] i_imag_3, + output [17:0] o_real_3, + output [17:0] o_imag_3, + input [17:0] i_real_4, + input [17:0] i_imag_4, + output [17:0] o_real_4, + output [17:0] o_imag_4, + input [17:0] i_real_5, + input [17:0] i_imag_5, + output [17:0] o_real_5, + output [17:0] o_imag_5, + input [17:0] i_real_6, + input [17:0] i_imag_6, + output [17:0] o_real_6, + output [17:0] o_imag_6, + input [17:0] i_real_7, + input [17:0] i_imag_7, + output [17:0] o_real_7, + output [17:0] o_imag_7, + input [17:0] i_real_8, + input [17:0] i_imag_8, + output [17:0] o_real_8, + output [17:0] o_imag_8, + input [17:0] i_real_9, + input [17:0] i_imag_9, + output [17:0] o_real_9, + output [17:0] o_imag_9, + input [17:0] i_real_10, + input [17:0] i_imag_10, + output [17:0] o_real_10, + output [17:0] o_imag_10, + input [17:0] i_real_11, + input [17:0] i_imag_11, + output [17:0] o_real_11, + output [17:0] o_imag_11, + input [17:0] i_real_12, + input [17:0] i_imag_12, + output [17:0] o_real_12, + output [17:0] o_imag_12, + input [17:0] i_real_13, + input [17:0] i_imag_13, + output [17:0] o_real_13, + output [17:0] o_imag_13, + input [17:0] i_real_14, + input [17:0] i_imag_14, + output [17:0] o_real_14, + output [17:0] o_imag_14, + input [17:0] i_real_15, + input [17:0] i_imag_15, + output [17:0] o_real_15, + output [17:0] o_imag_15, + output o_valid +); + +reg [17:0] sum_real_0; +reg [17:0] sum_imag_0; +reg [17:0] sum_real_1; +reg [17:0] sum_imag_1; +reg [17:0] sum_real_2; +reg [17:0] sum_imag_2; +reg [17:0] sum_real_3; +reg [17:0] sum_imag_3; +reg [17:0] sum_real_4; +reg [17:0] sum_imag_4; +reg [17:0] sum_real_5; +reg [17:0] sum_imag_5; +reg [17:0] sum_real_6; +reg [17:0] sum_imag_6; +reg [17:0] sum_real_7; +reg [17:0] sum_imag_7; +reg [17:0] sum_real_8; +reg [17:0] sum_imag_8; +reg [17:0] sum_real_9; +reg [17:0] sum_imag_9; +reg [17:0] sum_real_10; +reg [17:0] sum_imag_10; +reg [17:0] sum_real_11; +reg [17:0] sum_imag_11; +reg [17:0] sum_real_12; +reg [17:0] sum_imag_12; +reg [17:0] sum_real_13; +reg [17:0] sum_imag_13; +reg [17:0] sum_real_14; +reg [17:0] sum_imag_14; +reg [17:0] sum_real_15; +reg [17:0] sum_imag_15; +reg reg_i_valid; + +// Count the number data in accumulation +reg [13:0] counter; +wire counter_full; +always @ (posedge clk) begin + if (clr) begin + sum_real_0 <= 0; + sum_imag_0 <= 0; + sum_real_1 <= 0; + sum_imag_1 <= 0; + sum_real_2 <= 0; + sum_imag_2 <= 0; + sum_real_3 <= 0; + sum_imag_3 <= 0; + sum_real_4 <= 0; + sum_imag_4 <= 0; + sum_real_5 <= 0; + sum_imag_5 <= 0; + sum_real_6 <= 0; + sum_imag_6 <= 0; + sum_real_7 <= 0; + sum_imag_7 <= 0; + sum_real_8 <= 0; + sum_imag_8 <= 0; + sum_real_9 <= 0; + sum_imag_9 <= 0; + sum_real_10 <= 0; + sum_imag_10 <= 0; + sum_real_11 <= 0; + sum_imag_11 <= 0; + sum_real_12 <= 0; + sum_imag_12 <= 0; + sum_real_13 <= 0; + sum_imag_13 <= 0; + sum_real_14 <= 0; + sum_imag_14 <= 0; + sum_real_15 <= 0; + sum_imag_15 <= 0; + counter <= 14'd0; + reg_i_valid <= 1'b0; + end else if (enable) begin + reg_i_valid <= i_valid; + // Accumulate the number only when data is valid + if (i_valid) begin + if (counter == 64) + counter <= 1; + else + counter <= counter + 1'b1; + + if (counter == 64) begin + sum_real_0 <= i_real_0; + sum_imag_0 <= i_imag_0; + sum_real_1 <= i_real_1; + sum_imag_1 <= i_imag_1; + sum_real_2 <= i_real_2; + sum_imag_2 <= i_imag_2; + sum_real_3 <= i_real_3; + sum_imag_3 <= i_imag_3; + sum_real_4 <= i_real_4; + sum_imag_4 <= i_imag_4; + sum_real_5 <= i_real_5; + sum_imag_5 <= i_imag_5; + sum_real_6 <= i_real_6; + sum_imag_6 <= i_imag_6; + sum_real_7 <= i_real_7; + sum_imag_7 <= i_imag_7; + sum_real_8 <= i_real_8; + sum_imag_8 <= i_imag_8; + sum_real_9 <= i_real_9; + sum_imag_9 <= i_imag_9; + sum_real_10 <= i_real_10; + sum_imag_10 <= i_imag_10; + sum_real_11 <= i_real_11; + sum_imag_11 <= i_imag_11; + sum_real_12 <= i_real_12; + sum_imag_12 <= i_imag_12; + sum_real_13 <= i_real_13; + sum_imag_13 <= i_imag_13; + sum_real_14 <= i_real_14; + sum_imag_14 <= i_imag_14; + sum_real_15 <= i_real_15; + sum_imag_15 <= i_imag_15; + end else begin + sum_real_0 <= sum_real_0 + i_real_0; + sum_imag_0 <= sum_imag_0 + i_imag_0; + sum_real_1 <= sum_real_1 + i_real_1; + sum_imag_1 <= sum_imag_1 + i_imag_1; + sum_real_2 <= sum_real_2 + i_real_2; + sum_imag_2 <= sum_imag_2 + i_imag_2; + sum_real_3 <= sum_real_3 + i_real_3; + sum_imag_3 <= sum_imag_3 + i_imag_3; + sum_real_4 <= sum_real_4 + i_real_4; + sum_imag_4 <= sum_imag_4 + i_imag_4; + sum_real_5 <= sum_real_5 + i_real_5; + sum_imag_5 <= sum_imag_5 + i_imag_5; + sum_real_6 <= sum_real_6 + i_real_6; + sum_imag_6 <= sum_imag_6 + i_imag_6; + sum_real_7 <= sum_real_7 + i_real_7; + sum_imag_7 <= sum_imag_7 + i_imag_7; + sum_real_8 <= sum_real_8 + i_real_8; + sum_imag_8 <= sum_imag_8 + i_imag_8; + sum_real_9 <= sum_real_9 + i_real_9; + sum_imag_9 <= sum_imag_9 + i_imag_9; + sum_real_10 <= sum_real_10 + i_real_10; + sum_imag_10 <= sum_imag_10 + i_imag_10; + sum_real_11 <= sum_real_11 + i_real_11; + sum_imag_11 <= sum_imag_11 + i_imag_11; + sum_real_12 <= sum_real_12 + i_real_12; + sum_imag_12 <= sum_imag_12 + i_imag_12; + sum_real_13 <= sum_real_13 + i_real_13; + sum_imag_13 <= sum_imag_13 + i_imag_13; + sum_real_14 <= sum_real_14 + i_real_14; + sum_imag_14 <= sum_imag_14 + i_imag_14; + sum_real_15 <= sum_real_15 + i_real_15; + sum_imag_15 <= sum_imag_15 + i_imag_15; + end + end + end +end + +assign counter_full = (counter == 64); +assign o_real_0 = sum_real_0; +assign o_imag_0 = sum_imag_0; +assign o_real_1 = sum_real_1; +assign o_imag_1 = sum_imag_1; +assign o_real_2 = sum_real_2; +assign o_imag_2 = sum_imag_2; +assign o_real_3 = sum_real_3; +assign o_imag_3 = sum_imag_3; +assign o_real_4 = sum_real_4; +assign o_imag_4 = sum_imag_4; +assign o_real_5 = sum_real_5; +assign o_imag_5 = sum_imag_5; +assign o_real_6 = sum_real_6; +assign o_imag_6 = sum_imag_6; +assign o_real_7 = sum_real_7; +assign o_imag_7 = sum_imag_7; +assign o_real_8 = sum_real_8; +assign o_imag_8 = sum_imag_8; +assign o_real_9 = sum_real_9; +assign o_imag_9 = sum_imag_9; +assign o_real_10 = sum_real_10; +assign o_imag_10 = sum_imag_10; +assign o_real_11 = sum_real_11; +assign o_imag_11 = sum_imag_11; +assign o_real_12 = sum_real_12; +assign o_imag_12 = sum_imag_12; +assign o_real_13 = sum_real_13; +assign o_imag_13 = sum_imag_13; +assign o_real_14 = sum_real_14; +assign o_imag_14 = sum_imag_14; +assign o_real_15 = sum_real_15; +assign o_imag_15 = sum_imag_15; +assign o_valid = counter_full & reg_i_valid; + +endmodule + +module stage3_X_Y_buffer_18_16_1_10_32_64 ( + input clk, + input reset, + input i_X_valid, + input i_Y_valid, + input feed_start, + input [17:0] i_X_data_0, + input [17:0] i_Y_data_0, + output [17:0] o_data_0, + input [17:0] i_X_data_1, + input [17:0] i_Y_data_1, + output [17:0] o_data_1, + input [17:0] i_X_data_2, + input [17:0] i_Y_data_2, + output [17:0] o_data_2, + input [17:0] i_X_data_3, + input [17:0] i_Y_data_3, + output [17:0] o_data_3, + input [17:0] i_X_data_4, + input [17:0] i_Y_data_4, + output [17:0] o_data_4, + input [17:0] i_X_data_5, + input [17:0] i_Y_data_5, + output [17:0] o_data_5, + input [17:0] i_X_data_6, + input [17:0] i_Y_data_6, + output [17:0] o_data_6, + input [17:0] i_X_data_7, + input [17:0] i_Y_data_7, + output [17:0] o_data_7, + input [17:0] i_X_data_8, + input [17:0] i_Y_data_8, + output [17:0] o_data_8, + input [17:0] i_X_data_9, + input [17:0] i_Y_data_9, + output [17:0] o_data_9, + input [17:0] i_X_data_10, + input [17:0] i_Y_data_10, + output [17:0] o_data_10, + input [17:0] i_X_data_11, + input [17:0] i_Y_data_11, + output [17:0] o_data_11, + input [17:0] i_X_data_12, + input [17:0] i_Y_data_12, + output [17:0] o_data_12, + input [17:0] i_X_data_13, + input [17:0] i_Y_data_13, + output [17:0] o_data_13, + input [17:0] i_X_data_14, + input [17:0] i_Y_data_14, + output [17:0] o_data_14, + input [17:0] i_X_data_15, + input [17:0] i_Y_data_15, + output [17:0] o_data_15, + output o_valid, + output o_ready +); + +reg reg_feed_start; +reg [17:0] i_data_0; +reg [17:0] i_data_1; +reg [17:0] i_data_2; +reg [17:0] i_data_3; +reg [17:0] i_data_4; +reg [17:0] i_data_5; +reg [17:0] i_data_6; +reg [17:0] i_data_7; +reg [17:0] i_data_8; +reg [17:0] i_data_9; +reg [17:0] i_data_10; +reg [17:0] i_data_11; +reg [17:0] i_data_12; +reg [17:0] i_data_13; +reg [17:0] i_data_14; +reg [17:0] i_data_15; +wire [287:0] packed_o_data; +wire [287:0] packed_data; +reg wen; +wire ready_to_accept_new_X; +wire [13:0] input_index_counter; +assign ready_to_accept_new_X = (input_index_counter >= 32); +assign o_ready = ready_to_accept_new_X; +always @ (*) begin + if(ready_to_accept_new_X) begin + wen <= i_X_valid; + i_data_0 <= i_X_data_0; + i_data_1 <= i_X_data_1; + i_data_2 <= i_X_data_2; + i_data_3 <= i_X_data_3; + i_data_4 <= i_X_data_4; + i_data_5 <= i_X_data_5; + i_data_6 <= i_X_data_6; + i_data_7 <= i_X_data_7; + i_data_8 <= i_X_data_8; + i_data_9 <= i_X_data_9; + i_data_10 <= i_X_data_10; + i_data_11 <= i_X_data_11; + i_data_12 <= i_X_data_12; + i_data_13 <= i_X_data_13; + i_data_14 <= i_X_data_14; + i_data_15 <= i_X_data_15; + end else begin + wen <= i_Y_valid; + i_data_0 <= i_Y_data_0; + i_data_1 <= i_Y_data_1; + i_data_2 <= i_Y_data_2; + i_data_3 <= i_Y_data_3; + i_data_4 <= i_Y_data_4; + i_data_5 <= i_Y_data_5; + i_data_6 <= i_Y_data_6; + i_data_7 <= i_Y_data_7; + i_data_8 <= i_Y_data_8; + i_data_9 <= i_Y_data_9; + i_data_10 <= i_Y_data_10; + i_data_11 <= i_Y_data_11; + i_data_12 <= i_Y_data_12; + i_data_13 <= i_Y_data_13; + i_data_14 <= i_Y_data_14; + i_data_15 <= i_Y_data_15; + end +end + +assign o_data_0 = packed_o_data[17:0]; +assign packed_data[17:0] = i_data_0; +assign o_data_1 = packed_o_data[35:18]; +assign packed_data[35:18] = i_data_1; +assign o_data_2 = packed_o_data[53:36]; +assign packed_data[53:36] = i_data_2; +assign o_data_3 = packed_o_data[71:54]; +assign packed_data[71:54] = i_data_3; +assign o_data_4 = packed_o_data[89:72]; +assign packed_data[89:72] = i_data_4; +assign o_data_5 = packed_o_data[107:90]; +assign packed_data[107:90] = i_data_5; +assign o_data_6 = packed_o_data[125:108]; +assign packed_data[125:108] = i_data_6; +assign o_data_7 = packed_o_data[143:126]; +assign packed_data[143:126] = i_data_7; +assign o_data_8 = packed_o_data[161:144]; +assign packed_data[161:144] = i_data_8; +assign o_data_9 = packed_o_data[179:162]; +assign packed_data[179:162] = i_data_9; +assign o_data_10 = packed_o_data[197:180]; +assign packed_data[197:180] = i_data_10; +assign o_data_11 = packed_o_data[215:198]; +assign packed_data[215:198] = i_data_11; +assign o_data_12 = packed_o_data[233:216]; +assign packed_data[233:216] = i_data_12; +assign o_data_13 = packed_o_data[251:234]; +assign packed_data[251:234] = i_data_13; +assign o_data_14 = packed_o_data[269:252]; +assign packed_data[269:252] = i_data_14; +assign o_data_15 = packed_o_data[287:270]; +assign packed_data[287:270] = i_data_15; +counter_41_1_32 counter_41_1_32_inst_fwkgmzszuy ( + .clk(clk), + .reset(reset), + .ena(wen), + .count(input_index_counter) +); + +wire [13:0] output_index_counter; +reg en_output_counter; +counter_41_1 counter_41_1_inst_qnhhncvarb ( + .clk(clk), + .reset(reset), + .ena(en_output_counter), + .count(output_index_counter) +); + +wire incr_loop_index; +assign incr_loop_index = (output_index_counter == 41 && en_output_counter); +reg output_finish; +wire [13:0] loop_counter; +counter_63_1 counter_63_1_inst_loop ( + .clk(clk), + .reset(reset), + .ena(incr_loop_index), + .count(loop_counter) +); + +ram_18_0_42 ram_18_0_42_inst_uahdxwtmbr ( + .clk(clk), + .waddr(input_index_counter), + .wdata(packed_data), + .wen(wen), + .raddr(output_index_counter), + .q(packed_o_data) +); + +shift_register_unit_1_2 shift_register_unit_1_2_inst_afurwsscuf ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .in(en_output_counter), + .out(o_valid) +); + +always @ (posedge clk) begin + if (reset) begin + en_output_counter <= 1'b0; + output_finish <= 1'b0; + reg_feed_start <= 1'b0; + end else begin + en_output_counter <= (reg_feed_start && ~en_output_counter && ~output_finish); + if(feed_start) + reg_feed_start <= 1'b1; + else if (output_finish) + reg_feed_start <= 1'b0; + if ((loop_counter == 63) + &&(output_index_counter == 41) + && en_output_counter) + output_finish <= 1'b1; + else if (loop_counter == 0 && wen) + output_finish <= 1'b0; + end +end + +endmodule + +module counter_41_1_32 ( + input clk, + input reset, + input ena, + output reg [13:0] count +); + +always @ (posedge clk) begin + if (reset) begin + count <= 32; + end else if (ena) begin + if((count + 14'd1) <= 41) begin + count <= count + 14'd1; + end else begin + count <= 14'd0; + end + end +end + +endmodule + +module ram_18_0_42 ( + input clk, + input [4:0] waddr, + input [17:0] wdata, + input wen, + input [4:0] raddr, + output [17:0] q +); + +wire [17:0] rd_dummy_signal; +wire [17:0] wr_dummy_signal; +assign rd_dummy_signal = 0; + +dpram # (.AWIDTH(5), .DWIDTH(18), .NUM_WORDS(1<<5)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(q), + .clk(clk) +); +endmodule + +module shift_register_unit_1_2 ( + input clk, + input reset, + input enable, + input [0:0] in, + output [0:0] out +); + +reg [0:0] shift_registers_0; +reg [0:0] shift_registers_1; +always @ (posedge clk) begin + if (reset) begin + shift_registers_0 <= 1'd0; + shift_registers_1 <= 1'd0; + end else if (enable) begin + shift_registers_0 <= in; + shift_registers_1 <= shift_registers_0; + end +end + +assign out = shift_registers_1; + +endmodule + diff --git a/designs/koios/clstm_like.small/clstm_random.sv b/designs/koios/clstm_like.small/clstm_random.sv new file mode 100644 index 000000000..e2cd7b25b --- /dev/null +++ b/designs/koios/clstm_like.small/clstm_random.sv @@ -0,0 +1,102 @@ +/* +Random inputs to clstm +*/ + +`include "../../random_number_generator.sv" + +module clstm_random( + input logic clk, + input logic rst, + input logic [7:0] wen_stage1, + input logic [6:0] wen_stage2, + input logic [1:0] wen_stage3, + input logic i_ready, + input logic i_valid, + input logic start_compute, + output logic o_valid, + output logic o_ready, + output logic [17:0] data, + input logic [3:0] data_sel1 +); + +logic [161:0] wdata_stage1; +RandomNumberGenerator #(162, 0) rng1 ( + .clk(clk), + .reset(rst), + .random_number(wdata_stage1) +); + +logic [287:0] wdata_stage2; +RandomNumberGenerator #(288, 1) rng2 ( + .clk(clk), + .reset(rst), + .random_number(wdata_stage2) +); + +logic [161:0] wdata_stage3; +RandomNumberGenerator #(162, 3) rng3 ( + .clk(clk), + .reset(rst), + .random_number(wdata_stage3) +); + +logic [17:0] i_X_data [15:0]; +generate + genvar i; + for (i = 0; i < 16; i = i + 1) begin: gen_X_data + RandomNumberGenerator #(18, i) rng_X_data ( + .clk(clk), + .reset(rst), + .random_number(i_X_data[i]) + ); + end +endgenerate + +logic [17:0] o_sel [15:0]; +assign data = o_sel[data_sel1[3:0]]; + +C_LSTM_datapath ( + clk, + rst, + wdata_stage1, + wen_stage1, + wdata_stage2, + wen_stage2, + wdata_stage3, + wen_stage3, + i_X_data[0], + i_X_data[1], + i_X_data[2], + i_X_data[3], + i_X_data[4], + i_X_data[5], + i_X_data[6], + i_X_data[7], + i_X_data[8], + i_X_data[9], + i_X_data[10], + i_X_data[11], + i_X_data[12], + i_X_data[13], + i_X_data[14], + i_X_data[15], + o_sel[0][0], + o_sel[0][1], + o_sel[0][2], + o_sel[0][3], + o_sel[0][4], + o_sel[0][5], + o_sel[0][6], + o_sel[0][7], + o_sel[0][8], + o_sel[0][9], + o_sel[0][10], + o_sel[0][11], + o_sel[0][12], + o_sel[0][13], + o_sel[0][14], + o_sel[0][15] +); + + +endmodule \ No newline at end of file diff --git a/designs/koios/clstm_like.small/design.yaml b/designs/koios/clstm_like.small/design.yaml new file mode 100644 index 000000000..4b726b0fb --- /dev/null +++ b/designs/koios/clstm_like.small/design.yaml @@ -0,0 +1 @@ +top: clstm_random diff --git a/designs/koios/conv_layer/conv_layer.v b/designs/koios/conv_layer/conv_layer.v new file mode 100644 index 000000000..a6b15bbd8 --- /dev/null +++ b/designs/koios/conv_layer/conv_layer.v @@ -0,0 +1,2869 @@ +////////////////////////////////////////////////////////////////////////////// +// Convolution layer accelerator design. +// 1. 16-bit integer precision is used +// 2. Convolution lowered into matrix multiplication. Uses tiling and elementwise addition of partial products. +// 3. An 8x8 fp16 input image with 3 channels, padding=1, stride=1, filter size = 3x3 and batch size=2. +////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////// +// Author: Aman Arora +////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/1ns +//`define complex_dsp 1 +`define DWIDTH 16 +`define AWIDTH 10 +`define MEM_SIZE 1024 +`define DESIGN_SIZE 8 +`define MAT_MUL_SIZE 4 +`define MASK_WIDTH 4 +`define LOG2_MAT_MUL_SIZE 2 +`define NUM_CYCLES_IN_MAC 3 +`define MEM_ACCESS_LATENCY 1 +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 +`define ADDR_STRIDE_WIDTH 16 +`define REG_STDN_TPU_ADDR 32'h4 +`define REG_MATRIX_A_ADDR 32'he +`define REG_MATRIX_B_ADDR 32'h12 +`define REG_MATRIX_C_ADDR 32'h16 +`define REG_VALID_MASK_A_ROWS_ADDR 32'h20 +`define REG_VALID_MASK_A_COLS_ADDR 32'h54 +`define REG_VALID_MASK_B_ROWS_ADDR 32'h5c +`define REG_VALID_MASK_B_COLS_ADDR 32'h58 +`define REG_MATRIX_A_STRIDE_ADDR 32'h28 +`define REG_MATRIX_B_STRIDE_ADDR 32'h32 +`define REG_MATRIX_C_STRIDE_ADDR 32'h36 +`define ADDRESS_BASE_A 10'd0 +`define ADDRESS_BASE_B 10'd0 +`define ADDRESS_BASE_C 10'd0 + +module conv_layer( + input clk, + input clk_mem, + input resetn, + input pe_resetn, + input start, + output reg done, + input [7:0] bram_select, + input [`AWIDTH-1:0] bram_addr_ext, + output reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_ext, + input [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_ext, + input [`MAT_MUL_SIZE-1:0] bram_we_ext +); + + + //wire PCLK; + //assign PCLK = clk; + //Dummy register to sync all other invalid/unimplemented addresses + reg [`REG_DATAWIDTH-1:0] reg_dummy; + +wire reset; +assign reset = ~resetn; +wire pe_reset; +assign pe_reset = ~pe_resetn; + + + reg pe_reset_0; + reg start_mat_mul_0; + wire done_mat_mul_0; + reg [`AWIDTH-1:0] address_mat_a_0; + reg [`AWIDTH-1:0] address_mat_b_0; + reg [`AWIDTH-1:0] address_mat_c_0; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a_0; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b_0; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c_0; + wire [3:0] flags_NC_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in_0_NC; + assign a_data_in_0_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in_0_NC; + assign b_data_in_0_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in_0_NC; + assign c_data_in_0_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out_0_NC; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out_0_NC; + wire [`AWIDTH-1:0] a_addr_0; + wire [`AWIDTH-1:0] b_addr_0; + wire [`AWIDTH-1:0] c_addr_0; + wire c_data_0_available; + reg [3:0] validity_mask_a_0_rows; + reg [3:0] validity_mask_a_0_cols; + reg [3:0] validity_mask_b_0_rows; + reg [3:0] validity_mask_b_0_cols; + + + + reg pe_reset_1; + reg start_mat_mul_1; + wire done_mat_mul_1; + reg [`AWIDTH-1:0] address_mat_a_1; + reg [`AWIDTH-1:0] address_mat_b_1; + reg [`AWIDTH-1:0] address_mat_c_1; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a_1; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b_1; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c_1; + wire [3:0] flags_NC_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in_1_NC; + assign a_data_in_1_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in_1_NC; + assign b_data_in_1_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in_1_NC; + assign c_data_in_1_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out_1_NC; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out_1_NC; + wire [`AWIDTH-1:0] a_addr_1; + wire [`AWIDTH-1:0] b_addr_1; + wire [`AWIDTH-1:0] c_addr_1; + wire c_data_1_available; + reg [3:0] validity_mask_a_1_rows; + reg [3:0] validity_mask_a_1_cols; + reg [3:0] validity_mask_b_1_rows; + reg [3:0] validity_mask_b_1_cols; + + + + reg pe_reset_2; + reg start_mat_mul_2; + wire done_mat_mul_2; + reg [`AWIDTH-1:0] address_mat_a_2; + reg [`AWIDTH-1:0] address_mat_b_2; + reg [`AWIDTH-1:0] address_mat_c_2; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a_2; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b_2; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c_2; + wire [3:0] flags_NC_2; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_2; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_2; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_2; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in_2_NC; + assign a_data_in_2_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in_2_NC; + assign b_data_in_2_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in_2_NC; + assign c_data_in_2_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out_2_NC; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out_2_NC; + wire [`AWIDTH-1:0] a_addr_2; + wire [`AWIDTH-1:0] b_addr_2; + wire [`AWIDTH-1:0] c_addr_2; + wire c_data_2_available; + reg [3:0] validity_mask_a_2_rows; + reg [3:0] validity_mask_a_2_cols; + reg [3:0] validity_mask_b_2_rows; + reg [3:0] validity_mask_b_2_cols; + + + + reg pe_reset_3; + reg start_mat_mul_3; + wire done_mat_mul_3; + reg [`AWIDTH-1:0] address_mat_a_3; + reg [`AWIDTH-1:0] address_mat_b_3; + reg [`AWIDTH-1:0] address_mat_c_3; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a_3; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b_3; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c_3; + wire [3:0] flags_NC_3; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_3; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_3; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_3; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in_3_NC; + assign a_data_in_3_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in_3_NC; + assign b_data_in_3_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in_3_NC; + assign c_data_in_3_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out_3_NC; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out_3_NC; + wire [`AWIDTH-1:0] a_addr_3; + wire [`AWIDTH-1:0] b_addr_3; + wire [`AWIDTH-1:0] c_addr_3; + wire c_data_3_available; + reg [3:0] validity_mask_a_3_rows; + reg [3:0] validity_mask_a_3_cols; + reg [3:0] validity_mask_b_3_rows; + reg [3:0] validity_mask_b_3_cols; + + + + reg pe_reset_4; + reg start_mat_mul_4; + wire done_mat_mul_4; + reg [`AWIDTH-1:0] address_mat_a_4; + reg [`AWIDTH-1:0] address_mat_b_4; + reg [`AWIDTH-1:0] address_mat_c_4; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a_4; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b_4; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c_4; + wire [3:0] flags_NC_4; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_4; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_4; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_4; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in_4_NC; + assign a_data_in_4_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in_4_NC; + assign b_data_in_4_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in_4_NC; + assign c_data_in_4_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out_4_NC; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out_4_NC; + wire [`AWIDTH-1:0] a_addr_4; + wire [`AWIDTH-1:0] b_addr_4; + wire [`AWIDTH-1:0] c_addr_4; + wire c_data_4_available; + reg [3:0] validity_mask_a_4_rows; + reg [3:0] validity_mask_a_4_cols; + reg [3:0] validity_mask_b_4_rows; + reg [3:0] validity_mask_b_4_cols; + + + + reg pe_reset_5; + reg start_mat_mul_5; + wire done_mat_mul_5; + reg [`AWIDTH-1:0] address_mat_a_5; + reg [`AWIDTH-1:0] address_mat_b_5; + reg [`AWIDTH-1:0] address_mat_c_5; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a_5; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b_5; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c_5; + wire [3:0] flags_NC_5; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_5; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_5; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_5; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in_5_NC; + assign a_data_in_5_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in_5_NC; + assign b_data_in_5_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in_5_NC; + assign c_data_in_5_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out_5_NC; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out_5_NC; + wire [`AWIDTH-1:0] a_addr_5; + wire [`AWIDTH-1:0] b_addr_5; + wire [`AWIDTH-1:0] c_addr_5; + wire c_data_5_available; + reg [3:0] validity_mask_a_5_rows; + reg [3:0] validity_mask_a_5_cols; + reg [3:0] validity_mask_b_5_rows; + reg [3:0] validity_mask_b_5_cols; + + + + reg pe_reset_6; + reg start_mat_mul_6; + wire done_mat_mul_6; + reg [`AWIDTH-1:0] address_mat_a_6; + reg [`AWIDTH-1:0] address_mat_b_6; + reg [`AWIDTH-1:0] address_mat_c_6; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a_6; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b_6; + reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c_6; + wire [3:0] flags_NC_6; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_6; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_6; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_6; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in_6_NC; + assign a_data_in_6_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in_6_NC; + assign b_data_in_6_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in_6_NC; + assign c_data_in_6_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out_6_NC; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out_6_NC; + wire [`AWIDTH-1:0] a_addr_6; + wire [`AWIDTH-1:0] b_addr_6; + wire [`AWIDTH-1:0] c_addr_6; + wire c_data_6_available; + reg [3:0] validity_mask_a_6_rows; + reg [3:0] validity_mask_a_6_cols; + reg [3:0] validity_mask_b_6_rows; + reg [3:0] validity_mask_b_6_cols; + + + + reg [`AWIDTH-1:0] bram_addr_a_0_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_0_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_0_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_0_ext; + + wire [`AWIDTH-1:0] bram_addr_a_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_0; + wire [`MASK_WIDTH-1:0] bram_we_a_0; + wire bram_en_a_0; + + reg [`AWIDTH-1:0] bram_addr_b_0_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_0_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_0_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_0_ext; + + wire [`AWIDTH-1:0] bram_addr_b_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_0; + wire [`MASK_WIDTH-1:0] bram_we_b_0; + wire bram_en_b_0; + + + + reg [`AWIDTH-1:0] bram_addr_a_1_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_1_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_1_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_1_ext; + + wire [`AWIDTH-1:0] bram_addr_a_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_1; + wire [`MASK_WIDTH-1:0] bram_we_a_1; + wire bram_en_a_1; + + reg [`AWIDTH-1:0] bram_addr_b_1_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_1_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_1_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_1_ext; + + wire [`AWIDTH-1:0] bram_addr_b_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_1; + wire [`MASK_WIDTH-1:0] bram_we_b_1; + wire bram_en_b_1; + + + + reg [`AWIDTH-1:0] bram_addr_a_2_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_2_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_2_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_2_ext; + + wire [`AWIDTH-1:0] bram_addr_a_2; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_2; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_2; + wire [`MASK_WIDTH-1:0] bram_we_a_2; + wire bram_en_a_2; + + reg [`AWIDTH-1:0] bram_addr_b_2_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_2_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_2_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_2_ext; + + wire [`AWIDTH-1:0] bram_addr_b_2; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_2; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_2; + wire [`MASK_WIDTH-1:0] bram_we_b_2; + wire bram_en_b_2; + + + + reg [`AWIDTH-1:0] bram_addr_a_3_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_3_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_3_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_3_ext; + + wire [`AWIDTH-1:0] bram_addr_a_3; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_3; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_3; + wire [`MASK_WIDTH-1:0] bram_we_a_3; + wire bram_en_a_3; + + reg [`AWIDTH-1:0] bram_addr_b_3_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_3_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_3_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_3_ext; + + wire [`AWIDTH-1:0] bram_addr_b_3; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_3; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_3; + wire [`MASK_WIDTH-1:0] bram_we_b_3; + wire bram_en_b_3; + + + + reg [`AWIDTH-1:0] bram_addr_a_4_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_4_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_4_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_4_ext; + + wire [`AWIDTH-1:0] bram_addr_a_4; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_4; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_4; + wire [`MASK_WIDTH-1:0] bram_we_a_4; + wire bram_en_a_4; + + reg [`AWIDTH-1:0] bram_addr_b_4_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_4_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_4_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_4_ext; + + wire [`AWIDTH-1:0] bram_addr_b_4; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_4; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_4; + wire [`MASK_WIDTH-1:0] bram_we_b_4; + wire bram_en_b_4; + + + + reg [`AWIDTH-1:0] bram_addr_a_5_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_5_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_5_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_5_ext; + + wire [`AWIDTH-1:0] bram_addr_a_5; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_5; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_5; + wire [`MASK_WIDTH-1:0] bram_we_a_5; + wire bram_en_a_5; + + reg [`AWIDTH-1:0] bram_addr_b_5_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_5_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_5_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_5_ext; + + wire [`AWIDTH-1:0] bram_addr_b_5; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_5; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_5; + wire [`MASK_WIDTH-1:0] bram_we_b_5; + wire bram_en_b_5; + + + + reg [`AWIDTH-1:0] bram_addr_a_6_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_6_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_6_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_6_ext; + + wire [`AWIDTH-1:0] bram_addr_a_6; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_6; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_6; + wire [`MASK_WIDTH-1:0] bram_we_a_6; + wire bram_en_a_6; + + reg [`AWIDTH-1:0] bram_addr_b_6_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_6_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_6_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_6_ext; + + wire [`AWIDTH-1:0] bram_addr_b_6; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_6; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_6; + wire [`MASK_WIDTH-1:0] bram_we_b_6; + wire bram_en_b_6; + + + + always @ (posedge clk) begin + case (bram_select) + 0: begin + bram_addr_a_0_ext <= bram_addr_ext; + bram_wdata_a_0_ext <= bram_wdata_ext; + bram_we_a_0_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_a_0_ext; + end + + + 1: begin + bram_addr_b_0_ext <= bram_addr_ext; + bram_wdata_b_0_ext <= bram_wdata_ext; + bram_we_b_0_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_b_0_ext; + end + + + 2: begin + bram_addr_a_1_ext <= bram_addr_ext; + bram_wdata_a_1_ext <= bram_wdata_ext; + bram_we_a_1_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_a_1_ext; + end + + + 3: begin + bram_addr_b_1_ext <= bram_addr_ext; + bram_wdata_b_1_ext <= bram_wdata_ext; + bram_we_b_1_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_b_1_ext; + end + + + 4: begin + bram_addr_a_2_ext <= bram_addr_ext; + bram_wdata_a_2_ext <= bram_wdata_ext; + bram_we_a_2_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_a_2_ext; + end + + + 5: begin + bram_addr_b_2_ext <= bram_addr_ext; + bram_wdata_b_2_ext <= bram_wdata_ext; + bram_we_b_2_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_b_2_ext; + end + + + 6: begin + bram_addr_a_3_ext <= bram_addr_ext; + bram_wdata_a_3_ext <= bram_wdata_ext; + bram_we_a_3_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_a_3_ext; + end + + + 7: begin + bram_addr_b_3_ext <= bram_addr_ext; + bram_wdata_b_3_ext <= bram_wdata_ext; + bram_we_b_3_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_b_3_ext; + end + + + 8: begin + bram_addr_a_4_ext <= bram_addr_ext; + bram_wdata_a_4_ext <= bram_wdata_ext; + bram_we_a_4_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_a_4_ext; + end + + + 9: begin + bram_addr_b_4_ext <= bram_addr_ext; + bram_wdata_b_4_ext <= bram_wdata_ext; + bram_we_b_4_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_b_4_ext; + end + + + 10: begin + bram_addr_a_5_ext <= bram_addr_ext; + bram_wdata_a_5_ext <= bram_wdata_ext; + bram_we_a_5_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_a_5_ext; + end + + + 11: begin + bram_addr_b_5_ext <= bram_addr_ext; + bram_wdata_b_5_ext <= bram_wdata_ext; + bram_we_b_5_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_b_5_ext; + end + + + 12: begin + bram_addr_a_6_ext <= bram_addr_ext; + bram_wdata_a_6_ext <= bram_wdata_ext; + bram_we_a_6_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_a_6_ext; + end + + + 13: begin + bram_addr_b_6_ext <= bram_addr_ext; + bram_wdata_b_6_ext <= bram_wdata_ext; + bram_we_b_6_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_b_6_ext; + end + + + default: begin + bram_rdata_ext <= 0; + bram_addr_a_0_ext <= bram_addr_a_0_ext; + bram_wdata_a_0_ext <= bram_wdata_a_0_ext; + bram_we_a_0_ext <= bram_we_a_0_ext; + end + endcase + end + + + ram matrix_A_0( + .addr0(bram_addr_a_0), + .d0(bram_wdata_a_0), + .we0(bram_we_a_0), + .q0(a_data_0), + .addr1(bram_addr_a_0_ext), + .d1(bram_wdata_a_0_ext), + .we1(bram_we_a_0_ext), + .q1(bram_rdata_a_0_ext), + .clk(clk_mem)); + + ram matrix_B_0( + .addr0(b_addr_0), + .d0(bram_wdata_b_0), + .we0(bram_we_b_0), + .q0(b_data_0), + .addr1(bram_addr_b_0_ext), + .d1(bram_wdata_b_0_ext), + .we1(bram_we_b_0_ext), + .q1(bram_rdata_b_0_ext), + .clk(clk_mem)); + + + + ram matrix_A_1( + .addr0(bram_addr_a_1), + .d0(bram_wdata_a_1), + .we0(bram_we_a_1), + .q0(a_data_1), + .addr1(bram_addr_a_1_ext), + .d1(bram_wdata_a_1_ext), + .we1(bram_we_a_1_ext), + .q1(bram_rdata_a_1_ext), + .clk(clk_mem)); + + ram matrix_B_1( + .addr0(b_addr_1), + .d0(bram_wdata_b_1), + .we0(bram_we_b_1), + .q0(b_data_1), + .addr1(bram_addr_b_1_ext), + .d1(bram_wdata_b_1_ext), + .we1(bram_we_b_1_ext), + .q1(bram_rdata_b_1_ext), + .clk(clk_mem)); + + + + ram matrix_A_2( + .addr0(bram_addr_a_2), + .d0(bram_wdata_a_2), + .we0(bram_we_a_2), + .q0(a_data_2), + .addr1(bram_addr_a_2_ext), + .d1(bram_wdata_a_2_ext), + .we1(bram_we_a_2_ext), + .q1(bram_rdata_a_2_ext), + .clk(clk_mem)); + + ram matrix_B_2( + .addr0(b_addr_2), + .d0(bram_wdata_b_2), + .we0(bram_we_b_2), + .q0(b_data_2), + .addr1(bram_addr_b_2_ext), + .d1(bram_wdata_b_2_ext), + .we1(bram_we_b_2_ext), + .q1(bram_rdata_b_2_ext), + .clk(clk_mem)); + + + + ram matrix_A_3( + .addr0(bram_addr_a_3), + .d0(bram_wdata_a_3), + .we0(bram_we_a_3), + .q0(a_data_3), + .addr1(bram_addr_a_3_ext), + .d1(bram_wdata_a_3_ext), + .we1(bram_we_a_3_ext), + .q1(bram_rdata_a_3_ext), + .clk(clk_mem)); + + ram matrix_B_3( + .addr0(b_addr_3), + .d0(bram_wdata_b_3), + .we0(bram_we_b_3), + .q0(b_data_3), + .addr1(bram_addr_b_3_ext), + .d1(bram_wdata_b_3_ext), + .we1(bram_we_b_3_ext), + .q1(bram_rdata_b_3_ext), + .clk(clk_mem)); + + + + ram matrix_A_4( + .addr0(bram_addr_a_4), + .d0(bram_wdata_a_4), + .we0(bram_we_a_4), + .q0(a_data_4), + .addr1(bram_addr_a_4_ext), + .d1(bram_wdata_a_4_ext), + .we1(bram_we_a_4_ext), + .q1(bram_rdata_a_4_ext), + .clk(clk_mem)); + + ram matrix_B_4( + .addr0(b_addr_4), + .d0(bram_wdata_b_4), + .we0(bram_we_b_4), + .q0(b_data_4), + .addr1(bram_addr_b_4_ext), + .d1(bram_wdata_b_4_ext), + .we1(bram_we_b_4_ext), + .q1(bram_rdata_b_4_ext), + .clk(clk_mem)); + + + + ram matrix_A_5( + .addr0(bram_addr_a_5), + .d0(bram_wdata_a_5), + .we0(bram_we_a_5), + .q0(a_data_5), + .addr1(bram_addr_a_5_ext), + .d1(bram_wdata_a_5_ext), + .we1(bram_we_a_5_ext), + .q1(bram_rdata_a_5_ext), + .clk(clk_mem)); + + ram matrix_B_5( + .addr0(b_addr_5), + .d0(bram_wdata_b_5), + .we0(bram_we_b_5), + .q0(b_data_5), + .addr1(bram_addr_b_5_ext), + .d1(bram_wdata_b_5_ext), + .we1(bram_we_b_5_ext), + .q1(bram_rdata_b_5_ext), + .clk(clk_mem)); + + + + ram matrix_A_6( + .addr0(bram_addr_a_6), + .d0(bram_wdata_a_6), + .we0(bram_we_a_6), + .q0(a_data_6), + .addr1(bram_addr_a_6_ext), + .d1(bram_wdata_a_6_ext), + .we1(bram_we_a_6_ext), + .q1(bram_rdata_a_6_ext), + .clk(clk_mem)); + + ram matrix_B_6( + .addr0(b_addr_6), + .d0(bram_wdata_b_6), + .we0(bram_we_b_6), + .q0(b_data_6), + .addr1(bram_addr_b_6_ext), + .d1(bram_wdata_b_6_ext), + .we1(bram_we_b_6_ext), + .q1(bram_rdata_b_6_ext), + .clk(clk_mem)); + + + + + assign bram_wdata_a_0 = c_data_0; + assign bram_en_a_0 = 1'b1; + assign bram_we_a_0 = (c_data_0_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + assign bram_addr_a_0 = (c_data_0_available) ? c_addr_0 : a_addr_0; + + assign bram_wdata_b_0 = {`MAT_MUL_SIZE*`DWIDTH{1'b0}}; + assign bram_en_b_0 = 1'b1; + assign bram_we_b_0 = {`MASK_WIDTH{1'b0}}; + + + + assign bram_wdata_a_1 = c_data_1; + assign bram_en_a_1 = 1'b1; + assign bram_we_a_1 = (c_data_1_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + assign bram_addr_a_1 = (c_data_1_available) ? c_addr_1 : a_addr_1; + + assign bram_wdata_b_1 = {`MAT_MUL_SIZE*`DWIDTH{1'b0}}; + assign bram_en_b_1 = 1'b1; + assign bram_we_b_1 = {`MASK_WIDTH{1'b0}}; + + + + assign bram_wdata_a_2 = c_data_2; + assign bram_en_a_2 = 1'b1; + assign bram_we_a_2 = (c_data_2_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + assign bram_addr_a_2 = (c_data_2_available) ? c_addr_2 : a_addr_2; + + assign bram_wdata_b_2 = {`MAT_MUL_SIZE*`DWIDTH{1'b0}}; + assign bram_en_b_2 = 1'b1; + assign bram_we_b_2 = {`MASK_WIDTH{1'b0}}; + + + + assign bram_wdata_a_3 = c_data_3; + assign bram_en_a_3 = 1'b1; + assign bram_we_a_3 = (c_data_3_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + assign bram_addr_a_3 = (c_data_3_available) ? c_addr_3 : a_addr_3; + + assign bram_wdata_b_3 = {`MAT_MUL_SIZE*`DWIDTH{1'b0}}; + assign bram_en_b_3 = 1'b1; + assign bram_we_b_3 = {`MASK_WIDTH{1'b0}}; + + + + assign bram_wdata_a_4 = c_data_4; + assign bram_en_a_4 = 1'b1; + assign bram_we_a_4 = (c_data_4_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + assign bram_addr_a_4 = (c_data_4_available) ? c_addr_4 : a_addr_4; + + assign bram_wdata_b_4 = {`MAT_MUL_SIZE*`DWIDTH{1'b0}}; + assign bram_en_b_4 = 1'b1; + assign bram_we_b_4 = {`MASK_WIDTH{1'b0}}; + + + + assign bram_wdata_a_5 = c_data_5; + assign bram_en_a_5 = 1'b1; + assign bram_we_a_5 = (c_data_5_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + assign bram_addr_a_5 = (c_data_5_available) ? c_addr_5 : a_addr_5; + + assign bram_wdata_b_5 = {`MAT_MUL_SIZE*`DWIDTH{1'b0}}; + assign bram_en_b_5 = 1'b1; + assign bram_we_b_5 = {`MASK_WIDTH{1'b0}}; + + + + assign bram_wdata_a_6 = c_data_6; + assign bram_en_a_6 = 1'b1; + assign bram_we_a_6 = (c_data_6_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + assign bram_addr_a_6 = (c_data_6_available) ? c_addr_6 : a_addr_6; + + assign bram_wdata_b_6 = {`MAT_MUL_SIZE*`DWIDTH{1'b0}}; + assign bram_en_b_6 = 1'b1; + assign bram_we_b_6 = {`MASK_WIDTH{1'b0}}; + + +wire done_mat_mul; +assign done_mat_mul = +done_mat_mul_0 & +done_mat_mul_1 & +done_mat_mul_2 & +done_mat_mul_3 & +done_mat_mul_4 & +done_mat_mul_5 & +done_mat_mul_6; + +wire done_eltwise_add_phase_1; +wire done_eltwise_add_phase_2; +wire done_eltwise_add_phase_3; +assign done_eltwise_add_phase_1 = done_mat_mul_4 & done_mat_mul_5 & done_mat_mul_6; +assign done_eltwise_add_phase_2 = done_mat_mul_5 & done_mat_mul_6; +assign done_eltwise_add_phase_3 = done_mat_mul_6; + + + +reg [1:0] slice_0_op; + + +reg [1:0] slice_1_op; + + +reg [1:0] slice_2_op; + + +reg [1:0] slice_3_op; + + +reg [1:0] slice_4_op; + + +reg [1:0] slice_5_op; + + +reg [1:0] slice_6_op; + + +reg [3:0] count; +reg [4:0] state; +reg [4:0] vertical_count; + + always @( posedge clk) begin + if (resetn == 1'b0) begin + state <= 5'd0; + done <= 0; + + + slice_0_op <= 0; + start_mat_mul_0 <= 0; + address_mat_a_0 <= 0; + address_mat_b_0 <= 0; + address_mat_c_0 <= 0; + address_stride_a_0 <= 0; + address_stride_b_0 <= 0; + address_stride_c_0 <= 0; + validity_mask_a_0_rows <= 0; + validity_mask_a_0_cols <= 0; + validity_mask_b_0_rows <= 0; + validity_mask_b_0_cols <= 0; + + + slice_1_op <= 0; + start_mat_mul_1 <= 0; + address_mat_a_1 <= 0; + address_mat_b_1 <= 0; + address_mat_c_1 <= 0; + address_stride_a_1 <= 0; + address_stride_b_1 <= 0; + address_stride_c_1 <= 0; + validity_mask_a_1_rows <= 0; + validity_mask_a_1_cols <= 0; + validity_mask_b_1_rows <= 0; + validity_mask_b_1_cols <= 0; + + + slice_2_op <= 0; + start_mat_mul_2 <= 0; + address_mat_a_2 <= 0; + address_mat_b_2 <= 0; + address_mat_c_2 <= 0; + address_stride_a_2 <= 0; + address_stride_b_2 <= 0; + address_stride_c_2 <= 0; + validity_mask_a_2_rows <= 0; + validity_mask_a_2_cols <= 0; + validity_mask_b_2_rows <= 0; + validity_mask_b_2_cols <= 0; + + + slice_3_op <= 0; + start_mat_mul_3 <= 0; + address_mat_a_3 <= 0; + address_mat_b_3 <= 0; + address_mat_c_3 <= 0; + address_stride_a_3 <= 0; + address_stride_b_3 <= 0; + address_stride_c_3 <= 0; + validity_mask_a_3_rows <= 0; + validity_mask_a_3_cols <= 0; + validity_mask_b_3_rows <= 0; + validity_mask_b_3_cols <= 0; + + + slice_4_op <= 0; + start_mat_mul_4 <= 0; + address_mat_a_4 <= 0; + address_mat_b_4 <= 0; + address_mat_c_4 <= 0; + address_stride_a_4 <= 0; + address_stride_b_4 <= 0; + address_stride_c_4 <= 0; + validity_mask_a_4_rows <= 0; + validity_mask_a_4_cols <= 0; + validity_mask_b_4_rows <= 0; + validity_mask_b_4_cols <= 0; + + + slice_5_op <= 0; + start_mat_mul_5 <= 0; + address_mat_a_5 <= 0; + address_mat_b_5 <= 0; + address_mat_c_5 <= 0; + address_stride_a_5 <= 0; + address_stride_b_5 <= 0; + address_stride_c_5 <= 0; + validity_mask_a_5_rows <= 0; + validity_mask_a_5_cols <= 0; + validity_mask_b_5_rows <= 0; + validity_mask_b_5_cols <= 0; + + + slice_6_op <= 0; + start_mat_mul_6 <= 0; + address_mat_a_6 <= 0; + address_mat_b_6 <= 0; + address_mat_c_6 <= 0; + address_stride_a_6 <= 0; + address_stride_b_6 <= 0; + address_stride_c_6 <= 0; + validity_mask_a_6_rows <= 0; + validity_mask_a_6_cols <= 0; + validity_mask_b_6_rows <= 0; + validity_mask_b_6_cols <= 0; + + + count <= 0; + vertical_count <= 0; + end + else begin + case (state) + 5'd0: begin + +start_mat_mul_0 <= 1'b0; +start_mat_mul_1 <= 1'b0; +start_mat_mul_2 <= 1'b0; +start_mat_mul_3 <= 1'b0; +start_mat_mul_4 <= 1'b0; +start_mat_mul_5 <= 1'b0; +start_mat_mul_6 <= 1'b0; + + if (start== 1'b1) begin + count <= 4'd1; + vertical_count <= 5'd1; + state <= 5'd1; + done <= 0; + end + end + + + 5'd1: begin + + + slice_0_op <= 2'b00; + start_mat_mul_0 <= 1'b1; + address_mat_a_0 <= vertical_count + `ADDRESS_BASE_A +10'd0; //will change horizontally + address_mat_b_0 <= vertical_count + `ADDRESS_BASE_B +10'd0; //will change horizontally + address_mat_c_0 <= vertical_count + `ADDRESS_BASE_A +10'd192; //will stay constant horizontally + //if (count==4'd4) begin + // address_stride_a_0 <= 16'd8; + //end else begin + address_stride_a_0 <= 16'd1; + //end + address_stride_b_0 <= 16'd3; //constant horiz + address_stride_c_0 <= 16'd64; //constant horiz + validity_mask_a_0_rows <= 4'b1111; //constant + validity_mask_a_0_cols <= 4'b1111; //constant + validity_mask_b_0_rows <= 4'b1111; //constant + validity_mask_b_0_cols <= 4'b0111; //constant + + + slice_1_op <= 2'b00; + start_mat_mul_1 <= 1'b1; + address_mat_a_1 <= vertical_count + `ADDRESS_BASE_A +10'd11; //will change horizontally + address_mat_b_1 <= vertical_count + `ADDRESS_BASE_B +10'd12; //will change horizontally + address_mat_c_1 <= vertical_count + `ADDRESS_BASE_A +10'd192; //will stay constant horizontally + //if (count==4'd4) begin + // address_stride_a_1 <= 16'd8; + //end else begin + address_stride_a_1 <= 16'd1; + //end + address_stride_b_1 <= 16'd3; //constant horiz + address_stride_c_1 <= 16'd64; //constant horiz + validity_mask_a_1_rows <= 4'b1111; //constant + validity_mask_a_1_cols <= 4'b1111; //constant + validity_mask_b_1_rows <= 4'b1111; //constant + validity_mask_b_1_cols <= 4'b0111; //constant + + + slice_2_op <= 2'b00; + start_mat_mul_2 <= 1'b1; + address_mat_a_2 <= vertical_count + `ADDRESS_BASE_A +10'd22; //will change horizontally + address_mat_b_2 <= vertical_count + `ADDRESS_BASE_B +10'd24; //will change horizontally + address_mat_c_2 <= vertical_count + `ADDRESS_BASE_A +10'd192; //will stay constant horizontally + //if (count==4'd4) begin + // address_stride_a_2 <= 16'd8; + //end else begin + address_stride_a_2 <= 16'd1; + //end + address_stride_b_2 <= 16'd3; //constant horiz + address_stride_c_2 <= 16'd64; //constant horiz + validity_mask_a_2_rows <= 4'b1111; //constant + validity_mask_a_2_cols <= 4'b1111; //constant + validity_mask_b_2_rows <= 4'b1111; //constant + validity_mask_b_2_cols <= 4'b0111; //constant + + + slice_3_op <= 2'b00; + start_mat_mul_3 <= 1'b1; + address_mat_a_3 <= vertical_count + `ADDRESS_BASE_A +10'd33; //will change horizontally + address_mat_b_3 <= vertical_count + `ADDRESS_BASE_B +10'd36; //will change horizontally + address_mat_c_3 <= vertical_count + `ADDRESS_BASE_A +10'd192; //will stay constant horizontally + //if (count==4'd4) begin + // address_stride_a_3 <= 16'd8; + //end else begin + address_stride_a_3 <= 16'd1; + //end + address_stride_b_3 <= 16'd3; //constant horiz + address_stride_c_3 <= 16'd64; //constant horiz + validity_mask_a_3_rows <= 4'b1111; //constant + validity_mask_a_3_cols <= 4'b1111; //constant + validity_mask_b_3_rows <= 4'b1111; //constant + validity_mask_b_3_cols <= 4'b0111; //constant + + + slice_4_op <= 2'b00; + start_mat_mul_4 <= 1'b1; + address_mat_a_4 <= vertical_count + `ADDRESS_BASE_A +10'd44; //will change horizontally + address_mat_b_4 <= vertical_count + `ADDRESS_BASE_B +10'd48; //will change horizontally + address_mat_c_4 <= vertical_count + `ADDRESS_BASE_A +10'd192; //will stay constant horizontally + //if (count==4'd4) begin + // address_stride_a_4 <= 16'd8; + //end else begin + address_stride_a_4 <= 16'd1; + //end + address_stride_b_4 <= 16'd3; //constant horiz + address_stride_c_4 <= 16'd64; //constant horiz + validity_mask_a_4_rows <= 4'b1111; //constant + validity_mask_a_4_cols <= 4'b1111; //constant + validity_mask_b_4_rows <= 4'b1111; //constant + validity_mask_b_4_cols <= 4'b0111; //constant + + + slice_5_op <= 2'b00; + start_mat_mul_5 <= 1'b1; + address_mat_a_5 <= vertical_count + `ADDRESS_BASE_A +10'd55; //will change horizontally + address_mat_b_5 <= vertical_count + `ADDRESS_BASE_B +10'd60; //will change horizontally + address_mat_c_5 <= vertical_count + `ADDRESS_BASE_A +10'd192; //will stay constant horizontally + //if (count==4'd4) begin + // address_stride_a_5 <= 16'd8; + //end else begin + address_stride_a_5 <= 16'd1; + //end + address_stride_b_5 <= 16'd3; //constant horiz + address_stride_c_5 <= 16'd64; //constant horiz + validity_mask_a_5_rows <= 4'b1111; //constant + validity_mask_a_5_cols <= 4'b1111; //constant + validity_mask_b_5_rows <= 4'b1111; //constant + validity_mask_b_5_cols <= 4'b0111; //constant + + + slice_6_op <= 2'b00; + start_mat_mul_6 <= 1'b1; + address_mat_a_6 <= vertical_count + `ADDRESS_BASE_A +10'd66; //will change horizontally + address_mat_b_6 <= vertical_count + `ADDRESS_BASE_B +10'd72; //will change horizontally + address_mat_c_6 <= vertical_count + `ADDRESS_BASE_A +10'd192; //will stay constant horizontally + //if (count==4'd4) begin + // address_stride_a_6 <= 16'd8; + //end else begin + address_stride_a_6 <= 16'd1; + //end + address_stride_b_6 <= 16'd3; //constant horiz + address_stride_c_6 <= 16'd64; //constant horiz + validity_mask_a_6_rows <= 4'b1111; //constant + validity_mask_a_6_cols <= 4'b1111; //constant + validity_mask_b_6_rows <= 4'b1111; //constant + validity_mask_b_6_cols <= 4'b0111; //constant + + + count <= count + 1'b1; + + if (done_mat_mul == 1'b1) begin + state <= 5'd2; + + + end +end + + + 5'd2: begin + count <= 4'b0; + + + start_mat_mul_0 <= 1'b0; + + start_mat_mul_1 <= 1'b0; + + start_mat_mul_2 <= 1'b0; + + start_mat_mul_3 <= 1'b0; + + start_mat_mul_4 <= 1'b0; + + start_mat_mul_5 <= 1'b0; + + start_mat_mul_6 <= 1'b0; + + state <= 5'd3; + end + + + 5'd3: begin + + + slice_4_op <= 2'b10; + start_mat_mul_4 <= 1'b1; + address_mat_a_4 <= vertical_count + `ADDRESS_BASE_A + 10'd192; //will stay constant horizontally + address_mat_b_4 <= vertical_count + `ADDRESS_BASE_A + 10'd192; //will stay constant horizontally + address_mat_c_4 <= vertical_count + `ADDRESS_BASE_A + 10'd512; //will stay constant horizontally + address_stride_a_4 <= 16'd64; + address_stride_b_4 <= 16'd64; + address_stride_c_4 <= 16'd64; + validity_mask_a_4_rows <= 4'b1111; //constant + validity_mask_a_4_cols <= 4'b1111; //constant + validity_mask_b_4_rows <= 4'b1111; //constant + validity_mask_b_4_cols <= 4'b0111; //constant + + + slice_5_op <= 2'b10; + start_mat_mul_5 <= 1'b1; + address_mat_a_5 <= vertical_count + `ADDRESS_BASE_A + 10'd192; //will stay constant horizontally + address_mat_b_5 <= vertical_count + `ADDRESS_BASE_A + 10'd192; //will stay constant horizontally + address_mat_c_5 <= vertical_count + `ADDRESS_BASE_A + 10'd512; //will stay constant horizontally + address_stride_a_5 <= 16'd64; + address_stride_b_5 <= 16'd64; + address_stride_c_5 <= 16'd64; + validity_mask_a_5_rows <= 4'b1111; //constant + validity_mask_a_5_cols <= 4'b1111; //constant + validity_mask_b_5_rows <= 4'b1111; //constant + validity_mask_b_5_cols <= 4'b0111; //constant + + + slice_6_op <= 2'b10; + start_mat_mul_6 <= 1'b1; + address_mat_a_6 <= vertical_count + `ADDRESS_BASE_A + 10'd192; //will stay constant horizontally + address_mat_b_6 <= vertical_count + `ADDRESS_BASE_A + 10'd192; //will stay constant horizontally + address_mat_c_6 <= vertical_count + `ADDRESS_BASE_A + 10'd512; //will stay constant horizontally + address_stride_a_6 <= 16'd64; + address_stride_b_6 <= 16'd64; + address_stride_c_6 <= 16'd64; + validity_mask_a_6_rows <= 4'b1111; //constant + validity_mask_a_6_cols <= 4'b1111; //constant + validity_mask_b_6_rows <= 4'b1111; //constant + validity_mask_b_6_cols <= 4'b0111; //constant + + + if (done_eltwise_add_phase_1 == 1'b1) begin + state <= 5'd4; + end + + +end + 5'd4: begin + start_mat_mul_4 <= 1'b0; + start_mat_mul_5 <= 1'b0; + start_mat_mul_6 <= 1'b0; + state <= 5'd5; + + +end + 5'd5: begin + + + slice_5_op <= 2'b10; + start_mat_mul_5 <= 1'b1; + address_mat_a_5 <= vertical_count + `ADDRESS_BASE_A + 10'd512; //will stay constant horizontally + address_mat_b_5 <= vertical_count + `ADDRESS_BASE_A + 10'd512; //will stay constant horizontally + address_mat_c_5 <= vertical_count + `ADDRESS_BASE_A + 10'd768; //will stay constant horizontally + address_stride_a_5 <= 16'd64; + address_stride_b_5 <= 16'd64; + address_stride_c_5 <= 16'd64; + validity_mask_a_5_rows <= 4'b1111; //constant + validity_mask_a_5_cols <= 4'b1111; //constant + validity_mask_b_5_rows <= 4'b1111; //constant + validity_mask_b_5_cols <= 4'b0111; //constant + + + slice_6_op <= 2'b10; + start_mat_mul_6 <= 1'b1; + address_mat_a_6 <= vertical_count + `ADDRESS_BASE_A + 10'd512; //will stay constant horizontally + address_mat_b_6 <= vertical_count + `ADDRESS_BASE_A + 10'd512; //will stay constant horizontally + address_mat_c_6 <= vertical_count + `ADDRESS_BASE_A + 10'd768; //will stay constant horizontally + address_stride_a_6 <= 16'd64; + address_stride_b_6 <= 16'd64; + address_stride_c_6 <= 16'd64; + validity_mask_a_6_rows <= 4'b1111; //constant + validity_mask_a_6_cols <= 4'b1111; //constant + validity_mask_b_6_rows <= 4'b1111; //constant + validity_mask_b_6_cols <= 4'b0111; //constant + + + if (done_eltwise_add_phase_2 == 1'b1) begin + state <= 5'd6; + end + + +end + 5'd6: begin + state <= 5'd7; + start_mat_mul_5 <= 1'b0; + start_mat_mul_6 <= 1'b0; + + +end + 5'd7: begin + + + slice_6_op <= 2'b10; + start_mat_mul_6 <= 1'b1; + address_mat_a_6 <= vertical_count + `ADDRESS_BASE_A + 10'd768; //will stay constant horizontally + address_mat_b_6 <= vertical_count + `ADDRESS_BASE_A + 10'd768; //will stay constant horizontally + address_mat_c_6 <= vertical_count + `ADDRESS_BASE_A + 10'd900; //will stay constant horizontally + address_stride_a_6 <= 16'd64; + address_stride_b_6 <= 16'd64; + address_stride_c_6 <= 16'd64; + validity_mask_a_6_rows <= 4'b1111; //constant + validity_mask_a_6_cols <= 4'b1111; //constant + validity_mask_b_6_rows <= 4'b1111; //constant + validity_mask_b_6_cols <= 4'b0111; //constant + + + if (done_eltwise_add_phase_3 == 1'b1) begin + state <= 5'd8; + end +end + + + 5'd8: begin + state <= 5'd9; + start_mat_mul_6 <= 1'b0; +end + + + 5'd9: begin + if (vertical_count == 5'd16) begin + done <= 1'b1; + state <= 5'd0; + end + else begin + vertical_count <= vertical_count + 1'b1; + state <= 5'd1; + end + end + +endcase +end +end + + + matmul_4x4_systolic u_matmul_4x4_systolic_0( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul_0), + .done_mat_mul(done_mat_mul_0), + .address_mat_a(address_mat_a_0), + .address_mat_b(address_mat_b_0), + .address_mat_c(address_mat_c_0), + .address_stride_a(address_stride_a_0), + .address_stride_b(address_stride_b_0), + .address_stride_c(address_stride_c_0), + .a_data(a_data_0), + .b_data(b_data_0), + .a_data_in(a_data_in_0_NC), + .b_data_in(b_data_in_0_NC), + .c_data_in(c_data_in_0_NC), + .c_data_out(c_data_0), + .a_data_out(a_data_out_0_NC), + .b_data_out(b_data_out_0_NC), + .a_addr(a_addr_0), + .b_addr(b_addr_0), + .c_addr(c_addr_0), + .c_data_available(c_data_0_available), + .flags(flags_NC_0), + .validity_mask_a_rows(validity_mask_a_0_rows), + .validity_mask_a_cols(validity_mask_a_0_cols), + .validity_mask_b_rows(validity_mask_b_0_rows), + .validity_mask_b_cols(validity_mask_b_0_cols), + .slice_mode(1'b0), //0 is SLICE_MODE_MATMUL + .slice_dtype(1'b0), + .op(slice_0_op), + .preload(1'b0), + .final_mat_mul_size(8'd4), + .a_loc(8'd0), + .b_loc(8'd0) + ); + + + + matmul_4x4_systolic u_matmul_4x4_systolic_1( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul_1), + .done_mat_mul(done_mat_mul_1), + .address_mat_a(address_mat_a_1), + .address_mat_b(address_mat_b_1), + .address_mat_c(address_mat_c_1), + .address_stride_a(address_stride_a_1), + .address_stride_b(address_stride_b_1), + .address_stride_c(address_stride_c_1), + .a_data(a_data_1), + .b_data(b_data_1), + .a_data_in(a_data_in_1_NC), + .b_data_in(b_data_in_1_NC), + .c_data_in(c_data_in_1_NC), + .c_data_out(c_data_1), + .a_data_out(a_data_out_1_NC), + .b_data_out(b_data_out_1_NC), + .a_addr(a_addr_1), + .b_addr(b_addr_1), + .c_addr(c_addr_1), + .c_data_available(c_data_1_available), + .flags(flags_NC_1), + .validity_mask_a_rows(validity_mask_a_1_rows), + .validity_mask_a_cols(validity_mask_a_1_cols), + .validity_mask_b_rows(validity_mask_b_1_rows), + .validity_mask_b_cols(validity_mask_b_1_cols), + .slice_mode(1'b0), //0 is SLICE_MODE_MATMUL + .slice_dtype(1'b0), + .op(slice_1_op), + .preload(1'b0), + .final_mat_mul_size(8'd4), + .a_loc(8'd0), + .b_loc(8'd0) + ); + + + + matmul_4x4_systolic u_matmul_4x4_systolic_2( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul_2), + .done_mat_mul(done_mat_mul_2), + .address_mat_a(address_mat_a_2), + .address_mat_b(address_mat_b_2), + .address_mat_c(address_mat_c_2), + .address_stride_a(address_stride_a_2), + .address_stride_b(address_stride_b_2), + .address_stride_c(address_stride_c_2), + .a_data(a_data_2), + .b_data(b_data_2), + .a_data_in(a_data_in_2_NC), + .b_data_in(b_data_in_2_NC), + .c_data_in(c_data_in_2_NC), + .c_data_out(c_data_2), + .a_data_out(a_data_out_2_NC), + .b_data_out(b_data_out_2_NC), + .a_addr(a_addr_2), + .b_addr(b_addr_2), + .c_addr(c_addr_2), + .c_data_available(c_data_2_available), + .flags(flags_NC_2), + .validity_mask_a_rows(validity_mask_a_2_rows), + .validity_mask_a_cols(validity_mask_a_2_cols), + .validity_mask_b_rows(validity_mask_b_2_rows), + .validity_mask_b_cols(validity_mask_b_2_cols), + .slice_mode(1'b0), //0 is SLICE_MODE_MATMUL + .slice_dtype(1'b0), + .op(slice_2_op), + .preload(1'b0), + .final_mat_mul_size(8'd4), + .a_loc(8'd0), + .b_loc(8'd0) + ); + + + + matmul_4x4_systolic u_matmul_4x4_systolic_3( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul_3), + .done_mat_mul(done_mat_mul_3), + .address_mat_a(address_mat_a_3), + .address_mat_b(address_mat_b_3), + .address_mat_c(address_mat_c_3), + .address_stride_a(address_stride_a_3), + .address_stride_b(address_stride_b_3), + .address_stride_c(address_stride_c_3), + .a_data(a_data_3), + .b_data(b_data_3), + .a_data_in(a_data_in_3_NC), + .b_data_in(b_data_in_3_NC), + .c_data_in(c_data_in_3_NC), + .c_data_out(c_data_3), + .a_data_out(a_data_out_3_NC), + .b_data_out(b_data_out_3_NC), + .a_addr(a_addr_3), + .b_addr(b_addr_3), + .c_addr(c_addr_3), + .c_data_available(c_data_3_available), + .flags(flags_NC_3), + .validity_mask_a_rows(validity_mask_a_3_rows), + .validity_mask_a_cols(validity_mask_a_3_cols), + .validity_mask_b_rows(validity_mask_b_3_rows), + .validity_mask_b_cols(validity_mask_b_3_cols), + .slice_mode(1'b0), //0 is SLICE_MODE_MATMUL + .slice_dtype(1'b0), + .op(slice_3_op), + .preload(1'b0), + .final_mat_mul_size(8'd4), + .a_loc(8'd0), + .b_loc(8'd0) + ); + + + + matmul_4x4_systolic u_matmul_4x4_systolic_4( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul_4), + .done_mat_mul(done_mat_mul_4), + .address_mat_a(address_mat_a_4), + .address_mat_b(address_mat_b_4), + .address_mat_c(address_mat_c_4), + .address_stride_a(address_stride_a_4), + .address_stride_b(address_stride_b_4), + .address_stride_c(address_stride_c_4), + .a_data(a_data_4), + .b_data(b_data_4), + .a_data_in(a_data_in_4_NC), + .b_data_in(b_data_in_4_NC), + .c_data_in(c_data_in_4_NC), + .c_data_out(c_data_4), + .a_data_out(a_data_out_4_NC), + .b_data_out(b_data_out_4_NC), + .a_addr(a_addr_4), + .b_addr(b_addr_4), + .c_addr(c_addr_4), + .c_data_available(c_data_4_available), + .flags(flags_NC_4), + .validity_mask_a_rows(validity_mask_a_4_rows), + .validity_mask_a_cols(validity_mask_a_4_cols), + .validity_mask_b_rows(validity_mask_b_4_rows), + .validity_mask_b_cols(validity_mask_b_4_cols), + .slice_mode(1'b0), //0 is SLICE_MODE_MATMUL + .slice_dtype(1'b0), + .op(slice_4_op), + .preload(1'b0), + .final_mat_mul_size(8'd4), + .a_loc(8'd0), + .b_loc(8'd0) + ); + + + + matmul_4x4_systolic u_matmul_4x4_systolic_5( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul_5), + .done_mat_mul(done_mat_mul_5), + .address_mat_a(address_mat_a_5), + .address_mat_b(address_mat_b_5), + .address_mat_c(address_mat_c_5), + .address_stride_a(address_stride_a_5), + .address_stride_b(address_stride_b_5), + .address_stride_c(address_stride_c_5), + .a_data(a_data_5), + .b_data(b_data_5), + .a_data_in(a_data_in_5_NC), + .b_data_in(b_data_in_5_NC), + .c_data_in(c_data_in_5_NC), + .c_data_out(c_data_5), + .a_data_out(a_data_out_5_NC), + .b_data_out(b_data_out_5_NC), + .a_addr(a_addr_5), + .b_addr(b_addr_5), + .c_addr(c_addr_5), + .c_data_available(c_data_5_available), + .flags(flags_NC_5), + .validity_mask_a_rows(validity_mask_a_5_rows), + .validity_mask_a_cols(validity_mask_a_5_cols), + .validity_mask_b_rows(validity_mask_b_5_rows), + .validity_mask_b_cols(validity_mask_b_5_cols), + .slice_mode(1'b0), //0 is SLICE_MODE_MATMUL + .slice_dtype(1'b0), + .op(slice_5_op), + .preload(1'b0), + .final_mat_mul_size(8'd4), + .a_loc(8'd0), + .b_loc(8'd0) + ); + + + + matmul_4x4_systolic u_matmul_4x4_systolic_6( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul_6), + .done_mat_mul(done_mat_mul_6), + .address_mat_a(address_mat_a_6), + .address_mat_b(address_mat_b_6), + .address_mat_c(address_mat_c_6), + .address_stride_a(address_stride_a_6), + .address_stride_b(address_stride_b_6), + .address_stride_c(address_stride_c_6), + .a_data(a_data_6), + .b_data(b_data_6), + .a_data_in(a_data_in_6_NC), + .b_data_in(b_data_in_6_NC), + .c_data_in(c_data_in_6_NC), + .c_data_out(c_data_6), + .a_data_out(a_data_out_6_NC), + .b_data_out(b_data_out_6_NC), + .a_addr(a_addr_6), + .b_addr(b_addr_6), + .c_addr(c_addr_6), + .c_data_available(c_data_6_available), + .flags(flags_NC_6), + .validity_mask_a_rows(validity_mask_a_6_rows), + .validity_mask_a_cols(validity_mask_a_6_cols), + .validity_mask_b_rows(validity_mask_b_6_rows), + .validity_mask_b_cols(validity_mask_b_6_cols), + .slice_mode(1'b0), //0 is SLICE_MODE_MATMUL + .slice_dtype(1'b0), + .op(slice_6_op), + .preload(1'b0), + .final_mat_mul_size(8'd4), + .a_loc(8'd0), + .b_loc(8'd0) + ); + + + + +endmodule + + +////////////////////////////////// +//Dual port RAM +////////////////////////////////// +module ram ( + addr0, + d0, + we0, + q0, + addr1, + d1, + we1, + q1, + clk); + +input [`AWIDTH-1:0] addr0; +input [`AWIDTH-1:0] addr1; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] d0; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] d1; +input [`MAT_MUL_SIZE-1:0] we0; +input [`MAT_MUL_SIZE-1:0] we1; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] q0; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] q1; +input clk; + +genvar i; + +generate +`ifdef QUARTUS + for (i=0;i<`MAT_MUL_SIZE;i=i+1) begin: gen_dpram +`else + for (i=0;i<`MAT_MUL_SIZE;i=i+1) begin +`endif + dpram_original #(.AWIDTH(`AWIDTH),.DWIDTH(`DWIDTH),.NUM_WORDS(1<<`AWIDTH)) dp1 (.clk(clk),.address_a(addr0),.address_b(addr1),.wren_a(we0[i]),.wren_b(we1[i]),.data_a(d0[i*`DWIDTH +: `DWIDTH]),.data_b(d1[i*`DWIDTH +: `DWIDTH]),.out_a(q0[i*`DWIDTH +: `DWIDTH]),.out_b(q1[i*`DWIDTH +: `DWIDTH])); + end +endgenerate +endmodule + +module dpram_original ( + clk, + address_a, + address_b, + wren_a, + wren_b, + data_a, + data_b, + out_a, + out_b +); +parameter AWIDTH=10; +parameter NUM_WORDS=1024; +parameter DWIDTH=32; +input clk; +input [(AWIDTH-1):0] address_a; +input [(AWIDTH-1):0] address_b; +input wren_a; +input wren_b; +input [(DWIDTH-1):0] data_a; +input [(DWIDTH-1):0] data_b; +output reg [(DWIDTH-1):0] out_a; +output reg [(DWIDTH-1):0] out_b; + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram[NUM_WORDS-1:0]; +always @ (posedge clk) begin + if (wren_a) begin + ram[address_a] <= data_a; + end + else begin + out_a <= ram[address_a]; + end +end + +always @ (posedge clk) begin + if (wren_b) begin + ram[address_b] <= data_b; + end + else begin + out_b <= ram[address_b]; + end +end + +`else + +defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; +defparam u_dual_port_ram.DATA_WIDTH = DWIDTH; + +dual_port_ram u_dual_port_ram( +.addr1(address_a), +.we1(wren_a), +.data1(data_a), +.out1(out_a), +.addr2(address_b), +.we2(wren_b), +.data2(data_b), +.out2(out_b), +.clk(clk) +); + +`endif +endmodule + + +module matmul_4x4_systolic( + clk, + reset, + pe_reset, + start_mat_mul, + done_mat_mul, + address_mat_a, + address_mat_b, + address_mat_c, + address_stride_a, + address_stride_b, + address_stride_c, + a_data, + b_data, + a_data_in, //Data values coming in from previous matmul - systolic connections + b_data_in, + c_data_in, //Data values coming in from previous matmul - systolic shifting + c_data_out, //Data values going out to next matmul - systolic shifting + a_data_out, + b_data_out, + a_addr, + b_addr, + c_addr, + c_data_available, + flags, + validity_mask_a_rows, + validity_mask_a_cols, + validity_mask_b_rows, + validity_mask_b_cols, + slice_mode, + slice_dtype, + op, + preload, + final_mat_mul_size, + a_loc, + b_loc +); + + input clk; + input reset; + input pe_reset; + input start_mat_mul; + output done_mat_mul; + input [`AWIDTH-1:0] address_mat_a; + input [`AWIDTH-1:0] address_mat_b; + input [`AWIDTH-1:0] address_mat_c; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + output [`AWIDTH-1:0] a_addr; + output [`AWIDTH-1:0] b_addr; + output [`AWIDTH-1:0] c_addr; + output c_data_available; + output [3:0] flags; + input [`MASK_WIDTH-1:0] validity_mask_a_rows; + input [`MASK_WIDTH-1:0] validity_mask_a_cols; + input [`MASK_WIDTH-1:0] validity_mask_b_rows; + input [`MASK_WIDTH-1:0] validity_mask_b_cols; +//7:0 is okay here. We aren't going to make a matmul larger than 128x128 +//In fact, these will get optimized out by the synthesis tool, because +//we hardcode them at the instantiation level. + input [7:0] final_mat_mul_size; + input [7:0] a_loc; + input [7:0] b_loc; + input slice_dtype; + input slice_mode; + input [1:0] op; + input preload; + + + wire slice_dtype_NC; + wire slice_mode_NC; + wire preload_NC; + + assign slice_dtype_NC = slice_dtype; + assign slice_mode_NC = slice_mode; + assign preload_NC = preload; + +//op[1] op[0] +// 0 0 -> mat mul +// 0 1 -> elt mul +// 1 0 -> elt add +// 1 1 -> elt sub +wire eltwise_mode; +wire eltwise_mul; +wire eltwise_add; +wire eltwise_sub; +assign eltwise_mode = ( op[1] | op[0]); +assign eltwise_mul = (~op[1] & op[0]); +assign eltwise_add = ( op[1] & ~op[0]); +assign eltwise_sub = ( op[1] & op[0]); + +////////////////////////////////////////////////////////////////////////// +// Logic for clock counting and when to assert done +////////////////////////////////////////////////////////////////////////// + +reg done_mat_mul; +//This is 7 bits because the expectation is that clock count will be pretty +//small. For large matmuls, this will need to increased to have more bits. +//In general, a systolic multiplier takes 4*N-2+P cycles, where N is the size +//of the matmul and P is the number of pipleine stages in the MAC block. +reg [7:0] clk_cnt; + +//Finding out number of cycles to assert matmul done. +//When we have to save the outputs to accumulators, then we don't need to +//shift out data. So, we can assert done_mat_mul early. +//In the normal case, we have to include the time to shift out the results. +//Note: the count expression used to contain "4*final_mat_mul_size", but +//to avoid multiplication, we now use "final_mat_mul_size<<2" +wire [7:0] clk_cnt_for_done; +assign clk_cnt_for_done = + (eltwise_mode) ? ((final_mat_mul_size<<1) + 1'b1): + //hardcoding the define to avoid odin failure + //((final_mat_mul_size<<2) - 2'd2 + 8'd`NUM_CYCLES_IN_MAC) ; + ((final_mat_mul_size<<2) - 2'd2 + 8'd3) ; + +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + clk_cnt <= 0; + done_mat_mul <= 0; + end + else if (clk_cnt == clk_cnt_for_done) begin + done_mat_mul <= 1; + clk_cnt <= clk_cnt + 1'b1; + end + else if (done_mat_mul == 0) begin + clk_cnt <= clk_cnt + 1'b1; + end + else begin + done_mat_mul <= 0; + clk_cnt <= clk_cnt + 1'b1; + end +end + + +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] a1_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_1; +wire [`DWIDTH-1:0] a3_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_3; +wire [`DWIDTH-1:0] b1_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_1; +wire [`DWIDTH-1:0] b3_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_3; + +////////////////////////////////////////////////////////////////////////// +// Instantiation of systolic data setup +////////////////////////////////////////////////////////////////////////// +systolic_data_setup u_systolic_data_setup( +.clk(clk), +.reset(reset), +.start_mat_mul(start_mat_mul), +.eltwise_mode(eltwise_mode), +.a_addr(a_addr), +.b_addr(b_addr), +.address_mat_a(address_mat_a), +.address_mat_b(address_mat_b), +.address_stride_a(address_stride_a), +.address_stride_b(address_stride_b), +.a_data(a_data), +.b_data(b_data), +.clk_cnt(clk_cnt), +.a0_data(a0_data), +.a1_data_delayed_1(a1_data_delayed_1), +.a2_data_delayed_2(a2_data_delayed_2), +.a3_data_delayed_3(a3_data_delayed_3), +.b0_data(b0_data), +.b1_data_delayed_1(b1_data_delayed_1), +.b2_data_delayed_2(b2_data_delayed_2), +.b3_data_delayed_3(b3_data_delayed_3), +.validity_mask_a_rows(validity_mask_a_rows), +.validity_mask_a_cols(validity_mask_a_cols), +.validity_mask_b_rows(validity_mask_b_rows), +.validity_mask_b_cols(validity_mask_b_cols), +.final_mat_mul_size(final_mat_mul_size), +.a_loc(a_loc), +.b_loc(b_loc) +); + + +////////////////////////////////////////////////////////////////////////// +// Logic to mux data_in coming from neighboring matmuls +////////////////////////////////////////////////////////////////////////// +wire [`DWIDTH-1:0] a0; +wire [`DWIDTH-1:0] a1; +wire [`DWIDTH-1:0] a2; +wire [`DWIDTH-1:0] a3; +wire [`DWIDTH-1:0] b0; +wire [`DWIDTH-1:0] b1; +wire [`DWIDTH-1:0] b2; +wire [`DWIDTH-1:0] b3; + +wire [`DWIDTH-1:0] a0_data_in; +wire [`DWIDTH-1:0] a1_data_in; +wire [`DWIDTH-1:0] a2_data_in; +wire [`DWIDTH-1:0] a3_data_in; +assign a0_data_in = a_data_in[`DWIDTH-1:0]; +assign a1_data_in = a_data_in[2*`DWIDTH-1:`DWIDTH]; +assign a2_data_in = a_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign a3_data_in = a_data_in[4*`DWIDTH-1:3*`DWIDTH]; + +wire [`DWIDTH-1:0] b0_data_in; +wire [`DWIDTH-1:0] b1_data_in; +wire [`DWIDTH-1:0] b2_data_in; +wire [`DWIDTH-1:0] b3_data_in; +assign b0_data_in = b_data_in[`DWIDTH-1:0]; +assign b1_data_in = b_data_in[2*`DWIDTH-1:`DWIDTH]; +assign b2_data_in = b_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign b3_data_in = b_data_in[4*`DWIDTH-1:3*`DWIDTH]; + +//If b_loc is 0, that means this matmul block is on the top-row of the +//final large matmul. In that case, b will take inputs from mem. +//If b_loc != 0, that means this matmul block is not on the top-row of the +//final large matmul. In that case, b will take inputs from the matmul on top +//of this one. +assign a0 = (b_loc==0) ? a0_data : a0_data_in; +assign a1 = (b_loc==0) ? a1_data_delayed_1 : a1_data_in; +assign a2 = (b_loc==0) ? a2_data_delayed_2 : a2_data_in; +assign a3 = (b_loc==0) ? a3_data_delayed_3 : a3_data_in; + +//If a_loc is 0, that means this matmul block is on the left-col of the +//final large matmul. In that case, a will take inputs from mem. +//If a_loc != 0, that means this matmul block is not on the left-col of the +//final large matmul. In that case, a will take inputs from the matmul on left +//of this one. +assign b0 = (a_loc==0) ? b0_data : b0_data_in; +assign b1 = (a_loc==0) ? b1_data_delayed_1 : b1_data_in; +assign b2 = (a_loc==0) ? b2_data_delayed_2 : b2_data_in; +assign b3 = (a_loc==0) ? b3_data_delayed_3 : b3_data_in; + + +wire [`DWIDTH-1:0] matrixC00; +wire [`DWIDTH-1:0] matrixC01; +wire [`DWIDTH-1:0] matrixC02; +wire [`DWIDTH-1:0] matrixC03; +wire [`DWIDTH-1:0] matrixC10; +wire [`DWIDTH-1:0] matrixC11; +wire [`DWIDTH-1:0] matrixC12; +wire [`DWIDTH-1:0] matrixC13; +wire [`DWIDTH-1:0] matrixC20; +wire [`DWIDTH-1:0] matrixC21; +wire [`DWIDTH-1:0] matrixC22; +wire [`DWIDTH-1:0] matrixC23; +wire [`DWIDTH-1:0] matrixC30; +wire [`DWIDTH-1:0] matrixC31; +wire [`DWIDTH-1:0] matrixC32; +wire [`DWIDTH-1:0] matrixC33; + + +////////////////////////////////////////////////////////////////////////// +// Instantiation of the output logic +////////////////////////////////////////////////////////////////////////// +output_logic u_output_logic( +.clk(clk), +.reset(reset), +.start_mat_mul(start_mat_mul), +.done_mat_mul(done_mat_mul), +.eltwise_mode(eltwise_mode), +.address_mat_c(address_mat_c), +.address_stride_c(address_stride_c), +.c_data_out(c_data_out), +.c_data_in(c_data_in), +.c_addr(c_addr), +.c_data_available(c_data_available), +.clk_cnt(clk_cnt), +.row_latch_en(row_latch_en), +.final_mat_mul_size(final_mat_mul_size), +.matrixC00(matrixC00), +.matrixC01(matrixC01), +.matrixC02(matrixC02), +.matrixC03(matrixC03), +.matrixC10(matrixC10), +.matrixC11(matrixC11), +.matrixC12(matrixC12), +.matrixC13(matrixC13), +.matrixC20(matrixC20), +.matrixC21(matrixC21), +.matrixC22(matrixC22), +.matrixC23(matrixC23), +.matrixC30(matrixC30), +.matrixC31(matrixC31), +.matrixC32(matrixC32), +.matrixC33(matrixC33) +); + +wire ready_for_eltwise_op; +assign ready_for_eltwise_op = (clk_cnt > final_mat_mul_size); + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +systolic_pe_matrix u_systolic_pe_matrix( +.reset(reset), +.clk(clk), +.pe_reset(pe_reset), +.start_mat_mul(start_mat_mul), +.ready_for_eltwise_op(ready_for_eltwise_op), +.op(op), +.a0(a0), +.a1(a1), +.a2(a2), +.a3(a3), +.b0(b0), +.b1(b1), +.b2(b2), +.b3(b3), +.matrixC00(matrixC00), +.matrixC01(matrixC01), +.matrixC02(matrixC02), +.matrixC03(matrixC03), +.matrixC10(matrixC10), +.matrixC11(matrixC11), +.matrixC12(matrixC12), +.matrixC13(matrixC13), +.matrixC20(matrixC20), +.matrixC21(matrixC21), +.matrixC22(matrixC22), +.matrixC23(matrixC23), +.matrixC30(matrixC30), +.matrixC31(matrixC31), +.matrixC32(matrixC32), +.matrixC33(matrixC33), +.a_data_out(a_data_out), +.b_data_out(b_data_out), +.flags(flags) +); + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Output logic +////////////////////////////////////////////////////////////////////////// +module output_logic( +clk, +reset, +start_mat_mul, +done_mat_mul, +eltwise_mode, +address_mat_c, +address_stride_c, +c_data_in, +c_data_out, //Data values going out to next matmul - systolic shifting +c_addr, +c_data_available, +clk_cnt, +row_latch_en, +final_mat_mul_size, +matrixC00, +matrixC01, +matrixC02, +matrixC03, +matrixC10, +matrixC11, +matrixC12, +matrixC13, +matrixC20, +matrixC21, +matrixC22, +matrixC23, +matrixC30, +matrixC31, +matrixC32, +matrixC33 +); + +input clk; +input reset; +input start_mat_mul; +input done_mat_mul; +input eltwise_mode; +input [`AWIDTH-1:0] address_mat_c; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; +output [`AWIDTH-1:0] c_addr; +output c_data_available; +input [7:0] clk_cnt; +output row_latch_en; +input [7:0] final_mat_mul_size; +input [`DWIDTH-1:0] matrixC00; +input [`DWIDTH-1:0] matrixC01; +input [`DWIDTH-1:0] matrixC02; +input [`DWIDTH-1:0] matrixC03; +input [`DWIDTH-1:0] matrixC10; +input [`DWIDTH-1:0] matrixC11; +input [`DWIDTH-1:0] matrixC12; +input [`DWIDTH-1:0] matrixC13; +input [`DWIDTH-1:0] matrixC20; +input [`DWIDTH-1:0] matrixC21; +input [`DWIDTH-1:0] matrixC22; +input [`DWIDTH-1:0] matrixC23; +input [`DWIDTH-1:0] matrixC30; +input [`DWIDTH-1:0] matrixC31; +input [`DWIDTH-1:0] matrixC32; +input [`DWIDTH-1:0] matrixC33; + +wire row_latch_en; + +////////////////////////////////////////////////////////////////////////// +// Logic to capture matrix C data from the PEs and shift it out +////////////////////////////////////////////////////////////////////////// + +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + (a_loc+b_loc) * `BB_MAT_MUL_SIZE + 10 + `NUM_CYCLES_IN_MAC - 1)); +//Writing the line above to avoid multiplication: +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + ((a_loc+b_loc) << `LOG2_MAT_MUL_SIZE) + 10 + `NUM_CYCLES_IN_MAC - 1)); +//Fixing bug. The line above is inaccurate. Using the line below. +//TODO: This line needs to be fixed to include a_loc and b_loc ie. when final_mat_mul_size is different from `MAT_MUL_SIZE +assign row_latch_en = + //((clk_cnt == ((`MAT_MUL_SIZE<<2) - `MAT_MUL_SIZE -2 +`NUM_CYCLES_IN_MAC))); + (eltwise_mode) ? ((clk_cnt == (final_mat_mul_size + 1 ))) : + ((clk_cnt == ((final_mat_mul_size<<2) - final_mat_mul_size -1 +`NUM_CYCLES_IN_MAC))); + +reg c_data_available; +reg [`AWIDTH-1:0] c_addr; +reg start_capturing_c_data; +reg [31:0] counter; +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out_1; +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out_2; +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out_3; + +wire [`MAT_MUL_SIZE*`DWIDTH-1:0] col0; +wire [`MAT_MUL_SIZE*`DWIDTH-1:0] col1; +wire [`MAT_MUL_SIZE*`DWIDTH-1:0] col2; +wire [`MAT_MUL_SIZE*`DWIDTH-1:0] col3; +assign col0 = {matrixC30, matrixC20, matrixC10, matrixC00}; +assign col1 = {matrixC31, matrixC21, matrixC11, matrixC01}; +assign col2 = {matrixC32, matrixC22, matrixC12, matrixC02}; +assign col3 = {matrixC33, matrixC23, matrixC13, matrixC03}; + +//If save_output_to_accum is asserted, that means we are not intending to shift +//out the outputs, because the outputs are still partial sums. +wire condition_to_start_shifting_output; +assign condition_to_start_shifting_output = + row_latch_en ; + +//For larger matmuls, this logic will have more entries in the case statement +always @(posedge clk) begin + if (reset | ~start_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c+address_stride_c[`AWIDTH-1:0]; + c_data_out <= 0; + counter <= 0; + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + end + else if (condition_to_start_shifting_output) begin + start_capturing_c_data <= 1'b1; + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c[`AWIDTH-1:0]; + c_data_out <= col0; + c_data_out_1 <= col1; + c_data_out_2 <= col2; + c_data_out_3 <= col3; + counter <= counter + 1; + end + else if (done_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c+address_stride_c[`AWIDTH-1:0]; + c_data_out <= 0; + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + end + else if (counter >= `MAT_MUL_SIZE) begin + c_addr <= c_addr - address_stride_c[`AWIDTH-1:0]; + c_data_out <= c_data_out_1; + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_in; + end + else if (start_capturing_c_data) begin + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c[`AWIDTH-1:0]; + counter <= counter + 1; + c_data_out <= c_data_out_1; + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_in; + end +end + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Systolic data setup +////////////////////////////////////////////////////////////////////////// +module systolic_data_setup( +clk, +reset, +start_mat_mul, +eltwise_mode, +a_addr, +b_addr, +address_mat_a, +address_mat_b, +address_stride_a, +address_stride_b, +a_data, +b_data, +clk_cnt, +a0_data, +a1_data_delayed_1, +a2_data_delayed_2, +a3_data_delayed_3, +b0_data, +b1_data_delayed_1, +b2_data_delayed_2, +b3_data_delayed_3, +validity_mask_a_rows, +validity_mask_a_cols, +validity_mask_b_rows, +validity_mask_b_cols, +final_mat_mul_size, +a_loc, +b_loc +); + +input clk; +input reset; +input start_mat_mul; +input eltwise_mode; +output [`AWIDTH-1:0] a_addr; +output [`AWIDTH-1:0] b_addr; +input [`AWIDTH-1:0] address_mat_a; +input [`AWIDTH-1:0] address_mat_b; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; +input [7:0] clk_cnt; +output [`DWIDTH-1:0] a0_data; +output [`DWIDTH-1:0] a1_data_delayed_1; +output [`DWIDTH-1:0] a2_data_delayed_2; +output [`DWIDTH-1:0] a3_data_delayed_3; +output [`DWIDTH-1:0] b0_data; +output [`DWIDTH-1:0] b1_data_delayed_1; +output [`DWIDTH-1:0] b2_data_delayed_2; +output [`DWIDTH-1:0] b3_data_delayed_3; +input [`MASK_WIDTH-1:0] validity_mask_a_rows; +input [`MASK_WIDTH-1:0] validity_mask_a_cols; +input [`MASK_WIDTH-1:0] validity_mask_b_rows; +input [`MASK_WIDTH-1:0] validity_mask_b_cols; +input [7:0] final_mat_mul_size; +input [7:0] a_loc; +input [7:0] b_loc; + +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM A +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] a_addr; +reg a_mem_access; //flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin + //else if (clk_cnt >= a_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + if ((reset || ~start_mat_mul) || (clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + a_addr <= address_mat_a-address_stride_a[`AWIDTH-1:0]; + a_mem_access <= 0; + end + + //else if ((clk_cnt >= a_loc*`MAT_MUL_SIZE) && (clk_cnt < a_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + else if ((clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (a_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + a_addr <= a_addr + address_stride_a[`AWIDTH-1:0]; + a_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM A +////////////////////////////////////////////////////////////////////////// +reg [7:0] a_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + a_mem_access_counter <= 0; + end + else if (a_mem_access == 1) begin + a_mem_access_counter <= a_mem_access_counter + 1'b1; + + end + else begin + a_mem_access_counter <= 0; + end +end + +wire a_data_valid; //flag that tells whether the data from memory is valid +assign a_data_valid = + ((validity_mask_a_cols[0]==1'b0 && a_mem_access_counter==1) || + (validity_mask_a_cols[1]==1'b0 && a_mem_access_counter==2) || + (validity_mask_a_cols[2]==1'b0 && a_mem_access_counter==3) || + (validity_mask_a_cols[3]==1'b0 && a_mem_access_counter==4)) ? + 1'b0 : (a_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM A (systolic data setup) +////////////////////////////////////////////////////////////////////////// +//Slice data into chunks and qualify it with whether it is valid or not +assign a0_data = a_data[`DWIDTH-1:0] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[0]}}; +assign a1_data = a_data[2*`DWIDTH-1:`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[1]}}; +assign a2_data = a_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[2]}}; +assign a3_data = a_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[3]}}; + +//For larger matmuls, more such delaying flops will be needed +reg [`DWIDTH-1:0] a1_data_delayed_1_temp; +reg [`DWIDTH-1:0] a2_data_delayed_1_temp; +reg [`DWIDTH-1:0] a2_data_delayed_2_temp; +reg [`DWIDTH-1:0] a3_data_delayed_1_temp; +reg [`DWIDTH-1:0] a3_data_delayed_2_temp; +reg [`DWIDTH-1:0] a3_data_delayed_3_temp; +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + a1_data_delayed_1_temp <= 0; + a2_data_delayed_1_temp <= 0; + a2_data_delayed_2_temp <= 0; + a3_data_delayed_1_temp <= 0; + a3_data_delayed_2_temp <= 0; + a3_data_delayed_3_temp <= 0; + end + else begin + a1_data_delayed_1_temp <= a1_data; + a2_data_delayed_1_temp <= a2_data; + a2_data_delayed_2_temp <= a2_data_delayed_1_temp; + a3_data_delayed_1_temp <= a3_data; + a3_data_delayed_2_temp <= a3_data_delayed_1_temp; + a3_data_delayed_3_temp <= a3_data_delayed_2_temp; + end +end + +assign a1_data_delayed_1 = eltwise_mode ? a1_data : a1_data_delayed_1_temp; +assign a2_data_delayed_2 = eltwise_mode ? a2_data : a2_data_delayed_2_temp; +assign a3_data_delayed_3 = eltwise_mode ? a3_data : a3_data_delayed_3_temp; + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM B +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] b_addr; +reg b_mem_access; //flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin + //else if (clk_cnt >= b_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + if ((reset || ~start_mat_mul) || (clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + b_addr <= address_mat_b - address_stride_b[`AWIDTH-1:0]; + b_mem_access <= 0; + end + //else if ((clk_cnt >= b_loc*`MAT_MUL_SIZE) && (clk_cnt < b_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + else if ((clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (b_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + b_addr <= b_addr + address_stride_b[`AWIDTH-1:0]; + b_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM B +////////////////////////////////////////////////////////////////////////// +reg [7:0] b_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + b_mem_access_counter <= 0; + end + else if (b_mem_access == 1) begin + b_mem_access_counter <= b_mem_access_counter + 1'b1; + end + else begin + b_mem_access_counter <= 0; + end +end + +wire b_data_valid; //flag that tells whether the data from memory is valid +assign b_data_valid = + ((validity_mask_b_rows[0]==1'b0 && b_mem_access_counter==1) || + (validity_mask_b_rows[1]==1'b0 && b_mem_access_counter==2) || + (validity_mask_b_rows[2]==1'b0 && b_mem_access_counter==3) || + (validity_mask_b_rows[3]==1'b0 && b_mem_access_counter==4)) ? + 1'b0 : (b_mem_access_counter >= `MEM_ACCESS_LATENCY); + + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM B (systolic data setup) +////////////////////////////////////////////////////////////////////////// +//Slice data into chunks and qualify it with whether it is valid or not +assign b0_data = b_data[`DWIDTH-1:0] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[0]}}; +assign b1_data = b_data[2*`DWIDTH-1:`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[1]}}; +assign b2_data = b_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[2]}}; +assign b3_data = b_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[3]}}; + +//For larger matmuls, more such delaying flops will be needed +reg [`DWIDTH-1:0] b1_data_delayed_1_temp; +reg [`DWIDTH-1:0] b2_data_delayed_1_temp; +reg [`DWIDTH-1:0] b2_data_delayed_2_temp; +reg [`DWIDTH-1:0] b3_data_delayed_1_temp; +reg [`DWIDTH-1:0] b3_data_delayed_2_temp; +reg [`DWIDTH-1:0] b3_data_delayed_3_temp; +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + b1_data_delayed_1_temp <= 0; + b2_data_delayed_1_temp <= 0; + b2_data_delayed_2_temp <= 0; + b3_data_delayed_1_temp <= 0; + b3_data_delayed_2_temp <= 0; + b3_data_delayed_3_temp <= 0; + end + else begin + b1_data_delayed_1_temp <= b1_data; + b2_data_delayed_1_temp <= b2_data; + b2_data_delayed_2_temp <= b2_data_delayed_1_temp; + b3_data_delayed_1_temp <= b3_data; + b3_data_delayed_2_temp <= b3_data_delayed_1_temp; + b3_data_delayed_3_temp <= b3_data_delayed_2_temp; + end +end + + +assign b1_data_delayed_1 = eltwise_mode ? b1_data : b1_data_delayed_1_temp; +assign b2_data_delayed_2 = eltwise_mode ? b2_data : b2_data_delayed_2_temp; +assign b3_data_delayed_3 = eltwise_mode ? b3_data : b3_data_delayed_3_temp; + +endmodule + + + +////////////////////////////////////////////////////////////////////////// +// Systolically connected PEs +////////////////////////////////////////////////////////////////////////// +module systolic_pe_matrix( +reset, +clk, +pe_reset, +start_mat_mul, +ready_for_eltwise_op, +op, +a0, a1, a2, a3, +b0, b1, b2, b3, +matrixC00, +matrixC01, +matrixC02, +matrixC03, +matrixC10, +matrixC11, +matrixC12, +matrixC13, +matrixC20, +matrixC21, +matrixC22, +matrixC23, +matrixC30, +matrixC31, +matrixC32, +matrixC33, +a_data_out, +b_data_out, +flags +); + +input clk; +input reset; +input pe_reset; +input start_mat_mul; +input ready_for_eltwise_op; +input [1:0] op; +input [`DWIDTH-1:0] a0; +input [`DWIDTH-1:0] a1; +input [`DWIDTH-1:0] a2; +input [`DWIDTH-1:0] a3; +input [`DWIDTH-1:0] b0; +input [`DWIDTH-1:0] b1; +input [`DWIDTH-1:0] b2; +input [`DWIDTH-1:0] b3; +output [`DWIDTH-1:0] matrixC00; +output [`DWIDTH-1:0] matrixC01; +output [`DWIDTH-1:0] matrixC02; +output [`DWIDTH-1:0] matrixC03; +output [`DWIDTH-1:0] matrixC10; +output [`DWIDTH-1:0] matrixC11; +output [`DWIDTH-1:0] matrixC12; +output [`DWIDTH-1:0] matrixC13; +output [`DWIDTH-1:0] matrixC20; +output [`DWIDTH-1:0] matrixC21; +output [`DWIDTH-1:0] matrixC22; +output [`DWIDTH-1:0] matrixC23; +output [`DWIDTH-1:0] matrixC30; +output [`DWIDTH-1:0] matrixC31; +output [`DWIDTH-1:0] matrixC32; +output [`DWIDTH-1:0] matrixC33; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; +output [3:0] flags; + +wire [`DWIDTH-1:0] a00to01, a01to02, a02to03, a03to04; +wire [`DWIDTH-1:0] a10to11, a11to12, a12to13, a13to14; +wire [`DWIDTH-1:0] a20to21, a21to22, a22to23, a23to24; +wire [`DWIDTH-1:0] a30to31, a31to32, a32to33, a33to34; + +wire [`DWIDTH-1:0] b00to10, b10to20, b20to30, b30to40; +wire [`DWIDTH-1:0] b01to11, b11to21, b21to31, b31to41; +wire [`DWIDTH-1:0] b02to12, b12to22, b22to32, b32to42; +wire [`DWIDTH-1:0] b03to13, b13to23, b23to33, b33to43; + +wire effective_rst; +assign effective_rst = reset | pe_reset; + +wire [3:0] flags_pe00; +wire [3:0] flags_pe01; +wire [3:0] flags_pe02; +wire [3:0] flags_pe03; +wire [3:0] flags_pe10; +wire [3:0] flags_pe11; +wire [3:0] flags_pe12; +wire [3:0] flags_pe13; +wire [3:0] flags_pe20; +wire [3:0] flags_pe21; +wire [3:0] flags_pe22; +wire [3:0] flags_pe23; +wire [3:0] flags_pe30; +wire [3:0] flags_pe31; +wire [3:0] flags_pe32; +wire [3:0] flags_pe33; + +assign flags = +flags_pe00 | +flags_pe01 | +flags_pe02 | +flags_pe03 | +flags_pe10 | +flags_pe11 | +flags_pe12 | +flags_pe13 | +flags_pe20 | +flags_pe21 | +flags_pe22 | +flags_pe23 | +flags_pe30 | +flags_pe31 | +flags_pe32 | +flags_pe33; + +assign flags_pe03 = 4'b0; +assign flags_pe13 = 4'b0; +assign flags_pe23 = 4'b0; +assign flags_pe33 = 4'b0; + +processing_element pe00(.reset(effective_rst), .clk(clk), .flags(flags_pe00), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a0), .in_b(b0), .out_a(a00to01), .out_b(b00to10), .out_c(matrixC00)); +processing_element pe01(.reset(effective_rst), .clk(clk), .flags(flags_pe01), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a00to01), .in_b(b1), .out_a(a01to02), .out_b(b01to11), .out_c(matrixC01)); +processing_element pe02(.reset(effective_rst), .clk(clk), .flags(flags_pe02), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a01to02), .in_b(b2), .out_a(a02to03), .out_b(b02to12), .out_c(matrixC02)); +//processing_element pe03(.reset(effective_rst), .clk(clk), .flags(flags_pe03), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a02to03), .in_b(b3), .out_a(a03to04), .out_b(b03to13), .out_c(matrixC03)); + +processing_element pe10(.reset(effective_rst), .clk(clk), .flags(flags_pe10), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a1), .in_b(b00to10), .out_a(a10to11), .out_b(b10to20), .out_c(matrixC10)); +processing_element pe11(.reset(effective_rst), .clk(clk), .flags(flags_pe11), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a10to11), .in_b(b01to11), .out_a(a11to12), .out_b(b11to21), .out_c(matrixC11)); +processing_element pe12(.reset(effective_rst), .clk(clk), .flags(flags_pe12), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a11to12), .in_b(b02to12), .out_a(a12to13), .out_b(b12to22), .out_c(matrixC12)); +//processing_element pe13(.reset(effective_rst), .clk(clk), .flags(flags_pe13), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a12to13), .in_b(b03to13), .out_a(a13to14), .out_b(b13to23), .out_c(matrixC13)); + +processing_element pe20(.reset(effective_rst), .clk(clk), .flags(flags_pe20), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a2), .in_b(b10to20), .out_a(a20to21), .out_b(b20to30), .out_c(matrixC20)); +processing_element pe21(.reset(effective_rst), .clk(clk), .flags(flags_pe21), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a20to21), .in_b(b11to21), .out_a(a21to22), .out_b(b21to31), .out_c(matrixC21)); +processing_element pe22(.reset(effective_rst), .clk(clk), .flags(flags_pe22), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a21to22), .in_b(b12to22), .out_a(a22to23), .out_b(b22to32), .out_c(matrixC22)); +//processing_element pe23(.reset(effective_rst), .clk(clk), .flags(flags_pe23), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a22to23), .in_b(b13to23), .out_a(a23to24), .out_b(b23to33), .out_c(matrixC23)); + +processing_element pe30(.reset(effective_rst), .clk(clk), .flags(flags_pe30), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a3), .in_b(b20to30), .out_a(a30to31), .out_b(b30to40), .out_c(matrixC30)); +processing_element pe31(.reset(effective_rst), .clk(clk), .flags(flags_pe31), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a30to31), .in_b(b21to31), .out_a(a31to32), .out_b(b31to41), .out_c(matrixC31)); +processing_element pe32(.reset(effective_rst), .clk(clk), .flags(flags_pe32), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a31to32), .in_b(b22to32), .out_a(a32to33), .out_b(b32to42), .out_c(matrixC32)); +//processing_element pe33(.reset(effective_rst), .clk(clk), .flags(flags_pe33), .op(op), .ready_for_eltwise_op(ready_for_eltwise_op), .in_a(a32to33), .in_b(b23to33), .out_a(a33to34), .out_b(b33to43), .out_c(matrixC33)); + +assign a_data_out = {a33to34,a23to24,a13to14,a03to04}; +assign b_data_out = {b33to43,b32to42,b31to41,b30to40}; + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Processing element (PE) +////////////////////////////////////////////////////////////////////////// +module processing_element( + reset, + clk, + op, + ready_for_eltwise_op, + in_a, + in_b, + out_a, + out_b, + out_c, + flags + ); + + input reset; + input clk; + input [1:0] op; + input ready_for_eltwise_op; + input [`DWIDTH-1:0] in_a; + input [`DWIDTH-1:0] in_b; + output [`DWIDTH-1:0] out_a; + output [`DWIDTH-1:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + output [3:0] flags; + + reg [`DWIDTH-1:0] out_a; + reg [`DWIDTH-1:0] out_b; + wire [`DWIDTH-1:0] out_c; + + wire [`DWIDTH-1:0] out_mac; + +//op[1] op[0] +// 0 0 -> mat mul +// 0 1 -> elt mul +// 1 0 -> elt add +// 1 1 -> elt sub +wire eltwise_mode; +wire eltwise_mul; +wire eltwise_add; +wire eltwise_sub; +assign eltwise_mode = ( op[1] | op[0]); +assign eltwise_mul = (~op[1] & op[0]); +assign eltwise_add = ( op[1] & ~op[0]); +assign eltwise_sub = ( op[1] & op[0]); + + assign out_c = out_mac; + + //Keep the mac in reset if we're adding + wire mac_reset; + assign mac_reset = reset || (eltwise_mode && (~ready_for_eltwise_op)); + seq_mac u_mac(.a(in_a), .b(in_b), .out(out_mac), .eltwise_mode(eltwise_mode), .eltwise_add(eltwise_add), .reset(mac_reset), .clk(clk)); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + out_b<=0; + end + //stop shifting when you're in eltwise mode and ready to perform the op + else if ((~eltwise_mode) || (eltwise_mode & ~ready_for_eltwise_op)) begin + out_a<=in_a; + out_b<=in_b; + end + end + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Multiply-and-accumulate (MAC) block +////////////////////////////////////////////////////////////////////////// + +`ifdef complex_dsp + +module seq_mac(a, b, out, eltwise_mode, eltwise_add, reset, clk); +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +output [`DWIDTH-1:0] out; +input eltwise_mode; +input eltwise_add; +input reset; +input clk; + +reg [`DWIDTH-1:0] out; +wire [`DWIDTH-1:0] add_out; +wire [2*`DWIDTH-1:0] add_out_temp; +wire [2*`DWIDTH-1:0] mac_out; +reg [2*`DWIDTH-1:0] add_out_reg; + +reg [`DWIDTH-1:0] a_flopped; +reg [`DWIDTH-1:0] b_flopped; + +always @(posedge clk) begin + if (reset) begin + a_flopped <= 0; + b_flopped <= 0; + end else begin + a_flopped <= a; + b_flopped <= b; + end +end + +wire [17:0] a_in; +wire [18:0] b_in; +wire [36:0] c_out; +assign a_in = {1'b0,a_flopped}; +assign b_in = {1'b0,1'b0,b_flopped}; +mac_int_18x19 u_mac (.clk(clk), .reset(reset), .a(a_flopped), .b(b_flopped), .out(c_out)); +assign mac_out = c_out[2*`DWIDTH-1:0]; + + +wire [2*`DWIDTH-1:0] add_in1; +wire [2*`DWIDTH-1:0] add_in2; +assign add_in1 = {{`DWIDTH{1'b0}}, a_flopped}; +assign add_in2 = {{`DWIDTH{1'b0}}, b_flopped}; +qadd add_u1(.a(add_in1), .b(add_in2), .c(add_out_temp)); + +always @(posedge clk) begin + if (reset) begin + add_out_reg <= 0; + end + else if(eltwise_mode & eltwise_add) begin + add_out_reg <= add_out_temp; + end + else begin + add_out_reg <= mac_out; + end +end + +//down cast the result +assign add_out = + (add_out_reg[2*`DWIDTH-1] == 0) ? //positive number + ( + (|(add_out_reg[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 1, that means overlfow + {add_out_reg[2*`DWIDTH-1] , {(`DWIDTH-1){1'b1}}} : //sign bit and then all 1s + {add_out_reg[2*`DWIDTH-1] , add_out_reg[`DWIDTH-2:0]} + ) + : //negative number + ( + (|(add_out_reg[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 0, that means overlfow + {add_out_reg[2*`DWIDTH-1] , add_out_reg[`DWIDTH-2:0]} : + {add_out_reg[2*`DWIDTH-1] , {(`DWIDTH-1){1'b0}}} //sign bit and then all 0s + ); + + +always @(posedge clk) begin + if (reset) begin + out <= 0; + end + else begin + out <= add_out; + end +end + +endmodule + + +module qadd(a,b,c); +input [2*`DWIDTH-1:0] a; +input [2*`DWIDTH-1:0] b; +output [2*`DWIDTH-1:0] c; + +assign c = a + b; +//DW01_add #(`DWIDTH) u_add(.A(a), .B(b), .CI(1'b0), .SUM(c), .CO()); +endmodule + + + +`else +module seq_mac(a, b, out, eltwise_mode, eltwise_add, reset, clk); +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +output [`DWIDTH-1:0] out; +input eltwise_mode; +input eltwise_add; +input reset; +input clk; + +reg [`DWIDTH-1:0] out; +wire [2*`DWIDTH-1:0] add_out; + +reg [`DWIDTH-1:0] a_flopped; +reg [`DWIDTH-1:0] b_flopped; + +wire [2*`DWIDTH-1:0] mul_out; +reg [2*`DWIDTH-1:0] mul_out_reg; + +always @(posedge clk) begin + if (reset) begin + a_flopped <= 0; + b_flopped <= 0; + end else begin + a_flopped <= a; + b_flopped <= b; + end +end + +qmult mult_u1(.i_multiplicand(a_flopped), .i_multiplier(b_flopped), .o_result(mul_out)); + +always @(posedge clk) begin + if (reset) begin + mul_out_reg <= 0; + end else begin + mul_out_reg <= mul_out; + end +end + + +wire [2*`DWIDTH-1:0] add_in1; +wire [2*`DWIDTH-1:0] add_in2; +reg [2*`DWIDTH-1:0] add_out_reg; +assign add_in1 = (eltwise_mode & eltwise_add) ? {{`DWIDTH{1'b0}}, a_flopped} : add_out_reg; +assign add_in2 = (eltwise_mode & eltwise_add) ? {{`DWIDTH{1'b0}}, b_flopped} : mul_out_reg; + +qadd add_u1(.a(add_in1), .b(add_in2), .c(add_out)); + +always @(posedge clk) begin + if (reset) begin + add_out_reg <= 0; + end else begin + add_out_reg <= add_out; + end +end + +wire [`DWIDTH-1:0] mac_out; + +//down cast the result +assign mac_out = + (add_out_reg[2*`DWIDTH-1] == 0) ? //positive number + ( + (|(add_out_reg[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 1, that means overlfow + {add_out_reg[2*`DWIDTH-1] , {(`DWIDTH-1){1'b1}}} : //sign bit and then all 1s + {add_out_reg[2*`DWIDTH-1] , add_out_reg[`DWIDTH-2:0]} + ) + : //negative number + ( + (|(add_out_reg[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 0, that means overlfow + {add_out_reg[2*`DWIDTH-1] , add_out_reg[`DWIDTH-2:0]} : + {add_out_reg[2*`DWIDTH-1] , {(`DWIDTH-1){1'b0}}} //sign bit and then all 0s + ); + + +always @(posedge clk) begin + if (reset) begin + out <= 0; + end else begin + out <= mac_out; + end +end + +endmodule + + +module qmult(i_multiplicand,i_multiplier,o_result); +input [`DWIDTH-1:0] i_multiplicand; +input [`DWIDTH-1:0] i_multiplier; +output [2*`DWIDTH-1:0] o_result; + +assign o_result = i_multiplicand * i_multiplier; +//DW02_mult #(`DWIDTH,`DWIDTH) u_mult(.A(i_multiplicand), .B(i_multiplier), .TC(1'b1), .PRODUCT(o_result)); + +endmodule + +module qadd(a,b,c); +input [2*`DWIDTH-1:0] a; +input [2*`DWIDTH-1:0] b; +output [2*`DWIDTH-1:0] c; + +assign c = a + b; +//DW01_add #(`DWIDTH) u_add(.A(a), .B(b), .CI(1'b0), .SUM(c), .CO()); +endmodule + +`endif + diff --git a/designs/koios/conv_layer/conv_layer_random.sv b/designs/koios/conv_layer/conv_layer_random.sv new file mode 100644 index 000000000..6d339084a --- /dev/null +++ b/designs/koios/conv_layer/conv_layer_random.sv @@ -0,0 +1,89 @@ +/* +Random inputs to conv layer +*/ + +`include "../../random_number_generator.sv" + +`define DWIDTH 16 +`define AWIDTH 10 +`define MEM_SIZE 1024 +`define DESIGN_SIZE 8 +`define MAT_MUL_SIZE 4 +`define MASK_WIDTH 4 +`define LOG2_MAT_MUL_SIZE 2 +`define NUM_CYCLES_IN_MAC 3 +`define MEM_ACCESS_LATENCY 1 +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 +`define ADDR_STRIDE_WIDTH 16 +`define REG_STDN_TPU_ADDR 32'h4 +`define REG_MATRIX_A_ADDR 32'he +`define REG_MATRIX_B_ADDR 32'h12 +`define REG_MATRIX_C_ADDR 32'h16 +`define REG_VALID_MASK_A_ROWS_ADDR 32'h20 +`define REG_VALID_MASK_A_COLS_ADDR 32'h54 +`define REG_VALID_MASK_B_ROWS_ADDR 32'h5c +`define REG_VALID_MASK_B_COLS_ADDR 32'h58 +`define REG_MATRIX_A_STRIDE_ADDR 32'h28 +`define REG_MATRIX_B_STRIDE_ADDR 32'h32 +`define REG_MATRIX_C_STRIDE_ADDR 32'h36 +`define ADDRESS_BASE_A 10'd0 +`define ADDRESS_BASE_B 10'd0 +`define ADDRESS_BASE_C 10'd0 + +module conv_layer_random( + input logic clk, + input logic clk_mem, + input logic resetn, + input logic pe_resetn, + input logic start, + output logic done, + input logic [7:0] bram_select, + output logic [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_ext +); + +logic [`AWIDTH-1:0] bram_addr_ext; +RandomNumberGenerator #( + .RANDOM_WIDTH(`AWIDTH), + .SEED(0) +) rng ( + .clk(clk), + .reset(resetn), + .random_number(bram_addr_ext) +); + +logic [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_ext; +RandomNumberGenerator #( + .RANDOM_WIDTH(`MAT_MUL_SIZE*`DWIDTH), + .SEED(0) +) rng2 ( + .clk(clk), + .reset(resetn), + .random_number(bram_wdata_ext) +); + +logic [`MAT_MUL_SIZE-1:0] bram_we_ext; +RandomNumberGenerator #( + .RANDOM_WIDTH(`MAT_MUL_SIZE), + .SEED(0) +) rng3 ( + .clk(clk), + .reset(resetn), + .random_number(bram_we_ext) +); + +conv_layer( + clk, + clk_mem, + resetn, + pe_resetn, + start, + done, + bram_select, + bram_addr_ext, + bram_rdata_ext, + bram_wdata_ext, + bram_we_ext +); + +endmodule \ No newline at end of file diff --git a/designs/koios/conv_layer/design.yaml b/designs/koios/conv_layer/design.yaml new file mode 100644 index 000000000..c2b3b24b6 --- /dev/null +++ b/designs/koios/conv_layer/design.yaml @@ -0,0 +1 @@ +top: conv_layer_random diff --git a/designs/koios/conv_layer_hls/conv_layer_hls.v b/designs/koios/conv_layer_hls/conv_layer_hls.v new file mode 100644 index 000000000..6546e8d9a --- /dev/null +++ b/designs/koios/conv_layer_hls/conv_layer_hls.v @@ -0,0 +1,7807 @@ +////////////////////////////////////////////////////////////////////////////// +// HLS generated design for a convolution layer. The layer is one of the layers +// from Tiny Darknet network. Here are some properties of the design: +// 1. Uses ieee float16 precision. +// 2. Uses sliding window convolution algorithm. +// 3. Input dimensions are 56x56x32, output dimensions are 56x56x16 and weights are 1x1x32. +// 4. 3 input channels and 2 output channels processed at the same time. +////////////////////////////////////////////////////////////////////////////// + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +////////////////////////////////////////////////////////////////////////////// +// Abridged for VTR by: Daniel Rauch +////////////////////////////////////////////////////////////////////////////// + + +module dpram ( + + clk, + + address_a, + + address_b, + + wren_a, + + wren_b, + + data_a, + + data_b, + + out_a, + + out_b + +); + +parameter AWIDTH=10; + +parameter NUM_WORDS=1024; + +parameter DWIDTH=32; + +input clk; + +input [(AWIDTH-1):0] address_a; + +input [(AWIDTH-1):0] address_b; + +input wren_a; + +input wren_b; + +input [(DWIDTH-1):0] data_a; + +input [(DWIDTH-1):0] data_b; + +output reg [(DWIDTH-1):0] out_a; + +output reg [(DWIDTH-1):0] out_b; + + + +`ifndef hard_mem + + + +reg [DWIDTH-1:0] ram[NUM_WORDS-1:0]; + +always @ (posedge clk) begin + + if (wren_a) begin + + ram[address_a] <= data_a; + + end + + out_a <= ram[address_a]; + + +end + + + +always @ (posedge clk) begin + + if (wren_b) begin + + ram[address_b] <= data_b; + + end + + out_b <= ram[address_b]; + +end + + + +`else + + +defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; +defparam u_dual_port_ram.DATA_WIDTH = DWIDTH; + +dual_port_ram u_dual_port_ram( + +.addr1(address_a), + +.we1(wren_a), + +.data1(data_a), + +.out1(out_a), + +.addr2(address_b), + +.we2(wren_b), + +.data2(data_b), + +.out2(out_b), + +.clk(clk) + +); + +`endif + +endmodule + +`timescale 1 ns / 1 ps + +module td_fused_top_Block_entry_proc_proc505 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + tmp, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] tmp; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg ap_block_state1; +reg [15:0] ap_return_preg; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 ap_return_preg = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 16'd0; + end else begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return_preg <= tmp; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return = tmp; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 1'b0; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //td_fused_top_Block_entry_proc_proc505 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +/*`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP49028_accum1_out_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 3; +parameter MEM_SIZE = 8; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule*/ + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP49028_accum1_out_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd8; +parameter AddressWidth = 32'd3; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +/*td_fused_top_dataflow_in_loop_TOP_LOOP49028_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP49028_accum1_out_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ));*/ + +wire wren0, wren1; +assign wren0 = we0 & ce0; +assign wren1 = we1 & ce1; +wire [DataWidth-1:0] q1; +dpram +#(.AWIDTH(AddressWidth), + .NUM_WORDS(AddressRange), + .DWIDTH(DataWidth)) +td_fused_top_dataflow_in_loop_TOP_LOOP49028_accum1_out_0_memcore_ram_U ( + .clk(clk), + .address_a(address0), + .address_b(address1), + .wren_a(wren0), + .wren_b(wren1), + .data_a(d0), + .data_b(d1), + .out_a(q0), + .out_b(q1) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP49028_accum1_out_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 3, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP49028_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP49028_accum1_out_0_memcore_U_0 ( + .clk ( clk ), + .reset ( reset ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .address0 ( buf_a0_0 ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .address1 ( buf_a1_0 ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP49028_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP49028_accum1_out_0_memcore_U_1 ( + .clk ( clk ), + .reset ( reset ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .address0 ( buf_a0_1 ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .address1 ( buf_a1_1 ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +/*`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP49028_ifmap_vec_0_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 5; +parameter MEM_SIZE = 32; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule +*/ + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP49028_ifmap_vec_0_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd32; +parameter AddressWidth = 32'd5; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +/*td_fused_top_dataflow_in_loop_TOP_LOOP49028_ifmap_vec_0_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP49028_ifmap_vec_0_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ));*/ + +wire wren0, wren1; +assign wren0 = we0 & ce0; +assign wren1 = we1 & ce1; +wire [DataWidth-1:0] q1; +dpram +#(.AWIDTH(AddressWidth), + .NUM_WORDS(AddressRange), + .DWIDTH(DataWidth)) +td_fused_top_dataflow_in_loop_TOP_LOOP49028_ifmap_vec_0_0_memcore_ram_U( + .clk(clk), + .address_a(address0), + .address_b(address1), + .wren_a(wren0), + .wren_b(wren1), + .data_a(d0), + .data_b(d1), + .out_a(q0), + .out_b(q1) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP49028_ifmap_vec_0_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 5, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP49028_ifmap_vec_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP49028_ifmap_vec_0_0_memcore_U_0 ( + .clk ( clk ), + .reset ( reset ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .address0 ( buf_a0_0 ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .address1 ( buf_a1_0 ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP49028_ifmap_vec_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP49028_ifmap_vec_0_0_memcore_U_1 ( + .clk ( clk ), + .reset ( reset ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .address0 ( buf_a0_1 ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .address1 ( buf_a1_1 ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +//assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign i_q0 = (prev_iptr == 1'b1) ? buf_q0_1 : buf_q0_0; + +//assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); +wire [DataWidth-1:0] buf_q0_prev; +assign buf_q0_prev = (prev_tptr == 1'b1) ? buf_q0_1 : buf_q0_0; +assign t_q0 = reg_valid0 ? reg_q0 : buf_q0_prev; + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= buf_q0_prev; + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +/*`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP49028_products_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 5; +parameter MEM_SIZE = 32; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule*/ + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP49028_products_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd32; +parameter AddressWidth = 32'd5; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +/*td_fused_top_dataflow_in_loop_TOP_LOOP49028_products_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP49028_products_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ));*/ + +wire wren0, wren1; +assign wren0 = we0 & ce0; +assign wren1 = 1'b0; //we1 & ce1; +wire [DataWidth-1:0] d1; +dpram +#(.AWIDTH(AddressWidth), + .NUM_WORDS(AddressRange), + .DWIDTH(DataWidth)) +td_fused_top_dataflow_in_loop_TOP_LOOP49028_products_0_memcore_ram_U( + .clk(clk), + .address_a(address0), + .address_b(address1), + .wren_a(wren0), + .wren_b(wren1), + .data_a(d0), + .data_b(d1), + .out_a(q0), + .out_b(q1) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP49028_products_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 5, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire [AddressWidth-1:0] i_address1, + output wire [DataWidth-1:0] i_q1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire [AddressWidth-1:0] t_address1, + output wire [DataWidth-1:0] t_q1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_q1_0, buf_q1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP49028_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP49028_products_0_memcore_U_0 ( + .clk ( clk ), + .reset ( reset ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .address0 ( buf_a0_0 ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .address1 ( buf_a1_0 ), + .q1 ( buf_q1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP49028_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP49028_products_0_memcore_U_1 ( + .clk ( clk ), + .reset ( reset ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .address0 ( buf_a0_1 ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .address1 ( buf_a1_1 ), + .q1 ( buf_q1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign i_q1 = (prev_iptr == 1'b1 ? buf_q1_1 : buf_q1_0); +assign t_q1 = reg_valid1 ? reg_q1 : (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// reg_q1 and reg_valid1 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q1 <= 1'b0; + reg_valid1 <= 1'b0; + end else if (!t_ce1 && !reg_valid1) begin + reg_q1 <= (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + reg_valid1 <= 1'b1; + end else if (t_ce1) begin + reg_valid1 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP49028 ( + ap_clk, + ap_rst, + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + ap_start, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +input ap_clk; +input ap_rst; +output [14:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [14:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [8:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [8:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [11:0] out_data_address0; +output out_data_ce0; +output [255:0] out_data_d0; +input [255:0] out_data_q0; +output out_data_we0; +output [11:0] out_data_address1; +output out_data_ce1; +output [255:0] out_data_d1; +input [255:0] out_data_q1; +output out_data_we1; +input ap_start; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +wire [15:0] ifmap_vec_0_0_i_q0; +wire [15:0] ifmap_vec_0_0_t_q0; +wire [15:0] weight_vecs_0_0_0_i_q0; +wire [15:0] weight_vecs_0_0_0_t_q0; +wire [15:0] products_0_i_q0; +wire [15:0] products_0_i_q1; +wire [15:0] products_0_t_q0; +wire [15:0] products_0_t_q1; +wire [15:0] accum1_out_0_i_q0; +wire [15:0] accum1_out_0_t_q0; +wire tdf3_get_next_ijk_U0_ap_start; +wire tdf3_get_next_ijk_U0_ap_done; +wire tdf3_get_next_ijk_U0_ap_continue; +wire tdf3_get_next_ijk_U0_ap_idle; +wire tdf3_get_next_ijk_U0_ap_ready; +wire [15:0] tdf3_get_next_ijk_U0_indices_0_din; +wire tdf3_get_next_ijk_U0_indices_0_write; +wire [15:0] tdf3_get_next_ijk_U0_indices_1_din; +wire tdf3_get_next_ijk_U0_indices_1_write; +wire [3:0] tdf3_get_next_ijk_U0_ap_return; +wire ap_channel_done_indices_2; +wire indices_2_full_n; +wire tdf3_readInputs_U0_ap_start; +wire tdf3_readInputs_U0_ap_done; +wire tdf3_readInputs_U0_ap_continue; +wire tdf3_readInputs_U0_ap_idle; +wire tdf3_readInputs_U0_ap_ready; +wire [14:0] tdf3_readInputs_U0_in_data_address0; +wire tdf3_readInputs_U0_in_data_ce0; +wire tdf3_readInputs_U0_indices_01_read; +wire tdf3_readInputs_U0_indices_12_read; +wire [4:0] tdf3_readInputs_U0_ifmap_vec_0_0_address0; +wire tdf3_readInputs_U0_ifmap_vec_0_0_ce0; +wire tdf3_readInputs_U0_ifmap_vec_0_0_we0; +wire [15:0] tdf3_readInputs_U0_ifmap_vec_0_0_d0; +wire [4:0] tdf3_readInputs_U0_ifmap_vec_0_0_address1; +wire tdf3_readInputs_U0_ifmap_vec_0_0_ce1; +wire tdf3_readInputs_U0_ifmap_vec_0_0_we1; +wire [15:0] tdf3_readInputs_U0_ifmap_vec_0_0_d1; +wire [5:0] tdf3_readInputs_U0_indices_01_out_din; +wire tdf3_readInputs_U0_indices_01_out_write; +wire [11:0] tdf3_readInputs_U0_indices_12_out_din; +wire tdf3_readInputs_U0_indices_12_out_write; +wire tdf3_readInputs_U0_in_data_full_n; +wire tdf3_readInputs_U0_in_data_write; +wire ap_channel_done_ifmap_vec_0_0; +wire tdf3_readInputs_U0_ifmap_vec_0_0_full_n; +wire tdf3_readFilters30_U0_ap_start; +wire tdf3_readFilters30_U0_ap_done; +wire tdf3_readFilters30_U0_ap_continue; +wire tdf3_readFilters30_U0_ap_idle; +wire tdf3_readFilters30_U0_ap_ready; +wire [8:0] tdf3_readFilters30_U0_filter_data_address0; +wire tdf3_readFilters30_U0_filter_data_ce0; +wire [4:0] tdf3_readFilters30_U0_weight_vecs_0_0_0_address0; +wire tdf3_readFilters30_U0_weight_vecs_0_0_0_ce0; +wire tdf3_readFilters30_U0_weight_vecs_0_0_0_we0; +wire [15:0] tdf3_readFilters30_U0_weight_vecs_0_0_0_d0; +wire ap_channel_done_weight_vecs_0_0_0; +wire tdf3_readFilters30_U0_weight_vecs_0_0_0_full_n; +wire tdf3_dot_product_U0_ap_start; +wire tdf3_dot_product_U0_ap_done; +wire tdf3_dot_product_U0_ap_continue; +wire tdf3_dot_product_U0_ap_idle; +wire tdf3_dot_product_U0_ap_ready; +wire [4:0] tdf3_dot_product_U0_ifmap_vec_0_0_address0; +wire tdf3_dot_product_U0_ifmap_vec_0_0_ce0; +wire [4:0] tdf3_dot_product_U0_weight_vecs_0_0_0_address0; +wire tdf3_dot_product_U0_weight_vecs_0_0_0_ce0; +wire [4:0] tdf3_dot_product_U0_products_0_address0; +wire tdf3_dot_product_U0_products_0_ce0; +wire tdf3_dot_product_U0_products_0_we0; +wire [15:0] tdf3_dot_product_U0_products_0_d0; +wire ap_channel_done_products_0; +wire tdf3_dot_product_U0_products_0_full_n; +wire tdf3_accum_1_U0_ap_start; +wire tdf3_accum_1_U0_ap_done; +wire tdf3_accum_1_U0_ap_continue; +wire tdf3_accum_1_U0_ap_idle; +wire tdf3_accum_1_U0_ap_ready; +wire [4:0] tdf3_accum_1_U0_accum_in_0_address0; +wire tdf3_accum_1_U0_accum_in_0_ce0; +wire [4:0] tdf3_accum_1_U0_accum_in_0_address1; +wire tdf3_accum_1_U0_accum_in_0_ce1; +wire [2:0] tdf3_accum_1_U0_accum_out_address0; +wire tdf3_accum_1_U0_accum_out_ce0; +wire tdf3_accum_1_U0_accum_out_we0; +wire [15:0] tdf3_accum_1_U0_accum_out_d0; +wire [2:0] tdf3_accum_1_U0_accum_out_address1; +wire tdf3_accum_1_U0_accum_out_ce1; +wire tdf3_accum_1_U0_accum_out_we1; +wire [15:0] tdf3_accum_1_U0_accum_out_d1; +wire ap_channel_done_accum1_out_0; +wire tdf3_accum_1_U0_accum_out_full_n; +wire tdf3_accum_2_U0_ap_start; +wire tdf3_accum_2_U0_ap_done; +wire tdf3_accum_2_U0_ap_continue; +wire tdf3_accum_2_U0_ap_idle; +wire tdf3_accum_2_U0_ap_ready; +wire [15:0] tdf3_accum_2_U0_accum_in_14; +wire tdf3_accum_2_U0_accum_in_14_ap_vld; +wire [2:0] tdf3_accum_2_U0_accum_in_address0; +wire tdf3_accum_2_U0_accum_in_ce0; +wire ap_channel_done_tmp_channel; +wire tmp_channel_full_n; +wire Block_entry_proc_proc505_U0_ap_start; +wire Block_entry_proc_proc505_U0_ap_done; +wire Block_entry_proc_proc505_U0_ap_continue; +wire Block_entry_proc_proc505_U0_ap_idle; +wire Block_entry_proc_proc505_U0_ap_ready; +wire [15:0] Block_entry_proc_proc505_U0_ap_return; +wire ap_channel_done_outputs_0; +wire outputs_0_full_n; +wire tdf3_writeOutputs_unaligned_U0_ap_start; +wire tdf3_writeOutputs_unaligned_U0_ap_done; +wire tdf3_writeOutputs_unaligned_U0_ap_continue; +wire tdf3_writeOutputs_unaligned_U0_ap_idle; +wire tdf3_writeOutputs_unaligned_U0_ap_ready; +wire tdf3_writeOutputs_unaligned_U0_indices_01_read; +wire tdf3_writeOutputs_unaligned_U0_indices_12_read; +wire [11:0] tdf3_writeOutputs_unaligned_U0_out_data_address0; +wire tdf3_writeOutputs_unaligned_U0_out_data_ce0; +wire [11:0] tdf3_writeOutputs_unaligned_U0_out_data_address1; +wire tdf3_writeOutputs_unaligned_U0_out_data_ce1; +wire tdf3_writeOutputs_unaligned_U0_out_data_we1; +wire [255:0] tdf3_writeOutputs_unaligned_U0_out_data_d1; +wire tdf3_writeOutputs_unaligned_U0_out_data_full_n; +wire tdf3_writeOutputs_unaligned_U0_out_data_write; +wire ap_sync_continue; +wire ifmap_vec_0_0_i_full_n; +wire ifmap_vec_0_0_t_empty_n; +wire weight_vecs_0_0_0_i_full_n; +wire weight_vecs_0_0_0_t_empty_n; +wire products_0_i_full_n; +wire products_0_t_empty_n; +wire [15:0] products_0_t_d1; +wire products_0_t_we1; +wire accum1_out_0_i_full_n; +wire accum1_out_0_t_empty_n; +wire indices_01_c_full_n; +wire [15:0] indices_01_c_dout; +wire indices_01_c_empty_n; +wire indices_12_c_full_n; +wire [15:0] indices_12_c_dout; +wire indices_12_c_empty_n; +wire [3:0] indices_2_dout; +wire indices_2_empty_n; +wire indices_01_c1_full_n; +wire [5:0] indices_01_c1_dout; +wire indices_01_c1_empty_n; +wire indices_12_c2_full_n; +wire [11:0] indices_12_c2_dout; +wire indices_12_c2_empty_n; +wire [15:0] tmp_channel_dout; +wire tmp_channel_empty_n; +wire [15:0] outputs_0_dout; +wire outputs_0_empty_n; +wire ap_sync_done; +wire ap_sync_ready; +reg ap_sync_reg_tdf3_get_next_ijk_U0_ap_ready; +wire ap_sync_tdf3_get_next_ijk_U0_ap_ready; +reg ap_sync_reg_tdf3_readInputs_U0_ap_ready; +wire ap_sync_tdf3_readInputs_U0_ap_ready; +reg ap_sync_reg_tdf3_writeOutputs_unaligned_U0_ap_ready; +wire ap_sync_tdf3_writeOutputs_unaligned_U0_ap_ready; +wire tdf3_get_next_ijk_U0_start_full_n; +wire tdf3_get_next_ijk_U0_start_write; +wire tdf3_readInputs_U0_start_full_n; +wire tdf3_readInputs_U0_start_write; +wire tdf3_readFilters30_U0_start_full_n; +wire tdf3_readFilters30_U0_start_write; +wire tdf3_dot_product_U0_start_full_n; +wire tdf3_dot_product_U0_start_write; +wire tdf3_accum_1_U0_start_full_n; +wire tdf3_accum_1_U0_start_write; +wire tdf3_accum_2_U0_start_full_n; +wire tdf3_accum_2_U0_start_write; +wire Block_entry_proc_proc505_U0_start_full_n; +wire Block_entry_proc_proc505_U0_start_write; +wire tdf3_writeOutputs_unaligned_U0_start_full_n; +wire tdf3_writeOutputs_unaligned_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_sync_reg_tdf3_get_next_ijk_U0_ap_ready = 1'b0; +#0 ap_sync_reg_tdf3_readInputs_U0_ap_ready = 1'b0; +#0 ap_sync_reg_tdf3_writeOutputs_unaligned_U0_ap_ready = 1'b0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP49028_ifmap_vec_0_0 #( + .DataWidth( 16 ), + .AddressRange( 32 ), + .AddressWidth( 5 )) +ifmap_vec_0_0_U( + .clk(ap_clk), + .reset(ap_rst), + // i + .i_ce(1'b1), + .i_write(tdf3_readInputs_U0_ap_done), + .i_full_n(ifmap_vec_0_0_i_full_n), + .i_ce0(tdf3_readInputs_U0_ifmap_vec_0_0_ce0), + .i_we0(tdf3_readInputs_U0_ifmap_vec_0_0_we0), + .i_address0(tdf3_readInputs_U0_ifmap_vec_0_0_address0), + .i_d0(tdf3_readInputs_U0_ifmap_vec_0_0_d0), + .i_q0(ifmap_vec_0_0_i_q0), + .i_ce1(tdf3_readInputs_U0_ifmap_vec_0_0_ce1), + .i_we1(tdf3_readInputs_U0_ifmap_vec_0_0_we1), + .i_address1(tdf3_readInputs_U0_ifmap_vec_0_0_address1), + .i_d1(tdf3_readInputs_U0_ifmap_vec_0_0_d1), + // t + .t_ce(1'b1), + .t_read(tdf3_dot_product_U0_ap_ready), + .t_empty_n(ifmap_vec_0_0_t_empty_n), + .t_ce0(tdf3_dot_product_U0_ifmap_vec_0_0_ce0), + .t_we0(1'b0), + .t_address0(tdf3_dot_product_U0_ifmap_vec_0_0_address0), + .t_d0(16'd0), + .t_q0(ifmap_vec_0_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(5'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP49028_weight_vecs_0_0_0 #( + .DataWidth( 16 ), + .AddressRange( 32 ), + .AddressWidth( 5 )) +weight_vecs_0_0_0_U( + .clk(ap_clk), + .reset(ap_rst), + // i + .i_ce(1'b1), + .i_write(tdf3_readFilters30_U0_ap_done), + .i_full_n(weight_vecs_0_0_0_i_full_n), + .i_ce0(tdf3_readFilters30_U0_weight_vecs_0_0_0_ce0), + .i_we0(tdf3_readFilters30_U0_weight_vecs_0_0_0_we0), + .i_address0(tdf3_readFilters30_U0_weight_vecs_0_0_0_address0), + .i_d0(tdf3_readFilters30_U0_weight_vecs_0_0_0_d0), + .i_q0(weight_vecs_0_0_0_i_q0), + // t + .t_ce(1'b1), + .t_read(tdf3_dot_product_U0_ap_ready), + .t_empty_n(weight_vecs_0_0_0_t_empty_n), + .t_ce0(tdf3_dot_product_U0_weight_vecs_0_0_0_ce0), + .t_we0(1'b0), + .t_address0(tdf3_dot_product_U0_weight_vecs_0_0_0_address0), + .t_d0(16'd0), + .t_q0(weight_vecs_0_0_0_t_q0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP49028_products_0 #( + .DataWidth( 16 ), + .AddressRange( 32 ), + .AddressWidth( 5 )) +products_0_U( + .clk(ap_clk), + .reset(ap_rst), + // i + .i_ce(1'b1), + .i_write(tdf3_dot_product_U0_ap_done), + .i_full_n(products_0_i_full_n), + .i_ce0(tdf3_dot_product_U0_products_0_ce0), + .i_we0(tdf3_dot_product_U0_products_0_we0), + .i_address0(tdf3_dot_product_U0_products_0_address0), + .i_d0(tdf3_dot_product_U0_products_0_d0), + .i_q0(products_0_i_q0), + .i_ce1(1'b0), + .i_address1(5'd0), + .i_q1(products_0_i_q1), + // t + .t_ce(1'b1), + .t_read(tdf3_accum_1_U0_ap_ready), + .t_empty_n(products_0_t_empty_n), + .t_ce0(tdf3_accum_1_U0_accum_in_0_ce0), + .t_we0(1'b0), + .t_address0(tdf3_accum_1_U0_accum_in_0_address0), + .t_d0(16'd0), + .t_q0(products_0_t_q0), + .t_ce1(tdf3_accum_1_U0_accum_in_0_ce1), + .t_address1(tdf3_accum_1_U0_accum_in_0_address1), + .t_q1(products_0_t_q1) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP49028_accum1_out_0 #( + .DataWidth( 16 ), + .AddressRange( 8 ), + .AddressWidth( 3 )) +accum1_out_0_U( + .clk(ap_clk), + .reset(ap_rst), + // i + .i_ce(1'b1), + .i_write(tdf3_accum_1_U0_ap_done), + .i_full_n(accum1_out_0_i_full_n), + .i_ce0(tdf3_accum_1_U0_accum_out_ce0), + .i_we0(tdf3_accum_1_U0_accum_out_we0), + .i_address0(tdf3_accum_1_U0_accum_out_address0), + .i_d0(tdf3_accum_1_U0_accum_out_d0), + .i_q0(accum1_out_0_i_q0), + .i_ce1(tdf3_accum_1_U0_accum_out_ce1), + .i_we1(tdf3_accum_1_U0_accum_out_we1), + .i_address1(tdf3_accum_1_U0_accum_out_address1), + .i_d1(tdf3_accum_1_U0_accum_out_d1), + // t + .t_ce(1'b1), + .t_read(tdf3_accum_2_U0_ap_ready), + .t_empty_n(accum1_out_0_t_empty_n), + .t_ce0(tdf3_accum_2_U0_accum_in_ce0), + .t_we0(1'b0), + .t_address0(tdf3_accum_2_U0_accum_in_address0), + .t_d0(16'd0), + .t_q0(accum1_out_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(3'd0), + .t_d1(16'd0) +); + +td_fused_top_tdf3_get_next_ijk tdf3_get_next_ijk_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf3_get_next_ijk_U0_ap_start), + .ap_done(tdf3_get_next_ijk_U0_ap_done), + .ap_continue(tdf3_get_next_ijk_U0_ap_continue), + .ap_idle(tdf3_get_next_ijk_U0_ap_idle), + .ap_ready(tdf3_get_next_ijk_U0_ap_ready), + .indices_0_din(tdf3_get_next_ijk_U0_indices_0_din), + .indices_0_full_n(indices_01_c_full_n), + .indices_0_write(tdf3_get_next_ijk_U0_indices_0_write), + .indices_1_din(tdf3_get_next_ijk_U0_indices_1_din), + .indices_1_full_n(indices_12_c_full_n), + .indices_1_write(tdf3_get_next_ijk_U0_indices_1_write), + .ap_return(tdf3_get_next_ijk_U0_ap_return) +); + +td_fused_top_tdf3_readInputs tdf3_readInputs_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf3_readInputs_U0_ap_start), + .ap_done(tdf3_readInputs_U0_ap_done), + .ap_continue(tdf3_readInputs_U0_ap_continue), + .ap_idle(tdf3_readInputs_U0_ap_idle), + .ap_ready(tdf3_readInputs_U0_ap_ready), + .in_data_address0(tdf3_readInputs_U0_in_data_address0), + .in_data_ce0(tdf3_readInputs_U0_in_data_ce0), + .in_data_q0(in_data_q0), + .indices_01_dout(indices_01_c_dout), + .indices_01_empty_n(indices_01_c_empty_n), + .indices_01_read(tdf3_readInputs_U0_indices_01_read), + .indices_12_dout(indices_12_c_dout), + .indices_12_empty_n(indices_12_c_empty_n), + .indices_12_read(tdf3_readInputs_U0_indices_12_read), + .ifmap_vec_0_0_address0(tdf3_readInputs_U0_ifmap_vec_0_0_address0), + .ifmap_vec_0_0_ce0(tdf3_readInputs_U0_ifmap_vec_0_0_ce0), + .ifmap_vec_0_0_we0(tdf3_readInputs_U0_ifmap_vec_0_0_we0), + .ifmap_vec_0_0_d0(tdf3_readInputs_U0_ifmap_vec_0_0_d0), + .ifmap_vec_0_0_address1(tdf3_readInputs_U0_ifmap_vec_0_0_address1), + .ifmap_vec_0_0_ce1(tdf3_readInputs_U0_ifmap_vec_0_0_ce1), + .ifmap_vec_0_0_we1(tdf3_readInputs_U0_ifmap_vec_0_0_we1), + .ifmap_vec_0_0_d1(tdf3_readInputs_U0_ifmap_vec_0_0_d1), + .indices_01_out_din(tdf3_readInputs_U0_indices_01_out_din), + .indices_01_out_full_n(indices_01_c1_full_n), + .indices_01_out_write(tdf3_readInputs_U0_indices_01_out_write), + .indices_12_out_din(tdf3_readInputs_U0_indices_12_out_din), + .indices_12_out_full_n(indices_12_c2_full_n), + .indices_12_out_write(tdf3_readInputs_U0_indices_12_out_write) +); + +td_fused_top_tdf3_readFilters30 tdf3_readFilters30_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf3_readFilters30_U0_ap_start), + .ap_done(tdf3_readFilters30_U0_ap_done), + .ap_continue(tdf3_readFilters30_U0_ap_continue), + .ap_idle(tdf3_readFilters30_U0_ap_idle), + .ap_ready(tdf3_readFilters30_U0_ap_ready), + .filter_data_address0(tdf3_readFilters30_U0_filter_data_address0), + .filter_data_ce0(tdf3_readFilters30_U0_filter_data_ce0), + .filter_data_q0(filter_data_q0), + .k_21(indices_2_dout), + .weight_vecs_0_0_0_address0(tdf3_readFilters30_U0_weight_vecs_0_0_0_address0), + .weight_vecs_0_0_0_ce0(tdf3_readFilters30_U0_weight_vecs_0_0_0_ce0), + .weight_vecs_0_0_0_we0(tdf3_readFilters30_U0_weight_vecs_0_0_0_we0), + .weight_vecs_0_0_0_d0(tdf3_readFilters30_U0_weight_vecs_0_0_0_d0) +); + +td_fused_top_tdf3_dot_product tdf3_dot_product_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf3_dot_product_U0_ap_start), + .ap_done(tdf3_dot_product_U0_ap_done), + .ap_continue(tdf3_dot_product_U0_ap_continue), + .ap_idle(tdf3_dot_product_U0_ap_idle), + .ap_ready(tdf3_dot_product_U0_ap_ready), + .ifmap_vec_0_0_address0(tdf3_dot_product_U0_ifmap_vec_0_0_address0), + .ifmap_vec_0_0_ce0(tdf3_dot_product_U0_ifmap_vec_0_0_ce0), + .ifmap_vec_0_0_q0(ifmap_vec_0_0_t_q0), + .weight_vecs_0_0_0_address0(tdf3_dot_product_U0_weight_vecs_0_0_0_address0), + .weight_vecs_0_0_0_ce0(tdf3_dot_product_U0_weight_vecs_0_0_0_ce0), + .weight_vecs_0_0_0_q0(weight_vecs_0_0_0_t_q0), + .products_0_address0(tdf3_dot_product_U0_products_0_address0), + .products_0_ce0(tdf3_dot_product_U0_products_0_ce0), + .products_0_we0(tdf3_dot_product_U0_products_0_we0), + .products_0_d0(tdf3_dot_product_U0_products_0_d0) +); + +td_fused_top_tdf3_accum_1 tdf3_accum_1_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf3_accum_1_U0_ap_start), + .ap_done(tdf3_accum_1_U0_ap_done), + .ap_continue(tdf3_accum_1_U0_ap_continue), + .ap_idle(tdf3_accum_1_U0_ap_idle), + .ap_ready(tdf3_accum_1_U0_ap_ready), + .accum_in_0_address0(tdf3_accum_1_U0_accum_in_0_address0), + .accum_in_0_ce0(tdf3_accum_1_U0_accum_in_0_ce0), + .accum_in_0_q0(products_0_t_q0), + .accum_in_0_address1(tdf3_accum_1_U0_accum_in_0_address1), + .accum_in_0_ce1(tdf3_accum_1_U0_accum_in_0_ce1), + .accum_in_0_q1(products_0_t_q1), + .accum_out_address0(tdf3_accum_1_U0_accum_out_address0), + .accum_out_ce0(tdf3_accum_1_U0_accum_out_ce0), + .accum_out_we0(tdf3_accum_1_U0_accum_out_we0), + .accum_out_d0(tdf3_accum_1_U0_accum_out_d0), + .accum_out_address1(tdf3_accum_1_U0_accum_out_address1), + .accum_out_ce1(tdf3_accum_1_U0_accum_out_ce1), + .accum_out_we1(tdf3_accum_1_U0_accum_out_we1), + .accum_out_d1(tdf3_accum_1_U0_accum_out_d1) +); + +td_fused_top_tdf3_accum_2 tdf3_accum_2_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf3_accum_2_U0_ap_start), + .ap_done(tdf3_accum_2_U0_ap_done), + .ap_continue(tdf3_accum_2_U0_ap_continue), + .ap_idle(tdf3_accum_2_U0_ap_idle), + .ap_ready(tdf3_accum_2_U0_ap_ready), + .accum_in_14(tdf3_accum_2_U0_accum_in_14), + .accum_in_14_ap_vld(tdf3_accum_2_U0_accum_in_14_ap_vld), + .accum_in_address0(tdf3_accum_2_U0_accum_in_address0), + .accum_in_ce0(tdf3_accum_2_U0_accum_in_ce0), + .accum_in_q0(accum1_out_0_t_q0) +); + +td_fused_top_Block_entry_proc_proc505 Block_entry_proc_proc505_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(Block_entry_proc_proc505_U0_ap_start), + .ap_done(Block_entry_proc_proc505_U0_ap_done), + .ap_continue(Block_entry_proc_proc505_U0_ap_continue), + .ap_idle(Block_entry_proc_proc505_U0_ap_idle), + .ap_ready(Block_entry_proc_proc505_U0_ap_ready), + .tmp(tmp_channel_dout), + .ap_return(Block_entry_proc_proc505_U0_ap_return) +); + +td_fused_top_tdf3_writeOutputs_unaligned tdf3_writeOutputs_unaligned_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf3_writeOutputs_unaligned_U0_ap_start), + .ap_done(tdf3_writeOutputs_unaligned_U0_ap_done), + .ap_continue(tdf3_writeOutputs_unaligned_U0_ap_continue), + .ap_idle(tdf3_writeOutputs_unaligned_U0_ap_idle), + .ap_ready(tdf3_writeOutputs_unaligned_U0_ap_ready), + .indices_01_dout(indices_01_c1_dout), + .indices_01_empty_n(indices_01_c1_empty_n), + .indices_01_read(tdf3_writeOutputs_unaligned_U0_indices_01_read), + .indices_12_dout(indices_12_c2_dout), + .indices_12_empty_n(indices_12_c2_empty_n), + .indices_12_read(tdf3_writeOutputs_unaligned_U0_indices_12_read), + .p_read(outputs_0_dout), + .out_data_address0(tdf3_writeOutputs_unaligned_U0_out_data_address0), + .out_data_ce0(tdf3_writeOutputs_unaligned_U0_out_data_ce0), + .out_data_q0(out_data_q0), + .out_data_address1(tdf3_writeOutputs_unaligned_U0_out_data_address1), + .out_data_ce1(tdf3_writeOutputs_unaligned_U0_out_data_ce1), + .out_data_we1(tdf3_writeOutputs_unaligned_U0_out_data_we1), + .out_data_d1(tdf3_writeOutputs_unaligned_U0_out_data_d1) +); + +td_fused_top_fifo_w16_d2_S_x0 indices_01_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(tdf3_get_next_ijk_U0_indices_0_din), + .if_full_n(indices_01_c_full_n), + .if_write(tdf3_get_next_ijk_U0_indices_0_write), + .if_dout(indices_01_c_dout), + .if_empty_n(indices_01_c_empty_n), + .if_read(tdf3_readInputs_U0_indices_01_read) +); + +td_fused_top_fifo_w16_d2_S_x0 indices_12_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(tdf3_get_next_ijk_U0_indices_1_din), + .if_full_n(indices_12_c_full_n), + .if_write(tdf3_get_next_ijk_U0_indices_1_write), + .if_dout(indices_12_c_dout), + .if_empty_n(indices_12_c_empty_n), + .if_read(tdf3_readInputs_U0_indices_12_read) +); + +td_fused_top_fifo_w4_d2_S_x indices_2_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(tdf3_get_next_ijk_U0_ap_return), + .if_full_n(indices_2_full_n), + .if_write(tdf3_get_next_ijk_U0_ap_done), + .if_dout(indices_2_dout), + .if_empty_n(indices_2_empty_n), + .if_read(tdf3_readFilters30_U0_ap_ready) +); + +td_fused_top_fifo_w6_d6_S indices_01_c1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(tdf3_readInputs_U0_indices_01_out_din), + .if_full_n(indices_01_c1_full_n), + .if_write(tdf3_readInputs_U0_indices_01_out_write), + .if_dout(indices_01_c1_dout), + .if_empty_n(indices_01_c1_empty_n), + .if_read(tdf3_writeOutputs_unaligned_U0_indices_01_read) +); + +td_fused_top_fifo_w12_d6_S indices_12_c2_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(tdf3_readInputs_U0_indices_12_out_din), + .if_full_n(indices_12_c2_full_n), + .if_write(tdf3_readInputs_U0_indices_12_out_write), + .if_dout(indices_12_c2_dout), + .if_empty_n(indices_12_c2_empty_n), + .if_read(tdf3_writeOutputs_unaligned_U0_indices_12_read) +); + +td_fused_top_fifo_w16_d2_S_x0 tmp_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(tdf3_accum_2_U0_accum_in_14), + .if_full_n(tmp_channel_full_n), + .if_write(tdf3_accum_2_U0_ap_done), + .if_dout(tmp_channel_dout), + .if_empty_n(tmp_channel_empty_n), + .if_read(Block_entry_proc_proc505_U0_ap_ready) +); + +td_fused_top_fifo_w16_d2_S_x0 outputs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(Block_entry_proc_proc505_U0_ap_return), + .if_full_n(outputs_0_full_n), + .if_write(Block_entry_proc_proc505_U0_ap_done), + .if_dout(outputs_0_dout), + .if_empty_n(outputs_0_empty_n), + .if_read(tdf3_writeOutputs_unaligned_U0_ap_ready) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf3_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf3_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf3_get_next_ijk_U0_ap_ready <= ap_sync_tdf3_get_next_ijk_U0_ap_ready; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf3_readInputs_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf3_readInputs_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf3_readInputs_U0_ap_ready <= ap_sync_tdf3_readInputs_U0_ap_ready; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf3_writeOutputs_unaligned_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf3_writeOutputs_unaligned_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf3_writeOutputs_unaligned_U0_ap_ready <= ap_sync_tdf3_writeOutputs_unaligned_U0_ap_ready; + end + end +end + +assign Block_entry_proc_proc505_U0_ap_continue = outputs_0_full_n; + +assign Block_entry_proc_proc505_U0_ap_start = tmp_channel_empty_n; + +assign Block_entry_proc_proc505_U0_start_full_n = 1'b1; + +assign Block_entry_proc_proc505_U0_start_write = 1'b0; + +assign ap_channel_done_accum1_out_0 = tdf3_accum_1_U0_ap_done; + +assign ap_channel_done_ifmap_vec_0_0 = tdf3_readInputs_U0_ap_done; + +assign ap_channel_done_indices_2 = tdf3_get_next_ijk_U0_ap_done; + +assign ap_channel_done_outputs_0 = Block_entry_proc_proc505_U0_ap_done; + +assign ap_channel_done_products_0 = tdf3_dot_product_U0_ap_done; + +assign ap_channel_done_tmp_channel = tdf3_accum_2_U0_ap_done; + +assign ap_channel_done_weight_vecs_0_0_0 = tdf3_readFilters30_U0_ap_done; + +assign ap_done = tdf3_writeOutputs_unaligned_U0_ap_done; + +assign ap_idle = (tdf3_writeOutputs_unaligned_U0_ap_idle & tdf3_readInputs_U0_ap_idle & tdf3_readFilters30_U0_ap_idle & tdf3_get_next_ijk_U0_ap_idle & tdf3_dot_product_U0_ap_idle & tdf3_accum_2_U0_ap_idle & tdf3_accum_1_U0_ap_idle & (outputs_0_empty_n ^ 1'b1) & (tmp_channel_empty_n ^ 1'b1) & (indices_2_empty_n ^ 1'b1) & (products_0_t_empty_n ^ 1'b1) & (weight_vecs_0_0_0_t_empty_n ^ 1'b1) & (ifmap_vec_0_0_t_empty_n ^ 1'b1) & (1'b1 ^ accum1_out_0_t_empty_n) & Block_entry_proc_proc505_U0_ap_idle); + +assign ap_ready = ap_sync_ready; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = tdf3_writeOutputs_unaligned_U0_ap_done; + +assign ap_sync_ready = (ap_sync_tdf3_writeOutputs_unaligned_U0_ap_ready & ap_sync_tdf3_readInputs_U0_ap_ready & ap_sync_tdf3_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf3_get_next_ijk_U0_ap_ready = (tdf3_get_next_ijk_U0_ap_ready | ap_sync_reg_tdf3_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf3_readInputs_U0_ap_ready = (tdf3_readInputs_U0_ap_ready | ap_sync_reg_tdf3_readInputs_U0_ap_ready); + +assign ap_sync_tdf3_writeOutputs_unaligned_U0_ap_ready = (tdf3_writeOutputs_unaligned_U0_ap_ready | ap_sync_reg_tdf3_writeOutputs_unaligned_U0_ap_ready); + +assign filter_data_address0 = tdf3_readFilters30_U0_filter_data_address0; + +assign filter_data_address1 = 9'd0; + +assign filter_data_ce0 = tdf3_readFilters30_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = tdf3_readInputs_U0_in_data_address0; + +assign in_data_address1 = 15'd0; + +assign in_data_ce0 = tdf3_readInputs_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = tdf3_readInputs_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = tdf3_writeOutputs_unaligned_U0_out_data_address0; + +assign out_data_address1 = tdf3_writeOutputs_unaligned_U0_out_data_address1; + +assign out_data_ce0 = tdf3_writeOutputs_unaligned_U0_out_data_ce0; + +assign out_data_ce1 = tdf3_writeOutputs_unaligned_U0_out_data_ce1; + +assign out_data_d0 = 256'd0; + +assign out_data_d1 = tdf3_writeOutputs_unaligned_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = tdf3_writeOutputs_unaligned_U0_out_data_we1; + +assign out_data_write = tdf3_writeOutputs_unaligned_U0_out_data_write; + +assign products_0_t_d1 = 16'd0; + +assign products_0_t_we1 = 1'b0; + +assign tdf3_accum_1_U0_accum_out_full_n = accum1_out_0_i_full_n; + +assign tdf3_accum_1_U0_ap_continue = accum1_out_0_i_full_n; + +assign tdf3_accum_1_U0_ap_start = products_0_t_empty_n; + +assign tdf3_accum_1_U0_start_full_n = 1'b1; + +assign tdf3_accum_1_U0_start_write = 1'b0; + +assign tdf3_accum_2_U0_ap_continue = tmp_channel_full_n; + +assign tdf3_accum_2_U0_ap_start = accum1_out_0_t_empty_n; + +assign tdf3_accum_2_U0_start_full_n = 1'b1; + +assign tdf3_accum_2_U0_start_write = 1'b0; + +assign tdf3_dot_product_U0_ap_continue = products_0_i_full_n; + +assign tdf3_dot_product_U0_ap_start = (weight_vecs_0_0_0_t_empty_n & ifmap_vec_0_0_t_empty_n); + +assign tdf3_dot_product_U0_products_0_full_n = products_0_i_full_n; + +assign tdf3_dot_product_U0_start_full_n = 1'b1; + +assign tdf3_dot_product_U0_start_write = 1'b0; + +assign tdf3_get_next_ijk_U0_ap_continue = indices_2_full_n; + +assign tdf3_get_next_ijk_U0_ap_start = ((ap_sync_reg_tdf3_get_next_ijk_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf3_get_next_ijk_U0_start_full_n = 1'b1; + +assign tdf3_get_next_ijk_U0_start_write = 1'b0; + +assign tdf3_readFilters30_U0_ap_continue = weight_vecs_0_0_0_i_full_n; + +assign tdf3_readFilters30_U0_ap_start = indices_2_empty_n; + +assign tdf3_readFilters30_U0_start_full_n = 1'b1; + +assign tdf3_readFilters30_U0_start_write = 1'b0; + +assign tdf3_readFilters30_U0_weight_vecs_0_0_0_full_n = weight_vecs_0_0_0_i_full_n; + +assign tdf3_readInputs_U0_ap_continue = ifmap_vec_0_0_i_full_n; + +assign tdf3_readInputs_U0_ap_start = ((ap_sync_reg_tdf3_readInputs_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf3_readInputs_U0_ifmap_vec_0_0_full_n = ifmap_vec_0_0_i_full_n; + +assign tdf3_readInputs_U0_in_data_full_n = in_data_empty_n; + +assign tdf3_readInputs_U0_in_data_write = 1'b0; + +assign tdf3_readInputs_U0_start_full_n = 1'b1; + +assign tdf3_readInputs_U0_start_write = 1'b0; + +assign tdf3_writeOutputs_unaligned_U0_ap_continue = ap_continue; + +assign tdf3_writeOutputs_unaligned_U0_ap_start = (outputs_0_empty_n & (ap_sync_reg_tdf3_writeOutputs_unaligned_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf3_writeOutputs_unaligned_U0_out_data_full_n = out_data_full_n; + +assign tdf3_writeOutputs_unaligned_U0_out_data_write = 1'b0; + +assign tdf3_writeOutputs_unaligned_U0_start_full_n = 1'b1; + +assign tdf3_writeOutputs_unaligned_U0_start_write = 1'b0; + +endmodule //td_fused_top_dataflow_in_loop_TOP_LOOP49028 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +/*`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP49028_weight_vecs_0_0_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 6; +parameter MEM_SIZE = 64; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule +*/ + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP49028_weight_vecs_0_0_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd64; +parameter AddressWidth = 32'd6; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +/*td_fused_top_dataflow_in_loop_TOP_LOOP49028_weight_vecs_0_0_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP49028_weight_vecs_0_0_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ));*/ + +wire wren0, wren1; +assign wren0 = we0 & ce0; +assign wren1 = we1 & ce1; +dpram +#(.AWIDTH(AddressWidth), + .NUM_WORDS(AddressRange), + .DWIDTH(DataWidth)) +td_fused_top_dataflow_in_loop_TOP_LOOP49028_weight_vecs_0_0_0_memcore_ram_U ( + .clk(clk), + .address_a(address0), + .address_b(address1), + .wren_a(wren0), + .wren_b(wren1), + .data_a(d0), + .data_b(d1), + .out_a(q0), + .out_b(q1) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP49028_weight_vecs_0_0_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 5, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP49028_weight_vecs_0_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP49028_weight_vecs_0_0_0_memcore_U ( + .clk ( clk ), + .reset ( reset ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .address0 ( memcore_iaddr ), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .address1 ( memcore_taddr ), + .d1 ( t_d0 ), + .q1 ( t_q0 ) +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w12_d6_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd12; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd6; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output [DATA_WIDTH-1:0] q; +reg [DATA_WIDTH-1:0] q_tmp; + +reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_5 <= sr_4; + sr_4 <= sr_3; + sr_3 <= sr_2; + sr_2 <= sr_1; + sr_1 <= sr_0; + sr_0 <= data; + end + end + +//assign q = SRL_SIG[a]; +always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, a) begin + case (a) + 3'd0: q_tmp = sr_0; + 3'd1: q_tmp = sr_1; + 3'd2: q_tmp = sr_2; + 3'd3: q_tmp = sr_3; + 3'd4: q_tmp = sr_4; + 3'd5: q_tmp = sr_5; + default: q_tmp = sr_5; + endcase +end + +assign q = q_tmp; + +endmodule + +module td_fused_top_fifo_w12_d6_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd12; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd6; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w12_d6_S_shiftReg +//#( +// .DATA_WIDTH(DATA_WIDTH), +// .ADDR_WIDTH(ADDR_WIDTH), +// .DEPTH(DEPTH)) +U_td_fused_top_fifo_w12_d6_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q)); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w16_d2_S_x0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output [DATA_WIDTH-1:0] q; + +reg [DATA_WIDTH-1:0] q_tmp; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_1 <= sr_0; + sr_0 <= data; + end + end + +always @(sr_0, sr_1, a) begin + case (a) + 1'b0: q_tmp = sr_0; + 1'b1: q_tmp = sr_1; + default: q_tmp = sr_1; + endcase +end + +assign q = q_tmp; + +endmodule + +module td_fused_top_fifo_w16_d2_S_x0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w16_d2_S_x0_shiftReg +//#( +// .DATA_WIDTH(DATA_WIDTH), +// .ADDR_WIDTH(ADDR_WIDTH), +// .DEPTH(DEPTH)) +U_td_fused_top_fifo_w16_d2_S_x0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q)); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w4_d2_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output [DATA_WIDTH-1:0] q; +reg [DATA_WIDTH-1:0] q_tmp; + +reg [DATA_WIDTH-1:0] sr_0, sr_1; + +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_1 <= sr_0; + sr_0 <= data; + end + end + +always @(sr_0, sr_1, a) begin + case (a) + 1'b0: q_tmp = sr_0; + 1'b1: q_tmp = sr_1; + default: q_tmp = sr_1; + endcase +end + +assign q = q_tmp; + +endmodule + +module td_fused_top_fifo_w4_d2_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w4_d2_S_x_shiftReg +//#( +// .DATA_WIDTH(DATA_WIDTH), +// .ADDR_WIDTH(ADDR_WIDTH), +// .DEPTH(DEPTH)) +U_td_fused_top_fifo_w4_d2_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q)); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w6_d6_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd6; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd6; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output [DATA_WIDTH-1:0] q; +reg [DATA_WIDTH-1:0] q_tmp; + +//reg[DATA_WIDTH-1:0] SRL_SIG [DEPTH-1:0]; +reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_5 <= sr_4; + sr_4 <= sr_3; + sr_3 <= sr_2; + sr_2 <= sr_1; + sr_1 <= sr_0; + sr_0 <= data; + end + end + +//assign q = SRL_SIG[a]; +always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, a) begin + case (a) + 3'd0: q_tmp = sr_0; + 3'd1: q_tmp = sr_1; + 3'd2: q_tmp = sr_2; + 3'd3: q_tmp = sr_3; + 3'd4: q_tmp = sr_4; + 3'd5: q_tmp = sr_5; + default: q_tmp = sr_5; + endcase +end + +assign q = q_tmp; + +endmodule + +module td_fused_top_fifo_w6_d6_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd6; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd6; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w6_d6_S_shiftReg +//#( +// .DATA_WIDTH(DATA_WIDTH), +// .ADDR_WIDTH(ADDR_WIDTH), +// .DEPTH(DEPTH)) +U_td_fused_top_fifo_w6_d6_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q)); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_ap_hadd_0_full_dsp_16 ( + input wire s_axis_a_tvalid, + input wire [15:0] s_axis_a_tdata, + input wire s_axis_b_tvalid, + input wire [15:0] s_axis_b_tdata, + output wire m_axis_result_tvalid, + output wire [15:0] m_axis_result_tdata +); + + +`ifdef complex_dsp + addition_fp_16 u_add_fp ( + .a(s_axis_a_tdata), + .b(s_axis_b_tdata), + .out(m_axis_result_tdata) + ); +`else +FPAddSub u_FPAddSub (.clk(), .rst(1'b0), .a(s_axis_a_tdata), .b(s_axis_b_tdata), .operation(1'b0), .result(m_axis_result_tdata), .flags()); +`endif + +endmodule + +module td_fused_top_hadd_16ns_16ns_16_2_full_dsp_1 +#(parameter + ID = 45, + NUM_STAGE = 2, + din0_WIDTH = 16, + din1_WIDTH = 16, + dout_WIDTH = 16 +)( + input wire clk, + input wire reset, + input wire ce, + input wire [din0_WIDTH-1:0] din0, + input wire [din1_WIDTH-1:0] din1, + output wire [dout_WIDTH-1:0] dout +); +//------------------------Local signal------------------- +wire a_tvalid; +wire [15:0] a_tdata; +wire b_tvalid; +wire [15:0] b_tdata; +wire r_tvalid; +wire [15:0] r_tdata; +reg [din0_WIDTH-1:0] din0_buf1; +reg [din1_WIDTH-1:0] din1_buf1; +reg ce_r; +wire [dout_WIDTH-1:0] dout_i; +reg [dout_WIDTH-1:0] dout_r; +//------------------------Instantiation------------------ +td_fused_top_ap_hadd_0_full_dsp_16 td_fused_top_ap_hadd_0_full_dsp_16_u ( + .s_axis_a_tvalid ( a_tvalid ), + .s_axis_a_tdata ( a_tdata ), + .s_axis_b_tvalid ( b_tvalid ), + .s_axis_b_tdata ( b_tdata ), + .m_axis_result_tvalid ( r_tvalid ), + .m_axis_result_tdata ( r_tdata ) +); +//------------------------Body--------------------------- +assign a_tvalid = 1'b1; +assign a_tdata = din0_buf1; +assign b_tvalid = 1'b1; +assign b_tdata = din1_buf1; +assign dout_i = r_tdata; + +always @(posedge clk) begin + if (ce) begin + din0_buf1 <= din0; + din1_buf1 <= din1; + end +end + +always @ (posedge clk) begin + ce_r <= ce; +end + +always @ (posedge clk) begin + if (ce_r) begin + dout_r <= dout_i; + end +end + +assign dout = ce_r?dout_i:dout_r; +endmodule +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_ap_hmul_0_max_dsp_16 ( + input wire s_axis_a_tvalid, + input wire [15:0] s_axis_a_tdata, + input wire s_axis_b_tvalid, + input wire [15:0] s_axis_b_tdata, + output wire m_axis_result_tvalid, + output wire [15:0] m_axis_result_tdata +); + +`ifdef complex_dsp + mult_fp_16 u_mult_fp ( + .a(s_axis_a_tdata), + .b(s_axis_b_tdata), + .out(m_axis_result_tdata) + ); +`else +FPMult_16 u_FPMult (.clk(), .rst(1'b0), .a(s_axis_a_tdata), .b(s_axis_b_tdata), .result(m_axis_result_tdata), .flags()); +`endif + + +endmodule + + +module td_fused_top_hmul_16ns_16ns_16_2_max_dsp_1 +#(parameter + ID = 31, + NUM_STAGE = 2, + din0_WIDTH = 16, + din1_WIDTH = 16, + dout_WIDTH = 16 +)( + input wire clk, + input wire reset, + input wire ce, + input wire [din0_WIDTH-1:0] din0, + input wire [din1_WIDTH-1:0] din1, + output wire [dout_WIDTH-1:0] dout +); +//------------------------Local signal------------------- +wire a_tvalid; +wire [15:0] a_tdata; +wire b_tvalid; +wire [15:0] b_tdata; +wire r_tvalid; +wire [15:0] r_tdata; +reg [din0_WIDTH-1:0] din0_buf1; +reg [din1_WIDTH-1:0] din1_buf1; +reg ce_r; +wire [dout_WIDTH-1:0] dout_i; +reg [dout_WIDTH-1:0] dout_r; +//------------------------Instantiation------------------ +td_fused_top_ap_hmul_0_max_dsp_16 td_fused_top_ap_hmul_0_max_dsp_16_u ( + .s_axis_a_tvalid ( a_tvalid ), + .s_axis_a_tdata ( a_tdata ), + .s_axis_b_tvalid ( b_tvalid ), + .s_axis_b_tdata ( b_tdata ), + .m_axis_result_tvalid ( r_tvalid ), + .m_axis_result_tdata ( r_tdata ) +); +//------------------------Body--------------------------- +assign a_tvalid = 1'b1; +assign a_tdata = din0_buf1; +assign b_tvalid = 1'b1; +assign b_tdata = din1_buf1; +assign dout_i = r_tdata; + +always @(posedge clk) begin + if (ce) begin + din0_buf1 <= din0; + din1_buf1 <= din1; + end +end + +always @ (posedge clk) begin + ce_r <= ce; +end + +always @ (posedge clk) begin + if (ce_r) begin + dout_r <= dout_i; + end +end + +assign dout = ce_r?dout_i:dout_r; +endmodule +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 8'd1; +parameter ap_ST_fsm_pp0_stage0 = 8'd2; +parameter ap_ST_fsm_pp0_stage1 = 8'd4; +parameter ap_ST_fsm_pp0_stage2 = 8'd8; +parameter ap_ST_fsm_pp0_stage3 = 8'd16; +parameter ap_ST_fsm_state8 = 8'd32; +parameter ap_ST_fsm_state9 = 8'd64; +parameter ap_ST_fsm_state10 = 8'd128; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [4:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [4:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[4:0] accum_in_0_address0; +reg accum_in_0_ce0; +reg[4:0] accum_in_0_address1; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [7:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [5:0] x_reg_168; +reg [15:0] psum_7_08_reg_180; +reg [15:0] psum_6_07_reg_192; +reg [15:0] psum_5_06_reg_204; +reg [15:0] psum_4_05_reg_216; +reg [15:0] psum_3_04_reg_228; +reg [15:0] psum_2_03_reg_240; +reg [15:0] psum_1_02_reg_252; +reg [15:0] psum_0_01_reg_264; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state7_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +reg [0:0] tmp_reg_504; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_pp0_stage2_11001; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_pp0_stage3_11001; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter1; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state6_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +wire [0:0] tmp_fu_333_p3; +reg [0:0] tmp_reg_504_pp0_iter1_reg; +wire [4:0] trunc_ln25_fu_346_p1; +reg [4:0] trunc_ln25_reg_508; +wire [15:0] grp_fu_305_p2; +reg [15:0] psum_0_reg_538; +wire [15:0] grp_fu_311_p2; +reg [15:0] psum_1_reg_543; +wire [5:0] add_ln25_fu_401_p2; +reg [5:0] add_ln25_reg_558; +reg [15:0] psum_2_reg_563; +reg [15:0] psum_3_reg_568; +reg [15:0] psum_4_reg_583; +reg [15:0] psum_5_reg_588; +wire [3:0] add_ln33_fu_444_p2; +wire ap_CS_fsm_state9; +wire [0:0] tmp_80_fu_427_p3; +reg ap_block_state1; +wire ap_block_pp0_stage1_subdone; +reg ap_condition_pp0_exit_iter0_state3; +wire ap_block_pp0_stage3_subdone; +reg [5:0] ap_phi_mux_x_phi_fu_172_p4; +wire ap_block_pp0_stage0; +wire ap_block_pp0_stage1; +reg [3:0] q_reg_276; +wire ap_CS_fsm_state8; +reg [15:0] ap_phi_mux_phi_ln45_phi_fu_290_p8; +wire [2:0] trunc_ln33_fu_440_p1; +wire [63:0] zext_ln25_fu_341_p1; +wire [63:0] zext_ln29_fu_356_p1; +wire [63:0] zext_ln29_13_fu_366_p1; +wire [63:0] zext_ln29_14_fu_376_p1; +wire [63:0] zext_ln29_15_fu_386_p1; +wire ap_block_pp0_stage2; +wire [63:0] zext_ln29_16_fu_396_p1; +wire [63:0] zext_ln29_17_fu_412_p1; +wire ap_block_pp0_stage3; +wire [63:0] zext_ln29_18_fu_422_p1; +wire [63:0] zext_ln33_fu_435_p1; +wire [63:0] zext_ln33_3_fu_456_p1; +reg [15:0] grp_fu_305_p0; +reg [15:0] grp_fu_311_p0; +wire [4:0] or_ln29_fu_350_p2; +wire [4:0] or_ln29_13_fu_361_p2; +wire [4:0] or_ln29_14_fu_371_p2; +wire [4:0] or_ln29_15_fu_381_p2; +wire [4:0] or_ln29_16_fu_391_p2; +wire [4:0] or_ln29_17_fu_407_p2; +wire [4:0] or_ln29_18_fu_417_p2; +wire [2:0] or_ln33_fu_450_p2; +wire [0:0] icmp_ln45_fu_461_p2; +wire [0:0] icmp_ln45_5_fu_475_p2; +wire [15:0] select_ln45_fu_467_p3; +wire [0:0] icmp_ln45_6_fu_489_p2; +wire [15:0] select_ln45_5_fu_481_p3; +wire ap_CS_fsm_state10; +reg [7:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +wire ap_block_pp0_stage2_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_467; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 8'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_2_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_2_full_dsp_1_U254( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_305_p0), + .din1(accum_in_0_q1), + .ce(1'b1), + .dout(grp_fu_305_p2) +); + +td_fused_top_hadd_16ns_16ns_16_2_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_2_full_dsp_1_U255( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_311_p0), + .din1(accum_in_0_q0), + .ce(1'b1), + .dout(grp_fu_311_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + q_reg_276 <= 4'd0; + end else if (((1'b1 == ap_CS_fsm_state9) & (tmp_80_fu_427_p3 == 1'd0))) begin + q_reg_276 <= add_ln33_fu_444_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_504 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + x_reg_168 <= add_ln25_reg_558; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_168 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_504 == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + add_ln25_reg_558 <= add_ln25_fu_401_p2; + psum_2_reg_563 <= grp_fu_305_p2; + psum_3_reg_568 <= grp_fu_311_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (tmp_reg_504_pp0_iter1_reg == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_0_01_reg_264 <= psum_0_reg_538; + psum_1_02_reg_252 <= psum_1_reg_543; + psum_2_03_reg_240 <= psum_2_reg_563; + psum_3_04_reg_228 <= psum_3_reg_568; + psum_4_05_reg_216 <= psum_4_reg_583; + psum_5_06_reg_204 <= psum_5_reg_588; + psum_6_07_reg_192 <= grp_fu_305_p2; + psum_7_08_reg_180 <= grp_fu_311_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_504 == 1'd0) & (1'b0 == ap_block_pp0_stage2_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + psum_0_reg_538 <= grp_fu_305_p2; + psum_1_reg_543 <= grp_fu_311_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_504 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_4_reg_583 <= grp_fu_305_p2; + psum_5_reg_588 <= grp_fu_311_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + tmp_reg_504 <= ap_phi_mux_x_phi_fu_172_p4[32'd5]; + tmp_reg_504_pp0_iter1_reg <= tmp_reg_504; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (tmp_fu_333_p3 == 1'd0))) begin + trunc_ln25_reg_508 <= trunc_ln25_fu_346_p1; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address0 = zext_ln29_18_fu_422_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address0 = zext_ln29_16_fu_396_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address0 = zext_ln29_14_fu_376_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address0 = zext_ln29_fu_356_p1; + end else begin + accum_in_0_address0 = 5'd0; + end + end else begin + accum_in_0_address0 = 5'd0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address1 = zext_ln29_17_fu_412_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address1 = zext_ln29_15_fu_386_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address1 = zext_ln29_13_fu_366_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address1 = zext_ln25_fu_341_p1; + end else begin + accum_in_0_address1 = 5'd0; + end + end else begin + accum_in_0_address1 = 5'd0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage2_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((1'b0 == ap_block_pp0_stage1_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage3_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage2_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((1'b0 == ap_block_pp0_stage1_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage3_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state9) & (tmp_80_fu_427_p3 == 1'd0))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state9) & (tmp_80_fu_427_p3 == 1'd0))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_reg_504 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state9) & (tmp_80_fu_427_p3 == 1'd0))) begin + if ((trunc_ln33_fu_440_p1 == 3'd0)) begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = psum_0_01_reg_264; + end else if ((1'b1 == ap_condition_467)) begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = psum_6_07_reg_192; + end else if ((trunc_ln33_fu_440_p1 == 3'd4)) begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = psum_4_05_reg_216; + end else if ((trunc_ln33_fu_440_p1 == 3'd2)) begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = psum_2_03_reg_240; + end else begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = 16'd0; + end + end else begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = 16'd0; + end +end + +always @ (*) begin + if (((tmp_reg_504 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_x_phi_fu_172_p4 = add_ln25_reg_558; + end else begin + ap_phi_mux_x_phi_fu_172_p4 = x_reg_168; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = psum_6_07_reg_192; + end else if (((1'b0 == ap_block_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p0 = psum_4_05_reg_216; + end else if (((1'b0 == ap_block_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p0 = psum_2_03_reg_240; + end else if (((1'b0 == ap_block_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + grp_fu_305_p0 = psum_0_reg_538; + end else begin + grp_fu_305_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_311_p0 = psum_7_08_reg_180; + end else if (((1'b0 == ap_block_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_311_p0 = psum_5_06_reg_204; + end else if (((1'b0 == ap_block_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_311_p0 = psum_3_04_reg_228; + end else if (((1'b0 == ap_block_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + grp_fu_311_p0 = psum_1_reg_543; + end else begin + grp_fu_311_p0 = 16'd0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((tmp_reg_504 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((tmp_reg_504 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state8; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((1'b0 == ap_block_pp0_stage2_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + if (((1'b1 == ap_CS_fsm_state9) & (tmp_80_fu_427_p3 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state9; + end else begin + ap_NS_fsm = ap_ST_fsm_state10; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 8'b0; + end + endcase +end + +assign accum_out_address0 = zext_ln33_3_fu_456_p1; + +assign accum_out_address1 = zext_ln33_fu_435_p1; + +assign accum_out_d0 = ((icmp_ln45_6_fu_489_p2[0:0] == 1'b1) ? psum_5_06_reg_204 : select_ln45_5_fu_481_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln45_phi_fu_290_p8; + +assign add_ln25_fu_401_p2 = (x_reg_168 + 6'd8); + +assign add_ln33_fu_444_p2 = (q_reg_276 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd6]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_467 = (~(trunc_ln33_fu_440_p1 == 3'd0) & ~(trunc_ln33_fu_440_p1 == 3'd4) & ~(trunc_ln33_fu_440_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign icmp_ln45_5_fu_475_p2 = ((or_ln33_fu_450_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln45_6_fu_489_p2 = ((or_ln33_fu_450_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln45_fu_461_p2 = ((or_ln33_fu_450_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln29_13_fu_361_p2 = (trunc_ln25_reg_508 | 5'd2); + +assign or_ln29_14_fu_371_p2 = (trunc_ln25_reg_508 | 5'd3); + +assign or_ln29_15_fu_381_p2 = (trunc_ln25_reg_508 | 5'd4); + +assign or_ln29_16_fu_391_p2 = (trunc_ln25_reg_508 | 5'd5); + +assign or_ln29_17_fu_407_p2 = (trunc_ln25_reg_508 | 5'd6); + +assign or_ln29_18_fu_417_p2 = (trunc_ln25_reg_508 | 5'd7); + +assign or_ln29_fu_350_p2 = (trunc_ln25_fu_346_p1 | 5'd1); + +assign or_ln33_fu_450_p2 = (trunc_ln33_fu_440_p1 | 3'd1); + +assign select_ln45_5_fu_481_p3 = ((icmp_ln45_5_fu_475_p2[0:0] == 1'b1) ? psum_3_04_reg_228 : select_ln45_fu_467_p3); + +assign select_ln45_fu_467_p3 = ((icmp_ln45_fu_461_p2[0:0] == 1'b1) ? psum_1_02_reg_252 : psum_7_08_reg_180); + +assign tmp_80_fu_427_p3 = q_reg_276[32'd3]; + +assign tmp_fu_333_p3 = ap_phi_mux_x_phi_fu_172_p4[32'd5]; + +assign trunc_ln25_fu_346_p1 = ap_phi_mux_x_phi_fu_172_p4[4:0]; + +assign trunc_ln33_fu_440_p1 = q_reg_276[2:0]; + +assign zext_ln25_fu_341_p1 = ap_phi_mux_x_phi_fu_172_p4; + +assign zext_ln29_13_fu_366_p1 = or_ln29_13_fu_361_p2; + +assign zext_ln29_14_fu_376_p1 = or_ln29_14_fu_371_p2; + +assign zext_ln29_15_fu_386_p1 = or_ln29_15_fu_381_p2; + +assign zext_ln29_16_fu_396_p1 = or_ln29_16_fu_391_p2; + +assign zext_ln29_17_fu_412_p1 = or_ln29_17_fu_407_p2; + +assign zext_ln29_18_fu_422_p1 = or_ln29_18_fu_417_p2; + +assign zext_ln29_fu_356_p1 = or_ln29_fu_350_p2; + +assign zext_ln33_3_fu_456_p1 = or_ln33_fu_450_p2; + +assign zext_ln33_fu_435_p1 = q_reg_276; + +endmodule //td_fused_top_tdf3_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_14, + accum_in_14_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_state3 = 4'd4; +parameter ap_ST_fsm_state4 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_14; +output accum_in_14_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_14; +reg accum_in_14_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln57_fu_74_p2; +reg [3:0] add_ln57_reg_91; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln57_fu_85_p2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state4; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln57_fu_80_p1; +reg [15:0] accum_in_14_preg; +reg [3:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 accum_in_14_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_2_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_2_full_dsp_1_U258( + .clk(ap_clk), + .reset(ap_rst), + .din0(sum_01_reg_55), + .din1(accum_in_q0), + .ce(1'b1), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_14_preg <= 16'd0; + end else begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_14_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state4)) begin + i_1_1_reg_44 <= add_ln57_reg_91; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state4)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln57_reg_91 <= add_ln57_fu_74_p2; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_14 = sum_01_reg_55; + end else begin + accum_in_14 = accum_in_14_preg; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_14_ap_vld = 1'b1; + end else begin + accum_in_14_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 4'd0; + end + endcase +end + +assign accum_in_address0 = zext_ln57_fu_80_p1; + +assign add_ln57_fu_74_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign icmp_ln57_fu_85_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln57_fu_80_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf3_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_q0, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state5 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [4:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +input [15:0] ifmap_vec_0_0_q0; +output [4:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +input [15:0] weight_vecs_0_0_0_q0; +output [4:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_0_0_ce0; +reg weight_vecs_0_0_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [5:0] ic_0_0_reg_69; +wire [5:0] add_ln148_fu_87_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln148_fu_93_p2; +reg [0:0] icmp_ln148_reg_118; +reg [0:0] icmp_ln148_reg_118_pp0_iter1_reg; +wire [4:0] trunc_ln149_fu_105_p1; +reg [4:0] trunc_ln149_reg_122; +reg [4:0] trunc_ln149_reg_122_pp0_iter1_reg; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +wire [63:0] zext_ln148_fu_99_p1; +wire ap_block_pp0_stage0; +wire [63:0] idxprom30_0_0_fu_109_p1; +wire [15:0] grp_fu_80_p2; +wire ap_CS_fsm_state5; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_2_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_2_max_dsp_1_U250( + .clk(ap_clk), + .reset(ap_rst), + .din0(ifmap_vec_0_0_q0), + .din1(weight_vecs_0_0_0_q0), + .ce(1'b1), + .dout(grp_fu_80_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state5)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_0_0_reg_69 <= 6'd0; + end else if (((icmp_ln148_fu_93_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_0_0_reg_69 <= add_ln148_fu_87_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln148_reg_118 <= icmp_ln148_fu_93_p2; + icmp_ln148_reg_118_pp0_iter1_reg <= icmp_ln148_reg_118; + trunc_ln149_reg_122_pp0_iter1_reg <= trunc_ln149_reg_122; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln148_fu_93_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln149_reg_122 <= trunc_ln149_fu_105_p1; + end +end + +always @ (*) begin + if ((icmp_ln148_fu_93_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state5)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state5)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln148_reg_118_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln148_fu_93_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln148_fu_93_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state5; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 3'd0; + end + endcase +end + +assign add_ln148_fu_87_p2 = (ic_0_0_reg_69 + 6'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state5 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign icmp_ln148_fu_93_p2 = ((ic_0_0_reg_69 == 6'd32) ? 1'b1 : 1'b0); + +assign idxprom30_0_0_fu_109_p1 = trunc_ln149_reg_122_pp0_iter1_reg; + +assign ifmap_vec_0_0_address0 = zext_ln148_fu_99_p1; + +assign products_0_address0 = idxprom30_0_0_fu_109_p1; + +assign products_0_d0 = grp_fu_80_p2; + +assign trunc_ln149_fu_105_p1 = ic_0_0_reg_69[4:0]; + +assign weight_vecs_0_0_0_address0 = zext_ln148_fu_99_p1; + +assign zext_ln148_fu_99_p1 = ic_0_0_reg_69; + +endmodule //td_fused_top_tdf3_dot_product +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [3:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_0_write; +reg indices_1_write; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] i_2; +reg [15:0] j_2; +reg [15:0] k_2; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg [0:0] ap_phi_mux_j_14_flag_0_i_phi_fu_55_p6; +reg ap_block_state1; +wire [0:0] icmp_ln78_fu_117_p2; +wire [0:0] icmp_ln81_fu_130_p2; +reg [15:0] ap_phi_mux_j_14_new_0_i_phi_fu_69_p6; +wire [15:0] add_ln80_fu_123_p2; +reg [15:0] ap_phi_mux_k_14_new_0_i_phi_fu_82_p6; +wire [15:0] add_ln77_fu_110_p2; +wire [15:0] select_ln84_fu_148_p3; +wire [15:0] add_ln83_fu_136_p2; +wire [0:0] icmp_ln84_fu_142_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_2 = 16'd0; +#0 j_2 = 16'd0; +#0 k_2 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln81_fu_130_p2 == 1'd1) & (icmp_ln78_fu_117_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_2 <= select_ln84_fu_148_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_14_flag_0_i_phi_fu_55_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j_2 <= ap_phi_mux_j_14_new_0_i_phi_fu_69_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k_2 <= ap_phi_mux_k_14_new_0_i_phi_fu_82_p6; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_117_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_14_flag_0_i_phi_fu_55_p6 = 1'd0; + end else if ((((icmp_ln81_fu_130_p2 == 1'd0) & (icmp_ln78_fu_117_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln81_fu_130_p2 == 1'd1) & (icmp_ln78_fu_117_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_14_flag_0_i_phi_fu_55_p6 = 1'd1; + end else begin + ap_phi_mux_j_14_flag_0_i_phi_fu_55_p6 = 16'd0; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_117_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln81_fu_130_p2 == 1'd0)) begin + ap_phi_mux_j_14_new_0_i_phi_fu_69_p6 = add_ln80_fu_123_p2; + end else if ((icmp_ln81_fu_130_p2 == 1'd1)) begin + ap_phi_mux_j_14_new_0_i_phi_fu_69_p6 = 16'd0; + end else begin + ap_phi_mux_j_14_new_0_i_phi_fu_69_p6 = 16'd0; + end + end else begin + ap_phi_mux_j_14_new_0_i_phi_fu_69_p6 = 16'd0; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_117_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_14_new_0_i_phi_fu_82_p6 = add_ln77_fu_110_p2; + end else if ((((icmp_ln81_fu_130_p2 == 1'd0) & (icmp_ln78_fu_117_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln81_fu_130_p2 == 1'd1) & (icmp_ln78_fu_117_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_14_new_0_i_phi_fu_82_p6 = 16'd0; + end else begin + ap_phi_mux_k_14_new_0_i_phi_fu_82_p6 = 16'd0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 1'b0; + end + endcase +end + +assign add_ln77_fu_110_p2 = (k_2 + 16'd1); + +assign add_ln80_fu_123_p2 = (j_2 + 16'd1); + +assign add_ln83_fu_136_p2 = (i_2 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_return = k_2[3:0]; + +assign icmp_ln78_fu_117_p2 = ((add_ln77_fu_110_p2 == 16'd16) ? 1'b1 : 1'b0); + +assign icmp_ln81_fu_130_p2 = ((add_ln80_fu_123_p2 == 16'd56) ? 1'b1 : 1'b0); + +assign icmp_ln84_fu_142_p2 = ((add_ln83_fu_136_p2 == 16'd56) ? 1'b1 : 1'b0); + +assign indices_0_din = i_2; + +assign indices_1_din = j_2; + +assign select_ln84_fu_148_p3 = ((icmp_ln84_fu_142_p2[0:0] == 1'b1) ? 16'd0 : add_ln83_fu_136_p2); + +endmodule //td_fused_top_tdf3_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_readFilters30 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + k_21, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_we0, + weight_vecs_0_0_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state4 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [8:0] filter_data_address0; +output filter_data_ce0; +input [15:0] filter_data_q0; +input [3:0] k_21; +output [4:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +output weight_vecs_0_0_0_we0; +output [15:0] weight_vecs_0_0_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg weight_vecs_0_0_0_ce0; +reg weight_vecs_0_0_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [5:0] kk_0_0_i_reg_81; +wire [8:0] tmp_fu_93_p3; +reg [8:0] tmp_reg_132; +wire [5:0] add_ln48_fu_101_p2; +reg [5:0] add_ln48_reg_137; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln48_fu_107_p2; +reg [0:0] icmp_ln48_reg_142; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg [5:0] ap_phi_mux_kk_0_0_i_phi_fu_85_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln54_63_fu_122_p1; +wire [63:0] zext_ln48_fu_127_p1; +wire [8:0] zext_ln54_fu_113_p1; +wire [8:0] add_ln54_fu_117_p2; +wire ap_CS_fsm_state4; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state4)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln48_reg_142 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_0_0_i_reg_81 <= add_ln48_reg_137; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_0_0_i_reg_81 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln48_reg_137 <= add_ln48_fu_101_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln48_reg_142 <= icmp_ln48_fu_107_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + tmp_reg_132[8 : 5] <= tmp_fu_93_p3[8 : 5]; + end +end + +always @ (*) begin + if ((icmp_ln48_fu_107_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln48_reg_142 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_kk_0_0_i_phi_fu_85_p4 = add_ln48_reg_137; + end else begin + ap_phi_mux_kk_0_0_i_phi_fu_85_p4 = kk_0_0_i_reg_81; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln48_reg_142 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((icmp_ln48_fu_107_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((icmp_ln48_fu_107_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 3'd0; + end + endcase +end + +assign add_ln48_fu_101_p2 = (ap_phi_mux_kk_0_0_i_phi_fu_85_p4 + 6'd1); + +assign add_ln54_fu_117_p2 = (tmp_reg_132 + zext_ln54_fu_113_p1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_address0 = zext_ln54_63_fu_122_p1; + +assign icmp_ln48_fu_107_p2 = ((ap_phi_mux_kk_0_0_i_phi_fu_85_p4 == 6'd32) ? 1'b1 : 1'b0); + +assign tmp_fu_93_p3 = {{k_21}, {5'd0}}; + +assign weight_vecs_0_0_0_address0 = zext_ln48_fu_127_p1; + +assign weight_vecs_0_0_0_d0 = filter_data_q0; + +assign zext_ln48_fu_127_p1 = kk_0_0_i_reg_81; + +assign zext_ln54_63_fu_122_p1 = add_ln54_fu_117_p2; + +assign zext_ln54_fu_113_p1 = ap_phi_mux_kk_0_0_i_phi_fu_85_p4; + +always @ (posedge ap_clk) begin + tmp_reg_132[4:0] <= 5'b00000; +end + +endmodule //td_fused_top_tdf3_readFilters30 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_readInputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_we0, + ifmap_vec_0_0_d0, + ifmap_vec_0_0_address1, + ifmap_vec_0_0_ce1, + ifmap_vec_0_0_we1, + ifmap_vec_0_0_d1, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_pp0_stage0 = 4'd2; +parameter ap_ST_fsm_pp0_stage1 = 4'd4; +parameter ap_ST_fsm_state5 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [14:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [4:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +output ifmap_vec_0_0_we0; +output [15:0] ifmap_vec_0_0_d0; +output [4:0] ifmap_vec_0_0_address1; +output ifmap_vec_0_0_ce1; +output ifmap_vec_0_0_we1; +output [15:0] ifmap_vec_0_0_d1; +output [5:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [11:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg[4:0] ifmap_vec_0_0_address0; +reg ifmap_vec_0_0_ce0; +reg ifmap_vec_0_0_we0; +reg[15:0] ifmap_vec_0_0_d0; +reg[4:0] ifmap_vec_0_0_address1; +reg ifmap_vec_0_0_ce1; +reg ifmap_vec_0_0_we1; +reg[15:0] ifmap_vec_0_0_d1; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [5:0] kk_0_i_i_reg_178; +wire [0:0] is_padding_fu_216_p2; +reg [0:0] is_padding_reg_436; +wire [13:0] add_ln31_fu_276_p2; +reg [13:0] add_ln31_reg_444; +wire [0:0] icmp_ln24_fu_282_p2; +reg [0:0] icmp_ln24_reg_449; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state4_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +wire [5:0] add_ln24_fu_310_p2; +reg [5:0] add_ln24_reg_458; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_pp0_stage1_11001; +wire [4:0] empty_142_fu_321_p1; +reg [4:0] empty_142_reg_463; +wire [15:0] select_ln32_40_fu_388_p3; +reg [15:0] select_ln32_40_reg_469; +wire [15:0] select_ln32_41_fu_409_p3; +reg [15:0] select_ln32_41_reg_474; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +wire ap_block_pp0_stage1_subdone; +reg [5:0] ap_phi_mux_kk_0_i_i_phi_fu_182_p4; +wire ap_block_pp0_stage0; +wire [63:0] sext_ln31_fu_305_p1; +wire [63:0] kk_0_cast4_i_i_fu_316_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln31_9_fu_347_p1; +wire [63:0] zext_ln31_10_fu_421_p1; +wire [63:0] zext_ln31_11_fu_431_p1; +wire [5:0] trunc_ln131_fu_190_p1; +wire [15:0] select_ln32_fu_333_p3; +wire [15:0] select_ln32_39_fu_366_p3; +wire [0:0] cmp7_i_i_fu_204_p2; +wire [0:0] icmp_ln23_fu_210_p2; +wire [5:0] empty_140_fu_200_p1; +wire [5:0] row_coord_int_fu_222_p3; +wire [11:0] tmp_fu_238_p3; +wire [8:0] tmp_s_fu_250_p3; +wire [12:0] zext_ln31_fu_246_p1; +wire [12:0] zext_ln31_17_fu_258_p1; +wire [12:0] sub_ln31_fu_262_p2; +wire [5:0] col_coord_int_fu_230_p3; +wire [13:0] sub_ln31_cast_fu_268_p1; +wire [13:0] zext_ln31_18_fu_272_p1; +wire [2:0] lshr_ln_fu_288_p4; +wire [16:0] tmp_79_fu_298_p3; +wire [15:0] trunc_ln31_fu_325_p1; +wire [15:0] bitcast_ln31_fu_329_p1; +wire [4:0] or_ln24_fu_341_p2; +wire [15:0] tmp_285_i_i_fu_352_p4; +wire [15:0] bitcast_ln31_22_fu_362_p1; +wire [15:0] tmp_286_i_i_fu_374_p4; +wire [15:0] bitcast_ln31_23_fu_384_p1; +wire [15:0] tmp_287_i_i_fu_395_p4; +wire [15:0] bitcast_ln31_24_fu_405_p1; +wire [4:0] or_ln24_5_fu_416_p2; +wire [4:0] or_ln24_6_fu_426_p2; +wire ap_CS_fsm_state5; +reg [3:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state5)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((((ap_enable_reg_pp0_iter0 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln24_reg_449 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_i_i_reg_178 <= add_ln24_reg_458; + end else if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_0_i_i_reg_178 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln24_reg_449 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + add_ln24_reg_458 <= add_ln24_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + add_ln31_reg_444 <= add_ln31_fu_276_p2; + is_padding_reg_436 <= is_padding_fu_216_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln24_reg_449 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + empty_142_reg_463 <= empty_142_fu_321_p1; + select_ln32_40_reg_469 <= select_ln32_40_fu_388_p3; + select_ln32_41_reg_474 <= select_ln32_41_fu_409_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln24_reg_449 <= icmp_ln24_fu_282_p2; + end +end + +always @ (*) begin + if ((icmp_ln24_fu_282_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state5)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (icmp_ln24_reg_449 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_i_i_phi_fu_182_p4 = add_ln24_reg_458; + end else begin + ap_phi_mux_kk_0_i_i_phi_fu_182_p4 = kk_0_i_i_reg_178; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state5)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_address0 = zext_ln31_11_fu_431_p1; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_0_0_address0 = zext_ln31_9_fu_347_p1; + end else begin + ifmap_vec_0_0_address0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_address1 = zext_ln31_10_fu_421_p1; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_0_0_address1 = kk_0_cast4_i_i_fu_316_p1; + end else begin + ifmap_vec_0_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + ifmap_vec_0_0_ce1 = 1'b1; + end else begin + ifmap_vec_0_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_d0 = select_ln32_41_reg_474; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_0_0_d0 = select_ln32_39_fu_366_p3; + end else begin + ifmap_vec_0_0_d0 = 16'd0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_d1 = select_ln32_40_reg_469; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_0_0_d1 = select_ln32_fu_333_p3; + end else begin + ifmap_vec_0_0_d1 = 16'd0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln24_reg_449 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln24_reg_449 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + ifmap_vec_0_0_we0 = 1'b1; + end else begin + ifmap_vec_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln24_reg_449 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln24_reg_449 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + ifmap_vec_0_0_we1 = 1'b1; + end else begin + ifmap_vec_0_0_we1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln24_fu_282_p2 == 1'd1)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln24_fu_282_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state5; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 4'd0; + end + endcase +end + +assign add_ln24_fu_310_p2 = (kk_0_i_i_reg_178 + 6'd4); + +assign add_ln31_fu_276_p2 = ((sub_ln31_cast_fu_268_p1) + (zext_ln31_18_fu_272_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state5 = ap_CS_fsm[32'd3]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln31_22_fu_362_p1 = tmp_285_i_i_fu_352_p4; + +assign bitcast_ln31_23_fu_384_p1 = tmp_286_i_i_fu_374_p4; + +assign bitcast_ln31_24_fu_405_p1 = tmp_287_i_i_fu_395_p4; + +assign bitcast_ln31_fu_329_p1 = trunc_ln31_fu_325_p1; + +assign cmp7_i_i_fu_204_p2 = ((indices_01_dout > 16'd55) ? 1'b1 : 1'b0); + +assign col_coord_int_fu_230_p3 = ((is_padding_fu_216_p2[0:0] == 1'b1) ? 6'd0 : empty_140_fu_200_p1); + +assign empty_140_fu_200_p1 = indices_12_dout[5:0]; + +assign empty_142_fu_321_p1 = kk_0_i_i_reg_178[4:0]; + +assign icmp_ln23_fu_210_p2 = ((indices_12_dout > 16'd55) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_282_p2 = ((ap_phi_mux_kk_0_i_i_phi_fu_182_p4 == 6'd32) ? 1'b1 : 1'b0); + +assign in_data_address0 = sext_ln31_fu_305_p1; + +assign indices_01_out_din = trunc_ln131_fu_190_p1; + +assign indices_12_out_din = indices_12_dout[11:0]; + +assign is_padding_fu_216_p2 = (icmp_ln23_fu_210_p2 | cmp7_i_i_fu_204_p2); + +assign kk_0_cast4_i_i_fu_316_p1 = kk_0_i_i_reg_178; + +assign lshr_ln_fu_288_p4 = {{ap_phi_mux_kk_0_i_i_phi_fu_182_p4[4:2]}}; + +assign or_ln24_5_fu_416_p2 = (empty_142_reg_463 | 5'd2); + +assign or_ln24_6_fu_426_p2 = (empty_142_reg_463 | 5'd3); + +assign or_ln24_fu_341_p2 = (empty_142_fu_321_p1 | 5'd1); + +assign row_coord_int_fu_222_p3 = ((is_padding_fu_216_p2[0:0] == 1'b1) ? 6'd0 : trunc_ln131_fu_190_p1); + +assign select_ln32_39_fu_366_p3 = ((is_padding_reg_436[0:0] == 1'b1) ? 16'd0 : bitcast_ln31_22_fu_362_p1); + +assign select_ln32_40_fu_388_p3 = ((is_padding_reg_436[0:0] == 1'b1) ? 16'd0 : bitcast_ln31_23_fu_384_p1); + +assign select_ln32_41_fu_409_p3 = ((is_padding_reg_436[0:0] == 1'b1) ? 16'd0 : bitcast_ln31_24_fu_405_p1); + +assign select_ln32_fu_333_p3 = ((is_padding_reg_436[0:0] == 1'b1) ? 16'd0 : bitcast_ln31_fu_329_p1); + +assign sext_ln31_fu_305_p1 = (tmp_79_fu_298_p3); + +assign sub_ln31_cast_fu_268_p1 = (sub_ln31_fu_262_p2); + +assign sub_ln31_fu_262_p2 = (zext_ln31_fu_246_p1 - zext_ln31_17_fu_258_p1); + +assign tmp_285_i_i_fu_352_p4 = {{in_data_q0[31:16]}}; + +assign tmp_286_i_i_fu_374_p4 = {{in_data_q0[47:32]}}; + +assign tmp_287_i_i_fu_395_p4 = {{in_data_q0[63:48]}}; + +assign tmp_79_fu_298_p3 = {{add_ln31_reg_444}, {lshr_ln_fu_288_p4}}; + +assign tmp_fu_238_p3 = {{row_coord_int_fu_222_p3}, {6'd0}}; + +assign tmp_s_fu_250_p3 = {{row_coord_int_fu_222_p3}, {3'd0}}; + +assign trunc_ln131_fu_190_p1 = indices_01_dout[5:0]; + +assign trunc_ln31_fu_325_p1 = in_data_q0[15:0]; + +assign zext_ln31_10_fu_421_p1 = or_ln24_5_fu_416_p2; + +assign zext_ln31_11_fu_431_p1 = or_ln24_6_fu_426_p2; + +assign zext_ln31_17_fu_258_p1 = tmp_s_fu_250_p3; + +assign zext_ln31_18_fu_272_p1 = col_coord_int_fu_230_p3; + +assign zext_ln31_9_fu_347_p1 = or_ln24_fu_341_p2; + +assign zext_ln31_fu_246_p1 = tmp_fu_238_p3; + +endmodule //td_fused_top_tdf3_readInputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_writeOutputs_unaligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + p_read, + out_data_address0, + out_data_ce0, + out_data_q0, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 2'd1; +parameter ap_ST_fsm_state2 = 2'd2; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [5:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [11:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [15:0] p_read; +output [11:0] out_data_address0; +output out_data_ce0; +input [255:0] out_data_q0; +output [11:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [255:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg out_data_ce0; +reg out_data_ce1; +reg out_data_we1; + +reg ap_done_reg; + reg [1:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] outputCount_4; +reg [15:0] outputChanIdx_4; +reg [15:0] outputRow_8_0; +reg [15:0] outputRow_8_1; +reg [15:0] outputRow_8_2; +reg [15:0] outputRow_8_3; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg [11:0] out_data_addr_reg_903; +wire [15:0] add_ln86_fu_208_p2; +wire [0:0] icmp_ln87_fu_214_p2; +reg [0:0] icmp_ln87_reg_917; +reg [15:0] ap_phi_mux_empty_139_phi_fu_132_p4; +reg [15:0] empty_139_reg_129; +reg ap_block_state1; +wire ap_CS_fsm_state2; +wire [63:0] zext_ln93_59_fu_171_p1; +wire [15:0] select_ln96_fu_883_p3; +wire [1:0] trunc_ln85_fu_180_p1; +wire [8:0] tmp_s_fu_147_p3; +wire [11:0] tmp_fu_139_p3; +wire [11:0] zext_ln93_fu_155_p1; +wire [11:0] sub_ln93_fu_159_p2; +wire [11:0] add_ln93_fu_165_p2; +wire [1:0] trunc_ln93_fu_228_p1; +wire [7:0] shl_ln_fu_244_p3; +wire [7:0] empty_fu_252_p2; +wire [15:0] bitcast_ln93_fu_240_p1; +wire [8:0] zext_ln93_60_fu_264_p1; +wire [0:0] icmp_ln93_fu_258_p2; +wire [8:0] zext_ln93_61_fu_268_p1; +wire [8:0] xor_ln93_fu_276_p2; +wire [8:0] select_ln93_fu_282_p3; +wire [8:0] select_ln93_32_fu_298_p3; +wire [8:0] select_ln93_31_fu_290_p3; +wire [8:0] xor_ln93_23_fu_306_p2; +wire [255:0] zext_ln93_62_fu_272_p1; +wire [255:0] zext_ln93_63_fu_312_p1; +wire [255:0] shl_ln93_fu_324_p2; +reg [255:0] tmp_75_fu_330_p4; +wire [255:0] zext_ln93_64_fu_316_p1; +wire [255:0] zext_ln93_65_fu_320_p1; +wire [255:0] shl_ln93_19_fu_348_p2; +wire [255:0] lshr_ln93_fu_354_p2; +wire [255:0] and_ln93_fu_360_p2; +wire [255:0] xor_ln93_24_fu_366_p2; +wire [255:0] select_ln93_33_fu_340_p3; +wire [255:0] and_ln93_23_fu_372_p2; +wire [255:0] and_ln93_24_fu_378_p2; +wire [3:0] trunc_ln_fu_232_p3; +wire [3:0] or_ln93_fu_394_p2; +wire [7:0] shl_ln93_9_fu_404_p3; +wire [7:0] empty_136_fu_412_p2; +wire [15:0] bitcast_ln93_13_fu_400_p1; +wire [8:0] zext_ln93_66_fu_424_p1; +wire [0:0] icmp_ln93_7_fu_418_p2; +wire [8:0] zext_ln93_67_fu_428_p1; +wire [8:0] xor_ln93_25_fu_436_p2; +wire [8:0] select_ln93_34_fu_442_p3; +wire [8:0] select_ln93_36_fu_458_p3; +wire [8:0] select_ln93_35_fu_450_p3; +wire [8:0] xor_ln93_26_fu_466_p2; +wire [255:0] zext_ln93_68_fu_432_p1; +wire [255:0] zext_ln93_69_fu_472_p1; +wire [255:0] shl_ln93_20_fu_484_p2; +reg [255:0] tmp_76_fu_490_p4; +wire [255:0] zext_ln93_70_fu_476_p1; +wire [255:0] zext_ln93_71_fu_480_p1; +wire [255:0] shl_ln93_21_fu_508_p2; +wire [255:0] lshr_ln93_7_fu_514_p2; +wire [255:0] and_ln93_25_fu_520_p2; +wire [255:0] or_ln93_11_fu_384_p2; +wire [255:0] xor_ln93_27_fu_526_p2; +wire [255:0] select_ln93_37_fu_500_p3; +wire [255:0] and_ln93_26_fu_532_p2; +wire [255:0] and_ln93_27_fu_538_p2; +wire [3:0] or_ln93_5_fu_554_p2; +wire [7:0] shl_ln93_s_fu_564_p3; +wire [7:0] empty_137_fu_572_p2; +wire [15:0] bitcast_ln93_14_fu_560_p1; +wire [8:0] zext_ln93_72_fu_584_p1; +wire [0:0] icmp_ln93_8_fu_578_p2; +wire [8:0] zext_ln93_73_fu_588_p1; +wire [8:0] xor_ln93_28_fu_596_p2; +wire [8:0] select_ln93_38_fu_602_p3; +wire [8:0] select_ln93_40_fu_618_p3; +wire [8:0] select_ln93_39_fu_610_p3; +wire [8:0] xor_ln93_29_fu_626_p2; +wire [255:0] zext_ln93_74_fu_592_p1; +wire [255:0] zext_ln93_75_fu_632_p1; +wire [255:0] shl_ln93_22_fu_644_p2; +reg [255:0] tmp_77_fu_650_p4; +wire [255:0] zext_ln93_76_fu_636_p1; +wire [255:0] zext_ln93_77_fu_640_p1; +wire [255:0] shl_ln93_23_fu_668_p2; +wire [255:0] lshr_ln93_8_fu_674_p2; +wire [255:0] and_ln93_28_fu_680_p2; +wire [255:0] or_ln93_12_fu_544_p2; +wire [255:0] xor_ln93_30_fu_686_p2; +wire [255:0] select_ln93_41_fu_660_p3; +wire [255:0] and_ln93_29_fu_692_p2; +wire [255:0] and_ln93_30_fu_698_p2; +wire [3:0] or_ln93_6_fu_714_p2; +wire [7:0] shl_ln93_1_fu_724_p3; +wire [7:0] empty_138_fu_732_p2; +wire [15:0] bitcast_ln93_15_fu_720_p1; +wire [8:0] zext_ln93_78_fu_744_p1; +wire [0:0] icmp_ln93_9_fu_738_p2; +wire [8:0] zext_ln93_79_fu_748_p1; +wire [8:0] xor_ln93_31_fu_756_p2; +wire [8:0] select_ln93_42_fu_762_p3; +wire [8:0] select_ln93_44_fu_778_p3; +wire [8:0] select_ln93_43_fu_770_p3; +wire [8:0] xor_ln93_32_fu_786_p2; +wire [255:0] zext_ln93_80_fu_752_p1; +wire [255:0] zext_ln93_81_fu_792_p1; +wire [255:0] shl_ln93_24_fu_804_p2; +reg [255:0] tmp_78_fu_810_p4; +wire [255:0] zext_ln93_82_fu_796_p1; +wire [255:0] zext_ln93_83_fu_800_p1; +wire [255:0] shl_ln93_25_fu_828_p2; +wire [255:0] lshr_ln93_9_fu_834_p2; +wire [255:0] and_ln93_31_fu_840_p2; +wire [255:0] or_ln93_13_fu_704_p2; +wire [255:0] xor_ln93_33_fu_846_p2; +wire [255:0] select_ln93_45_fu_820_p3; +wire [255:0] and_ln93_32_fu_852_p2; +wire [255:0] and_ln93_33_fu_858_p2; +wire [15:0] add_ln95_fu_871_p2; +wire [0:0] icmp_ln96_fu_877_p2; +reg [1:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 2'd1; +#0 outputCount_4 = 16'd0; +#0 outputChanIdx_4 = 16'd0; +#0 outputRow_8_0 = 16'd0; +#0 outputRow_8_1 = 16'd0; +#0 outputRow_8_2 = 16'd0; +#0 outputRow_8_3 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln87_reg_917 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + empty_139_reg_129 <= 16'd0; + end else if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln87_fu_214_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + empty_139_reg_129 <= add_ln86_fu_208_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + icmp_ln87_reg_917 <= icmp_ln87_fu_214_p2; + out_data_addr_reg_903 <= zext_ln93_59_fu_171_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln87_reg_917 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + outputChanIdx_4 <= select_ln96_fu_883_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + outputCount_4 <= ap_phi_mux_empty_139_phi_fu_132_p4; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (trunc_ln85_fu_180_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_8_0 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (trunc_ln85_fu_180_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_8_1 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (trunc_ln85_fu_180_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_8_2 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (trunc_ln85_fu_180_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_8_3 <= p_read; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln87_reg_917 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_phi_mux_empty_139_phi_fu_132_p4 = 16'd0; + end else begin + ap_phi_mux_empty_139_phi_fu_132_p4 = empty_139_reg_129; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_data_ce0 = 1'b1; + end else begin + out_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln87_reg_917 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 1'd0; + end + endcase +end + +assign add_ln86_fu_208_p2 = (outputCount_4 + 16'd1); + +assign add_ln93_fu_165_p2 = (sub_ln93_fu_159_p2 + indices_12_dout); + +assign add_ln95_fu_871_p2 = (outputChanIdx_4 + 16'd1); + +assign and_ln93_23_fu_372_p2 = (xor_ln93_24_fu_366_p2 & out_data_q0); + +assign and_ln93_24_fu_378_p2 = (select_ln93_33_fu_340_p3 & and_ln93_fu_360_p2); + +assign and_ln93_25_fu_520_p2 = (shl_ln93_21_fu_508_p2 & lshr_ln93_7_fu_514_p2); + +assign and_ln93_26_fu_532_p2 = (xor_ln93_27_fu_526_p2 & or_ln93_11_fu_384_p2); + +assign and_ln93_27_fu_538_p2 = (select_ln93_37_fu_500_p3 & and_ln93_25_fu_520_p2); + +assign and_ln93_28_fu_680_p2 = (shl_ln93_23_fu_668_p2 & lshr_ln93_8_fu_674_p2); + +assign and_ln93_29_fu_692_p2 = (xor_ln93_30_fu_686_p2 & or_ln93_12_fu_544_p2); + +assign and_ln93_30_fu_698_p2 = (select_ln93_41_fu_660_p3 & and_ln93_28_fu_680_p2); + +assign and_ln93_31_fu_840_p2 = (shl_ln93_25_fu_828_p2 & lshr_ln93_9_fu_834_p2); + +assign and_ln93_32_fu_852_p2 = (xor_ln93_33_fu_846_p2 & or_ln93_13_fu_704_p2); + +assign and_ln93_33_fu_858_p2 = (select_ln93_45_fu_820_p3 & and_ln93_31_fu_840_p2); + +assign and_ln93_fu_360_p2 = (shl_ln93_19_fu_348_p2 & lshr_ln93_fu_354_p2); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign bitcast_ln93_13_fu_400_p1 = outputRow_8_1; + +assign bitcast_ln93_14_fu_560_p1 = outputRow_8_2; + +assign bitcast_ln93_15_fu_720_p1 = outputRow_8_3; + +assign bitcast_ln93_fu_240_p1 = outputRow_8_0; + +assign empty_136_fu_412_p2 = (shl_ln93_9_fu_404_p3 | 8'd15); + +assign empty_137_fu_572_p2 = (shl_ln93_s_fu_564_p3 | 8'd15); + +assign empty_138_fu_732_p2 = (shl_ln93_1_fu_724_p3 | 8'd15); + +assign empty_fu_252_p2 = (shl_ln_fu_244_p3 | 8'd15); + +assign icmp_ln87_fu_214_p2 = ((add_ln86_fu_208_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign icmp_ln93_7_fu_418_p2 = ((shl_ln93_9_fu_404_p3 > empty_136_fu_412_p2) ? 1'b1 : 1'b0); + +assign icmp_ln93_8_fu_578_p2 = ((shl_ln93_s_fu_564_p3 > empty_137_fu_572_p2) ? 1'b1 : 1'b0); + +assign icmp_ln93_9_fu_738_p2 = ((shl_ln93_1_fu_724_p3 > empty_138_fu_732_p2) ? 1'b1 : 1'b0); + +assign icmp_ln93_fu_258_p2 = ((shl_ln_fu_244_p3 > empty_fu_252_p2) ? 1'b1 : 1'b0); + +assign icmp_ln96_fu_877_p2 = ((add_ln95_fu_871_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign lshr_ln93_7_fu_514_p2 = 256'd115792089237316195423570985008687907853269984665640564039457584007913129639935 >> zext_ln93_71_fu_480_p1; + +assign lshr_ln93_8_fu_674_p2 = 256'd115792089237316195423570985008687907853269984665640564039457584007913129639935 >> zext_ln93_77_fu_640_p1; + +assign lshr_ln93_9_fu_834_p2 = 256'd115792089237316195423570985008687907853269984665640564039457584007913129639935 >> zext_ln93_83_fu_800_p1; + +assign lshr_ln93_fu_354_p2 = 256'd115792089237316195423570985008687907853269984665640564039457584007913129639935 >> zext_ln93_65_fu_320_p1; + +assign or_ln93_11_fu_384_p2 = (and_ln93_24_fu_378_p2 | and_ln93_23_fu_372_p2); + +assign or_ln93_12_fu_544_p2 = (and_ln93_27_fu_538_p2 | and_ln93_26_fu_532_p2); + +assign or_ln93_13_fu_704_p2 = (and_ln93_30_fu_698_p2 | and_ln93_29_fu_692_p2); + +assign or_ln93_5_fu_554_p2 = (trunc_ln_fu_232_p3 | 4'd2); + +assign or_ln93_6_fu_714_p2 = (trunc_ln_fu_232_p3 | 4'd3); + +assign or_ln93_fu_394_p2 = (trunc_ln_fu_232_p3 | 4'd1); + +assign out_data_address0 = zext_ln93_59_fu_171_p1; + +assign out_data_address1 = out_data_addr_reg_903; + +assign out_data_d1 = (and_ln93_33_fu_858_p2 | and_ln93_32_fu_852_p2); + +assign select_ln93_31_fu_290_p3 = ((icmp_ln93_fu_258_p2[0:0] == 1'b1) ? zext_ln93_61_fu_268_p1 : zext_ln93_60_fu_264_p1); + +assign select_ln93_32_fu_298_p3 = ((icmp_ln93_fu_258_p2[0:0] == 1'b1) ? xor_ln93_fu_276_p2 : zext_ln93_60_fu_264_p1); + +assign select_ln93_33_fu_340_p3 = ((icmp_ln93_fu_258_p2[0:0] == 1'b1) ? tmp_75_fu_330_p4 : shl_ln93_fu_324_p2); + +assign select_ln93_34_fu_442_p3 = ((icmp_ln93_7_fu_418_p2[0:0] == 1'b1) ? zext_ln93_66_fu_424_p1 : zext_ln93_67_fu_428_p1); + +assign select_ln93_35_fu_450_p3 = ((icmp_ln93_7_fu_418_p2[0:0] == 1'b1) ? zext_ln93_67_fu_428_p1 : zext_ln93_66_fu_424_p1); + +assign select_ln93_36_fu_458_p3 = ((icmp_ln93_7_fu_418_p2[0:0] == 1'b1) ? xor_ln93_25_fu_436_p2 : zext_ln93_66_fu_424_p1); + +assign select_ln93_37_fu_500_p3 = ((icmp_ln93_7_fu_418_p2[0:0] == 1'b1) ? tmp_76_fu_490_p4 : shl_ln93_20_fu_484_p2); + +assign select_ln93_38_fu_602_p3 = ((icmp_ln93_8_fu_578_p2[0:0] == 1'b1) ? zext_ln93_72_fu_584_p1 : zext_ln93_73_fu_588_p1); + +assign select_ln93_39_fu_610_p3 = ((icmp_ln93_8_fu_578_p2[0:0] == 1'b1) ? zext_ln93_73_fu_588_p1 : zext_ln93_72_fu_584_p1); + +assign select_ln93_40_fu_618_p3 = ((icmp_ln93_8_fu_578_p2[0:0] == 1'b1) ? xor_ln93_28_fu_596_p2 : zext_ln93_72_fu_584_p1); + +assign select_ln93_41_fu_660_p3 = ((icmp_ln93_8_fu_578_p2[0:0] == 1'b1) ? tmp_77_fu_650_p4 : shl_ln93_22_fu_644_p2); + +assign select_ln93_42_fu_762_p3 = ((icmp_ln93_9_fu_738_p2[0:0] == 1'b1) ? zext_ln93_78_fu_744_p1 : zext_ln93_79_fu_748_p1); + +assign select_ln93_43_fu_770_p3 = ((icmp_ln93_9_fu_738_p2[0:0] == 1'b1) ? zext_ln93_79_fu_748_p1 : zext_ln93_78_fu_744_p1); + +assign select_ln93_44_fu_778_p3 = ((icmp_ln93_9_fu_738_p2[0:0] == 1'b1) ? xor_ln93_31_fu_756_p2 : zext_ln93_78_fu_744_p1); + +assign select_ln93_45_fu_820_p3 = ((icmp_ln93_9_fu_738_p2[0:0] == 1'b1) ? tmp_78_fu_810_p4 : shl_ln93_24_fu_804_p2); + +assign select_ln93_fu_282_p3 = ((icmp_ln93_fu_258_p2[0:0] == 1'b1) ? zext_ln93_60_fu_264_p1 : zext_ln93_61_fu_268_p1); + +assign select_ln96_fu_883_p3 = ((icmp_ln96_fu_877_p2[0:0] == 1'b1) ? 16'd0 : add_ln95_fu_871_p2); + +assign shl_ln93_19_fu_348_p2 = 256'd115792089237316195423570985008687907853269984665640564039457584007913129639935 << zext_ln93_64_fu_316_p1; + +assign shl_ln93_1_fu_724_p3 = {{or_ln93_6_fu_714_p2}, {4'd0}}; + +assign shl_ln93_20_fu_484_p2 = zext_ln93_68_fu_432_p1 << zext_ln93_69_fu_472_p1; + +assign shl_ln93_21_fu_508_p2 = 256'd115792089237316195423570985008687907853269984665640564039457584007913129639935 << zext_ln93_70_fu_476_p1; + +assign shl_ln93_22_fu_644_p2 = zext_ln93_74_fu_592_p1 << zext_ln93_75_fu_632_p1; + +assign shl_ln93_23_fu_668_p2 = 256'd115792089237316195423570985008687907853269984665640564039457584007913129639935 << zext_ln93_76_fu_636_p1; + +assign shl_ln93_24_fu_804_p2 = zext_ln93_80_fu_752_p1 << zext_ln93_81_fu_792_p1; + +assign shl_ln93_25_fu_828_p2 = 256'd115792089237316195423570985008687907853269984665640564039457584007913129639935 << zext_ln93_82_fu_796_p1; + +assign shl_ln93_9_fu_404_p3 = {{or_ln93_fu_394_p2}, {4'd0}}; + +assign shl_ln93_fu_324_p2 = zext_ln93_62_fu_272_p1 << zext_ln93_63_fu_312_p1; + +assign shl_ln93_s_fu_564_p3 = {{or_ln93_5_fu_554_p2}, {4'd0}}; + +assign shl_ln_fu_244_p3 = {{trunc_ln93_fu_228_p1}, {6'd0}}; + +assign sub_ln93_fu_159_p2 = (tmp_fu_139_p3 - zext_ln93_fu_155_p1); + +integer ap_tvar_int_0; + +always @ (shl_ln93_fu_324_p2) begin + //for (ap_tvar_int_0 = 256 - 1; ap_tvar_int_0 >= 0; ap_tvar_int_0 = ap_tvar_int_0 - 1) begin + for (ap_tvar_int_0 = 0; ap_tvar_int_0 < 256; ap_tvar_int_0 = ap_tvar_int_0 + 1) begin + if (ap_tvar_int_0 > 255 - 0) begin + tmp_75_fu_330_p4[ap_tvar_int_0] = 1'b0; + end else begin + tmp_75_fu_330_p4[ap_tvar_int_0] = shl_ln93_fu_324_p2[255 - ap_tvar_int_0]; + end + end +end + +integer ap_tvar_int_1; + +always @ (shl_ln93_20_fu_484_p2) begin + //for (ap_tvar_int_1 = 256 - 1; ap_tvar_int_1 >= 0; ap_tvar_int_1 = ap_tvar_int_1 - 1) begin + for (ap_tvar_int_1 = 0; ap_tvar_int_1 < 256; ap_tvar_int_1 = ap_tvar_int_1 + 1) begin + if (ap_tvar_int_1 > 255 - 0) begin + tmp_76_fu_490_p4[ap_tvar_int_1] = 1'b0; + end else begin + tmp_76_fu_490_p4[ap_tvar_int_1] = shl_ln93_20_fu_484_p2[255 - ap_tvar_int_1]; + end + end +end + +integer ap_tvar_int_2; + +always @ (shl_ln93_22_fu_644_p2) begin + //for (ap_tvar_int_2 = 256 - 1; ap_tvar_int_2 >= 0; ap_tvar_int_2 = ap_tvar_int_2 - 1) begin + for (ap_tvar_int_2 = 0; ap_tvar_int_2 < 256; ap_tvar_int_2 = ap_tvar_int_2 + 1) begin + if (ap_tvar_int_2 > 255 - 0) begin + tmp_77_fu_650_p4[ap_tvar_int_2] = 1'b0; + end else begin + tmp_77_fu_650_p4[ap_tvar_int_2] = shl_ln93_22_fu_644_p2[255 - ap_tvar_int_2]; + end + end +end + +integer ap_tvar_int_3; + +always @ (shl_ln93_24_fu_804_p2) begin + //for (ap_tvar_int_3 = 256 - 1; ap_tvar_int_3 >= 0; ap_tvar_int_3 = ap_tvar_int_3 - 1) begin + for (ap_tvar_int_3 = 0; ap_tvar_int_3 < 256; ap_tvar_int_3 = ap_tvar_int_3 + 1) begin + if (ap_tvar_int_3 > 255 - 0) begin + tmp_78_fu_810_p4[ap_tvar_int_3] = 1'b0; + end else begin + tmp_78_fu_810_p4[ap_tvar_int_3] = shl_ln93_24_fu_804_p2[255 - ap_tvar_int_3]; + end + end +end + +assign tmp_fu_139_p3 = {{indices_01_dout}, {6'd0}}; + +assign tmp_s_fu_147_p3 = {{indices_01_dout}, {3'd0}}; + +assign trunc_ln85_fu_180_p1 = outputCount_4[1:0]; + +assign trunc_ln93_fu_228_p1 = outputChanIdx_4[1:0]; + +assign trunc_ln_fu_232_p3 = {{trunc_ln93_fu_228_p1}, {2'd0}}; + +assign xor_ln93_23_fu_306_p2 = (select_ln93_fu_282_p3 ^ 9'd255); + +assign xor_ln93_24_fu_366_p2 = (256'd115792089237316195423570985008687907853269984665640564039457584007913129639935 ^ and_ln93_fu_360_p2); + +assign xor_ln93_25_fu_436_p2 = (zext_ln93_66_fu_424_p1 ^ 9'd255); + +assign xor_ln93_26_fu_466_p2 = (select_ln93_34_fu_442_p3 ^ 9'd255); + +assign xor_ln93_27_fu_526_p2 = (256'd115792089237316195423570985008687907853269984665640564039457584007913129639935 ^ and_ln93_25_fu_520_p2); + +assign xor_ln93_28_fu_596_p2 = (zext_ln93_72_fu_584_p1 ^ 9'd255); + +assign xor_ln93_29_fu_626_p2 = (select_ln93_38_fu_602_p3 ^ 9'd255); + +assign xor_ln93_30_fu_686_p2 = (256'd115792089237316195423570985008687907853269984665640564039457584007913129639935 ^ and_ln93_28_fu_680_p2); + +assign xor_ln93_31_fu_756_p2 = (zext_ln93_78_fu_744_p1 ^ 9'd255); + +assign xor_ln93_32_fu_786_p2 = (select_ln93_42_fu_762_p3 ^ 9'd255); + +assign xor_ln93_33_fu_846_p2 = (256'd115792089237316195423570985008687907853269984665640564039457584007913129639935 ^ and_ln93_31_fu_840_p2); + +assign xor_ln93_fu_276_p2 = (zext_ln93_60_fu_264_p1 ^ 9'd255); + +assign zext_ln93_59_fu_171_p1 = add_ln93_fu_165_p2; + +assign zext_ln93_60_fu_264_p1 = shl_ln_fu_244_p3; + +assign zext_ln93_61_fu_268_p1 = empty_fu_252_p2; + +assign zext_ln93_62_fu_272_p1 = bitcast_ln93_fu_240_p1; + +assign zext_ln93_63_fu_312_p1 = select_ln93_32_fu_298_p3; + +assign zext_ln93_64_fu_316_p1 = select_ln93_31_fu_290_p3; + +assign zext_ln93_65_fu_320_p1 = xor_ln93_23_fu_306_p2; + +assign zext_ln93_66_fu_424_p1 = shl_ln93_9_fu_404_p3; + +assign zext_ln93_67_fu_428_p1 = empty_136_fu_412_p2; + +assign zext_ln93_68_fu_432_p1 = bitcast_ln93_13_fu_400_p1; + +assign zext_ln93_69_fu_472_p1 = select_ln93_36_fu_458_p3; + +assign zext_ln93_70_fu_476_p1 = select_ln93_35_fu_450_p3; + +assign zext_ln93_71_fu_480_p1 = xor_ln93_26_fu_466_p2; + +assign zext_ln93_72_fu_584_p1 = shl_ln93_s_fu_564_p3; + +assign zext_ln93_73_fu_588_p1 = empty_137_fu_572_p2; + +assign zext_ln93_74_fu_592_p1 = bitcast_ln93_14_fu_560_p1; + +assign zext_ln93_75_fu_632_p1 = select_ln93_40_fu_618_p3; + +assign zext_ln93_76_fu_636_p1 = select_ln93_39_fu_610_p3; + +assign zext_ln93_77_fu_640_p1 = xor_ln93_29_fu_626_p2; + +assign zext_ln93_78_fu_744_p1 = shl_ln93_1_fu_724_p3; + +assign zext_ln93_79_fu_748_p1 = empty_138_fu_732_p2; + +assign zext_ln93_80_fu_752_p1 = bitcast_ln93_15_fu_720_p1; + +assign zext_ln93_81_fu_792_p1 = select_ln93_44_fu_778_p3; + +assign zext_ln93_82_fu_796_p1 = select_ln93_43_fu_770_p3; + +assign zext_ln93_83_fu_800_p1 = xor_ln93_32_fu_786_p2; + +assign zext_ln93_fu_155_p1 = tmp_s_fu_147_p3; + +endmodule //td_fused_top_tdf3_writeOutputs_unaligned + +module top ( + ap_clk, + ap_rst, + in_data_address0_0, + in_data_address0_1, + in_data_address0_2, + in_data_ce0_0, + in_data_ce0_1, + in_data_ce0_2, + in_data_d0_0, + in_data_d0_1, + in_data_d0_2, + in_data_q0_0, + in_data_q0_1, + in_data_q0_2, + in_data_we0_0, + in_data_we0_1, + in_data_we0_2, + in_data_address1_0, + in_data_address1_1, + in_data_address1_2, + in_data_ce1_0, + in_data_ce1_1, + in_data_ce1_2, + in_data_d1_0, + in_data_d1_1, + in_data_d1_2, + in_data_q1_0, + in_data_q1_1, + in_data_q1_2, + in_data_we1_0, + in_data_we1_1, + in_data_we1_2, + filter_data_address0_0, + filter_data_address0_1, + filter_data_address0_2, + filter_data_ce0_0, + filter_data_ce0_1, + filter_data_ce0_2, + filter_data_d0_0, + filter_data_d0_1, + filter_data_d0_2, + filter_data_q0_0, + filter_data_q0_1, + filter_data_q0_2, + filter_data_we0_0, + filter_data_we0_1, + filter_data_we0_2, + filter_data_address1_0, + filter_data_address1_1, + filter_data_address1_2, + filter_data_ce1_0, + filter_data_ce1_1, + filter_data_ce1_2, + filter_data_d1_0, + filter_data_d1_1, + filter_data_d1_2, + filter_data_q1_0, + filter_data_q1_1, + filter_data_q1_2, + filter_data_we1_0, + filter_data_we1_1, + filter_data_we1_2, + out_data_address0_0, + out_data_address0_1, + out_data_address0_2, + out_data_ce0_0, + out_data_ce0_1, + out_data_ce0_2, + out_data_d0_0, + out_data_d0_1, + out_data_d0_2, + out_data_q0_0, + out_data_q0_1, + out_data_q0_2, + out_data_we0_0, + out_data_we0_1, + out_data_we0_2, + out_data_address1_0, + out_data_address1_1, + out_data_address1_2, + out_data_ce1_0, + out_data_ce1_1, + out_data_ce1_2, + out_data_d1_0, + out_data_d1_1, + out_data_d1_2, + out_data_q1_0, + out_data_q1_1, + out_data_q1_2, + out_data_we1_0, + out_data_we1_1, + out_data_we1_2, + ap_start_0, + ap_start_1, + ap_start_2, + in_data_empty_n_0, + in_data_empty_n_1, + in_data_empty_n_2, + in_data_read_0, + in_data_read_1, + in_data_read_2, + out_data_full_n_0, + out_data_full_n_1, + out_data_full_n_2, + out_data_write_0, + out_data_write_1, + out_data_write_2, + ap_done_0, + ap_done_1, + ap_done_2, + ap_ready_0, + ap_ready_1, + ap_ready_2, + ap_idle_0, + ap_idle_1, + ap_idle_2, + ap_continue_0, + ap_continue_1, + ap_continue_2 +); + + +input ap_clk; +input ap_rst; +///////////////////////////////////////////////// +output [14:0] in_data_address0_0; +output in_data_ce0_0; +output [63:0] in_data_d0_0; +input [63:0] in_data_q0_0; +output in_data_we0_0; +output [14:0] in_data_address1_0; +output in_data_ce1_0; +output [63:0] in_data_d1_0; +input [63:0] in_data_q1_0; +output in_data_we1_0; +output [8:0] filter_data_address0_0; +output filter_data_ce0_0; +output [15:0] filter_data_d0_0; +input [15:0] filter_data_q0_0; +output filter_data_we0_0; +output [8:0] filter_data_address1_0; +output filter_data_ce1_0; +output [15:0] filter_data_d1_0; +input [15:0] filter_data_q1_0; +output filter_data_we1_0; +output [11:0] out_data_address0_0; +output out_data_ce0_0; +output [255:0] out_data_d0_0; +input [255:0] out_data_q0_0; +output out_data_we0_0; +output [11:0] out_data_address1_0; +output out_data_ce1_0; +output [255:0] out_data_d1_0; +input [255:0] out_data_q1_0; +output out_data_we1_0; +input ap_start_0; +input in_data_empty_n_0; +output in_data_read_0; +input out_data_full_n_0; +output out_data_write_0; +output ap_done_0; +output ap_ready_0; +output ap_idle_0; +input ap_continue_0; +///////////////////////////////////////////////// +output [14:0] in_data_address0_1; +output in_data_ce0_1; +output [63:0] in_data_d0_1; +input [63:0] in_data_q0_1; +output in_data_we0_1; +output [14:0] in_data_address1_1; +output in_data_ce1_1; +output [63:0] in_data_d1_1; +input [63:0] in_data_q1_1; +output in_data_we1_1; +output [8:0] filter_data_address0_1; +output filter_data_ce0_1; +output [15:0] filter_data_d0_1; +input [15:0] filter_data_q0_1; +output filter_data_we0_1; +output [8:0] filter_data_address1_1; +output filter_data_ce1_1; +output [15:0] filter_data_d1_1; +input [15:0] filter_data_q1_1; +output filter_data_we1_1; +output [11:0] out_data_address0_1; +output out_data_ce0_1; +output [255:0] out_data_d0_1; +input [255:0] out_data_q0_1; +output out_data_we0_1; +output [11:0] out_data_address1_1; +output out_data_ce1_1; +output [255:0] out_data_d1_1; +input [255:0] out_data_q1_1; +output out_data_we1_1; +input ap_start_1; +input in_data_empty_n_1; +output in_data_read_1; +input out_data_full_n_1; +output out_data_write_1; +output ap_done_1; +output ap_ready_1; +output ap_idle_1; +input ap_continue_1; +///////////////////////////////////////////////// +output [14:0] in_data_address0_2; +output in_data_ce0_2; +output [63:0] in_data_d0_2; +input [63:0] in_data_q0_2; +output in_data_we0_2; +output [14:0] in_data_address1_2; +output in_data_ce1_2; +output [63:0] in_data_d1_2; +input [63:0] in_data_q1_2; +output in_data_we1_2; +output [8:0] filter_data_address0_2; +output filter_data_ce0_2; +output [15:0] filter_data_d0_2; +input [15:0] filter_data_q0_2; +output filter_data_we0_2; +output [8:0] filter_data_address1_2; +output filter_data_ce1_2; +output [15:0] filter_data_d1_2; +input [15:0] filter_data_q1_2; +output filter_data_we1_2; +output [11:0] out_data_address0_2; +output out_data_ce0_2; +output [255:0] out_data_d0_2; +input [255:0] out_data_q0_2; +output out_data_we0_2; +output [11:0] out_data_address1_2; +output out_data_ce1_2; +output [255:0] out_data_d1_2; +input [255:0] out_data_q1_2; +output out_data_we1_2; +input ap_start_2; +input in_data_empty_n_2; +output in_data_read_2; +input out_data_full_n_2; +output out_data_write_2; +output ap_done_2; +output ap_ready_2; +output ap_idle_2; +input ap_continue_2; + + + td_fused_top_dataflow_in_loop_TOP_LOOP49028 i_0 ( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(in_data_address0_0), + .in_data_ce0(in_data_ce0_0), + .in_data_d0(in_data_d0_0), + .in_data_q0(in_data_q0_0), + .in_data_we0(in_data_we0_0), + .in_data_address1(in_data_address1_0), + .in_data_ce1(in_data_ce1_0), + .in_data_d1(in_data_d1_0), + .in_data_q1(in_data_q1_0), + .in_data_we1(in_data_we1_0), + .filter_data_address0(filter_data_address0_0), + .filter_data_ce0(filter_data_ce0_0), + .filter_data_d0(filter_data_d0_0), + .filter_data_q0(filter_data_q0_0), + .filter_data_we0(filter_data_we0_0), + .filter_data_address1(filter_data_address1_0), + .filter_data_ce1(filter_data_ce1_0), + .filter_data_d1(filter_data_d1_0), + .filter_data_q1(filter_data_q1_0), + .filter_data_we1(filter_data_we1_0), + .out_data_address0(out_data_address0_0), + .out_data_ce0(out_data_ce0_0), + .out_data_d0(out_data_d0_0), + .out_data_q0(out_data_q0_0), + .out_data_we0(out_data_we0_0), + .out_data_address1(out_data_address1_0), + .out_data_ce1(out_data_ce1_0), + .out_data_d1(out_data_d1_0), + .out_data_q1(out_data_q1_0), + .out_data_we1(out_data_we1_0), + .ap_start(ap_start_0), + .in_data_empty_n(in_data_empty_n_0), + .in_data_read(in_data_read_0), + .out_data_full_n(out_data_full_n_0), + .out_data_write(out_data_write_0), + .ap_done(ap_done_0), + .ap_ready(ap_ready_0), + .ap_idle(ap_idle_0), + .ap_continue(ap_continue_0) + ); + + + td_fused_top_dataflow_in_loop_TOP_LOOP49028 i_1 ( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(in_data_address0_1), + .in_data_ce0(in_data_ce0_1), + .in_data_d0(in_data_d0_1), + .in_data_q0(in_data_q0_1), + .in_data_we0(in_data_we0_1), + .in_data_address1(in_data_address1_1), + .in_data_ce1(in_data_ce1_1), + .in_data_d1(in_data_d1_1), + .in_data_q1(in_data_q1_1), + .in_data_we1(in_data_we1_1), + .filter_data_address0(filter_data_address0_1), + .filter_data_ce0(filter_data_ce0_1), + .filter_data_d0(filter_data_d0_1), + .filter_data_q0(filter_data_q0_1), + .filter_data_we0(filter_data_we0_1), + .filter_data_address1(filter_data_address1_1), + .filter_data_ce1(filter_data_ce1_1), + .filter_data_d1(filter_data_d1_1), + .filter_data_q1(filter_data_q1_1), + .filter_data_we1(filter_data_we1_1), + .out_data_address0(out_data_address0_1), + .out_data_ce0(out_data_ce0_1), + .out_data_d0(out_data_d0_1), + .out_data_q0(out_data_q0_1), + .out_data_we0(out_data_we0_1), + .out_data_address1(out_data_address1_1), + .out_data_ce1(out_data_ce1_1), + .out_data_d1(out_data_d1_1), + .out_data_q1(out_data_q1_1), + .out_data_we1(out_data_we1_1), + .ap_start(ap_start_1), + .in_data_empty_n(in_data_empty_n_1), + .in_data_read(in_data_read_1), + .out_data_full_n(out_data_full_n_1), + .out_data_write(out_data_write_1), + .ap_done(ap_done_1), + .ap_ready(ap_ready_1), + .ap_idle(ap_idle_1), + .ap_continue(ap_continue_1) + ); + + + td_fused_top_dataflow_in_loop_TOP_LOOP49028 i_2 ( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(in_data_address0_2), + .in_data_ce0(in_data_ce0_2), + .in_data_d0(in_data_d0_2), + .in_data_q0(in_data_q0_2), + .in_data_we0(in_data_we0_2), + .in_data_address1(in_data_address1_2), + .in_data_ce1(in_data_ce1_2), + .in_data_d1(in_data_d1_2), + .in_data_q1(in_data_q1_2), + .in_data_we1(in_data_we1_2), + .filter_data_address0(filter_data_address0_2), + .filter_data_ce0(filter_data_ce0_2), + .filter_data_d0(filter_data_d0_2), + .filter_data_q0(filter_data_q0_2), + .filter_data_we0(filter_data_we0_2), + .filter_data_address1(filter_data_address1_2), + .filter_data_ce1(filter_data_ce1_2), + .filter_data_d1(filter_data_d1_2), + .filter_data_q1(filter_data_q1_2), + .filter_data_we1(filter_data_we1_2), + .out_data_address0(out_data_address0_2), + .out_data_ce0(out_data_ce0_2), + .out_data_d0(out_data_d0_2), + .out_data_q0(out_data_q0_2), + .out_data_we0(out_data_we0_2), + .out_data_address1(out_data_address1_2), + .out_data_ce1(out_data_ce1_2), + .out_data_d1(out_data_d1_2), + .out_data_q1(out_data_q1_2), + .out_data_we1(out_data_we1_2), + .ap_start(ap_start_2), + .in_data_empty_n(in_data_empty_n_2), + .in_data_read(in_data_read_2), + .out_data_full_n(out_data_full_n_2), + .out_data_write(out_data_write_2), + .ap_done(ap_done_2), + .ap_ready(ap_ready_2), + .ap_idle(ap_idle_2), + .ap_continue(ap_continue_2) + ); + +endmodule + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Floating point 16-bit multiplier +// This is a heavily modified version of: +// https://github.com/fbrosser/DSP48E1-FP/tree/master/src/FPMult +// Original author: Fredrik Brosser +// Abridged by: Samidh Mehta +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// + +`ifndef complex_dsp + +`define EXPONENT 5 +`define MANTISSA 10 +`define ACTUAL_MANTISSA 11 +`define EXPONENT_LSB 10 +`define EXPONENT_MSB 14 +`define MANTISSA_LSB 0 +`define MANTISSA_MSB 9 +`define MANTISSA_MUL_SPLIT_LSB 3 +`define MANTISSA_MUL_SPLIT_MSB 9 +`define SIGN 1 +`define SIGN_LOC 15 +`define DWIDTH (`SIGN+`EXPONENT+`MANTISSA) +`define IEEE_COMPLIANCE 1 + +module FPMult_16( + clk, + rst, + a, + b, + result, + flags + ); + + // Input Ports + input clk ; // Clock + input rst ; // Reset signal + input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number + + // Output ports + output [`DWIDTH-1:0] result ; // Product, result of the operation, 32-bit FP number + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Internal signals + wire [31:0] Z_int ; // Product, result of the operation, 32-bit FP number + wire [4:0] Flags_int ; // Flags indicating exceptions according to IEEE754 + + wire Sa ; // A's sign + wire Sb ; // B's sign + wire Sp ; // Product sign + wire [`EXPONENT-1:0] Ea ; // A's exponent + wire [`EXPONENT-1:0] Eb ; // B's exponent + wire [2*`MANTISSA+1:0] Mp ; // Product mantissa + wire [4:0] InputExc ; // Exceptions in inputs + wire [`MANTISSA-1:0] NormM ; // Normalized mantissa + wire [`EXPONENT:0] NormE ; // Normalized exponent + wire [`MANTISSA:0] RoundM ; // Normalized mantissa + wire [`EXPONENT:0] RoundE ; // Normalized exponent + wire [`MANTISSA:0] RoundMP ; // Normalized mantissa + wire [`EXPONENT:0] RoundEP ; // Normalized exponent + wire GRS ; + + //reg [63:0] pipe_0; // Pipeline register Input->Prep + reg [2*`DWIDTH-1:0] pipe_0; // Pipeline register Input->Prep + + //reg [92:0] pipe_1; // Pipeline register Prep->Execute + reg [3*`MANTISSA+2*`EXPONENT+7:0] pipe_1; // Pipeline register Prep->Execute + + //reg [38:0] pipe_2; // Pipeline register Execute->Normalize + reg [`MANTISSA+`EXPONENT+7:0] pipe_2; // Pipeline register Execute->Normalize + + //reg [72:0] pipe_3; // Pipeline register Normalize->Round + reg [2*`MANTISSA+2*`EXPONENT+10:0] pipe_3; // Pipeline register Normalize->Round + + //reg [36:0] pipe_4; // Pipeline register Round->Output + reg [`DWIDTH+4:0] pipe_4; // Pipeline register Round->Output + + assign result = pipe_4[`DWIDTH+4:5] ; + assign flags = pipe_4[4:0] ; + + // Prepare the operands for alignment and check for exceptions + FPMult_PrepModule PrepModule(clk, rst, pipe_0[2*`DWIDTH-1:`DWIDTH], pipe_0[`DWIDTH-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]) ; + + // Perform (unsigned) mantissa multiplication + FPMult_ExecuteModule ExecuteModule(pipe_1[3*`MANTISSA+`EXPONENT*2+7:2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7:2*`MANTISSA+7], pipe_1[2*`MANTISSA+6:5], pipe_1[2*`MANTISSA+2*`EXPONENT+6:2*`MANTISSA+`EXPONENT+7], pipe_1[2*`MANTISSA+`EXPONENT+6:2*`MANTISSA+7], pipe_1[2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7], Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0], GRS) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + FPMult_NormalizeModule NormalizeModule(pipe_2[`MANTISSA-1:0], pipe_2[`MANTISSA+`EXPONENT:`MANTISSA], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + //FPMult_RoundModule RoundModule(pipe_3[47:24], pipe_3[23:0], pipe_3[65:57], pipe_3[56:48], pipe_3[66], pipe_3[67], pipe_3[72:68], Z_int[31:0], Flags_int[4:0]) ; + FPMult_RoundModule RoundModule(pipe_3[2*`MANTISSA+1:`MANTISSA+1], pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+2*`EXPONENT+3:2*`MANTISSA+`EXPONENT+3], pipe_3[2*`MANTISSA+`EXPONENT+2:2*`MANTISSA+2], pipe_3[2*`MANTISSA+2*`EXPONENT+4], pipe_3[2*`MANTISSA+2*`EXPONENT+5], pipe_3[2*`MANTISSA+2*`EXPONENT+10:2*`MANTISSA+2*`EXPONENT+6], Z_int[`DWIDTH-1:0], Flags_int[4:0]) ; + + always @ (*) begin + if(rst) begin + pipe_0 = 0; + pipe_1 = 0; + pipe_2 = 0; + pipe_3 = 0; + pipe_4 = 0; + end + else begin + /* PIPE 0 + [63:32] A + [31:0] B + */ + pipe_0 = {a, b} ; + + /* PIPE 1 + [70] Sa + [69] Sb + [68:61] Ea + [60:53] Eb + [52:5] Mp + [4:0] InputExc + */ + //pipe_1 <= {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[`MANTISSA_MUL_SPLIT_LSB-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA-1:0], InputExc[4:0]} ; + pipe_1 = {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[8:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]} ; + /* PIPE 2 + [38:34] InputExc + [33] GRS + [32] Sp + [31:23] NormE + [22:0] NormM + */ + pipe_2 = {pipe_1[4:0], GRS, Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0]} ; + /* PIPE 3 + [72:68] InputExc + [67] GRS + [66] Sp + [65:57] RoundE + [56:48] RoundEP + [47:24] RoundM + [23:0] RoundMP + */ + pipe_3 = {pipe_2[`EXPONENT+`MANTISSA+7:`EXPONENT+`MANTISSA+1], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]} ; + /* PIPE 4 + [36:5] Z + [4:0] Flags + */ + pipe_4 = {Z_int[`DWIDTH-1:0], Flags_int[4:0]} ; + end + end + +endmodule + + +module FPMult_PrepModule ( + clk, + rst, + a, + b, + Sa, + Sb, + Ea, + Eb, + Mp, + InputExc + ); + + // Input ports + input clk ; + input rst ; + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [`EXPONENT-1:0] Ea ; // A's exponent + output [`EXPONENT-1:0] Eb ; // B's exponent + output [2*`MANTISSA+1:0] Mp ; // Mantissa product + output [4:0] InputExc ; // Input numbers are exceptions + + // Internal signals // If signal is high... + wire ANaN ; // A is a signalling NaN + wire BNaN ; // B is a signalling NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`MANTISSA-1:0] Ma; + wire [`MANTISSA-1:0] Mb; + + assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + + // Check for any exceptions and put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + //assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ; + + // Take input numbers apart + assign Sa = a[`DWIDTH-1] ; // A's sign + assign Sb = b[`DWIDTH-1] ; // B's sign + assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception + assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception +// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB]; + // assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB]; + + + + //assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ; + assign Mp = ({1'b1,a[`MANTISSA-1:0]}*{1'b1, b[`MANTISSA-1:0]}) ; + + + //We multiply part of the mantissa here + //Full mantissa of A + //Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B + // wire [`ACTUAL_MANTISSA-1:0] inp_A; + // wire [`ACTUAL_MANTISSA-1:0] inp_B; + // assign inp_A = {1'b1, Ma}; + // assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp)); +endmodule + + +module FPMult_ExecuteModule( + a, + b, + MpC, + Ea, + Eb, + Sa, + Sb, + Sp, + NormE, + NormM, + GRS + ); + + // Input ports + input [`MANTISSA-1:0] a ; + input [2*`EXPONENT:0] b ; + input [2*`MANTISSA+1:0] MpC ; + input [`EXPONENT-1:0] Ea ; // A's exponent + input [`EXPONENT-1:0] Eb ; // B's exponent + input Sa ; // A's sign + input Sb ; // B's sign + + // Output ports + output Sp ; // Product sign + output [`EXPONENT:0] NormE ; // Normalized exponent + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output GRS ; + + wire [2*`MANTISSA+1:0] Mp ; + + assign Sp = (Sa ^ Sb) ; // Equal signs give a positive product + + // wire [`ACTUAL_MANTISSA-1:0] inp_a; + // wire [`ACTUAL_MANTISSA-1:0] inp_b; + // assign inp_a = {1'b1, a}; + // assign inp_b = {{(`MANTISSA-`MANTISSA_MUL_SPLIT_LSB){1'b0}}, 1'b0, b}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_a), .B(inp_b), .TC(1'b0), .PRODUCT(Mp_temp)); + // DW01_add #(2*`ACTUAL_MANTISSA) u_add(.A(Mp_temp), .B(MpC<<`MANTISSA_MUL_SPLIT_LSB), .CI(1'b0), .SUM(Mp), .CO()); + + //assign Mp = (MpC<<(2*`EXPONENT+1)) + ({4'b0001, a[`MANTISSA-1:0]}*{1'b0, b[2*`EXPONENT:0]}) ; + assign Mp = MpC; + + + assign NormM = (Mp[2*`MANTISSA+1] ? Mp[2*`MANTISSA:`MANTISSA+1] : Mp[2*`MANTISSA-1:`MANTISSA]); // Check for overflow + assign NormE = (Ea + Eb + Mp[2*`MANTISSA+1]); // If so, increment exponent + + assign GRS = ((Mp[`MANTISSA]&(Mp[`MANTISSA+1]))|(|Mp[`MANTISSA-1:0])) ; + +endmodule + +module FPMult_NormalizeModule( + NormM, + NormE, + RoundE, + RoundEP, + RoundM, + RoundMP + ); + + // Input Ports + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input [`EXPONENT:0] NormE ; // Normalized exponent + + // Output Ports + output [`EXPONENT:0] RoundE ; + output [`EXPONENT:0] RoundEP ; + output [`MANTISSA:0] RoundM ; + output [`MANTISSA:0] RoundMP ; + + assign RoundE = NormE - 6'd15 ; + assign RoundEP = NormE - 6'd14 ; + assign RoundM = NormM ; + assign RoundMP = NormM ; + +endmodule + +module FPMult_RoundModule( + RoundM, + RoundMP, + RoundE, + RoundEP, + Sp, + GRS, + InputExc, + Z, + Flags + ); + + // Input Ports + input [`MANTISSA:0] RoundM ; // Normalized mantissa + input [`MANTISSA:0] RoundMP ; // Normalized exponent + input [`EXPONENT:0] RoundE ; // Normalized mantissa + 1 + input [`EXPONENT:0] RoundEP ; // Normalized exponent + 1 + input Sp ; // Product sign + input GRS ; + input [4:0] InputExc ; + + // Output Ports + output [`DWIDTH-1:0] Z ; // Final product + output [4:0] Flags ; + + // Internal Signals + wire [`EXPONENT:0] FinalE ; // Rounded exponent + wire [`MANTISSA:0] FinalM; + wire [`MANTISSA:0] PreShiftM; + + assign PreShiftM = GRS ? RoundMP : RoundM ; // Round up if R and (G or S) + + // Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow) + assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]) ; + + assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done + + assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]} ; // Putting the pieces together + assign Flags = InputExc[4:0]; + +endmodule + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Definition of a 16-bit floating point adder/subtractor +// This is a heavily modified version of: +// https://github.com/fbrosser/DSP48E1-FP/tree/master/src/FP_AddSub +// Original author: Fredrik Brosser +// Abridged by: Samidh Mehta +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// + +module FPAddSub( + clk, + rst, + a, + b, + operation, // 0 add, 1 sub + result, + flags + ); + + // Clock and reset + input clk ; // Clock signal + input rst ; // Reset (active high, resets pipeline registers) + + // Input ports + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + input operation ; // Operation select signal + + // Output ports + output [`DWIDTH-1:0] result ; // Result of the operation + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Pipeline Registers + //reg [79:0] pipe_1; // Pipeline register PreAlign->Align1 + reg [`DWIDTH*2+15:0] pipe_1; // Pipeline register PreAlign->Align1 + + //reg [67:0] pipe_2; // Pipeline register Align1->Align3 + reg [`MANTISSA*2+`EXPONENT+13:0] pipe_2; // Pipeline register Align1->Align3 + + //reg [76:0] pipe_3; 68 // Pipeline register Align1->Align3 + reg [`MANTISSA*2+`EXPONENT+14:0] pipe_3; // Pipeline register Align1->Align3 + + //reg [69:0] pipe_4; // Pipeline register Align3->Execute + reg [`MANTISSA*2+`EXPONENT+15:0] pipe_4; // Pipeline register Align3->Execute + + //reg [51:0] pipe_5; // Pipeline register Execute->Normalize + reg [`DWIDTH+`EXPONENT+11:0] pipe_5; // Pipeline register Execute->Normalize + + //reg [56:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + reg [`DWIDTH+`EXPONENT+16:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + + //reg [56:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + reg [`DWIDTH+`EXPONENT+16:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + + //reg [54:0] pipe_8; // Pipeline register NormalizeShift3->Round + reg [`EXPONENT*2+`MANTISSA+15:0] pipe_8; // Pipeline register NormalizeShift3->Round + + //reg [40:0] pipe_9; // Pipeline register NormalizeShift3->Round + reg [`DWIDTH+8:0] pipe_9; // Pipeline register NormalizeShift3->Round + + // Internal wires between modules + wire [`DWIDTH-2:0] Aout_0 ; // A - sign + wire [`DWIDTH-2:0] Bout_0 ; // B - sign + wire Opout_0 ; // A's sign + wire Sa_0 ; // A's sign + wire Sb_0 ; // B's sign + wire MaxAB_1 ; // Indicates the larger of A and B(0/A, 1/B) + wire [`EXPONENT-1:0] CExp_1 ; // Common Exponent + wire [4:0] Shift_1 ; // Number of steps to smaller mantissa shift right (align) + wire [`MANTISSA-1:0] Mmax_1 ; // Larger mantissa + wire [4:0] InputExc_0 ; // Input numbers are exceptions + wire [9:0] ShiftDet_0 ; + wire [`MANTISSA-1:0] MminS_1 ; // Smaller mantissa after 0/16 shift + wire [`MANTISSA:0] MminS_2 ; // Smaller mantissa after 0/4/8/12 shift + wire [`MANTISSA:0] Mmin_3 ; // Smaller mantissa after 0/1/2/3 shift + wire [`DWIDTH:0] Sum_4 ; + wire PSgn_4 ; + wire Opr_4 ; + wire [4:0] Shift_5 ; // Number of steps to shift sum left (normalize) + wire [`DWIDTH:0] SumS_5 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_6 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_7 ; // Sum after 0/16 shift + wire [`MANTISSA-1:0] NormM_8 ; // Normalized mantissa + wire [`EXPONENT:0] NormE_8; // Adjusted exponent + wire ZeroSum_8 ; // Zero flag + wire NegE_8 ; // Flag indicating negative exponent + wire R_8 ; // Round bit + wire S_8 ; // Final sticky bit + wire FG_8 ; // Final sticky bit + wire [`DWIDTH-1:0] P_int ; + wire EOF ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_PrealignModule PrealignModule + ( // Inputs + a, b, operation, + // Outputs + Sa_0, Sb_0, ShiftDet_0[9:0], InputExc_0[4:0], Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Opout_0) ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_AlignModule AlignModule + ( // Inputs + pipe_1[14+2*`DWIDTH:16+`DWIDTH], pipe_1[15+`DWIDTH:17], pipe_1[14:5], + // Outputs + CExp_1[`EXPONENT-1:0], MaxAB_1, Shift_1[4:0], MminS_1[`MANTISSA-1:0], Mmax_1[`MANTISSA-1:0]) ; + + // Alignment Shift Stage 1 + FPAddSub_AlignShift1 AlignShift1 + ( // Inputs + pipe_2[`MANTISSA-1:0], pipe_2[2*`MANTISSA+9:2*`MANTISSA+7], + // Outputs + MminS_2[`MANTISSA:0]) ; + + // Alignment Shift Stage 3 and compution of guard and sticky bits + FPAddSub_AlignShift2 AlignShift2 + ( // Inputs + pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+7:2*`MANTISSA+6], + // Outputs + Mmin_3[`MANTISSA:0]) ; + + // Perform mantissa addition + FPAddSub_ExecutionModule ExecutionModule + ( // Inputs + pipe_4[`MANTISSA*2+5:`MANTISSA+6], pipe_4[`MANTISSA:0], pipe_4[`MANTISSA*2+`EXPONENT+13], pipe_4[`MANTISSA*2+`EXPONENT+12], pipe_4[`MANTISSA*2+`EXPONENT+11], pipe_4[`MANTISSA*2+`EXPONENT+14], + // Outputs + Sum_4[`DWIDTH:0], PSgn_4, Opr_4) ; + + // Prepare normalization of result + FPAddSub_NormalizeModule NormalizeModule + ( // Inputs + pipe_5[`DWIDTH:0], + // Outputs + SumS_5[`DWIDTH:0], Shift_5[4:0]) ; + + // Normalization Shift Stage 1 + FPAddSub_NormalizeShift1 NormalizeShift1 + ( // Inputs + pipe_6[`DWIDTH:0], pipe_6[`DWIDTH+`EXPONENT+14:`DWIDTH+`EXPONENT+11], + // Outputs + SumS_7[`DWIDTH:0]) ; + + // Normalization Shift Stage 3 and final guard, sticky and round bits + FPAddSub_NormalizeShift2 NormalizeShift2 + ( // Inputs + pipe_7[`DWIDTH:0], pipe_7[`DWIDTH+`EXPONENT+5:`DWIDTH+6], pipe_7[`DWIDTH+`EXPONENT+15:`DWIDTH+`EXPONENT+11], + // Outputs + NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8, FG_8) ; + + // Round and put result together + FPAddSub_RoundModule RoundModule + ( // Inputs + pipe_8[3], pipe_8[4+`EXPONENT:4], pipe_8[`EXPONENT+`MANTISSA+4:5+`EXPONENT], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT*2+`MANTISSA+15], pipe_8[`EXPONENT*2+`MANTISSA+12], pipe_8[`EXPONENT*2+`MANTISSA+11], pipe_8[`EXPONENT*2+`MANTISSA+14], pipe_8[`EXPONENT*2+`MANTISSA+10], + // Outputs + P_int[`DWIDTH-1:0], EOF) ; + + // Check for exceptions + FPAddSub_ExceptionModule Exceptionmodule + ( // Inputs + pipe_9[8+`DWIDTH:9], pipe_9[8], pipe_9[7], pipe_9[6], pipe_9[5:1], pipe_9[0], + // Outputs + result[`DWIDTH-1:0], flags[4:0]) ; + + always @ (*) begin + if(rst) begin + pipe_1 = 0; + pipe_2 = 0; + pipe_3 = 0; + pipe_4 = 0; + pipe_5 = 0; + pipe_6 = 0; + pipe_7 = 0; + pipe_8 = 0; + pipe_9 = 0; + end + else begin + + pipe_1 = {Opout_0, Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Sa_0, Sb_0, ShiftDet_0[9:0], InputExc_0[4:0]} ; + // PIPE_2 : + //[67] operation + //[66] Sa_0 + //[65] Sb_0 + //[64] MaxAB_0 + //[63:56] CExp_0 + //[55:51] Shift_0 + //[50:28] Mmax_0 + //[27:23] InputExc_0 + //[22:0] MminS_1 + // + pipe_2 = {pipe_1[`DWIDTH*2+15], pipe_1[16:15], MaxAB_1, CExp_1[`EXPONENT-1:0], Shift_1[4:0], Mmax_1[`MANTISSA-1:0], pipe_1[4:0], MminS_1[`MANTISSA-1:0]} ; + // PIPE_3 : + //[68] operation + //[67] Sa_0 + //[66] Sb_0 + //[65] MaxAB_0 + //[64:57] CExp_0 + //[56:52] Shift_0 + //[51:29] Mmax_0 + //[28:24] InputExc_0 + //[23:0] MminS_1 + // + pipe_3 = {pipe_2[`MANTISSA*2+`EXPONENT+13:`MANTISSA], MminS_2[`MANTISSA:0]} ; + // PIPE_4 : + //[68] operation + //[67] Sa_0 + //[66] Sb_0 + //[65] MaxAB_0 + //[64:57] CExp_0 + //[56:52] Shift_0 + //[51:29] Mmax_0 + //[28:24] InputExc_0 + //[23:0] Mmin_3 + // + pipe_4 = {pipe_3[`MANTISSA*2+`EXPONENT+14:`MANTISSA+1], Mmin_3[`MANTISSA:0]} ; + // PIPE_5 : + //[51] operation + //[50] PSgn_4 + //[49] Opr_4 + //[48] Sa_0 + //[47] Sb_0 + //[46] MaxAB_0 + //[45:38] CExp_0 + //[37:33] InputExc_0 + //[32:0] Sum_4 + // + pipe_5 = {pipe_4[2*`MANTISSA+`EXPONENT+14], PSgn_4, Opr_4, pipe_4[2*`MANTISSA+`EXPONENT+13:2*`MANTISSA+11], pipe_4[`MANTISSA+5:`MANTISSA+1], Sum_4[`DWIDTH:0]} ; + // PIPE_6 : + //[56] operation + //[55:51] Shift_5 + //[50] PSgn_4 + //[49] Opr_4 + //[48] Sa_0 + //[47] Sb_0 + //[46] MaxAB_0 + //[45:38] CExp_0 + //[37:33] InputExc_0 + //[32:0] Sum_4 + // + pipe_6 = {pipe_5[`EXPONENT+`EXPONENT+11], Shift_5[4:0], pipe_5[`DWIDTH+`EXPONENT+10:`DWIDTH+1], SumS_5[`DWIDTH:0]} ; + // pipe_7 : + //[56] operation + //[55:51] Shift_5 + //[50] PSgn_4 + //[49] Opr_4 + //[48] Sa_0 + //[47] Sb_0 + //[46] MaxAB_0 + //[45:38] CExp_0 + //[37:33] InputExc_0 + //[32:0] Sum_4 + // + pipe_7 = {pipe_6[`DWIDTH+`EXPONENT+16:`DWIDTH+1], SumS_7[`DWIDTH:0]} ; + // pipe_8: + //[54] FG_8 + //[53] operation + //[52] PSgn_4 + //[51] Sa_0 + //[50] Sb_0 + //[49] MaxAB_0 + //[48:41] CExp_0 + //[40:36] InputExc_8 + //[35:13] NormM_8 + //[12:4] NormE_8 + //[3] ZeroSum_8 + //[2] NegE_8 + //[1] R_8 + //[0] S_8 + // + pipe_8 = {FG_8, pipe_7[`DWIDTH+`EXPONENT+16], pipe_7[`DWIDTH+`EXPONENT+10], pipe_7[`DWIDTH+`EXPONENT+8:`DWIDTH+1], NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8} ; + // pipe_9: + //[40:9] P_int + //[8] NegE_8 + //[7] R_8 + //[6] S_8 + //[5:1] InputExc_8 + //[0] EOF + // + pipe_9 = {P_int[`DWIDTH-1:0], pipe_8[2], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT+`MANTISSA+9:`EXPONENT+`MANTISSA+5], EOF} ; + end + end + +endmodule + +// Description: The pre-alignment module is responsible for taking the inputs +// apart and checking the parts for exceptions. +// The exponent difference is also calculated in this module. + +module FPAddSub_PrealignModule( + A, + B, + operation, + Sa, + Sb, + ShiftDet, + InputExc, + Aout, + Bout, + Opout + ); + + // Input ports + input [`DWIDTH-1:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] B ; // Input B, a 32-bit floating point number + input operation ; + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [9:0] ShiftDet ; + output [4:0] InputExc ; // Input numbers are exceptions + output [`DWIDTH-2:0] Aout ; + output [`DWIDTH-2:0] Bout ; + output Opout ; + + // Internal signals // If signal is high... + wire ANaN ; // A is a NaN (Not-a-Number) + wire BNaN ; // B is a NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`EXPONENT-1:0] DAB ; // ExpA - ExpB + wire [`EXPONENT-1:0] DBA ; // ExpB - ExpA + + assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + + // Put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + + //assign DAB = (A[30:23] - B[30:23]) ; + //assign DBA = (B[30:23] - A[30:23]) ; + assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1'b1) ; + assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1'b1) ; + + assign Sa = A[`DWIDTH-1] ; // A's sign bit + assign Sb = B[`DWIDTH-1] ; // B's sign bit + assign ShiftDet = {DBA[4:0], DAB[4:0]} ; // Shift data + assign Opout = operation ; + assign Aout = A[`DWIDTH-2:0] ; + assign Bout = B[`DWIDTH-2:0] ; + +endmodule + +// Description: The alignment module determines the larger input operand and +// sets the mantissas, shift and common exponent accordingly. + +module FPAddSub_AlignModule ( + A, + B, + ShiftDet, + CExp, + MaxAB, + Shift, + Mmin, + Mmax + ); + + // Input ports + input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-2:0] B ; // Input B, a 32-bit floating point number + input [9:0] ShiftDet ; + + // Output ports + output [`EXPONENT-1:0] CExp ; // Common Exponent + output MaxAB ; // Incidates larger of A and B (0/A, 1/B) + output [4:0] Shift ; // Number of steps to smaller mantissa shift right + output [`MANTISSA-1:0] Mmin ; // Smaller mantissa + output [`MANTISSA-1:0] Mmax ; // Larger mantissa + + // Internal signals + //wire BOF ; // Check for shifting overflow if B is larger + //wire AOF ; // Check for shifting overflow if A is larger + + assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]) ; + //assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits + //assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits + + // Determine final shift value + //assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ; + + assign Shift = MaxAB ? ShiftDet[9:5] : ShiftDet[4:0] ; + + // Take out smaller mantissa and append shift space + assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0] ; + + // Take out larger mantissa + assign Mmax = MaxAB ? B[`MANTISSA-1:0]: A[`MANTISSA-1:0] ; + + // Common exponent + assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]) ; + +endmodule + +// Description: Alignment shift stage 1, performs 16|12|8|4 shift + +module FPAddSub_AlignShift1( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`MANTISSA-1:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [2:0] Shift ; // Shift amount + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + // Internal signals + reg [`MANTISSA:0] Lvl1; + reg [`MANTISSA:0] Lvl2; + wire [2*`MANTISSA+1:0] Stage1; + integer i; // Loop variable + + always @(*) begin + // Rotate by 16? + //Lvl1 <= Shift[2] ? {17'b00000000000000001, MminP[22:16]} : {1'b1, MminP}; + Lvl1 <= Shift[2] ? {11'b0000000000} : {1'b1, MminP}; + + end + + assign Stage1 = {Lvl1, Lvl1}; + + always @(*) begin // Rotate {0 | 4 | 8 | 12} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl2 <= Stage1[`MANTISSA:0]; + // Rotate by 4 + 2'b01: Lvl2 <= Stage1[`MANTISSA+4:4]; + // Rotate by 8 + 2'b10: Lvl2 <= Stage1[`MANTISSA+8:8]; + // Rotate by 12 + 2'b11: Lvl2[`MANTISSA: 0] <= 0; + default: Lvl2[`MANTISSA: 0] <= 0; + endcase + end + + // Assign output to next shift stage + assign Mmin = Lvl2; + +endmodule + +// Description: Alignment shift stage 2, performs 3|2|1 shift + +module FPAddSub_AlignShift2( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`MANTISSA:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [1:0] Shift ; // Shift amount + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + // Internal Signal + reg [`MANTISSA:0] Lvl3; + wire [2*`MANTISSA+1:0] Stage2; + integer j; // Loop variable + + assign Stage2 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl3 <= Stage2[`MANTISSA:0]; + // Rotate by 1 + 2'b01: Lvl3 <= Stage2[`MANTISSA+1:1]; + // Rotate by 2 + 2'b10: Lvl3 <= Stage2[`MANTISSA+2:2]; + // Rotate by 3 + 2'b11: Lvl3 <= Stage2[`MANTISSA+3:3]; + default: Lvl3 <= Stage2[`MANTISSA+3:3]; + endcase + end + + // Assign output + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + +// Description: Module that executes the addition or subtraction on mantissas. + +module FPAddSub_ExecutionModule( + Mmax, + Mmin, + Sa, + Sb, + MaxAB, + OpMode, + Sum, + PSgn, + Opr + ); + + // Input ports + input [`MANTISSA-1:0] Mmax ; // The larger mantissa + input [`MANTISSA:0] Mmin ; // The smaller mantissa + input Sa ; // Sign bit of larger number + input Sb ; // Sign bit of smaller number + input MaxAB ; // Indicates the larger number (0/A, 1/B) + input OpMode ; // Operation to be performed (0/Add, 1/Sub) + + // Output ports + output [`DWIDTH:0] Sum ; // The result of the operation + output PSgn ; // The sign for the result + output Opr ; // The effective (performed) operation + + assign Opr = (OpMode^Sa^Sb); // Resolve sign to determine operation + + // Perform effective operation + assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, 5'b00000} - {Mmin, 5'b00000}) : ({1'b1, Mmax, 5'b00000} + {Mmin, 5'b00000}) ; + + // Assign result sign + assign PSgn = (MaxAB ? Sb : Sa) ; + +endmodule + +// Description: Determine the normalization shift amount and perform 16-shift + +module FPAddSub_NormalizeModule( + Sum, + Mmin, + Shift + ); + + // Input ports + input [`DWIDTH:0] Sum ; // Mantissa sum including hidden 1 and GRS + + // Output ports + output [`DWIDTH:0] Mmin ; // Mantissa after 16|0 shift + output [4:0] Shift ; // Shift amount + + // Determine normalization shift amount by finding leading nought + assign Shift = ( + Sum[16] ? 5'b00000 : + Sum[15] ? 5'b00001 : + Sum[14] ? 5'b00010 : + Sum[13] ? 5'b00011 : + Sum[12] ? 5'b00100 : + Sum[11] ? 5'b00101 : + Sum[10] ? 5'b00110 : + Sum[9] ? 5'b00111 : + Sum[8] ? 5'b01000 : + Sum[7] ? 5'b01001 : + Sum[6] ? 5'b01010 : + Sum[5] ? 5'b01011 : + Sum[4] ? 5'b01100 : 5'b01101 + // Sum[19] ? 5'b01101 : + // Sum[18] ? 5'b01110 : + // Sum[17] ? 5'b01111 : + // Sum[16] ? 5'b10000 : + // Sum[15] ? 5'b10001 : + // Sum[14] ? 5'b10010 : + // Sum[13] ? 5'b10011 : + // Sum[12] ? 5'b10100 : + // Sum[11] ? 5'b10101 : + // Sum[10] ? 5'b10110 : + // Sum[9] ? 5'b10111 : + // Sum[8] ? 5'b11000 : + // Sum[7] ? 5'b11001 : 5'b11010 + ); + + reg [`DWIDTH:0] Lvl1; + + always @(*) begin + // Rotate by 16? + Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum; + end + + // Assign outputs + assign Mmin = Lvl1; // Take out smaller mantissa + +endmodule + +// Description: Normalization shift stage 1, performs 12|8|4|3|2|1|0 shift + +module FPAddSub_NormalizeShift1( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`DWIDTH:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [3:0] Shift ; // Shift amount + + // Output ports + output [`DWIDTH:0] Mmin ; // The smaller mantissa + + reg [`DWIDTH:0] Lvl2; + wire [2*`DWIDTH+1:0] Stage1; + reg [`DWIDTH:0] Lvl3; + wire [2*`DWIDTH+1:0] Stage2; + integer i; // Loop variable + + assign Stage1 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 4 | 8 | 12} bits + case (Shift[3:2]) + // Rotate by 0 + 2'b00: //Lvl2 <= Stage1[`DWIDTH:0]; + begin Lvl2 = Stage1[`DWIDTH:0]; end + // Rotate by 4 + 2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-4]; end Lvl2[3:0] <= 0; end + begin Lvl2[`DWIDTH: (`DWIDTH-4)] = Stage1[3:0]; Lvl2[`DWIDTH-4-1:0] = Stage1[`DWIDTH-4]; end + // Rotate by 8 + 2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-8]; end Lvl2[7:0] <= 0; end + begin Lvl2[`DWIDTH: (`DWIDTH-8)] = Stage1[3:0]; Lvl2[`DWIDTH-8-1:0] = Stage1[`DWIDTH-8]; end + // Rotate by 12 + 2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end + begin Lvl2[`DWIDTH: (`DWIDTH-12)] = Stage1[3:0]; Lvl2[`DWIDTH-12-1:0] = Stage1[`DWIDTH-12]; end + endcase + end + + assign Stage2 = {Lvl2, Lvl2}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: //Lvl3 <= Stage2[`DWIDTH:0]; + begin Lvl3 = Stage2[`DWIDTH:0]; end + // Rotate by 1 + 2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-1]; end Lvl3[0] <= 0; end + begin Lvl3[`DWIDTH: (`DWIDTH-1)] = Stage2[3:0]; Lvl3[`DWIDTH-1-1:0] = Stage2[`DWIDTH-1]; end + // Rotate by 2 + 2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-2]; end Lvl3[1:0] <= 0; end + begin Lvl3[`DWIDTH: (`DWIDTH-2)] = Stage2[3:0]; Lvl3[`DWIDTH-2-1:0] = Stage2[`DWIDTH-2]; end + // Rotate by 3 + 2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end + begin Lvl3[`DWIDTH: (`DWIDTH-3)] = Stage2[3:0]; Lvl3[`DWIDTH-3-1:0] = Stage2[`DWIDTH-3]; end + endcase + end + + // Assign outputs + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + +// Description: Normalization shift stage 2, calculates post-normalization +// mantissa and exponent, as well as the bits used in rounding + +module FPAddSub_NormalizeShift2( + PSSum, + CExp, + Shift, + NormM, + NormE, + ZeroSum, + NegE, + R, + S, + FG + ); + + // Input ports + input [`DWIDTH:0] PSSum ; // The Pre-Shift-Sum + input [`EXPONENT-1:0] CExp ; + input [4:0] Shift ; // Amount to be shifted + + // Output ports + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output [`EXPONENT:0] NormE ; // Adjusted exponent + output ZeroSum ; // Zero flag + output NegE ; // Flag indicating negative exponent + output R ; // Round bit + output S ; // Final sticky bit + output FG ; + + // Internal signals + wire MSBShift ; // Flag indicating that a second shift is needed + wire [`EXPONENT:0] ExpOF ; // MSB set in sum indicates overflow + wire [`EXPONENT:0] ExpOK ; // MSB not set, no adjustment + + // Calculate normalized exponent and mantissa, check for all-zero sum + assign MSBShift = PSSum[`DWIDTH] ; // Check MSB in unnormalized sum + assign ZeroSum = ~|PSSum ; // Check for all zero sum + assign ExpOK = CExp - Shift ; // Adjust exponent for new normalized mantissa + assign NegE = ExpOK[`EXPONENT] ; // Check for exponent overflow + assign ExpOF = CExp - Shift + 1'b1 ; // If MSB set, add one to exponent(x2) + assign NormE = MSBShift ? ExpOF : ExpOK ; // Check for exponent overflow + assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1] ; // The new, normalized mantissa + + // Also need to compute sticky and round bits for the rounding stage + assign FG = PSSum[`EXPONENT] ; + assign R = PSSum[`EXPONENT-1] ; + assign S = |PSSum[`EXPONENT-2:0] ; + +endmodule + +// Description: Performs 'Round to nearest, tie to even'-rounding on the +// normalized mantissa according to the G, R, S bits. Calculates +// final result and checks for exponent overflow. + +module FPAddSub_RoundModule( + ZeroSum, + NormE, + NormM, + R, + S, + G, + Sa, + Sb, + Ctrl, + MaxAB, + Z, + EOF + ); + + // Input ports + input ZeroSum ; // Sum is zero + input [`EXPONENT:0] NormE ; // Normalized exponent + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input R ; // Round bit + input S ; // Sticky bit + input G ; + input Sa ; // A's sign bit + input Sb ; // B's sign bit + input Ctrl ; // Control bit (operation) + input MaxAB ; + + // Output ports + output [`DWIDTH-1:0] Z ; // Final result + output EOF ; + + // Internal signals + wire [`MANTISSA:0] RoundUpM ; // Rounded up sum with room for overflow + wire [`MANTISSA-1:0] RoundM ; // The final rounded sum + wire [`EXPONENT:0] RoundE ; // Rounded exponent (note extra bit due to poential overflow ) + wire RoundUp ; // Flag indicating that the sum should be rounded up + wire FSgn; + wire ExpAdd ; // May have to add 1 to compensate for overflow + wire RoundOF ; // Rounding overflow + + // The cases where we need to round upwards (= adding one) in Round to nearest, tie to even + assign RoundUp = (G & ((R | S) | NormM[0])) ; + + // Note that in the other cases (rounding down), the sum is already 'rounded' + assign RoundUpM = (NormM + 1'b1) ; // The sum, rounded up by 1 + assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM) ; // Compute final mantissa + assign RoundOF = RoundUp & RoundUpM[`MANTISSA] ; // Check for overflow when rounding up + + // Calculate post-rounding exponent + assign ExpAdd = (RoundOF ? 1'b1 : 1'b0) ; // Add 1 to exponent to compensate for overflow + assign RoundE = ZeroSum ? 5'b00000 : (NormE + ExpAdd) ; // Final exponent + + // If zero, need to determine sign according to rounding + assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ; + + // Assign final result + assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]} ; + + // Indicate exponent overflow + assign EOF = RoundE[`EXPONENT]; + +endmodule + +// Description: Check the final result for exception conditions and set +// flags accordingly. + +module FPAddSub_ExceptionModule( + Z, + NegE, + R, + S, + InputExc, + EOF, + P, + Flags + ); + + // Input ports + input [`DWIDTH-1:0] Z ; // Final product + input NegE ; // Negative exponent? + input R ; // Round bit + input S ; // Sticky bit + input [4:0] InputExc ; // Exceptions in inputs A and B + input EOF ; + + // Output ports + output [`DWIDTH-1:0] P ; // Final result + output [4:0] Flags ; // Exception flags + + // Internal signals + wire Overflow ; // Overflow flag + wire Underflow ; // Underflow flag + wire DivideByZero ; // Divide-by-Zero flag (always 0 in Add/Sub) + wire Invalid ; // Invalid inputs or result + wire Inexact ; // Result is inexact because of rounding + + // Exception flags + + // Result is too big to be represented + assign Overflow = EOF | InputExc[1] | InputExc[0] ; + + // Result is too small to be represented + assign Underflow = NegE & (R | S); + + // Infinite result computed exactly from finite operands + assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0]; + + // Invalid inputs or operation + assign Invalid = |(InputExc[4:2]) ; + + // Inexact answer due to rounding, overflow or underflow + assign Inexact = (R | S) | Overflow | Underflow; + + // Put pieces together to form final result + assign P = Z ; + + // Collect exception flags + assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact} ; + +endmodule +`endif + + diff --git a/designs/koios/conv_layer_hls/conv_layer_random.sv b/designs/koios/conv_layer_hls/conv_layer_random.sv new file mode 100644 index 000000000..fc1c49b28 --- /dev/null +++ b/designs/koios/conv_layer_hls/conv_layer_random.sv @@ -0,0 +1,447 @@ +/* +Random inputs to hls conv layer +*/ + +`include "../../random_number_generator.sv" + +module conv_layer_random ( + input logic clk, + input logic ap_rst, + output logic in_data_ce0_0, + output logic in_data_we0_0, + output logic in_data_ce1_0, + output logic in_data_we1_0, + output logic out_data_we1_2, + input logic ap_start_2, + input logic in_data_empty_n_2, + output logic in_data_read_2, + input logic out_data_full_n_2, + output logic out_data_write_2, + output logic ap_done_2, + output logic ap_ready_2, + output logic ap_idle_2, + input logic ap_continue_2, + output logic filter_data_ce0_0, + output logic out_data_we1_0, + input logic ap_start_0, + input logic in_data_empty_n_0, + output logic in_data_read_0, + input logic out_data_full_n_0, + output logic out_data_write_0, + output logic ap_done_0, + output logic ap_ready_0, + output logic ap_idle_0, + input logic ap_continue_0, + output logic filter_data_we0_0, + output logic filter_data_ce1_0, + output logic filter_data_we1_0, + output logic out_data_ce0_0, + output logic out_data_we0_0, + output logic out_data_ce1_0, + input logic ap_start_1, + input logic in_data_empty_n_1, + output logic in_data_read_1, + input logic out_data_full_n_1, + output logic out_data_write_1, + output logic ap_done_1, + output logic ap_ready_1, + output logic ap_idle_1, + input logic ap_continue_1, + output logic in_data_ce0_1, + output logic in_data_we0_1, + output logic in_data_ce1_1, + output logic in_data_we1_1, + output logic filter_data_ce0_1, + output logic filter_data_we0_1, + output logic filter_data_ce1_1, + output logic filter_data_we1_1, + output logic out_data_ce0_1, + output logic out_data_we0_1, + output logic out_data_we1_1, + output logic out_data_ce1_1, + output logic in_data_we0_2, + output logic in_data_ce0_2, + output logic in_data_ce1_2, + output logic in_data_we1_2, + output logic filter_data_ce0_2, + output logic filter_data_we1_2, + output logic out_data_we0_2, + output logic filter_data_we0_2, + output logic filter_data_ce1_2, + output logic out_data_ce1_2, + output logic out_data_ce0_2, + input logic [2:0] data_out_select0, + output logic [8:0] filter_data, + output logic [11:0] out_data_addr, + output logic [14:0] in_data_addr, + output logic [15:0] filter_data_d_out, + input logic [3:0] data_out_select1, + output logic [7:0] in_data, + input logic [4:0] data_out_select2, + output logic [7:0] out_data +); + +logic [8:0] filter_data_address[5:0]; +assign filter_data = filter_data_address[data_out_select0[2:0]]; + +logic [11:0] out_data_address[5:0]; +assign out_data_addr = out_data_addr[data_out_select0[2:0]]; + +logic [14:0] in_data_address[5:0]; +assign in_data_addr = in_data_address[data_out_select0[2:0]]; + +logic [15:0] filter_data_d[5:0]; +assign filter_data_d_out = filter_data_d[data_out_select0[2:0]]; + +logic [63:0] in_data_d[5:0]; +logic [63:0] in_data_row; +assign in_data_row = in_data_d[data_out_select0[2:0]]; +always_comb begin + case (data_out_select1[3:0]) + 4'd0: in_data = in_data_row[7:0]; + 4'd1: in_data = in_data_row[15:8]; + 4'd2: in_data = in_data_row[23:16]; + 4'd3: in_data = in_data_row[31:24]; + 4'd4: in_data = in_data_row[39:32]; + 4'd5: in_data = in_data_row[47:40]; + 4'd6: in_data = in_data_row[55:48]; + 4'd7: in_data = in_data_row[63:56]; + default: in_data = 8'd0; + endcase +end + +logic [255:0] out_data_d[5:0]; +logic [255:0] out_data_row; +assign out_data_row = out_data_d[data_out_select0[2:0]]; +always_comb begin + case (data_out_select2[4:0]) + 8'd0: out_data = out_data_row[7:0]; + 8'd1: out_data = out_data_row[15:8]; + 8'd2: out_data = out_data_row[23:16]; + 8'd3: out_data = out_data_row[31:24]; + 8'd4: out_data = out_data_row[39:32]; + 8'd5: out_data = out_data_row[47:40]; + 8'd6: out_data = out_data_row[55:48]; + 8'd7: out_data = out_data_row[63:56]; + 8'd8: out_data = out_data_row[71:64]; + 8'd9: out_data = out_data_row[79:72]; + 8'd10: out_data = out_data_row[87:80]; + 8'd11: out_data = out_data_row[95:88]; + 8'd12: out_data = out_data_row[103:96]; + 8'd13: out_data = out_data_row[111:104]; + 8'd14: out_data = out_data_row[119:112]; + 8'd15: out_data = out_data_row[127:120]; + 8'd16: out_data = out_data_row[135:128]; + 8'd17: out_data = out_data_row[143:136]; + 8'd18: out_data = out_data_row[151:144]; + 8'd19: out_data = out_data_row[159:152]; + 8'd20: out_data = out_data_row[167:160]; + 8'd21: out_data = out_data_row[175:168]; + 8'd22: out_data = out_data_row[183:176]; + 8'd23: out_data = out_data_row[191:184]; + 8'd24: out_data = out_data_row[199:192]; + 8'd25: out_data = out_data_row[207:200]; + 8'd26: out_data = out_data_row[215:208]; + 8'd27: out_data = out_data_row[223:216]; + 8'd28: out_data = out_data_row[231:224]; + 8'd29: out_data = out_data_row[239:232]; + 8'd30: out_data = out_data_row[247:240]; + 8'd31: out_data = out_data_row[255:248]; + default: out_data = 8'd0; + endcase +end + + +logic [63:0] in_data_q0_0; +RandomNumberGenerator #( + .RANDOM_WIDTH(64), + .SEED(0) +) rng_in_data_q0_0 ( + .clk(clk), + .reset(ap_rst), + .random_number(in_data_q0_0) +); + +logic [63:0] in_data_q1_0; +RandomNumberGenerator #( + .RANDOM_WIDTH(64), + .SEED(0) +) rng_in_data_q1_0 ( + .clk(clk), + .reset(ap_rst), + .random_number(in_data_q1_0) +); + +logic [15:0] filter_data_q0_0; +RandomNumberGenerator #( + .RANDOM_WIDTH(16), + .SEED(0) +) rng_filter_data_q0_0 ( + .clk(clk), + .reset(ap_rst), + .random_number(filter_data_q0_0) +); + +logic [15:0] filter_data_q1_0; +RandomNumberGenerator #( + .RANDOM_WIDTH(16), + .SEED(0) +) rng_filter_data_q1_0 ( + .clk(clk), + .reset(ap_rst), + .random_number(filter_data_q1_0) +); + +logic [255:0] out_data_q0_0; +RandomNumberGenerator #( + .RANDOM_WIDTH(256), + .SEED(0) +) rng_out_data_q0_0 ( + .clk(clk), + .reset(ap_rst), + .random_number(out_data_q0_0) +); + +logic [255:0] out_data_q1_0; +RandomNumberGenerator #( + .RANDOM_WIDTH(256), + .SEED(0) +) rng_out_data_q1_0 ( + .clk(clk), + .reset(ap_rst), + .random_number(out_data_q1_0) +); + +logic [63:0] in_data_q1_1; +RandomNumberGenerator #( + .RANDOM_WIDTH(64), + .SEED(0) +) rng_in_data_q1_1 ( + .clk(clk), + .reset(ap_rst), + .random_number(in_data_q1_1) +); +logic [63:0] in_data_q0_1; +RandomNumberGenerator #( + .RANDOM_WIDTH(64), + .SEED(0) +) rng_in_data_q0_1 ( + .clk(clk), + .reset(ap_rst), + .random_number(in_data_q0_1) +); +logic [15:0] filter_data_q0_1; +RandomNumberGenerator #( + .RANDOM_WIDTH(16), + .SEED(0) +) rng_filter_data_q0_1 ( + .clk(clk), + .reset(ap_rst), + .random_number(filter_data_q0_1) +); +logic [15:0] filter_data_q1_1; +RandomNumberGenerator #( + .RANDOM_WIDTH(16), + .SEED(0) +) rng_filter_data_q1_1 ( + .clk(clk), + .reset(ap_rst), + .random_number(filter_data_q0_1) +); +logic [255:0] out_data_q0_1; +RandomNumberGenerator #( + .RANDOM_WIDTH(256), + .SEED(0) +) rng_out_data_q0_1 ( + .clk(clk), + .reset(ap_rst), + .random_number(filter_data_q0_1) +); +logic [255:0] out_data_q1_1; +RandomNumberGenerator #( + .RANDOM_WIDTH(256), + .SEED(0) +) rng_out_data_q1_1 ( + .clk(clk), + .reset(ap_rst), + .random_number(filter_data_q0_1) +); + +logic [63:0] in_data_q0_2; +RandomNumberGenerator #( + .RANDOM_WIDTH(64), + .SEED(0) +) rng_in_data_q0_2 ( + .clk(clk), + .reset(ap_rst), + .random_number(in_data_q0_2) +); +logic [63:0] in_data_q1_2; +RandomNumberGenerator #( + .RANDOM_WIDTH(64), + .SEED(0) +) rng_in_data_q1_2 ( + .clk(clk), + .reset(ap_rst), + .random_number(in_data_q1_2) +); +logic [15:0] filter_data_q0_2; +RandomNumberGenerator #( + .RANDOM_WIDTH(16), + .SEED(0) +) rng_filter_data_q0_2 ( + .clk(clk), + .reset(ap_rst), + .random_number(filter_data_q0_2) +); +logic [15:0] filter_data_q1_2; +RandomNumberGenerator #( + .RANDOM_WIDTH(16), + .SEED(0) +) rng_filter_data_q1_2 ( + .clk(clk), + .reset(ap_rst), + .random_number(filter_data_q1_2) +); +logic [255:0] out_data_q0_2; +RandomNumberGenerator #( + .RANDOM_WIDTH(256), + .SEED(0) +) rng_out_data_q0_2 ( + .clk(clk), + .reset(ap_rst), + .random_number(out_data_q0_2) +); +logic [255:0] out_data_q1_2; +RandomNumberGenerator #( + .RANDOM_WIDTH(256), + .SEED(0) +) rng_out_data_q1_2 ( + .clk(clk), + .reset(ap_rst), + .random_number(out_data_q1_2) +); + +top ( + clk, + ap_rst, + in_data_address[0], + in_data_address[1], + in_data_address[2], + in_data_ce0_0, + in_data_ce0_1, + in_data_ce0_2, + in_data_d[0], + in_data_d[1], + in_data_d[2], + in_data_q0_0, + in_data_q0_1, + in_data_q0_2, + in_data_we0_0, + in_data_we0_1, + in_data_we0_2, + in_data_address[3], + in_data_address[4], + in_data_address[5], + in_data_ce1_0, + in_data_ce1_1, + in_data_ce1_2, + in_data_d[3], + in_data_d[4], + in_data_d[5], + in_data_q1_0, + in_data_q1_1, + in_data_q1_2, + in_data_we1_0, + in_data_we1_1, + in_data_we1_2, + filter_data_address[0], + filter_data_address[1], + filter_data_address[2], + filter_data_ce0_0, + filter_data_ce0_1, + filter_data_ce0_2, + filter_data_d[0], + filter_data_d[1], + filter_data_d[2], + filter_data_q0_0, + filter_data_q0_1, + filter_data_q0_2, + filter_data_we0_0, + filter_data_we0_1, + filter_data_we0_2, + filter_data_address[3], + filter_data_address[4], + filter_data_address[5], + filter_data_ce1_0, + filter_data_ce1_1, + filter_data_ce1_2, + filter_data_d[3], + filter_data_d[4], + filter_data_d[5], + filter_data_q1_0, + filter_data_q1_1, + filter_data_q1_2, + filter_data_we1_0, + filter_data_we1_1, + filter_data_we1_2, + out_data_address[0], + out_data_address[1], + out_data_address[2], + out_data_ce0_0, + out_data_ce0_1, + out_data_ce0_2, + out_data_d[0], + out_data_d[1], + out_data_d[2], + out_data_q0_0, + out_data_q0_1, + out_data_q0_2, + out_data_we0_0, + out_data_we0_1, + out_data_we0_2, + out_data_address[4], + out_data_address[5], + out_data_address[6], + out_data_ce1_0, + out_data_ce1_1, + out_data_ce1_2, + out_data_d[3], + out_data_d[4], + out_data_d[5], + out_data_q1_0, + out_data_q1_1, + out_data_q1_2, + out_data_we1_0, + out_data_we1_1, + out_data_we1_2, + ap_start_0, + ap_start_1, + ap_start_2, + in_data_empty_n_0, + in_data_empty_n_1, + in_data_empty_n_2, + in_data_read_0, + in_data_read_1, + in_data_read_2, + out_data_full_n_0, + out_data_full_n_1, + out_data_full_n_2, + out_data_write_0, + out_data_write_1, + out_data_write_2, + ap_done_0, + ap_done_1, + ap_done_2, + ap_ready_0, + ap_ready_1, + ap_ready_2, + ap_idle_0, + ap_idle_1, + ap_idle_2, + ap_continue_0, + ap_continue_1, + ap_continue_2 +); + +endmodule \ No newline at end of file diff --git a/designs/koios/conv_layer_hls/design.yaml b/designs/koios/conv_layer_hls/design.yaml new file mode 100644 index 000000000..c2b3b24b6 --- /dev/null +++ b/designs/koios/conv_layer_hls/design.yaml @@ -0,0 +1 @@ +top: conv_layer_random diff --git a/designs/koios/dla_like.large/design.yaml b/designs/koios/dla_like.large/design.yaml new file mode 100644 index 000000000..fd623a753 --- /dev/null +++ b/designs/koios/dla_like.large/design.yaml @@ -0,0 +1 @@ +top: dla_random diff --git a/designs/koios/dla_like.large/dla_like.large.v b/designs/koios/dla_like.large/dla_like.large.v new file mode 100644 index 000000000..49d597755 --- /dev/null +++ b/designs/koios/dla_like.large/dla_like.large.v @@ -0,0 +1,69918 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Andrew Boutros +////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +//A CNN accelerator overlay called DLA from Intel based on the paper: +//U. Aydonat et al., “An OpenCL Deep Learning Accelerator on Arria10,” in International Symposium on Field-Programmable Gate Arrays (FPGA), 2017. +//This design was also used in this paper: +//A. Boutros et al., “You Cannot Improve What You Do Not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference,” ACM Transactions on Reconfigurable Technology Systems (TRETS), vol. 11, no. 3, 2018 +// +//Some properties of the design are: +//1. 16-bit fixed point for activations, 8-bit fixed point for weights +//2. Winograd Transform based convolution. +//3. 2D mac array. Centralized weight buffer for processing elements. +//4. Double-buffering after each layer. +/////////////////////////////////////////////////////////////////////////////// +module DLA ( + input clk, + input i_reset, + input i_ddr_wen_0_0, + input [15:0] i_ddr_0_0, + output o_dummy_out_0_0, + input i_ddr_wen_0_1, + input [15:0] i_ddr_0_1, + output o_dummy_out_0_1, + input i_ddr_wen_0_2, + input [15:0] i_ddr_0_2, + output o_dummy_out_0_2, + input i_ddr_wen_0_3, + input [15:0] i_ddr_0_3, + output o_dummy_out_0_3, + input i_ddr_wen_0_4, + input [15:0] i_ddr_0_4, + output o_dummy_out_0_4, + input i_ddr_wen_0_5, + input [15:0] i_ddr_0_5, + output o_dummy_out_0_5, + input i_ddr_wen_0_6, + input [15:0] i_ddr_0_6, + output o_dummy_out_0_6, + input i_ddr_wen_0_7, + input [15:0] i_ddr_0_7, + output o_dummy_out_0_7, + input i_ddr_wen_1_0, + input [15:0] i_ddr_1_0, + output o_dummy_out_1_0, + input i_ddr_wen_1_1, + input [15:0] i_ddr_1_1, + output o_dummy_out_1_1, + input i_ddr_wen_1_2, + input [15:0] i_ddr_1_2, + output o_dummy_out_1_2, + input i_ddr_wen_1_3, + input [15:0] i_ddr_1_3, + output o_dummy_out_1_3, + input i_ddr_wen_1_4, + input [15:0] i_ddr_1_4, + output o_dummy_out_1_4, + input i_ddr_wen_1_5, + input [15:0] i_ddr_1_5, + output o_dummy_out_1_5, + input i_ddr_wen_1_6, + input [15:0] i_ddr_1_6, + output o_dummy_out_1_6, + input i_ddr_wen_1_7, + input [15:0] i_ddr_1_7, + output o_dummy_out_1_7, + input i_ddr_wen_2_0, + input [15:0] i_ddr_2_0, + output o_dummy_out_2_0, + input i_ddr_wen_2_1, + input [15:0] i_ddr_2_1, + output o_dummy_out_2_1, + input i_ddr_wen_2_2, + input [15:0] i_ddr_2_2, + output o_dummy_out_2_2, + input i_ddr_wen_2_3, + input [15:0] i_ddr_2_3, + output o_dummy_out_2_3, + input i_ddr_wen_2_4, + input [15:0] i_ddr_2_4, + output o_dummy_out_2_4, + input i_ddr_wen_2_5, + input [15:0] i_ddr_2_5, + output o_dummy_out_2_5, + input i_ddr_wen_2_6, + input [15:0] i_ddr_2_6, + output o_dummy_out_2_6, + input i_ddr_wen_2_7, + input [15:0] i_ddr_2_7, + output o_dummy_out_2_7, + input i_ddr_wen_3_0, + input [15:0] i_ddr_3_0, + output o_dummy_out_3_0, + input i_ddr_wen_3_1, + input [15:0] i_ddr_3_1, + output o_dummy_out_3_1, + input i_ddr_wen_3_2, + input [15:0] i_ddr_3_2, + output o_dummy_out_3_2, + input i_ddr_wen_3_3, + input [15:0] i_ddr_3_3, + output o_dummy_out_3_3, + input i_ddr_wen_3_4, + input [15:0] i_ddr_3_4, + output o_dummy_out_3_4, + input i_ddr_wen_3_5, + input [15:0] i_ddr_3_5, + output o_dummy_out_3_5, + input i_ddr_wen_3_6, + input [15:0] i_ddr_3_6, + output o_dummy_out_3_6, + input i_ddr_wen_3_7, + input [15:0] i_ddr_3_7, + output o_dummy_out_3_7, + input i_ddr_wen_4_0, + input [15:0] i_ddr_4_0, + output o_dummy_out_4_0, + input i_ddr_wen_4_1, + input [15:0] i_ddr_4_1, + output o_dummy_out_4_1, + input i_ddr_wen_4_2, + input [15:0] i_ddr_4_2, + output o_dummy_out_4_2, + input i_ddr_wen_4_3, + input [15:0] i_ddr_4_3, + output o_dummy_out_4_3, + input i_ddr_wen_4_4, + input [15:0] i_ddr_4_4, + output o_dummy_out_4_4, + input i_ddr_wen_4_5, + input [15:0] i_ddr_4_5, + output o_dummy_out_4_5, + input i_ddr_wen_4_6, + input [15:0] i_ddr_4_6, + output o_dummy_out_4_6, + input i_ddr_wen_4_7, + input [15:0] i_ddr_4_7, + output o_dummy_out_4_7, + input i_ddr_wen_5_0, + input [15:0] i_ddr_5_0, + output o_dummy_out_5_0, + input i_ddr_wen_5_1, + input [15:0] i_ddr_5_1, + output o_dummy_out_5_1, + input i_ddr_wen_5_2, + input [15:0] i_ddr_5_2, + output o_dummy_out_5_2, + input i_ddr_wen_5_3, + input [15:0] i_ddr_5_3, + output o_dummy_out_5_3, + input i_ddr_wen_5_4, + input [15:0] i_ddr_5_4, + output o_dummy_out_5_4, + input i_ddr_wen_5_5, + input [15:0] i_ddr_5_5, + output o_dummy_out_5_5, + input i_ddr_wen_5_6, + input [15:0] i_ddr_5_6, + output o_dummy_out_5_6, + input i_ddr_wen_5_7, + input [15:0] i_ddr_5_7, + output o_dummy_out_5_7, + output o_valid +); + +wire [15:0] f_buffer_pe_0_0; +wire valid_buff_0_0; +wire [15:0] f_buffer_pe_0_1; +wire valid_buff_0_1; +wire [15:0] f_buffer_pe_0_2; +wire valid_buff_0_2; +wire [15:0] f_buffer_pe_0_3; +wire valid_buff_0_3; +wire [15:0] f_buffer_pe_0_4; +wire valid_buff_0_4; +wire [15:0] f_buffer_pe_0_5; +wire valid_buff_0_5; +wire [15:0] f_buffer_pe_0_6; +wire valid_buff_0_6; +wire [15:0] f_buffer_pe_0_7; +wire valid_buff_0_7; +wire [15:0] f_buffer_pe_1_0; +wire valid_buff_1_0; +wire [15:0] f_buffer_pe_1_1; +wire valid_buff_1_1; +wire [15:0] f_buffer_pe_1_2; +wire valid_buff_1_2; +wire [15:0] f_buffer_pe_1_3; +wire valid_buff_1_3; +wire [15:0] f_buffer_pe_1_4; +wire valid_buff_1_4; +wire [15:0] f_buffer_pe_1_5; +wire valid_buff_1_5; +wire [15:0] f_buffer_pe_1_6; +wire valid_buff_1_6; +wire [15:0] f_buffer_pe_1_7; +wire valid_buff_1_7; +wire [15:0] f_buffer_pe_2_0; +wire valid_buff_2_0; +wire [15:0] f_buffer_pe_2_1; +wire valid_buff_2_1; +wire [15:0] f_buffer_pe_2_2; +wire valid_buff_2_2; +wire [15:0] f_buffer_pe_2_3; +wire valid_buff_2_3; +wire [15:0] f_buffer_pe_2_4; +wire valid_buff_2_4; +wire [15:0] f_buffer_pe_2_5; +wire valid_buff_2_5; +wire [15:0] f_buffer_pe_2_6; +wire valid_buff_2_6; +wire [15:0] f_buffer_pe_2_7; +wire valid_buff_2_7; +wire [15:0] f_buffer_pe_3_0; +wire valid_buff_3_0; +wire [15:0] f_buffer_pe_3_1; +wire valid_buff_3_1; +wire [15:0] f_buffer_pe_3_2; +wire valid_buff_3_2; +wire [15:0] f_buffer_pe_3_3; +wire valid_buff_3_3; +wire [15:0] f_buffer_pe_3_4; +wire valid_buff_3_4; +wire [15:0] f_buffer_pe_3_5; +wire valid_buff_3_5; +wire [15:0] f_buffer_pe_3_6; +wire valid_buff_3_6; +wire [15:0] f_buffer_pe_3_7; +wire valid_buff_3_7; +wire [15:0] f_buffer_pe_4_0; +wire valid_buff_4_0; +wire [15:0] f_buffer_pe_4_1; +wire valid_buff_4_1; +wire [15:0] f_buffer_pe_4_2; +wire valid_buff_4_2; +wire [15:0] f_buffer_pe_4_3; +wire valid_buff_4_3; +wire [15:0] f_buffer_pe_4_4; +wire valid_buff_4_4; +wire [15:0] f_buffer_pe_4_5; +wire valid_buff_4_5; +wire [15:0] f_buffer_pe_4_6; +wire valid_buff_4_6; +wire [15:0] f_buffer_pe_4_7; +wire valid_buff_4_7; +wire [15:0] f_buffer_pe_5_0; +wire valid_buff_5_0; +wire [15:0] f_buffer_pe_5_1; +wire valid_buff_5_1; +wire [15:0] f_buffer_pe_5_2; +wire valid_buff_5_2; +wire [15:0] f_buffer_pe_5_3; +wire valid_buff_5_3; +wire [15:0] f_buffer_pe_5_4; +wire valid_buff_5_4; +wire [15:0] f_buffer_pe_5_5; +wire valid_buff_5_5; +wire [15:0] f_buffer_pe_5_6; +wire valid_buff_5_6; +wire [15:0] f_buffer_pe_5_7; +wire valid_buff_5_7; +wire ready; +wire [15:0] f_winograd_0_0; +wire [15:0] f_winograd_0_1; +wire [15:0] f_winograd_0_2; +wire [15:0] f_winograd_0_3; +wire [15:0] f_winograd_0_4; +wire [15:0] f_winograd_0_5; +wire [15:0] f_winograd_1_0; +wire [15:0] f_winograd_1_1; +wire [15:0] f_winograd_1_2; +wire [15:0] f_winograd_1_3; +wire [15:0] f_winograd_1_4; +wire [15:0] f_winograd_1_5; +wire [15:0] f_winograd_2_0; +wire [15:0] f_winograd_2_1; +wire [15:0] f_winograd_2_2; +wire [15:0] f_winograd_2_3; +wire [15:0] f_winograd_2_4; +wire [15:0] f_winograd_2_5; +wire [15:0] f_winograd_3_0; +wire [15:0] f_winograd_3_1; +wire [15:0] f_winograd_3_2; +wire [15:0] f_winograd_3_3; +wire [15:0] f_winograd_3_4; +wire [15:0] f_winograd_3_5; +wire [15:0] f_winograd_4_0; +wire [15:0] f_winograd_4_1; +wire [15:0] f_winograd_4_2; +wire [15:0] f_winograd_4_3; +wire [15:0] f_winograd_4_4; +wire [15:0] f_winograd_4_5; +wire [15:0] f_winograd_5_0; +wire [15:0] f_winograd_5_1; +wire [15:0] f_winograd_5_2; +wire [15:0] f_winograd_5_3; +wire [15:0] f_winograd_5_4; +wire [15:0] f_winograd_5_5; +wire [15:0] f_winograd_6_0; +wire [15:0] f_winograd_6_1; +wire [15:0] f_winograd_6_2; +wire [15:0] f_winograd_6_3; +wire [15:0] f_winograd_6_4; +wire [15:0] f_winograd_6_5; +wire [15:0] f_winograd_7_0; +wire [15:0] f_winograd_7_1; +wire [15:0] f_winograd_7_2; +wire [15:0] f_winograd_7_3; +wire [15:0] f_winograd_7_4; +wire [15:0] f_winograd_7_5; +wire winograd_valid_0; +wire winograd_valid_1; +wire winograd_valid_2; +wire winograd_valid_3; +wire winograd_valid_4; +wire winograd_valid_5; +wire winograd_valid_6; +wire winograd_valid_7; + +// PE Wires +wire [15:0] daisy_chain_0_0_0; +wire [15:0] daisy_chain_0_0_1; +wire [15:0] daisy_chain_0_0_2; +wire [15:0] daisy_chain_0_0_3; +wire [15:0] daisy_chain_0_0_4; +wire [15:0] daisy_chain_0_0_5; +wire [15:0] daisy_chain_0_1_0; +wire [15:0] daisy_chain_0_1_1; +wire [15:0] daisy_chain_0_1_2; +wire [15:0] daisy_chain_0_1_3; +wire [15:0] daisy_chain_0_1_4; +wire [15:0] daisy_chain_0_1_5; +wire [15:0] daisy_chain_0_2_0; +wire [15:0] daisy_chain_0_2_1; +wire [15:0] daisy_chain_0_2_2; +wire [15:0] daisy_chain_0_2_3; +wire [15:0] daisy_chain_0_2_4; +wire [15:0] daisy_chain_0_2_5; +wire [15:0] daisy_chain_0_3_0; +wire [15:0] daisy_chain_0_3_1; +wire [15:0] daisy_chain_0_3_2; +wire [15:0] daisy_chain_0_3_3; +wire [15:0] daisy_chain_0_3_4; +wire [15:0] daisy_chain_0_3_5; +wire [15:0] daisy_chain_0_4_0; +wire [15:0] daisy_chain_0_4_1; +wire [15:0] daisy_chain_0_4_2; +wire [15:0] daisy_chain_0_4_3; +wire [15:0] daisy_chain_0_4_4; +wire [15:0] daisy_chain_0_4_5; +wire [15:0] daisy_chain_0_5_0; +wire [15:0] daisy_chain_0_5_1; +wire [15:0] daisy_chain_0_5_2; +wire [15:0] daisy_chain_0_5_3; +wire [15:0] daisy_chain_0_5_4; +wire [15:0] daisy_chain_0_5_5; +wire [15:0] daisy_chain_0_6_0; +wire [15:0] daisy_chain_0_6_1; +wire [15:0] daisy_chain_0_6_2; +wire [15:0] daisy_chain_0_6_3; +wire [15:0] daisy_chain_0_6_4; +wire [15:0] daisy_chain_0_6_5; +wire [15:0] daisy_chain_0_7_0; +wire [15:0] daisy_chain_0_7_1; +wire [15:0] daisy_chain_0_7_2; +wire [15:0] daisy_chain_0_7_3; +wire [15:0] daisy_chain_0_7_4; +wire [15:0] daisy_chain_0_7_5; +wire [15:0] daisy_chain_1_0_0; +wire [15:0] daisy_chain_1_0_1; +wire [15:0] daisy_chain_1_0_2; +wire [15:0] daisy_chain_1_0_3; +wire [15:0] daisy_chain_1_0_4; +wire [15:0] daisy_chain_1_0_5; +wire [15:0] daisy_chain_1_1_0; +wire [15:0] daisy_chain_1_1_1; +wire [15:0] daisy_chain_1_1_2; +wire [15:0] daisy_chain_1_1_3; +wire [15:0] daisy_chain_1_1_4; +wire [15:0] daisy_chain_1_1_5; +wire [15:0] daisy_chain_1_2_0; +wire [15:0] daisy_chain_1_2_1; +wire [15:0] daisy_chain_1_2_2; +wire [15:0] daisy_chain_1_2_3; +wire [15:0] daisy_chain_1_2_4; +wire [15:0] daisy_chain_1_2_5; +wire [15:0] daisy_chain_1_3_0; +wire [15:0] daisy_chain_1_3_1; +wire [15:0] daisy_chain_1_3_2; +wire [15:0] daisy_chain_1_3_3; +wire [15:0] daisy_chain_1_3_4; +wire [15:0] daisy_chain_1_3_5; +wire [15:0] daisy_chain_1_4_0; +wire [15:0] daisy_chain_1_4_1; +wire [15:0] daisy_chain_1_4_2; +wire [15:0] daisy_chain_1_4_3; +wire [15:0] daisy_chain_1_4_4; +wire [15:0] daisy_chain_1_4_5; +wire [15:0] daisy_chain_1_5_0; +wire [15:0] daisy_chain_1_5_1; +wire [15:0] daisy_chain_1_5_2; +wire [15:0] daisy_chain_1_5_3; +wire [15:0] daisy_chain_1_5_4; +wire [15:0] daisy_chain_1_5_5; +wire [15:0] daisy_chain_1_6_0; +wire [15:0] daisy_chain_1_6_1; +wire [15:0] daisy_chain_1_6_2; +wire [15:0] daisy_chain_1_6_3; +wire [15:0] daisy_chain_1_6_4; +wire [15:0] daisy_chain_1_6_5; +wire [15:0] daisy_chain_1_7_0; +wire [15:0] daisy_chain_1_7_1; +wire [15:0] daisy_chain_1_7_2; +wire [15:0] daisy_chain_1_7_3; +wire [15:0] daisy_chain_1_7_4; +wire [15:0] daisy_chain_1_7_5; +wire [15:0] daisy_chain_2_0_0; +wire [15:0] daisy_chain_2_0_1; +wire [15:0] daisy_chain_2_0_2; +wire [15:0] daisy_chain_2_0_3; +wire [15:0] daisy_chain_2_0_4; +wire [15:0] daisy_chain_2_0_5; +wire [15:0] daisy_chain_2_1_0; +wire [15:0] daisy_chain_2_1_1; +wire [15:0] daisy_chain_2_1_2; +wire [15:0] daisy_chain_2_1_3; +wire [15:0] daisy_chain_2_1_4; +wire [15:0] daisy_chain_2_1_5; +wire [15:0] daisy_chain_2_2_0; +wire [15:0] daisy_chain_2_2_1; +wire [15:0] daisy_chain_2_2_2; +wire [15:0] daisy_chain_2_2_3; +wire [15:0] daisy_chain_2_2_4; +wire [15:0] daisy_chain_2_2_5; +wire [15:0] daisy_chain_2_3_0; +wire [15:0] daisy_chain_2_3_1; +wire [15:0] daisy_chain_2_3_2; +wire [15:0] daisy_chain_2_3_3; +wire [15:0] daisy_chain_2_3_4; +wire [15:0] daisy_chain_2_3_5; +wire [15:0] daisy_chain_2_4_0; +wire [15:0] daisy_chain_2_4_1; +wire [15:0] daisy_chain_2_4_2; +wire [15:0] daisy_chain_2_4_3; +wire [15:0] daisy_chain_2_4_4; +wire [15:0] daisy_chain_2_4_5; +wire [15:0] daisy_chain_2_5_0; +wire [15:0] daisy_chain_2_5_1; +wire [15:0] daisy_chain_2_5_2; +wire [15:0] daisy_chain_2_5_3; +wire [15:0] daisy_chain_2_5_4; +wire [15:0] daisy_chain_2_5_5; +wire [15:0] daisy_chain_2_6_0; +wire [15:0] daisy_chain_2_6_1; +wire [15:0] daisy_chain_2_6_2; +wire [15:0] daisy_chain_2_6_3; +wire [15:0] daisy_chain_2_6_4; +wire [15:0] daisy_chain_2_6_5; +wire [15:0] daisy_chain_2_7_0; +wire [15:0] daisy_chain_2_7_1; +wire [15:0] daisy_chain_2_7_2; +wire [15:0] daisy_chain_2_7_3; +wire [15:0] daisy_chain_2_7_4; +wire [15:0] daisy_chain_2_7_5; +wire [15:0] daisy_chain_3_0_0; +wire [15:0] daisy_chain_3_0_1; +wire [15:0] daisy_chain_3_0_2; +wire [15:0] daisy_chain_3_0_3; +wire [15:0] daisy_chain_3_0_4; +wire [15:0] daisy_chain_3_0_5; +wire [15:0] daisy_chain_3_1_0; +wire [15:0] daisy_chain_3_1_1; +wire [15:0] daisy_chain_3_1_2; +wire [15:0] daisy_chain_3_1_3; +wire [15:0] daisy_chain_3_1_4; +wire [15:0] daisy_chain_3_1_5; +wire [15:0] daisy_chain_3_2_0; +wire [15:0] daisy_chain_3_2_1; +wire [15:0] daisy_chain_3_2_2; +wire [15:0] daisy_chain_3_2_3; +wire [15:0] daisy_chain_3_2_4; +wire [15:0] daisy_chain_3_2_5; +wire [15:0] daisy_chain_3_3_0; +wire [15:0] daisy_chain_3_3_1; +wire [15:0] daisy_chain_3_3_2; +wire [15:0] daisy_chain_3_3_3; +wire [15:0] daisy_chain_3_3_4; +wire [15:0] daisy_chain_3_3_5; +wire [15:0] daisy_chain_3_4_0; +wire [15:0] daisy_chain_3_4_1; +wire [15:0] daisy_chain_3_4_2; +wire [15:0] daisy_chain_3_4_3; +wire [15:0] daisy_chain_3_4_4; +wire [15:0] daisy_chain_3_4_5; +wire [15:0] daisy_chain_3_5_0; +wire [15:0] daisy_chain_3_5_1; +wire [15:0] daisy_chain_3_5_2; +wire [15:0] daisy_chain_3_5_3; +wire [15:0] daisy_chain_3_5_4; +wire [15:0] daisy_chain_3_5_5; +wire [15:0] daisy_chain_3_6_0; +wire [15:0] daisy_chain_3_6_1; +wire [15:0] daisy_chain_3_6_2; +wire [15:0] daisy_chain_3_6_3; +wire [15:0] daisy_chain_3_6_4; +wire [15:0] daisy_chain_3_6_5; +wire [15:0] daisy_chain_3_7_0; +wire [15:0] daisy_chain_3_7_1; +wire [15:0] daisy_chain_3_7_2; +wire [15:0] daisy_chain_3_7_3; +wire [15:0] daisy_chain_3_7_4; +wire [15:0] daisy_chain_3_7_5; +wire [15:0] daisy_chain_4_0_0; +wire [15:0] daisy_chain_4_0_1; +wire [15:0] daisy_chain_4_0_2; +wire [15:0] daisy_chain_4_0_3; +wire [15:0] daisy_chain_4_0_4; +wire [15:0] daisy_chain_4_0_5; +wire [15:0] daisy_chain_4_1_0; +wire [15:0] daisy_chain_4_1_1; +wire [15:0] daisy_chain_4_1_2; +wire [15:0] daisy_chain_4_1_3; +wire [15:0] daisy_chain_4_1_4; +wire [15:0] daisy_chain_4_1_5; +wire [15:0] daisy_chain_4_2_0; +wire [15:0] daisy_chain_4_2_1; +wire [15:0] daisy_chain_4_2_2; +wire [15:0] daisy_chain_4_2_3; +wire [15:0] daisy_chain_4_2_4; +wire [15:0] daisy_chain_4_2_5; +wire [15:0] daisy_chain_4_3_0; +wire [15:0] daisy_chain_4_3_1; +wire [15:0] daisy_chain_4_3_2; +wire [15:0] daisy_chain_4_3_3; +wire [15:0] daisy_chain_4_3_4; +wire [15:0] daisy_chain_4_3_5; +wire [15:0] daisy_chain_4_4_0; +wire [15:0] daisy_chain_4_4_1; +wire [15:0] daisy_chain_4_4_2; +wire [15:0] daisy_chain_4_4_3; +wire [15:0] daisy_chain_4_4_4; +wire [15:0] daisy_chain_4_4_5; +wire [15:0] daisy_chain_4_5_0; +wire [15:0] daisy_chain_4_5_1; +wire [15:0] daisy_chain_4_5_2; +wire [15:0] daisy_chain_4_5_3; +wire [15:0] daisy_chain_4_5_4; +wire [15:0] daisy_chain_4_5_5; +wire [15:0] daisy_chain_4_6_0; +wire [15:0] daisy_chain_4_6_1; +wire [15:0] daisy_chain_4_6_2; +wire [15:0] daisy_chain_4_6_3; +wire [15:0] daisy_chain_4_6_4; +wire [15:0] daisy_chain_4_6_5; +wire [15:0] daisy_chain_4_7_0; +wire [15:0] daisy_chain_4_7_1; +wire [15:0] daisy_chain_4_7_2; +wire [15:0] daisy_chain_4_7_3; +wire [15:0] daisy_chain_4_7_4; +wire [15:0] daisy_chain_4_7_5; +wire [15:0] daisy_chain_5_0_0; +wire [15:0] daisy_chain_5_0_1; +wire [15:0] daisy_chain_5_0_2; +wire [15:0] daisy_chain_5_0_3; +wire [15:0] daisy_chain_5_0_4; +wire [15:0] daisy_chain_5_0_5; +wire [15:0] daisy_chain_5_1_0; +wire [15:0] daisy_chain_5_1_1; +wire [15:0] daisy_chain_5_1_2; +wire [15:0] daisy_chain_5_1_3; +wire [15:0] daisy_chain_5_1_4; +wire [15:0] daisy_chain_5_1_5; +wire [15:0] daisy_chain_5_2_0; +wire [15:0] daisy_chain_5_2_1; +wire [15:0] daisy_chain_5_2_2; +wire [15:0] daisy_chain_5_2_3; +wire [15:0] daisy_chain_5_2_4; +wire [15:0] daisy_chain_5_2_5; +wire [15:0] daisy_chain_5_3_0; +wire [15:0] daisy_chain_5_3_1; +wire [15:0] daisy_chain_5_3_2; +wire [15:0] daisy_chain_5_3_3; +wire [15:0] daisy_chain_5_3_4; +wire [15:0] daisy_chain_5_3_5; +wire [15:0] daisy_chain_5_4_0; +wire [15:0] daisy_chain_5_4_1; +wire [15:0] daisy_chain_5_4_2; +wire [15:0] daisy_chain_5_4_3; +wire [15:0] daisy_chain_5_4_4; +wire [15:0] daisy_chain_5_4_5; +wire [15:0] daisy_chain_5_5_0; +wire [15:0] daisy_chain_5_5_1; +wire [15:0] daisy_chain_5_5_2; +wire [15:0] daisy_chain_5_5_3; +wire [15:0] daisy_chain_5_5_4; +wire [15:0] daisy_chain_5_5_5; +wire [15:0] daisy_chain_5_6_0; +wire [15:0] daisy_chain_5_6_1; +wire [15:0] daisy_chain_5_6_2; +wire [15:0] daisy_chain_5_6_3; +wire [15:0] daisy_chain_5_6_4; +wire [15:0] daisy_chain_5_6_5; +wire [15:0] daisy_chain_5_7_0; +wire [15:0] daisy_chain_5_7_1; +wire [15:0] daisy_chain_5_7_2; +wire [15:0] daisy_chain_5_7_3; +wire [15:0] daisy_chain_5_7_4; +wire [15:0] daisy_chain_5_7_5; +wire [15:0] daisy_chain_6_0_0; +wire [15:0] daisy_chain_6_0_1; +wire [15:0] daisy_chain_6_0_2; +wire [15:0] daisy_chain_6_0_3; +wire [15:0] daisy_chain_6_0_4; +wire [15:0] daisy_chain_6_0_5; +wire [15:0] daisy_chain_6_1_0; +wire [15:0] daisy_chain_6_1_1; +wire [15:0] daisy_chain_6_1_2; +wire [15:0] daisy_chain_6_1_3; +wire [15:0] daisy_chain_6_1_4; +wire [15:0] daisy_chain_6_1_5; +wire [15:0] daisy_chain_6_2_0; +wire [15:0] daisy_chain_6_2_1; +wire [15:0] daisy_chain_6_2_2; +wire [15:0] daisy_chain_6_2_3; +wire [15:0] daisy_chain_6_2_4; +wire [15:0] daisy_chain_6_2_5; +wire [15:0] daisy_chain_6_3_0; +wire [15:0] daisy_chain_6_3_1; +wire [15:0] daisy_chain_6_3_2; +wire [15:0] daisy_chain_6_3_3; +wire [15:0] daisy_chain_6_3_4; +wire [15:0] daisy_chain_6_3_5; +wire [15:0] daisy_chain_6_4_0; +wire [15:0] daisy_chain_6_4_1; +wire [15:0] daisy_chain_6_4_2; +wire [15:0] daisy_chain_6_4_3; +wire [15:0] daisy_chain_6_4_4; +wire [15:0] daisy_chain_6_4_5; +wire [15:0] daisy_chain_6_5_0; +wire [15:0] daisy_chain_6_5_1; +wire [15:0] daisy_chain_6_5_2; +wire [15:0] daisy_chain_6_5_3; +wire [15:0] daisy_chain_6_5_4; +wire [15:0] daisy_chain_6_5_5; +wire [15:0] daisy_chain_6_6_0; +wire [15:0] daisy_chain_6_6_1; +wire [15:0] daisy_chain_6_6_2; +wire [15:0] daisy_chain_6_6_3; +wire [15:0] daisy_chain_6_6_4; +wire [15:0] daisy_chain_6_6_5; +wire [15:0] daisy_chain_6_7_0; +wire [15:0] daisy_chain_6_7_1; +wire [15:0] daisy_chain_6_7_2; +wire [15:0] daisy_chain_6_7_3; +wire [15:0] daisy_chain_6_7_4; +wire [15:0] daisy_chain_6_7_5; +wire [15:0] daisy_chain_7_0_0; +wire [15:0] daisy_chain_7_0_1; +wire [15:0] daisy_chain_7_0_2; +wire [15:0] daisy_chain_7_0_3; +wire [15:0] daisy_chain_7_0_4; +wire [15:0] daisy_chain_7_0_5; +wire [15:0] daisy_chain_7_1_0; +wire [15:0] daisy_chain_7_1_1; +wire [15:0] daisy_chain_7_1_2; +wire [15:0] daisy_chain_7_1_3; +wire [15:0] daisy_chain_7_1_4; +wire [15:0] daisy_chain_7_1_5; +wire [15:0] daisy_chain_7_2_0; +wire [15:0] daisy_chain_7_2_1; +wire [15:0] daisy_chain_7_2_2; +wire [15:0] daisy_chain_7_2_3; +wire [15:0] daisy_chain_7_2_4; +wire [15:0] daisy_chain_7_2_5; +wire [15:0] daisy_chain_7_3_0; +wire [15:0] daisy_chain_7_3_1; +wire [15:0] daisy_chain_7_3_2; +wire [15:0] daisy_chain_7_3_3; +wire [15:0] daisy_chain_7_3_4; +wire [15:0] daisy_chain_7_3_5; +wire [15:0] daisy_chain_7_4_0; +wire [15:0] daisy_chain_7_4_1; +wire [15:0] daisy_chain_7_4_2; +wire [15:0] daisy_chain_7_4_3; +wire [15:0] daisy_chain_7_4_4; +wire [15:0] daisy_chain_7_4_5; +wire [15:0] daisy_chain_7_5_0; +wire [15:0] daisy_chain_7_5_1; +wire [15:0] daisy_chain_7_5_2; +wire [15:0] daisy_chain_7_5_3; +wire [15:0] daisy_chain_7_5_4; +wire [15:0] daisy_chain_7_5_5; +wire [15:0] daisy_chain_7_6_0; +wire [15:0] daisy_chain_7_6_1; +wire [15:0] daisy_chain_7_6_2; +wire [15:0] daisy_chain_7_6_3; +wire [15:0] daisy_chain_7_6_4; +wire [15:0] daisy_chain_7_6_5; +wire [15:0] daisy_chain_7_7_0; +wire [15:0] daisy_chain_7_7_1; +wire [15:0] daisy_chain_7_7_2; +wire [15:0] daisy_chain_7_7_3; +wire [15:0] daisy_chain_7_7_4; +wire [15:0] daisy_chain_7_7_5; +wire [15:0] daisy_chain_8_0_0; +wire [15:0] daisy_chain_8_0_1; +wire [15:0] daisy_chain_8_0_2; +wire [15:0] daisy_chain_8_0_3; +wire [15:0] daisy_chain_8_0_4; +wire [15:0] daisy_chain_8_0_5; +wire [15:0] daisy_chain_8_1_0; +wire [15:0] daisy_chain_8_1_1; +wire [15:0] daisy_chain_8_1_2; +wire [15:0] daisy_chain_8_1_3; +wire [15:0] daisy_chain_8_1_4; +wire [15:0] daisy_chain_8_1_5; +wire [15:0] daisy_chain_8_2_0; +wire [15:0] daisy_chain_8_2_1; +wire [15:0] daisy_chain_8_2_2; +wire [15:0] daisy_chain_8_2_3; +wire [15:0] daisy_chain_8_2_4; +wire [15:0] daisy_chain_8_2_5; +wire [15:0] daisy_chain_8_3_0; +wire [15:0] daisy_chain_8_3_1; +wire [15:0] daisy_chain_8_3_2; +wire [15:0] daisy_chain_8_3_3; +wire [15:0] daisy_chain_8_3_4; +wire [15:0] daisy_chain_8_3_5; +wire [15:0] daisy_chain_8_4_0; +wire [15:0] daisy_chain_8_4_1; +wire [15:0] daisy_chain_8_4_2; +wire [15:0] daisy_chain_8_4_3; +wire [15:0] daisy_chain_8_4_4; +wire [15:0] daisy_chain_8_4_5; +wire [15:0] daisy_chain_8_5_0; +wire [15:0] daisy_chain_8_5_1; +wire [15:0] daisy_chain_8_5_2; +wire [15:0] daisy_chain_8_5_3; +wire [15:0] daisy_chain_8_5_4; +wire [15:0] daisy_chain_8_5_5; +wire [15:0] daisy_chain_8_6_0; +wire [15:0] daisy_chain_8_6_1; +wire [15:0] daisy_chain_8_6_2; +wire [15:0] daisy_chain_8_6_3; +wire [15:0] daisy_chain_8_6_4; +wire [15:0] daisy_chain_8_6_5; +wire [15:0] daisy_chain_8_7_0; +wire [15:0] daisy_chain_8_7_1; +wire [15:0] daisy_chain_8_7_2; +wire [15:0] daisy_chain_8_7_3; +wire [15:0] daisy_chain_8_7_4; +wire [15:0] daisy_chain_8_7_5; +wire [15:0] daisy_chain_9_0_0; +wire [15:0] daisy_chain_9_0_1; +wire [15:0] daisy_chain_9_0_2; +wire [15:0] daisy_chain_9_0_3; +wire [15:0] daisy_chain_9_0_4; +wire [15:0] daisy_chain_9_0_5; +wire [15:0] daisy_chain_9_1_0; +wire [15:0] daisy_chain_9_1_1; +wire [15:0] daisy_chain_9_1_2; +wire [15:0] daisy_chain_9_1_3; +wire [15:0] daisy_chain_9_1_4; +wire [15:0] daisy_chain_9_1_5; +wire [15:0] daisy_chain_9_2_0; +wire [15:0] daisy_chain_9_2_1; +wire [15:0] daisy_chain_9_2_2; +wire [15:0] daisy_chain_9_2_3; +wire [15:0] daisy_chain_9_2_4; +wire [15:0] daisy_chain_9_2_5; +wire [15:0] daisy_chain_9_3_0; +wire [15:0] daisy_chain_9_3_1; +wire [15:0] daisy_chain_9_3_2; +wire [15:0] daisy_chain_9_3_3; +wire [15:0] daisy_chain_9_3_4; +wire [15:0] daisy_chain_9_3_5; +wire [15:0] daisy_chain_9_4_0; +wire [15:0] daisy_chain_9_4_1; +wire [15:0] daisy_chain_9_4_2; +wire [15:0] daisy_chain_9_4_3; +wire [15:0] daisy_chain_9_4_4; +wire [15:0] daisy_chain_9_4_5; +wire [15:0] daisy_chain_9_5_0; +wire [15:0] daisy_chain_9_5_1; +wire [15:0] daisy_chain_9_5_2; +wire [15:0] daisy_chain_9_5_3; +wire [15:0] daisy_chain_9_5_4; +wire [15:0] daisy_chain_9_5_5; +wire [15:0] daisy_chain_9_6_0; +wire [15:0] daisy_chain_9_6_1; +wire [15:0] daisy_chain_9_6_2; +wire [15:0] daisy_chain_9_6_3; +wire [15:0] daisy_chain_9_6_4; +wire [15:0] daisy_chain_9_6_5; +wire [15:0] daisy_chain_9_7_0; +wire [15:0] daisy_chain_9_7_1; +wire [15:0] daisy_chain_9_7_2; +wire [15:0] daisy_chain_9_7_3; +wire [15:0] daisy_chain_9_7_4; +wire [15:0] daisy_chain_9_7_5; +wire [15:0] daisy_chain_10_0_0; +wire [15:0] daisy_chain_10_0_1; +wire [15:0] daisy_chain_10_0_2; +wire [15:0] daisy_chain_10_0_3; +wire [15:0] daisy_chain_10_0_4; +wire [15:0] daisy_chain_10_0_5; +wire [15:0] daisy_chain_10_1_0; +wire [15:0] daisy_chain_10_1_1; +wire [15:0] daisy_chain_10_1_2; +wire [15:0] daisy_chain_10_1_3; +wire [15:0] daisy_chain_10_1_4; +wire [15:0] daisy_chain_10_1_5; +wire [15:0] daisy_chain_10_2_0; +wire [15:0] daisy_chain_10_2_1; +wire [15:0] daisy_chain_10_2_2; +wire [15:0] daisy_chain_10_2_3; +wire [15:0] daisy_chain_10_2_4; +wire [15:0] daisy_chain_10_2_5; +wire [15:0] daisy_chain_10_3_0; +wire [15:0] daisy_chain_10_3_1; +wire [15:0] daisy_chain_10_3_2; +wire [15:0] daisy_chain_10_3_3; +wire [15:0] daisy_chain_10_3_4; +wire [15:0] daisy_chain_10_3_5; +wire [15:0] daisy_chain_10_4_0; +wire [15:0] daisy_chain_10_4_1; +wire [15:0] daisy_chain_10_4_2; +wire [15:0] daisy_chain_10_4_3; +wire [15:0] daisy_chain_10_4_4; +wire [15:0] daisy_chain_10_4_5; +wire [15:0] daisy_chain_10_5_0; +wire [15:0] daisy_chain_10_5_1; +wire [15:0] daisy_chain_10_5_2; +wire [15:0] daisy_chain_10_5_3; +wire [15:0] daisy_chain_10_5_4; +wire [15:0] daisy_chain_10_5_5; +wire [15:0] daisy_chain_10_6_0; +wire [15:0] daisy_chain_10_6_1; +wire [15:0] daisy_chain_10_6_2; +wire [15:0] daisy_chain_10_6_3; +wire [15:0] daisy_chain_10_6_4; +wire [15:0] daisy_chain_10_6_5; +wire [15:0] daisy_chain_10_7_0; +wire [15:0] daisy_chain_10_7_1; +wire [15:0] daisy_chain_10_7_2; +wire [15:0] daisy_chain_10_7_3; +wire [15:0] daisy_chain_10_7_4; +wire [15:0] daisy_chain_10_7_5; +wire [15:0] daisy_chain_11_0_0; +wire [15:0] daisy_chain_11_0_1; +wire [15:0] daisy_chain_11_0_2; +wire [15:0] daisy_chain_11_0_3; +wire [15:0] daisy_chain_11_0_4; +wire [15:0] daisy_chain_11_0_5; +wire [15:0] daisy_chain_11_1_0; +wire [15:0] daisy_chain_11_1_1; +wire [15:0] daisy_chain_11_1_2; +wire [15:0] daisy_chain_11_1_3; +wire [15:0] daisy_chain_11_1_4; +wire [15:0] daisy_chain_11_1_5; +wire [15:0] daisy_chain_11_2_0; +wire [15:0] daisy_chain_11_2_1; +wire [15:0] daisy_chain_11_2_2; +wire [15:0] daisy_chain_11_2_3; +wire [15:0] daisy_chain_11_2_4; +wire [15:0] daisy_chain_11_2_5; +wire [15:0] daisy_chain_11_3_0; +wire [15:0] daisy_chain_11_3_1; +wire [15:0] daisy_chain_11_3_2; +wire [15:0] daisy_chain_11_3_3; +wire [15:0] daisy_chain_11_3_4; +wire [15:0] daisy_chain_11_3_5; +wire [15:0] daisy_chain_11_4_0; +wire [15:0] daisy_chain_11_4_1; +wire [15:0] daisy_chain_11_4_2; +wire [15:0] daisy_chain_11_4_3; +wire [15:0] daisy_chain_11_4_4; +wire [15:0] daisy_chain_11_4_5; +wire [15:0] daisy_chain_11_5_0; +wire [15:0] daisy_chain_11_5_1; +wire [15:0] daisy_chain_11_5_2; +wire [15:0] daisy_chain_11_5_3; +wire [15:0] daisy_chain_11_5_4; +wire [15:0] daisy_chain_11_5_5; +wire [15:0] daisy_chain_11_6_0; +wire [15:0] daisy_chain_11_6_1; +wire [15:0] daisy_chain_11_6_2; +wire [15:0] daisy_chain_11_6_3; +wire [15:0] daisy_chain_11_6_4; +wire [15:0] daisy_chain_11_6_5; +wire [15:0] daisy_chain_11_7_0; +wire [15:0] daisy_chain_11_7_1; +wire [15:0] daisy_chain_11_7_2; +wire [15:0] daisy_chain_11_7_3; +wire [15:0] daisy_chain_11_7_4; +wire [15:0] daisy_chain_11_7_5; +wire [15:0] daisy_chain_12_0_0; +wire [15:0] daisy_chain_12_0_1; +wire [15:0] daisy_chain_12_0_2; +wire [15:0] daisy_chain_12_0_3; +wire [15:0] daisy_chain_12_0_4; +wire [15:0] daisy_chain_12_0_5; +wire [15:0] daisy_chain_12_1_0; +wire [15:0] daisy_chain_12_1_1; +wire [15:0] daisy_chain_12_1_2; +wire [15:0] daisy_chain_12_1_3; +wire [15:0] daisy_chain_12_1_4; +wire [15:0] daisy_chain_12_1_5; +wire [15:0] daisy_chain_12_2_0; +wire [15:0] daisy_chain_12_2_1; +wire [15:0] daisy_chain_12_2_2; +wire [15:0] daisy_chain_12_2_3; +wire [15:0] daisy_chain_12_2_4; +wire [15:0] daisy_chain_12_2_5; +wire [15:0] daisy_chain_12_3_0; +wire [15:0] daisy_chain_12_3_1; +wire [15:0] daisy_chain_12_3_2; +wire [15:0] daisy_chain_12_3_3; +wire [15:0] daisy_chain_12_3_4; +wire [15:0] daisy_chain_12_3_5; +wire [15:0] daisy_chain_12_4_0; +wire [15:0] daisy_chain_12_4_1; +wire [15:0] daisy_chain_12_4_2; +wire [15:0] daisy_chain_12_4_3; +wire [15:0] daisy_chain_12_4_4; +wire [15:0] daisy_chain_12_4_5; +wire [15:0] daisy_chain_12_5_0; +wire [15:0] daisy_chain_12_5_1; +wire [15:0] daisy_chain_12_5_2; +wire [15:0] daisy_chain_12_5_3; +wire [15:0] daisy_chain_12_5_4; +wire [15:0] daisy_chain_12_5_5; +wire [15:0] daisy_chain_12_6_0; +wire [15:0] daisy_chain_12_6_1; +wire [15:0] daisy_chain_12_6_2; +wire [15:0] daisy_chain_12_6_3; +wire [15:0] daisy_chain_12_6_4; +wire [15:0] daisy_chain_12_6_5; +wire [15:0] daisy_chain_12_7_0; +wire [15:0] daisy_chain_12_7_1; +wire [15:0] daisy_chain_12_7_2; +wire [15:0] daisy_chain_12_7_3; +wire [15:0] daisy_chain_12_7_4; +wire [15:0] daisy_chain_12_7_5; +wire [15:0] daisy_chain_13_0_0; +wire [15:0] daisy_chain_13_0_1; +wire [15:0] daisy_chain_13_0_2; +wire [15:0] daisy_chain_13_0_3; +wire [15:0] daisy_chain_13_0_4; +wire [15:0] daisy_chain_13_0_5; +wire [15:0] daisy_chain_13_1_0; +wire [15:0] daisy_chain_13_1_1; +wire [15:0] daisy_chain_13_1_2; +wire [15:0] daisy_chain_13_1_3; +wire [15:0] daisy_chain_13_1_4; +wire [15:0] daisy_chain_13_1_5; +wire [15:0] daisy_chain_13_2_0; +wire [15:0] daisy_chain_13_2_1; +wire [15:0] daisy_chain_13_2_2; +wire [15:0] daisy_chain_13_2_3; +wire [15:0] daisy_chain_13_2_4; +wire [15:0] daisy_chain_13_2_5; +wire [15:0] daisy_chain_13_3_0; +wire [15:0] daisy_chain_13_3_1; +wire [15:0] daisy_chain_13_3_2; +wire [15:0] daisy_chain_13_3_3; +wire [15:0] daisy_chain_13_3_4; +wire [15:0] daisy_chain_13_3_5; +wire [15:0] daisy_chain_13_4_0; +wire [15:0] daisy_chain_13_4_1; +wire [15:0] daisy_chain_13_4_2; +wire [15:0] daisy_chain_13_4_3; +wire [15:0] daisy_chain_13_4_4; +wire [15:0] daisy_chain_13_4_5; +wire [15:0] daisy_chain_13_5_0; +wire [15:0] daisy_chain_13_5_1; +wire [15:0] daisy_chain_13_5_2; +wire [15:0] daisy_chain_13_5_3; +wire [15:0] daisy_chain_13_5_4; +wire [15:0] daisy_chain_13_5_5; +wire [15:0] daisy_chain_13_6_0; +wire [15:0] daisy_chain_13_6_1; +wire [15:0] daisy_chain_13_6_2; +wire [15:0] daisy_chain_13_6_3; +wire [15:0] daisy_chain_13_6_4; +wire [15:0] daisy_chain_13_6_5; +wire [15:0] daisy_chain_13_7_0; +wire [15:0] daisy_chain_13_7_1; +wire [15:0] daisy_chain_13_7_2; +wire [15:0] daisy_chain_13_7_3; +wire [15:0] daisy_chain_13_7_4; +wire [15:0] daisy_chain_13_7_5; +wire [15:0] daisy_chain_14_0_0; +wire [15:0] daisy_chain_14_0_1; +wire [15:0] daisy_chain_14_0_2; +wire [15:0] daisy_chain_14_0_3; +wire [15:0] daisy_chain_14_0_4; +wire [15:0] daisy_chain_14_0_5; +wire [15:0] daisy_chain_14_1_0; +wire [15:0] daisy_chain_14_1_1; +wire [15:0] daisy_chain_14_1_2; +wire [15:0] daisy_chain_14_1_3; +wire [15:0] daisy_chain_14_1_4; +wire [15:0] daisy_chain_14_1_5; +wire [15:0] daisy_chain_14_2_0; +wire [15:0] daisy_chain_14_2_1; +wire [15:0] daisy_chain_14_2_2; +wire [15:0] daisy_chain_14_2_3; +wire [15:0] daisy_chain_14_2_4; +wire [15:0] daisy_chain_14_2_5; +wire [15:0] daisy_chain_14_3_0; +wire [15:0] daisy_chain_14_3_1; +wire [15:0] daisy_chain_14_3_2; +wire [15:0] daisy_chain_14_3_3; +wire [15:0] daisy_chain_14_3_4; +wire [15:0] daisy_chain_14_3_5; +wire [15:0] daisy_chain_14_4_0; +wire [15:0] daisy_chain_14_4_1; +wire [15:0] daisy_chain_14_4_2; +wire [15:0] daisy_chain_14_4_3; +wire [15:0] daisy_chain_14_4_4; +wire [15:0] daisy_chain_14_4_5; +wire [15:0] daisy_chain_14_5_0; +wire [15:0] daisy_chain_14_5_1; +wire [15:0] daisy_chain_14_5_2; +wire [15:0] daisy_chain_14_5_3; +wire [15:0] daisy_chain_14_5_4; +wire [15:0] daisy_chain_14_5_5; +wire [15:0] daisy_chain_14_6_0; +wire [15:0] daisy_chain_14_6_1; +wire [15:0] daisy_chain_14_6_2; +wire [15:0] daisy_chain_14_6_3; +wire [15:0] daisy_chain_14_6_4; +wire [15:0] daisy_chain_14_6_5; +wire [15:0] daisy_chain_14_7_0; +wire [15:0] daisy_chain_14_7_1; +wire [15:0] daisy_chain_14_7_2; +wire [15:0] daisy_chain_14_7_3; +wire [15:0] daisy_chain_14_7_4; +wire [15:0] daisy_chain_14_7_5; +wire [15:0] daisy_chain_15_0_0; +wire [15:0] daisy_chain_15_0_1; +wire [15:0] daisy_chain_15_0_2; +wire [15:0] daisy_chain_15_0_3; +wire [15:0] daisy_chain_15_0_4; +wire [15:0] daisy_chain_15_0_5; +wire [15:0] daisy_chain_15_1_0; +wire [15:0] daisy_chain_15_1_1; +wire [15:0] daisy_chain_15_1_2; +wire [15:0] daisy_chain_15_1_3; +wire [15:0] daisy_chain_15_1_4; +wire [15:0] daisy_chain_15_1_5; +wire [15:0] daisy_chain_15_2_0; +wire [15:0] daisy_chain_15_2_1; +wire [15:0] daisy_chain_15_2_2; +wire [15:0] daisy_chain_15_2_3; +wire [15:0] daisy_chain_15_2_4; +wire [15:0] daisy_chain_15_2_5; +wire [15:0] daisy_chain_15_3_0; +wire [15:0] daisy_chain_15_3_1; +wire [15:0] daisy_chain_15_3_2; +wire [15:0] daisy_chain_15_3_3; +wire [15:0] daisy_chain_15_3_4; +wire [15:0] daisy_chain_15_3_5; +wire [15:0] daisy_chain_15_4_0; +wire [15:0] daisy_chain_15_4_1; +wire [15:0] daisy_chain_15_4_2; +wire [15:0] daisy_chain_15_4_3; +wire [15:0] daisy_chain_15_4_4; +wire [15:0] daisy_chain_15_4_5; +wire [15:0] daisy_chain_15_5_0; +wire [15:0] daisy_chain_15_5_1; +wire [15:0] daisy_chain_15_5_2; +wire [15:0] daisy_chain_15_5_3; +wire [15:0] daisy_chain_15_5_4; +wire [15:0] daisy_chain_15_5_5; +wire [15:0] daisy_chain_15_6_0; +wire [15:0] daisy_chain_15_6_1; +wire [15:0] daisy_chain_15_6_2; +wire [15:0] daisy_chain_15_6_3; +wire [15:0] daisy_chain_15_6_4; +wire [15:0] daisy_chain_15_6_5; +wire [15:0] daisy_chain_15_7_0; +wire [15:0] daisy_chain_15_7_1; +wire [15:0] daisy_chain_15_7_2; +wire [15:0] daisy_chain_15_7_3; +wire [15:0] daisy_chain_15_7_4; +wire [15:0] daisy_chain_15_7_5; +wire [15:0] daisy_chain_16_0_0; +wire [15:0] daisy_chain_16_0_1; +wire [15:0] daisy_chain_16_0_2; +wire [15:0] daisy_chain_16_0_3; +wire [15:0] daisy_chain_16_0_4; +wire [15:0] daisy_chain_16_0_5; +wire [15:0] daisy_chain_16_1_0; +wire [15:0] daisy_chain_16_1_1; +wire [15:0] daisy_chain_16_1_2; +wire [15:0] daisy_chain_16_1_3; +wire [15:0] daisy_chain_16_1_4; +wire [15:0] daisy_chain_16_1_5; +wire [15:0] daisy_chain_16_2_0; +wire [15:0] daisy_chain_16_2_1; +wire [15:0] daisy_chain_16_2_2; +wire [15:0] daisy_chain_16_2_3; +wire [15:0] daisy_chain_16_2_4; +wire [15:0] daisy_chain_16_2_5; +wire [15:0] daisy_chain_16_3_0; +wire [15:0] daisy_chain_16_3_1; +wire [15:0] daisy_chain_16_3_2; +wire [15:0] daisy_chain_16_3_3; +wire [15:0] daisy_chain_16_3_4; +wire [15:0] daisy_chain_16_3_5; +wire [15:0] daisy_chain_16_4_0; +wire [15:0] daisy_chain_16_4_1; +wire [15:0] daisy_chain_16_4_2; +wire [15:0] daisy_chain_16_4_3; +wire [15:0] daisy_chain_16_4_4; +wire [15:0] daisy_chain_16_4_5; +wire [15:0] daisy_chain_16_5_0; +wire [15:0] daisy_chain_16_5_1; +wire [15:0] daisy_chain_16_5_2; +wire [15:0] daisy_chain_16_5_3; +wire [15:0] daisy_chain_16_5_4; +wire [15:0] daisy_chain_16_5_5; +wire [15:0] daisy_chain_16_6_0; +wire [15:0] daisy_chain_16_6_1; +wire [15:0] daisy_chain_16_6_2; +wire [15:0] daisy_chain_16_6_3; +wire [15:0] daisy_chain_16_6_4; +wire [15:0] daisy_chain_16_6_5; +wire [15:0] daisy_chain_16_7_0; +wire [15:0] daisy_chain_16_7_1; +wire [15:0] daisy_chain_16_7_2; +wire [15:0] daisy_chain_16_7_3; +wire [15:0] daisy_chain_16_7_4; +wire [15:0] daisy_chain_16_7_5; +wire [15:0] daisy_chain_17_0_0; +wire [15:0] daisy_chain_17_0_1; +wire [15:0] daisy_chain_17_0_2; +wire [15:0] daisy_chain_17_0_3; +wire [15:0] daisy_chain_17_0_4; +wire [15:0] daisy_chain_17_0_5; +wire [15:0] daisy_chain_17_1_0; +wire [15:0] daisy_chain_17_1_1; +wire [15:0] daisy_chain_17_1_2; +wire [15:0] daisy_chain_17_1_3; +wire [15:0] daisy_chain_17_1_4; +wire [15:0] daisy_chain_17_1_5; +wire [15:0] daisy_chain_17_2_0; +wire [15:0] daisy_chain_17_2_1; +wire [15:0] daisy_chain_17_2_2; +wire [15:0] daisy_chain_17_2_3; +wire [15:0] daisy_chain_17_2_4; +wire [15:0] daisy_chain_17_2_5; +wire [15:0] daisy_chain_17_3_0; +wire [15:0] daisy_chain_17_3_1; +wire [15:0] daisy_chain_17_3_2; +wire [15:0] daisy_chain_17_3_3; +wire [15:0] daisy_chain_17_3_4; +wire [15:0] daisy_chain_17_3_5; +wire [15:0] daisy_chain_17_4_0; +wire [15:0] daisy_chain_17_4_1; +wire [15:0] daisy_chain_17_4_2; +wire [15:0] daisy_chain_17_4_3; +wire [15:0] daisy_chain_17_4_4; +wire [15:0] daisy_chain_17_4_5; +wire [15:0] daisy_chain_17_5_0; +wire [15:0] daisy_chain_17_5_1; +wire [15:0] daisy_chain_17_5_2; +wire [15:0] daisy_chain_17_5_3; +wire [15:0] daisy_chain_17_5_4; +wire [15:0] daisy_chain_17_5_5; +wire [15:0] daisy_chain_17_6_0; +wire [15:0] daisy_chain_17_6_1; +wire [15:0] daisy_chain_17_6_2; +wire [15:0] daisy_chain_17_6_3; +wire [15:0] daisy_chain_17_6_4; +wire [15:0] daisy_chain_17_6_5; +wire [15:0] daisy_chain_17_7_0; +wire [15:0] daisy_chain_17_7_1; +wire [15:0] daisy_chain_17_7_2; +wire [15:0] daisy_chain_17_7_3; +wire [15:0] daisy_chain_17_7_4; +wire [15:0] daisy_chain_17_7_5; +wire [15:0] daisy_chain_18_0_0; +wire [15:0] daisy_chain_18_0_1; +wire [15:0] daisy_chain_18_0_2; +wire [15:0] daisy_chain_18_0_3; +wire [15:0] daisy_chain_18_0_4; +wire [15:0] daisy_chain_18_0_5; +wire [15:0] daisy_chain_18_1_0; +wire [15:0] daisy_chain_18_1_1; +wire [15:0] daisy_chain_18_1_2; +wire [15:0] daisy_chain_18_1_3; +wire [15:0] daisy_chain_18_1_4; +wire [15:0] daisy_chain_18_1_5; +wire [15:0] daisy_chain_18_2_0; +wire [15:0] daisy_chain_18_2_1; +wire [15:0] daisy_chain_18_2_2; +wire [15:0] daisy_chain_18_2_3; +wire [15:0] daisy_chain_18_2_4; +wire [15:0] daisy_chain_18_2_5; +wire [15:0] daisy_chain_18_3_0; +wire [15:0] daisy_chain_18_3_1; +wire [15:0] daisy_chain_18_3_2; +wire [15:0] daisy_chain_18_3_3; +wire [15:0] daisy_chain_18_3_4; +wire [15:0] daisy_chain_18_3_5; +wire [15:0] daisy_chain_18_4_0; +wire [15:0] daisy_chain_18_4_1; +wire [15:0] daisy_chain_18_4_2; +wire [15:0] daisy_chain_18_4_3; +wire [15:0] daisy_chain_18_4_4; +wire [15:0] daisy_chain_18_4_5; +wire [15:0] daisy_chain_18_5_0; +wire [15:0] daisy_chain_18_5_1; +wire [15:0] daisy_chain_18_5_2; +wire [15:0] daisy_chain_18_5_3; +wire [15:0] daisy_chain_18_5_4; +wire [15:0] daisy_chain_18_5_5; +wire [15:0] daisy_chain_18_6_0; +wire [15:0] daisy_chain_18_6_1; +wire [15:0] daisy_chain_18_6_2; +wire [15:0] daisy_chain_18_6_3; +wire [15:0] daisy_chain_18_6_4; +wire [15:0] daisy_chain_18_6_5; +wire [15:0] daisy_chain_18_7_0; +wire [15:0] daisy_chain_18_7_1; +wire [15:0] daisy_chain_18_7_2; +wire [15:0] daisy_chain_18_7_3; +wire [15:0] daisy_chain_18_7_4; +wire [15:0] daisy_chain_18_7_5; +wire [15:0] daisy_chain_19_0_0; +wire [15:0] daisy_chain_19_0_1; +wire [15:0] daisy_chain_19_0_2; +wire [15:0] daisy_chain_19_0_3; +wire [15:0] daisy_chain_19_0_4; +wire [15:0] daisy_chain_19_0_5; +wire [15:0] daisy_chain_19_1_0; +wire [15:0] daisy_chain_19_1_1; +wire [15:0] daisy_chain_19_1_2; +wire [15:0] daisy_chain_19_1_3; +wire [15:0] daisy_chain_19_1_4; +wire [15:0] daisy_chain_19_1_5; +wire [15:0] daisy_chain_19_2_0; +wire [15:0] daisy_chain_19_2_1; +wire [15:0] daisy_chain_19_2_2; +wire [15:0] daisy_chain_19_2_3; +wire [15:0] daisy_chain_19_2_4; +wire [15:0] daisy_chain_19_2_5; +wire [15:0] daisy_chain_19_3_0; +wire [15:0] daisy_chain_19_3_1; +wire [15:0] daisy_chain_19_3_2; +wire [15:0] daisy_chain_19_3_3; +wire [15:0] daisy_chain_19_3_4; +wire [15:0] daisy_chain_19_3_5; +wire [15:0] daisy_chain_19_4_0; +wire [15:0] daisy_chain_19_4_1; +wire [15:0] daisy_chain_19_4_2; +wire [15:0] daisy_chain_19_4_3; +wire [15:0] daisy_chain_19_4_4; +wire [15:0] daisy_chain_19_4_5; +wire [15:0] daisy_chain_19_5_0; +wire [15:0] daisy_chain_19_5_1; +wire [15:0] daisy_chain_19_5_2; +wire [15:0] daisy_chain_19_5_3; +wire [15:0] daisy_chain_19_5_4; +wire [15:0] daisy_chain_19_5_5; +wire [15:0] daisy_chain_19_6_0; +wire [15:0] daisy_chain_19_6_1; +wire [15:0] daisy_chain_19_6_2; +wire [15:0] daisy_chain_19_6_3; +wire [15:0] daisy_chain_19_6_4; +wire [15:0] daisy_chain_19_6_5; +wire [15:0] daisy_chain_19_7_0; +wire [15:0] daisy_chain_19_7_1; +wire [15:0] daisy_chain_19_7_2; +wire [15:0] daisy_chain_19_7_3; +wire [15:0] daisy_chain_19_7_4; +wire [15:0] daisy_chain_19_7_5; +wire [15:0] daisy_chain_20_0_0; +wire [15:0] daisy_chain_20_0_1; +wire [15:0] daisy_chain_20_0_2; +wire [15:0] daisy_chain_20_0_3; +wire [15:0] daisy_chain_20_0_4; +wire [15:0] daisy_chain_20_0_5; +wire [15:0] daisy_chain_20_1_0; +wire [15:0] daisy_chain_20_1_1; +wire [15:0] daisy_chain_20_1_2; +wire [15:0] daisy_chain_20_1_3; +wire [15:0] daisy_chain_20_1_4; +wire [15:0] daisy_chain_20_1_5; +wire [15:0] daisy_chain_20_2_0; +wire [15:0] daisy_chain_20_2_1; +wire [15:0] daisy_chain_20_2_2; +wire [15:0] daisy_chain_20_2_3; +wire [15:0] daisy_chain_20_2_4; +wire [15:0] daisy_chain_20_2_5; +wire [15:0] daisy_chain_20_3_0; +wire [15:0] daisy_chain_20_3_1; +wire [15:0] daisy_chain_20_3_2; +wire [15:0] daisy_chain_20_3_3; +wire [15:0] daisy_chain_20_3_4; +wire [15:0] daisy_chain_20_3_5; +wire [15:0] daisy_chain_20_4_0; +wire [15:0] daisy_chain_20_4_1; +wire [15:0] daisy_chain_20_4_2; +wire [15:0] daisy_chain_20_4_3; +wire [15:0] daisy_chain_20_4_4; +wire [15:0] daisy_chain_20_4_5; +wire [15:0] daisy_chain_20_5_0; +wire [15:0] daisy_chain_20_5_1; +wire [15:0] daisy_chain_20_5_2; +wire [15:0] daisy_chain_20_5_3; +wire [15:0] daisy_chain_20_5_4; +wire [15:0] daisy_chain_20_5_5; +wire [15:0] daisy_chain_20_6_0; +wire [15:0] daisy_chain_20_6_1; +wire [15:0] daisy_chain_20_6_2; +wire [15:0] daisy_chain_20_6_3; +wire [15:0] daisy_chain_20_6_4; +wire [15:0] daisy_chain_20_6_5; +wire [15:0] daisy_chain_20_7_0; +wire [15:0] daisy_chain_20_7_1; +wire [15:0] daisy_chain_20_7_2; +wire [15:0] daisy_chain_20_7_3; +wire [15:0] daisy_chain_20_7_4; +wire [15:0] daisy_chain_20_7_5; +wire [15:0] daisy_chain_21_0_0; +wire [15:0] daisy_chain_21_0_1; +wire [15:0] daisy_chain_21_0_2; +wire [15:0] daisy_chain_21_0_3; +wire [15:0] daisy_chain_21_0_4; +wire [15:0] daisy_chain_21_0_5; +wire [15:0] daisy_chain_21_1_0; +wire [15:0] daisy_chain_21_1_1; +wire [15:0] daisy_chain_21_1_2; +wire [15:0] daisy_chain_21_1_3; +wire [15:0] daisy_chain_21_1_4; +wire [15:0] daisy_chain_21_1_5; +wire [15:0] daisy_chain_21_2_0; +wire [15:0] daisy_chain_21_2_1; +wire [15:0] daisy_chain_21_2_2; +wire [15:0] daisy_chain_21_2_3; +wire [15:0] daisy_chain_21_2_4; +wire [15:0] daisy_chain_21_2_5; +wire [15:0] daisy_chain_21_3_0; +wire [15:0] daisy_chain_21_3_1; +wire [15:0] daisy_chain_21_3_2; +wire [15:0] daisy_chain_21_3_3; +wire [15:0] daisy_chain_21_3_4; +wire [15:0] daisy_chain_21_3_5; +wire [15:0] daisy_chain_21_4_0; +wire [15:0] daisy_chain_21_4_1; +wire [15:0] daisy_chain_21_4_2; +wire [15:0] daisy_chain_21_4_3; +wire [15:0] daisy_chain_21_4_4; +wire [15:0] daisy_chain_21_4_5; +wire [15:0] daisy_chain_21_5_0; +wire [15:0] daisy_chain_21_5_1; +wire [15:0] daisy_chain_21_5_2; +wire [15:0] daisy_chain_21_5_3; +wire [15:0] daisy_chain_21_5_4; +wire [15:0] daisy_chain_21_5_5; +wire [15:0] daisy_chain_21_6_0; +wire [15:0] daisy_chain_21_6_1; +wire [15:0] daisy_chain_21_6_2; +wire [15:0] daisy_chain_21_6_3; +wire [15:0] daisy_chain_21_6_4; +wire [15:0] daisy_chain_21_6_5; +wire [15:0] daisy_chain_21_7_0; +wire [15:0] daisy_chain_21_7_1; +wire [15:0] daisy_chain_21_7_2; +wire [15:0] daisy_chain_21_7_3; +wire [15:0] daisy_chain_21_7_4; +wire [15:0] daisy_chain_21_7_5; +wire [15:0] daisy_chain_22_0_0; +wire [15:0] daisy_chain_22_0_1; +wire [15:0] daisy_chain_22_0_2; +wire [15:0] daisy_chain_22_0_3; +wire [15:0] daisy_chain_22_0_4; +wire [15:0] daisy_chain_22_0_5; +wire [15:0] daisy_chain_22_1_0; +wire [15:0] daisy_chain_22_1_1; +wire [15:0] daisy_chain_22_1_2; +wire [15:0] daisy_chain_22_1_3; +wire [15:0] daisy_chain_22_1_4; +wire [15:0] daisy_chain_22_1_5; +wire [15:0] daisy_chain_22_2_0; +wire [15:0] daisy_chain_22_2_1; +wire [15:0] daisy_chain_22_2_2; +wire [15:0] daisy_chain_22_2_3; +wire [15:0] daisy_chain_22_2_4; +wire [15:0] daisy_chain_22_2_5; +wire [15:0] daisy_chain_22_3_0; +wire [15:0] daisy_chain_22_3_1; +wire [15:0] daisy_chain_22_3_2; +wire [15:0] daisy_chain_22_3_3; +wire [15:0] daisy_chain_22_3_4; +wire [15:0] daisy_chain_22_3_5; +wire [15:0] daisy_chain_22_4_0; +wire [15:0] daisy_chain_22_4_1; +wire [15:0] daisy_chain_22_4_2; +wire [15:0] daisy_chain_22_4_3; +wire [15:0] daisy_chain_22_4_4; +wire [15:0] daisy_chain_22_4_5; +wire [15:0] daisy_chain_22_5_0; +wire [15:0] daisy_chain_22_5_1; +wire [15:0] daisy_chain_22_5_2; +wire [15:0] daisy_chain_22_5_3; +wire [15:0] daisy_chain_22_5_4; +wire [15:0] daisy_chain_22_5_5; +wire [15:0] daisy_chain_22_6_0; +wire [15:0] daisy_chain_22_6_1; +wire [15:0] daisy_chain_22_6_2; +wire [15:0] daisy_chain_22_6_3; +wire [15:0] daisy_chain_22_6_4; +wire [15:0] daisy_chain_22_6_5; +wire [15:0] daisy_chain_22_7_0; +wire [15:0] daisy_chain_22_7_1; +wire [15:0] daisy_chain_22_7_2; +wire [15:0] daisy_chain_22_7_3; +wire [15:0] daisy_chain_22_7_4; +wire [15:0] daisy_chain_22_7_5; +wire [15:0] daisy_chain_23_0_0; +wire [15:0] daisy_chain_23_0_1; +wire [15:0] daisy_chain_23_0_2; +wire [15:0] daisy_chain_23_0_3; +wire [15:0] daisy_chain_23_0_4; +wire [15:0] daisy_chain_23_0_5; +wire [15:0] daisy_chain_23_1_0; +wire [15:0] daisy_chain_23_1_1; +wire [15:0] daisy_chain_23_1_2; +wire [15:0] daisy_chain_23_1_3; +wire [15:0] daisy_chain_23_1_4; +wire [15:0] daisy_chain_23_1_5; +wire [15:0] daisy_chain_23_2_0; +wire [15:0] daisy_chain_23_2_1; +wire [15:0] daisy_chain_23_2_2; +wire [15:0] daisy_chain_23_2_3; +wire [15:0] daisy_chain_23_2_4; +wire [15:0] daisy_chain_23_2_5; +wire [15:0] daisy_chain_23_3_0; +wire [15:0] daisy_chain_23_3_1; +wire [15:0] daisy_chain_23_3_2; +wire [15:0] daisy_chain_23_3_3; +wire [15:0] daisy_chain_23_3_4; +wire [15:0] daisy_chain_23_3_5; +wire [15:0] daisy_chain_23_4_0; +wire [15:0] daisy_chain_23_4_1; +wire [15:0] daisy_chain_23_4_2; +wire [15:0] daisy_chain_23_4_3; +wire [15:0] daisy_chain_23_4_4; +wire [15:0] daisy_chain_23_4_5; +wire [15:0] daisy_chain_23_5_0; +wire [15:0] daisy_chain_23_5_1; +wire [15:0] daisy_chain_23_5_2; +wire [15:0] daisy_chain_23_5_3; +wire [15:0] daisy_chain_23_5_4; +wire [15:0] daisy_chain_23_5_5; +wire [15:0] daisy_chain_23_6_0; +wire [15:0] daisy_chain_23_6_1; +wire [15:0] daisy_chain_23_6_2; +wire [15:0] daisy_chain_23_6_3; +wire [15:0] daisy_chain_23_6_4; +wire [15:0] daisy_chain_23_6_5; +wire [15:0] daisy_chain_23_7_0; +wire [15:0] daisy_chain_23_7_1; +wire [15:0] daisy_chain_23_7_2; +wire [15:0] daisy_chain_23_7_3; +wire [15:0] daisy_chain_23_7_4; +wire [15:0] daisy_chain_23_7_5; +wire [15:0] daisy_chain_24_0_0; +wire [15:0] daisy_chain_24_0_1; +wire [15:0] daisy_chain_24_0_2; +wire [15:0] daisy_chain_24_0_3; +wire [15:0] daisy_chain_24_0_4; +wire [15:0] daisy_chain_24_0_5; +wire [15:0] daisy_chain_24_1_0; +wire [15:0] daisy_chain_24_1_1; +wire [15:0] daisy_chain_24_1_2; +wire [15:0] daisy_chain_24_1_3; +wire [15:0] daisy_chain_24_1_4; +wire [15:0] daisy_chain_24_1_5; +wire [15:0] daisy_chain_24_2_0; +wire [15:0] daisy_chain_24_2_1; +wire [15:0] daisy_chain_24_2_2; +wire [15:0] daisy_chain_24_2_3; +wire [15:0] daisy_chain_24_2_4; +wire [15:0] daisy_chain_24_2_5; +wire [15:0] daisy_chain_24_3_0; +wire [15:0] daisy_chain_24_3_1; +wire [15:0] daisy_chain_24_3_2; +wire [15:0] daisy_chain_24_3_3; +wire [15:0] daisy_chain_24_3_4; +wire [15:0] daisy_chain_24_3_5; +wire [15:0] daisy_chain_24_4_0; +wire [15:0] daisy_chain_24_4_1; +wire [15:0] daisy_chain_24_4_2; +wire [15:0] daisy_chain_24_4_3; +wire [15:0] daisy_chain_24_4_4; +wire [15:0] daisy_chain_24_4_5; +wire [15:0] daisy_chain_24_5_0; +wire [15:0] daisy_chain_24_5_1; +wire [15:0] daisy_chain_24_5_2; +wire [15:0] daisy_chain_24_5_3; +wire [15:0] daisy_chain_24_5_4; +wire [15:0] daisy_chain_24_5_5; +wire [15:0] daisy_chain_24_6_0; +wire [15:0] daisy_chain_24_6_1; +wire [15:0] daisy_chain_24_6_2; +wire [15:0] daisy_chain_24_6_3; +wire [15:0] daisy_chain_24_6_4; +wire [15:0] daisy_chain_24_6_5; +wire [15:0] daisy_chain_24_7_0; +wire [15:0] daisy_chain_24_7_1; +wire [15:0] daisy_chain_24_7_2; +wire [15:0] daisy_chain_24_7_3; +wire [15:0] daisy_chain_24_7_4; +wire [15:0] daisy_chain_24_7_5; +wire [15:0] daisy_chain_25_0_0; +wire [15:0] daisy_chain_25_0_1; +wire [15:0] daisy_chain_25_0_2; +wire [15:0] daisy_chain_25_0_3; +wire [15:0] daisy_chain_25_0_4; +wire [15:0] daisy_chain_25_0_5; +wire [15:0] daisy_chain_25_1_0; +wire [15:0] daisy_chain_25_1_1; +wire [15:0] daisy_chain_25_1_2; +wire [15:0] daisy_chain_25_1_3; +wire [15:0] daisy_chain_25_1_4; +wire [15:0] daisy_chain_25_1_5; +wire [15:0] daisy_chain_25_2_0; +wire [15:0] daisy_chain_25_2_1; +wire [15:0] daisy_chain_25_2_2; +wire [15:0] daisy_chain_25_2_3; +wire [15:0] daisy_chain_25_2_4; +wire [15:0] daisy_chain_25_2_5; +wire [15:0] daisy_chain_25_3_0; +wire [15:0] daisy_chain_25_3_1; +wire [15:0] daisy_chain_25_3_2; +wire [15:0] daisy_chain_25_3_3; +wire [15:0] daisy_chain_25_3_4; +wire [15:0] daisy_chain_25_3_5; +wire [15:0] daisy_chain_25_4_0; +wire [15:0] daisy_chain_25_4_1; +wire [15:0] daisy_chain_25_4_2; +wire [15:0] daisy_chain_25_4_3; +wire [15:0] daisy_chain_25_4_4; +wire [15:0] daisy_chain_25_4_5; +wire [15:0] daisy_chain_25_5_0; +wire [15:0] daisy_chain_25_5_1; +wire [15:0] daisy_chain_25_5_2; +wire [15:0] daisy_chain_25_5_3; +wire [15:0] daisy_chain_25_5_4; +wire [15:0] daisy_chain_25_5_5; +wire [15:0] daisy_chain_25_6_0; +wire [15:0] daisy_chain_25_6_1; +wire [15:0] daisy_chain_25_6_2; +wire [15:0] daisy_chain_25_6_3; +wire [15:0] daisy_chain_25_6_4; +wire [15:0] daisy_chain_25_6_5; +wire [15:0] daisy_chain_25_7_0; +wire [15:0] daisy_chain_25_7_1; +wire [15:0] daisy_chain_25_7_2; +wire [15:0] daisy_chain_25_7_3; +wire [15:0] daisy_chain_25_7_4; +wire [15:0] daisy_chain_25_7_5; +wire [15:0] daisy_chain_26_0_0; +wire [15:0] daisy_chain_26_0_1; +wire [15:0] daisy_chain_26_0_2; +wire [15:0] daisy_chain_26_0_3; +wire [15:0] daisy_chain_26_0_4; +wire [15:0] daisy_chain_26_0_5; +wire [15:0] daisy_chain_26_1_0; +wire [15:0] daisy_chain_26_1_1; +wire [15:0] daisy_chain_26_1_2; +wire [15:0] daisy_chain_26_1_3; +wire [15:0] daisy_chain_26_1_4; +wire [15:0] daisy_chain_26_1_5; +wire [15:0] daisy_chain_26_2_0; +wire [15:0] daisy_chain_26_2_1; +wire [15:0] daisy_chain_26_2_2; +wire [15:0] daisy_chain_26_2_3; +wire [15:0] daisy_chain_26_2_4; +wire [15:0] daisy_chain_26_2_5; +wire [15:0] daisy_chain_26_3_0; +wire [15:0] daisy_chain_26_3_1; +wire [15:0] daisy_chain_26_3_2; +wire [15:0] daisy_chain_26_3_3; +wire [15:0] daisy_chain_26_3_4; +wire [15:0] daisy_chain_26_3_5; +wire [15:0] daisy_chain_26_4_0; +wire [15:0] daisy_chain_26_4_1; +wire [15:0] daisy_chain_26_4_2; +wire [15:0] daisy_chain_26_4_3; +wire [15:0] daisy_chain_26_4_4; +wire [15:0] daisy_chain_26_4_5; +wire [15:0] daisy_chain_26_5_0; +wire [15:0] daisy_chain_26_5_1; +wire [15:0] daisy_chain_26_5_2; +wire [15:0] daisy_chain_26_5_3; +wire [15:0] daisy_chain_26_5_4; +wire [15:0] daisy_chain_26_5_5; +wire [15:0] daisy_chain_26_6_0; +wire [15:0] daisy_chain_26_6_1; +wire [15:0] daisy_chain_26_6_2; +wire [15:0] daisy_chain_26_6_3; +wire [15:0] daisy_chain_26_6_4; +wire [15:0] daisy_chain_26_6_5; +wire [15:0] daisy_chain_26_7_0; +wire [15:0] daisy_chain_26_7_1; +wire [15:0] daisy_chain_26_7_2; +wire [15:0] daisy_chain_26_7_3; +wire [15:0] daisy_chain_26_7_4; +wire [15:0] daisy_chain_26_7_5; +wire [15:0] daisy_chain_27_0_0; +wire [15:0] daisy_chain_27_0_1; +wire [15:0] daisy_chain_27_0_2; +wire [15:0] daisy_chain_27_0_3; +wire [15:0] daisy_chain_27_0_4; +wire [15:0] daisy_chain_27_0_5; +wire [15:0] daisy_chain_27_1_0; +wire [15:0] daisy_chain_27_1_1; +wire [15:0] daisy_chain_27_1_2; +wire [15:0] daisy_chain_27_1_3; +wire [15:0] daisy_chain_27_1_4; +wire [15:0] daisy_chain_27_1_5; +wire [15:0] daisy_chain_27_2_0; +wire [15:0] daisy_chain_27_2_1; +wire [15:0] daisy_chain_27_2_2; +wire [15:0] daisy_chain_27_2_3; +wire [15:0] daisy_chain_27_2_4; +wire [15:0] daisy_chain_27_2_5; +wire [15:0] daisy_chain_27_3_0; +wire [15:0] daisy_chain_27_3_1; +wire [15:0] daisy_chain_27_3_2; +wire [15:0] daisy_chain_27_3_3; +wire [15:0] daisy_chain_27_3_4; +wire [15:0] daisy_chain_27_3_5; +wire [15:0] daisy_chain_27_4_0; +wire [15:0] daisy_chain_27_4_1; +wire [15:0] daisy_chain_27_4_2; +wire [15:0] daisy_chain_27_4_3; +wire [15:0] daisy_chain_27_4_4; +wire [15:0] daisy_chain_27_4_5; +wire [15:0] daisy_chain_27_5_0; +wire [15:0] daisy_chain_27_5_1; +wire [15:0] daisy_chain_27_5_2; +wire [15:0] daisy_chain_27_5_3; +wire [15:0] daisy_chain_27_5_4; +wire [15:0] daisy_chain_27_5_5; +wire [15:0] daisy_chain_27_6_0; +wire [15:0] daisy_chain_27_6_1; +wire [15:0] daisy_chain_27_6_2; +wire [15:0] daisy_chain_27_6_3; +wire [15:0] daisy_chain_27_6_4; +wire [15:0] daisy_chain_27_6_5; +wire [15:0] daisy_chain_27_7_0; +wire [15:0] daisy_chain_27_7_1; +wire [15:0] daisy_chain_27_7_2; +wire [15:0] daisy_chain_27_7_3; +wire [15:0] daisy_chain_27_7_4; +wire [15:0] daisy_chain_27_7_5; +wire [15:0] daisy_chain_28_0_0; +wire [15:0] daisy_chain_28_0_1; +wire [15:0] daisy_chain_28_0_2; +wire [15:0] daisy_chain_28_0_3; +wire [15:0] daisy_chain_28_0_4; +wire [15:0] daisy_chain_28_0_5; +wire [15:0] daisy_chain_28_1_0; +wire [15:0] daisy_chain_28_1_1; +wire [15:0] daisy_chain_28_1_2; +wire [15:0] daisy_chain_28_1_3; +wire [15:0] daisy_chain_28_1_4; +wire [15:0] daisy_chain_28_1_5; +wire [15:0] daisy_chain_28_2_0; +wire [15:0] daisy_chain_28_2_1; +wire [15:0] daisy_chain_28_2_2; +wire [15:0] daisy_chain_28_2_3; +wire [15:0] daisy_chain_28_2_4; +wire [15:0] daisy_chain_28_2_5; +wire [15:0] daisy_chain_28_3_0; +wire [15:0] daisy_chain_28_3_1; +wire [15:0] daisy_chain_28_3_2; +wire [15:0] daisy_chain_28_3_3; +wire [15:0] daisy_chain_28_3_4; +wire [15:0] daisy_chain_28_3_5; +wire [15:0] daisy_chain_28_4_0; +wire [15:0] daisy_chain_28_4_1; +wire [15:0] daisy_chain_28_4_2; +wire [15:0] daisy_chain_28_4_3; +wire [15:0] daisy_chain_28_4_4; +wire [15:0] daisy_chain_28_4_5; +wire [15:0] daisy_chain_28_5_0; +wire [15:0] daisy_chain_28_5_1; +wire [15:0] daisy_chain_28_5_2; +wire [15:0] daisy_chain_28_5_3; +wire [15:0] daisy_chain_28_5_4; +wire [15:0] daisy_chain_28_5_5; +wire [15:0] daisy_chain_28_6_0; +wire [15:0] daisy_chain_28_6_1; +wire [15:0] daisy_chain_28_6_2; +wire [15:0] daisy_chain_28_6_3; +wire [15:0] daisy_chain_28_6_4; +wire [15:0] daisy_chain_28_6_5; +wire [15:0] daisy_chain_28_7_0; +wire [15:0] daisy_chain_28_7_1; +wire [15:0] daisy_chain_28_7_2; +wire [15:0] daisy_chain_28_7_3; +wire [15:0] daisy_chain_28_7_4; +wire [15:0] daisy_chain_28_7_5; +wire [15:0] daisy_chain_29_0_0; +wire [15:0] daisy_chain_29_0_1; +wire [15:0] daisy_chain_29_0_2; +wire [15:0] daisy_chain_29_0_3; +wire [15:0] daisy_chain_29_0_4; +wire [15:0] daisy_chain_29_0_5; +wire [15:0] daisy_chain_29_1_0; +wire [15:0] daisy_chain_29_1_1; +wire [15:0] daisy_chain_29_1_2; +wire [15:0] daisy_chain_29_1_3; +wire [15:0] daisy_chain_29_1_4; +wire [15:0] daisy_chain_29_1_5; +wire [15:0] daisy_chain_29_2_0; +wire [15:0] daisy_chain_29_2_1; +wire [15:0] daisy_chain_29_2_2; +wire [15:0] daisy_chain_29_2_3; +wire [15:0] daisy_chain_29_2_4; +wire [15:0] daisy_chain_29_2_5; +wire [15:0] daisy_chain_29_3_0; +wire [15:0] daisy_chain_29_3_1; +wire [15:0] daisy_chain_29_3_2; +wire [15:0] daisy_chain_29_3_3; +wire [15:0] daisy_chain_29_3_4; +wire [15:0] daisy_chain_29_3_5; +wire [15:0] daisy_chain_29_4_0; +wire [15:0] daisy_chain_29_4_1; +wire [15:0] daisy_chain_29_4_2; +wire [15:0] daisy_chain_29_4_3; +wire [15:0] daisy_chain_29_4_4; +wire [15:0] daisy_chain_29_4_5; +wire [15:0] daisy_chain_29_5_0; +wire [15:0] daisy_chain_29_5_1; +wire [15:0] daisy_chain_29_5_2; +wire [15:0] daisy_chain_29_5_3; +wire [15:0] daisy_chain_29_5_4; +wire [15:0] daisy_chain_29_5_5; +wire [15:0] daisy_chain_29_6_0; +wire [15:0] daisy_chain_29_6_1; +wire [15:0] daisy_chain_29_6_2; +wire [15:0] daisy_chain_29_6_3; +wire [15:0] daisy_chain_29_6_4; +wire [15:0] daisy_chain_29_6_5; +wire [15:0] daisy_chain_29_7_0; +wire [15:0] daisy_chain_29_7_1; +wire [15:0] daisy_chain_29_7_2; +wire [15:0] daisy_chain_29_7_3; +wire [15:0] daisy_chain_29_7_4; +wire [15:0] daisy_chain_29_7_5; +wire [15:0] daisy_chain_30_0_0; +wire [15:0] daisy_chain_30_0_1; +wire [15:0] daisy_chain_30_0_2; +wire [15:0] daisy_chain_30_0_3; +wire [15:0] daisy_chain_30_0_4; +wire [15:0] daisy_chain_30_0_5; +wire [15:0] daisy_chain_30_1_0; +wire [15:0] daisy_chain_30_1_1; +wire [15:0] daisy_chain_30_1_2; +wire [15:0] daisy_chain_30_1_3; +wire [15:0] daisy_chain_30_1_4; +wire [15:0] daisy_chain_30_1_5; +wire [15:0] daisy_chain_30_2_0; +wire [15:0] daisy_chain_30_2_1; +wire [15:0] daisy_chain_30_2_2; +wire [15:0] daisy_chain_30_2_3; +wire [15:0] daisy_chain_30_2_4; +wire [15:0] daisy_chain_30_2_5; +wire [15:0] daisy_chain_30_3_0; +wire [15:0] daisy_chain_30_3_1; +wire [15:0] daisy_chain_30_3_2; +wire [15:0] daisy_chain_30_3_3; +wire [15:0] daisy_chain_30_3_4; +wire [15:0] daisy_chain_30_3_5; +wire [15:0] daisy_chain_30_4_0; +wire [15:0] daisy_chain_30_4_1; +wire [15:0] daisy_chain_30_4_2; +wire [15:0] daisy_chain_30_4_3; +wire [15:0] daisy_chain_30_4_4; +wire [15:0] daisy_chain_30_4_5; +wire [15:0] daisy_chain_30_5_0; +wire [15:0] daisy_chain_30_5_1; +wire [15:0] daisy_chain_30_5_2; +wire [15:0] daisy_chain_30_5_3; +wire [15:0] daisy_chain_30_5_4; +wire [15:0] daisy_chain_30_5_5; +wire [15:0] daisy_chain_30_6_0; +wire [15:0] daisy_chain_30_6_1; +wire [15:0] daisy_chain_30_6_2; +wire [15:0] daisy_chain_30_6_3; +wire [15:0] daisy_chain_30_6_4; +wire [15:0] daisy_chain_30_6_5; +wire [15:0] daisy_chain_30_7_0; +wire [15:0] daisy_chain_30_7_1; +wire [15:0] daisy_chain_30_7_2; +wire [15:0] daisy_chain_30_7_3; +wire [15:0] daisy_chain_30_7_4; +wire [15:0] daisy_chain_30_7_5; +wire [15:0] daisy_chain_31_0_0; +wire [15:0] daisy_chain_31_0_1; +wire [15:0] daisy_chain_31_0_2; +wire [15:0] daisy_chain_31_0_3; +wire [15:0] daisy_chain_31_0_4; +wire [15:0] daisy_chain_31_0_5; +wire [15:0] daisy_chain_31_1_0; +wire [15:0] daisy_chain_31_1_1; +wire [15:0] daisy_chain_31_1_2; +wire [15:0] daisy_chain_31_1_3; +wire [15:0] daisy_chain_31_1_4; +wire [15:0] daisy_chain_31_1_5; +wire [15:0] daisy_chain_31_2_0; +wire [15:0] daisy_chain_31_2_1; +wire [15:0] daisy_chain_31_2_2; +wire [15:0] daisy_chain_31_2_3; +wire [15:0] daisy_chain_31_2_4; +wire [15:0] daisy_chain_31_2_5; +wire [15:0] daisy_chain_31_3_0; +wire [15:0] daisy_chain_31_3_1; +wire [15:0] daisy_chain_31_3_2; +wire [15:0] daisy_chain_31_3_3; +wire [15:0] daisy_chain_31_3_4; +wire [15:0] daisy_chain_31_3_5; +wire [15:0] daisy_chain_31_4_0; +wire [15:0] daisy_chain_31_4_1; +wire [15:0] daisy_chain_31_4_2; +wire [15:0] daisy_chain_31_4_3; +wire [15:0] daisy_chain_31_4_4; +wire [15:0] daisy_chain_31_4_5; +wire [15:0] daisy_chain_31_5_0; +wire [15:0] daisy_chain_31_5_1; +wire [15:0] daisy_chain_31_5_2; +wire [15:0] daisy_chain_31_5_3; +wire [15:0] daisy_chain_31_5_4; +wire [15:0] daisy_chain_31_5_5; +wire [15:0] daisy_chain_31_6_0; +wire [15:0] daisy_chain_31_6_1; +wire [15:0] daisy_chain_31_6_2; +wire [15:0] daisy_chain_31_6_3; +wire [15:0] daisy_chain_31_6_4; +wire [15:0] daisy_chain_31_6_5; +wire [15:0] daisy_chain_31_7_0; +wire [15:0] daisy_chain_31_7_1; +wire [15:0] daisy_chain_31_7_2; +wire [15:0] daisy_chain_31_7_3; +wire [15:0] daisy_chain_31_7_4; +wire [15:0] daisy_chain_31_7_5; +wire [15:0] daisy_chain_32_0_0; +wire [15:0] daisy_chain_32_0_1; +wire [15:0] daisy_chain_32_0_2; +wire [15:0] daisy_chain_32_0_3; +wire [15:0] daisy_chain_32_0_4; +wire [15:0] daisy_chain_32_0_5; +wire [15:0] daisy_chain_32_1_0; +wire [15:0] daisy_chain_32_1_1; +wire [15:0] daisy_chain_32_1_2; +wire [15:0] daisy_chain_32_1_3; +wire [15:0] daisy_chain_32_1_4; +wire [15:0] daisy_chain_32_1_5; +wire [15:0] daisy_chain_32_2_0; +wire [15:0] daisy_chain_32_2_1; +wire [15:0] daisy_chain_32_2_2; +wire [15:0] daisy_chain_32_2_3; +wire [15:0] daisy_chain_32_2_4; +wire [15:0] daisy_chain_32_2_5; +wire [15:0] daisy_chain_32_3_0; +wire [15:0] daisy_chain_32_3_1; +wire [15:0] daisy_chain_32_3_2; +wire [15:0] daisy_chain_32_3_3; +wire [15:0] daisy_chain_32_3_4; +wire [15:0] daisy_chain_32_3_5; +wire [15:0] daisy_chain_32_4_0; +wire [15:0] daisy_chain_32_4_1; +wire [15:0] daisy_chain_32_4_2; +wire [15:0] daisy_chain_32_4_3; +wire [15:0] daisy_chain_32_4_4; +wire [15:0] daisy_chain_32_4_5; +wire [15:0] daisy_chain_32_5_0; +wire [15:0] daisy_chain_32_5_1; +wire [15:0] daisy_chain_32_5_2; +wire [15:0] daisy_chain_32_5_3; +wire [15:0] daisy_chain_32_5_4; +wire [15:0] daisy_chain_32_5_5; +wire [15:0] daisy_chain_32_6_0; +wire [15:0] daisy_chain_32_6_1; +wire [15:0] daisy_chain_32_6_2; +wire [15:0] daisy_chain_32_6_3; +wire [15:0] daisy_chain_32_6_4; +wire [15:0] daisy_chain_32_6_5; +wire [15:0] daisy_chain_32_7_0; +wire [15:0] daisy_chain_32_7_1; +wire [15:0] daisy_chain_32_7_2; +wire [15:0] daisy_chain_32_7_3; +wire [15:0] daisy_chain_32_7_4; +wire [15:0] daisy_chain_32_7_5; +wire [15:0] daisy_chain_33_0_0; +wire [15:0] daisy_chain_33_0_1; +wire [15:0] daisy_chain_33_0_2; +wire [15:0] daisy_chain_33_0_3; +wire [15:0] daisy_chain_33_0_4; +wire [15:0] daisy_chain_33_0_5; +wire [15:0] daisy_chain_33_1_0; +wire [15:0] daisy_chain_33_1_1; +wire [15:0] daisy_chain_33_1_2; +wire [15:0] daisy_chain_33_1_3; +wire [15:0] daisy_chain_33_1_4; +wire [15:0] daisy_chain_33_1_5; +wire [15:0] daisy_chain_33_2_0; +wire [15:0] daisy_chain_33_2_1; +wire [15:0] daisy_chain_33_2_2; +wire [15:0] daisy_chain_33_2_3; +wire [15:0] daisy_chain_33_2_4; +wire [15:0] daisy_chain_33_2_5; +wire [15:0] daisy_chain_33_3_0; +wire [15:0] daisy_chain_33_3_1; +wire [15:0] daisy_chain_33_3_2; +wire [15:0] daisy_chain_33_3_3; +wire [15:0] daisy_chain_33_3_4; +wire [15:0] daisy_chain_33_3_5; +wire [15:0] daisy_chain_33_4_0; +wire [15:0] daisy_chain_33_4_1; +wire [15:0] daisy_chain_33_4_2; +wire [15:0] daisy_chain_33_4_3; +wire [15:0] daisy_chain_33_4_4; +wire [15:0] daisy_chain_33_4_5; +wire [15:0] daisy_chain_33_5_0; +wire [15:0] daisy_chain_33_5_1; +wire [15:0] daisy_chain_33_5_2; +wire [15:0] daisy_chain_33_5_3; +wire [15:0] daisy_chain_33_5_4; +wire [15:0] daisy_chain_33_5_5; +wire [15:0] daisy_chain_33_6_0; +wire [15:0] daisy_chain_33_6_1; +wire [15:0] daisy_chain_33_6_2; +wire [15:0] daisy_chain_33_6_3; +wire [15:0] daisy_chain_33_6_4; +wire [15:0] daisy_chain_33_6_5; +wire [15:0] daisy_chain_33_7_0; +wire [15:0] daisy_chain_33_7_1; +wire [15:0] daisy_chain_33_7_2; +wire [15:0] daisy_chain_33_7_3; +wire [15:0] daisy_chain_33_7_4; +wire [15:0] daisy_chain_33_7_5; +wire [15:0] daisy_chain_34_0_0; +wire [15:0] daisy_chain_34_0_1; +wire [15:0] daisy_chain_34_0_2; +wire [15:0] daisy_chain_34_0_3; +wire [15:0] daisy_chain_34_0_4; +wire [15:0] daisy_chain_34_0_5; +wire [15:0] daisy_chain_34_1_0; +wire [15:0] daisy_chain_34_1_1; +wire [15:0] daisy_chain_34_1_2; +wire [15:0] daisy_chain_34_1_3; +wire [15:0] daisy_chain_34_1_4; +wire [15:0] daisy_chain_34_1_5; +wire [15:0] daisy_chain_34_2_0; +wire [15:0] daisy_chain_34_2_1; +wire [15:0] daisy_chain_34_2_2; +wire [15:0] daisy_chain_34_2_3; +wire [15:0] daisy_chain_34_2_4; +wire [15:0] daisy_chain_34_2_5; +wire [15:0] daisy_chain_34_3_0; +wire [15:0] daisy_chain_34_3_1; +wire [15:0] daisy_chain_34_3_2; +wire [15:0] daisy_chain_34_3_3; +wire [15:0] daisy_chain_34_3_4; +wire [15:0] daisy_chain_34_3_5; +wire [15:0] daisy_chain_34_4_0; +wire [15:0] daisy_chain_34_4_1; +wire [15:0] daisy_chain_34_4_2; +wire [15:0] daisy_chain_34_4_3; +wire [15:0] daisy_chain_34_4_4; +wire [15:0] daisy_chain_34_4_5; +wire [15:0] daisy_chain_34_5_0; +wire [15:0] daisy_chain_34_5_1; +wire [15:0] daisy_chain_34_5_2; +wire [15:0] daisy_chain_34_5_3; +wire [15:0] daisy_chain_34_5_4; +wire [15:0] daisy_chain_34_5_5; +wire [15:0] daisy_chain_34_6_0; +wire [15:0] daisy_chain_34_6_1; +wire [15:0] daisy_chain_34_6_2; +wire [15:0] daisy_chain_34_6_3; +wire [15:0] daisy_chain_34_6_4; +wire [15:0] daisy_chain_34_6_5; +wire [15:0] daisy_chain_34_7_0; +wire [15:0] daisy_chain_34_7_1; +wire [15:0] daisy_chain_34_7_2; +wire [15:0] daisy_chain_34_7_3; +wire [15:0] daisy_chain_34_7_4; +wire [15:0] daisy_chain_34_7_5; +wire [15:0] daisy_chain_35_0_0; +wire [15:0] daisy_chain_35_0_1; +wire [15:0] daisy_chain_35_0_2; +wire [15:0] daisy_chain_35_0_3; +wire [15:0] daisy_chain_35_0_4; +wire [15:0] daisy_chain_35_0_5; +wire [15:0] daisy_chain_35_1_0; +wire [15:0] daisy_chain_35_1_1; +wire [15:0] daisy_chain_35_1_2; +wire [15:0] daisy_chain_35_1_3; +wire [15:0] daisy_chain_35_1_4; +wire [15:0] daisy_chain_35_1_5; +wire [15:0] daisy_chain_35_2_0; +wire [15:0] daisy_chain_35_2_1; +wire [15:0] daisy_chain_35_2_2; +wire [15:0] daisy_chain_35_2_3; +wire [15:0] daisy_chain_35_2_4; +wire [15:0] daisy_chain_35_2_5; +wire [15:0] daisy_chain_35_3_0; +wire [15:0] daisy_chain_35_3_1; +wire [15:0] daisy_chain_35_3_2; +wire [15:0] daisy_chain_35_3_3; +wire [15:0] daisy_chain_35_3_4; +wire [15:0] daisy_chain_35_3_5; +wire [15:0] daisy_chain_35_4_0; +wire [15:0] daisy_chain_35_4_1; +wire [15:0] daisy_chain_35_4_2; +wire [15:0] daisy_chain_35_4_3; +wire [15:0] daisy_chain_35_4_4; +wire [15:0] daisy_chain_35_4_5; +wire [15:0] daisy_chain_35_5_0; +wire [15:0] daisy_chain_35_5_1; +wire [15:0] daisy_chain_35_5_2; +wire [15:0] daisy_chain_35_5_3; +wire [15:0] daisy_chain_35_5_4; +wire [15:0] daisy_chain_35_5_5; +wire [15:0] daisy_chain_35_6_0; +wire [15:0] daisy_chain_35_6_1; +wire [15:0] daisy_chain_35_6_2; +wire [15:0] daisy_chain_35_6_3; +wire [15:0] daisy_chain_35_6_4; +wire [15:0] daisy_chain_35_6_5; +wire [15:0] daisy_chain_35_7_0; +wire [15:0] daisy_chain_35_7_1; +wire [15:0] daisy_chain_35_7_2; +wire [15:0] daisy_chain_35_7_3; +wire [15:0] daisy_chain_35_7_4; +wire [15:0] daisy_chain_35_7_5; +wire [15:0] daisy_chain_36_0_0; +wire [15:0] daisy_chain_36_0_1; +wire [15:0] daisy_chain_36_0_2; +wire [15:0] daisy_chain_36_0_3; +wire [15:0] daisy_chain_36_0_4; +wire [15:0] daisy_chain_36_0_5; +wire [15:0] daisy_chain_36_1_0; +wire [15:0] daisy_chain_36_1_1; +wire [15:0] daisy_chain_36_1_2; +wire [15:0] daisy_chain_36_1_3; +wire [15:0] daisy_chain_36_1_4; +wire [15:0] daisy_chain_36_1_5; +wire [15:0] daisy_chain_36_2_0; +wire [15:0] daisy_chain_36_2_1; +wire [15:0] daisy_chain_36_2_2; +wire [15:0] daisy_chain_36_2_3; +wire [15:0] daisy_chain_36_2_4; +wire [15:0] daisy_chain_36_2_5; +wire [15:0] daisy_chain_36_3_0; +wire [15:0] daisy_chain_36_3_1; +wire [15:0] daisy_chain_36_3_2; +wire [15:0] daisy_chain_36_3_3; +wire [15:0] daisy_chain_36_3_4; +wire [15:0] daisy_chain_36_3_5; +wire [15:0] daisy_chain_36_4_0; +wire [15:0] daisy_chain_36_4_1; +wire [15:0] daisy_chain_36_4_2; +wire [15:0] daisy_chain_36_4_3; +wire [15:0] daisy_chain_36_4_4; +wire [15:0] daisy_chain_36_4_5; +wire [15:0] daisy_chain_36_5_0; +wire [15:0] daisy_chain_36_5_1; +wire [15:0] daisy_chain_36_5_2; +wire [15:0] daisy_chain_36_5_3; +wire [15:0] daisy_chain_36_5_4; +wire [15:0] daisy_chain_36_5_5; +wire [15:0] daisy_chain_36_6_0; +wire [15:0] daisy_chain_36_6_1; +wire [15:0] daisy_chain_36_6_2; +wire [15:0] daisy_chain_36_6_3; +wire [15:0] daisy_chain_36_6_4; +wire [15:0] daisy_chain_36_6_5; +wire [15:0] daisy_chain_36_7_0; +wire [15:0] daisy_chain_36_7_1; +wire [15:0] daisy_chain_36_7_2; +wire [15:0] daisy_chain_36_7_3; +wire [15:0] daisy_chain_36_7_4; +wire [15:0] daisy_chain_36_7_5; +wire [15:0] daisy_chain_37_0_0; +wire [15:0] daisy_chain_37_0_1; +wire [15:0] daisy_chain_37_0_2; +wire [15:0] daisy_chain_37_0_3; +wire [15:0] daisy_chain_37_0_4; +wire [15:0] daisy_chain_37_0_5; +wire [15:0] daisy_chain_37_1_0; +wire [15:0] daisy_chain_37_1_1; +wire [15:0] daisy_chain_37_1_2; +wire [15:0] daisy_chain_37_1_3; +wire [15:0] daisy_chain_37_1_4; +wire [15:0] daisy_chain_37_1_5; +wire [15:0] daisy_chain_37_2_0; +wire [15:0] daisy_chain_37_2_1; +wire [15:0] daisy_chain_37_2_2; +wire [15:0] daisy_chain_37_2_3; +wire [15:0] daisy_chain_37_2_4; +wire [15:0] daisy_chain_37_2_5; +wire [15:0] daisy_chain_37_3_0; +wire [15:0] daisy_chain_37_3_1; +wire [15:0] daisy_chain_37_3_2; +wire [15:0] daisy_chain_37_3_3; +wire [15:0] daisy_chain_37_3_4; +wire [15:0] daisy_chain_37_3_5; +wire [15:0] daisy_chain_37_4_0; +wire [15:0] daisy_chain_37_4_1; +wire [15:0] daisy_chain_37_4_2; +wire [15:0] daisy_chain_37_4_3; +wire [15:0] daisy_chain_37_4_4; +wire [15:0] daisy_chain_37_4_5; +wire [15:0] daisy_chain_37_5_0; +wire [15:0] daisy_chain_37_5_1; +wire [15:0] daisy_chain_37_5_2; +wire [15:0] daisy_chain_37_5_3; +wire [15:0] daisy_chain_37_5_4; +wire [15:0] daisy_chain_37_5_5; +wire [15:0] daisy_chain_37_6_0; +wire [15:0] daisy_chain_37_6_1; +wire [15:0] daisy_chain_37_6_2; +wire [15:0] daisy_chain_37_6_3; +wire [15:0] daisy_chain_37_6_4; +wire [15:0] daisy_chain_37_6_5; +wire [15:0] daisy_chain_37_7_0; +wire [15:0] daisy_chain_37_7_1; +wire [15:0] daisy_chain_37_7_2; +wire [15:0] daisy_chain_37_7_3; +wire [15:0] daisy_chain_37_7_4; +wire [15:0] daisy_chain_37_7_5; +wire [15:0] daisy_chain_38_0_0; +wire [15:0] daisy_chain_38_0_1; +wire [15:0] daisy_chain_38_0_2; +wire [15:0] daisy_chain_38_0_3; +wire [15:0] daisy_chain_38_0_4; +wire [15:0] daisy_chain_38_0_5; +wire [15:0] daisy_chain_38_1_0; +wire [15:0] daisy_chain_38_1_1; +wire [15:0] daisy_chain_38_1_2; +wire [15:0] daisy_chain_38_1_3; +wire [15:0] daisy_chain_38_1_4; +wire [15:0] daisy_chain_38_1_5; +wire [15:0] daisy_chain_38_2_0; +wire [15:0] daisy_chain_38_2_1; +wire [15:0] daisy_chain_38_2_2; +wire [15:0] daisy_chain_38_2_3; +wire [15:0] daisy_chain_38_2_4; +wire [15:0] daisy_chain_38_2_5; +wire [15:0] daisy_chain_38_3_0; +wire [15:0] daisy_chain_38_3_1; +wire [15:0] daisy_chain_38_3_2; +wire [15:0] daisy_chain_38_3_3; +wire [15:0] daisy_chain_38_3_4; +wire [15:0] daisy_chain_38_3_5; +wire [15:0] daisy_chain_38_4_0; +wire [15:0] daisy_chain_38_4_1; +wire [15:0] daisy_chain_38_4_2; +wire [15:0] daisy_chain_38_4_3; +wire [15:0] daisy_chain_38_4_4; +wire [15:0] daisy_chain_38_4_5; +wire [15:0] daisy_chain_38_5_0; +wire [15:0] daisy_chain_38_5_1; +wire [15:0] daisy_chain_38_5_2; +wire [15:0] daisy_chain_38_5_3; +wire [15:0] daisy_chain_38_5_4; +wire [15:0] daisy_chain_38_5_5; +wire [15:0] daisy_chain_38_6_0; +wire [15:0] daisy_chain_38_6_1; +wire [15:0] daisy_chain_38_6_2; +wire [15:0] daisy_chain_38_6_3; +wire [15:0] daisy_chain_38_6_4; +wire [15:0] daisy_chain_38_6_5; +wire [15:0] daisy_chain_38_7_0; +wire [15:0] daisy_chain_38_7_1; +wire [15:0] daisy_chain_38_7_2; +wire [15:0] daisy_chain_38_7_3; +wire [15:0] daisy_chain_38_7_4; +wire [15:0] daisy_chain_38_7_5; +wire [15:0] daisy_chain_39_0_0; +wire [15:0] daisy_chain_39_0_1; +wire [15:0] daisy_chain_39_0_2; +wire [15:0] daisy_chain_39_0_3; +wire [15:0] daisy_chain_39_0_4; +wire [15:0] daisy_chain_39_0_5; +wire [15:0] daisy_chain_39_1_0; +wire [15:0] daisy_chain_39_1_1; +wire [15:0] daisy_chain_39_1_2; +wire [15:0] daisy_chain_39_1_3; +wire [15:0] daisy_chain_39_1_4; +wire [15:0] daisy_chain_39_1_5; +wire [15:0] daisy_chain_39_2_0; +wire [15:0] daisy_chain_39_2_1; +wire [15:0] daisy_chain_39_2_2; +wire [15:0] daisy_chain_39_2_3; +wire [15:0] daisy_chain_39_2_4; +wire [15:0] daisy_chain_39_2_5; +wire [15:0] daisy_chain_39_3_0; +wire [15:0] daisy_chain_39_3_1; +wire [15:0] daisy_chain_39_3_2; +wire [15:0] daisy_chain_39_3_3; +wire [15:0] daisy_chain_39_3_4; +wire [15:0] daisy_chain_39_3_5; +wire [15:0] daisy_chain_39_4_0; +wire [15:0] daisy_chain_39_4_1; +wire [15:0] daisy_chain_39_4_2; +wire [15:0] daisy_chain_39_4_3; +wire [15:0] daisy_chain_39_4_4; +wire [15:0] daisy_chain_39_4_5; +wire [15:0] daisy_chain_39_5_0; +wire [15:0] daisy_chain_39_5_1; +wire [15:0] daisy_chain_39_5_2; +wire [15:0] daisy_chain_39_5_3; +wire [15:0] daisy_chain_39_5_4; +wire [15:0] daisy_chain_39_5_5; +wire [15:0] daisy_chain_39_6_0; +wire [15:0] daisy_chain_39_6_1; +wire [15:0] daisy_chain_39_6_2; +wire [15:0] daisy_chain_39_6_3; +wire [15:0] daisy_chain_39_6_4; +wire [15:0] daisy_chain_39_6_5; +wire [15:0] daisy_chain_39_7_0; +wire [15:0] daisy_chain_39_7_1; +wire [15:0] daisy_chain_39_7_2; +wire [15:0] daisy_chain_39_7_3; +wire [15:0] daisy_chain_39_7_4; +wire [15:0] daisy_chain_39_7_5; +wire [15:0] daisy_chain_40_0_0; +wire [15:0] daisy_chain_40_0_1; +wire [15:0] daisy_chain_40_0_2; +wire [15:0] daisy_chain_40_0_3; +wire [15:0] daisy_chain_40_0_4; +wire [15:0] daisy_chain_40_0_5; +wire [15:0] daisy_chain_40_1_0; +wire [15:0] daisy_chain_40_1_1; +wire [15:0] daisy_chain_40_1_2; +wire [15:0] daisy_chain_40_1_3; +wire [15:0] daisy_chain_40_1_4; +wire [15:0] daisy_chain_40_1_5; +wire [15:0] daisy_chain_40_2_0; +wire [15:0] daisy_chain_40_2_1; +wire [15:0] daisy_chain_40_2_2; +wire [15:0] daisy_chain_40_2_3; +wire [15:0] daisy_chain_40_2_4; +wire [15:0] daisy_chain_40_2_5; +wire [15:0] daisy_chain_40_3_0; +wire [15:0] daisy_chain_40_3_1; +wire [15:0] daisy_chain_40_3_2; +wire [15:0] daisy_chain_40_3_3; +wire [15:0] daisy_chain_40_3_4; +wire [15:0] daisy_chain_40_3_5; +wire [15:0] daisy_chain_40_4_0; +wire [15:0] daisy_chain_40_4_1; +wire [15:0] daisy_chain_40_4_2; +wire [15:0] daisy_chain_40_4_3; +wire [15:0] daisy_chain_40_4_4; +wire [15:0] daisy_chain_40_4_5; +wire [15:0] daisy_chain_40_5_0; +wire [15:0] daisy_chain_40_5_1; +wire [15:0] daisy_chain_40_5_2; +wire [15:0] daisy_chain_40_5_3; +wire [15:0] daisy_chain_40_5_4; +wire [15:0] daisy_chain_40_5_5; +wire [15:0] daisy_chain_40_6_0; +wire [15:0] daisy_chain_40_6_1; +wire [15:0] daisy_chain_40_6_2; +wire [15:0] daisy_chain_40_6_3; +wire [15:0] daisy_chain_40_6_4; +wire [15:0] daisy_chain_40_6_5; +wire [15:0] daisy_chain_40_7_0; +wire [15:0] daisy_chain_40_7_1; +wire [15:0] daisy_chain_40_7_2; +wire [15:0] daisy_chain_40_7_3; +wire [15:0] daisy_chain_40_7_4; +wire [15:0] daisy_chain_40_7_5; +wire [15:0] daisy_chain_41_0_0; +wire [15:0] daisy_chain_41_0_1; +wire [15:0] daisy_chain_41_0_2; +wire [15:0] daisy_chain_41_0_3; +wire [15:0] daisy_chain_41_0_4; +wire [15:0] daisy_chain_41_0_5; +wire [15:0] daisy_chain_41_1_0; +wire [15:0] daisy_chain_41_1_1; +wire [15:0] daisy_chain_41_1_2; +wire [15:0] daisy_chain_41_1_3; +wire [15:0] daisy_chain_41_1_4; +wire [15:0] daisy_chain_41_1_5; +wire [15:0] daisy_chain_41_2_0; +wire [15:0] daisy_chain_41_2_1; +wire [15:0] daisy_chain_41_2_2; +wire [15:0] daisy_chain_41_2_3; +wire [15:0] daisy_chain_41_2_4; +wire [15:0] daisy_chain_41_2_5; +wire [15:0] daisy_chain_41_3_0; +wire [15:0] daisy_chain_41_3_1; +wire [15:0] daisy_chain_41_3_2; +wire [15:0] daisy_chain_41_3_3; +wire [15:0] daisy_chain_41_3_4; +wire [15:0] daisy_chain_41_3_5; +wire [15:0] daisy_chain_41_4_0; +wire [15:0] daisy_chain_41_4_1; +wire [15:0] daisy_chain_41_4_2; +wire [15:0] daisy_chain_41_4_3; +wire [15:0] daisy_chain_41_4_4; +wire [15:0] daisy_chain_41_4_5; +wire [15:0] daisy_chain_41_5_0; +wire [15:0] daisy_chain_41_5_1; +wire [15:0] daisy_chain_41_5_2; +wire [15:0] daisy_chain_41_5_3; +wire [15:0] daisy_chain_41_5_4; +wire [15:0] daisy_chain_41_5_5; +wire [15:0] daisy_chain_41_6_0; +wire [15:0] daisy_chain_41_6_1; +wire [15:0] daisy_chain_41_6_2; +wire [15:0] daisy_chain_41_6_3; +wire [15:0] daisy_chain_41_6_4; +wire [15:0] daisy_chain_41_6_5; +wire [15:0] daisy_chain_41_7_0; +wire [15:0] daisy_chain_41_7_1; +wire [15:0] daisy_chain_41_7_2; +wire [15:0] daisy_chain_41_7_3; +wire [15:0] daisy_chain_41_7_4; +wire [15:0] daisy_chain_41_7_5; +wire [15:0] daisy_chain_42_0_0; +wire [15:0] daisy_chain_42_0_1; +wire [15:0] daisy_chain_42_0_2; +wire [15:0] daisy_chain_42_0_3; +wire [15:0] daisy_chain_42_0_4; +wire [15:0] daisy_chain_42_0_5; +wire [15:0] daisy_chain_42_1_0; +wire [15:0] daisy_chain_42_1_1; +wire [15:0] daisy_chain_42_1_2; +wire [15:0] daisy_chain_42_1_3; +wire [15:0] daisy_chain_42_1_4; +wire [15:0] daisy_chain_42_1_5; +wire [15:0] daisy_chain_42_2_0; +wire [15:0] daisy_chain_42_2_1; +wire [15:0] daisy_chain_42_2_2; +wire [15:0] daisy_chain_42_2_3; +wire [15:0] daisy_chain_42_2_4; +wire [15:0] daisy_chain_42_2_5; +wire [15:0] daisy_chain_42_3_0; +wire [15:0] daisy_chain_42_3_1; +wire [15:0] daisy_chain_42_3_2; +wire [15:0] daisy_chain_42_3_3; +wire [15:0] daisy_chain_42_3_4; +wire [15:0] daisy_chain_42_3_5; +wire [15:0] daisy_chain_42_4_0; +wire [15:0] daisy_chain_42_4_1; +wire [15:0] daisy_chain_42_4_2; +wire [15:0] daisy_chain_42_4_3; +wire [15:0] daisy_chain_42_4_4; +wire [15:0] daisy_chain_42_4_5; +wire [15:0] daisy_chain_42_5_0; +wire [15:0] daisy_chain_42_5_1; +wire [15:0] daisy_chain_42_5_2; +wire [15:0] daisy_chain_42_5_3; +wire [15:0] daisy_chain_42_5_4; +wire [15:0] daisy_chain_42_5_5; +wire [15:0] daisy_chain_42_6_0; +wire [15:0] daisy_chain_42_6_1; +wire [15:0] daisy_chain_42_6_2; +wire [15:0] daisy_chain_42_6_3; +wire [15:0] daisy_chain_42_6_4; +wire [15:0] daisy_chain_42_6_5; +wire [15:0] daisy_chain_42_7_0; +wire [15:0] daisy_chain_42_7_1; +wire [15:0] daisy_chain_42_7_2; +wire [15:0] daisy_chain_42_7_3; +wire [15:0] daisy_chain_42_7_4; +wire [15:0] daisy_chain_42_7_5; +wire [15:0] daisy_chain_43_0_0; +wire [15:0] daisy_chain_43_0_1; +wire [15:0] daisy_chain_43_0_2; +wire [15:0] daisy_chain_43_0_3; +wire [15:0] daisy_chain_43_0_4; +wire [15:0] daisy_chain_43_0_5; +wire [15:0] daisy_chain_43_1_0; +wire [15:0] daisy_chain_43_1_1; +wire [15:0] daisy_chain_43_1_2; +wire [15:0] daisy_chain_43_1_3; +wire [15:0] daisy_chain_43_1_4; +wire [15:0] daisy_chain_43_1_5; +wire [15:0] daisy_chain_43_2_0; +wire [15:0] daisy_chain_43_2_1; +wire [15:0] daisy_chain_43_2_2; +wire [15:0] daisy_chain_43_2_3; +wire [15:0] daisy_chain_43_2_4; +wire [15:0] daisy_chain_43_2_5; +wire [15:0] daisy_chain_43_3_0; +wire [15:0] daisy_chain_43_3_1; +wire [15:0] daisy_chain_43_3_2; +wire [15:0] daisy_chain_43_3_3; +wire [15:0] daisy_chain_43_3_4; +wire [15:0] daisy_chain_43_3_5; +wire [15:0] daisy_chain_43_4_0; +wire [15:0] daisy_chain_43_4_1; +wire [15:0] daisy_chain_43_4_2; +wire [15:0] daisy_chain_43_4_3; +wire [15:0] daisy_chain_43_4_4; +wire [15:0] daisy_chain_43_4_5; +wire [15:0] daisy_chain_43_5_0; +wire [15:0] daisy_chain_43_5_1; +wire [15:0] daisy_chain_43_5_2; +wire [15:0] daisy_chain_43_5_3; +wire [15:0] daisy_chain_43_5_4; +wire [15:0] daisy_chain_43_5_5; +wire [15:0] daisy_chain_43_6_0; +wire [15:0] daisy_chain_43_6_1; +wire [15:0] daisy_chain_43_6_2; +wire [15:0] daisy_chain_43_6_3; +wire [15:0] daisy_chain_43_6_4; +wire [15:0] daisy_chain_43_6_5; +wire [15:0] daisy_chain_43_7_0; +wire [15:0] daisy_chain_43_7_1; +wire [15:0] daisy_chain_43_7_2; +wire [15:0] daisy_chain_43_7_3; +wire [15:0] daisy_chain_43_7_4; +wire [15:0] daisy_chain_43_7_5; +wire [15:0] daisy_chain_44_0_0; +wire [15:0] daisy_chain_44_0_1; +wire [15:0] daisy_chain_44_0_2; +wire [15:0] daisy_chain_44_0_3; +wire [15:0] daisy_chain_44_0_4; +wire [15:0] daisy_chain_44_0_5; +wire [15:0] daisy_chain_44_1_0; +wire [15:0] daisy_chain_44_1_1; +wire [15:0] daisy_chain_44_1_2; +wire [15:0] daisy_chain_44_1_3; +wire [15:0] daisy_chain_44_1_4; +wire [15:0] daisy_chain_44_1_5; +wire [15:0] daisy_chain_44_2_0; +wire [15:0] daisy_chain_44_2_1; +wire [15:0] daisy_chain_44_2_2; +wire [15:0] daisy_chain_44_2_3; +wire [15:0] daisy_chain_44_2_4; +wire [15:0] daisy_chain_44_2_5; +wire [15:0] daisy_chain_44_3_0; +wire [15:0] daisy_chain_44_3_1; +wire [15:0] daisy_chain_44_3_2; +wire [15:0] daisy_chain_44_3_3; +wire [15:0] daisy_chain_44_3_4; +wire [15:0] daisy_chain_44_3_5; +wire [15:0] daisy_chain_44_4_0; +wire [15:0] daisy_chain_44_4_1; +wire [15:0] daisy_chain_44_4_2; +wire [15:0] daisy_chain_44_4_3; +wire [15:0] daisy_chain_44_4_4; +wire [15:0] daisy_chain_44_4_5; +wire [15:0] daisy_chain_44_5_0; +wire [15:0] daisy_chain_44_5_1; +wire [15:0] daisy_chain_44_5_2; +wire [15:0] daisy_chain_44_5_3; +wire [15:0] daisy_chain_44_5_4; +wire [15:0] daisy_chain_44_5_5; +wire [15:0] daisy_chain_44_6_0; +wire [15:0] daisy_chain_44_6_1; +wire [15:0] daisy_chain_44_6_2; +wire [15:0] daisy_chain_44_6_3; +wire [15:0] daisy_chain_44_6_4; +wire [15:0] daisy_chain_44_6_5; +wire [15:0] daisy_chain_44_7_0; +wire [15:0] daisy_chain_44_7_1; +wire [15:0] daisy_chain_44_7_2; +wire [15:0] daisy_chain_44_7_3; +wire [15:0] daisy_chain_44_7_4; +wire [15:0] daisy_chain_44_7_5; +wire [15:0] daisy_chain_45_0_0; +wire [15:0] daisy_chain_45_0_1; +wire [15:0] daisy_chain_45_0_2; +wire [15:0] daisy_chain_45_0_3; +wire [15:0] daisy_chain_45_0_4; +wire [15:0] daisy_chain_45_0_5; +wire [15:0] daisy_chain_45_1_0; +wire [15:0] daisy_chain_45_1_1; +wire [15:0] daisy_chain_45_1_2; +wire [15:0] daisy_chain_45_1_3; +wire [15:0] daisy_chain_45_1_4; +wire [15:0] daisy_chain_45_1_5; +wire [15:0] daisy_chain_45_2_0; +wire [15:0] daisy_chain_45_2_1; +wire [15:0] daisy_chain_45_2_2; +wire [15:0] daisy_chain_45_2_3; +wire [15:0] daisy_chain_45_2_4; +wire [15:0] daisy_chain_45_2_5; +wire [15:0] daisy_chain_45_3_0; +wire [15:0] daisy_chain_45_3_1; +wire [15:0] daisy_chain_45_3_2; +wire [15:0] daisy_chain_45_3_3; +wire [15:0] daisy_chain_45_3_4; +wire [15:0] daisy_chain_45_3_5; +wire [15:0] daisy_chain_45_4_0; +wire [15:0] daisy_chain_45_4_1; +wire [15:0] daisy_chain_45_4_2; +wire [15:0] daisy_chain_45_4_3; +wire [15:0] daisy_chain_45_4_4; +wire [15:0] daisy_chain_45_4_5; +wire [15:0] daisy_chain_45_5_0; +wire [15:0] daisy_chain_45_5_1; +wire [15:0] daisy_chain_45_5_2; +wire [15:0] daisy_chain_45_5_3; +wire [15:0] daisy_chain_45_5_4; +wire [15:0] daisy_chain_45_5_5; +wire [15:0] daisy_chain_45_6_0; +wire [15:0] daisy_chain_45_6_1; +wire [15:0] daisy_chain_45_6_2; +wire [15:0] daisy_chain_45_6_3; +wire [15:0] daisy_chain_45_6_4; +wire [15:0] daisy_chain_45_6_5; +wire [15:0] daisy_chain_45_7_0; +wire [15:0] daisy_chain_45_7_1; +wire [15:0] daisy_chain_45_7_2; +wire [15:0] daisy_chain_45_7_3; +wire [15:0] daisy_chain_45_7_4; +wire [15:0] daisy_chain_45_7_5; +wire [15:0] daisy_chain_46_0_0; +wire [15:0] daisy_chain_46_0_1; +wire [15:0] daisy_chain_46_0_2; +wire [15:0] daisy_chain_46_0_3; +wire [15:0] daisy_chain_46_0_4; +wire [15:0] daisy_chain_46_0_5; +wire [15:0] daisy_chain_46_1_0; +wire [15:0] daisy_chain_46_1_1; +wire [15:0] daisy_chain_46_1_2; +wire [15:0] daisy_chain_46_1_3; +wire [15:0] daisy_chain_46_1_4; +wire [15:0] daisy_chain_46_1_5; +wire [15:0] daisy_chain_46_2_0; +wire [15:0] daisy_chain_46_2_1; +wire [15:0] daisy_chain_46_2_2; +wire [15:0] daisy_chain_46_2_3; +wire [15:0] daisy_chain_46_2_4; +wire [15:0] daisy_chain_46_2_5; +wire [15:0] daisy_chain_46_3_0; +wire [15:0] daisy_chain_46_3_1; +wire [15:0] daisy_chain_46_3_2; +wire [15:0] daisy_chain_46_3_3; +wire [15:0] daisy_chain_46_3_4; +wire [15:0] daisy_chain_46_3_5; +wire [15:0] daisy_chain_46_4_0; +wire [15:0] daisy_chain_46_4_1; +wire [15:0] daisy_chain_46_4_2; +wire [15:0] daisy_chain_46_4_3; +wire [15:0] daisy_chain_46_4_4; +wire [15:0] daisy_chain_46_4_5; +wire [15:0] daisy_chain_46_5_0; +wire [15:0] daisy_chain_46_5_1; +wire [15:0] daisy_chain_46_5_2; +wire [15:0] daisy_chain_46_5_3; +wire [15:0] daisy_chain_46_5_4; +wire [15:0] daisy_chain_46_5_5; +wire [15:0] daisy_chain_46_6_0; +wire [15:0] daisy_chain_46_6_1; +wire [15:0] daisy_chain_46_6_2; +wire [15:0] daisy_chain_46_6_3; +wire [15:0] daisy_chain_46_6_4; +wire [15:0] daisy_chain_46_6_5; +wire [15:0] daisy_chain_46_7_0; +wire [15:0] daisy_chain_46_7_1; +wire [15:0] daisy_chain_46_7_2; +wire [15:0] daisy_chain_46_7_3; +wire [15:0] daisy_chain_46_7_4; +wire [15:0] daisy_chain_46_7_5; +wire [15:0] daisy_chain_47_0_0; +wire [15:0] daisy_chain_47_0_1; +wire [15:0] daisy_chain_47_0_2; +wire [15:0] daisy_chain_47_0_3; +wire [15:0] daisy_chain_47_0_4; +wire [15:0] daisy_chain_47_0_5; +wire [15:0] daisy_chain_47_1_0; +wire [15:0] daisy_chain_47_1_1; +wire [15:0] daisy_chain_47_1_2; +wire [15:0] daisy_chain_47_1_3; +wire [15:0] daisy_chain_47_1_4; +wire [15:0] daisy_chain_47_1_5; +wire [15:0] daisy_chain_47_2_0; +wire [15:0] daisy_chain_47_2_1; +wire [15:0] daisy_chain_47_2_2; +wire [15:0] daisy_chain_47_2_3; +wire [15:0] daisy_chain_47_2_4; +wire [15:0] daisy_chain_47_2_5; +wire [15:0] daisy_chain_47_3_0; +wire [15:0] daisy_chain_47_3_1; +wire [15:0] daisy_chain_47_3_2; +wire [15:0] daisy_chain_47_3_3; +wire [15:0] daisy_chain_47_3_4; +wire [15:0] daisy_chain_47_3_5; +wire [15:0] daisy_chain_47_4_0; +wire [15:0] daisy_chain_47_4_1; +wire [15:0] daisy_chain_47_4_2; +wire [15:0] daisy_chain_47_4_3; +wire [15:0] daisy_chain_47_4_4; +wire [15:0] daisy_chain_47_4_5; +wire [15:0] daisy_chain_47_5_0; +wire [15:0] daisy_chain_47_5_1; +wire [15:0] daisy_chain_47_5_2; +wire [15:0] daisy_chain_47_5_3; +wire [15:0] daisy_chain_47_5_4; +wire [15:0] daisy_chain_47_5_5; +wire [15:0] daisy_chain_47_6_0; +wire [15:0] daisy_chain_47_6_1; +wire [15:0] daisy_chain_47_6_2; +wire [15:0] daisy_chain_47_6_3; +wire [15:0] daisy_chain_47_6_4; +wire [15:0] daisy_chain_47_6_5; +wire [15:0] daisy_chain_47_7_0; +wire [15:0] daisy_chain_47_7_1; +wire [15:0] daisy_chain_47_7_2; +wire [15:0] daisy_chain_47_7_3; +wire [15:0] daisy_chain_47_7_4; +wire [15:0] daisy_chain_47_7_5; +wire [29:0] PE_output_0_0; +wire [29:0] PE_output_0_1; +wire [29:0] PE_output_0_2; +wire [29:0] PE_output_0_3; +wire [29:0] PE_output_0_4; +wire [29:0] PE_output_0_5; +wire [29:0] PE_output_1_0; +wire [29:0] PE_output_1_1; +wire [29:0] PE_output_1_2; +wire [29:0] PE_output_1_3; +wire [29:0] PE_output_1_4; +wire [29:0] PE_output_1_5; +wire [29:0] PE_output_2_0; +wire [29:0] PE_output_2_1; +wire [29:0] PE_output_2_2; +wire [29:0] PE_output_2_3; +wire [29:0] PE_output_2_4; +wire [29:0] PE_output_2_5; +wire [29:0] PE_output_3_0; +wire [29:0] PE_output_3_1; +wire [29:0] PE_output_3_2; +wire [29:0] PE_output_3_3; +wire [29:0] PE_output_3_4; +wire [29:0] PE_output_3_5; +wire [29:0] PE_output_4_0; +wire [29:0] PE_output_4_1; +wire [29:0] PE_output_4_2; +wire [29:0] PE_output_4_3; +wire [29:0] PE_output_4_4; +wire [29:0] PE_output_4_5; +wire [29:0] PE_output_5_0; +wire [29:0] PE_output_5_1; +wire [29:0] PE_output_5_2; +wire [29:0] PE_output_5_3; +wire [29:0] PE_output_5_4; +wire [29:0] PE_output_5_5; +wire [29:0] PE_output_6_0; +wire [29:0] PE_output_6_1; +wire [29:0] PE_output_6_2; +wire [29:0] PE_output_6_3; +wire [29:0] PE_output_6_4; +wire [29:0] PE_output_6_5; +wire [29:0] PE_output_7_0; +wire [29:0] PE_output_7_1; +wire [29:0] PE_output_7_2; +wire [29:0] PE_output_7_3; +wire [29:0] PE_output_7_4; +wire [29:0] PE_output_7_5; +wire [29:0] PE_output_8_0; +wire [29:0] PE_output_8_1; +wire [29:0] PE_output_8_2; +wire [29:0] PE_output_8_3; +wire [29:0] PE_output_8_4; +wire [29:0] PE_output_8_5; +wire [29:0] PE_output_9_0; +wire [29:0] PE_output_9_1; +wire [29:0] PE_output_9_2; +wire [29:0] PE_output_9_3; +wire [29:0] PE_output_9_4; +wire [29:0] PE_output_9_5; +wire [29:0] PE_output_10_0; +wire [29:0] PE_output_10_1; +wire [29:0] PE_output_10_2; +wire [29:0] PE_output_10_3; +wire [29:0] PE_output_10_4; +wire [29:0] PE_output_10_5; +wire [29:0] PE_output_11_0; +wire [29:0] PE_output_11_1; +wire [29:0] PE_output_11_2; +wire [29:0] PE_output_11_3; +wire [29:0] PE_output_11_4; +wire [29:0] PE_output_11_5; +wire [29:0] PE_output_12_0; +wire [29:0] PE_output_12_1; +wire [29:0] PE_output_12_2; +wire [29:0] PE_output_12_3; +wire [29:0] PE_output_12_4; +wire [29:0] PE_output_12_5; +wire [29:0] PE_output_13_0; +wire [29:0] PE_output_13_1; +wire [29:0] PE_output_13_2; +wire [29:0] PE_output_13_3; +wire [29:0] PE_output_13_4; +wire [29:0] PE_output_13_5; +wire [29:0] PE_output_14_0; +wire [29:0] PE_output_14_1; +wire [29:0] PE_output_14_2; +wire [29:0] PE_output_14_3; +wire [29:0] PE_output_14_4; +wire [29:0] PE_output_14_5; +wire [29:0] PE_output_15_0; +wire [29:0] PE_output_15_1; +wire [29:0] PE_output_15_2; +wire [29:0] PE_output_15_3; +wire [29:0] PE_output_15_4; +wire [29:0] PE_output_15_5; +wire [29:0] PE_output_16_0; +wire [29:0] PE_output_16_1; +wire [29:0] PE_output_16_2; +wire [29:0] PE_output_16_3; +wire [29:0] PE_output_16_4; +wire [29:0] PE_output_16_5; +wire [29:0] PE_output_17_0; +wire [29:0] PE_output_17_1; +wire [29:0] PE_output_17_2; +wire [29:0] PE_output_17_3; +wire [29:0] PE_output_17_4; +wire [29:0] PE_output_17_5; +wire [29:0] PE_output_18_0; +wire [29:0] PE_output_18_1; +wire [29:0] PE_output_18_2; +wire [29:0] PE_output_18_3; +wire [29:0] PE_output_18_4; +wire [29:0] PE_output_18_5; +wire [29:0] PE_output_19_0; +wire [29:0] PE_output_19_1; +wire [29:0] PE_output_19_2; +wire [29:0] PE_output_19_3; +wire [29:0] PE_output_19_4; +wire [29:0] PE_output_19_5; +wire [29:0] PE_output_20_0; +wire [29:0] PE_output_20_1; +wire [29:0] PE_output_20_2; +wire [29:0] PE_output_20_3; +wire [29:0] PE_output_20_4; +wire [29:0] PE_output_20_5; +wire [29:0] PE_output_21_0; +wire [29:0] PE_output_21_1; +wire [29:0] PE_output_21_2; +wire [29:0] PE_output_21_3; +wire [29:0] PE_output_21_4; +wire [29:0] PE_output_21_5; +wire [29:0] PE_output_22_0; +wire [29:0] PE_output_22_1; +wire [29:0] PE_output_22_2; +wire [29:0] PE_output_22_3; +wire [29:0] PE_output_22_4; +wire [29:0] PE_output_22_5; +wire [29:0] PE_output_23_0; +wire [29:0] PE_output_23_1; +wire [29:0] PE_output_23_2; +wire [29:0] PE_output_23_3; +wire [29:0] PE_output_23_4; +wire [29:0] PE_output_23_5; +wire [29:0] PE_output_24_0; +wire [29:0] PE_output_24_1; +wire [29:0] PE_output_24_2; +wire [29:0] PE_output_24_3; +wire [29:0] PE_output_24_4; +wire [29:0] PE_output_24_5; +wire [29:0] PE_output_25_0; +wire [29:0] PE_output_25_1; +wire [29:0] PE_output_25_2; +wire [29:0] PE_output_25_3; +wire [29:0] PE_output_25_4; +wire [29:0] PE_output_25_5; +wire [29:0] PE_output_26_0; +wire [29:0] PE_output_26_1; +wire [29:0] PE_output_26_2; +wire [29:0] PE_output_26_3; +wire [29:0] PE_output_26_4; +wire [29:0] PE_output_26_5; +wire [29:0] PE_output_27_0; +wire [29:0] PE_output_27_1; +wire [29:0] PE_output_27_2; +wire [29:0] PE_output_27_3; +wire [29:0] PE_output_27_4; +wire [29:0] PE_output_27_5; +wire [29:0] PE_output_28_0; +wire [29:0] PE_output_28_1; +wire [29:0] PE_output_28_2; +wire [29:0] PE_output_28_3; +wire [29:0] PE_output_28_4; +wire [29:0] PE_output_28_5; +wire [29:0] PE_output_29_0; +wire [29:0] PE_output_29_1; +wire [29:0] PE_output_29_2; +wire [29:0] PE_output_29_3; +wire [29:0] PE_output_29_4; +wire [29:0] PE_output_29_5; +wire [29:0] PE_output_30_0; +wire [29:0] PE_output_30_1; +wire [29:0] PE_output_30_2; +wire [29:0] PE_output_30_3; +wire [29:0] PE_output_30_4; +wire [29:0] PE_output_30_5; +wire [29:0] PE_output_31_0; +wire [29:0] PE_output_31_1; +wire [29:0] PE_output_31_2; +wire [29:0] PE_output_31_3; +wire [29:0] PE_output_31_4; +wire [29:0] PE_output_31_5; +wire [29:0] PE_output_32_0; +wire [29:0] PE_output_32_1; +wire [29:0] PE_output_32_2; +wire [29:0] PE_output_32_3; +wire [29:0] PE_output_32_4; +wire [29:0] PE_output_32_5; +wire [29:0] PE_output_33_0; +wire [29:0] PE_output_33_1; +wire [29:0] PE_output_33_2; +wire [29:0] PE_output_33_3; +wire [29:0] PE_output_33_4; +wire [29:0] PE_output_33_5; +wire [29:0] PE_output_34_0; +wire [29:0] PE_output_34_1; +wire [29:0] PE_output_34_2; +wire [29:0] PE_output_34_3; +wire [29:0] PE_output_34_4; +wire [29:0] PE_output_34_5; +wire [29:0] PE_output_35_0; +wire [29:0] PE_output_35_1; +wire [29:0] PE_output_35_2; +wire [29:0] PE_output_35_3; +wire [29:0] PE_output_35_4; +wire [29:0] PE_output_35_5; +wire [29:0] PE_output_36_0; +wire [29:0] PE_output_36_1; +wire [29:0] PE_output_36_2; +wire [29:0] PE_output_36_3; +wire [29:0] PE_output_36_4; +wire [29:0] PE_output_36_5; +wire [29:0] PE_output_37_0; +wire [29:0] PE_output_37_1; +wire [29:0] PE_output_37_2; +wire [29:0] PE_output_37_3; +wire [29:0] PE_output_37_4; +wire [29:0] PE_output_37_5; +wire [29:0] PE_output_38_0; +wire [29:0] PE_output_38_1; +wire [29:0] PE_output_38_2; +wire [29:0] PE_output_38_3; +wire [29:0] PE_output_38_4; +wire [29:0] PE_output_38_5; +wire [29:0] PE_output_39_0; +wire [29:0] PE_output_39_1; +wire [29:0] PE_output_39_2; +wire [29:0] PE_output_39_3; +wire [29:0] PE_output_39_4; +wire [29:0] PE_output_39_5; +wire [29:0] PE_output_40_0; +wire [29:0] PE_output_40_1; +wire [29:0] PE_output_40_2; +wire [29:0] PE_output_40_3; +wire [29:0] PE_output_40_4; +wire [29:0] PE_output_40_5; +wire [29:0] PE_output_41_0; +wire [29:0] PE_output_41_1; +wire [29:0] PE_output_41_2; +wire [29:0] PE_output_41_3; +wire [29:0] PE_output_41_4; +wire [29:0] PE_output_41_5; +wire [29:0] PE_output_42_0; +wire [29:0] PE_output_42_1; +wire [29:0] PE_output_42_2; +wire [29:0] PE_output_42_3; +wire [29:0] PE_output_42_4; +wire [29:0] PE_output_42_5; +wire [29:0] PE_output_43_0; +wire [29:0] PE_output_43_1; +wire [29:0] PE_output_43_2; +wire [29:0] PE_output_43_3; +wire [29:0] PE_output_43_4; +wire [29:0] PE_output_43_5; +wire [29:0] PE_output_44_0; +wire [29:0] PE_output_44_1; +wire [29:0] PE_output_44_2; +wire [29:0] PE_output_44_3; +wire [29:0] PE_output_44_4; +wire [29:0] PE_output_44_5; +wire [29:0] PE_output_45_0; +wire [29:0] PE_output_45_1; +wire [29:0] PE_output_45_2; +wire [29:0] PE_output_45_3; +wire [29:0] PE_output_45_4; +wire [29:0] PE_output_45_5; +wire [29:0] PE_output_46_0; +wire [29:0] PE_output_46_1; +wire [29:0] PE_output_46_2; +wire [29:0] PE_output_46_3; +wire [29:0] PE_output_46_4; +wire [29:0] PE_output_46_5; +wire [29:0] PE_output_47_0; +wire [29:0] PE_output_47_1; +wire [29:0] PE_output_47_2; +wire [29:0] PE_output_47_3; +wire [29:0] PE_output_47_4; +wire [29:0] PE_output_47_5; +wire PE_valid_0; +wire PE_next_reset_0; +wire PE_next_valid_0; +wire PE_valid_1; +wire PE_next_reset_1; +wire PE_next_valid_1; +wire PE_valid_2; +wire PE_next_reset_2; +wire PE_next_valid_2; +wire PE_valid_3; +wire PE_next_reset_3; +wire PE_next_valid_3; +wire PE_valid_4; +wire PE_next_reset_4; +wire PE_next_valid_4; +wire PE_valid_5; +wire PE_next_reset_5; +wire PE_next_valid_5; +wire PE_valid_6; +wire PE_next_reset_6; +wire PE_next_valid_6; +wire PE_valid_7; +wire PE_next_reset_7; +wire PE_next_valid_7; +wire PE_valid_8; +wire PE_next_reset_8; +wire PE_next_valid_8; +wire PE_valid_9; +wire PE_next_reset_9; +wire PE_next_valid_9; +wire PE_valid_10; +wire PE_next_reset_10; +wire PE_next_valid_10; +wire PE_valid_11; +wire PE_next_reset_11; +wire PE_next_valid_11; +wire PE_valid_12; +wire PE_next_reset_12; +wire PE_next_valid_12; +wire PE_valid_13; +wire PE_next_reset_13; +wire PE_next_valid_13; +wire PE_valid_14; +wire PE_next_reset_14; +wire PE_next_valid_14; +wire PE_valid_15; +wire PE_next_reset_15; +wire PE_next_valid_15; +wire PE_valid_16; +wire PE_next_reset_16; +wire PE_next_valid_16; +wire PE_valid_17; +wire PE_next_reset_17; +wire PE_next_valid_17; +wire PE_valid_18; +wire PE_next_reset_18; +wire PE_next_valid_18; +wire PE_valid_19; +wire PE_next_reset_19; +wire PE_next_valid_19; +wire PE_valid_20; +wire PE_next_reset_20; +wire PE_next_valid_20; +wire PE_valid_21; +wire PE_next_reset_21; +wire PE_next_valid_21; +wire PE_valid_22; +wire PE_next_reset_22; +wire PE_next_valid_22; +wire PE_valid_23; +wire PE_next_reset_23; +wire PE_next_valid_23; +wire PE_valid_24; +wire PE_next_reset_24; +wire PE_next_valid_24; +wire PE_valid_25; +wire PE_next_reset_25; +wire PE_next_valid_25; +wire PE_valid_26; +wire PE_next_reset_26; +wire PE_next_valid_26; +wire PE_valid_27; +wire PE_next_reset_27; +wire PE_next_valid_27; +wire PE_valid_28; +wire PE_next_reset_28; +wire PE_next_valid_28; +wire PE_valid_29; +wire PE_next_reset_29; +wire PE_next_valid_29; +wire PE_valid_30; +wire PE_next_reset_30; +wire PE_next_valid_30; +wire PE_valid_31; +wire PE_next_reset_31; +wire PE_next_valid_31; +wire PE_valid_32; +wire PE_next_reset_32; +wire PE_next_valid_32; +wire PE_valid_33; +wire PE_next_reset_33; +wire PE_next_valid_33; +wire PE_valid_34; +wire PE_next_reset_34; +wire PE_next_valid_34; +wire PE_valid_35; +wire PE_next_reset_35; +wire PE_next_valid_35; +wire PE_valid_36; +wire PE_next_reset_36; +wire PE_next_valid_36; +wire PE_valid_37; +wire PE_next_reset_37; +wire PE_next_valid_37; +wire PE_valid_38; +wire PE_next_reset_38; +wire PE_next_valid_38; +wire PE_valid_39; +wire PE_next_reset_39; +wire PE_next_valid_39; +wire PE_valid_40; +wire PE_next_reset_40; +wire PE_next_valid_40; +wire PE_valid_41; +wire PE_next_reset_41; +wire PE_next_valid_41; +wire PE_valid_42; +wire PE_next_reset_42; +wire PE_next_valid_42; +wire PE_valid_43; +wire PE_next_reset_43; +wire PE_next_valid_43; +wire PE_valid_44; +wire PE_next_reset_44; +wire PE_next_valid_44; +wire PE_valid_45; +wire PE_next_reset_45; +wire PE_next_valid_45; +wire PE_valid_46; +wire PE_next_reset_46; +wire PE_next_valid_46; +wire PE_valid_47; +wire PE_next_reset_47; +wire PE_next_valid_47; + +// Inverse Winograd Wires +wire [15:0] INV_output_0_0; +wire [15:0] INV_output_0_1; +wire [15:0] INV_output_0_2; +wire [15:0] INV_output_0_3; +wire INV_valid_0; +wire [15:0] INV_output_1_0; +wire [15:0] INV_output_1_1; +wire [15:0] INV_output_1_2; +wire [15:0] INV_output_1_3; +wire INV_valid_1; +wire [15:0] INV_output_2_0; +wire [15:0] INV_output_2_1; +wire [15:0] INV_output_2_2; +wire [15:0] INV_output_2_3; +wire INV_valid_2; +wire [15:0] INV_output_3_0; +wire [15:0] INV_output_3_1; +wire [15:0] INV_output_3_2; +wire [15:0] INV_output_3_3; +wire INV_valid_3; +wire [15:0] INV_output_4_0; +wire [15:0] INV_output_4_1; +wire [15:0] INV_output_4_2; +wire [15:0] INV_output_4_3; +wire INV_valid_4; +wire [15:0] INV_output_5_0; +wire [15:0] INV_output_5_1; +wire [15:0] INV_output_5_2; +wire [15:0] INV_output_5_3; +wire INV_valid_5; +wire [15:0] INV_output_6_0; +wire [15:0] INV_output_6_1; +wire [15:0] INV_output_6_2; +wire [15:0] INV_output_6_3; +wire INV_valid_6; +wire [15:0] INV_output_7_0; +wire [15:0] INV_output_7_1; +wire [15:0] INV_output_7_2; +wire [15:0] INV_output_7_3; +wire INV_valid_7; +wire [15:0] INV_output_8_0; +wire [15:0] INV_output_8_1; +wire [15:0] INV_output_8_2; +wire [15:0] INV_output_8_3; +wire INV_valid_8; +wire [15:0] INV_output_9_0; +wire [15:0] INV_output_9_1; +wire [15:0] INV_output_9_2; +wire [15:0] INV_output_9_3; +wire INV_valid_9; +wire [15:0] INV_output_10_0; +wire [15:0] INV_output_10_1; +wire [15:0] INV_output_10_2; +wire [15:0] INV_output_10_3; +wire INV_valid_10; +wire [15:0] INV_output_11_0; +wire [15:0] INV_output_11_1; +wire [15:0] INV_output_11_2; +wire [15:0] INV_output_11_3; +wire INV_valid_11; +wire [15:0] INV_output_12_0; +wire [15:0] INV_output_12_1; +wire [15:0] INV_output_12_2; +wire [15:0] INV_output_12_3; +wire INV_valid_12; +wire [15:0] INV_output_13_0; +wire [15:0] INV_output_13_1; +wire [15:0] INV_output_13_2; +wire [15:0] INV_output_13_3; +wire INV_valid_13; +wire [15:0] INV_output_14_0; +wire [15:0] INV_output_14_1; +wire [15:0] INV_output_14_2; +wire [15:0] INV_output_14_3; +wire INV_valid_14; +wire [15:0] INV_output_15_0; +wire [15:0] INV_output_15_1; +wire [15:0] INV_output_15_2; +wire [15:0] INV_output_15_3; +wire INV_valid_15; +wire [15:0] INV_output_16_0; +wire [15:0] INV_output_16_1; +wire [15:0] INV_output_16_2; +wire [15:0] INV_output_16_3; +wire INV_valid_16; +wire [15:0] INV_output_17_0; +wire [15:0] INV_output_17_1; +wire [15:0] INV_output_17_2; +wire [15:0] INV_output_17_3; +wire INV_valid_17; +wire [15:0] INV_output_18_0; +wire [15:0] INV_output_18_1; +wire [15:0] INV_output_18_2; +wire [15:0] INV_output_18_3; +wire INV_valid_18; +wire [15:0] INV_output_19_0; +wire [15:0] INV_output_19_1; +wire [15:0] INV_output_19_2; +wire [15:0] INV_output_19_3; +wire INV_valid_19; +wire [15:0] INV_output_20_0; +wire [15:0] INV_output_20_1; +wire [15:0] INV_output_20_2; +wire [15:0] INV_output_20_3; +wire INV_valid_20; +wire [15:0] INV_output_21_0; +wire [15:0] INV_output_21_1; +wire [15:0] INV_output_21_2; +wire [15:0] INV_output_21_3; +wire INV_valid_21; +wire [15:0] INV_output_22_0; +wire [15:0] INV_output_22_1; +wire [15:0] INV_output_22_2; +wire [15:0] INV_output_22_3; +wire INV_valid_22; +wire [15:0] INV_output_23_0; +wire [15:0] INV_output_23_1; +wire [15:0] INV_output_23_2; +wire [15:0] INV_output_23_3; +wire INV_valid_23; +wire [15:0] INV_output_24_0; +wire [15:0] INV_output_24_1; +wire [15:0] INV_output_24_2; +wire [15:0] INV_output_24_3; +wire INV_valid_24; +wire [15:0] INV_output_25_0; +wire [15:0] INV_output_25_1; +wire [15:0] INV_output_25_2; +wire [15:0] INV_output_25_3; +wire INV_valid_25; +wire [15:0] INV_output_26_0; +wire [15:0] INV_output_26_1; +wire [15:0] INV_output_26_2; +wire [15:0] INV_output_26_3; +wire INV_valid_26; +wire [15:0] INV_output_27_0; +wire [15:0] INV_output_27_1; +wire [15:0] INV_output_27_2; +wire [15:0] INV_output_27_3; +wire INV_valid_27; +wire [15:0] INV_output_28_0; +wire [15:0] INV_output_28_1; +wire [15:0] INV_output_28_2; +wire [15:0] INV_output_28_3; +wire INV_valid_28; +wire [15:0] INV_output_29_0; +wire [15:0] INV_output_29_1; +wire [15:0] INV_output_29_2; +wire [15:0] INV_output_29_3; +wire INV_valid_29; +wire [15:0] INV_output_30_0; +wire [15:0] INV_output_30_1; +wire [15:0] INV_output_30_2; +wire [15:0] INV_output_30_3; +wire INV_valid_30; +wire [15:0] INV_output_31_0; +wire [15:0] INV_output_31_1; +wire [15:0] INV_output_31_2; +wire [15:0] INV_output_31_3; +wire INV_valid_31; +wire [15:0] INV_output_32_0; +wire [15:0] INV_output_32_1; +wire [15:0] INV_output_32_2; +wire [15:0] INV_output_32_3; +wire INV_valid_32; +wire [15:0] INV_output_33_0; +wire [15:0] INV_output_33_1; +wire [15:0] INV_output_33_2; +wire [15:0] INV_output_33_3; +wire INV_valid_33; +wire [15:0] INV_output_34_0; +wire [15:0] INV_output_34_1; +wire [15:0] INV_output_34_2; +wire [15:0] INV_output_34_3; +wire INV_valid_34; +wire [15:0] INV_output_35_0; +wire [15:0] INV_output_35_1; +wire [15:0] INV_output_35_2; +wire [15:0] INV_output_35_3; +wire INV_valid_35; +wire [15:0] INV_output_36_0; +wire [15:0] INV_output_36_1; +wire [15:0] INV_output_36_2; +wire [15:0] INV_output_36_3; +wire INV_valid_36; +wire [15:0] INV_output_37_0; +wire [15:0] INV_output_37_1; +wire [15:0] INV_output_37_2; +wire [15:0] INV_output_37_3; +wire INV_valid_37; +wire [15:0] INV_output_38_0; +wire [15:0] INV_output_38_1; +wire [15:0] INV_output_38_2; +wire [15:0] INV_output_38_3; +wire INV_valid_38; +wire [15:0] INV_output_39_0; +wire [15:0] INV_output_39_1; +wire [15:0] INV_output_39_2; +wire [15:0] INV_output_39_3; +wire INV_valid_39; +wire [15:0] INV_output_40_0; +wire [15:0] INV_output_40_1; +wire [15:0] INV_output_40_2; +wire [15:0] INV_output_40_3; +wire INV_valid_40; +wire [15:0] INV_output_41_0; +wire [15:0] INV_output_41_1; +wire [15:0] INV_output_41_2; +wire [15:0] INV_output_41_3; +wire INV_valid_41; +wire [15:0] INV_output_42_0; +wire [15:0] INV_output_42_1; +wire [15:0] INV_output_42_2; +wire [15:0] INV_output_42_3; +wire INV_valid_42; +wire [15:0] INV_output_43_0; +wire [15:0] INV_output_43_1; +wire [15:0] INV_output_43_2; +wire [15:0] INV_output_43_3; +wire INV_valid_43; +wire [15:0] INV_output_44_0; +wire [15:0] INV_output_44_1; +wire [15:0] INV_output_44_2; +wire [15:0] INV_output_44_3; +wire INV_valid_44; +wire [15:0] INV_output_45_0; +wire [15:0] INV_output_45_1; +wire [15:0] INV_output_45_2; +wire [15:0] INV_output_45_3; +wire INV_valid_45; +wire [15:0] INV_output_46_0; +wire [15:0] INV_output_46_1; +wire [15:0] INV_output_46_2; +wire [15:0] INV_output_46_3; +wire INV_valid_46; +wire [15:0] INV_output_47_0; +wire [15:0] INV_output_47_1; +wire [15:0] INV_output_47_2; +wire [15:0] INV_output_47_3; +wire INV_valid_47; + +// Pooling Wires +wire [15:0] POOL_output_0; +wire POOL_valid_0; +wire [15:0] POOL_output_1; +wire POOL_valid_1; +wire [15:0] POOL_output_2; +wire POOL_valid_2; +wire [15:0] POOL_output_3; +wire POOL_valid_3; +wire [15:0] POOL_output_4; +wire POOL_valid_4; +wire [15:0] POOL_output_5; +wire POOL_valid_5; +wire [15:0] POOL_output_6; +wire POOL_valid_6; +wire [15:0] POOL_output_7; +wire POOL_valid_7; +wire [15:0] POOL_output_8; +wire POOL_valid_8; +wire [15:0] POOL_output_9; +wire POOL_valid_9; +wire [15:0] POOL_output_10; +wire POOL_valid_10; +wire [15:0] POOL_output_11; +wire POOL_valid_11; +wire [15:0] POOL_output_12; +wire POOL_valid_12; +wire [15:0] POOL_output_13; +wire POOL_valid_13; +wire [15:0] POOL_output_14; +wire POOL_valid_14; +wire [15:0] POOL_output_15; +wire POOL_valid_15; +wire [15:0] POOL_output_16; +wire POOL_valid_16; +wire [15:0] POOL_output_17; +wire POOL_valid_17; +wire [15:0] POOL_output_18; +wire POOL_valid_18; +wire [15:0] POOL_output_19; +wire POOL_valid_19; +wire [15:0] POOL_output_20; +wire POOL_valid_20; +wire [15:0] POOL_output_21; +wire POOL_valid_21; +wire [15:0] POOL_output_22; +wire POOL_valid_22; +wire [15:0] POOL_output_23; +wire POOL_valid_23; +wire [15:0] POOL_output_24; +wire POOL_valid_24; +wire [15:0] POOL_output_25; +wire POOL_valid_25; +wire [15:0] POOL_output_26; +wire POOL_valid_26; +wire [15:0] POOL_output_27; +wire POOL_valid_27; +wire [15:0] POOL_output_28; +wire POOL_valid_28; +wire [15:0] POOL_output_29; +wire POOL_valid_29; +wire [15:0] POOL_output_30; +wire POOL_valid_30; +wire [15:0] POOL_output_31; +wire POOL_valid_31; +wire [15:0] POOL_output_32; +wire POOL_valid_32; +wire [15:0] POOL_output_33; +wire POOL_valid_33; +wire [15:0] POOL_output_34; +wire POOL_valid_34; +wire [15:0] POOL_output_35; +wire POOL_valid_35; +wire [15:0] POOL_output_36; +wire POOL_valid_36; +wire [15:0] POOL_output_37; +wire POOL_valid_37; +wire [15:0] POOL_output_38; +wire POOL_valid_38; +wire [15:0] POOL_output_39; +wire POOL_valid_39; +wire [15:0] POOL_output_40; +wire POOL_valid_40; +wire [15:0] POOL_output_41; +wire POOL_valid_41; +wire [15:0] POOL_output_42; +wire POOL_valid_42; +wire [15:0] POOL_output_43; +wire POOL_valid_43; +wire [15:0] POOL_output_44; +wire POOL_valid_44; +wire [15:0] POOL_output_45; +wire POOL_valid_45; +wire [15:0] POOL_output_46; +wire POOL_valid_46; +wire [15:0] POOL_output_47; +wire POOL_valid_47; + +// Store Output Wires +wire [15:0] STORE_output_0_0; +wire [15:0] STORE_output_0_1; +wire [15:0] STORE_output_0_2; +wire [15:0] STORE_output_0_3; +wire [15:0] STORE_output_0_4; +wire [15:0] STORE_output_0_5; +wire [15:0] STORE_output_0_6; +wire [15:0] STORE_output_0_7; +wire [15:0] STORE_output_1_0; +wire [15:0] STORE_output_1_1; +wire [15:0] STORE_output_1_2; +wire [15:0] STORE_output_1_3; +wire [15:0] STORE_output_1_4; +wire [15:0] STORE_output_1_5; +wire [15:0] STORE_output_1_6; +wire [15:0] STORE_output_1_7; +wire [15:0] STORE_output_2_0; +wire [15:0] STORE_output_2_1; +wire [15:0] STORE_output_2_2; +wire [15:0] STORE_output_2_3; +wire [15:0] STORE_output_2_4; +wire [15:0] STORE_output_2_5; +wire [15:0] STORE_output_2_6; +wire [15:0] STORE_output_2_7; +wire [15:0] STORE_output_3_0; +wire [15:0] STORE_output_3_1; +wire [15:0] STORE_output_3_2; +wire [15:0] STORE_output_3_3; +wire [15:0] STORE_output_3_4; +wire [15:0] STORE_output_3_5; +wire [15:0] STORE_output_3_6; +wire [15:0] STORE_output_3_7; +wire [15:0] STORE_output_4_0; +wire [15:0] STORE_output_4_1; +wire [15:0] STORE_output_4_2; +wire [15:0] STORE_output_4_3; +wire [15:0] STORE_output_4_4; +wire [15:0] STORE_output_4_5; +wire [15:0] STORE_output_4_6; +wire [15:0] STORE_output_4_7; +wire [15:0] STORE_output_5_0; +wire [15:0] STORE_output_5_1; +wire [15:0] STORE_output_5_2; +wire [15:0] STORE_output_5_3; +wire [15:0] STORE_output_5_4; +wire [15:0] STORE_output_5_5; +wire [15:0] STORE_output_5_6; +wire [15:0] STORE_output_5_7; +wire [12:0] STORE_addr; +wire STORE_wen_0; +wire STORE_wen_1; +wire STORE_wen_2; +wire STORE_wen_3; +wire STORE_wen_4; +wire STORE_wen_5; + +// Eltwise Wires +wire [15:0] f_buffer_el_0_0; +wire [15:0] f_buffer_el_0_1; +wire [15:0] f_buffer_el_0_2; +wire [15:0] f_buffer_el_0_3; +wire [15:0] f_buffer_el_0_4; +wire [15:0] f_buffer_el_0_5; +wire [15:0] f_buffer_el_0_6; +wire [15:0] f_buffer_el_0_7; +wire [15:0] f_buffer_el_1_0; +wire [15:0] f_buffer_el_1_1; +wire [15:0] f_buffer_el_1_2; +wire [15:0] f_buffer_el_1_3; +wire [15:0] f_buffer_el_1_4; +wire [15:0] f_buffer_el_1_5; +wire [15:0] f_buffer_el_1_6; +wire [15:0] f_buffer_el_1_7; +wire [15:0] f_buffer_el_2_0; +wire [15:0] f_buffer_el_2_1; +wire [15:0] f_buffer_el_2_2; +wire [15:0] f_buffer_el_2_3; +wire [15:0] f_buffer_el_2_4; +wire [15:0] f_buffer_el_2_5; +wire [15:0] f_buffer_el_2_6; +wire [15:0] f_buffer_el_2_7; +wire [15:0] f_buffer_el_3_0; +wire [15:0] f_buffer_el_3_1; +wire [15:0] f_buffer_el_3_2; +wire [15:0] f_buffer_el_3_3; +wire [15:0] f_buffer_el_3_4; +wire [15:0] f_buffer_el_3_5; +wire [15:0] f_buffer_el_3_6; +wire [15:0] f_buffer_el_3_7; +wire [15:0] f_buffer_el_4_0; +wire [15:0] f_buffer_el_4_1; +wire [15:0] f_buffer_el_4_2; +wire [15:0] f_buffer_el_4_3; +wire [15:0] f_buffer_el_4_4; +wire [15:0] f_buffer_el_4_5; +wire [15:0] f_buffer_el_4_6; +wire [15:0] f_buffer_el_4_7; +wire [15:0] f_buffer_el_5_0; +wire [15:0] f_buffer_el_5_1; +wire [15:0] f_buffer_el_5_2; +wire [15:0] f_buffer_el_5_3; +wire [15:0] f_buffer_el_5_4; +wire [15:0] f_buffer_el_5_5; +wire [15:0] f_buffer_el_5_6; +wire [15:0] f_buffer_el_5_7; + +// Output Wires +wire [15:0] dummy_out_0_0; +wire [15:0] dummy_out_0_1; +wire [15:0] dummy_out_0_2; +wire [15:0] dummy_out_0_3; +wire [15:0] dummy_out_0_4; +wire [15:0] dummy_out_0_5; +wire [15:0] dummy_out_0_6; +wire [15:0] dummy_out_0_7; +wire [15:0] dummy_out_1_0; +wire [15:0] dummy_out_1_1; +wire [15:0] dummy_out_1_2; +wire [15:0] dummy_out_1_3; +wire [15:0] dummy_out_1_4; +wire [15:0] dummy_out_1_5; +wire [15:0] dummy_out_1_6; +wire [15:0] dummy_out_1_7; +wire [15:0] dummy_out_2_0; +wire [15:0] dummy_out_2_1; +wire [15:0] dummy_out_2_2; +wire [15:0] dummy_out_2_3; +wire [15:0] dummy_out_2_4; +wire [15:0] dummy_out_2_5; +wire [15:0] dummy_out_2_6; +wire [15:0] dummy_out_2_7; +wire [15:0] dummy_out_3_0; +wire [15:0] dummy_out_3_1; +wire [15:0] dummy_out_3_2; +wire [15:0] dummy_out_3_3; +wire [15:0] dummy_out_3_4; +wire [15:0] dummy_out_3_5; +wire [15:0] dummy_out_3_6; +wire [15:0] dummy_out_3_7; +wire [15:0] dummy_out_4_0; +wire [15:0] dummy_out_4_1; +wire [15:0] dummy_out_4_2; +wire [15:0] dummy_out_4_3; +wire [15:0] dummy_out_4_4; +wire [15:0] dummy_out_4_5; +wire [15:0] dummy_out_4_6; +wire [15:0] dummy_out_4_7; +wire [15:0] dummy_out_5_0; +wire [15:0] dummy_out_5_1; +wire [15:0] dummy_out_5_2; +wire [15:0] dummy_out_5_3; +wire [15:0] dummy_out_5_4; +wire [15:0] dummy_out_5_5; +wire [15:0] dummy_out_5_6; +wire [15:0] dummy_out_5_7; + +stream_buffer_0_0 stream_buffer_0_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_0_0), + .i_wen1(STORE_wen_0), + .i_ddr(i_ddr_0_0), + .i_pool(STORE_output_0_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_0_0), + .o_feature_1(f_buffer_el_0_0), + .o_done(valid_buff_0_0) +); +assign dummy_out_0_0 = f_buffer_el_0_0; + +stream_buffer_0_1 stream_buffer_0_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_0_1), + .i_wen1(STORE_wen_0), + .i_ddr(i_ddr_0_1), + .i_pool(STORE_output_0_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_0_1), + .o_feature_1(f_buffer_el_0_1), + .o_done(valid_buff_0_1) +); +assign dummy_out_0_1 = f_buffer_el_0_1; + +stream_buffer_0_2 stream_buffer_0_2_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_0_2), + .i_wen1(STORE_wen_0), + .i_ddr(i_ddr_0_2), + .i_pool(STORE_output_0_2), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_0_2), + .o_feature_1(f_buffer_el_0_2), + .o_done(valid_buff_0_2) +); +assign dummy_out_0_2 = f_buffer_el_0_2; + +stream_buffer_0_3 stream_buffer_0_3_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_0_3), + .i_wen1(STORE_wen_0), + .i_ddr(i_ddr_0_3), + .i_pool(STORE_output_0_3), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_0_3), + .o_feature_1(f_buffer_el_0_3), + .o_done(valid_buff_0_3) +); +assign dummy_out_0_3 = f_buffer_el_0_3; + +stream_buffer_0_4 stream_buffer_0_4_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_0_4), + .i_wen1(STORE_wen_0), + .i_ddr(i_ddr_0_4), + .i_pool(STORE_output_0_4), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_0_4), + .o_feature_1(f_buffer_el_0_4), + .o_done(valid_buff_0_4) +); +assign dummy_out_0_4 = f_buffer_el_0_4; + +stream_buffer_0_5 stream_buffer_0_5_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_0_5), + .i_wen1(STORE_wen_0), + .i_ddr(i_ddr_0_5), + .i_pool(STORE_output_0_5), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_0_5), + .o_feature_1(f_buffer_el_0_5), + .o_done(valid_buff_0_5) +); +assign dummy_out_0_5 = f_buffer_el_0_5; + +stream_buffer_0_6 stream_buffer_0_6_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_0_6), + .i_wen1(STORE_wen_0), + .i_ddr(i_ddr_0_6), + .i_pool(STORE_output_0_6), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_0_6), + .o_feature_1(f_buffer_el_0_6), + .o_done(valid_buff_0_6) +); +assign dummy_out_0_6 = f_buffer_el_0_6; + +stream_buffer_0_7 stream_buffer_0_7_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_0_7), + .i_wen1(STORE_wen_0), + .i_ddr(i_ddr_0_7), + .i_pool(STORE_output_0_7), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_0_7), + .o_feature_1(f_buffer_el_0_7), + .o_done(valid_buff_0_7) +); +assign dummy_out_0_7 = f_buffer_el_0_7; + +stream_buffer_1_0 stream_buffer_1_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_1_0), + .i_wen1(STORE_wen_1), + .i_ddr(i_ddr_1_0), + .i_pool(STORE_output_1_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_1_0), + .o_feature_1(f_buffer_el_1_0), + .o_done(valid_buff_1_0) +); +assign dummy_out_1_0 = f_buffer_el_1_0; + +stream_buffer_1_1 stream_buffer_1_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_1_1), + .i_wen1(STORE_wen_1), + .i_ddr(i_ddr_1_1), + .i_pool(STORE_output_1_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_1_1), + .o_feature_1(f_buffer_el_1_1), + .o_done(valid_buff_1_1) +); +assign dummy_out_1_1 = f_buffer_el_1_1; + +stream_buffer_1_2 stream_buffer_1_2_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_1_2), + .i_wen1(STORE_wen_1), + .i_ddr(i_ddr_1_2), + .i_pool(STORE_output_1_2), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_1_2), + .o_feature_1(f_buffer_el_1_2), + .o_done(valid_buff_1_2) +); +assign dummy_out_1_2 = f_buffer_el_1_2; + +stream_buffer_1_3 stream_buffer_1_3_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_1_3), + .i_wen1(STORE_wen_1), + .i_ddr(i_ddr_1_3), + .i_pool(STORE_output_1_3), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_1_3), + .o_feature_1(f_buffer_el_1_3), + .o_done(valid_buff_1_3) +); +assign dummy_out_1_3 = f_buffer_el_1_3; + +stream_buffer_1_4 stream_buffer_1_4_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_1_4), + .i_wen1(STORE_wen_1), + .i_ddr(i_ddr_1_4), + .i_pool(STORE_output_1_4), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_1_4), + .o_feature_1(f_buffer_el_1_4), + .o_done(valid_buff_1_4) +); +assign dummy_out_1_4 = f_buffer_el_1_4; + +stream_buffer_1_5 stream_buffer_1_5_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_1_5), + .i_wen1(STORE_wen_1), + .i_ddr(i_ddr_1_5), + .i_pool(STORE_output_1_5), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_1_5), + .o_feature_1(f_buffer_el_1_5), + .o_done(valid_buff_1_5) +); +assign dummy_out_1_5 = f_buffer_el_1_5; + +stream_buffer_1_6 stream_buffer_1_6_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_1_6), + .i_wen1(STORE_wen_1), + .i_ddr(i_ddr_1_6), + .i_pool(STORE_output_1_6), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_1_6), + .o_feature_1(f_buffer_el_1_6), + .o_done(valid_buff_1_6) +); +assign dummy_out_1_6 = f_buffer_el_1_6; + +stream_buffer_1_7 stream_buffer_1_7_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_1_7), + .i_wen1(STORE_wen_1), + .i_ddr(i_ddr_1_7), + .i_pool(STORE_output_1_7), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_1_7), + .o_feature_1(f_buffer_el_1_7), + .o_done(valid_buff_1_7) +); +assign dummy_out_1_7 = f_buffer_el_1_7; + +stream_buffer_2_0 stream_buffer_2_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_2_0), + .i_wen1(STORE_wen_2), + .i_ddr(i_ddr_2_0), + .i_pool(STORE_output_2_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_2_0), + .o_feature_1(f_buffer_el_2_0), + .o_done(valid_buff_2_0) +); +assign dummy_out_2_0 = f_buffer_el_2_0; + +stream_buffer_2_1 stream_buffer_2_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_2_1), + .i_wen1(STORE_wen_2), + .i_ddr(i_ddr_2_1), + .i_pool(STORE_output_2_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_2_1), + .o_feature_1(f_buffer_el_2_1), + .o_done(valid_buff_2_1) +); +assign dummy_out_2_1 = f_buffer_el_2_1; + +stream_buffer_2_2 stream_buffer_2_2_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_2_2), + .i_wen1(STORE_wen_2), + .i_ddr(i_ddr_2_2), + .i_pool(STORE_output_2_2), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_2_2), + .o_feature_1(f_buffer_el_2_2), + .o_done(valid_buff_2_2) +); +assign dummy_out_2_2 = f_buffer_el_2_2; + +stream_buffer_2_3 stream_buffer_2_3_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_2_3), + .i_wen1(STORE_wen_2), + .i_ddr(i_ddr_2_3), + .i_pool(STORE_output_2_3), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_2_3), + .o_feature_1(f_buffer_el_2_3), + .o_done(valid_buff_2_3) +); +assign dummy_out_2_3 = f_buffer_el_2_3; + +stream_buffer_2_4 stream_buffer_2_4_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_2_4), + .i_wen1(STORE_wen_2), + .i_ddr(i_ddr_2_4), + .i_pool(STORE_output_2_4), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_2_4), + .o_feature_1(f_buffer_el_2_4), + .o_done(valid_buff_2_4) +); +assign dummy_out_2_4 = f_buffer_el_2_4; + +stream_buffer_2_5 stream_buffer_2_5_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_2_5), + .i_wen1(STORE_wen_2), + .i_ddr(i_ddr_2_5), + .i_pool(STORE_output_2_5), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_2_5), + .o_feature_1(f_buffer_el_2_5), + .o_done(valid_buff_2_5) +); +assign dummy_out_2_5 = f_buffer_el_2_5; + +stream_buffer_2_6 stream_buffer_2_6_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_2_6), + .i_wen1(STORE_wen_2), + .i_ddr(i_ddr_2_6), + .i_pool(STORE_output_2_6), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_2_6), + .o_feature_1(f_buffer_el_2_6), + .o_done(valid_buff_2_6) +); +assign dummy_out_2_6 = f_buffer_el_2_6; + +stream_buffer_2_7 stream_buffer_2_7_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_2_7), + .i_wen1(STORE_wen_2), + .i_ddr(i_ddr_2_7), + .i_pool(STORE_output_2_7), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_2_7), + .o_feature_1(f_buffer_el_2_7), + .o_done(valid_buff_2_7) +); +assign dummy_out_2_7 = f_buffer_el_2_7; + +stream_buffer_3_0 stream_buffer_3_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_3_0), + .i_wen1(STORE_wen_3), + .i_ddr(i_ddr_3_0), + .i_pool(STORE_output_3_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_3_0), + .o_feature_1(f_buffer_el_3_0), + .o_done(valid_buff_3_0) +); +assign dummy_out_3_0 = f_buffer_el_3_0; + +stream_buffer_3_1 stream_buffer_3_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_3_1), + .i_wen1(STORE_wen_3), + .i_ddr(i_ddr_3_1), + .i_pool(STORE_output_3_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_3_1), + .o_feature_1(f_buffer_el_3_1), + .o_done(valid_buff_3_1) +); +assign dummy_out_3_1 = f_buffer_el_3_1; + +stream_buffer_3_2 stream_buffer_3_2_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_3_2), + .i_wen1(STORE_wen_3), + .i_ddr(i_ddr_3_2), + .i_pool(STORE_output_3_2), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_3_2), + .o_feature_1(f_buffer_el_3_2), + .o_done(valid_buff_3_2) +); +assign dummy_out_3_2 = f_buffer_el_3_2; + +stream_buffer_3_3 stream_buffer_3_3_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_3_3), + .i_wen1(STORE_wen_3), + .i_ddr(i_ddr_3_3), + .i_pool(STORE_output_3_3), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_3_3), + .o_feature_1(f_buffer_el_3_3), + .o_done(valid_buff_3_3) +); +assign dummy_out_3_3 = f_buffer_el_3_3; + +stream_buffer_3_4 stream_buffer_3_4_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_3_4), + .i_wen1(STORE_wen_3), + .i_ddr(i_ddr_3_4), + .i_pool(STORE_output_3_4), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_3_4), + .o_feature_1(f_buffer_el_3_4), + .o_done(valid_buff_3_4) +); +assign dummy_out_3_4 = f_buffer_el_3_4; + +stream_buffer_3_5 stream_buffer_3_5_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_3_5), + .i_wen1(STORE_wen_3), + .i_ddr(i_ddr_3_5), + .i_pool(STORE_output_3_5), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_3_5), + .o_feature_1(f_buffer_el_3_5), + .o_done(valid_buff_3_5) +); +assign dummy_out_3_5 = f_buffer_el_3_5; + +stream_buffer_3_6 stream_buffer_3_6_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_3_6), + .i_wen1(STORE_wen_3), + .i_ddr(i_ddr_3_6), + .i_pool(STORE_output_3_6), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_3_6), + .o_feature_1(f_buffer_el_3_6), + .o_done(valid_buff_3_6) +); +assign dummy_out_3_6 = f_buffer_el_3_6; + +stream_buffer_3_7 stream_buffer_3_7_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_3_7), + .i_wen1(STORE_wen_3), + .i_ddr(i_ddr_3_7), + .i_pool(STORE_output_3_7), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_3_7), + .o_feature_1(f_buffer_el_3_7), + .o_done(valid_buff_3_7) +); +assign dummy_out_3_7 = f_buffer_el_3_7; + +stream_buffer_4_0 stream_buffer_4_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_4_0), + .i_wen1(STORE_wen_4), + .i_ddr(i_ddr_4_0), + .i_pool(STORE_output_4_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_4_0), + .o_feature_1(f_buffer_el_4_0), + .o_done(valid_buff_4_0) +); +assign dummy_out_4_0 = f_buffer_el_4_0; + +stream_buffer_4_1 stream_buffer_4_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_4_1), + .i_wen1(STORE_wen_4), + .i_ddr(i_ddr_4_1), + .i_pool(STORE_output_4_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_4_1), + .o_feature_1(f_buffer_el_4_1), + .o_done(valid_buff_4_1) +); +assign dummy_out_4_1 = f_buffer_el_4_1; + +stream_buffer_4_2 stream_buffer_4_2_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_4_2), + .i_wen1(STORE_wen_4), + .i_ddr(i_ddr_4_2), + .i_pool(STORE_output_4_2), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_4_2), + .o_feature_1(f_buffer_el_4_2), + .o_done(valid_buff_4_2) +); +assign dummy_out_4_2 = f_buffer_el_4_2; + +stream_buffer_4_3 stream_buffer_4_3_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_4_3), + .i_wen1(STORE_wen_4), + .i_ddr(i_ddr_4_3), + .i_pool(STORE_output_4_3), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_4_3), + .o_feature_1(f_buffer_el_4_3), + .o_done(valid_buff_4_3) +); +assign dummy_out_4_3 = f_buffer_el_4_3; + +stream_buffer_4_4 stream_buffer_4_4_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_4_4), + .i_wen1(STORE_wen_4), + .i_ddr(i_ddr_4_4), + .i_pool(STORE_output_4_4), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_4_4), + .o_feature_1(f_buffer_el_4_4), + .o_done(valid_buff_4_4) +); +assign dummy_out_4_4 = f_buffer_el_4_4; + +stream_buffer_4_5 stream_buffer_4_5_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_4_5), + .i_wen1(STORE_wen_4), + .i_ddr(i_ddr_4_5), + .i_pool(STORE_output_4_5), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_4_5), + .o_feature_1(f_buffer_el_4_5), + .o_done(valid_buff_4_5) +); +assign dummy_out_4_5 = f_buffer_el_4_5; + +stream_buffer_4_6 stream_buffer_4_6_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_4_6), + .i_wen1(STORE_wen_4), + .i_ddr(i_ddr_4_6), + .i_pool(STORE_output_4_6), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_4_6), + .o_feature_1(f_buffer_el_4_6), + .o_done(valid_buff_4_6) +); +assign dummy_out_4_6 = f_buffer_el_4_6; + +stream_buffer_4_7 stream_buffer_4_7_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_4_7), + .i_wen1(STORE_wen_4), + .i_ddr(i_ddr_4_7), + .i_pool(STORE_output_4_7), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_4_7), + .o_feature_1(f_buffer_el_4_7), + .o_done(valid_buff_4_7) +); +assign dummy_out_4_7 = f_buffer_el_4_7; + +stream_buffer_5_0 stream_buffer_5_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_5_0), + .i_wen1(STORE_wen_5), + .i_ddr(i_ddr_5_0), + .i_pool(STORE_output_5_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_5_0), + .o_feature_1(f_buffer_el_5_0), + .o_done(valid_buff_5_0) +); +assign dummy_out_5_0 = f_buffer_el_5_0; + +stream_buffer_5_1 stream_buffer_5_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_5_1), + .i_wen1(STORE_wen_5), + .i_ddr(i_ddr_5_1), + .i_pool(STORE_output_5_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_5_1), + .o_feature_1(f_buffer_el_5_1), + .o_done(valid_buff_5_1) +); +assign dummy_out_5_1 = f_buffer_el_5_1; + +stream_buffer_5_2 stream_buffer_5_2_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_5_2), + .i_wen1(STORE_wen_5), + .i_ddr(i_ddr_5_2), + .i_pool(STORE_output_5_2), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_5_2), + .o_feature_1(f_buffer_el_5_2), + .o_done(valid_buff_5_2) +); +assign dummy_out_5_2 = f_buffer_el_5_2; + +stream_buffer_5_3 stream_buffer_5_3_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_5_3), + .i_wen1(STORE_wen_5), + .i_ddr(i_ddr_5_3), + .i_pool(STORE_output_5_3), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_5_3), + .o_feature_1(f_buffer_el_5_3), + .o_done(valid_buff_5_3) +); +assign dummy_out_5_3 = f_buffer_el_5_3; + +stream_buffer_5_4 stream_buffer_5_4_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_5_4), + .i_wen1(STORE_wen_5), + .i_ddr(i_ddr_5_4), + .i_pool(STORE_output_5_4), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_5_4), + .o_feature_1(f_buffer_el_5_4), + .o_done(valid_buff_5_4) +); +assign dummy_out_5_4 = f_buffer_el_5_4; + +stream_buffer_5_5 stream_buffer_5_5_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_5_5), + .i_wen1(STORE_wen_5), + .i_ddr(i_ddr_5_5), + .i_pool(STORE_output_5_5), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_5_5), + .o_feature_1(f_buffer_el_5_5), + .o_done(valid_buff_5_5) +); +assign dummy_out_5_5 = f_buffer_el_5_5; + +stream_buffer_5_6 stream_buffer_5_6_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_5_6), + .i_wen1(STORE_wen_5), + .i_ddr(i_ddr_5_6), + .i_pool(STORE_output_5_6), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_5_6), + .o_feature_1(f_buffer_el_5_6), + .o_done(valid_buff_5_6) +); +assign dummy_out_5_6 = f_buffer_el_5_6; + +stream_buffer_5_7 stream_buffer_5_7_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_5_7), + .i_wen1(STORE_wen_5), + .i_ddr(i_ddr_5_7), + .i_pool(STORE_output_5_7), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_5_7), + .o_feature_1(f_buffer_el_5_7), + .o_done(valid_buff_5_7) +); +assign dummy_out_5_7 = f_buffer_el_5_7; + +winograd_transform_0 winograd_transform_0_inst ( + .clk(clk), + .i_valid(valid_buff_0_0), + .i_result_0_0(f_buffer_pe_0_0), + .i_result_0_1(f_buffer_pe_0_1), + .i_result_0_2(f_buffer_pe_0_2), + .i_result_0_3(f_buffer_pe_0_3), + .i_result_0_4(f_buffer_pe_0_4), + .i_result_0_5(f_buffer_pe_0_5), + .i_result_0_6(f_buffer_pe_0_6), + .i_result_0_7(f_buffer_pe_0_7), + .i_result_1_0(f_buffer_pe_1_0), + .i_result_1_1(f_buffer_pe_1_1), + .i_result_1_2(f_buffer_pe_1_2), + .i_result_1_3(f_buffer_pe_1_3), + .i_result_1_4(f_buffer_pe_1_4), + .i_result_1_5(f_buffer_pe_1_5), + .i_result_1_6(f_buffer_pe_1_6), + .i_result_1_7(f_buffer_pe_1_7), + .i_result_2_0(f_buffer_pe_2_0), + .i_result_2_1(f_buffer_pe_2_1), + .i_result_2_2(f_buffer_pe_2_2), + .i_result_2_3(f_buffer_pe_2_3), + .i_result_2_4(f_buffer_pe_2_4), + .i_result_2_5(f_buffer_pe_2_5), + .i_result_2_6(f_buffer_pe_2_6), + .i_result_2_7(f_buffer_pe_2_7), + .i_result_3_0(f_buffer_pe_3_0), + .i_result_3_1(f_buffer_pe_3_1), + .i_result_3_2(f_buffer_pe_3_2), + .i_result_3_3(f_buffer_pe_3_3), + .i_result_3_4(f_buffer_pe_3_4), + .i_result_3_5(f_buffer_pe_3_5), + .i_result_3_6(f_buffer_pe_3_6), + .i_result_3_7(f_buffer_pe_3_7), + .i_result_4_0(f_buffer_pe_4_0), + .i_result_4_1(f_buffer_pe_4_1), + .i_result_4_2(f_buffer_pe_4_2), + .i_result_4_3(f_buffer_pe_4_3), + .i_result_4_4(f_buffer_pe_4_4), + .i_result_4_5(f_buffer_pe_4_5), + .i_result_4_6(f_buffer_pe_4_6), + .i_result_4_7(f_buffer_pe_4_7), + .i_result_5_0(f_buffer_pe_5_0), + .i_result_5_1(f_buffer_pe_5_1), + .i_result_5_2(f_buffer_pe_5_2), + .i_result_5_3(f_buffer_pe_5_3), + .i_result_5_4(f_buffer_pe_5_4), + .i_result_5_5(f_buffer_pe_5_5), + .i_result_5_6(f_buffer_pe_5_6), + .i_result_5_7(f_buffer_pe_5_7), + .o_feature_0(f_winograd_0_0), + .o_feature_1(f_winograd_0_1), + .o_feature_2(f_winograd_0_2), + .o_feature_3(f_winograd_0_3), + .o_feature_4(f_winograd_0_4), + .o_feature_5(f_winograd_0_5), + .o_valid(winograd_valid_0) +); + +winograd_transform_1 winograd_transform_1_inst ( + .clk(clk), + .i_valid(valid_buff_0_0), + .i_result_0_0(f_buffer_pe_0_0), + .i_result_0_1(f_buffer_pe_0_1), + .i_result_0_2(f_buffer_pe_0_2), + .i_result_0_3(f_buffer_pe_0_3), + .i_result_0_4(f_buffer_pe_0_4), + .i_result_0_5(f_buffer_pe_0_5), + .i_result_0_6(f_buffer_pe_0_6), + .i_result_0_7(f_buffer_pe_0_7), + .i_result_1_0(f_buffer_pe_1_0), + .i_result_1_1(f_buffer_pe_1_1), + .i_result_1_2(f_buffer_pe_1_2), + .i_result_1_3(f_buffer_pe_1_3), + .i_result_1_4(f_buffer_pe_1_4), + .i_result_1_5(f_buffer_pe_1_5), + .i_result_1_6(f_buffer_pe_1_6), + .i_result_1_7(f_buffer_pe_1_7), + .i_result_2_0(f_buffer_pe_2_0), + .i_result_2_1(f_buffer_pe_2_1), + .i_result_2_2(f_buffer_pe_2_2), + .i_result_2_3(f_buffer_pe_2_3), + .i_result_2_4(f_buffer_pe_2_4), + .i_result_2_5(f_buffer_pe_2_5), + .i_result_2_6(f_buffer_pe_2_6), + .i_result_2_7(f_buffer_pe_2_7), + .i_result_3_0(f_buffer_pe_3_0), + .i_result_3_1(f_buffer_pe_3_1), + .i_result_3_2(f_buffer_pe_3_2), + .i_result_3_3(f_buffer_pe_3_3), + .i_result_3_4(f_buffer_pe_3_4), + .i_result_3_5(f_buffer_pe_3_5), + .i_result_3_6(f_buffer_pe_3_6), + .i_result_3_7(f_buffer_pe_3_7), + .i_result_4_0(f_buffer_pe_4_0), + .i_result_4_1(f_buffer_pe_4_1), + .i_result_4_2(f_buffer_pe_4_2), + .i_result_4_3(f_buffer_pe_4_3), + .i_result_4_4(f_buffer_pe_4_4), + .i_result_4_5(f_buffer_pe_4_5), + .i_result_4_6(f_buffer_pe_4_6), + .i_result_4_7(f_buffer_pe_4_7), + .i_result_5_0(f_buffer_pe_5_0), + .i_result_5_1(f_buffer_pe_5_1), + .i_result_5_2(f_buffer_pe_5_2), + .i_result_5_3(f_buffer_pe_5_3), + .i_result_5_4(f_buffer_pe_5_4), + .i_result_5_5(f_buffer_pe_5_5), + .i_result_5_6(f_buffer_pe_5_6), + .i_result_5_7(f_buffer_pe_5_7), + .o_feature_0(f_winograd_1_0), + .o_feature_1(f_winograd_1_1), + .o_feature_2(f_winograd_1_2), + .o_feature_3(f_winograd_1_3), + .o_feature_4(f_winograd_1_4), + .o_feature_5(f_winograd_1_5), + .o_valid(winograd_valid_1) +); + +winograd_transform_2 winograd_transform_2_inst ( + .clk(clk), + .i_valid(valid_buff_0_0), + .i_result_0_0(f_buffer_pe_0_0), + .i_result_0_1(f_buffer_pe_0_1), + .i_result_0_2(f_buffer_pe_0_2), + .i_result_0_3(f_buffer_pe_0_3), + .i_result_0_4(f_buffer_pe_0_4), + .i_result_0_5(f_buffer_pe_0_5), + .i_result_0_6(f_buffer_pe_0_6), + .i_result_0_7(f_buffer_pe_0_7), + .i_result_1_0(f_buffer_pe_1_0), + .i_result_1_1(f_buffer_pe_1_1), + .i_result_1_2(f_buffer_pe_1_2), + .i_result_1_3(f_buffer_pe_1_3), + .i_result_1_4(f_buffer_pe_1_4), + .i_result_1_5(f_buffer_pe_1_5), + .i_result_1_6(f_buffer_pe_1_6), + .i_result_1_7(f_buffer_pe_1_7), + .i_result_2_0(f_buffer_pe_2_0), + .i_result_2_1(f_buffer_pe_2_1), + .i_result_2_2(f_buffer_pe_2_2), + .i_result_2_3(f_buffer_pe_2_3), + .i_result_2_4(f_buffer_pe_2_4), + .i_result_2_5(f_buffer_pe_2_5), + .i_result_2_6(f_buffer_pe_2_6), + .i_result_2_7(f_buffer_pe_2_7), + .i_result_3_0(f_buffer_pe_3_0), + .i_result_3_1(f_buffer_pe_3_1), + .i_result_3_2(f_buffer_pe_3_2), + .i_result_3_3(f_buffer_pe_3_3), + .i_result_3_4(f_buffer_pe_3_4), + .i_result_3_5(f_buffer_pe_3_5), + .i_result_3_6(f_buffer_pe_3_6), + .i_result_3_7(f_buffer_pe_3_7), + .i_result_4_0(f_buffer_pe_4_0), + .i_result_4_1(f_buffer_pe_4_1), + .i_result_4_2(f_buffer_pe_4_2), + .i_result_4_3(f_buffer_pe_4_3), + .i_result_4_4(f_buffer_pe_4_4), + .i_result_4_5(f_buffer_pe_4_5), + .i_result_4_6(f_buffer_pe_4_6), + .i_result_4_7(f_buffer_pe_4_7), + .i_result_5_0(f_buffer_pe_5_0), + .i_result_5_1(f_buffer_pe_5_1), + .i_result_5_2(f_buffer_pe_5_2), + .i_result_5_3(f_buffer_pe_5_3), + .i_result_5_4(f_buffer_pe_5_4), + .i_result_5_5(f_buffer_pe_5_5), + .i_result_5_6(f_buffer_pe_5_6), + .i_result_5_7(f_buffer_pe_5_7), + .o_feature_0(f_winograd_2_0), + .o_feature_1(f_winograd_2_1), + .o_feature_2(f_winograd_2_2), + .o_feature_3(f_winograd_2_3), + .o_feature_4(f_winograd_2_4), + .o_feature_5(f_winograd_2_5), + .o_valid(winograd_valid_2) +); + +winograd_transform_3 winograd_transform_3_inst ( + .clk(clk), + .i_valid(valid_buff_0_0), + .i_result_0_0(f_buffer_pe_0_0), + .i_result_0_1(f_buffer_pe_0_1), + .i_result_0_2(f_buffer_pe_0_2), + .i_result_0_3(f_buffer_pe_0_3), + .i_result_0_4(f_buffer_pe_0_4), + .i_result_0_5(f_buffer_pe_0_5), + .i_result_0_6(f_buffer_pe_0_6), + .i_result_0_7(f_buffer_pe_0_7), + .i_result_1_0(f_buffer_pe_1_0), + .i_result_1_1(f_buffer_pe_1_1), + .i_result_1_2(f_buffer_pe_1_2), + .i_result_1_3(f_buffer_pe_1_3), + .i_result_1_4(f_buffer_pe_1_4), + .i_result_1_5(f_buffer_pe_1_5), + .i_result_1_6(f_buffer_pe_1_6), + .i_result_1_7(f_buffer_pe_1_7), + .i_result_2_0(f_buffer_pe_2_0), + .i_result_2_1(f_buffer_pe_2_1), + .i_result_2_2(f_buffer_pe_2_2), + .i_result_2_3(f_buffer_pe_2_3), + .i_result_2_4(f_buffer_pe_2_4), + .i_result_2_5(f_buffer_pe_2_5), + .i_result_2_6(f_buffer_pe_2_6), + .i_result_2_7(f_buffer_pe_2_7), + .i_result_3_0(f_buffer_pe_3_0), + .i_result_3_1(f_buffer_pe_3_1), + .i_result_3_2(f_buffer_pe_3_2), + .i_result_3_3(f_buffer_pe_3_3), + .i_result_3_4(f_buffer_pe_3_4), + .i_result_3_5(f_buffer_pe_3_5), + .i_result_3_6(f_buffer_pe_3_6), + .i_result_3_7(f_buffer_pe_3_7), + .i_result_4_0(f_buffer_pe_4_0), + .i_result_4_1(f_buffer_pe_4_1), + .i_result_4_2(f_buffer_pe_4_2), + .i_result_4_3(f_buffer_pe_4_3), + .i_result_4_4(f_buffer_pe_4_4), + .i_result_4_5(f_buffer_pe_4_5), + .i_result_4_6(f_buffer_pe_4_6), + .i_result_4_7(f_buffer_pe_4_7), + .i_result_5_0(f_buffer_pe_5_0), + .i_result_5_1(f_buffer_pe_5_1), + .i_result_5_2(f_buffer_pe_5_2), + .i_result_5_3(f_buffer_pe_5_3), + .i_result_5_4(f_buffer_pe_5_4), + .i_result_5_5(f_buffer_pe_5_5), + .i_result_5_6(f_buffer_pe_5_6), + .i_result_5_7(f_buffer_pe_5_7), + .o_feature_0(f_winograd_3_0), + .o_feature_1(f_winograd_3_1), + .o_feature_2(f_winograd_3_2), + .o_feature_3(f_winograd_3_3), + .o_feature_4(f_winograd_3_4), + .o_feature_5(f_winograd_3_5), + .o_valid(winograd_valid_3) +); + +winograd_transform_4 winograd_transform_4_inst ( + .clk(clk), + .i_valid(valid_buff_0_0), + .i_result_0_0(f_buffer_pe_0_0), + .i_result_0_1(f_buffer_pe_0_1), + .i_result_0_2(f_buffer_pe_0_2), + .i_result_0_3(f_buffer_pe_0_3), + .i_result_0_4(f_buffer_pe_0_4), + .i_result_0_5(f_buffer_pe_0_5), + .i_result_0_6(f_buffer_pe_0_6), + .i_result_0_7(f_buffer_pe_0_7), + .i_result_1_0(f_buffer_pe_1_0), + .i_result_1_1(f_buffer_pe_1_1), + .i_result_1_2(f_buffer_pe_1_2), + .i_result_1_3(f_buffer_pe_1_3), + .i_result_1_4(f_buffer_pe_1_4), + .i_result_1_5(f_buffer_pe_1_5), + .i_result_1_6(f_buffer_pe_1_6), + .i_result_1_7(f_buffer_pe_1_7), + .i_result_2_0(f_buffer_pe_2_0), + .i_result_2_1(f_buffer_pe_2_1), + .i_result_2_2(f_buffer_pe_2_2), + .i_result_2_3(f_buffer_pe_2_3), + .i_result_2_4(f_buffer_pe_2_4), + .i_result_2_5(f_buffer_pe_2_5), + .i_result_2_6(f_buffer_pe_2_6), + .i_result_2_7(f_buffer_pe_2_7), + .i_result_3_0(f_buffer_pe_3_0), + .i_result_3_1(f_buffer_pe_3_1), + .i_result_3_2(f_buffer_pe_3_2), + .i_result_3_3(f_buffer_pe_3_3), + .i_result_3_4(f_buffer_pe_3_4), + .i_result_3_5(f_buffer_pe_3_5), + .i_result_3_6(f_buffer_pe_3_6), + .i_result_3_7(f_buffer_pe_3_7), + .i_result_4_0(f_buffer_pe_4_0), + .i_result_4_1(f_buffer_pe_4_1), + .i_result_4_2(f_buffer_pe_4_2), + .i_result_4_3(f_buffer_pe_4_3), + .i_result_4_4(f_buffer_pe_4_4), + .i_result_4_5(f_buffer_pe_4_5), + .i_result_4_6(f_buffer_pe_4_6), + .i_result_4_7(f_buffer_pe_4_7), + .i_result_5_0(f_buffer_pe_5_0), + .i_result_5_1(f_buffer_pe_5_1), + .i_result_5_2(f_buffer_pe_5_2), + .i_result_5_3(f_buffer_pe_5_3), + .i_result_5_4(f_buffer_pe_5_4), + .i_result_5_5(f_buffer_pe_5_5), + .i_result_5_6(f_buffer_pe_5_6), + .i_result_5_7(f_buffer_pe_5_7), + .o_feature_0(f_winograd_4_0), + .o_feature_1(f_winograd_4_1), + .o_feature_2(f_winograd_4_2), + .o_feature_3(f_winograd_4_3), + .o_feature_4(f_winograd_4_4), + .o_feature_5(f_winograd_4_5), + .o_valid(winograd_valid_4) +); + +winograd_transform_5 winograd_transform_5_inst ( + .clk(clk), + .i_valid(valid_buff_0_0), + .i_result_0_0(f_buffer_pe_0_0), + .i_result_0_1(f_buffer_pe_0_1), + .i_result_0_2(f_buffer_pe_0_2), + .i_result_0_3(f_buffer_pe_0_3), + .i_result_0_4(f_buffer_pe_0_4), + .i_result_0_5(f_buffer_pe_0_5), + .i_result_0_6(f_buffer_pe_0_6), + .i_result_0_7(f_buffer_pe_0_7), + .i_result_1_0(f_buffer_pe_1_0), + .i_result_1_1(f_buffer_pe_1_1), + .i_result_1_2(f_buffer_pe_1_2), + .i_result_1_3(f_buffer_pe_1_3), + .i_result_1_4(f_buffer_pe_1_4), + .i_result_1_5(f_buffer_pe_1_5), + .i_result_1_6(f_buffer_pe_1_6), + .i_result_1_7(f_buffer_pe_1_7), + .i_result_2_0(f_buffer_pe_2_0), + .i_result_2_1(f_buffer_pe_2_1), + .i_result_2_2(f_buffer_pe_2_2), + .i_result_2_3(f_buffer_pe_2_3), + .i_result_2_4(f_buffer_pe_2_4), + .i_result_2_5(f_buffer_pe_2_5), + .i_result_2_6(f_buffer_pe_2_6), + .i_result_2_7(f_buffer_pe_2_7), + .i_result_3_0(f_buffer_pe_3_0), + .i_result_3_1(f_buffer_pe_3_1), + .i_result_3_2(f_buffer_pe_3_2), + .i_result_3_3(f_buffer_pe_3_3), + .i_result_3_4(f_buffer_pe_3_4), + .i_result_3_5(f_buffer_pe_3_5), + .i_result_3_6(f_buffer_pe_3_6), + .i_result_3_7(f_buffer_pe_3_7), + .i_result_4_0(f_buffer_pe_4_0), + .i_result_4_1(f_buffer_pe_4_1), + .i_result_4_2(f_buffer_pe_4_2), + .i_result_4_3(f_buffer_pe_4_3), + .i_result_4_4(f_buffer_pe_4_4), + .i_result_4_5(f_buffer_pe_4_5), + .i_result_4_6(f_buffer_pe_4_6), + .i_result_4_7(f_buffer_pe_4_7), + .i_result_5_0(f_buffer_pe_5_0), + .i_result_5_1(f_buffer_pe_5_1), + .i_result_5_2(f_buffer_pe_5_2), + .i_result_5_3(f_buffer_pe_5_3), + .i_result_5_4(f_buffer_pe_5_4), + .i_result_5_5(f_buffer_pe_5_5), + .i_result_5_6(f_buffer_pe_5_6), + .i_result_5_7(f_buffer_pe_5_7), + .o_feature_0(f_winograd_5_0), + .o_feature_1(f_winograd_5_1), + .o_feature_2(f_winograd_5_2), + .o_feature_3(f_winograd_5_3), + .o_feature_4(f_winograd_5_4), + .o_feature_5(f_winograd_5_5), + .o_valid(winograd_valid_5) +); + +winograd_transform_6 winograd_transform_6_inst ( + .clk(clk), + .i_valid(valid_buff_0_0), + .i_result_0_0(f_buffer_pe_0_0), + .i_result_0_1(f_buffer_pe_0_1), + .i_result_0_2(f_buffer_pe_0_2), + .i_result_0_3(f_buffer_pe_0_3), + .i_result_0_4(f_buffer_pe_0_4), + .i_result_0_5(f_buffer_pe_0_5), + .i_result_0_6(f_buffer_pe_0_6), + .i_result_0_7(f_buffer_pe_0_7), + .i_result_1_0(f_buffer_pe_1_0), + .i_result_1_1(f_buffer_pe_1_1), + .i_result_1_2(f_buffer_pe_1_2), + .i_result_1_3(f_buffer_pe_1_3), + .i_result_1_4(f_buffer_pe_1_4), + .i_result_1_5(f_buffer_pe_1_5), + .i_result_1_6(f_buffer_pe_1_6), + .i_result_1_7(f_buffer_pe_1_7), + .i_result_2_0(f_buffer_pe_2_0), + .i_result_2_1(f_buffer_pe_2_1), + .i_result_2_2(f_buffer_pe_2_2), + .i_result_2_3(f_buffer_pe_2_3), + .i_result_2_4(f_buffer_pe_2_4), + .i_result_2_5(f_buffer_pe_2_5), + .i_result_2_6(f_buffer_pe_2_6), + .i_result_2_7(f_buffer_pe_2_7), + .i_result_3_0(f_buffer_pe_3_0), + .i_result_3_1(f_buffer_pe_3_1), + .i_result_3_2(f_buffer_pe_3_2), + .i_result_3_3(f_buffer_pe_3_3), + .i_result_3_4(f_buffer_pe_3_4), + .i_result_3_5(f_buffer_pe_3_5), + .i_result_3_6(f_buffer_pe_3_6), + .i_result_3_7(f_buffer_pe_3_7), + .i_result_4_0(f_buffer_pe_4_0), + .i_result_4_1(f_buffer_pe_4_1), + .i_result_4_2(f_buffer_pe_4_2), + .i_result_4_3(f_buffer_pe_4_3), + .i_result_4_4(f_buffer_pe_4_4), + .i_result_4_5(f_buffer_pe_4_5), + .i_result_4_6(f_buffer_pe_4_6), + .i_result_4_7(f_buffer_pe_4_7), + .i_result_5_0(f_buffer_pe_5_0), + .i_result_5_1(f_buffer_pe_5_1), + .i_result_5_2(f_buffer_pe_5_2), + .i_result_5_3(f_buffer_pe_5_3), + .i_result_5_4(f_buffer_pe_5_4), + .i_result_5_5(f_buffer_pe_5_5), + .i_result_5_6(f_buffer_pe_5_6), + .i_result_5_7(f_buffer_pe_5_7), + .o_feature_0(f_winograd_6_0), + .o_feature_1(f_winograd_6_1), + .o_feature_2(f_winograd_6_2), + .o_feature_3(f_winograd_6_3), + .o_feature_4(f_winograd_6_4), + .o_feature_5(f_winograd_6_5), + .o_valid(winograd_valid_6) +); + +winograd_transform_7 winograd_transform_7_inst ( + .clk(clk), + .i_valid(valid_buff_0_0), + .i_result_0_0(f_buffer_pe_0_0), + .i_result_0_1(f_buffer_pe_0_1), + .i_result_0_2(f_buffer_pe_0_2), + .i_result_0_3(f_buffer_pe_0_3), + .i_result_0_4(f_buffer_pe_0_4), + .i_result_0_5(f_buffer_pe_0_5), + .i_result_0_6(f_buffer_pe_0_6), + .i_result_0_7(f_buffer_pe_0_7), + .i_result_1_0(f_buffer_pe_1_0), + .i_result_1_1(f_buffer_pe_1_1), + .i_result_1_2(f_buffer_pe_1_2), + .i_result_1_3(f_buffer_pe_1_3), + .i_result_1_4(f_buffer_pe_1_4), + .i_result_1_5(f_buffer_pe_1_5), + .i_result_1_6(f_buffer_pe_1_6), + .i_result_1_7(f_buffer_pe_1_7), + .i_result_2_0(f_buffer_pe_2_0), + .i_result_2_1(f_buffer_pe_2_1), + .i_result_2_2(f_buffer_pe_2_2), + .i_result_2_3(f_buffer_pe_2_3), + .i_result_2_4(f_buffer_pe_2_4), + .i_result_2_5(f_buffer_pe_2_5), + .i_result_2_6(f_buffer_pe_2_6), + .i_result_2_7(f_buffer_pe_2_7), + .i_result_3_0(f_buffer_pe_3_0), + .i_result_3_1(f_buffer_pe_3_1), + .i_result_3_2(f_buffer_pe_3_2), + .i_result_3_3(f_buffer_pe_3_3), + .i_result_3_4(f_buffer_pe_3_4), + .i_result_3_5(f_buffer_pe_3_5), + .i_result_3_6(f_buffer_pe_3_6), + .i_result_3_7(f_buffer_pe_3_7), + .i_result_4_0(f_buffer_pe_4_0), + .i_result_4_1(f_buffer_pe_4_1), + .i_result_4_2(f_buffer_pe_4_2), + .i_result_4_3(f_buffer_pe_4_3), + .i_result_4_4(f_buffer_pe_4_4), + .i_result_4_5(f_buffer_pe_4_5), + .i_result_4_6(f_buffer_pe_4_6), + .i_result_4_7(f_buffer_pe_4_7), + .i_result_5_0(f_buffer_pe_5_0), + .i_result_5_1(f_buffer_pe_5_1), + .i_result_5_2(f_buffer_pe_5_2), + .i_result_5_3(f_buffer_pe_5_3), + .i_result_5_4(f_buffer_pe_5_4), + .i_result_5_5(f_buffer_pe_5_5), + .i_result_5_6(f_buffer_pe_5_6), + .i_result_5_7(f_buffer_pe_5_7), + .o_feature_0(f_winograd_7_0), + .o_feature_1(f_winograd_7_1), + .o_feature_2(f_winograd_7_2), + .o_feature_3(f_winograd_7_3), + .o_feature_4(f_winograd_7_4), + .o_feature_5(f_winograd_7_5), + .o_valid(winograd_valid_7) +); + +processing_element processing_element_inst_0 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(winograd_valid_0), + .i_features_0_0(f_winograd_0_0), + .o_features_0_0(daisy_chain_0_0_0), + .i_features_0_1(f_winograd_0_1), + .o_features_0_1(daisy_chain_0_0_1), + .i_features_0_2(f_winograd_0_2), + .o_features_0_2(daisy_chain_0_0_2), + .i_features_0_3(f_winograd_0_3), + .o_features_0_3(daisy_chain_0_0_3), + .i_features_0_4(f_winograd_0_4), + .o_features_0_4(daisy_chain_0_0_4), + .i_features_0_5(f_winograd_0_5), + .o_features_0_5(daisy_chain_0_0_5), + .i_features_1_0(f_winograd_1_0), + .o_features_1_0(daisy_chain_0_1_0), + .i_features_1_1(f_winograd_1_1), + .o_features_1_1(daisy_chain_0_1_1), + .i_features_1_2(f_winograd_1_2), + .o_features_1_2(daisy_chain_0_1_2), + .i_features_1_3(f_winograd_1_3), + .o_features_1_3(daisy_chain_0_1_3), + .i_features_1_4(f_winograd_1_4), + .o_features_1_4(daisy_chain_0_1_4), + .i_features_1_5(f_winograd_1_5), + .o_features_1_5(daisy_chain_0_1_5), + .i_features_2_0(f_winograd_2_0), + .o_features_2_0(daisy_chain_0_2_0), + .i_features_2_1(f_winograd_2_1), + .o_features_2_1(daisy_chain_0_2_1), + .i_features_2_2(f_winograd_2_2), + .o_features_2_2(daisy_chain_0_2_2), + .i_features_2_3(f_winograd_2_3), + .o_features_2_3(daisy_chain_0_2_3), + .i_features_2_4(f_winograd_2_4), + .o_features_2_4(daisy_chain_0_2_4), + .i_features_2_5(f_winograd_2_5), + .o_features_2_5(daisy_chain_0_2_5), + .i_features_3_0(f_winograd_3_0), + .o_features_3_0(daisy_chain_0_3_0), + .i_features_3_1(f_winograd_3_1), + .o_features_3_1(daisy_chain_0_3_1), + .i_features_3_2(f_winograd_3_2), + .o_features_3_2(daisy_chain_0_3_2), + .i_features_3_3(f_winograd_3_3), + .o_features_3_3(daisy_chain_0_3_3), + .i_features_3_4(f_winograd_3_4), + .o_features_3_4(daisy_chain_0_3_4), + .i_features_3_5(f_winograd_3_5), + .o_features_3_5(daisy_chain_0_3_5), + .i_features_4_0(f_winograd_4_0), + .o_features_4_0(daisy_chain_0_4_0), + .i_features_4_1(f_winograd_4_1), + .o_features_4_1(daisy_chain_0_4_1), + .i_features_4_2(f_winograd_4_2), + .o_features_4_2(daisy_chain_0_4_2), + .i_features_4_3(f_winograd_4_3), + .o_features_4_3(daisy_chain_0_4_3), + .i_features_4_4(f_winograd_4_4), + .o_features_4_4(daisy_chain_0_4_4), + .i_features_4_5(f_winograd_4_5), + .o_features_4_5(daisy_chain_0_4_5), + .i_features_5_0(f_winograd_5_0), + .o_features_5_0(daisy_chain_0_5_0), + .i_features_5_1(f_winograd_5_1), + .o_features_5_1(daisy_chain_0_5_1), + .i_features_5_2(f_winograd_5_2), + .o_features_5_2(daisy_chain_0_5_2), + .i_features_5_3(f_winograd_5_3), + .o_features_5_3(daisy_chain_0_5_3), + .i_features_5_4(f_winograd_5_4), + .o_features_5_4(daisy_chain_0_5_4), + .i_features_5_5(f_winograd_5_5), + .o_features_5_5(daisy_chain_0_5_5), + .i_features_6_0(f_winograd_6_0), + .o_features_6_0(daisy_chain_0_6_0), + .i_features_6_1(f_winograd_6_1), + .o_features_6_1(daisy_chain_0_6_1), + .i_features_6_2(f_winograd_6_2), + .o_features_6_2(daisy_chain_0_6_2), + .i_features_6_3(f_winograd_6_3), + .o_features_6_3(daisy_chain_0_6_3), + .i_features_6_4(f_winograd_6_4), + .o_features_6_4(daisy_chain_0_6_4), + .i_features_6_5(f_winograd_6_5), + .o_features_6_5(daisy_chain_0_6_5), + .i_features_7_0(f_winograd_7_0), + .o_features_7_0(daisy_chain_0_7_0), + .i_features_7_1(f_winograd_7_1), + .o_features_7_1(daisy_chain_0_7_1), + .i_features_7_2(f_winograd_7_2), + .o_features_7_2(daisy_chain_0_7_2), + .i_features_7_3(f_winograd_7_3), + .o_features_7_3(daisy_chain_0_7_3), + .i_features_7_4(f_winograd_7_4), + .o_features_7_4(daisy_chain_0_7_4), + .i_features_7_5(f_winograd_7_5), + .o_features_7_5(daisy_chain_0_7_5), + .o_result_0(PE_output_0_0), + .o_result_1(PE_output_0_1), + .o_result_2(PE_output_0_2), + .o_result_3(PE_output_0_3), + .o_result_4(PE_output_0_4), + .o_result_5(PE_output_0_5), + .o_valid(PE_valid_0), + .o_next_reset(PE_next_reset_0), + .o_next_valid(PE_next_valid_0) +); + +processing_element processing_element_inst_1 ( + .clk(clk), + .i_reset(PE_next_reset_0), + .i_valid(PE_next_valid_0), + .i_features_0_0(daisy_chain_0_0_0), + .o_features_0_0(daisy_chain_1_0_0), + .i_features_0_1(daisy_chain_0_0_1), + .o_features_0_1(daisy_chain_1_0_1), + .i_features_0_2(daisy_chain_0_0_2), + .o_features_0_2(daisy_chain_1_0_2), + .i_features_0_3(daisy_chain_0_0_3), + .o_features_0_3(daisy_chain_1_0_3), + .i_features_0_4(daisy_chain_0_0_4), + .o_features_0_4(daisy_chain_1_0_4), + .i_features_0_5(daisy_chain_0_0_5), + .o_features_0_5(daisy_chain_1_0_5), + .i_features_1_0(daisy_chain_0_1_0), + .o_features_1_0(daisy_chain_1_1_0), + .i_features_1_1(daisy_chain_0_1_1), + .o_features_1_1(daisy_chain_1_1_1), + .i_features_1_2(daisy_chain_0_1_2), + .o_features_1_2(daisy_chain_1_1_2), + .i_features_1_3(daisy_chain_0_1_3), + .o_features_1_3(daisy_chain_1_1_3), + .i_features_1_4(daisy_chain_0_1_4), + .o_features_1_4(daisy_chain_1_1_4), + .i_features_1_5(daisy_chain_0_1_5), + .o_features_1_5(daisy_chain_1_1_5), + .i_features_2_0(daisy_chain_0_2_0), + .o_features_2_0(daisy_chain_1_2_0), + .i_features_2_1(daisy_chain_0_2_1), + .o_features_2_1(daisy_chain_1_2_1), + .i_features_2_2(daisy_chain_0_2_2), + .o_features_2_2(daisy_chain_1_2_2), + .i_features_2_3(daisy_chain_0_2_3), + .o_features_2_3(daisy_chain_1_2_3), + .i_features_2_4(daisy_chain_0_2_4), + .o_features_2_4(daisy_chain_1_2_4), + .i_features_2_5(daisy_chain_0_2_5), + .o_features_2_5(daisy_chain_1_2_5), + .i_features_3_0(daisy_chain_0_3_0), + .o_features_3_0(daisy_chain_1_3_0), + .i_features_3_1(daisy_chain_0_3_1), + .o_features_3_1(daisy_chain_1_3_1), + .i_features_3_2(daisy_chain_0_3_2), + .o_features_3_2(daisy_chain_1_3_2), + .i_features_3_3(daisy_chain_0_3_3), + .o_features_3_3(daisy_chain_1_3_3), + .i_features_3_4(daisy_chain_0_3_4), + .o_features_3_4(daisy_chain_1_3_4), + .i_features_3_5(daisy_chain_0_3_5), + .o_features_3_5(daisy_chain_1_3_5), + .i_features_4_0(daisy_chain_0_4_0), + .o_features_4_0(daisy_chain_1_4_0), + .i_features_4_1(daisy_chain_0_4_1), + .o_features_4_1(daisy_chain_1_4_1), + .i_features_4_2(daisy_chain_0_4_2), + .o_features_4_2(daisy_chain_1_4_2), + .i_features_4_3(daisy_chain_0_4_3), + .o_features_4_3(daisy_chain_1_4_3), + .i_features_4_4(daisy_chain_0_4_4), + .o_features_4_4(daisy_chain_1_4_4), + .i_features_4_5(daisy_chain_0_4_5), + .o_features_4_5(daisy_chain_1_4_5), + .i_features_5_0(daisy_chain_0_5_0), + .o_features_5_0(daisy_chain_1_5_0), + .i_features_5_1(daisy_chain_0_5_1), + .o_features_5_1(daisy_chain_1_5_1), + .i_features_5_2(daisy_chain_0_5_2), + .o_features_5_2(daisy_chain_1_5_2), + .i_features_5_3(daisy_chain_0_5_3), + .o_features_5_3(daisy_chain_1_5_3), + .i_features_5_4(daisy_chain_0_5_4), + .o_features_5_4(daisy_chain_1_5_4), + .i_features_5_5(daisy_chain_0_5_5), + .o_features_5_5(daisy_chain_1_5_5), + .i_features_6_0(daisy_chain_0_6_0), + .o_features_6_0(daisy_chain_1_6_0), + .i_features_6_1(daisy_chain_0_6_1), + .o_features_6_1(daisy_chain_1_6_1), + .i_features_6_2(daisy_chain_0_6_2), + .o_features_6_2(daisy_chain_1_6_2), + .i_features_6_3(daisy_chain_0_6_3), + .o_features_6_3(daisy_chain_1_6_3), + .i_features_6_4(daisy_chain_0_6_4), + .o_features_6_4(daisy_chain_1_6_4), + .i_features_6_5(daisy_chain_0_6_5), + .o_features_6_5(daisy_chain_1_6_5), + .i_features_7_0(daisy_chain_0_7_0), + .o_features_7_0(daisy_chain_1_7_0), + .i_features_7_1(daisy_chain_0_7_1), + .o_features_7_1(daisy_chain_1_7_1), + .i_features_7_2(daisy_chain_0_7_2), + .o_features_7_2(daisy_chain_1_7_2), + .i_features_7_3(daisy_chain_0_7_3), + .o_features_7_3(daisy_chain_1_7_3), + .i_features_7_4(daisy_chain_0_7_4), + .o_features_7_4(daisy_chain_1_7_4), + .i_features_7_5(daisy_chain_0_7_5), + .o_features_7_5(daisy_chain_1_7_5), + .o_result_0(PE_output_1_0), + .o_result_1(PE_output_1_1), + .o_result_2(PE_output_1_2), + .o_result_3(PE_output_1_3), + .o_result_4(PE_output_1_4), + .o_result_5(PE_output_1_5), + .o_valid(PE_valid_1), + .o_next_reset(PE_next_reset_1), + .o_next_valid(PE_next_valid_1) +); + +processing_element processing_element_inst_2 ( + .clk(clk), + .i_reset(PE_next_reset_1), + .i_valid(PE_next_valid_1), + .i_features_0_0(daisy_chain_1_0_0), + .o_features_0_0(daisy_chain_2_0_0), + .i_features_0_1(daisy_chain_1_0_1), + .o_features_0_1(daisy_chain_2_0_1), + .i_features_0_2(daisy_chain_1_0_2), + .o_features_0_2(daisy_chain_2_0_2), + .i_features_0_3(daisy_chain_1_0_3), + .o_features_0_3(daisy_chain_2_0_3), + .i_features_0_4(daisy_chain_1_0_4), + .o_features_0_4(daisy_chain_2_0_4), + .i_features_0_5(daisy_chain_1_0_5), + .o_features_0_5(daisy_chain_2_0_5), + .i_features_1_0(daisy_chain_1_1_0), + .o_features_1_0(daisy_chain_2_1_0), + .i_features_1_1(daisy_chain_1_1_1), + .o_features_1_1(daisy_chain_2_1_1), + .i_features_1_2(daisy_chain_1_1_2), + .o_features_1_2(daisy_chain_2_1_2), + .i_features_1_3(daisy_chain_1_1_3), + .o_features_1_3(daisy_chain_2_1_3), + .i_features_1_4(daisy_chain_1_1_4), + .o_features_1_4(daisy_chain_2_1_4), + .i_features_1_5(daisy_chain_1_1_5), + .o_features_1_5(daisy_chain_2_1_5), + .i_features_2_0(daisy_chain_1_2_0), + .o_features_2_0(daisy_chain_2_2_0), + .i_features_2_1(daisy_chain_1_2_1), + .o_features_2_1(daisy_chain_2_2_1), + .i_features_2_2(daisy_chain_1_2_2), + .o_features_2_2(daisy_chain_2_2_2), + .i_features_2_3(daisy_chain_1_2_3), + .o_features_2_3(daisy_chain_2_2_3), + .i_features_2_4(daisy_chain_1_2_4), + .o_features_2_4(daisy_chain_2_2_4), + .i_features_2_5(daisy_chain_1_2_5), + .o_features_2_5(daisy_chain_2_2_5), + .i_features_3_0(daisy_chain_1_3_0), + .o_features_3_0(daisy_chain_2_3_0), + .i_features_3_1(daisy_chain_1_3_1), + .o_features_3_1(daisy_chain_2_3_1), + .i_features_3_2(daisy_chain_1_3_2), + .o_features_3_2(daisy_chain_2_3_2), + .i_features_3_3(daisy_chain_1_3_3), + .o_features_3_3(daisy_chain_2_3_3), + .i_features_3_4(daisy_chain_1_3_4), + .o_features_3_4(daisy_chain_2_3_4), + .i_features_3_5(daisy_chain_1_3_5), + .o_features_3_5(daisy_chain_2_3_5), + .i_features_4_0(daisy_chain_1_4_0), + .o_features_4_0(daisy_chain_2_4_0), + .i_features_4_1(daisy_chain_1_4_1), + .o_features_4_1(daisy_chain_2_4_1), + .i_features_4_2(daisy_chain_1_4_2), + .o_features_4_2(daisy_chain_2_4_2), + .i_features_4_3(daisy_chain_1_4_3), + .o_features_4_3(daisy_chain_2_4_3), + .i_features_4_4(daisy_chain_1_4_4), + .o_features_4_4(daisy_chain_2_4_4), + .i_features_4_5(daisy_chain_1_4_5), + .o_features_4_5(daisy_chain_2_4_5), + .i_features_5_0(daisy_chain_1_5_0), + .o_features_5_0(daisy_chain_2_5_0), + .i_features_5_1(daisy_chain_1_5_1), + .o_features_5_1(daisy_chain_2_5_1), + .i_features_5_2(daisy_chain_1_5_2), + .o_features_5_2(daisy_chain_2_5_2), + .i_features_5_3(daisy_chain_1_5_3), + .o_features_5_3(daisy_chain_2_5_3), + .i_features_5_4(daisy_chain_1_5_4), + .o_features_5_4(daisy_chain_2_5_4), + .i_features_5_5(daisy_chain_1_5_5), + .o_features_5_5(daisy_chain_2_5_5), + .i_features_6_0(daisy_chain_1_6_0), + .o_features_6_0(daisy_chain_2_6_0), + .i_features_6_1(daisy_chain_1_6_1), + .o_features_6_1(daisy_chain_2_6_1), + .i_features_6_2(daisy_chain_1_6_2), + .o_features_6_2(daisy_chain_2_6_2), + .i_features_6_3(daisy_chain_1_6_3), + .o_features_6_3(daisy_chain_2_6_3), + .i_features_6_4(daisy_chain_1_6_4), + .o_features_6_4(daisy_chain_2_6_4), + .i_features_6_5(daisy_chain_1_6_5), + .o_features_6_5(daisy_chain_2_6_5), + .i_features_7_0(daisy_chain_1_7_0), + .o_features_7_0(daisy_chain_2_7_0), + .i_features_7_1(daisy_chain_1_7_1), + .o_features_7_1(daisy_chain_2_7_1), + .i_features_7_2(daisy_chain_1_7_2), + .o_features_7_2(daisy_chain_2_7_2), + .i_features_7_3(daisy_chain_1_7_3), + .o_features_7_3(daisy_chain_2_7_3), + .i_features_7_4(daisy_chain_1_7_4), + .o_features_7_4(daisy_chain_2_7_4), + .i_features_7_5(daisy_chain_1_7_5), + .o_features_7_5(daisy_chain_2_7_5), + .o_result_0(PE_output_2_0), + .o_result_1(PE_output_2_1), + .o_result_2(PE_output_2_2), + .o_result_3(PE_output_2_3), + .o_result_4(PE_output_2_4), + .o_result_5(PE_output_2_5), + .o_valid(PE_valid_2), + .o_next_reset(PE_next_reset_2), + .o_next_valid(PE_next_valid_2) +); + +processing_element processing_element_inst_3 ( + .clk(clk), + .i_reset(PE_next_reset_2), + .i_valid(PE_next_valid_2), + .i_features_0_0(daisy_chain_2_0_0), + .o_features_0_0(daisy_chain_3_0_0), + .i_features_0_1(daisy_chain_2_0_1), + .o_features_0_1(daisy_chain_3_0_1), + .i_features_0_2(daisy_chain_2_0_2), + .o_features_0_2(daisy_chain_3_0_2), + .i_features_0_3(daisy_chain_2_0_3), + .o_features_0_3(daisy_chain_3_0_3), + .i_features_0_4(daisy_chain_2_0_4), + .o_features_0_4(daisy_chain_3_0_4), + .i_features_0_5(daisy_chain_2_0_5), + .o_features_0_5(daisy_chain_3_0_5), + .i_features_1_0(daisy_chain_2_1_0), + .o_features_1_0(daisy_chain_3_1_0), + .i_features_1_1(daisy_chain_2_1_1), + .o_features_1_1(daisy_chain_3_1_1), + .i_features_1_2(daisy_chain_2_1_2), + .o_features_1_2(daisy_chain_3_1_2), + .i_features_1_3(daisy_chain_2_1_3), + .o_features_1_3(daisy_chain_3_1_3), + .i_features_1_4(daisy_chain_2_1_4), + .o_features_1_4(daisy_chain_3_1_4), + .i_features_1_5(daisy_chain_2_1_5), + .o_features_1_5(daisy_chain_3_1_5), + .i_features_2_0(daisy_chain_2_2_0), + .o_features_2_0(daisy_chain_3_2_0), + .i_features_2_1(daisy_chain_2_2_1), + .o_features_2_1(daisy_chain_3_2_1), + .i_features_2_2(daisy_chain_2_2_2), + .o_features_2_2(daisy_chain_3_2_2), + .i_features_2_3(daisy_chain_2_2_3), + .o_features_2_3(daisy_chain_3_2_3), + .i_features_2_4(daisy_chain_2_2_4), + .o_features_2_4(daisy_chain_3_2_4), + .i_features_2_5(daisy_chain_2_2_5), + .o_features_2_5(daisy_chain_3_2_5), + .i_features_3_0(daisy_chain_2_3_0), + .o_features_3_0(daisy_chain_3_3_0), + .i_features_3_1(daisy_chain_2_3_1), + .o_features_3_1(daisy_chain_3_3_1), + .i_features_3_2(daisy_chain_2_3_2), + .o_features_3_2(daisy_chain_3_3_2), + .i_features_3_3(daisy_chain_2_3_3), + .o_features_3_3(daisy_chain_3_3_3), + .i_features_3_4(daisy_chain_2_3_4), + .o_features_3_4(daisy_chain_3_3_4), + .i_features_3_5(daisy_chain_2_3_5), + .o_features_3_5(daisy_chain_3_3_5), + .i_features_4_0(daisy_chain_2_4_0), + .o_features_4_0(daisy_chain_3_4_0), + .i_features_4_1(daisy_chain_2_4_1), + .o_features_4_1(daisy_chain_3_4_1), + .i_features_4_2(daisy_chain_2_4_2), + .o_features_4_2(daisy_chain_3_4_2), + .i_features_4_3(daisy_chain_2_4_3), + .o_features_4_3(daisy_chain_3_4_3), + .i_features_4_4(daisy_chain_2_4_4), + .o_features_4_4(daisy_chain_3_4_4), + .i_features_4_5(daisy_chain_2_4_5), + .o_features_4_5(daisy_chain_3_4_5), + .i_features_5_0(daisy_chain_2_5_0), + .o_features_5_0(daisy_chain_3_5_0), + .i_features_5_1(daisy_chain_2_5_1), + .o_features_5_1(daisy_chain_3_5_1), + .i_features_5_2(daisy_chain_2_5_2), + .o_features_5_2(daisy_chain_3_5_2), + .i_features_5_3(daisy_chain_2_5_3), + .o_features_5_3(daisy_chain_3_5_3), + .i_features_5_4(daisy_chain_2_5_4), + .o_features_5_4(daisy_chain_3_5_4), + .i_features_5_5(daisy_chain_2_5_5), + .o_features_5_5(daisy_chain_3_5_5), + .i_features_6_0(daisy_chain_2_6_0), + .o_features_6_0(daisy_chain_3_6_0), + .i_features_6_1(daisy_chain_2_6_1), + .o_features_6_1(daisy_chain_3_6_1), + .i_features_6_2(daisy_chain_2_6_2), + .o_features_6_2(daisy_chain_3_6_2), + .i_features_6_3(daisy_chain_2_6_3), + .o_features_6_3(daisy_chain_3_6_3), + .i_features_6_4(daisy_chain_2_6_4), + .o_features_6_4(daisy_chain_3_6_4), + .i_features_6_5(daisy_chain_2_6_5), + .o_features_6_5(daisy_chain_3_6_5), + .i_features_7_0(daisy_chain_2_7_0), + .o_features_7_0(daisy_chain_3_7_0), + .i_features_7_1(daisy_chain_2_7_1), + .o_features_7_1(daisy_chain_3_7_1), + .i_features_7_2(daisy_chain_2_7_2), + .o_features_7_2(daisy_chain_3_7_2), + .i_features_7_3(daisy_chain_2_7_3), + .o_features_7_3(daisy_chain_3_7_3), + .i_features_7_4(daisy_chain_2_7_4), + .o_features_7_4(daisy_chain_3_7_4), + .i_features_7_5(daisy_chain_2_7_5), + .o_features_7_5(daisy_chain_3_7_5), + .o_result_0(PE_output_3_0), + .o_result_1(PE_output_3_1), + .o_result_2(PE_output_3_2), + .o_result_3(PE_output_3_3), + .o_result_4(PE_output_3_4), + .o_result_5(PE_output_3_5), + .o_valid(PE_valid_3), + .o_next_reset(PE_next_reset_3), + .o_next_valid(PE_next_valid_3) +); + +processing_element processing_element_inst_4 ( + .clk(clk), + .i_reset(PE_next_reset_3), + .i_valid(PE_next_valid_3), + .i_features_0_0(daisy_chain_3_0_0), + .o_features_0_0(daisy_chain_4_0_0), + .i_features_0_1(daisy_chain_3_0_1), + .o_features_0_1(daisy_chain_4_0_1), + .i_features_0_2(daisy_chain_3_0_2), + .o_features_0_2(daisy_chain_4_0_2), + .i_features_0_3(daisy_chain_3_0_3), + .o_features_0_3(daisy_chain_4_0_3), + .i_features_0_4(daisy_chain_3_0_4), + .o_features_0_4(daisy_chain_4_0_4), + .i_features_0_5(daisy_chain_3_0_5), + .o_features_0_5(daisy_chain_4_0_5), + .i_features_1_0(daisy_chain_3_1_0), + .o_features_1_0(daisy_chain_4_1_0), + .i_features_1_1(daisy_chain_3_1_1), + .o_features_1_1(daisy_chain_4_1_1), + .i_features_1_2(daisy_chain_3_1_2), + .o_features_1_2(daisy_chain_4_1_2), + .i_features_1_3(daisy_chain_3_1_3), + .o_features_1_3(daisy_chain_4_1_3), + .i_features_1_4(daisy_chain_3_1_4), + .o_features_1_4(daisy_chain_4_1_4), + .i_features_1_5(daisy_chain_3_1_5), + .o_features_1_5(daisy_chain_4_1_5), + .i_features_2_0(daisy_chain_3_2_0), + .o_features_2_0(daisy_chain_4_2_0), + .i_features_2_1(daisy_chain_3_2_1), + .o_features_2_1(daisy_chain_4_2_1), + .i_features_2_2(daisy_chain_3_2_2), + .o_features_2_2(daisy_chain_4_2_2), + .i_features_2_3(daisy_chain_3_2_3), + .o_features_2_3(daisy_chain_4_2_3), + .i_features_2_4(daisy_chain_3_2_4), + .o_features_2_4(daisy_chain_4_2_4), + .i_features_2_5(daisy_chain_3_2_5), + .o_features_2_5(daisy_chain_4_2_5), + .i_features_3_0(daisy_chain_3_3_0), + .o_features_3_0(daisy_chain_4_3_0), + .i_features_3_1(daisy_chain_3_3_1), + .o_features_3_1(daisy_chain_4_3_1), + .i_features_3_2(daisy_chain_3_3_2), + .o_features_3_2(daisy_chain_4_3_2), + .i_features_3_3(daisy_chain_3_3_3), + .o_features_3_3(daisy_chain_4_3_3), + .i_features_3_4(daisy_chain_3_3_4), + .o_features_3_4(daisy_chain_4_3_4), + .i_features_3_5(daisy_chain_3_3_5), + .o_features_3_5(daisy_chain_4_3_5), + .i_features_4_0(daisy_chain_3_4_0), + .o_features_4_0(daisy_chain_4_4_0), + .i_features_4_1(daisy_chain_3_4_1), + .o_features_4_1(daisy_chain_4_4_1), + .i_features_4_2(daisy_chain_3_4_2), + .o_features_4_2(daisy_chain_4_4_2), + .i_features_4_3(daisy_chain_3_4_3), + .o_features_4_3(daisy_chain_4_4_3), + .i_features_4_4(daisy_chain_3_4_4), + .o_features_4_4(daisy_chain_4_4_4), + .i_features_4_5(daisy_chain_3_4_5), + .o_features_4_5(daisy_chain_4_4_5), + .i_features_5_0(daisy_chain_3_5_0), + .o_features_5_0(daisy_chain_4_5_0), + .i_features_5_1(daisy_chain_3_5_1), + .o_features_5_1(daisy_chain_4_5_1), + .i_features_5_2(daisy_chain_3_5_2), + .o_features_5_2(daisy_chain_4_5_2), + .i_features_5_3(daisy_chain_3_5_3), + .o_features_5_3(daisy_chain_4_5_3), + .i_features_5_4(daisy_chain_3_5_4), + .o_features_5_4(daisy_chain_4_5_4), + .i_features_5_5(daisy_chain_3_5_5), + .o_features_5_5(daisy_chain_4_5_5), + .i_features_6_0(daisy_chain_3_6_0), + .o_features_6_0(daisy_chain_4_6_0), + .i_features_6_1(daisy_chain_3_6_1), + .o_features_6_1(daisy_chain_4_6_1), + .i_features_6_2(daisy_chain_3_6_2), + .o_features_6_2(daisy_chain_4_6_2), + .i_features_6_3(daisy_chain_3_6_3), + .o_features_6_3(daisy_chain_4_6_3), + .i_features_6_4(daisy_chain_3_6_4), + .o_features_6_4(daisy_chain_4_6_4), + .i_features_6_5(daisy_chain_3_6_5), + .o_features_6_5(daisy_chain_4_6_5), + .i_features_7_0(daisy_chain_3_7_0), + .o_features_7_0(daisy_chain_4_7_0), + .i_features_7_1(daisy_chain_3_7_1), + .o_features_7_1(daisy_chain_4_7_1), + .i_features_7_2(daisy_chain_3_7_2), + .o_features_7_2(daisy_chain_4_7_2), + .i_features_7_3(daisy_chain_3_7_3), + .o_features_7_3(daisy_chain_4_7_3), + .i_features_7_4(daisy_chain_3_7_4), + .o_features_7_4(daisy_chain_4_7_4), + .i_features_7_5(daisy_chain_3_7_5), + .o_features_7_5(daisy_chain_4_7_5), + .o_result_0(PE_output_4_0), + .o_result_1(PE_output_4_1), + .o_result_2(PE_output_4_2), + .o_result_3(PE_output_4_3), + .o_result_4(PE_output_4_4), + .o_result_5(PE_output_4_5), + .o_valid(PE_valid_4), + .o_next_reset(PE_next_reset_4), + .o_next_valid(PE_next_valid_4) +); + +processing_element processing_element_inst_5 ( + .clk(clk), + .i_reset(PE_next_reset_4), + .i_valid(PE_next_valid_4), + .i_features_0_0(daisy_chain_4_0_0), + .o_features_0_0(daisy_chain_5_0_0), + .i_features_0_1(daisy_chain_4_0_1), + .o_features_0_1(daisy_chain_5_0_1), + .i_features_0_2(daisy_chain_4_0_2), + .o_features_0_2(daisy_chain_5_0_2), + .i_features_0_3(daisy_chain_4_0_3), + .o_features_0_3(daisy_chain_5_0_3), + .i_features_0_4(daisy_chain_4_0_4), + .o_features_0_4(daisy_chain_5_0_4), + .i_features_0_5(daisy_chain_4_0_5), + .o_features_0_5(daisy_chain_5_0_5), + .i_features_1_0(daisy_chain_4_1_0), + .o_features_1_0(daisy_chain_5_1_0), + .i_features_1_1(daisy_chain_4_1_1), + .o_features_1_1(daisy_chain_5_1_1), + .i_features_1_2(daisy_chain_4_1_2), + .o_features_1_2(daisy_chain_5_1_2), + .i_features_1_3(daisy_chain_4_1_3), + .o_features_1_3(daisy_chain_5_1_3), + .i_features_1_4(daisy_chain_4_1_4), + .o_features_1_4(daisy_chain_5_1_4), + .i_features_1_5(daisy_chain_4_1_5), + .o_features_1_5(daisy_chain_5_1_5), + .i_features_2_0(daisy_chain_4_2_0), + .o_features_2_0(daisy_chain_5_2_0), + .i_features_2_1(daisy_chain_4_2_1), + .o_features_2_1(daisy_chain_5_2_1), + .i_features_2_2(daisy_chain_4_2_2), + .o_features_2_2(daisy_chain_5_2_2), + .i_features_2_3(daisy_chain_4_2_3), + .o_features_2_3(daisy_chain_5_2_3), + .i_features_2_4(daisy_chain_4_2_4), + .o_features_2_4(daisy_chain_5_2_4), + .i_features_2_5(daisy_chain_4_2_5), + .o_features_2_5(daisy_chain_5_2_5), + .i_features_3_0(daisy_chain_4_3_0), + .o_features_3_0(daisy_chain_5_3_0), + .i_features_3_1(daisy_chain_4_3_1), + .o_features_3_1(daisy_chain_5_3_1), + .i_features_3_2(daisy_chain_4_3_2), + .o_features_3_2(daisy_chain_5_3_2), + .i_features_3_3(daisy_chain_4_3_3), + .o_features_3_3(daisy_chain_5_3_3), + .i_features_3_4(daisy_chain_4_3_4), + .o_features_3_4(daisy_chain_5_3_4), + .i_features_3_5(daisy_chain_4_3_5), + .o_features_3_5(daisy_chain_5_3_5), + .i_features_4_0(daisy_chain_4_4_0), + .o_features_4_0(daisy_chain_5_4_0), + .i_features_4_1(daisy_chain_4_4_1), + .o_features_4_1(daisy_chain_5_4_1), + .i_features_4_2(daisy_chain_4_4_2), + .o_features_4_2(daisy_chain_5_4_2), + .i_features_4_3(daisy_chain_4_4_3), + .o_features_4_3(daisy_chain_5_4_3), + .i_features_4_4(daisy_chain_4_4_4), + .o_features_4_4(daisy_chain_5_4_4), + .i_features_4_5(daisy_chain_4_4_5), + .o_features_4_5(daisy_chain_5_4_5), + .i_features_5_0(daisy_chain_4_5_0), + .o_features_5_0(daisy_chain_5_5_0), + .i_features_5_1(daisy_chain_4_5_1), + .o_features_5_1(daisy_chain_5_5_1), + .i_features_5_2(daisy_chain_4_5_2), + .o_features_5_2(daisy_chain_5_5_2), + .i_features_5_3(daisy_chain_4_5_3), + .o_features_5_3(daisy_chain_5_5_3), + .i_features_5_4(daisy_chain_4_5_4), + .o_features_5_4(daisy_chain_5_5_4), + .i_features_5_5(daisy_chain_4_5_5), + .o_features_5_5(daisy_chain_5_5_5), + .i_features_6_0(daisy_chain_4_6_0), + .o_features_6_0(daisy_chain_5_6_0), + .i_features_6_1(daisy_chain_4_6_1), + .o_features_6_1(daisy_chain_5_6_1), + .i_features_6_2(daisy_chain_4_6_2), + .o_features_6_2(daisy_chain_5_6_2), + .i_features_6_3(daisy_chain_4_6_3), + .o_features_6_3(daisy_chain_5_6_3), + .i_features_6_4(daisy_chain_4_6_4), + .o_features_6_4(daisy_chain_5_6_4), + .i_features_6_5(daisy_chain_4_6_5), + .o_features_6_5(daisy_chain_5_6_5), + .i_features_7_0(daisy_chain_4_7_0), + .o_features_7_0(daisy_chain_5_7_0), + .i_features_7_1(daisy_chain_4_7_1), + .o_features_7_1(daisy_chain_5_7_1), + .i_features_7_2(daisy_chain_4_7_2), + .o_features_7_2(daisy_chain_5_7_2), + .i_features_7_3(daisy_chain_4_7_3), + .o_features_7_3(daisy_chain_5_7_3), + .i_features_7_4(daisy_chain_4_7_4), + .o_features_7_4(daisy_chain_5_7_4), + .i_features_7_5(daisy_chain_4_7_5), + .o_features_7_5(daisy_chain_5_7_5), + .o_result_0(PE_output_5_0), + .o_result_1(PE_output_5_1), + .o_result_2(PE_output_5_2), + .o_result_3(PE_output_5_3), + .o_result_4(PE_output_5_4), + .o_result_5(PE_output_5_5), + .o_valid(PE_valid_5), + .o_next_reset(PE_next_reset_5), + .o_next_valid(PE_next_valid_5) +); + +processing_element processing_element_inst_6 ( + .clk(clk), + .i_reset(PE_next_reset_5), + .i_valid(PE_next_valid_5), + .i_features_0_0(daisy_chain_5_0_0), + .o_features_0_0(daisy_chain_6_0_0), + .i_features_0_1(daisy_chain_5_0_1), + .o_features_0_1(daisy_chain_6_0_1), + .i_features_0_2(daisy_chain_5_0_2), + .o_features_0_2(daisy_chain_6_0_2), + .i_features_0_3(daisy_chain_5_0_3), + .o_features_0_3(daisy_chain_6_0_3), + .i_features_0_4(daisy_chain_5_0_4), + .o_features_0_4(daisy_chain_6_0_4), + .i_features_0_5(daisy_chain_5_0_5), + .o_features_0_5(daisy_chain_6_0_5), + .i_features_1_0(daisy_chain_5_1_0), + .o_features_1_0(daisy_chain_6_1_0), + .i_features_1_1(daisy_chain_5_1_1), + .o_features_1_1(daisy_chain_6_1_1), + .i_features_1_2(daisy_chain_5_1_2), + .o_features_1_2(daisy_chain_6_1_2), + .i_features_1_3(daisy_chain_5_1_3), + .o_features_1_3(daisy_chain_6_1_3), + .i_features_1_4(daisy_chain_5_1_4), + .o_features_1_4(daisy_chain_6_1_4), + .i_features_1_5(daisy_chain_5_1_5), + .o_features_1_5(daisy_chain_6_1_5), + .i_features_2_0(daisy_chain_5_2_0), + .o_features_2_0(daisy_chain_6_2_0), + .i_features_2_1(daisy_chain_5_2_1), + .o_features_2_1(daisy_chain_6_2_1), + .i_features_2_2(daisy_chain_5_2_2), + .o_features_2_2(daisy_chain_6_2_2), + .i_features_2_3(daisy_chain_5_2_3), + .o_features_2_3(daisy_chain_6_2_3), + .i_features_2_4(daisy_chain_5_2_4), + .o_features_2_4(daisy_chain_6_2_4), + .i_features_2_5(daisy_chain_5_2_5), + .o_features_2_5(daisy_chain_6_2_5), + .i_features_3_0(daisy_chain_5_3_0), + .o_features_3_0(daisy_chain_6_3_0), + .i_features_3_1(daisy_chain_5_3_1), + .o_features_3_1(daisy_chain_6_3_1), + .i_features_3_2(daisy_chain_5_3_2), + .o_features_3_2(daisy_chain_6_3_2), + .i_features_3_3(daisy_chain_5_3_3), + .o_features_3_3(daisy_chain_6_3_3), + .i_features_3_4(daisy_chain_5_3_4), + .o_features_3_4(daisy_chain_6_3_4), + .i_features_3_5(daisy_chain_5_3_5), + .o_features_3_5(daisy_chain_6_3_5), + .i_features_4_0(daisy_chain_5_4_0), + .o_features_4_0(daisy_chain_6_4_0), + .i_features_4_1(daisy_chain_5_4_1), + .o_features_4_1(daisy_chain_6_4_1), + .i_features_4_2(daisy_chain_5_4_2), + .o_features_4_2(daisy_chain_6_4_2), + .i_features_4_3(daisy_chain_5_4_3), + .o_features_4_3(daisy_chain_6_4_3), + .i_features_4_4(daisy_chain_5_4_4), + .o_features_4_4(daisy_chain_6_4_4), + .i_features_4_5(daisy_chain_5_4_5), + .o_features_4_5(daisy_chain_6_4_5), + .i_features_5_0(daisy_chain_5_5_0), + .o_features_5_0(daisy_chain_6_5_0), + .i_features_5_1(daisy_chain_5_5_1), + .o_features_5_1(daisy_chain_6_5_1), + .i_features_5_2(daisy_chain_5_5_2), + .o_features_5_2(daisy_chain_6_5_2), + .i_features_5_3(daisy_chain_5_5_3), + .o_features_5_3(daisy_chain_6_5_3), + .i_features_5_4(daisy_chain_5_5_4), + .o_features_5_4(daisy_chain_6_5_4), + .i_features_5_5(daisy_chain_5_5_5), + .o_features_5_5(daisy_chain_6_5_5), + .i_features_6_0(daisy_chain_5_6_0), + .o_features_6_0(daisy_chain_6_6_0), + .i_features_6_1(daisy_chain_5_6_1), + .o_features_6_1(daisy_chain_6_6_1), + .i_features_6_2(daisy_chain_5_6_2), + .o_features_6_2(daisy_chain_6_6_2), + .i_features_6_3(daisy_chain_5_6_3), + .o_features_6_3(daisy_chain_6_6_3), + .i_features_6_4(daisy_chain_5_6_4), + .o_features_6_4(daisy_chain_6_6_4), + .i_features_6_5(daisy_chain_5_6_5), + .o_features_6_5(daisy_chain_6_6_5), + .i_features_7_0(daisy_chain_5_7_0), + .o_features_7_0(daisy_chain_6_7_0), + .i_features_7_1(daisy_chain_5_7_1), + .o_features_7_1(daisy_chain_6_7_1), + .i_features_7_2(daisy_chain_5_7_2), + .o_features_7_2(daisy_chain_6_7_2), + .i_features_7_3(daisy_chain_5_7_3), + .o_features_7_3(daisy_chain_6_7_3), + .i_features_7_4(daisy_chain_5_7_4), + .o_features_7_4(daisy_chain_6_7_4), + .i_features_7_5(daisy_chain_5_7_5), + .o_features_7_5(daisy_chain_6_7_5), + .o_result_0(PE_output_6_0), + .o_result_1(PE_output_6_1), + .o_result_2(PE_output_6_2), + .o_result_3(PE_output_6_3), + .o_result_4(PE_output_6_4), + .o_result_5(PE_output_6_5), + .o_valid(PE_valid_6), + .o_next_reset(PE_next_reset_6), + .o_next_valid(PE_next_valid_6) +); + +processing_element processing_element_inst_7 ( + .clk(clk), + .i_reset(PE_next_reset_6), + .i_valid(PE_next_valid_6), + .i_features_0_0(daisy_chain_6_0_0), + .o_features_0_0(daisy_chain_7_0_0), + .i_features_0_1(daisy_chain_6_0_1), + .o_features_0_1(daisy_chain_7_0_1), + .i_features_0_2(daisy_chain_6_0_2), + .o_features_0_2(daisy_chain_7_0_2), + .i_features_0_3(daisy_chain_6_0_3), + .o_features_0_3(daisy_chain_7_0_3), + .i_features_0_4(daisy_chain_6_0_4), + .o_features_0_4(daisy_chain_7_0_4), + .i_features_0_5(daisy_chain_6_0_5), + .o_features_0_5(daisy_chain_7_0_5), + .i_features_1_0(daisy_chain_6_1_0), + .o_features_1_0(daisy_chain_7_1_0), + .i_features_1_1(daisy_chain_6_1_1), + .o_features_1_1(daisy_chain_7_1_1), + .i_features_1_2(daisy_chain_6_1_2), + .o_features_1_2(daisy_chain_7_1_2), + .i_features_1_3(daisy_chain_6_1_3), + .o_features_1_3(daisy_chain_7_1_3), + .i_features_1_4(daisy_chain_6_1_4), + .o_features_1_4(daisy_chain_7_1_4), + .i_features_1_5(daisy_chain_6_1_5), + .o_features_1_5(daisy_chain_7_1_5), + .i_features_2_0(daisy_chain_6_2_0), + .o_features_2_0(daisy_chain_7_2_0), + .i_features_2_1(daisy_chain_6_2_1), + .o_features_2_1(daisy_chain_7_2_1), + .i_features_2_2(daisy_chain_6_2_2), + .o_features_2_2(daisy_chain_7_2_2), + .i_features_2_3(daisy_chain_6_2_3), + .o_features_2_3(daisy_chain_7_2_3), + .i_features_2_4(daisy_chain_6_2_4), + .o_features_2_4(daisy_chain_7_2_4), + .i_features_2_5(daisy_chain_6_2_5), + .o_features_2_5(daisy_chain_7_2_5), + .i_features_3_0(daisy_chain_6_3_0), + .o_features_3_0(daisy_chain_7_3_0), + .i_features_3_1(daisy_chain_6_3_1), + .o_features_3_1(daisy_chain_7_3_1), + .i_features_3_2(daisy_chain_6_3_2), + .o_features_3_2(daisy_chain_7_3_2), + .i_features_3_3(daisy_chain_6_3_3), + .o_features_3_3(daisy_chain_7_3_3), + .i_features_3_4(daisy_chain_6_3_4), + .o_features_3_4(daisy_chain_7_3_4), + .i_features_3_5(daisy_chain_6_3_5), + .o_features_3_5(daisy_chain_7_3_5), + .i_features_4_0(daisy_chain_6_4_0), + .o_features_4_0(daisy_chain_7_4_0), + .i_features_4_1(daisy_chain_6_4_1), + .o_features_4_1(daisy_chain_7_4_1), + .i_features_4_2(daisy_chain_6_4_2), + .o_features_4_2(daisy_chain_7_4_2), + .i_features_4_3(daisy_chain_6_4_3), + .o_features_4_3(daisy_chain_7_4_3), + .i_features_4_4(daisy_chain_6_4_4), + .o_features_4_4(daisy_chain_7_4_4), + .i_features_4_5(daisy_chain_6_4_5), + .o_features_4_5(daisy_chain_7_4_5), + .i_features_5_0(daisy_chain_6_5_0), + .o_features_5_0(daisy_chain_7_5_0), + .i_features_5_1(daisy_chain_6_5_1), + .o_features_5_1(daisy_chain_7_5_1), + .i_features_5_2(daisy_chain_6_5_2), + .o_features_5_2(daisy_chain_7_5_2), + .i_features_5_3(daisy_chain_6_5_3), + .o_features_5_3(daisy_chain_7_5_3), + .i_features_5_4(daisy_chain_6_5_4), + .o_features_5_4(daisy_chain_7_5_4), + .i_features_5_5(daisy_chain_6_5_5), + .o_features_5_5(daisy_chain_7_5_5), + .i_features_6_0(daisy_chain_6_6_0), + .o_features_6_0(daisy_chain_7_6_0), + .i_features_6_1(daisy_chain_6_6_1), + .o_features_6_1(daisy_chain_7_6_1), + .i_features_6_2(daisy_chain_6_6_2), + .o_features_6_2(daisy_chain_7_6_2), + .i_features_6_3(daisy_chain_6_6_3), + .o_features_6_3(daisy_chain_7_6_3), + .i_features_6_4(daisy_chain_6_6_4), + .o_features_6_4(daisy_chain_7_6_4), + .i_features_6_5(daisy_chain_6_6_5), + .o_features_6_5(daisy_chain_7_6_5), + .i_features_7_0(daisy_chain_6_7_0), + .o_features_7_0(daisy_chain_7_7_0), + .i_features_7_1(daisy_chain_6_7_1), + .o_features_7_1(daisy_chain_7_7_1), + .i_features_7_2(daisy_chain_6_7_2), + .o_features_7_2(daisy_chain_7_7_2), + .i_features_7_3(daisy_chain_6_7_3), + .o_features_7_3(daisy_chain_7_7_3), + .i_features_7_4(daisy_chain_6_7_4), + .o_features_7_4(daisy_chain_7_7_4), + .i_features_7_5(daisy_chain_6_7_5), + .o_features_7_5(daisy_chain_7_7_5), + .o_result_0(PE_output_7_0), + .o_result_1(PE_output_7_1), + .o_result_2(PE_output_7_2), + .o_result_3(PE_output_7_3), + .o_result_4(PE_output_7_4), + .o_result_5(PE_output_7_5), + .o_valid(PE_valid_7), + .o_next_reset(PE_next_reset_7), + .o_next_valid(PE_next_valid_7) +); + +processing_element processing_element_inst_8 ( + .clk(clk), + .i_reset(PE_next_reset_7), + .i_valid(PE_next_valid_7), + .i_features_0_0(daisy_chain_7_0_0), + .o_features_0_0(daisy_chain_8_0_0), + .i_features_0_1(daisy_chain_7_0_1), + .o_features_0_1(daisy_chain_8_0_1), + .i_features_0_2(daisy_chain_7_0_2), + .o_features_0_2(daisy_chain_8_0_2), + .i_features_0_3(daisy_chain_7_0_3), + .o_features_0_3(daisy_chain_8_0_3), + .i_features_0_4(daisy_chain_7_0_4), + .o_features_0_4(daisy_chain_8_0_4), + .i_features_0_5(daisy_chain_7_0_5), + .o_features_0_5(daisy_chain_8_0_5), + .i_features_1_0(daisy_chain_7_1_0), + .o_features_1_0(daisy_chain_8_1_0), + .i_features_1_1(daisy_chain_7_1_1), + .o_features_1_1(daisy_chain_8_1_1), + .i_features_1_2(daisy_chain_7_1_2), + .o_features_1_2(daisy_chain_8_1_2), + .i_features_1_3(daisy_chain_7_1_3), + .o_features_1_3(daisy_chain_8_1_3), + .i_features_1_4(daisy_chain_7_1_4), + .o_features_1_4(daisy_chain_8_1_4), + .i_features_1_5(daisy_chain_7_1_5), + .o_features_1_5(daisy_chain_8_1_5), + .i_features_2_0(daisy_chain_7_2_0), + .o_features_2_0(daisy_chain_8_2_0), + .i_features_2_1(daisy_chain_7_2_1), + .o_features_2_1(daisy_chain_8_2_1), + .i_features_2_2(daisy_chain_7_2_2), + .o_features_2_2(daisy_chain_8_2_2), + .i_features_2_3(daisy_chain_7_2_3), + .o_features_2_3(daisy_chain_8_2_3), + .i_features_2_4(daisy_chain_7_2_4), + .o_features_2_4(daisy_chain_8_2_4), + .i_features_2_5(daisy_chain_7_2_5), + .o_features_2_5(daisy_chain_8_2_5), + .i_features_3_0(daisy_chain_7_3_0), + .o_features_3_0(daisy_chain_8_3_0), + .i_features_3_1(daisy_chain_7_3_1), + .o_features_3_1(daisy_chain_8_3_1), + .i_features_3_2(daisy_chain_7_3_2), + .o_features_3_2(daisy_chain_8_3_2), + .i_features_3_3(daisy_chain_7_3_3), + .o_features_3_3(daisy_chain_8_3_3), + .i_features_3_4(daisy_chain_7_3_4), + .o_features_3_4(daisy_chain_8_3_4), + .i_features_3_5(daisy_chain_7_3_5), + .o_features_3_5(daisy_chain_8_3_5), + .i_features_4_0(daisy_chain_7_4_0), + .o_features_4_0(daisy_chain_8_4_0), + .i_features_4_1(daisy_chain_7_4_1), + .o_features_4_1(daisy_chain_8_4_1), + .i_features_4_2(daisy_chain_7_4_2), + .o_features_4_2(daisy_chain_8_4_2), + .i_features_4_3(daisy_chain_7_4_3), + .o_features_4_3(daisy_chain_8_4_3), + .i_features_4_4(daisy_chain_7_4_4), + .o_features_4_4(daisy_chain_8_4_4), + .i_features_4_5(daisy_chain_7_4_5), + .o_features_4_5(daisy_chain_8_4_5), + .i_features_5_0(daisy_chain_7_5_0), + .o_features_5_0(daisy_chain_8_5_0), + .i_features_5_1(daisy_chain_7_5_1), + .o_features_5_1(daisy_chain_8_5_1), + .i_features_5_2(daisy_chain_7_5_2), + .o_features_5_2(daisy_chain_8_5_2), + .i_features_5_3(daisy_chain_7_5_3), + .o_features_5_3(daisy_chain_8_5_3), + .i_features_5_4(daisy_chain_7_5_4), + .o_features_5_4(daisy_chain_8_5_4), + .i_features_5_5(daisy_chain_7_5_5), + .o_features_5_5(daisy_chain_8_5_5), + .i_features_6_0(daisy_chain_7_6_0), + .o_features_6_0(daisy_chain_8_6_0), + .i_features_6_1(daisy_chain_7_6_1), + .o_features_6_1(daisy_chain_8_6_1), + .i_features_6_2(daisy_chain_7_6_2), + .o_features_6_2(daisy_chain_8_6_2), + .i_features_6_3(daisy_chain_7_6_3), + .o_features_6_3(daisy_chain_8_6_3), + .i_features_6_4(daisy_chain_7_6_4), + .o_features_6_4(daisy_chain_8_6_4), + .i_features_6_5(daisy_chain_7_6_5), + .o_features_6_5(daisy_chain_8_6_5), + .i_features_7_0(daisy_chain_7_7_0), + .o_features_7_0(daisy_chain_8_7_0), + .i_features_7_1(daisy_chain_7_7_1), + .o_features_7_1(daisy_chain_8_7_1), + .i_features_7_2(daisy_chain_7_7_2), + .o_features_7_2(daisy_chain_8_7_2), + .i_features_7_3(daisy_chain_7_7_3), + .o_features_7_3(daisy_chain_8_7_3), + .i_features_7_4(daisy_chain_7_7_4), + .o_features_7_4(daisy_chain_8_7_4), + .i_features_7_5(daisy_chain_7_7_5), + .o_features_7_5(daisy_chain_8_7_5), + .o_result_0(PE_output_8_0), + .o_result_1(PE_output_8_1), + .o_result_2(PE_output_8_2), + .o_result_3(PE_output_8_3), + .o_result_4(PE_output_8_4), + .o_result_5(PE_output_8_5), + .o_valid(PE_valid_8), + .o_next_reset(PE_next_reset_8), + .o_next_valid(PE_next_valid_8) +); + +processing_element processing_element_inst_9 ( + .clk(clk), + .i_reset(PE_next_reset_8), + .i_valid(PE_next_valid_8), + .i_features_0_0(daisy_chain_8_0_0), + .o_features_0_0(daisy_chain_9_0_0), + .i_features_0_1(daisy_chain_8_0_1), + .o_features_0_1(daisy_chain_9_0_1), + .i_features_0_2(daisy_chain_8_0_2), + .o_features_0_2(daisy_chain_9_0_2), + .i_features_0_3(daisy_chain_8_0_3), + .o_features_0_3(daisy_chain_9_0_3), + .i_features_0_4(daisy_chain_8_0_4), + .o_features_0_4(daisy_chain_9_0_4), + .i_features_0_5(daisy_chain_8_0_5), + .o_features_0_5(daisy_chain_9_0_5), + .i_features_1_0(daisy_chain_8_1_0), + .o_features_1_0(daisy_chain_9_1_0), + .i_features_1_1(daisy_chain_8_1_1), + .o_features_1_1(daisy_chain_9_1_1), + .i_features_1_2(daisy_chain_8_1_2), + .o_features_1_2(daisy_chain_9_1_2), + .i_features_1_3(daisy_chain_8_1_3), + .o_features_1_3(daisy_chain_9_1_3), + .i_features_1_4(daisy_chain_8_1_4), + .o_features_1_4(daisy_chain_9_1_4), + .i_features_1_5(daisy_chain_8_1_5), + .o_features_1_5(daisy_chain_9_1_5), + .i_features_2_0(daisy_chain_8_2_0), + .o_features_2_0(daisy_chain_9_2_0), + .i_features_2_1(daisy_chain_8_2_1), + .o_features_2_1(daisy_chain_9_2_1), + .i_features_2_2(daisy_chain_8_2_2), + .o_features_2_2(daisy_chain_9_2_2), + .i_features_2_3(daisy_chain_8_2_3), + .o_features_2_3(daisy_chain_9_2_3), + .i_features_2_4(daisy_chain_8_2_4), + .o_features_2_4(daisy_chain_9_2_4), + .i_features_2_5(daisy_chain_8_2_5), + .o_features_2_5(daisy_chain_9_2_5), + .i_features_3_0(daisy_chain_8_3_0), + .o_features_3_0(daisy_chain_9_3_0), + .i_features_3_1(daisy_chain_8_3_1), + .o_features_3_1(daisy_chain_9_3_1), + .i_features_3_2(daisy_chain_8_3_2), + .o_features_3_2(daisy_chain_9_3_2), + .i_features_3_3(daisy_chain_8_3_3), + .o_features_3_3(daisy_chain_9_3_3), + .i_features_3_4(daisy_chain_8_3_4), + .o_features_3_4(daisy_chain_9_3_4), + .i_features_3_5(daisy_chain_8_3_5), + .o_features_3_5(daisy_chain_9_3_5), + .i_features_4_0(daisy_chain_8_4_0), + .o_features_4_0(daisy_chain_9_4_0), + .i_features_4_1(daisy_chain_8_4_1), + .o_features_4_1(daisy_chain_9_4_1), + .i_features_4_2(daisy_chain_8_4_2), + .o_features_4_2(daisy_chain_9_4_2), + .i_features_4_3(daisy_chain_8_4_3), + .o_features_4_3(daisy_chain_9_4_3), + .i_features_4_4(daisy_chain_8_4_4), + .o_features_4_4(daisy_chain_9_4_4), + .i_features_4_5(daisy_chain_8_4_5), + .o_features_4_5(daisy_chain_9_4_5), + .i_features_5_0(daisy_chain_8_5_0), + .o_features_5_0(daisy_chain_9_5_0), + .i_features_5_1(daisy_chain_8_5_1), + .o_features_5_1(daisy_chain_9_5_1), + .i_features_5_2(daisy_chain_8_5_2), + .o_features_5_2(daisy_chain_9_5_2), + .i_features_5_3(daisy_chain_8_5_3), + .o_features_5_3(daisy_chain_9_5_3), + .i_features_5_4(daisy_chain_8_5_4), + .o_features_5_4(daisy_chain_9_5_4), + .i_features_5_5(daisy_chain_8_5_5), + .o_features_5_5(daisy_chain_9_5_5), + .i_features_6_0(daisy_chain_8_6_0), + .o_features_6_0(daisy_chain_9_6_0), + .i_features_6_1(daisy_chain_8_6_1), + .o_features_6_1(daisy_chain_9_6_1), + .i_features_6_2(daisy_chain_8_6_2), + .o_features_6_2(daisy_chain_9_6_2), + .i_features_6_3(daisy_chain_8_6_3), + .o_features_6_3(daisy_chain_9_6_3), + .i_features_6_4(daisy_chain_8_6_4), + .o_features_6_4(daisy_chain_9_6_4), + .i_features_6_5(daisy_chain_8_6_5), + .o_features_6_5(daisy_chain_9_6_5), + .i_features_7_0(daisy_chain_8_7_0), + .o_features_7_0(daisy_chain_9_7_0), + .i_features_7_1(daisy_chain_8_7_1), + .o_features_7_1(daisy_chain_9_7_1), + .i_features_7_2(daisy_chain_8_7_2), + .o_features_7_2(daisy_chain_9_7_2), + .i_features_7_3(daisy_chain_8_7_3), + .o_features_7_3(daisy_chain_9_7_3), + .i_features_7_4(daisy_chain_8_7_4), + .o_features_7_4(daisy_chain_9_7_4), + .i_features_7_5(daisy_chain_8_7_5), + .o_features_7_5(daisy_chain_9_7_5), + .o_result_0(PE_output_9_0), + .o_result_1(PE_output_9_1), + .o_result_2(PE_output_9_2), + .o_result_3(PE_output_9_3), + .o_result_4(PE_output_9_4), + .o_result_5(PE_output_9_5), + .o_valid(PE_valid_9), + .o_next_reset(PE_next_reset_9), + .o_next_valid(PE_next_valid_9) +); + +processing_element processing_element_inst_10 ( + .clk(clk), + .i_reset(PE_next_reset_9), + .i_valid(PE_next_valid_9), + .i_features_0_0(daisy_chain_9_0_0), + .o_features_0_0(daisy_chain_10_0_0), + .i_features_0_1(daisy_chain_9_0_1), + .o_features_0_1(daisy_chain_10_0_1), + .i_features_0_2(daisy_chain_9_0_2), + .o_features_0_2(daisy_chain_10_0_2), + .i_features_0_3(daisy_chain_9_0_3), + .o_features_0_3(daisy_chain_10_0_3), + .i_features_0_4(daisy_chain_9_0_4), + .o_features_0_4(daisy_chain_10_0_4), + .i_features_0_5(daisy_chain_9_0_5), + .o_features_0_5(daisy_chain_10_0_5), + .i_features_1_0(daisy_chain_9_1_0), + .o_features_1_0(daisy_chain_10_1_0), + .i_features_1_1(daisy_chain_9_1_1), + .o_features_1_1(daisy_chain_10_1_1), + .i_features_1_2(daisy_chain_9_1_2), + .o_features_1_2(daisy_chain_10_1_2), + .i_features_1_3(daisy_chain_9_1_3), + .o_features_1_3(daisy_chain_10_1_3), + .i_features_1_4(daisy_chain_9_1_4), + .o_features_1_4(daisy_chain_10_1_4), + .i_features_1_5(daisy_chain_9_1_5), + .o_features_1_5(daisy_chain_10_1_5), + .i_features_2_0(daisy_chain_9_2_0), + .o_features_2_0(daisy_chain_10_2_0), + .i_features_2_1(daisy_chain_9_2_1), + .o_features_2_1(daisy_chain_10_2_1), + .i_features_2_2(daisy_chain_9_2_2), + .o_features_2_2(daisy_chain_10_2_2), + .i_features_2_3(daisy_chain_9_2_3), + .o_features_2_3(daisy_chain_10_2_3), + .i_features_2_4(daisy_chain_9_2_4), + .o_features_2_4(daisy_chain_10_2_4), + .i_features_2_5(daisy_chain_9_2_5), + .o_features_2_5(daisy_chain_10_2_5), + .i_features_3_0(daisy_chain_9_3_0), + .o_features_3_0(daisy_chain_10_3_0), + .i_features_3_1(daisy_chain_9_3_1), + .o_features_3_1(daisy_chain_10_3_1), + .i_features_3_2(daisy_chain_9_3_2), + .o_features_3_2(daisy_chain_10_3_2), + .i_features_3_3(daisy_chain_9_3_3), + .o_features_3_3(daisy_chain_10_3_3), + .i_features_3_4(daisy_chain_9_3_4), + .o_features_3_4(daisy_chain_10_3_4), + .i_features_3_5(daisy_chain_9_3_5), + .o_features_3_5(daisy_chain_10_3_5), + .i_features_4_0(daisy_chain_9_4_0), + .o_features_4_0(daisy_chain_10_4_0), + .i_features_4_1(daisy_chain_9_4_1), + .o_features_4_1(daisy_chain_10_4_1), + .i_features_4_2(daisy_chain_9_4_2), + .o_features_4_2(daisy_chain_10_4_2), + .i_features_4_3(daisy_chain_9_4_3), + .o_features_4_3(daisy_chain_10_4_3), + .i_features_4_4(daisy_chain_9_4_4), + .o_features_4_4(daisy_chain_10_4_4), + .i_features_4_5(daisy_chain_9_4_5), + .o_features_4_5(daisy_chain_10_4_5), + .i_features_5_0(daisy_chain_9_5_0), + .o_features_5_0(daisy_chain_10_5_0), + .i_features_5_1(daisy_chain_9_5_1), + .o_features_5_1(daisy_chain_10_5_1), + .i_features_5_2(daisy_chain_9_5_2), + .o_features_5_2(daisy_chain_10_5_2), + .i_features_5_3(daisy_chain_9_5_3), + .o_features_5_3(daisy_chain_10_5_3), + .i_features_5_4(daisy_chain_9_5_4), + .o_features_5_4(daisy_chain_10_5_4), + .i_features_5_5(daisy_chain_9_5_5), + .o_features_5_5(daisy_chain_10_5_5), + .i_features_6_0(daisy_chain_9_6_0), + .o_features_6_0(daisy_chain_10_6_0), + .i_features_6_1(daisy_chain_9_6_1), + .o_features_6_1(daisy_chain_10_6_1), + .i_features_6_2(daisy_chain_9_6_2), + .o_features_6_2(daisy_chain_10_6_2), + .i_features_6_3(daisy_chain_9_6_3), + .o_features_6_3(daisy_chain_10_6_3), + .i_features_6_4(daisy_chain_9_6_4), + .o_features_6_4(daisy_chain_10_6_4), + .i_features_6_5(daisy_chain_9_6_5), + .o_features_6_5(daisy_chain_10_6_5), + .i_features_7_0(daisy_chain_9_7_0), + .o_features_7_0(daisy_chain_10_7_0), + .i_features_7_1(daisy_chain_9_7_1), + .o_features_7_1(daisy_chain_10_7_1), + .i_features_7_2(daisy_chain_9_7_2), + .o_features_7_2(daisy_chain_10_7_2), + .i_features_7_3(daisy_chain_9_7_3), + .o_features_7_3(daisy_chain_10_7_3), + .i_features_7_4(daisy_chain_9_7_4), + .o_features_7_4(daisy_chain_10_7_4), + .i_features_7_5(daisy_chain_9_7_5), + .o_features_7_5(daisy_chain_10_7_5), + .o_result_0(PE_output_10_0), + .o_result_1(PE_output_10_1), + .o_result_2(PE_output_10_2), + .o_result_3(PE_output_10_3), + .o_result_4(PE_output_10_4), + .o_result_5(PE_output_10_5), + .o_valid(PE_valid_10), + .o_next_reset(PE_next_reset_10), + .o_next_valid(PE_next_valid_10) +); + +processing_element processing_element_inst_11 ( + .clk(clk), + .i_reset(PE_next_reset_10), + .i_valid(PE_next_valid_10), + .i_features_0_0(daisy_chain_10_0_0), + .o_features_0_0(daisy_chain_11_0_0), + .i_features_0_1(daisy_chain_10_0_1), + .o_features_0_1(daisy_chain_11_0_1), + .i_features_0_2(daisy_chain_10_0_2), + .o_features_0_2(daisy_chain_11_0_2), + .i_features_0_3(daisy_chain_10_0_3), + .o_features_0_3(daisy_chain_11_0_3), + .i_features_0_4(daisy_chain_10_0_4), + .o_features_0_4(daisy_chain_11_0_4), + .i_features_0_5(daisy_chain_10_0_5), + .o_features_0_5(daisy_chain_11_0_5), + .i_features_1_0(daisy_chain_10_1_0), + .o_features_1_0(daisy_chain_11_1_0), + .i_features_1_1(daisy_chain_10_1_1), + .o_features_1_1(daisy_chain_11_1_1), + .i_features_1_2(daisy_chain_10_1_2), + .o_features_1_2(daisy_chain_11_1_2), + .i_features_1_3(daisy_chain_10_1_3), + .o_features_1_3(daisy_chain_11_1_3), + .i_features_1_4(daisy_chain_10_1_4), + .o_features_1_4(daisy_chain_11_1_4), + .i_features_1_5(daisy_chain_10_1_5), + .o_features_1_5(daisy_chain_11_1_5), + .i_features_2_0(daisy_chain_10_2_0), + .o_features_2_0(daisy_chain_11_2_0), + .i_features_2_1(daisy_chain_10_2_1), + .o_features_2_1(daisy_chain_11_2_1), + .i_features_2_2(daisy_chain_10_2_2), + .o_features_2_2(daisy_chain_11_2_2), + .i_features_2_3(daisy_chain_10_2_3), + .o_features_2_3(daisy_chain_11_2_3), + .i_features_2_4(daisy_chain_10_2_4), + .o_features_2_4(daisy_chain_11_2_4), + .i_features_2_5(daisy_chain_10_2_5), + .o_features_2_5(daisy_chain_11_2_5), + .i_features_3_0(daisy_chain_10_3_0), + .o_features_3_0(daisy_chain_11_3_0), + .i_features_3_1(daisy_chain_10_3_1), + .o_features_3_1(daisy_chain_11_3_1), + .i_features_3_2(daisy_chain_10_3_2), + .o_features_3_2(daisy_chain_11_3_2), + .i_features_3_3(daisy_chain_10_3_3), + .o_features_3_3(daisy_chain_11_3_3), + .i_features_3_4(daisy_chain_10_3_4), + .o_features_3_4(daisy_chain_11_3_4), + .i_features_3_5(daisy_chain_10_3_5), + .o_features_3_5(daisy_chain_11_3_5), + .i_features_4_0(daisy_chain_10_4_0), + .o_features_4_0(daisy_chain_11_4_0), + .i_features_4_1(daisy_chain_10_4_1), + .o_features_4_1(daisy_chain_11_4_1), + .i_features_4_2(daisy_chain_10_4_2), + .o_features_4_2(daisy_chain_11_4_2), + .i_features_4_3(daisy_chain_10_4_3), + .o_features_4_3(daisy_chain_11_4_3), + .i_features_4_4(daisy_chain_10_4_4), + .o_features_4_4(daisy_chain_11_4_4), + .i_features_4_5(daisy_chain_10_4_5), + .o_features_4_5(daisy_chain_11_4_5), + .i_features_5_0(daisy_chain_10_5_0), + .o_features_5_0(daisy_chain_11_5_0), + .i_features_5_1(daisy_chain_10_5_1), + .o_features_5_1(daisy_chain_11_5_1), + .i_features_5_2(daisy_chain_10_5_2), + .o_features_5_2(daisy_chain_11_5_2), + .i_features_5_3(daisy_chain_10_5_3), + .o_features_5_3(daisy_chain_11_5_3), + .i_features_5_4(daisy_chain_10_5_4), + .o_features_5_4(daisy_chain_11_5_4), + .i_features_5_5(daisy_chain_10_5_5), + .o_features_5_5(daisy_chain_11_5_5), + .i_features_6_0(daisy_chain_10_6_0), + .o_features_6_0(daisy_chain_11_6_0), + .i_features_6_1(daisy_chain_10_6_1), + .o_features_6_1(daisy_chain_11_6_1), + .i_features_6_2(daisy_chain_10_6_2), + .o_features_6_2(daisy_chain_11_6_2), + .i_features_6_3(daisy_chain_10_6_3), + .o_features_6_3(daisy_chain_11_6_3), + .i_features_6_4(daisy_chain_10_6_4), + .o_features_6_4(daisy_chain_11_6_4), + .i_features_6_5(daisy_chain_10_6_5), + .o_features_6_5(daisy_chain_11_6_5), + .i_features_7_0(daisy_chain_10_7_0), + .o_features_7_0(daisy_chain_11_7_0), + .i_features_7_1(daisy_chain_10_7_1), + .o_features_7_1(daisy_chain_11_7_1), + .i_features_7_2(daisy_chain_10_7_2), + .o_features_7_2(daisy_chain_11_7_2), + .i_features_7_3(daisy_chain_10_7_3), + .o_features_7_3(daisy_chain_11_7_3), + .i_features_7_4(daisy_chain_10_7_4), + .o_features_7_4(daisy_chain_11_7_4), + .i_features_7_5(daisy_chain_10_7_5), + .o_features_7_5(daisy_chain_11_7_5), + .o_result_0(PE_output_11_0), + .o_result_1(PE_output_11_1), + .o_result_2(PE_output_11_2), + .o_result_3(PE_output_11_3), + .o_result_4(PE_output_11_4), + .o_result_5(PE_output_11_5), + .o_valid(PE_valid_11), + .o_next_reset(PE_next_reset_11), + .o_next_valid(PE_next_valid_11) +); + +processing_element processing_element_inst_12 ( + .clk(clk), + .i_reset(PE_next_reset_11), + .i_valid(PE_next_valid_11), + .i_features_0_0(daisy_chain_11_0_0), + .o_features_0_0(daisy_chain_12_0_0), + .i_features_0_1(daisy_chain_11_0_1), + .o_features_0_1(daisy_chain_12_0_1), + .i_features_0_2(daisy_chain_11_0_2), + .o_features_0_2(daisy_chain_12_0_2), + .i_features_0_3(daisy_chain_11_0_3), + .o_features_0_3(daisy_chain_12_0_3), + .i_features_0_4(daisy_chain_11_0_4), + .o_features_0_4(daisy_chain_12_0_4), + .i_features_0_5(daisy_chain_11_0_5), + .o_features_0_5(daisy_chain_12_0_5), + .i_features_1_0(daisy_chain_11_1_0), + .o_features_1_0(daisy_chain_12_1_0), + .i_features_1_1(daisy_chain_11_1_1), + .o_features_1_1(daisy_chain_12_1_1), + .i_features_1_2(daisy_chain_11_1_2), + .o_features_1_2(daisy_chain_12_1_2), + .i_features_1_3(daisy_chain_11_1_3), + .o_features_1_3(daisy_chain_12_1_3), + .i_features_1_4(daisy_chain_11_1_4), + .o_features_1_4(daisy_chain_12_1_4), + .i_features_1_5(daisy_chain_11_1_5), + .o_features_1_5(daisy_chain_12_1_5), + .i_features_2_0(daisy_chain_11_2_0), + .o_features_2_0(daisy_chain_12_2_0), + .i_features_2_1(daisy_chain_11_2_1), + .o_features_2_1(daisy_chain_12_2_1), + .i_features_2_2(daisy_chain_11_2_2), + .o_features_2_2(daisy_chain_12_2_2), + .i_features_2_3(daisy_chain_11_2_3), + .o_features_2_3(daisy_chain_12_2_3), + .i_features_2_4(daisy_chain_11_2_4), + .o_features_2_4(daisy_chain_12_2_4), + .i_features_2_5(daisy_chain_11_2_5), + .o_features_2_5(daisy_chain_12_2_5), + .i_features_3_0(daisy_chain_11_3_0), + .o_features_3_0(daisy_chain_12_3_0), + .i_features_3_1(daisy_chain_11_3_1), + .o_features_3_1(daisy_chain_12_3_1), + .i_features_3_2(daisy_chain_11_3_2), + .o_features_3_2(daisy_chain_12_3_2), + .i_features_3_3(daisy_chain_11_3_3), + .o_features_3_3(daisy_chain_12_3_3), + .i_features_3_4(daisy_chain_11_3_4), + .o_features_3_4(daisy_chain_12_3_4), + .i_features_3_5(daisy_chain_11_3_5), + .o_features_3_5(daisy_chain_12_3_5), + .i_features_4_0(daisy_chain_11_4_0), + .o_features_4_0(daisy_chain_12_4_0), + .i_features_4_1(daisy_chain_11_4_1), + .o_features_4_1(daisy_chain_12_4_1), + .i_features_4_2(daisy_chain_11_4_2), + .o_features_4_2(daisy_chain_12_4_2), + .i_features_4_3(daisy_chain_11_4_3), + .o_features_4_3(daisy_chain_12_4_3), + .i_features_4_4(daisy_chain_11_4_4), + .o_features_4_4(daisy_chain_12_4_4), + .i_features_4_5(daisy_chain_11_4_5), + .o_features_4_5(daisy_chain_12_4_5), + .i_features_5_0(daisy_chain_11_5_0), + .o_features_5_0(daisy_chain_12_5_0), + .i_features_5_1(daisy_chain_11_5_1), + .o_features_5_1(daisy_chain_12_5_1), + .i_features_5_2(daisy_chain_11_5_2), + .o_features_5_2(daisy_chain_12_5_2), + .i_features_5_3(daisy_chain_11_5_3), + .o_features_5_3(daisy_chain_12_5_3), + .i_features_5_4(daisy_chain_11_5_4), + .o_features_5_4(daisy_chain_12_5_4), + .i_features_5_5(daisy_chain_11_5_5), + .o_features_5_5(daisy_chain_12_5_5), + .i_features_6_0(daisy_chain_11_6_0), + .o_features_6_0(daisy_chain_12_6_0), + .i_features_6_1(daisy_chain_11_6_1), + .o_features_6_1(daisy_chain_12_6_1), + .i_features_6_2(daisy_chain_11_6_2), + .o_features_6_2(daisy_chain_12_6_2), + .i_features_6_3(daisy_chain_11_6_3), + .o_features_6_3(daisy_chain_12_6_3), + .i_features_6_4(daisy_chain_11_6_4), + .o_features_6_4(daisy_chain_12_6_4), + .i_features_6_5(daisy_chain_11_6_5), + .o_features_6_5(daisy_chain_12_6_5), + .i_features_7_0(daisy_chain_11_7_0), + .o_features_7_0(daisy_chain_12_7_0), + .i_features_7_1(daisy_chain_11_7_1), + .o_features_7_1(daisy_chain_12_7_1), + .i_features_7_2(daisy_chain_11_7_2), + .o_features_7_2(daisy_chain_12_7_2), + .i_features_7_3(daisy_chain_11_7_3), + .o_features_7_3(daisy_chain_12_7_3), + .i_features_7_4(daisy_chain_11_7_4), + .o_features_7_4(daisy_chain_12_7_4), + .i_features_7_5(daisy_chain_11_7_5), + .o_features_7_5(daisy_chain_12_7_5), + .o_result_0(PE_output_12_0), + .o_result_1(PE_output_12_1), + .o_result_2(PE_output_12_2), + .o_result_3(PE_output_12_3), + .o_result_4(PE_output_12_4), + .o_result_5(PE_output_12_5), + .o_valid(PE_valid_12), + .o_next_reset(PE_next_reset_12), + .o_next_valid(PE_next_valid_12) +); + +processing_element processing_element_inst_13 ( + .clk(clk), + .i_reset(PE_next_reset_12), + .i_valid(PE_next_valid_12), + .i_features_0_0(daisy_chain_12_0_0), + .o_features_0_0(daisy_chain_13_0_0), + .i_features_0_1(daisy_chain_12_0_1), + .o_features_0_1(daisy_chain_13_0_1), + .i_features_0_2(daisy_chain_12_0_2), + .o_features_0_2(daisy_chain_13_0_2), + .i_features_0_3(daisy_chain_12_0_3), + .o_features_0_3(daisy_chain_13_0_3), + .i_features_0_4(daisy_chain_12_0_4), + .o_features_0_4(daisy_chain_13_0_4), + .i_features_0_5(daisy_chain_12_0_5), + .o_features_0_5(daisy_chain_13_0_5), + .i_features_1_0(daisy_chain_12_1_0), + .o_features_1_0(daisy_chain_13_1_0), + .i_features_1_1(daisy_chain_12_1_1), + .o_features_1_1(daisy_chain_13_1_1), + .i_features_1_2(daisy_chain_12_1_2), + .o_features_1_2(daisy_chain_13_1_2), + .i_features_1_3(daisy_chain_12_1_3), + .o_features_1_3(daisy_chain_13_1_3), + .i_features_1_4(daisy_chain_12_1_4), + .o_features_1_4(daisy_chain_13_1_4), + .i_features_1_5(daisy_chain_12_1_5), + .o_features_1_5(daisy_chain_13_1_5), + .i_features_2_0(daisy_chain_12_2_0), + .o_features_2_0(daisy_chain_13_2_0), + .i_features_2_1(daisy_chain_12_2_1), + .o_features_2_1(daisy_chain_13_2_1), + .i_features_2_2(daisy_chain_12_2_2), + .o_features_2_2(daisy_chain_13_2_2), + .i_features_2_3(daisy_chain_12_2_3), + .o_features_2_3(daisy_chain_13_2_3), + .i_features_2_4(daisy_chain_12_2_4), + .o_features_2_4(daisy_chain_13_2_4), + .i_features_2_5(daisy_chain_12_2_5), + .o_features_2_5(daisy_chain_13_2_5), + .i_features_3_0(daisy_chain_12_3_0), + .o_features_3_0(daisy_chain_13_3_0), + .i_features_3_1(daisy_chain_12_3_1), + .o_features_3_1(daisy_chain_13_3_1), + .i_features_3_2(daisy_chain_12_3_2), + .o_features_3_2(daisy_chain_13_3_2), + .i_features_3_3(daisy_chain_12_3_3), + .o_features_3_3(daisy_chain_13_3_3), + .i_features_3_4(daisy_chain_12_3_4), + .o_features_3_4(daisy_chain_13_3_4), + .i_features_3_5(daisy_chain_12_3_5), + .o_features_3_5(daisy_chain_13_3_5), + .i_features_4_0(daisy_chain_12_4_0), + .o_features_4_0(daisy_chain_13_4_0), + .i_features_4_1(daisy_chain_12_4_1), + .o_features_4_1(daisy_chain_13_4_1), + .i_features_4_2(daisy_chain_12_4_2), + .o_features_4_2(daisy_chain_13_4_2), + .i_features_4_3(daisy_chain_12_4_3), + .o_features_4_3(daisy_chain_13_4_3), + .i_features_4_4(daisy_chain_12_4_4), + .o_features_4_4(daisy_chain_13_4_4), + .i_features_4_5(daisy_chain_12_4_5), + .o_features_4_5(daisy_chain_13_4_5), + .i_features_5_0(daisy_chain_12_5_0), + .o_features_5_0(daisy_chain_13_5_0), + .i_features_5_1(daisy_chain_12_5_1), + .o_features_5_1(daisy_chain_13_5_1), + .i_features_5_2(daisy_chain_12_5_2), + .o_features_5_2(daisy_chain_13_5_2), + .i_features_5_3(daisy_chain_12_5_3), + .o_features_5_3(daisy_chain_13_5_3), + .i_features_5_4(daisy_chain_12_5_4), + .o_features_5_4(daisy_chain_13_5_4), + .i_features_5_5(daisy_chain_12_5_5), + .o_features_5_5(daisy_chain_13_5_5), + .i_features_6_0(daisy_chain_12_6_0), + .o_features_6_0(daisy_chain_13_6_0), + .i_features_6_1(daisy_chain_12_6_1), + .o_features_6_1(daisy_chain_13_6_1), + .i_features_6_2(daisy_chain_12_6_2), + .o_features_6_2(daisy_chain_13_6_2), + .i_features_6_3(daisy_chain_12_6_3), + .o_features_6_3(daisy_chain_13_6_3), + .i_features_6_4(daisy_chain_12_6_4), + .o_features_6_4(daisy_chain_13_6_4), + .i_features_6_5(daisy_chain_12_6_5), + .o_features_6_5(daisy_chain_13_6_5), + .i_features_7_0(daisy_chain_12_7_0), + .o_features_7_0(daisy_chain_13_7_0), + .i_features_7_1(daisy_chain_12_7_1), + .o_features_7_1(daisy_chain_13_7_1), + .i_features_7_2(daisy_chain_12_7_2), + .o_features_7_2(daisy_chain_13_7_2), + .i_features_7_3(daisy_chain_12_7_3), + .o_features_7_3(daisy_chain_13_7_3), + .i_features_7_4(daisy_chain_12_7_4), + .o_features_7_4(daisy_chain_13_7_4), + .i_features_7_5(daisy_chain_12_7_5), + .o_features_7_5(daisy_chain_13_7_5), + .o_result_0(PE_output_13_0), + .o_result_1(PE_output_13_1), + .o_result_2(PE_output_13_2), + .o_result_3(PE_output_13_3), + .o_result_4(PE_output_13_4), + .o_result_5(PE_output_13_5), + .o_valid(PE_valid_13), + .o_next_reset(PE_next_reset_13), + .o_next_valid(PE_next_valid_13) +); + +processing_element processing_element_inst_14 ( + .clk(clk), + .i_reset(PE_next_reset_13), + .i_valid(PE_next_valid_13), + .i_features_0_0(daisy_chain_13_0_0), + .o_features_0_0(daisy_chain_14_0_0), + .i_features_0_1(daisy_chain_13_0_1), + .o_features_0_1(daisy_chain_14_0_1), + .i_features_0_2(daisy_chain_13_0_2), + .o_features_0_2(daisy_chain_14_0_2), + .i_features_0_3(daisy_chain_13_0_3), + .o_features_0_3(daisy_chain_14_0_3), + .i_features_0_4(daisy_chain_13_0_4), + .o_features_0_4(daisy_chain_14_0_4), + .i_features_0_5(daisy_chain_13_0_5), + .o_features_0_5(daisy_chain_14_0_5), + .i_features_1_0(daisy_chain_13_1_0), + .o_features_1_0(daisy_chain_14_1_0), + .i_features_1_1(daisy_chain_13_1_1), + .o_features_1_1(daisy_chain_14_1_1), + .i_features_1_2(daisy_chain_13_1_2), + .o_features_1_2(daisy_chain_14_1_2), + .i_features_1_3(daisy_chain_13_1_3), + .o_features_1_3(daisy_chain_14_1_3), + .i_features_1_4(daisy_chain_13_1_4), + .o_features_1_4(daisy_chain_14_1_4), + .i_features_1_5(daisy_chain_13_1_5), + .o_features_1_5(daisy_chain_14_1_5), + .i_features_2_0(daisy_chain_13_2_0), + .o_features_2_0(daisy_chain_14_2_0), + .i_features_2_1(daisy_chain_13_2_1), + .o_features_2_1(daisy_chain_14_2_1), + .i_features_2_2(daisy_chain_13_2_2), + .o_features_2_2(daisy_chain_14_2_2), + .i_features_2_3(daisy_chain_13_2_3), + .o_features_2_3(daisy_chain_14_2_3), + .i_features_2_4(daisy_chain_13_2_4), + .o_features_2_4(daisy_chain_14_2_4), + .i_features_2_5(daisy_chain_13_2_5), + .o_features_2_5(daisy_chain_14_2_5), + .i_features_3_0(daisy_chain_13_3_0), + .o_features_3_0(daisy_chain_14_3_0), + .i_features_3_1(daisy_chain_13_3_1), + .o_features_3_1(daisy_chain_14_3_1), + .i_features_3_2(daisy_chain_13_3_2), + .o_features_3_2(daisy_chain_14_3_2), + .i_features_3_3(daisy_chain_13_3_3), + .o_features_3_3(daisy_chain_14_3_3), + .i_features_3_4(daisy_chain_13_3_4), + .o_features_3_4(daisy_chain_14_3_4), + .i_features_3_5(daisy_chain_13_3_5), + .o_features_3_5(daisy_chain_14_3_5), + .i_features_4_0(daisy_chain_13_4_0), + .o_features_4_0(daisy_chain_14_4_0), + .i_features_4_1(daisy_chain_13_4_1), + .o_features_4_1(daisy_chain_14_4_1), + .i_features_4_2(daisy_chain_13_4_2), + .o_features_4_2(daisy_chain_14_4_2), + .i_features_4_3(daisy_chain_13_4_3), + .o_features_4_3(daisy_chain_14_4_3), + .i_features_4_4(daisy_chain_13_4_4), + .o_features_4_4(daisy_chain_14_4_4), + .i_features_4_5(daisy_chain_13_4_5), + .o_features_4_5(daisy_chain_14_4_5), + .i_features_5_0(daisy_chain_13_5_0), + .o_features_5_0(daisy_chain_14_5_0), + .i_features_5_1(daisy_chain_13_5_1), + .o_features_5_1(daisy_chain_14_5_1), + .i_features_5_2(daisy_chain_13_5_2), + .o_features_5_2(daisy_chain_14_5_2), + .i_features_5_3(daisy_chain_13_5_3), + .o_features_5_3(daisy_chain_14_5_3), + .i_features_5_4(daisy_chain_13_5_4), + .o_features_5_4(daisy_chain_14_5_4), + .i_features_5_5(daisy_chain_13_5_5), + .o_features_5_5(daisy_chain_14_5_5), + .i_features_6_0(daisy_chain_13_6_0), + .o_features_6_0(daisy_chain_14_6_0), + .i_features_6_1(daisy_chain_13_6_1), + .o_features_6_1(daisy_chain_14_6_1), + .i_features_6_2(daisy_chain_13_6_2), + .o_features_6_2(daisy_chain_14_6_2), + .i_features_6_3(daisy_chain_13_6_3), + .o_features_6_3(daisy_chain_14_6_3), + .i_features_6_4(daisy_chain_13_6_4), + .o_features_6_4(daisy_chain_14_6_4), + .i_features_6_5(daisy_chain_13_6_5), + .o_features_6_5(daisy_chain_14_6_5), + .i_features_7_0(daisy_chain_13_7_0), + .o_features_7_0(daisy_chain_14_7_0), + .i_features_7_1(daisy_chain_13_7_1), + .o_features_7_1(daisy_chain_14_7_1), + .i_features_7_2(daisy_chain_13_7_2), + .o_features_7_2(daisy_chain_14_7_2), + .i_features_7_3(daisy_chain_13_7_3), + .o_features_7_3(daisy_chain_14_7_3), + .i_features_7_4(daisy_chain_13_7_4), + .o_features_7_4(daisy_chain_14_7_4), + .i_features_7_5(daisy_chain_13_7_5), + .o_features_7_5(daisy_chain_14_7_5), + .o_result_0(PE_output_14_0), + .o_result_1(PE_output_14_1), + .o_result_2(PE_output_14_2), + .o_result_3(PE_output_14_3), + .o_result_4(PE_output_14_4), + .o_result_5(PE_output_14_5), + .o_valid(PE_valid_14), + .o_next_reset(PE_next_reset_14), + .o_next_valid(PE_next_valid_14) +); + +processing_element processing_element_inst_15 ( + .clk(clk), + .i_reset(PE_next_reset_14), + .i_valid(PE_next_valid_14), + .i_features_0_0(daisy_chain_14_0_0), + .o_features_0_0(daisy_chain_15_0_0), + .i_features_0_1(daisy_chain_14_0_1), + .o_features_0_1(daisy_chain_15_0_1), + .i_features_0_2(daisy_chain_14_0_2), + .o_features_0_2(daisy_chain_15_0_2), + .i_features_0_3(daisy_chain_14_0_3), + .o_features_0_3(daisy_chain_15_0_3), + .i_features_0_4(daisy_chain_14_0_4), + .o_features_0_4(daisy_chain_15_0_4), + .i_features_0_5(daisy_chain_14_0_5), + .o_features_0_5(daisy_chain_15_0_5), + .i_features_1_0(daisy_chain_14_1_0), + .o_features_1_0(daisy_chain_15_1_0), + .i_features_1_1(daisy_chain_14_1_1), + .o_features_1_1(daisy_chain_15_1_1), + .i_features_1_2(daisy_chain_14_1_2), + .o_features_1_2(daisy_chain_15_1_2), + .i_features_1_3(daisy_chain_14_1_3), + .o_features_1_3(daisy_chain_15_1_3), + .i_features_1_4(daisy_chain_14_1_4), + .o_features_1_4(daisy_chain_15_1_4), + .i_features_1_5(daisy_chain_14_1_5), + .o_features_1_5(daisy_chain_15_1_5), + .i_features_2_0(daisy_chain_14_2_0), + .o_features_2_0(daisy_chain_15_2_0), + .i_features_2_1(daisy_chain_14_2_1), + .o_features_2_1(daisy_chain_15_2_1), + .i_features_2_2(daisy_chain_14_2_2), + .o_features_2_2(daisy_chain_15_2_2), + .i_features_2_3(daisy_chain_14_2_3), + .o_features_2_3(daisy_chain_15_2_3), + .i_features_2_4(daisy_chain_14_2_4), + .o_features_2_4(daisy_chain_15_2_4), + .i_features_2_5(daisy_chain_14_2_5), + .o_features_2_5(daisy_chain_15_2_5), + .i_features_3_0(daisy_chain_14_3_0), + .o_features_3_0(daisy_chain_15_3_0), + .i_features_3_1(daisy_chain_14_3_1), + .o_features_3_1(daisy_chain_15_3_1), + .i_features_3_2(daisy_chain_14_3_2), + .o_features_3_2(daisy_chain_15_3_2), + .i_features_3_3(daisy_chain_14_3_3), + .o_features_3_3(daisy_chain_15_3_3), + .i_features_3_4(daisy_chain_14_3_4), + .o_features_3_4(daisy_chain_15_3_4), + .i_features_3_5(daisy_chain_14_3_5), + .o_features_3_5(daisy_chain_15_3_5), + .i_features_4_0(daisy_chain_14_4_0), + .o_features_4_0(daisy_chain_15_4_0), + .i_features_4_1(daisy_chain_14_4_1), + .o_features_4_1(daisy_chain_15_4_1), + .i_features_4_2(daisy_chain_14_4_2), + .o_features_4_2(daisy_chain_15_4_2), + .i_features_4_3(daisy_chain_14_4_3), + .o_features_4_3(daisy_chain_15_4_3), + .i_features_4_4(daisy_chain_14_4_4), + .o_features_4_4(daisy_chain_15_4_4), + .i_features_4_5(daisy_chain_14_4_5), + .o_features_4_5(daisy_chain_15_4_5), + .i_features_5_0(daisy_chain_14_5_0), + .o_features_5_0(daisy_chain_15_5_0), + .i_features_5_1(daisy_chain_14_5_1), + .o_features_5_1(daisy_chain_15_5_1), + .i_features_5_2(daisy_chain_14_5_2), + .o_features_5_2(daisy_chain_15_5_2), + .i_features_5_3(daisy_chain_14_5_3), + .o_features_5_3(daisy_chain_15_5_3), + .i_features_5_4(daisy_chain_14_5_4), + .o_features_5_4(daisy_chain_15_5_4), + .i_features_5_5(daisy_chain_14_5_5), + .o_features_5_5(daisy_chain_15_5_5), + .i_features_6_0(daisy_chain_14_6_0), + .o_features_6_0(daisy_chain_15_6_0), + .i_features_6_1(daisy_chain_14_6_1), + .o_features_6_1(daisy_chain_15_6_1), + .i_features_6_2(daisy_chain_14_6_2), + .o_features_6_2(daisy_chain_15_6_2), + .i_features_6_3(daisy_chain_14_6_3), + .o_features_6_3(daisy_chain_15_6_3), + .i_features_6_4(daisy_chain_14_6_4), + .o_features_6_4(daisy_chain_15_6_4), + .i_features_6_5(daisy_chain_14_6_5), + .o_features_6_5(daisy_chain_15_6_5), + .i_features_7_0(daisy_chain_14_7_0), + .o_features_7_0(daisy_chain_15_7_0), + .i_features_7_1(daisy_chain_14_7_1), + .o_features_7_1(daisy_chain_15_7_1), + .i_features_7_2(daisy_chain_14_7_2), + .o_features_7_2(daisy_chain_15_7_2), + .i_features_7_3(daisy_chain_14_7_3), + .o_features_7_3(daisy_chain_15_7_3), + .i_features_7_4(daisy_chain_14_7_4), + .o_features_7_4(daisy_chain_15_7_4), + .i_features_7_5(daisy_chain_14_7_5), + .o_features_7_5(daisy_chain_15_7_5), + .o_result_0(PE_output_15_0), + .o_result_1(PE_output_15_1), + .o_result_2(PE_output_15_2), + .o_result_3(PE_output_15_3), + .o_result_4(PE_output_15_4), + .o_result_5(PE_output_15_5), + .o_valid(PE_valid_15), + .o_next_reset(PE_next_reset_15), + .o_next_valid(PE_next_valid_15) +); + +processing_element processing_element_inst_16 ( + .clk(clk), + .i_reset(PE_next_reset_15), + .i_valid(PE_next_valid_15), + .i_features_0_0(daisy_chain_15_0_0), + .o_features_0_0(daisy_chain_16_0_0), + .i_features_0_1(daisy_chain_15_0_1), + .o_features_0_1(daisy_chain_16_0_1), + .i_features_0_2(daisy_chain_15_0_2), + .o_features_0_2(daisy_chain_16_0_2), + .i_features_0_3(daisy_chain_15_0_3), + .o_features_0_3(daisy_chain_16_0_3), + .i_features_0_4(daisy_chain_15_0_4), + .o_features_0_4(daisy_chain_16_0_4), + .i_features_0_5(daisy_chain_15_0_5), + .o_features_0_5(daisy_chain_16_0_5), + .i_features_1_0(daisy_chain_15_1_0), + .o_features_1_0(daisy_chain_16_1_0), + .i_features_1_1(daisy_chain_15_1_1), + .o_features_1_1(daisy_chain_16_1_1), + .i_features_1_2(daisy_chain_15_1_2), + .o_features_1_2(daisy_chain_16_1_2), + .i_features_1_3(daisy_chain_15_1_3), + .o_features_1_3(daisy_chain_16_1_3), + .i_features_1_4(daisy_chain_15_1_4), + .o_features_1_4(daisy_chain_16_1_4), + .i_features_1_5(daisy_chain_15_1_5), + .o_features_1_5(daisy_chain_16_1_5), + .i_features_2_0(daisy_chain_15_2_0), + .o_features_2_0(daisy_chain_16_2_0), + .i_features_2_1(daisy_chain_15_2_1), + .o_features_2_1(daisy_chain_16_2_1), + .i_features_2_2(daisy_chain_15_2_2), + .o_features_2_2(daisy_chain_16_2_2), + .i_features_2_3(daisy_chain_15_2_3), + .o_features_2_3(daisy_chain_16_2_3), + .i_features_2_4(daisy_chain_15_2_4), + .o_features_2_4(daisy_chain_16_2_4), + .i_features_2_5(daisy_chain_15_2_5), + .o_features_2_5(daisy_chain_16_2_5), + .i_features_3_0(daisy_chain_15_3_0), + .o_features_3_0(daisy_chain_16_3_0), + .i_features_3_1(daisy_chain_15_3_1), + .o_features_3_1(daisy_chain_16_3_1), + .i_features_3_2(daisy_chain_15_3_2), + .o_features_3_2(daisy_chain_16_3_2), + .i_features_3_3(daisy_chain_15_3_3), + .o_features_3_3(daisy_chain_16_3_3), + .i_features_3_4(daisy_chain_15_3_4), + .o_features_3_4(daisy_chain_16_3_4), + .i_features_3_5(daisy_chain_15_3_5), + .o_features_3_5(daisy_chain_16_3_5), + .i_features_4_0(daisy_chain_15_4_0), + .o_features_4_0(daisy_chain_16_4_0), + .i_features_4_1(daisy_chain_15_4_1), + .o_features_4_1(daisy_chain_16_4_1), + .i_features_4_2(daisy_chain_15_4_2), + .o_features_4_2(daisy_chain_16_4_2), + .i_features_4_3(daisy_chain_15_4_3), + .o_features_4_3(daisy_chain_16_4_3), + .i_features_4_4(daisy_chain_15_4_4), + .o_features_4_4(daisy_chain_16_4_4), + .i_features_4_5(daisy_chain_15_4_5), + .o_features_4_5(daisy_chain_16_4_5), + .i_features_5_0(daisy_chain_15_5_0), + .o_features_5_0(daisy_chain_16_5_0), + .i_features_5_1(daisy_chain_15_5_1), + .o_features_5_1(daisy_chain_16_5_1), + .i_features_5_2(daisy_chain_15_5_2), + .o_features_5_2(daisy_chain_16_5_2), + .i_features_5_3(daisy_chain_15_5_3), + .o_features_5_3(daisy_chain_16_5_3), + .i_features_5_4(daisy_chain_15_5_4), + .o_features_5_4(daisy_chain_16_5_4), + .i_features_5_5(daisy_chain_15_5_5), + .o_features_5_5(daisy_chain_16_5_5), + .i_features_6_0(daisy_chain_15_6_0), + .o_features_6_0(daisy_chain_16_6_0), + .i_features_6_1(daisy_chain_15_6_1), + .o_features_6_1(daisy_chain_16_6_1), + .i_features_6_2(daisy_chain_15_6_2), + .o_features_6_2(daisy_chain_16_6_2), + .i_features_6_3(daisy_chain_15_6_3), + .o_features_6_3(daisy_chain_16_6_3), + .i_features_6_4(daisy_chain_15_6_4), + .o_features_6_4(daisy_chain_16_6_4), + .i_features_6_5(daisy_chain_15_6_5), + .o_features_6_5(daisy_chain_16_6_5), + .i_features_7_0(daisy_chain_15_7_0), + .o_features_7_0(daisy_chain_16_7_0), + .i_features_7_1(daisy_chain_15_7_1), + .o_features_7_1(daisy_chain_16_7_1), + .i_features_7_2(daisy_chain_15_7_2), + .o_features_7_2(daisy_chain_16_7_2), + .i_features_7_3(daisy_chain_15_7_3), + .o_features_7_3(daisy_chain_16_7_3), + .i_features_7_4(daisy_chain_15_7_4), + .o_features_7_4(daisy_chain_16_7_4), + .i_features_7_5(daisy_chain_15_7_5), + .o_features_7_5(daisy_chain_16_7_5), + .o_result_0(PE_output_16_0), + .o_result_1(PE_output_16_1), + .o_result_2(PE_output_16_2), + .o_result_3(PE_output_16_3), + .o_result_4(PE_output_16_4), + .o_result_5(PE_output_16_5), + .o_valid(PE_valid_16), + .o_next_reset(PE_next_reset_16), + .o_next_valid(PE_next_valid_16) +); + +processing_element processing_element_inst_17 ( + .clk(clk), + .i_reset(PE_next_reset_16), + .i_valid(PE_next_valid_16), + .i_features_0_0(daisy_chain_16_0_0), + .o_features_0_0(daisy_chain_17_0_0), + .i_features_0_1(daisy_chain_16_0_1), + .o_features_0_1(daisy_chain_17_0_1), + .i_features_0_2(daisy_chain_16_0_2), + .o_features_0_2(daisy_chain_17_0_2), + .i_features_0_3(daisy_chain_16_0_3), + .o_features_0_3(daisy_chain_17_0_3), + .i_features_0_4(daisy_chain_16_0_4), + .o_features_0_4(daisy_chain_17_0_4), + .i_features_0_5(daisy_chain_16_0_5), + .o_features_0_5(daisy_chain_17_0_5), + .i_features_1_0(daisy_chain_16_1_0), + .o_features_1_0(daisy_chain_17_1_0), + .i_features_1_1(daisy_chain_16_1_1), + .o_features_1_1(daisy_chain_17_1_1), + .i_features_1_2(daisy_chain_16_1_2), + .o_features_1_2(daisy_chain_17_1_2), + .i_features_1_3(daisy_chain_16_1_3), + .o_features_1_3(daisy_chain_17_1_3), + .i_features_1_4(daisy_chain_16_1_4), + .o_features_1_4(daisy_chain_17_1_4), + .i_features_1_5(daisy_chain_16_1_5), + .o_features_1_5(daisy_chain_17_1_5), + .i_features_2_0(daisy_chain_16_2_0), + .o_features_2_0(daisy_chain_17_2_0), + .i_features_2_1(daisy_chain_16_2_1), + .o_features_2_1(daisy_chain_17_2_1), + .i_features_2_2(daisy_chain_16_2_2), + .o_features_2_2(daisy_chain_17_2_2), + .i_features_2_3(daisy_chain_16_2_3), + .o_features_2_3(daisy_chain_17_2_3), + .i_features_2_4(daisy_chain_16_2_4), + .o_features_2_4(daisy_chain_17_2_4), + .i_features_2_5(daisy_chain_16_2_5), + .o_features_2_5(daisy_chain_17_2_5), + .i_features_3_0(daisy_chain_16_3_0), + .o_features_3_0(daisy_chain_17_3_0), + .i_features_3_1(daisy_chain_16_3_1), + .o_features_3_1(daisy_chain_17_3_1), + .i_features_3_2(daisy_chain_16_3_2), + .o_features_3_2(daisy_chain_17_3_2), + .i_features_3_3(daisy_chain_16_3_3), + .o_features_3_3(daisy_chain_17_3_3), + .i_features_3_4(daisy_chain_16_3_4), + .o_features_3_4(daisy_chain_17_3_4), + .i_features_3_5(daisy_chain_16_3_5), + .o_features_3_5(daisy_chain_17_3_5), + .i_features_4_0(daisy_chain_16_4_0), + .o_features_4_0(daisy_chain_17_4_0), + .i_features_4_1(daisy_chain_16_4_1), + .o_features_4_1(daisy_chain_17_4_1), + .i_features_4_2(daisy_chain_16_4_2), + .o_features_4_2(daisy_chain_17_4_2), + .i_features_4_3(daisy_chain_16_4_3), + .o_features_4_3(daisy_chain_17_4_3), + .i_features_4_4(daisy_chain_16_4_4), + .o_features_4_4(daisy_chain_17_4_4), + .i_features_4_5(daisy_chain_16_4_5), + .o_features_4_5(daisy_chain_17_4_5), + .i_features_5_0(daisy_chain_16_5_0), + .o_features_5_0(daisy_chain_17_5_0), + .i_features_5_1(daisy_chain_16_5_1), + .o_features_5_1(daisy_chain_17_5_1), + .i_features_5_2(daisy_chain_16_5_2), + .o_features_5_2(daisy_chain_17_5_2), + .i_features_5_3(daisy_chain_16_5_3), + .o_features_5_3(daisy_chain_17_5_3), + .i_features_5_4(daisy_chain_16_5_4), + .o_features_5_4(daisy_chain_17_5_4), + .i_features_5_5(daisy_chain_16_5_5), + .o_features_5_5(daisy_chain_17_5_5), + .i_features_6_0(daisy_chain_16_6_0), + .o_features_6_0(daisy_chain_17_6_0), + .i_features_6_1(daisy_chain_16_6_1), + .o_features_6_1(daisy_chain_17_6_1), + .i_features_6_2(daisy_chain_16_6_2), + .o_features_6_2(daisy_chain_17_6_2), + .i_features_6_3(daisy_chain_16_6_3), + .o_features_6_3(daisy_chain_17_6_3), + .i_features_6_4(daisy_chain_16_6_4), + .o_features_6_4(daisy_chain_17_6_4), + .i_features_6_5(daisy_chain_16_6_5), + .o_features_6_5(daisy_chain_17_6_5), + .i_features_7_0(daisy_chain_16_7_0), + .o_features_7_0(daisy_chain_17_7_0), + .i_features_7_1(daisy_chain_16_7_1), + .o_features_7_1(daisy_chain_17_7_1), + .i_features_7_2(daisy_chain_16_7_2), + .o_features_7_2(daisy_chain_17_7_2), + .i_features_7_3(daisy_chain_16_7_3), + .o_features_7_3(daisy_chain_17_7_3), + .i_features_7_4(daisy_chain_16_7_4), + .o_features_7_4(daisy_chain_17_7_4), + .i_features_7_5(daisy_chain_16_7_5), + .o_features_7_5(daisy_chain_17_7_5), + .o_result_0(PE_output_17_0), + .o_result_1(PE_output_17_1), + .o_result_2(PE_output_17_2), + .o_result_3(PE_output_17_3), + .o_result_4(PE_output_17_4), + .o_result_5(PE_output_17_5), + .o_valid(PE_valid_17), + .o_next_reset(PE_next_reset_17), + .o_next_valid(PE_next_valid_17) +); + +processing_element processing_element_inst_18 ( + .clk(clk), + .i_reset(PE_next_reset_17), + .i_valid(PE_next_valid_17), + .i_features_0_0(daisy_chain_17_0_0), + .o_features_0_0(daisy_chain_18_0_0), + .i_features_0_1(daisy_chain_17_0_1), + .o_features_0_1(daisy_chain_18_0_1), + .i_features_0_2(daisy_chain_17_0_2), + .o_features_0_2(daisy_chain_18_0_2), + .i_features_0_3(daisy_chain_17_0_3), + .o_features_0_3(daisy_chain_18_0_3), + .i_features_0_4(daisy_chain_17_0_4), + .o_features_0_4(daisy_chain_18_0_4), + .i_features_0_5(daisy_chain_17_0_5), + .o_features_0_5(daisy_chain_18_0_5), + .i_features_1_0(daisy_chain_17_1_0), + .o_features_1_0(daisy_chain_18_1_0), + .i_features_1_1(daisy_chain_17_1_1), + .o_features_1_1(daisy_chain_18_1_1), + .i_features_1_2(daisy_chain_17_1_2), + .o_features_1_2(daisy_chain_18_1_2), + .i_features_1_3(daisy_chain_17_1_3), + .o_features_1_3(daisy_chain_18_1_3), + .i_features_1_4(daisy_chain_17_1_4), + .o_features_1_4(daisy_chain_18_1_4), + .i_features_1_5(daisy_chain_17_1_5), + .o_features_1_5(daisy_chain_18_1_5), + .i_features_2_0(daisy_chain_17_2_0), + .o_features_2_0(daisy_chain_18_2_0), + .i_features_2_1(daisy_chain_17_2_1), + .o_features_2_1(daisy_chain_18_2_1), + .i_features_2_2(daisy_chain_17_2_2), + .o_features_2_2(daisy_chain_18_2_2), + .i_features_2_3(daisy_chain_17_2_3), + .o_features_2_3(daisy_chain_18_2_3), + .i_features_2_4(daisy_chain_17_2_4), + .o_features_2_4(daisy_chain_18_2_4), + .i_features_2_5(daisy_chain_17_2_5), + .o_features_2_5(daisy_chain_18_2_5), + .i_features_3_0(daisy_chain_17_3_0), + .o_features_3_0(daisy_chain_18_3_0), + .i_features_3_1(daisy_chain_17_3_1), + .o_features_3_1(daisy_chain_18_3_1), + .i_features_3_2(daisy_chain_17_3_2), + .o_features_3_2(daisy_chain_18_3_2), + .i_features_3_3(daisy_chain_17_3_3), + .o_features_3_3(daisy_chain_18_3_3), + .i_features_3_4(daisy_chain_17_3_4), + .o_features_3_4(daisy_chain_18_3_4), + .i_features_3_5(daisy_chain_17_3_5), + .o_features_3_5(daisy_chain_18_3_5), + .i_features_4_0(daisy_chain_17_4_0), + .o_features_4_0(daisy_chain_18_4_0), + .i_features_4_1(daisy_chain_17_4_1), + .o_features_4_1(daisy_chain_18_4_1), + .i_features_4_2(daisy_chain_17_4_2), + .o_features_4_2(daisy_chain_18_4_2), + .i_features_4_3(daisy_chain_17_4_3), + .o_features_4_3(daisy_chain_18_4_3), + .i_features_4_4(daisy_chain_17_4_4), + .o_features_4_4(daisy_chain_18_4_4), + .i_features_4_5(daisy_chain_17_4_5), + .o_features_4_5(daisy_chain_18_4_5), + .i_features_5_0(daisy_chain_17_5_0), + .o_features_5_0(daisy_chain_18_5_0), + .i_features_5_1(daisy_chain_17_5_1), + .o_features_5_1(daisy_chain_18_5_1), + .i_features_5_2(daisy_chain_17_5_2), + .o_features_5_2(daisy_chain_18_5_2), + .i_features_5_3(daisy_chain_17_5_3), + .o_features_5_3(daisy_chain_18_5_3), + .i_features_5_4(daisy_chain_17_5_4), + .o_features_5_4(daisy_chain_18_5_4), + .i_features_5_5(daisy_chain_17_5_5), + .o_features_5_5(daisy_chain_18_5_5), + .i_features_6_0(daisy_chain_17_6_0), + .o_features_6_0(daisy_chain_18_6_0), + .i_features_6_1(daisy_chain_17_6_1), + .o_features_6_1(daisy_chain_18_6_1), + .i_features_6_2(daisy_chain_17_6_2), + .o_features_6_2(daisy_chain_18_6_2), + .i_features_6_3(daisy_chain_17_6_3), + .o_features_6_3(daisy_chain_18_6_3), + .i_features_6_4(daisy_chain_17_6_4), + .o_features_6_4(daisy_chain_18_6_4), + .i_features_6_5(daisy_chain_17_6_5), + .o_features_6_5(daisy_chain_18_6_5), + .i_features_7_0(daisy_chain_17_7_0), + .o_features_7_0(daisy_chain_18_7_0), + .i_features_7_1(daisy_chain_17_7_1), + .o_features_7_1(daisy_chain_18_7_1), + .i_features_7_2(daisy_chain_17_7_2), + .o_features_7_2(daisy_chain_18_7_2), + .i_features_7_3(daisy_chain_17_7_3), + .o_features_7_3(daisy_chain_18_7_3), + .i_features_7_4(daisy_chain_17_7_4), + .o_features_7_4(daisy_chain_18_7_4), + .i_features_7_5(daisy_chain_17_7_5), + .o_features_7_5(daisy_chain_18_7_5), + .o_result_0(PE_output_18_0), + .o_result_1(PE_output_18_1), + .o_result_2(PE_output_18_2), + .o_result_3(PE_output_18_3), + .o_result_4(PE_output_18_4), + .o_result_5(PE_output_18_5), + .o_valid(PE_valid_18), + .o_next_reset(PE_next_reset_18), + .o_next_valid(PE_next_valid_18) +); + +processing_element processing_element_inst_19 ( + .clk(clk), + .i_reset(PE_next_reset_18), + .i_valid(PE_next_valid_18), + .i_features_0_0(daisy_chain_18_0_0), + .o_features_0_0(daisy_chain_19_0_0), + .i_features_0_1(daisy_chain_18_0_1), + .o_features_0_1(daisy_chain_19_0_1), + .i_features_0_2(daisy_chain_18_0_2), + .o_features_0_2(daisy_chain_19_0_2), + .i_features_0_3(daisy_chain_18_0_3), + .o_features_0_3(daisy_chain_19_0_3), + .i_features_0_4(daisy_chain_18_0_4), + .o_features_0_4(daisy_chain_19_0_4), + .i_features_0_5(daisy_chain_18_0_5), + .o_features_0_5(daisy_chain_19_0_5), + .i_features_1_0(daisy_chain_18_1_0), + .o_features_1_0(daisy_chain_19_1_0), + .i_features_1_1(daisy_chain_18_1_1), + .o_features_1_1(daisy_chain_19_1_1), + .i_features_1_2(daisy_chain_18_1_2), + .o_features_1_2(daisy_chain_19_1_2), + .i_features_1_3(daisy_chain_18_1_3), + .o_features_1_3(daisy_chain_19_1_3), + .i_features_1_4(daisy_chain_18_1_4), + .o_features_1_4(daisy_chain_19_1_4), + .i_features_1_5(daisy_chain_18_1_5), + .o_features_1_5(daisy_chain_19_1_5), + .i_features_2_0(daisy_chain_18_2_0), + .o_features_2_0(daisy_chain_19_2_0), + .i_features_2_1(daisy_chain_18_2_1), + .o_features_2_1(daisy_chain_19_2_1), + .i_features_2_2(daisy_chain_18_2_2), + .o_features_2_2(daisy_chain_19_2_2), + .i_features_2_3(daisy_chain_18_2_3), + .o_features_2_3(daisy_chain_19_2_3), + .i_features_2_4(daisy_chain_18_2_4), + .o_features_2_4(daisy_chain_19_2_4), + .i_features_2_5(daisy_chain_18_2_5), + .o_features_2_5(daisy_chain_19_2_5), + .i_features_3_0(daisy_chain_18_3_0), + .o_features_3_0(daisy_chain_19_3_0), + .i_features_3_1(daisy_chain_18_3_1), + .o_features_3_1(daisy_chain_19_3_1), + .i_features_3_2(daisy_chain_18_3_2), + .o_features_3_2(daisy_chain_19_3_2), + .i_features_3_3(daisy_chain_18_3_3), + .o_features_3_3(daisy_chain_19_3_3), + .i_features_3_4(daisy_chain_18_3_4), + .o_features_3_4(daisy_chain_19_3_4), + .i_features_3_5(daisy_chain_18_3_5), + .o_features_3_5(daisy_chain_19_3_5), + .i_features_4_0(daisy_chain_18_4_0), + .o_features_4_0(daisy_chain_19_4_0), + .i_features_4_1(daisy_chain_18_4_1), + .o_features_4_1(daisy_chain_19_4_1), + .i_features_4_2(daisy_chain_18_4_2), + .o_features_4_2(daisy_chain_19_4_2), + .i_features_4_3(daisy_chain_18_4_3), + .o_features_4_3(daisy_chain_19_4_3), + .i_features_4_4(daisy_chain_18_4_4), + .o_features_4_4(daisy_chain_19_4_4), + .i_features_4_5(daisy_chain_18_4_5), + .o_features_4_5(daisy_chain_19_4_5), + .i_features_5_0(daisy_chain_18_5_0), + .o_features_5_0(daisy_chain_19_5_0), + .i_features_5_1(daisy_chain_18_5_1), + .o_features_5_1(daisy_chain_19_5_1), + .i_features_5_2(daisy_chain_18_5_2), + .o_features_5_2(daisy_chain_19_5_2), + .i_features_5_3(daisy_chain_18_5_3), + .o_features_5_3(daisy_chain_19_5_3), + .i_features_5_4(daisy_chain_18_5_4), + .o_features_5_4(daisy_chain_19_5_4), + .i_features_5_5(daisy_chain_18_5_5), + .o_features_5_5(daisy_chain_19_5_5), + .i_features_6_0(daisy_chain_18_6_0), + .o_features_6_0(daisy_chain_19_6_0), + .i_features_6_1(daisy_chain_18_6_1), + .o_features_6_1(daisy_chain_19_6_1), + .i_features_6_2(daisy_chain_18_6_2), + .o_features_6_2(daisy_chain_19_6_2), + .i_features_6_3(daisy_chain_18_6_3), + .o_features_6_3(daisy_chain_19_6_3), + .i_features_6_4(daisy_chain_18_6_4), + .o_features_6_4(daisy_chain_19_6_4), + .i_features_6_5(daisy_chain_18_6_5), + .o_features_6_5(daisy_chain_19_6_5), + .i_features_7_0(daisy_chain_18_7_0), + .o_features_7_0(daisy_chain_19_7_0), + .i_features_7_1(daisy_chain_18_7_1), + .o_features_7_1(daisy_chain_19_7_1), + .i_features_7_2(daisy_chain_18_7_2), + .o_features_7_2(daisy_chain_19_7_2), + .i_features_7_3(daisy_chain_18_7_3), + .o_features_7_3(daisy_chain_19_7_3), + .i_features_7_4(daisy_chain_18_7_4), + .o_features_7_4(daisy_chain_19_7_4), + .i_features_7_5(daisy_chain_18_7_5), + .o_features_7_5(daisy_chain_19_7_5), + .o_result_0(PE_output_19_0), + .o_result_1(PE_output_19_1), + .o_result_2(PE_output_19_2), + .o_result_3(PE_output_19_3), + .o_result_4(PE_output_19_4), + .o_result_5(PE_output_19_5), + .o_valid(PE_valid_19), + .o_next_reset(PE_next_reset_19), + .o_next_valid(PE_next_valid_19) +); + +processing_element processing_element_inst_20 ( + .clk(clk), + .i_reset(PE_next_reset_19), + .i_valid(PE_next_valid_19), + .i_features_0_0(daisy_chain_19_0_0), + .o_features_0_0(daisy_chain_20_0_0), + .i_features_0_1(daisy_chain_19_0_1), + .o_features_0_1(daisy_chain_20_0_1), + .i_features_0_2(daisy_chain_19_0_2), + .o_features_0_2(daisy_chain_20_0_2), + .i_features_0_3(daisy_chain_19_0_3), + .o_features_0_3(daisy_chain_20_0_3), + .i_features_0_4(daisy_chain_19_0_4), + .o_features_0_4(daisy_chain_20_0_4), + .i_features_0_5(daisy_chain_19_0_5), + .o_features_0_5(daisy_chain_20_0_5), + .i_features_1_0(daisy_chain_19_1_0), + .o_features_1_0(daisy_chain_20_1_0), + .i_features_1_1(daisy_chain_19_1_1), + .o_features_1_1(daisy_chain_20_1_1), + .i_features_1_2(daisy_chain_19_1_2), + .o_features_1_2(daisy_chain_20_1_2), + .i_features_1_3(daisy_chain_19_1_3), + .o_features_1_3(daisy_chain_20_1_3), + .i_features_1_4(daisy_chain_19_1_4), + .o_features_1_4(daisy_chain_20_1_4), + .i_features_1_5(daisy_chain_19_1_5), + .o_features_1_5(daisy_chain_20_1_5), + .i_features_2_0(daisy_chain_19_2_0), + .o_features_2_0(daisy_chain_20_2_0), + .i_features_2_1(daisy_chain_19_2_1), + .o_features_2_1(daisy_chain_20_2_1), + .i_features_2_2(daisy_chain_19_2_2), + .o_features_2_2(daisy_chain_20_2_2), + .i_features_2_3(daisy_chain_19_2_3), + .o_features_2_3(daisy_chain_20_2_3), + .i_features_2_4(daisy_chain_19_2_4), + .o_features_2_4(daisy_chain_20_2_4), + .i_features_2_5(daisy_chain_19_2_5), + .o_features_2_5(daisy_chain_20_2_5), + .i_features_3_0(daisy_chain_19_3_0), + .o_features_3_0(daisy_chain_20_3_0), + .i_features_3_1(daisy_chain_19_3_1), + .o_features_3_1(daisy_chain_20_3_1), + .i_features_3_2(daisy_chain_19_3_2), + .o_features_3_2(daisy_chain_20_3_2), + .i_features_3_3(daisy_chain_19_3_3), + .o_features_3_3(daisy_chain_20_3_3), + .i_features_3_4(daisy_chain_19_3_4), + .o_features_3_4(daisy_chain_20_3_4), + .i_features_3_5(daisy_chain_19_3_5), + .o_features_3_5(daisy_chain_20_3_5), + .i_features_4_0(daisy_chain_19_4_0), + .o_features_4_0(daisy_chain_20_4_0), + .i_features_4_1(daisy_chain_19_4_1), + .o_features_4_1(daisy_chain_20_4_1), + .i_features_4_2(daisy_chain_19_4_2), + .o_features_4_2(daisy_chain_20_4_2), + .i_features_4_3(daisy_chain_19_4_3), + .o_features_4_3(daisy_chain_20_4_3), + .i_features_4_4(daisy_chain_19_4_4), + .o_features_4_4(daisy_chain_20_4_4), + .i_features_4_5(daisy_chain_19_4_5), + .o_features_4_5(daisy_chain_20_4_5), + .i_features_5_0(daisy_chain_19_5_0), + .o_features_5_0(daisy_chain_20_5_0), + .i_features_5_1(daisy_chain_19_5_1), + .o_features_5_1(daisy_chain_20_5_1), + .i_features_5_2(daisy_chain_19_5_2), + .o_features_5_2(daisy_chain_20_5_2), + .i_features_5_3(daisy_chain_19_5_3), + .o_features_5_3(daisy_chain_20_5_3), + .i_features_5_4(daisy_chain_19_5_4), + .o_features_5_4(daisy_chain_20_5_4), + .i_features_5_5(daisy_chain_19_5_5), + .o_features_5_5(daisy_chain_20_5_5), + .i_features_6_0(daisy_chain_19_6_0), + .o_features_6_0(daisy_chain_20_6_0), + .i_features_6_1(daisy_chain_19_6_1), + .o_features_6_1(daisy_chain_20_6_1), + .i_features_6_2(daisy_chain_19_6_2), + .o_features_6_2(daisy_chain_20_6_2), + .i_features_6_3(daisy_chain_19_6_3), + .o_features_6_3(daisy_chain_20_6_3), + .i_features_6_4(daisy_chain_19_6_4), + .o_features_6_4(daisy_chain_20_6_4), + .i_features_6_5(daisy_chain_19_6_5), + .o_features_6_5(daisy_chain_20_6_5), + .i_features_7_0(daisy_chain_19_7_0), + .o_features_7_0(daisy_chain_20_7_0), + .i_features_7_1(daisy_chain_19_7_1), + .o_features_7_1(daisy_chain_20_7_1), + .i_features_7_2(daisy_chain_19_7_2), + .o_features_7_2(daisy_chain_20_7_2), + .i_features_7_3(daisy_chain_19_7_3), + .o_features_7_3(daisy_chain_20_7_3), + .i_features_7_4(daisy_chain_19_7_4), + .o_features_7_4(daisy_chain_20_7_4), + .i_features_7_5(daisy_chain_19_7_5), + .o_features_7_5(daisy_chain_20_7_5), + .o_result_0(PE_output_20_0), + .o_result_1(PE_output_20_1), + .o_result_2(PE_output_20_2), + .o_result_3(PE_output_20_3), + .o_result_4(PE_output_20_4), + .o_result_5(PE_output_20_5), + .o_valid(PE_valid_20), + .o_next_reset(PE_next_reset_20), + .o_next_valid(PE_next_valid_20) +); + +processing_element processing_element_inst_21 ( + .clk(clk), + .i_reset(PE_next_reset_20), + .i_valid(PE_next_valid_20), + .i_features_0_0(daisy_chain_20_0_0), + .o_features_0_0(daisy_chain_21_0_0), + .i_features_0_1(daisy_chain_20_0_1), + .o_features_0_1(daisy_chain_21_0_1), + .i_features_0_2(daisy_chain_20_0_2), + .o_features_0_2(daisy_chain_21_0_2), + .i_features_0_3(daisy_chain_20_0_3), + .o_features_0_3(daisy_chain_21_0_3), + .i_features_0_4(daisy_chain_20_0_4), + .o_features_0_4(daisy_chain_21_0_4), + .i_features_0_5(daisy_chain_20_0_5), + .o_features_0_5(daisy_chain_21_0_5), + .i_features_1_0(daisy_chain_20_1_0), + .o_features_1_0(daisy_chain_21_1_0), + .i_features_1_1(daisy_chain_20_1_1), + .o_features_1_1(daisy_chain_21_1_1), + .i_features_1_2(daisy_chain_20_1_2), + .o_features_1_2(daisy_chain_21_1_2), + .i_features_1_3(daisy_chain_20_1_3), + .o_features_1_3(daisy_chain_21_1_3), + .i_features_1_4(daisy_chain_20_1_4), + .o_features_1_4(daisy_chain_21_1_4), + .i_features_1_5(daisy_chain_20_1_5), + .o_features_1_5(daisy_chain_21_1_5), + .i_features_2_0(daisy_chain_20_2_0), + .o_features_2_0(daisy_chain_21_2_0), + .i_features_2_1(daisy_chain_20_2_1), + .o_features_2_1(daisy_chain_21_2_1), + .i_features_2_2(daisy_chain_20_2_2), + .o_features_2_2(daisy_chain_21_2_2), + .i_features_2_3(daisy_chain_20_2_3), + .o_features_2_3(daisy_chain_21_2_3), + .i_features_2_4(daisy_chain_20_2_4), + .o_features_2_4(daisy_chain_21_2_4), + .i_features_2_5(daisy_chain_20_2_5), + .o_features_2_5(daisy_chain_21_2_5), + .i_features_3_0(daisy_chain_20_3_0), + .o_features_3_0(daisy_chain_21_3_0), + .i_features_3_1(daisy_chain_20_3_1), + .o_features_3_1(daisy_chain_21_3_1), + .i_features_3_2(daisy_chain_20_3_2), + .o_features_3_2(daisy_chain_21_3_2), + .i_features_3_3(daisy_chain_20_3_3), + .o_features_3_3(daisy_chain_21_3_3), + .i_features_3_4(daisy_chain_20_3_4), + .o_features_3_4(daisy_chain_21_3_4), + .i_features_3_5(daisy_chain_20_3_5), + .o_features_3_5(daisy_chain_21_3_5), + .i_features_4_0(daisy_chain_20_4_0), + .o_features_4_0(daisy_chain_21_4_0), + .i_features_4_1(daisy_chain_20_4_1), + .o_features_4_1(daisy_chain_21_4_1), + .i_features_4_2(daisy_chain_20_4_2), + .o_features_4_2(daisy_chain_21_4_2), + .i_features_4_3(daisy_chain_20_4_3), + .o_features_4_3(daisy_chain_21_4_3), + .i_features_4_4(daisy_chain_20_4_4), + .o_features_4_4(daisy_chain_21_4_4), + .i_features_4_5(daisy_chain_20_4_5), + .o_features_4_5(daisy_chain_21_4_5), + .i_features_5_0(daisy_chain_20_5_0), + .o_features_5_0(daisy_chain_21_5_0), + .i_features_5_1(daisy_chain_20_5_1), + .o_features_5_1(daisy_chain_21_5_1), + .i_features_5_2(daisy_chain_20_5_2), + .o_features_5_2(daisy_chain_21_5_2), + .i_features_5_3(daisy_chain_20_5_3), + .o_features_5_3(daisy_chain_21_5_3), + .i_features_5_4(daisy_chain_20_5_4), + .o_features_5_4(daisy_chain_21_5_4), + .i_features_5_5(daisy_chain_20_5_5), + .o_features_5_5(daisy_chain_21_5_5), + .i_features_6_0(daisy_chain_20_6_0), + .o_features_6_0(daisy_chain_21_6_0), + .i_features_6_1(daisy_chain_20_6_1), + .o_features_6_1(daisy_chain_21_6_1), + .i_features_6_2(daisy_chain_20_6_2), + .o_features_6_2(daisy_chain_21_6_2), + .i_features_6_3(daisy_chain_20_6_3), + .o_features_6_3(daisy_chain_21_6_3), + .i_features_6_4(daisy_chain_20_6_4), + .o_features_6_4(daisy_chain_21_6_4), + .i_features_6_5(daisy_chain_20_6_5), + .o_features_6_5(daisy_chain_21_6_5), + .i_features_7_0(daisy_chain_20_7_0), + .o_features_7_0(daisy_chain_21_7_0), + .i_features_7_1(daisy_chain_20_7_1), + .o_features_7_1(daisy_chain_21_7_1), + .i_features_7_2(daisy_chain_20_7_2), + .o_features_7_2(daisy_chain_21_7_2), + .i_features_7_3(daisy_chain_20_7_3), + .o_features_7_3(daisy_chain_21_7_3), + .i_features_7_4(daisy_chain_20_7_4), + .o_features_7_4(daisy_chain_21_7_4), + .i_features_7_5(daisy_chain_20_7_5), + .o_features_7_5(daisy_chain_21_7_5), + .o_result_0(PE_output_21_0), + .o_result_1(PE_output_21_1), + .o_result_2(PE_output_21_2), + .o_result_3(PE_output_21_3), + .o_result_4(PE_output_21_4), + .o_result_5(PE_output_21_5), + .o_valid(PE_valid_21), + .o_next_reset(PE_next_reset_21), + .o_next_valid(PE_next_valid_21) +); + +processing_element processing_element_inst_22 ( + .clk(clk), + .i_reset(PE_next_reset_21), + .i_valid(PE_next_valid_21), + .i_features_0_0(daisy_chain_21_0_0), + .o_features_0_0(daisy_chain_22_0_0), + .i_features_0_1(daisy_chain_21_0_1), + .o_features_0_1(daisy_chain_22_0_1), + .i_features_0_2(daisy_chain_21_0_2), + .o_features_0_2(daisy_chain_22_0_2), + .i_features_0_3(daisy_chain_21_0_3), + .o_features_0_3(daisy_chain_22_0_3), + .i_features_0_4(daisy_chain_21_0_4), + .o_features_0_4(daisy_chain_22_0_4), + .i_features_0_5(daisy_chain_21_0_5), + .o_features_0_5(daisy_chain_22_0_5), + .i_features_1_0(daisy_chain_21_1_0), + .o_features_1_0(daisy_chain_22_1_0), + .i_features_1_1(daisy_chain_21_1_1), + .o_features_1_1(daisy_chain_22_1_1), + .i_features_1_2(daisy_chain_21_1_2), + .o_features_1_2(daisy_chain_22_1_2), + .i_features_1_3(daisy_chain_21_1_3), + .o_features_1_3(daisy_chain_22_1_3), + .i_features_1_4(daisy_chain_21_1_4), + .o_features_1_4(daisy_chain_22_1_4), + .i_features_1_5(daisy_chain_21_1_5), + .o_features_1_5(daisy_chain_22_1_5), + .i_features_2_0(daisy_chain_21_2_0), + .o_features_2_0(daisy_chain_22_2_0), + .i_features_2_1(daisy_chain_21_2_1), + .o_features_2_1(daisy_chain_22_2_1), + .i_features_2_2(daisy_chain_21_2_2), + .o_features_2_2(daisy_chain_22_2_2), + .i_features_2_3(daisy_chain_21_2_3), + .o_features_2_3(daisy_chain_22_2_3), + .i_features_2_4(daisy_chain_21_2_4), + .o_features_2_4(daisy_chain_22_2_4), + .i_features_2_5(daisy_chain_21_2_5), + .o_features_2_5(daisy_chain_22_2_5), + .i_features_3_0(daisy_chain_21_3_0), + .o_features_3_0(daisy_chain_22_3_0), + .i_features_3_1(daisy_chain_21_3_1), + .o_features_3_1(daisy_chain_22_3_1), + .i_features_3_2(daisy_chain_21_3_2), + .o_features_3_2(daisy_chain_22_3_2), + .i_features_3_3(daisy_chain_21_3_3), + .o_features_3_3(daisy_chain_22_3_3), + .i_features_3_4(daisy_chain_21_3_4), + .o_features_3_4(daisy_chain_22_3_4), + .i_features_3_5(daisy_chain_21_3_5), + .o_features_3_5(daisy_chain_22_3_5), + .i_features_4_0(daisy_chain_21_4_0), + .o_features_4_0(daisy_chain_22_4_0), + .i_features_4_1(daisy_chain_21_4_1), + .o_features_4_1(daisy_chain_22_4_1), + .i_features_4_2(daisy_chain_21_4_2), + .o_features_4_2(daisy_chain_22_4_2), + .i_features_4_3(daisy_chain_21_4_3), + .o_features_4_3(daisy_chain_22_4_3), + .i_features_4_4(daisy_chain_21_4_4), + .o_features_4_4(daisy_chain_22_4_4), + .i_features_4_5(daisy_chain_21_4_5), + .o_features_4_5(daisy_chain_22_4_5), + .i_features_5_0(daisy_chain_21_5_0), + .o_features_5_0(daisy_chain_22_5_0), + .i_features_5_1(daisy_chain_21_5_1), + .o_features_5_1(daisy_chain_22_5_1), + .i_features_5_2(daisy_chain_21_5_2), + .o_features_5_2(daisy_chain_22_5_2), + .i_features_5_3(daisy_chain_21_5_3), + .o_features_5_3(daisy_chain_22_5_3), + .i_features_5_4(daisy_chain_21_5_4), + .o_features_5_4(daisy_chain_22_5_4), + .i_features_5_5(daisy_chain_21_5_5), + .o_features_5_5(daisy_chain_22_5_5), + .i_features_6_0(daisy_chain_21_6_0), + .o_features_6_0(daisy_chain_22_6_0), + .i_features_6_1(daisy_chain_21_6_1), + .o_features_6_1(daisy_chain_22_6_1), + .i_features_6_2(daisy_chain_21_6_2), + .o_features_6_2(daisy_chain_22_6_2), + .i_features_6_3(daisy_chain_21_6_3), + .o_features_6_3(daisy_chain_22_6_3), + .i_features_6_4(daisy_chain_21_6_4), + .o_features_6_4(daisy_chain_22_6_4), + .i_features_6_5(daisy_chain_21_6_5), + .o_features_6_5(daisy_chain_22_6_5), + .i_features_7_0(daisy_chain_21_7_0), + .o_features_7_0(daisy_chain_22_7_0), + .i_features_7_1(daisy_chain_21_7_1), + .o_features_7_1(daisy_chain_22_7_1), + .i_features_7_2(daisy_chain_21_7_2), + .o_features_7_2(daisy_chain_22_7_2), + .i_features_7_3(daisy_chain_21_7_3), + .o_features_7_3(daisy_chain_22_7_3), + .i_features_7_4(daisy_chain_21_7_4), + .o_features_7_4(daisy_chain_22_7_4), + .i_features_7_5(daisy_chain_21_7_5), + .o_features_7_5(daisy_chain_22_7_5), + .o_result_0(PE_output_22_0), + .o_result_1(PE_output_22_1), + .o_result_2(PE_output_22_2), + .o_result_3(PE_output_22_3), + .o_result_4(PE_output_22_4), + .o_result_5(PE_output_22_5), + .o_valid(PE_valid_22), + .o_next_reset(PE_next_reset_22), + .o_next_valid(PE_next_valid_22) +); + +processing_element processing_element_inst_23 ( + .clk(clk), + .i_reset(PE_next_reset_22), + .i_valid(PE_next_valid_22), + .i_features_0_0(daisy_chain_22_0_0), + .o_features_0_0(daisy_chain_23_0_0), + .i_features_0_1(daisy_chain_22_0_1), + .o_features_0_1(daisy_chain_23_0_1), + .i_features_0_2(daisy_chain_22_0_2), + .o_features_0_2(daisy_chain_23_0_2), + .i_features_0_3(daisy_chain_22_0_3), + .o_features_0_3(daisy_chain_23_0_3), + .i_features_0_4(daisy_chain_22_0_4), + .o_features_0_4(daisy_chain_23_0_4), + .i_features_0_5(daisy_chain_22_0_5), + .o_features_0_5(daisy_chain_23_0_5), + .i_features_1_0(daisy_chain_22_1_0), + .o_features_1_0(daisy_chain_23_1_0), + .i_features_1_1(daisy_chain_22_1_1), + .o_features_1_1(daisy_chain_23_1_1), + .i_features_1_2(daisy_chain_22_1_2), + .o_features_1_2(daisy_chain_23_1_2), + .i_features_1_3(daisy_chain_22_1_3), + .o_features_1_3(daisy_chain_23_1_3), + .i_features_1_4(daisy_chain_22_1_4), + .o_features_1_4(daisy_chain_23_1_4), + .i_features_1_5(daisy_chain_22_1_5), + .o_features_1_5(daisy_chain_23_1_5), + .i_features_2_0(daisy_chain_22_2_0), + .o_features_2_0(daisy_chain_23_2_0), + .i_features_2_1(daisy_chain_22_2_1), + .o_features_2_1(daisy_chain_23_2_1), + .i_features_2_2(daisy_chain_22_2_2), + .o_features_2_2(daisy_chain_23_2_2), + .i_features_2_3(daisy_chain_22_2_3), + .o_features_2_3(daisy_chain_23_2_3), + .i_features_2_4(daisy_chain_22_2_4), + .o_features_2_4(daisy_chain_23_2_4), + .i_features_2_5(daisy_chain_22_2_5), + .o_features_2_5(daisy_chain_23_2_5), + .i_features_3_0(daisy_chain_22_3_0), + .o_features_3_0(daisy_chain_23_3_0), + .i_features_3_1(daisy_chain_22_3_1), + .o_features_3_1(daisy_chain_23_3_1), + .i_features_3_2(daisy_chain_22_3_2), + .o_features_3_2(daisy_chain_23_3_2), + .i_features_3_3(daisy_chain_22_3_3), + .o_features_3_3(daisy_chain_23_3_3), + .i_features_3_4(daisy_chain_22_3_4), + .o_features_3_4(daisy_chain_23_3_4), + .i_features_3_5(daisy_chain_22_3_5), + .o_features_3_5(daisy_chain_23_3_5), + .i_features_4_0(daisy_chain_22_4_0), + .o_features_4_0(daisy_chain_23_4_0), + .i_features_4_1(daisy_chain_22_4_1), + .o_features_4_1(daisy_chain_23_4_1), + .i_features_4_2(daisy_chain_22_4_2), + .o_features_4_2(daisy_chain_23_4_2), + .i_features_4_3(daisy_chain_22_4_3), + .o_features_4_3(daisy_chain_23_4_3), + .i_features_4_4(daisy_chain_22_4_4), + .o_features_4_4(daisy_chain_23_4_4), + .i_features_4_5(daisy_chain_22_4_5), + .o_features_4_5(daisy_chain_23_4_5), + .i_features_5_0(daisy_chain_22_5_0), + .o_features_5_0(daisy_chain_23_5_0), + .i_features_5_1(daisy_chain_22_5_1), + .o_features_5_1(daisy_chain_23_5_1), + .i_features_5_2(daisy_chain_22_5_2), + .o_features_5_2(daisy_chain_23_5_2), + .i_features_5_3(daisy_chain_22_5_3), + .o_features_5_3(daisy_chain_23_5_3), + .i_features_5_4(daisy_chain_22_5_4), + .o_features_5_4(daisy_chain_23_5_4), + .i_features_5_5(daisy_chain_22_5_5), + .o_features_5_5(daisy_chain_23_5_5), + .i_features_6_0(daisy_chain_22_6_0), + .o_features_6_0(daisy_chain_23_6_0), + .i_features_6_1(daisy_chain_22_6_1), + .o_features_6_1(daisy_chain_23_6_1), + .i_features_6_2(daisy_chain_22_6_2), + .o_features_6_2(daisy_chain_23_6_2), + .i_features_6_3(daisy_chain_22_6_3), + .o_features_6_3(daisy_chain_23_6_3), + .i_features_6_4(daisy_chain_22_6_4), + .o_features_6_4(daisy_chain_23_6_4), + .i_features_6_5(daisy_chain_22_6_5), + .o_features_6_5(daisy_chain_23_6_5), + .i_features_7_0(daisy_chain_22_7_0), + .o_features_7_0(daisy_chain_23_7_0), + .i_features_7_1(daisy_chain_22_7_1), + .o_features_7_1(daisy_chain_23_7_1), + .i_features_7_2(daisy_chain_22_7_2), + .o_features_7_2(daisy_chain_23_7_2), + .i_features_7_3(daisy_chain_22_7_3), + .o_features_7_3(daisy_chain_23_7_3), + .i_features_7_4(daisy_chain_22_7_4), + .o_features_7_4(daisy_chain_23_7_4), + .i_features_7_5(daisy_chain_22_7_5), + .o_features_7_5(daisy_chain_23_7_5), + .o_result_0(PE_output_23_0), + .o_result_1(PE_output_23_1), + .o_result_2(PE_output_23_2), + .o_result_3(PE_output_23_3), + .o_result_4(PE_output_23_4), + .o_result_5(PE_output_23_5), + .o_valid(PE_valid_23), + .o_next_reset(PE_next_reset_23), + .o_next_valid(PE_next_valid_23) +); + +processing_element processing_element_inst_24 ( + .clk(clk), + .i_reset(PE_next_reset_23), + .i_valid(PE_next_valid_23), + .i_features_0_0(daisy_chain_23_0_0), + .o_features_0_0(daisy_chain_24_0_0), + .i_features_0_1(daisy_chain_23_0_1), + .o_features_0_1(daisy_chain_24_0_1), + .i_features_0_2(daisy_chain_23_0_2), + .o_features_0_2(daisy_chain_24_0_2), + .i_features_0_3(daisy_chain_23_0_3), + .o_features_0_3(daisy_chain_24_0_3), + .i_features_0_4(daisy_chain_23_0_4), + .o_features_0_4(daisy_chain_24_0_4), + .i_features_0_5(daisy_chain_23_0_5), + .o_features_0_5(daisy_chain_24_0_5), + .i_features_1_0(daisy_chain_23_1_0), + .o_features_1_0(daisy_chain_24_1_0), + .i_features_1_1(daisy_chain_23_1_1), + .o_features_1_1(daisy_chain_24_1_1), + .i_features_1_2(daisy_chain_23_1_2), + .o_features_1_2(daisy_chain_24_1_2), + .i_features_1_3(daisy_chain_23_1_3), + .o_features_1_3(daisy_chain_24_1_3), + .i_features_1_4(daisy_chain_23_1_4), + .o_features_1_4(daisy_chain_24_1_4), + .i_features_1_5(daisy_chain_23_1_5), + .o_features_1_5(daisy_chain_24_1_5), + .i_features_2_0(daisy_chain_23_2_0), + .o_features_2_0(daisy_chain_24_2_0), + .i_features_2_1(daisy_chain_23_2_1), + .o_features_2_1(daisy_chain_24_2_1), + .i_features_2_2(daisy_chain_23_2_2), + .o_features_2_2(daisy_chain_24_2_2), + .i_features_2_3(daisy_chain_23_2_3), + .o_features_2_3(daisy_chain_24_2_3), + .i_features_2_4(daisy_chain_23_2_4), + .o_features_2_4(daisy_chain_24_2_4), + .i_features_2_5(daisy_chain_23_2_5), + .o_features_2_5(daisy_chain_24_2_5), + .i_features_3_0(daisy_chain_23_3_0), + .o_features_3_0(daisy_chain_24_3_0), + .i_features_3_1(daisy_chain_23_3_1), + .o_features_3_1(daisy_chain_24_3_1), + .i_features_3_2(daisy_chain_23_3_2), + .o_features_3_2(daisy_chain_24_3_2), + .i_features_3_3(daisy_chain_23_3_3), + .o_features_3_3(daisy_chain_24_3_3), + .i_features_3_4(daisy_chain_23_3_4), + .o_features_3_4(daisy_chain_24_3_4), + .i_features_3_5(daisy_chain_23_3_5), + .o_features_3_5(daisy_chain_24_3_5), + .i_features_4_0(daisy_chain_23_4_0), + .o_features_4_0(daisy_chain_24_4_0), + .i_features_4_1(daisy_chain_23_4_1), + .o_features_4_1(daisy_chain_24_4_1), + .i_features_4_2(daisy_chain_23_4_2), + .o_features_4_2(daisy_chain_24_4_2), + .i_features_4_3(daisy_chain_23_4_3), + .o_features_4_3(daisy_chain_24_4_3), + .i_features_4_4(daisy_chain_23_4_4), + .o_features_4_4(daisy_chain_24_4_4), + .i_features_4_5(daisy_chain_23_4_5), + .o_features_4_5(daisy_chain_24_4_5), + .i_features_5_0(daisy_chain_23_5_0), + .o_features_5_0(daisy_chain_24_5_0), + .i_features_5_1(daisy_chain_23_5_1), + .o_features_5_1(daisy_chain_24_5_1), + .i_features_5_2(daisy_chain_23_5_2), + .o_features_5_2(daisy_chain_24_5_2), + .i_features_5_3(daisy_chain_23_5_3), + .o_features_5_3(daisy_chain_24_5_3), + .i_features_5_4(daisy_chain_23_5_4), + .o_features_5_4(daisy_chain_24_5_4), + .i_features_5_5(daisy_chain_23_5_5), + .o_features_5_5(daisy_chain_24_5_5), + .i_features_6_0(daisy_chain_23_6_0), + .o_features_6_0(daisy_chain_24_6_0), + .i_features_6_1(daisy_chain_23_6_1), + .o_features_6_1(daisy_chain_24_6_1), + .i_features_6_2(daisy_chain_23_6_2), + .o_features_6_2(daisy_chain_24_6_2), + .i_features_6_3(daisy_chain_23_6_3), + .o_features_6_3(daisy_chain_24_6_3), + .i_features_6_4(daisy_chain_23_6_4), + .o_features_6_4(daisy_chain_24_6_4), + .i_features_6_5(daisy_chain_23_6_5), + .o_features_6_5(daisy_chain_24_6_5), + .i_features_7_0(daisy_chain_23_7_0), + .o_features_7_0(daisy_chain_24_7_0), + .i_features_7_1(daisy_chain_23_7_1), + .o_features_7_1(daisy_chain_24_7_1), + .i_features_7_2(daisy_chain_23_7_2), + .o_features_7_2(daisy_chain_24_7_2), + .i_features_7_3(daisy_chain_23_7_3), + .o_features_7_3(daisy_chain_24_7_3), + .i_features_7_4(daisy_chain_23_7_4), + .o_features_7_4(daisy_chain_24_7_4), + .i_features_7_5(daisy_chain_23_7_5), + .o_features_7_5(daisy_chain_24_7_5), + .o_result_0(PE_output_24_0), + .o_result_1(PE_output_24_1), + .o_result_2(PE_output_24_2), + .o_result_3(PE_output_24_3), + .o_result_4(PE_output_24_4), + .o_result_5(PE_output_24_5), + .o_valid(PE_valid_24), + .o_next_reset(PE_next_reset_24), + .o_next_valid(PE_next_valid_24) +); + +processing_element processing_element_inst_25 ( + .clk(clk), + .i_reset(PE_next_reset_24), + .i_valid(PE_next_valid_24), + .i_features_0_0(daisy_chain_24_0_0), + .o_features_0_0(daisy_chain_25_0_0), + .i_features_0_1(daisy_chain_24_0_1), + .o_features_0_1(daisy_chain_25_0_1), + .i_features_0_2(daisy_chain_24_0_2), + .o_features_0_2(daisy_chain_25_0_2), + .i_features_0_3(daisy_chain_24_0_3), + .o_features_0_3(daisy_chain_25_0_3), + .i_features_0_4(daisy_chain_24_0_4), + .o_features_0_4(daisy_chain_25_0_4), + .i_features_0_5(daisy_chain_24_0_5), + .o_features_0_5(daisy_chain_25_0_5), + .i_features_1_0(daisy_chain_24_1_0), + .o_features_1_0(daisy_chain_25_1_0), + .i_features_1_1(daisy_chain_24_1_1), + .o_features_1_1(daisy_chain_25_1_1), + .i_features_1_2(daisy_chain_24_1_2), + .o_features_1_2(daisy_chain_25_1_2), + .i_features_1_3(daisy_chain_24_1_3), + .o_features_1_3(daisy_chain_25_1_3), + .i_features_1_4(daisy_chain_24_1_4), + .o_features_1_4(daisy_chain_25_1_4), + .i_features_1_5(daisy_chain_24_1_5), + .o_features_1_5(daisy_chain_25_1_5), + .i_features_2_0(daisy_chain_24_2_0), + .o_features_2_0(daisy_chain_25_2_0), + .i_features_2_1(daisy_chain_24_2_1), + .o_features_2_1(daisy_chain_25_2_1), + .i_features_2_2(daisy_chain_24_2_2), + .o_features_2_2(daisy_chain_25_2_2), + .i_features_2_3(daisy_chain_24_2_3), + .o_features_2_3(daisy_chain_25_2_3), + .i_features_2_4(daisy_chain_24_2_4), + .o_features_2_4(daisy_chain_25_2_4), + .i_features_2_5(daisy_chain_24_2_5), + .o_features_2_5(daisy_chain_25_2_5), + .i_features_3_0(daisy_chain_24_3_0), + .o_features_3_0(daisy_chain_25_3_0), + .i_features_3_1(daisy_chain_24_3_1), + .o_features_3_1(daisy_chain_25_3_1), + .i_features_3_2(daisy_chain_24_3_2), + .o_features_3_2(daisy_chain_25_3_2), + .i_features_3_3(daisy_chain_24_3_3), + .o_features_3_3(daisy_chain_25_3_3), + .i_features_3_4(daisy_chain_24_3_4), + .o_features_3_4(daisy_chain_25_3_4), + .i_features_3_5(daisy_chain_24_3_5), + .o_features_3_5(daisy_chain_25_3_5), + .i_features_4_0(daisy_chain_24_4_0), + .o_features_4_0(daisy_chain_25_4_0), + .i_features_4_1(daisy_chain_24_4_1), + .o_features_4_1(daisy_chain_25_4_1), + .i_features_4_2(daisy_chain_24_4_2), + .o_features_4_2(daisy_chain_25_4_2), + .i_features_4_3(daisy_chain_24_4_3), + .o_features_4_3(daisy_chain_25_4_3), + .i_features_4_4(daisy_chain_24_4_4), + .o_features_4_4(daisy_chain_25_4_4), + .i_features_4_5(daisy_chain_24_4_5), + .o_features_4_5(daisy_chain_25_4_5), + .i_features_5_0(daisy_chain_24_5_0), + .o_features_5_0(daisy_chain_25_5_0), + .i_features_5_1(daisy_chain_24_5_1), + .o_features_5_1(daisy_chain_25_5_1), + .i_features_5_2(daisy_chain_24_5_2), + .o_features_5_2(daisy_chain_25_5_2), + .i_features_5_3(daisy_chain_24_5_3), + .o_features_5_3(daisy_chain_25_5_3), + .i_features_5_4(daisy_chain_24_5_4), + .o_features_5_4(daisy_chain_25_5_4), + .i_features_5_5(daisy_chain_24_5_5), + .o_features_5_5(daisy_chain_25_5_5), + .i_features_6_0(daisy_chain_24_6_0), + .o_features_6_0(daisy_chain_25_6_0), + .i_features_6_1(daisy_chain_24_6_1), + .o_features_6_1(daisy_chain_25_6_1), + .i_features_6_2(daisy_chain_24_6_2), + .o_features_6_2(daisy_chain_25_6_2), + .i_features_6_3(daisy_chain_24_6_3), + .o_features_6_3(daisy_chain_25_6_3), + .i_features_6_4(daisy_chain_24_6_4), + .o_features_6_4(daisy_chain_25_6_4), + .i_features_6_5(daisy_chain_24_6_5), + .o_features_6_5(daisy_chain_25_6_5), + .i_features_7_0(daisy_chain_24_7_0), + .o_features_7_0(daisy_chain_25_7_0), + .i_features_7_1(daisy_chain_24_7_1), + .o_features_7_1(daisy_chain_25_7_1), + .i_features_7_2(daisy_chain_24_7_2), + .o_features_7_2(daisy_chain_25_7_2), + .i_features_7_3(daisy_chain_24_7_3), + .o_features_7_3(daisy_chain_25_7_3), + .i_features_7_4(daisy_chain_24_7_4), + .o_features_7_4(daisy_chain_25_7_4), + .i_features_7_5(daisy_chain_24_7_5), + .o_features_7_5(daisy_chain_25_7_5), + .o_result_0(PE_output_25_0), + .o_result_1(PE_output_25_1), + .o_result_2(PE_output_25_2), + .o_result_3(PE_output_25_3), + .o_result_4(PE_output_25_4), + .o_result_5(PE_output_25_5), + .o_valid(PE_valid_25), + .o_next_reset(PE_next_reset_25), + .o_next_valid(PE_next_valid_25) +); + +processing_element processing_element_inst_26 ( + .clk(clk), + .i_reset(PE_next_reset_25), + .i_valid(PE_next_valid_25), + .i_features_0_0(daisy_chain_25_0_0), + .o_features_0_0(daisy_chain_26_0_0), + .i_features_0_1(daisy_chain_25_0_1), + .o_features_0_1(daisy_chain_26_0_1), + .i_features_0_2(daisy_chain_25_0_2), + .o_features_0_2(daisy_chain_26_0_2), + .i_features_0_3(daisy_chain_25_0_3), + .o_features_0_3(daisy_chain_26_0_3), + .i_features_0_4(daisy_chain_25_0_4), + .o_features_0_4(daisy_chain_26_0_4), + .i_features_0_5(daisy_chain_25_0_5), + .o_features_0_5(daisy_chain_26_0_5), + .i_features_1_0(daisy_chain_25_1_0), + .o_features_1_0(daisy_chain_26_1_0), + .i_features_1_1(daisy_chain_25_1_1), + .o_features_1_1(daisy_chain_26_1_1), + .i_features_1_2(daisy_chain_25_1_2), + .o_features_1_2(daisy_chain_26_1_2), + .i_features_1_3(daisy_chain_25_1_3), + .o_features_1_3(daisy_chain_26_1_3), + .i_features_1_4(daisy_chain_25_1_4), + .o_features_1_4(daisy_chain_26_1_4), + .i_features_1_5(daisy_chain_25_1_5), + .o_features_1_5(daisy_chain_26_1_5), + .i_features_2_0(daisy_chain_25_2_0), + .o_features_2_0(daisy_chain_26_2_0), + .i_features_2_1(daisy_chain_25_2_1), + .o_features_2_1(daisy_chain_26_2_1), + .i_features_2_2(daisy_chain_25_2_2), + .o_features_2_2(daisy_chain_26_2_2), + .i_features_2_3(daisy_chain_25_2_3), + .o_features_2_3(daisy_chain_26_2_3), + .i_features_2_4(daisy_chain_25_2_4), + .o_features_2_4(daisy_chain_26_2_4), + .i_features_2_5(daisy_chain_25_2_5), + .o_features_2_5(daisy_chain_26_2_5), + .i_features_3_0(daisy_chain_25_3_0), + .o_features_3_0(daisy_chain_26_3_0), + .i_features_3_1(daisy_chain_25_3_1), + .o_features_3_1(daisy_chain_26_3_1), + .i_features_3_2(daisy_chain_25_3_2), + .o_features_3_2(daisy_chain_26_3_2), + .i_features_3_3(daisy_chain_25_3_3), + .o_features_3_3(daisy_chain_26_3_3), + .i_features_3_4(daisy_chain_25_3_4), + .o_features_3_4(daisy_chain_26_3_4), + .i_features_3_5(daisy_chain_25_3_5), + .o_features_3_5(daisy_chain_26_3_5), + .i_features_4_0(daisy_chain_25_4_0), + .o_features_4_0(daisy_chain_26_4_0), + .i_features_4_1(daisy_chain_25_4_1), + .o_features_4_1(daisy_chain_26_4_1), + .i_features_4_2(daisy_chain_25_4_2), + .o_features_4_2(daisy_chain_26_4_2), + .i_features_4_3(daisy_chain_25_4_3), + .o_features_4_3(daisy_chain_26_4_3), + .i_features_4_4(daisy_chain_25_4_4), + .o_features_4_4(daisy_chain_26_4_4), + .i_features_4_5(daisy_chain_25_4_5), + .o_features_4_5(daisy_chain_26_4_5), + .i_features_5_0(daisy_chain_25_5_0), + .o_features_5_0(daisy_chain_26_5_0), + .i_features_5_1(daisy_chain_25_5_1), + .o_features_5_1(daisy_chain_26_5_1), + .i_features_5_2(daisy_chain_25_5_2), + .o_features_5_2(daisy_chain_26_5_2), + .i_features_5_3(daisy_chain_25_5_3), + .o_features_5_3(daisy_chain_26_5_3), + .i_features_5_4(daisy_chain_25_5_4), + .o_features_5_4(daisy_chain_26_5_4), + .i_features_5_5(daisy_chain_25_5_5), + .o_features_5_5(daisy_chain_26_5_5), + .i_features_6_0(daisy_chain_25_6_0), + .o_features_6_0(daisy_chain_26_6_0), + .i_features_6_1(daisy_chain_25_6_1), + .o_features_6_1(daisy_chain_26_6_1), + .i_features_6_2(daisy_chain_25_6_2), + .o_features_6_2(daisy_chain_26_6_2), + .i_features_6_3(daisy_chain_25_6_3), + .o_features_6_3(daisy_chain_26_6_3), + .i_features_6_4(daisy_chain_25_6_4), + .o_features_6_4(daisy_chain_26_6_4), + .i_features_6_5(daisy_chain_25_6_5), + .o_features_6_5(daisy_chain_26_6_5), + .i_features_7_0(daisy_chain_25_7_0), + .o_features_7_0(daisy_chain_26_7_0), + .i_features_7_1(daisy_chain_25_7_1), + .o_features_7_1(daisy_chain_26_7_1), + .i_features_7_2(daisy_chain_25_7_2), + .o_features_7_2(daisy_chain_26_7_2), + .i_features_7_3(daisy_chain_25_7_3), + .o_features_7_3(daisy_chain_26_7_3), + .i_features_7_4(daisy_chain_25_7_4), + .o_features_7_4(daisy_chain_26_7_4), + .i_features_7_5(daisy_chain_25_7_5), + .o_features_7_5(daisy_chain_26_7_5), + .o_result_0(PE_output_26_0), + .o_result_1(PE_output_26_1), + .o_result_2(PE_output_26_2), + .o_result_3(PE_output_26_3), + .o_result_4(PE_output_26_4), + .o_result_5(PE_output_26_5), + .o_valid(PE_valid_26), + .o_next_reset(PE_next_reset_26), + .o_next_valid(PE_next_valid_26) +); + +processing_element processing_element_inst_27 ( + .clk(clk), + .i_reset(PE_next_reset_26), + .i_valid(PE_next_valid_26), + .i_features_0_0(daisy_chain_26_0_0), + .o_features_0_0(daisy_chain_27_0_0), + .i_features_0_1(daisy_chain_26_0_1), + .o_features_0_1(daisy_chain_27_0_1), + .i_features_0_2(daisy_chain_26_0_2), + .o_features_0_2(daisy_chain_27_0_2), + .i_features_0_3(daisy_chain_26_0_3), + .o_features_0_3(daisy_chain_27_0_3), + .i_features_0_4(daisy_chain_26_0_4), + .o_features_0_4(daisy_chain_27_0_4), + .i_features_0_5(daisy_chain_26_0_5), + .o_features_0_5(daisy_chain_27_0_5), + .i_features_1_0(daisy_chain_26_1_0), + .o_features_1_0(daisy_chain_27_1_0), + .i_features_1_1(daisy_chain_26_1_1), + .o_features_1_1(daisy_chain_27_1_1), + .i_features_1_2(daisy_chain_26_1_2), + .o_features_1_2(daisy_chain_27_1_2), + .i_features_1_3(daisy_chain_26_1_3), + .o_features_1_3(daisy_chain_27_1_3), + .i_features_1_4(daisy_chain_26_1_4), + .o_features_1_4(daisy_chain_27_1_4), + .i_features_1_5(daisy_chain_26_1_5), + .o_features_1_5(daisy_chain_27_1_5), + .i_features_2_0(daisy_chain_26_2_0), + .o_features_2_0(daisy_chain_27_2_0), + .i_features_2_1(daisy_chain_26_2_1), + .o_features_2_1(daisy_chain_27_2_1), + .i_features_2_2(daisy_chain_26_2_2), + .o_features_2_2(daisy_chain_27_2_2), + .i_features_2_3(daisy_chain_26_2_3), + .o_features_2_3(daisy_chain_27_2_3), + .i_features_2_4(daisy_chain_26_2_4), + .o_features_2_4(daisy_chain_27_2_4), + .i_features_2_5(daisy_chain_26_2_5), + .o_features_2_5(daisy_chain_27_2_5), + .i_features_3_0(daisy_chain_26_3_0), + .o_features_3_0(daisy_chain_27_3_0), + .i_features_3_1(daisy_chain_26_3_1), + .o_features_3_1(daisy_chain_27_3_1), + .i_features_3_2(daisy_chain_26_3_2), + .o_features_3_2(daisy_chain_27_3_2), + .i_features_3_3(daisy_chain_26_3_3), + .o_features_3_3(daisy_chain_27_3_3), + .i_features_3_4(daisy_chain_26_3_4), + .o_features_3_4(daisy_chain_27_3_4), + .i_features_3_5(daisy_chain_26_3_5), + .o_features_3_5(daisy_chain_27_3_5), + .i_features_4_0(daisy_chain_26_4_0), + .o_features_4_0(daisy_chain_27_4_0), + .i_features_4_1(daisy_chain_26_4_1), + .o_features_4_1(daisy_chain_27_4_1), + .i_features_4_2(daisy_chain_26_4_2), + .o_features_4_2(daisy_chain_27_4_2), + .i_features_4_3(daisy_chain_26_4_3), + .o_features_4_3(daisy_chain_27_4_3), + .i_features_4_4(daisy_chain_26_4_4), + .o_features_4_4(daisy_chain_27_4_4), + .i_features_4_5(daisy_chain_26_4_5), + .o_features_4_5(daisy_chain_27_4_5), + .i_features_5_0(daisy_chain_26_5_0), + .o_features_5_0(daisy_chain_27_5_0), + .i_features_5_1(daisy_chain_26_5_1), + .o_features_5_1(daisy_chain_27_5_1), + .i_features_5_2(daisy_chain_26_5_2), + .o_features_5_2(daisy_chain_27_5_2), + .i_features_5_3(daisy_chain_26_5_3), + .o_features_5_3(daisy_chain_27_5_3), + .i_features_5_4(daisy_chain_26_5_4), + .o_features_5_4(daisy_chain_27_5_4), + .i_features_5_5(daisy_chain_26_5_5), + .o_features_5_5(daisy_chain_27_5_5), + .i_features_6_0(daisy_chain_26_6_0), + .o_features_6_0(daisy_chain_27_6_0), + .i_features_6_1(daisy_chain_26_6_1), + .o_features_6_1(daisy_chain_27_6_1), + .i_features_6_2(daisy_chain_26_6_2), + .o_features_6_2(daisy_chain_27_6_2), + .i_features_6_3(daisy_chain_26_6_3), + .o_features_6_3(daisy_chain_27_6_3), + .i_features_6_4(daisy_chain_26_6_4), + .o_features_6_4(daisy_chain_27_6_4), + .i_features_6_5(daisy_chain_26_6_5), + .o_features_6_5(daisy_chain_27_6_5), + .i_features_7_0(daisy_chain_26_7_0), + .o_features_7_0(daisy_chain_27_7_0), + .i_features_7_1(daisy_chain_26_7_1), + .o_features_7_1(daisy_chain_27_7_1), + .i_features_7_2(daisy_chain_26_7_2), + .o_features_7_2(daisy_chain_27_7_2), + .i_features_7_3(daisy_chain_26_7_3), + .o_features_7_3(daisy_chain_27_7_3), + .i_features_7_4(daisy_chain_26_7_4), + .o_features_7_4(daisy_chain_27_7_4), + .i_features_7_5(daisy_chain_26_7_5), + .o_features_7_5(daisy_chain_27_7_5), + .o_result_0(PE_output_27_0), + .o_result_1(PE_output_27_1), + .o_result_2(PE_output_27_2), + .o_result_3(PE_output_27_3), + .o_result_4(PE_output_27_4), + .o_result_5(PE_output_27_5), + .o_valid(PE_valid_27), + .o_next_reset(PE_next_reset_27), + .o_next_valid(PE_next_valid_27) +); + +processing_element processing_element_inst_28 ( + .clk(clk), + .i_reset(PE_next_reset_27), + .i_valid(PE_next_valid_27), + .i_features_0_0(daisy_chain_27_0_0), + .o_features_0_0(daisy_chain_28_0_0), + .i_features_0_1(daisy_chain_27_0_1), + .o_features_0_1(daisy_chain_28_0_1), + .i_features_0_2(daisy_chain_27_0_2), + .o_features_0_2(daisy_chain_28_0_2), + .i_features_0_3(daisy_chain_27_0_3), + .o_features_0_3(daisy_chain_28_0_3), + .i_features_0_4(daisy_chain_27_0_4), + .o_features_0_4(daisy_chain_28_0_4), + .i_features_0_5(daisy_chain_27_0_5), + .o_features_0_5(daisy_chain_28_0_5), + .i_features_1_0(daisy_chain_27_1_0), + .o_features_1_0(daisy_chain_28_1_0), + .i_features_1_1(daisy_chain_27_1_1), + .o_features_1_1(daisy_chain_28_1_1), + .i_features_1_2(daisy_chain_27_1_2), + .o_features_1_2(daisy_chain_28_1_2), + .i_features_1_3(daisy_chain_27_1_3), + .o_features_1_3(daisy_chain_28_1_3), + .i_features_1_4(daisy_chain_27_1_4), + .o_features_1_4(daisy_chain_28_1_4), + .i_features_1_5(daisy_chain_27_1_5), + .o_features_1_5(daisy_chain_28_1_5), + .i_features_2_0(daisy_chain_27_2_0), + .o_features_2_0(daisy_chain_28_2_0), + .i_features_2_1(daisy_chain_27_2_1), + .o_features_2_1(daisy_chain_28_2_1), + .i_features_2_2(daisy_chain_27_2_2), + .o_features_2_2(daisy_chain_28_2_2), + .i_features_2_3(daisy_chain_27_2_3), + .o_features_2_3(daisy_chain_28_2_3), + .i_features_2_4(daisy_chain_27_2_4), + .o_features_2_4(daisy_chain_28_2_4), + .i_features_2_5(daisy_chain_27_2_5), + .o_features_2_5(daisy_chain_28_2_5), + .i_features_3_0(daisy_chain_27_3_0), + .o_features_3_0(daisy_chain_28_3_0), + .i_features_3_1(daisy_chain_27_3_1), + .o_features_3_1(daisy_chain_28_3_1), + .i_features_3_2(daisy_chain_27_3_2), + .o_features_3_2(daisy_chain_28_3_2), + .i_features_3_3(daisy_chain_27_3_3), + .o_features_3_3(daisy_chain_28_3_3), + .i_features_3_4(daisy_chain_27_3_4), + .o_features_3_4(daisy_chain_28_3_4), + .i_features_3_5(daisy_chain_27_3_5), + .o_features_3_5(daisy_chain_28_3_5), + .i_features_4_0(daisy_chain_27_4_0), + .o_features_4_0(daisy_chain_28_4_0), + .i_features_4_1(daisy_chain_27_4_1), + .o_features_4_1(daisy_chain_28_4_1), + .i_features_4_2(daisy_chain_27_4_2), + .o_features_4_2(daisy_chain_28_4_2), + .i_features_4_3(daisy_chain_27_4_3), + .o_features_4_3(daisy_chain_28_4_3), + .i_features_4_4(daisy_chain_27_4_4), + .o_features_4_4(daisy_chain_28_4_4), + .i_features_4_5(daisy_chain_27_4_5), + .o_features_4_5(daisy_chain_28_4_5), + .i_features_5_0(daisy_chain_27_5_0), + .o_features_5_0(daisy_chain_28_5_0), + .i_features_5_1(daisy_chain_27_5_1), + .o_features_5_1(daisy_chain_28_5_1), + .i_features_5_2(daisy_chain_27_5_2), + .o_features_5_2(daisy_chain_28_5_2), + .i_features_5_3(daisy_chain_27_5_3), + .o_features_5_3(daisy_chain_28_5_3), + .i_features_5_4(daisy_chain_27_5_4), + .o_features_5_4(daisy_chain_28_5_4), + .i_features_5_5(daisy_chain_27_5_5), + .o_features_5_5(daisy_chain_28_5_5), + .i_features_6_0(daisy_chain_27_6_0), + .o_features_6_0(daisy_chain_28_6_0), + .i_features_6_1(daisy_chain_27_6_1), + .o_features_6_1(daisy_chain_28_6_1), + .i_features_6_2(daisy_chain_27_6_2), + .o_features_6_2(daisy_chain_28_6_2), + .i_features_6_3(daisy_chain_27_6_3), + .o_features_6_3(daisy_chain_28_6_3), + .i_features_6_4(daisy_chain_27_6_4), + .o_features_6_4(daisy_chain_28_6_4), + .i_features_6_5(daisy_chain_27_6_5), + .o_features_6_5(daisy_chain_28_6_5), + .i_features_7_0(daisy_chain_27_7_0), + .o_features_7_0(daisy_chain_28_7_0), + .i_features_7_1(daisy_chain_27_7_1), + .o_features_7_1(daisy_chain_28_7_1), + .i_features_7_2(daisy_chain_27_7_2), + .o_features_7_2(daisy_chain_28_7_2), + .i_features_7_3(daisy_chain_27_7_3), + .o_features_7_3(daisy_chain_28_7_3), + .i_features_7_4(daisy_chain_27_7_4), + .o_features_7_4(daisy_chain_28_7_4), + .i_features_7_5(daisy_chain_27_7_5), + .o_features_7_5(daisy_chain_28_7_5), + .o_result_0(PE_output_28_0), + .o_result_1(PE_output_28_1), + .o_result_2(PE_output_28_2), + .o_result_3(PE_output_28_3), + .o_result_4(PE_output_28_4), + .o_result_5(PE_output_28_5), + .o_valid(PE_valid_28), + .o_next_reset(PE_next_reset_28), + .o_next_valid(PE_next_valid_28) +); + +processing_element processing_element_inst_29 ( + .clk(clk), + .i_reset(PE_next_reset_28), + .i_valid(PE_next_valid_28), + .i_features_0_0(daisy_chain_28_0_0), + .o_features_0_0(daisy_chain_29_0_0), + .i_features_0_1(daisy_chain_28_0_1), + .o_features_0_1(daisy_chain_29_0_1), + .i_features_0_2(daisy_chain_28_0_2), + .o_features_0_2(daisy_chain_29_0_2), + .i_features_0_3(daisy_chain_28_0_3), + .o_features_0_3(daisy_chain_29_0_3), + .i_features_0_4(daisy_chain_28_0_4), + .o_features_0_4(daisy_chain_29_0_4), + .i_features_0_5(daisy_chain_28_0_5), + .o_features_0_5(daisy_chain_29_0_5), + .i_features_1_0(daisy_chain_28_1_0), + .o_features_1_0(daisy_chain_29_1_0), + .i_features_1_1(daisy_chain_28_1_1), + .o_features_1_1(daisy_chain_29_1_1), + .i_features_1_2(daisy_chain_28_1_2), + .o_features_1_2(daisy_chain_29_1_2), + .i_features_1_3(daisy_chain_28_1_3), + .o_features_1_3(daisy_chain_29_1_3), + .i_features_1_4(daisy_chain_28_1_4), + .o_features_1_4(daisy_chain_29_1_4), + .i_features_1_5(daisy_chain_28_1_5), + .o_features_1_5(daisy_chain_29_1_5), + .i_features_2_0(daisy_chain_28_2_0), + .o_features_2_0(daisy_chain_29_2_0), + .i_features_2_1(daisy_chain_28_2_1), + .o_features_2_1(daisy_chain_29_2_1), + .i_features_2_2(daisy_chain_28_2_2), + .o_features_2_2(daisy_chain_29_2_2), + .i_features_2_3(daisy_chain_28_2_3), + .o_features_2_3(daisy_chain_29_2_3), + .i_features_2_4(daisy_chain_28_2_4), + .o_features_2_4(daisy_chain_29_2_4), + .i_features_2_5(daisy_chain_28_2_5), + .o_features_2_5(daisy_chain_29_2_5), + .i_features_3_0(daisy_chain_28_3_0), + .o_features_3_0(daisy_chain_29_3_0), + .i_features_3_1(daisy_chain_28_3_1), + .o_features_3_1(daisy_chain_29_3_1), + .i_features_3_2(daisy_chain_28_3_2), + .o_features_3_2(daisy_chain_29_3_2), + .i_features_3_3(daisy_chain_28_3_3), + .o_features_3_3(daisy_chain_29_3_3), + .i_features_3_4(daisy_chain_28_3_4), + .o_features_3_4(daisy_chain_29_3_4), + .i_features_3_5(daisy_chain_28_3_5), + .o_features_3_5(daisy_chain_29_3_5), + .i_features_4_0(daisy_chain_28_4_0), + .o_features_4_0(daisy_chain_29_4_0), + .i_features_4_1(daisy_chain_28_4_1), + .o_features_4_1(daisy_chain_29_4_1), + .i_features_4_2(daisy_chain_28_4_2), + .o_features_4_2(daisy_chain_29_4_2), + .i_features_4_3(daisy_chain_28_4_3), + .o_features_4_3(daisy_chain_29_4_3), + .i_features_4_4(daisy_chain_28_4_4), + .o_features_4_4(daisy_chain_29_4_4), + .i_features_4_5(daisy_chain_28_4_5), + .o_features_4_5(daisy_chain_29_4_5), + .i_features_5_0(daisy_chain_28_5_0), + .o_features_5_0(daisy_chain_29_5_0), + .i_features_5_1(daisy_chain_28_5_1), + .o_features_5_1(daisy_chain_29_5_1), + .i_features_5_2(daisy_chain_28_5_2), + .o_features_5_2(daisy_chain_29_5_2), + .i_features_5_3(daisy_chain_28_5_3), + .o_features_5_3(daisy_chain_29_5_3), + .i_features_5_4(daisy_chain_28_5_4), + .o_features_5_4(daisy_chain_29_5_4), + .i_features_5_5(daisy_chain_28_5_5), + .o_features_5_5(daisy_chain_29_5_5), + .i_features_6_0(daisy_chain_28_6_0), + .o_features_6_0(daisy_chain_29_6_0), + .i_features_6_1(daisy_chain_28_6_1), + .o_features_6_1(daisy_chain_29_6_1), + .i_features_6_2(daisy_chain_28_6_2), + .o_features_6_2(daisy_chain_29_6_2), + .i_features_6_3(daisy_chain_28_6_3), + .o_features_6_3(daisy_chain_29_6_3), + .i_features_6_4(daisy_chain_28_6_4), + .o_features_6_4(daisy_chain_29_6_4), + .i_features_6_5(daisy_chain_28_6_5), + .o_features_6_5(daisy_chain_29_6_5), + .i_features_7_0(daisy_chain_28_7_0), + .o_features_7_0(daisy_chain_29_7_0), + .i_features_7_1(daisy_chain_28_7_1), + .o_features_7_1(daisy_chain_29_7_1), + .i_features_7_2(daisy_chain_28_7_2), + .o_features_7_2(daisy_chain_29_7_2), + .i_features_7_3(daisy_chain_28_7_3), + .o_features_7_3(daisy_chain_29_7_3), + .i_features_7_4(daisy_chain_28_7_4), + .o_features_7_4(daisy_chain_29_7_4), + .i_features_7_5(daisy_chain_28_7_5), + .o_features_7_5(daisy_chain_29_7_5), + .o_result_0(PE_output_29_0), + .o_result_1(PE_output_29_1), + .o_result_2(PE_output_29_2), + .o_result_3(PE_output_29_3), + .o_result_4(PE_output_29_4), + .o_result_5(PE_output_29_5), + .o_valid(PE_valid_29), + .o_next_reset(PE_next_reset_29), + .o_next_valid(PE_next_valid_29) +); + +processing_element processing_element_inst_30 ( + .clk(clk), + .i_reset(PE_next_reset_29), + .i_valid(PE_next_valid_29), + .i_features_0_0(daisy_chain_29_0_0), + .o_features_0_0(daisy_chain_30_0_0), + .i_features_0_1(daisy_chain_29_0_1), + .o_features_0_1(daisy_chain_30_0_1), + .i_features_0_2(daisy_chain_29_0_2), + .o_features_0_2(daisy_chain_30_0_2), + .i_features_0_3(daisy_chain_29_0_3), + .o_features_0_3(daisy_chain_30_0_3), + .i_features_0_4(daisy_chain_29_0_4), + .o_features_0_4(daisy_chain_30_0_4), + .i_features_0_5(daisy_chain_29_0_5), + .o_features_0_5(daisy_chain_30_0_5), + .i_features_1_0(daisy_chain_29_1_0), + .o_features_1_0(daisy_chain_30_1_0), + .i_features_1_1(daisy_chain_29_1_1), + .o_features_1_1(daisy_chain_30_1_1), + .i_features_1_2(daisy_chain_29_1_2), + .o_features_1_2(daisy_chain_30_1_2), + .i_features_1_3(daisy_chain_29_1_3), + .o_features_1_3(daisy_chain_30_1_3), + .i_features_1_4(daisy_chain_29_1_4), + .o_features_1_4(daisy_chain_30_1_4), + .i_features_1_5(daisy_chain_29_1_5), + .o_features_1_5(daisy_chain_30_1_5), + .i_features_2_0(daisy_chain_29_2_0), + .o_features_2_0(daisy_chain_30_2_0), + .i_features_2_1(daisy_chain_29_2_1), + .o_features_2_1(daisy_chain_30_2_1), + .i_features_2_2(daisy_chain_29_2_2), + .o_features_2_2(daisy_chain_30_2_2), + .i_features_2_3(daisy_chain_29_2_3), + .o_features_2_3(daisy_chain_30_2_3), + .i_features_2_4(daisy_chain_29_2_4), + .o_features_2_4(daisy_chain_30_2_4), + .i_features_2_5(daisy_chain_29_2_5), + .o_features_2_5(daisy_chain_30_2_5), + .i_features_3_0(daisy_chain_29_3_0), + .o_features_3_0(daisy_chain_30_3_0), + .i_features_3_1(daisy_chain_29_3_1), + .o_features_3_1(daisy_chain_30_3_1), + .i_features_3_2(daisy_chain_29_3_2), + .o_features_3_2(daisy_chain_30_3_2), + .i_features_3_3(daisy_chain_29_3_3), + .o_features_3_3(daisy_chain_30_3_3), + .i_features_3_4(daisy_chain_29_3_4), + .o_features_3_4(daisy_chain_30_3_4), + .i_features_3_5(daisy_chain_29_3_5), + .o_features_3_5(daisy_chain_30_3_5), + .i_features_4_0(daisy_chain_29_4_0), + .o_features_4_0(daisy_chain_30_4_0), + .i_features_4_1(daisy_chain_29_4_1), + .o_features_4_1(daisy_chain_30_4_1), + .i_features_4_2(daisy_chain_29_4_2), + .o_features_4_2(daisy_chain_30_4_2), + .i_features_4_3(daisy_chain_29_4_3), + .o_features_4_3(daisy_chain_30_4_3), + .i_features_4_4(daisy_chain_29_4_4), + .o_features_4_4(daisy_chain_30_4_4), + .i_features_4_5(daisy_chain_29_4_5), + .o_features_4_5(daisy_chain_30_4_5), + .i_features_5_0(daisy_chain_29_5_0), + .o_features_5_0(daisy_chain_30_5_0), + .i_features_5_1(daisy_chain_29_5_1), + .o_features_5_1(daisy_chain_30_5_1), + .i_features_5_2(daisy_chain_29_5_2), + .o_features_5_2(daisy_chain_30_5_2), + .i_features_5_3(daisy_chain_29_5_3), + .o_features_5_3(daisy_chain_30_5_3), + .i_features_5_4(daisy_chain_29_5_4), + .o_features_5_4(daisy_chain_30_5_4), + .i_features_5_5(daisy_chain_29_5_5), + .o_features_5_5(daisy_chain_30_5_5), + .i_features_6_0(daisy_chain_29_6_0), + .o_features_6_0(daisy_chain_30_6_0), + .i_features_6_1(daisy_chain_29_6_1), + .o_features_6_1(daisy_chain_30_6_1), + .i_features_6_2(daisy_chain_29_6_2), + .o_features_6_2(daisy_chain_30_6_2), + .i_features_6_3(daisy_chain_29_6_3), + .o_features_6_3(daisy_chain_30_6_3), + .i_features_6_4(daisy_chain_29_6_4), + .o_features_6_4(daisy_chain_30_6_4), + .i_features_6_5(daisy_chain_29_6_5), + .o_features_6_5(daisy_chain_30_6_5), + .i_features_7_0(daisy_chain_29_7_0), + .o_features_7_0(daisy_chain_30_7_0), + .i_features_7_1(daisy_chain_29_7_1), + .o_features_7_1(daisy_chain_30_7_1), + .i_features_7_2(daisy_chain_29_7_2), + .o_features_7_2(daisy_chain_30_7_2), + .i_features_7_3(daisy_chain_29_7_3), + .o_features_7_3(daisy_chain_30_7_3), + .i_features_7_4(daisy_chain_29_7_4), + .o_features_7_4(daisy_chain_30_7_4), + .i_features_7_5(daisy_chain_29_7_5), + .o_features_7_5(daisy_chain_30_7_5), + .o_result_0(PE_output_30_0), + .o_result_1(PE_output_30_1), + .o_result_2(PE_output_30_2), + .o_result_3(PE_output_30_3), + .o_result_4(PE_output_30_4), + .o_result_5(PE_output_30_5), + .o_valid(PE_valid_30), + .o_next_reset(PE_next_reset_30), + .o_next_valid(PE_next_valid_30) +); + +processing_element processing_element_inst_31 ( + .clk(clk), + .i_reset(PE_next_reset_30), + .i_valid(PE_next_valid_30), + .i_features_0_0(daisy_chain_30_0_0), + .o_features_0_0(daisy_chain_31_0_0), + .i_features_0_1(daisy_chain_30_0_1), + .o_features_0_1(daisy_chain_31_0_1), + .i_features_0_2(daisy_chain_30_0_2), + .o_features_0_2(daisy_chain_31_0_2), + .i_features_0_3(daisy_chain_30_0_3), + .o_features_0_3(daisy_chain_31_0_3), + .i_features_0_4(daisy_chain_30_0_4), + .o_features_0_4(daisy_chain_31_0_4), + .i_features_0_5(daisy_chain_30_0_5), + .o_features_0_5(daisy_chain_31_0_5), + .i_features_1_0(daisy_chain_30_1_0), + .o_features_1_0(daisy_chain_31_1_0), + .i_features_1_1(daisy_chain_30_1_1), + .o_features_1_1(daisy_chain_31_1_1), + .i_features_1_2(daisy_chain_30_1_2), + .o_features_1_2(daisy_chain_31_1_2), + .i_features_1_3(daisy_chain_30_1_3), + .o_features_1_3(daisy_chain_31_1_3), + .i_features_1_4(daisy_chain_30_1_4), + .o_features_1_4(daisy_chain_31_1_4), + .i_features_1_5(daisy_chain_30_1_5), + .o_features_1_5(daisy_chain_31_1_5), + .i_features_2_0(daisy_chain_30_2_0), + .o_features_2_0(daisy_chain_31_2_0), + .i_features_2_1(daisy_chain_30_2_1), + .o_features_2_1(daisy_chain_31_2_1), + .i_features_2_2(daisy_chain_30_2_2), + .o_features_2_2(daisy_chain_31_2_2), + .i_features_2_3(daisy_chain_30_2_3), + .o_features_2_3(daisy_chain_31_2_3), + .i_features_2_4(daisy_chain_30_2_4), + .o_features_2_4(daisy_chain_31_2_4), + .i_features_2_5(daisy_chain_30_2_5), + .o_features_2_5(daisy_chain_31_2_5), + .i_features_3_0(daisy_chain_30_3_0), + .o_features_3_0(daisy_chain_31_3_0), + .i_features_3_1(daisy_chain_30_3_1), + .o_features_3_1(daisy_chain_31_3_1), + .i_features_3_2(daisy_chain_30_3_2), + .o_features_3_2(daisy_chain_31_3_2), + .i_features_3_3(daisy_chain_30_3_3), + .o_features_3_3(daisy_chain_31_3_3), + .i_features_3_4(daisy_chain_30_3_4), + .o_features_3_4(daisy_chain_31_3_4), + .i_features_3_5(daisy_chain_30_3_5), + .o_features_3_5(daisy_chain_31_3_5), + .i_features_4_0(daisy_chain_30_4_0), + .o_features_4_0(daisy_chain_31_4_0), + .i_features_4_1(daisy_chain_30_4_1), + .o_features_4_1(daisy_chain_31_4_1), + .i_features_4_2(daisy_chain_30_4_2), + .o_features_4_2(daisy_chain_31_4_2), + .i_features_4_3(daisy_chain_30_4_3), + .o_features_4_3(daisy_chain_31_4_3), + .i_features_4_4(daisy_chain_30_4_4), + .o_features_4_4(daisy_chain_31_4_4), + .i_features_4_5(daisy_chain_30_4_5), + .o_features_4_5(daisy_chain_31_4_5), + .i_features_5_0(daisy_chain_30_5_0), + .o_features_5_0(daisy_chain_31_5_0), + .i_features_5_1(daisy_chain_30_5_1), + .o_features_5_1(daisy_chain_31_5_1), + .i_features_5_2(daisy_chain_30_5_2), + .o_features_5_2(daisy_chain_31_5_2), + .i_features_5_3(daisy_chain_30_5_3), + .o_features_5_3(daisy_chain_31_5_3), + .i_features_5_4(daisy_chain_30_5_4), + .o_features_5_4(daisy_chain_31_5_4), + .i_features_5_5(daisy_chain_30_5_5), + .o_features_5_5(daisy_chain_31_5_5), + .i_features_6_0(daisy_chain_30_6_0), + .o_features_6_0(daisy_chain_31_6_0), + .i_features_6_1(daisy_chain_30_6_1), + .o_features_6_1(daisy_chain_31_6_1), + .i_features_6_2(daisy_chain_30_6_2), + .o_features_6_2(daisy_chain_31_6_2), + .i_features_6_3(daisy_chain_30_6_3), + .o_features_6_3(daisy_chain_31_6_3), + .i_features_6_4(daisy_chain_30_6_4), + .o_features_6_4(daisy_chain_31_6_4), + .i_features_6_5(daisy_chain_30_6_5), + .o_features_6_5(daisy_chain_31_6_5), + .i_features_7_0(daisy_chain_30_7_0), + .o_features_7_0(daisy_chain_31_7_0), + .i_features_7_1(daisy_chain_30_7_1), + .o_features_7_1(daisy_chain_31_7_1), + .i_features_7_2(daisy_chain_30_7_2), + .o_features_7_2(daisy_chain_31_7_2), + .i_features_7_3(daisy_chain_30_7_3), + .o_features_7_3(daisy_chain_31_7_3), + .i_features_7_4(daisy_chain_30_7_4), + .o_features_7_4(daisy_chain_31_7_4), + .i_features_7_5(daisy_chain_30_7_5), + .o_features_7_5(daisy_chain_31_7_5), + .o_result_0(PE_output_31_0), + .o_result_1(PE_output_31_1), + .o_result_2(PE_output_31_2), + .o_result_3(PE_output_31_3), + .o_result_4(PE_output_31_4), + .o_result_5(PE_output_31_5), + .o_valid(PE_valid_31), + .o_next_reset(PE_next_reset_31), + .o_next_valid(PE_next_valid_31) +); + +processing_element processing_element_inst_32 ( + .clk(clk), + .i_reset(PE_next_reset_31), + .i_valid(PE_next_valid_31), + .i_features_0_0(daisy_chain_31_0_0), + .o_features_0_0(daisy_chain_32_0_0), + .i_features_0_1(daisy_chain_31_0_1), + .o_features_0_1(daisy_chain_32_0_1), + .i_features_0_2(daisy_chain_31_0_2), + .o_features_0_2(daisy_chain_32_0_2), + .i_features_0_3(daisy_chain_31_0_3), + .o_features_0_3(daisy_chain_32_0_3), + .i_features_0_4(daisy_chain_31_0_4), + .o_features_0_4(daisy_chain_32_0_4), + .i_features_0_5(daisy_chain_31_0_5), + .o_features_0_5(daisy_chain_32_0_5), + .i_features_1_0(daisy_chain_31_1_0), + .o_features_1_0(daisy_chain_32_1_0), + .i_features_1_1(daisy_chain_31_1_1), + .o_features_1_1(daisy_chain_32_1_1), + .i_features_1_2(daisy_chain_31_1_2), + .o_features_1_2(daisy_chain_32_1_2), + .i_features_1_3(daisy_chain_31_1_3), + .o_features_1_3(daisy_chain_32_1_3), + .i_features_1_4(daisy_chain_31_1_4), + .o_features_1_4(daisy_chain_32_1_4), + .i_features_1_5(daisy_chain_31_1_5), + .o_features_1_5(daisy_chain_32_1_5), + .i_features_2_0(daisy_chain_31_2_0), + .o_features_2_0(daisy_chain_32_2_0), + .i_features_2_1(daisy_chain_31_2_1), + .o_features_2_1(daisy_chain_32_2_1), + .i_features_2_2(daisy_chain_31_2_2), + .o_features_2_2(daisy_chain_32_2_2), + .i_features_2_3(daisy_chain_31_2_3), + .o_features_2_3(daisy_chain_32_2_3), + .i_features_2_4(daisy_chain_31_2_4), + .o_features_2_4(daisy_chain_32_2_4), + .i_features_2_5(daisy_chain_31_2_5), + .o_features_2_5(daisy_chain_32_2_5), + .i_features_3_0(daisy_chain_31_3_0), + .o_features_3_0(daisy_chain_32_3_0), + .i_features_3_1(daisy_chain_31_3_1), + .o_features_3_1(daisy_chain_32_3_1), + .i_features_3_2(daisy_chain_31_3_2), + .o_features_3_2(daisy_chain_32_3_2), + .i_features_3_3(daisy_chain_31_3_3), + .o_features_3_3(daisy_chain_32_3_3), + .i_features_3_4(daisy_chain_31_3_4), + .o_features_3_4(daisy_chain_32_3_4), + .i_features_3_5(daisy_chain_31_3_5), + .o_features_3_5(daisy_chain_32_3_5), + .i_features_4_0(daisy_chain_31_4_0), + .o_features_4_0(daisy_chain_32_4_0), + .i_features_4_1(daisy_chain_31_4_1), + .o_features_4_1(daisy_chain_32_4_1), + .i_features_4_2(daisy_chain_31_4_2), + .o_features_4_2(daisy_chain_32_4_2), + .i_features_4_3(daisy_chain_31_4_3), + .o_features_4_3(daisy_chain_32_4_3), + .i_features_4_4(daisy_chain_31_4_4), + .o_features_4_4(daisy_chain_32_4_4), + .i_features_4_5(daisy_chain_31_4_5), + .o_features_4_5(daisy_chain_32_4_5), + .i_features_5_0(daisy_chain_31_5_0), + .o_features_5_0(daisy_chain_32_5_0), + .i_features_5_1(daisy_chain_31_5_1), + .o_features_5_1(daisy_chain_32_5_1), + .i_features_5_2(daisy_chain_31_5_2), + .o_features_5_2(daisy_chain_32_5_2), + .i_features_5_3(daisy_chain_31_5_3), + .o_features_5_3(daisy_chain_32_5_3), + .i_features_5_4(daisy_chain_31_5_4), + .o_features_5_4(daisy_chain_32_5_4), + .i_features_5_5(daisy_chain_31_5_5), + .o_features_5_5(daisy_chain_32_5_5), + .i_features_6_0(daisy_chain_31_6_0), + .o_features_6_0(daisy_chain_32_6_0), + .i_features_6_1(daisy_chain_31_6_1), + .o_features_6_1(daisy_chain_32_6_1), + .i_features_6_2(daisy_chain_31_6_2), + .o_features_6_2(daisy_chain_32_6_2), + .i_features_6_3(daisy_chain_31_6_3), + .o_features_6_3(daisy_chain_32_6_3), + .i_features_6_4(daisy_chain_31_6_4), + .o_features_6_4(daisy_chain_32_6_4), + .i_features_6_5(daisy_chain_31_6_5), + .o_features_6_5(daisy_chain_32_6_5), + .i_features_7_0(daisy_chain_31_7_0), + .o_features_7_0(daisy_chain_32_7_0), + .i_features_7_1(daisy_chain_31_7_1), + .o_features_7_1(daisy_chain_32_7_1), + .i_features_7_2(daisy_chain_31_7_2), + .o_features_7_2(daisy_chain_32_7_2), + .i_features_7_3(daisy_chain_31_7_3), + .o_features_7_3(daisy_chain_32_7_3), + .i_features_7_4(daisy_chain_31_7_4), + .o_features_7_4(daisy_chain_32_7_4), + .i_features_7_5(daisy_chain_31_7_5), + .o_features_7_5(daisy_chain_32_7_5), + .o_result_0(PE_output_32_0), + .o_result_1(PE_output_32_1), + .o_result_2(PE_output_32_2), + .o_result_3(PE_output_32_3), + .o_result_4(PE_output_32_4), + .o_result_5(PE_output_32_5), + .o_valid(PE_valid_32), + .o_next_reset(PE_next_reset_32), + .o_next_valid(PE_next_valid_32) +); + +processing_element processing_element_inst_33 ( + .clk(clk), + .i_reset(PE_next_reset_32), + .i_valid(PE_next_valid_32), + .i_features_0_0(daisy_chain_32_0_0), + .o_features_0_0(daisy_chain_33_0_0), + .i_features_0_1(daisy_chain_32_0_1), + .o_features_0_1(daisy_chain_33_0_1), + .i_features_0_2(daisy_chain_32_0_2), + .o_features_0_2(daisy_chain_33_0_2), + .i_features_0_3(daisy_chain_32_0_3), + .o_features_0_3(daisy_chain_33_0_3), + .i_features_0_4(daisy_chain_32_0_4), + .o_features_0_4(daisy_chain_33_0_4), + .i_features_0_5(daisy_chain_32_0_5), + .o_features_0_5(daisy_chain_33_0_5), + .i_features_1_0(daisy_chain_32_1_0), + .o_features_1_0(daisy_chain_33_1_0), + .i_features_1_1(daisy_chain_32_1_1), + .o_features_1_1(daisy_chain_33_1_1), + .i_features_1_2(daisy_chain_32_1_2), + .o_features_1_2(daisy_chain_33_1_2), + .i_features_1_3(daisy_chain_32_1_3), + .o_features_1_3(daisy_chain_33_1_3), + .i_features_1_4(daisy_chain_32_1_4), + .o_features_1_4(daisy_chain_33_1_4), + .i_features_1_5(daisy_chain_32_1_5), + .o_features_1_5(daisy_chain_33_1_5), + .i_features_2_0(daisy_chain_32_2_0), + .o_features_2_0(daisy_chain_33_2_0), + .i_features_2_1(daisy_chain_32_2_1), + .o_features_2_1(daisy_chain_33_2_1), + .i_features_2_2(daisy_chain_32_2_2), + .o_features_2_2(daisy_chain_33_2_2), + .i_features_2_3(daisy_chain_32_2_3), + .o_features_2_3(daisy_chain_33_2_3), + .i_features_2_4(daisy_chain_32_2_4), + .o_features_2_4(daisy_chain_33_2_4), + .i_features_2_5(daisy_chain_32_2_5), + .o_features_2_5(daisy_chain_33_2_5), + .i_features_3_0(daisy_chain_32_3_0), + .o_features_3_0(daisy_chain_33_3_0), + .i_features_3_1(daisy_chain_32_3_1), + .o_features_3_1(daisy_chain_33_3_1), + .i_features_3_2(daisy_chain_32_3_2), + .o_features_3_2(daisy_chain_33_3_2), + .i_features_3_3(daisy_chain_32_3_3), + .o_features_3_3(daisy_chain_33_3_3), + .i_features_3_4(daisy_chain_32_3_4), + .o_features_3_4(daisy_chain_33_3_4), + .i_features_3_5(daisy_chain_32_3_5), + .o_features_3_5(daisy_chain_33_3_5), + .i_features_4_0(daisy_chain_32_4_0), + .o_features_4_0(daisy_chain_33_4_0), + .i_features_4_1(daisy_chain_32_4_1), + .o_features_4_1(daisy_chain_33_4_1), + .i_features_4_2(daisy_chain_32_4_2), + .o_features_4_2(daisy_chain_33_4_2), + .i_features_4_3(daisy_chain_32_4_3), + .o_features_4_3(daisy_chain_33_4_3), + .i_features_4_4(daisy_chain_32_4_4), + .o_features_4_4(daisy_chain_33_4_4), + .i_features_4_5(daisy_chain_32_4_5), + .o_features_4_5(daisy_chain_33_4_5), + .i_features_5_0(daisy_chain_32_5_0), + .o_features_5_0(daisy_chain_33_5_0), + .i_features_5_1(daisy_chain_32_5_1), + .o_features_5_1(daisy_chain_33_5_1), + .i_features_5_2(daisy_chain_32_5_2), + .o_features_5_2(daisy_chain_33_5_2), + .i_features_5_3(daisy_chain_32_5_3), + .o_features_5_3(daisy_chain_33_5_3), + .i_features_5_4(daisy_chain_32_5_4), + .o_features_5_4(daisy_chain_33_5_4), + .i_features_5_5(daisy_chain_32_5_5), + .o_features_5_5(daisy_chain_33_5_5), + .i_features_6_0(daisy_chain_32_6_0), + .o_features_6_0(daisy_chain_33_6_0), + .i_features_6_1(daisy_chain_32_6_1), + .o_features_6_1(daisy_chain_33_6_1), + .i_features_6_2(daisy_chain_32_6_2), + .o_features_6_2(daisy_chain_33_6_2), + .i_features_6_3(daisy_chain_32_6_3), + .o_features_6_3(daisy_chain_33_6_3), + .i_features_6_4(daisy_chain_32_6_4), + .o_features_6_4(daisy_chain_33_6_4), + .i_features_6_5(daisy_chain_32_6_5), + .o_features_6_5(daisy_chain_33_6_5), + .i_features_7_0(daisy_chain_32_7_0), + .o_features_7_0(daisy_chain_33_7_0), + .i_features_7_1(daisy_chain_32_7_1), + .o_features_7_1(daisy_chain_33_7_1), + .i_features_7_2(daisy_chain_32_7_2), + .o_features_7_2(daisy_chain_33_7_2), + .i_features_7_3(daisy_chain_32_7_3), + .o_features_7_3(daisy_chain_33_7_3), + .i_features_7_4(daisy_chain_32_7_4), + .o_features_7_4(daisy_chain_33_7_4), + .i_features_7_5(daisy_chain_32_7_5), + .o_features_7_5(daisy_chain_33_7_5), + .o_result_0(PE_output_33_0), + .o_result_1(PE_output_33_1), + .o_result_2(PE_output_33_2), + .o_result_3(PE_output_33_3), + .o_result_4(PE_output_33_4), + .o_result_5(PE_output_33_5), + .o_valid(PE_valid_33), + .o_next_reset(PE_next_reset_33), + .o_next_valid(PE_next_valid_33) +); + +processing_element processing_element_inst_34 ( + .clk(clk), + .i_reset(PE_next_reset_33), + .i_valid(PE_next_valid_33), + .i_features_0_0(daisy_chain_33_0_0), + .o_features_0_0(daisy_chain_34_0_0), + .i_features_0_1(daisy_chain_33_0_1), + .o_features_0_1(daisy_chain_34_0_1), + .i_features_0_2(daisy_chain_33_0_2), + .o_features_0_2(daisy_chain_34_0_2), + .i_features_0_3(daisy_chain_33_0_3), + .o_features_0_3(daisy_chain_34_0_3), + .i_features_0_4(daisy_chain_33_0_4), + .o_features_0_4(daisy_chain_34_0_4), + .i_features_0_5(daisy_chain_33_0_5), + .o_features_0_5(daisy_chain_34_0_5), + .i_features_1_0(daisy_chain_33_1_0), + .o_features_1_0(daisy_chain_34_1_0), + .i_features_1_1(daisy_chain_33_1_1), + .o_features_1_1(daisy_chain_34_1_1), + .i_features_1_2(daisy_chain_33_1_2), + .o_features_1_2(daisy_chain_34_1_2), + .i_features_1_3(daisy_chain_33_1_3), + .o_features_1_3(daisy_chain_34_1_3), + .i_features_1_4(daisy_chain_33_1_4), + .o_features_1_4(daisy_chain_34_1_4), + .i_features_1_5(daisy_chain_33_1_5), + .o_features_1_5(daisy_chain_34_1_5), + .i_features_2_0(daisy_chain_33_2_0), + .o_features_2_0(daisy_chain_34_2_0), + .i_features_2_1(daisy_chain_33_2_1), + .o_features_2_1(daisy_chain_34_2_1), + .i_features_2_2(daisy_chain_33_2_2), + .o_features_2_2(daisy_chain_34_2_2), + .i_features_2_3(daisy_chain_33_2_3), + .o_features_2_3(daisy_chain_34_2_3), + .i_features_2_4(daisy_chain_33_2_4), + .o_features_2_4(daisy_chain_34_2_4), + .i_features_2_5(daisy_chain_33_2_5), + .o_features_2_5(daisy_chain_34_2_5), + .i_features_3_0(daisy_chain_33_3_0), + .o_features_3_0(daisy_chain_34_3_0), + .i_features_3_1(daisy_chain_33_3_1), + .o_features_3_1(daisy_chain_34_3_1), + .i_features_3_2(daisy_chain_33_3_2), + .o_features_3_2(daisy_chain_34_3_2), + .i_features_3_3(daisy_chain_33_3_3), + .o_features_3_3(daisy_chain_34_3_3), + .i_features_3_4(daisy_chain_33_3_4), + .o_features_3_4(daisy_chain_34_3_4), + .i_features_3_5(daisy_chain_33_3_5), + .o_features_3_5(daisy_chain_34_3_5), + .i_features_4_0(daisy_chain_33_4_0), + .o_features_4_0(daisy_chain_34_4_0), + .i_features_4_1(daisy_chain_33_4_1), + .o_features_4_1(daisy_chain_34_4_1), + .i_features_4_2(daisy_chain_33_4_2), + .o_features_4_2(daisy_chain_34_4_2), + .i_features_4_3(daisy_chain_33_4_3), + .o_features_4_3(daisy_chain_34_4_3), + .i_features_4_4(daisy_chain_33_4_4), + .o_features_4_4(daisy_chain_34_4_4), + .i_features_4_5(daisy_chain_33_4_5), + .o_features_4_5(daisy_chain_34_4_5), + .i_features_5_0(daisy_chain_33_5_0), + .o_features_5_0(daisy_chain_34_5_0), + .i_features_5_1(daisy_chain_33_5_1), + .o_features_5_1(daisy_chain_34_5_1), + .i_features_5_2(daisy_chain_33_5_2), + .o_features_5_2(daisy_chain_34_5_2), + .i_features_5_3(daisy_chain_33_5_3), + .o_features_5_3(daisy_chain_34_5_3), + .i_features_5_4(daisy_chain_33_5_4), + .o_features_5_4(daisy_chain_34_5_4), + .i_features_5_5(daisy_chain_33_5_5), + .o_features_5_5(daisy_chain_34_5_5), + .i_features_6_0(daisy_chain_33_6_0), + .o_features_6_0(daisy_chain_34_6_0), + .i_features_6_1(daisy_chain_33_6_1), + .o_features_6_1(daisy_chain_34_6_1), + .i_features_6_2(daisy_chain_33_6_2), + .o_features_6_2(daisy_chain_34_6_2), + .i_features_6_3(daisy_chain_33_6_3), + .o_features_6_3(daisy_chain_34_6_3), + .i_features_6_4(daisy_chain_33_6_4), + .o_features_6_4(daisy_chain_34_6_4), + .i_features_6_5(daisy_chain_33_6_5), + .o_features_6_5(daisy_chain_34_6_5), + .i_features_7_0(daisy_chain_33_7_0), + .o_features_7_0(daisy_chain_34_7_0), + .i_features_7_1(daisy_chain_33_7_1), + .o_features_7_1(daisy_chain_34_7_1), + .i_features_7_2(daisy_chain_33_7_2), + .o_features_7_2(daisy_chain_34_7_2), + .i_features_7_3(daisy_chain_33_7_3), + .o_features_7_3(daisy_chain_34_7_3), + .i_features_7_4(daisy_chain_33_7_4), + .o_features_7_4(daisy_chain_34_7_4), + .i_features_7_5(daisy_chain_33_7_5), + .o_features_7_5(daisy_chain_34_7_5), + .o_result_0(PE_output_34_0), + .o_result_1(PE_output_34_1), + .o_result_2(PE_output_34_2), + .o_result_3(PE_output_34_3), + .o_result_4(PE_output_34_4), + .o_result_5(PE_output_34_5), + .o_valid(PE_valid_34), + .o_next_reset(PE_next_reset_34), + .o_next_valid(PE_next_valid_34) +); + +processing_element processing_element_inst_35 ( + .clk(clk), + .i_reset(PE_next_reset_34), + .i_valid(PE_next_valid_34), + .i_features_0_0(daisy_chain_34_0_0), + .o_features_0_0(daisy_chain_35_0_0), + .i_features_0_1(daisy_chain_34_0_1), + .o_features_0_1(daisy_chain_35_0_1), + .i_features_0_2(daisy_chain_34_0_2), + .o_features_0_2(daisy_chain_35_0_2), + .i_features_0_3(daisy_chain_34_0_3), + .o_features_0_3(daisy_chain_35_0_3), + .i_features_0_4(daisy_chain_34_0_4), + .o_features_0_4(daisy_chain_35_0_4), + .i_features_0_5(daisy_chain_34_0_5), + .o_features_0_5(daisy_chain_35_0_5), + .i_features_1_0(daisy_chain_34_1_0), + .o_features_1_0(daisy_chain_35_1_0), + .i_features_1_1(daisy_chain_34_1_1), + .o_features_1_1(daisy_chain_35_1_1), + .i_features_1_2(daisy_chain_34_1_2), + .o_features_1_2(daisy_chain_35_1_2), + .i_features_1_3(daisy_chain_34_1_3), + .o_features_1_3(daisy_chain_35_1_3), + .i_features_1_4(daisy_chain_34_1_4), + .o_features_1_4(daisy_chain_35_1_4), + .i_features_1_5(daisy_chain_34_1_5), + .o_features_1_5(daisy_chain_35_1_5), + .i_features_2_0(daisy_chain_34_2_0), + .o_features_2_0(daisy_chain_35_2_0), + .i_features_2_1(daisy_chain_34_2_1), + .o_features_2_1(daisy_chain_35_2_1), + .i_features_2_2(daisy_chain_34_2_2), + .o_features_2_2(daisy_chain_35_2_2), + .i_features_2_3(daisy_chain_34_2_3), + .o_features_2_3(daisy_chain_35_2_3), + .i_features_2_4(daisy_chain_34_2_4), + .o_features_2_4(daisy_chain_35_2_4), + .i_features_2_5(daisy_chain_34_2_5), + .o_features_2_5(daisy_chain_35_2_5), + .i_features_3_0(daisy_chain_34_3_0), + .o_features_3_0(daisy_chain_35_3_0), + .i_features_3_1(daisy_chain_34_3_1), + .o_features_3_1(daisy_chain_35_3_1), + .i_features_3_2(daisy_chain_34_3_2), + .o_features_3_2(daisy_chain_35_3_2), + .i_features_3_3(daisy_chain_34_3_3), + .o_features_3_3(daisy_chain_35_3_3), + .i_features_3_4(daisy_chain_34_3_4), + .o_features_3_4(daisy_chain_35_3_4), + .i_features_3_5(daisy_chain_34_3_5), + .o_features_3_5(daisy_chain_35_3_5), + .i_features_4_0(daisy_chain_34_4_0), + .o_features_4_0(daisy_chain_35_4_0), + .i_features_4_1(daisy_chain_34_4_1), + .o_features_4_1(daisy_chain_35_4_1), + .i_features_4_2(daisy_chain_34_4_2), + .o_features_4_2(daisy_chain_35_4_2), + .i_features_4_3(daisy_chain_34_4_3), + .o_features_4_3(daisy_chain_35_4_3), + .i_features_4_4(daisy_chain_34_4_4), + .o_features_4_4(daisy_chain_35_4_4), + .i_features_4_5(daisy_chain_34_4_5), + .o_features_4_5(daisy_chain_35_4_5), + .i_features_5_0(daisy_chain_34_5_0), + .o_features_5_0(daisy_chain_35_5_0), + .i_features_5_1(daisy_chain_34_5_1), + .o_features_5_1(daisy_chain_35_5_1), + .i_features_5_2(daisy_chain_34_5_2), + .o_features_5_2(daisy_chain_35_5_2), + .i_features_5_3(daisy_chain_34_5_3), + .o_features_5_3(daisy_chain_35_5_3), + .i_features_5_4(daisy_chain_34_5_4), + .o_features_5_4(daisy_chain_35_5_4), + .i_features_5_5(daisy_chain_34_5_5), + .o_features_5_5(daisy_chain_35_5_5), + .i_features_6_0(daisy_chain_34_6_0), + .o_features_6_0(daisy_chain_35_6_0), + .i_features_6_1(daisy_chain_34_6_1), + .o_features_6_1(daisy_chain_35_6_1), + .i_features_6_2(daisy_chain_34_6_2), + .o_features_6_2(daisy_chain_35_6_2), + .i_features_6_3(daisy_chain_34_6_3), + .o_features_6_3(daisy_chain_35_6_3), + .i_features_6_4(daisy_chain_34_6_4), + .o_features_6_4(daisy_chain_35_6_4), + .i_features_6_5(daisy_chain_34_6_5), + .o_features_6_5(daisy_chain_35_6_5), + .i_features_7_0(daisy_chain_34_7_0), + .o_features_7_0(daisy_chain_35_7_0), + .i_features_7_1(daisy_chain_34_7_1), + .o_features_7_1(daisy_chain_35_7_1), + .i_features_7_2(daisy_chain_34_7_2), + .o_features_7_2(daisy_chain_35_7_2), + .i_features_7_3(daisy_chain_34_7_3), + .o_features_7_3(daisy_chain_35_7_3), + .i_features_7_4(daisy_chain_34_7_4), + .o_features_7_4(daisy_chain_35_7_4), + .i_features_7_5(daisy_chain_34_7_5), + .o_features_7_5(daisy_chain_35_7_5), + .o_result_0(PE_output_35_0), + .o_result_1(PE_output_35_1), + .o_result_2(PE_output_35_2), + .o_result_3(PE_output_35_3), + .o_result_4(PE_output_35_4), + .o_result_5(PE_output_35_5), + .o_valid(PE_valid_35), + .o_next_reset(PE_next_reset_35), + .o_next_valid(PE_next_valid_35) +); + +processing_element processing_element_inst_36 ( + .clk(clk), + .i_reset(PE_next_reset_35), + .i_valid(PE_next_valid_35), + .i_features_0_0(daisy_chain_35_0_0), + .o_features_0_0(daisy_chain_36_0_0), + .i_features_0_1(daisy_chain_35_0_1), + .o_features_0_1(daisy_chain_36_0_1), + .i_features_0_2(daisy_chain_35_0_2), + .o_features_0_2(daisy_chain_36_0_2), + .i_features_0_3(daisy_chain_35_0_3), + .o_features_0_3(daisy_chain_36_0_3), + .i_features_0_4(daisy_chain_35_0_4), + .o_features_0_4(daisy_chain_36_0_4), + .i_features_0_5(daisy_chain_35_0_5), + .o_features_0_5(daisy_chain_36_0_5), + .i_features_1_0(daisy_chain_35_1_0), + .o_features_1_0(daisy_chain_36_1_0), + .i_features_1_1(daisy_chain_35_1_1), + .o_features_1_1(daisy_chain_36_1_1), + .i_features_1_2(daisy_chain_35_1_2), + .o_features_1_2(daisy_chain_36_1_2), + .i_features_1_3(daisy_chain_35_1_3), + .o_features_1_3(daisy_chain_36_1_3), + .i_features_1_4(daisy_chain_35_1_4), + .o_features_1_4(daisy_chain_36_1_4), + .i_features_1_5(daisy_chain_35_1_5), + .o_features_1_5(daisy_chain_36_1_5), + .i_features_2_0(daisy_chain_35_2_0), + .o_features_2_0(daisy_chain_36_2_0), + .i_features_2_1(daisy_chain_35_2_1), + .o_features_2_1(daisy_chain_36_2_1), + .i_features_2_2(daisy_chain_35_2_2), + .o_features_2_2(daisy_chain_36_2_2), + .i_features_2_3(daisy_chain_35_2_3), + .o_features_2_3(daisy_chain_36_2_3), + .i_features_2_4(daisy_chain_35_2_4), + .o_features_2_4(daisy_chain_36_2_4), + .i_features_2_5(daisy_chain_35_2_5), + .o_features_2_5(daisy_chain_36_2_5), + .i_features_3_0(daisy_chain_35_3_0), + .o_features_3_0(daisy_chain_36_3_0), + .i_features_3_1(daisy_chain_35_3_1), + .o_features_3_1(daisy_chain_36_3_1), + .i_features_3_2(daisy_chain_35_3_2), + .o_features_3_2(daisy_chain_36_3_2), + .i_features_3_3(daisy_chain_35_3_3), + .o_features_3_3(daisy_chain_36_3_3), + .i_features_3_4(daisy_chain_35_3_4), + .o_features_3_4(daisy_chain_36_3_4), + .i_features_3_5(daisy_chain_35_3_5), + .o_features_3_5(daisy_chain_36_3_5), + .i_features_4_0(daisy_chain_35_4_0), + .o_features_4_0(daisy_chain_36_4_0), + .i_features_4_1(daisy_chain_35_4_1), + .o_features_4_1(daisy_chain_36_4_1), + .i_features_4_2(daisy_chain_35_4_2), + .o_features_4_2(daisy_chain_36_4_2), + .i_features_4_3(daisy_chain_35_4_3), + .o_features_4_3(daisy_chain_36_4_3), + .i_features_4_4(daisy_chain_35_4_4), + .o_features_4_4(daisy_chain_36_4_4), + .i_features_4_5(daisy_chain_35_4_5), + .o_features_4_5(daisy_chain_36_4_5), + .i_features_5_0(daisy_chain_35_5_0), + .o_features_5_0(daisy_chain_36_5_0), + .i_features_5_1(daisy_chain_35_5_1), + .o_features_5_1(daisy_chain_36_5_1), + .i_features_5_2(daisy_chain_35_5_2), + .o_features_5_2(daisy_chain_36_5_2), + .i_features_5_3(daisy_chain_35_5_3), + .o_features_5_3(daisy_chain_36_5_3), + .i_features_5_4(daisy_chain_35_5_4), + .o_features_5_4(daisy_chain_36_5_4), + .i_features_5_5(daisy_chain_35_5_5), + .o_features_5_5(daisy_chain_36_5_5), + .i_features_6_0(daisy_chain_35_6_0), + .o_features_6_0(daisy_chain_36_6_0), + .i_features_6_1(daisy_chain_35_6_1), + .o_features_6_1(daisy_chain_36_6_1), + .i_features_6_2(daisy_chain_35_6_2), + .o_features_6_2(daisy_chain_36_6_2), + .i_features_6_3(daisy_chain_35_6_3), + .o_features_6_3(daisy_chain_36_6_3), + .i_features_6_4(daisy_chain_35_6_4), + .o_features_6_4(daisy_chain_36_6_4), + .i_features_6_5(daisy_chain_35_6_5), + .o_features_6_5(daisy_chain_36_6_5), + .i_features_7_0(daisy_chain_35_7_0), + .o_features_7_0(daisy_chain_36_7_0), + .i_features_7_1(daisy_chain_35_7_1), + .o_features_7_1(daisy_chain_36_7_1), + .i_features_7_2(daisy_chain_35_7_2), + .o_features_7_2(daisy_chain_36_7_2), + .i_features_7_3(daisy_chain_35_7_3), + .o_features_7_3(daisy_chain_36_7_3), + .i_features_7_4(daisy_chain_35_7_4), + .o_features_7_4(daisy_chain_36_7_4), + .i_features_7_5(daisy_chain_35_7_5), + .o_features_7_5(daisy_chain_36_7_5), + .o_result_0(PE_output_36_0), + .o_result_1(PE_output_36_1), + .o_result_2(PE_output_36_2), + .o_result_3(PE_output_36_3), + .o_result_4(PE_output_36_4), + .o_result_5(PE_output_36_5), + .o_valid(PE_valid_36), + .o_next_reset(PE_next_reset_36), + .o_next_valid(PE_next_valid_36) +); + +processing_element processing_element_inst_37 ( + .clk(clk), + .i_reset(PE_next_reset_36), + .i_valid(PE_next_valid_36), + .i_features_0_0(daisy_chain_36_0_0), + .o_features_0_0(daisy_chain_37_0_0), + .i_features_0_1(daisy_chain_36_0_1), + .o_features_0_1(daisy_chain_37_0_1), + .i_features_0_2(daisy_chain_36_0_2), + .o_features_0_2(daisy_chain_37_0_2), + .i_features_0_3(daisy_chain_36_0_3), + .o_features_0_3(daisy_chain_37_0_3), + .i_features_0_4(daisy_chain_36_0_4), + .o_features_0_4(daisy_chain_37_0_4), + .i_features_0_5(daisy_chain_36_0_5), + .o_features_0_5(daisy_chain_37_0_5), + .i_features_1_0(daisy_chain_36_1_0), + .o_features_1_0(daisy_chain_37_1_0), + .i_features_1_1(daisy_chain_36_1_1), + .o_features_1_1(daisy_chain_37_1_1), + .i_features_1_2(daisy_chain_36_1_2), + .o_features_1_2(daisy_chain_37_1_2), + .i_features_1_3(daisy_chain_36_1_3), + .o_features_1_3(daisy_chain_37_1_3), + .i_features_1_4(daisy_chain_36_1_4), + .o_features_1_4(daisy_chain_37_1_4), + .i_features_1_5(daisy_chain_36_1_5), + .o_features_1_5(daisy_chain_37_1_5), + .i_features_2_0(daisy_chain_36_2_0), + .o_features_2_0(daisy_chain_37_2_0), + .i_features_2_1(daisy_chain_36_2_1), + .o_features_2_1(daisy_chain_37_2_1), + .i_features_2_2(daisy_chain_36_2_2), + .o_features_2_2(daisy_chain_37_2_2), + .i_features_2_3(daisy_chain_36_2_3), + .o_features_2_3(daisy_chain_37_2_3), + .i_features_2_4(daisy_chain_36_2_4), + .o_features_2_4(daisy_chain_37_2_4), + .i_features_2_5(daisy_chain_36_2_5), + .o_features_2_5(daisy_chain_37_2_5), + .i_features_3_0(daisy_chain_36_3_0), + .o_features_3_0(daisy_chain_37_3_0), + .i_features_3_1(daisy_chain_36_3_1), + .o_features_3_1(daisy_chain_37_3_1), + .i_features_3_2(daisy_chain_36_3_2), + .o_features_3_2(daisy_chain_37_3_2), + .i_features_3_3(daisy_chain_36_3_3), + .o_features_3_3(daisy_chain_37_3_3), + .i_features_3_4(daisy_chain_36_3_4), + .o_features_3_4(daisy_chain_37_3_4), + .i_features_3_5(daisy_chain_36_3_5), + .o_features_3_5(daisy_chain_37_3_5), + .i_features_4_0(daisy_chain_36_4_0), + .o_features_4_0(daisy_chain_37_4_0), + .i_features_4_1(daisy_chain_36_4_1), + .o_features_4_1(daisy_chain_37_4_1), + .i_features_4_2(daisy_chain_36_4_2), + .o_features_4_2(daisy_chain_37_4_2), + .i_features_4_3(daisy_chain_36_4_3), + .o_features_4_3(daisy_chain_37_4_3), + .i_features_4_4(daisy_chain_36_4_4), + .o_features_4_4(daisy_chain_37_4_4), + .i_features_4_5(daisy_chain_36_4_5), + .o_features_4_5(daisy_chain_37_4_5), + .i_features_5_0(daisy_chain_36_5_0), + .o_features_5_0(daisy_chain_37_5_0), + .i_features_5_1(daisy_chain_36_5_1), + .o_features_5_1(daisy_chain_37_5_1), + .i_features_5_2(daisy_chain_36_5_2), + .o_features_5_2(daisy_chain_37_5_2), + .i_features_5_3(daisy_chain_36_5_3), + .o_features_5_3(daisy_chain_37_5_3), + .i_features_5_4(daisy_chain_36_5_4), + .o_features_5_4(daisy_chain_37_5_4), + .i_features_5_5(daisy_chain_36_5_5), + .o_features_5_5(daisy_chain_37_5_5), + .i_features_6_0(daisy_chain_36_6_0), + .o_features_6_0(daisy_chain_37_6_0), + .i_features_6_1(daisy_chain_36_6_1), + .o_features_6_1(daisy_chain_37_6_1), + .i_features_6_2(daisy_chain_36_6_2), + .o_features_6_2(daisy_chain_37_6_2), + .i_features_6_3(daisy_chain_36_6_3), + .o_features_6_3(daisy_chain_37_6_3), + .i_features_6_4(daisy_chain_36_6_4), + .o_features_6_4(daisy_chain_37_6_4), + .i_features_6_5(daisy_chain_36_6_5), + .o_features_6_5(daisy_chain_37_6_5), + .i_features_7_0(daisy_chain_36_7_0), + .o_features_7_0(daisy_chain_37_7_0), + .i_features_7_1(daisy_chain_36_7_1), + .o_features_7_1(daisy_chain_37_7_1), + .i_features_7_2(daisy_chain_36_7_2), + .o_features_7_2(daisy_chain_37_7_2), + .i_features_7_3(daisy_chain_36_7_3), + .o_features_7_3(daisy_chain_37_7_3), + .i_features_7_4(daisy_chain_36_7_4), + .o_features_7_4(daisy_chain_37_7_4), + .i_features_7_5(daisy_chain_36_7_5), + .o_features_7_5(daisy_chain_37_7_5), + .o_result_0(PE_output_37_0), + .o_result_1(PE_output_37_1), + .o_result_2(PE_output_37_2), + .o_result_3(PE_output_37_3), + .o_result_4(PE_output_37_4), + .o_result_5(PE_output_37_5), + .o_valid(PE_valid_37), + .o_next_reset(PE_next_reset_37), + .o_next_valid(PE_next_valid_37) +); + +processing_element processing_element_inst_38 ( + .clk(clk), + .i_reset(PE_next_reset_37), + .i_valid(PE_next_valid_37), + .i_features_0_0(daisy_chain_37_0_0), + .o_features_0_0(daisy_chain_38_0_0), + .i_features_0_1(daisy_chain_37_0_1), + .o_features_0_1(daisy_chain_38_0_1), + .i_features_0_2(daisy_chain_37_0_2), + .o_features_0_2(daisy_chain_38_0_2), + .i_features_0_3(daisy_chain_37_0_3), + .o_features_0_3(daisy_chain_38_0_3), + .i_features_0_4(daisy_chain_37_0_4), + .o_features_0_4(daisy_chain_38_0_4), + .i_features_0_5(daisy_chain_37_0_5), + .o_features_0_5(daisy_chain_38_0_5), + .i_features_1_0(daisy_chain_37_1_0), + .o_features_1_0(daisy_chain_38_1_0), + .i_features_1_1(daisy_chain_37_1_1), + .o_features_1_1(daisy_chain_38_1_1), + .i_features_1_2(daisy_chain_37_1_2), + .o_features_1_2(daisy_chain_38_1_2), + .i_features_1_3(daisy_chain_37_1_3), + .o_features_1_3(daisy_chain_38_1_3), + .i_features_1_4(daisy_chain_37_1_4), + .o_features_1_4(daisy_chain_38_1_4), + .i_features_1_5(daisy_chain_37_1_5), + .o_features_1_5(daisy_chain_38_1_5), + .i_features_2_0(daisy_chain_37_2_0), + .o_features_2_0(daisy_chain_38_2_0), + .i_features_2_1(daisy_chain_37_2_1), + .o_features_2_1(daisy_chain_38_2_1), + .i_features_2_2(daisy_chain_37_2_2), + .o_features_2_2(daisy_chain_38_2_2), + .i_features_2_3(daisy_chain_37_2_3), + .o_features_2_3(daisy_chain_38_2_3), + .i_features_2_4(daisy_chain_37_2_4), + .o_features_2_4(daisy_chain_38_2_4), + .i_features_2_5(daisy_chain_37_2_5), + .o_features_2_5(daisy_chain_38_2_5), + .i_features_3_0(daisy_chain_37_3_0), + .o_features_3_0(daisy_chain_38_3_0), + .i_features_3_1(daisy_chain_37_3_1), + .o_features_3_1(daisy_chain_38_3_1), + .i_features_3_2(daisy_chain_37_3_2), + .o_features_3_2(daisy_chain_38_3_2), + .i_features_3_3(daisy_chain_37_3_3), + .o_features_3_3(daisy_chain_38_3_3), + .i_features_3_4(daisy_chain_37_3_4), + .o_features_3_4(daisy_chain_38_3_4), + .i_features_3_5(daisy_chain_37_3_5), + .o_features_3_5(daisy_chain_38_3_5), + .i_features_4_0(daisy_chain_37_4_0), + .o_features_4_0(daisy_chain_38_4_0), + .i_features_4_1(daisy_chain_37_4_1), + .o_features_4_1(daisy_chain_38_4_1), + .i_features_4_2(daisy_chain_37_4_2), + .o_features_4_2(daisy_chain_38_4_2), + .i_features_4_3(daisy_chain_37_4_3), + .o_features_4_3(daisy_chain_38_4_3), + .i_features_4_4(daisy_chain_37_4_4), + .o_features_4_4(daisy_chain_38_4_4), + .i_features_4_5(daisy_chain_37_4_5), + .o_features_4_5(daisy_chain_38_4_5), + .i_features_5_0(daisy_chain_37_5_0), + .o_features_5_0(daisy_chain_38_5_0), + .i_features_5_1(daisy_chain_37_5_1), + .o_features_5_1(daisy_chain_38_5_1), + .i_features_5_2(daisy_chain_37_5_2), + .o_features_5_2(daisy_chain_38_5_2), + .i_features_5_3(daisy_chain_37_5_3), + .o_features_5_3(daisy_chain_38_5_3), + .i_features_5_4(daisy_chain_37_5_4), + .o_features_5_4(daisy_chain_38_5_4), + .i_features_5_5(daisy_chain_37_5_5), + .o_features_5_5(daisy_chain_38_5_5), + .i_features_6_0(daisy_chain_37_6_0), + .o_features_6_0(daisy_chain_38_6_0), + .i_features_6_1(daisy_chain_37_6_1), + .o_features_6_1(daisy_chain_38_6_1), + .i_features_6_2(daisy_chain_37_6_2), + .o_features_6_2(daisy_chain_38_6_2), + .i_features_6_3(daisy_chain_37_6_3), + .o_features_6_3(daisy_chain_38_6_3), + .i_features_6_4(daisy_chain_37_6_4), + .o_features_6_4(daisy_chain_38_6_4), + .i_features_6_5(daisy_chain_37_6_5), + .o_features_6_5(daisy_chain_38_6_5), + .i_features_7_0(daisy_chain_37_7_0), + .o_features_7_0(daisy_chain_38_7_0), + .i_features_7_1(daisy_chain_37_7_1), + .o_features_7_1(daisy_chain_38_7_1), + .i_features_7_2(daisy_chain_37_7_2), + .o_features_7_2(daisy_chain_38_7_2), + .i_features_7_3(daisy_chain_37_7_3), + .o_features_7_3(daisy_chain_38_7_3), + .i_features_7_4(daisy_chain_37_7_4), + .o_features_7_4(daisy_chain_38_7_4), + .i_features_7_5(daisy_chain_37_7_5), + .o_features_7_5(daisy_chain_38_7_5), + .o_result_0(PE_output_38_0), + .o_result_1(PE_output_38_1), + .o_result_2(PE_output_38_2), + .o_result_3(PE_output_38_3), + .o_result_4(PE_output_38_4), + .o_result_5(PE_output_38_5), + .o_valid(PE_valid_38), + .o_next_reset(PE_next_reset_38), + .o_next_valid(PE_next_valid_38) +); + +processing_element processing_element_inst_39 ( + .clk(clk), + .i_reset(PE_next_reset_38), + .i_valid(PE_next_valid_38), + .i_features_0_0(daisy_chain_38_0_0), + .o_features_0_0(daisy_chain_39_0_0), + .i_features_0_1(daisy_chain_38_0_1), + .o_features_0_1(daisy_chain_39_0_1), + .i_features_0_2(daisy_chain_38_0_2), + .o_features_0_2(daisy_chain_39_0_2), + .i_features_0_3(daisy_chain_38_0_3), + .o_features_0_3(daisy_chain_39_0_3), + .i_features_0_4(daisy_chain_38_0_4), + .o_features_0_4(daisy_chain_39_0_4), + .i_features_0_5(daisy_chain_38_0_5), + .o_features_0_5(daisy_chain_39_0_5), + .i_features_1_0(daisy_chain_38_1_0), + .o_features_1_0(daisy_chain_39_1_0), + .i_features_1_1(daisy_chain_38_1_1), + .o_features_1_1(daisy_chain_39_1_1), + .i_features_1_2(daisy_chain_38_1_2), + .o_features_1_2(daisy_chain_39_1_2), + .i_features_1_3(daisy_chain_38_1_3), + .o_features_1_3(daisy_chain_39_1_3), + .i_features_1_4(daisy_chain_38_1_4), + .o_features_1_4(daisy_chain_39_1_4), + .i_features_1_5(daisy_chain_38_1_5), + .o_features_1_5(daisy_chain_39_1_5), + .i_features_2_0(daisy_chain_38_2_0), + .o_features_2_0(daisy_chain_39_2_0), + .i_features_2_1(daisy_chain_38_2_1), + .o_features_2_1(daisy_chain_39_2_1), + .i_features_2_2(daisy_chain_38_2_2), + .o_features_2_2(daisy_chain_39_2_2), + .i_features_2_3(daisy_chain_38_2_3), + .o_features_2_3(daisy_chain_39_2_3), + .i_features_2_4(daisy_chain_38_2_4), + .o_features_2_4(daisy_chain_39_2_4), + .i_features_2_5(daisy_chain_38_2_5), + .o_features_2_5(daisy_chain_39_2_5), + .i_features_3_0(daisy_chain_38_3_0), + .o_features_3_0(daisy_chain_39_3_0), + .i_features_3_1(daisy_chain_38_3_1), + .o_features_3_1(daisy_chain_39_3_1), + .i_features_3_2(daisy_chain_38_3_2), + .o_features_3_2(daisy_chain_39_3_2), + .i_features_3_3(daisy_chain_38_3_3), + .o_features_3_3(daisy_chain_39_3_3), + .i_features_3_4(daisy_chain_38_3_4), + .o_features_3_4(daisy_chain_39_3_4), + .i_features_3_5(daisy_chain_38_3_5), + .o_features_3_5(daisy_chain_39_3_5), + .i_features_4_0(daisy_chain_38_4_0), + .o_features_4_0(daisy_chain_39_4_0), + .i_features_4_1(daisy_chain_38_4_1), + .o_features_4_1(daisy_chain_39_4_1), + .i_features_4_2(daisy_chain_38_4_2), + .o_features_4_2(daisy_chain_39_4_2), + .i_features_4_3(daisy_chain_38_4_3), + .o_features_4_3(daisy_chain_39_4_3), + .i_features_4_4(daisy_chain_38_4_4), + .o_features_4_4(daisy_chain_39_4_4), + .i_features_4_5(daisy_chain_38_4_5), + .o_features_4_5(daisy_chain_39_4_5), + .i_features_5_0(daisy_chain_38_5_0), + .o_features_5_0(daisy_chain_39_5_0), + .i_features_5_1(daisy_chain_38_5_1), + .o_features_5_1(daisy_chain_39_5_1), + .i_features_5_2(daisy_chain_38_5_2), + .o_features_5_2(daisy_chain_39_5_2), + .i_features_5_3(daisy_chain_38_5_3), + .o_features_5_3(daisy_chain_39_5_3), + .i_features_5_4(daisy_chain_38_5_4), + .o_features_5_4(daisy_chain_39_5_4), + .i_features_5_5(daisy_chain_38_5_5), + .o_features_5_5(daisy_chain_39_5_5), + .i_features_6_0(daisy_chain_38_6_0), + .o_features_6_0(daisy_chain_39_6_0), + .i_features_6_1(daisy_chain_38_6_1), + .o_features_6_1(daisy_chain_39_6_1), + .i_features_6_2(daisy_chain_38_6_2), + .o_features_6_2(daisy_chain_39_6_2), + .i_features_6_3(daisy_chain_38_6_3), + .o_features_6_3(daisy_chain_39_6_3), + .i_features_6_4(daisy_chain_38_6_4), + .o_features_6_4(daisy_chain_39_6_4), + .i_features_6_5(daisy_chain_38_6_5), + .o_features_6_5(daisy_chain_39_6_5), + .i_features_7_0(daisy_chain_38_7_0), + .o_features_7_0(daisy_chain_39_7_0), + .i_features_7_1(daisy_chain_38_7_1), + .o_features_7_1(daisy_chain_39_7_1), + .i_features_7_2(daisy_chain_38_7_2), + .o_features_7_2(daisy_chain_39_7_2), + .i_features_7_3(daisy_chain_38_7_3), + .o_features_7_3(daisy_chain_39_7_3), + .i_features_7_4(daisy_chain_38_7_4), + .o_features_7_4(daisy_chain_39_7_4), + .i_features_7_5(daisy_chain_38_7_5), + .o_features_7_5(daisy_chain_39_7_5), + .o_result_0(PE_output_39_0), + .o_result_1(PE_output_39_1), + .o_result_2(PE_output_39_2), + .o_result_3(PE_output_39_3), + .o_result_4(PE_output_39_4), + .o_result_5(PE_output_39_5), + .o_valid(PE_valid_39), + .o_next_reset(PE_next_reset_39), + .o_next_valid(PE_next_valid_39) +); + +processing_element processing_element_inst_40 ( + .clk(clk), + .i_reset(PE_next_reset_39), + .i_valid(PE_next_valid_39), + .i_features_0_0(daisy_chain_39_0_0), + .o_features_0_0(daisy_chain_40_0_0), + .i_features_0_1(daisy_chain_39_0_1), + .o_features_0_1(daisy_chain_40_0_1), + .i_features_0_2(daisy_chain_39_0_2), + .o_features_0_2(daisy_chain_40_0_2), + .i_features_0_3(daisy_chain_39_0_3), + .o_features_0_3(daisy_chain_40_0_3), + .i_features_0_4(daisy_chain_39_0_4), + .o_features_0_4(daisy_chain_40_0_4), + .i_features_0_5(daisy_chain_39_0_5), + .o_features_0_5(daisy_chain_40_0_5), + .i_features_1_0(daisy_chain_39_1_0), + .o_features_1_0(daisy_chain_40_1_0), + .i_features_1_1(daisy_chain_39_1_1), + .o_features_1_1(daisy_chain_40_1_1), + .i_features_1_2(daisy_chain_39_1_2), + .o_features_1_2(daisy_chain_40_1_2), + .i_features_1_3(daisy_chain_39_1_3), + .o_features_1_3(daisy_chain_40_1_3), + .i_features_1_4(daisy_chain_39_1_4), + .o_features_1_4(daisy_chain_40_1_4), + .i_features_1_5(daisy_chain_39_1_5), + .o_features_1_5(daisy_chain_40_1_5), + .i_features_2_0(daisy_chain_39_2_0), + .o_features_2_0(daisy_chain_40_2_0), + .i_features_2_1(daisy_chain_39_2_1), + .o_features_2_1(daisy_chain_40_2_1), + .i_features_2_2(daisy_chain_39_2_2), + .o_features_2_2(daisy_chain_40_2_2), + .i_features_2_3(daisy_chain_39_2_3), + .o_features_2_3(daisy_chain_40_2_3), + .i_features_2_4(daisy_chain_39_2_4), + .o_features_2_4(daisy_chain_40_2_4), + .i_features_2_5(daisy_chain_39_2_5), + .o_features_2_5(daisy_chain_40_2_5), + .i_features_3_0(daisy_chain_39_3_0), + .o_features_3_0(daisy_chain_40_3_0), + .i_features_3_1(daisy_chain_39_3_1), + .o_features_3_1(daisy_chain_40_3_1), + .i_features_3_2(daisy_chain_39_3_2), + .o_features_3_2(daisy_chain_40_3_2), + .i_features_3_3(daisy_chain_39_3_3), + .o_features_3_3(daisy_chain_40_3_3), + .i_features_3_4(daisy_chain_39_3_4), + .o_features_3_4(daisy_chain_40_3_4), + .i_features_3_5(daisy_chain_39_3_5), + .o_features_3_5(daisy_chain_40_3_5), + .i_features_4_0(daisy_chain_39_4_0), + .o_features_4_0(daisy_chain_40_4_0), + .i_features_4_1(daisy_chain_39_4_1), + .o_features_4_1(daisy_chain_40_4_1), + .i_features_4_2(daisy_chain_39_4_2), + .o_features_4_2(daisy_chain_40_4_2), + .i_features_4_3(daisy_chain_39_4_3), + .o_features_4_3(daisy_chain_40_4_3), + .i_features_4_4(daisy_chain_39_4_4), + .o_features_4_4(daisy_chain_40_4_4), + .i_features_4_5(daisy_chain_39_4_5), + .o_features_4_5(daisy_chain_40_4_5), + .i_features_5_0(daisy_chain_39_5_0), + .o_features_5_0(daisy_chain_40_5_0), + .i_features_5_1(daisy_chain_39_5_1), + .o_features_5_1(daisy_chain_40_5_1), + .i_features_5_2(daisy_chain_39_5_2), + .o_features_5_2(daisy_chain_40_5_2), + .i_features_5_3(daisy_chain_39_5_3), + .o_features_5_3(daisy_chain_40_5_3), + .i_features_5_4(daisy_chain_39_5_4), + .o_features_5_4(daisy_chain_40_5_4), + .i_features_5_5(daisy_chain_39_5_5), + .o_features_5_5(daisy_chain_40_5_5), + .i_features_6_0(daisy_chain_39_6_0), + .o_features_6_0(daisy_chain_40_6_0), + .i_features_6_1(daisy_chain_39_6_1), + .o_features_6_1(daisy_chain_40_6_1), + .i_features_6_2(daisy_chain_39_6_2), + .o_features_6_2(daisy_chain_40_6_2), + .i_features_6_3(daisy_chain_39_6_3), + .o_features_6_3(daisy_chain_40_6_3), + .i_features_6_4(daisy_chain_39_6_4), + .o_features_6_4(daisy_chain_40_6_4), + .i_features_6_5(daisy_chain_39_6_5), + .o_features_6_5(daisy_chain_40_6_5), + .i_features_7_0(daisy_chain_39_7_0), + .o_features_7_0(daisy_chain_40_7_0), + .i_features_7_1(daisy_chain_39_7_1), + .o_features_7_1(daisy_chain_40_7_1), + .i_features_7_2(daisy_chain_39_7_2), + .o_features_7_2(daisy_chain_40_7_2), + .i_features_7_3(daisy_chain_39_7_3), + .o_features_7_3(daisy_chain_40_7_3), + .i_features_7_4(daisy_chain_39_7_4), + .o_features_7_4(daisy_chain_40_7_4), + .i_features_7_5(daisy_chain_39_7_5), + .o_features_7_5(daisy_chain_40_7_5), + .o_result_0(PE_output_40_0), + .o_result_1(PE_output_40_1), + .o_result_2(PE_output_40_2), + .o_result_3(PE_output_40_3), + .o_result_4(PE_output_40_4), + .o_result_5(PE_output_40_5), + .o_valid(PE_valid_40), + .o_next_reset(PE_next_reset_40), + .o_next_valid(PE_next_valid_40) +); + +processing_element processing_element_inst_41 ( + .clk(clk), + .i_reset(PE_next_reset_40), + .i_valid(PE_next_valid_40), + .i_features_0_0(daisy_chain_40_0_0), + .o_features_0_0(daisy_chain_41_0_0), + .i_features_0_1(daisy_chain_40_0_1), + .o_features_0_1(daisy_chain_41_0_1), + .i_features_0_2(daisy_chain_40_0_2), + .o_features_0_2(daisy_chain_41_0_2), + .i_features_0_3(daisy_chain_40_0_3), + .o_features_0_3(daisy_chain_41_0_3), + .i_features_0_4(daisy_chain_40_0_4), + .o_features_0_4(daisy_chain_41_0_4), + .i_features_0_5(daisy_chain_40_0_5), + .o_features_0_5(daisy_chain_41_0_5), + .i_features_1_0(daisy_chain_40_1_0), + .o_features_1_0(daisy_chain_41_1_0), + .i_features_1_1(daisy_chain_40_1_1), + .o_features_1_1(daisy_chain_41_1_1), + .i_features_1_2(daisy_chain_40_1_2), + .o_features_1_2(daisy_chain_41_1_2), + .i_features_1_3(daisy_chain_40_1_3), + .o_features_1_3(daisy_chain_41_1_3), + .i_features_1_4(daisy_chain_40_1_4), + .o_features_1_4(daisy_chain_41_1_4), + .i_features_1_5(daisy_chain_40_1_5), + .o_features_1_5(daisy_chain_41_1_5), + .i_features_2_0(daisy_chain_40_2_0), + .o_features_2_0(daisy_chain_41_2_0), + .i_features_2_1(daisy_chain_40_2_1), + .o_features_2_1(daisy_chain_41_2_1), + .i_features_2_2(daisy_chain_40_2_2), + .o_features_2_2(daisy_chain_41_2_2), + .i_features_2_3(daisy_chain_40_2_3), + .o_features_2_3(daisy_chain_41_2_3), + .i_features_2_4(daisy_chain_40_2_4), + .o_features_2_4(daisy_chain_41_2_4), + .i_features_2_5(daisy_chain_40_2_5), + .o_features_2_5(daisy_chain_41_2_5), + .i_features_3_0(daisy_chain_40_3_0), + .o_features_3_0(daisy_chain_41_3_0), + .i_features_3_1(daisy_chain_40_3_1), + .o_features_3_1(daisy_chain_41_3_1), + .i_features_3_2(daisy_chain_40_3_2), + .o_features_3_2(daisy_chain_41_3_2), + .i_features_3_3(daisy_chain_40_3_3), + .o_features_3_3(daisy_chain_41_3_3), + .i_features_3_4(daisy_chain_40_3_4), + .o_features_3_4(daisy_chain_41_3_4), + .i_features_3_5(daisy_chain_40_3_5), + .o_features_3_5(daisy_chain_41_3_5), + .i_features_4_0(daisy_chain_40_4_0), + .o_features_4_0(daisy_chain_41_4_0), + .i_features_4_1(daisy_chain_40_4_1), + .o_features_4_1(daisy_chain_41_4_1), + .i_features_4_2(daisy_chain_40_4_2), + .o_features_4_2(daisy_chain_41_4_2), + .i_features_4_3(daisy_chain_40_4_3), + .o_features_4_3(daisy_chain_41_4_3), + .i_features_4_4(daisy_chain_40_4_4), + .o_features_4_4(daisy_chain_41_4_4), + .i_features_4_5(daisy_chain_40_4_5), + .o_features_4_5(daisy_chain_41_4_5), + .i_features_5_0(daisy_chain_40_5_0), + .o_features_5_0(daisy_chain_41_5_0), + .i_features_5_1(daisy_chain_40_5_1), + .o_features_5_1(daisy_chain_41_5_1), + .i_features_5_2(daisy_chain_40_5_2), + .o_features_5_2(daisy_chain_41_5_2), + .i_features_5_3(daisy_chain_40_5_3), + .o_features_5_3(daisy_chain_41_5_3), + .i_features_5_4(daisy_chain_40_5_4), + .o_features_5_4(daisy_chain_41_5_4), + .i_features_5_5(daisy_chain_40_5_5), + .o_features_5_5(daisy_chain_41_5_5), + .i_features_6_0(daisy_chain_40_6_0), + .o_features_6_0(daisy_chain_41_6_0), + .i_features_6_1(daisy_chain_40_6_1), + .o_features_6_1(daisy_chain_41_6_1), + .i_features_6_2(daisy_chain_40_6_2), + .o_features_6_2(daisy_chain_41_6_2), + .i_features_6_3(daisy_chain_40_6_3), + .o_features_6_3(daisy_chain_41_6_3), + .i_features_6_4(daisy_chain_40_6_4), + .o_features_6_4(daisy_chain_41_6_4), + .i_features_6_5(daisy_chain_40_6_5), + .o_features_6_5(daisy_chain_41_6_5), + .i_features_7_0(daisy_chain_40_7_0), + .o_features_7_0(daisy_chain_41_7_0), + .i_features_7_1(daisy_chain_40_7_1), + .o_features_7_1(daisy_chain_41_7_1), + .i_features_7_2(daisy_chain_40_7_2), + .o_features_7_2(daisy_chain_41_7_2), + .i_features_7_3(daisy_chain_40_7_3), + .o_features_7_3(daisy_chain_41_7_3), + .i_features_7_4(daisy_chain_40_7_4), + .o_features_7_4(daisy_chain_41_7_4), + .i_features_7_5(daisy_chain_40_7_5), + .o_features_7_5(daisy_chain_41_7_5), + .o_result_0(PE_output_41_0), + .o_result_1(PE_output_41_1), + .o_result_2(PE_output_41_2), + .o_result_3(PE_output_41_3), + .o_result_4(PE_output_41_4), + .o_result_5(PE_output_41_5), + .o_valid(PE_valid_41), + .o_next_reset(PE_next_reset_41), + .o_next_valid(PE_next_valid_41) +); + +processing_element processing_element_inst_42 ( + .clk(clk), + .i_reset(PE_next_reset_41), + .i_valid(PE_next_valid_41), + .i_features_0_0(daisy_chain_41_0_0), + .o_features_0_0(daisy_chain_42_0_0), + .i_features_0_1(daisy_chain_41_0_1), + .o_features_0_1(daisy_chain_42_0_1), + .i_features_0_2(daisy_chain_41_0_2), + .o_features_0_2(daisy_chain_42_0_2), + .i_features_0_3(daisy_chain_41_0_3), + .o_features_0_3(daisy_chain_42_0_3), + .i_features_0_4(daisy_chain_41_0_4), + .o_features_0_4(daisy_chain_42_0_4), + .i_features_0_5(daisy_chain_41_0_5), + .o_features_0_5(daisy_chain_42_0_5), + .i_features_1_0(daisy_chain_41_1_0), + .o_features_1_0(daisy_chain_42_1_0), + .i_features_1_1(daisy_chain_41_1_1), + .o_features_1_1(daisy_chain_42_1_1), + .i_features_1_2(daisy_chain_41_1_2), + .o_features_1_2(daisy_chain_42_1_2), + .i_features_1_3(daisy_chain_41_1_3), + .o_features_1_3(daisy_chain_42_1_3), + .i_features_1_4(daisy_chain_41_1_4), + .o_features_1_4(daisy_chain_42_1_4), + .i_features_1_5(daisy_chain_41_1_5), + .o_features_1_5(daisy_chain_42_1_5), + .i_features_2_0(daisy_chain_41_2_0), + .o_features_2_0(daisy_chain_42_2_0), + .i_features_2_1(daisy_chain_41_2_1), + .o_features_2_1(daisy_chain_42_2_1), + .i_features_2_2(daisy_chain_41_2_2), + .o_features_2_2(daisy_chain_42_2_2), + .i_features_2_3(daisy_chain_41_2_3), + .o_features_2_3(daisy_chain_42_2_3), + .i_features_2_4(daisy_chain_41_2_4), + .o_features_2_4(daisy_chain_42_2_4), + .i_features_2_5(daisy_chain_41_2_5), + .o_features_2_5(daisy_chain_42_2_5), + .i_features_3_0(daisy_chain_41_3_0), + .o_features_3_0(daisy_chain_42_3_0), + .i_features_3_1(daisy_chain_41_3_1), + .o_features_3_1(daisy_chain_42_3_1), + .i_features_3_2(daisy_chain_41_3_2), + .o_features_3_2(daisy_chain_42_3_2), + .i_features_3_3(daisy_chain_41_3_3), + .o_features_3_3(daisy_chain_42_3_3), + .i_features_3_4(daisy_chain_41_3_4), + .o_features_3_4(daisy_chain_42_3_4), + .i_features_3_5(daisy_chain_41_3_5), + .o_features_3_5(daisy_chain_42_3_5), + .i_features_4_0(daisy_chain_41_4_0), + .o_features_4_0(daisy_chain_42_4_0), + .i_features_4_1(daisy_chain_41_4_1), + .o_features_4_1(daisy_chain_42_4_1), + .i_features_4_2(daisy_chain_41_4_2), + .o_features_4_2(daisy_chain_42_4_2), + .i_features_4_3(daisy_chain_41_4_3), + .o_features_4_3(daisy_chain_42_4_3), + .i_features_4_4(daisy_chain_41_4_4), + .o_features_4_4(daisy_chain_42_4_4), + .i_features_4_5(daisy_chain_41_4_5), + .o_features_4_5(daisy_chain_42_4_5), + .i_features_5_0(daisy_chain_41_5_0), + .o_features_5_0(daisy_chain_42_5_0), + .i_features_5_1(daisy_chain_41_5_1), + .o_features_5_1(daisy_chain_42_5_1), + .i_features_5_2(daisy_chain_41_5_2), + .o_features_5_2(daisy_chain_42_5_2), + .i_features_5_3(daisy_chain_41_5_3), + .o_features_5_3(daisy_chain_42_5_3), + .i_features_5_4(daisy_chain_41_5_4), + .o_features_5_4(daisy_chain_42_5_4), + .i_features_5_5(daisy_chain_41_5_5), + .o_features_5_5(daisy_chain_42_5_5), + .i_features_6_0(daisy_chain_41_6_0), + .o_features_6_0(daisy_chain_42_6_0), + .i_features_6_1(daisy_chain_41_6_1), + .o_features_6_1(daisy_chain_42_6_1), + .i_features_6_2(daisy_chain_41_6_2), + .o_features_6_2(daisy_chain_42_6_2), + .i_features_6_3(daisy_chain_41_6_3), + .o_features_6_3(daisy_chain_42_6_3), + .i_features_6_4(daisy_chain_41_6_4), + .o_features_6_4(daisy_chain_42_6_4), + .i_features_6_5(daisy_chain_41_6_5), + .o_features_6_5(daisy_chain_42_6_5), + .i_features_7_0(daisy_chain_41_7_0), + .o_features_7_0(daisy_chain_42_7_0), + .i_features_7_1(daisy_chain_41_7_1), + .o_features_7_1(daisy_chain_42_7_1), + .i_features_7_2(daisy_chain_41_7_2), + .o_features_7_2(daisy_chain_42_7_2), + .i_features_7_3(daisy_chain_41_7_3), + .o_features_7_3(daisy_chain_42_7_3), + .i_features_7_4(daisy_chain_41_7_4), + .o_features_7_4(daisy_chain_42_7_4), + .i_features_7_5(daisy_chain_41_7_5), + .o_features_7_5(daisy_chain_42_7_5), + .o_result_0(PE_output_42_0), + .o_result_1(PE_output_42_1), + .o_result_2(PE_output_42_2), + .o_result_3(PE_output_42_3), + .o_result_4(PE_output_42_4), + .o_result_5(PE_output_42_5), + .o_valid(PE_valid_42), + .o_next_reset(PE_next_reset_42), + .o_next_valid(PE_next_valid_42) +); + +processing_element processing_element_inst_43 ( + .clk(clk), + .i_reset(PE_next_reset_42), + .i_valid(PE_next_valid_42), + .i_features_0_0(daisy_chain_42_0_0), + .o_features_0_0(daisy_chain_43_0_0), + .i_features_0_1(daisy_chain_42_0_1), + .o_features_0_1(daisy_chain_43_0_1), + .i_features_0_2(daisy_chain_42_0_2), + .o_features_0_2(daisy_chain_43_0_2), + .i_features_0_3(daisy_chain_42_0_3), + .o_features_0_3(daisy_chain_43_0_3), + .i_features_0_4(daisy_chain_42_0_4), + .o_features_0_4(daisy_chain_43_0_4), + .i_features_0_5(daisy_chain_42_0_5), + .o_features_0_5(daisy_chain_43_0_5), + .i_features_1_0(daisy_chain_42_1_0), + .o_features_1_0(daisy_chain_43_1_0), + .i_features_1_1(daisy_chain_42_1_1), + .o_features_1_1(daisy_chain_43_1_1), + .i_features_1_2(daisy_chain_42_1_2), + .o_features_1_2(daisy_chain_43_1_2), + .i_features_1_3(daisy_chain_42_1_3), + .o_features_1_3(daisy_chain_43_1_3), + .i_features_1_4(daisy_chain_42_1_4), + .o_features_1_4(daisy_chain_43_1_4), + .i_features_1_5(daisy_chain_42_1_5), + .o_features_1_5(daisy_chain_43_1_5), + .i_features_2_0(daisy_chain_42_2_0), + .o_features_2_0(daisy_chain_43_2_0), + .i_features_2_1(daisy_chain_42_2_1), + .o_features_2_1(daisy_chain_43_2_1), + .i_features_2_2(daisy_chain_42_2_2), + .o_features_2_2(daisy_chain_43_2_2), + .i_features_2_3(daisy_chain_42_2_3), + .o_features_2_3(daisy_chain_43_2_3), + .i_features_2_4(daisy_chain_42_2_4), + .o_features_2_4(daisy_chain_43_2_4), + .i_features_2_5(daisy_chain_42_2_5), + .o_features_2_5(daisy_chain_43_2_5), + .i_features_3_0(daisy_chain_42_3_0), + .o_features_3_0(daisy_chain_43_3_0), + .i_features_3_1(daisy_chain_42_3_1), + .o_features_3_1(daisy_chain_43_3_1), + .i_features_3_2(daisy_chain_42_3_2), + .o_features_3_2(daisy_chain_43_3_2), + .i_features_3_3(daisy_chain_42_3_3), + .o_features_3_3(daisy_chain_43_3_3), + .i_features_3_4(daisy_chain_42_3_4), + .o_features_3_4(daisy_chain_43_3_4), + .i_features_3_5(daisy_chain_42_3_5), + .o_features_3_5(daisy_chain_43_3_5), + .i_features_4_0(daisy_chain_42_4_0), + .o_features_4_0(daisy_chain_43_4_0), + .i_features_4_1(daisy_chain_42_4_1), + .o_features_4_1(daisy_chain_43_4_1), + .i_features_4_2(daisy_chain_42_4_2), + .o_features_4_2(daisy_chain_43_4_2), + .i_features_4_3(daisy_chain_42_4_3), + .o_features_4_3(daisy_chain_43_4_3), + .i_features_4_4(daisy_chain_42_4_4), + .o_features_4_4(daisy_chain_43_4_4), + .i_features_4_5(daisy_chain_42_4_5), + .o_features_4_5(daisy_chain_43_4_5), + .i_features_5_0(daisy_chain_42_5_0), + .o_features_5_0(daisy_chain_43_5_0), + .i_features_5_1(daisy_chain_42_5_1), + .o_features_5_1(daisy_chain_43_5_1), + .i_features_5_2(daisy_chain_42_5_2), + .o_features_5_2(daisy_chain_43_5_2), + .i_features_5_3(daisy_chain_42_5_3), + .o_features_5_3(daisy_chain_43_5_3), + .i_features_5_4(daisy_chain_42_5_4), + .o_features_5_4(daisy_chain_43_5_4), + .i_features_5_5(daisy_chain_42_5_5), + .o_features_5_5(daisy_chain_43_5_5), + .i_features_6_0(daisy_chain_42_6_0), + .o_features_6_0(daisy_chain_43_6_0), + .i_features_6_1(daisy_chain_42_6_1), + .o_features_6_1(daisy_chain_43_6_1), + .i_features_6_2(daisy_chain_42_6_2), + .o_features_6_2(daisy_chain_43_6_2), + .i_features_6_3(daisy_chain_42_6_3), + .o_features_6_3(daisy_chain_43_6_3), + .i_features_6_4(daisy_chain_42_6_4), + .o_features_6_4(daisy_chain_43_6_4), + .i_features_6_5(daisy_chain_42_6_5), + .o_features_6_5(daisy_chain_43_6_5), + .i_features_7_0(daisy_chain_42_7_0), + .o_features_7_0(daisy_chain_43_7_0), + .i_features_7_1(daisy_chain_42_7_1), + .o_features_7_1(daisy_chain_43_7_1), + .i_features_7_2(daisy_chain_42_7_2), + .o_features_7_2(daisy_chain_43_7_2), + .i_features_7_3(daisy_chain_42_7_3), + .o_features_7_3(daisy_chain_43_7_3), + .i_features_7_4(daisy_chain_42_7_4), + .o_features_7_4(daisy_chain_43_7_4), + .i_features_7_5(daisy_chain_42_7_5), + .o_features_7_5(daisy_chain_43_7_5), + .o_result_0(PE_output_43_0), + .o_result_1(PE_output_43_1), + .o_result_2(PE_output_43_2), + .o_result_3(PE_output_43_3), + .o_result_4(PE_output_43_4), + .o_result_5(PE_output_43_5), + .o_valid(PE_valid_43), + .o_next_reset(PE_next_reset_43), + .o_next_valid(PE_next_valid_43) +); + +processing_element processing_element_inst_44 ( + .clk(clk), + .i_reset(PE_next_reset_43), + .i_valid(PE_next_valid_43), + .i_features_0_0(daisy_chain_43_0_0), + .o_features_0_0(daisy_chain_44_0_0), + .i_features_0_1(daisy_chain_43_0_1), + .o_features_0_1(daisy_chain_44_0_1), + .i_features_0_2(daisy_chain_43_0_2), + .o_features_0_2(daisy_chain_44_0_2), + .i_features_0_3(daisy_chain_43_0_3), + .o_features_0_3(daisy_chain_44_0_3), + .i_features_0_4(daisy_chain_43_0_4), + .o_features_0_4(daisy_chain_44_0_4), + .i_features_0_5(daisy_chain_43_0_5), + .o_features_0_5(daisy_chain_44_0_5), + .i_features_1_0(daisy_chain_43_1_0), + .o_features_1_0(daisy_chain_44_1_0), + .i_features_1_1(daisy_chain_43_1_1), + .o_features_1_1(daisy_chain_44_1_1), + .i_features_1_2(daisy_chain_43_1_2), + .o_features_1_2(daisy_chain_44_1_2), + .i_features_1_3(daisy_chain_43_1_3), + .o_features_1_3(daisy_chain_44_1_3), + .i_features_1_4(daisy_chain_43_1_4), + .o_features_1_4(daisy_chain_44_1_4), + .i_features_1_5(daisy_chain_43_1_5), + .o_features_1_5(daisy_chain_44_1_5), + .i_features_2_0(daisy_chain_43_2_0), + .o_features_2_0(daisy_chain_44_2_0), + .i_features_2_1(daisy_chain_43_2_1), + .o_features_2_1(daisy_chain_44_2_1), + .i_features_2_2(daisy_chain_43_2_2), + .o_features_2_2(daisy_chain_44_2_2), + .i_features_2_3(daisy_chain_43_2_3), + .o_features_2_3(daisy_chain_44_2_3), + .i_features_2_4(daisy_chain_43_2_4), + .o_features_2_4(daisy_chain_44_2_4), + .i_features_2_5(daisy_chain_43_2_5), + .o_features_2_5(daisy_chain_44_2_5), + .i_features_3_0(daisy_chain_43_3_0), + .o_features_3_0(daisy_chain_44_3_0), + .i_features_3_1(daisy_chain_43_3_1), + .o_features_3_1(daisy_chain_44_3_1), + .i_features_3_2(daisy_chain_43_3_2), + .o_features_3_2(daisy_chain_44_3_2), + .i_features_3_3(daisy_chain_43_3_3), + .o_features_3_3(daisy_chain_44_3_3), + .i_features_3_4(daisy_chain_43_3_4), + .o_features_3_4(daisy_chain_44_3_4), + .i_features_3_5(daisy_chain_43_3_5), + .o_features_3_5(daisy_chain_44_3_5), + .i_features_4_0(daisy_chain_43_4_0), + .o_features_4_0(daisy_chain_44_4_0), + .i_features_4_1(daisy_chain_43_4_1), + .o_features_4_1(daisy_chain_44_4_1), + .i_features_4_2(daisy_chain_43_4_2), + .o_features_4_2(daisy_chain_44_4_2), + .i_features_4_3(daisy_chain_43_4_3), + .o_features_4_3(daisy_chain_44_4_3), + .i_features_4_4(daisy_chain_43_4_4), + .o_features_4_4(daisy_chain_44_4_4), + .i_features_4_5(daisy_chain_43_4_5), + .o_features_4_5(daisy_chain_44_4_5), + .i_features_5_0(daisy_chain_43_5_0), + .o_features_5_0(daisy_chain_44_5_0), + .i_features_5_1(daisy_chain_43_5_1), + .o_features_5_1(daisy_chain_44_5_1), + .i_features_5_2(daisy_chain_43_5_2), + .o_features_5_2(daisy_chain_44_5_2), + .i_features_5_3(daisy_chain_43_5_3), + .o_features_5_3(daisy_chain_44_5_3), + .i_features_5_4(daisy_chain_43_5_4), + .o_features_5_4(daisy_chain_44_5_4), + .i_features_5_5(daisy_chain_43_5_5), + .o_features_5_5(daisy_chain_44_5_5), + .i_features_6_0(daisy_chain_43_6_0), + .o_features_6_0(daisy_chain_44_6_0), + .i_features_6_1(daisy_chain_43_6_1), + .o_features_6_1(daisy_chain_44_6_1), + .i_features_6_2(daisy_chain_43_6_2), + .o_features_6_2(daisy_chain_44_6_2), + .i_features_6_3(daisy_chain_43_6_3), + .o_features_6_3(daisy_chain_44_6_3), + .i_features_6_4(daisy_chain_43_6_4), + .o_features_6_4(daisy_chain_44_6_4), + .i_features_6_5(daisy_chain_43_6_5), + .o_features_6_5(daisy_chain_44_6_5), + .i_features_7_0(daisy_chain_43_7_0), + .o_features_7_0(daisy_chain_44_7_0), + .i_features_7_1(daisy_chain_43_7_1), + .o_features_7_1(daisy_chain_44_7_1), + .i_features_7_2(daisy_chain_43_7_2), + .o_features_7_2(daisy_chain_44_7_2), + .i_features_7_3(daisy_chain_43_7_3), + .o_features_7_3(daisy_chain_44_7_3), + .i_features_7_4(daisy_chain_43_7_4), + .o_features_7_4(daisy_chain_44_7_4), + .i_features_7_5(daisy_chain_43_7_5), + .o_features_7_5(daisy_chain_44_7_5), + .o_result_0(PE_output_44_0), + .o_result_1(PE_output_44_1), + .o_result_2(PE_output_44_2), + .o_result_3(PE_output_44_3), + .o_result_4(PE_output_44_4), + .o_result_5(PE_output_44_5), + .o_valid(PE_valid_44), + .o_next_reset(PE_next_reset_44), + .o_next_valid(PE_next_valid_44) +); + +processing_element processing_element_inst_45 ( + .clk(clk), + .i_reset(PE_next_reset_44), + .i_valid(PE_next_valid_44), + .i_features_0_0(daisy_chain_44_0_0), + .o_features_0_0(daisy_chain_45_0_0), + .i_features_0_1(daisy_chain_44_0_1), + .o_features_0_1(daisy_chain_45_0_1), + .i_features_0_2(daisy_chain_44_0_2), + .o_features_0_2(daisy_chain_45_0_2), + .i_features_0_3(daisy_chain_44_0_3), + .o_features_0_3(daisy_chain_45_0_3), + .i_features_0_4(daisy_chain_44_0_4), + .o_features_0_4(daisy_chain_45_0_4), + .i_features_0_5(daisy_chain_44_0_5), + .o_features_0_5(daisy_chain_45_0_5), + .i_features_1_0(daisy_chain_44_1_0), + .o_features_1_0(daisy_chain_45_1_0), + .i_features_1_1(daisy_chain_44_1_1), + .o_features_1_1(daisy_chain_45_1_1), + .i_features_1_2(daisy_chain_44_1_2), + .o_features_1_2(daisy_chain_45_1_2), + .i_features_1_3(daisy_chain_44_1_3), + .o_features_1_3(daisy_chain_45_1_3), + .i_features_1_4(daisy_chain_44_1_4), + .o_features_1_4(daisy_chain_45_1_4), + .i_features_1_5(daisy_chain_44_1_5), + .o_features_1_5(daisy_chain_45_1_5), + .i_features_2_0(daisy_chain_44_2_0), + .o_features_2_0(daisy_chain_45_2_0), + .i_features_2_1(daisy_chain_44_2_1), + .o_features_2_1(daisy_chain_45_2_1), + .i_features_2_2(daisy_chain_44_2_2), + .o_features_2_2(daisy_chain_45_2_2), + .i_features_2_3(daisy_chain_44_2_3), + .o_features_2_3(daisy_chain_45_2_3), + .i_features_2_4(daisy_chain_44_2_4), + .o_features_2_4(daisy_chain_45_2_4), + .i_features_2_5(daisy_chain_44_2_5), + .o_features_2_5(daisy_chain_45_2_5), + .i_features_3_0(daisy_chain_44_3_0), + .o_features_3_0(daisy_chain_45_3_0), + .i_features_3_1(daisy_chain_44_3_1), + .o_features_3_1(daisy_chain_45_3_1), + .i_features_3_2(daisy_chain_44_3_2), + .o_features_3_2(daisy_chain_45_3_2), + .i_features_3_3(daisy_chain_44_3_3), + .o_features_3_3(daisy_chain_45_3_3), + .i_features_3_4(daisy_chain_44_3_4), + .o_features_3_4(daisy_chain_45_3_4), + .i_features_3_5(daisy_chain_44_3_5), + .o_features_3_5(daisy_chain_45_3_5), + .i_features_4_0(daisy_chain_44_4_0), + .o_features_4_0(daisy_chain_45_4_0), + .i_features_4_1(daisy_chain_44_4_1), + .o_features_4_1(daisy_chain_45_4_1), + .i_features_4_2(daisy_chain_44_4_2), + .o_features_4_2(daisy_chain_45_4_2), + .i_features_4_3(daisy_chain_44_4_3), + .o_features_4_3(daisy_chain_45_4_3), + .i_features_4_4(daisy_chain_44_4_4), + .o_features_4_4(daisy_chain_45_4_4), + .i_features_4_5(daisy_chain_44_4_5), + .o_features_4_5(daisy_chain_45_4_5), + .i_features_5_0(daisy_chain_44_5_0), + .o_features_5_0(daisy_chain_45_5_0), + .i_features_5_1(daisy_chain_44_5_1), + .o_features_5_1(daisy_chain_45_5_1), + .i_features_5_2(daisy_chain_44_5_2), + .o_features_5_2(daisy_chain_45_5_2), + .i_features_5_3(daisy_chain_44_5_3), + .o_features_5_3(daisy_chain_45_5_3), + .i_features_5_4(daisy_chain_44_5_4), + .o_features_5_4(daisy_chain_45_5_4), + .i_features_5_5(daisy_chain_44_5_5), + .o_features_5_5(daisy_chain_45_5_5), + .i_features_6_0(daisy_chain_44_6_0), + .o_features_6_0(daisy_chain_45_6_0), + .i_features_6_1(daisy_chain_44_6_1), + .o_features_6_1(daisy_chain_45_6_1), + .i_features_6_2(daisy_chain_44_6_2), + .o_features_6_2(daisy_chain_45_6_2), + .i_features_6_3(daisy_chain_44_6_3), + .o_features_6_3(daisy_chain_45_6_3), + .i_features_6_4(daisy_chain_44_6_4), + .o_features_6_4(daisy_chain_45_6_4), + .i_features_6_5(daisy_chain_44_6_5), + .o_features_6_5(daisy_chain_45_6_5), + .i_features_7_0(daisy_chain_44_7_0), + .o_features_7_0(daisy_chain_45_7_0), + .i_features_7_1(daisy_chain_44_7_1), + .o_features_7_1(daisy_chain_45_7_1), + .i_features_7_2(daisy_chain_44_7_2), + .o_features_7_2(daisy_chain_45_7_2), + .i_features_7_3(daisy_chain_44_7_3), + .o_features_7_3(daisy_chain_45_7_3), + .i_features_7_4(daisy_chain_44_7_4), + .o_features_7_4(daisy_chain_45_7_4), + .i_features_7_5(daisy_chain_44_7_5), + .o_features_7_5(daisy_chain_45_7_5), + .o_result_0(PE_output_45_0), + .o_result_1(PE_output_45_1), + .o_result_2(PE_output_45_2), + .o_result_3(PE_output_45_3), + .o_result_4(PE_output_45_4), + .o_result_5(PE_output_45_5), + .o_valid(PE_valid_45), + .o_next_reset(PE_next_reset_45), + .o_next_valid(PE_next_valid_45) +); + +processing_element processing_element_inst_46 ( + .clk(clk), + .i_reset(PE_next_reset_45), + .i_valid(PE_next_valid_45), + .i_features_0_0(daisy_chain_45_0_0), + .o_features_0_0(daisy_chain_46_0_0), + .i_features_0_1(daisy_chain_45_0_1), + .o_features_0_1(daisy_chain_46_0_1), + .i_features_0_2(daisy_chain_45_0_2), + .o_features_0_2(daisy_chain_46_0_2), + .i_features_0_3(daisy_chain_45_0_3), + .o_features_0_3(daisy_chain_46_0_3), + .i_features_0_4(daisy_chain_45_0_4), + .o_features_0_4(daisy_chain_46_0_4), + .i_features_0_5(daisy_chain_45_0_5), + .o_features_0_5(daisy_chain_46_0_5), + .i_features_1_0(daisy_chain_45_1_0), + .o_features_1_0(daisy_chain_46_1_0), + .i_features_1_1(daisy_chain_45_1_1), + .o_features_1_1(daisy_chain_46_1_1), + .i_features_1_2(daisy_chain_45_1_2), + .o_features_1_2(daisy_chain_46_1_2), + .i_features_1_3(daisy_chain_45_1_3), + .o_features_1_3(daisy_chain_46_1_3), + .i_features_1_4(daisy_chain_45_1_4), + .o_features_1_4(daisy_chain_46_1_4), + .i_features_1_5(daisy_chain_45_1_5), + .o_features_1_5(daisy_chain_46_1_5), + .i_features_2_0(daisy_chain_45_2_0), + .o_features_2_0(daisy_chain_46_2_0), + .i_features_2_1(daisy_chain_45_2_1), + .o_features_2_1(daisy_chain_46_2_1), + .i_features_2_2(daisy_chain_45_2_2), + .o_features_2_2(daisy_chain_46_2_2), + .i_features_2_3(daisy_chain_45_2_3), + .o_features_2_3(daisy_chain_46_2_3), + .i_features_2_4(daisy_chain_45_2_4), + .o_features_2_4(daisy_chain_46_2_4), + .i_features_2_5(daisy_chain_45_2_5), + .o_features_2_5(daisy_chain_46_2_5), + .i_features_3_0(daisy_chain_45_3_0), + .o_features_3_0(daisy_chain_46_3_0), + .i_features_3_1(daisy_chain_45_3_1), + .o_features_3_1(daisy_chain_46_3_1), + .i_features_3_2(daisy_chain_45_3_2), + .o_features_3_2(daisy_chain_46_3_2), + .i_features_3_3(daisy_chain_45_3_3), + .o_features_3_3(daisy_chain_46_3_3), + .i_features_3_4(daisy_chain_45_3_4), + .o_features_3_4(daisy_chain_46_3_4), + .i_features_3_5(daisy_chain_45_3_5), + .o_features_3_5(daisy_chain_46_3_5), + .i_features_4_0(daisy_chain_45_4_0), + .o_features_4_0(daisy_chain_46_4_0), + .i_features_4_1(daisy_chain_45_4_1), + .o_features_4_1(daisy_chain_46_4_1), + .i_features_4_2(daisy_chain_45_4_2), + .o_features_4_2(daisy_chain_46_4_2), + .i_features_4_3(daisy_chain_45_4_3), + .o_features_4_3(daisy_chain_46_4_3), + .i_features_4_4(daisy_chain_45_4_4), + .o_features_4_4(daisy_chain_46_4_4), + .i_features_4_5(daisy_chain_45_4_5), + .o_features_4_5(daisy_chain_46_4_5), + .i_features_5_0(daisy_chain_45_5_0), + .o_features_5_0(daisy_chain_46_5_0), + .i_features_5_1(daisy_chain_45_5_1), + .o_features_5_1(daisy_chain_46_5_1), + .i_features_5_2(daisy_chain_45_5_2), + .o_features_5_2(daisy_chain_46_5_2), + .i_features_5_3(daisy_chain_45_5_3), + .o_features_5_3(daisy_chain_46_5_3), + .i_features_5_4(daisy_chain_45_5_4), + .o_features_5_4(daisy_chain_46_5_4), + .i_features_5_5(daisy_chain_45_5_5), + .o_features_5_5(daisy_chain_46_5_5), + .i_features_6_0(daisy_chain_45_6_0), + .o_features_6_0(daisy_chain_46_6_0), + .i_features_6_1(daisy_chain_45_6_1), + .o_features_6_1(daisy_chain_46_6_1), + .i_features_6_2(daisy_chain_45_6_2), + .o_features_6_2(daisy_chain_46_6_2), + .i_features_6_3(daisy_chain_45_6_3), + .o_features_6_3(daisy_chain_46_6_3), + .i_features_6_4(daisy_chain_45_6_4), + .o_features_6_4(daisy_chain_46_6_4), + .i_features_6_5(daisy_chain_45_6_5), + .o_features_6_5(daisy_chain_46_6_5), + .i_features_7_0(daisy_chain_45_7_0), + .o_features_7_0(daisy_chain_46_7_0), + .i_features_7_1(daisy_chain_45_7_1), + .o_features_7_1(daisy_chain_46_7_1), + .i_features_7_2(daisy_chain_45_7_2), + .o_features_7_2(daisy_chain_46_7_2), + .i_features_7_3(daisy_chain_45_7_3), + .o_features_7_3(daisy_chain_46_7_3), + .i_features_7_4(daisy_chain_45_7_4), + .o_features_7_4(daisy_chain_46_7_4), + .i_features_7_5(daisy_chain_45_7_5), + .o_features_7_5(daisy_chain_46_7_5), + .o_result_0(PE_output_46_0), + .o_result_1(PE_output_46_1), + .o_result_2(PE_output_46_2), + .o_result_3(PE_output_46_3), + .o_result_4(PE_output_46_4), + .o_result_5(PE_output_46_5), + .o_valid(PE_valid_46), + .o_next_reset(PE_next_reset_46), + .o_next_valid(PE_next_valid_46) +); + +processing_element processing_element_inst_47 ( + .clk(clk), + .i_reset(PE_next_reset_46), + .i_valid(PE_next_valid_46), + .i_features_0_0(daisy_chain_46_0_0), + .o_features_0_0(daisy_chain_47_0_0), + .i_features_0_1(daisy_chain_46_0_1), + .o_features_0_1(daisy_chain_47_0_1), + .i_features_0_2(daisy_chain_46_0_2), + .o_features_0_2(daisy_chain_47_0_2), + .i_features_0_3(daisy_chain_46_0_3), + .o_features_0_3(daisy_chain_47_0_3), + .i_features_0_4(daisy_chain_46_0_4), + .o_features_0_4(daisy_chain_47_0_4), + .i_features_0_5(daisy_chain_46_0_5), + .o_features_0_5(daisy_chain_47_0_5), + .i_features_1_0(daisy_chain_46_1_0), + .o_features_1_0(daisy_chain_47_1_0), + .i_features_1_1(daisy_chain_46_1_1), + .o_features_1_1(daisy_chain_47_1_1), + .i_features_1_2(daisy_chain_46_1_2), + .o_features_1_2(daisy_chain_47_1_2), + .i_features_1_3(daisy_chain_46_1_3), + .o_features_1_3(daisy_chain_47_1_3), + .i_features_1_4(daisy_chain_46_1_4), + .o_features_1_4(daisy_chain_47_1_4), + .i_features_1_5(daisy_chain_46_1_5), + .o_features_1_5(daisy_chain_47_1_5), + .i_features_2_0(daisy_chain_46_2_0), + .o_features_2_0(daisy_chain_47_2_0), + .i_features_2_1(daisy_chain_46_2_1), + .o_features_2_1(daisy_chain_47_2_1), + .i_features_2_2(daisy_chain_46_2_2), + .o_features_2_2(daisy_chain_47_2_2), + .i_features_2_3(daisy_chain_46_2_3), + .o_features_2_3(daisy_chain_47_2_3), + .i_features_2_4(daisy_chain_46_2_4), + .o_features_2_4(daisy_chain_47_2_4), + .i_features_2_5(daisy_chain_46_2_5), + .o_features_2_5(daisy_chain_47_2_5), + .i_features_3_0(daisy_chain_46_3_0), + .o_features_3_0(daisy_chain_47_3_0), + .i_features_3_1(daisy_chain_46_3_1), + .o_features_3_1(daisy_chain_47_3_1), + .i_features_3_2(daisy_chain_46_3_2), + .o_features_3_2(daisy_chain_47_3_2), + .i_features_3_3(daisy_chain_46_3_3), + .o_features_3_3(daisy_chain_47_3_3), + .i_features_3_4(daisy_chain_46_3_4), + .o_features_3_4(daisy_chain_47_3_4), + .i_features_3_5(daisy_chain_46_3_5), + .o_features_3_5(daisy_chain_47_3_5), + .i_features_4_0(daisy_chain_46_4_0), + .o_features_4_0(daisy_chain_47_4_0), + .i_features_4_1(daisy_chain_46_4_1), + .o_features_4_1(daisy_chain_47_4_1), + .i_features_4_2(daisy_chain_46_4_2), + .o_features_4_2(daisy_chain_47_4_2), + .i_features_4_3(daisy_chain_46_4_3), + .o_features_4_3(daisy_chain_47_4_3), + .i_features_4_4(daisy_chain_46_4_4), + .o_features_4_4(daisy_chain_47_4_4), + .i_features_4_5(daisy_chain_46_4_5), + .o_features_4_5(daisy_chain_47_4_5), + .i_features_5_0(daisy_chain_46_5_0), + .o_features_5_0(daisy_chain_47_5_0), + .i_features_5_1(daisy_chain_46_5_1), + .o_features_5_1(daisy_chain_47_5_1), + .i_features_5_2(daisy_chain_46_5_2), + .o_features_5_2(daisy_chain_47_5_2), + .i_features_5_3(daisy_chain_46_5_3), + .o_features_5_3(daisy_chain_47_5_3), + .i_features_5_4(daisy_chain_46_5_4), + .o_features_5_4(daisy_chain_47_5_4), + .i_features_5_5(daisy_chain_46_5_5), + .o_features_5_5(daisy_chain_47_5_5), + .i_features_6_0(daisy_chain_46_6_0), + .o_features_6_0(daisy_chain_47_6_0), + .i_features_6_1(daisy_chain_46_6_1), + .o_features_6_1(daisy_chain_47_6_1), + .i_features_6_2(daisy_chain_46_6_2), + .o_features_6_2(daisy_chain_47_6_2), + .i_features_6_3(daisy_chain_46_6_3), + .o_features_6_3(daisy_chain_47_6_3), + .i_features_6_4(daisy_chain_46_6_4), + .o_features_6_4(daisy_chain_47_6_4), + .i_features_6_5(daisy_chain_46_6_5), + .o_features_6_5(daisy_chain_47_6_5), + .i_features_7_0(daisy_chain_46_7_0), + .o_features_7_0(daisy_chain_47_7_0), + .i_features_7_1(daisy_chain_46_7_1), + .o_features_7_1(daisy_chain_47_7_1), + .i_features_7_2(daisy_chain_46_7_2), + .o_features_7_2(daisy_chain_47_7_2), + .i_features_7_3(daisy_chain_46_7_3), + .o_features_7_3(daisy_chain_47_7_3), + .i_features_7_4(daisy_chain_46_7_4), + .o_features_7_4(daisy_chain_47_7_4), + .i_features_7_5(daisy_chain_46_7_5), + .o_features_7_5(daisy_chain_47_7_5), + .o_result_0(PE_output_47_0), + .o_result_1(PE_output_47_1), + .o_result_2(PE_output_47_2), + .o_result_3(PE_output_47_3), + .o_result_4(PE_output_47_4), + .o_result_5(PE_output_47_5), + .o_valid(PE_valid_47), + .o_next_reset(PE_next_reset_47), + .o_next_valid(PE_next_valid_47) +); + +inverse_winograd_0 inverse_winograd_0_inst ( + .clk(clk), + .i_valid(PE_valid_0), + .i_result_0(PE_output_0_0), + .i_result_1(PE_output_0_1), + .i_result_2(PE_output_0_2), + .i_result_3(PE_output_0_3), + .i_result_4(PE_output_0_4), + .i_result_5(PE_output_0_5), + .o_result_0(INV_output_0_0), + .o_result_1(INV_output_0_1), + .o_result_2(INV_output_0_2), + .o_result_3(INV_output_0_3), + .o_valid(INV_valid_0) +); + +inverse_winograd_1 inverse_winograd_1_inst ( + .clk(clk), + .i_valid(PE_valid_1), + .i_result_0(PE_output_1_0), + .i_result_1(PE_output_1_1), + .i_result_2(PE_output_1_2), + .i_result_3(PE_output_1_3), + .i_result_4(PE_output_1_4), + .i_result_5(PE_output_1_5), + .o_result_0(INV_output_1_0), + .o_result_1(INV_output_1_1), + .o_result_2(INV_output_1_2), + .o_result_3(INV_output_1_3), + .o_valid(INV_valid_1) +); + +inverse_winograd_2 inverse_winograd_2_inst ( + .clk(clk), + .i_valid(PE_valid_2), + .i_result_0(PE_output_2_0), + .i_result_1(PE_output_2_1), + .i_result_2(PE_output_2_2), + .i_result_3(PE_output_2_3), + .i_result_4(PE_output_2_4), + .i_result_5(PE_output_2_5), + .o_result_0(INV_output_2_0), + .o_result_1(INV_output_2_1), + .o_result_2(INV_output_2_2), + .o_result_3(INV_output_2_3), + .o_valid(INV_valid_2) +); + +inverse_winograd_3 inverse_winograd_3_inst ( + .clk(clk), + .i_valid(PE_valid_3), + .i_result_0(PE_output_3_0), + .i_result_1(PE_output_3_1), + .i_result_2(PE_output_3_2), + .i_result_3(PE_output_3_3), + .i_result_4(PE_output_3_4), + .i_result_5(PE_output_3_5), + .o_result_0(INV_output_3_0), + .o_result_1(INV_output_3_1), + .o_result_2(INV_output_3_2), + .o_result_3(INV_output_3_3), + .o_valid(INV_valid_3) +); + +inverse_winograd_4 inverse_winograd_4_inst ( + .clk(clk), + .i_valid(PE_valid_4), + .i_result_0(PE_output_4_0), + .i_result_1(PE_output_4_1), + .i_result_2(PE_output_4_2), + .i_result_3(PE_output_4_3), + .i_result_4(PE_output_4_4), + .i_result_5(PE_output_4_5), + .o_result_0(INV_output_4_0), + .o_result_1(INV_output_4_1), + .o_result_2(INV_output_4_2), + .o_result_3(INV_output_4_3), + .o_valid(INV_valid_4) +); + +inverse_winograd_5 inverse_winograd_5_inst ( + .clk(clk), + .i_valid(PE_valid_5), + .i_result_0(PE_output_5_0), + .i_result_1(PE_output_5_1), + .i_result_2(PE_output_5_2), + .i_result_3(PE_output_5_3), + .i_result_4(PE_output_5_4), + .i_result_5(PE_output_5_5), + .o_result_0(INV_output_5_0), + .o_result_1(INV_output_5_1), + .o_result_2(INV_output_5_2), + .o_result_3(INV_output_5_3), + .o_valid(INV_valid_5) +); + +inverse_winograd_6 inverse_winograd_6_inst ( + .clk(clk), + .i_valid(PE_valid_6), + .i_result_0(PE_output_6_0), + .i_result_1(PE_output_6_1), + .i_result_2(PE_output_6_2), + .i_result_3(PE_output_6_3), + .i_result_4(PE_output_6_4), + .i_result_5(PE_output_6_5), + .o_result_0(INV_output_6_0), + .o_result_1(INV_output_6_1), + .o_result_2(INV_output_6_2), + .o_result_3(INV_output_6_3), + .o_valid(INV_valid_6) +); + +inverse_winograd_7 inverse_winograd_7_inst ( + .clk(clk), + .i_valid(PE_valid_7), + .i_result_0(PE_output_7_0), + .i_result_1(PE_output_7_1), + .i_result_2(PE_output_7_2), + .i_result_3(PE_output_7_3), + .i_result_4(PE_output_7_4), + .i_result_5(PE_output_7_5), + .o_result_0(INV_output_7_0), + .o_result_1(INV_output_7_1), + .o_result_2(INV_output_7_2), + .o_result_3(INV_output_7_3), + .o_valid(INV_valid_7) +); + +inverse_winograd_8 inverse_winograd_8_inst ( + .clk(clk), + .i_valid(PE_valid_8), + .i_result_0(PE_output_8_0), + .i_result_1(PE_output_8_1), + .i_result_2(PE_output_8_2), + .i_result_3(PE_output_8_3), + .i_result_4(PE_output_8_4), + .i_result_5(PE_output_8_5), + .o_result_0(INV_output_8_0), + .o_result_1(INV_output_8_1), + .o_result_2(INV_output_8_2), + .o_result_3(INV_output_8_3), + .o_valid(INV_valid_8) +); + +inverse_winograd_9 inverse_winograd_9_inst ( + .clk(clk), + .i_valid(PE_valid_9), + .i_result_0(PE_output_9_0), + .i_result_1(PE_output_9_1), + .i_result_2(PE_output_9_2), + .i_result_3(PE_output_9_3), + .i_result_4(PE_output_9_4), + .i_result_5(PE_output_9_5), + .o_result_0(INV_output_9_0), + .o_result_1(INV_output_9_1), + .o_result_2(INV_output_9_2), + .o_result_3(INV_output_9_3), + .o_valid(INV_valid_9) +); + +inverse_winograd_10 inverse_winograd_10_inst ( + .clk(clk), + .i_valid(PE_valid_10), + .i_result_0(PE_output_10_0), + .i_result_1(PE_output_10_1), + .i_result_2(PE_output_10_2), + .i_result_3(PE_output_10_3), + .i_result_4(PE_output_10_4), + .i_result_5(PE_output_10_5), + .o_result_0(INV_output_10_0), + .o_result_1(INV_output_10_1), + .o_result_2(INV_output_10_2), + .o_result_3(INV_output_10_3), + .o_valid(INV_valid_10) +); + +inverse_winograd_11 inverse_winograd_11_inst ( + .clk(clk), + .i_valid(PE_valid_11), + .i_result_0(PE_output_11_0), + .i_result_1(PE_output_11_1), + .i_result_2(PE_output_11_2), + .i_result_3(PE_output_11_3), + .i_result_4(PE_output_11_4), + .i_result_5(PE_output_11_5), + .o_result_0(INV_output_11_0), + .o_result_1(INV_output_11_1), + .o_result_2(INV_output_11_2), + .o_result_3(INV_output_11_3), + .o_valid(INV_valid_11) +); + +inverse_winograd_12 inverse_winograd_12_inst ( + .clk(clk), + .i_valid(PE_valid_12), + .i_result_0(PE_output_12_0), + .i_result_1(PE_output_12_1), + .i_result_2(PE_output_12_2), + .i_result_3(PE_output_12_3), + .i_result_4(PE_output_12_4), + .i_result_5(PE_output_12_5), + .o_result_0(INV_output_12_0), + .o_result_1(INV_output_12_1), + .o_result_2(INV_output_12_2), + .o_result_3(INV_output_12_3), + .o_valid(INV_valid_12) +); + +inverse_winograd_13 inverse_winograd_13_inst ( + .clk(clk), + .i_valid(PE_valid_13), + .i_result_0(PE_output_13_0), + .i_result_1(PE_output_13_1), + .i_result_2(PE_output_13_2), + .i_result_3(PE_output_13_3), + .i_result_4(PE_output_13_4), + .i_result_5(PE_output_13_5), + .o_result_0(INV_output_13_0), + .o_result_1(INV_output_13_1), + .o_result_2(INV_output_13_2), + .o_result_3(INV_output_13_3), + .o_valid(INV_valid_13) +); + +inverse_winograd_14 inverse_winograd_14_inst ( + .clk(clk), + .i_valid(PE_valid_14), + .i_result_0(PE_output_14_0), + .i_result_1(PE_output_14_1), + .i_result_2(PE_output_14_2), + .i_result_3(PE_output_14_3), + .i_result_4(PE_output_14_4), + .i_result_5(PE_output_14_5), + .o_result_0(INV_output_14_0), + .o_result_1(INV_output_14_1), + .o_result_2(INV_output_14_2), + .o_result_3(INV_output_14_3), + .o_valid(INV_valid_14) +); + +inverse_winograd_15 inverse_winograd_15_inst ( + .clk(clk), + .i_valid(PE_valid_15), + .i_result_0(PE_output_15_0), + .i_result_1(PE_output_15_1), + .i_result_2(PE_output_15_2), + .i_result_3(PE_output_15_3), + .i_result_4(PE_output_15_4), + .i_result_5(PE_output_15_5), + .o_result_0(INV_output_15_0), + .o_result_1(INV_output_15_1), + .o_result_2(INV_output_15_2), + .o_result_3(INV_output_15_3), + .o_valid(INV_valid_15) +); + +inverse_winograd_16 inverse_winograd_16_inst ( + .clk(clk), + .i_valid(PE_valid_16), + .i_result_0(PE_output_16_0), + .i_result_1(PE_output_16_1), + .i_result_2(PE_output_16_2), + .i_result_3(PE_output_16_3), + .i_result_4(PE_output_16_4), + .i_result_5(PE_output_16_5), + .o_result_0(INV_output_16_0), + .o_result_1(INV_output_16_1), + .o_result_2(INV_output_16_2), + .o_result_3(INV_output_16_3), + .o_valid(INV_valid_16) +); + +inverse_winograd_17 inverse_winograd_17_inst ( + .clk(clk), + .i_valid(PE_valid_17), + .i_result_0(PE_output_17_0), + .i_result_1(PE_output_17_1), + .i_result_2(PE_output_17_2), + .i_result_3(PE_output_17_3), + .i_result_4(PE_output_17_4), + .i_result_5(PE_output_17_5), + .o_result_0(INV_output_17_0), + .o_result_1(INV_output_17_1), + .o_result_2(INV_output_17_2), + .o_result_3(INV_output_17_3), + .o_valid(INV_valid_17) +); + +inverse_winograd_18 inverse_winograd_18_inst ( + .clk(clk), + .i_valid(PE_valid_18), + .i_result_0(PE_output_18_0), + .i_result_1(PE_output_18_1), + .i_result_2(PE_output_18_2), + .i_result_3(PE_output_18_3), + .i_result_4(PE_output_18_4), + .i_result_5(PE_output_18_5), + .o_result_0(INV_output_18_0), + .o_result_1(INV_output_18_1), + .o_result_2(INV_output_18_2), + .o_result_3(INV_output_18_3), + .o_valid(INV_valid_18) +); + +inverse_winograd_19 inverse_winograd_19_inst ( + .clk(clk), + .i_valid(PE_valid_19), + .i_result_0(PE_output_19_0), + .i_result_1(PE_output_19_1), + .i_result_2(PE_output_19_2), + .i_result_3(PE_output_19_3), + .i_result_4(PE_output_19_4), + .i_result_5(PE_output_19_5), + .o_result_0(INV_output_19_0), + .o_result_1(INV_output_19_1), + .o_result_2(INV_output_19_2), + .o_result_3(INV_output_19_3), + .o_valid(INV_valid_19) +); + +inverse_winograd_20 inverse_winograd_20_inst ( + .clk(clk), + .i_valid(PE_valid_20), + .i_result_0(PE_output_20_0), + .i_result_1(PE_output_20_1), + .i_result_2(PE_output_20_2), + .i_result_3(PE_output_20_3), + .i_result_4(PE_output_20_4), + .i_result_5(PE_output_20_5), + .o_result_0(INV_output_20_0), + .o_result_1(INV_output_20_1), + .o_result_2(INV_output_20_2), + .o_result_3(INV_output_20_3), + .o_valid(INV_valid_20) +); + +inverse_winograd_21 inverse_winograd_21_inst ( + .clk(clk), + .i_valid(PE_valid_21), + .i_result_0(PE_output_21_0), + .i_result_1(PE_output_21_1), + .i_result_2(PE_output_21_2), + .i_result_3(PE_output_21_3), + .i_result_4(PE_output_21_4), + .i_result_5(PE_output_21_5), + .o_result_0(INV_output_21_0), + .o_result_1(INV_output_21_1), + .o_result_2(INV_output_21_2), + .o_result_3(INV_output_21_3), + .o_valid(INV_valid_21) +); + +inverse_winograd_22 inverse_winograd_22_inst ( + .clk(clk), + .i_valid(PE_valid_22), + .i_result_0(PE_output_22_0), + .i_result_1(PE_output_22_1), + .i_result_2(PE_output_22_2), + .i_result_3(PE_output_22_3), + .i_result_4(PE_output_22_4), + .i_result_5(PE_output_22_5), + .o_result_0(INV_output_22_0), + .o_result_1(INV_output_22_1), + .o_result_2(INV_output_22_2), + .o_result_3(INV_output_22_3), + .o_valid(INV_valid_22) +); + +inverse_winograd_23 inverse_winograd_23_inst ( + .clk(clk), + .i_valid(PE_valid_23), + .i_result_0(PE_output_23_0), + .i_result_1(PE_output_23_1), + .i_result_2(PE_output_23_2), + .i_result_3(PE_output_23_3), + .i_result_4(PE_output_23_4), + .i_result_5(PE_output_23_5), + .o_result_0(INV_output_23_0), + .o_result_1(INV_output_23_1), + .o_result_2(INV_output_23_2), + .o_result_3(INV_output_23_3), + .o_valid(INV_valid_23) +); + +inverse_winograd_24 inverse_winograd_24_inst ( + .clk(clk), + .i_valid(PE_valid_24), + .i_result_0(PE_output_24_0), + .i_result_1(PE_output_24_1), + .i_result_2(PE_output_24_2), + .i_result_3(PE_output_24_3), + .i_result_4(PE_output_24_4), + .i_result_5(PE_output_24_5), + .o_result_0(INV_output_24_0), + .o_result_1(INV_output_24_1), + .o_result_2(INV_output_24_2), + .o_result_3(INV_output_24_3), + .o_valid(INV_valid_24) +); + +inverse_winograd_25 inverse_winograd_25_inst ( + .clk(clk), + .i_valid(PE_valid_25), + .i_result_0(PE_output_25_0), + .i_result_1(PE_output_25_1), + .i_result_2(PE_output_25_2), + .i_result_3(PE_output_25_3), + .i_result_4(PE_output_25_4), + .i_result_5(PE_output_25_5), + .o_result_0(INV_output_25_0), + .o_result_1(INV_output_25_1), + .o_result_2(INV_output_25_2), + .o_result_3(INV_output_25_3), + .o_valid(INV_valid_25) +); + +inverse_winograd_26 inverse_winograd_26_inst ( + .clk(clk), + .i_valid(PE_valid_26), + .i_result_0(PE_output_26_0), + .i_result_1(PE_output_26_1), + .i_result_2(PE_output_26_2), + .i_result_3(PE_output_26_3), + .i_result_4(PE_output_26_4), + .i_result_5(PE_output_26_5), + .o_result_0(INV_output_26_0), + .o_result_1(INV_output_26_1), + .o_result_2(INV_output_26_2), + .o_result_3(INV_output_26_3), + .o_valid(INV_valid_26) +); + +inverse_winograd_27 inverse_winograd_27_inst ( + .clk(clk), + .i_valid(PE_valid_27), + .i_result_0(PE_output_27_0), + .i_result_1(PE_output_27_1), + .i_result_2(PE_output_27_2), + .i_result_3(PE_output_27_3), + .i_result_4(PE_output_27_4), + .i_result_5(PE_output_27_5), + .o_result_0(INV_output_27_0), + .o_result_1(INV_output_27_1), + .o_result_2(INV_output_27_2), + .o_result_3(INV_output_27_3), + .o_valid(INV_valid_27) +); + +inverse_winograd_28 inverse_winograd_28_inst ( + .clk(clk), + .i_valid(PE_valid_28), + .i_result_0(PE_output_28_0), + .i_result_1(PE_output_28_1), + .i_result_2(PE_output_28_2), + .i_result_3(PE_output_28_3), + .i_result_4(PE_output_28_4), + .i_result_5(PE_output_28_5), + .o_result_0(INV_output_28_0), + .o_result_1(INV_output_28_1), + .o_result_2(INV_output_28_2), + .o_result_3(INV_output_28_3), + .o_valid(INV_valid_28) +); + +inverse_winograd_29 inverse_winograd_29_inst ( + .clk(clk), + .i_valid(PE_valid_29), + .i_result_0(PE_output_29_0), + .i_result_1(PE_output_29_1), + .i_result_2(PE_output_29_2), + .i_result_3(PE_output_29_3), + .i_result_4(PE_output_29_4), + .i_result_5(PE_output_29_5), + .o_result_0(INV_output_29_0), + .o_result_1(INV_output_29_1), + .o_result_2(INV_output_29_2), + .o_result_3(INV_output_29_3), + .o_valid(INV_valid_29) +); + +inverse_winograd_30 inverse_winograd_30_inst ( + .clk(clk), + .i_valid(PE_valid_30), + .i_result_0(PE_output_30_0), + .i_result_1(PE_output_30_1), + .i_result_2(PE_output_30_2), + .i_result_3(PE_output_30_3), + .i_result_4(PE_output_30_4), + .i_result_5(PE_output_30_5), + .o_result_0(INV_output_30_0), + .o_result_1(INV_output_30_1), + .o_result_2(INV_output_30_2), + .o_result_3(INV_output_30_3), + .o_valid(INV_valid_30) +); + +inverse_winograd_31 inverse_winograd_31_inst ( + .clk(clk), + .i_valid(PE_valid_31), + .i_result_0(PE_output_31_0), + .i_result_1(PE_output_31_1), + .i_result_2(PE_output_31_2), + .i_result_3(PE_output_31_3), + .i_result_4(PE_output_31_4), + .i_result_5(PE_output_31_5), + .o_result_0(INV_output_31_0), + .o_result_1(INV_output_31_1), + .o_result_2(INV_output_31_2), + .o_result_3(INV_output_31_3), + .o_valid(INV_valid_31) +); + +inverse_winograd_32 inverse_winograd_32_inst ( + .clk(clk), + .i_valid(PE_valid_32), + .i_result_0(PE_output_32_0), + .i_result_1(PE_output_32_1), + .i_result_2(PE_output_32_2), + .i_result_3(PE_output_32_3), + .i_result_4(PE_output_32_4), + .i_result_5(PE_output_32_5), + .o_result_0(INV_output_32_0), + .o_result_1(INV_output_32_1), + .o_result_2(INV_output_32_2), + .o_result_3(INV_output_32_3), + .o_valid(INV_valid_32) +); + +inverse_winograd_33 inverse_winograd_33_inst ( + .clk(clk), + .i_valid(PE_valid_33), + .i_result_0(PE_output_33_0), + .i_result_1(PE_output_33_1), + .i_result_2(PE_output_33_2), + .i_result_3(PE_output_33_3), + .i_result_4(PE_output_33_4), + .i_result_5(PE_output_33_5), + .o_result_0(INV_output_33_0), + .o_result_1(INV_output_33_1), + .o_result_2(INV_output_33_2), + .o_result_3(INV_output_33_3), + .o_valid(INV_valid_33) +); + +inverse_winograd_34 inverse_winograd_34_inst ( + .clk(clk), + .i_valid(PE_valid_34), + .i_result_0(PE_output_34_0), + .i_result_1(PE_output_34_1), + .i_result_2(PE_output_34_2), + .i_result_3(PE_output_34_3), + .i_result_4(PE_output_34_4), + .i_result_5(PE_output_34_5), + .o_result_0(INV_output_34_0), + .o_result_1(INV_output_34_1), + .o_result_2(INV_output_34_2), + .o_result_3(INV_output_34_3), + .o_valid(INV_valid_34) +); + +inverse_winograd_35 inverse_winograd_35_inst ( + .clk(clk), + .i_valid(PE_valid_35), + .i_result_0(PE_output_35_0), + .i_result_1(PE_output_35_1), + .i_result_2(PE_output_35_2), + .i_result_3(PE_output_35_3), + .i_result_4(PE_output_35_4), + .i_result_5(PE_output_35_5), + .o_result_0(INV_output_35_0), + .o_result_1(INV_output_35_1), + .o_result_2(INV_output_35_2), + .o_result_3(INV_output_35_3), + .o_valid(INV_valid_35) +); + +inverse_winograd_36 inverse_winograd_36_inst ( + .clk(clk), + .i_valid(PE_valid_36), + .i_result_0(PE_output_36_0), + .i_result_1(PE_output_36_1), + .i_result_2(PE_output_36_2), + .i_result_3(PE_output_36_3), + .i_result_4(PE_output_36_4), + .i_result_5(PE_output_36_5), + .o_result_0(INV_output_36_0), + .o_result_1(INV_output_36_1), + .o_result_2(INV_output_36_2), + .o_result_3(INV_output_36_3), + .o_valid(INV_valid_36) +); + +inverse_winograd_37 inverse_winograd_37_inst ( + .clk(clk), + .i_valid(PE_valid_37), + .i_result_0(PE_output_37_0), + .i_result_1(PE_output_37_1), + .i_result_2(PE_output_37_2), + .i_result_3(PE_output_37_3), + .i_result_4(PE_output_37_4), + .i_result_5(PE_output_37_5), + .o_result_0(INV_output_37_0), + .o_result_1(INV_output_37_1), + .o_result_2(INV_output_37_2), + .o_result_3(INV_output_37_3), + .o_valid(INV_valid_37) +); + +inverse_winograd_38 inverse_winograd_38_inst ( + .clk(clk), + .i_valid(PE_valid_38), + .i_result_0(PE_output_38_0), + .i_result_1(PE_output_38_1), + .i_result_2(PE_output_38_2), + .i_result_3(PE_output_38_3), + .i_result_4(PE_output_38_4), + .i_result_5(PE_output_38_5), + .o_result_0(INV_output_38_0), + .o_result_1(INV_output_38_1), + .o_result_2(INV_output_38_2), + .o_result_3(INV_output_38_3), + .o_valid(INV_valid_38) +); + +inverse_winograd_39 inverse_winograd_39_inst ( + .clk(clk), + .i_valid(PE_valid_39), + .i_result_0(PE_output_39_0), + .i_result_1(PE_output_39_1), + .i_result_2(PE_output_39_2), + .i_result_3(PE_output_39_3), + .i_result_4(PE_output_39_4), + .i_result_5(PE_output_39_5), + .o_result_0(INV_output_39_0), + .o_result_1(INV_output_39_1), + .o_result_2(INV_output_39_2), + .o_result_3(INV_output_39_3), + .o_valid(INV_valid_39) +); + +inverse_winograd_40 inverse_winograd_40_inst ( + .clk(clk), + .i_valid(PE_valid_40), + .i_result_0(PE_output_40_0), + .i_result_1(PE_output_40_1), + .i_result_2(PE_output_40_2), + .i_result_3(PE_output_40_3), + .i_result_4(PE_output_40_4), + .i_result_5(PE_output_40_5), + .o_result_0(INV_output_40_0), + .o_result_1(INV_output_40_1), + .o_result_2(INV_output_40_2), + .o_result_3(INV_output_40_3), + .o_valid(INV_valid_40) +); + +inverse_winograd_41 inverse_winograd_41_inst ( + .clk(clk), + .i_valid(PE_valid_41), + .i_result_0(PE_output_41_0), + .i_result_1(PE_output_41_1), + .i_result_2(PE_output_41_2), + .i_result_3(PE_output_41_3), + .i_result_4(PE_output_41_4), + .i_result_5(PE_output_41_5), + .o_result_0(INV_output_41_0), + .o_result_1(INV_output_41_1), + .o_result_2(INV_output_41_2), + .o_result_3(INV_output_41_3), + .o_valid(INV_valid_41) +); + +inverse_winograd_42 inverse_winograd_42_inst ( + .clk(clk), + .i_valid(PE_valid_42), + .i_result_0(PE_output_42_0), + .i_result_1(PE_output_42_1), + .i_result_2(PE_output_42_2), + .i_result_3(PE_output_42_3), + .i_result_4(PE_output_42_4), + .i_result_5(PE_output_42_5), + .o_result_0(INV_output_42_0), + .o_result_1(INV_output_42_1), + .o_result_2(INV_output_42_2), + .o_result_3(INV_output_42_3), + .o_valid(INV_valid_42) +); + +inverse_winograd_43 inverse_winograd_43_inst ( + .clk(clk), + .i_valid(PE_valid_43), + .i_result_0(PE_output_43_0), + .i_result_1(PE_output_43_1), + .i_result_2(PE_output_43_2), + .i_result_3(PE_output_43_3), + .i_result_4(PE_output_43_4), + .i_result_5(PE_output_43_5), + .o_result_0(INV_output_43_0), + .o_result_1(INV_output_43_1), + .o_result_2(INV_output_43_2), + .o_result_3(INV_output_43_3), + .o_valid(INV_valid_43) +); + +inverse_winograd_44 inverse_winograd_44_inst ( + .clk(clk), + .i_valid(PE_valid_44), + .i_result_0(PE_output_44_0), + .i_result_1(PE_output_44_1), + .i_result_2(PE_output_44_2), + .i_result_3(PE_output_44_3), + .i_result_4(PE_output_44_4), + .i_result_5(PE_output_44_5), + .o_result_0(INV_output_44_0), + .o_result_1(INV_output_44_1), + .o_result_2(INV_output_44_2), + .o_result_3(INV_output_44_3), + .o_valid(INV_valid_44) +); + +inverse_winograd_45 inverse_winograd_45_inst ( + .clk(clk), + .i_valid(PE_valid_45), + .i_result_0(PE_output_45_0), + .i_result_1(PE_output_45_1), + .i_result_2(PE_output_45_2), + .i_result_3(PE_output_45_3), + .i_result_4(PE_output_45_4), + .i_result_5(PE_output_45_5), + .o_result_0(INV_output_45_0), + .o_result_1(INV_output_45_1), + .o_result_2(INV_output_45_2), + .o_result_3(INV_output_45_3), + .o_valid(INV_valid_45) +); + +inverse_winograd_46 inverse_winograd_46_inst ( + .clk(clk), + .i_valid(PE_valid_46), + .i_result_0(PE_output_46_0), + .i_result_1(PE_output_46_1), + .i_result_2(PE_output_46_2), + .i_result_3(PE_output_46_3), + .i_result_4(PE_output_46_4), + .i_result_5(PE_output_46_5), + .o_result_0(INV_output_46_0), + .o_result_1(INV_output_46_1), + .o_result_2(INV_output_46_2), + .o_result_3(INV_output_46_3), + .o_valid(INV_valid_46) +); + +inverse_winograd_47 inverse_winograd_47_inst ( + .clk(clk), + .i_valid(PE_valid_47), + .i_result_0(PE_output_47_0), + .i_result_1(PE_output_47_1), + .i_result_2(PE_output_47_2), + .i_result_3(PE_output_47_3), + .i_result_4(PE_output_47_4), + .i_result_5(PE_output_47_5), + .o_result_0(INV_output_47_0), + .o_result_1(INV_output_47_1), + .o_result_2(INV_output_47_2), + .o_result_3(INV_output_47_3), + .o_valid(INV_valid_47) +); + +pooling pooling_inst_0 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_0), + .i_result_0(INV_output_0_0), + .i_result_1(INV_output_0_1), + .i_result_2(INV_output_0_2), + .i_result_3(INV_output_0_3), + .o_result(POOL_output_0), + .o_valid(POOL_valid_0) +); + +pooling pooling_inst_1 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_1), + .i_result_0(INV_output_1_0), + .i_result_1(INV_output_1_1), + .i_result_2(INV_output_1_2), + .i_result_3(INV_output_1_3), + .o_result(POOL_output_1), + .o_valid(POOL_valid_1) +); + +pooling pooling_inst_2 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_2), + .i_result_0(INV_output_2_0), + .i_result_1(INV_output_2_1), + .i_result_2(INV_output_2_2), + .i_result_3(INV_output_2_3), + .o_result(POOL_output_2), + .o_valid(POOL_valid_2) +); + +pooling pooling_inst_3 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_3), + .i_result_0(INV_output_3_0), + .i_result_1(INV_output_3_1), + .i_result_2(INV_output_3_2), + .i_result_3(INV_output_3_3), + .o_result(POOL_output_3), + .o_valid(POOL_valid_3) +); + +pooling pooling_inst_4 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_4), + .i_result_0(INV_output_4_0), + .i_result_1(INV_output_4_1), + .i_result_2(INV_output_4_2), + .i_result_3(INV_output_4_3), + .o_result(POOL_output_4), + .o_valid(POOL_valid_4) +); + +pooling pooling_inst_5 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_5), + .i_result_0(INV_output_5_0), + .i_result_1(INV_output_5_1), + .i_result_2(INV_output_5_2), + .i_result_3(INV_output_5_3), + .o_result(POOL_output_5), + .o_valid(POOL_valid_5) +); + +pooling pooling_inst_6 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_6), + .i_result_0(INV_output_6_0), + .i_result_1(INV_output_6_1), + .i_result_2(INV_output_6_2), + .i_result_3(INV_output_6_3), + .o_result(POOL_output_6), + .o_valid(POOL_valid_6) +); + +pooling pooling_inst_7 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_7), + .i_result_0(INV_output_7_0), + .i_result_1(INV_output_7_1), + .i_result_2(INV_output_7_2), + .i_result_3(INV_output_7_3), + .o_result(POOL_output_7), + .o_valid(POOL_valid_7) +); + +pooling pooling_inst_8 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_8), + .i_result_0(INV_output_8_0), + .i_result_1(INV_output_8_1), + .i_result_2(INV_output_8_2), + .i_result_3(INV_output_8_3), + .o_result(POOL_output_8), + .o_valid(POOL_valid_8) +); + +pooling pooling_inst_9 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_9), + .i_result_0(INV_output_9_0), + .i_result_1(INV_output_9_1), + .i_result_2(INV_output_9_2), + .i_result_3(INV_output_9_3), + .o_result(POOL_output_9), + .o_valid(POOL_valid_9) +); + +pooling pooling_inst_10 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_10), + .i_result_0(INV_output_10_0), + .i_result_1(INV_output_10_1), + .i_result_2(INV_output_10_2), + .i_result_3(INV_output_10_3), + .o_result(POOL_output_10), + .o_valid(POOL_valid_10) +); + +pooling pooling_inst_11 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_11), + .i_result_0(INV_output_11_0), + .i_result_1(INV_output_11_1), + .i_result_2(INV_output_11_2), + .i_result_3(INV_output_11_3), + .o_result(POOL_output_11), + .o_valid(POOL_valid_11) +); + +pooling pooling_inst_12 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_12), + .i_result_0(INV_output_12_0), + .i_result_1(INV_output_12_1), + .i_result_2(INV_output_12_2), + .i_result_3(INV_output_12_3), + .o_result(POOL_output_12), + .o_valid(POOL_valid_12) +); + +pooling pooling_inst_13 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_13), + .i_result_0(INV_output_13_0), + .i_result_1(INV_output_13_1), + .i_result_2(INV_output_13_2), + .i_result_3(INV_output_13_3), + .o_result(POOL_output_13), + .o_valid(POOL_valid_13) +); + +pooling pooling_inst_14 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_14), + .i_result_0(INV_output_14_0), + .i_result_1(INV_output_14_1), + .i_result_2(INV_output_14_2), + .i_result_3(INV_output_14_3), + .o_result(POOL_output_14), + .o_valid(POOL_valid_14) +); + +pooling pooling_inst_15 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_15), + .i_result_0(INV_output_15_0), + .i_result_1(INV_output_15_1), + .i_result_2(INV_output_15_2), + .i_result_3(INV_output_15_3), + .o_result(POOL_output_15), + .o_valid(POOL_valid_15) +); + +pooling pooling_inst_16 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_16), + .i_result_0(INV_output_16_0), + .i_result_1(INV_output_16_1), + .i_result_2(INV_output_16_2), + .i_result_3(INV_output_16_3), + .o_result(POOL_output_16), + .o_valid(POOL_valid_16) +); + +pooling pooling_inst_17 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_17), + .i_result_0(INV_output_17_0), + .i_result_1(INV_output_17_1), + .i_result_2(INV_output_17_2), + .i_result_3(INV_output_17_3), + .o_result(POOL_output_17), + .o_valid(POOL_valid_17) +); + +pooling pooling_inst_18 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_18), + .i_result_0(INV_output_18_0), + .i_result_1(INV_output_18_1), + .i_result_2(INV_output_18_2), + .i_result_3(INV_output_18_3), + .o_result(POOL_output_18), + .o_valid(POOL_valid_18) +); + +pooling pooling_inst_19 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_19), + .i_result_0(INV_output_19_0), + .i_result_1(INV_output_19_1), + .i_result_2(INV_output_19_2), + .i_result_3(INV_output_19_3), + .o_result(POOL_output_19), + .o_valid(POOL_valid_19) +); + +pooling pooling_inst_20 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_20), + .i_result_0(INV_output_20_0), + .i_result_1(INV_output_20_1), + .i_result_2(INV_output_20_2), + .i_result_3(INV_output_20_3), + .o_result(POOL_output_20), + .o_valid(POOL_valid_20) +); + +pooling pooling_inst_21 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_21), + .i_result_0(INV_output_21_0), + .i_result_1(INV_output_21_1), + .i_result_2(INV_output_21_2), + .i_result_3(INV_output_21_3), + .o_result(POOL_output_21), + .o_valid(POOL_valid_21) +); + +pooling pooling_inst_22 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_22), + .i_result_0(INV_output_22_0), + .i_result_1(INV_output_22_1), + .i_result_2(INV_output_22_2), + .i_result_3(INV_output_22_3), + .o_result(POOL_output_22), + .o_valid(POOL_valid_22) +); + +pooling pooling_inst_23 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_23), + .i_result_0(INV_output_23_0), + .i_result_1(INV_output_23_1), + .i_result_2(INV_output_23_2), + .i_result_3(INV_output_23_3), + .o_result(POOL_output_23), + .o_valid(POOL_valid_23) +); + +pooling pooling_inst_24 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_24), + .i_result_0(INV_output_24_0), + .i_result_1(INV_output_24_1), + .i_result_2(INV_output_24_2), + .i_result_3(INV_output_24_3), + .o_result(POOL_output_24), + .o_valid(POOL_valid_24) +); + +pooling pooling_inst_25 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_25), + .i_result_0(INV_output_25_0), + .i_result_1(INV_output_25_1), + .i_result_2(INV_output_25_2), + .i_result_3(INV_output_25_3), + .o_result(POOL_output_25), + .o_valid(POOL_valid_25) +); + +pooling pooling_inst_26 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_26), + .i_result_0(INV_output_26_0), + .i_result_1(INV_output_26_1), + .i_result_2(INV_output_26_2), + .i_result_3(INV_output_26_3), + .o_result(POOL_output_26), + .o_valid(POOL_valid_26) +); + +pooling pooling_inst_27 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_27), + .i_result_0(INV_output_27_0), + .i_result_1(INV_output_27_1), + .i_result_2(INV_output_27_2), + .i_result_3(INV_output_27_3), + .o_result(POOL_output_27), + .o_valid(POOL_valid_27) +); + +pooling pooling_inst_28 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_28), + .i_result_0(INV_output_28_0), + .i_result_1(INV_output_28_1), + .i_result_2(INV_output_28_2), + .i_result_3(INV_output_28_3), + .o_result(POOL_output_28), + .o_valid(POOL_valid_28) +); + +pooling pooling_inst_29 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_29), + .i_result_0(INV_output_29_0), + .i_result_1(INV_output_29_1), + .i_result_2(INV_output_29_2), + .i_result_3(INV_output_29_3), + .o_result(POOL_output_29), + .o_valid(POOL_valid_29) +); + +pooling pooling_inst_30 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_30), + .i_result_0(INV_output_30_0), + .i_result_1(INV_output_30_1), + .i_result_2(INV_output_30_2), + .i_result_3(INV_output_30_3), + .o_result(POOL_output_30), + .o_valid(POOL_valid_30) +); + +pooling pooling_inst_31 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_31), + .i_result_0(INV_output_31_0), + .i_result_1(INV_output_31_1), + .i_result_2(INV_output_31_2), + .i_result_3(INV_output_31_3), + .o_result(POOL_output_31), + .o_valid(POOL_valid_31) +); + +pooling pooling_inst_32 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_32), + .i_result_0(INV_output_32_0), + .i_result_1(INV_output_32_1), + .i_result_2(INV_output_32_2), + .i_result_3(INV_output_32_3), + .o_result(POOL_output_32), + .o_valid(POOL_valid_32) +); + +pooling pooling_inst_33 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_33), + .i_result_0(INV_output_33_0), + .i_result_1(INV_output_33_1), + .i_result_2(INV_output_33_2), + .i_result_3(INV_output_33_3), + .o_result(POOL_output_33), + .o_valid(POOL_valid_33) +); + +pooling pooling_inst_34 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_34), + .i_result_0(INV_output_34_0), + .i_result_1(INV_output_34_1), + .i_result_2(INV_output_34_2), + .i_result_3(INV_output_34_3), + .o_result(POOL_output_34), + .o_valid(POOL_valid_34) +); + +pooling pooling_inst_35 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_35), + .i_result_0(INV_output_35_0), + .i_result_1(INV_output_35_1), + .i_result_2(INV_output_35_2), + .i_result_3(INV_output_35_3), + .o_result(POOL_output_35), + .o_valid(POOL_valid_35) +); + +pooling pooling_inst_36 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_36), + .i_result_0(INV_output_36_0), + .i_result_1(INV_output_36_1), + .i_result_2(INV_output_36_2), + .i_result_3(INV_output_36_3), + .o_result(POOL_output_36), + .o_valid(POOL_valid_36) +); + +pooling pooling_inst_37 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_37), + .i_result_0(INV_output_37_0), + .i_result_1(INV_output_37_1), + .i_result_2(INV_output_37_2), + .i_result_3(INV_output_37_3), + .o_result(POOL_output_37), + .o_valid(POOL_valid_37) +); + +pooling pooling_inst_38 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_38), + .i_result_0(INV_output_38_0), + .i_result_1(INV_output_38_1), + .i_result_2(INV_output_38_2), + .i_result_3(INV_output_38_3), + .o_result(POOL_output_38), + .o_valid(POOL_valid_38) +); + +pooling pooling_inst_39 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_39), + .i_result_0(INV_output_39_0), + .i_result_1(INV_output_39_1), + .i_result_2(INV_output_39_2), + .i_result_3(INV_output_39_3), + .o_result(POOL_output_39), + .o_valid(POOL_valid_39) +); + +pooling pooling_inst_40 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_40), + .i_result_0(INV_output_40_0), + .i_result_1(INV_output_40_1), + .i_result_2(INV_output_40_2), + .i_result_3(INV_output_40_3), + .o_result(POOL_output_40), + .o_valid(POOL_valid_40) +); + +pooling pooling_inst_41 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_41), + .i_result_0(INV_output_41_0), + .i_result_1(INV_output_41_1), + .i_result_2(INV_output_41_2), + .i_result_3(INV_output_41_3), + .o_result(POOL_output_41), + .o_valid(POOL_valid_41) +); + +pooling pooling_inst_42 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_42), + .i_result_0(INV_output_42_0), + .i_result_1(INV_output_42_1), + .i_result_2(INV_output_42_2), + .i_result_3(INV_output_42_3), + .o_result(POOL_output_42), + .o_valid(POOL_valid_42) +); + +pooling pooling_inst_43 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_43), + .i_result_0(INV_output_43_0), + .i_result_1(INV_output_43_1), + .i_result_2(INV_output_43_2), + .i_result_3(INV_output_43_3), + .o_result(POOL_output_43), + .o_valid(POOL_valid_43) +); + +pooling pooling_inst_44 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_44), + .i_result_0(INV_output_44_0), + .i_result_1(INV_output_44_1), + .i_result_2(INV_output_44_2), + .i_result_3(INV_output_44_3), + .o_result(POOL_output_44), + .o_valid(POOL_valid_44) +); + +pooling pooling_inst_45 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_45), + .i_result_0(INV_output_45_0), + .i_result_1(INV_output_45_1), + .i_result_2(INV_output_45_2), + .i_result_3(INV_output_45_3), + .o_result(POOL_output_45), + .o_valid(POOL_valid_45) +); + +pooling pooling_inst_46 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_46), + .i_result_0(INV_output_46_0), + .i_result_1(INV_output_46_1), + .i_result_2(INV_output_46_2), + .i_result_3(INV_output_46_3), + .o_result(POOL_output_46), + .o_valid(POOL_valid_46) +); + +pooling pooling_inst_47 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_47), + .i_result_0(INV_output_47_0), + .i_result_1(INV_output_47_1), + .i_result_2(INV_output_47_2), + .i_result_3(INV_output_47_3), + .o_result(POOL_output_47), + .o_valid(POOL_valid_47) +); + +store_output store_output_inst ( + .clk(clk), + .i_valid(POOL_valid_0), + .i_reset(i_reset), + .i_result_0(POOL_output_0), + .i_result_1(POOL_output_1), + .i_result_2(POOL_output_2), + .i_result_3(POOL_output_3), + .i_result_4(POOL_output_4), + .i_result_5(POOL_output_5), + .i_result_6(POOL_output_6), + .i_result_7(POOL_output_7), + .i_result_8(POOL_output_8), + .i_result_9(POOL_output_9), + .i_result_10(POOL_output_10), + .i_result_11(POOL_output_11), + .i_result_12(POOL_output_12), + .i_result_13(POOL_output_13), + .i_result_14(POOL_output_14), + .i_result_15(POOL_output_15), + .i_result_16(POOL_output_16), + .i_result_17(POOL_output_17), + .i_result_18(POOL_output_18), + .i_result_19(POOL_output_19), + .i_result_20(POOL_output_20), + .i_result_21(POOL_output_21), + .i_result_22(POOL_output_22), + .i_result_23(POOL_output_23), + .i_result_24(POOL_output_24), + .i_result_25(POOL_output_25), + .i_result_26(POOL_output_26), + .i_result_27(POOL_output_27), + .i_result_28(POOL_output_28), + .i_result_29(POOL_output_29), + .i_result_30(POOL_output_30), + .i_result_31(POOL_output_31), + .i_result_32(POOL_output_32), + .i_result_33(POOL_output_33), + .i_result_34(POOL_output_34), + .i_result_35(POOL_output_35), + .i_result_36(POOL_output_36), + .i_result_37(POOL_output_37), + .i_result_38(POOL_output_38), + .i_result_39(POOL_output_39), + .i_result_40(POOL_output_40), + .i_result_41(POOL_output_41), + .i_result_42(POOL_output_42), + .i_result_43(POOL_output_43), + .i_result_44(POOL_output_44), + .i_result_45(POOL_output_45), + .i_result_46(POOL_output_46), + .i_result_47(POOL_output_47), + .o_store_0_0(STORE_output_0_0), + .o_store_0_1(STORE_output_0_1), + .o_store_0_2(STORE_output_0_2), + .o_store_0_3(STORE_output_0_3), + .o_store_0_4(STORE_output_0_4), + .o_store_0_5(STORE_output_0_5), + .o_store_0_6(STORE_output_0_6), + .o_store_0_7(STORE_output_0_7), + .o_store_1_0(STORE_output_1_0), + .o_store_1_1(STORE_output_1_1), + .o_store_1_2(STORE_output_1_2), + .o_store_1_3(STORE_output_1_3), + .o_store_1_4(STORE_output_1_4), + .o_store_1_5(STORE_output_1_5), + .o_store_1_6(STORE_output_1_6), + .o_store_1_7(STORE_output_1_7), + .o_store_2_0(STORE_output_2_0), + .o_store_2_1(STORE_output_2_1), + .o_store_2_2(STORE_output_2_2), + .o_store_2_3(STORE_output_2_3), + .o_store_2_4(STORE_output_2_4), + .o_store_2_5(STORE_output_2_5), + .o_store_2_6(STORE_output_2_6), + .o_store_2_7(STORE_output_2_7), + .o_store_3_0(STORE_output_3_0), + .o_store_3_1(STORE_output_3_1), + .o_store_3_2(STORE_output_3_2), + .o_store_3_3(STORE_output_3_3), + .o_store_3_4(STORE_output_3_4), + .o_store_3_5(STORE_output_3_5), + .o_store_3_6(STORE_output_3_6), + .o_store_3_7(STORE_output_3_7), + .o_store_4_0(STORE_output_4_0), + .o_store_4_1(STORE_output_4_1), + .o_store_4_2(STORE_output_4_2), + .o_store_4_3(STORE_output_4_3), + .o_store_4_4(STORE_output_4_4), + .o_store_4_5(STORE_output_4_5), + .o_store_4_6(STORE_output_4_6), + .o_store_4_7(STORE_output_4_7), + .o_store_5_0(STORE_output_5_0), + .o_store_5_1(STORE_output_5_1), + .o_store_5_2(STORE_output_5_2), + .o_store_5_3(STORE_output_5_3), + .o_store_5_4(STORE_output_5_4), + .o_store_5_5(STORE_output_5_5), + .o_store_5_6(STORE_output_5_6), + .o_store_5_7(STORE_output_5_7), + .o_wen_0(STORE_wen_0), + .o_wen_1(STORE_wen_1), + .o_wen_2(STORE_wen_2), + .o_wen_3(STORE_wen_3), + .o_wen_4(STORE_wen_4), + .o_wen_5(STORE_wen_5), + .o_addr(STORE_addr) +); + +signal_width_reducer signal_width_reducer_inst ( + .clk(clk), + .signals_0_0(dummy_out_0_0), + .reduced_signals_0_0(o_dummy_out_0_0), + .signals_0_1(dummy_out_0_1), + .reduced_signals_0_1(o_dummy_out_0_1), + .signals_0_2(dummy_out_0_2), + .reduced_signals_0_2(o_dummy_out_0_2), + .signals_0_3(dummy_out_0_3), + .reduced_signals_0_3(o_dummy_out_0_3), + .signals_0_4(dummy_out_0_4), + .reduced_signals_0_4(o_dummy_out_0_4), + .signals_0_5(dummy_out_0_5), + .reduced_signals_0_5(o_dummy_out_0_5), + .signals_0_6(dummy_out_0_6), + .reduced_signals_0_6(o_dummy_out_0_6), + .signals_0_7(dummy_out_0_7), + .reduced_signals_0_7(o_dummy_out_0_7), + .signals_1_0(dummy_out_1_0), + .reduced_signals_1_0(o_dummy_out_1_0), + .signals_1_1(dummy_out_1_1), + .reduced_signals_1_1(o_dummy_out_1_1), + .signals_1_2(dummy_out_1_2), + .reduced_signals_1_2(o_dummy_out_1_2), + .signals_1_3(dummy_out_1_3), + .reduced_signals_1_3(o_dummy_out_1_3), + .signals_1_4(dummy_out_1_4), + .reduced_signals_1_4(o_dummy_out_1_4), + .signals_1_5(dummy_out_1_5), + .reduced_signals_1_5(o_dummy_out_1_5), + .signals_1_6(dummy_out_1_6), + .reduced_signals_1_6(o_dummy_out_1_6), + .signals_1_7(dummy_out_1_7), + .reduced_signals_1_7(o_dummy_out_1_7), + .signals_2_0(dummy_out_2_0), + .reduced_signals_2_0(o_dummy_out_2_0), + .signals_2_1(dummy_out_2_1), + .reduced_signals_2_1(o_dummy_out_2_1), + .signals_2_2(dummy_out_2_2), + .reduced_signals_2_2(o_dummy_out_2_2), + .signals_2_3(dummy_out_2_3), + .reduced_signals_2_3(o_dummy_out_2_3), + .signals_2_4(dummy_out_2_4), + .reduced_signals_2_4(o_dummy_out_2_4), + .signals_2_5(dummy_out_2_5), + .reduced_signals_2_5(o_dummy_out_2_5), + .signals_2_6(dummy_out_2_6), + .reduced_signals_2_6(o_dummy_out_2_6), + .signals_2_7(dummy_out_2_7), + .reduced_signals_2_7(o_dummy_out_2_7), + .signals_3_0(dummy_out_3_0), + .reduced_signals_3_0(o_dummy_out_3_0), + .signals_3_1(dummy_out_3_1), + .reduced_signals_3_1(o_dummy_out_3_1), + .signals_3_2(dummy_out_3_2), + .reduced_signals_3_2(o_dummy_out_3_2), + .signals_3_3(dummy_out_3_3), + .reduced_signals_3_3(o_dummy_out_3_3), + .signals_3_4(dummy_out_3_4), + .reduced_signals_3_4(o_dummy_out_3_4), + .signals_3_5(dummy_out_3_5), + .reduced_signals_3_5(o_dummy_out_3_5), + .signals_3_6(dummy_out_3_6), + .reduced_signals_3_6(o_dummy_out_3_6), + .signals_3_7(dummy_out_3_7), + .reduced_signals_3_7(o_dummy_out_3_7), + .signals_4_0(dummy_out_4_0), + .reduced_signals_4_0(o_dummy_out_4_0), + .signals_4_1(dummy_out_4_1), + .reduced_signals_4_1(o_dummy_out_4_1), + .signals_4_2(dummy_out_4_2), + .reduced_signals_4_2(o_dummy_out_4_2), + .signals_4_3(dummy_out_4_3), + .reduced_signals_4_3(o_dummy_out_4_3), + .signals_4_4(dummy_out_4_4), + .reduced_signals_4_4(o_dummy_out_4_4), + .signals_4_5(dummy_out_4_5), + .reduced_signals_4_5(o_dummy_out_4_5), + .signals_4_6(dummy_out_4_6), + .reduced_signals_4_6(o_dummy_out_4_6), + .signals_4_7(dummy_out_4_7), + .reduced_signals_4_7(o_dummy_out_4_7), + .signals_5_0(dummy_out_5_0), + .reduced_signals_5_0(o_dummy_out_5_0), + .signals_5_1(dummy_out_5_1), + .reduced_signals_5_1(o_dummy_out_5_1), + .signals_5_2(dummy_out_5_2), + .reduced_signals_5_2(o_dummy_out_5_2), + .signals_5_3(dummy_out_5_3), + .reduced_signals_5_3(o_dummy_out_5_3), + .signals_5_4(dummy_out_5_4), + .reduced_signals_5_4(o_dummy_out_5_4), + .signals_5_5(dummy_out_5_5), + .reduced_signals_5_5(o_dummy_out_5_5), + .signals_5_6(dummy_out_5_6), + .reduced_signals_5_6(o_dummy_out_5_6), + .signals_5_7(dummy_out_5_7), + .reduced_signals_5_7(o_dummy_out_5_7), + .reset(i_reset) +); + +assign o_valid = POOL_valid_0; + +endmodule + +module processing_element ( + input clk, + input i_reset, + input i_valid, + input [15:0] i_features_0_0, + output [15:0] o_features_0_0, + input [15:0] i_features_0_1, + output [15:0] o_features_0_1, + input [15:0] i_features_0_2, + output [15:0] o_features_0_2, + input [15:0] i_features_0_3, + output [15:0] o_features_0_3, + input [15:0] i_features_0_4, + output [15:0] o_features_0_4, + input [15:0] i_features_0_5, + output [15:0] o_features_0_5, + input [15:0] i_features_1_0, + output [15:0] o_features_1_0, + input [15:0] i_features_1_1, + output [15:0] o_features_1_1, + input [15:0] i_features_1_2, + output [15:0] o_features_1_2, + input [15:0] i_features_1_3, + output [15:0] o_features_1_3, + input [15:0] i_features_1_4, + output [15:0] o_features_1_4, + input [15:0] i_features_1_5, + output [15:0] o_features_1_5, + input [15:0] i_features_2_0, + output [15:0] o_features_2_0, + input [15:0] i_features_2_1, + output [15:0] o_features_2_1, + input [15:0] i_features_2_2, + output [15:0] o_features_2_2, + input [15:0] i_features_2_3, + output [15:0] o_features_2_3, + input [15:0] i_features_2_4, + output [15:0] o_features_2_4, + input [15:0] i_features_2_5, + output [15:0] o_features_2_5, + input [15:0] i_features_3_0, + output [15:0] o_features_3_0, + input [15:0] i_features_3_1, + output [15:0] o_features_3_1, + input [15:0] i_features_3_2, + output [15:0] o_features_3_2, + input [15:0] i_features_3_3, + output [15:0] o_features_3_3, + input [15:0] i_features_3_4, + output [15:0] o_features_3_4, + input [15:0] i_features_3_5, + output [15:0] o_features_3_5, + input [15:0] i_features_4_0, + output [15:0] o_features_4_0, + input [15:0] i_features_4_1, + output [15:0] o_features_4_1, + input [15:0] i_features_4_2, + output [15:0] o_features_4_2, + input [15:0] i_features_4_3, + output [15:0] o_features_4_3, + input [15:0] i_features_4_4, + output [15:0] o_features_4_4, + input [15:0] i_features_4_5, + output [15:0] o_features_4_5, + input [15:0] i_features_5_0, + output [15:0] o_features_5_0, + input [15:0] i_features_5_1, + output [15:0] o_features_5_1, + input [15:0] i_features_5_2, + output [15:0] o_features_5_2, + input [15:0] i_features_5_3, + output [15:0] o_features_5_3, + input [15:0] i_features_5_4, + output [15:0] o_features_5_4, + input [15:0] i_features_5_5, + output [15:0] o_features_5_5, + input [15:0] i_features_6_0, + output [15:0] o_features_6_0, + input [15:0] i_features_6_1, + output [15:0] o_features_6_1, + input [15:0] i_features_6_2, + output [15:0] o_features_6_2, + input [15:0] i_features_6_3, + output [15:0] o_features_6_3, + input [15:0] i_features_6_4, + output [15:0] o_features_6_4, + input [15:0] i_features_6_5, + output [15:0] o_features_6_5, + input [15:0] i_features_7_0, + output [15:0] o_features_7_0, + input [15:0] i_features_7_1, + output [15:0] o_features_7_1, + input [15:0] i_features_7_2, + output [15:0] o_features_7_2, + input [15:0] i_features_7_3, + output [15:0] o_features_7_3, + input [15:0] i_features_7_4, + output [15:0] o_features_7_4, + input [15:0] i_features_7_5, + output [15:0] o_features_7_5, + output [29:0] o_result_0, + output [29:0] o_result_1, + output [29:0] o_result_2, + output [29:0] o_result_3, + output [29:0] o_result_4, + output [29:0] o_result_5, + output o_valid, + output o_next_reset, + output o_next_valid +); + +wire [23:0] DP_res_0; +reg [15:0] if_reg_0_0; +wire [7:0] weights_0_0; +reg [15:0] if_reg_0_1; +wire [7:0] weights_0_1; +reg [15:0] if_reg_0_2; +wire [7:0] weights_0_2; +reg [15:0] if_reg_0_3; +wire [7:0] weights_0_3; +reg [15:0] if_reg_0_4; +wire [7:0] weights_0_4; +reg [15:0] if_reg_0_5; +wire [7:0] weights_0_5; +reg [15:0] if_reg_0_6; +wire [7:0] weights_0_6; +reg [15:0] if_reg_0_7; +wire [7:0] weights_0_7; +wire [23:0] DP_res_1; +reg [15:0] if_reg_1_0; +wire [7:0] weights_1_0; +reg [15:0] if_reg_1_1; +wire [7:0] weights_1_1; +reg [15:0] if_reg_1_2; +wire [7:0] weights_1_2; +reg [15:0] if_reg_1_3; +wire [7:0] weights_1_3; +reg [15:0] if_reg_1_4; +wire [7:0] weights_1_4; +reg [15:0] if_reg_1_5; +wire [7:0] weights_1_5; +reg [15:0] if_reg_1_6; +wire [7:0] weights_1_6; +reg [15:0] if_reg_1_7; +wire [7:0] weights_1_7; +wire [23:0] DP_res_2; +reg [15:0] if_reg_2_0; +wire [7:0] weights_2_0; +reg [15:0] if_reg_2_1; +wire [7:0] weights_2_1; +reg [15:0] if_reg_2_2; +wire [7:0] weights_2_2; +reg [15:0] if_reg_2_3; +wire [7:0] weights_2_3; +reg [15:0] if_reg_2_4; +wire [7:0] weights_2_4; +reg [15:0] if_reg_2_5; +wire [7:0] weights_2_5; +reg [15:0] if_reg_2_6; +wire [7:0] weights_2_6; +reg [15:0] if_reg_2_7; +wire [7:0] weights_2_7; +wire [23:0] DP_res_3; +reg [15:0] if_reg_3_0; +wire [7:0] weights_3_0; +reg [15:0] if_reg_3_1; +wire [7:0] weights_3_1; +reg [15:0] if_reg_3_2; +wire [7:0] weights_3_2; +reg [15:0] if_reg_3_3; +wire [7:0] weights_3_3; +reg [15:0] if_reg_3_4; +wire [7:0] weights_3_4; +reg [15:0] if_reg_3_5; +wire [7:0] weights_3_5; +reg [15:0] if_reg_3_6; +wire [7:0] weights_3_6; +reg [15:0] if_reg_3_7; +wire [7:0] weights_3_7; +wire [23:0] DP_res_4; +reg [15:0] if_reg_4_0; +wire [7:0] weights_4_0; +reg [15:0] if_reg_4_1; +wire [7:0] weights_4_1; +reg [15:0] if_reg_4_2; +wire [7:0] weights_4_2; +reg [15:0] if_reg_4_3; +wire [7:0] weights_4_3; +reg [15:0] if_reg_4_4; +wire [7:0] weights_4_4; +reg [15:0] if_reg_4_5; +wire [7:0] weights_4_5; +reg [15:0] if_reg_4_6; +wire [7:0] weights_4_6; +reg [15:0] if_reg_4_7; +wire [7:0] weights_4_7; +wire [23:0] DP_res_5; +reg [15:0] if_reg_5_0; +wire [7:0] weights_5_0; +reg [15:0] if_reg_5_1; +wire [7:0] weights_5_1; +reg [15:0] if_reg_5_2; +wire [7:0] weights_5_2; +reg [15:0] if_reg_5_3; +wire [7:0] weights_5_3; +reg [15:0] if_reg_5_4; +wire [7:0] weights_5_4; +reg [15:0] if_reg_5_5; +wire [7:0] weights_5_5; +reg [15:0] if_reg_5_6; +wire [7:0] weights_5_6; +reg [15:0] if_reg_5_7; +wire [7:0] weights_5_7; + +reg [10:0] base_addr; +reg [10:0] offset; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [15:0] T_counter; + +reg reset_1, reset_2, reset_3, next_reset, next_reset_2; +reg done, done_1, done_2, done_3, done_4, done_5, done_6; + +wire [15:0] features_0_0; +wire [15:0] features_0_1; +wire [15:0] features_0_2; +wire [15:0] features_0_3; +wire [15:0] features_0_4; +wire [15:0] features_0_5; +wire [15:0] features_0_6; +wire [15:0] features_0_7; +wire [15:0] features_1_0; +wire [15:0] features_1_1; +wire [15:0] features_1_2; +wire [15:0] features_1_3; +wire [15:0] features_1_4; +wire [15:0] features_1_5; +wire [15:0] features_1_6; +wire [15:0] features_1_7; +wire [15:0] features_2_0; +wire [15:0] features_2_1; +wire [15:0] features_2_2; +wire [15:0] features_2_3; +wire [15:0] features_2_4; +wire [15:0] features_2_5; +wire [15:0] features_2_6; +wire [15:0] features_2_7; +wire [15:0] features_3_0; +wire [15:0] features_3_1; +wire [15:0] features_3_2; +wire [15:0] features_3_3; +wire [15:0] features_3_4; +wire [15:0] features_3_5; +wire [15:0] features_3_6; +wire [15:0] features_3_7; +wire [15:0] features_4_0; +wire [15:0] features_4_1; +wire [15:0] features_4_2; +wire [15:0] features_4_3; +wire [15:0] features_4_4; +wire [15:0] features_4_5; +wire [15:0] features_4_6; +wire [15:0] features_4_7; +wire [15:0] features_5_0; +wire [15:0] features_5_1; +wire [15:0] features_5_2; +wire [15:0] features_5_3; +wire [15:0] features_5_4; +wire [15:0] features_5_5; +wire [15:0] features_5_6; +wire [15:0] features_5_7; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg next_valid; + +always @ (posedge clk) begin + reset_1 <= ~(i_valid || valid_11); + reset_2 <= reset_1; + reset_3 <= reset_2; + next_reset <= i_reset; + next_reset_2 <= next_reset; + if (i_reset == 1'b0) begin + if_reg_0_0 <= features_0_0; + if_reg_0_1 <= features_0_1; + if_reg_0_2 <= features_0_2; + if_reg_0_3 <= features_0_3; + if_reg_0_4 <= features_0_4; + if_reg_0_5 <= features_0_5; + if_reg_0_6 <= features_0_6; + if_reg_0_7 <= features_0_7; + if_reg_1_0 <= features_1_0; + if_reg_1_1 <= features_1_1; + if_reg_1_2 <= features_1_2; + if_reg_1_3 <= features_1_3; + if_reg_1_4 <= features_1_4; + if_reg_1_5 <= features_1_5; + if_reg_1_6 <= features_1_6; + if_reg_1_7 <= features_1_7; + if_reg_2_0 <= features_2_0; + if_reg_2_1 <= features_2_1; + if_reg_2_2 <= features_2_2; + if_reg_2_3 <= features_2_3; + if_reg_2_4 <= features_2_4; + if_reg_2_5 <= features_2_5; + if_reg_2_6 <= features_2_6; + if_reg_2_7 <= features_2_7; + if_reg_3_0 <= features_3_0; + if_reg_3_1 <= features_3_1; + if_reg_3_2 <= features_3_2; + if_reg_3_3 <= features_3_3; + if_reg_3_4 <= features_3_4; + if_reg_3_5 <= features_3_5; + if_reg_3_6 <= features_3_6; + if_reg_3_7 <= features_3_7; + if_reg_4_0 <= features_4_0; + if_reg_4_1 <= features_4_1; + if_reg_4_2 <= features_4_2; + if_reg_4_3 <= features_4_3; + if_reg_4_4 <= features_4_4; + if_reg_4_5 <= features_4_5; + if_reg_4_6 <= features_4_6; + if_reg_4_7 <= features_4_7; + if_reg_5_0 <= features_5_0; + if_reg_5_1 <= features_5_1; + if_reg_5_2 <= features_5_2; + if_reg_5_3 <= features_5_3; + if_reg_5_4 <= features_5_4; + if_reg_5_5 <= features_5_5; + if_reg_5_6 <= features_5_6; + if_reg_5_7 <= features_5_7; + end +end + +always @ (posedge clk) begin + next_valid <= i_valid; + if (i_reset) begin + valid_0 <= 0; + valid_1 <= 0; + valid_2 <= 0; + valid_3 <= 0; + valid_4 <= 0; + valid_5 <= 0; + valid_6 <= 0; + valid_7 <= 0; + valid_8 <= 0; + valid_9 <= 0; + valid_10 <= 0; + valid_11 <= 0; + end else if ((i_valid == 1'b0) && (valid_11 == 1'b0)) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + T_counter <= 0; + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + done_4 <= 0; + done_5 <= 0; + done_6 <= 0; + end else if (i_valid || valid_11) begin + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + if (T_counter <= 1809025) begin + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + done_4 <= done_3; + done_5 <= done_4; + done_6 <= done_5; + if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + done <= 1; + T_counter <= T_counter + 1'b1; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + done <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end + end +end + +dot_product_16_8_30_8 dot_product_16_8_30_8_inst_0 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_0_0), + .i_weights_0(weights_0_0), + .i_features_1(features_0_1), + .i_weights_1(weights_0_1), + .i_features_2(features_0_2), + .i_weights_2(weights_0_2), + .i_features_3(features_0_3), + .i_weights_3(weights_0_3), + .i_features_4(features_0_4), + .i_weights_4(weights_0_4), + .i_features_5(features_0_5), + .i_weights_5(weights_0_5), + .i_features_6(features_0_6), + .i_weights_6(weights_0_6), + .i_features_7(features_0_7), + .i_weights_7(weights_0_7), + .o_result(DP_res_0) +); + +dot_product_16_8_30_8 dot_product_16_8_30_8_inst_1 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_1_0), + .i_weights_0(weights_1_0), + .i_features_1(features_1_1), + .i_weights_1(weights_1_1), + .i_features_2(features_1_2), + .i_weights_2(weights_1_2), + .i_features_3(features_1_3), + .i_weights_3(weights_1_3), + .i_features_4(features_1_4), + .i_weights_4(weights_1_4), + .i_features_5(features_1_5), + .i_weights_5(weights_1_5), + .i_features_6(features_1_6), + .i_weights_6(weights_1_6), + .i_features_7(features_1_7), + .i_weights_7(weights_1_7), + .o_result(DP_res_1) +); + +dot_product_16_8_30_8 dot_product_16_8_30_8_inst_2 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_2_0), + .i_weights_0(weights_2_0), + .i_features_1(features_2_1), + .i_weights_1(weights_2_1), + .i_features_2(features_2_2), + .i_weights_2(weights_2_2), + .i_features_3(features_2_3), + .i_weights_3(weights_2_3), + .i_features_4(features_2_4), + .i_weights_4(weights_2_4), + .i_features_5(features_2_5), + .i_weights_5(weights_2_5), + .i_features_6(features_2_6), + .i_weights_6(weights_2_6), + .i_features_7(features_2_7), + .i_weights_7(weights_2_7), + .o_result(DP_res_2) +); + +dot_product_16_8_30_8 dot_product_16_8_30_8_inst_3 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_3_0), + .i_weights_0(weights_3_0), + .i_features_1(features_3_1), + .i_weights_1(weights_3_1), + .i_features_2(features_3_2), + .i_weights_2(weights_3_2), + .i_features_3(features_3_3), + .i_weights_3(weights_3_3), + .i_features_4(features_3_4), + .i_weights_4(weights_3_4), + .i_features_5(features_3_5), + .i_weights_5(weights_3_5), + .i_features_6(features_3_6), + .i_weights_6(weights_3_6), + .i_features_7(features_3_7), + .i_weights_7(weights_3_7), + .o_result(DP_res_3) +); + +dot_product_16_8_30_8 dot_product_16_8_30_8_inst_4 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_4_0), + .i_weights_0(weights_4_0), + .i_features_1(features_4_1), + .i_weights_1(weights_4_1), + .i_features_2(features_4_2), + .i_weights_2(weights_4_2), + .i_features_3(features_4_3), + .i_weights_3(weights_4_3), + .i_features_4(features_4_4), + .i_weights_4(weights_4_4), + .i_features_5(features_4_5), + .i_weights_5(weights_4_5), + .i_features_6(features_4_6), + .i_weights_6(weights_4_6), + .i_features_7(features_4_7), + .i_weights_7(weights_4_7), + .o_result(DP_res_4) +); + +dot_product_16_8_30_8 dot_product_16_8_30_8_inst_5 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_5_0), + .i_weights_0(weights_5_0), + .i_features_1(features_5_1), + .i_weights_1(weights_5_1), + .i_features_2(features_5_2), + .i_weights_2(weights_5_2), + .i_features_3(features_5_3), + .i_weights_3(weights_5_3), + .i_features_4(features_5_4), + .i_weights_4(weights_5_4), + .i_features_5(features_5_5), + .i_weights_5(weights_5_5), + .i_features_6(features_5_6), + .i_weights_6(weights_5_6), + .i_features_7(features_5_7), + .i_weights_7(weights_5_7), + .o_result(DP_res_5) +); + +accumulator_24_30_6 accumulator_24_30_6_inst_0 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_0), + .i_dp_done(done_5), + .o_accum(o_result_0) +); + +accumulator_24_30_6 accumulator_24_30_6_inst_1 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_1), + .i_dp_done(done_5), + .o_accum(o_result_1) +); + +accumulator_24_30_6 accumulator_24_30_6_inst_2 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_2), + .i_dp_done(done_5), + .o_accum(o_result_2) +); + +accumulator_24_30_6 accumulator_24_30_6_inst_3 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_3), + .i_dp_done(done_5), + .o_accum(o_result_3) +); + +accumulator_24_30_6 accumulator_24_30_6_inst_4 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_4), + .i_dp_done(done_5), + .o_accum(o_result_4) +); + +accumulator_24_30_6 accumulator_24_30_6_inst_5 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_5), + .i_dp_done(done_5), + .o_accum(o_result_5) +); + +reg [9:0] weight_cache_addr; +always @ (*) begin + weight_cache_addr <= base_addr+offset; +end +weight_cache_2048_8_0_weight_init_00 weight_cache_2048_8_0_weight_init_00_inst_0_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_0_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_0_1) +); + +weight_cache_2048_8_0_weight_init_20 weight_cache_2048_8_0_weight_init_20_inst_0_2 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_0_2), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_0_3) +); + +weight_cache_2048_8_0_weight_init_40 weight_cache_2048_8_0_weight_init_40_inst_0_4 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_0_4), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_0_5) +); + +weight_cache_2048_8_0_weight_init_60 weight_cache_2048_8_0_weight_init_60_inst_0_6 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_0_6), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_0_7) +); + +weight_cache_2048_8_0_weight_init_01 weight_cache_2048_8_0_weight_init_01_inst_1_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_1_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_1_1) +); + +weight_cache_2048_8_0_weight_init_21 weight_cache_2048_8_0_weight_init_21_inst_1_2 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_1_2), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_1_3) +); + +weight_cache_2048_8_0_weight_init_41 weight_cache_2048_8_0_weight_init_41_inst_1_4 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_1_4), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_1_5) +); + +weight_cache_2048_8_0_weight_init_61 weight_cache_2048_8_0_weight_init_61_inst_1_6 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_1_6), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_1_7) +); + +weight_cache_2048_8_0_weight_init_02 weight_cache_2048_8_0_weight_init_02_inst_2_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_2_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_2_1) +); + +weight_cache_2048_8_0_weight_init_22 weight_cache_2048_8_0_weight_init_22_inst_2_2 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_2_2), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_2_3) +); + +weight_cache_2048_8_0_weight_init_42 weight_cache_2048_8_0_weight_init_42_inst_2_4 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_2_4), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_2_5) +); + +weight_cache_2048_8_0_weight_init_62 weight_cache_2048_8_0_weight_init_62_inst_2_6 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_2_6), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_2_7) +); + +weight_cache_2048_8_0_weight_init_03 weight_cache_2048_8_0_weight_init_03_inst_3_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_3_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_3_1) +); + +weight_cache_2048_8_0_weight_init_23 weight_cache_2048_8_0_weight_init_23_inst_3_2 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_3_2), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_3_3) +); + +weight_cache_2048_8_0_weight_init_43 weight_cache_2048_8_0_weight_init_43_inst_3_4 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_3_4), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_3_5) +); + +weight_cache_2048_8_0_weight_init_63 weight_cache_2048_8_0_weight_init_63_inst_3_6 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_3_6), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_3_7) +); + +weight_cache_2048_8_0_weight_init_04 weight_cache_2048_8_0_weight_init_04_inst_4_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_4_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_4_1) +); + +weight_cache_2048_8_0_weight_init_24 weight_cache_2048_8_0_weight_init_24_inst_4_2 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_4_2), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_4_3) +); + +weight_cache_2048_8_0_weight_init_44 weight_cache_2048_8_0_weight_init_44_inst_4_4 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_4_4), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_4_5) +); + +weight_cache_2048_8_0_weight_init_64 weight_cache_2048_8_0_weight_init_64_inst_4_6 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_4_6), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_4_7) +); + +weight_cache_2048_8_0_weight_init_05 weight_cache_2048_8_0_weight_init_05_inst_5_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_5_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_5_1) +); + +weight_cache_2048_8_0_weight_init_25 weight_cache_2048_8_0_weight_init_25_inst_5_2 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_5_2), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_5_3) +); + +weight_cache_2048_8_0_weight_init_45 weight_cache_2048_8_0_weight_init_45_inst_5_4 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_5_4), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_5_5) +); + +weight_cache_2048_8_0_weight_init_65 weight_cache_2048_8_0_weight_init_65_inst_5_6 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_5_6), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_5_7) +); + +assign o_features_0_0 = if_reg_0_0; +assign features_0_0 = i_features_0_0; +assign o_features_1_0 = if_reg_0_1; +assign features_0_1 = i_features_1_0; +assign o_features_2_0 = if_reg_0_2; +assign features_0_2 = i_features_2_0; +assign o_features_3_0 = if_reg_0_3; +assign features_0_3 = i_features_3_0; +assign o_features_4_0 = if_reg_0_4; +assign features_0_4 = i_features_4_0; +assign o_features_5_0 = if_reg_0_5; +assign features_0_5 = i_features_5_0; +assign o_features_6_0 = if_reg_0_6; +assign features_0_6 = i_features_6_0; +assign o_features_7_0 = if_reg_0_7; +assign features_0_7 = i_features_7_0; +assign o_features_0_1 = if_reg_1_0; +assign features_1_0 = i_features_0_1; +assign o_features_1_1 = if_reg_1_1; +assign features_1_1 = i_features_1_1; +assign o_features_2_1 = if_reg_1_2; +assign features_1_2 = i_features_2_1; +assign o_features_3_1 = if_reg_1_3; +assign features_1_3 = i_features_3_1; +assign o_features_4_1 = if_reg_1_4; +assign features_1_4 = i_features_4_1; +assign o_features_5_1 = if_reg_1_5; +assign features_1_5 = i_features_5_1; +assign o_features_6_1 = if_reg_1_6; +assign features_1_6 = i_features_6_1; +assign o_features_7_1 = if_reg_1_7; +assign features_1_7 = i_features_7_1; +assign o_features_0_2 = if_reg_2_0; +assign features_2_0 = i_features_0_2; +assign o_features_1_2 = if_reg_2_1; +assign features_2_1 = i_features_1_2; +assign o_features_2_2 = if_reg_2_2; +assign features_2_2 = i_features_2_2; +assign o_features_3_2 = if_reg_2_3; +assign features_2_3 = i_features_3_2; +assign o_features_4_2 = if_reg_2_4; +assign features_2_4 = i_features_4_2; +assign o_features_5_2 = if_reg_2_5; +assign features_2_5 = i_features_5_2; +assign o_features_6_2 = if_reg_2_6; +assign features_2_6 = i_features_6_2; +assign o_features_7_2 = if_reg_2_7; +assign features_2_7 = i_features_7_2; +assign o_features_0_3 = if_reg_3_0; +assign features_3_0 = i_features_0_3; +assign o_features_1_3 = if_reg_3_1; +assign features_3_1 = i_features_1_3; +assign o_features_2_3 = if_reg_3_2; +assign features_3_2 = i_features_2_3; +assign o_features_3_3 = if_reg_3_3; +assign features_3_3 = i_features_3_3; +assign o_features_4_3 = if_reg_3_4; +assign features_3_4 = i_features_4_3; +assign o_features_5_3 = if_reg_3_5; +assign features_3_5 = i_features_5_3; +assign o_features_6_3 = if_reg_3_6; +assign features_3_6 = i_features_6_3; +assign o_features_7_3 = if_reg_3_7; +assign features_3_7 = i_features_7_3; +assign o_features_0_4 = if_reg_4_0; +assign features_4_0 = i_features_0_4; +assign o_features_1_4 = if_reg_4_1; +assign features_4_1 = i_features_1_4; +assign o_features_2_4 = if_reg_4_2; +assign features_4_2 = i_features_2_4; +assign o_features_3_4 = if_reg_4_3; +assign features_4_3 = i_features_3_4; +assign o_features_4_4 = if_reg_4_4; +assign features_4_4 = i_features_4_4; +assign o_features_5_4 = if_reg_4_5; +assign features_4_5 = i_features_5_4; +assign o_features_6_4 = if_reg_4_6; +assign features_4_6 = i_features_6_4; +assign o_features_7_4 = if_reg_4_7; +assign features_4_7 = i_features_7_4; +assign o_features_0_5 = if_reg_5_0; +assign features_5_0 = i_features_0_5; +assign o_features_1_5 = if_reg_5_1; +assign features_5_1 = i_features_1_5; +assign o_features_2_5 = if_reg_5_2; +assign features_5_2 = i_features_2_5; +assign o_features_3_5 = if_reg_5_3; +assign features_5_3 = i_features_3_5; +assign o_features_4_5 = if_reg_5_4; +assign features_5_4 = i_features_4_5; +assign o_features_5_5 = if_reg_5_5; +assign features_5_5 = i_features_5_5; +assign o_features_6_5 = if_reg_5_6; +assign features_5_6 = i_features_6_5; +assign o_features_7_5 = if_reg_5_7; +assign features_5_7 = i_features_7_5; + +assign o_valid = done_6; +assign o_next_reset = next_reset; +assign o_next_valid = next_valid; + +endmodule + +module weight_cache_2048_8_0_weight_init_21 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_20 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_23 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_22 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_25 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_24 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_45 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_44 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_43 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_42 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_41 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_40 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_03 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_64 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_01 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_00 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_61 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_60 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_63 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_04 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_65 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_02 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module dot_product_16_8_30_8 ( + input clk, + input i_reset, + input [15:0] i_features_0, + input [7:0] i_weights_0, + input [15:0] i_features_1, + input [7:0] i_weights_1, + input [15:0] i_features_2, + input [7:0] i_weights_2, + input [15:0] i_features_3, + input [7:0] i_weights_3, + input [15:0] i_features_4, + input [7:0] i_weights_4, + input [15:0] i_features_5, + input [7:0] i_weights_5, + input [15:0] i_features_6, + input [7:0] i_weights_6, + input [15:0] i_features_7, + input [7:0] i_weights_7, + output [23:0] o_result +); + +wire [63:0] chains_0; +wire [63:0] chains_1; +wire [63:0] chains_2; +wire [63:0] chains_3; +wire [23:0] res; +reg [15:0] f_pipeline_0_0; +reg [7:0] w_pipeline_0_0; +reg [15:0] f_pipeline_0_1; +reg [7:0] w_pipeline_0_1; +reg [15:0] f_pipeline_0_2; +reg [7:0] w_pipeline_0_2; +reg [15:0] f_pipeline_0_3; +reg [7:0] w_pipeline_0_3; +reg [15:0] f_pipeline_1_0; +reg [7:0] w_pipeline_1_0; +reg [15:0] f_pipeline_1_1; +reg [7:0] w_pipeline_1_1; +reg [15:0] f_pipeline_1_2; +reg [7:0] w_pipeline_1_2; +reg [15:0] f_pipeline_1_3; +reg [7:0] w_pipeline_1_3; +reg [15:0] f_pipeline_2_0; +reg [7:0] w_pipeline_2_0; +reg [15:0] f_pipeline_2_1; +reg [7:0] w_pipeline_2_1; +reg [15:0] f_pipeline_2_2; +reg [7:0] w_pipeline_2_2; +reg [15:0] f_pipeline_2_3; +reg [7:0] w_pipeline_2_3; +reg [15:0] f_pipeline_3_0; +reg [7:0] w_pipeline_3_0; +reg [15:0] f_pipeline_3_1; +reg [7:0] w_pipeline_3_1; +reg [15:0] f_pipeline_3_2; +reg [7:0] w_pipeline_3_2; +reg [15:0] f_pipeline_3_3; +reg [7:0] w_pipeline_3_3; +reg [15:0] f_pipeline_4_0; +reg [7:0] w_pipeline_4_0; +reg [15:0] f_pipeline_4_1; +reg [7:0] w_pipeline_4_1; +reg [15:0] f_pipeline_4_2; +reg [7:0] w_pipeline_4_2; +reg [15:0] f_pipeline_4_3; +reg [7:0] w_pipeline_4_3; +reg [15:0] f_pipeline_5_0; +reg [7:0] w_pipeline_5_0; +reg [15:0] f_pipeline_5_1; +reg [7:0] w_pipeline_5_1; +reg [15:0] f_pipeline_5_2; +reg [7:0] w_pipeline_5_2; +reg [15:0] f_pipeline_5_3; +reg [7:0] w_pipeline_5_3; +reg [15:0] f_pipeline_6_0; +reg [7:0] w_pipeline_6_0; +reg [15:0] f_pipeline_6_1; +reg [7:0] w_pipeline_6_1; +reg [15:0] f_pipeline_6_2; +reg [7:0] w_pipeline_6_2; +reg [15:0] f_pipeline_6_3; +reg [7:0] w_pipeline_6_3; +reg [15:0] f_pipeline_7_0; +reg [7:0] w_pipeline_7_0; +reg [15:0] f_pipeline_7_1; +reg [7:0] w_pipeline_7_1; +reg [15:0] f_pipeline_7_2; +reg [7:0] w_pipeline_7_2; +reg [15:0] f_pipeline_7_3; +reg [7:0] w_pipeline_7_3; +reg r_pipeline_0; +reg r_pipeline_1; +reg r_pipeline_2; +reg r_pipeline_3; + +always @ (posedge clk) begin + r_pipeline_0 <= i_reset; + if(i_reset == 1'b1) begin + f_pipeline_0_0 <= 0; + w_pipeline_0_0 <= 0; + f_pipeline_1_0 <= 0; + w_pipeline_1_0 <= 0; + f_pipeline_2_0 <= 0; + w_pipeline_2_0 <= 0; + f_pipeline_3_0 <= 0; + w_pipeline_3_0 <= 0; + f_pipeline_4_0 <= 0; + w_pipeline_4_0 <= 0; + f_pipeline_5_0 <= 0; + w_pipeline_5_0 <= 0; + f_pipeline_6_0 <= 0; + w_pipeline_6_0 <= 0; + f_pipeline_7_0 <= 0; + w_pipeline_7_0 <= 0; + f_pipeline_0_1 <= 0; + w_pipeline_0_1 <= 0; + f_pipeline_1_1 <= 0; + w_pipeline_1_1 <= 0; + f_pipeline_2_1 <= 0; + w_pipeline_2_1 <= 0; + f_pipeline_3_1 <= 0; + w_pipeline_3_1 <= 0; + f_pipeline_4_1 <= 0; + w_pipeline_4_1 <= 0; + f_pipeline_5_1 <= 0; + w_pipeline_5_1 <= 0; + f_pipeline_6_1 <= 0; + w_pipeline_6_1 <= 0; + f_pipeline_7_1 <= 0; + w_pipeline_7_1 <= 0; + f_pipeline_0_2 <= 0; + w_pipeline_0_2 <= 0; + f_pipeline_1_2 <= 0; + w_pipeline_1_2 <= 0; + f_pipeline_2_2 <= 0; + w_pipeline_2_2 <= 0; + f_pipeline_3_2 <= 0; + w_pipeline_3_2 <= 0; + f_pipeline_4_2 <= 0; + w_pipeline_4_2 <= 0; + f_pipeline_5_2 <= 0; + w_pipeline_5_2 <= 0; + f_pipeline_6_2 <= 0; + w_pipeline_6_2 <= 0; + f_pipeline_7_2 <= 0; + w_pipeline_7_2 <= 0; + f_pipeline_0_3 <= 0; + w_pipeline_0_3 <= 0; + f_pipeline_1_3 <= 0; + w_pipeline_1_3 <= 0; + f_pipeline_2_3 <= 0; + w_pipeline_2_3 <= 0; + f_pipeline_3_3 <= 0; + w_pipeline_3_3 <= 0; + f_pipeline_4_3 <= 0; + w_pipeline_4_3 <= 0; + f_pipeline_5_3 <= 0; + w_pipeline_5_3 <= 0; + f_pipeline_6_3 <= 0; + w_pipeline_6_3 <= 0; + f_pipeline_7_3 <= 0; + w_pipeline_7_3 <= 0; + r_pipeline_1 <= 1'b1; + r_pipeline_2 <= 1'b1; + r_pipeline_3 <= 1'b1; + end else begin + f_pipeline_0_0 <= i_features_0; + w_pipeline_0_0 <= i_weights_0; + f_pipeline_1_0 <= i_features_1; + w_pipeline_1_0 <= i_weights_1; + f_pipeline_2_0 <= i_features_2; + w_pipeline_2_0 <= i_weights_2; + f_pipeline_3_0 <= i_features_3; + w_pipeline_3_0 <= i_weights_3; + f_pipeline_4_0 <= i_features_4; + w_pipeline_4_0 <= i_weights_4; + f_pipeline_5_0 <= i_features_5; + w_pipeline_5_0 <= i_weights_5; + f_pipeline_6_0 <= i_features_6; + w_pipeline_6_0 <= i_weights_6; + f_pipeline_7_0 <= i_features_7; + w_pipeline_7_0 <= i_weights_7; + r_pipeline_1 <= r_pipeline_0; + f_pipeline_0_1 <= f_pipeline_0_0; + w_pipeline_0_1 <= w_pipeline_0_0; + f_pipeline_1_1 <= f_pipeline_1_0; + w_pipeline_1_1 <= w_pipeline_1_0; + f_pipeline_2_1 <= f_pipeline_2_0; + w_pipeline_2_1 <= w_pipeline_2_0; + f_pipeline_3_1 <= f_pipeline_3_0; + w_pipeline_3_1 <= w_pipeline_3_0; + f_pipeline_4_1 <= f_pipeline_4_0; + w_pipeline_4_1 <= w_pipeline_4_0; + f_pipeline_5_1 <= f_pipeline_5_0; + w_pipeline_5_1 <= w_pipeline_5_0; + f_pipeline_6_1 <= f_pipeline_6_0; + w_pipeline_6_1 <= w_pipeline_6_0; + f_pipeline_7_1 <= f_pipeline_7_0; + w_pipeline_7_1 <= w_pipeline_7_0; + r_pipeline_2 <= r_pipeline_1; + f_pipeline_0_2 <= f_pipeline_0_1; + w_pipeline_0_2 <= w_pipeline_0_1; + f_pipeline_1_2 <= f_pipeline_1_1; + w_pipeline_1_2 <= w_pipeline_1_1; + f_pipeline_2_2 <= f_pipeline_2_1; + w_pipeline_2_2 <= w_pipeline_2_1; + f_pipeline_3_2 <= f_pipeline_3_1; + w_pipeline_3_2 <= w_pipeline_3_1; + f_pipeline_4_2 <= f_pipeline_4_1; + w_pipeline_4_2 <= w_pipeline_4_1; + f_pipeline_5_2 <= f_pipeline_5_1; + w_pipeline_5_2 <= w_pipeline_5_1; + f_pipeline_6_2 <= f_pipeline_6_1; + w_pipeline_6_2 <= w_pipeline_6_1; + f_pipeline_7_2 <= f_pipeline_7_1; + w_pipeline_7_2 <= w_pipeline_7_1; + r_pipeline_3 <= r_pipeline_2; + f_pipeline_0_3 <= f_pipeline_0_2; + w_pipeline_0_3 <= w_pipeline_0_2; + f_pipeline_1_3 <= f_pipeline_1_2; + w_pipeline_1_3 <= w_pipeline_1_2; + f_pipeline_2_3 <= f_pipeline_2_2; + w_pipeline_2_3 <= w_pipeline_2_2; + f_pipeline_3_3 <= f_pipeline_3_2; + w_pipeline_3_3 <= w_pipeline_3_2; + f_pipeline_4_3 <= f_pipeline_4_2; + w_pipeline_4_3 <= w_pipeline_4_2; + f_pipeline_5_3 <= f_pipeline_5_2; + w_pipeline_5_3 <= w_pipeline_5_2; + f_pipeline_6_3 <= f_pipeline_6_2; + w_pipeline_6_3 <= w_pipeline_6_2; + f_pipeline_7_3 <= f_pipeline_7_2; + w_pipeline_7_3 <= w_pipeline_7_2; + end +end + +wire [23:0] dummy_res_0; +dsp_block_16_8_false dsp_block_16_8_false_inst_0 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ax(f_pipeline_0_0), + .ay(w_pipeline_0_0), + .bx(f_pipeline_1_0), + .by(w_pipeline_1_0), + .chainin(64'd0), + .chainout(chains_0), + .resulta(dummy_res_0) +); + +wire [23:0] dummy_res_2; +dsp_block_16_8_true dsp_block_16_8_true_inst_2 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ax(f_pipeline_2_1), + .ay(w_pipeline_2_1), + .bx(f_pipeline_3_1), + .by(w_pipeline_3_1), + .chainin(chains_0), + .chainout(chains_1), + .resulta(dummy_res_2) +); + +wire [23:0] dummy_res_4; +dsp_block_16_8_true dsp_block_16_8_true_inst_4 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ax(f_pipeline_4_2), + .ay(w_pipeline_4_2), + .bx(f_pipeline_5_2), + .by(w_pipeline_5_2), + .chainin(chains_1), + .chainout(chains_2), + .resulta(dummy_res_4) +); + +dsp_block_16_8_true dsp_block_16_8_true_inst_6 ( + .clk(clk), + .ena(1'b1), + .aclr(r_pipeline_3), + .ax(f_pipeline_6_3), + .ay(w_pipeline_6_3), + .bx(f_pipeline_7_3), + .by(w_pipeline_7_3), + .chainin(chains_2), + .chainout(chains_3), + .resulta(res) +); + +assign o_result = res; + +endmodule + +module dsp_block_16_8_true ( + input clk, + input ena, + input aclr, + input [15:0] ax, + input [7:0] ay, + input [15:0] bx, + input [7:0] by, + input [63:0] chainin, + output [63:0] chainout, + output [23:0] resulta +); + +wire [11:0] mode; +assign mode = 12'b1010_1010_0110; + +`ifdef complex_dsp +int_sop_2 mac_component ( + .mode_sigs(mode), + .clk(clk), + .reset(aclr), + .ax(ax), + .ay(ay), + .bx(bx), + .by(by), + .chainin(chainin), + .result(resulta), + .chainout(chainout) +); +`else +reg [15:0] ax_reg; +reg [7:0] ay_reg; +reg [15:0] bx_reg; +reg [7:0] by_reg; +reg [23:0] resulta_tmp; +always @(posedge clk) begin + if(aclr) begin + resulta_tmp <= 0; + ax_reg <= 0; + ay_reg <= 0; + bx_reg <= 0; + by_reg <= 0; + end + else begin + ax_reg <= ax; + ay_reg <= ay; + bx_reg <= bx; + by_reg <= by; + resulta_tmp <= ax_reg * ay_reg + bx_reg * by_reg + chainin; + end +end +assign resulta = resulta_tmp; +assign chainout = {40'b0, resulta_tmp}; +`endif + + +endmodule + +module dsp_block_16_8_false ( + input clk, + input ena, + input aclr, + input [15:0] ax, + input [7:0] ay, + input [15:0] bx, + input [7:0] by, + input [63:0] chainin, + output [63:0] chainout, + output [23:0] resulta +); + +wire [11:0] mode; +assign mode = 12'b1010_1010_0110; + +`ifdef complex_dsp +int_sop_2 mac_component ( + .mode_sigs(mode), + .clk(clk), + .reset(aclr), + .ax(ax), + .ay(ay), + .bx(bx), + .by(by), + .chainin(chainin), + .result(resulta), + .chainout(chainout) +); +`else +reg [15:0] ax_reg; +reg [7:0] ay_reg; +reg [15:0] bx_reg; +reg [7:0] by_reg; +reg [23:0] resulta_tmp; +always @(posedge clk) begin + if(aclr) begin + resulta_tmp <= 0; + ax_reg <= 0; + ay_reg <= 0; + bx_reg <= 0; + by_reg <= 0; + end + else begin + ax_reg <= ax; + ay_reg <= ay; + bx_reg <= bx; + by_reg <= by; + resulta_tmp <= ax_reg * ay_reg + bx_reg * by_reg + chainin; + end +end +assign resulta = resulta_tmp; +assign chainout = {40'b0, resulta_tmp}; +`endif + +endmodule + +module accumulator_24_30_6 ( + input clk, + input i_reset, + input [23:0] i_result, + input i_dp_done, + output [29:0] o_accum +); + +reg [29:0] cir_shift_reg_0; +reg [29:0] cir_shift_reg_1; +reg [29:0] cir_shift_reg_2; +reg [29:0] cir_shift_reg_3; +reg [29:0] cir_shift_reg_4; +reg [29:0] cir_shift_reg_5; +reg [29:0] out_reg; +reg [29:0] in_reg; + +always @ (posedge clk) begin + if(i_reset == 1'b1) begin + cir_shift_reg_0 <= 0; + cir_shift_reg_1 <= 0; + cir_shift_reg_2 <= 0; + cir_shift_reg_3 <= 0; + cir_shift_reg_4 <= 0; + cir_shift_reg_5 <= 0; + out_reg <= 0; + in_reg <= 0; + end else begin + if (i_result[23] == 1'b0) begin + in_reg <= {6'b000000, i_result}; + end else begin + in_reg <= {6'b111111, i_result}; + end + if(i_dp_done == 1'b1) begin + out_reg <= (cir_shift_reg_0 + in_reg); + cir_shift_reg_5 <= 0; + end else begin + cir_shift_reg_5 <= (cir_shift_reg_0 + in_reg); + end + cir_shift_reg_0 <= cir_shift_reg_1; + cir_shift_reg_1 <= cir_shift_reg_2; + cir_shift_reg_2 <= cir_shift_reg_3; + cir_shift_reg_3 <= cir_shift_reg_4; + cir_shift_reg_4 <= cir_shift_reg_5; + end +end + +assign o_accum = out_reg; + +endmodule + +module weight_cache_2048_8_0_weight_init_05 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_62 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module stream_buffer_1_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_11 buffer_16_6050_buffer_init_11_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_11 buffer_16_6050_buffer_init_11_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_11 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_1_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_01 buffer_16_6050_buffer_init_01_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_01 buffer_16_6050_buffer_init_01_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_01 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_1_3 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_31 buffer_16_6050_buffer_init_31_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_31 buffer_16_6050_buffer_init_31_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_31 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_1_2 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_21 buffer_16_6050_buffer_init_21_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_21 buffer_16_6050_buffer_init_21_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_21 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_1_5 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_51 buffer_16_6050_buffer_init_51_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_51 buffer_16_6050_buffer_init_51_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_51 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_1_4 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_41 buffer_16_6050_buffer_init_41_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_41 buffer_16_6050_buffer_init_41_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_41 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_1_7 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_71 buffer_16_6050_buffer_init_71_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_71 buffer_16_6050_buffer_init_71_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_71 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_1_6 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_61 buffer_16_6050_buffer_init_61_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_61 buffer_16_6050_buffer_init_61_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_61 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_3_7 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_73 buffer_16_6050_buffer_init_73_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_73 buffer_16_6050_buffer_init_73_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_73 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_3_6 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_63 buffer_16_6050_buffer_init_63_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_63 buffer_16_6050_buffer_init_63_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_63 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_3_5 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_53 buffer_16_6050_buffer_init_53_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_53 buffer_16_6050_buffer_init_53_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_53 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_3_4 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_43 buffer_16_6050_buffer_init_43_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_43 buffer_16_6050_buffer_init_43_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_43 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_3_3 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_33 buffer_16_6050_buffer_init_33_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_33 buffer_16_6050_buffer_init_33_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_33 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_3_2 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_23 buffer_16_6050_buffer_init_23_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_23 buffer_16_6050_buffer_init_23_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_23 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_3_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_13 buffer_16_6050_buffer_init_13_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_13 buffer_16_6050_buffer_init_13_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_13 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_3_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_03 buffer_16_6050_buffer_init_03_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_03 buffer_16_6050_buffer_init_03_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_03 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module inverse_winograd_33 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_19_0[29] == 1'b0) begin + result_wire_0 <= result_reg_19_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_19_1[29] == 1'b0) begin + result_wire_1 <= result_reg_19_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_19_2[29] == 1'b0) begin + result_wire_2 <= result_reg_19_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_19_3[29] == 1'b0) begin + result_wire_3 <= result_reg_19_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_19; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_adder_30_3 ( + input clock, + input [29:0] data0x, + input [29:0] data1x, + input [29:0] data2x, + input [29:0] data3x, + input [29:0] data4x, + input [29:0] data5x, + output [29:0] result +); + +reg [32:0] pipeline_0_0; +reg [32:0] pipeline_0_1; +reg [32:0] pipeline_0_2; +reg [32:0] pipeline_1_0; +reg [32:0] pipeline_1_1; +reg [32:0] pipeline_2_0; + +always @ (posedge clock) begin + pipeline_0_0 <= data0x + data1x; + pipeline_0_1 <= data2x + data3x; + pipeline_0_2 <= data4x + data5x; + pipeline_1_0 <= pipeline_0_0 + pipeline_0_1; + pipeline_1_1 <= pipeline_0_2; + pipeline_2_0 <= pipeline_1_0 + pipeline_1_1; +end + +assign result = pipeline_2_0; + +endmodule + +module inverse_winograd_32 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_20_0[29] == 1'b0) begin + result_wire_0 <= result_reg_20_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_20_1[29] == 1'b0) begin + result_wire_1 <= result_reg_20_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_20_2[29] == 1'b0) begin + result_wire_2 <= result_reg_20_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_20_3[29] == 1'b0) begin + result_wire_3 <= result_reg_20_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_20; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_31 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_21_0[29] == 1'b0) begin + result_wire_0 <= result_reg_21_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_21_1[29] == 1'b0) begin + result_wire_1 <= result_reg_21_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_21_2[29] == 1'b0) begin + result_wire_2 <= result_reg_21_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_21_3[29] == 1'b0) begin + result_wire_3 <= result_reg_21_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_21; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_30 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_22_0[29] == 1'b0) begin + result_wire_0 <= result_reg_22_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_22_1[29] == 1'b0) begin + result_wire_1 <= result_reg_22_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_22_2[29] == 1'b0) begin + result_wire_2 <= result_reg_22_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_22_3[29] == 1'b0) begin + result_wire_3 <= result_reg_22_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_22; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_37 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_15_0[29] == 1'b0) begin + result_wire_0 <= result_reg_15_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_15_1[29] == 1'b0) begin + result_wire_1 <= result_reg_15_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_15_2[29] == 1'b0) begin + result_wire_2 <= result_reg_15_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_15_3[29] == 1'b0) begin + result_wire_3 <= result_reg_15_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_15; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_36 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_16_0[29] == 1'b0) begin + result_wire_0 <= result_reg_16_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_16_1[29] == 1'b0) begin + result_wire_1 <= result_reg_16_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_16_2[29] == 1'b0) begin + result_wire_2 <= result_reg_16_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_16_3[29] == 1'b0) begin + result_wire_3 <= result_reg_16_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_16; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_35 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_17_0[29] == 1'b0) begin + result_wire_0 <= result_reg_17_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_17_1[29] == 1'b0) begin + result_wire_1 <= result_reg_17_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_17_2[29] == 1'b0) begin + result_wire_2 <= result_reg_17_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_17_3[29] == 1'b0) begin + result_wire_3 <= result_reg_17_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_17; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_34 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_18_0[29] == 1'b0) begin + result_wire_0 <= result_reg_18_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_18_1[29] == 1'b0) begin + result_wire_1 <= result_reg_18_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_18_2[29] == 1'b0) begin + result_wire_2 <= result_reg_18_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_18_3[29] == 1'b0) begin + result_wire_3 <= result_reg_18_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_18; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_39 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_13_0[29] == 1'b0) begin + result_wire_0 <= result_reg_13_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_13_1[29] == 1'b0) begin + result_wire_1 <= result_reg_13_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_13_2[29] == 1'b0) begin + result_wire_2 <= result_reg_13_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_13_3[29] == 1'b0) begin + result_wire_3 <= result_reg_13_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_13; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_38 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_14_0[29] == 1'b0) begin + result_wire_0 <= result_reg_14_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_14_1[29] == 1'b0) begin + result_wire_1 <= result_reg_14_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_14_2[29] == 1'b0) begin + result_wire_2 <= result_reg_14_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_14_3[29] == 1'b0) begin + result_wire_3 <= result_reg_14_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_14; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_46 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_6_0[29] == 1'b0) begin + result_wire_0 <= result_reg_6_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_6_1[29] == 1'b0) begin + result_wire_1 <= result_reg_6_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_6_2[29] == 1'b0) begin + result_wire_2 <= result_reg_6_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_6_3[29] == 1'b0) begin + result_wire_3 <= result_reg_6_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_6; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_47 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_5_0[29] == 1'b0) begin + result_wire_0 <= result_reg_5_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_5_1[29] == 1'b0) begin + result_wire_1 <= result_reg_5_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_5_2[29] == 1'b0) begin + result_wire_2 <= result_reg_5_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_5_3[29] == 1'b0) begin + result_wire_3 <= result_reg_5_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_5; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_44 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_8_0[29] == 1'b0) begin + result_wire_0 <= result_reg_8_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_8_1[29] == 1'b0) begin + result_wire_1 <= result_reg_8_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_8_2[29] == 1'b0) begin + result_wire_2 <= result_reg_8_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_8_3[29] == 1'b0) begin + result_wire_3 <= result_reg_8_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_8; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_45 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_7_0[29] == 1'b0) begin + result_wire_0 <= result_reg_7_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_7_1[29] == 1'b0) begin + result_wire_1 <= result_reg_7_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_7_2[29] == 1'b0) begin + result_wire_2 <= result_reg_7_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_7_3[29] == 1'b0) begin + result_wire_3 <= result_reg_7_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_7; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_42 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_10_0[29] == 1'b0) begin + result_wire_0 <= result_reg_10_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_10_1[29] == 1'b0) begin + result_wire_1 <= result_reg_10_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_10_2[29] == 1'b0) begin + result_wire_2 <= result_reg_10_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_10_3[29] == 1'b0) begin + result_wire_3 <= result_reg_10_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_10; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_43 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_9_0[29] == 1'b0) begin + result_wire_0 <= result_reg_9_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_9_1[29] == 1'b0) begin + result_wire_1 <= result_reg_9_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_9_2[29] == 1'b0) begin + result_wire_2 <= result_reg_9_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_9_3[29] == 1'b0) begin + result_wire_3 <= result_reg_9_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_9; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_40 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_12_0[29] == 1'b0) begin + result_wire_0 <= result_reg_12_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_12_1[29] == 1'b0) begin + result_wire_1 <= result_reg_12_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_12_2[29] == 1'b0) begin + result_wire_2 <= result_reg_12_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_12_3[29] == 1'b0) begin + result_wire_3 <= result_reg_12_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_12; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_41 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_11_0[29] == 1'b0) begin + result_wire_0 <= result_reg_11_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_11_1[29] == 1'b0) begin + result_wire_1 <= result_reg_11_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_11_2[29] == 1'b0) begin + result_wire_2 <= result_reg_11_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_11_3[29] == 1'b0) begin + result_wire_3 <= result_reg_11_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_11; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module stream_buffer_5_5 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_55 buffer_16_6050_buffer_init_55_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_55 buffer_16_6050_buffer_init_55_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_55 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_5_4 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_45 buffer_16_6050_buffer_init_45_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_45 buffer_16_6050_buffer_init_45_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_45 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_5_7 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_75 buffer_16_6050_buffer_init_75_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_75 buffer_16_6050_buffer_init_75_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_75 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_5_6 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_65 buffer_16_6050_buffer_init_65_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_65 buffer_16_6050_buffer_init_65_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_65 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_5_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_15 buffer_16_6050_buffer_init_15_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_15 buffer_16_6050_buffer_init_15_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_15 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_5_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_05 buffer_16_6050_buffer_init_05_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_05 buffer_16_6050_buffer_init_05_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_05 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_5_3 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_35 buffer_16_6050_buffer_init_35_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_35 buffer_16_6050_buffer_init_35_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_35 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_5_2 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_25 buffer_16_6050_buffer_init_25_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_25 buffer_16_6050_buffer_init_25_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_25 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_2_6 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_62 buffer_16_6050_buffer_init_62_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_62 buffer_16_6050_buffer_init_62_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_62 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_2_7 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_72 buffer_16_6050_buffer_init_72_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_72 buffer_16_6050_buffer_init_72_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_72 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_2_4 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_42 buffer_16_6050_buffer_init_42_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_42 buffer_16_6050_buffer_init_42_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_42 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_2_5 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_52 buffer_16_6050_buffer_init_52_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_52 buffer_16_6050_buffer_init_52_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_52 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_2_2 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_22 buffer_16_6050_buffer_init_22_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_22 buffer_16_6050_buffer_init_22_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_22 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_2_3 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_32 buffer_16_6050_buffer_init_32_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_32 buffer_16_6050_buffer_init_32_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_32 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_2_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_02 buffer_16_6050_buffer_init_02_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_02 buffer_16_6050_buffer_init_02_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_02 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_2_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_12 buffer_16_6050_buffer_init_12_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_12 buffer_16_6050_buffer_init_12_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_12 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module inverse_winograd_20 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_32_0[29] == 1'b0) begin + result_wire_0 <= result_reg_32_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_32_1[29] == 1'b0) begin + result_wire_1 <= result_reg_32_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_32_2[29] == 1'b0) begin + result_wire_2 <= result_reg_32_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_32_3[29] == 1'b0) begin + result_wire_3 <= result_reg_32_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_32; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_21 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_31_0[29] == 1'b0) begin + result_wire_0 <= result_reg_31_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_31_1[29] == 1'b0) begin + result_wire_1 <= result_reg_31_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_31_2[29] == 1'b0) begin + result_wire_2 <= result_reg_31_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_31_3[29] == 1'b0) begin + result_wire_3 <= result_reg_31_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_31; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_22 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_30_0[29] == 1'b0) begin + result_wire_0 <= result_reg_30_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_30_1[29] == 1'b0) begin + result_wire_1 <= result_reg_30_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_30_2[29] == 1'b0) begin + result_wire_2 <= result_reg_30_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_30_3[29] == 1'b0) begin + result_wire_3 <= result_reg_30_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_30; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_23 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_29_0[29] == 1'b0) begin + result_wire_0 <= result_reg_29_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_29_1[29] == 1'b0) begin + result_wire_1 <= result_reg_29_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_29_2[29] == 1'b0) begin + result_wire_2 <= result_reg_29_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_29_3[29] == 1'b0) begin + result_wire_3 <= result_reg_29_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_29; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_24 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_28_0[29] == 1'b0) begin + result_wire_0 <= result_reg_28_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_28_1[29] == 1'b0) begin + result_wire_1 <= result_reg_28_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_28_2[29] == 1'b0) begin + result_wire_2 <= result_reg_28_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_28_3[29] == 1'b0) begin + result_wire_3 <= result_reg_28_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_28; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_25 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_27_0[29] == 1'b0) begin + result_wire_0 <= result_reg_27_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_27_1[29] == 1'b0) begin + result_wire_1 <= result_reg_27_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_27_2[29] == 1'b0) begin + result_wire_2 <= result_reg_27_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_27_3[29] == 1'b0) begin + result_wire_3 <= result_reg_27_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_27; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_26 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_26_0[29] == 1'b0) begin + result_wire_0 <= result_reg_26_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_26_1[29] == 1'b0) begin + result_wire_1 <= result_reg_26_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_26_2[29] == 1'b0) begin + result_wire_2 <= result_reg_26_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_26_3[29] == 1'b0) begin + result_wire_3 <= result_reg_26_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_26; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_27 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_25_0[29] == 1'b0) begin + result_wire_0 <= result_reg_25_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_25_1[29] == 1'b0) begin + result_wire_1 <= result_reg_25_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_25_2[29] == 1'b0) begin + result_wire_2 <= result_reg_25_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_25_3[29] == 1'b0) begin + result_wire_3 <= result_reg_25_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_25; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module stream_buffer_0_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_00 buffer_16_6050_buffer_init_00_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_00 buffer_16_6050_buffer_init_00_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_00 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_0_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_10 buffer_16_6050_buffer_init_10_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_10 buffer_16_6050_buffer_init_10_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_10 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_0_2 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_20 buffer_16_6050_buffer_init_20_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_20 buffer_16_6050_buffer_init_20_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_20 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_0_3 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_30 buffer_16_6050_buffer_init_30_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_30 buffer_16_6050_buffer_init_30_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_30 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_0_4 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_40 buffer_16_6050_buffer_init_40_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_40 buffer_16_6050_buffer_init_40_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_40 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_0_5 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_50 buffer_16_6050_buffer_init_50_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_50 buffer_16_6050_buffer_init_50_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_50 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_0_6 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_60 buffer_16_6050_buffer_init_60_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_60 buffer_16_6050_buffer_init_60_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_60 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_0_7 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_70 buffer_16_6050_buffer_init_70_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_70 buffer_16_6050_buffer_init_70_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_70 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module pooling ( + input clk, + input i_valid, + input i_reset, + input [15:0] i_result_0, + input [15:0] i_result_1, + input [15:0] i_result_2, + input [15:0] i_result_3, + output [15:0] o_result, + output o_valid +); + +reg [15:0] buffer_0_0; +reg [15:0] buffer_0_1; +reg [15:0] buffer_1_0; +reg [15:0] buffer_1_1; +reg [1:0] count; +reg [0:0] s_count; +reg [15:0] result_0; +reg [15:0] result_1; +reg valid_1, valid_2, valid_3; + +always @(posedge clk) begin + buffer_0_1 <= buffer_0_0; + buffer_1_1 <= buffer_1_0; + valid_1 <= i_valid; + valid_2 <= valid_1; + valid_3 <= valid_2; + if (i_valid) begin + count <= 0; + end else begin + if(count == 3) begin + count <= 0; + end else begin + count <= count + 1'b1; + end + if(i_result_0 > i_result_1) begin + buffer_0_0 <= i_result_0; + end else begin + buffer_0_0 <= i_result_1; + end + if(i_result_2 > i_result_3) begin + buffer_1_0 <= i_result_2; + end else begin + buffer_1_0 <= i_result_3; + end + end +end + +always @(posedge clk) begin + if (i_reset) begin + s_count <= 0; + end else if (valid_1 || valid_2) begin + if (s_count == 1) begin + if (buffer_0_0 > buffer_0_1) begin + result_0 <= buffer_0_0; + end else begin + result_0 <= buffer_0_1; + end + if (buffer_1_0 > buffer_1_1) begin + result_1 <= buffer_1_0; + end else begin + result_1 <= buffer_1_1; + end + s_count <= 0; + end else begin + result_0 <= result_1; + s_count <= s_count + 1'b1; + end + end else begin + s_count <= 0; + end +end + +assign o_result = result_0; +assign o_valid = valid_3; + +endmodule + +module inverse_winograd_15 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_37_0[29] == 1'b0) begin + result_wire_0 <= result_reg_37_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_37_1[29] == 1'b0) begin + result_wire_1 <= result_reg_37_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_37_2[29] == 1'b0) begin + result_wire_2 <= result_reg_37_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_37_3[29] == 1'b0) begin + result_wire_3 <= result_reg_37_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_37; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_14 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; +reg [29:0] result_reg_38_0; +reg [29:0] result_reg_38_1; +reg [29:0] result_reg_38_2; +reg [29:0] result_reg_38_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg out_valid_38; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; + out_valid_38 <= out_valid_37; + result_reg_38_0 <= result_reg_37_0; + result_reg_38_1 <= result_reg_37_1; + result_reg_38_2 <= result_reg_37_2; + result_reg_38_3 <= result_reg_37_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_38_0[29] == 1'b0) begin + result_wire_0 <= result_reg_38_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_38_1[29] == 1'b0) begin + result_wire_1 <= result_reg_38_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_38_2[29] == 1'b0) begin + result_wire_2 <= result_reg_38_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_38_3[29] == 1'b0) begin + result_wire_3 <= result_reg_38_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_38; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_17 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_35_0[29] == 1'b0) begin + result_wire_0 <= result_reg_35_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_35_1[29] == 1'b0) begin + result_wire_1 <= result_reg_35_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_35_2[29] == 1'b0) begin + result_wire_2 <= result_reg_35_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_35_3[29] == 1'b0) begin + result_wire_3 <= result_reg_35_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_35; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_16 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_36_0[29] == 1'b0) begin + result_wire_0 <= result_reg_36_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_36_1[29] == 1'b0) begin + result_wire_1 <= result_reg_36_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_36_2[29] == 1'b0) begin + result_wire_2 <= result_reg_36_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_36_3[29] == 1'b0) begin + result_wire_3 <= result_reg_36_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_36; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_11 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; +reg [29:0] result_reg_38_0; +reg [29:0] result_reg_38_1; +reg [29:0] result_reg_38_2; +reg [29:0] result_reg_38_3; +reg [29:0] result_reg_39_0; +reg [29:0] result_reg_39_1; +reg [29:0] result_reg_39_2; +reg [29:0] result_reg_39_3; +reg [29:0] result_reg_40_0; +reg [29:0] result_reg_40_1; +reg [29:0] result_reg_40_2; +reg [29:0] result_reg_40_3; +reg [29:0] result_reg_41_0; +reg [29:0] result_reg_41_1; +reg [29:0] result_reg_41_2; +reg [29:0] result_reg_41_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg out_valid_38; +reg out_valid_39; +reg out_valid_40; +reg out_valid_41; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; + out_valid_38 <= out_valid_37; + result_reg_38_0 <= result_reg_37_0; + result_reg_38_1 <= result_reg_37_1; + result_reg_38_2 <= result_reg_37_2; + result_reg_38_3 <= result_reg_37_3; + out_valid_39 <= out_valid_38; + result_reg_39_0 <= result_reg_38_0; + result_reg_39_1 <= result_reg_38_1; + result_reg_39_2 <= result_reg_38_2; + result_reg_39_3 <= result_reg_38_3; + out_valid_40 <= out_valid_39; + result_reg_40_0 <= result_reg_39_0; + result_reg_40_1 <= result_reg_39_1; + result_reg_40_2 <= result_reg_39_2; + result_reg_40_3 <= result_reg_39_3; + out_valid_41 <= out_valid_40; + result_reg_41_0 <= result_reg_40_0; + result_reg_41_1 <= result_reg_40_1; + result_reg_41_2 <= result_reg_40_2; + result_reg_41_3 <= result_reg_40_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_41_0[29] == 1'b0) begin + result_wire_0 <= result_reg_41_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_41_1[29] == 1'b0) begin + result_wire_1 <= result_reg_41_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_41_2[29] == 1'b0) begin + result_wire_2 <= result_reg_41_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_41_3[29] == 1'b0) begin + result_wire_3 <= result_reg_41_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_41; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_10 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; +reg [29:0] result_reg_38_0; +reg [29:0] result_reg_38_1; +reg [29:0] result_reg_38_2; +reg [29:0] result_reg_38_3; +reg [29:0] result_reg_39_0; +reg [29:0] result_reg_39_1; +reg [29:0] result_reg_39_2; +reg [29:0] result_reg_39_3; +reg [29:0] result_reg_40_0; +reg [29:0] result_reg_40_1; +reg [29:0] result_reg_40_2; +reg [29:0] result_reg_40_3; +reg [29:0] result_reg_41_0; +reg [29:0] result_reg_41_1; +reg [29:0] result_reg_41_2; +reg [29:0] result_reg_41_3; +reg [29:0] result_reg_42_0; +reg [29:0] result_reg_42_1; +reg [29:0] result_reg_42_2; +reg [29:0] result_reg_42_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg out_valid_38; +reg out_valid_39; +reg out_valid_40; +reg out_valid_41; +reg out_valid_42; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; + out_valid_38 <= out_valid_37; + result_reg_38_0 <= result_reg_37_0; + result_reg_38_1 <= result_reg_37_1; + result_reg_38_2 <= result_reg_37_2; + result_reg_38_3 <= result_reg_37_3; + out_valid_39 <= out_valid_38; + result_reg_39_0 <= result_reg_38_0; + result_reg_39_1 <= result_reg_38_1; + result_reg_39_2 <= result_reg_38_2; + result_reg_39_3 <= result_reg_38_3; + out_valid_40 <= out_valid_39; + result_reg_40_0 <= result_reg_39_0; + result_reg_40_1 <= result_reg_39_1; + result_reg_40_2 <= result_reg_39_2; + result_reg_40_3 <= result_reg_39_3; + out_valid_41 <= out_valid_40; + result_reg_41_0 <= result_reg_40_0; + result_reg_41_1 <= result_reg_40_1; + result_reg_41_2 <= result_reg_40_2; + result_reg_41_3 <= result_reg_40_3; + out_valid_42 <= out_valid_41; + result_reg_42_0 <= result_reg_41_0; + result_reg_42_1 <= result_reg_41_1; + result_reg_42_2 <= result_reg_41_2; + result_reg_42_3 <= result_reg_41_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_42_0[29] == 1'b0) begin + result_wire_0 <= result_reg_42_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_42_1[29] == 1'b0) begin + result_wire_1 <= result_reg_42_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_42_2[29] == 1'b0) begin + result_wire_2 <= result_reg_42_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_42_3[29] == 1'b0) begin + result_wire_3 <= result_reg_42_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_42; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_13 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; +reg [29:0] result_reg_38_0; +reg [29:0] result_reg_38_1; +reg [29:0] result_reg_38_2; +reg [29:0] result_reg_38_3; +reg [29:0] result_reg_39_0; +reg [29:0] result_reg_39_1; +reg [29:0] result_reg_39_2; +reg [29:0] result_reg_39_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg out_valid_38; +reg out_valid_39; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; + out_valid_38 <= out_valid_37; + result_reg_38_0 <= result_reg_37_0; + result_reg_38_1 <= result_reg_37_1; + result_reg_38_2 <= result_reg_37_2; + result_reg_38_3 <= result_reg_37_3; + out_valid_39 <= out_valid_38; + result_reg_39_0 <= result_reg_38_0; + result_reg_39_1 <= result_reg_38_1; + result_reg_39_2 <= result_reg_38_2; + result_reg_39_3 <= result_reg_38_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_39_0[29] == 1'b0) begin + result_wire_0 <= result_reg_39_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_39_1[29] == 1'b0) begin + result_wire_1 <= result_reg_39_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_39_2[29] == 1'b0) begin + result_wire_2 <= result_reg_39_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_39_3[29] == 1'b0) begin + result_wire_3 <= result_reg_39_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_39; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_12 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; +reg [29:0] result_reg_38_0; +reg [29:0] result_reg_38_1; +reg [29:0] result_reg_38_2; +reg [29:0] result_reg_38_3; +reg [29:0] result_reg_39_0; +reg [29:0] result_reg_39_1; +reg [29:0] result_reg_39_2; +reg [29:0] result_reg_39_3; +reg [29:0] result_reg_40_0; +reg [29:0] result_reg_40_1; +reg [29:0] result_reg_40_2; +reg [29:0] result_reg_40_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg out_valid_38; +reg out_valid_39; +reg out_valid_40; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; + out_valid_38 <= out_valid_37; + result_reg_38_0 <= result_reg_37_0; + result_reg_38_1 <= result_reg_37_1; + result_reg_38_2 <= result_reg_37_2; + result_reg_38_3 <= result_reg_37_3; + out_valid_39 <= out_valid_38; + result_reg_39_0 <= result_reg_38_0; + result_reg_39_1 <= result_reg_38_1; + result_reg_39_2 <= result_reg_38_2; + result_reg_39_3 <= result_reg_38_3; + out_valid_40 <= out_valid_39; + result_reg_40_0 <= result_reg_39_0; + result_reg_40_1 <= result_reg_39_1; + result_reg_40_2 <= result_reg_39_2; + result_reg_40_3 <= result_reg_39_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_40_0[29] == 1'b0) begin + result_wire_0 <= result_reg_40_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_40_1[29] == 1'b0) begin + result_wire_1 <= result_reg_40_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_40_2[29] == 1'b0) begin + result_wire_2 <= result_reg_40_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_40_3[29] == 1'b0) begin + result_wire_3 <= result_reg_40_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_40; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_19 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_33_0[29] == 1'b0) begin + result_wire_0 <= result_reg_33_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_33_1[29] == 1'b0) begin + result_wire_1 <= result_reg_33_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_33_2[29] == 1'b0) begin + result_wire_2 <= result_reg_33_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_33_3[29] == 1'b0) begin + result_wire_3 <= result_reg_33_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_33; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_18 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_34_0[29] == 1'b0) begin + result_wire_0 <= result_reg_34_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_34_1[29] == 1'b0) begin + result_wire_1 <= result_reg_34_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_34_2[29] == 1'b0) begin + result_wire_2 <= result_reg_34_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_34_3[29] == 1'b0) begin + result_wire_3 <= result_reg_34_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_34; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_28 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_24_0[29] == 1'b0) begin + result_wire_0 <= result_reg_24_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_24_1[29] == 1'b0) begin + result_wire_1 <= result_reg_24_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_24_2[29] == 1'b0) begin + result_wire_2 <= result_reg_24_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_24_3[29] == 1'b0) begin + result_wire_3 <= result_reg_24_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_24; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module stream_buffer_4_4 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_44 buffer_16_6050_buffer_init_44_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_44 buffer_16_6050_buffer_init_44_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_44 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_4_5 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_54 buffer_16_6050_buffer_init_54_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_54 buffer_16_6050_buffer_init_54_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_54 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_4_6 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_64 buffer_16_6050_buffer_init_64_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_64 buffer_16_6050_buffer_init_64_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_64 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_4_7 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_74 buffer_16_6050_buffer_init_74_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_74 buffer_16_6050_buffer_init_74_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_74 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_4_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_04 buffer_16_6050_buffer_init_04_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_04 buffer_16_6050_buffer_init_04_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_04 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_4_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_14 buffer_16_6050_buffer_init_14_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_14 buffer_16_6050_buffer_init_14_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_14 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_4_2 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_24 buffer_16_6050_buffer_init_24_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_24 buffer_16_6050_buffer_init_24_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_24 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_4_3 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [12:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [12:0] base_addr; +reg [12:0] offset; +reg [12:0] base_addr_b1; +reg [12:0] offset_b1; +reg [2:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [2:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 5)) begin + base_addr <= base_addr + 6; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 5) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 5)) begin + base_addr_b1 <= base_addr_b1 + 6; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 5) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 5)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [12:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_6050_buffer_init_34 buffer_16_6050_buffer_init_34_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_6050_buffer_init_34 buffer_16_6050_buffer_init_34_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_6050_buffer_init_34 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module inverse_winograd_29 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_23_0[29] == 1'b0) begin + result_wire_0 <= result_reg_23_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_23_1[29] == 1'b0) begin + result_wire_1 <= result_reg_23_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_23_2[29] == 1'b0) begin + result_wire_2 <= result_reg_23_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_23_3[29] == 1'b0) begin + result_wire_3 <= result_reg_23_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_23; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module store_output ( + input clk, + input i_valid, + input i_reset, + input [15:0] i_result_0, + input [15:0] i_result_1, + input [15:0] i_result_2, + input [15:0] i_result_3, + input [15:0] i_result_4, + input [15:0] i_result_5, + input [15:0] i_result_6, + input [15:0] i_result_7, + input [15:0] i_result_8, + input [15:0] i_result_9, + input [15:0] i_result_10, + input [15:0] i_result_11, + input [15:0] i_result_12, + input [15:0] i_result_13, + input [15:0] i_result_14, + input [15:0] i_result_15, + input [15:0] i_result_16, + input [15:0] i_result_17, + input [15:0] i_result_18, + input [15:0] i_result_19, + input [15:0] i_result_20, + input [15:0] i_result_21, + input [15:0] i_result_22, + input [15:0] i_result_23, + input [15:0] i_result_24, + input [15:0] i_result_25, + input [15:0] i_result_26, + input [15:0] i_result_27, + input [15:0] i_result_28, + input [15:0] i_result_29, + input [15:0] i_result_30, + input [15:0] i_result_31, + input [15:0] i_result_32, + input [15:0] i_result_33, + input [15:0] i_result_34, + input [15:0] i_result_35, + input [15:0] i_result_36, + input [15:0] i_result_37, + input [15:0] i_result_38, + input [15:0] i_result_39, + input [15:0] i_result_40, + input [15:0] i_result_41, + input [15:0] i_result_42, + input [15:0] i_result_43, + input [15:0] i_result_44, + input [15:0] i_result_45, + input [15:0] i_result_46, + input [15:0] i_result_47, + output [15:0] o_store_0_0, + output [15:0] o_store_0_1, + output [15:0] o_store_0_2, + output [15:0] o_store_0_3, + output [15:0] o_store_0_4, + output [15:0] o_store_0_5, + output [15:0] o_store_0_6, + output [15:0] o_store_0_7, + output [15:0] o_store_1_0, + output [15:0] o_store_1_1, + output [15:0] o_store_1_2, + output [15:0] o_store_1_3, + output [15:0] o_store_1_4, + output [15:0] o_store_1_5, + output [15:0] o_store_1_6, + output [15:0] o_store_1_7, + output [15:0] o_store_2_0, + output [15:0] o_store_2_1, + output [15:0] o_store_2_2, + output [15:0] o_store_2_3, + output [15:0] o_store_2_4, + output [15:0] o_store_2_5, + output [15:0] o_store_2_6, + output [15:0] o_store_2_7, + output [15:0] o_store_3_0, + output [15:0] o_store_3_1, + output [15:0] o_store_3_2, + output [15:0] o_store_3_3, + output [15:0] o_store_3_4, + output [15:0] o_store_3_5, + output [15:0] o_store_3_6, + output [15:0] o_store_3_7, + output [15:0] o_store_4_0, + output [15:0] o_store_4_1, + output [15:0] o_store_4_2, + output [15:0] o_store_4_3, + output [15:0] o_store_4_4, + output [15:0] o_store_4_5, + output [15:0] o_store_4_6, + output [15:0] o_store_4_7, + output [15:0] o_store_5_0, + output [15:0] o_store_5_1, + output [15:0] o_store_5_2, + output [15:0] o_store_5_3, + output [15:0] o_store_5_4, + output [15:0] o_store_5_5, + output [15:0] o_store_5_6, + output [15:0] o_store_5_7, + output o_wen_0, + output o_wen_1, + output o_wen_2, + output o_wen_3, + output o_wen_4, + output o_wen_5, + output [12:0] o_addr +); + +reg wen_0; +reg wen_1; +reg wen_2; +reg wen_3; +reg wen_4; +reg wen_5; +reg [12:0] base_addr; +reg [12:0] offset; +reg [5:0] count; +reg [5:0] count_to_wvec; +reg [5:0] count_x; +reg [5:0] count_y; +reg valid; +reg [15:0] buffer_reg_0; +reg [15:0] buffer_reg_1; +reg [15:0] buffer_reg_2; +reg [15:0] buffer_reg_3; +reg [15:0] buffer_reg_4; +reg [15:0] buffer_reg_5; +reg [15:0] buffer_reg_6; +reg [15:0] buffer_reg_7; +reg [15:0] buffer_reg_8; +reg [15:0] buffer_reg_9; +reg [15:0] buffer_reg_10; +reg [15:0] buffer_reg_11; +reg [15:0] buffer_reg_12; +reg [15:0] buffer_reg_13; +reg [15:0] buffer_reg_14; +reg [15:0] buffer_reg_15; +reg [15:0] buffer_reg_16; +reg [15:0] buffer_reg_17; +reg [15:0] buffer_reg_18; +reg [15:0] buffer_reg_19; +reg [15:0] buffer_reg_20; +reg [15:0] buffer_reg_21; +reg [15:0] buffer_reg_22; +reg [15:0] buffer_reg_23; +reg [15:0] buffer_reg_24; +reg [15:0] buffer_reg_25; +reg [15:0] buffer_reg_26; +reg [15:0] buffer_reg_27; +reg [15:0] buffer_reg_28; +reg [15:0] buffer_reg_29; +reg [15:0] buffer_reg_30; +reg [15:0] buffer_reg_31; +reg [15:0] buffer_reg_32; +reg [15:0] buffer_reg_33; +reg [15:0] buffer_reg_34; +reg [15:0] buffer_reg_35; +reg [15:0] buffer_reg_36; +reg [15:0] buffer_reg_37; +reg [15:0] buffer_reg_38; +reg [15:0] buffer_reg_39; +reg [15:0] buffer_reg_40; +reg [15:0] buffer_reg_41; +reg [15:0] buffer_reg_42; +reg [15:0] buffer_reg_43; +reg [15:0] buffer_reg_44; +reg [15:0] buffer_reg_45; +reg [15:0] buffer_reg_46; +reg [15:0] buffer_reg_47; +reg [12:0] addr_reg; + +wire [5:0] count_div_two; +assign count_div_two = count >> 1; +always @ (posedge clk) begin + valid <= i_valid; + buffer_reg_0 <= i_result_0; + buffer_reg_1 <= i_result_1; + buffer_reg_2 <= i_result_2; + buffer_reg_3 <= i_result_3; + buffer_reg_4 <= i_result_4; + buffer_reg_5 <= i_result_5; + buffer_reg_6 <= i_result_6; + buffer_reg_7 <= i_result_7; + buffer_reg_8 <= i_result_8; + buffer_reg_9 <= i_result_9; + buffer_reg_10 <= i_result_10; + buffer_reg_11 <= i_result_11; + buffer_reg_12 <= i_result_12; + buffer_reg_13 <= i_result_13; + buffer_reg_14 <= i_result_14; + buffer_reg_15 <= i_result_15; + buffer_reg_16 <= i_result_16; + buffer_reg_17 <= i_result_17; + buffer_reg_18 <= i_result_18; + buffer_reg_19 <= i_result_19; + buffer_reg_20 <= i_result_20; + buffer_reg_21 <= i_result_21; + buffer_reg_22 <= i_result_22; + buffer_reg_23 <= i_result_23; + buffer_reg_24 <= i_result_24; + buffer_reg_25 <= i_result_25; + buffer_reg_26 <= i_result_26; + buffer_reg_27 <= i_result_27; + buffer_reg_28 <= i_result_28; + buffer_reg_29 <= i_result_29; + buffer_reg_30 <= i_result_30; + buffer_reg_31 <= i_result_31; + buffer_reg_32 <= i_result_32; + buffer_reg_33 <= i_result_33; + buffer_reg_34 <= i_result_34; + buffer_reg_35 <= i_result_35; + buffer_reg_36 <= i_result_36; + buffer_reg_37 <= i_result_37; + buffer_reg_38 <= i_result_38; + buffer_reg_39 <= i_result_39; + buffer_reg_40 <= i_result_40; + buffer_reg_41 <= i_result_41; + buffer_reg_42 <= i_result_42; + buffer_reg_43 <= i_result_43; + buffer_reg_44 <= i_result_44; + buffer_reg_45 <= i_result_45; + buffer_reg_46 <= i_result_46; + buffer_reg_47 <= i_result_47; + addr_reg <= base_addr + offset; + if (i_reset) begin + count <= 0; + count_to_wvec <= 0; + base_addr <= 0; + offset <= 0; + count_x <= 0; + count_y <= 0; + wen_0 <= 1'b0; + wen_1 <= 1'b0; + wen_2 <= 1'b0; + wen_3 <= 1'b0; + wen_4 <= 1'b0; + wen_5 <= 1'b0; + end else if (i_valid) begin + if (count_x == 5) begin + if(count_y == 6)begin + base_addr <= base_addr + 4; + count_y <= 0; + count_x <= 0; + offset <= 0; + end else begin + if(count[0] == 1'b0) begin + offset <= 2; + count <= count + 1'b1; + if(count_to_wvec == 5) begin + count_to_wvec <= 0; + end else begin + count_to_wvec <= count_to_wvec + 1'b1; + end + end else if (count[1] == 1'b1) begin + offset <= 0; + base_addr <= base_addr + 4; + count_x <= 0; + count_y <= count_y + 2; + count <= count + 1'b1; + if(count_to_wvec == 5) begin + count_to_wvec <= 0; + end else begin + count_to_wvec <= count_to_wvec + 1'b1; + end + end + end + end else if(count[0] == 1'b0) begin + offset <= 2; + count <= count + 1'b1; + if(count_to_wvec == 5) begin + count_to_wvec <= 0; + end else begin + count_to_wvec <= count_to_wvec + 1'b1; + end + end else if (count[0] == 1'b1) begin + offset <= 0; + count <= count + 1'b1; + if(count_to_wvec == 5) begin + count_to_wvec <= 0; + end else begin + count_to_wvec <= count_to_wvec + 1'b1; + end + count_x <= count_x + 1'b1; + end + if ((i_valid || valid) == 1'b1) begin + if ((count_to_wvec == 0) && i_valid == 1) begin + wen_0 <= 1'b1; + end else begin + wen_0 <= 1'b0; + end + if ((count_to_wvec == 1) && i_valid == 1) begin + wen_1 <= 1'b1; + end else begin + wen_1 <= 1'b0; + end + if ((count_to_wvec == 2) && i_valid == 1) begin + wen_2 <= 1'b1; + end else begin + wen_2 <= 1'b0; + end + if ((count_to_wvec == 3) && i_valid == 1) begin + wen_3 <= 1'b1; + end else begin + wen_3 <= 1'b0; + end + if ((count_to_wvec == 4) && i_valid == 1) begin + wen_4 <= 1'b1; + end else begin + wen_4 <= 1'b0; + end + if ((count_to_wvec == 5) && i_valid == 1) begin + wen_5 <= 1'b1; + end else begin + wen_5 <= 1'b0; + end + end + end +end + +assign o_addr = addr_reg; +assign o_store_0_0 = buffer_reg_0; +assign o_store_1_0 = buffer_reg_8; +assign o_store_2_0 = buffer_reg_16; +assign o_store_3_0 = buffer_reg_24; +assign o_store_4_0 = buffer_reg_32; +assign o_store_5_0 = buffer_reg_40; +assign o_store_0_1 = buffer_reg_1; +assign o_store_1_1 = buffer_reg_9; +assign o_store_2_1 = buffer_reg_17; +assign o_store_3_1 = buffer_reg_25; +assign o_store_4_1 = buffer_reg_33; +assign o_store_5_1 = buffer_reg_41; +assign o_store_0_2 = buffer_reg_2; +assign o_store_1_2 = buffer_reg_10; +assign o_store_2_2 = buffer_reg_18; +assign o_store_3_2 = buffer_reg_26; +assign o_store_4_2 = buffer_reg_34; +assign o_store_5_2 = buffer_reg_42; +assign o_store_0_3 = buffer_reg_3; +assign o_store_1_3 = buffer_reg_11; +assign o_store_2_3 = buffer_reg_19; +assign o_store_3_3 = buffer_reg_27; +assign o_store_4_3 = buffer_reg_35; +assign o_store_5_3 = buffer_reg_43; +assign o_store_0_4 = buffer_reg_4; +assign o_store_1_4 = buffer_reg_12; +assign o_store_2_4 = buffer_reg_20; +assign o_store_3_4 = buffer_reg_28; +assign o_store_4_4 = buffer_reg_36; +assign o_store_5_4 = buffer_reg_44; +assign o_store_0_5 = buffer_reg_5; +assign o_store_1_5 = buffer_reg_13; +assign o_store_2_5 = buffer_reg_21; +assign o_store_3_5 = buffer_reg_29; +assign o_store_4_5 = buffer_reg_37; +assign o_store_5_5 = buffer_reg_45; +assign o_store_0_6 = buffer_reg_6; +assign o_store_1_6 = buffer_reg_14; +assign o_store_2_6 = buffer_reg_22; +assign o_store_3_6 = buffer_reg_30; +assign o_store_4_6 = buffer_reg_38; +assign o_store_5_6 = buffer_reg_46; +assign o_store_0_7 = buffer_reg_7; +assign o_store_1_7 = buffer_reg_15; +assign o_store_2_7 = buffer_reg_23; +assign o_store_3_7 = buffer_reg_31; +assign o_store_4_7 = buffer_reg_39; +assign o_store_5_7 = buffer_reg_47; + +assign o_wen_0 = wen_0; +assign o_wen_1 = wen_1; +assign o_wen_2 = wen_2; +assign o_wen_3 = wen_3; +assign o_wen_4 = wen_4; +assign o_wen_5 = wen_5; + +endmodule + +module inverse_winograd_1 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; +reg [29:0] result_reg_38_0; +reg [29:0] result_reg_38_1; +reg [29:0] result_reg_38_2; +reg [29:0] result_reg_38_3; +reg [29:0] result_reg_39_0; +reg [29:0] result_reg_39_1; +reg [29:0] result_reg_39_2; +reg [29:0] result_reg_39_3; +reg [29:0] result_reg_40_0; +reg [29:0] result_reg_40_1; +reg [29:0] result_reg_40_2; +reg [29:0] result_reg_40_3; +reg [29:0] result_reg_41_0; +reg [29:0] result_reg_41_1; +reg [29:0] result_reg_41_2; +reg [29:0] result_reg_41_3; +reg [29:0] result_reg_42_0; +reg [29:0] result_reg_42_1; +reg [29:0] result_reg_42_2; +reg [29:0] result_reg_42_3; +reg [29:0] result_reg_43_0; +reg [29:0] result_reg_43_1; +reg [29:0] result_reg_43_2; +reg [29:0] result_reg_43_3; +reg [29:0] result_reg_44_0; +reg [29:0] result_reg_44_1; +reg [29:0] result_reg_44_2; +reg [29:0] result_reg_44_3; +reg [29:0] result_reg_45_0; +reg [29:0] result_reg_45_1; +reg [29:0] result_reg_45_2; +reg [29:0] result_reg_45_3; +reg [29:0] result_reg_46_0; +reg [29:0] result_reg_46_1; +reg [29:0] result_reg_46_2; +reg [29:0] result_reg_46_3; +reg [29:0] result_reg_47_0; +reg [29:0] result_reg_47_1; +reg [29:0] result_reg_47_2; +reg [29:0] result_reg_47_3; +reg [29:0] result_reg_48_0; +reg [29:0] result_reg_48_1; +reg [29:0] result_reg_48_2; +reg [29:0] result_reg_48_3; +reg [29:0] result_reg_49_0; +reg [29:0] result_reg_49_1; +reg [29:0] result_reg_49_2; +reg [29:0] result_reg_49_3; +reg [29:0] result_reg_50_0; +reg [29:0] result_reg_50_1; +reg [29:0] result_reg_50_2; +reg [29:0] result_reg_50_3; +reg [29:0] result_reg_51_0; +reg [29:0] result_reg_51_1; +reg [29:0] result_reg_51_2; +reg [29:0] result_reg_51_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg out_valid_38; +reg out_valid_39; +reg out_valid_40; +reg out_valid_41; +reg out_valid_42; +reg out_valid_43; +reg out_valid_44; +reg out_valid_45; +reg out_valid_46; +reg out_valid_47; +reg out_valid_48; +reg out_valid_49; +reg out_valid_50; +reg out_valid_51; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; + out_valid_38 <= out_valid_37; + result_reg_38_0 <= result_reg_37_0; + result_reg_38_1 <= result_reg_37_1; + result_reg_38_2 <= result_reg_37_2; + result_reg_38_3 <= result_reg_37_3; + out_valid_39 <= out_valid_38; + result_reg_39_0 <= result_reg_38_0; + result_reg_39_1 <= result_reg_38_1; + result_reg_39_2 <= result_reg_38_2; + result_reg_39_3 <= result_reg_38_3; + out_valid_40 <= out_valid_39; + result_reg_40_0 <= result_reg_39_0; + result_reg_40_1 <= result_reg_39_1; + result_reg_40_2 <= result_reg_39_2; + result_reg_40_3 <= result_reg_39_3; + out_valid_41 <= out_valid_40; + result_reg_41_0 <= result_reg_40_0; + result_reg_41_1 <= result_reg_40_1; + result_reg_41_2 <= result_reg_40_2; + result_reg_41_3 <= result_reg_40_3; + out_valid_42 <= out_valid_41; + result_reg_42_0 <= result_reg_41_0; + result_reg_42_1 <= result_reg_41_1; + result_reg_42_2 <= result_reg_41_2; + result_reg_42_3 <= result_reg_41_3; + out_valid_43 <= out_valid_42; + result_reg_43_0 <= result_reg_42_0; + result_reg_43_1 <= result_reg_42_1; + result_reg_43_2 <= result_reg_42_2; + result_reg_43_3 <= result_reg_42_3; + out_valid_44 <= out_valid_43; + result_reg_44_0 <= result_reg_43_0; + result_reg_44_1 <= result_reg_43_1; + result_reg_44_2 <= result_reg_43_2; + result_reg_44_3 <= result_reg_43_3; + out_valid_45 <= out_valid_44; + result_reg_45_0 <= result_reg_44_0; + result_reg_45_1 <= result_reg_44_1; + result_reg_45_2 <= result_reg_44_2; + result_reg_45_3 <= result_reg_44_3; + out_valid_46 <= out_valid_45; + result_reg_46_0 <= result_reg_45_0; + result_reg_46_1 <= result_reg_45_1; + result_reg_46_2 <= result_reg_45_2; + result_reg_46_3 <= result_reg_45_3; + out_valid_47 <= out_valid_46; + result_reg_47_0 <= result_reg_46_0; + result_reg_47_1 <= result_reg_46_1; + result_reg_47_2 <= result_reg_46_2; + result_reg_47_3 <= result_reg_46_3; + out_valid_48 <= out_valid_47; + result_reg_48_0 <= result_reg_47_0; + result_reg_48_1 <= result_reg_47_1; + result_reg_48_2 <= result_reg_47_2; + result_reg_48_3 <= result_reg_47_3; + out_valid_49 <= out_valid_48; + result_reg_49_0 <= result_reg_48_0; + result_reg_49_1 <= result_reg_48_1; + result_reg_49_2 <= result_reg_48_2; + result_reg_49_3 <= result_reg_48_3; + out_valid_50 <= out_valid_49; + result_reg_50_0 <= result_reg_49_0; + result_reg_50_1 <= result_reg_49_1; + result_reg_50_2 <= result_reg_49_2; + result_reg_50_3 <= result_reg_49_3; + out_valid_51 <= out_valid_50; + result_reg_51_0 <= result_reg_50_0; + result_reg_51_1 <= result_reg_50_1; + result_reg_51_2 <= result_reg_50_2; + result_reg_51_3 <= result_reg_50_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_51_0[29] == 1'b0) begin + result_wire_0 <= result_reg_51_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_51_1[29] == 1'b0) begin + result_wire_1 <= result_reg_51_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_51_2[29] == 1'b0) begin + result_wire_2 <= result_reg_51_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_51_3[29] == 1'b0) begin + result_wire_3 <= result_reg_51_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_51; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_0 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; +reg [29:0] result_reg_38_0; +reg [29:0] result_reg_38_1; +reg [29:0] result_reg_38_2; +reg [29:0] result_reg_38_3; +reg [29:0] result_reg_39_0; +reg [29:0] result_reg_39_1; +reg [29:0] result_reg_39_2; +reg [29:0] result_reg_39_3; +reg [29:0] result_reg_40_0; +reg [29:0] result_reg_40_1; +reg [29:0] result_reg_40_2; +reg [29:0] result_reg_40_3; +reg [29:0] result_reg_41_0; +reg [29:0] result_reg_41_1; +reg [29:0] result_reg_41_2; +reg [29:0] result_reg_41_3; +reg [29:0] result_reg_42_0; +reg [29:0] result_reg_42_1; +reg [29:0] result_reg_42_2; +reg [29:0] result_reg_42_3; +reg [29:0] result_reg_43_0; +reg [29:0] result_reg_43_1; +reg [29:0] result_reg_43_2; +reg [29:0] result_reg_43_3; +reg [29:0] result_reg_44_0; +reg [29:0] result_reg_44_1; +reg [29:0] result_reg_44_2; +reg [29:0] result_reg_44_3; +reg [29:0] result_reg_45_0; +reg [29:0] result_reg_45_1; +reg [29:0] result_reg_45_2; +reg [29:0] result_reg_45_3; +reg [29:0] result_reg_46_0; +reg [29:0] result_reg_46_1; +reg [29:0] result_reg_46_2; +reg [29:0] result_reg_46_3; +reg [29:0] result_reg_47_0; +reg [29:0] result_reg_47_1; +reg [29:0] result_reg_47_2; +reg [29:0] result_reg_47_3; +reg [29:0] result_reg_48_0; +reg [29:0] result_reg_48_1; +reg [29:0] result_reg_48_2; +reg [29:0] result_reg_48_3; +reg [29:0] result_reg_49_0; +reg [29:0] result_reg_49_1; +reg [29:0] result_reg_49_2; +reg [29:0] result_reg_49_3; +reg [29:0] result_reg_50_0; +reg [29:0] result_reg_50_1; +reg [29:0] result_reg_50_2; +reg [29:0] result_reg_50_3; +reg [29:0] result_reg_51_0; +reg [29:0] result_reg_51_1; +reg [29:0] result_reg_51_2; +reg [29:0] result_reg_51_3; +reg [29:0] result_reg_52_0; +reg [29:0] result_reg_52_1; +reg [29:0] result_reg_52_2; +reg [29:0] result_reg_52_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg out_valid_38; +reg out_valid_39; +reg out_valid_40; +reg out_valid_41; +reg out_valid_42; +reg out_valid_43; +reg out_valid_44; +reg out_valid_45; +reg out_valid_46; +reg out_valid_47; +reg out_valid_48; +reg out_valid_49; +reg out_valid_50; +reg out_valid_51; +reg out_valid_52; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; + out_valid_38 <= out_valid_37; + result_reg_38_0 <= result_reg_37_0; + result_reg_38_1 <= result_reg_37_1; + result_reg_38_2 <= result_reg_37_2; + result_reg_38_3 <= result_reg_37_3; + out_valid_39 <= out_valid_38; + result_reg_39_0 <= result_reg_38_0; + result_reg_39_1 <= result_reg_38_1; + result_reg_39_2 <= result_reg_38_2; + result_reg_39_3 <= result_reg_38_3; + out_valid_40 <= out_valid_39; + result_reg_40_0 <= result_reg_39_0; + result_reg_40_1 <= result_reg_39_1; + result_reg_40_2 <= result_reg_39_2; + result_reg_40_3 <= result_reg_39_3; + out_valid_41 <= out_valid_40; + result_reg_41_0 <= result_reg_40_0; + result_reg_41_1 <= result_reg_40_1; + result_reg_41_2 <= result_reg_40_2; + result_reg_41_3 <= result_reg_40_3; + out_valid_42 <= out_valid_41; + result_reg_42_0 <= result_reg_41_0; + result_reg_42_1 <= result_reg_41_1; + result_reg_42_2 <= result_reg_41_2; + result_reg_42_3 <= result_reg_41_3; + out_valid_43 <= out_valid_42; + result_reg_43_0 <= result_reg_42_0; + result_reg_43_1 <= result_reg_42_1; + result_reg_43_2 <= result_reg_42_2; + result_reg_43_3 <= result_reg_42_3; + out_valid_44 <= out_valid_43; + result_reg_44_0 <= result_reg_43_0; + result_reg_44_1 <= result_reg_43_1; + result_reg_44_2 <= result_reg_43_2; + result_reg_44_3 <= result_reg_43_3; + out_valid_45 <= out_valid_44; + result_reg_45_0 <= result_reg_44_0; + result_reg_45_1 <= result_reg_44_1; + result_reg_45_2 <= result_reg_44_2; + result_reg_45_3 <= result_reg_44_3; + out_valid_46 <= out_valid_45; + result_reg_46_0 <= result_reg_45_0; + result_reg_46_1 <= result_reg_45_1; + result_reg_46_2 <= result_reg_45_2; + result_reg_46_3 <= result_reg_45_3; + out_valid_47 <= out_valid_46; + result_reg_47_0 <= result_reg_46_0; + result_reg_47_1 <= result_reg_46_1; + result_reg_47_2 <= result_reg_46_2; + result_reg_47_3 <= result_reg_46_3; + out_valid_48 <= out_valid_47; + result_reg_48_0 <= result_reg_47_0; + result_reg_48_1 <= result_reg_47_1; + result_reg_48_2 <= result_reg_47_2; + result_reg_48_3 <= result_reg_47_3; + out_valid_49 <= out_valid_48; + result_reg_49_0 <= result_reg_48_0; + result_reg_49_1 <= result_reg_48_1; + result_reg_49_2 <= result_reg_48_2; + result_reg_49_3 <= result_reg_48_3; + out_valid_50 <= out_valid_49; + result_reg_50_0 <= result_reg_49_0; + result_reg_50_1 <= result_reg_49_1; + result_reg_50_2 <= result_reg_49_2; + result_reg_50_3 <= result_reg_49_3; + out_valid_51 <= out_valid_50; + result_reg_51_0 <= result_reg_50_0; + result_reg_51_1 <= result_reg_50_1; + result_reg_51_2 <= result_reg_50_2; + result_reg_51_3 <= result_reg_50_3; + out_valid_52 <= out_valid_51; + result_reg_52_0 <= result_reg_51_0; + result_reg_52_1 <= result_reg_51_1; + result_reg_52_2 <= result_reg_51_2; + result_reg_52_3 <= result_reg_51_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_52_0[29] == 1'b0) begin + result_wire_0 <= result_reg_52_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_52_1[29] == 1'b0) begin + result_wire_1 <= result_reg_52_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_52_2[29] == 1'b0) begin + result_wire_2 <= result_reg_52_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_52_3[29] == 1'b0) begin + result_wire_3 <= result_reg_52_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_52; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_3 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; +reg [29:0] result_reg_38_0; +reg [29:0] result_reg_38_1; +reg [29:0] result_reg_38_2; +reg [29:0] result_reg_38_3; +reg [29:0] result_reg_39_0; +reg [29:0] result_reg_39_1; +reg [29:0] result_reg_39_2; +reg [29:0] result_reg_39_3; +reg [29:0] result_reg_40_0; +reg [29:0] result_reg_40_1; +reg [29:0] result_reg_40_2; +reg [29:0] result_reg_40_3; +reg [29:0] result_reg_41_0; +reg [29:0] result_reg_41_1; +reg [29:0] result_reg_41_2; +reg [29:0] result_reg_41_3; +reg [29:0] result_reg_42_0; +reg [29:0] result_reg_42_1; +reg [29:0] result_reg_42_2; +reg [29:0] result_reg_42_3; +reg [29:0] result_reg_43_0; +reg [29:0] result_reg_43_1; +reg [29:0] result_reg_43_2; +reg [29:0] result_reg_43_3; +reg [29:0] result_reg_44_0; +reg [29:0] result_reg_44_1; +reg [29:0] result_reg_44_2; +reg [29:0] result_reg_44_3; +reg [29:0] result_reg_45_0; +reg [29:0] result_reg_45_1; +reg [29:0] result_reg_45_2; +reg [29:0] result_reg_45_3; +reg [29:0] result_reg_46_0; +reg [29:0] result_reg_46_1; +reg [29:0] result_reg_46_2; +reg [29:0] result_reg_46_3; +reg [29:0] result_reg_47_0; +reg [29:0] result_reg_47_1; +reg [29:0] result_reg_47_2; +reg [29:0] result_reg_47_3; +reg [29:0] result_reg_48_0; +reg [29:0] result_reg_48_1; +reg [29:0] result_reg_48_2; +reg [29:0] result_reg_48_3; +reg [29:0] result_reg_49_0; +reg [29:0] result_reg_49_1; +reg [29:0] result_reg_49_2; +reg [29:0] result_reg_49_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg out_valid_38; +reg out_valid_39; +reg out_valid_40; +reg out_valid_41; +reg out_valid_42; +reg out_valid_43; +reg out_valid_44; +reg out_valid_45; +reg out_valid_46; +reg out_valid_47; +reg out_valid_48; +reg out_valid_49; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; + out_valid_38 <= out_valid_37; + result_reg_38_0 <= result_reg_37_0; + result_reg_38_1 <= result_reg_37_1; + result_reg_38_2 <= result_reg_37_2; + result_reg_38_3 <= result_reg_37_3; + out_valid_39 <= out_valid_38; + result_reg_39_0 <= result_reg_38_0; + result_reg_39_1 <= result_reg_38_1; + result_reg_39_2 <= result_reg_38_2; + result_reg_39_3 <= result_reg_38_3; + out_valid_40 <= out_valid_39; + result_reg_40_0 <= result_reg_39_0; + result_reg_40_1 <= result_reg_39_1; + result_reg_40_2 <= result_reg_39_2; + result_reg_40_3 <= result_reg_39_3; + out_valid_41 <= out_valid_40; + result_reg_41_0 <= result_reg_40_0; + result_reg_41_1 <= result_reg_40_1; + result_reg_41_2 <= result_reg_40_2; + result_reg_41_3 <= result_reg_40_3; + out_valid_42 <= out_valid_41; + result_reg_42_0 <= result_reg_41_0; + result_reg_42_1 <= result_reg_41_1; + result_reg_42_2 <= result_reg_41_2; + result_reg_42_3 <= result_reg_41_3; + out_valid_43 <= out_valid_42; + result_reg_43_0 <= result_reg_42_0; + result_reg_43_1 <= result_reg_42_1; + result_reg_43_2 <= result_reg_42_2; + result_reg_43_3 <= result_reg_42_3; + out_valid_44 <= out_valid_43; + result_reg_44_0 <= result_reg_43_0; + result_reg_44_1 <= result_reg_43_1; + result_reg_44_2 <= result_reg_43_2; + result_reg_44_3 <= result_reg_43_3; + out_valid_45 <= out_valid_44; + result_reg_45_0 <= result_reg_44_0; + result_reg_45_1 <= result_reg_44_1; + result_reg_45_2 <= result_reg_44_2; + result_reg_45_3 <= result_reg_44_3; + out_valid_46 <= out_valid_45; + result_reg_46_0 <= result_reg_45_0; + result_reg_46_1 <= result_reg_45_1; + result_reg_46_2 <= result_reg_45_2; + result_reg_46_3 <= result_reg_45_3; + out_valid_47 <= out_valid_46; + result_reg_47_0 <= result_reg_46_0; + result_reg_47_1 <= result_reg_46_1; + result_reg_47_2 <= result_reg_46_2; + result_reg_47_3 <= result_reg_46_3; + out_valid_48 <= out_valid_47; + result_reg_48_0 <= result_reg_47_0; + result_reg_48_1 <= result_reg_47_1; + result_reg_48_2 <= result_reg_47_2; + result_reg_48_3 <= result_reg_47_3; + out_valid_49 <= out_valid_48; + result_reg_49_0 <= result_reg_48_0; + result_reg_49_1 <= result_reg_48_1; + result_reg_49_2 <= result_reg_48_2; + result_reg_49_3 <= result_reg_48_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_49_0[29] == 1'b0) begin + result_wire_0 <= result_reg_49_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_49_1[29] == 1'b0) begin + result_wire_1 <= result_reg_49_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_49_2[29] == 1'b0) begin + result_wire_2 <= result_reg_49_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_49_3[29] == 1'b0) begin + result_wire_3 <= result_reg_49_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_49; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_2 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; +reg [29:0] result_reg_38_0; +reg [29:0] result_reg_38_1; +reg [29:0] result_reg_38_2; +reg [29:0] result_reg_38_3; +reg [29:0] result_reg_39_0; +reg [29:0] result_reg_39_1; +reg [29:0] result_reg_39_2; +reg [29:0] result_reg_39_3; +reg [29:0] result_reg_40_0; +reg [29:0] result_reg_40_1; +reg [29:0] result_reg_40_2; +reg [29:0] result_reg_40_3; +reg [29:0] result_reg_41_0; +reg [29:0] result_reg_41_1; +reg [29:0] result_reg_41_2; +reg [29:0] result_reg_41_3; +reg [29:0] result_reg_42_0; +reg [29:0] result_reg_42_1; +reg [29:0] result_reg_42_2; +reg [29:0] result_reg_42_3; +reg [29:0] result_reg_43_0; +reg [29:0] result_reg_43_1; +reg [29:0] result_reg_43_2; +reg [29:0] result_reg_43_3; +reg [29:0] result_reg_44_0; +reg [29:0] result_reg_44_1; +reg [29:0] result_reg_44_2; +reg [29:0] result_reg_44_3; +reg [29:0] result_reg_45_0; +reg [29:0] result_reg_45_1; +reg [29:0] result_reg_45_2; +reg [29:0] result_reg_45_3; +reg [29:0] result_reg_46_0; +reg [29:0] result_reg_46_1; +reg [29:0] result_reg_46_2; +reg [29:0] result_reg_46_3; +reg [29:0] result_reg_47_0; +reg [29:0] result_reg_47_1; +reg [29:0] result_reg_47_2; +reg [29:0] result_reg_47_3; +reg [29:0] result_reg_48_0; +reg [29:0] result_reg_48_1; +reg [29:0] result_reg_48_2; +reg [29:0] result_reg_48_3; +reg [29:0] result_reg_49_0; +reg [29:0] result_reg_49_1; +reg [29:0] result_reg_49_2; +reg [29:0] result_reg_49_3; +reg [29:0] result_reg_50_0; +reg [29:0] result_reg_50_1; +reg [29:0] result_reg_50_2; +reg [29:0] result_reg_50_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg out_valid_38; +reg out_valid_39; +reg out_valid_40; +reg out_valid_41; +reg out_valid_42; +reg out_valid_43; +reg out_valid_44; +reg out_valid_45; +reg out_valid_46; +reg out_valid_47; +reg out_valid_48; +reg out_valid_49; +reg out_valid_50; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; + out_valid_38 <= out_valid_37; + result_reg_38_0 <= result_reg_37_0; + result_reg_38_1 <= result_reg_37_1; + result_reg_38_2 <= result_reg_37_2; + result_reg_38_3 <= result_reg_37_3; + out_valid_39 <= out_valid_38; + result_reg_39_0 <= result_reg_38_0; + result_reg_39_1 <= result_reg_38_1; + result_reg_39_2 <= result_reg_38_2; + result_reg_39_3 <= result_reg_38_3; + out_valid_40 <= out_valid_39; + result_reg_40_0 <= result_reg_39_0; + result_reg_40_1 <= result_reg_39_1; + result_reg_40_2 <= result_reg_39_2; + result_reg_40_3 <= result_reg_39_3; + out_valid_41 <= out_valid_40; + result_reg_41_0 <= result_reg_40_0; + result_reg_41_1 <= result_reg_40_1; + result_reg_41_2 <= result_reg_40_2; + result_reg_41_3 <= result_reg_40_3; + out_valid_42 <= out_valid_41; + result_reg_42_0 <= result_reg_41_0; + result_reg_42_1 <= result_reg_41_1; + result_reg_42_2 <= result_reg_41_2; + result_reg_42_3 <= result_reg_41_3; + out_valid_43 <= out_valid_42; + result_reg_43_0 <= result_reg_42_0; + result_reg_43_1 <= result_reg_42_1; + result_reg_43_2 <= result_reg_42_2; + result_reg_43_3 <= result_reg_42_3; + out_valid_44 <= out_valid_43; + result_reg_44_0 <= result_reg_43_0; + result_reg_44_1 <= result_reg_43_1; + result_reg_44_2 <= result_reg_43_2; + result_reg_44_3 <= result_reg_43_3; + out_valid_45 <= out_valid_44; + result_reg_45_0 <= result_reg_44_0; + result_reg_45_1 <= result_reg_44_1; + result_reg_45_2 <= result_reg_44_2; + result_reg_45_3 <= result_reg_44_3; + out_valid_46 <= out_valid_45; + result_reg_46_0 <= result_reg_45_0; + result_reg_46_1 <= result_reg_45_1; + result_reg_46_2 <= result_reg_45_2; + result_reg_46_3 <= result_reg_45_3; + out_valid_47 <= out_valid_46; + result_reg_47_0 <= result_reg_46_0; + result_reg_47_1 <= result_reg_46_1; + result_reg_47_2 <= result_reg_46_2; + result_reg_47_3 <= result_reg_46_3; + out_valid_48 <= out_valid_47; + result_reg_48_0 <= result_reg_47_0; + result_reg_48_1 <= result_reg_47_1; + result_reg_48_2 <= result_reg_47_2; + result_reg_48_3 <= result_reg_47_3; + out_valid_49 <= out_valid_48; + result_reg_49_0 <= result_reg_48_0; + result_reg_49_1 <= result_reg_48_1; + result_reg_49_2 <= result_reg_48_2; + result_reg_49_3 <= result_reg_48_3; + out_valid_50 <= out_valid_49; + result_reg_50_0 <= result_reg_49_0; + result_reg_50_1 <= result_reg_49_1; + result_reg_50_2 <= result_reg_49_2; + result_reg_50_3 <= result_reg_49_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_50_0[29] == 1'b0) begin + result_wire_0 <= result_reg_50_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_50_1[29] == 1'b0) begin + result_wire_1 <= result_reg_50_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_50_2[29] == 1'b0) begin + result_wire_2 <= result_reg_50_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_50_3[29] == 1'b0) begin + result_wire_3 <= result_reg_50_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_50; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_5 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; +reg [29:0] result_reg_38_0; +reg [29:0] result_reg_38_1; +reg [29:0] result_reg_38_2; +reg [29:0] result_reg_38_3; +reg [29:0] result_reg_39_0; +reg [29:0] result_reg_39_1; +reg [29:0] result_reg_39_2; +reg [29:0] result_reg_39_3; +reg [29:0] result_reg_40_0; +reg [29:0] result_reg_40_1; +reg [29:0] result_reg_40_2; +reg [29:0] result_reg_40_3; +reg [29:0] result_reg_41_0; +reg [29:0] result_reg_41_1; +reg [29:0] result_reg_41_2; +reg [29:0] result_reg_41_3; +reg [29:0] result_reg_42_0; +reg [29:0] result_reg_42_1; +reg [29:0] result_reg_42_2; +reg [29:0] result_reg_42_3; +reg [29:0] result_reg_43_0; +reg [29:0] result_reg_43_1; +reg [29:0] result_reg_43_2; +reg [29:0] result_reg_43_3; +reg [29:0] result_reg_44_0; +reg [29:0] result_reg_44_1; +reg [29:0] result_reg_44_2; +reg [29:0] result_reg_44_3; +reg [29:0] result_reg_45_0; +reg [29:0] result_reg_45_1; +reg [29:0] result_reg_45_2; +reg [29:0] result_reg_45_3; +reg [29:0] result_reg_46_0; +reg [29:0] result_reg_46_1; +reg [29:0] result_reg_46_2; +reg [29:0] result_reg_46_3; +reg [29:0] result_reg_47_0; +reg [29:0] result_reg_47_1; +reg [29:0] result_reg_47_2; +reg [29:0] result_reg_47_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg out_valid_38; +reg out_valid_39; +reg out_valid_40; +reg out_valid_41; +reg out_valid_42; +reg out_valid_43; +reg out_valid_44; +reg out_valid_45; +reg out_valid_46; +reg out_valid_47; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; + out_valid_38 <= out_valid_37; + result_reg_38_0 <= result_reg_37_0; + result_reg_38_1 <= result_reg_37_1; + result_reg_38_2 <= result_reg_37_2; + result_reg_38_3 <= result_reg_37_3; + out_valid_39 <= out_valid_38; + result_reg_39_0 <= result_reg_38_0; + result_reg_39_1 <= result_reg_38_1; + result_reg_39_2 <= result_reg_38_2; + result_reg_39_3 <= result_reg_38_3; + out_valid_40 <= out_valid_39; + result_reg_40_0 <= result_reg_39_0; + result_reg_40_1 <= result_reg_39_1; + result_reg_40_2 <= result_reg_39_2; + result_reg_40_3 <= result_reg_39_3; + out_valid_41 <= out_valid_40; + result_reg_41_0 <= result_reg_40_0; + result_reg_41_1 <= result_reg_40_1; + result_reg_41_2 <= result_reg_40_2; + result_reg_41_3 <= result_reg_40_3; + out_valid_42 <= out_valid_41; + result_reg_42_0 <= result_reg_41_0; + result_reg_42_1 <= result_reg_41_1; + result_reg_42_2 <= result_reg_41_2; + result_reg_42_3 <= result_reg_41_3; + out_valid_43 <= out_valid_42; + result_reg_43_0 <= result_reg_42_0; + result_reg_43_1 <= result_reg_42_1; + result_reg_43_2 <= result_reg_42_2; + result_reg_43_3 <= result_reg_42_3; + out_valid_44 <= out_valid_43; + result_reg_44_0 <= result_reg_43_0; + result_reg_44_1 <= result_reg_43_1; + result_reg_44_2 <= result_reg_43_2; + result_reg_44_3 <= result_reg_43_3; + out_valid_45 <= out_valid_44; + result_reg_45_0 <= result_reg_44_0; + result_reg_45_1 <= result_reg_44_1; + result_reg_45_2 <= result_reg_44_2; + result_reg_45_3 <= result_reg_44_3; + out_valid_46 <= out_valid_45; + result_reg_46_0 <= result_reg_45_0; + result_reg_46_1 <= result_reg_45_1; + result_reg_46_2 <= result_reg_45_2; + result_reg_46_3 <= result_reg_45_3; + out_valid_47 <= out_valid_46; + result_reg_47_0 <= result_reg_46_0; + result_reg_47_1 <= result_reg_46_1; + result_reg_47_2 <= result_reg_46_2; + result_reg_47_3 <= result_reg_46_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_47_0[29] == 1'b0) begin + result_wire_0 <= result_reg_47_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_47_1[29] == 1'b0) begin + result_wire_1 <= result_reg_47_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_47_2[29] == 1'b0) begin + result_wire_2 <= result_reg_47_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_47_3[29] == 1'b0) begin + result_wire_3 <= result_reg_47_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_47; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_4 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; +reg [29:0] result_reg_38_0; +reg [29:0] result_reg_38_1; +reg [29:0] result_reg_38_2; +reg [29:0] result_reg_38_3; +reg [29:0] result_reg_39_0; +reg [29:0] result_reg_39_1; +reg [29:0] result_reg_39_2; +reg [29:0] result_reg_39_3; +reg [29:0] result_reg_40_0; +reg [29:0] result_reg_40_1; +reg [29:0] result_reg_40_2; +reg [29:0] result_reg_40_3; +reg [29:0] result_reg_41_0; +reg [29:0] result_reg_41_1; +reg [29:0] result_reg_41_2; +reg [29:0] result_reg_41_3; +reg [29:0] result_reg_42_0; +reg [29:0] result_reg_42_1; +reg [29:0] result_reg_42_2; +reg [29:0] result_reg_42_3; +reg [29:0] result_reg_43_0; +reg [29:0] result_reg_43_1; +reg [29:0] result_reg_43_2; +reg [29:0] result_reg_43_3; +reg [29:0] result_reg_44_0; +reg [29:0] result_reg_44_1; +reg [29:0] result_reg_44_2; +reg [29:0] result_reg_44_3; +reg [29:0] result_reg_45_0; +reg [29:0] result_reg_45_1; +reg [29:0] result_reg_45_2; +reg [29:0] result_reg_45_3; +reg [29:0] result_reg_46_0; +reg [29:0] result_reg_46_1; +reg [29:0] result_reg_46_2; +reg [29:0] result_reg_46_3; +reg [29:0] result_reg_47_0; +reg [29:0] result_reg_47_1; +reg [29:0] result_reg_47_2; +reg [29:0] result_reg_47_3; +reg [29:0] result_reg_48_0; +reg [29:0] result_reg_48_1; +reg [29:0] result_reg_48_2; +reg [29:0] result_reg_48_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg out_valid_38; +reg out_valid_39; +reg out_valid_40; +reg out_valid_41; +reg out_valid_42; +reg out_valid_43; +reg out_valid_44; +reg out_valid_45; +reg out_valid_46; +reg out_valid_47; +reg out_valid_48; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; + out_valid_38 <= out_valid_37; + result_reg_38_0 <= result_reg_37_0; + result_reg_38_1 <= result_reg_37_1; + result_reg_38_2 <= result_reg_37_2; + result_reg_38_3 <= result_reg_37_3; + out_valid_39 <= out_valid_38; + result_reg_39_0 <= result_reg_38_0; + result_reg_39_1 <= result_reg_38_1; + result_reg_39_2 <= result_reg_38_2; + result_reg_39_3 <= result_reg_38_3; + out_valid_40 <= out_valid_39; + result_reg_40_0 <= result_reg_39_0; + result_reg_40_1 <= result_reg_39_1; + result_reg_40_2 <= result_reg_39_2; + result_reg_40_3 <= result_reg_39_3; + out_valid_41 <= out_valid_40; + result_reg_41_0 <= result_reg_40_0; + result_reg_41_1 <= result_reg_40_1; + result_reg_41_2 <= result_reg_40_2; + result_reg_41_3 <= result_reg_40_3; + out_valid_42 <= out_valid_41; + result_reg_42_0 <= result_reg_41_0; + result_reg_42_1 <= result_reg_41_1; + result_reg_42_2 <= result_reg_41_2; + result_reg_42_3 <= result_reg_41_3; + out_valid_43 <= out_valid_42; + result_reg_43_0 <= result_reg_42_0; + result_reg_43_1 <= result_reg_42_1; + result_reg_43_2 <= result_reg_42_2; + result_reg_43_3 <= result_reg_42_3; + out_valid_44 <= out_valid_43; + result_reg_44_0 <= result_reg_43_0; + result_reg_44_1 <= result_reg_43_1; + result_reg_44_2 <= result_reg_43_2; + result_reg_44_3 <= result_reg_43_3; + out_valid_45 <= out_valid_44; + result_reg_45_0 <= result_reg_44_0; + result_reg_45_1 <= result_reg_44_1; + result_reg_45_2 <= result_reg_44_2; + result_reg_45_3 <= result_reg_44_3; + out_valid_46 <= out_valid_45; + result_reg_46_0 <= result_reg_45_0; + result_reg_46_1 <= result_reg_45_1; + result_reg_46_2 <= result_reg_45_2; + result_reg_46_3 <= result_reg_45_3; + out_valid_47 <= out_valid_46; + result_reg_47_0 <= result_reg_46_0; + result_reg_47_1 <= result_reg_46_1; + result_reg_47_2 <= result_reg_46_2; + result_reg_47_3 <= result_reg_46_3; + out_valid_48 <= out_valid_47; + result_reg_48_0 <= result_reg_47_0; + result_reg_48_1 <= result_reg_47_1; + result_reg_48_2 <= result_reg_47_2; + result_reg_48_3 <= result_reg_47_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_48_0[29] == 1'b0) begin + result_wire_0 <= result_reg_48_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_48_1[29] == 1'b0) begin + result_wire_1 <= result_reg_48_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_48_2[29] == 1'b0) begin + result_wire_2 <= result_reg_48_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_48_3[29] == 1'b0) begin + result_wire_3 <= result_reg_48_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_48; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_7 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; +reg [29:0] result_reg_38_0; +reg [29:0] result_reg_38_1; +reg [29:0] result_reg_38_2; +reg [29:0] result_reg_38_3; +reg [29:0] result_reg_39_0; +reg [29:0] result_reg_39_1; +reg [29:0] result_reg_39_2; +reg [29:0] result_reg_39_3; +reg [29:0] result_reg_40_0; +reg [29:0] result_reg_40_1; +reg [29:0] result_reg_40_2; +reg [29:0] result_reg_40_3; +reg [29:0] result_reg_41_0; +reg [29:0] result_reg_41_1; +reg [29:0] result_reg_41_2; +reg [29:0] result_reg_41_3; +reg [29:0] result_reg_42_0; +reg [29:0] result_reg_42_1; +reg [29:0] result_reg_42_2; +reg [29:0] result_reg_42_3; +reg [29:0] result_reg_43_0; +reg [29:0] result_reg_43_1; +reg [29:0] result_reg_43_2; +reg [29:0] result_reg_43_3; +reg [29:0] result_reg_44_0; +reg [29:0] result_reg_44_1; +reg [29:0] result_reg_44_2; +reg [29:0] result_reg_44_3; +reg [29:0] result_reg_45_0; +reg [29:0] result_reg_45_1; +reg [29:0] result_reg_45_2; +reg [29:0] result_reg_45_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg out_valid_38; +reg out_valid_39; +reg out_valid_40; +reg out_valid_41; +reg out_valid_42; +reg out_valid_43; +reg out_valid_44; +reg out_valid_45; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; + out_valid_38 <= out_valid_37; + result_reg_38_0 <= result_reg_37_0; + result_reg_38_1 <= result_reg_37_1; + result_reg_38_2 <= result_reg_37_2; + result_reg_38_3 <= result_reg_37_3; + out_valid_39 <= out_valid_38; + result_reg_39_0 <= result_reg_38_0; + result_reg_39_1 <= result_reg_38_1; + result_reg_39_2 <= result_reg_38_2; + result_reg_39_3 <= result_reg_38_3; + out_valid_40 <= out_valid_39; + result_reg_40_0 <= result_reg_39_0; + result_reg_40_1 <= result_reg_39_1; + result_reg_40_2 <= result_reg_39_2; + result_reg_40_3 <= result_reg_39_3; + out_valid_41 <= out_valid_40; + result_reg_41_0 <= result_reg_40_0; + result_reg_41_1 <= result_reg_40_1; + result_reg_41_2 <= result_reg_40_2; + result_reg_41_3 <= result_reg_40_3; + out_valid_42 <= out_valid_41; + result_reg_42_0 <= result_reg_41_0; + result_reg_42_1 <= result_reg_41_1; + result_reg_42_2 <= result_reg_41_2; + result_reg_42_3 <= result_reg_41_3; + out_valid_43 <= out_valid_42; + result_reg_43_0 <= result_reg_42_0; + result_reg_43_1 <= result_reg_42_1; + result_reg_43_2 <= result_reg_42_2; + result_reg_43_3 <= result_reg_42_3; + out_valid_44 <= out_valid_43; + result_reg_44_0 <= result_reg_43_0; + result_reg_44_1 <= result_reg_43_1; + result_reg_44_2 <= result_reg_43_2; + result_reg_44_3 <= result_reg_43_3; + out_valid_45 <= out_valid_44; + result_reg_45_0 <= result_reg_44_0; + result_reg_45_1 <= result_reg_44_1; + result_reg_45_2 <= result_reg_44_2; + result_reg_45_3 <= result_reg_44_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_45_0[29] == 1'b0) begin + result_wire_0 <= result_reg_45_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_45_1[29] == 1'b0) begin + result_wire_1 <= result_reg_45_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_45_2[29] == 1'b0) begin + result_wire_2 <= result_reg_45_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_45_3[29] == 1'b0) begin + result_wire_3 <= result_reg_45_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_45; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_6 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; +reg [29:0] result_reg_38_0; +reg [29:0] result_reg_38_1; +reg [29:0] result_reg_38_2; +reg [29:0] result_reg_38_3; +reg [29:0] result_reg_39_0; +reg [29:0] result_reg_39_1; +reg [29:0] result_reg_39_2; +reg [29:0] result_reg_39_3; +reg [29:0] result_reg_40_0; +reg [29:0] result_reg_40_1; +reg [29:0] result_reg_40_2; +reg [29:0] result_reg_40_3; +reg [29:0] result_reg_41_0; +reg [29:0] result_reg_41_1; +reg [29:0] result_reg_41_2; +reg [29:0] result_reg_41_3; +reg [29:0] result_reg_42_0; +reg [29:0] result_reg_42_1; +reg [29:0] result_reg_42_2; +reg [29:0] result_reg_42_3; +reg [29:0] result_reg_43_0; +reg [29:0] result_reg_43_1; +reg [29:0] result_reg_43_2; +reg [29:0] result_reg_43_3; +reg [29:0] result_reg_44_0; +reg [29:0] result_reg_44_1; +reg [29:0] result_reg_44_2; +reg [29:0] result_reg_44_3; +reg [29:0] result_reg_45_0; +reg [29:0] result_reg_45_1; +reg [29:0] result_reg_45_2; +reg [29:0] result_reg_45_3; +reg [29:0] result_reg_46_0; +reg [29:0] result_reg_46_1; +reg [29:0] result_reg_46_2; +reg [29:0] result_reg_46_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg out_valid_38; +reg out_valid_39; +reg out_valid_40; +reg out_valid_41; +reg out_valid_42; +reg out_valid_43; +reg out_valid_44; +reg out_valid_45; +reg out_valid_46; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; + out_valid_38 <= out_valid_37; + result_reg_38_0 <= result_reg_37_0; + result_reg_38_1 <= result_reg_37_1; + result_reg_38_2 <= result_reg_37_2; + result_reg_38_3 <= result_reg_37_3; + out_valid_39 <= out_valid_38; + result_reg_39_0 <= result_reg_38_0; + result_reg_39_1 <= result_reg_38_1; + result_reg_39_2 <= result_reg_38_2; + result_reg_39_3 <= result_reg_38_3; + out_valid_40 <= out_valid_39; + result_reg_40_0 <= result_reg_39_0; + result_reg_40_1 <= result_reg_39_1; + result_reg_40_2 <= result_reg_39_2; + result_reg_40_3 <= result_reg_39_3; + out_valid_41 <= out_valid_40; + result_reg_41_0 <= result_reg_40_0; + result_reg_41_1 <= result_reg_40_1; + result_reg_41_2 <= result_reg_40_2; + result_reg_41_3 <= result_reg_40_3; + out_valid_42 <= out_valid_41; + result_reg_42_0 <= result_reg_41_0; + result_reg_42_1 <= result_reg_41_1; + result_reg_42_2 <= result_reg_41_2; + result_reg_42_3 <= result_reg_41_3; + out_valid_43 <= out_valid_42; + result_reg_43_0 <= result_reg_42_0; + result_reg_43_1 <= result_reg_42_1; + result_reg_43_2 <= result_reg_42_2; + result_reg_43_3 <= result_reg_42_3; + out_valid_44 <= out_valid_43; + result_reg_44_0 <= result_reg_43_0; + result_reg_44_1 <= result_reg_43_1; + result_reg_44_2 <= result_reg_43_2; + result_reg_44_3 <= result_reg_43_3; + out_valid_45 <= out_valid_44; + result_reg_45_0 <= result_reg_44_0; + result_reg_45_1 <= result_reg_44_1; + result_reg_45_2 <= result_reg_44_2; + result_reg_45_3 <= result_reg_44_3; + out_valid_46 <= out_valid_45; + result_reg_46_0 <= result_reg_45_0; + result_reg_46_1 <= result_reg_45_1; + result_reg_46_2 <= result_reg_45_2; + result_reg_46_3 <= result_reg_45_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_46_0[29] == 1'b0) begin + result_wire_0 <= result_reg_46_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_46_1[29] == 1'b0) begin + result_wire_1 <= result_reg_46_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_46_2[29] == 1'b0) begin + result_wire_2 <= result_reg_46_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_46_3[29] == 1'b0) begin + result_wire_3 <= result_reg_46_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_46; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_9 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; +reg [29:0] result_reg_38_0; +reg [29:0] result_reg_38_1; +reg [29:0] result_reg_38_2; +reg [29:0] result_reg_38_3; +reg [29:0] result_reg_39_0; +reg [29:0] result_reg_39_1; +reg [29:0] result_reg_39_2; +reg [29:0] result_reg_39_3; +reg [29:0] result_reg_40_0; +reg [29:0] result_reg_40_1; +reg [29:0] result_reg_40_2; +reg [29:0] result_reg_40_3; +reg [29:0] result_reg_41_0; +reg [29:0] result_reg_41_1; +reg [29:0] result_reg_41_2; +reg [29:0] result_reg_41_3; +reg [29:0] result_reg_42_0; +reg [29:0] result_reg_42_1; +reg [29:0] result_reg_42_2; +reg [29:0] result_reg_42_3; +reg [29:0] result_reg_43_0; +reg [29:0] result_reg_43_1; +reg [29:0] result_reg_43_2; +reg [29:0] result_reg_43_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg out_valid_38; +reg out_valid_39; +reg out_valid_40; +reg out_valid_41; +reg out_valid_42; +reg out_valid_43; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; + out_valid_38 <= out_valid_37; + result_reg_38_0 <= result_reg_37_0; + result_reg_38_1 <= result_reg_37_1; + result_reg_38_2 <= result_reg_37_2; + result_reg_38_3 <= result_reg_37_3; + out_valid_39 <= out_valid_38; + result_reg_39_0 <= result_reg_38_0; + result_reg_39_1 <= result_reg_38_1; + result_reg_39_2 <= result_reg_38_2; + result_reg_39_3 <= result_reg_38_3; + out_valid_40 <= out_valid_39; + result_reg_40_0 <= result_reg_39_0; + result_reg_40_1 <= result_reg_39_1; + result_reg_40_2 <= result_reg_39_2; + result_reg_40_3 <= result_reg_39_3; + out_valid_41 <= out_valid_40; + result_reg_41_0 <= result_reg_40_0; + result_reg_41_1 <= result_reg_40_1; + result_reg_41_2 <= result_reg_40_2; + result_reg_41_3 <= result_reg_40_3; + out_valid_42 <= out_valid_41; + result_reg_42_0 <= result_reg_41_0; + result_reg_42_1 <= result_reg_41_1; + result_reg_42_2 <= result_reg_41_2; + result_reg_42_3 <= result_reg_41_3; + out_valid_43 <= out_valid_42; + result_reg_43_0 <= result_reg_42_0; + result_reg_43_1 <= result_reg_42_1; + result_reg_43_2 <= result_reg_42_2; + result_reg_43_3 <= result_reg_42_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_43_0[29] == 1'b0) begin + result_wire_0 <= result_reg_43_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_43_1[29] == 1'b0) begin + result_wire_1 <= result_reg_43_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_43_2[29] == 1'b0) begin + result_wire_2 <= result_reg_43_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_43_3[29] == 1'b0) begin + result_wire_3 <= result_reg_43_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_43; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_8 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; +reg [29:0] result_reg_29_0; +reg [29:0] result_reg_29_1; +reg [29:0] result_reg_29_2; +reg [29:0] result_reg_29_3; +reg [29:0] result_reg_30_0; +reg [29:0] result_reg_30_1; +reg [29:0] result_reg_30_2; +reg [29:0] result_reg_30_3; +reg [29:0] result_reg_31_0; +reg [29:0] result_reg_31_1; +reg [29:0] result_reg_31_2; +reg [29:0] result_reg_31_3; +reg [29:0] result_reg_32_0; +reg [29:0] result_reg_32_1; +reg [29:0] result_reg_32_2; +reg [29:0] result_reg_32_3; +reg [29:0] result_reg_33_0; +reg [29:0] result_reg_33_1; +reg [29:0] result_reg_33_2; +reg [29:0] result_reg_33_3; +reg [29:0] result_reg_34_0; +reg [29:0] result_reg_34_1; +reg [29:0] result_reg_34_2; +reg [29:0] result_reg_34_3; +reg [29:0] result_reg_35_0; +reg [29:0] result_reg_35_1; +reg [29:0] result_reg_35_2; +reg [29:0] result_reg_35_3; +reg [29:0] result_reg_36_0; +reg [29:0] result_reg_36_1; +reg [29:0] result_reg_36_2; +reg [29:0] result_reg_36_3; +reg [29:0] result_reg_37_0; +reg [29:0] result_reg_37_1; +reg [29:0] result_reg_37_2; +reg [29:0] result_reg_37_3; +reg [29:0] result_reg_38_0; +reg [29:0] result_reg_38_1; +reg [29:0] result_reg_38_2; +reg [29:0] result_reg_38_3; +reg [29:0] result_reg_39_0; +reg [29:0] result_reg_39_1; +reg [29:0] result_reg_39_2; +reg [29:0] result_reg_39_3; +reg [29:0] result_reg_40_0; +reg [29:0] result_reg_40_1; +reg [29:0] result_reg_40_2; +reg [29:0] result_reg_40_3; +reg [29:0] result_reg_41_0; +reg [29:0] result_reg_41_1; +reg [29:0] result_reg_41_2; +reg [29:0] result_reg_41_3; +reg [29:0] result_reg_42_0; +reg [29:0] result_reg_42_1; +reg [29:0] result_reg_42_2; +reg [29:0] result_reg_42_3; +reg [29:0] result_reg_43_0; +reg [29:0] result_reg_43_1; +reg [29:0] result_reg_43_2; +reg [29:0] result_reg_43_3; +reg [29:0] result_reg_44_0; +reg [29:0] result_reg_44_1; +reg [29:0] result_reg_44_2; +reg [29:0] result_reg_44_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg out_valid_29; +reg out_valid_30; +reg out_valid_31; +reg out_valid_32; +reg out_valid_33; +reg out_valid_34; +reg out_valid_35; +reg out_valid_36; +reg out_valid_37; +reg out_valid_38; +reg out_valid_39; +reg out_valid_40; +reg out_valid_41; +reg out_valid_42; +reg out_valid_43; +reg out_valid_44; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; + out_valid_29 <= out_valid_28; + result_reg_29_0 <= result_reg_28_0; + result_reg_29_1 <= result_reg_28_1; + result_reg_29_2 <= result_reg_28_2; + result_reg_29_3 <= result_reg_28_3; + out_valid_30 <= out_valid_29; + result_reg_30_0 <= result_reg_29_0; + result_reg_30_1 <= result_reg_29_1; + result_reg_30_2 <= result_reg_29_2; + result_reg_30_3 <= result_reg_29_3; + out_valid_31 <= out_valid_30; + result_reg_31_0 <= result_reg_30_0; + result_reg_31_1 <= result_reg_30_1; + result_reg_31_2 <= result_reg_30_2; + result_reg_31_3 <= result_reg_30_3; + out_valid_32 <= out_valid_31; + result_reg_32_0 <= result_reg_31_0; + result_reg_32_1 <= result_reg_31_1; + result_reg_32_2 <= result_reg_31_2; + result_reg_32_3 <= result_reg_31_3; + out_valid_33 <= out_valid_32; + result_reg_33_0 <= result_reg_32_0; + result_reg_33_1 <= result_reg_32_1; + result_reg_33_2 <= result_reg_32_2; + result_reg_33_3 <= result_reg_32_3; + out_valid_34 <= out_valid_33; + result_reg_34_0 <= result_reg_33_0; + result_reg_34_1 <= result_reg_33_1; + result_reg_34_2 <= result_reg_33_2; + result_reg_34_3 <= result_reg_33_3; + out_valid_35 <= out_valid_34; + result_reg_35_0 <= result_reg_34_0; + result_reg_35_1 <= result_reg_34_1; + result_reg_35_2 <= result_reg_34_2; + result_reg_35_3 <= result_reg_34_3; + out_valid_36 <= out_valid_35; + result_reg_36_0 <= result_reg_35_0; + result_reg_36_1 <= result_reg_35_1; + result_reg_36_2 <= result_reg_35_2; + result_reg_36_3 <= result_reg_35_3; + out_valid_37 <= out_valid_36; + result_reg_37_0 <= result_reg_36_0; + result_reg_37_1 <= result_reg_36_1; + result_reg_37_2 <= result_reg_36_2; + result_reg_37_3 <= result_reg_36_3; + out_valid_38 <= out_valid_37; + result_reg_38_0 <= result_reg_37_0; + result_reg_38_1 <= result_reg_37_1; + result_reg_38_2 <= result_reg_37_2; + result_reg_38_3 <= result_reg_37_3; + out_valid_39 <= out_valid_38; + result_reg_39_0 <= result_reg_38_0; + result_reg_39_1 <= result_reg_38_1; + result_reg_39_2 <= result_reg_38_2; + result_reg_39_3 <= result_reg_38_3; + out_valid_40 <= out_valid_39; + result_reg_40_0 <= result_reg_39_0; + result_reg_40_1 <= result_reg_39_1; + result_reg_40_2 <= result_reg_39_2; + result_reg_40_3 <= result_reg_39_3; + out_valid_41 <= out_valid_40; + result_reg_41_0 <= result_reg_40_0; + result_reg_41_1 <= result_reg_40_1; + result_reg_41_2 <= result_reg_40_2; + result_reg_41_3 <= result_reg_40_3; + out_valid_42 <= out_valid_41; + result_reg_42_0 <= result_reg_41_0; + result_reg_42_1 <= result_reg_41_1; + result_reg_42_2 <= result_reg_41_2; + result_reg_42_3 <= result_reg_41_3; + out_valid_43 <= out_valid_42; + result_reg_43_0 <= result_reg_42_0; + result_reg_43_1 <= result_reg_42_1; + result_reg_43_2 <= result_reg_42_2; + result_reg_43_3 <= result_reg_42_3; + out_valid_44 <= out_valid_43; + result_reg_44_0 <= result_reg_43_0; + result_reg_44_1 <= result_reg_43_1; + result_reg_44_2 <= result_reg_43_2; + result_reg_44_3 <= result_reg_43_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_44_0[29] == 1'b0) begin + result_wire_0 <= result_reg_44_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_44_1[29] == 1'b0) begin + result_wire_1 <= result_reg_44_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_44_2[29] == 1'b0) begin + result_wire_2 <= result_reg_44_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_44_3[29] == 1'b0) begin + result_wire_3 <= result_reg_44_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_44; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module winograd_transform_5 ( + input clk, + input i_valid, + input [15:0] i_result_0_0, + input [15:0] i_result_0_1, + input [15:0] i_result_0_2, + input [15:0] i_result_0_3, + input [15:0] i_result_0_4, + input [15:0] i_result_0_5, + input [15:0] i_result_0_6, + input [15:0] i_result_0_7, + input [15:0] i_result_1_0, + input [15:0] i_result_1_1, + input [15:0] i_result_1_2, + input [15:0] i_result_1_3, + input [15:0] i_result_1_4, + input [15:0] i_result_1_5, + input [15:0] i_result_1_6, + input [15:0] i_result_1_7, + input [15:0] i_result_2_0, + input [15:0] i_result_2_1, + input [15:0] i_result_2_2, + input [15:0] i_result_2_3, + input [15:0] i_result_2_4, + input [15:0] i_result_2_5, + input [15:0] i_result_2_6, + input [15:0] i_result_2_7, + input [15:0] i_result_3_0, + input [15:0] i_result_3_1, + input [15:0] i_result_3_2, + input [15:0] i_result_3_3, + input [15:0] i_result_3_4, + input [15:0] i_result_3_5, + input [15:0] i_result_3_6, + input [15:0] i_result_3_7, + input [15:0] i_result_4_0, + input [15:0] i_result_4_1, + input [15:0] i_result_4_2, + input [15:0] i_result_4_3, + input [15:0] i_result_4_4, + input [15:0] i_result_4_5, + input [15:0] i_result_4_6, + input [15:0] i_result_4_7, + input [15:0] i_result_5_0, + input [15:0] i_result_5_1, + input [15:0] i_result_5_2, + input [15:0] i_result_5_3, + input [15:0] i_result_5_4, + input [15:0] i_result_5_5, + input [15:0] i_result_5_6, + input [15:0] i_result_5_7, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output [15:0] o_feature_2, + output [15:0] o_feature_3, + output [15:0] o_feature_4, + output [15:0] o_feature_5, + output o_valid +); + +reg [15:0] input_buffer_0_0; +reg [19:0] output_buffer_0_0; +wire [19:0] rslt_buffer_0_0; +reg [15:0] input_buffer_0_1; +reg [19:0] output_buffer_0_1; +wire [19:0] rslt_buffer_0_1; +reg [15:0] input_buffer_0_2; +reg [19:0] output_buffer_0_2; +wire [19:0] rslt_buffer_0_2; +reg [15:0] input_buffer_0_3; +reg [19:0] output_buffer_0_3; +wire [19:0] rslt_buffer_0_3; +reg [15:0] input_buffer_0_4; +reg [19:0] output_buffer_0_4; +wire [19:0] rslt_buffer_0_4; +reg [15:0] input_buffer_0_5; +reg [19:0] output_buffer_0_5; +wire [19:0] rslt_buffer_0_5; +reg [15:0] input_buffer_1_0; +reg [19:0] output_buffer_1_0; +wire [19:0] rslt_buffer_1_0; +reg [15:0] input_buffer_1_1; +reg [19:0] output_buffer_1_1; +wire [19:0] rslt_buffer_1_1; +reg [15:0] input_buffer_1_2; +reg [19:0] output_buffer_1_2; +wire [19:0] rslt_buffer_1_2; +reg [15:0] input_buffer_1_3; +reg [19:0] output_buffer_1_3; +wire [19:0] rslt_buffer_1_3; +reg [15:0] input_buffer_1_4; +reg [19:0] output_buffer_1_4; +wire [19:0] rslt_buffer_1_4; +reg [15:0] input_buffer_1_5; +reg [19:0] output_buffer_1_5; +wire [19:0] rslt_buffer_1_5; +reg [15:0] input_buffer_2_0; +reg [19:0] output_buffer_2_0; +wire [19:0] rslt_buffer_2_0; +reg [15:0] input_buffer_2_1; +reg [19:0] output_buffer_2_1; +wire [19:0] rslt_buffer_2_1; +reg [15:0] input_buffer_2_2; +reg [19:0] output_buffer_2_2; +wire [19:0] rslt_buffer_2_2; +reg [15:0] input_buffer_2_3; +reg [19:0] output_buffer_2_3; +wire [19:0] rslt_buffer_2_3; +reg [15:0] input_buffer_2_4; +reg [19:0] output_buffer_2_4; +wire [19:0] rslt_buffer_2_4; +reg [15:0] input_buffer_2_5; +reg [19:0] output_buffer_2_5; +wire [19:0] rslt_buffer_2_5; +reg [15:0] input_buffer_3_0; +reg [19:0] output_buffer_3_0; +wire [19:0] rslt_buffer_3_0; +reg [15:0] input_buffer_3_1; +reg [19:0] output_buffer_3_1; +wire [19:0] rslt_buffer_3_1; +reg [15:0] input_buffer_3_2; +reg [19:0] output_buffer_3_2; +wire [19:0] rslt_buffer_3_2; +reg [15:0] input_buffer_3_3; +reg [19:0] output_buffer_3_3; +wire [19:0] rslt_buffer_3_3; +reg [15:0] input_buffer_3_4; +reg [19:0] output_buffer_3_4; +wire [19:0] rslt_buffer_3_4; +reg [15:0] input_buffer_3_5; +reg [19:0] output_buffer_3_5; +wire [19:0] rslt_buffer_3_5; +reg [15:0] input_buffer_4_0; +reg [19:0] output_buffer_4_0; +wire [19:0] rslt_buffer_4_0; +reg [15:0] input_buffer_4_1; +reg [19:0] output_buffer_4_1; +wire [19:0] rslt_buffer_4_1; +reg [15:0] input_buffer_4_2; +reg [19:0] output_buffer_4_2; +wire [19:0] rslt_buffer_4_2; +reg [15:0] input_buffer_4_3; +reg [19:0] output_buffer_4_3; +wire [19:0] rslt_buffer_4_3; +reg [15:0] input_buffer_4_4; +reg [19:0] output_buffer_4_4; +wire [19:0] rslt_buffer_4_4; +reg [15:0] input_buffer_4_5; +reg [19:0] output_buffer_4_5; +wire [19:0] rslt_buffer_4_5; +reg [15:0] input_buffer_5_0; +reg [19:0] output_buffer_5_0; +wire [19:0] rslt_buffer_5_0; +reg [15:0] input_buffer_5_1; +reg [19:0] output_buffer_5_1; +wire [19:0] rslt_buffer_5_1; +reg [15:0] input_buffer_5_2; +reg [19:0] output_buffer_5_2; +wire [19:0] rslt_buffer_5_2; +reg [15:0] input_buffer_5_3; +reg [19:0] output_buffer_5_3; +wire [19:0] rslt_buffer_5_3; +reg [15:0] input_buffer_5_4; +reg [19:0] output_buffer_5_4; +wire [19:0] rslt_buffer_5_4; +reg [15:0] input_buffer_5_5; +reg [19:0] output_buffer_5_5; +wire [19:0] rslt_buffer_5_5; +reg calculate, calculate_1, calculate_2, calculate_3; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg valid_12; +reg [2:0] input_buffer_count; +wire [15:0] dsp_out_1_0; +wire [15:0] dsp_out_1_1; +wire [15:0] dsp_out_1_2; +wire [15:0] dsp_out_1_3; +wire [15:0] dsp_out_1_4; +wire [15:0] dsp_out_1_5; +wire [15:0] dsp_out_1_6; +wire [15:0] dsp_out_1_7; +wire [15:0] dsp_out_1_8; +wire [15:0] dsp_out_1_9; +wire [15:0] dsp_out_1_10; +wire [15:0] dsp_out_1_11; +wire [15:0] dsp_out_2_0; +wire [15:0] dsp_out_2_1; +wire [15:0] dsp_out_2_2; +wire [15:0] dsp_out_2_3; +wire [15:0] dsp_out_2_4; +wire [15:0] dsp_out_2_5; +wire [15:0] dsp_out_2_6; +wire [15:0] dsp_out_2_7; +wire [15:0] dsp_out_3_0; +wire [15:0] dsp_out_3_1; +wire [15:0] dsp_out_3_2; +wire [15:0] dsp_out_3_3; +wire [15:0] dsp_out_3_4; +wire [15:0] dsp_out_3_5; +wire [15:0] dsp_out_3_6; +wire [15:0] dsp_out_3_7; +wire [15:0] dsp_out_4_0; +wire [15:0] dsp_out_4_1; +wire [15:0] dsp_out_4_2; +wire [15:0] dsp_out_4_3; +wire [15:0] dsp_out_4_4; +wire [15:0] dsp_out_4_5; +wire [15:0] dsp_out_4_6; +wire [15:0] dsp_out_4_7; +wire [15:0] dsp_out_5_0; +wire [15:0] dsp_out_5_1; +wire [15:0] dsp_out_5_2; +wire [15:0] dsp_out_5_3; +wire [15:0] dsp_out_5_4; +wire [15:0] dsp_out_5_5; +wire [15:0] dsp_out_5_6; +wire [15:0] dsp_out_5_7; +wire [15:0] dsp_out_6_0; +wire [15:0] dsp_out_6_1; +wire [15:0] dsp_out_6_2; +wire [15:0] dsp_out_6_3; +wire [15:0] dsp_out_6_4; +wire [15:0] dsp_out_6_5; +wire [15:0] dsp_out_6_6; +wire [15:0] dsp_out_6_7; +wire [15:0] dsp_out_6_8; +wire [15:0] dsp_out_6_9; +wire [15:0] dsp_out_6_10; +wire [15:0] dsp_out_6_11; +reg [15:0] feature_reg_0_0_0; +reg [15:0] feature_reg_0_0_1; +reg [15:0] feature_reg_0_1_0; +reg [15:0] feature_reg_0_1_1; +reg [15:0] feature_reg_0_2_0; +reg [15:0] feature_reg_0_2_1; +reg [15:0] feature_reg_0_3_0; +reg [15:0] feature_reg_0_3_1; +reg [15:0] feature_reg_0_4_0; +reg [15:0] feature_reg_0_4_1; +reg [15:0] feature_reg_0_5_0; +reg [15:0] feature_reg_0_5_1; +reg [15:0] feature_reg_1_0_0; +reg [15:0] feature_reg_1_0_1; +reg [15:0] feature_reg_1_1_0; +reg [15:0] feature_reg_1_1_1; +reg [15:0] feature_reg_1_2_0; +reg [15:0] feature_reg_1_2_1; +reg [15:0] feature_reg_1_3_0; +reg [15:0] feature_reg_1_3_1; +reg [15:0] feature_reg_1_4_0; +reg [15:0] feature_reg_1_4_1; +reg [15:0] feature_reg_1_5_0; +reg [15:0] feature_reg_1_5_1; +reg [15:0] feature_reg_2_0_0; +reg [15:0] feature_reg_2_0_1; +reg [15:0] feature_reg_2_1_0; +reg [15:0] feature_reg_2_1_1; +reg [15:0] feature_reg_2_2_0; +reg [15:0] feature_reg_2_2_1; +reg [15:0] feature_reg_2_3_0; +reg [15:0] feature_reg_2_3_1; +reg [15:0] feature_reg_2_4_0; +reg [15:0] feature_reg_2_4_1; +reg [15:0] feature_reg_2_5_0; +reg [15:0] feature_reg_2_5_1; +reg [15:0] feature_reg_3_0_0; +reg [15:0] feature_reg_3_0_1; +reg [15:0] feature_reg_3_1_0; +reg [15:0] feature_reg_3_1_1; +reg [15:0] feature_reg_3_2_0; +reg [15:0] feature_reg_3_2_1; +reg [15:0] feature_reg_3_3_0; +reg [15:0] feature_reg_3_3_1; +reg [15:0] feature_reg_3_4_0; +reg [15:0] feature_reg_3_4_1; +reg [15:0] feature_reg_3_5_0; +reg [15:0] feature_reg_3_5_1; +reg [15:0] feature_reg_4_0_0; +reg [15:0] feature_reg_4_0_1; +reg [15:0] feature_reg_4_1_0; +reg [15:0] feature_reg_4_1_1; +reg [15:0] feature_reg_4_2_0; +reg [15:0] feature_reg_4_2_1; +reg [15:0] feature_reg_4_3_0; +reg [15:0] feature_reg_4_3_1; +reg [15:0] feature_reg_4_4_0; +reg [15:0] feature_reg_4_4_1; +reg [15:0] feature_reg_4_5_0; +reg [15:0] feature_reg_4_5_1; +reg [15:0] feature_reg_5_0_0; +reg [15:0] feature_reg_5_0_1; +reg [15:0] feature_reg_5_1_0; +reg [15:0] feature_reg_5_1_1; +reg [15:0] feature_reg_5_2_0; +reg [15:0] feature_reg_5_2_1; +reg [15:0] feature_reg_5_3_0; +reg [15:0] feature_reg_5_3_1; +reg [15:0] feature_reg_5_4_0; +reg [15:0] feature_reg_5_4_1; +reg [15:0] feature_reg_5_5_0; +reg [15:0] feature_reg_5_5_1; + +always @ (posedge clk) begin + calculate_1 <= calculate; + calculate_2 <= calculate_1; + calculate_3 <= calculate_2; + //Valid pipeline + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + valid_12 <= valid_11; + if (i_valid) begin + input_buffer_count <= 0; + calculate <= 0; + end else begin + //Input buffering logic + if (input_buffer_count == 5) begin + calculate <= 1; + input_buffer_count <= 0; + end else begin + calculate <= 0; + input_buffer_count <= input_buffer_count + 1'b1; + end + input_buffer_5_0 <= i_result_0_5; + input_buffer_5_1 <= i_result_1_5; + input_buffer_5_2 <= i_result_2_5; + input_buffer_5_3 <= i_result_3_5; + input_buffer_5_4 <= i_result_4_5; + input_buffer_5_5 <= i_result_5_5; + end + input_buffer_0_0 <= input_buffer_1_0; + input_buffer_0_1 <= input_buffer_1_1; + input_buffer_0_2 <= input_buffer_1_2; + input_buffer_0_3 <= input_buffer_1_3; + input_buffer_0_4 <= input_buffer_1_4; + input_buffer_0_5 <= input_buffer_1_5; + input_buffer_1_0 <= input_buffer_2_0; + input_buffer_1_1 <= input_buffer_2_1; + input_buffer_1_2 <= input_buffer_2_2; + input_buffer_1_3 <= input_buffer_2_3; + input_buffer_1_4 <= input_buffer_2_4; + input_buffer_1_5 <= input_buffer_2_5; + input_buffer_2_0 <= input_buffer_3_0; + input_buffer_2_1 <= input_buffer_3_1; + input_buffer_2_2 <= input_buffer_3_2; + input_buffer_2_3 <= input_buffer_3_3; + input_buffer_2_4 <= input_buffer_3_4; + input_buffer_2_5 <= input_buffer_3_5; + input_buffer_3_0 <= input_buffer_4_0; + input_buffer_3_1 <= input_buffer_4_1; + input_buffer_3_2 <= input_buffer_4_2; + input_buffer_3_3 <= input_buffer_4_3; + input_buffer_3_4 <= input_buffer_4_4; + input_buffer_3_5 <= input_buffer_4_5; + input_buffer_4_0 <= input_buffer_5_0; + input_buffer_4_1 <= input_buffer_5_1; + input_buffer_4_2 <= input_buffer_5_2; + input_buffer_4_3 <= input_buffer_5_3; + input_buffer_4_4 <= input_buffer_5_4; + input_buffer_4_5 <= input_buffer_5_5; + //Pipelining to synchronize DSPs and non-DSPs + feature_reg_0_0_0 <= input_buffer_0_0; + feature_reg_0_1_0 <= input_buffer_0_1; + feature_reg_0_2_0 <= input_buffer_0_2; + feature_reg_0_3_0 <= input_buffer_0_3; + feature_reg_0_4_0 <= input_buffer_0_4; + feature_reg_0_5_0 <= input_buffer_0_5; + feature_reg_1_0_0 <= input_buffer_1_0; + feature_reg_1_1_0 <= input_buffer_1_1; + feature_reg_1_2_0 <= input_buffer_1_2; + feature_reg_1_3_0 <= input_buffer_1_3; + feature_reg_1_4_0 <= input_buffer_1_4; + feature_reg_1_5_0 <= input_buffer_1_5; + feature_reg_2_0_0 <= input_buffer_2_0; + feature_reg_2_1_0 <= input_buffer_2_1; + feature_reg_2_2_0 <= input_buffer_2_2; + feature_reg_2_3_0 <= input_buffer_2_3; + feature_reg_2_4_0 <= input_buffer_2_4; + feature_reg_2_5_0 <= input_buffer_2_5; + feature_reg_3_0_0 <= input_buffer_3_0; + feature_reg_3_1_0 <= input_buffer_3_1; + feature_reg_3_2_0 <= input_buffer_3_2; + feature_reg_3_3_0 <= input_buffer_3_3; + feature_reg_3_4_0 <= input_buffer_3_4; + feature_reg_3_5_0 <= input_buffer_3_5; + feature_reg_4_0_0 <= input_buffer_4_0; + feature_reg_4_1_0 <= input_buffer_4_1; + feature_reg_4_2_0 <= input_buffer_4_2; + feature_reg_4_3_0 <= input_buffer_4_3; + feature_reg_4_4_0 <= input_buffer_4_4; + feature_reg_4_5_0 <= input_buffer_4_5; + feature_reg_5_0_0 <= input_buffer_5_0; + feature_reg_5_1_0 <= input_buffer_5_1; + feature_reg_5_2_0 <= input_buffer_5_2; + feature_reg_5_3_0 <= input_buffer_5_3; + feature_reg_5_4_0 <= input_buffer_5_4; + feature_reg_5_5_0 <= input_buffer_5_5; + feature_reg_0_0_1 <= feature_reg_0_0_0; + feature_reg_0_1_1 <= feature_reg_0_1_0; + feature_reg_0_2_1 <= feature_reg_0_2_0; + feature_reg_0_3_1 <= feature_reg_0_3_0; + feature_reg_0_4_1 <= feature_reg_0_4_0; + feature_reg_0_5_1 <= feature_reg_0_5_0; + feature_reg_1_0_1 <= feature_reg_1_0_0; + feature_reg_1_1_1 <= feature_reg_1_1_0; + feature_reg_1_2_1 <= feature_reg_1_2_0; + feature_reg_1_3_1 <= feature_reg_1_3_0; + feature_reg_1_4_1 <= feature_reg_1_4_0; + feature_reg_1_5_1 <= feature_reg_1_5_0; + feature_reg_2_0_1 <= feature_reg_2_0_0; + feature_reg_2_1_1 <= feature_reg_2_1_0; + feature_reg_2_2_1 <= feature_reg_2_2_0; + feature_reg_2_3_1 <= feature_reg_2_3_0; + feature_reg_2_4_1 <= feature_reg_2_4_0; + feature_reg_2_5_1 <= feature_reg_2_5_0; + feature_reg_3_0_1 <= feature_reg_3_0_0; + feature_reg_3_1_1 <= feature_reg_3_1_0; + feature_reg_3_2_1 <= feature_reg_3_2_0; + feature_reg_3_3_1 <= feature_reg_3_3_0; + feature_reg_3_4_1 <= feature_reg_3_4_0; + feature_reg_3_5_1 <= feature_reg_3_5_0; + feature_reg_4_0_1 <= feature_reg_4_0_0; + feature_reg_4_1_1 <= feature_reg_4_1_0; + feature_reg_4_2_1 <= feature_reg_4_2_0; + feature_reg_4_3_1 <= feature_reg_4_3_0; + feature_reg_4_4_1 <= feature_reg_4_4_0; + feature_reg_4_5_1 <= feature_reg_4_5_0; + feature_reg_5_0_1 <= feature_reg_5_0_0; + feature_reg_5_1_1 <= feature_reg_5_1_0; + feature_reg_5_2_1 <= feature_reg_5_2_0; + feature_reg_5_3_1 <= feature_reg_5_3_0; + feature_reg_5_4_1 <= feature_reg_5_4_0; + feature_reg_5_5_1 <= feature_reg_5_5_0; + //Output Serializing logic + if (calculate_3) begin + output_buffer_0_0 <= rslt_buffer_0_0; + output_buffer_1_0 <= rslt_buffer_0_1; + output_buffer_2_0 <= rslt_buffer_0_2; + output_buffer_3_0 <= rslt_buffer_0_3; + output_buffer_4_0 <= rslt_buffer_0_4; + output_buffer_5_0 <= rslt_buffer_0_5; + output_buffer_0_1 <= rslt_buffer_1_0; + output_buffer_1_1 <= rslt_buffer_1_1; + output_buffer_2_1 <= rslt_buffer_1_2; + output_buffer_3_1 <= rslt_buffer_1_3; + output_buffer_4_1 <= rslt_buffer_1_4; + output_buffer_5_1 <= rslt_buffer_1_5; + output_buffer_0_2 <= rslt_buffer_2_0; + output_buffer_1_2 <= rslt_buffer_2_1; + output_buffer_2_2 <= rslt_buffer_2_2; + output_buffer_3_2 <= rslt_buffer_2_3; + output_buffer_4_2 <= rslt_buffer_2_4; + output_buffer_5_2 <= rslt_buffer_2_5; + output_buffer_0_3 <= rslt_buffer_3_0; + output_buffer_1_3 <= rslt_buffer_3_1; + output_buffer_2_3 <= rslt_buffer_3_2; + output_buffer_3_3 <= rslt_buffer_3_3; + output_buffer_4_3 <= rslt_buffer_3_4; + output_buffer_5_3 <= rslt_buffer_3_5; + output_buffer_0_4 <= rslt_buffer_4_0; + output_buffer_1_4 <= rslt_buffer_4_1; + output_buffer_2_4 <= rslt_buffer_4_2; + output_buffer_3_4 <= rslt_buffer_4_3; + output_buffer_4_4 <= rslt_buffer_4_4; + output_buffer_5_4 <= rslt_buffer_4_5; + output_buffer_0_5 <= rslt_buffer_5_0; + output_buffer_1_5 <= rslt_buffer_5_1; + output_buffer_2_5 <= rslt_buffer_5_2; + output_buffer_3_5 <= rslt_buffer_5_3; + output_buffer_4_5 <= rslt_buffer_5_4; + output_buffer_5_5 <= rslt_buffer_5_5; + end else begin + output_buffer_0_0 <= output_buffer_0_1; + output_buffer_0_1 <= output_buffer_0_2; + output_buffer_0_2 <= output_buffer_0_3; + output_buffer_0_3 <= output_buffer_0_4; + output_buffer_0_4 <= output_buffer_0_5; + output_buffer_1_0 <= output_buffer_1_1; + output_buffer_1_1 <= output_buffer_1_2; + output_buffer_1_2 <= output_buffer_1_3; + output_buffer_1_3 <= output_buffer_1_4; + output_buffer_1_4 <= output_buffer_1_5; + output_buffer_2_0 <= output_buffer_2_1; + output_buffer_2_1 <= output_buffer_2_2; + output_buffer_2_2 <= output_buffer_2_3; + output_buffer_2_3 <= output_buffer_2_4; + output_buffer_2_4 <= output_buffer_2_5; + output_buffer_3_0 <= output_buffer_3_1; + output_buffer_3_1 <= output_buffer_3_2; + output_buffer_3_2 <= output_buffer_3_3; + output_buffer_3_3 <= output_buffer_3_4; + output_buffer_3_4 <= output_buffer_3_5; + output_buffer_4_0 <= output_buffer_4_1; + output_buffer_4_1 <= output_buffer_4_2; + output_buffer_4_2 <= output_buffer_4_3; + output_buffer_4_3 <= output_buffer_4_4; + output_buffer_4_4 <= output_buffer_4_5; + output_buffer_5_0 <= output_buffer_5_1; + output_buffer_5_1 <= output_buffer_5_2; + output_buffer_5_2 <= output_buffer_5_3; + output_buffer_5_3 <= output_buffer_5_4; + output_buffer_5_4 <= output_buffer_5_5; + end +end + +////// FIRST COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD00 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_2), + .by(input_buffer_2_0), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_1_0), + .resultb(dsp_out_1_1) +); + +winograd_dsp_16 winograd_dsp_16_WD10 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_2_4), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_1_2), + .resultb(dsp_out_1_3) +); + +winograd_dsp_16 winograd_dsp_16_WD20 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_2), + .by(input_buffer_1_0), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_1_4), + .resultb(dsp_out_1_5) +); + +winograd_dsp_16 winograd_dsp_16_WD30 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_1_6), + .resultb(dsp_out_1_7) +); + +winograd_dsp_16 winograd_dsp_16_WD40 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_0), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_1_8), + .resultb(dsp_out_1_9) +); + +winograd_dsp_16 winograd_dsp_16_WD50 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_4), + .by(input_buffer_5_2), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_1_10), + .resultb(dsp_out_1_11) +); + +////// SECOND COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD01 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_0), + .resultb(dsp_out_2_1) +); + +winograd_dsp_16 winograd_dsp_16_WD11 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_2), + .resultb(dsp_out_2_3) +); + +winograd_dsp_16 winograd_dsp_16_WD21 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_4), + .resultb(dsp_out_2_5) +); + +winograd_dsp_16 winograd_dsp_16_WD31 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_6), + .resultb(dsp_out_2_7) +); + +////// THIRD COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD02 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_0), + .resultb(dsp_out_3_1) +); + +winograd_dsp_16 winograd_dsp_16_WD12 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_2), + .resultb(dsp_out_3_3) +); + +winograd_dsp_16 winograd_dsp_16_WD22 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_4), + .resultb(dsp_out_3_5) +); + +winograd_dsp_16 winograd_dsp_16_WD32 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_6), + .resultb(dsp_out_3_7) +); + +////// FOURTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD03 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_0), + .resultb(dsp_out_4_1) +); + +winograd_dsp_16 winograd_dsp_16_WD13 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_2), + .resultb(dsp_out_4_3) +); + +winograd_dsp_16 winograd_dsp_16_WD23 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_4), + .resultb(dsp_out_4_5) +); + +winograd_dsp_16 winograd_dsp_16_WD33 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_6), + .resultb(dsp_out_4_7) +); + +////// FIFTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD04 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_0), + .resultb(dsp_out_5_1) +); + +winograd_dsp_16 winograd_dsp_16_WD14 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_2), + .resultb(dsp_out_5_3) +); + +winograd_dsp_16 winograd_dsp_16_WD24 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_4), + .resultb(dsp_out_5_5) +); + +winograd_dsp_16 winograd_dsp_16_WD34 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_6), + .resultb(dsp_out_5_7) +); + +////// SIXTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD05 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_3), + .by(input_buffer_2_1), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_6_0), + .resultb(dsp_out_6_1) +); + +winograd_dsp_16 winograd_dsp_16_WD15 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_5), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_6_2), + .resultb(dsp_out_6_3) +); + +winograd_dsp_16 winograd_dsp_16_WD25 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_3), + .by(input_buffer_1_3), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_6_4), + .resultb(dsp_out_6_5) +); + +winograd_dsp_16 winograd_dsp_16_WD35 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_3_3), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_6_6), + .resultb(dsp_out_6_7) +); + +winograd_dsp_16 winograd_dsp_16_WD45 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_3), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_6_8), + .resultb(dsp_out_6_9) +); + +winograd_dsp_16 winograd_dsp_16_WD55 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_5), + .by(input_buffer_5_3), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_6_10), + .resultb(dsp_out_6_11) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA00 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_0_1[11:0], 4'b0000}), + .data1x(dsp_out_1_0), + .data2x({feature_reg_0_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_1), + .data4x(dsp_out_1_2), + .data5x(dsp_out_1_3), + .data6x({feature_reg_4_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_4), + .data8x(feature_reg_4_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_0) +); + +wire [15:0] f1, f2, f3, f4; +assign f1 = -{feature_reg_1_0_1[11:0], 4'b0000}; +assign f2 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f3 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f4 = -{feature_reg_2_4_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA10 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_1_5), + .data1x(f1), + .data2x(f2), + .data3x(f3), + .data4x(dsp_out_1_6), + .data5x(f4), + .data6x({feature_reg_3_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_7), + .data8x(feature_reg_3_4_1), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_0) +); + +wire [15:0] f5, f6, f7, f8, f9, f10; +assign f5 = -dsp_out_1_5; +assign f6 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f7 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f8 = -{feature_reg_3_0_1[13:0], 2'b00}; +assign f9 = -dsp_out_1_7; +assign f10 = -feature_reg_3_4_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA20 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f5), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(f6), + .data4x(dsp_out_1_6), + .data5x(f7), + .data6x(f8), + .data7x(f9), + .data8x(f10), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_0) +); + +wire [15:0] f11, f12, f13, f14, f15, f16, f17; +assign f11 = -{feature_reg_1_0_1[12:0], 3'b000}; +assign f12 = -{feature_reg_1_4_1[14:0], 1'b0}; +assign f13 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f14 = -feature_reg_2_4_1; +assign f15 = dsp_out_1_5 >>> 1; +assign f16 = dsp_out_1_6 >>> 2; +assign f17 = dsp_out_1_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA30 ( + .clock(clk), + .clken(calculate_2), + .data0x(f15), + .data1x(f11), + .data2x(f12), + .data3x(f13), + .data4x(f16), + .data5x(f14), + .data6x({feature_reg_3_0_1[12:0], 3'b000}), + .data7x(f17), + .data8x({feature_reg_3_4_1[14:0], 1'b0}), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_0) +); + +wire [15:0] f18, f19, f20, f21, f22, f23, f23b; +assign f18 = -(dsp_out_1_5 >>> 1); +assign f19 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f20 = -feature_reg_2_4_1; +assign f21 = -{feature_reg_3_0_1[12:0], 3'b000}; +assign f22 = -(dsp_out_1_7 <<< 1); +assign f23 = -{feature_reg_3_4_1[14:0], 1'b0}; +assign f23b = dsp_out_1_6 >>> 2; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA40 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[12:0], 3'b000}), + .data1x(f18), + .data2x({feature_reg_1_4_1[14:0], 1'b0}), + .data3x(f19), + .data4x(f23b), + .data5x(f20), + .data6x(f21), + .data7x(f22), + .data8x(f23), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_0) +); + +wire [15:0] f24; +assign f24 = -dsp_out_1_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA50 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f24), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_8), + .data4x(dsp_out_1_9), + .data5x(dsp_out_1_10), + .data6x({feature_reg_5_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_11), + .data8x(feature_reg_5_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_0) +); + +wire [15:0] f25, f26, f27, f28; +assign f25 = -{feature_reg_0_2_1[11:0], 4'b0000}; +assign f26 = -{feature_reg_0_1_1[11:0], 4'b0000}; +assign f27 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f28 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA01 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[13:0], 2'b00}), + .data1x(f25), + .data2x(f26), + .data3x({feature_reg_0_4_1[13:0], 2'b00}), + .data4x(dsp_out_2_0), + .data5x(dsp_out_2_1), + .data6x(dsp_out_2_2), + .data7x(dsp_out_2_3), + .data8x(f27), + .data9x(f28), + .data10x(feature_reg_4_3_1), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_1) +); + +wire [15:0] f29, f30, f31, f32, f33, f34, f35, f36; +assign f29 = -{feature_reg_1_3_1[13:0], 2'b00}; +assign f30 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f31 = -{feature_reg_2_3_1[13:0], 2'b00}; +assign f32 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f33 = -{feature_reg_3_1_1[13:0], 2'b00}; +assign f34 = -{feature_reg_3_2_1[13:0], 2'b00}; +assign f35 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f36 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA11 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0], 4'b0000}), + .data1x({feature_reg_1_2_1[11:0], 4'b0000}), + .data2x(f29), + .data3x(f30), + .data4x({feature_reg_2_1_1[11:0], 4'b0000}), + .data5x({feature_reg_2_2_1[11:0], 4'b0000}), + .data6x(f31), + .data7x(f32), + .data8x(f33), + .data9x(f34), + .data10x(feature_reg_3_3_1), + .data11x(feature_reg_3_4_1), + .data12x(f35), + .data13x(f36), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_1) +); + +wire [15:0] f37, f38, f39, f40, f41, f42, f43, f44; +assign f37 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f38 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f39 = -{feature_reg_2_3_1[13:0],2'b00}; +assign f40 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f41 = -feature_reg_3_3_1; +assign f42 = -feature_reg_3_4_1; +assign f43 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f44 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA21 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f37), + .data2x(f38), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[11:0],4'b0000}), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x(f39), + .data7x(f40), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(f41), + .data11x(f42), + .data12x(f43), + .data13x(f44), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_1) +); + +wire [15:0] f45, f46, f47, f48, f49, f50, f51, f52; +assign f45 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f46 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f47 = -feature_reg_2_3_1; +assign f48 = -feature_reg_2_4_1; +assign f49 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f50 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f51 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f52 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA31 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[12:0],3'b000}), + .data2x(f45), + .data3x(f46), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f47), + .data7x(f48), + .data8x(f49), + .data9x(f50), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f51), + .data13x(f52), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_1) +); + +wire [15:0] f53, f54, f55, f56, f57, f58, f59, f60; +assign f53 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f54 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f55 = -feature_reg_2_3_1; +assign f56 = -feature_reg_2_4_1; +assign f57 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f58 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f59 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f60 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA41 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[14:0],1'b0}), + .data1x(f53), + .data2x(f54), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f55), + .data7x(f56), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x(f57), + .data11x(f58), + .data12x(f59), + .data13x(f60), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_1) +); + +wire [15:0] f61, f62, f63, f64; +assign f61 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f62 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f63 = -{feature_reg_5_1_1[13:0],2'b00}; +assign f64 = -{feature_reg_5_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA51 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f61), + .data2x(f62), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_2_4), + .data5x(dsp_out_2_5), + .data6x(dsp_out_2_6), + .data7x(dsp_out_2_7), + .data8x(f63), + .data9x(f64), + .data10x(feature_reg_5_3_1), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_1) +); + +wire [15:0] f65, f66, f67, f68; +assign f65 = -{feature_reg_0_2_1[11:0],4'b0000}; +assign f66 = -{feature_reg_0_3_1[13:0],2'b00}; +assign f67 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f68 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA02 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(f65), + .data2x(f66), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_3_0), + .data5x(dsp_out_3_1), + .data6x(dsp_out_3_2), + .data7x(dsp_out_3_3), + .data8x({feature_reg_4_1_1[13:0],2'b00}), + .data9x(f67), + .data10x(f68), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_2) +); + +wire [15:0] f69, f70, f71, f72, f73, f74, f75, f76; +assign f69 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f70 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f71 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f72 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f73 = -{feature_reg_3_2_1[13:0],2'b00}; +assign f74 = -feature_reg_3_3_1; +assign f75 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f76 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA12 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[11:0],4'b0000}), + .data1x(f69), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f70), + .data4x(f71), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f72), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f73), + .data10x(f74), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f75), + .data14x(f76), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_2) +); + +wire [15:0] f77, f78, f79, f80, f81, f82, f83, f84; +assign f77 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f78 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f79 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f80 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f81 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f82 = -feature_reg_3_4_1; +assign f83 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f84 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA22 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f77), + .data2x(f78), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f79), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f80), + .data8x(f81), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(feature_reg_3_3_1), + .data11x(f82), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f83), + .data14x(f84), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_2) +); + +wire [15:0] f85, f86, f87, f88, f89, f90, f91, f92; +assign f85 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f86 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f87 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f88 = -feature_reg_2_4_1; +assign f89 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f90 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f91 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f92 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA32 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[12:0],3'b000}), + .data1x(f85), + .data2x({feature_reg_1_3_1[14:0],1'b0}), + .data3x(f86), + .data4x(f87), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f88), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x(f89), + .data10x(f90), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f91), + .data14x(f92), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_2) +); + +wire [15:0] f93, f94, f95, f96, f97, f98, f99, f100; +assign f93 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f94 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f95 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f96 = -feature_reg_2_4_1; +assign f97 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f98 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f99 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f100 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA42 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f93), + .data2x(f94), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f95), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f96), + .data8x(f97), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f98), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f99), + .data14x(f100), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_2) +); + +wire [15:0] f101, f102, f103, f104; +assign f101 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f102 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f103 = -{feature_reg_5_2_1[13:0],2'b00}; +assign f104 = -feature_reg_5_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA52 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f101), + .data2x(f102), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_3_4), + .data5x(dsp_out_3_5), + .data6x(dsp_out_3_6), + .data7x(dsp_out_3_7), + .data8x({feature_reg_5_1_1[13:0],2'b00}), + .data9x(f103), + .data10x(f104), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_2) +); + +wire [15:0] f105, f106, f107, f108; +assign f105 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f106 = -{feature_reg_0_1_1[12:0],3'b000}; +assign f107 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f108 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA03 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[12:0],3'b000}), + .data1x(f105), + .data2x(f106), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_4_0), + .data5x(dsp_out_4_1), + .data6x(dsp_out_4_2), + .data7x(dsp_out_4_3), + .data8x(f107), + .data9x(f108), + .data10x({feature_reg_4_3_1[14:0],1'b0}), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_3) +); + +wire [15:0] f109, f110, f111, f112, f113, f114, f115, f116; +assign f109 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f110 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f111 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f112 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f113 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f114 = -feature_reg_3_2_1; +assign f115 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f116 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA13 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[13:0],2'b00}), + .data2x(f109), + .data3x(f110), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f111), + .data7x(f112), + .data8x(f113), + .data9x(f114), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(feature_reg_3_4_1), + .data12x(f115), + .data13x(f116), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_3) +); + +wire [15:0] f117, f118, f119, f120, f121, f122, f123, f124; +assign f117 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f118 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f119 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f120 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f121 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f122 = -feature_reg_3_4_1; +assign f123 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f124 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA23 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f117), + .data2x(f118), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f119), + .data7x(f120), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(feature_reg_3_2_1), + .data10x(f121), + .data11x(f122), + .data12x(f123), + .data13x(f124), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_3) +); + +wire [15:0] f125, f126, f127, f128, f129, f130, f131, f132; +assign f125 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f126 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f127 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f128 = -feature_reg_2_4_1; +assign f129 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f130 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f131 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f132 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA33 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x({feature_reg_1_2_1[14:0],1'b0}), + .data2x(f125), + .data3x(f126), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f127), + .data7x(f128), + .data8x(f129), + .data9x(f130), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f131), + .data13x(f132), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_3) +); + +wire [15:0] f133, f134, f135, f136, f137, f138, f139, f140; +assign f133 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f134 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f135 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f136 = -feature_reg_2_4_1; +assign f137 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f138 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f139 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f140 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA43 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f133), + .data2x(f134), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f135), + .data7x(f136), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x(f137), + .data11x(f138), + .data12x(f139), + .data13x(f140), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_3) +); + +wire [15:0] f141, f142, f143, f144; +assign f141 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f142 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f143 = -{feature_reg_5_1_1[14:0],1'b0}; +assign f144 = -feature_reg_5_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA53 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f141), + .data2x(f142), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_4_4), + .data5x(dsp_out_4_5), + .data6x(dsp_out_4_6), + .data7x(dsp_out_4_7), + .data8x(f143), + .data9x(f144), + .data10x({feature_reg_5_3_1[14:0],1'b0}), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_3) +); + +wire [15:0] f145, f146, f147, f148; +assign f145 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f146 = -{feature_reg_0_3_1[12:0],3'b000}; +assign f147 = -feature_reg_4_2_1; +assign f148 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA04 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[12:0],3'b000}), + .data1x(f145), + .data2x(f146), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_5_0), + .data5x(dsp_out_5_1), + .data6x(dsp_out_5_2), + .data7x(dsp_out_5_3), + .data8x({feature_reg_4_1_1[14:0],1'b0}), + .data9x(f147), + .data10x(f148), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_4) +); + +wire [15:0] f149, f150, f151, f152, f153, f154, f155, f156; +assign f149 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f150 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f151 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f152 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f153 = -feature_reg_3_2_1; +assign f154 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f155 = -feature_reg_4_2_1; +assign f156 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA14 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[13:0],2'b00}), + .data1x(f149), + .data2x({feature_reg_1_3_1[12:0],3'b000}), + .data3x(f150), + .data4x(f151), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f152), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(f153), + .data10x(f154), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f155), + .data14x(f156), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_4) +); + +wire [15:0] f157, f158, f159, f160, f161, f162, f163, f164; +assign f157 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f158 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f159 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f160 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f161 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f162 = -feature_reg_3_4_1; +assign f163 = -feature_reg_4_2_1; +assign f164 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA24 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f157), + .data2x(f158), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f159), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f160), + .data8x(f161), + .data9x(feature_reg_3_2_1), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f162), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f163), + .data14x(f164), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_4) +); + +wire [15:0] f165, f166, f167, f168, f169, f170, f171, f172; +assign f165 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f166 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f167 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f168 = -feature_reg_2_4_1; +assign f169 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f170 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f171 = -feature_reg_4_2_1; +assign f172 = -{feature_reg_4_1_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA34 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[14:0],1'b0}), + .data1x(f165), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f166), + .data4x(f167), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f168), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f169), + .data10x(f170), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f171), + .data14x(f172), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_4) +); + +wire [15:0] f173, f174, f175, f176, f177, f178, f179, f180; +assign f173 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f174 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f175 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f176 = -feature_reg_2_4_1; +assign f177 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f178 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f179 = -feature_reg_4_2_1; +assign f180 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA44 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x(f173), + .data2x(f174), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f175), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f176), + .data8x(f177), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x(f178), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f179), + .data14x(f180), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_4) +); + +wire [15:0] f181, f182, f183, f184; +assign f181 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f182 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f183 = -feature_reg_5_2_1; +assign f184 = -{feature_reg_5_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA54 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f181), + .data2x(f182), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_5_4), + .data5x(dsp_out_5_5), + .data6x(dsp_out_5_6), + .data7x(dsp_out_5_7), + .data8x({feature_reg_5_1_1[14:0],1'b0}), + .data9x(f183), + .data10x(f184), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_4) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA05 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(dsp_out_6_0), + .data2x({feature_reg_0_5_1[13:0],2'b00}), + .data3x(dsp_out_6_1), + .data4x(dsp_out_6_2), + .data5x(dsp_out_6_3), + .data6x({feature_reg_4_1_1[13:0],2'b00}), + .data7x(dsp_out_6_4), + .data8x(feature_reg_4_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_5) +); + +wire [15:0] f185, f186, f187, f188; +assign f185 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f186 = -{feature_reg_1_5_1[13:0],2'b00}; +assign f187 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f188 = -{feature_reg_2_5_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA15 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_6_5), + .data1x(f185), + .data2x(f186), + .data3x(f187), + .data4x(dsp_out_6_6), + .data5x(f188), + .data6x({feature_reg_3_1_1[13:0],2'b00}), + .data7x(dsp_out_6_7), + .data8x(feature_reg_3_5_1), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_5) +); + +wire [15:0] f189, f190, f191, f192, f193, f194; +assign f189 = -dsp_out_6_5; +assign f190 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f191 = -{feature_reg_2_5_1[13:0],2'b00}; +assign f192 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f193 = -dsp_out_6_7; +assign f194 = -feature_reg_3_5_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA25 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f189), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(f190), + .data4x(dsp_out_6_6), + .data5x(f191), + .data6x(f192), + .data7x(f193), + .data8x(f194), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_5) +); + +wire [15:0] f195, f196, f197, f198, f199, f200, f201; +assign f195 = dsp_out_6_5 >>> 1; +assign f196 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f197 = -{feature_reg_1_5_1[14:0],1'b0}; +assign f198 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f199 = dsp_out_6_6 >>> 2; +assign f200 = -feature_reg_2_5_1; +assign f201 = dsp_out_6_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA35 ( + .clock(clk), + .clken(calculate_2), + .data0x(f195), + .data1x(f196), + .data2x(f197), + .data3x(f198), + .data4x(f199), + .data5x(f200), + .data6x({feature_reg_3_1_1[12:0],3'b000}), + .data7x(f201), + .data8x({feature_reg_3_5_1[14:0],1'b0}), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_5) +); + +wire [15:0] f202, f203, f204, f205, f206, f207, f208; +assign f202 = -(dsp_out_6_5 >>> 1); +assign f203 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f204 = dsp_out_6_6 >>> 2; +assign f205 = -feature_reg_2_5_1; +assign f206 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f207 = -(dsp_out_6_7 <<< 1); +assign f208 = -{feature_reg_3_5_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA45 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f202), + .data2x({feature_reg_1_5_1[14:0],1'b0}), + .data3x(f203), + .data4x(f204), + .data5x(f205), + .data6x(f206), + .data7x(f207), + .data8x(f208), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_5) +); + +wire [15:0] f209; +assign f209 = -dsp_out_6_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA55 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f209), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(dsp_out_6_8), + .data4x(dsp_out_6_9), + .data5x(dsp_out_6_10), + .data6x({feature_reg_5_1_1[13:0],2'b00}), + .data7x(dsp_out_6_11), + .data8x(feature_reg_5_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_5) +); + +assign o_feature_0 = output_buffer_0_0[15:0]; +assign o_feature_1 = output_buffer_1_0[15:0]; +assign o_feature_2 = output_buffer_2_0[15:0]; +assign o_feature_3 = output_buffer_3_0[15:0]; +assign o_feature_4 = output_buffer_4_0[15:0]; +assign o_feature_5 = output_buffer_5_0[15:0]; +assign o_valid = valid_9; + +endmodule + +module winograd_adder_16_20_4 ( + input clken, + input clock, + input [15:0] data0x, + input [15:0] data1x, + input [15:0] data2x, + input [15:0] data3x, + input [15:0] data4x, + input [15:0] data5x, + input [15:0] data6x, + input [15:0] data7x, + input [15:0] data8x, + input [15:0] data9x, + input [15:0] data10x, + input [15:0] data11x, + input [15:0] data12x, + input [15:0] data13x, + input [15:0] data14x, + input [15:0] data15x, + output [19:0] result +); + +reg [19:0] pipeline_0_0; +reg [19:0] pipeline_0_1; +reg [19:0] pipeline_0_2; +reg [19:0] pipeline_0_3; +reg [19:0] pipeline_0_4; +reg [19:0] pipeline_0_5; +reg [19:0] pipeline_0_6; +reg [19:0] pipeline_0_7; +reg [19:0] pipeline_1_0; +reg [19:0] pipeline_1_1; +reg [19:0] pipeline_1_2; +reg [19:0] pipeline_1_3; +reg [19:0] pipeline_2_0; +reg [19:0] pipeline_2_1; +reg [19:0] pipeline_3_0; + +always @ (posedge clock) begin + pipeline_0_0 <= data0x + data1x; + pipeline_0_1 <= data2x + data3x; + pipeline_0_2 <= data4x + data5x; + pipeline_0_3 <= data6x + data7x; + pipeline_0_4 <= data8x + data9x; + pipeline_0_5 <= data10x + data11x; + pipeline_0_6 <= data12x + data13x; + pipeline_0_7 <= data14x + data15x; + pipeline_1_0 <= pipeline_0_0 + pipeline_0_1; + pipeline_1_1 <= pipeline_0_2 + pipeline_0_3; + pipeline_1_2 <= pipeline_0_4 + pipeline_0_5; + pipeline_1_3 <= pipeline_0_6 + pipeline_0_7; + pipeline_2_0 <= pipeline_1_0 + pipeline_1_1; + pipeline_2_1 <= pipeline_1_2 + pipeline_1_3; + pipeline_3_0 <= pipeline_2_0 + pipeline_2_1; +end + +assign result = pipeline_3_0; + +endmodule + +module winograd_dsp_16 ( + input clk, + input ena, + input aclr, + input [15:0] ay, + input [15:0] by, + input [2:0] coefsela, + input [2:0] coefselb, + output [15:0] resulta, + output [15:0] resultb +); + +reg [15:0] coefa, coefb, ay_reg, by_reg, resa_reg, resb_reg; +assign resulta = resa_reg; +assign resultb = resb_reg; + +always @ (posedge clk) begin + if (aclr) begin + coefa <= 0; + coefb <= 0; + ay_reg <= 0; + by_reg <= 0; + resa_reg <= 0; + resb_reg <= 0; + end else begin + ay_reg <= ay; + by_reg <= by; + if (coefsela == 0) begin + coefa <= 5; + end else if (coefsela == 1) begin + coefa <= -5; + end else if (coefsela == 2) begin + coefa <= 10; + end else if (coefsela == 3) begin + coefa <= -10; + end else if (coefsela == 4) begin + coefa <= 20; + end else if (coefsela == 5) begin + coefa <= -20; + end else if (coefsela == 6) begin + coefa <= 25; + end else if (coefsela == 7) begin + coefa <= -25; + end else begin + coefa <= 0; + end + if (coefselb == 0) begin + coefb <= 5; + end else if (coefselb == 1) begin + coefb <= -5; + end else if (coefselb == 2) begin + coefb <= 10; + end else if (coefselb == 3) begin + coefb <= -10; + end else if (coefselb == 4) begin + coefb <= 20; + end else if (coefselb == 5) begin + coefb <= -20; + end else if (coefselb == 6) begin + coefb <= 25; + end else if (coefselb == 7) begin + coefb <= -25; + end else begin + coefb <= 0; + end + resa_reg <= ay_reg * coefa; + resb_reg <= by_reg * coefb; + end +end + +endmodule + +module winograd_transform_4 ( + input clk, + input i_valid, + input [15:0] i_result_0_0, + input [15:0] i_result_0_1, + input [15:0] i_result_0_2, + input [15:0] i_result_0_3, + input [15:0] i_result_0_4, + input [15:0] i_result_0_5, + input [15:0] i_result_0_6, + input [15:0] i_result_0_7, + input [15:0] i_result_1_0, + input [15:0] i_result_1_1, + input [15:0] i_result_1_2, + input [15:0] i_result_1_3, + input [15:0] i_result_1_4, + input [15:0] i_result_1_5, + input [15:0] i_result_1_6, + input [15:0] i_result_1_7, + input [15:0] i_result_2_0, + input [15:0] i_result_2_1, + input [15:0] i_result_2_2, + input [15:0] i_result_2_3, + input [15:0] i_result_2_4, + input [15:0] i_result_2_5, + input [15:0] i_result_2_6, + input [15:0] i_result_2_7, + input [15:0] i_result_3_0, + input [15:0] i_result_3_1, + input [15:0] i_result_3_2, + input [15:0] i_result_3_3, + input [15:0] i_result_3_4, + input [15:0] i_result_3_5, + input [15:0] i_result_3_6, + input [15:0] i_result_3_7, + input [15:0] i_result_4_0, + input [15:0] i_result_4_1, + input [15:0] i_result_4_2, + input [15:0] i_result_4_3, + input [15:0] i_result_4_4, + input [15:0] i_result_4_5, + input [15:0] i_result_4_6, + input [15:0] i_result_4_7, + input [15:0] i_result_5_0, + input [15:0] i_result_5_1, + input [15:0] i_result_5_2, + input [15:0] i_result_5_3, + input [15:0] i_result_5_4, + input [15:0] i_result_5_5, + input [15:0] i_result_5_6, + input [15:0] i_result_5_7, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output [15:0] o_feature_2, + output [15:0] o_feature_3, + output [15:0] o_feature_4, + output [15:0] o_feature_5, + output o_valid +); + +reg [15:0] input_buffer_0_0; +reg [19:0] output_buffer_0_0; +wire [19:0] rslt_buffer_0_0; +reg [15:0] input_buffer_0_1; +reg [19:0] output_buffer_0_1; +wire [19:0] rslt_buffer_0_1; +reg [15:0] input_buffer_0_2; +reg [19:0] output_buffer_0_2; +wire [19:0] rslt_buffer_0_2; +reg [15:0] input_buffer_0_3; +reg [19:0] output_buffer_0_3; +wire [19:0] rslt_buffer_0_3; +reg [15:0] input_buffer_0_4; +reg [19:0] output_buffer_0_4; +wire [19:0] rslt_buffer_0_4; +reg [15:0] input_buffer_0_5; +reg [19:0] output_buffer_0_5; +wire [19:0] rslt_buffer_0_5; +reg [15:0] input_buffer_1_0; +reg [19:0] output_buffer_1_0; +wire [19:0] rslt_buffer_1_0; +reg [15:0] input_buffer_1_1; +reg [19:0] output_buffer_1_1; +wire [19:0] rslt_buffer_1_1; +reg [15:0] input_buffer_1_2; +reg [19:0] output_buffer_1_2; +wire [19:0] rslt_buffer_1_2; +reg [15:0] input_buffer_1_3; +reg [19:0] output_buffer_1_3; +wire [19:0] rslt_buffer_1_3; +reg [15:0] input_buffer_1_4; +reg [19:0] output_buffer_1_4; +wire [19:0] rslt_buffer_1_4; +reg [15:0] input_buffer_1_5; +reg [19:0] output_buffer_1_5; +wire [19:0] rslt_buffer_1_5; +reg [15:0] input_buffer_2_0; +reg [19:0] output_buffer_2_0; +wire [19:0] rslt_buffer_2_0; +reg [15:0] input_buffer_2_1; +reg [19:0] output_buffer_2_1; +wire [19:0] rslt_buffer_2_1; +reg [15:0] input_buffer_2_2; +reg [19:0] output_buffer_2_2; +wire [19:0] rslt_buffer_2_2; +reg [15:0] input_buffer_2_3; +reg [19:0] output_buffer_2_3; +wire [19:0] rslt_buffer_2_3; +reg [15:0] input_buffer_2_4; +reg [19:0] output_buffer_2_4; +wire [19:0] rslt_buffer_2_4; +reg [15:0] input_buffer_2_5; +reg [19:0] output_buffer_2_5; +wire [19:0] rslt_buffer_2_5; +reg [15:0] input_buffer_3_0; +reg [19:0] output_buffer_3_0; +wire [19:0] rslt_buffer_3_0; +reg [15:0] input_buffer_3_1; +reg [19:0] output_buffer_3_1; +wire [19:0] rslt_buffer_3_1; +reg [15:0] input_buffer_3_2; +reg [19:0] output_buffer_3_2; +wire [19:0] rslt_buffer_3_2; +reg [15:0] input_buffer_3_3; +reg [19:0] output_buffer_3_3; +wire [19:0] rslt_buffer_3_3; +reg [15:0] input_buffer_3_4; +reg [19:0] output_buffer_3_4; +wire [19:0] rslt_buffer_3_4; +reg [15:0] input_buffer_3_5; +reg [19:0] output_buffer_3_5; +wire [19:0] rslt_buffer_3_5; +reg [15:0] input_buffer_4_0; +reg [19:0] output_buffer_4_0; +wire [19:0] rslt_buffer_4_0; +reg [15:0] input_buffer_4_1; +reg [19:0] output_buffer_4_1; +wire [19:0] rslt_buffer_4_1; +reg [15:0] input_buffer_4_2; +reg [19:0] output_buffer_4_2; +wire [19:0] rslt_buffer_4_2; +reg [15:0] input_buffer_4_3; +reg [19:0] output_buffer_4_3; +wire [19:0] rslt_buffer_4_3; +reg [15:0] input_buffer_4_4; +reg [19:0] output_buffer_4_4; +wire [19:0] rslt_buffer_4_4; +reg [15:0] input_buffer_4_5; +reg [19:0] output_buffer_4_5; +wire [19:0] rslt_buffer_4_5; +reg [15:0] input_buffer_5_0; +reg [19:0] output_buffer_5_0; +wire [19:0] rslt_buffer_5_0; +reg [15:0] input_buffer_5_1; +reg [19:0] output_buffer_5_1; +wire [19:0] rslt_buffer_5_1; +reg [15:0] input_buffer_5_2; +reg [19:0] output_buffer_5_2; +wire [19:0] rslt_buffer_5_2; +reg [15:0] input_buffer_5_3; +reg [19:0] output_buffer_5_3; +wire [19:0] rslt_buffer_5_3; +reg [15:0] input_buffer_5_4; +reg [19:0] output_buffer_5_4; +wire [19:0] rslt_buffer_5_4; +reg [15:0] input_buffer_5_5; +reg [19:0] output_buffer_5_5; +wire [19:0] rslt_buffer_5_5; +reg calculate, calculate_1, calculate_2, calculate_3; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg valid_12; +reg [2:0] input_buffer_count; +wire [15:0] dsp_out_1_0; +wire [15:0] dsp_out_1_1; +wire [15:0] dsp_out_1_2; +wire [15:0] dsp_out_1_3; +wire [15:0] dsp_out_1_4; +wire [15:0] dsp_out_1_5; +wire [15:0] dsp_out_1_6; +wire [15:0] dsp_out_1_7; +wire [15:0] dsp_out_1_8; +wire [15:0] dsp_out_1_9; +wire [15:0] dsp_out_1_10; +wire [15:0] dsp_out_1_11; +wire [15:0] dsp_out_2_0; +wire [15:0] dsp_out_2_1; +wire [15:0] dsp_out_2_2; +wire [15:0] dsp_out_2_3; +wire [15:0] dsp_out_2_4; +wire [15:0] dsp_out_2_5; +wire [15:0] dsp_out_2_6; +wire [15:0] dsp_out_2_7; +wire [15:0] dsp_out_3_0; +wire [15:0] dsp_out_3_1; +wire [15:0] dsp_out_3_2; +wire [15:0] dsp_out_3_3; +wire [15:0] dsp_out_3_4; +wire [15:0] dsp_out_3_5; +wire [15:0] dsp_out_3_6; +wire [15:0] dsp_out_3_7; +wire [15:0] dsp_out_4_0; +wire [15:0] dsp_out_4_1; +wire [15:0] dsp_out_4_2; +wire [15:0] dsp_out_4_3; +wire [15:0] dsp_out_4_4; +wire [15:0] dsp_out_4_5; +wire [15:0] dsp_out_4_6; +wire [15:0] dsp_out_4_7; +wire [15:0] dsp_out_5_0; +wire [15:0] dsp_out_5_1; +wire [15:0] dsp_out_5_2; +wire [15:0] dsp_out_5_3; +wire [15:0] dsp_out_5_4; +wire [15:0] dsp_out_5_5; +wire [15:0] dsp_out_5_6; +wire [15:0] dsp_out_5_7; +wire [15:0] dsp_out_6_0; +wire [15:0] dsp_out_6_1; +wire [15:0] dsp_out_6_2; +wire [15:0] dsp_out_6_3; +wire [15:0] dsp_out_6_4; +wire [15:0] dsp_out_6_5; +wire [15:0] dsp_out_6_6; +wire [15:0] dsp_out_6_7; +wire [15:0] dsp_out_6_8; +wire [15:0] dsp_out_6_9; +wire [15:0] dsp_out_6_10; +wire [15:0] dsp_out_6_11; +reg [15:0] feature_reg_0_0_0; +reg [15:0] feature_reg_0_0_1; +reg [15:0] feature_reg_0_1_0; +reg [15:0] feature_reg_0_1_1; +reg [15:0] feature_reg_0_2_0; +reg [15:0] feature_reg_0_2_1; +reg [15:0] feature_reg_0_3_0; +reg [15:0] feature_reg_0_3_1; +reg [15:0] feature_reg_0_4_0; +reg [15:0] feature_reg_0_4_1; +reg [15:0] feature_reg_0_5_0; +reg [15:0] feature_reg_0_5_1; +reg [15:0] feature_reg_1_0_0; +reg [15:0] feature_reg_1_0_1; +reg [15:0] feature_reg_1_1_0; +reg [15:0] feature_reg_1_1_1; +reg [15:0] feature_reg_1_2_0; +reg [15:0] feature_reg_1_2_1; +reg [15:0] feature_reg_1_3_0; +reg [15:0] feature_reg_1_3_1; +reg [15:0] feature_reg_1_4_0; +reg [15:0] feature_reg_1_4_1; +reg [15:0] feature_reg_1_5_0; +reg [15:0] feature_reg_1_5_1; +reg [15:0] feature_reg_2_0_0; +reg [15:0] feature_reg_2_0_1; +reg [15:0] feature_reg_2_1_0; +reg [15:0] feature_reg_2_1_1; +reg [15:0] feature_reg_2_2_0; +reg [15:0] feature_reg_2_2_1; +reg [15:0] feature_reg_2_3_0; +reg [15:0] feature_reg_2_3_1; +reg [15:0] feature_reg_2_4_0; +reg [15:0] feature_reg_2_4_1; +reg [15:0] feature_reg_2_5_0; +reg [15:0] feature_reg_2_5_1; +reg [15:0] feature_reg_3_0_0; +reg [15:0] feature_reg_3_0_1; +reg [15:0] feature_reg_3_1_0; +reg [15:0] feature_reg_3_1_1; +reg [15:0] feature_reg_3_2_0; +reg [15:0] feature_reg_3_2_1; +reg [15:0] feature_reg_3_3_0; +reg [15:0] feature_reg_3_3_1; +reg [15:0] feature_reg_3_4_0; +reg [15:0] feature_reg_3_4_1; +reg [15:0] feature_reg_3_5_0; +reg [15:0] feature_reg_3_5_1; +reg [15:0] feature_reg_4_0_0; +reg [15:0] feature_reg_4_0_1; +reg [15:0] feature_reg_4_1_0; +reg [15:0] feature_reg_4_1_1; +reg [15:0] feature_reg_4_2_0; +reg [15:0] feature_reg_4_2_1; +reg [15:0] feature_reg_4_3_0; +reg [15:0] feature_reg_4_3_1; +reg [15:0] feature_reg_4_4_0; +reg [15:0] feature_reg_4_4_1; +reg [15:0] feature_reg_4_5_0; +reg [15:0] feature_reg_4_5_1; +reg [15:0] feature_reg_5_0_0; +reg [15:0] feature_reg_5_0_1; +reg [15:0] feature_reg_5_1_0; +reg [15:0] feature_reg_5_1_1; +reg [15:0] feature_reg_5_2_0; +reg [15:0] feature_reg_5_2_1; +reg [15:0] feature_reg_5_3_0; +reg [15:0] feature_reg_5_3_1; +reg [15:0] feature_reg_5_4_0; +reg [15:0] feature_reg_5_4_1; +reg [15:0] feature_reg_5_5_0; +reg [15:0] feature_reg_5_5_1; + +always @ (posedge clk) begin + calculate_1 <= calculate; + calculate_2 <= calculate_1; + calculate_3 <= calculate_2; + //Valid pipeline + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + valid_12 <= valid_11; + if (i_valid) begin + input_buffer_count <= 0; + calculate <= 0; + end else begin + //Input buffering logic + if (input_buffer_count == 5) begin + calculate <= 1; + input_buffer_count <= 0; + end else begin + calculate <= 0; + input_buffer_count <= input_buffer_count + 1'b1; + end + input_buffer_5_0 <= i_result_0_4; + input_buffer_5_1 <= i_result_1_4; + input_buffer_5_2 <= i_result_2_4; + input_buffer_5_3 <= i_result_3_4; + input_buffer_5_4 <= i_result_4_4; + input_buffer_5_5 <= i_result_5_4; + end + input_buffer_0_0 <= input_buffer_1_0; + input_buffer_0_1 <= input_buffer_1_1; + input_buffer_0_2 <= input_buffer_1_2; + input_buffer_0_3 <= input_buffer_1_3; + input_buffer_0_4 <= input_buffer_1_4; + input_buffer_0_5 <= input_buffer_1_5; + input_buffer_1_0 <= input_buffer_2_0; + input_buffer_1_1 <= input_buffer_2_1; + input_buffer_1_2 <= input_buffer_2_2; + input_buffer_1_3 <= input_buffer_2_3; + input_buffer_1_4 <= input_buffer_2_4; + input_buffer_1_5 <= input_buffer_2_5; + input_buffer_2_0 <= input_buffer_3_0; + input_buffer_2_1 <= input_buffer_3_1; + input_buffer_2_2 <= input_buffer_3_2; + input_buffer_2_3 <= input_buffer_3_3; + input_buffer_2_4 <= input_buffer_3_4; + input_buffer_2_5 <= input_buffer_3_5; + input_buffer_3_0 <= input_buffer_4_0; + input_buffer_3_1 <= input_buffer_4_1; + input_buffer_3_2 <= input_buffer_4_2; + input_buffer_3_3 <= input_buffer_4_3; + input_buffer_3_4 <= input_buffer_4_4; + input_buffer_3_5 <= input_buffer_4_5; + input_buffer_4_0 <= input_buffer_5_0; + input_buffer_4_1 <= input_buffer_5_1; + input_buffer_4_2 <= input_buffer_5_2; + input_buffer_4_3 <= input_buffer_5_3; + input_buffer_4_4 <= input_buffer_5_4; + input_buffer_4_5 <= input_buffer_5_5; + //Pipelining to synchronize DSPs and non-DSPs + feature_reg_0_0_0 <= input_buffer_0_0; + feature_reg_0_1_0 <= input_buffer_0_1; + feature_reg_0_2_0 <= input_buffer_0_2; + feature_reg_0_3_0 <= input_buffer_0_3; + feature_reg_0_4_0 <= input_buffer_0_4; + feature_reg_0_5_0 <= input_buffer_0_5; + feature_reg_1_0_0 <= input_buffer_1_0; + feature_reg_1_1_0 <= input_buffer_1_1; + feature_reg_1_2_0 <= input_buffer_1_2; + feature_reg_1_3_0 <= input_buffer_1_3; + feature_reg_1_4_0 <= input_buffer_1_4; + feature_reg_1_5_0 <= input_buffer_1_5; + feature_reg_2_0_0 <= input_buffer_2_0; + feature_reg_2_1_0 <= input_buffer_2_1; + feature_reg_2_2_0 <= input_buffer_2_2; + feature_reg_2_3_0 <= input_buffer_2_3; + feature_reg_2_4_0 <= input_buffer_2_4; + feature_reg_2_5_0 <= input_buffer_2_5; + feature_reg_3_0_0 <= input_buffer_3_0; + feature_reg_3_1_0 <= input_buffer_3_1; + feature_reg_3_2_0 <= input_buffer_3_2; + feature_reg_3_3_0 <= input_buffer_3_3; + feature_reg_3_4_0 <= input_buffer_3_4; + feature_reg_3_5_0 <= input_buffer_3_5; + feature_reg_4_0_0 <= input_buffer_4_0; + feature_reg_4_1_0 <= input_buffer_4_1; + feature_reg_4_2_0 <= input_buffer_4_2; + feature_reg_4_3_0 <= input_buffer_4_3; + feature_reg_4_4_0 <= input_buffer_4_4; + feature_reg_4_5_0 <= input_buffer_4_5; + feature_reg_5_0_0 <= input_buffer_5_0; + feature_reg_5_1_0 <= input_buffer_5_1; + feature_reg_5_2_0 <= input_buffer_5_2; + feature_reg_5_3_0 <= input_buffer_5_3; + feature_reg_5_4_0 <= input_buffer_5_4; + feature_reg_5_5_0 <= input_buffer_5_5; + feature_reg_0_0_1 <= feature_reg_0_0_0; + feature_reg_0_1_1 <= feature_reg_0_1_0; + feature_reg_0_2_1 <= feature_reg_0_2_0; + feature_reg_0_3_1 <= feature_reg_0_3_0; + feature_reg_0_4_1 <= feature_reg_0_4_0; + feature_reg_0_5_1 <= feature_reg_0_5_0; + feature_reg_1_0_1 <= feature_reg_1_0_0; + feature_reg_1_1_1 <= feature_reg_1_1_0; + feature_reg_1_2_1 <= feature_reg_1_2_0; + feature_reg_1_3_1 <= feature_reg_1_3_0; + feature_reg_1_4_1 <= feature_reg_1_4_0; + feature_reg_1_5_1 <= feature_reg_1_5_0; + feature_reg_2_0_1 <= feature_reg_2_0_0; + feature_reg_2_1_1 <= feature_reg_2_1_0; + feature_reg_2_2_1 <= feature_reg_2_2_0; + feature_reg_2_3_1 <= feature_reg_2_3_0; + feature_reg_2_4_1 <= feature_reg_2_4_0; + feature_reg_2_5_1 <= feature_reg_2_5_0; + feature_reg_3_0_1 <= feature_reg_3_0_0; + feature_reg_3_1_1 <= feature_reg_3_1_0; + feature_reg_3_2_1 <= feature_reg_3_2_0; + feature_reg_3_3_1 <= feature_reg_3_3_0; + feature_reg_3_4_1 <= feature_reg_3_4_0; + feature_reg_3_5_1 <= feature_reg_3_5_0; + feature_reg_4_0_1 <= feature_reg_4_0_0; + feature_reg_4_1_1 <= feature_reg_4_1_0; + feature_reg_4_2_1 <= feature_reg_4_2_0; + feature_reg_4_3_1 <= feature_reg_4_3_0; + feature_reg_4_4_1 <= feature_reg_4_4_0; + feature_reg_4_5_1 <= feature_reg_4_5_0; + feature_reg_5_0_1 <= feature_reg_5_0_0; + feature_reg_5_1_1 <= feature_reg_5_1_0; + feature_reg_5_2_1 <= feature_reg_5_2_0; + feature_reg_5_3_1 <= feature_reg_5_3_0; + feature_reg_5_4_1 <= feature_reg_5_4_0; + feature_reg_5_5_1 <= feature_reg_5_5_0; + //Output Serializing logic + if (calculate_3) begin + output_buffer_0_0 <= rslt_buffer_0_0; + output_buffer_1_0 <= rslt_buffer_0_1; + output_buffer_2_0 <= rslt_buffer_0_2; + output_buffer_3_0 <= rslt_buffer_0_3; + output_buffer_4_0 <= rslt_buffer_0_4; + output_buffer_5_0 <= rslt_buffer_0_5; + output_buffer_0_1 <= rslt_buffer_1_0; + output_buffer_1_1 <= rslt_buffer_1_1; + output_buffer_2_1 <= rslt_buffer_1_2; + output_buffer_3_1 <= rslt_buffer_1_3; + output_buffer_4_1 <= rslt_buffer_1_4; + output_buffer_5_1 <= rslt_buffer_1_5; + output_buffer_0_2 <= rslt_buffer_2_0; + output_buffer_1_2 <= rslt_buffer_2_1; + output_buffer_2_2 <= rslt_buffer_2_2; + output_buffer_3_2 <= rslt_buffer_2_3; + output_buffer_4_2 <= rslt_buffer_2_4; + output_buffer_5_2 <= rslt_buffer_2_5; + output_buffer_0_3 <= rslt_buffer_3_0; + output_buffer_1_3 <= rslt_buffer_3_1; + output_buffer_2_3 <= rslt_buffer_3_2; + output_buffer_3_3 <= rslt_buffer_3_3; + output_buffer_4_3 <= rslt_buffer_3_4; + output_buffer_5_3 <= rslt_buffer_3_5; + output_buffer_0_4 <= rslt_buffer_4_0; + output_buffer_1_4 <= rslt_buffer_4_1; + output_buffer_2_4 <= rslt_buffer_4_2; + output_buffer_3_4 <= rslt_buffer_4_3; + output_buffer_4_4 <= rslt_buffer_4_4; + output_buffer_5_4 <= rslt_buffer_4_5; + output_buffer_0_5 <= rslt_buffer_5_0; + output_buffer_1_5 <= rslt_buffer_5_1; + output_buffer_2_5 <= rslt_buffer_5_2; + output_buffer_3_5 <= rslt_buffer_5_3; + output_buffer_4_5 <= rslt_buffer_5_4; + output_buffer_5_5 <= rslt_buffer_5_5; + end else begin + output_buffer_0_0 <= output_buffer_0_1; + output_buffer_0_1 <= output_buffer_0_2; + output_buffer_0_2 <= output_buffer_0_3; + output_buffer_0_3 <= output_buffer_0_4; + output_buffer_0_4 <= output_buffer_0_5; + output_buffer_1_0 <= output_buffer_1_1; + output_buffer_1_1 <= output_buffer_1_2; + output_buffer_1_2 <= output_buffer_1_3; + output_buffer_1_3 <= output_buffer_1_4; + output_buffer_1_4 <= output_buffer_1_5; + output_buffer_2_0 <= output_buffer_2_1; + output_buffer_2_1 <= output_buffer_2_2; + output_buffer_2_2 <= output_buffer_2_3; + output_buffer_2_3 <= output_buffer_2_4; + output_buffer_2_4 <= output_buffer_2_5; + output_buffer_3_0 <= output_buffer_3_1; + output_buffer_3_1 <= output_buffer_3_2; + output_buffer_3_2 <= output_buffer_3_3; + output_buffer_3_3 <= output_buffer_3_4; + output_buffer_3_4 <= output_buffer_3_5; + output_buffer_4_0 <= output_buffer_4_1; + output_buffer_4_1 <= output_buffer_4_2; + output_buffer_4_2 <= output_buffer_4_3; + output_buffer_4_3 <= output_buffer_4_4; + output_buffer_4_4 <= output_buffer_4_5; + output_buffer_5_0 <= output_buffer_5_1; + output_buffer_5_1 <= output_buffer_5_2; + output_buffer_5_2 <= output_buffer_5_3; + output_buffer_5_3 <= output_buffer_5_4; + output_buffer_5_4 <= output_buffer_5_5; + end +end + +////// FIRST COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD00 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_2), + .by(input_buffer_2_0), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_1_0), + .resultb(dsp_out_1_1) +); + +winograd_dsp_16 winograd_dsp_16_WD10 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_2_4), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_1_2), + .resultb(dsp_out_1_3) +); + +winograd_dsp_16 winograd_dsp_16_WD20 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_2), + .by(input_buffer_1_0), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_1_4), + .resultb(dsp_out_1_5) +); + +winograd_dsp_16 winograd_dsp_16_WD30 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_1_6), + .resultb(dsp_out_1_7) +); + +winograd_dsp_16 winograd_dsp_16_WD40 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_0), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_1_8), + .resultb(dsp_out_1_9) +); + +winograd_dsp_16 winograd_dsp_16_WD50 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_4), + .by(input_buffer_5_2), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_1_10), + .resultb(dsp_out_1_11) +); + +////// SECOND COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD01 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_0), + .resultb(dsp_out_2_1) +); + +winograd_dsp_16 winograd_dsp_16_WD11 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_2), + .resultb(dsp_out_2_3) +); + +winograd_dsp_16 winograd_dsp_16_WD21 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_4), + .resultb(dsp_out_2_5) +); + +winograd_dsp_16 winograd_dsp_16_WD31 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_6), + .resultb(dsp_out_2_7) +); + +////// THIRD COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD02 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_0), + .resultb(dsp_out_3_1) +); + +winograd_dsp_16 winograd_dsp_16_WD12 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_2), + .resultb(dsp_out_3_3) +); + +winograd_dsp_16 winograd_dsp_16_WD22 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_4), + .resultb(dsp_out_3_5) +); + +winograd_dsp_16 winograd_dsp_16_WD32 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_6), + .resultb(dsp_out_3_7) +); + +////// FOURTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD03 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_0), + .resultb(dsp_out_4_1) +); + +winograd_dsp_16 winograd_dsp_16_WD13 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_2), + .resultb(dsp_out_4_3) +); + +winograd_dsp_16 winograd_dsp_16_WD23 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_4), + .resultb(dsp_out_4_5) +); + +winograd_dsp_16 winograd_dsp_16_WD33 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_6), + .resultb(dsp_out_4_7) +); + +////// FIFTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD04 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_0), + .resultb(dsp_out_5_1) +); + +winograd_dsp_16 winograd_dsp_16_WD14 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_2), + .resultb(dsp_out_5_3) +); + +winograd_dsp_16 winograd_dsp_16_WD24 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_4), + .resultb(dsp_out_5_5) +); + +winograd_dsp_16 winograd_dsp_16_WD34 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_6), + .resultb(dsp_out_5_7) +); + +////// SIXTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD05 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_3), + .by(input_buffer_2_1), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_6_0), + .resultb(dsp_out_6_1) +); + +winograd_dsp_16 winograd_dsp_16_WD15 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_5), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_6_2), + .resultb(dsp_out_6_3) +); + +winograd_dsp_16 winograd_dsp_16_WD25 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_3), + .by(input_buffer_1_3), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_6_4), + .resultb(dsp_out_6_5) +); + +winograd_dsp_16 winograd_dsp_16_WD35 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_3_3), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_6_6), + .resultb(dsp_out_6_7) +); + +winograd_dsp_16 winograd_dsp_16_WD45 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_3), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_6_8), + .resultb(dsp_out_6_9) +); + +winograd_dsp_16 winograd_dsp_16_WD55 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_5), + .by(input_buffer_5_3), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_6_10), + .resultb(dsp_out_6_11) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA00 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_0_1[11:0], 4'b0000}), + .data1x(dsp_out_1_0), + .data2x({feature_reg_0_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_1), + .data4x(dsp_out_1_2), + .data5x(dsp_out_1_3), + .data6x({feature_reg_4_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_4), + .data8x(feature_reg_4_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_0) +); + +wire [15:0] f1, f2, f3, f4; +assign f1 = -{feature_reg_1_0_1[11:0], 4'b0000}; +assign f2 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f3 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f4 = -{feature_reg_2_4_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA10 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_1_5), + .data1x(f1), + .data2x(f2), + .data3x(f3), + .data4x(dsp_out_1_6), + .data5x(f4), + .data6x({feature_reg_3_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_7), + .data8x(feature_reg_3_4_1), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_0) +); + +wire [15:0] f5, f6, f7, f8, f9, f10; +assign f5 = -dsp_out_1_5; +assign f6 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f7 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f8 = -{feature_reg_3_0_1[13:0], 2'b00}; +assign f9 = -dsp_out_1_7; +assign f10 = -feature_reg_3_4_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA20 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f5), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(f6), + .data4x(dsp_out_1_6), + .data5x(f7), + .data6x(f8), + .data7x(f9), + .data8x(f10), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_0) +); + +wire [15:0] f11, f12, f13, f14, f15, f16, f17; +assign f11 = -{feature_reg_1_0_1[12:0], 3'b000}; +assign f12 = -{feature_reg_1_4_1[14:0], 1'b0}; +assign f13 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f14 = -feature_reg_2_4_1; +assign f15 = dsp_out_1_5 >>> 1; +assign f16 = dsp_out_1_6 >>> 2; +assign f17 = dsp_out_1_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA30 ( + .clock(clk), + .clken(calculate_2), + .data0x(f15), + .data1x(f11), + .data2x(f12), + .data3x(f13), + .data4x(f16), + .data5x(f14), + .data6x({feature_reg_3_0_1[12:0], 3'b000}), + .data7x(f17), + .data8x({feature_reg_3_4_1[14:0], 1'b0}), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_0) +); + +wire [15:0] f18, f19, f20, f21, f22, f23, f23b; +assign f18 = -(dsp_out_1_5 >>> 1); +assign f19 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f20 = -feature_reg_2_4_1; +assign f21 = -{feature_reg_3_0_1[12:0], 3'b000}; +assign f22 = -(dsp_out_1_7 <<< 1); +assign f23 = -{feature_reg_3_4_1[14:0], 1'b0}; +assign f23b = dsp_out_1_6 >>> 2; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA40 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[12:0], 3'b000}), + .data1x(f18), + .data2x({feature_reg_1_4_1[14:0], 1'b0}), + .data3x(f19), + .data4x(f23b), + .data5x(f20), + .data6x(f21), + .data7x(f22), + .data8x(f23), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_0) +); + +wire [15:0] f24; +assign f24 = -dsp_out_1_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA50 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f24), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_8), + .data4x(dsp_out_1_9), + .data5x(dsp_out_1_10), + .data6x({feature_reg_5_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_11), + .data8x(feature_reg_5_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_0) +); + +wire [15:0] f25, f26, f27, f28; +assign f25 = -{feature_reg_0_2_1[11:0], 4'b0000}; +assign f26 = -{feature_reg_0_1_1[11:0], 4'b0000}; +assign f27 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f28 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA01 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[13:0], 2'b00}), + .data1x(f25), + .data2x(f26), + .data3x({feature_reg_0_4_1[13:0], 2'b00}), + .data4x(dsp_out_2_0), + .data5x(dsp_out_2_1), + .data6x(dsp_out_2_2), + .data7x(dsp_out_2_3), + .data8x(f27), + .data9x(f28), + .data10x(feature_reg_4_3_1), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_1) +); + +wire [15:0] f29, f30, f31, f32, f33, f34, f35, f36; +assign f29 = -{feature_reg_1_3_1[13:0], 2'b00}; +assign f30 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f31 = -{feature_reg_2_3_1[13:0], 2'b00}; +assign f32 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f33 = -{feature_reg_3_1_1[13:0], 2'b00}; +assign f34 = -{feature_reg_3_2_1[13:0], 2'b00}; +assign f35 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f36 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA11 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0], 4'b0000}), + .data1x({feature_reg_1_2_1[11:0], 4'b0000}), + .data2x(f29), + .data3x(f30), + .data4x({feature_reg_2_1_1[11:0], 4'b0000}), + .data5x({feature_reg_2_2_1[11:0], 4'b0000}), + .data6x(f31), + .data7x(f32), + .data8x(f33), + .data9x(f34), + .data10x(feature_reg_3_3_1), + .data11x(feature_reg_3_4_1), + .data12x(f35), + .data13x(f36), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_1) +); + +wire [15:0] f37, f38, f39, f40, f41, f42, f43, f44; +assign f37 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f38 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f39 = -{feature_reg_2_3_1[13:0],2'b00}; +assign f40 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f41 = -feature_reg_3_3_1; +assign f42 = -feature_reg_3_4_1; +assign f43 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f44 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA21 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f37), + .data2x(f38), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[11:0],4'b0000}), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x(f39), + .data7x(f40), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(f41), + .data11x(f42), + .data12x(f43), + .data13x(f44), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_1) +); + +wire [15:0] f45, f46, f47, f48, f49, f50, f51, f52; +assign f45 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f46 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f47 = -feature_reg_2_3_1; +assign f48 = -feature_reg_2_4_1; +assign f49 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f50 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f51 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f52 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA31 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[12:0],3'b000}), + .data2x(f45), + .data3x(f46), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f47), + .data7x(f48), + .data8x(f49), + .data9x(f50), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f51), + .data13x(f52), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_1) +); + +wire [15:0] f53, f54, f55, f56, f57, f58, f59, f60; +assign f53 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f54 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f55 = -feature_reg_2_3_1; +assign f56 = -feature_reg_2_4_1; +assign f57 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f58 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f59 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f60 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA41 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[14:0],1'b0}), + .data1x(f53), + .data2x(f54), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f55), + .data7x(f56), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x(f57), + .data11x(f58), + .data12x(f59), + .data13x(f60), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_1) +); + +wire [15:0] f61, f62, f63, f64; +assign f61 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f62 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f63 = -{feature_reg_5_1_1[13:0],2'b00}; +assign f64 = -{feature_reg_5_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA51 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f61), + .data2x(f62), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_2_4), + .data5x(dsp_out_2_5), + .data6x(dsp_out_2_6), + .data7x(dsp_out_2_7), + .data8x(f63), + .data9x(f64), + .data10x(feature_reg_5_3_1), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_1) +); + +wire [15:0] f65, f66, f67, f68; +assign f65 = -{feature_reg_0_2_1[11:0],4'b0000}; +assign f66 = -{feature_reg_0_3_1[13:0],2'b00}; +assign f67 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f68 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA02 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(f65), + .data2x(f66), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_3_0), + .data5x(dsp_out_3_1), + .data6x(dsp_out_3_2), + .data7x(dsp_out_3_3), + .data8x({feature_reg_4_1_1[13:0],2'b00}), + .data9x(f67), + .data10x(f68), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_2) +); + +wire [15:0] f69, f70, f71, f72, f73, f74, f75, f76; +assign f69 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f70 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f71 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f72 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f73 = -{feature_reg_3_2_1[13:0],2'b00}; +assign f74 = -feature_reg_3_3_1; +assign f75 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f76 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA12 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[11:0],4'b0000}), + .data1x(f69), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f70), + .data4x(f71), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f72), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f73), + .data10x(f74), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f75), + .data14x(f76), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_2) +); + +wire [15:0] f77, f78, f79, f80, f81, f82, f83, f84; +assign f77 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f78 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f79 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f80 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f81 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f82 = -feature_reg_3_4_1; +assign f83 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f84 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA22 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f77), + .data2x(f78), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f79), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f80), + .data8x(f81), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(feature_reg_3_3_1), + .data11x(f82), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f83), + .data14x(f84), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_2) +); + +wire [15:0] f85, f86, f87, f88, f89, f90, f91, f92; +assign f85 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f86 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f87 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f88 = -feature_reg_2_4_1; +assign f89 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f90 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f91 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f92 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA32 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[12:0],3'b000}), + .data1x(f85), + .data2x({feature_reg_1_3_1[14:0],1'b0}), + .data3x(f86), + .data4x(f87), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f88), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x(f89), + .data10x(f90), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f91), + .data14x(f92), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_2) +); + +wire [15:0] f93, f94, f95, f96, f97, f98, f99, f100; +assign f93 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f94 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f95 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f96 = -feature_reg_2_4_1; +assign f97 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f98 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f99 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f100 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA42 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f93), + .data2x(f94), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f95), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f96), + .data8x(f97), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f98), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f99), + .data14x(f100), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_2) +); + +wire [15:0] f101, f102, f103, f104; +assign f101 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f102 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f103 = -{feature_reg_5_2_1[13:0],2'b00}; +assign f104 = -feature_reg_5_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA52 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f101), + .data2x(f102), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_3_4), + .data5x(dsp_out_3_5), + .data6x(dsp_out_3_6), + .data7x(dsp_out_3_7), + .data8x({feature_reg_5_1_1[13:0],2'b00}), + .data9x(f103), + .data10x(f104), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_2) +); + +wire [15:0] f105, f106, f107, f108; +assign f105 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f106 = -{feature_reg_0_1_1[12:0],3'b000}; +assign f107 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f108 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA03 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[12:0],3'b000}), + .data1x(f105), + .data2x(f106), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_4_0), + .data5x(dsp_out_4_1), + .data6x(dsp_out_4_2), + .data7x(dsp_out_4_3), + .data8x(f107), + .data9x(f108), + .data10x({feature_reg_4_3_1[14:0],1'b0}), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_3) +); + +wire [15:0] f109, f110, f111, f112, f113, f114, f115, f116; +assign f109 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f110 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f111 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f112 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f113 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f114 = -feature_reg_3_2_1; +assign f115 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f116 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA13 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[13:0],2'b00}), + .data2x(f109), + .data3x(f110), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f111), + .data7x(f112), + .data8x(f113), + .data9x(f114), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(feature_reg_3_4_1), + .data12x(f115), + .data13x(f116), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_3) +); + +wire [15:0] f117, f118, f119, f120, f121, f122, f123, f124; +assign f117 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f118 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f119 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f120 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f121 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f122 = -feature_reg_3_4_1; +assign f123 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f124 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA23 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f117), + .data2x(f118), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f119), + .data7x(f120), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(feature_reg_3_2_1), + .data10x(f121), + .data11x(f122), + .data12x(f123), + .data13x(f124), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_3) +); + +wire [15:0] f125, f126, f127, f128, f129, f130, f131, f132; +assign f125 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f126 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f127 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f128 = -feature_reg_2_4_1; +assign f129 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f130 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f131 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f132 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA33 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x({feature_reg_1_2_1[14:0],1'b0}), + .data2x(f125), + .data3x(f126), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f127), + .data7x(f128), + .data8x(f129), + .data9x(f130), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f131), + .data13x(f132), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_3) +); + +wire [15:0] f133, f134, f135, f136, f137, f138, f139, f140; +assign f133 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f134 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f135 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f136 = -feature_reg_2_4_1; +assign f137 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f138 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f139 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f140 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA43 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f133), + .data2x(f134), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f135), + .data7x(f136), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x(f137), + .data11x(f138), + .data12x(f139), + .data13x(f140), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_3) +); + +wire [15:0] f141, f142, f143, f144; +assign f141 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f142 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f143 = -{feature_reg_5_1_1[14:0],1'b0}; +assign f144 = -feature_reg_5_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA53 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f141), + .data2x(f142), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_4_4), + .data5x(dsp_out_4_5), + .data6x(dsp_out_4_6), + .data7x(dsp_out_4_7), + .data8x(f143), + .data9x(f144), + .data10x({feature_reg_5_3_1[14:0],1'b0}), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_3) +); + +wire [15:0] f145, f146, f147, f148; +assign f145 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f146 = -{feature_reg_0_3_1[12:0],3'b000}; +assign f147 = -feature_reg_4_2_1; +assign f148 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA04 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[12:0],3'b000}), + .data1x(f145), + .data2x(f146), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_5_0), + .data5x(dsp_out_5_1), + .data6x(dsp_out_5_2), + .data7x(dsp_out_5_3), + .data8x({feature_reg_4_1_1[14:0],1'b0}), + .data9x(f147), + .data10x(f148), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_4) +); + +wire [15:0] f149, f150, f151, f152, f153, f154, f155, f156; +assign f149 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f150 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f151 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f152 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f153 = -feature_reg_3_2_1; +assign f154 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f155 = -feature_reg_4_2_1; +assign f156 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA14 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[13:0],2'b00}), + .data1x(f149), + .data2x({feature_reg_1_3_1[12:0],3'b000}), + .data3x(f150), + .data4x(f151), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f152), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(f153), + .data10x(f154), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f155), + .data14x(f156), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_4) +); + +wire [15:0] f157, f158, f159, f160, f161, f162, f163, f164; +assign f157 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f158 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f159 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f160 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f161 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f162 = -feature_reg_3_4_1; +assign f163 = -feature_reg_4_2_1; +assign f164 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA24 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f157), + .data2x(f158), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f159), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f160), + .data8x(f161), + .data9x(feature_reg_3_2_1), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f162), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f163), + .data14x(f164), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_4) +); + +wire [15:0] f165, f166, f167, f168, f169, f170, f171, f172; +assign f165 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f166 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f167 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f168 = -feature_reg_2_4_1; +assign f169 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f170 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f171 = -feature_reg_4_2_1; +assign f172 = -{feature_reg_4_1_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA34 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[14:0],1'b0}), + .data1x(f165), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f166), + .data4x(f167), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f168), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f169), + .data10x(f170), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f171), + .data14x(f172), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_4) +); + +wire [15:0] f173, f174, f175, f176, f177, f178, f179, f180; +assign f173 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f174 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f175 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f176 = -feature_reg_2_4_1; +assign f177 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f178 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f179 = -feature_reg_4_2_1; +assign f180 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA44 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x(f173), + .data2x(f174), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f175), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f176), + .data8x(f177), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x(f178), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f179), + .data14x(f180), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_4) +); + +wire [15:0] f181, f182, f183, f184; +assign f181 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f182 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f183 = -feature_reg_5_2_1; +assign f184 = -{feature_reg_5_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA54 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f181), + .data2x(f182), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_5_4), + .data5x(dsp_out_5_5), + .data6x(dsp_out_5_6), + .data7x(dsp_out_5_7), + .data8x({feature_reg_5_1_1[14:0],1'b0}), + .data9x(f183), + .data10x(f184), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_4) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA05 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(dsp_out_6_0), + .data2x({feature_reg_0_5_1[13:0],2'b00}), + .data3x(dsp_out_6_1), + .data4x(dsp_out_6_2), + .data5x(dsp_out_6_3), + .data6x({feature_reg_4_1_1[13:0],2'b00}), + .data7x(dsp_out_6_4), + .data8x(feature_reg_4_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_5) +); + +wire [15:0] f185, f186, f187, f188; +assign f185 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f186 = -{feature_reg_1_5_1[13:0],2'b00}; +assign f187 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f188 = -{feature_reg_2_5_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA15 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_6_5), + .data1x(f185), + .data2x(f186), + .data3x(f187), + .data4x(dsp_out_6_6), + .data5x(f188), + .data6x({feature_reg_3_1_1[13:0],2'b00}), + .data7x(dsp_out_6_7), + .data8x(feature_reg_3_5_1), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_5) +); + +wire [15:0] f189, f190, f191, f192, f193, f194; +assign f189 = -dsp_out_6_5; +assign f190 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f191 = -{feature_reg_2_5_1[13:0],2'b00}; +assign f192 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f193 = -dsp_out_6_7; +assign f194 = -feature_reg_3_5_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA25 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f189), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(f190), + .data4x(dsp_out_6_6), + .data5x(f191), + .data6x(f192), + .data7x(f193), + .data8x(f194), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_5) +); + +wire [15:0] f195, f196, f197, f198, f199, f200, f201; +assign f195 = dsp_out_6_5 >>> 1; +assign f196 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f197 = -{feature_reg_1_5_1[14:0],1'b0}; +assign f198 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f199 = dsp_out_6_6 >>> 2; +assign f200 = -feature_reg_2_5_1; +assign f201 = dsp_out_6_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA35 ( + .clock(clk), + .clken(calculate_2), + .data0x(f195), + .data1x(f196), + .data2x(f197), + .data3x(f198), + .data4x(f199), + .data5x(f200), + .data6x({feature_reg_3_1_1[12:0],3'b000}), + .data7x(f201), + .data8x({feature_reg_3_5_1[14:0],1'b0}), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_5) +); + +wire [15:0] f202, f203, f204, f205, f206, f207, f208; +assign f202 = -(dsp_out_6_5 >>> 1); +assign f203 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f204 = dsp_out_6_6 >>> 2; +assign f205 = -feature_reg_2_5_1; +assign f206 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f207 = -(dsp_out_6_7 <<< 1); +assign f208 = -{feature_reg_3_5_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA45 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f202), + .data2x({feature_reg_1_5_1[14:0],1'b0}), + .data3x(f203), + .data4x(f204), + .data5x(f205), + .data6x(f206), + .data7x(f207), + .data8x(f208), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_5) +); + +wire [15:0] f209; +assign f209 = -dsp_out_6_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA55 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f209), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(dsp_out_6_8), + .data4x(dsp_out_6_9), + .data5x(dsp_out_6_10), + .data6x({feature_reg_5_1_1[13:0],2'b00}), + .data7x(dsp_out_6_11), + .data8x(feature_reg_5_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_5) +); + +assign o_feature_0 = output_buffer_0_0[15:0]; +assign o_feature_1 = output_buffer_1_0[15:0]; +assign o_feature_2 = output_buffer_2_0[15:0]; +assign o_feature_3 = output_buffer_3_0[15:0]; +assign o_feature_4 = output_buffer_4_0[15:0]; +assign o_feature_5 = output_buffer_5_0[15:0]; +assign o_valid = valid_9; + +endmodule + +module winograd_transform_7 ( + input clk, + input i_valid, + input [15:0] i_result_0_0, + input [15:0] i_result_0_1, + input [15:0] i_result_0_2, + input [15:0] i_result_0_3, + input [15:0] i_result_0_4, + input [15:0] i_result_0_5, + input [15:0] i_result_0_6, + input [15:0] i_result_0_7, + input [15:0] i_result_1_0, + input [15:0] i_result_1_1, + input [15:0] i_result_1_2, + input [15:0] i_result_1_3, + input [15:0] i_result_1_4, + input [15:0] i_result_1_5, + input [15:0] i_result_1_6, + input [15:0] i_result_1_7, + input [15:0] i_result_2_0, + input [15:0] i_result_2_1, + input [15:0] i_result_2_2, + input [15:0] i_result_2_3, + input [15:0] i_result_2_4, + input [15:0] i_result_2_5, + input [15:0] i_result_2_6, + input [15:0] i_result_2_7, + input [15:0] i_result_3_0, + input [15:0] i_result_3_1, + input [15:0] i_result_3_2, + input [15:0] i_result_3_3, + input [15:0] i_result_3_4, + input [15:0] i_result_3_5, + input [15:0] i_result_3_6, + input [15:0] i_result_3_7, + input [15:0] i_result_4_0, + input [15:0] i_result_4_1, + input [15:0] i_result_4_2, + input [15:0] i_result_4_3, + input [15:0] i_result_4_4, + input [15:0] i_result_4_5, + input [15:0] i_result_4_6, + input [15:0] i_result_4_7, + input [15:0] i_result_5_0, + input [15:0] i_result_5_1, + input [15:0] i_result_5_2, + input [15:0] i_result_5_3, + input [15:0] i_result_5_4, + input [15:0] i_result_5_5, + input [15:0] i_result_5_6, + input [15:0] i_result_5_7, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output [15:0] o_feature_2, + output [15:0] o_feature_3, + output [15:0] o_feature_4, + output [15:0] o_feature_5, + output o_valid +); + +reg [15:0] input_buffer_0_0; +reg [19:0] output_buffer_0_0; +wire [19:0] rslt_buffer_0_0; +reg [15:0] input_buffer_0_1; +reg [19:0] output_buffer_0_1; +wire [19:0] rslt_buffer_0_1; +reg [15:0] input_buffer_0_2; +reg [19:0] output_buffer_0_2; +wire [19:0] rslt_buffer_0_2; +reg [15:0] input_buffer_0_3; +reg [19:0] output_buffer_0_3; +wire [19:0] rslt_buffer_0_3; +reg [15:0] input_buffer_0_4; +reg [19:0] output_buffer_0_4; +wire [19:0] rslt_buffer_0_4; +reg [15:0] input_buffer_0_5; +reg [19:0] output_buffer_0_5; +wire [19:0] rslt_buffer_0_5; +reg [15:0] input_buffer_1_0; +reg [19:0] output_buffer_1_0; +wire [19:0] rslt_buffer_1_0; +reg [15:0] input_buffer_1_1; +reg [19:0] output_buffer_1_1; +wire [19:0] rslt_buffer_1_1; +reg [15:0] input_buffer_1_2; +reg [19:0] output_buffer_1_2; +wire [19:0] rslt_buffer_1_2; +reg [15:0] input_buffer_1_3; +reg [19:0] output_buffer_1_3; +wire [19:0] rslt_buffer_1_3; +reg [15:0] input_buffer_1_4; +reg [19:0] output_buffer_1_4; +wire [19:0] rslt_buffer_1_4; +reg [15:0] input_buffer_1_5; +reg [19:0] output_buffer_1_5; +wire [19:0] rslt_buffer_1_5; +reg [15:0] input_buffer_2_0; +reg [19:0] output_buffer_2_0; +wire [19:0] rslt_buffer_2_0; +reg [15:0] input_buffer_2_1; +reg [19:0] output_buffer_2_1; +wire [19:0] rslt_buffer_2_1; +reg [15:0] input_buffer_2_2; +reg [19:0] output_buffer_2_2; +wire [19:0] rslt_buffer_2_2; +reg [15:0] input_buffer_2_3; +reg [19:0] output_buffer_2_3; +wire [19:0] rslt_buffer_2_3; +reg [15:0] input_buffer_2_4; +reg [19:0] output_buffer_2_4; +wire [19:0] rslt_buffer_2_4; +reg [15:0] input_buffer_2_5; +reg [19:0] output_buffer_2_5; +wire [19:0] rslt_buffer_2_5; +reg [15:0] input_buffer_3_0; +reg [19:0] output_buffer_3_0; +wire [19:0] rslt_buffer_3_0; +reg [15:0] input_buffer_3_1; +reg [19:0] output_buffer_3_1; +wire [19:0] rslt_buffer_3_1; +reg [15:0] input_buffer_3_2; +reg [19:0] output_buffer_3_2; +wire [19:0] rslt_buffer_3_2; +reg [15:0] input_buffer_3_3; +reg [19:0] output_buffer_3_3; +wire [19:0] rslt_buffer_3_3; +reg [15:0] input_buffer_3_4; +reg [19:0] output_buffer_3_4; +wire [19:0] rslt_buffer_3_4; +reg [15:0] input_buffer_3_5; +reg [19:0] output_buffer_3_5; +wire [19:0] rslt_buffer_3_5; +reg [15:0] input_buffer_4_0; +reg [19:0] output_buffer_4_0; +wire [19:0] rslt_buffer_4_0; +reg [15:0] input_buffer_4_1; +reg [19:0] output_buffer_4_1; +wire [19:0] rslt_buffer_4_1; +reg [15:0] input_buffer_4_2; +reg [19:0] output_buffer_4_2; +wire [19:0] rslt_buffer_4_2; +reg [15:0] input_buffer_4_3; +reg [19:0] output_buffer_4_3; +wire [19:0] rslt_buffer_4_3; +reg [15:0] input_buffer_4_4; +reg [19:0] output_buffer_4_4; +wire [19:0] rslt_buffer_4_4; +reg [15:0] input_buffer_4_5; +reg [19:0] output_buffer_4_5; +wire [19:0] rslt_buffer_4_5; +reg [15:0] input_buffer_5_0; +reg [19:0] output_buffer_5_0; +wire [19:0] rslt_buffer_5_0; +reg [15:0] input_buffer_5_1; +reg [19:0] output_buffer_5_1; +wire [19:0] rslt_buffer_5_1; +reg [15:0] input_buffer_5_2; +reg [19:0] output_buffer_5_2; +wire [19:0] rslt_buffer_5_2; +reg [15:0] input_buffer_5_3; +reg [19:0] output_buffer_5_3; +wire [19:0] rslt_buffer_5_3; +reg [15:0] input_buffer_5_4; +reg [19:0] output_buffer_5_4; +wire [19:0] rslt_buffer_5_4; +reg [15:0] input_buffer_5_5; +reg [19:0] output_buffer_5_5; +wire [19:0] rslt_buffer_5_5; +reg calculate, calculate_1, calculate_2, calculate_3; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg valid_12; +reg [2:0] input_buffer_count; +wire [15:0] dsp_out_1_0; +wire [15:0] dsp_out_1_1; +wire [15:0] dsp_out_1_2; +wire [15:0] dsp_out_1_3; +wire [15:0] dsp_out_1_4; +wire [15:0] dsp_out_1_5; +wire [15:0] dsp_out_1_6; +wire [15:0] dsp_out_1_7; +wire [15:0] dsp_out_1_8; +wire [15:0] dsp_out_1_9; +wire [15:0] dsp_out_1_10; +wire [15:0] dsp_out_1_11; +wire [15:0] dsp_out_2_0; +wire [15:0] dsp_out_2_1; +wire [15:0] dsp_out_2_2; +wire [15:0] dsp_out_2_3; +wire [15:0] dsp_out_2_4; +wire [15:0] dsp_out_2_5; +wire [15:0] dsp_out_2_6; +wire [15:0] dsp_out_2_7; +wire [15:0] dsp_out_3_0; +wire [15:0] dsp_out_3_1; +wire [15:0] dsp_out_3_2; +wire [15:0] dsp_out_3_3; +wire [15:0] dsp_out_3_4; +wire [15:0] dsp_out_3_5; +wire [15:0] dsp_out_3_6; +wire [15:0] dsp_out_3_7; +wire [15:0] dsp_out_4_0; +wire [15:0] dsp_out_4_1; +wire [15:0] dsp_out_4_2; +wire [15:0] dsp_out_4_3; +wire [15:0] dsp_out_4_4; +wire [15:0] dsp_out_4_5; +wire [15:0] dsp_out_4_6; +wire [15:0] dsp_out_4_7; +wire [15:0] dsp_out_5_0; +wire [15:0] dsp_out_5_1; +wire [15:0] dsp_out_5_2; +wire [15:0] dsp_out_5_3; +wire [15:0] dsp_out_5_4; +wire [15:0] dsp_out_5_5; +wire [15:0] dsp_out_5_6; +wire [15:0] dsp_out_5_7; +wire [15:0] dsp_out_6_0; +wire [15:0] dsp_out_6_1; +wire [15:0] dsp_out_6_2; +wire [15:0] dsp_out_6_3; +wire [15:0] dsp_out_6_4; +wire [15:0] dsp_out_6_5; +wire [15:0] dsp_out_6_6; +wire [15:0] dsp_out_6_7; +wire [15:0] dsp_out_6_8; +wire [15:0] dsp_out_6_9; +wire [15:0] dsp_out_6_10; +wire [15:0] dsp_out_6_11; +reg [15:0] feature_reg_0_0_0; +reg [15:0] feature_reg_0_0_1; +reg [15:0] feature_reg_0_1_0; +reg [15:0] feature_reg_0_1_1; +reg [15:0] feature_reg_0_2_0; +reg [15:0] feature_reg_0_2_1; +reg [15:0] feature_reg_0_3_0; +reg [15:0] feature_reg_0_3_1; +reg [15:0] feature_reg_0_4_0; +reg [15:0] feature_reg_0_4_1; +reg [15:0] feature_reg_0_5_0; +reg [15:0] feature_reg_0_5_1; +reg [15:0] feature_reg_1_0_0; +reg [15:0] feature_reg_1_0_1; +reg [15:0] feature_reg_1_1_0; +reg [15:0] feature_reg_1_1_1; +reg [15:0] feature_reg_1_2_0; +reg [15:0] feature_reg_1_2_1; +reg [15:0] feature_reg_1_3_0; +reg [15:0] feature_reg_1_3_1; +reg [15:0] feature_reg_1_4_0; +reg [15:0] feature_reg_1_4_1; +reg [15:0] feature_reg_1_5_0; +reg [15:0] feature_reg_1_5_1; +reg [15:0] feature_reg_2_0_0; +reg [15:0] feature_reg_2_0_1; +reg [15:0] feature_reg_2_1_0; +reg [15:0] feature_reg_2_1_1; +reg [15:0] feature_reg_2_2_0; +reg [15:0] feature_reg_2_2_1; +reg [15:0] feature_reg_2_3_0; +reg [15:0] feature_reg_2_3_1; +reg [15:0] feature_reg_2_4_0; +reg [15:0] feature_reg_2_4_1; +reg [15:0] feature_reg_2_5_0; +reg [15:0] feature_reg_2_5_1; +reg [15:0] feature_reg_3_0_0; +reg [15:0] feature_reg_3_0_1; +reg [15:0] feature_reg_3_1_0; +reg [15:0] feature_reg_3_1_1; +reg [15:0] feature_reg_3_2_0; +reg [15:0] feature_reg_3_2_1; +reg [15:0] feature_reg_3_3_0; +reg [15:0] feature_reg_3_3_1; +reg [15:0] feature_reg_3_4_0; +reg [15:0] feature_reg_3_4_1; +reg [15:0] feature_reg_3_5_0; +reg [15:0] feature_reg_3_5_1; +reg [15:0] feature_reg_4_0_0; +reg [15:0] feature_reg_4_0_1; +reg [15:0] feature_reg_4_1_0; +reg [15:0] feature_reg_4_1_1; +reg [15:0] feature_reg_4_2_0; +reg [15:0] feature_reg_4_2_1; +reg [15:0] feature_reg_4_3_0; +reg [15:0] feature_reg_4_3_1; +reg [15:0] feature_reg_4_4_0; +reg [15:0] feature_reg_4_4_1; +reg [15:0] feature_reg_4_5_0; +reg [15:0] feature_reg_4_5_1; +reg [15:0] feature_reg_5_0_0; +reg [15:0] feature_reg_5_0_1; +reg [15:0] feature_reg_5_1_0; +reg [15:0] feature_reg_5_1_1; +reg [15:0] feature_reg_5_2_0; +reg [15:0] feature_reg_5_2_1; +reg [15:0] feature_reg_5_3_0; +reg [15:0] feature_reg_5_3_1; +reg [15:0] feature_reg_5_4_0; +reg [15:0] feature_reg_5_4_1; +reg [15:0] feature_reg_5_5_0; +reg [15:0] feature_reg_5_5_1; + +always @ (posedge clk) begin + calculate_1 <= calculate; + calculate_2 <= calculate_1; + calculate_3 <= calculate_2; + //Valid pipeline + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + valid_12 <= valid_11; + if (i_valid) begin + input_buffer_count <= 0; + calculate <= 0; + end else begin + //Input buffering logic + if (input_buffer_count == 5) begin + calculate <= 1; + input_buffer_count <= 0; + end else begin + calculate <= 0; + input_buffer_count <= input_buffer_count + 1'b1; + end + input_buffer_5_0 <= i_result_0_7; + input_buffer_5_1 <= i_result_1_7; + input_buffer_5_2 <= i_result_2_7; + input_buffer_5_3 <= i_result_3_7; + input_buffer_5_4 <= i_result_4_7; + input_buffer_5_5 <= i_result_5_7; + end + input_buffer_0_0 <= input_buffer_1_0; + input_buffer_0_1 <= input_buffer_1_1; + input_buffer_0_2 <= input_buffer_1_2; + input_buffer_0_3 <= input_buffer_1_3; + input_buffer_0_4 <= input_buffer_1_4; + input_buffer_0_5 <= input_buffer_1_5; + input_buffer_1_0 <= input_buffer_2_0; + input_buffer_1_1 <= input_buffer_2_1; + input_buffer_1_2 <= input_buffer_2_2; + input_buffer_1_3 <= input_buffer_2_3; + input_buffer_1_4 <= input_buffer_2_4; + input_buffer_1_5 <= input_buffer_2_5; + input_buffer_2_0 <= input_buffer_3_0; + input_buffer_2_1 <= input_buffer_3_1; + input_buffer_2_2 <= input_buffer_3_2; + input_buffer_2_3 <= input_buffer_3_3; + input_buffer_2_4 <= input_buffer_3_4; + input_buffer_2_5 <= input_buffer_3_5; + input_buffer_3_0 <= input_buffer_4_0; + input_buffer_3_1 <= input_buffer_4_1; + input_buffer_3_2 <= input_buffer_4_2; + input_buffer_3_3 <= input_buffer_4_3; + input_buffer_3_4 <= input_buffer_4_4; + input_buffer_3_5 <= input_buffer_4_5; + input_buffer_4_0 <= input_buffer_5_0; + input_buffer_4_1 <= input_buffer_5_1; + input_buffer_4_2 <= input_buffer_5_2; + input_buffer_4_3 <= input_buffer_5_3; + input_buffer_4_4 <= input_buffer_5_4; + input_buffer_4_5 <= input_buffer_5_5; + //Pipelining to synchronize DSPs and non-DSPs + feature_reg_0_0_0 <= input_buffer_0_0; + feature_reg_0_1_0 <= input_buffer_0_1; + feature_reg_0_2_0 <= input_buffer_0_2; + feature_reg_0_3_0 <= input_buffer_0_3; + feature_reg_0_4_0 <= input_buffer_0_4; + feature_reg_0_5_0 <= input_buffer_0_5; + feature_reg_1_0_0 <= input_buffer_1_0; + feature_reg_1_1_0 <= input_buffer_1_1; + feature_reg_1_2_0 <= input_buffer_1_2; + feature_reg_1_3_0 <= input_buffer_1_3; + feature_reg_1_4_0 <= input_buffer_1_4; + feature_reg_1_5_0 <= input_buffer_1_5; + feature_reg_2_0_0 <= input_buffer_2_0; + feature_reg_2_1_0 <= input_buffer_2_1; + feature_reg_2_2_0 <= input_buffer_2_2; + feature_reg_2_3_0 <= input_buffer_2_3; + feature_reg_2_4_0 <= input_buffer_2_4; + feature_reg_2_5_0 <= input_buffer_2_5; + feature_reg_3_0_0 <= input_buffer_3_0; + feature_reg_3_1_0 <= input_buffer_3_1; + feature_reg_3_2_0 <= input_buffer_3_2; + feature_reg_3_3_0 <= input_buffer_3_3; + feature_reg_3_4_0 <= input_buffer_3_4; + feature_reg_3_5_0 <= input_buffer_3_5; + feature_reg_4_0_0 <= input_buffer_4_0; + feature_reg_4_1_0 <= input_buffer_4_1; + feature_reg_4_2_0 <= input_buffer_4_2; + feature_reg_4_3_0 <= input_buffer_4_3; + feature_reg_4_4_0 <= input_buffer_4_4; + feature_reg_4_5_0 <= input_buffer_4_5; + feature_reg_5_0_0 <= input_buffer_5_0; + feature_reg_5_1_0 <= input_buffer_5_1; + feature_reg_5_2_0 <= input_buffer_5_2; + feature_reg_5_3_0 <= input_buffer_5_3; + feature_reg_5_4_0 <= input_buffer_5_4; + feature_reg_5_5_0 <= input_buffer_5_5; + feature_reg_0_0_1 <= feature_reg_0_0_0; + feature_reg_0_1_1 <= feature_reg_0_1_0; + feature_reg_0_2_1 <= feature_reg_0_2_0; + feature_reg_0_3_1 <= feature_reg_0_3_0; + feature_reg_0_4_1 <= feature_reg_0_4_0; + feature_reg_0_5_1 <= feature_reg_0_5_0; + feature_reg_1_0_1 <= feature_reg_1_0_0; + feature_reg_1_1_1 <= feature_reg_1_1_0; + feature_reg_1_2_1 <= feature_reg_1_2_0; + feature_reg_1_3_1 <= feature_reg_1_3_0; + feature_reg_1_4_1 <= feature_reg_1_4_0; + feature_reg_1_5_1 <= feature_reg_1_5_0; + feature_reg_2_0_1 <= feature_reg_2_0_0; + feature_reg_2_1_1 <= feature_reg_2_1_0; + feature_reg_2_2_1 <= feature_reg_2_2_0; + feature_reg_2_3_1 <= feature_reg_2_3_0; + feature_reg_2_4_1 <= feature_reg_2_4_0; + feature_reg_2_5_1 <= feature_reg_2_5_0; + feature_reg_3_0_1 <= feature_reg_3_0_0; + feature_reg_3_1_1 <= feature_reg_3_1_0; + feature_reg_3_2_1 <= feature_reg_3_2_0; + feature_reg_3_3_1 <= feature_reg_3_3_0; + feature_reg_3_4_1 <= feature_reg_3_4_0; + feature_reg_3_5_1 <= feature_reg_3_5_0; + feature_reg_4_0_1 <= feature_reg_4_0_0; + feature_reg_4_1_1 <= feature_reg_4_1_0; + feature_reg_4_2_1 <= feature_reg_4_2_0; + feature_reg_4_3_1 <= feature_reg_4_3_0; + feature_reg_4_4_1 <= feature_reg_4_4_0; + feature_reg_4_5_1 <= feature_reg_4_5_0; + feature_reg_5_0_1 <= feature_reg_5_0_0; + feature_reg_5_1_1 <= feature_reg_5_1_0; + feature_reg_5_2_1 <= feature_reg_5_2_0; + feature_reg_5_3_1 <= feature_reg_5_3_0; + feature_reg_5_4_1 <= feature_reg_5_4_0; + feature_reg_5_5_1 <= feature_reg_5_5_0; + //Output Serializing logic + if (calculate_3) begin + output_buffer_0_0 <= rslt_buffer_0_0; + output_buffer_1_0 <= rslt_buffer_0_1; + output_buffer_2_0 <= rslt_buffer_0_2; + output_buffer_3_0 <= rslt_buffer_0_3; + output_buffer_4_0 <= rslt_buffer_0_4; + output_buffer_5_0 <= rslt_buffer_0_5; + output_buffer_0_1 <= rslt_buffer_1_0; + output_buffer_1_1 <= rslt_buffer_1_1; + output_buffer_2_1 <= rslt_buffer_1_2; + output_buffer_3_1 <= rslt_buffer_1_3; + output_buffer_4_1 <= rslt_buffer_1_4; + output_buffer_5_1 <= rslt_buffer_1_5; + output_buffer_0_2 <= rslt_buffer_2_0; + output_buffer_1_2 <= rslt_buffer_2_1; + output_buffer_2_2 <= rslt_buffer_2_2; + output_buffer_3_2 <= rslt_buffer_2_3; + output_buffer_4_2 <= rslt_buffer_2_4; + output_buffer_5_2 <= rslt_buffer_2_5; + output_buffer_0_3 <= rslt_buffer_3_0; + output_buffer_1_3 <= rslt_buffer_3_1; + output_buffer_2_3 <= rslt_buffer_3_2; + output_buffer_3_3 <= rslt_buffer_3_3; + output_buffer_4_3 <= rslt_buffer_3_4; + output_buffer_5_3 <= rslt_buffer_3_5; + output_buffer_0_4 <= rslt_buffer_4_0; + output_buffer_1_4 <= rslt_buffer_4_1; + output_buffer_2_4 <= rslt_buffer_4_2; + output_buffer_3_4 <= rslt_buffer_4_3; + output_buffer_4_4 <= rslt_buffer_4_4; + output_buffer_5_4 <= rslt_buffer_4_5; + output_buffer_0_5 <= rslt_buffer_5_0; + output_buffer_1_5 <= rslt_buffer_5_1; + output_buffer_2_5 <= rslt_buffer_5_2; + output_buffer_3_5 <= rslt_buffer_5_3; + output_buffer_4_5 <= rslt_buffer_5_4; + output_buffer_5_5 <= rslt_buffer_5_5; + end else begin + output_buffer_0_0 <= output_buffer_0_1; + output_buffer_0_1 <= output_buffer_0_2; + output_buffer_0_2 <= output_buffer_0_3; + output_buffer_0_3 <= output_buffer_0_4; + output_buffer_0_4 <= output_buffer_0_5; + output_buffer_1_0 <= output_buffer_1_1; + output_buffer_1_1 <= output_buffer_1_2; + output_buffer_1_2 <= output_buffer_1_3; + output_buffer_1_3 <= output_buffer_1_4; + output_buffer_1_4 <= output_buffer_1_5; + output_buffer_2_0 <= output_buffer_2_1; + output_buffer_2_1 <= output_buffer_2_2; + output_buffer_2_2 <= output_buffer_2_3; + output_buffer_2_3 <= output_buffer_2_4; + output_buffer_2_4 <= output_buffer_2_5; + output_buffer_3_0 <= output_buffer_3_1; + output_buffer_3_1 <= output_buffer_3_2; + output_buffer_3_2 <= output_buffer_3_3; + output_buffer_3_3 <= output_buffer_3_4; + output_buffer_3_4 <= output_buffer_3_5; + output_buffer_4_0 <= output_buffer_4_1; + output_buffer_4_1 <= output_buffer_4_2; + output_buffer_4_2 <= output_buffer_4_3; + output_buffer_4_3 <= output_buffer_4_4; + output_buffer_4_4 <= output_buffer_4_5; + output_buffer_5_0 <= output_buffer_5_1; + output_buffer_5_1 <= output_buffer_5_2; + output_buffer_5_2 <= output_buffer_5_3; + output_buffer_5_3 <= output_buffer_5_4; + output_buffer_5_4 <= output_buffer_5_5; + end +end + +////// FIRST COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD00 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_2), + .by(input_buffer_2_0), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_1_0), + .resultb(dsp_out_1_1) +); + +winograd_dsp_16 winograd_dsp_16_WD10 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_2_4), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_1_2), + .resultb(dsp_out_1_3) +); + +winograd_dsp_16 winograd_dsp_16_WD20 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_2), + .by(input_buffer_1_0), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_1_4), + .resultb(dsp_out_1_5) +); + +winograd_dsp_16 winograd_dsp_16_WD30 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_1_6), + .resultb(dsp_out_1_7) +); + +winograd_dsp_16 winograd_dsp_16_WD40 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_0), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_1_8), + .resultb(dsp_out_1_9) +); + +winograd_dsp_16 winograd_dsp_16_WD50 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_4), + .by(input_buffer_5_2), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_1_10), + .resultb(dsp_out_1_11) +); + +////// SECOND COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD01 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_0), + .resultb(dsp_out_2_1) +); + +winograd_dsp_16 winograd_dsp_16_WD11 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_2), + .resultb(dsp_out_2_3) +); + +winograd_dsp_16 winograd_dsp_16_WD21 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_4), + .resultb(dsp_out_2_5) +); + +winograd_dsp_16 winograd_dsp_16_WD31 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_6), + .resultb(dsp_out_2_7) +); + +////// THIRD COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD02 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_0), + .resultb(dsp_out_3_1) +); + +winograd_dsp_16 winograd_dsp_16_WD12 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_2), + .resultb(dsp_out_3_3) +); + +winograd_dsp_16 winograd_dsp_16_WD22 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_4), + .resultb(dsp_out_3_5) +); + +winograd_dsp_16 winograd_dsp_16_WD32 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_6), + .resultb(dsp_out_3_7) +); + +////// FOURTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD03 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_0), + .resultb(dsp_out_4_1) +); + +winograd_dsp_16 winograd_dsp_16_WD13 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_2), + .resultb(dsp_out_4_3) +); + +winograd_dsp_16 winograd_dsp_16_WD23 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_4), + .resultb(dsp_out_4_5) +); + +winograd_dsp_16 winograd_dsp_16_WD33 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_6), + .resultb(dsp_out_4_7) +); + +////// FIFTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD04 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_0), + .resultb(dsp_out_5_1) +); + +winograd_dsp_16 winograd_dsp_16_WD14 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_2), + .resultb(dsp_out_5_3) +); + +winograd_dsp_16 winograd_dsp_16_WD24 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_4), + .resultb(dsp_out_5_5) +); + +winograd_dsp_16 winograd_dsp_16_WD34 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_6), + .resultb(dsp_out_5_7) +); + +////// SIXTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD05 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_3), + .by(input_buffer_2_1), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_6_0), + .resultb(dsp_out_6_1) +); + +winograd_dsp_16 winograd_dsp_16_WD15 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_5), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_6_2), + .resultb(dsp_out_6_3) +); + +winograd_dsp_16 winograd_dsp_16_WD25 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_3), + .by(input_buffer_1_3), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_6_4), + .resultb(dsp_out_6_5) +); + +winograd_dsp_16 winograd_dsp_16_WD35 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_3_3), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_6_6), + .resultb(dsp_out_6_7) +); + +winograd_dsp_16 winograd_dsp_16_WD45 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_3), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_6_8), + .resultb(dsp_out_6_9) +); + +winograd_dsp_16 winograd_dsp_16_WD55 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_5), + .by(input_buffer_5_3), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_6_10), + .resultb(dsp_out_6_11) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA00 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_0_1[11:0], 4'b0000}), + .data1x(dsp_out_1_0), + .data2x({feature_reg_0_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_1), + .data4x(dsp_out_1_2), + .data5x(dsp_out_1_3), + .data6x({feature_reg_4_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_4), + .data8x(feature_reg_4_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_0) +); + +wire [15:0] f1, f2, f3, f4; +assign f1 = -{feature_reg_1_0_1[11:0], 4'b0000}; +assign f2 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f3 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f4 = -{feature_reg_2_4_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA10 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_1_5), + .data1x(f1), + .data2x(f2), + .data3x(f3), + .data4x(dsp_out_1_6), + .data5x(f4), + .data6x({feature_reg_3_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_7), + .data8x(feature_reg_3_4_1), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_0) +); + +wire [15:0] f5, f6, f7, f8, f9, f10; +assign f5 = -dsp_out_1_5; +assign f6 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f7 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f8 = -{feature_reg_3_0_1[13:0], 2'b00}; +assign f9 = -dsp_out_1_7; +assign f10 = -feature_reg_3_4_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA20 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f5), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(f6), + .data4x(dsp_out_1_6), + .data5x(f7), + .data6x(f8), + .data7x(f9), + .data8x(f10), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_0) +); + +wire [15:0] f11, f12, f13, f14, f15, f16, f17; +assign f11 = -{feature_reg_1_0_1[12:0], 3'b000}; +assign f12 = -{feature_reg_1_4_1[14:0], 1'b0}; +assign f13 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f14 = -feature_reg_2_4_1; +assign f15 = dsp_out_1_5 >>> 1; +assign f16 = dsp_out_1_6 >>> 2; +assign f17 = dsp_out_1_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA30 ( + .clock(clk), + .clken(calculate_2), + .data0x(f15), + .data1x(f11), + .data2x(f12), + .data3x(f13), + .data4x(f16), + .data5x(f14), + .data6x({feature_reg_3_0_1[12:0], 3'b000}), + .data7x(f17), + .data8x({feature_reg_3_4_1[14:0], 1'b0}), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_0) +); + +wire [15:0] f18, f19, f20, f21, f22, f23, f23b; +assign f18 = -(dsp_out_1_5 >>> 1); +assign f19 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f20 = -feature_reg_2_4_1; +assign f21 = -{feature_reg_3_0_1[12:0], 3'b000}; +assign f22 = -(dsp_out_1_7 <<< 1); +assign f23 = -{feature_reg_3_4_1[14:0], 1'b0}; +assign f23b = dsp_out_1_6 >>> 2; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA40 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[12:0], 3'b000}), + .data1x(f18), + .data2x({feature_reg_1_4_1[14:0], 1'b0}), + .data3x(f19), + .data4x(f23b), + .data5x(f20), + .data6x(f21), + .data7x(f22), + .data8x(f23), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_0) +); + +wire [15:0] f24; +assign f24 = -dsp_out_1_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA50 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f24), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_8), + .data4x(dsp_out_1_9), + .data5x(dsp_out_1_10), + .data6x({feature_reg_5_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_11), + .data8x(feature_reg_5_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_0) +); + +wire [15:0] f25, f26, f27, f28; +assign f25 = -{feature_reg_0_2_1[11:0], 4'b0000}; +assign f26 = -{feature_reg_0_1_1[11:0], 4'b0000}; +assign f27 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f28 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA01 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[13:0], 2'b00}), + .data1x(f25), + .data2x(f26), + .data3x({feature_reg_0_4_1[13:0], 2'b00}), + .data4x(dsp_out_2_0), + .data5x(dsp_out_2_1), + .data6x(dsp_out_2_2), + .data7x(dsp_out_2_3), + .data8x(f27), + .data9x(f28), + .data10x(feature_reg_4_3_1), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_1) +); + +wire [15:0] f29, f30, f31, f32, f33, f34, f35, f36; +assign f29 = -{feature_reg_1_3_1[13:0], 2'b00}; +assign f30 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f31 = -{feature_reg_2_3_1[13:0], 2'b00}; +assign f32 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f33 = -{feature_reg_3_1_1[13:0], 2'b00}; +assign f34 = -{feature_reg_3_2_1[13:0], 2'b00}; +assign f35 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f36 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA11 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0], 4'b0000}), + .data1x({feature_reg_1_2_1[11:0], 4'b0000}), + .data2x(f29), + .data3x(f30), + .data4x({feature_reg_2_1_1[11:0], 4'b0000}), + .data5x({feature_reg_2_2_1[11:0], 4'b0000}), + .data6x(f31), + .data7x(f32), + .data8x(f33), + .data9x(f34), + .data10x(feature_reg_3_3_1), + .data11x(feature_reg_3_4_1), + .data12x(f35), + .data13x(f36), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_1) +); + +wire [15:0] f37, f38, f39, f40, f41, f42, f43, f44; +assign f37 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f38 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f39 = -{feature_reg_2_3_1[13:0],2'b00}; +assign f40 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f41 = -feature_reg_3_3_1; +assign f42 = -feature_reg_3_4_1; +assign f43 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f44 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA21 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f37), + .data2x(f38), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[11:0],4'b0000}), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x(f39), + .data7x(f40), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(f41), + .data11x(f42), + .data12x(f43), + .data13x(f44), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_1) +); + +wire [15:0] f45, f46, f47, f48, f49, f50, f51, f52; +assign f45 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f46 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f47 = -feature_reg_2_3_1; +assign f48 = -feature_reg_2_4_1; +assign f49 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f50 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f51 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f52 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA31 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[12:0],3'b000}), + .data2x(f45), + .data3x(f46), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f47), + .data7x(f48), + .data8x(f49), + .data9x(f50), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f51), + .data13x(f52), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_1) +); + +wire [15:0] f53, f54, f55, f56, f57, f58, f59, f60; +assign f53 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f54 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f55 = -feature_reg_2_3_1; +assign f56 = -feature_reg_2_4_1; +assign f57 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f58 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f59 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f60 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA41 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[14:0],1'b0}), + .data1x(f53), + .data2x(f54), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f55), + .data7x(f56), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x(f57), + .data11x(f58), + .data12x(f59), + .data13x(f60), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_1) +); + +wire [15:0] f61, f62, f63, f64; +assign f61 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f62 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f63 = -{feature_reg_5_1_1[13:0],2'b00}; +assign f64 = -{feature_reg_5_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA51 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f61), + .data2x(f62), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_2_4), + .data5x(dsp_out_2_5), + .data6x(dsp_out_2_6), + .data7x(dsp_out_2_7), + .data8x(f63), + .data9x(f64), + .data10x(feature_reg_5_3_1), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_1) +); + +wire [15:0] f65, f66, f67, f68; +assign f65 = -{feature_reg_0_2_1[11:0],4'b0000}; +assign f66 = -{feature_reg_0_3_1[13:0],2'b00}; +assign f67 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f68 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA02 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(f65), + .data2x(f66), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_3_0), + .data5x(dsp_out_3_1), + .data6x(dsp_out_3_2), + .data7x(dsp_out_3_3), + .data8x({feature_reg_4_1_1[13:0],2'b00}), + .data9x(f67), + .data10x(f68), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_2) +); + +wire [15:0] f69, f70, f71, f72, f73, f74, f75, f76; +assign f69 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f70 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f71 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f72 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f73 = -{feature_reg_3_2_1[13:0],2'b00}; +assign f74 = -feature_reg_3_3_1; +assign f75 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f76 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA12 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[11:0],4'b0000}), + .data1x(f69), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f70), + .data4x(f71), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f72), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f73), + .data10x(f74), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f75), + .data14x(f76), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_2) +); + +wire [15:0] f77, f78, f79, f80, f81, f82, f83, f84; +assign f77 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f78 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f79 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f80 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f81 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f82 = -feature_reg_3_4_1; +assign f83 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f84 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA22 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f77), + .data2x(f78), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f79), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f80), + .data8x(f81), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(feature_reg_3_3_1), + .data11x(f82), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f83), + .data14x(f84), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_2) +); + +wire [15:0] f85, f86, f87, f88, f89, f90, f91, f92; +assign f85 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f86 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f87 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f88 = -feature_reg_2_4_1; +assign f89 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f90 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f91 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f92 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA32 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[12:0],3'b000}), + .data1x(f85), + .data2x({feature_reg_1_3_1[14:0],1'b0}), + .data3x(f86), + .data4x(f87), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f88), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x(f89), + .data10x(f90), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f91), + .data14x(f92), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_2) +); + +wire [15:0] f93, f94, f95, f96, f97, f98, f99, f100; +assign f93 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f94 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f95 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f96 = -feature_reg_2_4_1; +assign f97 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f98 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f99 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f100 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA42 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f93), + .data2x(f94), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f95), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f96), + .data8x(f97), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f98), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f99), + .data14x(f100), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_2) +); + +wire [15:0] f101, f102, f103, f104; +assign f101 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f102 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f103 = -{feature_reg_5_2_1[13:0],2'b00}; +assign f104 = -feature_reg_5_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA52 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f101), + .data2x(f102), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_3_4), + .data5x(dsp_out_3_5), + .data6x(dsp_out_3_6), + .data7x(dsp_out_3_7), + .data8x({feature_reg_5_1_1[13:0],2'b00}), + .data9x(f103), + .data10x(f104), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_2) +); + +wire [15:0] f105, f106, f107, f108; +assign f105 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f106 = -{feature_reg_0_1_1[12:0],3'b000}; +assign f107 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f108 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA03 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[12:0],3'b000}), + .data1x(f105), + .data2x(f106), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_4_0), + .data5x(dsp_out_4_1), + .data6x(dsp_out_4_2), + .data7x(dsp_out_4_3), + .data8x(f107), + .data9x(f108), + .data10x({feature_reg_4_3_1[14:0],1'b0}), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_3) +); + +wire [15:0] f109, f110, f111, f112, f113, f114, f115, f116; +assign f109 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f110 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f111 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f112 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f113 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f114 = -feature_reg_3_2_1; +assign f115 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f116 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA13 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[13:0],2'b00}), + .data2x(f109), + .data3x(f110), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f111), + .data7x(f112), + .data8x(f113), + .data9x(f114), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(feature_reg_3_4_1), + .data12x(f115), + .data13x(f116), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_3) +); + +wire [15:0] f117, f118, f119, f120, f121, f122, f123, f124; +assign f117 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f118 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f119 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f120 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f121 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f122 = -feature_reg_3_4_1; +assign f123 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f124 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA23 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f117), + .data2x(f118), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f119), + .data7x(f120), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(feature_reg_3_2_1), + .data10x(f121), + .data11x(f122), + .data12x(f123), + .data13x(f124), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_3) +); + +wire [15:0] f125, f126, f127, f128, f129, f130, f131, f132; +assign f125 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f126 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f127 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f128 = -feature_reg_2_4_1; +assign f129 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f130 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f131 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f132 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA33 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x({feature_reg_1_2_1[14:0],1'b0}), + .data2x(f125), + .data3x(f126), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f127), + .data7x(f128), + .data8x(f129), + .data9x(f130), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f131), + .data13x(f132), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_3) +); + +wire [15:0] f133, f134, f135, f136, f137, f138, f139, f140; +assign f133 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f134 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f135 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f136 = -feature_reg_2_4_1; +assign f137 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f138 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f139 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f140 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA43 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f133), + .data2x(f134), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f135), + .data7x(f136), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x(f137), + .data11x(f138), + .data12x(f139), + .data13x(f140), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_3) +); + +wire [15:0] f141, f142, f143, f144; +assign f141 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f142 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f143 = -{feature_reg_5_1_1[14:0],1'b0}; +assign f144 = -feature_reg_5_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA53 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f141), + .data2x(f142), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_4_4), + .data5x(dsp_out_4_5), + .data6x(dsp_out_4_6), + .data7x(dsp_out_4_7), + .data8x(f143), + .data9x(f144), + .data10x({feature_reg_5_3_1[14:0],1'b0}), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_3) +); + +wire [15:0] f145, f146, f147, f148; +assign f145 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f146 = -{feature_reg_0_3_1[12:0],3'b000}; +assign f147 = -feature_reg_4_2_1; +assign f148 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA04 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[12:0],3'b000}), + .data1x(f145), + .data2x(f146), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_5_0), + .data5x(dsp_out_5_1), + .data6x(dsp_out_5_2), + .data7x(dsp_out_5_3), + .data8x({feature_reg_4_1_1[14:0],1'b0}), + .data9x(f147), + .data10x(f148), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_4) +); + +wire [15:0] f149, f150, f151, f152, f153, f154, f155, f156; +assign f149 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f150 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f151 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f152 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f153 = -feature_reg_3_2_1; +assign f154 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f155 = -feature_reg_4_2_1; +assign f156 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA14 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[13:0],2'b00}), + .data1x(f149), + .data2x({feature_reg_1_3_1[12:0],3'b000}), + .data3x(f150), + .data4x(f151), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f152), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(f153), + .data10x(f154), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f155), + .data14x(f156), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_4) +); + +wire [15:0] f157, f158, f159, f160, f161, f162, f163, f164; +assign f157 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f158 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f159 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f160 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f161 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f162 = -feature_reg_3_4_1; +assign f163 = -feature_reg_4_2_1; +assign f164 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA24 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f157), + .data2x(f158), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f159), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f160), + .data8x(f161), + .data9x(feature_reg_3_2_1), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f162), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f163), + .data14x(f164), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_4) +); + +wire [15:0] f165, f166, f167, f168, f169, f170, f171, f172; +assign f165 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f166 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f167 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f168 = -feature_reg_2_4_1; +assign f169 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f170 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f171 = -feature_reg_4_2_1; +assign f172 = -{feature_reg_4_1_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA34 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[14:0],1'b0}), + .data1x(f165), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f166), + .data4x(f167), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f168), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f169), + .data10x(f170), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f171), + .data14x(f172), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_4) +); + +wire [15:0] f173, f174, f175, f176, f177, f178, f179, f180; +assign f173 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f174 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f175 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f176 = -feature_reg_2_4_1; +assign f177 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f178 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f179 = -feature_reg_4_2_1; +assign f180 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA44 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x(f173), + .data2x(f174), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f175), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f176), + .data8x(f177), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x(f178), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f179), + .data14x(f180), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_4) +); + +wire [15:0] f181, f182, f183, f184; +assign f181 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f182 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f183 = -feature_reg_5_2_1; +assign f184 = -{feature_reg_5_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA54 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f181), + .data2x(f182), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_5_4), + .data5x(dsp_out_5_5), + .data6x(dsp_out_5_6), + .data7x(dsp_out_5_7), + .data8x({feature_reg_5_1_1[14:0],1'b0}), + .data9x(f183), + .data10x(f184), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_4) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA05 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(dsp_out_6_0), + .data2x({feature_reg_0_5_1[13:0],2'b00}), + .data3x(dsp_out_6_1), + .data4x(dsp_out_6_2), + .data5x(dsp_out_6_3), + .data6x({feature_reg_4_1_1[13:0],2'b00}), + .data7x(dsp_out_6_4), + .data8x(feature_reg_4_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_5) +); + +wire [15:0] f185, f186, f187, f188; +assign f185 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f186 = -{feature_reg_1_5_1[13:0],2'b00}; +assign f187 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f188 = -{feature_reg_2_5_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA15 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_6_5), + .data1x(f185), + .data2x(f186), + .data3x(f187), + .data4x(dsp_out_6_6), + .data5x(f188), + .data6x({feature_reg_3_1_1[13:0],2'b00}), + .data7x(dsp_out_6_7), + .data8x(feature_reg_3_5_1), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_5) +); + +wire [15:0] f189, f190, f191, f192, f193, f194; +assign f189 = -dsp_out_6_5; +assign f190 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f191 = -{feature_reg_2_5_1[13:0],2'b00}; +assign f192 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f193 = -dsp_out_6_7; +assign f194 = -feature_reg_3_5_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA25 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f189), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(f190), + .data4x(dsp_out_6_6), + .data5x(f191), + .data6x(f192), + .data7x(f193), + .data8x(f194), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_5) +); + +wire [15:0] f195, f196, f197, f198, f199, f200, f201; +assign f195 = dsp_out_6_5 >>> 1; +assign f196 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f197 = -{feature_reg_1_5_1[14:0],1'b0}; +assign f198 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f199 = dsp_out_6_6 >>> 2; +assign f200 = -feature_reg_2_5_1; +assign f201 = dsp_out_6_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA35 ( + .clock(clk), + .clken(calculate_2), + .data0x(f195), + .data1x(f196), + .data2x(f197), + .data3x(f198), + .data4x(f199), + .data5x(f200), + .data6x({feature_reg_3_1_1[12:0],3'b000}), + .data7x(f201), + .data8x({feature_reg_3_5_1[14:0],1'b0}), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_5) +); + +wire [15:0] f202, f203, f204, f205, f206, f207, f208; +assign f202 = -(dsp_out_6_5 >>> 1); +assign f203 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f204 = dsp_out_6_6 >>> 2; +assign f205 = -feature_reg_2_5_1; +assign f206 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f207 = -(dsp_out_6_7 <<< 1); +assign f208 = -{feature_reg_3_5_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA45 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f202), + .data2x({feature_reg_1_5_1[14:0],1'b0}), + .data3x(f203), + .data4x(f204), + .data5x(f205), + .data6x(f206), + .data7x(f207), + .data8x(f208), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_5) +); + +wire [15:0] f209; +assign f209 = -dsp_out_6_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA55 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f209), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(dsp_out_6_8), + .data4x(dsp_out_6_9), + .data5x(dsp_out_6_10), + .data6x({feature_reg_5_1_1[13:0],2'b00}), + .data7x(dsp_out_6_11), + .data8x(feature_reg_5_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_5) +); + +assign o_feature_0 = output_buffer_0_0[15:0]; +assign o_feature_1 = output_buffer_1_0[15:0]; +assign o_feature_2 = output_buffer_2_0[15:0]; +assign o_feature_3 = output_buffer_3_0[15:0]; +assign o_feature_4 = output_buffer_4_0[15:0]; +assign o_feature_5 = output_buffer_5_0[15:0]; +assign o_valid = valid_9; + +endmodule + +module winograd_transform_6 ( + input clk, + input i_valid, + input [15:0] i_result_0_0, + input [15:0] i_result_0_1, + input [15:0] i_result_0_2, + input [15:0] i_result_0_3, + input [15:0] i_result_0_4, + input [15:0] i_result_0_5, + input [15:0] i_result_0_6, + input [15:0] i_result_0_7, + input [15:0] i_result_1_0, + input [15:0] i_result_1_1, + input [15:0] i_result_1_2, + input [15:0] i_result_1_3, + input [15:0] i_result_1_4, + input [15:0] i_result_1_5, + input [15:0] i_result_1_6, + input [15:0] i_result_1_7, + input [15:0] i_result_2_0, + input [15:0] i_result_2_1, + input [15:0] i_result_2_2, + input [15:0] i_result_2_3, + input [15:0] i_result_2_4, + input [15:0] i_result_2_5, + input [15:0] i_result_2_6, + input [15:0] i_result_2_7, + input [15:0] i_result_3_0, + input [15:0] i_result_3_1, + input [15:0] i_result_3_2, + input [15:0] i_result_3_3, + input [15:0] i_result_3_4, + input [15:0] i_result_3_5, + input [15:0] i_result_3_6, + input [15:0] i_result_3_7, + input [15:0] i_result_4_0, + input [15:0] i_result_4_1, + input [15:0] i_result_4_2, + input [15:0] i_result_4_3, + input [15:0] i_result_4_4, + input [15:0] i_result_4_5, + input [15:0] i_result_4_6, + input [15:0] i_result_4_7, + input [15:0] i_result_5_0, + input [15:0] i_result_5_1, + input [15:0] i_result_5_2, + input [15:0] i_result_5_3, + input [15:0] i_result_5_4, + input [15:0] i_result_5_5, + input [15:0] i_result_5_6, + input [15:0] i_result_5_7, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output [15:0] o_feature_2, + output [15:0] o_feature_3, + output [15:0] o_feature_4, + output [15:0] o_feature_5, + output o_valid +); + +reg [15:0] input_buffer_0_0; +reg [19:0] output_buffer_0_0; +wire [19:0] rslt_buffer_0_0; +reg [15:0] input_buffer_0_1; +reg [19:0] output_buffer_0_1; +wire [19:0] rslt_buffer_0_1; +reg [15:0] input_buffer_0_2; +reg [19:0] output_buffer_0_2; +wire [19:0] rslt_buffer_0_2; +reg [15:0] input_buffer_0_3; +reg [19:0] output_buffer_0_3; +wire [19:0] rslt_buffer_0_3; +reg [15:0] input_buffer_0_4; +reg [19:0] output_buffer_0_4; +wire [19:0] rslt_buffer_0_4; +reg [15:0] input_buffer_0_5; +reg [19:0] output_buffer_0_5; +wire [19:0] rslt_buffer_0_5; +reg [15:0] input_buffer_1_0; +reg [19:0] output_buffer_1_0; +wire [19:0] rslt_buffer_1_0; +reg [15:0] input_buffer_1_1; +reg [19:0] output_buffer_1_1; +wire [19:0] rslt_buffer_1_1; +reg [15:0] input_buffer_1_2; +reg [19:0] output_buffer_1_2; +wire [19:0] rslt_buffer_1_2; +reg [15:0] input_buffer_1_3; +reg [19:0] output_buffer_1_3; +wire [19:0] rslt_buffer_1_3; +reg [15:0] input_buffer_1_4; +reg [19:0] output_buffer_1_4; +wire [19:0] rslt_buffer_1_4; +reg [15:0] input_buffer_1_5; +reg [19:0] output_buffer_1_5; +wire [19:0] rslt_buffer_1_5; +reg [15:0] input_buffer_2_0; +reg [19:0] output_buffer_2_0; +wire [19:0] rslt_buffer_2_0; +reg [15:0] input_buffer_2_1; +reg [19:0] output_buffer_2_1; +wire [19:0] rslt_buffer_2_1; +reg [15:0] input_buffer_2_2; +reg [19:0] output_buffer_2_2; +wire [19:0] rslt_buffer_2_2; +reg [15:0] input_buffer_2_3; +reg [19:0] output_buffer_2_3; +wire [19:0] rslt_buffer_2_3; +reg [15:0] input_buffer_2_4; +reg [19:0] output_buffer_2_4; +wire [19:0] rslt_buffer_2_4; +reg [15:0] input_buffer_2_5; +reg [19:0] output_buffer_2_5; +wire [19:0] rslt_buffer_2_5; +reg [15:0] input_buffer_3_0; +reg [19:0] output_buffer_3_0; +wire [19:0] rslt_buffer_3_0; +reg [15:0] input_buffer_3_1; +reg [19:0] output_buffer_3_1; +wire [19:0] rslt_buffer_3_1; +reg [15:0] input_buffer_3_2; +reg [19:0] output_buffer_3_2; +wire [19:0] rslt_buffer_3_2; +reg [15:0] input_buffer_3_3; +reg [19:0] output_buffer_3_3; +wire [19:0] rslt_buffer_3_3; +reg [15:0] input_buffer_3_4; +reg [19:0] output_buffer_3_4; +wire [19:0] rslt_buffer_3_4; +reg [15:0] input_buffer_3_5; +reg [19:0] output_buffer_3_5; +wire [19:0] rslt_buffer_3_5; +reg [15:0] input_buffer_4_0; +reg [19:0] output_buffer_4_0; +wire [19:0] rslt_buffer_4_0; +reg [15:0] input_buffer_4_1; +reg [19:0] output_buffer_4_1; +wire [19:0] rslt_buffer_4_1; +reg [15:0] input_buffer_4_2; +reg [19:0] output_buffer_4_2; +wire [19:0] rslt_buffer_4_2; +reg [15:0] input_buffer_4_3; +reg [19:0] output_buffer_4_3; +wire [19:0] rslt_buffer_4_3; +reg [15:0] input_buffer_4_4; +reg [19:0] output_buffer_4_4; +wire [19:0] rslt_buffer_4_4; +reg [15:0] input_buffer_4_5; +reg [19:0] output_buffer_4_5; +wire [19:0] rslt_buffer_4_5; +reg [15:0] input_buffer_5_0; +reg [19:0] output_buffer_5_0; +wire [19:0] rslt_buffer_5_0; +reg [15:0] input_buffer_5_1; +reg [19:0] output_buffer_5_1; +wire [19:0] rslt_buffer_5_1; +reg [15:0] input_buffer_5_2; +reg [19:0] output_buffer_5_2; +wire [19:0] rslt_buffer_5_2; +reg [15:0] input_buffer_5_3; +reg [19:0] output_buffer_5_3; +wire [19:0] rslt_buffer_5_3; +reg [15:0] input_buffer_5_4; +reg [19:0] output_buffer_5_4; +wire [19:0] rslt_buffer_5_4; +reg [15:0] input_buffer_5_5; +reg [19:0] output_buffer_5_5; +wire [19:0] rslt_buffer_5_5; +reg calculate, calculate_1, calculate_2, calculate_3; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg valid_12; +reg [2:0] input_buffer_count; +wire [15:0] dsp_out_1_0; +wire [15:0] dsp_out_1_1; +wire [15:0] dsp_out_1_2; +wire [15:0] dsp_out_1_3; +wire [15:0] dsp_out_1_4; +wire [15:0] dsp_out_1_5; +wire [15:0] dsp_out_1_6; +wire [15:0] dsp_out_1_7; +wire [15:0] dsp_out_1_8; +wire [15:0] dsp_out_1_9; +wire [15:0] dsp_out_1_10; +wire [15:0] dsp_out_1_11; +wire [15:0] dsp_out_2_0; +wire [15:0] dsp_out_2_1; +wire [15:0] dsp_out_2_2; +wire [15:0] dsp_out_2_3; +wire [15:0] dsp_out_2_4; +wire [15:0] dsp_out_2_5; +wire [15:0] dsp_out_2_6; +wire [15:0] dsp_out_2_7; +wire [15:0] dsp_out_3_0; +wire [15:0] dsp_out_3_1; +wire [15:0] dsp_out_3_2; +wire [15:0] dsp_out_3_3; +wire [15:0] dsp_out_3_4; +wire [15:0] dsp_out_3_5; +wire [15:0] dsp_out_3_6; +wire [15:0] dsp_out_3_7; +wire [15:0] dsp_out_4_0; +wire [15:0] dsp_out_4_1; +wire [15:0] dsp_out_4_2; +wire [15:0] dsp_out_4_3; +wire [15:0] dsp_out_4_4; +wire [15:0] dsp_out_4_5; +wire [15:0] dsp_out_4_6; +wire [15:0] dsp_out_4_7; +wire [15:0] dsp_out_5_0; +wire [15:0] dsp_out_5_1; +wire [15:0] dsp_out_5_2; +wire [15:0] dsp_out_5_3; +wire [15:0] dsp_out_5_4; +wire [15:0] dsp_out_5_5; +wire [15:0] dsp_out_5_6; +wire [15:0] dsp_out_5_7; +wire [15:0] dsp_out_6_0; +wire [15:0] dsp_out_6_1; +wire [15:0] dsp_out_6_2; +wire [15:0] dsp_out_6_3; +wire [15:0] dsp_out_6_4; +wire [15:0] dsp_out_6_5; +wire [15:0] dsp_out_6_6; +wire [15:0] dsp_out_6_7; +wire [15:0] dsp_out_6_8; +wire [15:0] dsp_out_6_9; +wire [15:0] dsp_out_6_10; +wire [15:0] dsp_out_6_11; +reg [15:0] feature_reg_0_0_0; +reg [15:0] feature_reg_0_0_1; +reg [15:0] feature_reg_0_1_0; +reg [15:0] feature_reg_0_1_1; +reg [15:0] feature_reg_0_2_0; +reg [15:0] feature_reg_0_2_1; +reg [15:0] feature_reg_0_3_0; +reg [15:0] feature_reg_0_3_1; +reg [15:0] feature_reg_0_4_0; +reg [15:0] feature_reg_0_4_1; +reg [15:0] feature_reg_0_5_0; +reg [15:0] feature_reg_0_5_1; +reg [15:0] feature_reg_1_0_0; +reg [15:0] feature_reg_1_0_1; +reg [15:0] feature_reg_1_1_0; +reg [15:0] feature_reg_1_1_1; +reg [15:0] feature_reg_1_2_0; +reg [15:0] feature_reg_1_2_1; +reg [15:0] feature_reg_1_3_0; +reg [15:0] feature_reg_1_3_1; +reg [15:0] feature_reg_1_4_0; +reg [15:0] feature_reg_1_4_1; +reg [15:0] feature_reg_1_5_0; +reg [15:0] feature_reg_1_5_1; +reg [15:0] feature_reg_2_0_0; +reg [15:0] feature_reg_2_0_1; +reg [15:0] feature_reg_2_1_0; +reg [15:0] feature_reg_2_1_1; +reg [15:0] feature_reg_2_2_0; +reg [15:0] feature_reg_2_2_1; +reg [15:0] feature_reg_2_3_0; +reg [15:0] feature_reg_2_3_1; +reg [15:0] feature_reg_2_4_0; +reg [15:0] feature_reg_2_4_1; +reg [15:0] feature_reg_2_5_0; +reg [15:0] feature_reg_2_5_1; +reg [15:0] feature_reg_3_0_0; +reg [15:0] feature_reg_3_0_1; +reg [15:0] feature_reg_3_1_0; +reg [15:0] feature_reg_3_1_1; +reg [15:0] feature_reg_3_2_0; +reg [15:0] feature_reg_3_2_1; +reg [15:0] feature_reg_3_3_0; +reg [15:0] feature_reg_3_3_1; +reg [15:0] feature_reg_3_4_0; +reg [15:0] feature_reg_3_4_1; +reg [15:0] feature_reg_3_5_0; +reg [15:0] feature_reg_3_5_1; +reg [15:0] feature_reg_4_0_0; +reg [15:0] feature_reg_4_0_1; +reg [15:0] feature_reg_4_1_0; +reg [15:0] feature_reg_4_1_1; +reg [15:0] feature_reg_4_2_0; +reg [15:0] feature_reg_4_2_1; +reg [15:0] feature_reg_4_3_0; +reg [15:0] feature_reg_4_3_1; +reg [15:0] feature_reg_4_4_0; +reg [15:0] feature_reg_4_4_1; +reg [15:0] feature_reg_4_5_0; +reg [15:0] feature_reg_4_5_1; +reg [15:0] feature_reg_5_0_0; +reg [15:0] feature_reg_5_0_1; +reg [15:0] feature_reg_5_1_0; +reg [15:0] feature_reg_5_1_1; +reg [15:0] feature_reg_5_2_0; +reg [15:0] feature_reg_5_2_1; +reg [15:0] feature_reg_5_3_0; +reg [15:0] feature_reg_5_3_1; +reg [15:0] feature_reg_5_4_0; +reg [15:0] feature_reg_5_4_1; +reg [15:0] feature_reg_5_5_0; +reg [15:0] feature_reg_5_5_1; + +always @ (posedge clk) begin + calculate_1 <= calculate; + calculate_2 <= calculate_1; + calculate_3 <= calculate_2; + //Valid pipeline + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + valid_12 <= valid_11; + if (i_valid) begin + input_buffer_count <= 0; + calculate <= 0; + end else begin + //Input buffering logic + if (input_buffer_count == 5) begin + calculate <= 1; + input_buffer_count <= 0; + end else begin + calculate <= 0; + input_buffer_count <= input_buffer_count + 1'b1; + end + input_buffer_5_0 <= i_result_0_6; + input_buffer_5_1 <= i_result_1_6; + input_buffer_5_2 <= i_result_2_6; + input_buffer_5_3 <= i_result_3_6; + input_buffer_5_4 <= i_result_4_6; + input_buffer_5_5 <= i_result_5_6; + end + input_buffer_0_0 <= input_buffer_1_0; + input_buffer_0_1 <= input_buffer_1_1; + input_buffer_0_2 <= input_buffer_1_2; + input_buffer_0_3 <= input_buffer_1_3; + input_buffer_0_4 <= input_buffer_1_4; + input_buffer_0_5 <= input_buffer_1_5; + input_buffer_1_0 <= input_buffer_2_0; + input_buffer_1_1 <= input_buffer_2_1; + input_buffer_1_2 <= input_buffer_2_2; + input_buffer_1_3 <= input_buffer_2_3; + input_buffer_1_4 <= input_buffer_2_4; + input_buffer_1_5 <= input_buffer_2_5; + input_buffer_2_0 <= input_buffer_3_0; + input_buffer_2_1 <= input_buffer_3_1; + input_buffer_2_2 <= input_buffer_3_2; + input_buffer_2_3 <= input_buffer_3_3; + input_buffer_2_4 <= input_buffer_3_4; + input_buffer_2_5 <= input_buffer_3_5; + input_buffer_3_0 <= input_buffer_4_0; + input_buffer_3_1 <= input_buffer_4_1; + input_buffer_3_2 <= input_buffer_4_2; + input_buffer_3_3 <= input_buffer_4_3; + input_buffer_3_4 <= input_buffer_4_4; + input_buffer_3_5 <= input_buffer_4_5; + input_buffer_4_0 <= input_buffer_5_0; + input_buffer_4_1 <= input_buffer_5_1; + input_buffer_4_2 <= input_buffer_5_2; + input_buffer_4_3 <= input_buffer_5_3; + input_buffer_4_4 <= input_buffer_5_4; + input_buffer_4_5 <= input_buffer_5_5; + //Pipelining to synchronize DSPs and non-DSPs + feature_reg_0_0_0 <= input_buffer_0_0; + feature_reg_0_1_0 <= input_buffer_0_1; + feature_reg_0_2_0 <= input_buffer_0_2; + feature_reg_0_3_0 <= input_buffer_0_3; + feature_reg_0_4_0 <= input_buffer_0_4; + feature_reg_0_5_0 <= input_buffer_0_5; + feature_reg_1_0_0 <= input_buffer_1_0; + feature_reg_1_1_0 <= input_buffer_1_1; + feature_reg_1_2_0 <= input_buffer_1_2; + feature_reg_1_3_0 <= input_buffer_1_3; + feature_reg_1_4_0 <= input_buffer_1_4; + feature_reg_1_5_0 <= input_buffer_1_5; + feature_reg_2_0_0 <= input_buffer_2_0; + feature_reg_2_1_0 <= input_buffer_2_1; + feature_reg_2_2_0 <= input_buffer_2_2; + feature_reg_2_3_0 <= input_buffer_2_3; + feature_reg_2_4_0 <= input_buffer_2_4; + feature_reg_2_5_0 <= input_buffer_2_5; + feature_reg_3_0_0 <= input_buffer_3_0; + feature_reg_3_1_0 <= input_buffer_3_1; + feature_reg_3_2_0 <= input_buffer_3_2; + feature_reg_3_3_0 <= input_buffer_3_3; + feature_reg_3_4_0 <= input_buffer_3_4; + feature_reg_3_5_0 <= input_buffer_3_5; + feature_reg_4_0_0 <= input_buffer_4_0; + feature_reg_4_1_0 <= input_buffer_4_1; + feature_reg_4_2_0 <= input_buffer_4_2; + feature_reg_4_3_0 <= input_buffer_4_3; + feature_reg_4_4_0 <= input_buffer_4_4; + feature_reg_4_5_0 <= input_buffer_4_5; + feature_reg_5_0_0 <= input_buffer_5_0; + feature_reg_5_1_0 <= input_buffer_5_1; + feature_reg_5_2_0 <= input_buffer_5_2; + feature_reg_5_3_0 <= input_buffer_5_3; + feature_reg_5_4_0 <= input_buffer_5_4; + feature_reg_5_5_0 <= input_buffer_5_5; + feature_reg_0_0_1 <= feature_reg_0_0_0; + feature_reg_0_1_1 <= feature_reg_0_1_0; + feature_reg_0_2_1 <= feature_reg_0_2_0; + feature_reg_0_3_1 <= feature_reg_0_3_0; + feature_reg_0_4_1 <= feature_reg_0_4_0; + feature_reg_0_5_1 <= feature_reg_0_5_0; + feature_reg_1_0_1 <= feature_reg_1_0_0; + feature_reg_1_1_1 <= feature_reg_1_1_0; + feature_reg_1_2_1 <= feature_reg_1_2_0; + feature_reg_1_3_1 <= feature_reg_1_3_0; + feature_reg_1_4_1 <= feature_reg_1_4_0; + feature_reg_1_5_1 <= feature_reg_1_5_0; + feature_reg_2_0_1 <= feature_reg_2_0_0; + feature_reg_2_1_1 <= feature_reg_2_1_0; + feature_reg_2_2_1 <= feature_reg_2_2_0; + feature_reg_2_3_1 <= feature_reg_2_3_0; + feature_reg_2_4_1 <= feature_reg_2_4_0; + feature_reg_2_5_1 <= feature_reg_2_5_0; + feature_reg_3_0_1 <= feature_reg_3_0_0; + feature_reg_3_1_1 <= feature_reg_3_1_0; + feature_reg_3_2_1 <= feature_reg_3_2_0; + feature_reg_3_3_1 <= feature_reg_3_3_0; + feature_reg_3_4_1 <= feature_reg_3_4_0; + feature_reg_3_5_1 <= feature_reg_3_5_0; + feature_reg_4_0_1 <= feature_reg_4_0_0; + feature_reg_4_1_1 <= feature_reg_4_1_0; + feature_reg_4_2_1 <= feature_reg_4_2_0; + feature_reg_4_3_1 <= feature_reg_4_3_0; + feature_reg_4_4_1 <= feature_reg_4_4_0; + feature_reg_4_5_1 <= feature_reg_4_5_0; + feature_reg_5_0_1 <= feature_reg_5_0_0; + feature_reg_5_1_1 <= feature_reg_5_1_0; + feature_reg_5_2_1 <= feature_reg_5_2_0; + feature_reg_5_3_1 <= feature_reg_5_3_0; + feature_reg_5_4_1 <= feature_reg_5_4_0; + feature_reg_5_5_1 <= feature_reg_5_5_0; + //Output Serializing logic + if (calculate_3) begin + output_buffer_0_0 <= rslt_buffer_0_0; + output_buffer_1_0 <= rslt_buffer_0_1; + output_buffer_2_0 <= rslt_buffer_0_2; + output_buffer_3_0 <= rslt_buffer_0_3; + output_buffer_4_0 <= rslt_buffer_0_4; + output_buffer_5_0 <= rslt_buffer_0_5; + output_buffer_0_1 <= rslt_buffer_1_0; + output_buffer_1_1 <= rslt_buffer_1_1; + output_buffer_2_1 <= rslt_buffer_1_2; + output_buffer_3_1 <= rslt_buffer_1_3; + output_buffer_4_1 <= rslt_buffer_1_4; + output_buffer_5_1 <= rslt_buffer_1_5; + output_buffer_0_2 <= rslt_buffer_2_0; + output_buffer_1_2 <= rslt_buffer_2_1; + output_buffer_2_2 <= rslt_buffer_2_2; + output_buffer_3_2 <= rslt_buffer_2_3; + output_buffer_4_2 <= rslt_buffer_2_4; + output_buffer_5_2 <= rslt_buffer_2_5; + output_buffer_0_3 <= rslt_buffer_3_0; + output_buffer_1_3 <= rslt_buffer_3_1; + output_buffer_2_3 <= rslt_buffer_3_2; + output_buffer_3_3 <= rslt_buffer_3_3; + output_buffer_4_3 <= rslt_buffer_3_4; + output_buffer_5_3 <= rslt_buffer_3_5; + output_buffer_0_4 <= rslt_buffer_4_0; + output_buffer_1_4 <= rslt_buffer_4_1; + output_buffer_2_4 <= rslt_buffer_4_2; + output_buffer_3_4 <= rslt_buffer_4_3; + output_buffer_4_4 <= rslt_buffer_4_4; + output_buffer_5_4 <= rslt_buffer_4_5; + output_buffer_0_5 <= rslt_buffer_5_0; + output_buffer_1_5 <= rslt_buffer_5_1; + output_buffer_2_5 <= rslt_buffer_5_2; + output_buffer_3_5 <= rslt_buffer_5_3; + output_buffer_4_5 <= rslt_buffer_5_4; + output_buffer_5_5 <= rslt_buffer_5_5; + end else begin + output_buffer_0_0 <= output_buffer_0_1; + output_buffer_0_1 <= output_buffer_0_2; + output_buffer_0_2 <= output_buffer_0_3; + output_buffer_0_3 <= output_buffer_0_4; + output_buffer_0_4 <= output_buffer_0_5; + output_buffer_1_0 <= output_buffer_1_1; + output_buffer_1_1 <= output_buffer_1_2; + output_buffer_1_2 <= output_buffer_1_3; + output_buffer_1_3 <= output_buffer_1_4; + output_buffer_1_4 <= output_buffer_1_5; + output_buffer_2_0 <= output_buffer_2_1; + output_buffer_2_1 <= output_buffer_2_2; + output_buffer_2_2 <= output_buffer_2_3; + output_buffer_2_3 <= output_buffer_2_4; + output_buffer_2_4 <= output_buffer_2_5; + output_buffer_3_0 <= output_buffer_3_1; + output_buffer_3_1 <= output_buffer_3_2; + output_buffer_3_2 <= output_buffer_3_3; + output_buffer_3_3 <= output_buffer_3_4; + output_buffer_3_4 <= output_buffer_3_5; + output_buffer_4_0 <= output_buffer_4_1; + output_buffer_4_1 <= output_buffer_4_2; + output_buffer_4_2 <= output_buffer_4_3; + output_buffer_4_3 <= output_buffer_4_4; + output_buffer_4_4 <= output_buffer_4_5; + output_buffer_5_0 <= output_buffer_5_1; + output_buffer_5_1 <= output_buffer_5_2; + output_buffer_5_2 <= output_buffer_5_3; + output_buffer_5_3 <= output_buffer_5_4; + output_buffer_5_4 <= output_buffer_5_5; + end +end + +////// FIRST COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD00 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_2), + .by(input_buffer_2_0), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_1_0), + .resultb(dsp_out_1_1) +); + +winograd_dsp_16 winograd_dsp_16_WD10 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_2_4), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_1_2), + .resultb(dsp_out_1_3) +); + +winograd_dsp_16 winograd_dsp_16_WD20 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_2), + .by(input_buffer_1_0), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_1_4), + .resultb(dsp_out_1_5) +); + +winograd_dsp_16 winograd_dsp_16_WD30 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_1_6), + .resultb(dsp_out_1_7) +); + +winograd_dsp_16 winograd_dsp_16_WD40 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_0), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_1_8), + .resultb(dsp_out_1_9) +); + +winograd_dsp_16 winograd_dsp_16_WD50 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_4), + .by(input_buffer_5_2), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_1_10), + .resultb(dsp_out_1_11) +); + +////// SECOND COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD01 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_0), + .resultb(dsp_out_2_1) +); + +winograd_dsp_16 winograd_dsp_16_WD11 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_2), + .resultb(dsp_out_2_3) +); + +winograd_dsp_16 winograd_dsp_16_WD21 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_4), + .resultb(dsp_out_2_5) +); + +winograd_dsp_16 winograd_dsp_16_WD31 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_6), + .resultb(dsp_out_2_7) +); + +////// THIRD COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD02 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_0), + .resultb(dsp_out_3_1) +); + +winograd_dsp_16 winograd_dsp_16_WD12 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_2), + .resultb(dsp_out_3_3) +); + +winograd_dsp_16 winograd_dsp_16_WD22 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_4), + .resultb(dsp_out_3_5) +); + +winograd_dsp_16 winograd_dsp_16_WD32 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_6), + .resultb(dsp_out_3_7) +); + +////// FOURTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD03 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_0), + .resultb(dsp_out_4_1) +); + +winograd_dsp_16 winograd_dsp_16_WD13 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_2), + .resultb(dsp_out_4_3) +); + +winograd_dsp_16 winograd_dsp_16_WD23 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_4), + .resultb(dsp_out_4_5) +); + +winograd_dsp_16 winograd_dsp_16_WD33 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_6), + .resultb(dsp_out_4_7) +); + +////// FIFTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD04 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_0), + .resultb(dsp_out_5_1) +); + +winograd_dsp_16 winograd_dsp_16_WD14 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_2), + .resultb(dsp_out_5_3) +); + +winograd_dsp_16 winograd_dsp_16_WD24 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_4), + .resultb(dsp_out_5_5) +); + +winograd_dsp_16 winograd_dsp_16_WD34 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_6), + .resultb(dsp_out_5_7) +); + +////// SIXTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD05 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_3), + .by(input_buffer_2_1), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_6_0), + .resultb(dsp_out_6_1) +); + +winograd_dsp_16 winograd_dsp_16_WD15 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_5), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_6_2), + .resultb(dsp_out_6_3) +); + +winograd_dsp_16 winograd_dsp_16_WD25 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_3), + .by(input_buffer_1_3), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_6_4), + .resultb(dsp_out_6_5) +); + +winograd_dsp_16 winograd_dsp_16_WD35 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_3_3), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_6_6), + .resultb(dsp_out_6_7) +); + +winograd_dsp_16 winograd_dsp_16_WD45 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_3), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_6_8), + .resultb(dsp_out_6_9) +); + +winograd_dsp_16 winograd_dsp_16_WD55 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_5), + .by(input_buffer_5_3), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_6_10), + .resultb(dsp_out_6_11) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA00 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_0_1[11:0], 4'b0000}), + .data1x(dsp_out_1_0), + .data2x({feature_reg_0_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_1), + .data4x(dsp_out_1_2), + .data5x(dsp_out_1_3), + .data6x({feature_reg_4_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_4), + .data8x(feature_reg_4_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_0) +); + +wire [15:0] f1, f2, f3, f4; +assign f1 = -{feature_reg_1_0_1[11:0], 4'b0000}; +assign f2 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f3 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f4 = -{feature_reg_2_4_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA10 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_1_5), + .data1x(f1), + .data2x(f2), + .data3x(f3), + .data4x(dsp_out_1_6), + .data5x(f4), + .data6x({feature_reg_3_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_7), + .data8x(feature_reg_3_4_1), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_0) +); + +wire [15:0] f5, f6, f7, f8, f9, f10; +assign f5 = -dsp_out_1_5; +assign f6 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f7 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f8 = -{feature_reg_3_0_1[13:0], 2'b00}; +assign f9 = -dsp_out_1_7; +assign f10 = -feature_reg_3_4_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA20 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f5), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(f6), + .data4x(dsp_out_1_6), + .data5x(f7), + .data6x(f8), + .data7x(f9), + .data8x(f10), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_0) +); + +wire [15:0] f11, f12, f13, f14, f15, f16, f17; +assign f11 = -{feature_reg_1_0_1[12:0], 3'b000}; +assign f12 = -{feature_reg_1_4_1[14:0], 1'b0}; +assign f13 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f14 = -feature_reg_2_4_1; +assign f15 = dsp_out_1_5 >>> 1; +assign f16 = dsp_out_1_6 >>> 2; +assign f17 = dsp_out_1_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA30 ( + .clock(clk), + .clken(calculate_2), + .data0x(f15), + .data1x(f11), + .data2x(f12), + .data3x(f13), + .data4x(f16), + .data5x(f14), + .data6x({feature_reg_3_0_1[12:0], 3'b000}), + .data7x(f17), + .data8x({feature_reg_3_4_1[14:0], 1'b0}), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_0) +); + +wire [15:0] f18, f19, f20, f21, f22, f23, f23b; +assign f18 = -(dsp_out_1_5 >>> 1); +assign f19 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f20 = -feature_reg_2_4_1; +assign f21 = -{feature_reg_3_0_1[12:0], 3'b000}; +assign f22 = -(dsp_out_1_7 <<< 1); +assign f23 = -{feature_reg_3_4_1[14:0], 1'b0}; +assign f23b = dsp_out_1_6 >>> 2; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA40 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[12:0], 3'b000}), + .data1x(f18), + .data2x({feature_reg_1_4_1[14:0], 1'b0}), + .data3x(f19), + .data4x(f23b), + .data5x(f20), + .data6x(f21), + .data7x(f22), + .data8x(f23), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_0) +); + +wire [15:0] f24; +assign f24 = -dsp_out_1_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA50 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f24), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_8), + .data4x(dsp_out_1_9), + .data5x(dsp_out_1_10), + .data6x({feature_reg_5_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_11), + .data8x(feature_reg_5_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_0) +); + +wire [15:0] f25, f26, f27, f28; +assign f25 = -{feature_reg_0_2_1[11:0], 4'b0000}; +assign f26 = -{feature_reg_0_1_1[11:0], 4'b0000}; +assign f27 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f28 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA01 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[13:0], 2'b00}), + .data1x(f25), + .data2x(f26), + .data3x({feature_reg_0_4_1[13:0], 2'b00}), + .data4x(dsp_out_2_0), + .data5x(dsp_out_2_1), + .data6x(dsp_out_2_2), + .data7x(dsp_out_2_3), + .data8x(f27), + .data9x(f28), + .data10x(feature_reg_4_3_1), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_1) +); + +wire [15:0] f29, f30, f31, f32, f33, f34, f35, f36; +assign f29 = -{feature_reg_1_3_1[13:0], 2'b00}; +assign f30 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f31 = -{feature_reg_2_3_1[13:0], 2'b00}; +assign f32 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f33 = -{feature_reg_3_1_1[13:0], 2'b00}; +assign f34 = -{feature_reg_3_2_1[13:0], 2'b00}; +assign f35 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f36 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA11 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0], 4'b0000}), + .data1x({feature_reg_1_2_1[11:0], 4'b0000}), + .data2x(f29), + .data3x(f30), + .data4x({feature_reg_2_1_1[11:0], 4'b0000}), + .data5x({feature_reg_2_2_1[11:0], 4'b0000}), + .data6x(f31), + .data7x(f32), + .data8x(f33), + .data9x(f34), + .data10x(feature_reg_3_3_1), + .data11x(feature_reg_3_4_1), + .data12x(f35), + .data13x(f36), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_1) +); + +wire [15:0] f37, f38, f39, f40, f41, f42, f43, f44; +assign f37 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f38 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f39 = -{feature_reg_2_3_1[13:0],2'b00}; +assign f40 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f41 = -feature_reg_3_3_1; +assign f42 = -feature_reg_3_4_1; +assign f43 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f44 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA21 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f37), + .data2x(f38), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[11:0],4'b0000}), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x(f39), + .data7x(f40), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(f41), + .data11x(f42), + .data12x(f43), + .data13x(f44), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_1) +); + +wire [15:0] f45, f46, f47, f48, f49, f50, f51, f52; +assign f45 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f46 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f47 = -feature_reg_2_3_1; +assign f48 = -feature_reg_2_4_1; +assign f49 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f50 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f51 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f52 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA31 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[12:0],3'b000}), + .data2x(f45), + .data3x(f46), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f47), + .data7x(f48), + .data8x(f49), + .data9x(f50), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f51), + .data13x(f52), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_1) +); + +wire [15:0] f53, f54, f55, f56, f57, f58, f59, f60; +assign f53 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f54 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f55 = -feature_reg_2_3_1; +assign f56 = -feature_reg_2_4_1; +assign f57 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f58 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f59 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f60 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA41 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[14:0],1'b0}), + .data1x(f53), + .data2x(f54), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f55), + .data7x(f56), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x(f57), + .data11x(f58), + .data12x(f59), + .data13x(f60), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_1) +); + +wire [15:0] f61, f62, f63, f64; +assign f61 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f62 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f63 = -{feature_reg_5_1_1[13:0],2'b00}; +assign f64 = -{feature_reg_5_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA51 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f61), + .data2x(f62), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_2_4), + .data5x(dsp_out_2_5), + .data6x(dsp_out_2_6), + .data7x(dsp_out_2_7), + .data8x(f63), + .data9x(f64), + .data10x(feature_reg_5_3_1), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_1) +); + +wire [15:0] f65, f66, f67, f68; +assign f65 = -{feature_reg_0_2_1[11:0],4'b0000}; +assign f66 = -{feature_reg_0_3_1[13:0],2'b00}; +assign f67 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f68 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA02 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(f65), + .data2x(f66), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_3_0), + .data5x(dsp_out_3_1), + .data6x(dsp_out_3_2), + .data7x(dsp_out_3_3), + .data8x({feature_reg_4_1_1[13:0],2'b00}), + .data9x(f67), + .data10x(f68), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_2) +); + +wire [15:0] f69, f70, f71, f72, f73, f74, f75, f76; +assign f69 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f70 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f71 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f72 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f73 = -{feature_reg_3_2_1[13:0],2'b00}; +assign f74 = -feature_reg_3_3_1; +assign f75 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f76 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA12 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[11:0],4'b0000}), + .data1x(f69), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f70), + .data4x(f71), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f72), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f73), + .data10x(f74), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f75), + .data14x(f76), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_2) +); + +wire [15:0] f77, f78, f79, f80, f81, f82, f83, f84; +assign f77 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f78 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f79 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f80 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f81 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f82 = -feature_reg_3_4_1; +assign f83 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f84 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA22 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f77), + .data2x(f78), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f79), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f80), + .data8x(f81), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(feature_reg_3_3_1), + .data11x(f82), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f83), + .data14x(f84), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_2) +); + +wire [15:0] f85, f86, f87, f88, f89, f90, f91, f92; +assign f85 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f86 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f87 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f88 = -feature_reg_2_4_1; +assign f89 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f90 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f91 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f92 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA32 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[12:0],3'b000}), + .data1x(f85), + .data2x({feature_reg_1_3_1[14:0],1'b0}), + .data3x(f86), + .data4x(f87), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f88), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x(f89), + .data10x(f90), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f91), + .data14x(f92), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_2) +); + +wire [15:0] f93, f94, f95, f96, f97, f98, f99, f100; +assign f93 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f94 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f95 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f96 = -feature_reg_2_4_1; +assign f97 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f98 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f99 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f100 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA42 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f93), + .data2x(f94), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f95), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f96), + .data8x(f97), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f98), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f99), + .data14x(f100), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_2) +); + +wire [15:0] f101, f102, f103, f104; +assign f101 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f102 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f103 = -{feature_reg_5_2_1[13:0],2'b00}; +assign f104 = -feature_reg_5_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA52 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f101), + .data2x(f102), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_3_4), + .data5x(dsp_out_3_5), + .data6x(dsp_out_3_6), + .data7x(dsp_out_3_7), + .data8x({feature_reg_5_1_1[13:0],2'b00}), + .data9x(f103), + .data10x(f104), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_2) +); + +wire [15:0] f105, f106, f107, f108; +assign f105 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f106 = -{feature_reg_0_1_1[12:0],3'b000}; +assign f107 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f108 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA03 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[12:0],3'b000}), + .data1x(f105), + .data2x(f106), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_4_0), + .data5x(dsp_out_4_1), + .data6x(dsp_out_4_2), + .data7x(dsp_out_4_3), + .data8x(f107), + .data9x(f108), + .data10x({feature_reg_4_3_1[14:0],1'b0}), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_3) +); + +wire [15:0] f109, f110, f111, f112, f113, f114, f115, f116; +assign f109 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f110 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f111 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f112 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f113 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f114 = -feature_reg_3_2_1; +assign f115 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f116 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA13 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[13:0],2'b00}), + .data2x(f109), + .data3x(f110), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f111), + .data7x(f112), + .data8x(f113), + .data9x(f114), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(feature_reg_3_4_1), + .data12x(f115), + .data13x(f116), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_3) +); + +wire [15:0] f117, f118, f119, f120, f121, f122, f123, f124; +assign f117 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f118 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f119 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f120 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f121 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f122 = -feature_reg_3_4_1; +assign f123 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f124 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA23 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f117), + .data2x(f118), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f119), + .data7x(f120), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(feature_reg_3_2_1), + .data10x(f121), + .data11x(f122), + .data12x(f123), + .data13x(f124), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_3) +); + +wire [15:0] f125, f126, f127, f128, f129, f130, f131, f132; +assign f125 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f126 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f127 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f128 = -feature_reg_2_4_1; +assign f129 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f130 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f131 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f132 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA33 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x({feature_reg_1_2_1[14:0],1'b0}), + .data2x(f125), + .data3x(f126), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f127), + .data7x(f128), + .data8x(f129), + .data9x(f130), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f131), + .data13x(f132), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_3) +); + +wire [15:0] f133, f134, f135, f136, f137, f138, f139, f140; +assign f133 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f134 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f135 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f136 = -feature_reg_2_4_1; +assign f137 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f138 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f139 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f140 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA43 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f133), + .data2x(f134), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f135), + .data7x(f136), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x(f137), + .data11x(f138), + .data12x(f139), + .data13x(f140), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_3) +); + +wire [15:0] f141, f142, f143, f144; +assign f141 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f142 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f143 = -{feature_reg_5_1_1[14:0],1'b0}; +assign f144 = -feature_reg_5_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA53 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f141), + .data2x(f142), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_4_4), + .data5x(dsp_out_4_5), + .data6x(dsp_out_4_6), + .data7x(dsp_out_4_7), + .data8x(f143), + .data9x(f144), + .data10x({feature_reg_5_3_1[14:0],1'b0}), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_3) +); + +wire [15:0] f145, f146, f147, f148; +assign f145 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f146 = -{feature_reg_0_3_1[12:0],3'b000}; +assign f147 = -feature_reg_4_2_1; +assign f148 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA04 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[12:0],3'b000}), + .data1x(f145), + .data2x(f146), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_5_0), + .data5x(dsp_out_5_1), + .data6x(dsp_out_5_2), + .data7x(dsp_out_5_3), + .data8x({feature_reg_4_1_1[14:0],1'b0}), + .data9x(f147), + .data10x(f148), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_4) +); + +wire [15:0] f149, f150, f151, f152, f153, f154, f155, f156; +assign f149 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f150 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f151 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f152 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f153 = -feature_reg_3_2_1; +assign f154 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f155 = -feature_reg_4_2_1; +assign f156 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA14 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[13:0],2'b00}), + .data1x(f149), + .data2x({feature_reg_1_3_1[12:0],3'b000}), + .data3x(f150), + .data4x(f151), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f152), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(f153), + .data10x(f154), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f155), + .data14x(f156), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_4) +); + +wire [15:0] f157, f158, f159, f160, f161, f162, f163, f164; +assign f157 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f158 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f159 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f160 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f161 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f162 = -feature_reg_3_4_1; +assign f163 = -feature_reg_4_2_1; +assign f164 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA24 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f157), + .data2x(f158), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f159), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f160), + .data8x(f161), + .data9x(feature_reg_3_2_1), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f162), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f163), + .data14x(f164), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_4) +); + +wire [15:0] f165, f166, f167, f168, f169, f170, f171, f172; +assign f165 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f166 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f167 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f168 = -feature_reg_2_4_1; +assign f169 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f170 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f171 = -feature_reg_4_2_1; +assign f172 = -{feature_reg_4_1_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA34 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[14:0],1'b0}), + .data1x(f165), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f166), + .data4x(f167), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f168), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f169), + .data10x(f170), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f171), + .data14x(f172), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_4) +); + +wire [15:0] f173, f174, f175, f176, f177, f178, f179, f180; +assign f173 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f174 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f175 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f176 = -feature_reg_2_4_1; +assign f177 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f178 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f179 = -feature_reg_4_2_1; +assign f180 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA44 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x(f173), + .data2x(f174), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f175), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f176), + .data8x(f177), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x(f178), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f179), + .data14x(f180), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_4) +); + +wire [15:0] f181, f182, f183, f184; +assign f181 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f182 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f183 = -feature_reg_5_2_1; +assign f184 = -{feature_reg_5_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA54 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f181), + .data2x(f182), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_5_4), + .data5x(dsp_out_5_5), + .data6x(dsp_out_5_6), + .data7x(dsp_out_5_7), + .data8x({feature_reg_5_1_1[14:0],1'b0}), + .data9x(f183), + .data10x(f184), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_4) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA05 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(dsp_out_6_0), + .data2x({feature_reg_0_5_1[13:0],2'b00}), + .data3x(dsp_out_6_1), + .data4x(dsp_out_6_2), + .data5x(dsp_out_6_3), + .data6x({feature_reg_4_1_1[13:0],2'b00}), + .data7x(dsp_out_6_4), + .data8x(feature_reg_4_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_5) +); + +wire [15:0] f185, f186, f187, f188; +assign f185 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f186 = -{feature_reg_1_5_1[13:0],2'b00}; +assign f187 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f188 = -{feature_reg_2_5_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA15 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_6_5), + .data1x(f185), + .data2x(f186), + .data3x(f187), + .data4x(dsp_out_6_6), + .data5x(f188), + .data6x({feature_reg_3_1_1[13:0],2'b00}), + .data7x(dsp_out_6_7), + .data8x(feature_reg_3_5_1), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_5) +); + +wire [15:0] f189, f190, f191, f192, f193, f194; +assign f189 = -dsp_out_6_5; +assign f190 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f191 = -{feature_reg_2_5_1[13:0],2'b00}; +assign f192 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f193 = -dsp_out_6_7; +assign f194 = -feature_reg_3_5_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA25 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f189), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(f190), + .data4x(dsp_out_6_6), + .data5x(f191), + .data6x(f192), + .data7x(f193), + .data8x(f194), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_5) +); + +wire [15:0] f195, f196, f197, f198, f199, f200, f201; +assign f195 = dsp_out_6_5 >>> 1; +assign f196 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f197 = -{feature_reg_1_5_1[14:0],1'b0}; +assign f198 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f199 = dsp_out_6_6 >>> 2; +assign f200 = -feature_reg_2_5_1; +assign f201 = dsp_out_6_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA35 ( + .clock(clk), + .clken(calculate_2), + .data0x(f195), + .data1x(f196), + .data2x(f197), + .data3x(f198), + .data4x(f199), + .data5x(f200), + .data6x({feature_reg_3_1_1[12:0],3'b000}), + .data7x(f201), + .data8x({feature_reg_3_5_1[14:0],1'b0}), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_5) +); + +wire [15:0] f202, f203, f204, f205, f206, f207, f208; +assign f202 = -(dsp_out_6_5 >>> 1); +assign f203 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f204 = dsp_out_6_6 >>> 2; +assign f205 = -feature_reg_2_5_1; +assign f206 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f207 = -(dsp_out_6_7 <<< 1); +assign f208 = -{feature_reg_3_5_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA45 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f202), + .data2x({feature_reg_1_5_1[14:0],1'b0}), + .data3x(f203), + .data4x(f204), + .data5x(f205), + .data6x(f206), + .data7x(f207), + .data8x(f208), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_5) +); + +wire [15:0] f209; +assign f209 = -dsp_out_6_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA55 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f209), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(dsp_out_6_8), + .data4x(dsp_out_6_9), + .data5x(dsp_out_6_10), + .data6x({feature_reg_5_1_1[13:0],2'b00}), + .data7x(dsp_out_6_11), + .data8x(feature_reg_5_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_5) +); + +assign o_feature_0 = output_buffer_0_0[15:0]; +assign o_feature_1 = output_buffer_1_0[15:0]; +assign o_feature_2 = output_buffer_2_0[15:0]; +assign o_feature_3 = output_buffer_3_0[15:0]; +assign o_feature_4 = output_buffer_4_0[15:0]; +assign o_feature_5 = output_buffer_5_0[15:0]; +assign o_valid = valid_9; + +endmodule + +module winograd_transform_1 ( + input clk, + input i_valid, + input [15:0] i_result_0_0, + input [15:0] i_result_0_1, + input [15:0] i_result_0_2, + input [15:0] i_result_0_3, + input [15:0] i_result_0_4, + input [15:0] i_result_0_5, + input [15:0] i_result_0_6, + input [15:0] i_result_0_7, + input [15:0] i_result_1_0, + input [15:0] i_result_1_1, + input [15:0] i_result_1_2, + input [15:0] i_result_1_3, + input [15:0] i_result_1_4, + input [15:0] i_result_1_5, + input [15:0] i_result_1_6, + input [15:0] i_result_1_7, + input [15:0] i_result_2_0, + input [15:0] i_result_2_1, + input [15:0] i_result_2_2, + input [15:0] i_result_2_3, + input [15:0] i_result_2_4, + input [15:0] i_result_2_5, + input [15:0] i_result_2_6, + input [15:0] i_result_2_7, + input [15:0] i_result_3_0, + input [15:0] i_result_3_1, + input [15:0] i_result_3_2, + input [15:0] i_result_3_3, + input [15:0] i_result_3_4, + input [15:0] i_result_3_5, + input [15:0] i_result_3_6, + input [15:0] i_result_3_7, + input [15:0] i_result_4_0, + input [15:0] i_result_4_1, + input [15:0] i_result_4_2, + input [15:0] i_result_4_3, + input [15:0] i_result_4_4, + input [15:0] i_result_4_5, + input [15:0] i_result_4_6, + input [15:0] i_result_4_7, + input [15:0] i_result_5_0, + input [15:0] i_result_5_1, + input [15:0] i_result_5_2, + input [15:0] i_result_5_3, + input [15:0] i_result_5_4, + input [15:0] i_result_5_5, + input [15:0] i_result_5_6, + input [15:0] i_result_5_7, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output [15:0] o_feature_2, + output [15:0] o_feature_3, + output [15:0] o_feature_4, + output [15:0] o_feature_5, + output o_valid +); + +reg [15:0] input_buffer_0_0; +reg [19:0] output_buffer_0_0; +wire [19:0] rslt_buffer_0_0; +reg [15:0] input_buffer_0_1; +reg [19:0] output_buffer_0_1; +wire [19:0] rslt_buffer_0_1; +reg [15:0] input_buffer_0_2; +reg [19:0] output_buffer_0_2; +wire [19:0] rslt_buffer_0_2; +reg [15:0] input_buffer_0_3; +reg [19:0] output_buffer_0_3; +wire [19:0] rslt_buffer_0_3; +reg [15:0] input_buffer_0_4; +reg [19:0] output_buffer_0_4; +wire [19:0] rslt_buffer_0_4; +reg [15:0] input_buffer_0_5; +reg [19:0] output_buffer_0_5; +wire [19:0] rslt_buffer_0_5; +reg [15:0] input_buffer_1_0; +reg [19:0] output_buffer_1_0; +wire [19:0] rslt_buffer_1_0; +reg [15:0] input_buffer_1_1; +reg [19:0] output_buffer_1_1; +wire [19:0] rslt_buffer_1_1; +reg [15:0] input_buffer_1_2; +reg [19:0] output_buffer_1_2; +wire [19:0] rslt_buffer_1_2; +reg [15:0] input_buffer_1_3; +reg [19:0] output_buffer_1_3; +wire [19:0] rslt_buffer_1_3; +reg [15:0] input_buffer_1_4; +reg [19:0] output_buffer_1_4; +wire [19:0] rslt_buffer_1_4; +reg [15:0] input_buffer_1_5; +reg [19:0] output_buffer_1_5; +wire [19:0] rslt_buffer_1_5; +reg [15:0] input_buffer_2_0; +reg [19:0] output_buffer_2_0; +wire [19:0] rslt_buffer_2_0; +reg [15:0] input_buffer_2_1; +reg [19:0] output_buffer_2_1; +wire [19:0] rslt_buffer_2_1; +reg [15:0] input_buffer_2_2; +reg [19:0] output_buffer_2_2; +wire [19:0] rslt_buffer_2_2; +reg [15:0] input_buffer_2_3; +reg [19:0] output_buffer_2_3; +wire [19:0] rslt_buffer_2_3; +reg [15:0] input_buffer_2_4; +reg [19:0] output_buffer_2_4; +wire [19:0] rslt_buffer_2_4; +reg [15:0] input_buffer_2_5; +reg [19:0] output_buffer_2_5; +wire [19:0] rslt_buffer_2_5; +reg [15:0] input_buffer_3_0; +reg [19:0] output_buffer_3_0; +wire [19:0] rslt_buffer_3_0; +reg [15:0] input_buffer_3_1; +reg [19:0] output_buffer_3_1; +wire [19:0] rslt_buffer_3_1; +reg [15:0] input_buffer_3_2; +reg [19:0] output_buffer_3_2; +wire [19:0] rslt_buffer_3_2; +reg [15:0] input_buffer_3_3; +reg [19:0] output_buffer_3_3; +wire [19:0] rslt_buffer_3_3; +reg [15:0] input_buffer_3_4; +reg [19:0] output_buffer_3_4; +wire [19:0] rslt_buffer_3_4; +reg [15:0] input_buffer_3_5; +reg [19:0] output_buffer_3_5; +wire [19:0] rslt_buffer_3_5; +reg [15:0] input_buffer_4_0; +reg [19:0] output_buffer_4_0; +wire [19:0] rslt_buffer_4_0; +reg [15:0] input_buffer_4_1; +reg [19:0] output_buffer_4_1; +wire [19:0] rslt_buffer_4_1; +reg [15:0] input_buffer_4_2; +reg [19:0] output_buffer_4_2; +wire [19:0] rslt_buffer_4_2; +reg [15:0] input_buffer_4_3; +reg [19:0] output_buffer_4_3; +wire [19:0] rslt_buffer_4_3; +reg [15:0] input_buffer_4_4; +reg [19:0] output_buffer_4_4; +wire [19:0] rslt_buffer_4_4; +reg [15:0] input_buffer_4_5; +reg [19:0] output_buffer_4_5; +wire [19:0] rslt_buffer_4_5; +reg [15:0] input_buffer_5_0; +reg [19:0] output_buffer_5_0; +wire [19:0] rslt_buffer_5_0; +reg [15:0] input_buffer_5_1; +reg [19:0] output_buffer_5_1; +wire [19:0] rslt_buffer_5_1; +reg [15:0] input_buffer_5_2; +reg [19:0] output_buffer_5_2; +wire [19:0] rslt_buffer_5_2; +reg [15:0] input_buffer_5_3; +reg [19:0] output_buffer_5_3; +wire [19:0] rslt_buffer_5_3; +reg [15:0] input_buffer_5_4; +reg [19:0] output_buffer_5_4; +wire [19:0] rslt_buffer_5_4; +reg [15:0] input_buffer_5_5; +reg [19:0] output_buffer_5_5; +wire [19:0] rslt_buffer_5_5; +reg calculate, calculate_1, calculate_2, calculate_3; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg valid_12; +reg [2:0] input_buffer_count; +wire [15:0] dsp_out_1_0; +wire [15:0] dsp_out_1_1; +wire [15:0] dsp_out_1_2; +wire [15:0] dsp_out_1_3; +wire [15:0] dsp_out_1_4; +wire [15:0] dsp_out_1_5; +wire [15:0] dsp_out_1_6; +wire [15:0] dsp_out_1_7; +wire [15:0] dsp_out_1_8; +wire [15:0] dsp_out_1_9; +wire [15:0] dsp_out_1_10; +wire [15:0] dsp_out_1_11; +wire [15:0] dsp_out_2_0; +wire [15:0] dsp_out_2_1; +wire [15:0] dsp_out_2_2; +wire [15:0] dsp_out_2_3; +wire [15:0] dsp_out_2_4; +wire [15:0] dsp_out_2_5; +wire [15:0] dsp_out_2_6; +wire [15:0] dsp_out_2_7; +wire [15:0] dsp_out_3_0; +wire [15:0] dsp_out_3_1; +wire [15:0] dsp_out_3_2; +wire [15:0] dsp_out_3_3; +wire [15:0] dsp_out_3_4; +wire [15:0] dsp_out_3_5; +wire [15:0] dsp_out_3_6; +wire [15:0] dsp_out_3_7; +wire [15:0] dsp_out_4_0; +wire [15:0] dsp_out_4_1; +wire [15:0] dsp_out_4_2; +wire [15:0] dsp_out_4_3; +wire [15:0] dsp_out_4_4; +wire [15:0] dsp_out_4_5; +wire [15:0] dsp_out_4_6; +wire [15:0] dsp_out_4_7; +wire [15:0] dsp_out_5_0; +wire [15:0] dsp_out_5_1; +wire [15:0] dsp_out_5_2; +wire [15:0] dsp_out_5_3; +wire [15:0] dsp_out_5_4; +wire [15:0] dsp_out_5_5; +wire [15:0] dsp_out_5_6; +wire [15:0] dsp_out_5_7; +wire [15:0] dsp_out_6_0; +wire [15:0] dsp_out_6_1; +wire [15:0] dsp_out_6_2; +wire [15:0] dsp_out_6_3; +wire [15:0] dsp_out_6_4; +wire [15:0] dsp_out_6_5; +wire [15:0] dsp_out_6_6; +wire [15:0] dsp_out_6_7; +wire [15:0] dsp_out_6_8; +wire [15:0] dsp_out_6_9; +wire [15:0] dsp_out_6_10; +wire [15:0] dsp_out_6_11; +reg [15:0] feature_reg_0_0_0; +reg [15:0] feature_reg_0_0_1; +reg [15:0] feature_reg_0_1_0; +reg [15:0] feature_reg_0_1_1; +reg [15:0] feature_reg_0_2_0; +reg [15:0] feature_reg_0_2_1; +reg [15:0] feature_reg_0_3_0; +reg [15:0] feature_reg_0_3_1; +reg [15:0] feature_reg_0_4_0; +reg [15:0] feature_reg_0_4_1; +reg [15:0] feature_reg_0_5_0; +reg [15:0] feature_reg_0_5_1; +reg [15:0] feature_reg_1_0_0; +reg [15:0] feature_reg_1_0_1; +reg [15:0] feature_reg_1_1_0; +reg [15:0] feature_reg_1_1_1; +reg [15:0] feature_reg_1_2_0; +reg [15:0] feature_reg_1_2_1; +reg [15:0] feature_reg_1_3_0; +reg [15:0] feature_reg_1_3_1; +reg [15:0] feature_reg_1_4_0; +reg [15:0] feature_reg_1_4_1; +reg [15:0] feature_reg_1_5_0; +reg [15:0] feature_reg_1_5_1; +reg [15:0] feature_reg_2_0_0; +reg [15:0] feature_reg_2_0_1; +reg [15:0] feature_reg_2_1_0; +reg [15:0] feature_reg_2_1_1; +reg [15:0] feature_reg_2_2_0; +reg [15:0] feature_reg_2_2_1; +reg [15:0] feature_reg_2_3_0; +reg [15:0] feature_reg_2_3_1; +reg [15:0] feature_reg_2_4_0; +reg [15:0] feature_reg_2_4_1; +reg [15:0] feature_reg_2_5_0; +reg [15:0] feature_reg_2_5_1; +reg [15:0] feature_reg_3_0_0; +reg [15:0] feature_reg_3_0_1; +reg [15:0] feature_reg_3_1_0; +reg [15:0] feature_reg_3_1_1; +reg [15:0] feature_reg_3_2_0; +reg [15:0] feature_reg_3_2_1; +reg [15:0] feature_reg_3_3_0; +reg [15:0] feature_reg_3_3_1; +reg [15:0] feature_reg_3_4_0; +reg [15:0] feature_reg_3_4_1; +reg [15:0] feature_reg_3_5_0; +reg [15:0] feature_reg_3_5_1; +reg [15:0] feature_reg_4_0_0; +reg [15:0] feature_reg_4_0_1; +reg [15:0] feature_reg_4_1_0; +reg [15:0] feature_reg_4_1_1; +reg [15:0] feature_reg_4_2_0; +reg [15:0] feature_reg_4_2_1; +reg [15:0] feature_reg_4_3_0; +reg [15:0] feature_reg_4_3_1; +reg [15:0] feature_reg_4_4_0; +reg [15:0] feature_reg_4_4_1; +reg [15:0] feature_reg_4_5_0; +reg [15:0] feature_reg_4_5_1; +reg [15:0] feature_reg_5_0_0; +reg [15:0] feature_reg_5_0_1; +reg [15:0] feature_reg_5_1_0; +reg [15:0] feature_reg_5_1_1; +reg [15:0] feature_reg_5_2_0; +reg [15:0] feature_reg_5_2_1; +reg [15:0] feature_reg_5_3_0; +reg [15:0] feature_reg_5_3_1; +reg [15:0] feature_reg_5_4_0; +reg [15:0] feature_reg_5_4_1; +reg [15:0] feature_reg_5_5_0; +reg [15:0] feature_reg_5_5_1; + +always @ (posedge clk) begin + calculate_1 <= calculate; + calculate_2 <= calculate_1; + calculate_3 <= calculate_2; + //Valid pipeline + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + valid_12 <= valid_11; + if (i_valid) begin + input_buffer_count <= 0; + calculate <= 0; + end else begin + //Input buffering logic + if (input_buffer_count == 5) begin + calculate <= 1; + input_buffer_count <= 0; + end else begin + calculate <= 0; + input_buffer_count <= input_buffer_count + 1'b1; + end + input_buffer_5_0 <= i_result_0_1; + input_buffer_5_1 <= i_result_1_1; + input_buffer_5_2 <= i_result_2_1; + input_buffer_5_3 <= i_result_3_1; + input_buffer_5_4 <= i_result_4_1; + input_buffer_5_5 <= i_result_5_1; + end + input_buffer_0_0 <= input_buffer_1_0; + input_buffer_0_1 <= input_buffer_1_1; + input_buffer_0_2 <= input_buffer_1_2; + input_buffer_0_3 <= input_buffer_1_3; + input_buffer_0_4 <= input_buffer_1_4; + input_buffer_0_5 <= input_buffer_1_5; + input_buffer_1_0 <= input_buffer_2_0; + input_buffer_1_1 <= input_buffer_2_1; + input_buffer_1_2 <= input_buffer_2_2; + input_buffer_1_3 <= input_buffer_2_3; + input_buffer_1_4 <= input_buffer_2_4; + input_buffer_1_5 <= input_buffer_2_5; + input_buffer_2_0 <= input_buffer_3_0; + input_buffer_2_1 <= input_buffer_3_1; + input_buffer_2_2 <= input_buffer_3_2; + input_buffer_2_3 <= input_buffer_3_3; + input_buffer_2_4 <= input_buffer_3_4; + input_buffer_2_5 <= input_buffer_3_5; + input_buffer_3_0 <= input_buffer_4_0; + input_buffer_3_1 <= input_buffer_4_1; + input_buffer_3_2 <= input_buffer_4_2; + input_buffer_3_3 <= input_buffer_4_3; + input_buffer_3_4 <= input_buffer_4_4; + input_buffer_3_5 <= input_buffer_4_5; + input_buffer_4_0 <= input_buffer_5_0; + input_buffer_4_1 <= input_buffer_5_1; + input_buffer_4_2 <= input_buffer_5_2; + input_buffer_4_3 <= input_buffer_5_3; + input_buffer_4_4 <= input_buffer_5_4; + input_buffer_4_5 <= input_buffer_5_5; + //Pipelining to synchronize DSPs and non-DSPs + feature_reg_0_0_0 <= input_buffer_0_0; + feature_reg_0_1_0 <= input_buffer_0_1; + feature_reg_0_2_0 <= input_buffer_0_2; + feature_reg_0_3_0 <= input_buffer_0_3; + feature_reg_0_4_0 <= input_buffer_0_4; + feature_reg_0_5_0 <= input_buffer_0_5; + feature_reg_1_0_0 <= input_buffer_1_0; + feature_reg_1_1_0 <= input_buffer_1_1; + feature_reg_1_2_0 <= input_buffer_1_2; + feature_reg_1_3_0 <= input_buffer_1_3; + feature_reg_1_4_0 <= input_buffer_1_4; + feature_reg_1_5_0 <= input_buffer_1_5; + feature_reg_2_0_0 <= input_buffer_2_0; + feature_reg_2_1_0 <= input_buffer_2_1; + feature_reg_2_2_0 <= input_buffer_2_2; + feature_reg_2_3_0 <= input_buffer_2_3; + feature_reg_2_4_0 <= input_buffer_2_4; + feature_reg_2_5_0 <= input_buffer_2_5; + feature_reg_3_0_0 <= input_buffer_3_0; + feature_reg_3_1_0 <= input_buffer_3_1; + feature_reg_3_2_0 <= input_buffer_3_2; + feature_reg_3_3_0 <= input_buffer_3_3; + feature_reg_3_4_0 <= input_buffer_3_4; + feature_reg_3_5_0 <= input_buffer_3_5; + feature_reg_4_0_0 <= input_buffer_4_0; + feature_reg_4_1_0 <= input_buffer_4_1; + feature_reg_4_2_0 <= input_buffer_4_2; + feature_reg_4_3_0 <= input_buffer_4_3; + feature_reg_4_4_0 <= input_buffer_4_4; + feature_reg_4_5_0 <= input_buffer_4_5; + feature_reg_5_0_0 <= input_buffer_5_0; + feature_reg_5_1_0 <= input_buffer_5_1; + feature_reg_5_2_0 <= input_buffer_5_2; + feature_reg_5_3_0 <= input_buffer_5_3; + feature_reg_5_4_0 <= input_buffer_5_4; + feature_reg_5_5_0 <= input_buffer_5_5; + feature_reg_0_0_1 <= feature_reg_0_0_0; + feature_reg_0_1_1 <= feature_reg_0_1_0; + feature_reg_0_2_1 <= feature_reg_0_2_0; + feature_reg_0_3_1 <= feature_reg_0_3_0; + feature_reg_0_4_1 <= feature_reg_0_4_0; + feature_reg_0_5_1 <= feature_reg_0_5_0; + feature_reg_1_0_1 <= feature_reg_1_0_0; + feature_reg_1_1_1 <= feature_reg_1_1_0; + feature_reg_1_2_1 <= feature_reg_1_2_0; + feature_reg_1_3_1 <= feature_reg_1_3_0; + feature_reg_1_4_1 <= feature_reg_1_4_0; + feature_reg_1_5_1 <= feature_reg_1_5_0; + feature_reg_2_0_1 <= feature_reg_2_0_0; + feature_reg_2_1_1 <= feature_reg_2_1_0; + feature_reg_2_2_1 <= feature_reg_2_2_0; + feature_reg_2_3_1 <= feature_reg_2_3_0; + feature_reg_2_4_1 <= feature_reg_2_4_0; + feature_reg_2_5_1 <= feature_reg_2_5_0; + feature_reg_3_0_1 <= feature_reg_3_0_0; + feature_reg_3_1_1 <= feature_reg_3_1_0; + feature_reg_3_2_1 <= feature_reg_3_2_0; + feature_reg_3_3_1 <= feature_reg_3_3_0; + feature_reg_3_4_1 <= feature_reg_3_4_0; + feature_reg_3_5_1 <= feature_reg_3_5_0; + feature_reg_4_0_1 <= feature_reg_4_0_0; + feature_reg_4_1_1 <= feature_reg_4_1_0; + feature_reg_4_2_1 <= feature_reg_4_2_0; + feature_reg_4_3_1 <= feature_reg_4_3_0; + feature_reg_4_4_1 <= feature_reg_4_4_0; + feature_reg_4_5_1 <= feature_reg_4_5_0; + feature_reg_5_0_1 <= feature_reg_5_0_0; + feature_reg_5_1_1 <= feature_reg_5_1_0; + feature_reg_5_2_1 <= feature_reg_5_2_0; + feature_reg_5_3_1 <= feature_reg_5_3_0; + feature_reg_5_4_1 <= feature_reg_5_4_0; + feature_reg_5_5_1 <= feature_reg_5_5_0; + //Output Serializing logic + if (calculate_3) begin + output_buffer_0_0 <= rslt_buffer_0_0; + output_buffer_1_0 <= rslt_buffer_0_1; + output_buffer_2_0 <= rslt_buffer_0_2; + output_buffer_3_0 <= rslt_buffer_0_3; + output_buffer_4_0 <= rslt_buffer_0_4; + output_buffer_5_0 <= rslt_buffer_0_5; + output_buffer_0_1 <= rslt_buffer_1_0; + output_buffer_1_1 <= rslt_buffer_1_1; + output_buffer_2_1 <= rslt_buffer_1_2; + output_buffer_3_1 <= rslt_buffer_1_3; + output_buffer_4_1 <= rslt_buffer_1_4; + output_buffer_5_1 <= rslt_buffer_1_5; + output_buffer_0_2 <= rslt_buffer_2_0; + output_buffer_1_2 <= rslt_buffer_2_1; + output_buffer_2_2 <= rslt_buffer_2_2; + output_buffer_3_2 <= rslt_buffer_2_3; + output_buffer_4_2 <= rslt_buffer_2_4; + output_buffer_5_2 <= rslt_buffer_2_5; + output_buffer_0_3 <= rslt_buffer_3_0; + output_buffer_1_3 <= rslt_buffer_3_1; + output_buffer_2_3 <= rslt_buffer_3_2; + output_buffer_3_3 <= rslt_buffer_3_3; + output_buffer_4_3 <= rslt_buffer_3_4; + output_buffer_5_3 <= rslt_buffer_3_5; + output_buffer_0_4 <= rslt_buffer_4_0; + output_buffer_1_4 <= rslt_buffer_4_1; + output_buffer_2_4 <= rslt_buffer_4_2; + output_buffer_3_4 <= rslt_buffer_4_3; + output_buffer_4_4 <= rslt_buffer_4_4; + output_buffer_5_4 <= rslt_buffer_4_5; + output_buffer_0_5 <= rslt_buffer_5_0; + output_buffer_1_5 <= rslt_buffer_5_1; + output_buffer_2_5 <= rslt_buffer_5_2; + output_buffer_3_5 <= rslt_buffer_5_3; + output_buffer_4_5 <= rslt_buffer_5_4; + output_buffer_5_5 <= rslt_buffer_5_5; + end else begin + output_buffer_0_0 <= output_buffer_0_1; + output_buffer_0_1 <= output_buffer_0_2; + output_buffer_0_2 <= output_buffer_0_3; + output_buffer_0_3 <= output_buffer_0_4; + output_buffer_0_4 <= output_buffer_0_5; + output_buffer_1_0 <= output_buffer_1_1; + output_buffer_1_1 <= output_buffer_1_2; + output_buffer_1_2 <= output_buffer_1_3; + output_buffer_1_3 <= output_buffer_1_4; + output_buffer_1_4 <= output_buffer_1_5; + output_buffer_2_0 <= output_buffer_2_1; + output_buffer_2_1 <= output_buffer_2_2; + output_buffer_2_2 <= output_buffer_2_3; + output_buffer_2_3 <= output_buffer_2_4; + output_buffer_2_4 <= output_buffer_2_5; + output_buffer_3_0 <= output_buffer_3_1; + output_buffer_3_1 <= output_buffer_3_2; + output_buffer_3_2 <= output_buffer_3_3; + output_buffer_3_3 <= output_buffer_3_4; + output_buffer_3_4 <= output_buffer_3_5; + output_buffer_4_0 <= output_buffer_4_1; + output_buffer_4_1 <= output_buffer_4_2; + output_buffer_4_2 <= output_buffer_4_3; + output_buffer_4_3 <= output_buffer_4_4; + output_buffer_4_4 <= output_buffer_4_5; + output_buffer_5_0 <= output_buffer_5_1; + output_buffer_5_1 <= output_buffer_5_2; + output_buffer_5_2 <= output_buffer_5_3; + output_buffer_5_3 <= output_buffer_5_4; + output_buffer_5_4 <= output_buffer_5_5; + end +end + +////// FIRST COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD00 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_2), + .by(input_buffer_2_0), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_1_0), + .resultb(dsp_out_1_1) +); + +winograd_dsp_16 winograd_dsp_16_WD10 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_2_4), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_1_2), + .resultb(dsp_out_1_3) +); + +winograd_dsp_16 winograd_dsp_16_WD20 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_2), + .by(input_buffer_1_0), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_1_4), + .resultb(dsp_out_1_5) +); + +winograd_dsp_16 winograd_dsp_16_WD30 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_1_6), + .resultb(dsp_out_1_7) +); + +winograd_dsp_16 winograd_dsp_16_WD40 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_0), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_1_8), + .resultb(dsp_out_1_9) +); + +winograd_dsp_16 winograd_dsp_16_WD50 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_4), + .by(input_buffer_5_2), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_1_10), + .resultb(dsp_out_1_11) +); + +////// SECOND COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD01 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_0), + .resultb(dsp_out_2_1) +); + +winograd_dsp_16 winograd_dsp_16_WD11 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_2), + .resultb(dsp_out_2_3) +); + +winograd_dsp_16 winograd_dsp_16_WD21 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_4), + .resultb(dsp_out_2_5) +); + +winograd_dsp_16 winograd_dsp_16_WD31 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_6), + .resultb(dsp_out_2_7) +); + +////// THIRD COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD02 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_0), + .resultb(dsp_out_3_1) +); + +winograd_dsp_16 winograd_dsp_16_WD12 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_2), + .resultb(dsp_out_3_3) +); + +winograd_dsp_16 winograd_dsp_16_WD22 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_4), + .resultb(dsp_out_3_5) +); + +winograd_dsp_16 winograd_dsp_16_WD32 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_6), + .resultb(dsp_out_3_7) +); + +////// FOURTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD03 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_0), + .resultb(dsp_out_4_1) +); + +winograd_dsp_16 winograd_dsp_16_WD13 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_2), + .resultb(dsp_out_4_3) +); + +winograd_dsp_16 winograd_dsp_16_WD23 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_4), + .resultb(dsp_out_4_5) +); + +winograd_dsp_16 winograd_dsp_16_WD33 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_6), + .resultb(dsp_out_4_7) +); + +////// FIFTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD04 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_0), + .resultb(dsp_out_5_1) +); + +winograd_dsp_16 winograd_dsp_16_WD14 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_2), + .resultb(dsp_out_5_3) +); + +winograd_dsp_16 winograd_dsp_16_WD24 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_4), + .resultb(dsp_out_5_5) +); + +winograd_dsp_16 winograd_dsp_16_WD34 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_6), + .resultb(dsp_out_5_7) +); + +////// SIXTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD05 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_3), + .by(input_buffer_2_1), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_6_0), + .resultb(dsp_out_6_1) +); + +winograd_dsp_16 winograd_dsp_16_WD15 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_5), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_6_2), + .resultb(dsp_out_6_3) +); + +winograd_dsp_16 winograd_dsp_16_WD25 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_3), + .by(input_buffer_1_3), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_6_4), + .resultb(dsp_out_6_5) +); + +winograd_dsp_16 winograd_dsp_16_WD35 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_3_3), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_6_6), + .resultb(dsp_out_6_7) +); + +winograd_dsp_16 winograd_dsp_16_WD45 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_3), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_6_8), + .resultb(dsp_out_6_9) +); + +winograd_dsp_16 winograd_dsp_16_WD55 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_5), + .by(input_buffer_5_3), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_6_10), + .resultb(dsp_out_6_11) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA00 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_0_1[11:0], 4'b0000}), + .data1x(dsp_out_1_0), + .data2x({feature_reg_0_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_1), + .data4x(dsp_out_1_2), + .data5x(dsp_out_1_3), + .data6x({feature_reg_4_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_4), + .data8x(feature_reg_4_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_0) +); + +wire [15:0] f1, f2, f3, f4; +assign f1 = -{feature_reg_1_0_1[11:0], 4'b0000}; +assign f2 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f3 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f4 = -{feature_reg_2_4_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA10 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_1_5), + .data1x(f1), + .data2x(f2), + .data3x(f3), + .data4x(dsp_out_1_6), + .data5x(f4), + .data6x({feature_reg_3_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_7), + .data8x(feature_reg_3_4_1), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_0) +); + +wire [15:0] f5, f6, f7, f8, f9, f10; +assign f5 = -dsp_out_1_5; +assign f6 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f7 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f8 = -{feature_reg_3_0_1[13:0], 2'b00}; +assign f9 = -dsp_out_1_7; +assign f10 = -feature_reg_3_4_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA20 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f5), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(f6), + .data4x(dsp_out_1_6), + .data5x(f7), + .data6x(f8), + .data7x(f9), + .data8x(f10), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_0) +); + +wire [15:0] f11, f12, f13, f14, f15, f16, f17; +assign f11 = -{feature_reg_1_0_1[12:0], 3'b000}; +assign f12 = -{feature_reg_1_4_1[14:0], 1'b0}; +assign f13 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f14 = -feature_reg_2_4_1; +assign f15 = dsp_out_1_5 >>> 1; +assign f16 = dsp_out_1_6 >>> 2; +assign f17 = dsp_out_1_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA30 ( + .clock(clk), + .clken(calculate_2), + .data0x(f15), + .data1x(f11), + .data2x(f12), + .data3x(f13), + .data4x(f16), + .data5x(f14), + .data6x({feature_reg_3_0_1[12:0], 3'b000}), + .data7x(f17), + .data8x({feature_reg_3_4_1[14:0], 1'b0}), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_0) +); + +wire [15:0] f18, f19, f20, f21, f22, f23, f23b; +assign f18 = -(dsp_out_1_5 >>> 1); +assign f19 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f20 = -feature_reg_2_4_1; +assign f21 = -{feature_reg_3_0_1[12:0], 3'b000}; +assign f22 = -(dsp_out_1_7 <<< 1); +assign f23 = -{feature_reg_3_4_1[14:0], 1'b0}; +assign f23b = dsp_out_1_6 >>> 2; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA40 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[12:0], 3'b000}), + .data1x(f18), + .data2x({feature_reg_1_4_1[14:0], 1'b0}), + .data3x(f19), + .data4x(f23b), + .data5x(f20), + .data6x(f21), + .data7x(f22), + .data8x(f23), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_0) +); + +wire [15:0] f24; +assign f24 = -dsp_out_1_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA50 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f24), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_8), + .data4x(dsp_out_1_9), + .data5x(dsp_out_1_10), + .data6x({feature_reg_5_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_11), + .data8x(feature_reg_5_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_0) +); + +wire [15:0] f25, f26, f27, f28; +assign f25 = -{feature_reg_0_2_1[11:0], 4'b0000}; +assign f26 = -{feature_reg_0_1_1[11:0], 4'b0000}; +assign f27 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f28 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA01 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[13:0], 2'b00}), + .data1x(f25), + .data2x(f26), + .data3x({feature_reg_0_4_1[13:0], 2'b00}), + .data4x(dsp_out_2_0), + .data5x(dsp_out_2_1), + .data6x(dsp_out_2_2), + .data7x(dsp_out_2_3), + .data8x(f27), + .data9x(f28), + .data10x(feature_reg_4_3_1), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_1) +); + +wire [15:0] f29, f30, f31, f32, f33, f34, f35, f36; +assign f29 = -{feature_reg_1_3_1[13:0], 2'b00}; +assign f30 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f31 = -{feature_reg_2_3_1[13:0], 2'b00}; +assign f32 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f33 = -{feature_reg_3_1_1[13:0], 2'b00}; +assign f34 = -{feature_reg_3_2_1[13:0], 2'b00}; +assign f35 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f36 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA11 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0], 4'b0000}), + .data1x({feature_reg_1_2_1[11:0], 4'b0000}), + .data2x(f29), + .data3x(f30), + .data4x({feature_reg_2_1_1[11:0], 4'b0000}), + .data5x({feature_reg_2_2_1[11:0], 4'b0000}), + .data6x(f31), + .data7x(f32), + .data8x(f33), + .data9x(f34), + .data10x(feature_reg_3_3_1), + .data11x(feature_reg_3_4_1), + .data12x(f35), + .data13x(f36), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_1) +); + +wire [15:0] f37, f38, f39, f40, f41, f42, f43, f44; +assign f37 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f38 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f39 = -{feature_reg_2_3_1[13:0],2'b00}; +assign f40 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f41 = -feature_reg_3_3_1; +assign f42 = -feature_reg_3_4_1; +assign f43 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f44 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA21 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f37), + .data2x(f38), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[11:0],4'b0000}), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x(f39), + .data7x(f40), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(f41), + .data11x(f42), + .data12x(f43), + .data13x(f44), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_1) +); + +wire [15:0] f45, f46, f47, f48, f49, f50, f51, f52; +assign f45 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f46 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f47 = -feature_reg_2_3_1; +assign f48 = -feature_reg_2_4_1; +assign f49 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f50 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f51 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f52 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA31 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[12:0],3'b000}), + .data2x(f45), + .data3x(f46), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f47), + .data7x(f48), + .data8x(f49), + .data9x(f50), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f51), + .data13x(f52), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_1) +); + +wire [15:0] f53, f54, f55, f56, f57, f58, f59, f60; +assign f53 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f54 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f55 = -feature_reg_2_3_1; +assign f56 = -feature_reg_2_4_1; +assign f57 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f58 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f59 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f60 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA41 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[14:0],1'b0}), + .data1x(f53), + .data2x(f54), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f55), + .data7x(f56), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x(f57), + .data11x(f58), + .data12x(f59), + .data13x(f60), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_1) +); + +wire [15:0] f61, f62, f63, f64; +assign f61 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f62 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f63 = -{feature_reg_5_1_1[13:0],2'b00}; +assign f64 = -{feature_reg_5_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA51 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f61), + .data2x(f62), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_2_4), + .data5x(dsp_out_2_5), + .data6x(dsp_out_2_6), + .data7x(dsp_out_2_7), + .data8x(f63), + .data9x(f64), + .data10x(feature_reg_5_3_1), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_1) +); + +wire [15:0] f65, f66, f67, f68; +assign f65 = -{feature_reg_0_2_1[11:0],4'b0000}; +assign f66 = -{feature_reg_0_3_1[13:0],2'b00}; +assign f67 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f68 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA02 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(f65), + .data2x(f66), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_3_0), + .data5x(dsp_out_3_1), + .data6x(dsp_out_3_2), + .data7x(dsp_out_3_3), + .data8x({feature_reg_4_1_1[13:0],2'b00}), + .data9x(f67), + .data10x(f68), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_2) +); + +wire [15:0] f69, f70, f71, f72, f73, f74, f75, f76; +assign f69 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f70 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f71 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f72 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f73 = -{feature_reg_3_2_1[13:0],2'b00}; +assign f74 = -feature_reg_3_3_1; +assign f75 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f76 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA12 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[11:0],4'b0000}), + .data1x(f69), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f70), + .data4x(f71), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f72), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f73), + .data10x(f74), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f75), + .data14x(f76), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_2) +); + +wire [15:0] f77, f78, f79, f80, f81, f82, f83, f84; +assign f77 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f78 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f79 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f80 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f81 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f82 = -feature_reg_3_4_1; +assign f83 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f84 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA22 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f77), + .data2x(f78), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f79), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f80), + .data8x(f81), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(feature_reg_3_3_1), + .data11x(f82), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f83), + .data14x(f84), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_2) +); + +wire [15:0] f85, f86, f87, f88, f89, f90, f91, f92; +assign f85 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f86 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f87 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f88 = -feature_reg_2_4_1; +assign f89 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f90 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f91 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f92 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA32 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[12:0],3'b000}), + .data1x(f85), + .data2x({feature_reg_1_3_1[14:0],1'b0}), + .data3x(f86), + .data4x(f87), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f88), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x(f89), + .data10x(f90), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f91), + .data14x(f92), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_2) +); + +wire [15:0] f93, f94, f95, f96, f97, f98, f99, f100; +assign f93 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f94 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f95 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f96 = -feature_reg_2_4_1; +assign f97 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f98 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f99 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f100 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA42 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f93), + .data2x(f94), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f95), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f96), + .data8x(f97), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f98), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f99), + .data14x(f100), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_2) +); + +wire [15:0] f101, f102, f103, f104; +assign f101 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f102 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f103 = -{feature_reg_5_2_1[13:0],2'b00}; +assign f104 = -feature_reg_5_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA52 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f101), + .data2x(f102), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_3_4), + .data5x(dsp_out_3_5), + .data6x(dsp_out_3_6), + .data7x(dsp_out_3_7), + .data8x({feature_reg_5_1_1[13:0],2'b00}), + .data9x(f103), + .data10x(f104), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_2) +); + +wire [15:0] f105, f106, f107, f108; +assign f105 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f106 = -{feature_reg_0_1_1[12:0],3'b000}; +assign f107 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f108 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA03 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[12:0],3'b000}), + .data1x(f105), + .data2x(f106), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_4_0), + .data5x(dsp_out_4_1), + .data6x(dsp_out_4_2), + .data7x(dsp_out_4_3), + .data8x(f107), + .data9x(f108), + .data10x({feature_reg_4_3_1[14:0],1'b0}), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_3) +); + +wire [15:0] f109, f110, f111, f112, f113, f114, f115, f116; +assign f109 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f110 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f111 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f112 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f113 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f114 = -feature_reg_3_2_1; +assign f115 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f116 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA13 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[13:0],2'b00}), + .data2x(f109), + .data3x(f110), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f111), + .data7x(f112), + .data8x(f113), + .data9x(f114), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(feature_reg_3_4_1), + .data12x(f115), + .data13x(f116), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_3) +); + +wire [15:0] f117, f118, f119, f120, f121, f122, f123, f124; +assign f117 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f118 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f119 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f120 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f121 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f122 = -feature_reg_3_4_1; +assign f123 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f124 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA23 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f117), + .data2x(f118), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f119), + .data7x(f120), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(feature_reg_3_2_1), + .data10x(f121), + .data11x(f122), + .data12x(f123), + .data13x(f124), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_3) +); + +wire [15:0] f125, f126, f127, f128, f129, f130, f131, f132; +assign f125 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f126 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f127 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f128 = -feature_reg_2_4_1; +assign f129 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f130 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f131 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f132 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA33 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x({feature_reg_1_2_1[14:0],1'b0}), + .data2x(f125), + .data3x(f126), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f127), + .data7x(f128), + .data8x(f129), + .data9x(f130), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f131), + .data13x(f132), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_3) +); + +wire [15:0] f133, f134, f135, f136, f137, f138, f139, f140; +assign f133 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f134 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f135 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f136 = -feature_reg_2_4_1; +assign f137 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f138 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f139 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f140 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA43 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f133), + .data2x(f134), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f135), + .data7x(f136), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x(f137), + .data11x(f138), + .data12x(f139), + .data13x(f140), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_3) +); + +wire [15:0] f141, f142, f143, f144; +assign f141 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f142 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f143 = -{feature_reg_5_1_1[14:0],1'b0}; +assign f144 = -feature_reg_5_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA53 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f141), + .data2x(f142), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_4_4), + .data5x(dsp_out_4_5), + .data6x(dsp_out_4_6), + .data7x(dsp_out_4_7), + .data8x(f143), + .data9x(f144), + .data10x({feature_reg_5_3_1[14:0],1'b0}), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_3) +); + +wire [15:0] f145, f146, f147, f148; +assign f145 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f146 = -{feature_reg_0_3_1[12:0],3'b000}; +assign f147 = -feature_reg_4_2_1; +assign f148 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA04 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[12:0],3'b000}), + .data1x(f145), + .data2x(f146), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_5_0), + .data5x(dsp_out_5_1), + .data6x(dsp_out_5_2), + .data7x(dsp_out_5_3), + .data8x({feature_reg_4_1_1[14:0],1'b0}), + .data9x(f147), + .data10x(f148), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_4) +); + +wire [15:0] f149, f150, f151, f152, f153, f154, f155, f156; +assign f149 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f150 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f151 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f152 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f153 = -feature_reg_3_2_1; +assign f154 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f155 = -feature_reg_4_2_1; +assign f156 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA14 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[13:0],2'b00}), + .data1x(f149), + .data2x({feature_reg_1_3_1[12:0],3'b000}), + .data3x(f150), + .data4x(f151), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f152), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(f153), + .data10x(f154), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f155), + .data14x(f156), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_4) +); + +wire [15:0] f157, f158, f159, f160, f161, f162, f163, f164; +assign f157 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f158 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f159 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f160 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f161 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f162 = -feature_reg_3_4_1; +assign f163 = -feature_reg_4_2_1; +assign f164 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA24 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f157), + .data2x(f158), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f159), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f160), + .data8x(f161), + .data9x(feature_reg_3_2_1), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f162), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f163), + .data14x(f164), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_4) +); + +wire [15:0] f165, f166, f167, f168, f169, f170, f171, f172; +assign f165 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f166 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f167 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f168 = -feature_reg_2_4_1; +assign f169 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f170 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f171 = -feature_reg_4_2_1; +assign f172 = -{feature_reg_4_1_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA34 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[14:0],1'b0}), + .data1x(f165), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f166), + .data4x(f167), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f168), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f169), + .data10x(f170), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f171), + .data14x(f172), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_4) +); + +wire [15:0] f173, f174, f175, f176, f177, f178, f179, f180; +assign f173 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f174 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f175 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f176 = -feature_reg_2_4_1; +assign f177 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f178 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f179 = -feature_reg_4_2_1; +assign f180 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA44 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x(f173), + .data2x(f174), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f175), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f176), + .data8x(f177), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x(f178), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f179), + .data14x(f180), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_4) +); + +wire [15:0] f181, f182, f183, f184; +assign f181 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f182 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f183 = -feature_reg_5_2_1; +assign f184 = -{feature_reg_5_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA54 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f181), + .data2x(f182), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_5_4), + .data5x(dsp_out_5_5), + .data6x(dsp_out_5_6), + .data7x(dsp_out_5_7), + .data8x({feature_reg_5_1_1[14:0],1'b0}), + .data9x(f183), + .data10x(f184), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_4) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA05 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(dsp_out_6_0), + .data2x({feature_reg_0_5_1[13:0],2'b00}), + .data3x(dsp_out_6_1), + .data4x(dsp_out_6_2), + .data5x(dsp_out_6_3), + .data6x({feature_reg_4_1_1[13:0],2'b00}), + .data7x(dsp_out_6_4), + .data8x(feature_reg_4_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_5) +); + +wire [15:0] f185, f186, f187, f188; +assign f185 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f186 = -{feature_reg_1_5_1[13:0],2'b00}; +assign f187 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f188 = -{feature_reg_2_5_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA15 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_6_5), + .data1x(f185), + .data2x(f186), + .data3x(f187), + .data4x(dsp_out_6_6), + .data5x(f188), + .data6x({feature_reg_3_1_1[13:0],2'b00}), + .data7x(dsp_out_6_7), + .data8x(feature_reg_3_5_1), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_5) +); + +wire [15:0] f189, f190, f191, f192, f193, f194; +assign f189 = -dsp_out_6_5; +assign f190 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f191 = -{feature_reg_2_5_1[13:0],2'b00}; +assign f192 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f193 = -dsp_out_6_7; +assign f194 = -feature_reg_3_5_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA25 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f189), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(f190), + .data4x(dsp_out_6_6), + .data5x(f191), + .data6x(f192), + .data7x(f193), + .data8x(f194), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_5) +); + +wire [15:0] f195, f196, f197, f198, f199, f200, f201; +assign f195 = dsp_out_6_5 >>> 1; +assign f196 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f197 = -{feature_reg_1_5_1[14:0],1'b0}; +assign f198 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f199 = dsp_out_6_6 >>> 2; +assign f200 = -feature_reg_2_5_1; +assign f201 = dsp_out_6_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA35 ( + .clock(clk), + .clken(calculate_2), + .data0x(f195), + .data1x(f196), + .data2x(f197), + .data3x(f198), + .data4x(f199), + .data5x(f200), + .data6x({feature_reg_3_1_1[12:0],3'b000}), + .data7x(f201), + .data8x({feature_reg_3_5_1[14:0],1'b0}), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_5) +); + +wire [15:0] f202, f203, f204, f205, f206, f207, f208; +assign f202 = -(dsp_out_6_5 >>> 1); +assign f203 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f204 = dsp_out_6_6 >>> 2; +assign f205 = -feature_reg_2_5_1; +assign f206 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f207 = -(dsp_out_6_7 <<< 1); +assign f208 = -{feature_reg_3_5_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA45 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f202), + .data2x({feature_reg_1_5_1[14:0],1'b0}), + .data3x(f203), + .data4x(f204), + .data5x(f205), + .data6x(f206), + .data7x(f207), + .data8x(f208), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_5) +); + +wire [15:0] f209; +assign f209 = -dsp_out_6_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA55 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f209), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(dsp_out_6_8), + .data4x(dsp_out_6_9), + .data5x(dsp_out_6_10), + .data6x({feature_reg_5_1_1[13:0],2'b00}), + .data7x(dsp_out_6_11), + .data8x(feature_reg_5_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_5) +); + +assign o_feature_0 = output_buffer_0_0[15:0]; +assign o_feature_1 = output_buffer_1_0[15:0]; +assign o_feature_2 = output_buffer_2_0[15:0]; +assign o_feature_3 = output_buffer_3_0[15:0]; +assign o_feature_4 = output_buffer_4_0[15:0]; +assign o_feature_5 = output_buffer_5_0[15:0]; +assign o_valid = valid_9; + +endmodule + +module winograd_transform_0 ( + input clk, + input i_valid, + input [15:0] i_result_0_0, + input [15:0] i_result_0_1, + input [15:0] i_result_0_2, + input [15:0] i_result_0_3, + input [15:0] i_result_0_4, + input [15:0] i_result_0_5, + input [15:0] i_result_0_6, + input [15:0] i_result_0_7, + input [15:0] i_result_1_0, + input [15:0] i_result_1_1, + input [15:0] i_result_1_2, + input [15:0] i_result_1_3, + input [15:0] i_result_1_4, + input [15:0] i_result_1_5, + input [15:0] i_result_1_6, + input [15:0] i_result_1_7, + input [15:0] i_result_2_0, + input [15:0] i_result_2_1, + input [15:0] i_result_2_2, + input [15:0] i_result_2_3, + input [15:0] i_result_2_4, + input [15:0] i_result_2_5, + input [15:0] i_result_2_6, + input [15:0] i_result_2_7, + input [15:0] i_result_3_0, + input [15:0] i_result_3_1, + input [15:0] i_result_3_2, + input [15:0] i_result_3_3, + input [15:0] i_result_3_4, + input [15:0] i_result_3_5, + input [15:0] i_result_3_6, + input [15:0] i_result_3_7, + input [15:0] i_result_4_0, + input [15:0] i_result_4_1, + input [15:0] i_result_4_2, + input [15:0] i_result_4_3, + input [15:0] i_result_4_4, + input [15:0] i_result_4_5, + input [15:0] i_result_4_6, + input [15:0] i_result_4_7, + input [15:0] i_result_5_0, + input [15:0] i_result_5_1, + input [15:0] i_result_5_2, + input [15:0] i_result_5_3, + input [15:0] i_result_5_4, + input [15:0] i_result_5_5, + input [15:0] i_result_5_6, + input [15:0] i_result_5_7, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output [15:0] o_feature_2, + output [15:0] o_feature_3, + output [15:0] o_feature_4, + output [15:0] o_feature_5, + output o_valid +); + +reg [15:0] input_buffer_0_0; +reg [19:0] output_buffer_0_0; +wire [19:0] rslt_buffer_0_0; +reg [15:0] input_buffer_0_1; +reg [19:0] output_buffer_0_1; +wire [19:0] rslt_buffer_0_1; +reg [15:0] input_buffer_0_2; +reg [19:0] output_buffer_0_2; +wire [19:0] rslt_buffer_0_2; +reg [15:0] input_buffer_0_3; +reg [19:0] output_buffer_0_3; +wire [19:0] rslt_buffer_0_3; +reg [15:0] input_buffer_0_4; +reg [19:0] output_buffer_0_4; +wire [19:0] rslt_buffer_0_4; +reg [15:0] input_buffer_0_5; +reg [19:0] output_buffer_0_5; +wire [19:0] rslt_buffer_0_5; +reg [15:0] input_buffer_1_0; +reg [19:0] output_buffer_1_0; +wire [19:0] rslt_buffer_1_0; +reg [15:0] input_buffer_1_1; +reg [19:0] output_buffer_1_1; +wire [19:0] rslt_buffer_1_1; +reg [15:0] input_buffer_1_2; +reg [19:0] output_buffer_1_2; +wire [19:0] rslt_buffer_1_2; +reg [15:0] input_buffer_1_3; +reg [19:0] output_buffer_1_3; +wire [19:0] rslt_buffer_1_3; +reg [15:0] input_buffer_1_4; +reg [19:0] output_buffer_1_4; +wire [19:0] rslt_buffer_1_4; +reg [15:0] input_buffer_1_5; +reg [19:0] output_buffer_1_5; +wire [19:0] rslt_buffer_1_5; +reg [15:0] input_buffer_2_0; +reg [19:0] output_buffer_2_0; +wire [19:0] rslt_buffer_2_0; +reg [15:0] input_buffer_2_1; +reg [19:0] output_buffer_2_1; +wire [19:0] rslt_buffer_2_1; +reg [15:0] input_buffer_2_2; +reg [19:0] output_buffer_2_2; +wire [19:0] rslt_buffer_2_2; +reg [15:0] input_buffer_2_3; +reg [19:0] output_buffer_2_3; +wire [19:0] rslt_buffer_2_3; +reg [15:0] input_buffer_2_4; +reg [19:0] output_buffer_2_4; +wire [19:0] rslt_buffer_2_4; +reg [15:0] input_buffer_2_5; +reg [19:0] output_buffer_2_5; +wire [19:0] rslt_buffer_2_5; +reg [15:0] input_buffer_3_0; +reg [19:0] output_buffer_3_0; +wire [19:0] rslt_buffer_3_0; +reg [15:0] input_buffer_3_1; +reg [19:0] output_buffer_3_1; +wire [19:0] rslt_buffer_3_1; +reg [15:0] input_buffer_3_2; +reg [19:0] output_buffer_3_2; +wire [19:0] rslt_buffer_3_2; +reg [15:0] input_buffer_3_3; +reg [19:0] output_buffer_3_3; +wire [19:0] rslt_buffer_3_3; +reg [15:0] input_buffer_3_4; +reg [19:0] output_buffer_3_4; +wire [19:0] rslt_buffer_3_4; +reg [15:0] input_buffer_3_5; +reg [19:0] output_buffer_3_5; +wire [19:0] rslt_buffer_3_5; +reg [15:0] input_buffer_4_0; +reg [19:0] output_buffer_4_0; +wire [19:0] rslt_buffer_4_0; +reg [15:0] input_buffer_4_1; +reg [19:0] output_buffer_4_1; +wire [19:0] rslt_buffer_4_1; +reg [15:0] input_buffer_4_2; +reg [19:0] output_buffer_4_2; +wire [19:0] rslt_buffer_4_2; +reg [15:0] input_buffer_4_3; +reg [19:0] output_buffer_4_3; +wire [19:0] rslt_buffer_4_3; +reg [15:0] input_buffer_4_4; +reg [19:0] output_buffer_4_4; +wire [19:0] rslt_buffer_4_4; +reg [15:0] input_buffer_4_5; +reg [19:0] output_buffer_4_5; +wire [19:0] rslt_buffer_4_5; +reg [15:0] input_buffer_5_0; +reg [19:0] output_buffer_5_0; +wire [19:0] rslt_buffer_5_0; +reg [15:0] input_buffer_5_1; +reg [19:0] output_buffer_5_1; +wire [19:0] rslt_buffer_5_1; +reg [15:0] input_buffer_5_2; +reg [19:0] output_buffer_5_2; +wire [19:0] rslt_buffer_5_2; +reg [15:0] input_buffer_5_3; +reg [19:0] output_buffer_5_3; +wire [19:0] rslt_buffer_5_3; +reg [15:0] input_buffer_5_4; +reg [19:0] output_buffer_5_4; +wire [19:0] rslt_buffer_5_4; +reg [15:0] input_buffer_5_5; +reg [19:0] output_buffer_5_5; +wire [19:0] rslt_buffer_5_5; +reg calculate, calculate_1, calculate_2, calculate_3; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg valid_12; +reg [2:0] input_buffer_count; +wire [15:0] dsp_out_1_0; +wire [15:0] dsp_out_1_1; +wire [15:0] dsp_out_1_2; +wire [15:0] dsp_out_1_3; +wire [15:0] dsp_out_1_4; +wire [15:0] dsp_out_1_5; +wire [15:0] dsp_out_1_6; +wire [15:0] dsp_out_1_7; +wire [15:0] dsp_out_1_8; +wire [15:0] dsp_out_1_9; +wire [15:0] dsp_out_1_10; +wire [15:0] dsp_out_1_11; +wire [15:0] dsp_out_2_0; +wire [15:0] dsp_out_2_1; +wire [15:0] dsp_out_2_2; +wire [15:0] dsp_out_2_3; +wire [15:0] dsp_out_2_4; +wire [15:0] dsp_out_2_5; +wire [15:0] dsp_out_2_6; +wire [15:0] dsp_out_2_7; +wire [15:0] dsp_out_3_0; +wire [15:0] dsp_out_3_1; +wire [15:0] dsp_out_3_2; +wire [15:0] dsp_out_3_3; +wire [15:0] dsp_out_3_4; +wire [15:0] dsp_out_3_5; +wire [15:0] dsp_out_3_6; +wire [15:0] dsp_out_3_7; +wire [15:0] dsp_out_4_0; +wire [15:0] dsp_out_4_1; +wire [15:0] dsp_out_4_2; +wire [15:0] dsp_out_4_3; +wire [15:0] dsp_out_4_4; +wire [15:0] dsp_out_4_5; +wire [15:0] dsp_out_4_6; +wire [15:0] dsp_out_4_7; +wire [15:0] dsp_out_5_0; +wire [15:0] dsp_out_5_1; +wire [15:0] dsp_out_5_2; +wire [15:0] dsp_out_5_3; +wire [15:0] dsp_out_5_4; +wire [15:0] dsp_out_5_5; +wire [15:0] dsp_out_5_6; +wire [15:0] dsp_out_5_7; +wire [15:0] dsp_out_6_0; +wire [15:0] dsp_out_6_1; +wire [15:0] dsp_out_6_2; +wire [15:0] dsp_out_6_3; +wire [15:0] dsp_out_6_4; +wire [15:0] dsp_out_6_5; +wire [15:0] dsp_out_6_6; +wire [15:0] dsp_out_6_7; +wire [15:0] dsp_out_6_8; +wire [15:0] dsp_out_6_9; +wire [15:0] dsp_out_6_10; +wire [15:0] dsp_out_6_11; +reg [15:0] feature_reg_0_0_0; +reg [15:0] feature_reg_0_0_1; +reg [15:0] feature_reg_0_1_0; +reg [15:0] feature_reg_0_1_1; +reg [15:0] feature_reg_0_2_0; +reg [15:0] feature_reg_0_2_1; +reg [15:0] feature_reg_0_3_0; +reg [15:0] feature_reg_0_3_1; +reg [15:0] feature_reg_0_4_0; +reg [15:0] feature_reg_0_4_1; +reg [15:0] feature_reg_0_5_0; +reg [15:0] feature_reg_0_5_1; +reg [15:0] feature_reg_1_0_0; +reg [15:0] feature_reg_1_0_1; +reg [15:0] feature_reg_1_1_0; +reg [15:0] feature_reg_1_1_1; +reg [15:0] feature_reg_1_2_0; +reg [15:0] feature_reg_1_2_1; +reg [15:0] feature_reg_1_3_0; +reg [15:0] feature_reg_1_3_1; +reg [15:0] feature_reg_1_4_0; +reg [15:0] feature_reg_1_4_1; +reg [15:0] feature_reg_1_5_0; +reg [15:0] feature_reg_1_5_1; +reg [15:0] feature_reg_2_0_0; +reg [15:0] feature_reg_2_0_1; +reg [15:0] feature_reg_2_1_0; +reg [15:0] feature_reg_2_1_1; +reg [15:0] feature_reg_2_2_0; +reg [15:0] feature_reg_2_2_1; +reg [15:0] feature_reg_2_3_0; +reg [15:0] feature_reg_2_3_1; +reg [15:0] feature_reg_2_4_0; +reg [15:0] feature_reg_2_4_1; +reg [15:0] feature_reg_2_5_0; +reg [15:0] feature_reg_2_5_1; +reg [15:0] feature_reg_3_0_0; +reg [15:0] feature_reg_3_0_1; +reg [15:0] feature_reg_3_1_0; +reg [15:0] feature_reg_3_1_1; +reg [15:0] feature_reg_3_2_0; +reg [15:0] feature_reg_3_2_1; +reg [15:0] feature_reg_3_3_0; +reg [15:0] feature_reg_3_3_1; +reg [15:0] feature_reg_3_4_0; +reg [15:0] feature_reg_3_4_1; +reg [15:0] feature_reg_3_5_0; +reg [15:0] feature_reg_3_5_1; +reg [15:0] feature_reg_4_0_0; +reg [15:0] feature_reg_4_0_1; +reg [15:0] feature_reg_4_1_0; +reg [15:0] feature_reg_4_1_1; +reg [15:0] feature_reg_4_2_0; +reg [15:0] feature_reg_4_2_1; +reg [15:0] feature_reg_4_3_0; +reg [15:0] feature_reg_4_3_1; +reg [15:0] feature_reg_4_4_0; +reg [15:0] feature_reg_4_4_1; +reg [15:0] feature_reg_4_5_0; +reg [15:0] feature_reg_4_5_1; +reg [15:0] feature_reg_5_0_0; +reg [15:0] feature_reg_5_0_1; +reg [15:0] feature_reg_5_1_0; +reg [15:0] feature_reg_5_1_1; +reg [15:0] feature_reg_5_2_0; +reg [15:0] feature_reg_5_2_1; +reg [15:0] feature_reg_5_3_0; +reg [15:0] feature_reg_5_3_1; +reg [15:0] feature_reg_5_4_0; +reg [15:0] feature_reg_5_4_1; +reg [15:0] feature_reg_5_5_0; +reg [15:0] feature_reg_5_5_1; + +always @ (posedge clk) begin + calculate_1 <= calculate; + calculate_2 <= calculate_1; + calculate_3 <= calculate_2; + //Valid pipeline + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + valid_12 <= valid_11; + if (i_valid) begin + input_buffer_count <= 0; + calculate <= 0; + end else begin + //Input buffering logic + if (input_buffer_count == 5) begin + calculate <= 1; + input_buffer_count <= 0; + end else begin + calculate <= 0; + input_buffer_count <= input_buffer_count + 1'b1; + end + input_buffer_5_0 <= i_result_0_0; + input_buffer_5_1 <= i_result_1_0; + input_buffer_5_2 <= i_result_2_0; + input_buffer_5_3 <= i_result_3_0; + input_buffer_5_4 <= i_result_4_0; + input_buffer_5_5 <= i_result_5_0; + end + input_buffer_0_0 <= input_buffer_1_0; + input_buffer_0_1 <= input_buffer_1_1; + input_buffer_0_2 <= input_buffer_1_2; + input_buffer_0_3 <= input_buffer_1_3; + input_buffer_0_4 <= input_buffer_1_4; + input_buffer_0_5 <= input_buffer_1_5; + input_buffer_1_0 <= input_buffer_2_0; + input_buffer_1_1 <= input_buffer_2_1; + input_buffer_1_2 <= input_buffer_2_2; + input_buffer_1_3 <= input_buffer_2_3; + input_buffer_1_4 <= input_buffer_2_4; + input_buffer_1_5 <= input_buffer_2_5; + input_buffer_2_0 <= input_buffer_3_0; + input_buffer_2_1 <= input_buffer_3_1; + input_buffer_2_2 <= input_buffer_3_2; + input_buffer_2_3 <= input_buffer_3_3; + input_buffer_2_4 <= input_buffer_3_4; + input_buffer_2_5 <= input_buffer_3_5; + input_buffer_3_0 <= input_buffer_4_0; + input_buffer_3_1 <= input_buffer_4_1; + input_buffer_3_2 <= input_buffer_4_2; + input_buffer_3_3 <= input_buffer_4_3; + input_buffer_3_4 <= input_buffer_4_4; + input_buffer_3_5 <= input_buffer_4_5; + input_buffer_4_0 <= input_buffer_5_0; + input_buffer_4_1 <= input_buffer_5_1; + input_buffer_4_2 <= input_buffer_5_2; + input_buffer_4_3 <= input_buffer_5_3; + input_buffer_4_4 <= input_buffer_5_4; + input_buffer_4_5 <= input_buffer_5_5; + //Pipelining to synchronize DSPs and non-DSPs + feature_reg_0_0_0 <= input_buffer_0_0; + feature_reg_0_1_0 <= input_buffer_0_1; + feature_reg_0_2_0 <= input_buffer_0_2; + feature_reg_0_3_0 <= input_buffer_0_3; + feature_reg_0_4_0 <= input_buffer_0_4; + feature_reg_0_5_0 <= input_buffer_0_5; + feature_reg_1_0_0 <= input_buffer_1_0; + feature_reg_1_1_0 <= input_buffer_1_1; + feature_reg_1_2_0 <= input_buffer_1_2; + feature_reg_1_3_0 <= input_buffer_1_3; + feature_reg_1_4_0 <= input_buffer_1_4; + feature_reg_1_5_0 <= input_buffer_1_5; + feature_reg_2_0_0 <= input_buffer_2_0; + feature_reg_2_1_0 <= input_buffer_2_1; + feature_reg_2_2_0 <= input_buffer_2_2; + feature_reg_2_3_0 <= input_buffer_2_3; + feature_reg_2_4_0 <= input_buffer_2_4; + feature_reg_2_5_0 <= input_buffer_2_5; + feature_reg_3_0_0 <= input_buffer_3_0; + feature_reg_3_1_0 <= input_buffer_3_1; + feature_reg_3_2_0 <= input_buffer_3_2; + feature_reg_3_3_0 <= input_buffer_3_3; + feature_reg_3_4_0 <= input_buffer_3_4; + feature_reg_3_5_0 <= input_buffer_3_5; + feature_reg_4_0_0 <= input_buffer_4_0; + feature_reg_4_1_0 <= input_buffer_4_1; + feature_reg_4_2_0 <= input_buffer_4_2; + feature_reg_4_3_0 <= input_buffer_4_3; + feature_reg_4_4_0 <= input_buffer_4_4; + feature_reg_4_5_0 <= input_buffer_4_5; + feature_reg_5_0_0 <= input_buffer_5_0; + feature_reg_5_1_0 <= input_buffer_5_1; + feature_reg_5_2_0 <= input_buffer_5_2; + feature_reg_5_3_0 <= input_buffer_5_3; + feature_reg_5_4_0 <= input_buffer_5_4; + feature_reg_5_5_0 <= input_buffer_5_5; + feature_reg_0_0_1 <= feature_reg_0_0_0; + feature_reg_0_1_1 <= feature_reg_0_1_0; + feature_reg_0_2_1 <= feature_reg_0_2_0; + feature_reg_0_3_1 <= feature_reg_0_3_0; + feature_reg_0_4_1 <= feature_reg_0_4_0; + feature_reg_0_5_1 <= feature_reg_0_5_0; + feature_reg_1_0_1 <= feature_reg_1_0_0; + feature_reg_1_1_1 <= feature_reg_1_1_0; + feature_reg_1_2_1 <= feature_reg_1_2_0; + feature_reg_1_3_1 <= feature_reg_1_3_0; + feature_reg_1_4_1 <= feature_reg_1_4_0; + feature_reg_1_5_1 <= feature_reg_1_5_0; + feature_reg_2_0_1 <= feature_reg_2_0_0; + feature_reg_2_1_1 <= feature_reg_2_1_0; + feature_reg_2_2_1 <= feature_reg_2_2_0; + feature_reg_2_3_1 <= feature_reg_2_3_0; + feature_reg_2_4_1 <= feature_reg_2_4_0; + feature_reg_2_5_1 <= feature_reg_2_5_0; + feature_reg_3_0_1 <= feature_reg_3_0_0; + feature_reg_3_1_1 <= feature_reg_3_1_0; + feature_reg_3_2_1 <= feature_reg_3_2_0; + feature_reg_3_3_1 <= feature_reg_3_3_0; + feature_reg_3_4_1 <= feature_reg_3_4_0; + feature_reg_3_5_1 <= feature_reg_3_5_0; + feature_reg_4_0_1 <= feature_reg_4_0_0; + feature_reg_4_1_1 <= feature_reg_4_1_0; + feature_reg_4_2_1 <= feature_reg_4_2_0; + feature_reg_4_3_1 <= feature_reg_4_3_0; + feature_reg_4_4_1 <= feature_reg_4_4_0; + feature_reg_4_5_1 <= feature_reg_4_5_0; + feature_reg_5_0_1 <= feature_reg_5_0_0; + feature_reg_5_1_1 <= feature_reg_5_1_0; + feature_reg_5_2_1 <= feature_reg_5_2_0; + feature_reg_5_3_1 <= feature_reg_5_3_0; + feature_reg_5_4_1 <= feature_reg_5_4_0; + feature_reg_5_5_1 <= feature_reg_5_5_0; + //Output Serializing logic + if (calculate_3) begin + output_buffer_0_0 <= rslt_buffer_0_0; + output_buffer_1_0 <= rslt_buffer_0_1; + output_buffer_2_0 <= rslt_buffer_0_2; + output_buffer_3_0 <= rslt_buffer_0_3; + output_buffer_4_0 <= rslt_buffer_0_4; + output_buffer_5_0 <= rslt_buffer_0_5; + output_buffer_0_1 <= rslt_buffer_1_0; + output_buffer_1_1 <= rslt_buffer_1_1; + output_buffer_2_1 <= rslt_buffer_1_2; + output_buffer_3_1 <= rslt_buffer_1_3; + output_buffer_4_1 <= rslt_buffer_1_4; + output_buffer_5_1 <= rslt_buffer_1_5; + output_buffer_0_2 <= rslt_buffer_2_0; + output_buffer_1_2 <= rslt_buffer_2_1; + output_buffer_2_2 <= rslt_buffer_2_2; + output_buffer_3_2 <= rslt_buffer_2_3; + output_buffer_4_2 <= rslt_buffer_2_4; + output_buffer_5_2 <= rslt_buffer_2_5; + output_buffer_0_3 <= rslt_buffer_3_0; + output_buffer_1_3 <= rslt_buffer_3_1; + output_buffer_2_3 <= rslt_buffer_3_2; + output_buffer_3_3 <= rslt_buffer_3_3; + output_buffer_4_3 <= rslt_buffer_3_4; + output_buffer_5_3 <= rslt_buffer_3_5; + output_buffer_0_4 <= rslt_buffer_4_0; + output_buffer_1_4 <= rslt_buffer_4_1; + output_buffer_2_4 <= rslt_buffer_4_2; + output_buffer_3_4 <= rslt_buffer_4_3; + output_buffer_4_4 <= rslt_buffer_4_4; + output_buffer_5_4 <= rslt_buffer_4_5; + output_buffer_0_5 <= rslt_buffer_5_0; + output_buffer_1_5 <= rslt_buffer_5_1; + output_buffer_2_5 <= rslt_buffer_5_2; + output_buffer_3_5 <= rslt_buffer_5_3; + output_buffer_4_5 <= rslt_buffer_5_4; + output_buffer_5_5 <= rslt_buffer_5_5; + end else begin + output_buffer_0_0 <= output_buffer_0_1; + output_buffer_0_1 <= output_buffer_0_2; + output_buffer_0_2 <= output_buffer_0_3; + output_buffer_0_3 <= output_buffer_0_4; + output_buffer_0_4 <= output_buffer_0_5; + output_buffer_1_0 <= output_buffer_1_1; + output_buffer_1_1 <= output_buffer_1_2; + output_buffer_1_2 <= output_buffer_1_3; + output_buffer_1_3 <= output_buffer_1_4; + output_buffer_1_4 <= output_buffer_1_5; + output_buffer_2_0 <= output_buffer_2_1; + output_buffer_2_1 <= output_buffer_2_2; + output_buffer_2_2 <= output_buffer_2_3; + output_buffer_2_3 <= output_buffer_2_4; + output_buffer_2_4 <= output_buffer_2_5; + output_buffer_3_0 <= output_buffer_3_1; + output_buffer_3_1 <= output_buffer_3_2; + output_buffer_3_2 <= output_buffer_3_3; + output_buffer_3_3 <= output_buffer_3_4; + output_buffer_3_4 <= output_buffer_3_5; + output_buffer_4_0 <= output_buffer_4_1; + output_buffer_4_1 <= output_buffer_4_2; + output_buffer_4_2 <= output_buffer_4_3; + output_buffer_4_3 <= output_buffer_4_4; + output_buffer_4_4 <= output_buffer_4_5; + output_buffer_5_0 <= output_buffer_5_1; + output_buffer_5_1 <= output_buffer_5_2; + output_buffer_5_2 <= output_buffer_5_3; + output_buffer_5_3 <= output_buffer_5_4; + output_buffer_5_4 <= output_buffer_5_5; + end +end + +////// FIRST COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD00 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_2), + .by(input_buffer_2_0), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_1_0), + .resultb(dsp_out_1_1) +); + +winograd_dsp_16 winograd_dsp_16_WD10 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_2_4), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_1_2), + .resultb(dsp_out_1_3) +); + +winograd_dsp_16 winograd_dsp_16_WD20 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_2), + .by(input_buffer_1_0), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_1_4), + .resultb(dsp_out_1_5) +); + +winograd_dsp_16 winograd_dsp_16_WD30 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_1_6), + .resultb(dsp_out_1_7) +); + +winograd_dsp_16 winograd_dsp_16_WD40 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_0), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_1_8), + .resultb(dsp_out_1_9) +); + +winograd_dsp_16 winograd_dsp_16_WD50 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_4), + .by(input_buffer_5_2), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_1_10), + .resultb(dsp_out_1_11) +); + +////// SECOND COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD01 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_0), + .resultb(dsp_out_2_1) +); + +winograd_dsp_16 winograd_dsp_16_WD11 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_2), + .resultb(dsp_out_2_3) +); + +winograd_dsp_16 winograd_dsp_16_WD21 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_4), + .resultb(dsp_out_2_5) +); + +winograd_dsp_16 winograd_dsp_16_WD31 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_6), + .resultb(dsp_out_2_7) +); + +////// THIRD COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD02 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_0), + .resultb(dsp_out_3_1) +); + +winograd_dsp_16 winograd_dsp_16_WD12 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_2), + .resultb(dsp_out_3_3) +); + +winograd_dsp_16 winograd_dsp_16_WD22 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_4), + .resultb(dsp_out_3_5) +); + +winograd_dsp_16 winograd_dsp_16_WD32 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_6), + .resultb(dsp_out_3_7) +); + +////// FOURTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD03 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_0), + .resultb(dsp_out_4_1) +); + +winograd_dsp_16 winograd_dsp_16_WD13 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_2), + .resultb(dsp_out_4_3) +); + +winograd_dsp_16 winograd_dsp_16_WD23 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_4), + .resultb(dsp_out_4_5) +); + +winograd_dsp_16 winograd_dsp_16_WD33 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_6), + .resultb(dsp_out_4_7) +); + +////// FIFTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD04 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_0), + .resultb(dsp_out_5_1) +); + +winograd_dsp_16 winograd_dsp_16_WD14 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_2), + .resultb(dsp_out_5_3) +); + +winograd_dsp_16 winograd_dsp_16_WD24 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_4), + .resultb(dsp_out_5_5) +); + +winograd_dsp_16 winograd_dsp_16_WD34 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_6), + .resultb(dsp_out_5_7) +); + +////// SIXTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD05 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_3), + .by(input_buffer_2_1), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_6_0), + .resultb(dsp_out_6_1) +); + +winograd_dsp_16 winograd_dsp_16_WD15 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_5), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_6_2), + .resultb(dsp_out_6_3) +); + +winograd_dsp_16 winograd_dsp_16_WD25 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_3), + .by(input_buffer_1_3), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_6_4), + .resultb(dsp_out_6_5) +); + +winograd_dsp_16 winograd_dsp_16_WD35 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_3_3), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_6_6), + .resultb(dsp_out_6_7) +); + +winograd_dsp_16 winograd_dsp_16_WD45 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_3), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_6_8), + .resultb(dsp_out_6_9) +); + +winograd_dsp_16 winograd_dsp_16_WD55 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_5), + .by(input_buffer_5_3), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_6_10), + .resultb(dsp_out_6_11) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA00 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_0_1[11:0], 4'b0000}), + .data1x(dsp_out_1_0), + .data2x({feature_reg_0_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_1), + .data4x(dsp_out_1_2), + .data5x(dsp_out_1_3), + .data6x({feature_reg_4_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_4), + .data8x(feature_reg_4_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_0) +); + +wire [15:0] f1, f2, f3, f4; +assign f1 = -{feature_reg_1_0_1[11:0], 4'b0000}; +assign f2 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f3 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f4 = -{feature_reg_2_4_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA10 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_1_5), + .data1x(f1), + .data2x(f2), + .data3x(f3), + .data4x(dsp_out_1_6), + .data5x(f4), + .data6x({feature_reg_3_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_7), + .data8x(feature_reg_3_4_1), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_0) +); + +wire [15:0] f5, f6, f7, f8, f9, f10; +assign f5 = -dsp_out_1_5; +assign f6 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f7 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f8 = -{feature_reg_3_0_1[13:0], 2'b00}; +assign f9 = -dsp_out_1_7; +assign f10 = -feature_reg_3_4_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA20 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f5), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(f6), + .data4x(dsp_out_1_6), + .data5x(f7), + .data6x(f8), + .data7x(f9), + .data8x(f10), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_0) +); + +wire [15:0] f11, f12, f13, f14, f15, f16, f17; +assign f11 = -{feature_reg_1_0_1[12:0], 3'b000}; +assign f12 = -{feature_reg_1_4_1[14:0], 1'b0}; +assign f13 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f14 = -feature_reg_2_4_1; +assign f15 = dsp_out_1_5 >>> 1; +assign f16 = dsp_out_1_6 >>> 2; +assign f17 = dsp_out_1_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA30 ( + .clock(clk), + .clken(calculate_2), + .data0x(f15), + .data1x(f11), + .data2x(f12), + .data3x(f13), + .data4x(f16), + .data5x(f14), + .data6x({feature_reg_3_0_1[12:0], 3'b000}), + .data7x(f17), + .data8x({feature_reg_3_4_1[14:0], 1'b0}), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_0) +); + +wire [15:0] f18, f19, f20, f21, f22, f23, f23b; +assign f18 = -(dsp_out_1_5 >>> 1); +assign f19 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f20 = -feature_reg_2_4_1; +assign f21 = -{feature_reg_3_0_1[12:0], 3'b000}; +assign f22 = -(dsp_out_1_7 <<< 1); +assign f23 = -{feature_reg_3_4_1[14:0], 1'b0}; +assign f23b = dsp_out_1_6 >>> 2; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA40 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[12:0], 3'b000}), + .data1x(f18), + .data2x({feature_reg_1_4_1[14:0], 1'b0}), + .data3x(f19), + .data4x(f23b), + .data5x(f20), + .data6x(f21), + .data7x(f22), + .data8x(f23), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_0) +); + +wire [15:0] f24; +assign f24 = -dsp_out_1_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA50 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f24), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_8), + .data4x(dsp_out_1_9), + .data5x(dsp_out_1_10), + .data6x({feature_reg_5_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_11), + .data8x(feature_reg_5_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_0) +); + +wire [15:0] f25, f26, f27, f28; +assign f25 = -{feature_reg_0_2_1[11:0], 4'b0000}; +assign f26 = -{feature_reg_0_1_1[11:0], 4'b0000}; +assign f27 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f28 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA01 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[13:0], 2'b00}), + .data1x(f25), + .data2x(f26), + .data3x({feature_reg_0_4_1[13:0], 2'b00}), + .data4x(dsp_out_2_0), + .data5x(dsp_out_2_1), + .data6x(dsp_out_2_2), + .data7x(dsp_out_2_3), + .data8x(f27), + .data9x(f28), + .data10x(feature_reg_4_3_1), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_1) +); + +wire [15:0] f29, f30, f31, f32, f33, f34, f35, f36; +assign f29 = -{feature_reg_1_3_1[13:0], 2'b00}; +assign f30 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f31 = -{feature_reg_2_3_1[13:0], 2'b00}; +assign f32 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f33 = -{feature_reg_3_1_1[13:0], 2'b00}; +assign f34 = -{feature_reg_3_2_1[13:0], 2'b00}; +assign f35 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f36 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA11 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0], 4'b0000}), + .data1x({feature_reg_1_2_1[11:0], 4'b0000}), + .data2x(f29), + .data3x(f30), + .data4x({feature_reg_2_1_1[11:0], 4'b0000}), + .data5x({feature_reg_2_2_1[11:0], 4'b0000}), + .data6x(f31), + .data7x(f32), + .data8x(f33), + .data9x(f34), + .data10x(feature_reg_3_3_1), + .data11x(feature_reg_3_4_1), + .data12x(f35), + .data13x(f36), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_1) +); + +wire [15:0] f37, f38, f39, f40, f41, f42, f43, f44; +assign f37 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f38 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f39 = -{feature_reg_2_3_1[13:0],2'b00}; +assign f40 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f41 = -feature_reg_3_3_1; +assign f42 = -feature_reg_3_4_1; +assign f43 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f44 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA21 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f37), + .data2x(f38), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[11:0],4'b0000}), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x(f39), + .data7x(f40), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(f41), + .data11x(f42), + .data12x(f43), + .data13x(f44), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_1) +); + +wire [15:0] f45, f46, f47, f48, f49, f50, f51, f52; +assign f45 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f46 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f47 = -feature_reg_2_3_1; +assign f48 = -feature_reg_2_4_1; +assign f49 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f50 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f51 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f52 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA31 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[12:0],3'b000}), + .data2x(f45), + .data3x(f46), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f47), + .data7x(f48), + .data8x(f49), + .data9x(f50), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f51), + .data13x(f52), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_1) +); + +wire [15:0] f53, f54, f55, f56, f57, f58, f59, f60; +assign f53 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f54 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f55 = -feature_reg_2_3_1; +assign f56 = -feature_reg_2_4_1; +assign f57 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f58 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f59 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f60 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA41 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[14:0],1'b0}), + .data1x(f53), + .data2x(f54), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f55), + .data7x(f56), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x(f57), + .data11x(f58), + .data12x(f59), + .data13x(f60), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_1) +); + +wire [15:0] f61, f62, f63, f64; +assign f61 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f62 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f63 = -{feature_reg_5_1_1[13:0],2'b00}; +assign f64 = -{feature_reg_5_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA51 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f61), + .data2x(f62), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_2_4), + .data5x(dsp_out_2_5), + .data6x(dsp_out_2_6), + .data7x(dsp_out_2_7), + .data8x(f63), + .data9x(f64), + .data10x(feature_reg_5_3_1), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_1) +); + +wire [15:0] f65, f66, f67, f68; +assign f65 = -{feature_reg_0_2_1[11:0],4'b0000}; +assign f66 = -{feature_reg_0_3_1[13:0],2'b00}; +assign f67 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f68 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA02 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(f65), + .data2x(f66), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_3_0), + .data5x(dsp_out_3_1), + .data6x(dsp_out_3_2), + .data7x(dsp_out_3_3), + .data8x({feature_reg_4_1_1[13:0],2'b00}), + .data9x(f67), + .data10x(f68), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_2) +); + +wire [15:0] f69, f70, f71, f72, f73, f74, f75, f76; +assign f69 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f70 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f71 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f72 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f73 = -{feature_reg_3_2_1[13:0],2'b00}; +assign f74 = -feature_reg_3_3_1; +assign f75 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f76 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA12 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[11:0],4'b0000}), + .data1x(f69), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f70), + .data4x(f71), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f72), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f73), + .data10x(f74), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f75), + .data14x(f76), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_2) +); + +wire [15:0] f77, f78, f79, f80, f81, f82, f83, f84; +assign f77 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f78 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f79 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f80 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f81 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f82 = -feature_reg_3_4_1; +assign f83 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f84 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA22 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f77), + .data2x(f78), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f79), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f80), + .data8x(f81), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(feature_reg_3_3_1), + .data11x(f82), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f83), + .data14x(f84), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_2) +); + +wire [15:0] f85, f86, f87, f88, f89, f90, f91, f92; +assign f85 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f86 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f87 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f88 = -feature_reg_2_4_1; +assign f89 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f90 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f91 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f92 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA32 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[12:0],3'b000}), + .data1x(f85), + .data2x({feature_reg_1_3_1[14:0],1'b0}), + .data3x(f86), + .data4x(f87), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f88), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x(f89), + .data10x(f90), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f91), + .data14x(f92), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_2) +); + +wire [15:0] f93, f94, f95, f96, f97, f98, f99, f100; +assign f93 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f94 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f95 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f96 = -feature_reg_2_4_1; +assign f97 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f98 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f99 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f100 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA42 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f93), + .data2x(f94), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f95), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f96), + .data8x(f97), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f98), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f99), + .data14x(f100), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_2) +); + +wire [15:0] f101, f102, f103, f104; +assign f101 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f102 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f103 = -{feature_reg_5_2_1[13:0],2'b00}; +assign f104 = -feature_reg_5_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA52 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f101), + .data2x(f102), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_3_4), + .data5x(dsp_out_3_5), + .data6x(dsp_out_3_6), + .data7x(dsp_out_3_7), + .data8x({feature_reg_5_1_1[13:0],2'b00}), + .data9x(f103), + .data10x(f104), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_2) +); + +wire [15:0] f105, f106, f107, f108; +assign f105 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f106 = -{feature_reg_0_1_1[12:0],3'b000}; +assign f107 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f108 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA03 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[12:0],3'b000}), + .data1x(f105), + .data2x(f106), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_4_0), + .data5x(dsp_out_4_1), + .data6x(dsp_out_4_2), + .data7x(dsp_out_4_3), + .data8x(f107), + .data9x(f108), + .data10x({feature_reg_4_3_1[14:0],1'b0}), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_3) +); + +wire [15:0] f109, f110, f111, f112, f113, f114, f115, f116; +assign f109 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f110 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f111 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f112 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f113 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f114 = -feature_reg_3_2_1; +assign f115 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f116 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA13 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[13:0],2'b00}), + .data2x(f109), + .data3x(f110), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f111), + .data7x(f112), + .data8x(f113), + .data9x(f114), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(feature_reg_3_4_1), + .data12x(f115), + .data13x(f116), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_3) +); + +wire [15:0] f117, f118, f119, f120, f121, f122, f123, f124; +assign f117 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f118 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f119 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f120 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f121 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f122 = -feature_reg_3_4_1; +assign f123 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f124 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA23 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f117), + .data2x(f118), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f119), + .data7x(f120), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(feature_reg_3_2_1), + .data10x(f121), + .data11x(f122), + .data12x(f123), + .data13x(f124), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_3) +); + +wire [15:0] f125, f126, f127, f128, f129, f130, f131, f132; +assign f125 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f126 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f127 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f128 = -feature_reg_2_4_1; +assign f129 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f130 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f131 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f132 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA33 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x({feature_reg_1_2_1[14:0],1'b0}), + .data2x(f125), + .data3x(f126), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f127), + .data7x(f128), + .data8x(f129), + .data9x(f130), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f131), + .data13x(f132), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_3) +); + +wire [15:0] f133, f134, f135, f136, f137, f138, f139, f140; +assign f133 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f134 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f135 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f136 = -feature_reg_2_4_1; +assign f137 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f138 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f139 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f140 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA43 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f133), + .data2x(f134), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f135), + .data7x(f136), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x(f137), + .data11x(f138), + .data12x(f139), + .data13x(f140), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_3) +); + +wire [15:0] f141, f142, f143, f144; +assign f141 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f142 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f143 = -{feature_reg_5_1_1[14:0],1'b0}; +assign f144 = -feature_reg_5_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA53 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f141), + .data2x(f142), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_4_4), + .data5x(dsp_out_4_5), + .data6x(dsp_out_4_6), + .data7x(dsp_out_4_7), + .data8x(f143), + .data9x(f144), + .data10x({feature_reg_5_3_1[14:0],1'b0}), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_3) +); + +wire [15:0] f145, f146, f147, f148; +assign f145 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f146 = -{feature_reg_0_3_1[12:0],3'b000}; +assign f147 = -feature_reg_4_2_1; +assign f148 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA04 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[12:0],3'b000}), + .data1x(f145), + .data2x(f146), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_5_0), + .data5x(dsp_out_5_1), + .data6x(dsp_out_5_2), + .data7x(dsp_out_5_3), + .data8x({feature_reg_4_1_1[14:0],1'b0}), + .data9x(f147), + .data10x(f148), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_4) +); + +wire [15:0] f149, f150, f151, f152, f153, f154, f155, f156; +assign f149 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f150 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f151 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f152 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f153 = -feature_reg_3_2_1; +assign f154 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f155 = -feature_reg_4_2_1; +assign f156 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA14 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[13:0],2'b00}), + .data1x(f149), + .data2x({feature_reg_1_3_1[12:0],3'b000}), + .data3x(f150), + .data4x(f151), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f152), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(f153), + .data10x(f154), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f155), + .data14x(f156), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_4) +); + +wire [15:0] f157, f158, f159, f160, f161, f162, f163, f164; +assign f157 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f158 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f159 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f160 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f161 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f162 = -feature_reg_3_4_1; +assign f163 = -feature_reg_4_2_1; +assign f164 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA24 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f157), + .data2x(f158), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f159), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f160), + .data8x(f161), + .data9x(feature_reg_3_2_1), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f162), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f163), + .data14x(f164), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_4) +); + +wire [15:0] f165, f166, f167, f168, f169, f170, f171, f172; +assign f165 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f166 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f167 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f168 = -feature_reg_2_4_1; +assign f169 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f170 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f171 = -feature_reg_4_2_1; +assign f172 = -{feature_reg_4_1_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA34 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[14:0],1'b0}), + .data1x(f165), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f166), + .data4x(f167), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f168), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f169), + .data10x(f170), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f171), + .data14x(f172), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_4) +); + +wire [15:0] f173, f174, f175, f176, f177, f178, f179, f180; +assign f173 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f174 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f175 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f176 = -feature_reg_2_4_1; +assign f177 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f178 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f179 = -feature_reg_4_2_1; +assign f180 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA44 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x(f173), + .data2x(f174), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f175), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f176), + .data8x(f177), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x(f178), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f179), + .data14x(f180), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_4) +); + +wire [15:0] f181, f182, f183, f184; +assign f181 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f182 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f183 = -feature_reg_5_2_1; +assign f184 = -{feature_reg_5_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA54 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f181), + .data2x(f182), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_5_4), + .data5x(dsp_out_5_5), + .data6x(dsp_out_5_6), + .data7x(dsp_out_5_7), + .data8x({feature_reg_5_1_1[14:0],1'b0}), + .data9x(f183), + .data10x(f184), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_4) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA05 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(dsp_out_6_0), + .data2x({feature_reg_0_5_1[13:0],2'b00}), + .data3x(dsp_out_6_1), + .data4x(dsp_out_6_2), + .data5x(dsp_out_6_3), + .data6x({feature_reg_4_1_1[13:0],2'b00}), + .data7x(dsp_out_6_4), + .data8x(feature_reg_4_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_5) +); + +wire [15:0] f185, f186, f187, f188; +assign f185 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f186 = -{feature_reg_1_5_1[13:0],2'b00}; +assign f187 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f188 = -{feature_reg_2_5_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA15 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_6_5), + .data1x(f185), + .data2x(f186), + .data3x(f187), + .data4x(dsp_out_6_6), + .data5x(f188), + .data6x({feature_reg_3_1_1[13:0],2'b00}), + .data7x(dsp_out_6_7), + .data8x(feature_reg_3_5_1), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_5) +); + +wire [15:0] f189, f190, f191, f192, f193, f194; +assign f189 = -dsp_out_6_5; +assign f190 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f191 = -{feature_reg_2_5_1[13:0],2'b00}; +assign f192 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f193 = -dsp_out_6_7; +assign f194 = -feature_reg_3_5_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA25 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f189), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(f190), + .data4x(dsp_out_6_6), + .data5x(f191), + .data6x(f192), + .data7x(f193), + .data8x(f194), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_5) +); + +wire [15:0] f195, f196, f197, f198, f199, f200, f201; +assign f195 = dsp_out_6_5 >>> 1; +assign f196 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f197 = -{feature_reg_1_5_1[14:0],1'b0}; +assign f198 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f199 = dsp_out_6_6 >>> 2; +assign f200 = -feature_reg_2_5_1; +assign f201 = dsp_out_6_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA35 ( + .clock(clk), + .clken(calculate_2), + .data0x(f195), + .data1x(f196), + .data2x(f197), + .data3x(f198), + .data4x(f199), + .data5x(f200), + .data6x({feature_reg_3_1_1[12:0],3'b000}), + .data7x(f201), + .data8x({feature_reg_3_5_1[14:0],1'b0}), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_5) +); + +wire [15:0] f202, f203, f204, f205, f206, f207, f208; +assign f202 = -(dsp_out_6_5 >>> 1); +assign f203 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f204 = dsp_out_6_6 >>> 2; +assign f205 = -feature_reg_2_5_1; +assign f206 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f207 = -(dsp_out_6_7 <<< 1); +assign f208 = -{feature_reg_3_5_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA45 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f202), + .data2x({feature_reg_1_5_1[14:0],1'b0}), + .data3x(f203), + .data4x(f204), + .data5x(f205), + .data6x(f206), + .data7x(f207), + .data8x(f208), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_5) +); + +wire [15:0] f209; +assign f209 = -dsp_out_6_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA55 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f209), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(dsp_out_6_8), + .data4x(dsp_out_6_9), + .data5x(dsp_out_6_10), + .data6x({feature_reg_5_1_1[13:0],2'b00}), + .data7x(dsp_out_6_11), + .data8x(feature_reg_5_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_5) +); + +assign o_feature_0 = output_buffer_0_0[15:0]; +assign o_feature_1 = output_buffer_1_0[15:0]; +assign o_feature_2 = output_buffer_2_0[15:0]; +assign o_feature_3 = output_buffer_3_0[15:0]; +assign o_feature_4 = output_buffer_4_0[15:0]; +assign o_feature_5 = output_buffer_5_0[15:0]; +assign o_valid = valid_9; + +endmodule + +module winograd_transform_3 ( + input clk, + input i_valid, + input [15:0] i_result_0_0, + input [15:0] i_result_0_1, + input [15:0] i_result_0_2, + input [15:0] i_result_0_3, + input [15:0] i_result_0_4, + input [15:0] i_result_0_5, + input [15:0] i_result_0_6, + input [15:0] i_result_0_7, + input [15:0] i_result_1_0, + input [15:0] i_result_1_1, + input [15:0] i_result_1_2, + input [15:0] i_result_1_3, + input [15:0] i_result_1_4, + input [15:0] i_result_1_5, + input [15:0] i_result_1_6, + input [15:0] i_result_1_7, + input [15:0] i_result_2_0, + input [15:0] i_result_2_1, + input [15:0] i_result_2_2, + input [15:0] i_result_2_3, + input [15:0] i_result_2_4, + input [15:0] i_result_2_5, + input [15:0] i_result_2_6, + input [15:0] i_result_2_7, + input [15:0] i_result_3_0, + input [15:0] i_result_3_1, + input [15:0] i_result_3_2, + input [15:0] i_result_3_3, + input [15:0] i_result_3_4, + input [15:0] i_result_3_5, + input [15:0] i_result_3_6, + input [15:0] i_result_3_7, + input [15:0] i_result_4_0, + input [15:0] i_result_4_1, + input [15:0] i_result_4_2, + input [15:0] i_result_4_3, + input [15:0] i_result_4_4, + input [15:0] i_result_4_5, + input [15:0] i_result_4_6, + input [15:0] i_result_4_7, + input [15:0] i_result_5_0, + input [15:0] i_result_5_1, + input [15:0] i_result_5_2, + input [15:0] i_result_5_3, + input [15:0] i_result_5_4, + input [15:0] i_result_5_5, + input [15:0] i_result_5_6, + input [15:0] i_result_5_7, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output [15:0] o_feature_2, + output [15:0] o_feature_3, + output [15:0] o_feature_4, + output [15:0] o_feature_5, + output o_valid +); + +reg [15:0] input_buffer_0_0; +reg [19:0] output_buffer_0_0; +wire [19:0] rslt_buffer_0_0; +reg [15:0] input_buffer_0_1; +reg [19:0] output_buffer_0_1; +wire [19:0] rslt_buffer_0_1; +reg [15:0] input_buffer_0_2; +reg [19:0] output_buffer_0_2; +wire [19:0] rslt_buffer_0_2; +reg [15:0] input_buffer_0_3; +reg [19:0] output_buffer_0_3; +wire [19:0] rslt_buffer_0_3; +reg [15:0] input_buffer_0_4; +reg [19:0] output_buffer_0_4; +wire [19:0] rslt_buffer_0_4; +reg [15:0] input_buffer_0_5; +reg [19:0] output_buffer_0_5; +wire [19:0] rslt_buffer_0_5; +reg [15:0] input_buffer_1_0; +reg [19:0] output_buffer_1_0; +wire [19:0] rslt_buffer_1_0; +reg [15:0] input_buffer_1_1; +reg [19:0] output_buffer_1_1; +wire [19:0] rslt_buffer_1_1; +reg [15:0] input_buffer_1_2; +reg [19:0] output_buffer_1_2; +wire [19:0] rslt_buffer_1_2; +reg [15:0] input_buffer_1_3; +reg [19:0] output_buffer_1_3; +wire [19:0] rslt_buffer_1_3; +reg [15:0] input_buffer_1_4; +reg [19:0] output_buffer_1_4; +wire [19:0] rslt_buffer_1_4; +reg [15:0] input_buffer_1_5; +reg [19:0] output_buffer_1_5; +wire [19:0] rslt_buffer_1_5; +reg [15:0] input_buffer_2_0; +reg [19:0] output_buffer_2_0; +wire [19:0] rslt_buffer_2_0; +reg [15:0] input_buffer_2_1; +reg [19:0] output_buffer_2_1; +wire [19:0] rslt_buffer_2_1; +reg [15:0] input_buffer_2_2; +reg [19:0] output_buffer_2_2; +wire [19:0] rslt_buffer_2_2; +reg [15:0] input_buffer_2_3; +reg [19:0] output_buffer_2_3; +wire [19:0] rslt_buffer_2_3; +reg [15:0] input_buffer_2_4; +reg [19:0] output_buffer_2_4; +wire [19:0] rslt_buffer_2_4; +reg [15:0] input_buffer_2_5; +reg [19:0] output_buffer_2_5; +wire [19:0] rslt_buffer_2_5; +reg [15:0] input_buffer_3_0; +reg [19:0] output_buffer_3_0; +wire [19:0] rslt_buffer_3_0; +reg [15:0] input_buffer_3_1; +reg [19:0] output_buffer_3_1; +wire [19:0] rslt_buffer_3_1; +reg [15:0] input_buffer_3_2; +reg [19:0] output_buffer_3_2; +wire [19:0] rslt_buffer_3_2; +reg [15:0] input_buffer_3_3; +reg [19:0] output_buffer_3_3; +wire [19:0] rslt_buffer_3_3; +reg [15:0] input_buffer_3_4; +reg [19:0] output_buffer_3_4; +wire [19:0] rslt_buffer_3_4; +reg [15:0] input_buffer_3_5; +reg [19:0] output_buffer_3_5; +wire [19:0] rslt_buffer_3_5; +reg [15:0] input_buffer_4_0; +reg [19:0] output_buffer_4_0; +wire [19:0] rslt_buffer_4_0; +reg [15:0] input_buffer_4_1; +reg [19:0] output_buffer_4_1; +wire [19:0] rslt_buffer_4_1; +reg [15:0] input_buffer_4_2; +reg [19:0] output_buffer_4_2; +wire [19:0] rslt_buffer_4_2; +reg [15:0] input_buffer_4_3; +reg [19:0] output_buffer_4_3; +wire [19:0] rslt_buffer_4_3; +reg [15:0] input_buffer_4_4; +reg [19:0] output_buffer_4_4; +wire [19:0] rslt_buffer_4_4; +reg [15:0] input_buffer_4_5; +reg [19:0] output_buffer_4_5; +wire [19:0] rslt_buffer_4_5; +reg [15:0] input_buffer_5_0; +reg [19:0] output_buffer_5_0; +wire [19:0] rslt_buffer_5_0; +reg [15:0] input_buffer_5_1; +reg [19:0] output_buffer_5_1; +wire [19:0] rslt_buffer_5_1; +reg [15:0] input_buffer_5_2; +reg [19:0] output_buffer_5_2; +wire [19:0] rslt_buffer_5_2; +reg [15:0] input_buffer_5_3; +reg [19:0] output_buffer_5_3; +wire [19:0] rslt_buffer_5_3; +reg [15:0] input_buffer_5_4; +reg [19:0] output_buffer_5_4; +wire [19:0] rslt_buffer_5_4; +reg [15:0] input_buffer_5_5; +reg [19:0] output_buffer_5_5; +wire [19:0] rslt_buffer_5_5; +reg calculate, calculate_1, calculate_2, calculate_3; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg valid_12; +reg [2:0] input_buffer_count; +wire [15:0] dsp_out_1_0; +wire [15:0] dsp_out_1_1; +wire [15:0] dsp_out_1_2; +wire [15:0] dsp_out_1_3; +wire [15:0] dsp_out_1_4; +wire [15:0] dsp_out_1_5; +wire [15:0] dsp_out_1_6; +wire [15:0] dsp_out_1_7; +wire [15:0] dsp_out_1_8; +wire [15:0] dsp_out_1_9; +wire [15:0] dsp_out_1_10; +wire [15:0] dsp_out_1_11; +wire [15:0] dsp_out_2_0; +wire [15:0] dsp_out_2_1; +wire [15:0] dsp_out_2_2; +wire [15:0] dsp_out_2_3; +wire [15:0] dsp_out_2_4; +wire [15:0] dsp_out_2_5; +wire [15:0] dsp_out_2_6; +wire [15:0] dsp_out_2_7; +wire [15:0] dsp_out_3_0; +wire [15:0] dsp_out_3_1; +wire [15:0] dsp_out_3_2; +wire [15:0] dsp_out_3_3; +wire [15:0] dsp_out_3_4; +wire [15:0] dsp_out_3_5; +wire [15:0] dsp_out_3_6; +wire [15:0] dsp_out_3_7; +wire [15:0] dsp_out_4_0; +wire [15:0] dsp_out_4_1; +wire [15:0] dsp_out_4_2; +wire [15:0] dsp_out_4_3; +wire [15:0] dsp_out_4_4; +wire [15:0] dsp_out_4_5; +wire [15:0] dsp_out_4_6; +wire [15:0] dsp_out_4_7; +wire [15:0] dsp_out_5_0; +wire [15:0] dsp_out_5_1; +wire [15:0] dsp_out_5_2; +wire [15:0] dsp_out_5_3; +wire [15:0] dsp_out_5_4; +wire [15:0] dsp_out_5_5; +wire [15:0] dsp_out_5_6; +wire [15:0] dsp_out_5_7; +wire [15:0] dsp_out_6_0; +wire [15:0] dsp_out_6_1; +wire [15:0] dsp_out_6_2; +wire [15:0] dsp_out_6_3; +wire [15:0] dsp_out_6_4; +wire [15:0] dsp_out_6_5; +wire [15:0] dsp_out_6_6; +wire [15:0] dsp_out_6_7; +wire [15:0] dsp_out_6_8; +wire [15:0] dsp_out_6_9; +wire [15:0] dsp_out_6_10; +wire [15:0] dsp_out_6_11; +reg [15:0] feature_reg_0_0_0; +reg [15:0] feature_reg_0_0_1; +reg [15:0] feature_reg_0_1_0; +reg [15:0] feature_reg_0_1_1; +reg [15:0] feature_reg_0_2_0; +reg [15:0] feature_reg_0_2_1; +reg [15:0] feature_reg_0_3_0; +reg [15:0] feature_reg_0_3_1; +reg [15:0] feature_reg_0_4_0; +reg [15:0] feature_reg_0_4_1; +reg [15:0] feature_reg_0_5_0; +reg [15:0] feature_reg_0_5_1; +reg [15:0] feature_reg_1_0_0; +reg [15:0] feature_reg_1_0_1; +reg [15:0] feature_reg_1_1_0; +reg [15:0] feature_reg_1_1_1; +reg [15:0] feature_reg_1_2_0; +reg [15:0] feature_reg_1_2_1; +reg [15:0] feature_reg_1_3_0; +reg [15:0] feature_reg_1_3_1; +reg [15:0] feature_reg_1_4_0; +reg [15:0] feature_reg_1_4_1; +reg [15:0] feature_reg_1_5_0; +reg [15:0] feature_reg_1_5_1; +reg [15:0] feature_reg_2_0_0; +reg [15:0] feature_reg_2_0_1; +reg [15:0] feature_reg_2_1_0; +reg [15:0] feature_reg_2_1_1; +reg [15:0] feature_reg_2_2_0; +reg [15:0] feature_reg_2_2_1; +reg [15:0] feature_reg_2_3_0; +reg [15:0] feature_reg_2_3_1; +reg [15:0] feature_reg_2_4_0; +reg [15:0] feature_reg_2_4_1; +reg [15:0] feature_reg_2_5_0; +reg [15:0] feature_reg_2_5_1; +reg [15:0] feature_reg_3_0_0; +reg [15:0] feature_reg_3_0_1; +reg [15:0] feature_reg_3_1_0; +reg [15:0] feature_reg_3_1_1; +reg [15:0] feature_reg_3_2_0; +reg [15:0] feature_reg_3_2_1; +reg [15:0] feature_reg_3_3_0; +reg [15:0] feature_reg_3_3_1; +reg [15:0] feature_reg_3_4_0; +reg [15:0] feature_reg_3_4_1; +reg [15:0] feature_reg_3_5_0; +reg [15:0] feature_reg_3_5_1; +reg [15:0] feature_reg_4_0_0; +reg [15:0] feature_reg_4_0_1; +reg [15:0] feature_reg_4_1_0; +reg [15:0] feature_reg_4_1_1; +reg [15:0] feature_reg_4_2_0; +reg [15:0] feature_reg_4_2_1; +reg [15:0] feature_reg_4_3_0; +reg [15:0] feature_reg_4_3_1; +reg [15:0] feature_reg_4_4_0; +reg [15:0] feature_reg_4_4_1; +reg [15:0] feature_reg_4_5_0; +reg [15:0] feature_reg_4_5_1; +reg [15:0] feature_reg_5_0_0; +reg [15:0] feature_reg_5_0_1; +reg [15:0] feature_reg_5_1_0; +reg [15:0] feature_reg_5_1_1; +reg [15:0] feature_reg_5_2_0; +reg [15:0] feature_reg_5_2_1; +reg [15:0] feature_reg_5_3_0; +reg [15:0] feature_reg_5_3_1; +reg [15:0] feature_reg_5_4_0; +reg [15:0] feature_reg_5_4_1; +reg [15:0] feature_reg_5_5_0; +reg [15:0] feature_reg_5_5_1; + +always @ (posedge clk) begin + calculate_1 <= calculate; + calculate_2 <= calculate_1; + calculate_3 <= calculate_2; + //Valid pipeline + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + valid_12 <= valid_11; + if (i_valid) begin + input_buffer_count <= 0; + calculate <= 0; + end else begin + //Input buffering logic + if (input_buffer_count == 5) begin + calculate <= 1; + input_buffer_count <= 0; + end else begin + calculate <= 0; + input_buffer_count <= input_buffer_count + 1'b1; + end + input_buffer_5_0 <= i_result_0_3; + input_buffer_5_1 <= i_result_1_3; + input_buffer_5_2 <= i_result_2_3; + input_buffer_5_3 <= i_result_3_3; + input_buffer_5_4 <= i_result_4_3; + input_buffer_5_5 <= i_result_5_3; + end + input_buffer_0_0 <= input_buffer_1_0; + input_buffer_0_1 <= input_buffer_1_1; + input_buffer_0_2 <= input_buffer_1_2; + input_buffer_0_3 <= input_buffer_1_3; + input_buffer_0_4 <= input_buffer_1_4; + input_buffer_0_5 <= input_buffer_1_5; + input_buffer_1_0 <= input_buffer_2_0; + input_buffer_1_1 <= input_buffer_2_1; + input_buffer_1_2 <= input_buffer_2_2; + input_buffer_1_3 <= input_buffer_2_3; + input_buffer_1_4 <= input_buffer_2_4; + input_buffer_1_5 <= input_buffer_2_5; + input_buffer_2_0 <= input_buffer_3_0; + input_buffer_2_1 <= input_buffer_3_1; + input_buffer_2_2 <= input_buffer_3_2; + input_buffer_2_3 <= input_buffer_3_3; + input_buffer_2_4 <= input_buffer_3_4; + input_buffer_2_5 <= input_buffer_3_5; + input_buffer_3_0 <= input_buffer_4_0; + input_buffer_3_1 <= input_buffer_4_1; + input_buffer_3_2 <= input_buffer_4_2; + input_buffer_3_3 <= input_buffer_4_3; + input_buffer_3_4 <= input_buffer_4_4; + input_buffer_3_5 <= input_buffer_4_5; + input_buffer_4_0 <= input_buffer_5_0; + input_buffer_4_1 <= input_buffer_5_1; + input_buffer_4_2 <= input_buffer_5_2; + input_buffer_4_3 <= input_buffer_5_3; + input_buffer_4_4 <= input_buffer_5_4; + input_buffer_4_5 <= input_buffer_5_5; + //Pipelining to synchronize DSPs and non-DSPs + feature_reg_0_0_0 <= input_buffer_0_0; + feature_reg_0_1_0 <= input_buffer_0_1; + feature_reg_0_2_0 <= input_buffer_0_2; + feature_reg_0_3_0 <= input_buffer_0_3; + feature_reg_0_4_0 <= input_buffer_0_4; + feature_reg_0_5_0 <= input_buffer_0_5; + feature_reg_1_0_0 <= input_buffer_1_0; + feature_reg_1_1_0 <= input_buffer_1_1; + feature_reg_1_2_0 <= input_buffer_1_2; + feature_reg_1_3_0 <= input_buffer_1_3; + feature_reg_1_4_0 <= input_buffer_1_4; + feature_reg_1_5_0 <= input_buffer_1_5; + feature_reg_2_0_0 <= input_buffer_2_0; + feature_reg_2_1_0 <= input_buffer_2_1; + feature_reg_2_2_0 <= input_buffer_2_2; + feature_reg_2_3_0 <= input_buffer_2_3; + feature_reg_2_4_0 <= input_buffer_2_4; + feature_reg_2_5_0 <= input_buffer_2_5; + feature_reg_3_0_0 <= input_buffer_3_0; + feature_reg_3_1_0 <= input_buffer_3_1; + feature_reg_3_2_0 <= input_buffer_3_2; + feature_reg_3_3_0 <= input_buffer_3_3; + feature_reg_3_4_0 <= input_buffer_3_4; + feature_reg_3_5_0 <= input_buffer_3_5; + feature_reg_4_0_0 <= input_buffer_4_0; + feature_reg_4_1_0 <= input_buffer_4_1; + feature_reg_4_2_0 <= input_buffer_4_2; + feature_reg_4_3_0 <= input_buffer_4_3; + feature_reg_4_4_0 <= input_buffer_4_4; + feature_reg_4_5_0 <= input_buffer_4_5; + feature_reg_5_0_0 <= input_buffer_5_0; + feature_reg_5_1_0 <= input_buffer_5_1; + feature_reg_5_2_0 <= input_buffer_5_2; + feature_reg_5_3_0 <= input_buffer_5_3; + feature_reg_5_4_0 <= input_buffer_5_4; + feature_reg_5_5_0 <= input_buffer_5_5; + feature_reg_0_0_1 <= feature_reg_0_0_0; + feature_reg_0_1_1 <= feature_reg_0_1_0; + feature_reg_0_2_1 <= feature_reg_0_2_0; + feature_reg_0_3_1 <= feature_reg_0_3_0; + feature_reg_0_4_1 <= feature_reg_0_4_0; + feature_reg_0_5_1 <= feature_reg_0_5_0; + feature_reg_1_0_1 <= feature_reg_1_0_0; + feature_reg_1_1_1 <= feature_reg_1_1_0; + feature_reg_1_2_1 <= feature_reg_1_2_0; + feature_reg_1_3_1 <= feature_reg_1_3_0; + feature_reg_1_4_1 <= feature_reg_1_4_0; + feature_reg_1_5_1 <= feature_reg_1_5_0; + feature_reg_2_0_1 <= feature_reg_2_0_0; + feature_reg_2_1_1 <= feature_reg_2_1_0; + feature_reg_2_2_1 <= feature_reg_2_2_0; + feature_reg_2_3_1 <= feature_reg_2_3_0; + feature_reg_2_4_1 <= feature_reg_2_4_0; + feature_reg_2_5_1 <= feature_reg_2_5_0; + feature_reg_3_0_1 <= feature_reg_3_0_0; + feature_reg_3_1_1 <= feature_reg_3_1_0; + feature_reg_3_2_1 <= feature_reg_3_2_0; + feature_reg_3_3_1 <= feature_reg_3_3_0; + feature_reg_3_4_1 <= feature_reg_3_4_0; + feature_reg_3_5_1 <= feature_reg_3_5_0; + feature_reg_4_0_1 <= feature_reg_4_0_0; + feature_reg_4_1_1 <= feature_reg_4_1_0; + feature_reg_4_2_1 <= feature_reg_4_2_0; + feature_reg_4_3_1 <= feature_reg_4_3_0; + feature_reg_4_4_1 <= feature_reg_4_4_0; + feature_reg_4_5_1 <= feature_reg_4_5_0; + feature_reg_5_0_1 <= feature_reg_5_0_0; + feature_reg_5_1_1 <= feature_reg_5_1_0; + feature_reg_5_2_1 <= feature_reg_5_2_0; + feature_reg_5_3_1 <= feature_reg_5_3_0; + feature_reg_5_4_1 <= feature_reg_5_4_0; + feature_reg_5_5_1 <= feature_reg_5_5_0; + //Output Serializing logic + if (calculate_3) begin + output_buffer_0_0 <= rslt_buffer_0_0; + output_buffer_1_0 <= rslt_buffer_0_1; + output_buffer_2_0 <= rslt_buffer_0_2; + output_buffer_3_0 <= rslt_buffer_0_3; + output_buffer_4_0 <= rslt_buffer_0_4; + output_buffer_5_0 <= rslt_buffer_0_5; + output_buffer_0_1 <= rslt_buffer_1_0; + output_buffer_1_1 <= rslt_buffer_1_1; + output_buffer_2_1 <= rslt_buffer_1_2; + output_buffer_3_1 <= rslt_buffer_1_3; + output_buffer_4_1 <= rslt_buffer_1_4; + output_buffer_5_1 <= rslt_buffer_1_5; + output_buffer_0_2 <= rslt_buffer_2_0; + output_buffer_1_2 <= rslt_buffer_2_1; + output_buffer_2_2 <= rslt_buffer_2_2; + output_buffer_3_2 <= rslt_buffer_2_3; + output_buffer_4_2 <= rslt_buffer_2_4; + output_buffer_5_2 <= rslt_buffer_2_5; + output_buffer_0_3 <= rslt_buffer_3_0; + output_buffer_1_3 <= rslt_buffer_3_1; + output_buffer_2_3 <= rslt_buffer_3_2; + output_buffer_3_3 <= rslt_buffer_3_3; + output_buffer_4_3 <= rslt_buffer_3_4; + output_buffer_5_3 <= rslt_buffer_3_5; + output_buffer_0_4 <= rslt_buffer_4_0; + output_buffer_1_4 <= rslt_buffer_4_1; + output_buffer_2_4 <= rslt_buffer_4_2; + output_buffer_3_4 <= rslt_buffer_4_3; + output_buffer_4_4 <= rslt_buffer_4_4; + output_buffer_5_4 <= rslt_buffer_4_5; + output_buffer_0_5 <= rslt_buffer_5_0; + output_buffer_1_5 <= rslt_buffer_5_1; + output_buffer_2_5 <= rslt_buffer_5_2; + output_buffer_3_5 <= rslt_buffer_5_3; + output_buffer_4_5 <= rslt_buffer_5_4; + output_buffer_5_5 <= rslt_buffer_5_5; + end else begin + output_buffer_0_0 <= output_buffer_0_1; + output_buffer_0_1 <= output_buffer_0_2; + output_buffer_0_2 <= output_buffer_0_3; + output_buffer_0_3 <= output_buffer_0_4; + output_buffer_0_4 <= output_buffer_0_5; + output_buffer_1_0 <= output_buffer_1_1; + output_buffer_1_1 <= output_buffer_1_2; + output_buffer_1_2 <= output_buffer_1_3; + output_buffer_1_3 <= output_buffer_1_4; + output_buffer_1_4 <= output_buffer_1_5; + output_buffer_2_0 <= output_buffer_2_1; + output_buffer_2_1 <= output_buffer_2_2; + output_buffer_2_2 <= output_buffer_2_3; + output_buffer_2_3 <= output_buffer_2_4; + output_buffer_2_4 <= output_buffer_2_5; + output_buffer_3_0 <= output_buffer_3_1; + output_buffer_3_1 <= output_buffer_3_2; + output_buffer_3_2 <= output_buffer_3_3; + output_buffer_3_3 <= output_buffer_3_4; + output_buffer_3_4 <= output_buffer_3_5; + output_buffer_4_0 <= output_buffer_4_1; + output_buffer_4_1 <= output_buffer_4_2; + output_buffer_4_2 <= output_buffer_4_3; + output_buffer_4_3 <= output_buffer_4_4; + output_buffer_4_4 <= output_buffer_4_5; + output_buffer_5_0 <= output_buffer_5_1; + output_buffer_5_1 <= output_buffer_5_2; + output_buffer_5_2 <= output_buffer_5_3; + output_buffer_5_3 <= output_buffer_5_4; + output_buffer_5_4 <= output_buffer_5_5; + end +end + +////// FIRST COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD00 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_2), + .by(input_buffer_2_0), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_1_0), + .resultb(dsp_out_1_1) +); + +winograd_dsp_16 winograd_dsp_16_WD10 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_2_4), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_1_2), + .resultb(dsp_out_1_3) +); + +winograd_dsp_16 winograd_dsp_16_WD20 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_2), + .by(input_buffer_1_0), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_1_4), + .resultb(dsp_out_1_5) +); + +winograd_dsp_16 winograd_dsp_16_WD30 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_1_6), + .resultb(dsp_out_1_7) +); + +winograd_dsp_16 winograd_dsp_16_WD40 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_0), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_1_8), + .resultb(dsp_out_1_9) +); + +winograd_dsp_16 winograd_dsp_16_WD50 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_4), + .by(input_buffer_5_2), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_1_10), + .resultb(dsp_out_1_11) +); + +////// SECOND COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD01 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_0), + .resultb(dsp_out_2_1) +); + +winograd_dsp_16 winograd_dsp_16_WD11 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_2), + .resultb(dsp_out_2_3) +); + +winograd_dsp_16 winograd_dsp_16_WD21 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_4), + .resultb(dsp_out_2_5) +); + +winograd_dsp_16 winograd_dsp_16_WD31 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_6), + .resultb(dsp_out_2_7) +); + +////// THIRD COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD02 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_0), + .resultb(dsp_out_3_1) +); + +winograd_dsp_16 winograd_dsp_16_WD12 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_2), + .resultb(dsp_out_3_3) +); + +winograd_dsp_16 winograd_dsp_16_WD22 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_4), + .resultb(dsp_out_3_5) +); + +winograd_dsp_16 winograd_dsp_16_WD32 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_6), + .resultb(dsp_out_3_7) +); + +////// FOURTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD03 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_0), + .resultb(dsp_out_4_1) +); + +winograd_dsp_16 winograd_dsp_16_WD13 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_2), + .resultb(dsp_out_4_3) +); + +winograd_dsp_16 winograd_dsp_16_WD23 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_4), + .resultb(dsp_out_4_5) +); + +winograd_dsp_16 winograd_dsp_16_WD33 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_6), + .resultb(dsp_out_4_7) +); + +////// FIFTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD04 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_0), + .resultb(dsp_out_5_1) +); + +winograd_dsp_16 winograd_dsp_16_WD14 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_2), + .resultb(dsp_out_5_3) +); + +winograd_dsp_16 winograd_dsp_16_WD24 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_4), + .resultb(dsp_out_5_5) +); + +winograd_dsp_16 winograd_dsp_16_WD34 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_6), + .resultb(dsp_out_5_7) +); + +////// SIXTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD05 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_3), + .by(input_buffer_2_1), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_6_0), + .resultb(dsp_out_6_1) +); + +winograd_dsp_16 winograd_dsp_16_WD15 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_5), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_6_2), + .resultb(dsp_out_6_3) +); + +winograd_dsp_16 winograd_dsp_16_WD25 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_3), + .by(input_buffer_1_3), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_6_4), + .resultb(dsp_out_6_5) +); + +winograd_dsp_16 winograd_dsp_16_WD35 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_3_3), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_6_6), + .resultb(dsp_out_6_7) +); + +winograd_dsp_16 winograd_dsp_16_WD45 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_3), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_6_8), + .resultb(dsp_out_6_9) +); + +winograd_dsp_16 winograd_dsp_16_WD55 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_5), + .by(input_buffer_5_3), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_6_10), + .resultb(dsp_out_6_11) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA00 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_0_1[11:0], 4'b0000}), + .data1x(dsp_out_1_0), + .data2x({feature_reg_0_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_1), + .data4x(dsp_out_1_2), + .data5x(dsp_out_1_3), + .data6x({feature_reg_4_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_4), + .data8x(feature_reg_4_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_0) +); + +wire [15:0] f1, f2, f3, f4; +assign f1 = -{feature_reg_1_0_1[11:0], 4'b0000}; +assign f2 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f3 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f4 = -{feature_reg_2_4_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA10 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_1_5), + .data1x(f1), + .data2x(f2), + .data3x(f3), + .data4x(dsp_out_1_6), + .data5x(f4), + .data6x({feature_reg_3_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_7), + .data8x(feature_reg_3_4_1), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_0) +); + +wire [15:0] f5, f6, f7, f8, f9, f10; +assign f5 = -dsp_out_1_5; +assign f6 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f7 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f8 = -{feature_reg_3_0_1[13:0], 2'b00}; +assign f9 = -dsp_out_1_7; +assign f10 = -feature_reg_3_4_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA20 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f5), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(f6), + .data4x(dsp_out_1_6), + .data5x(f7), + .data6x(f8), + .data7x(f9), + .data8x(f10), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_0) +); + +wire [15:0] f11, f12, f13, f14, f15, f16, f17; +assign f11 = -{feature_reg_1_0_1[12:0], 3'b000}; +assign f12 = -{feature_reg_1_4_1[14:0], 1'b0}; +assign f13 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f14 = -feature_reg_2_4_1; +assign f15 = dsp_out_1_5 >>> 1; +assign f16 = dsp_out_1_6 >>> 2; +assign f17 = dsp_out_1_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA30 ( + .clock(clk), + .clken(calculate_2), + .data0x(f15), + .data1x(f11), + .data2x(f12), + .data3x(f13), + .data4x(f16), + .data5x(f14), + .data6x({feature_reg_3_0_1[12:0], 3'b000}), + .data7x(f17), + .data8x({feature_reg_3_4_1[14:0], 1'b0}), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_0) +); + +wire [15:0] f18, f19, f20, f21, f22, f23, f23b; +assign f18 = -(dsp_out_1_5 >>> 1); +assign f19 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f20 = -feature_reg_2_4_1; +assign f21 = -{feature_reg_3_0_1[12:0], 3'b000}; +assign f22 = -(dsp_out_1_7 <<< 1); +assign f23 = -{feature_reg_3_4_1[14:0], 1'b0}; +assign f23b = dsp_out_1_6 >>> 2; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA40 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[12:0], 3'b000}), + .data1x(f18), + .data2x({feature_reg_1_4_1[14:0], 1'b0}), + .data3x(f19), + .data4x(f23b), + .data5x(f20), + .data6x(f21), + .data7x(f22), + .data8x(f23), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_0) +); + +wire [15:0] f24; +assign f24 = -dsp_out_1_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA50 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f24), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_8), + .data4x(dsp_out_1_9), + .data5x(dsp_out_1_10), + .data6x({feature_reg_5_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_11), + .data8x(feature_reg_5_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_0) +); + +wire [15:0] f25, f26, f27, f28; +assign f25 = -{feature_reg_0_2_1[11:0], 4'b0000}; +assign f26 = -{feature_reg_0_1_1[11:0], 4'b0000}; +assign f27 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f28 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA01 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[13:0], 2'b00}), + .data1x(f25), + .data2x(f26), + .data3x({feature_reg_0_4_1[13:0], 2'b00}), + .data4x(dsp_out_2_0), + .data5x(dsp_out_2_1), + .data6x(dsp_out_2_2), + .data7x(dsp_out_2_3), + .data8x(f27), + .data9x(f28), + .data10x(feature_reg_4_3_1), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_1) +); + +wire [15:0] f29, f30, f31, f32, f33, f34, f35, f36; +assign f29 = -{feature_reg_1_3_1[13:0], 2'b00}; +assign f30 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f31 = -{feature_reg_2_3_1[13:0], 2'b00}; +assign f32 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f33 = -{feature_reg_3_1_1[13:0], 2'b00}; +assign f34 = -{feature_reg_3_2_1[13:0], 2'b00}; +assign f35 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f36 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA11 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0], 4'b0000}), + .data1x({feature_reg_1_2_1[11:0], 4'b0000}), + .data2x(f29), + .data3x(f30), + .data4x({feature_reg_2_1_1[11:0], 4'b0000}), + .data5x({feature_reg_2_2_1[11:0], 4'b0000}), + .data6x(f31), + .data7x(f32), + .data8x(f33), + .data9x(f34), + .data10x(feature_reg_3_3_1), + .data11x(feature_reg_3_4_1), + .data12x(f35), + .data13x(f36), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_1) +); + +wire [15:0] f37, f38, f39, f40, f41, f42, f43, f44; +assign f37 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f38 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f39 = -{feature_reg_2_3_1[13:0],2'b00}; +assign f40 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f41 = -feature_reg_3_3_1; +assign f42 = -feature_reg_3_4_1; +assign f43 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f44 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA21 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f37), + .data2x(f38), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[11:0],4'b0000}), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x(f39), + .data7x(f40), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(f41), + .data11x(f42), + .data12x(f43), + .data13x(f44), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_1) +); + +wire [15:0] f45, f46, f47, f48, f49, f50, f51, f52; +assign f45 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f46 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f47 = -feature_reg_2_3_1; +assign f48 = -feature_reg_2_4_1; +assign f49 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f50 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f51 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f52 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA31 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[12:0],3'b000}), + .data2x(f45), + .data3x(f46), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f47), + .data7x(f48), + .data8x(f49), + .data9x(f50), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f51), + .data13x(f52), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_1) +); + +wire [15:0] f53, f54, f55, f56, f57, f58, f59, f60; +assign f53 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f54 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f55 = -feature_reg_2_3_1; +assign f56 = -feature_reg_2_4_1; +assign f57 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f58 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f59 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f60 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA41 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[14:0],1'b0}), + .data1x(f53), + .data2x(f54), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f55), + .data7x(f56), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x(f57), + .data11x(f58), + .data12x(f59), + .data13x(f60), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_1) +); + +wire [15:0] f61, f62, f63, f64; +assign f61 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f62 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f63 = -{feature_reg_5_1_1[13:0],2'b00}; +assign f64 = -{feature_reg_5_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA51 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f61), + .data2x(f62), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_2_4), + .data5x(dsp_out_2_5), + .data6x(dsp_out_2_6), + .data7x(dsp_out_2_7), + .data8x(f63), + .data9x(f64), + .data10x(feature_reg_5_3_1), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_1) +); + +wire [15:0] f65, f66, f67, f68; +assign f65 = -{feature_reg_0_2_1[11:0],4'b0000}; +assign f66 = -{feature_reg_0_3_1[13:0],2'b00}; +assign f67 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f68 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA02 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(f65), + .data2x(f66), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_3_0), + .data5x(dsp_out_3_1), + .data6x(dsp_out_3_2), + .data7x(dsp_out_3_3), + .data8x({feature_reg_4_1_1[13:0],2'b00}), + .data9x(f67), + .data10x(f68), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_2) +); + +wire [15:0] f69, f70, f71, f72, f73, f74, f75, f76; +assign f69 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f70 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f71 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f72 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f73 = -{feature_reg_3_2_1[13:0],2'b00}; +assign f74 = -feature_reg_3_3_1; +assign f75 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f76 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA12 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[11:0],4'b0000}), + .data1x(f69), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f70), + .data4x(f71), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f72), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f73), + .data10x(f74), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f75), + .data14x(f76), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_2) +); + +wire [15:0] f77, f78, f79, f80, f81, f82, f83, f84; +assign f77 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f78 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f79 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f80 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f81 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f82 = -feature_reg_3_4_1; +assign f83 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f84 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA22 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f77), + .data2x(f78), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f79), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f80), + .data8x(f81), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(feature_reg_3_3_1), + .data11x(f82), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f83), + .data14x(f84), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_2) +); + +wire [15:0] f85, f86, f87, f88, f89, f90, f91, f92; +assign f85 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f86 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f87 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f88 = -feature_reg_2_4_1; +assign f89 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f90 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f91 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f92 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA32 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[12:0],3'b000}), + .data1x(f85), + .data2x({feature_reg_1_3_1[14:0],1'b0}), + .data3x(f86), + .data4x(f87), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f88), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x(f89), + .data10x(f90), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f91), + .data14x(f92), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_2) +); + +wire [15:0] f93, f94, f95, f96, f97, f98, f99, f100; +assign f93 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f94 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f95 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f96 = -feature_reg_2_4_1; +assign f97 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f98 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f99 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f100 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA42 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f93), + .data2x(f94), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f95), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f96), + .data8x(f97), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f98), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f99), + .data14x(f100), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_2) +); + +wire [15:0] f101, f102, f103, f104; +assign f101 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f102 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f103 = -{feature_reg_5_2_1[13:0],2'b00}; +assign f104 = -feature_reg_5_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA52 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f101), + .data2x(f102), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_3_4), + .data5x(dsp_out_3_5), + .data6x(dsp_out_3_6), + .data7x(dsp_out_3_7), + .data8x({feature_reg_5_1_1[13:0],2'b00}), + .data9x(f103), + .data10x(f104), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_2) +); + +wire [15:0] f105, f106, f107, f108; +assign f105 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f106 = -{feature_reg_0_1_1[12:0],3'b000}; +assign f107 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f108 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA03 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[12:0],3'b000}), + .data1x(f105), + .data2x(f106), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_4_0), + .data5x(dsp_out_4_1), + .data6x(dsp_out_4_2), + .data7x(dsp_out_4_3), + .data8x(f107), + .data9x(f108), + .data10x({feature_reg_4_3_1[14:0],1'b0}), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_3) +); + +wire [15:0] f109, f110, f111, f112, f113, f114, f115, f116; +assign f109 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f110 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f111 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f112 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f113 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f114 = -feature_reg_3_2_1; +assign f115 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f116 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA13 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[13:0],2'b00}), + .data2x(f109), + .data3x(f110), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f111), + .data7x(f112), + .data8x(f113), + .data9x(f114), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(feature_reg_3_4_1), + .data12x(f115), + .data13x(f116), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_3) +); + +wire [15:0] f117, f118, f119, f120, f121, f122, f123, f124; +assign f117 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f118 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f119 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f120 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f121 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f122 = -feature_reg_3_4_1; +assign f123 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f124 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA23 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f117), + .data2x(f118), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f119), + .data7x(f120), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(feature_reg_3_2_1), + .data10x(f121), + .data11x(f122), + .data12x(f123), + .data13x(f124), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_3) +); + +wire [15:0] f125, f126, f127, f128, f129, f130, f131, f132; +assign f125 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f126 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f127 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f128 = -feature_reg_2_4_1; +assign f129 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f130 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f131 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f132 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA33 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x({feature_reg_1_2_1[14:0],1'b0}), + .data2x(f125), + .data3x(f126), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f127), + .data7x(f128), + .data8x(f129), + .data9x(f130), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f131), + .data13x(f132), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_3) +); + +wire [15:0] f133, f134, f135, f136, f137, f138, f139, f140; +assign f133 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f134 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f135 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f136 = -feature_reg_2_4_1; +assign f137 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f138 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f139 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f140 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA43 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f133), + .data2x(f134), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f135), + .data7x(f136), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x(f137), + .data11x(f138), + .data12x(f139), + .data13x(f140), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_3) +); + +wire [15:0] f141, f142, f143, f144; +assign f141 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f142 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f143 = -{feature_reg_5_1_1[14:0],1'b0}; +assign f144 = -feature_reg_5_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA53 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f141), + .data2x(f142), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_4_4), + .data5x(dsp_out_4_5), + .data6x(dsp_out_4_6), + .data7x(dsp_out_4_7), + .data8x(f143), + .data9x(f144), + .data10x({feature_reg_5_3_1[14:0],1'b0}), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_3) +); + +wire [15:0] f145, f146, f147, f148; +assign f145 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f146 = -{feature_reg_0_3_1[12:0],3'b000}; +assign f147 = -feature_reg_4_2_1; +assign f148 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA04 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[12:0],3'b000}), + .data1x(f145), + .data2x(f146), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_5_0), + .data5x(dsp_out_5_1), + .data6x(dsp_out_5_2), + .data7x(dsp_out_5_3), + .data8x({feature_reg_4_1_1[14:0],1'b0}), + .data9x(f147), + .data10x(f148), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_4) +); + +wire [15:0] f149, f150, f151, f152, f153, f154, f155, f156; +assign f149 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f150 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f151 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f152 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f153 = -feature_reg_3_2_1; +assign f154 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f155 = -feature_reg_4_2_1; +assign f156 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA14 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[13:0],2'b00}), + .data1x(f149), + .data2x({feature_reg_1_3_1[12:0],3'b000}), + .data3x(f150), + .data4x(f151), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f152), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(f153), + .data10x(f154), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f155), + .data14x(f156), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_4) +); + +wire [15:0] f157, f158, f159, f160, f161, f162, f163, f164; +assign f157 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f158 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f159 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f160 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f161 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f162 = -feature_reg_3_4_1; +assign f163 = -feature_reg_4_2_1; +assign f164 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA24 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f157), + .data2x(f158), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f159), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f160), + .data8x(f161), + .data9x(feature_reg_3_2_1), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f162), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f163), + .data14x(f164), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_4) +); + +wire [15:0] f165, f166, f167, f168, f169, f170, f171, f172; +assign f165 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f166 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f167 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f168 = -feature_reg_2_4_1; +assign f169 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f170 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f171 = -feature_reg_4_2_1; +assign f172 = -{feature_reg_4_1_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA34 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[14:0],1'b0}), + .data1x(f165), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f166), + .data4x(f167), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f168), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f169), + .data10x(f170), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f171), + .data14x(f172), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_4) +); + +wire [15:0] f173, f174, f175, f176, f177, f178, f179, f180; +assign f173 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f174 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f175 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f176 = -feature_reg_2_4_1; +assign f177 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f178 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f179 = -feature_reg_4_2_1; +assign f180 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA44 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x(f173), + .data2x(f174), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f175), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f176), + .data8x(f177), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x(f178), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f179), + .data14x(f180), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_4) +); + +wire [15:0] f181, f182, f183, f184; +assign f181 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f182 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f183 = -feature_reg_5_2_1; +assign f184 = -{feature_reg_5_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA54 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f181), + .data2x(f182), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_5_4), + .data5x(dsp_out_5_5), + .data6x(dsp_out_5_6), + .data7x(dsp_out_5_7), + .data8x({feature_reg_5_1_1[14:0],1'b0}), + .data9x(f183), + .data10x(f184), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_4) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA05 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(dsp_out_6_0), + .data2x({feature_reg_0_5_1[13:0],2'b00}), + .data3x(dsp_out_6_1), + .data4x(dsp_out_6_2), + .data5x(dsp_out_6_3), + .data6x({feature_reg_4_1_1[13:0],2'b00}), + .data7x(dsp_out_6_4), + .data8x(feature_reg_4_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_5) +); + +wire [15:0] f185, f186, f187, f188; +assign f185 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f186 = -{feature_reg_1_5_1[13:0],2'b00}; +assign f187 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f188 = -{feature_reg_2_5_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA15 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_6_5), + .data1x(f185), + .data2x(f186), + .data3x(f187), + .data4x(dsp_out_6_6), + .data5x(f188), + .data6x({feature_reg_3_1_1[13:0],2'b00}), + .data7x(dsp_out_6_7), + .data8x(feature_reg_3_5_1), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_5) +); + +wire [15:0] f189, f190, f191, f192, f193, f194; +assign f189 = -dsp_out_6_5; +assign f190 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f191 = -{feature_reg_2_5_1[13:0],2'b00}; +assign f192 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f193 = -dsp_out_6_7; +assign f194 = -feature_reg_3_5_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA25 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f189), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(f190), + .data4x(dsp_out_6_6), + .data5x(f191), + .data6x(f192), + .data7x(f193), + .data8x(f194), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_5) +); + +wire [15:0] f195, f196, f197, f198, f199, f200, f201; +assign f195 = dsp_out_6_5 >>> 1; +assign f196 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f197 = -{feature_reg_1_5_1[14:0],1'b0}; +assign f198 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f199 = dsp_out_6_6 >>> 2; +assign f200 = -feature_reg_2_5_1; +assign f201 = dsp_out_6_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA35 ( + .clock(clk), + .clken(calculate_2), + .data0x(f195), + .data1x(f196), + .data2x(f197), + .data3x(f198), + .data4x(f199), + .data5x(f200), + .data6x({feature_reg_3_1_1[12:0],3'b000}), + .data7x(f201), + .data8x({feature_reg_3_5_1[14:0],1'b0}), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_5) +); + +wire [15:0] f202, f203, f204, f205, f206, f207, f208; +assign f202 = -(dsp_out_6_5 >>> 1); +assign f203 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f204 = dsp_out_6_6 >>> 2; +assign f205 = -feature_reg_2_5_1; +assign f206 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f207 = -(dsp_out_6_7 <<< 1); +assign f208 = -{feature_reg_3_5_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA45 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f202), + .data2x({feature_reg_1_5_1[14:0],1'b0}), + .data3x(f203), + .data4x(f204), + .data5x(f205), + .data6x(f206), + .data7x(f207), + .data8x(f208), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_5) +); + +wire [15:0] f209; +assign f209 = -dsp_out_6_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA55 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f209), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(dsp_out_6_8), + .data4x(dsp_out_6_9), + .data5x(dsp_out_6_10), + .data6x({feature_reg_5_1_1[13:0],2'b00}), + .data7x(dsp_out_6_11), + .data8x(feature_reg_5_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_5) +); + +assign o_feature_0 = output_buffer_0_0[15:0]; +assign o_feature_1 = output_buffer_1_0[15:0]; +assign o_feature_2 = output_buffer_2_0[15:0]; +assign o_feature_3 = output_buffer_3_0[15:0]; +assign o_feature_4 = output_buffer_4_0[15:0]; +assign o_feature_5 = output_buffer_5_0[15:0]; +assign o_valid = valid_9; + +endmodule + +module winograd_transform_2 ( + input clk, + input i_valid, + input [15:0] i_result_0_0, + input [15:0] i_result_0_1, + input [15:0] i_result_0_2, + input [15:0] i_result_0_3, + input [15:0] i_result_0_4, + input [15:0] i_result_0_5, + input [15:0] i_result_0_6, + input [15:0] i_result_0_7, + input [15:0] i_result_1_0, + input [15:0] i_result_1_1, + input [15:0] i_result_1_2, + input [15:0] i_result_1_3, + input [15:0] i_result_1_4, + input [15:0] i_result_1_5, + input [15:0] i_result_1_6, + input [15:0] i_result_1_7, + input [15:0] i_result_2_0, + input [15:0] i_result_2_1, + input [15:0] i_result_2_2, + input [15:0] i_result_2_3, + input [15:0] i_result_2_4, + input [15:0] i_result_2_5, + input [15:0] i_result_2_6, + input [15:0] i_result_2_7, + input [15:0] i_result_3_0, + input [15:0] i_result_3_1, + input [15:0] i_result_3_2, + input [15:0] i_result_3_3, + input [15:0] i_result_3_4, + input [15:0] i_result_3_5, + input [15:0] i_result_3_6, + input [15:0] i_result_3_7, + input [15:0] i_result_4_0, + input [15:0] i_result_4_1, + input [15:0] i_result_4_2, + input [15:0] i_result_4_3, + input [15:0] i_result_4_4, + input [15:0] i_result_4_5, + input [15:0] i_result_4_6, + input [15:0] i_result_4_7, + input [15:0] i_result_5_0, + input [15:0] i_result_5_1, + input [15:0] i_result_5_2, + input [15:0] i_result_5_3, + input [15:0] i_result_5_4, + input [15:0] i_result_5_5, + input [15:0] i_result_5_6, + input [15:0] i_result_5_7, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output [15:0] o_feature_2, + output [15:0] o_feature_3, + output [15:0] o_feature_4, + output [15:0] o_feature_5, + output o_valid +); + +reg [15:0] input_buffer_0_0; +reg [19:0] output_buffer_0_0; +wire [19:0] rslt_buffer_0_0; +reg [15:0] input_buffer_0_1; +reg [19:0] output_buffer_0_1; +wire [19:0] rslt_buffer_0_1; +reg [15:0] input_buffer_0_2; +reg [19:0] output_buffer_0_2; +wire [19:0] rslt_buffer_0_2; +reg [15:0] input_buffer_0_3; +reg [19:0] output_buffer_0_3; +wire [19:0] rslt_buffer_0_3; +reg [15:0] input_buffer_0_4; +reg [19:0] output_buffer_0_4; +wire [19:0] rslt_buffer_0_4; +reg [15:0] input_buffer_0_5; +reg [19:0] output_buffer_0_5; +wire [19:0] rslt_buffer_0_5; +reg [15:0] input_buffer_1_0; +reg [19:0] output_buffer_1_0; +wire [19:0] rslt_buffer_1_0; +reg [15:0] input_buffer_1_1; +reg [19:0] output_buffer_1_1; +wire [19:0] rslt_buffer_1_1; +reg [15:0] input_buffer_1_2; +reg [19:0] output_buffer_1_2; +wire [19:0] rslt_buffer_1_2; +reg [15:0] input_buffer_1_3; +reg [19:0] output_buffer_1_3; +wire [19:0] rslt_buffer_1_3; +reg [15:0] input_buffer_1_4; +reg [19:0] output_buffer_1_4; +wire [19:0] rslt_buffer_1_4; +reg [15:0] input_buffer_1_5; +reg [19:0] output_buffer_1_5; +wire [19:0] rslt_buffer_1_5; +reg [15:0] input_buffer_2_0; +reg [19:0] output_buffer_2_0; +wire [19:0] rslt_buffer_2_0; +reg [15:0] input_buffer_2_1; +reg [19:0] output_buffer_2_1; +wire [19:0] rslt_buffer_2_1; +reg [15:0] input_buffer_2_2; +reg [19:0] output_buffer_2_2; +wire [19:0] rslt_buffer_2_2; +reg [15:0] input_buffer_2_3; +reg [19:0] output_buffer_2_3; +wire [19:0] rslt_buffer_2_3; +reg [15:0] input_buffer_2_4; +reg [19:0] output_buffer_2_4; +wire [19:0] rslt_buffer_2_4; +reg [15:0] input_buffer_2_5; +reg [19:0] output_buffer_2_5; +wire [19:0] rslt_buffer_2_5; +reg [15:0] input_buffer_3_0; +reg [19:0] output_buffer_3_0; +wire [19:0] rslt_buffer_3_0; +reg [15:0] input_buffer_3_1; +reg [19:0] output_buffer_3_1; +wire [19:0] rslt_buffer_3_1; +reg [15:0] input_buffer_3_2; +reg [19:0] output_buffer_3_2; +wire [19:0] rslt_buffer_3_2; +reg [15:0] input_buffer_3_3; +reg [19:0] output_buffer_3_3; +wire [19:0] rslt_buffer_3_3; +reg [15:0] input_buffer_3_4; +reg [19:0] output_buffer_3_4; +wire [19:0] rslt_buffer_3_4; +reg [15:0] input_buffer_3_5; +reg [19:0] output_buffer_3_5; +wire [19:0] rslt_buffer_3_5; +reg [15:0] input_buffer_4_0; +reg [19:0] output_buffer_4_0; +wire [19:0] rslt_buffer_4_0; +reg [15:0] input_buffer_4_1; +reg [19:0] output_buffer_4_1; +wire [19:0] rslt_buffer_4_1; +reg [15:0] input_buffer_4_2; +reg [19:0] output_buffer_4_2; +wire [19:0] rslt_buffer_4_2; +reg [15:0] input_buffer_4_3; +reg [19:0] output_buffer_4_3; +wire [19:0] rslt_buffer_4_3; +reg [15:0] input_buffer_4_4; +reg [19:0] output_buffer_4_4; +wire [19:0] rslt_buffer_4_4; +reg [15:0] input_buffer_4_5; +reg [19:0] output_buffer_4_5; +wire [19:0] rslt_buffer_4_5; +reg [15:0] input_buffer_5_0; +reg [19:0] output_buffer_5_0; +wire [19:0] rslt_buffer_5_0; +reg [15:0] input_buffer_5_1; +reg [19:0] output_buffer_5_1; +wire [19:0] rslt_buffer_5_1; +reg [15:0] input_buffer_5_2; +reg [19:0] output_buffer_5_2; +wire [19:0] rslt_buffer_5_2; +reg [15:0] input_buffer_5_3; +reg [19:0] output_buffer_5_3; +wire [19:0] rslt_buffer_5_3; +reg [15:0] input_buffer_5_4; +reg [19:0] output_buffer_5_4; +wire [19:0] rslt_buffer_5_4; +reg [15:0] input_buffer_5_5; +reg [19:0] output_buffer_5_5; +wire [19:0] rslt_buffer_5_5; +reg calculate, calculate_1, calculate_2, calculate_3; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg valid_12; +reg [2:0] input_buffer_count; +wire [15:0] dsp_out_1_0; +wire [15:0] dsp_out_1_1; +wire [15:0] dsp_out_1_2; +wire [15:0] dsp_out_1_3; +wire [15:0] dsp_out_1_4; +wire [15:0] dsp_out_1_5; +wire [15:0] dsp_out_1_6; +wire [15:0] dsp_out_1_7; +wire [15:0] dsp_out_1_8; +wire [15:0] dsp_out_1_9; +wire [15:0] dsp_out_1_10; +wire [15:0] dsp_out_1_11; +wire [15:0] dsp_out_2_0; +wire [15:0] dsp_out_2_1; +wire [15:0] dsp_out_2_2; +wire [15:0] dsp_out_2_3; +wire [15:0] dsp_out_2_4; +wire [15:0] dsp_out_2_5; +wire [15:0] dsp_out_2_6; +wire [15:0] dsp_out_2_7; +wire [15:0] dsp_out_3_0; +wire [15:0] dsp_out_3_1; +wire [15:0] dsp_out_3_2; +wire [15:0] dsp_out_3_3; +wire [15:0] dsp_out_3_4; +wire [15:0] dsp_out_3_5; +wire [15:0] dsp_out_3_6; +wire [15:0] dsp_out_3_7; +wire [15:0] dsp_out_4_0; +wire [15:0] dsp_out_4_1; +wire [15:0] dsp_out_4_2; +wire [15:0] dsp_out_4_3; +wire [15:0] dsp_out_4_4; +wire [15:0] dsp_out_4_5; +wire [15:0] dsp_out_4_6; +wire [15:0] dsp_out_4_7; +wire [15:0] dsp_out_5_0; +wire [15:0] dsp_out_5_1; +wire [15:0] dsp_out_5_2; +wire [15:0] dsp_out_5_3; +wire [15:0] dsp_out_5_4; +wire [15:0] dsp_out_5_5; +wire [15:0] dsp_out_5_6; +wire [15:0] dsp_out_5_7; +wire [15:0] dsp_out_6_0; +wire [15:0] dsp_out_6_1; +wire [15:0] dsp_out_6_2; +wire [15:0] dsp_out_6_3; +wire [15:0] dsp_out_6_4; +wire [15:0] dsp_out_6_5; +wire [15:0] dsp_out_6_6; +wire [15:0] dsp_out_6_7; +wire [15:0] dsp_out_6_8; +wire [15:0] dsp_out_6_9; +wire [15:0] dsp_out_6_10; +wire [15:0] dsp_out_6_11; +reg [15:0] feature_reg_0_0_0; +reg [15:0] feature_reg_0_0_1; +reg [15:0] feature_reg_0_1_0; +reg [15:0] feature_reg_0_1_1; +reg [15:0] feature_reg_0_2_0; +reg [15:0] feature_reg_0_2_1; +reg [15:0] feature_reg_0_3_0; +reg [15:0] feature_reg_0_3_1; +reg [15:0] feature_reg_0_4_0; +reg [15:0] feature_reg_0_4_1; +reg [15:0] feature_reg_0_5_0; +reg [15:0] feature_reg_0_5_1; +reg [15:0] feature_reg_1_0_0; +reg [15:0] feature_reg_1_0_1; +reg [15:0] feature_reg_1_1_0; +reg [15:0] feature_reg_1_1_1; +reg [15:0] feature_reg_1_2_0; +reg [15:0] feature_reg_1_2_1; +reg [15:0] feature_reg_1_3_0; +reg [15:0] feature_reg_1_3_1; +reg [15:0] feature_reg_1_4_0; +reg [15:0] feature_reg_1_4_1; +reg [15:0] feature_reg_1_5_0; +reg [15:0] feature_reg_1_5_1; +reg [15:0] feature_reg_2_0_0; +reg [15:0] feature_reg_2_0_1; +reg [15:0] feature_reg_2_1_0; +reg [15:0] feature_reg_2_1_1; +reg [15:0] feature_reg_2_2_0; +reg [15:0] feature_reg_2_2_1; +reg [15:0] feature_reg_2_3_0; +reg [15:0] feature_reg_2_3_1; +reg [15:0] feature_reg_2_4_0; +reg [15:0] feature_reg_2_4_1; +reg [15:0] feature_reg_2_5_0; +reg [15:0] feature_reg_2_5_1; +reg [15:0] feature_reg_3_0_0; +reg [15:0] feature_reg_3_0_1; +reg [15:0] feature_reg_3_1_0; +reg [15:0] feature_reg_3_1_1; +reg [15:0] feature_reg_3_2_0; +reg [15:0] feature_reg_3_2_1; +reg [15:0] feature_reg_3_3_0; +reg [15:0] feature_reg_3_3_1; +reg [15:0] feature_reg_3_4_0; +reg [15:0] feature_reg_3_4_1; +reg [15:0] feature_reg_3_5_0; +reg [15:0] feature_reg_3_5_1; +reg [15:0] feature_reg_4_0_0; +reg [15:0] feature_reg_4_0_1; +reg [15:0] feature_reg_4_1_0; +reg [15:0] feature_reg_4_1_1; +reg [15:0] feature_reg_4_2_0; +reg [15:0] feature_reg_4_2_1; +reg [15:0] feature_reg_4_3_0; +reg [15:0] feature_reg_4_3_1; +reg [15:0] feature_reg_4_4_0; +reg [15:0] feature_reg_4_4_1; +reg [15:0] feature_reg_4_5_0; +reg [15:0] feature_reg_4_5_1; +reg [15:0] feature_reg_5_0_0; +reg [15:0] feature_reg_5_0_1; +reg [15:0] feature_reg_5_1_0; +reg [15:0] feature_reg_5_1_1; +reg [15:0] feature_reg_5_2_0; +reg [15:0] feature_reg_5_2_1; +reg [15:0] feature_reg_5_3_0; +reg [15:0] feature_reg_5_3_1; +reg [15:0] feature_reg_5_4_0; +reg [15:0] feature_reg_5_4_1; +reg [15:0] feature_reg_5_5_0; +reg [15:0] feature_reg_5_5_1; + +always @ (posedge clk) begin + calculate_1 <= calculate; + calculate_2 <= calculate_1; + calculate_3 <= calculate_2; + //Valid pipeline + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + valid_12 <= valid_11; + if (i_valid) begin + input_buffer_count <= 0; + calculate <= 0; + end else begin + //Input buffering logic + if (input_buffer_count == 5) begin + calculate <= 1; + input_buffer_count <= 0; + end else begin + calculate <= 0; + input_buffer_count <= input_buffer_count + 1'b1; + end + input_buffer_5_0 <= i_result_0_2; + input_buffer_5_1 <= i_result_1_2; + input_buffer_5_2 <= i_result_2_2; + input_buffer_5_3 <= i_result_3_2; + input_buffer_5_4 <= i_result_4_2; + input_buffer_5_5 <= i_result_5_2; + end + input_buffer_0_0 <= input_buffer_1_0; + input_buffer_0_1 <= input_buffer_1_1; + input_buffer_0_2 <= input_buffer_1_2; + input_buffer_0_3 <= input_buffer_1_3; + input_buffer_0_4 <= input_buffer_1_4; + input_buffer_0_5 <= input_buffer_1_5; + input_buffer_1_0 <= input_buffer_2_0; + input_buffer_1_1 <= input_buffer_2_1; + input_buffer_1_2 <= input_buffer_2_2; + input_buffer_1_3 <= input_buffer_2_3; + input_buffer_1_4 <= input_buffer_2_4; + input_buffer_1_5 <= input_buffer_2_5; + input_buffer_2_0 <= input_buffer_3_0; + input_buffer_2_1 <= input_buffer_3_1; + input_buffer_2_2 <= input_buffer_3_2; + input_buffer_2_3 <= input_buffer_3_3; + input_buffer_2_4 <= input_buffer_3_4; + input_buffer_2_5 <= input_buffer_3_5; + input_buffer_3_0 <= input_buffer_4_0; + input_buffer_3_1 <= input_buffer_4_1; + input_buffer_3_2 <= input_buffer_4_2; + input_buffer_3_3 <= input_buffer_4_3; + input_buffer_3_4 <= input_buffer_4_4; + input_buffer_3_5 <= input_buffer_4_5; + input_buffer_4_0 <= input_buffer_5_0; + input_buffer_4_1 <= input_buffer_5_1; + input_buffer_4_2 <= input_buffer_5_2; + input_buffer_4_3 <= input_buffer_5_3; + input_buffer_4_4 <= input_buffer_5_4; + input_buffer_4_5 <= input_buffer_5_5; + //Pipelining to synchronize DSPs and non-DSPs + feature_reg_0_0_0 <= input_buffer_0_0; + feature_reg_0_1_0 <= input_buffer_0_1; + feature_reg_0_2_0 <= input_buffer_0_2; + feature_reg_0_3_0 <= input_buffer_0_3; + feature_reg_0_4_0 <= input_buffer_0_4; + feature_reg_0_5_0 <= input_buffer_0_5; + feature_reg_1_0_0 <= input_buffer_1_0; + feature_reg_1_1_0 <= input_buffer_1_1; + feature_reg_1_2_0 <= input_buffer_1_2; + feature_reg_1_3_0 <= input_buffer_1_3; + feature_reg_1_4_0 <= input_buffer_1_4; + feature_reg_1_5_0 <= input_buffer_1_5; + feature_reg_2_0_0 <= input_buffer_2_0; + feature_reg_2_1_0 <= input_buffer_2_1; + feature_reg_2_2_0 <= input_buffer_2_2; + feature_reg_2_3_0 <= input_buffer_2_3; + feature_reg_2_4_0 <= input_buffer_2_4; + feature_reg_2_5_0 <= input_buffer_2_5; + feature_reg_3_0_0 <= input_buffer_3_0; + feature_reg_3_1_0 <= input_buffer_3_1; + feature_reg_3_2_0 <= input_buffer_3_2; + feature_reg_3_3_0 <= input_buffer_3_3; + feature_reg_3_4_0 <= input_buffer_3_4; + feature_reg_3_5_0 <= input_buffer_3_5; + feature_reg_4_0_0 <= input_buffer_4_0; + feature_reg_4_1_0 <= input_buffer_4_1; + feature_reg_4_2_0 <= input_buffer_4_2; + feature_reg_4_3_0 <= input_buffer_4_3; + feature_reg_4_4_0 <= input_buffer_4_4; + feature_reg_4_5_0 <= input_buffer_4_5; + feature_reg_5_0_0 <= input_buffer_5_0; + feature_reg_5_1_0 <= input_buffer_5_1; + feature_reg_5_2_0 <= input_buffer_5_2; + feature_reg_5_3_0 <= input_buffer_5_3; + feature_reg_5_4_0 <= input_buffer_5_4; + feature_reg_5_5_0 <= input_buffer_5_5; + feature_reg_0_0_1 <= feature_reg_0_0_0; + feature_reg_0_1_1 <= feature_reg_0_1_0; + feature_reg_0_2_1 <= feature_reg_0_2_0; + feature_reg_0_3_1 <= feature_reg_0_3_0; + feature_reg_0_4_1 <= feature_reg_0_4_0; + feature_reg_0_5_1 <= feature_reg_0_5_0; + feature_reg_1_0_1 <= feature_reg_1_0_0; + feature_reg_1_1_1 <= feature_reg_1_1_0; + feature_reg_1_2_1 <= feature_reg_1_2_0; + feature_reg_1_3_1 <= feature_reg_1_3_0; + feature_reg_1_4_1 <= feature_reg_1_4_0; + feature_reg_1_5_1 <= feature_reg_1_5_0; + feature_reg_2_0_1 <= feature_reg_2_0_0; + feature_reg_2_1_1 <= feature_reg_2_1_0; + feature_reg_2_2_1 <= feature_reg_2_2_0; + feature_reg_2_3_1 <= feature_reg_2_3_0; + feature_reg_2_4_1 <= feature_reg_2_4_0; + feature_reg_2_5_1 <= feature_reg_2_5_0; + feature_reg_3_0_1 <= feature_reg_3_0_0; + feature_reg_3_1_1 <= feature_reg_3_1_0; + feature_reg_3_2_1 <= feature_reg_3_2_0; + feature_reg_3_3_1 <= feature_reg_3_3_0; + feature_reg_3_4_1 <= feature_reg_3_4_0; + feature_reg_3_5_1 <= feature_reg_3_5_0; + feature_reg_4_0_1 <= feature_reg_4_0_0; + feature_reg_4_1_1 <= feature_reg_4_1_0; + feature_reg_4_2_1 <= feature_reg_4_2_0; + feature_reg_4_3_1 <= feature_reg_4_3_0; + feature_reg_4_4_1 <= feature_reg_4_4_0; + feature_reg_4_5_1 <= feature_reg_4_5_0; + feature_reg_5_0_1 <= feature_reg_5_0_0; + feature_reg_5_1_1 <= feature_reg_5_1_0; + feature_reg_5_2_1 <= feature_reg_5_2_0; + feature_reg_5_3_1 <= feature_reg_5_3_0; + feature_reg_5_4_1 <= feature_reg_5_4_0; + feature_reg_5_5_1 <= feature_reg_5_5_0; + //Output Serializing logic + if (calculate_3) begin + output_buffer_0_0 <= rslt_buffer_0_0; + output_buffer_1_0 <= rslt_buffer_0_1; + output_buffer_2_0 <= rslt_buffer_0_2; + output_buffer_3_0 <= rslt_buffer_0_3; + output_buffer_4_0 <= rslt_buffer_0_4; + output_buffer_5_0 <= rslt_buffer_0_5; + output_buffer_0_1 <= rslt_buffer_1_0; + output_buffer_1_1 <= rslt_buffer_1_1; + output_buffer_2_1 <= rslt_buffer_1_2; + output_buffer_3_1 <= rslt_buffer_1_3; + output_buffer_4_1 <= rslt_buffer_1_4; + output_buffer_5_1 <= rslt_buffer_1_5; + output_buffer_0_2 <= rslt_buffer_2_0; + output_buffer_1_2 <= rslt_buffer_2_1; + output_buffer_2_2 <= rslt_buffer_2_2; + output_buffer_3_2 <= rslt_buffer_2_3; + output_buffer_4_2 <= rslt_buffer_2_4; + output_buffer_5_2 <= rslt_buffer_2_5; + output_buffer_0_3 <= rslt_buffer_3_0; + output_buffer_1_3 <= rslt_buffer_3_1; + output_buffer_2_3 <= rslt_buffer_3_2; + output_buffer_3_3 <= rslt_buffer_3_3; + output_buffer_4_3 <= rslt_buffer_3_4; + output_buffer_5_3 <= rslt_buffer_3_5; + output_buffer_0_4 <= rslt_buffer_4_0; + output_buffer_1_4 <= rslt_buffer_4_1; + output_buffer_2_4 <= rslt_buffer_4_2; + output_buffer_3_4 <= rslt_buffer_4_3; + output_buffer_4_4 <= rslt_buffer_4_4; + output_buffer_5_4 <= rslt_buffer_4_5; + output_buffer_0_5 <= rslt_buffer_5_0; + output_buffer_1_5 <= rslt_buffer_5_1; + output_buffer_2_5 <= rslt_buffer_5_2; + output_buffer_3_5 <= rslt_buffer_5_3; + output_buffer_4_5 <= rslt_buffer_5_4; + output_buffer_5_5 <= rslt_buffer_5_5; + end else begin + output_buffer_0_0 <= output_buffer_0_1; + output_buffer_0_1 <= output_buffer_0_2; + output_buffer_0_2 <= output_buffer_0_3; + output_buffer_0_3 <= output_buffer_0_4; + output_buffer_0_4 <= output_buffer_0_5; + output_buffer_1_0 <= output_buffer_1_1; + output_buffer_1_1 <= output_buffer_1_2; + output_buffer_1_2 <= output_buffer_1_3; + output_buffer_1_3 <= output_buffer_1_4; + output_buffer_1_4 <= output_buffer_1_5; + output_buffer_2_0 <= output_buffer_2_1; + output_buffer_2_1 <= output_buffer_2_2; + output_buffer_2_2 <= output_buffer_2_3; + output_buffer_2_3 <= output_buffer_2_4; + output_buffer_2_4 <= output_buffer_2_5; + output_buffer_3_0 <= output_buffer_3_1; + output_buffer_3_1 <= output_buffer_3_2; + output_buffer_3_2 <= output_buffer_3_3; + output_buffer_3_3 <= output_buffer_3_4; + output_buffer_3_4 <= output_buffer_3_5; + output_buffer_4_0 <= output_buffer_4_1; + output_buffer_4_1 <= output_buffer_4_2; + output_buffer_4_2 <= output_buffer_4_3; + output_buffer_4_3 <= output_buffer_4_4; + output_buffer_4_4 <= output_buffer_4_5; + output_buffer_5_0 <= output_buffer_5_1; + output_buffer_5_1 <= output_buffer_5_2; + output_buffer_5_2 <= output_buffer_5_3; + output_buffer_5_3 <= output_buffer_5_4; + output_buffer_5_4 <= output_buffer_5_5; + end +end + +////// FIRST COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD00 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_2), + .by(input_buffer_2_0), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_1_0), + .resultb(dsp_out_1_1) +); + +winograd_dsp_16 winograd_dsp_16_WD10 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_2_4), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_1_2), + .resultb(dsp_out_1_3) +); + +winograd_dsp_16 winograd_dsp_16_WD20 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_2), + .by(input_buffer_1_0), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_1_4), + .resultb(dsp_out_1_5) +); + +winograd_dsp_16 winograd_dsp_16_WD30 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_1_6), + .resultb(dsp_out_1_7) +); + +winograd_dsp_16 winograd_dsp_16_WD40 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_0), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_1_8), + .resultb(dsp_out_1_9) +); + +winograd_dsp_16 winograd_dsp_16_WD50 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_4), + .by(input_buffer_5_2), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_1_10), + .resultb(dsp_out_1_11) +); + +////// SECOND COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD01 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_0), + .resultb(dsp_out_2_1) +); + +winograd_dsp_16 winograd_dsp_16_WD11 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_2), + .resultb(dsp_out_2_3) +); + +winograd_dsp_16 winograd_dsp_16_WD21 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_4), + .resultb(dsp_out_2_5) +); + +winograd_dsp_16 winograd_dsp_16_WD31 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_6), + .resultb(dsp_out_2_7) +); + +////// THIRD COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD02 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_0), + .resultb(dsp_out_3_1) +); + +winograd_dsp_16 winograd_dsp_16_WD12 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_2), + .resultb(dsp_out_3_3) +); + +winograd_dsp_16 winograd_dsp_16_WD22 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_4), + .resultb(dsp_out_3_5) +); + +winograd_dsp_16 winograd_dsp_16_WD32 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_6), + .resultb(dsp_out_3_7) +); + +////// FOURTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD03 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_0), + .resultb(dsp_out_4_1) +); + +winograd_dsp_16 winograd_dsp_16_WD13 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_2), + .resultb(dsp_out_4_3) +); + +winograd_dsp_16 winograd_dsp_16_WD23 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_4), + .resultb(dsp_out_4_5) +); + +winograd_dsp_16 winograd_dsp_16_WD33 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_6), + .resultb(dsp_out_4_7) +); + +////// FIFTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD04 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_0), + .resultb(dsp_out_5_1) +); + +winograd_dsp_16 winograd_dsp_16_WD14 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_2), + .resultb(dsp_out_5_3) +); + +winograd_dsp_16 winograd_dsp_16_WD24 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_4), + .resultb(dsp_out_5_5) +); + +winograd_dsp_16 winograd_dsp_16_WD34 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_6), + .resultb(dsp_out_5_7) +); + +////// SIXTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD05 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_3), + .by(input_buffer_2_1), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_6_0), + .resultb(dsp_out_6_1) +); + +winograd_dsp_16 winograd_dsp_16_WD15 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_5), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_6_2), + .resultb(dsp_out_6_3) +); + +winograd_dsp_16 winograd_dsp_16_WD25 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_3), + .by(input_buffer_1_3), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_6_4), + .resultb(dsp_out_6_5) +); + +winograd_dsp_16 winograd_dsp_16_WD35 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_3_3), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_6_6), + .resultb(dsp_out_6_7) +); + +winograd_dsp_16 winograd_dsp_16_WD45 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_3), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_6_8), + .resultb(dsp_out_6_9) +); + +winograd_dsp_16 winograd_dsp_16_WD55 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_5), + .by(input_buffer_5_3), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_6_10), + .resultb(dsp_out_6_11) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA00 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_0_1[11:0], 4'b0000}), + .data1x(dsp_out_1_0), + .data2x({feature_reg_0_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_1), + .data4x(dsp_out_1_2), + .data5x(dsp_out_1_3), + .data6x({feature_reg_4_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_4), + .data8x(feature_reg_4_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_0) +); + +wire [15:0] f1, f2, f3, f4; +assign f1 = -{feature_reg_1_0_1[11:0], 4'b0000}; +assign f2 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f3 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f4 = -{feature_reg_2_4_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA10 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_1_5), + .data1x(f1), + .data2x(f2), + .data3x(f3), + .data4x(dsp_out_1_6), + .data5x(f4), + .data6x({feature_reg_3_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_7), + .data8x(feature_reg_3_4_1), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_0) +); + +wire [15:0] f5, f6, f7, f8, f9, f10; +assign f5 = -dsp_out_1_5; +assign f6 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f7 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f8 = -{feature_reg_3_0_1[13:0], 2'b00}; +assign f9 = -dsp_out_1_7; +assign f10 = -feature_reg_3_4_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA20 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f5), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(f6), + .data4x(dsp_out_1_6), + .data5x(f7), + .data6x(f8), + .data7x(f9), + .data8x(f10), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_0) +); + +wire [15:0] f11, f12, f13, f14, f15, f16, f17; +assign f11 = -{feature_reg_1_0_1[12:0], 3'b000}; +assign f12 = -{feature_reg_1_4_1[14:0], 1'b0}; +assign f13 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f14 = -feature_reg_2_4_1; +assign f15 = dsp_out_1_5 >>> 1; +assign f16 = dsp_out_1_6 >>> 2; +assign f17 = dsp_out_1_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA30 ( + .clock(clk), + .clken(calculate_2), + .data0x(f15), + .data1x(f11), + .data2x(f12), + .data3x(f13), + .data4x(f16), + .data5x(f14), + .data6x({feature_reg_3_0_1[12:0], 3'b000}), + .data7x(f17), + .data8x({feature_reg_3_4_1[14:0], 1'b0}), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_0) +); + +wire [15:0] f18, f19, f20, f21, f22, f23, f23b; +assign f18 = -(dsp_out_1_5 >>> 1); +assign f19 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f20 = -feature_reg_2_4_1; +assign f21 = -{feature_reg_3_0_1[12:0], 3'b000}; +assign f22 = -(dsp_out_1_7 <<< 1); +assign f23 = -{feature_reg_3_4_1[14:0], 1'b0}; +assign f23b = dsp_out_1_6 >>> 2; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA40 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[12:0], 3'b000}), + .data1x(f18), + .data2x({feature_reg_1_4_1[14:0], 1'b0}), + .data3x(f19), + .data4x(f23b), + .data5x(f20), + .data6x(f21), + .data7x(f22), + .data8x(f23), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_0) +); + +wire [15:0] f24; +assign f24 = -dsp_out_1_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA50 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f24), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_8), + .data4x(dsp_out_1_9), + .data5x(dsp_out_1_10), + .data6x({feature_reg_5_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_11), + .data8x(feature_reg_5_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_0) +); + +wire [15:0] f25, f26, f27, f28; +assign f25 = -{feature_reg_0_2_1[11:0], 4'b0000}; +assign f26 = -{feature_reg_0_1_1[11:0], 4'b0000}; +assign f27 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f28 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA01 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[13:0], 2'b00}), + .data1x(f25), + .data2x(f26), + .data3x({feature_reg_0_4_1[13:0], 2'b00}), + .data4x(dsp_out_2_0), + .data5x(dsp_out_2_1), + .data6x(dsp_out_2_2), + .data7x(dsp_out_2_3), + .data8x(f27), + .data9x(f28), + .data10x(feature_reg_4_3_1), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_1) +); + +wire [15:0] f29, f30, f31, f32, f33, f34, f35, f36; +assign f29 = -{feature_reg_1_3_1[13:0], 2'b00}; +assign f30 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f31 = -{feature_reg_2_3_1[13:0], 2'b00}; +assign f32 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f33 = -{feature_reg_3_1_1[13:0], 2'b00}; +assign f34 = -{feature_reg_3_2_1[13:0], 2'b00}; +assign f35 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f36 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA11 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0], 4'b0000}), + .data1x({feature_reg_1_2_1[11:0], 4'b0000}), + .data2x(f29), + .data3x(f30), + .data4x({feature_reg_2_1_1[11:0], 4'b0000}), + .data5x({feature_reg_2_2_1[11:0], 4'b0000}), + .data6x(f31), + .data7x(f32), + .data8x(f33), + .data9x(f34), + .data10x(feature_reg_3_3_1), + .data11x(feature_reg_3_4_1), + .data12x(f35), + .data13x(f36), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_1) +); + +wire [15:0] f37, f38, f39, f40, f41, f42, f43, f44; +assign f37 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f38 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f39 = -{feature_reg_2_3_1[13:0],2'b00}; +assign f40 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f41 = -feature_reg_3_3_1; +assign f42 = -feature_reg_3_4_1; +assign f43 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f44 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA21 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f37), + .data2x(f38), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[11:0],4'b0000}), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x(f39), + .data7x(f40), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(f41), + .data11x(f42), + .data12x(f43), + .data13x(f44), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_1) +); + +wire [15:0] f45, f46, f47, f48, f49, f50, f51, f52; +assign f45 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f46 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f47 = -feature_reg_2_3_1; +assign f48 = -feature_reg_2_4_1; +assign f49 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f50 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f51 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f52 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA31 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[12:0],3'b000}), + .data2x(f45), + .data3x(f46), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f47), + .data7x(f48), + .data8x(f49), + .data9x(f50), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f51), + .data13x(f52), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_1) +); + +wire [15:0] f53, f54, f55, f56, f57, f58, f59, f60; +assign f53 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f54 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f55 = -feature_reg_2_3_1; +assign f56 = -feature_reg_2_4_1; +assign f57 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f58 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f59 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f60 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA41 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[14:0],1'b0}), + .data1x(f53), + .data2x(f54), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f55), + .data7x(f56), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x(f57), + .data11x(f58), + .data12x(f59), + .data13x(f60), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_1) +); + +wire [15:0] f61, f62, f63, f64; +assign f61 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f62 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f63 = -{feature_reg_5_1_1[13:0],2'b00}; +assign f64 = -{feature_reg_5_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA51 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f61), + .data2x(f62), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_2_4), + .data5x(dsp_out_2_5), + .data6x(dsp_out_2_6), + .data7x(dsp_out_2_7), + .data8x(f63), + .data9x(f64), + .data10x(feature_reg_5_3_1), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_1) +); + +wire [15:0] f65, f66, f67, f68; +assign f65 = -{feature_reg_0_2_1[11:0],4'b0000}; +assign f66 = -{feature_reg_0_3_1[13:0],2'b00}; +assign f67 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f68 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA02 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(f65), + .data2x(f66), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_3_0), + .data5x(dsp_out_3_1), + .data6x(dsp_out_3_2), + .data7x(dsp_out_3_3), + .data8x({feature_reg_4_1_1[13:0],2'b00}), + .data9x(f67), + .data10x(f68), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_2) +); + +wire [15:0] f69, f70, f71, f72, f73, f74, f75, f76; +assign f69 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f70 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f71 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f72 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f73 = -{feature_reg_3_2_1[13:0],2'b00}; +assign f74 = -feature_reg_3_3_1; +assign f75 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f76 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA12 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[11:0],4'b0000}), + .data1x(f69), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f70), + .data4x(f71), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f72), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f73), + .data10x(f74), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f75), + .data14x(f76), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_2) +); + +wire [15:0] f77, f78, f79, f80, f81, f82, f83, f84; +assign f77 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f78 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f79 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f80 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f81 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f82 = -feature_reg_3_4_1; +assign f83 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f84 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA22 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f77), + .data2x(f78), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f79), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f80), + .data8x(f81), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(feature_reg_3_3_1), + .data11x(f82), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f83), + .data14x(f84), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_2) +); + +wire [15:0] f85, f86, f87, f88, f89, f90, f91, f92; +assign f85 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f86 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f87 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f88 = -feature_reg_2_4_1; +assign f89 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f90 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f91 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f92 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA32 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[12:0],3'b000}), + .data1x(f85), + .data2x({feature_reg_1_3_1[14:0],1'b0}), + .data3x(f86), + .data4x(f87), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f88), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x(f89), + .data10x(f90), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f91), + .data14x(f92), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_2) +); + +wire [15:0] f93, f94, f95, f96, f97, f98, f99, f100; +assign f93 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f94 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f95 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f96 = -feature_reg_2_4_1; +assign f97 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f98 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f99 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f100 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA42 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f93), + .data2x(f94), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f95), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f96), + .data8x(f97), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f98), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f99), + .data14x(f100), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_2) +); + +wire [15:0] f101, f102, f103, f104; +assign f101 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f102 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f103 = -{feature_reg_5_2_1[13:0],2'b00}; +assign f104 = -feature_reg_5_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA52 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f101), + .data2x(f102), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_3_4), + .data5x(dsp_out_3_5), + .data6x(dsp_out_3_6), + .data7x(dsp_out_3_7), + .data8x({feature_reg_5_1_1[13:0],2'b00}), + .data9x(f103), + .data10x(f104), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_2) +); + +wire [15:0] f105, f106, f107, f108; +assign f105 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f106 = -{feature_reg_0_1_1[12:0],3'b000}; +assign f107 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f108 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA03 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[12:0],3'b000}), + .data1x(f105), + .data2x(f106), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_4_0), + .data5x(dsp_out_4_1), + .data6x(dsp_out_4_2), + .data7x(dsp_out_4_3), + .data8x(f107), + .data9x(f108), + .data10x({feature_reg_4_3_1[14:0],1'b0}), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_3) +); + +wire [15:0] f109, f110, f111, f112, f113, f114, f115, f116; +assign f109 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f110 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f111 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f112 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f113 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f114 = -feature_reg_3_2_1; +assign f115 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f116 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA13 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[13:0],2'b00}), + .data2x(f109), + .data3x(f110), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f111), + .data7x(f112), + .data8x(f113), + .data9x(f114), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(feature_reg_3_4_1), + .data12x(f115), + .data13x(f116), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_3) +); + +wire [15:0] f117, f118, f119, f120, f121, f122, f123, f124; +assign f117 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f118 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f119 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f120 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f121 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f122 = -feature_reg_3_4_1; +assign f123 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f124 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA23 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f117), + .data2x(f118), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f119), + .data7x(f120), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(feature_reg_3_2_1), + .data10x(f121), + .data11x(f122), + .data12x(f123), + .data13x(f124), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_3) +); + +wire [15:0] f125, f126, f127, f128, f129, f130, f131, f132; +assign f125 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f126 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f127 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f128 = -feature_reg_2_4_1; +assign f129 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f130 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f131 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f132 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA33 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x({feature_reg_1_2_1[14:0],1'b0}), + .data2x(f125), + .data3x(f126), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f127), + .data7x(f128), + .data8x(f129), + .data9x(f130), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f131), + .data13x(f132), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_3) +); + +wire [15:0] f133, f134, f135, f136, f137, f138, f139, f140; +assign f133 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f134 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f135 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f136 = -feature_reg_2_4_1; +assign f137 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f138 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f139 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f140 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA43 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f133), + .data2x(f134), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f135), + .data7x(f136), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x(f137), + .data11x(f138), + .data12x(f139), + .data13x(f140), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_3) +); + +wire [15:0] f141, f142, f143, f144; +assign f141 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f142 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f143 = -{feature_reg_5_1_1[14:0],1'b0}; +assign f144 = -feature_reg_5_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA53 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f141), + .data2x(f142), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_4_4), + .data5x(dsp_out_4_5), + .data6x(dsp_out_4_6), + .data7x(dsp_out_4_7), + .data8x(f143), + .data9x(f144), + .data10x({feature_reg_5_3_1[14:0],1'b0}), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_3) +); + +wire [15:0] f145, f146, f147, f148; +assign f145 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f146 = -{feature_reg_0_3_1[12:0],3'b000}; +assign f147 = -feature_reg_4_2_1; +assign f148 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA04 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[12:0],3'b000}), + .data1x(f145), + .data2x(f146), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_5_0), + .data5x(dsp_out_5_1), + .data6x(dsp_out_5_2), + .data7x(dsp_out_5_3), + .data8x({feature_reg_4_1_1[14:0],1'b0}), + .data9x(f147), + .data10x(f148), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_4) +); + +wire [15:0] f149, f150, f151, f152, f153, f154, f155, f156; +assign f149 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f150 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f151 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f152 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f153 = -feature_reg_3_2_1; +assign f154 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f155 = -feature_reg_4_2_1; +assign f156 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA14 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[13:0],2'b00}), + .data1x(f149), + .data2x({feature_reg_1_3_1[12:0],3'b000}), + .data3x(f150), + .data4x(f151), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f152), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(f153), + .data10x(f154), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f155), + .data14x(f156), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_4) +); + +wire [15:0] f157, f158, f159, f160, f161, f162, f163, f164; +assign f157 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f158 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f159 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f160 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f161 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f162 = -feature_reg_3_4_1; +assign f163 = -feature_reg_4_2_1; +assign f164 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA24 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f157), + .data2x(f158), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f159), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f160), + .data8x(f161), + .data9x(feature_reg_3_2_1), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f162), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f163), + .data14x(f164), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_4) +); + +wire [15:0] f165, f166, f167, f168, f169, f170, f171, f172; +assign f165 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f166 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f167 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f168 = -feature_reg_2_4_1; +assign f169 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f170 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f171 = -feature_reg_4_2_1; +assign f172 = -{feature_reg_4_1_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA34 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[14:0],1'b0}), + .data1x(f165), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f166), + .data4x(f167), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f168), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f169), + .data10x(f170), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f171), + .data14x(f172), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_4) +); + +wire [15:0] f173, f174, f175, f176, f177, f178, f179, f180; +assign f173 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f174 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f175 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f176 = -feature_reg_2_4_1; +assign f177 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f178 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f179 = -feature_reg_4_2_1; +assign f180 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA44 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x(f173), + .data2x(f174), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f175), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f176), + .data8x(f177), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x(f178), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f179), + .data14x(f180), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_4) +); + +wire [15:0] f181, f182, f183, f184; +assign f181 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f182 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f183 = -feature_reg_5_2_1; +assign f184 = -{feature_reg_5_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA54 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f181), + .data2x(f182), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_5_4), + .data5x(dsp_out_5_5), + .data6x(dsp_out_5_6), + .data7x(dsp_out_5_7), + .data8x({feature_reg_5_1_1[14:0],1'b0}), + .data9x(f183), + .data10x(f184), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_4) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA05 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(dsp_out_6_0), + .data2x({feature_reg_0_5_1[13:0],2'b00}), + .data3x(dsp_out_6_1), + .data4x(dsp_out_6_2), + .data5x(dsp_out_6_3), + .data6x({feature_reg_4_1_1[13:0],2'b00}), + .data7x(dsp_out_6_4), + .data8x(feature_reg_4_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_5) +); + +wire [15:0] f185, f186, f187, f188; +assign f185 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f186 = -{feature_reg_1_5_1[13:0],2'b00}; +assign f187 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f188 = -{feature_reg_2_5_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA15 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_6_5), + .data1x(f185), + .data2x(f186), + .data3x(f187), + .data4x(dsp_out_6_6), + .data5x(f188), + .data6x({feature_reg_3_1_1[13:0],2'b00}), + .data7x(dsp_out_6_7), + .data8x(feature_reg_3_5_1), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_5) +); + +wire [15:0] f189, f190, f191, f192, f193, f194; +assign f189 = -dsp_out_6_5; +assign f190 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f191 = -{feature_reg_2_5_1[13:0],2'b00}; +assign f192 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f193 = -dsp_out_6_7; +assign f194 = -feature_reg_3_5_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA25 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f189), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(f190), + .data4x(dsp_out_6_6), + .data5x(f191), + .data6x(f192), + .data7x(f193), + .data8x(f194), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_5) +); + +wire [15:0] f195, f196, f197, f198, f199, f200, f201; +assign f195 = dsp_out_6_5 >>> 1; +assign f196 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f197 = -{feature_reg_1_5_1[14:0],1'b0}; +assign f198 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f199 = dsp_out_6_6 >>> 2; +assign f200 = -feature_reg_2_5_1; +assign f201 = dsp_out_6_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA35 ( + .clock(clk), + .clken(calculate_2), + .data0x(f195), + .data1x(f196), + .data2x(f197), + .data3x(f198), + .data4x(f199), + .data5x(f200), + .data6x({feature_reg_3_1_1[12:0],3'b000}), + .data7x(f201), + .data8x({feature_reg_3_5_1[14:0],1'b0}), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_5) +); + +wire [15:0] f202, f203, f204, f205, f206, f207, f208; +assign f202 = -(dsp_out_6_5 >>> 1); +assign f203 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f204 = dsp_out_6_6 >>> 2; +assign f205 = -feature_reg_2_5_1; +assign f206 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f207 = -(dsp_out_6_7 <<< 1); +assign f208 = -{feature_reg_3_5_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA45 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f202), + .data2x({feature_reg_1_5_1[14:0],1'b0}), + .data3x(f203), + .data4x(f204), + .data5x(f205), + .data6x(f206), + .data7x(f207), + .data8x(f208), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_5) +); + +wire [15:0] f209; +assign f209 = -dsp_out_6_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA55 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f209), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(dsp_out_6_8), + .data4x(dsp_out_6_9), + .data5x(dsp_out_6_10), + .data6x({feature_reg_5_1_1[13:0],2'b00}), + .data7x(dsp_out_6_11), + .data8x(feature_reg_5_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_5) +); + +assign o_feature_0 = output_buffer_0_0[15:0]; +assign o_feature_1 = output_buffer_1_0[15:0]; +assign o_feature_2 = output_buffer_2_0[15:0]; +assign o_feature_3 = output_buffer_3_0[15:0]; +assign o_feature_4 = output_buffer_4_0[15:0]; +assign o_feature_5 = output_buffer_5_0[15:0]; +assign o_valid = valid_9; + +endmodule + +module signal_width_reducer ( + input clk, + input [15:0] signals_0_0, + output reduced_signals_0_0, + input [15:0] signals_0_1, + output reduced_signals_0_1, + input [15:0] signals_0_2, + output reduced_signals_0_2, + input [15:0] signals_0_3, + output reduced_signals_0_3, + input [15:0] signals_0_4, + output reduced_signals_0_4, + input [15:0] signals_0_5, + output reduced_signals_0_5, + input [15:0] signals_0_6, + output reduced_signals_0_6, + input [15:0] signals_0_7, + output reduced_signals_0_7, + input [15:0] signals_1_0, + output reduced_signals_1_0, + input [15:0] signals_1_1, + output reduced_signals_1_1, + input [15:0] signals_1_2, + output reduced_signals_1_2, + input [15:0] signals_1_3, + output reduced_signals_1_3, + input [15:0] signals_1_4, + output reduced_signals_1_4, + input [15:0] signals_1_5, + output reduced_signals_1_5, + input [15:0] signals_1_6, + output reduced_signals_1_6, + input [15:0] signals_1_7, + output reduced_signals_1_7, + input [15:0] signals_2_0, + output reduced_signals_2_0, + input [15:0] signals_2_1, + output reduced_signals_2_1, + input [15:0] signals_2_2, + output reduced_signals_2_2, + input [15:0] signals_2_3, + output reduced_signals_2_3, + input [15:0] signals_2_4, + output reduced_signals_2_4, + input [15:0] signals_2_5, + output reduced_signals_2_5, + input [15:0] signals_2_6, + output reduced_signals_2_6, + input [15:0] signals_2_7, + output reduced_signals_2_7, + input [15:0] signals_3_0, + output reduced_signals_3_0, + input [15:0] signals_3_1, + output reduced_signals_3_1, + input [15:0] signals_3_2, + output reduced_signals_3_2, + input [15:0] signals_3_3, + output reduced_signals_3_3, + input [15:0] signals_3_4, + output reduced_signals_3_4, + input [15:0] signals_3_5, + output reduced_signals_3_5, + input [15:0] signals_3_6, + output reduced_signals_3_6, + input [15:0] signals_3_7, + output reduced_signals_3_7, + input [15:0] signals_4_0, + output reduced_signals_4_0, + input [15:0] signals_4_1, + output reduced_signals_4_1, + input [15:0] signals_4_2, + output reduced_signals_4_2, + input [15:0] signals_4_3, + output reduced_signals_4_3, + input [15:0] signals_4_4, + output reduced_signals_4_4, + input [15:0] signals_4_5, + output reduced_signals_4_5, + input [15:0] signals_4_6, + output reduced_signals_4_6, + input [15:0] signals_4_7, + output reduced_signals_4_7, + input [15:0] signals_5_0, + output reduced_signals_5_0, + input [15:0] signals_5_1, + output reduced_signals_5_1, + input [15:0] signals_5_2, + output reduced_signals_5_2, + input [15:0] signals_5_3, + output reduced_signals_5_3, + input [15:0] signals_5_4, + output reduced_signals_5_4, + input [15:0] signals_5_5, + output reduced_signals_5_5, + input [15:0] signals_5_6, + output reduced_signals_5_6, + input [15:0] signals_5_7, + output reduced_signals_5_7, + input reset +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_0_0 ( + .clk(clk), + .reset(reset), + .signal(signals_0_0), + .reduced_signal(reduced_signals_0_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_0_1 ( + .clk(clk), + .reset(reset), + .signal(signals_0_1), + .reduced_signal(reduced_signals_0_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_0_2 ( + .clk(clk), + .reset(reset), + .signal(signals_0_2), + .reduced_signal(reduced_signals_0_2) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_0_3 ( + .clk(clk), + .reset(reset), + .signal(signals_0_3), + .reduced_signal(reduced_signals_0_3) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_0_4 ( + .clk(clk), + .reset(reset), + .signal(signals_0_4), + .reduced_signal(reduced_signals_0_4) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_0_5 ( + .clk(clk), + .reset(reset), + .signal(signals_0_5), + .reduced_signal(reduced_signals_0_5) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_0_6 ( + .clk(clk), + .reset(reset), + .signal(signals_0_6), + .reduced_signal(reduced_signals_0_6) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_0_7 ( + .clk(clk), + .reset(reset), + .signal(signals_0_7), + .reduced_signal(reduced_signals_0_7) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_1_0 ( + .clk(clk), + .reset(reset), + .signal(signals_1_0), + .reduced_signal(reduced_signals_1_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_1_1 ( + .clk(clk), + .reset(reset), + .signal(signals_1_1), + .reduced_signal(reduced_signals_1_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_1_2 ( + .clk(clk), + .reset(reset), + .signal(signals_1_2), + .reduced_signal(reduced_signals_1_2) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_1_3 ( + .clk(clk), + .reset(reset), + .signal(signals_1_3), + .reduced_signal(reduced_signals_1_3) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_1_4 ( + .clk(clk), + .reset(reset), + .signal(signals_1_4), + .reduced_signal(reduced_signals_1_4) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_1_5 ( + .clk(clk), + .reset(reset), + .signal(signals_1_5), + .reduced_signal(reduced_signals_1_5) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_1_6 ( + .clk(clk), + .reset(reset), + .signal(signals_1_6), + .reduced_signal(reduced_signals_1_6) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_1_7 ( + .clk(clk), + .reset(reset), + .signal(signals_1_7), + .reduced_signal(reduced_signals_1_7) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_2_0 ( + .clk(clk), + .reset(reset), + .signal(signals_2_0), + .reduced_signal(reduced_signals_2_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_2_1 ( + .clk(clk), + .reset(reset), + .signal(signals_2_1), + .reduced_signal(reduced_signals_2_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_2_2 ( + .clk(clk), + .reset(reset), + .signal(signals_2_2), + .reduced_signal(reduced_signals_2_2) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_2_3 ( + .clk(clk), + .reset(reset), + .signal(signals_2_3), + .reduced_signal(reduced_signals_2_3) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_2_4 ( + .clk(clk), + .reset(reset), + .signal(signals_2_4), + .reduced_signal(reduced_signals_2_4) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_2_5 ( + .clk(clk), + .reset(reset), + .signal(signals_2_5), + .reduced_signal(reduced_signals_2_5) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_2_6 ( + .clk(clk), + .reset(reset), + .signal(signals_2_6), + .reduced_signal(reduced_signals_2_6) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_2_7 ( + .clk(clk), + .reset(reset), + .signal(signals_2_7), + .reduced_signal(reduced_signals_2_7) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_3_0 ( + .clk(clk), + .reset(reset), + .signal(signals_3_0), + .reduced_signal(reduced_signals_3_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_3_1 ( + .clk(clk), + .reset(reset), + .signal(signals_3_1), + .reduced_signal(reduced_signals_3_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_3_2 ( + .clk(clk), + .reset(reset), + .signal(signals_3_2), + .reduced_signal(reduced_signals_3_2) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_3_3 ( + .clk(clk), + .reset(reset), + .signal(signals_3_3), + .reduced_signal(reduced_signals_3_3) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_3_4 ( + .clk(clk), + .reset(reset), + .signal(signals_3_4), + .reduced_signal(reduced_signals_3_4) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_3_5 ( + .clk(clk), + .reset(reset), + .signal(signals_3_5), + .reduced_signal(reduced_signals_3_5) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_3_6 ( + .clk(clk), + .reset(reset), + .signal(signals_3_6), + .reduced_signal(reduced_signals_3_6) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_3_7 ( + .clk(clk), + .reset(reset), + .signal(signals_3_7), + .reduced_signal(reduced_signals_3_7) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_4_0 ( + .clk(clk), + .reset(reset), + .signal(signals_4_0), + .reduced_signal(reduced_signals_4_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_4_1 ( + .clk(clk), + .reset(reset), + .signal(signals_4_1), + .reduced_signal(reduced_signals_4_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_4_2 ( + .clk(clk), + .reset(reset), + .signal(signals_4_2), + .reduced_signal(reduced_signals_4_2) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_4_3 ( + .clk(clk), + .reset(reset), + .signal(signals_4_3), + .reduced_signal(reduced_signals_4_3) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_4_4 ( + .clk(clk), + .reset(reset), + .signal(signals_4_4), + .reduced_signal(reduced_signals_4_4) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_4_5 ( + .clk(clk), + .reset(reset), + .signal(signals_4_5), + .reduced_signal(reduced_signals_4_5) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_4_6 ( + .clk(clk), + .reset(reset), + .signal(signals_4_6), + .reduced_signal(reduced_signals_4_6) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_4_7 ( + .clk(clk), + .reset(reset), + .signal(signals_4_7), + .reduced_signal(reduced_signals_4_7) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_5_0 ( + .clk(clk), + .reset(reset), + .signal(signals_5_0), + .reduced_signal(reduced_signals_5_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_5_1 ( + .clk(clk), + .reset(reset), + .signal(signals_5_1), + .reduced_signal(reduced_signals_5_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_5_2 ( + .clk(clk), + .reset(reset), + .signal(signals_5_2), + .reduced_signal(reduced_signals_5_2) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_5_3 ( + .clk(clk), + .reset(reset), + .signal(signals_5_3), + .reduced_signal(reduced_signals_5_3) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_5_4 ( + .clk(clk), + .reset(reset), + .signal(signals_5_4), + .reduced_signal(reduced_signals_5_4) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_5_5 ( + .clk(clk), + .reset(reset), + .signal(signals_5_5), + .reduced_signal(reduced_signals_5_5) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_5_6 ( + .clk(clk), + .reset(reset), + .signal(signals_5_6), + .reduced_signal(reduced_signals_5_6) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_5_7 ( + .clk(clk), + .reset(reset), + .signal(signals_5_7), + .reduced_signal(reduced_signals_5_7) +); + +endmodule + +module pipelined_xor_tree_16 ( + input clk, + input reset, + input [15:0] signal, + output reduced_signal +); + +reg pipeline_0_0; +reg pipeline_0_1; +reg pipeline_0_2; +reg pipeline_1_0; +reg pipeline_1_1; +reg pipeline_1_2; +reg pipeline_2_0; +reg pipeline_2_1; +reg pipeline_2_2; +reg pipeline_3_0; +reg pipeline_3_1; +reg pipeline_3_2; +reg pipeline_4_0; +reg pipeline_4_1; +reg pipeline_4_2; +reg pipeline_5_0; +reg pipeline_5_1; +reg pipeline_5_2; +reg pipeline_6_0; +reg pipeline_6_1; +reg pipeline_6_2; +reg pipeline_7_0; +reg pipeline_7_1; +reg pipeline_7_2; +reg pipeline_8_0; +reg pipeline_8_1; +reg pipeline_8_2; +reg pipeline_9_0; +reg pipeline_9_1; +reg pipeline_9_2; +reg pipeline_10_0; +reg pipeline_10_1; +reg pipeline_10_2; +reg pipeline_11_0; +reg pipeline_11_1; +reg pipeline_11_2; +reg pipeline_12_0; +reg pipeline_12_1; +reg pipeline_12_2; +reg pipeline_13_0; +reg pipeline_13_1; +reg pipeline_13_2; +reg pipeline_14_0; +reg pipeline_14_1; +reg pipeline_14_2; +reg pipeline_15_0; +reg pipeline_15_1; +reg pipeline_15_2; + +always @ (posedge clk) begin + if (reset) begin + pipeline_0_0 <= 0; + pipeline_0_1 <= 0; + pipeline_0_2 <= 0; + pipeline_1_0 <= 0; + pipeline_1_1 <= 0; + pipeline_1_2 <= 0; + pipeline_2_0 <= 0; + pipeline_2_1 <= 0; + pipeline_2_2 <= 0; + pipeline_3_0 <= 0; + pipeline_3_1 <= 0; + pipeline_3_2 <= 0; + pipeline_4_0 <= 0; + pipeline_4_1 <= 0; + pipeline_4_2 <= 0; + pipeline_5_0 <= 0; + pipeline_5_1 <= 0; + pipeline_5_2 <= 0; + pipeline_6_0 <= 0; + pipeline_6_1 <= 0; + pipeline_6_2 <= 0; + pipeline_7_0 <= 0; + pipeline_7_1 <= 0; + pipeline_7_2 <= 0; + pipeline_8_0 <= 0; + pipeline_8_1 <= 0; + pipeline_8_2 <= 0; + pipeline_9_0 <= 0; + pipeline_9_1 <= 0; + pipeline_9_2 <= 0; + pipeline_10_0 <= 0; + pipeline_10_1 <= 0; + pipeline_10_2 <= 0; + pipeline_11_0 <= 0; + pipeline_11_1 <= 0; + pipeline_11_2 <= 0; + pipeline_12_0 <= 0; + pipeline_12_1 <= 0; + pipeline_12_2 <= 0; + pipeline_13_0 <= 0; + pipeline_13_1 <= 0; + pipeline_13_2 <= 0; + pipeline_14_0 <= 0; + pipeline_14_1 <= 0; + pipeline_14_2 <= 0; + pipeline_15_0 <= 0; + pipeline_15_1 <= 0; + pipeline_15_2 <= 0; + end else begin + pipeline_0_0 <= signal[15]; + pipeline_1_0 <= signal[14]; + pipeline_2_0 <= signal[13]; + pipeline_3_0 <= signal[12]; + pipeline_4_0 <= signal[11]; + pipeline_5_0 <= signal[10]; + pipeline_6_0 <= signal[9]; + pipeline_7_0 <= signal[8]; + pipeline_8_0 <= signal[7]; + pipeline_9_0 <= signal[6]; + pipeline_10_0 <= signal[5]; + pipeline_11_0 <= signal[4]; + pipeline_12_0 <= signal[3]; + pipeline_13_0 <= signal[2]; + pipeline_14_0 <= signal[1]; + pipeline_15_0 <= signal[0]; + pipeline_0_1 <= pipeline_0_0 ^ pipeline_1_0^ pipeline_2_0 ^ pipeline_3_0; + pipeline_4_1 <= pipeline_4_0 ^ pipeline_5_0^ pipeline_6_0 ^ pipeline_7_0; + pipeline_8_1 <= pipeline_8_0 ^ pipeline_9_0^ pipeline_10_0 ^ pipeline_11_0; + pipeline_12_1 <= pipeline_12_0 ^ pipeline_13_0^ pipeline_14_0 ^ pipeline_15_0; + pipeline_0_2 <= pipeline_0_1 ^ pipeline_4_1^ pipeline_8_1 ^ pipeline_12_1; + end +end + +assign reduced_signal = pipeline_0_2; + +endmodule + +module dpram ( + clk, + addr1, + addr2, + we1, + we2, + data1, + data2, + out1, + out2 +); +parameter AWIDTH=10; +parameter NUM_WORDS=1024; +parameter DWIDTH=32; +input clk; +input [(AWIDTH-1):0] addr1; +input [(AWIDTH-1):0] addr2; +input we1; +input we2; +input [(DWIDTH-1):0] data1; +input [(DWIDTH-1):0] data2; +output reg [(DWIDTH-1):0] out1; +output reg [(DWIDTH-1):0] out2; + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram[NUM_WORDS-1:0]; +always @ (posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end + else begin + out1 <= ram[addr1]; + end +end + +always @ (posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end + else begin + out2 <= ram[addr2]; + end +end + +`else +defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; +defparam u_dual_port_ram.DATA_WIDTH = DWIDTH; + +dual_port_ram u_dual_port_ram( +.addr1(addr1), +.we1(we1), +.data1(data1), +.out1(out1), +.addr2(addr2), +.we2(we2), +.data2(data2), +.out2(out2), +.clk(clk) +); + +`endif +endmodule + + diff --git a/designs/koios/dla_like.large/dla_random.sv b/designs/koios/dla_like.large/dla_random.sv new file mode 100644 index 000000000..78dc593b0 --- /dev/null +++ b/designs/koios/dla_like.large/dla_random.sv @@ -0,0 +1,276 @@ +/* +Random input logic for DLA +*/ + +`include "../../random_number_generator.sv" + +module dla_random( + input logic clk, + input logic rst, + input logic i_ddr_wen_0_0, + output logic o_dummy_out_0_0, + input logic i_ddr_wen_0_1, + output logic o_dummy_out_0_1, + input logic i_ddr_wen_0_2, + output logic o_dummy_out_0_2, + input logic i_ddr_wen_0_3, + output logic o_dummy_out_0_3, + input logic i_ddr_wen_0_4, + output logic o_dummy_out_0_4, + input logic i_ddr_wen_0_5, + output logic o_dummy_out_0_5, + input logic i_ddr_wen_0_6, + output logic o_dummy_out_0_6, + input logic i_ddr_wen_0_7, + output logic o_dummy_out_0_7, + input logic i_ddr_wen_1_0, + output logic o_dummy_out_1_0, + input logic i_ddr_wen_1_1, + output logic o_dummy_out_1_1, + input logic i_ddr_wen_1_2, + output logic o_dummy_out_1_2, + input logic i_ddr_wen_1_3, + output logic o_dummy_out_1_3, + input logic i_ddr_wen_1_4, + output logic o_dummy_out_1_4, + input logic i_ddr_wen_1_5, + output logic o_dummy_out_1_5, + input logic i_ddr_wen_1_6, + output logic o_dummy_out_1_6, + input logic i_ddr_wen_1_7, + output logic o_dummy_out_1_7, + input logic i_ddr_wen_2_0, + output logic o_dummy_out_2_0, + input logic i_ddr_wen_2_1, + output logic o_dummy_out_2_1, + input logic i_ddr_wen_2_2, + output logic o_dummy_out_2_2, + input logic i_ddr_wen_2_3, + output logic o_dummy_out_2_3, + input logic i_ddr_wen_2_4, + output logic o_dummy_out_2_4, + input logic i_ddr_wen_2_5, + output logic o_dummy_out_2_5, + input logic i_ddr_wen_2_6, + output logic o_dummy_out_2_6, + input logic i_ddr_wen_2_7, + output logic o_dummy_out_2_7, + input logic i_ddr_wen_3_0, + output logic o_dummy_out_3_0, + input logic i_ddr_wen_3_1, + output logic o_dummy_out_3_1, + input logic i_ddr_wen_3_2, + output logic o_dummy_out_3_2, + input logic i_ddr_wen_3_3, + output logic o_dummy_out_3_3, + input logic i_ddr_wen_3_4, + output logic o_dummy_out_3_4, + input logic i_ddr_wen_3_5, + output logic o_dummy_out_3_5, + input logic i_ddr_wen_3_6, + output logic o_dummy_out_3_6, + input logic i_ddr_wen_3_7, + output logic o_dummy_out_3_7, + input logic i_ddr_wen_4_0, + output logic o_dummy_out_4_0, + input logic i_ddr_wen_4_1, + output logic o_dummy_out_4_1, + input logic i_ddr_wen_4_2, + output logic o_dummy_out_4_2, + input logic i_ddr_wen_4_3, + output logic o_dummy_out_4_3, + input logic i_ddr_wen_4_4, + output logic o_dummy_out_4_4, + input logic i_ddr_wen_4_5, + output logic o_dummy_out_4_5, + input logic i_ddr_wen_4_6, + output logic o_dummy_out_4_6, + input logic i_ddr_wen_4_7, + output logic o_dummy_out_4_7, + input logic i_ddr_wen_5_0, + output logic o_dummy_out_5_0, + input logic i_ddr_wen_5_1, + output logic o_dummy_out_5_1, + input logic i_ddr_wen_5_2, + output logic o_dummy_out_5_2, + input logic i_ddr_wen_5_3, + output logic o_dummy_out_5_3, + input logic i_ddr_wen_5_4, + output logic o_dummy_out_5_4, + input logic i_ddr_wen_5_5, + output logic o_dummy_out_5_5, + input logic i_ddr_wen_5_6, + output logic o_dummy_out_5_6, + input logic i_ddr_wen_5_7, + output logic o_dummy_out_5_7, + output logic o_valid +); + +logic [15:0] i_ddr[5:0][7:0]; +generate // generate block for random number generator +genvar i; +genvar j; +for(i=0; i<6; i=i+1) begin + for(j=0; j<8; j=j+1) begin + RandomNumberGenerator #(16, i+j) random_number_generator_0( + .clk(clk), + .reset(rst), + .random_number(i_ddr[i][j]) + ); + end +end +endgenerate + + +DLA dla0( + clk, + rst, + i_ddr_wen_0_0, + i_ddr[0][0], + o_dummy_out_0_0, + i_ddr_wen_0_1, + i_ddr[0][1], + o_dummy_out_0_1, + i_ddr_wen_0_2, + i_ddr[0][2], + o_dummy_out_0_2, + i_ddr_wen_0_3, + i_ddr[0][3], + o_dummy_out_0_3, + i_ddr_wen_0_4, + i_ddr[0][4], + o_dummy_out_0_4, + i_ddr_wen_0_5, + i_ddr[0][5], + o_dummy_out_0_5, + i_ddr_wen_0_6, + i_ddr[0][6], + o_dummy_out_0_6, + i_ddr_wen_0_7, + i_ddr[0][7], + o_dummy_out_0_7, + i_ddr_wen_1_0, + i_ddr[1][0], + o_dummy_out_1_0, + i_ddr_wen_1_1, + i_ddr[1][1], + o_dummy_out_1_1, + i_ddr_wen_1_2, + i_ddr[1][2], + o_dummy_out_1_2, + i_ddr_wen_1_3, + i_ddr[1][3], + o_dummy_out_1_3, + i_ddr_wen_1_4, + i_ddr[1][4], + o_dummy_out_1_4, + i_ddr_wen_1_5, + i_ddr[1][5], + o_dummy_out_1_5, + i_ddr_wen_1_6, + i_ddr[1][6], + o_dummy_out_1_6, + i_ddr_wen_1_7, + i_ddr[1][7], + o_dummy_out_1_7, + i_ddr_wen_2_0, + i_ddr[2][0], + o_dummy_out_2_0, + i_ddr_wen_2_1, + i_ddr[2][1], + o_dummy_out_2_1, + i_ddr_wen_2_2, + i_ddr[2][2], + o_dummy_out_2_2, + i_ddr_wen_2_3, + i_ddr[2][3], + o_dummy_out_2_3, + i_ddr_wen_2_4, + i_ddr[2][4], + o_dummy_out_2_4, + i_ddr_wen_2_5, + i_ddr[2][5], + o_dummy_out_2_5, + i_ddr_wen_2_6, + i_ddr[2][6], + o_dummy_out_2_6, + i_ddr_wen_2_7, + i_ddr[2][7], + o_dummy_out_2_7, + i_ddr_wen_3_0, + i_ddr[3][0], + o_dummy_out_3_0, + i_ddr_wen_3_1, + i_ddr[3][1], + o_dummy_out_3_1, + i_ddr_wen_3_2, + i_ddr[3][2], + o_dummy_out_3_2, + i_ddr_wen_3_3, + i_ddr[3][3], + o_dummy_out_3_3, + i_ddr_wen_3_4, + i_ddr[3][4], + o_dummy_out_3_4, + i_ddr_wen_3_5, + i_ddr[3][5], + o_dummy_out_3_5, + i_ddr_wen_3_6, + i_ddr[3][6], + o_dummy_out_3_6, + i_ddr_wen_3_7, + i_ddr[3][7], + o_dummy_out_3_7, + i_ddr_wen_4_0, + i_ddr[4][0], + o_dummy_out_4_0, + i_ddr_wen_4_1, + i_ddr[4][1], + o_dummy_out_4_1, + i_ddr_wen_4_2, + i_ddr[4][2], + o_dummy_out_4_2, + i_ddr_wen_4_3, + i_ddr[4][3], + o_dummy_out_4_3, + i_ddr_wen_4_4, + i_ddr[4][4], + o_dummy_out_4_4, + i_ddr_wen_4_5, + i_ddr[4][5], + o_dummy_out_4_5, + i_ddr_wen_4_6, + i_ddr[4][6], + o_dummy_out_4_6, + i_ddr_wen_4_7, + i_ddr[4][7], + o_dummy_out_4_7, + i_ddr_wen_5_0, + i_ddr[5][0], + o_dummy_out_5_0, + i_ddr_wen_5_1, + i_ddr[5][1], + o_dummy_out_5_1, + i_ddr_wen_5_2, + i_ddr[5][2], + o_dummy_out_5_2, + i_ddr_wen_5_3, + i_ddr[5][3], + o_dummy_out_5_3, + i_ddr_wen_5_4, + i_ddr[5][4], + o_dummy_out_5_4, + i_ddr_wen_5_5, + i_ddr[5][5], + o_dummy_out_5_5, + i_ddr_wen_5_6, + i_ddr[5][6], + o_dummy_out_5_6, + i_ddr_wen_5_7, + i_ddr[5][7], + o_dummy_out_5_7, + o_valid +); + + +endmodule \ No newline at end of file diff --git a/designs/koios/dla_like.medium/design.yaml b/designs/koios/dla_like.medium/design.yaml new file mode 100644 index 000000000..fd623a753 --- /dev/null +++ b/designs/koios/dla_like.medium/design.yaml @@ -0,0 +1 @@ +top: dla_random diff --git a/designs/koios/dla_like.medium/dla_like.medium.v b/designs/koios/dla_like.medium/dla_like.medium.v new file mode 100644 index 000000000..e532636c1 --- /dev/null +++ b/designs/koios/dla_like.medium/dla_like.medium.v @@ -0,0 +1,30630 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Andrew Boutros +////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +//A CNN accelerator overlay called DLA from Intel based on the paper: +//U. Aydonat et al., “An OpenCL Deep Learning Accelerator on Arria10,” in International Symposium on Field-Programmable Gate Arrays (FPGA), 2017. +//This design was also used in this paper: +//A. Boutros et al., “You Cannot Improve What You Do Not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference,” ACM Transactions on Reconfigurable Technology Systems (TRETS), vol. 11, no. 3, 2018 +// +//Some properties of the design are: +//1. 16-bit fixed point for activations, 8-bit fixed point for weights +//2. Winograd Transform based convolution. +//3. 2D mac array. Centralized weight buffer for processing elements. +//4. Double-buffering after each layer. +/////////////////////////////////////////////////////////////////////////////// + + +module DLA ( + input clk, + input i_reset, + input i_ddr_wen_0_0, + input [15:0] i_ddr_0_0, + output o_dummy_out_0_0, + input i_ddr_wen_0_1, + input [15:0] i_ddr_0_1, + output o_dummy_out_0_1, + input i_ddr_wen_0_2, + input [15:0] i_ddr_0_2, + output o_dummy_out_0_2, + input i_ddr_wen_0_3, + input [15:0] i_ddr_0_3, + output o_dummy_out_0_3, + input i_ddr_wen_1_0, + input [15:0] i_ddr_1_0, + output o_dummy_out_1_0, + input i_ddr_wen_1_1, + input [15:0] i_ddr_1_1, + output o_dummy_out_1_1, + input i_ddr_wen_1_2, + input [15:0] i_ddr_1_2, + output o_dummy_out_1_2, + input i_ddr_wen_1_3, + input [15:0] i_ddr_1_3, + output o_dummy_out_1_3, + input i_ddr_wen_2_0, + input [15:0] i_ddr_2_0, + output o_dummy_out_2_0, + input i_ddr_wen_2_1, + input [15:0] i_ddr_2_1, + output o_dummy_out_2_1, + input i_ddr_wen_2_2, + input [15:0] i_ddr_2_2, + output o_dummy_out_2_2, + input i_ddr_wen_2_3, + input [15:0] i_ddr_2_3, + output o_dummy_out_2_3, + input i_ddr_wen_3_0, + input [15:0] i_ddr_3_0, + output o_dummy_out_3_0, + input i_ddr_wen_3_1, + input [15:0] i_ddr_3_1, + output o_dummy_out_3_1, + input i_ddr_wen_3_2, + input [15:0] i_ddr_3_2, + output o_dummy_out_3_2, + input i_ddr_wen_3_3, + input [15:0] i_ddr_3_3, + output o_dummy_out_3_3, + input i_ddr_wen_4_0, + input [15:0] i_ddr_4_0, + output o_dummy_out_4_0, + input i_ddr_wen_4_1, + input [15:0] i_ddr_4_1, + output o_dummy_out_4_1, + input i_ddr_wen_4_2, + input [15:0] i_ddr_4_2, + output o_dummy_out_4_2, + input i_ddr_wen_4_3, + input [15:0] i_ddr_4_3, + output o_dummy_out_4_3, + input i_ddr_wen_5_0, + input [15:0] i_ddr_5_0, + output o_dummy_out_5_0, + input i_ddr_wen_5_1, + input [15:0] i_ddr_5_1, + output o_dummy_out_5_1, + input i_ddr_wen_5_2, + input [15:0] i_ddr_5_2, + output o_dummy_out_5_2, + input i_ddr_wen_5_3, + input [15:0] i_ddr_5_3, + output o_dummy_out_5_3, + output o_valid +); + +wire [15:0] f_buffer_pe_0_0; +wire valid_buff_0_0; +wire [15:0] f_buffer_pe_0_1; +wire valid_buff_0_1; +wire [15:0] f_buffer_pe_0_2; +wire valid_buff_0_2; +wire [15:0] f_buffer_pe_0_3; +wire valid_buff_0_3; +wire [15:0] f_buffer_pe_1_0; +wire valid_buff_1_0; +wire [15:0] f_buffer_pe_1_1; +wire valid_buff_1_1; +wire [15:0] f_buffer_pe_1_2; +wire valid_buff_1_2; +wire [15:0] f_buffer_pe_1_3; +wire valid_buff_1_3; +wire [15:0] f_buffer_pe_2_0; +wire valid_buff_2_0; +wire [15:0] f_buffer_pe_2_1; +wire valid_buff_2_1; +wire [15:0] f_buffer_pe_2_2; +wire valid_buff_2_2; +wire [15:0] f_buffer_pe_2_3; +wire valid_buff_2_3; +wire [15:0] f_buffer_pe_3_0; +wire valid_buff_3_0; +wire [15:0] f_buffer_pe_3_1; +wire valid_buff_3_1; +wire [15:0] f_buffer_pe_3_2; +wire valid_buff_3_2; +wire [15:0] f_buffer_pe_3_3; +wire valid_buff_3_3; +wire [15:0] f_buffer_pe_4_0; +wire valid_buff_4_0; +wire [15:0] f_buffer_pe_4_1; +wire valid_buff_4_1; +wire [15:0] f_buffer_pe_4_2; +wire valid_buff_4_2; +wire [15:0] f_buffer_pe_4_3; +wire valid_buff_4_3; +wire [15:0] f_buffer_pe_5_0; +wire valid_buff_5_0; +wire [15:0] f_buffer_pe_5_1; +wire valid_buff_5_1; +wire [15:0] f_buffer_pe_5_2; +wire valid_buff_5_2; +wire [15:0] f_buffer_pe_5_3; +wire valid_buff_5_3; +wire ready; +wire [15:0] f_winograd_0_0; +wire [15:0] f_winograd_0_1; +wire [15:0] f_winograd_0_2; +wire [15:0] f_winograd_0_3; +wire [15:0] f_winograd_0_4; +wire [15:0] f_winograd_0_5; +wire [15:0] f_winograd_1_0; +wire [15:0] f_winograd_1_1; +wire [15:0] f_winograd_1_2; +wire [15:0] f_winograd_1_3; +wire [15:0] f_winograd_1_4; +wire [15:0] f_winograd_1_5; +wire [15:0] f_winograd_2_0; +wire [15:0] f_winograd_2_1; +wire [15:0] f_winograd_2_2; +wire [15:0] f_winograd_2_3; +wire [15:0] f_winograd_2_4; +wire [15:0] f_winograd_2_5; +wire [15:0] f_winograd_3_0; +wire [15:0] f_winograd_3_1; +wire [15:0] f_winograd_3_2; +wire [15:0] f_winograd_3_3; +wire [15:0] f_winograd_3_4; +wire [15:0] f_winograd_3_5; +wire winograd_valid_0; +wire winograd_valid_1; +wire winograd_valid_2; +wire winograd_valid_3; + +// PE Wires +wire [15:0] daisy_chain_0_0_0; +wire [15:0] daisy_chain_0_0_1; +wire [15:0] daisy_chain_0_0_2; +wire [15:0] daisy_chain_0_0_3; +wire [15:0] daisy_chain_0_0_4; +wire [15:0] daisy_chain_0_0_5; +wire [15:0] daisy_chain_0_1_0; +wire [15:0] daisy_chain_0_1_1; +wire [15:0] daisy_chain_0_1_2; +wire [15:0] daisy_chain_0_1_3; +wire [15:0] daisy_chain_0_1_4; +wire [15:0] daisy_chain_0_1_5; +wire [15:0] daisy_chain_0_2_0; +wire [15:0] daisy_chain_0_2_1; +wire [15:0] daisy_chain_0_2_2; +wire [15:0] daisy_chain_0_2_3; +wire [15:0] daisy_chain_0_2_4; +wire [15:0] daisy_chain_0_2_5; +wire [15:0] daisy_chain_0_3_0; +wire [15:0] daisy_chain_0_3_1; +wire [15:0] daisy_chain_0_3_2; +wire [15:0] daisy_chain_0_3_3; +wire [15:0] daisy_chain_0_3_4; +wire [15:0] daisy_chain_0_3_5; +wire [15:0] daisy_chain_1_0_0; +wire [15:0] daisy_chain_1_0_1; +wire [15:0] daisy_chain_1_0_2; +wire [15:0] daisy_chain_1_0_3; +wire [15:0] daisy_chain_1_0_4; +wire [15:0] daisy_chain_1_0_5; +wire [15:0] daisy_chain_1_1_0; +wire [15:0] daisy_chain_1_1_1; +wire [15:0] daisy_chain_1_1_2; +wire [15:0] daisy_chain_1_1_3; +wire [15:0] daisy_chain_1_1_4; +wire [15:0] daisy_chain_1_1_5; +wire [15:0] daisy_chain_1_2_0; +wire [15:0] daisy_chain_1_2_1; +wire [15:0] daisy_chain_1_2_2; +wire [15:0] daisy_chain_1_2_3; +wire [15:0] daisy_chain_1_2_4; +wire [15:0] daisy_chain_1_2_5; +wire [15:0] daisy_chain_1_3_0; +wire [15:0] daisy_chain_1_3_1; +wire [15:0] daisy_chain_1_3_2; +wire [15:0] daisy_chain_1_3_3; +wire [15:0] daisy_chain_1_3_4; +wire [15:0] daisy_chain_1_3_5; +wire [15:0] daisy_chain_2_0_0; +wire [15:0] daisy_chain_2_0_1; +wire [15:0] daisy_chain_2_0_2; +wire [15:0] daisy_chain_2_0_3; +wire [15:0] daisy_chain_2_0_4; +wire [15:0] daisy_chain_2_0_5; +wire [15:0] daisy_chain_2_1_0; +wire [15:0] daisy_chain_2_1_1; +wire [15:0] daisy_chain_2_1_2; +wire [15:0] daisy_chain_2_1_3; +wire [15:0] daisy_chain_2_1_4; +wire [15:0] daisy_chain_2_1_5; +wire [15:0] daisy_chain_2_2_0; +wire [15:0] daisy_chain_2_2_1; +wire [15:0] daisy_chain_2_2_2; +wire [15:0] daisy_chain_2_2_3; +wire [15:0] daisy_chain_2_2_4; +wire [15:0] daisy_chain_2_2_5; +wire [15:0] daisy_chain_2_3_0; +wire [15:0] daisy_chain_2_3_1; +wire [15:0] daisy_chain_2_3_2; +wire [15:0] daisy_chain_2_3_3; +wire [15:0] daisy_chain_2_3_4; +wire [15:0] daisy_chain_2_3_5; +wire [15:0] daisy_chain_3_0_0; +wire [15:0] daisy_chain_3_0_1; +wire [15:0] daisy_chain_3_0_2; +wire [15:0] daisy_chain_3_0_3; +wire [15:0] daisy_chain_3_0_4; +wire [15:0] daisy_chain_3_0_5; +wire [15:0] daisy_chain_3_1_0; +wire [15:0] daisy_chain_3_1_1; +wire [15:0] daisy_chain_3_1_2; +wire [15:0] daisy_chain_3_1_3; +wire [15:0] daisy_chain_3_1_4; +wire [15:0] daisy_chain_3_1_5; +wire [15:0] daisy_chain_3_2_0; +wire [15:0] daisy_chain_3_2_1; +wire [15:0] daisy_chain_3_2_2; +wire [15:0] daisy_chain_3_2_3; +wire [15:0] daisy_chain_3_2_4; +wire [15:0] daisy_chain_3_2_5; +wire [15:0] daisy_chain_3_3_0; +wire [15:0] daisy_chain_3_3_1; +wire [15:0] daisy_chain_3_3_2; +wire [15:0] daisy_chain_3_3_3; +wire [15:0] daisy_chain_3_3_4; +wire [15:0] daisy_chain_3_3_5; +wire [15:0] daisy_chain_4_0_0; +wire [15:0] daisy_chain_4_0_1; +wire [15:0] daisy_chain_4_0_2; +wire [15:0] daisy_chain_4_0_3; +wire [15:0] daisy_chain_4_0_4; +wire [15:0] daisy_chain_4_0_5; +wire [15:0] daisy_chain_4_1_0; +wire [15:0] daisy_chain_4_1_1; +wire [15:0] daisy_chain_4_1_2; +wire [15:0] daisy_chain_4_1_3; +wire [15:0] daisy_chain_4_1_4; +wire [15:0] daisy_chain_4_1_5; +wire [15:0] daisy_chain_4_2_0; +wire [15:0] daisy_chain_4_2_1; +wire [15:0] daisy_chain_4_2_2; +wire [15:0] daisy_chain_4_2_3; +wire [15:0] daisy_chain_4_2_4; +wire [15:0] daisy_chain_4_2_5; +wire [15:0] daisy_chain_4_3_0; +wire [15:0] daisy_chain_4_3_1; +wire [15:0] daisy_chain_4_3_2; +wire [15:0] daisy_chain_4_3_3; +wire [15:0] daisy_chain_4_3_4; +wire [15:0] daisy_chain_4_3_5; +wire [15:0] daisy_chain_5_0_0; +wire [15:0] daisy_chain_5_0_1; +wire [15:0] daisy_chain_5_0_2; +wire [15:0] daisy_chain_5_0_3; +wire [15:0] daisy_chain_5_0_4; +wire [15:0] daisy_chain_5_0_5; +wire [15:0] daisy_chain_5_1_0; +wire [15:0] daisy_chain_5_1_1; +wire [15:0] daisy_chain_5_1_2; +wire [15:0] daisy_chain_5_1_3; +wire [15:0] daisy_chain_5_1_4; +wire [15:0] daisy_chain_5_1_5; +wire [15:0] daisy_chain_5_2_0; +wire [15:0] daisy_chain_5_2_1; +wire [15:0] daisy_chain_5_2_2; +wire [15:0] daisy_chain_5_2_3; +wire [15:0] daisy_chain_5_2_4; +wire [15:0] daisy_chain_5_2_5; +wire [15:0] daisy_chain_5_3_0; +wire [15:0] daisy_chain_5_3_1; +wire [15:0] daisy_chain_5_3_2; +wire [15:0] daisy_chain_5_3_3; +wire [15:0] daisy_chain_5_3_4; +wire [15:0] daisy_chain_5_3_5; +wire [15:0] daisy_chain_6_0_0; +wire [15:0] daisy_chain_6_0_1; +wire [15:0] daisy_chain_6_0_2; +wire [15:0] daisy_chain_6_0_3; +wire [15:0] daisy_chain_6_0_4; +wire [15:0] daisy_chain_6_0_5; +wire [15:0] daisy_chain_6_1_0; +wire [15:0] daisy_chain_6_1_1; +wire [15:0] daisy_chain_6_1_2; +wire [15:0] daisy_chain_6_1_3; +wire [15:0] daisy_chain_6_1_4; +wire [15:0] daisy_chain_6_1_5; +wire [15:0] daisy_chain_6_2_0; +wire [15:0] daisy_chain_6_2_1; +wire [15:0] daisy_chain_6_2_2; +wire [15:0] daisy_chain_6_2_3; +wire [15:0] daisy_chain_6_2_4; +wire [15:0] daisy_chain_6_2_5; +wire [15:0] daisy_chain_6_3_0; +wire [15:0] daisy_chain_6_3_1; +wire [15:0] daisy_chain_6_3_2; +wire [15:0] daisy_chain_6_3_3; +wire [15:0] daisy_chain_6_3_4; +wire [15:0] daisy_chain_6_3_5; +wire [15:0] daisy_chain_7_0_0; +wire [15:0] daisy_chain_7_0_1; +wire [15:0] daisy_chain_7_0_2; +wire [15:0] daisy_chain_7_0_3; +wire [15:0] daisy_chain_7_0_4; +wire [15:0] daisy_chain_7_0_5; +wire [15:0] daisy_chain_7_1_0; +wire [15:0] daisy_chain_7_1_1; +wire [15:0] daisy_chain_7_1_2; +wire [15:0] daisy_chain_7_1_3; +wire [15:0] daisy_chain_7_1_4; +wire [15:0] daisy_chain_7_1_5; +wire [15:0] daisy_chain_7_2_0; +wire [15:0] daisy_chain_7_2_1; +wire [15:0] daisy_chain_7_2_2; +wire [15:0] daisy_chain_7_2_3; +wire [15:0] daisy_chain_7_2_4; +wire [15:0] daisy_chain_7_2_5; +wire [15:0] daisy_chain_7_3_0; +wire [15:0] daisy_chain_7_3_1; +wire [15:0] daisy_chain_7_3_2; +wire [15:0] daisy_chain_7_3_3; +wire [15:0] daisy_chain_7_3_4; +wire [15:0] daisy_chain_7_3_5; +wire [15:0] daisy_chain_8_0_0; +wire [15:0] daisy_chain_8_0_1; +wire [15:0] daisy_chain_8_0_2; +wire [15:0] daisy_chain_8_0_3; +wire [15:0] daisy_chain_8_0_4; +wire [15:0] daisy_chain_8_0_5; +wire [15:0] daisy_chain_8_1_0; +wire [15:0] daisy_chain_8_1_1; +wire [15:0] daisy_chain_8_1_2; +wire [15:0] daisy_chain_8_1_3; +wire [15:0] daisy_chain_8_1_4; +wire [15:0] daisy_chain_8_1_5; +wire [15:0] daisy_chain_8_2_0; +wire [15:0] daisy_chain_8_2_1; +wire [15:0] daisy_chain_8_2_2; +wire [15:0] daisy_chain_8_2_3; +wire [15:0] daisy_chain_8_2_4; +wire [15:0] daisy_chain_8_2_5; +wire [15:0] daisy_chain_8_3_0; +wire [15:0] daisy_chain_8_3_1; +wire [15:0] daisy_chain_8_3_2; +wire [15:0] daisy_chain_8_3_3; +wire [15:0] daisy_chain_8_3_4; +wire [15:0] daisy_chain_8_3_5; +wire [15:0] daisy_chain_9_0_0; +wire [15:0] daisy_chain_9_0_1; +wire [15:0] daisy_chain_9_0_2; +wire [15:0] daisy_chain_9_0_3; +wire [15:0] daisy_chain_9_0_4; +wire [15:0] daisy_chain_9_0_5; +wire [15:0] daisy_chain_9_1_0; +wire [15:0] daisy_chain_9_1_1; +wire [15:0] daisy_chain_9_1_2; +wire [15:0] daisy_chain_9_1_3; +wire [15:0] daisy_chain_9_1_4; +wire [15:0] daisy_chain_9_1_5; +wire [15:0] daisy_chain_9_2_0; +wire [15:0] daisy_chain_9_2_1; +wire [15:0] daisy_chain_9_2_2; +wire [15:0] daisy_chain_9_2_3; +wire [15:0] daisy_chain_9_2_4; +wire [15:0] daisy_chain_9_2_5; +wire [15:0] daisy_chain_9_3_0; +wire [15:0] daisy_chain_9_3_1; +wire [15:0] daisy_chain_9_3_2; +wire [15:0] daisy_chain_9_3_3; +wire [15:0] daisy_chain_9_3_4; +wire [15:0] daisy_chain_9_3_5; +wire [15:0] daisy_chain_10_0_0; +wire [15:0] daisy_chain_10_0_1; +wire [15:0] daisy_chain_10_0_2; +wire [15:0] daisy_chain_10_0_3; +wire [15:0] daisy_chain_10_0_4; +wire [15:0] daisy_chain_10_0_5; +wire [15:0] daisy_chain_10_1_0; +wire [15:0] daisy_chain_10_1_1; +wire [15:0] daisy_chain_10_1_2; +wire [15:0] daisy_chain_10_1_3; +wire [15:0] daisy_chain_10_1_4; +wire [15:0] daisy_chain_10_1_5; +wire [15:0] daisy_chain_10_2_0; +wire [15:0] daisy_chain_10_2_1; +wire [15:0] daisy_chain_10_2_2; +wire [15:0] daisy_chain_10_2_3; +wire [15:0] daisy_chain_10_2_4; +wire [15:0] daisy_chain_10_2_5; +wire [15:0] daisy_chain_10_3_0; +wire [15:0] daisy_chain_10_3_1; +wire [15:0] daisy_chain_10_3_2; +wire [15:0] daisy_chain_10_3_3; +wire [15:0] daisy_chain_10_3_4; +wire [15:0] daisy_chain_10_3_5; +wire [15:0] daisy_chain_11_0_0; +wire [15:0] daisy_chain_11_0_1; +wire [15:0] daisy_chain_11_0_2; +wire [15:0] daisy_chain_11_0_3; +wire [15:0] daisy_chain_11_0_4; +wire [15:0] daisy_chain_11_0_5; +wire [15:0] daisy_chain_11_1_0; +wire [15:0] daisy_chain_11_1_1; +wire [15:0] daisy_chain_11_1_2; +wire [15:0] daisy_chain_11_1_3; +wire [15:0] daisy_chain_11_1_4; +wire [15:0] daisy_chain_11_1_5; +wire [15:0] daisy_chain_11_2_0; +wire [15:0] daisy_chain_11_2_1; +wire [15:0] daisy_chain_11_2_2; +wire [15:0] daisy_chain_11_2_3; +wire [15:0] daisy_chain_11_2_4; +wire [15:0] daisy_chain_11_2_5; +wire [15:0] daisy_chain_11_3_0; +wire [15:0] daisy_chain_11_3_1; +wire [15:0] daisy_chain_11_3_2; +wire [15:0] daisy_chain_11_3_3; +wire [15:0] daisy_chain_11_3_4; +wire [15:0] daisy_chain_11_3_5; +wire [15:0] daisy_chain_12_0_0; +wire [15:0] daisy_chain_12_0_1; +wire [15:0] daisy_chain_12_0_2; +wire [15:0] daisy_chain_12_0_3; +wire [15:0] daisy_chain_12_0_4; +wire [15:0] daisy_chain_12_0_5; +wire [15:0] daisy_chain_12_1_0; +wire [15:0] daisy_chain_12_1_1; +wire [15:0] daisy_chain_12_1_2; +wire [15:0] daisy_chain_12_1_3; +wire [15:0] daisy_chain_12_1_4; +wire [15:0] daisy_chain_12_1_5; +wire [15:0] daisy_chain_12_2_0; +wire [15:0] daisy_chain_12_2_1; +wire [15:0] daisy_chain_12_2_2; +wire [15:0] daisy_chain_12_2_3; +wire [15:0] daisy_chain_12_2_4; +wire [15:0] daisy_chain_12_2_5; +wire [15:0] daisy_chain_12_3_0; +wire [15:0] daisy_chain_12_3_1; +wire [15:0] daisy_chain_12_3_2; +wire [15:0] daisy_chain_12_3_3; +wire [15:0] daisy_chain_12_3_4; +wire [15:0] daisy_chain_12_3_5; +wire [15:0] daisy_chain_13_0_0; +wire [15:0] daisy_chain_13_0_1; +wire [15:0] daisy_chain_13_0_2; +wire [15:0] daisy_chain_13_0_3; +wire [15:0] daisy_chain_13_0_4; +wire [15:0] daisy_chain_13_0_5; +wire [15:0] daisy_chain_13_1_0; +wire [15:0] daisy_chain_13_1_1; +wire [15:0] daisy_chain_13_1_2; +wire [15:0] daisy_chain_13_1_3; +wire [15:0] daisy_chain_13_1_4; +wire [15:0] daisy_chain_13_1_5; +wire [15:0] daisy_chain_13_2_0; +wire [15:0] daisy_chain_13_2_1; +wire [15:0] daisy_chain_13_2_2; +wire [15:0] daisy_chain_13_2_3; +wire [15:0] daisy_chain_13_2_4; +wire [15:0] daisy_chain_13_2_5; +wire [15:0] daisy_chain_13_3_0; +wire [15:0] daisy_chain_13_3_1; +wire [15:0] daisy_chain_13_3_2; +wire [15:0] daisy_chain_13_3_3; +wire [15:0] daisy_chain_13_3_4; +wire [15:0] daisy_chain_13_3_5; +wire [15:0] daisy_chain_14_0_0; +wire [15:0] daisy_chain_14_0_1; +wire [15:0] daisy_chain_14_0_2; +wire [15:0] daisy_chain_14_0_3; +wire [15:0] daisy_chain_14_0_4; +wire [15:0] daisy_chain_14_0_5; +wire [15:0] daisy_chain_14_1_0; +wire [15:0] daisy_chain_14_1_1; +wire [15:0] daisy_chain_14_1_2; +wire [15:0] daisy_chain_14_1_3; +wire [15:0] daisy_chain_14_1_4; +wire [15:0] daisy_chain_14_1_5; +wire [15:0] daisy_chain_14_2_0; +wire [15:0] daisy_chain_14_2_1; +wire [15:0] daisy_chain_14_2_2; +wire [15:0] daisy_chain_14_2_3; +wire [15:0] daisy_chain_14_2_4; +wire [15:0] daisy_chain_14_2_5; +wire [15:0] daisy_chain_14_3_0; +wire [15:0] daisy_chain_14_3_1; +wire [15:0] daisy_chain_14_3_2; +wire [15:0] daisy_chain_14_3_3; +wire [15:0] daisy_chain_14_3_4; +wire [15:0] daisy_chain_14_3_5; +wire [15:0] daisy_chain_15_0_0; +wire [15:0] daisy_chain_15_0_1; +wire [15:0] daisy_chain_15_0_2; +wire [15:0] daisy_chain_15_0_3; +wire [15:0] daisy_chain_15_0_4; +wire [15:0] daisy_chain_15_0_5; +wire [15:0] daisy_chain_15_1_0; +wire [15:0] daisy_chain_15_1_1; +wire [15:0] daisy_chain_15_1_2; +wire [15:0] daisy_chain_15_1_3; +wire [15:0] daisy_chain_15_1_4; +wire [15:0] daisy_chain_15_1_5; +wire [15:0] daisy_chain_15_2_0; +wire [15:0] daisy_chain_15_2_1; +wire [15:0] daisy_chain_15_2_2; +wire [15:0] daisy_chain_15_2_3; +wire [15:0] daisy_chain_15_2_4; +wire [15:0] daisy_chain_15_2_5; +wire [15:0] daisy_chain_15_3_0; +wire [15:0] daisy_chain_15_3_1; +wire [15:0] daisy_chain_15_3_2; +wire [15:0] daisy_chain_15_3_3; +wire [15:0] daisy_chain_15_3_4; +wire [15:0] daisy_chain_15_3_5; +wire [15:0] daisy_chain_16_0_0; +wire [15:0] daisy_chain_16_0_1; +wire [15:0] daisy_chain_16_0_2; +wire [15:0] daisy_chain_16_0_3; +wire [15:0] daisy_chain_16_0_4; +wire [15:0] daisy_chain_16_0_5; +wire [15:0] daisy_chain_16_1_0; +wire [15:0] daisy_chain_16_1_1; +wire [15:0] daisy_chain_16_1_2; +wire [15:0] daisy_chain_16_1_3; +wire [15:0] daisy_chain_16_1_4; +wire [15:0] daisy_chain_16_1_5; +wire [15:0] daisy_chain_16_2_0; +wire [15:0] daisy_chain_16_2_1; +wire [15:0] daisy_chain_16_2_2; +wire [15:0] daisy_chain_16_2_3; +wire [15:0] daisy_chain_16_2_4; +wire [15:0] daisy_chain_16_2_5; +wire [15:0] daisy_chain_16_3_0; +wire [15:0] daisy_chain_16_3_1; +wire [15:0] daisy_chain_16_3_2; +wire [15:0] daisy_chain_16_3_3; +wire [15:0] daisy_chain_16_3_4; +wire [15:0] daisy_chain_16_3_5; +wire [15:0] daisy_chain_17_0_0; +wire [15:0] daisy_chain_17_0_1; +wire [15:0] daisy_chain_17_0_2; +wire [15:0] daisy_chain_17_0_3; +wire [15:0] daisy_chain_17_0_4; +wire [15:0] daisy_chain_17_0_5; +wire [15:0] daisy_chain_17_1_0; +wire [15:0] daisy_chain_17_1_1; +wire [15:0] daisy_chain_17_1_2; +wire [15:0] daisy_chain_17_1_3; +wire [15:0] daisy_chain_17_1_4; +wire [15:0] daisy_chain_17_1_5; +wire [15:0] daisy_chain_17_2_0; +wire [15:0] daisy_chain_17_2_1; +wire [15:0] daisy_chain_17_2_2; +wire [15:0] daisy_chain_17_2_3; +wire [15:0] daisy_chain_17_2_4; +wire [15:0] daisy_chain_17_2_5; +wire [15:0] daisy_chain_17_3_0; +wire [15:0] daisy_chain_17_3_1; +wire [15:0] daisy_chain_17_3_2; +wire [15:0] daisy_chain_17_3_3; +wire [15:0] daisy_chain_17_3_4; +wire [15:0] daisy_chain_17_3_5; +wire [15:0] daisy_chain_18_0_0; +wire [15:0] daisy_chain_18_0_1; +wire [15:0] daisy_chain_18_0_2; +wire [15:0] daisy_chain_18_0_3; +wire [15:0] daisy_chain_18_0_4; +wire [15:0] daisy_chain_18_0_5; +wire [15:0] daisy_chain_18_1_0; +wire [15:0] daisy_chain_18_1_1; +wire [15:0] daisy_chain_18_1_2; +wire [15:0] daisy_chain_18_1_3; +wire [15:0] daisy_chain_18_1_4; +wire [15:0] daisy_chain_18_1_5; +wire [15:0] daisy_chain_18_2_0; +wire [15:0] daisy_chain_18_2_1; +wire [15:0] daisy_chain_18_2_2; +wire [15:0] daisy_chain_18_2_3; +wire [15:0] daisy_chain_18_2_4; +wire [15:0] daisy_chain_18_2_5; +wire [15:0] daisy_chain_18_3_0; +wire [15:0] daisy_chain_18_3_1; +wire [15:0] daisy_chain_18_3_2; +wire [15:0] daisy_chain_18_3_3; +wire [15:0] daisy_chain_18_3_4; +wire [15:0] daisy_chain_18_3_5; +wire [15:0] daisy_chain_19_0_0; +wire [15:0] daisy_chain_19_0_1; +wire [15:0] daisy_chain_19_0_2; +wire [15:0] daisy_chain_19_0_3; +wire [15:0] daisy_chain_19_0_4; +wire [15:0] daisy_chain_19_0_5; +wire [15:0] daisy_chain_19_1_0; +wire [15:0] daisy_chain_19_1_1; +wire [15:0] daisy_chain_19_1_2; +wire [15:0] daisy_chain_19_1_3; +wire [15:0] daisy_chain_19_1_4; +wire [15:0] daisy_chain_19_1_5; +wire [15:0] daisy_chain_19_2_0; +wire [15:0] daisy_chain_19_2_1; +wire [15:0] daisy_chain_19_2_2; +wire [15:0] daisy_chain_19_2_3; +wire [15:0] daisy_chain_19_2_4; +wire [15:0] daisy_chain_19_2_5; +wire [15:0] daisy_chain_19_3_0; +wire [15:0] daisy_chain_19_3_1; +wire [15:0] daisy_chain_19_3_2; +wire [15:0] daisy_chain_19_3_3; +wire [15:0] daisy_chain_19_3_4; +wire [15:0] daisy_chain_19_3_5; +wire [15:0] daisy_chain_20_0_0; +wire [15:0] daisy_chain_20_0_1; +wire [15:0] daisy_chain_20_0_2; +wire [15:0] daisy_chain_20_0_3; +wire [15:0] daisy_chain_20_0_4; +wire [15:0] daisy_chain_20_0_5; +wire [15:0] daisy_chain_20_1_0; +wire [15:0] daisy_chain_20_1_1; +wire [15:0] daisy_chain_20_1_2; +wire [15:0] daisy_chain_20_1_3; +wire [15:0] daisy_chain_20_1_4; +wire [15:0] daisy_chain_20_1_5; +wire [15:0] daisy_chain_20_2_0; +wire [15:0] daisy_chain_20_2_1; +wire [15:0] daisy_chain_20_2_2; +wire [15:0] daisy_chain_20_2_3; +wire [15:0] daisy_chain_20_2_4; +wire [15:0] daisy_chain_20_2_5; +wire [15:0] daisy_chain_20_3_0; +wire [15:0] daisy_chain_20_3_1; +wire [15:0] daisy_chain_20_3_2; +wire [15:0] daisy_chain_20_3_3; +wire [15:0] daisy_chain_20_3_4; +wire [15:0] daisy_chain_20_3_5; +wire [15:0] daisy_chain_21_0_0; +wire [15:0] daisy_chain_21_0_1; +wire [15:0] daisy_chain_21_0_2; +wire [15:0] daisy_chain_21_0_3; +wire [15:0] daisy_chain_21_0_4; +wire [15:0] daisy_chain_21_0_5; +wire [15:0] daisy_chain_21_1_0; +wire [15:0] daisy_chain_21_1_1; +wire [15:0] daisy_chain_21_1_2; +wire [15:0] daisy_chain_21_1_3; +wire [15:0] daisy_chain_21_1_4; +wire [15:0] daisy_chain_21_1_5; +wire [15:0] daisy_chain_21_2_0; +wire [15:0] daisy_chain_21_2_1; +wire [15:0] daisy_chain_21_2_2; +wire [15:0] daisy_chain_21_2_3; +wire [15:0] daisy_chain_21_2_4; +wire [15:0] daisy_chain_21_2_5; +wire [15:0] daisy_chain_21_3_0; +wire [15:0] daisy_chain_21_3_1; +wire [15:0] daisy_chain_21_3_2; +wire [15:0] daisy_chain_21_3_3; +wire [15:0] daisy_chain_21_3_4; +wire [15:0] daisy_chain_21_3_5; +wire [15:0] daisy_chain_22_0_0; +wire [15:0] daisy_chain_22_0_1; +wire [15:0] daisy_chain_22_0_2; +wire [15:0] daisy_chain_22_0_3; +wire [15:0] daisy_chain_22_0_4; +wire [15:0] daisy_chain_22_0_5; +wire [15:0] daisy_chain_22_1_0; +wire [15:0] daisy_chain_22_1_1; +wire [15:0] daisy_chain_22_1_2; +wire [15:0] daisy_chain_22_1_3; +wire [15:0] daisy_chain_22_1_4; +wire [15:0] daisy_chain_22_1_5; +wire [15:0] daisy_chain_22_2_0; +wire [15:0] daisy_chain_22_2_1; +wire [15:0] daisy_chain_22_2_2; +wire [15:0] daisy_chain_22_2_3; +wire [15:0] daisy_chain_22_2_4; +wire [15:0] daisy_chain_22_2_5; +wire [15:0] daisy_chain_22_3_0; +wire [15:0] daisy_chain_22_3_1; +wire [15:0] daisy_chain_22_3_2; +wire [15:0] daisy_chain_22_3_3; +wire [15:0] daisy_chain_22_3_4; +wire [15:0] daisy_chain_22_3_5; +wire [15:0] daisy_chain_23_0_0; +wire [15:0] daisy_chain_23_0_1; +wire [15:0] daisy_chain_23_0_2; +wire [15:0] daisy_chain_23_0_3; +wire [15:0] daisy_chain_23_0_4; +wire [15:0] daisy_chain_23_0_5; +wire [15:0] daisy_chain_23_1_0; +wire [15:0] daisy_chain_23_1_1; +wire [15:0] daisy_chain_23_1_2; +wire [15:0] daisy_chain_23_1_3; +wire [15:0] daisy_chain_23_1_4; +wire [15:0] daisy_chain_23_1_5; +wire [15:0] daisy_chain_23_2_0; +wire [15:0] daisy_chain_23_2_1; +wire [15:0] daisy_chain_23_2_2; +wire [15:0] daisy_chain_23_2_3; +wire [15:0] daisy_chain_23_2_4; +wire [15:0] daisy_chain_23_2_5; +wire [15:0] daisy_chain_23_3_0; +wire [15:0] daisy_chain_23_3_1; +wire [15:0] daisy_chain_23_3_2; +wire [15:0] daisy_chain_23_3_3; +wire [15:0] daisy_chain_23_3_4; +wire [15:0] daisy_chain_23_3_5; +wire [29:0] PE_output_0_0; +wire [29:0] PE_output_0_1; +wire [29:0] PE_output_0_2; +wire [29:0] PE_output_0_3; +wire [29:0] PE_output_0_4; +wire [29:0] PE_output_0_5; +wire [29:0] PE_output_1_0; +wire [29:0] PE_output_1_1; +wire [29:0] PE_output_1_2; +wire [29:0] PE_output_1_3; +wire [29:0] PE_output_1_4; +wire [29:0] PE_output_1_5; +wire [29:0] PE_output_2_0; +wire [29:0] PE_output_2_1; +wire [29:0] PE_output_2_2; +wire [29:0] PE_output_2_3; +wire [29:0] PE_output_2_4; +wire [29:0] PE_output_2_5; +wire [29:0] PE_output_3_0; +wire [29:0] PE_output_3_1; +wire [29:0] PE_output_3_2; +wire [29:0] PE_output_3_3; +wire [29:0] PE_output_3_4; +wire [29:0] PE_output_3_5; +wire [29:0] PE_output_4_0; +wire [29:0] PE_output_4_1; +wire [29:0] PE_output_4_2; +wire [29:0] PE_output_4_3; +wire [29:0] PE_output_4_4; +wire [29:0] PE_output_4_5; +wire [29:0] PE_output_5_0; +wire [29:0] PE_output_5_1; +wire [29:0] PE_output_5_2; +wire [29:0] PE_output_5_3; +wire [29:0] PE_output_5_4; +wire [29:0] PE_output_5_5; +wire [29:0] PE_output_6_0; +wire [29:0] PE_output_6_1; +wire [29:0] PE_output_6_2; +wire [29:0] PE_output_6_3; +wire [29:0] PE_output_6_4; +wire [29:0] PE_output_6_5; +wire [29:0] PE_output_7_0; +wire [29:0] PE_output_7_1; +wire [29:0] PE_output_7_2; +wire [29:0] PE_output_7_3; +wire [29:0] PE_output_7_4; +wire [29:0] PE_output_7_5; +wire [29:0] PE_output_8_0; +wire [29:0] PE_output_8_1; +wire [29:0] PE_output_8_2; +wire [29:0] PE_output_8_3; +wire [29:0] PE_output_8_4; +wire [29:0] PE_output_8_5; +wire [29:0] PE_output_9_0; +wire [29:0] PE_output_9_1; +wire [29:0] PE_output_9_2; +wire [29:0] PE_output_9_3; +wire [29:0] PE_output_9_4; +wire [29:0] PE_output_9_5; +wire [29:0] PE_output_10_0; +wire [29:0] PE_output_10_1; +wire [29:0] PE_output_10_2; +wire [29:0] PE_output_10_3; +wire [29:0] PE_output_10_4; +wire [29:0] PE_output_10_5; +wire [29:0] PE_output_11_0; +wire [29:0] PE_output_11_1; +wire [29:0] PE_output_11_2; +wire [29:0] PE_output_11_3; +wire [29:0] PE_output_11_4; +wire [29:0] PE_output_11_5; +wire [29:0] PE_output_12_0; +wire [29:0] PE_output_12_1; +wire [29:0] PE_output_12_2; +wire [29:0] PE_output_12_3; +wire [29:0] PE_output_12_4; +wire [29:0] PE_output_12_5; +wire [29:0] PE_output_13_0; +wire [29:0] PE_output_13_1; +wire [29:0] PE_output_13_2; +wire [29:0] PE_output_13_3; +wire [29:0] PE_output_13_4; +wire [29:0] PE_output_13_5; +wire [29:0] PE_output_14_0; +wire [29:0] PE_output_14_1; +wire [29:0] PE_output_14_2; +wire [29:0] PE_output_14_3; +wire [29:0] PE_output_14_4; +wire [29:0] PE_output_14_5; +wire [29:0] PE_output_15_0; +wire [29:0] PE_output_15_1; +wire [29:0] PE_output_15_2; +wire [29:0] PE_output_15_3; +wire [29:0] PE_output_15_4; +wire [29:0] PE_output_15_5; +wire [29:0] PE_output_16_0; +wire [29:0] PE_output_16_1; +wire [29:0] PE_output_16_2; +wire [29:0] PE_output_16_3; +wire [29:0] PE_output_16_4; +wire [29:0] PE_output_16_5; +wire [29:0] PE_output_17_0; +wire [29:0] PE_output_17_1; +wire [29:0] PE_output_17_2; +wire [29:0] PE_output_17_3; +wire [29:0] PE_output_17_4; +wire [29:0] PE_output_17_5; +wire [29:0] PE_output_18_0; +wire [29:0] PE_output_18_1; +wire [29:0] PE_output_18_2; +wire [29:0] PE_output_18_3; +wire [29:0] PE_output_18_4; +wire [29:0] PE_output_18_5; +wire [29:0] PE_output_19_0; +wire [29:0] PE_output_19_1; +wire [29:0] PE_output_19_2; +wire [29:0] PE_output_19_3; +wire [29:0] PE_output_19_4; +wire [29:0] PE_output_19_5; +wire [29:0] PE_output_20_0; +wire [29:0] PE_output_20_1; +wire [29:0] PE_output_20_2; +wire [29:0] PE_output_20_3; +wire [29:0] PE_output_20_4; +wire [29:0] PE_output_20_5; +wire [29:0] PE_output_21_0; +wire [29:0] PE_output_21_1; +wire [29:0] PE_output_21_2; +wire [29:0] PE_output_21_3; +wire [29:0] PE_output_21_4; +wire [29:0] PE_output_21_5; +wire [29:0] PE_output_22_0; +wire [29:0] PE_output_22_1; +wire [29:0] PE_output_22_2; +wire [29:0] PE_output_22_3; +wire [29:0] PE_output_22_4; +wire [29:0] PE_output_22_5; +wire [29:0] PE_output_23_0; +wire [29:0] PE_output_23_1; +wire [29:0] PE_output_23_2; +wire [29:0] PE_output_23_3; +wire [29:0] PE_output_23_4; +wire [29:0] PE_output_23_5; +wire PE_valid_0; +wire PE_next_reset_0; +wire PE_next_valid_0; +wire PE_valid_1; +wire PE_next_reset_1; +wire PE_next_valid_1; +wire PE_valid_2; +wire PE_next_reset_2; +wire PE_next_valid_2; +wire PE_valid_3; +wire PE_next_reset_3; +wire PE_next_valid_3; +wire PE_valid_4; +wire PE_next_reset_4; +wire PE_next_valid_4; +wire PE_valid_5; +wire PE_next_reset_5; +wire PE_next_valid_5; +wire PE_valid_6; +wire PE_next_reset_6; +wire PE_next_valid_6; +wire PE_valid_7; +wire PE_next_reset_7; +wire PE_next_valid_7; +wire PE_valid_8; +wire PE_next_reset_8; +wire PE_next_valid_8; +wire PE_valid_9; +wire PE_next_reset_9; +wire PE_next_valid_9; +wire PE_valid_10; +wire PE_next_reset_10; +wire PE_next_valid_10; +wire PE_valid_11; +wire PE_next_reset_11; +wire PE_next_valid_11; +wire PE_valid_12; +wire PE_next_reset_12; +wire PE_next_valid_12; +wire PE_valid_13; +wire PE_next_reset_13; +wire PE_next_valid_13; +wire PE_valid_14; +wire PE_next_reset_14; +wire PE_next_valid_14; +wire PE_valid_15; +wire PE_next_reset_15; +wire PE_next_valid_15; +wire PE_valid_16; +wire PE_next_reset_16; +wire PE_next_valid_16; +wire PE_valid_17; +wire PE_next_reset_17; +wire PE_next_valid_17; +wire PE_valid_18; +wire PE_next_reset_18; +wire PE_next_valid_18; +wire PE_valid_19; +wire PE_next_reset_19; +wire PE_next_valid_19; +wire PE_valid_20; +wire PE_next_reset_20; +wire PE_next_valid_20; +wire PE_valid_21; +wire PE_next_reset_21; +wire PE_next_valid_21; +wire PE_valid_22; +wire PE_next_reset_22; +wire PE_next_valid_22; +wire PE_valid_23; +wire PE_next_reset_23; +wire PE_next_valid_23; + +// Inverse Winograd Wires +wire [15:0] INV_output_0_0; +wire [15:0] INV_output_0_1; +wire [15:0] INV_output_0_2; +wire [15:0] INV_output_0_3; +wire INV_valid_0; +wire [15:0] INV_output_1_0; +wire [15:0] INV_output_1_1; +wire [15:0] INV_output_1_2; +wire [15:0] INV_output_1_3; +wire INV_valid_1; +wire [15:0] INV_output_2_0; +wire [15:0] INV_output_2_1; +wire [15:0] INV_output_2_2; +wire [15:0] INV_output_2_3; +wire INV_valid_2; +wire [15:0] INV_output_3_0; +wire [15:0] INV_output_3_1; +wire [15:0] INV_output_3_2; +wire [15:0] INV_output_3_3; +wire INV_valid_3; +wire [15:0] INV_output_4_0; +wire [15:0] INV_output_4_1; +wire [15:0] INV_output_4_2; +wire [15:0] INV_output_4_3; +wire INV_valid_4; +wire [15:0] INV_output_5_0; +wire [15:0] INV_output_5_1; +wire [15:0] INV_output_5_2; +wire [15:0] INV_output_5_3; +wire INV_valid_5; +wire [15:0] INV_output_6_0; +wire [15:0] INV_output_6_1; +wire [15:0] INV_output_6_2; +wire [15:0] INV_output_6_3; +wire INV_valid_6; +wire [15:0] INV_output_7_0; +wire [15:0] INV_output_7_1; +wire [15:0] INV_output_7_2; +wire [15:0] INV_output_7_3; +wire INV_valid_7; +wire [15:0] INV_output_8_0; +wire [15:0] INV_output_8_1; +wire [15:0] INV_output_8_2; +wire [15:0] INV_output_8_3; +wire INV_valid_8; +wire [15:0] INV_output_9_0; +wire [15:0] INV_output_9_1; +wire [15:0] INV_output_9_2; +wire [15:0] INV_output_9_3; +wire INV_valid_9; +wire [15:0] INV_output_10_0; +wire [15:0] INV_output_10_1; +wire [15:0] INV_output_10_2; +wire [15:0] INV_output_10_3; +wire INV_valid_10; +wire [15:0] INV_output_11_0; +wire [15:0] INV_output_11_1; +wire [15:0] INV_output_11_2; +wire [15:0] INV_output_11_3; +wire INV_valid_11; +wire [15:0] INV_output_12_0; +wire [15:0] INV_output_12_1; +wire [15:0] INV_output_12_2; +wire [15:0] INV_output_12_3; +wire INV_valid_12; +wire [15:0] INV_output_13_0; +wire [15:0] INV_output_13_1; +wire [15:0] INV_output_13_2; +wire [15:0] INV_output_13_3; +wire INV_valid_13; +wire [15:0] INV_output_14_0; +wire [15:0] INV_output_14_1; +wire [15:0] INV_output_14_2; +wire [15:0] INV_output_14_3; +wire INV_valid_14; +wire [15:0] INV_output_15_0; +wire [15:0] INV_output_15_1; +wire [15:0] INV_output_15_2; +wire [15:0] INV_output_15_3; +wire INV_valid_15; +wire [15:0] INV_output_16_0; +wire [15:0] INV_output_16_1; +wire [15:0] INV_output_16_2; +wire [15:0] INV_output_16_3; +wire INV_valid_16; +wire [15:0] INV_output_17_0; +wire [15:0] INV_output_17_1; +wire [15:0] INV_output_17_2; +wire [15:0] INV_output_17_3; +wire INV_valid_17; +wire [15:0] INV_output_18_0; +wire [15:0] INV_output_18_1; +wire [15:0] INV_output_18_2; +wire [15:0] INV_output_18_3; +wire INV_valid_18; +wire [15:0] INV_output_19_0; +wire [15:0] INV_output_19_1; +wire [15:0] INV_output_19_2; +wire [15:0] INV_output_19_3; +wire INV_valid_19; +wire [15:0] INV_output_20_0; +wire [15:0] INV_output_20_1; +wire [15:0] INV_output_20_2; +wire [15:0] INV_output_20_3; +wire INV_valid_20; +wire [15:0] INV_output_21_0; +wire [15:0] INV_output_21_1; +wire [15:0] INV_output_21_2; +wire [15:0] INV_output_21_3; +wire INV_valid_21; +wire [15:0] INV_output_22_0; +wire [15:0] INV_output_22_1; +wire [15:0] INV_output_22_2; +wire [15:0] INV_output_22_3; +wire INV_valid_22; +wire [15:0] INV_output_23_0; +wire [15:0] INV_output_23_1; +wire [15:0] INV_output_23_2; +wire [15:0] INV_output_23_3; +wire INV_valid_23; + +// Pooling Wires +wire [15:0] POOL_output_0; +wire POOL_valid_0; +wire [15:0] POOL_output_1; +wire POOL_valid_1; +wire [15:0] POOL_output_2; +wire POOL_valid_2; +wire [15:0] POOL_output_3; +wire POOL_valid_3; +wire [15:0] POOL_output_4; +wire POOL_valid_4; +wire [15:0] POOL_output_5; +wire POOL_valid_5; +wire [15:0] POOL_output_6; +wire POOL_valid_6; +wire [15:0] POOL_output_7; +wire POOL_valid_7; +wire [15:0] POOL_output_8; +wire POOL_valid_8; +wire [15:0] POOL_output_9; +wire POOL_valid_9; +wire [15:0] POOL_output_10; +wire POOL_valid_10; +wire [15:0] POOL_output_11; +wire POOL_valid_11; +wire [15:0] POOL_output_12; +wire POOL_valid_12; +wire [15:0] POOL_output_13; +wire POOL_valid_13; +wire [15:0] POOL_output_14; +wire POOL_valid_14; +wire [15:0] POOL_output_15; +wire POOL_valid_15; +wire [15:0] POOL_output_16; +wire POOL_valid_16; +wire [15:0] POOL_output_17; +wire POOL_valid_17; +wire [15:0] POOL_output_18; +wire POOL_valid_18; +wire [15:0] POOL_output_19; +wire POOL_valid_19; +wire [15:0] POOL_output_20; +wire POOL_valid_20; +wire [15:0] POOL_output_21; +wire POOL_valid_21; +wire [15:0] POOL_output_22; +wire POOL_valid_22; +wire [15:0] POOL_output_23; +wire POOL_valid_23; + +// Store Output Wires +wire [15:0] STORE_output_0_0; +wire [15:0] STORE_output_0_1; +wire [15:0] STORE_output_0_2; +wire [15:0] STORE_output_0_3; +wire [15:0] STORE_output_1_0; +wire [15:0] STORE_output_1_1; +wire [15:0] STORE_output_1_2; +wire [15:0] STORE_output_1_3; +wire [15:0] STORE_output_2_0; +wire [15:0] STORE_output_2_1; +wire [15:0] STORE_output_2_2; +wire [15:0] STORE_output_2_3; +wire [15:0] STORE_output_3_0; +wire [15:0] STORE_output_3_1; +wire [15:0] STORE_output_3_2; +wire [15:0] STORE_output_3_3; +wire [15:0] STORE_output_4_0; +wire [15:0] STORE_output_4_1; +wire [15:0] STORE_output_4_2; +wire [15:0] STORE_output_4_3; +wire [15:0] STORE_output_5_0; +wire [15:0] STORE_output_5_1; +wire [15:0] STORE_output_5_2; +wire [15:0] STORE_output_5_3; +wire [13:0] STORE_addr; +wire STORE_wen_0; +wire STORE_wen_1; +wire STORE_wen_2; +wire STORE_wen_3; +wire STORE_wen_4; +wire STORE_wen_5; + +// Eltwise Wires +wire [15:0] f_buffer_el_0_0; +wire [15:0] f_buffer_el_0_1; +wire [15:0] f_buffer_el_0_2; +wire [15:0] f_buffer_el_0_3; +wire [15:0] f_buffer_el_1_0; +wire [15:0] f_buffer_el_1_1; +wire [15:0] f_buffer_el_1_2; +wire [15:0] f_buffer_el_1_3; +wire [15:0] f_buffer_el_2_0; +wire [15:0] f_buffer_el_2_1; +wire [15:0] f_buffer_el_2_2; +wire [15:0] f_buffer_el_2_3; +wire [15:0] f_buffer_el_3_0; +wire [15:0] f_buffer_el_3_1; +wire [15:0] f_buffer_el_3_2; +wire [15:0] f_buffer_el_3_3; +wire [15:0] f_buffer_el_4_0; +wire [15:0] f_buffer_el_4_1; +wire [15:0] f_buffer_el_4_2; +wire [15:0] f_buffer_el_4_3; +wire [15:0] f_buffer_el_5_0; +wire [15:0] f_buffer_el_5_1; +wire [15:0] f_buffer_el_5_2; +wire [15:0] f_buffer_el_5_3; + +// Output Wires +wire [15:0] dummy_out_0_0; +wire [15:0] dummy_out_0_1; +wire [15:0] dummy_out_0_2; +wire [15:0] dummy_out_0_3; +wire [15:0] dummy_out_1_0; +wire [15:0] dummy_out_1_1; +wire [15:0] dummy_out_1_2; +wire [15:0] dummy_out_1_3; +wire [15:0] dummy_out_2_0; +wire [15:0] dummy_out_2_1; +wire [15:0] dummy_out_2_2; +wire [15:0] dummy_out_2_3; +wire [15:0] dummy_out_3_0; +wire [15:0] dummy_out_3_1; +wire [15:0] dummy_out_3_2; +wire [15:0] dummy_out_3_3; +wire [15:0] dummy_out_4_0; +wire [15:0] dummy_out_4_1; +wire [15:0] dummy_out_4_2; +wire [15:0] dummy_out_4_3; +wire [15:0] dummy_out_5_0; +wire [15:0] dummy_out_5_1; +wire [15:0] dummy_out_5_2; +wire [15:0] dummy_out_5_3; + +stream_buffer_0_0 stream_buffer_0_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_0_0), + .i_wen1(STORE_wen_0), + .i_ddr(i_ddr_0_0), + .i_pool(STORE_output_0_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_0_0), + .o_feature_1(f_buffer_el_0_0), + .o_done(valid_buff_0_0) +); +assign dummy_out_0_0 = f_buffer_el_0_0; + +stream_buffer_0_1 stream_buffer_0_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_0_1), + .i_wen1(STORE_wen_0), + .i_ddr(i_ddr_0_1), + .i_pool(STORE_output_0_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_0_1), + .o_feature_1(f_buffer_el_0_1), + .o_done(valid_buff_0_1) +); +assign dummy_out_0_1 = f_buffer_el_0_1; + +stream_buffer_0_2 stream_buffer_0_2_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_0_2), + .i_wen1(STORE_wen_0), + .i_ddr(i_ddr_0_2), + .i_pool(STORE_output_0_2), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_0_2), + .o_feature_1(f_buffer_el_0_2), + .o_done(valid_buff_0_2) +); +assign dummy_out_0_2 = f_buffer_el_0_2; + +stream_buffer_0_3 stream_buffer_0_3_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_0_3), + .i_wen1(STORE_wen_0), + .i_ddr(i_ddr_0_3), + .i_pool(STORE_output_0_3), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_0_3), + .o_feature_1(f_buffer_el_0_3), + .o_done(valid_buff_0_3) +); +assign dummy_out_0_3 = f_buffer_el_0_3; + +stream_buffer_1_0 stream_buffer_1_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_1_0), + .i_wen1(STORE_wen_1), + .i_ddr(i_ddr_1_0), + .i_pool(STORE_output_1_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_1_0), + .o_feature_1(f_buffer_el_1_0), + .o_done(valid_buff_1_0) +); +assign dummy_out_1_0 = f_buffer_el_1_0; + +stream_buffer_1_1 stream_buffer_1_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_1_1), + .i_wen1(STORE_wen_1), + .i_ddr(i_ddr_1_1), + .i_pool(STORE_output_1_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_1_1), + .o_feature_1(f_buffer_el_1_1), + .o_done(valid_buff_1_1) +); +assign dummy_out_1_1 = f_buffer_el_1_1; + +stream_buffer_1_2 stream_buffer_1_2_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_1_2), + .i_wen1(STORE_wen_1), + .i_ddr(i_ddr_1_2), + .i_pool(STORE_output_1_2), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_1_2), + .o_feature_1(f_buffer_el_1_2), + .o_done(valid_buff_1_2) +); +assign dummy_out_1_2 = f_buffer_el_1_2; + +stream_buffer_1_3 stream_buffer_1_3_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_1_3), + .i_wen1(STORE_wen_1), + .i_ddr(i_ddr_1_3), + .i_pool(STORE_output_1_3), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_1_3), + .o_feature_1(f_buffer_el_1_3), + .o_done(valid_buff_1_3) +); +assign dummy_out_1_3 = f_buffer_el_1_3; + +stream_buffer_2_0 stream_buffer_2_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_2_0), + .i_wen1(STORE_wen_2), + .i_ddr(i_ddr_2_0), + .i_pool(STORE_output_2_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_2_0), + .o_feature_1(f_buffer_el_2_0), + .o_done(valid_buff_2_0) +); +assign dummy_out_2_0 = f_buffer_el_2_0; + +stream_buffer_2_1 stream_buffer_2_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_2_1), + .i_wen1(STORE_wen_2), + .i_ddr(i_ddr_2_1), + .i_pool(STORE_output_2_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_2_1), + .o_feature_1(f_buffer_el_2_1), + .o_done(valid_buff_2_1) +); +assign dummy_out_2_1 = f_buffer_el_2_1; + +stream_buffer_2_2 stream_buffer_2_2_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_2_2), + .i_wen1(STORE_wen_2), + .i_ddr(i_ddr_2_2), + .i_pool(STORE_output_2_2), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_2_2), + .o_feature_1(f_buffer_el_2_2), + .o_done(valid_buff_2_2) +); +assign dummy_out_2_2 = f_buffer_el_2_2; + +stream_buffer_2_3 stream_buffer_2_3_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_2_3), + .i_wen1(STORE_wen_2), + .i_ddr(i_ddr_2_3), + .i_pool(STORE_output_2_3), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_2_3), + .o_feature_1(f_buffer_el_2_3), + .o_done(valid_buff_2_3) +); +assign dummy_out_2_3 = f_buffer_el_2_3; + +stream_buffer_3_0 stream_buffer_3_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_3_0), + .i_wen1(STORE_wen_3), + .i_ddr(i_ddr_3_0), + .i_pool(STORE_output_3_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_3_0), + .o_feature_1(f_buffer_el_3_0), + .o_done(valid_buff_3_0) +); +assign dummy_out_3_0 = f_buffer_el_3_0; + +stream_buffer_3_1 stream_buffer_3_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_3_1), + .i_wen1(STORE_wen_3), + .i_ddr(i_ddr_3_1), + .i_pool(STORE_output_3_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_3_1), + .o_feature_1(f_buffer_el_3_1), + .o_done(valid_buff_3_1) +); +assign dummy_out_3_1 = f_buffer_el_3_1; + +stream_buffer_3_2 stream_buffer_3_2_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_3_2), + .i_wen1(STORE_wen_3), + .i_ddr(i_ddr_3_2), + .i_pool(STORE_output_3_2), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_3_2), + .o_feature_1(f_buffer_el_3_2), + .o_done(valid_buff_3_2) +); +assign dummy_out_3_2 = f_buffer_el_3_2; + +stream_buffer_3_3 stream_buffer_3_3_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_3_3), + .i_wen1(STORE_wen_3), + .i_ddr(i_ddr_3_3), + .i_pool(STORE_output_3_3), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_3_3), + .o_feature_1(f_buffer_el_3_3), + .o_done(valid_buff_3_3) +); +assign dummy_out_3_3 = f_buffer_el_3_3; + +stream_buffer_4_0 stream_buffer_4_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_4_0), + .i_wen1(STORE_wen_4), + .i_ddr(i_ddr_4_0), + .i_pool(STORE_output_4_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_4_0), + .o_feature_1(f_buffer_el_4_0), + .o_done(valid_buff_4_0) +); +assign dummy_out_4_0 = f_buffer_el_4_0; + +stream_buffer_4_1 stream_buffer_4_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_4_1), + .i_wen1(STORE_wen_4), + .i_ddr(i_ddr_4_1), + .i_pool(STORE_output_4_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_4_1), + .o_feature_1(f_buffer_el_4_1), + .o_done(valid_buff_4_1) +); +assign dummy_out_4_1 = f_buffer_el_4_1; + +stream_buffer_4_2 stream_buffer_4_2_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_4_2), + .i_wen1(STORE_wen_4), + .i_ddr(i_ddr_4_2), + .i_pool(STORE_output_4_2), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_4_2), + .o_feature_1(f_buffer_el_4_2), + .o_done(valid_buff_4_2) +); +assign dummy_out_4_2 = f_buffer_el_4_2; + +stream_buffer_4_3 stream_buffer_4_3_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_4_3), + .i_wen1(STORE_wen_4), + .i_ddr(i_ddr_4_3), + .i_pool(STORE_output_4_3), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_4_3), + .o_feature_1(f_buffer_el_4_3), + .o_done(valid_buff_4_3) +); +assign dummy_out_4_3 = f_buffer_el_4_3; + +stream_buffer_5_0 stream_buffer_5_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_5_0), + .i_wen1(STORE_wen_5), + .i_ddr(i_ddr_5_0), + .i_pool(STORE_output_5_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_5_0), + .o_feature_1(f_buffer_el_5_0), + .o_done(valid_buff_5_0) +); +assign dummy_out_5_0 = f_buffer_el_5_0; + +stream_buffer_5_1 stream_buffer_5_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_5_1), + .i_wen1(STORE_wen_5), + .i_ddr(i_ddr_5_1), + .i_pool(STORE_output_5_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_5_1), + .o_feature_1(f_buffer_el_5_1), + .o_done(valid_buff_5_1) +); +assign dummy_out_5_1 = f_buffer_el_5_1; + +stream_buffer_5_2 stream_buffer_5_2_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_5_2), + .i_wen1(STORE_wen_5), + .i_ddr(i_ddr_5_2), + .i_pool(STORE_output_5_2), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_5_2), + .o_feature_1(f_buffer_el_5_2), + .o_done(valid_buff_5_2) +); +assign dummy_out_5_2 = f_buffer_el_5_2; + +stream_buffer_5_3 stream_buffer_5_3_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_5_3), + .i_wen1(STORE_wen_5), + .i_ddr(i_ddr_5_3), + .i_pool(STORE_output_5_3), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_5_3), + .o_feature_1(f_buffer_el_5_3), + .o_done(valid_buff_5_3) +); +assign dummy_out_5_3 = f_buffer_el_5_3; + +winograd_transform_0 winograd_transform_0_inst ( + .clk(clk), + .i_valid(valid_buff_0_0), + .i_result_0_0(f_buffer_pe_0_0), + .i_result_0_1(f_buffer_pe_0_1), + .i_result_0_2(f_buffer_pe_0_2), + .i_result_0_3(f_buffer_pe_0_3), + .i_result_1_0(f_buffer_pe_1_0), + .i_result_1_1(f_buffer_pe_1_1), + .i_result_1_2(f_buffer_pe_1_2), + .i_result_1_3(f_buffer_pe_1_3), + .i_result_2_0(f_buffer_pe_2_0), + .i_result_2_1(f_buffer_pe_2_1), + .i_result_2_2(f_buffer_pe_2_2), + .i_result_2_3(f_buffer_pe_2_3), + .i_result_3_0(f_buffer_pe_3_0), + .i_result_3_1(f_buffer_pe_3_1), + .i_result_3_2(f_buffer_pe_3_2), + .i_result_3_3(f_buffer_pe_3_3), + .i_result_4_0(f_buffer_pe_4_0), + .i_result_4_1(f_buffer_pe_4_1), + .i_result_4_2(f_buffer_pe_4_2), + .i_result_4_3(f_buffer_pe_4_3), + .i_result_5_0(f_buffer_pe_5_0), + .i_result_5_1(f_buffer_pe_5_1), + .i_result_5_2(f_buffer_pe_5_2), + .i_result_5_3(f_buffer_pe_5_3), + .o_feature_0(f_winograd_0_0), + .o_feature_1(f_winograd_0_1), + .o_feature_2(f_winograd_0_2), + .o_feature_3(f_winograd_0_3), + .o_feature_4(f_winograd_0_4), + .o_feature_5(f_winograd_0_5), + .o_valid(winograd_valid_0) +); + +winograd_transform_1 winograd_transform_1_inst ( + .clk(clk), + .i_valid(valid_buff_0_0), + .i_result_0_0(f_buffer_pe_0_0), + .i_result_0_1(f_buffer_pe_0_1), + .i_result_0_2(f_buffer_pe_0_2), + .i_result_0_3(f_buffer_pe_0_3), + .i_result_1_0(f_buffer_pe_1_0), + .i_result_1_1(f_buffer_pe_1_1), + .i_result_1_2(f_buffer_pe_1_2), + .i_result_1_3(f_buffer_pe_1_3), + .i_result_2_0(f_buffer_pe_2_0), + .i_result_2_1(f_buffer_pe_2_1), + .i_result_2_2(f_buffer_pe_2_2), + .i_result_2_3(f_buffer_pe_2_3), + .i_result_3_0(f_buffer_pe_3_0), + .i_result_3_1(f_buffer_pe_3_1), + .i_result_3_2(f_buffer_pe_3_2), + .i_result_3_3(f_buffer_pe_3_3), + .i_result_4_0(f_buffer_pe_4_0), + .i_result_4_1(f_buffer_pe_4_1), + .i_result_4_2(f_buffer_pe_4_2), + .i_result_4_3(f_buffer_pe_4_3), + .i_result_5_0(f_buffer_pe_5_0), + .i_result_5_1(f_buffer_pe_5_1), + .i_result_5_2(f_buffer_pe_5_2), + .i_result_5_3(f_buffer_pe_5_3), + .o_feature_0(f_winograd_1_0), + .o_feature_1(f_winograd_1_1), + .o_feature_2(f_winograd_1_2), + .o_feature_3(f_winograd_1_3), + .o_feature_4(f_winograd_1_4), + .o_feature_5(f_winograd_1_5), + .o_valid(winograd_valid_1) +); + +winograd_transform_2 winograd_transform_2_inst ( + .clk(clk), + .i_valid(valid_buff_0_0), + .i_result_0_0(f_buffer_pe_0_0), + .i_result_0_1(f_buffer_pe_0_1), + .i_result_0_2(f_buffer_pe_0_2), + .i_result_0_3(f_buffer_pe_0_3), + .i_result_1_0(f_buffer_pe_1_0), + .i_result_1_1(f_buffer_pe_1_1), + .i_result_1_2(f_buffer_pe_1_2), + .i_result_1_3(f_buffer_pe_1_3), + .i_result_2_0(f_buffer_pe_2_0), + .i_result_2_1(f_buffer_pe_2_1), + .i_result_2_2(f_buffer_pe_2_2), + .i_result_2_3(f_buffer_pe_2_3), + .i_result_3_0(f_buffer_pe_3_0), + .i_result_3_1(f_buffer_pe_3_1), + .i_result_3_2(f_buffer_pe_3_2), + .i_result_3_3(f_buffer_pe_3_3), + .i_result_4_0(f_buffer_pe_4_0), + .i_result_4_1(f_buffer_pe_4_1), + .i_result_4_2(f_buffer_pe_4_2), + .i_result_4_3(f_buffer_pe_4_3), + .i_result_5_0(f_buffer_pe_5_0), + .i_result_5_1(f_buffer_pe_5_1), + .i_result_5_2(f_buffer_pe_5_2), + .i_result_5_3(f_buffer_pe_5_3), + .o_feature_0(f_winograd_2_0), + .o_feature_1(f_winograd_2_1), + .o_feature_2(f_winograd_2_2), + .o_feature_3(f_winograd_2_3), + .o_feature_4(f_winograd_2_4), + .o_feature_5(f_winograd_2_5), + .o_valid(winograd_valid_2) +); + +winograd_transform_3 winograd_transform_3_inst ( + .clk(clk), + .i_valid(valid_buff_0_0), + .i_result_0_0(f_buffer_pe_0_0), + .i_result_0_1(f_buffer_pe_0_1), + .i_result_0_2(f_buffer_pe_0_2), + .i_result_0_3(f_buffer_pe_0_3), + .i_result_1_0(f_buffer_pe_1_0), + .i_result_1_1(f_buffer_pe_1_1), + .i_result_1_2(f_buffer_pe_1_2), + .i_result_1_3(f_buffer_pe_1_3), + .i_result_2_0(f_buffer_pe_2_0), + .i_result_2_1(f_buffer_pe_2_1), + .i_result_2_2(f_buffer_pe_2_2), + .i_result_2_3(f_buffer_pe_2_3), + .i_result_3_0(f_buffer_pe_3_0), + .i_result_3_1(f_buffer_pe_3_1), + .i_result_3_2(f_buffer_pe_3_2), + .i_result_3_3(f_buffer_pe_3_3), + .i_result_4_0(f_buffer_pe_4_0), + .i_result_4_1(f_buffer_pe_4_1), + .i_result_4_2(f_buffer_pe_4_2), + .i_result_4_3(f_buffer_pe_4_3), + .i_result_5_0(f_buffer_pe_5_0), + .i_result_5_1(f_buffer_pe_5_1), + .i_result_5_2(f_buffer_pe_5_2), + .i_result_5_3(f_buffer_pe_5_3), + .o_feature_0(f_winograd_3_0), + .o_feature_1(f_winograd_3_1), + .o_feature_2(f_winograd_3_2), + .o_feature_3(f_winograd_3_3), + .o_feature_4(f_winograd_3_4), + .o_feature_5(f_winograd_3_5), + .o_valid(winograd_valid_3) +); + +processing_element processing_element_inst_0 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(winograd_valid_0), + .i_features_0_0(f_winograd_0_0), + .o_features_0_0(daisy_chain_0_0_0), + .i_features_0_1(f_winograd_0_1), + .o_features_0_1(daisy_chain_0_0_1), + .i_features_0_2(f_winograd_0_2), + .o_features_0_2(daisy_chain_0_0_2), + .i_features_0_3(f_winograd_0_3), + .o_features_0_3(daisy_chain_0_0_3), + .i_features_0_4(f_winograd_0_4), + .o_features_0_4(daisy_chain_0_0_4), + .i_features_0_5(f_winograd_0_5), + .o_features_0_5(daisy_chain_0_0_5), + .i_features_1_0(f_winograd_1_0), + .o_features_1_0(daisy_chain_0_1_0), + .i_features_1_1(f_winograd_1_1), + .o_features_1_1(daisy_chain_0_1_1), + .i_features_1_2(f_winograd_1_2), + .o_features_1_2(daisy_chain_0_1_2), + .i_features_1_3(f_winograd_1_3), + .o_features_1_3(daisy_chain_0_1_3), + .i_features_1_4(f_winograd_1_4), + .o_features_1_4(daisy_chain_0_1_4), + .i_features_1_5(f_winograd_1_5), + .o_features_1_5(daisy_chain_0_1_5), + .i_features_2_0(f_winograd_2_0), + .o_features_2_0(daisy_chain_0_2_0), + .i_features_2_1(f_winograd_2_1), + .o_features_2_1(daisy_chain_0_2_1), + .i_features_2_2(f_winograd_2_2), + .o_features_2_2(daisy_chain_0_2_2), + .i_features_2_3(f_winograd_2_3), + .o_features_2_3(daisy_chain_0_2_3), + .i_features_2_4(f_winograd_2_4), + .o_features_2_4(daisy_chain_0_2_4), + .i_features_2_5(f_winograd_2_5), + .o_features_2_5(daisy_chain_0_2_5), + .i_features_3_0(f_winograd_3_0), + .o_features_3_0(daisy_chain_0_3_0), + .i_features_3_1(f_winograd_3_1), + .o_features_3_1(daisy_chain_0_3_1), + .i_features_3_2(f_winograd_3_2), + .o_features_3_2(daisy_chain_0_3_2), + .i_features_3_3(f_winograd_3_3), + .o_features_3_3(daisy_chain_0_3_3), + .i_features_3_4(f_winograd_3_4), + .o_features_3_4(daisy_chain_0_3_4), + .i_features_3_5(f_winograd_3_5), + .o_features_3_5(daisy_chain_0_3_5), + .o_result_0(PE_output_0_0), + .o_result_1(PE_output_0_1), + .o_result_2(PE_output_0_2), + .o_result_3(PE_output_0_3), + .o_result_4(PE_output_0_4), + .o_result_5(PE_output_0_5), + .o_valid(PE_valid_0), + .o_next_reset(PE_next_reset_0), + .o_next_valid(PE_next_valid_0) +); + +processing_element processing_element_inst_1 ( + .clk(clk), + .i_reset(PE_next_reset_0), + .i_valid(PE_next_valid_0), + .i_features_0_0(daisy_chain_0_0_0), + .o_features_0_0(daisy_chain_1_0_0), + .i_features_0_1(daisy_chain_0_0_1), + .o_features_0_1(daisy_chain_1_0_1), + .i_features_0_2(daisy_chain_0_0_2), + .o_features_0_2(daisy_chain_1_0_2), + .i_features_0_3(daisy_chain_0_0_3), + .o_features_0_3(daisy_chain_1_0_3), + .i_features_0_4(daisy_chain_0_0_4), + .o_features_0_4(daisy_chain_1_0_4), + .i_features_0_5(daisy_chain_0_0_5), + .o_features_0_5(daisy_chain_1_0_5), + .i_features_1_0(daisy_chain_0_1_0), + .o_features_1_0(daisy_chain_1_1_0), + .i_features_1_1(daisy_chain_0_1_1), + .o_features_1_1(daisy_chain_1_1_1), + .i_features_1_2(daisy_chain_0_1_2), + .o_features_1_2(daisy_chain_1_1_2), + .i_features_1_3(daisy_chain_0_1_3), + .o_features_1_3(daisy_chain_1_1_3), + .i_features_1_4(daisy_chain_0_1_4), + .o_features_1_4(daisy_chain_1_1_4), + .i_features_1_5(daisy_chain_0_1_5), + .o_features_1_5(daisy_chain_1_1_5), + .i_features_2_0(daisy_chain_0_2_0), + .o_features_2_0(daisy_chain_1_2_0), + .i_features_2_1(daisy_chain_0_2_1), + .o_features_2_1(daisy_chain_1_2_1), + .i_features_2_2(daisy_chain_0_2_2), + .o_features_2_2(daisy_chain_1_2_2), + .i_features_2_3(daisy_chain_0_2_3), + .o_features_2_3(daisy_chain_1_2_3), + .i_features_2_4(daisy_chain_0_2_4), + .o_features_2_4(daisy_chain_1_2_4), + .i_features_2_5(daisy_chain_0_2_5), + .o_features_2_5(daisy_chain_1_2_5), + .i_features_3_0(daisy_chain_0_3_0), + .o_features_3_0(daisy_chain_1_3_0), + .i_features_3_1(daisy_chain_0_3_1), + .o_features_3_1(daisy_chain_1_3_1), + .i_features_3_2(daisy_chain_0_3_2), + .o_features_3_2(daisy_chain_1_3_2), + .i_features_3_3(daisy_chain_0_3_3), + .o_features_3_3(daisy_chain_1_3_3), + .i_features_3_4(daisy_chain_0_3_4), + .o_features_3_4(daisy_chain_1_3_4), + .i_features_3_5(daisy_chain_0_3_5), + .o_features_3_5(daisy_chain_1_3_5), + .o_result_0(PE_output_1_0), + .o_result_1(PE_output_1_1), + .o_result_2(PE_output_1_2), + .o_result_3(PE_output_1_3), + .o_result_4(PE_output_1_4), + .o_result_5(PE_output_1_5), + .o_valid(PE_valid_1), + .o_next_reset(PE_next_reset_1), + .o_next_valid(PE_next_valid_1) +); + +processing_element processing_element_inst_2 ( + .clk(clk), + .i_reset(PE_next_reset_1), + .i_valid(PE_next_valid_1), + .i_features_0_0(daisy_chain_1_0_0), + .o_features_0_0(daisy_chain_2_0_0), + .i_features_0_1(daisy_chain_1_0_1), + .o_features_0_1(daisy_chain_2_0_1), + .i_features_0_2(daisy_chain_1_0_2), + .o_features_0_2(daisy_chain_2_0_2), + .i_features_0_3(daisy_chain_1_0_3), + .o_features_0_3(daisy_chain_2_0_3), + .i_features_0_4(daisy_chain_1_0_4), + .o_features_0_4(daisy_chain_2_0_4), + .i_features_0_5(daisy_chain_1_0_5), + .o_features_0_5(daisy_chain_2_0_5), + .i_features_1_0(daisy_chain_1_1_0), + .o_features_1_0(daisy_chain_2_1_0), + .i_features_1_1(daisy_chain_1_1_1), + .o_features_1_1(daisy_chain_2_1_1), + .i_features_1_2(daisy_chain_1_1_2), + .o_features_1_2(daisy_chain_2_1_2), + .i_features_1_3(daisy_chain_1_1_3), + .o_features_1_3(daisy_chain_2_1_3), + .i_features_1_4(daisy_chain_1_1_4), + .o_features_1_4(daisy_chain_2_1_4), + .i_features_1_5(daisy_chain_1_1_5), + .o_features_1_5(daisy_chain_2_1_5), + .i_features_2_0(daisy_chain_1_2_0), + .o_features_2_0(daisy_chain_2_2_0), + .i_features_2_1(daisy_chain_1_2_1), + .o_features_2_1(daisy_chain_2_2_1), + .i_features_2_2(daisy_chain_1_2_2), + .o_features_2_2(daisy_chain_2_2_2), + .i_features_2_3(daisy_chain_1_2_3), + .o_features_2_3(daisy_chain_2_2_3), + .i_features_2_4(daisy_chain_1_2_4), + .o_features_2_4(daisy_chain_2_2_4), + .i_features_2_5(daisy_chain_1_2_5), + .o_features_2_5(daisy_chain_2_2_5), + .i_features_3_0(daisy_chain_1_3_0), + .o_features_3_0(daisy_chain_2_3_0), + .i_features_3_1(daisy_chain_1_3_1), + .o_features_3_1(daisy_chain_2_3_1), + .i_features_3_2(daisy_chain_1_3_2), + .o_features_3_2(daisy_chain_2_3_2), + .i_features_3_3(daisy_chain_1_3_3), + .o_features_3_3(daisy_chain_2_3_3), + .i_features_3_4(daisy_chain_1_3_4), + .o_features_3_4(daisy_chain_2_3_4), + .i_features_3_5(daisy_chain_1_3_5), + .o_features_3_5(daisy_chain_2_3_5), + .o_result_0(PE_output_2_0), + .o_result_1(PE_output_2_1), + .o_result_2(PE_output_2_2), + .o_result_3(PE_output_2_3), + .o_result_4(PE_output_2_4), + .o_result_5(PE_output_2_5), + .o_valid(PE_valid_2), + .o_next_reset(PE_next_reset_2), + .o_next_valid(PE_next_valid_2) +); + +processing_element processing_element_inst_3 ( + .clk(clk), + .i_reset(PE_next_reset_2), + .i_valid(PE_next_valid_2), + .i_features_0_0(daisy_chain_2_0_0), + .o_features_0_0(daisy_chain_3_0_0), + .i_features_0_1(daisy_chain_2_0_1), + .o_features_0_1(daisy_chain_3_0_1), + .i_features_0_2(daisy_chain_2_0_2), + .o_features_0_2(daisy_chain_3_0_2), + .i_features_0_3(daisy_chain_2_0_3), + .o_features_0_3(daisy_chain_3_0_3), + .i_features_0_4(daisy_chain_2_0_4), + .o_features_0_4(daisy_chain_3_0_4), + .i_features_0_5(daisy_chain_2_0_5), + .o_features_0_5(daisy_chain_3_0_5), + .i_features_1_0(daisy_chain_2_1_0), + .o_features_1_0(daisy_chain_3_1_0), + .i_features_1_1(daisy_chain_2_1_1), + .o_features_1_1(daisy_chain_3_1_1), + .i_features_1_2(daisy_chain_2_1_2), + .o_features_1_2(daisy_chain_3_1_2), + .i_features_1_3(daisy_chain_2_1_3), + .o_features_1_3(daisy_chain_3_1_3), + .i_features_1_4(daisy_chain_2_1_4), + .o_features_1_4(daisy_chain_3_1_4), + .i_features_1_5(daisy_chain_2_1_5), + .o_features_1_5(daisy_chain_3_1_5), + .i_features_2_0(daisy_chain_2_2_0), + .o_features_2_0(daisy_chain_3_2_0), + .i_features_2_1(daisy_chain_2_2_1), + .o_features_2_1(daisy_chain_3_2_1), + .i_features_2_2(daisy_chain_2_2_2), + .o_features_2_2(daisy_chain_3_2_2), + .i_features_2_3(daisy_chain_2_2_3), + .o_features_2_3(daisy_chain_3_2_3), + .i_features_2_4(daisy_chain_2_2_4), + .o_features_2_4(daisy_chain_3_2_4), + .i_features_2_5(daisy_chain_2_2_5), + .o_features_2_5(daisy_chain_3_2_5), + .i_features_3_0(daisy_chain_2_3_0), + .o_features_3_0(daisy_chain_3_3_0), + .i_features_3_1(daisy_chain_2_3_1), + .o_features_3_1(daisy_chain_3_3_1), + .i_features_3_2(daisy_chain_2_3_2), + .o_features_3_2(daisy_chain_3_3_2), + .i_features_3_3(daisy_chain_2_3_3), + .o_features_3_3(daisy_chain_3_3_3), + .i_features_3_4(daisy_chain_2_3_4), + .o_features_3_4(daisy_chain_3_3_4), + .i_features_3_5(daisy_chain_2_3_5), + .o_features_3_5(daisy_chain_3_3_5), + .o_result_0(PE_output_3_0), + .o_result_1(PE_output_3_1), + .o_result_2(PE_output_3_2), + .o_result_3(PE_output_3_3), + .o_result_4(PE_output_3_4), + .o_result_5(PE_output_3_5), + .o_valid(PE_valid_3), + .o_next_reset(PE_next_reset_3), + .o_next_valid(PE_next_valid_3) +); + +processing_element processing_element_inst_4 ( + .clk(clk), + .i_reset(PE_next_reset_3), + .i_valid(PE_next_valid_3), + .i_features_0_0(daisy_chain_3_0_0), + .o_features_0_0(daisy_chain_4_0_0), + .i_features_0_1(daisy_chain_3_0_1), + .o_features_0_1(daisy_chain_4_0_1), + .i_features_0_2(daisy_chain_3_0_2), + .o_features_0_2(daisy_chain_4_0_2), + .i_features_0_3(daisy_chain_3_0_3), + .o_features_0_3(daisy_chain_4_0_3), + .i_features_0_4(daisy_chain_3_0_4), + .o_features_0_4(daisy_chain_4_0_4), + .i_features_0_5(daisy_chain_3_0_5), + .o_features_0_5(daisy_chain_4_0_5), + .i_features_1_0(daisy_chain_3_1_0), + .o_features_1_0(daisy_chain_4_1_0), + .i_features_1_1(daisy_chain_3_1_1), + .o_features_1_1(daisy_chain_4_1_1), + .i_features_1_2(daisy_chain_3_1_2), + .o_features_1_2(daisy_chain_4_1_2), + .i_features_1_3(daisy_chain_3_1_3), + .o_features_1_3(daisy_chain_4_1_3), + .i_features_1_4(daisy_chain_3_1_4), + .o_features_1_4(daisy_chain_4_1_4), + .i_features_1_5(daisy_chain_3_1_5), + .o_features_1_5(daisy_chain_4_1_5), + .i_features_2_0(daisy_chain_3_2_0), + .o_features_2_0(daisy_chain_4_2_0), + .i_features_2_1(daisy_chain_3_2_1), + .o_features_2_1(daisy_chain_4_2_1), + .i_features_2_2(daisy_chain_3_2_2), + .o_features_2_2(daisy_chain_4_2_2), + .i_features_2_3(daisy_chain_3_2_3), + .o_features_2_3(daisy_chain_4_2_3), + .i_features_2_4(daisy_chain_3_2_4), + .o_features_2_4(daisy_chain_4_2_4), + .i_features_2_5(daisy_chain_3_2_5), + .o_features_2_5(daisy_chain_4_2_5), + .i_features_3_0(daisy_chain_3_3_0), + .o_features_3_0(daisy_chain_4_3_0), + .i_features_3_1(daisy_chain_3_3_1), + .o_features_3_1(daisy_chain_4_3_1), + .i_features_3_2(daisy_chain_3_3_2), + .o_features_3_2(daisy_chain_4_3_2), + .i_features_3_3(daisy_chain_3_3_3), + .o_features_3_3(daisy_chain_4_3_3), + .i_features_3_4(daisy_chain_3_3_4), + .o_features_3_4(daisy_chain_4_3_4), + .i_features_3_5(daisy_chain_3_3_5), + .o_features_3_5(daisy_chain_4_3_5), + .o_result_0(PE_output_4_0), + .o_result_1(PE_output_4_1), + .o_result_2(PE_output_4_2), + .o_result_3(PE_output_4_3), + .o_result_4(PE_output_4_4), + .o_result_5(PE_output_4_5), + .o_valid(PE_valid_4), + .o_next_reset(PE_next_reset_4), + .o_next_valid(PE_next_valid_4) +); + +processing_element processing_element_inst_5 ( + .clk(clk), + .i_reset(PE_next_reset_4), + .i_valid(PE_next_valid_4), + .i_features_0_0(daisy_chain_4_0_0), + .o_features_0_0(daisy_chain_5_0_0), + .i_features_0_1(daisy_chain_4_0_1), + .o_features_0_1(daisy_chain_5_0_1), + .i_features_0_2(daisy_chain_4_0_2), + .o_features_0_2(daisy_chain_5_0_2), + .i_features_0_3(daisy_chain_4_0_3), + .o_features_0_3(daisy_chain_5_0_3), + .i_features_0_4(daisy_chain_4_0_4), + .o_features_0_4(daisy_chain_5_0_4), + .i_features_0_5(daisy_chain_4_0_5), + .o_features_0_5(daisy_chain_5_0_5), + .i_features_1_0(daisy_chain_4_1_0), + .o_features_1_0(daisy_chain_5_1_0), + .i_features_1_1(daisy_chain_4_1_1), + .o_features_1_1(daisy_chain_5_1_1), + .i_features_1_2(daisy_chain_4_1_2), + .o_features_1_2(daisy_chain_5_1_2), + .i_features_1_3(daisy_chain_4_1_3), + .o_features_1_3(daisy_chain_5_1_3), + .i_features_1_4(daisy_chain_4_1_4), + .o_features_1_4(daisy_chain_5_1_4), + .i_features_1_5(daisy_chain_4_1_5), + .o_features_1_5(daisy_chain_5_1_5), + .i_features_2_0(daisy_chain_4_2_0), + .o_features_2_0(daisy_chain_5_2_0), + .i_features_2_1(daisy_chain_4_2_1), + .o_features_2_1(daisy_chain_5_2_1), + .i_features_2_2(daisy_chain_4_2_2), + .o_features_2_2(daisy_chain_5_2_2), + .i_features_2_3(daisy_chain_4_2_3), + .o_features_2_3(daisy_chain_5_2_3), + .i_features_2_4(daisy_chain_4_2_4), + .o_features_2_4(daisy_chain_5_2_4), + .i_features_2_5(daisy_chain_4_2_5), + .o_features_2_5(daisy_chain_5_2_5), + .i_features_3_0(daisy_chain_4_3_0), + .o_features_3_0(daisy_chain_5_3_0), + .i_features_3_1(daisy_chain_4_3_1), + .o_features_3_1(daisy_chain_5_3_1), + .i_features_3_2(daisy_chain_4_3_2), + .o_features_3_2(daisy_chain_5_3_2), + .i_features_3_3(daisy_chain_4_3_3), + .o_features_3_3(daisy_chain_5_3_3), + .i_features_3_4(daisy_chain_4_3_4), + .o_features_3_4(daisy_chain_5_3_4), + .i_features_3_5(daisy_chain_4_3_5), + .o_features_3_5(daisy_chain_5_3_5), + .o_result_0(PE_output_5_0), + .o_result_1(PE_output_5_1), + .o_result_2(PE_output_5_2), + .o_result_3(PE_output_5_3), + .o_result_4(PE_output_5_4), + .o_result_5(PE_output_5_5), + .o_valid(PE_valid_5), + .o_next_reset(PE_next_reset_5), + .o_next_valid(PE_next_valid_5) +); + +processing_element processing_element_inst_6 ( + .clk(clk), + .i_reset(PE_next_reset_5), + .i_valid(PE_next_valid_5), + .i_features_0_0(daisy_chain_5_0_0), + .o_features_0_0(daisy_chain_6_0_0), + .i_features_0_1(daisy_chain_5_0_1), + .o_features_0_1(daisy_chain_6_0_1), + .i_features_0_2(daisy_chain_5_0_2), + .o_features_0_2(daisy_chain_6_0_2), + .i_features_0_3(daisy_chain_5_0_3), + .o_features_0_3(daisy_chain_6_0_3), + .i_features_0_4(daisy_chain_5_0_4), + .o_features_0_4(daisy_chain_6_0_4), + .i_features_0_5(daisy_chain_5_0_5), + .o_features_0_5(daisy_chain_6_0_5), + .i_features_1_0(daisy_chain_5_1_0), + .o_features_1_0(daisy_chain_6_1_0), + .i_features_1_1(daisy_chain_5_1_1), + .o_features_1_1(daisy_chain_6_1_1), + .i_features_1_2(daisy_chain_5_1_2), + .o_features_1_2(daisy_chain_6_1_2), + .i_features_1_3(daisy_chain_5_1_3), + .o_features_1_3(daisy_chain_6_1_3), + .i_features_1_4(daisy_chain_5_1_4), + .o_features_1_4(daisy_chain_6_1_4), + .i_features_1_5(daisy_chain_5_1_5), + .o_features_1_5(daisy_chain_6_1_5), + .i_features_2_0(daisy_chain_5_2_0), + .o_features_2_0(daisy_chain_6_2_0), + .i_features_2_1(daisy_chain_5_2_1), + .o_features_2_1(daisy_chain_6_2_1), + .i_features_2_2(daisy_chain_5_2_2), + .o_features_2_2(daisy_chain_6_2_2), + .i_features_2_3(daisy_chain_5_2_3), + .o_features_2_3(daisy_chain_6_2_3), + .i_features_2_4(daisy_chain_5_2_4), + .o_features_2_4(daisy_chain_6_2_4), + .i_features_2_5(daisy_chain_5_2_5), + .o_features_2_5(daisy_chain_6_2_5), + .i_features_3_0(daisy_chain_5_3_0), + .o_features_3_0(daisy_chain_6_3_0), + .i_features_3_1(daisy_chain_5_3_1), + .o_features_3_1(daisy_chain_6_3_1), + .i_features_3_2(daisy_chain_5_3_2), + .o_features_3_2(daisy_chain_6_3_2), + .i_features_3_3(daisy_chain_5_3_3), + .o_features_3_3(daisy_chain_6_3_3), + .i_features_3_4(daisy_chain_5_3_4), + .o_features_3_4(daisy_chain_6_3_4), + .i_features_3_5(daisy_chain_5_3_5), + .o_features_3_5(daisy_chain_6_3_5), + .o_result_0(PE_output_6_0), + .o_result_1(PE_output_6_1), + .o_result_2(PE_output_6_2), + .o_result_3(PE_output_6_3), + .o_result_4(PE_output_6_4), + .o_result_5(PE_output_6_5), + .o_valid(PE_valid_6), + .o_next_reset(PE_next_reset_6), + .o_next_valid(PE_next_valid_6) +); + +processing_element processing_element_inst_7 ( + .clk(clk), + .i_reset(PE_next_reset_6), + .i_valid(PE_next_valid_6), + .i_features_0_0(daisy_chain_6_0_0), + .o_features_0_0(daisy_chain_7_0_0), + .i_features_0_1(daisy_chain_6_0_1), + .o_features_0_1(daisy_chain_7_0_1), + .i_features_0_2(daisy_chain_6_0_2), + .o_features_0_2(daisy_chain_7_0_2), + .i_features_0_3(daisy_chain_6_0_3), + .o_features_0_3(daisy_chain_7_0_3), + .i_features_0_4(daisy_chain_6_0_4), + .o_features_0_4(daisy_chain_7_0_4), + .i_features_0_5(daisy_chain_6_0_5), + .o_features_0_5(daisy_chain_7_0_5), + .i_features_1_0(daisy_chain_6_1_0), + .o_features_1_0(daisy_chain_7_1_0), + .i_features_1_1(daisy_chain_6_1_1), + .o_features_1_1(daisy_chain_7_1_1), + .i_features_1_2(daisy_chain_6_1_2), + .o_features_1_2(daisy_chain_7_1_2), + .i_features_1_3(daisy_chain_6_1_3), + .o_features_1_3(daisy_chain_7_1_3), + .i_features_1_4(daisy_chain_6_1_4), + .o_features_1_4(daisy_chain_7_1_4), + .i_features_1_5(daisy_chain_6_1_5), + .o_features_1_5(daisy_chain_7_1_5), + .i_features_2_0(daisy_chain_6_2_0), + .o_features_2_0(daisy_chain_7_2_0), + .i_features_2_1(daisy_chain_6_2_1), + .o_features_2_1(daisy_chain_7_2_1), + .i_features_2_2(daisy_chain_6_2_2), + .o_features_2_2(daisy_chain_7_2_2), + .i_features_2_3(daisy_chain_6_2_3), + .o_features_2_3(daisy_chain_7_2_3), + .i_features_2_4(daisy_chain_6_2_4), + .o_features_2_4(daisy_chain_7_2_4), + .i_features_2_5(daisy_chain_6_2_5), + .o_features_2_5(daisy_chain_7_2_5), + .i_features_3_0(daisy_chain_6_3_0), + .o_features_3_0(daisy_chain_7_3_0), + .i_features_3_1(daisy_chain_6_3_1), + .o_features_3_1(daisy_chain_7_3_1), + .i_features_3_2(daisy_chain_6_3_2), + .o_features_3_2(daisy_chain_7_3_2), + .i_features_3_3(daisy_chain_6_3_3), + .o_features_3_3(daisy_chain_7_3_3), + .i_features_3_4(daisy_chain_6_3_4), + .o_features_3_4(daisy_chain_7_3_4), + .i_features_3_5(daisy_chain_6_3_5), + .o_features_3_5(daisy_chain_7_3_5), + .o_result_0(PE_output_7_0), + .o_result_1(PE_output_7_1), + .o_result_2(PE_output_7_2), + .o_result_3(PE_output_7_3), + .o_result_4(PE_output_7_4), + .o_result_5(PE_output_7_5), + .o_valid(PE_valid_7), + .o_next_reset(PE_next_reset_7), + .o_next_valid(PE_next_valid_7) +); + +processing_element processing_element_inst_8 ( + .clk(clk), + .i_reset(PE_next_reset_7), + .i_valid(PE_next_valid_7), + .i_features_0_0(daisy_chain_7_0_0), + .o_features_0_0(daisy_chain_8_0_0), + .i_features_0_1(daisy_chain_7_0_1), + .o_features_0_1(daisy_chain_8_0_1), + .i_features_0_2(daisy_chain_7_0_2), + .o_features_0_2(daisy_chain_8_0_2), + .i_features_0_3(daisy_chain_7_0_3), + .o_features_0_3(daisy_chain_8_0_3), + .i_features_0_4(daisy_chain_7_0_4), + .o_features_0_4(daisy_chain_8_0_4), + .i_features_0_5(daisy_chain_7_0_5), + .o_features_0_5(daisy_chain_8_0_5), + .i_features_1_0(daisy_chain_7_1_0), + .o_features_1_0(daisy_chain_8_1_0), + .i_features_1_1(daisy_chain_7_1_1), + .o_features_1_1(daisy_chain_8_1_1), + .i_features_1_2(daisy_chain_7_1_2), + .o_features_1_2(daisy_chain_8_1_2), + .i_features_1_3(daisy_chain_7_1_3), + .o_features_1_3(daisy_chain_8_1_3), + .i_features_1_4(daisy_chain_7_1_4), + .o_features_1_4(daisy_chain_8_1_4), + .i_features_1_5(daisy_chain_7_1_5), + .o_features_1_5(daisy_chain_8_1_5), + .i_features_2_0(daisy_chain_7_2_0), + .o_features_2_0(daisy_chain_8_2_0), + .i_features_2_1(daisy_chain_7_2_1), + .o_features_2_1(daisy_chain_8_2_1), + .i_features_2_2(daisy_chain_7_2_2), + .o_features_2_2(daisy_chain_8_2_2), + .i_features_2_3(daisy_chain_7_2_3), + .o_features_2_3(daisy_chain_8_2_3), + .i_features_2_4(daisy_chain_7_2_4), + .o_features_2_4(daisy_chain_8_2_4), + .i_features_2_5(daisy_chain_7_2_5), + .o_features_2_5(daisy_chain_8_2_5), + .i_features_3_0(daisy_chain_7_3_0), + .o_features_3_0(daisy_chain_8_3_0), + .i_features_3_1(daisy_chain_7_3_1), + .o_features_3_1(daisy_chain_8_3_1), + .i_features_3_2(daisy_chain_7_3_2), + .o_features_3_2(daisy_chain_8_3_2), + .i_features_3_3(daisy_chain_7_3_3), + .o_features_3_3(daisy_chain_8_3_3), + .i_features_3_4(daisy_chain_7_3_4), + .o_features_3_4(daisy_chain_8_3_4), + .i_features_3_5(daisy_chain_7_3_5), + .o_features_3_5(daisy_chain_8_3_5), + .o_result_0(PE_output_8_0), + .o_result_1(PE_output_8_1), + .o_result_2(PE_output_8_2), + .o_result_3(PE_output_8_3), + .o_result_4(PE_output_8_4), + .o_result_5(PE_output_8_5), + .o_valid(PE_valid_8), + .o_next_reset(PE_next_reset_8), + .o_next_valid(PE_next_valid_8) +); + +processing_element processing_element_inst_9 ( + .clk(clk), + .i_reset(PE_next_reset_8), + .i_valid(PE_next_valid_8), + .i_features_0_0(daisy_chain_8_0_0), + .o_features_0_0(daisy_chain_9_0_0), + .i_features_0_1(daisy_chain_8_0_1), + .o_features_0_1(daisy_chain_9_0_1), + .i_features_0_2(daisy_chain_8_0_2), + .o_features_0_2(daisy_chain_9_0_2), + .i_features_0_3(daisy_chain_8_0_3), + .o_features_0_3(daisy_chain_9_0_3), + .i_features_0_4(daisy_chain_8_0_4), + .o_features_0_4(daisy_chain_9_0_4), + .i_features_0_5(daisy_chain_8_0_5), + .o_features_0_5(daisy_chain_9_0_5), + .i_features_1_0(daisy_chain_8_1_0), + .o_features_1_0(daisy_chain_9_1_0), + .i_features_1_1(daisy_chain_8_1_1), + .o_features_1_1(daisy_chain_9_1_1), + .i_features_1_2(daisy_chain_8_1_2), + .o_features_1_2(daisy_chain_9_1_2), + .i_features_1_3(daisy_chain_8_1_3), + .o_features_1_3(daisy_chain_9_1_3), + .i_features_1_4(daisy_chain_8_1_4), + .o_features_1_4(daisy_chain_9_1_4), + .i_features_1_5(daisy_chain_8_1_5), + .o_features_1_5(daisy_chain_9_1_5), + .i_features_2_0(daisy_chain_8_2_0), + .o_features_2_0(daisy_chain_9_2_0), + .i_features_2_1(daisy_chain_8_2_1), + .o_features_2_1(daisy_chain_9_2_1), + .i_features_2_2(daisy_chain_8_2_2), + .o_features_2_2(daisy_chain_9_2_2), + .i_features_2_3(daisy_chain_8_2_3), + .o_features_2_3(daisy_chain_9_2_3), + .i_features_2_4(daisy_chain_8_2_4), + .o_features_2_4(daisy_chain_9_2_4), + .i_features_2_5(daisy_chain_8_2_5), + .o_features_2_5(daisy_chain_9_2_5), + .i_features_3_0(daisy_chain_8_3_0), + .o_features_3_0(daisy_chain_9_3_0), + .i_features_3_1(daisy_chain_8_3_1), + .o_features_3_1(daisy_chain_9_3_1), + .i_features_3_2(daisy_chain_8_3_2), + .o_features_3_2(daisy_chain_9_3_2), + .i_features_3_3(daisy_chain_8_3_3), + .o_features_3_3(daisy_chain_9_3_3), + .i_features_3_4(daisy_chain_8_3_4), + .o_features_3_4(daisy_chain_9_3_4), + .i_features_3_5(daisy_chain_8_3_5), + .o_features_3_5(daisy_chain_9_3_5), + .o_result_0(PE_output_9_0), + .o_result_1(PE_output_9_1), + .o_result_2(PE_output_9_2), + .o_result_3(PE_output_9_3), + .o_result_4(PE_output_9_4), + .o_result_5(PE_output_9_5), + .o_valid(PE_valid_9), + .o_next_reset(PE_next_reset_9), + .o_next_valid(PE_next_valid_9) +); + +processing_element processing_element_inst_10 ( + .clk(clk), + .i_reset(PE_next_reset_9), + .i_valid(PE_next_valid_9), + .i_features_0_0(daisy_chain_9_0_0), + .o_features_0_0(daisy_chain_10_0_0), + .i_features_0_1(daisy_chain_9_0_1), + .o_features_0_1(daisy_chain_10_0_1), + .i_features_0_2(daisy_chain_9_0_2), + .o_features_0_2(daisy_chain_10_0_2), + .i_features_0_3(daisy_chain_9_0_3), + .o_features_0_3(daisy_chain_10_0_3), + .i_features_0_4(daisy_chain_9_0_4), + .o_features_0_4(daisy_chain_10_0_4), + .i_features_0_5(daisy_chain_9_0_5), + .o_features_0_5(daisy_chain_10_0_5), + .i_features_1_0(daisy_chain_9_1_0), + .o_features_1_0(daisy_chain_10_1_0), + .i_features_1_1(daisy_chain_9_1_1), + .o_features_1_1(daisy_chain_10_1_1), + .i_features_1_2(daisy_chain_9_1_2), + .o_features_1_2(daisy_chain_10_1_2), + .i_features_1_3(daisy_chain_9_1_3), + .o_features_1_3(daisy_chain_10_1_3), + .i_features_1_4(daisy_chain_9_1_4), + .o_features_1_4(daisy_chain_10_1_4), + .i_features_1_5(daisy_chain_9_1_5), + .o_features_1_5(daisy_chain_10_1_5), + .i_features_2_0(daisy_chain_9_2_0), + .o_features_2_0(daisy_chain_10_2_0), + .i_features_2_1(daisy_chain_9_2_1), + .o_features_2_1(daisy_chain_10_2_1), + .i_features_2_2(daisy_chain_9_2_2), + .o_features_2_2(daisy_chain_10_2_2), + .i_features_2_3(daisy_chain_9_2_3), + .o_features_2_3(daisy_chain_10_2_3), + .i_features_2_4(daisy_chain_9_2_4), + .o_features_2_4(daisy_chain_10_2_4), + .i_features_2_5(daisy_chain_9_2_5), + .o_features_2_5(daisy_chain_10_2_5), + .i_features_3_0(daisy_chain_9_3_0), + .o_features_3_0(daisy_chain_10_3_0), + .i_features_3_1(daisy_chain_9_3_1), + .o_features_3_1(daisy_chain_10_3_1), + .i_features_3_2(daisy_chain_9_3_2), + .o_features_3_2(daisy_chain_10_3_2), + .i_features_3_3(daisy_chain_9_3_3), + .o_features_3_3(daisy_chain_10_3_3), + .i_features_3_4(daisy_chain_9_3_4), + .o_features_3_4(daisy_chain_10_3_4), + .i_features_3_5(daisy_chain_9_3_5), + .o_features_3_5(daisy_chain_10_3_5), + .o_result_0(PE_output_10_0), + .o_result_1(PE_output_10_1), + .o_result_2(PE_output_10_2), + .o_result_3(PE_output_10_3), + .o_result_4(PE_output_10_4), + .o_result_5(PE_output_10_5), + .o_valid(PE_valid_10), + .o_next_reset(PE_next_reset_10), + .o_next_valid(PE_next_valid_10) +); + +processing_element processing_element_inst_11 ( + .clk(clk), + .i_reset(PE_next_reset_10), + .i_valid(PE_next_valid_10), + .i_features_0_0(daisy_chain_10_0_0), + .o_features_0_0(daisy_chain_11_0_0), + .i_features_0_1(daisy_chain_10_0_1), + .o_features_0_1(daisy_chain_11_0_1), + .i_features_0_2(daisy_chain_10_0_2), + .o_features_0_2(daisy_chain_11_0_2), + .i_features_0_3(daisy_chain_10_0_3), + .o_features_0_3(daisy_chain_11_0_3), + .i_features_0_4(daisy_chain_10_0_4), + .o_features_0_4(daisy_chain_11_0_4), + .i_features_0_5(daisy_chain_10_0_5), + .o_features_0_5(daisy_chain_11_0_5), + .i_features_1_0(daisy_chain_10_1_0), + .o_features_1_0(daisy_chain_11_1_0), + .i_features_1_1(daisy_chain_10_1_1), + .o_features_1_1(daisy_chain_11_1_1), + .i_features_1_2(daisy_chain_10_1_2), + .o_features_1_2(daisy_chain_11_1_2), + .i_features_1_3(daisy_chain_10_1_3), + .o_features_1_3(daisy_chain_11_1_3), + .i_features_1_4(daisy_chain_10_1_4), + .o_features_1_4(daisy_chain_11_1_4), + .i_features_1_5(daisy_chain_10_1_5), + .o_features_1_5(daisy_chain_11_1_5), + .i_features_2_0(daisy_chain_10_2_0), + .o_features_2_0(daisy_chain_11_2_0), + .i_features_2_1(daisy_chain_10_2_1), + .o_features_2_1(daisy_chain_11_2_1), + .i_features_2_2(daisy_chain_10_2_2), + .o_features_2_2(daisy_chain_11_2_2), + .i_features_2_3(daisy_chain_10_2_3), + .o_features_2_3(daisy_chain_11_2_3), + .i_features_2_4(daisy_chain_10_2_4), + .o_features_2_4(daisy_chain_11_2_4), + .i_features_2_5(daisy_chain_10_2_5), + .o_features_2_5(daisy_chain_11_2_5), + .i_features_3_0(daisy_chain_10_3_0), + .o_features_3_0(daisy_chain_11_3_0), + .i_features_3_1(daisy_chain_10_3_1), + .o_features_3_1(daisy_chain_11_3_1), + .i_features_3_2(daisy_chain_10_3_2), + .o_features_3_2(daisy_chain_11_3_2), + .i_features_3_3(daisy_chain_10_3_3), + .o_features_3_3(daisy_chain_11_3_3), + .i_features_3_4(daisy_chain_10_3_4), + .o_features_3_4(daisy_chain_11_3_4), + .i_features_3_5(daisy_chain_10_3_5), + .o_features_3_5(daisy_chain_11_3_5), + .o_result_0(PE_output_11_0), + .o_result_1(PE_output_11_1), + .o_result_2(PE_output_11_2), + .o_result_3(PE_output_11_3), + .o_result_4(PE_output_11_4), + .o_result_5(PE_output_11_5), + .o_valid(PE_valid_11), + .o_next_reset(PE_next_reset_11), + .o_next_valid(PE_next_valid_11) +); + +processing_element processing_element_inst_12 ( + .clk(clk), + .i_reset(PE_next_reset_11), + .i_valid(PE_next_valid_11), + .i_features_0_0(daisy_chain_11_0_0), + .o_features_0_0(daisy_chain_12_0_0), + .i_features_0_1(daisy_chain_11_0_1), + .o_features_0_1(daisy_chain_12_0_1), + .i_features_0_2(daisy_chain_11_0_2), + .o_features_0_2(daisy_chain_12_0_2), + .i_features_0_3(daisy_chain_11_0_3), + .o_features_0_3(daisy_chain_12_0_3), + .i_features_0_4(daisy_chain_11_0_4), + .o_features_0_4(daisy_chain_12_0_4), + .i_features_0_5(daisy_chain_11_0_5), + .o_features_0_5(daisy_chain_12_0_5), + .i_features_1_0(daisy_chain_11_1_0), + .o_features_1_0(daisy_chain_12_1_0), + .i_features_1_1(daisy_chain_11_1_1), + .o_features_1_1(daisy_chain_12_1_1), + .i_features_1_2(daisy_chain_11_1_2), + .o_features_1_2(daisy_chain_12_1_2), + .i_features_1_3(daisy_chain_11_1_3), + .o_features_1_3(daisy_chain_12_1_3), + .i_features_1_4(daisy_chain_11_1_4), + .o_features_1_4(daisy_chain_12_1_4), + .i_features_1_5(daisy_chain_11_1_5), + .o_features_1_5(daisy_chain_12_1_5), + .i_features_2_0(daisy_chain_11_2_0), + .o_features_2_0(daisy_chain_12_2_0), + .i_features_2_1(daisy_chain_11_2_1), + .o_features_2_1(daisy_chain_12_2_1), + .i_features_2_2(daisy_chain_11_2_2), + .o_features_2_2(daisy_chain_12_2_2), + .i_features_2_3(daisy_chain_11_2_3), + .o_features_2_3(daisy_chain_12_2_3), + .i_features_2_4(daisy_chain_11_2_4), + .o_features_2_4(daisy_chain_12_2_4), + .i_features_2_5(daisy_chain_11_2_5), + .o_features_2_5(daisy_chain_12_2_5), + .i_features_3_0(daisy_chain_11_3_0), + .o_features_3_0(daisy_chain_12_3_0), + .i_features_3_1(daisy_chain_11_3_1), + .o_features_3_1(daisy_chain_12_3_1), + .i_features_3_2(daisy_chain_11_3_2), + .o_features_3_2(daisy_chain_12_3_2), + .i_features_3_3(daisy_chain_11_3_3), + .o_features_3_3(daisy_chain_12_3_3), + .i_features_3_4(daisy_chain_11_3_4), + .o_features_3_4(daisy_chain_12_3_4), + .i_features_3_5(daisy_chain_11_3_5), + .o_features_3_5(daisy_chain_12_3_5), + .o_result_0(PE_output_12_0), + .o_result_1(PE_output_12_1), + .o_result_2(PE_output_12_2), + .o_result_3(PE_output_12_3), + .o_result_4(PE_output_12_4), + .o_result_5(PE_output_12_5), + .o_valid(PE_valid_12), + .o_next_reset(PE_next_reset_12), + .o_next_valid(PE_next_valid_12) +); + +processing_element processing_element_inst_13 ( + .clk(clk), + .i_reset(PE_next_reset_12), + .i_valid(PE_next_valid_12), + .i_features_0_0(daisy_chain_12_0_0), + .o_features_0_0(daisy_chain_13_0_0), + .i_features_0_1(daisy_chain_12_0_1), + .o_features_0_1(daisy_chain_13_0_1), + .i_features_0_2(daisy_chain_12_0_2), + .o_features_0_2(daisy_chain_13_0_2), + .i_features_0_3(daisy_chain_12_0_3), + .o_features_0_3(daisy_chain_13_0_3), + .i_features_0_4(daisy_chain_12_0_4), + .o_features_0_4(daisy_chain_13_0_4), + .i_features_0_5(daisy_chain_12_0_5), + .o_features_0_5(daisy_chain_13_0_5), + .i_features_1_0(daisy_chain_12_1_0), + .o_features_1_0(daisy_chain_13_1_0), + .i_features_1_1(daisy_chain_12_1_1), + .o_features_1_1(daisy_chain_13_1_1), + .i_features_1_2(daisy_chain_12_1_2), + .o_features_1_2(daisy_chain_13_1_2), + .i_features_1_3(daisy_chain_12_1_3), + .o_features_1_3(daisy_chain_13_1_3), + .i_features_1_4(daisy_chain_12_1_4), + .o_features_1_4(daisy_chain_13_1_4), + .i_features_1_5(daisy_chain_12_1_5), + .o_features_1_5(daisy_chain_13_1_5), + .i_features_2_0(daisy_chain_12_2_0), + .o_features_2_0(daisy_chain_13_2_0), + .i_features_2_1(daisy_chain_12_2_1), + .o_features_2_1(daisy_chain_13_2_1), + .i_features_2_2(daisy_chain_12_2_2), + .o_features_2_2(daisy_chain_13_2_2), + .i_features_2_3(daisy_chain_12_2_3), + .o_features_2_3(daisy_chain_13_2_3), + .i_features_2_4(daisy_chain_12_2_4), + .o_features_2_4(daisy_chain_13_2_4), + .i_features_2_5(daisy_chain_12_2_5), + .o_features_2_5(daisy_chain_13_2_5), + .i_features_3_0(daisy_chain_12_3_0), + .o_features_3_0(daisy_chain_13_3_0), + .i_features_3_1(daisy_chain_12_3_1), + .o_features_3_1(daisy_chain_13_3_1), + .i_features_3_2(daisy_chain_12_3_2), + .o_features_3_2(daisy_chain_13_3_2), + .i_features_3_3(daisy_chain_12_3_3), + .o_features_3_3(daisy_chain_13_3_3), + .i_features_3_4(daisy_chain_12_3_4), + .o_features_3_4(daisy_chain_13_3_4), + .i_features_3_5(daisy_chain_12_3_5), + .o_features_3_5(daisy_chain_13_3_5), + .o_result_0(PE_output_13_0), + .o_result_1(PE_output_13_1), + .o_result_2(PE_output_13_2), + .o_result_3(PE_output_13_3), + .o_result_4(PE_output_13_4), + .o_result_5(PE_output_13_5), + .o_valid(PE_valid_13), + .o_next_reset(PE_next_reset_13), + .o_next_valid(PE_next_valid_13) +); + +processing_element processing_element_inst_14 ( + .clk(clk), + .i_reset(PE_next_reset_13), + .i_valid(PE_next_valid_13), + .i_features_0_0(daisy_chain_13_0_0), + .o_features_0_0(daisy_chain_14_0_0), + .i_features_0_1(daisy_chain_13_0_1), + .o_features_0_1(daisy_chain_14_0_1), + .i_features_0_2(daisy_chain_13_0_2), + .o_features_0_2(daisy_chain_14_0_2), + .i_features_0_3(daisy_chain_13_0_3), + .o_features_0_3(daisy_chain_14_0_3), + .i_features_0_4(daisy_chain_13_0_4), + .o_features_0_4(daisy_chain_14_0_4), + .i_features_0_5(daisy_chain_13_0_5), + .o_features_0_5(daisy_chain_14_0_5), + .i_features_1_0(daisy_chain_13_1_0), + .o_features_1_0(daisy_chain_14_1_0), + .i_features_1_1(daisy_chain_13_1_1), + .o_features_1_1(daisy_chain_14_1_1), + .i_features_1_2(daisy_chain_13_1_2), + .o_features_1_2(daisy_chain_14_1_2), + .i_features_1_3(daisy_chain_13_1_3), + .o_features_1_3(daisy_chain_14_1_3), + .i_features_1_4(daisy_chain_13_1_4), + .o_features_1_4(daisy_chain_14_1_4), + .i_features_1_5(daisy_chain_13_1_5), + .o_features_1_5(daisy_chain_14_1_5), + .i_features_2_0(daisy_chain_13_2_0), + .o_features_2_0(daisy_chain_14_2_0), + .i_features_2_1(daisy_chain_13_2_1), + .o_features_2_1(daisy_chain_14_2_1), + .i_features_2_2(daisy_chain_13_2_2), + .o_features_2_2(daisy_chain_14_2_2), + .i_features_2_3(daisy_chain_13_2_3), + .o_features_2_3(daisy_chain_14_2_3), + .i_features_2_4(daisy_chain_13_2_4), + .o_features_2_4(daisy_chain_14_2_4), + .i_features_2_5(daisy_chain_13_2_5), + .o_features_2_5(daisy_chain_14_2_5), + .i_features_3_0(daisy_chain_13_3_0), + .o_features_3_0(daisy_chain_14_3_0), + .i_features_3_1(daisy_chain_13_3_1), + .o_features_3_1(daisy_chain_14_3_1), + .i_features_3_2(daisy_chain_13_3_2), + .o_features_3_2(daisy_chain_14_3_2), + .i_features_3_3(daisy_chain_13_3_3), + .o_features_3_3(daisy_chain_14_3_3), + .i_features_3_4(daisy_chain_13_3_4), + .o_features_3_4(daisy_chain_14_3_4), + .i_features_3_5(daisy_chain_13_3_5), + .o_features_3_5(daisy_chain_14_3_5), + .o_result_0(PE_output_14_0), + .o_result_1(PE_output_14_1), + .o_result_2(PE_output_14_2), + .o_result_3(PE_output_14_3), + .o_result_4(PE_output_14_4), + .o_result_5(PE_output_14_5), + .o_valid(PE_valid_14), + .o_next_reset(PE_next_reset_14), + .o_next_valid(PE_next_valid_14) +); + +processing_element processing_element_inst_15 ( + .clk(clk), + .i_reset(PE_next_reset_14), + .i_valid(PE_next_valid_14), + .i_features_0_0(daisy_chain_14_0_0), + .o_features_0_0(daisy_chain_15_0_0), + .i_features_0_1(daisy_chain_14_0_1), + .o_features_0_1(daisy_chain_15_0_1), + .i_features_0_2(daisy_chain_14_0_2), + .o_features_0_2(daisy_chain_15_0_2), + .i_features_0_3(daisy_chain_14_0_3), + .o_features_0_3(daisy_chain_15_0_3), + .i_features_0_4(daisy_chain_14_0_4), + .o_features_0_4(daisy_chain_15_0_4), + .i_features_0_5(daisy_chain_14_0_5), + .o_features_0_5(daisy_chain_15_0_5), + .i_features_1_0(daisy_chain_14_1_0), + .o_features_1_0(daisy_chain_15_1_0), + .i_features_1_1(daisy_chain_14_1_1), + .o_features_1_1(daisy_chain_15_1_1), + .i_features_1_2(daisy_chain_14_1_2), + .o_features_1_2(daisy_chain_15_1_2), + .i_features_1_3(daisy_chain_14_1_3), + .o_features_1_3(daisy_chain_15_1_3), + .i_features_1_4(daisy_chain_14_1_4), + .o_features_1_4(daisy_chain_15_1_4), + .i_features_1_5(daisy_chain_14_1_5), + .o_features_1_5(daisy_chain_15_1_5), + .i_features_2_0(daisy_chain_14_2_0), + .o_features_2_0(daisy_chain_15_2_0), + .i_features_2_1(daisy_chain_14_2_1), + .o_features_2_1(daisy_chain_15_2_1), + .i_features_2_2(daisy_chain_14_2_2), + .o_features_2_2(daisy_chain_15_2_2), + .i_features_2_3(daisy_chain_14_2_3), + .o_features_2_3(daisy_chain_15_2_3), + .i_features_2_4(daisy_chain_14_2_4), + .o_features_2_4(daisy_chain_15_2_4), + .i_features_2_5(daisy_chain_14_2_5), + .o_features_2_5(daisy_chain_15_2_5), + .i_features_3_0(daisy_chain_14_3_0), + .o_features_3_0(daisy_chain_15_3_0), + .i_features_3_1(daisy_chain_14_3_1), + .o_features_3_1(daisy_chain_15_3_1), + .i_features_3_2(daisy_chain_14_3_2), + .o_features_3_2(daisy_chain_15_3_2), + .i_features_3_3(daisy_chain_14_3_3), + .o_features_3_3(daisy_chain_15_3_3), + .i_features_3_4(daisy_chain_14_3_4), + .o_features_3_4(daisy_chain_15_3_4), + .i_features_3_5(daisy_chain_14_3_5), + .o_features_3_5(daisy_chain_15_3_5), + .o_result_0(PE_output_15_0), + .o_result_1(PE_output_15_1), + .o_result_2(PE_output_15_2), + .o_result_3(PE_output_15_3), + .o_result_4(PE_output_15_4), + .o_result_5(PE_output_15_5), + .o_valid(PE_valid_15), + .o_next_reset(PE_next_reset_15), + .o_next_valid(PE_next_valid_15) +); + +processing_element processing_element_inst_16 ( + .clk(clk), + .i_reset(PE_next_reset_15), + .i_valid(PE_next_valid_15), + .i_features_0_0(daisy_chain_15_0_0), + .o_features_0_0(daisy_chain_16_0_0), + .i_features_0_1(daisy_chain_15_0_1), + .o_features_0_1(daisy_chain_16_0_1), + .i_features_0_2(daisy_chain_15_0_2), + .o_features_0_2(daisy_chain_16_0_2), + .i_features_0_3(daisy_chain_15_0_3), + .o_features_0_3(daisy_chain_16_0_3), + .i_features_0_4(daisy_chain_15_0_4), + .o_features_0_4(daisy_chain_16_0_4), + .i_features_0_5(daisy_chain_15_0_5), + .o_features_0_5(daisy_chain_16_0_5), + .i_features_1_0(daisy_chain_15_1_0), + .o_features_1_0(daisy_chain_16_1_0), + .i_features_1_1(daisy_chain_15_1_1), + .o_features_1_1(daisy_chain_16_1_1), + .i_features_1_2(daisy_chain_15_1_2), + .o_features_1_2(daisy_chain_16_1_2), + .i_features_1_3(daisy_chain_15_1_3), + .o_features_1_3(daisy_chain_16_1_3), + .i_features_1_4(daisy_chain_15_1_4), + .o_features_1_4(daisy_chain_16_1_4), + .i_features_1_5(daisy_chain_15_1_5), + .o_features_1_5(daisy_chain_16_1_5), + .i_features_2_0(daisy_chain_15_2_0), + .o_features_2_0(daisy_chain_16_2_0), + .i_features_2_1(daisy_chain_15_2_1), + .o_features_2_1(daisy_chain_16_2_1), + .i_features_2_2(daisy_chain_15_2_2), + .o_features_2_2(daisy_chain_16_2_2), + .i_features_2_3(daisy_chain_15_2_3), + .o_features_2_3(daisy_chain_16_2_3), + .i_features_2_4(daisy_chain_15_2_4), + .o_features_2_4(daisy_chain_16_2_4), + .i_features_2_5(daisy_chain_15_2_5), + .o_features_2_5(daisy_chain_16_2_5), + .i_features_3_0(daisy_chain_15_3_0), + .o_features_3_0(daisy_chain_16_3_0), + .i_features_3_1(daisy_chain_15_3_1), + .o_features_3_1(daisy_chain_16_3_1), + .i_features_3_2(daisy_chain_15_3_2), + .o_features_3_2(daisy_chain_16_3_2), + .i_features_3_3(daisy_chain_15_3_3), + .o_features_3_3(daisy_chain_16_3_3), + .i_features_3_4(daisy_chain_15_3_4), + .o_features_3_4(daisy_chain_16_3_4), + .i_features_3_5(daisy_chain_15_3_5), + .o_features_3_5(daisy_chain_16_3_5), + .o_result_0(PE_output_16_0), + .o_result_1(PE_output_16_1), + .o_result_2(PE_output_16_2), + .o_result_3(PE_output_16_3), + .o_result_4(PE_output_16_4), + .o_result_5(PE_output_16_5), + .o_valid(PE_valid_16), + .o_next_reset(PE_next_reset_16), + .o_next_valid(PE_next_valid_16) +); + +processing_element processing_element_inst_17 ( + .clk(clk), + .i_reset(PE_next_reset_16), + .i_valid(PE_next_valid_16), + .i_features_0_0(daisy_chain_16_0_0), + .o_features_0_0(daisy_chain_17_0_0), + .i_features_0_1(daisy_chain_16_0_1), + .o_features_0_1(daisy_chain_17_0_1), + .i_features_0_2(daisy_chain_16_0_2), + .o_features_0_2(daisy_chain_17_0_2), + .i_features_0_3(daisy_chain_16_0_3), + .o_features_0_3(daisy_chain_17_0_3), + .i_features_0_4(daisy_chain_16_0_4), + .o_features_0_4(daisy_chain_17_0_4), + .i_features_0_5(daisy_chain_16_0_5), + .o_features_0_5(daisy_chain_17_0_5), + .i_features_1_0(daisy_chain_16_1_0), + .o_features_1_0(daisy_chain_17_1_0), + .i_features_1_1(daisy_chain_16_1_1), + .o_features_1_1(daisy_chain_17_1_1), + .i_features_1_2(daisy_chain_16_1_2), + .o_features_1_2(daisy_chain_17_1_2), + .i_features_1_3(daisy_chain_16_1_3), + .o_features_1_3(daisy_chain_17_1_3), + .i_features_1_4(daisy_chain_16_1_4), + .o_features_1_4(daisy_chain_17_1_4), + .i_features_1_5(daisy_chain_16_1_5), + .o_features_1_5(daisy_chain_17_1_5), + .i_features_2_0(daisy_chain_16_2_0), + .o_features_2_0(daisy_chain_17_2_0), + .i_features_2_1(daisy_chain_16_2_1), + .o_features_2_1(daisy_chain_17_2_1), + .i_features_2_2(daisy_chain_16_2_2), + .o_features_2_2(daisy_chain_17_2_2), + .i_features_2_3(daisy_chain_16_2_3), + .o_features_2_3(daisy_chain_17_2_3), + .i_features_2_4(daisy_chain_16_2_4), + .o_features_2_4(daisy_chain_17_2_4), + .i_features_2_5(daisy_chain_16_2_5), + .o_features_2_5(daisy_chain_17_2_5), + .i_features_3_0(daisy_chain_16_3_0), + .o_features_3_0(daisy_chain_17_3_0), + .i_features_3_1(daisy_chain_16_3_1), + .o_features_3_1(daisy_chain_17_3_1), + .i_features_3_2(daisy_chain_16_3_2), + .o_features_3_2(daisy_chain_17_3_2), + .i_features_3_3(daisy_chain_16_3_3), + .o_features_3_3(daisy_chain_17_3_3), + .i_features_3_4(daisy_chain_16_3_4), + .o_features_3_4(daisy_chain_17_3_4), + .i_features_3_5(daisy_chain_16_3_5), + .o_features_3_5(daisy_chain_17_3_5), + .o_result_0(PE_output_17_0), + .o_result_1(PE_output_17_1), + .o_result_2(PE_output_17_2), + .o_result_3(PE_output_17_3), + .o_result_4(PE_output_17_4), + .o_result_5(PE_output_17_5), + .o_valid(PE_valid_17), + .o_next_reset(PE_next_reset_17), + .o_next_valid(PE_next_valid_17) +); + +processing_element processing_element_inst_18 ( + .clk(clk), + .i_reset(PE_next_reset_17), + .i_valid(PE_next_valid_17), + .i_features_0_0(daisy_chain_17_0_0), + .o_features_0_0(daisy_chain_18_0_0), + .i_features_0_1(daisy_chain_17_0_1), + .o_features_0_1(daisy_chain_18_0_1), + .i_features_0_2(daisy_chain_17_0_2), + .o_features_0_2(daisy_chain_18_0_2), + .i_features_0_3(daisy_chain_17_0_3), + .o_features_0_3(daisy_chain_18_0_3), + .i_features_0_4(daisy_chain_17_0_4), + .o_features_0_4(daisy_chain_18_0_4), + .i_features_0_5(daisy_chain_17_0_5), + .o_features_0_5(daisy_chain_18_0_5), + .i_features_1_0(daisy_chain_17_1_0), + .o_features_1_0(daisy_chain_18_1_0), + .i_features_1_1(daisy_chain_17_1_1), + .o_features_1_1(daisy_chain_18_1_1), + .i_features_1_2(daisy_chain_17_1_2), + .o_features_1_2(daisy_chain_18_1_2), + .i_features_1_3(daisy_chain_17_1_3), + .o_features_1_3(daisy_chain_18_1_3), + .i_features_1_4(daisy_chain_17_1_4), + .o_features_1_4(daisy_chain_18_1_4), + .i_features_1_5(daisy_chain_17_1_5), + .o_features_1_5(daisy_chain_18_1_5), + .i_features_2_0(daisy_chain_17_2_0), + .o_features_2_0(daisy_chain_18_2_0), + .i_features_2_1(daisy_chain_17_2_1), + .o_features_2_1(daisy_chain_18_2_1), + .i_features_2_2(daisy_chain_17_2_2), + .o_features_2_2(daisy_chain_18_2_2), + .i_features_2_3(daisy_chain_17_2_3), + .o_features_2_3(daisy_chain_18_2_3), + .i_features_2_4(daisy_chain_17_2_4), + .o_features_2_4(daisy_chain_18_2_4), + .i_features_2_5(daisy_chain_17_2_5), + .o_features_2_5(daisy_chain_18_2_5), + .i_features_3_0(daisy_chain_17_3_0), + .o_features_3_0(daisy_chain_18_3_0), + .i_features_3_1(daisy_chain_17_3_1), + .o_features_3_1(daisy_chain_18_3_1), + .i_features_3_2(daisy_chain_17_3_2), + .o_features_3_2(daisy_chain_18_3_2), + .i_features_3_3(daisy_chain_17_3_3), + .o_features_3_3(daisy_chain_18_3_3), + .i_features_3_4(daisy_chain_17_3_4), + .o_features_3_4(daisy_chain_18_3_4), + .i_features_3_5(daisy_chain_17_3_5), + .o_features_3_5(daisy_chain_18_3_5), + .o_result_0(PE_output_18_0), + .o_result_1(PE_output_18_1), + .o_result_2(PE_output_18_2), + .o_result_3(PE_output_18_3), + .o_result_4(PE_output_18_4), + .o_result_5(PE_output_18_5), + .o_valid(PE_valid_18), + .o_next_reset(PE_next_reset_18), + .o_next_valid(PE_next_valid_18) +); + +processing_element processing_element_inst_19 ( + .clk(clk), + .i_reset(PE_next_reset_18), + .i_valid(PE_next_valid_18), + .i_features_0_0(daisy_chain_18_0_0), + .o_features_0_0(daisy_chain_19_0_0), + .i_features_0_1(daisy_chain_18_0_1), + .o_features_0_1(daisy_chain_19_0_1), + .i_features_0_2(daisy_chain_18_0_2), + .o_features_0_2(daisy_chain_19_0_2), + .i_features_0_3(daisy_chain_18_0_3), + .o_features_0_3(daisy_chain_19_0_3), + .i_features_0_4(daisy_chain_18_0_4), + .o_features_0_4(daisy_chain_19_0_4), + .i_features_0_5(daisy_chain_18_0_5), + .o_features_0_5(daisy_chain_19_0_5), + .i_features_1_0(daisy_chain_18_1_0), + .o_features_1_0(daisy_chain_19_1_0), + .i_features_1_1(daisy_chain_18_1_1), + .o_features_1_1(daisy_chain_19_1_1), + .i_features_1_2(daisy_chain_18_1_2), + .o_features_1_2(daisy_chain_19_1_2), + .i_features_1_3(daisy_chain_18_1_3), + .o_features_1_3(daisy_chain_19_1_3), + .i_features_1_4(daisy_chain_18_1_4), + .o_features_1_4(daisy_chain_19_1_4), + .i_features_1_5(daisy_chain_18_1_5), + .o_features_1_5(daisy_chain_19_1_5), + .i_features_2_0(daisy_chain_18_2_0), + .o_features_2_0(daisy_chain_19_2_0), + .i_features_2_1(daisy_chain_18_2_1), + .o_features_2_1(daisy_chain_19_2_1), + .i_features_2_2(daisy_chain_18_2_2), + .o_features_2_2(daisy_chain_19_2_2), + .i_features_2_3(daisy_chain_18_2_3), + .o_features_2_3(daisy_chain_19_2_3), + .i_features_2_4(daisy_chain_18_2_4), + .o_features_2_4(daisy_chain_19_2_4), + .i_features_2_5(daisy_chain_18_2_5), + .o_features_2_5(daisy_chain_19_2_5), + .i_features_3_0(daisy_chain_18_3_0), + .o_features_3_0(daisy_chain_19_3_0), + .i_features_3_1(daisy_chain_18_3_1), + .o_features_3_1(daisy_chain_19_3_1), + .i_features_3_2(daisy_chain_18_3_2), + .o_features_3_2(daisy_chain_19_3_2), + .i_features_3_3(daisy_chain_18_3_3), + .o_features_3_3(daisy_chain_19_3_3), + .i_features_3_4(daisy_chain_18_3_4), + .o_features_3_4(daisy_chain_19_3_4), + .i_features_3_5(daisy_chain_18_3_5), + .o_features_3_5(daisy_chain_19_3_5), + .o_result_0(PE_output_19_0), + .o_result_1(PE_output_19_1), + .o_result_2(PE_output_19_2), + .o_result_3(PE_output_19_3), + .o_result_4(PE_output_19_4), + .o_result_5(PE_output_19_5), + .o_valid(PE_valid_19), + .o_next_reset(PE_next_reset_19), + .o_next_valid(PE_next_valid_19) +); + +processing_element processing_element_inst_20 ( + .clk(clk), + .i_reset(PE_next_reset_19), + .i_valid(PE_next_valid_19), + .i_features_0_0(daisy_chain_19_0_0), + .o_features_0_0(daisy_chain_20_0_0), + .i_features_0_1(daisy_chain_19_0_1), + .o_features_0_1(daisy_chain_20_0_1), + .i_features_0_2(daisy_chain_19_0_2), + .o_features_0_2(daisy_chain_20_0_2), + .i_features_0_3(daisy_chain_19_0_3), + .o_features_0_3(daisy_chain_20_0_3), + .i_features_0_4(daisy_chain_19_0_4), + .o_features_0_4(daisy_chain_20_0_4), + .i_features_0_5(daisy_chain_19_0_5), + .o_features_0_5(daisy_chain_20_0_5), + .i_features_1_0(daisy_chain_19_1_0), + .o_features_1_0(daisy_chain_20_1_0), + .i_features_1_1(daisy_chain_19_1_1), + .o_features_1_1(daisy_chain_20_1_1), + .i_features_1_2(daisy_chain_19_1_2), + .o_features_1_2(daisy_chain_20_1_2), + .i_features_1_3(daisy_chain_19_1_3), + .o_features_1_3(daisy_chain_20_1_3), + .i_features_1_4(daisy_chain_19_1_4), + .o_features_1_4(daisy_chain_20_1_4), + .i_features_1_5(daisy_chain_19_1_5), + .o_features_1_5(daisy_chain_20_1_5), + .i_features_2_0(daisy_chain_19_2_0), + .o_features_2_0(daisy_chain_20_2_0), + .i_features_2_1(daisy_chain_19_2_1), + .o_features_2_1(daisy_chain_20_2_1), + .i_features_2_2(daisy_chain_19_2_2), + .o_features_2_2(daisy_chain_20_2_2), + .i_features_2_3(daisy_chain_19_2_3), + .o_features_2_3(daisy_chain_20_2_3), + .i_features_2_4(daisy_chain_19_2_4), + .o_features_2_4(daisy_chain_20_2_4), + .i_features_2_5(daisy_chain_19_2_5), + .o_features_2_5(daisy_chain_20_2_5), + .i_features_3_0(daisy_chain_19_3_0), + .o_features_3_0(daisy_chain_20_3_0), + .i_features_3_1(daisy_chain_19_3_1), + .o_features_3_1(daisy_chain_20_3_1), + .i_features_3_2(daisy_chain_19_3_2), + .o_features_3_2(daisy_chain_20_3_2), + .i_features_3_3(daisy_chain_19_3_3), + .o_features_3_3(daisy_chain_20_3_3), + .i_features_3_4(daisy_chain_19_3_4), + .o_features_3_4(daisy_chain_20_3_4), + .i_features_3_5(daisy_chain_19_3_5), + .o_features_3_5(daisy_chain_20_3_5), + .o_result_0(PE_output_20_0), + .o_result_1(PE_output_20_1), + .o_result_2(PE_output_20_2), + .o_result_3(PE_output_20_3), + .o_result_4(PE_output_20_4), + .o_result_5(PE_output_20_5), + .o_valid(PE_valid_20), + .o_next_reset(PE_next_reset_20), + .o_next_valid(PE_next_valid_20) +); + +processing_element processing_element_inst_21 ( + .clk(clk), + .i_reset(PE_next_reset_20), + .i_valid(PE_next_valid_20), + .i_features_0_0(daisy_chain_20_0_0), + .o_features_0_0(daisy_chain_21_0_0), + .i_features_0_1(daisy_chain_20_0_1), + .o_features_0_1(daisy_chain_21_0_1), + .i_features_0_2(daisy_chain_20_0_2), + .o_features_0_2(daisy_chain_21_0_2), + .i_features_0_3(daisy_chain_20_0_3), + .o_features_0_3(daisy_chain_21_0_3), + .i_features_0_4(daisy_chain_20_0_4), + .o_features_0_4(daisy_chain_21_0_4), + .i_features_0_5(daisy_chain_20_0_5), + .o_features_0_5(daisy_chain_21_0_5), + .i_features_1_0(daisy_chain_20_1_0), + .o_features_1_0(daisy_chain_21_1_0), + .i_features_1_1(daisy_chain_20_1_1), + .o_features_1_1(daisy_chain_21_1_1), + .i_features_1_2(daisy_chain_20_1_2), + .o_features_1_2(daisy_chain_21_1_2), + .i_features_1_3(daisy_chain_20_1_3), + .o_features_1_3(daisy_chain_21_1_3), + .i_features_1_4(daisy_chain_20_1_4), + .o_features_1_4(daisy_chain_21_1_4), + .i_features_1_5(daisy_chain_20_1_5), + .o_features_1_5(daisy_chain_21_1_5), + .i_features_2_0(daisy_chain_20_2_0), + .o_features_2_0(daisy_chain_21_2_0), + .i_features_2_1(daisy_chain_20_2_1), + .o_features_2_1(daisy_chain_21_2_1), + .i_features_2_2(daisy_chain_20_2_2), + .o_features_2_2(daisy_chain_21_2_2), + .i_features_2_3(daisy_chain_20_2_3), + .o_features_2_3(daisy_chain_21_2_3), + .i_features_2_4(daisy_chain_20_2_4), + .o_features_2_4(daisy_chain_21_2_4), + .i_features_2_5(daisy_chain_20_2_5), + .o_features_2_5(daisy_chain_21_2_5), + .i_features_3_0(daisy_chain_20_3_0), + .o_features_3_0(daisy_chain_21_3_0), + .i_features_3_1(daisy_chain_20_3_1), + .o_features_3_1(daisy_chain_21_3_1), + .i_features_3_2(daisy_chain_20_3_2), + .o_features_3_2(daisy_chain_21_3_2), + .i_features_3_3(daisy_chain_20_3_3), + .o_features_3_3(daisy_chain_21_3_3), + .i_features_3_4(daisy_chain_20_3_4), + .o_features_3_4(daisy_chain_21_3_4), + .i_features_3_5(daisy_chain_20_3_5), + .o_features_3_5(daisy_chain_21_3_5), + .o_result_0(PE_output_21_0), + .o_result_1(PE_output_21_1), + .o_result_2(PE_output_21_2), + .o_result_3(PE_output_21_3), + .o_result_4(PE_output_21_4), + .o_result_5(PE_output_21_5), + .o_valid(PE_valid_21), + .o_next_reset(PE_next_reset_21), + .o_next_valid(PE_next_valid_21) +); + +processing_element processing_element_inst_22 ( + .clk(clk), + .i_reset(PE_next_reset_21), + .i_valid(PE_next_valid_21), + .i_features_0_0(daisy_chain_21_0_0), + .o_features_0_0(daisy_chain_22_0_0), + .i_features_0_1(daisy_chain_21_0_1), + .o_features_0_1(daisy_chain_22_0_1), + .i_features_0_2(daisy_chain_21_0_2), + .o_features_0_2(daisy_chain_22_0_2), + .i_features_0_3(daisy_chain_21_0_3), + .o_features_0_3(daisy_chain_22_0_3), + .i_features_0_4(daisy_chain_21_0_4), + .o_features_0_4(daisy_chain_22_0_4), + .i_features_0_5(daisy_chain_21_0_5), + .o_features_0_5(daisy_chain_22_0_5), + .i_features_1_0(daisy_chain_21_1_0), + .o_features_1_0(daisy_chain_22_1_0), + .i_features_1_1(daisy_chain_21_1_1), + .o_features_1_1(daisy_chain_22_1_1), + .i_features_1_2(daisy_chain_21_1_2), + .o_features_1_2(daisy_chain_22_1_2), + .i_features_1_3(daisy_chain_21_1_3), + .o_features_1_3(daisy_chain_22_1_3), + .i_features_1_4(daisy_chain_21_1_4), + .o_features_1_4(daisy_chain_22_1_4), + .i_features_1_5(daisy_chain_21_1_5), + .o_features_1_5(daisy_chain_22_1_5), + .i_features_2_0(daisy_chain_21_2_0), + .o_features_2_0(daisy_chain_22_2_0), + .i_features_2_1(daisy_chain_21_2_1), + .o_features_2_1(daisy_chain_22_2_1), + .i_features_2_2(daisy_chain_21_2_2), + .o_features_2_2(daisy_chain_22_2_2), + .i_features_2_3(daisy_chain_21_2_3), + .o_features_2_3(daisy_chain_22_2_3), + .i_features_2_4(daisy_chain_21_2_4), + .o_features_2_4(daisy_chain_22_2_4), + .i_features_2_5(daisy_chain_21_2_5), + .o_features_2_5(daisy_chain_22_2_5), + .i_features_3_0(daisy_chain_21_3_0), + .o_features_3_0(daisy_chain_22_3_0), + .i_features_3_1(daisy_chain_21_3_1), + .o_features_3_1(daisy_chain_22_3_1), + .i_features_3_2(daisy_chain_21_3_2), + .o_features_3_2(daisy_chain_22_3_2), + .i_features_3_3(daisy_chain_21_3_3), + .o_features_3_3(daisy_chain_22_3_3), + .i_features_3_4(daisy_chain_21_3_4), + .o_features_3_4(daisy_chain_22_3_4), + .i_features_3_5(daisy_chain_21_3_5), + .o_features_3_5(daisy_chain_22_3_5), + .o_result_0(PE_output_22_0), + .o_result_1(PE_output_22_1), + .o_result_2(PE_output_22_2), + .o_result_3(PE_output_22_3), + .o_result_4(PE_output_22_4), + .o_result_5(PE_output_22_5), + .o_valid(PE_valid_22), + .o_next_reset(PE_next_reset_22), + .o_next_valid(PE_next_valid_22) +); + +processing_element processing_element_inst_23 ( + .clk(clk), + .i_reset(PE_next_reset_22), + .i_valid(PE_next_valid_22), + .i_features_0_0(daisy_chain_22_0_0), + .o_features_0_0(daisy_chain_23_0_0), + .i_features_0_1(daisy_chain_22_0_1), + .o_features_0_1(daisy_chain_23_0_1), + .i_features_0_2(daisy_chain_22_0_2), + .o_features_0_2(daisy_chain_23_0_2), + .i_features_0_3(daisy_chain_22_0_3), + .o_features_0_3(daisy_chain_23_0_3), + .i_features_0_4(daisy_chain_22_0_4), + .o_features_0_4(daisy_chain_23_0_4), + .i_features_0_5(daisy_chain_22_0_5), + .o_features_0_5(daisy_chain_23_0_5), + .i_features_1_0(daisy_chain_22_1_0), + .o_features_1_0(daisy_chain_23_1_0), + .i_features_1_1(daisy_chain_22_1_1), + .o_features_1_1(daisy_chain_23_1_1), + .i_features_1_2(daisy_chain_22_1_2), + .o_features_1_2(daisy_chain_23_1_2), + .i_features_1_3(daisy_chain_22_1_3), + .o_features_1_3(daisy_chain_23_1_3), + .i_features_1_4(daisy_chain_22_1_4), + .o_features_1_4(daisy_chain_23_1_4), + .i_features_1_5(daisy_chain_22_1_5), + .o_features_1_5(daisy_chain_23_1_5), + .i_features_2_0(daisy_chain_22_2_0), + .o_features_2_0(daisy_chain_23_2_0), + .i_features_2_1(daisy_chain_22_2_1), + .o_features_2_1(daisy_chain_23_2_1), + .i_features_2_2(daisy_chain_22_2_2), + .o_features_2_2(daisy_chain_23_2_2), + .i_features_2_3(daisy_chain_22_2_3), + .o_features_2_3(daisy_chain_23_2_3), + .i_features_2_4(daisy_chain_22_2_4), + .o_features_2_4(daisy_chain_23_2_4), + .i_features_2_5(daisy_chain_22_2_5), + .o_features_2_5(daisy_chain_23_2_5), + .i_features_3_0(daisy_chain_22_3_0), + .o_features_3_0(daisy_chain_23_3_0), + .i_features_3_1(daisy_chain_22_3_1), + .o_features_3_1(daisy_chain_23_3_1), + .i_features_3_2(daisy_chain_22_3_2), + .o_features_3_2(daisy_chain_23_3_2), + .i_features_3_3(daisy_chain_22_3_3), + .o_features_3_3(daisy_chain_23_3_3), + .i_features_3_4(daisy_chain_22_3_4), + .o_features_3_4(daisy_chain_23_3_4), + .i_features_3_5(daisy_chain_22_3_5), + .o_features_3_5(daisy_chain_23_3_5), + .o_result_0(PE_output_23_0), + .o_result_1(PE_output_23_1), + .o_result_2(PE_output_23_2), + .o_result_3(PE_output_23_3), + .o_result_4(PE_output_23_4), + .o_result_5(PE_output_23_5), + .o_valid(PE_valid_23), + .o_next_reset(PE_next_reset_23), + .o_next_valid(PE_next_valid_23) +); + +inverse_winograd_0 inverse_winograd_0_inst ( + .clk(clk), + .i_valid(PE_valid_0), + .i_result_0(PE_output_0_0), + .i_result_1(PE_output_0_1), + .i_result_2(PE_output_0_2), + .i_result_3(PE_output_0_3), + .i_result_4(PE_output_0_4), + .i_result_5(PE_output_0_5), + .o_result_0(INV_output_0_0), + .o_result_1(INV_output_0_1), + .o_result_2(INV_output_0_2), + .o_result_3(INV_output_0_3), + .o_valid(INV_valid_0) +); + +inverse_winograd_1 inverse_winograd_1_inst ( + .clk(clk), + .i_valid(PE_valid_1), + .i_result_0(PE_output_1_0), + .i_result_1(PE_output_1_1), + .i_result_2(PE_output_1_2), + .i_result_3(PE_output_1_3), + .i_result_4(PE_output_1_4), + .i_result_5(PE_output_1_5), + .o_result_0(INV_output_1_0), + .o_result_1(INV_output_1_1), + .o_result_2(INV_output_1_2), + .o_result_3(INV_output_1_3), + .o_valid(INV_valid_1) +); + +inverse_winograd_2 inverse_winograd_2_inst ( + .clk(clk), + .i_valid(PE_valid_2), + .i_result_0(PE_output_2_0), + .i_result_1(PE_output_2_1), + .i_result_2(PE_output_2_2), + .i_result_3(PE_output_2_3), + .i_result_4(PE_output_2_4), + .i_result_5(PE_output_2_5), + .o_result_0(INV_output_2_0), + .o_result_1(INV_output_2_1), + .o_result_2(INV_output_2_2), + .o_result_3(INV_output_2_3), + .o_valid(INV_valid_2) +); + +inverse_winograd_3 inverse_winograd_3_inst ( + .clk(clk), + .i_valid(PE_valid_3), + .i_result_0(PE_output_3_0), + .i_result_1(PE_output_3_1), + .i_result_2(PE_output_3_2), + .i_result_3(PE_output_3_3), + .i_result_4(PE_output_3_4), + .i_result_5(PE_output_3_5), + .o_result_0(INV_output_3_0), + .o_result_1(INV_output_3_1), + .o_result_2(INV_output_3_2), + .o_result_3(INV_output_3_3), + .o_valid(INV_valid_3) +); + +inverse_winograd_4 inverse_winograd_4_inst ( + .clk(clk), + .i_valid(PE_valid_4), + .i_result_0(PE_output_4_0), + .i_result_1(PE_output_4_1), + .i_result_2(PE_output_4_2), + .i_result_3(PE_output_4_3), + .i_result_4(PE_output_4_4), + .i_result_5(PE_output_4_5), + .o_result_0(INV_output_4_0), + .o_result_1(INV_output_4_1), + .o_result_2(INV_output_4_2), + .o_result_3(INV_output_4_3), + .o_valid(INV_valid_4) +); + +inverse_winograd_5 inverse_winograd_5_inst ( + .clk(clk), + .i_valid(PE_valid_5), + .i_result_0(PE_output_5_0), + .i_result_1(PE_output_5_1), + .i_result_2(PE_output_5_2), + .i_result_3(PE_output_5_3), + .i_result_4(PE_output_5_4), + .i_result_5(PE_output_5_5), + .o_result_0(INV_output_5_0), + .o_result_1(INV_output_5_1), + .o_result_2(INV_output_5_2), + .o_result_3(INV_output_5_3), + .o_valid(INV_valid_5) +); + +inverse_winograd_6 inverse_winograd_6_inst ( + .clk(clk), + .i_valid(PE_valid_6), + .i_result_0(PE_output_6_0), + .i_result_1(PE_output_6_1), + .i_result_2(PE_output_6_2), + .i_result_3(PE_output_6_3), + .i_result_4(PE_output_6_4), + .i_result_5(PE_output_6_5), + .o_result_0(INV_output_6_0), + .o_result_1(INV_output_6_1), + .o_result_2(INV_output_6_2), + .o_result_3(INV_output_6_3), + .o_valid(INV_valid_6) +); + +inverse_winograd_7 inverse_winograd_7_inst ( + .clk(clk), + .i_valid(PE_valid_7), + .i_result_0(PE_output_7_0), + .i_result_1(PE_output_7_1), + .i_result_2(PE_output_7_2), + .i_result_3(PE_output_7_3), + .i_result_4(PE_output_7_4), + .i_result_5(PE_output_7_5), + .o_result_0(INV_output_7_0), + .o_result_1(INV_output_7_1), + .o_result_2(INV_output_7_2), + .o_result_3(INV_output_7_3), + .o_valid(INV_valid_7) +); + +inverse_winograd_8 inverse_winograd_8_inst ( + .clk(clk), + .i_valid(PE_valid_8), + .i_result_0(PE_output_8_0), + .i_result_1(PE_output_8_1), + .i_result_2(PE_output_8_2), + .i_result_3(PE_output_8_3), + .i_result_4(PE_output_8_4), + .i_result_5(PE_output_8_5), + .o_result_0(INV_output_8_0), + .o_result_1(INV_output_8_1), + .o_result_2(INV_output_8_2), + .o_result_3(INV_output_8_3), + .o_valid(INV_valid_8) +); + +inverse_winograd_9 inverse_winograd_9_inst ( + .clk(clk), + .i_valid(PE_valid_9), + .i_result_0(PE_output_9_0), + .i_result_1(PE_output_9_1), + .i_result_2(PE_output_9_2), + .i_result_3(PE_output_9_3), + .i_result_4(PE_output_9_4), + .i_result_5(PE_output_9_5), + .o_result_0(INV_output_9_0), + .o_result_1(INV_output_9_1), + .o_result_2(INV_output_9_2), + .o_result_3(INV_output_9_3), + .o_valid(INV_valid_9) +); + +inverse_winograd_10 inverse_winograd_10_inst ( + .clk(clk), + .i_valid(PE_valid_10), + .i_result_0(PE_output_10_0), + .i_result_1(PE_output_10_1), + .i_result_2(PE_output_10_2), + .i_result_3(PE_output_10_3), + .i_result_4(PE_output_10_4), + .i_result_5(PE_output_10_5), + .o_result_0(INV_output_10_0), + .o_result_1(INV_output_10_1), + .o_result_2(INV_output_10_2), + .o_result_3(INV_output_10_3), + .o_valid(INV_valid_10) +); + +inverse_winograd_11 inverse_winograd_11_inst ( + .clk(clk), + .i_valid(PE_valid_11), + .i_result_0(PE_output_11_0), + .i_result_1(PE_output_11_1), + .i_result_2(PE_output_11_2), + .i_result_3(PE_output_11_3), + .i_result_4(PE_output_11_4), + .i_result_5(PE_output_11_5), + .o_result_0(INV_output_11_0), + .o_result_1(INV_output_11_1), + .o_result_2(INV_output_11_2), + .o_result_3(INV_output_11_3), + .o_valid(INV_valid_11) +); + +inverse_winograd_12 inverse_winograd_12_inst ( + .clk(clk), + .i_valid(PE_valid_12), + .i_result_0(PE_output_12_0), + .i_result_1(PE_output_12_1), + .i_result_2(PE_output_12_2), + .i_result_3(PE_output_12_3), + .i_result_4(PE_output_12_4), + .i_result_5(PE_output_12_5), + .o_result_0(INV_output_12_0), + .o_result_1(INV_output_12_1), + .o_result_2(INV_output_12_2), + .o_result_3(INV_output_12_3), + .o_valid(INV_valid_12) +); + +inverse_winograd_13 inverse_winograd_13_inst ( + .clk(clk), + .i_valid(PE_valid_13), + .i_result_0(PE_output_13_0), + .i_result_1(PE_output_13_1), + .i_result_2(PE_output_13_2), + .i_result_3(PE_output_13_3), + .i_result_4(PE_output_13_4), + .i_result_5(PE_output_13_5), + .o_result_0(INV_output_13_0), + .o_result_1(INV_output_13_1), + .o_result_2(INV_output_13_2), + .o_result_3(INV_output_13_3), + .o_valid(INV_valid_13) +); + +inverse_winograd_14 inverse_winograd_14_inst ( + .clk(clk), + .i_valid(PE_valid_14), + .i_result_0(PE_output_14_0), + .i_result_1(PE_output_14_1), + .i_result_2(PE_output_14_2), + .i_result_3(PE_output_14_3), + .i_result_4(PE_output_14_4), + .i_result_5(PE_output_14_5), + .o_result_0(INV_output_14_0), + .o_result_1(INV_output_14_1), + .o_result_2(INV_output_14_2), + .o_result_3(INV_output_14_3), + .o_valid(INV_valid_14) +); + +inverse_winograd_15 inverse_winograd_15_inst ( + .clk(clk), + .i_valid(PE_valid_15), + .i_result_0(PE_output_15_0), + .i_result_1(PE_output_15_1), + .i_result_2(PE_output_15_2), + .i_result_3(PE_output_15_3), + .i_result_4(PE_output_15_4), + .i_result_5(PE_output_15_5), + .o_result_0(INV_output_15_0), + .o_result_1(INV_output_15_1), + .o_result_2(INV_output_15_2), + .o_result_3(INV_output_15_3), + .o_valid(INV_valid_15) +); + +inverse_winograd_16 inverse_winograd_16_inst ( + .clk(clk), + .i_valid(PE_valid_16), + .i_result_0(PE_output_16_0), + .i_result_1(PE_output_16_1), + .i_result_2(PE_output_16_2), + .i_result_3(PE_output_16_3), + .i_result_4(PE_output_16_4), + .i_result_5(PE_output_16_5), + .o_result_0(INV_output_16_0), + .o_result_1(INV_output_16_1), + .o_result_2(INV_output_16_2), + .o_result_3(INV_output_16_3), + .o_valid(INV_valid_16) +); + +inverse_winograd_17 inverse_winograd_17_inst ( + .clk(clk), + .i_valid(PE_valid_17), + .i_result_0(PE_output_17_0), + .i_result_1(PE_output_17_1), + .i_result_2(PE_output_17_2), + .i_result_3(PE_output_17_3), + .i_result_4(PE_output_17_4), + .i_result_5(PE_output_17_5), + .o_result_0(INV_output_17_0), + .o_result_1(INV_output_17_1), + .o_result_2(INV_output_17_2), + .o_result_3(INV_output_17_3), + .o_valid(INV_valid_17) +); + +inverse_winograd_18 inverse_winograd_18_inst ( + .clk(clk), + .i_valid(PE_valid_18), + .i_result_0(PE_output_18_0), + .i_result_1(PE_output_18_1), + .i_result_2(PE_output_18_2), + .i_result_3(PE_output_18_3), + .i_result_4(PE_output_18_4), + .i_result_5(PE_output_18_5), + .o_result_0(INV_output_18_0), + .o_result_1(INV_output_18_1), + .o_result_2(INV_output_18_2), + .o_result_3(INV_output_18_3), + .o_valid(INV_valid_18) +); + +inverse_winograd_19 inverse_winograd_19_inst ( + .clk(clk), + .i_valid(PE_valid_19), + .i_result_0(PE_output_19_0), + .i_result_1(PE_output_19_1), + .i_result_2(PE_output_19_2), + .i_result_3(PE_output_19_3), + .i_result_4(PE_output_19_4), + .i_result_5(PE_output_19_5), + .o_result_0(INV_output_19_0), + .o_result_1(INV_output_19_1), + .o_result_2(INV_output_19_2), + .o_result_3(INV_output_19_3), + .o_valid(INV_valid_19) +); + +inverse_winograd_20 inverse_winograd_20_inst ( + .clk(clk), + .i_valid(PE_valid_20), + .i_result_0(PE_output_20_0), + .i_result_1(PE_output_20_1), + .i_result_2(PE_output_20_2), + .i_result_3(PE_output_20_3), + .i_result_4(PE_output_20_4), + .i_result_5(PE_output_20_5), + .o_result_0(INV_output_20_0), + .o_result_1(INV_output_20_1), + .o_result_2(INV_output_20_2), + .o_result_3(INV_output_20_3), + .o_valid(INV_valid_20) +); + +inverse_winograd_21 inverse_winograd_21_inst ( + .clk(clk), + .i_valid(PE_valid_21), + .i_result_0(PE_output_21_0), + .i_result_1(PE_output_21_1), + .i_result_2(PE_output_21_2), + .i_result_3(PE_output_21_3), + .i_result_4(PE_output_21_4), + .i_result_5(PE_output_21_5), + .o_result_0(INV_output_21_0), + .o_result_1(INV_output_21_1), + .o_result_2(INV_output_21_2), + .o_result_3(INV_output_21_3), + .o_valid(INV_valid_21) +); + +inverse_winograd_22 inverse_winograd_22_inst ( + .clk(clk), + .i_valid(PE_valid_22), + .i_result_0(PE_output_22_0), + .i_result_1(PE_output_22_1), + .i_result_2(PE_output_22_2), + .i_result_3(PE_output_22_3), + .i_result_4(PE_output_22_4), + .i_result_5(PE_output_22_5), + .o_result_0(INV_output_22_0), + .o_result_1(INV_output_22_1), + .o_result_2(INV_output_22_2), + .o_result_3(INV_output_22_3), + .o_valid(INV_valid_22) +); + +inverse_winograd_23 inverse_winograd_23_inst ( + .clk(clk), + .i_valid(PE_valid_23), + .i_result_0(PE_output_23_0), + .i_result_1(PE_output_23_1), + .i_result_2(PE_output_23_2), + .i_result_3(PE_output_23_3), + .i_result_4(PE_output_23_4), + .i_result_5(PE_output_23_5), + .o_result_0(INV_output_23_0), + .o_result_1(INV_output_23_1), + .o_result_2(INV_output_23_2), + .o_result_3(INV_output_23_3), + .o_valid(INV_valid_23) +); + +pooling pooling_inst_0 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_0), + .i_result_0(INV_output_0_0), + .i_result_1(INV_output_0_1), + .i_result_2(INV_output_0_2), + .i_result_3(INV_output_0_3), + .o_result(POOL_output_0), + .o_valid(POOL_valid_0) +); + +pooling pooling_inst_1 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_1), + .i_result_0(INV_output_1_0), + .i_result_1(INV_output_1_1), + .i_result_2(INV_output_1_2), + .i_result_3(INV_output_1_3), + .o_result(POOL_output_1), + .o_valid(POOL_valid_1) +); + +pooling pooling_inst_2 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_2), + .i_result_0(INV_output_2_0), + .i_result_1(INV_output_2_1), + .i_result_2(INV_output_2_2), + .i_result_3(INV_output_2_3), + .o_result(POOL_output_2), + .o_valid(POOL_valid_2) +); + +pooling pooling_inst_3 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_3), + .i_result_0(INV_output_3_0), + .i_result_1(INV_output_3_1), + .i_result_2(INV_output_3_2), + .i_result_3(INV_output_3_3), + .o_result(POOL_output_3), + .o_valid(POOL_valid_3) +); + +pooling pooling_inst_4 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_4), + .i_result_0(INV_output_4_0), + .i_result_1(INV_output_4_1), + .i_result_2(INV_output_4_2), + .i_result_3(INV_output_4_3), + .o_result(POOL_output_4), + .o_valid(POOL_valid_4) +); + +pooling pooling_inst_5 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_5), + .i_result_0(INV_output_5_0), + .i_result_1(INV_output_5_1), + .i_result_2(INV_output_5_2), + .i_result_3(INV_output_5_3), + .o_result(POOL_output_5), + .o_valid(POOL_valid_5) +); + +pooling pooling_inst_6 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_6), + .i_result_0(INV_output_6_0), + .i_result_1(INV_output_6_1), + .i_result_2(INV_output_6_2), + .i_result_3(INV_output_6_3), + .o_result(POOL_output_6), + .o_valid(POOL_valid_6) +); + +pooling pooling_inst_7 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_7), + .i_result_0(INV_output_7_0), + .i_result_1(INV_output_7_1), + .i_result_2(INV_output_7_2), + .i_result_3(INV_output_7_3), + .o_result(POOL_output_7), + .o_valid(POOL_valid_7) +); + +pooling pooling_inst_8 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_8), + .i_result_0(INV_output_8_0), + .i_result_1(INV_output_8_1), + .i_result_2(INV_output_8_2), + .i_result_3(INV_output_8_3), + .o_result(POOL_output_8), + .o_valid(POOL_valid_8) +); + +pooling pooling_inst_9 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_9), + .i_result_0(INV_output_9_0), + .i_result_1(INV_output_9_1), + .i_result_2(INV_output_9_2), + .i_result_3(INV_output_9_3), + .o_result(POOL_output_9), + .o_valid(POOL_valid_9) +); + +pooling pooling_inst_10 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_10), + .i_result_0(INV_output_10_0), + .i_result_1(INV_output_10_1), + .i_result_2(INV_output_10_2), + .i_result_3(INV_output_10_3), + .o_result(POOL_output_10), + .o_valid(POOL_valid_10) +); + +pooling pooling_inst_11 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_11), + .i_result_0(INV_output_11_0), + .i_result_1(INV_output_11_1), + .i_result_2(INV_output_11_2), + .i_result_3(INV_output_11_3), + .o_result(POOL_output_11), + .o_valid(POOL_valid_11) +); + +pooling pooling_inst_12 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_12), + .i_result_0(INV_output_12_0), + .i_result_1(INV_output_12_1), + .i_result_2(INV_output_12_2), + .i_result_3(INV_output_12_3), + .o_result(POOL_output_12), + .o_valid(POOL_valid_12) +); + +pooling pooling_inst_13 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_13), + .i_result_0(INV_output_13_0), + .i_result_1(INV_output_13_1), + .i_result_2(INV_output_13_2), + .i_result_3(INV_output_13_3), + .o_result(POOL_output_13), + .o_valid(POOL_valid_13) +); + +pooling pooling_inst_14 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_14), + .i_result_0(INV_output_14_0), + .i_result_1(INV_output_14_1), + .i_result_2(INV_output_14_2), + .i_result_3(INV_output_14_3), + .o_result(POOL_output_14), + .o_valid(POOL_valid_14) +); + +pooling pooling_inst_15 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_15), + .i_result_0(INV_output_15_0), + .i_result_1(INV_output_15_1), + .i_result_2(INV_output_15_2), + .i_result_3(INV_output_15_3), + .o_result(POOL_output_15), + .o_valid(POOL_valid_15) +); + +pooling pooling_inst_16 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_16), + .i_result_0(INV_output_16_0), + .i_result_1(INV_output_16_1), + .i_result_2(INV_output_16_2), + .i_result_3(INV_output_16_3), + .o_result(POOL_output_16), + .o_valid(POOL_valid_16) +); + +pooling pooling_inst_17 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_17), + .i_result_0(INV_output_17_0), + .i_result_1(INV_output_17_1), + .i_result_2(INV_output_17_2), + .i_result_3(INV_output_17_3), + .o_result(POOL_output_17), + .o_valid(POOL_valid_17) +); + +pooling pooling_inst_18 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_18), + .i_result_0(INV_output_18_0), + .i_result_1(INV_output_18_1), + .i_result_2(INV_output_18_2), + .i_result_3(INV_output_18_3), + .o_result(POOL_output_18), + .o_valid(POOL_valid_18) +); + +pooling pooling_inst_19 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_19), + .i_result_0(INV_output_19_0), + .i_result_1(INV_output_19_1), + .i_result_2(INV_output_19_2), + .i_result_3(INV_output_19_3), + .o_result(POOL_output_19), + .o_valid(POOL_valid_19) +); + +pooling pooling_inst_20 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_20), + .i_result_0(INV_output_20_0), + .i_result_1(INV_output_20_1), + .i_result_2(INV_output_20_2), + .i_result_3(INV_output_20_3), + .o_result(POOL_output_20), + .o_valid(POOL_valid_20) +); + +pooling pooling_inst_21 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_21), + .i_result_0(INV_output_21_0), + .i_result_1(INV_output_21_1), + .i_result_2(INV_output_21_2), + .i_result_3(INV_output_21_3), + .o_result(POOL_output_21), + .o_valid(POOL_valid_21) +); + +pooling pooling_inst_22 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_22), + .i_result_0(INV_output_22_0), + .i_result_1(INV_output_22_1), + .i_result_2(INV_output_22_2), + .i_result_3(INV_output_22_3), + .o_result(POOL_output_22), + .o_valid(POOL_valid_22) +); + +pooling pooling_inst_23 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_23), + .i_result_0(INV_output_23_0), + .i_result_1(INV_output_23_1), + .i_result_2(INV_output_23_2), + .i_result_3(INV_output_23_3), + .o_result(POOL_output_23), + .o_valid(POOL_valid_23) +); + +store_output store_output_inst ( + .clk(clk), + .i_valid(POOL_valid_0), + .i_reset(i_reset), + .i_result_0(POOL_output_0), + .i_result_1(POOL_output_1), + .i_result_2(POOL_output_2), + .i_result_3(POOL_output_3), + .i_result_4(POOL_output_4), + .i_result_5(POOL_output_5), + .i_result_6(POOL_output_6), + .i_result_7(POOL_output_7), + .i_result_8(POOL_output_8), + .i_result_9(POOL_output_9), + .i_result_10(POOL_output_10), + .i_result_11(POOL_output_11), + .i_result_12(POOL_output_12), + .i_result_13(POOL_output_13), + .i_result_14(POOL_output_14), + .i_result_15(POOL_output_15), + .i_result_16(POOL_output_16), + .i_result_17(POOL_output_17), + .i_result_18(POOL_output_18), + .i_result_19(POOL_output_19), + .i_result_20(POOL_output_20), + .i_result_21(POOL_output_21), + .i_result_22(POOL_output_22), + .i_result_23(POOL_output_23), + .o_store_0_0(STORE_output_0_0), + .o_store_0_1(STORE_output_0_1), + .o_store_0_2(STORE_output_0_2), + .o_store_0_3(STORE_output_0_3), + .o_store_1_0(STORE_output_1_0), + .o_store_1_1(STORE_output_1_1), + .o_store_1_2(STORE_output_1_2), + .o_store_1_3(STORE_output_1_3), + .o_store_2_0(STORE_output_2_0), + .o_store_2_1(STORE_output_2_1), + .o_store_2_2(STORE_output_2_2), + .o_store_2_3(STORE_output_2_3), + .o_store_3_0(STORE_output_3_0), + .o_store_3_1(STORE_output_3_1), + .o_store_3_2(STORE_output_3_2), + .o_store_3_3(STORE_output_3_3), + .o_store_4_0(STORE_output_4_0), + .o_store_4_1(STORE_output_4_1), + .o_store_4_2(STORE_output_4_2), + .o_store_4_3(STORE_output_4_3), + .o_store_5_0(STORE_output_5_0), + .o_store_5_1(STORE_output_5_1), + .o_store_5_2(STORE_output_5_2), + .o_store_5_3(STORE_output_5_3), + .o_wen_0(STORE_wen_0), + .o_wen_1(STORE_wen_1), + .o_wen_2(STORE_wen_2), + .o_wen_3(STORE_wen_3), + .o_wen_4(STORE_wen_4), + .o_wen_5(STORE_wen_5), + .o_addr(STORE_addr) +); + +signal_width_reducer signal_width_reducer_inst ( + .clk(clk), + .signals_0_0(dummy_out_0_0), + .reduced_signals_0_0(o_dummy_out_0_0), + .signals_0_1(dummy_out_0_1), + .reduced_signals_0_1(o_dummy_out_0_1), + .signals_0_2(dummy_out_0_2), + .reduced_signals_0_2(o_dummy_out_0_2), + .signals_0_3(dummy_out_0_3), + .reduced_signals_0_3(o_dummy_out_0_3), + .signals_1_0(dummy_out_1_0), + .reduced_signals_1_0(o_dummy_out_1_0), + .signals_1_1(dummy_out_1_1), + .reduced_signals_1_1(o_dummy_out_1_1), + .signals_1_2(dummy_out_1_2), + .reduced_signals_1_2(o_dummy_out_1_2), + .signals_1_3(dummy_out_1_3), + .reduced_signals_1_3(o_dummy_out_1_3), + .signals_2_0(dummy_out_2_0), + .reduced_signals_2_0(o_dummy_out_2_0), + .signals_2_1(dummy_out_2_1), + .reduced_signals_2_1(o_dummy_out_2_1), + .signals_2_2(dummy_out_2_2), + .reduced_signals_2_2(o_dummy_out_2_2), + .signals_2_3(dummy_out_2_3), + .reduced_signals_2_3(o_dummy_out_2_3), + .signals_3_0(dummy_out_3_0), + .reduced_signals_3_0(o_dummy_out_3_0), + .signals_3_1(dummy_out_3_1), + .reduced_signals_3_1(o_dummy_out_3_1), + .signals_3_2(dummy_out_3_2), + .reduced_signals_3_2(o_dummy_out_3_2), + .signals_3_3(dummy_out_3_3), + .reduced_signals_3_3(o_dummy_out_3_3), + .signals_4_0(dummy_out_4_0), + .reduced_signals_4_0(o_dummy_out_4_0), + .signals_4_1(dummy_out_4_1), + .reduced_signals_4_1(o_dummy_out_4_1), + .signals_4_2(dummy_out_4_2), + .reduced_signals_4_2(o_dummy_out_4_2), + .signals_4_3(dummy_out_4_3), + .reduced_signals_4_3(o_dummy_out_4_3), + .signals_5_0(dummy_out_5_0), + .reduced_signals_5_0(o_dummy_out_5_0), + .signals_5_1(dummy_out_5_1), + .reduced_signals_5_1(o_dummy_out_5_1), + .signals_5_2(dummy_out_5_2), + .reduced_signals_5_2(o_dummy_out_5_2), + .signals_5_3(dummy_out_5_3), + .reduced_signals_5_3(o_dummy_out_5_3), + .reset(i_reset) +); + +assign o_valid = POOL_valid_0; + +endmodule + +module inverse_winograd_1 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_27_0[29] == 1'b0) begin + result_wire_0 <= result_reg_27_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_27_1[29] == 1'b0) begin + result_wire_1 <= result_reg_27_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_27_2[29] == 1'b0) begin + result_wire_2 <= result_reg_27_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_27_3[29] == 1'b0) begin + result_wire_3 <= result_reg_27_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_27; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_adder_30_3 ( + input clock, + input [29:0] data0x, + input [29:0] data1x, + input [29:0] data2x, + input [29:0] data3x, + input [29:0] data4x, + input [29:0] data5x, + output [29:0] result +); + +reg [32:0] pipeline_0_0; +reg [32:0] pipeline_0_1; +reg [32:0] pipeline_0_2; +reg [32:0] pipeline_1_0; +reg [32:0] pipeline_1_1; +reg [32:0] pipeline_2_0; + +always @ (posedge clock) begin + pipeline_0_0 <= data0x + data1x; + pipeline_0_1 <= data2x + data3x; + pipeline_0_2 <= data4x + data5x; + pipeline_1_0 <= pipeline_0_0 + pipeline_0_1; + pipeline_1_1 <= pipeline_0_2; + pipeline_2_0 <= pipeline_1_0 + pipeline_1_1; +end + +assign result = pipeline_2_0; + +endmodule + +module inverse_winograd_0 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; +reg [29:0] result_reg_27_0; +reg [29:0] result_reg_27_1; +reg [29:0] result_reg_27_2; +reg [29:0] result_reg_27_3; +reg [29:0] result_reg_28_0; +reg [29:0] result_reg_28_1; +reg [29:0] result_reg_28_2; +reg [29:0] result_reg_28_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg out_valid_27; +reg out_valid_28; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; + out_valid_27 <= out_valid_26; + result_reg_27_0 <= result_reg_26_0; + result_reg_27_1 <= result_reg_26_1; + result_reg_27_2 <= result_reg_26_2; + result_reg_27_3 <= result_reg_26_3; + out_valid_28 <= out_valid_27; + result_reg_28_0 <= result_reg_27_0; + result_reg_28_1 <= result_reg_27_1; + result_reg_28_2 <= result_reg_27_2; + result_reg_28_3 <= result_reg_27_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_28_0[29] == 1'b0) begin + result_wire_0 <= result_reg_28_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_28_1[29] == 1'b0) begin + result_wire_1 <= result_reg_28_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_28_2[29] == 1'b0) begin + result_wire_2 <= result_reg_28_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_28_3[29] == 1'b0) begin + result_wire_3 <= result_reg_28_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_28; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_3 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_25_0[29] == 1'b0) begin + result_wire_0 <= result_reg_25_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_25_1[29] == 1'b0) begin + result_wire_1 <= result_reg_25_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_25_2[29] == 1'b0) begin + result_wire_2 <= result_reg_25_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_25_3[29] == 1'b0) begin + result_wire_3 <= result_reg_25_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_25; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_2 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; +reg [29:0] result_reg_25_0; +reg [29:0] result_reg_25_1; +reg [29:0] result_reg_25_2; +reg [29:0] result_reg_25_3; +reg [29:0] result_reg_26_0; +reg [29:0] result_reg_26_1; +reg [29:0] result_reg_26_2; +reg [29:0] result_reg_26_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg out_valid_25; +reg out_valid_26; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; + out_valid_25 <= out_valid_24; + result_reg_25_0 <= result_reg_24_0; + result_reg_25_1 <= result_reg_24_1; + result_reg_25_2 <= result_reg_24_2; + result_reg_25_3 <= result_reg_24_3; + out_valid_26 <= out_valid_25; + result_reg_26_0 <= result_reg_25_0; + result_reg_26_1 <= result_reg_25_1; + result_reg_26_2 <= result_reg_25_2; + result_reg_26_3 <= result_reg_25_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_26_0[29] == 1'b0) begin + result_wire_0 <= result_reg_26_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_26_1[29] == 1'b0) begin + result_wire_1 <= result_reg_26_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_26_2[29] == 1'b0) begin + result_wire_2 <= result_reg_26_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_26_3[29] == 1'b0) begin + result_wire_3 <= result_reg_26_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_26; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_5 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_23_0[29] == 1'b0) begin + result_wire_0 <= result_reg_23_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_23_1[29] == 1'b0) begin + result_wire_1 <= result_reg_23_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_23_2[29] == 1'b0) begin + result_wire_2 <= result_reg_23_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_23_3[29] == 1'b0) begin + result_wire_3 <= result_reg_23_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_23; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_4 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; +reg [29:0] result_reg_23_0; +reg [29:0] result_reg_23_1; +reg [29:0] result_reg_23_2; +reg [29:0] result_reg_23_3; +reg [29:0] result_reg_24_0; +reg [29:0] result_reg_24_1; +reg [29:0] result_reg_24_2; +reg [29:0] result_reg_24_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg out_valid_23; +reg out_valid_24; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; + out_valid_23 <= out_valid_22; + result_reg_23_0 <= result_reg_22_0; + result_reg_23_1 <= result_reg_22_1; + result_reg_23_2 <= result_reg_22_2; + result_reg_23_3 <= result_reg_22_3; + out_valid_24 <= out_valid_23; + result_reg_24_0 <= result_reg_23_0; + result_reg_24_1 <= result_reg_23_1; + result_reg_24_2 <= result_reg_23_2; + result_reg_24_3 <= result_reg_23_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_24_0[29] == 1'b0) begin + result_wire_0 <= result_reg_24_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_24_1[29] == 1'b0) begin + result_wire_1 <= result_reg_24_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_24_2[29] == 1'b0) begin + result_wire_2 <= result_reg_24_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_24_3[29] == 1'b0) begin + result_wire_3 <= result_reg_24_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_24; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_7 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_21_0[29] == 1'b0) begin + result_wire_0 <= result_reg_21_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_21_1[29] == 1'b0) begin + result_wire_1 <= result_reg_21_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_21_2[29] == 1'b0) begin + result_wire_2 <= result_reg_21_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_21_3[29] == 1'b0) begin + result_wire_3 <= result_reg_21_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_21; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_6 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; +reg [29:0] result_reg_21_0; +reg [29:0] result_reg_21_1; +reg [29:0] result_reg_21_2; +reg [29:0] result_reg_21_3; +reg [29:0] result_reg_22_0; +reg [29:0] result_reg_22_1; +reg [29:0] result_reg_22_2; +reg [29:0] result_reg_22_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg out_valid_21; +reg out_valid_22; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; + out_valid_21 <= out_valid_20; + result_reg_21_0 <= result_reg_20_0; + result_reg_21_1 <= result_reg_20_1; + result_reg_21_2 <= result_reg_20_2; + result_reg_21_3 <= result_reg_20_3; + out_valid_22 <= out_valid_21; + result_reg_22_0 <= result_reg_21_0; + result_reg_22_1 <= result_reg_21_1; + result_reg_22_2 <= result_reg_21_2; + result_reg_22_3 <= result_reg_21_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_22_0[29] == 1'b0) begin + result_wire_0 <= result_reg_22_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_22_1[29] == 1'b0) begin + result_wire_1 <= result_reg_22_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_22_2[29] == 1'b0) begin + result_wire_2 <= result_reg_22_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_22_3[29] == 1'b0) begin + result_wire_3 <= result_reg_22_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_22; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_9 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_19_0[29] == 1'b0) begin + result_wire_0 <= result_reg_19_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_19_1[29] == 1'b0) begin + result_wire_1 <= result_reg_19_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_19_2[29] == 1'b0) begin + result_wire_2 <= result_reg_19_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_19_3[29] == 1'b0) begin + result_wire_3 <= result_reg_19_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_19; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_8 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; +reg [29:0] result_reg_19_0; +reg [29:0] result_reg_19_1; +reg [29:0] result_reg_19_2; +reg [29:0] result_reg_19_3; +reg [29:0] result_reg_20_0; +reg [29:0] result_reg_20_1; +reg [29:0] result_reg_20_2; +reg [29:0] result_reg_20_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg out_valid_19; +reg out_valid_20; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; + out_valid_19 <= out_valid_18; + result_reg_19_0 <= result_reg_18_0; + result_reg_19_1 <= result_reg_18_1; + result_reg_19_2 <= result_reg_18_2; + result_reg_19_3 <= result_reg_18_3; + out_valid_20 <= out_valid_19; + result_reg_20_0 <= result_reg_19_0; + result_reg_20_1 <= result_reg_19_1; + result_reg_20_2 <= result_reg_19_2; + result_reg_20_3 <= result_reg_19_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_20_0[29] == 1'b0) begin + result_wire_0 <= result_reg_20_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_20_1[29] == 1'b0) begin + result_wire_1 <= result_reg_20_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_20_2[29] == 1'b0) begin + result_wire_2 <= result_reg_20_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_20_3[29] == 1'b0) begin + result_wire_3 <= result_reg_20_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_20; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_15 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_13_0[29] == 1'b0) begin + result_wire_0 <= result_reg_13_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_13_1[29] == 1'b0) begin + result_wire_1 <= result_reg_13_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_13_2[29] == 1'b0) begin + result_wire_2 <= result_reg_13_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_13_3[29] == 1'b0) begin + result_wire_3 <= result_reg_13_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_13; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_14 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_14_0[29] == 1'b0) begin + result_wire_0 <= result_reg_14_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_14_1[29] == 1'b0) begin + result_wire_1 <= result_reg_14_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_14_2[29] == 1'b0) begin + result_wire_2 <= result_reg_14_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_14_3[29] == 1'b0) begin + result_wire_3 <= result_reg_14_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_14; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_17 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_11_0[29] == 1'b0) begin + result_wire_0 <= result_reg_11_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_11_1[29] == 1'b0) begin + result_wire_1 <= result_reg_11_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_11_2[29] == 1'b0) begin + result_wire_2 <= result_reg_11_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_11_3[29] == 1'b0) begin + result_wire_3 <= result_reg_11_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_11; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_16 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_12_0[29] == 1'b0) begin + result_wire_0 <= result_reg_12_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_12_1[29] == 1'b0) begin + result_wire_1 <= result_reg_12_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_12_2[29] == 1'b0) begin + result_wire_2 <= result_reg_12_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_12_3[29] == 1'b0) begin + result_wire_3 <= result_reg_12_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_12; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_11 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_17_0[29] == 1'b0) begin + result_wire_0 <= result_reg_17_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_17_1[29] == 1'b0) begin + result_wire_1 <= result_reg_17_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_17_2[29] == 1'b0) begin + result_wire_2 <= result_reg_17_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_17_3[29] == 1'b0) begin + result_wire_3 <= result_reg_17_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_17; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_10 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; +reg [29:0] result_reg_17_0; +reg [29:0] result_reg_17_1; +reg [29:0] result_reg_17_2; +reg [29:0] result_reg_17_3; +reg [29:0] result_reg_18_0; +reg [29:0] result_reg_18_1; +reg [29:0] result_reg_18_2; +reg [29:0] result_reg_18_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg out_valid_17; +reg out_valid_18; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; + out_valid_17 <= out_valid_16; + result_reg_17_0 <= result_reg_16_0; + result_reg_17_1 <= result_reg_16_1; + result_reg_17_2 <= result_reg_16_2; + result_reg_17_3 <= result_reg_16_3; + out_valid_18 <= out_valid_17; + result_reg_18_0 <= result_reg_17_0; + result_reg_18_1 <= result_reg_17_1; + result_reg_18_2 <= result_reg_17_2; + result_reg_18_3 <= result_reg_17_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_18_0[29] == 1'b0) begin + result_wire_0 <= result_reg_18_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_18_1[29] == 1'b0) begin + result_wire_1 <= result_reg_18_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_18_2[29] == 1'b0) begin + result_wire_2 <= result_reg_18_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_18_3[29] == 1'b0) begin + result_wire_3 <= result_reg_18_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_18; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_13 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_15_0[29] == 1'b0) begin + result_wire_0 <= result_reg_15_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_15_1[29] == 1'b0) begin + result_wire_1 <= result_reg_15_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_15_2[29] == 1'b0) begin + result_wire_2 <= result_reg_15_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_15_3[29] == 1'b0) begin + result_wire_3 <= result_reg_15_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_15; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_12 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_16_0[29] == 1'b0) begin + result_wire_0 <= result_reg_16_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_16_1[29] == 1'b0) begin + result_wire_1 <= result_reg_16_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_16_2[29] == 1'b0) begin + result_wire_2 <= result_reg_16_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_16_3[29] == 1'b0) begin + result_wire_3 <= result_reg_16_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_16; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_19 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_9_0[29] == 1'b0) begin + result_wire_0 <= result_reg_9_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_9_1[29] == 1'b0) begin + result_wire_1 <= result_reg_9_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_9_2[29] == 1'b0) begin + result_wire_2 <= result_reg_9_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_9_3[29] == 1'b0) begin + result_wire_3 <= result_reg_9_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_9; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_18 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_10_0[29] == 1'b0) begin + result_wire_0 <= result_reg_10_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_10_1[29] == 1'b0) begin + result_wire_1 <= result_reg_10_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_10_2[29] == 1'b0) begin + result_wire_2 <= result_reg_10_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_10_3[29] == 1'b0) begin + result_wire_3 <= result_reg_10_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_10; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module winograd_transform_1 ( + input clk, + input i_valid, + input [15:0] i_result_0_0, + input [15:0] i_result_0_1, + input [15:0] i_result_0_2, + input [15:0] i_result_0_3, + input [15:0] i_result_1_0, + input [15:0] i_result_1_1, + input [15:0] i_result_1_2, + input [15:0] i_result_1_3, + input [15:0] i_result_2_0, + input [15:0] i_result_2_1, + input [15:0] i_result_2_2, + input [15:0] i_result_2_3, + input [15:0] i_result_3_0, + input [15:0] i_result_3_1, + input [15:0] i_result_3_2, + input [15:0] i_result_3_3, + input [15:0] i_result_4_0, + input [15:0] i_result_4_1, + input [15:0] i_result_4_2, + input [15:0] i_result_4_3, + input [15:0] i_result_5_0, + input [15:0] i_result_5_1, + input [15:0] i_result_5_2, + input [15:0] i_result_5_3, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output [15:0] o_feature_2, + output [15:0] o_feature_3, + output [15:0] o_feature_4, + output [15:0] o_feature_5, + output o_valid +); + +reg [15:0] input_buffer_0_0; +reg [19:0] output_buffer_0_0; +wire [19:0] rslt_buffer_0_0; +reg [15:0] input_buffer_0_1; +reg [19:0] output_buffer_0_1; +wire [19:0] rslt_buffer_0_1; +reg [15:0] input_buffer_0_2; +reg [19:0] output_buffer_0_2; +wire [19:0] rslt_buffer_0_2; +reg [15:0] input_buffer_0_3; +reg [19:0] output_buffer_0_3; +wire [19:0] rslt_buffer_0_3; +reg [15:0] input_buffer_0_4; +reg [19:0] output_buffer_0_4; +wire [19:0] rslt_buffer_0_4; +reg [15:0] input_buffer_0_5; +reg [19:0] output_buffer_0_5; +wire [19:0] rslt_buffer_0_5; +reg [15:0] input_buffer_1_0; +reg [19:0] output_buffer_1_0; +wire [19:0] rslt_buffer_1_0; +reg [15:0] input_buffer_1_1; +reg [19:0] output_buffer_1_1; +wire [19:0] rslt_buffer_1_1; +reg [15:0] input_buffer_1_2; +reg [19:0] output_buffer_1_2; +wire [19:0] rslt_buffer_1_2; +reg [15:0] input_buffer_1_3; +reg [19:0] output_buffer_1_3; +wire [19:0] rslt_buffer_1_3; +reg [15:0] input_buffer_1_4; +reg [19:0] output_buffer_1_4; +wire [19:0] rslt_buffer_1_4; +reg [15:0] input_buffer_1_5; +reg [19:0] output_buffer_1_5; +wire [19:0] rslt_buffer_1_5; +reg [15:0] input_buffer_2_0; +reg [19:0] output_buffer_2_0; +wire [19:0] rslt_buffer_2_0; +reg [15:0] input_buffer_2_1; +reg [19:0] output_buffer_2_1; +wire [19:0] rslt_buffer_2_1; +reg [15:0] input_buffer_2_2; +reg [19:0] output_buffer_2_2; +wire [19:0] rslt_buffer_2_2; +reg [15:0] input_buffer_2_3; +reg [19:0] output_buffer_2_3; +wire [19:0] rslt_buffer_2_3; +reg [15:0] input_buffer_2_4; +reg [19:0] output_buffer_2_4; +wire [19:0] rslt_buffer_2_4; +reg [15:0] input_buffer_2_5; +reg [19:0] output_buffer_2_5; +wire [19:0] rslt_buffer_2_5; +reg [15:0] input_buffer_3_0; +reg [19:0] output_buffer_3_0; +wire [19:0] rslt_buffer_3_0; +reg [15:0] input_buffer_3_1; +reg [19:0] output_buffer_3_1; +wire [19:0] rslt_buffer_3_1; +reg [15:0] input_buffer_3_2; +reg [19:0] output_buffer_3_2; +wire [19:0] rslt_buffer_3_2; +reg [15:0] input_buffer_3_3; +reg [19:0] output_buffer_3_3; +wire [19:0] rslt_buffer_3_3; +reg [15:0] input_buffer_3_4; +reg [19:0] output_buffer_3_4; +wire [19:0] rslt_buffer_3_4; +reg [15:0] input_buffer_3_5; +reg [19:0] output_buffer_3_5; +wire [19:0] rslt_buffer_3_5; +reg [15:0] input_buffer_4_0; +reg [19:0] output_buffer_4_0; +wire [19:0] rslt_buffer_4_0; +reg [15:0] input_buffer_4_1; +reg [19:0] output_buffer_4_1; +wire [19:0] rslt_buffer_4_1; +reg [15:0] input_buffer_4_2; +reg [19:0] output_buffer_4_2; +wire [19:0] rslt_buffer_4_2; +reg [15:0] input_buffer_4_3; +reg [19:0] output_buffer_4_3; +wire [19:0] rslt_buffer_4_3; +reg [15:0] input_buffer_4_4; +reg [19:0] output_buffer_4_4; +wire [19:0] rslt_buffer_4_4; +reg [15:0] input_buffer_4_5; +reg [19:0] output_buffer_4_5; +wire [19:0] rslt_buffer_4_5; +reg [15:0] input_buffer_5_0; +reg [19:0] output_buffer_5_0; +wire [19:0] rslt_buffer_5_0; +reg [15:0] input_buffer_5_1; +reg [19:0] output_buffer_5_1; +wire [19:0] rslt_buffer_5_1; +reg [15:0] input_buffer_5_2; +reg [19:0] output_buffer_5_2; +wire [19:0] rslt_buffer_5_2; +reg [15:0] input_buffer_5_3; +reg [19:0] output_buffer_5_3; +wire [19:0] rslt_buffer_5_3; +reg [15:0] input_buffer_5_4; +reg [19:0] output_buffer_5_4; +wire [19:0] rslt_buffer_5_4; +reg [15:0] input_buffer_5_5; +reg [19:0] output_buffer_5_5; +wire [19:0] rslt_buffer_5_5; +reg calculate, calculate_1, calculate_2, calculate_3; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg valid_12; +reg [2:0] input_buffer_count; +wire [15:0] dsp_out_1_0; +wire [15:0] dsp_out_1_1; +wire [15:0] dsp_out_1_2; +wire [15:0] dsp_out_1_3; +wire [15:0] dsp_out_1_4; +wire [15:0] dsp_out_1_5; +wire [15:0] dsp_out_1_6; +wire [15:0] dsp_out_1_7; +wire [15:0] dsp_out_1_8; +wire [15:0] dsp_out_1_9; +wire [15:0] dsp_out_1_10; +wire [15:0] dsp_out_1_11; +wire [15:0] dsp_out_2_0; +wire [15:0] dsp_out_2_1; +wire [15:0] dsp_out_2_2; +wire [15:0] dsp_out_2_3; +wire [15:0] dsp_out_2_4; +wire [15:0] dsp_out_2_5; +wire [15:0] dsp_out_2_6; +wire [15:0] dsp_out_2_7; +wire [15:0] dsp_out_3_0; +wire [15:0] dsp_out_3_1; +wire [15:0] dsp_out_3_2; +wire [15:0] dsp_out_3_3; +wire [15:0] dsp_out_3_4; +wire [15:0] dsp_out_3_5; +wire [15:0] dsp_out_3_6; +wire [15:0] dsp_out_3_7; +wire [15:0] dsp_out_4_0; +wire [15:0] dsp_out_4_1; +wire [15:0] dsp_out_4_2; +wire [15:0] dsp_out_4_3; +wire [15:0] dsp_out_4_4; +wire [15:0] dsp_out_4_5; +wire [15:0] dsp_out_4_6; +wire [15:0] dsp_out_4_7; +wire [15:0] dsp_out_5_0; +wire [15:0] dsp_out_5_1; +wire [15:0] dsp_out_5_2; +wire [15:0] dsp_out_5_3; +wire [15:0] dsp_out_5_4; +wire [15:0] dsp_out_5_5; +wire [15:0] dsp_out_5_6; +wire [15:0] dsp_out_5_7; +wire [15:0] dsp_out_6_0; +wire [15:0] dsp_out_6_1; +wire [15:0] dsp_out_6_2; +wire [15:0] dsp_out_6_3; +wire [15:0] dsp_out_6_4; +wire [15:0] dsp_out_6_5; +wire [15:0] dsp_out_6_6; +wire [15:0] dsp_out_6_7; +wire [15:0] dsp_out_6_8; +wire [15:0] dsp_out_6_9; +wire [15:0] dsp_out_6_10; +wire [15:0] dsp_out_6_11; +reg [15:0] feature_reg_0_0_0; +reg [15:0] feature_reg_0_0_1; +reg [15:0] feature_reg_0_1_0; +reg [15:0] feature_reg_0_1_1; +reg [15:0] feature_reg_0_2_0; +reg [15:0] feature_reg_0_2_1; +reg [15:0] feature_reg_0_3_0; +reg [15:0] feature_reg_0_3_1; +reg [15:0] feature_reg_0_4_0; +reg [15:0] feature_reg_0_4_1; +reg [15:0] feature_reg_0_5_0; +reg [15:0] feature_reg_0_5_1; +reg [15:0] feature_reg_1_0_0; +reg [15:0] feature_reg_1_0_1; +reg [15:0] feature_reg_1_1_0; +reg [15:0] feature_reg_1_1_1; +reg [15:0] feature_reg_1_2_0; +reg [15:0] feature_reg_1_2_1; +reg [15:0] feature_reg_1_3_0; +reg [15:0] feature_reg_1_3_1; +reg [15:0] feature_reg_1_4_0; +reg [15:0] feature_reg_1_4_1; +reg [15:0] feature_reg_1_5_0; +reg [15:0] feature_reg_1_5_1; +reg [15:0] feature_reg_2_0_0; +reg [15:0] feature_reg_2_0_1; +reg [15:0] feature_reg_2_1_0; +reg [15:0] feature_reg_2_1_1; +reg [15:0] feature_reg_2_2_0; +reg [15:0] feature_reg_2_2_1; +reg [15:0] feature_reg_2_3_0; +reg [15:0] feature_reg_2_3_1; +reg [15:0] feature_reg_2_4_0; +reg [15:0] feature_reg_2_4_1; +reg [15:0] feature_reg_2_5_0; +reg [15:0] feature_reg_2_5_1; +reg [15:0] feature_reg_3_0_0; +reg [15:0] feature_reg_3_0_1; +reg [15:0] feature_reg_3_1_0; +reg [15:0] feature_reg_3_1_1; +reg [15:0] feature_reg_3_2_0; +reg [15:0] feature_reg_3_2_1; +reg [15:0] feature_reg_3_3_0; +reg [15:0] feature_reg_3_3_1; +reg [15:0] feature_reg_3_4_0; +reg [15:0] feature_reg_3_4_1; +reg [15:0] feature_reg_3_5_0; +reg [15:0] feature_reg_3_5_1; +reg [15:0] feature_reg_4_0_0; +reg [15:0] feature_reg_4_0_1; +reg [15:0] feature_reg_4_1_0; +reg [15:0] feature_reg_4_1_1; +reg [15:0] feature_reg_4_2_0; +reg [15:0] feature_reg_4_2_1; +reg [15:0] feature_reg_4_3_0; +reg [15:0] feature_reg_4_3_1; +reg [15:0] feature_reg_4_4_0; +reg [15:0] feature_reg_4_4_1; +reg [15:0] feature_reg_4_5_0; +reg [15:0] feature_reg_4_5_1; +reg [15:0] feature_reg_5_0_0; +reg [15:0] feature_reg_5_0_1; +reg [15:0] feature_reg_5_1_0; +reg [15:0] feature_reg_5_1_1; +reg [15:0] feature_reg_5_2_0; +reg [15:0] feature_reg_5_2_1; +reg [15:0] feature_reg_5_3_0; +reg [15:0] feature_reg_5_3_1; +reg [15:0] feature_reg_5_4_0; +reg [15:0] feature_reg_5_4_1; +reg [15:0] feature_reg_5_5_0; +reg [15:0] feature_reg_5_5_1; + +always @ (posedge clk) begin + calculate_1 <= calculate; + calculate_2 <= calculate_1; + calculate_3 <= calculate_2; + //Valid pipeline + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + valid_12 <= valid_11; + if (i_valid) begin + input_buffer_count <= 0; + calculate <= 0; + end else begin + //Input buffering logic + if (input_buffer_count == 5) begin + calculate <= 1; + input_buffer_count <= 0; + end else begin + calculate <= 0; + input_buffer_count <= input_buffer_count + 1'b1; + end + input_buffer_5_0 <= i_result_0_1; + input_buffer_5_1 <= i_result_1_1; + input_buffer_5_2 <= i_result_2_1; + input_buffer_5_3 <= i_result_3_1; + input_buffer_5_4 <= i_result_4_1; + input_buffer_5_5 <= i_result_5_1; + end + input_buffer_0_0 <= input_buffer_1_0; + input_buffer_0_1 <= input_buffer_1_1; + input_buffer_0_2 <= input_buffer_1_2; + input_buffer_0_3 <= input_buffer_1_3; + input_buffer_0_4 <= input_buffer_1_4; + input_buffer_0_5 <= input_buffer_1_5; + input_buffer_1_0 <= input_buffer_2_0; + input_buffer_1_1 <= input_buffer_2_1; + input_buffer_1_2 <= input_buffer_2_2; + input_buffer_1_3 <= input_buffer_2_3; + input_buffer_1_4 <= input_buffer_2_4; + input_buffer_1_5 <= input_buffer_2_5; + input_buffer_2_0 <= input_buffer_3_0; + input_buffer_2_1 <= input_buffer_3_1; + input_buffer_2_2 <= input_buffer_3_2; + input_buffer_2_3 <= input_buffer_3_3; + input_buffer_2_4 <= input_buffer_3_4; + input_buffer_2_5 <= input_buffer_3_5; + input_buffer_3_0 <= input_buffer_4_0; + input_buffer_3_1 <= input_buffer_4_1; + input_buffer_3_2 <= input_buffer_4_2; + input_buffer_3_3 <= input_buffer_4_3; + input_buffer_3_4 <= input_buffer_4_4; + input_buffer_3_5 <= input_buffer_4_5; + input_buffer_4_0 <= input_buffer_5_0; + input_buffer_4_1 <= input_buffer_5_1; + input_buffer_4_2 <= input_buffer_5_2; + input_buffer_4_3 <= input_buffer_5_3; + input_buffer_4_4 <= input_buffer_5_4; + input_buffer_4_5 <= input_buffer_5_5; + //Pipelining to synchronize DSPs and non-DSPs + feature_reg_0_0_0 <= input_buffer_0_0; + feature_reg_0_1_0 <= input_buffer_0_1; + feature_reg_0_2_0 <= input_buffer_0_2; + feature_reg_0_3_0 <= input_buffer_0_3; + feature_reg_0_4_0 <= input_buffer_0_4; + feature_reg_0_5_0 <= input_buffer_0_5; + feature_reg_1_0_0 <= input_buffer_1_0; + feature_reg_1_1_0 <= input_buffer_1_1; + feature_reg_1_2_0 <= input_buffer_1_2; + feature_reg_1_3_0 <= input_buffer_1_3; + feature_reg_1_4_0 <= input_buffer_1_4; + feature_reg_1_5_0 <= input_buffer_1_5; + feature_reg_2_0_0 <= input_buffer_2_0; + feature_reg_2_1_0 <= input_buffer_2_1; + feature_reg_2_2_0 <= input_buffer_2_2; + feature_reg_2_3_0 <= input_buffer_2_3; + feature_reg_2_4_0 <= input_buffer_2_4; + feature_reg_2_5_0 <= input_buffer_2_5; + feature_reg_3_0_0 <= input_buffer_3_0; + feature_reg_3_1_0 <= input_buffer_3_1; + feature_reg_3_2_0 <= input_buffer_3_2; + feature_reg_3_3_0 <= input_buffer_3_3; + feature_reg_3_4_0 <= input_buffer_3_4; + feature_reg_3_5_0 <= input_buffer_3_5; + feature_reg_4_0_0 <= input_buffer_4_0; + feature_reg_4_1_0 <= input_buffer_4_1; + feature_reg_4_2_0 <= input_buffer_4_2; + feature_reg_4_3_0 <= input_buffer_4_3; + feature_reg_4_4_0 <= input_buffer_4_4; + feature_reg_4_5_0 <= input_buffer_4_5; + feature_reg_5_0_0 <= input_buffer_5_0; + feature_reg_5_1_0 <= input_buffer_5_1; + feature_reg_5_2_0 <= input_buffer_5_2; + feature_reg_5_3_0 <= input_buffer_5_3; + feature_reg_5_4_0 <= input_buffer_5_4; + feature_reg_5_5_0 <= input_buffer_5_5; + feature_reg_0_0_1 <= feature_reg_0_0_0; + feature_reg_0_1_1 <= feature_reg_0_1_0; + feature_reg_0_2_1 <= feature_reg_0_2_0; + feature_reg_0_3_1 <= feature_reg_0_3_0; + feature_reg_0_4_1 <= feature_reg_0_4_0; + feature_reg_0_5_1 <= feature_reg_0_5_0; + feature_reg_1_0_1 <= feature_reg_1_0_0; + feature_reg_1_1_1 <= feature_reg_1_1_0; + feature_reg_1_2_1 <= feature_reg_1_2_0; + feature_reg_1_3_1 <= feature_reg_1_3_0; + feature_reg_1_4_1 <= feature_reg_1_4_0; + feature_reg_1_5_1 <= feature_reg_1_5_0; + feature_reg_2_0_1 <= feature_reg_2_0_0; + feature_reg_2_1_1 <= feature_reg_2_1_0; + feature_reg_2_2_1 <= feature_reg_2_2_0; + feature_reg_2_3_1 <= feature_reg_2_3_0; + feature_reg_2_4_1 <= feature_reg_2_4_0; + feature_reg_2_5_1 <= feature_reg_2_5_0; + feature_reg_3_0_1 <= feature_reg_3_0_0; + feature_reg_3_1_1 <= feature_reg_3_1_0; + feature_reg_3_2_1 <= feature_reg_3_2_0; + feature_reg_3_3_1 <= feature_reg_3_3_0; + feature_reg_3_4_1 <= feature_reg_3_4_0; + feature_reg_3_5_1 <= feature_reg_3_5_0; + feature_reg_4_0_1 <= feature_reg_4_0_0; + feature_reg_4_1_1 <= feature_reg_4_1_0; + feature_reg_4_2_1 <= feature_reg_4_2_0; + feature_reg_4_3_1 <= feature_reg_4_3_0; + feature_reg_4_4_1 <= feature_reg_4_4_0; + feature_reg_4_5_1 <= feature_reg_4_5_0; + feature_reg_5_0_1 <= feature_reg_5_0_0; + feature_reg_5_1_1 <= feature_reg_5_1_0; + feature_reg_5_2_1 <= feature_reg_5_2_0; + feature_reg_5_3_1 <= feature_reg_5_3_0; + feature_reg_5_4_1 <= feature_reg_5_4_0; + feature_reg_5_5_1 <= feature_reg_5_5_0; + //Output Serializing logic + if (calculate_3) begin + output_buffer_0_0 <= rslt_buffer_0_0; + output_buffer_1_0 <= rslt_buffer_0_1; + output_buffer_2_0 <= rslt_buffer_0_2; + output_buffer_3_0 <= rslt_buffer_0_3; + output_buffer_4_0 <= rslt_buffer_0_4; + output_buffer_5_0 <= rslt_buffer_0_5; + output_buffer_0_1 <= rslt_buffer_1_0; + output_buffer_1_1 <= rslt_buffer_1_1; + output_buffer_2_1 <= rslt_buffer_1_2; + output_buffer_3_1 <= rslt_buffer_1_3; + output_buffer_4_1 <= rslt_buffer_1_4; + output_buffer_5_1 <= rslt_buffer_1_5; + output_buffer_0_2 <= rslt_buffer_2_0; + output_buffer_1_2 <= rslt_buffer_2_1; + output_buffer_2_2 <= rslt_buffer_2_2; + output_buffer_3_2 <= rslt_buffer_2_3; + output_buffer_4_2 <= rslt_buffer_2_4; + output_buffer_5_2 <= rslt_buffer_2_5; + output_buffer_0_3 <= rslt_buffer_3_0; + output_buffer_1_3 <= rslt_buffer_3_1; + output_buffer_2_3 <= rslt_buffer_3_2; + output_buffer_3_3 <= rslt_buffer_3_3; + output_buffer_4_3 <= rslt_buffer_3_4; + output_buffer_5_3 <= rslt_buffer_3_5; + output_buffer_0_4 <= rslt_buffer_4_0; + output_buffer_1_4 <= rslt_buffer_4_1; + output_buffer_2_4 <= rslt_buffer_4_2; + output_buffer_3_4 <= rslt_buffer_4_3; + output_buffer_4_4 <= rslt_buffer_4_4; + output_buffer_5_4 <= rslt_buffer_4_5; + output_buffer_0_5 <= rslt_buffer_5_0; + output_buffer_1_5 <= rslt_buffer_5_1; + output_buffer_2_5 <= rslt_buffer_5_2; + output_buffer_3_5 <= rslt_buffer_5_3; + output_buffer_4_5 <= rslt_buffer_5_4; + output_buffer_5_5 <= rslt_buffer_5_5; + end else begin + output_buffer_0_0 <= output_buffer_0_1; + output_buffer_0_1 <= output_buffer_0_2; + output_buffer_0_2 <= output_buffer_0_3; + output_buffer_0_3 <= output_buffer_0_4; + output_buffer_0_4 <= output_buffer_0_5; + output_buffer_1_0 <= output_buffer_1_1; + output_buffer_1_1 <= output_buffer_1_2; + output_buffer_1_2 <= output_buffer_1_3; + output_buffer_1_3 <= output_buffer_1_4; + output_buffer_1_4 <= output_buffer_1_5; + output_buffer_2_0 <= output_buffer_2_1; + output_buffer_2_1 <= output_buffer_2_2; + output_buffer_2_2 <= output_buffer_2_3; + output_buffer_2_3 <= output_buffer_2_4; + output_buffer_2_4 <= output_buffer_2_5; + output_buffer_3_0 <= output_buffer_3_1; + output_buffer_3_1 <= output_buffer_3_2; + output_buffer_3_2 <= output_buffer_3_3; + output_buffer_3_3 <= output_buffer_3_4; + output_buffer_3_4 <= output_buffer_3_5; + output_buffer_4_0 <= output_buffer_4_1; + output_buffer_4_1 <= output_buffer_4_2; + output_buffer_4_2 <= output_buffer_4_3; + output_buffer_4_3 <= output_buffer_4_4; + output_buffer_4_4 <= output_buffer_4_5; + output_buffer_5_0 <= output_buffer_5_1; + output_buffer_5_1 <= output_buffer_5_2; + output_buffer_5_2 <= output_buffer_5_3; + output_buffer_5_3 <= output_buffer_5_4; + output_buffer_5_4 <= output_buffer_5_5; + end +end + +////// FIRST COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD00 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_2), + .by(input_buffer_2_0), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_1_0), + .resultb(dsp_out_1_1) +); + +winograd_dsp_16 winograd_dsp_16_WD10 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_2_4), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_1_2), + .resultb(dsp_out_1_3) +); + +winograd_dsp_16 winograd_dsp_16_WD20 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_2), + .by(input_buffer_1_0), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_1_4), + .resultb(dsp_out_1_5) +); + +winograd_dsp_16 winograd_dsp_16_WD30 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_1_6), + .resultb(dsp_out_1_7) +); + +winograd_dsp_16 winograd_dsp_16_WD40 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_0), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_1_8), + .resultb(dsp_out_1_9) +); + +winograd_dsp_16 winograd_dsp_16_WD50 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_4), + .by(input_buffer_5_2), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_1_10), + .resultb(dsp_out_1_11) +); + +////// SECOND COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD01 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_0), + .resultb(dsp_out_2_1) +); + +winograd_dsp_16 winograd_dsp_16_WD11 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_2), + .resultb(dsp_out_2_3) +); + +winograd_dsp_16 winograd_dsp_16_WD21 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_4), + .resultb(dsp_out_2_5) +); + +winograd_dsp_16 winograd_dsp_16_WD31 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_6), + .resultb(dsp_out_2_7) +); + +////// THIRD COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD02 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_0), + .resultb(dsp_out_3_1) +); + +winograd_dsp_16 winograd_dsp_16_WD12 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_2), + .resultb(dsp_out_3_3) +); + +winograd_dsp_16 winograd_dsp_16_WD22 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_4), + .resultb(dsp_out_3_5) +); + +winograd_dsp_16 winograd_dsp_16_WD32 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_6), + .resultb(dsp_out_3_7) +); + +////// FOURTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD03 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_0), + .resultb(dsp_out_4_1) +); + +winograd_dsp_16 winograd_dsp_16_WD13 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_2), + .resultb(dsp_out_4_3) +); + +winograd_dsp_16 winograd_dsp_16_WD23 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_4), + .resultb(dsp_out_4_5) +); + +winograd_dsp_16 winograd_dsp_16_WD33 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_6), + .resultb(dsp_out_4_7) +); + +////// FIFTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD04 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_0), + .resultb(dsp_out_5_1) +); + +winograd_dsp_16 winograd_dsp_16_WD14 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_2), + .resultb(dsp_out_5_3) +); + +winograd_dsp_16 winograd_dsp_16_WD24 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_4), + .resultb(dsp_out_5_5) +); + +winograd_dsp_16 winograd_dsp_16_WD34 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_6), + .resultb(dsp_out_5_7) +); + +////// SIXTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD05 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_3), + .by(input_buffer_2_1), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_6_0), + .resultb(dsp_out_6_1) +); + +winograd_dsp_16 winograd_dsp_16_WD15 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_5), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_6_2), + .resultb(dsp_out_6_3) +); + +winograd_dsp_16 winograd_dsp_16_WD25 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_3), + .by(input_buffer_1_3), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_6_4), + .resultb(dsp_out_6_5) +); + +winograd_dsp_16 winograd_dsp_16_WD35 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_3_3), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_6_6), + .resultb(dsp_out_6_7) +); + +winograd_dsp_16 winograd_dsp_16_WD45 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_3), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_6_8), + .resultb(dsp_out_6_9) +); + +winograd_dsp_16 winograd_dsp_16_WD55 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_5), + .by(input_buffer_5_3), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_6_10), + .resultb(dsp_out_6_11) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA00 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_0_1[11:0], 4'b0000}), + .data1x(dsp_out_1_0), + .data2x({feature_reg_0_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_1), + .data4x(dsp_out_1_2), + .data5x(dsp_out_1_3), + .data6x({feature_reg_4_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_4), + .data8x(feature_reg_4_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_0) +); + +wire [15:0] f1, f2, f3, f4; +assign f1 = -{feature_reg_1_0_1[11:0], 4'b0000}; +assign f2 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f3 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f4 = -{feature_reg_2_4_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA10 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_1_5), + .data1x(f1), + .data2x(f2), + .data3x(f3), + .data4x(dsp_out_1_6), + .data5x(f4), + .data6x({feature_reg_3_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_7), + .data8x(feature_reg_3_4_1), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_0) +); + +wire [15:0] f5, f6, f7, f8, f9, f10; +assign f5 = -dsp_out_1_5; +assign f6 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f7 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f8 = -{feature_reg_3_0_1[13:0], 2'b00}; +assign f9 = -dsp_out_1_7; +assign f10 = -feature_reg_3_4_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA20 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f5), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(f6), + .data4x(dsp_out_1_6), + .data5x(f7), + .data6x(f8), + .data7x(f9), + .data8x(f10), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_0) +); + +wire [15:0] f11, f12, f13, f14, f15, f16, f17; +assign f11 = -{feature_reg_1_0_1[12:0], 3'b000}; +assign f12 = -{feature_reg_1_4_1[14:0], 1'b0}; +assign f13 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f14 = -feature_reg_2_4_1; +assign f15 = dsp_out_1_5 >>> 1; +assign f16 = dsp_out_1_6 >>> 2; +assign f17 = dsp_out_1_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA30 ( + .clock(clk), + .clken(calculate_2), + .data0x(f15), + .data1x(f11), + .data2x(f12), + .data3x(f13), + .data4x(f16), + .data5x(f14), + .data6x({feature_reg_3_0_1[12:0], 3'b000}), + .data7x(f17), + .data8x({feature_reg_3_4_1[14:0], 1'b0}), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_0) +); + +wire [15:0] f18, f19, f20, f21, f22, f23, f23b; +assign f18 = -(dsp_out_1_5 >>> 1); +assign f19 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f20 = -feature_reg_2_4_1; +assign f21 = -{feature_reg_3_0_1[12:0], 3'b000}; +assign f22 = -(dsp_out_1_7 <<< 1); +assign f23 = -{feature_reg_3_4_1[14:0], 1'b0}; +assign f23b = dsp_out_1_6 >>> 2; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA40 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[12:0], 3'b000}), + .data1x(f18), + .data2x({feature_reg_1_4_1[14:0], 1'b0}), + .data3x(f19), + .data4x(f23b), + .data5x(f20), + .data6x(f21), + .data7x(f22), + .data8x(f23), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_0) +); + +wire [15:0] f24; +assign f24 = -dsp_out_1_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA50 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f24), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_8), + .data4x(dsp_out_1_9), + .data5x(dsp_out_1_10), + .data6x({feature_reg_5_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_11), + .data8x(feature_reg_5_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_0) +); + +wire [15:0] f25, f26, f27, f28; +assign f25 = -{feature_reg_0_2_1[11:0], 4'b0000}; +assign f26 = -{feature_reg_0_1_1[11:0], 4'b0000}; +assign f27 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f28 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA01 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[13:0], 2'b00}), + .data1x(f25), + .data2x(f26), + .data3x({feature_reg_0_4_1[13:0], 2'b00}), + .data4x(dsp_out_2_0), + .data5x(dsp_out_2_1), + .data6x(dsp_out_2_2), + .data7x(dsp_out_2_3), + .data8x(f27), + .data9x(f28), + .data10x(feature_reg_4_3_1), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_1) +); + +wire [15:0] f29, f30, f31, f32, f33, f34, f35, f36; +assign f29 = -{feature_reg_1_3_1[13:0], 2'b00}; +assign f30 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f31 = -{feature_reg_2_3_1[13:0], 2'b00}; +assign f32 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f33 = -{feature_reg_3_1_1[13:0], 2'b00}; +assign f34 = -{feature_reg_3_2_1[13:0], 2'b00}; +assign f35 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f36 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA11 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0], 4'b0000}), + .data1x({feature_reg_1_2_1[11:0], 4'b0000}), + .data2x(f29), + .data3x(f30), + .data4x({feature_reg_2_1_1[11:0], 4'b0000}), + .data5x({feature_reg_2_2_1[11:0], 4'b0000}), + .data6x(f31), + .data7x(f32), + .data8x(f33), + .data9x(f34), + .data10x(feature_reg_3_3_1), + .data11x(feature_reg_3_4_1), + .data12x(f35), + .data13x(f36), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_1) +); + +wire [15:0] f37, f38, f39, f40, f41, f42, f43, f44; +assign f37 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f38 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f39 = -{feature_reg_2_3_1[13:0],2'b00}; +assign f40 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f41 = -feature_reg_3_3_1; +assign f42 = -feature_reg_3_4_1; +assign f43 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f44 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA21 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f37), + .data2x(f38), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[11:0],4'b0000}), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x(f39), + .data7x(f40), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(f41), + .data11x(f42), + .data12x(f43), + .data13x(f44), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_1) +); + +wire [15:0] f45, f46, f47, f48, f49, f50, f51, f52; +assign f45 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f46 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f47 = -feature_reg_2_3_1; +assign f48 = -feature_reg_2_4_1; +assign f49 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f50 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f51 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f52 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA31 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[12:0],3'b000}), + .data2x(f45), + .data3x(f46), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f47), + .data7x(f48), + .data8x(f49), + .data9x(f50), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f51), + .data13x(f52), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_1) +); + +wire [15:0] f53, f54, f55, f56, f57, f58, f59, f60; +assign f53 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f54 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f55 = -feature_reg_2_3_1; +assign f56 = -feature_reg_2_4_1; +assign f57 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f58 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f59 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f60 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA41 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[14:0],1'b0}), + .data1x(f53), + .data2x(f54), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f55), + .data7x(f56), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x(f57), + .data11x(f58), + .data12x(f59), + .data13x(f60), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_1) +); + +wire [15:0] f61, f62, f63, f64; +assign f61 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f62 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f63 = -{feature_reg_5_1_1[13:0],2'b00}; +assign f64 = -{feature_reg_5_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA51 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f61), + .data2x(f62), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_2_4), + .data5x(dsp_out_2_5), + .data6x(dsp_out_2_6), + .data7x(dsp_out_2_7), + .data8x(f63), + .data9x(f64), + .data10x(feature_reg_5_3_1), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_1) +); + +wire [15:0] f65, f66, f67, f68; +assign f65 = -{feature_reg_0_2_1[11:0],4'b0000}; +assign f66 = -{feature_reg_0_3_1[13:0],2'b00}; +assign f67 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f68 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA02 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(f65), + .data2x(f66), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_3_0), + .data5x(dsp_out_3_1), + .data6x(dsp_out_3_2), + .data7x(dsp_out_3_3), + .data8x({feature_reg_4_1_1[13:0],2'b00}), + .data9x(f67), + .data10x(f68), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_2) +); + +wire [15:0] f69, f70, f71, f72, f73, f74, f75, f76; +assign f69 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f70 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f71 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f72 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f73 = -{feature_reg_3_2_1[13:0],2'b00}; +assign f74 = -feature_reg_3_3_1; +assign f75 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f76 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA12 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[11:0],4'b0000}), + .data1x(f69), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f70), + .data4x(f71), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f72), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f73), + .data10x(f74), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f75), + .data14x(f76), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_2) +); + +wire [15:0] f77, f78, f79, f80, f81, f82, f83, f84; +assign f77 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f78 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f79 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f80 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f81 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f82 = -feature_reg_3_4_1; +assign f83 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f84 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA22 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f77), + .data2x(f78), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f79), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f80), + .data8x(f81), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(feature_reg_3_3_1), + .data11x(f82), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f83), + .data14x(f84), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_2) +); + +wire [15:0] f85, f86, f87, f88, f89, f90, f91, f92; +assign f85 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f86 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f87 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f88 = -feature_reg_2_4_1; +assign f89 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f90 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f91 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f92 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA32 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[12:0],3'b000}), + .data1x(f85), + .data2x({feature_reg_1_3_1[14:0],1'b0}), + .data3x(f86), + .data4x(f87), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f88), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x(f89), + .data10x(f90), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f91), + .data14x(f92), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_2) +); + +wire [15:0] f93, f94, f95, f96, f97, f98, f99, f100; +assign f93 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f94 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f95 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f96 = -feature_reg_2_4_1; +assign f97 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f98 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f99 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f100 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA42 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f93), + .data2x(f94), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f95), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f96), + .data8x(f97), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f98), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f99), + .data14x(f100), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_2) +); + +wire [15:0] f101, f102, f103, f104; +assign f101 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f102 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f103 = -{feature_reg_5_2_1[13:0],2'b00}; +assign f104 = -feature_reg_5_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA52 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f101), + .data2x(f102), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_3_4), + .data5x(dsp_out_3_5), + .data6x(dsp_out_3_6), + .data7x(dsp_out_3_7), + .data8x({feature_reg_5_1_1[13:0],2'b00}), + .data9x(f103), + .data10x(f104), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_2) +); + +wire [15:0] f105, f106, f107, f108; +assign f105 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f106 = -{feature_reg_0_1_1[12:0],3'b000}; +assign f107 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f108 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA03 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[12:0],3'b000}), + .data1x(f105), + .data2x(f106), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_4_0), + .data5x(dsp_out_4_1), + .data6x(dsp_out_4_2), + .data7x(dsp_out_4_3), + .data8x(f107), + .data9x(f108), + .data10x({feature_reg_4_3_1[14:0],1'b0}), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_3) +); + +wire [15:0] f109, f110, f111, f112, f113, f114, f115, f116; +assign f109 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f110 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f111 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f112 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f113 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f114 = -feature_reg_3_2_1; +assign f115 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f116 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA13 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[13:0],2'b00}), + .data2x(f109), + .data3x(f110), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f111), + .data7x(f112), + .data8x(f113), + .data9x(f114), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(feature_reg_3_4_1), + .data12x(f115), + .data13x(f116), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_3) +); + +wire [15:0] f117, f118, f119, f120, f121, f122, f123, f124; +assign f117 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f118 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f119 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f120 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f121 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f122 = -feature_reg_3_4_1; +assign f123 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f124 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA23 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f117), + .data2x(f118), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f119), + .data7x(f120), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(feature_reg_3_2_1), + .data10x(f121), + .data11x(f122), + .data12x(f123), + .data13x(f124), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_3) +); + +wire [15:0] f125, f126, f127, f128, f129, f130, f131, f132; +assign f125 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f126 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f127 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f128 = -feature_reg_2_4_1; +assign f129 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f130 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f131 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f132 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA33 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x({feature_reg_1_2_1[14:0],1'b0}), + .data2x(f125), + .data3x(f126), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f127), + .data7x(f128), + .data8x(f129), + .data9x(f130), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f131), + .data13x(f132), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_3) +); + +wire [15:0] f133, f134, f135, f136, f137, f138, f139, f140; +assign f133 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f134 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f135 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f136 = -feature_reg_2_4_1; +assign f137 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f138 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f139 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f140 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA43 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f133), + .data2x(f134), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f135), + .data7x(f136), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x(f137), + .data11x(f138), + .data12x(f139), + .data13x(f140), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_3) +); + +wire [15:0] f141, f142, f143, f144; +assign f141 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f142 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f143 = -{feature_reg_5_1_1[14:0],1'b0}; +assign f144 = -feature_reg_5_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA53 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f141), + .data2x(f142), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_4_4), + .data5x(dsp_out_4_5), + .data6x(dsp_out_4_6), + .data7x(dsp_out_4_7), + .data8x(f143), + .data9x(f144), + .data10x({feature_reg_5_3_1[14:0],1'b0}), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_3) +); + +wire [15:0] f145, f146, f147, f148; +assign f145 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f146 = -{feature_reg_0_3_1[12:0],3'b000}; +assign f147 = -feature_reg_4_2_1; +assign f148 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA04 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[12:0],3'b000}), + .data1x(f145), + .data2x(f146), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_5_0), + .data5x(dsp_out_5_1), + .data6x(dsp_out_5_2), + .data7x(dsp_out_5_3), + .data8x({feature_reg_4_1_1[14:0],1'b0}), + .data9x(f147), + .data10x(f148), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_4) +); + +wire [15:0] f149, f150, f151, f152, f153, f154, f155, f156; +assign f149 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f150 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f151 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f152 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f153 = -feature_reg_3_2_1; +assign f154 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f155 = -feature_reg_4_2_1; +assign f156 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA14 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[13:0],2'b00}), + .data1x(f149), + .data2x({feature_reg_1_3_1[12:0],3'b000}), + .data3x(f150), + .data4x(f151), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f152), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(f153), + .data10x(f154), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f155), + .data14x(f156), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_4) +); + +wire [15:0] f157, f158, f159, f160, f161, f162, f163, f164; +assign f157 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f158 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f159 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f160 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f161 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f162 = -feature_reg_3_4_1; +assign f163 = -feature_reg_4_2_1; +assign f164 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA24 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f157), + .data2x(f158), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f159), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f160), + .data8x(f161), + .data9x(feature_reg_3_2_1), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f162), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f163), + .data14x(f164), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_4) +); + +wire [15:0] f165, f166, f167, f168, f169, f170, f171, f172; +assign f165 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f166 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f167 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f168 = -feature_reg_2_4_1; +assign f169 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f170 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f171 = -feature_reg_4_2_1; +assign f172 = -{feature_reg_4_1_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA34 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[14:0],1'b0}), + .data1x(f165), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f166), + .data4x(f167), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f168), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f169), + .data10x(f170), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f171), + .data14x(f172), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_4) +); + +wire [15:0] f173, f174, f175, f176, f177, f178, f179, f180; +assign f173 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f174 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f175 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f176 = -feature_reg_2_4_1; +assign f177 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f178 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f179 = -feature_reg_4_2_1; +assign f180 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA44 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x(f173), + .data2x(f174), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f175), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f176), + .data8x(f177), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x(f178), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f179), + .data14x(f180), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_4) +); + +wire [15:0] f181, f182, f183, f184; +assign f181 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f182 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f183 = -feature_reg_5_2_1; +assign f184 = -{feature_reg_5_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA54 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f181), + .data2x(f182), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_5_4), + .data5x(dsp_out_5_5), + .data6x(dsp_out_5_6), + .data7x(dsp_out_5_7), + .data8x({feature_reg_5_1_1[14:0],1'b0}), + .data9x(f183), + .data10x(f184), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_4) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA05 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(dsp_out_6_0), + .data2x({feature_reg_0_5_1[13:0],2'b00}), + .data3x(dsp_out_6_1), + .data4x(dsp_out_6_2), + .data5x(dsp_out_6_3), + .data6x({feature_reg_4_1_1[13:0],2'b00}), + .data7x(dsp_out_6_4), + .data8x(feature_reg_4_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_5) +); + +wire [15:0] f185, f186, f187, f188; +assign f185 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f186 = -{feature_reg_1_5_1[13:0],2'b00}; +assign f187 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f188 = -{feature_reg_2_5_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA15 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_6_5), + .data1x(f185), + .data2x(f186), + .data3x(f187), + .data4x(dsp_out_6_6), + .data5x(f188), + .data6x({feature_reg_3_1_1[13:0],2'b00}), + .data7x(dsp_out_6_7), + .data8x(feature_reg_3_5_1), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_5) +); + +wire [15:0] f189, f190, f191, f192, f193, f194; +assign f189 = -dsp_out_6_5; +assign f190 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f191 = -{feature_reg_2_5_1[13:0],2'b00}; +assign f192 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f193 = -dsp_out_6_7; +assign f194 = -feature_reg_3_5_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA25 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f189), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(f190), + .data4x(dsp_out_6_6), + .data5x(f191), + .data6x(f192), + .data7x(f193), + .data8x(f194), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_5) +); + +wire [15:0] f195, f196, f197, f198, f199, f200, f201; +assign f195 = dsp_out_6_5 >>> 1; +assign f196 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f197 = -{feature_reg_1_5_1[14:0],1'b0}; +assign f198 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f199 = dsp_out_6_6 >>> 2; +assign f200 = -feature_reg_2_5_1; +assign f201 = dsp_out_6_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA35 ( + .clock(clk), + .clken(calculate_2), + .data0x(f195), + .data1x(f196), + .data2x(f197), + .data3x(f198), + .data4x(f199), + .data5x(f200), + .data6x({feature_reg_3_1_1[12:0],3'b000}), + .data7x(f201), + .data8x({feature_reg_3_5_1[14:0],1'b0}), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_5) +); + +wire [15:0] f202, f203, f204, f205, f206, f207, f208; +assign f202 = -(dsp_out_6_5 >>> 1); +assign f203 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f204 = dsp_out_6_6 >>> 2; +assign f205 = -feature_reg_2_5_1; +assign f206 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f207 = -(dsp_out_6_7 <<< 1); +assign f208 = -{feature_reg_3_5_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA45 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f202), + .data2x({feature_reg_1_5_1[14:0],1'b0}), + .data3x(f203), + .data4x(f204), + .data5x(f205), + .data6x(f206), + .data7x(f207), + .data8x(f208), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_5) +); + +wire [15:0] f209; +assign f209 = -dsp_out_6_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA55 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f209), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(dsp_out_6_8), + .data4x(dsp_out_6_9), + .data5x(dsp_out_6_10), + .data6x({feature_reg_5_1_1[13:0],2'b00}), + .data7x(dsp_out_6_11), + .data8x(feature_reg_5_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_5) +); + +assign o_feature_0 = output_buffer_0_0[15:0]; +assign o_feature_1 = output_buffer_1_0[15:0]; +assign o_feature_2 = output_buffer_2_0[15:0]; +assign o_feature_3 = output_buffer_3_0[15:0]; +assign o_feature_4 = output_buffer_4_0[15:0]; +assign o_feature_5 = output_buffer_5_0[15:0]; +assign o_valid = valid_9; + +endmodule + +module winograd_adder_16_20_4 ( + input clken, + input clock, + input [15:0] data0x, + input [15:0] data1x, + input [15:0] data2x, + input [15:0] data3x, + input [15:0] data4x, + input [15:0] data5x, + input [15:0] data6x, + input [15:0] data7x, + input [15:0] data8x, + input [15:0] data9x, + input [15:0] data10x, + input [15:0] data11x, + input [15:0] data12x, + input [15:0] data13x, + input [15:0] data14x, + input [15:0] data15x, + output [19:0] result +); + +reg [19:0] pipeline_0_0; +reg [19:0] pipeline_0_1; +reg [19:0] pipeline_0_2; +reg [19:0] pipeline_0_3; +reg [19:0] pipeline_0_4; +reg [19:0] pipeline_0_5; +reg [19:0] pipeline_0_6; +reg [19:0] pipeline_0_7; +reg [19:0] pipeline_1_0; +reg [19:0] pipeline_1_1; +reg [19:0] pipeline_1_2; +reg [19:0] pipeline_1_3; +reg [19:0] pipeline_2_0; +reg [19:0] pipeline_2_1; +reg [19:0] pipeline_3_0; + +always @ (posedge clock) begin + pipeline_0_0 <= data0x + data1x; + pipeline_0_1 <= data2x + data3x; + pipeline_0_2 <= data4x + data5x; + pipeline_0_3 <= data6x + data7x; + pipeline_0_4 <= data8x + data9x; + pipeline_0_5 <= data10x + data11x; + pipeline_0_6 <= data12x + data13x; + pipeline_0_7 <= data14x + data15x; + pipeline_1_0 <= pipeline_0_0 + pipeline_0_1; + pipeline_1_1 <= pipeline_0_2 + pipeline_0_3; + pipeline_1_2 <= pipeline_0_4 + pipeline_0_5; + pipeline_1_3 <= pipeline_0_6 + pipeline_0_7; + pipeline_2_0 <= pipeline_1_0 + pipeline_1_1; + pipeline_2_1 <= pipeline_1_2 + pipeline_1_3; + pipeline_3_0 <= pipeline_2_0 + pipeline_2_1; +end + +assign result = pipeline_3_0; + +endmodule + +module winograd_dsp_16 ( + input clk, + input ena, + input aclr, + input [15:0] ay, + input [15:0] by, + input [2:0] coefsela, + input [2:0] coefselb, + output [15:0] resulta, + output [15:0] resultb +); + +reg [15:0] coefa, coefb, ay_reg, by_reg, resa_reg, resb_reg; +assign resulta = resa_reg; +assign resultb = resb_reg; + +always @ (posedge clk) begin + if (aclr) begin + coefa <= 0; + coefb <= 0; + ay_reg <= 0; + by_reg <= 0; + resa_reg <= 0; + resb_reg <= 0; + end else begin + ay_reg <= ay; + by_reg <= by; + if (coefsela == 0) begin + coefa <= 5; + end else if (coefsela == 1) begin + coefa <= -5; + end else if (coefsela == 2) begin + coefa <= 10; + end else if (coefsela == 3) begin + coefa <= -10; + end else if (coefsela == 4) begin + coefa <= 20; + end else if (coefsela == 5) begin + coefa <= -20; + end else if (coefsela == 6) begin + coefa <= 25; + end else if (coefsela == 7) begin + coefa <= -25; + end else begin + coefa <= 0; + end + if (coefselb == 0) begin + coefb <= 5; + end else if (coefselb == 1) begin + coefb <= -5; + end else if (coefselb == 2) begin + coefb <= 10; + end else if (coefselb == 3) begin + coefb <= -10; + end else if (coefselb == 4) begin + coefb <= 20; + end else if (coefselb == 5) begin + coefb <= -20; + end else if (coefselb == 6) begin + coefb <= 25; + end else if (coefselb == 7) begin + coefb <= -25; + end else begin + coefb <= 0; + end + resa_reg <= ay_reg * coefa; + resb_reg <= by_reg * coefb; + end +end + +endmodule + +module winograd_transform_0 ( + input clk, + input i_valid, + input [15:0] i_result_0_0, + input [15:0] i_result_0_1, + input [15:0] i_result_0_2, + input [15:0] i_result_0_3, + input [15:0] i_result_1_0, + input [15:0] i_result_1_1, + input [15:0] i_result_1_2, + input [15:0] i_result_1_3, + input [15:0] i_result_2_0, + input [15:0] i_result_2_1, + input [15:0] i_result_2_2, + input [15:0] i_result_2_3, + input [15:0] i_result_3_0, + input [15:0] i_result_3_1, + input [15:0] i_result_3_2, + input [15:0] i_result_3_3, + input [15:0] i_result_4_0, + input [15:0] i_result_4_1, + input [15:0] i_result_4_2, + input [15:0] i_result_4_3, + input [15:0] i_result_5_0, + input [15:0] i_result_5_1, + input [15:0] i_result_5_2, + input [15:0] i_result_5_3, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output [15:0] o_feature_2, + output [15:0] o_feature_3, + output [15:0] o_feature_4, + output [15:0] o_feature_5, + output o_valid +); + +reg [15:0] input_buffer_0_0; +reg [19:0] output_buffer_0_0; +wire [19:0] rslt_buffer_0_0; +reg [15:0] input_buffer_0_1; +reg [19:0] output_buffer_0_1; +wire [19:0] rslt_buffer_0_1; +reg [15:0] input_buffer_0_2; +reg [19:0] output_buffer_0_2; +wire [19:0] rslt_buffer_0_2; +reg [15:0] input_buffer_0_3; +reg [19:0] output_buffer_0_3; +wire [19:0] rslt_buffer_0_3; +reg [15:0] input_buffer_0_4; +reg [19:0] output_buffer_0_4; +wire [19:0] rslt_buffer_0_4; +reg [15:0] input_buffer_0_5; +reg [19:0] output_buffer_0_5; +wire [19:0] rslt_buffer_0_5; +reg [15:0] input_buffer_1_0; +reg [19:0] output_buffer_1_0; +wire [19:0] rslt_buffer_1_0; +reg [15:0] input_buffer_1_1; +reg [19:0] output_buffer_1_1; +wire [19:0] rslt_buffer_1_1; +reg [15:0] input_buffer_1_2; +reg [19:0] output_buffer_1_2; +wire [19:0] rslt_buffer_1_2; +reg [15:0] input_buffer_1_3; +reg [19:0] output_buffer_1_3; +wire [19:0] rslt_buffer_1_3; +reg [15:0] input_buffer_1_4; +reg [19:0] output_buffer_1_4; +wire [19:0] rslt_buffer_1_4; +reg [15:0] input_buffer_1_5; +reg [19:0] output_buffer_1_5; +wire [19:0] rslt_buffer_1_5; +reg [15:0] input_buffer_2_0; +reg [19:0] output_buffer_2_0; +wire [19:0] rslt_buffer_2_0; +reg [15:0] input_buffer_2_1; +reg [19:0] output_buffer_2_1; +wire [19:0] rslt_buffer_2_1; +reg [15:0] input_buffer_2_2; +reg [19:0] output_buffer_2_2; +wire [19:0] rslt_buffer_2_2; +reg [15:0] input_buffer_2_3; +reg [19:0] output_buffer_2_3; +wire [19:0] rslt_buffer_2_3; +reg [15:0] input_buffer_2_4; +reg [19:0] output_buffer_2_4; +wire [19:0] rslt_buffer_2_4; +reg [15:0] input_buffer_2_5; +reg [19:0] output_buffer_2_5; +wire [19:0] rslt_buffer_2_5; +reg [15:0] input_buffer_3_0; +reg [19:0] output_buffer_3_0; +wire [19:0] rslt_buffer_3_0; +reg [15:0] input_buffer_3_1; +reg [19:0] output_buffer_3_1; +wire [19:0] rslt_buffer_3_1; +reg [15:0] input_buffer_3_2; +reg [19:0] output_buffer_3_2; +wire [19:0] rslt_buffer_3_2; +reg [15:0] input_buffer_3_3; +reg [19:0] output_buffer_3_3; +wire [19:0] rslt_buffer_3_3; +reg [15:0] input_buffer_3_4; +reg [19:0] output_buffer_3_4; +wire [19:0] rslt_buffer_3_4; +reg [15:0] input_buffer_3_5; +reg [19:0] output_buffer_3_5; +wire [19:0] rslt_buffer_3_5; +reg [15:0] input_buffer_4_0; +reg [19:0] output_buffer_4_0; +wire [19:0] rslt_buffer_4_0; +reg [15:0] input_buffer_4_1; +reg [19:0] output_buffer_4_1; +wire [19:0] rslt_buffer_4_1; +reg [15:0] input_buffer_4_2; +reg [19:0] output_buffer_4_2; +wire [19:0] rslt_buffer_4_2; +reg [15:0] input_buffer_4_3; +reg [19:0] output_buffer_4_3; +wire [19:0] rslt_buffer_4_3; +reg [15:0] input_buffer_4_4; +reg [19:0] output_buffer_4_4; +wire [19:0] rslt_buffer_4_4; +reg [15:0] input_buffer_4_5; +reg [19:0] output_buffer_4_5; +wire [19:0] rslt_buffer_4_5; +reg [15:0] input_buffer_5_0; +reg [19:0] output_buffer_5_0; +wire [19:0] rslt_buffer_5_0; +reg [15:0] input_buffer_5_1; +reg [19:0] output_buffer_5_1; +wire [19:0] rslt_buffer_5_1; +reg [15:0] input_buffer_5_2; +reg [19:0] output_buffer_5_2; +wire [19:0] rslt_buffer_5_2; +reg [15:0] input_buffer_5_3; +reg [19:0] output_buffer_5_3; +wire [19:0] rslt_buffer_5_3; +reg [15:0] input_buffer_5_4; +reg [19:0] output_buffer_5_4; +wire [19:0] rslt_buffer_5_4; +reg [15:0] input_buffer_5_5; +reg [19:0] output_buffer_5_5; +wire [19:0] rslt_buffer_5_5; +reg calculate, calculate_1, calculate_2, calculate_3; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg valid_12; +reg [2:0] input_buffer_count; +wire [15:0] dsp_out_1_0; +wire [15:0] dsp_out_1_1; +wire [15:0] dsp_out_1_2; +wire [15:0] dsp_out_1_3; +wire [15:0] dsp_out_1_4; +wire [15:0] dsp_out_1_5; +wire [15:0] dsp_out_1_6; +wire [15:0] dsp_out_1_7; +wire [15:0] dsp_out_1_8; +wire [15:0] dsp_out_1_9; +wire [15:0] dsp_out_1_10; +wire [15:0] dsp_out_1_11; +wire [15:0] dsp_out_2_0; +wire [15:0] dsp_out_2_1; +wire [15:0] dsp_out_2_2; +wire [15:0] dsp_out_2_3; +wire [15:0] dsp_out_2_4; +wire [15:0] dsp_out_2_5; +wire [15:0] dsp_out_2_6; +wire [15:0] dsp_out_2_7; +wire [15:0] dsp_out_3_0; +wire [15:0] dsp_out_3_1; +wire [15:0] dsp_out_3_2; +wire [15:0] dsp_out_3_3; +wire [15:0] dsp_out_3_4; +wire [15:0] dsp_out_3_5; +wire [15:0] dsp_out_3_6; +wire [15:0] dsp_out_3_7; +wire [15:0] dsp_out_4_0; +wire [15:0] dsp_out_4_1; +wire [15:0] dsp_out_4_2; +wire [15:0] dsp_out_4_3; +wire [15:0] dsp_out_4_4; +wire [15:0] dsp_out_4_5; +wire [15:0] dsp_out_4_6; +wire [15:0] dsp_out_4_7; +wire [15:0] dsp_out_5_0; +wire [15:0] dsp_out_5_1; +wire [15:0] dsp_out_5_2; +wire [15:0] dsp_out_5_3; +wire [15:0] dsp_out_5_4; +wire [15:0] dsp_out_5_5; +wire [15:0] dsp_out_5_6; +wire [15:0] dsp_out_5_7; +wire [15:0] dsp_out_6_0; +wire [15:0] dsp_out_6_1; +wire [15:0] dsp_out_6_2; +wire [15:0] dsp_out_6_3; +wire [15:0] dsp_out_6_4; +wire [15:0] dsp_out_6_5; +wire [15:0] dsp_out_6_6; +wire [15:0] dsp_out_6_7; +wire [15:0] dsp_out_6_8; +wire [15:0] dsp_out_6_9; +wire [15:0] dsp_out_6_10; +wire [15:0] dsp_out_6_11; +reg [15:0] feature_reg_0_0_0; +reg [15:0] feature_reg_0_0_1; +reg [15:0] feature_reg_0_1_0; +reg [15:0] feature_reg_0_1_1; +reg [15:0] feature_reg_0_2_0; +reg [15:0] feature_reg_0_2_1; +reg [15:0] feature_reg_0_3_0; +reg [15:0] feature_reg_0_3_1; +reg [15:0] feature_reg_0_4_0; +reg [15:0] feature_reg_0_4_1; +reg [15:0] feature_reg_0_5_0; +reg [15:0] feature_reg_0_5_1; +reg [15:0] feature_reg_1_0_0; +reg [15:0] feature_reg_1_0_1; +reg [15:0] feature_reg_1_1_0; +reg [15:0] feature_reg_1_1_1; +reg [15:0] feature_reg_1_2_0; +reg [15:0] feature_reg_1_2_1; +reg [15:0] feature_reg_1_3_0; +reg [15:0] feature_reg_1_3_1; +reg [15:0] feature_reg_1_4_0; +reg [15:0] feature_reg_1_4_1; +reg [15:0] feature_reg_1_5_0; +reg [15:0] feature_reg_1_5_1; +reg [15:0] feature_reg_2_0_0; +reg [15:0] feature_reg_2_0_1; +reg [15:0] feature_reg_2_1_0; +reg [15:0] feature_reg_2_1_1; +reg [15:0] feature_reg_2_2_0; +reg [15:0] feature_reg_2_2_1; +reg [15:0] feature_reg_2_3_0; +reg [15:0] feature_reg_2_3_1; +reg [15:0] feature_reg_2_4_0; +reg [15:0] feature_reg_2_4_1; +reg [15:0] feature_reg_2_5_0; +reg [15:0] feature_reg_2_5_1; +reg [15:0] feature_reg_3_0_0; +reg [15:0] feature_reg_3_0_1; +reg [15:0] feature_reg_3_1_0; +reg [15:0] feature_reg_3_1_1; +reg [15:0] feature_reg_3_2_0; +reg [15:0] feature_reg_3_2_1; +reg [15:0] feature_reg_3_3_0; +reg [15:0] feature_reg_3_3_1; +reg [15:0] feature_reg_3_4_0; +reg [15:0] feature_reg_3_4_1; +reg [15:0] feature_reg_3_5_0; +reg [15:0] feature_reg_3_5_1; +reg [15:0] feature_reg_4_0_0; +reg [15:0] feature_reg_4_0_1; +reg [15:0] feature_reg_4_1_0; +reg [15:0] feature_reg_4_1_1; +reg [15:0] feature_reg_4_2_0; +reg [15:0] feature_reg_4_2_1; +reg [15:0] feature_reg_4_3_0; +reg [15:0] feature_reg_4_3_1; +reg [15:0] feature_reg_4_4_0; +reg [15:0] feature_reg_4_4_1; +reg [15:0] feature_reg_4_5_0; +reg [15:0] feature_reg_4_5_1; +reg [15:0] feature_reg_5_0_0; +reg [15:0] feature_reg_5_0_1; +reg [15:0] feature_reg_5_1_0; +reg [15:0] feature_reg_5_1_1; +reg [15:0] feature_reg_5_2_0; +reg [15:0] feature_reg_5_2_1; +reg [15:0] feature_reg_5_3_0; +reg [15:0] feature_reg_5_3_1; +reg [15:0] feature_reg_5_4_0; +reg [15:0] feature_reg_5_4_1; +reg [15:0] feature_reg_5_5_0; +reg [15:0] feature_reg_5_5_1; + +always @ (posedge clk) begin + calculate_1 <= calculate; + calculate_2 <= calculate_1; + calculate_3 <= calculate_2; + //Valid pipeline + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + valid_12 <= valid_11; + if (i_valid) begin + input_buffer_count <= 0; + calculate <= 0; + end else begin + //Input buffering logic + if (input_buffer_count == 5) begin + calculate <= 1; + input_buffer_count <= 0; + end else begin + calculate <= 0; + input_buffer_count <= input_buffer_count + 1'b1; + end + input_buffer_5_0 <= i_result_0_0; + input_buffer_5_1 <= i_result_1_0; + input_buffer_5_2 <= i_result_2_0; + input_buffer_5_3 <= i_result_3_0; + input_buffer_5_4 <= i_result_4_0; + input_buffer_5_5 <= i_result_5_0; + end + input_buffer_0_0 <= input_buffer_1_0; + input_buffer_0_1 <= input_buffer_1_1; + input_buffer_0_2 <= input_buffer_1_2; + input_buffer_0_3 <= input_buffer_1_3; + input_buffer_0_4 <= input_buffer_1_4; + input_buffer_0_5 <= input_buffer_1_5; + input_buffer_1_0 <= input_buffer_2_0; + input_buffer_1_1 <= input_buffer_2_1; + input_buffer_1_2 <= input_buffer_2_2; + input_buffer_1_3 <= input_buffer_2_3; + input_buffer_1_4 <= input_buffer_2_4; + input_buffer_1_5 <= input_buffer_2_5; + input_buffer_2_0 <= input_buffer_3_0; + input_buffer_2_1 <= input_buffer_3_1; + input_buffer_2_2 <= input_buffer_3_2; + input_buffer_2_3 <= input_buffer_3_3; + input_buffer_2_4 <= input_buffer_3_4; + input_buffer_2_5 <= input_buffer_3_5; + input_buffer_3_0 <= input_buffer_4_0; + input_buffer_3_1 <= input_buffer_4_1; + input_buffer_3_2 <= input_buffer_4_2; + input_buffer_3_3 <= input_buffer_4_3; + input_buffer_3_4 <= input_buffer_4_4; + input_buffer_3_5 <= input_buffer_4_5; + input_buffer_4_0 <= input_buffer_5_0; + input_buffer_4_1 <= input_buffer_5_1; + input_buffer_4_2 <= input_buffer_5_2; + input_buffer_4_3 <= input_buffer_5_3; + input_buffer_4_4 <= input_buffer_5_4; + input_buffer_4_5 <= input_buffer_5_5; + //Pipelining to synchronize DSPs and non-DSPs + feature_reg_0_0_0 <= input_buffer_0_0; + feature_reg_0_1_0 <= input_buffer_0_1; + feature_reg_0_2_0 <= input_buffer_0_2; + feature_reg_0_3_0 <= input_buffer_0_3; + feature_reg_0_4_0 <= input_buffer_0_4; + feature_reg_0_5_0 <= input_buffer_0_5; + feature_reg_1_0_0 <= input_buffer_1_0; + feature_reg_1_1_0 <= input_buffer_1_1; + feature_reg_1_2_0 <= input_buffer_1_2; + feature_reg_1_3_0 <= input_buffer_1_3; + feature_reg_1_4_0 <= input_buffer_1_4; + feature_reg_1_5_0 <= input_buffer_1_5; + feature_reg_2_0_0 <= input_buffer_2_0; + feature_reg_2_1_0 <= input_buffer_2_1; + feature_reg_2_2_0 <= input_buffer_2_2; + feature_reg_2_3_0 <= input_buffer_2_3; + feature_reg_2_4_0 <= input_buffer_2_4; + feature_reg_2_5_0 <= input_buffer_2_5; + feature_reg_3_0_0 <= input_buffer_3_0; + feature_reg_3_1_0 <= input_buffer_3_1; + feature_reg_3_2_0 <= input_buffer_3_2; + feature_reg_3_3_0 <= input_buffer_3_3; + feature_reg_3_4_0 <= input_buffer_3_4; + feature_reg_3_5_0 <= input_buffer_3_5; + feature_reg_4_0_0 <= input_buffer_4_0; + feature_reg_4_1_0 <= input_buffer_4_1; + feature_reg_4_2_0 <= input_buffer_4_2; + feature_reg_4_3_0 <= input_buffer_4_3; + feature_reg_4_4_0 <= input_buffer_4_4; + feature_reg_4_5_0 <= input_buffer_4_5; + feature_reg_5_0_0 <= input_buffer_5_0; + feature_reg_5_1_0 <= input_buffer_5_1; + feature_reg_5_2_0 <= input_buffer_5_2; + feature_reg_5_3_0 <= input_buffer_5_3; + feature_reg_5_4_0 <= input_buffer_5_4; + feature_reg_5_5_0 <= input_buffer_5_5; + feature_reg_0_0_1 <= feature_reg_0_0_0; + feature_reg_0_1_1 <= feature_reg_0_1_0; + feature_reg_0_2_1 <= feature_reg_0_2_0; + feature_reg_0_3_1 <= feature_reg_0_3_0; + feature_reg_0_4_1 <= feature_reg_0_4_0; + feature_reg_0_5_1 <= feature_reg_0_5_0; + feature_reg_1_0_1 <= feature_reg_1_0_0; + feature_reg_1_1_1 <= feature_reg_1_1_0; + feature_reg_1_2_1 <= feature_reg_1_2_0; + feature_reg_1_3_1 <= feature_reg_1_3_0; + feature_reg_1_4_1 <= feature_reg_1_4_0; + feature_reg_1_5_1 <= feature_reg_1_5_0; + feature_reg_2_0_1 <= feature_reg_2_0_0; + feature_reg_2_1_1 <= feature_reg_2_1_0; + feature_reg_2_2_1 <= feature_reg_2_2_0; + feature_reg_2_3_1 <= feature_reg_2_3_0; + feature_reg_2_4_1 <= feature_reg_2_4_0; + feature_reg_2_5_1 <= feature_reg_2_5_0; + feature_reg_3_0_1 <= feature_reg_3_0_0; + feature_reg_3_1_1 <= feature_reg_3_1_0; + feature_reg_3_2_1 <= feature_reg_3_2_0; + feature_reg_3_3_1 <= feature_reg_3_3_0; + feature_reg_3_4_1 <= feature_reg_3_4_0; + feature_reg_3_5_1 <= feature_reg_3_5_0; + feature_reg_4_0_1 <= feature_reg_4_0_0; + feature_reg_4_1_1 <= feature_reg_4_1_0; + feature_reg_4_2_1 <= feature_reg_4_2_0; + feature_reg_4_3_1 <= feature_reg_4_3_0; + feature_reg_4_4_1 <= feature_reg_4_4_0; + feature_reg_4_5_1 <= feature_reg_4_5_0; + feature_reg_5_0_1 <= feature_reg_5_0_0; + feature_reg_5_1_1 <= feature_reg_5_1_0; + feature_reg_5_2_1 <= feature_reg_5_2_0; + feature_reg_5_3_1 <= feature_reg_5_3_0; + feature_reg_5_4_1 <= feature_reg_5_4_0; + feature_reg_5_5_1 <= feature_reg_5_5_0; + //Output Serializing logic + if (calculate_3) begin + output_buffer_0_0 <= rslt_buffer_0_0; + output_buffer_1_0 <= rslt_buffer_0_1; + output_buffer_2_0 <= rslt_buffer_0_2; + output_buffer_3_0 <= rslt_buffer_0_3; + output_buffer_4_0 <= rslt_buffer_0_4; + output_buffer_5_0 <= rslt_buffer_0_5; + output_buffer_0_1 <= rslt_buffer_1_0; + output_buffer_1_1 <= rslt_buffer_1_1; + output_buffer_2_1 <= rslt_buffer_1_2; + output_buffer_3_1 <= rslt_buffer_1_3; + output_buffer_4_1 <= rslt_buffer_1_4; + output_buffer_5_1 <= rslt_buffer_1_5; + output_buffer_0_2 <= rslt_buffer_2_0; + output_buffer_1_2 <= rslt_buffer_2_1; + output_buffer_2_2 <= rslt_buffer_2_2; + output_buffer_3_2 <= rslt_buffer_2_3; + output_buffer_4_2 <= rslt_buffer_2_4; + output_buffer_5_2 <= rslt_buffer_2_5; + output_buffer_0_3 <= rslt_buffer_3_0; + output_buffer_1_3 <= rslt_buffer_3_1; + output_buffer_2_3 <= rslt_buffer_3_2; + output_buffer_3_3 <= rslt_buffer_3_3; + output_buffer_4_3 <= rslt_buffer_3_4; + output_buffer_5_3 <= rslt_buffer_3_5; + output_buffer_0_4 <= rslt_buffer_4_0; + output_buffer_1_4 <= rslt_buffer_4_1; + output_buffer_2_4 <= rslt_buffer_4_2; + output_buffer_3_4 <= rslt_buffer_4_3; + output_buffer_4_4 <= rslt_buffer_4_4; + output_buffer_5_4 <= rslt_buffer_4_5; + output_buffer_0_5 <= rslt_buffer_5_0; + output_buffer_1_5 <= rslt_buffer_5_1; + output_buffer_2_5 <= rslt_buffer_5_2; + output_buffer_3_5 <= rslt_buffer_5_3; + output_buffer_4_5 <= rslt_buffer_5_4; + output_buffer_5_5 <= rslt_buffer_5_5; + end else begin + output_buffer_0_0 <= output_buffer_0_1; + output_buffer_0_1 <= output_buffer_0_2; + output_buffer_0_2 <= output_buffer_0_3; + output_buffer_0_3 <= output_buffer_0_4; + output_buffer_0_4 <= output_buffer_0_5; + output_buffer_1_0 <= output_buffer_1_1; + output_buffer_1_1 <= output_buffer_1_2; + output_buffer_1_2 <= output_buffer_1_3; + output_buffer_1_3 <= output_buffer_1_4; + output_buffer_1_4 <= output_buffer_1_5; + output_buffer_2_0 <= output_buffer_2_1; + output_buffer_2_1 <= output_buffer_2_2; + output_buffer_2_2 <= output_buffer_2_3; + output_buffer_2_3 <= output_buffer_2_4; + output_buffer_2_4 <= output_buffer_2_5; + output_buffer_3_0 <= output_buffer_3_1; + output_buffer_3_1 <= output_buffer_3_2; + output_buffer_3_2 <= output_buffer_3_3; + output_buffer_3_3 <= output_buffer_3_4; + output_buffer_3_4 <= output_buffer_3_5; + output_buffer_4_0 <= output_buffer_4_1; + output_buffer_4_1 <= output_buffer_4_2; + output_buffer_4_2 <= output_buffer_4_3; + output_buffer_4_3 <= output_buffer_4_4; + output_buffer_4_4 <= output_buffer_4_5; + output_buffer_5_0 <= output_buffer_5_1; + output_buffer_5_1 <= output_buffer_5_2; + output_buffer_5_2 <= output_buffer_5_3; + output_buffer_5_3 <= output_buffer_5_4; + output_buffer_5_4 <= output_buffer_5_5; + end +end + +////// FIRST COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD00 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_2), + .by(input_buffer_2_0), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_1_0), + .resultb(dsp_out_1_1) +); + +winograd_dsp_16 winograd_dsp_16_WD10 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_2_4), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_1_2), + .resultb(dsp_out_1_3) +); + +winograd_dsp_16 winograd_dsp_16_WD20 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_2), + .by(input_buffer_1_0), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_1_4), + .resultb(dsp_out_1_5) +); + +winograd_dsp_16 winograd_dsp_16_WD30 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_1_6), + .resultb(dsp_out_1_7) +); + +winograd_dsp_16 winograd_dsp_16_WD40 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_0), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_1_8), + .resultb(dsp_out_1_9) +); + +winograd_dsp_16 winograd_dsp_16_WD50 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_4), + .by(input_buffer_5_2), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_1_10), + .resultb(dsp_out_1_11) +); + +////// SECOND COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD01 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_0), + .resultb(dsp_out_2_1) +); + +winograd_dsp_16 winograd_dsp_16_WD11 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_2), + .resultb(dsp_out_2_3) +); + +winograd_dsp_16 winograd_dsp_16_WD21 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_4), + .resultb(dsp_out_2_5) +); + +winograd_dsp_16 winograd_dsp_16_WD31 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_6), + .resultb(dsp_out_2_7) +); + +////// THIRD COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD02 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_0), + .resultb(dsp_out_3_1) +); + +winograd_dsp_16 winograd_dsp_16_WD12 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_2), + .resultb(dsp_out_3_3) +); + +winograd_dsp_16 winograd_dsp_16_WD22 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_4), + .resultb(dsp_out_3_5) +); + +winograd_dsp_16 winograd_dsp_16_WD32 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_6), + .resultb(dsp_out_3_7) +); + +////// FOURTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD03 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_0), + .resultb(dsp_out_4_1) +); + +winograd_dsp_16 winograd_dsp_16_WD13 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_2), + .resultb(dsp_out_4_3) +); + +winograd_dsp_16 winograd_dsp_16_WD23 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_4), + .resultb(dsp_out_4_5) +); + +winograd_dsp_16 winograd_dsp_16_WD33 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_6), + .resultb(dsp_out_4_7) +); + +////// FIFTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD04 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_0), + .resultb(dsp_out_5_1) +); + +winograd_dsp_16 winograd_dsp_16_WD14 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_2), + .resultb(dsp_out_5_3) +); + +winograd_dsp_16 winograd_dsp_16_WD24 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_4), + .resultb(dsp_out_5_5) +); + +winograd_dsp_16 winograd_dsp_16_WD34 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_6), + .resultb(dsp_out_5_7) +); + +////// SIXTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD05 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_3), + .by(input_buffer_2_1), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_6_0), + .resultb(dsp_out_6_1) +); + +winograd_dsp_16 winograd_dsp_16_WD15 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_5), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_6_2), + .resultb(dsp_out_6_3) +); + +winograd_dsp_16 winograd_dsp_16_WD25 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_3), + .by(input_buffer_1_3), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_6_4), + .resultb(dsp_out_6_5) +); + +winograd_dsp_16 winograd_dsp_16_WD35 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_3_3), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_6_6), + .resultb(dsp_out_6_7) +); + +winograd_dsp_16 winograd_dsp_16_WD45 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_3), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_6_8), + .resultb(dsp_out_6_9) +); + +winograd_dsp_16 winograd_dsp_16_WD55 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_5), + .by(input_buffer_5_3), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_6_10), + .resultb(dsp_out_6_11) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA00 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_0_1[11:0], 4'b0000}), + .data1x(dsp_out_1_0), + .data2x({feature_reg_0_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_1), + .data4x(dsp_out_1_2), + .data5x(dsp_out_1_3), + .data6x({feature_reg_4_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_4), + .data8x(feature_reg_4_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_0) +); + +wire [15:0] f1, f2, f3, f4; +assign f1 = -{feature_reg_1_0_1[11:0], 4'b0000}; +assign f2 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f3 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f4 = -{feature_reg_2_4_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA10 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_1_5), + .data1x(f1), + .data2x(f2), + .data3x(f3), + .data4x(dsp_out_1_6), + .data5x(f4), + .data6x({feature_reg_3_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_7), + .data8x(feature_reg_3_4_1), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_0) +); + +wire [15:0] f5, f6, f7, f8, f9, f10; +assign f5 = -dsp_out_1_5; +assign f6 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f7 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f8 = -{feature_reg_3_0_1[13:0], 2'b00}; +assign f9 = -dsp_out_1_7; +assign f10 = -feature_reg_3_4_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA20 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f5), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(f6), + .data4x(dsp_out_1_6), + .data5x(f7), + .data6x(f8), + .data7x(f9), + .data8x(f10), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_0) +); + +wire [15:0] f11, f12, f13, f14, f15, f16, f17; +assign f11 = -{feature_reg_1_0_1[12:0], 3'b000}; +assign f12 = -{feature_reg_1_4_1[14:0], 1'b0}; +assign f13 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f14 = -feature_reg_2_4_1; +assign f15 = dsp_out_1_5 >>> 1; +assign f16 = dsp_out_1_6 >>> 2; +assign f17 = dsp_out_1_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA30 ( + .clock(clk), + .clken(calculate_2), + .data0x(f15), + .data1x(f11), + .data2x(f12), + .data3x(f13), + .data4x(f16), + .data5x(f14), + .data6x({feature_reg_3_0_1[12:0], 3'b000}), + .data7x(f17), + .data8x({feature_reg_3_4_1[14:0], 1'b0}), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_0) +); + +wire [15:0] f18, f19, f20, f21, f22, f23, f23b; +assign f18 = -(dsp_out_1_5 >>> 1); +assign f19 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f20 = -feature_reg_2_4_1; +assign f21 = -{feature_reg_3_0_1[12:0], 3'b000}; +assign f22 = -(dsp_out_1_7 <<< 1); +assign f23 = -{feature_reg_3_4_1[14:0], 1'b0}; +assign f23b = dsp_out_1_6 >>> 2; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA40 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[12:0], 3'b000}), + .data1x(f18), + .data2x({feature_reg_1_4_1[14:0], 1'b0}), + .data3x(f19), + .data4x(f23b), + .data5x(f20), + .data6x(f21), + .data7x(f22), + .data8x(f23), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_0) +); + +wire [15:0] f24; +assign f24 = -dsp_out_1_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA50 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f24), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_8), + .data4x(dsp_out_1_9), + .data5x(dsp_out_1_10), + .data6x({feature_reg_5_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_11), + .data8x(feature_reg_5_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_0) +); + +wire [15:0] f25, f26, f27, f28; +assign f25 = -{feature_reg_0_2_1[11:0], 4'b0000}; +assign f26 = -{feature_reg_0_1_1[11:0], 4'b0000}; +assign f27 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f28 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA01 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[13:0], 2'b00}), + .data1x(f25), + .data2x(f26), + .data3x({feature_reg_0_4_1[13:0], 2'b00}), + .data4x(dsp_out_2_0), + .data5x(dsp_out_2_1), + .data6x(dsp_out_2_2), + .data7x(dsp_out_2_3), + .data8x(f27), + .data9x(f28), + .data10x(feature_reg_4_3_1), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_1) +); + +wire [15:0] f29, f30, f31, f32, f33, f34, f35, f36; +assign f29 = -{feature_reg_1_3_1[13:0], 2'b00}; +assign f30 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f31 = -{feature_reg_2_3_1[13:0], 2'b00}; +assign f32 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f33 = -{feature_reg_3_1_1[13:0], 2'b00}; +assign f34 = -{feature_reg_3_2_1[13:0], 2'b00}; +assign f35 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f36 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA11 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0], 4'b0000}), + .data1x({feature_reg_1_2_1[11:0], 4'b0000}), + .data2x(f29), + .data3x(f30), + .data4x({feature_reg_2_1_1[11:0], 4'b0000}), + .data5x({feature_reg_2_2_1[11:0], 4'b0000}), + .data6x(f31), + .data7x(f32), + .data8x(f33), + .data9x(f34), + .data10x(feature_reg_3_3_1), + .data11x(feature_reg_3_4_1), + .data12x(f35), + .data13x(f36), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_1) +); + +wire [15:0] f37, f38, f39, f40, f41, f42, f43, f44; +assign f37 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f38 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f39 = -{feature_reg_2_3_1[13:0],2'b00}; +assign f40 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f41 = -feature_reg_3_3_1; +assign f42 = -feature_reg_3_4_1; +assign f43 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f44 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA21 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f37), + .data2x(f38), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[11:0],4'b0000}), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x(f39), + .data7x(f40), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(f41), + .data11x(f42), + .data12x(f43), + .data13x(f44), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_1) +); + +wire [15:0] f45, f46, f47, f48, f49, f50, f51, f52; +assign f45 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f46 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f47 = -feature_reg_2_3_1; +assign f48 = -feature_reg_2_4_1; +assign f49 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f50 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f51 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f52 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA31 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[12:0],3'b000}), + .data2x(f45), + .data3x(f46), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f47), + .data7x(f48), + .data8x(f49), + .data9x(f50), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f51), + .data13x(f52), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_1) +); + +wire [15:0] f53, f54, f55, f56, f57, f58, f59, f60; +assign f53 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f54 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f55 = -feature_reg_2_3_1; +assign f56 = -feature_reg_2_4_1; +assign f57 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f58 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f59 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f60 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA41 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[14:0],1'b0}), + .data1x(f53), + .data2x(f54), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f55), + .data7x(f56), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x(f57), + .data11x(f58), + .data12x(f59), + .data13x(f60), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_1) +); + +wire [15:0] f61, f62, f63, f64; +assign f61 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f62 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f63 = -{feature_reg_5_1_1[13:0],2'b00}; +assign f64 = -{feature_reg_5_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA51 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f61), + .data2x(f62), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_2_4), + .data5x(dsp_out_2_5), + .data6x(dsp_out_2_6), + .data7x(dsp_out_2_7), + .data8x(f63), + .data9x(f64), + .data10x(feature_reg_5_3_1), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_1) +); + +wire [15:0] f65, f66, f67, f68; +assign f65 = -{feature_reg_0_2_1[11:0],4'b0000}; +assign f66 = -{feature_reg_0_3_1[13:0],2'b00}; +assign f67 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f68 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA02 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(f65), + .data2x(f66), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_3_0), + .data5x(dsp_out_3_1), + .data6x(dsp_out_3_2), + .data7x(dsp_out_3_3), + .data8x({feature_reg_4_1_1[13:0],2'b00}), + .data9x(f67), + .data10x(f68), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_2) +); + +wire [15:0] f69, f70, f71, f72, f73, f74, f75, f76; +assign f69 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f70 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f71 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f72 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f73 = -{feature_reg_3_2_1[13:0],2'b00}; +assign f74 = -feature_reg_3_3_1; +assign f75 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f76 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA12 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[11:0],4'b0000}), + .data1x(f69), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f70), + .data4x(f71), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f72), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f73), + .data10x(f74), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f75), + .data14x(f76), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_2) +); + +wire [15:0] f77, f78, f79, f80, f81, f82, f83, f84; +assign f77 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f78 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f79 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f80 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f81 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f82 = -feature_reg_3_4_1; +assign f83 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f84 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA22 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f77), + .data2x(f78), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f79), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f80), + .data8x(f81), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(feature_reg_3_3_1), + .data11x(f82), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f83), + .data14x(f84), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_2) +); + +wire [15:0] f85, f86, f87, f88, f89, f90, f91, f92; +assign f85 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f86 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f87 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f88 = -feature_reg_2_4_1; +assign f89 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f90 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f91 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f92 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA32 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[12:0],3'b000}), + .data1x(f85), + .data2x({feature_reg_1_3_1[14:0],1'b0}), + .data3x(f86), + .data4x(f87), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f88), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x(f89), + .data10x(f90), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f91), + .data14x(f92), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_2) +); + +wire [15:0] f93, f94, f95, f96, f97, f98, f99, f100; +assign f93 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f94 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f95 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f96 = -feature_reg_2_4_1; +assign f97 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f98 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f99 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f100 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA42 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f93), + .data2x(f94), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f95), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f96), + .data8x(f97), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f98), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f99), + .data14x(f100), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_2) +); + +wire [15:0] f101, f102, f103, f104; +assign f101 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f102 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f103 = -{feature_reg_5_2_1[13:0],2'b00}; +assign f104 = -feature_reg_5_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA52 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f101), + .data2x(f102), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_3_4), + .data5x(dsp_out_3_5), + .data6x(dsp_out_3_6), + .data7x(dsp_out_3_7), + .data8x({feature_reg_5_1_1[13:0],2'b00}), + .data9x(f103), + .data10x(f104), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_2) +); + +wire [15:0] f105, f106, f107, f108; +assign f105 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f106 = -{feature_reg_0_1_1[12:0],3'b000}; +assign f107 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f108 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA03 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[12:0],3'b000}), + .data1x(f105), + .data2x(f106), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_4_0), + .data5x(dsp_out_4_1), + .data6x(dsp_out_4_2), + .data7x(dsp_out_4_3), + .data8x(f107), + .data9x(f108), + .data10x({feature_reg_4_3_1[14:0],1'b0}), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_3) +); + +wire [15:0] f109, f110, f111, f112, f113, f114, f115, f116; +assign f109 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f110 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f111 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f112 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f113 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f114 = -feature_reg_3_2_1; +assign f115 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f116 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA13 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[13:0],2'b00}), + .data2x(f109), + .data3x(f110), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f111), + .data7x(f112), + .data8x(f113), + .data9x(f114), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(feature_reg_3_4_1), + .data12x(f115), + .data13x(f116), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_3) +); + +wire [15:0] f117, f118, f119, f120, f121, f122, f123, f124; +assign f117 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f118 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f119 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f120 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f121 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f122 = -feature_reg_3_4_1; +assign f123 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f124 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA23 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f117), + .data2x(f118), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f119), + .data7x(f120), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(feature_reg_3_2_1), + .data10x(f121), + .data11x(f122), + .data12x(f123), + .data13x(f124), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_3) +); + +wire [15:0] f125, f126, f127, f128, f129, f130, f131, f132; +assign f125 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f126 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f127 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f128 = -feature_reg_2_4_1; +assign f129 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f130 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f131 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f132 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA33 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x({feature_reg_1_2_1[14:0],1'b0}), + .data2x(f125), + .data3x(f126), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f127), + .data7x(f128), + .data8x(f129), + .data9x(f130), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f131), + .data13x(f132), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_3) +); + +wire [15:0] f133, f134, f135, f136, f137, f138, f139, f140; +assign f133 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f134 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f135 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f136 = -feature_reg_2_4_1; +assign f137 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f138 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f139 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f140 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA43 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f133), + .data2x(f134), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f135), + .data7x(f136), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x(f137), + .data11x(f138), + .data12x(f139), + .data13x(f140), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_3) +); + +wire [15:0] f141, f142, f143, f144; +assign f141 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f142 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f143 = -{feature_reg_5_1_1[14:0],1'b0}; +assign f144 = -feature_reg_5_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA53 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f141), + .data2x(f142), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_4_4), + .data5x(dsp_out_4_5), + .data6x(dsp_out_4_6), + .data7x(dsp_out_4_7), + .data8x(f143), + .data9x(f144), + .data10x({feature_reg_5_3_1[14:0],1'b0}), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_3) +); + +wire [15:0] f145, f146, f147, f148; +assign f145 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f146 = -{feature_reg_0_3_1[12:0],3'b000}; +assign f147 = -feature_reg_4_2_1; +assign f148 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA04 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[12:0],3'b000}), + .data1x(f145), + .data2x(f146), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_5_0), + .data5x(dsp_out_5_1), + .data6x(dsp_out_5_2), + .data7x(dsp_out_5_3), + .data8x({feature_reg_4_1_1[14:0],1'b0}), + .data9x(f147), + .data10x(f148), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_4) +); + +wire [15:0] f149, f150, f151, f152, f153, f154, f155, f156; +assign f149 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f150 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f151 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f152 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f153 = -feature_reg_3_2_1; +assign f154 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f155 = -feature_reg_4_2_1; +assign f156 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA14 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[13:0],2'b00}), + .data1x(f149), + .data2x({feature_reg_1_3_1[12:0],3'b000}), + .data3x(f150), + .data4x(f151), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f152), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(f153), + .data10x(f154), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f155), + .data14x(f156), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_4) +); + +wire [15:0] f157, f158, f159, f160, f161, f162, f163, f164; +assign f157 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f158 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f159 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f160 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f161 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f162 = -feature_reg_3_4_1; +assign f163 = -feature_reg_4_2_1; +assign f164 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA24 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f157), + .data2x(f158), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f159), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f160), + .data8x(f161), + .data9x(feature_reg_3_2_1), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f162), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f163), + .data14x(f164), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_4) +); + +wire [15:0] f165, f166, f167, f168, f169, f170, f171, f172; +assign f165 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f166 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f167 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f168 = -feature_reg_2_4_1; +assign f169 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f170 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f171 = -feature_reg_4_2_1; +assign f172 = -{feature_reg_4_1_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA34 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[14:0],1'b0}), + .data1x(f165), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f166), + .data4x(f167), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f168), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f169), + .data10x(f170), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f171), + .data14x(f172), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_4) +); + +wire [15:0] f173, f174, f175, f176, f177, f178, f179, f180; +assign f173 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f174 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f175 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f176 = -feature_reg_2_4_1; +assign f177 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f178 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f179 = -feature_reg_4_2_1; +assign f180 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA44 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x(f173), + .data2x(f174), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f175), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f176), + .data8x(f177), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x(f178), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f179), + .data14x(f180), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_4) +); + +wire [15:0] f181, f182, f183, f184; +assign f181 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f182 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f183 = -feature_reg_5_2_1; +assign f184 = -{feature_reg_5_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA54 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f181), + .data2x(f182), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_5_4), + .data5x(dsp_out_5_5), + .data6x(dsp_out_5_6), + .data7x(dsp_out_5_7), + .data8x({feature_reg_5_1_1[14:0],1'b0}), + .data9x(f183), + .data10x(f184), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_4) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA05 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(dsp_out_6_0), + .data2x({feature_reg_0_5_1[13:0],2'b00}), + .data3x(dsp_out_6_1), + .data4x(dsp_out_6_2), + .data5x(dsp_out_6_3), + .data6x({feature_reg_4_1_1[13:0],2'b00}), + .data7x(dsp_out_6_4), + .data8x(feature_reg_4_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_5) +); + +wire [15:0] f185, f186, f187, f188; +assign f185 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f186 = -{feature_reg_1_5_1[13:0],2'b00}; +assign f187 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f188 = -{feature_reg_2_5_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA15 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_6_5), + .data1x(f185), + .data2x(f186), + .data3x(f187), + .data4x(dsp_out_6_6), + .data5x(f188), + .data6x({feature_reg_3_1_1[13:0],2'b00}), + .data7x(dsp_out_6_7), + .data8x(feature_reg_3_5_1), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_5) +); + +wire [15:0] f189, f190, f191, f192, f193, f194; +assign f189 = -dsp_out_6_5; +assign f190 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f191 = -{feature_reg_2_5_1[13:0],2'b00}; +assign f192 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f193 = -dsp_out_6_7; +assign f194 = -feature_reg_3_5_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA25 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f189), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(f190), + .data4x(dsp_out_6_6), + .data5x(f191), + .data6x(f192), + .data7x(f193), + .data8x(f194), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_5) +); + +wire [15:0] f195, f196, f197, f198, f199, f200, f201; +assign f195 = dsp_out_6_5 >>> 1; +assign f196 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f197 = -{feature_reg_1_5_1[14:0],1'b0}; +assign f198 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f199 = dsp_out_6_6 >>> 2; +assign f200 = -feature_reg_2_5_1; +assign f201 = dsp_out_6_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA35 ( + .clock(clk), + .clken(calculate_2), + .data0x(f195), + .data1x(f196), + .data2x(f197), + .data3x(f198), + .data4x(f199), + .data5x(f200), + .data6x({feature_reg_3_1_1[12:0],3'b000}), + .data7x(f201), + .data8x({feature_reg_3_5_1[14:0],1'b0}), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_5) +); + +wire [15:0] f202, f203, f204, f205, f206, f207, f208; +assign f202 = -(dsp_out_6_5 >>> 1); +assign f203 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f204 = dsp_out_6_6 >>> 2; +assign f205 = -feature_reg_2_5_1; +assign f206 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f207 = -(dsp_out_6_7 <<< 1); +assign f208 = -{feature_reg_3_5_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA45 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f202), + .data2x({feature_reg_1_5_1[14:0],1'b0}), + .data3x(f203), + .data4x(f204), + .data5x(f205), + .data6x(f206), + .data7x(f207), + .data8x(f208), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_5) +); + +wire [15:0] f209; +assign f209 = -dsp_out_6_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA55 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f209), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(dsp_out_6_8), + .data4x(dsp_out_6_9), + .data5x(dsp_out_6_10), + .data6x({feature_reg_5_1_1[13:0],2'b00}), + .data7x(dsp_out_6_11), + .data8x(feature_reg_5_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_5) +); + +assign o_feature_0 = output_buffer_0_0[15:0]; +assign o_feature_1 = output_buffer_1_0[15:0]; +assign o_feature_2 = output_buffer_2_0[15:0]; +assign o_feature_3 = output_buffer_3_0[15:0]; +assign o_feature_4 = output_buffer_4_0[15:0]; +assign o_feature_5 = output_buffer_5_0[15:0]; +assign o_valid = valid_9; + +endmodule + +module winograd_transform_3 ( + input clk, + input i_valid, + input [15:0] i_result_0_0, + input [15:0] i_result_0_1, + input [15:0] i_result_0_2, + input [15:0] i_result_0_3, + input [15:0] i_result_1_0, + input [15:0] i_result_1_1, + input [15:0] i_result_1_2, + input [15:0] i_result_1_3, + input [15:0] i_result_2_0, + input [15:0] i_result_2_1, + input [15:0] i_result_2_2, + input [15:0] i_result_2_3, + input [15:0] i_result_3_0, + input [15:0] i_result_3_1, + input [15:0] i_result_3_2, + input [15:0] i_result_3_3, + input [15:0] i_result_4_0, + input [15:0] i_result_4_1, + input [15:0] i_result_4_2, + input [15:0] i_result_4_3, + input [15:0] i_result_5_0, + input [15:0] i_result_5_1, + input [15:0] i_result_5_2, + input [15:0] i_result_5_3, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output [15:0] o_feature_2, + output [15:0] o_feature_3, + output [15:0] o_feature_4, + output [15:0] o_feature_5, + output o_valid +); + +reg [15:0] input_buffer_0_0; +reg [19:0] output_buffer_0_0; +wire [19:0] rslt_buffer_0_0; +reg [15:0] input_buffer_0_1; +reg [19:0] output_buffer_0_1; +wire [19:0] rslt_buffer_0_1; +reg [15:0] input_buffer_0_2; +reg [19:0] output_buffer_0_2; +wire [19:0] rslt_buffer_0_2; +reg [15:0] input_buffer_0_3; +reg [19:0] output_buffer_0_3; +wire [19:0] rslt_buffer_0_3; +reg [15:0] input_buffer_0_4; +reg [19:0] output_buffer_0_4; +wire [19:0] rslt_buffer_0_4; +reg [15:0] input_buffer_0_5; +reg [19:0] output_buffer_0_5; +wire [19:0] rslt_buffer_0_5; +reg [15:0] input_buffer_1_0; +reg [19:0] output_buffer_1_0; +wire [19:0] rslt_buffer_1_0; +reg [15:0] input_buffer_1_1; +reg [19:0] output_buffer_1_1; +wire [19:0] rslt_buffer_1_1; +reg [15:0] input_buffer_1_2; +reg [19:0] output_buffer_1_2; +wire [19:0] rslt_buffer_1_2; +reg [15:0] input_buffer_1_3; +reg [19:0] output_buffer_1_3; +wire [19:0] rslt_buffer_1_3; +reg [15:0] input_buffer_1_4; +reg [19:0] output_buffer_1_4; +wire [19:0] rslt_buffer_1_4; +reg [15:0] input_buffer_1_5; +reg [19:0] output_buffer_1_5; +wire [19:0] rslt_buffer_1_5; +reg [15:0] input_buffer_2_0; +reg [19:0] output_buffer_2_0; +wire [19:0] rslt_buffer_2_0; +reg [15:0] input_buffer_2_1; +reg [19:0] output_buffer_2_1; +wire [19:0] rslt_buffer_2_1; +reg [15:0] input_buffer_2_2; +reg [19:0] output_buffer_2_2; +wire [19:0] rslt_buffer_2_2; +reg [15:0] input_buffer_2_3; +reg [19:0] output_buffer_2_3; +wire [19:0] rslt_buffer_2_3; +reg [15:0] input_buffer_2_4; +reg [19:0] output_buffer_2_4; +wire [19:0] rslt_buffer_2_4; +reg [15:0] input_buffer_2_5; +reg [19:0] output_buffer_2_5; +wire [19:0] rslt_buffer_2_5; +reg [15:0] input_buffer_3_0; +reg [19:0] output_buffer_3_0; +wire [19:0] rslt_buffer_3_0; +reg [15:0] input_buffer_3_1; +reg [19:0] output_buffer_3_1; +wire [19:0] rslt_buffer_3_1; +reg [15:0] input_buffer_3_2; +reg [19:0] output_buffer_3_2; +wire [19:0] rslt_buffer_3_2; +reg [15:0] input_buffer_3_3; +reg [19:0] output_buffer_3_3; +wire [19:0] rslt_buffer_3_3; +reg [15:0] input_buffer_3_4; +reg [19:0] output_buffer_3_4; +wire [19:0] rslt_buffer_3_4; +reg [15:0] input_buffer_3_5; +reg [19:0] output_buffer_3_5; +wire [19:0] rslt_buffer_3_5; +reg [15:0] input_buffer_4_0; +reg [19:0] output_buffer_4_0; +wire [19:0] rslt_buffer_4_0; +reg [15:0] input_buffer_4_1; +reg [19:0] output_buffer_4_1; +wire [19:0] rslt_buffer_4_1; +reg [15:0] input_buffer_4_2; +reg [19:0] output_buffer_4_2; +wire [19:0] rslt_buffer_4_2; +reg [15:0] input_buffer_4_3; +reg [19:0] output_buffer_4_3; +wire [19:0] rslt_buffer_4_3; +reg [15:0] input_buffer_4_4; +reg [19:0] output_buffer_4_4; +wire [19:0] rslt_buffer_4_4; +reg [15:0] input_buffer_4_5; +reg [19:0] output_buffer_4_5; +wire [19:0] rslt_buffer_4_5; +reg [15:0] input_buffer_5_0; +reg [19:0] output_buffer_5_0; +wire [19:0] rslt_buffer_5_0; +reg [15:0] input_buffer_5_1; +reg [19:0] output_buffer_5_1; +wire [19:0] rslt_buffer_5_1; +reg [15:0] input_buffer_5_2; +reg [19:0] output_buffer_5_2; +wire [19:0] rslt_buffer_5_2; +reg [15:0] input_buffer_5_3; +reg [19:0] output_buffer_5_3; +wire [19:0] rslt_buffer_5_3; +reg [15:0] input_buffer_5_4; +reg [19:0] output_buffer_5_4; +wire [19:0] rslt_buffer_5_4; +reg [15:0] input_buffer_5_5; +reg [19:0] output_buffer_5_5; +wire [19:0] rslt_buffer_5_5; +reg calculate, calculate_1, calculate_2, calculate_3; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg valid_12; +reg [2:0] input_buffer_count; +wire [15:0] dsp_out_1_0; +wire [15:0] dsp_out_1_1; +wire [15:0] dsp_out_1_2; +wire [15:0] dsp_out_1_3; +wire [15:0] dsp_out_1_4; +wire [15:0] dsp_out_1_5; +wire [15:0] dsp_out_1_6; +wire [15:0] dsp_out_1_7; +wire [15:0] dsp_out_1_8; +wire [15:0] dsp_out_1_9; +wire [15:0] dsp_out_1_10; +wire [15:0] dsp_out_1_11; +wire [15:0] dsp_out_2_0; +wire [15:0] dsp_out_2_1; +wire [15:0] dsp_out_2_2; +wire [15:0] dsp_out_2_3; +wire [15:0] dsp_out_2_4; +wire [15:0] dsp_out_2_5; +wire [15:0] dsp_out_2_6; +wire [15:0] dsp_out_2_7; +wire [15:0] dsp_out_3_0; +wire [15:0] dsp_out_3_1; +wire [15:0] dsp_out_3_2; +wire [15:0] dsp_out_3_3; +wire [15:0] dsp_out_3_4; +wire [15:0] dsp_out_3_5; +wire [15:0] dsp_out_3_6; +wire [15:0] dsp_out_3_7; +wire [15:0] dsp_out_4_0; +wire [15:0] dsp_out_4_1; +wire [15:0] dsp_out_4_2; +wire [15:0] dsp_out_4_3; +wire [15:0] dsp_out_4_4; +wire [15:0] dsp_out_4_5; +wire [15:0] dsp_out_4_6; +wire [15:0] dsp_out_4_7; +wire [15:0] dsp_out_5_0; +wire [15:0] dsp_out_5_1; +wire [15:0] dsp_out_5_2; +wire [15:0] dsp_out_5_3; +wire [15:0] dsp_out_5_4; +wire [15:0] dsp_out_5_5; +wire [15:0] dsp_out_5_6; +wire [15:0] dsp_out_5_7; +wire [15:0] dsp_out_6_0; +wire [15:0] dsp_out_6_1; +wire [15:0] dsp_out_6_2; +wire [15:0] dsp_out_6_3; +wire [15:0] dsp_out_6_4; +wire [15:0] dsp_out_6_5; +wire [15:0] dsp_out_6_6; +wire [15:0] dsp_out_6_7; +wire [15:0] dsp_out_6_8; +wire [15:0] dsp_out_6_9; +wire [15:0] dsp_out_6_10; +wire [15:0] dsp_out_6_11; +reg [15:0] feature_reg_0_0_0; +reg [15:0] feature_reg_0_0_1; +reg [15:0] feature_reg_0_1_0; +reg [15:0] feature_reg_0_1_1; +reg [15:0] feature_reg_0_2_0; +reg [15:0] feature_reg_0_2_1; +reg [15:0] feature_reg_0_3_0; +reg [15:0] feature_reg_0_3_1; +reg [15:0] feature_reg_0_4_0; +reg [15:0] feature_reg_0_4_1; +reg [15:0] feature_reg_0_5_0; +reg [15:0] feature_reg_0_5_1; +reg [15:0] feature_reg_1_0_0; +reg [15:0] feature_reg_1_0_1; +reg [15:0] feature_reg_1_1_0; +reg [15:0] feature_reg_1_1_1; +reg [15:0] feature_reg_1_2_0; +reg [15:0] feature_reg_1_2_1; +reg [15:0] feature_reg_1_3_0; +reg [15:0] feature_reg_1_3_1; +reg [15:0] feature_reg_1_4_0; +reg [15:0] feature_reg_1_4_1; +reg [15:0] feature_reg_1_5_0; +reg [15:0] feature_reg_1_5_1; +reg [15:0] feature_reg_2_0_0; +reg [15:0] feature_reg_2_0_1; +reg [15:0] feature_reg_2_1_0; +reg [15:0] feature_reg_2_1_1; +reg [15:0] feature_reg_2_2_0; +reg [15:0] feature_reg_2_2_1; +reg [15:0] feature_reg_2_3_0; +reg [15:0] feature_reg_2_3_1; +reg [15:0] feature_reg_2_4_0; +reg [15:0] feature_reg_2_4_1; +reg [15:0] feature_reg_2_5_0; +reg [15:0] feature_reg_2_5_1; +reg [15:0] feature_reg_3_0_0; +reg [15:0] feature_reg_3_0_1; +reg [15:0] feature_reg_3_1_0; +reg [15:0] feature_reg_3_1_1; +reg [15:0] feature_reg_3_2_0; +reg [15:0] feature_reg_3_2_1; +reg [15:0] feature_reg_3_3_0; +reg [15:0] feature_reg_3_3_1; +reg [15:0] feature_reg_3_4_0; +reg [15:0] feature_reg_3_4_1; +reg [15:0] feature_reg_3_5_0; +reg [15:0] feature_reg_3_5_1; +reg [15:0] feature_reg_4_0_0; +reg [15:0] feature_reg_4_0_1; +reg [15:0] feature_reg_4_1_0; +reg [15:0] feature_reg_4_1_1; +reg [15:0] feature_reg_4_2_0; +reg [15:0] feature_reg_4_2_1; +reg [15:0] feature_reg_4_3_0; +reg [15:0] feature_reg_4_3_1; +reg [15:0] feature_reg_4_4_0; +reg [15:0] feature_reg_4_4_1; +reg [15:0] feature_reg_4_5_0; +reg [15:0] feature_reg_4_5_1; +reg [15:0] feature_reg_5_0_0; +reg [15:0] feature_reg_5_0_1; +reg [15:0] feature_reg_5_1_0; +reg [15:0] feature_reg_5_1_1; +reg [15:0] feature_reg_5_2_0; +reg [15:0] feature_reg_5_2_1; +reg [15:0] feature_reg_5_3_0; +reg [15:0] feature_reg_5_3_1; +reg [15:0] feature_reg_5_4_0; +reg [15:0] feature_reg_5_4_1; +reg [15:0] feature_reg_5_5_0; +reg [15:0] feature_reg_5_5_1; + +always @ (posedge clk) begin + calculate_1 <= calculate; + calculate_2 <= calculate_1; + calculate_3 <= calculate_2; + //Valid pipeline + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + valid_12 <= valid_11; + if (i_valid) begin + input_buffer_count <= 0; + calculate <= 0; + end else begin + //Input buffering logic + if (input_buffer_count == 5) begin + calculate <= 1; + input_buffer_count <= 0; + end else begin + calculate <= 0; + input_buffer_count <= input_buffer_count + 1'b1; + end + input_buffer_5_0 <= i_result_0_3; + input_buffer_5_1 <= i_result_1_3; + input_buffer_5_2 <= i_result_2_3; + input_buffer_5_3 <= i_result_3_3; + input_buffer_5_4 <= i_result_4_3; + input_buffer_5_5 <= i_result_5_3; + end + input_buffer_0_0 <= input_buffer_1_0; + input_buffer_0_1 <= input_buffer_1_1; + input_buffer_0_2 <= input_buffer_1_2; + input_buffer_0_3 <= input_buffer_1_3; + input_buffer_0_4 <= input_buffer_1_4; + input_buffer_0_5 <= input_buffer_1_5; + input_buffer_1_0 <= input_buffer_2_0; + input_buffer_1_1 <= input_buffer_2_1; + input_buffer_1_2 <= input_buffer_2_2; + input_buffer_1_3 <= input_buffer_2_3; + input_buffer_1_4 <= input_buffer_2_4; + input_buffer_1_5 <= input_buffer_2_5; + input_buffer_2_0 <= input_buffer_3_0; + input_buffer_2_1 <= input_buffer_3_1; + input_buffer_2_2 <= input_buffer_3_2; + input_buffer_2_3 <= input_buffer_3_3; + input_buffer_2_4 <= input_buffer_3_4; + input_buffer_2_5 <= input_buffer_3_5; + input_buffer_3_0 <= input_buffer_4_0; + input_buffer_3_1 <= input_buffer_4_1; + input_buffer_3_2 <= input_buffer_4_2; + input_buffer_3_3 <= input_buffer_4_3; + input_buffer_3_4 <= input_buffer_4_4; + input_buffer_3_5 <= input_buffer_4_5; + input_buffer_4_0 <= input_buffer_5_0; + input_buffer_4_1 <= input_buffer_5_1; + input_buffer_4_2 <= input_buffer_5_2; + input_buffer_4_3 <= input_buffer_5_3; + input_buffer_4_4 <= input_buffer_5_4; + input_buffer_4_5 <= input_buffer_5_5; + //Pipelining to synchronize DSPs and non-DSPs + feature_reg_0_0_0 <= input_buffer_0_0; + feature_reg_0_1_0 <= input_buffer_0_1; + feature_reg_0_2_0 <= input_buffer_0_2; + feature_reg_0_3_0 <= input_buffer_0_3; + feature_reg_0_4_0 <= input_buffer_0_4; + feature_reg_0_5_0 <= input_buffer_0_5; + feature_reg_1_0_0 <= input_buffer_1_0; + feature_reg_1_1_0 <= input_buffer_1_1; + feature_reg_1_2_0 <= input_buffer_1_2; + feature_reg_1_3_0 <= input_buffer_1_3; + feature_reg_1_4_0 <= input_buffer_1_4; + feature_reg_1_5_0 <= input_buffer_1_5; + feature_reg_2_0_0 <= input_buffer_2_0; + feature_reg_2_1_0 <= input_buffer_2_1; + feature_reg_2_2_0 <= input_buffer_2_2; + feature_reg_2_3_0 <= input_buffer_2_3; + feature_reg_2_4_0 <= input_buffer_2_4; + feature_reg_2_5_0 <= input_buffer_2_5; + feature_reg_3_0_0 <= input_buffer_3_0; + feature_reg_3_1_0 <= input_buffer_3_1; + feature_reg_3_2_0 <= input_buffer_3_2; + feature_reg_3_3_0 <= input_buffer_3_3; + feature_reg_3_4_0 <= input_buffer_3_4; + feature_reg_3_5_0 <= input_buffer_3_5; + feature_reg_4_0_0 <= input_buffer_4_0; + feature_reg_4_1_0 <= input_buffer_4_1; + feature_reg_4_2_0 <= input_buffer_4_2; + feature_reg_4_3_0 <= input_buffer_4_3; + feature_reg_4_4_0 <= input_buffer_4_4; + feature_reg_4_5_0 <= input_buffer_4_5; + feature_reg_5_0_0 <= input_buffer_5_0; + feature_reg_5_1_0 <= input_buffer_5_1; + feature_reg_5_2_0 <= input_buffer_5_2; + feature_reg_5_3_0 <= input_buffer_5_3; + feature_reg_5_4_0 <= input_buffer_5_4; + feature_reg_5_5_0 <= input_buffer_5_5; + feature_reg_0_0_1 <= feature_reg_0_0_0; + feature_reg_0_1_1 <= feature_reg_0_1_0; + feature_reg_0_2_1 <= feature_reg_0_2_0; + feature_reg_0_3_1 <= feature_reg_0_3_0; + feature_reg_0_4_1 <= feature_reg_0_4_0; + feature_reg_0_5_1 <= feature_reg_0_5_0; + feature_reg_1_0_1 <= feature_reg_1_0_0; + feature_reg_1_1_1 <= feature_reg_1_1_0; + feature_reg_1_2_1 <= feature_reg_1_2_0; + feature_reg_1_3_1 <= feature_reg_1_3_0; + feature_reg_1_4_1 <= feature_reg_1_4_0; + feature_reg_1_5_1 <= feature_reg_1_5_0; + feature_reg_2_0_1 <= feature_reg_2_0_0; + feature_reg_2_1_1 <= feature_reg_2_1_0; + feature_reg_2_2_1 <= feature_reg_2_2_0; + feature_reg_2_3_1 <= feature_reg_2_3_0; + feature_reg_2_4_1 <= feature_reg_2_4_0; + feature_reg_2_5_1 <= feature_reg_2_5_0; + feature_reg_3_0_1 <= feature_reg_3_0_0; + feature_reg_3_1_1 <= feature_reg_3_1_0; + feature_reg_3_2_1 <= feature_reg_3_2_0; + feature_reg_3_3_1 <= feature_reg_3_3_0; + feature_reg_3_4_1 <= feature_reg_3_4_0; + feature_reg_3_5_1 <= feature_reg_3_5_0; + feature_reg_4_0_1 <= feature_reg_4_0_0; + feature_reg_4_1_1 <= feature_reg_4_1_0; + feature_reg_4_2_1 <= feature_reg_4_2_0; + feature_reg_4_3_1 <= feature_reg_4_3_0; + feature_reg_4_4_1 <= feature_reg_4_4_0; + feature_reg_4_5_1 <= feature_reg_4_5_0; + feature_reg_5_0_1 <= feature_reg_5_0_0; + feature_reg_5_1_1 <= feature_reg_5_1_0; + feature_reg_5_2_1 <= feature_reg_5_2_0; + feature_reg_5_3_1 <= feature_reg_5_3_0; + feature_reg_5_4_1 <= feature_reg_5_4_0; + feature_reg_5_5_1 <= feature_reg_5_5_0; + //Output Serializing logic + if (calculate_3) begin + output_buffer_0_0 <= rslt_buffer_0_0; + output_buffer_1_0 <= rslt_buffer_0_1; + output_buffer_2_0 <= rslt_buffer_0_2; + output_buffer_3_0 <= rslt_buffer_0_3; + output_buffer_4_0 <= rslt_buffer_0_4; + output_buffer_5_0 <= rslt_buffer_0_5; + output_buffer_0_1 <= rslt_buffer_1_0; + output_buffer_1_1 <= rslt_buffer_1_1; + output_buffer_2_1 <= rslt_buffer_1_2; + output_buffer_3_1 <= rslt_buffer_1_3; + output_buffer_4_1 <= rslt_buffer_1_4; + output_buffer_5_1 <= rslt_buffer_1_5; + output_buffer_0_2 <= rslt_buffer_2_0; + output_buffer_1_2 <= rslt_buffer_2_1; + output_buffer_2_2 <= rslt_buffer_2_2; + output_buffer_3_2 <= rslt_buffer_2_3; + output_buffer_4_2 <= rslt_buffer_2_4; + output_buffer_5_2 <= rslt_buffer_2_5; + output_buffer_0_3 <= rslt_buffer_3_0; + output_buffer_1_3 <= rslt_buffer_3_1; + output_buffer_2_3 <= rslt_buffer_3_2; + output_buffer_3_3 <= rslt_buffer_3_3; + output_buffer_4_3 <= rslt_buffer_3_4; + output_buffer_5_3 <= rslt_buffer_3_5; + output_buffer_0_4 <= rslt_buffer_4_0; + output_buffer_1_4 <= rslt_buffer_4_1; + output_buffer_2_4 <= rslt_buffer_4_2; + output_buffer_3_4 <= rslt_buffer_4_3; + output_buffer_4_4 <= rslt_buffer_4_4; + output_buffer_5_4 <= rslt_buffer_4_5; + output_buffer_0_5 <= rslt_buffer_5_0; + output_buffer_1_5 <= rslt_buffer_5_1; + output_buffer_2_5 <= rslt_buffer_5_2; + output_buffer_3_5 <= rslt_buffer_5_3; + output_buffer_4_5 <= rslt_buffer_5_4; + output_buffer_5_5 <= rslt_buffer_5_5; + end else begin + output_buffer_0_0 <= output_buffer_0_1; + output_buffer_0_1 <= output_buffer_0_2; + output_buffer_0_2 <= output_buffer_0_3; + output_buffer_0_3 <= output_buffer_0_4; + output_buffer_0_4 <= output_buffer_0_5; + output_buffer_1_0 <= output_buffer_1_1; + output_buffer_1_1 <= output_buffer_1_2; + output_buffer_1_2 <= output_buffer_1_3; + output_buffer_1_3 <= output_buffer_1_4; + output_buffer_1_4 <= output_buffer_1_5; + output_buffer_2_0 <= output_buffer_2_1; + output_buffer_2_1 <= output_buffer_2_2; + output_buffer_2_2 <= output_buffer_2_3; + output_buffer_2_3 <= output_buffer_2_4; + output_buffer_2_4 <= output_buffer_2_5; + output_buffer_3_0 <= output_buffer_3_1; + output_buffer_3_1 <= output_buffer_3_2; + output_buffer_3_2 <= output_buffer_3_3; + output_buffer_3_3 <= output_buffer_3_4; + output_buffer_3_4 <= output_buffer_3_5; + output_buffer_4_0 <= output_buffer_4_1; + output_buffer_4_1 <= output_buffer_4_2; + output_buffer_4_2 <= output_buffer_4_3; + output_buffer_4_3 <= output_buffer_4_4; + output_buffer_4_4 <= output_buffer_4_5; + output_buffer_5_0 <= output_buffer_5_1; + output_buffer_5_1 <= output_buffer_5_2; + output_buffer_5_2 <= output_buffer_5_3; + output_buffer_5_3 <= output_buffer_5_4; + output_buffer_5_4 <= output_buffer_5_5; + end +end + +////// FIRST COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD00 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_2), + .by(input_buffer_2_0), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_1_0), + .resultb(dsp_out_1_1) +); + +winograd_dsp_16 winograd_dsp_16_WD10 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_2_4), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_1_2), + .resultb(dsp_out_1_3) +); + +winograd_dsp_16 winograd_dsp_16_WD20 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_2), + .by(input_buffer_1_0), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_1_4), + .resultb(dsp_out_1_5) +); + +winograd_dsp_16 winograd_dsp_16_WD30 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_1_6), + .resultb(dsp_out_1_7) +); + +winograd_dsp_16 winograd_dsp_16_WD40 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_0), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_1_8), + .resultb(dsp_out_1_9) +); + +winograd_dsp_16 winograd_dsp_16_WD50 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_4), + .by(input_buffer_5_2), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_1_10), + .resultb(dsp_out_1_11) +); + +////// SECOND COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD01 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_0), + .resultb(dsp_out_2_1) +); + +winograd_dsp_16 winograd_dsp_16_WD11 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_2), + .resultb(dsp_out_2_3) +); + +winograd_dsp_16 winograd_dsp_16_WD21 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_4), + .resultb(dsp_out_2_5) +); + +winograd_dsp_16 winograd_dsp_16_WD31 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_6), + .resultb(dsp_out_2_7) +); + +////// THIRD COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD02 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_0), + .resultb(dsp_out_3_1) +); + +winograd_dsp_16 winograd_dsp_16_WD12 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_2), + .resultb(dsp_out_3_3) +); + +winograd_dsp_16 winograd_dsp_16_WD22 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_4), + .resultb(dsp_out_3_5) +); + +winograd_dsp_16 winograd_dsp_16_WD32 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_6), + .resultb(dsp_out_3_7) +); + +////// FOURTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD03 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_0), + .resultb(dsp_out_4_1) +); + +winograd_dsp_16 winograd_dsp_16_WD13 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_2), + .resultb(dsp_out_4_3) +); + +winograd_dsp_16 winograd_dsp_16_WD23 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_4), + .resultb(dsp_out_4_5) +); + +winograd_dsp_16 winograd_dsp_16_WD33 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_6), + .resultb(dsp_out_4_7) +); + +////// FIFTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD04 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_0), + .resultb(dsp_out_5_1) +); + +winograd_dsp_16 winograd_dsp_16_WD14 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_2), + .resultb(dsp_out_5_3) +); + +winograd_dsp_16 winograd_dsp_16_WD24 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_4), + .resultb(dsp_out_5_5) +); + +winograd_dsp_16 winograd_dsp_16_WD34 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_6), + .resultb(dsp_out_5_7) +); + +////// SIXTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD05 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_3), + .by(input_buffer_2_1), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_6_0), + .resultb(dsp_out_6_1) +); + +winograd_dsp_16 winograd_dsp_16_WD15 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_5), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_6_2), + .resultb(dsp_out_6_3) +); + +winograd_dsp_16 winograd_dsp_16_WD25 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_3), + .by(input_buffer_1_3), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_6_4), + .resultb(dsp_out_6_5) +); + +winograd_dsp_16 winograd_dsp_16_WD35 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_3_3), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_6_6), + .resultb(dsp_out_6_7) +); + +winograd_dsp_16 winograd_dsp_16_WD45 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_3), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_6_8), + .resultb(dsp_out_6_9) +); + +winograd_dsp_16 winograd_dsp_16_WD55 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_5), + .by(input_buffer_5_3), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_6_10), + .resultb(dsp_out_6_11) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA00 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_0_1[11:0], 4'b0000}), + .data1x(dsp_out_1_0), + .data2x({feature_reg_0_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_1), + .data4x(dsp_out_1_2), + .data5x(dsp_out_1_3), + .data6x({feature_reg_4_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_4), + .data8x(feature_reg_4_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_0) +); + +wire [15:0] f1, f2, f3, f4; +assign f1 = -{feature_reg_1_0_1[11:0], 4'b0000}; +assign f2 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f3 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f4 = -{feature_reg_2_4_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA10 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_1_5), + .data1x(f1), + .data2x(f2), + .data3x(f3), + .data4x(dsp_out_1_6), + .data5x(f4), + .data6x({feature_reg_3_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_7), + .data8x(feature_reg_3_4_1), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_0) +); + +wire [15:0] f5, f6, f7, f8, f9, f10; +assign f5 = -dsp_out_1_5; +assign f6 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f7 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f8 = -{feature_reg_3_0_1[13:0], 2'b00}; +assign f9 = -dsp_out_1_7; +assign f10 = -feature_reg_3_4_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA20 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f5), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(f6), + .data4x(dsp_out_1_6), + .data5x(f7), + .data6x(f8), + .data7x(f9), + .data8x(f10), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_0) +); + +wire [15:0] f11, f12, f13, f14, f15, f16, f17; +assign f11 = -{feature_reg_1_0_1[12:0], 3'b000}; +assign f12 = -{feature_reg_1_4_1[14:0], 1'b0}; +assign f13 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f14 = -feature_reg_2_4_1; +assign f15 = dsp_out_1_5 >>> 1; +assign f16 = dsp_out_1_6 >>> 2; +assign f17 = dsp_out_1_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA30 ( + .clock(clk), + .clken(calculate_2), + .data0x(f15), + .data1x(f11), + .data2x(f12), + .data3x(f13), + .data4x(f16), + .data5x(f14), + .data6x({feature_reg_3_0_1[12:0], 3'b000}), + .data7x(f17), + .data8x({feature_reg_3_4_1[14:0], 1'b0}), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_0) +); + +wire [15:0] f18, f19, f20, f21, f22, f23, f23b; +assign f18 = -(dsp_out_1_5 >>> 1); +assign f19 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f20 = -feature_reg_2_4_1; +assign f21 = -{feature_reg_3_0_1[12:0], 3'b000}; +assign f22 = -(dsp_out_1_7 <<< 1); +assign f23 = -{feature_reg_3_4_1[14:0], 1'b0}; +assign f23b = dsp_out_1_6 >>> 2; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA40 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[12:0], 3'b000}), + .data1x(f18), + .data2x({feature_reg_1_4_1[14:0], 1'b0}), + .data3x(f19), + .data4x(f23b), + .data5x(f20), + .data6x(f21), + .data7x(f22), + .data8x(f23), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_0) +); + +wire [15:0] f24; +assign f24 = -dsp_out_1_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA50 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f24), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_8), + .data4x(dsp_out_1_9), + .data5x(dsp_out_1_10), + .data6x({feature_reg_5_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_11), + .data8x(feature_reg_5_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_0) +); + +wire [15:0] f25, f26, f27, f28; +assign f25 = -{feature_reg_0_2_1[11:0], 4'b0000}; +assign f26 = -{feature_reg_0_1_1[11:0], 4'b0000}; +assign f27 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f28 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA01 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[13:0], 2'b00}), + .data1x(f25), + .data2x(f26), + .data3x({feature_reg_0_4_1[13:0], 2'b00}), + .data4x(dsp_out_2_0), + .data5x(dsp_out_2_1), + .data6x(dsp_out_2_2), + .data7x(dsp_out_2_3), + .data8x(f27), + .data9x(f28), + .data10x(feature_reg_4_3_1), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_1) +); + +wire [15:0] f29, f30, f31, f32, f33, f34, f35, f36; +assign f29 = -{feature_reg_1_3_1[13:0], 2'b00}; +assign f30 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f31 = -{feature_reg_2_3_1[13:0], 2'b00}; +assign f32 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f33 = -{feature_reg_3_1_1[13:0], 2'b00}; +assign f34 = -{feature_reg_3_2_1[13:0], 2'b00}; +assign f35 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f36 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA11 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0], 4'b0000}), + .data1x({feature_reg_1_2_1[11:0], 4'b0000}), + .data2x(f29), + .data3x(f30), + .data4x({feature_reg_2_1_1[11:0], 4'b0000}), + .data5x({feature_reg_2_2_1[11:0], 4'b0000}), + .data6x(f31), + .data7x(f32), + .data8x(f33), + .data9x(f34), + .data10x(feature_reg_3_3_1), + .data11x(feature_reg_3_4_1), + .data12x(f35), + .data13x(f36), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_1) +); + +wire [15:0] f37, f38, f39, f40, f41, f42, f43, f44; +assign f37 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f38 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f39 = -{feature_reg_2_3_1[13:0],2'b00}; +assign f40 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f41 = -feature_reg_3_3_1; +assign f42 = -feature_reg_3_4_1; +assign f43 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f44 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA21 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f37), + .data2x(f38), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[11:0],4'b0000}), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x(f39), + .data7x(f40), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(f41), + .data11x(f42), + .data12x(f43), + .data13x(f44), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_1) +); + +wire [15:0] f45, f46, f47, f48, f49, f50, f51, f52; +assign f45 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f46 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f47 = -feature_reg_2_3_1; +assign f48 = -feature_reg_2_4_1; +assign f49 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f50 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f51 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f52 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA31 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[12:0],3'b000}), + .data2x(f45), + .data3x(f46), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f47), + .data7x(f48), + .data8x(f49), + .data9x(f50), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f51), + .data13x(f52), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_1) +); + +wire [15:0] f53, f54, f55, f56, f57, f58, f59, f60; +assign f53 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f54 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f55 = -feature_reg_2_3_1; +assign f56 = -feature_reg_2_4_1; +assign f57 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f58 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f59 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f60 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA41 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[14:0],1'b0}), + .data1x(f53), + .data2x(f54), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f55), + .data7x(f56), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x(f57), + .data11x(f58), + .data12x(f59), + .data13x(f60), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_1) +); + +wire [15:0] f61, f62, f63, f64; +assign f61 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f62 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f63 = -{feature_reg_5_1_1[13:0],2'b00}; +assign f64 = -{feature_reg_5_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA51 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f61), + .data2x(f62), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_2_4), + .data5x(dsp_out_2_5), + .data6x(dsp_out_2_6), + .data7x(dsp_out_2_7), + .data8x(f63), + .data9x(f64), + .data10x(feature_reg_5_3_1), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_1) +); + +wire [15:0] f65, f66, f67, f68; +assign f65 = -{feature_reg_0_2_1[11:0],4'b0000}; +assign f66 = -{feature_reg_0_3_1[13:0],2'b00}; +assign f67 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f68 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA02 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(f65), + .data2x(f66), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_3_0), + .data5x(dsp_out_3_1), + .data6x(dsp_out_3_2), + .data7x(dsp_out_3_3), + .data8x({feature_reg_4_1_1[13:0],2'b00}), + .data9x(f67), + .data10x(f68), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_2) +); + +wire [15:0] f69, f70, f71, f72, f73, f74, f75, f76; +assign f69 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f70 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f71 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f72 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f73 = -{feature_reg_3_2_1[13:0],2'b00}; +assign f74 = -feature_reg_3_3_1; +assign f75 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f76 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA12 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[11:0],4'b0000}), + .data1x(f69), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f70), + .data4x(f71), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f72), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f73), + .data10x(f74), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f75), + .data14x(f76), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_2) +); + +wire [15:0] f77, f78, f79, f80, f81, f82, f83, f84; +assign f77 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f78 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f79 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f80 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f81 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f82 = -feature_reg_3_4_1; +assign f83 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f84 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA22 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f77), + .data2x(f78), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f79), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f80), + .data8x(f81), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(feature_reg_3_3_1), + .data11x(f82), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f83), + .data14x(f84), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_2) +); + +wire [15:0] f85, f86, f87, f88, f89, f90, f91, f92; +assign f85 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f86 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f87 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f88 = -feature_reg_2_4_1; +assign f89 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f90 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f91 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f92 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA32 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[12:0],3'b000}), + .data1x(f85), + .data2x({feature_reg_1_3_1[14:0],1'b0}), + .data3x(f86), + .data4x(f87), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f88), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x(f89), + .data10x(f90), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f91), + .data14x(f92), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_2) +); + +wire [15:0] f93, f94, f95, f96, f97, f98, f99, f100; +assign f93 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f94 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f95 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f96 = -feature_reg_2_4_1; +assign f97 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f98 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f99 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f100 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA42 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f93), + .data2x(f94), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f95), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f96), + .data8x(f97), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f98), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f99), + .data14x(f100), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_2) +); + +wire [15:0] f101, f102, f103, f104; +assign f101 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f102 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f103 = -{feature_reg_5_2_1[13:0],2'b00}; +assign f104 = -feature_reg_5_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA52 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f101), + .data2x(f102), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_3_4), + .data5x(dsp_out_3_5), + .data6x(dsp_out_3_6), + .data7x(dsp_out_3_7), + .data8x({feature_reg_5_1_1[13:0],2'b00}), + .data9x(f103), + .data10x(f104), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_2) +); + +wire [15:0] f105, f106, f107, f108; +assign f105 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f106 = -{feature_reg_0_1_1[12:0],3'b000}; +assign f107 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f108 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA03 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[12:0],3'b000}), + .data1x(f105), + .data2x(f106), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_4_0), + .data5x(dsp_out_4_1), + .data6x(dsp_out_4_2), + .data7x(dsp_out_4_3), + .data8x(f107), + .data9x(f108), + .data10x({feature_reg_4_3_1[14:0],1'b0}), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_3) +); + +wire [15:0] f109, f110, f111, f112, f113, f114, f115, f116; +assign f109 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f110 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f111 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f112 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f113 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f114 = -feature_reg_3_2_1; +assign f115 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f116 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA13 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[13:0],2'b00}), + .data2x(f109), + .data3x(f110), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f111), + .data7x(f112), + .data8x(f113), + .data9x(f114), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(feature_reg_3_4_1), + .data12x(f115), + .data13x(f116), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_3) +); + +wire [15:0] f117, f118, f119, f120, f121, f122, f123, f124; +assign f117 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f118 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f119 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f120 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f121 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f122 = -feature_reg_3_4_1; +assign f123 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f124 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA23 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f117), + .data2x(f118), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f119), + .data7x(f120), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(feature_reg_3_2_1), + .data10x(f121), + .data11x(f122), + .data12x(f123), + .data13x(f124), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_3) +); + +wire [15:0] f125, f126, f127, f128, f129, f130, f131, f132; +assign f125 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f126 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f127 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f128 = -feature_reg_2_4_1; +assign f129 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f130 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f131 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f132 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA33 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x({feature_reg_1_2_1[14:0],1'b0}), + .data2x(f125), + .data3x(f126), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f127), + .data7x(f128), + .data8x(f129), + .data9x(f130), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f131), + .data13x(f132), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_3) +); + +wire [15:0] f133, f134, f135, f136, f137, f138, f139, f140; +assign f133 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f134 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f135 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f136 = -feature_reg_2_4_1; +assign f137 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f138 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f139 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f140 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA43 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f133), + .data2x(f134), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f135), + .data7x(f136), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x(f137), + .data11x(f138), + .data12x(f139), + .data13x(f140), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_3) +); + +wire [15:0] f141, f142, f143, f144; +assign f141 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f142 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f143 = -{feature_reg_5_1_1[14:0],1'b0}; +assign f144 = -feature_reg_5_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA53 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f141), + .data2x(f142), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_4_4), + .data5x(dsp_out_4_5), + .data6x(dsp_out_4_6), + .data7x(dsp_out_4_7), + .data8x(f143), + .data9x(f144), + .data10x({feature_reg_5_3_1[14:0],1'b0}), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_3) +); + +wire [15:0] f145, f146, f147, f148; +assign f145 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f146 = -{feature_reg_0_3_1[12:0],3'b000}; +assign f147 = -feature_reg_4_2_1; +assign f148 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA04 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[12:0],3'b000}), + .data1x(f145), + .data2x(f146), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_5_0), + .data5x(dsp_out_5_1), + .data6x(dsp_out_5_2), + .data7x(dsp_out_5_3), + .data8x({feature_reg_4_1_1[14:0],1'b0}), + .data9x(f147), + .data10x(f148), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_4) +); + +wire [15:0] f149, f150, f151, f152, f153, f154, f155, f156; +assign f149 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f150 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f151 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f152 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f153 = -feature_reg_3_2_1; +assign f154 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f155 = -feature_reg_4_2_1; +assign f156 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA14 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[13:0],2'b00}), + .data1x(f149), + .data2x({feature_reg_1_3_1[12:0],3'b000}), + .data3x(f150), + .data4x(f151), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f152), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(f153), + .data10x(f154), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f155), + .data14x(f156), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_4) +); + +wire [15:0] f157, f158, f159, f160, f161, f162, f163, f164; +assign f157 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f158 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f159 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f160 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f161 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f162 = -feature_reg_3_4_1; +assign f163 = -feature_reg_4_2_1; +assign f164 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA24 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f157), + .data2x(f158), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f159), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f160), + .data8x(f161), + .data9x(feature_reg_3_2_1), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f162), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f163), + .data14x(f164), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_4) +); + +wire [15:0] f165, f166, f167, f168, f169, f170, f171, f172; +assign f165 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f166 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f167 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f168 = -feature_reg_2_4_1; +assign f169 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f170 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f171 = -feature_reg_4_2_1; +assign f172 = -{feature_reg_4_1_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA34 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[14:0],1'b0}), + .data1x(f165), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f166), + .data4x(f167), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f168), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f169), + .data10x(f170), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f171), + .data14x(f172), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_4) +); + +wire [15:0] f173, f174, f175, f176, f177, f178, f179, f180; +assign f173 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f174 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f175 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f176 = -feature_reg_2_4_1; +assign f177 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f178 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f179 = -feature_reg_4_2_1; +assign f180 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA44 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x(f173), + .data2x(f174), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f175), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f176), + .data8x(f177), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x(f178), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f179), + .data14x(f180), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_4) +); + +wire [15:0] f181, f182, f183, f184; +assign f181 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f182 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f183 = -feature_reg_5_2_1; +assign f184 = -{feature_reg_5_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA54 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f181), + .data2x(f182), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_5_4), + .data5x(dsp_out_5_5), + .data6x(dsp_out_5_6), + .data7x(dsp_out_5_7), + .data8x({feature_reg_5_1_1[14:0],1'b0}), + .data9x(f183), + .data10x(f184), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_4) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA05 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(dsp_out_6_0), + .data2x({feature_reg_0_5_1[13:0],2'b00}), + .data3x(dsp_out_6_1), + .data4x(dsp_out_6_2), + .data5x(dsp_out_6_3), + .data6x({feature_reg_4_1_1[13:0],2'b00}), + .data7x(dsp_out_6_4), + .data8x(feature_reg_4_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_5) +); + +wire [15:0] f185, f186, f187, f188; +assign f185 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f186 = -{feature_reg_1_5_1[13:0],2'b00}; +assign f187 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f188 = -{feature_reg_2_5_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA15 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_6_5), + .data1x(f185), + .data2x(f186), + .data3x(f187), + .data4x(dsp_out_6_6), + .data5x(f188), + .data6x({feature_reg_3_1_1[13:0],2'b00}), + .data7x(dsp_out_6_7), + .data8x(feature_reg_3_5_1), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_5) +); + +wire [15:0] f189, f190, f191, f192, f193, f194; +assign f189 = -dsp_out_6_5; +assign f190 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f191 = -{feature_reg_2_5_1[13:0],2'b00}; +assign f192 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f193 = -dsp_out_6_7; +assign f194 = -feature_reg_3_5_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA25 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f189), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(f190), + .data4x(dsp_out_6_6), + .data5x(f191), + .data6x(f192), + .data7x(f193), + .data8x(f194), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_5) +); + +wire [15:0] f195, f196, f197, f198, f199, f200, f201; +assign f195 = dsp_out_6_5 >>> 1; +assign f196 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f197 = -{feature_reg_1_5_1[14:0],1'b0}; +assign f198 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f199 = dsp_out_6_6 >>> 2; +assign f200 = -feature_reg_2_5_1; +assign f201 = dsp_out_6_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA35 ( + .clock(clk), + .clken(calculate_2), + .data0x(f195), + .data1x(f196), + .data2x(f197), + .data3x(f198), + .data4x(f199), + .data5x(f200), + .data6x({feature_reg_3_1_1[12:0],3'b000}), + .data7x(f201), + .data8x({feature_reg_3_5_1[14:0],1'b0}), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_5) +); + +wire [15:0] f202, f203, f204, f205, f206, f207, f208; +assign f202 = -(dsp_out_6_5 >>> 1); +assign f203 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f204 = dsp_out_6_6 >>> 2; +assign f205 = -feature_reg_2_5_1; +assign f206 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f207 = -(dsp_out_6_7 <<< 1); +assign f208 = -{feature_reg_3_5_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA45 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f202), + .data2x({feature_reg_1_5_1[14:0],1'b0}), + .data3x(f203), + .data4x(f204), + .data5x(f205), + .data6x(f206), + .data7x(f207), + .data8x(f208), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_5) +); + +wire [15:0] f209; +assign f209 = -dsp_out_6_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA55 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f209), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(dsp_out_6_8), + .data4x(dsp_out_6_9), + .data5x(dsp_out_6_10), + .data6x({feature_reg_5_1_1[13:0],2'b00}), + .data7x(dsp_out_6_11), + .data8x(feature_reg_5_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_5) +); + +assign o_feature_0 = output_buffer_0_0[15:0]; +assign o_feature_1 = output_buffer_1_0[15:0]; +assign o_feature_2 = output_buffer_2_0[15:0]; +assign o_feature_3 = output_buffer_3_0[15:0]; +assign o_feature_4 = output_buffer_4_0[15:0]; +assign o_feature_5 = output_buffer_5_0[15:0]; +assign o_valid = valid_9; + +endmodule + +module winograd_transform_2 ( + input clk, + input i_valid, + input [15:0] i_result_0_0, + input [15:0] i_result_0_1, + input [15:0] i_result_0_2, + input [15:0] i_result_0_3, + input [15:0] i_result_1_0, + input [15:0] i_result_1_1, + input [15:0] i_result_1_2, + input [15:0] i_result_1_3, + input [15:0] i_result_2_0, + input [15:0] i_result_2_1, + input [15:0] i_result_2_2, + input [15:0] i_result_2_3, + input [15:0] i_result_3_0, + input [15:0] i_result_3_1, + input [15:0] i_result_3_2, + input [15:0] i_result_3_3, + input [15:0] i_result_4_0, + input [15:0] i_result_4_1, + input [15:0] i_result_4_2, + input [15:0] i_result_4_3, + input [15:0] i_result_5_0, + input [15:0] i_result_5_1, + input [15:0] i_result_5_2, + input [15:0] i_result_5_3, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output [15:0] o_feature_2, + output [15:0] o_feature_3, + output [15:0] o_feature_4, + output [15:0] o_feature_5, + output o_valid +); + +reg [15:0] input_buffer_0_0; +reg [19:0] output_buffer_0_0; +wire [19:0] rslt_buffer_0_0; +reg [15:0] input_buffer_0_1; +reg [19:0] output_buffer_0_1; +wire [19:0] rslt_buffer_0_1; +reg [15:0] input_buffer_0_2; +reg [19:0] output_buffer_0_2; +wire [19:0] rslt_buffer_0_2; +reg [15:0] input_buffer_0_3; +reg [19:0] output_buffer_0_3; +wire [19:0] rslt_buffer_0_3; +reg [15:0] input_buffer_0_4; +reg [19:0] output_buffer_0_4; +wire [19:0] rslt_buffer_0_4; +reg [15:0] input_buffer_0_5; +reg [19:0] output_buffer_0_5; +wire [19:0] rslt_buffer_0_5; +reg [15:0] input_buffer_1_0; +reg [19:0] output_buffer_1_0; +wire [19:0] rslt_buffer_1_0; +reg [15:0] input_buffer_1_1; +reg [19:0] output_buffer_1_1; +wire [19:0] rslt_buffer_1_1; +reg [15:0] input_buffer_1_2; +reg [19:0] output_buffer_1_2; +wire [19:0] rslt_buffer_1_2; +reg [15:0] input_buffer_1_3; +reg [19:0] output_buffer_1_3; +wire [19:0] rslt_buffer_1_3; +reg [15:0] input_buffer_1_4; +reg [19:0] output_buffer_1_4; +wire [19:0] rslt_buffer_1_4; +reg [15:0] input_buffer_1_5; +reg [19:0] output_buffer_1_5; +wire [19:0] rslt_buffer_1_5; +reg [15:0] input_buffer_2_0; +reg [19:0] output_buffer_2_0; +wire [19:0] rslt_buffer_2_0; +reg [15:0] input_buffer_2_1; +reg [19:0] output_buffer_2_1; +wire [19:0] rslt_buffer_2_1; +reg [15:0] input_buffer_2_2; +reg [19:0] output_buffer_2_2; +wire [19:0] rslt_buffer_2_2; +reg [15:0] input_buffer_2_3; +reg [19:0] output_buffer_2_3; +wire [19:0] rslt_buffer_2_3; +reg [15:0] input_buffer_2_4; +reg [19:0] output_buffer_2_4; +wire [19:0] rslt_buffer_2_4; +reg [15:0] input_buffer_2_5; +reg [19:0] output_buffer_2_5; +wire [19:0] rslt_buffer_2_5; +reg [15:0] input_buffer_3_0; +reg [19:0] output_buffer_3_0; +wire [19:0] rslt_buffer_3_0; +reg [15:0] input_buffer_3_1; +reg [19:0] output_buffer_3_1; +wire [19:0] rslt_buffer_3_1; +reg [15:0] input_buffer_3_2; +reg [19:0] output_buffer_3_2; +wire [19:0] rslt_buffer_3_2; +reg [15:0] input_buffer_3_3; +reg [19:0] output_buffer_3_3; +wire [19:0] rslt_buffer_3_3; +reg [15:0] input_buffer_3_4; +reg [19:0] output_buffer_3_4; +wire [19:0] rslt_buffer_3_4; +reg [15:0] input_buffer_3_5; +reg [19:0] output_buffer_3_5; +wire [19:0] rslt_buffer_3_5; +reg [15:0] input_buffer_4_0; +reg [19:0] output_buffer_4_0; +wire [19:0] rslt_buffer_4_0; +reg [15:0] input_buffer_4_1; +reg [19:0] output_buffer_4_1; +wire [19:0] rslt_buffer_4_1; +reg [15:0] input_buffer_4_2; +reg [19:0] output_buffer_4_2; +wire [19:0] rslt_buffer_4_2; +reg [15:0] input_buffer_4_3; +reg [19:0] output_buffer_4_3; +wire [19:0] rslt_buffer_4_3; +reg [15:0] input_buffer_4_4; +reg [19:0] output_buffer_4_4; +wire [19:0] rslt_buffer_4_4; +reg [15:0] input_buffer_4_5; +reg [19:0] output_buffer_4_5; +wire [19:0] rslt_buffer_4_5; +reg [15:0] input_buffer_5_0; +reg [19:0] output_buffer_5_0; +wire [19:0] rslt_buffer_5_0; +reg [15:0] input_buffer_5_1; +reg [19:0] output_buffer_5_1; +wire [19:0] rslt_buffer_5_1; +reg [15:0] input_buffer_5_2; +reg [19:0] output_buffer_5_2; +wire [19:0] rslt_buffer_5_2; +reg [15:0] input_buffer_5_3; +reg [19:0] output_buffer_5_3; +wire [19:0] rslt_buffer_5_3; +reg [15:0] input_buffer_5_4; +reg [19:0] output_buffer_5_4; +wire [19:0] rslt_buffer_5_4; +reg [15:0] input_buffer_5_5; +reg [19:0] output_buffer_5_5; +wire [19:0] rslt_buffer_5_5; +reg calculate, calculate_1, calculate_2, calculate_3; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg valid_12; +reg [2:0] input_buffer_count; +wire [15:0] dsp_out_1_0; +wire [15:0] dsp_out_1_1; +wire [15:0] dsp_out_1_2; +wire [15:0] dsp_out_1_3; +wire [15:0] dsp_out_1_4; +wire [15:0] dsp_out_1_5; +wire [15:0] dsp_out_1_6; +wire [15:0] dsp_out_1_7; +wire [15:0] dsp_out_1_8; +wire [15:0] dsp_out_1_9; +wire [15:0] dsp_out_1_10; +wire [15:0] dsp_out_1_11; +wire [15:0] dsp_out_2_0; +wire [15:0] dsp_out_2_1; +wire [15:0] dsp_out_2_2; +wire [15:0] dsp_out_2_3; +wire [15:0] dsp_out_2_4; +wire [15:0] dsp_out_2_5; +wire [15:0] dsp_out_2_6; +wire [15:0] dsp_out_2_7; +wire [15:0] dsp_out_3_0; +wire [15:0] dsp_out_3_1; +wire [15:0] dsp_out_3_2; +wire [15:0] dsp_out_3_3; +wire [15:0] dsp_out_3_4; +wire [15:0] dsp_out_3_5; +wire [15:0] dsp_out_3_6; +wire [15:0] dsp_out_3_7; +wire [15:0] dsp_out_4_0; +wire [15:0] dsp_out_4_1; +wire [15:0] dsp_out_4_2; +wire [15:0] dsp_out_4_3; +wire [15:0] dsp_out_4_4; +wire [15:0] dsp_out_4_5; +wire [15:0] dsp_out_4_6; +wire [15:0] dsp_out_4_7; +wire [15:0] dsp_out_5_0; +wire [15:0] dsp_out_5_1; +wire [15:0] dsp_out_5_2; +wire [15:0] dsp_out_5_3; +wire [15:0] dsp_out_5_4; +wire [15:0] dsp_out_5_5; +wire [15:0] dsp_out_5_6; +wire [15:0] dsp_out_5_7; +wire [15:0] dsp_out_6_0; +wire [15:0] dsp_out_6_1; +wire [15:0] dsp_out_6_2; +wire [15:0] dsp_out_6_3; +wire [15:0] dsp_out_6_4; +wire [15:0] dsp_out_6_5; +wire [15:0] dsp_out_6_6; +wire [15:0] dsp_out_6_7; +wire [15:0] dsp_out_6_8; +wire [15:0] dsp_out_6_9; +wire [15:0] dsp_out_6_10; +wire [15:0] dsp_out_6_11; +reg [15:0] feature_reg_0_0_0; +reg [15:0] feature_reg_0_0_1; +reg [15:0] feature_reg_0_1_0; +reg [15:0] feature_reg_0_1_1; +reg [15:0] feature_reg_0_2_0; +reg [15:0] feature_reg_0_2_1; +reg [15:0] feature_reg_0_3_0; +reg [15:0] feature_reg_0_3_1; +reg [15:0] feature_reg_0_4_0; +reg [15:0] feature_reg_0_4_1; +reg [15:0] feature_reg_0_5_0; +reg [15:0] feature_reg_0_5_1; +reg [15:0] feature_reg_1_0_0; +reg [15:0] feature_reg_1_0_1; +reg [15:0] feature_reg_1_1_0; +reg [15:0] feature_reg_1_1_1; +reg [15:0] feature_reg_1_2_0; +reg [15:0] feature_reg_1_2_1; +reg [15:0] feature_reg_1_3_0; +reg [15:0] feature_reg_1_3_1; +reg [15:0] feature_reg_1_4_0; +reg [15:0] feature_reg_1_4_1; +reg [15:0] feature_reg_1_5_0; +reg [15:0] feature_reg_1_5_1; +reg [15:0] feature_reg_2_0_0; +reg [15:0] feature_reg_2_0_1; +reg [15:0] feature_reg_2_1_0; +reg [15:0] feature_reg_2_1_1; +reg [15:0] feature_reg_2_2_0; +reg [15:0] feature_reg_2_2_1; +reg [15:0] feature_reg_2_3_0; +reg [15:0] feature_reg_2_3_1; +reg [15:0] feature_reg_2_4_0; +reg [15:0] feature_reg_2_4_1; +reg [15:0] feature_reg_2_5_0; +reg [15:0] feature_reg_2_5_1; +reg [15:0] feature_reg_3_0_0; +reg [15:0] feature_reg_3_0_1; +reg [15:0] feature_reg_3_1_0; +reg [15:0] feature_reg_3_1_1; +reg [15:0] feature_reg_3_2_0; +reg [15:0] feature_reg_3_2_1; +reg [15:0] feature_reg_3_3_0; +reg [15:0] feature_reg_3_3_1; +reg [15:0] feature_reg_3_4_0; +reg [15:0] feature_reg_3_4_1; +reg [15:0] feature_reg_3_5_0; +reg [15:0] feature_reg_3_5_1; +reg [15:0] feature_reg_4_0_0; +reg [15:0] feature_reg_4_0_1; +reg [15:0] feature_reg_4_1_0; +reg [15:0] feature_reg_4_1_1; +reg [15:0] feature_reg_4_2_0; +reg [15:0] feature_reg_4_2_1; +reg [15:0] feature_reg_4_3_0; +reg [15:0] feature_reg_4_3_1; +reg [15:0] feature_reg_4_4_0; +reg [15:0] feature_reg_4_4_1; +reg [15:0] feature_reg_4_5_0; +reg [15:0] feature_reg_4_5_1; +reg [15:0] feature_reg_5_0_0; +reg [15:0] feature_reg_5_0_1; +reg [15:0] feature_reg_5_1_0; +reg [15:0] feature_reg_5_1_1; +reg [15:0] feature_reg_5_2_0; +reg [15:0] feature_reg_5_2_1; +reg [15:0] feature_reg_5_3_0; +reg [15:0] feature_reg_5_3_1; +reg [15:0] feature_reg_5_4_0; +reg [15:0] feature_reg_5_4_1; +reg [15:0] feature_reg_5_5_0; +reg [15:0] feature_reg_5_5_1; + +always @ (posedge clk) begin + calculate_1 <= calculate; + calculate_2 <= calculate_1; + calculate_3 <= calculate_2; + //Valid pipeline + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + valid_12 <= valid_11; + if (i_valid) begin + input_buffer_count <= 0; + calculate <= 0; + end else begin + //Input buffering logic + if (input_buffer_count == 5) begin + calculate <= 1; + input_buffer_count <= 0; + end else begin + calculate <= 0; + input_buffer_count <= input_buffer_count + 1'b1; + end + input_buffer_5_0 <= i_result_0_2; + input_buffer_5_1 <= i_result_1_2; + input_buffer_5_2 <= i_result_2_2; + input_buffer_5_3 <= i_result_3_2; + input_buffer_5_4 <= i_result_4_2; + input_buffer_5_5 <= i_result_5_2; + end + input_buffer_0_0 <= input_buffer_1_0; + input_buffer_0_1 <= input_buffer_1_1; + input_buffer_0_2 <= input_buffer_1_2; + input_buffer_0_3 <= input_buffer_1_3; + input_buffer_0_4 <= input_buffer_1_4; + input_buffer_0_5 <= input_buffer_1_5; + input_buffer_1_0 <= input_buffer_2_0; + input_buffer_1_1 <= input_buffer_2_1; + input_buffer_1_2 <= input_buffer_2_2; + input_buffer_1_3 <= input_buffer_2_3; + input_buffer_1_4 <= input_buffer_2_4; + input_buffer_1_5 <= input_buffer_2_5; + input_buffer_2_0 <= input_buffer_3_0; + input_buffer_2_1 <= input_buffer_3_1; + input_buffer_2_2 <= input_buffer_3_2; + input_buffer_2_3 <= input_buffer_3_3; + input_buffer_2_4 <= input_buffer_3_4; + input_buffer_2_5 <= input_buffer_3_5; + input_buffer_3_0 <= input_buffer_4_0; + input_buffer_3_1 <= input_buffer_4_1; + input_buffer_3_2 <= input_buffer_4_2; + input_buffer_3_3 <= input_buffer_4_3; + input_buffer_3_4 <= input_buffer_4_4; + input_buffer_3_5 <= input_buffer_4_5; + input_buffer_4_0 <= input_buffer_5_0; + input_buffer_4_1 <= input_buffer_5_1; + input_buffer_4_2 <= input_buffer_5_2; + input_buffer_4_3 <= input_buffer_5_3; + input_buffer_4_4 <= input_buffer_5_4; + input_buffer_4_5 <= input_buffer_5_5; + //Pipelining to synchronize DSPs and non-DSPs + feature_reg_0_0_0 <= input_buffer_0_0; + feature_reg_0_1_0 <= input_buffer_0_1; + feature_reg_0_2_0 <= input_buffer_0_2; + feature_reg_0_3_0 <= input_buffer_0_3; + feature_reg_0_4_0 <= input_buffer_0_4; + feature_reg_0_5_0 <= input_buffer_0_5; + feature_reg_1_0_0 <= input_buffer_1_0; + feature_reg_1_1_0 <= input_buffer_1_1; + feature_reg_1_2_0 <= input_buffer_1_2; + feature_reg_1_3_0 <= input_buffer_1_3; + feature_reg_1_4_0 <= input_buffer_1_4; + feature_reg_1_5_0 <= input_buffer_1_5; + feature_reg_2_0_0 <= input_buffer_2_0; + feature_reg_2_1_0 <= input_buffer_2_1; + feature_reg_2_2_0 <= input_buffer_2_2; + feature_reg_2_3_0 <= input_buffer_2_3; + feature_reg_2_4_0 <= input_buffer_2_4; + feature_reg_2_5_0 <= input_buffer_2_5; + feature_reg_3_0_0 <= input_buffer_3_0; + feature_reg_3_1_0 <= input_buffer_3_1; + feature_reg_3_2_0 <= input_buffer_3_2; + feature_reg_3_3_0 <= input_buffer_3_3; + feature_reg_3_4_0 <= input_buffer_3_4; + feature_reg_3_5_0 <= input_buffer_3_5; + feature_reg_4_0_0 <= input_buffer_4_0; + feature_reg_4_1_0 <= input_buffer_4_1; + feature_reg_4_2_0 <= input_buffer_4_2; + feature_reg_4_3_0 <= input_buffer_4_3; + feature_reg_4_4_0 <= input_buffer_4_4; + feature_reg_4_5_0 <= input_buffer_4_5; + feature_reg_5_0_0 <= input_buffer_5_0; + feature_reg_5_1_0 <= input_buffer_5_1; + feature_reg_5_2_0 <= input_buffer_5_2; + feature_reg_5_3_0 <= input_buffer_5_3; + feature_reg_5_4_0 <= input_buffer_5_4; + feature_reg_5_5_0 <= input_buffer_5_5; + feature_reg_0_0_1 <= feature_reg_0_0_0; + feature_reg_0_1_1 <= feature_reg_0_1_0; + feature_reg_0_2_1 <= feature_reg_0_2_0; + feature_reg_0_3_1 <= feature_reg_0_3_0; + feature_reg_0_4_1 <= feature_reg_0_4_0; + feature_reg_0_5_1 <= feature_reg_0_5_0; + feature_reg_1_0_1 <= feature_reg_1_0_0; + feature_reg_1_1_1 <= feature_reg_1_1_0; + feature_reg_1_2_1 <= feature_reg_1_2_0; + feature_reg_1_3_1 <= feature_reg_1_3_0; + feature_reg_1_4_1 <= feature_reg_1_4_0; + feature_reg_1_5_1 <= feature_reg_1_5_0; + feature_reg_2_0_1 <= feature_reg_2_0_0; + feature_reg_2_1_1 <= feature_reg_2_1_0; + feature_reg_2_2_1 <= feature_reg_2_2_0; + feature_reg_2_3_1 <= feature_reg_2_3_0; + feature_reg_2_4_1 <= feature_reg_2_4_0; + feature_reg_2_5_1 <= feature_reg_2_5_0; + feature_reg_3_0_1 <= feature_reg_3_0_0; + feature_reg_3_1_1 <= feature_reg_3_1_0; + feature_reg_3_2_1 <= feature_reg_3_2_0; + feature_reg_3_3_1 <= feature_reg_3_3_0; + feature_reg_3_4_1 <= feature_reg_3_4_0; + feature_reg_3_5_1 <= feature_reg_3_5_0; + feature_reg_4_0_1 <= feature_reg_4_0_0; + feature_reg_4_1_1 <= feature_reg_4_1_0; + feature_reg_4_2_1 <= feature_reg_4_2_0; + feature_reg_4_3_1 <= feature_reg_4_3_0; + feature_reg_4_4_1 <= feature_reg_4_4_0; + feature_reg_4_5_1 <= feature_reg_4_5_0; + feature_reg_5_0_1 <= feature_reg_5_0_0; + feature_reg_5_1_1 <= feature_reg_5_1_0; + feature_reg_5_2_1 <= feature_reg_5_2_0; + feature_reg_5_3_1 <= feature_reg_5_3_0; + feature_reg_5_4_1 <= feature_reg_5_4_0; + feature_reg_5_5_1 <= feature_reg_5_5_0; + //Output Serializing logic + if (calculate_3) begin + output_buffer_0_0 <= rslt_buffer_0_0; + output_buffer_1_0 <= rslt_buffer_0_1; + output_buffer_2_0 <= rslt_buffer_0_2; + output_buffer_3_0 <= rslt_buffer_0_3; + output_buffer_4_0 <= rslt_buffer_0_4; + output_buffer_5_0 <= rslt_buffer_0_5; + output_buffer_0_1 <= rslt_buffer_1_0; + output_buffer_1_1 <= rslt_buffer_1_1; + output_buffer_2_1 <= rslt_buffer_1_2; + output_buffer_3_1 <= rslt_buffer_1_3; + output_buffer_4_1 <= rslt_buffer_1_4; + output_buffer_5_1 <= rslt_buffer_1_5; + output_buffer_0_2 <= rslt_buffer_2_0; + output_buffer_1_2 <= rslt_buffer_2_1; + output_buffer_2_2 <= rslt_buffer_2_2; + output_buffer_3_2 <= rslt_buffer_2_3; + output_buffer_4_2 <= rslt_buffer_2_4; + output_buffer_5_2 <= rslt_buffer_2_5; + output_buffer_0_3 <= rslt_buffer_3_0; + output_buffer_1_3 <= rslt_buffer_3_1; + output_buffer_2_3 <= rslt_buffer_3_2; + output_buffer_3_3 <= rslt_buffer_3_3; + output_buffer_4_3 <= rslt_buffer_3_4; + output_buffer_5_3 <= rslt_buffer_3_5; + output_buffer_0_4 <= rslt_buffer_4_0; + output_buffer_1_4 <= rslt_buffer_4_1; + output_buffer_2_4 <= rslt_buffer_4_2; + output_buffer_3_4 <= rslt_buffer_4_3; + output_buffer_4_4 <= rslt_buffer_4_4; + output_buffer_5_4 <= rslt_buffer_4_5; + output_buffer_0_5 <= rslt_buffer_5_0; + output_buffer_1_5 <= rslt_buffer_5_1; + output_buffer_2_5 <= rslt_buffer_5_2; + output_buffer_3_5 <= rslt_buffer_5_3; + output_buffer_4_5 <= rslt_buffer_5_4; + output_buffer_5_5 <= rslt_buffer_5_5; + end else begin + output_buffer_0_0 <= output_buffer_0_1; + output_buffer_0_1 <= output_buffer_0_2; + output_buffer_0_2 <= output_buffer_0_3; + output_buffer_0_3 <= output_buffer_0_4; + output_buffer_0_4 <= output_buffer_0_5; + output_buffer_1_0 <= output_buffer_1_1; + output_buffer_1_1 <= output_buffer_1_2; + output_buffer_1_2 <= output_buffer_1_3; + output_buffer_1_3 <= output_buffer_1_4; + output_buffer_1_4 <= output_buffer_1_5; + output_buffer_2_0 <= output_buffer_2_1; + output_buffer_2_1 <= output_buffer_2_2; + output_buffer_2_2 <= output_buffer_2_3; + output_buffer_2_3 <= output_buffer_2_4; + output_buffer_2_4 <= output_buffer_2_5; + output_buffer_3_0 <= output_buffer_3_1; + output_buffer_3_1 <= output_buffer_3_2; + output_buffer_3_2 <= output_buffer_3_3; + output_buffer_3_3 <= output_buffer_3_4; + output_buffer_3_4 <= output_buffer_3_5; + output_buffer_4_0 <= output_buffer_4_1; + output_buffer_4_1 <= output_buffer_4_2; + output_buffer_4_2 <= output_buffer_4_3; + output_buffer_4_3 <= output_buffer_4_4; + output_buffer_4_4 <= output_buffer_4_5; + output_buffer_5_0 <= output_buffer_5_1; + output_buffer_5_1 <= output_buffer_5_2; + output_buffer_5_2 <= output_buffer_5_3; + output_buffer_5_3 <= output_buffer_5_4; + output_buffer_5_4 <= output_buffer_5_5; + end +end + +////// FIRST COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD00 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_2), + .by(input_buffer_2_0), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_1_0), + .resultb(dsp_out_1_1) +); + +winograd_dsp_16 winograd_dsp_16_WD10 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_2_4), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_1_2), + .resultb(dsp_out_1_3) +); + +winograd_dsp_16 winograd_dsp_16_WD20 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_2), + .by(input_buffer_1_0), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_1_4), + .resultb(dsp_out_1_5) +); + +winograd_dsp_16 winograd_dsp_16_WD30 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_1_6), + .resultb(dsp_out_1_7) +); + +winograd_dsp_16 winograd_dsp_16_WD40 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_0), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_1_8), + .resultb(dsp_out_1_9) +); + +winograd_dsp_16 winograd_dsp_16_WD50 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_4), + .by(input_buffer_5_2), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_1_10), + .resultb(dsp_out_1_11) +); + +////// SECOND COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD01 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_0), + .resultb(dsp_out_2_1) +); + +winograd_dsp_16 winograd_dsp_16_WD11 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_2), + .resultb(dsp_out_2_3) +); + +winograd_dsp_16 winograd_dsp_16_WD21 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_4), + .resultb(dsp_out_2_5) +); + +winograd_dsp_16 winograd_dsp_16_WD31 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_6), + .resultb(dsp_out_2_7) +); + +////// THIRD COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD02 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_0), + .resultb(dsp_out_3_1) +); + +winograd_dsp_16 winograd_dsp_16_WD12 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_2), + .resultb(dsp_out_3_3) +); + +winograd_dsp_16 winograd_dsp_16_WD22 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_4), + .resultb(dsp_out_3_5) +); + +winograd_dsp_16 winograd_dsp_16_WD32 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_6), + .resultb(dsp_out_3_7) +); + +////// FOURTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD03 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_0), + .resultb(dsp_out_4_1) +); + +winograd_dsp_16 winograd_dsp_16_WD13 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_2), + .resultb(dsp_out_4_3) +); + +winograd_dsp_16 winograd_dsp_16_WD23 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_4), + .resultb(dsp_out_4_5) +); + +winograd_dsp_16 winograd_dsp_16_WD33 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_6), + .resultb(dsp_out_4_7) +); + +////// FIFTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD04 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_0), + .resultb(dsp_out_5_1) +); + +winograd_dsp_16 winograd_dsp_16_WD14 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_2), + .resultb(dsp_out_5_3) +); + +winograd_dsp_16 winograd_dsp_16_WD24 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_4), + .resultb(dsp_out_5_5) +); + +winograd_dsp_16 winograd_dsp_16_WD34 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_6), + .resultb(dsp_out_5_7) +); + +////// SIXTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD05 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_3), + .by(input_buffer_2_1), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_6_0), + .resultb(dsp_out_6_1) +); + +winograd_dsp_16 winograd_dsp_16_WD15 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_5), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_6_2), + .resultb(dsp_out_6_3) +); + +winograd_dsp_16 winograd_dsp_16_WD25 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_3), + .by(input_buffer_1_3), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_6_4), + .resultb(dsp_out_6_5) +); + +winograd_dsp_16 winograd_dsp_16_WD35 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_3_3), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_6_6), + .resultb(dsp_out_6_7) +); + +winograd_dsp_16 winograd_dsp_16_WD45 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_3), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_6_8), + .resultb(dsp_out_6_9) +); + +winograd_dsp_16 winograd_dsp_16_WD55 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_5), + .by(input_buffer_5_3), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_6_10), + .resultb(dsp_out_6_11) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA00 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_0_1[11:0], 4'b0000}), + .data1x(dsp_out_1_0), + .data2x({feature_reg_0_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_1), + .data4x(dsp_out_1_2), + .data5x(dsp_out_1_3), + .data6x({feature_reg_4_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_4), + .data8x(feature_reg_4_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_0) +); + +wire [15:0] f1, f2, f3, f4; +assign f1 = -{feature_reg_1_0_1[11:0], 4'b0000}; +assign f2 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f3 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f4 = -{feature_reg_2_4_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA10 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_1_5), + .data1x(f1), + .data2x(f2), + .data3x(f3), + .data4x(dsp_out_1_6), + .data5x(f4), + .data6x({feature_reg_3_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_7), + .data8x(feature_reg_3_4_1), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_0) +); + +wire [15:0] f5, f6, f7, f8, f9, f10; +assign f5 = -dsp_out_1_5; +assign f6 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f7 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f8 = -{feature_reg_3_0_1[13:0], 2'b00}; +assign f9 = -dsp_out_1_7; +assign f10 = -feature_reg_3_4_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA20 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f5), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(f6), + .data4x(dsp_out_1_6), + .data5x(f7), + .data6x(f8), + .data7x(f9), + .data8x(f10), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_0) +); + +wire [15:0] f11, f12, f13, f14, f15, f16, f17; +assign f11 = -{feature_reg_1_0_1[12:0], 3'b000}; +assign f12 = -{feature_reg_1_4_1[14:0], 1'b0}; +assign f13 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f14 = -feature_reg_2_4_1; +assign f15 = dsp_out_1_5 >>> 1; +assign f16 = dsp_out_1_6 >>> 2; +assign f17 = dsp_out_1_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA30 ( + .clock(clk), + .clken(calculate_2), + .data0x(f15), + .data1x(f11), + .data2x(f12), + .data3x(f13), + .data4x(f16), + .data5x(f14), + .data6x({feature_reg_3_0_1[12:0], 3'b000}), + .data7x(f17), + .data8x({feature_reg_3_4_1[14:0], 1'b0}), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_0) +); + +wire [15:0] f18, f19, f20, f21, f22, f23, f23b; +assign f18 = -(dsp_out_1_5 >>> 1); +assign f19 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f20 = -feature_reg_2_4_1; +assign f21 = -{feature_reg_3_0_1[12:0], 3'b000}; +assign f22 = -(dsp_out_1_7 <<< 1); +assign f23 = -{feature_reg_3_4_1[14:0], 1'b0}; +assign f23b = dsp_out_1_6 >>> 2; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA40 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[12:0], 3'b000}), + .data1x(f18), + .data2x({feature_reg_1_4_1[14:0], 1'b0}), + .data3x(f19), + .data4x(f23b), + .data5x(f20), + .data6x(f21), + .data7x(f22), + .data8x(f23), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_0) +); + +wire [15:0] f24; +assign f24 = -dsp_out_1_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA50 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f24), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_8), + .data4x(dsp_out_1_9), + .data5x(dsp_out_1_10), + .data6x({feature_reg_5_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_11), + .data8x(feature_reg_5_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_0) +); + +wire [15:0] f25, f26, f27, f28; +assign f25 = -{feature_reg_0_2_1[11:0], 4'b0000}; +assign f26 = -{feature_reg_0_1_1[11:0], 4'b0000}; +assign f27 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f28 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA01 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[13:0], 2'b00}), + .data1x(f25), + .data2x(f26), + .data3x({feature_reg_0_4_1[13:0], 2'b00}), + .data4x(dsp_out_2_0), + .data5x(dsp_out_2_1), + .data6x(dsp_out_2_2), + .data7x(dsp_out_2_3), + .data8x(f27), + .data9x(f28), + .data10x(feature_reg_4_3_1), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_1) +); + +wire [15:0] f29, f30, f31, f32, f33, f34, f35, f36; +assign f29 = -{feature_reg_1_3_1[13:0], 2'b00}; +assign f30 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f31 = -{feature_reg_2_3_1[13:0], 2'b00}; +assign f32 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f33 = -{feature_reg_3_1_1[13:0], 2'b00}; +assign f34 = -{feature_reg_3_2_1[13:0], 2'b00}; +assign f35 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f36 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA11 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0], 4'b0000}), + .data1x({feature_reg_1_2_1[11:0], 4'b0000}), + .data2x(f29), + .data3x(f30), + .data4x({feature_reg_2_1_1[11:0], 4'b0000}), + .data5x({feature_reg_2_2_1[11:0], 4'b0000}), + .data6x(f31), + .data7x(f32), + .data8x(f33), + .data9x(f34), + .data10x(feature_reg_3_3_1), + .data11x(feature_reg_3_4_1), + .data12x(f35), + .data13x(f36), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_1) +); + +wire [15:0] f37, f38, f39, f40, f41, f42, f43, f44; +assign f37 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f38 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f39 = -{feature_reg_2_3_1[13:0],2'b00}; +assign f40 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f41 = -feature_reg_3_3_1; +assign f42 = -feature_reg_3_4_1; +assign f43 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f44 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA21 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f37), + .data2x(f38), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[11:0],4'b0000}), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x(f39), + .data7x(f40), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(f41), + .data11x(f42), + .data12x(f43), + .data13x(f44), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_1) +); + +wire [15:0] f45, f46, f47, f48, f49, f50, f51, f52; +assign f45 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f46 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f47 = -feature_reg_2_3_1; +assign f48 = -feature_reg_2_4_1; +assign f49 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f50 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f51 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f52 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA31 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[12:0],3'b000}), + .data2x(f45), + .data3x(f46), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f47), + .data7x(f48), + .data8x(f49), + .data9x(f50), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f51), + .data13x(f52), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_1) +); + +wire [15:0] f53, f54, f55, f56, f57, f58, f59, f60; +assign f53 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f54 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f55 = -feature_reg_2_3_1; +assign f56 = -feature_reg_2_4_1; +assign f57 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f58 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f59 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f60 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA41 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[14:0],1'b0}), + .data1x(f53), + .data2x(f54), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f55), + .data7x(f56), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x(f57), + .data11x(f58), + .data12x(f59), + .data13x(f60), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_1) +); + +wire [15:0] f61, f62, f63, f64; +assign f61 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f62 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f63 = -{feature_reg_5_1_1[13:0],2'b00}; +assign f64 = -{feature_reg_5_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA51 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f61), + .data2x(f62), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_2_4), + .data5x(dsp_out_2_5), + .data6x(dsp_out_2_6), + .data7x(dsp_out_2_7), + .data8x(f63), + .data9x(f64), + .data10x(feature_reg_5_3_1), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_1) +); + +wire [15:0] f65, f66, f67, f68; +assign f65 = -{feature_reg_0_2_1[11:0],4'b0000}; +assign f66 = -{feature_reg_0_3_1[13:0],2'b00}; +assign f67 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f68 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA02 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(f65), + .data2x(f66), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_3_0), + .data5x(dsp_out_3_1), + .data6x(dsp_out_3_2), + .data7x(dsp_out_3_3), + .data8x({feature_reg_4_1_1[13:0],2'b00}), + .data9x(f67), + .data10x(f68), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_2) +); + +wire [15:0] f69, f70, f71, f72, f73, f74, f75, f76; +assign f69 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f70 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f71 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f72 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f73 = -{feature_reg_3_2_1[13:0],2'b00}; +assign f74 = -feature_reg_3_3_1; +assign f75 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f76 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA12 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[11:0],4'b0000}), + .data1x(f69), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f70), + .data4x(f71), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f72), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f73), + .data10x(f74), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f75), + .data14x(f76), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_2) +); + +wire [15:0] f77, f78, f79, f80, f81, f82, f83, f84; +assign f77 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f78 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f79 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f80 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f81 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f82 = -feature_reg_3_4_1; +assign f83 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f84 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA22 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f77), + .data2x(f78), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f79), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f80), + .data8x(f81), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(feature_reg_3_3_1), + .data11x(f82), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f83), + .data14x(f84), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_2) +); + +wire [15:0] f85, f86, f87, f88, f89, f90, f91, f92; +assign f85 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f86 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f87 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f88 = -feature_reg_2_4_1; +assign f89 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f90 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f91 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f92 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA32 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[12:0],3'b000}), + .data1x(f85), + .data2x({feature_reg_1_3_1[14:0],1'b0}), + .data3x(f86), + .data4x(f87), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f88), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x(f89), + .data10x(f90), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f91), + .data14x(f92), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_2) +); + +wire [15:0] f93, f94, f95, f96, f97, f98, f99, f100; +assign f93 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f94 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f95 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f96 = -feature_reg_2_4_1; +assign f97 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f98 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f99 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f100 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA42 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f93), + .data2x(f94), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f95), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f96), + .data8x(f97), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f98), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f99), + .data14x(f100), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_2) +); + +wire [15:0] f101, f102, f103, f104; +assign f101 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f102 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f103 = -{feature_reg_5_2_1[13:0],2'b00}; +assign f104 = -feature_reg_5_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA52 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f101), + .data2x(f102), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_3_4), + .data5x(dsp_out_3_5), + .data6x(dsp_out_3_6), + .data7x(dsp_out_3_7), + .data8x({feature_reg_5_1_1[13:0],2'b00}), + .data9x(f103), + .data10x(f104), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_2) +); + +wire [15:0] f105, f106, f107, f108; +assign f105 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f106 = -{feature_reg_0_1_1[12:0],3'b000}; +assign f107 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f108 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA03 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[12:0],3'b000}), + .data1x(f105), + .data2x(f106), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_4_0), + .data5x(dsp_out_4_1), + .data6x(dsp_out_4_2), + .data7x(dsp_out_4_3), + .data8x(f107), + .data9x(f108), + .data10x({feature_reg_4_3_1[14:0],1'b0}), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_3) +); + +wire [15:0] f109, f110, f111, f112, f113, f114, f115, f116; +assign f109 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f110 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f111 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f112 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f113 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f114 = -feature_reg_3_2_1; +assign f115 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f116 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA13 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[13:0],2'b00}), + .data2x(f109), + .data3x(f110), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f111), + .data7x(f112), + .data8x(f113), + .data9x(f114), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(feature_reg_3_4_1), + .data12x(f115), + .data13x(f116), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_3) +); + +wire [15:0] f117, f118, f119, f120, f121, f122, f123, f124; +assign f117 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f118 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f119 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f120 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f121 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f122 = -feature_reg_3_4_1; +assign f123 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f124 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA23 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f117), + .data2x(f118), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f119), + .data7x(f120), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(feature_reg_3_2_1), + .data10x(f121), + .data11x(f122), + .data12x(f123), + .data13x(f124), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_3) +); + +wire [15:0] f125, f126, f127, f128, f129, f130, f131, f132; +assign f125 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f126 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f127 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f128 = -feature_reg_2_4_1; +assign f129 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f130 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f131 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f132 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA33 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x({feature_reg_1_2_1[14:0],1'b0}), + .data2x(f125), + .data3x(f126), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f127), + .data7x(f128), + .data8x(f129), + .data9x(f130), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f131), + .data13x(f132), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_3) +); + +wire [15:0] f133, f134, f135, f136, f137, f138, f139, f140; +assign f133 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f134 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f135 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f136 = -feature_reg_2_4_1; +assign f137 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f138 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f139 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f140 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA43 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f133), + .data2x(f134), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f135), + .data7x(f136), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x(f137), + .data11x(f138), + .data12x(f139), + .data13x(f140), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_3) +); + +wire [15:0] f141, f142, f143, f144; +assign f141 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f142 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f143 = -{feature_reg_5_1_1[14:0],1'b0}; +assign f144 = -feature_reg_5_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA53 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f141), + .data2x(f142), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_4_4), + .data5x(dsp_out_4_5), + .data6x(dsp_out_4_6), + .data7x(dsp_out_4_7), + .data8x(f143), + .data9x(f144), + .data10x({feature_reg_5_3_1[14:0],1'b0}), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_3) +); + +wire [15:0] f145, f146, f147, f148; +assign f145 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f146 = -{feature_reg_0_3_1[12:0],3'b000}; +assign f147 = -feature_reg_4_2_1; +assign f148 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA04 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[12:0],3'b000}), + .data1x(f145), + .data2x(f146), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_5_0), + .data5x(dsp_out_5_1), + .data6x(dsp_out_5_2), + .data7x(dsp_out_5_3), + .data8x({feature_reg_4_1_1[14:0],1'b0}), + .data9x(f147), + .data10x(f148), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_4) +); + +wire [15:0] f149, f150, f151, f152, f153, f154, f155, f156; +assign f149 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f150 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f151 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f152 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f153 = -feature_reg_3_2_1; +assign f154 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f155 = -feature_reg_4_2_1; +assign f156 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA14 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[13:0],2'b00}), + .data1x(f149), + .data2x({feature_reg_1_3_1[12:0],3'b000}), + .data3x(f150), + .data4x(f151), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f152), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(f153), + .data10x(f154), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f155), + .data14x(f156), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_4) +); + +wire [15:0] f157, f158, f159, f160, f161, f162, f163, f164; +assign f157 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f158 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f159 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f160 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f161 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f162 = -feature_reg_3_4_1; +assign f163 = -feature_reg_4_2_1; +assign f164 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA24 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f157), + .data2x(f158), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f159), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f160), + .data8x(f161), + .data9x(feature_reg_3_2_1), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f162), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f163), + .data14x(f164), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_4) +); + +wire [15:0] f165, f166, f167, f168, f169, f170, f171, f172; +assign f165 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f166 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f167 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f168 = -feature_reg_2_4_1; +assign f169 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f170 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f171 = -feature_reg_4_2_1; +assign f172 = -{feature_reg_4_1_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA34 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[14:0],1'b0}), + .data1x(f165), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f166), + .data4x(f167), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f168), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f169), + .data10x(f170), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f171), + .data14x(f172), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_4) +); + +wire [15:0] f173, f174, f175, f176, f177, f178, f179, f180; +assign f173 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f174 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f175 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f176 = -feature_reg_2_4_1; +assign f177 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f178 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f179 = -feature_reg_4_2_1; +assign f180 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA44 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x(f173), + .data2x(f174), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f175), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f176), + .data8x(f177), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x(f178), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f179), + .data14x(f180), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_4) +); + +wire [15:0] f181, f182, f183, f184; +assign f181 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f182 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f183 = -feature_reg_5_2_1; +assign f184 = -{feature_reg_5_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA54 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f181), + .data2x(f182), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_5_4), + .data5x(dsp_out_5_5), + .data6x(dsp_out_5_6), + .data7x(dsp_out_5_7), + .data8x({feature_reg_5_1_1[14:0],1'b0}), + .data9x(f183), + .data10x(f184), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_4) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA05 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(dsp_out_6_0), + .data2x({feature_reg_0_5_1[13:0],2'b00}), + .data3x(dsp_out_6_1), + .data4x(dsp_out_6_2), + .data5x(dsp_out_6_3), + .data6x({feature_reg_4_1_1[13:0],2'b00}), + .data7x(dsp_out_6_4), + .data8x(feature_reg_4_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_5) +); + +wire [15:0] f185, f186, f187, f188; +assign f185 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f186 = -{feature_reg_1_5_1[13:0],2'b00}; +assign f187 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f188 = -{feature_reg_2_5_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA15 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_6_5), + .data1x(f185), + .data2x(f186), + .data3x(f187), + .data4x(dsp_out_6_6), + .data5x(f188), + .data6x({feature_reg_3_1_1[13:0],2'b00}), + .data7x(dsp_out_6_7), + .data8x(feature_reg_3_5_1), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_5) +); + +wire [15:0] f189, f190, f191, f192, f193, f194; +assign f189 = -dsp_out_6_5; +assign f190 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f191 = -{feature_reg_2_5_1[13:0],2'b00}; +assign f192 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f193 = -dsp_out_6_7; +assign f194 = -feature_reg_3_5_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA25 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f189), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(f190), + .data4x(dsp_out_6_6), + .data5x(f191), + .data6x(f192), + .data7x(f193), + .data8x(f194), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_5) +); + +wire [15:0] f195, f196, f197, f198, f199, f200, f201; +assign f195 = dsp_out_6_5 >>> 1; +assign f196 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f197 = -{feature_reg_1_5_1[14:0],1'b0}; +assign f198 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f199 = dsp_out_6_6 >>> 2; +assign f200 = -feature_reg_2_5_1; +assign f201 = dsp_out_6_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA35 ( + .clock(clk), + .clken(calculate_2), + .data0x(f195), + .data1x(f196), + .data2x(f197), + .data3x(f198), + .data4x(f199), + .data5x(f200), + .data6x({feature_reg_3_1_1[12:0],3'b000}), + .data7x(f201), + .data8x({feature_reg_3_5_1[14:0],1'b0}), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_5) +); + +wire [15:0] f202, f203, f204, f205, f206, f207, f208; +assign f202 = -(dsp_out_6_5 >>> 1); +assign f203 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f204 = dsp_out_6_6 >>> 2; +assign f205 = -feature_reg_2_5_1; +assign f206 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f207 = -(dsp_out_6_7 <<< 1); +assign f208 = -{feature_reg_3_5_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA45 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f202), + .data2x({feature_reg_1_5_1[14:0],1'b0}), + .data3x(f203), + .data4x(f204), + .data5x(f205), + .data6x(f206), + .data7x(f207), + .data8x(f208), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_5) +); + +wire [15:0] f209; +assign f209 = -dsp_out_6_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA55 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f209), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(dsp_out_6_8), + .data4x(dsp_out_6_9), + .data5x(dsp_out_6_10), + .data6x({feature_reg_5_1_1[13:0],2'b00}), + .data7x(dsp_out_6_11), + .data8x(feature_reg_5_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_5) +); + +assign o_feature_0 = output_buffer_0_0[15:0]; +assign o_feature_1 = output_buffer_1_0[15:0]; +assign o_feature_2 = output_buffer_2_0[15:0]; +assign o_feature_3 = output_buffer_3_0[15:0]; +assign o_feature_4 = output_buffer_4_0[15:0]; +assign o_feature_5 = output_buffer_5_0[15:0]; +assign o_valid = valid_9; + +endmodule + +module stream_buffer_5_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_15 buffer_16_12100_buffer_init_15_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_15 buffer_16_12100_buffer_init_15_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_15 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_5_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_05 buffer_16_12100_buffer_init_05_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_05 buffer_16_12100_buffer_init_05_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_05 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_5_3 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_35 buffer_16_12100_buffer_init_35_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_35 buffer_16_12100_buffer_init_35_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_35 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_5_2 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_25 buffer_16_12100_buffer_init_25_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_25 buffer_16_12100_buffer_init_25_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_25 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_4_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_04 buffer_16_12100_buffer_init_04_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_04 buffer_16_12100_buffer_init_04_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_04 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_4_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_14 buffer_16_12100_buffer_init_14_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_14 buffer_16_12100_buffer_init_14_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_14 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_4_2 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_24 buffer_16_12100_buffer_init_24_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_24 buffer_16_12100_buffer_init_24_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_24 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_4_3 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_34 buffer_16_12100_buffer_init_34_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_34 buffer_16_12100_buffer_init_34_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_34 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_2_2 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_22 buffer_16_12100_buffer_init_22_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_22 buffer_16_12100_buffer_init_22_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_22 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_2_3 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_32 buffer_16_12100_buffer_init_32_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_32 buffer_16_12100_buffer_init_32_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_32 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_2_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_02 buffer_16_12100_buffer_init_02_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_02 buffer_16_12100_buffer_init_02_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_02 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_2_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_12 buffer_16_12100_buffer_init_12_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_12 buffer_16_12100_buffer_init_12_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_12 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module processing_element ( + input clk, + input i_reset, + input i_valid, + input [15:0] i_features_0_0, + output [15:0] o_features_0_0, + input [15:0] i_features_0_1, + output [15:0] o_features_0_1, + input [15:0] i_features_0_2, + output [15:0] o_features_0_2, + input [15:0] i_features_0_3, + output [15:0] o_features_0_3, + input [15:0] i_features_0_4, + output [15:0] o_features_0_4, + input [15:0] i_features_0_5, + output [15:0] o_features_0_5, + input [15:0] i_features_1_0, + output [15:0] o_features_1_0, + input [15:0] i_features_1_1, + output [15:0] o_features_1_1, + input [15:0] i_features_1_2, + output [15:0] o_features_1_2, + input [15:0] i_features_1_3, + output [15:0] o_features_1_3, + input [15:0] i_features_1_4, + output [15:0] o_features_1_4, + input [15:0] i_features_1_5, + output [15:0] o_features_1_5, + input [15:0] i_features_2_0, + output [15:0] o_features_2_0, + input [15:0] i_features_2_1, + output [15:0] o_features_2_1, + input [15:0] i_features_2_2, + output [15:0] o_features_2_2, + input [15:0] i_features_2_3, + output [15:0] o_features_2_3, + input [15:0] i_features_2_4, + output [15:0] o_features_2_4, + input [15:0] i_features_2_5, + output [15:0] o_features_2_5, + input [15:0] i_features_3_0, + output [15:0] o_features_3_0, + input [15:0] i_features_3_1, + output [15:0] o_features_3_1, + input [15:0] i_features_3_2, + output [15:0] o_features_3_2, + input [15:0] i_features_3_3, + output [15:0] o_features_3_3, + input [15:0] i_features_3_4, + output [15:0] o_features_3_4, + input [15:0] i_features_3_5, + output [15:0] o_features_3_5, + output [29:0] o_result_0, + output [29:0] o_result_1, + output [29:0] o_result_2, + output [29:0] o_result_3, + output [29:0] o_result_4, + output [29:0] o_result_5, + output o_valid, + output o_next_reset, + output o_next_valid +); + +wire [23:0] DP_res_0; +reg [15:0] if_reg_0_0; +wire [7:0] weights_0_0; +reg [15:0] if_reg_0_1; +wire [7:0] weights_0_1; +reg [15:0] if_reg_0_2; +wire [7:0] weights_0_2; +reg [15:0] if_reg_0_3; +wire [7:0] weights_0_3; +wire [23:0] DP_res_1; +reg [15:0] if_reg_1_0; +wire [7:0] weights_1_0; +reg [15:0] if_reg_1_1; +wire [7:0] weights_1_1; +reg [15:0] if_reg_1_2; +wire [7:0] weights_1_2; +reg [15:0] if_reg_1_3; +wire [7:0] weights_1_3; +wire [23:0] DP_res_2; +reg [15:0] if_reg_2_0; +wire [7:0] weights_2_0; +reg [15:0] if_reg_2_1; +wire [7:0] weights_2_1; +reg [15:0] if_reg_2_2; +wire [7:0] weights_2_2; +reg [15:0] if_reg_2_3; +wire [7:0] weights_2_3; +wire [23:0] DP_res_3; +reg [15:0] if_reg_3_0; +wire [7:0] weights_3_0; +reg [15:0] if_reg_3_1; +wire [7:0] weights_3_1; +reg [15:0] if_reg_3_2; +wire [7:0] weights_3_2; +reg [15:0] if_reg_3_3; +wire [7:0] weights_3_3; +wire [23:0] DP_res_4; +reg [15:0] if_reg_4_0; +wire [7:0] weights_4_0; +reg [15:0] if_reg_4_1; +wire [7:0] weights_4_1; +reg [15:0] if_reg_4_2; +wire [7:0] weights_4_2; +reg [15:0] if_reg_4_3; +wire [7:0] weights_4_3; +wire [23:0] DP_res_5; +reg [15:0] if_reg_5_0; +wire [7:0] weights_5_0; +reg [15:0] if_reg_5_1; +wire [7:0] weights_5_1; +reg [15:0] if_reg_5_2; +wire [7:0] weights_5_2; +reg [15:0] if_reg_5_3; +wire [7:0] weights_5_3; + +reg [10:0] base_addr; +reg [10:0] offset; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [15:0] T_counter; + +reg reset_1, reset_2, reset_3, next_reset, next_reset_2; +reg done, done_1, done_2, done_3, done_4, done_5, done_6; + +wire [15:0] features_0_0; +wire [15:0] features_0_1; +wire [15:0] features_0_2; +wire [15:0] features_0_3; +wire [15:0] features_1_0; +wire [15:0] features_1_1; +wire [15:0] features_1_2; +wire [15:0] features_1_3; +wire [15:0] features_2_0; +wire [15:0] features_2_1; +wire [15:0] features_2_2; +wire [15:0] features_2_3; +wire [15:0] features_3_0; +wire [15:0] features_3_1; +wire [15:0] features_3_2; +wire [15:0] features_3_3; +wire [15:0] features_4_0; +wire [15:0] features_4_1; +wire [15:0] features_4_2; +wire [15:0] features_4_3; +wire [15:0] features_5_0; +wire [15:0] features_5_1; +wire [15:0] features_5_2; +wire [15:0] features_5_3; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg next_valid; + +always @ (posedge clk) begin + reset_1 <= ~(i_valid || valid_11); + reset_2 <= reset_1; + reset_3 <= reset_2; + next_reset <= i_reset; + next_reset_2 <= next_reset; + if (i_reset == 1'b0) begin + if_reg_0_0 <= features_0_0; + if_reg_0_1 <= features_0_1; + if_reg_0_2 <= features_0_2; + if_reg_0_3 <= features_0_3; + if_reg_1_0 <= features_1_0; + if_reg_1_1 <= features_1_1; + if_reg_1_2 <= features_1_2; + if_reg_1_3 <= features_1_3; + if_reg_2_0 <= features_2_0; + if_reg_2_1 <= features_2_1; + if_reg_2_2 <= features_2_2; + if_reg_2_3 <= features_2_3; + if_reg_3_0 <= features_3_0; + if_reg_3_1 <= features_3_1; + if_reg_3_2 <= features_3_2; + if_reg_3_3 <= features_3_3; + if_reg_4_0 <= features_4_0; + if_reg_4_1 <= features_4_1; + if_reg_4_2 <= features_4_2; + if_reg_4_3 <= features_4_3; + if_reg_5_0 <= features_5_0; + if_reg_5_1 <= features_5_1; + if_reg_5_2 <= features_5_2; + if_reg_5_3 <= features_5_3; + end +end + +always @ (posedge clk) begin + next_valid <= i_valid; + if (i_reset) begin + valid_0 <= 0; + valid_1 <= 0; + valid_2 <= 0; + valid_3 <= 0; + valid_4 <= 0; + valid_5 <= 0; + valid_6 <= 0; + valid_7 <= 0; + valid_8 <= 0; + valid_9 <= 0; + valid_10 <= 0; + valid_11 <= 0; + end else if ((i_valid == 1'b0) && (valid_11 == 1'b0)) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + T_counter <= 0; + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + done_4 <= 0; + done_5 <= 0; + done_6 <= 0; + end else if (i_valid || valid_11) begin + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + if (T_counter <= 1809025) begin + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + done_4 <= done_3; + done_5 <= done_4; + done_6 <= done_5; + if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + done <= 1; + T_counter <= T_counter + 1'b1; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + done <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end + end +end + +dot_product_16_8_30_4 dot_product_16_8_30_4_inst_0 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_0_0), + .i_weights_0(weights_0_0), + .i_features_1(features_0_1), + .i_weights_1(weights_0_1), + .i_features_2(features_0_2), + .i_weights_2(weights_0_2), + .i_features_3(features_0_3), + .i_weights_3(weights_0_3), + .o_result(DP_res_0) +); + +dot_product_16_8_30_4 dot_product_16_8_30_4_inst_1 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_1_0), + .i_weights_0(weights_1_0), + .i_features_1(features_1_1), + .i_weights_1(weights_1_1), + .i_features_2(features_1_2), + .i_weights_2(weights_1_2), + .i_features_3(features_1_3), + .i_weights_3(weights_1_3), + .o_result(DP_res_1) +); + +dot_product_16_8_30_4 dot_product_16_8_30_4_inst_2 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_2_0), + .i_weights_0(weights_2_0), + .i_features_1(features_2_1), + .i_weights_1(weights_2_1), + .i_features_2(features_2_2), + .i_weights_2(weights_2_2), + .i_features_3(features_2_3), + .i_weights_3(weights_2_3), + .o_result(DP_res_2) +); + +dot_product_16_8_30_4 dot_product_16_8_30_4_inst_3 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_3_0), + .i_weights_0(weights_3_0), + .i_features_1(features_3_1), + .i_weights_1(weights_3_1), + .i_features_2(features_3_2), + .i_weights_2(weights_3_2), + .i_features_3(features_3_3), + .i_weights_3(weights_3_3), + .o_result(DP_res_3) +); + +dot_product_16_8_30_4 dot_product_16_8_30_4_inst_4 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_4_0), + .i_weights_0(weights_4_0), + .i_features_1(features_4_1), + .i_weights_1(weights_4_1), + .i_features_2(features_4_2), + .i_weights_2(weights_4_2), + .i_features_3(features_4_3), + .i_weights_3(weights_4_3), + .o_result(DP_res_4) +); + +dot_product_16_8_30_4 dot_product_16_8_30_4_inst_5 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_5_0), + .i_weights_0(weights_5_0), + .i_features_1(features_5_1), + .i_weights_1(weights_5_1), + .i_features_2(features_5_2), + .i_weights_2(weights_5_2), + .i_features_3(features_5_3), + .i_weights_3(weights_5_3), + .o_result(DP_res_5) +); + +accumulator_24_30_4 accumulator_24_30_4_inst_0 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_0), + .i_dp_done(done_5), + .o_accum(o_result_0) +); + +accumulator_24_30_4 accumulator_24_30_4_inst_1 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_1), + .i_dp_done(done_5), + .o_accum(o_result_1) +); + +accumulator_24_30_4 accumulator_24_30_4_inst_2 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_2), + .i_dp_done(done_5), + .o_accum(o_result_2) +); + +accumulator_24_30_4 accumulator_24_30_4_inst_3 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_3), + .i_dp_done(done_5), + .o_accum(o_result_3) +); + +accumulator_24_30_4 accumulator_24_30_4_inst_4 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_4), + .i_dp_done(done_5), + .o_accum(o_result_4) +); + +accumulator_24_30_4 accumulator_24_30_4_inst_5 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_5), + .i_dp_done(done_5), + .o_accum(o_result_5) +); + +reg [9:0] weight_cache_addr; +always @ (*) begin + weight_cache_addr <= base_addr+offset; +end +weight_cache_2048_8_0_weight_init_00 weight_cache_2048_8_0_weight_init_00_inst_0_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_0_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_0_1) +); + +weight_cache_2048_8_0_weight_init_20 weight_cache_2048_8_0_weight_init_20_inst_0_2 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_0_2), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_0_3) +); + +weight_cache_2048_8_0_weight_init_01 weight_cache_2048_8_0_weight_init_01_inst_1_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_1_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_1_1) +); + +weight_cache_2048_8_0_weight_init_21 weight_cache_2048_8_0_weight_init_21_inst_1_2 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_1_2), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_1_3) +); + +weight_cache_2048_8_0_weight_init_02 weight_cache_2048_8_0_weight_init_02_inst_2_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_2_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_2_1) +); + +weight_cache_2048_8_0_weight_init_22 weight_cache_2048_8_0_weight_init_22_inst_2_2 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_2_2), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_2_3) +); + +weight_cache_2048_8_0_weight_init_03 weight_cache_2048_8_0_weight_init_03_inst_3_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_3_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_3_1) +); + +weight_cache_2048_8_0_weight_init_23 weight_cache_2048_8_0_weight_init_23_inst_3_2 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_3_2), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_3_3) +); + +weight_cache_2048_8_0_weight_init_04 weight_cache_2048_8_0_weight_init_04_inst_4_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_4_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_4_1) +); + +weight_cache_2048_8_0_weight_init_24 weight_cache_2048_8_0_weight_init_24_inst_4_2 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_4_2), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_4_3) +); + +weight_cache_2048_8_0_weight_init_05 weight_cache_2048_8_0_weight_init_05_inst_5_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_5_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_5_1) +); + +weight_cache_2048_8_0_weight_init_25 weight_cache_2048_8_0_weight_init_25_inst_5_2 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_5_2), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_5_3) +); + +assign o_features_0_0 = if_reg_0_0; +assign features_0_0 = i_features_0_0; +assign o_features_1_0 = if_reg_0_1; +assign features_0_1 = i_features_1_0; +assign o_features_2_0 = if_reg_0_2; +assign features_0_2 = i_features_2_0; +assign o_features_3_0 = if_reg_0_3; +assign features_0_3 = i_features_3_0; +assign o_features_0_1 = if_reg_1_0; +assign features_1_0 = i_features_0_1; +assign o_features_1_1 = if_reg_1_1; +assign features_1_1 = i_features_1_1; +assign o_features_2_1 = if_reg_1_2; +assign features_1_2 = i_features_2_1; +assign o_features_3_1 = if_reg_1_3; +assign features_1_3 = i_features_3_1; +assign o_features_0_2 = if_reg_2_0; +assign features_2_0 = i_features_0_2; +assign o_features_1_2 = if_reg_2_1; +assign features_2_1 = i_features_1_2; +assign o_features_2_2 = if_reg_2_2; +assign features_2_2 = i_features_2_2; +assign o_features_3_2 = if_reg_2_3; +assign features_2_3 = i_features_3_2; +assign o_features_0_3 = if_reg_3_0; +assign features_3_0 = i_features_0_3; +assign o_features_1_3 = if_reg_3_1; +assign features_3_1 = i_features_1_3; +assign o_features_2_3 = if_reg_3_2; +assign features_3_2 = i_features_2_3; +assign o_features_3_3 = if_reg_3_3; +assign features_3_3 = i_features_3_3; +assign o_features_0_4 = if_reg_4_0; +assign features_4_0 = i_features_0_4; +assign o_features_1_4 = if_reg_4_1; +assign features_4_1 = i_features_1_4; +assign o_features_2_4 = if_reg_4_2; +assign features_4_2 = i_features_2_4; +assign o_features_3_4 = if_reg_4_3; +assign features_4_3 = i_features_3_4; +assign o_features_0_5 = if_reg_5_0; +assign features_5_0 = i_features_0_5; +assign o_features_1_5 = if_reg_5_1; +assign features_5_1 = i_features_1_5; +assign o_features_2_5 = if_reg_5_2; +assign features_5_2 = i_features_2_5; +assign o_features_3_5 = if_reg_5_3; +assign features_5_3 = i_features_3_5; + +assign o_valid = done_6; +assign o_next_reset = next_reset; +assign o_next_valid = next_valid; + +endmodule + +module weight_cache_2048_8_0_weight_init_21 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_20 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_23 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_22 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_25 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_24 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module dot_product_16_8_30_4 ( + input clk, + input i_reset, + input [15:0] i_features_0, + input [7:0] i_weights_0, + input [15:0] i_features_1, + input [7:0] i_weights_1, + input [15:0] i_features_2, + input [7:0] i_weights_2, + input [15:0] i_features_3, + input [7:0] i_weights_3, + output [23:0] o_result +); + +wire [63:0] chains_0; +wire [63:0] chains_1; +wire [23:0] res; +reg [15:0] f_pipeline_0_0; +reg [7:0] w_pipeline_0_0; +reg [15:0] f_pipeline_0_1; +reg [7:0] w_pipeline_0_1; +reg [15:0] f_pipeline_1_0; +reg [7:0] w_pipeline_1_0; +reg [15:0] f_pipeline_1_1; +reg [7:0] w_pipeline_1_1; +reg [15:0] f_pipeline_2_0; +reg [7:0] w_pipeline_2_0; +reg [15:0] f_pipeline_2_1; +reg [7:0] w_pipeline_2_1; +reg [15:0] f_pipeline_3_0; +reg [7:0] w_pipeline_3_0; +reg [15:0] f_pipeline_3_1; +reg [7:0] w_pipeline_3_1; +reg r_pipeline_0; +reg r_pipeline_1; + +always @ (posedge clk) begin + r_pipeline_0 <= i_reset; + if(i_reset == 1'b1) begin + f_pipeline_0_0 <= 0; + w_pipeline_0_0 <= 0; + f_pipeline_1_0 <= 0; + w_pipeline_1_0 <= 0; + f_pipeline_2_0 <= 0; + w_pipeline_2_0 <= 0; + f_pipeline_3_0 <= 0; + w_pipeline_3_0 <= 0; + f_pipeline_0_1 <= 0; + w_pipeline_0_1 <= 0; + f_pipeline_1_1 <= 0; + w_pipeline_1_1 <= 0; + f_pipeline_2_1 <= 0; + w_pipeline_2_1 <= 0; + f_pipeline_3_1 <= 0; + w_pipeline_3_1 <= 0; + r_pipeline_1 <= 1'b1; + end else begin + f_pipeline_0_0 <= i_features_0; + w_pipeline_0_0 <= i_weights_0; + f_pipeline_1_0 <= i_features_1; + w_pipeline_1_0 <= i_weights_1; + f_pipeline_2_0 <= i_features_2; + w_pipeline_2_0 <= i_weights_2; + f_pipeline_3_0 <= i_features_3; + w_pipeline_3_0 <= i_weights_3; + r_pipeline_1 <= r_pipeline_0; + f_pipeline_0_1 <= f_pipeline_0_0; + w_pipeline_0_1 <= w_pipeline_0_0; + f_pipeline_1_1 <= f_pipeline_1_0; + w_pipeline_1_1 <= w_pipeline_1_0; + f_pipeline_2_1 <= f_pipeline_2_0; + w_pipeline_2_1 <= w_pipeline_2_0; + f_pipeline_3_1 <= f_pipeline_3_0; + w_pipeline_3_1 <= w_pipeline_3_0; + end +end + +wire [23:0] dummy_res_0; +dsp_block_16_8_false dsp_block_16_8_false_inst_0 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ax(f_pipeline_0_0), + .ay(w_pipeline_0_0), + .bx(f_pipeline_1_0), + .by(w_pipeline_1_0), + .chainin(64'd0), + .chainout(chains_0), + .resulta(dummy_res_0) +); + +dsp_block_16_8_true dsp_block_16_8_true_inst_2 ( + .clk(clk), + .ena(1'b1), + .aclr(r_pipeline_1), + .ax(f_pipeline_2_1), + .ay(w_pipeline_2_1), + .bx(f_pipeline_3_1), + .by(w_pipeline_3_1), + .chainin(chains_0), + .chainout(chains_1), + .resulta(res) +); + +assign o_result = res; + +endmodule + +module dsp_block_16_8_true ( + input clk, + input ena, + input aclr, + input [15:0] ax, + input [7:0] ay, + input [15:0] bx, + input [7:0] by, + input [63:0] chainin, + output [63:0] chainout, + output [23:0] resulta +); + +wire [11:0] mode; +assign mode = 12'b1010_1010_0110; + +`ifdef complex_dsp +int_sop_2 mac_component ( + .mode_sigs(mode), + .clk(clk), + .reset(aclr), + .ax(ax), + .ay(ay), + .bx(bx), + .by(by), + .chainin(chainin), + .result(resulta), + .chainout(chainout) +); +`else +reg [15:0] ax_reg; +reg [7:0] ay_reg; +reg [15:0] bx_reg; +reg [7:0] by_reg; +reg [23:0] resulta_tmp; +always @(posedge clk) begin + if(aclr) begin + resulta_tmp <= 0; + ax_reg <= 0; + ay_reg <= 0; + bx_reg <= 0; + by_reg <= 0; + end + else begin + ax_reg <= ax; + ay_reg <= ay; + bx_reg <= bx; + by_reg <= by; + resulta_tmp <= ax_reg * ay_reg + bx_reg * by_reg + chainin; + end +end +assign resulta = resulta_tmp; +assign chainout = {40'b0, resulta_tmp}; +`endif + + +endmodule + +module dsp_block_16_8_false ( + input clk, + input ena, + input aclr, + input [15:0] ax, + input [7:0] ay, + input [15:0] bx, + input [7:0] by, + input [63:0] chainin, + output [63:0] chainout, + output [23:0] resulta +); + +wire [11:0] mode; +assign mode = 12'b1010_1010_0110; + +`ifdef complex_dsp +int_sop_2 mac_component ( + .mode_sigs(mode), + .clk(clk), + .reset(aclr), + .ax(ax), + .ay(ay), + .bx(bx), + .by(by), + .chainin(chainin), + .result(resulta), + .chainout(chainout) +); +`else +reg [15:0] ax_reg; +reg [7:0] ay_reg; +reg [15:0] bx_reg; +reg [7:0] by_reg; +reg [23:0] resulta_tmp; +always @(posedge clk) begin + if(aclr) begin + resulta_tmp <= 0; + ax_reg <= 0; + ay_reg <= 0; + bx_reg <= 0; + by_reg <= 0; + end + else begin + ax_reg <= ax; + ay_reg <= ay; + bx_reg <= bx; + by_reg <= by; + resulta_tmp <= ax_reg * ay_reg + bx_reg * by_reg + chainin; + end +end +assign resulta = resulta_tmp; +assign chainout = {40'b0, resulta_tmp}; +`endif + +endmodule + +module weight_cache_2048_8_0_weight_init_02 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_03 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module accumulator_24_30_4 ( + input clk, + input i_reset, + input [23:0] i_result, + input i_dp_done, + output [29:0] o_accum +); + +reg [29:0] cir_shift_reg_0; +reg [29:0] cir_shift_reg_1; +reg [29:0] cir_shift_reg_2; +reg [29:0] cir_shift_reg_3; +reg [29:0] out_reg; +reg [29:0] in_reg; + +always @ (posedge clk) begin + if(i_reset == 1'b1) begin + cir_shift_reg_0 <= 0; + cir_shift_reg_1 <= 0; + cir_shift_reg_2 <= 0; + cir_shift_reg_3 <= 0; + out_reg <= 0; + in_reg <= 0; + end else begin + if (i_result[23] == 1'b0) begin + in_reg <= {6'b000000, i_result}; + end else begin + in_reg <= {6'b111111, i_result}; + end + if(i_dp_done == 1'b1) begin + out_reg <= (cir_shift_reg_0 + in_reg); + cir_shift_reg_3 <= 0; + end else begin + cir_shift_reg_3 <= (cir_shift_reg_0 + in_reg); + end + cir_shift_reg_0 <= cir_shift_reg_1; + cir_shift_reg_1 <= cir_shift_reg_2; + cir_shift_reg_2 <= cir_shift_reg_3; + end +end + +assign o_accum = out_reg; + +endmodule + +module weight_cache_2048_8_0_weight_init_01 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_00 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_05 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_04 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module stream_buffer_1_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_11 buffer_16_12100_buffer_init_11_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_11 buffer_16_12100_buffer_init_11_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_11 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_1_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_01 buffer_16_12100_buffer_init_01_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_01 buffer_16_12100_buffer_init_01_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_01 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_1_3 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_31 buffer_16_12100_buffer_init_31_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_31 buffer_16_12100_buffer_init_31_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_31 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_1_2 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_21 buffer_16_12100_buffer_init_21_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_21 buffer_16_12100_buffer_init_21_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_21 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_0_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_00 buffer_16_12100_buffer_init_00_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_00 buffer_16_12100_buffer_init_00_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_00 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_0_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_10 buffer_16_12100_buffer_init_10_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_10 buffer_16_12100_buffer_init_10_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_10 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_0_2 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_20 buffer_16_12100_buffer_init_20_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_20 buffer_16_12100_buffer_init_20_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_20 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_0_3 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_30 buffer_16_12100_buffer_init_30_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_30 buffer_16_12100_buffer_init_30_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_30 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module inverse_winograd_20 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_8_0[29] == 1'b0) begin + result_wire_0 <= result_reg_8_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_8_1[29] == 1'b0) begin + result_wire_1 <= result_reg_8_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_8_2[29] == 1'b0) begin + result_wire_2 <= result_reg_8_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_8_3[29] == 1'b0) begin + result_wire_3 <= result_reg_8_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_8; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_21 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_7_0[29] == 1'b0) begin + result_wire_0 <= result_reg_7_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_7_1[29] == 1'b0) begin + result_wire_1 <= result_reg_7_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_7_2[29] == 1'b0) begin + result_wire_2 <= result_reg_7_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_7_3[29] == 1'b0) begin + result_wire_3 <= result_reg_7_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_7; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module signal_width_reducer ( + input clk, + input [15:0] signals_0_0, + output reduced_signals_0_0, + input [15:0] signals_0_1, + output reduced_signals_0_1, + input [15:0] signals_0_2, + output reduced_signals_0_2, + input [15:0] signals_0_3, + output reduced_signals_0_3, + input [15:0] signals_1_0, + output reduced_signals_1_0, + input [15:0] signals_1_1, + output reduced_signals_1_1, + input [15:0] signals_1_2, + output reduced_signals_1_2, + input [15:0] signals_1_3, + output reduced_signals_1_3, + input [15:0] signals_2_0, + output reduced_signals_2_0, + input [15:0] signals_2_1, + output reduced_signals_2_1, + input [15:0] signals_2_2, + output reduced_signals_2_2, + input [15:0] signals_2_3, + output reduced_signals_2_3, + input [15:0] signals_3_0, + output reduced_signals_3_0, + input [15:0] signals_3_1, + output reduced_signals_3_1, + input [15:0] signals_3_2, + output reduced_signals_3_2, + input [15:0] signals_3_3, + output reduced_signals_3_3, + input [15:0] signals_4_0, + output reduced_signals_4_0, + input [15:0] signals_4_1, + output reduced_signals_4_1, + input [15:0] signals_4_2, + output reduced_signals_4_2, + input [15:0] signals_4_3, + output reduced_signals_4_3, + input [15:0] signals_5_0, + output reduced_signals_5_0, + input [15:0] signals_5_1, + output reduced_signals_5_1, + input [15:0] signals_5_2, + output reduced_signals_5_2, + input [15:0] signals_5_3, + output reduced_signals_5_3, + input reset +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_0_0 ( + .clk(clk), + .reset(reset), + .signal(signals_0_0), + .reduced_signal(reduced_signals_0_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_0_1 ( + .clk(clk), + .reset(reset), + .signal(signals_0_1), + .reduced_signal(reduced_signals_0_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_0_2 ( + .clk(clk), + .reset(reset), + .signal(signals_0_2), + .reduced_signal(reduced_signals_0_2) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_0_3 ( + .clk(clk), + .reset(reset), + .signal(signals_0_3), + .reduced_signal(reduced_signals_0_3) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_1_0 ( + .clk(clk), + .reset(reset), + .signal(signals_1_0), + .reduced_signal(reduced_signals_1_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_1_1 ( + .clk(clk), + .reset(reset), + .signal(signals_1_1), + .reduced_signal(reduced_signals_1_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_1_2 ( + .clk(clk), + .reset(reset), + .signal(signals_1_2), + .reduced_signal(reduced_signals_1_2) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_1_3 ( + .clk(clk), + .reset(reset), + .signal(signals_1_3), + .reduced_signal(reduced_signals_1_3) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_2_0 ( + .clk(clk), + .reset(reset), + .signal(signals_2_0), + .reduced_signal(reduced_signals_2_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_2_1 ( + .clk(clk), + .reset(reset), + .signal(signals_2_1), + .reduced_signal(reduced_signals_2_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_2_2 ( + .clk(clk), + .reset(reset), + .signal(signals_2_2), + .reduced_signal(reduced_signals_2_2) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_2_3 ( + .clk(clk), + .reset(reset), + .signal(signals_2_3), + .reduced_signal(reduced_signals_2_3) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_3_0 ( + .clk(clk), + .reset(reset), + .signal(signals_3_0), + .reduced_signal(reduced_signals_3_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_3_1 ( + .clk(clk), + .reset(reset), + .signal(signals_3_1), + .reduced_signal(reduced_signals_3_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_3_2 ( + .clk(clk), + .reset(reset), + .signal(signals_3_2), + .reduced_signal(reduced_signals_3_2) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_3_3 ( + .clk(clk), + .reset(reset), + .signal(signals_3_3), + .reduced_signal(reduced_signals_3_3) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_4_0 ( + .clk(clk), + .reset(reset), + .signal(signals_4_0), + .reduced_signal(reduced_signals_4_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_4_1 ( + .clk(clk), + .reset(reset), + .signal(signals_4_1), + .reduced_signal(reduced_signals_4_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_4_2 ( + .clk(clk), + .reset(reset), + .signal(signals_4_2), + .reduced_signal(reduced_signals_4_2) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_4_3 ( + .clk(clk), + .reset(reset), + .signal(signals_4_3), + .reduced_signal(reduced_signals_4_3) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_5_0 ( + .clk(clk), + .reset(reset), + .signal(signals_5_0), + .reduced_signal(reduced_signals_5_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_5_1 ( + .clk(clk), + .reset(reset), + .signal(signals_5_1), + .reduced_signal(reduced_signals_5_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_5_2 ( + .clk(clk), + .reset(reset), + .signal(signals_5_2), + .reduced_signal(reduced_signals_5_2) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_5_3 ( + .clk(clk), + .reset(reset), + .signal(signals_5_3), + .reduced_signal(reduced_signals_5_3) +); + +endmodule + +module pipelined_xor_tree_16 ( + input clk, + input reset, + input [15:0] signal, + output reduced_signal +); + +reg pipeline_0_0; +reg pipeline_0_1; +reg pipeline_0_2; +reg pipeline_1_0; +reg pipeline_1_1; +reg pipeline_1_2; +reg pipeline_2_0; +reg pipeline_2_1; +reg pipeline_2_2; +reg pipeline_3_0; +reg pipeline_3_1; +reg pipeline_3_2; +reg pipeline_4_0; +reg pipeline_4_1; +reg pipeline_4_2; +reg pipeline_5_0; +reg pipeline_5_1; +reg pipeline_5_2; +reg pipeline_6_0; +reg pipeline_6_1; +reg pipeline_6_2; +reg pipeline_7_0; +reg pipeline_7_1; +reg pipeline_7_2; +reg pipeline_8_0; +reg pipeline_8_1; +reg pipeline_8_2; +reg pipeline_9_0; +reg pipeline_9_1; +reg pipeline_9_2; +reg pipeline_10_0; +reg pipeline_10_1; +reg pipeline_10_2; +reg pipeline_11_0; +reg pipeline_11_1; +reg pipeline_11_2; +reg pipeline_12_0; +reg pipeline_12_1; +reg pipeline_12_2; +reg pipeline_13_0; +reg pipeline_13_1; +reg pipeline_13_2; +reg pipeline_14_0; +reg pipeline_14_1; +reg pipeline_14_2; +reg pipeline_15_0; +reg pipeline_15_1; +reg pipeline_15_2; + +always @ (posedge clk) begin + if (reset) begin + pipeline_0_0 <= 0; + pipeline_0_1 <= 0; + pipeline_0_2 <= 0; + pipeline_1_0 <= 0; + pipeline_1_1 <= 0; + pipeline_1_2 <= 0; + pipeline_2_0 <= 0; + pipeline_2_1 <= 0; + pipeline_2_2 <= 0; + pipeline_3_0 <= 0; + pipeline_3_1 <= 0; + pipeline_3_2 <= 0; + pipeline_4_0 <= 0; + pipeline_4_1 <= 0; + pipeline_4_2 <= 0; + pipeline_5_0 <= 0; + pipeline_5_1 <= 0; + pipeline_5_2 <= 0; + pipeline_6_0 <= 0; + pipeline_6_1 <= 0; + pipeline_6_2 <= 0; + pipeline_7_0 <= 0; + pipeline_7_1 <= 0; + pipeline_7_2 <= 0; + pipeline_8_0 <= 0; + pipeline_8_1 <= 0; + pipeline_8_2 <= 0; + pipeline_9_0 <= 0; + pipeline_9_1 <= 0; + pipeline_9_2 <= 0; + pipeline_10_0 <= 0; + pipeline_10_1 <= 0; + pipeline_10_2 <= 0; + pipeline_11_0 <= 0; + pipeline_11_1 <= 0; + pipeline_11_2 <= 0; + pipeline_12_0 <= 0; + pipeline_12_1 <= 0; + pipeline_12_2 <= 0; + pipeline_13_0 <= 0; + pipeline_13_1 <= 0; + pipeline_13_2 <= 0; + pipeline_14_0 <= 0; + pipeline_14_1 <= 0; + pipeline_14_2 <= 0; + pipeline_15_0 <= 0; + pipeline_15_1 <= 0; + pipeline_15_2 <= 0; + end else begin + pipeline_0_0 <= signal[15]; + pipeline_1_0 <= signal[14]; + pipeline_2_0 <= signal[13]; + pipeline_3_0 <= signal[12]; + pipeline_4_0 <= signal[11]; + pipeline_5_0 <= signal[10]; + pipeline_6_0 <= signal[9]; + pipeline_7_0 <= signal[8]; + pipeline_8_0 <= signal[7]; + pipeline_9_0 <= signal[6]; + pipeline_10_0 <= signal[5]; + pipeline_11_0 <= signal[4]; + pipeline_12_0 <= signal[3]; + pipeline_13_0 <= signal[2]; + pipeline_14_0 <= signal[1]; + pipeline_15_0 <= signal[0]; + pipeline_0_1 <= pipeline_0_0 ^ pipeline_1_0^ pipeline_2_0 ^ pipeline_3_0; + pipeline_4_1 <= pipeline_4_0 ^ pipeline_5_0^ pipeline_6_0 ^ pipeline_7_0; + pipeline_8_1 <= pipeline_8_0 ^ pipeline_9_0^ pipeline_10_0 ^ pipeline_11_0; + pipeline_12_1 <= pipeline_12_0 ^ pipeline_13_0^ pipeline_14_0 ^ pipeline_15_0; + pipeline_0_2 <= pipeline_0_1 ^ pipeline_4_1^ pipeline_8_1 ^ pipeline_12_1; + end +end + +assign reduced_signal = pipeline_0_2; + +endmodule + +module inverse_winograd_22 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_6_0[29] == 1'b0) begin + result_wire_0 <= result_reg_6_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_6_1[29] == 1'b0) begin + result_wire_1 <= result_reg_6_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_6_2[29] == 1'b0) begin + result_wire_2 <= result_reg_6_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_6_3[29] == 1'b0) begin + result_wire_3 <= result_reg_6_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_6; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module pooling ( + input clk, + input i_valid, + input i_reset, + input [15:0] i_result_0, + input [15:0] i_result_1, + input [15:0] i_result_2, + input [15:0] i_result_3, + output [15:0] o_result, + output o_valid +); + +reg [15:0] buffer_0_0; +reg [15:0] buffer_0_1; +reg [15:0] buffer_1_0; +reg [15:0] buffer_1_1; +reg [1:0] count; +reg [0:0] s_count; +reg [15:0] result_0; +reg [15:0] result_1; +reg valid_1, valid_2, valid_3; + +always @(posedge clk) begin + buffer_0_1 <= buffer_0_0; + buffer_1_1 <= buffer_1_0; + valid_1 <= i_valid; + valid_2 <= valid_1; + valid_3 <= valid_2; + if (i_valid) begin + count <= 0; + end else begin + if(count == 3) begin + count <= 0; + end else begin + count <= count + 1'b1; + end + if(i_result_0 > i_result_1) begin + buffer_0_0 <= i_result_0; + end else begin + buffer_0_0 <= i_result_1; + end + if(i_result_2 > i_result_3) begin + buffer_1_0 <= i_result_2; + end else begin + buffer_1_0 <= i_result_3; + end + end +end + +always @(posedge clk) begin + if (i_reset) begin + s_count <= 0; + end else if (valid_1 || valid_2) begin + if (s_count == 1) begin + if (buffer_0_0 > buffer_0_1) begin + result_0 <= buffer_0_0; + end else begin + result_0 <= buffer_0_1; + end + if (buffer_1_0 > buffer_1_1) begin + result_1 <= buffer_1_0; + end else begin + result_1 <= buffer_1_1; + end + s_count <= 0; + end else begin + result_0 <= result_1; + s_count <= s_count + 1'b1; + end + end else begin + s_count <= 0; + end +end + +assign o_result = result_0; +assign o_valid = valid_3; + +endmodule + +module inverse_winograd_23 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_5_0[29] == 1'b0) begin + result_wire_0 <= result_reg_5_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_5_1[29] == 1'b0) begin + result_wire_1 <= result_reg_5_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_5_2[29] == 1'b0) begin + result_wire_2 <= result_reg_5_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_5_3[29] == 1'b0) begin + result_wire_3 <= result_reg_5_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_5; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module store_output ( + input clk, + input i_valid, + input i_reset, + input [15:0] i_result_0, + input [15:0] i_result_1, + input [15:0] i_result_2, + input [15:0] i_result_3, + input [15:0] i_result_4, + input [15:0] i_result_5, + input [15:0] i_result_6, + input [15:0] i_result_7, + input [15:0] i_result_8, + input [15:0] i_result_9, + input [15:0] i_result_10, + input [15:0] i_result_11, + input [15:0] i_result_12, + input [15:0] i_result_13, + input [15:0] i_result_14, + input [15:0] i_result_15, + input [15:0] i_result_16, + input [15:0] i_result_17, + input [15:0] i_result_18, + input [15:0] i_result_19, + input [15:0] i_result_20, + input [15:0] i_result_21, + input [15:0] i_result_22, + input [15:0] i_result_23, + output [15:0] o_store_0_0, + output [15:0] o_store_0_1, + output [15:0] o_store_0_2, + output [15:0] o_store_0_3, + output [15:0] o_store_1_0, + output [15:0] o_store_1_1, + output [15:0] o_store_1_2, + output [15:0] o_store_1_3, + output [15:0] o_store_2_0, + output [15:0] o_store_2_1, + output [15:0] o_store_2_2, + output [15:0] o_store_2_3, + output [15:0] o_store_3_0, + output [15:0] o_store_3_1, + output [15:0] o_store_3_2, + output [15:0] o_store_3_3, + output [15:0] o_store_4_0, + output [15:0] o_store_4_1, + output [15:0] o_store_4_2, + output [15:0] o_store_4_3, + output [15:0] o_store_5_0, + output [15:0] o_store_5_1, + output [15:0] o_store_5_2, + output [15:0] o_store_5_3, + output o_wen_0, + output o_wen_1, + output o_wen_2, + output o_wen_3, + output o_wen_4, + output o_wen_5, + output [13:0] o_addr +); + +reg wen_0; +reg wen_1; +reg wen_2; +reg wen_3; +reg wen_4; +reg wen_5; +reg [13:0] base_addr; +reg [13:0] offset; +reg [5:0] count; +reg [5:0] count_to_wvec; +reg [5:0] count_x; +reg [5:0] count_y; +reg valid; +reg [15:0] buffer_reg_0; +reg [15:0] buffer_reg_1; +reg [15:0] buffer_reg_2; +reg [15:0] buffer_reg_3; +reg [15:0] buffer_reg_4; +reg [15:0] buffer_reg_5; +reg [15:0] buffer_reg_6; +reg [15:0] buffer_reg_7; +reg [15:0] buffer_reg_8; +reg [15:0] buffer_reg_9; +reg [15:0] buffer_reg_10; +reg [15:0] buffer_reg_11; +reg [15:0] buffer_reg_12; +reg [15:0] buffer_reg_13; +reg [15:0] buffer_reg_14; +reg [15:0] buffer_reg_15; +reg [15:0] buffer_reg_16; +reg [15:0] buffer_reg_17; +reg [15:0] buffer_reg_18; +reg [15:0] buffer_reg_19; +reg [15:0] buffer_reg_20; +reg [15:0] buffer_reg_21; +reg [15:0] buffer_reg_22; +reg [15:0] buffer_reg_23; +reg [13:0] addr_reg; + +wire [5:0] count_div_two; +assign count_div_two = count >> 1; +always @ (posedge clk) begin + valid <= i_valid; + buffer_reg_0 <= i_result_0; + buffer_reg_1 <= i_result_1; + buffer_reg_2 <= i_result_2; + buffer_reg_3 <= i_result_3; + buffer_reg_4 <= i_result_4; + buffer_reg_5 <= i_result_5; + buffer_reg_6 <= i_result_6; + buffer_reg_7 <= i_result_7; + buffer_reg_8 <= i_result_8; + buffer_reg_9 <= i_result_9; + buffer_reg_10 <= i_result_10; + buffer_reg_11 <= i_result_11; + buffer_reg_12 <= i_result_12; + buffer_reg_13 <= i_result_13; + buffer_reg_14 <= i_result_14; + buffer_reg_15 <= i_result_15; + buffer_reg_16 <= i_result_16; + buffer_reg_17 <= i_result_17; + buffer_reg_18 <= i_result_18; + buffer_reg_19 <= i_result_19; + buffer_reg_20 <= i_result_20; + buffer_reg_21 <= i_result_21; + buffer_reg_22 <= i_result_22; + buffer_reg_23 <= i_result_23; + addr_reg <= base_addr + offset; + if (i_reset) begin + count <= 0; + count_to_wvec <= 0; + base_addr <= 0; + offset <= 0; + count_x <= 0; + count_y <= 0; + wen_0 <= 1'b0; + wen_1 <= 1'b0; + wen_2 <= 1'b0; + wen_3 <= 1'b0; + wen_4 <= 1'b0; + wen_5 <= 1'b0; + end else if (i_valid) begin + if (count_x == 5) begin + if(count_y == 6)begin + base_addr <= base_addr + 8; + count_y <= 0; + count_x <= 0; + offset <= 0; + end else begin + if(count[0] == 1'b0) begin + offset <= 4; + count <= count + 1'b1; + if(count_to_wvec == 5) begin + count_to_wvec <= 0; + end else begin + count_to_wvec <= count_to_wvec + 1'b1; + end + end else if (count[1] == 1'b1) begin + offset <= 0; + base_addr <= base_addr + 8; + count_x <= 0; + count_y <= count_y + 2; + count <= count + 1'b1; + if(count_to_wvec == 5) begin + count_to_wvec <= 0; + end else begin + count_to_wvec <= count_to_wvec + 1'b1; + end + end + end + end else if(count[0] == 1'b0) begin + offset <= 4; + count <= count + 1'b1; + if(count_to_wvec == 5) begin + count_to_wvec <= 0; + end else begin + count_to_wvec <= count_to_wvec + 1'b1; + end + end else if (count[0] == 1'b1) begin + offset <= 0; + count <= count + 1'b1; + if(count_to_wvec == 5) begin + count_to_wvec <= 0; + end else begin + count_to_wvec <= count_to_wvec + 1'b1; + end + count_x <= count_x + 1'b1; + end + if ((i_valid || valid) == 1'b1) begin + if ((count_to_wvec == 0) && i_valid == 1) begin + wen_0 <= 1'b1; + end else begin + wen_0 <= 1'b0; + end + if ((count_to_wvec == 1) && i_valid == 1) begin + wen_1 <= 1'b1; + end else begin + wen_1 <= 1'b0; + end + if ((count_to_wvec == 2) && i_valid == 1) begin + wen_2 <= 1'b1; + end else begin + wen_2 <= 1'b0; + end + if ((count_to_wvec == 3) && i_valid == 1) begin + wen_3 <= 1'b1; + end else begin + wen_3 <= 1'b0; + end + if ((count_to_wvec == 4) && i_valid == 1) begin + wen_4 <= 1'b1; + end else begin + wen_4 <= 1'b0; + end + if ((count_to_wvec == 5) && i_valid == 1) begin + wen_5 <= 1'b1; + end else begin + wen_5 <= 1'b0; + end + end + end +end + +assign o_addr = addr_reg; +assign o_store_0_0 = buffer_reg_0; +assign o_store_1_0 = buffer_reg_4; +assign o_store_2_0 = buffer_reg_8; +assign o_store_3_0 = buffer_reg_12; +assign o_store_4_0 = buffer_reg_16; +assign o_store_5_0 = buffer_reg_20; +assign o_store_0_1 = buffer_reg_1; +assign o_store_1_1 = buffer_reg_5; +assign o_store_2_1 = buffer_reg_9; +assign o_store_3_1 = buffer_reg_13; +assign o_store_4_1 = buffer_reg_17; +assign o_store_5_1 = buffer_reg_21; +assign o_store_0_2 = buffer_reg_2; +assign o_store_1_2 = buffer_reg_6; +assign o_store_2_2 = buffer_reg_10; +assign o_store_3_2 = buffer_reg_14; +assign o_store_4_2 = buffer_reg_18; +assign o_store_5_2 = buffer_reg_22; +assign o_store_0_3 = buffer_reg_3; +assign o_store_1_3 = buffer_reg_7; +assign o_store_2_3 = buffer_reg_11; +assign o_store_3_3 = buffer_reg_15; +assign o_store_4_3 = buffer_reg_19; +assign o_store_5_3 = buffer_reg_23; + +assign o_wen_0 = wen_0; +assign o_wen_1 = wen_1; +assign o_wen_2 = wen_2; +assign o_wen_3 = wen_3; +assign o_wen_4 = wen_4; +assign o_wen_5 = wen_5; + +endmodule + +module stream_buffer_3_3 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_33 buffer_16_12100_buffer_init_33_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_33 buffer_16_12100_buffer_init_33_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_33 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_3_2 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_23 buffer_16_12100_buffer_init_23_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_23 buffer_16_12100_buffer_init_23_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_23 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_3_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_13 buffer_16_12100_buffer_init_13_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_13 buffer_16_12100_buffer_init_13_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_13 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_3_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [13:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [13:0] base_addr; +reg [13:0] offset; +reg [13:0] base_addr_b1; +reg [13:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 0) && (L_counter == 3)) begin + base_addr <= base_addr + 4; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 3) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin + base_addr_b1 <= base_addr_b1 + 4; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 3) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 1; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [13:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_12100_buffer_init_03 buffer_16_12100_buffer_init_03_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_12100_buffer_init_03 buffer_16_12100_buffer_init_03_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_12100_buffer_init_03 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module dpram ( + clk, + addr1, + addr2, + we1, + we2, + data1, + data2, + out1, + out2 +); +parameter AWIDTH=10; +parameter NUM_WORDS=1024; +parameter DWIDTH=32; +input clk; +input [(AWIDTH-1):0] addr1; +input [(AWIDTH-1):0] addr2; +input we1; +input we2; +input [(DWIDTH-1):0] data1; +input [(DWIDTH-1):0] data2; +output reg [(DWIDTH-1):0] out1; +output reg [(DWIDTH-1):0] out2; + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram[NUM_WORDS-1:0]; +always @ (posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end + out1 <= ram[addr1]; +end + +always @ (posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end + out2 <= ram[addr2]; +end + +`else +defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; +defparam u_dual_port_ram.DATA_WIDTH = DWIDTH; + +dual_port_ram u_dual_port_ram( +.addr1(addr1), +.we1(we1), +.data1(data1), +.out1(out1), +.addr2(addr2), +.we2(we2), +.data2(data2), +.out2(out2), +.clk(clk) +); + +`endif +endmodule + + diff --git a/designs/koios/dla_like.medium/dla_random.sv b/designs/koios/dla_like.medium/dla_random.sv new file mode 100644 index 000000000..002d9baf2 --- /dev/null +++ b/designs/koios/dla_like.medium/dla_random.sv @@ -0,0 +1,156 @@ +/* +Random input logic for DLA +*/ + +`include "../../random_number_generator.sv" + +module dla_random( + input logic clk, + input logic rst, + input logic i_ddr_wen_0_0, + output logic o_dummy_out_0_0, + input logic i_ddr_wen_0_1, + output logic o_dummy_out_0_1, + input logic i_ddr_wen_0_2, + output logic o_dummy_out_0_2, + input logic i_ddr_wen_0_3, + output logic o_dummy_out_0_3, + input logic i_ddr_wen_1_0, + output logic o_dummy_out_1_0, + input logic i_ddr_wen_1_1, + output logic o_dummy_out_1_1, + input logic i_ddr_wen_1_2, + output logic o_dummy_out_1_2, + input logic i_ddr_wen_1_3, + output logic o_dummy_out_1_3, + input logic i_ddr_wen_2_0, + output logic o_dummy_out_2_0, + input logic i_ddr_wen_2_1, + output logic o_dummy_out_2_1, + input logic i_ddr_wen_2_2, + output logic o_dummy_out_2_2, + input logic i_ddr_wen_2_3, + output logic o_dummy_out_2_3, + input logic i_ddr_wen_3_0, + output logic o_dummy_out_3_0, + input logic i_ddr_wen_3_1, + output logic o_dummy_out_3_1, + input logic i_ddr_wen_3_2, + output logic o_dummy_out_3_2, + input logic i_ddr_wen_3_3, + output logic o_dummy_out_3_3, + input logic i_ddr_wen_4_0, + output logic o_dummy_out_4_0, + input logic i_ddr_wen_4_1, + output logic o_dummy_out_4_1, + input logic i_ddr_wen_4_2, + output logic o_dummy_out_4_2, + input logic i_ddr_wen_4_3, + output logic o_dummy_out_4_3, + input logic i_ddr_wen_5_0, + output logic o_dummy_out_5_0, + input logic i_ddr_wen_5_1, + output logic o_dummy_out_5_1, + input logic i_ddr_wen_5_2, + output logic o_dummy_out_5_2, + input logic i_ddr_wen_5_3, + output logic o_dummy_out_5_3, + output logic o_valid +); + +logic [15:0] i_ddr[5:0][3:0]; +generate // generate block for random number generator +genvar i; +genvar j; +for(i=0; i<6; i=i+1) begin + for(j=0; j<4; j=j+1) begin + RandomNumberGenerator #(16, i+j) random_number_generator_0( + .clk(clk), + .reset(rst), + .random_number(i_ddr[i][j]) + ); + end +end +endgenerate + + +DLA dla0( + clk, + rst, + i_ddr_wen_0_0, + i_ddr[0][0], + o_dummy_out_0_0, + i_ddr_wen_0_1, + i_ddr[0][1], + o_dummy_out_0_1, + i_ddr_wen_0_2, + i_ddr[0][2], + o_dummy_out_0_2, + i_ddr_wen_0_3, + i_ddr[0][3], + o_dummy_out_0_3, + i_ddr_wen_1_0, + i_ddr[1][0], + o_dummy_out_1_0, + i_ddr_wen_1_1, + i_ddr[1][1], + o_dummy_out_1_1, + i_ddr_wen_1_2, + i_ddr[1][2], + o_dummy_out_1_2, + i_ddr_wen_1_3, + i_ddr[1][3], + o_dummy_out_1_3, + i_ddr_wen_2_0, + i_ddr[2][0], + o_dummy_out_2_0, + i_ddr_wen_2_1, + i_ddr[2][1], + o_dummy_out_2_1, + i_ddr_wen_2_2, + i_ddr[2][2], + o_dummy_out_2_2, + i_ddr_wen_2_3, + i_ddr[2][3], + o_dummy_out_2_3, + i_ddr_wen_3_0, + i_ddr[3][0], + o_dummy_out_3_0, + i_ddr_wen_3_1, + i_ddr[3][1], + o_dummy_out_3_1, + i_ddr_wen_3_2, + i_ddr[3][2], + o_dummy_out_3_2, + i_ddr_wen_3_3, + i_ddr[3][3], + o_dummy_out_3_3, + i_ddr_wen_4_0, + i_ddr[4][0], + o_dummy_out_4_0, + i_ddr_wen_4_1, + i_ddr[4][1], + o_dummy_out_4_1, + i_ddr_wen_4_2, + i_ddr[4][2], + o_dummy_out_4_2, + i_ddr_wen_4_3, + i_ddr[4][3], + o_dummy_out_4_3, + i_ddr_wen_5_0, + i_ddr[5][0], + o_dummy_out_5_0, + i_ddr_wen_5_1, + i_ddr[5][1], + o_dummy_out_5_1, + i_ddr_wen_5_2, + i_ddr[5][2], + o_dummy_out_5_2, + i_ddr_wen_5_3, + i_ddr[5][3], + o_dummy_out_5_3, + o_valid +); + + +endmodule \ No newline at end of file diff --git a/designs/koios/dla_like.small/design.yaml b/designs/koios/dla_like.small/design.yaml new file mode 100644 index 000000000..9262b6f01 --- /dev/null +++ b/designs/koios/dla_like.small/design.yaml @@ -0,0 +1 @@ +top: DLA \ No newline at end of file diff --git a/designs/koios/dla_like.small/dla_like.small.v b/designs/koios/dla_like.small/dla_like.small.v new file mode 100644 index 000000000..7d02b56be --- /dev/null +++ b/designs/koios/dla_like.small/dla_like.small.v @@ -0,0 +1,14570 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Andrew Boutros +////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +//A CNN accelerator overlay called DLA from Intel based on the paper: +//U. Aydonat et al., “An OpenCL Deep Learning Accelerator on Arria10,” in International Symposium on Field-Programmable Gate Arrays (FPGA), 2017. +//This design was also used in this paper: +//A. Boutros et al., “You Cannot Improve What You Do Not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference,” ACM Transactions on Reconfigurable Technology Systems (TRETS), vol. 11, no. 3, 2018 +// +//Some properties of the design are: +//1. 16-bit fixed point for activations, 8-bit fixed point for weights +//2. Winograd Transform based convolution. +//3. 2D mac array. Centralized weight buffer for processing elements. +//4. Double-buffering after each layer. +/////////////////////////////////////////////////////////////////////////////// + + +module DLA ( + input clk, + input i_reset, + input i_ddr_wen_0_0, + input [15:0] i_ddr_0_0, + output o_dummy_out_0_0, + input i_ddr_wen_0_1, + input [15:0] i_ddr_0_1, + output o_dummy_out_0_1, + input i_ddr_wen_1_0, + input [15:0] i_ddr_1_0, + output o_dummy_out_1_0, + input i_ddr_wen_1_1, + input [15:0] i_ddr_1_1, + output o_dummy_out_1_1, + input i_ddr_wen_2_0, + input [15:0] i_ddr_2_0, + output o_dummy_out_2_0, + input i_ddr_wen_2_1, + input [15:0] i_ddr_2_1, + output o_dummy_out_2_1, + input i_ddr_wen_3_0, + input [15:0] i_ddr_3_0, + output o_dummy_out_3_0, + input i_ddr_wen_3_1, + input [15:0] i_ddr_3_1, + output o_dummy_out_3_1, + input i_ddr_wen_4_0, + input [15:0] i_ddr_4_0, + output o_dummy_out_4_0, + input i_ddr_wen_4_1, + input [15:0] i_ddr_4_1, + output o_dummy_out_4_1, + input i_ddr_wen_5_0, + input [15:0] i_ddr_5_0, + output o_dummy_out_5_0, + input i_ddr_wen_5_1, + input [15:0] i_ddr_5_1, + output o_dummy_out_5_1, + output o_valid +); + +wire [15:0] f_buffer_pe_0_0; +wire valid_buff_0_0; +wire [15:0] f_buffer_pe_0_1; +wire valid_buff_0_1; +wire [15:0] f_buffer_pe_1_0; +wire valid_buff_1_0; +wire [15:0] f_buffer_pe_1_1; +wire valid_buff_1_1; +wire [15:0] f_buffer_pe_2_0; +wire valid_buff_2_0; +wire [15:0] f_buffer_pe_2_1; +wire valid_buff_2_1; +wire [15:0] f_buffer_pe_3_0; +wire valid_buff_3_0; +wire [15:0] f_buffer_pe_3_1; +wire valid_buff_3_1; +wire [15:0] f_buffer_pe_4_0; +wire valid_buff_4_0; +wire [15:0] f_buffer_pe_4_1; +wire valid_buff_4_1; +wire [15:0] f_buffer_pe_5_0; +wire valid_buff_5_0; +wire [15:0] f_buffer_pe_5_1; +wire valid_buff_5_1; +wire ready; +wire [15:0] f_winograd_0_0; +wire [15:0] f_winograd_0_1; +wire [15:0] f_winograd_0_2; +wire [15:0] f_winograd_0_3; +wire [15:0] f_winograd_0_4; +wire [15:0] f_winograd_0_5; +wire [15:0] f_winograd_1_0; +wire [15:0] f_winograd_1_1; +wire [15:0] f_winograd_1_2; +wire [15:0] f_winograd_1_3; +wire [15:0] f_winograd_1_4; +wire [15:0] f_winograd_1_5; +wire winograd_valid_0; +wire winograd_valid_1; + +// PE Wires +wire [15:0] daisy_chain_0_0_0; +wire [15:0] daisy_chain_0_0_1; +wire [15:0] daisy_chain_0_0_2; +wire [15:0] daisy_chain_0_0_3; +wire [15:0] daisy_chain_0_0_4; +wire [15:0] daisy_chain_0_0_5; +wire [15:0] daisy_chain_0_1_0; +wire [15:0] daisy_chain_0_1_1; +wire [15:0] daisy_chain_0_1_2; +wire [15:0] daisy_chain_0_1_3; +wire [15:0] daisy_chain_0_1_4; +wire [15:0] daisy_chain_0_1_5; +wire [15:0] daisy_chain_1_0_0; +wire [15:0] daisy_chain_1_0_1; +wire [15:0] daisy_chain_1_0_2; +wire [15:0] daisy_chain_1_0_3; +wire [15:0] daisy_chain_1_0_4; +wire [15:0] daisy_chain_1_0_5; +wire [15:0] daisy_chain_1_1_0; +wire [15:0] daisy_chain_1_1_1; +wire [15:0] daisy_chain_1_1_2; +wire [15:0] daisy_chain_1_1_3; +wire [15:0] daisy_chain_1_1_4; +wire [15:0] daisy_chain_1_1_5; +wire [15:0] daisy_chain_2_0_0; +wire [15:0] daisy_chain_2_0_1; +wire [15:0] daisy_chain_2_0_2; +wire [15:0] daisy_chain_2_0_3; +wire [15:0] daisy_chain_2_0_4; +wire [15:0] daisy_chain_2_0_5; +wire [15:0] daisy_chain_2_1_0; +wire [15:0] daisy_chain_2_1_1; +wire [15:0] daisy_chain_2_1_2; +wire [15:0] daisy_chain_2_1_3; +wire [15:0] daisy_chain_2_1_4; +wire [15:0] daisy_chain_2_1_5; +wire [15:0] daisy_chain_3_0_0; +wire [15:0] daisy_chain_3_0_1; +wire [15:0] daisy_chain_3_0_2; +wire [15:0] daisy_chain_3_0_3; +wire [15:0] daisy_chain_3_0_4; +wire [15:0] daisy_chain_3_0_5; +wire [15:0] daisy_chain_3_1_0; +wire [15:0] daisy_chain_3_1_1; +wire [15:0] daisy_chain_3_1_2; +wire [15:0] daisy_chain_3_1_3; +wire [15:0] daisy_chain_3_1_4; +wire [15:0] daisy_chain_3_1_5; +wire [15:0] daisy_chain_4_0_0; +wire [15:0] daisy_chain_4_0_1; +wire [15:0] daisy_chain_4_0_2; +wire [15:0] daisy_chain_4_0_3; +wire [15:0] daisy_chain_4_0_4; +wire [15:0] daisy_chain_4_0_5; +wire [15:0] daisy_chain_4_1_0; +wire [15:0] daisy_chain_4_1_1; +wire [15:0] daisy_chain_4_1_2; +wire [15:0] daisy_chain_4_1_3; +wire [15:0] daisy_chain_4_1_4; +wire [15:0] daisy_chain_4_1_5; +wire [15:0] daisy_chain_5_0_0; +wire [15:0] daisy_chain_5_0_1; +wire [15:0] daisy_chain_5_0_2; +wire [15:0] daisy_chain_5_0_3; +wire [15:0] daisy_chain_5_0_4; +wire [15:0] daisy_chain_5_0_5; +wire [15:0] daisy_chain_5_1_0; +wire [15:0] daisy_chain_5_1_1; +wire [15:0] daisy_chain_5_1_2; +wire [15:0] daisy_chain_5_1_3; +wire [15:0] daisy_chain_5_1_4; +wire [15:0] daisy_chain_5_1_5; +wire [15:0] daisy_chain_6_0_0; +wire [15:0] daisy_chain_6_0_1; +wire [15:0] daisy_chain_6_0_2; +wire [15:0] daisy_chain_6_0_3; +wire [15:0] daisy_chain_6_0_4; +wire [15:0] daisy_chain_6_0_5; +wire [15:0] daisy_chain_6_1_0; +wire [15:0] daisy_chain_6_1_1; +wire [15:0] daisy_chain_6_1_2; +wire [15:0] daisy_chain_6_1_3; +wire [15:0] daisy_chain_6_1_4; +wire [15:0] daisy_chain_6_1_5; +wire [15:0] daisy_chain_7_0_0; +wire [15:0] daisy_chain_7_0_1; +wire [15:0] daisy_chain_7_0_2; +wire [15:0] daisy_chain_7_0_3; +wire [15:0] daisy_chain_7_0_4; +wire [15:0] daisy_chain_7_0_5; +wire [15:0] daisy_chain_7_1_0; +wire [15:0] daisy_chain_7_1_1; +wire [15:0] daisy_chain_7_1_2; +wire [15:0] daisy_chain_7_1_3; +wire [15:0] daisy_chain_7_1_4; +wire [15:0] daisy_chain_7_1_5; +wire [15:0] daisy_chain_8_0_0; +wire [15:0] daisy_chain_8_0_1; +wire [15:0] daisy_chain_8_0_2; +wire [15:0] daisy_chain_8_0_3; +wire [15:0] daisy_chain_8_0_4; +wire [15:0] daisy_chain_8_0_5; +wire [15:0] daisy_chain_8_1_0; +wire [15:0] daisy_chain_8_1_1; +wire [15:0] daisy_chain_8_1_2; +wire [15:0] daisy_chain_8_1_3; +wire [15:0] daisy_chain_8_1_4; +wire [15:0] daisy_chain_8_1_5; +wire [15:0] daisy_chain_9_0_0; +wire [15:0] daisy_chain_9_0_1; +wire [15:0] daisy_chain_9_0_2; +wire [15:0] daisy_chain_9_0_3; +wire [15:0] daisy_chain_9_0_4; +wire [15:0] daisy_chain_9_0_5; +wire [15:0] daisy_chain_9_1_0; +wire [15:0] daisy_chain_9_1_1; +wire [15:0] daisy_chain_9_1_2; +wire [15:0] daisy_chain_9_1_3; +wire [15:0] daisy_chain_9_1_4; +wire [15:0] daisy_chain_9_1_5; +wire [15:0] daisy_chain_10_0_0; +wire [15:0] daisy_chain_10_0_1; +wire [15:0] daisy_chain_10_0_2; +wire [15:0] daisy_chain_10_0_3; +wire [15:0] daisy_chain_10_0_4; +wire [15:0] daisy_chain_10_0_5; +wire [15:0] daisy_chain_10_1_0; +wire [15:0] daisy_chain_10_1_1; +wire [15:0] daisy_chain_10_1_2; +wire [15:0] daisy_chain_10_1_3; +wire [15:0] daisy_chain_10_1_4; +wire [15:0] daisy_chain_10_1_5; +wire [15:0] daisy_chain_11_0_0; +wire [15:0] daisy_chain_11_0_1; +wire [15:0] daisy_chain_11_0_2; +wire [15:0] daisy_chain_11_0_3; +wire [15:0] daisy_chain_11_0_4; +wire [15:0] daisy_chain_11_0_5; +wire [15:0] daisy_chain_11_1_0; +wire [15:0] daisy_chain_11_1_1; +wire [15:0] daisy_chain_11_1_2; +wire [15:0] daisy_chain_11_1_3; +wire [15:0] daisy_chain_11_1_4; +wire [15:0] daisy_chain_11_1_5; +wire [29:0] PE_output_0_0; +wire [29:0] PE_output_0_1; +wire [29:0] PE_output_0_2; +wire [29:0] PE_output_0_3; +wire [29:0] PE_output_0_4; +wire [29:0] PE_output_0_5; +wire [29:0] PE_output_1_0; +wire [29:0] PE_output_1_1; +wire [29:0] PE_output_1_2; +wire [29:0] PE_output_1_3; +wire [29:0] PE_output_1_4; +wire [29:0] PE_output_1_5; +wire [29:0] PE_output_2_0; +wire [29:0] PE_output_2_1; +wire [29:0] PE_output_2_2; +wire [29:0] PE_output_2_3; +wire [29:0] PE_output_2_4; +wire [29:0] PE_output_2_5; +wire [29:0] PE_output_3_0; +wire [29:0] PE_output_3_1; +wire [29:0] PE_output_3_2; +wire [29:0] PE_output_3_3; +wire [29:0] PE_output_3_4; +wire [29:0] PE_output_3_5; +wire [29:0] PE_output_4_0; +wire [29:0] PE_output_4_1; +wire [29:0] PE_output_4_2; +wire [29:0] PE_output_4_3; +wire [29:0] PE_output_4_4; +wire [29:0] PE_output_4_5; +wire [29:0] PE_output_5_0; +wire [29:0] PE_output_5_1; +wire [29:0] PE_output_5_2; +wire [29:0] PE_output_5_3; +wire [29:0] PE_output_5_4; +wire [29:0] PE_output_5_5; +wire [29:0] PE_output_6_0; +wire [29:0] PE_output_6_1; +wire [29:0] PE_output_6_2; +wire [29:0] PE_output_6_3; +wire [29:0] PE_output_6_4; +wire [29:0] PE_output_6_5; +wire [29:0] PE_output_7_0; +wire [29:0] PE_output_7_1; +wire [29:0] PE_output_7_2; +wire [29:0] PE_output_7_3; +wire [29:0] PE_output_7_4; +wire [29:0] PE_output_7_5; +wire [29:0] PE_output_8_0; +wire [29:0] PE_output_8_1; +wire [29:0] PE_output_8_2; +wire [29:0] PE_output_8_3; +wire [29:0] PE_output_8_4; +wire [29:0] PE_output_8_5; +wire [29:0] PE_output_9_0; +wire [29:0] PE_output_9_1; +wire [29:0] PE_output_9_2; +wire [29:0] PE_output_9_3; +wire [29:0] PE_output_9_4; +wire [29:0] PE_output_9_5; +wire [29:0] PE_output_10_0; +wire [29:0] PE_output_10_1; +wire [29:0] PE_output_10_2; +wire [29:0] PE_output_10_3; +wire [29:0] PE_output_10_4; +wire [29:0] PE_output_10_5; +wire [29:0] PE_output_11_0; +wire [29:0] PE_output_11_1; +wire [29:0] PE_output_11_2; +wire [29:0] PE_output_11_3; +wire [29:0] PE_output_11_4; +wire [29:0] PE_output_11_5; +wire PE_valid_0; +wire PE_next_reset_0; +wire PE_next_valid_0; +wire PE_valid_1; +wire PE_next_reset_1; +wire PE_next_valid_1; +wire PE_valid_2; +wire PE_next_reset_2; +wire PE_next_valid_2; +wire PE_valid_3; +wire PE_next_reset_3; +wire PE_next_valid_3; +wire PE_valid_4; +wire PE_next_reset_4; +wire PE_next_valid_4; +wire PE_valid_5; +wire PE_next_reset_5; +wire PE_next_valid_5; +wire PE_valid_6; +wire PE_next_reset_6; +wire PE_next_valid_6; +wire PE_valid_7; +wire PE_next_reset_7; +wire PE_next_valid_7; +wire PE_valid_8; +wire PE_next_reset_8; +wire PE_next_valid_8; +wire PE_valid_9; +wire PE_next_reset_9; +wire PE_next_valid_9; +wire PE_valid_10; +wire PE_next_reset_10; +wire PE_next_valid_10; +wire PE_valid_11; +wire PE_next_reset_11; +wire PE_next_valid_11; + +// Inverse Winograd Wires +wire [15:0] INV_output_0_0; +wire [15:0] INV_output_0_1; +wire [15:0] INV_output_0_2; +wire [15:0] INV_output_0_3; +wire INV_valid_0; +wire [15:0] INV_output_1_0; +wire [15:0] INV_output_1_1; +wire [15:0] INV_output_1_2; +wire [15:0] INV_output_1_3; +wire INV_valid_1; +wire [15:0] INV_output_2_0; +wire [15:0] INV_output_2_1; +wire [15:0] INV_output_2_2; +wire [15:0] INV_output_2_3; +wire INV_valid_2; +wire [15:0] INV_output_3_0; +wire [15:0] INV_output_3_1; +wire [15:0] INV_output_3_2; +wire [15:0] INV_output_3_3; +wire INV_valid_3; +wire [15:0] INV_output_4_0; +wire [15:0] INV_output_4_1; +wire [15:0] INV_output_4_2; +wire [15:0] INV_output_4_3; +wire INV_valid_4; +wire [15:0] INV_output_5_0; +wire [15:0] INV_output_5_1; +wire [15:0] INV_output_5_2; +wire [15:0] INV_output_5_3; +wire INV_valid_5; +wire [15:0] INV_output_6_0; +wire [15:0] INV_output_6_1; +wire [15:0] INV_output_6_2; +wire [15:0] INV_output_6_3; +wire INV_valid_6; +wire [15:0] INV_output_7_0; +wire [15:0] INV_output_7_1; +wire [15:0] INV_output_7_2; +wire [15:0] INV_output_7_3; +wire INV_valid_7; +wire [15:0] INV_output_8_0; +wire [15:0] INV_output_8_1; +wire [15:0] INV_output_8_2; +wire [15:0] INV_output_8_3; +wire INV_valid_8; +wire [15:0] INV_output_9_0; +wire [15:0] INV_output_9_1; +wire [15:0] INV_output_9_2; +wire [15:0] INV_output_9_3; +wire INV_valid_9; +wire [15:0] INV_output_10_0; +wire [15:0] INV_output_10_1; +wire [15:0] INV_output_10_2; +wire [15:0] INV_output_10_3; +wire INV_valid_10; +wire [15:0] INV_output_11_0; +wire [15:0] INV_output_11_1; +wire [15:0] INV_output_11_2; +wire [15:0] INV_output_11_3; +wire INV_valid_11; + +// Pooling Wires +wire [15:0] POOL_output_0; +wire POOL_valid_0; +wire [15:0] POOL_output_1; +wire POOL_valid_1; +wire [15:0] POOL_output_2; +wire POOL_valid_2; +wire [15:0] POOL_output_3; +wire POOL_valid_3; +wire [15:0] POOL_output_4; +wire POOL_valid_4; +wire [15:0] POOL_output_5; +wire POOL_valid_5; +wire [15:0] POOL_output_6; +wire POOL_valid_6; +wire [15:0] POOL_output_7; +wire POOL_valid_7; +wire [15:0] POOL_output_8; +wire POOL_valid_8; +wire [15:0] POOL_output_9; +wire POOL_valid_9; +wire [15:0] POOL_output_10; +wire POOL_valid_10; +wire [15:0] POOL_output_11; +wire POOL_valid_11; + +// Store Output Wires +wire [15:0] STORE_output_0_0; +wire [15:0] STORE_output_0_1; +wire [15:0] STORE_output_1_0; +wire [15:0] STORE_output_1_1; +wire [15:0] STORE_output_2_0; +wire [15:0] STORE_output_2_1; +wire [15:0] STORE_output_3_0; +wire [15:0] STORE_output_3_1; +wire [15:0] STORE_output_4_0; +wire [15:0] STORE_output_4_1; +wire [15:0] STORE_output_5_0; +wire [15:0] STORE_output_5_1; +wire [14:0] STORE_addr; +wire STORE_wen_0; +wire STORE_wen_1; +wire STORE_wen_2; +wire STORE_wen_3; +wire STORE_wen_4; +wire STORE_wen_5; + +// Eltwise Wires +wire [15:0] f_buffer_el_0_0; +wire [15:0] f_buffer_el_0_1; +wire [15:0] f_buffer_el_1_0; +wire [15:0] f_buffer_el_1_1; +wire [15:0] f_buffer_el_2_0; +wire [15:0] f_buffer_el_2_1; +wire [15:0] f_buffer_el_3_0; +wire [15:0] f_buffer_el_3_1; +wire [15:0] f_buffer_el_4_0; +wire [15:0] f_buffer_el_4_1; +wire [15:0] f_buffer_el_5_0; +wire [15:0] f_buffer_el_5_1; + +// Output Wires +wire [15:0] dummy_out_0_0; +wire [15:0] dummy_out_0_1; +wire [15:0] dummy_out_1_0; +wire [15:0] dummy_out_1_1; +wire [15:0] dummy_out_2_0; +wire [15:0] dummy_out_2_1; +wire [15:0] dummy_out_3_0; +wire [15:0] dummy_out_3_1; +wire [15:0] dummy_out_4_0; +wire [15:0] dummy_out_4_1; +wire [15:0] dummy_out_5_0; +wire [15:0] dummy_out_5_1; + +stream_buffer_0_0 stream_buffer_0_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_0_0), + .i_wen1(STORE_wen_0), + .i_ddr(i_ddr_0_0), + .i_pool(STORE_output_0_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_0_0), + .o_feature_1(f_buffer_el_0_0), + .o_done(valid_buff_0_0) +); +assign dummy_out_0_0 = f_buffer_el_0_0; + +stream_buffer_0_1 stream_buffer_0_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_0_1), + .i_wen1(STORE_wen_0), + .i_ddr(i_ddr_0_1), + .i_pool(STORE_output_0_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_0_1), + .o_feature_1(f_buffer_el_0_1), + .o_done(valid_buff_0_1) +); +assign dummy_out_0_1 = f_buffer_el_0_1; + +stream_buffer_1_0 stream_buffer_1_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_1_0), + .i_wen1(STORE_wen_1), + .i_ddr(i_ddr_1_0), + .i_pool(STORE_output_1_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_1_0), + .o_feature_1(f_buffer_el_1_0), + .o_done(valid_buff_1_0) +); +assign dummy_out_1_0 = f_buffer_el_1_0; + +stream_buffer_1_1 stream_buffer_1_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_1_1), + .i_wen1(STORE_wen_1), + .i_ddr(i_ddr_1_1), + .i_pool(STORE_output_1_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_1_1), + .o_feature_1(f_buffer_el_1_1), + .o_done(valid_buff_1_1) +); +assign dummy_out_1_1 = f_buffer_el_1_1; + +stream_buffer_2_0 stream_buffer_2_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_2_0), + .i_wen1(STORE_wen_2), + .i_ddr(i_ddr_2_0), + .i_pool(STORE_output_2_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_2_0), + .o_feature_1(f_buffer_el_2_0), + .o_done(valid_buff_2_0) +); +assign dummy_out_2_0 = f_buffer_el_2_0; + +stream_buffer_2_1 stream_buffer_2_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_2_1), + .i_wen1(STORE_wen_2), + .i_ddr(i_ddr_2_1), + .i_pool(STORE_output_2_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_2_1), + .o_feature_1(f_buffer_el_2_1), + .o_done(valid_buff_2_1) +); +assign dummy_out_2_1 = f_buffer_el_2_1; + +stream_buffer_3_0 stream_buffer_3_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_3_0), + .i_wen1(STORE_wen_3), + .i_ddr(i_ddr_3_0), + .i_pool(STORE_output_3_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_3_0), + .o_feature_1(f_buffer_el_3_0), + .o_done(valid_buff_3_0) +); +assign dummy_out_3_0 = f_buffer_el_3_0; + +stream_buffer_3_1 stream_buffer_3_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_3_1), + .i_wen1(STORE_wen_3), + .i_ddr(i_ddr_3_1), + .i_pool(STORE_output_3_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_3_1), + .o_feature_1(f_buffer_el_3_1), + .o_done(valid_buff_3_1) +); +assign dummy_out_3_1 = f_buffer_el_3_1; + +stream_buffer_4_0 stream_buffer_4_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_4_0), + .i_wen1(STORE_wen_4), + .i_ddr(i_ddr_4_0), + .i_pool(STORE_output_4_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_4_0), + .o_feature_1(f_buffer_el_4_0), + .o_done(valid_buff_4_0) +); +assign dummy_out_4_0 = f_buffer_el_4_0; + +stream_buffer_4_1 stream_buffer_4_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_4_1), + .i_wen1(STORE_wen_4), + .i_ddr(i_ddr_4_1), + .i_pool(STORE_output_4_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_4_1), + .o_feature_1(f_buffer_el_4_1), + .o_done(valid_buff_4_1) +); +assign dummy_out_4_1 = f_buffer_el_4_1; + +stream_buffer_5_0 stream_buffer_5_0_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_5_0), + .i_wen1(STORE_wen_5), + .i_ddr(i_ddr_5_0), + .i_pool(STORE_output_5_0), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_5_0), + .o_feature_1(f_buffer_el_5_0), + .o_done(valid_buff_5_0) +); +assign dummy_out_5_0 = f_buffer_el_5_0; + +stream_buffer_5_1 stream_buffer_5_1_inst ( + .clk(clk), + .i_reset(i_reset), + .i_wen0(i_ddr_wen_5_1), + .i_wen1(STORE_wen_5), + .i_ddr(i_ddr_5_1), + .i_pool(STORE_output_5_1), + .i_eltwise_sel(1'b0), + .i_eltwise(0), + .i_waddr(STORE_addr), + .o_feature_0(f_buffer_pe_5_1), + .o_feature_1(f_buffer_el_5_1), + .o_done(valid_buff_5_1) +); +assign dummy_out_5_1 = f_buffer_el_5_1; + +winograd_transform_0 winograd_transform_0_inst ( + .clk(clk), + .i_valid(valid_buff_0_0), + .i_result_0_0(f_buffer_pe_0_0), + .i_result_0_1(f_buffer_pe_0_1), + .i_result_1_0(f_buffer_pe_1_0), + .i_result_1_1(f_buffer_pe_1_1), + .i_result_2_0(f_buffer_pe_2_0), + .i_result_2_1(f_buffer_pe_2_1), + .i_result_3_0(f_buffer_pe_3_0), + .i_result_3_1(f_buffer_pe_3_1), + .i_result_4_0(f_buffer_pe_4_0), + .i_result_4_1(f_buffer_pe_4_1), + .i_result_5_0(f_buffer_pe_5_0), + .i_result_5_1(f_buffer_pe_5_1), + .o_feature_0(f_winograd_0_0), + .o_feature_1(f_winograd_0_1), + .o_feature_2(f_winograd_0_2), + .o_feature_3(f_winograd_0_3), + .o_feature_4(f_winograd_0_4), + .o_feature_5(f_winograd_0_5), + .o_valid(winograd_valid_0) +); + +winograd_transform_1 winograd_transform_1_inst ( + .clk(clk), + .i_valid(valid_buff_0_0), + .i_result_0_0(f_buffer_pe_0_0), + .i_result_0_1(f_buffer_pe_0_1), + .i_result_1_0(f_buffer_pe_1_0), + .i_result_1_1(f_buffer_pe_1_1), + .i_result_2_0(f_buffer_pe_2_0), + .i_result_2_1(f_buffer_pe_2_1), + .i_result_3_0(f_buffer_pe_3_0), + .i_result_3_1(f_buffer_pe_3_1), + .i_result_4_0(f_buffer_pe_4_0), + .i_result_4_1(f_buffer_pe_4_1), + .i_result_5_0(f_buffer_pe_5_0), + .i_result_5_1(f_buffer_pe_5_1), + .o_feature_0(f_winograd_1_0), + .o_feature_1(f_winograd_1_1), + .o_feature_2(f_winograd_1_2), + .o_feature_3(f_winograd_1_3), + .o_feature_4(f_winograd_1_4), + .o_feature_5(f_winograd_1_5), + .o_valid(winograd_valid_1) +); + +processing_element processing_element_inst_0 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(winograd_valid_0), + .i_features_0_0(f_winograd_0_0), + .o_features_0_0(daisy_chain_0_0_0), + .i_features_0_1(f_winograd_0_1), + .o_features_0_1(daisy_chain_0_0_1), + .i_features_0_2(f_winograd_0_2), + .o_features_0_2(daisy_chain_0_0_2), + .i_features_0_3(f_winograd_0_3), + .o_features_0_3(daisy_chain_0_0_3), + .i_features_0_4(f_winograd_0_4), + .o_features_0_4(daisy_chain_0_0_4), + .i_features_0_5(f_winograd_0_5), + .o_features_0_5(daisy_chain_0_0_5), + .i_features_1_0(f_winograd_1_0), + .o_features_1_0(daisy_chain_0_1_0), + .i_features_1_1(f_winograd_1_1), + .o_features_1_1(daisy_chain_0_1_1), + .i_features_1_2(f_winograd_1_2), + .o_features_1_2(daisy_chain_0_1_2), + .i_features_1_3(f_winograd_1_3), + .o_features_1_3(daisy_chain_0_1_3), + .i_features_1_4(f_winograd_1_4), + .o_features_1_4(daisy_chain_0_1_4), + .i_features_1_5(f_winograd_1_5), + .o_features_1_5(daisy_chain_0_1_5), + .o_result_0(PE_output_0_0), + .o_result_1(PE_output_0_1), + .o_result_2(PE_output_0_2), + .o_result_3(PE_output_0_3), + .o_result_4(PE_output_0_4), + .o_result_5(PE_output_0_5), + .o_valid(PE_valid_0), + .o_next_reset(PE_next_reset_0), + .o_next_valid(PE_next_valid_0) +); + +processing_element processing_element_inst_1 ( + .clk(clk), + .i_reset(PE_next_reset_0), + .i_valid(PE_next_valid_0), + .i_features_0_0(daisy_chain_0_0_0), + .o_features_0_0(daisy_chain_1_0_0), + .i_features_0_1(daisy_chain_0_0_1), + .o_features_0_1(daisy_chain_1_0_1), + .i_features_0_2(daisy_chain_0_0_2), + .o_features_0_2(daisy_chain_1_0_2), + .i_features_0_3(daisy_chain_0_0_3), + .o_features_0_3(daisy_chain_1_0_3), + .i_features_0_4(daisy_chain_0_0_4), + .o_features_0_4(daisy_chain_1_0_4), + .i_features_0_5(daisy_chain_0_0_5), + .o_features_0_5(daisy_chain_1_0_5), + .i_features_1_0(daisy_chain_0_1_0), + .o_features_1_0(daisy_chain_1_1_0), + .i_features_1_1(daisy_chain_0_1_1), + .o_features_1_1(daisy_chain_1_1_1), + .i_features_1_2(daisy_chain_0_1_2), + .o_features_1_2(daisy_chain_1_1_2), + .i_features_1_3(daisy_chain_0_1_3), + .o_features_1_3(daisy_chain_1_1_3), + .i_features_1_4(daisy_chain_0_1_4), + .o_features_1_4(daisy_chain_1_1_4), + .i_features_1_5(daisy_chain_0_1_5), + .o_features_1_5(daisy_chain_1_1_5), + .o_result_0(PE_output_1_0), + .o_result_1(PE_output_1_1), + .o_result_2(PE_output_1_2), + .o_result_3(PE_output_1_3), + .o_result_4(PE_output_1_4), + .o_result_5(PE_output_1_5), + .o_valid(PE_valid_1), + .o_next_reset(PE_next_reset_1), + .o_next_valid(PE_next_valid_1) +); + +processing_element processing_element_inst_2 ( + .clk(clk), + .i_reset(PE_next_reset_1), + .i_valid(PE_next_valid_1), + .i_features_0_0(daisy_chain_1_0_0), + .o_features_0_0(daisy_chain_2_0_0), + .i_features_0_1(daisy_chain_1_0_1), + .o_features_0_1(daisy_chain_2_0_1), + .i_features_0_2(daisy_chain_1_0_2), + .o_features_0_2(daisy_chain_2_0_2), + .i_features_0_3(daisy_chain_1_0_3), + .o_features_0_3(daisy_chain_2_0_3), + .i_features_0_4(daisy_chain_1_0_4), + .o_features_0_4(daisy_chain_2_0_4), + .i_features_0_5(daisy_chain_1_0_5), + .o_features_0_5(daisy_chain_2_0_5), + .i_features_1_0(daisy_chain_1_1_0), + .o_features_1_0(daisy_chain_2_1_0), + .i_features_1_1(daisy_chain_1_1_1), + .o_features_1_1(daisy_chain_2_1_1), + .i_features_1_2(daisy_chain_1_1_2), + .o_features_1_2(daisy_chain_2_1_2), + .i_features_1_3(daisy_chain_1_1_3), + .o_features_1_3(daisy_chain_2_1_3), + .i_features_1_4(daisy_chain_1_1_4), + .o_features_1_4(daisy_chain_2_1_4), + .i_features_1_5(daisy_chain_1_1_5), + .o_features_1_5(daisy_chain_2_1_5), + .o_result_0(PE_output_2_0), + .o_result_1(PE_output_2_1), + .o_result_2(PE_output_2_2), + .o_result_3(PE_output_2_3), + .o_result_4(PE_output_2_4), + .o_result_5(PE_output_2_5), + .o_valid(PE_valid_2), + .o_next_reset(PE_next_reset_2), + .o_next_valid(PE_next_valid_2) +); + +processing_element processing_element_inst_3 ( + .clk(clk), + .i_reset(PE_next_reset_2), + .i_valid(PE_next_valid_2), + .i_features_0_0(daisy_chain_2_0_0), + .o_features_0_0(daisy_chain_3_0_0), + .i_features_0_1(daisy_chain_2_0_1), + .o_features_0_1(daisy_chain_3_0_1), + .i_features_0_2(daisy_chain_2_0_2), + .o_features_0_2(daisy_chain_3_0_2), + .i_features_0_3(daisy_chain_2_0_3), + .o_features_0_3(daisy_chain_3_0_3), + .i_features_0_4(daisy_chain_2_0_4), + .o_features_0_4(daisy_chain_3_0_4), + .i_features_0_5(daisy_chain_2_0_5), + .o_features_0_5(daisy_chain_3_0_5), + .i_features_1_0(daisy_chain_2_1_0), + .o_features_1_0(daisy_chain_3_1_0), + .i_features_1_1(daisy_chain_2_1_1), + .o_features_1_1(daisy_chain_3_1_1), + .i_features_1_2(daisy_chain_2_1_2), + .o_features_1_2(daisy_chain_3_1_2), + .i_features_1_3(daisy_chain_2_1_3), + .o_features_1_3(daisy_chain_3_1_3), + .i_features_1_4(daisy_chain_2_1_4), + .o_features_1_4(daisy_chain_3_1_4), + .i_features_1_5(daisy_chain_2_1_5), + .o_features_1_5(daisy_chain_3_1_5), + .o_result_0(PE_output_3_0), + .o_result_1(PE_output_3_1), + .o_result_2(PE_output_3_2), + .o_result_3(PE_output_3_3), + .o_result_4(PE_output_3_4), + .o_result_5(PE_output_3_5), + .o_valid(PE_valid_3), + .o_next_reset(PE_next_reset_3), + .o_next_valid(PE_next_valid_3) +); + +processing_element processing_element_inst_4 ( + .clk(clk), + .i_reset(PE_next_reset_3), + .i_valid(PE_next_valid_3), + .i_features_0_0(daisy_chain_3_0_0), + .o_features_0_0(daisy_chain_4_0_0), + .i_features_0_1(daisy_chain_3_0_1), + .o_features_0_1(daisy_chain_4_0_1), + .i_features_0_2(daisy_chain_3_0_2), + .o_features_0_2(daisy_chain_4_0_2), + .i_features_0_3(daisy_chain_3_0_3), + .o_features_0_3(daisy_chain_4_0_3), + .i_features_0_4(daisy_chain_3_0_4), + .o_features_0_4(daisy_chain_4_0_4), + .i_features_0_5(daisy_chain_3_0_5), + .o_features_0_5(daisy_chain_4_0_5), + .i_features_1_0(daisy_chain_3_1_0), + .o_features_1_0(daisy_chain_4_1_0), + .i_features_1_1(daisy_chain_3_1_1), + .o_features_1_1(daisy_chain_4_1_1), + .i_features_1_2(daisy_chain_3_1_2), + .o_features_1_2(daisy_chain_4_1_2), + .i_features_1_3(daisy_chain_3_1_3), + .o_features_1_3(daisy_chain_4_1_3), + .i_features_1_4(daisy_chain_3_1_4), + .o_features_1_4(daisy_chain_4_1_4), + .i_features_1_5(daisy_chain_3_1_5), + .o_features_1_5(daisy_chain_4_1_5), + .o_result_0(PE_output_4_0), + .o_result_1(PE_output_4_1), + .o_result_2(PE_output_4_2), + .o_result_3(PE_output_4_3), + .o_result_4(PE_output_4_4), + .o_result_5(PE_output_4_5), + .o_valid(PE_valid_4), + .o_next_reset(PE_next_reset_4), + .o_next_valid(PE_next_valid_4) +); + +processing_element processing_element_inst_5 ( + .clk(clk), + .i_reset(PE_next_reset_4), + .i_valid(PE_next_valid_4), + .i_features_0_0(daisy_chain_4_0_0), + .o_features_0_0(daisy_chain_5_0_0), + .i_features_0_1(daisy_chain_4_0_1), + .o_features_0_1(daisy_chain_5_0_1), + .i_features_0_2(daisy_chain_4_0_2), + .o_features_0_2(daisy_chain_5_0_2), + .i_features_0_3(daisy_chain_4_0_3), + .o_features_0_3(daisy_chain_5_0_3), + .i_features_0_4(daisy_chain_4_0_4), + .o_features_0_4(daisy_chain_5_0_4), + .i_features_0_5(daisy_chain_4_0_5), + .o_features_0_5(daisy_chain_5_0_5), + .i_features_1_0(daisy_chain_4_1_0), + .o_features_1_0(daisy_chain_5_1_0), + .i_features_1_1(daisy_chain_4_1_1), + .o_features_1_1(daisy_chain_5_1_1), + .i_features_1_2(daisy_chain_4_1_2), + .o_features_1_2(daisy_chain_5_1_2), + .i_features_1_3(daisy_chain_4_1_3), + .o_features_1_3(daisy_chain_5_1_3), + .i_features_1_4(daisy_chain_4_1_4), + .o_features_1_4(daisy_chain_5_1_4), + .i_features_1_5(daisy_chain_4_1_5), + .o_features_1_5(daisy_chain_5_1_5), + .o_result_0(PE_output_5_0), + .o_result_1(PE_output_5_1), + .o_result_2(PE_output_5_2), + .o_result_3(PE_output_5_3), + .o_result_4(PE_output_5_4), + .o_result_5(PE_output_5_5), + .o_valid(PE_valid_5), + .o_next_reset(PE_next_reset_5), + .o_next_valid(PE_next_valid_5) +); + +processing_element processing_element_inst_6 ( + .clk(clk), + .i_reset(PE_next_reset_5), + .i_valid(PE_next_valid_5), + .i_features_0_0(daisy_chain_5_0_0), + .o_features_0_0(daisy_chain_6_0_0), + .i_features_0_1(daisy_chain_5_0_1), + .o_features_0_1(daisy_chain_6_0_1), + .i_features_0_2(daisy_chain_5_0_2), + .o_features_0_2(daisy_chain_6_0_2), + .i_features_0_3(daisy_chain_5_0_3), + .o_features_0_3(daisy_chain_6_0_3), + .i_features_0_4(daisy_chain_5_0_4), + .o_features_0_4(daisy_chain_6_0_4), + .i_features_0_5(daisy_chain_5_0_5), + .o_features_0_5(daisy_chain_6_0_5), + .i_features_1_0(daisy_chain_5_1_0), + .o_features_1_0(daisy_chain_6_1_0), + .i_features_1_1(daisy_chain_5_1_1), + .o_features_1_1(daisy_chain_6_1_1), + .i_features_1_2(daisy_chain_5_1_2), + .o_features_1_2(daisy_chain_6_1_2), + .i_features_1_3(daisy_chain_5_1_3), + .o_features_1_3(daisy_chain_6_1_3), + .i_features_1_4(daisy_chain_5_1_4), + .o_features_1_4(daisy_chain_6_1_4), + .i_features_1_5(daisy_chain_5_1_5), + .o_features_1_5(daisy_chain_6_1_5), + .o_result_0(PE_output_6_0), + .o_result_1(PE_output_6_1), + .o_result_2(PE_output_6_2), + .o_result_3(PE_output_6_3), + .o_result_4(PE_output_6_4), + .o_result_5(PE_output_6_5), + .o_valid(PE_valid_6), + .o_next_reset(PE_next_reset_6), + .o_next_valid(PE_next_valid_6) +); + +processing_element processing_element_inst_7 ( + .clk(clk), + .i_reset(PE_next_reset_6), + .i_valid(PE_next_valid_6), + .i_features_0_0(daisy_chain_6_0_0), + .o_features_0_0(daisy_chain_7_0_0), + .i_features_0_1(daisy_chain_6_0_1), + .o_features_0_1(daisy_chain_7_0_1), + .i_features_0_2(daisy_chain_6_0_2), + .o_features_0_2(daisy_chain_7_0_2), + .i_features_0_3(daisy_chain_6_0_3), + .o_features_0_3(daisy_chain_7_0_3), + .i_features_0_4(daisy_chain_6_0_4), + .o_features_0_4(daisy_chain_7_0_4), + .i_features_0_5(daisy_chain_6_0_5), + .o_features_0_5(daisy_chain_7_0_5), + .i_features_1_0(daisy_chain_6_1_0), + .o_features_1_0(daisy_chain_7_1_0), + .i_features_1_1(daisy_chain_6_1_1), + .o_features_1_1(daisy_chain_7_1_1), + .i_features_1_2(daisy_chain_6_1_2), + .o_features_1_2(daisy_chain_7_1_2), + .i_features_1_3(daisy_chain_6_1_3), + .o_features_1_3(daisy_chain_7_1_3), + .i_features_1_4(daisy_chain_6_1_4), + .o_features_1_4(daisy_chain_7_1_4), + .i_features_1_5(daisy_chain_6_1_5), + .o_features_1_5(daisy_chain_7_1_5), + .o_result_0(PE_output_7_0), + .o_result_1(PE_output_7_1), + .o_result_2(PE_output_7_2), + .o_result_3(PE_output_7_3), + .o_result_4(PE_output_7_4), + .o_result_5(PE_output_7_5), + .o_valid(PE_valid_7), + .o_next_reset(PE_next_reset_7), + .o_next_valid(PE_next_valid_7) +); + +processing_element processing_element_inst_8 ( + .clk(clk), + .i_reset(PE_next_reset_7), + .i_valid(PE_next_valid_7), + .i_features_0_0(daisy_chain_7_0_0), + .o_features_0_0(daisy_chain_8_0_0), + .i_features_0_1(daisy_chain_7_0_1), + .o_features_0_1(daisy_chain_8_0_1), + .i_features_0_2(daisy_chain_7_0_2), + .o_features_0_2(daisy_chain_8_0_2), + .i_features_0_3(daisy_chain_7_0_3), + .o_features_0_3(daisy_chain_8_0_3), + .i_features_0_4(daisy_chain_7_0_4), + .o_features_0_4(daisy_chain_8_0_4), + .i_features_0_5(daisy_chain_7_0_5), + .o_features_0_5(daisy_chain_8_0_5), + .i_features_1_0(daisy_chain_7_1_0), + .o_features_1_0(daisy_chain_8_1_0), + .i_features_1_1(daisy_chain_7_1_1), + .o_features_1_1(daisy_chain_8_1_1), + .i_features_1_2(daisy_chain_7_1_2), + .o_features_1_2(daisy_chain_8_1_2), + .i_features_1_3(daisy_chain_7_1_3), + .o_features_1_3(daisy_chain_8_1_3), + .i_features_1_4(daisy_chain_7_1_4), + .o_features_1_4(daisy_chain_8_1_4), + .i_features_1_5(daisy_chain_7_1_5), + .o_features_1_5(daisy_chain_8_1_5), + .o_result_0(PE_output_8_0), + .o_result_1(PE_output_8_1), + .o_result_2(PE_output_8_2), + .o_result_3(PE_output_8_3), + .o_result_4(PE_output_8_4), + .o_result_5(PE_output_8_5), + .o_valid(PE_valid_8), + .o_next_reset(PE_next_reset_8), + .o_next_valid(PE_next_valid_8) +); + +processing_element processing_element_inst_9 ( + .clk(clk), + .i_reset(PE_next_reset_8), + .i_valid(PE_next_valid_8), + .i_features_0_0(daisy_chain_8_0_0), + .o_features_0_0(daisy_chain_9_0_0), + .i_features_0_1(daisy_chain_8_0_1), + .o_features_0_1(daisy_chain_9_0_1), + .i_features_0_2(daisy_chain_8_0_2), + .o_features_0_2(daisy_chain_9_0_2), + .i_features_0_3(daisy_chain_8_0_3), + .o_features_0_3(daisy_chain_9_0_3), + .i_features_0_4(daisy_chain_8_0_4), + .o_features_0_4(daisy_chain_9_0_4), + .i_features_0_5(daisy_chain_8_0_5), + .o_features_0_5(daisy_chain_9_0_5), + .i_features_1_0(daisy_chain_8_1_0), + .o_features_1_0(daisy_chain_9_1_0), + .i_features_1_1(daisy_chain_8_1_1), + .o_features_1_1(daisy_chain_9_1_1), + .i_features_1_2(daisy_chain_8_1_2), + .o_features_1_2(daisy_chain_9_1_2), + .i_features_1_3(daisy_chain_8_1_3), + .o_features_1_3(daisy_chain_9_1_3), + .i_features_1_4(daisy_chain_8_1_4), + .o_features_1_4(daisy_chain_9_1_4), + .i_features_1_5(daisy_chain_8_1_5), + .o_features_1_5(daisy_chain_9_1_5), + .o_result_0(PE_output_9_0), + .o_result_1(PE_output_9_1), + .o_result_2(PE_output_9_2), + .o_result_3(PE_output_9_3), + .o_result_4(PE_output_9_4), + .o_result_5(PE_output_9_5), + .o_valid(PE_valid_9), + .o_next_reset(PE_next_reset_9), + .o_next_valid(PE_next_valid_9) +); + +processing_element processing_element_inst_10 ( + .clk(clk), + .i_reset(PE_next_reset_9), + .i_valid(PE_next_valid_9), + .i_features_0_0(daisy_chain_9_0_0), + .o_features_0_0(daisy_chain_10_0_0), + .i_features_0_1(daisy_chain_9_0_1), + .o_features_0_1(daisy_chain_10_0_1), + .i_features_0_2(daisy_chain_9_0_2), + .o_features_0_2(daisy_chain_10_0_2), + .i_features_0_3(daisy_chain_9_0_3), + .o_features_0_3(daisy_chain_10_0_3), + .i_features_0_4(daisy_chain_9_0_4), + .o_features_0_4(daisy_chain_10_0_4), + .i_features_0_5(daisy_chain_9_0_5), + .o_features_0_5(daisy_chain_10_0_5), + .i_features_1_0(daisy_chain_9_1_0), + .o_features_1_0(daisy_chain_10_1_0), + .i_features_1_1(daisy_chain_9_1_1), + .o_features_1_1(daisy_chain_10_1_1), + .i_features_1_2(daisy_chain_9_1_2), + .o_features_1_2(daisy_chain_10_1_2), + .i_features_1_3(daisy_chain_9_1_3), + .o_features_1_3(daisy_chain_10_1_3), + .i_features_1_4(daisy_chain_9_1_4), + .o_features_1_4(daisy_chain_10_1_4), + .i_features_1_5(daisy_chain_9_1_5), + .o_features_1_5(daisy_chain_10_1_5), + .o_result_0(PE_output_10_0), + .o_result_1(PE_output_10_1), + .o_result_2(PE_output_10_2), + .o_result_3(PE_output_10_3), + .o_result_4(PE_output_10_4), + .o_result_5(PE_output_10_5), + .o_valid(PE_valid_10), + .o_next_reset(PE_next_reset_10), + .o_next_valid(PE_next_valid_10) +); + +processing_element processing_element_inst_11 ( + .clk(clk), + .i_reset(PE_next_reset_10), + .i_valid(PE_next_valid_10), + .i_features_0_0(daisy_chain_10_0_0), + .o_features_0_0(daisy_chain_11_0_0), + .i_features_0_1(daisy_chain_10_0_1), + .o_features_0_1(daisy_chain_11_0_1), + .i_features_0_2(daisy_chain_10_0_2), + .o_features_0_2(daisy_chain_11_0_2), + .i_features_0_3(daisy_chain_10_0_3), + .o_features_0_3(daisy_chain_11_0_3), + .i_features_0_4(daisy_chain_10_0_4), + .o_features_0_4(daisy_chain_11_0_4), + .i_features_0_5(daisy_chain_10_0_5), + .o_features_0_5(daisy_chain_11_0_5), + .i_features_1_0(daisy_chain_10_1_0), + .o_features_1_0(daisy_chain_11_1_0), + .i_features_1_1(daisy_chain_10_1_1), + .o_features_1_1(daisy_chain_11_1_1), + .i_features_1_2(daisy_chain_10_1_2), + .o_features_1_2(daisy_chain_11_1_2), + .i_features_1_3(daisy_chain_10_1_3), + .o_features_1_3(daisy_chain_11_1_3), + .i_features_1_4(daisy_chain_10_1_4), + .o_features_1_4(daisy_chain_11_1_4), + .i_features_1_5(daisy_chain_10_1_5), + .o_features_1_5(daisy_chain_11_1_5), + .o_result_0(PE_output_11_0), + .o_result_1(PE_output_11_1), + .o_result_2(PE_output_11_2), + .o_result_3(PE_output_11_3), + .o_result_4(PE_output_11_4), + .o_result_5(PE_output_11_5), + .o_valid(PE_valid_11), + .o_next_reset(PE_next_reset_11), + .o_next_valid(PE_next_valid_11) +); + +inverse_winograd_0 inverse_winograd_0_inst ( + .clk(clk), + .i_valid(PE_valid_0), + .i_result_0(PE_output_0_0), + .i_result_1(PE_output_0_1), + .i_result_2(PE_output_0_2), + .i_result_3(PE_output_0_3), + .i_result_4(PE_output_0_4), + .i_result_5(PE_output_0_5), + .o_result_0(INV_output_0_0), + .o_result_1(INV_output_0_1), + .o_result_2(INV_output_0_2), + .o_result_3(INV_output_0_3), + .o_valid(INV_valid_0) +); + +inverse_winograd_1 inverse_winograd_1_inst ( + .clk(clk), + .i_valid(PE_valid_1), + .i_result_0(PE_output_1_0), + .i_result_1(PE_output_1_1), + .i_result_2(PE_output_1_2), + .i_result_3(PE_output_1_3), + .i_result_4(PE_output_1_4), + .i_result_5(PE_output_1_5), + .o_result_0(INV_output_1_0), + .o_result_1(INV_output_1_1), + .o_result_2(INV_output_1_2), + .o_result_3(INV_output_1_3), + .o_valid(INV_valid_1) +); + +inverse_winograd_2 inverse_winograd_2_inst ( + .clk(clk), + .i_valid(PE_valid_2), + .i_result_0(PE_output_2_0), + .i_result_1(PE_output_2_1), + .i_result_2(PE_output_2_2), + .i_result_3(PE_output_2_3), + .i_result_4(PE_output_2_4), + .i_result_5(PE_output_2_5), + .o_result_0(INV_output_2_0), + .o_result_1(INV_output_2_1), + .o_result_2(INV_output_2_2), + .o_result_3(INV_output_2_3), + .o_valid(INV_valid_2) +); + +inverse_winograd_3 inverse_winograd_3_inst ( + .clk(clk), + .i_valid(PE_valid_3), + .i_result_0(PE_output_3_0), + .i_result_1(PE_output_3_1), + .i_result_2(PE_output_3_2), + .i_result_3(PE_output_3_3), + .i_result_4(PE_output_3_4), + .i_result_5(PE_output_3_5), + .o_result_0(INV_output_3_0), + .o_result_1(INV_output_3_1), + .o_result_2(INV_output_3_2), + .o_result_3(INV_output_3_3), + .o_valid(INV_valid_3) +); + +inverse_winograd_4 inverse_winograd_4_inst ( + .clk(clk), + .i_valid(PE_valid_4), + .i_result_0(PE_output_4_0), + .i_result_1(PE_output_4_1), + .i_result_2(PE_output_4_2), + .i_result_3(PE_output_4_3), + .i_result_4(PE_output_4_4), + .i_result_5(PE_output_4_5), + .o_result_0(INV_output_4_0), + .o_result_1(INV_output_4_1), + .o_result_2(INV_output_4_2), + .o_result_3(INV_output_4_3), + .o_valid(INV_valid_4) +); + +inverse_winograd_5 inverse_winograd_5_inst ( + .clk(clk), + .i_valid(PE_valid_5), + .i_result_0(PE_output_5_0), + .i_result_1(PE_output_5_1), + .i_result_2(PE_output_5_2), + .i_result_3(PE_output_5_3), + .i_result_4(PE_output_5_4), + .i_result_5(PE_output_5_5), + .o_result_0(INV_output_5_0), + .o_result_1(INV_output_5_1), + .o_result_2(INV_output_5_2), + .o_result_3(INV_output_5_3), + .o_valid(INV_valid_5) +); + +inverse_winograd_6 inverse_winograd_6_inst ( + .clk(clk), + .i_valid(PE_valid_6), + .i_result_0(PE_output_6_0), + .i_result_1(PE_output_6_1), + .i_result_2(PE_output_6_2), + .i_result_3(PE_output_6_3), + .i_result_4(PE_output_6_4), + .i_result_5(PE_output_6_5), + .o_result_0(INV_output_6_0), + .o_result_1(INV_output_6_1), + .o_result_2(INV_output_6_2), + .o_result_3(INV_output_6_3), + .o_valid(INV_valid_6) +); + +inverse_winograd_7 inverse_winograd_7_inst ( + .clk(clk), + .i_valid(PE_valid_7), + .i_result_0(PE_output_7_0), + .i_result_1(PE_output_7_1), + .i_result_2(PE_output_7_2), + .i_result_3(PE_output_7_3), + .i_result_4(PE_output_7_4), + .i_result_5(PE_output_7_5), + .o_result_0(INV_output_7_0), + .o_result_1(INV_output_7_1), + .o_result_2(INV_output_7_2), + .o_result_3(INV_output_7_3), + .o_valid(INV_valid_7) +); + +inverse_winograd_8 inverse_winograd_8_inst ( + .clk(clk), + .i_valid(PE_valid_8), + .i_result_0(PE_output_8_0), + .i_result_1(PE_output_8_1), + .i_result_2(PE_output_8_2), + .i_result_3(PE_output_8_3), + .i_result_4(PE_output_8_4), + .i_result_5(PE_output_8_5), + .o_result_0(INV_output_8_0), + .o_result_1(INV_output_8_1), + .o_result_2(INV_output_8_2), + .o_result_3(INV_output_8_3), + .o_valid(INV_valid_8) +); + +inverse_winograd_9 inverse_winograd_9_inst ( + .clk(clk), + .i_valid(PE_valid_9), + .i_result_0(PE_output_9_0), + .i_result_1(PE_output_9_1), + .i_result_2(PE_output_9_2), + .i_result_3(PE_output_9_3), + .i_result_4(PE_output_9_4), + .i_result_5(PE_output_9_5), + .o_result_0(INV_output_9_0), + .o_result_1(INV_output_9_1), + .o_result_2(INV_output_9_2), + .o_result_3(INV_output_9_3), + .o_valid(INV_valid_9) +); + +inverse_winograd_10 inverse_winograd_10_inst ( + .clk(clk), + .i_valid(PE_valid_10), + .i_result_0(PE_output_10_0), + .i_result_1(PE_output_10_1), + .i_result_2(PE_output_10_2), + .i_result_3(PE_output_10_3), + .i_result_4(PE_output_10_4), + .i_result_5(PE_output_10_5), + .o_result_0(INV_output_10_0), + .o_result_1(INV_output_10_1), + .o_result_2(INV_output_10_2), + .o_result_3(INV_output_10_3), + .o_valid(INV_valid_10) +); + +inverse_winograd_11 inverse_winograd_11_inst ( + .clk(clk), + .i_valid(PE_valid_11), + .i_result_0(PE_output_11_0), + .i_result_1(PE_output_11_1), + .i_result_2(PE_output_11_2), + .i_result_3(PE_output_11_3), + .i_result_4(PE_output_11_4), + .i_result_5(PE_output_11_5), + .o_result_0(INV_output_11_0), + .o_result_1(INV_output_11_1), + .o_result_2(INV_output_11_2), + .o_result_3(INV_output_11_3), + .o_valid(INV_valid_11) +); + +pooling pooling_inst_0 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_0), + .i_result_0(INV_output_0_0), + .i_result_1(INV_output_0_1), + .i_result_2(INV_output_0_2), + .i_result_3(INV_output_0_3), + .o_result(POOL_output_0), + .o_valid(POOL_valid_0) +); + +pooling pooling_inst_1 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_1), + .i_result_0(INV_output_1_0), + .i_result_1(INV_output_1_1), + .i_result_2(INV_output_1_2), + .i_result_3(INV_output_1_3), + .o_result(POOL_output_1), + .o_valid(POOL_valid_1) +); + +pooling pooling_inst_2 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_2), + .i_result_0(INV_output_2_0), + .i_result_1(INV_output_2_1), + .i_result_2(INV_output_2_2), + .i_result_3(INV_output_2_3), + .o_result(POOL_output_2), + .o_valid(POOL_valid_2) +); + +pooling pooling_inst_3 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_3), + .i_result_0(INV_output_3_0), + .i_result_1(INV_output_3_1), + .i_result_2(INV_output_3_2), + .i_result_3(INV_output_3_3), + .o_result(POOL_output_3), + .o_valid(POOL_valid_3) +); + +pooling pooling_inst_4 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_4), + .i_result_0(INV_output_4_0), + .i_result_1(INV_output_4_1), + .i_result_2(INV_output_4_2), + .i_result_3(INV_output_4_3), + .o_result(POOL_output_4), + .o_valid(POOL_valid_4) +); + +pooling pooling_inst_5 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_5), + .i_result_0(INV_output_5_0), + .i_result_1(INV_output_5_1), + .i_result_2(INV_output_5_2), + .i_result_3(INV_output_5_3), + .o_result(POOL_output_5), + .o_valid(POOL_valid_5) +); + +pooling pooling_inst_6 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_6), + .i_result_0(INV_output_6_0), + .i_result_1(INV_output_6_1), + .i_result_2(INV_output_6_2), + .i_result_3(INV_output_6_3), + .o_result(POOL_output_6), + .o_valid(POOL_valid_6) +); + +pooling pooling_inst_7 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_7), + .i_result_0(INV_output_7_0), + .i_result_1(INV_output_7_1), + .i_result_2(INV_output_7_2), + .i_result_3(INV_output_7_3), + .o_result(POOL_output_7), + .o_valid(POOL_valid_7) +); + +pooling pooling_inst_8 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_8), + .i_result_0(INV_output_8_0), + .i_result_1(INV_output_8_1), + .i_result_2(INV_output_8_2), + .i_result_3(INV_output_8_3), + .o_result(POOL_output_8), + .o_valid(POOL_valid_8) +); + +pooling pooling_inst_9 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_9), + .i_result_0(INV_output_9_0), + .i_result_1(INV_output_9_1), + .i_result_2(INV_output_9_2), + .i_result_3(INV_output_9_3), + .o_result(POOL_output_9), + .o_valid(POOL_valid_9) +); + +pooling pooling_inst_10 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_10), + .i_result_0(INV_output_10_0), + .i_result_1(INV_output_10_1), + .i_result_2(INV_output_10_2), + .i_result_3(INV_output_10_3), + .o_result(POOL_output_10), + .o_valid(POOL_valid_10) +); + +pooling pooling_inst_11 ( + .clk(clk), + .i_reset(i_reset), + .i_valid(INV_valid_11), + .i_result_0(INV_output_11_0), + .i_result_1(INV_output_11_1), + .i_result_2(INV_output_11_2), + .i_result_3(INV_output_11_3), + .o_result(POOL_output_11), + .o_valid(POOL_valid_11) +); + +store_output store_output_inst ( + .clk(clk), + .i_valid(POOL_valid_0), + .i_reset(i_reset), + .i_result_0(POOL_output_0), + .i_result_1(POOL_output_1), + .i_result_2(POOL_output_2), + .i_result_3(POOL_output_3), + .i_result_4(POOL_output_4), + .i_result_5(POOL_output_5), + .i_result_6(POOL_output_6), + .i_result_7(POOL_output_7), + .i_result_8(POOL_output_8), + .i_result_9(POOL_output_9), + .i_result_10(POOL_output_10), + .i_result_11(POOL_output_11), + .o_store_0_0(STORE_output_0_0), + .o_store_0_1(STORE_output_0_1), + .o_store_1_0(STORE_output_1_0), + .o_store_1_1(STORE_output_1_1), + .o_store_2_0(STORE_output_2_0), + .o_store_2_1(STORE_output_2_1), + .o_store_3_0(STORE_output_3_0), + .o_store_3_1(STORE_output_3_1), + .o_store_4_0(STORE_output_4_0), + .o_store_4_1(STORE_output_4_1), + .o_store_5_0(STORE_output_5_0), + .o_store_5_1(STORE_output_5_1), + .o_wen_0(STORE_wen_0), + .o_wen_1(STORE_wen_1), + .o_wen_2(STORE_wen_2), + .o_wen_3(STORE_wen_3), + .o_wen_4(STORE_wen_4), + .o_wen_5(STORE_wen_5), + .o_addr(STORE_addr) +); + +signal_width_reducer signal_width_reducer_inst ( + .clk(clk), + .signals_0_0(dummy_out_0_0), + .reduced_signals_0_0(o_dummy_out_0_0), + .signals_0_1(dummy_out_0_1), + .reduced_signals_0_1(o_dummy_out_0_1), + .signals_1_0(dummy_out_1_0), + .reduced_signals_1_0(o_dummy_out_1_0), + .signals_1_1(dummy_out_1_1), + .reduced_signals_1_1(o_dummy_out_1_1), + .signals_2_0(dummy_out_2_0), + .reduced_signals_2_0(o_dummy_out_2_0), + .signals_2_1(dummy_out_2_1), + .reduced_signals_2_1(o_dummy_out_2_1), + .signals_3_0(dummy_out_3_0), + .reduced_signals_3_0(o_dummy_out_3_0), + .signals_3_1(dummy_out_3_1), + .reduced_signals_3_1(o_dummy_out_3_1), + .signals_4_0(dummy_out_4_0), + .reduced_signals_4_0(o_dummy_out_4_0), + .signals_4_1(dummy_out_4_1), + .reduced_signals_4_1(o_dummy_out_4_1), + .signals_5_0(dummy_out_5_0), + .reduced_signals_5_0(o_dummy_out_5_0), + .signals_5_1(dummy_out_5_1), + .reduced_signals_5_1(o_dummy_out_5_1), + .reset(i_reset) +); + +assign o_valid = POOL_valid_0; + +endmodule + +module inverse_winograd_1 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_15_0[29] == 1'b0) begin + result_wire_0 <= result_reg_15_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_15_1[29] == 1'b0) begin + result_wire_1 <= result_reg_15_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_15_2[29] == 1'b0) begin + result_wire_2 <= result_reg_15_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_15_3[29] == 1'b0) begin + result_wire_3 <= result_reg_15_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_15; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_adder_30_3 ( + input clock, + input [29:0] data0x, + input [29:0] data1x, + input [29:0] data2x, + input [29:0] data3x, + input [29:0] data4x, + input [29:0] data5x, + output [29:0] result +); + +reg [32:0] pipeline_0_0; +reg [32:0] pipeline_0_1; +reg [32:0] pipeline_0_2; +reg [32:0] pipeline_1_0; +reg [32:0] pipeline_1_1; +reg [32:0] pipeline_2_0; + +always @ (posedge clock) begin + pipeline_0_0 <= data0x + data1x; + pipeline_0_1 <= data2x + data3x; + pipeline_0_2 <= data4x + data5x; + pipeline_1_0 <= pipeline_0_0 + pipeline_0_1; + pipeline_1_1 <= pipeline_0_2; + pipeline_2_0 <= pipeline_1_0 + pipeline_1_1; +end + +assign result = pipeline_2_0; + +endmodule + +module inverse_winograd_0 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; +reg [29:0] result_reg_15_0; +reg [29:0] result_reg_15_1; +reg [29:0] result_reg_15_2; +reg [29:0] result_reg_15_3; +reg [29:0] result_reg_16_0; +reg [29:0] result_reg_16_1; +reg [29:0] result_reg_16_2; +reg [29:0] result_reg_16_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg out_valid_15; +reg out_valid_16; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; + out_valid_15 <= out_valid_14; + result_reg_15_0 <= result_reg_14_0; + result_reg_15_1 <= result_reg_14_1; + result_reg_15_2 <= result_reg_14_2; + result_reg_15_3 <= result_reg_14_3; + out_valid_16 <= out_valid_15; + result_reg_16_0 <= result_reg_15_0; + result_reg_16_1 <= result_reg_15_1; + result_reg_16_2 <= result_reg_15_2; + result_reg_16_3 <= result_reg_15_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_16_0[29] == 1'b0) begin + result_wire_0 <= result_reg_16_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_16_1[29] == 1'b0) begin + result_wire_1 <= result_reg_16_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_16_2[29] == 1'b0) begin + result_wire_2 <= result_reg_16_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_16_3[29] == 1'b0) begin + result_wire_3 <= result_reg_16_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_16; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_3 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_13_0[29] == 1'b0) begin + result_wire_0 <= result_reg_13_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_13_1[29] == 1'b0) begin + result_wire_1 <= result_reg_13_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_13_2[29] == 1'b0) begin + result_wire_2 <= result_reg_13_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_13_3[29] == 1'b0) begin + result_wire_3 <= result_reg_13_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_13; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_2 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; +reg [29:0] result_reg_13_0; +reg [29:0] result_reg_13_1; +reg [29:0] result_reg_13_2; +reg [29:0] result_reg_13_3; +reg [29:0] result_reg_14_0; +reg [29:0] result_reg_14_1; +reg [29:0] result_reg_14_2; +reg [29:0] result_reg_14_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg out_valid_13; +reg out_valid_14; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; + out_valid_13 <= out_valid_12; + result_reg_13_0 <= result_reg_12_0; + result_reg_13_1 <= result_reg_12_1; + result_reg_13_2 <= result_reg_12_2; + result_reg_13_3 <= result_reg_12_3; + out_valid_14 <= out_valid_13; + result_reg_14_0 <= result_reg_13_0; + result_reg_14_1 <= result_reg_13_1; + result_reg_14_2 <= result_reg_13_2; + result_reg_14_3 <= result_reg_13_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_14_0[29] == 1'b0) begin + result_wire_0 <= result_reg_14_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_14_1[29] == 1'b0) begin + result_wire_1 <= result_reg_14_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_14_2[29] == 1'b0) begin + result_wire_2 <= result_reg_14_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_14_3[29] == 1'b0) begin + result_wire_3 <= result_reg_14_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_14; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_5 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_11_0[29] == 1'b0) begin + result_wire_0 <= result_reg_11_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_11_1[29] == 1'b0) begin + result_wire_1 <= result_reg_11_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_11_2[29] == 1'b0) begin + result_wire_2 <= result_reg_11_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_11_3[29] == 1'b0) begin + result_wire_3 <= result_reg_11_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_11; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_4 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; +reg [29:0] result_reg_11_0; +reg [29:0] result_reg_11_1; +reg [29:0] result_reg_11_2; +reg [29:0] result_reg_11_3; +reg [29:0] result_reg_12_0; +reg [29:0] result_reg_12_1; +reg [29:0] result_reg_12_2; +reg [29:0] result_reg_12_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg out_valid_11; +reg out_valid_12; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; + out_valid_11 <= out_valid_10; + result_reg_11_0 <= result_reg_10_0; + result_reg_11_1 <= result_reg_10_1; + result_reg_11_2 <= result_reg_10_2; + result_reg_11_3 <= result_reg_10_3; + out_valid_12 <= out_valid_11; + result_reg_12_0 <= result_reg_11_0; + result_reg_12_1 <= result_reg_11_1; + result_reg_12_2 <= result_reg_11_2; + result_reg_12_3 <= result_reg_11_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_12_0[29] == 1'b0) begin + result_wire_0 <= result_reg_12_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_12_1[29] == 1'b0) begin + result_wire_1 <= result_reg_12_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_12_2[29] == 1'b0) begin + result_wire_2 <= result_reg_12_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_12_3[29] == 1'b0) begin + result_wire_3 <= result_reg_12_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_12; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_7 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_9_0[29] == 1'b0) begin + result_wire_0 <= result_reg_9_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_9_1[29] == 1'b0) begin + result_wire_1 <= result_reg_9_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_9_2[29] == 1'b0) begin + result_wire_2 <= result_reg_9_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_9_3[29] == 1'b0) begin + result_wire_3 <= result_reg_9_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_9; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_6 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; +reg [29:0] result_reg_9_0; +reg [29:0] result_reg_9_1; +reg [29:0] result_reg_9_2; +reg [29:0] result_reg_9_3; +reg [29:0] result_reg_10_0; +reg [29:0] result_reg_10_1; +reg [29:0] result_reg_10_2; +reg [29:0] result_reg_10_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg out_valid_9; +reg out_valid_10; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; + out_valid_9 <= out_valid_8; + result_reg_9_0 <= result_reg_8_0; + result_reg_9_1 <= result_reg_8_1; + result_reg_9_2 <= result_reg_8_2; + result_reg_9_3 <= result_reg_8_3; + out_valid_10 <= out_valid_9; + result_reg_10_0 <= result_reg_9_0; + result_reg_10_1 <= result_reg_9_1; + result_reg_10_2 <= result_reg_9_2; + result_reg_10_3 <= result_reg_9_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_10_0[29] == 1'b0) begin + result_wire_0 <= result_reg_10_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_10_1[29] == 1'b0) begin + result_wire_1 <= result_reg_10_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_10_2[29] == 1'b0) begin + result_wire_2 <= result_reg_10_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_10_3[29] == 1'b0) begin + result_wire_3 <= result_reg_10_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_10; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_9 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_7_0[29] == 1'b0) begin + result_wire_0 <= result_reg_7_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_7_1[29] == 1'b0) begin + result_wire_1 <= result_reg_7_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_7_2[29] == 1'b0) begin + result_wire_2 <= result_reg_7_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_7_3[29] == 1'b0) begin + result_wire_3 <= result_reg_7_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_7; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_8 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; +reg [29:0] result_reg_7_0; +reg [29:0] result_reg_7_1; +reg [29:0] result_reg_7_2; +reg [29:0] result_reg_7_3; +reg [29:0] result_reg_8_0; +reg [29:0] result_reg_8_1; +reg [29:0] result_reg_8_2; +reg [29:0] result_reg_8_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg out_valid_7; +reg out_valid_8; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; + out_valid_7 <= out_valid_6; + result_reg_7_0 <= result_reg_6_0; + result_reg_7_1 <= result_reg_6_1; + result_reg_7_2 <= result_reg_6_2; + result_reg_7_3 <= result_reg_6_3; + out_valid_8 <= out_valid_7; + result_reg_8_0 <= result_reg_7_0; + result_reg_8_1 <= result_reg_7_1; + result_reg_8_2 <= result_reg_7_2; + result_reg_8_3 <= result_reg_7_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_8_0[29] == 1'b0) begin + result_wire_0 <= result_reg_8_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_8_1[29] == 1'b0) begin + result_wire_1 <= result_reg_8_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_8_2[29] == 1'b0) begin + result_wire_2 <= result_reg_8_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_8_3[29] == 1'b0) begin + result_wire_3 <= result_reg_8_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_8; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_11 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_5_0[29] == 1'b0) begin + result_wire_0 <= result_reg_5_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_5_1[29] == 1'b0) begin + result_wire_1 <= result_reg_5_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_5_2[29] == 1'b0) begin + result_wire_2 <= result_reg_5_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_5_3[29] == 1'b0) begin + result_wire_3 <= result_reg_5_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_5; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module inverse_winograd_10 ( + input clk, + input i_valid, + input [29:0] i_result_0, + input [29:0] i_result_1, + input [29:0] i_result_2, + input [29:0] i_result_3, + input [29:0] i_result_4, + input [29:0] i_result_5, + output [15:0] o_result_0, + output [15:0] o_result_1, + output [15:0] o_result_2, + output [15:0] o_result_3, + output o_valid +); + +reg [2:0] state, next_state; +wire [29:0] adders_res_0_0; +reg [29:0] serialize_reg_0_0; +reg [29:0] adders_res_0_1; +reg [29:0] serialize_reg_0_1; +reg [29:0] adders_res_0_2; +reg [29:0] serialize_reg_0_2; +reg [29:0] adders_res_0_3; +reg [29:0] serialize_reg_0_3; +reg [29:0] adders_res_0_4; +reg [29:0] serialize_reg_0_4; +reg [29:0] adders_res_0_5; +reg [29:0] serialize_reg_0_5; +wire [29:0] adders_res_1_0; +reg [29:0] serialize_reg_1_0; +reg [29:0] adders_res_1_1; +reg [29:0] serialize_reg_1_1; +reg [29:0] adders_res_1_2; +reg [29:0] serialize_reg_1_2; +reg [29:0] adders_res_1_3; +reg [29:0] serialize_reg_1_3; +reg [29:0] adders_res_1_4; +reg [29:0] serialize_reg_1_4; +reg [29:0] adders_res_1_5; +reg [29:0] serialize_reg_1_5; +wire [29:0] adders_res_2_0; +reg [29:0] serialize_reg_2_0; +reg [29:0] adders_res_2_1; +reg [29:0] serialize_reg_2_1; +reg [29:0] adders_res_2_2; +reg [29:0] serialize_reg_2_2; +reg [29:0] adders_res_2_3; +reg [29:0] serialize_reg_2_3; +reg [29:0] adders_res_2_4; +reg [29:0] serialize_reg_2_4; +reg [29:0] adders_res_2_5; +reg [29:0] serialize_reg_2_5; +wire [29:0] adders_res_3_0; +reg [29:0] serialize_reg_3_0; +reg [29:0] adders_res_3_1; +reg [29:0] serialize_reg_3_1; +reg [29:0] adders_res_3_2; +reg [29:0] serialize_reg_3_2; +reg [29:0] adders_res_3_3; +reg [29:0] serialize_reg_3_3; +reg [29:0] adders_res_3_4; +reg [29:0] serialize_reg_3_4; +reg [29:0] adders_res_3_5; +reg [29:0] serialize_reg_3_5; + +wire [29:0] result_reg_0_0; +wire [29:0] result_reg_0_1; +wire [29:0] result_reg_0_2; +wire [29:0] result_reg_0_3; +reg [29:0] result_reg_1_0; +reg [29:0] result_reg_1_1; +reg [29:0] result_reg_1_2; +reg [29:0] result_reg_1_3; +reg [29:0] result_reg_2_0; +reg [29:0] result_reg_2_1; +reg [29:0] result_reg_2_2; +reg [29:0] result_reg_2_3; +reg [29:0] result_reg_3_0; +reg [29:0] result_reg_3_1; +reg [29:0] result_reg_3_2; +reg [29:0] result_reg_3_3; +reg [29:0] result_reg_4_0; +reg [29:0] result_reg_4_1; +reg [29:0] result_reg_4_2; +reg [29:0] result_reg_4_3; +reg [29:0] result_reg_5_0; +reg [29:0] result_reg_5_1; +reg [29:0] result_reg_5_2; +reg [29:0] result_reg_5_3; +reg [29:0] result_reg_6_0; +reg [29:0] result_reg_6_1; +reg [29:0] result_reg_6_2; +reg [29:0] result_reg_6_3; + +reg out_valid_0; +reg out_valid_1; +reg out_valid_2; +reg out_valid_3; +reg out_valid_4; +reg out_valid_5; +reg out_valid_6; +reg [1:0] serialize_count; + +always @ (posedge clk) begin + out_valid_1 <= out_valid_0; + result_reg_1_0 <= result_reg_0_0; + result_reg_1_1 <= result_reg_0_1; + result_reg_1_2 <= result_reg_0_2; + result_reg_1_3 <= result_reg_0_3; + out_valid_2 <= out_valid_1; + result_reg_2_0 <= result_reg_1_0; + result_reg_2_1 <= result_reg_1_1; + result_reg_2_2 <= result_reg_1_2; + result_reg_2_3 <= result_reg_1_3; + out_valid_3 <= out_valid_2; + result_reg_3_0 <= result_reg_2_0; + result_reg_3_1 <= result_reg_2_1; + result_reg_3_2 <= result_reg_2_2; + result_reg_3_3 <= result_reg_2_3; + out_valid_4 <= out_valid_3; + result_reg_4_0 <= result_reg_3_0; + result_reg_4_1 <= result_reg_3_1; + result_reg_4_2 <= result_reg_3_2; + result_reg_4_3 <= result_reg_3_3; + out_valid_5 <= out_valid_4; + result_reg_5_0 <= result_reg_4_0; + result_reg_5_1 <= result_reg_4_1; + result_reg_5_2 <= result_reg_4_2; + result_reg_5_3 <= result_reg_4_3; + out_valid_6 <= out_valid_5; + result_reg_6_0 <= result_reg_5_0; + result_reg_6_1 <= result_reg_5_1; + result_reg_6_2 <= result_reg_5_2; + result_reg_6_3 <= result_reg_5_3; +end + +// FSM Combinational Logic +always @ (state or i_valid or serialize_count) begin + if(state == 3'b000) begin + if(i_valid == 1'b1)begin + next_state = 3'b010; + end else begin + next_state = 3'b000; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b0) begin + next_state = 3'b100; + end else begin + next_state = 3'b010; + end + end else if (state == 3'b100) begin + if(serialize_count == 3)begin + next_state = 3'b000; + end else begin + next_state = 3'b100; + end + end else begin + next_state = 3'b000; + end +end + +// FSM Sequential Logic +always @ (posedge clk) begin + if (state == 3'b000) begin + serialize_count <= 0; + out_valid_0 <= 0; + if (i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end + end else if (state == 3'b010) begin + if(i_valid == 1'b1) begin + adders_res_0_1 <= adders_res_0_0; + adders_res_1_1 <= adders_res_1_0; + adders_res_2_1 <= adders_res_2_0; + adders_res_3_1 <= adders_res_3_0; + adders_res_0_2 <= adders_res_0_1; + adders_res_1_2 <= adders_res_1_1; + adders_res_2_2 <= adders_res_2_1; + adders_res_3_2 <= adders_res_3_1; + adders_res_0_3 <= adders_res_0_2; + adders_res_1_3 <= adders_res_1_2; + adders_res_2_3 <= adders_res_2_2; + adders_res_3_3 <= adders_res_3_2; + adders_res_0_4 <= adders_res_0_3; + adders_res_1_4 <= adders_res_1_3; + adders_res_2_4 <= adders_res_2_3; + adders_res_3_4 <= adders_res_3_3; + adders_res_0_5 <= adders_res_0_4; + adders_res_1_5 <= adders_res_1_4; + adders_res_2_5 <= adders_res_2_4; + adders_res_3_5 <= adders_res_3_4; + end else begin + serialize_reg_0_0 <= adders_res_0_0; + serialize_reg_1_0 <= adders_res_1_0; + serialize_reg_2_0 <= adders_res_2_0; + serialize_reg_3_0 <= adders_res_3_0; + serialize_reg_0_1 <= adders_res_0_1; + serialize_reg_1_1 <= adders_res_1_1; + serialize_reg_2_1 <= adders_res_2_1; + serialize_reg_3_1 <= adders_res_3_1; + serialize_reg_0_2 <= adders_res_0_2; + serialize_reg_1_2 <= adders_res_1_2; + serialize_reg_2_2 <= adders_res_2_2; + serialize_reg_3_2 <= adders_res_3_2; + serialize_reg_0_3 <= adders_res_0_3; + serialize_reg_1_3 <= adders_res_1_3; + serialize_reg_2_3 <= adders_res_2_3; + serialize_reg_3_3 <= adders_res_3_3; + serialize_reg_0_4 <= adders_res_0_4; + serialize_reg_1_4 <= adders_res_1_4; + serialize_reg_2_4 <= adders_res_2_4; + serialize_reg_3_4 <= adders_res_3_4; + serialize_reg_0_5 <= adders_res_0_5; + serialize_reg_1_5 <= adders_res_1_5; + serialize_reg_2_5 <= adders_res_2_5; + serialize_reg_3_5 <= adders_res_3_5; + end + end else if (state == 3'b100) begin + if (serialize_count < 3) begin + serialize_reg_0_0 <= serialize_reg_1_0; + serialize_reg_0_1 <= serialize_reg_1_1; + serialize_reg_0_2 <= serialize_reg_1_2; + serialize_reg_0_3 <= serialize_reg_1_3; + serialize_reg_0_4 <= serialize_reg_1_4; + serialize_reg_0_5 <= serialize_reg_1_5; + serialize_reg_1_0 <= serialize_reg_2_0; + serialize_reg_1_1 <= serialize_reg_2_1; + serialize_reg_1_2 <= serialize_reg_2_2; + serialize_reg_1_3 <= serialize_reg_2_3; + serialize_reg_1_4 <= serialize_reg_2_4; + serialize_reg_1_5 <= serialize_reg_2_5; + serialize_reg_2_0 <= serialize_reg_3_0; + serialize_reg_2_1 <= serialize_reg_3_1; + serialize_reg_2_2 <= serialize_reg_3_2; + serialize_reg_2_3 <= serialize_reg_3_3; + serialize_reg_2_4 <= serialize_reg_3_4; + serialize_reg_2_5 <= serialize_reg_3_5; + serialize_count <= serialize_count + 1'b1; + out_valid_0 <= 1; + end + end + state <= next_state; +end + +// AT Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA0 ( + .data0x(i_result_0), + .data1x(i_result_1), + .data2x(i_result_2), + .data3x(i_result_3), + .data4x(i_result_4), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(adders_res_0_0) +); +wire [29:0] f1, f2; +assign f1 = -i_result_2; +assign f2 = -{i_result_4[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA1 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f1), + .data3x({i_result_3[28:0], 1'b0}), + .data4x(f2), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_1_0) +); +wire [29:0] f3, f4; +assign f3 = -i_result_2; +assign f4 = -{i_result_4[27:0], 2'b00}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA2 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f3), + .data3x({i_result_3[27:0], 2'b00}), + .data4x(f4), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(adders_res_2_0) +); +wire [29:0] f5, f6; +assign f5 = -i_result_2; +assign f6 = -{i_result_4[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWA3 ( + .data0x({ (30){1'b0} }), + .data1x(i_result_1), + .data2x(f5), + .data3x({i_result_3[26:0], 3'b000}), + .data4x(f6), + .data5x(i_result_5), + .clock(clk), + .result(adders_res_3_0) +); + +// A Adders +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT0 ( + .data0x(serialize_reg_0_5), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x(serialize_reg_0_2), + .data4x(serialize_reg_0_1), + .data5x({ (30) {1'b0} }), + .clock(clk), + .result(result_reg_0_0) +); +wire [29:0] f7, f8; +assign f7 = -serialize_reg_0_3; +assign f8 = -{serialize_reg_0_1[28:0], 1'b0}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT1 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f7), + .data3x({serialize_reg_0_2[28:0], 1'b0}), + .data4x(f8), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_1) +); +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT2 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(serialize_reg_0_3), + .data3x({serialize_reg_0_2[27:0], 2'b00}), + .data4x({serialize_reg_0_1[27:0], 2'b00}), + .data5x({ (30){1'b0} }), + .clock(clk), + .result(result_reg_0_2) +); +wire [29:0] f9, f10; +assign f9 = -serialize_reg_0_3; +assign f10 = -{serialize_reg_0_1[26:0], 3'b000}; +inverse_winograd_adder_30_3 inverse_winograd_adder_30_3_inst_IWAT3 ( + .data0x({ (30){1'b0} }), + .data1x(serialize_reg_0_4), + .data2x(f9), + .data3x({serialize_reg_0_2[26:0], 3'b000}), + .data4x(f10), + .data5x(serialize_reg_0_0), + .clock(clk), + .result(result_reg_0_3) +); + +reg [15:0] result_wire_0; +reg [15:0] result_wire_1; +reg [15:0] result_wire_2; +reg [15:0] result_wire_3; + +always @ (*) begin + if(result_reg_6_0[29] == 1'b0) begin + result_wire_0 <= result_reg_6_0[23:8]; + end else begin + result_wire_0 <= { (16){1'b0} }; + end + if(result_reg_6_1[29] == 1'b0) begin + result_wire_1 <= result_reg_6_1[23:8]; + end else begin + result_wire_1 <= { (16){1'b0} }; + end + if(result_reg_6_2[29] == 1'b0) begin + result_wire_2 <= result_reg_6_2[23:8]; + end else begin + result_wire_2 <= { (16){1'b0} }; + end + if(result_reg_6_3[29] == 1'b0) begin + result_wire_3 <= result_reg_6_3[23:8]; + end else begin + result_wire_3 <= { (16){1'b0} }; + end +end + +assign o_valid = out_valid_6; +assign o_result_0 = result_wire_0; +assign o_result_1 = result_wire_1; +assign o_result_2 = result_wire_2; +assign o_result_3 = result_wire_3; + +endmodule + +module winograd_transform_1 ( + input clk, + input i_valid, + input [15:0] i_result_0_0, + input [15:0] i_result_0_1, + input [15:0] i_result_1_0, + input [15:0] i_result_1_1, + input [15:0] i_result_2_0, + input [15:0] i_result_2_1, + input [15:0] i_result_3_0, + input [15:0] i_result_3_1, + input [15:0] i_result_4_0, + input [15:0] i_result_4_1, + input [15:0] i_result_5_0, + input [15:0] i_result_5_1, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output [15:0] o_feature_2, + output [15:0] o_feature_3, + output [15:0] o_feature_4, + output [15:0] o_feature_5, + output o_valid +); + +reg [15:0] input_buffer_0_0; +reg [19:0] output_buffer_0_0; +wire [19:0] rslt_buffer_0_0; +reg [15:0] input_buffer_0_1; +reg [19:0] output_buffer_0_1; +wire [19:0] rslt_buffer_0_1; +reg [15:0] input_buffer_0_2; +reg [19:0] output_buffer_0_2; +wire [19:0] rslt_buffer_0_2; +reg [15:0] input_buffer_0_3; +reg [19:0] output_buffer_0_3; +wire [19:0] rslt_buffer_0_3; +reg [15:0] input_buffer_0_4; +reg [19:0] output_buffer_0_4; +wire [19:0] rslt_buffer_0_4; +reg [15:0] input_buffer_0_5; +reg [19:0] output_buffer_0_5; +wire [19:0] rslt_buffer_0_5; +reg [15:0] input_buffer_1_0; +reg [19:0] output_buffer_1_0; +wire [19:0] rslt_buffer_1_0; +reg [15:0] input_buffer_1_1; +reg [19:0] output_buffer_1_1; +wire [19:0] rslt_buffer_1_1; +reg [15:0] input_buffer_1_2; +reg [19:0] output_buffer_1_2; +wire [19:0] rslt_buffer_1_2; +reg [15:0] input_buffer_1_3; +reg [19:0] output_buffer_1_3; +wire [19:0] rslt_buffer_1_3; +reg [15:0] input_buffer_1_4; +reg [19:0] output_buffer_1_4; +wire [19:0] rslt_buffer_1_4; +reg [15:0] input_buffer_1_5; +reg [19:0] output_buffer_1_5; +wire [19:0] rslt_buffer_1_5; +reg [15:0] input_buffer_2_0; +reg [19:0] output_buffer_2_0; +wire [19:0] rslt_buffer_2_0; +reg [15:0] input_buffer_2_1; +reg [19:0] output_buffer_2_1; +wire [19:0] rslt_buffer_2_1; +reg [15:0] input_buffer_2_2; +reg [19:0] output_buffer_2_2; +wire [19:0] rslt_buffer_2_2; +reg [15:0] input_buffer_2_3; +reg [19:0] output_buffer_2_3; +wire [19:0] rslt_buffer_2_3; +reg [15:0] input_buffer_2_4; +reg [19:0] output_buffer_2_4; +wire [19:0] rslt_buffer_2_4; +reg [15:0] input_buffer_2_5; +reg [19:0] output_buffer_2_5; +wire [19:0] rslt_buffer_2_5; +reg [15:0] input_buffer_3_0; +reg [19:0] output_buffer_3_0; +wire [19:0] rslt_buffer_3_0; +reg [15:0] input_buffer_3_1; +reg [19:0] output_buffer_3_1; +wire [19:0] rslt_buffer_3_1; +reg [15:0] input_buffer_3_2; +reg [19:0] output_buffer_3_2; +wire [19:0] rslt_buffer_3_2; +reg [15:0] input_buffer_3_3; +reg [19:0] output_buffer_3_3; +wire [19:0] rslt_buffer_3_3; +reg [15:0] input_buffer_3_4; +reg [19:0] output_buffer_3_4; +wire [19:0] rslt_buffer_3_4; +reg [15:0] input_buffer_3_5; +reg [19:0] output_buffer_3_5; +wire [19:0] rslt_buffer_3_5; +reg [15:0] input_buffer_4_0; +reg [19:0] output_buffer_4_0; +wire [19:0] rslt_buffer_4_0; +reg [15:0] input_buffer_4_1; +reg [19:0] output_buffer_4_1; +wire [19:0] rslt_buffer_4_1; +reg [15:0] input_buffer_4_2; +reg [19:0] output_buffer_4_2; +wire [19:0] rslt_buffer_4_2; +reg [15:0] input_buffer_4_3; +reg [19:0] output_buffer_4_3; +wire [19:0] rslt_buffer_4_3; +reg [15:0] input_buffer_4_4; +reg [19:0] output_buffer_4_4; +wire [19:0] rslt_buffer_4_4; +reg [15:0] input_buffer_4_5; +reg [19:0] output_buffer_4_5; +wire [19:0] rslt_buffer_4_5; +reg [15:0] input_buffer_5_0; +reg [19:0] output_buffer_5_0; +wire [19:0] rslt_buffer_5_0; +reg [15:0] input_buffer_5_1; +reg [19:0] output_buffer_5_1; +wire [19:0] rslt_buffer_5_1; +reg [15:0] input_buffer_5_2; +reg [19:0] output_buffer_5_2; +wire [19:0] rslt_buffer_5_2; +reg [15:0] input_buffer_5_3; +reg [19:0] output_buffer_5_3; +wire [19:0] rslt_buffer_5_3; +reg [15:0] input_buffer_5_4; +reg [19:0] output_buffer_5_4; +wire [19:0] rslt_buffer_5_4; +reg [15:0] input_buffer_5_5; +reg [19:0] output_buffer_5_5; +wire [19:0] rslt_buffer_5_5; +reg calculate, calculate_1, calculate_2, calculate_3; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg valid_12; +reg [2:0] input_buffer_count; +wire [15:0] dsp_out_1_0; +wire [15:0] dsp_out_1_1; +wire [15:0] dsp_out_1_2; +wire [15:0] dsp_out_1_3; +wire [15:0] dsp_out_1_4; +wire [15:0] dsp_out_1_5; +wire [15:0] dsp_out_1_6; +wire [15:0] dsp_out_1_7; +wire [15:0] dsp_out_1_8; +wire [15:0] dsp_out_1_9; +wire [15:0] dsp_out_1_10; +wire [15:0] dsp_out_1_11; +wire [15:0] dsp_out_2_0; +wire [15:0] dsp_out_2_1; +wire [15:0] dsp_out_2_2; +wire [15:0] dsp_out_2_3; +wire [15:0] dsp_out_2_4; +wire [15:0] dsp_out_2_5; +wire [15:0] dsp_out_2_6; +wire [15:0] dsp_out_2_7; +wire [15:0] dsp_out_3_0; +wire [15:0] dsp_out_3_1; +wire [15:0] dsp_out_3_2; +wire [15:0] dsp_out_3_3; +wire [15:0] dsp_out_3_4; +wire [15:0] dsp_out_3_5; +wire [15:0] dsp_out_3_6; +wire [15:0] dsp_out_3_7; +wire [15:0] dsp_out_4_0; +wire [15:0] dsp_out_4_1; +wire [15:0] dsp_out_4_2; +wire [15:0] dsp_out_4_3; +wire [15:0] dsp_out_4_4; +wire [15:0] dsp_out_4_5; +wire [15:0] dsp_out_4_6; +wire [15:0] dsp_out_4_7; +wire [15:0] dsp_out_5_0; +wire [15:0] dsp_out_5_1; +wire [15:0] dsp_out_5_2; +wire [15:0] dsp_out_5_3; +wire [15:0] dsp_out_5_4; +wire [15:0] dsp_out_5_5; +wire [15:0] dsp_out_5_6; +wire [15:0] dsp_out_5_7; +wire [15:0] dsp_out_6_0; +wire [15:0] dsp_out_6_1; +wire [15:0] dsp_out_6_2; +wire [15:0] dsp_out_6_3; +wire [15:0] dsp_out_6_4; +wire [15:0] dsp_out_6_5; +wire [15:0] dsp_out_6_6; +wire [15:0] dsp_out_6_7; +wire [15:0] dsp_out_6_8; +wire [15:0] dsp_out_6_9; +wire [15:0] dsp_out_6_10; +wire [15:0] dsp_out_6_11; +reg [15:0] feature_reg_0_0_0; +reg [15:0] feature_reg_0_0_1; +reg [15:0] feature_reg_0_1_0; +reg [15:0] feature_reg_0_1_1; +reg [15:0] feature_reg_0_2_0; +reg [15:0] feature_reg_0_2_1; +reg [15:0] feature_reg_0_3_0; +reg [15:0] feature_reg_0_3_1; +reg [15:0] feature_reg_0_4_0; +reg [15:0] feature_reg_0_4_1; +reg [15:0] feature_reg_0_5_0; +reg [15:0] feature_reg_0_5_1; +reg [15:0] feature_reg_1_0_0; +reg [15:0] feature_reg_1_0_1; +reg [15:0] feature_reg_1_1_0; +reg [15:0] feature_reg_1_1_1; +reg [15:0] feature_reg_1_2_0; +reg [15:0] feature_reg_1_2_1; +reg [15:0] feature_reg_1_3_0; +reg [15:0] feature_reg_1_3_1; +reg [15:0] feature_reg_1_4_0; +reg [15:0] feature_reg_1_4_1; +reg [15:0] feature_reg_1_5_0; +reg [15:0] feature_reg_1_5_1; +reg [15:0] feature_reg_2_0_0; +reg [15:0] feature_reg_2_0_1; +reg [15:0] feature_reg_2_1_0; +reg [15:0] feature_reg_2_1_1; +reg [15:0] feature_reg_2_2_0; +reg [15:0] feature_reg_2_2_1; +reg [15:0] feature_reg_2_3_0; +reg [15:0] feature_reg_2_3_1; +reg [15:0] feature_reg_2_4_0; +reg [15:0] feature_reg_2_4_1; +reg [15:0] feature_reg_2_5_0; +reg [15:0] feature_reg_2_5_1; +reg [15:0] feature_reg_3_0_0; +reg [15:0] feature_reg_3_0_1; +reg [15:0] feature_reg_3_1_0; +reg [15:0] feature_reg_3_1_1; +reg [15:0] feature_reg_3_2_0; +reg [15:0] feature_reg_3_2_1; +reg [15:0] feature_reg_3_3_0; +reg [15:0] feature_reg_3_3_1; +reg [15:0] feature_reg_3_4_0; +reg [15:0] feature_reg_3_4_1; +reg [15:0] feature_reg_3_5_0; +reg [15:0] feature_reg_3_5_1; +reg [15:0] feature_reg_4_0_0; +reg [15:0] feature_reg_4_0_1; +reg [15:0] feature_reg_4_1_0; +reg [15:0] feature_reg_4_1_1; +reg [15:0] feature_reg_4_2_0; +reg [15:0] feature_reg_4_2_1; +reg [15:0] feature_reg_4_3_0; +reg [15:0] feature_reg_4_3_1; +reg [15:0] feature_reg_4_4_0; +reg [15:0] feature_reg_4_4_1; +reg [15:0] feature_reg_4_5_0; +reg [15:0] feature_reg_4_5_1; +reg [15:0] feature_reg_5_0_0; +reg [15:0] feature_reg_5_0_1; +reg [15:0] feature_reg_5_1_0; +reg [15:0] feature_reg_5_1_1; +reg [15:0] feature_reg_5_2_0; +reg [15:0] feature_reg_5_2_1; +reg [15:0] feature_reg_5_3_0; +reg [15:0] feature_reg_5_3_1; +reg [15:0] feature_reg_5_4_0; +reg [15:0] feature_reg_5_4_1; +reg [15:0] feature_reg_5_5_0; +reg [15:0] feature_reg_5_5_1; + +always @ (posedge clk) begin + calculate_1 <= calculate; + calculate_2 <= calculate_1; + calculate_3 <= calculate_2; + //Valid pipeline + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + valid_12 <= valid_11; + if (i_valid) begin + input_buffer_count <= 0; + calculate <= 0; + end else begin + //Input buffering logic + if (input_buffer_count == 5) begin + calculate <= 1; + input_buffer_count <= 0; + end else begin + calculate <= 0; + input_buffer_count <= input_buffer_count + 1'b1; + end + input_buffer_5_0 <= i_result_0_1; + input_buffer_5_1 <= i_result_1_1; + input_buffer_5_2 <= i_result_2_1; + input_buffer_5_3 <= i_result_3_1; + input_buffer_5_4 <= i_result_4_1; + input_buffer_5_5 <= i_result_5_1; + end + input_buffer_0_0 <= input_buffer_1_0; + input_buffer_0_1 <= input_buffer_1_1; + input_buffer_0_2 <= input_buffer_1_2; + input_buffer_0_3 <= input_buffer_1_3; + input_buffer_0_4 <= input_buffer_1_4; + input_buffer_0_5 <= input_buffer_1_5; + input_buffer_1_0 <= input_buffer_2_0; + input_buffer_1_1 <= input_buffer_2_1; + input_buffer_1_2 <= input_buffer_2_2; + input_buffer_1_3 <= input_buffer_2_3; + input_buffer_1_4 <= input_buffer_2_4; + input_buffer_1_5 <= input_buffer_2_5; + input_buffer_2_0 <= input_buffer_3_0; + input_buffer_2_1 <= input_buffer_3_1; + input_buffer_2_2 <= input_buffer_3_2; + input_buffer_2_3 <= input_buffer_3_3; + input_buffer_2_4 <= input_buffer_3_4; + input_buffer_2_5 <= input_buffer_3_5; + input_buffer_3_0 <= input_buffer_4_0; + input_buffer_3_1 <= input_buffer_4_1; + input_buffer_3_2 <= input_buffer_4_2; + input_buffer_3_3 <= input_buffer_4_3; + input_buffer_3_4 <= input_buffer_4_4; + input_buffer_3_5 <= input_buffer_4_5; + input_buffer_4_0 <= input_buffer_5_0; + input_buffer_4_1 <= input_buffer_5_1; + input_buffer_4_2 <= input_buffer_5_2; + input_buffer_4_3 <= input_buffer_5_3; + input_buffer_4_4 <= input_buffer_5_4; + input_buffer_4_5 <= input_buffer_5_5; + //Pipelining to synchronize DSPs and non-DSPs + feature_reg_0_0_0 <= input_buffer_0_0; + feature_reg_0_1_0 <= input_buffer_0_1; + feature_reg_0_2_0 <= input_buffer_0_2; + feature_reg_0_3_0 <= input_buffer_0_3; + feature_reg_0_4_0 <= input_buffer_0_4; + feature_reg_0_5_0 <= input_buffer_0_5; + feature_reg_1_0_0 <= input_buffer_1_0; + feature_reg_1_1_0 <= input_buffer_1_1; + feature_reg_1_2_0 <= input_buffer_1_2; + feature_reg_1_3_0 <= input_buffer_1_3; + feature_reg_1_4_0 <= input_buffer_1_4; + feature_reg_1_5_0 <= input_buffer_1_5; + feature_reg_2_0_0 <= input_buffer_2_0; + feature_reg_2_1_0 <= input_buffer_2_1; + feature_reg_2_2_0 <= input_buffer_2_2; + feature_reg_2_3_0 <= input_buffer_2_3; + feature_reg_2_4_0 <= input_buffer_2_4; + feature_reg_2_5_0 <= input_buffer_2_5; + feature_reg_3_0_0 <= input_buffer_3_0; + feature_reg_3_1_0 <= input_buffer_3_1; + feature_reg_3_2_0 <= input_buffer_3_2; + feature_reg_3_3_0 <= input_buffer_3_3; + feature_reg_3_4_0 <= input_buffer_3_4; + feature_reg_3_5_0 <= input_buffer_3_5; + feature_reg_4_0_0 <= input_buffer_4_0; + feature_reg_4_1_0 <= input_buffer_4_1; + feature_reg_4_2_0 <= input_buffer_4_2; + feature_reg_4_3_0 <= input_buffer_4_3; + feature_reg_4_4_0 <= input_buffer_4_4; + feature_reg_4_5_0 <= input_buffer_4_5; + feature_reg_5_0_0 <= input_buffer_5_0; + feature_reg_5_1_0 <= input_buffer_5_1; + feature_reg_5_2_0 <= input_buffer_5_2; + feature_reg_5_3_0 <= input_buffer_5_3; + feature_reg_5_4_0 <= input_buffer_5_4; + feature_reg_5_5_0 <= input_buffer_5_5; + feature_reg_0_0_1 <= feature_reg_0_0_0; + feature_reg_0_1_1 <= feature_reg_0_1_0; + feature_reg_0_2_1 <= feature_reg_0_2_0; + feature_reg_0_3_1 <= feature_reg_0_3_0; + feature_reg_0_4_1 <= feature_reg_0_4_0; + feature_reg_0_5_1 <= feature_reg_0_5_0; + feature_reg_1_0_1 <= feature_reg_1_0_0; + feature_reg_1_1_1 <= feature_reg_1_1_0; + feature_reg_1_2_1 <= feature_reg_1_2_0; + feature_reg_1_3_1 <= feature_reg_1_3_0; + feature_reg_1_4_1 <= feature_reg_1_4_0; + feature_reg_1_5_1 <= feature_reg_1_5_0; + feature_reg_2_0_1 <= feature_reg_2_0_0; + feature_reg_2_1_1 <= feature_reg_2_1_0; + feature_reg_2_2_1 <= feature_reg_2_2_0; + feature_reg_2_3_1 <= feature_reg_2_3_0; + feature_reg_2_4_1 <= feature_reg_2_4_0; + feature_reg_2_5_1 <= feature_reg_2_5_0; + feature_reg_3_0_1 <= feature_reg_3_0_0; + feature_reg_3_1_1 <= feature_reg_3_1_0; + feature_reg_3_2_1 <= feature_reg_3_2_0; + feature_reg_3_3_1 <= feature_reg_3_3_0; + feature_reg_3_4_1 <= feature_reg_3_4_0; + feature_reg_3_5_1 <= feature_reg_3_5_0; + feature_reg_4_0_1 <= feature_reg_4_0_0; + feature_reg_4_1_1 <= feature_reg_4_1_0; + feature_reg_4_2_1 <= feature_reg_4_2_0; + feature_reg_4_3_1 <= feature_reg_4_3_0; + feature_reg_4_4_1 <= feature_reg_4_4_0; + feature_reg_4_5_1 <= feature_reg_4_5_0; + feature_reg_5_0_1 <= feature_reg_5_0_0; + feature_reg_5_1_1 <= feature_reg_5_1_0; + feature_reg_5_2_1 <= feature_reg_5_2_0; + feature_reg_5_3_1 <= feature_reg_5_3_0; + feature_reg_5_4_1 <= feature_reg_5_4_0; + feature_reg_5_5_1 <= feature_reg_5_5_0; + //Output Serializing logic + if (calculate_3) begin + output_buffer_0_0 <= rslt_buffer_0_0; + output_buffer_1_0 <= rslt_buffer_0_1; + output_buffer_2_0 <= rslt_buffer_0_2; + output_buffer_3_0 <= rslt_buffer_0_3; + output_buffer_4_0 <= rslt_buffer_0_4; + output_buffer_5_0 <= rslt_buffer_0_5; + output_buffer_0_1 <= rslt_buffer_1_0; + output_buffer_1_1 <= rslt_buffer_1_1; + output_buffer_2_1 <= rslt_buffer_1_2; + output_buffer_3_1 <= rslt_buffer_1_3; + output_buffer_4_1 <= rslt_buffer_1_4; + output_buffer_5_1 <= rslt_buffer_1_5; + output_buffer_0_2 <= rslt_buffer_2_0; + output_buffer_1_2 <= rslt_buffer_2_1; + output_buffer_2_2 <= rslt_buffer_2_2; + output_buffer_3_2 <= rslt_buffer_2_3; + output_buffer_4_2 <= rslt_buffer_2_4; + output_buffer_5_2 <= rslt_buffer_2_5; + output_buffer_0_3 <= rslt_buffer_3_0; + output_buffer_1_3 <= rslt_buffer_3_1; + output_buffer_2_3 <= rslt_buffer_3_2; + output_buffer_3_3 <= rslt_buffer_3_3; + output_buffer_4_3 <= rslt_buffer_3_4; + output_buffer_5_3 <= rslt_buffer_3_5; + output_buffer_0_4 <= rslt_buffer_4_0; + output_buffer_1_4 <= rslt_buffer_4_1; + output_buffer_2_4 <= rslt_buffer_4_2; + output_buffer_3_4 <= rslt_buffer_4_3; + output_buffer_4_4 <= rslt_buffer_4_4; + output_buffer_5_4 <= rslt_buffer_4_5; + output_buffer_0_5 <= rslt_buffer_5_0; + output_buffer_1_5 <= rslt_buffer_5_1; + output_buffer_2_5 <= rslt_buffer_5_2; + output_buffer_3_5 <= rslt_buffer_5_3; + output_buffer_4_5 <= rslt_buffer_5_4; + output_buffer_5_5 <= rslt_buffer_5_5; + end else begin + output_buffer_0_0 <= output_buffer_0_1; + output_buffer_0_1 <= output_buffer_0_2; + output_buffer_0_2 <= output_buffer_0_3; + output_buffer_0_3 <= output_buffer_0_4; + output_buffer_0_4 <= output_buffer_0_5; + output_buffer_1_0 <= output_buffer_1_1; + output_buffer_1_1 <= output_buffer_1_2; + output_buffer_1_2 <= output_buffer_1_3; + output_buffer_1_3 <= output_buffer_1_4; + output_buffer_1_4 <= output_buffer_1_5; + output_buffer_2_0 <= output_buffer_2_1; + output_buffer_2_1 <= output_buffer_2_2; + output_buffer_2_2 <= output_buffer_2_3; + output_buffer_2_3 <= output_buffer_2_4; + output_buffer_2_4 <= output_buffer_2_5; + output_buffer_3_0 <= output_buffer_3_1; + output_buffer_3_1 <= output_buffer_3_2; + output_buffer_3_2 <= output_buffer_3_3; + output_buffer_3_3 <= output_buffer_3_4; + output_buffer_3_4 <= output_buffer_3_5; + output_buffer_4_0 <= output_buffer_4_1; + output_buffer_4_1 <= output_buffer_4_2; + output_buffer_4_2 <= output_buffer_4_3; + output_buffer_4_3 <= output_buffer_4_4; + output_buffer_4_4 <= output_buffer_4_5; + output_buffer_5_0 <= output_buffer_5_1; + output_buffer_5_1 <= output_buffer_5_2; + output_buffer_5_2 <= output_buffer_5_3; + output_buffer_5_3 <= output_buffer_5_4; + output_buffer_5_4 <= output_buffer_5_5; + end +end + +////// FIRST COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD00 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_2), + .by(input_buffer_2_0), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_1_0), + .resultb(dsp_out_1_1) +); + +winograd_dsp_16 winograd_dsp_16_WD10 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_2_4), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_1_2), + .resultb(dsp_out_1_3) +); + +winograd_dsp_16 winograd_dsp_16_WD20 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_2), + .by(input_buffer_1_0), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_1_4), + .resultb(dsp_out_1_5) +); + +winograd_dsp_16 winograd_dsp_16_WD30 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_1_6), + .resultb(dsp_out_1_7) +); + +winograd_dsp_16 winograd_dsp_16_WD40 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_0), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_1_8), + .resultb(dsp_out_1_9) +); + +winograd_dsp_16 winograd_dsp_16_WD50 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_4), + .by(input_buffer_5_2), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_1_10), + .resultb(dsp_out_1_11) +); + +////// SECOND COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD01 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_0), + .resultb(dsp_out_2_1) +); + +winograd_dsp_16 winograd_dsp_16_WD11 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_2), + .resultb(dsp_out_2_3) +); + +winograd_dsp_16 winograd_dsp_16_WD21 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_4), + .resultb(dsp_out_2_5) +); + +winograd_dsp_16 winograd_dsp_16_WD31 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_6), + .resultb(dsp_out_2_7) +); + +////// THIRD COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD02 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_0), + .resultb(dsp_out_3_1) +); + +winograd_dsp_16 winograd_dsp_16_WD12 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_2), + .resultb(dsp_out_3_3) +); + +winograd_dsp_16 winograd_dsp_16_WD22 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_4), + .resultb(dsp_out_3_5) +); + +winograd_dsp_16 winograd_dsp_16_WD32 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_6), + .resultb(dsp_out_3_7) +); + +////// FOURTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD03 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_0), + .resultb(dsp_out_4_1) +); + +winograd_dsp_16 winograd_dsp_16_WD13 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_2), + .resultb(dsp_out_4_3) +); + +winograd_dsp_16 winograd_dsp_16_WD23 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_4), + .resultb(dsp_out_4_5) +); + +winograd_dsp_16 winograd_dsp_16_WD33 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_6), + .resultb(dsp_out_4_7) +); + +////// FIFTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD04 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_0), + .resultb(dsp_out_5_1) +); + +winograd_dsp_16 winograd_dsp_16_WD14 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_2), + .resultb(dsp_out_5_3) +); + +winograd_dsp_16 winograd_dsp_16_WD24 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_4), + .resultb(dsp_out_5_5) +); + +winograd_dsp_16 winograd_dsp_16_WD34 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_6), + .resultb(dsp_out_5_7) +); + +////// SIXTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD05 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_3), + .by(input_buffer_2_1), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_6_0), + .resultb(dsp_out_6_1) +); + +winograd_dsp_16 winograd_dsp_16_WD15 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_5), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_6_2), + .resultb(dsp_out_6_3) +); + +winograd_dsp_16 winograd_dsp_16_WD25 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_3), + .by(input_buffer_1_3), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_6_4), + .resultb(dsp_out_6_5) +); + +winograd_dsp_16 winograd_dsp_16_WD35 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_3_3), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_6_6), + .resultb(dsp_out_6_7) +); + +winograd_dsp_16 winograd_dsp_16_WD45 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_3), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_6_8), + .resultb(dsp_out_6_9) +); + +winograd_dsp_16 winograd_dsp_16_WD55 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_5), + .by(input_buffer_5_3), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_6_10), + .resultb(dsp_out_6_11) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA00 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_0_1[11:0], 4'b0000}), + .data1x(dsp_out_1_0), + .data2x({feature_reg_0_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_1), + .data4x(dsp_out_1_2), + .data5x(dsp_out_1_3), + .data6x({feature_reg_4_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_4), + .data8x(feature_reg_4_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_0) +); + +wire [15:0] f1, f2, f3, f4; +assign f1 = -{feature_reg_1_0_1[11:0], 4'b0000}; +assign f2 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f3 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f4 = -{feature_reg_2_4_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA10 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_1_5), + .data1x(f1), + .data2x(f2), + .data3x(f3), + .data4x(dsp_out_1_6), + .data5x(f4), + .data6x({feature_reg_3_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_7), + .data8x(feature_reg_3_4_1), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_0) +); + +wire [15:0] f5, f6, f7, f8, f9, f10; +assign f5 = -dsp_out_1_5; +assign f6 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f7 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f8 = -{feature_reg_3_0_1[13:0], 2'b00}; +assign f9 = -dsp_out_1_7; +assign f10 = -feature_reg_3_4_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA20 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f5), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(f6), + .data4x(dsp_out_1_6), + .data5x(f7), + .data6x(f8), + .data7x(f9), + .data8x(f10), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_0) +); + +wire [15:0] f11, f12, f13, f14, f15, f16, f17; +assign f11 = -{feature_reg_1_0_1[12:0], 3'b000}; +assign f12 = -{feature_reg_1_4_1[14:0], 1'b0}; +assign f13 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f14 = -feature_reg_2_4_1; +assign f15 = dsp_out_1_5 >>> 1; +assign f16 = dsp_out_1_6 >>> 2; +assign f17 = dsp_out_1_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA30 ( + .clock(clk), + .clken(calculate_2), + .data0x(f15), + .data1x(f11), + .data2x(f12), + .data3x(f13), + .data4x(f16), + .data5x(f14), + .data6x({feature_reg_3_0_1[12:0], 3'b000}), + .data7x(f17), + .data8x({feature_reg_3_4_1[14:0], 1'b0}), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_0) +); + +wire [15:0] f18, f19, f20, f21, f22, f23, f23b; +assign f18 = -(dsp_out_1_5 >>> 1); +assign f19 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f20 = -feature_reg_2_4_1; +assign f21 = -{feature_reg_3_0_1[12:0], 3'b000}; +assign f22 = -(dsp_out_1_7 <<< 1); +assign f23 = -{feature_reg_3_4_1[14:0], 1'b0}; +assign f23b = dsp_out_1_6 >>> 2; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA40 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[12:0], 3'b000}), + .data1x(f18), + .data2x({feature_reg_1_4_1[14:0], 1'b0}), + .data3x(f19), + .data4x(f23b), + .data5x(f20), + .data6x(f21), + .data7x(f22), + .data8x(f23), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_0) +); + +wire [15:0] f24; +assign f24 = -dsp_out_1_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA50 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f24), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_8), + .data4x(dsp_out_1_9), + .data5x(dsp_out_1_10), + .data6x({feature_reg_5_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_11), + .data8x(feature_reg_5_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_0) +); + +wire [15:0] f25, f26, f27, f28; +assign f25 = -{feature_reg_0_2_1[11:0], 4'b0000}; +assign f26 = -{feature_reg_0_1_1[11:0], 4'b0000}; +assign f27 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f28 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA01 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[13:0], 2'b00}), + .data1x(f25), + .data2x(f26), + .data3x({feature_reg_0_4_1[13:0], 2'b00}), + .data4x(dsp_out_2_0), + .data5x(dsp_out_2_1), + .data6x(dsp_out_2_2), + .data7x(dsp_out_2_3), + .data8x(f27), + .data9x(f28), + .data10x(feature_reg_4_3_1), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_1) +); + +wire [15:0] f29, f30, f31, f32, f33, f34, f35, f36; +assign f29 = -{feature_reg_1_3_1[13:0], 2'b00}; +assign f30 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f31 = -{feature_reg_2_3_1[13:0], 2'b00}; +assign f32 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f33 = -{feature_reg_3_1_1[13:0], 2'b00}; +assign f34 = -{feature_reg_3_2_1[13:0], 2'b00}; +assign f35 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f36 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA11 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0], 4'b0000}), + .data1x({feature_reg_1_2_1[11:0], 4'b0000}), + .data2x(f29), + .data3x(f30), + .data4x({feature_reg_2_1_1[11:0], 4'b0000}), + .data5x({feature_reg_2_2_1[11:0], 4'b0000}), + .data6x(f31), + .data7x(f32), + .data8x(f33), + .data9x(f34), + .data10x(feature_reg_3_3_1), + .data11x(feature_reg_3_4_1), + .data12x(f35), + .data13x(f36), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_1) +); + +wire [15:0] f37, f38, f39, f40, f41, f42, f43, f44; +assign f37 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f38 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f39 = -{feature_reg_2_3_1[13:0],2'b00}; +assign f40 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f41 = -feature_reg_3_3_1; +assign f42 = -feature_reg_3_4_1; +assign f43 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f44 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA21 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f37), + .data2x(f38), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[11:0],4'b0000}), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x(f39), + .data7x(f40), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(f41), + .data11x(f42), + .data12x(f43), + .data13x(f44), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_1) +); + +wire [15:0] f45, f46, f47, f48, f49, f50, f51, f52; +assign f45 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f46 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f47 = -feature_reg_2_3_1; +assign f48 = -feature_reg_2_4_1; +assign f49 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f50 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f51 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f52 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA31 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[12:0],3'b000}), + .data2x(f45), + .data3x(f46), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f47), + .data7x(f48), + .data8x(f49), + .data9x(f50), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f51), + .data13x(f52), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_1) +); + +wire [15:0] f53, f54, f55, f56, f57, f58, f59, f60; +assign f53 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f54 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f55 = -feature_reg_2_3_1; +assign f56 = -feature_reg_2_4_1; +assign f57 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f58 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f59 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f60 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA41 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[14:0],1'b0}), + .data1x(f53), + .data2x(f54), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f55), + .data7x(f56), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x(f57), + .data11x(f58), + .data12x(f59), + .data13x(f60), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_1) +); + +wire [15:0] f61, f62, f63, f64; +assign f61 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f62 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f63 = -{feature_reg_5_1_1[13:0],2'b00}; +assign f64 = -{feature_reg_5_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA51 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f61), + .data2x(f62), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_2_4), + .data5x(dsp_out_2_5), + .data6x(dsp_out_2_6), + .data7x(dsp_out_2_7), + .data8x(f63), + .data9x(f64), + .data10x(feature_reg_5_3_1), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_1) +); + +wire [15:0] f65, f66, f67, f68; +assign f65 = -{feature_reg_0_2_1[11:0],4'b0000}; +assign f66 = -{feature_reg_0_3_1[13:0],2'b00}; +assign f67 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f68 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA02 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(f65), + .data2x(f66), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_3_0), + .data5x(dsp_out_3_1), + .data6x(dsp_out_3_2), + .data7x(dsp_out_3_3), + .data8x({feature_reg_4_1_1[13:0],2'b00}), + .data9x(f67), + .data10x(f68), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_2) +); + +wire [15:0] f69, f70, f71, f72, f73, f74, f75, f76; +assign f69 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f70 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f71 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f72 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f73 = -{feature_reg_3_2_1[13:0],2'b00}; +assign f74 = -feature_reg_3_3_1; +assign f75 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f76 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA12 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[11:0],4'b0000}), + .data1x(f69), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f70), + .data4x(f71), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f72), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f73), + .data10x(f74), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f75), + .data14x(f76), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_2) +); + +wire [15:0] f77, f78, f79, f80, f81, f82, f83, f84; +assign f77 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f78 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f79 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f80 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f81 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f82 = -feature_reg_3_4_1; +assign f83 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f84 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA22 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f77), + .data2x(f78), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f79), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f80), + .data8x(f81), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(feature_reg_3_3_1), + .data11x(f82), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f83), + .data14x(f84), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_2) +); + +wire [15:0] f85, f86, f87, f88, f89, f90, f91, f92; +assign f85 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f86 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f87 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f88 = -feature_reg_2_4_1; +assign f89 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f90 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f91 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f92 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA32 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[12:0],3'b000}), + .data1x(f85), + .data2x({feature_reg_1_3_1[14:0],1'b0}), + .data3x(f86), + .data4x(f87), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f88), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x(f89), + .data10x(f90), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f91), + .data14x(f92), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_2) +); + +wire [15:0] f93, f94, f95, f96, f97, f98, f99, f100; +assign f93 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f94 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f95 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f96 = -feature_reg_2_4_1; +assign f97 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f98 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f99 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f100 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA42 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f93), + .data2x(f94), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f95), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f96), + .data8x(f97), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f98), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f99), + .data14x(f100), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_2) +); + +wire [15:0] f101, f102, f103, f104; +assign f101 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f102 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f103 = -{feature_reg_5_2_1[13:0],2'b00}; +assign f104 = -feature_reg_5_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA52 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f101), + .data2x(f102), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_3_4), + .data5x(dsp_out_3_5), + .data6x(dsp_out_3_6), + .data7x(dsp_out_3_7), + .data8x({feature_reg_5_1_1[13:0],2'b00}), + .data9x(f103), + .data10x(f104), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_2) +); + +wire [15:0] f105, f106, f107, f108; +assign f105 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f106 = -{feature_reg_0_1_1[12:0],3'b000}; +assign f107 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f108 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA03 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[12:0],3'b000}), + .data1x(f105), + .data2x(f106), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_4_0), + .data5x(dsp_out_4_1), + .data6x(dsp_out_4_2), + .data7x(dsp_out_4_3), + .data8x(f107), + .data9x(f108), + .data10x({feature_reg_4_3_1[14:0],1'b0}), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_3) +); + +wire [15:0] f109, f110, f111, f112, f113, f114, f115, f116; +assign f109 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f110 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f111 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f112 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f113 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f114 = -feature_reg_3_2_1; +assign f115 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f116 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA13 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[13:0],2'b00}), + .data2x(f109), + .data3x(f110), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f111), + .data7x(f112), + .data8x(f113), + .data9x(f114), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(feature_reg_3_4_1), + .data12x(f115), + .data13x(f116), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_3) +); + +wire [15:0] f117, f118, f119, f120, f121, f122, f123, f124; +assign f117 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f118 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f119 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f120 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f121 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f122 = -feature_reg_3_4_1; +assign f123 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f124 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA23 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f117), + .data2x(f118), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f119), + .data7x(f120), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(feature_reg_3_2_1), + .data10x(f121), + .data11x(f122), + .data12x(f123), + .data13x(f124), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_3) +); + +wire [15:0] f125, f126, f127, f128, f129, f130, f131, f132; +assign f125 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f126 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f127 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f128 = -feature_reg_2_4_1; +assign f129 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f130 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f131 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f132 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA33 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x({feature_reg_1_2_1[14:0],1'b0}), + .data2x(f125), + .data3x(f126), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f127), + .data7x(f128), + .data8x(f129), + .data9x(f130), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f131), + .data13x(f132), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_3) +); + +wire [15:0] f133, f134, f135, f136, f137, f138, f139, f140; +assign f133 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f134 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f135 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f136 = -feature_reg_2_4_1; +assign f137 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f138 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f139 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f140 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA43 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f133), + .data2x(f134), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f135), + .data7x(f136), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x(f137), + .data11x(f138), + .data12x(f139), + .data13x(f140), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_3) +); + +wire [15:0] f141, f142, f143, f144; +assign f141 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f142 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f143 = -{feature_reg_5_1_1[14:0],1'b0}; +assign f144 = -feature_reg_5_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA53 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f141), + .data2x(f142), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_4_4), + .data5x(dsp_out_4_5), + .data6x(dsp_out_4_6), + .data7x(dsp_out_4_7), + .data8x(f143), + .data9x(f144), + .data10x({feature_reg_5_3_1[14:0],1'b0}), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_3) +); + +wire [15:0] f145, f146, f147, f148; +assign f145 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f146 = -{feature_reg_0_3_1[12:0],3'b000}; +assign f147 = -feature_reg_4_2_1; +assign f148 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA04 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[12:0],3'b000}), + .data1x(f145), + .data2x(f146), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_5_0), + .data5x(dsp_out_5_1), + .data6x(dsp_out_5_2), + .data7x(dsp_out_5_3), + .data8x({feature_reg_4_1_1[14:0],1'b0}), + .data9x(f147), + .data10x(f148), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_4) +); + +wire [15:0] f149, f150, f151, f152, f153, f154, f155, f156; +assign f149 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f150 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f151 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f152 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f153 = -feature_reg_3_2_1; +assign f154 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f155 = -feature_reg_4_2_1; +assign f156 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA14 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[13:0],2'b00}), + .data1x(f149), + .data2x({feature_reg_1_3_1[12:0],3'b000}), + .data3x(f150), + .data4x(f151), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f152), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(f153), + .data10x(f154), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f155), + .data14x(f156), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_4) +); + +wire [15:0] f157, f158, f159, f160, f161, f162, f163, f164; +assign f157 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f158 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f159 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f160 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f161 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f162 = -feature_reg_3_4_1; +assign f163 = -feature_reg_4_2_1; +assign f164 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA24 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f157), + .data2x(f158), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f159), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f160), + .data8x(f161), + .data9x(feature_reg_3_2_1), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f162), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f163), + .data14x(f164), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_4) +); + +wire [15:0] f165, f166, f167, f168, f169, f170, f171, f172; +assign f165 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f166 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f167 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f168 = -feature_reg_2_4_1; +assign f169 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f170 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f171 = -feature_reg_4_2_1; +assign f172 = -{feature_reg_4_1_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA34 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[14:0],1'b0}), + .data1x(f165), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f166), + .data4x(f167), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f168), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f169), + .data10x(f170), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f171), + .data14x(f172), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_4) +); + +wire [15:0] f173, f174, f175, f176, f177, f178, f179, f180; +assign f173 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f174 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f175 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f176 = -feature_reg_2_4_1; +assign f177 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f178 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f179 = -feature_reg_4_2_1; +assign f180 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA44 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x(f173), + .data2x(f174), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f175), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f176), + .data8x(f177), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x(f178), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f179), + .data14x(f180), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_4) +); + +wire [15:0] f181, f182, f183, f184; +assign f181 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f182 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f183 = -feature_reg_5_2_1; +assign f184 = -{feature_reg_5_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA54 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f181), + .data2x(f182), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_5_4), + .data5x(dsp_out_5_5), + .data6x(dsp_out_5_6), + .data7x(dsp_out_5_7), + .data8x({feature_reg_5_1_1[14:0],1'b0}), + .data9x(f183), + .data10x(f184), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_4) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA05 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(dsp_out_6_0), + .data2x({feature_reg_0_5_1[13:0],2'b00}), + .data3x(dsp_out_6_1), + .data4x(dsp_out_6_2), + .data5x(dsp_out_6_3), + .data6x({feature_reg_4_1_1[13:0],2'b00}), + .data7x(dsp_out_6_4), + .data8x(feature_reg_4_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_5) +); + +wire [15:0] f185, f186, f187, f188; +assign f185 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f186 = -{feature_reg_1_5_1[13:0],2'b00}; +assign f187 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f188 = -{feature_reg_2_5_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA15 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_6_5), + .data1x(f185), + .data2x(f186), + .data3x(f187), + .data4x(dsp_out_6_6), + .data5x(f188), + .data6x({feature_reg_3_1_1[13:0],2'b00}), + .data7x(dsp_out_6_7), + .data8x(feature_reg_3_5_1), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_5) +); + +wire [15:0] f189, f190, f191, f192, f193, f194; +assign f189 = -dsp_out_6_5; +assign f190 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f191 = -{feature_reg_2_5_1[13:0],2'b00}; +assign f192 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f193 = -dsp_out_6_7; +assign f194 = -feature_reg_3_5_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA25 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f189), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(f190), + .data4x(dsp_out_6_6), + .data5x(f191), + .data6x(f192), + .data7x(f193), + .data8x(f194), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_5) +); + +wire [15:0] f195, f196, f197, f198, f199, f200, f201; +assign f195 = dsp_out_6_5 >>> 1; +assign f196 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f197 = -{feature_reg_1_5_1[14:0],1'b0}; +assign f198 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f199 = dsp_out_6_6 >>> 2; +assign f200 = -feature_reg_2_5_1; +assign f201 = dsp_out_6_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA35 ( + .clock(clk), + .clken(calculate_2), + .data0x(f195), + .data1x(f196), + .data2x(f197), + .data3x(f198), + .data4x(f199), + .data5x(f200), + .data6x({feature_reg_3_1_1[12:0],3'b000}), + .data7x(f201), + .data8x({feature_reg_3_5_1[14:0],1'b0}), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_5) +); + +wire [15:0] f202, f203, f204, f205, f206, f207, f208; +assign f202 = -(dsp_out_6_5 >>> 1); +assign f203 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f204 = dsp_out_6_6 >>> 2; +assign f205 = -feature_reg_2_5_1; +assign f206 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f207 = -(dsp_out_6_7 <<< 1); +assign f208 = -{feature_reg_3_5_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA45 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f202), + .data2x({feature_reg_1_5_1[14:0],1'b0}), + .data3x(f203), + .data4x(f204), + .data5x(f205), + .data6x(f206), + .data7x(f207), + .data8x(f208), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_5) +); + +wire [15:0] f209; +assign f209 = -dsp_out_6_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA55 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f209), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(dsp_out_6_8), + .data4x(dsp_out_6_9), + .data5x(dsp_out_6_10), + .data6x({feature_reg_5_1_1[13:0],2'b00}), + .data7x(dsp_out_6_11), + .data8x(feature_reg_5_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_5) +); + +assign o_feature_0 = output_buffer_0_0[15:0]; +assign o_feature_1 = output_buffer_1_0[15:0]; +assign o_feature_2 = output_buffer_2_0[15:0]; +assign o_feature_3 = output_buffer_3_0[15:0]; +assign o_feature_4 = output_buffer_4_0[15:0]; +assign o_feature_5 = output_buffer_5_0[15:0]; +assign o_valid = valid_9; + +endmodule + +module winograd_adder_16_20_4 ( + input clken, + input clock, + input [15:0] data0x, + input [15:0] data1x, + input [15:0] data2x, + input [15:0] data3x, + input [15:0] data4x, + input [15:0] data5x, + input [15:0] data6x, + input [15:0] data7x, + input [15:0] data8x, + input [15:0] data9x, + input [15:0] data10x, + input [15:0] data11x, + input [15:0] data12x, + input [15:0] data13x, + input [15:0] data14x, + input [15:0] data15x, + output [19:0] result +); + +reg [19:0] pipeline_0_0; +reg [19:0] pipeline_0_1; +reg [19:0] pipeline_0_2; +reg [19:0] pipeline_0_3; +reg [19:0] pipeline_0_4; +reg [19:0] pipeline_0_5; +reg [19:0] pipeline_0_6; +reg [19:0] pipeline_0_7; +reg [19:0] pipeline_1_0; +reg [19:0] pipeline_1_1; +reg [19:0] pipeline_1_2; +reg [19:0] pipeline_1_3; +reg [19:0] pipeline_2_0; +reg [19:0] pipeline_2_1; +reg [19:0] pipeline_3_0; + +always @ (posedge clock) begin + pipeline_0_0 <= data0x + data1x; + pipeline_0_1 <= data2x + data3x; + pipeline_0_2 <= data4x + data5x; + pipeline_0_3 <= data6x + data7x; + pipeline_0_4 <= data8x + data9x; + pipeline_0_5 <= data10x + data11x; + pipeline_0_6 <= data12x + data13x; + pipeline_0_7 <= data14x + data15x; + pipeline_1_0 <= pipeline_0_0 + pipeline_0_1; + pipeline_1_1 <= pipeline_0_2 + pipeline_0_3; + pipeline_1_2 <= pipeline_0_4 + pipeline_0_5; + pipeline_1_3 <= pipeline_0_6 + pipeline_0_7; + pipeline_2_0 <= pipeline_1_0 + pipeline_1_1; + pipeline_2_1 <= pipeline_1_2 + pipeline_1_3; + pipeline_3_0 <= pipeline_2_0 + pipeline_2_1; +end + +assign result = pipeline_3_0; + +endmodule + +module winograd_dsp_16 ( + input clk, + input ena, + input aclr, + input [15:0] ay, + input [15:0] by, + input [2:0] coefsela, + input [2:0] coefselb, + output [15:0] resulta, + output [15:0] resultb +); + +reg [15:0] coefa, coefb, ay_reg, by_reg, resa_reg, resb_reg; +assign resulta = resa_reg; +assign resultb = resb_reg; + +always @ (posedge clk) begin + if (aclr) begin + coefa <= 0; + coefb <= 0; + ay_reg <= 0; + by_reg <= 0; + resa_reg <= 0; + resb_reg <= 0; + end else begin + ay_reg <= ay; + by_reg <= by; + if (coefsela == 0) begin + coefa <= 5; + end else if (coefsela == 1) begin + coefa <= -5; + end else if (coefsela == 2) begin + coefa <= 10; + end else if (coefsela == 3) begin + coefa <= -10; + end else if (coefsela == 4) begin + coefa <= 20; + end else if (coefsela == 5) begin + coefa <= -20; + end else if (coefsela == 6) begin + coefa <= 25; + end else if (coefsela == 7) begin + coefa <= -25; + end else begin + coefa <= 0; + end + if (coefselb == 0) begin + coefb <= 5; + end else if (coefselb == 1) begin + coefb <= -5; + end else if (coefselb == 2) begin + coefb <= 10; + end else if (coefselb == 3) begin + coefb <= -10; + end else if (coefselb == 4) begin + coefb <= 20; + end else if (coefselb == 5) begin + coefb <= -20; + end else if (coefselb == 6) begin + coefb <= 25; + end else if (coefselb == 7) begin + coefb <= -25; + end else begin + coefb <= 0; + end + resa_reg <= ay_reg * coefa; + resb_reg <= by_reg * coefb; + end +end + +endmodule + +module winograd_transform_0 ( + input clk, + input i_valid, + input [15:0] i_result_0_0, + input [15:0] i_result_0_1, + input [15:0] i_result_1_0, + input [15:0] i_result_1_1, + input [15:0] i_result_2_0, + input [15:0] i_result_2_1, + input [15:0] i_result_3_0, + input [15:0] i_result_3_1, + input [15:0] i_result_4_0, + input [15:0] i_result_4_1, + input [15:0] i_result_5_0, + input [15:0] i_result_5_1, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output [15:0] o_feature_2, + output [15:0] o_feature_3, + output [15:0] o_feature_4, + output [15:0] o_feature_5, + output o_valid +); + +reg [15:0] input_buffer_0_0; +reg [19:0] output_buffer_0_0; +wire [19:0] rslt_buffer_0_0; +reg [15:0] input_buffer_0_1; +reg [19:0] output_buffer_0_1; +wire [19:0] rslt_buffer_0_1; +reg [15:0] input_buffer_0_2; +reg [19:0] output_buffer_0_2; +wire [19:0] rslt_buffer_0_2; +reg [15:0] input_buffer_0_3; +reg [19:0] output_buffer_0_3; +wire [19:0] rslt_buffer_0_3; +reg [15:0] input_buffer_0_4; +reg [19:0] output_buffer_0_4; +wire [19:0] rslt_buffer_0_4; +reg [15:0] input_buffer_0_5; +reg [19:0] output_buffer_0_5; +wire [19:0] rslt_buffer_0_5; +reg [15:0] input_buffer_1_0; +reg [19:0] output_buffer_1_0; +wire [19:0] rslt_buffer_1_0; +reg [15:0] input_buffer_1_1; +reg [19:0] output_buffer_1_1; +wire [19:0] rslt_buffer_1_1; +reg [15:0] input_buffer_1_2; +reg [19:0] output_buffer_1_2; +wire [19:0] rslt_buffer_1_2; +reg [15:0] input_buffer_1_3; +reg [19:0] output_buffer_1_3; +wire [19:0] rslt_buffer_1_3; +reg [15:0] input_buffer_1_4; +reg [19:0] output_buffer_1_4; +wire [19:0] rslt_buffer_1_4; +reg [15:0] input_buffer_1_5; +reg [19:0] output_buffer_1_5; +wire [19:0] rslt_buffer_1_5; +reg [15:0] input_buffer_2_0; +reg [19:0] output_buffer_2_0; +wire [19:0] rslt_buffer_2_0; +reg [15:0] input_buffer_2_1; +reg [19:0] output_buffer_2_1; +wire [19:0] rslt_buffer_2_1; +reg [15:0] input_buffer_2_2; +reg [19:0] output_buffer_2_2; +wire [19:0] rslt_buffer_2_2; +reg [15:0] input_buffer_2_3; +reg [19:0] output_buffer_2_3; +wire [19:0] rslt_buffer_2_3; +reg [15:0] input_buffer_2_4; +reg [19:0] output_buffer_2_4; +wire [19:0] rslt_buffer_2_4; +reg [15:0] input_buffer_2_5; +reg [19:0] output_buffer_2_5; +wire [19:0] rslt_buffer_2_5; +reg [15:0] input_buffer_3_0; +reg [19:0] output_buffer_3_0; +wire [19:0] rslt_buffer_3_0; +reg [15:0] input_buffer_3_1; +reg [19:0] output_buffer_3_1; +wire [19:0] rslt_buffer_3_1; +reg [15:0] input_buffer_3_2; +reg [19:0] output_buffer_3_2; +wire [19:0] rslt_buffer_3_2; +reg [15:0] input_buffer_3_3; +reg [19:0] output_buffer_3_3; +wire [19:0] rslt_buffer_3_3; +reg [15:0] input_buffer_3_4; +reg [19:0] output_buffer_3_4; +wire [19:0] rslt_buffer_3_4; +reg [15:0] input_buffer_3_5; +reg [19:0] output_buffer_3_5; +wire [19:0] rslt_buffer_3_5; +reg [15:0] input_buffer_4_0; +reg [19:0] output_buffer_4_0; +wire [19:0] rslt_buffer_4_0; +reg [15:0] input_buffer_4_1; +reg [19:0] output_buffer_4_1; +wire [19:0] rslt_buffer_4_1; +reg [15:0] input_buffer_4_2; +reg [19:0] output_buffer_4_2; +wire [19:0] rslt_buffer_4_2; +reg [15:0] input_buffer_4_3; +reg [19:0] output_buffer_4_3; +wire [19:0] rslt_buffer_4_3; +reg [15:0] input_buffer_4_4; +reg [19:0] output_buffer_4_4; +wire [19:0] rslt_buffer_4_4; +reg [15:0] input_buffer_4_5; +reg [19:0] output_buffer_4_5; +wire [19:0] rslt_buffer_4_5; +reg [15:0] input_buffer_5_0; +reg [19:0] output_buffer_5_0; +wire [19:0] rslt_buffer_5_0; +reg [15:0] input_buffer_5_1; +reg [19:0] output_buffer_5_1; +wire [19:0] rslt_buffer_5_1; +reg [15:0] input_buffer_5_2; +reg [19:0] output_buffer_5_2; +wire [19:0] rslt_buffer_5_2; +reg [15:0] input_buffer_5_3; +reg [19:0] output_buffer_5_3; +wire [19:0] rslt_buffer_5_3; +reg [15:0] input_buffer_5_4; +reg [19:0] output_buffer_5_4; +wire [19:0] rslt_buffer_5_4; +reg [15:0] input_buffer_5_5; +reg [19:0] output_buffer_5_5; +wire [19:0] rslt_buffer_5_5; +reg calculate, calculate_1, calculate_2, calculate_3; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg valid_12; +reg [2:0] input_buffer_count; +wire [15:0] dsp_out_1_0; +wire [15:0] dsp_out_1_1; +wire [15:0] dsp_out_1_2; +wire [15:0] dsp_out_1_3; +wire [15:0] dsp_out_1_4; +wire [15:0] dsp_out_1_5; +wire [15:0] dsp_out_1_6; +wire [15:0] dsp_out_1_7; +wire [15:0] dsp_out_1_8; +wire [15:0] dsp_out_1_9; +wire [15:0] dsp_out_1_10; +wire [15:0] dsp_out_1_11; +wire [15:0] dsp_out_2_0; +wire [15:0] dsp_out_2_1; +wire [15:0] dsp_out_2_2; +wire [15:0] dsp_out_2_3; +wire [15:0] dsp_out_2_4; +wire [15:0] dsp_out_2_5; +wire [15:0] dsp_out_2_6; +wire [15:0] dsp_out_2_7; +wire [15:0] dsp_out_3_0; +wire [15:0] dsp_out_3_1; +wire [15:0] dsp_out_3_2; +wire [15:0] dsp_out_3_3; +wire [15:0] dsp_out_3_4; +wire [15:0] dsp_out_3_5; +wire [15:0] dsp_out_3_6; +wire [15:0] dsp_out_3_7; +wire [15:0] dsp_out_4_0; +wire [15:0] dsp_out_4_1; +wire [15:0] dsp_out_4_2; +wire [15:0] dsp_out_4_3; +wire [15:0] dsp_out_4_4; +wire [15:0] dsp_out_4_5; +wire [15:0] dsp_out_4_6; +wire [15:0] dsp_out_4_7; +wire [15:0] dsp_out_5_0; +wire [15:0] dsp_out_5_1; +wire [15:0] dsp_out_5_2; +wire [15:0] dsp_out_5_3; +wire [15:0] dsp_out_5_4; +wire [15:0] dsp_out_5_5; +wire [15:0] dsp_out_5_6; +wire [15:0] dsp_out_5_7; +wire [15:0] dsp_out_6_0; +wire [15:0] dsp_out_6_1; +wire [15:0] dsp_out_6_2; +wire [15:0] dsp_out_6_3; +wire [15:0] dsp_out_6_4; +wire [15:0] dsp_out_6_5; +wire [15:0] dsp_out_6_6; +wire [15:0] dsp_out_6_7; +wire [15:0] dsp_out_6_8; +wire [15:0] dsp_out_6_9; +wire [15:0] dsp_out_6_10; +wire [15:0] dsp_out_6_11; +reg [15:0] feature_reg_0_0_0; +reg [15:0] feature_reg_0_0_1; +reg [15:0] feature_reg_0_1_0; +reg [15:0] feature_reg_0_1_1; +reg [15:0] feature_reg_0_2_0; +reg [15:0] feature_reg_0_2_1; +reg [15:0] feature_reg_0_3_0; +reg [15:0] feature_reg_0_3_1; +reg [15:0] feature_reg_0_4_0; +reg [15:0] feature_reg_0_4_1; +reg [15:0] feature_reg_0_5_0; +reg [15:0] feature_reg_0_5_1; +reg [15:0] feature_reg_1_0_0; +reg [15:0] feature_reg_1_0_1; +reg [15:0] feature_reg_1_1_0; +reg [15:0] feature_reg_1_1_1; +reg [15:0] feature_reg_1_2_0; +reg [15:0] feature_reg_1_2_1; +reg [15:0] feature_reg_1_3_0; +reg [15:0] feature_reg_1_3_1; +reg [15:0] feature_reg_1_4_0; +reg [15:0] feature_reg_1_4_1; +reg [15:0] feature_reg_1_5_0; +reg [15:0] feature_reg_1_5_1; +reg [15:0] feature_reg_2_0_0; +reg [15:0] feature_reg_2_0_1; +reg [15:0] feature_reg_2_1_0; +reg [15:0] feature_reg_2_1_1; +reg [15:0] feature_reg_2_2_0; +reg [15:0] feature_reg_2_2_1; +reg [15:0] feature_reg_2_3_0; +reg [15:0] feature_reg_2_3_1; +reg [15:0] feature_reg_2_4_0; +reg [15:0] feature_reg_2_4_1; +reg [15:0] feature_reg_2_5_0; +reg [15:0] feature_reg_2_5_1; +reg [15:0] feature_reg_3_0_0; +reg [15:0] feature_reg_3_0_1; +reg [15:0] feature_reg_3_1_0; +reg [15:0] feature_reg_3_1_1; +reg [15:0] feature_reg_3_2_0; +reg [15:0] feature_reg_3_2_1; +reg [15:0] feature_reg_3_3_0; +reg [15:0] feature_reg_3_3_1; +reg [15:0] feature_reg_3_4_0; +reg [15:0] feature_reg_3_4_1; +reg [15:0] feature_reg_3_5_0; +reg [15:0] feature_reg_3_5_1; +reg [15:0] feature_reg_4_0_0; +reg [15:0] feature_reg_4_0_1; +reg [15:0] feature_reg_4_1_0; +reg [15:0] feature_reg_4_1_1; +reg [15:0] feature_reg_4_2_0; +reg [15:0] feature_reg_4_2_1; +reg [15:0] feature_reg_4_3_0; +reg [15:0] feature_reg_4_3_1; +reg [15:0] feature_reg_4_4_0; +reg [15:0] feature_reg_4_4_1; +reg [15:0] feature_reg_4_5_0; +reg [15:0] feature_reg_4_5_1; +reg [15:0] feature_reg_5_0_0; +reg [15:0] feature_reg_5_0_1; +reg [15:0] feature_reg_5_1_0; +reg [15:0] feature_reg_5_1_1; +reg [15:0] feature_reg_5_2_0; +reg [15:0] feature_reg_5_2_1; +reg [15:0] feature_reg_5_3_0; +reg [15:0] feature_reg_5_3_1; +reg [15:0] feature_reg_5_4_0; +reg [15:0] feature_reg_5_4_1; +reg [15:0] feature_reg_5_5_0; +reg [15:0] feature_reg_5_5_1; + +always @ (posedge clk) begin + calculate_1 <= calculate; + calculate_2 <= calculate_1; + calculate_3 <= calculate_2; + //Valid pipeline + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + valid_12 <= valid_11; + if (i_valid) begin + input_buffer_count <= 0; + calculate <= 0; + end else begin + //Input buffering logic + if (input_buffer_count == 5) begin + calculate <= 1; + input_buffer_count <= 0; + end else begin + calculate <= 0; + input_buffer_count <= input_buffer_count + 1'b1; + end + input_buffer_5_0 <= i_result_0_0; + input_buffer_5_1 <= i_result_1_0; + input_buffer_5_2 <= i_result_2_0; + input_buffer_5_3 <= i_result_3_0; + input_buffer_5_4 <= i_result_4_0; + input_buffer_5_5 <= i_result_5_0; + end + input_buffer_0_0 <= input_buffer_1_0; + input_buffer_0_1 <= input_buffer_1_1; + input_buffer_0_2 <= input_buffer_1_2; + input_buffer_0_3 <= input_buffer_1_3; + input_buffer_0_4 <= input_buffer_1_4; + input_buffer_0_5 <= input_buffer_1_5; + input_buffer_1_0 <= input_buffer_2_0; + input_buffer_1_1 <= input_buffer_2_1; + input_buffer_1_2 <= input_buffer_2_2; + input_buffer_1_3 <= input_buffer_2_3; + input_buffer_1_4 <= input_buffer_2_4; + input_buffer_1_5 <= input_buffer_2_5; + input_buffer_2_0 <= input_buffer_3_0; + input_buffer_2_1 <= input_buffer_3_1; + input_buffer_2_2 <= input_buffer_3_2; + input_buffer_2_3 <= input_buffer_3_3; + input_buffer_2_4 <= input_buffer_3_4; + input_buffer_2_5 <= input_buffer_3_5; + input_buffer_3_0 <= input_buffer_4_0; + input_buffer_3_1 <= input_buffer_4_1; + input_buffer_3_2 <= input_buffer_4_2; + input_buffer_3_3 <= input_buffer_4_3; + input_buffer_3_4 <= input_buffer_4_4; + input_buffer_3_5 <= input_buffer_4_5; + input_buffer_4_0 <= input_buffer_5_0; + input_buffer_4_1 <= input_buffer_5_1; + input_buffer_4_2 <= input_buffer_5_2; + input_buffer_4_3 <= input_buffer_5_3; + input_buffer_4_4 <= input_buffer_5_4; + input_buffer_4_5 <= input_buffer_5_5; + //Pipelining to synchronize DSPs and non-DSPs + feature_reg_0_0_0 <= input_buffer_0_0; + feature_reg_0_1_0 <= input_buffer_0_1; + feature_reg_0_2_0 <= input_buffer_0_2; + feature_reg_0_3_0 <= input_buffer_0_3; + feature_reg_0_4_0 <= input_buffer_0_4; + feature_reg_0_5_0 <= input_buffer_0_5; + feature_reg_1_0_0 <= input_buffer_1_0; + feature_reg_1_1_0 <= input_buffer_1_1; + feature_reg_1_2_0 <= input_buffer_1_2; + feature_reg_1_3_0 <= input_buffer_1_3; + feature_reg_1_4_0 <= input_buffer_1_4; + feature_reg_1_5_0 <= input_buffer_1_5; + feature_reg_2_0_0 <= input_buffer_2_0; + feature_reg_2_1_0 <= input_buffer_2_1; + feature_reg_2_2_0 <= input_buffer_2_2; + feature_reg_2_3_0 <= input_buffer_2_3; + feature_reg_2_4_0 <= input_buffer_2_4; + feature_reg_2_5_0 <= input_buffer_2_5; + feature_reg_3_0_0 <= input_buffer_3_0; + feature_reg_3_1_0 <= input_buffer_3_1; + feature_reg_3_2_0 <= input_buffer_3_2; + feature_reg_3_3_0 <= input_buffer_3_3; + feature_reg_3_4_0 <= input_buffer_3_4; + feature_reg_3_5_0 <= input_buffer_3_5; + feature_reg_4_0_0 <= input_buffer_4_0; + feature_reg_4_1_0 <= input_buffer_4_1; + feature_reg_4_2_0 <= input_buffer_4_2; + feature_reg_4_3_0 <= input_buffer_4_3; + feature_reg_4_4_0 <= input_buffer_4_4; + feature_reg_4_5_0 <= input_buffer_4_5; + feature_reg_5_0_0 <= input_buffer_5_0; + feature_reg_5_1_0 <= input_buffer_5_1; + feature_reg_5_2_0 <= input_buffer_5_2; + feature_reg_5_3_0 <= input_buffer_5_3; + feature_reg_5_4_0 <= input_buffer_5_4; + feature_reg_5_5_0 <= input_buffer_5_5; + feature_reg_0_0_1 <= feature_reg_0_0_0; + feature_reg_0_1_1 <= feature_reg_0_1_0; + feature_reg_0_2_1 <= feature_reg_0_2_0; + feature_reg_0_3_1 <= feature_reg_0_3_0; + feature_reg_0_4_1 <= feature_reg_0_4_0; + feature_reg_0_5_1 <= feature_reg_0_5_0; + feature_reg_1_0_1 <= feature_reg_1_0_0; + feature_reg_1_1_1 <= feature_reg_1_1_0; + feature_reg_1_2_1 <= feature_reg_1_2_0; + feature_reg_1_3_1 <= feature_reg_1_3_0; + feature_reg_1_4_1 <= feature_reg_1_4_0; + feature_reg_1_5_1 <= feature_reg_1_5_0; + feature_reg_2_0_1 <= feature_reg_2_0_0; + feature_reg_2_1_1 <= feature_reg_2_1_0; + feature_reg_2_2_1 <= feature_reg_2_2_0; + feature_reg_2_3_1 <= feature_reg_2_3_0; + feature_reg_2_4_1 <= feature_reg_2_4_0; + feature_reg_2_5_1 <= feature_reg_2_5_0; + feature_reg_3_0_1 <= feature_reg_3_0_0; + feature_reg_3_1_1 <= feature_reg_3_1_0; + feature_reg_3_2_1 <= feature_reg_3_2_0; + feature_reg_3_3_1 <= feature_reg_3_3_0; + feature_reg_3_4_1 <= feature_reg_3_4_0; + feature_reg_3_5_1 <= feature_reg_3_5_0; + feature_reg_4_0_1 <= feature_reg_4_0_0; + feature_reg_4_1_1 <= feature_reg_4_1_0; + feature_reg_4_2_1 <= feature_reg_4_2_0; + feature_reg_4_3_1 <= feature_reg_4_3_0; + feature_reg_4_4_1 <= feature_reg_4_4_0; + feature_reg_4_5_1 <= feature_reg_4_5_0; + feature_reg_5_0_1 <= feature_reg_5_0_0; + feature_reg_5_1_1 <= feature_reg_5_1_0; + feature_reg_5_2_1 <= feature_reg_5_2_0; + feature_reg_5_3_1 <= feature_reg_5_3_0; + feature_reg_5_4_1 <= feature_reg_5_4_0; + feature_reg_5_5_1 <= feature_reg_5_5_0; + //Output Serializing logic + if (calculate_3) begin + output_buffer_0_0 <= rslt_buffer_0_0; + output_buffer_1_0 <= rslt_buffer_0_1; + output_buffer_2_0 <= rslt_buffer_0_2; + output_buffer_3_0 <= rslt_buffer_0_3; + output_buffer_4_0 <= rslt_buffer_0_4; + output_buffer_5_0 <= rslt_buffer_0_5; + output_buffer_0_1 <= rslt_buffer_1_0; + output_buffer_1_1 <= rslt_buffer_1_1; + output_buffer_2_1 <= rslt_buffer_1_2; + output_buffer_3_1 <= rslt_buffer_1_3; + output_buffer_4_1 <= rslt_buffer_1_4; + output_buffer_5_1 <= rslt_buffer_1_5; + output_buffer_0_2 <= rslt_buffer_2_0; + output_buffer_1_2 <= rslt_buffer_2_1; + output_buffer_2_2 <= rslt_buffer_2_2; + output_buffer_3_2 <= rslt_buffer_2_3; + output_buffer_4_2 <= rslt_buffer_2_4; + output_buffer_5_2 <= rslt_buffer_2_5; + output_buffer_0_3 <= rslt_buffer_3_0; + output_buffer_1_3 <= rslt_buffer_3_1; + output_buffer_2_3 <= rslt_buffer_3_2; + output_buffer_3_3 <= rslt_buffer_3_3; + output_buffer_4_3 <= rslt_buffer_3_4; + output_buffer_5_3 <= rslt_buffer_3_5; + output_buffer_0_4 <= rslt_buffer_4_0; + output_buffer_1_4 <= rslt_buffer_4_1; + output_buffer_2_4 <= rslt_buffer_4_2; + output_buffer_3_4 <= rslt_buffer_4_3; + output_buffer_4_4 <= rslt_buffer_4_4; + output_buffer_5_4 <= rslt_buffer_4_5; + output_buffer_0_5 <= rslt_buffer_5_0; + output_buffer_1_5 <= rslt_buffer_5_1; + output_buffer_2_5 <= rslt_buffer_5_2; + output_buffer_3_5 <= rslt_buffer_5_3; + output_buffer_4_5 <= rslt_buffer_5_4; + output_buffer_5_5 <= rslt_buffer_5_5; + end else begin + output_buffer_0_0 <= output_buffer_0_1; + output_buffer_0_1 <= output_buffer_0_2; + output_buffer_0_2 <= output_buffer_0_3; + output_buffer_0_3 <= output_buffer_0_4; + output_buffer_0_4 <= output_buffer_0_5; + output_buffer_1_0 <= output_buffer_1_1; + output_buffer_1_1 <= output_buffer_1_2; + output_buffer_1_2 <= output_buffer_1_3; + output_buffer_1_3 <= output_buffer_1_4; + output_buffer_1_4 <= output_buffer_1_5; + output_buffer_2_0 <= output_buffer_2_1; + output_buffer_2_1 <= output_buffer_2_2; + output_buffer_2_2 <= output_buffer_2_3; + output_buffer_2_3 <= output_buffer_2_4; + output_buffer_2_4 <= output_buffer_2_5; + output_buffer_3_0 <= output_buffer_3_1; + output_buffer_3_1 <= output_buffer_3_2; + output_buffer_3_2 <= output_buffer_3_3; + output_buffer_3_3 <= output_buffer_3_4; + output_buffer_3_4 <= output_buffer_3_5; + output_buffer_4_0 <= output_buffer_4_1; + output_buffer_4_1 <= output_buffer_4_2; + output_buffer_4_2 <= output_buffer_4_3; + output_buffer_4_3 <= output_buffer_4_4; + output_buffer_4_4 <= output_buffer_4_5; + output_buffer_5_0 <= output_buffer_5_1; + output_buffer_5_1 <= output_buffer_5_2; + output_buffer_5_2 <= output_buffer_5_3; + output_buffer_5_3 <= output_buffer_5_4; + output_buffer_5_4 <= output_buffer_5_5; + end +end + +////// FIRST COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD00 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_2), + .by(input_buffer_2_0), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_1_0), + .resultb(dsp_out_1_1) +); + +winograd_dsp_16 winograd_dsp_16_WD10 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_2_4), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_1_2), + .resultb(dsp_out_1_3) +); + +winograd_dsp_16 winograd_dsp_16_WD20 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_2), + .by(input_buffer_1_0), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_1_4), + .resultb(dsp_out_1_5) +); + +winograd_dsp_16 winograd_dsp_16_WD30 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_2), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_1_6), + .resultb(dsp_out_1_7) +); + +winograd_dsp_16 winograd_dsp_16_WD40 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_0), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_1_8), + .resultb(dsp_out_1_9) +); + +winograd_dsp_16 winograd_dsp_16_WD50 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_4), + .by(input_buffer_5_2), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_1_10), + .resultb(dsp_out_1_11) +); + +////// SECOND COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD01 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_0), + .resultb(dsp_out_2_1) +); + +winograd_dsp_16 winograd_dsp_16_WD11 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_2), + .resultb(dsp_out_2_3) +); + +winograd_dsp_16 winograd_dsp_16_WD21 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b100), + .coefselb(3'b100), + .resulta(dsp_out_2_4), + .resultb(dsp_out_2_5) +); + +winograd_dsp_16 winograd_dsp_16_WD31 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_2_6), + .resultb(dsp_out_2_7) +); + +////// THIRD COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD02 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_0), + .resultb(dsp_out_3_1) +); + +winograd_dsp_16 winograd_dsp_16_WD12 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_2), + .resultb(dsp_out_3_3) +); + +winograd_dsp_16 winograd_dsp_16_WD22 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b101), + .coefselb(3'b100), + .resulta(dsp_out_3_4), + .resultb(dsp_out_3_5) +); + +winograd_dsp_16 winograd_dsp_16_WD32 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b000), + .coefselb(3'b001), + .resulta(dsp_out_3_6), + .resultb(dsp_out_3_7) +); + +////// FOURTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD03 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_0), + .resultb(dsp_out_4_1) +); + +winograd_dsp_16 winograd_dsp_16_WD13 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_2), + .resultb(dsp_out_4_3) +); + +winograd_dsp_16 winograd_dsp_16_WD23 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b010), + .coefselb(3'b000), + .resulta(dsp_out_4_4), + .resultb(dsp_out_4_5) +); + +winograd_dsp_16 winograd_dsp_16_WD33 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b011), + .coefselb(3'b001), + .resulta(dsp_out_4_6), + .resultb(dsp_out_4_7) +); + +////// FIFTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD04 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_1), + .by(input_buffer_2_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_0), + .resultb(dsp_out_5_1) +); + +winograd_dsp_16 winograd_dsp_16_WD14 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_2), + .resultb(dsp_out_5_3) +); + +winograd_dsp_16 winograd_dsp_16_WD24 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_2), + .coefsela(3'b011), + .coefselb(3'b000), + .resulta(dsp_out_5_4), + .resultb(dsp_out_5_5) +); + +winograd_dsp_16 winograd_dsp_16_WD34 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_3), + .by(input_buffer_3_4), + .coefsela(3'b010), + .coefselb(3'b001), + .resulta(dsp_out_5_6), + .resultb(dsp_out_5_7) +); + +////// SIXTH COLUMN ////// +winograd_dsp_16 winograd_dsp_16_WD05 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_0_3), + .by(input_buffer_2_1), + .coefsela(3'b101), + .coefselb(3'b101), + .resulta(dsp_out_6_0), + .resultb(dsp_out_6_1) +); + +winograd_dsp_16 winograd_dsp_16_WD15 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_2_5), + .coefsela(3'b110), + .coefselb(3'b001), + .resulta(dsp_out_6_2), + .resultb(dsp_out_6_3) +); + +winograd_dsp_16 winograd_dsp_16_WD25 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_4_3), + .by(input_buffer_1_3), + .coefsela(3'b001), + .coefselb(3'b100), + .resulta(dsp_out_6_4), + .resultb(dsp_out_6_5) +); + +winograd_dsp_16 winograd_dsp_16_WD35 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_2_3), + .by(input_buffer_3_3), + .coefsela(3'b100), + .coefselb(3'b001), + .resulta(dsp_out_6_6), + .resultb(dsp_out_6_7) +); + +winograd_dsp_16 winograd_dsp_16_WD45 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_1), + .by(input_buffer_3_3), + .coefsela(3'b101), + .coefselb(3'b110), + .resulta(dsp_out_6_8), + .resultb(dsp_out_6_9) +); + +winograd_dsp_16 winograd_dsp_16_WD55 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ay(input_buffer_3_5), + .by(input_buffer_5_3), + .coefsela(3'b001), + .coefselb(3'b001), + .resulta(dsp_out_6_10), + .resultb(dsp_out_6_11) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA00 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_0_1[11:0], 4'b0000}), + .data1x(dsp_out_1_0), + .data2x({feature_reg_0_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_1), + .data4x(dsp_out_1_2), + .data5x(dsp_out_1_3), + .data6x({feature_reg_4_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_4), + .data8x(feature_reg_4_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_0) +); + +wire [15:0] f1, f2, f3, f4; +assign f1 = -{feature_reg_1_0_1[11:0], 4'b0000}; +assign f2 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f3 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f4 = -{feature_reg_2_4_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA10 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_1_5), + .data1x(f1), + .data2x(f2), + .data3x(f3), + .data4x(dsp_out_1_6), + .data5x(f4), + .data6x({feature_reg_3_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_7), + .data8x(feature_reg_3_4_1), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_0) +); + +wire [15:0] f5, f6, f7, f8, f9, f10; +assign f5 = -dsp_out_1_5; +assign f6 = -{feature_reg_2_0_1[11:0], 4'b0000}; +assign f7 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f8 = -{feature_reg_3_0_1[13:0], 2'b00}; +assign f9 = -dsp_out_1_7; +assign f10 = -feature_reg_3_4_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA20 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f5), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(f6), + .data4x(dsp_out_1_6), + .data5x(f7), + .data6x(f8), + .data7x(f9), + .data8x(f10), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_0) +); + +wire [15:0] f11, f12, f13, f14, f15, f16, f17; +assign f11 = -{feature_reg_1_0_1[12:0], 3'b000}; +assign f12 = -{feature_reg_1_4_1[14:0], 1'b0}; +assign f13 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f14 = -feature_reg_2_4_1; +assign f15 = dsp_out_1_5 >>> 1; +assign f16 = dsp_out_1_6 >>> 2; +assign f17 = dsp_out_1_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA30 ( + .clock(clk), + .clken(calculate_2), + .data0x(f15), + .data1x(f11), + .data2x(f12), + .data3x(f13), + .data4x(f16), + .data5x(f14), + .data6x({feature_reg_3_0_1[12:0], 3'b000}), + .data7x(f17), + .data8x({feature_reg_3_4_1[14:0], 1'b0}), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_0) +); + +wire [15:0] f18, f19, f20, f21, f22, f23, f23b; +assign f18 = -(dsp_out_1_5 >>> 1); +assign f19 = -{feature_reg_2_0_1[13:0], 2'b00}; +assign f20 = -feature_reg_2_4_1; +assign f21 = -{feature_reg_3_0_1[12:0], 3'b000}; +assign f22 = -(dsp_out_1_7 <<< 1); +assign f23 = -{feature_reg_3_4_1[14:0], 1'b0}; +assign f23b = dsp_out_1_6 >>> 2; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA40 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[12:0], 3'b000}), + .data1x(f18), + .data2x({feature_reg_1_4_1[14:0], 1'b0}), + .data3x(f19), + .data4x(f23b), + .data5x(f20), + .data6x(f21), + .data7x(f22), + .data8x(f23), + .data9x({feature_reg_4_0_1[13:0], 2'b00}), + .data10x(dsp_out_1_4), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_0) +); + +wire [15:0] f24; +assign f24 = -dsp_out_1_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA50 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_0_1[11:0], 4'b0000}), + .data1x(f24), + .data2x({feature_reg_1_4_1[13:0], 2'b00}), + .data3x(dsp_out_1_8), + .data4x(dsp_out_1_9), + .data5x(dsp_out_1_10), + .data6x({feature_reg_5_0_1[13:0], 2'b00}), + .data7x(dsp_out_1_11), + .data8x(feature_reg_5_4_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_0) +); + +wire [15:0] f25, f26, f27, f28; +assign f25 = -{feature_reg_0_2_1[11:0], 4'b0000}; +assign f26 = -{feature_reg_0_1_1[11:0], 4'b0000}; +assign f27 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f28 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA01 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[13:0], 2'b00}), + .data1x(f25), + .data2x(f26), + .data3x({feature_reg_0_4_1[13:0], 2'b00}), + .data4x(dsp_out_2_0), + .data5x(dsp_out_2_1), + .data6x(dsp_out_2_2), + .data7x(dsp_out_2_3), + .data8x(f27), + .data9x(f28), + .data10x(feature_reg_4_3_1), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_1) +); + +wire [15:0] f29, f30, f31, f32, f33, f34, f35, f36; +assign f29 = -{feature_reg_1_3_1[13:0], 2'b00}; +assign f30 = -{feature_reg_1_4_1[13:0], 2'b00}; +assign f31 = -{feature_reg_2_3_1[13:0], 2'b00}; +assign f32 = -{feature_reg_2_4_1[13:0], 2'b00}; +assign f33 = -{feature_reg_3_1_1[13:0], 2'b00}; +assign f34 = -{feature_reg_3_2_1[13:0], 2'b00}; +assign f35 = -{feature_reg_4_1_1[13:0], 2'b00}; +assign f36 = -{feature_reg_4_2_1[13:0], 2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA11 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0], 4'b0000}), + .data1x({feature_reg_1_2_1[11:0], 4'b0000}), + .data2x(f29), + .data3x(f30), + .data4x({feature_reg_2_1_1[11:0], 4'b0000}), + .data5x({feature_reg_2_2_1[11:0], 4'b0000}), + .data6x(f31), + .data7x(f32), + .data8x(f33), + .data9x(f34), + .data10x(feature_reg_3_3_1), + .data11x(feature_reg_3_4_1), + .data12x(f35), + .data13x(f36), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_1) +); + +wire [15:0] f37, f38, f39, f40, f41, f42, f43, f44; +assign f37 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f38 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f39 = -{feature_reg_2_3_1[13:0],2'b00}; +assign f40 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f41 = -feature_reg_3_3_1; +assign f42 = -feature_reg_3_4_1; +assign f43 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f44 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA21 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f37), + .data2x(f38), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[11:0],4'b0000}), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x(f39), + .data7x(f40), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(f41), + .data11x(f42), + .data12x(f43), + .data13x(f44), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_1) +); + +wire [15:0] f45, f46, f47, f48, f49, f50, f51, f52; +assign f45 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f46 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f47 = -feature_reg_2_3_1; +assign f48 = -feature_reg_2_4_1; +assign f49 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f50 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f51 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f52 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA31 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[12:0],3'b000}), + .data2x(f45), + .data3x(f46), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f47), + .data7x(f48), + .data8x(f49), + .data9x(f50), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f51), + .data13x(f52), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_1) +); + +wire [15:0] f53, f54, f55, f56, f57, f58, f59, f60; +assign f53 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f54 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f55 = -feature_reg_2_3_1; +assign f56 = -feature_reg_2_4_1; +assign f57 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f58 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f59 = -{feature_reg_4_1_1[13:0],2'b00}; +assign f60 = -{feature_reg_4_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA41 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[14:0],1'b0}), + .data1x(f53), + .data2x(f54), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[13:0],2'b00}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f55), + .data7x(f56), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x(f57), + .data11x(f58), + .data12x(f59), + .data13x(f60), + .data14x(feature_reg_4_3_1), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_1) +); + +wire [15:0] f61, f62, f63, f64; +assign f61 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f62 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f63 = -{feature_reg_5_1_1[13:0],2'b00}; +assign f64 = -{feature_reg_5_2_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA51 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f61), + .data2x(f62), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_2_4), + .data5x(dsp_out_2_5), + .data6x(dsp_out_2_6), + .data7x(dsp_out_2_7), + .data8x(f63), + .data9x(f64), + .data10x(feature_reg_5_3_1), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_1) +); + +wire [15:0] f65, f66, f67, f68; +assign f65 = -{feature_reg_0_2_1[11:0],4'b0000}; +assign f66 = -{feature_reg_0_3_1[13:0],2'b00}; +assign f67 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f68 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA02 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(f65), + .data2x(f66), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_3_0), + .data5x(dsp_out_3_1), + .data6x(dsp_out_3_2), + .data7x(dsp_out_3_3), + .data8x({feature_reg_4_1_1[13:0],2'b00}), + .data9x(f67), + .data10x(f68), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_2) +); + +wire [15:0] f69, f70, f71, f72, f73, f74, f75, f76; +assign f69 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f70 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f71 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f72 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f73 = -{feature_reg_3_2_1[13:0],2'b00}; +assign f74 = -feature_reg_3_3_1; +assign f75 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f76 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA12 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[11:0],4'b0000}), + .data1x(f69), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f70), + .data4x(f71), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f72), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f73), + .data10x(f74), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f75), + .data14x(f76), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_2) +); + +wire [15:0] f77, f78, f79, f80, f81, f82, f83, f84; +assign f77 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f78 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f79 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f80 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f81 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f82 = -feature_reg_3_4_1; +assign f83 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f84 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA22 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f77), + .data2x(f78), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f79), + .data5x({feature_reg_2_2_1[11:0],4'b0000}), + .data6x({feature_reg_2_3_1[13:0],2'b00}), + .data7x(f80), + .data8x(f81), + .data9x({feature_reg_3_2_1[13:0],2'b00}), + .data10x(feature_reg_3_3_1), + .data11x(f82), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f83), + .data14x(f84), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_2) +); + +wire [15:0] f85, f86, f87, f88, f89, f90, f91, f92; +assign f85 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f86 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f87 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f88 = -feature_reg_2_4_1; +assign f89 = -{feature_reg_3_2_1[12:0],3'b000}; +assign f90 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f91 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f92 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA32 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[12:0],3'b000}), + .data1x(f85), + .data2x({feature_reg_1_3_1[14:0],1'b0}), + .data3x(f86), + .data4x(f87), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f88), + .data8x({feature_reg_3_1_1[12:0],3'b000}), + .data9x(f89), + .data10x(f90), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f91), + .data14x(f92), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_2) +); + +wire [15:0] f93, f94, f95, f96, f97, f98, f99, f100; +assign f93 = -{feature_reg_1_2_1[12:0],3'b000}; +assign f94 = -{feature_reg_1_3_1[14:0],1'b0}; +assign f95 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f96 = -feature_reg_2_4_1; +assign f97 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f98 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f99 = -{feature_reg_4_2_1[13:0],2'b00}; +assign f100 = -feature_reg_4_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA42 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f93), + .data2x(f94), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f95), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(feature_reg_2_3_1), + .data7x(f96), + .data8x(f97), + .data9x({feature_reg_3_2_1[12:0],3'b000}), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f98), + .data12x({feature_reg_4_1_1[13:0],2'b00}), + .data13x(f99), + .data14x(f100), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_2) +); + +wire [15:0] f101, f102, f103, f104; +assign f101 = -{feature_reg_1_2_1[11:0],4'b0000}; +assign f102 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f103 = -{feature_reg_5_2_1[13:0],2'b00}; +assign f104 = -feature_reg_5_3_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA52 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f101), + .data2x(f102), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_3_4), + .data5x(dsp_out_3_5), + .data6x(dsp_out_3_6), + .data7x(dsp_out_3_7), + .data8x({feature_reg_5_1_1[13:0],2'b00}), + .data9x(f103), + .data10x(f104), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_2) +); + +wire [15:0] f105, f106, f107, f108; +assign f105 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f106 = -{feature_reg_0_1_1[12:0],3'b000}; +assign f107 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f108 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA03 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_3_1[12:0],3'b000}), + .data1x(f105), + .data2x(f106), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_4_0), + .data5x(dsp_out_4_1), + .data6x(dsp_out_4_2), + .data7x(dsp_out_4_3), + .data8x(f107), + .data9x(f108), + .data10x({feature_reg_4_3_1[14:0],1'b0}), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_3) +); + +wire [15:0] f109, f110, f111, f112, f113, f114, f115, f116; +assign f109 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f110 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f111 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f112 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f113 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f114 = -feature_reg_3_2_1; +assign f115 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f116 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA13 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x({feature_reg_1_2_1[13:0],2'b00}), + .data2x(f109), + .data3x(f110), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f111), + .data7x(f112), + .data8x(f113), + .data9x(f114), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(feature_reg_3_4_1), + .data12x(f115), + .data13x(f116), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_3) +); + +wire [15:0] f117, f118, f119, f120, f121, f122, f123, f124; +assign f117 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f118 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f119 = -{feature_reg_2_3_1[12:0],3'b000}; +assign f120 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f121 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f122 = -feature_reg_3_4_1; +assign f123 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f124 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA23 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f117), + .data2x(f118), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x({feature_reg_2_1_1[12:0],3'b000}), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x(f119), + .data7x(f120), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(feature_reg_3_2_1), + .data10x(f121), + .data11x(f122), + .data12x(f123), + .data13x(f124), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_3) +); + +wire [15:0] f125, f126, f127, f128, f129, f130, f131, f132; +assign f125 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f126 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f127 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f128 = -feature_reg_2_4_1; +assign f129 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f130 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f131 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f132 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA33 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x({feature_reg_1_2_1[14:0],1'b0}), + .data2x(f125), + .data3x(f126), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f127), + .data7x(f128), + .data8x(f129), + .data9x(f130), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x(f131), + .data13x(f132), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_3) +); + +wire [15:0] f133, f134, f135, f136, f137, f138, f139, f140; +assign f133 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f134 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f135 = -{feature_reg_2_3_1[14:0],1'b0}; +assign f136 = -feature_reg_2_4_1; +assign f137 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f138 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f139 = -{feature_reg_4_1_1[14:0],1'b0}; +assign f140 = -feature_reg_4_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA43 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[13:0],2'b00}), + .data1x(f133), + .data2x(f134), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x({feature_reg_2_1_1[14:0],1'b0}), + .data5x(feature_reg_2_2_1), + .data6x(f135), + .data7x(f136), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x(f137), + .data11x(f138), + .data12x(f139), + .data13x(f140), + .data14x({feature_reg_4_3_1[14:0],1'b0}), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_3) +); + +wire [15:0] f141, f142, f143, f144; +assign f141 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f142 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f143 = -{feature_reg_5_1_1[14:0],1'b0}; +assign f144 = -feature_reg_5_2_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA53 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_3_1[12:0],3'b000}), + .data1x(f141), + .data2x(f142), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_4_4), + .data5x(dsp_out_4_5), + .data6x(dsp_out_4_6), + .data7x(dsp_out_4_7), + .data8x(f143), + .data9x(f144), + .data10x({feature_reg_5_3_1[14:0],1'b0}), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_3) +); + +wire [15:0] f145, f146, f147, f148; +assign f145 = -{feature_reg_0_2_1[13:0],2'b00}; +assign f146 = -{feature_reg_0_3_1[12:0],3'b000}; +assign f147 = -feature_reg_4_2_1; +assign f148 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA04 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[12:0],3'b000}), + .data1x(f145), + .data2x(f146), + .data3x({feature_reg_0_4_1[13:0],2'b00}), + .data4x(dsp_out_5_0), + .data5x(dsp_out_5_1), + .data6x(dsp_out_5_2), + .data7x(dsp_out_5_3), + .data8x({feature_reg_4_1_1[14:0],1'b0}), + .data9x(f147), + .data10x(f148), + .data11x(feature_reg_4_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_4) +); + +wire [15:0] f149, f150, f151, f152, f153, f154, f155, f156; +assign f149 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f150 = -{feature_reg_1_4_1[13:0],2'b00}; +assign f151 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f152 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f153 = -feature_reg_3_2_1; +assign f154 = -{feature_reg_3_3_1[14:0],1'b0}; +assign f155 = -feature_reg_4_2_1; +assign f156 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA14 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[13:0],2'b00}), + .data1x(f149), + .data2x({feature_reg_1_3_1[12:0],3'b000}), + .data3x(f150), + .data4x(f151), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f152), + .data8x({feature_reg_3_1_1[14:0],1'b0}), + .data9x(f153), + .data10x(f154), + .data11x(feature_reg_3_4_1), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f155), + .data14x(f156), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_1_4) +); + +wire [15:0] f157, f158, f159, f160, f161, f162, f163, f164; +assign f157 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f158 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f159 = -{feature_reg_2_1_1[12:0],3'b000}; +assign f160 = -{feature_reg_2_4_1[13:0],2'b00}; +assign f161 = -{feature_reg_3_1_1[14:0],1'b0}; +assign f162 = -feature_reg_3_4_1; +assign f163 = -feature_reg_4_2_1; +assign f164 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA24 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f157), + .data2x(f158), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(f159), + .data5x({feature_reg_2_2_1[13:0],2'b00}), + .data6x({feature_reg_2_3_1[12:0],3'b000}), + .data7x(f160), + .data8x(f161), + .data9x(feature_reg_3_2_1), + .data10x({feature_reg_3_3_1[14:0],1'b0}), + .data11x(f162), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f163), + .data14x(f164), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_2_4) +); + +wire [15:0] f165, f166, f167, f168, f169, f170, f171, f172; +assign f165 = -{feature_reg_1_1_1[13:0],2'b00}; +assign f166 = -{feature_reg_1_4_1[14:0],1'b0}; +assign f167 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f168 = -feature_reg_2_4_1; +assign f169 = -{feature_reg_3_2_1[14:0],1'b0}; +assign f170 = -{feature_reg_3_3_1[13:0],2'b00}; +assign f171 = -feature_reg_4_2_1; +assign f172 = -{feature_reg_4_1_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA34 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_2_1[14:0],1'b0}), + .data1x(f165), + .data2x({feature_reg_1_3_1[13:0],2'b00}), + .data3x(f166), + .data4x(f167), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f168), + .data8x({feature_reg_3_1_1[13:0],2'b00}), + .data9x(f169), + .data10x(f170), + .data11x({feature_reg_3_4_1[14:0],1'b0}), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f171), + .data14x(f172), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_3_4) +); + +wire [15:0] f173, f174, f175, f176, f177, f178, f179, f180; +assign f173 = -{feature_reg_1_2_1[14:0],1'b0}; +assign f174 = -{feature_reg_1_3_1[13:0],2'b00}; +assign f175 = -{feature_reg_2_1_1[14:0],1'b0}; +assign f176 = -feature_reg_2_4_1; +assign f177 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f178 = -{feature_reg_3_4_1[14:0],1'b0}; +assign f179 = -feature_reg_4_2_1; +assign f180 = -{feature_reg_4_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA44 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[13:0],2'b00}), + .data1x(f173), + .data2x(f174), + .data3x({feature_reg_1_4_1[14:0],1'b0}), + .data4x(f175), + .data5x(feature_reg_2_2_1), + .data6x({feature_reg_2_3_1[14:0],1'b0}), + .data7x(f176), + .data8x(f177), + .data9x({feature_reg_3_2_1[14:0],1'b0}), + .data10x({feature_reg_3_3_1[13:0],2'b00}), + .data11x(f178), + .data12x({feature_reg_4_1_1[14:0],1'b0}), + .data13x(f179), + .data14x(f180), + .data15x(feature_reg_4_4_1), + .result(rslt_buffer_4_4) +); + +wire [15:0] f181, f182, f183, f184; +assign f181 = -{feature_reg_1_2_1[13:0],2'b00}; +assign f182 = -{feature_reg_1_3_1[12:0],3'b000}; +assign f183 = -feature_reg_5_2_1; +assign f184 = -{feature_reg_5_3_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA54 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f181), + .data2x(f182), + .data3x({feature_reg_1_4_1[13:0],2'b00}), + .data4x(dsp_out_5_4), + .data5x(dsp_out_5_5), + .data6x(dsp_out_5_6), + .data7x(dsp_out_5_7), + .data8x({feature_reg_5_1_1[14:0],1'b0}), + .data9x(f183), + .data10x(f184), + .data11x(feature_reg_5_4_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_4) +); + +winograd_adder_16_20_4 winograd_adder_16_20_4_WA05 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_0_1_1[11:0],4'b0000}), + .data1x(dsp_out_6_0), + .data2x({feature_reg_0_5_1[13:0],2'b00}), + .data3x(dsp_out_6_1), + .data4x(dsp_out_6_2), + .data5x(dsp_out_6_3), + .data6x({feature_reg_4_1_1[13:0],2'b00}), + .data7x(dsp_out_6_4), + .data8x(feature_reg_4_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_0_5) +); + +wire [15:0] f185, f186, f187, f188; +assign f185 = -{feature_reg_1_1_1[11:0],4'b0000}; +assign f186 = -{feature_reg_1_5_1[13:0],2'b00}; +assign f187 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f188 = -{feature_reg_2_5_1[13:0],2'b00}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA15 ( + .clock(clk), + .clken(calculate_2), + .data0x(dsp_out_6_5), + .data1x(f185), + .data2x(f186), + .data3x(f187), + .data4x(dsp_out_6_6), + .data5x(f188), + .data6x({feature_reg_3_1_1[13:0],2'b00}), + .data7x(dsp_out_6_7), + .data8x(feature_reg_3_5_1), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_1_5) +); + +wire [15:0] f189, f190, f191, f192, f193, f194; +assign f189 = -dsp_out_6_5; +assign f190 = -{feature_reg_2_1_1[11:0],4'b0000}; +assign f191 = -{feature_reg_2_5_1[13:0],2'b00}; +assign f192 = -{feature_reg_3_1_1[13:0],2'b00}; +assign f193 = -dsp_out_6_7; +assign f194 = -feature_reg_3_5_1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA25 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f189), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(f190), + .data4x(dsp_out_6_6), + .data5x(f191), + .data6x(f192), + .data7x(f193), + .data8x(f194), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_2_5) +); + +wire [15:0] f195, f196, f197, f198, f199, f200, f201; +assign f195 = dsp_out_6_5 >>> 1; +assign f196 = -{feature_reg_1_1_1[12:0],3'b000}; +assign f197 = -{feature_reg_1_5_1[14:0],1'b0}; +assign f198 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f199 = dsp_out_6_6 >>> 2; +assign f200 = -feature_reg_2_5_1; +assign f201 = dsp_out_6_7 <<< 1; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA35 ( + .clock(clk), + .clken(calculate_2), + .data0x(f195), + .data1x(f196), + .data2x(f197), + .data3x(f198), + .data4x(f199), + .data5x(f200), + .data6x({feature_reg_3_1_1[12:0],3'b000}), + .data7x(f201), + .data8x({feature_reg_3_5_1[14:0],1'b0}), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_3_5) +); + +wire [15:0] f202, f203, f204, f205, f206, f207, f208; +assign f202 = -(dsp_out_6_5 >>> 1); +assign f203 = -{feature_reg_2_1_1[13:0],2'b00}; +assign f204 = dsp_out_6_6 >>> 2; +assign f205 = -feature_reg_2_5_1; +assign f206 = -{feature_reg_3_1_1[12:0],3'b000}; +assign f207 = -(dsp_out_6_7 <<< 1); +assign f208 = -{feature_reg_3_5_1[14:0],1'b0}; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA45 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[12:0],3'b000}), + .data1x(f202), + .data2x({feature_reg_1_5_1[14:0],1'b0}), + .data3x(f203), + .data4x(f204), + .data5x(f205), + .data6x(f206), + .data7x(f207), + .data8x(f208), + .data9x({feature_reg_4_1_1[13:0],2'b00}), + .data10x(dsp_out_6_4), + .data11x(feature_reg_4_5_1), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_4_5) +); + +wire [15:0] f209; +assign f209 = -dsp_out_6_5; +winograd_adder_16_20_4 winograd_adder_16_20_4_WA55 ( + .clock(clk), + .clken(calculate_2), + .data0x({feature_reg_1_1_1[11:0],4'b0000}), + .data1x(f209), + .data2x({feature_reg_1_5_1[13:0],2'b00}), + .data3x(dsp_out_6_8), + .data4x(dsp_out_6_9), + .data5x(dsp_out_6_10), + .data6x({feature_reg_5_1_1[13:0],2'b00}), + .data7x(dsp_out_6_11), + .data8x(feature_reg_5_5_1), + .data9x(0), + .data10x(0), + .data11x(0), + .data12x(0), + .data13x(0), + .data14x(0), + .data15x(0), + .result(rslt_buffer_5_5) +); + +assign o_feature_0 = output_buffer_0_0[15:0]; +assign o_feature_1 = output_buffer_1_0[15:0]; +assign o_feature_2 = output_buffer_2_0[15:0]; +assign o_feature_3 = output_buffer_3_0[15:0]; +assign o_feature_4 = output_buffer_4_0[15:0]; +assign o_feature_5 = output_buffer_5_0[15:0]; +assign o_valid = valid_9; + +endmodule + +module stream_buffer_5_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [14:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [14:0] base_addr; +reg [14:0] offset; +reg [14:0] base_addr_b1; +reg [14:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 1) && (L_counter == 2)) begin + base_addr <= base_addr + 5; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 2) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 2; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= base_addr_b1 + 5; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 2) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 2; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [14:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_24200_buffer_init_15 buffer_16_24200_buffer_init_15_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_24200_buffer_init_15 buffer_16_24200_buffer_init_15_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_24200_buffer_init_15 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_5_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [14:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [14:0] base_addr; +reg [14:0] offset; +reg [14:0] base_addr_b1; +reg [14:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 1) && (L_counter == 2)) begin + base_addr <= base_addr + 5; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 2) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 2; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= base_addr_b1 + 5; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 2) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 2; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [14:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_24200_buffer_init_05 buffer_16_24200_buffer_init_05_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_24200_buffer_init_05 buffer_16_24200_buffer_init_05_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_24200_buffer_init_05 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module processing_element ( + input clk, + input i_reset, + input i_valid, + input [15:0] i_features_0_0, + output [15:0] o_features_0_0, + input [15:0] i_features_0_1, + output [15:0] o_features_0_1, + input [15:0] i_features_0_2, + output [15:0] o_features_0_2, + input [15:0] i_features_0_3, + output [15:0] o_features_0_3, + input [15:0] i_features_0_4, + output [15:0] o_features_0_4, + input [15:0] i_features_0_5, + output [15:0] o_features_0_5, + input [15:0] i_features_1_0, + output [15:0] o_features_1_0, + input [15:0] i_features_1_1, + output [15:0] o_features_1_1, + input [15:0] i_features_1_2, + output [15:0] o_features_1_2, + input [15:0] i_features_1_3, + output [15:0] o_features_1_3, + input [15:0] i_features_1_4, + output [15:0] o_features_1_4, + input [15:0] i_features_1_5, + output [15:0] o_features_1_5, + output [29:0] o_result_0, + output [29:0] o_result_1, + output [29:0] o_result_2, + output [29:0] o_result_3, + output [29:0] o_result_4, + output [29:0] o_result_5, + output o_valid, + output o_next_reset, + output o_next_valid +); + +wire [23:0] DP_res_0; +reg [15:0] if_reg_0_0; +wire [7:0] weights_0_0; +reg [15:0] if_reg_0_1; +wire [7:0] weights_0_1; +wire [23:0] DP_res_1; +reg [15:0] if_reg_1_0; +wire [7:0] weights_1_0; +reg [15:0] if_reg_1_1; +wire [7:0] weights_1_1; +wire [23:0] DP_res_2; +reg [15:0] if_reg_2_0; +wire [7:0] weights_2_0; +reg [15:0] if_reg_2_1; +wire [7:0] weights_2_1; +wire [23:0] DP_res_3; +reg [15:0] if_reg_3_0; +wire [7:0] weights_3_0; +reg [15:0] if_reg_3_1; +wire [7:0] weights_3_1; +wire [23:0] DP_res_4; +reg [15:0] if_reg_4_0; +wire [7:0] weights_4_0; +reg [15:0] if_reg_4_1; +wire [7:0] weights_4_1; +wire [23:0] DP_res_5; +reg [15:0] if_reg_5_0; +wire [7:0] weights_5_0; +reg [15:0] if_reg_5_1; +wire [7:0] weights_5_1; + +reg [10:0] base_addr; +reg [10:0] offset; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [15:0] T_counter; + +reg reset_1, reset_2, reset_3, next_reset, next_reset_2; +reg done, done_1, done_2, done_3, done_4, done_5, done_6; + +wire [15:0] features_0_0; +wire [15:0] features_0_1; +wire [15:0] features_1_0; +wire [15:0] features_1_1; +wire [15:0] features_2_0; +wire [15:0] features_2_1; +wire [15:0] features_3_0; +wire [15:0] features_3_1; +wire [15:0] features_4_0; +wire [15:0] features_4_1; +wire [15:0] features_5_0; +wire [15:0] features_5_1; +reg valid_0; +reg valid_1; +reg valid_2; +reg valid_3; +reg valid_4; +reg valid_5; +reg valid_6; +reg valid_7; +reg valid_8; +reg valid_9; +reg valid_10; +reg valid_11; +reg next_valid; + +always @ (posedge clk) begin + reset_1 <= ~(i_valid || valid_11); + reset_2 <= reset_1; + reset_3 <= reset_2; + next_reset <= i_reset; + next_reset_2 <= next_reset; + if (i_reset == 1'b0) begin + if_reg_0_0 <= features_0_0; + if_reg_0_1 <= features_0_1; + if_reg_1_0 <= features_1_0; + if_reg_1_1 <= features_1_1; + if_reg_2_0 <= features_2_0; + if_reg_2_1 <= features_2_1; + if_reg_3_0 <= features_3_0; + if_reg_3_1 <= features_3_1; + if_reg_4_0 <= features_4_0; + if_reg_4_1 <= features_4_1; + if_reg_5_0 <= features_5_0; + if_reg_5_1 <= features_5_1; + end +end + +always @ (posedge clk) begin + next_valid <= i_valid; + if (i_reset) begin + valid_0 <= 0; + valid_1 <= 0; + valid_2 <= 0; + valid_3 <= 0; + valid_4 <= 0; + valid_5 <= 0; + valid_6 <= 0; + valid_7 <= 0; + valid_8 <= 0; + valid_9 <= 0; + valid_10 <= 0; + valid_11 <= 0; + end else if ((i_valid == 1'b0) && (valid_11 == 1'b0)) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + T_counter <= 0; + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + done_4 <= 0; + done_5 <= 0; + done_6 <= 0; + end else if (i_valid || valid_11) begin + valid_0 <= i_valid; + valid_1 <= valid_0; + valid_2 <= valid_1; + valid_3 <= valid_2; + valid_4 <= valid_3; + valid_5 <= valid_4; + valid_6 <= valid_5; + valid_7 <= valid_6; + valid_8 <= valid_7; + valid_9 <= valid_8; + valid_10 <= valid_9; + valid_11 <= valid_10; + if (T_counter <= 1809025) begin + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + done_4 <= done_3; + done_5 <= done_4; + done_6 <= done_5; + if((C_counter == 0) && (L_counter == 2)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + done <= 1; + T_counter <= T_counter + 1'b1; + end else if(L_counter == 2) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + done <= 0; + end else begin + offset <= offset + 1; + L_counter <= L_counter + 1'b1; + end + end + end +end + +dot_product_16_8_30_2 dot_product_16_8_30_2_inst_0 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_0_0), + .i_weights_0(weights_0_0), + .i_features_1(features_0_1), + .i_weights_1(weights_0_1), + .o_result(DP_res_0) +); + +dot_product_16_8_30_2 dot_product_16_8_30_2_inst_1 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_1_0), + .i_weights_0(weights_1_0), + .i_features_1(features_1_1), + .i_weights_1(weights_1_1), + .o_result(DP_res_1) +); + +dot_product_16_8_30_2 dot_product_16_8_30_2_inst_2 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_2_0), + .i_weights_0(weights_2_0), + .i_features_1(features_2_1), + .i_weights_1(weights_2_1), + .o_result(DP_res_2) +); + +dot_product_16_8_30_2 dot_product_16_8_30_2_inst_3 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_3_0), + .i_weights_0(weights_3_0), + .i_features_1(features_3_1), + .i_weights_1(weights_3_1), + .o_result(DP_res_3) +); + +dot_product_16_8_30_2 dot_product_16_8_30_2_inst_4 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_4_0), + .i_weights_0(weights_4_0), + .i_features_1(features_4_1), + .i_weights_1(weights_4_1), + .o_result(DP_res_4) +); + +dot_product_16_8_30_2 dot_product_16_8_30_2_inst_5 ( + .clk(clk), + .i_reset(reset_3), + .i_features_0(features_5_0), + .i_weights_0(weights_5_0), + .i_features_1(features_5_1), + .i_weights_1(weights_5_1), + .o_result(DP_res_5) +); + +accumulator_24_30_3 accumulator_24_30_3_inst_0 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_0), + .i_dp_done(done_5), + .o_accum(o_result_0) +); + +accumulator_24_30_3 accumulator_24_30_3_inst_1 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_1), + .i_dp_done(done_5), + .o_accum(o_result_1) +); + +accumulator_24_30_3 accumulator_24_30_3_inst_2 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_2), + .i_dp_done(done_5), + .o_accum(o_result_2) +); + +accumulator_24_30_3 accumulator_24_30_3_inst_3 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_3), + .i_dp_done(done_5), + .o_accum(o_result_3) +); + +accumulator_24_30_3 accumulator_24_30_3_inst_4 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_4), + .i_dp_done(done_5), + .o_accum(o_result_4) +); + +accumulator_24_30_3 accumulator_24_30_3_inst_5 ( + .clk(clk), + .i_reset(reset_3), + .i_result(DP_res_5), + .i_dp_done(done_5), + .o_accum(o_result_5) +); + +reg [9:0] weight_cache_addr; +always @ (*) begin + weight_cache_addr <= base_addr+offset; +end +weight_cache_2048_8_0_weight_init_00 weight_cache_2048_8_0_weight_init_00_inst_0_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_0_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_0_1) +); + +weight_cache_2048_8_0_weight_init_01 weight_cache_2048_8_0_weight_init_01_inst_1_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_1_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_1_1) +); + +weight_cache_2048_8_0_weight_init_02 weight_cache_2048_8_0_weight_init_02_inst_2_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_2_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_2_1) +); + +weight_cache_2048_8_0_weight_init_03 weight_cache_2048_8_0_weight_init_03_inst_3_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_3_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_3_1) +); + +weight_cache_2048_8_0_weight_init_04 weight_cache_2048_8_0_weight_init_04_inst_4_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_4_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_4_1) +); + +weight_cache_2048_8_0_weight_init_05 weight_cache_2048_8_0_weight_init_05_inst_5_0 ( + .clk(clk), + .wen0(1'b0), + .wen1(1'b0), + .addr0(weight_cache_addr), + .wdata0(8'd0), + .data0(weights_5_0), + .addr1(weight_cache_addr), + .wdata1(8'd0), + .data1(weights_5_1) +); + +assign o_features_0_0 = if_reg_0_0; +assign features_0_0 = i_features_0_0; +assign o_features_1_0 = if_reg_0_1; +assign features_0_1 = i_features_1_0; +assign o_features_0_1 = if_reg_1_0; +assign features_1_0 = i_features_0_1; +assign o_features_1_1 = if_reg_1_1; +assign features_1_1 = i_features_1_1; +assign o_features_0_2 = if_reg_2_0; +assign features_2_0 = i_features_0_2; +assign o_features_1_2 = if_reg_2_1; +assign features_2_1 = i_features_1_2; +assign o_features_0_3 = if_reg_3_0; +assign features_3_0 = i_features_0_3; +assign o_features_1_3 = if_reg_3_1; +assign features_3_1 = i_features_1_3; +assign o_features_0_4 = if_reg_4_0; +assign features_4_0 = i_features_0_4; +assign o_features_1_4 = if_reg_4_1; +assign features_4_1 = i_features_1_4; +assign o_features_0_5 = if_reg_5_0; +assign features_5_0 = i_features_0_5; +assign o_features_1_5 = if_reg_5_1; +assign features_5_1 = i_features_1_5; + +assign o_valid = done_6; +assign o_next_reset = next_reset; +assign o_next_valid = next_valid; + +endmodule + +module dot_product_16_8_30_2 ( + input clk, + input i_reset, + input [15:0] i_features_0, + input [7:0] i_weights_0, + input [15:0] i_features_1, + input [7:0] i_weights_1, + output [23:0] o_result +); + +wire [63:0] chains_0; +wire [23:0] res; +reg [15:0] f_pipeline_0_0; +reg [7:0] w_pipeline_0_0; +reg [15:0] f_pipeline_1_0; +reg [7:0] w_pipeline_1_0; +reg r_pipeline_0; + +always @ (posedge clk) begin + r_pipeline_0 <= i_reset; + if(i_reset == 1'b1) begin + f_pipeline_0_0 <= 0; + w_pipeline_0_0 <= 0; + f_pipeline_1_0 <= 0; + w_pipeline_1_0 <= 0; + end else begin + f_pipeline_0_0 <= i_features_0; + w_pipeline_0_0 <= i_weights_0; + f_pipeline_1_0 <= i_features_1; + w_pipeline_1_0 <= i_weights_1; + end +end + +dsp_block_16_8_false dsp_block_16_8_false_inst_0 ( + .clk(clk), + .ena(1'b1), + .aclr(r_pipeline_0), + .ax(f_pipeline_0_0), + .ay(w_pipeline_0_0), + .bx(f_pipeline_1_0), + .by(w_pipeline_1_0), + .chainin(64'd0), + .chainout(chains_0), + .resulta(res) +); + +assign o_result = res; + +endmodule + +module dsp_block_16_8_false ( + input clk, + input ena, + input aclr, + input [15:0] ax, + input [7:0] ay, + input [15:0] bx, + input [7:0] by, + input [63:0] chainin, + output [63:0] chainout, + output [23:0] resulta +); + +wire [11:0] mode; +assign mode = 12'b1010_1010_0110; + +`ifdef complex_dsp +int_sop_2 mac_component ( + .mode_sigs(mode), + .clk(clk), + .reset(aclr), + .ax(ax), + .ay(ay), + .bx(bx), + .by(by), + .chainin(chainin), + .result(resulta), + .chainout(chainout) +); + +`else +reg [15:0] ax_reg; +reg [7:0] ay_reg; +reg [15:0] bx_reg; +reg [7:0] by_reg; +reg [23:0] resulta_tmp; +always @(posedge clk) begin + if(aclr) begin + resulta_tmp <= 0; + ax_reg <= 0; + ay_reg <= 0; + bx_reg <= 0; + by_reg <= 0; + end + else begin + ax_reg <= ax; + ay_reg <= ay; + bx_reg <= bx; + by_reg <= by; + resulta_tmp <= ax_reg * ay_reg + bx_reg * by_reg + chainin; + end +end +assign resulta = resulta_tmp; +assign chainout = {40'b0, resulta_tmp}; +`endif + +endmodule + +module weight_cache_2048_8_0_weight_init_05 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_03 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_02 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_01 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module weight_cache_2048_8_0_weight_init_00 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module accumulator_24_30_3 ( + input clk, + input i_reset, + input [23:0] i_result, + input i_dp_done, + output [29:0] o_accum +); + +reg [29:0] cir_shift_reg_0; +reg [29:0] cir_shift_reg_1; +reg [29:0] cir_shift_reg_2; +reg [29:0] out_reg; +reg [29:0] in_reg; + +always @ (posedge clk) begin + if(i_reset == 1'b1) begin + cir_shift_reg_0 <= 0; + cir_shift_reg_1 <= 0; + cir_shift_reg_2 <= 0; + out_reg <= 0; + in_reg <= 0; + end else begin + if (i_result[23] == 1'b0) begin + in_reg <= {6'b000000, i_result}; + end else begin + in_reg <= {6'b111111, i_result}; + end + if(i_dp_done == 1'b1) begin + out_reg <= (cir_shift_reg_0 + in_reg); + cir_shift_reg_2 <= 0; + end else begin + cir_shift_reg_2 <= (cir_shift_reg_0 + in_reg); + end + cir_shift_reg_0 <= cir_shift_reg_1; + cir_shift_reg_1 <= cir_shift_reg_2; + end +end + +assign o_accum = out_reg; + +endmodule + +module weight_cache_2048_8_0_weight_init_04 ( + input clk, + input wen0, + input wen1, + input [9:0] addr0, + input [7:0] wdata0, + output [7:0] data0, + input [9:0] addr1, + input [7:0] wdata1, + output [7:0] data1 +); + +reg [9:0] addr0_reg; +wire [7:0] data0_reg; +reg [9:0] addr1_reg; +wire [7:0] data1_reg; +reg [7:0] pipeline0_reg_0; +reg [7:0] pipeline1_reg_0; +always @(posedge clk) begin + addr0_reg <= addr0; + addr1_reg <= addr1; + pipeline0_reg_0 <= data0_reg; + pipeline1_reg_0 <= data1_reg; +end + +dpram #(.AWIDTH(10),.DWIDTH(8),.NUM_WORDS(1<<10)) u_dpram( + .addr1(addr0_reg), + .we1(wen0), + .data1(wdata0), + .out1(data0_reg), + .addr2(addr1_reg), + .we2(wen1), + .data2(wdata1), + .out2(data1_reg), + .clk(clk) +); + +assign data0 = pipeline0_reg_0; +assign data1 = pipeline1_reg_0; + +endmodule + +module stream_buffer_4_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [14:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [14:0] base_addr; +reg [14:0] offset; +reg [14:0] base_addr_b1; +reg [14:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 1) && (L_counter == 2)) begin + base_addr <= base_addr + 5; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 2) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 2; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= base_addr_b1 + 5; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 2) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 2; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [14:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_24200_buffer_init_04 buffer_16_24200_buffer_init_04_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_24200_buffer_init_04 buffer_16_24200_buffer_init_04_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_24200_buffer_init_04 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_4_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [14:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [14:0] base_addr; +reg [14:0] offset; +reg [14:0] base_addr_b1; +reg [14:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 1) && (L_counter == 2)) begin + base_addr <= base_addr + 5; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 2) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 2; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= base_addr_b1 + 5; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 2) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 2; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [14:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_24200_buffer_init_14 buffer_16_24200_buffer_init_14_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_24200_buffer_init_14 buffer_16_24200_buffer_init_14_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_24200_buffer_init_14 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_2_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [14:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [14:0] base_addr; +reg [14:0] offset; +reg [14:0] base_addr_b1; +reg [14:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 1) && (L_counter == 2)) begin + base_addr <= base_addr + 5; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 2) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 2; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= base_addr_b1 + 5; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 2) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 2; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [14:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_24200_buffer_init_02 buffer_16_24200_buffer_init_02_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_24200_buffer_init_02 buffer_16_24200_buffer_init_02_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_24200_buffer_init_02 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_2_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [14:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [14:0] base_addr; +reg [14:0] offset; +reg [14:0] base_addr_b1; +reg [14:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 1) && (L_counter == 2)) begin + base_addr <= base_addr + 5; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 2) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 2; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= base_addr_b1 + 5; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 2) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 2; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [14:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_24200_buffer_init_12 buffer_16_24200_buffer_init_12_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_24200_buffer_init_12 buffer_16_24200_buffer_init_12_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_24200_buffer_init_12 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_1_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [14:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [14:0] base_addr; +reg [14:0] offset; +reg [14:0] base_addr_b1; +reg [14:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 1) && (L_counter == 2)) begin + base_addr <= base_addr + 5; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 2) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 2; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= base_addr_b1 + 5; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 2) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 2; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [14:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_24200_buffer_init_11 buffer_16_24200_buffer_init_11_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_24200_buffer_init_11 buffer_16_24200_buffer_init_11_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_24200_buffer_init_11 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_1_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [14:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [14:0] base_addr; +reg [14:0] offset; +reg [14:0] base_addr_b1; +reg [14:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 1) && (L_counter == 2)) begin + base_addr <= base_addr + 5; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 2) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 2; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= base_addr_b1 + 5; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 2) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 2; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [14:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_24200_buffer_init_01 buffer_16_24200_buffer_init_01_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_24200_buffer_init_01 buffer_16_24200_buffer_init_01_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_24200_buffer_init_01 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_0_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [14:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [14:0] base_addr; +reg [14:0] offset; +reg [14:0] base_addr_b1; +reg [14:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 1) && (L_counter == 2)) begin + base_addr <= base_addr + 5; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 2) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 2; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= base_addr_b1 + 5; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 2) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 2; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [14:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_24200_buffer_init_00 buffer_16_24200_buffer_init_00_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_24200_buffer_init_00 buffer_16_24200_buffer_init_00_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_24200_buffer_init_00 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [12:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_0_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [14:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [14:0] base_addr; +reg [14:0] offset; +reg [14:0] base_addr_b1; +reg [14:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 1) && (L_counter == 2)) begin + base_addr <= base_addr + 5; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 2) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 2; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= base_addr_b1 + 5; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 2) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 2; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [14:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_24200_buffer_init_10 buffer_16_24200_buffer_init_10_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_24200_buffer_init_10 buffer_16_24200_buffer_init_10_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_24200_buffer_init_10 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module signal_width_reducer ( + input clk, + input [15:0] signals_0_0, + output reduced_signals_0_0, + input [15:0] signals_0_1, + output reduced_signals_0_1, + input [15:0] signals_1_0, + output reduced_signals_1_0, + input [15:0] signals_1_1, + output reduced_signals_1_1, + input [15:0] signals_2_0, + output reduced_signals_2_0, + input [15:0] signals_2_1, + output reduced_signals_2_1, + input [15:0] signals_3_0, + output reduced_signals_3_0, + input [15:0] signals_3_1, + output reduced_signals_3_1, + input [15:0] signals_4_0, + output reduced_signals_4_0, + input [15:0] signals_4_1, + output reduced_signals_4_1, + input [15:0] signals_5_0, + output reduced_signals_5_0, + input [15:0] signals_5_1, + output reduced_signals_5_1, + input reset +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_0_0 ( + .clk(clk), + .reset(reset), + .signal(signals_0_0), + .reduced_signal(reduced_signals_0_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_0_1 ( + .clk(clk), + .reset(reset), + .signal(signals_0_1), + .reduced_signal(reduced_signals_0_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_1_0 ( + .clk(clk), + .reset(reset), + .signal(signals_1_0), + .reduced_signal(reduced_signals_1_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_1_1 ( + .clk(clk), + .reset(reset), + .signal(signals_1_1), + .reduced_signal(reduced_signals_1_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_2_0 ( + .clk(clk), + .reset(reset), + .signal(signals_2_0), + .reduced_signal(reduced_signals_2_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_2_1 ( + .clk(clk), + .reset(reset), + .signal(signals_2_1), + .reduced_signal(reduced_signals_2_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_3_0 ( + .clk(clk), + .reset(reset), + .signal(signals_3_0), + .reduced_signal(reduced_signals_3_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_3_1 ( + .clk(clk), + .reset(reset), + .signal(signals_3_1), + .reduced_signal(reduced_signals_3_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_4_0 ( + .clk(clk), + .reset(reset), + .signal(signals_4_0), + .reduced_signal(reduced_signals_4_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_4_1 ( + .clk(clk), + .reset(reset), + .signal(signals_4_1), + .reduced_signal(reduced_signals_4_1) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_5_0 ( + .clk(clk), + .reset(reset), + .signal(signals_5_0), + .reduced_signal(reduced_signals_5_0) +); + +pipelined_xor_tree_16 pipelined_xor_tree_16_inst_5_1 ( + .clk(clk), + .reset(reset), + .signal(signals_5_1), + .reduced_signal(reduced_signals_5_1) +); + +endmodule + +module pipelined_xor_tree_16 ( + input clk, + input reset, + input [15:0] signal, + output reduced_signal +); + +reg pipeline_0_0; +reg pipeline_0_1; +reg pipeline_0_2; +reg pipeline_1_0; +reg pipeline_1_1; +reg pipeline_1_2; +reg pipeline_2_0; +reg pipeline_2_1; +reg pipeline_2_2; +reg pipeline_3_0; +reg pipeline_3_1; +reg pipeline_3_2; +reg pipeline_4_0; +reg pipeline_4_1; +reg pipeline_4_2; +reg pipeline_5_0; +reg pipeline_5_1; +reg pipeline_5_2; +reg pipeline_6_0; +reg pipeline_6_1; +reg pipeline_6_2; +reg pipeline_7_0; +reg pipeline_7_1; +reg pipeline_7_2; +reg pipeline_8_0; +reg pipeline_8_1; +reg pipeline_8_2; +reg pipeline_9_0; +reg pipeline_9_1; +reg pipeline_9_2; +reg pipeline_10_0; +reg pipeline_10_1; +reg pipeline_10_2; +reg pipeline_11_0; +reg pipeline_11_1; +reg pipeline_11_2; +reg pipeline_12_0; +reg pipeline_12_1; +reg pipeline_12_2; +reg pipeline_13_0; +reg pipeline_13_1; +reg pipeline_13_2; +reg pipeline_14_0; +reg pipeline_14_1; +reg pipeline_14_2; +reg pipeline_15_0; +reg pipeline_15_1; +reg pipeline_15_2; + +always @ (posedge clk) begin + if (reset) begin + pipeline_0_0 <= 0; + pipeline_0_1 <= 0; + pipeline_0_2 <= 0; + pipeline_1_0 <= 0; + pipeline_1_1 <= 0; + pipeline_1_2 <= 0; + pipeline_2_0 <= 0; + pipeline_2_1 <= 0; + pipeline_2_2 <= 0; + pipeline_3_0 <= 0; + pipeline_3_1 <= 0; + pipeline_3_2 <= 0; + pipeline_4_0 <= 0; + pipeline_4_1 <= 0; + pipeline_4_2 <= 0; + pipeline_5_0 <= 0; + pipeline_5_1 <= 0; + pipeline_5_2 <= 0; + pipeline_6_0 <= 0; + pipeline_6_1 <= 0; + pipeline_6_2 <= 0; + pipeline_7_0 <= 0; + pipeline_7_1 <= 0; + pipeline_7_2 <= 0; + pipeline_8_0 <= 0; + pipeline_8_1 <= 0; + pipeline_8_2 <= 0; + pipeline_9_0 <= 0; + pipeline_9_1 <= 0; + pipeline_9_2 <= 0; + pipeline_10_0 <= 0; + pipeline_10_1 <= 0; + pipeline_10_2 <= 0; + pipeline_11_0 <= 0; + pipeline_11_1 <= 0; + pipeline_11_2 <= 0; + pipeline_12_0 <= 0; + pipeline_12_1 <= 0; + pipeline_12_2 <= 0; + pipeline_13_0 <= 0; + pipeline_13_1 <= 0; + pipeline_13_2 <= 0; + pipeline_14_0 <= 0; + pipeline_14_1 <= 0; + pipeline_14_2 <= 0; + pipeline_15_0 <= 0; + pipeline_15_1 <= 0; + pipeline_15_2 <= 0; + end else begin + pipeline_0_0 <= signal[15]; + pipeline_1_0 <= signal[14]; + pipeline_2_0 <= signal[13]; + pipeline_3_0 <= signal[12]; + pipeline_4_0 <= signal[11]; + pipeline_5_0 <= signal[10]; + pipeline_6_0 <= signal[9]; + pipeline_7_0 <= signal[8]; + pipeline_8_0 <= signal[7]; + pipeline_9_0 <= signal[6]; + pipeline_10_0 <= signal[5]; + pipeline_11_0 <= signal[4]; + pipeline_12_0 <= signal[3]; + pipeline_13_0 <= signal[2]; + pipeline_14_0 <= signal[1]; + pipeline_15_0 <= signal[0]; + pipeline_0_1 <= pipeline_0_0 ^ pipeline_1_0^ pipeline_2_0 ^ pipeline_3_0; + pipeline_4_1 <= pipeline_4_0 ^ pipeline_5_0^ pipeline_6_0 ^ pipeline_7_0; + pipeline_8_1 <= pipeline_8_0 ^ pipeline_9_0^ pipeline_10_0 ^ pipeline_11_0; + pipeline_12_1 <= pipeline_12_0 ^ pipeline_13_0^ pipeline_14_0 ^ pipeline_15_0; + pipeline_0_2 <= pipeline_0_1 ^ pipeline_4_1^ pipeline_8_1 ^ pipeline_12_1; + end +end + +assign reduced_signal = pipeline_0_2; + +endmodule + +module pooling ( + input clk, + input i_valid, + input i_reset, + input [15:0] i_result_0, + input [15:0] i_result_1, + input [15:0] i_result_2, + input [15:0] i_result_3, + output [15:0] o_result, + output o_valid +); + +reg [15:0] buffer_0_0; +reg [15:0] buffer_0_1; +reg [15:0] buffer_1_0; +reg [15:0] buffer_1_1; +reg [1:0] count; +reg [0:0] s_count; +reg [15:0] result_0; +reg [15:0] result_1; +reg valid_1, valid_2, valid_3; + +always @(posedge clk) begin + buffer_0_1 <= buffer_0_0; + buffer_1_1 <= buffer_1_0; + valid_1 <= i_valid; + valid_2 <= valid_1; + valid_3 <= valid_2; + if (i_valid) begin + count <= 0; + end else begin + if(count == 3) begin + count <= 0; + end else begin + count <= count + 1'b1; + end + if(i_result_0 > i_result_1) begin + buffer_0_0 <= i_result_0; + end else begin + buffer_0_0 <= i_result_1; + end + if(i_result_2 > i_result_3) begin + buffer_1_0 <= i_result_2; + end else begin + buffer_1_0 <= i_result_3; + end + end +end + +always @(posedge clk) begin + if (i_reset) begin + s_count <= 0; + end else if (valid_1 || valid_2) begin + if (s_count == 1) begin + if (buffer_0_0 > buffer_0_1) begin + result_0 <= buffer_0_0; + end else begin + result_0 <= buffer_0_1; + end + if (buffer_1_0 > buffer_1_1) begin + result_1 <= buffer_1_0; + end else begin + result_1 <= buffer_1_1; + end + s_count <= 0; + end else begin + result_0 <= result_1; + s_count <= s_count + 1'b1; + end + end else begin + s_count <= 0; + end +end + +assign o_result = result_0; +assign o_valid = valid_3; + +endmodule + +module store_output ( + input clk, + input i_valid, + input i_reset, + input [15:0] i_result_0, + input [15:0] i_result_1, + input [15:0] i_result_2, + input [15:0] i_result_3, + input [15:0] i_result_4, + input [15:0] i_result_5, + input [15:0] i_result_6, + input [15:0] i_result_7, + input [15:0] i_result_8, + input [15:0] i_result_9, + input [15:0] i_result_10, + input [15:0] i_result_11, + output [15:0] o_store_0_0, + output [15:0] o_store_0_1, + output [15:0] o_store_1_0, + output [15:0] o_store_1_1, + output [15:0] o_store_2_0, + output [15:0] o_store_2_1, + output [15:0] o_store_3_0, + output [15:0] o_store_3_1, + output [15:0] o_store_4_0, + output [15:0] o_store_4_1, + output [15:0] o_store_5_0, + output [15:0] o_store_5_1, + output o_wen_0, + output o_wen_1, + output o_wen_2, + output o_wen_3, + output o_wen_4, + output o_wen_5, + output [14:0] o_addr +); + +reg wen_0; +reg wen_1; +reg wen_2; +reg wen_3; +reg wen_4; +reg wen_5; +reg [14:0] base_addr; +reg [14:0] offset; +reg [5:0] count; +reg [5:0] count_to_wvec; +reg [5:0] count_x; +reg [5:0] count_y; +reg valid; +reg [15:0] buffer_reg_0; +reg [15:0] buffer_reg_1; +reg [15:0] buffer_reg_2; +reg [15:0] buffer_reg_3; +reg [15:0] buffer_reg_4; +reg [15:0] buffer_reg_5; +reg [15:0] buffer_reg_6; +reg [15:0] buffer_reg_7; +reg [15:0] buffer_reg_8; +reg [15:0] buffer_reg_9; +reg [15:0] buffer_reg_10; +reg [15:0] buffer_reg_11; +reg [14:0] addr_reg; + +wire [5:0] count_div_two; +assign count_div_two = count >> 1; +always @ (posedge clk) begin + valid <= i_valid; + buffer_reg_0 <= i_result_0; + buffer_reg_1 <= i_result_1; + buffer_reg_2 <= i_result_2; + buffer_reg_3 <= i_result_3; + buffer_reg_4 <= i_result_4; + buffer_reg_5 <= i_result_5; + buffer_reg_6 <= i_result_6; + buffer_reg_7 <= i_result_7; + buffer_reg_8 <= i_result_8; + buffer_reg_9 <= i_result_9; + buffer_reg_10 <= i_result_10; + buffer_reg_11 <= i_result_11; + addr_reg <= base_addr + offset; + if (i_reset) begin + count <= 0; + count_to_wvec <= 0; + base_addr <= 0; + offset <= 0; + count_x <= 0; + count_y <= 0; + wen_0 <= 1'b0; + wen_1 <= 1'b0; + wen_2 <= 1'b0; + wen_3 <= 1'b0; + wen_4 <= 1'b0; + wen_5 <= 1'b0; + end else if (i_valid) begin + if (count_x == 5) begin + if(count_y == 6)begin + base_addr <= base_addr + 16; + count_y <= 0; + count_x <= 0; + offset <= 0; + end else begin + if(count[0] == 1'b0) begin + offset <= 8; + count <= count + 1'b1; + if(count_to_wvec == 5) begin + count_to_wvec <= 0; + end else begin + count_to_wvec <= count_to_wvec + 1'b1; + end + end else if (count[1] == 1'b1) begin + offset <= 0; + base_addr <= base_addr + 16; + count_x <= 0; + count_y <= count_y + 2; + count <= count + 1'b1; + if(count_to_wvec == 5) begin + count_to_wvec <= 0; + end else begin + count_to_wvec <= count_to_wvec + 1'b1; + end + end + end + end else if(count[0] == 1'b0) begin + offset <= 8; + count <= count + 1'b1; + if(count_to_wvec == 5) begin + count_to_wvec <= 0; + end else begin + count_to_wvec <= count_to_wvec + 1'b1; + end + end else if (count[0] == 1'b1) begin + offset <= 0; + count <= count + 1'b1; + if(count_to_wvec == 5) begin + count_to_wvec <= 0; + end else begin + count_to_wvec <= count_to_wvec + 1'b1; + end + count_x <= count_x + 1'b1; + end + if ((i_valid || valid) == 1'b1) begin + if ((count_to_wvec == 0) && i_valid == 1) begin + wen_0 <= 1'b1; + end else begin + wen_0 <= 1'b0; + end + if ((count_to_wvec == 1) && i_valid == 1) begin + wen_1 <= 1'b1; + end else begin + wen_1 <= 1'b0; + end + if ((count_to_wvec == 2) && i_valid == 1) begin + wen_2 <= 1'b1; + end else begin + wen_2 <= 1'b0; + end + if ((count_to_wvec == 3) && i_valid == 1) begin + wen_3 <= 1'b1; + end else begin + wen_3 <= 1'b0; + end + if ((count_to_wvec == 4) && i_valid == 1) begin + wen_4 <= 1'b1; + end else begin + wen_4 <= 1'b0; + end + if ((count_to_wvec == 5) && i_valid == 1) begin + wen_5 <= 1'b1; + end else begin + wen_5 <= 1'b0; + end + end + end +end + +assign o_addr = addr_reg; +assign o_store_0_0 = buffer_reg_0; +assign o_store_1_0 = buffer_reg_2; +assign o_store_2_0 = buffer_reg_4; +assign o_store_3_0 = buffer_reg_6; +assign o_store_4_0 = buffer_reg_8; +assign o_store_5_0 = buffer_reg_10; +assign o_store_0_1 = buffer_reg_1; +assign o_store_1_1 = buffer_reg_3; +assign o_store_2_1 = buffer_reg_5; +assign o_store_3_1 = buffer_reg_7; +assign o_store_4_1 = buffer_reg_9; +assign o_store_5_1 = buffer_reg_11; + +assign o_wen_0 = wen_0; +assign o_wen_1 = wen_1; +assign o_wen_2 = wen_2; +assign o_wen_3 = wen_3; +assign o_wen_4 = wen_4; +assign o_wen_5 = wen_5; + +endmodule + +module stream_buffer_3_1 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [14:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [14:0] base_addr; +reg [14:0] offset; +reg [14:0] base_addr_b1; +reg [14:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 1) && (L_counter == 2)) begin + base_addr <= base_addr + 5; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 2) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 2; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= base_addr_b1 + 5; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 2) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 2; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [14:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_24200_buffer_init_13 buffer_16_24200_buffer_init_13_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_24200_buffer_init_13 buffer_16_24200_buffer_init_13_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_24200_buffer_init_13 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module stream_buffer_3_0 ( + input clk, + input i_reset, + input i_wen0, + input i_wen1, + input [15:0] i_ddr, + input [15:0] i_pool, + input i_eltwise_sel, + input [15:0] i_eltwise, + input [14:0] i_waddr, + output [15:0] o_feature_0, + output [15:0] o_feature_1, + output o_done +); + +reg [14:0] base_addr; +reg [14:0] offset; +reg [14:0] base_addr_b1; +reg [14:0] offset_b1; +reg [1:0] L_counter; +reg [1:0] C_counter; +reg [1:0] W_counter; +reg [1:0] L_counter_b1; +reg [1:0] C_counter_b1; +reg [1:0] W_counter_b1; +reg done, done_1, done_2, done_3; +reg valid, valid_1, valid_2; +wire [15:0] feature_out_b0; +wire [15:0] feature_out_b1; + +always @ (posedge clk) begin + if (i_reset) begin + base_addr <= 0; + offset <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + end else if (done == 0) begin + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + base_addr <= 0; + C_counter <= 0; + L_counter <= 0; + W_counter <= 0; + offset <= 0; + end else if((C_counter == 1) && (L_counter == 2)) begin + base_addr <= base_addr + 5; + W_counter <= W_counter + 1'b1; + C_counter <= 0; + L_counter <= 0; + offset <= 0; + end else if(L_counter == 2) begin + base_addr <= base_addr + 1'b1; + C_counter <= C_counter + 1'b1; + L_counter <= 0; + offset <= 0; + end else begin + offset <= offset + 2; + L_counter <= L_counter + 1'b1; + end + end +end + +always @ (posedge clk) begin + if (i_reset) begin + base_addr_b1 <= 0; + offset_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + end else if (done == 0) begin + if((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= 0; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + W_counter_b1 <= 0; + offset_b1 <= 0; + end else if((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin + base_addr_b1 <= base_addr_b1 + 5; + W_counter_b1 <= W_counter_b1 + 1'b1; + C_counter_b1 <= 0; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else if(L_counter_b1 == 2) begin + base_addr_b1 <= base_addr_b1 + 1'b1; + C_counter_b1 <= C_counter_b1 + 1'b1; + L_counter_b1 <= 0; + offset_b1 <= 0; + end else begin + offset_b1 <= offset_b1 + 2; + L_counter_b1 <= L_counter_b1 + 1'b1; + end + end +end + +always @ (posedge clk) begin + if(i_reset == 1'b1)begin + done <= 0; + done_1 <= 0; + done_2 <= 0; + done_3 <= 0; + valid <= 0; + valid_1 <= 0; + valid_2 <= 0; + end else begin + valid <= 1; + if((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin + done <= 1; + end + done_1 <= done; + done_2 <= done_1; + done_3 <= done_2; + valid_1 <= valid; + valid_2 <= valid_1; + end +end + +reg [14:0] b0_waddr, b0_raddr, b1_raddr; +always @ (*) begin + b0_waddr <= base_addr+offset; + b0_raddr <= base_addr+offset; + b1_raddr <= base_addr_b1+offset_b1; +end +buffer_16_24200_buffer_init_03 buffer_16_24200_buffer_init_03_B0 ( + .clk(clk), + .wen(i_wen0), + .waddr(b0_waddr), + .wdata(i_ddr), + .raddr(b0_raddr), + .rdata(feature_out_b0) +); + +reg [15:0] B1_wdata; +always @ (*) begin + if (i_eltwise_sel) begin + B1_wdata <= i_eltwise; + end else begin + B1_wdata <= i_pool; + end +end + +buffer_16_24200_buffer_init_03 buffer_16_24200_buffer_init_03_B1 ( + .clk(clk), + .wen(i_wen1), + .waddr(i_waddr), + .wdata(B1_wdata), + .raddr(b1_raddr), + .rdata(feature_out_b1) +); + +assign o_done = valid_2 && (~done_3); +assign o_feature_0 = feature_out_b0; +assign o_feature_1 = feature_out_b1; + +endmodule + +module buffer_16_24200_buffer_init_03 ( + input clk, + input wen, + input [11:0] waddr, + input [15:0] wdata, + input [11:0] raddr, + output [15:0] rdata +); + +reg [11:0] raddr_reg; +reg [15:0] rdata_reg; +reg [15:0] pipeline_reg_0; +wire [15:0] rd_dummy_signal; +wire [15:0] wr_dummy_signal; +wire [15:0] rdata_wire; +assign rd_dummy_signal = 0; + +always @(posedge clk) begin + rdata_reg <= rdata_wire; + raddr_reg <= raddr; + pipeline_reg_0 <= rdata_reg; +end + +dpram #(.AWIDTH(12),.DWIDTH(16),.NUM_WORDS(1<<12)) u_dpram( + .addr1(waddr), + .we1(wen), + .data1(wdata), + .out1(wr_dummy_signal), + .addr2(raddr_reg), + .we2(1'b0), + .data2(rd_dummy_signal), + .out2(rdata_wire), + .clk(clk) +); +assign rdata = pipeline_reg_0; + +endmodule + +module dpram ( + clk, + addr1, + addr2, + we1, + we2, + data1, + data2, + out1, + out2 +); +parameter AWIDTH=10; +parameter NUM_WORDS=1024; +parameter DWIDTH=32; +input clk; +input [(AWIDTH-1):0] addr1; +input [(AWIDTH-1):0] addr2; +input we1; +input we2; +input [(DWIDTH-1):0] data1; +input [(DWIDTH-1):0] data2; +output reg [(DWIDTH-1):0] out1; +output reg [(DWIDTH-1):0] out2; + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram[NUM_WORDS-1:0]; +always @ (posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end +// else begin + out1 <= ram[addr1]; +// end +end + +always @ (posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end +// else begin + out2 <= ram[addr2]; +// end +end + +`else +defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; +defparam u_dual_port_ram.DATA_WIDTH = DWIDTH; + +dual_port_ram u_dual_port_ram( +.addr1(addr1), +.we1(we1), +.data1(data1), +.out1(out1), +.addr2(addr2), +.we2(we2), +.data2(data2), +.out2(out2), +.clk(clk) +); + +`endif +endmodule + + diff --git a/designs/koios/dla_like.small/dla_random.sv b/designs/koios/dla_like.small/dla_random.sv new file mode 100644 index 000000000..133deb67b --- /dev/null +++ b/designs/koios/dla_like.small/dla_random.sv @@ -0,0 +1,96 @@ +/* +Random input logic for DLA +*/ + +`include "../../random_number_generator.sv" + +module dla_random( + input logic clk, + input logic rst, + input logic i_ddr_wen_0_0, + output logic o_dummy_out_0_0, + input logic i_ddr_wen_0_1, + output logic o_dummy_out_0_1, + input logic i_ddr_wen_1_0, + output logic o_dummy_out_1_0, + input logic i_ddr_wen_1_1, + output logic o_dummy_out_1_1, + input logic i_ddr_wen_2_0, + output logic o_dummy_out_2_0, + input logic i_ddr_wen_2_1, + output logic o_dummy_out_2_1, + input logic i_ddr_wen_3_0, + output logic o_dummy_out_3_0, + input logic i_ddr_wen_3_1, + output logic o_dummy_out_3_1, + input logic i_ddr_wen_4_0, + output logic o_dummy_out_4_0, + input logic i_ddr_wen_4_1, + output logic o_dummy_out_4_1, + input logic i_ddr_wen_5_0, + output logic o_dummy_out_5_0, + input logic i_ddr_wen_5_1, + output logic o_dummy_out_5_1, + output logic o_valid +); + +logic [15:0] i_ddr[5:0][3:0]; +generate // generate block for random number generator +genvar i; +genvar j; +for(i=0; i<6; i=i+1) begin + for(j=0; j<2; j=j+1) begin + RandomNumberGenerator #(16, i+j) random_number_generator_0( + .clk(clk), + .reset(rst), + .random_number(i_ddr[i][j]) + ); + end +end +endgenerate + + +DLA dla0( + clk, + rst, + i_ddr_wen_0_0, + i_ddr[0][0], + o_dummy_out_0_0, + i_ddr_wen_0_1, + i_ddr[0][1], + o_dummy_out_0_1, + i_ddr_wen_1_0, + i_ddr[1][0], + o_dummy_out_1_0, + i_ddr_wen_1_1, + i_ddr[1][1], + o_dummy_out_1_1, + i_ddr_wen_2_0, + i_ddr[2][0], + o_dummy_out_2_0, + i_ddr_wen_2_1, + i_ddr[2][1], + o_dummy_out_2_1, + i_ddr_wen_3_0, + i_ddr[3][0], + o_dummy_out_3_0, + i_ddr_wen_3_1, + i_ddr[3][1], + o_dummy_out_3_1, + i_ddr_wen_4_0, + i_ddr[4][0], + o_dummy_out_4_0, + i_ddr_wen_4_1, + i_ddr[4][1], + o_dummy_out_4_1, + i_ddr_wen_5_0, + i_ddr[5][0], + o_dummy_out_5_0, + i_ddr_wen_5_1, + i_ddr[5][1], + o_dummy_out_5_1, + o_valid +); + + +endmodule \ No newline at end of file diff --git a/designs/koios/dnnweaver/cl_wrapper_random.sv b/designs/koios/dnnweaver/cl_wrapper_random.sv new file mode 100644 index 000000000..c0671ff59 --- /dev/null +++ b/designs/koios/dnnweaver/cl_wrapper_random.sv @@ -0,0 +1,1044 @@ +/* +Random I/Os to cl_wrapper for dnnweaver +*/ + +`include "../../random_number_generator.sv" + +module cl_wrapper_random #( + parameter integer INST_W = 32, + parameter integer INST_ADDR_W = 5, + parameter integer IFIFO_ADDR_W = 10, + parameter integer BUF_TYPE_W = 2, + parameter integer OP_CODE_W= 5, + parameter integer OP_SPEC_W= 6, + parameter integer LOOP_ID_W= 5, + + // Systolic Array + parameter integer ARRAY_N = 32, + parameter integer ARRAY_M = 32, + + // Precision + parameter integer DATA_WIDTH = 8, + parameter integer BIAS_WIDTH = 16, + parameter integer ACC_WIDTH= 32, + + // Buffers + parameter integer NUM_TAGS = 2, + parameter integer IBUF_CAPACITY_BITS = ARRAY_N * DATA_WIDTH * 2048 / NUM_TAGS, + parameter integer WBUF_CAPACITY_BITS = ARRAY_N * ARRAY_M * DATA_WIDTH * 256 / NUM_TAGS, + parameter integer OBUF_CAPACITY_BITS = ARRAY_M * ACC_WIDTH * 2048 / NUM_TAGS, + parameter integer BBUF_CAPACITY_BITS = ARRAY_M * BIAS_WIDTH * 2048 / NUM_TAGS, + + // Buffer Addr Width + parameter integer IBUF_ADDR_WIDTH = $clog2(IBUF_CAPACITY_BITS / ARRAY_N / DATA_WIDTH), + parameter integer WBUF_ADDR_WIDTH = $clog2(WBUF_CAPACITY_BITS / ARRAY_N / ARRAY_M / DATA_WIDTH), + parameter integer OBUF_ADDR_WIDTH = $clog2(OBUF_CAPACITY_BITS / ARRAY_M / ACC_WIDTH), + parameter integer BBUF_ADDR_WIDTH = $clog2(BBUF_CAPACITY_BITS / ARRAY_M / BIAS_WIDTH), + + // AXI DATA + parameter integer AXI_ADDR_WIDTH= 42, + parameter integer AXI_BURST_WIDTH = 8, + parameter integer IBUF_AXI_DATA_WIDTH= 256, + parameter integer IBUF_WSTRB_W = IBUF_AXI_DATA_WIDTH/8, + parameter integer OBUF_AXI_DATA_WIDTH= 256, + parameter integer OBUF_WSTRB_W = OBUF_AXI_DATA_WIDTH/8, + parameter integer PU_AXI_DATA_WIDTH = 256, + parameter integer PU_WSTRB_W = PU_AXI_DATA_WIDTH/8, + parameter integer WBUF_AXI_DATA_WIDTH= 256, + parameter integer WBUF_WSTRB_W = WBUF_AXI_DATA_WIDTH/8, + parameter integer BBUF_AXI_DATA_WIDTH= 256, + parameter integer BBUF_WSTRB_W = BBUF_AXI_DATA_WIDTH/8, + parameter integer AXI_ID_WIDTH = 1, + // AXI Instructions + parameter integer INST_ADDR_WIDTH = 16, + parameter integer INST_DATA_WIDTH = 32, + parameter integer INST_WSTRB_WIDTH = INST_DATA_WIDTH/8, + parameter integer INST_BURST_WIDTH = 8, + // AXI-Lite + parameter integer CTRL_ADDR_WIDTH = 16, + parameter integer CTRL_DATA_WIDTH = 32, + parameter integer CTRL_WSTRB_WIDTH = CTRL_DATA_WIDTH/8 +) ( + input wire logic clk, + input wire logic reset, + // PCIe-> CL_wrapper AXI4-Lite interface + // Slave Write address + input wire logic pci_cl_ctrl_awvalid, + output logic pci_cl_ctrl_awready, + // Slave Write data + input wire logic pci_cl_ctrl_wvalid, + output logic pci_cl_ctrl_wready, + //Write response + output logic pci_cl_ctrl_bvalid, + output logic [2-1:0] pci_cl_ctrl_bresp, + input wire logic pci_cl_ctrl_bready, + //Read address + input wire logic pci_cl_ctrl_arvalid, + output logic pci_cl_ctrl_arready, + //Read data/response + output logic pci_cl_ctrl_rvalid, + output logic [CTRL_DATA_WIDTH-1:0] pci_cl_ctrl_rdata, + output logic [2-1:0] pci_cl_ctrl_rresp, + input wire logic pci_cl_ctrl_rready, + + // PCIe-> CL_wrapper AXI4 interface + // Slave Interface Write Address + input wire logic [3-1:0] pci_cl_data_awsize, + input wire logic [2-1:0] pci_cl_data_awburst, + input wire logic pci_cl_data_awvalid, + output logic pci_cl_data_awready, + // Slave Interface Write Data + input wire logic pci_cl_data_wlast, + input wire logic pci_cl_data_wvalid, + output logic pci_cl_data_wready, + // Slave Interface Write Response + output logic [2-1:0] pci_cl_data_bresp, + output logic pci_cl_data_bvalid, + input wire logic pci_cl_data_bready, + // Slave Interface Read Address + input wire logic [3-1:0] pci_cl_data_arsize, + input wire logic [2-1:0] pci_cl_data_arburst, + input wire logic pci_cl_data_arvalid, + output logic pci_cl_data_arready, + // Slave Interface Read Data + output logic [INST_DATA_WIDTH-1:0] pci_cl_data_rdata, + output logic [2-1:0] pci_cl_data_rresp, + output logic pci_cl_data_rlast, + output logic pci_cl_data_rvalid, + input wire logic pci_cl_data_rready, + + // CL_wrapper-> DDR0 AXI4 interface + // Master Interface Write Address + output logic [3-1:0] cl_ddr0_awsize, + output logic [2-1:0] cl_ddr0_awburst, + output logic cl_ddr0_awvalid, + input wire logic cl_ddr0_awready, + // Master Interface Write Data + output logic cl_ddr0_wlast, + output logic cl_ddr0_wvalid, + input wire logic cl_ddr0_wready, + // Master Interface Write Response + input wire logic [2-1:0] cl_ddr0_bresp, + input wire logic cl_ddr0_bvalid, + output logic cl_ddr0_bready, + // Master Interface Read Address + output logic [3-1:0] cl_ddr0_arsize, + output logic [2-1:0] cl_ddr0_arburst, + output logic cl_ddr0_arvalid, + output logic [AXI_ID_WIDTH-1:0] cl_ddr0_arid, + input wire logic cl_ddr0_arready, + // Master Interface Read Data + input wire logic [2-1:0] cl_ddr0_rresp, + input wire logic cl_ddr0_rlast, + input wire logic cl_ddr0_rvalid, + output logic cl_ddr0_rready, + + // CL_wrapper-> DDR1 AXI4 interface + // Master Interface Write Address + output logic [3-1:0] cl_ddr1_awsize, + output logic [2-1:0] cl_ddr1_awburst, + output logic cl_ddr1_awvalid, + input wire logic cl_ddr1_awready, + // Master Interface Write Data + output logic cl_ddr1_wlast, + output logic cl_ddr1_wvalid, + input wire logic cl_ddr1_wready, + // Master Interface Write Response + input wire logic [2-1:0] cl_ddr1_bresp, + input wire logic cl_ddr1_bvalid, + output logic cl_ddr1_bready, + // Master Interface Read Address + output logic [3-1:0] cl_ddr1_arsize, + output logic [2-1:0] cl_ddr1_arburst, + output logic cl_ddr1_arvalid, + output logic [AXI_ID_WIDTH-1:0] cl_ddr1_arid, + input wire logic cl_ddr1_arready, + // Master Interface Read Data + input wire logic [2-1:0] cl_ddr1_rresp, + input wire logic cl_ddr1_rlast, + input wire logic cl_ddr1_rvalid, + output logic cl_ddr1_rready, + + // CL_wrapper-> DDR2 AXI4 interface + // Master Interface Write Address + output logic [3-1:0] cl_ddr2_awsize, + output logic [2-1:0] cl_ddr2_awburst, + output logic cl_ddr2_awvalid, + input wire logic cl_ddr2_awready, + // Master Interface Write Data + output logic cl_ddr2_wlast, + output logic cl_ddr2_wvalid, + input wire logic cl_ddr2_wready, + // Master Interface Write Response + input wire logic [2-1:0] cl_ddr2_bresp, + input wire logic cl_ddr2_bvalid, + output logic cl_ddr2_bready, + // Master Interface Read Address + output logic [3-1:0] cl_ddr2_arsize, + output logic [2-1:0] cl_ddr2_arburst, + output logic cl_ddr2_arvalid, + output logic [AXI_ID_WIDTH-1:0] cl_ddr2_arid, + input wire logic cl_ddr2_arready, + // Master Interface Read Data + input wire logic [2-1:0] cl_ddr2_rresp, + input wire logic cl_ddr2_rlast, + input wire logic cl_ddr2_rvalid, + output logic cl_ddr2_rready, + + // CL_wrapper-> DDR3 AXI4 interface + // Master Interface Write Address + output logic [3-1:0] cl_ddr3_awsize, + output logic [2-1:0] cl_ddr3_awburst, + output logic cl_ddr3_awvalid, + input wire logic cl_ddr3_awready, + // Master Interface Write Data + output logic cl_ddr3_wlast, + output logic cl_ddr3_wvalid, + input wire logic cl_ddr3_wready, + // Master Interface Write Response + input wire logic [2-1:0] cl_ddr3_bresp, + input wire logic cl_ddr3_bvalid, + output logic cl_ddr3_bready, + // Master Interface Read Address + output logic [3-1:0] cl_ddr3_arsize, + output logic [2-1:0] cl_ddr3_arburst, + output logic cl_ddr3_arvalid, + output logic [AXI_ID_WIDTH-1:0] cl_ddr3_arid, + input wire logic cl_ddr3_arready, + // Master Interface Read Data + input wire logic [2-1:0] cl_ddr3_rresp, + input wire logic cl_ddr3_rlast, + input wire logic cl_ddr3_rvalid, + output logic cl_ddr3_rready, + + + // CL_wrapper-> DDR3 AXI4 interface + // Master Interface Write Address + output logic [3-1:0] cl_ddr4_awsize, + output logic [2-1:0] cl_ddr4_awburst, + output logic cl_ddr4_awvalid, + input wire logic cl_ddr4_awready, + // Master Interface Write Data + output logic cl_ddr4_wlast, + output logic cl_ddr4_wvalid, + input wire logic cl_ddr4_wready, + // Master Interface Write Response + input wire logic [2-1:0] cl_ddr4_bresp, + input wire logic cl_ddr4_bvalid, + output logic cl_ddr4_bready, + // Master Interface Read Address + output logic [3-1:0] cl_ddr4_arsize, + output logic [2-1:0] cl_ddr4_arburst, + output logic cl_ddr4_arvalid, + output logic [AXI_ID_WIDTH-1:0] cl_ddr4_arid, + input wire logic cl_ddr4_arready, + // Master Interface Read Data + input wire logic [2-1:0] cl_ddr4_rresp, + input wire logic cl_ddr4_rlast, + input wire logic cl_ddr4_rvalid, + output logic cl_ddr4_rready, + input wire logic[4:0] wstrb_sel, + input wire logic [7:0] wdata_sel, + input wire logic [3:0] ax_addr_sel, + input wire logic [5:0] arw_addr_sel, + output logic [7:0] data_out, + input wire logic [1:0] out_sel +); +logic [7:0] wstrb; +logic [7:0] wdata; +logic [AXI_BURST_WIDTH-1:0] ax_addr; +logic [6:0] arw_addr; +always_comb begin + case (out_sel[1:0]) + 0: data_out = wstrb; + 1: data_out = wdata; + 2: data_out = ax_addr; + 3: data_out = {1'b0, arw_addr}; + default: data_out = 8'b0; + endcase +end + +logic [IBUF_WSTRB_W-1:0] cl_ddr0_wstrb; +logic [OBUF_WSTRB_W-1:0] cl_ddr1_wstrb; +logic [WBUF_WSTRB_W-1:0] cl_ddr2_wstrb; +logic [BBUF_WSTRB_W-1:0] cl_ddr3_wstrb; +logic [PU_WSTRB_W-1:0] cl_ddr4_wstrb; + +always_comb begin + case (wstrb_sel[4:0]) + 0: wstrb = cl_ddr0_wstrb[7:0]; + 1: wstrb = cl_ddr0_wstrb[15:8]; + 2: wstrb = cl_ddr0_wstrb[23:16]; + 3: wstrb = cl_ddr0_wstrb[31:24]; + 4: wstrb = cl_ddr1_wstrb[7:0]; + 5: wstrb = cl_ddr1_wstrb[15:8]; + 6: wstrb = cl_ddr1_wstrb[23:16]; + 7: wstrb = cl_ddr1_wstrb[31:24]; + 8: wstrb = cl_ddr2_wstrb[7:0]; + 9: wstrb = cl_ddr2_wstrb[15:8]; + 10: wstrb = cl_ddr2_wstrb[23:16]; + 11: wstrb = cl_ddr2_wstrb[31:24]; + 12: wstrb = cl_ddr3_wstrb[7:0]; + 13: wstrb = cl_ddr3_wstrb[15:8]; + 14: wstrb = cl_ddr3_wstrb[23:16]; + 15: wstrb = cl_ddr3_wstrb[31:24]; + 16: wstrb = cl_ddr4_wstrb[7:0]; + 17: wstrb = cl_ddr4_wstrb[15:8]; + 18: wstrb = cl_ddr4_wstrb[23:16]; + 19: wstrb = cl_ddr4_wstrb[31:24]; + default: wstrb = 8'b0; + endcase +end + + +logic [IBUF_AXI_DATA_WIDTH-1:0] cl_ddr0_wdata; +logic [OBUF_AXI_DATA_WIDTH-1:0] cl_ddr1_wdata; +logic [WBUF_AXI_DATA_WIDTH-1:0] cl_ddr2_wdata; +logic [BBUF_AXI_DATA_WIDTH-1:0] cl_ddr3_wdata; +logic [PU_AXI_DATA_WIDTH-1:0] cl_ddr4_wdata; +always_comb begin + case (wdata_sel[7:0]) + 0: wdata = cl_ddr0_wdata[7:0]; + 1: wdata = cl_ddr0_wdata[15:8]; + 2: wdata = cl_ddr0_wdata[23:16]; + 3: wdata = cl_ddr0_wdata[31:24]; + 4: wdata = cl_ddr0_wdata[39:32]; + 5: wdata = cl_ddr0_wdata[47:40]; + 6: wdata = cl_ddr0_wdata[55:48]; + 7: wdata = cl_ddr0_wdata[63:56]; + 8: wdata = cl_ddr0_wdata[71:64]; + 9: wdata = cl_ddr0_wdata[79:72]; + 10: wdata = cl_ddr0_wdata[87:80]; + 11: wdata = cl_ddr0_wdata[95:88]; + 12: wdata = cl_ddr0_wdata[103:96]; + 13: wdata = cl_ddr0_wdata[111:104]; + 14: wdata = cl_ddr0_wdata[119:112]; + 15: wdata = cl_ddr0_wdata[127:120]; + 16: wdata = cl_ddr0_wdata[135:128]; + 17: wdata = cl_ddr0_wdata[143:136]; + 18: wdata = cl_ddr0_wdata[151:144]; + 19: wdata = cl_ddr0_wdata[159:152]; + 20: wdata = cl_ddr0_wdata[167:160]; + 21: wdata = cl_ddr0_wdata[175:168]; + 22: wdata = cl_ddr0_wdata[183:176]; + 23: wdata = cl_ddr0_wdata[191:184]; + 24: wdata = cl_ddr0_wdata[199:192]; + 25: wdata = cl_ddr0_wdata[207:200]; + 26: wdata = cl_ddr0_wdata[215:208]; + 27: wdata = cl_ddr0_wdata[223:216]; + 28: wdata = cl_ddr0_wdata[231:224]; + 29: wdata = cl_ddr0_wdata[239:232]; + 30: wdata = cl_ddr0_wdata[247:240]; + 31: wdata = cl_ddr0_wdata[255:248]; + 32: wdata = cl_ddr1_wdata[7:0]; + 33: wdata = cl_ddr1_wdata[15:8]; + 34: wdata = cl_ddr1_wdata[23:16]; + 35: wdata = cl_ddr1_wdata[31:24]; + 36: wdata = cl_ddr1_wdata[39:32]; + 37: wdata = cl_ddr1_wdata[47:40]; + 38: wdata = cl_ddr1_wdata[55:48]; + 39: wdata = cl_ddr1_wdata[63:56]; + 40: wdata = cl_ddr1_wdata[71:64]; + 41: wdata = cl_ddr1_wdata[79:72]; + 42: wdata = cl_ddr1_wdata[87:80]; + 43: wdata = cl_ddr1_wdata[95:88]; + 44: wdata = cl_ddr1_wdata[103:96]; + 45: wdata = cl_ddr1_wdata[111:104]; + 46: wdata = cl_ddr1_wdata[119:112]; + 47: wdata = cl_ddr1_wdata[127:120]; + 48: wdata = cl_ddr1_wdata[135:128]; + 49: wdata = cl_ddr1_wdata[143:136]; + 50: wdata = cl_ddr1_wdata[151:144]; + 51: wdata = cl_ddr1_wdata[159:152]; + 52: wdata = cl_ddr1_wdata[167:160]; + 53: wdata = cl_ddr1_wdata[175:168]; + 54: wdata = cl_ddr1_wdata[183:176]; + 55: wdata = cl_ddr1_wdata[191:184]; + 56: wdata = cl_ddr1_wdata[199:192]; + 57: wdata = cl_ddr1_wdata[207:200]; + 58: wdata = cl_ddr1_wdata[215:208]; + 59: wdata = cl_ddr1_wdata[223:216]; + 60: wdata = cl_ddr1_wdata[231:224]; + 61: wdata = cl_ddr1_wdata[239:232]; + 62: wdata = cl_ddr1_wdata[247:240]; + 63: wdata = cl_ddr1_wdata[255:248]; + 64: wdata = cl_ddr2_wdata[7:0]; + 65: wdata = cl_ddr2_wdata[15:8]; + 66: wdata = cl_ddr2_wdata[23:16]; + 67: wdata = cl_ddr2_wdata[31:24]; + 68: wdata = cl_ddr2_wdata[39:32]; + 69: wdata = cl_ddr2_wdata[47:40]; + 70: wdata = cl_ddr2_wdata[55:48]; + 71: wdata = cl_ddr2_wdata[63:56]; + 72: wdata = cl_ddr2_wdata[71:64]; + 73: wdata = cl_ddr2_wdata[79:72]; + 74: wdata = cl_ddr2_wdata[87:80]; + 75: wdata = cl_ddr2_wdata[95:88]; + 76: wdata = cl_ddr2_wdata[103:96]; + 77: wdata = cl_ddr2_wdata[111:104]; + 78: wdata = cl_ddr2_wdata[119:112]; + 79: wdata = cl_ddr2_wdata[127:120]; + 80: wdata = cl_ddr2_wdata[135:128]; + 81: wdata = cl_ddr2_wdata[143:136]; + 82: wdata = cl_ddr2_wdata[151:144]; + 83: wdata = cl_ddr2_wdata[159:152]; + 84: wdata = cl_ddr2_wdata[167:160]; + 85: wdata = cl_ddr2_wdata[175:168]; + 86: wdata = cl_ddr2_wdata[183:176]; + 87: wdata = cl_ddr2_wdata[191:184]; + 88: wdata = cl_ddr2_wdata[199:192]; + 89: wdata = cl_ddr2_wdata[207:200]; + 90: wdata = cl_ddr2_wdata[215:208]; + 91: wdata = cl_ddr2_wdata[223:216]; + 92: wdata = cl_ddr2_wdata[231:224]; + 93: wdata = cl_ddr2_wdata[239:232]; + 94: wdata = cl_ddr2_wdata[247:240]; + 95: wdata = cl_ddr2_wdata[255:248]; + 96: wdata = cl_ddr3_wdata[7:0]; + 97: wdata = cl_ddr3_wdata[15:8]; + 98: wdata = cl_ddr3_wdata[23:16]; + 99: wdata = cl_ddr3_wdata[31:24]; + 100: wdata = cl_ddr3_wdata[39:32]; + 101: wdata = cl_ddr3_wdata[47:40]; + 102: wdata = cl_ddr3_wdata[55:48]; + 103: wdata = cl_ddr3_wdata[63:56]; + 104: wdata = cl_ddr3_wdata[71:64]; + 105: wdata = cl_ddr3_wdata[79:72]; + 106: wdata = cl_ddr3_wdata[87:80]; + 107: wdata = cl_ddr3_wdata[95:88]; + 108: wdata = cl_ddr3_wdata[103:96]; + 109: wdata = cl_ddr3_wdata[111:104]; + 110: wdata = cl_ddr3_wdata[119:112]; + 111: wdata = cl_ddr3_wdata[127:120]; + 112: wdata = cl_ddr3_wdata[135:128]; + 113: wdata = cl_ddr3_wdata[143:136]; + 114: wdata = cl_ddr3_wdata[151:144]; + 115: wdata = cl_ddr3_wdata[159:152]; + 116: wdata = cl_ddr3_wdata[167:160]; + 117: wdata = cl_ddr3_wdata[175:168]; + 118: wdata = cl_ddr3_wdata[183:176]; + 119: wdata = cl_ddr3_wdata[191:184]; + 120: wdata = cl_ddr3_wdata[199:192]; + 121: wdata = cl_ddr3_wdata[207:200]; + 122: wdata = cl_ddr3_wdata[215:208]; + 123: wdata = cl_ddr3_wdata[223:216]; + 124: wdata = cl_ddr3_wdata[231:224]; + 125: wdata = cl_ddr3_wdata[239:232]; + 126: wdata = cl_ddr3_wdata[247:240]; + 127: wdata = cl_ddr3_wdata[255:248]; + 128: wdata = cl_ddr4_wdata[7:0]; + 129: wdata = cl_ddr4_wdata[15:8]; + 130: wdata = cl_ddr4_wdata[23:16]; + 131: wdata = cl_ddr4_wdata[31:24]; + 132: wdata = cl_ddr4_wdata[39:32]; + 133: wdata = cl_ddr4_wdata[47:40]; + 134: wdata = cl_ddr4_wdata[55:48]; + 135: wdata = cl_ddr4_wdata[63:56]; + 136: wdata = cl_ddr4_wdata[71:64]; + 137: wdata = cl_ddr4_wdata[79:72]; + 138: wdata = cl_ddr4_wdata[87:80]; + 139: wdata = cl_ddr4_wdata[95:88]; + 140: wdata = cl_ddr4_wdata[103:96]; + 141: wdata = cl_ddr4_wdata[111:104]; + 142: wdata = cl_ddr4_wdata[119:112]; + 143: wdata = cl_ddr4_wdata[127:120]; + 144: wdata = cl_ddr4_wdata[135:128]; + 145: wdata = cl_ddr4_wdata[143:136]; + 146: wdata = cl_ddr4_wdata[151:144]; + 147: wdata = cl_ddr4_wdata[159:152]; + 148: wdata = cl_ddr4_wdata[167:160]; + 149: wdata = cl_ddr4_wdata[175:168]; + 150: wdata = cl_ddr4_wdata[183:176]; + 151: wdata = cl_ddr4_wdata[191:184]; + 152: wdata = cl_ddr4_wdata[199:192]; + 153: wdata = cl_ddr4_wdata[207:200]; + 154: wdata = cl_ddr4_wdata[215:208]; + 155: wdata = cl_ddr4_wdata[223:216]; + 156: wdata = cl_ddr4_wdata[231:224]; + 157: wdata = cl_ddr4_wdata[239:232]; + 158: wdata = cl_ddr4_wdata[247:240]; + 159: wdata = cl_ddr4_wdata[255:248]; + default: wdata = 8'b0; + endcase +end + + +logic [AXI_BURST_WIDTH-1:0] cl_ddr0_arlen; +logic [AXI_BURST_WIDTH-1:0] cl_ddr0_awlen; +logic [AXI_BURST_WIDTH-1:0] cl_ddr1_awlen; +logic [AXI_BURST_WIDTH-1:0] cl_ddr1_arlen; +logic [AXI_BURST_WIDTH-1:0] cl_ddr2_awlen; +logic [AXI_BURST_WIDTH-1:0] cl_ddr2_arlen; +logic [AXI_BURST_WIDTH-1:0] cl_ddr3_awlen; +logic [AXI_BURST_WIDTH-1:0] cl_ddr3_arlen; +logic [AXI_BURST_WIDTH-1:0] cl_ddr4_awlen; +logic [AXI_BURST_WIDTH-1:0] cl_ddr4_arlen; +always_comb begin + case (ax_addr_sel[3:0]) + 0: ax_addr = cl_ddr0_arlen; + 1: ax_addr = cl_ddr0_awlen; + 2: ax_addr = cl_ddr1_awlen; + 3: ax_addr = cl_ddr1_arlen; + 4: ax_addr = cl_ddr2_awlen; + 5: ax_addr = cl_ddr2_arlen; + 6: ax_addr = cl_ddr3_awlen; + 7: ax_addr = cl_ddr3_arlen; + 8: ax_addr = cl_ddr4_awlen; + 9: ax_addr = cl_ddr4_arlen; + default: ax_addr = {AXI_BURST_WIDTH{1'b0}}; + endcase +end + + +logic [AXI_ADDR_WIDTH-1:0] cl_ddr0_araddr; +logic [AXI_ADDR_WIDTH-1:0] cl_ddr0_awaddr; +logic [AXI_ADDR_WIDTH-1:0] cl_ddr1_awaddr; +logic [AXI_ADDR_WIDTH-1:0] cl_ddr1_araddr; +logic [AXI_ADDR_WIDTH-1:0] cl_ddr2_awaddr; +logic [AXI_ADDR_WIDTH-1:0] cl_ddr2_araddr; +logic [AXI_ADDR_WIDTH-1:0] cl_ddr3_awaddr; +logic [AXI_ADDR_WIDTH-1:0] cl_ddr3_araddr; +logic [AXI_ADDR_WIDTH-1:0] cl_ddr4_awaddr; +logic [AXI_ADDR_WIDTH-1:0] cl_ddr4_araddr; +always_comb begin + case (arw_addr_sel[5:0]) + 0: arw_addr = cl_ddr0_araddr[6:0]; + 1: arw_addr = cl_ddr0_araddr[13:7]; + 2: arw_addr = cl_ddr0_araddr[20:14]; + 3: arw_addr = cl_ddr0_araddr[27:21]; + 4: arw_addr = cl_ddr0_araddr[34:28]; + 5: arw_addr = cl_ddr0_araddr[41:35]; + 6: arw_addr = cl_ddr0_awaddr[6:0]; + 7: arw_addr = cl_ddr0_awaddr[13:7]; + 8: arw_addr = cl_ddr0_awaddr[20:14]; + 9: arw_addr = cl_ddr0_awaddr[27:21]; + 10: arw_addr = cl_ddr0_awaddr[34:28]; + 11: arw_addr = cl_ddr0_awaddr[41:35]; + 12: arw_addr = cl_ddr1_araddr[6:0]; + 13: arw_addr = cl_ddr1_araddr[13:7]; + 14: arw_addr = cl_ddr1_araddr[20:14]; + 15: arw_addr = cl_ddr1_araddr[27:21]; + 16: arw_addr = cl_ddr1_araddr[34:28]; + 17: arw_addr = cl_ddr1_araddr[41:35]; + 18: arw_addr = cl_ddr1_awaddr[6:0]; + 19: arw_addr = cl_ddr1_awaddr[13:7]; + 20: arw_addr = cl_ddr1_awaddr[20:14]; + 21: arw_addr = cl_ddr1_awaddr[27:21]; + 22: arw_addr = cl_ddr1_awaddr[34:28]; + 23: arw_addr = cl_ddr1_awaddr[41:35]; + 24: arw_addr = cl_ddr2_araddr[6:0]; + 25: arw_addr = cl_ddr2_araddr[13:7]; + 26: arw_addr = cl_ddr2_araddr[20:14]; + 27: arw_addr = cl_ddr2_araddr[27:21]; + 28: arw_addr = cl_ddr2_araddr[34:28]; + 29: arw_addr = cl_ddr2_araddr[41:35]; + 30: arw_addr = cl_ddr2_awaddr[6:0]; + 31: arw_addr = cl_ddr2_awaddr[13:7]; + 32: arw_addr = cl_ddr2_awaddr[20:14]; + 33: arw_addr = cl_ddr2_awaddr[27:21]; + 34: arw_addr = cl_ddr2_awaddr[34:28]; + 35: arw_addr = cl_ddr2_awaddr[41:35]; + 36: arw_addr = cl_ddr3_araddr[6:0]; + 37: arw_addr = cl_ddr3_araddr[13:7]; + 38: arw_addr = cl_ddr3_araddr[20:14]; + 39: arw_addr = cl_ddr3_araddr[27:21]; + 40: arw_addr = cl_ddr3_araddr[34:28]; + 41: arw_addr = cl_ddr3_araddr[41:35]; + 42: arw_addr = cl_ddr3_awaddr[6:0]; + 43: arw_addr = cl_ddr3_awaddr[13:7]; + 44: arw_addr = cl_ddr3_awaddr[20:14]; + 45: arw_addr = cl_ddr3_awaddr[27:21]; + 46: arw_addr = cl_ddr3_awaddr[34:28]; + 47: arw_addr = cl_ddr3_awaddr[41:35]; + 48: arw_addr = cl_ddr4_araddr[6:0]; + 49: arw_addr = cl_ddr4_araddr[13:7]; + 50: arw_addr = cl_ddr4_araddr[20:14]; + 51: arw_addr = cl_ddr4_araddr[27:21]; + 52: arw_addr = cl_ddr4_araddr[34:28]; + 53: arw_addr = cl_ddr4_araddr[41:35]; + 54: arw_addr = cl_ddr4_awaddr[6:0]; + 55: arw_addr = cl_ddr4_awaddr[13:7]; + 56: arw_addr = cl_ddr4_awaddr[20:14]; + 57: arw_addr = cl_ddr4_awaddr[27:21]; + 58: arw_addr = cl_ddr4_awaddr[34:28]; + 59: arw_addr = cl_ddr4_awaddr[41:35]; + default: arw_addr = {AXI_ADDR_WIDTH{1'b0}}; + endcase + end + +logic [INST_DATA_WIDTH-1:0] pci_cl_data_wdata; +RandomNumberGenerator #( + .RANDOM_WIDTH(INST_DATA_WIDTH), + .SEED(0) +) rng0 ( + .clk(clk), + .reset(reset), + .random_number(pci_cl_data_wdata) +); + +logic [INST_WSTRB_WIDTH-1:0] pci_cl_data_wstrb; +logic [CTRL_ADDR_WIDTH-1:0] pci_cl_ctrl_awaddr; +logic [CTRL_DATA_WIDTH-1:0] pci_cl_ctrl_wdata; +logic [CTRL_WSTRB_WIDTH-1:0] pci_cl_ctrl_wstrb; +logic [CTRL_ADDR_WIDTH-1:0] pci_cl_ctrl_araddr; +logic [INST_ADDR_WIDTH-1:0] pci_cl_data_awaddr; +logic [INST_BURST_WIDTH-1:0] pci_cl_data_awlen; +logic [INST_ADDR_WIDTH-1:0] pci_cl_data_araddr; +logic [INST_BURST_WIDTH-1:0] pci_cl_data_arlen; +logic [IBUF_AXI_DATA_WIDTH-1:0] cl_ddr0_rdata; +logic [AXI_ID_WIDTH-1:0] cl_ddr0_rid; +logic [OBUF_AXI_DATA_WIDTH-1:0] cl_ddr1_rdata; +logic [AXI_ID_WIDTH-1:0] cl_ddr1_rid; +logic [WBUF_AXI_DATA_WIDTH-1:0] cl_ddr2_rdata; +logic [AXI_ID_WIDTH-1:0] cl_ddr2_rid; +logic [BBUF_AXI_DATA_WIDTH-1:0] cl_ddr3_rdata; +logic [AXI_ID_WIDTH-1:0] cl_ddr3_rid; +logic [PU_AXI_DATA_WIDTH-1:0] cl_ddr4_rdata; +logic [AXI_ID_WIDTH-1:0] cl_ddr4_rid; + +RandomNumberGenerator #( + .RANDOM_WIDTH(INST_WSTRB_WIDTH), + .SEED(1) +) rng1 ( + .clk(clk), + .reset(reset), + .random_number(pci_cl_data_wstrb) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(CTRL_ADDR_WIDTH), + .SEED(2) +) rng2 ( + .clk(clk), + .reset(reset), + .random_number(pci_cl_ctrl_awaddr) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(CTRL_DATA_WIDTH), + .SEED(3) +) rng3 ( + .clk(clk), + .reset(reset), + .random_number(pci_cl_ctrl_wdata) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(CTRL_WSTRB_WIDTH), + .SEED(4) +) rng4 ( + .clk(clk), + .reset(reset), + .random_number(pci_cl_ctrl_wstrb) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(CTRL_ADDR_WIDTH), + .SEED(5) +) rng5 ( + .clk(clk), + .reset(reset), + .random_number(pci_cl_ctrl_araddr) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(INST_ADDR_WIDTH), + .SEED(6) +) rng6 ( + .clk(clk), + .reset(reset), + .random_number(pci_cl_data_awaddr) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(INST_BURST_WIDTH), + .SEED(7) +) rng7 ( + .clk(clk), + .reset(reset), + .random_number(pci_cl_data_awlen) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(INST_ADDR_WIDTH), + .SEED(8) +) rng8 ( + .clk(clk), + .reset(reset), + .random_number(pci_cl_data_araddr) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(INST_BURST_WIDTH), + .SEED(9) +) rng9 ( + .clk(clk), + .reset(reset), + .random_number(pci_cl_data_arlen) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(IBUF_AXI_DATA_WIDTH), + .SEED(10) +) rng10 ( + .clk(clk), + .reset(reset), + .random_number(cl_ddr0_rdata) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(AXI_ID_WIDTH), + .SEED(11) +) rng11 ( + .clk(clk), + .reset(reset), + .random_number(cl_ddr0_rid) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(OBUF_AXI_DATA_WIDTH), + .SEED(12) +) rng12 ( + .clk(clk), + .reset(reset), + .random_number(cl_ddr1_rdata) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(AXI_ID_WIDTH), + .SEED(13) +) rng13 ( + .clk(clk), + .reset(reset), + .random_number(cl_ddr1_rid) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(WBUF_AXI_DATA_WIDTH), + .SEED(14) +) rng14 ( + .clk(clk), + .reset(reset), + .random_number(cl_ddr2_rdata) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(AXI_ID_WIDTH), + .SEED(15) +) rng15 ( + .clk(clk), + .reset(reset), + .random_number(cl_ddr2_rid) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(BBUF_AXI_DATA_WIDTH), + .SEED(16) +) rng16 ( + .clk(clk), + .reset(reset), + .random_number(cl_ddr3_rdata) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(AXI_ID_WIDTH), + .SEED(17) +) rng17 ( + .clk(clk), + .reset(reset), + .random_number(cl_ddr3_rid) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(PU_AXI_DATA_WIDTH), + .SEED(18) +) rng18 ( + .clk(clk), + .reset(reset), + .random_number(cl_ddr4_rdata) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(AXI_ID_WIDTH), + .SEED(19) +) rng19 ( + .clk(clk), + .reset(reset), + .random_number(cl_ddr4_rid) +); + + + + +cl_wrapper #( + .INST_W(INST_W), + .INST_ADDR_W(INST_ADDR_W), + .IFIFO_ADDR_W(IFIFO_ADDR_W), + .BUF_TYPE_W(BUF_TYPE_W), + .OP_CODE_W(OP_CODE_W), + .OP_SPEC_W(OP_SPEC_W), + .LOOP_ID_W(LOOP_ID_W), + .ARRAY_N(ARRAY_N), + .ARRAY_M(ARRAY_M), + .DATA_WIDTH(DATA_WIDTH), + .BIAS_WIDTH(BIAS_WIDTH), + .ACC_WIDTH(ACC_WIDTH), + .NUM_TAGS(NUM_TAGS), + .IBUF_CAPACITY_BITS(IBUF_CAPACITY_BITS), + .WBUF_CAPACITY_BITS(WBUF_CAPACITY_BITS), + .OBUF_CAPACITY_BITS(OBUF_CAPACITY_BITS), + .BBUF_CAPACITY_BITS(BBUF_CAPACITY_BITS), + .IBUF_ADDR_WIDTH(IBUF_ADDR_WIDTH), + .WBUF_ADDR_WIDTH(WBUF_ADDR_WIDTH), + .OBUF_ADDR_WIDTH(OBUF_ADDR_WIDTH), + .BBUF_ADDR_WIDTH(BBUF_ADDR_WIDTH), + .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), + .AXI_BURST_WIDTH(AXI_BURST_WIDTH), + .IBUF_AXI_DATA_WIDTH(IBUF_AXI_DATA_WIDTH), + .IBUF_WSTRB_W(IBUF_WSTRB_W), + .OBUF_AXI_DATA_WIDTH(OBUF_AXI_DATA_WIDTH), + .OBUF_WSTRB_W(OBUF_WSTRB_W), + .PU_AXI_DATA_WIDTH(PU_AXI_DATA_WIDTH), + .PU_WSTRB_W(PU_WSTRB_W), + .WBUF_AXI_DATA_WIDTH(WBUF_AXI_DATA_WIDTH), + .WBUF_WSTRB_W(WBUF_WSTRB_W), + .BBUF_AXI_DATA_WIDTH(BBUF_AXI_DATA_WIDTH), + .BBUF_WSTRB_W(BBUF_WSTRB_W), + .AXI_ID_WIDTH(AXI_ID_WIDTH), + .INST_ADDR_WIDTH(INST_ADDR_WIDTH), + .INST_DATA_WIDTH(INST_DATA_WIDTH), + .INST_WSTRB_WIDTH(INST_WSTRB_WIDTH), + .INST_BURST_WIDTH(INST_BURST_WIDTH), + .CTRL_ADDR_WIDTH(CTRL_ADDR_WIDTH), + .CTRL_DATA_WIDTH(CTRL_DATA_WIDTH), + .CTRL_WSTRB_WIDTH(CTRL_WSTRB_WIDTH) +) dnnweaver_wrapped( + clk, + reset, + pci_cl_ctrl_awvalid, + pci_cl_ctrl_awaddr, + pci_cl_ctrl_awready, + // Slave Write data + pci_cl_ctrl_wvalid, + pci_cl_ctrl_wdata, + pci_cl_ctrl_wstrb, + pci_cl_ctrl_wready, + //Write response + pci_cl_ctrl_bvalid, + pci_cl_ctrl_bresp, + pci_cl_ctrl_bready, + //Read address + pci_cl_ctrl_arvalid, + pci_cl_ctrl_araddr, + pci_cl_ctrl_arready, + //Read data/response + pci_cl_ctrl_rvalid, + pci_cl_ctrl_rdata, + pci_cl_ctrl_rresp, + pci_cl_ctrl_rready, + + // PCIe-> CL_wrapper AXI4 interface + // Slave Interface Write Address + pci_cl_data_awaddr, + pci_cl_data_awlen, + pci_cl_data_awsize, + pci_cl_data_awburst, + pci_cl_data_awvalid, + pci_cl_data_awready, + // Slave Interface Write Data + pci_cl_data_wdata, + pci_cl_data_wstrb, + pci_cl_data_wlast, + pci_cl_data_wvalid, + pci_cl_data_wready, + // Slave Interface Write Response + pci_cl_data_bresp, + pci_cl_data_bvalid, + pci_cl_data_bready, + // Slave Interface Read Address + pci_cl_data_araddr, + pci_cl_data_arlen, + pci_cl_data_arsize, + pci_cl_data_arburst, + pci_cl_data_arvalid, + pci_cl_data_arready, + // Slave Interface Read Data + pci_cl_data_rdata, + pci_cl_data_rresp, + pci_cl_data_rlast, + pci_cl_data_rvalid, + pci_cl_data_rready, + + // CL_wrapper-> DDR0 AXI4 interface + // Master Interface Write Address + cl_ddr0_awaddr, + cl_ddr0_awlen, + cl_ddr0_awsize, + cl_ddr0_awburst, + cl_ddr0_awvalid, + cl_ddr0_awready, + // Master Interface Write Data + cl_ddr0_wdata, + cl_ddr0_wstrb, + cl_ddr0_wlast, + cl_ddr0_wvalid, + cl_ddr0_wready, + // Master Interface Write Response + cl_ddr0_bresp, + cl_ddr0_bvalid, + cl_ddr0_bready, + // Master Interface Read Address + cl_ddr0_araddr, + cl_ddr0_arlen, + cl_ddr0_arsize, + cl_ddr0_arburst, + cl_ddr0_arvalid, + cl_ddr0_arid, + cl_ddr0_arready, + // Master Interface Read Data + cl_ddr0_rdata, + cl_ddr0_rid, + cl_ddr0_rresp, + cl_ddr0_rlast, + cl_ddr0_rvalid, + cl_ddr0_rready, + + // CL_wrapper-> DDR1 AXI4 interface + // Master Interface Write Address + cl_ddr1_awaddr, + cl_ddr1_awlen, + cl_ddr1_awsize, + cl_ddr1_awburst, + cl_ddr1_awvalid, + cl_ddr1_awready, + // Master Interface Write Data + cl_ddr1_wdata, + cl_ddr1_wstrb, + cl_ddr1_wlast, + cl_ddr1_wvalid, + cl_ddr1_wready, + // Master Interface Write Response + cl_ddr1_bresp, + cl_ddr1_bvalid, + cl_ddr1_bready, + // Master Interface Read Address + cl_ddr1_araddr, + cl_ddr1_arlen, + cl_ddr1_arsize, + cl_ddr1_arburst, + cl_ddr1_arvalid, + cl_ddr1_arid, + cl_ddr1_arready, + // Master Interface Read Data + cl_ddr1_rdata, + cl_ddr1_rid, + cl_ddr1_rresp, + cl_ddr1_rlast, + cl_ddr1_rvalid, + cl_ddr1_rready, + + // CL_wrapper-> DDR2 AXI4 interface + // Master Interface Write Address + cl_ddr2_awaddr, + cl_ddr2_awlen, + cl_ddr2_awsize, + cl_ddr2_awburst, + cl_ddr2_awvalid, + cl_ddr2_awready, + // Master Interface Write Data + cl_ddr2_wdata, + cl_ddr2_wstrb, + cl_ddr2_wlast, + cl_ddr2_wvalid, + cl_ddr2_wready, + // Master Interface Write Response + cl_ddr2_bresp, + cl_ddr2_bvalid, + cl_ddr2_bready, + // Master Interface Read Address + cl_ddr2_araddr, + cl_ddr2_arlen, + cl_ddr2_arsize, + cl_ddr2_arburst, + cl_ddr2_arvalid, + cl_ddr2_arid, + cl_ddr2_arready, + // Master Interface Read Data + cl_ddr2_rdata, + cl_ddr2_rid, + cl_ddr2_rresp, + cl_ddr2_rlast, + cl_ddr2_rvalid, + cl_ddr2_rready, + + // CL_wrapper-> DDR3 AXI4 interface + // Master Interface Write Address + cl_ddr3_awaddr, + cl_ddr3_awlen, + cl_ddr3_awsize, + cl_ddr3_awburst, + cl_ddr3_awvalid, + cl_ddr3_awready, + // Master Interface Write Data + cl_ddr3_wdata, + cl_ddr3_wstrb, + cl_ddr3_wlast, + cl_ddr3_wvalid, + cl_ddr3_wready, + // Master Interface Write Response + cl_ddr3_bresp, + cl_ddr3_bvalid, + cl_ddr3_bready, + // Master Interface Read Address + cl_ddr3_araddr, + cl_ddr3_arlen, + cl_ddr3_arsize, + cl_ddr3_arburst, + cl_ddr3_arvalid, + cl_ddr3_arid, + cl_ddr3_arready, + // Master Interface Read Data + cl_ddr3_rdata, + cl_ddr3_rid, + cl_ddr3_rresp, + cl_ddr3_rlast, + cl_ddr3_rvalid, + cl_ddr3_rready, + + + // CL_wrapper-> DDR3 AXI4 interface + // Master Interface Write Address + cl_ddr4_awaddr, + cl_ddr4_awlen, + cl_ddr4_awsize, + cl_ddr4_awburst, + cl_ddr4_awvalid, + cl_ddr4_awready, + // Master Interface Write Data + cl_ddr4_wdata, + cl_ddr4_wstrb, + cl_ddr4_wlast, + cl_ddr4_wvalid, + cl_ddr4_wready, + // Master Interface Write Response + cl_ddr4_bresp, + cl_ddr4_bvalid, + cl_ddr4_bready, + // Master Interface Read Address + cl_ddr4_araddr, + cl_ddr4_arlen, + cl_ddr4_arsize, + cl_ddr4_arburst, + cl_ddr4_arvalid, + cl_ddr4_arid, + cl_ddr4_arready, + // Master Interface Read Data + cl_ddr4_rdata, + cl_ddr4_rid, + cl_ddr4_rresp, + cl_ddr4_rlast, + cl_ddr4_rvalid, + cl_ddr4_rready +); + +endmodule \ No newline at end of file diff --git a/designs/koios/dnnweaver/design.yaml b/designs/koios/dnnweaver/design.yaml new file mode 100644 index 000000000..b6a7fa2a7 --- /dev/null +++ b/designs/koios/dnnweaver/design.yaml @@ -0,0 +1 @@ +top: cl_wrapper_random diff --git a/designs/koios/dnnweaver/dnnweaver.v b/designs/koios/dnnweaver/dnnweaver.v new file mode 100644 index 000000000..06cfcc584 --- /dev/null +++ b/designs/koios/dnnweaver/dnnweaver.v @@ -0,0 +1,14842 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Aman Arora +////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////// +// This benchmark is derived from the RTL provided with DNNWeaver 2.0 (http://dnnweaver.org/) +////////////////////////////////////////////////////////////////////////////// +`timescale 1ns/1ps +module ram +#( + parameter integer DATA_WIDTH = 10, + parameter integer ADDR_WIDTH = 12, + parameter integer OUTPUT_REG = 0 +) +( + input wire clk, + input wire reset, + + input wire s_read_req, + input wire [ ADDR_WIDTH -1 : 0 ] s_read_addr, + output wire [ DATA_WIDTH -1 : 0 ] s_read_data, + + input wire s_write_req, + input wire [ ADDR_WIDTH -1 : 0 ] s_write_addr, + input wire [ DATA_WIDTH -1 : 0 ] s_write_data +); + + //reg [ DATA_WIDTH -1 : 0 ] mem [ 0 : 1< RD_DATA_WIDTH) begin: WR_GT_RD + reg [ FIFO_ID_W -1 : 0 ] rd_ptr; + reg [ FIFO_ID_W -1 : 0 ] rd_ptr_dly; + + + assign s_read_ready = local_s_read_ready[rd_ptr]; + assign s_write_ready = &local_s_write_ready; + assign almost_empty = local_almost_empty[rd_ptr]; + assign almost_full = |local_almost_full; + + always @(posedge clk) begin + if (reset) + rd_ptr <= 0; + else if (s_read_req && s_read_ready) begin + if (rd_ptr == NUM_FIFO-1) + rd_ptr <= 0; + else + rd_ptr <= rd_ptr + 1'b1; + end + end + + always @(posedge clk) begin + if (s_read_req && s_read_ready) + rd_ptr_dly <= rd_ptr; + end + + for (i=0; i= BURST_LEN) ? BURST_LEN-1: (rx_size_q-1); + rx_size_d = rx_size_q >= BURST_LEN ? rx_size_d - BURST_LEN : 0; + end + end + AR_WAIT: begin + arvalid_d = wdata_req_buf_wr_ready; + if (m_axi_arvalid && m_axi_arready) begin + arvalid_d = 1'b0; + araddr_offset_d = araddr_offset_q + BURST_LEN * AXI_DATA_WIDTH / 8; + if (rx_size_q == 0) begin + ar_state_d = AR_IDLE; + end + else begin + ar_state_d = AR_SEND; + end + end + end + endcase + end + + always @(posedge clk) + begin + if (reset) begin + arlen_q <= 0; + arvalid_q <= 1'b0; + ar_state_q <= AR_IDLE; + araddr_offset_q <= 'b0; + rx_size_q <= 0; + arid_q <= 0; + end else begin + arlen_q <= arlen_d; + arvalid_q <= arvalid_d; + ar_state_q <= ar_state_d; + araddr_offset_q <= araddr_offset_d; + rx_size_q <= rx_size_d; + arid_q <= arid_d; + end + end + + // + //The FIFO stores the read requests + // + fifo #( + .DATA_WIDTH ( REQ_BUF_DATA_W ), + .ADDR_WIDTH ( 3 ) + ) rd_req_buf ( + .clk ( clk ), //input + .reset ( reset ), //input + .s_read_req ( rd_req_buf_pop ), //input + .s_read_ready ( rd_req_buf_rd_ready ), //output + .s_read_data ( rd_req_buf_data_out ), //output + .s_write_req ( rd_req_buf_push ), //input + .s_write_ready ( rd_req_buf_wr_ready ), //output + .s_write_data ( rd_req_buf_data_in ), //input + .almost_full ( rd_req_buf_almost_full ), //output + .almost_empty ( rd_req_buf_almost_empty ) //output + ); +//============================================================================== + +//============================================================================== +// Read channel +//============================================================================== + + localparam integer R_IDLE = 0; + localparam integer R_READ = 1; + + reg r_state_d; + reg r_state_q; + + assign rx_req_id_buf_push = (ar_state_q == AR_SEND) && ~rx_req_id_buf_almost_full; + assign rx_req_id_buf_data_in = arid_q; + assign rx_req_id_buf_pop = r_state_q == R_IDLE; + assign mem_write_id = rx_req_id_buf_data_out; + // + //The FIFO stores the read request IDs + // + fifo #( + .DATA_WIDTH ( AXI_ID_WIDTH ), + .ADDR_WIDTH ( 5 ) + ) rx_req_id_buf ( + .clk ( clk ), //input + .reset ( reset ), //input + .s_read_req ( rx_req_id_buf_pop ), //input + .s_read_ready ( rx_req_id_buf_rd_ready ), //output + .s_read_data ( rx_req_id_buf_data_out ), //output + .s_write_req ( rx_req_id_buf_push ), //input + .s_write_ready ( rx_req_id_buf_wr_ready ), //output + .s_write_data ( rx_req_id_buf_data_in ), //input + .almost_full ( rx_req_id_buf_almost_full ), //output + .almost_empty ( rx_req_id_buf_almost_empty ) //output + ); + + + always @(*) + begin + r_state_d = r_state_q; + case (r_state_q) + R_IDLE: begin + if (rx_req_id_buf_rd_ready) + r_state_d = R_READ; + end + R_READ: begin + if (m_axi_rready && m_axi_rlast) + r_state_d = R_IDLE; + end + endcase + end + + always @(posedge clk) + begin + if (reset) + r_state_q <= R_IDLE; + else + r_state_q <= r_state_d; + end + + // Read and Read Response (R) + assign m_axi_rready = rready; + assign rready = (AXI_SUPPORTS_READ == 1) && mem_write_ready && r_state_q == R_READ; + assign rnext = m_axi_rvalid && m_axi_rready; +//============================================================================== + +//============================================================================== +// CL - read ready +//============================================================================== + wire rburst_complete; + wire rburst_req; + assign rburst_complete = m_axi_rlast && m_axi_rready; + assign rburst_req = ar_state_q == AR_SEND && ~rx_req_id_buf_almost_full; + + always @(posedge clk) + begin + if (reset) + axi_outstanding_reads <= 0; + else if (rburst_req && ~rburst_complete) + axi_outstanding_reads <= axi_outstanding_reads + 1'b1; + else if (!rburst_req && rburst_complete) + axi_outstanding_reads <= axi_outstanding_reads - 1'b1; + end + + always @(posedge clk) + begin + rd_done_q <= (axi_outstanding_reads == 0 && ar_state_q == AR_IDLE); + end + assign rd_done = rd_done_q && ~rd_req_buf_rd_ready; +//============================================================================== + +//============================================================================== +// CL - write ready +//============================================================================== + wire wburst_complete; + wire wburst_req; + + reg [ 2 -1 : 0 ] aw_state_d; + reg [ 2 -1 : 0 ] aw_state_q; + + localparam integer AW_IDLE = 0; + localparam integer AW_REQ_READ = 1; + localparam integer AW_SEND = 2; + localparam integer AW_WAIT = 3; + + assign wburst_complete = m_axi_wlast && m_axi_wready; + assign wburst_req = aw_state_q == AW_SEND && ~wdata_req_buf_almost_full; + always @(posedge clk) + begin + if (reset) + axi_outstanding_writes <= 0; + else if (wburst_req && ~wburst_complete) + axi_outstanding_writes <= axi_outstanding_writes + 1'b1; + else if (!wburst_req && wburst_complete) + axi_outstanding_writes <= axi_outstanding_writes - 1'b1; + end + + always @(posedge clk) + begin + wr_done_q <= axi_outstanding_writes == 0 && aw_state_q == AW_IDLE; + end + assign wr_done = wr_done_q; +//============================================================================== + +//============================================================================== +// AW channel +//============================================================================== + assign wr_req_buf_pop = aw_state_q == AW_IDLE; + assign wr_req_buf_push = wr_req; + assign wr_ready = ~wr_req_buf_almost_full; + assign wr_req_buf_data_in = {wr_req_size, wr_addr}; + assign {wx_req_size_buf, wx_addr_buf} = wr_req_buf_data_out; + + always @(*) + begin + aw_state_d = aw_state_q; + awaddr_offset_d = awaddr_offset_q; + awvalid_d = awvalid_q; + wx_size_d = wx_size_q; + awlen_d = awlen_q; + case(aw_state_q) + AW_IDLE: begin + if (wr_req_buf_rd_ready) + aw_state_d = AW_REQ_READ; + end + AW_REQ_READ: begin + aw_state_d = AW_SEND; + awaddr_offset_d = wx_addr_buf; + wx_size_d = wx_req_size_buf; + end + AW_SEND: begin + if (~wdata_req_buf_almost_full) begin + awvalid_d = 1'b1; + aw_state_d = AW_WAIT; + awlen_d = (wx_size_q >= BURST_LEN) ? BURST_LEN-1: (wx_size_q-1); + wx_size_d = wx_size_q >= BURST_LEN ? wx_size_d - BURST_LEN : 0; + end + end + AW_WAIT: begin + if (m_axi_awvalid && m_axi_awready) begin + awvalid_d = 1'b0; + awaddr_offset_d = awaddr_offset_q + BURST_LEN * AXI_DATA_WIDTH / 8; + if (wx_size_q == 0) begin + aw_state_d = AW_IDLE; + end + else begin + aw_state_d = AW_SEND; + end + end + end + endcase + end + + assign m_axi_awvalid = awvalid_q; + assign m_axi_awlen = awlen_q; + assign m_axi_awaddr = {wx_addr_buf[AXI_ADDR_WIDTH-1:C_OFFSET_WIDTH], awaddr_offset_q}; + + always @(posedge clk) + begin + if (reset) begin + awlen_q <= 0; + awvalid_q <= 1'b0; + aw_state_q <= AR_IDLE; + awaddr_offset_q <= 'b0; + wx_size_q <= 0; + end else begin + awlen_q <= awlen_d; + awvalid_q <= awvalid_d; + aw_state_q <= aw_state_d; + awaddr_offset_q <= awaddr_offset_d; + wx_size_q <= wx_size_d; + end + end + + // + //The FIFO stores the read requests + // + fifo #( + .DATA_WIDTH ( REQ_BUF_DATA_W ), + .ADDR_WIDTH ( 4 ) + ) awr_req_buf ( + .clk ( clk ), //input + .reset ( reset ), //input + .s_read_req ( wr_req_buf_pop ), //input + .s_read_ready ( wr_req_buf_rd_ready ), //output + .s_read_data ( wr_req_buf_data_out ), //output + .s_write_req ( wr_req_buf_push ), //input + .s_write_ready ( wr_req_buf_wr_ready ), //output + .s_write_data ( wr_req_buf_data_in ), //input + .almost_full ( wr_req_buf_almost_full ), //output + .almost_empty ( wr_req_buf_almost_empty ) //output + ); +//============================================================================== + +//============================================================================== +// Write Data (W) Channel +//============================================================================== + reg [ 2 -1 : 0 ] w_state_d; + reg [ 2 -1 : 0 ] w_state_q; + + reg [ AXI_BURST_WIDTH -1 : 0 ] wlen_count_d; + reg [ AXI_BURST_WIDTH -1 : 0 ] wlen_count_q; + + localparam integer W_IDLE = 0; + localparam integer W_WAIT = 1; + localparam integer W_SEND = 2; + + always @(*) + begin + w_state_d = w_state_q; + wlen_count_d = wlen_count_q; + case(w_state_q) + W_IDLE: begin + if (wdata_req_buf_rd_ready && mem_read_ready) + w_state_d = W_SEND; + end + W_SEND: begin + if (m_axi_wready) begin + if (~m_axi_wlast) + wlen_count_d = wlen_count_q + mem_read_valid_q; + else begin + wlen_count_d = 0; + w_state_d = W_IDLE; + end + end + end + endcase + end + + assign m_axi_wlast = (wlen_count_q == wdata_req_buf_data_out) && mem_read_valid_q; + assign m_axi_wvalid = mem_read_valid_q; + assign m_axi_wdata = mem_read_data; + // assign m_axi_wdata = 'b0; + assign mem_read_req = mem_read_ready && (w_state_q != W_IDLE) && ~m_axi_wlast && (~mem_read_valid_q || m_axi_wready); + + always @(posedge clk) + begin + if (reset) + mem_read_valid_q <= 1'b0; + else + mem_read_valid_q <= mem_read_valid_d; + end + + always @(*) + begin + mem_read_valid_d = mem_read_valid_q; + case (mem_read_valid_q) + 0: begin + if (mem_read_req) + mem_read_valid_d = 1; + end + 1: begin + if (m_axi_wready && ~mem_read_req) + mem_read_valid_d = 0; + end + endcase + end + + always @(posedge clk) + begin + if (reset) begin + wlen_count_q <= 0; + w_state_q <= W_IDLE; + end + else begin + wlen_count_q <= wlen_count_d; + w_state_q <= w_state_d; + end + end + + assign wdata_req_buf_pop = w_state_q == W_IDLE && mem_read_ready; + assign wdata_req_buf_push = m_axi_awvalid && m_axi_awready; + assign wdata_req_buf_data_in = m_axi_awlen; + + // + //The FIFO stores the read requests + // + fifo #( + .DATA_WIDTH ( AXI_BURST_WIDTH ), + .ADDR_WIDTH ( 4 ) + ) wdata_req_buf ( + .clk ( clk ), //input + .reset ( reset ), //input + .s_read_req ( wdata_req_buf_pop ), //input + .s_read_ready ( wdata_req_buf_rd_ready ), //output + .s_read_data ( wdata_req_buf_data_out ), //output + .s_write_req ( wdata_req_buf_push ), //input + .s_write_ready ( wdata_req_buf_wr_ready ), //output + .s_write_data ( wdata_req_buf_data_in ), //input + .almost_full ( wdata_req_buf_almost_full ), //output + .almost_empty ( wdata_req_buf_almost_empty ) //output + ); +//============================================================================== + + + +`ifdef COCOTB_SIM + +reg [15:0] _rid_mismatch_count; +always @(posedge clk) +begin + if (reset) + _rid_mismatch_count <= 0; + else if (m_axi_rvalid && m_axi_rready) + _rid_mismatch_count <= (m_axi_rid != mem_write_id) + _rid_mismatch_count; +end + + integer missed_wdata_push; + always @(posedge clk) + if (reset) + missed_wdata_push <=0; + else + missed_wdata_push <= missed_wdata_push + (wdata_req_buf_push && ~wdata_req_buf_wr_ready); + + + integer missed_wr_req_count; + always @(posedge clk) + if (reset) + missed_wr_req_count <=0; + else + missed_wr_req_count <=wr_req && ~wr_req_buf_wr_ready; + + integer wr_req_count; + always @(posedge clk) + if (reset) + wr_req_count <=0; + else + wr_req_count <=wr_req_count + (wr_req && wr_ready); +`endif //COCOTB_SIM + + +`ifdef COCOTB_TOPLEVEL_axi_master + initial + begin + $dumpfile("axi_master.vcd"); + $dumpvars(0,axi_master); + end +`endif + +endmodule +// +// Tag logic for double buffering +// +// Hardik Sharma +// (hsharma@gatech.edu) + +`timescale 1ns/1ps +module tag_logic #( + parameter integer STORE_ENABLED = 1 +) +( + input wire clk, + input wire reset, + input wire tag_req, + input wire tag_reuse, + input wire tag_bias_prev_sw, + input wire tag_ddr_pe_sw, + output wire tag_ready, + output wire tag_done, + input wire tag_flush, + input wire compute_tag_done, + output wire next_compute_tag, +// output wire compute_tag_reuse, + output wire compute_bias_prev_sw, + output wire compute_tag_ready, + input wire ldmem_tag_done, + output wire ldmem_tag_ready, + input wire stmem_tag_done, + output wire stmem_ddr_pe_sw, + output wire stmem_tag_ready +); + +//============================================================================== +// Wires/Regs +//============================================================================== + localparam integer TAG_FREE = 0; + localparam integer TAG_LDMEM = 1; + localparam integer TAG_COMPUTE = 2; + localparam integer TAG_COMPUTE_CHECK = 3; + localparam integer TAG_STMEM = 4; + + localparam integer TAG_STATE_W = 3; + + localparam integer REUSE_STATE_W = 1; + localparam integer REUSE_FALSE = 0; + localparam integer REUSE_TRUE = 1; + + reg tag_flush_state_d; + reg tag_flush_state_q; + reg tag_reuse_state_d; + reg tag_reuse_state_q; + + reg [2 : 0] tag_reuse_counter; + + reg tag_ddr_pe_sw_q; + reg compute_ddr_pe_sw; + reg _stmem_ddr_pe_sw; + reg tag_bias_prev_sw_q; + reg reuse_tag_bias_prev_sw_q; + reg [ TAG_STATE_W -1 : 0 ] tag_state_d; + reg [ TAG_STATE_W -1 : 0 ] tag_state_q; +//============================================================================== + +//============================================================================== +// Tag allocation +//============================================================================== + + assign tag_done = tag_state_q == TAG_FREE; + + assign ldmem_tag_ready = tag_state_q == TAG_LDMEM; + assign compute_tag_ready = tag_state_q == TAG_COMPUTE; + assign stmem_tag_ready = tag_state_q == TAG_STMEM; + assign tag_ready = tag_state_q == TAG_FREE; + + assign compute_bias_prev_sw = tag_bias_prev_sw_q; + assign stmem_ddr_pe_sw = _stmem_ddr_pe_sw; + + always @(*) + begin: TAG0_STATE + tag_state_d = tag_state_q; + case (tag_state_q) + TAG_FREE: begin + if (tag_req) begin + tag_state_d = TAG_LDMEM; + end + end + TAG_LDMEM: begin + if (ldmem_tag_done) + tag_state_d = TAG_COMPUTE; + end + TAG_COMPUTE_CHECK: begin + if (tag_reuse_counter == 0 && tag_flush_state_q == 1) begin + if (STORE_ENABLED) + tag_state_d = TAG_STMEM; + else + tag_state_d = TAG_FREE; + end + else if (tag_reuse_counter != 0) + tag_state_d = TAG_COMPUTE; + end + TAG_COMPUTE: begin + if (compute_tag_done) + tag_state_d = TAG_COMPUTE_CHECK; + end + TAG_STMEM: begin + if (stmem_tag_done) + tag_state_d = TAG_FREE; + end + endcase + end + + always @(posedge clk) + begin + if (reset) begin + tag_state_q <= TAG_FREE; + end + else begin + tag_state_q <= tag_state_d; + end + end + + always @(*) + begin + tag_flush_state_d = tag_flush_state_q; + case (tag_flush_state_q) + 0: begin + if (tag_flush && tag_state_q != TAG_FREE) + tag_flush_state_d = 1; + end + 1: begin + if (tag_state_q == TAG_COMPUTE_CHECK && tag_reuse_counter == 0) + tag_flush_state_d = 0; + end + endcase + end + + always @(posedge clk) + begin + if (reset) + tag_flush_state_q <= 0; + else + tag_flush_state_q <= tag_flush_state_d; + end + + assign next_compute_tag = tag_state_q == TAG_COMPUTE_CHECK && tag_flush_state_q == 1 && tag_reuse_counter == 0; + + always @(posedge clk) + begin + if (reset) + tag_reuse_counter <= 0; + else begin + if (compute_tag_done && ~(tag_req || tag_reuse) && tag_reuse_counter != 0) + tag_reuse_counter <= tag_reuse_counter - 1'b1; + else if (~compute_tag_done && (tag_reuse || tag_req)) + tag_reuse_counter <= tag_reuse_counter + 1'b1; + end + end + + always @(posedge clk) + begin + if (reset) begin + compute_ddr_pe_sw <= 1'b0; + end else if (ldmem_tag_done || tag_state_q == TAG_COMPUTE_CHECK) begin + compute_ddr_pe_sw <= tag_ddr_pe_sw_q; + end + end + + always @(posedge clk) + begin + if (reset) begin + _stmem_ddr_pe_sw <= 1'b0; + end else if (compute_tag_done) begin + _stmem_ddr_pe_sw <= compute_ddr_pe_sw; + end + end + + always @(posedge clk) + begin + if (reset) begin + tag_bias_prev_sw_q <= 1'b0; + end + else if (tag_req && tag_ready) begin + tag_bias_prev_sw_q <= tag_bias_prev_sw; + end + else if (compute_tag_done) + tag_bias_prev_sw_q <= reuse_tag_bias_prev_sw_q; + end + + always @(posedge clk) + begin + if (reset) begin + tag_ddr_pe_sw_q <= 1'b0; + end + else if ((tag_req && tag_ready) || tag_reuse) begin + tag_ddr_pe_sw_q <= tag_ddr_pe_sw; + end + end + + always @(posedge clk) + if (reset) + reuse_tag_bias_prev_sw_q <= 1'b0; + else if (tag_reuse) + reuse_tag_bias_prev_sw_q <= tag_bias_prev_sw; +//============================================================================== + +//============================================================================== +// VCD +//============================================================================== +`ifdef COCOTB_TOPLEVEL_tag_logic +initial begin + $dumpfile("tag_logic.vcd"); + $dumpvars(0, tag_logic); +end +`endif +//============================================================================== + +endmodule +// +// Memory Walker - stride +// +// Hardik Sharma +// (hsharma@gatech.edu) + +`timescale 1ns/1ps +module mem_walker_stride #( + // Internal Parameters + parameter integer ADDR_WIDTH = 48, + parameter integer ADDR_STRIDE_W = 16, + parameter integer LOOP_ID_W = 5 +) ( + input wire clk, + input wire reset, + // From loop controller + input wire [ ADDR_WIDTH -1 : 0 ] base_addr, + input wire loop_ctrl_done, + input wire [ LOOP_ID_W -1 : 0 ] loop_index, + input wire loop_index_valid, + input wire loop_init, + input wire loop_enter, + input wire loop_exit, + // Address offset - from instruction decoder + input wire cfg_addr_stride_v, + input wire [ ADDR_STRIDE_W -1 : 0 ] cfg_addr_stride, + output wire [ ADDR_WIDTH -1 : 0 ] addr_out, + output wire addr_out_valid +); + +//============================================================= +// Wires/Regs +//============================================================= + reg [ LOOP_ID_W -1 : 0 ] addr_stride_wr_ptr; + wire addr_stride_wr_req; + wire [ ADDR_STRIDE_W -1 : 0 ] addr_stride_wr_data; + + wire [ LOOP_ID_W -1 : 0 ] addr_stride_rd_ptr; + wire addr_stride_rd_req; + wire [ ADDR_STRIDE_W -1 : 0 ] addr_stride_rd_data; + + wire [ LOOP_ID_W -1 : 0 ] addr_offset_wr_ptr; + wire addr_offset_wr_req; + wire [ ADDR_WIDTH -1 : 0 ] addr_offset_wr_data; + + wire [ LOOP_ID_W -1 : 0 ] addr_offset_rd_ptr; + wire addr_offset_rd_req; + wire [ ADDR_WIDTH -1 : 0 ] addr_offset_rd_data; + + wire [ ADDR_WIDTH -1 : 0 ] prev_addr; + + wire [ ADDR_WIDTH -1 : 0 ] offset_updated; + + reg [ ADDR_WIDTH -1 : 0 ] _addr_out; + wire _addr_out_valid; + + reg loop_enter_q; + +//============================================================= + +//============================================================= +// Address stride buffer +// This module stores the address strides +//============================================================= + always @(posedge clk) + begin:WR_PTR + if (reset) + addr_stride_wr_ptr <= 'b0; + else begin + if (cfg_addr_stride_v) + addr_stride_wr_ptr <= addr_stride_wr_ptr + 1'b1; + else if (loop_ctrl_done) + addr_stride_wr_ptr <= 'b0; + end + end + + assign addr_stride_wr_req = cfg_addr_stride_v; + assign addr_stride_wr_data = cfg_addr_stride; + + assign addr_stride_rd_ptr = loop_index; + assign addr_stride_rd_req = loop_index_valid || loop_enter; + + ram #( + .ADDR_WIDTH ( LOOP_ID_W ), + .DATA_WIDTH ( ADDR_STRIDE_W ) + ) stride_buf ( + .clk ( clk ), + .reset ( reset ), + .s_write_addr ( addr_stride_wr_ptr ), + .s_write_req ( addr_stride_wr_req ), + .s_write_data ( addr_stride_wr_data ), + .s_read_addr ( addr_stride_rd_ptr ), + .s_read_req ( addr_stride_rd_req ), + .s_read_data ( addr_stride_rd_data ) + ); + +//============================================================= + + +//============================================================= +// Offset buffer +// This module stores the current offset +//============================================================= + assign addr_offset_wr_ptr = cfg_addr_stride_v ? addr_stride_wr_ptr : loop_index; + assign addr_offset_wr_req = (cfg_addr_stride_v || loop_enter || loop_index_valid); + assign addr_offset_wr_data = cfg_addr_stride_v ? 'b0 : offset_updated; + assign prev_addr = loop_init ? base_addr : (loop_enter && loop_enter_q) ? addr_out : addr_offset_rd_data; + assign offset_updated = prev_addr + addr_stride_rd_data; + + assign addr_offset_rd_ptr = loop_index; + assign addr_offset_rd_req = loop_index_valid || loop_enter; + + ram #( + .ADDR_WIDTH ( LOOP_ID_W ), + .DATA_WIDTH ( ADDR_WIDTH ) + ) offset_buf ( + .clk ( clk ), + .reset ( reset ), + .s_write_addr ( addr_offset_wr_ptr ), + .s_write_req ( addr_offset_wr_req ), + .s_write_data ( addr_offset_wr_data ), + .s_read_addr ( addr_offset_rd_ptr ), + .s_read_req ( addr_offset_rd_req ), + .s_read_data ( addr_offset_rd_data ) + ); + +//============================================================= + + +//============================================================= +// Output address stride logic +//============================================================= + + assign _addr_out_valid = loop_index_valid; + + always @(posedge clk) + begin + if (reset) + loop_enter_q <= 1'b0; + else + loop_enter_q <= loop_enter; + end + + always @(posedge clk) + begin + if (reset) + _addr_out <= 0; + else if (loop_init) + _addr_out <= base_addr; + else if (loop_enter && !loop_enter_q) + _addr_out <= addr_offset_rd_data; + else if (loop_index_valid) + _addr_out <= _addr_out + addr_stride_rd_data; + end + + assign addr_out_valid = _addr_out_valid; + assign addr_out = _addr_out; +//============================================================= + + + +//============================================================= +// VCD +//============================================================= +`ifdef COCOTB_TOPLEVEL_mem_walker_stride +initial begin + $dumpfile("mem_walker_stride.vcd"); + $dumpvars(0, mem_walker_stride); +end +`endif +//============================================================= + +endmodule +// +// Tag logic for double buffering +// +// Hardik Sharma +// (hsharma@gatech.edu) + +`timescale 1ns/1ps +module tag_sync #( + parameter integer NUM_TAGS = 2, + parameter integer TAG_W = $clog2(NUM_TAGS), + parameter integer STORE_ENABLED = 1 +) +( + input wire clk, + input wire reset, + input wire block_done, + input wire tag_req, + input wire tag_reuse, + input wire tag_bias_prev_sw, + input wire tag_ddr_pe_sw, + output wire tag_ready, + output wire [ TAG_W -1 : 0 ] tag, + output wire tag_done, + input wire compute_tag_done, + output wire compute_tag_ready, + output wire compute_bias_prev_sw, + output wire [ TAG_W -1 : 0 ] compute_tag, + input wire ldmem_tag_done, + output wire ldmem_tag_ready, + output wire [ TAG_W -1 : 0 ] ldmem_tag, + input wire [ TAG_W -1 : 0 ] raw_stmem_tag, + output wire raw_stmem_tag_ready, + output wire stmem_ddr_pe_sw, + input wire stmem_tag_done, + output wire stmem_tag_ready, + output wire [ TAG_W -1 : 0 ] stmem_tag +); + +//============================================================================== +// Wires/Regs +//============================================================================== + reg [ TAG_W -1 : 0 ] prev_tag; + reg [ TAG_W -1 : 0 ] tag_alloc; + reg [ TAG_W -1 : 0 ] ldmem_tag_alloc; + reg [ TAG_W -1 : 0 ] compute_tag_alloc; + reg [ TAG_W -1 : 0 ] stmem_tag_alloc; + reg [ 2 -1 : 0 ] tag0_state_d; + reg [ 2 -1 : 0 ] tag0_state_q; + reg [ 2 -1 : 0 ] tag1_state_d; + reg [ 2 -1 : 0 ] tag1_state_q; + + wire next_compute_tag; + + wire [ NUM_TAGS -1 : 0 ] local_next_compute_tag; + wire [ NUM_TAGS -1 : 0 ] local_tag_ready; + wire [ NUM_TAGS -1 : 0 ] local_compute_tag_ready; +// wire [ NUM_TAGS -1 : 0 ] local_compute_tag_reuse; + wire [ NUM_TAGS -1 : 0 ] local_bias_prev_sw; + wire [ NUM_TAGS -1 : 0 ] local_stmem_ddr_pe_sw; + wire [ NUM_TAGS -1 : 0 ] local_ldmem_tag_ready; + wire [ NUM_TAGS -1 : 0 ] local_stmem_tag_ready; + + localparam integer TAG_FREE = 0; + localparam integer TAG_LDMEM = 1; + localparam integer TAG_COMPUTE = 2; + localparam integer TAG_STMEM = 3; + +// wire compute_tag_reuse; + + wire cache_hit; + wire cache_flush; +//============================================================================== + +//============================================================================== +// Tag allocation +//============================================================================== + + assign cache_hit = tag_reuse; + assign cache_flush = (tag_req && ~tag_reuse) || block_done; + + always @(posedge clk) + begin + if (reset) + tag_alloc <= 'b0; + else if (tag_req && tag_ready && ~cache_hit) begin + if (tag_alloc == NUM_TAGS-1) + tag_alloc <= 'b0; + else + tag_alloc <= tag_alloc + 1'b1; + end + end + always @(posedge clk) + begin + if (reset) + prev_tag <= 'b0; + else if (tag_req && tag_ready && ~cache_hit) begin + prev_tag <= tag_alloc; + end + end + + always @(posedge clk) + begin + if (reset) + ldmem_tag_alloc <= 'b0; + else if (ldmem_tag_done) + if (ldmem_tag_alloc == NUM_TAGS-1) + ldmem_tag_alloc <= 'b0; + else + ldmem_tag_alloc <= ldmem_tag_alloc + 1'b1; + end + + always @(posedge clk) + begin + if (reset) + compute_tag_alloc <= 'b0; + else if (next_compute_tag) + if (compute_tag_alloc == NUM_TAGS-1) + compute_tag_alloc <= 'b0; + else + compute_tag_alloc <= compute_tag_alloc + 1'b1; + end + + always @(posedge clk) + begin + if (reset) + stmem_tag_alloc <= 'b0; + else if (stmem_tag_done) + if (stmem_tag_alloc == NUM_TAGS-1) + stmem_tag_alloc <= 'b0; + else + stmem_tag_alloc <= stmem_tag_alloc + 1'b1; + end + + assign tag_done = &local_tag_ready; + + // Buffer hit/miss logic + assign tag = tag_reuse ? prev_tag: tag_alloc; + assign tag_ready = local_tag_ready[prev_tag] || local_tag_ready[tag_alloc]; + + assign next_compute_tag = local_next_compute_tag[compute_tag_alloc]; + + assign ldmem_tag = ldmem_tag_alloc; + assign compute_tag = compute_tag_alloc; + assign stmem_tag = stmem_tag_alloc; + + assign ldmem_tag_ready = local_ldmem_tag_ready[ldmem_tag]; + assign compute_tag_ready = local_compute_tag_ready[compute_tag]; + assign compute_bias_prev_sw = local_bias_prev_sw[compute_tag]; + assign stmem_ddr_pe_sw = local_stmem_ddr_pe_sw[stmem_tag]; + assign stmem_tag_ready = local_stmem_tag_ready[stmem_tag]; + + assign raw_stmem_tag_ready = local_stmem_tag_ready[raw_stmem_tag]; + +// assign compute_tag_reuse = local_compute_tag_reuse[compute_tag]; + + genvar t; + generate + for (t=0; t CL_wrapper AXI4-Lite interface + // Slave Write address + input wire pci_cl_ctrl_awvalid, + input wire [ CTRL_ADDR_WIDTH -1 : 0 ] pci_cl_ctrl_awaddr, + output wire pci_cl_ctrl_awready, + // Slave Write data + input wire pci_cl_ctrl_wvalid, + input wire [ CTRL_DATA_WIDTH -1 : 0 ] pci_cl_ctrl_wdata, + input wire [ CTRL_WSTRB_WIDTH -1 : 0 ] pci_cl_ctrl_wstrb, + output wire pci_cl_ctrl_wready, + //Write response + output wire pci_cl_ctrl_bvalid, + output wire [ 2 -1 : 0 ] pci_cl_ctrl_bresp, + input wire pci_cl_ctrl_bready, + //Read address + input wire pci_cl_ctrl_arvalid, + input wire [ CTRL_ADDR_WIDTH -1 : 0 ] pci_cl_ctrl_araddr, + output wire pci_cl_ctrl_arready, + //Read data/response + output wire pci_cl_ctrl_rvalid, + output wire [ CTRL_DATA_WIDTH -1 : 0 ] pci_cl_ctrl_rdata, + output wire [ 2 -1 : 0 ] pci_cl_ctrl_rresp, + input wire pci_cl_ctrl_rready, + + // PCIe -> CL_wrapper AXI4 interface + // Slave Interface Write Address + input wire [ INST_ADDR_WIDTH -1 : 0 ] pci_cl_data_awaddr, + input wire [ INST_BURST_WIDTH -1 : 0 ] pci_cl_data_awlen, + input wire [ 3 -1 : 0 ] pci_cl_data_awsize, + input wire [ 2 -1 : 0 ] pci_cl_data_awburst, + input wire pci_cl_data_awvalid, + output wire pci_cl_data_awready, + // Slave Interface Write Data + input wire [ INST_DATA_WIDTH -1 : 0 ] pci_cl_data_wdata, + input wire [ INST_WSTRB_WIDTH -1 : 0 ] pci_cl_data_wstrb, + input wire pci_cl_data_wlast, + input wire pci_cl_data_wvalid, + output wire pci_cl_data_wready, + // Slave Interface Write Response + output wire [ 2 -1 : 0 ] pci_cl_data_bresp, + output wire pci_cl_data_bvalid, + input wire pci_cl_data_bready, + // Slave Interface Read Address + input wire [ INST_ADDR_WIDTH -1 : 0 ] pci_cl_data_araddr, + input wire [ INST_BURST_WIDTH -1 : 0 ] pci_cl_data_arlen, + input wire [ 3 -1 : 0 ] pci_cl_data_arsize, + input wire [ 2 -1 : 0 ] pci_cl_data_arburst, + input wire pci_cl_data_arvalid, + output wire pci_cl_data_arready, + // Slave Interface Read Data + output wire [ INST_DATA_WIDTH -1 : 0 ] pci_cl_data_rdata, + output wire [ 2 -1 : 0 ] pci_cl_data_rresp, + output wire pci_cl_data_rlast, + output wire pci_cl_data_rvalid, + input wire pci_cl_data_rready, + + // CL_wrapper -> DDR0 AXI4 interface + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr0_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr0_awlen, + output wire [ 3 -1 : 0 ] cl_ddr0_awsize, + output wire [ 2 -1 : 0 ] cl_ddr0_awburst, + output wire cl_ddr0_awvalid, + input wire cl_ddr0_awready, + // Master Interface Write Data + output wire [ IBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr0_wdata, + output wire [ IBUF_WSTRB_W -1 : 0 ] cl_ddr0_wstrb, + output wire cl_ddr0_wlast, + output wire cl_ddr0_wvalid, + input wire cl_ddr0_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] cl_ddr0_bresp, + input wire cl_ddr0_bvalid, + output wire cl_ddr0_bready, + // Master Interface Read Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr0_araddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr0_arlen, + output wire [ 3 -1 : 0 ] cl_ddr0_arsize, + output wire [ 2 -1 : 0 ] cl_ddr0_arburst, + output wire cl_ddr0_arvalid, + output wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr0_arid, + input wire cl_ddr0_arready, + // Master Interface Read Data + input wire [ IBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr0_rdata, + input wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr0_rid, + input wire [ 2 -1 : 0 ] cl_ddr0_rresp, + input wire cl_ddr0_rlast, + input wire cl_ddr0_rvalid, + output wire cl_ddr0_rready, + + // CL_wrapper -> DDR1 AXI4 interface + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr1_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr1_awlen, + output wire [ 3 -1 : 0 ] cl_ddr1_awsize, + output wire [ 2 -1 : 0 ] cl_ddr1_awburst, + output wire cl_ddr1_awvalid, + input wire cl_ddr1_awready, + // Master Interface Write Data + output wire [ OBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr1_wdata, + output wire [ OBUF_WSTRB_W -1 : 0 ] cl_ddr1_wstrb, + output wire cl_ddr1_wlast, + output wire cl_ddr1_wvalid, + input wire cl_ddr1_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] cl_ddr1_bresp, + input wire cl_ddr1_bvalid, + output wire cl_ddr1_bready, + // Master Interface Read Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr1_araddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr1_arlen, + output wire [ 3 -1 : 0 ] cl_ddr1_arsize, + output wire [ 2 -1 : 0 ] cl_ddr1_arburst, + output wire cl_ddr1_arvalid, + output wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr1_arid, + input wire cl_ddr1_arready, + // Master Interface Read Data + input wire [ OBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr1_rdata, + input wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr1_rid, + input wire [ 2 -1 : 0 ] cl_ddr1_rresp, + input wire cl_ddr1_rlast, + input wire cl_ddr1_rvalid, + output wire cl_ddr1_rready, + + // CL_wrapper -> DDR2 AXI4 interface + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr2_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr2_awlen, + output wire [ 3 -1 : 0 ] cl_ddr2_awsize, + output wire [ 2 -1 : 0 ] cl_ddr2_awburst, + output wire cl_ddr2_awvalid, + input wire cl_ddr2_awready, + // Master Interface Write Data + output wire [ WBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr2_wdata, + output wire [ WBUF_WSTRB_W -1 : 0 ] cl_ddr2_wstrb, + output wire cl_ddr2_wlast, + output wire cl_ddr2_wvalid, + input wire cl_ddr2_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] cl_ddr2_bresp, + input wire cl_ddr2_bvalid, + output wire cl_ddr2_bready, + // Master Interface Read Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr2_araddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr2_arlen, + output wire [ 3 -1 : 0 ] cl_ddr2_arsize, + output wire [ 2 -1 : 0 ] cl_ddr2_arburst, + output wire cl_ddr2_arvalid, + output wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr2_arid, + input wire cl_ddr2_arready, + // Master Interface Read Data + input wire [ WBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr2_rdata, + input wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr2_rid, + input wire [ 2 -1 : 0 ] cl_ddr2_rresp, + input wire cl_ddr2_rlast, + input wire cl_ddr2_rvalid, + output wire cl_ddr2_rready, + + // CL_wrapper -> DDR3 AXI4 interface + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr3_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr3_awlen, + output wire [ 3 -1 : 0 ] cl_ddr3_awsize, + output wire [ 2 -1 : 0 ] cl_ddr3_awburst, + output wire cl_ddr3_awvalid, + input wire cl_ddr3_awready, + // Master Interface Write Data + output wire [ BBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr3_wdata, + output wire [ BBUF_WSTRB_W -1 : 0 ] cl_ddr3_wstrb, + output wire cl_ddr3_wlast, + output wire cl_ddr3_wvalid, + input wire cl_ddr3_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] cl_ddr3_bresp, + input wire cl_ddr3_bvalid, + output wire cl_ddr3_bready, + // Master Interface Read Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr3_araddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr3_arlen, + output wire [ 3 -1 : 0 ] cl_ddr3_arsize, + output wire [ 2 -1 : 0 ] cl_ddr3_arburst, + output wire cl_ddr3_arvalid, + output wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr3_arid, + input wire cl_ddr3_arready, + // Master Interface Read Data + input wire [ BBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr3_rdata, + input wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr3_rid, + input wire [ 2 -1 : 0 ] cl_ddr3_rresp, + input wire cl_ddr3_rlast, + input wire cl_ddr3_rvalid, + output wire cl_ddr3_rready, + + + // CL_wrapper -> DDR3 AXI4 interface + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr4_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr4_awlen, + output wire [ 3 -1 : 0 ] cl_ddr4_awsize, + output wire [ 2 -1 : 0 ] cl_ddr4_awburst, + output wire cl_ddr4_awvalid, + input wire cl_ddr4_awready, + // Master Interface Write Data + output wire [ PU_AXI_DATA_WIDTH -1 : 0 ] cl_ddr4_wdata, + output wire [ PU_WSTRB_W -1 : 0 ] cl_ddr4_wstrb, + output wire cl_ddr4_wlast, + output wire cl_ddr4_wvalid, + input wire cl_ddr4_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] cl_ddr4_bresp, + input wire cl_ddr4_bvalid, + output wire cl_ddr4_bready, + // Master Interface Read Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr4_araddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr4_arlen, + output wire [ 3 -1 : 0 ] cl_ddr4_arsize, + output wire [ 2 -1 : 0 ] cl_ddr4_arburst, + output wire cl_ddr4_arvalid, + output wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr4_arid, + input wire cl_ddr4_arready, + // Master Interface Read Data + input wire [ PU_AXI_DATA_WIDTH -1 : 0 ] cl_ddr4_rdata, + input wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr4_rid, + input wire [ 2 -1 : 0 ] cl_ddr4_rresp, + input wire cl_ddr4_rlast, + input wire cl_ddr4_rvalid, + output wire cl_ddr4_rready + +); + +//============================================================= +// Wires/Regs +//============================================================= +//============================================================= + +//============================================================= +// Comb Logic +//============================================================= +//============================================================= + +//============================================================= +// DnnWeaver2 Wrapper +//============================================================= + dnnweaver2_controller #( + .ARRAY_N ( ARRAY_N ), + .ARRAY_M ( ARRAY_M ), + .DATA_WIDTH ( DATA_WIDTH ), + .BIAS_WIDTH ( BIAS_WIDTH ), + .ACC_WIDTH ( ACC_WIDTH ), + + .IBUF_CAPACITY_BITS ( IBUF_CAPACITY_BITS ), + .WBUF_CAPACITY_BITS ( WBUF_CAPACITY_BITS ), + .OBUF_CAPACITY_BITS ( OBUF_CAPACITY_BITS ), + .BBUF_CAPACITY_BITS ( BBUF_CAPACITY_BITS ), + + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_BURST_WIDTH ( AXI_BURST_WIDTH ), + .IBUF_AXI_DATA_WIDTH ( IBUF_AXI_DATA_WIDTH ), + .OBUF_AXI_DATA_WIDTH ( OBUF_AXI_DATA_WIDTH ), + .PU_AXI_DATA_WIDTH ( PU_AXI_DATA_WIDTH ), + .WBUF_AXI_DATA_WIDTH ( WBUF_AXI_DATA_WIDTH ), + .BBUF_AXI_DATA_WIDTH ( BBUF_AXI_DATA_WIDTH ), + .INST_ADDR_WIDTH ( INST_ADDR_WIDTH ), + .INST_DATA_WIDTH ( INST_DATA_WIDTH ), + .CTRL_ADDR_WIDTH ( CTRL_ADDR_WIDTH ), + .CTRL_DATA_WIDTH ( CTRL_DATA_WIDTH ) + ) u_bf_wrap ( + .clk ( clk ), + .reset ( reset ), + + .pci_cl_data_awaddr ( pci_cl_data_awaddr ), + .pci_cl_data_awlen ( pci_cl_data_awlen ), + .pci_cl_data_awsize ( pci_cl_data_awsize ), + .pci_cl_data_awburst ( pci_cl_data_awburst ), + .pci_cl_data_awvalid ( pci_cl_data_awvalid ), + .pci_cl_data_awready ( pci_cl_data_awready ), + .pci_cl_data_wdata ( pci_cl_data_wdata ), + .pci_cl_data_wstrb ( pci_cl_data_wstrb ), + .pci_cl_data_wlast ( pci_cl_data_wlast ), + .pci_cl_data_wvalid ( pci_cl_data_wvalid ), + .pci_cl_data_wready ( pci_cl_data_wready ), + .pci_cl_data_bresp ( pci_cl_data_bresp ), + .pci_cl_data_bvalid ( pci_cl_data_bvalid ), + .pci_cl_data_bready ( pci_cl_data_bready ), + .pci_cl_data_araddr ( pci_cl_data_araddr ), + .pci_cl_data_arlen ( pci_cl_data_arlen ), + .pci_cl_data_arsize ( pci_cl_data_arsize ), + .pci_cl_data_arburst ( pci_cl_data_arburst ), + .pci_cl_data_arvalid ( pci_cl_data_arvalid ), + .pci_cl_data_arready ( pci_cl_data_arready ), + .pci_cl_data_rdata ( pci_cl_data_rdata ), + .pci_cl_data_rresp ( pci_cl_data_rresp ), + .pci_cl_data_rlast ( pci_cl_data_rlast ), + .pci_cl_data_rvalid ( pci_cl_data_rvalid ), + .pci_cl_data_rready ( pci_cl_data_rready ), + + .pci_cl_ctrl_awvalid ( pci_cl_ctrl_awvalid ), + .pci_cl_ctrl_awaddr ( pci_cl_ctrl_awaddr ), + .pci_cl_ctrl_awready ( pci_cl_ctrl_awready ), + .pci_cl_ctrl_wvalid ( pci_cl_ctrl_wvalid ), + .pci_cl_ctrl_wdata ( pci_cl_ctrl_wdata ), + .pci_cl_ctrl_wstrb ( pci_cl_ctrl_wstrb ), + .pci_cl_ctrl_wready ( pci_cl_ctrl_wready ), + .pci_cl_ctrl_bvalid ( pci_cl_ctrl_bvalid ), + .pci_cl_ctrl_bresp ( pci_cl_ctrl_bresp ), + .pci_cl_ctrl_bready ( pci_cl_ctrl_bready ), + .pci_cl_ctrl_arvalid ( pci_cl_ctrl_arvalid ), + .pci_cl_ctrl_araddr ( pci_cl_ctrl_araddr ), + .pci_cl_ctrl_arready ( pci_cl_ctrl_arready ), + .pci_cl_ctrl_rvalid ( pci_cl_ctrl_rvalid ), + .pci_cl_ctrl_rdata ( pci_cl_ctrl_rdata ), + .pci_cl_ctrl_rresp ( pci_cl_ctrl_rresp ), + .pci_cl_ctrl_rready ( pci_cl_ctrl_rready ), + + .cl_ddr0_awaddr ( cl_ddr0_awaddr ), + .cl_ddr0_awlen ( cl_ddr0_awlen ), + .cl_ddr0_awsize ( cl_ddr0_awsize ), + .cl_ddr0_awburst ( cl_ddr0_awburst ), + .cl_ddr0_awvalid ( cl_ddr0_awvalid ), + .cl_ddr0_awready ( cl_ddr0_awready ), + .cl_ddr0_wdata ( cl_ddr0_wdata ), + .cl_ddr0_wstrb ( cl_ddr0_wstrb ), + .cl_ddr0_wlast ( cl_ddr0_wlast ), + .cl_ddr0_wvalid ( cl_ddr0_wvalid ), + .cl_ddr0_wready ( cl_ddr0_wready ), + .cl_ddr0_bresp ( cl_ddr0_bresp ), + .cl_ddr0_bvalid ( cl_ddr0_bvalid ), + .cl_ddr0_bready ( cl_ddr0_bready ), + .cl_ddr0_araddr ( cl_ddr0_araddr ), + .cl_ddr0_arlen ( cl_ddr0_arlen ), + .cl_ddr0_arsize ( cl_ddr0_arsize ), + .cl_ddr0_arburst ( cl_ddr0_arburst ), + .cl_ddr0_arvalid ( cl_ddr0_arvalid ), + .cl_ddr0_arid ( cl_ddr0_arid ), + .cl_ddr0_arready ( cl_ddr0_arready ), + .cl_ddr0_rdata ( cl_ddr0_rdata ), + .cl_ddr0_rid ( cl_ddr0_rid ), + .cl_ddr0_rresp ( cl_ddr0_rresp ), + .cl_ddr0_rlast ( cl_ddr0_rlast ), + .cl_ddr0_rvalid ( cl_ddr0_rvalid ), + .cl_ddr0_rready ( cl_ddr0_rready ), + + .cl_ddr1_awaddr ( cl_ddr1_awaddr ), + .cl_ddr1_awlen ( cl_ddr1_awlen ), + .cl_ddr1_awsize ( cl_ddr1_awsize ), + .cl_ddr1_awburst ( cl_ddr1_awburst ), + .cl_ddr1_awvalid ( cl_ddr1_awvalid ), + .cl_ddr1_awready ( cl_ddr1_awready ), + .cl_ddr1_wdata ( cl_ddr1_wdata ), + .cl_ddr1_wstrb ( cl_ddr1_wstrb ), + .cl_ddr1_wlast ( cl_ddr1_wlast ), + .cl_ddr1_wvalid ( cl_ddr1_wvalid ), + .cl_ddr1_wready ( cl_ddr1_wready ), + .cl_ddr1_bresp ( cl_ddr1_bresp ), + .cl_ddr1_bvalid ( cl_ddr1_bvalid ), + .cl_ddr1_bready ( cl_ddr1_bready ), + .cl_ddr1_araddr ( cl_ddr1_araddr ), + .cl_ddr1_arlen ( cl_ddr1_arlen ), + .cl_ddr1_arsize ( cl_ddr1_arsize ), + .cl_ddr1_arburst ( cl_ddr1_arburst ), + .cl_ddr1_arvalid ( cl_ddr1_arvalid ), + .cl_ddr1_arid ( cl_ddr1_arid ), + .cl_ddr1_arready ( cl_ddr1_arready ), + .cl_ddr1_rdata ( cl_ddr1_rdata ), + .cl_ddr1_rid ( cl_ddr1_rid ), + .cl_ddr1_rresp ( cl_ddr1_rresp ), + .cl_ddr1_rlast ( cl_ddr1_rlast ), + .cl_ddr1_rvalid ( cl_ddr1_rvalid ), + .cl_ddr1_rready ( cl_ddr1_rready ), + + .cl_ddr2_awaddr ( cl_ddr2_awaddr ), + .cl_ddr2_awlen ( cl_ddr2_awlen ), + .cl_ddr2_awsize ( cl_ddr2_awsize ), + .cl_ddr2_awburst ( cl_ddr2_awburst ), + .cl_ddr2_awvalid ( cl_ddr2_awvalid ), + .cl_ddr2_awready ( cl_ddr2_awready ), + .cl_ddr2_wdata ( cl_ddr2_wdata ), + .cl_ddr2_wstrb ( cl_ddr2_wstrb ), + .cl_ddr2_wlast ( cl_ddr2_wlast ), + .cl_ddr2_wvalid ( cl_ddr2_wvalid ), + .cl_ddr2_wready ( cl_ddr2_wready ), + .cl_ddr2_bresp ( cl_ddr2_bresp ), + .cl_ddr2_bvalid ( cl_ddr2_bvalid ), + .cl_ddr2_bready ( cl_ddr2_bready ), + .cl_ddr2_araddr ( cl_ddr2_araddr ), + .cl_ddr2_arlen ( cl_ddr2_arlen ), + .cl_ddr2_arsize ( cl_ddr2_arsize ), + .cl_ddr2_arburst ( cl_ddr2_arburst ), + .cl_ddr2_arvalid ( cl_ddr2_arvalid ), + .cl_ddr2_arid ( cl_ddr2_arid ), + .cl_ddr2_arready ( cl_ddr2_arready ), + .cl_ddr2_rdata ( cl_ddr2_rdata ), + .cl_ddr2_rid ( cl_ddr2_rid ), + .cl_ddr2_rresp ( cl_ddr2_rresp ), + .cl_ddr2_rlast ( cl_ddr2_rlast ), + .cl_ddr2_rvalid ( cl_ddr2_rvalid ), + .cl_ddr2_rready ( cl_ddr2_rready ), + + .cl_ddr3_awaddr ( cl_ddr3_awaddr ), + .cl_ddr3_awlen ( cl_ddr3_awlen ), + .cl_ddr3_awsize ( cl_ddr3_awsize ), + .cl_ddr3_awburst ( cl_ddr3_awburst ), + .cl_ddr3_awvalid ( cl_ddr3_awvalid ), + .cl_ddr3_awready ( cl_ddr3_awready ), + .cl_ddr3_wdata ( cl_ddr3_wdata ), + .cl_ddr3_wstrb ( cl_ddr3_wstrb ), + .cl_ddr3_wlast ( cl_ddr3_wlast ), + .cl_ddr3_wvalid ( cl_ddr3_wvalid ), + .cl_ddr3_wready ( cl_ddr3_wready ), + .cl_ddr3_bresp ( cl_ddr3_bresp ), + .cl_ddr3_bvalid ( cl_ddr3_bvalid ), + .cl_ddr3_bready ( cl_ddr3_bready ), + .cl_ddr3_araddr ( cl_ddr3_araddr ), + .cl_ddr3_arlen ( cl_ddr3_arlen ), + .cl_ddr3_arsize ( cl_ddr3_arsize ), + .cl_ddr3_arburst ( cl_ddr3_arburst ), + .cl_ddr3_arvalid ( cl_ddr3_arvalid ), + .cl_ddr3_arid ( cl_ddr3_arid ), + .cl_ddr3_arready ( cl_ddr3_arready ), + .cl_ddr3_rdata ( cl_ddr3_rdata ), + .cl_ddr3_rid ( cl_ddr3_rid ), + .cl_ddr3_rresp ( cl_ddr3_rresp ), + .cl_ddr3_rlast ( cl_ddr3_rlast ), + .cl_ddr3_rvalid ( cl_ddr3_rvalid ), + .cl_ddr3_rready ( cl_ddr3_rready ), + + .cl_ddr4_awaddr ( cl_ddr4_awaddr ), + .cl_ddr4_awlen ( cl_ddr4_awlen ), + .cl_ddr4_awsize ( cl_ddr4_awsize ), + .cl_ddr4_awburst ( cl_ddr4_awburst ), + .cl_ddr4_awvalid ( cl_ddr4_awvalid ), + .cl_ddr4_awready ( cl_ddr4_awready ), + .cl_ddr4_wdata ( cl_ddr4_wdata ), + .cl_ddr4_wstrb ( cl_ddr4_wstrb ), + .cl_ddr4_wlast ( cl_ddr4_wlast ), + .cl_ddr4_wvalid ( cl_ddr4_wvalid ), + .cl_ddr4_wready ( cl_ddr4_wready ), + .cl_ddr4_bresp ( cl_ddr4_bresp ), + .cl_ddr4_bvalid ( cl_ddr4_bvalid ), + .cl_ddr4_bready ( cl_ddr4_bready ), + .cl_ddr4_araddr ( cl_ddr4_araddr ), + .cl_ddr4_arlen ( cl_ddr4_arlen ), + .cl_ddr4_arsize ( cl_ddr4_arsize ), + .cl_ddr4_arburst ( cl_ddr4_arburst ), + .cl_ddr4_arvalid ( cl_ddr4_arvalid ), + .cl_ddr4_arid ( cl_ddr4_arid ), + .cl_ddr4_arready ( cl_ddr4_arready ), + .cl_ddr4_rdata ( cl_ddr4_rdata ), + .cl_ddr4_rid ( cl_ddr4_rid ), + .cl_ddr4_rresp ( cl_ddr4_rresp ), + .cl_ddr4_rlast ( cl_ddr4_rlast ), + .cl_ddr4_rvalid ( cl_ddr4_rvalid ), + .cl_ddr4_rready ( cl_ddr4_rready ) + ); +//============================================================= + +//============================================================= +// VCD +//============================================================= +`ifdef COCOTB_TOPLEVEL_cl_wrapper + initial begin + $dumpfile("cl_wrapper.vcd"); + $dumpvars(0, cl_wrapper); + end +`endif +//============================================================= + +endmodule + +// +// Wrapper for memory +// +// Hardik Sharma +// (hsharma@gatech.edu) + +`timescale 1ns/1ps +module pu_ld_obuf_wrapper #( + // Internal Parameters + parameter integer MEM_ID = 0, + parameter integer STORE_ENABLED = MEM_ID == 1 ? 1 : 0, + parameter integer MEM_REQ_W = 16, + parameter integer ADDR_WIDTH = 8, + parameter integer LOOP_ITER_W = 16, + parameter integer ADDR_STRIDE_W = ADDR_WIDTH, + parameter integer LOOP_ID_W = 5, + parameter integer BUF_TYPE_W = 2, + parameter integer NUM_TAGS = 4, + parameter integer TAG_W = $clog2(NUM_TAGS), + + parameter integer OBUF_AXI_DATA_WIDTH = 256, + parameter integer SIMD_INTERIM_WIDTH = 512, + parameter integer NUM_FIFO = SIMD_INTERIM_WIDTH / OBUF_AXI_DATA_WIDTH, + + // AXI + parameter integer AXI_DATA_WIDTH = 64, + parameter integer AXI_BURST_WIDTH = 8, + parameter integer WSTRB_W = AXI_DATA_WIDTH/8 +) ( + input wire clk, + input wire reset, + + input wire start, + output wire done, + input wire [ ADDR_WIDTH -1 : 0 ] base_addr, + + // Programming + input wire cfg_loop_stride_v, + input wire [ ADDR_STRIDE_W -1 : 0 ] cfg_loop_stride, + input wire [ 3 -1 : 0 ] cfg_loop_stride_type, + + input wire cfg_loop_iter_v, + input wire [ LOOP_ITER_W -1 : 0 ] cfg_loop_iter, + input wire [ 3 -1 : 0 ] cfg_loop_iter_type, + + // LD + output wire mem_req, + input wire mem_ready, + output wire [ ADDR_WIDTH -1 : 0 ] mem_addr, + + input wire obuf_ld_stream_write_ready +); + +//============================================================================== +// Localparams +//============================================================================== +//============================================================================== + +//============================================================================== +// Wires/Regs +//============================================================================== + reg [ LOOP_ID_W -1 : 0 ] mem_loop_id_counter; + + wire fifo_stall; + wire fsm_stall; + wire loop_ctrl_stall; + wire [ LOOP_ID_W -1 : 0 ] loop_ctrl_index; + wire loop_ctrl_index_valid; + wire loop_ctrl_init; + wire loop_ctrl_done; + wire loop_ctrl_enter; + wire loop_ctrl_exit; + wire loop_ctrl_next_addr; + + wire [ ADDR_WIDTH -1 : 0 ] ld_addr; + reg [ ADDR_WIDTH -1 : 0 ] ld_addr_d; + reg [ ADDR_WIDTH -1 : 0 ] ld_addr_q; + wire ld_addr_valid; + + wire obuf_ld_loop_iter_v; +//============================================================================== + +//============================================================================== +// Assigns +//============================================================================== + reg mem_access_state_d; + reg mem_access_state_q; + reg done_state_d; + reg done_state_q; + assign fifo_stall = ~mem_ready || ~obuf_ld_stream_write_ready; + assign loop_ctrl_stall = fifo_stall || fsm_stall; + assign mem_req = (~fifo_stall) && (ld_addr_valid || fsm_stall); + assign loop_ctrl_next_addr = loop_ctrl_index_valid && ~loop_ctrl_stall; + assign done = mem_access_state_q == 0 && done_state_q == 1; + // assign done = loop_ctrl_done; +//============================================================================== + +//============================================================================== +// OBUF LD Address Generation +//============================================================================== + + // Need done state for the case when we need to stall after the loop + // controller has finished + + localparam FIFO_ID_WIDTH = $clog2(NUM_FIFO); + reg [ FIFO_ID_WIDTH -1 : 0 ] fifo_id_d; + reg [ FIFO_ID_WIDTH -1 : 0 ] fifo_id_q; + + always @(posedge clk) + begin + if (reset) begin + mem_access_state_q <= 1'b0; + fifo_id_q <= 0; + ld_addr_q <= 0; + end else begin + mem_access_state_q <= mem_access_state_d; + fifo_id_q <= fifo_id_d; + ld_addr_q <= ld_addr_d; + end + end + + assign fsm_stall = mem_access_state_q == 1; + +generate +if (NUM_FIFO == 1) begin + assign mem_addr = ld_addr; +end else begin + assign mem_addr = mem_access_state_q ? {ld_addr_q, fifo_id_q} : {ld_addr, fifo_id_q}; +end +endgenerate + + always @(*) + begin: MEM_ACCESS_STATE + mem_access_state_d = mem_access_state_q; + fifo_id_d = fifo_id_q; + ld_addr_d = ld_addr_q; + case (mem_access_state_q) + 0: begin + if (mem_req && NUM_FIFO > 1) begin + mem_access_state_d = 1; + fifo_id_d = 1; + ld_addr_d = ld_addr; + end + end + 1: begin + if (mem_req) begin + if (fifo_id_q == NUM_FIFO-1) begin + fifo_id_d = 0; + mem_access_state_d = 0; + end else begin + fifo_id_d = fifo_id_q + 1; + end + end + end + endcase + end + + always @(posedge clk) + begin + if (reset) + done_state_q <= 1'b0; + else + done_state_q <= done_state_d; + end + + always @(*) + begin + done_state_d = done_state_q; + case (done_state_q) + 1'b0: begin + if (loop_ctrl_done) + done_state_d = 1'b1; + end + 1'b1: begin + if (done) + done_state_d = 1'b0; + end + endcase + end +//============================================================================== + +//============================================================================== +// Address generators +//============================================================================== + wire obuf_ld_stride_v; + assign obuf_ld_stride_v = cfg_loop_stride_v && cfg_loop_stride_type == 0; + mem_walker_stride #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) mws_ld ( + .clk ( clk ), //input + .reset ( reset ), //input + .base_addr ( base_addr ), //input + .loop_ctrl_done ( loop_ctrl_done ), //input + .loop_index ( loop_ctrl_index ), //input + .loop_index_valid ( loop_ctrl_next_addr ), //input + .loop_init ( loop_ctrl_init ), //input + .loop_enter ( loop_ctrl_enter ), //input + .loop_exit ( loop_ctrl_exit ), //input + .cfg_addr_stride_v ( obuf_ld_stride_v ), //input + .cfg_addr_stride ( cfg_loop_stride ), //input + .addr_out ( ld_addr ), //output + .addr_out_valid ( ld_addr_valid ) //output + ); +//============================================================================== + +//============================================================================== +// Loop controller +//============================================================================== + always@(posedge clk) + begin + if (reset) + mem_loop_id_counter <= 'b0; + else begin + if (obuf_ld_loop_iter_v) + mem_loop_id_counter <= mem_loop_id_counter + 1'b1; + else if (start) + mem_loop_id_counter <= 'b0; + end + end + + assign obuf_ld_loop_iter_v = cfg_loop_iter_v && cfg_loop_iter_type == 0; + + controller_fsm #( + .LOOP_ID_W ( LOOP_ID_W ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .IMEM_ADDR_W ( LOOP_ID_W ) + ) loop_ctrl ( + .clk ( clk ), //input + .reset ( reset ), //input + .stall ( loop_ctrl_stall ), //input + .cfg_loop_iter_v ( obuf_ld_loop_iter_v ), //input + .cfg_loop_iter ( cfg_loop_iter ), //input + .cfg_loop_iter_loop_id ( mem_loop_id_counter ), //input + .start ( start ), //input + .done ( loop_ctrl_done ), //output + .loop_init ( loop_ctrl_init ), //output + .loop_enter ( loop_ctrl_enter ), //output + .loop_last_iter ( ), //output + .loop_exit ( loop_ctrl_exit ), //output + .loop_index ( loop_ctrl_index ), //output + .loop_index_valid ( loop_ctrl_index_valid ) //output + ); +//============================================================================== + +//============================================================================== +// VCD +//============================================================================== +`ifdef COCOTB_TOPLEVEL_pu_ld_obuf_wrapper +initial begin + $dumpfile("pu_ld_obuf_wrapper.vcd"); + $dumpvars(0, pu_ld_obuf_wrapper); +end +`endif +//============================================================================== +endmodule +`timescale 1ns / 1ps +module gen_pu_ctrl #( + parameter integer ADDR_WIDTH = 42, + parameter integer BUF_TYPE_W = 2, + parameter integer INST_WIDTH = 32, + parameter integer DATA_WIDTH = 32, + parameter integer IMEM_ADDR_WIDTH = 5, // 1K = 1 BRAM + parameter integer IMM_WIDTH = 16, + parameter integer ADDR_STRIDE_W = 32, + parameter integer FN_WIDTH = 3, + parameter integer RF_ADDR_WIDTH = 4, + parameter integer OP_CODE_W = 4, + parameter integer OP_SPEC_W = 7, + parameter integer LOOP_ID_W = 5, + parameter integer LOOP_ITER_W = IMM_WIDTH +) ( + input wire clk, + input wire reset, + + // DEBUG + output wire [ 3 -1 : 0 ] pu_ctrl_state, + + // Handshake - program + input wire pu_block_start, + input wire pu_compute_start, + output wire pu_compute_ready, + + // Handshake - compute + output wire done, + + // Buffer instruction write (to PE) interface + // TODO: connect inst_wr_req + input wire inst_wr_req, + input wire [ INST_WIDTH -1 : 0 ] inst_wr_data, + output wire inst_wr_ready, + + // data streamer - loop iterations + output wire cfg_loop_iter_v, + output wire [ IMM_WIDTH -1 : 0 ] cfg_loop_iter, + output wire [ 3 -1 : 0 ] cfg_loop_iter_type, + + // data streamer - address generation + output wire cfg_loop_stride_v, + output wire [ ADDR_STRIDE_W -1 : 0 ] cfg_loop_stride, + output wire [ 3 -1 : 0 ] cfg_loop_stride_type, + + // ddr ld streamer + output wire cfg_mem_req_v, + output wire [ 2 -1 : 0 ] cfg_mem_req_type, + + output wire [ ADDR_WIDTH -1 : 0 ] tag_ld0_base_addr, + output wire [ ADDR_WIDTH -1 : 0 ] tag_ld1_base_addr, + output wire [ ADDR_WIDTH -1 : 0 ] tag_st_base_addr, + + // data streamer - address generation + output wire alu_fn_valid, + output wire [ FN_WIDTH -1 : 0 ] alu_fn, + output wire [ RF_ADDR_WIDTH -1 : 0 ] alu_in0_addr, + output wire alu_in1_src, + output wire [ RF_ADDR_WIDTH -1 : 0 ] alu_in1_addr, + output wire [ RF_ADDR_WIDTH -1 : 0 ] alu_out_addr, + output wire [ IMM_WIDTH -1 : 0 ] alu_imm, + + // From controller + output wire obuf_ld_stream_read_req, + input wire obuf_ld_stream_read_ready, + output wire ddr_ld0_stream_read_req, + input wire ddr_ld0_stream_read_ready, + output wire ddr_ld1_stream_read_req, + input wire ddr_ld1_stream_read_ready, + output wire ddr_st_stream_write_req, + input wire ddr_st_stream_write_ready, + input wire ddr_st_done +); + +//============================================================================== +// Localparams +//============================================================================== + localparam BASE_ADDR_PART_W = IMM_WIDTH + LOOP_ID_W; + localparam integer PU_CTRL_IDLE = 0; + localparam integer PU_CTRL_DECODE = 1; + localparam integer PU_CTRL_COMPUTE_START = 2; + localparam integer PU_BASE_ADDR_CALC = 3; + localparam integer PU_CTRL_COMPUTE_WAIT = 4; + localparam integer PU_CTRL_COMPUTE = 5; + localparam integer PU_CTRL_COMPUTE_DONE = 6; + localparam integer PU_CTRL_DONE = 7; + + localparam integer OP_SETUP = 0; + localparam integer OP_LDMEM = 1; + localparam integer OP_STMEM = 2; + localparam integer OP_RDBUF = 3; + localparam integer OP_WRBUF = 4; + localparam integer OP_GENADDR_HI = 5; + localparam integer OP_GENADDR_LO = 6; + localparam integer OP_LOOP = 7; + localparam integer OP_BLOCK_REPEAT = 8; + localparam integer OP_BASE_ADDR = 9; + localparam integer OP_PU_BLOCK = 10; + localparam integer OP_COMPUTE_R = 11; + localparam integer OP_COMPUTE_I = 12; + + localparam LD_OBUF = 0; + localparam LD0_DDR = 1; + localparam LD1_DDR = 2; +//============================================================================== + +//============================================================================== +// Wires & Regs +//============================================================================== + reg [ IMM_WIDTH -1 : 0 ] loop_stride_hi; + + wire [ ADDR_WIDTH -1 : 0 ] st_addr; + wire st_addr_valid; + + wire [ ADDR_WIDTH -1 : 0 ] ld0_addr; + wire ld0_addr_valid; + wire [ ADDR_WIDTH -1 : 0 ] ld1_addr; + wire ld1_addr_valid; + + reg [ 1 -1 : 0 ] stmem_state_d; + reg [ 1 -1 : 0 ] stmem_state_q; + + reg loop_status_d; + reg loop_status_q; + + reg [ ADDR_WIDTH -1 : 0 ] tag_ld0_base_addr_d; + reg [ ADDR_WIDTH -1 : 0 ] tag_ld0_base_addr_q; + reg [ ADDR_WIDTH -1 : 0 ] tag_ld1_base_addr_d; + reg [ ADDR_WIDTH -1 : 0 ] tag_ld1_base_addr_q; + reg [ ADDR_WIDTH -1 : 0 ] tag_st_base_addr_d; + reg [ ADDR_WIDTH -1 : 0 ] tag_st_base_addr_q; + + wire loop_ctrl_loop_iter_v; + wire [ IMM_WIDTH -1 : 0 ] loop_ctrl_loop_iter; + wire loop_ctrl_loop_done; + wire loop_ctrl_loop_init; + wire loop_ctrl_loop_enter; + wire loop_ctrl_loop_exit; + wire [ LOOP_ID_W -1 : 0 ] loop_ctrl_loop_index; + wire loop_ctrl_loop_index_valid; + wire loop_ctrl_loop_index_step; + + wire loop_ctrl_start; + wire loop_ctrl_stall; + reg [ LOOP_ID_W -1 : 0 ] loop_ctrl_loop_id_counter; + wire st_stride_v; + wire [ ADDR_STRIDE_W -1 : 0 ] st_stride; + wire ld0_stride_v; + wire [ ADDR_STRIDE_W -1 : 0 ] ld0_stride; + wire ld1_stride_v; + wire [ ADDR_STRIDE_W -1 : 0 ] ld1_stride; + + wire [ ADDR_WIDTH -1 : 0 ] ld0_tensor_base_addr; + wire [ ADDR_WIDTH -1 : 0 ] ld1_tensor_base_addr; + wire [ ADDR_WIDTH -1 : 0 ] st_tensor_base_addr; + wire cfg_loop_stride_base; + + reg [ 3 -1 : 0 ] pu_ctrl_state_d; + reg [ 3 -1 : 0 ] pu_ctrl_state_q; + wire instruction_valid; + wire pu_block_end; + + wire [ OP_CODE_W -1 : 0 ] op_code; + wire [ OP_SPEC_W -1 : 0 ] op_spec; + wire [ LOOP_ID_W -1 : 0 ] loop_id; + wire [ IMM_WIDTH -1 : 0 ] imm; + + wire stall; + wire _alu_fn_valid; + wire _obuf_ld_stream_read_req; + wire _ddr_ld0_stream_read_req; + wire _ddr_ld1_stream_read_req; + wire _ddr_st_stream_write_req; + wire _ddr_st_stream_write_req_dly1; + wire _ddr_st_stream_write_req_dly2; + wire _ddr_st_stream_write_req_dly3; + + wire [ IMM_WIDTH -1 : 0 ] block_inst_repeat; + reg [ IMM_WIDTH -1 : 0 ] block_inst_repeat_d; + reg [ IMM_WIDTH -1 : 0 ] block_inst_repeat_q; + reg [ IMM_WIDTH -1 : 0 ] repeat_counter_d; + reg [ IMM_WIDTH -1 : 0 ] repeat_counter_q; + + //reg [ INST_WIDTH -1 : 0 ] mem [ 0 : 1< DDR0 AXI4 interface + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] pu_ddr_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] pu_ddr_awlen, + output wire [ 3 -1 : 0 ] pu_ddr_awsize, + output wire [ 2 -1 : 0 ] pu_ddr_awburst, + output wire pu_ddr_awvalid, + input wire pu_ddr_awready, + // Master Interface Write Data + output wire [ AXI_DATA_WIDTH -1 : 0 ] pu_ddr_wdata, + output wire [ AXI_WSTRB_WIDTH -1 : 0 ] pu_ddr_wstrb, + output wire pu_ddr_wlast, + output wire pu_ddr_wvalid, + input wire pu_ddr_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] pu_ddr_bresp, + input wire pu_ddr_bvalid, + output wire pu_ddr_bready, + // Master Interface Read Address + output wire [ AXI_ID_WIDTH -1 : 0 ] pu_ddr_arid, + output wire [ AXI_ADDR_WIDTH -1 : 0 ] pu_ddr_araddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] pu_ddr_arlen, + output wire [ 3 -1 : 0 ] pu_ddr_arsize, + output wire [ 2 -1 : 0 ] pu_ddr_arburst, + output wire pu_ddr_arvalid, + input wire pu_ddr_arready, + // Master Interface Read Data + input wire [ AXI_ID_WIDTH -1 : 0 ] pu_ddr_rid, + input wire [ AXI_DATA_WIDTH -1 : 0 ] pu_ddr_rdata, + input wire [ 2 -1 : 0 ] pu_ddr_rresp, + input wire pu_ddr_rlast, + input wire pu_ddr_rvalid, + output wire pu_ddr_rready, + + output wire [ INST_WIDTH -1 : 0 ] obuf_ld_stream_read_count, + output wire [ INST_WIDTH -1 : 0 ] obuf_ld_stream_write_count, + output wire [ INST_WIDTH -1 : 0 ] ddr_st_stream_read_count, + output wire [ INST_WIDTH -1 : 0 ] ddr_st_stream_write_count, + output wire [ INST_WIDTH -1 : 0 ] ld0_stream_counts, + output wire [ INST_WIDTH -1 : 0 ] ld1_stream_counts, + output wire [ INST_WIDTH -1 : 0 ] axi_wr_fifo_counts + + ); + +//============================================================================== +// Wires and Regs +//============================================================================== + wire obuf_ld_stream_read_req; + wire obuf_ld_stream_read_ready; + wire ddr_ld0_stream_read_req; + wire ddr_ld0_stream_read_ready; + wire ddr_ld1_stream_read_req; + wire ddr_ld1_stream_read_ready; + wire ddr_st_stream_write_req; + wire ddr_st_stream_write_ready; + + wire ld_obuf_done; + + wire ddr_st_done; + + wire ld_data_ready; + wire ld_data_valid; + + wire cfg_loop_iter_v; + wire [ IMM_WIDTH -1 : 0 ] cfg_loop_iter; + wire [ 3 -1 : 0 ] cfg_loop_iter_type; + + wire cfg_loop_stride_v; + wire [ ADDR_STRIDE_W -1 : 0 ] cfg_loop_stride; + wire [ 3 -1 : 0 ] cfg_loop_stride_type; + + wire cfg_mem_req_v; + wire [ 2 -1 : 0 ] cfg_mem_req_type; + + wire alu_fn_valid; + wire [ 3 -1 : 0 ] alu_fn; + wire [ 4 -1 : 0 ] alu_in0_addr; + wire alu_in1_src; + wire [ 4 -1 : 0 ] alu_in1_addr; + wire [ IMM_WIDTH -1 : 0 ] alu_imm; + wire [ 4 -1 : 0 ] alu_out_addr; + + wire obuf_ld_stream_write_ready; + wire ddr_ld0_stream_write_req; + wire ddr_ld0_stream_write_ready; + wire [ AXI_DATA_WIDTH -1 : 0 ] ddr_ld0_stream_write_data; + wire ddr_ld1_stream_write_req; + wire ddr_ld1_stream_write_ready; + wire [ AXI_DATA_WIDTH -1 : 0 ] ddr_ld1_stream_write_data; + wire ddr_st_stream_read_req; + wire [ AXI_DATA_WIDTH -1 : 0 ] ddr_st_stream_read_data; + wire ddr_st_stream_read_ready; + + wire ld_obuf_start; + wire [ OBUF_ADDR_WIDTH -1 : 0 ] ld_obuf_base_addr; + + wire pu_ddr_start; + wire pu_ddr_done; + wire pu_ddr_data_valid; + + wire [ AXI_ADDR_WIDTH -1 : 0 ] pu_ddr_st_base_addr; + wire [ AXI_ADDR_WIDTH -1 : 0 ] pu_ddr_ld0_base_addr; + wire [ AXI_ADDR_WIDTH -1 : 0 ] pu_ddr_ld1_base_addr; + + wire pu_ld0_read_req; + wire pu_ld1_read_req; + + wire ddr_ld0_req; + wire ddr_ld0_ready; + wire [ SIMD_DATA_WIDTH -1 : 0 ] ddr_ld0_data; + wire ddr_ld1_req; + wire ddr_ld1_ready; + wire [ SIMD_DATA_WIDTH -1 : 0 ] ddr_ld1_data; + wire ddr_st_req; + wire ddr_st_ready; + wire [ SIMD_DATA_WIDTH -1 : 0 ] ddr_st_data; +//============================================================================== + +//============================================================================== +// Assigns +//============================================================================== + assign pu_write_done = ddr_st_done; +//============================================================================== + +//============================================================================== +// Gen PU controller +//============================================================================== + gen_pu_ctrl #( + .ADDR_WIDTH ( AXI_ADDR_WIDTH ) + ) + u_ctrl ( + .clk ( clk ), //input + .reset ( reset ), //input + + .pu_block_start ( pu_block_start ), //input + .pu_compute_start ( pu_compute_start ), //input + .pu_compute_ready ( pu_compute_ready ), //output + + .tag_ld0_base_addr ( pu_ddr_ld0_base_addr ), //output + .tag_ld1_base_addr ( pu_ddr_ld1_base_addr ), //output + .tag_st_base_addr ( pu_ddr_st_base_addr ), //output + + .pu_ctrl_state ( pu_ctrl_state ), //output + .done ( done ), //output + + .inst_wr_req ( inst_wr_req ), //input + .inst_wr_data ( inst_wr_data ), //input + .inst_wr_ready ( inst_wr_ready ), //output + + .cfg_loop_iter_v ( cfg_loop_iter_v ), //output + .cfg_loop_iter ( cfg_loop_iter ), //output + .cfg_loop_iter_type ( cfg_loop_iter_type ), //output + + .cfg_mem_req_v ( cfg_mem_req_v ), //output + .cfg_mem_req_type ( cfg_mem_req_type ), //output + + .cfg_loop_stride_v ( cfg_loop_stride_v ), //output + .cfg_loop_stride ( cfg_loop_stride ), //output + .cfg_loop_stride_type ( cfg_loop_stride_type ), //output + + .obuf_ld_stream_read_req ( obuf_ld_stream_read_req ), //output + .obuf_ld_stream_read_ready ( obuf_ld_stream_read_ready ), //input + .ddr_ld0_stream_read_req ( ddr_ld0_stream_read_req ), //output + .ddr_ld0_stream_read_ready ( ddr_ld0_stream_read_ready ), //input + .ddr_ld1_stream_read_req ( ddr_ld1_stream_read_req ), //output + .ddr_ld1_stream_read_ready ( ddr_ld1_stream_read_ready ), //input + .ddr_st_stream_write_req ( ddr_st_stream_write_req ), //output + .ddr_st_stream_write_ready ( ddr_st_stream_write_ready ), //input + .ddr_st_done ( ddr_st_done ), //input + + .alu_fn_valid ( alu_fn_valid ), //output + .alu_in0_addr ( alu_in0_addr ), //output + .alu_in1_src ( alu_in1_src ), //output + .alu_in1_addr ( alu_in1_addr ), //output + .alu_imm ( alu_imm ), //output + .alu_out_addr ( alu_out_addr ), //output + .alu_fn ( alu_fn ) //output + ); +//============================================================================== + +//============================================================================== +// LD Obuf stream +//============================================================================== + assign ld_obuf_start = pu_compute_start; + assign ld_obuf_base_addr = 0; + assign pu_compute_done = ld_obuf_done; + + wire [ OBUF_ADDR_WIDTH -1 : 0 ] ld_obuf_stride; + assign ld_obuf_stride = cfg_loop_stride; + + pu_ld_obuf_wrapper #( + .NUM_FIFO ( NUM_FIFO ), + .SIMD_INTERIM_WIDTH ( SIMD_INTERIM_WIDTH ), + .OBUF_AXI_DATA_WIDTH ( OBUF_AXI_DATA_WIDTH ), + .ADDR_WIDTH ( OBUF_ADDR_WIDTH ) + ) + u_ld_obuf_wrapper ( + .clk ( clk ), //input + .reset ( reset ), //input + .start ( ld_obuf_start ), //input + .done ( ld_obuf_done ), //output + .base_addr ( ld_obuf_base_addr ), //input + .cfg_loop_iter_v ( cfg_loop_iter_v ), //output + .cfg_loop_iter ( cfg_loop_iter ), //output + .cfg_loop_iter_type ( cfg_loop_iter_type ), //output + .cfg_loop_stride_v ( cfg_loop_stride_v ), //output + .cfg_loop_stride ( ld_obuf_stride ), //output + .cfg_loop_stride_type ( cfg_loop_stride_type ), //output + .mem_req ( ld_obuf_req ), //output + .mem_ready ( ld_obuf_ready ), //output + .mem_addr ( ld_obuf_addr ), //output + .obuf_ld_stream_write_ready ( obuf_ld_stream_write_ready ) //input + ); +//============================================================================== + +//============================================================================== +// LD/ST DDR stream +//============================================================================== + assign pu_ddr_start = pu_compute_start; + + ldst_ddr_wrapper #( + .SIMD_DATA_WIDTH ( SIMD_DATA_WIDTH ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ) + ) + u_ldst_ddr_wrapper ( + .clk ( clk ), //input + .reset ( reset ), //input + .start ( pu_ddr_start ), //input + .pu_block_start ( pu_block_start ), //input + .done ( ddr_st_done ), //output + .st_base_addr ( pu_ddr_st_base_addr ), //input + .ld0_base_addr ( pu_ddr_ld0_base_addr ), //input + .ld1_base_addr ( pu_ddr_ld1_base_addr ), //input + .cfg_loop_stride_v ( cfg_loop_stride_v ), //input + .cfg_loop_stride ( cfg_loop_stride ), //input + .cfg_loop_stride_type ( cfg_loop_stride_type ), //input + .cfg_loop_iter_v ( cfg_loop_iter_v ), //input + .cfg_loop_iter ( cfg_loop_iter ), //input + .cfg_loop_iter_type ( cfg_loop_iter_type ), //input + + .cfg_mem_req_v ( cfg_mem_req_v ), //input + .cfg_mem_req_type ( cfg_mem_req_type ), //input + + .ddr_st_stream_read_req ( ddr_st_stream_read_req ), //output + .ddr_st_stream_read_ready ( ddr_st_stream_read_ready ), //input + .ddr_st_stream_read_data ( ddr_st_stream_read_data ), //input + + .ddr_ld0_stream_write_req ( ddr_ld0_stream_write_req ), //output + .ddr_ld0_stream_write_data ( ddr_ld0_stream_write_data ), //input + .ddr_ld0_stream_write_ready ( ddr_ld0_stream_write_ready ), //input + + .ddr_ld1_stream_write_req ( ddr_ld1_stream_write_req ), //output + .ddr_ld1_stream_write_data ( ddr_ld1_stream_write_data ), //input + .ddr_ld1_stream_write_ready ( ddr_ld1_stream_write_ready ), //input + + .pu_ddr_awaddr ( pu_ddr_awaddr ), //output + .pu_ddr_awlen ( pu_ddr_awlen ), //output + .pu_ddr_awsize ( pu_ddr_awsize ), //output + .pu_ddr_awburst ( pu_ddr_awburst ), //output + .pu_ddr_awvalid ( pu_ddr_awvalid ), //output + .pu_ddr_awready ( pu_ddr_awready ), //input + .pu_ddr_wdata ( pu_ddr_wdata ), //output + .pu_ddr_wstrb ( pu_ddr_wstrb ), //output + .pu_ddr_wlast ( pu_ddr_wlast ), //output + .pu_ddr_wvalid ( pu_ddr_wvalid ), //output + .pu_ddr_wready ( pu_ddr_wready ), //input + .pu_ddr_bresp ( pu_ddr_bresp ), //input + .pu_ddr_bvalid ( pu_ddr_bvalid ), //input + .pu_ddr_bready ( pu_ddr_bready ), //output + .pu_ddr_arid ( pu_ddr_arid ), //output + .pu_ddr_araddr ( pu_ddr_araddr ), //output + .pu_ddr_arlen ( pu_ddr_arlen ), //output + .pu_ddr_arsize ( pu_ddr_arsize ), //output + .pu_ddr_arburst ( pu_ddr_arburst ), //output + .pu_ddr_arvalid ( pu_ddr_arvalid ), //output + .pu_ddr_arready ( pu_ddr_arready ), //input + .pu_ddr_rid ( pu_ddr_rid ), //input + .pu_ddr_rdata ( pu_ddr_rdata ), //input + .pu_ddr_rresp ( pu_ddr_rresp ), //input + .pu_ddr_rlast ( pu_ddr_rlast ), //input + .pu_ddr_rvalid ( pu_ddr_rvalid ), //input + .pu_ddr_rready ( pu_ddr_rready ) //output + ); +//============================================================================== + +//============================================================================== +// SIMD core - RF + ALU +//============================================================================== + // assign ddr_st_stream_write_count = {u_ldst_ddr_wrapper.u_axi_mm_master.awr_req_buf.fifo_count, u_ldst_ddr_wrapper.u_axi_mm_master.wdata_req_buf.fifo_count}; + //wire [15:0] ddr_wr_awr_req_buf = u_ldst_ddr_wrapper.u_axi_mm_master.awr_req_buf.fifo_count; + //wire [15:0] ddr_wr_wr_req_buf = u_ldst_ddr_wrapper.u_axi_mm_master.wdata_req_buf.fifo_count; + //assign axi_wr_fifo_counts = {ddr_wr_awr_req_buf, ddr_wr_wr_req_buf}; + simd_pu_core #( + .DATA_WIDTH ( DATA_WIDTH ), + .OBUF_AXI_DATA_WIDTH ( OBUF_AXI_DATA_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .ACC_DATA_WIDTH ( ACC_DATA_WIDTH ), + .SIMD_LANES ( SIMD_LANES ), + .SIMD_DATA_WIDTH ( SIMD_DATA_WIDTH ), + .SRC_ADDR_WIDTH ( SRC_ADDR_WIDTH ), + .OP_WIDTH ( OP_WIDTH ), + .FN_WIDTH ( FN_WIDTH ), + .IMM_WIDTH ( IMM_WIDTH ) + ) simd_core ( + .clk ( clk ), //input + .reset ( reset ), //input + + .obuf_ld_stream_write_req ( obuf_ld_stream_write_req ), //input + .obuf_ld_stream_write_ready ( obuf_ld_stream_write_ready ), //output + .obuf_ld_stream_write_data ( obuf_ld_stream_write_data ), //output + + // DEBUG + .obuf_ld_stream_read_count ( obuf_ld_stream_read_count ), //output + .obuf_ld_stream_write_count ( obuf_ld_stream_write_count ), //output + .ddr_st_stream_read_count ( ddr_st_stream_read_count ), //output + .ddr_st_stream_write_count ( ddr_st_stream_write_count ), //output + .ld0_stream_counts ( ld0_stream_counts ), //output + .ld1_stream_counts ( ld1_stream_counts ), //output + // DEBUG + + + .obuf_ld_stream_read_req ( obuf_ld_stream_read_req ), //input + .obuf_ld_stream_read_ready ( obuf_ld_stream_read_ready ), //output + .ddr_ld0_stream_read_req ( ddr_ld0_stream_read_req ), //input + .ddr_ld0_stream_read_ready ( ddr_ld0_stream_read_ready ), //output + .ddr_ld1_stream_read_req ( ddr_ld1_stream_read_req ), //input + .ddr_ld1_stream_read_ready ( ddr_ld1_stream_read_ready ), //output + .ddr_st_stream_write_req ( ddr_st_stream_write_req ), //input + .ddr_st_stream_write_ready ( ddr_st_stream_write_ready ), //output + + .ddr_st_stream_read_req ( ddr_st_stream_read_req ), //input + .ddr_st_stream_read_data ( ddr_st_stream_read_data ), //output + .ddr_st_stream_read_ready ( ddr_st_stream_read_ready ), //output + + .ddr_ld0_stream_write_req ( ddr_ld0_stream_write_req ), //input + .ddr_ld0_stream_write_data ( ddr_ld0_stream_write_data ), //output + .ddr_ld0_stream_write_ready ( ddr_ld0_stream_write_ready ), //output + + .ddr_ld1_stream_write_req ( ddr_ld1_stream_write_req ), //input + .ddr_ld1_stream_write_data ( ddr_ld1_stream_write_data ), //output + .ddr_ld1_stream_write_ready ( ddr_ld1_stream_write_ready ), //output + + .alu_fn_valid ( alu_fn_valid ), //input + .alu_fn ( alu_fn ), //input + .alu_imm ( alu_imm ), //input + .alu_in0_addr ( alu_in0_addr ), //input + .alu_in1_src ( alu_in1_src ), //input + .alu_in1_addr ( alu_in1_addr ), //input + .alu_out_addr ( alu_out_addr ) //input + ); +//============================================================================== + +//============================================================================== +// VCD +//============================================================================== + `ifdef COCOTB_TOPLEVEL_gen_pu + initial begin + $dumpfile("gen_pu.vcd"); + $dumpvars(0, gen_pu); + end + `endif +//============================================================================== + +endmodule +`timescale 1ns / 1ps +module simd_pu_core #( + // Instruction width for PU controller + parameter integer INST_WIDTH = 32, + // Data width + parameter integer DATA_WIDTH = 16, + parameter integer ACC_DATA_WIDTH = 32, + parameter integer SIMD_LANES = 1, + parameter integer SIMD_DATA_WIDTH = SIMD_LANES * DATA_WIDTH, + parameter integer SIMD_INTERIM_WIDTH = SIMD_LANES * ACC_DATA_WIDTH, + parameter integer OBUF_AXI_DATA_WIDTH = 256, + + parameter integer AXI_DATA_WIDTH = 64, + + parameter integer SRC_ADDR_WIDTH = 4, + parameter integer RF_ADDR_WIDTH = SRC_ADDR_WIDTH-1, + + parameter integer OP_WIDTH = 3, + parameter integer FN_WIDTH = 3, + parameter integer IMM_WIDTH = 16 +) +( + input wire clk, + input wire reset, + + input wire alu_fn_valid, + input wire [ FN_WIDTH -1 : 0 ] alu_fn, + input wire [ IMM_WIDTH -1 : 0 ] alu_imm, + + input wire [ SRC_ADDR_WIDTH -1 : 0 ] alu_in0_addr, + input wire alu_in1_src, + input wire [ SRC_ADDR_WIDTH -1 : 0 ] alu_in1_addr, + input wire [ SRC_ADDR_WIDTH -1 : 0 ] alu_out_addr, + + // From controller + input wire obuf_ld_stream_read_req, + output wire obuf_ld_stream_read_ready, + input wire ddr_ld0_stream_read_req, + output wire ddr_ld0_stream_read_ready, + input wire ddr_ld1_stream_read_req, + output wire ddr_ld1_stream_read_ready, + input wire ddr_st_stream_write_req, + output wire ddr_st_stream_write_ready, + + // From DDR + input wire ddr_st_stream_read_req, + output wire [ AXI_DATA_WIDTH -1 : 0 ] ddr_st_stream_read_data, + output wire ddr_st_stream_read_ready, + + input wire ddr_ld0_stream_write_req, + input wire [ AXI_DATA_WIDTH -1 : 0 ] ddr_ld0_stream_write_data, + output wire ddr_ld0_stream_write_ready, + + input wire ddr_ld1_stream_write_req, + input wire [ AXI_DATA_WIDTH -1 : 0 ] ddr_ld1_stream_write_data, + output wire ddr_ld1_stream_write_ready, + + // From OBUF + input wire obuf_ld_stream_write_req, + input wire [ OBUF_AXI_DATA_WIDTH -1 : 0 ] obuf_ld_stream_write_data, + output wire obuf_ld_stream_write_ready, + + output wire [ INST_WIDTH -1 : 0 ] obuf_ld_stream_read_count, + output wire [ INST_WIDTH -1 : 0 ] obuf_ld_stream_write_count, + output wire [ INST_WIDTH -1 : 0 ] ddr_st_stream_read_count, + output wire [ INST_WIDTH -1 : 0 ] ddr_st_stream_write_count, + output wire [ INST_WIDTH -1 : 0 ] ld0_stream_counts, + output wire [ INST_WIDTH -1 : 0 ] ld1_stream_counts +); + +//============================================================================== +// Localparams +//============================================================================== +//============================================================================== + +//============================================================================== +// Wires & Regs +//============================================================================== + wire [ SIMD_INTERIM_WIDTH -1 : 0 ] alu_in0_data; + wire [ SIMD_INTERIM_WIDTH -1 : 0 ] alu_in1_data; + + wire [ SIMD_INTERIM_WIDTH -1 : 0 ] obuf_ld_stream_read_data; + + wire [ SIMD_DATA_WIDTH -1 : 0 ] ddr_ld0_stream_read_data; + wire ld0_req_buf_write_ready; + wire ld0_req_buf_almost_full; + wire ld0_req_buf_almost_empty; + wire [15:0] ld0_req_buf_fifo_count; + + wire [ SIMD_DATA_WIDTH -1 : 0 ] ddr_ld1_stream_read_data; + wire ld1_req_buf_write_ready; + wire ld1_req_buf_almost_full; + wire ld1_req_buf_almost_empty; + wire [15:0] ld1_req_buf_fifo_count; + + wire st_req_buf_almost_full; + wire st_req_buf_almost_empty; + wire [15:0] st_req_buf_fifo_count; + wire [ SIMD_DATA_WIDTH -1 : 0 ] ddr_st_stream_write_data; + + wire [ FN_WIDTH -1 : 0 ] alu_fn_stage2; + wire alu_fn_valid_stage2; + wire alu_fn_valid_stage3; + wire [ IMM_WIDTH -1 : 0 ] alu_imm_stage2; + wire alu_in1_src_stage2; + wire [ SRC_ADDR_WIDTH -1 : 0 ] alu_in0_addr_stage2; + wire [ SRC_ADDR_WIDTH -1 : 0 ] alu_in1_addr_stage2; + + wire ld_req_buf_almost_full; + wire ld_req_buf_almost_empty; + wire [15:0] ld_req_buf_fifo_count; + + wire alu_in0_req; + wire alu_in1_req; + wire [ SIMD_INTERIM_WIDTH -1 : 0 ] alu_out; + reg [ SIMD_INTERIM_WIDTH -1 : 0 ] alu_out_fwd; + + // chaining consecutive ops + wire chain_rs0; + wire chain_rs1; + wire chain_rs0_stage2; + wire chain_rs1_stage2; + + // forwarding between ops + wire fwd_rs0; + wire fwd_rs1; + wire fwd_rs0_stage2; + wire fwd_rs1_stage2; + + wire [ SRC_ADDR_WIDTH -1 : 0 ] alu_out_addr_stage2; + wire [ SRC_ADDR_WIDTH -1 : 0 ] alu_out_addr_stage3; + + genvar i; +//============================================================================== + +//============================================================================== +// Chaining/Forwarding logic +//============================================================================== + assign chain_rs0 = alu_fn_valid && alu_fn_valid_stage2 && (alu_in0_addr[2:0] == alu_out_addr_stage2[2:0]); + assign chain_rs1 = alu_fn_valid && alu_fn_valid_stage2 && (alu_in1_addr[2:0] == alu_out_addr_stage2[2:0]); + + assign fwd_rs0 = (alu_fn_valid && alu_fn_valid_stage3 && (alu_in0_addr == alu_out_addr_stage3)); + assign fwd_rs1 = (alu_fn_valid && alu_fn_valid_stage3 && (alu_in1_addr == alu_out_addr_stage3)); +//============================================================================== + +//============================================================================== +// Registers +//============================================================================== + register_sync_with_enable #(1) stage2_chain_rs0 + (clk, reset, 1'b1, chain_rs0, chain_rs0_stage2); + + register_sync_with_enable #(1) stage2_chain_rs1 + (clk, reset, 1'b1, chain_rs1, chain_rs1_stage2); + + register_sync_with_enable #(1) stage2_fwd_rs0 + (clk, reset, 1'b1, fwd_rs0, fwd_rs0_stage2); + + register_sync_with_enable #(1) stage2_fwd_rs1 + (clk, reset, 1'b1, fwd_rs1, fwd_rs1_stage2); + + register_sync_with_enable #(SRC_ADDR_WIDTH) stage2_alu_out_addr + (clk, reset, 1'b1, alu_out_addr, alu_out_addr_stage2); + register_sync_with_enable #(SRC_ADDR_WIDTH) stage3_alu_out_addr + (clk, reset, 1'b1, alu_out_addr_stage2, alu_out_addr_stage3); +//============================================================================== + +//============================================================================== +// Assigns +//============================================================================== +//============================================================================== + +//============================================================================== +// PU OBUF LD FIFO +//============================================================================== + assign obuf_ld_stream_write_ready = ~ld_req_buf_almost_full; + fifo_asymmetric #( + .WR_DATA_WIDTH ( OBUF_AXI_DATA_WIDTH ), + .RD_DATA_WIDTH ( SIMD_INTERIM_WIDTH ), + .WR_ADDR_WIDTH ( 3 ) + ) ld_req_buf ( + .clk ( clk ), //input + .reset ( reset ), //input + .s_write_req ( obuf_ld_stream_write_req ), //input + .s_write_data ( obuf_ld_stream_write_data ), //input + .s_write_ready ( ), //output + .s_read_req ( obuf_ld_stream_read_req ), //input + .s_read_ready ( obuf_ld_stream_read_ready ), //output + .s_read_data ( obuf_ld_stream_read_data ), //output + .almost_full ( ld_req_buf_almost_full ), //output + .almost_empty ( ld_req_buf_almost_empty ), //output + .fifo_count ( ld_req_buf_fifo_count ) + ); +//============================================================================== + +//============================================================================== +// PU Store FIFO +//============================================================================== + assign ddr_st_stream_write_ready = ~st_req_buf_almost_full; +generate +for (i=0; i _alu_in1; + assign max_out = gt_out ? _alu_in0 : _alu_in1; + assign min_out = ~gt_out ? _alu_in0 : _alu_in1; + assign mvhi_out = {imm, 16'b0}; + + assign shift_amount = _alu_in1; + assign _rshift_out = $signed(alu_in0) >>> shift_amount; + + wire signed [ DATA_WIDTH -1 : 0 ] _max; + wire signed [ DATA_WIDTH -1 : 0 ] _min; + wire overflow; + wire sign; + + assign overflow = (_rshift_out > _max) || (_rshift_out < _min); + assign sign = $signed(alu_in0) < 0; + + assign _max = (1 << (DATA_WIDTH - 1)) - 1; + assign _min = -(1 << (DATA_WIDTH - 1)); + + assign rshift_out = overflow ? sign ? _min : _max : _rshift_out; + + always @(*) + begin + case (fn) + FN_NOP: alu_out_d = alu_in0; + FN_ADD: alu_out_d = add_out; + FN_SUB: alu_out_d = sub_out; + FN_MUL: alu_out_d = mul_out; + FN_MVHI: alu_out_d = mvhi_out; + FN_MAX: alu_out_d = max_out; + FN_MIN: alu_out_d = min_out; + FN_RSHIFT: alu_out_d = rshift_out; + default: alu_out_d = 'd0; + endcase + end + + always @(posedge clk) + begin + if (fn_valid) + alu_out_q <= alu_out_d; + end + + assign alu_out = alu_out_q; + +endmodule +`timescale 1ns / 1ps +module reg_file #( + parameter integer DATA_WIDTH = 32, + parameter integer ADDR_WIDTH = 4 +) ( + input wire clk, + input wire rd_req_0, + input wire [ ADDR_WIDTH -1 : 0 ] rd_addr_0, + output wire [ DATA_WIDTH -1 : 0 ] rd_data_0, + input wire rd_req_1, + input wire [ ADDR_WIDTH -1 : 0 ] rd_addr_1, + output wire [ DATA_WIDTH -1 : 0 ] rd_data_1, + input wire wr_req_0, + input wire [ ADDR_WIDTH -1 : 0 ] wr_addr_0, + input wire [ DATA_WIDTH -1 : 0 ] wr_data_0 +); + +////========================================= +//// Wires and Regs +////========================================= +// (* ram_style = "distributed" *) +// reg [ DATA_WIDTH -1 : 0 ] mem [0 : (1 << ADDR_WIDTH) - 1]; +// reg [ DATA_WIDTH -1 : 0 ] mem_copy [0 : (1 << ADDR_WIDTH) - 1]; +// reg [ DATA_WIDTH -1 : 0 ] rd_data_0_q; +// reg [ DATA_WIDTH -1 : 0 ] rd_data_1_q; +////========================================= +// +// +// always @(posedge clk) +// begin +// if (rd_req_0) +// rd_data_0_q <= mem[rd_addr_0]; +// end +// assign rd_data_0 = rd_data_0_q; +// +// always @(posedge clk) +// begin +// if (rd_req_1) +// rd_data_1_q <= mem_copy[rd_addr_1]; +// end +// assign rd_data_1 = rd_data_1_q; +// +// always @(posedge clk) +// begin +// if (wr_req_0) +// mem[wr_addr_0] <= wr_data_0; +// mem_copy[wr_addr_0] <= wr_data_0; +// end + wire reset; + ram #( + .ADDR_WIDTH ( ADDR_WIDTH), + .DATA_WIDTH ( DATA_WIDTH) + ) u_ram1( + .clk ( clk ), + .reset ( reset ), + .s_write_addr ( wr_addr_0), + .s_write_req ( wr_req_0), + .s_write_data ( wr_data_0), + .s_read_addr ( rd_addr_0), + .s_read_req ( rd_req_0), + .s_read_data ( rd_data_0) + ); + + ram #( + .ADDR_WIDTH ( ADDR_WIDTH), + .DATA_WIDTH ( DATA_WIDTH) + ) u_ram2( + .clk ( clk ), + .reset ( reset ), + .s_write_addr ( wr_addr_0), + .s_write_req ( wr_req_0), + .s_write_data ( wr_data_0), + .s_read_addr ( rd_addr_1), + .s_read_req ( rd_req_1), + .s_read_data ( rd_data_1) + ); + +endmodule +// +// Wrapper for memory +// +// Hardik Sharma +// (hsharma@gatech.edu) + +`timescale 1ns/1ps +module ldst_ddr_wrapper #( + // Internal Parameters + parameter integer MEM_ID = 0, + parameter integer STORE_ENABLED = MEM_ID == 1 ? 1 : 0, + parameter integer MEM_REQ_W = 16, + parameter integer LOOP_ITER_W = 16, + parameter integer ADDR_STRIDE_W = 16, + parameter integer LOOP_ID_W = 5, + parameter integer BUF_TYPE_W = 2, + parameter integer NUM_TAGS = 4, + parameter integer TAG_W = $clog2(NUM_TAGS), + parameter integer SIMD_DATA_WIDTH = 256, + + // AXI + parameter integer AXI_ID_WIDTH = 1, + parameter integer AXI_ADDR_WIDTH = 42, + parameter integer AXI_DATA_WIDTH = 64, + parameter integer AXI_BURST_WIDTH = 8, + parameter integer WSTRB_W = AXI_DATA_WIDTH/8 +) ( + input wire clk, + input wire reset, + + input wire pu_block_start, + input wire start, + output wire done, + + input wire [ AXI_ADDR_WIDTH -1 : 0 ] st_base_addr, + input wire [ AXI_ADDR_WIDTH -1 : 0 ] ld0_base_addr, + input wire [ AXI_ADDR_WIDTH -1 : 0 ] ld1_base_addr, + + // Programming + input wire cfg_loop_stride_v, + input wire [ ADDR_STRIDE_W -1 : 0 ] cfg_loop_stride, + input wire [ 3 -1 : 0 ] cfg_loop_stride_type, + + input wire [ LOOP_ITER_W -1 : 0 ] cfg_loop_iter, + input wire cfg_loop_iter_v, + input wire [ 3 -1 : 0 ] cfg_loop_iter_type, + + input wire cfg_mem_req_v, + input wire [ 2 -1 : 0 ] cfg_mem_req_type, + + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] pu_ddr_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] pu_ddr_awlen, + output wire [ 3 -1 : 0 ] pu_ddr_awsize, + output wire [ 2 -1 : 0 ] pu_ddr_awburst, + output wire pu_ddr_awvalid, + input wire pu_ddr_awready, + // Master Interface Write Data + output wire [ AXI_DATA_WIDTH -1 : 0 ] pu_ddr_wdata, + output wire [ WSTRB_W -1 : 0 ] pu_ddr_wstrb, + output wire pu_ddr_wlast, + output wire pu_ddr_wvalid, + input wire pu_ddr_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] pu_ddr_bresp, + input wire pu_ddr_bvalid, + output wire pu_ddr_bready, + // Master Interface Read Address + output wire [ 1 -1 : 0 ] pu_ddr_arid, + output wire [ AXI_ADDR_WIDTH -1 : 0 ] pu_ddr_araddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] pu_ddr_arlen, + output wire [ 3 -1 : 0 ] pu_ddr_arsize, + output wire [ 2 -1 : 0 ] pu_ddr_arburst, + output wire pu_ddr_arvalid, + input wire pu_ddr_arready, + // Master Interface Read Data + input wire [ 1 -1 : 0 ] pu_ddr_rid, + input wire [ AXI_DATA_WIDTH -1 : 0 ] pu_ddr_rdata, + input wire [ 2 -1 : 0 ] pu_ddr_rresp, + input wire pu_ddr_rlast, + input wire pu_ddr_rvalid, + output wire pu_ddr_rready, + + // LD0 + output wire ddr_ld0_stream_write_req, + input wire ddr_ld0_stream_write_ready, + output wire [ AXI_DATA_WIDTH -1 : 0 ] ddr_ld0_stream_write_data, + + // LD1 + output wire ddr_ld1_stream_write_req, + input wire ddr_ld1_stream_write_ready, + output wire [ AXI_DATA_WIDTH -1 : 0 ] ddr_ld1_stream_write_data, + + // Stores + output wire ddr_st_stream_read_req, + input wire ddr_st_stream_read_ready, + input wire [ AXI_DATA_WIDTH -1 : 0 ] ddr_st_stream_read_data + +); + +//============================================================================== +// Localparams +//============================================================================== +//============================================================================== + +//============================================================================== +// Wires/Regs +//============================================================================== + wire st_done; + wire [ AXI_DATA_WIDTH -1 : 0 ] ddr_ld0_data; + wire [ AXI_DATA_WIDTH -1 : 0 ] ddr_ld1_data; + // Loads + wire mem_write_req; + wire mem_write_ready; + wire [ AXI_DATA_WIDTH -1 : 0 ] mem_write_data; + wire [ AXI_ID_WIDTH -1 : 0 ] mem_write_id; + + wire ld0_req_buf_almost_full; + wire ld0_req_buf_almost_empty; + + wire [ AXI_ID_WIDTH -1 : 0 ] ld_req_id; + + wire [ MEM_REQ_W -1 : 0 ] st_req_size; + + wire st_stall; + wire [ AXI_ADDR_WIDTH -1 : 0 ] st_addr; + wire st_addr_req; + wire st_addr_valid; + wire [ ADDR_STRIDE_W -1 : 0 ] st_stride; + wire st_stride_v; + wire st_ready; + reg [ LOOP_ID_W -1 : 0 ] st_loop_id_counter; + wire st_loop_iter_v; + wire [ LOOP_ITER_W -1 : 0 ] st_loop_iter; + wire st_loop_done; + wire st_loop_init; + wire st_loop_enter; + wire st_loop_exit; + wire [ LOOP_ID_W -1 : 0 ] st_loop_index; + wire st_loop_index_valid; + wire st_loop_index_step; + + wire [ AXI_ADDR_WIDTH -1 : 0 ] ld_addr; + wire ld_addr_req; + wire ld_ready; + wire ld_done; + wire [ MEM_REQ_W -1 : 0 ] ld_req_size; + + wire ld0_stall; + wire [ AXI_ADDR_WIDTH -1 : 0 ] ld0_addr; + wire ld0_addr_req; + wire [ ADDR_STRIDE_W -1 : 0 ] ld0_stride; + wire ld0_stride_v; + reg ld0_required; + wire ld0_ready; + reg [ LOOP_ID_W -1 : 0 ] ld0_loop_id_counter; + wire ld0_loop_iter_v; + wire [ LOOP_ITER_W -1 : 0 ] ld0_loop_iter; + wire ld0_loop_done; + wire ld0_loop_init; + wire ld0_loop_enter; + wire ld0_loop_exit; + wire [ LOOP_ID_W -1 : 0 ] ld0_loop_index; + wire ld0_loop_index_valid; + wire ld0_loop_index_step; + + wire ld1_stall; + wire [ AXI_ADDR_WIDTH -1 : 0 ] ld1_addr; + wire ld1_addr_req; + wire [ ADDR_STRIDE_W -1 : 0 ] ld1_stride; + wire ld1_stride_v; + reg ld1_required; + wire ld1_ready; + reg [ LOOP_ID_W -1 : 0 ] ld1_loop_id_counter; + wire ld1_loop_iter_v; + wire [ LOOP_ITER_W -1 : 0 ] ld1_loop_iter; + wire ld1_loop_done; + wire ld1_loop_init; + wire ld1_loop_enter; + wire ld1_loop_exit; + wire [ LOOP_ID_W -1 : 0 ] ld1_loop_index; + wire ld1_loop_index_valid; + wire ld1_loop_index_step; +//============================================================================== + +//============================================================================== +// LD/ST required +//============================================================================== + always @(posedge clk) + begin + if (reset) + ld0_required <= 1'b0; + else begin + if (pu_block_start) + ld0_required <= 1'b0; + else if (cfg_mem_req_v && cfg_mem_req_type == 2) + ld0_required <= 1'b1; + end + end + + always @(posedge clk) + begin + if (reset) + ld1_required <= 1'b0; + else begin + if (pu_block_start) + ld1_required <= 1'b0; + else if (cfg_mem_req_v && cfg_mem_req_type == 3) + ld1_required <= 1'b1; + end + end + + assign st_req_size = SIMD_DATA_WIDTH/AXI_DATA_WIDTH; +//============================================================================== + +//============================================================================== +// Assigns +//============================================================================== + assign st_stride_v = cfg_loop_stride_v && (cfg_loop_stride_type == 1); + assign ld0_stride_v = cfg_loop_stride_v && (cfg_loop_stride_type == 2); + assign ld1_stride_v = cfg_loop_stride_v && (cfg_loop_stride_type == 3); + + assign st_stall = ~st_ready; + assign ld0_stall = ld0_required && ~ld0_ready; + assign ld1_stall = ld1_required && ~ld1_ready; + assign st_addr_req = st_addr_valid && ~st_stall; +//============================================================================== + +//============================================================================== +// FSM for Loads +//============================================================================== + reg ld_addr_state_d; + reg ld_addr_state_q; + always @(posedge clk) + begin + if (reset) + ld_addr_state_q <= 1'b0; + else + ld_addr_state_q <= ld_addr_state_d; + end + always @(*) + begin + ld_addr_state_d = ld_addr_state_q; + case (ld_addr_state_q) + 0: begin + if (ld0_required && ld0_addr_req && ld_ready) + ld_addr_state_d = 1'b1; + end + 1: begin + if (ld1_required && ld1_addr_req && ld_ready) + ld_addr_state_d = 1'b0; + end + endcase + end + + assign ld0_ready = ld_ready && ld_addr_state_q == 1'b0; + assign ld1_ready = ld_ready && ld_addr_state_q == 1'b1; + + assign ld_req_size = SIMD_DATA_WIDTH / AXI_DATA_WIDTH; + assign ld_addr = ld_addr_state_q == 1'b0 ? ld0_addr : ld1_addr; + assign ld_addr_req = (ld_addr_state_q == 1'b0 ? ld0_addr_req && ld0_required : ld1_addr_req && ld1_required) && ld_ready; + assign ld_req_id = ld_addr_state_q; + + assign ddr_ld0_stream_write_req = mem_write_id == 1'b0 && mem_write_req; + assign ddr_ld0_stream_write_data = mem_write_data; + + assign ddr_ld1_stream_write_req = mem_write_id == 1'b1 && mem_write_req; + assign ddr_ld1_stream_write_data = mem_write_data; + + // assign mem_write_ready = mem_write_id == 1'b0 ? ddr_ld0_stream_write_ready : ddr_ld1_stream_write_ready; + assign mem_write_ready = ddr_ld0_stream_write_ready && ddr_ld1_stream_write_ready; + // assign mem_write_ready = (ddr_ld0_stream_write_ready || ~ld0_required) && + // (ddr_ld1_stream_write_ready || ~ld1_required); +//============================================================================== + +//============================================================================== +// FSM for Stores +//============================================================================== + reg [2-1:0] st_state_d; + reg [2-1:0] st_state_q; + reg [5-1:0] wait_cycles_d; + reg [5-1:0] wait_cycles_q; + localparam integer ST_IDLE = 0; + localparam integer ST_BUSY = 1; + localparam integer ST_WAIT = 2; + localparam integer ST_DONE = 3; + + always @(posedge clk) + begin + if (reset) begin + st_state_q <= ST_IDLE; + wait_cycles_q <= 0; + end else begin + st_state_q <= st_state_d; + wait_cycles_q <= wait_cycles_d; + end + end + + always @(*) + begin + st_state_d = st_state_q; + wait_cycles_d = wait_cycles_q; + case (st_state_q) + ST_IDLE: begin + if (start) + st_state_d = ST_BUSY; + end + ST_BUSY: begin + if (st_loop_done) begin + st_state_d = ST_WAIT; + wait_cycles_d = 4; + end + end + ST_WAIT: begin + if (wait_cycles_q != 0) + wait_cycles_d = wait_cycles_d - 1'b1; + else if (st_done) + st_state_d = ST_DONE; + end + ST_DONE: begin + st_state_d = ST_IDLE; + end + endcase + end + + assign done = st_state_q == ST_DONE; +//============================================================================== + +//============================================================================== +// Loop controller - ST +//============================================================================== + always@(posedge clk) + begin + if (reset) + st_loop_id_counter <= 'b0; + else begin + if (cfg_loop_iter_v && cfg_loop_iter_type == 1) + st_loop_id_counter <= st_loop_id_counter + 1'b1; + else if (start) + st_loop_id_counter <= 'b0; + end + end + + assign st_loop_iter_v = cfg_loop_iter_v && cfg_loop_iter_type == 1; + assign st_loop_iter = cfg_loop_iter; + + controller_fsm #( + .LOOP_ID_W ( LOOP_ID_W ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .IMEM_ADDR_W ( LOOP_ID_W ) + ) loop_ctrl_st ( + .clk ( clk ), //input + .reset ( reset ), //input + .stall ( st_stall ), //input + .cfg_loop_iter_v ( st_loop_iter_v ), //input + .cfg_loop_iter ( st_loop_iter ), //input + .cfg_loop_iter_loop_id ( st_loop_id_counter ), //input + .start ( start ), //input + .done ( st_loop_done ), //output + .loop_init ( st_loop_init ), //output + .loop_enter ( st_loop_enter ), //output + .loop_last_iter ( ), //output + .loop_exit ( st_loop_exit ), //output + .loop_index ( st_loop_index ), //output + .loop_index_valid ( st_loop_index_valid ) //output + ); +//============================================================================== + +//============================================================================== +// Address generators - ST +//============================================================================== + assign st_stride = cfg_loop_stride * SIMD_DATA_WIDTH / 8; + assign st_loop_index_step = st_loop_index_valid && ~st_stall; + mem_walker_stride #( + .ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) mws_st ( + .clk ( clk ), //input + .reset ( reset ), //input + .base_addr ( st_base_addr ), //input + .loop_ctrl_done ( st_loop_done ), //input + .loop_index ( st_loop_index ), //input + .loop_index_valid ( st_loop_index_step ), //input + .loop_init ( st_loop_init ), //input + .loop_enter ( st_loop_enter ), //input + .loop_exit ( st_loop_exit ), //input + .cfg_addr_stride_v ( st_stride_v ), //input + .cfg_addr_stride ( st_stride ), //input + .addr_out ( st_addr ), //output + .addr_out_valid ( st_addr_valid ) //output + ); +//============================================================================== + +//============================================================================== +// Loop controller - LD0 +//============================================================================== + always@(posedge clk) + begin + if (reset) + ld0_loop_id_counter <= 'b0; + else begin + if (cfg_loop_iter_v && cfg_loop_iter_type == 2) + ld0_loop_id_counter <= ld0_loop_id_counter + 1'b1; + else if (start) + ld0_loop_id_counter <= 'b0; + end + end + + assign ld0_loop_iter_v = cfg_loop_iter_v && cfg_loop_iter_type == 2; + assign ld0_loop_iter = cfg_loop_iter; + + controller_fsm #( + .LOOP_ID_W ( LOOP_ID_W ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .IMEM_ADDR_W ( LOOP_ID_W ) + ) loop_ctrl_ld0 ( + .clk ( clk ), //input + .reset ( reset ), //input + .stall ( ld0_stall ), //input + .cfg_loop_iter_v ( ld0_loop_iter_v ), //input + .cfg_loop_iter ( ld0_loop_iter ), //input + .cfg_loop_iter_loop_id ( ld0_loop_id_counter ), //input + .start ( start ), //input + .done ( ld0_loop_done ), //output + .loop_init ( ld0_loop_init ), //output + .loop_enter ( ld0_loop_enter ), //output + .loop_last_iter ( ), //output + .loop_exit ( ld0_loop_exit ), //output + .loop_index ( ld0_loop_index ), //output + .loop_index_valid ( ld0_loop_index_valid ) //output + ); +//============================================================================== + +//============================================================================== +// Address generators - LD0 +//============================================================================== + assign ld0_loop_index_step = ld0_loop_index_valid && ~ld0_stall; + assign ld0_stride = cfg_loop_stride * SIMD_DATA_WIDTH / 8; + mem_walker_stride #( + .ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) mws_ld0 ( + .clk ( clk ), //input + .reset ( reset ), //input + .base_addr ( ld0_base_addr ), //input + .loop_ctrl_done ( ld0_loop_done ), //input + .loop_index ( ld0_loop_index ), //input + .loop_index_valid ( ld0_loop_index_step ), //input + .loop_init ( ld0_loop_init ), //input + .loop_enter ( ld0_loop_enter ), //input + .loop_exit ( ld0_loop_exit ), //input + .cfg_addr_stride_v ( ld0_stride_v ), //input + .cfg_addr_stride ( ld0_stride ), //input + .addr_out ( ld0_addr ), //output + .addr_out_valid ( ld0_addr_req ) //output + ); +//============================================================================== + +//============================================================================== +// Loop controller - LD1 +//============================================================================== + always@(posedge clk) + begin + if (reset) + ld1_loop_id_counter <= 'b0; + else begin + if (cfg_loop_iter_v && cfg_loop_iter_type == 3) + ld1_loop_id_counter <= ld1_loop_id_counter + 1'b1; + else if (start) + ld1_loop_id_counter <= 'b0; + end + end + + assign ld1_loop_iter_v = cfg_loop_iter_v && cfg_loop_iter_type == 3; + assign ld1_loop_iter = cfg_loop_iter; + + controller_fsm #( + .LOOP_ID_W ( LOOP_ID_W ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .IMEM_ADDR_W ( LOOP_ID_W ) + ) loop_ctrl_ld1 ( + .clk ( clk ), //input + .reset ( reset ), //input + .stall ( ld1_stall ), //input + .cfg_loop_iter_v ( ld1_loop_iter_v ), //input + .cfg_loop_iter ( ld1_loop_iter ), //input + .cfg_loop_iter_loop_id ( ld1_loop_id_counter ), //input + .start ( start ), //input + .done ( ld1_loop_done ), //output + .loop_init ( ld1_loop_init ), //output + .loop_enter ( ld1_loop_enter ), //output + .loop_last_iter ( ), //output + .loop_exit ( ld1_loop_exit ), //output + .loop_index ( ld1_loop_index ), //output + .loop_index_valid ( ld1_loop_index_valid ) //output + ); +//============================================================================== + +//============================================================================== +// Address generators - LD1 +//============================================================================== + assign ld1_loop_index_step = ld1_loop_index_valid && ~ld1_stall; + assign ld1_stride = cfg_loop_stride * SIMD_DATA_WIDTH / 8; + mem_walker_stride #( + .ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) mws_ld1 ( + .clk ( clk ), //input + .reset ( reset ), //input + .base_addr ( ld1_base_addr ), //input + .loop_ctrl_done ( ld1_loop_done ), //input + .loop_index ( ld1_loop_index ), //input + .loop_index_valid ( ld1_loop_index_step ), //input + .loop_init ( ld1_loop_init ), //input + .loop_enter ( ld1_loop_enter ), //input + .loop_exit ( ld1_loop_exit ), //input + .cfg_addr_stride_v ( ld1_stride_v ), //input + .cfg_addr_stride ( ld1_stride ), //input + .addr_out ( ld1_addr ), //output + .addr_out_valid ( ld1_addr_req ) //output + ); +//============================================================================== + +//============================================================================== +// AXI4 Memory Mapped interface +//============================================================================== + wire [AXI_ID_WIDTH-1:0] st_addr_req_id; + assign st_addr_req_id = 0; + axi_master #( + .TX_SIZE_WIDTH ( MEM_REQ_W ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_BURST_WIDTH ( AXI_BURST_WIDTH ) + ) u_axi_mm_master ( + .clk ( clk ), + .reset ( reset ), + .m_axi_awaddr ( pu_ddr_awaddr ), + .m_axi_awlen ( pu_ddr_awlen ), + .m_axi_awsize ( pu_ddr_awsize ), + .m_axi_awburst ( pu_ddr_awburst ), + .m_axi_awvalid ( pu_ddr_awvalid ), + .m_axi_awready ( pu_ddr_awready ), + .m_axi_wdata ( pu_ddr_wdata ), + .m_axi_wstrb ( pu_ddr_wstrb ), + .m_axi_wlast ( pu_ddr_wlast ), + .m_axi_wvalid ( pu_ddr_wvalid ), + .m_axi_wready ( pu_ddr_wready ), + .m_axi_bresp ( pu_ddr_bresp ), + .m_axi_bvalid ( pu_ddr_bvalid ), + .m_axi_bready ( pu_ddr_bready ), + .m_axi_arid ( pu_ddr_arid ), + .m_axi_araddr ( pu_ddr_araddr ), + .m_axi_arlen ( pu_ddr_arlen ), + .m_axi_arsize ( pu_ddr_arsize ), + .m_axi_arburst ( pu_ddr_arburst ), + .m_axi_arvalid ( pu_ddr_arvalid ), + .m_axi_arready ( pu_ddr_arready ), + .m_axi_rid ( pu_ddr_rid ), + .m_axi_rdata ( pu_ddr_rdata ), + .m_axi_rresp ( pu_ddr_rresp ), + .m_axi_rlast ( pu_ddr_rlast ), + .m_axi_rvalid ( pu_ddr_rvalid ), + .m_axi_rready ( pu_ddr_rready ), + // Buffer + .mem_write_id ( mem_write_id ), + .mem_write_req ( mem_write_req ), + .mem_write_data ( mem_write_data ), + .mem_write_ready ( mem_write_ready ), + .mem_read_req ( ddr_st_stream_read_req ), + .mem_read_data ( ddr_st_stream_read_data ), + .mem_read_ready ( ddr_st_stream_read_ready ), + // AXI RD Req + .rd_req_id ( ld_req_id ), + .rd_req ( ld_addr_req ), + .rd_done ( ld_done ), + .rd_ready ( ld_ready ), + .rd_req_size ( ld_req_size ), + .rd_addr ( ld_addr ), + // AXI WR Req + .wr_req_id ( st_addr_req_id ), + .wr_req ( st_addr_req ), + .wr_ready ( st_ready ), + .wr_req_size ( st_req_size ), + .wr_addr ( st_addr ), + .wr_done ( st_done ) + ); +//============================================================================== + +//============================================================================== +// VCD +//============================================================================== +`ifdef COCOTB_TOPLEVEL_pu_ld_obuf_wrapper +initial begin + $dumpfile("pu_ld_obuf_wrapper.vcd"); + $dumpvars(0, pu_ld_obuf_wrapper); +end +`endif +//============================================================================== +endmodule +// +// Register +// +// Hardik Sharma +// (hsharma@gatech.edu) + +`timescale 1ns/1ps +module register_sync_with_enable #( + parameter integer WIDTH = 8 +) ( + input wire clk, + input wire reset, + input wire enable, + input wire [ WIDTH -1 : 0 ] in, + output wire [ WIDTH -1 : 0 ] out +); + + reg [ WIDTH -1 : 0 ] out_reg; + + always @(posedge clk) + begin + if (reset) + out_reg <= 'b0; + else if (enable) + out_reg <= in; + end + + assign out = out_reg; + +endmodule +// +// IBUF +// +// Hardik Sharma +// (hsharma@gatech.edu) +`timescale 1ns/1ps +module ibuf #( + parameter integer TAG_W = 2, // Log number of banks + parameter integer MEM_DATA_WIDTH = 64, + parameter integer ARRAY_N = 1, + parameter integer DATA_WIDTH = 32, + parameter integer BUF_ADDR_WIDTH = 10, + + parameter integer GROUP_SIZE = MEM_DATA_WIDTH / DATA_WIDTH, + parameter integer GROUP_ID_W = GROUP_SIZE == 1 ? 0 : $clog2(GROUP_SIZE), + parameter integer BUF_ID_W = $clog2(ARRAY_N) - GROUP_ID_W, + + parameter integer MEM_ADDR_WIDTH = BUF_ADDR_WIDTH + BUF_ID_W, + parameter integer BUF_DATA_WIDTH = ARRAY_N * DATA_WIDTH +) +( + input wire clk, + input wire reset, + + input wire mem_write_req, + input wire [ MEM_ADDR_WIDTH -1 : 0 ] mem_write_addr, + input wire [ MEM_DATA_WIDTH -1 : 0 ] mem_write_data, + + input wire buf_read_req, + input wire [ BUF_ADDR_WIDTH -1 : 0 ] buf_read_addr, + output wire [ BUF_DATA_WIDTH -1 : 0 ] buf_read_data + ); + + genvar n; + generate + for (n=0; n DDR AXI4 interface + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] mws_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] mws_awlen, + output wire [ 3 -1 : 0 ] mws_awsize, + output wire [ 2 -1 : 0 ] mws_awburst, + output wire mws_awvalid, + input wire mws_awready, + // Master Interface Write Data + output wire [ AXI_DATA_WIDTH -1 : 0 ] mws_wdata, + output wire [ WSTRB_W -1 : 0 ] mws_wstrb, + output wire mws_wlast, + output wire mws_wvalid, + input wire mws_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] mws_bresp, + input wire mws_bvalid, + output wire mws_bready, + // Master Interface Read Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] mws_araddr, + output wire [ AXI_ID_WIDTH -1 : 0 ] mws_arid, + output wire [ AXI_BURST_WIDTH -1 : 0 ] mws_arlen, + output wire [ 3 -1 : 0 ] mws_arsize, + output wire [ 2 -1 : 0 ] mws_arburst, + output wire mws_arvalid, + input wire mws_arready, + // Master Interface Read Data + input wire [ AXI_DATA_WIDTH -1 : 0 ] mws_rdata, + input wire [ AXI_ID_WIDTH -1 : 0 ] mws_rid, + input wire [ 2 -1 : 0 ] mws_rresp, + input wire mws_rlast, + input wire mws_rvalid, + output wire mws_rready +); + +//============================================================================== +// Localparams +//============================================================================== + localparam integer LDMEM_IDLE = 0; + localparam integer LDMEM_CHECK_RAW = 1; + localparam integer LDMEM_BUSY = 2; + localparam integer LDMEM_WAIT_0 = 3; + localparam integer LDMEM_WAIT_1 = 4; + localparam integer LDMEM_WAIT_2 = 5; + localparam integer LDMEM_WAIT_3 = 6; + localparam integer LDMEM_DONE = 7; + + localparam integer STMEM_IDLE = 0; + localparam integer STMEM_DDR = 1; + localparam integer STMEM_WAIT_0 = 2; + localparam integer STMEM_WAIT_1 = 3; + localparam integer STMEM_WAIT_2 = 4; + localparam integer STMEM_WAIT_3 = 5; + localparam integer STMEM_DONE = 6; + localparam integer STMEM_PU = 7; + + localparam integer MEM_LD = 0; + localparam integer MEM_ST = 1; + localparam integer MEM_RD = 2; + localparam integer MEM_WR = 3; +//============================================================================== + +//============================================================================== +// Wires/Regs +//============================================================================== + wire compute_tag_done; + wire compute_tag_reuse; + wire compute_tag_ready; + wire [ TAG_W -1 : 0 ] compute_tag; + wire [ TAG_W -1 : 0 ] compute_tag_delayed; + wire ldmem_tag_done; + wire ldmem_tag_ready; + wire [ TAG_W -1 : 0 ] ldmem_tag; + wire stmem_tag_done; + wire stmem_tag_ready; + wire [ TAG_W -1 : 0 ] stmem_tag; + wire stmem_ddr_pe_sw; + + reg [ 4 -1 : 0 ] ldmem_state_d; + reg [ 4 -1 : 0 ] ldmem_state_q; + + reg [ 3 -1 : 0 ] stmem_state_d; + reg [ 3 -1 : 0 ] stmem_state_q; + + wire ld_mem_req_v; + wire st_mem_req_v; + + wire [ TAG_W -1 : 0 ] tag; + + + reg ld_iter_v_q; + reg [ LOOP_ITER_W -1 : 0 ] iter_q; + + reg [ LOOP_ID_W -1 : 0 ] ld_loop_id_counter; + + wire [ LOOP_ID_W -1 : 0 ] mws_ld_loop_iter_loop_id; + wire [ LOOP_ITER_W -1 : 0 ] mws_ld_loop_iter; + wire mws_ld_loop_iter_v; + wire mws_ld_start; + wire mws_ld_done; + wire mws_ld_stall; + wire mws_ld_init; + wire mws_ld_enter; + wire mws_ld_exit; + wire [ LOOP_ID_W -1 : 0 ] mws_ld_index; + wire mws_ld_index_valid; + wire mws_ld_step; + + wire [ LOOP_ID_W -1 : 0 ] mws_st_loop_iter_loop_id; + wire [ LOOP_ITER_W -1 : 0 ] mws_st_loop_iter; + wire mws_st_loop_iter_v; + wire mws_st_start; + wire mws_st_done; + wire mws_st_stall; + wire mws_st_init; + wire mws_st_enter; + wire mws_st_exit; + wire [ LOOP_ID_W -1 : 0 ] mws_st_index; + wire mws_st_index_valid; + wire mws_st_step; + + wire ld_stride_v; + wire [ ADDR_STRIDE_W -1 : 0 ] ld_stride; + wire [ BUF_TYPE_W -1 : 0 ] ld_stride_id; + wire st_stride_v; + wire [ ADDR_STRIDE_W -1 : 0 ] st_stride; + wire [ BUF_TYPE_W -1 : 0 ] st_stride_id; + + wire [ ADDR_WIDTH -1 : 0 ] ld_addr; + wire [ ADDR_WIDTH -1 : 0 ] mws_ld_base_addr; + wire ld_addr_v; + wire [ ADDR_WIDTH -1 : 0 ] st_addr; + wire [ ADDR_WIDTH -1 : 0 ] mws_st_base_addr; + wire st_addr_v; + + + reg [ MEM_REQ_W -1 : 0 ] ld_req_size; + reg [ MEM_REQ_W -1 : 0 ] st_req_size; + + wire ld_req_valid_d; + reg ld_req_valid_q; + + //reg [ ADDR_WIDTH -1 : 0 ] tag_ld_addr[0:NUM_TAGS-1]; + + reg [ ADDR_WIDTH -1 : 0 ] ld_req_addr; + + // reg [ MEM_REQ_W -1 : 0 ] ld_req_loop_id; + reg [ MEM_REQ_W -1 : 0 ] st_req_loop_id; + + wire axi_rd_req; + wire [ AXI_ID_WIDTH -1 : 0 ] axi_rd_req_id; + wire axi_rd_done; + wire [ MEM_REQ_W -1 : 0 ] axi_rd_req_size; + wire axi_rd_ready; + wire [ AXI_ADDR_WIDTH -1 : 0 ] axi_rd_addr; + + wire axi_wr_req; + wire [ AXI_ID_WIDTH -1 : 0 ] axi_wr_req_id; + wire axi_wr_done; + wire [ MEM_REQ_W -1 : 0 ] axi_wr_req_size; + wire axi_wr_ready; + wire [ AXI_ADDR_WIDTH -1 : 0 ] axi_wr_addr; + + wire [ AXI_ID_WIDTH -1 : 0 ] mem_write_id; + wire mem_write_req; + wire [ AXI_DATA_WIDTH -1 : 0 ] mem_write_data; + reg [ MEM_ADDR_W -1 : 0 ] mem_write_addr; + wire mem_write_ready; + wire [ AXI_DATA_WIDTH -1 : 0 ] mem_read_data; + reg [ MEM_ADDR_W -1 : 0 ] mem_read_addr; + wire mem_read_req; + wire mem_read_ready; + + // Adding register to buf read data + wire [ BUF_DATA_WIDTH -1 : 0 ] _buf_read_data; +//============================================================================== + +//============================================================================== +// Assigns +//============================================================================== + assign ld_stride = cfg_loop_stride; + assign ld_stride_v = cfg_loop_stride_v && cfg_loop_stride_loop_id == 1 + MEM_ID && cfg_loop_stride_type == MEM_LD && cfg_loop_stride_id == MEM_ID; + assign st_stride = cfg_loop_stride; + assign st_stride_v = cfg_loop_stride_v && cfg_loop_stride_loop_id == 1 + MEM_ID && cfg_loop_stride_type == MEM_ST && cfg_loop_stride_id == MEM_ID; + + //assign mws_ld_base_addr = tag_ld_addr[ldmem_tag]; + assign axi_rd_req = ld_req_valid_q; + assign axi_rd_req_size = ld_req_size * (ARRAY_M * DATA_WIDTH) / AXI_DATA_WIDTH; + assign axi_rd_addr = ld_req_addr; + + assign axi_wr_req = 1'b0; + assign axi_wr_req_id = 1'b0; + assign axi_wr_req_size = 0; + assign axi_wr_addr = 0; +//============================================================================== + +//============================================================================== +// Address generators +//============================================================================== + assign mws_ld_stall = ~ldmem_tag_ready || ~axi_rd_ready; + assign mws_ld_step = mws_ld_index_valid && !mws_ld_stall; + mem_walker_stride #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) mws_ld ( + .clk ( clk ), //input + .reset ( reset ), //input + .base_addr ( mws_ld_base_addr ), //input + .loop_ctrl_done ( mws_ld_done ), //input + .loop_index ( mws_ld_index ), //input + .loop_index_valid ( mws_ld_step ), //input + .loop_init ( mws_ld_init ), //input + .loop_enter ( mws_ld_enter ), //input + .loop_exit ( mws_ld_exit ), //input + .cfg_addr_stride_v ( ld_stride_v ), //input + .cfg_addr_stride ( ld_stride ), //input + .addr_out ( ld_addr ), //output + .addr_out_valid ( ld_addr_v ) //output + ); + generate + if (STORE_ENABLED == 1) begin: STORE + assign mws_st_step = mws_st_index_valid && !mws_st_stall; + assign mws_st_stall = ~stmem_tag_ready || ~axi_wr_ready; + mem_walker_stride #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) mws_st ( + .clk ( clk ), //input + .reset ( reset ), //input + .base_addr ( mws_st_base_addr ), //input + .loop_ctrl_done ( mws_st_done ), //input + .loop_index ( mws_st_index ), //input + .loop_index_valid ( mws_st_step ), //input + .loop_init ( mws_st_init ), //input + .loop_enter ( mws_st_enter ), //input + .loop_exit ( mws_st_exit ), //input + .cfg_addr_stride_v ( st_stride_v ), //input + .cfg_addr_stride ( st_stride ), //input + .addr_out ( st_addr ), //output + .addr_out_valid ( st_addr_v ) //output + ); + + //assign mws_st_step = mws_st_index_valid && !mws_st_stall; + //assign mws_st_stall = ~stmem_tag_ready || ~axi_wr_ready; + end + endgenerate +//============================================================================== + +//============================================================= +// Loop controller +//============================================================= + always@(posedge clk) + begin + if (reset) + ld_loop_id_counter <= 'b0; + else begin + if (mws_ld_loop_iter_v) + ld_loop_id_counter <= ld_loop_id_counter + 1'b1; + else if (tag_req && tag_ready) + ld_loop_id_counter <= 'b0; + end + end + + always @(posedge clk) + begin + if (reset) + ld_iter_v_q <= 1'b0; + else begin + if (cfg_loop_iter_v && cfg_loop_iter_loop_id == 1 + MEM_ID) + ld_iter_v_q <= 1'b1; + else if (cfg_loop_iter_v || ld_stride_v) + ld_iter_v_q <= 1'b0; + end + end + + + assign mws_ld_start = ldmem_state_q == LDMEM_BUSY; + assign mws_ld_loop_iter_v = ld_stride_v && ld_iter_v_q; + assign mws_ld_loop_iter = iter_q; + assign mws_ld_loop_iter_loop_id = ld_loop_id_counter; + + always @(posedge clk) + begin + if (reset) begin + iter_q <= 'b0; + end + else if (cfg_loop_iter_v && cfg_loop_iter_loop_id == 1 + MEM_ID) begin + iter_q <= cfg_loop_iter; + end + end + + controller_fsm #( + .LOOP_ID_W ( LOOP_ID_W ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .IMEM_ADDR_W ( LOOP_ID_W ) + ) mws_ld_ctrl ( + .clk ( clk ), //input + .reset ( reset ), //input + .stall ( mws_ld_stall ), //input + .cfg_loop_iter_v ( mws_ld_loop_iter_v ), //input + .cfg_loop_iter ( mws_ld_loop_iter ), //input + .cfg_loop_iter_loop_id ( mws_ld_loop_iter_loop_id ), //input + .start ( mws_ld_start ), //input + .done ( mws_ld_done ), //output + .loop_init ( mws_ld_init ), //output + .loop_enter ( mws_ld_enter ), //output + .loop_last_iter ( ), //output + .loop_exit ( mws_ld_exit ), //output + .loop_index ( mws_ld_index ), //output + .loop_index_valid ( mws_ld_index_valid ) //output + ); +//============================================================= + +//============================================================================== +// Memory Request generation +//============================================================================== + assign ld_mem_req_v = cfg_mem_req_v && cfg_mem_req_loop_id == (1 + MEM_ID) && cfg_mem_req_type == MEM_LD && cfg_mem_req_id == MEM_ID; + always @(posedge clk) + begin + if (reset) begin + ld_req_size <= 'b0; + // ld_req_loop_id <= 'b0; + end + else if (ld_mem_req_v) begin + ld_req_size <= cfg_mem_req_size; + // ld_req_loop_id <= ld_loop_id_counter; + end + end + + // assign ld_req_valid_d = (ld_req_loop_id == mws_ld_index) && (mws_ld_enter || mws_ld_step); + // assign ld_req_valid_d = (ld_req_loop_id == mws_ld_index) && ld_addr_v; + assign ld_req_valid_d = ld_addr_v; + + always @(posedge clk) + begin + if (reset) begin + ld_req_valid_q <= 1'b0; + ld_req_addr <= 'b0; + end + else begin + ld_req_valid_q <= ld_req_valid_d; + ld_req_addr <= ld_addr; + end + end + + //always @(posedge clk) + //begin + // if (tag_req && tag_ready) begin + // tag_ld_addr[tag] <= tag_base_ld_addr; + // end + //end + + ram #( + .ADDR_WIDTH ( $clog2(NUM_TAGS)), + .DATA_WIDTH ( ADDR_WIDTH) + ) u_ram_tag_ld_1( + .clk ( clk ), + .reset ( reset ), + .s_write_addr ( tag), + .s_write_req ( tag_req && tag_ready), + .s_write_data ( tag_base_ld_addr), + .s_read_addr ( ldmem_tag), + .s_read_req ( 1'b1), + .s_read_data ( mws_ld_base_addr) + ); + + // wire [ 31 : 0 ] tag0_ld_addr; + // wire [ 31 : 0 ] tag1_ld_addr; + // wire [ 31 : 0 ] tag0_st_addr; + // wire [ 31 : 0 ] tag1_st_addr; + // assign tag0_ld_addr = tag_ld_addr[0]; + // assign tag1_ld_addr = tag_ld_addr[1]; +//============================================================================== + +//============================================================================== +// Tag-based synchronization for double buffering +//============================================================================== + reg raw; + reg [ TAG_W -1 : 0 ] raw_stmem_tag_d; + reg [ TAG_W -1 : 0 ] raw_stmem_tag_q; + wire [ TAG_W -1 : 0 ] raw_stmem_tag; + wire raw_stmem_tag_ready; + wire [ ADDR_WIDTH -1 : 0 ] raw_stmem_st_addr; + + always @(posedge clk) + begin + if (reset) + raw_stmem_tag_q <= 0; + else + raw_stmem_tag_q <= raw_stmem_tag_d; + end + + always @(*) + begin + ldmem_state_d = ldmem_state_q; + raw_stmem_tag_d = raw_stmem_tag_q; + case(ldmem_state_q) + LDMEM_IDLE: begin + if (ldmem_tag_ready) begin + ldmem_state_d = LDMEM_BUSY; + end + end + LDMEM_BUSY: begin + if (mws_ld_done) + ldmem_state_d = LDMEM_WAIT_0; + end + LDMEM_WAIT_0: begin + ldmem_state_d = LDMEM_WAIT_1; + end + LDMEM_WAIT_1: begin + ldmem_state_d = LDMEM_WAIT_2; + end + LDMEM_WAIT_2: begin + ldmem_state_d = LDMEM_WAIT_3; + end + LDMEM_WAIT_3: begin + if (axi_rd_done) + ldmem_state_d = LDMEM_DONE; + end + LDMEM_DONE: begin + ldmem_state_d = LDMEM_IDLE; + end + endcase + end + + always @(posedge clk) + begin + if (reset) + ldmem_state_q <= LDMEM_IDLE; + else + ldmem_state_q <= ldmem_state_d; + end + + wire pu_done = 1'b1; + + always @(*) + begin + stmem_state_d = stmem_state_q; + case(stmem_state_q) + STMEM_IDLE: begin + if (stmem_tag_ready) begin + stmem_state_d = STMEM_DONE; + end + end + STMEM_DONE: begin + stmem_state_d = STMEM_IDLE; + end + endcase + end + + always @(posedge clk) + begin + if (reset) + stmem_state_q <= STMEM_IDLE; + else + stmem_state_q <= stmem_state_d; + end + + wire ldmem_ready; + + assign compute_tag_done = compute_done; + assign compute_ready = compute_tag_ready; + + assign ldmem_tag_done = ldmem_state_q == LDMEM_DONE; + assign ldmem_ready = ldmem_tag_ready; + // assign ldmem_tag_done = mws_ld_done; + + assign stmem_tag_done = stmem_state_q == STMEM_DONE; + + tag_sync #( + .NUM_TAGS ( NUM_TAGS ) + ) + mws_tag ( + .clk ( clk ), + .reset ( reset ), + .block_done ( block_done ), + .tag_req ( tag_req ), + .tag_reuse ( tag_reuse ), + .tag_bias_prev_sw ( tag_bias_prev_sw ), + .tag_ddr_pe_sw ( tag_ddr_pe_sw ), //input + .tag_ready ( tag_ready ), + .tag ( tag ), + .tag_done ( tag_done ), + .raw_stmem_tag ( raw_stmem_tag_q ), + .raw_stmem_tag_ready ( raw_stmem_tag_ready ), + .compute_tag_done ( compute_tag_done ), + .compute_tag_ready ( compute_tag_ready ), + .compute_bias_prev_sw ( compute_bias_prev_sw ), + .compute_tag ( compute_tag ), + .ldmem_tag_done ( ldmem_tag_done ), + .ldmem_tag_ready ( ldmem_tag_ready ), + .ldmem_tag ( ldmem_tag ), + .stmem_ddr_pe_sw ( stmem_ddr_pe_sw ), + .stmem_tag_done ( stmem_tag_done ), + .stmem_tag_ready ( stmem_tag_ready ), + .stmem_tag ( stmem_tag ) + ); +//============================================================================== + + +//============================================================================== +// AXI4 Memory Mapped interface +//============================================================================== + assign mem_write_ready = 1'b1; + assign mem_read_ready = 1'b1; + assign axi_rd_req_id = 0; + assign mem_read_data = 0; + axi_master #( + .TX_SIZE_WIDTH ( MEM_REQ_W ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_BURST_WIDTH ( AXI_BURST_WIDTH ) + ) u_axi_mm_master ( + .clk ( clk ), + .reset ( reset ), + .m_axi_awaddr ( mws_awaddr ), + .m_axi_awlen ( mws_awlen ), + .m_axi_awsize ( mws_awsize ), + .m_axi_awburst ( mws_awburst ), + .m_axi_awvalid ( mws_awvalid ), + .m_axi_awready ( mws_awready ), + .m_axi_wdata ( mws_wdata ), + .m_axi_wstrb ( mws_wstrb ), + .m_axi_wlast ( mws_wlast ), + .m_axi_wvalid ( mws_wvalid ), + .m_axi_wready ( mws_wready ), + .m_axi_bresp ( mws_bresp ), + .m_axi_bvalid ( mws_bvalid ), + .m_axi_bready ( mws_bready ), + .m_axi_araddr ( mws_araddr ), + .m_axi_arid ( mws_arid ), + .m_axi_arlen ( mws_arlen ), + .m_axi_arsize ( mws_arsize ), + .m_axi_arburst ( mws_arburst ), + .m_axi_arvalid ( mws_arvalid ), + .m_axi_arready ( mws_arready ), + .m_axi_rdata ( mws_rdata ), + .m_axi_rid ( mws_rid ), + .m_axi_rresp ( mws_rresp ), + .m_axi_rlast ( mws_rlast ), + .m_axi_rvalid ( mws_rvalid ), + .m_axi_rready ( mws_rready ), + // Buffer + .mem_write_req ( mem_write_req ), + .mem_write_id ( mem_write_id ), + .mem_write_data ( mem_write_data ), + .mem_write_ready ( mem_write_ready ), + .mem_read_data ( mem_read_data ), + .mem_read_req ( mem_read_req ), + .mem_read_ready ( mem_read_ready ), + // AXI RD Req + .rd_req ( axi_rd_req ), + .rd_req_id ( axi_rd_req_id ), + .rd_done ( axi_rd_done ), + .rd_ready ( axi_rd_ready ), + .rd_req_size ( axi_rd_req_size ), + .rd_addr ( axi_rd_addr ), + // AXI WR Req + .wr_req ( axi_wr_req ), + .wr_req_id ( axi_wr_req_id ), + .wr_ready ( axi_wr_ready ), + .wr_req_size ( axi_wr_req_size ), + .wr_addr ( axi_wr_addr ), + .wr_done ( axi_wr_done ) + ); +//============================================================================== + +//============================================================================== +// Dual-port RAM +//============================================================================== + always @(posedge clk) + begin + if (reset) + mem_write_addr <= 0; + else begin + if (mem_write_req) + mem_write_addr <= mem_write_addr + 1'b1; + else if (ldmem_state_q == LDMEM_DONE) + mem_write_addr <= 0; + end + end + + wire [ TAG_MEM_ADDR_W -1 : 0 ] tag_mem_write_addr; + wire [ TAG_BUF_ADDR_W -1 : 0 ] tag_buf_read_addr; + + assign tag_mem_write_addr = {ldmem_tag, mem_write_addr}; + + genvar i; + generate + if (MEM_ID == 1 || MEM_ID == 3) + begin: OBUF_TAG_DELAY + for (i=0; i CL_wrapper AXI4 interface + // Slave Interface Write Address + input wire [ INST_ADDR_WIDTH -1 : 0 ] pci_cl_data_awaddr, + input wire [ INST_BURST_WIDTH -1 : 0 ] pci_cl_data_awlen, + input wire [ 3 -1 : 0 ] pci_cl_data_awsize, + input wire [ 2 -1 : 0 ] pci_cl_data_awburst, + input wire pci_cl_data_awvalid, + output wire pci_cl_data_awready, + // Slave Interface Write Data + input wire [ INST_DATA_WIDTH -1 : 0 ] pci_cl_data_wdata, + input wire [ INST_WSTRB_WIDTH -1 : 0 ] pci_cl_data_wstrb, + input wire pci_cl_data_wlast, + input wire pci_cl_data_wvalid, + output wire pci_cl_data_wready, + // Slave Interface Write Response + output wire [ 2 -1 : 0 ] pci_cl_data_bresp, + output wire pci_cl_data_bvalid, + input wire pci_cl_data_bready, + // Slave Interface Read Address + input wire [ INST_ADDR_WIDTH -1 : 0 ] pci_cl_data_araddr, + input wire [ INST_BURST_WIDTH -1 : 0 ] pci_cl_data_arlen, + input wire [ 3 -1 : 0 ] pci_cl_data_arsize, + input wire [ 2 -1 : 0 ] pci_cl_data_arburst, + input wire pci_cl_data_arvalid, + output wire pci_cl_data_arready, + // Slave Interface Read Data + output wire [ INST_DATA_WIDTH -1 : 0 ] pci_cl_data_rdata, + output wire [ 2 -1 : 0 ] pci_cl_data_rresp, + output wire pci_cl_data_rlast, + output wire pci_cl_data_rvalid, + input wire pci_cl_data_rready +); + +//============================================================= +// Localparams +//============================================================= + // Width of state + localparam integer STATE_W = 3; + // States + localparam integer IMEM_IDLE = 0; + localparam integer IMEM_WR_ADDR = 1; + localparam integer IMEM_WR_DATA = 2; + localparam integer IMEM_RD_ADDR = 3; + localparam integer IMEM_RD_REQ = 4; + localparam integer IMEM_RD_DATA = 5; + // RD count + localparam R_COUNT_W = INST_BURST_WIDTH + 1; + // Bytes per word + localparam BYTES_PER_WORD = DATA_WIDTH / 8; + localparam BYTE_ADDR_W = $clog2(BYTES_PER_WORD); +//============================================================= + +//============================================================= +// Wires/Regs +//============================================================= + // Host <-> imem + wire s_req_a; + wire s_wr_en_a; + wire [ DATA_WIDTH -1 : 0 ] s_read_data_a; + wire [ ADDR_WIDTH -1 : 0 ] s_read_addr_a; + wire [ DATA_WIDTH -1 : 0 ] s_write_data_a; + wire [ ADDR_WIDTH -1 : 0 ] s_write_addr_a; + // FSM for writes to instruction memory (imem) + reg [ STATE_W -1 : 0 ] imem_state_q; + reg [ STATE_W -1 : 0 ] imem_state_d; + // writes address for instruction memory (imem) + reg [ INST_ADDR_WIDTH -1 : 0 ] w_addr_d; + reg [ INST_ADDR_WIDTH -1 : 0 ] w_addr_q; + + // read address for instruction memory (imem) + reg [ INST_ADDR_WIDTH -1 : 0 ] r_addr_d; + reg [ INST_ADDR_WIDTH -1 : 0 ] r_addr_q; + // read counter + reg [ R_COUNT_W -1 : 0 ] r_count_d; + reg [ R_COUNT_W -1 : 0 ] r_count_q; + reg [ R_COUNT_W -1 : 0 ] r_count_max_d; + reg [ R_COUNT_W -1 : 0 ] r_count_max_q; + + reg [ DATA_WIDTH -1 : 0 ] _s_read_data_a; + reg [ DATA_WIDTH -1 : 0 ] _s_read_data_b; +//============================================================= + +//============================================================= +// Assigns +//============================================================= + //assign s_read_data_a = _s_read_data_a; + //assign s_read_data_b = _s_read_data_b; + + assign pci_cl_data_awready = imem_state_q == IMEM_WR_ADDR; + assign pci_cl_data_wready = imem_state_q == IMEM_WR_DATA; + + assign pci_cl_data_bvalid = imem_state_q == IMEM_WR_DATA && pci_cl_data_wlast; + assign pci_cl_data_bresp = 0; + + assign pci_cl_data_arready = imem_state_q == IMEM_RD_ADDR; + assign pci_cl_data_rvalid = imem_state_q == IMEM_RD_DATA; + assign pci_cl_data_rlast = imem_state_q == IMEM_RD_DATA && pci_cl_data_rready && r_count_q == r_count_max_q; + + + assign s_write_addr_a = w_addr_q[INST_ADDR_WIDTH-1:BYTE_ADDR_W]; + assign s_write_data_a = pci_cl_data_wdata; + + assign s_read_addr_a = r_addr_q[INST_ADDR_WIDTH-1:BYTE_ADDR_W]; + assign s_req_a = ((imem_state_q == IMEM_RD_REQ || + (imem_state_q == IMEM_RD_DATA && pci_cl_data_rready)) + || (imem_state_q == IMEM_WR_DATA && pci_cl_data_wvalid)); + assign s_wr_en_a = imem_state_q == IMEM_WR_DATA; + + assign pci_cl_data_rdata = s_read_data_a; + assign pci_cl_data_rresp = 2'b0; +//============================================================= + +//============================================================= +// FSM +//============================================================= + always @(*) + begin: READ_FSM + imem_state_d = imem_state_q; + r_addr_d = r_addr_q; + r_count_max_d = r_count_max_q; + r_count_d = r_count_q; + w_addr_d = w_addr_q; + case(imem_state_q) + IMEM_IDLE: begin + if (pci_cl_data_awvalid) + begin + imem_state_d = IMEM_WR_ADDR; + end else if (pci_cl_data_arvalid) + begin + imem_state_d = IMEM_RD_ADDR; + end + end + IMEM_WR_ADDR: begin + if (pci_cl_data_awvalid) begin + w_addr_d = pci_cl_data_awaddr; + imem_state_d = IMEM_WR_DATA; + end + else + imem_state_d = IMEM_IDLE; + end + IMEM_WR_DATA: begin + if (pci_cl_data_wlast) + imem_state_d = IMEM_IDLE; + if (pci_cl_data_wvalid) + w_addr_d = w_addr_d + BYTES_PER_WORD; + end + IMEM_RD_ADDR: begin + if (pci_cl_data_arvalid) begin + r_addr_d = pci_cl_data_araddr; + r_count_max_d = pci_cl_data_arlen; + r_count_d = 0; + imem_state_d = IMEM_RD_REQ; + end + else + imem_state_d = IMEM_IDLE; + end + IMEM_RD_REQ: begin + r_addr_d = r_addr_d + BYTES_PER_WORD; + imem_state_d = IMEM_RD_DATA; + end + IMEM_RD_DATA: begin + if (pci_cl_data_rlast) + imem_state_d = IMEM_IDLE; + if (pci_cl_data_rvalid && pci_cl_data_rready) begin + r_addr_d = r_addr_d + BYTES_PER_WORD; + r_count_d = r_count_d + 1'b1; + end + end + endcase + end + + always @(posedge clk) + begin + if (reset) + imem_state_q <= IMEM_IDLE; + else + imem_state_q <= imem_state_d; + end + + always @(posedge clk) + begin + if (reset) + w_addr_q <= 0; + else + w_addr_q <= w_addr_d; + end + + always @(posedge clk) + begin + if (reset) + r_addr_q <= 0; + else + r_addr_q <= r_addr_d; + end + + always @(posedge clk) + begin + if (reset) + r_count_q <= 0; + else + r_count_q <= r_count_d; + end + + always @(posedge clk) + begin + if (reset) + r_count_max_q <= 0; + else + r_count_max_q <= r_count_max_d; + end +//============================================================= + +//============================================================= +// Dual port ram +//============================================================= +// reg [ DATA_WIDTH -1 : 0 ] mem [ 0 : 1< compute handshakes + output wire tag_flush, + output wire tag_req, + output wire ibuf_tag_reuse, + output wire obuf_tag_reuse, + output wire wbuf_tag_reuse, + output wire bias_tag_reuse, + input wire tag_ready, + input wire ibuf_tag_done, + input wire wbuf_tag_done, + input wire obuf_tag_done, + input wire bias_tag_done, + + input wire compute_done, + input wire pu_compute_done, + input wire pu_write_done, + input wire pu_compute_start, + input wire [ 3 -1 : 0 ] pu_ctrl_state, + input wire [ 4 -1 : 0 ] stmem_state, + input wire [ TAG_W -1 : 0 ] stmem_tag, + input wire stmem_ddr_pe_sw, + input wire ld_obuf_req, + input wire ld_obuf_ready, + + // Load/Store addresses + // Bias load address + output wire [ BBUF_ADDR_WIDTH -1 : 0 ] bias_ld_addr, + output wire bias_ld_addr_v, + // IBUF load address + output wire [ IBUF_ADDR_WIDTH -1 : 0 ] ibuf_ld_addr, + output wire ibuf_ld_addr_v, + // WBUF load address + output wire [ WBUF_ADDR_WIDTH -1 : 0 ] wbuf_ld_addr, + output wire wbuf_ld_addr_v, + // OBUF load/store address + output wire [ OBUF_ADDR_WIDTH -1 : 0 ] obuf_ld_addr, + output wire obuf_ld_addr_v, + output wire [ OBUF_ADDR_WIDTH -1 : 0 ] obuf_st_addr, + output wire obuf_st_addr_v, + + // Load bias or obuf + output wire tag_bias_prev_sw, + output wire tag_ddr_pe_sw, + + // PCIe -> CL_wrapper AXI4-Lite interface + // Slave Write address + input wire pci_cl_ctrl_awvalid, + input wire [ CTRL_ADDR_WIDTH -1 : 0 ] pci_cl_ctrl_awaddr, + output wire pci_cl_ctrl_awready, + // Slave Write data + input wire pci_cl_ctrl_wvalid, + input wire [ CTRL_DATA_WIDTH -1 : 0 ] pci_cl_ctrl_wdata, + input wire [ CTRL_WSTRB_WIDTH -1 : 0 ] pci_cl_ctrl_wstrb, + output wire pci_cl_ctrl_wready, + // Slave Write response + output wire pci_cl_ctrl_bvalid, + output wire [ 2 -1 : 0 ] pci_cl_ctrl_bresp, + input wire pci_cl_ctrl_bready, + // Slave Read address + input wire pci_cl_ctrl_arvalid, + input wire [ CTRL_ADDR_WIDTH -1 : 0 ] pci_cl_ctrl_araddr, + output wire pci_cl_ctrl_arready, + // Slave Read data/response + output wire pci_cl_ctrl_rvalid, + output wire [ CTRL_DATA_WIDTH -1 : 0 ] pci_cl_ctrl_rdata, + output wire [ 2 -1 : 0 ] pci_cl_ctrl_rresp, + input wire pci_cl_ctrl_rready, + + // PCIe -> CL_wrapper AXI4 interface + // Slave Interface Write Address + input wire [ INST_ADDR_WIDTH -1 : 0 ] pci_cl_data_awaddr, + input wire [ INST_BURST_WIDTH -1 : 0 ] pci_cl_data_awlen, + input wire [ 3 -1 : 0 ] pci_cl_data_awsize, + input wire [ 2 -1 : 0 ] pci_cl_data_awburst, + input wire pci_cl_data_awvalid, + output wire pci_cl_data_awready, + // Slave Interface Write Data + input wire [ INST_DATA_WIDTH -1 : 0 ] pci_cl_data_wdata, + input wire [ INST_WSTRB_WIDTH -1 : 0 ] pci_cl_data_wstrb, + input wire pci_cl_data_wlast, + input wire pci_cl_data_wvalid, + output wire pci_cl_data_wready, + // Slave Interface Write Response + output wire [ 2 -1 : 0 ] pci_cl_data_bresp, + output wire pci_cl_data_bvalid, + input wire pci_cl_data_bready, + // Slave Interface Read Address + input wire [ INST_ADDR_WIDTH -1 : 0 ] pci_cl_data_araddr, + input wire [ INST_BURST_WIDTH -1 : 0 ] pci_cl_data_arlen, + input wire [ 3 -1 : 0 ] pci_cl_data_arsize, + input wire [ 2 -1 : 0 ] pci_cl_data_arburst, + input wire pci_cl_data_arvalid, + output wire pci_cl_data_arready, + // Slave Interface Read Data + output wire [ INST_DATA_WIDTH -1 : 0 ] pci_cl_data_rdata, + output wire [ 2 -1 : 0 ] pci_cl_data_rresp, + output wire pci_cl_data_rlast, + output wire pci_cl_data_rvalid, + input wire pci_cl_data_rready, + + input wire ibuf_compute_ready, + input wire wbuf_compute_ready, + input wire obuf_compute_ready, + input wire bias_compute_ready, + + // Programming interface + // Loop iterations + output wire [ LOOP_ITER_W -1 : 0 ] cfg_loop_iter, + output wire [ LOOP_ID_W -1 : 0 ] cfg_loop_iter_loop_id, + output wire cfg_loop_iter_v, + // Loop stride + output wire [ ADDR_STRIDE_W -1 : 0 ] cfg_loop_stride, + output wire cfg_loop_stride_v, + output wire [ BUF_TYPE_W -1 : 0 ] cfg_loop_stride_id, + output wire [ 2 -1 : 0 ] cfg_loop_stride_type, + output wire [ LOOP_ID_W -1 : 0 ] cfg_loop_stride_loop_id, + // Memory request + output wire [ MEM_REQ_W -1 : 0 ] cfg_mem_req_size, + output wire cfg_mem_req_v, + output wire [ 2 -1 : 0 ] cfg_mem_req_type, + output wire [ BUF_TYPE_W -1 : 0 ] cfg_mem_req_id, + output wire [ LOOP_ID_W -1 : 0 ] cfg_mem_req_loop_id, + // Buffer request + output wire [ MEM_REQ_W -1 : 0 ] cfg_buf_req_size, + output wire cfg_buf_req_v, + output wire cfg_buf_req_type, + output wire [ BUF_TYPE_W -1 : 0 ] cfg_buf_req_loop_id, + + output wire cfg_pu_inst_v, + output wire [ INST_DATA_WIDTH -1 : 0 ] cfg_pu_inst, + output wire pu_block_start, + + // Snoop CL DDR0 + // AR channel + input wire [ CTRL_ADDR_WIDTH -1 : 0 ] snoop_cl_ddr0_araddr, + input wire snoop_cl_ddr0_arvalid, + input wire snoop_cl_ddr0_arready, + input wire [ AXI_BURST_WIDTH -1 : 0 ] snoop_cl_ddr0_arlen, + // R channel + input wire snoop_cl_ddr0_rvalid, + input wire snoop_cl_ddr0_rready, + + // Snoop CL DDR1 + // AW channel + input wire [ CTRL_ADDR_WIDTH -1 : 0 ] snoop_cl_ddr1_awaddr, + input wire snoop_cl_ddr1_awvalid, + input wire snoop_cl_ddr1_awready, + input wire [ AXI_BURST_WIDTH -1 : 0 ] snoop_cl_ddr1_awlen, + // AR channel + input wire [ CTRL_ADDR_WIDTH -1 : 0 ] snoop_cl_ddr1_araddr, + input wire snoop_cl_ddr1_arvalid, + input wire snoop_cl_ddr1_arready, + input wire [ AXI_BURST_WIDTH -1 : 0 ] snoop_cl_ddr1_arlen, + // W channel + input wire snoop_cl_ddr1_wvalid, + input wire snoop_cl_ddr1_wready, + // R channel + input wire snoop_cl_ddr1_rvalid, + input wire snoop_cl_ddr1_rready, + + // Snoop CL DDR2 + // AR channel + input wire [ CTRL_ADDR_WIDTH -1 : 0 ] snoop_cl_ddr2_araddr, + input wire snoop_cl_ddr2_arvalid, + input wire snoop_cl_ddr2_arready, + input wire [ AXI_BURST_WIDTH -1 : 0 ] snoop_cl_ddr2_arlen, + // R channel + input wire snoop_cl_ddr2_rvalid, + input wire snoop_cl_ddr2_rready, + + // Snoop CL DDR3 + // AR channel + input wire [ CTRL_ADDR_WIDTH -1 : 0 ] snoop_cl_ddr3_araddr, + input wire snoop_cl_ddr3_arvalid, + input wire snoop_cl_ddr3_arready, + input wire [ AXI_BURST_WIDTH -1 : 0 ] snoop_cl_ddr3_arlen, + // R channel + input wire snoop_cl_ddr3_rvalid, + input wire snoop_cl_ddr3_rready, + + // Snoop CL DDR4 + // AW channel + input wire [ CTRL_ADDR_WIDTH -1 : 0 ] snoop_cl_ddr4_awaddr, + input wire snoop_cl_ddr4_awvalid, + input wire snoop_cl_ddr4_awready, + input wire [ AXI_BURST_WIDTH -1 : 0 ] snoop_cl_ddr4_awlen, + // AR channel + input wire [ CTRL_ADDR_WIDTH -1 : 0 ] snoop_cl_ddr4_araddr, + input wire snoop_cl_ddr4_arvalid, + input wire snoop_cl_ddr4_arready, + input wire [ AXI_BURST_WIDTH -1 : 0 ] snoop_cl_ddr4_arlen, + // W channel + input wire snoop_cl_ddr4_wvalid, + input wire snoop_cl_ddr4_wready, + // R channel + input wire snoop_cl_ddr4_rvalid, + input wire snoop_cl_ddr4_rready, + + input wire [ INST_DATA_WIDTH -1 : 0 ] obuf_ld_stream_read_count, + input wire [ INST_DATA_WIDTH -1 : 0 ] obuf_ld_stream_write_count, + input wire [ INST_DATA_WIDTH -1 : 0 ] ddr_st_stream_read_count, + input wire [ INST_DATA_WIDTH -1 : 0 ] ddr_st_stream_write_count, + input wire [ INST_DATA_WIDTH -1 : 0 ] ld0_stream_counts, + input wire [ INST_DATA_WIDTH -1 : 0 ] ld1_stream_counts, + input wire [ INST_DATA_WIDTH -1 : 0 ] axi_wr_fifo_counts + ); + +//============================================================= +// Localparam +//============================================================= + // DnnWeaver2 controller state + localparam integer IDLE = 0; + localparam integer DECODE = 1; + localparam integer BASE_LOOP = 2; + localparam integer MEM_WAIT = 3; + localparam integer PU_WR_WAIT = 4; + localparam integer BLOCK_DONE = 5; + localparam integer DONE = 6; + + localparam integer TM_STATE_WIDTH = 2; + localparam integer TM_IDLE = 0; + localparam integer TM_REQUEST = 1; + localparam integer TM_CHECK = 2; + localparam integer TM_FLUSH = 3; +//============================================================= + +//============================================================= +// Wires/Regs +//============================================================= + wire last_block; + // --------Debug-------- + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_busy_cycles; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_decode_cycles; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_execute_cycles; + + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_block_started; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_block_finished; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_tag_started; + + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_axi_wr_id; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_axi_write_req; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_axi_write_finished; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_axi_read_req; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_axi_read_finished; + + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_cl_ddr0_read_req; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_cl_ddr0_read_finished; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_cl_ddr1_write_req; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_cl_ddr1_write_finished; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_cl_ddr1_read_req; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_cl_ddr1_read_finished; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_cl_ddr2_read_req; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_cl_ddr2_read_finished; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_cl_ddr3_read_req; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_cl_ddr3_read_finished; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_cl_ddr4_write_req; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_cl_ddr4_write_finished; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_cl_ddr4_read_req; + wire [ CTRL_DATA_WIDTH -1 : 0 ] pmon_cl_ddr4_read_finished; + + // --------Debug-------- + + // DnnWeaver2 states + reg [ 3 -1 : 0 ] dnnweaver2_state_d; + reg [ 3 -1 : 0 ] dnnweaver2_state_q; + wire [ 3 -1 : 0 ] dnnweaver2_state; + + // Base addresses + wire [ IBUF_ADDR_WIDTH -1 : 0 ] ibuf_base_addr; + wire [ IBUF_ADDR_WIDTH -1 : 0 ] wbuf_base_addr; + wire [ IBUF_ADDR_WIDTH -1 : 0 ] obuf_base_addr; + wire [ IBUF_ADDR_WIDTH -1 : 0 ] bias_base_addr; + + // Handshake signals for main loop controller + wire base_loop_ctrl_start; + wire base_loop_ctrl_done; + + wire block_done; + wire dnnweaver2_done; + + // Handshake signals for decoder + wire decoder_start; + wire decoder_done; + + // Instruction memory Read Port - Decoder + wire inst_read_req; + wire [ IMEM_ADDR_WIDTH -1 : 0 ] inst_read_addr; + wire [ INST_DATA_WIDTH -1 : 0 ] inst_read_data; + + // Start address for fetching/decoding instruction block + wire [ IMEM_ADDR_WIDTH -1 : 0 ] num_blocks; + + // resetn for axi slave + wire resetn; + + // Slave registers + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg0_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg0_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg1_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg1_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg2_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg2_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg3_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg3_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg4_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg4_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg5_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg5_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg6_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg6_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg7_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg7_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg8_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg8_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg9_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg9_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg10_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg10_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg11_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg11_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg12_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg12_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg13_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg13_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg14_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg14_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg15_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg15_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg16_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg16_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg17_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg17_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg18_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg18_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg19_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg19_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg20_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg20_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg21_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg21_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg22_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg22_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg23_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg23_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg24_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg24_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg25_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg25_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg26_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg26_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg27_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg27_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg28_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg28_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg29_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg29_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg30_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg30_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg31_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg31_out; + // Slave registers end + + // Accelerator start logic + wire start_bit_d; + reg start_bit_q; + + // TM State + reg [ TM_STATE_WIDTH -1 : 0 ] tm_state_d; + reg [ TM_STATE_WIDTH -1 : 0 ] tm_state_q; + + reg tm_ibuf_tag_reuse_d; + reg tm_ibuf_tag_reuse_q; + reg tm_obuf_tag_reuse_d; + reg tm_obuf_tag_reuse_q; + reg tm_wbuf_tag_reuse_d; + reg tm_wbuf_tag_reuse_q; + reg tm_bias_tag_reuse_d; + reg tm_bias_tag_reuse_q; + + reg [ ADDR_WIDTH -1 : 0 ] tm_ibuf_tag_addr_d; + reg [ ADDR_WIDTH -1 : 0 ] tm_ibuf_tag_addr_q; + reg [ ADDR_WIDTH -1 : 0 ] tm_obuf_tag_addr_d; + reg [ ADDR_WIDTH -1 : 0 ] tm_obuf_tag_addr_q; + reg [ ADDR_WIDTH -1 : 0 ] tm_wbuf_tag_addr_d; + reg [ ADDR_WIDTH -1 : 0 ] tm_wbuf_tag_addr_q; + reg [ ADDR_WIDTH -1 : 0 ] tm_bias_tag_addr_d; + reg [ ADDR_WIDTH -1 : 0 ] tm_bias_tag_addr_q; + + wire base_ctrl_tag_req; + wire base_ctrl_tag_ready; + + assign tag_req = tm_state_q == TM_REQUEST; + + always @(posedge clk) + begin + if(reset) + tm_state_q <= TM_IDLE; + else + tm_state_q <= tm_state_d; + end + + always @(posedge clk) + begin + if(reset) begin + tm_ibuf_tag_reuse_q <= 1'b0; + tm_obuf_tag_reuse_q <= 1'b0; + tm_wbuf_tag_reuse_q <= 1'b0; + tm_bias_tag_reuse_q <= 1'b0; + tm_ibuf_tag_addr_q <= 0; + tm_obuf_tag_addr_q <= 0; + tm_wbuf_tag_addr_q <= 0; + tm_bias_tag_addr_q <= 0; + end else begin + tm_ibuf_tag_reuse_q <= tm_ibuf_tag_reuse_d; + tm_obuf_tag_reuse_q <= tm_obuf_tag_reuse_d; + tm_wbuf_tag_reuse_q <= tm_wbuf_tag_reuse_d; + tm_bias_tag_reuse_q <= tm_bias_tag_reuse_d; + tm_ibuf_tag_addr_q <= tm_ibuf_tag_addr_d; + tm_obuf_tag_addr_q <= tm_obuf_tag_addr_d; + tm_wbuf_tag_addr_q <= tm_wbuf_tag_addr_d; + tm_bias_tag_addr_q <= tm_bias_tag_addr_d; + end + end + + always @(*) + begin + + tm_state_d = tm_state_q; + + tm_ibuf_tag_reuse_d = 1'b0; + tm_obuf_tag_reuse_d = 1'b0; + tm_wbuf_tag_reuse_d = 1'b0; + tm_bias_tag_reuse_d = 1'b0; + + tm_ibuf_tag_addr_d = tm_ibuf_tag_addr_q; + tm_obuf_tag_addr_d = tm_obuf_tag_addr_q; + tm_wbuf_tag_addr_d = tm_wbuf_tag_addr_q; + tm_bias_tag_addr_d = tm_bias_tag_addr_q; + + case(tm_state_q) + TM_IDLE: begin + if (base_ctrl_tag_req && tag_ready) + tm_state_d = TM_REQUEST; + end + TM_REQUEST: begin + if (tag_ready) begin + tm_state_d = TM_CHECK; + tm_ibuf_tag_addr_d = ibuf_ld_addr; + tm_obuf_tag_addr_d = obuf_ld_addr; + tm_wbuf_tag_addr_d = wbuf_ld_addr; + tm_bias_tag_addr_d = bias_ld_addr; + end + end + TM_CHECK: begin + if (base_ctrl_tag_req && tag_ready) begin + tm_state_d = TM_REQUEST; + tm_ibuf_tag_reuse_d = tm_ibuf_tag_addr_q == ibuf_ld_addr; + tm_obuf_tag_reuse_d = tm_obuf_tag_addr_q == obuf_ld_addr; + tm_wbuf_tag_reuse_d = tm_wbuf_tag_addr_q == wbuf_ld_addr; + tm_bias_tag_reuse_d = tm_bias_tag_addr_q == bias_ld_addr; + end + else if (dnnweaver2_state_q == MEM_WAIT) + begin + tm_state_d = TM_FLUSH; + end + end + TM_FLUSH: begin + tm_state_d = TM_IDLE; + end + endcase + end + + assign tag_flush = tm_state_q == TM_FLUSH; + + assign ibuf_tag_reuse = tm_ibuf_tag_reuse_q; + assign obuf_tag_reuse = tm_obuf_tag_reuse_q; + assign wbuf_tag_reuse = tm_wbuf_tag_reuse_q; + assign bias_tag_reuse = tm_bias_tag_reuse_q; + + assign base_ctrl_tag_ready = tag_ready && tm_state_q == TM_REQUEST; +//============================================================= + +//============================================================= +// Accelerator Start logic +//============================================================= + always @(posedge clk) + begin + if (reset) + start_bit_q <= 1'b0; + else + start_bit_q <= start_bit_d; + end +//============================================================= + +//============================================================= +// FSM +//============================================================= + always @(posedge clk) + begin + if (reset) begin + dnnweaver2_state_q <= IDLE; + end + else begin + dnnweaver2_state_q <= dnnweaver2_state_d; + end + end + + always @(*) + begin + dnnweaver2_state_d = dnnweaver2_state_q; + case(dnnweaver2_state_q) + IDLE: begin + if (decoder_start) begin + dnnweaver2_state_d = DECODE; + end + end + DECODE: begin + if (base_loop_ctrl_start) + dnnweaver2_state_d = BASE_LOOP; + end + BASE_LOOP: begin + if (base_loop_ctrl_done) + dnnweaver2_state_d = MEM_WAIT; + end + MEM_WAIT: begin + if (ibuf_tag_done && wbuf_tag_done && obuf_tag_done && bias_tag_done) + dnnweaver2_state_d = PU_WR_WAIT; + end + PU_WR_WAIT: begin + if (pu_write_done) begin + dnnweaver2_state_d = BLOCK_DONE; + end + end + BLOCK_DONE: begin + if (~last_block) + dnnweaver2_state_d = DECODE; + else + dnnweaver2_state_d = DONE; + end + DONE: begin + dnnweaver2_state_d = IDLE; + end + endcase + end + assign block_done = dnnweaver2_state == BLOCK_DONE; + assign dnnweaver2_done = dnnweaver2_state == DONE; +//============================================================= + +//============================================================= +// Debug +//============================================================= + reg [ CTRL_DATA_WIDTH -1 : 0 ] tag_req_count; + reg [ CTRL_DATA_WIDTH -1 : 0 ] compute_done_count; + reg [ CTRL_DATA_WIDTH -1 : 0 ] pu_compute_done_count; + reg [ CTRL_DATA_WIDTH -1 : 0 ] pu_compute_start_count; + always @(posedge clk) + begin + if (reset) + tag_req_count <= 0; + else if (tm_state_q == TM_REQUEST) + tag_req_count <= tag_req_count + 1'b1; + end + + always @(posedge clk) + begin + if (reset) + compute_done_count <= 0; + else if (compute_done) + compute_done_count <= compute_done_count + 1'b1; + end + + always @(posedge clk) + begin + if (reset) + pu_compute_done_count <= 0; + else if (pu_compute_done) + pu_compute_done_count <= pu_compute_done_count + 1'b1; + end + + always @(posedge clk) + begin + if (reset) + pu_compute_start_count <= 0; + else if (pu_compute_start) + pu_compute_start_count <= pu_compute_start_count + 1'b1; + end +//============================================================= + +//============================================================= +// Assigns +//============================================================= + assign dnnweaver2_state = dnnweaver2_state_q; + + assign resetn = ~reset; + + assign num_blocks = slv_reg1_out; + + assign start_bit_d = slv_reg0_out[0]; + assign decoder_start = (start_bit_q ^ start_bit_d) && dnnweaver2_state_q == IDLE; + + assign slv_reg0_in = slv_reg0_out; // Used as start trigger + assign slv_reg1_in = slv_reg1_out; // Used as start address + + assign slv_reg2_in = dnnweaver2_state; + assign slv_reg3_in = tag_req_count; + assign slv_reg4_in = compute_done_count; + assign slv_reg5_in = pu_compute_done_count; + assign slv_reg6_in = pu_compute_start_count; + + // assign slv_reg3_in = pmon_decode_cycles; + // assign slv_reg4_in = pmon_execute_cycles; + // assign slv_reg5_in = pmon_busy_cycles; + + assign slv_reg7_in = {stmem_state, 14'b0, stmem_ddr_pe_sw, stmem_tag}; + + assign slv_reg8_in = pmon_axi_write_req; + assign slv_reg9_in = pmon_axi_write_finished; + assign slv_reg10_in = pmon_axi_read_req; + assign slv_reg11_in = pmon_axi_read_finished; + assign slv_reg12_in = pmon_axi_wr_id; + + assign slv_reg13_in = ld0_stream_counts; + assign slv_reg14_in = ld1_stream_counts; + assign slv_reg15_in = axi_wr_fifo_counts; + + assign slv_reg16_in = pmon_cl_ddr0_read_req; + assign slv_reg17_in = pmon_cl_ddr0_read_finished; + + assign slv_reg18_in = pmon_cl_ddr1_write_req; + assign slv_reg19_in = pmon_cl_ddr1_write_finished; + assign slv_reg20_in = pmon_cl_ddr1_read_req; + assign slv_reg21_in = pmon_cl_ddr1_read_finished; + + assign slv_reg22_in = obuf_ld_stream_read_count; + assign slv_reg23_in = obuf_ld_stream_write_count; + assign slv_reg24_in = ddr_st_stream_read_count; + assign slv_reg25_in = ddr_st_stream_write_count; + + assign slv_reg26_in = pmon_cl_ddr4_write_req; + assign slv_reg27_in = pmon_cl_ddr4_write_finished; + assign slv_reg28_in = pmon_cl_ddr4_read_req; + assign slv_reg29_in = pmon_cl_ddr4_read_finished; + + assign slv_reg30_in = pu_ctrl_state; + + reg [ CTRL_DATA_WIDTH -1 : 0 ] ld_obuf_read_counter; + + always @(posedge clk) + begin + if (reset) + ld_obuf_read_counter <= 0; + else if (ld_obuf_req) + ld_obuf_read_counter <= ld_obuf_read_counter + 1'b1; + end + assign slv_reg31_in = ld_obuf_read_counter; + +//============================================================= + +//============================================================= +// Performance monitor +//============================================================= + performance_monitor #( + .STATS_WIDTH ( CTRL_DATA_WIDTH ) + ) u_perf_mon ( + .clk ( clk ), + .reset ( reset ), + .dnnweaver2_state ( dnnweaver2_state_q ), //input + .tag_req ( tag_req ), //input + .tag_ready ( tag_ready ), //input + + .decoder_start ( decoder_start ), //input + + .ibuf_tag_done ( ibuf_tag_done ), //input + .wbuf_tag_done ( wbuf_tag_done ), //input + .obuf_tag_done ( obuf_tag_done ), //input + .bias_tag_done ( bias_tag_done ), //input + + .pci_cl_data_awvalid ( pci_cl_data_awvalid ), //input + .pci_cl_data_awlen ( pci_cl_data_awlen ), //input + .pci_cl_data_awready ( pci_cl_data_awready ), //input + .pci_cl_data_arvalid ( pci_cl_data_arvalid ), //input + .pci_cl_data_arlen ( pci_cl_data_arlen ), //input + .pci_cl_data_arready ( pci_cl_data_arready ), //input + .pci_cl_data_wvalid ( pci_cl_data_wvalid ), //input + .pci_cl_data_wready ( pci_cl_data_wready ), //input + .pci_cl_data_rvalid ( pci_cl_data_rvalid ), //input + .pci_cl_data_rready ( pci_cl_data_rready ), //input + + .snoop_cl_ddr0_arvalid ( snoop_cl_ddr0_arvalid ), //input + .snoop_cl_ddr0_arready ( snoop_cl_ddr0_arready ), //input + .snoop_cl_ddr0_arlen ( snoop_cl_ddr0_arlen ), //input + .snoop_cl_ddr0_rvalid ( snoop_cl_ddr0_rvalid ), //input + .snoop_cl_ddr0_rready ( snoop_cl_ddr0_rready ), //input + + .snoop_cl_ddr1_awvalid ( snoop_cl_ddr1_awvalid ), //input + .snoop_cl_ddr1_awready ( snoop_cl_ddr1_awready ), //input + .snoop_cl_ddr1_awlen ( snoop_cl_ddr1_awlen ), //input + .snoop_cl_ddr1_arvalid ( snoop_cl_ddr1_arvalid ), //input + .snoop_cl_ddr1_arready ( snoop_cl_ddr1_arready ), //input + .snoop_cl_ddr1_arlen ( snoop_cl_ddr1_arlen ), //input + .snoop_cl_ddr1_wvalid ( snoop_cl_ddr1_wvalid ), //input + .snoop_cl_ddr1_wready ( snoop_cl_ddr1_wready ), //input + .snoop_cl_ddr1_rvalid ( snoop_cl_ddr1_rvalid ), //input + .snoop_cl_ddr1_rready ( snoop_cl_ddr1_rready ), //input + + .snoop_cl_ddr2_arvalid ( snoop_cl_ddr2_arvalid ), //input + .snoop_cl_ddr2_arready ( snoop_cl_ddr2_arready ), //input + .snoop_cl_ddr2_arlen ( snoop_cl_ddr2_arlen ), //input + .snoop_cl_ddr2_rvalid ( snoop_cl_ddr2_rvalid ), //input + .snoop_cl_ddr2_rready ( snoop_cl_ddr2_rready ), //input + + .snoop_cl_ddr3_arvalid ( snoop_cl_ddr3_arvalid ), //input + .snoop_cl_ddr3_arready ( snoop_cl_ddr3_arready ), //input + .snoop_cl_ddr3_arlen ( snoop_cl_ddr3_arlen ), //input + .snoop_cl_ddr3_rvalid ( snoop_cl_ddr3_rvalid ), //input + .snoop_cl_ddr3_rready ( snoop_cl_ddr3_rready ), //input + + .snoop_cl_ddr4_awvalid ( snoop_cl_ddr4_awvalid ), //input + .snoop_cl_ddr4_awready ( snoop_cl_ddr4_awready ), //input + .snoop_cl_ddr4_awlen ( snoop_cl_ddr4_awlen ), //input + .snoop_cl_ddr4_arvalid ( snoop_cl_ddr4_arvalid ), //input + .snoop_cl_ddr4_arready ( snoop_cl_ddr4_arready ), //input + .snoop_cl_ddr4_arlen ( snoop_cl_ddr4_arlen ), //input + .snoop_cl_ddr4_wvalid ( snoop_cl_ddr4_wvalid ), //input + .snoop_cl_ddr4_wready ( snoop_cl_ddr4_wready ), //input + .snoop_cl_ddr4_rvalid ( snoop_cl_ddr4_rvalid ), //input + .snoop_cl_ddr4_rready ( snoop_cl_ddr4_rready ), //input + + .pmon_cl_ddr0_read_req ( pmon_cl_ddr0_read_req ), //output + .pmon_cl_ddr0_read_finished ( pmon_cl_ddr0_read_finished ), //output + .pmon_cl_ddr1_write_req ( pmon_cl_ddr1_write_req ), //output + .pmon_cl_ddr1_write_finished ( pmon_cl_ddr1_write_finished ), //output + .pmon_cl_ddr1_read_req ( pmon_cl_ddr1_read_req ), //output + .pmon_cl_ddr1_read_finished ( pmon_cl_ddr1_read_finished ), //output + .pmon_cl_ddr2_read_req ( pmon_cl_ddr2_read_req ), //output + .pmon_cl_ddr2_read_finished ( pmon_cl_ddr2_read_finished ), //output + .pmon_cl_ddr3_read_req ( pmon_cl_ddr3_read_req ), //output + .pmon_cl_ddr3_read_finished ( pmon_cl_ddr3_read_finished ), //output + .pmon_cl_ddr4_write_req ( pmon_cl_ddr4_write_req ), //output + .pmon_cl_ddr4_write_finished ( pmon_cl_ddr4_write_finished ), //output + .pmon_cl_ddr4_read_req ( pmon_cl_ddr4_read_req ), //output + .pmon_cl_ddr4_read_finished ( pmon_cl_ddr4_read_finished ), //output + + .decode_cycles ( pmon_decode_cycles ), //output + .execute_cycles ( pmon_execute_cycles ), //output + .busy_cycles ( pmon_busy_cycles ), //output + + .tag_started ( pmon_tag_started ), //output + .block_started ( pmon_block_started ), //output + .block_finished ( pmon_block_finished ), //output + + .axi_wr_id ( pmon_axi_wr_id ), //output + .axi_write_req ( pmon_axi_write_req ), //output + .axi_write_finished ( pmon_axi_write_finished ), //output + .axi_read_req ( pmon_axi_read_req ), //output + .axi_read_finished ( pmon_axi_read_finished ) //output + ); +//============================================================= + +//============================================================= +// Instruction Memory +//============================================================= + instruction_memory #( + .DATA_WIDTH ( INST_DATA_WIDTH ), + .ADDR_WIDTH ( IMEM_ADDR_WIDTH ) + ) imem ( + .clk ( clk ), + .reset ( reset ), + .pci_cl_data_awaddr ( pci_cl_data_awaddr ), //input + .pci_cl_data_awlen ( pci_cl_data_awlen ), //input + .pci_cl_data_awsize ( pci_cl_data_awsize ), //input + .pci_cl_data_awburst ( pci_cl_data_awburst ), //input + .pci_cl_data_awvalid ( pci_cl_data_awvalid ), //input + .pci_cl_data_awready ( pci_cl_data_awready ), //output + .pci_cl_data_wdata ( pci_cl_data_wdata ), //input + .pci_cl_data_wstrb ( pci_cl_data_wstrb ), //input + .pci_cl_data_wlast ( pci_cl_data_wlast ), //input + .pci_cl_data_wvalid ( pci_cl_data_wvalid ), //input + .pci_cl_data_wready ( pci_cl_data_wready ), //output + .pci_cl_data_bresp ( pci_cl_data_bresp ), //output + .pci_cl_data_bvalid ( pci_cl_data_bvalid ), //output + .pci_cl_data_bready ( pci_cl_data_bready ), //input + .pci_cl_data_araddr ( pci_cl_data_araddr ), //input + .pci_cl_data_arlen ( pci_cl_data_arlen ), //input + .pci_cl_data_arsize ( pci_cl_data_arsize ), //input + .pci_cl_data_arburst ( pci_cl_data_arburst ), //input + .pci_cl_data_arvalid ( pci_cl_data_arvalid ), //input + .pci_cl_data_arready ( pci_cl_data_arready ), //output + .pci_cl_data_rdata ( pci_cl_data_rdata ), //output + .pci_cl_data_rresp ( pci_cl_data_rresp ), //output + .pci_cl_data_rlast ( pci_cl_data_rlast ), //output + .pci_cl_data_rvalid ( pci_cl_data_rvalid ), //output + .pci_cl_data_rready ( pci_cl_data_rready ), //input + .s_read_addr_b ( inst_read_addr ), //input + .s_read_req_b ( inst_read_req ), //input + .s_read_data_b ( inst_read_data ) //output + ); +//============================================================= + +//============================================================= +// Status/Control AXI4-Lite +//============================================================= + wire [ CTRL_DATA_WIDTH -1 : 0 ] ibuf_rd_addr; + wire ibuf_rd_addr_v; + wire [ CTRL_DATA_WIDTH -1 : 0 ] obuf_wr_addr; + wire obuf_wr_addr_v; + wire [ CTRL_DATA_WIDTH -1 : 0 ] obuf_rd_addr; + wire obuf_rd_addr_v; + wire [ CTRL_DATA_WIDTH -1 : 0 ] wbuf_rd_addr; + wire wbuf_rd_addr_v; + wire [ CTRL_DATA_WIDTH -1 : 0 ] bias_rd_addr; + wire bias_rd_addr_v; + + assign ibuf_rd_addr = snoop_cl_ddr0_araddr; + assign ibuf_rd_addr_v = snoop_cl_ddr0_arvalid && snoop_cl_ddr0_arready; + assign obuf_wr_addr = snoop_cl_ddr1_awaddr; + assign obuf_wr_addr_v = snoop_cl_ddr1_awvalid && snoop_cl_ddr1_awready; + assign obuf_rd_addr = snoop_cl_ddr1_araddr; + assign obuf_rd_addr_v = snoop_cl_ddr1_arvalid && snoop_cl_ddr1_arready; + assign wbuf_rd_addr = snoop_cl_ddr2_araddr; + assign wbuf_rd_addr_v = snoop_cl_ddr2_arvalid && snoop_cl_ddr2_arready; + assign bias_rd_addr = snoop_cl_ddr3_araddr; + assign bias_rd_addr_v = snoop_cl_ddr3_arvalid && snoop_cl_ddr3_arready; + + axi4lite_slave #( + .AXIS_ADDR_WIDTH ( CTRL_ADDR_WIDTH ), + .AXIS_DATA_WIDTH ( CTRL_DATA_WIDTH ) + ) status_ctrl_slv ( + .clk ( clk ), + .resetn ( resetn ), + // Slave registers + .slv_reg0_in ( slv_reg0_in ), + .slv_reg0_out ( slv_reg0_out ), + .slv_reg1_in ( slv_reg1_in ), + .slv_reg1_out ( slv_reg1_out ), + .slv_reg2_in ( slv_reg2_in ), + .slv_reg2_out ( slv_reg2_out ), + .slv_reg3_in ( slv_reg3_in ), + .slv_reg3_out ( slv_reg3_out ), + .slv_reg4_in ( slv_reg4_in ), + .slv_reg4_out ( slv_reg4_out ), + .slv_reg5_in ( slv_reg5_in ), + .slv_reg5_out ( slv_reg5_out ), + .slv_reg6_in ( slv_reg6_in ), + .slv_reg6_out ( slv_reg6_out ), + .slv_reg7_in ( slv_reg7_in ), + .slv_reg7_out ( slv_reg7_out ), + .slv_reg8_in ( slv_reg8_in ), + .slv_reg8_out ( slv_reg8_out ), + .slv_reg9_in ( slv_reg9_in ), + .slv_reg9_out ( slv_reg9_out ), + .slv_reg10_in ( slv_reg10_in ), + .slv_reg10_out ( slv_reg10_out ), + .slv_reg11_in ( slv_reg11_in ), + .slv_reg11_out ( slv_reg11_out ), + .slv_reg12_in ( slv_reg12_in ), + .slv_reg12_out ( slv_reg12_out ), + .slv_reg13_in ( slv_reg13_in ), + .slv_reg13_out ( slv_reg13_out ), + .slv_reg14_in ( slv_reg14_in ), + .slv_reg14_out ( slv_reg14_out ), + .slv_reg15_in ( slv_reg15_in ), + .slv_reg15_out ( slv_reg15_out ), + + .slv_reg16_in ( slv_reg16_in ), + .slv_reg16_out ( slv_reg16_out ), + .slv_reg17_in ( slv_reg17_in ), + .slv_reg17_out ( slv_reg17_out ), + .slv_reg18_in ( slv_reg18_in ), + .slv_reg18_out ( slv_reg18_out ), + .slv_reg19_in ( slv_reg19_in ), + .slv_reg19_out ( slv_reg19_out ), + .slv_reg20_in ( slv_reg20_in ), + .slv_reg20_out ( slv_reg20_out ), + .slv_reg21_in ( slv_reg21_in ), + .slv_reg21_out ( slv_reg21_out ), + .slv_reg22_in ( slv_reg22_in ), + .slv_reg22_out ( slv_reg22_out ), + .slv_reg23_in ( slv_reg23_in ), + .slv_reg23_out ( slv_reg23_out ), + .slv_reg24_in ( slv_reg24_in ), + .slv_reg24_out ( slv_reg24_out ), + .slv_reg25_in ( slv_reg25_in ), + .slv_reg25_out ( slv_reg25_out ), + .slv_reg26_in ( slv_reg26_in ), + .slv_reg26_out ( slv_reg26_out ), + .slv_reg27_in ( slv_reg27_in ), + .slv_reg27_out ( slv_reg27_out ), + .slv_reg28_in ( slv_reg28_in ), + .slv_reg28_out ( slv_reg28_out ), + .slv_reg29_in ( slv_reg29_in ), + .slv_reg29_out ( slv_reg29_out ), + .slv_reg30_in ( slv_reg30_in ), + .slv_reg30_out ( slv_reg30_out ), + .slv_reg31_in ( slv_reg31_in ), + .slv_reg31_out ( slv_reg31_out ), + + .decoder_start ( decoder_start ), + .ibuf_rd_addr ( ibuf_rd_addr ), + .ibuf_rd_addr_v ( ibuf_rd_addr_v ), + .obuf_wr_addr ( obuf_wr_addr ), + .obuf_wr_addr_v ( obuf_wr_addr_v ), + .obuf_rd_addr ( obuf_rd_addr ), + .obuf_rd_addr_v ( obuf_rd_addr_v ), + .wbuf_rd_addr ( wbuf_rd_addr ), + .wbuf_rd_addr_v ( wbuf_rd_addr_v ), + .bias_rd_addr ( bias_rd_addr ), + .bias_rd_addr_v ( bias_rd_addr_v ), + + .s_axi_awaddr ( pci_cl_ctrl_awaddr ), + .s_axi_awvalid ( pci_cl_ctrl_awvalid ), + .s_axi_awready ( pci_cl_ctrl_awready ), + .s_axi_wdata ( pci_cl_ctrl_wdata ), + .s_axi_wstrb ( pci_cl_ctrl_wstrb ), + .s_axi_wvalid ( pci_cl_ctrl_wvalid ), + .s_axi_wready ( pci_cl_ctrl_wready ), + .s_axi_bresp ( pci_cl_ctrl_bresp ), + .s_axi_bvalid ( pci_cl_ctrl_bvalid ), + .s_axi_bready ( pci_cl_ctrl_bready ), + .s_axi_araddr ( pci_cl_ctrl_araddr ), + .s_axi_arvalid ( pci_cl_ctrl_arvalid ), + .s_axi_arready ( pci_cl_ctrl_arready ), + .s_axi_rdata ( pci_cl_ctrl_rdata ), + .s_axi_rresp ( pci_cl_ctrl_rresp ), + .s_axi_rvalid ( pci_cl_ctrl_rvalid ), + .s_axi_rready ( pci_cl_ctrl_rready ) + ); +//============================================================= + +//============================================================= +// Decoder +//============================================================= + decoder #( + .IMEM_ADDR_W ( IMEM_ADDR_WIDTH ) + ) instruction_decoder ( + .clk ( clk ), //input + .reset ( reset ), //input + .imem_read_data ( inst_read_data ), //input + .imem_read_addr ( inst_read_addr ), //output + .imem_read_req ( inst_read_req ), //output + .start ( decoder_start ), //input + .done ( decoder_done ), //output + .loop_ctrl_start ( base_loop_ctrl_start ), //output + .loop_ctrl_done ( base_loop_ctrl_done ), //input + .block_done ( block_done ), //input + .last_block ( last_block ), //output + .cfg_loop_iter_v ( cfg_loop_iter_v ), //output + .cfg_loop_iter ( cfg_loop_iter ), //output + .cfg_loop_iter_loop_id ( cfg_loop_iter_loop_id ), //output + .cfg_loop_stride_v ( cfg_loop_stride_v ), //output + .cfg_loop_stride ( cfg_loop_stride ), //output + .cfg_loop_stride_loop_id ( cfg_loop_stride_loop_id ), //output + .cfg_loop_stride_type ( cfg_loop_stride_type ), //output + .cfg_loop_stride_id ( cfg_loop_stride_id ), //output + .ibuf_base_addr ( ibuf_base_addr ), //output + .wbuf_base_addr ( wbuf_base_addr ), //output + .obuf_base_addr ( obuf_base_addr ), //output + .bias_base_addr ( bias_base_addr ), //output + .cfg_mem_req_v ( cfg_mem_req_v ), //output + .cfg_mem_req_size ( cfg_mem_req_size ), //output + .cfg_mem_req_type ( cfg_mem_req_type ), //output + .cfg_mem_req_id ( cfg_mem_req_id ), //output + .cfg_mem_req_loop_id ( cfg_mem_req_loop_id ), //output + .cfg_buf_req_v ( cfg_buf_req_v ), //output + .cfg_buf_req_size ( cfg_buf_req_size ), //output + .cfg_buf_req_type ( cfg_buf_req_type ), //output + .cfg_buf_req_loop_id ( cfg_buf_req_loop_id ), //output + .cfg_pu_inst ( cfg_pu_inst ), //output + .cfg_pu_inst_v ( cfg_pu_inst_v ), //output + .pu_block_start ( pu_block_start ) //output + ); +//============================================================= + +//============================================================= +// Base address generator +// This module is in charge of the outer loops [16 - 31] +//============================================================= + base_addr_gen #( + .BASE_ID ( 1 ), + .MEM_REQ_W ( MEM_REQ_W ), + .IBUF_ADDR_WIDTH ( IBUF_ADDR_WIDTH ), + .WBUF_ADDR_WIDTH ( WBUF_ADDR_WIDTH ), + .OBUF_ADDR_WIDTH ( OBUF_ADDR_WIDTH ), + .BBUF_ADDR_WIDTH ( BBUF_ADDR_WIDTH ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) base_ctrl ( + .clk ( clk ), //input + .reset ( reset ), //input + + .start ( base_loop_ctrl_start ), //input + .done ( base_loop_ctrl_done ), //output + + .tag_req ( base_ctrl_tag_req ), //output + .tag_ready ( base_ctrl_tag_ready ), //output + + .cfg_loop_iter_v ( cfg_loop_iter_v ), //input + .cfg_loop_iter ( cfg_loop_iter ), //input + .cfg_loop_iter_loop_id ( cfg_loop_iter_loop_id ), //input + + .cfg_loop_stride_v ( cfg_loop_stride_v ), //input + .cfg_loop_stride ( cfg_loop_stride ), //input + .cfg_loop_stride_loop_id ( cfg_loop_stride_loop_id ), //input + .cfg_loop_stride_type ( cfg_loop_stride_type ), //input + .cfg_loop_stride_id ( cfg_loop_stride_id ), //input + + .obuf_base_addr ( obuf_base_addr ), //input + .obuf_ld_addr ( obuf_ld_addr ), //output + .obuf_ld_addr_v ( obuf_ld_addr_v ), //output + .obuf_st_addr ( obuf_st_addr ), //output + .obuf_st_addr_v ( obuf_st_addr_v ), //output + .ibuf_base_addr ( ibuf_base_addr ), //input + .ibuf_ld_addr ( ibuf_ld_addr ), //output + .ibuf_ld_addr_v ( ibuf_ld_addr_v ), //output + .wbuf_base_addr ( wbuf_base_addr ), //input + .wbuf_ld_addr ( wbuf_ld_addr ), //output + .wbuf_ld_addr_v ( wbuf_ld_addr_v ), //output + .bias_base_addr ( bias_base_addr ), //input + .bias_ld_addr ( bias_ld_addr ), //output + .bias_ld_addr_v ( bias_ld_addr_v ), //output + + .bias_prev_sw ( tag_bias_prev_sw ), //output + .ddr_pe_sw ( tag_ddr_pe_sw ) //output + ); +//============================================================= + +//============================================================= +// VCD +//============================================================= + `ifdef COCOTB_TOPLEVEL_controller + initial begin + $dumpfile("controller.vcd"); + $dumpvars(0, controller); + end + `endif +//============================================================= + +endmodule +// +// Loop Controller +// +// (1) RAM to hold loop instructions (max iter count) +// (2) RAM to hold loop states (current iter count) +// (3) FSM that starts when we get the start signal, stops when done +// (4) Stack for the head pointer +// +// Update the loop iterations in controller_fsm when exiting loop +// Update the loop offset in mem-walker-stride when entering loop +// +// Hardik Sharma +// (hsharma@gatech.edu) + +`timescale 1ns/1ps +module controller_fsm #( + parameter integer LOOP_ID_W = 5, + parameter integer LOOP_ITER_W = 16, + parameter integer IMEM_ADDR_W = 5, + // Internal Parameters + parameter integer STATE_W = 3, + parameter integer LOOP_STATE_W = LOOP_ID_W, + parameter integer STACK_DEPTH = (1 << IMEM_ADDR_W) +) ( + input wire clk, + input wire reset, + + // Start and Done handshake signals + input wire start, + output wire done, + input wire stall, + + // Loop instruction valid + input wire cfg_loop_iter_v, + input wire [ LOOP_ITER_W -1 : 0 ] cfg_loop_iter, + input wire [ LOOP_ID_W -1 : 0 ] cfg_loop_iter_loop_id, + + output wire [ LOOP_ID_W -1 : 0 ] loop_index, + output wire loop_index_valid, + output wire loop_last_iter, + output wire loop_init, + output wire loop_enter, + output wire loop_exit +); + + +//============================================================= +// Wires/Regs +//============================================================= + + wire loop_wr_req; + wire [ IMEM_ADDR_W -1 : 0 ] loop_wr_ptr; + wire [ LOOP_ITER_W -1 : 0 ] loop_wr_max_iter; + + reg [ IMEM_ADDR_W -1 : 0 ] max_loop_ptr; + wire [ IMEM_ADDR_W -1 : 0 ] loop_rd_ptr; + + wire loop_rd_v; + wire [ LOOP_ITER_W -1 : 0 ] loop_rd_max; + + wire [ IMEM_ADDR_W -1 : 0 ] iter_wr_ptr; + wire iter_wr_v; + wire [ LOOP_ITER_W -1 : 0 ] iter_wr_data; + + reg [ IMEM_ADDR_W -1 : 0 ] loop_index_q; + reg [ IMEM_ADDR_W -1 : 0 ] loop_index_d; // d -> q + + wire [ IMEM_ADDR_W -1 : 0 ] iter_rd_ptr; + wire iter_rd_v; + wire [ LOOP_ITER_W -1 : 0 ] iter_rd_data; + + reg [ IMEM_ADDR_W -1 : 0 ] stall_rd_ptr; + + wire [ STATE_W -1 : 0 ] state; + reg [ STATE_W -1 : 0 ] state_q; + reg [ STATE_W -1 : 0 ] state_d; + +//============================================================= + +//============================================================= +// Loop Instruction Buffer +//============================================================= + + always @(posedge clk) + begin: MAX_LOOP_PTR + if (loop_wr_req) + max_loop_ptr <= cfg_loop_iter_loop_id; + end + + assign loop_rd_v = iter_rd_v; + assign loop_rd_ptr = iter_rd_ptr; + + // + //This module stores the loop max iterations. + // + assign loop_wr_ptr = cfg_loop_iter_loop_id; + assign loop_wr_req = cfg_loop_iter_v; + assign loop_wr_max_iter = cfg_loop_iter; + ram #( + .ADDR_WIDTH ( IMEM_ADDR_W ), + .DATA_WIDTH ( LOOP_ITER_W ) + ) loop_buf ( + .clk ( clk ), + .reset ( reset ), + .s_write_addr ( loop_wr_ptr ), + .s_write_req ( loop_wr_req ), + .s_write_data ( loop_wr_max_iter ), + .s_read_addr ( loop_rd_ptr ), + .s_read_req ( loop_rd_v ), + .s_read_data ( loop_rd_max ) + ); +//============================================================= + +//============================================================= +// Loop Counters +//============================================================= + // + //This module stores the current loop iterations. + // + + ram #( + .ADDR_WIDTH ( IMEM_ADDR_W ), + .DATA_WIDTH ( LOOP_ITER_W ) + ) iter_buf ( + .clk ( clk ), + .reset ( reset ), + .s_write_addr ( iter_wr_ptr ), + .s_write_req ( iter_wr_v ), + .s_write_data ( iter_wr_data ), + .s_read_addr ( iter_rd_ptr ), + .s_read_req ( iter_rd_v ), + .s_read_data ( iter_rd_data ) + ); +//============================================================= + +//============================================================= +// FSM +//============================================================= + + localparam integer IDLE = 0; + localparam integer INIT_LOOP = 1; + localparam integer ENTER_LOOP = 2; + localparam integer INNER_LOOP = 3; + localparam integer EXIT_LOOP = 4; + + always @(*) + begin + state_d = state_q; + loop_index_d = loop_index_q; + case (state_q) + IDLE: begin + loop_index_d = max_loop_ptr; + if (start) begin + state_d = INIT_LOOP; + end + end + INIT_LOOP: begin + if (max_loop_ptr != 0) + loop_index_d = loop_index_q - 1'b1; + if (loop_index_q == 1 || loop_index_q == 0) + state_d = INNER_LOOP; + end + ENTER_LOOP: begin + loop_index_d = loop_index_q - 1'b1; + if (loop_index_q == 1) + state_d = INNER_LOOP; + end + INNER_LOOP: begin + if (done) + state_d = IDLE; + else if (loop_last_iter && !stall) + begin + if (max_loop_ptr != 0) begin + loop_index_d = loop_index_q + 1'b1; + state_d = EXIT_LOOP; + end + else + state_d = IDLE; + end + end + EXIT_LOOP: begin + if (done) + begin + loop_index_d = 0; + state_d = IDLE; + end + else if (loop_last_iter) + loop_index_d = loop_index_q + 1'b1; + else if (!loop_last_iter) + state_d = ENTER_LOOP; + end + default: begin + state_d = IDLE; + loop_index_d = 0; + end + endcase + end + + always @(posedge clk) + begin + if (reset) + loop_index_q <= 'b0; + else + loop_index_q <= loop_index_d; + end + + assign loop_index = loop_index_q; + + always @(posedge clk) + begin + if (reset) + state_q <= 'b0; + else + state_q <= state_d; + end + + assign state = state_q; + +//============================================================= + +//============================================================= + // Loop Iteration logic: + // + // Set iter counts to zero when initializing the max iters + // Otherwise, increment write pointer and read pointer every + // cycle + // max_loop_ptr keeps track of the last loop + // iter_rd signals correspond to the current iter count + // loop_last_iter whenever the current count == max count +//============================================================= + // assign done = (loop_index == max_loop_ptr) && loop_last_iter; + assign done = (((state == EXIT_LOOP) && (loop_index == max_loop_ptr)) || ((state == INNER_LOOP) && (max_loop_ptr == 0) && (~stall))) && loop_last_iter; + assign iter_rd_v = state != IDLE; + + // The below three assign statements update the loop iterations + assign iter_wr_v = loop_wr_req || state == EXIT_LOOP || (state == INNER_LOOP && !stall); + + assign iter_wr_data = state == IDLE ? 'b0 : + loop_last_iter ? 'b0 : iter_rd_data + 1'b1; + assign iter_wr_ptr = state == IDLE ? cfg_loop_iter_loop_id : loop_index; + + assign loop_last_iter = iter_rd_data == loop_rd_max; + +//============================================================= + + +//============================================================= +// OFFSET generation +//============================================================= + + assign iter_rd_ptr = loop_index; + assign loop_index_valid = state == INNER_LOOP; + + assign loop_enter = state == ENTER_LOOP || state == INIT_LOOP; + assign loop_init = state == INIT_LOOP; + assign loop_exit = state == EXIT_LOOP; + +//============================================================= + +//============================================================= +// VCD +//============================================================= +`ifdef COCOTB_TOPLEVEL_controller_fsm +initial begin + $dumpfile("controller_fsm.vcd"); + $dumpvars(0, controller_fsm); +end +`endif +//============================================================= + +endmodule +// +// OBUF - Output Buffer +// +// Hardik Sharma +// (hsharma@gatech.edu) +`timescale 1ns/1ps +module obuf #( + parameter integer TAG_W = 2, // Log number of banks + parameter integer MEM_DATA_WIDTH = 64, + parameter integer ARRAY_M = 2, + parameter integer DATA_WIDTH = 32, + parameter integer BUF_ADDR_WIDTH = 10, + + parameter integer GROUP_SIZE = MEM_DATA_WIDTH / DATA_WIDTH, + parameter integer GROUP_ID_W = GROUP_SIZE == 1 ? 0 : $clog2(GROUP_SIZE), + parameter integer BUF_ID_W = $clog2(ARRAY_M) - GROUP_ID_W, + + parameter integer MEM_ADDR_WIDTH = BUF_ADDR_WIDTH + BUF_ID_W, + parameter integer BUF_DATA_WIDTH = ARRAY_M * DATA_WIDTH +) +( + input wire clk, + input wire reset, + + input wire mem_read_req, + input wire [ MEM_ADDR_WIDTH -1 : 0 ] mem_read_addr, + output wire [ MEM_DATA_WIDTH -1 : 0 ] mem_read_data, + + input wire mem_write_req, + input wire [ MEM_ADDR_WIDTH -1 : 0 ] mem_write_addr, + input wire [ MEM_DATA_WIDTH -1 : 0 ] mem_write_data, + + input wire buf_read_req, + input wire [ BUF_ADDR_WIDTH -1 : 0 ] buf_read_addr, + output wire [ BUF_DATA_WIDTH -1 : 0 ] buf_read_data, + + input wire buf_write_req, + input wire [ BUF_ADDR_WIDTH -1 : 0 ] buf_write_addr, + input wire [ BUF_DATA_WIDTH -1 : 0 ] buf_write_data + ); + + wire [ DATA_WIDTH*ARRAY_M-1 : 0 ] mem_read_data_raw; + + genvar m; + generate + for (m=0; m 1) +//begin +// localparam integer SEL_LOW_WIDTH = LOG2_N-1; // select at lower level has 1 less width +// localparam integer IN_LOW_WIDTH = IN_WIDTH / 2; // Input at lower level has half width +// localparam integer OUT_LOW_WIDTH = OUT_WIDTH; // Output at lower level has same width +// +// wire [ SEL_LOW_WIDTH -1 : 0 ] sel_low; +// wire [ IN_LOW_WIDTH -1 : 0 ] in_0; +// wire [ IN_LOW_WIDTH -1 : 0 ] in_1; +// wire [ OUT_LOW_WIDTH -1 : 0 ] out_0; +// wire [ OUT_LOW_WIDTH -1 : 0 ] out_1; +// +// assign sel_low = sel[LOG2_N-2: 0]; +// assign in_0 = data_in[0+:IN_LOW_WIDTH]; +// assign in_1 = data_in[IN_LOW_WIDTH+:IN_LOW_WIDTH]; +// +// mux_n_1 #( +// .WIDTH ( WIDTH ), +// .TOP_MODULE ( 0 ), +// .LOG2_N ( SEL_LOW_WIDTH ) +// ) mux_0 ( +// .sel ( sel_low ), +// .data_in ( in_0 ), +// .data_out ( out_0 ) +// ); +// +// mux_n_1 #( +// .WIDTH ( WIDTH ), +// .TOP_MODULE ( 0 ), +// .LOG2_N ( SEL_LOW_WIDTH ) +// ) mux_1 ( +// .sel ( sel_low ), +// .data_in ( in_1 ), +// .data_out ( out_1 ) +// ); +// +// wire sel_curr = sel[LOG2_N-1]; +// localparam IN_CURR_WIDTH = 2 * OUT_WIDTH; +// wire [ IN_CURR_WIDTH -1 : 0 ] in_curr = {out_1, out_0}; +// +// mux_2_1 #( +// .WIDTH ( WIDTH ) +// ) mux_inst_curr ( +// .sel ( sel_curr ), +// .data_in ( in_curr ), +// .data_out ( data_out ) +// ); +//end +//else +//begin + mux_2_1 #( + .WIDTH ( WIDTH ) + ) mux_inst_curr ( + .sel ( sel ), + .data_in ( data_in ), + .data_out ( data_out ) + ); +//end +//endgenerate +//========================================= +// Debugging: COCOTB VCD +//========================================= +`ifdef COCOTB_TOPLEVEL_mux_n_1 +if (TOP_MODULE == 1) +begin + initial begin + $dumpfile("mux_n_1.vcd"); + $dumpvars(0, mux_n_1); + end +end +`endif + +endmodule +// +// Base address generator +// +// Hardik Sharma +// (hsharma@gatech.edu) + +`timescale 1ns/1ps +module base_addr_gen #( + // Internal Parameters + parameter integer BASE_ID = 1, + parameter integer IBUF_MEM_ID = 0, + parameter integer OBUF_MEM_ID = 1, + parameter integer WBUF_MEM_ID = 2, + parameter integer BBUF_MEM_ID = 3, + + parameter integer MEM_REQ_W = 16, + parameter integer IBUF_ADDR_WIDTH = 8, + parameter integer WBUF_ADDR_WIDTH = 8, + parameter integer OBUF_ADDR_WIDTH = 8, + parameter integer BBUF_ADDR_WIDTH = 8, + parameter integer DATA_WIDTH = 32, + parameter integer LOOP_ITER_W = 16, + parameter integer ADDR_STRIDE_W = 16, + parameter integer LOOP_ID_W = 5, + parameter integer BUF_TYPE_W = 2 +) ( + input wire clk, + input wire reset, + + input wire start, + output wire done, + + output wire tag_req, + input wire tag_ready, + + // Programming + input wire cfg_loop_iter_v, + input wire [ LOOP_ITER_W -1 : 0 ] cfg_loop_iter, + input wire [ LOOP_ID_W -1 : 0 ] cfg_loop_iter_loop_id, + + // Programming + input wire cfg_loop_stride_v, + input wire [ ADDR_STRIDE_W -1 : 0 ] cfg_loop_stride, + input wire [ LOOP_ID_W -1 : 0 ] cfg_loop_stride_loop_id, + input wire [ BUF_TYPE_W -1 : 0 ] cfg_loop_stride_id, + input wire [ 2 -1 : 0 ] cfg_loop_stride_type, + + // Address - OBUF LD/ST + input wire [ OBUF_ADDR_WIDTH -1 : 0 ] obuf_base_addr, + output wire [ OBUF_ADDR_WIDTH -1 : 0 ] obuf_ld_addr, + output wire obuf_ld_addr_v, + output wire [ OBUF_ADDR_WIDTH -1 : 0 ] obuf_st_addr, + output wire obuf_st_addr_v, + // Address - IBUF LD + input wire [ IBUF_ADDR_WIDTH -1 : 0 ] ibuf_base_addr, + output wire [ IBUF_ADDR_WIDTH -1 : 0 ] ibuf_ld_addr, + output wire ibuf_ld_addr_v, + // Address - WBUF LD + input wire [ WBUF_ADDR_WIDTH -1 : 0 ] wbuf_base_addr, + output wire [ WBUF_ADDR_WIDTH -1 : 0 ] wbuf_ld_addr, + output wire wbuf_ld_addr_v, + // Address - BIAS LD + input wire [ BBUF_ADDR_WIDTH -1 : 0 ] bias_base_addr, + output wire [ BBUF_ADDR_WIDTH -1 : 0 ] bias_ld_addr, + output wire bias_ld_addr_v, + + output wire bias_prev_sw, + output wire ddr_pe_sw +); + +//============================================================================== +// Wires/Regs +//============================================================================== + // Programming - Base loop + wire cfg_base_loop_iter_v; + wire [ LOOP_ITER_W -1 : 0 ] cfg_base_loop_iter; + reg [ LOOP_ID_W -1 : 0 ] cfg_base_loop_iter_loop_id; + + // Base loop + wire base_loop_start; + wire base_loop_done; + wire base_loop_stall; + wire base_loop_init; + wire base_loop_enter; + wire base_loop_exit; + wire base_loop_last_iter; + wire [ LOOP_ID_W -1 : 0 ] base_loop_index; + wire base_loop_index_valid; + wire _base_loop_index_valid; + + // Programming - OBUF LD/ST + wire obuf_stride_v; + wire [ ADDR_STRIDE_W -1 : 0 ] obuf_stride; + // Programming - Bias + wire bias_stride_v; + wire [ ADDR_STRIDE_W -1 : 0 ] bias_stride; + // Programming - OBUF ST + wire ibuf_stride_v; + wire [ ADDR_STRIDE_W -1 : 0 ] ibuf_stride; + // Programming - OBUF ST + wire wbuf_stride_v; + wire [ ADDR_STRIDE_W -1 : 0 ] wbuf_stride; + + + wire [ OBUF_ADDR_WIDTH -1 : 0 ] obuf_addr; + wire obuf_addr_v; + + + reg [ MEM_REQ_W -1 : 0 ] obuf_ld_req_size; + reg [ MEM_REQ_W -1 : 0 ] obuf_st_req_size; + + wire obuf_ld_req_valid; + wire obuf_st_req_valid; + + reg [ MEM_REQ_W -1 : 0 ] obuf_ld_req_loop_id; + reg [ MEM_REQ_W -1 : 0 ] obuf_st_req_loop_id; + + wire cfg_base_stride_v; +//============================================================================== + +//============================================================================== +// Assigns +//============================================================================== + assign cfg_base_loop_iter_v = cfg_loop_iter_v && cfg_loop_iter_loop_id == BASE_ID * 16; + assign cfg_base_loop_iter = cfg_loop_iter; + + assign cfg_base_stride_v = cfg_loop_stride_v && cfg_loop_stride_loop_id == BASE_ID * 16; + + assign obuf_stride = cfg_loop_stride; + assign obuf_stride_v = cfg_base_stride_v && cfg_loop_stride_type[0] == 1'b0 && cfg_loop_stride_id == OBUF_MEM_ID; + assign bias_stride = cfg_loop_stride; + assign bias_stride_v = cfg_base_stride_v && cfg_loop_stride_type[0] == 1'b0 && cfg_loop_stride_id == BBUF_MEM_ID; + assign ibuf_stride = cfg_loop_stride; + assign ibuf_stride_v = cfg_base_stride_v && cfg_loop_stride_type[0] == 1'b0 && cfg_loop_stride_id == IBUF_MEM_ID; + assign wbuf_stride = cfg_loop_stride; + assign wbuf_stride_v = cfg_base_stride_v && cfg_loop_stride_type[0] == 1'b0 && cfg_loop_stride_id == WBUF_MEM_ID; +//============================================================================== + +//============================================================================== +// Address generators +//============================================================================== + mem_walker_stride #( + .ADDR_WIDTH ( OBUF_ADDR_WIDTH ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) mws_obuf_ld ( + .clk ( clk ), //input + .reset ( reset ), //input + .base_addr ( obuf_base_addr ), //input + .loop_ctrl_done ( base_loop_done ), //input + .loop_index ( base_loop_index ), //input + .loop_index_valid ( _base_loop_index_valid ), //input + .loop_init ( base_loop_init ), //input + .loop_enter ( base_loop_enter ), //input + .loop_exit ( base_loop_exit ), //input + .cfg_addr_stride_v ( obuf_stride_v ), //input + .cfg_addr_stride ( obuf_stride ), //input + .addr_out ( obuf_addr ), //output + .addr_out_valid ( obuf_addr_v ) //output + ); + + assign obuf_st_addr = obuf_addr; + assign obuf_st_addr_v = obuf_addr_v; + + assign obuf_ld_addr = obuf_addr; + assign obuf_ld_addr_v = obuf_addr_v; + + obuf_bias_sel_logic #( + .LOOP_ID_W ( LOOP_ID_W ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ) + ) u_sel_logic ( + .clk ( clk ), // input + .reset ( reset ), // input + .start ( start ), // input + .done ( done ), // input + .obuf_stride ( obuf_stride ), // input + .obuf_stride_v ( obuf_stride_v ), // input + .loop_stall ( base_loop_stall ), // input + .loop_enter ( base_loop_enter ), // input + .loop_exit ( base_loop_exit ), // input + .loop_last_iter ( base_loop_last_iter ), // input + .loop_index_valid ( base_loop_index_valid ), // input + .loop_index ( base_loop_index ), // input + .bias_prev_sw ( bias_prev_sw ), // output + .ddr_pe_sw ( ddr_pe_sw ) // output + ); + + mem_walker_stride #( + .ADDR_WIDTH ( BBUF_ADDR_WIDTH ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) mws_bias_ld ( + .clk ( clk ), //input + .reset ( reset ), //input + .base_addr ( bias_base_addr ), //input + .loop_ctrl_done ( base_loop_done ), //input + .loop_index ( base_loop_index ), //input + .loop_index_valid ( _base_loop_index_valid ), //input + .loop_init ( base_loop_init ), //input + .loop_enter ( base_loop_enter ), //input + .loop_exit ( base_loop_exit ), //input + .cfg_addr_stride_v ( bias_stride_v ), //input + .cfg_addr_stride ( bias_stride ), //input + .addr_out ( bias_ld_addr ), //output + .addr_out_valid ( bias_ld_addr_v ) //output + ); + + mem_walker_stride #( + .ADDR_WIDTH ( IBUF_ADDR_WIDTH ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) mws_ibuf_ld ( + .clk ( clk ), //input + .reset ( reset ), //input + .base_addr ( ibuf_base_addr ), //input + .loop_ctrl_done ( base_loop_done ), //input + .loop_index ( base_loop_index ), //input + .loop_index_valid ( _base_loop_index_valid ), //input + .loop_init ( base_loop_init ), //input + .loop_enter ( base_loop_enter ), //input + .loop_exit ( base_loop_exit ), //input + .cfg_addr_stride_v ( ibuf_stride_v ), //input + .cfg_addr_stride ( ibuf_stride ), //input + .addr_out ( ibuf_ld_addr ), //output + .addr_out_valid ( ibuf_ld_addr_v ) //output + ); + + mem_walker_stride #( + .ADDR_WIDTH ( WBUF_ADDR_WIDTH ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) mws_wbuf_ld ( + .clk ( clk ), //input + .reset ( reset ), //input + .base_addr ( wbuf_base_addr ), //input + .loop_ctrl_done ( base_loop_done ), //input + .loop_index ( base_loop_index ), //input + .loop_index_valid ( _base_loop_index_valid ), //input + .loop_init ( base_loop_init ), //input + .loop_enter ( base_loop_enter ), //input + .loop_exit ( base_loop_exit ), //input + .cfg_addr_stride_v ( wbuf_stride_v ), //input + .cfg_addr_stride ( wbuf_stride ), //input + .addr_out ( wbuf_ld_addr ), //output + .addr_out_valid ( wbuf_ld_addr_v ) //output + ); +//============================================================================== + +//============================================================================== +// Base loop controller +//============================================================================== + assign base_loop_start = start; + assign base_loop_stall = !tag_ready; + assign done = base_loop_done; + assign tag_req = base_loop_index_valid; // && tag_ready; + assign _base_loop_index_valid = tag_req && tag_ready; + + // assign cfg_base_loop_iter_loop_id = {1'b0, cfg_loop_iter_loop_id[3:0]}; + always @(posedge clk) + begin + if (reset) + cfg_base_loop_iter_loop_id <= 0; + else begin + if (start) + cfg_base_loop_iter_loop_id <= 0; + else if (cfg_base_loop_iter_v) + cfg_base_loop_iter_loop_id <= cfg_base_loop_iter_loop_id + 1'b1; + end + end + + controller_fsm #( + .LOOP_ID_W ( LOOP_ID_W ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .IMEM_ADDR_W ( LOOP_ID_W ) + ) base_loop_ctrl ( + .clk ( clk ), //input + .reset ( reset ), //input + .cfg_loop_iter_v ( cfg_base_loop_iter_v ), //input + .cfg_loop_iter ( cfg_base_loop_iter ), //input + .cfg_loop_iter_loop_id ( cfg_base_loop_iter_loop_id ), //input + .start ( base_loop_start ), //input + .done ( base_loop_done ), //output + .stall ( base_loop_stall ), //input + .loop_init ( base_loop_init ), //output + .loop_enter ( base_loop_enter ), //output + .loop_exit ( base_loop_exit ), //output + .loop_last_iter ( base_loop_last_iter ), //output + .loop_index ( base_loop_index ), //output + .loop_index_valid ( base_loop_index_valid ) //output + ); +//============================================================================== + +//============================================================================== +// VCD +//============================================================================== +`ifdef COCOTB_TOPLEVEL_base_addr_gen +initial begin + $dumpfile("base_addr_gen.vcd"); + $dumpvars(0, base_addr_gen); +end +`endif +//============================================================================== +endmodule +// +// Signed Adder +// Implements: out = a + b +// +// Hardik Sharma +// (hsharma@gatech.edu) + +`timescale 1ns/1ps +module signed_adder #( + parameter integer DTYPE = "FXP", + parameter REGISTER_OUTPUT = "FALSE", + parameter integer IN1_WIDTH = 20, + parameter integer IN2_WIDTH = 32, + parameter integer OUT_WIDTH = 32 +) ( + input wire clk, + input wire reset, + input wire enable, + input wire [ IN1_WIDTH -1 : 0 ] a, + input wire [ IN2_WIDTH -1 : 0 ] b, + output wire [ OUT_WIDTH -1 : 0 ] out + ); + + generate + if (DTYPE == "FXP") begin + wire signed [ IN1_WIDTH-1:0] _a; + wire signed [ IN2_WIDTH-1:0] _b; + wire signed [ OUT_WIDTH-1:0] alu_out; + assign _a = a; + assign _b = b; + assign alu_out = _a + _b; + if (REGISTER_OUTPUT == "TRUE") begin + reg [OUT_WIDTH-1:0] _alu_out; + always @(posedge clk) + begin + if (enable) + _alu_out <= alu_out; + end + assign out = _alu_out; + end else + assign out = alu_out; + end + else if (DTYPE == "FP32") begin + fp32_add add ( + .clk ( clk ), + .a ( a ), + .b ( b ), + .result ( out ) + ); + end + else if (DTYPE == "FP16") begin + fp_mixed_add add ( + .clk ( clk ), + .a ( a ), + .b ( b ), + .result ( out ) + ); + end + endgenerate + +endmodule +// +// Wrapper for memory +// +// Hardik Sharma +// (hsharma@gatech.edu) + +`timescale 1ns/1ps +module obuf_mem_wrapper #( + // Internal Parameters + parameter integer MEM_ID = 1, + parameter integer STORE_ENABLED = 1, + parameter integer MEM_REQ_W = 16, + parameter integer ADDR_WIDTH = 8, + parameter integer DATA_WIDTH = 64, + parameter integer LOOP_ITER_W = 16, + parameter integer ADDR_STRIDE_W = 32, + parameter integer LOOP_ID_W = 5, + parameter integer BUF_TYPE_W = 2, + parameter integer NUM_TAGS = 4, + parameter integer TAG_W = $clog2(NUM_TAGS), + + // AXI + parameter integer AXI_ID_WIDTH = 1, + parameter integer AXI_ADDR_WIDTH = 42, + parameter integer AXI_DATA_WIDTH = 64, + parameter integer AXI_BURST_WIDTH = 8, + parameter integer WSTRB_W = AXI_DATA_WIDTH/8, + + // Buffer + parameter integer ARRAY_N = 4, + parameter integer ARRAY_M = 4, + parameter integer BUF_DATA_WIDTH = DATA_WIDTH * ARRAY_M, + parameter integer BUF_ADDR_W = 16, + parameter integer MEM_ADDR_W = BUF_ADDR_W + $clog2(BUF_DATA_WIDTH / AXI_DATA_WIDTH), + parameter integer TAG_BUF_ADDR_W = BUF_ADDR_W + TAG_W, + parameter integer TAG_MEM_ADDR_W = MEM_ADDR_W + TAG_W +) ( + input wire clk, + input wire reset, + + input wire tag_req, + input wire tag_reuse, + input wire tag_bias_prev_sw, + input wire tag_ddr_pe_sw, + output wire tag_ready, + output wire tag_done, + input wire compute_done, + input wire block_done, + input wire [ ADDR_WIDTH -1 : 0 ] tag_base_ld_addr, + input wire [ ADDR_WIDTH -1 : 0 ] tag_base_st_addr, + + output wire compute_ready, + output wire compute_bias_prev_sw, + + // Programming + input wire cfg_loop_stride_v, + input wire [ ADDR_STRIDE_W -1 : 0 ] cfg_loop_stride, + input wire [ LOOP_ID_W -1 : 0 ] cfg_loop_stride_loop_id, + input wire [ BUF_TYPE_W -1 : 0 ] cfg_loop_stride_id, + input wire [ 2 -1 : 0 ] cfg_loop_stride_type, + + input wire cfg_loop_iter_v, + input wire [ LOOP_ITER_W -1 : 0 ] cfg_loop_iter, + input wire [ LOOP_ID_W -1 : 0 ] cfg_loop_iter_loop_id, + + input wire cfg_mem_req_v, + input wire [ BUF_TYPE_W -1 : 0 ] cfg_mem_req_id, + input wire [ MEM_REQ_W -1 : 0 ] cfg_mem_req_size, + input wire [ LOOP_ID_W -1 : 0 ] cfg_mem_req_loop_id, + input wire [ 2 -1 : 0 ] cfg_mem_req_type, + + // Systolic Array + input wire [ BUF_DATA_WIDTH -1 : 0 ] buf_write_data, + input wire buf_write_req, + input wire [ BUF_ADDR_W -1 : 0 ] buf_write_addr, + output wire [ BUF_DATA_WIDTH -1 : 0 ] buf_read_data, + input wire buf_read_req, + input wire [ BUF_ADDR_W -1 : 0 ] buf_read_addr, + + // PU + input wire pu_buf_read_req, + input wire [ MEM_ADDR_W -1 : 0 ] pu_buf_read_addr, + output wire pu_buf_read_ready, + + output wire [ AXI_DATA_WIDTH -1 : 0 ] obuf_ld_stream_write_data, + output wire obuf_ld_stream_write_req, + + output wire pu_compute_start, + input wire pu_compute_ready, + input wire pu_compute_done, + + // CL_wrapper -> DDR AXI4 interface + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] mws_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] mws_awlen, + output wire [ 3 -1 : 0 ] mws_awsize, + output wire [ 2 -1 : 0 ] mws_awburst, + output wire mws_awvalid, + input wire mws_awready, + // Master Interface Write Data + output wire [ AXI_DATA_WIDTH -1 : 0 ] mws_wdata, + output wire [ WSTRB_W -1 : 0 ] mws_wstrb, + output wire mws_wlast, + output wire mws_wvalid, + input wire mws_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] mws_bresp, + input wire mws_bvalid, + output wire mws_bready, + // Master Interface Read Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] mws_araddr, + output wire [ AXI_ID_WIDTH -1 : 0 ] mws_arid, + output wire [ AXI_BURST_WIDTH -1 : 0 ] mws_arlen, + output wire [ 3 -1 : 0 ] mws_arsize, + output wire [ 2 -1 : 0 ] mws_arburst, + output wire mws_arvalid, + input wire mws_arready, + // Master Interface Read Data + input wire [ AXI_DATA_WIDTH -1 : 0 ] mws_rdata, + input wire [ AXI_ID_WIDTH -1 : 0 ] mws_rid, + input wire [ 2 -1 : 0 ] mws_rresp, + input wire mws_rlast, + input wire mws_rvalid, + output wire mws_rready, + + output wire [ 4 -1 : 0 ] stmem_state, + output wire [ TAG_W -1 : 0 ] stmem_tag, + output wire stmem_ddr_pe_sw +); + +//============================================================================== +// Localparams +//============================================================================== + localparam integer LDMEM_IDLE = 0; + localparam integer LDMEM_CHECK_RAW = 1; + localparam integer LDMEM_BUSY = 2; + localparam integer LDMEM_WAIT_0 = 3; + localparam integer LDMEM_WAIT_1 = 4; + localparam integer LDMEM_WAIT_2 = 5; + localparam integer LDMEM_WAIT_3 = 6; + localparam integer LDMEM_DONE = 7; + + localparam integer STMEM_IDLE = 0; + localparam integer STMEM_COMPUTE_WAIT = 1; + localparam integer STMEM_DDR = 2; + localparam integer STMEM_DDR_WAIT = 3; + localparam integer STMEM_DONE = 4; + localparam integer STMEM_PU = 5; + + localparam integer MEM_LD = 0; + localparam integer MEM_ST = 1; + localparam integer MEM_RD = 2; + localparam integer MEM_WR = 3; +//============================================================================== + +//============================================================================== +// Wires/Regs +//============================================================================== + wire compute_tag_done; + wire compute_tag_reuse; + wire compute_tag_ready; + wire [ TAG_W -1 : 0 ] compute_tag; + wire [ TAG_W -1 : 0 ] compute_tag_delayed; + wire ldmem_tag_done; + wire ldmem_tag_ready; + wire [ TAG_W -1 : 0 ] ldmem_tag; + wire stmem_tag_done; + wire stmem_tag_ready; + + reg [ 4 -1 : 0 ] ldmem_state_d; + reg [ 4 -1 : 0 ] ldmem_state_q; + + reg [ 4 -1 : 0 ] stmem_state_d; + reg [ 4 -1 : 0 ] stmem_state_q; + + wire ld_mem_req_v; + wire st_mem_req_v; + + wire [ TAG_W -1 : 0 ] tag; + + + reg ld_iter_v_q; + reg [ LOOP_ITER_W -1 : 0 ] iter_q; + reg st_iter_v_q; + + reg [ LOOP_ID_W -1 : 0 ] ld_loop_id_counter; + reg [ LOOP_ID_W -1 : 0 ] st_loop_id_counter; + + wire [ LOOP_ID_W -1 : 0 ] mws_ld_loop_iter_loop_id; + wire [ LOOP_ITER_W -1 : 0 ] mws_ld_loop_iter; + wire mws_ld_loop_iter_v; + wire mws_ld_start; + wire mws_ld_done; + wire mws_ld_stall; + wire mws_ld_init; + wire mws_ld_enter; + wire mws_ld_exit; + wire [ LOOP_ID_W -1 : 0 ] mws_ld_index; + wire mws_ld_index_valid; + wire mws_ld_step; + + wire [ LOOP_ID_W -1 : 0 ] mws_st_loop_iter_loop_id; + wire [ LOOP_ITER_W -1 : 0 ] mws_st_loop_iter; + wire mws_st_loop_iter_v; + wire mws_st_start; + wire mws_st_done; + wire mws_st_stall; + wire mws_st_init; + wire mws_st_enter; + wire mws_st_exit; + wire [ LOOP_ID_W -1 : 0 ] mws_st_index; + wire mws_st_index_valid; + wire mws_st_step; + + wire ld_stride_v; + wire [ ADDR_STRIDE_W -1 : 0 ] ld_stride; + wire [ BUF_TYPE_W -1 : 0 ] ld_stride_id; + wire st_stride_v; + wire [ ADDR_STRIDE_W -1 : 0 ] st_stride; + wire [ BUF_TYPE_W -1 : 0 ] st_stride_id; + + wire [ ADDR_WIDTH -1 : 0 ] ld_addr; + wire [ ADDR_WIDTH -1 : 0 ] mws_ld_base_addr; + wire ld_addr_v; + wire [ ADDR_WIDTH -1 : 0 ] st_addr; + wire [ ADDR_WIDTH -1 : 0 ] mws_st_base_addr; + wire st_addr_v; + + + reg [ MEM_REQ_W -1 : 0 ] ld_req_size; + reg [ MEM_REQ_W -1 : 0 ] st_req_size; + + wire ld_req_valid_d; + wire st_req_valid_d; + + reg ld_req_valid_q; + reg st_req_valid_q; + + //reg [ ADDR_WIDTH -1 : 0 ] tag_ld_addr[0:NUM_TAGS-1]; + //reg [ ADDR_WIDTH -1 : 0 ] tag_st_addr[0:NUM_TAGS-1]; + //reg [ ADDR_WIDTH -1 : 0 ] tag_st_addr_copy[0:NUM_TAGS-1]; + + reg [ ADDR_WIDTH -1 : 0 ] ld_req_addr; + reg [ ADDR_WIDTH -1 : 0 ] st_req_addr; + + reg [ MEM_REQ_W -1 : 0 ] st_req_loop_id; + + wire axi_rd_req; + wire [ AXI_ID_WIDTH -1 : 0 ] axi_rd_req_id; + wire axi_rd_done; + wire [ MEM_REQ_W -1 : 0 ] axi_rd_req_size; + wire axi_rd_ready; + wire [ AXI_ADDR_WIDTH -1 : 0 ] axi_rd_addr; + + wire axi_wr_req; + wire [ AXI_ID_WIDTH -1 : 0 ] axi_wr_req_id; + wire axi_wr_done; + wire [ MEM_REQ_W -1 : 0 ] axi_wr_req_size; + wire axi_wr_ready; + wire [ AXI_ADDR_WIDTH -1 : 0 ] axi_wr_addr; + + wire mem_write_req; + wire [ AXI_ID_WIDTH -1 : 0 ] mem_write_id; + wire [ AXI_DATA_WIDTH -1 : 0 ] mem_write_data; + reg [ MEM_ADDR_W -1 : 0 ] mem_write_addr; + wire mem_write_ready; + wire [ AXI_DATA_WIDTH -1 : 0 ] mem_read_data; + wire [ MEM_ADDR_W -1 : 0 ] mem_read_addr; + reg [ MEM_ADDR_W -1 : 0 ] axi_mem_read_addr; + wire axi_mem_read_req; + wire axi_mem_read_ready; + wire mem_read_req; + wire mem_read_ready; + + // Adding register to buf read data + wire [ BUF_DATA_WIDTH -1 : 0 ] _buf_read_data; +//============================================================================== + +//============================================================================== +// Assigns +//============================================================================== + assign ld_stride = cfg_loop_stride; + assign ld_stride_v = cfg_loop_stride_v && cfg_loop_stride_loop_id == 1 + MEM_ID && cfg_loop_stride_type == MEM_LD && cfg_loop_stride_id == MEM_ID; + assign st_stride = cfg_loop_stride; + assign st_stride_v = cfg_loop_stride_v && cfg_loop_stride_loop_id == 1 + MEM_ID && cfg_loop_stride_type == MEM_ST && cfg_loop_stride_id == MEM_ID; + + //assign mws_ld_base_addr = tag_ld_addr[ldmem_tag]; + //assign mws_st_base_addr = tag_st_addr[stmem_tag]; + assign axi_rd_req = ld_req_valid_q; + assign axi_rd_req_size = ld_req_size * (ARRAY_M * DATA_WIDTH) / AXI_DATA_WIDTH; + assign axi_rd_addr = ld_req_addr; + + assign axi_wr_req = st_req_valid_q; + assign axi_wr_req_id = 1'b0; + assign axi_wr_req_size = st_req_size * (ARRAY_M * DATA_WIDTH) / AXI_DATA_WIDTH; + assign axi_wr_addr = st_req_addr; +//============================================================================== + +//============================================================================== +//============================================================================== + reg read_req_dly1; + always @(posedge clk) + begin + if (reset) begin + read_req_dly1 <= 1'b0; + end else begin + read_req_dly1 <= pu_buf_read_req; + end + end + assign obuf_ld_stream_write_req = read_req_dly1; + assign obuf_ld_stream_write_data = mem_read_data; +//============================================================================== + +//============================================================================== +// Address generators +//============================================================================== + assign mws_ld_stall = ~ldmem_tag_ready || ~axi_rd_ready; + assign mws_ld_step = mws_ld_index_valid && !mws_ld_stall; + + mem_walker_stride #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) mws_ld ( + .clk ( clk ), //input + .reset ( reset ), //input + .base_addr ( mws_ld_base_addr ), //input + .loop_ctrl_done ( mws_ld_done ), //input + .loop_index ( mws_ld_index ), //input + .loop_index_valid ( mws_ld_step ), //input + .loop_init ( mws_ld_init ), //input + .loop_enter ( mws_ld_enter ), //input + .loop_exit ( mws_ld_exit ), //input + .cfg_addr_stride_v ( ld_stride_v ), //input + .cfg_addr_stride ( ld_stride ), //input + .addr_out ( ld_addr ), //output + .addr_out_valid ( ld_addr_v ) //output + ); + assign mws_st_step = mws_st_index_valid && !mws_st_stall; + assign mws_st_stall = ~stmem_tag_ready || ~axi_wr_ready; + wire _mws_st_done; + assign _mws_st_done = mws_st_done || mws_ld_done; // Added for the cases when the mws_st is programmed but not used + mem_walker_stride #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) mws_st ( + .clk ( clk ), //input + .reset ( reset ), //input + .base_addr ( mws_st_base_addr ), //input + .loop_ctrl_done ( _mws_st_done ), //input + .loop_index ( mws_st_index ), //input + .loop_index_valid ( mws_st_step ), //input + .loop_init ( mws_st_init ), //input + .loop_enter ( mws_st_enter ), //input + .loop_exit ( mws_st_exit ), //input + .cfg_addr_stride_v ( st_stride_v ), //input + .cfg_addr_stride ( st_stride ), //input + .addr_out ( st_addr ), //output + .addr_out_valid ( st_addr_v ) //output + ); + + //assign mws_st_step = mws_st_index_valid && !mws_st_stall; + //assign mws_st_stall = ~stmem_tag_ready || ~axi_wr_ready; +//============================================================================== + +//============================================================= +// Loop controller +//============================================================= + always@(posedge clk) + begin + if (reset) + ld_loop_id_counter <= 'b0; + else begin + if (mws_ld_loop_iter_v) + ld_loop_id_counter <= ld_loop_id_counter + 1'b1; + else if (tag_req && tag_ready) + ld_loop_id_counter <= 'b0; + end + end + + always @(posedge clk) + begin + if (reset) + ld_iter_v_q <= 1'b0; + else begin + if (cfg_loop_iter_v && cfg_loop_iter_loop_id == 1 + MEM_ID) + ld_iter_v_q <= 1'b1; + else if (cfg_loop_iter_v || ld_stride_v) + ld_iter_v_q <= 1'b0; + end + end + + + always @(posedge clk) + begin + if (reset) + st_iter_v_q <= 1'b0; + else begin + if (cfg_loop_iter_v && cfg_loop_iter_loop_id == 1 + MEM_ID) + st_iter_v_q <= 1'b1; + else if (cfg_loop_iter_v || st_stride_v) + st_iter_v_q <= 1'b0; + end + end + + always@(posedge clk) + begin + if (reset) + st_loop_id_counter <= 'b0; + else begin + if (mws_st_loop_iter_v) + st_loop_id_counter <= st_loop_id_counter + 1'b1; + else if (tag_req && tag_ready) + st_loop_id_counter <= 'b0; + end + end + + assign mws_ld_start = (ldmem_state_q == LDMEM_BUSY); + assign mws_ld_loop_iter_v = ld_stride_v && ld_iter_v_q; + assign mws_ld_loop_iter = iter_q; + assign mws_ld_loop_iter_loop_id = ld_loop_id_counter; + + always @(posedge clk) + begin + if (reset) begin + iter_q <= 'b0; + end + else if (cfg_loop_iter_v && cfg_loop_iter_loop_id == 1 + MEM_ID) begin + iter_q <= cfg_loop_iter; + end + end + + controller_fsm #( + .LOOP_ID_W ( LOOP_ID_W ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .IMEM_ADDR_W ( LOOP_ID_W ) + ) mws_ld_ctrl ( + .clk ( clk ), //input + .reset ( reset ), //input + .stall ( mws_ld_stall ), //input + .cfg_loop_iter_v ( mws_ld_loop_iter_v ), //input + .cfg_loop_iter ( mws_ld_loop_iter ), //input + .cfg_loop_iter_loop_id ( mws_ld_loop_iter_loop_id ), //input + .start ( mws_ld_start ), //input + .done ( mws_ld_done ), //output + .loop_init ( mws_ld_init ), //output + .loop_enter ( mws_ld_enter ), //output + .loop_last_iter ( ), //output + .loop_exit ( mws_ld_exit ), //output + .loop_index ( mws_ld_index ), //output + .loop_index_valid ( mws_ld_index_valid ) //output + ); + + assign mws_st_loop_iter_loop_id = st_loop_id_counter; + assign mws_st_start = stmem_state_q == STMEM_DDR; + assign mws_st_loop_iter = iter_q; + + assign mws_st_loop_iter_v = st_stride_v && st_iter_v_q; + + controller_fsm #( + .LOOP_ID_W ( LOOP_ID_W ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .IMEM_ADDR_W ( LOOP_ID_W ) + ) mws_st_ctrl ( + .clk ( clk ), //input + .reset ( reset ), //input + .stall ( mws_st_stall ), //input + .cfg_loop_iter_v ( mws_st_loop_iter_v ), //input + .cfg_loop_iter ( mws_st_loop_iter ), //input + .cfg_loop_iter_loop_id ( mws_st_loop_iter_loop_id ), //input + .start ( mws_st_start ), //input + .done ( mws_st_done ), //output + .loop_init ( mws_st_init ), //output + .loop_last_iter ( ), //output + .loop_enter ( mws_st_enter ), //output + .loop_exit ( mws_st_exit ), //output + .loop_index ( mws_st_index ), //output + .loop_index_valid ( mws_st_index_valid ) //output + ); +//============================================================= + +//============================================================================== +// Memory Request generation +//============================================================================== + assign ld_mem_req_v = cfg_mem_req_v && cfg_mem_req_loop_id == (1 + MEM_ID) && cfg_mem_req_type == MEM_LD && cfg_mem_req_id == MEM_ID; + always @(posedge clk) + begin + if (reset) begin + ld_req_size <= 'b0; + end + else if (ld_mem_req_v) begin + ld_req_size <= cfg_mem_req_size; + end + end + + assign st_mem_req_v = cfg_mem_req_v && cfg_mem_req_loop_id == (1 + MEM_ID) && cfg_mem_req_type == MEM_ST && cfg_mem_req_id == MEM_ID; + always @(posedge clk) + begin + if (reset) begin + st_req_size <= 'b0; + st_req_loop_id <= 'b0; + end + else if (st_mem_req_v) begin + st_req_size <= cfg_mem_req_size; + st_req_loop_id <= st_loop_id_counter; + end + end + + // assign ld_req_valid_d = (ld_req_loop_id == mws_ld_index) && (mws_ld_enter || mws_ld_step); + // assign ld_req_valid_d = (ld_req_loop_id == mws_ld_index) && ld_addr_v; + assign ld_req_valid_d = ld_addr_v; + // assign st_req_valid_d = STORE_ENABLED == 1 && (st_req_loop_id == mws_st_index) && (mws_st_step || mws_st_exit); + assign st_req_valid_d = STORE_ENABLED == 1 && (st_req_loop_id == mws_st_index) && st_addr_v; + + always @(posedge clk) + begin + if (reset) begin + ld_req_valid_q <= 1'b0; + ld_req_addr <= 'b0; + st_req_valid_q <= 1'b0; + st_req_addr <= 1'b0; + end + else begin + ld_req_valid_q <= ld_req_valid_d; + ld_req_addr <= ld_addr; + st_req_valid_q <= st_req_valid_d; + st_req_addr <= st_addr; + end + end + + //always @(posedge clk) + //begin + // if (tag_req && tag_ready) begin + // tag_ld_addr[tag] <= tag_base_ld_addr; + // tag_st_addr[tag] <= tag_base_st_addr; + // tag_st_addr_copy[tag] <= tag_base_st_addr; + // end + //end + + // wire [ 31 : 0 ] tag0_ld_addr; + // wire [ 31 : 0 ] tag1_ld_addr; + // wire [ 31 : 0 ] tag0_st_addr; + // wire [ 31 : 0 ] tag1_st_addr; + // assign tag0_ld_addr = tag_ld_addr[0]; + // assign tag1_ld_addr = tag_ld_addr[1]; + // assign tag0_st_addr = tag_st_addr[0]; + // assign tag1_st_addr = tag_st_addr[1]; +//============================================================================== + +//============================================================================== +// Tag-based synchronization for double buffering +//============================================================================== + reg raw; + reg [ TAG_W -1 : 0 ] raw_stmem_tag_d; + reg [ TAG_W -1 : 0 ] raw_stmem_tag_q; + wire [ TAG_W -1 : 0 ] raw_stmem_tag; + wire raw_stmem_tag_ready; + wire [ ADDR_WIDTH -1 : 0 ] raw_stmem_st_addr; + + always @(posedge clk) + begin + if (reset) + raw_stmem_tag_q <= 0; + else + raw_stmem_tag_q <= raw_stmem_tag_d; + end + + assign raw_stmem_tag = raw_stmem_tag_q; + //assign raw_stmem_st_addr = tag_st_addr_copy[raw_stmem_tag]; + + ram #( + .ADDR_WIDTH ( $clog2(NUM_TAGS)), + .DATA_WIDTH ( ADDR_WIDTH) + ) u_ram_tag_st1( + .clk ( clk ), + .reset ( reset ), + .s_write_addr ( tag), + .s_write_req ( tag_req && tag_ready), + .s_write_data ( tag_base_st_addr), + .s_read_addr ( raw_stmem_tag), + .s_read_req (1'b1 ), + .s_read_data ( raw_stmem_st_addr) + ); + + ram #( + .ADDR_WIDTH ( $clog2(NUM_TAGS)), + .DATA_WIDTH ( ADDR_WIDTH) + ) u_ram_tag_st2( + .clk ( clk ), + .reset ( reset ), + .s_write_addr ( tag), + .s_write_req ( tag_req && tag_ready), + .s_write_data ( tag_base_st_addr), + .s_read_addr ( stmem_tag), + .s_read_req ( 1'b1), + .s_read_data ( mws_st_base_addr) + ); + + ram #( + .ADDR_WIDTH ( $clog2(NUM_TAGS)), + .DATA_WIDTH ( ADDR_WIDTH) + ) u_ram_tag_ld( + .clk ( clk ), + .reset ( reset ), + .s_write_addr ( tag), + .s_write_req ( tag_req && tag_ready), + .s_write_data ( tag_base_ld_addr), + .s_read_addr ( ldmem_tag), + .s_read_req ( 1'b1), + .s_read_data ( mws_ld_base_addr) + ); + + + assign stmem_state = stmem_state_q; + always @(*) + begin + ldmem_state_d = ldmem_state_q; + raw_stmem_tag_d = raw_stmem_tag_q; + case(ldmem_state_q) + LDMEM_IDLE: begin + if (ldmem_tag_ready) begin + if (ldmem_tag == stmem_tag) + ldmem_state_d = LDMEM_BUSY; + else begin + ldmem_state_d = LDMEM_CHECK_RAW; + raw_stmem_tag_d = stmem_tag; + end + end + end + LDMEM_CHECK_RAW: begin + if (raw_stmem_st_addr != mws_ld_base_addr) + ldmem_state_d = LDMEM_BUSY; + else if (stmem_state_q == STMEM_DONE) + ldmem_state_d = LDMEM_IDLE; + end + LDMEM_BUSY: begin + if (mws_ld_done) + ldmem_state_d = LDMEM_WAIT_0; + end + LDMEM_WAIT_0: begin + ldmem_state_d = LDMEM_WAIT_1; + end + LDMEM_WAIT_1: begin + ldmem_state_d = LDMEM_WAIT_2; + end + LDMEM_WAIT_2: begin + ldmem_state_d = LDMEM_WAIT_3; + end + LDMEM_WAIT_3: begin + if (axi_rd_done) + ldmem_state_d = LDMEM_DONE; + end + LDMEM_DONE: begin + ldmem_state_d = LDMEM_IDLE; + end + endcase + end + + always @(posedge clk) + begin + if (reset) + ldmem_state_q <= LDMEM_IDLE; + else + ldmem_state_q <= ldmem_state_d; + end + + reg pu_start_d; + reg pu_start_q; + assign pu_compute_start = pu_start_q; + + always @(posedge clk) + begin + if (reset) + pu_start_q <= 1'b0; + else + pu_start_q <= pu_start_d; + end + + localparam integer WAIT_CYCLE_WIDTH = $clog2(ARRAY_N) > 5 ? $clog2(ARRAY_N) : 5; + reg [ WAIT_CYCLE_WIDTH : 0 ] wait_cycles_d; + reg [ WAIT_CYCLE_WIDTH : 0 ] wait_cycles_q; + + always @(posedge clk) + begin + if (reset) + wait_cycles_q <= 0; + else + wait_cycles_q <= wait_cycles_d; + end + + always @(*) + begin + stmem_state_d = stmem_state_q; + pu_start_d = 1'b0; + wait_cycles_d = wait_cycles_q; + case(stmem_state_q) + STMEM_IDLE: begin + if (stmem_tag_ready) begin + stmem_state_d = STMEM_COMPUTE_WAIT; + wait_cycles_d = ARRAY_N; + end + end + STMEM_COMPUTE_WAIT: begin + if (wait_cycles_q == 0) begin + if (~stmem_ddr_pe_sw) + stmem_state_d = STMEM_DDR; + else if (pu_compute_ready) begin + stmem_state_d = STMEM_PU; + pu_start_d = 1'b1; + wait_cycles_d = ARRAY_N + 1'b1; + end + end + else + wait_cycles_d = wait_cycles_q - 1'b1; + end + STMEM_PU: begin + if (pu_compute_done) + stmem_state_d = STMEM_DONE; + end + STMEM_DDR: begin + if (mws_st_done) begin + stmem_state_d = STMEM_DDR_WAIT; + wait_cycles_d = 4; + end + end + STMEM_DDR_WAIT: begin + if (wait_cycles_q == 0) begin + if (axi_wr_done) begin + stmem_state_d = STMEM_DONE; + wait_cycles_d = 0; + end + end else + wait_cycles_d = wait_cycles_q - 1'b1; + end + STMEM_DONE: begin + stmem_state_d = STMEM_IDLE; + end + endcase + end + + always @(posedge clk) + begin + if (reset) + stmem_state_q <= STMEM_IDLE; + else + stmem_state_q <= stmem_state_d; + end + + + wire ldmem_ready; + + assign compute_tag_done = compute_done; + assign compute_ready = compute_tag_ready; + + assign ldmem_tag_done = ldmem_state_q == LDMEM_DONE; + assign ldmem_ready = ldmem_tag_ready; + // assign ldmem_tag_done = mws_ld_done; + + assign stmem_tag_done = stmem_state_q == STMEM_DONE; + + tag_sync #( + .NUM_TAGS ( NUM_TAGS ) + ) + mws_tag ( + .clk ( clk ), + .reset ( reset ), + .block_done ( block_done ), + .tag_req ( tag_req ), + .tag_reuse ( tag_reuse ), + .tag_bias_prev_sw ( tag_bias_prev_sw ), + .tag_ddr_pe_sw ( tag_ddr_pe_sw ), //input + .tag_ready ( tag_ready ), + .tag ( tag ), + .tag_done ( tag_done ), + .raw_stmem_tag ( raw_stmem_tag_q ), + .raw_stmem_tag_ready ( raw_stmem_tag_ready ), + .compute_tag_done ( compute_tag_done ), + .compute_tag_ready ( compute_tag_ready ), + .compute_bias_prev_sw ( compute_bias_prev_sw ), + .compute_tag ( compute_tag ), + .ldmem_tag_done ( ldmem_tag_done ), + .ldmem_tag_ready ( ldmem_tag_ready ), + .ldmem_tag ( ldmem_tag ), + .stmem_ddr_pe_sw ( stmem_ddr_pe_sw ), + .stmem_tag_done ( stmem_tag_done ), + .stmem_tag_ready ( stmem_tag_ready ), + .stmem_tag ( stmem_tag ) + ); +//============================================================================== + +//============================================================================== +// AXI4 Memory Mapped interface +//============================================================================== + assign mem_write_ready = 1'b1; + assign mem_read_ready = 1'b1; + assign axi_rd_req_id = 0; + axi_master #( + .TX_SIZE_WIDTH ( MEM_REQ_W ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_BURST_WIDTH ( AXI_BURST_WIDTH ) + ) u_axi_mm_master ( + .clk ( clk ), + .reset ( reset ), + .m_axi_awaddr ( mws_awaddr ), + .m_axi_awlen ( mws_awlen ), + .m_axi_awsize ( mws_awsize ), + .m_axi_awburst ( mws_awburst ), + .m_axi_awvalid ( mws_awvalid ), + .m_axi_awready ( mws_awready ), + .m_axi_wdata ( mws_wdata ), + .m_axi_wstrb ( mws_wstrb ), + .m_axi_wlast ( mws_wlast ), + .m_axi_wvalid ( mws_wvalid ), + .m_axi_wready ( mws_wready ), + .m_axi_bresp ( mws_bresp ), + .m_axi_bvalid ( mws_bvalid ), + .m_axi_bready ( mws_bready ), + .m_axi_araddr ( mws_araddr ), + .m_axi_arid ( mws_arid ), + .m_axi_arlen ( mws_arlen ), + .m_axi_arsize ( mws_arsize ), + .m_axi_arburst ( mws_arburst ), + .m_axi_arvalid ( mws_arvalid ), + .m_axi_arready ( mws_arready ), + .m_axi_rdata ( mws_rdata ), + .m_axi_rid ( mws_rid ), + .m_axi_rresp ( mws_rresp ), + .m_axi_rlast ( mws_rlast ), + .m_axi_rvalid ( mws_rvalid ), + .m_axi_rready ( mws_rready ), + // Buffer + .mem_write_id ( mem_write_id ), + .mem_write_req ( mem_write_req ), + .mem_write_data ( mem_write_data ), + .mem_write_ready ( mem_write_ready ), + .mem_read_data ( mem_read_data ), + .mem_read_req ( axi_mem_read_req ), + .mem_read_ready ( axi_mem_read_ready ), + // AXI RD Req + .rd_req ( axi_rd_req ), + .rd_req_id ( axi_rd_req_id ), + .rd_done ( axi_rd_done ), + .rd_ready ( axi_rd_ready ), + .rd_req_size ( axi_rd_req_size ), + .rd_addr ( axi_rd_addr ), + // AXI WR Req + .wr_req ( axi_wr_req ), + .wr_req_id ( axi_wr_req_id ), + .wr_ready ( axi_wr_ready ), + .wr_req_size ( axi_wr_req_size ), + .wr_addr ( axi_wr_addr ), + .wr_done ( axi_wr_done ) + ); +//============================================================================== + +//============================================================================== +// Dual-port RAM +//============================================================================== + always @(posedge clk) + begin + if (reset) + axi_mem_read_addr <= 0; + else begin + if (mem_read_req) + axi_mem_read_addr <= axi_mem_read_addr + 1'b1; + else if (stmem_state_q == STMEM_DONE) + axi_mem_read_addr <= 0; + end + end + + assign mem_read_addr = stmem_state_q == STMEM_PU ? pu_buf_read_addr : axi_mem_read_addr; + assign mem_read_req = stmem_state_q == STMEM_PU ? pu_buf_read_req : axi_mem_read_req; + assign axi_mem_read_ready = stmem_state_q != STMEM_PU; + assign pu_buf_read_ready = stmem_state_q == STMEM_PU; + + always @(posedge clk) + begin + if (reset) + mem_write_addr <= 0; + else begin + if (mem_write_req) + mem_write_addr <= mem_write_addr + 1'b1; + else if (ldmem_state_q == LDMEM_DONE) + mem_write_addr <= 0; + end + end + + wire [ TAG_MEM_ADDR_W -1 : 0 ] tag_mem_read_addr; + wire [ TAG_MEM_ADDR_W -1 : 0 ] tag_mem_write_addr; + + wire [ TAG_BUF_ADDR_W -1 : 0 ] tag_buf_read_addr; + wire [ TAG_BUF_ADDR_W -1 : 0 ] tag_buf_write_addr; + + assign tag_mem_read_addr = {stmem_tag, mem_read_addr}; + assign tag_mem_write_addr = {ldmem_tag, mem_write_addr}; + + genvar i; + generate + if (MEM_ID == 1 || MEM_ID == 3) + begin: OBUF_TAG_DELAY + for (i=0; i CL_wrapper AXI4-Lite interface + // Slave Write address + input wire pci_cl_ctrl_awvalid, + input wire [ CTRL_ADDR_WIDTH -1 : 0 ] pci_cl_ctrl_awaddr, + output wire pci_cl_ctrl_awready, + // Slave Write data + input wire pci_cl_ctrl_wvalid, + input wire [ CTRL_DATA_WIDTH -1 : 0 ] pci_cl_ctrl_wdata, + input wire [ CTRL_WSTRB_WIDTH -1 : 0 ] pci_cl_ctrl_wstrb, + output wire pci_cl_ctrl_wready, + // Slave Write response + output wire pci_cl_ctrl_bvalid, + output wire [ 2 -1 : 0 ] pci_cl_ctrl_bresp, + input wire pci_cl_ctrl_bready, + // Slave Read address + input wire pci_cl_ctrl_arvalid, + input wire [ CTRL_ADDR_WIDTH -1 : 0 ] pci_cl_ctrl_araddr, + output wire pci_cl_ctrl_arready, + // Slave Read data/response + output wire pci_cl_ctrl_rvalid, + output wire [ CTRL_DATA_WIDTH -1 : 0 ] pci_cl_ctrl_rdata, + output wire [ 2 -1 : 0 ] pci_cl_ctrl_rresp, + input wire pci_cl_ctrl_rready, + + // PCIe -> CL_wrapper AXI4 interface + // Slave Interface Write Address + input wire [ INST_ADDR_WIDTH -1 : 0 ] pci_cl_data_awaddr, + input wire [ INST_BURST_WIDTH -1 : 0 ] pci_cl_data_awlen, + input wire [ 3 -1 : 0 ] pci_cl_data_awsize, + input wire [ 2 -1 : 0 ] pci_cl_data_awburst, + input wire pci_cl_data_awvalid, + output wire pci_cl_data_awready, + // Slave Interface Write Data + input wire [ INST_DATA_WIDTH -1 : 0 ] pci_cl_data_wdata, + input wire [ INST_WSTRB_WIDTH -1 : 0 ] pci_cl_data_wstrb, + input wire pci_cl_data_wlast, + input wire pci_cl_data_wvalid, + output wire pci_cl_data_wready, + // Slave Interface Write Response + output wire [ 2 -1 : 0 ] pci_cl_data_bresp, + output wire pci_cl_data_bvalid, + input wire pci_cl_data_bready, + // Slave Interface Read Address + input wire [ INST_ADDR_WIDTH -1 : 0 ] pci_cl_data_araddr, + input wire [ INST_BURST_WIDTH -1 : 0 ] pci_cl_data_arlen, + input wire [ 3 -1 : 0 ] pci_cl_data_arsize, + input wire [ 2 -1 : 0 ] pci_cl_data_arburst, + input wire pci_cl_data_arvalid, + output wire pci_cl_data_arready, + // Slave Interface Read Data + output wire [ INST_DATA_WIDTH -1 : 0 ] pci_cl_data_rdata, + output wire [ 2 -1 : 0 ] pci_cl_data_rresp, + output wire pci_cl_data_rlast, + output wire pci_cl_data_rvalid, + input wire pci_cl_data_rready, + + // CL_wrapper -> DDR0 AXI4 interface + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr0_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr0_awlen, + output wire [ 3 -1 : 0 ] cl_ddr0_awsize, + output wire [ 2 -1 : 0 ] cl_ddr0_awburst, + output wire cl_ddr0_awvalid, + input wire cl_ddr0_awready, + // Master Interface Write Data + output wire [ IBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr0_wdata, + output wire [ IBUF_WSTRB_W -1 : 0 ] cl_ddr0_wstrb, + output wire cl_ddr0_wlast, + output wire cl_ddr0_wvalid, + input wire cl_ddr0_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] cl_ddr0_bresp, + input wire cl_ddr0_bvalid, + output wire cl_ddr0_bready, + // Master Interface Read Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr0_araddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr0_arlen, + output wire [ 3 -1 : 0 ] cl_ddr0_arsize, + output wire [ 2 -1 : 0 ] cl_ddr0_arburst, + output wire cl_ddr0_arvalid, + output wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr0_arid, + input wire cl_ddr0_arready, + // Master Interface Read Data + input wire [ IBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr0_rdata, + input wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr0_rid, + input wire [ 2 -1 : 0 ] cl_ddr0_rresp, + input wire cl_ddr0_rlast, + input wire cl_ddr0_rvalid, + output wire cl_ddr0_rready, + + // CL_wrapper -> DDR1 AXI4 interface + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr1_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr1_awlen, + output wire [ 3 -1 : 0 ] cl_ddr1_awsize, + output wire [ 2 -1 : 0 ] cl_ddr1_awburst, + output wire cl_ddr1_awvalid, + input wire cl_ddr1_awready, + // Master Interface Write Data + output wire [ OBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr1_wdata, + output wire [ OBUF_WSTRB_W -1 : 0 ] cl_ddr1_wstrb, + output wire cl_ddr1_wlast, + output wire cl_ddr1_wvalid, + input wire cl_ddr1_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] cl_ddr1_bresp, + input wire cl_ddr1_bvalid, + output wire cl_ddr1_bready, + // Master Interface Read Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr1_araddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr1_arlen, + output wire [ 3 -1 : 0 ] cl_ddr1_arsize, + output wire [ 2 -1 : 0 ] cl_ddr1_arburst, + output wire cl_ddr1_arvalid, + output wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr1_arid, + input wire cl_ddr1_arready, + // Master Interface Read Data + input wire [ OBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr1_rdata, + input wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr1_rid, + input wire [ 2 -1 : 0 ] cl_ddr1_rresp, + input wire cl_ddr1_rlast, + input wire cl_ddr1_rvalid, + output wire cl_ddr1_rready, + + // CL_wrapper -> DDR2 AXI4 interface + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr2_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr2_awlen, + output wire [ 3 -1 : 0 ] cl_ddr2_awsize, + output wire [ 2 -1 : 0 ] cl_ddr2_awburst, + output wire cl_ddr2_awvalid, + input wire cl_ddr2_awready, + // Master Interface Write Data + output wire [ WBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr2_wdata, + output wire [ WBUF_WSTRB_W -1 : 0 ] cl_ddr2_wstrb, + output wire cl_ddr2_wlast, + output wire cl_ddr2_wvalid, + input wire cl_ddr2_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] cl_ddr2_bresp, + input wire cl_ddr2_bvalid, + output wire cl_ddr2_bready, + // Master Interface Read Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr2_araddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr2_arlen, + output wire [ 3 -1 : 0 ] cl_ddr2_arsize, + output wire [ 2 -1 : 0 ] cl_ddr2_arburst, + output wire cl_ddr2_arvalid, + output wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr2_arid, + input wire cl_ddr2_arready, + // Master Interface Read Data + input wire [ WBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr2_rdata, + input wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr2_rid, + input wire [ 2 -1 : 0 ] cl_ddr2_rresp, + input wire cl_ddr2_rlast, + input wire cl_ddr2_rvalid, + output wire cl_ddr2_rready, + + // CL_wrapper -> DDR3 AXI4 interface + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr3_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr3_awlen, + output wire [ 3 -1 : 0 ] cl_ddr3_awsize, + output wire [ 2 -1 : 0 ] cl_ddr3_awburst, + output wire cl_ddr3_awvalid, + input wire cl_ddr3_awready, + // Master Interface Write Data + output wire [ BBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr3_wdata, + output wire [ BBUF_WSTRB_W -1 : 0 ] cl_ddr3_wstrb, + output wire cl_ddr3_wlast, + output wire cl_ddr3_wvalid, + input wire cl_ddr3_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] cl_ddr3_bresp, + input wire cl_ddr3_bvalid, + output wire cl_ddr3_bready, + // Master Interface Read Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr3_araddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr3_arlen, + output wire [ 3 -1 : 0 ] cl_ddr3_arsize, + output wire [ 2 -1 : 0 ] cl_ddr3_arburst, + output wire cl_ddr3_arvalid, + output wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr3_arid, + input wire cl_ddr3_arready, + // Master Interface Read Data + input wire [ BBUF_AXI_DATA_WIDTH -1 : 0 ] cl_ddr3_rdata, + input wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr3_rid, + input wire [ 2 -1 : 0 ] cl_ddr3_rresp, + input wire cl_ddr3_rlast, + input wire cl_ddr3_rvalid, + output wire cl_ddr3_rready, + + // CL_wrapper -> DDR3 AXI4 interface + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr4_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr4_awlen, + output wire [ 3 -1 : 0 ] cl_ddr4_awsize, + output wire [ 2 -1 : 0 ] cl_ddr4_awburst, + output wire cl_ddr4_awvalid, + input wire cl_ddr4_awready, + // Master Interface Write Data + output wire [ PU_AXI_DATA_WIDTH -1 : 0 ] cl_ddr4_wdata, + output wire [ PU_WSTRB_W -1 : 0 ] cl_ddr4_wstrb, + output wire cl_ddr4_wlast, + output wire cl_ddr4_wvalid, + input wire cl_ddr4_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] cl_ddr4_bresp, + input wire cl_ddr4_bvalid, + output wire cl_ddr4_bready, + // Master Interface Read Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] cl_ddr4_araddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] cl_ddr4_arlen, + output wire [ 3 -1 : 0 ] cl_ddr4_arsize, + output wire [ 2 -1 : 0 ] cl_ddr4_arburst, + output wire cl_ddr4_arvalid, + output wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr4_arid, + input wire cl_ddr4_arready, + // Master Interface Read Data + input wire [ PU_AXI_DATA_WIDTH -1 : 0 ] cl_ddr4_rdata, + input wire [ AXI_ID_WIDTH -1 : 0 ] cl_ddr4_rid, + input wire [ 2 -1 : 0 ] cl_ddr4_rresp, + input wire cl_ddr4_rlast, + input wire cl_ddr4_rvalid, + output wire cl_ddr4_rready + ); + +//============================================================= +// Localparams +//============================================================= + localparam integer STATE_W = 1; + localparam integer ACCUMULATOR_WIDTH = 48; + // localparam integer PMAX = DATA_WIDTH; + // localparam integer PMIN = DATA_WIDTH; +//============================================================= + +//============================================================= +// Wires/Regs +//============================================================= + wire [ INST_DATA_WIDTH -1 : 0 ] obuf_ld_stream_read_count; + wire [ INST_DATA_WIDTH -1 : 0 ] obuf_ld_stream_write_count; + wire [ INST_DATA_WIDTH -1 : 0 ] ddr_st_stream_read_count; + wire [ INST_DATA_WIDTH -1 : 0 ] ddr_st_stream_write_count; + wire [ INST_DATA_WIDTH -1 : 0 ] ld0_stream_counts; + wire [ INST_DATA_WIDTH -1 : 0 ] ld1_stream_counts; + wire [ INST_DATA_WIDTH -1 : 0 ] axi_wr_fifo_counts; + + // OBUF STMEM state + wire [ 4 -1 : 0 ] stmem_state; + wire [ TAG_W -1 : 0 ] stmem_tag; + wire stmem_ddr_pe_sw; + + // PU + wire pu_compute_start; + wire pu_compute_ready; + wire pu_compute_done; + wire pu_write_done; + wire [ 3 -1 : 0 ] pu_ctrl_state; + wire pu_done; + wire pu_inst_wr_ready; + // PU -> OBUF addr + wire ld_obuf_req; + wire ld_obuf_ready; + wire [ PU_OBUF_ADDR_WIDTH -1 : 0 ] ld_obuf_addr; + // OBUF -> PU addr + wire obuf_ld_stream_write_req; + wire [ OBUF_AXI_DATA_WIDTH -1 : 0 ] obuf_ld_stream_write_data; + + // Snoop + wire [ CTRL_DATA_WIDTH -1 : 0 ] snoop_cl_ddr0_araddr; + wire [ CTRL_DATA_WIDTH -1 : 0 ] snoop_cl_ddr1_araddr; + wire [ CTRL_DATA_WIDTH -1 : 0 ] snoop_cl_ddr1_awaddr; + wire [ CTRL_DATA_WIDTH -1 : 0 ] snoop_cl_ddr2_araddr; + wire [ CTRL_DATA_WIDTH -1 : 0 ] snoop_cl_ddr3_araddr; + wire [ CTRL_DATA_WIDTH -1 : 0 ] snoop_cl_ddr4_araddr; + wire [ CTRL_DATA_WIDTH -1 : 0 ] snoop_cl_ddr4_awaddr; + + // PU Instructions + wire cfg_pu_inst_v; + wire [ INST_DATA_WIDTH -1 : 0 ] cfg_pu_inst; + wire pu_block_start; + wire pu_block_end; + // Systolic array + wire acc_clear; + wire [ OBUF_DATA_WIDTH -1 : 0 ] sys_obuf_write_data; + + // switch between bias and obuf + wire rd_bias_prev_sw; + + // Loop iterations + wire [ LOOP_ITER_W -1 : 0 ] cfg_loop_iter; + wire [ LOOP_ID_W -1 : 0 ] cfg_loop_iter_loop_id; + wire cfg_loop_iter_v; + // Loop stride + wire [ 16 -1 : 0 ] cfg_loop_stride_lo; + wire [ ADDR_STRIDE_W -1 : 0 ] cfg_loop_stride; + wire cfg_loop_stride_v; + wire [ BUF_TYPE_W -1 : 0 ] cfg_loop_stride_id; + wire [ 2 -1 : 0 ] cfg_loop_stride_type; + wire [ LOOP_ID_W -1 : 0 ] cfg_loop_stride_loop_id; + + // Memory request + wire [ MEM_REQ_W -1 : 0 ] cfg_mem_req_size; + wire cfg_mem_req_v; + wire [ 2 -1 : 0 ] cfg_mem_req_type; + wire [ BUF_TYPE_W -1 : 0 ] cfg_mem_req_id; + wire [ LOOP_ID_W -1 : 0 ] cfg_mem_req_loop_id; + // Buffer request + wire [ MEM_REQ_W -1 : 0 ] cfg_buf_req_size; + wire cfg_buf_req_v; + wire cfg_buf_req_type; + wire [ BUF_TYPE_W -1 : 0 ] cfg_buf_req_loop_id; + + wire main_start; + wire main_done; + + // Address - OBUF + wire [ ADDR_WIDTH -1 : 0 ] obuf_base_addr; + wire [ ADDR_WIDTH -1 : 0 ] obuf_ld_addr; + wire obuf_ld_addr_v; + wire [ ADDR_WIDTH -1 : 0 ] obuf_st_addr; + wire obuf_st_addr_v; + // Address - IBUF + wire [ ADDR_WIDTH -1 : 0 ] ibuf_base_addr; + wire [ ADDR_WIDTH -1 : 0 ] ibuf_ld_addr; + wire ibuf_ld_addr_v; + // Address - WBUF + wire [ ADDR_WIDTH -1 : 0 ] wbuf_base_addr; + wire [ ADDR_WIDTH -1 : 0 ] wbuf_ld_addr; + wire wbuf_ld_addr_v; + wire [ ADDR_WIDTH -1 : 0 ] wbuf_st_addr; + wire wbuf_st_addr_v; + // Address - BIAS + wire [ ADDR_WIDTH -1 : 0 ] bias_base_addr; + wire [ ADDR_WIDTH -1 : 0 ] bias_ld_addr; + wire bias_ld_addr_v; + wire [ ADDR_WIDTH -1 : 0 ] bias_st_addr; + wire bias_st_addr_v; + // Address - OBUF + wire [ OBUF_ADDR_WIDTH -1 : 0 ] obuf_rd_addr; + wire obuf_rd_addr_v; + wire [ OBUF_ADDR_WIDTH -1 : 0 ] obuf_wr_addr; + wire obuf_wr_addr_v; + // Address - IBUF + wire [ IBUF_ADDR_WIDTH -1 : 0 ] ibuf_rd_addr; + wire ibuf_rd_addr_v; + wire [ IBUF_ADDR_WIDTH -1 : 0 ] ibuf_wr_addr; + wire ibuf_wr_addr_v; + // Address - WBUF + wire [ WBUF_ADDR_WIDTH -1 : 0 ] wbuf_rd_addr; + wire wbuf_rd_addr_v; + wire [ WBUF_ADDR_WIDTH -1 : 0 ] wbuf_wr_addr; + wire wbuf_wr_addr_v; + // Select logic for bias (0) or obuf_read_data (1) + wire compute_bias_prev_sw; + wire tag_bias_prev_sw; + wire tag_ddr_pe_sw; + + // IBUF + wire [ IBUF_DATA_WIDTH -1 : 0 ] ibuf_read_data; + wire ibuf_read_req; + wire [ IBUF_ADDR_WIDTH -1 : 0 ] ibuf_read_addr; + + // WBUF + wire [ WBUF_DATA_WIDTH -1 : 0 ] wbuf_read_data; + wire wbuf_read_req; + wire [ WBUF_ADDR_WIDTH -1 : 0 ] wbuf_read_addr; + + // BIAS + wire [ BBUF_DATA_WIDTH -1 : 0 ] bbuf_read_data; + wire bias_read_req; + wire [ BBUF_ADDR_WIDTH -1 : 0 ] bias_read_addr; + wire sys_bias_read_req; + wire [ BBUF_ADDR_WIDTH -1 : 0 ] sys_bias_read_addr; + + // OBUF + wire [ OBUF_DATA_WIDTH -1 : 0 ] obuf_write_data; + wire obuf_write_req; + wire [ OBUF_ADDR_WIDTH -1 : 0 ] obuf_write_addr; + wire [ OBUF_DATA_WIDTH -1 : 0 ] obuf_read_data; + wire obuf_read_req; + wire [ OBUF_ADDR_WIDTH -1 : 0 ] obuf_read_addr; + + wire sys_obuf_write_req; + wire [ OBUF_ADDR_WIDTH -1 : 0 ] sys_obuf_write_addr; + + wire sys_obuf_read_req; + wire [ OBUF_ADDR_WIDTH -1 : 0 ] sys_obuf_read_addr; + + // Slave registers + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg0_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg0_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg1_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg1_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg2_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg2_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg3_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg3_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg4_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg4_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg5_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg5_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg6_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg6_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg7_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg7_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg8_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg8_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg9_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg9_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg10_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg10_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg11_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg11_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg12_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg12_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg13_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg13_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg14_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg14_out; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg15_in; + wire [ CTRL_DATA_WIDTH -1 : 0 ] slv_reg15_out; + // Slave registers end + + + wire [ IMEM_ADDR_W -1 : 0 ] start_addr; + + reg [ STATE_W -1 : 0 ] w_state_q; + reg [ STATE_W -1 : 0 ] w_state_d; + + reg [ STATE_W -1 : 0 ] r_state_q; + reg [ STATE_W -1 : 0 ] r_state_d; + + reg [ AXI_ADDR_WIDTH -1 : 0 ] w_addr_d; + reg [ AXI_ADDR_WIDTH -1 : 0 ] w_addr_q; + + wire imem_read_req_a; + wire [ IMEM_ADDR_W -1 : 0 ] imem_read_addr_a; + wire [ INST_DATA_WIDTH -1 : 0 ] imem_read_data_a; + + wire imem_write_req_a; + wire [ IMEM_ADDR_W -1 : 0 ] imem_write_addr_a; + wire [ INST_DATA_WIDTH -1 : 0 ] imem_write_data_a; + + wire imem_read_req_b; + wire [ IMEM_ADDR_W -1 : 0 ] imem_read_addr_b; + wire [ INST_DATA_WIDTH -1 : 0 ] imem_read_data_b; + + wire ibuf_tag_ready; + wire ibuf_tag_done; + wire ibuf_compute_ready; + + wire wbuf_tag_ready; + wire wbuf_tag_done; + wire wbuf_compute_ready; + + wire obuf_tag_ready; + wire obuf_tag_done; + wire obuf_compute_ready; + wire obuf_bias_prev_sw; + + wire bias_tag_ready; + wire bias_tag_done; + wire bias_compute_ready; + + wire tag_flush; + wire tag_req; + wire ibuf_tag_reuse; + wire obuf_tag_reuse; + wire wbuf_tag_reuse; + wire bias_tag_reuse; + wire sync_tag_req; + wire tag_ready; + + wire compute_done; + wire compute_req; + + wire [ IBUF_ADDR_WIDTH -1 : 0 ] tie_ibuf_buf_base_addr; + wire [ WBUF_ADDR_WIDTH -1 : 0 ] tie_wbuf_buf_base_addr; + wire [ OBUF_ADDR_WIDTH -1 : 0 ] tie_obuf_buf_base_addr; + wire [ BBUF_ADDR_WIDTH -1 : 0 ] tie_bias_buf_base_addr; + + wire sys_array_c_sel; +//============================================================= + +//============================================================= +// Assigns +//============================================================= + // TODO: bias tag handling + // Use the bias tag ready when obuf not needed + assign compute_req = ibuf_compute_ready && wbuf_compute_ready && obuf_compute_ready && bias_compute_ready; + assign tag_ready = (ibuf_tag_ready && wbuf_tag_ready && obuf_tag_ready && bias_tag_ready); + + // ST tie-offs + assign wbuf_st_addr_v = 1'b0; + assign wbuf_st_addr = 'b0; + assign bias_st_addr_v = 1'b0; + assign bias_st_addr = 'b0; + + // Address tie-off + assign tie_ibuf_buf_base_addr = {IBUF_ADDR_WIDTH{1'b0}}; + assign tie_wbuf_buf_base_addr = {WBUF_ADDR_WIDTH{1'b0}}; + assign tie_obuf_buf_base_addr = {OBUF_ADDR_WIDTH{1'b0}}; + assign tie_bias_buf_base_addr = {BBUF_ADDR_WIDTH{1'b0}}; + + // Buf write port tie-offs + + // Systolic array + assign acc_clear = compute_done; + + // Synchronize tag req + assign sync_tag_req = tag_req && ibuf_tag_ready && wbuf_tag_ready && obuf_tag_ready && bias_tag_ready; + + // Snoop + assign snoop_cl_ddr0_araddr = cl_ddr0_araddr; + assign snoop_cl_ddr1_araddr = cl_ddr1_araddr; + assign snoop_cl_ddr1_awaddr = cl_ddr1_awaddr; + assign snoop_cl_ddr2_araddr = cl_ddr2_araddr; + assign snoop_cl_ddr3_araddr = cl_ddr3_araddr; + assign snoop_cl_ddr4_araddr = cl_ddr4_araddr; + assign snoop_cl_ddr4_awaddr = cl_ddr4_awaddr; + +//============================================================= + +//============================================================= +// Base controller +// This module is in charge of the outer loops [16 - 31] +//============================================================= + controller #( + .CTRL_ADDR_WIDTH ( CTRL_ADDR_WIDTH ), + .CTRL_DATA_WIDTH ( CTRL_DATA_WIDTH ), + .INST_ADDR_WIDTH ( INST_ADDR_WIDTH ) + ) u_ctrl ( + .clk ( clk ), //input + .reset ( reset ), //input + + .tag_flush ( tag_flush ), //output + .tag_req ( tag_req ), //output + .tag_ready ( tag_ready ), //input + + .compute_done ( compute_done ), //input + .pu_compute_start ( pu_compute_start ), //input + .pu_compute_done ( pu_compute_done ), //input + .pu_write_done ( pu_write_done ), //input + .pu_ctrl_state ( pu_ctrl_state ), //input + + //DEBUG + .obuf_ld_stream_read_count ( obuf_ld_stream_read_count ), //input + .obuf_ld_stream_write_count ( obuf_ld_stream_write_count ), //input + .ddr_st_stream_read_count ( ddr_st_stream_read_count ), //input + .ddr_st_stream_write_count ( ddr_st_stream_write_count ), //input + .ld0_stream_counts ( ld0_stream_counts ), //output + .ld1_stream_counts ( ld1_stream_counts ), //output + .axi_wr_fifo_counts ( axi_wr_fifo_counts ), //output + //DEBUG + + .ibuf_tag_reuse ( ibuf_tag_reuse ), //output + .obuf_tag_reuse ( obuf_tag_reuse ), //output + .wbuf_tag_reuse ( wbuf_tag_reuse ), //output + .bias_tag_reuse ( bias_tag_reuse ), //output + + .ibuf_tag_done ( ibuf_tag_done ), //input + .wbuf_tag_done ( wbuf_tag_done ), //input + .obuf_tag_done ( obuf_tag_done ), //input + .bias_tag_done ( bias_tag_done ), //input + + .tag_bias_prev_sw ( tag_bias_prev_sw ), //output + .tag_ddr_pe_sw ( tag_ddr_pe_sw ), //output + .bias_ld_addr ( bias_ld_addr ), //output + .bias_ld_addr_v ( bias_ld_addr_v ), //output + .ibuf_ld_addr ( ibuf_ld_addr ), //output + .ibuf_ld_addr_v ( ibuf_ld_addr_v ), //output + .wbuf_ld_addr ( wbuf_ld_addr ), //output + .wbuf_ld_addr_v ( wbuf_ld_addr_v ), //output + .obuf_ld_addr ( obuf_ld_addr ), //output + .obuf_ld_addr_v ( obuf_ld_addr_v ), //output + .obuf_st_addr ( obuf_st_addr ), //output + .obuf_st_addr_v ( obuf_st_addr_v ), //output + + .stmem_state ( stmem_state ), //input + .stmem_tag ( stmem_tag ), //input + .stmem_ddr_pe_sw ( stmem_ddr_pe_sw ), //input + + .pci_cl_ctrl_awvalid ( pci_cl_ctrl_awvalid ), //input + .pci_cl_ctrl_awaddr ( pci_cl_ctrl_awaddr ), //input + .pci_cl_ctrl_awready ( pci_cl_ctrl_awready ), //output + .pci_cl_ctrl_wvalid ( pci_cl_ctrl_wvalid ), //input + .pci_cl_ctrl_wdata ( pci_cl_ctrl_wdata ), //input + .pci_cl_ctrl_wstrb ( pci_cl_ctrl_wstrb ), //input + .pci_cl_ctrl_wready ( pci_cl_ctrl_wready ), //output + .pci_cl_ctrl_bvalid ( pci_cl_ctrl_bvalid ), //output + .pci_cl_ctrl_bresp ( pci_cl_ctrl_bresp ), //output + .pci_cl_ctrl_bready ( pci_cl_ctrl_bready ), //input + .pci_cl_ctrl_arvalid ( pci_cl_ctrl_arvalid ), //input + .pci_cl_ctrl_araddr ( pci_cl_ctrl_araddr ), //input + .pci_cl_ctrl_arready ( pci_cl_ctrl_arready ), //output + .pci_cl_ctrl_rvalid ( pci_cl_ctrl_rvalid ), //output + .pci_cl_ctrl_rdata ( pci_cl_ctrl_rdata ), //output + .pci_cl_ctrl_rresp ( pci_cl_ctrl_rresp ), //output + .pci_cl_ctrl_rready ( pci_cl_ctrl_rready ), //input + + .pci_cl_data_awaddr ( pci_cl_data_awaddr ), //input + .pci_cl_data_awlen ( pci_cl_data_awlen ), //input + .pci_cl_data_awsize ( pci_cl_data_awsize ), //input + .pci_cl_data_awburst ( pci_cl_data_awburst ), //input + .pci_cl_data_awvalid ( pci_cl_data_awvalid ), //input + .pci_cl_data_awready ( pci_cl_data_awready ), //output + .pci_cl_data_wdata ( pci_cl_data_wdata ), //input + .pci_cl_data_wstrb ( pci_cl_data_wstrb ), //input + .pci_cl_data_wlast ( pci_cl_data_wlast ), //input + .pci_cl_data_wvalid ( pci_cl_data_wvalid ), //input + .pci_cl_data_wready ( pci_cl_data_wready ), //output + .pci_cl_data_bresp ( pci_cl_data_bresp ), //output + .pci_cl_data_bvalid ( pci_cl_data_bvalid ), //output + .pci_cl_data_bready ( pci_cl_data_bready ), //input + .pci_cl_data_araddr ( pci_cl_data_araddr ), //input + .pci_cl_data_arlen ( pci_cl_data_arlen ), //input + .pci_cl_data_arsize ( pci_cl_data_arsize ), //input + .pci_cl_data_arburst ( pci_cl_data_arburst ), //input + .pci_cl_data_arvalid ( pci_cl_data_arvalid ), //input + .pci_cl_data_arready ( pci_cl_data_arready ), //output + .pci_cl_data_rdata ( pci_cl_data_rdata ), //output + .pci_cl_data_rresp ( pci_cl_data_rresp ), //output + .pci_cl_data_rlast ( pci_cl_data_rlast ), //output + .pci_cl_data_rvalid ( pci_cl_data_rvalid ), //output + .pci_cl_data_rready ( pci_cl_data_rready ), //input + + .ibuf_compute_ready ( ibuf_compute_ready ), //input + .wbuf_compute_ready ( wbuf_compute_ready ), //input + .obuf_compute_ready ( obuf_compute_ready ), //input + .bias_compute_ready ( bias_compute_ready ), //input + + .cfg_loop_iter ( cfg_loop_iter ), //output + .cfg_loop_iter_loop_id ( cfg_loop_iter_loop_id ), //output + .cfg_loop_iter_v ( cfg_loop_iter_v ), //output + .cfg_loop_stride ( cfg_loop_stride ), //output + .cfg_loop_stride_v ( cfg_loop_stride_v ), //output + .cfg_loop_stride_id ( cfg_loop_stride_id ), //output + .cfg_loop_stride_type ( cfg_loop_stride_type ), //output + .cfg_loop_stride_loop_id ( cfg_loop_stride_loop_id ), //output + .cfg_mem_req_size ( cfg_mem_req_size ), //output + .cfg_mem_req_v ( cfg_mem_req_v ), //output + .cfg_mem_req_type ( cfg_mem_req_type ), //output + .cfg_mem_req_id ( cfg_mem_req_id ), //output + .cfg_mem_req_loop_id ( cfg_mem_req_loop_id ), //output + .cfg_buf_req_size ( cfg_buf_req_size ), //output + .cfg_buf_req_v ( cfg_buf_req_v ), //output + .cfg_buf_req_type ( cfg_buf_req_type ), //output + .cfg_buf_req_loop_id ( cfg_buf_req_loop_id ), //output + + .cfg_pu_inst ( cfg_pu_inst ), //output + .cfg_pu_inst_v ( cfg_pu_inst_v ), //output + .pu_block_start ( pu_block_start ), //output + + .snoop_cl_ddr0_araddr ( snoop_cl_ddr0_araddr ), //input + .snoop_cl_ddr0_arvalid ( cl_ddr0_arvalid ), //input + .snoop_cl_ddr0_arready ( cl_ddr0_arready ), //input + .snoop_cl_ddr0_arlen ( cl_ddr0_arlen ), //input + .snoop_cl_ddr0_rvalid ( cl_ddr0_rvalid ), //input + .snoop_cl_ddr0_rready ( cl_ddr0_rready ), //input + + .snoop_cl_ddr1_awaddr ( snoop_cl_ddr1_awaddr ), //input + .snoop_cl_ddr1_awvalid ( cl_ddr1_awvalid ), //input + .snoop_cl_ddr1_awready ( cl_ddr1_awready ), //input + .snoop_cl_ddr1_awlen ( cl_ddr1_awlen ), //input + .snoop_cl_ddr1_araddr ( snoop_cl_ddr1_araddr ), //input + .snoop_cl_ddr1_arvalid ( cl_ddr1_arvalid ), //input + .snoop_cl_ddr1_arready ( cl_ddr1_arready ), //input + .snoop_cl_ddr1_arlen ( cl_ddr1_arlen ), //input + .snoop_cl_ddr1_wvalid ( cl_ddr1_wvalid ), //input + .snoop_cl_ddr1_wready ( cl_ddr1_wready ), //input + .snoop_cl_ddr1_rvalid ( cl_ddr1_rvalid ), //input + .snoop_cl_ddr1_rready ( cl_ddr1_rready ), //input + + .snoop_cl_ddr2_araddr ( snoop_cl_ddr2_araddr ), //input + .snoop_cl_ddr2_arvalid ( cl_ddr2_arvalid ), //input + .snoop_cl_ddr2_arready ( cl_ddr2_arready ), //input + .snoop_cl_ddr2_arlen ( cl_ddr2_arlen ), //input + .snoop_cl_ddr2_rvalid ( cl_ddr2_rvalid ), //input + .snoop_cl_ddr2_rready ( cl_ddr2_rready ), //input + + .snoop_cl_ddr3_araddr ( snoop_cl_ddr3_araddr ), //input + .snoop_cl_ddr3_arvalid ( cl_ddr3_arvalid ), //input + .snoop_cl_ddr3_arready ( cl_ddr3_arready ), //input + .snoop_cl_ddr3_arlen ( cl_ddr3_arlen ), //input + .snoop_cl_ddr3_rvalid ( cl_ddr3_rvalid ), //input + .snoop_cl_ddr3_rready ( cl_ddr3_rready ), //input + + .snoop_cl_ddr4_awaddr ( snoop_cl_ddr4_awaddr ), //input + .snoop_cl_ddr4_awvalid ( cl_ddr4_awvalid ), //input + .snoop_cl_ddr4_awready ( cl_ddr4_awready ), //input + .snoop_cl_ddr4_awlen ( cl_ddr4_awlen ), //input + .snoop_cl_ddr4_araddr ( snoop_cl_ddr4_araddr ), //input + .snoop_cl_ddr4_arvalid ( cl_ddr4_arvalid ), //input + .snoop_cl_ddr4_arready ( cl_ddr4_arready ), //input + .snoop_cl_ddr4_arlen ( cl_ddr4_arlen ), //input + .snoop_cl_ddr4_wvalid ( cl_ddr4_wvalid ), //input + .snoop_cl_ddr4_wready ( cl_ddr4_wready ), //input + .snoop_cl_ddr4_rvalid ( cl_ddr4_rvalid ), //input + .snoop_cl_ddr4_rready ( cl_ddr4_rready ), //input + + .ld_obuf_req ( ld_obuf_req ), //input + .ld_obuf_ready ( ld_obuf_ready ) //input + + ); +//============================================================= + +//============================================================= +// Compute controller +// This module is in charge of the compute loops [0 - 15] +//============================================================= + assign cfg_loop_stride_lo = cfg_loop_stride; + base_addr_gen #( + .BASE_ID ( 0 ), + .MEM_REQ_W ( MEM_REQ_W ), + .IBUF_ADDR_WIDTH ( IBUF_ADDR_WIDTH ), + .WBUF_ADDR_WIDTH ( WBUF_ADDR_WIDTH ), + .OBUF_ADDR_WIDTH ( OBUF_ADDR_WIDTH ), + .BBUF_ADDR_WIDTH ( BBUF_ADDR_WIDTH ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) compute_ctrl ( + .clk ( clk ), //input + .reset ( reset ), //input + + .start ( compute_req ), //input + .done ( compute_done ), //output + + //TODO + .tag_req ( ), //output + .tag_ready ( 1'b1 ), //input + + .cfg_loop_iter_v ( cfg_loop_iter_v ), //input + .cfg_loop_iter ( cfg_loop_iter ), //input + .cfg_loop_iter_loop_id ( cfg_loop_iter_loop_id ), //input + + .cfg_loop_stride_v ( cfg_loop_stride_v ), //input + .cfg_loop_stride ( cfg_loop_stride_lo ), //input + .cfg_loop_stride_loop_id ( cfg_loop_stride_loop_id ), //input + .cfg_loop_stride_type ( cfg_loop_stride_type ), //input + .cfg_loop_stride_id ( cfg_loop_stride_id ), //input + + .ibuf_base_addr ( tie_ibuf_buf_base_addr ), //input + .wbuf_base_addr ( tie_wbuf_buf_base_addr ), //input + .obuf_base_addr ( tie_obuf_buf_base_addr ), //input + .bias_base_addr ( tie_bias_buf_base_addr ), //input + + .obuf_ld_addr ( obuf_read_addr ), //output + .obuf_ld_addr_v ( obuf_read_req ), //output + .obuf_st_addr ( obuf_write_addr ), //output + .obuf_st_addr_v ( obuf_write_req ), //output + .ibuf_ld_addr ( ibuf_read_addr ), //output + .ibuf_ld_addr_v ( ibuf_read_req ), //output + .wbuf_ld_addr ( wbuf_read_addr ), //output + .wbuf_ld_addr_v ( wbuf_read_req ), //output + + .bias_ld_addr ( bias_read_addr ), //output + .bias_ld_addr_v ( bias_read_req ), //output + + .bias_prev_sw ( rd_bias_prev_sw ), //output + .ddr_pe_sw ( ) //output + ); +//============================================================= + +//============================================================= +// 4x Memory wrappers - IBUF, WBUF, OBUF, Bias +//============================================================= + ibuf_mem_wrapper #( + // Internal Parameters + .AXI_DATA_WIDTH ( IBUF_AXI_DATA_WIDTH ), + .AXI_BURST_WIDTH ( AXI_BURST_WIDTH ), + .MEM_ID ( 0 ), + .NUM_TAGS ( NUM_TAGS ), + .ARRAY_N ( ARRAY_N ), + .DATA_WIDTH ( DATA_WIDTH ), + .MEM_REQ_W ( MEM_REQ_W ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .BUF_ADDR_W ( IBUF_ADDR_WIDTH ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) ibuf_mem ( + .clk ( clk ), //input + .reset ( reset ), //input + + .compute_done ( compute_done ), //input + .compute_ready ( ibuf_compute_ready ), //input + .compute_bias_prev_sw ( ), //output + + .block_done ( tag_flush ), //input + .tag_req ( sync_tag_req ), //input + .tag_reuse ( ibuf_tag_reuse ), //input + .tag_bias_prev_sw ( tag_bias_prev_sw ), //input + .tag_ddr_pe_sw ( tag_ddr_pe_sw ), //input + .tag_ready ( ibuf_tag_ready ), //output + .tag_done ( ibuf_tag_done ), //output + + .tag_base_ld_addr ( ibuf_ld_addr ), //input + + .cfg_loop_iter_v ( cfg_loop_iter_v ), //input + .cfg_loop_iter ( cfg_loop_iter ), //input + .cfg_loop_iter_loop_id ( cfg_loop_iter_loop_id ), //input + + .cfg_loop_stride_v ( cfg_loop_stride_v ), //input + .cfg_loop_stride ( cfg_loop_stride ), //input + .cfg_loop_stride_loop_id ( cfg_loop_stride_loop_id ), //input + .cfg_loop_stride_type ( cfg_loop_stride_type ), //input + .cfg_loop_stride_id ( cfg_loop_stride_id ), //input + + .cfg_mem_req_v ( cfg_mem_req_v ), + .cfg_mem_req_size ( cfg_mem_req_size ), + .cfg_mem_req_type ( cfg_mem_req_type ), // 0: RD, 1:WR + .cfg_mem_req_id ( cfg_mem_req_id ), // specify which scratchpad + .cfg_mem_req_loop_id ( cfg_mem_req_loop_id ), // specify which loop + + .buf_read_data ( ibuf_read_data ), + .buf_read_req ( ibuf_read_req ), + .buf_read_addr ( ibuf_read_addr ), + + .mws_awaddr ( cl_ddr0_awaddr ), + .mws_awlen ( cl_ddr0_awlen ), + .mws_awsize ( cl_ddr0_awsize ), + .mws_awburst ( cl_ddr0_awburst ), + .mws_awvalid ( cl_ddr0_awvalid ), + .mws_awready ( cl_ddr0_awready ), + .mws_wdata ( cl_ddr0_wdata ), + .mws_wstrb ( cl_ddr0_wstrb ), + .mws_wlast ( cl_ddr0_wlast ), + .mws_wvalid ( cl_ddr0_wvalid ), + .mws_wready ( cl_ddr0_wready ), + .mws_bresp ( cl_ddr0_bresp ), + .mws_bvalid ( cl_ddr0_bvalid ), + .mws_bready ( cl_ddr0_bready ), + .mws_araddr ( cl_ddr0_araddr ), + .mws_arid ( cl_ddr0_arid ), + .mws_arlen ( cl_ddr0_arlen ), + .mws_arsize ( cl_ddr0_arsize ), + .mws_arburst ( cl_ddr0_arburst ), + .mws_arvalid ( cl_ddr0_arvalid ), + .mws_arready ( cl_ddr0_arready ), + .mws_rdata ( cl_ddr0_rdata ), + .mws_rid ( cl_ddr0_rid ), + .mws_rresp ( cl_ddr0_rresp ), + .mws_rlast ( cl_ddr0_rlast ), + .mws_rvalid ( cl_ddr0_rvalid ), + .mws_rready ( cl_ddr0_rready ) + ); + + wbuf_mem_wrapper #( + // Internal Parameters + .AXI_DATA_WIDTH ( WBUF_AXI_DATA_WIDTH ), + .AXI_BURST_WIDTH ( AXI_BURST_WIDTH ), + .MEM_ID ( 2 ), + .NUM_TAGS ( NUM_TAGS ), + .ARRAY_N ( ARRAY_N ), + .DATA_WIDTH ( DATA_WIDTH ), + .MEM_REQ_W ( MEM_REQ_W ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .BUF_ADDR_W ( WBUF_ADDR_WIDTH ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) wbuf_mem ( + .clk ( clk ), //input + .reset ( reset ), //input + + .compute_done ( compute_done ), //input + .compute_ready ( wbuf_compute_ready ), //input + .compute_bias_prev_sw ( ), //output + .block_done ( tag_flush ), //input + .tag_req ( sync_tag_req ), //input + .tag_reuse ( wbuf_tag_reuse ), //input + .tag_bias_prev_sw ( tag_bias_prev_sw ), //input + .tag_ddr_pe_sw ( tag_ddr_pe_sw ), //input + .tag_ready ( wbuf_tag_ready ), //output + .tag_done ( wbuf_tag_done ), //output + + .tag_base_ld_addr ( wbuf_ld_addr ), //input + + .cfg_loop_iter_v ( cfg_loop_iter_v ), //input + .cfg_loop_iter ( cfg_loop_iter ), //input + .cfg_loop_iter_loop_id ( cfg_loop_iter_loop_id ), //input + + .cfg_loop_stride_v ( cfg_loop_stride_v ), //input + .cfg_loop_stride ( cfg_loop_stride ), //input + .cfg_loop_stride_loop_id ( cfg_loop_stride_loop_id ), //input + .cfg_loop_stride_type ( cfg_loop_stride_type ), //input + .cfg_loop_stride_id ( cfg_loop_stride_id ), //input + + .cfg_mem_req_v ( cfg_mem_req_v ), + .cfg_mem_req_size ( cfg_mem_req_size ), + .cfg_mem_req_type ( cfg_mem_req_type ), // 0: RD, 1:WR + .cfg_mem_req_id ( cfg_mem_req_id ), // specify which scratchpad + .cfg_mem_req_loop_id ( cfg_mem_req_loop_id ), // specify which loop + + .buf_read_data ( wbuf_read_data ), + .buf_read_req ( wbuf_read_req ), + .buf_read_addr ( wbuf_read_addr ), + + .mws_awaddr ( cl_ddr2_awaddr ), + .mws_awlen ( cl_ddr2_awlen ), + .mws_awsize ( cl_ddr2_awsize ), + .mws_awburst ( cl_ddr2_awburst ), + .mws_awvalid ( cl_ddr2_awvalid ), + .mws_awready ( cl_ddr2_awready ), + .mws_wdata ( cl_ddr2_wdata ), + .mws_wstrb ( cl_ddr2_wstrb ), + .mws_wlast ( cl_ddr2_wlast ), + .mws_wvalid ( cl_ddr2_wvalid ), + .mws_wready ( cl_ddr2_wready ), + .mws_bresp ( cl_ddr2_bresp ), + .mws_bvalid ( cl_ddr2_bvalid ), + .mws_bready ( cl_ddr2_bready ), + .mws_araddr ( cl_ddr2_araddr ), + .mws_arid ( cl_ddr2_arid ), + .mws_arlen ( cl_ddr2_arlen ), + .mws_arsize ( cl_ddr2_arsize ), + .mws_arburst ( cl_ddr2_arburst ), + .mws_arvalid ( cl_ddr2_arvalid ), + .mws_arready ( cl_ddr2_arready ), + .mws_rdata ( cl_ddr2_rdata ), + .mws_rid ( cl_ddr2_rid ), + .mws_rresp ( cl_ddr2_rresp ), + .mws_rlast ( cl_ddr2_rlast ), + .mws_rvalid ( cl_ddr2_rvalid ), + .mws_rready ( cl_ddr2_rready ) + ); + + obuf_mem_wrapper #( + // Internal Parameters + .AXI_DATA_WIDTH ( OBUF_AXI_DATA_WIDTH ), + .AXI_BURST_WIDTH ( AXI_BURST_WIDTH ), + .MEM_ID ( 1 ), + .NUM_TAGS ( NUM_TAGS ), + .ARRAY_N ( ARRAY_N ), + .ARRAY_M ( ARRAY_M ), + .DATA_WIDTH ( 64 ), + .MEM_REQ_W ( MEM_REQ_W ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .BUF_ADDR_W ( OBUF_ADDR_WIDTH ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) obuf_mem ( + .clk ( clk ), //input + .reset ( reset ), //input + + .compute_done ( compute_done ), //input + .compute_ready ( obuf_compute_ready ), //output + .compute_bias_prev_sw ( obuf_bias_prev_sw ), //output + .block_done ( tag_flush ), //input + .tag_req ( sync_tag_req ), //input + .tag_reuse ( obuf_tag_reuse ), //input + .tag_bias_prev_sw ( tag_bias_prev_sw ), //input + .tag_ddr_pe_sw ( tag_ddr_pe_sw ), //input + .tag_ready ( obuf_tag_ready ), //output + .tag_done ( obuf_tag_done ), //output + + .tag_base_ld_addr ( obuf_ld_addr ), //input + .tag_base_st_addr ( obuf_st_addr ), //input + + .cfg_loop_iter_v ( cfg_loop_iter_v ), //input + .cfg_loop_iter ( cfg_loop_iter ), //input + .cfg_loop_iter_loop_id ( cfg_loop_iter_loop_id ), //input + + .cfg_loop_stride_v ( cfg_loop_stride_v ), //input + .cfg_loop_stride ( cfg_loop_stride ), //input + .cfg_loop_stride_loop_id ( cfg_loop_stride_loop_id ), //input + .cfg_loop_stride_type ( cfg_loop_stride_type ), //input + .cfg_loop_stride_id ( cfg_loop_stride_id ), //input + + .cfg_mem_req_v ( cfg_mem_req_v ), + .cfg_mem_req_size ( cfg_mem_req_size ), + .cfg_mem_req_type ( cfg_mem_req_type ), // 0: RD, 1:WR + .cfg_mem_req_id ( cfg_mem_req_id ), // specify which scratchpad + .cfg_mem_req_loop_id ( cfg_mem_req_loop_id ), // specify which loop + + .buf_write_data ( obuf_write_data ), + .buf_write_req ( sys_obuf_write_req ), + .buf_write_addr ( sys_obuf_write_addr ), + .buf_read_data ( obuf_read_data ), + .buf_read_req ( sys_obuf_read_req ), + .buf_read_addr ( sys_obuf_read_addr ), + + .pu_buf_read_ready ( ld_obuf_ready ), + .pu_buf_read_req ( ld_obuf_req ), + .pu_buf_read_addr ( ld_obuf_addr ), + + .pu_compute_start ( pu_compute_start ), //output + .pu_compute_done ( pu_compute_done ), //input + .pu_compute_ready ( pu_compute_ready ), //input + + .obuf_ld_stream_write_req ( obuf_ld_stream_write_req ), + .obuf_ld_stream_write_data ( obuf_ld_stream_write_data ), + + .stmem_state ( stmem_state ), //output + .stmem_tag ( stmem_tag ), //output + .stmem_ddr_pe_sw ( stmem_ddr_pe_sw ), //output + + .mws_awaddr ( cl_ddr1_awaddr ), + .mws_awlen ( cl_ddr1_awlen ), + .mws_awsize ( cl_ddr1_awsize ), + .mws_awburst ( cl_ddr1_awburst ), + .mws_awvalid ( cl_ddr1_awvalid ), + .mws_awready ( cl_ddr1_awready ), + .mws_wdata ( cl_ddr1_wdata ), + .mws_wstrb ( cl_ddr1_wstrb ), + .mws_wlast ( cl_ddr1_wlast ), + .mws_wvalid ( cl_ddr1_wvalid ), + .mws_wready ( cl_ddr1_wready ), + .mws_bresp ( cl_ddr1_bresp ), + .mws_bvalid ( cl_ddr1_bvalid ), + .mws_bready ( cl_ddr1_bready ), + .mws_araddr ( cl_ddr1_araddr ), + .mws_arid ( cl_ddr1_arid ), + .mws_arlen ( cl_ddr1_arlen ), + .mws_arsize ( cl_ddr1_arsize ), + .mws_arburst ( cl_ddr1_arburst ), + .mws_arvalid ( cl_ddr1_arvalid ), + .mws_arready ( cl_ddr1_arready ), + .mws_rdata ( cl_ddr1_rdata ), + .mws_rid ( cl_ddr1_rid ), + .mws_rresp ( cl_ddr1_rresp ), + .mws_rlast ( cl_ddr1_rlast ), + .mws_rvalid ( cl_ddr1_rvalid ), + .mws_rready ( cl_ddr1_rready ) + ); + + bbuf_mem_wrapper #( + // Internal Parameters + .AXI_DATA_WIDTH ( BBUF_AXI_DATA_WIDTH ), + .AXI_BURST_WIDTH ( AXI_BURST_WIDTH ), + .MEM_ID ( 3 ), + .NUM_TAGS ( NUM_TAGS ), + .ARRAY_N ( ARRAY_N ), + .ARRAY_M ( ARRAY_M ), + .DATA_WIDTH ( 32 ), + .MEM_REQ_W ( MEM_REQ_W ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .BUF_ADDR_W ( BBUF_ADDR_WIDTH ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) bbuf_mem ( + .clk ( clk ), //input + .reset ( reset ), //input + + .compute_done ( compute_done ), //input + .compute_ready ( bias_compute_ready ), //input + .compute_bias_prev_sw ( ), //output + .block_done ( tag_flush ), //input + .tag_req ( sync_tag_req ), //input + .tag_reuse ( bias_tag_reuse ), //input + .tag_bias_prev_sw ( tag_bias_prev_sw ), //input + .tag_ddr_pe_sw ( tag_ddr_pe_sw ), //input + .tag_ready ( bias_tag_ready ), //output + .tag_done ( bias_tag_done ), //output + + .tag_base_ld_addr ( bias_ld_addr ), //input + + .cfg_loop_iter_v ( cfg_loop_iter_v ), //input + .cfg_loop_iter ( cfg_loop_iter ), //input + .cfg_loop_iter_loop_id ( cfg_loop_iter_loop_id ), //input + + .cfg_loop_stride_v ( cfg_loop_stride_v ), //input + .cfg_loop_stride ( cfg_loop_stride ), //input + .cfg_loop_stride_loop_id ( cfg_loop_stride_loop_id ), //input + .cfg_loop_stride_type ( cfg_loop_stride_type ), //input + .cfg_loop_stride_id ( cfg_loop_stride_id ), //input + + .cfg_mem_req_v ( cfg_mem_req_v ), + .cfg_mem_req_size ( cfg_mem_req_size ), + .cfg_mem_req_type ( cfg_mem_req_type ), // 0: RD, 1:WR + .cfg_mem_req_id ( cfg_mem_req_id ), // specify which scratchpad + .cfg_mem_req_loop_id ( cfg_mem_req_loop_id ), // specify which loop + + .buf_read_data ( bbuf_read_data ), + .buf_read_req ( sys_bias_read_req ), + .buf_read_addr ( sys_bias_read_addr ), + + .mws_awaddr ( cl_ddr3_awaddr ), + .mws_awlen ( cl_ddr3_awlen ), + .mws_awsize ( cl_ddr3_awsize ), + .mws_awburst ( cl_ddr3_awburst ), + .mws_awvalid ( cl_ddr3_awvalid ), + .mws_awready ( cl_ddr3_awready ), + .mws_wdata ( cl_ddr3_wdata ), + .mws_wstrb ( cl_ddr3_wstrb ), + .mws_wlast ( cl_ddr3_wlast ), + .mws_wvalid ( cl_ddr3_wvalid ), + .mws_wready ( cl_ddr3_wready ), + .mws_bresp ( cl_ddr3_bresp ), + .mws_bvalid ( cl_ddr3_bvalid ), + .mws_bready ( cl_ddr3_bready ), + .mws_araddr ( cl_ddr3_araddr ), + .mws_arid ( cl_ddr3_arid ), + .mws_arlen ( cl_ddr3_arlen ), + .mws_arsize ( cl_ddr3_arsize ), + .mws_arburst ( cl_ddr3_arburst ), + .mws_arvalid ( cl_ddr3_arvalid ), + .mws_arready ( cl_ddr3_arready ), + .mws_rdata ( cl_ddr3_rdata ), + .mws_rid ( cl_ddr3_rid ), + .mws_rresp ( cl_ddr3_rresp ), + .mws_rlast ( cl_ddr3_rlast ), + .mws_rvalid ( cl_ddr3_rvalid ), + .mws_rready ( cl_ddr3_rready ) + ); +//============================================================= + +//============================================================= +// Systolic Array +//============================================================= + // Only select bias (0) if rd_bias_prev_sw == 0 and obuf_bias_prev_sw == 0; + assign sys_array_c_sel = rd_bias_prev_sw || obuf_bias_prev_sw; + systolic_array #( + .OBUF_ADDR_WIDTH ( OBUF_ADDR_WIDTH ), + .BBUF_ADDR_WIDTH ( BBUF_ADDR_WIDTH ), + .ACT_WIDTH ( DATA_WIDTH ), + .WGT_WIDTH ( DATA_WIDTH ), + .BIAS_WIDTH ( BIAS_WIDTH ), + .ACC_WIDTH ( ACC_WIDTH ), + .ARRAY_N ( ARRAY_N ), + .ARRAY_M ( ARRAY_M ) + ) sys_array ( + .clk ( clk ), + .reset ( reset ), + .acc_clear ( acc_clear ), + + .ibuf_read_data ( ibuf_read_data ), + + .wbuf_read_data ( wbuf_read_data ), + + .bbuf_read_data ( bbuf_read_data ), + .bias_read_req ( bias_read_req ), + .bias_read_addr ( bias_read_addr ), + .sys_bias_read_req ( sys_bias_read_req ), + .sys_bias_read_addr ( sys_bias_read_addr ), + .bias_prev_sw ( sys_array_c_sel ), + + .obuf_read_data ( obuf_read_data ), + .obuf_read_addr ( obuf_read_addr ), + .sys_obuf_read_req ( sys_obuf_read_req ), + .sys_obuf_read_addr ( sys_obuf_read_addr ), + .obuf_write_req ( obuf_write_req ), + .obuf_write_addr ( obuf_write_addr ), + .obuf_write_data ( sys_obuf_write_data ), + .sys_obuf_write_req ( sys_obuf_write_req ), + .sys_obuf_write_addr ( sys_obuf_write_addr ) + ); + + + wire [ 64 -1 : 0 ] obuf_out0; + wire [ 64 -1 : 0 ] obuf_out1; + wire [ 64 -1 : 0 ] obuf_out2; + wire [ 64 -1 : 0 ] obuf_out3; + + wire [ 64 -1 : 0 ] obuf_out4; + wire [ 64 -1 : 0 ] obuf_out5; + wire [ 64 -1 : 0 ] obuf_out6; + wire [ 64 -1 : 0 ] obuf_out7; + + wire [ 64 -1 : 0 ] obuf_in0; + wire [ 64 -1 : 0 ] obuf_in1; + wire [ 64 -1 : 0 ] obuf_in2; + wire [ 64 -1 : 0 ] obuf_in3; + + wire [ 32 -1 : 0 ] bias_in0; + wire [ 32 -1 : 0 ] bias_in1; + wire [ 32 -1 : 0 ] bias_in2; + wire [ 32 -1 : 0 ] bias_in3; + + wire [ 64 -1 : 0 ] obuf_mem_out0; + wire [ 64 -1 : 0 ] obuf_mem_out1; + + wire [ 16 -1 : 0 ] ibuf_in0; + wire [ 16 -1 : 0 ] ibuf_in1; + wire [ 16 -1 : 0 ] ibuf_in2; + wire [ 16 -1 : 0 ] ibuf_in3; + + wire [ 16 -1 : 0 ] ibuf_in4; + wire [ 16 -1 : 0 ] ibuf_in5; + wire [ 16 -1 : 0 ] ibuf_in6; + wire [ 16 -1 : 0 ] ibuf_in7; + + wire [ 16 -1 : 0 ] wbuf_in0; + wire [ 16 -1 : 0 ] wbuf_in1; + wire [ 16 -1 : 0 ] wbuf_in2; + wire [ 16 -1 : 0 ] wbuf_in3; + + wire [ 16 -1 : 0 ] wbuf_in4; + wire [ 16 -1 : 0 ] wbuf_in5; + wire [ 16 -1 : 0 ] wbuf_in6; + wire [ 16 -1 : 0 ] wbuf_in7; + + wire [ 16 -1 : 0 ] wbuf_in8; + wire [ 16 -1 : 0 ] wbuf_in9; + wire [ 16 -1 : 0 ] wbuf_in10; + wire [ 16 -1 : 0 ] wbuf_in11; + + wire [ 16 -1 : 0 ] wbuf_in12; + wire [ 16 -1 : 0 ] wbuf_in13; + wire [ 16 -1 : 0 ] wbuf_in14; + wire [ 16 -1 : 0 ] wbuf_in15; + + assign {obuf_out7,obuf_out6,obuf_out5,obuf_out4, + obuf_out3, obuf_out2, obuf_out1, obuf_out0} = sys_obuf_write_data; + assign {obuf_in3, obuf_in2, obuf_in1, obuf_in0} = obuf_read_data; + assign {bias_in3, bias_in2, bias_in1, bias_in0} = bbuf_read_data; + assign {obuf_mem_out1, obuf_mem_out0} = cl_ddr1_wdata; + + assign ibuf_in0 = ibuf_read_data[15:0]; + assign ibuf_in1 = ibuf_read_data[31:16]; + assign ibuf_in2 = ibuf_read_data[47:32]; + assign ibuf_in3 = ibuf_read_data[63:48]; + + assign ibuf_in4 = ibuf_read_data[79 :64]; + assign ibuf_in5 = ibuf_read_data[95 :80]; + assign ibuf_in6 = ibuf_read_data[111:96]; + assign ibuf_in7 = ibuf_read_data[127:112]; + + assign wbuf_in0 = wbuf_read_data[15:0]; + assign wbuf_in1 = wbuf_read_data[31:16]; + assign wbuf_in2 = wbuf_read_data[47:32]; + assign wbuf_in3 = wbuf_read_data[63:48]; + + assign wbuf_in4 = wbuf_read_data[79:64]; + assign wbuf_in5 = wbuf_read_data[95:80]; + assign wbuf_in6 = wbuf_read_data[111:96]; + assign wbuf_in7 = wbuf_read_data[127:112]; + + assign wbuf_in8 = wbuf_read_data[143:128]; + assign wbuf_in9 = wbuf_read_data[159:144]; + assign wbuf_in10 = wbuf_read_data[175:160]; + assign wbuf_in11 = wbuf_read_data[191:176]; + + assign wbuf_in12 = wbuf_read_data[207:192]; + assign wbuf_in13 = wbuf_read_data[223:208]; + assign wbuf_in14 = wbuf_read_data[239:224]; + assign wbuf_in15 = wbuf_read_data[255:240]; + + assign obuf_write_data = sys_obuf_write_data; +//============================================================= + +//============================================================= +// PU +//============================================================= + gen_pu #( + .INST_WIDTH ( INST_DATA_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .ACC_DATA_WIDTH ( 64 ), + .SIMD_LANES ( ARRAY_M ), + .OBUF_AXI_DATA_WIDTH ( OBUF_AXI_DATA_WIDTH ), + .AXI_DATA_WIDTH ( PU_AXI_DATA_WIDTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .OBUF_ADDR_WIDTH ( PU_OBUF_ADDR_WIDTH ), + .AXI_BURST_WIDTH ( AXI_BURST_WIDTH ) + ) u_pu + ( + .clk ( clk ), //input + .reset ( reset ), //input + .done ( pu_done ), //output + //DEBUG + .obuf_ld_stream_read_count ( obuf_ld_stream_read_count ), //output + .obuf_ld_stream_write_count ( obuf_ld_stream_write_count ), //output + .ddr_st_stream_read_count ( ddr_st_stream_read_count ), //output + .ddr_st_stream_write_count ( ddr_st_stream_write_count ), //output + .ld0_stream_counts ( ld0_stream_counts ), //output + .ld1_stream_counts ( ld1_stream_counts ), //output + .axi_wr_fifo_counts ( axi_wr_fifo_counts ), //output + //DEBUG + .pu_ctrl_state ( pu_ctrl_state ), //output + .obuf_ld_stream_write_req ( obuf_ld_stream_write_req ), //input + .obuf_ld_stream_write_data ( obuf_ld_stream_write_data ), //input + .inst_wr_req ( cfg_pu_inst_v ), //input + .inst_wr_data ( cfg_pu_inst ), //input + .pu_block_start ( pu_block_start ), //input + .pu_compute_start ( pu_compute_start ), //input + .pu_compute_ready ( pu_compute_ready ), //output + .pu_compute_done ( pu_compute_done ), //output + .pu_write_done ( pu_write_done ), //output + .inst_wr_ready ( pu_inst_wr_ready ), //output + .ld_obuf_req ( ld_obuf_req ), //output + .ld_obuf_addr ( ld_obuf_addr ), //output + .ld_obuf_ready ( ld_obuf_ready ), //input + .pu_ddr_awaddr ( cl_ddr4_awaddr ), //output + .pu_ddr_awlen ( cl_ddr4_awlen ), //output + .pu_ddr_awsize ( cl_ddr4_awsize ), //output + .pu_ddr_awburst ( cl_ddr4_awburst ), //output + .pu_ddr_awvalid ( cl_ddr4_awvalid ), //output + .pu_ddr_awready ( cl_ddr4_awready ), //input + .pu_ddr_wdata ( cl_ddr4_wdata ), //output + .pu_ddr_wstrb ( cl_ddr4_wstrb ), //output + .pu_ddr_wlast ( cl_ddr4_wlast ), //output + .pu_ddr_wvalid ( cl_ddr4_wvalid ), //output + .pu_ddr_wready ( cl_ddr4_wready ), //input + .pu_ddr_bresp ( cl_ddr4_bresp ), //input + .pu_ddr_bvalid ( cl_ddr4_bvalid ), //input + .pu_ddr_bready ( cl_ddr4_bready ), //output + .pu_ddr_araddr ( cl_ddr4_araddr ), //output + .pu_ddr_arid ( cl_ddr4_arid ), //output + .pu_ddr_arlen ( cl_ddr4_arlen ), //output + .pu_ddr_arsize ( cl_ddr4_arsize ), //output + .pu_ddr_arburst ( cl_ddr4_arburst ), //output + .pu_ddr_arvalid ( cl_ddr4_arvalid ), //output + .pu_ddr_arready ( cl_ddr4_arready ), //input + .pu_ddr_rdata ( cl_ddr4_rdata ), //input + .pu_ddr_rid ( cl_ddr4_rid ), //input + .pu_ddr_rresp ( cl_ddr4_rresp ), //input + .pu_ddr_rlast ( cl_ddr4_rlast ), //input + .pu_ddr_rvalid ( cl_ddr4_rvalid ), //input + .pu_ddr_rready ( cl_ddr4_rready ) //output + ); +//============================================================= + +//============================================================= +// VCD +//============================================================= + `ifdef COCOTB_TOPLEVEL_dnnweaver2_controller + initial begin + $dumpfile("dnnweaver2_controller.vcd"); + $dumpvars(0, dnnweaver2_controller); + end + `endif +//============================================================= + +endmodule + +// +// Banked RAM +// Allows simultaneous accesses for LD/ST and RD/WR instructions +// +// Hardik Sharma +// (hsharma@gatech.edu) +`timescale 1ns/1ps +module banked_ram +#( + parameter integer TAG_W = 2, + parameter integer NUM_TAGS = (1< DDR AXI4 interface + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] mws_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] mws_awlen, + output wire [ 3 -1 : 0 ] mws_awsize, + output wire [ 2 -1 : 0 ] mws_awburst, + output wire mws_awvalid, + input wire mws_awready, + // Master Interface Write Data + output wire [ AXI_DATA_WIDTH -1 : 0 ] mws_wdata, + output wire [ WSTRB_W -1 : 0 ] mws_wstrb, + output wire mws_wlast, + output wire mws_wvalid, + input wire mws_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] mws_bresp, + input wire mws_bvalid, + output wire mws_bready, + // Master Interface Read Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] mws_araddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] mws_arlen, + output wire [ 3 -1 : 0 ] mws_arsize, + output wire [ 2 -1 : 0 ] mws_arburst, + output wire mws_arvalid, + output wire [ AXI_ID_WIDTH -1 : 0 ] mws_arid, + input wire mws_arready, + // Master Interface Read Data + input wire [ AXI_DATA_WIDTH -1 : 0 ] mws_rdata, + input wire [ 2 -1 : 0 ] mws_rresp, + input wire mws_rlast, + input wire mws_rvalid, + input wire [ AXI_ID_WIDTH -1 : 0 ] mws_rid, + output wire mws_rready +); + +//============================================================================== +// Localparams +//============================================================================== + localparam integer LDMEM_IDLE = 0; + localparam integer LDMEM_CHECK_RAW = 1; + localparam integer LDMEM_BUSY = 2; + localparam integer LDMEM_WAIT_0 = 3; + localparam integer LDMEM_WAIT_1 = 4; + localparam integer LDMEM_WAIT_2 = 5; + localparam integer LDMEM_WAIT_3 = 6; + localparam integer LDMEM_DONE = 7; + + localparam integer STMEM_IDLE = 0; + localparam integer STMEM_DDR = 1; + localparam integer STMEM_WAIT_0 = 2; + localparam integer STMEM_WAIT_1 = 3; + localparam integer STMEM_WAIT_2 = 4; + localparam integer STMEM_WAIT_3 = 5; + localparam integer STMEM_DONE = 6; + localparam integer STMEM_PU = 7; + + localparam integer MEM_LD = 0; + localparam integer MEM_ST = 1; + localparam integer MEM_RD = 2; + localparam integer MEM_WR = 3; +//============================================================================== + +//============================================================================== +// Wires/Regs +//============================================================================== + wire [ TAG_MEM_ADDR_W -1 : 0 ] tag_mem_write_addr; + wire [ TAG_BUF_ADDR_W -1 : 0 ] tag_buf_read_addr; + + wire compute_tag_done; + wire compute_tag_reuse; + wire compute_tag_ready; + wire [ TAG_W -1 : 0 ] compute_tag; + wire ldmem_tag_done; + wire ldmem_tag_ready; + wire [ TAG_W -1 : 0 ] ldmem_tag; + wire stmem_tag_done; + wire stmem_tag_ready; + wire [ TAG_W -1 : 0 ] stmem_tag; + wire stmem_ddr_pe_sw; + + reg [ 4 -1 : 0 ] ldmem_state_d; + reg [ 4 -1 : 0 ] ldmem_state_q; + + reg [ 3 -1 : 0 ] stmem_state_d; + reg [ 3 -1 : 0 ] stmem_state_q; + + wire ld_mem_req_v; + wire st_mem_req_v; + + wire [ TAG_W -1 : 0 ] tag; + + + reg ld_iter_v_q; + reg [ LOOP_ITER_W -1 : 0 ] iter_q; + reg st_iter_v_q; + + reg [ LOOP_ID_W -1 : 0 ] ld_loop_id_counter; + reg [ LOOP_ID_W -1 : 0 ] st_loop_id_counter; + + wire [ LOOP_ID_W -1 : 0 ] mws_ld_loop_iter_loop_id; + wire [ LOOP_ITER_W -1 : 0 ] mws_ld_loop_iter; + wire mws_ld_loop_iter_v; + wire mws_ld_start; + wire mws_ld_done; + wire mws_ld_stall; + wire mws_ld_init; + wire mws_ld_enter; + wire mws_ld_exit; + wire [ LOOP_ID_W -1 : 0 ] mws_ld_index; + wire mws_ld_index_valid; + wire mws_ld_step; + + wire mws_st_stall; + wire mws_st_init; + wire mws_st_enter; + wire mws_st_exit; + wire [ LOOP_ID_W -1 : 0 ] mws_st_index; + wire mws_st_index_valid; + wire mws_st_step; + + wire ld_stride_v; + wire [ ADDR_STRIDE_W -1 : 0 ] ld_stride; + wire [ BUF_TYPE_W -1 : 0 ] ld_stride_id; + wire st_stride_v; + wire [ ADDR_STRIDE_W -1 : 0 ] st_stride; + wire [ BUF_TYPE_W -1 : 0 ] st_stride_id; + + wire [ ADDR_WIDTH -1 : 0 ] ld_addr; + wire [ ADDR_WIDTH -1 : 0 ] mws_ld_base_addr; + wire ld_addr_v; + + + reg [ MEM_REQ_W -1 : 0 ] ld_req_size; + wire ld_req_valid_d; + reg ld_req_valid_q; + reg [ ADDR_WIDTH -1 : 0 ] ld_req_addr; + + //reg [ ADDR_WIDTH -1 : 0 ] tag_ld_addr[0:NUM_TAGS-1]; + + + + wire axi_rd_req; + wire [ AXI_ID_WIDTH -1 : 0 ] axi_rd_req_id; + wire axi_rd_done; + wire [ MEM_REQ_W -1 : 0 ] axi_rd_req_size; + wire axi_rd_ready; + wire [ AXI_ADDR_WIDTH -1 : 0 ] axi_rd_addr; + + wire axi_wr_req; + wire [ AXI_ID_WIDTH -1 : 0 ] axi_wr_req_id; + wire axi_wr_done; + wire [ MEM_REQ_W -1 : 0 ] axi_wr_req_size; + wire axi_wr_ready; + wire [ AXI_ADDR_WIDTH -1 : 0 ] axi_wr_addr; + + wire mem_write_req; + wire [ AXI_DATA_WIDTH -1 : 0 ] mem_write_data; + reg [ MEM_ADDR_W -1 : 0 ] mem_write_addr; + wire mem_write_ready; + wire [ AXI_DATA_WIDTH -1 : 0 ] mem_read_data; + wire mem_read_req; + wire mem_read_ready; + + // Adding register to buf read data + wire [ BUF_DATA_WIDTH -1 : 0 ] _buf_read_data; + + // Read-after-write + reg raw; + wire [ TAG_W -1 : 0 ] raw_stmem_tag; + wire raw_stmem_tag_ready; + wire [ ADDR_WIDTH -1 : 0 ] raw_stmem_st_addr; + wire pu_done; + wire [ AXI_ID_WIDTH -1 : 0 ] mem_write_id; + wire ldmem_ready; +//============================================================================== + +//============================================================================== +// Assigns +//============================================================================== + assign pu_done= 1'b1; + + assign ld_stride = cfg_loop_stride; + assign ld_stride_v = cfg_loop_stride_v && cfg_loop_stride_loop_id == 1 + MEM_ID && cfg_loop_stride_type == MEM_LD && cfg_loop_stride_id == MEM_ID; + + //assign mws_ld_base_addr = tag_ld_addr[ldmem_tag]; + assign axi_rd_req = ld_req_valid_q; + assign axi_rd_req_size = ld_req_size * (ARRAY_N * ARRAY_M * DATA_WIDTH) / AXI_DATA_WIDTH; + assign axi_rd_addr = ld_req_addr; + + assign axi_wr_req = 1'b0; + assign axi_wr_req_id = 1'b0; + assign axi_wr_req_size = 0; + assign axi_wr_addr = 0; +//============================================================================== + +//============================================================================== +// Address generators +//============================================================================== + assign mws_ld_stall = ~ldmem_tag_ready || ~axi_rd_ready; + assign mws_ld_step = mws_ld_index_valid && !mws_ld_stall; + mem_walker_stride #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) mws_ld ( + .clk ( clk ), //input + .reset ( reset ), //input + .base_addr ( mws_ld_base_addr ), //input + .loop_ctrl_done ( mws_ld_done ), //input + .loop_index ( mws_ld_index ), //input + .loop_index_valid ( mws_ld_step ), //input + .loop_init ( mws_ld_init ), //input + .loop_enter ( mws_ld_enter ), //input + .loop_exit ( mws_ld_exit ), //input + .cfg_addr_stride_v ( ld_stride_v ), //input + .cfg_addr_stride ( ld_stride ), //input + .addr_out ( ld_addr ), //output + .addr_out_valid ( ld_addr_v ) //output + ); +//============================================================================== + +//============================================================= +// Loop controller +//============================================================= + always@(posedge clk) + begin + if (reset) + ld_loop_id_counter <= 'b0; + else begin + if (mws_ld_loop_iter_v) + ld_loop_id_counter <= ld_loop_id_counter + 1'b1; + else if (tag_req && tag_ready) + ld_loop_id_counter <= 'b0; + end + end + + always @(posedge clk) + begin + if (reset) + ld_iter_v_q <= 1'b0; + else begin + if (cfg_loop_iter_v && cfg_loop_iter_loop_id == 1 + MEM_ID) + ld_iter_v_q <= 1'b1; + else if (cfg_loop_iter_v || ld_stride_v) + ld_iter_v_q <= 1'b0; + end + end + + + assign mws_ld_start = ldmem_state_q == LDMEM_BUSY; + assign mws_ld_loop_iter_v = ld_stride_v && ld_iter_v_q; + assign mws_ld_loop_iter = iter_q; + assign mws_ld_loop_iter_loop_id = ld_loop_id_counter; + + always @(posedge clk) + begin + if (reset) begin + iter_q <= 'b0; + end + else if (cfg_loop_iter_v && cfg_loop_iter_loop_id == 1 + MEM_ID) begin + iter_q <= cfg_loop_iter; + end + end + + controller_fsm #( + .LOOP_ID_W ( LOOP_ID_W ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .IMEM_ADDR_W ( LOOP_ID_W ) + ) mws_ld_ctrl ( + .clk ( clk ), //input + .reset ( reset ), //input + .stall ( mws_ld_stall ), //input + .cfg_loop_iter_v ( mws_ld_loop_iter_v ), //input + .cfg_loop_iter ( mws_ld_loop_iter ), //input + .cfg_loop_iter_loop_id ( mws_ld_loop_iter_loop_id ), //input + .start ( mws_ld_start ), //input + .done ( mws_ld_done ), //output + .loop_init ( mws_ld_init ), //output + .loop_enter ( mws_ld_enter ), //output + .loop_last_iter ( ), //output + .loop_exit ( mws_ld_exit ), //output + .loop_index ( mws_ld_index ), //output + .loop_index_valid ( mws_ld_index_valid ) //output + ); +//============================================================= + +//============================================================================== +// Memory Request generation +//============================================================================== + assign ld_mem_req_v = cfg_mem_req_v && cfg_mem_req_loop_id == (1 + MEM_ID) && cfg_mem_req_type == MEM_LD && cfg_mem_req_id == MEM_ID; + always @(posedge clk) + begin + if (reset) begin + ld_req_size <= 'b0; +// ld_req_loop_id <= 'b0; + end + else if (ld_mem_req_v) begin + ld_req_size <= cfg_mem_req_size; +// ld_req_loop_id <= ld_loop_id_counter; + end + end + + + // assign ld_req_valid_d = (ld_req_loop_id == mws_ld_index) && (mws_ld_enter || mws_ld_step); + // assign ld_req_valid_d = (ld_req_loop_id == mws_ld_index) && ld_addr_v; + assign ld_req_valid_d = ld_addr_v; + + always @(posedge clk) + begin + if (reset) begin + ld_req_valid_q <= 1'b0; + ld_req_addr <= 'b0; + end + else begin + ld_req_valid_q <= ld_req_valid_d; + ld_req_addr <= ld_addr; + end + end + + //always @(posedge clk) + //begin + // if (tag_req && tag_ready) begin + // tag_ld_addr[tag] <= tag_base_ld_addr; + // end + //end + + ram #( + .ADDR_WIDTH ( $clog2(NUM_TAGS)), + .DATA_WIDTH ( ADDR_WIDTH) + ) u_ram_tag_ld_2( + .clk ( clk ), + .reset ( reset ), + .s_write_addr ( tag), + .s_write_req ( tag_req && tag_ready), + .s_write_data ( tag_base_ld_addr), + .s_read_addr ( ldmem_tag), + .s_read_req ( 1'b1), + .s_read_data ( mws_ld_base_addr) + ); + + // wire [ 31 : 0 ] tag0_ld_addr; + // wire [ 31 : 0 ] tag1_ld_addr; + // wire [ 31 : 0 ] tag0_st_addr; + // wire [ 31 : 0 ] tag1_st_addr; + // assign tag0_ld_addr = tag_ld_addr[0]; + // assign tag1_ld_addr = tag_ld_addr[1]; +//============================================================================== + +//============================================================================== +// Tag-based synchronization for double buffering +//============================================================================== + assign raw_stmem_tag = 0; + + always @(*) + begin + ldmem_state_d = ldmem_state_q; + case(ldmem_state_q) + LDMEM_IDLE: begin + if (ldmem_tag_ready) begin + ldmem_state_d = LDMEM_BUSY; + end + end + LDMEM_BUSY: begin + if (mws_ld_done) + ldmem_state_d = LDMEM_WAIT_0; + end + LDMEM_WAIT_0: begin + ldmem_state_d = LDMEM_WAIT_1; + end + LDMEM_WAIT_1: begin + ldmem_state_d = LDMEM_WAIT_2; + end + LDMEM_WAIT_2: begin + ldmem_state_d = LDMEM_WAIT_3; + end + LDMEM_WAIT_3: begin + if (axi_rd_done) + ldmem_state_d = LDMEM_DONE; + end + LDMEM_DONE: begin + ldmem_state_d = LDMEM_IDLE; + end + endcase + end + + always @(posedge clk) + begin + if (reset) + ldmem_state_q <= LDMEM_IDLE; + else + ldmem_state_q <= ldmem_state_d; + end + + always @(*) + begin + stmem_state_d = stmem_state_q; + case(stmem_state_q) + STMEM_IDLE: begin + if (stmem_tag_ready) begin + stmem_state_d = STMEM_DONE; + end + end + STMEM_DONE: begin + stmem_state_d = STMEM_IDLE; + end + endcase + end + + always @(posedge clk) + begin + if (reset) + stmem_state_q <= STMEM_IDLE; + else + stmem_state_q <= stmem_state_d; + end + + assign compute_tag_done = compute_done; + assign compute_ready = compute_tag_ready; + + assign ldmem_tag_done = ldmem_state_q == LDMEM_DONE; + assign ldmem_ready = ldmem_tag_ready; + // assign ldmem_tag_done = mws_ld_done; + + assign stmem_tag_done = stmem_state_q == STMEM_DONE; + + tag_sync #( + .NUM_TAGS ( NUM_TAGS ) + ) + mws_tag ( + .clk ( clk ), + .reset ( reset ), + .block_done ( block_done ), + .tag_req ( tag_req ), + .tag_reuse ( tag_reuse ), + .tag_bias_prev_sw ( tag_bias_prev_sw ), + .tag_ddr_pe_sw ( tag_ddr_pe_sw ), //input + .tag_ready ( tag_ready ), + .tag ( tag ), + .tag_done ( tag_done ), + .raw_stmem_tag ( raw_stmem_tag ), + .raw_stmem_tag_ready ( raw_stmem_tag_ready ), + .compute_tag_done ( compute_tag_done ), + .compute_tag_ready ( compute_tag_ready ), + .compute_bias_prev_sw ( compute_bias_prev_sw ), + .compute_tag ( compute_tag ), + .ldmem_tag_done ( ldmem_tag_done ), + .ldmem_tag_ready ( ldmem_tag_ready ), + .ldmem_tag ( ldmem_tag ), + .stmem_ddr_pe_sw ( stmem_ddr_pe_sw ), + .stmem_tag_done ( stmem_tag_done ), + .stmem_tag_ready ( stmem_tag_ready ), + .stmem_tag ( stmem_tag ) + ); +//============================================================================== + + +//============================================================================== +// AXI4 Memory Mapped interface +//============================================================================== + assign mem_write_ready = 1'b1; + assign mem_read_ready = 1'b0; + assign axi_rd_req_id = 0; + assign mem_read_data = 0; + axi_master #( + .TX_SIZE_WIDTH ( MEM_REQ_W ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_BURST_WIDTH ( AXI_BURST_WIDTH ) + ) u_axi_mm_master ( + .clk ( clk ), + .reset ( reset ), + .m_axi_awaddr ( mws_awaddr ), + .m_axi_awlen ( mws_awlen ), + .m_axi_awsize ( mws_awsize ), + .m_axi_awburst ( mws_awburst ), + .m_axi_awvalid ( mws_awvalid ), + .m_axi_awready ( mws_awready ), + .m_axi_wdata ( mws_wdata ), + .m_axi_wstrb ( mws_wstrb ), + .m_axi_wlast ( mws_wlast ), + .m_axi_wvalid ( mws_wvalid ), + .m_axi_wready ( mws_wready ), + .m_axi_bresp ( mws_bresp ), + .m_axi_bvalid ( mws_bvalid ), + .m_axi_bready ( mws_bready ), + .m_axi_araddr ( mws_araddr ), + .m_axi_arid ( mws_arid ), + .m_axi_arlen ( mws_arlen ), + .m_axi_arsize ( mws_arsize ), + .m_axi_arburst ( mws_arburst ), + .m_axi_arvalid ( mws_arvalid ), + .m_axi_arready ( mws_arready ), + .m_axi_rdata ( mws_rdata ), + .m_axi_rid ( mws_rid ), + .m_axi_rresp ( mws_rresp ), + .m_axi_rlast ( mws_rlast ), + .m_axi_rvalid ( mws_rvalid ), + .m_axi_rready ( mws_rready ), + // Buffer + .mem_write_id ( mem_write_id ), + .mem_write_req ( mem_write_req ), + .mem_write_data ( mem_write_data ), + .mem_write_ready ( mem_write_ready ), + .mem_read_data ( mem_read_data ), + .mem_read_req ( mem_read_req ), + .mem_read_ready ( mem_read_ready ), + // AXI RD Req + .rd_req_id ( axi_rd_req_id ), + .rd_req ( axi_rd_req ), + .rd_done ( axi_rd_done ), + .rd_ready ( axi_rd_ready ), + .rd_req_size ( axi_rd_req_size ), + .rd_addr ( axi_rd_addr ), + // AXI WR Req + .wr_req ( axi_wr_req ), + .wr_req_id ( axi_wr_req_id ), + .wr_ready ( axi_wr_ready ), + .wr_req_size ( axi_wr_req_size ), + .wr_addr ( axi_wr_addr ), + .wr_done ( axi_wr_done ) + ); +//============================================================================== + +`ifdef COCOTB_SIM + integer req_count; + always @(posedge clk) + begin + if (reset) req_count <= 0; + else req_count = req_count + (tag_req && tag_ready); + end +`endif //COCOTB_SIM +//============================================================================== +// Dual-port RAM +//============================================================================== + always @(posedge clk) + begin + if (reset) + mem_write_addr <= 0; + else begin + if (mem_write_req) + mem_write_addr <= mem_write_addr + 1'b1; + else if (ldmem_state_q == LDMEM_DONE) + mem_write_addr <= 0; + end + end + + assign tag_mem_write_addr = {ldmem_tag, mem_write_addr}; + assign tag_buf_read_addr = {compute_tag, buf_read_addr}; + + register_sync #(BUF_DATA_WIDTH) + buf_read_data_delay (clk, reset, _buf_read_data, buf_read_data); + + ibuf #( + .TAG_W ( TAG_W ), + .BUF_ADDR_WIDTH ( TAG_BUF_ADDR_W ), + .ARRAY_N ( ARRAY_N ), + .MEM_DATA_WIDTH ( AXI_DATA_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ) + ) buf_ram ( + .clk ( clk ), + .reset ( reset ), + .mem_write_addr ( tag_mem_write_addr ), + .mem_write_req ( mem_write_req ), + .mem_write_data ( mem_write_data ), + .buf_read_addr ( tag_buf_read_addr ), + .buf_read_req ( buf_read_req ), + .buf_read_data ( _buf_read_data ) + ); +//============================================================================== + + +//============================================================================== + +`ifdef COCOTB_SIM + integer wr_req_count=0; + always @(posedge clk) + if (reset) + wr_req_count <= 0; + else + wr_req_count <= wr_req_count + axi_wr_req; + + integer rd_req_count=0; + integer missed_rd_req_count=0; + always @(posedge clk) + if (reset) + rd_req_count <= 0; + else + rd_req_count <= rd_req_count + axi_rd_req; + always @(posedge clk) + if (reset) + missed_rd_req_count <= 0; + else + missed_rd_req_count <= missed_rd_req_count + (axi_rd_req && ~axi_rd_ready); +`endif + + +//============================================================= +// VCD +//============================================================= +`ifdef COCOTB_TOPLEVEL_mem_wrapper +initial begin + $dumpfile("mem_wrapper.vcd"); + $dumpvars(0, mem_wrapper); +end +`endif +//============================================================= +endmodule +// +// Wrapper for memory +// +// Hardik Sharma +// (hsharma@gatech.edu) + +`timescale 1ns/1ps +module wbuf_mem_wrapper #( + // Internal Parameters + parameter integer MEM_ID = 0, + parameter integer STORE_ENABLED = MEM_ID == 1 ? 1 : 0, + parameter integer MEM_REQ_W = 16, + parameter integer ADDR_WIDTH = 8, + parameter integer DATA_WIDTH = 32, + parameter integer LOOP_ITER_W = 16, + parameter integer ADDR_STRIDE_W = 32, + parameter integer LOOP_ID_W = 5, + parameter integer BUF_TYPE_W = 2, + parameter integer NUM_TAGS = 4, + parameter integer TAG_W = $clog2(NUM_TAGS), + + // AXI + parameter integer AXI_ADDR_WIDTH = 42, + parameter integer AXI_ID_WIDTH = 1, + parameter integer AXI_DATA_WIDTH = 64, + parameter integer AXI_BURST_WIDTH = 8, + parameter integer WSTRB_W = AXI_DATA_WIDTH/8, + + // Buffer + parameter integer ARRAY_N = 2, + parameter integer ARRAY_M = MEM_ID == 2 ? ARRAY_N : 1, + parameter integer BUF_DATA_WIDTH = DATA_WIDTH * ARRAY_N * ARRAY_M, + parameter integer BUF_ADDR_W = 16, + parameter integer MEM_ADDR_W = BUF_ADDR_W + $clog2(BUF_DATA_WIDTH / AXI_DATA_WIDTH), + parameter integer TAG_BUF_ADDR_W = BUF_ADDR_W + TAG_W, + parameter integer TAG_MEM_ADDR_W = MEM_ADDR_W + TAG_W +) ( + input wire clk, + input wire reset, + + input wire tag_req, + input wire tag_reuse, + input wire tag_bias_prev_sw, + input wire tag_ddr_pe_sw, + output wire tag_ready, + output wire tag_done, + input wire compute_done, + input wire block_done, + input wire [ ADDR_WIDTH -1 : 0 ] tag_base_ld_addr, + + output wire compute_ready, + output wire compute_bias_prev_sw, + + // Programming + input wire cfg_loop_stride_v, + input wire [ ADDR_STRIDE_W -1 : 0 ] cfg_loop_stride, + input wire [ LOOP_ID_W -1 : 0 ] cfg_loop_stride_loop_id, + input wire [ BUF_TYPE_W -1 : 0 ] cfg_loop_stride_id, + input wire [ 2 -1 : 0 ] cfg_loop_stride_type, + + input wire cfg_loop_iter_v, + input wire [ LOOP_ITER_W -1 : 0 ] cfg_loop_iter, + input wire [ LOOP_ID_W -1 : 0 ] cfg_loop_iter_loop_id, + + input wire cfg_mem_req_v, + input wire [ BUF_TYPE_W -1 : 0 ] cfg_mem_req_id, + input wire [ MEM_REQ_W -1 : 0 ] cfg_mem_req_size, + input wire [ LOOP_ID_W -1 : 0 ] cfg_mem_req_loop_id, + input wire [ 2 -1 : 0 ] cfg_mem_req_type, + + // Systolic Array + output wire [ BUF_DATA_WIDTH -1 : 0 ] buf_read_data, + input wire buf_read_req, + input wire [ BUF_ADDR_W -1 : 0 ] buf_read_addr, + + // CL_wrapper -> DDR AXI4 interface + // Master Interface Write Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] mws_awaddr, + output wire [ AXI_BURST_WIDTH -1 : 0 ] mws_awlen, + output wire [ 3 -1 : 0 ] mws_awsize, + output wire [ 2 -1 : 0 ] mws_awburst, + output wire mws_awvalid, + input wire mws_awready, + // Master Interface Write Data + output wire [ AXI_DATA_WIDTH -1 : 0 ] mws_wdata, + output wire [ WSTRB_W -1 : 0 ] mws_wstrb, + output wire mws_wlast, + output wire mws_wvalid, + input wire mws_wready, + // Master Interface Write Response + input wire [ 2 -1 : 0 ] mws_bresp, + input wire mws_bvalid, + output wire mws_bready, + // Master Interface Read Address + output wire [ AXI_ADDR_WIDTH -1 : 0 ] mws_araddr, + output wire [ AXI_ID_WIDTH -1 : 0 ] mws_arid, + output wire [ AXI_BURST_WIDTH -1 : 0 ] mws_arlen, + output wire [ 3 -1 : 0 ] mws_arsize, + output wire [ 2 -1 : 0 ] mws_arburst, + output wire mws_arvalid, + input wire mws_arready, + // Master Interface Read Data + input wire [ AXI_DATA_WIDTH -1 : 0 ] mws_rdata, + input wire [ AXI_ID_WIDTH -1 : 0 ] mws_rid, + input wire [ 2 -1 : 0 ] mws_rresp, + input wire mws_rlast, + input wire mws_rvalid, + output wire mws_rready +); + +//============================================================================== +// Localparams +//============================================================================== + localparam integer LDMEM_IDLE = 0; + localparam integer LDMEM_CHECK_RAW = 1; + localparam integer LDMEM_BUSY = 2; + localparam integer LDMEM_WAIT_0 = 3; + localparam integer LDMEM_WAIT_1 = 4; + localparam integer LDMEM_WAIT_2 = 5; + localparam integer LDMEM_WAIT_3 = 6; + localparam integer LDMEM_DONE = 7; + + localparam integer STMEM_IDLE = 0; + localparam integer STMEM_DDR = 1; + localparam integer STMEM_WAIT_0 = 2; + localparam integer STMEM_WAIT_1 = 3; + localparam integer STMEM_WAIT_2 = 4; + localparam integer STMEM_WAIT_3 = 5; + localparam integer STMEM_DONE = 6; + localparam integer STMEM_PU = 7; + + localparam integer MEM_LD = 0; + localparam integer MEM_ST = 1; + localparam integer MEM_RD = 2; + localparam integer MEM_WR = 3; +//============================================================================== + +//============================================================================== +// Wires/Regs +//============================================================================== + wire compute_tag_done; + wire compute_tag_reuse; + wire compute_tag_ready; + wire [ TAG_W -1 : 0 ] compute_tag; + wire [ TAG_W -1 : 0 ] compute_tag_delayed; + wire ldmem_tag_done; + wire ldmem_tag_ready; + wire [ TAG_W -1 : 0 ] ldmem_tag; + wire stmem_tag_done; + wire stmem_tag_ready; + wire [ TAG_W -1 : 0 ] stmem_tag; + wire stmem_ddr_pe_sw; + + reg [ 4 -1 : 0 ] ldmem_state_d; + reg [ 4 -1 : 0 ] ldmem_state_q; + + reg [ 3 -1 : 0 ] stmem_state_d; + reg [ 3 -1 : 0 ] stmem_state_q; + + wire ld_mem_req_v; + wire st_mem_req_v; + + wire [ TAG_W -1 : 0 ] tag; + + + reg ld_iter_v_q; + reg [ LOOP_ITER_W -1 : 0 ] iter_q; + + reg [ LOOP_ID_W -1 : 0 ] ld_loop_id_counter; + + wire [ LOOP_ID_W -1 : 0 ] mws_ld_loop_iter_loop_id; + wire [ LOOP_ITER_W -1 : 0 ] mws_ld_loop_iter; + wire mws_ld_loop_iter_v; + wire mws_ld_start; + wire mws_ld_done; + wire mws_ld_stall; + wire mws_ld_init; + wire mws_ld_enter; + wire mws_ld_exit; + wire [ LOOP_ID_W -1 : 0 ] mws_ld_index; + wire mws_ld_index_valid; + wire mws_ld_step; + + wire ld_stride_v; + wire [ ADDR_STRIDE_W -1 : 0 ] ld_stride; + wire [ BUF_TYPE_W -1 : 0 ] ld_stride_id; + + wire [ ADDR_WIDTH -1 : 0 ] ld_addr; + wire [ ADDR_WIDTH -1 : 0 ] mws_ld_base_addr; + wire ld_addr_v; + + reg [ MEM_REQ_W -1 : 0 ] ld_req_size; + + wire ld_req_valid_d; + + reg ld_req_valid_q; + + //reg [ ADDR_WIDTH -1 : 0 ] tag_ld_addr[0:NUM_TAGS-1]; + + reg [ ADDR_WIDTH -1 : 0 ] ld_req_addr; + + wire axi_rd_req; + wire [ AXI_ID_WIDTH -1 : 0 ] axi_rd_req_id; + wire axi_rd_done; + wire [ MEM_REQ_W -1 : 0 ] axi_rd_req_size; + wire axi_rd_ready; + wire [ AXI_ADDR_WIDTH -1 : 0 ] axi_rd_addr; + + wire axi_wr_req; + wire [ AXI_ID_WIDTH -1 : 0 ] axi_wr_req_id; + wire axi_wr_done; + wire [ MEM_REQ_W -1 : 0 ] axi_wr_req_size; + wire axi_wr_ready; + wire [ AXI_ADDR_WIDTH -1 : 0 ] axi_wr_addr; + + wire [ AXI_ID_WIDTH -1 : 0 ] mem_write_id; + wire mem_write_req; + wire [ AXI_DATA_WIDTH -1 : 0 ] mem_write_data; + reg [ MEM_ADDR_W -1 : 0 ] mem_write_addr; + wire mem_write_ready; + // Mem reads disabled + wire [ AXI_DATA_WIDTH -1 : 0 ] mem_read_data; + wire mem_read_req; + wire mem_read_ready; + + // Adding register to buf read data + wire [ BUF_DATA_WIDTH -1 : 0 ] _buf_read_data; +//============================================================================== + +//============================================================================== +// Assigns +//============================================================================== + assign ld_stride = cfg_loop_stride; + assign ld_stride_v = cfg_loop_stride_v && cfg_loop_stride_loop_id == 1 + MEM_ID && cfg_loop_stride_type == MEM_LD && cfg_loop_stride_id == MEM_ID; + + //assign mws_ld_base_addr = tag_ld_addr[ldmem_tag]; + + assign axi_rd_req = ld_req_valid_q; + assign axi_rd_req_size = ld_req_size * (ARRAY_N * ARRAY_M * DATA_WIDTH) / AXI_DATA_WIDTH; + assign axi_rd_addr = ld_req_addr; + + assign axi_wr_req = 1'b0; + assign axi_wr_req_id = 1'b0; + assign axi_wr_req_size = 0; + assign axi_wr_addr = 0; +//============================================================================== + +//============================================================================== +// Address generators +//============================================================================== + assign mws_ld_stall = ~ldmem_tag_ready || ~axi_rd_ready; + assign mws_ld_step = mws_ld_index_valid && !mws_ld_stall; + mem_walker_stride #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .ADDR_STRIDE_W ( ADDR_STRIDE_W ), + .LOOP_ID_W ( LOOP_ID_W ) + ) mws_ld ( + .clk ( clk ), //input + .reset ( reset ), //input + .base_addr ( mws_ld_base_addr ), //input + .loop_ctrl_done ( mws_ld_done ), //input + .loop_index ( mws_ld_index ), //input + .loop_index_valid ( mws_ld_step ), //input + .loop_init ( mws_ld_init ), //input + .loop_enter ( mws_ld_enter ), //input + .loop_exit ( mws_ld_exit ), //input + .cfg_addr_stride_v ( ld_stride_v ), //input + .cfg_addr_stride ( ld_stride ), //input + .addr_out ( ld_addr ), //output + .addr_out_valid ( ld_addr_v ) //output + ); +//============================================================================== + +//============================================================= +// Loop controller +//============================================================= + always@(posedge clk) + begin + if (reset) + ld_loop_id_counter <= 'b0; + else begin + if (mws_ld_loop_iter_v) + ld_loop_id_counter <= ld_loop_id_counter + 1'b1; + else if (tag_req && tag_ready) + ld_loop_id_counter <= 'b0; + end + end + + always @(posedge clk) + begin + if (reset) + ld_iter_v_q <= 1'b0; + else begin + if (cfg_loop_iter_v && cfg_loop_iter_loop_id == 1 + MEM_ID) + ld_iter_v_q <= 1'b1; + else if (cfg_loop_iter_v || ld_stride_v) + ld_iter_v_q <= 1'b0; + end + end + + + assign mws_ld_start = ldmem_state_q == LDMEM_BUSY; + assign mws_ld_loop_iter_v = ld_stride_v && ld_iter_v_q; + assign mws_ld_loop_iter = iter_q; + assign mws_ld_loop_iter_loop_id = ld_loop_id_counter; + + always @(posedge clk) + begin + if (reset) begin + iter_q <= 'b0; + end + else if (cfg_loop_iter_v && cfg_loop_iter_loop_id == 1 + MEM_ID) begin + iter_q <= cfg_loop_iter; + end + end + + controller_fsm #( + .LOOP_ID_W ( LOOP_ID_W ), + .LOOP_ITER_W ( LOOP_ITER_W ), + .IMEM_ADDR_W ( LOOP_ID_W ) + ) mws_ld_ctrl ( + .clk ( clk ), //input + .reset ( reset ), //input + .stall ( mws_ld_stall ), //input + .cfg_loop_iter_v ( mws_ld_loop_iter_v ), //input + .cfg_loop_iter ( mws_ld_loop_iter ), //input + .cfg_loop_iter_loop_id ( mws_ld_loop_iter_loop_id ), //input + .start ( mws_ld_start ), //input + .done ( mws_ld_done ), //output + .loop_init ( mws_ld_init ), //output + .loop_enter ( mws_ld_enter ), //output + .loop_last_iter ( ), //output + .loop_exit ( mws_ld_exit ), //output + .loop_index ( mws_ld_index ), //output + .loop_index_valid ( mws_ld_index_valid ) //output + ); +//============================================================= + +//============================================================================== +// Memory Request generation +//============================================================================== + assign ld_mem_req_v = cfg_mem_req_v && cfg_mem_req_loop_id == (1 + MEM_ID) && cfg_mem_req_type == MEM_LD && cfg_mem_req_id == MEM_ID; + always @(posedge clk) + begin + if (reset) begin + ld_req_size <= 'b0; + // ld_req_loop_id <= 'b0; + end + else if (ld_mem_req_v) begin + ld_req_size <= cfg_mem_req_size; + // ld_req_loop_id <= ld_loop_id_counter; + end + end + + // assign ld_req_valid_d = (ld_req_loop_id == mws_ld_index) && (mws_ld_enter || mws_ld_step); + // assign ld_req_valid_d = (ld_req_loop_id == mws_ld_index) && ld_addr_v; + assign ld_req_valid_d = ld_addr_v; + + always @(posedge clk) + begin + if (reset) begin + ld_req_valid_q <= 1'b0; + ld_req_addr <= 'b0; + end + else begin + ld_req_valid_q <= ld_req_valid_d; + ld_req_addr <= ld_addr; + end + end + + //always @(posedge clk) + //begin + // if (tag_req && tag_ready) begin + // tag_ld_addr[tag] <= tag_base_ld_addr; + // end + //end + + ram #( + .ADDR_WIDTH ( $clog2(NUM_TAGS)), + .DATA_WIDTH ( ADDR_WIDTH) + ) u_ram_tag_ld_3( + .clk ( clk ), + .reset ( reset ), + .s_write_addr ( tag), + .s_write_req ( tag_req && tag_ready), + .s_write_data ( tag_base_ld_addr), + .s_read_addr ( ldmem_tag), + .s_read_req ( 1'b1), + .s_read_data ( mws_ld_base_addr) + ); + + // wire [ 31 : 0 ] tag0_ld_addr; + // wire [ 31 : 0 ] tag1_ld_addr; + // wire [ 31 : 0 ] tag0_st_addr; + // wire [ 31 : 0 ] tag1_st_addr; + // assign tag0_ld_addr = tag_ld_addr[0]; + // assign tag1_ld_addr = tag_ld_addr[1]; + // assign tag0_st_addr = tag_st_addr[0]; + // assign tag1_st_addr = tag_st_addr[1]; +//============================================================================== + +//============================================================================== +// Tag-based synchronization for double buffering +//============================================================================== + wire [ TAG_W -1 : 0 ] raw_stmem_tag; + wire raw_stmem_tag_ready; + assign raw_stmem_tag = 0; + + always @(*) + begin + ldmem_state_d = ldmem_state_q; + case(ldmem_state_q) + LDMEM_IDLE: begin + if (ldmem_tag_ready) begin + ldmem_state_d = LDMEM_BUSY; + end + end + LDMEM_BUSY: begin + if (mws_ld_done) + ldmem_state_d = LDMEM_WAIT_0; + end + LDMEM_WAIT_0: begin + ldmem_state_d = LDMEM_WAIT_1; + end + LDMEM_WAIT_1: begin + ldmem_state_d = LDMEM_WAIT_2; + end + LDMEM_WAIT_2: begin + ldmem_state_d = LDMEM_WAIT_3; + end + LDMEM_WAIT_3: begin + if (axi_rd_done) + ldmem_state_d = LDMEM_DONE; + end + LDMEM_DONE: begin + ldmem_state_d = LDMEM_IDLE; + end + endcase + end + + always @(posedge clk) + begin + if (reset) + ldmem_state_q <= LDMEM_IDLE; + else + ldmem_state_q <= ldmem_state_d; + end + + + wire pu_done = 1'b1; + + always @(*) + begin + stmem_state_d = stmem_state_q; + case(stmem_state_q) + STMEM_IDLE: begin + if (stmem_tag_ready) begin + stmem_state_d = STMEM_DONE; + end + end + STMEM_DONE: begin + stmem_state_d = STMEM_IDLE; + end + endcase + end + + always @(posedge clk) + begin + if (reset) + stmem_state_q <= STMEM_IDLE; + else + stmem_state_q <= stmem_state_d; + end + + + wire ldmem_ready; + + assign compute_tag_done = compute_done; + assign compute_ready = compute_tag_ready; + + assign ldmem_tag_done = ldmem_state_q == LDMEM_DONE; + assign ldmem_ready = ldmem_tag_ready; + // assign ldmem_tag_done = mws_ld_done; + + assign stmem_tag_done = stmem_state_q == STMEM_DONE; + + tag_sync #( + .NUM_TAGS ( NUM_TAGS ) + ) + mws_tag ( + .clk ( clk ), + .reset ( reset ), + .block_done ( block_done ), + .tag_req ( tag_req ), + .tag_reuse ( tag_reuse ), + .tag_bias_prev_sw ( tag_bias_prev_sw ), + .tag_ddr_pe_sw ( tag_ddr_pe_sw ), //input + .tag_ready ( tag_ready ), + .tag ( tag ), + .tag_done ( tag_done ), + .raw_stmem_tag ( raw_stmem_tag ), + .raw_stmem_tag_ready ( raw_stmem_tag_ready ), + .compute_tag_done ( compute_tag_done ), + .compute_tag_ready ( compute_tag_ready ), + .compute_bias_prev_sw ( compute_bias_prev_sw ), + .compute_tag ( compute_tag ), + .ldmem_tag_done ( ldmem_tag_done ), + .ldmem_tag_ready ( ldmem_tag_ready ), + .ldmem_tag ( ldmem_tag ), + .stmem_ddr_pe_sw ( stmem_ddr_pe_sw ), + .stmem_tag_done ( stmem_tag_done ), + .stmem_tag_ready ( stmem_tag_ready ), + .stmem_tag ( stmem_tag ) + ); +//============================================================================== + + +//============================================================================== +// AXI4 Memory Mapped interface +//============================================================================== + assign mem_write_ready = 1'b1; + assign mem_read_ready = 1'b1; + assign axi_rd_req_id = 1'b0; + assign mem_read_data = 0; + axi_master #( + .TX_SIZE_WIDTH ( MEM_REQ_W ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_BURST_WIDTH ( AXI_BURST_WIDTH ) + ) u_axi_mm_master ( + .clk ( clk ), + .reset ( reset ), + .m_axi_awaddr ( mws_awaddr ), + .m_axi_awlen ( mws_awlen ), + .m_axi_awsize ( mws_awsize ), + .m_axi_awburst ( mws_awburst ), + .m_axi_awvalid ( mws_awvalid ), + .m_axi_awready ( mws_awready ), + .m_axi_wdata ( mws_wdata ), + .m_axi_wstrb ( mws_wstrb ), + .m_axi_wlast ( mws_wlast ), + .m_axi_wvalid ( mws_wvalid ), + .m_axi_wready ( mws_wready ), + .m_axi_bresp ( mws_bresp ), + .m_axi_bvalid ( mws_bvalid ), + .m_axi_bready ( mws_bready ), + .m_axi_araddr ( mws_araddr ), + .m_axi_arid ( mws_arid ), + .m_axi_arlen ( mws_arlen ), + .m_axi_arsize ( mws_arsize ), + .m_axi_arburst ( mws_arburst ), + .m_axi_arvalid ( mws_arvalid ), + .m_axi_arready ( mws_arready ), + .m_axi_rdata ( mws_rdata ), + .m_axi_rid ( mws_rid ), + .m_axi_rresp ( mws_rresp ), + .m_axi_rlast ( mws_rlast ), + .m_axi_rvalid ( mws_rvalid ), + .m_axi_rready ( mws_rready ), + // Buffer + .mem_write_id ( mem_write_id ), + .mem_write_req ( mem_write_req ), + .mem_write_data ( mem_write_data ), + .mem_write_ready ( mem_write_ready ), + .mem_read_data ( mem_read_data ), + .mem_read_req ( mem_read_req ), + .mem_read_ready ( mem_read_ready ), + // AXI RD Req + .rd_req_id ( axi_rd_req_id ), + .rd_req ( axi_rd_req ), + .rd_done ( axi_rd_done ), + .rd_ready ( axi_rd_ready ), + .rd_req_size ( axi_rd_req_size ), + .rd_addr ( axi_rd_addr ), + // AXI WR Req + .wr_req ( axi_wr_req ), + .wr_req_id ( axi_wr_req_id ), + .wr_ready ( axi_wr_ready ), + .wr_req_size ( axi_wr_req_size ), + .wr_addr ( axi_wr_addr ), + .wr_done ( axi_wr_done ) + ); +//============================================================================== + +//============================================================================== +// Dual-port RAM +//============================================================================== + always @(posedge clk) + begin + if (reset) + mem_write_addr <= 0; + else begin + if (mem_write_req) + mem_write_addr <= mem_write_addr + 1'b1; + else if (ldmem_state_q == LDMEM_DONE) + mem_write_addr <= 0; + end + end + + wire [ TAG_MEM_ADDR_W -1 : 0 ] tag_mem_read_addr; + wire [ TAG_MEM_ADDR_W -1 : 0 ] tag_mem_write_addr; + + wire [ TAG_BUF_ADDR_W -1 : 0 ] tag_buf_read_addr; + + assign tag_mem_write_addr = {ldmem_tag, mem_write_addr}; + + assign compute_tag_delayed = compute_tag; + + assign tag_buf_read_addr = {compute_tag_delayed, buf_read_addr}; + + register_sync #(BUF_DATA_WIDTH) + buf_read_data_delay (clk, reset, _buf_read_data, buf_read_data); + + wbuf #( + .TAG_W ( TAG_W ), + .BUF_ADDR_WIDTH ( TAG_BUF_ADDR_W ), + .ARRAY_N ( ARRAY_N ), + .ARRAY_M ( ARRAY_M ), + .MEM_DATA_WIDTH ( AXI_DATA_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ) + ) buf_ram ( + .clk ( clk ), + .reset ( reset ), + .mem_write_addr ( tag_mem_write_addr ), + .mem_write_req ( mem_write_req ), + .mem_write_data ( mem_write_data ), + .buf_read_addr ( tag_buf_read_addr ), + .buf_read_req ( buf_read_req ), + .buf_read_data ( _buf_read_data ) + ); +//============================================================================== + + +//============================================================================== + +`ifdef COCOTB_SIM + integer wr_req_count=0; + integer rd_req_count=0; + integer missed_rd_req_count=0; + integer req_count; + + always @(posedge clk) + if (reset) + wr_req_count <= 0; + else + wr_req_count <= wr_req_count + axi_wr_req; + + always @(posedge clk) + if (reset) + rd_req_count <= 0; + else + rd_req_count <= rd_req_count + axi_rd_req; + + always @(posedge clk) + if (reset) + missed_rd_req_count <= 0; + else + missed_rd_req_count <= missed_rd_req_count + (axi_rd_req && ~axi_rd_ready); + + always @(posedge clk) + begin + if (reset) req_count <= 0; + else req_count = req_count + (tag_req && tag_ready); + end +`endif + + +//============================================================= +// VCD +//============================================================= +`ifdef COCOTB_TOPLEVEL_mem_wrapper +initial begin + $dumpfile("mem_wrapper.vcd"); + $dumpvars(0, mem_wrapper); +end +`endif +//============================================================= +endmodule +// +// BBUF - Bias Buffer +// +// Hardik Sharma +// (hsharma@gatech.edu) +`timescale 1ns/1ps +module bbuf #( + parameter integer TAG_W = 2, // Log number of banks + parameter integer MEM_DATA_WIDTH = 64, + parameter integer ARRAY_M = 2, + parameter integer DATA_WIDTH = 32, + parameter integer BUF_ADDR_WIDTH = 10, + + parameter integer GROUP_SIZE = MEM_DATA_WIDTH / DATA_WIDTH, + parameter integer GROUP_ID_W = GROUP_SIZE == 1 ? 0 : $clog2(GROUP_SIZE), + parameter integer BUF_ID_W = $clog2(ARRAY_M) - GROUP_ID_W, + + parameter integer MEM_ADDR_WIDTH = BUF_ADDR_WIDTH + BUF_ID_W, + parameter integer BUF_DATA_WIDTH = ARRAY_M * DATA_WIDTH +) +( + input wire clk, + input wire reset, + + input wire mem_write_req, + input wire [ MEM_ADDR_WIDTH -1 : 0 ] mem_write_addr, + input wire [ MEM_DATA_WIDTH -1 : 0 ] mem_write_data, + + input wire buf_read_req, + input wire [ BUF_ADDR_WIDTH -1 : 0 ] buf_read_addr, + output wire [ BUF_DATA_WIDTH -1 : 0 ] buf_read_data +); + + genvar m; + generate + for (m=0; m Both operands (A and B) are matrices/vectors. Result is a matrix/vector. +// 1 -> Operand A is matrix/vector. Operand B is scalar. Result is a matrix/vector. +// op: +// 00 -> Addition +// 01 -> Subtraction +// 10 -> Multiplication +// +//The whole design can operate on 24xN matrices. +//Typically, to use this design, we'd break a large input +//matrix into 24 column sections and process the matrix +//section by section. The number of rows will be programmed +//in the "iterations" register in the design. + + +`define BFLOAT16 + +// IEEE Half Precision => EXPONENT = 5, MANTISSA = 10 +// BFLOAT16 => EXPONENT = 8, MANTISSA = 7 + +`ifdef BFLOAT16 +`define EXPONENT 8 +`define MANTISSA 7 +`else // for ieee half precision fp16 +`define EXPONENT 5 +`define MANTISSA 10 +`endif + +`define SIGN 1 +`define DWIDTH (`SIGN+`EXPONENT+`MANTISSA) + +`define AWIDTH 10 +`define MEM_SIZE 1024 +`define DESIGN_SIZE 12 +`define CU_SIZE 4 +`define MASK_WIDTH 4 +`define MEM_ACCESS_LATENCY 1 + +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 +`define ITERATIONS_WIDTH 32 + +`define REG_STDN_ADDR 32'h4 +`define REG_MATRIX_A_ADDR 32'he +`define REG_MATRIX_B_ADDR 32'h12 +`define REG_MATRIX_C_ADDR 32'h16 +`define REG_VALID_MASK_A_ADDR 32'h20 +`define REG_VALID_MASK_B_ADDR 32'h5c + +`define REG_ITERATIONS_ADDR 32'h40 + +//This is the pipeline depth of the PEs (adder/mult) +`define PE_PIPELINE_DEPTH 5 + +module eltwise_layer( + input clk, + input clk_mem, + input resetn, + input pe_resetn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output reg [`REG_DATAWIDTH-1:0] PRDATA, + output reg PREADY, + input [`DWIDTH-1:0] scalar_inp, + input mode, // mode==0 -> vector/matrix, mode==1 -> scalar + input [1:0] op, //op==11 -> Mul, op==01 -> Sub, op==00 -> Add + input [7:0] bram_select, + input [`AWIDTH-1:0] bram_addr_ext, + output reg [`CU_SIZE*`DWIDTH-1:0] bram_rdata_ext, + input [`CU_SIZE*`DWIDTH-1:0] bram_wdata_ext, + input [`CU_SIZE-1:0] bram_we_ext +); + + + wire PCLK; + assign PCLK = clk; + wire PRESETn; + assign PRESETn = resetn; + reg start_reg; + reg clear_done_reg; + + //Dummy register to sync all other invalid/unimplemented addresses + reg [`REG_DATAWIDTH-1:0] reg_dummy; + + reg [`AWIDTH-1:0] bram_addr_a_0_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_a_0_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_a_0_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_0_ext; + + reg [`AWIDTH-1:0] bram_addr_a_2_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_a_2_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_a_2_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_2_ext; + + reg [`AWIDTH-1:0] bram_addr_a_4_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_a_4_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_a_4_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_4_ext; + + reg [`AWIDTH-1:0] bram_addr_a_1_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_a_1_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_a_1_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_1_ext; + + reg [`AWIDTH-1:0] bram_addr_a_3_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_a_3_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_a_3_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_3_ext; + + reg [`AWIDTH-1:0] bram_addr_a_5_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_a_5_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_a_5_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_5_ext; + + + reg [`AWIDTH-1:0] bram_addr_b_0_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_b_0_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_b_0_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_0_ext; + + reg [`AWIDTH-1:0] bram_addr_b_1_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_b_1_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_b_1_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_1_ext; + + reg [`AWIDTH-1:0] bram_addr_b_2_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_b_2_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_b_2_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_2_ext; + + reg [`AWIDTH-1:0] bram_addr_b_3_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_b_3_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_b_3_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_3_ext; + + reg [`AWIDTH-1:0] bram_addr_b_4_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_b_4_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_b_4_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_4_ext; + + reg [`AWIDTH-1:0] bram_addr_b_5_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_b_5_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_b_5_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_5_ext; + + reg [`AWIDTH-1:0] bram_addr_c_0_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_c_0_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_c_0_ext; + reg [`MASK_WIDTH-1:0] bram_we_c_0_ext; + + reg [`AWIDTH-1:0] bram_addr_c_1_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_c_1_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_c_1_ext; + reg [`MASK_WIDTH-1:0] bram_we_c_1_ext; + + reg [`AWIDTH-1:0] bram_addr_c_2_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_c_2_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_c_2_ext; + reg [`MASK_WIDTH-1:0] bram_we_c_2_ext; + + reg [`AWIDTH-1:0] bram_addr_c_3_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_c_3_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_c_3_ext; + reg [`MASK_WIDTH-1:0] bram_we_c_3_ext; + + reg [`AWIDTH-1:0] bram_addr_c_4_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_c_4_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_c_4_ext; + reg [`MASK_WIDTH-1:0] bram_we_c_4_ext; + + reg [`AWIDTH-1:0] bram_addr_c_5_ext; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_c_5_ext; + reg [`CU_SIZE*`DWIDTH-1:0] bram_wdata_c_5_ext; + reg [`MASK_WIDTH-1:0] bram_we_c_5_ext; + + wire [`AWIDTH-1:0] bram_addr_a_0; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_a_0; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_a_0; + wire [`MASK_WIDTH-1:0] bram_we_a_0; + wire bram_en_a_0; + + wire [`AWIDTH-1:0] bram_addr_a_2; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_a_2; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_a_2; + wire [`MASK_WIDTH-1:0] bram_we_a_2; + wire bram_en_a_2; + + wire [`AWIDTH-1:0] bram_addr_a_4; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_a_4; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_a_4; + wire [`MASK_WIDTH-1:0] bram_we_a_4; + wire bram_en_a_4; + + wire [`AWIDTH-1:0] bram_addr_a_1; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_a_1; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_a_1; + wire [`MASK_WIDTH-1:0] bram_we_a_1; + wire bram_en_a_1; + + wire [`AWIDTH-1:0] bram_addr_a_3; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_a_3; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_a_3; + wire [`MASK_WIDTH-1:0] bram_we_a_3; + wire bram_en_a_3; + + wire [`AWIDTH-1:0] bram_addr_a_5; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_a_5; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_a_5; + wire [`MASK_WIDTH-1:0] bram_we_a_5; + wire bram_en_a_5; + + wire [`AWIDTH-1:0] bram_addr_b_0; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_b_0; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_b_0; + wire [`MASK_WIDTH-1:0] bram_we_b_0; + wire bram_en_b_0; + + wire [`AWIDTH-1:0] bram_addr_b_1; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_b_1; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_b_1; + wire [`MASK_WIDTH-1:0] bram_we_b_1; + wire bram_en_b_1; + + wire [`AWIDTH-1:0] bram_addr_b_2; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_b_2; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_b_2; + wire [`MASK_WIDTH-1:0] bram_we_b_2; + wire bram_en_b_2; + + wire [`AWIDTH-1:0] bram_addr_b_3; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_b_3; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_b_3; + wire [`MASK_WIDTH-1:0] bram_we_b_3; + wire bram_en_b_3; + + wire [`AWIDTH-1:0] bram_addr_b_4; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_b_4; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_b_4; + wire [`MASK_WIDTH-1:0] bram_we_b_4; + wire bram_en_b_4; + + wire [`AWIDTH-1:0] bram_addr_b_5; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_b_5; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_b_5; + wire [`MASK_WIDTH-1:0] bram_we_b_5; + wire bram_en_b_5; + + wire [`AWIDTH-1:0] bram_addr_c_0; + wire [`AWIDTH-1:0] bram_addr_c_1; + wire [`AWIDTH-1:0] bram_addr_c_2; + wire [`AWIDTH-1:0] bram_addr_c_3; + wire [`AWIDTH-1:0] bram_addr_c_4; + wire [`AWIDTH-1:0] bram_addr_c_5; + + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_c_0; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_c_1; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_c_2; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_c_3; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_c_4; + wire [`CU_SIZE*`DWIDTH-1:0] bram_wdata_c_5; + + wire [`MASK_WIDTH-1:0] bram_we_c_0; + wire [`MASK_WIDTH-1:0] bram_we_c_1; + wire [`MASK_WIDTH-1:0] bram_we_c_2; + wire [`MASK_WIDTH-1:0] bram_we_c_3; + wire [`MASK_WIDTH-1:0] bram_we_c_4; + wire [`MASK_WIDTH-1:0] bram_we_c_5; + + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_c_0; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_c_1; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_c_2; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_c_3; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_c_4; + wire [`CU_SIZE*`DWIDTH-1:0] bram_rdata_c_5; + + always @ (posedge clk) begin + case (bram_select) + + 0: begin + bram_addr_a_0_ext <= bram_addr_ext; + bram_wdata_a_0_ext <= bram_wdata_ext; + bram_we_a_0_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_a_0_ext; + end + + 1: begin + bram_addr_a_2_ext <= bram_addr_ext; + bram_wdata_a_2_ext <= bram_wdata_ext; + bram_we_a_2_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_a_2_ext; + end + + 2: begin + bram_addr_a_4_ext <= bram_addr_ext; + bram_wdata_a_4_ext <= bram_wdata_ext; + bram_we_a_4_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_a_4_ext; + end + + 3: begin + bram_addr_a_1_ext <= bram_addr_ext; + bram_wdata_a_1_ext <= bram_wdata_ext; + bram_we_a_1_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_a_1_ext; + end + + 4: begin + bram_addr_a_3_ext <= bram_addr_ext; + bram_wdata_a_3_ext <= bram_wdata_ext; + bram_we_a_3_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_a_3_ext; + end + + 5: begin + bram_addr_a_5_ext <= bram_addr_ext; + bram_wdata_a_5_ext <= bram_wdata_ext; + bram_we_a_5_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_a_5_ext; + end + + 6: begin + bram_addr_b_0_ext = bram_addr_ext; + bram_wdata_b_0_ext = bram_wdata_ext; + bram_we_b_0_ext = bram_we_ext; + bram_rdata_ext = bram_rdata_b_0_ext; + end + + 7: begin + bram_addr_b_1_ext <= bram_addr_ext; + bram_wdata_b_1_ext <= bram_wdata_ext; + bram_we_b_1_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_b_1_ext; + end + + 8: begin + bram_addr_b_2_ext <= bram_addr_ext; + bram_wdata_b_2_ext <= bram_wdata_ext; + bram_we_b_2_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_b_2_ext; + end + + 9: begin + bram_addr_b_3_ext <= bram_addr_ext; + bram_wdata_b_3_ext <= bram_wdata_ext; + bram_we_b_3_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_b_3_ext; + end + + 10: begin + bram_addr_b_4_ext <= bram_addr_ext; + bram_wdata_b_4_ext <= bram_wdata_ext; + bram_we_b_4_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_b_4_ext; + end + + 11: begin + bram_addr_b_5_ext <= bram_addr_ext; + bram_wdata_b_5_ext <= bram_wdata_ext; + bram_we_b_5_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_b_5_ext; + end + + 12: begin + bram_addr_c_0_ext <= bram_addr_ext; + bram_wdata_c_0_ext <= bram_wdata_ext; + bram_we_c_0_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_c_0_ext; + end + + 13: begin + bram_addr_c_1_ext <= bram_addr_ext; + bram_wdata_c_1_ext <= bram_wdata_ext; + bram_we_c_1_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_c_1_ext; + end + + 14: begin + bram_addr_c_2_ext <= bram_addr_ext; + bram_wdata_c_2_ext <= bram_wdata_ext; + bram_we_c_2_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_c_2_ext; + end + + 15: begin + bram_addr_c_3_ext <= bram_addr_ext; + bram_wdata_c_3_ext <= bram_wdata_ext; + bram_we_c_3_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_c_3_ext; + end + + 16: begin + bram_addr_c_4_ext <= bram_addr_ext; + bram_wdata_c_4_ext <= bram_wdata_ext; + bram_we_c_4_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_c_4_ext; + end + + 17: begin + bram_addr_c_5_ext <= bram_addr_ext; + bram_wdata_c_5_ext <= bram_wdata_ext; + bram_we_c_5_ext <= bram_we_ext; + bram_rdata_ext <= bram_rdata_c_5_ext; + end + + default: begin + bram_addr_c_5_ext <= bram_addr_ext; + bram_wdata_c_5_ext <= bram_wdata_ext; + bram_we_c_5_ext <= bram_we_ext; + bram_rdata_ext <= 0; + end + endcase + end + +///////////////////////////////////////////////// +// BRAMs to store matrix A +///////////////////////////////////////////////// + + + // BRAM matrix A 0 +ram matrix_A_0( + .addr0(bram_addr_a_0), + .d0(bram_wdata_a_0), + .we0(bram_we_a_0), + .q0(bram_rdata_a_0), + .addr1(bram_addr_a_0_ext), + .d1(bram_wdata_a_0_ext), + .we1(bram_we_a_0_ext), + .q1(bram_rdata_a_0_ext), + .clk(clk_mem)); + + // BRAM matrix A 2 +ram matrix_A_2( + .addr0(bram_addr_a_2), + .d0(bram_wdata_a_2), + .we0(bram_we_a_2), + .q0(bram_rdata_a_2), + .addr1(bram_addr_a_2_ext), + .d1(bram_wdata_a_2_ext), + .we1(bram_we_a_2_ext), + .q1(bram_rdata_a_2_ext), + .clk(clk_mem)); + + // BRAM matrix A 4 +ram matrix_A_4( + .addr0(bram_addr_a_4), + .d0(bram_wdata_a_4), + .we0(bram_we_a_4), + .q0(bram_rdata_a_4), + .addr1(bram_addr_a_4_ext), + .d1(bram_wdata_a_4_ext), + .we1(bram_we_a_4_ext), + .q1(bram_rdata_a_4_ext), + .clk(clk_mem)); + + + // BRAM matrix A 1 +ram matrix_A_1( + .addr0(bram_addr_a_1), + .d0(bram_wdata_a_1), + .we0(bram_we_a_1), + .q0(bram_rdata_a_1), + .addr1(bram_addr_a_1_ext), + .d1(bram_wdata_a_1_ext), + .we1(bram_we_a_1_ext), + .q1(bram_rdata_a_1_ext), + .clk(clk_mem)); + + // BRAM matrix A 3 +ram matrix_A_3( + .addr0(bram_addr_a_3), + .d0(bram_wdata_a_3), + .we0(bram_we_a_3), + .q0(bram_rdata_a_3), + .addr1(bram_addr_a_3_ext), + .d1(bram_wdata_a_3_ext), + .we1(bram_we_a_3_ext), + .q1(bram_rdata_a_3_ext), + .clk(clk_mem)); + + // BRAM matrix A 5 +ram matrix_A_5( + .addr0(bram_addr_a_5), + .d0(bram_wdata_a_5), + .we0(bram_we_a_5), + .q0(bram_rdata_a_5), + .addr1(bram_addr_a_5_ext), + .d1(bram_wdata_a_5_ext), + .we1(bram_we_a_5_ext), + .q1(bram_rdata_a_5_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////// +// BRAMs to store matrix B +///////////////////////////////////////////////// + + + // BRAM matrix B 0 +ram matrix_B_0( + .addr0(bram_addr_b_0), + .d0(bram_wdata_b_0), + .we0(bram_we_b_0), + .q0(bram_rdata_b_0), + .addr1(bram_addr_b_0_ext), + .d1(bram_wdata_b_0_ext), + .we1(bram_we_b_0_ext), + .q1(bram_rdata_b_0_ext), + .clk(clk_mem)); + + // BRAM matrix B 1 +ram matrix_B_1( + .addr0(bram_addr_b_1), + .d0(bram_wdata_b_1), + .we0(bram_we_b_1), + .q0(bram_rdata_b_1), + .addr1(bram_addr_b_1_ext), + .d1(bram_wdata_b_1_ext), + .we1(bram_we_b_1_ext), + .q1(bram_rdata_b_1_ext), + .clk(clk_mem)); + + // BRAM matrix B 2 +ram matrix_B_2( + .addr0(bram_addr_b_2), + .d0(bram_wdata_b_2), + .we0(bram_we_b_2), + .q0(bram_rdata_b_2), + .addr1(bram_addr_b_2_ext), + .d1(bram_wdata_b_2_ext), + .we1(bram_we_b_2_ext), + .q1(bram_rdata_b_2_ext), + .clk(clk_mem)); + + + // BRAM matrix B 3 +ram matrix_B_3( + .addr0(bram_addr_b_3), + .d0(bram_wdata_b_3), + .we0(bram_we_b_3), + .q0(bram_rdata_b_3), + .addr1(bram_addr_b_3_ext), + .d1(bram_wdata_b_3_ext), + .we1(bram_we_b_3_ext), + .q1(bram_rdata_b_3_ext), + .clk(clk_mem)); + + // BRAM matrix B 4 +ram matrix_B_4( + .addr0(bram_addr_b_4), + .d0(bram_wdata_b_4), + .we0(bram_we_b_4), + .q0(bram_rdata_b_4), + .addr1(bram_addr_b_4_ext), + .d1(bram_wdata_b_4_ext), + .we1(bram_we_b_4_ext), + .q1(bram_rdata_b_4_ext), + .clk(clk_mem)); + + + // BRAM matrix B 5 +ram matrix_B_5( + .addr0(bram_addr_b_5), + .d0(bram_wdata_b_5), + .we0(bram_we_b_5), + .q0(bram_rdata_b_5), + .addr1(bram_addr_b_5_ext), + .d1(bram_wdata_b_5_ext), + .we1(bram_we_b_5_ext), + .q1(bram_rdata_b_5_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////// +// BRAMs to store matrix C +///////////////////////////////////////////////// + + + // BRAM matrix C 0 +ram matrix_C_0( + .addr0(bram_addr_c_0), + .d0(bram_wdata_c_0), + .we0(bram_we_c_0), + .q0(bram_rdata_c_0), + .addr1(bram_addr_c_0_ext), + .d1(bram_wdata_c_0_ext), + .we1(bram_we_c_0_ext), + .q1(bram_rdata_c_0_ext), + .clk(clk_mem)); + + // BRAM matrix C 1 +ram matrix_C_1( + .addr0(bram_addr_c_1), + .d0(bram_wdata_c_1), + .we0(bram_we_c_1), + .q0(bram_rdata_c_1), + .addr1(bram_addr_c_1_ext), + .d1(bram_wdata_c_1_ext), + .we1(bram_we_c_1_ext), + .q1(bram_rdata_c_1_ext), + .clk(clk_mem)); + + // BRAM matrix C 2 +ram matrix_C_2( + .addr0(bram_addr_c_2), + .d0(bram_wdata_c_2), + .we0(bram_we_c_2), + .q0(bram_rdata_c_2), + .addr1(bram_addr_c_2_ext), + .d1(bram_wdata_c_2_ext), + .we1(bram_we_c_2_ext), + .q1(bram_rdata_c_2_ext), + .clk(clk_mem)); + + + // BRAM matrix C 3 +ram matrix_C_3( + .addr0(bram_addr_c_3), + .d0(bram_wdata_c_3), + .we0(bram_we_c_3), + .q0(bram_rdata_c_3), + .addr1(bram_addr_c_3_ext), + .d1(bram_wdata_c_3_ext), + .we1(bram_we_c_3_ext), + .q1(bram_rdata_c_3_ext), + .clk(clk_mem)); + + // BRAM matrix C 4 +ram matrix_C_4( + .addr0(bram_addr_c_4), + .d0(bram_wdata_c_4), + .we0(bram_we_c_4), + .q0(bram_rdata_c_4), + .addr1(bram_addr_c_4_ext), + .d1(bram_wdata_c_4_ext), + .we1(bram_we_c_4_ext), + .q1(bram_rdata_c_4_ext), + .clk(clk_mem)); + + + // BRAM matrix C 5 +ram matrix_C_5( + .addr0(bram_addr_c_5), + .d0(bram_wdata_c_5), + .we0(bram_we_c_5), + .q0(bram_rdata_c_5), + .addr1(bram_addr_c_5_ext), + .d1(bram_wdata_c_5_ext), + .we1(bram_we_c_5_ext), + .q1(bram_rdata_c_5_ext), + .clk(clk_mem)); + +reg start_eltwise_op; +wire done_eltwise_op; + +reg [3:0] state; + +//////////////////////////////////////////////////////////////// +// Control logic +//////////////////////////////////////////////////////////////// + always @( posedge clk) begin + if (resetn == 1'b0) begin + state <= 4'b0000; + start_eltwise_op <= 1'b0; + end + else begin + case (state) + + 4'b0000: begin + start_eltwise_op <= 1'b0; + if (start_reg == 1'b1) begin + state <= 4'b0001; + end else begin + state <= 4'b0000; + end + end + + 4'b0001: begin + start_eltwise_op <= 1'b1; + state <= 4'b1010; + end + + 4'b1010: begin + if (done_eltwise_op == 1'b1) begin + start_eltwise_op <= 1'b0; + state <= 4'b1000; + end + else begin + state <= 4'b1010; + end + end + + 4'b1000: begin + if (clear_done_reg == 1'b1) begin + state <= 4'b0000; + end + else begin + state <= 4'b1000; + end + end + endcase + end + end + +reg [1:0] state_apb; +`define IDLE 2'b00 +`define W_ENABLE 2'b01 +`define R_ENABLE 2'b10 + +reg [`AWIDTH-1:0] address_mat_a; +reg [`AWIDTH-1:0] address_mat_b; +reg [`AWIDTH-1:0] address_mat_c; +reg [`MASK_WIDTH-1:0] validity_mask_a; +reg [`MASK_WIDTH-1:0] validity_mask_b; +reg [`ITERATIONS_WIDTH-1:0] iterations; + +//////////////////////////////////////////////////////////////// +// Configuration logic +//////////////////////////////////////////////////////////////// +always @(posedge PCLK) begin + if (PRESETn == 0) begin + state_apb <= `IDLE; + PRDATA <= 0; + PREADY <= 0; + address_mat_a <= 0; + address_mat_b <= 0; + address_mat_c <= 0; + validity_mask_a <= {`MASK_WIDTH{1'b1}}; + validity_mask_b <= {`MASK_WIDTH{1'b1}}; + end + + else begin + case (state_apb) + `IDLE : begin + PRDATA <= 0; + if (PSEL) begin + if (PWRITE) begin + state_apb <= `W_ENABLE; + end + else begin + state_apb <= `R_ENABLE; + end + end + PREADY <= 0; + end + + `W_ENABLE : begin + if (PSEL && PWRITE && PENABLE) begin + case (PADDR) + `REG_STDN_ADDR : begin + start_reg <= PWDATA[0]; + clear_done_reg <= PWDATA[31]; + end + `REG_MATRIX_A_ADDR : address_mat_a <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_B_ADDR : address_mat_b <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_C_ADDR : address_mat_c <= PWDATA[`AWIDTH-1:0]; + `REG_VALID_MASK_A_ADDR: begin + validity_mask_a <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_ADDR: begin + validity_mask_b <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_ITERATIONS_ADDR: iterations <= PWDATA[`ITERATIONS_WIDTH-1:0]; + default : reg_dummy <= PWDATA; //sink writes to a dummy register + endcase + PREADY <=1; + end + state_apb <= `IDLE; + end + + `R_ENABLE : begin + if (PSEL && !PWRITE && PENABLE) begin + PREADY <= 1; + case (PADDR) + `REG_STDN_ADDR : PRDATA <= {done_eltwise_op, 30'b0, start_eltwise_op}; + `REG_MATRIX_A_ADDR : PRDATA <= address_mat_a; + `REG_MATRIX_B_ADDR : PRDATA <= address_mat_b; + `REG_MATRIX_C_ADDR : PRDATA <= address_mat_c; + `REG_VALID_MASK_A_ADDR: PRDATA <= validity_mask_a; + `REG_VALID_MASK_B_ADDR: PRDATA <= validity_mask_b; + `REG_ITERATIONS_ADDR: PRDATA <= iterations; + default : PRDATA <= reg_dummy; //read the dummy register for undefined addresses + endcase + end + state_apb <= `IDLE; + end + default: begin + state_apb <= `IDLE; + end + endcase + end +end + +wire reset; +assign reset = ~resetn; +wire pe_reset; +assign pe_reset = ~pe_resetn; + + wire c_data_0_available; + wire c_data_1_available; + wire c_data_2_available; + wire c_data_3_available; + wire c_data_4_available; + wire c_data_5_available; + + assign bram_wdata_a_0 = {`CU_SIZE*`DWIDTH{1'b0}}; + assign bram_en_a_0 = 1'b1; + assign bram_we_a_0 = {`MASK_WIDTH{1'b0}}; + + assign bram_wdata_a_1 = {`CU_SIZE*`DWIDTH{1'b0}}; + assign bram_en_a_1 = 1'b1; + assign bram_we_a_1 = {`MASK_WIDTH{1'b0}}; + + assign bram_wdata_a_2 = {`CU_SIZE*`DWIDTH{1'b0}}; + assign bram_en_a_2 = 1'b1; + assign bram_we_a_2 = {`MASK_WIDTH{1'b0}}; + + assign bram_wdata_a_3 = {`CU_SIZE*`DWIDTH{1'b0}}; + assign bram_en_a_3 = 1'b1; + assign bram_we_a_3 = {`MASK_WIDTH{1'b0}}; + + assign bram_wdata_a_4 = {`CU_SIZE*`DWIDTH{1'b0}}; + assign bram_en_a_4 = 1'b1; + assign bram_we_a_4 = {`MASK_WIDTH{1'b0}}; + + assign bram_wdata_a_5 = {`CU_SIZE*`DWIDTH{1'b0}}; + assign bram_en_a_5 = 1'b1; + assign bram_we_a_5 = {`MASK_WIDTH{1'b0}}; + + assign bram_wdata_b_0 = {`CU_SIZE*`DWIDTH{1'b0}}; + assign bram_en_b_0 = 1'b1; + assign bram_we_b_0 = {`MASK_WIDTH{1'b0}}; + + assign bram_wdata_b_1 = {`CU_SIZE*`DWIDTH{1'b0}}; + assign bram_en_b_1 = 1'b1; + assign bram_we_b_1 = {`MASK_WIDTH{1'b0}}; + + assign bram_wdata_b_2 = {`CU_SIZE*`DWIDTH{1'b0}}; + assign bram_en_b_2 = 1'b1; + assign bram_we_b_2 = {`MASK_WIDTH{1'b0}}; + + assign bram_wdata_b_3 = {`CU_SIZE*`DWIDTH{1'b0}}; + assign bram_en_b_3 = 1'b1; + assign bram_we_b_3 = {`MASK_WIDTH{1'b0}}; + + assign bram_wdata_b_4 = {`CU_SIZE*`DWIDTH{1'b0}}; + assign bram_en_b_4 = 1'b1; + assign bram_we_b_4 = {`MASK_WIDTH{1'b0}}; + + assign bram_wdata_b_5 = {`CU_SIZE*`DWIDTH{1'b0}}; + assign bram_en_b_5 = 1'b1; + assign bram_we_b_5 = {`MASK_WIDTH{1'b0}}; + + assign bram_we_c_0 = (c_data_0_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + assign bram_we_c_2 = (c_data_2_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + assign bram_we_c_4 = (c_data_4_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + assign bram_we_c_1 = (c_data_1_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + assign bram_we_c_3 = (c_data_3_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + assign bram_we_c_5 = (c_data_5_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + + ///////////////////////////////////////////////// + // ORing all done signals + ///////////////////////////////////////////////// + wire done_eltwise_op_0; + wire done_eltwise_op_1; + wire done_eltwise_op_2; + wire done_eltwise_op_3; + wire done_eltwise_op_4; + wire done_eltwise_op_5; + + assign done_eltwise_op = + done_eltwise_op_0 | + done_eltwise_op_1 | + done_eltwise_op_2 | + done_eltwise_op_3 | + done_eltwise_op_4 | + done_eltwise_op_5 ; + + ///////////////////////////////////////////////// + // Code to allow for scalar mode + ///////////////////////////////////////////////// + + wire [`CU_SIZE*`DWIDTH-1:0] b_data_0; + wire [`CU_SIZE*`DWIDTH-1:0] b_data_1; + wire [`CU_SIZE*`DWIDTH-1:0] b_data_2; + wire [`CU_SIZE*`DWIDTH-1:0] b_data_3; + wire [`CU_SIZE*`DWIDTH-1:0] b_data_4; + wire [`CU_SIZE*`DWIDTH-1:0] b_data_5; + + assign b_data_0 = mode ? bram_rdata_b_0 : {`CU_SIZE{scalar_inp}}; + assign b_data_1 = mode ? bram_rdata_b_1 : {`CU_SIZE{scalar_inp}}; + assign b_data_2 = mode ? bram_rdata_b_2 : {`CU_SIZE{scalar_inp}}; + assign b_data_3 = mode ? bram_rdata_b_3 : {`CU_SIZE{scalar_inp}}; + assign b_data_4 = mode ? bram_rdata_b_4 : {`CU_SIZE{scalar_inp}}; + assign b_data_5 = mode ? bram_rdata_b_5 : {`CU_SIZE{scalar_inp}}; + + ///////////////////////////////////////////////// + // Compute Unit 0 + ///////////////////////////////////////////////// + +eltwise_cu u_eltwise_cu_0( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_eltwise_op(start_eltwise_op), + .done_eltwise_op(done_eltwise_op_0), + .count(iterations), + .op(op), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .a_data(bram_rdata_a_0), + .b_data(b_data_0), + .c_data_out(bram_wdata_c_0), + .a_addr(bram_addr_a_0), + .b_addr(bram_addr_b_0), + .c_addr(bram_addr_c_0), + .c_data_available(c_data_0_available), + .validity_mask_a(4'b1111), + .validity_mask_b(4'b1111) +); + + ///////////////////////////////////////////////// + // Compute Unit 1 + ///////////////////////////////////////////////// + +eltwise_cu u_eltwise_cu_1( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_eltwise_op(start_eltwise_op), + .done_eltwise_op(done_eltwise_op_1), + .count(iterations), + .op(op), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .a_data(bram_rdata_a_1), + .b_data(b_data_1), + .c_data_out(bram_wdata_c_1), + .a_addr(bram_addr_a_1), + .b_addr(bram_addr_b_1), + .c_addr(bram_addr_c_1), + .c_data_available(c_data_1_available), + .validity_mask_a(4'b1111), + .validity_mask_b(4'b1111) +); + + ///////////////////////////////////////////////// + // Compute Unit 2 + ///////////////////////////////////////////////// + +eltwise_cu u_eltwise_cu_2( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_eltwise_op(start_eltwise_op), + .done_eltwise_op(done_eltwise_op_2), + .count(iterations), + .op(op), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .a_data(bram_rdata_a_2), + .b_data(b_data_2), + .c_data_out(bram_wdata_c_2), + .a_addr(bram_addr_a_2), + .b_addr(bram_addr_b_2), + .c_addr(bram_addr_c_2), + .c_data_available(c_data_2_available), + .validity_mask_a(4'b1111), + .validity_mask_b(4'b1111) +); + + ///////////////////////////////////////////////// + // Compute Unit 3 + ///////////////////////////////////////////////// + +eltwise_cu u_eltwise_cu_3( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_eltwise_op(start_eltwise_op), + .done_eltwise_op(done_eltwise_op_3), + .count(iterations), + .op(op), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .a_data(bram_rdata_a_3), + .b_data(b_data_3), + .c_data_out(bram_wdata_c_3), + .a_addr(bram_addr_a_3), + .b_addr(bram_addr_b_3), + .c_addr(bram_addr_c_3), + .c_data_available(c_data_3_available), + .validity_mask_a(4'b1111), + .validity_mask_b(4'b1111) +); + + ///////////////////////////////////////////////// + // Compute Unit 4 + ///////////////////////////////////////////////// + +eltwise_cu u_eltwise_cu_4( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_eltwise_op(start_eltwise_op), + .done_eltwise_op(done_eltwise_op_4), + .count(iterations), + .op(op), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .a_data(bram_rdata_a_4), + .b_data(b_data_4), + .c_data_out(bram_wdata_c_4), + .a_addr(bram_addr_a_4), + .b_addr(bram_addr_b_4), + .c_addr(bram_addr_c_4), + .c_data_available(c_data_4_available), + .validity_mask_a(4'b1111), + .validity_mask_b(4'b1111) +); + + ///////////////////////////////////////////////// + // Compute Unit 5 + ///////////////////////////////////////////////// + +eltwise_cu u_eltwise_cu_5( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_eltwise_op(start_eltwise_op), + .done_eltwise_op(done_eltwise_op_5), + .count(iterations), + .op(op), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .a_data(bram_rdata_a_5), + .b_data(b_data_5), + .c_data_out(bram_wdata_c_5), + .a_addr(bram_addr_a_5), + .b_addr(bram_addr_b_5), + .c_addr(bram_addr_c_5), + .c_data_available(c_data_5_available), + .validity_mask_a(4'b0011), + .validity_mask_b(4'b0011) +); + +endmodule + + +////////////////////////////////// +////////////////////////////////// +//Dual port RAM +////////////////////////////////// +////////////////////////////////// +module ram ( + addr0, + d0, + we0, + q0, + addr1, + d1, + we1, + q1, + clk); + +input [`AWIDTH-1:0] addr0; +input [`AWIDTH-1:0] addr1; +input [`CU_SIZE*`DWIDTH-1:0] d0; +input [`CU_SIZE*`DWIDTH-1:0] d1; +input [`CU_SIZE-1:0] we0; +input [`CU_SIZE-1:0] we1; +output [`CU_SIZE*`DWIDTH-1:0] q0; +output [`CU_SIZE*`DWIDTH-1:0] q1; +input clk; + +genvar i; + +generate +`ifdef QUARTUS + for (i=0;i<`CU_SIZE;i=i+1) begin: gen_dpram +`else + for (i=0;i<`CU_SIZE;i=i+1) begin +`endif + dpram_original #(.AWIDTH(`AWIDTH),.DWIDTH(`DWIDTH),.NUM_WORDS(1<<`AWIDTH)) dp1 (.clk(clk),.address_a(addr0),.address_b(addr1),.wren_a(we0[i]),.wren_b(we1[i]),.data_a(d0[i*`DWIDTH +: `DWIDTH]),.data_b(d1[i*`DWIDTH +: `DWIDTH]),.out_a(q0[i*`DWIDTH +: `DWIDTH]),.out_b(q1[i*`DWIDTH +: `DWIDTH])); + end +endgenerate + +endmodule + +module dpram_original ( + clk, + address_a, + address_b, + wren_a, + wren_b, + data_a, + data_b, + out_a, + out_b +); +parameter AWIDTH=10; +parameter NUM_WORDS=1024; +parameter DWIDTH=32; +input clk; +input [(AWIDTH-1):0] address_a; +input [(AWIDTH-1):0] address_b; +input wren_a; +input wren_b; +input [(DWIDTH-1):0] data_a; +input [(DWIDTH-1):0] data_b; +output reg [(DWIDTH-1):0] out_a; +output reg [(DWIDTH-1):0] out_b; + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram[NUM_WORDS-1:0]; +always @ (posedge clk) begin + if (wren_a) begin + ram[address_a] <= data_a; + end + out_a <= ram[address_a]; +end + +always @ (posedge clk) begin + if (wren_b) begin + ram[address_b] <= data_b; + end + out_b <= ram[address_b]; +end + +`else + +defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; +defparam u_dual_port_ram.DATA_WIDTH = DWIDTH; + +dual_port_ram u_dual_port_ram( +.addr1(address_a), +.we1(wren_a), +.data1(data_a), +.out1(out_a), +.addr2(address_b), +.we2(wren_b), +.data2(data_b), +.out2(out_b), +.clk(clk) +); + +`endif +endmodule + + +////////////////////////////////// +////////////////////////////////// +// Elementwise compute unit +////////////////////////////////// +////////////////////////////////// +module eltwise_cu( + clk, + reset, + pe_reset, + start_eltwise_op, + done_eltwise_op, + count, + op, + address_mat_a, + address_mat_b, + address_mat_c, + a_data, + b_data, + c_data_out, + a_addr, + b_addr, + c_addr, + c_data_available, + validity_mask_a, + validity_mask_b +); + + input clk; + input reset; + input pe_reset; + input start_eltwise_op; + output done_eltwise_op; + input [`ITERATIONS_WIDTH-1:0] count; + input [1:0] op; + input [`AWIDTH-1:0] address_mat_a; + input [`AWIDTH-1:0] address_mat_b; + input [`AWIDTH-1:0] address_mat_c; + input [`CU_SIZE*`DWIDTH-1:0] a_data; + input [`CU_SIZE*`DWIDTH-1:0] b_data; + output [`CU_SIZE*`DWIDTH-1:0] c_data_out; + output [`AWIDTH-1:0] a_addr; + output [`AWIDTH-1:0] b_addr; + output [`AWIDTH-1:0] c_addr; + output c_data_available; + input [`MASK_WIDTH-1:0] validity_mask_a; + input [`MASK_WIDTH-1:0] validity_mask_b; + +wire [`DWIDTH-1:0] out0; +wire [`DWIDTH-1:0] out1; +wire [`DWIDTH-1:0] out2; +wire [`DWIDTH-1:0] out3; + +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; + +////////////////////////////////////////////////////////////////////////// +// Logic for done +////////////////////////////////////////////////////////////////////////// +wire [7:0] clk_cnt_for_done; +reg [31:0] clk_cnt; +reg done_eltwise_op; + +assign clk_cnt_for_done = + `PE_PIPELINE_DEPTH + //This is dependent on the pipeline depth of the PEs + count //The number of iterations asked for this compute unit + ; + +always @(posedge clk) begin + if (reset || ~start_eltwise_op) begin + clk_cnt <= 0; + done_eltwise_op <= 0; + end + else if (clk_cnt == clk_cnt_for_done) begin + done_eltwise_op <= 1; + clk_cnt <= clk_cnt + 1; + end + else if (done_eltwise_op == 0) begin + clk_cnt <= clk_cnt + 1; + end + else begin + done_eltwise_op <= 0; + clk_cnt <= clk_cnt + 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Instantiation of input logic +////////////////////////////////////////////////////////////////////////// +input_logic u_input_logic( +.clk(clk), +.reset(reset), +.start_eltwise_op(start_eltwise_op), +.count(count), +.a_addr(a_addr), +.b_addr(b_addr), +.address_mat_a(address_mat_a), +.address_mat_b(address_mat_b), +.a_data(a_data), +.b_data(b_data), +.a0_data(a0_data), +.a1_data(a1_data), +.a2_data(a2_data), +.a3_data(a3_data), +.b0_data(b0_data), +.b1_data(b1_data), +.b2_data(b2_data), +.b3_data(b3_data), +.validity_mask_a(validity_mask_a), +.validity_mask_b(validity_mask_b) +); + +////////////////////////////////////////////////////////////////////////// +// Instantiation of the output logic +////////////////////////////////////////////////////////////////////////// +output_logic u_output_logic( +.clk(clk), +.reset(reset), +.start_eltwise_op(start_eltwise_op), +.done_eltwise_op(done_eltwise_op), +.address_mat_c(address_mat_c), +.c_data_out(c_data_out), +.c_addr(c_addr), +.c_data_available(c_data_available), +.out0(out0), +.out1(out1), +.out2(out2), +.out3(out3) +); + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +pe_array u_pe_array( +.reset(reset), +.clk(clk), +.pe_reset(pe_reset), +.op(op), +.a0(a0_data), +.a1(a1_data), +.a2(a2_data), +.a3(a3_data), +.b0(b0_data), +.b1(b1_data), +.b2(b2_data), +.b3(b3_data), +.out0(out0), +.out1(out1), +.out2(out2), +.out3(out3) +); + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Output logic +////////////////////////////////////////////////////////////////////////// +module output_logic( +clk, +reset, +start_eltwise_op, +done_eltwise_op, +address_mat_c, +c_data_out, +c_addr, +c_data_available, +out0, +out1, +out2, +out3 +); + +input clk; +input reset; +input start_eltwise_op; +input done_eltwise_op; +input [`AWIDTH-1:0] address_mat_c; +output [`CU_SIZE*`DWIDTH-1:0] c_data_out; +output [`AWIDTH-1:0] c_addr; +output c_data_available; +input [`DWIDTH-1:0] out0; +input [`DWIDTH-1:0] out1; +input [`DWIDTH-1:0] out2; +input [`DWIDTH-1:0] out3; + +reg c_data_available; +reg [`CU_SIZE*`DWIDTH-1:0] c_data_out; + +////////////////////////////////////////////////////////////////////////// +// Logic to capture matrix C data from the PEs and send to RAM +////////////////////////////////////////////////////////////////////////// + +reg [`AWIDTH-1:0] c_addr; +reg [7:0] cnt; + +always @(posedge clk) begin + if (reset | ~start_eltwise_op) begin + c_data_available <= 1'b0; + c_addr <= address_mat_c; + c_data_out <= 0; + cnt <= 0; + end + else if (cnt>`PE_PIPELINE_DEPTH) begin + c_data_available <= 1'b1; + c_addr <= c_addr+1; + c_data_out <= {out3, out2, out1, out0}; + cnt <= cnt + 1; + end else begin + cnt <= cnt + 1; + end +end + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Data setup +////////////////////////////////////////////////////////////////////////// +module input_logic( +clk, +reset, +start_eltwise_op, +count, +a_addr, +b_addr, +address_mat_a, +address_mat_b, +a_data, +b_data, +a0_data, +a1_data, +a2_data, +a3_data, +b0_data, +b1_data, +b2_data, +b3_data, +validity_mask_a, +validity_mask_b +); + +input clk; +input reset; +input start_eltwise_op; +input [`ITERATIONS_WIDTH-1:0] count; +output [`AWIDTH-1:0] a_addr; +output [`AWIDTH-1:0] b_addr; +input [`AWIDTH-1:0] address_mat_a; +input [`AWIDTH-1:0] address_mat_b; +input [`CU_SIZE*`DWIDTH-1:0] a_data; +input [`CU_SIZE*`DWIDTH-1:0] b_data; +output [`DWIDTH-1:0] a0_data; +output [`DWIDTH-1:0] a1_data; +output [`DWIDTH-1:0] a2_data; +output [`DWIDTH-1:0] a3_data; +output [`DWIDTH-1:0] b0_data; +output [`DWIDTH-1:0] b1_data; +output [`DWIDTH-1:0] b2_data; +output [`DWIDTH-1:0] b3_data; +input [`MASK_WIDTH-1:0] validity_mask_a; +input [`MASK_WIDTH-1:0] validity_mask_b; + +reg [7:0] iterations; + +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM A +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] a_addr; +reg a_mem_access; //flag that tells whether the compute unit is trying to access memory or not + +always @(posedge clk) begin + //else if (clk_cnt >= a_loc*`CU_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + if (reset || ~start_eltwise_op) begin + a_addr <= address_mat_a; + a_mem_access <= 0; + iterations <= 0; + end + + //else if ((clk_cnt >= a_loc*`CU_SIZE) && (clk_cnt < a_loc*`CU_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + else if (iterations <= count) begin + a_addr <= a_addr + 1; + a_mem_access <= 1; + iterations <= iterations + 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM A +////////////////////////////////////////////////////////////////////////// +reg [7:0] a_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_eltwise_op) begin + a_mem_access_counter <= 0; + end + else if (a_mem_access == 1) begin + a_mem_access_counter <= a_mem_access_counter + 1; + + end + else begin + a_mem_access_counter <= 0; + end +end + +wire bram_rdata_a_valid; //flag that tells whether the data from memory is valid +assign bram_rdata_a_valid = + ((validity_mask_a[0]==1'b0 && a_mem_access_counter==1) || + (validity_mask_a[1]==1'b0 && a_mem_access_counter==2) || + (validity_mask_a[2]==1'b0 && a_mem_access_counter==3) || + (validity_mask_a[3]==1'b0 && a_mem_access_counter==4)) ? + 1'b0 : (a_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM A (systolic data setup) +////////////////////////////////////////////////////////////////////////// +//Slice data into chunks and qualify it with whether it is valid or not +assign a0_data = a_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{bram_rdata_a_valid}} & {`DWIDTH{validity_mask_a[0]}}; +assign a1_data = a_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{bram_rdata_a_valid}} & {`DWIDTH{validity_mask_a[1]}}; +assign a2_data = a_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{bram_rdata_a_valid}} & {`DWIDTH{validity_mask_a[2]}}; +assign a3_data = a_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{bram_rdata_a_valid}} & {`DWIDTH{validity_mask_a[3]}}; + + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM B +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] b_addr; +reg b_mem_access; //flag that tells whether the compute unit is trying to access memory or not + +always @(posedge clk) begin + //else if (clk_cnt >= b_loc*`CU_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + if (reset || ~start_eltwise_op) begin + b_addr <= address_mat_b ; + b_mem_access <= 0; + end + //else if ((clk_cnt >= b_loc*`CU_SIZE) && (clk_cnt < b_loc*`CU_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + else if (iterations <= count) begin + b_addr <= b_addr + 1; + b_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM B +////////////////////////////////////////////////////////////////////////// +reg [7:0] b_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_eltwise_op) begin + b_mem_access_counter <= 0; + end + else if (b_mem_access == 1) begin + b_mem_access_counter <= b_mem_access_counter + 1; + end + else begin + b_mem_access_counter <= 0; + end +end + +wire bram_rdata_b_valid; //flag that tells whether the data from memory is valid +assign bram_rdata_b_valid = + ((validity_mask_b[0]==1'b0 && b_mem_access_counter==1) || + (validity_mask_b[1]==1'b0 && b_mem_access_counter==2) || + (validity_mask_b[2]==1'b0 && b_mem_access_counter==3) || + (validity_mask_b[3]==1'b0 && b_mem_access_counter==4)) ? + 1'b0 : (b_mem_access_counter >= `MEM_ACCESS_LATENCY); + +//Slice data into chunks and qualify it with whether it is valid or not +assign b0_data = b_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{bram_rdata_b_valid}} & {`DWIDTH{validity_mask_b[0]}}; +assign b1_data = b_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{bram_rdata_b_valid}} & {`DWIDTH{validity_mask_b[1]}}; +assign b2_data = b_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{bram_rdata_b_valid}} & {`DWIDTH{validity_mask_b[2]}}; +assign b3_data = b_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{bram_rdata_b_valid}} & {`DWIDTH{validity_mask_b[3]}}; + + +endmodule + + + +////////////////////////////////////////////////////////////////////////// +// Array of processing elements +////////////////////////////////////////////////////////////////////////// +module pe_array( +reset, +clk, +pe_reset, +op, +a0, a1, a2, a3, +b0, b1, b2, b3, +out0, out1, out2, out3 +); + +input clk; +input reset; +input pe_reset; +input [1:0] op; +input [`DWIDTH-1:0] a0; +input [`DWIDTH-1:0] a1; +input [`DWIDTH-1:0] a2; +input [`DWIDTH-1:0] a3; +input [`DWIDTH-1:0] b0; +input [`DWIDTH-1:0] b1; +input [`DWIDTH-1:0] b2; +input [`DWIDTH-1:0] b3; +output [`DWIDTH-1:0] out0; +output [`DWIDTH-1:0] out1; +output [`DWIDTH-1:0] out2; +output [`DWIDTH-1:0] out3; + +wire [`DWIDTH-1:0] out0, out1, out2, out3; + +wire effective_rst; +assign effective_rst = reset | pe_reset; + +processing_element pe0(.reset(effective_rst), .clk(clk), .in_a(a0), .in_b(b0), .op(op), .out(out0)); +processing_element pe1(.reset(effective_rst), .clk(clk), .in_a(a1), .in_b(b1), .op(op), .out(out1)); +processing_element pe2(.reset(effective_rst), .clk(clk), .in_a(a2), .in_b(b2), .op(op), .out(out2)); +processing_element pe3(.reset(effective_rst), .clk(clk), .in_a(a3), .in_b(b3), .op(op), .out(out3)); + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Processing element (PE) +////////////////////////////////////////////////////////////////////////// +module processing_element( + reset, + clk, + in_a, + in_b, + op, + out + ); + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [`DWIDTH-1:0] in_b; + input [1:0] op; + output [`DWIDTH-1:0] out; + + wire [`DWIDTH-1:0] out_mul; + wire [`DWIDTH-1:0] out_sum; + wire [`DWIDTH-1:0] out_sub; + + assign out = (op == 2'b00) ? out_sum : + (op == 2'b01) ? out_sub : + out_mul; + + seq_mul u_mul(.a(in_a), .b(in_b), .out(out_mul), .reset(reset), .clk(clk)); + seq_add u_add(.a(in_a), .b(in_b), .out(out_sum), .reset(reset), .clk(clk)); + seq_sub u_sub(.a(in_a), .b(in_b), .out(out_sub), .reset(reset), .clk(clk)); + +endmodule + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Multiply block +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +module seq_mul(a, b, out, reset, clk); +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +input reset; +input clk; +output [`DWIDTH-1:0] out; + +reg [`DWIDTH-1:0] a_flopped; +reg [`DWIDTH-1:0] b_flopped; + +wire [`DWIDTH-1:0] mul_out_temp; +reg [`DWIDTH-1:0] mul_out_temp_reg; + +always @(posedge clk) begin + if (reset) begin + a_flopped <= 0; + b_flopped <= 0; + end else begin + a_flopped <= a; + b_flopped <= b; + end +end + +//assign mul_out_temp = a * b; +`ifdef complex_dsp +mult_fp_clk_16 mul_u1(.clk(clk), .a(a_flopped), .b(b_flopped), .out(mul_out_temp)); +`else +FPMult_16 u_FPMult (.clk(clk), .rst(1'b0), .a(a_flopped), .b(b_flopped), .result(mul_out_temp), .flags()); +`endif + +always @(posedge clk) begin + if (reset) begin + mul_out_temp_reg <= 0; + end else begin + mul_out_temp_reg <= mul_out_temp; + end +end + +assign out = mul_out_temp_reg; + +endmodule + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Addition block +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +module seq_add(a, b, out, reset, clk); +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +input reset; +input clk; +output [`DWIDTH-1:0] out; + +reg [`DWIDTH-1:0] a_flopped; +reg [`DWIDTH-1:0] b_flopped; + +wire [`DWIDTH-1:0] sum_out_temp; +reg [`DWIDTH-1:0] sum_out_temp_reg; + +always @(posedge clk) begin + if (reset) begin + a_flopped <= 0; + b_flopped <= 0; + end else begin + a_flopped <= a; + b_flopped <= b; + end +end + +//assign sum_out_temp = a + b; +`ifdef complex_dsp +addition_fp_clk_16 add_u1(.clk(clk), .a(a_flopped), .b(b_flopped), .out(sum_out_temp)); +`else +FPAddSub u_FPAddSub (.clk(clk), .rst(1'b0), .a(a_flopped), .b(b_flopped), .operation(1'b0), .result(sum_out_temp), .flags()); +`endif + +always @(posedge clk) begin + if (reset) begin + sum_out_temp_reg <= 0; + end else begin + sum_out_temp_reg <= sum_out_temp; + end +end + +assign out = sum_out_temp_reg; + +endmodule + + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Subtraction block +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +module seq_sub(a, b, out, reset, clk); +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +input reset; +input clk; +output [`DWIDTH-1:0] out; + +reg [`DWIDTH-1:0] a_flopped; +reg [`DWIDTH-1:0] b_flopped; + +wire [`DWIDTH-1:0] sub_out_temp; +reg [`DWIDTH-1:0] sub_out_temp_reg; + +always @(posedge clk) begin + if (reset) begin + a_flopped <= 0; + b_flopped <= 0; + end else begin + a_flopped <= a; + b_flopped <= b; + end +end + +//assign sub_out_temp = a - b; +//Floating point adder has both modes - add and sub. +//We don't provide the name of the mode here though. + +`ifdef complex_dsp +addition_fp_clk_16 sub_u1(.clk(clk), .a(a_flopped), .b(b_flopped), .out(sub_out_temp)); +`else +FPAddSub u_FPAddSub2(.clk(clk), .rst(1'b0), .a(a_flopped), .b(b_flopped), .operation(1'b0), .result(sub_out_temp), .flags()); +`endif + +always @(posedge clk) begin + if (reset) begin + sub_out_temp_reg <= 0; + end else begin + sub_out_temp_reg <= sub_out_temp; + end +end + +assign out = sub_out_temp_reg; + +endmodule + + +`ifndef complex_dsp + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Floating point 16-bit multiplier +// This is a heavily modified version of: +// https://github.com/fbrosser/DSP48E1-FP/tree/master/src/FPMult +// Original author: Fredrik Brosser +// Abridged by: Samidh Mehta +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// + +module FPMult_16( + clk, + rst, + a, + b, + result, + flags + ); + + // Input Ports + input clk ; // Clock + input rst ; // Reset signal + input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number + + // Output ports + output [`DWIDTH-1:0] result ; // Product, result of the operation, 32-bit FP number + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Internal signals + wire [`DWIDTH-1:0] Z_int ; // Product, result of the operation, 32-bit FP number + wire [4:0] Flags_int ; // Flags indicating exceptions according to IEEE754 + + wire Sa ; // A's sign + wire Sb ; // B's sign + wire Sp ; // Product sign + wire [`EXPONENT-1:0] Ea ; // A's exponent + wire [`EXPONENT-1:0] Eb ; // B's exponent + wire [2*`MANTISSA+1:0] Mp ; // Product mantissa + wire [4:0] InputExc ; // Exceptions in inputs + wire [`MANTISSA-1:0] NormM ; // Normalized mantissa + wire [`EXPONENT:0] NormE ; // Normalized exponent + wire [`MANTISSA:0] RoundM ; // Normalized mantissa + wire [`EXPONENT:0] RoundE ; // Normalized exponent + wire [`MANTISSA:0] RoundMP ; // Normalized mantissa + wire [`EXPONENT:0] RoundEP ; // Normalized exponent + wire GRS ; + + //reg [63:0] pipe_0; // Pipeline register Input->Prep + reg [2*`DWIDTH-1:0] pipe_0; // Pipeline register Input->Prep + + //reg [92:0] pipe_1; // Pipeline register Prep->Execute + //reg [3*`MANTISSA+2*`EXPONENT+7:0] pipe_1; // Pipeline register Prep->Execute + reg [3*`MANTISSA+2*`EXPONENT+18:0] pipe_1; + + //reg [38:0] pipe_2; // Pipeline register Execute->Normalize + reg [`MANTISSA+`EXPONENT+7:0] pipe_2; // Pipeline register Execute->Normalize + + //reg [72:0] pipe_3; // Pipeline register Normalize->Round + reg [2*`MANTISSA+2*`EXPONENT+10:0] pipe_3; // Pipeline register Normalize->Round + + //reg [36:0] pipe_4; // Pipeline register Round->Output + reg [`DWIDTH+4:0] pipe_4; // Pipeline register Round->Output + + assign result = pipe_4[`DWIDTH+4:5] ; + assign flags = pipe_4[4:0] ; + + // Prepare the operands for alignment and check for exceptions + FPMult_PrepModule PrepModule(clk, rst, pipe_0[2*`DWIDTH-1:`DWIDTH], pipe_0[`DWIDTH-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]) ; + + // Perform (unsigned) mantissa multiplication + FPMult_ExecuteModule ExecuteModule(pipe_1[3*`MANTISSA+`EXPONENT*2+7:2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7:2*`MANTISSA+7], pipe_1[2*`MANTISSA+6:5], pipe_1[2*`MANTISSA+2*`EXPONENT+6:2*`MANTISSA+`EXPONENT+7], pipe_1[2*`MANTISSA+`EXPONENT+6:2*`MANTISSA+7], pipe_1[2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7], Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0], GRS) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + FPMult_NormalizeModule NormalizeModule(pipe_2[`MANTISSA-1:0], pipe_2[`MANTISSA+`EXPONENT:`MANTISSA], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + //FPMult_RoundModule RoundModule(pipe_3[47:24], pipe_3[23:0], pipe_3[65:57], pipe_3[56:48], pipe_3[66], pipe_3[67], pipe_3[72:68], Z_int[31:0], Flags_int[4:0]) ; + FPMult_RoundModule RoundModule(pipe_3[2*`MANTISSA+1:`MANTISSA+1], pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+2*`EXPONENT+3:2*`MANTISSA+`EXPONENT+3], pipe_3[2*`MANTISSA+`EXPONENT+2:2*`MANTISSA+2], pipe_3[2*`MANTISSA+2*`EXPONENT+4], pipe_3[2*`MANTISSA+2*`EXPONENT+5], pipe_3[2*`MANTISSA+2*`EXPONENT+10:2*`MANTISSA+2*`EXPONENT+6], Z_int[`DWIDTH-1:0], Flags_int[4:0]) ; + +//adding always@ (*) instead of posedge clock to make design combinational + always @ (posedge clk) begin + if(rst) begin + pipe_0 <= 0; + pipe_1 <= 0; + pipe_2 <= 0; + pipe_3 <= 0; + pipe_4 <= 0; + end + else begin + /* PIPE 0 + [2*`DWIDTH-1:`DWIDTH] A + [`DWIDTH-1:0] B + */ + pipe_0 <= {a, b} ; + + + /* PIPE 1 + [2*`EXPONENT+3*`MANTISSA + 18: 2*`EXPONENT+2*`MANTISSA + 18] //pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH] , mantissa of A + [2*`EXPONENT+2*`MANTISSA + 17 :2*`EXPONENT+2*`MANTISSA + 9] // pipe_0[8:0] + [2*`EXPONENT+2*`MANTISSA + 8] Sa + [2*`EXPONENT+2*`MANTISSA + 7] Sb + [2*`EXPONENT+2*`MANTISSA + 6:`EXPONENT+2*`MANTISSA+7] Ea + [`EXPONENT +2*`MANTISSA+6:2*`MANTISSA+7] Eb + [2*`MANTISSA+1+5:5] Mp + [4:0] InputExc + */ + //pipe_1 <= {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[`MANTISSA_MUL_SPLIT_LSB-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA-1:0], InputExc[4:0]} ; + pipe_1 <= {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[8:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]} ; + + /* PIPE 2 + [`EXPONENT + `MANTISSA + 7:`EXPONENT + `MANTISSA + 3] InputExc + [`EXPONENT + `MANTISSA + 2] GRS + [`EXPONENT + `MANTISSA + 1] Sp + [`EXPONENT + `MANTISSA:`MANTISSA] NormE + [`MANTISSA-1:0] NormM + */ + pipe_2 <= {pipe_1[4:0], GRS, Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0]} ; + /* PIPE 3 + [2*`EXPONENT+2*`MANTISSA+10:2*`EXPONENT+2*`MANTISSA+6] InputExc + [2*`EXPONENT+2*`MANTISSA+5] GRS + [2*`EXPONENT+2*`MANTISSA+4] Sp + [2*`EXPONENT+2*`MANTISSA+3:`EXPONENT+2*`MANTISSA+3] RoundE + [`EXPONENT+2*`MANTISSA+2:2*`MANTISSA+2] RoundEP + [2*`MANTISSA+1:`MANTISSA+1] RoundM + [`MANTISSA:0] RoundMP + */ + pipe_3 <= {pipe_2[`EXPONENT+`MANTISSA+7:`EXPONENT+`MANTISSA+1], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]} ; + /* PIPE 4 + [`DWIDTH+4:5] Z + [4:0] Flags + */ + pipe_4 <= {Z_int[`DWIDTH-1:0], Flags_int[4:0]} ; + end + end + +endmodule + + + +module FPMult_PrepModule ( + clk, + rst, + a, + b, + Sa, + Sb, + Ea, + Eb, + Mp, + InputExc + ); + + // Input ports + input clk ; + input rst ; + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [`EXPONENT-1:0] Ea ; // A's exponent + output [`EXPONENT-1:0] Eb ; // B's exponent + output [2*`MANTISSA+1:0] Mp ; // Mantissa product + output [4:0] InputExc ; // Input numbers are exceptions + + // Internal signals // If signal is high... + wire ANaN ; // A is a signalling NaN + wire BNaN ; // B is a signalling NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`MANTISSA-1:0] Ma; + wire [`MANTISSA-1:0] Mb; + + assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + + // Check for any exceptions and put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + //assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ; + + // Take input numbers apart + assign Sa = a[`DWIDTH-1] ; // A's sign + assign Sb = b[`DWIDTH-1] ; // B's sign + assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception + assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception +// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB]; + // assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB]; + + + + //assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ; + assign Mp = ({1'b1,a[`MANTISSA-1:0]}*{1'b1, b[`MANTISSA-1:0]}) ; + + + //We multiply part of the mantissa here + //Full mantissa of A + //Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B + // wire [`ACTUAL_MANTISSA-1:0] inp_A; + // wire [`ACTUAL_MANTISSA-1:0] inp_B; + // assign inp_A = {1'b1, Ma}; + // assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp)); +endmodule + + +module FPMult_ExecuteModule( + a, + b, + MpC, + Ea, + Eb, + Sa, + Sb, + Sp, + NormE, + NormM, + GRS + ); + + // Input ports + input [`MANTISSA-1:0] a ; + input [2*`EXPONENT:0] b ; + input [2*`MANTISSA+1:0] MpC ; + input [`EXPONENT-1:0] Ea ; // A's exponent + input [`EXPONENT-1:0] Eb ; // B's exponent + input Sa ; // A's sign + input Sb ; // B's sign + + // Output ports + output Sp ; // Product sign + output [`EXPONENT:0] NormE ; // Normalized exponent + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output GRS ; + + wire [2*`MANTISSA+1:0] Mp ; + + assign Sp = (Sa ^ Sb) ; // Equal signs give a positive product + + // wire [`ACTUAL_MANTISSA-1:0] inp_a; + // wire [`ACTUAL_MANTISSA-1:0] inp_b; + // assign inp_a = {1'b1, a}; + // assign inp_b = {{(`MANTISSA-`MANTISSA_MUL_SPLIT_LSB){1'b0}}, 1'b0, b}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_a), .B(inp_b), .TC(1'b0), .PRODUCT(Mp_temp)); + // DW01_add #(2*`ACTUAL_MANTISSA) u_add(.A(Mp_temp), .B(MpC<<`MANTISSA_MUL_SPLIT_LSB), .CI(1'b0), .SUM(Mp), .CO()); + + //assign Mp = (MpC<<(2*`EXPONENT+1)) + ({4'b0001, a[`MANTISSA-1:0]}*{1'b0, b[2*`EXPONENT:0]}) ; + assign Mp = MpC; + + + assign NormM = (Mp[2*`MANTISSA+1] ? Mp[2*`MANTISSA:`MANTISSA+1] : Mp[2*`MANTISSA-1:`MANTISSA]); // Check for overflow + assign NormE = (Ea + Eb + Mp[2*`MANTISSA+1]); // If so, increment exponent + + assign GRS = ((Mp[`MANTISSA]&(Mp[`MANTISSA+1]))|(|Mp[`MANTISSA-1:0])) ; + +endmodule + +module FPMult_NormalizeModule( + NormM, + NormE, + RoundE, + RoundEP, + RoundM, + RoundMP + ); + + // Input Ports + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input [`EXPONENT:0] NormE ; // Normalized exponent + + // Output Ports + output [`EXPONENT:0] RoundE ; + output [`EXPONENT:0] RoundEP ; + output [`MANTISSA:0] RoundM ; + output [`MANTISSA:0] RoundMP ; + +// EXPONENT = 5 +// EXPONENT -1 = 4 +// NEED to subtract 2^4 -1 = 15 + +wire [`EXPONENT-1 : 0] bias; + +assign bias = ((1<< (`EXPONENT -1)) -1); + + assign RoundE = NormE - bias ; + assign RoundEP = NormE - bias -1 ; + assign RoundM = NormM ; + assign RoundMP = NormM ; + +endmodule + +module FPMult_RoundModule( + RoundM, + RoundMP, + RoundE, + RoundEP, + Sp, + GRS, + InputExc, + Z, + Flags + ); + + // Input Ports + input [`MANTISSA:0] RoundM ; // Normalized mantissa + input [`MANTISSA:0] RoundMP ; // Normalized exponent + input [`EXPONENT:0] RoundE ; // Normalized mantissa + 1 + input [`EXPONENT:0] RoundEP ; // Normalized exponent + 1 + input Sp ; // Product sign + input GRS ; + input [4:0] InputExc ; + + // Output Ports + output [`DWIDTH-1:0] Z ; // Final product + output [4:0] Flags ; + + // Internal Signals + wire [`EXPONENT:0] FinalE ; // Rounded exponent + wire [`MANTISSA:0] FinalM; + wire [`MANTISSA:0] PreShiftM; + + assign PreShiftM = GRS ? RoundMP : RoundM ; // Round up if R and (G or S) + + // Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow) + assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]) ; + + assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done + + assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]} ; // Putting the pieces together + assign Flags = InputExc[4:0]; + +endmodule +`endif + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +// Floating point 16-bit adder +// This is a heavily modified version of: +// https://github.com/fbrosser/DSP48E1-FP/tree/master/src/FP_AddSub +// Original author: Fredrik Brosser +// Abridged by: Samidh Mehta +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +`ifndef complex_dsp + +module FPAddSub( + //bf16, + clk, + rst, + a, + b, + operation, // 0 add, 1 sub + result, + flags + ); + //input bf16; //1 for Bfloat16, 0 for IEEE half precision + + // Clock and reset + input clk ; // Clock signal + input rst ; // Reset (active high, resets pipeline registers) + + // Input ports + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + input operation ; // Operation select signal + + // Output ports + output [`DWIDTH-1:0] result ; // Result of the operation + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Pipeline Registers + //reg [79:0] pipe_1; // Pipeline register PreAlign->Align1 + reg [2*`EXPONENT + 2*`DWIDTH + 5:0] pipe_1; // Pipeline register PreAlign->Align1 + + //reg [67:0] pipe_2; // Pipeline register Align1->Align3 + //reg [2*`EXPONENT+ 2*`MANTISSA + 8:0] pipe_2; // Pipeline register Align1->Align3 + wire [2*`EXPONENT+ 2*`MANTISSA + 8:0] pipe_2; + + //reg [76:0] pipe_3; 68 // Pipeline register Align1->Align3 + reg [2*`EXPONENT+ 2*`MANTISSA + 9:0] pipe_3; // Pipeline register Align1->Align3 + + //reg [69:0] pipe_4; // Pipeline register Align3->Execute + //reg [2*`EXPONENT+ 2*`MANTISSA + 9:0] pipe_4; // Pipeline register Align3->Execute + wire [2*`EXPONENT+ 2*`MANTISSA + 9:0] pipe_4; + + //reg [51:0] pipe_5; // Pipeline register Execute->Normalize + reg [`DWIDTH+`EXPONENT+11:0] pipe_5; // Pipeline register Execute->Normalize + + //reg [56:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + //reg [`DWIDTH+`EXPONENT+16:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + wire [`DWIDTH+`EXPONENT+16:0] pipe_6; + + //reg [56:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + //reg [`DWIDTH+`EXPONENT+16:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + wire [`DWIDTH+`EXPONENT+16:0] pipe_7; + //reg [54:0] pipe_8; // Pipeline register NormalizeShift3->Round + reg [`EXPONENT*2+`MANTISSA+15:0] pipe_8; // Pipeline register NormalizeShift3->Round + + //reg [40:0] pipe_9; // Pipeline register NormalizeShift3->Round + //reg [`DWIDTH+8:0] pipe_9; // Pipeline register NormalizeShift3->Round + wire [`DWIDTH+8:0] pipe_9; + + // Internal wires between modules + wire [`DWIDTH-2:0] Aout_0 ; // A - sign + wire [`DWIDTH-2:0] Bout_0 ; // B - sign + wire Opout_0 ; // A's sign + wire Sa_0 ; // A's sign + wire Sb_0 ; // B's sign + wire MaxAB_1 ; // Indicates the larger of A and B(0/A, 1/B) + wire [`EXPONENT-1:0] CExp_1 ; // Common Exponent + wire [`EXPONENT-1:0] Shift_1 ; // Number of steps to smaller mantissa shift right (align) + wire [`MANTISSA-1:0] Mmax_1 ; // Larger mantissa + wire [4:0] InputExc_0 ; // Input numbers are exceptions + wire [2*`EXPONENT-1:0] ShiftDet_0 ; + wire [`MANTISSA-1:0] MminS_1 ; // Smaller mantissa after 0/16 shift + wire [`MANTISSA:0] MminS_2 ; // Smaller mantissa after 0/4/8/12 shift + wire [`MANTISSA:0] Mmin_3 ; // Smaller mantissa after 0/1/2/3 shift + wire [`DWIDTH:0] Sum_4 ; + wire PSgn_4 ; + wire Opr_4 ; + wire [`EXPONENT-1:0] Shift_5 ; // Number of steps to shift sum left (normalize) + wire [`DWIDTH:0] SumS_5 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_6 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_7 ; // Sum after 0/16 shift + wire [`MANTISSA-1:0] NormM_8 ; // Normalized mantissa + wire [`EXPONENT:0] NormE_8; // Adjusted exponent + wire ZeroSum_8 ; // Zero flag + wire NegE_8 ; // Flag indicating negative exponent + wire R_8 ; // Round bit + wire S_8 ; // Final sticky bit + wire FG_8 ; // Final sticky bit + wire [`DWIDTH-1:0] P_int ; + wire EOF ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_PrealignModule PrealignModule + ( // Inputs + a, b, operation, + // Outputs + Sa_0, Sb_0, ShiftDet_0[2*`EXPONENT-1:0], InputExc_0[4:0], Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Opout_0) ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_AlignModule AlignModule + ( // Inputs + pipe_1[2*`EXPONENT + 2*`DWIDTH + 4: 2*`EXPONENT +`DWIDTH + 6], pipe_1[2*`EXPONENT +`DWIDTH + 5 : 2*`EXPONENT +7], pipe_1[2*`EXPONENT+4:5], + // Outputs + CExp_1[`EXPONENT-1:0], MaxAB_1, Shift_1[`EXPONENT-1:0], MminS_1[`MANTISSA-1:0], Mmax_1[`MANTISSA-1:0]) ; + + // Alignment Shift Stage 1 + FPAddSub_AlignShift1 AlignShift1 + ( // Inputs + //bf16, + pipe_2[`MANTISSA-1:0], pipe_2[`EXPONENT+ 2*`MANTISSA + 4 : 2*`MANTISSA + 7], + // Outputs + MminS_2[`MANTISSA:0]) ; + + // Alignment Shift Stage 3 and compution of guard and sticky bits + FPAddSub_AlignShift2 AlignShift2 + ( // Inputs + pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+7:2*`MANTISSA+6], + // Outputs + Mmin_3[`MANTISSA:0]) ; + + // Perform mantissa addition + FPAddSub_ExecutionModule ExecutionModule + ( // Inputs + pipe_4[`MANTISSA*2+5:`MANTISSA+6], pipe_4[`MANTISSA:0], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 8], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 7], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 6], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 9], + // Outputs + Sum_4[`DWIDTH:0], PSgn_4, Opr_4) ; + + // Prepare normalization of result + FPAddSub_NormalizeModule NormalizeModule + ( // Inputs + pipe_5[`DWIDTH:0], + // Outputs + SumS_5[`DWIDTH:0], Shift_5[4:0]) ; + + // Normalization Shift Stage 1 + FPAddSub_NormalizeShift1 NormalizeShift1 + ( // Inputs + pipe_6[`DWIDTH:0], pipe_6[`DWIDTH+`EXPONENT+14:`DWIDTH+`EXPONENT+11], + // Outputs + SumS_7[`DWIDTH:0]) ; + + // Normalization Shift Stage 3 and final guard, sticky and round bits + FPAddSub_NormalizeShift2 NormalizeShift2 + ( // Inputs + pipe_7[`DWIDTH:0], pipe_7[`DWIDTH+`EXPONENT+5:`DWIDTH+6], pipe_7[`DWIDTH+`EXPONENT+15:`DWIDTH+`EXPONENT+11], + // Outputs + NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8, FG_8) ; + + // Round and put result together + FPAddSub_RoundModule RoundModule + ( // Inputs + pipe_8[3], pipe_8[4+`EXPONENT:4], pipe_8[`EXPONENT+`MANTISSA+4:5+`EXPONENT], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT*2+`MANTISSA+15], pipe_8[`EXPONENT*2+`MANTISSA+12], pipe_8[`EXPONENT*2+`MANTISSA+11], pipe_8[`EXPONENT*2+`MANTISSA+14], pipe_8[`EXPONENT*2+`MANTISSA+10], + // Outputs + P_int[`DWIDTH-1:0], EOF) ; + + // Check for exceptions + FPAddSub_ExceptionModule Exceptionmodule + ( // Inputs + pipe_9[8+`DWIDTH:9], pipe_9[8], pipe_9[7], pipe_9[6], pipe_9[5:1], pipe_9[0], + // Outputs + result[`DWIDTH-1:0], flags[4:0]) ; + + +assign pipe_2 = {pipe_1[2*`EXPONENT + 2*`DWIDTH + 5], pipe_1[2*`EXPONENT +6:2*`EXPONENT +5], MaxAB_1, CExp_1[`EXPONENT-1:0], Shift_1[`EXPONENT-1:0], Mmax_1[`MANTISSA-1:0], pipe_1[4:0], MminS_1[`MANTISSA-1:0]} ; +assign pipe_4 = {pipe_3[2*`EXPONENT+ 2*`MANTISSA + 9:`MANTISSA+1], Mmin_3[`MANTISSA:0]} ; +assign pipe_6 = {pipe_5[`DWIDTH+`EXPONENT+11], Shift_5[4:0], pipe_5[`DWIDTH+`EXPONENT+10:`DWIDTH+1], SumS_5[`DWIDTH:0]} ; +assign pipe_7 = {pipe_6[`DWIDTH+`EXPONENT+16:`DWIDTH+1], SumS_7[`DWIDTH:0]} ; +assign pipe_9 = {P_int[`DWIDTH-1:0], pipe_8[2], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT+`MANTISSA+9:`EXPONENT+`MANTISSA+5], EOF} ; + + always @ (posedge clk) begin + if(rst) begin + pipe_1 <= 0; + //pipe_2 <= 0; + pipe_3 <= 0; + //pipe_4 <= 0; + pipe_5 <= 0; + //pipe_6 <= 0; + //pipe_7 <= 0; + pipe_8 <= 0; + //pipe_9 <= 0; + end + else begin +/* PIPE_1: + [2*`EXPONENT + 2*`DWIDTH + 5] Opout_0 + [2*`EXPONENT + 2*`DWIDTH + 4: 2*`EXPONENT +`DWIDTH + 6] A_out0 + [2*`EXPONENT +`DWIDTH + 5 : 2*`EXPONENT +7] Bout_0 + [2*`EXPONENT +6] Sa_0 + [2*`EXPONENT +5] Sb_0 + [2*`EXPONENT +4 : 5] ShiftDet_0 + [4:0] Input Exc +*/ + pipe_1 <= {Opout_0, Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Sa_0, Sb_0, ShiftDet_0[2*`EXPONENT -1:0], InputExc_0[4:0]} ; +/* PIPE_2 +[2*`EXPONENT+ 2*`MANTISSA + 8] operation +[2*`EXPONENT+ 2*`MANTISSA + 7] Sa_0 +[2*`EXPONENT+ 2*`MANTISSA + 6] Sb_0 +[2*`EXPONENT+ 2*`MANTISSA + 5] MaxAB_0 +[2*`EXPONENT+ 2*`MANTISSA + 4:`EXPONENT+ 2*`MANTISSA + 5] CExp_0 +[`EXPONENT+ 2*`MANTISSA + 4 : 2*`MANTISSA + 5] Shift_0 +[2*`MANTISSA + 4:`MANTISSA + 5] Mmax_0 +[`MANTISSA + 4 : `MANTISSA] InputExc_0 +[`MANTISSA-1:0] MminS_1 +*/ + //pipe_2 <= {pipe_1[2*`EXPONENT + 2*`DWIDTH + 5], pipe_1[2*`EXPONENT +6:2*`EXPONENT +5], MaxAB_1, CExp_1[`EXPONENT-1:0], Shift_1[`EXPONENT-1:0], Mmax_1[`MANTISSA-1:0], pipe_1[4:0], MminS_1[`MANTISSA-1:0]} ; +/* PIPE_3 +[2*`EXPONENT+ 2*`MANTISSA + 9] operation +[2*`EXPONENT+ 2*`MANTISSA + 8] Sa_0 +[2*`EXPONENT+ 2*`MANTISSA + 7] Sb_0 +[2*`EXPONENT+ 2*`MANTISSA + 6] MaxAB_0 +[2*`EXPONENT+ 2*`MANTISSA + 5:`EXPONENT+ 2*`MANTISSA + 6] CExp_0 +[`EXPONENT+ 2*`MANTISSA + 5 : 2*`MANTISSA + 6] Shift_0 +[2*`MANTISSA + 5:`MANTISSA + 6] Mmax_0 +[`MANTISSA + 5 : `MANTISSA + 1] InputExc_0 +[`MANTISSA:0] MminS_2 +*/ + pipe_3 <= {pipe_2[2*`EXPONENT+ 2*`MANTISSA + 8:`MANTISSA], MminS_2[`MANTISSA:0]} ; +/* PIPE_4 +[2*`EXPONENT+ 2*`MANTISSA + 9] operation +[2*`EXPONENT+ 2*`MANTISSA + 8] Sa_0 +[2*`EXPONENT+ 2*`MANTISSA + 7] Sb_0 +[2*`EXPONENT+ 2*`MANTISSA + 6] MaxAB_0 +[2*`EXPONENT+ 2*`MANTISSA + 5:`EXPONENT+ 2*`MANTISSA + 6] CExp_0 +[`EXPONENT+ 2*`MANTISSA + 5 : 2*`MANTISSA + 6] Shift_0 +[2*`MANTISSA + 5:`MANTISSA + 6] Mmax_0 +[`MANTISSA + 5 : `MANTISSA + 1] InputExc_0 +[`MANTISSA:0] MminS_3 +*/ + //pipe_4 <= {pipe_3[2*`EXPONENT+ 2*`MANTISSA + 9:`MANTISSA+1], Mmin_3[`MANTISSA:0]} ; +/* PIPE_5 : +[`DWIDTH+ `EXPONENT + 11] operation +[`DWIDTH+ `EXPONENT + 10] PSgn_4 +[`DWIDTH+ `EXPONENT + 9] Opr_4 +[`DWIDTH+ `EXPONENT + 8] Sa_0 +[`DWIDTH+ `EXPONENT + 7] Sb_0 +[`DWIDTH+ `EXPONENT + 6] MaxAB_0 +[`DWIDTH+ `EXPONENT + 5 :`DWIDTH+6] CExp_0 +[`DWIDTH+5:`DWIDTH+1] InputExc_0 +[`DWIDTH:0] Sum_4 +*/ + pipe_5 <= {pipe_4[2*`EXPONENT+ 2*`MANTISSA + 9], PSgn_4, Opr_4, pipe_4[2*`EXPONENT+ 2*`MANTISSA + 8:`EXPONENT+ 2*`MANTISSA + 6], pipe_4[`MANTISSA+5:`MANTISSA+1], Sum_4[`DWIDTH:0]} ; +/* PIPE_6 : +[`DWIDTH+ `EXPONENT + 16] operation +[`DWIDTH+ `EXPONENT + 15:`DWIDTH+ `EXPONENT + 11] Shift_5 +[`DWIDTH+ `EXPONENT + 10] PSgn_4 +[`DWIDTH+ `EXPONENT + 9] Opr_4 +[`DWIDTH+ `EXPONENT + 8] Sa_0 +[`DWIDTH+ `EXPONENT + 7] Sb_0 +[`DWIDTH+ `EXPONENT + 6] MaxAB_0 +[`DWIDTH+ `EXPONENT + 5 :`DWIDTH+6] CExp_0 +[`DWIDTH+5:`DWIDTH+1] InputExc_0 +[`DWIDTH:0] Sum_4 +*/ + //pipe_6 <= {pipe_5[`DWIDTH+`EXPONENT+11], Shift_5[4:0], pipe_5[`DWIDTH+`EXPONENT+10:`DWIDTH+1], SumS_5[`DWIDTH:0]} ; +/* PIPE_7 : +[`DWIDTH+ `EXPONENT + 16] operation +[`DWIDTH+ `EXPONENT + 15:`DWIDTH+ `EXPONENT + 11] Shift_5 +[`DWIDTH+ `EXPONENT + 10] PSgn_4 +[`DWIDTH+ `EXPONENT + 9] Opr_4 +[`DWIDTH+ `EXPONENT + 8] Sa_0 +[`DWIDTH+ `EXPONENT + 7] Sb_0 +[`DWIDTH+ `EXPONENT + 6] MaxAB_0 +[`DWIDTH+ `EXPONENT + 5 :`DWIDTH+6] CExp_0 +[`DWIDTH+5:`DWIDTH+1] InputExc_0 +[`DWIDTH:0] Sum_4 +*/ + //pipe_7 <= {pipe_6[`DWIDTH+`EXPONENT+16:`DWIDTH+1], SumS_7[`DWIDTH:0]} ; +/* PIPE_8: +[2*`EXPONENT + `MANTISSA + 15] FG_8 +[2*`EXPONENT + `MANTISSA + 14] operation +[2*`EXPONENT + `MANTISSA + 13] PSgn_4 +[2*`EXPONENT + `MANTISSA + 12] Sa_0 +[2*`EXPONENT + `MANTISSA + 11] Sb_0 +[2*`EXPONENT + `MANTISSA + 10] MaxAB_0 +[2*`EXPONENT + `MANTISSA + 9:`EXPONENT + `MANTISSA + 10] CExp_0 +[`EXPONENT + `MANTISSA + 9:`EXPONENT + `MANTISSA + 5] InputExc_8 +[`EXPONENT + `MANTISSA + 4 :`EXPONENT + 5] NormM_8 +[`EXPONENT + 4 :4] NormE_8 +[3] ZeroSum_8 +[2] NegE_8 +[1] R_8 +[0] S_8 +*/ + pipe_8 <= {FG_8, pipe_7[`DWIDTH+`EXPONENT+16], pipe_7[`DWIDTH+`EXPONENT+10], pipe_7[`DWIDTH+`EXPONENT+8:`DWIDTH+1], NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8} ; +/* pipe_9: +[`DWIDTH + 8 :9] P_int +[8] NegE_8 +[7] R_8 +[6] S_8 +[5:1] InputExc_8 +[0] EOF +*/ + //pipe_9 <= {P_int[`DWIDTH-1:0], pipe_8[2], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT+`MANTISSA+9:`EXPONENT+`MANTISSA+5], EOF} ; + end + end + +endmodule + + +// +// Description: The pre-alignment module is responsible for taking the inputs +// apart and checking the parts for exceptions. +// The exponent difference is also calculated in this module. +// + + +module FPAddSub_PrealignModule( + A, + B, + operation, + Sa, + Sb, + ShiftDet, + InputExc, + Aout, + Bout, + Opout + ); + + // Input ports + input [`DWIDTH-1:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] B ; // Input B, a 32-bit floating point number + input operation ; + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [2*`EXPONENT-1:0] ShiftDet ; + output [4:0] InputExc ; // Input numbers are exceptions + output [`DWIDTH-2:0] Aout ; + output [`DWIDTH-2:0] Bout ; + output Opout ; + + // Internal signals // If signal is high... + wire ANaN ; // A is a NaN (Not-a-Number) + wire BNaN ; // B is a NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`EXPONENT-1:0] DAB ; // ExpA - ExpB + wire [`EXPONENT-1:0] DBA ; // ExpB - ExpA + + assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + + // Put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + + //assign DAB = (A[30:23] - B[30:23]) ; + //assign DBA = (B[30:23] - A[30:23]) ; + assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1) ; + assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1) ; + + assign Sa = A[`DWIDTH-1] ; // A's sign bit + assign Sb = B[`DWIDTH-1] ; // B's sign bit + assign ShiftDet = {DBA[`EXPONENT-1:0], DAB[`EXPONENT-1:0]} ; // Shift data + assign Opout = operation ; + assign Aout = A[`DWIDTH-2:0] ; + assign Bout = B[`DWIDTH-2:0] ; + +endmodule + + +// +// Description: The alignment module determines the larger input operand and +// sets the mantissas, shift and common exponent accordingly. +// + + +module FPAddSub_AlignModule ( + A, + B, + ShiftDet, + CExp, + MaxAB, + Shift, + Mmin, + Mmax + ); + + // Input ports + input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-2:0] B ; // Input B, a 32-bit floating point number + input [2*`EXPONENT-1:0] ShiftDet ; + + // Output ports + output [`EXPONENT-1:0] CExp ; // Common Exponent + output MaxAB ; // Incidates larger of A and B (0/A, 1/B) + output [`EXPONENT-1:0] Shift ; // Number of steps to smaller mantissa shift right + output [`MANTISSA-1:0] Mmin ; // Smaller mantissa + output [`MANTISSA-1:0] Mmax ; // Larger mantissa + + // Internal signals + //wire BOF ; // Check for shifting overflow if B is larger + //wire AOF ; // Check for shifting overflow if A is larger + + assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]) ; + //assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits + //assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits + + // Determine final shift value + //assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ; + + assign Shift = MaxAB ? ShiftDet[2*`EXPONENT-1:`EXPONENT] : ShiftDet[`EXPONENT-1:0] ; + + // Take out smaller mantissa and append shift space + assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0] ; + + // Take out larger mantissa + assign Mmax = MaxAB ? B[`MANTISSA-1:0]: A[`MANTISSA-1:0] ; + + // Common exponent + assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]) ; + +endmodule + + +// Description: Alignment shift stage 1, performs 16|12|8|4 shift +// + + +// ONLY THIS MODULE IS HARDCODED for half precision fp16 and bfloat16 +module FPAddSub_AlignShift1( + //bf16, + MminP, + Shift, + Mmin + ); + + // Input ports + //input bf16; + input [`MANTISSA-1:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bits + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + + wire bf16; + assign bf16 = 1'b1; //hardcoding to 1, to avoid ODIN issue. a `ifdef here wasn't working. apparently, nested `ifdefs don't work + + // Internal signals + reg [`MANTISSA:0] Lvl1; + reg [`MANTISSA:0] Lvl2; + wire [2*`MANTISSA+1:0] Stage1; + integer i; // Loop variable + + always @(*) begin + if (bf16 == 1'b1) begin +//hardcoding for bfloat16 + //For bfloat16, we can shift the mantissa by a max of 7 bits since mantissa has a width of 7. + //Hence if either, bit[3]/bit[4]/bit[5]/bit[6]/bit[7] is 1, we can make it 0. This corresponds to bits [5:1] in our updated shift which doesn't contain last 2 bits. + //Lvl1 <= (Shift[1]|Shift[2]|Shift[3]|Shift[4]|Shift[5]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width + Lvl1 <= (|Shift[`EXPONENT-3:1]) ? 'd0 : {1'b1, MminP}; // MANTISSA + 1 width + end + else begin + //for half precision fp16, 10 bits can be shifted. Hence, only shifts till 10 (01010)can be made. + Lvl1 <= Shift[2] ? 'd0 : {1'b1, MminP}; + end + end + + assign Stage1 = {Lvl1, Lvl1}; //2*MANTISSA + 2 width + + always @(*) begin // Rotate {0 | 4 } bits + if(bf16 == 1'b1) begin + case (Shift[0]) + // Rotate by 0 + 1'b0: Lvl2 <= Stage1[`MANTISSA:0]; + // Rotate by 4 + 1'b1: Lvl2 <= Stage1[`MANTISSA+4:4]; + default: Lvl2 <= Stage1[`MANTISSA+4:4]; + endcase + end + else begin + case (Shift[1:0]) // Rotate {0 | 4 | 8} bits + // Rotate by 0 + 2'b00: Lvl2 <= Stage1[`MANTISSA:0]; + // Rotate by 4 + 2'b01: Lvl2 <= Stage1[`MANTISSA+4:4]; + // Rotate by 8 + 2'b10: Lvl2 <= Stage1[`MANTISSA+8:8]; + // Rotate by 12 + 2'b11: Lvl2[`MANTISSA: 0] <= 0; + default: Lvl2[`MANTISSA: 0] <= 0; + endcase + end + end + + // Assign output to next shift stage + assign Mmin = Lvl2; + +endmodule + + +// Description: Alignment shift stage 2, performs 3|2|1 shift +// + + +module FPAddSub_AlignShift2( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`MANTISSA:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [1:0] Shift ; // Shift amount. Last 2 bits + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + // Internal Signal + reg [`MANTISSA:0] Lvl3; + wire [2*`MANTISSA+1:0] Stage2; + integer j; // Loop variable + + assign Stage2 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl3 <= Stage2[`MANTISSA:0]; + // Rotate by 1 + 2'b01: Lvl3 <= Stage2[`MANTISSA+1:1]; + // Rotate by 2 + 2'b10: Lvl3 <= Stage2[`MANTISSA+2:2]; + // Rotate by 3 + 2'b11: Lvl3 <= Stage2[`MANTISSA+3:3]; + endcase + end + + // Assign output + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + + +// +// Description: Module that executes the addition or subtraction on mantissas. +// + + +module FPAddSub_ExecutionModule( + Mmax, + Mmin, + Sa, + Sb, + MaxAB, + OpMode, + Sum, + PSgn, + Opr + ); + + // Input ports + input [`MANTISSA-1:0] Mmax ; // The larger mantissa + input [`MANTISSA:0] Mmin ; // The smaller mantissa + input Sa ; // Sign bit of larger number + input Sb ; // Sign bit of smaller number + input MaxAB ; // Indicates the larger number (0/A, 1/B) + input OpMode ; // Operation to be performed (0/Add, 1/Sub) + + // Output ports + output [`DWIDTH:0] Sum ; // The result of the operation + output PSgn ; // The sign for the result + output Opr ; // The effective (performed) operation + + wire [`EXPONENT-1:0]temp_1; + + assign Opr = (OpMode^Sa^Sb); // Resolve sign to determine operation + assign temp_1 = 0; + // Perform effective operation +//SAMIDH_UNSURE 5--> 8 + + assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, temp_1} - {Mmin, temp_1}) : ({1'b1, Mmax, temp_1} + {Mmin, temp_1}) ; + + // Assign result sign + assign PSgn = (MaxAB ? Sb : Sa) ; + +endmodule + + +// +// Description: Determine the normalization shift amount and perform 16-shift +// + + +module FPAddSub_NormalizeModule( + Sum, + Mmin, + Shift + ); + + // Input ports + input [`DWIDTH:0] Sum ; // Mantissa sum including hidden 1 and GRS + + // Output ports + output [`DWIDTH:0] Mmin ; // Mantissa after 16|0 shift + output [4:0] Shift ; // Shift amount + //Changes in this doesn't matter since even Bfloat16 can't go beyond 7 shift to the mantissa (only 3 bits valid here) + // Determine normalization shift amount by finding leading nought + assign Shift = ( + Sum[16] ? 5'b00000 : + Sum[15] ? 5'b00001 : + Sum[14] ? 5'b00010 : + Sum[13] ? 5'b00011 : + Sum[12] ? 5'b00100 : + Sum[11] ? 5'b00101 : + Sum[10] ? 5'b00110 : + Sum[9] ? 5'b00111 : + Sum[8] ? 5'b01000 : + Sum[7] ? 5'b01001 : + Sum[6] ? 5'b01010 : + Sum[5] ? 5'b01011 : + Sum[4] ? 5'b01100 : 5'b01101 + // Sum[19] ? 5'b01101 : + // Sum[18] ? 5'b01110 : + // Sum[17] ? 5'b01111 : + // Sum[16] ? 5'b10000 : + // Sum[15] ? 5'b10001 : + // Sum[14] ? 5'b10010 : + // Sum[13] ? 5'b10011 : + // Sum[12] ? 5'b10100 : + // Sum[11] ? 5'b10101 : + // Sum[10] ? 5'b10110 : + // Sum[9] ? 5'b10111 : + // Sum[8] ? 5'b11000 : + // Sum[7] ? 5'b11001 : 5'b11010 + ); + + reg [`DWIDTH:0] Lvl1; + + always @(*) begin + // Rotate by 16? + Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum; + end + + // Assign outputs + assign Mmin = Lvl1; // Take out smaller mantissa + +endmodule + + +// Description: Normalization shift stage 1, performs 12|8|4|3|2|1|0 shift +// +//Hardcoding loop start and end values of i. To avoid ODIN limitations. i=`DWIDTH*2+1 wasn't working. + +module FPAddSub_NormalizeShift1( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`DWIDTH:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [3:0] Shift ; // Shift amount + + // Output ports + output [`DWIDTH:0] Mmin ; // The smaller mantissa + + reg [`DWIDTH:0] Lvl2; + wire [2*`DWIDTH+1:0] Stage1; + reg [`DWIDTH:0] Lvl3; + wire [2*`DWIDTH+1:0] Stage2; + integer i; // Loop variable + + assign Stage1 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 4 | 8 | 12} bits + case (Shift[3:2]) + // Rotate by 0 + 2'b00: Lvl2 <= Stage1[`DWIDTH:0]; + // Rotate by 4 + 2'b01: Lvl2 <= Stage1[28:13]; + // Rotate by 8 + 2'b10: Lvl2 <= Stage1[24:9]; + // Rotate by 12 + 2'b11: Lvl2 <= Stage1[20:5]; + default: Lvl2 <= Stage1[`DWIDTH:0]; + endcase + end + + assign Stage2 = {Lvl2, Lvl2}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl3 <= Stage2[`DWIDTH:0]; + // Rotate by 1 + 2'b01: Lvl3 <= Stage2[31:16]; + // Rotate by 2 + 2'b10: Lvl3 <= Stage2[30:15]; + // Rotate by 3 + 2'b11: Lvl3 <= Stage2[29:14]; + default: Lvl3 <= Stage2[`DWIDTH:0]; + endcase + end + + // Assign outputs + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + + +// Description: Normalization shift stage 2, calculates post-normalization +// mantissa and exponent, as well as the bits used in rounding +// + + +module FPAddSub_NormalizeShift2( + PSSum, + CExp, + Shift, + NormM, + NormE, + ZeroSum, + NegE, + R, + S, + FG + ); + + // Input ports + input [`DWIDTH:0] PSSum ; // The Pre-Shift-Sum + input [`EXPONENT-1:0] CExp ; + input [4:0] Shift ; // Amount to be shifted + + // Output ports + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output [`EXPONENT:0] NormE ; // Adjusted exponent + output ZeroSum ; // Zero flag + output NegE ; // Flag indicating negative exponent + output R ; // Round bit + output S ; // Final sticky bit + output FG ; + + // Internal signals + wire MSBShift ; // Flag indicating that a second shift is needed + wire [`EXPONENT:0] ExpOF ; // MSB set in sum indicates overflow + wire [`EXPONENT:0] ExpOK ; // MSB not set, no adjustment + + // Calculate normalized exponent and mantissa, check for all-zero sum + assign MSBShift = PSSum[`DWIDTH] ; // Check MSB in unnormalized sum + assign ZeroSum = ~|PSSum ; // Check for all zero sum + assign ExpOK = CExp - Shift ; // Adjust exponent for new normalized mantissa + assign NegE = ExpOK[`EXPONENT] ; // Check for exponent overflow + assign ExpOF = CExp - Shift + 1'b1 ; // If MSB set, add one to exponent(x2) + assign NormE = MSBShift ? ExpOF : ExpOK ; // Check for exponent overflow + assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1] ; // The new, normalized mantissa + + // Also need to compute sticky and round bits for the rounding stage + assign FG = PSSum[`EXPONENT] ; + assign R = PSSum[`EXPONENT-1] ; + assign S = |PSSum[`EXPONENT-2:0] ; + +endmodule + + +// Description: Performs 'Round to nearest, tie to even'-rounding on the +// normalized mantissa according to the G, R, S bits. Calculates +// final result and checks for exponent overflow. +// + + +module FPAddSub_RoundModule( + ZeroSum, + NormE, + NormM, + R, + S, + G, + Sa, + Sb, + Ctrl, + MaxAB, + Z, + EOF + ); + + // Input ports + input ZeroSum ; // Sum is zero + input [`EXPONENT:0] NormE ; // Normalized exponent + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input R ; // Round bit + input S ; // Sticky bit + input G ; + input Sa ; // A's sign bit + input Sb ; // B's sign bit + input Ctrl ; // Control bit (operation) + input MaxAB ; + + // Output ports + output [`DWIDTH-1:0] Z ; // Final result + output EOF ; + + // Internal signals + wire [`MANTISSA:0] RoundUpM ; // Rounded up sum with room for overflow + wire [`MANTISSA-1:0] RoundM ; // The final rounded sum + wire [`EXPONENT:0] RoundE ; // Rounded exponent (note extra bit due to poential overflow ) + wire RoundUp ; // Flag indicating that the sum should be rounded up + wire FSgn; + wire ExpAdd ; // May have to add 1 to compensate for overflow + wire RoundOF ; // Rounding overflow + + wire [`EXPONENT:0]temp_2; + assign temp_2 = 0; + // The cases where we need to round upwards (= adding one) in Round to nearest, tie to even + assign RoundUp = (G & ((R | S) | NormM[0])) ; + + // Note that in the other cases (rounding down), the sum is already 'rounded' + assign RoundUpM = (NormM + 1) ; // The sum, rounded up by 1 + assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM) ; // Compute final mantissa + assign RoundOF = RoundUp & RoundUpM[`MANTISSA] ; // Check for overflow when rounding up + + // Calculate post-rounding exponent + assign ExpAdd = (RoundOF ? 1'b1 : 1'b0) ; // Add 1 to exponent to compensate for overflow + assign RoundE = ZeroSum ? temp_2 : (NormE + ExpAdd) ; // Final exponent + + // If zero, need to determine sign according to rounding + assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ; + + // Assign final result + assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]} ; + + // Indicate exponent overflow + assign EOF = RoundE[`EXPONENT]; + +endmodule + + +// +// Description: Check the final result for exception conditions and set +// flags accordingly. +// + + +module FPAddSub_ExceptionModule( + Z, + NegE, + R, + S, + InputExc, + EOF, + P, + Flags + ); + + // Input ports + input [`DWIDTH-1:0] Z ; // Final product + input NegE ; // Negative exponent? + input R ; // Round bit + input S ; // Sticky bit + input [4:0] InputExc ; // Exceptions in inputs A and B + input EOF ; + + // Output ports + output [`DWIDTH-1:0] P ; // Final result + output [4:0] Flags ; // Exception flags + + // Internal signals + wire Overflow ; // Overflow flag + wire Underflow ; // Underflow flag + wire DivideByZero ; // Divide-by-Zero flag (always 0 in Add/Sub) + wire Invalid ; // Invalid inputs or result + wire Inexact ; // Result is inexact because of rounding + + // Exception flags + + // Result is too big to be represented + assign Overflow = EOF | InputExc[1] | InputExc[0] ; + + // Result is too small to be represented + assign Underflow = NegE & (R | S); + + // Infinite result computed exactly from finite operands + assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0]; + + // Invalid inputs or operation + assign Invalid = |(InputExc[4:2]) ; + + // Inexact answer due to rounding, overflow or underflow + assign Inexact = (R | S) | Overflow | Underflow; + + // Put pieces together to form final result + assign P = Z ; + + // Collect exception flags + assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact} ; + +endmodule + +`endif + + diff --git a/designs/koios/gemm_layer/design.yaml b/designs/koios/gemm_layer/design.yaml new file mode 100644 index 000000000..159f924b2 --- /dev/null +++ b/designs/koios/gemm_layer/design.yaml @@ -0,0 +1 @@ +top: gemm_random diff --git a/designs/koios/gemm_layer/gemm_layer.v b/designs/koios/gemm_layer/gemm_layer.v new file mode 100644 index 000000000..c5a56a248 --- /dev/null +++ b/designs/koios/gemm_layer/gemm_layer.v @@ -0,0 +1,7976 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Aman Arora +////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +///////////////////////////////////////////////////////////////////////// +// GEMM (General Matrix Multiply) layer +// Precision BF16 +// Size of the layer 20x20 +// AXI interface to control/observe the unit +// RAMs that store inputs and outputs are not a part of this design +///////////////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////////////////// +// When using an FPGA architecture which has a complex DSP block +// (eg. COFFE_22m/k6n10LB_mem20K_complexDSP_customSB_22nm.xml), define +// the following macro. But comment it out if using an FPGA architecture +// with a simpler DSP (just a fixed point multiplier) like in the +// flagship arch timing/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml +///////////////////////////////////////////////////////////////////////// + +`define BFLOAT16 + +// IEEE Half Precision => EXPONENT = 5, MANTISSA = 10 +// BFLOAT16 => EXPONENT = 8, MANTISSA = 7 + +`ifdef BFLOAT16 +`define EXPONENT 8 +`define MANTISSA 7 +`else // for ieee half precision fp16 +`define EXPONENT 5 +`define MANTISSA 10 +`endif + +`define SIGN 1 +`define DWIDTH (`SIGN+`EXPONENT+`MANTISSA) + +`define AWIDTH 8 +`define MEM_SIZE 256 + +`define MAT_MUL_SIZE 20 +`define MASK_WIDTH 20 +//This define isn't needed for this design, because we set a_loc and b_loc to 0 +`define LOG2_MAT_MUL_SIZE 4 + +`define BB_MAT_MUL_SIZE `MAT_MUL_SIZE +`define NUM_CYCLES_IN_MAC 3 +`define MEM_ACCESS_LATENCY 1 +`define ADDR_STRIDE_WIDTH 8 + +///////////////////////////////////////////////////////////////////////// +// The AXI code is taken from the RTL generator by Xilinx Vivado +// block design. +///////////////////////////////////////////////////////////////////////// + +module gemm_layer # + ( + // Parameters of Axi Slave Bus Interface S00_AXI + parameter C_S00_AXI_DATA_WIDTH = 32, + parameter C_S00_AXI_ADDR_WIDTH = 6 + ) + ( + // Users to add ports here + output wire [14:0] bram_addr_a, + input wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a, + output wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a, + output wire[`MASK_WIDTH-1:0] bram_we_a, + output wire bram_en_a, + + output wire [14:0] bram_addr_b, + input wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b, + output wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b, + output wire[`MASK_WIDTH-1:0] bram_we_b, + output wire bram_en_b, + + output wire [14:0] bram_addr_c, + input wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_c, + output wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_c, + output wire[`MASK_WIDTH-1:0] bram_we_c, + output wire bram_en_c, + // User ports ends + // Do not modify the ports beyond this line + + + // Ports of Axi Slave Bus Interface S00_AXI + input wire s00_axi_aclk, + input wire s00_axi_aresetn, + input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr, + input wire [2 : 0] s00_axi_awprot, + input wire s00_axi_awvalid, + output wire s00_axi_awready, + input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata, + input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb, + input wire s00_axi_wvalid, + output wire s00_axi_wready, + output wire [1 : 0] s00_axi_bresp, + output wire s00_axi_bvalid, + input wire s00_axi_bready, + input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr, + input wire [2 : 0] s00_axi_arprot, + input wire s00_axi_arvalid, + output wire s00_axi_arready, + output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata, + output wire [1 : 0] s00_axi_rresp, + output wire s00_axi_rvalid, + input wire s00_axi_rready + ); + + // Instantiation of Axi Bus Interface S00_AXI + gemm_0_S00_AXI # ( + .C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH), + .C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH) + ) gemm_0_S00_AXI_inst ( + .bram_addr_a(bram_addr_a), + .bram_rdata_a(bram_rdata_a), + .bram_wdata_a(bram_wdata_a), + .bram_we_a(bram_we_a), + .bram_en_a(bram_en_a), + .bram_addr_b(bram_addr_b), + .bram_rdata_b(bram_rdata_b), + .bram_wdata_b(bram_wdata_b), + .bram_we_b(bram_we_b), + .bram_en_b(bram_en_b), + .bram_addr_c(bram_addr_c), + .bram_rdata_c(bram_rdata_c), + .bram_wdata_c(bram_wdata_c), + .bram_we_c(bram_we_c), + .bram_en_c(bram_en_c), + .S_AXI_ACLK(s00_axi_aclk), + .S_AXI_ARESETN(s00_axi_aresetn), + .S_AXI_AWADDR(s00_axi_awaddr), + .S_AXI_AWPROT(s00_axi_awprot), + .S_AXI_AWVALID(s00_axi_awvalid), + .S_AXI_AWREADY(s00_axi_awready), + .S_AXI_WDATA(s00_axi_wdata), + .S_AXI_WSTRB(s00_axi_wstrb), + .S_AXI_WVALID(s00_axi_wvalid), + .S_AXI_WREADY(s00_axi_wready), + .S_AXI_BRESP(s00_axi_bresp), + .S_AXI_BVALID(s00_axi_bvalid), + .S_AXI_BREADY(s00_axi_bready), + .S_AXI_ARADDR(s00_axi_araddr), + .S_AXI_ARPROT(s00_axi_arprot), + .S_AXI_ARVALID(s00_axi_arvalid), + .S_AXI_ARREADY(s00_axi_arready), + .S_AXI_RDATA(s00_axi_rdata), + .S_AXI_RRESP(s00_axi_rresp), + .S_AXI_RVALID(s00_axi_rvalid), + .S_AXI_RREADY(s00_axi_rready) + ); + + endmodule + + module gemm_0_S00_AXI # +( + // Width of S_AXI data bus + parameter C_S_AXI_DATA_WIDTH = 32, + // Width of S_AXI address bus + parameter C_S_AXI_ADDR_WIDTH = 6 + ) + ( + // Users to add ports here + output wire [14:0] bram_addr_a, + input wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a, + output wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a, + output wire [`MASK_WIDTH-1:0] bram_we_a, + output wire bram_en_a, + + output wire [14:0] bram_addr_b, + input wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b, + output wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b, + output wire [`MASK_WIDTH-1:0] bram_we_b, + output wire bram_en_b, + + output wire [14:0] bram_addr_c, + input wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_c, + output wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_c, + output wire [`MASK_WIDTH-1:0] bram_we_c, + output wire bram_en_c, + + // User ports ends + // Do not modify the ports beyond this line + + // Global Clock Signal + input wire S_AXI_ACLK, + // Global Reset Signal. This Signal is Active LOW + input wire S_AXI_ARESETN, + // Write address (issued by master, acceped by Slave) + input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR, + // Write channel Protection type. This signal indicates the + // privilege and security level of the transaction, and whether + // the transaction is a data access or an instruction access. + input wire [2 : 0] S_AXI_AWPROT, + // Write address valid. This signal indicates that the master signaling + // valid write address and control information. + input wire S_AXI_AWVALID, + // Write address ready. This signal indicates that the slave is ready + // to accept an address and associated control signals. + output wire S_AXI_AWREADY, + // Write data (issued by master, acceped by Slave) + input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA, + // Write strobes. This signal indicates which byte lanes hold + // valid data. There is one write strobe bit for each eight + // bits of the write data bus. + input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB, + // Write valid. This signal indicates that valid write + // data and strobes are available. + input wire S_AXI_WVALID, + // Write ready. This signal indicates that the slave + // can accept the write data. + output wire S_AXI_WREADY, + // Write response. This signal indicates the status + // of the write transaction. + output wire [1 : 0] S_AXI_BRESP, + // Write response valid. This signal indicates that the channel + // is signaling a valid write response. + output wire S_AXI_BVALID, + // Response ready. This signal indicates that the master + // can accept a write response. + input wire S_AXI_BREADY, + // Read address (issued by master, acceped by Slave) + input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR, + // Protection type. This signal indicates the privilege + // and security level of the transaction, and whether the + // transaction is a data access or an instruction access. + input wire [2 : 0] S_AXI_ARPROT, + // Read address valid. This signal indicates that the channel + // is signaling valid read address and control information. + input wire S_AXI_ARVALID, + // Read address ready. This signal indicates that the slave is + // ready to accept an address and associated control signals. + output wire S_AXI_ARREADY, + // Read data (issued by slave) + output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA, + // Read response. This signal indicates the status of the + // read transfer. + output wire [1 : 0] S_AXI_RRESP, + // Read valid. This signal indicates that the channel is + // signaling the required read data. + output wire S_AXI_RVALID, + // Read ready. This signal indicates that the master can + // accept the read data and response information. + input wire S_AXI_RREADY + ); + + // AXI4LITE signals + reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; + reg axi_awready; + reg axi_wready; + reg [1 : 0] axi_bresp; + reg axi_bvalid; + reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; + reg axi_arready; + reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; + reg [1 : 0] axi_rresp; + reg axi_rvalid; + + // Example-specific design signals + // local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + // ADDR_LSB is used for addressing 32/64 bit registers/memories + // ADDR_LSB = 2 for 32 bits (n downto 2) + // ADDR_LSB = 3 for 64 bits (n downto 3) + localparam ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; + localparam OPT_MEM_ADDR_BITS = 3; + //---------------------------------------------- + //-- Signals for user logic register space example + //------------------------------------------------ + //-- Number of Slave Registers 10 + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9; + wire slv_reg_rden; + wire slv_reg_wren; + reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; + reg [31:0] byte_index; + reg aw_en; + + // I/O Connections assignments + + assign S_AXI_AWREADY = axi_awready; + assign S_AXI_WREADY = axi_wready; + assign S_AXI_BRESP = axi_bresp; + assign S_AXI_BVALID = axi_bvalid; + assign S_AXI_ARREADY = axi_arready; + assign S_AXI_RDATA = axi_rdata; + assign S_AXI_RRESP = axi_rresp; + assign S_AXI_RVALID = axi_rvalid; + // Implement axi_awready generation + // axi_awready is asserted for one S_AXI_ACLK clock cycle when both + // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + // de-asserted when reset is low. + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_awready <= 1'b0; + aw_en <= 1'b1; + end + else + begin + if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en) + begin + // slave is ready to accept write address when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_awready <= 1'b1; + aw_en <= 1'b0; + end + else if (S_AXI_BREADY && axi_bvalid) + begin + aw_en <= 1'b1; + axi_awready <= 1'b0; + end + else + begin + axi_awready <= 1'b0; + end + end + end + + // Implement axi_awaddr latching + // This process is used to latch the address when both + // S_AXI_AWVALID and S_AXI_WVALID are valid. + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_awaddr <= 0; + end + else + begin + if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en) + begin + // Write Address latching + axi_awaddr <= S_AXI_AWADDR; + end + end + end + + // Implement axi_wready generation + // axi_wready is asserted for one S_AXI_ACLK clock cycle when both + // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + // de-asserted when reset is low. + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_wready <= 1'b0; + end + else + begin + if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en ) + begin + // slave is ready to accept write data when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_wready <= 1'b1; + end + else + begin + axi_wready <= 1'b0; + end + end + end + + // Implement memory mapped register select and write logic generation + // The write data is accepted and written to memory mapped registers when + // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + // select byte enables of slave registers while writing. + // These registers are cleared when reset (active low) is applied. + // Slave register write enable is asserted when valid address and data are available + // and the slave is ready to accept the write address and write data. + assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID; + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + slv_reg0 <= 0; + slv_reg1 <= 0; + slv_reg2 <= 0; + slv_reg3 <= 0; + slv_reg4 <= 0; + slv_reg5 <= 0; + slv_reg6 <= 0; + slv_reg7 <= 0; + slv_reg8 <= 0; + slv_reg9 <= 0; + end + else begin + if (slv_reg_wren) + begin + case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 4'h0: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 0 + slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 4'h1: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 1 + slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 4'h2: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 2 + slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 4'h3: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 3 + slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 4'h4: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 4 + slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 4'h5: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 5 + slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 4'h6: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 6 + slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 4'h7: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 7 + slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 4'h8: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 8 + slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 4'h9: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 9 + slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + default : begin + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + end + endcase + end + end + end + + // Implement write response logic generation + // The write response and response valid signals are asserted by the slave + // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + // This marks the acceptance of address and indicates the status of + // write transaction. + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_bvalid <= 0; + axi_bresp <= 2'b0; + end + else + begin + if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID) + begin + // indicates a valid write response is available + axi_bvalid <= 1'b1; + axi_bresp <= 2'b0; // 'OKAY' response + end // work error responses in future + else + begin + if (S_AXI_BREADY && axi_bvalid) + //check if bready is asserted while bvalid is high) + //(there is a possibility that bready is always asserted high) + begin + axi_bvalid <= 1'b0; + end + end + end + end + + // Implement axi_arready generation + // axi_arready is asserted for one S_AXI_ACLK clock cycle when + // S_AXI_ARVALID is asserted. axi_awready is + // de-asserted when reset (active low) is asserted. + // The read address is also latched when S_AXI_ARVALID is + // asserted. axi_araddr is reset to zero on reset assertion. + + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_arready <= 1'b0; + axi_araddr <= 32'b0; + end + else + begin + if (~axi_arready && S_AXI_ARVALID) + begin + // indicates that the slave has acceped the valid read address + axi_arready <= 1'b1; + // Read address latching + axi_araddr <= S_AXI_ARADDR; + end + else + begin + axi_arready <= 1'b0; + end + end + end + + // Implement axi_arvalid generation + // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + // S_AXI_ARVALID and axi_arready are asserted. The slave registers + // data are available on the axi_rdata bus at this instance. The + // assertion of axi_rvalid marks the validity of read data on the + // bus and axi_rresp indicates the status of read transaction.axi_rvalid + // is deasserted on reset (active low). axi_rresp and axi_rdata are + // cleared to zero on reset (active low). + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_rvalid <= 0; + axi_rresp <= 0; + end + else + begin + if (axi_arready && S_AXI_ARVALID && ~axi_rvalid) + begin + // Valid read data is available at the read data bus + axi_rvalid <= 1'b1; + axi_rresp <= 2'b0; // 'OKAY' response + end + else if (axi_rvalid && S_AXI_RREADY) + begin + // Read data is accepted by the master + axi_rvalid <= 1'b0; + end + end + end + + reg [3:0] state; + reg start_mat_mul; + wire done_mat_mul; + reg mat_mul_done_status; + + // Implement memory mapped register select and read logic generation + // Slave register read enable is asserted when valid address is available + // and the slave is ready to accept the read address. + assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid; + always @(*) + begin + // Address decoding for reading registers + case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 4'h0 : reg_data_out <= slv_reg0; + 4'h1 : reg_data_out <= {31'h0, mat_mul_done_status}; + 4'h2 : reg_data_out <= slv_reg2; //addresses for mat + 4'h3 : reg_data_out <= slv_reg3; + 4'h4 : reg_data_out <= slv_reg4; + 4'h5 : reg_data_out <= state; //debug + 4'h6 : reg_data_out <= slv_reg6; //validity masks + 4'h7 : reg_data_out <= slv_reg7; + 4'h8 : reg_data_out <= slv_reg8; + 4'h9 : reg_data_out <= 32'hdead_beef ; //debug + default : reg_data_out <= 0; + endcase + end + + // Output register or memory read data + always @( posedge S_AXI_ACLK ) + begin + if ( S_AXI_ARESETN == 1'b0 ) + begin + axi_rdata <= 0; + end + else + begin + // When there is a valid read address (S_AXI_ARVALID) with + // acceptance of read address by the slave (axi_arready), + // output the read dada + if (slv_reg_rden) + begin + axi_rdata <= reg_data_out; // register read data + end + end + end + + // Add user logic here + + + wire start_reg; + assign start_reg = slv_reg0[0]; + + wire clear_done_reg; + assign clear_done_reg = slv_reg1[0]; + + wire clk; + assign clk = S_AXI_ACLK; + wire reset; + assign reset = ~S_AXI_ARESETN; + wire resetn; + assign resetn = S_AXI_ARESETN; + + always @( posedge clk) begin + if (resetn == 1'b0) begin + state <= 4'b0000; + start_mat_mul <= 1'b0; + mat_mul_done_status <= 1'b0; + end else begin + case (state) + 4'b0000: begin + start_mat_mul <= 1'b0; + mat_mul_done_status <= 1'b0; + if (start_reg == 1'b1) begin + state <= 4'b0001; + end else begin + state <= 4'b0000; + end + end + + 4'b0001: begin + start_mat_mul <= 1'b1; + state <= 4'b1010; + end + + + 4'b1010: begin + if (done_mat_mul == 1'b1) begin + start_mat_mul <= 1'b0; + state <= 4'b1000; + end + else begin + state <= 4'b1010; + end + end + + 4'b1000: begin + if (clear_done_reg == 1'b1) begin + state <= 4'b0000; + mat_mul_done_status <= 1'b0; + end + else begin + state <= 4'b1000; + mat_mul_done_status <= 1'b1; + end + end + endcase + end + end + + + + +//Connections for bram c (output matrix) +//bram_addr_c -> connected to u_matmul_4x4 block +//bram_rdata_c -> not used +//bram_wdata_c -> connected to u_matmul_4x4 block +//bram_we_c -> set to 1 when c_data is available +//bram_en_c -> hardcoded to 1 + + wire c_data_available; + assign bram_en_c = 1'b1; + assign bram_we_c = (c_data_available) ? 4'b1111 : 4'b0000; + +//Connections for bram a (first input matrix) +//bram_addr_a -> connected to u_matmul_4x4 +//bram_rdata_a -> connected to u_matmul_4x4 +//bram_wdata_a -> hardcoded to 0 (this block only reads from bram a) +//bram_we_a -> hardcoded to 0 (this block only reads from bram a) +//bram_en_a -> hardcoded to 1 + + assign bram_wdata_a = 32'b0; + assign bram_en_a = 1'b1; + assign bram_we_a = 4'b0; + +//Connections for bram b (second input matrix) +//bram_addr_b -> connected to u_matmul_4x4 +//bram_rdata_b -> connected to u_matmul_4x4 +//bram_wdata_b -> hardcoded to 0 (this block only reads from bram b) +//bram_we_b -> hardcoded to 0 (this block only reads from bram b) +//bram_en_b -> hardcoded to 1 + + assign bram_wdata_b = 32'b0; + assign bram_en_b = 1'b1; + assign bram_we_b = 4'b0; + +//NC wires +wire [`BB_MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out_NC; +wire [`BB_MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out_NC; +wire [`BB_MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in_NC; +wire [`BB_MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in_NC; + +matmul_20x20_systolic u_matmul( + .clk(clk), + .reset(reset), + .pe_reset(reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .address_mat_a(slv_reg2[`AWIDTH-1:0]), + .address_mat_b(slv_reg3[`AWIDTH-1:0]), + .address_mat_c(slv_reg4[`AWIDTH-1:0]), + .address_stride_a({{(`ADDR_STRIDE_WIDTH-1){1'b0}},1'b1}), + .address_stride_b({{(`ADDR_STRIDE_WIDTH-1){1'b0}},1'b1}), + .address_stride_c({{(`ADDR_STRIDE_WIDTH-1){1'b0}},1'b1}), + .a_data(bram_rdata_a), + .b_data(bram_rdata_b), + .a_data_in(a_data_in_NC), + .b_data_in(b_data_in_NC), + .c_data_in({`BB_MAT_MUL_SIZE*`DWIDTH{1'b0}}), + .c_data_out(bram_wdata_c), + .a_data_out(a_data_out_NC), + .b_data_out(b_data_out_NC), + .a_addr(bram_addr_a), + .b_addr(bram_addr_b), + .c_addr(bram_addr_c), + .c_data_available(c_data_available), + .validity_mask_a_rows(slv_reg6[`MASK_WIDTH-1:0]), + .validity_mask_a_cols(slv_reg7[`MASK_WIDTH-1:0]), + .validity_mask_b_rows(slv_reg7[`MASK_WIDTH-1:0]), + .validity_mask_b_cols(slv_reg8[`MASK_WIDTH-1:0]), + .a_loc(8'd0), + .b_loc(8'd0) +); + +endmodule + +////////////////////////////////////////////////////////////////////////////////// +// The main matrix multiplication module +////////////////////////////////////////////////////////////////////////////////// + +module matmul_20x20_systolic( + clk, + reset, + pe_reset, + start_mat_mul, + done_mat_mul, + address_mat_a, + address_mat_b, + address_mat_c, + address_stride_a, + address_stride_b, + address_stride_c, + a_data, + b_data, + a_data_in, //Data values coming in from previous matmul - systolic connections + b_data_in, + c_data_in, //Data values coming in from previous matmul - systolic shifting + c_data_out, //Data values going out to next matmul - systolic shifting + a_data_out, + b_data_out, + a_addr, + b_addr, + c_addr, + c_data_available, + + validity_mask_a_rows, + validity_mask_a_cols, + validity_mask_b_rows, + validity_mask_b_cols, + + a_loc, + b_loc +); + + input clk; + input reset; + input pe_reset; + input start_mat_mul; + output done_mat_mul; + input [`AWIDTH-1:0] address_mat_a; + input [`AWIDTH-1:0] address_mat_b; + input [`AWIDTH-1:0] address_mat_c; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + output [`AWIDTH-1:0] a_addr; + output [`AWIDTH-1:0] b_addr; + output [`AWIDTH-1:0] c_addr; + output c_data_available; + + input [`MASK_WIDTH-1:0] validity_mask_a_rows; + input [`MASK_WIDTH-1:0] validity_mask_a_cols; + input [`MASK_WIDTH-1:0] validity_mask_b_rows; + input [`MASK_WIDTH-1:0] validity_mask_b_cols; + + input [7:0] a_loc; + input [7:0] b_loc; + +////////////////////////////////////////////////////////////////////////// +// Logic for clock counting and when to assert done +////////////////////////////////////////////////////////////////////////// + +reg done_mat_mul; +//This is 7 bits because the expectation is that clock count will be pretty +//small. For large matmuls, this will need to increased to have more bits. +//In general, a systolic multiplier takes 4*N-2+P cycles, where N is the size +//of the matmul and P is the number of pipleine stages in the MAC block. +reg [7:0] clk_cnt; + +//Finding out number of cycles to assert matmul done. +//When we have to save the outputs to accumulators, then we don't need to +//shift out data. So, we can assert done_mat_mul early. +//In the normal case, we have to include the time to shift out the results. +//Note: the count expression used to contain "4*final_mat_mul_size", but +//to avoid multiplication, we now use "final_mat_mul_size<<2" +wire [7:0] clk_cnt_for_done; + +assign clk_cnt_for_done = + (81); + +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + clk_cnt <= 0; + done_mat_mul <= 0; + end + else if (clk_cnt == clk_cnt_for_done) begin + done_mat_mul <= 1; + clk_cnt <= clk_cnt + 1; + + end + else if (done_mat_mul == 0) begin + clk_cnt <= clk_cnt + 1; + + end + else begin + done_mat_mul <= 0; + clk_cnt <= clk_cnt + 1; + end +end +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] a16_data; +wire [`DWIDTH-1:0] a17_data; +wire [`DWIDTH-1:0] a18_data; +wire [`DWIDTH-1:0] a19_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; +wire [`DWIDTH-1:0] b16_data; +wire [`DWIDTH-1:0] b17_data; +wire [`DWIDTH-1:0] b18_data; +wire [`DWIDTH-1:0] b19_data; +wire [`DWIDTH-1:0] a1_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_1; +wire [`DWIDTH-1:0] a3_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_1; +wire [`DWIDTH-1:0] a4_data_delayed_2; +wire [`DWIDTH-1:0] a4_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_1; +wire [`DWIDTH-1:0] a5_data_delayed_2; +wire [`DWIDTH-1:0] a5_data_delayed_3; +wire [`DWIDTH-1:0] a5_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_1; +wire [`DWIDTH-1:0] a6_data_delayed_2; +wire [`DWIDTH-1:0] a6_data_delayed_3; +wire [`DWIDTH-1:0] a6_data_delayed_4; +wire [`DWIDTH-1:0] a6_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_1; +wire [`DWIDTH-1:0] a7_data_delayed_2; +wire [`DWIDTH-1:0] a7_data_delayed_3; +wire [`DWIDTH-1:0] a7_data_delayed_4; +wire [`DWIDTH-1:0] a7_data_delayed_5; +wire [`DWIDTH-1:0] a7_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_1; +wire [`DWIDTH-1:0] a8_data_delayed_2; +wire [`DWIDTH-1:0] a8_data_delayed_3; +wire [`DWIDTH-1:0] a8_data_delayed_4; +wire [`DWIDTH-1:0] a8_data_delayed_5; +wire [`DWIDTH-1:0] a8_data_delayed_6; +wire [`DWIDTH-1:0] a8_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_1; +wire [`DWIDTH-1:0] a9_data_delayed_2; +wire [`DWIDTH-1:0] a9_data_delayed_3; +wire [`DWIDTH-1:0] a9_data_delayed_4; +wire [`DWIDTH-1:0] a9_data_delayed_5; +wire [`DWIDTH-1:0] a9_data_delayed_6; +wire [`DWIDTH-1:0] a9_data_delayed_7; +wire [`DWIDTH-1:0] a9_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_1; +wire [`DWIDTH-1:0] a10_data_delayed_2; +wire [`DWIDTH-1:0] a10_data_delayed_3; +wire [`DWIDTH-1:0] a10_data_delayed_4; +wire [`DWIDTH-1:0] a10_data_delayed_5; +wire [`DWIDTH-1:0] a10_data_delayed_6; +wire [`DWIDTH-1:0] a10_data_delayed_7; +wire [`DWIDTH-1:0] a10_data_delayed_8; +wire [`DWIDTH-1:0] a10_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_1; +wire [`DWIDTH-1:0] a11_data_delayed_2; +wire [`DWIDTH-1:0] a11_data_delayed_3; +wire [`DWIDTH-1:0] a11_data_delayed_4; +wire [`DWIDTH-1:0] a11_data_delayed_5; +wire [`DWIDTH-1:0] a11_data_delayed_6; +wire [`DWIDTH-1:0] a11_data_delayed_7; +wire [`DWIDTH-1:0] a11_data_delayed_8; +wire [`DWIDTH-1:0] a11_data_delayed_9; +wire [`DWIDTH-1:0] a11_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_1; +wire [`DWIDTH-1:0] a12_data_delayed_2; +wire [`DWIDTH-1:0] a12_data_delayed_3; +wire [`DWIDTH-1:0] a12_data_delayed_4; +wire [`DWIDTH-1:0] a12_data_delayed_5; +wire [`DWIDTH-1:0] a12_data_delayed_6; +wire [`DWIDTH-1:0] a12_data_delayed_7; +wire [`DWIDTH-1:0] a12_data_delayed_8; +wire [`DWIDTH-1:0] a12_data_delayed_9; +wire [`DWIDTH-1:0] a12_data_delayed_10; +wire [`DWIDTH-1:0] a12_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_1; +wire [`DWIDTH-1:0] a13_data_delayed_2; +wire [`DWIDTH-1:0] a13_data_delayed_3; +wire [`DWIDTH-1:0] a13_data_delayed_4; +wire [`DWIDTH-1:0] a13_data_delayed_5; +wire [`DWIDTH-1:0] a13_data_delayed_6; +wire [`DWIDTH-1:0] a13_data_delayed_7; +wire [`DWIDTH-1:0] a13_data_delayed_8; +wire [`DWIDTH-1:0] a13_data_delayed_9; +wire [`DWIDTH-1:0] a13_data_delayed_10; +wire [`DWIDTH-1:0] a13_data_delayed_11; +wire [`DWIDTH-1:0] a13_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_1; +wire [`DWIDTH-1:0] a14_data_delayed_2; +wire [`DWIDTH-1:0] a14_data_delayed_3; +wire [`DWIDTH-1:0] a14_data_delayed_4; +wire [`DWIDTH-1:0] a14_data_delayed_5; +wire [`DWIDTH-1:0] a14_data_delayed_6; +wire [`DWIDTH-1:0] a14_data_delayed_7; +wire [`DWIDTH-1:0] a14_data_delayed_8; +wire [`DWIDTH-1:0] a14_data_delayed_9; +wire [`DWIDTH-1:0] a14_data_delayed_10; +wire [`DWIDTH-1:0] a14_data_delayed_11; +wire [`DWIDTH-1:0] a14_data_delayed_12; +wire [`DWIDTH-1:0] a14_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_1; +wire [`DWIDTH-1:0] a15_data_delayed_2; +wire [`DWIDTH-1:0] a15_data_delayed_3; +wire [`DWIDTH-1:0] a15_data_delayed_4; +wire [`DWIDTH-1:0] a15_data_delayed_5; +wire [`DWIDTH-1:0] a15_data_delayed_6; +wire [`DWIDTH-1:0] a15_data_delayed_7; +wire [`DWIDTH-1:0] a15_data_delayed_8; +wire [`DWIDTH-1:0] a15_data_delayed_9; +wire [`DWIDTH-1:0] a15_data_delayed_10; +wire [`DWIDTH-1:0] a15_data_delayed_11; +wire [`DWIDTH-1:0] a15_data_delayed_12; +wire [`DWIDTH-1:0] a15_data_delayed_13; +wire [`DWIDTH-1:0] a15_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_15; +wire [`DWIDTH-1:0] a16_data_delayed_1; +wire [`DWIDTH-1:0] a16_data_delayed_2; +wire [`DWIDTH-1:0] a16_data_delayed_3; +wire [`DWIDTH-1:0] a16_data_delayed_4; +wire [`DWIDTH-1:0] a16_data_delayed_5; +wire [`DWIDTH-1:0] a16_data_delayed_6; +wire [`DWIDTH-1:0] a16_data_delayed_7; +wire [`DWIDTH-1:0] a16_data_delayed_8; +wire [`DWIDTH-1:0] a16_data_delayed_9; +wire [`DWIDTH-1:0] a16_data_delayed_10; +wire [`DWIDTH-1:0] a16_data_delayed_11; +wire [`DWIDTH-1:0] a16_data_delayed_12; +wire [`DWIDTH-1:0] a16_data_delayed_13; +wire [`DWIDTH-1:0] a16_data_delayed_14; +wire [`DWIDTH-1:0] a16_data_delayed_15; +wire [`DWIDTH-1:0] a16_data_delayed_16; +wire [`DWIDTH-1:0] a17_data_delayed_1; +wire [`DWIDTH-1:0] a17_data_delayed_2; +wire [`DWIDTH-1:0] a17_data_delayed_3; +wire [`DWIDTH-1:0] a17_data_delayed_4; +wire [`DWIDTH-1:0] a17_data_delayed_5; +wire [`DWIDTH-1:0] a17_data_delayed_6; +wire [`DWIDTH-1:0] a17_data_delayed_7; +wire [`DWIDTH-1:0] a17_data_delayed_8; +wire [`DWIDTH-1:0] a17_data_delayed_9; +wire [`DWIDTH-1:0] a17_data_delayed_10; +wire [`DWIDTH-1:0] a17_data_delayed_11; +wire [`DWIDTH-1:0] a17_data_delayed_12; +wire [`DWIDTH-1:0] a17_data_delayed_13; +wire [`DWIDTH-1:0] a17_data_delayed_14; +wire [`DWIDTH-1:0] a17_data_delayed_15; +wire [`DWIDTH-1:0] a17_data_delayed_16; +wire [`DWIDTH-1:0] a17_data_delayed_17; +wire [`DWIDTH-1:0] a18_data_delayed_1; +wire [`DWIDTH-1:0] a18_data_delayed_2; +wire [`DWIDTH-1:0] a18_data_delayed_3; +wire [`DWIDTH-1:0] a18_data_delayed_4; +wire [`DWIDTH-1:0] a18_data_delayed_5; +wire [`DWIDTH-1:0] a18_data_delayed_6; +wire [`DWIDTH-1:0] a18_data_delayed_7; +wire [`DWIDTH-1:0] a18_data_delayed_8; +wire [`DWIDTH-1:0] a18_data_delayed_9; +wire [`DWIDTH-1:0] a18_data_delayed_10; +wire [`DWIDTH-1:0] a18_data_delayed_11; +wire [`DWIDTH-1:0] a18_data_delayed_12; +wire [`DWIDTH-1:0] a18_data_delayed_13; +wire [`DWIDTH-1:0] a18_data_delayed_14; +wire [`DWIDTH-1:0] a18_data_delayed_15; +wire [`DWIDTH-1:0] a18_data_delayed_16; +wire [`DWIDTH-1:0] a18_data_delayed_17; +wire [`DWIDTH-1:0] a18_data_delayed_18; +wire [`DWIDTH-1:0] a19_data_delayed_1; +wire [`DWIDTH-1:0] a19_data_delayed_2; +wire [`DWIDTH-1:0] a19_data_delayed_3; +wire [`DWIDTH-1:0] a19_data_delayed_4; +wire [`DWIDTH-1:0] a19_data_delayed_5; +wire [`DWIDTH-1:0] a19_data_delayed_6; +wire [`DWIDTH-1:0] a19_data_delayed_7; +wire [`DWIDTH-1:0] a19_data_delayed_8; +wire [`DWIDTH-1:0] a19_data_delayed_9; +wire [`DWIDTH-1:0] a19_data_delayed_10; +wire [`DWIDTH-1:0] a19_data_delayed_11; +wire [`DWIDTH-1:0] a19_data_delayed_12; +wire [`DWIDTH-1:0] a19_data_delayed_13; +wire [`DWIDTH-1:0] a19_data_delayed_14; +wire [`DWIDTH-1:0] a19_data_delayed_15; +wire [`DWIDTH-1:0] a19_data_delayed_16; +wire [`DWIDTH-1:0] a19_data_delayed_17; +wire [`DWIDTH-1:0] a19_data_delayed_18; +wire [`DWIDTH-1:0] a19_data_delayed_19; +wire [`DWIDTH-1:0] b1_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_1; +wire [`DWIDTH-1:0] b3_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_3; +wire [`DWIDTH-1:0] b4_data_delayed_1; +wire [`DWIDTH-1:0] b4_data_delayed_2; +wire [`DWIDTH-1:0] b4_data_delayed_3; +wire [`DWIDTH-1:0] b4_data_delayed_4; +wire [`DWIDTH-1:0] b5_data_delayed_1; +wire [`DWIDTH-1:0] b5_data_delayed_2; +wire [`DWIDTH-1:0] b5_data_delayed_3; +wire [`DWIDTH-1:0] b5_data_delayed_4; +wire [`DWIDTH-1:0] b5_data_delayed_5; +wire [`DWIDTH-1:0] b6_data_delayed_1; +wire [`DWIDTH-1:0] b6_data_delayed_2; +wire [`DWIDTH-1:0] b6_data_delayed_3; +wire [`DWIDTH-1:0] b6_data_delayed_4; +wire [`DWIDTH-1:0] b6_data_delayed_5; +wire [`DWIDTH-1:0] b6_data_delayed_6; +wire [`DWIDTH-1:0] b7_data_delayed_1; +wire [`DWIDTH-1:0] b7_data_delayed_2; +wire [`DWIDTH-1:0] b7_data_delayed_3; +wire [`DWIDTH-1:0] b7_data_delayed_4; +wire [`DWIDTH-1:0] b7_data_delayed_5; +wire [`DWIDTH-1:0] b7_data_delayed_6; +wire [`DWIDTH-1:0] b7_data_delayed_7; +wire [`DWIDTH-1:0] b8_data_delayed_1; +wire [`DWIDTH-1:0] b8_data_delayed_2; +wire [`DWIDTH-1:0] b8_data_delayed_3; +wire [`DWIDTH-1:0] b8_data_delayed_4; +wire [`DWIDTH-1:0] b8_data_delayed_5; +wire [`DWIDTH-1:0] b8_data_delayed_6; +wire [`DWIDTH-1:0] b8_data_delayed_7; +wire [`DWIDTH-1:0] b8_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_1; +wire [`DWIDTH-1:0] b9_data_delayed_2; +wire [`DWIDTH-1:0] b9_data_delayed_3; +wire [`DWIDTH-1:0] b9_data_delayed_4; +wire [`DWIDTH-1:0] b9_data_delayed_5; +wire [`DWIDTH-1:0] b9_data_delayed_6; +wire [`DWIDTH-1:0] b9_data_delayed_7; +wire [`DWIDTH-1:0] b9_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_1; +wire [`DWIDTH-1:0] b10_data_delayed_2; +wire [`DWIDTH-1:0] b10_data_delayed_3; +wire [`DWIDTH-1:0] b10_data_delayed_4; +wire [`DWIDTH-1:0] b10_data_delayed_5; +wire [`DWIDTH-1:0] b10_data_delayed_6; +wire [`DWIDTH-1:0] b10_data_delayed_7; +wire [`DWIDTH-1:0] b10_data_delayed_8; +wire [`DWIDTH-1:0] b10_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_1; +wire [`DWIDTH-1:0] b11_data_delayed_2; +wire [`DWIDTH-1:0] b11_data_delayed_3; +wire [`DWIDTH-1:0] b11_data_delayed_4; +wire [`DWIDTH-1:0] b11_data_delayed_5; +wire [`DWIDTH-1:0] b11_data_delayed_6; +wire [`DWIDTH-1:0] b11_data_delayed_7; +wire [`DWIDTH-1:0] b11_data_delayed_8; +wire [`DWIDTH-1:0] b11_data_delayed_9; +wire [`DWIDTH-1:0] b11_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_1; +wire [`DWIDTH-1:0] b12_data_delayed_2; +wire [`DWIDTH-1:0] b12_data_delayed_3; +wire [`DWIDTH-1:0] b12_data_delayed_4; +wire [`DWIDTH-1:0] b12_data_delayed_5; +wire [`DWIDTH-1:0] b12_data_delayed_6; +wire [`DWIDTH-1:0] b12_data_delayed_7; +wire [`DWIDTH-1:0] b12_data_delayed_8; +wire [`DWIDTH-1:0] b12_data_delayed_9; +wire [`DWIDTH-1:0] b12_data_delayed_10; +wire [`DWIDTH-1:0] b12_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_1; +wire [`DWIDTH-1:0] b13_data_delayed_2; +wire [`DWIDTH-1:0] b13_data_delayed_3; +wire [`DWIDTH-1:0] b13_data_delayed_4; +wire [`DWIDTH-1:0] b13_data_delayed_5; +wire [`DWIDTH-1:0] b13_data_delayed_6; +wire [`DWIDTH-1:0] b13_data_delayed_7; +wire [`DWIDTH-1:0] b13_data_delayed_8; +wire [`DWIDTH-1:0] b13_data_delayed_9; +wire [`DWIDTH-1:0] b13_data_delayed_10; +wire [`DWIDTH-1:0] b13_data_delayed_11; +wire [`DWIDTH-1:0] b13_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_1; +wire [`DWIDTH-1:0] b14_data_delayed_2; +wire [`DWIDTH-1:0] b14_data_delayed_3; +wire [`DWIDTH-1:0] b14_data_delayed_4; +wire [`DWIDTH-1:0] b14_data_delayed_5; +wire [`DWIDTH-1:0] b14_data_delayed_6; +wire [`DWIDTH-1:0] b14_data_delayed_7; +wire [`DWIDTH-1:0] b14_data_delayed_8; +wire [`DWIDTH-1:0] b14_data_delayed_9; +wire [`DWIDTH-1:0] b14_data_delayed_10; +wire [`DWIDTH-1:0] b14_data_delayed_11; +wire [`DWIDTH-1:0] b14_data_delayed_12; +wire [`DWIDTH-1:0] b14_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_1; +wire [`DWIDTH-1:0] b15_data_delayed_2; +wire [`DWIDTH-1:0] b15_data_delayed_3; +wire [`DWIDTH-1:0] b15_data_delayed_4; +wire [`DWIDTH-1:0] b15_data_delayed_5; +wire [`DWIDTH-1:0] b15_data_delayed_6; +wire [`DWIDTH-1:0] b15_data_delayed_7; +wire [`DWIDTH-1:0] b15_data_delayed_8; +wire [`DWIDTH-1:0] b15_data_delayed_9; +wire [`DWIDTH-1:0] b15_data_delayed_10; +wire [`DWIDTH-1:0] b15_data_delayed_11; +wire [`DWIDTH-1:0] b15_data_delayed_12; +wire [`DWIDTH-1:0] b15_data_delayed_13; +wire [`DWIDTH-1:0] b15_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_15; +wire [`DWIDTH-1:0] b16_data_delayed_1; +wire [`DWIDTH-1:0] b16_data_delayed_2; +wire [`DWIDTH-1:0] b16_data_delayed_3; +wire [`DWIDTH-1:0] b16_data_delayed_4; +wire [`DWIDTH-1:0] b16_data_delayed_5; +wire [`DWIDTH-1:0] b16_data_delayed_6; +wire [`DWIDTH-1:0] b16_data_delayed_7; +wire [`DWIDTH-1:0] b16_data_delayed_8; +wire [`DWIDTH-1:0] b16_data_delayed_9; +wire [`DWIDTH-1:0] b16_data_delayed_10; +wire [`DWIDTH-1:0] b16_data_delayed_11; +wire [`DWIDTH-1:0] b16_data_delayed_12; +wire [`DWIDTH-1:0] b16_data_delayed_13; +wire [`DWIDTH-1:0] b16_data_delayed_14; +wire [`DWIDTH-1:0] b16_data_delayed_15; +wire [`DWIDTH-1:0] b16_data_delayed_16; +wire [`DWIDTH-1:0] b17_data_delayed_1; +wire [`DWIDTH-1:0] b17_data_delayed_2; +wire [`DWIDTH-1:0] b17_data_delayed_3; +wire [`DWIDTH-1:0] b17_data_delayed_4; +wire [`DWIDTH-1:0] b17_data_delayed_5; +wire [`DWIDTH-1:0] b17_data_delayed_6; +wire [`DWIDTH-1:0] b17_data_delayed_7; +wire [`DWIDTH-1:0] b17_data_delayed_8; +wire [`DWIDTH-1:0] b17_data_delayed_9; +wire [`DWIDTH-1:0] b17_data_delayed_10; +wire [`DWIDTH-1:0] b17_data_delayed_11; +wire [`DWIDTH-1:0] b17_data_delayed_12; +wire [`DWIDTH-1:0] b17_data_delayed_13; +wire [`DWIDTH-1:0] b17_data_delayed_14; +wire [`DWIDTH-1:0] b17_data_delayed_15; +wire [`DWIDTH-1:0] b17_data_delayed_16; +wire [`DWIDTH-1:0] b17_data_delayed_17; +wire [`DWIDTH-1:0] b18_data_delayed_1; +wire [`DWIDTH-1:0] b18_data_delayed_2; +wire [`DWIDTH-1:0] b18_data_delayed_3; +wire [`DWIDTH-1:0] b18_data_delayed_4; +wire [`DWIDTH-1:0] b18_data_delayed_5; +wire [`DWIDTH-1:0] b18_data_delayed_6; +wire [`DWIDTH-1:0] b18_data_delayed_7; +wire [`DWIDTH-1:0] b18_data_delayed_8; +wire [`DWIDTH-1:0] b18_data_delayed_9; +wire [`DWIDTH-1:0] b18_data_delayed_10; +wire [`DWIDTH-1:0] b18_data_delayed_11; +wire [`DWIDTH-1:0] b18_data_delayed_12; +wire [`DWIDTH-1:0] b18_data_delayed_13; +wire [`DWIDTH-1:0] b18_data_delayed_14; +wire [`DWIDTH-1:0] b18_data_delayed_15; +wire [`DWIDTH-1:0] b18_data_delayed_16; +wire [`DWIDTH-1:0] b18_data_delayed_17; +wire [`DWIDTH-1:0] b18_data_delayed_18; +wire [`DWIDTH-1:0] b19_data_delayed_1; +wire [`DWIDTH-1:0] b19_data_delayed_2; +wire [`DWIDTH-1:0] b19_data_delayed_3; +wire [`DWIDTH-1:0] b19_data_delayed_4; +wire [`DWIDTH-1:0] b19_data_delayed_5; +wire [`DWIDTH-1:0] b19_data_delayed_6; +wire [`DWIDTH-1:0] b19_data_delayed_7; +wire [`DWIDTH-1:0] b19_data_delayed_8; +wire [`DWIDTH-1:0] b19_data_delayed_9; +wire [`DWIDTH-1:0] b19_data_delayed_10; +wire [`DWIDTH-1:0] b19_data_delayed_11; +wire [`DWIDTH-1:0] b19_data_delayed_12; +wire [`DWIDTH-1:0] b19_data_delayed_13; +wire [`DWIDTH-1:0] b19_data_delayed_14; +wire [`DWIDTH-1:0] b19_data_delayed_15; +wire [`DWIDTH-1:0] b19_data_delayed_16; +wire [`DWIDTH-1:0] b19_data_delayed_17; +wire [`DWIDTH-1:0] b19_data_delayed_18; +wire [`DWIDTH-1:0] b19_data_delayed_19; + + +////////////////////////////////////////////////////////////////////////// +// Instantiation of systolic data setup +////////////////////////////////////////////////////////////////////////// +systolic_data_setup u_systolic_data_setup( +.clk(clk), +.reset(reset), +.start_mat_mul(start_mat_mul), +.a_addr(a_addr), +.b_addr(b_addr), +.address_mat_a(address_mat_a), +.address_mat_b(address_mat_b), +.address_stride_a(address_stride_a), +.address_stride_b(address_stride_b), +.a_data(a_data), +.b_data(b_data), +.clk_cnt(clk_cnt), +.a0_data(a0_data), +.b0_data(b0_data), +.a1_data_delayed_1(a1_data_delayed_1), +.b1_data_delayed_1(b1_data_delayed_1), +.a2_data_delayed_2(a2_data_delayed_2), +.b2_data_delayed_2(b2_data_delayed_2), +.a3_data_delayed_3(a3_data_delayed_3), +.b3_data_delayed_3(b3_data_delayed_3), +.a4_data_delayed_4(a4_data_delayed_4), +.b4_data_delayed_4(b4_data_delayed_4), +.a5_data_delayed_5(a5_data_delayed_5), +.b5_data_delayed_5(b5_data_delayed_5), +.a6_data_delayed_6(a6_data_delayed_6), +.b6_data_delayed_6(b6_data_delayed_6), +.a7_data_delayed_7(a7_data_delayed_7), +.b7_data_delayed_7(b7_data_delayed_7), +.a8_data_delayed_8(a8_data_delayed_8), +.b8_data_delayed_8(b8_data_delayed_8), +.a9_data_delayed_9(a9_data_delayed_9), +.b9_data_delayed_9(b9_data_delayed_9), +.a10_data_delayed_10(a10_data_delayed_10), +.b10_data_delayed_10(b10_data_delayed_10), +.a11_data_delayed_11(a11_data_delayed_11), +.b11_data_delayed_11(b11_data_delayed_11), +.a12_data_delayed_12(a12_data_delayed_12), +.b12_data_delayed_12(b12_data_delayed_12), +.a13_data_delayed_13(a13_data_delayed_13), +.b13_data_delayed_13(b13_data_delayed_13), +.a14_data_delayed_14(a14_data_delayed_14), +.b14_data_delayed_14(b14_data_delayed_14), +.a15_data_delayed_15(a15_data_delayed_15), +.b15_data_delayed_15(b15_data_delayed_15), +.a16_data_delayed_16(a16_data_delayed_16), +.b16_data_delayed_16(b16_data_delayed_16), +.a17_data_delayed_17(a17_data_delayed_17), +.b17_data_delayed_17(b17_data_delayed_17), +.a18_data_delayed_18(a18_data_delayed_18), +.b18_data_delayed_18(b18_data_delayed_18), +.a19_data_delayed_19(a19_data_delayed_19), +.b19_data_delayed_19(b19_data_delayed_19), + +.validity_mask_a_rows(validity_mask_a_rows), +.validity_mask_a_cols(validity_mask_a_cols), +.validity_mask_b_rows(validity_mask_b_rows), +.validity_mask_b_cols(validity_mask_b_cols), + +.a_loc(a_loc), +.b_loc(b_loc) +); + +////////////////////////////////////////////////////////////////////////// +// Logic to mux data_in coming from neighboring matmuls +////////////////////////////////////////////////////////////////////////// +wire [`DWIDTH-1:0] a0; +wire [`DWIDTH-1:0] a1; +wire [`DWIDTH-1:0] a2; +wire [`DWIDTH-1:0] a3; +wire [`DWIDTH-1:0] a4; +wire [`DWIDTH-1:0] a5; +wire [`DWIDTH-1:0] a6; +wire [`DWIDTH-1:0] a7; +wire [`DWIDTH-1:0] a8; +wire [`DWIDTH-1:0] a9; +wire [`DWIDTH-1:0] a10; +wire [`DWIDTH-1:0] a11; +wire [`DWIDTH-1:0] a12; +wire [`DWIDTH-1:0] a13; +wire [`DWIDTH-1:0] a14; +wire [`DWIDTH-1:0] a15; +wire [`DWIDTH-1:0] a16; +wire [`DWIDTH-1:0] a17; +wire [`DWIDTH-1:0] a18; +wire [`DWIDTH-1:0] a19; +wire [`DWIDTH-1:0] b0; +wire [`DWIDTH-1:0] b1; +wire [`DWIDTH-1:0] b2; +wire [`DWIDTH-1:0] b3; +wire [`DWIDTH-1:0] b4; +wire [`DWIDTH-1:0] b5; +wire [`DWIDTH-1:0] b6; +wire [`DWIDTH-1:0] b7; +wire [`DWIDTH-1:0] b8; +wire [`DWIDTH-1:0] b9; +wire [`DWIDTH-1:0] b10; +wire [`DWIDTH-1:0] b11; +wire [`DWIDTH-1:0] b12; +wire [`DWIDTH-1:0] b13; +wire [`DWIDTH-1:0] b14; +wire [`DWIDTH-1:0] b15; +wire [`DWIDTH-1:0] b16; +wire [`DWIDTH-1:0] b17; +wire [`DWIDTH-1:0] b18; +wire [`DWIDTH-1:0] b19; + +wire [`DWIDTH-1:0] a0_data_in; +wire [`DWIDTH-1:0] a1_data_in; +wire [`DWIDTH-1:0] a2_data_in; +wire [`DWIDTH-1:0] a3_data_in; +wire [`DWIDTH-1:0] a4_data_in; +wire [`DWIDTH-1:0] a5_data_in; +wire [`DWIDTH-1:0] a6_data_in; +wire [`DWIDTH-1:0] a7_data_in; +wire [`DWIDTH-1:0] a8_data_in; +wire [`DWIDTH-1:0] a9_data_in; +wire [`DWIDTH-1:0] a10_data_in; +wire [`DWIDTH-1:0] a11_data_in; +wire [`DWIDTH-1:0] a12_data_in; +wire [`DWIDTH-1:0] a13_data_in; +wire [`DWIDTH-1:0] a14_data_in; +wire [`DWIDTH-1:0] a15_data_in; +wire [`DWIDTH-1:0] a16_data_in; +wire [`DWIDTH-1:0] a17_data_in; +wire [`DWIDTH-1:0] a18_data_in; +wire [`DWIDTH-1:0] a19_data_in; + +assign a0_data_in = a_data_in[1*`DWIDTH-1:0*`DWIDTH]; +assign a1_data_in = a_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign a2_data_in = a_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign a3_data_in = a_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign a4_data_in = a_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign a5_data_in = a_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign a6_data_in = a_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign a7_data_in = a_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign a8_data_in = a_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign a9_data_in = a_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign a10_data_in = a_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign a11_data_in = a_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign a12_data_in = a_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign a13_data_in = a_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign a14_data_in = a_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign a15_data_in = a_data_in[16*`DWIDTH-1:15*`DWIDTH]; +assign a16_data_in = a_data_in[17*`DWIDTH-1:16*`DWIDTH]; +assign a17_data_in = a_data_in[18*`DWIDTH-1:17*`DWIDTH]; +assign a18_data_in = a_data_in[19*`DWIDTH-1:18*`DWIDTH]; +assign a19_data_in = a_data_in[20*`DWIDTH-1:19*`DWIDTH]; + +wire [`DWIDTH-1:0] b0_data_in; +wire [`DWIDTH-1:0] b1_data_in; +wire [`DWIDTH-1:0] b2_data_in; +wire [`DWIDTH-1:0] b3_data_in; +wire [`DWIDTH-1:0] b4_data_in; +wire [`DWIDTH-1:0] b5_data_in; +wire [`DWIDTH-1:0] b6_data_in; +wire [`DWIDTH-1:0] b7_data_in; +wire [`DWIDTH-1:0] b8_data_in; +wire [`DWIDTH-1:0] b9_data_in; +wire [`DWIDTH-1:0] b10_data_in; +wire [`DWIDTH-1:0] b11_data_in; +wire [`DWIDTH-1:0] b12_data_in; +wire [`DWIDTH-1:0] b13_data_in; +wire [`DWIDTH-1:0] b14_data_in; +wire [`DWIDTH-1:0] b15_data_in; +wire [`DWIDTH-1:0] b16_data_in; +wire [`DWIDTH-1:0] b17_data_in; +wire [`DWIDTH-1:0] b18_data_in; +wire [`DWIDTH-1:0] b19_data_in; + +assign b0_data_in = b_data_in[1*`DWIDTH-1:0*`DWIDTH]; +assign b1_data_in = b_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign b2_data_in = b_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign b3_data_in = b_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign b4_data_in = b_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign b5_data_in = b_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign b6_data_in = b_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign b7_data_in = b_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign b8_data_in = b_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign b9_data_in = b_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign b10_data_in = b_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign b11_data_in = b_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign b12_data_in = b_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign b13_data_in = b_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign b14_data_in = b_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign b15_data_in = b_data_in[16*`DWIDTH-1:15*`DWIDTH]; +assign b16_data_in = b_data_in[17*`DWIDTH-1:16*`DWIDTH]; +assign b17_data_in = b_data_in[18*`DWIDTH-1:17*`DWIDTH]; +assign b18_data_in = b_data_in[19*`DWIDTH-1:18*`DWIDTH]; +assign b19_data_in = b_data_in[20*`DWIDTH-1:19*`DWIDTH]; + +assign a0 = (b_loc==0) ? a0_data : a0_data_in; +assign a1 = (b_loc==0) ? a1_data_delayed_1 : a1_data_in; +assign a2 = (b_loc==0) ? a2_data_delayed_2 : a2_data_in; +assign a3 = (b_loc==0) ? a3_data_delayed_3 : a3_data_in; +assign a4 = (b_loc==0) ? a4_data_delayed_4 : a4_data_in; +assign a5 = (b_loc==0) ? a5_data_delayed_5 : a5_data_in; +assign a6 = (b_loc==0) ? a6_data_delayed_6 : a6_data_in; +assign a7 = (b_loc==0) ? a7_data_delayed_7 : a7_data_in; +assign a8 = (b_loc==0) ? a8_data_delayed_8 : a8_data_in; +assign a9 = (b_loc==0) ? a9_data_delayed_9 : a9_data_in; +assign a10 = (b_loc==0) ? a10_data_delayed_10 : a10_data_in; +assign a11 = (b_loc==0) ? a11_data_delayed_11 : a11_data_in; +assign a12 = (b_loc==0) ? a12_data_delayed_12 : a12_data_in; +assign a13 = (b_loc==0) ? a13_data_delayed_13 : a13_data_in; +assign a14 = (b_loc==0) ? a14_data_delayed_14 : a14_data_in; +assign a15 = (b_loc==0) ? a15_data_delayed_15 : a15_data_in; +assign a16 = (b_loc==0) ? a16_data_delayed_16 : a16_data_in; +assign a17 = (b_loc==0) ? a17_data_delayed_17 : a17_data_in; +assign a18 = (b_loc==0) ? a18_data_delayed_18 : a18_data_in; +assign a19 = (b_loc==0) ? a19_data_delayed_19 : a19_data_in; + +assign b0 = (a_loc==0) ? b0_data : b0_data_in; +assign b1 = (a_loc==0) ? b1_data_delayed_1 : b1_data_in; +assign b2 = (a_loc==0) ? b2_data_delayed_2 : b2_data_in; +assign b3 = (a_loc==0) ? b3_data_delayed_3 : b3_data_in; +assign b4 = (a_loc==0) ? b4_data_delayed_4 : b4_data_in; +assign b5 = (a_loc==0) ? b5_data_delayed_5 : b5_data_in; +assign b6 = (a_loc==0) ? b6_data_delayed_6 : b6_data_in; +assign b7 = (a_loc==0) ? b7_data_delayed_7 : b7_data_in; +assign b8 = (a_loc==0) ? b8_data_delayed_8 : b8_data_in; +assign b9 = (a_loc==0) ? b9_data_delayed_9 : b9_data_in; +assign b10 = (a_loc==0) ? b10_data_delayed_10 : b10_data_in; +assign b11 = (a_loc==0) ? b11_data_delayed_11 : b11_data_in; +assign b12 = (a_loc==0) ? b12_data_delayed_12 : b12_data_in; +assign b13 = (a_loc==0) ? b13_data_delayed_13 : b13_data_in; +assign b14 = (a_loc==0) ? b14_data_delayed_14 : b14_data_in; +assign b15 = (a_loc==0) ? b15_data_delayed_15 : b15_data_in; +assign b16 = (a_loc==0) ? b16_data_delayed_16 : b16_data_in; +assign b17 = (a_loc==0) ? b17_data_delayed_17 : b17_data_in; +assign b18 = (a_loc==0) ? b18_data_delayed_18 : b18_data_in; +assign b19 = (a_loc==0) ? b19_data_delayed_19 : b19_data_in; + +wire [`DWIDTH-1:0] matrixC0_0; +wire [`DWIDTH-1:0] matrixC0_1; +wire [`DWIDTH-1:0] matrixC0_2; +wire [`DWIDTH-1:0] matrixC0_3; +wire [`DWIDTH-1:0] matrixC0_4; +wire [`DWIDTH-1:0] matrixC0_5; +wire [`DWIDTH-1:0] matrixC0_6; +wire [`DWIDTH-1:0] matrixC0_7; +wire [`DWIDTH-1:0] matrixC0_8; +wire [`DWIDTH-1:0] matrixC0_9; +wire [`DWIDTH-1:0] matrixC0_10; +wire [`DWIDTH-1:0] matrixC0_11; +wire [`DWIDTH-1:0] matrixC0_12; +wire [`DWIDTH-1:0] matrixC0_13; +wire [`DWIDTH-1:0] matrixC0_14; +wire [`DWIDTH-1:0] matrixC0_15; +wire [`DWIDTH-1:0] matrixC0_16; +wire [`DWIDTH-1:0] matrixC0_17; +wire [`DWIDTH-1:0] matrixC0_18; +wire [`DWIDTH-1:0] matrixC0_19; +wire [`DWIDTH-1:0] matrixC1_0; +wire [`DWIDTH-1:0] matrixC1_1; +wire [`DWIDTH-1:0] matrixC1_2; +wire [`DWIDTH-1:0] matrixC1_3; +wire [`DWIDTH-1:0] matrixC1_4; +wire [`DWIDTH-1:0] matrixC1_5; +wire [`DWIDTH-1:0] matrixC1_6; +wire [`DWIDTH-1:0] matrixC1_7; +wire [`DWIDTH-1:0] matrixC1_8; +wire [`DWIDTH-1:0] matrixC1_9; +wire [`DWIDTH-1:0] matrixC1_10; +wire [`DWIDTH-1:0] matrixC1_11; +wire [`DWIDTH-1:0] matrixC1_12; +wire [`DWIDTH-1:0] matrixC1_13; +wire [`DWIDTH-1:0] matrixC1_14; +wire [`DWIDTH-1:0] matrixC1_15; +wire [`DWIDTH-1:0] matrixC1_16; +wire [`DWIDTH-1:0] matrixC1_17; +wire [`DWIDTH-1:0] matrixC1_18; +wire [`DWIDTH-1:0] matrixC1_19; +wire [`DWIDTH-1:0] matrixC2_0; +wire [`DWIDTH-1:0] matrixC2_1; +wire [`DWIDTH-1:0] matrixC2_2; +wire [`DWIDTH-1:0] matrixC2_3; +wire [`DWIDTH-1:0] matrixC2_4; +wire [`DWIDTH-1:0] matrixC2_5; +wire [`DWIDTH-1:0] matrixC2_6; +wire [`DWIDTH-1:0] matrixC2_7; +wire [`DWIDTH-1:0] matrixC2_8; +wire [`DWIDTH-1:0] matrixC2_9; +wire [`DWIDTH-1:0] matrixC2_10; +wire [`DWIDTH-1:0] matrixC2_11; +wire [`DWIDTH-1:0] matrixC2_12; +wire [`DWIDTH-1:0] matrixC2_13; +wire [`DWIDTH-1:0] matrixC2_14; +wire [`DWIDTH-1:0] matrixC2_15; +wire [`DWIDTH-1:0] matrixC2_16; +wire [`DWIDTH-1:0] matrixC2_17; +wire [`DWIDTH-1:0] matrixC2_18; +wire [`DWIDTH-1:0] matrixC2_19; +wire [`DWIDTH-1:0] matrixC3_0; +wire [`DWIDTH-1:0] matrixC3_1; +wire [`DWIDTH-1:0] matrixC3_2; +wire [`DWIDTH-1:0] matrixC3_3; +wire [`DWIDTH-1:0] matrixC3_4; +wire [`DWIDTH-1:0] matrixC3_5; +wire [`DWIDTH-1:0] matrixC3_6; +wire [`DWIDTH-1:0] matrixC3_7; +wire [`DWIDTH-1:0] matrixC3_8; +wire [`DWIDTH-1:0] matrixC3_9; +wire [`DWIDTH-1:0] matrixC3_10; +wire [`DWIDTH-1:0] matrixC3_11; +wire [`DWIDTH-1:0] matrixC3_12; +wire [`DWIDTH-1:0] matrixC3_13; +wire [`DWIDTH-1:0] matrixC3_14; +wire [`DWIDTH-1:0] matrixC3_15; +wire [`DWIDTH-1:0] matrixC3_16; +wire [`DWIDTH-1:0] matrixC3_17; +wire [`DWIDTH-1:0] matrixC3_18; +wire [`DWIDTH-1:0] matrixC3_19; +wire [`DWIDTH-1:0] matrixC4_0; +wire [`DWIDTH-1:0] matrixC4_1; +wire [`DWIDTH-1:0] matrixC4_2; +wire [`DWIDTH-1:0] matrixC4_3; +wire [`DWIDTH-1:0] matrixC4_4; +wire [`DWIDTH-1:0] matrixC4_5; +wire [`DWIDTH-1:0] matrixC4_6; +wire [`DWIDTH-1:0] matrixC4_7; +wire [`DWIDTH-1:0] matrixC4_8; +wire [`DWIDTH-1:0] matrixC4_9; +wire [`DWIDTH-1:0] matrixC4_10; +wire [`DWIDTH-1:0] matrixC4_11; +wire [`DWIDTH-1:0] matrixC4_12; +wire [`DWIDTH-1:0] matrixC4_13; +wire [`DWIDTH-1:0] matrixC4_14; +wire [`DWIDTH-1:0] matrixC4_15; +wire [`DWIDTH-1:0] matrixC4_16; +wire [`DWIDTH-1:0] matrixC4_17; +wire [`DWIDTH-1:0] matrixC4_18; +wire [`DWIDTH-1:0] matrixC4_19; +wire [`DWIDTH-1:0] matrixC5_0; +wire [`DWIDTH-1:0] matrixC5_1; +wire [`DWIDTH-1:0] matrixC5_2; +wire [`DWIDTH-1:0] matrixC5_3; +wire [`DWIDTH-1:0] matrixC5_4; +wire [`DWIDTH-1:0] matrixC5_5; +wire [`DWIDTH-1:0] matrixC5_6; +wire [`DWIDTH-1:0] matrixC5_7; +wire [`DWIDTH-1:0] matrixC5_8; +wire [`DWIDTH-1:0] matrixC5_9; +wire [`DWIDTH-1:0] matrixC5_10; +wire [`DWIDTH-1:0] matrixC5_11; +wire [`DWIDTH-1:0] matrixC5_12; +wire [`DWIDTH-1:0] matrixC5_13; +wire [`DWIDTH-1:0] matrixC5_14; +wire [`DWIDTH-1:0] matrixC5_15; +wire [`DWIDTH-1:0] matrixC5_16; +wire [`DWIDTH-1:0] matrixC5_17; +wire [`DWIDTH-1:0] matrixC5_18; +wire [`DWIDTH-1:0] matrixC5_19; +wire [`DWIDTH-1:0] matrixC6_0; +wire [`DWIDTH-1:0] matrixC6_1; +wire [`DWIDTH-1:0] matrixC6_2; +wire [`DWIDTH-1:0] matrixC6_3; +wire [`DWIDTH-1:0] matrixC6_4; +wire [`DWIDTH-1:0] matrixC6_5; +wire [`DWIDTH-1:0] matrixC6_6; +wire [`DWIDTH-1:0] matrixC6_7; +wire [`DWIDTH-1:0] matrixC6_8; +wire [`DWIDTH-1:0] matrixC6_9; +wire [`DWIDTH-1:0] matrixC6_10; +wire [`DWIDTH-1:0] matrixC6_11; +wire [`DWIDTH-1:0] matrixC6_12; +wire [`DWIDTH-1:0] matrixC6_13; +wire [`DWIDTH-1:0] matrixC6_14; +wire [`DWIDTH-1:0] matrixC6_15; +wire [`DWIDTH-1:0] matrixC6_16; +wire [`DWIDTH-1:0] matrixC6_17; +wire [`DWIDTH-1:0] matrixC6_18; +wire [`DWIDTH-1:0] matrixC6_19; +wire [`DWIDTH-1:0] matrixC7_0; +wire [`DWIDTH-1:0] matrixC7_1; +wire [`DWIDTH-1:0] matrixC7_2; +wire [`DWIDTH-1:0] matrixC7_3; +wire [`DWIDTH-1:0] matrixC7_4; +wire [`DWIDTH-1:0] matrixC7_5; +wire [`DWIDTH-1:0] matrixC7_6; +wire [`DWIDTH-1:0] matrixC7_7; +wire [`DWIDTH-1:0] matrixC7_8; +wire [`DWIDTH-1:0] matrixC7_9; +wire [`DWIDTH-1:0] matrixC7_10; +wire [`DWIDTH-1:0] matrixC7_11; +wire [`DWIDTH-1:0] matrixC7_12; +wire [`DWIDTH-1:0] matrixC7_13; +wire [`DWIDTH-1:0] matrixC7_14; +wire [`DWIDTH-1:0] matrixC7_15; +wire [`DWIDTH-1:0] matrixC7_16; +wire [`DWIDTH-1:0] matrixC7_17; +wire [`DWIDTH-1:0] matrixC7_18; +wire [`DWIDTH-1:0] matrixC7_19; +wire [`DWIDTH-1:0] matrixC8_0; +wire [`DWIDTH-1:0] matrixC8_1; +wire [`DWIDTH-1:0] matrixC8_2; +wire [`DWIDTH-1:0] matrixC8_3; +wire [`DWIDTH-1:0] matrixC8_4; +wire [`DWIDTH-1:0] matrixC8_5; +wire [`DWIDTH-1:0] matrixC8_6; +wire [`DWIDTH-1:0] matrixC8_7; +wire [`DWIDTH-1:0] matrixC8_8; +wire [`DWIDTH-1:0] matrixC8_9; +wire [`DWIDTH-1:0] matrixC8_10; +wire [`DWIDTH-1:0] matrixC8_11; +wire [`DWIDTH-1:0] matrixC8_12; +wire [`DWIDTH-1:0] matrixC8_13; +wire [`DWIDTH-1:0] matrixC8_14; +wire [`DWIDTH-1:0] matrixC8_15; +wire [`DWIDTH-1:0] matrixC8_16; +wire [`DWIDTH-1:0] matrixC8_17; +wire [`DWIDTH-1:0] matrixC8_18; +wire [`DWIDTH-1:0] matrixC8_19; +wire [`DWIDTH-1:0] matrixC9_0; +wire [`DWIDTH-1:0] matrixC9_1; +wire [`DWIDTH-1:0] matrixC9_2; +wire [`DWIDTH-1:0] matrixC9_3; +wire [`DWIDTH-1:0] matrixC9_4; +wire [`DWIDTH-1:0] matrixC9_5; +wire [`DWIDTH-1:0] matrixC9_6; +wire [`DWIDTH-1:0] matrixC9_7; +wire [`DWIDTH-1:0] matrixC9_8; +wire [`DWIDTH-1:0] matrixC9_9; +wire [`DWIDTH-1:0] matrixC9_10; +wire [`DWIDTH-1:0] matrixC9_11; +wire [`DWIDTH-1:0] matrixC9_12; +wire [`DWIDTH-1:0] matrixC9_13; +wire [`DWIDTH-1:0] matrixC9_14; +wire [`DWIDTH-1:0] matrixC9_15; +wire [`DWIDTH-1:0] matrixC9_16; +wire [`DWIDTH-1:0] matrixC9_17; +wire [`DWIDTH-1:0] matrixC9_18; +wire [`DWIDTH-1:0] matrixC9_19; +wire [`DWIDTH-1:0] matrixC10_0; +wire [`DWIDTH-1:0] matrixC10_1; +wire [`DWIDTH-1:0] matrixC10_2; +wire [`DWIDTH-1:0] matrixC10_3; +wire [`DWIDTH-1:0] matrixC10_4; +wire [`DWIDTH-1:0] matrixC10_5; +wire [`DWIDTH-1:0] matrixC10_6; +wire [`DWIDTH-1:0] matrixC10_7; +wire [`DWIDTH-1:0] matrixC10_8; +wire [`DWIDTH-1:0] matrixC10_9; +wire [`DWIDTH-1:0] matrixC10_10; +wire [`DWIDTH-1:0] matrixC10_11; +wire [`DWIDTH-1:0] matrixC10_12; +wire [`DWIDTH-1:0] matrixC10_13; +wire [`DWIDTH-1:0] matrixC10_14; +wire [`DWIDTH-1:0] matrixC10_15; +wire [`DWIDTH-1:0] matrixC10_16; +wire [`DWIDTH-1:0] matrixC10_17; +wire [`DWIDTH-1:0] matrixC10_18; +wire [`DWIDTH-1:0] matrixC10_19; +wire [`DWIDTH-1:0] matrixC11_0; +wire [`DWIDTH-1:0] matrixC11_1; +wire [`DWIDTH-1:0] matrixC11_2; +wire [`DWIDTH-1:0] matrixC11_3; +wire [`DWIDTH-1:0] matrixC11_4; +wire [`DWIDTH-1:0] matrixC11_5; +wire [`DWIDTH-1:0] matrixC11_6; +wire [`DWIDTH-1:0] matrixC11_7; +wire [`DWIDTH-1:0] matrixC11_8; +wire [`DWIDTH-1:0] matrixC11_9; +wire [`DWIDTH-1:0] matrixC11_10; +wire [`DWIDTH-1:0] matrixC11_11; +wire [`DWIDTH-1:0] matrixC11_12; +wire [`DWIDTH-1:0] matrixC11_13; +wire [`DWIDTH-1:0] matrixC11_14; +wire [`DWIDTH-1:0] matrixC11_15; +wire [`DWIDTH-1:0] matrixC11_16; +wire [`DWIDTH-1:0] matrixC11_17; +wire [`DWIDTH-1:0] matrixC11_18; +wire [`DWIDTH-1:0] matrixC11_19; +wire [`DWIDTH-1:0] matrixC12_0; +wire [`DWIDTH-1:0] matrixC12_1; +wire [`DWIDTH-1:0] matrixC12_2; +wire [`DWIDTH-1:0] matrixC12_3; +wire [`DWIDTH-1:0] matrixC12_4; +wire [`DWIDTH-1:0] matrixC12_5; +wire [`DWIDTH-1:0] matrixC12_6; +wire [`DWIDTH-1:0] matrixC12_7; +wire [`DWIDTH-1:0] matrixC12_8; +wire [`DWIDTH-1:0] matrixC12_9; +wire [`DWIDTH-1:0] matrixC12_10; +wire [`DWIDTH-1:0] matrixC12_11; +wire [`DWIDTH-1:0] matrixC12_12; +wire [`DWIDTH-1:0] matrixC12_13; +wire [`DWIDTH-1:0] matrixC12_14; +wire [`DWIDTH-1:0] matrixC12_15; +wire [`DWIDTH-1:0] matrixC12_16; +wire [`DWIDTH-1:0] matrixC12_17; +wire [`DWIDTH-1:0] matrixC12_18; +wire [`DWIDTH-1:0] matrixC12_19; +wire [`DWIDTH-1:0] matrixC13_0; +wire [`DWIDTH-1:0] matrixC13_1; +wire [`DWIDTH-1:0] matrixC13_2; +wire [`DWIDTH-1:0] matrixC13_3; +wire [`DWIDTH-1:0] matrixC13_4; +wire [`DWIDTH-1:0] matrixC13_5; +wire [`DWIDTH-1:0] matrixC13_6; +wire [`DWIDTH-1:0] matrixC13_7; +wire [`DWIDTH-1:0] matrixC13_8; +wire [`DWIDTH-1:0] matrixC13_9; +wire [`DWIDTH-1:0] matrixC13_10; +wire [`DWIDTH-1:0] matrixC13_11; +wire [`DWIDTH-1:0] matrixC13_12; +wire [`DWIDTH-1:0] matrixC13_13; +wire [`DWIDTH-1:0] matrixC13_14; +wire [`DWIDTH-1:0] matrixC13_15; +wire [`DWIDTH-1:0] matrixC13_16; +wire [`DWIDTH-1:0] matrixC13_17; +wire [`DWIDTH-1:0] matrixC13_18; +wire [`DWIDTH-1:0] matrixC13_19; +wire [`DWIDTH-1:0] matrixC14_0; +wire [`DWIDTH-1:0] matrixC14_1; +wire [`DWIDTH-1:0] matrixC14_2; +wire [`DWIDTH-1:0] matrixC14_3; +wire [`DWIDTH-1:0] matrixC14_4; +wire [`DWIDTH-1:0] matrixC14_5; +wire [`DWIDTH-1:0] matrixC14_6; +wire [`DWIDTH-1:0] matrixC14_7; +wire [`DWIDTH-1:0] matrixC14_8; +wire [`DWIDTH-1:0] matrixC14_9; +wire [`DWIDTH-1:0] matrixC14_10; +wire [`DWIDTH-1:0] matrixC14_11; +wire [`DWIDTH-1:0] matrixC14_12; +wire [`DWIDTH-1:0] matrixC14_13; +wire [`DWIDTH-1:0] matrixC14_14; +wire [`DWIDTH-1:0] matrixC14_15; +wire [`DWIDTH-1:0] matrixC14_16; +wire [`DWIDTH-1:0] matrixC14_17; +wire [`DWIDTH-1:0] matrixC14_18; +wire [`DWIDTH-1:0] matrixC14_19; +wire [`DWIDTH-1:0] matrixC15_0; +wire [`DWIDTH-1:0] matrixC15_1; +wire [`DWIDTH-1:0] matrixC15_2; +wire [`DWIDTH-1:0] matrixC15_3; +wire [`DWIDTH-1:0] matrixC15_4; +wire [`DWIDTH-1:0] matrixC15_5; +wire [`DWIDTH-1:0] matrixC15_6; +wire [`DWIDTH-1:0] matrixC15_7; +wire [`DWIDTH-1:0] matrixC15_8; +wire [`DWIDTH-1:0] matrixC15_9; +wire [`DWIDTH-1:0] matrixC15_10; +wire [`DWIDTH-1:0] matrixC15_11; +wire [`DWIDTH-1:0] matrixC15_12; +wire [`DWIDTH-1:0] matrixC15_13; +wire [`DWIDTH-1:0] matrixC15_14; +wire [`DWIDTH-1:0] matrixC15_15; +wire [`DWIDTH-1:0] matrixC15_16; +wire [`DWIDTH-1:0] matrixC15_17; +wire [`DWIDTH-1:0] matrixC15_18; +wire [`DWIDTH-1:0] matrixC15_19; +wire [`DWIDTH-1:0] matrixC16_0; +wire [`DWIDTH-1:0] matrixC16_1; +wire [`DWIDTH-1:0] matrixC16_2; +wire [`DWIDTH-1:0] matrixC16_3; +wire [`DWIDTH-1:0] matrixC16_4; +wire [`DWIDTH-1:0] matrixC16_5; +wire [`DWIDTH-1:0] matrixC16_6; +wire [`DWIDTH-1:0] matrixC16_7; +wire [`DWIDTH-1:0] matrixC16_8; +wire [`DWIDTH-1:0] matrixC16_9; +wire [`DWIDTH-1:0] matrixC16_10; +wire [`DWIDTH-1:0] matrixC16_11; +wire [`DWIDTH-1:0] matrixC16_12; +wire [`DWIDTH-1:0] matrixC16_13; +wire [`DWIDTH-1:0] matrixC16_14; +wire [`DWIDTH-1:0] matrixC16_15; +wire [`DWIDTH-1:0] matrixC16_16; +wire [`DWIDTH-1:0] matrixC16_17; +wire [`DWIDTH-1:0] matrixC16_18; +wire [`DWIDTH-1:0] matrixC16_19; +wire [`DWIDTH-1:0] matrixC17_0; +wire [`DWIDTH-1:0] matrixC17_1; +wire [`DWIDTH-1:0] matrixC17_2; +wire [`DWIDTH-1:0] matrixC17_3; +wire [`DWIDTH-1:0] matrixC17_4; +wire [`DWIDTH-1:0] matrixC17_5; +wire [`DWIDTH-1:0] matrixC17_6; +wire [`DWIDTH-1:0] matrixC17_7; +wire [`DWIDTH-1:0] matrixC17_8; +wire [`DWIDTH-1:0] matrixC17_9; +wire [`DWIDTH-1:0] matrixC17_10; +wire [`DWIDTH-1:0] matrixC17_11; +wire [`DWIDTH-1:0] matrixC17_12; +wire [`DWIDTH-1:0] matrixC17_13; +wire [`DWIDTH-1:0] matrixC17_14; +wire [`DWIDTH-1:0] matrixC17_15; +wire [`DWIDTH-1:0] matrixC17_16; +wire [`DWIDTH-1:0] matrixC17_17; +wire [`DWIDTH-1:0] matrixC17_18; +wire [`DWIDTH-1:0] matrixC17_19; +wire [`DWIDTH-1:0] matrixC18_0; +wire [`DWIDTH-1:0] matrixC18_1; +wire [`DWIDTH-1:0] matrixC18_2; +wire [`DWIDTH-1:0] matrixC18_3; +wire [`DWIDTH-1:0] matrixC18_4; +wire [`DWIDTH-1:0] matrixC18_5; +wire [`DWIDTH-1:0] matrixC18_6; +wire [`DWIDTH-1:0] matrixC18_7; +wire [`DWIDTH-1:0] matrixC18_8; +wire [`DWIDTH-1:0] matrixC18_9; +wire [`DWIDTH-1:0] matrixC18_10; +wire [`DWIDTH-1:0] matrixC18_11; +wire [`DWIDTH-1:0] matrixC18_12; +wire [`DWIDTH-1:0] matrixC18_13; +wire [`DWIDTH-1:0] matrixC18_14; +wire [`DWIDTH-1:0] matrixC18_15; +wire [`DWIDTH-1:0] matrixC18_16; +wire [`DWIDTH-1:0] matrixC18_17; +wire [`DWIDTH-1:0] matrixC18_18; +wire [`DWIDTH-1:0] matrixC18_19; +wire [`DWIDTH-1:0] matrixC19_0; +wire [`DWIDTH-1:0] matrixC19_1; +wire [`DWIDTH-1:0] matrixC19_2; +wire [`DWIDTH-1:0] matrixC19_3; +wire [`DWIDTH-1:0] matrixC19_4; +wire [`DWIDTH-1:0] matrixC19_5; +wire [`DWIDTH-1:0] matrixC19_6; +wire [`DWIDTH-1:0] matrixC19_7; +wire [`DWIDTH-1:0] matrixC19_8; +wire [`DWIDTH-1:0] matrixC19_9; +wire [`DWIDTH-1:0] matrixC19_10; +wire [`DWIDTH-1:0] matrixC19_11; +wire [`DWIDTH-1:0] matrixC19_12; +wire [`DWIDTH-1:0] matrixC19_13; +wire [`DWIDTH-1:0] matrixC19_14; +wire [`DWIDTH-1:0] matrixC19_15; +wire [`DWIDTH-1:0] matrixC19_16; +wire [`DWIDTH-1:0] matrixC19_17; +wire [`DWIDTH-1:0] matrixC19_18; +wire [`DWIDTH-1:0] matrixC19_19; + +wire row_latch_en; +////////////////////////////////////////////////////////////////////////// +// Instantiation of the output logic +////////////////////////////////////////////////////////////////////////// +output_logic u_output_logic( +.start_mat_mul(start_mat_mul), +.done_mat_mul(done_mat_mul), +.address_mat_c(address_mat_c), +.address_stride_c(address_stride_c), +.c_data_out(c_data_out), +.c_data_in(c_data_in), +.c_addr(c_addr), +.c_data_available(c_data_available), +.clk_cnt(clk_cnt), +.row_latch_en(row_latch_en), +.matrixC0_0(matrixC0_0), +.matrixC0_1(matrixC0_1), +.matrixC0_2(matrixC0_2), +.matrixC0_3(matrixC0_3), +.matrixC0_4(matrixC0_4), +.matrixC0_5(matrixC0_5), +.matrixC0_6(matrixC0_6), +.matrixC0_7(matrixC0_7), +.matrixC0_8(matrixC0_8), +.matrixC0_9(matrixC0_9), +.matrixC0_10(matrixC0_10), +.matrixC0_11(matrixC0_11), +.matrixC0_12(matrixC0_12), +.matrixC0_13(matrixC0_13), +.matrixC0_14(matrixC0_14), +.matrixC0_15(matrixC0_15), +.matrixC0_16(matrixC0_16), +.matrixC0_17(matrixC0_17), +.matrixC0_18(matrixC0_18), +.matrixC0_19(matrixC0_19), +.matrixC1_0(matrixC1_0), +.matrixC1_1(matrixC1_1), +.matrixC1_2(matrixC1_2), +.matrixC1_3(matrixC1_3), +.matrixC1_4(matrixC1_4), +.matrixC1_5(matrixC1_5), +.matrixC1_6(matrixC1_6), +.matrixC1_7(matrixC1_7), +.matrixC1_8(matrixC1_8), +.matrixC1_9(matrixC1_9), +.matrixC1_10(matrixC1_10), +.matrixC1_11(matrixC1_11), +.matrixC1_12(matrixC1_12), +.matrixC1_13(matrixC1_13), +.matrixC1_14(matrixC1_14), +.matrixC1_15(matrixC1_15), +.matrixC1_16(matrixC1_16), +.matrixC1_17(matrixC1_17), +.matrixC1_18(matrixC1_18), +.matrixC1_19(matrixC1_19), +.matrixC2_0(matrixC2_0), +.matrixC2_1(matrixC2_1), +.matrixC2_2(matrixC2_2), +.matrixC2_3(matrixC2_3), +.matrixC2_4(matrixC2_4), +.matrixC2_5(matrixC2_5), +.matrixC2_6(matrixC2_6), +.matrixC2_7(matrixC2_7), +.matrixC2_8(matrixC2_8), +.matrixC2_9(matrixC2_9), +.matrixC2_10(matrixC2_10), +.matrixC2_11(matrixC2_11), +.matrixC2_12(matrixC2_12), +.matrixC2_13(matrixC2_13), +.matrixC2_14(matrixC2_14), +.matrixC2_15(matrixC2_15), +.matrixC2_16(matrixC2_16), +.matrixC2_17(matrixC2_17), +.matrixC2_18(matrixC2_18), +.matrixC2_19(matrixC2_19), +.matrixC3_0(matrixC3_0), +.matrixC3_1(matrixC3_1), +.matrixC3_2(matrixC3_2), +.matrixC3_3(matrixC3_3), +.matrixC3_4(matrixC3_4), +.matrixC3_5(matrixC3_5), +.matrixC3_6(matrixC3_6), +.matrixC3_7(matrixC3_7), +.matrixC3_8(matrixC3_8), +.matrixC3_9(matrixC3_9), +.matrixC3_10(matrixC3_10), +.matrixC3_11(matrixC3_11), +.matrixC3_12(matrixC3_12), +.matrixC3_13(matrixC3_13), +.matrixC3_14(matrixC3_14), +.matrixC3_15(matrixC3_15), +.matrixC3_16(matrixC3_16), +.matrixC3_17(matrixC3_17), +.matrixC3_18(matrixC3_18), +.matrixC3_19(matrixC3_19), +.matrixC4_0(matrixC4_0), +.matrixC4_1(matrixC4_1), +.matrixC4_2(matrixC4_2), +.matrixC4_3(matrixC4_3), +.matrixC4_4(matrixC4_4), +.matrixC4_5(matrixC4_5), +.matrixC4_6(matrixC4_6), +.matrixC4_7(matrixC4_7), +.matrixC4_8(matrixC4_8), +.matrixC4_9(matrixC4_9), +.matrixC4_10(matrixC4_10), +.matrixC4_11(matrixC4_11), +.matrixC4_12(matrixC4_12), +.matrixC4_13(matrixC4_13), +.matrixC4_14(matrixC4_14), +.matrixC4_15(matrixC4_15), +.matrixC4_16(matrixC4_16), +.matrixC4_17(matrixC4_17), +.matrixC4_18(matrixC4_18), +.matrixC4_19(matrixC4_19), +.matrixC5_0(matrixC5_0), +.matrixC5_1(matrixC5_1), +.matrixC5_2(matrixC5_2), +.matrixC5_3(matrixC5_3), +.matrixC5_4(matrixC5_4), +.matrixC5_5(matrixC5_5), +.matrixC5_6(matrixC5_6), +.matrixC5_7(matrixC5_7), +.matrixC5_8(matrixC5_8), +.matrixC5_9(matrixC5_9), +.matrixC5_10(matrixC5_10), +.matrixC5_11(matrixC5_11), +.matrixC5_12(matrixC5_12), +.matrixC5_13(matrixC5_13), +.matrixC5_14(matrixC5_14), +.matrixC5_15(matrixC5_15), +.matrixC5_16(matrixC5_16), +.matrixC5_17(matrixC5_17), +.matrixC5_18(matrixC5_18), +.matrixC5_19(matrixC5_19), +.matrixC6_0(matrixC6_0), +.matrixC6_1(matrixC6_1), +.matrixC6_2(matrixC6_2), +.matrixC6_3(matrixC6_3), +.matrixC6_4(matrixC6_4), +.matrixC6_5(matrixC6_5), +.matrixC6_6(matrixC6_6), +.matrixC6_7(matrixC6_7), +.matrixC6_8(matrixC6_8), +.matrixC6_9(matrixC6_9), +.matrixC6_10(matrixC6_10), +.matrixC6_11(matrixC6_11), +.matrixC6_12(matrixC6_12), +.matrixC6_13(matrixC6_13), +.matrixC6_14(matrixC6_14), +.matrixC6_15(matrixC6_15), +.matrixC6_16(matrixC6_16), +.matrixC6_17(matrixC6_17), +.matrixC6_18(matrixC6_18), +.matrixC6_19(matrixC6_19), +.matrixC7_0(matrixC7_0), +.matrixC7_1(matrixC7_1), +.matrixC7_2(matrixC7_2), +.matrixC7_3(matrixC7_3), +.matrixC7_4(matrixC7_4), +.matrixC7_5(matrixC7_5), +.matrixC7_6(matrixC7_6), +.matrixC7_7(matrixC7_7), +.matrixC7_8(matrixC7_8), +.matrixC7_9(matrixC7_9), +.matrixC7_10(matrixC7_10), +.matrixC7_11(matrixC7_11), +.matrixC7_12(matrixC7_12), +.matrixC7_13(matrixC7_13), +.matrixC7_14(matrixC7_14), +.matrixC7_15(matrixC7_15), +.matrixC7_16(matrixC7_16), +.matrixC7_17(matrixC7_17), +.matrixC7_18(matrixC7_18), +.matrixC7_19(matrixC7_19), +.matrixC8_0(matrixC8_0), +.matrixC8_1(matrixC8_1), +.matrixC8_2(matrixC8_2), +.matrixC8_3(matrixC8_3), +.matrixC8_4(matrixC8_4), +.matrixC8_5(matrixC8_5), +.matrixC8_6(matrixC8_6), +.matrixC8_7(matrixC8_7), +.matrixC8_8(matrixC8_8), +.matrixC8_9(matrixC8_9), +.matrixC8_10(matrixC8_10), +.matrixC8_11(matrixC8_11), +.matrixC8_12(matrixC8_12), +.matrixC8_13(matrixC8_13), +.matrixC8_14(matrixC8_14), +.matrixC8_15(matrixC8_15), +.matrixC8_16(matrixC8_16), +.matrixC8_17(matrixC8_17), +.matrixC8_18(matrixC8_18), +.matrixC8_19(matrixC8_19), +.matrixC9_0(matrixC9_0), +.matrixC9_1(matrixC9_1), +.matrixC9_2(matrixC9_2), +.matrixC9_3(matrixC9_3), +.matrixC9_4(matrixC9_4), +.matrixC9_5(matrixC9_5), +.matrixC9_6(matrixC9_6), +.matrixC9_7(matrixC9_7), +.matrixC9_8(matrixC9_8), +.matrixC9_9(matrixC9_9), +.matrixC9_10(matrixC9_10), +.matrixC9_11(matrixC9_11), +.matrixC9_12(matrixC9_12), +.matrixC9_13(matrixC9_13), +.matrixC9_14(matrixC9_14), +.matrixC9_15(matrixC9_15), +.matrixC9_16(matrixC9_16), +.matrixC9_17(matrixC9_17), +.matrixC9_18(matrixC9_18), +.matrixC9_19(matrixC9_19), +.matrixC10_0(matrixC10_0), +.matrixC10_1(matrixC10_1), +.matrixC10_2(matrixC10_2), +.matrixC10_3(matrixC10_3), +.matrixC10_4(matrixC10_4), +.matrixC10_5(matrixC10_5), +.matrixC10_6(matrixC10_6), +.matrixC10_7(matrixC10_7), +.matrixC10_8(matrixC10_8), +.matrixC10_9(matrixC10_9), +.matrixC10_10(matrixC10_10), +.matrixC10_11(matrixC10_11), +.matrixC10_12(matrixC10_12), +.matrixC10_13(matrixC10_13), +.matrixC10_14(matrixC10_14), +.matrixC10_15(matrixC10_15), +.matrixC10_16(matrixC10_16), +.matrixC10_17(matrixC10_17), +.matrixC10_18(matrixC10_18), +.matrixC10_19(matrixC10_19), +.matrixC11_0(matrixC11_0), +.matrixC11_1(matrixC11_1), +.matrixC11_2(matrixC11_2), +.matrixC11_3(matrixC11_3), +.matrixC11_4(matrixC11_4), +.matrixC11_5(matrixC11_5), +.matrixC11_6(matrixC11_6), +.matrixC11_7(matrixC11_7), +.matrixC11_8(matrixC11_8), +.matrixC11_9(matrixC11_9), +.matrixC11_10(matrixC11_10), +.matrixC11_11(matrixC11_11), +.matrixC11_12(matrixC11_12), +.matrixC11_13(matrixC11_13), +.matrixC11_14(matrixC11_14), +.matrixC11_15(matrixC11_15), +.matrixC11_16(matrixC11_16), +.matrixC11_17(matrixC11_17), +.matrixC11_18(matrixC11_18), +.matrixC11_19(matrixC11_19), +.matrixC12_0(matrixC12_0), +.matrixC12_1(matrixC12_1), +.matrixC12_2(matrixC12_2), +.matrixC12_3(matrixC12_3), +.matrixC12_4(matrixC12_4), +.matrixC12_5(matrixC12_5), +.matrixC12_6(matrixC12_6), +.matrixC12_7(matrixC12_7), +.matrixC12_8(matrixC12_8), +.matrixC12_9(matrixC12_9), +.matrixC12_10(matrixC12_10), +.matrixC12_11(matrixC12_11), +.matrixC12_12(matrixC12_12), +.matrixC12_13(matrixC12_13), +.matrixC12_14(matrixC12_14), +.matrixC12_15(matrixC12_15), +.matrixC12_16(matrixC12_16), +.matrixC12_17(matrixC12_17), +.matrixC12_18(matrixC12_18), +.matrixC12_19(matrixC12_19), +.matrixC13_0(matrixC13_0), +.matrixC13_1(matrixC13_1), +.matrixC13_2(matrixC13_2), +.matrixC13_3(matrixC13_3), +.matrixC13_4(matrixC13_4), +.matrixC13_5(matrixC13_5), +.matrixC13_6(matrixC13_6), +.matrixC13_7(matrixC13_7), +.matrixC13_8(matrixC13_8), +.matrixC13_9(matrixC13_9), +.matrixC13_10(matrixC13_10), +.matrixC13_11(matrixC13_11), +.matrixC13_12(matrixC13_12), +.matrixC13_13(matrixC13_13), +.matrixC13_14(matrixC13_14), +.matrixC13_15(matrixC13_15), +.matrixC13_16(matrixC13_16), +.matrixC13_17(matrixC13_17), +.matrixC13_18(matrixC13_18), +.matrixC13_19(matrixC13_19), +.matrixC14_0(matrixC14_0), +.matrixC14_1(matrixC14_1), +.matrixC14_2(matrixC14_2), +.matrixC14_3(matrixC14_3), +.matrixC14_4(matrixC14_4), +.matrixC14_5(matrixC14_5), +.matrixC14_6(matrixC14_6), +.matrixC14_7(matrixC14_7), +.matrixC14_8(matrixC14_8), +.matrixC14_9(matrixC14_9), +.matrixC14_10(matrixC14_10), +.matrixC14_11(matrixC14_11), +.matrixC14_12(matrixC14_12), +.matrixC14_13(matrixC14_13), +.matrixC14_14(matrixC14_14), +.matrixC14_15(matrixC14_15), +.matrixC14_16(matrixC14_16), +.matrixC14_17(matrixC14_17), +.matrixC14_18(matrixC14_18), +.matrixC14_19(matrixC14_19), +.matrixC15_0(matrixC15_0), +.matrixC15_1(matrixC15_1), +.matrixC15_2(matrixC15_2), +.matrixC15_3(matrixC15_3), +.matrixC15_4(matrixC15_4), +.matrixC15_5(matrixC15_5), +.matrixC15_6(matrixC15_6), +.matrixC15_7(matrixC15_7), +.matrixC15_8(matrixC15_8), +.matrixC15_9(matrixC15_9), +.matrixC15_10(matrixC15_10), +.matrixC15_11(matrixC15_11), +.matrixC15_12(matrixC15_12), +.matrixC15_13(matrixC15_13), +.matrixC15_14(matrixC15_14), +.matrixC15_15(matrixC15_15), +.matrixC15_16(matrixC15_16), +.matrixC15_17(matrixC15_17), +.matrixC15_18(matrixC15_18), +.matrixC15_19(matrixC15_19), +.matrixC16_0(matrixC16_0), +.matrixC16_1(matrixC16_1), +.matrixC16_2(matrixC16_2), +.matrixC16_3(matrixC16_3), +.matrixC16_4(matrixC16_4), +.matrixC16_5(matrixC16_5), +.matrixC16_6(matrixC16_6), +.matrixC16_7(matrixC16_7), +.matrixC16_8(matrixC16_8), +.matrixC16_9(matrixC16_9), +.matrixC16_10(matrixC16_10), +.matrixC16_11(matrixC16_11), +.matrixC16_12(matrixC16_12), +.matrixC16_13(matrixC16_13), +.matrixC16_14(matrixC16_14), +.matrixC16_15(matrixC16_15), +.matrixC16_16(matrixC16_16), +.matrixC16_17(matrixC16_17), +.matrixC16_18(matrixC16_18), +.matrixC16_19(matrixC16_19), +.matrixC17_0(matrixC17_0), +.matrixC17_1(matrixC17_1), +.matrixC17_2(matrixC17_2), +.matrixC17_3(matrixC17_3), +.matrixC17_4(matrixC17_4), +.matrixC17_5(matrixC17_5), +.matrixC17_6(matrixC17_6), +.matrixC17_7(matrixC17_7), +.matrixC17_8(matrixC17_8), +.matrixC17_9(matrixC17_9), +.matrixC17_10(matrixC17_10), +.matrixC17_11(matrixC17_11), +.matrixC17_12(matrixC17_12), +.matrixC17_13(matrixC17_13), +.matrixC17_14(matrixC17_14), +.matrixC17_15(matrixC17_15), +.matrixC17_16(matrixC17_16), +.matrixC17_17(matrixC17_17), +.matrixC17_18(matrixC17_18), +.matrixC17_19(matrixC17_19), +.matrixC18_0(matrixC18_0), +.matrixC18_1(matrixC18_1), +.matrixC18_2(matrixC18_2), +.matrixC18_3(matrixC18_3), +.matrixC18_4(matrixC18_4), +.matrixC18_5(matrixC18_5), +.matrixC18_6(matrixC18_6), +.matrixC18_7(matrixC18_7), +.matrixC18_8(matrixC18_8), +.matrixC18_9(matrixC18_9), +.matrixC18_10(matrixC18_10), +.matrixC18_11(matrixC18_11), +.matrixC18_12(matrixC18_12), +.matrixC18_13(matrixC18_13), +.matrixC18_14(matrixC18_14), +.matrixC18_15(matrixC18_15), +.matrixC18_16(matrixC18_16), +.matrixC18_17(matrixC18_17), +.matrixC18_18(matrixC18_18), +.matrixC18_19(matrixC18_19), +.matrixC19_0(matrixC19_0), +.matrixC19_1(matrixC19_1), +.matrixC19_2(matrixC19_2), +.matrixC19_3(matrixC19_3), +.matrixC19_4(matrixC19_4), +.matrixC19_5(matrixC19_5), +.matrixC19_6(matrixC19_6), +.matrixC19_7(matrixC19_7), +.matrixC19_8(matrixC19_8), +.matrixC19_9(matrixC19_9), +.matrixC19_10(matrixC19_10), +.matrixC19_11(matrixC19_11), +.matrixC19_12(matrixC19_12), +.matrixC19_13(matrixC19_13), +.matrixC19_14(matrixC19_14), +.matrixC19_15(matrixC19_15), +.matrixC19_16(matrixC19_16), +.matrixC19_17(matrixC19_17), +.matrixC19_18(matrixC19_18), +.matrixC19_19(matrixC19_19), + +.clk(clk), +.reset(reset) +); + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +systolic_pe_matrix u_systolic_pe_matrix( +.clk(clk), +.reset(reset), +.pe_reset(pe_reset), +.a0(a0), +.a1(a1), +.a2(a2), +.a3(a3), +.a4(a4), +.a5(a5), +.a6(a6), +.a7(a7), +.a8(a8), +.a9(a9), +.a10(a10), +.a11(a11), +.a12(a12), +.a13(a13), +.a14(a14), +.a15(a15), +.a16(a16), +.a17(a17), +.a18(a18), +.a19(a19), +.b0(b0), +.b1(b1), +.b2(b2), +.b3(b3), +.b4(b4), +.b5(b5), +.b6(b6), +.b7(b7), +.b8(b8), +.b9(b9), +.b10(b10), +.b11(b11), +.b12(b12), +.b13(b13), +.b14(b14), +.b15(b15), +.b16(b16), +.b17(b17), +.b18(b18), +.b19(b19), +.matrixC0_0(matrixC0_0), +.matrixC0_1(matrixC0_1), +.matrixC0_2(matrixC0_2), +.matrixC0_3(matrixC0_3), +.matrixC0_4(matrixC0_4), +.matrixC0_5(matrixC0_5), +.matrixC0_6(matrixC0_6), +.matrixC0_7(matrixC0_7), +.matrixC0_8(matrixC0_8), +.matrixC0_9(matrixC0_9), +.matrixC0_10(matrixC0_10), +.matrixC0_11(matrixC0_11), +.matrixC0_12(matrixC0_12), +.matrixC0_13(matrixC0_13), +.matrixC0_14(matrixC0_14), +.matrixC0_15(matrixC0_15), +.matrixC0_16(matrixC0_16), +.matrixC0_17(matrixC0_17), +.matrixC0_18(matrixC0_18), +.matrixC0_19(matrixC0_19), +.matrixC1_0(matrixC1_0), +.matrixC1_1(matrixC1_1), +.matrixC1_2(matrixC1_2), +.matrixC1_3(matrixC1_3), +.matrixC1_4(matrixC1_4), +.matrixC1_5(matrixC1_5), +.matrixC1_6(matrixC1_6), +.matrixC1_7(matrixC1_7), +.matrixC1_8(matrixC1_8), +.matrixC1_9(matrixC1_9), +.matrixC1_10(matrixC1_10), +.matrixC1_11(matrixC1_11), +.matrixC1_12(matrixC1_12), +.matrixC1_13(matrixC1_13), +.matrixC1_14(matrixC1_14), +.matrixC1_15(matrixC1_15), +.matrixC1_16(matrixC1_16), +.matrixC1_17(matrixC1_17), +.matrixC1_18(matrixC1_18), +.matrixC1_19(matrixC1_19), +.matrixC2_0(matrixC2_0), +.matrixC2_1(matrixC2_1), +.matrixC2_2(matrixC2_2), +.matrixC2_3(matrixC2_3), +.matrixC2_4(matrixC2_4), +.matrixC2_5(matrixC2_5), +.matrixC2_6(matrixC2_6), +.matrixC2_7(matrixC2_7), +.matrixC2_8(matrixC2_8), +.matrixC2_9(matrixC2_9), +.matrixC2_10(matrixC2_10), +.matrixC2_11(matrixC2_11), +.matrixC2_12(matrixC2_12), +.matrixC2_13(matrixC2_13), +.matrixC2_14(matrixC2_14), +.matrixC2_15(matrixC2_15), +.matrixC2_16(matrixC2_16), +.matrixC2_17(matrixC2_17), +.matrixC2_18(matrixC2_18), +.matrixC2_19(matrixC2_19), +.matrixC3_0(matrixC3_0), +.matrixC3_1(matrixC3_1), +.matrixC3_2(matrixC3_2), +.matrixC3_3(matrixC3_3), +.matrixC3_4(matrixC3_4), +.matrixC3_5(matrixC3_5), +.matrixC3_6(matrixC3_6), +.matrixC3_7(matrixC3_7), +.matrixC3_8(matrixC3_8), +.matrixC3_9(matrixC3_9), +.matrixC3_10(matrixC3_10), +.matrixC3_11(matrixC3_11), +.matrixC3_12(matrixC3_12), +.matrixC3_13(matrixC3_13), +.matrixC3_14(matrixC3_14), +.matrixC3_15(matrixC3_15), +.matrixC3_16(matrixC3_16), +.matrixC3_17(matrixC3_17), +.matrixC3_18(matrixC3_18), +.matrixC3_19(matrixC3_19), +.matrixC4_0(matrixC4_0), +.matrixC4_1(matrixC4_1), +.matrixC4_2(matrixC4_2), +.matrixC4_3(matrixC4_3), +.matrixC4_4(matrixC4_4), +.matrixC4_5(matrixC4_5), +.matrixC4_6(matrixC4_6), +.matrixC4_7(matrixC4_7), +.matrixC4_8(matrixC4_8), +.matrixC4_9(matrixC4_9), +.matrixC4_10(matrixC4_10), +.matrixC4_11(matrixC4_11), +.matrixC4_12(matrixC4_12), +.matrixC4_13(matrixC4_13), +.matrixC4_14(matrixC4_14), +.matrixC4_15(matrixC4_15), +.matrixC4_16(matrixC4_16), +.matrixC4_17(matrixC4_17), +.matrixC4_18(matrixC4_18), +.matrixC4_19(matrixC4_19), +.matrixC5_0(matrixC5_0), +.matrixC5_1(matrixC5_1), +.matrixC5_2(matrixC5_2), +.matrixC5_3(matrixC5_3), +.matrixC5_4(matrixC5_4), +.matrixC5_5(matrixC5_5), +.matrixC5_6(matrixC5_6), +.matrixC5_7(matrixC5_7), +.matrixC5_8(matrixC5_8), +.matrixC5_9(matrixC5_9), +.matrixC5_10(matrixC5_10), +.matrixC5_11(matrixC5_11), +.matrixC5_12(matrixC5_12), +.matrixC5_13(matrixC5_13), +.matrixC5_14(matrixC5_14), +.matrixC5_15(matrixC5_15), +.matrixC5_16(matrixC5_16), +.matrixC5_17(matrixC5_17), +.matrixC5_18(matrixC5_18), +.matrixC5_19(matrixC5_19), +.matrixC6_0(matrixC6_0), +.matrixC6_1(matrixC6_1), +.matrixC6_2(matrixC6_2), +.matrixC6_3(matrixC6_3), +.matrixC6_4(matrixC6_4), +.matrixC6_5(matrixC6_5), +.matrixC6_6(matrixC6_6), +.matrixC6_7(matrixC6_7), +.matrixC6_8(matrixC6_8), +.matrixC6_9(matrixC6_9), +.matrixC6_10(matrixC6_10), +.matrixC6_11(matrixC6_11), +.matrixC6_12(matrixC6_12), +.matrixC6_13(matrixC6_13), +.matrixC6_14(matrixC6_14), +.matrixC6_15(matrixC6_15), +.matrixC6_16(matrixC6_16), +.matrixC6_17(matrixC6_17), +.matrixC6_18(matrixC6_18), +.matrixC6_19(matrixC6_19), +.matrixC7_0(matrixC7_0), +.matrixC7_1(matrixC7_1), +.matrixC7_2(matrixC7_2), +.matrixC7_3(matrixC7_3), +.matrixC7_4(matrixC7_4), +.matrixC7_5(matrixC7_5), +.matrixC7_6(matrixC7_6), +.matrixC7_7(matrixC7_7), +.matrixC7_8(matrixC7_8), +.matrixC7_9(matrixC7_9), +.matrixC7_10(matrixC7_10), +.matrixC7_11(matrixC7_11), +.matrixC7_12(matrixC7_12), +.matrixC7_13(matrixC7_13), +.matrixC7_14(matrixC7_14), +.matrixC7_15(matrixC7_15), +.matrixC7_16(matrixC7_16), +.matrixC7_17(matrixC7_17), +.matrixC7_18(matrixC7_18), +.matrixC7_19(matrixC7_19), +.matrixC8_0(matrixC8_0), +.matrixC8_1(matrixC8_1), +.matrixC8_2(matrixC8_2), +.matrixC8_3(matrixC8_3), +.matrixC8_4(matrixC8_4), +.matrixC8_5(matrixC8_5), +.matrixC8_6(matrixC8_6), +.matrixC8_7(matrixC8_7), +.matrixC8_8(matrixC8_8), +.matrixC8_9(matrixC8_9), +.matrixC8_10(matrixC8_10), +.matrixC8_11(matrixC8_11), +.matrixC8_12(matrixC8_12), +.matrixC8_13(matrixC8_13), +.matrixC8_14(matrixC8_14), +.matrixC8_15(matrixC8_15), +.matrixC8_16(matrixC8_16), +.matrixC8_17(matrixC8_17), +.matrixC8_18(matrixC8_18), +.matrixC8_19(matrixC8_19), +.matrixC9_0(matrixC9_0), +.matrixC9_1(matrixC9_1), +.matrixC9_2(matrixC9_2), +.matrixC9_3(matrixC9_3), +.matrixC9_4(matrixC9_4), +.matrixC9_5(matrixC9_5), +.matrixC9_6(matrixC9_6), +.matrixC9_7(matrixC9_7), +.matrixC9_8(matrixC9_8), +.matrixC9_9(matrixC9_9), +.matrixC9_10(matrixC9_10), +.matrixC9_11(matrixC9_11), +.matrixC9_12(matrixC9_12), +.matrixC9_13(matrixC9_13), +.matrixC9_14(matrixC9_14), +.matrixC9_15(matrixC9_15), +.matrixC9_16(matrixC9_16), +.matrixC9_17(matrixC9_17), +.matrixC9_18(matrixC9_18), +.matrixC9_19(matrixC9_19), +.matrixC10_0(matrixC10_0), +.matrixC10_1(matrixC10_1), +.matrixC10_2(matrixC10_2), +.matrixC10_3(matrixC10_3), +.matrixC10_4(matrixC10_4), +.matrixC10_5(matrixC10_5), +.matrixC10_6(matrixC10_6), +.matrixC10_7(matrixC10_7), +.matrixC10_8(matrixC10_8), +.matrixC10_9(matrixC10_9), +.matrixC10_10(matrixC10_10), +.matrixC10_11(matrixC10_11), +.matrixC10_12(matrixC10_12), +.matrixC10_13(matrixC10_13), +.matrixC10_14(matrixC10_14), +.matrixC10_15(matrixC10_15), +.matrixC10_16(matrixC10_16), +.matrixC10_17(matrixC10_17), +.matrixC10_18(matrixC10_18), +.matrixC10_19(matrixC10_19), +.matrixC11_0(matrixC11_0), +.matrixC11_1(matrixC11_1), +.matrixC11_2(matrixC11_2), +.matrixC11_3(matrixC11_3), +.matrixC11_4(matrixC11_4), +.matrixC11_5(matrixC11_5), +.matrixC11_6(matrixC11_6), +.matrixC11_7(matrixC11_7), +.matrixC11_8(matrixC11_8), +.matrixC11_9(matrixC11_9), +.matrixC11_10(matrixC11_10), +.matrixC11_11(matrixC11_11), +.matrixC11_12(matrixC11_12), +.matrixC11_13(matrixC11_13), +.matrixC11_14(matrixC11_14), +.matrixC11_15(matrixC11_15), +.matrixC11_16(matrixC11_16), +.matrixC11_17(matrixC11_17), +.matrixC11_18(matrixC11_18), +.matrixC11_19(matrixC11_19), +.matrixC12_0(matrixC12_0), +.matrixC12_1(matrixC12_1), +.matrixC12_2(matrixC12_2), +.matrixC12_3(matrixC12_3), +.matrixC12_4(matrixC12_4), +.matrixC12_5(matrixC12_5), +.matrixC12_6(matrixC12_6), +.matrixC12_7(matrixC12_7), +.matrixC12_8(matrixC12_8), +.matrixC12_9(matrixC12_9), +.matrixC12_10(matrixC12_10), +.matrixC12_11(matrixC12_11), +.matrixC12_12(matrixC12_12), +.matrixC12_13(matrixC12_13), +.matrixC12_14(matrixC12_14), +.matrixC12_15(matrixC12_15), +.matrixC12_16(matrixC12_16), +.matrixC12_17(matrixC12_17), +.matrixC12_18(matrixC12_18), +.matrixC12_19(matrixC12_19), +.matrixC13_0(matrixC13_0), +.matrixC13_1(matrixC13_1), +.matrixC13_2(matrixC13_2), +.matrixC13_3(matrixC13_3), +.matrixC13_4(matrixC13_4), +.matrixC13_5(matrixC13_5), +.matrixC13_6(matrixC13_6), +.matrixC13_7(matrixC13_7), +.matrixC13_8(matrixC13_8), +.matrixC13_9(matrixC13_9), +.matrixC13_10(matrixC13_10), +.matrixC13_11(matrixC13_11), +.matrixC13_12(matrixC13_12), +.matrixC13_13(matrixC13_13), +.matrixC13_14(matrixC13_14), +.matrixC13_15(matrixC13_15), +.matrixC13_16(matrixC13_16), +.matrixC13_17(matrixC13_17), +.matrixC13_18(matrixC13_18), +.matrixC13_19(matrixC13_19), +.matrixC14_0(matrixC14_0), +.matrixC14_1(matrixC14_1), +.matrixC14_2(matrixC14_2), +.matrixC14_3(matrixC14_3), +.matrixC14_4(matrixC14_4), +.matrixC14_5(matrixC14_5), +.matrixC14_6(matrixC14_6), +.matrixC14_7(matrixC14_7), +.matrixC14_8(matrixC14_8), +.matrixC14_9(matrixC14_9), +.matrixC14_10(matrixC14_10), +.matrixC14_11(matrixC14_11), +.matrixC14_12(matrixC14_12), +.matrixC14_13(matrixC14_13), +.matrixC14_14(matrixC14_14), +.matrixC14_15(matrixC14_15), +.matrixC14_16(matrixC14_16), +.matrixC14_17(matrixC14_17), +.matrixC14_18(matrixC14_18), +.matrixC14_19(matrixC14_19), +.matrixC15_0(matrixC15_0), +.matrixC15_1(matrixC15_1), +.matrixC15_2(matrixC15_2), +.matrixC15_3(matrixC15_3), +.matrixC15_4(matrixC15_4), +.matrixC15_5(matrixC15_5), +.matrixC15_6(matrixC15_6), +.matrixC15_7(matrixC15_7), +.matrixC15_8(matrixC15_8), +.matrixC15_9(matrixC15_9), +.matrixC15_10(matrixC15_10), +.matrixC15_11(matrixC15_11), +.matrixC15_12(matrixC15_12), +.matrixC15_13(matrixC15_13), +.matrixC15_14(matrixC15_14), +.matrixC15_15(matrixC15_15), +.matrixC15_16(matrixC15_16), +.matrixC15_17(matrixC15_17), +.matrixC15_18(matrixC15_18), +.matrixC15_19(matrixC15_19), +.matrixC16_0(matrixC16_0), +.matrixC16_1(matrixC16_1), +.matrixC16_2(matrixC16_2), +.matrixC16_3(matrixC16_3), +.matrixC16_4(matrixC16_4), +.matrixC16_5(matrixC16_5), +.matrixC16_6(matrixC16_6), +.matrixC16_7(matrixC16_7), +.matrixC16_8(matrixC16_8), +.matrixC16_9(matrixC16_9), +.matrixC16_10(matrixC16_10), +.matrixC16_11(matrixC16_11), +.matrixC16_12(matrixC16_12), +.matrixC16_13(matrixC16_13), +.matrixC16_14(matrixC16_14), +.matrixC16_15(matrixC16_15), +.matrixC16_16(matrixC16_16), +.matrixC16_17(matrixC16_17), +.matrixC16_18(matrixC16_18), +.matrixC16_19(matrixC16_19), +.matrixC17_0(matrixC17_0), +.matrixC17_1(matrixC17_1), +.matrixC17_2(matrixC17_2), +.matrixC17_3(matrixC17_3), +.matrixC17_4(matrixC17_4), +.matrixC17_5(matrixC17_5), +.matrixC17_6(matrixC17_6), +.matrixC17_7(matrixC17_7), +.matrixC17_8(matrixC17_8), +.matrixC17_9(matrixC17_9), +.matrixC17_10(matrixC17_10), +.matrixC17_11(matrixC17_11), +.matrixC17_12(matrixC17_12), +.matrixC17_13(matrixC17_13), +.matrixC17_14(matrixC17_14), +.matrixC17_15(matrixC17_15), +.matrixC17_16(matrixC17_16), +.matrixC17_17(matrixC17_17), +.matrixC17_18(matrixC17_18), +.matrixC17_19(matrixC17_19), +.matrixC18_0(matrixC18_0), +.matrixC18_1(matrixC18_1), +.matrixC18_2(matrixC18_2), +.matrixC18_3(matrixC18_3), +.matrixC18_4(matrixC18_4), +.matrixC18_5(matrixC18_5), +.matrixC18_6(matrixC18_6), +.matrixC18_7(matrixC18_7), +.matrixC18_8(matrixC18_8), +.matrixC18_9(matrixC18_9), +.matrixC18_10(matrixC18_10), +.matrixC18_11(matrixC18_11), +.matrixC18_12(matrixC18_12), +.matrixC18_13(matrixC18_13), +.matrixC18_14(matrixC18_14), +.matrixC18_15(matrixC18_15), +.matrixC18_16(matrixC18_16), +.matrixC18_17(matrixC18_17), +.matrixC18_18(matrixC18_18), +.matrixC18_19(matrixC18_19), +.matrixC19_0(matrixC19_0), +.matrixC19_1(matrixC19_1), +.matrixC19_2(matrixC19_2), +.matrixC19_3(matrixC19_3), +.matrixC19_4(matrixC19_4), +.matrixC19_5(matrixC19_5), +.matrixC19_6(matrixC19_6), +.matrixC19_7(matrixC19_7), +.matrixC19_8(matrixC19_8), +.matrixC19_9(matrixC19_9), +.matrixC19_10(matrixC19_10), +.matrixC19_11(matrixC19_11), +.matrixC19_12(matrixC19_12), +.matrixC19_13(matrixC19_13), +.matrixC19_14(matrixC19_14), +.matrixC19_15(matrixC19_15), +.matrixC19_16(matrixC19_16), +.matrixC19_17(matrixC19_17), +.matrixC19_18(matrixC19_18), +.matrixC19_19(matrixC19_19), + +.a_data_out(a_data_out), +.b_data_out(b_data_out) +); + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Output logic +////////////////////////////////////////////////////////////////////////// +module output_logic( +start_mat_mul, +done_mat_mul, +address_mat_c, +address_stride_c, +c_data_in, +c_data_out, //Data values going out to next matmul - systolic shifting +c_addr, +c_data_available, +clk_cnt, +row_latch_en, +matrixC0_0, +matrixC0_1, +matrixC0_2, +matrixC0_3, +matrixC0_4, +matrixC0_5, +matrixC0_6, +matrixC0_7, +matrixC0_8, +matrixC0_9, +matrixC0_10, +matrixC0_11, +matrixC0_12, +matrixC0_13, +matrixC0_14, +matrixC0_15, +matrixC0_16, +matrixC0_17, +matrixC0_18, +matrixC0_19, +matrixC1_0, +matrixC1_1, +matrixC1_2, +matrixC1_3, +matrixC1_4, +matrixC1_5, +matrixC1_6, +matrixC1_7, +matrixC1_8, +matrixC1_9, +matrixC1_10, +matrixC1_11, +matrixC1_12, +matrixC1_13, +matrixC1_14, +matrixC1_15, +matrixC1_16, +matrixC1_17, +matrixC1_18, +matrixC1_19, +matrixC2_0, +matrixC2_1, +matrixC2_2, +matrixC2_3, +matrixC2_4, +matrixC2_5, +matrixC2_6, +matrixC2_7, +matrixC2_8, +matrixC2_9, +matrixC2_10, +matrixC2_11, +matrixC2_12, +matrixC2_13, +matrixC2_14, +matrixC2_15, +matrixC2_16, +matrixC2_17, +matrixC2_18, +matrixC2_19, +matrixC3_0, +matrixC3_1, +matrixC3_2, +matrixC3_3, +matrixC3_4, +matrixC3_5, +matrixC3_6, +matrixC3_7, +matrixC3_8, +matrixC3_9, +matrixC3_10, +matrixC3_11, +matrixC3_12, +matrixC3_13, +matrixC3_14, +matrixC3_15, +matrixC3_16, +matrixC3_17, +matrixC3_18, +matrixC3_19, +matrixC4_0, +matrixC4_1, +matrixC4_2, +matrixC4_3, +matrixC4_4, +matrixC4_5, +matrixC4_6, +matrixC4_7, +matrixC4_8, +matrixC4_9, +matrixC4_10, +matrixC4_11, +matrixC4_12, +matrixC4_13, +matrixC4_14, +matrixC4_15, +matrixC4_16, +matrixC4_17, +matrixC4_18, +matrixC4_19, +matrixC5_0, +matrixC5_1, +matrixC5_2, +matrixC5_3, +matrixC5_4, +matrixC5_5, +matrixC5_6, +matrixC5_7, +matrixC5_8, +matrixC5_9, +matrixC5_10, +matrixC5_11, +matrixC5_12, +matrixC5_13, +matrixC5_14, +matrixC5_15, +matrixC5_16, +matrixC5_17, +matrixC5_18, +matrixC5_19, +matrixC6_0, +matrixC6_1, +matrixC6_2, +matrixC6_3, +matrixC6_4, +matrixC6_5, +matrixC6_6, +matrixC6_7, +matrixC6_8, +matrixC6_9, +matrixC6_10, +matrixC6_11, +matrixC6_12, +matrixC6_13, +matrixC6_14, +matrixC6_15, +matrixC6_16, +matrixC6_17, +matrixC6_18, +matrixC6_19, +matrixC7_0, +matrixC7_1, +matrixC7_2, +matrixC7_3, +matrixC7_4, +matrixC7_5, +matrixC7_6, +matrixC7_7, +matrixC7_8, +matrixC7_9, +matrixC7_10, +matrixC7_11, +matrixC7_12, +matrixC7_13, +matrixC7_14, +matrixC7_15, +matrixC7_16, +matrixC7_17, +matrixC7_18, +matrixC7_19, +matrixC8_0, +matrixC8_1, +matrixC8_2, +matrixC8_3, +matrixC8_4, +matrixC8_5, +matrixC8_6, +matrixC8_7, +matrixC8_8, +matrixC8_9, +matrixC8_10, +matrixC8_11, +matrixC8_12, +matrixC8_13, +matrixC8_14, +matrixC8_15, +matrixC8_16, +matrixC8_17, +matrixC8_18, +matrixC8_19, +matrixC9_0, +matrixC9_1, +matrixC9_2, +matrixC9_3, +matrixC9_4, +matrixC9_5, +matrixC9_6, +matrixC9_7, +matrixC9_8, +matrixC9_9, +matrixC9_10, +matrixC9_11, +matrixC9_12, +matrixC9_13, +matrixC9_14, +matrixC9_15, +matrixC9_16, +matrixC9_17, +matrixC9_18, +matrixC9_19, +matrixC10_0, +matrixC10_1, +matrixC10_2, +matrixC10_3, +matrixC10_4, +matrixC10_5, +matrixC10_6, +matrixC10_7, +matrixC10_8, +matrixC10_9, +matrixC10_10, +matrixC10_11, +matrixC10_12, +matrixC10_13, +matrixC10_14, +matrixC10_15, +matrixC10_16, +matrixC10_17, +matrixC10_18, +matrixC10_19, +matrixC11_0, +matrixC11_1, +matrixC11_2, +matrixC11_3, +matrixC11_4, +matrixC11_5, +matrixC11_6, +matrixC11_7, +matrixC11_8, +matrixC11_9, +matrixC11_10, +matrixC11_11, +matrixC11_12, +matrixC11_13, +matrixC11_14, +matrixC11_15, +matrixC11_16, +matrixC11_17, +matrixC11_18, +matrixC11_19, +matrixC12_0, +matrixC12_1, +matrixC12_2, +matrixC12_3, +matrixC12_4, +matrixC12_5, +matrixC12_6, +matrixC12_7, +matrixC12_8, +matrixC12_9, +matrixC12_10, +matrixC12_11, +matrixC12_12, +matrixC12_13, +matrixC12_14, +matrixC12_15, +matrixC12_16, +matrixC12_17, +matrixC12_18, +matrixC12_19, +matrixC13_0, +matrixC13_1, +matrixC13_2, +matrixC13_3, +matrixC13_4, +matrixC13_5, +matrixC13_6, +matrixC13_7, +matrixC13_8, +matrixC13_9, +matrixC13_10, +matrixC13_11, +matrixC13_12, +matrixC13_13, +matrixC13_14, +matrixC13_15, +matrixC13_16, +matrixC13_17, +matrixC13_18, +matrixC13_19, +matrixC14_0, +matrixC14_1, +matrixC14_2, +matrixC14_3, +matrixC14_4, +matrixC14_5, +matrixC14_6, +matrixC14_7, +matrixC14_8, +matrixC14_9, +matrixC14_10, +matrixC14_11, +matrixC14_12, +matrixC14_13, +matrixC14_14, +matrixC14_15, +matrixC14_16, +matrixC14_17, +matrixC14_18, +matrixC14_19, +matrixC15_0, +matrixC15_1, +matrixC15_2, +matrixC15_3, +matrixC15_4, +matrixC15_5, +matrixC15_6, +matrixC15_7, +matrixC15_8, +matrixC15_9, +matrixC15_10, +matrixC15_11, +matrixC15_12, +matrixC15_13, +matrixC15_14, +matrixC15_15, +matrixC15_16, +matrixC15_17, +matrixC15_18, +matrixC15_19, +matrixC16_0, +matrixC16_1, +matrixC16_2, +matrixC16_3, +matrixC16_4, +matrixC16_5, +matrixC16_6, +matrixC16_7, +matrixC16_8, +matrixC16_9, +matrixC16_10, +matrixC16_11, +matrixC16_12, +matrixC16_13, +matrixC16_14, +matrixC16_15, +matrixC16_16, +matrixC16_17, +matrixC16_18, +matrixC16_19, +matrixC17_0, +matrixC17_1, +matrixC17_2, +matrixC17_3, +matrixC17_4, +matrixC17_5, +matrixC17_6, +matrixC17_7, +matrixC17_8, +matrixC17_9, +matrixC17_10, +matrixC17_11, +matrixC17_12, +matrixC17_13, +matrixC17_14, +matrixC17_15, +matrixC17_16, +matrixC17_17, +matrixC17_18, +matrixC17_19, +matrixC18_0, +matrixC18_1, +matrixC18_2, +matrixC18_3, +matrixC18_4, +matrixC18_5, +matrixC18_6, +matrixC18_7, +matrixC18_8, +matrixC18_9, +matrixC18_10, +matrixC18_11, +matrixC18_12, +matrixC18_13, +matrixC18_14, +matrixC18_15, +matrixC18_16, +matrixC18_17, +matrixC18_18, +matrixC18_19, +matrixC19_0, +matrixC19_1, +matrixC19_2, +matrixC19_3, +matrixC19_4, +matrixC19_5, +matrixC19_6, +matrixC19_7, +matrixC19_8, +matrixC19_9, +matrixC19_10, +matrixC19_11, +matrixC19_12, +matrixC19_13, +matrixC19_14, +matrixC19_15, +matrixC19_16, +matrixC19_17, +matrixC19_18, +matrixC19_19, + +clk, +reset +); + +input clk; +input reset; +input start_mat_mul; +input done_mat_mul; +input [`AWIDTH-1:0] address_mat_c; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; +output [`AWIDTH-1:0] c_addr; +output c_data_available; +input [7:0] clk_cnt; +output row_latch_en; +input [`DWIDTH-1:0] matrixC0_0; +input [`DWIDTH-1:0] matrixC0_1; +input [`DWIDTH-1:0] matrixC0_2; +input [`DWIDTH-1:0] matrixC0_3; +input [`DWIDTH-1:0] matrixC0_4; +input [`DWIDTH-1:0] matrixC0_5; +input [`DWIDTH-1:0] matrixC0_6; +input [`DWIDTH-1:0] matrixC0_7; +input [`DWIDTH-1:0] matrixC0_8; +input [`DWIDTH-1:0] matrixC0_9; +input [`DWIDTH-1:0] matrixC0_10; +input [`DWIDTH-1:0] matrixC0_11; +input [`DWIDTH-1:0] matrixC0_12; +input [`DWIDTH-1:0] matrixC0_13; +input [`DWIDTH-1:0] matrixC0_14; +input [`DWIDTH-1:0] matrixC0_15; +input [`DWIDTH-1:0] matrixC0_16; +input [`DWIDTH-1:0] matrixC0_17; +input [`DWIDTH-1:0] matrixC0_18; +input [`DWIDTH-1:0] matrixC0_19; +input [`DWIDTH-1:0] matrixC1_0; +input [`DWIDTH-1:0] matrixC1_1; +input [`DWIDTH-1:0] matrixC1_2; +input [`DWIDTH-1:0] matrixC1_3; +input [`DWIDTH-1:0] matrixC1_4; +input [`DWIDTH-1:0] matrixC1_5; +input [`DWIDTH-1:0] matrixC1_6; +input [`DWIDTH-1:0] matrixC1_7; +input [`DWIDTH-1:0] matrixC1_8; +input [`DWIDTH-1:0] matrixC1_9; +input [`DWIDTH-1:0] matrixC1_10; +input [`DWIDTH-1:0] matrixC1_11; +input [`DWIDTH-1:0] matrixC1_12; +input [`DWIDTH-1:0] matrixC1_13; +input [`DWIDTH-1:0] matrixC1_14; +input [`DWIDTH-1:0] matrixC1_15; +input [`DWIDTH-1:0] matrixC1_16; +input [`DWIDTH-1:0] matrixC1_17; +input [`DWIDTH-1:0] matrixC1_18; +input [`DWIDTH-1:0] matrixC1_19; +input [`DWIDTH-1:0] matrixC2_0; +input [`DWIDTH-1:0] matrixC2_1; +input [`DWIDTH-1:0] matrixC2_2; +input [`DWIDTH-1:0] matrixC2_3; +input [`DWIDTH-1:0] matrixC2_4; +input [`DWIDTH-1:0] matrixC2_5; +input [`DWIDTH-1:0] matrixC2_6; +input [`DWIDTH-1:0] matrixC2_7; +input [`DWIDTH-1:0] matrixC2_8; +input [`DWIDTH-1:0] matrixC2_9; +input [`DWIDTH-1:0] matrixC2_10; +input [`DWIDTH-1:0] matrixC2_11; +input [`DWIDTH-1:0] matrixC2_12; +input [`DWIDTH-1:0] matrixC2_13; +input [`DWIDTH-1:0] matrixC2_14; +input [`DWIDTH-1:0] matrixC2_15; +input [`DWIDTH-1:0] matrixC2_16; +input [`DWIDTH-1:0] matrixC2_17; +input [`DWIDTH-1:0] matrixC2_18; +input [`DWIDTH-1:0] matrixC2_19; +input [`DWIDTH-1:0] matrixC3_0; +input [`DWIDTH-1:0] matrixC3_1; +input [`DWIDTH-1:0] matrixC3_2; +input [`DWIDTH-1:0] matrixC3_3; +input [`DWIDTH-1:0] matrixC3_4; +input [`DWIDTH-1:0] matrixC3_5; +input [`DWIDTH-1:0] matrixC3_6; +input [`DWIDTH-1:0] matrixC3_7; +input [`DWIDTH-1:0] matrixC3_8; +input [`DWIDTH-1:0] matrixC3_9; +input [`DWIDTH-1:0] matrixC3_10; +input [`DWIDTH-1:0] matrixC3_11; +input [`DWIDTH-1:0] matrixC3_12; +input [`DWIDTH-1:0] matrixC3_13; +input [`DWIDTH-1:0] matrixC3_14; +input [`DWIDTH-1:0] matrixC3_15; +input [`DWIDTH-1:0] matrixC3_16; +input [`DWIDTH-1:0] matrixC3_17; +input [`DWIDTH-1:0] matrixC3_18; +input [`DWIDTH-1:0] matrixC3_19; +input [`DWIDTH-1:0] matrixC4_0; +input [`DWIDTH-1:0] matrixC4_1; +input [`DWIDTH-1:0] matrixC4_2; +input [`DWIDTH-1:0] matrixC4_3; +input [`DWIDTH-1:0] matrixC4_4; +input [`DWIDTH-1:0] matrixC4_5; +input [`DWIDTH-1:0] matrixC4_6; +input [`DWIDTH-1:0] matrixC4_7; +input [`DWIDTH-1:0] matrixC4_8; +input [`DWIDTH-1:0] matrixC4_9; +input [`DWIDTH-1:0] matrixC4_10; +input [`DWIDTH-1:0] matrixC4_11; +input [`DWIDTH-1:0] matrixC4_12; +input [`DWIDTH-1:0] matrixC4_13; +input [`DWIDTH-1:0] matrixC4_14; +input [`DWIDTH-1:0] matrixC4_15; +input [`DWIDTH-1:0] matrixC4_16; +input [`DWIDTH-1:0] matrixC4_17; +input [`DWIDTH-1:0] matrixC4_18; +input [`DWIDTH-1:0] matrixC4_19; +input [`DWIDTH-1:0] matrixC5_0; +input [`DWIDTH-1:0] matrixC5_1; +input [`DWIDTH-1:0] matrixC5_2; +input [`DWIDTH-1:0] matrixC5_3; +input [`DWIDTH-1:0] matrixC5_4; +input [`DWIDTH-1:0] matrixC5_5; +input [`DWIDTH-1:0] matrixC5_6; +input [`DWIDTH-1:0] matrixC5_7; +input [`DWIDTH-1:0] matrixC5_8; +input [`DWIDTH-1:0] matrixC5_9; +input [`DWIDTH-1:0] matrixC5_10; +input [`DWIDTH-1:0] matrixC5_11; +input [`DWIDTH-1:0] matrixC5_12; +input [`DWIDTH-1:0] matrixC5_13; +input [`DWIDTH-1:0] matrixC5_14; +input [`DWIDTH-1:0] matrixC5_15; +input [`DWIDTH-1:0] matrixC5_16; +input [`DWIDTH-1:0] matrixC5_17; +input [`DWIDTH-1:0] matrixC5_18; +input [`DWIDTH-1:0] matrixC5_19; +input [`DWIDTH-1:0] matrixC6_0; +input [`DWIDTH-1:0] matrixC6_1; +input [`DWIDTH-1:0] matrixC6_2; +input [`DWIDTH-1:0] matrixC6_3; +input [`DWIDTH-1:0] matrixC6_4; +input [`DWIDTH-1:0] matrixC6_5; +input [`DWIDTH-1:0] matrixC6_6; +input [`DWIDTH-1:0] matrixC6_7; +input [`DWIDTH-1:0] matrixC6_8; +input [`DWIDTH-1:0] matrixC6_9; +input [`DWIDTH-1:0] matrixC6_10; +input [`DWIDTH-1:0] matrixC6_11; +input [`DWIDTH-1:0] matrixC6_12; +input [`DWIDTH-1:0] matrixC6_13; +input [`DWIDTH-1:0] matrixC6_14; +input [`DWIDTH-1:0] matrixC6_15; +input [`DWIDTH-1:0] matrixC6_16; +input [`DWIDTH-1:0] matrixC6_17; +input [`DWIDTH-1:0] matrixC6_18; +input [`DWIDTH-1:0] matrixC6_19; +input [`DWIDTH-1:0] matrixC7_0; +input [`DWIDTH-1:0] matrixC7_1; +input [`DWIDTH-1:0] matrixC7_2; +input [`DWIDTH-1:0] matrixC7_3; +input [`DWIDTH-1:0] matrixC7_4; +input [`DWIDTH-1:0] matrixC7_5; +input [`DWIDTH-1:0] matrixC7_6; +input [`DWIDTH-1:0] matrixC7_7; +input [`DWIDTH-1:0] matrixC7_8; +input [`DWIDTH-1:0] matrixC7_9; +input [`DWIDTH-1:0] matrixC7_10; +input [`DWIDTH-1:0] matrixC7_11; +input [`DWIDTH-1:0] matrixC7_12; +input [`DWIDTH-1:0] matrixC7_13; +input [`DWIDTH-1:0] matrixC7_14; +input [`DWIDTH-1:0] matrixC7_15; +input [`DWIDTH-1:0] matrixC7_16; +input [`DWIDTH-1:0] matrixC7_17; +input [`DWIDTH-1:0] matrixC7_18; +input [`DWIDTH-1:0] matrixC7_19; +input [`DWIDTH-1:0] matrixC8_0; +input [`DWIDTH-1:0] matrixC8_1; +input [`DWIDTH-1:0] matrixC8_2; +input [`DWIDTH-1:0] matrixC8_3; +input [`DWIDTH-1:0] matrixC8_4; +input [`DWIDTH-1:0] matrixC8_5; +input [`DWIDTH-1:0] matrixC8_6; +input [`DWIDTH-1:0] matrixC8_7; +input [`DWIDTH-1:0] matrixC8_8; +input [`DWIDTH-1:0] matrixC8_9; +input [`DWIDTH-1:0] matrixC8_10; +input [`DWIDTH-1:0] matrixC8_11; +input [`DWIDTH-1:0] matrixC8_12; +input [`DWIDTH-1:0] matrixC8_13; +input [`DWIDTH-1:0] matrixC8_14; +input [`DWIDTH-1:0] matrixC8_15; +input [`DWIDTH-1:0] matrixC8_16; +input [`DWIDTH-1:0] matrixC8_17; +input [`DWIDTH-1:0] matrixC8_18; +input [`DWIDTH-1:0] matrixC8_19; +input [`DWIDTH-1:0] matrixC9_0; +input [`DWIDTH-1:0] matrixC9_1; +input [`DWIDTH-1:0] matrixC9_2; +input [`DWIDTH-1:0] matrixC9_3; +input [`DWIDTH-1:0] matrixC9_4; +input [`DWIDTH-1:0] matrixC9_5; +input [`DWIDTH-1:0] matrixC9_6; +input [`DWIDTH-1:0] matrixC9_7; +input [`DWIDTH-1:0] matrixC9_8; +input [`DWIDTH-1:0] matrixC9_9; +input [`DWIDTH-1:0] matrixC9_10; +input [`DWIDTH-1:0] matrixC9_11; +input [`DWIDTH-1:0] matrixC9_12; +input [`DWIDTH-1:0] matrixC9_13; +input [`DWIDTH-1:0] matrixC9_14; +input [`DWIDTH-1:0] matrixC9_15; +input [`DWIDTH-1:0] matrixC9_16; +input [`DWIDTH-1:0] matrixC9_17; +input [`DWIDTH-1:0] matrixC9_18; +input [`DWIDTH-1:0] matrixC9_19; +input [`DWIDTH-1:0] matrixC10_0; +input [`DWIDTH-1:0] matrixC10_1; +input [`DWIDTH-1:0] matrixC10_2; +input [`DWIDTH-1:0] matrixC10_3; +input [`DWIDTH-1:0] matrixC10_4; +input [`DWIDTH-1:0] matrixC10_5; +input [`DWIDTH-1:0] matrixC10_6; +input [`DWIDTH-1:0] matrixC10_7; +input [`DWIDTH-1:0] matrixC10_8; +input [`DWIDTH-1:0] matrixC10_9; +input [`DWIDTH-1:0] matrixC10_10; +input [`DWIDTH-1:0] matrixC10_11; +input [`DWIDTH-1:0] matrixC10_12; +input [`DWIDTH-1:0] matrixC10_13; +input [`DWIDTH-1:0] matrixC10_14; +input [`DWIDTH-1:0] matrixC10_15; +input [`DWIDTH-1:0] matrixC10_16; +input [`DWIDTH-1:0] matrixC10_17; +input [`DWIDTH-1:0] matrixC10_18; +input [`DWIDTH-1:0] matrixC10_19; +input [`DWIDTH-1:0] matrixC11_0; +input [`DWIDTH-1:0] matrixC11_1; +input [`DWIDTH-1:0] matrixC11_2; +input [`DWIDTH-1:0] matrixC11_3; +input [`DWIDTH-1:0] matrixC11_4; +input [`DWIDTH-1:0] matrixC11_5; +input [`DWIDTH-1:0] matrixC11_6; +input [`DWIDTH-1:0] matrixC11_7; +input [`DWIDTH-1:0] matrixC11_8; +input [`DWIDTH-1:0] matrixC11_9; +input [`DWIDTH-1:0] matrixC11_10; +input [`DWIDTH-1:0] matrixC11_11; +input [`DWIDTH-1:0] matrixC11_12; +input [`DWIDTH-1:0] matrixC11_13; +input [`DWIDTH-1:0] matrixC11_14; +input [`DWIDTH-1:0] matrixC11_15; +input [`DWIDTH-1:0] matrixC11_16; +input [`DWIDTH-1:0] matrixC11_17; +input [`DWIDTH-1:0] matrixC11_18; +input [`DWIDTH-1:0] matrixC11_19; +input [`DWIDTH-1:0] matrixC12_0; +input [`DWIDTH-1:0] matrixC12_1; +input [`DWIDTH-1:0] matrixC12_2; +input [`DWIDTH-1:0] matrixC12_3; +input [`DWIDTH-1:0] matrixC12_4; +input [`DWIDTH-1:0] matrixC12_5; +input [`DWIDTH-1:0] matrixC12_6; +input [`DWIDTH-1:0] matrixC12_7; +input [`DWIDTH-1:0] matrixC12_8; +input [`DWIDTH-1:0] matrixC12_9; +input [`DWIDTH-1:0] matrixC12_10; +input [`DWIDTH-1:0] matrixC12_11; +input [`DWIDTH-1:0] matrixC12_12; +input [`DWIDTH-1:0] matrixC12_13; +input [`DWIDTH-1:0] matrixC12_14; +input [`DWIDTH-1:0] matrixC12_15; +input [`DWIDTH-1:0] matrixC12_16; +input [`DWIDTH-1:0] matrixC12_17; +input [`DWIDTH-1:0] matrixC12_18; +input [`DWIDTH-1:0] matrixC12_19; +input [`DWIDTH-1:0] matrixC13_0; +input [`DWIDTH-1:0] matrixC13_1; +input [`DWIDTH-1:0] matrixC13_2; +input [`DWIDTH-1:0] matrixC13_3; +input [`DWIDTH-1:0] matrixC13_4; +input [`DWIDTH-1:0] matrixC13_5; +input [`DWIDTH-1:0] matrixC13_6; +input [`DWIDTH-1:0] matrixC13_7; +input [`DWIDTH-1:0] matrixC13_8; +input [`DWIDTH-1:0] matrixC13_9; +input [`DWIDTH-1:0] matrixC13_10; +input [`DWIDTH-1:0] matrixC13_11; +input [`DWIDTH-1:0] matrixC13_12; +input [`DWIDTH-1:0] matrixC13_13; +input [`DWIDTH-1:0] matrixC13_14; +input [`DWIDTH-1:0] matrixC13_15; +input [`DWIDTH-1:0] matrixC13_16; +input [`DWIDTH-1:0] matrixC13_17; +input [`DWIDTH-1:0] matrixC13_18; +input [`DWIDTH-1:0] matrixC13_19; +input [`DWIDTH-1:0] matrixC14_0; +input [`DWIDTH-1:0] matrixC14_1; +input [`DWIDTH-1:0] matrixC14_2; +input [`DWIDTH-1:0] matrixC14_3; +input [`DWIDTH-1:0] matrixC14_4; +input [`DWIDTH-1:0] matrixC14_5; +input [`DWIDTH-1:0] matrixC14_6; +input [`DWIDTH-1:0] matrixC14_7; +input [`DWIDTH-1:0] matrixC14_8; +input [`DWIDTH-1:0] matrixC14_9; +input [`DWIDTH-1:0] matrixC14_10; +input [`DWIDTH-1:0] matrixC14_11; +input [`DWIDTH-1:0] matrixC14_12; +input [`DWIDTH-1:0] matrixC14_13; +input [`DWIDTH-1:0] matrixC14_14; +input [`DWIDTH-1:0] matrixC14_15; +input [`DWIDTH-1:0] matrixC14_16; +input [`DWIDTH-1:0] matrixC14_17; +input [`DWIDTH-1:0] matrixC14_18; +input [`DWIDTH-1:0] matrixC14_19; +input [`DWIDTH-1:0] matrixC15_0; +input [`DWIDTH-1:0] matrixC15_1; +input [`DWIDTH-1:0] matrixC15_2; +input [`DWIDTH-1:0] matrixC15_3; +input [`DWIDTH-1:0] matrixC15_4; +input [`DWIDTH-1:0] matrixC15_5; +input [`DWIDTH-1:0] matrixC15_6; +input [`DWIDTH-1:0] matrixC15_7; +input [`DWIDTH-1:0] matrixC15_8; +input [`DWIDTH-1:0] matrixC15_9; +input [`DWIDTH-1:0] matrixC15_10; +input [`DWIDTH-1:0] matrixC15_11; +input [`DWIDTH-1:0] matrixC15_12; +input [`DWIDTH-1:0] matrixC15_13; +input [`DWIDTH-1:0] matrixC15_14; +input [`DWIDTH-1:0] matrixC15_15; +input [`DWIDTH-1:0] matrixC15_16; +input [`DWIDTH-1:0] matrixC15_17; +input [`DWIDTH-1:0] matrixC15_18; +input [`DWIDTH-1:0] matrixC15_19; +input [`DWIDTH-1:0] matrixC16_0; +input [`DWIDTH-1:0] matrixC16_1; +input [`DWIDTH-1:0] matrixC16_2; +input [`DWIDTH-1:0] matrixC16_3; +input [`DWIDTH-1:0] matrixC16_4; +input [`DWIDTH-1:0] matrixC16_5; +input [`DWIDTH-1:0] matrixC16_6; +input [`DWIDTH-1:0] matrixC16_7; +input [`DWIDTH-1:0] matrixC16_8; +input [`DWIDTH-1:0] matrixC16_9; +input [`DWIDTH-1:0] matrixC16_10; +input [`DWIDTH-1:0] matrixC16_11; +input [`DWIDTH-1:0] matrixC16_12; +input [`DWIDTH-1:0] matrixC16_13; +input [`DWIDTH-1:0] matrixC16_14; +input [`DWIDTH-1:0] matrixC16_15; +input [`DWIDTH-1:0] matrixC16_16; +input [`DWIDTH-1:0] matrixC16_17; +input [`DWIDTH-1:0] matrixC16_18; +input [`DWIDTH-1:0] matrixC16_19; +input [`DWIDTH-1:0] matrixC17_0; +input [`DWIDTH-1:0] matrixC17_1; +input [`DWIDTH-1:0] matrixC17_2; +input [`DWIDTH-1:0] matrixC17_3; +input [`DWIDTH-1:0] matrixC17_4; +input [`DWIDTH-1:0] matrixC17_5; +input [`DWIDTH-1:0] matrixC17_6; +input [`DWIDTH-1:0] matrixC17_7; +input [`DWIDTH-1:0] matrixC17_8; +input [`DWIDTH-1:0] matrixC17_9; +input [`DWIDTH-1:0] matrixC17_10; +input [`DWIDTH-1:0] matrixC17_11; +input [`DWIDTH-1:0] matrixC17_12; +input [`DWIDTH-1:0] matrixC17_13; +input [`DWIDTH-1:0] matrixC17_14; +input [`DWIDTH-1:0] matrixC17_15; +input [`DWIDTH-1:0] matrixC17_16; +input [`DWIDTH-1:0] matrixC17_17; +input [`DWIDTH-1:0] matrixC17_18; +input [`DWIDTH-1:0] matrixC17_19; +input [`DWIDTH-1:0] matrixC18_0; +input [`DWIDTH-1:0] matrixC18_1; +input [`DWIDTH-1:0] matrixC18_2; +input [`DWIDTH-1:0] matrixC18_3; +input [`DWIDTH-1:0] matrixC18_4; +input [`DWIDTH-1:0] matrixC18_5; +input [`DWIDTH-1:0] matrixC18_6; +input [`DWIDTH-1:0] matrixC18_7; +input [`DWIDTH-1:0] matrixC18_8; +input [`DWIDTH-1:0] matrixC18_9; +input [`DWIDTH-1:0] matrixC18_10; +input [`DWIDTH-1:0] matrixC18_11; +input [`DWIDTH-1:0] matrixC18_12; +input [`DWIDTH-1:0] matrixC18_13; +input [`DWIDTH-1:0] matrixC18_14; +input [`DWIDTH-1:0] matrixC18_15; +input [`DWIDTH-1:0] matrixC18_16; +input [`DWIDTH-1:0] matrixC18_17; +input [`DWIDTH-1:0] matrixC18_18; +input [`DWIDTH-1:0] matrixC18_19; +input [`DWIDTH-1:0] matrixC19_0; +input [`DWIDTH-1:0] matrixC19_1; +input [`DWIDTH-1:0] matrixC19_2; +input [`DWIDTH-1:0] matrixC19_3; +input [`DWIDTH-1:0] matrixC19_4; +input [`DWIDTH-1:0] matrixC19_5; +input [`DWIDTH-1:0] matrixC19_6; +input [`DWIDTH-1:0] matrixC19_7; +input [`DWIDTH-1:0] matrixC19_8; +input [`DWIDTH-1:0] matrixC19_9; +input [`DWIDTH-1:0] matrixC19_10; +input [`DWIDTH-1:0] matrixC19_11; +input [`DWIDTH-1:0] matrixC19_12; +input [`DWIDTH-1:0] matrixC19_13; +input [`DWIDTH-1:0] matrixC19_14; +input [`DWIDTH-1:0] matrixC19_15; +input [`DWIDTH-1:0] matrixC19_16; +input [`DWIDTH-1:0] matrixC19_17; +input [`DWIDTH-1:0] matrixC19_18; +input [`DWIDTH-1:0] matrixC19_19; +wire row_latch_en; + + +////////////////////////////////////////////////////////////////////////// +// Logic to capture matrix C data from the PEs and shift it out +////////////////////////////////////////////////////////////////////////// +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + (a_loc+b_loc) * `BB_MAT_MUL_SIZE + 10 + `NUM_CYCLES_IN_MAC - 1)); +//Writing the line above to avoid multiplication: +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + ((a_loc+b_loc) << `LOG2_MAT_MUL_SIZE) + 10 + `NUM_CYCLES_IN_MAC - 1)); + +assign row_latch_en = + ((clk_cnt == 62 )); + +reg c_data_available; +reg [`AWIDTH-1:0] c_addr; +reg start_capturing_c_data; +integer counter; +reg [20*`DWIDTH-1:0] c_data_out; +reg [20*`DWIDTH-1:0] c_data_out_1; +reg [20*`DWIDTH-1:0] c_data_out_2; +reg [20*`DWIDTH-1:0] c_data_out_3; +reg [20*`DWIDTH-1:0] c_data_out_4; +reg [20*`DWIDTH-1:0] c_data_out_5; +reg [20*`DWIDTH-1:0] c_data_out_6; +reg [20*`DWIDTH-1:0] c_data_out_7; +reg [20*`DWIDTH-1:0] c_data_out_8; +reg [20*`DWIDTH-1:0] c_data_out_9; +reg [20*`DWIDTH-1:0] c_data_out_10; +reg [20*`DWIDTH-1:0] c_data_out_11; +reg [20*`DWIDTH-1:0] c_data_out_12; +reg [20*`DWIDTH-1:0] c_data_out_13; +reg [20*`DWIDTH-1:0] c_data_out_14; +reg [20*`DWIDTH-1:0] c_data_out_15; +reg [20*`DWIDTH-1:0] c_data_out_16; +reg [20*`DWIDTH-1:0] c_data_out_17; +reg [20*`DWIDTH-1:0] c_data_out_18; +reg [20*`DWIDTH-1:0] c_data_out_19; +wire condition_to_start_shifting_output; +assign condition_to_start_shifting_output = + row_latch_en ; + + +//For larger matmuls, this logic will have more entries in the case statement +always @(posedge clk) begin + if (reset | ~start_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c + address_stride_c; + c_data_out <= 0; + counter <= 0; + + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + c_data_out_4 <= 0; + c_data_out_5 <= 0; + c_data_out_6 <= 0; + c_data_out_7 <= 0; + c_data_out_8 <= 0; + c_data_out_9 <= 0; + c_data_out_10 <= 0; + c_data_out_11 <= 0; + c_data_out_12 <= 0; + c_data_out_13 <= 0; + c_data_out_14 <= 0; + c_data_out_15 <= 0; + c_data_out_16 <= 0; + c_data_out_17 <= 0; + c_data_out_18 <= 0; + c_data_out_19 <= 0; + end else if (condition_to_start_shifting_output) begin + start_capturing_c_data <= 1'b1; + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + c_data_out <= {matrixC19_19, matrixC18_19, matrixC17_19, matrixC16_19, matrixC15_19, matrixC14_19, matrixC13_19, matrixC12_19, matrixC11_19, matrixC10_19, matrixC9_19, matrixC8_19, matrixC7_19, matrixC6_19, matrixC5_19, matrixC4_19, matrixC3_19, matrixC2_19, matrixC1_19, matrixC0_19}; + c_data_out_1 <= {matrixC19_18, matrixC18_18, matrixC17_18, matrixC16_18, matrixC15_18, matrixC14_18, matrixC13_18, matrixC12_18, matrixC11_18, matrixC10_18, matrixC9_18, matrixC8_18, matrixC7_18, matrixC6_18, matrixC5_18, matrixC4_18, matrixC3_18, matrixC2_18, matrixC1_18, matrixC0_18}; + c_data_out_2 <= {matrixC19_17, matrixC18_17, matrixC17_17, matrixC16_17, matrixC15_17, matrixC14_17, matrixC13_17, matrixC12_17, matrixC11_17, matrixC10_17, matrixC9_17, matrixC8_17, matrixC7_17, matrixC6_17, matrixC5_17, matrixC4_17, matrixC3_17, matrixC2_17, matrixC1_17, matrixC0_17}; + c_data_out_3 <= {matrixC19_16, matrixC18_16, matrixC17_16, matrixC16_16, matrixC15_16, matrixC14_16, matrixC13_16, matrixC12_16, matrixC11_16, matrixC10_16, matrixC9_16, matrixC8_16, matrixC7_16, matrixC6_16, matrixC5_16, matrixC4_16, matrixC3_16, matrixC2_16, matrixC1_16, matrixC0_16}; + c_data_out_4 <= {matrixC19_15, matrixC18_15, matrixC17_15, matrixC16_15, matrixC15_15, matrixC14_15, matrixC13_15, matrixC12_15, matrixC11_15, matrixC10_15, matrixC9_15, matrixC8_15, matrixC7_15, matrixC6_15, matrixC5_15, matrixC4_15, matrixC3_15, matrixC2_15, matrixC1_15, matrixC0_15}; + c_data_out_5 <= {matrixC19_14, matrixC18_14, matrixC17_14, matrixC16_14, matrixC15_14, matrixC14_14, matrixC13_14, matrixC12_14, matrixC11_14, matrixC10_14, matrixC9_14, matrixC8_14, matrixC7_14, matrixC6_14, matrixC5_14, matrixC4_14, matrixC3_14, matrixC2_14, matrixC1_14, matrixC0_14}; + c_data_out_6 <= {matrixC19_13, matrixC18_13, matrixC17_13, matrixC16_13, matrixC15_13, matrixC14_13, matrixC13_13, matrixC12_13, matrixC11_13, matrixC10_13, matrixC9_13, matrixC8_13, matrixC7_13, matrixC6_13, matrixC5_13, matrixC4_13, matrixC3_13, matrixC2_13, matrixC1_13, matrixC0_13}; + c_data_out_7 <= {matrixC19_12, matrixC18_12, matrixC17_12, matrixC16_12, matrixC15_12, matrixC14_12, matrixC13_12, matrixC12_12, matrixC11_12, matrixC10_12, matrixC9_12, matrixC8_12, matrixC7_12, matrixC6_12, matrixC5_12, matrixC4_12, matrixC3_12, matrixC2_12, matrixC1_12, matrixC0_12}; + c_data_out_8 <= {matrixC19_11, matrixC18_11, matrixC17_11, matrixC16_11, matrixC15_11, matrixC14_11, matrixC13_11, matrixC12_11, matrixC11_11, matrixC10_11, matrixC9_11, matrixC8_11, matrixC7_11, matrixC6_11, matrixC5_11, matrixC4_11, matrixC3_11, matrixC2_11, matrixC1_11, matrixC0_11}; + c_data_out_9 <= {matrixC19_10, matrixC18_10, matrixC17_10, matrixC16_10, matrixC15_10, matrixC14_10, matrixC13_10, matrixC12_10, matrixC11_10, matrixC10_10, matrixC9_10, matrixC8_10, matrixC7_10, matrixC6_10, matrixC5_10, matrixC4_10, matrixC3_10, matrixC2_10, matrixC1_10, matrixC0_10}; + c_data_out_10 <= {matrixC19_9, matrixC18_9, matrixC17_9, matrixC16_9, matrixC15_9, matrixC14_9, matrixC13_9, matrixC12_9, matrixC11_9, matrixC10_9, matrixC9_9, matrixC8_9, matrixC7_9, matrixC6_9, matrixC5_9, matrixC4_9, matrixC3_9, matrixC2_9, matrixC1_9, matrixC0_9}; + c_data_out_11 <= {matrixC19_8, matrixC18_8, matrixC17_8, matrixC16_8, matrixC15_8, matrixC14_8, matrixC13_8, matrixC12_8, matrixC11_8, matrixC10_8, matrixC9_8, matrixC8_8, matrixC7_8, matrixC6_8, matrixC5_8, matrixC4_8, matrixC3_8, matrixC2_8, matrixC1_8, matrixC0_8}; + c_data_out_12 <= {matrixC19_7, matrixC18_7, matrixC17_7, matrixC16_7, matrixC15_7, matrixC14_7, matrixC13_7, matrixC12_7, matrixC11_7, matrixC10_7, matrixC9_7, matrixC8_7, matrixC7_7, matrixC6_7, matrixC5_7, matrixC4_7, matrixC3_7, matrixC2_7, matrixC1_7, matrixC0_7}; + c_data_out_13 <= {matrixC19_6, matrixC18_6, matrixC17_6, matrixC16_6, matrixC15_6, matrixC14_6, matrixC13_6, matrixC12_6, matrixC11_6, matrixC10_6, matrixC9_6, matrixC8_6, matrixC7_6, matrixC6_6, matrixC5_6, matrixC4_6, matrixC3_6, matrixC2_6, matrixC1_6, matrixC0_6}; + c_data_out_14 <= {matrixC19_5, matrixC18_5, matrixC17_5, matrixC16_5, matrixC15_5, matrixC14_5, matrixC13_5, matrixC12_5, matrixC11_5, matrixC10_5, matrixC9_5, matrixC8_5, matrixC7_5, matrixC6_5, matrixC5_5, matrixC4_5, matrixC3_5, matrixC2_5, matrixC1_5, matrixC0_5}; + c_data_out_15 <= {matrixC19_4, matrixC18_4, matrixC17_4, matrixC16_4, matrixC15_4, matrixC14_4, matrixC13_4, matrixC12_4, matrixC11_4, matrixC10_4, matrixC9_4, matrixC8_4, matrixC7_4, matrixC6_4, matrixC5_4, matrixC4_4, matrixC3_4, matrixC2_4, matrixC1_4, matrixC0_4}; + c_data_out_16 <= {matrixC19_3, matrixC18_3, matrixC17_3, matrixC16_3, matrixC15_3, matrixC14_3, matrixC13_3, matrixC12_3, matrixC11_3, matrixC10_3, matrixC9_3, matrixC8_3, matrixC7_3, matrixC6_3, matrixC5_3, matrixC4_3, matrixC3_3, matrixC2_3, matrixC1_3, matrixC0_3}; + c_data_out_17 <= {matrixC19_2, matrixC18_2, matrixC17_2, matrixC16_2, matrixC15_2, matrixC14_2, matrixC13_2, matrixC12_2, matrixC11_2, matrixC10_2, matrixC9_2, matrixC8_2, matrixC7_2, matrixC6_2, matrixC5_2, matrixC4_2, matrixC3_2, matrixC2_2, matrixC1_2, matrixC0_2}; + c_data_out_18 <= {matrixC19_1, matrixC18_1, matrixC17_1, matrixC16_1, matrixC15_1, matrixC14_1, matrixC13_1, matrixC12_1, matrixC11_1, matrixC10_1, matrixC9_1, matrixC8_1, matrixC7_1, matrixC6_1, matrixC5_1, matrixC4_1, matrixC3_1, matrixC2_1, matrixC1_1, matrixC0_1}; + c_data_out_19 <= {matrixC19_0, matrixC18_0, matrixC17_0, matrixC16_0, matrixC15_0, matrixC14_0, matrixC13_0, matrixC12_0, matrixC11_0, matrixC10_0, matrixC9_0, matrixC8_0, matrixC7_0, matrixC6_0, matrixC5_0, matrixC4_0, matrixC3_0, matrixC2_0, matrixC1_0, matrixC0_0}; + + counter <= counter + 1; + end else if (done_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c + address_stride_c; + c_data_out <= 0; + + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + c_data_out_4 <= 0; + c_data_out_5 <= 0; + c_data_out_6 <= 0; + c_data_out_7 <= 0; + c_data_out_8 <= 0; + c_data_out_9 <= 0; + c_data_out_10 <= 0; + c_data_out_11 <= 0; + c_data_out_12 <= 0; + c_data_out_13 <= 0; + c_data_out_14 <= 0; + c_data_out_15 <= 0; + c_data_out_16 <= 0; + c_data_out_17 <= 0; + c_data_out_18 <= 0; + c_data_out_19 <= 0; + end + else if (counter >= `MAT_MUL_SIZE) begin + c_data_out <= c_data_out_1; + c_addr <= c_addr - address_stride_c; + + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_out_4; + c_data_out_4 <= c_data_out_5; + c_data_out_5 <= c_data_out_6; + c_data_out_6 <= c_data_out_7; + c_data_out_7 <= c_data_out_8; + c_data_out_8 <= c_data_out_9; + c_data_out_9 <= c_data_out_10; + c_data_out_10 <= c_data_out_11; + c_data_out_11 <= c_data_out_12; + c_data_out_12 <= c_data_out_13; + c_data_out_13 <= c_data_out_14; + c_data_out_14 <= c_data_out_15; + c_data_out_15 <= c_data_out_16; + c_data_out_16 <= c_data_out_17; + c_data_out_17 <= c_data_out_18; + c_data_out_18 <= c_data_out_19; + c_data_out_19 <= c_data_in; + end + else if (start_capturing_c_data) begin + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + counter <= counter + 1; + c_data_out <= c_data_out_1; + + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_out_4; + c_data_out_4 <= c_data_out_5; + c_data_out_5 <= c_data_out_6; + c_data_out_6 <= c_data_out_7; + c_data_out_7 <= c_data_out_8; + c_data_out_8 <= c_data_out_9; + c_data_out_9 <= c_data_out_10; + c_data_out_10 <= c_data_out_11; + c_data_out_11 <= c_data_out_12; + c_data_out_12 <= c_data_out_13; + c_data_out_13 <= c_data_out_14; + c_data_out_14 <= c_data_out_15; + c_data_out_15 <= c_data_out_16; + c_data_out_16 <= c_data_out_17; + c_data_out_17 <= c_data_out_18; + c_data_out_18 <= c_data_out_19; + c_data_out_19 <= c_data_in; + end +end + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolic data setup +////////////////////////////////////////////////////////////////////////// +module systolic_data_setup( +clk, +reset, +start_mat_mul, +a_addr, +b_addr, +address_mat_a, +address_mat_b, +address_stride_a, +address_stride_b, +a_data, +b_data, +clk_cnt, +a0_data, +b0_data, +a1_data_delayed_1, +b1_data_delayed_1, +a2_data_delayed_2, +b2_data_delayed_2, +a3_data_delayed_3, +b3_data_delayed_3, +a4_data_delayed_4, +b4_data_delayed_4, +a5_data_delayed_5, +b5_data_delayed_5, +a6_data_delayed_6, +b6_data_delayed_6, +a7_data_delayed_7, +b7_data_delayed_7, +a8_data_delayed_8, +b8_data_delayed_8, +a9_data_delayed_9, +b9_data_delayed_9, +a10_data_delayed_10, +b10_data_delayed_10, +a11_data_delayed_11, +b11_data_delayed_11, +a12_data_delayed_12, +b12_data_delayed_12, +a13_data_delayed_13, +b13_data_delayed_13, +a14_data_delayed_14, +b14_data_delayed_14, +a15_data_delayed_15, +b15_data_delayed_15, +a16_data_delayed_16, +b16_data_delayed_16, +a17_data_delayed_17, +b17_data_delayed_17, +a18_data_delayed_18, +b18_data_delayed_18, +a19_data_delayed_19, +b19_data_delayed_19, + +validity_mask_a_rows, +validity_mask_a_cols, +validity_mask_b_rows, +validity_mask_b_cols, + +a_loc, +b_loc +); + +input clk; +input reset; +input start_mat_mul; +output [`AWIDTH-1:0] a_addr; +output [`AWIDTH-1:0] b_addr; +input [`AWIDTH-1:0] address_mat_a; +input [`AWIDTH-1:0] address_mat_b; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; +input [7:0] clk_cnt; +output [`DWIDTH-1:0] a0_data; +output [`DWIDTH-1:0] b0_data; +output [`DWIDTH-1:0] a1_data_delayed_1; +output [`DWIDTH-1:0] b1_data_delayed_1; +output [`DWIDTH-1:0] a2_data_delayed_2; +output [`DWIDTH-1:0] b2_data_delayed_2; +output [`DWIDTH-1:0] a3_data_delayed_3; +output [`DWIDTH-1:0] b3_data_delayed_3; +output [`DWIDTH-1:0] a4_data_delayed_4; +output [`DWIDTH-1:0] b4_data_delayed_4; +output [`DWIDTH-1:0] a5_data_delayed_5; +output [`DWIDTH-1:0] b5_data_delayed_5; +output [`DWIDTH-1:0] a6_data_delayed_6; +output [`DWIDTH-1:0] b6_data_delayed_6; +output [`DWIDTH-1:0] a7_data_delayed_7; +output [`DWIDTH-1:0] b7_data_delayed_7; +output [`DWIDTH-1:0] a8_data_delayed_8; +output [`DWIDTH-1:0] b8_data_delayed_8; +output [`DWIDTH-1:0] a9_data_delayed_9; +output [`DWIDTH-1:0] b9_data_delayed_9; +output [`DWIDTH-1:0] a10_data_delayed_10; +output [`DWIDTH-1:0] b10_data_delayed_10; +output [`DWIDTH-1:0] a11_data_delayed_11; +output [`DWIDTH-1:0] b11_data_delayed_11; +output [`DWIDTH-1:0] a12_data_delayed_12; +output [`DWIDTH-1:0] b12_data_delayed_12; +output [`DWIDTH-1:0] a13_data_delayed_13; +output [`DWIDTH-1:0] b13_data_delayed_13; +output [`DWIDTH-1:0] a14_data_delayed_14; +output [`DWIDTH-1:0] b14_data_delayed_14; +output [`DWIDTH-1:0] a15_data_delayed_15; +output [`DWIDTH-1:0] b15_data_delayed_15; +output [`DWIDTH-1:0] a16_data_delayed_16; +output [`DWIDTH-1:0] b16_data_delayed_16; +output [`DWIDTH-1:0] a17_data_delayed_17; +output [`DWIDTH-1:0] b17_data_delayed_17; +output [`DWIDTH-1:0] a18_data_delayed_18; +output [`DWIDTH-1:0] b18_data_delayed_18; +output [`DWIDTH-1:0] a19_data_delayed_19; +output [`DWIDTH-1:0] b19_data_delayed_19; + +input [`MASK_WIDTH-1:0] validity_mask_a_rows; +input [`MASK_WIDTH-1:0] validity_mask_a_cols; +input [`MASK_WIDTH-1:0] validity_mask_b_rows; +input [`MASK_WIDTH-1:0] validity_mask_b_cols; + +input [7:0] a_loc; +input [7:0] b_loc; +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] a16_data; +wire [`DWIDTH-1:0] a17_data; +wire [`DWIDTH-1:0] a18_data; +wire [`DWIDTH-1:0] a19_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; +wire [`DWIDTH-1:0] b16_data; +wire [`DWIDTH-1:0] b17_data; +wire [`DWIDTH-1:0] b18_data; +wire [`DWIDTH-1:0] b19_data; + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM A +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] a_addr; +reg a_mem_access; //flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin + //(clk_cnt >= a_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + + if (reset || ~start_mat_mul || (clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)+20)) begin + + a_addr <= address_mat_a-address_stride_a; + + a_mem_access <= 0; + end + //else if ((clk_cnt >= a_loc*`MAT_MUL_SIZE) && (clk_cnt < a_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + + else if ((clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (a_loc<<`LOG2_MAT_MUL_SIZE)+20)) begin + + a_addr <= a_addr + address_stride_a; + + a_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM A +////////////////////////////////////////////////////////////////////////// +reg [7:0] a_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + a_mem_access_counter <= 0; + end + else if (a_mem_access == 1) begin + a_mem_access_counter <= a_mem_access_counter + 1; + end + else begin + a_mem_access_counter <= 0; + end +end + +wire a_data_valid; //flag that tells whether the data from memory is valid +assign a_data_valid = + ((validity_mask_a_cols[0]==1'b0 && a_mem_access_counter==1) || + (validity_mask_a_cols[1]==1'b0 && a_mem_access_counter==2) || + (validity_mask_a_cols[2]==1'b0 && a_mem_access_counter==3) || + (validity_mask_a_cols[3]==1'b0 && a_mem_access_counter==4) || + (validity_mask_a_cols[4]==1'b0 && a_mem_access_counter==5) || + (validity_mask_a_cols[5]==1'b0 && a_mem_access_counter==6) || + (validity_mask_a_cols[6]==1'b0 && a_mem_access_counter==7) || + (validity_mask_a_cols[7]==1'b0 && a_mem_access_counter==8) || + (validity_mask_a_cols[8]==1'b0 && a_mem_access_counter==9) || + (validity_mask_a_cols[9]==1'b0 && a_mem_access_counter==10) || + (validity_mask_a_cols[10]==1'b0 && a_mem_access_counter==11) || + (validity_mask_a_cols[11]==1'b0 && a_mem_access_counter==12) || + (validity_mask_a_cols[12]==1'b0 && a_mem_access_counter==13) || + (validity_mask_a_cols[13]==1'b0 && a_mem_access_counter==14) || + (validity_mask_a_cols[14]==1'b0 && a_mem_access_counter==15) || + (validity_mask_a_cols[15]==1'b0 && a_mem_access_counter==16) || + (validity_mask_a_cols[16]==1'b0 && a_mem_access_counter==17) || + (validity_mask_a_cols[17]==1'b0 && a_mem_access_counter==18) || + (validity_mask_a_cols[18]==1'b0 && a_mem_access_counter==19) || + (validity_mask_a_cols[19]==1'b0 && a_mem_access_counter==20)) ? + + 1'b0 : (a_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM A (systolic data setup) +////////////////////////////////////////////////////////////////////////// +assign a0_data = a_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[0]}}; +assign a1_data = a_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[1]}}; +assign a2_data = a_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[2]}}; +assign a3_data = a_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[3]}}; +assign a4_data = a_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[4]}}; +assign a5_data = a_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[5]}}; +assign a6_data = a_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[6]}}; +assign a7_data = a_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[7]}}; +assign a8_data = a_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[8]}}; +assign a9_data = a_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[9]}}; +assign a10_data = a_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[10]}}; +assign a11_data = a_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[11]}}; +assign a12_data = a_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[12]}}; +assign a13_data = a_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[13]}}; +assign a14_data = a_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[14]}}; +assign a15_data = a_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[15]}}; +assign a16_data = a_data[17*`DWIDTH-1:16*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[16]}}; +assign a17_data = a_data[18*`DWIDTH-1:17*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[17]}}; +assign a18_data = a_data[19*`DWIDTH-1:18*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[18]}}; +assign a19_data = a_data[20*`DWIDTH-1:19*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[19]}}; + +reg [`DWIDTH-1:0] a1_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_1; +reg [`DWIDTH-1:0] a3_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_1; +reg [`DWIDTH-1:0] a4_data_delayed_2; +reg [`DWIDTH-1:0] a4_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_1; +reg [`DWIDTH-1:0] a5_data_delayed_2; +reg [`DWIDTH-1:0] a5_data_delayed_3; +reg [`DWIDTH-1:0] a5_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_1; +reg [`DWIDTH-1:0] a6_data_delayed_2; +reg [`DWIDTH-1:0] a6_data_delayed_3; +reg [`DWIDTH-1:0] a6_data_delayed_4; +reg [`DWIDTH-1:0] a6_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_1; +reg [`DWIDTH-1:0] a7_data_delayed_2; +reg [`DWIDTH-1:0] a7_data_delayed_3; +reg [`DWIDTH-1:0] a7_data_delayed_4; +reg [`DWIDTH-1:0] a7_data_delayed_5; +reg [`DWIDTH-1:0] a7_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_1; +reg [`DWIDTH-1:0] a8_data_delayed_2; +reg [`DWIDTH-1:0] a8_data_delayed_3; +reg [`DWIDTH-1:0] a8_data_delayed_4; +reg [`DWIDTH-1:0] a8_data_delayed_5; +reg [`DWIDTH-1:0] a8_data_delayed_6; +reg [`DWIDTH-1:0] a8_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_1; +reg [`DWIDTH-1:0] a9_data_delayed_2; +reg [`DWIDTH-1:0] a9_data_delayed_3; +reg [`DWIDTH-1:0] a9_data_delayed_4; +reg [`DWIDTH-1:0] a9_data_delayed_5; +reg [`DWIDTH-1:0] a9_data_delayed_6; +reg [`DWIDTH-1:0] a9_data_delayed_7; +reg [`DWIDTH-1:0] a9_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_1; +reg [`DWIDTH-1:0] a10_data_delayed_2; +reg [`DWIDTH-1:0] a10_data_delayed_3; +reg [`DWIDTH-1:0] a10_data_delayed_4; +reg [`DWIDTH-1:0] a10_data_delayed_5; +reg [`DWIDTH-1:0] a10_data_delayed_6; +reg [`DWIDTH-1:0] a10_data_delayed_7; +reg [`DWIDTH-1:0] a10_data_delayed_8; +reg [`DWIDTH-1:0] a10_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_1; +reg [`DWIDTH-1:0] a11_data_delayed_2; +reg [`DWIDTH-1:0] a11_data_delayed_3; +reg [`DWIDTH-1:0] a11_data_delayed_4; +reg [`DWIDTH-1:0] a11_data_delayed_5; +reg [`DWIDTH-1:0] a11_data_delayed_6; +reg [`DWIDTH-1:0] a11_data_delayed_7; +reg [`DWIDTH-1:0] a11_data_delayed_8; +reg [`DWIDTH-1:0] a11_data_delayed_9; +reg [`DWIDTH-1:0] a11_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_1; +reg [`DWIDTH-1:0] a12_data_delayed_2; +reg [`DWIDTH-1:0] a12_data_delayed_3; +reg [`DWIDTH-1:0] a12_data_delayed_4; +reg [`DWIDTH-1:0] a12_data_delayed_5; +reg [`DWIDTH-1:0] a12_data_delayed_6; +reg [`DWIDTH-1:0] a12_data_delayed_7; +reg [`DWIDTH-1:0] a12_data_delayed_8; +reg [`DWIDTH-1:0] a12_data_delayed_9; +reg [`DWIDTH-1:0] a12_data_delayed_10; +reg [`DWIDTH-1:0] a12_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_1; +reg [`DWIDTH-1:0] a13_data_delayed_2; +reg [`DWIDTH-1:0] a13_data_delayed_3; +reg [`DWIDTH-1:0] a13_data_delayed_4; +reg [`DWIDTH-1:0] a13_data_delayed_5; +reg [`DWIDTH-1:0] a13_data_delayed_6; +reg [`DWIDTH-1:0] a13_data_delayed_7; +reg [`DWIDTH-1:0] a13_data_delayed_8; +reg [`DWIDTH-1:0] a13_data_delayed_9; +reg [`DWIDTH-1:0] a13_data_delayed_10; +reg [`DWIDTH-1:0] a13_data_delayed_11; +reg [`DWIDTH-1:0] a13_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_1; +reg [`DWIDTH-1:0] a14_data_delayed_2; +reg [`DWIDTH-1:0] a14_data_delayed_3; +reg [`DWIDTH-1:0] a14_data_delayed_4; +reg [`DWIDTH-1:0] a14_data_delayed_5; +reg [`DWIDTH-1:0] a14_data_delayed_6; +reg [`DWIDTH-1:0] a14_data_delayed_7; +reg [`DWIDTH-1:0] a14_data_delayed_8; +reg [`DWIDTH-1:0] a14_data_delayed_9; +reg [`DWIDTH-1:0] a14_data_delayed_10; +reg [`DWIDTH-1:0] a14_data_delayed_11; +reg [`DWIDTH-1:0] a14_data_delayed_12; +reg [`DWIDTH-1:0] a14_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_1; +reg [`DWIDTH-1:0] a15_data_delayed_2; +reg [`DWIDTH-1:0] a15_data_delayed_3; +reg [`DWIDTH-1:0] a15_data_delayed_4; +reg [`DWIDTH-1:0] a15_data_delayed_5; +reg [`DWIDTH-1:0] a15_data_delayed_6; +reg [`DWIDTH-1:0] a15_data_delayed_7; +reg [`DWIDTH-1:0] a15_data_delayed_8; +reg [`DWIDTH-1:0] a15_data_delayed_9; +reg [`DWIDTH-1:0] a15_data_delayed_10; +reg [`DWIDTH-1:0] a15_data_delayed_11; +reg [`DWIDTH-1:0] a15_data_delayed_12; +reg [`DWIDTH-1:0] a15_data_delayed_13; +reg [`DWIDTH-1:0] a15_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_15; +reg [`DWIDTH-1:0] a16_data_delayed_1; +reg [`DWIDTH-1:0] a16_data_delayed_2; +reg [`DWIDTH-1:0] a16_data_delayed_3; +reg [`DWIDTH-1:0] a16_data_delayed_4; +reg [`DWIDTH-1:0] a16_data_delayed_5; +reg [`DWIDTH-1:0] a16_data_delayed_6; +reg [`DWIDTH-1:0] a16_data_delayed_7; +reg [`DWIDTH-1:0] a16_data_delayed_8; +reg [`DWIDTH-1:0] a16_data_delayed_9; +reg [`DWIDTH-1:0] a16_data_delayed_10; +reg [`DWIDTH-1:0] a16_data_delayed_11; +reg [`DWIDTH-1:0] a16_data_delayed_12; +reg [`DWIDTH-1:0] a16_data_delayed_13; +reg [`DWIDTH-1:0] a16_data_delayed_14; +reg [`DWIDTH-1:0] a16_data_delayed_15; +reg [`DWIDTH-1:0] a16_data_delayed_16; +reg [`DWIDTH-1:0] a17_data_delayed_1; +reg [`DWIDTH-1:0] a17_data_delayed_2; +reg [`DWIDTH-1:0] a17_data_delayed_3; +reg [`DWIDTH-1:0] a17_data_delayed_4; +reg [`DWIDTH-1:0] a17_data_delayed_5; +reg [`DWIDTH-1:0] a17_data_delayed_6; +reg [`DWIDTH-1:0] a17_data_delayed_7; +reg [`DWIDTH-1:0] a17_data_delayed_8; +reg [`DWIDTH-1:0] a17_data_delayed_9; +reg [`DWIDTH-1:0] a17_data_delayed_10; +reg [`DWIDTH-1:0] a17_data_delayed_11; +reg [`DWIDTH-1:0] a17_data_delayed_12; +reg [`DWIDTH-1:0] a17_data_delayed_13; +reg [`DWIDTH-1:0] a17_data_delayed_14; +reg [`DWIDTH-1:0] a17_data_delayed_15; +reg [`DWIDTH-1:0] a17_data_delayed_16; +reg [`DWIDTH-1:0] a17_data_delayed_17; +reg [`DWIDTH-1:0] a18_data_delayed_1; +reg [`DWIDTH-1:0] a18_data_delayed_2; +reg [`DWIDTH-1:0] a18_data_delayed_3; +reg [`DWIDTH-1:0] a18_data_delayed_4; +reg [`DWIDTH-1:0] a18_data_delayed_5; +reg [`DWIDTH-1:0] a18_data_delayed_6; +reg [`DWIDTH-1:0] a18_data_delayed_7; +reg [`DWIDTH-1:0] a18_data_delayed_8; +reg [`DWIDTH-1:0] a18_data_delayed_9; +reg [`DWIDTH-1:0] a18_data_delayed_10; +reg [`DWIDTH-1:0] a18_data_delayed_11; +reg [`DWIDTH-1:0] a18_data_delayed_12; +reg [`DWIDTH-1:0] a18_data_delayed_13; +reg [`DWIDTH-1:0] a18_data_delayed_14; +reg [`DWIDTH-1:0] a18_data_delayed_15; +reg [`DWIDTH-1:0] a18_data_delayed_16; +reg [`DWIDTH-1:0] a18_data_delayed_17; +reg [`DWIDTH-1:0] a18_data_delayed_18; +reg [`DWIDTH-1:0] a19_data_delayed_1; +reg [`DWIDTH-1:0] a19_data_delayed_2; +reg [`DWIDTH-1:0] a19_data_delayed_3; +reg [`DWIDTH-1:0] a19_data_delayed_4; +reg [`DWIDTH-1:0] a19_data_delayed_5; +reg [`DWIDTH-1:0] a19_data_delayed_6; +reg [`DWIDTH-1:0] a19_data_delayed_7; +reg [`DWIDTH-1:0] a19_data_delayed_8; +reg [`DWIDTH-1:0] a19_data_delayed_9; +reg [`DWIDTH-1:0] a19_data_delayed_10; +reg [`DWIDTH-1:0] a19_data_delayed_11; +reg [`DWIDTH-1:0] a19_data_delayed_12; +reg [`DWIDTH-1:0] a19_data_delayed_13; +reg [`DWIDTH-1:0] a19_data_delayed_14; +reg [`DWIDTH-1:0] a19_data_delayed_15; +reg [`DWIDTH-1:0] a19_data_delayed_16; +reg [`DWIDTH-1:0] a19_data_delayed_17; +reg [`DWIDTH-1:0] a19_data_delayed_18; +reg [`DWIDTH-1:0] a19_data_delayed_19; + + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + a1_data_delayed_1 <= 0; + a2_data_delayed_1 <= 0; + a2_data_delayed_2 <= 0; + a3_data_delayed_1 <= 0; + a3_data_delayed_2 <= 0; + a3_data_delayed_3 <= 0; + a4_data_delayed_1 <= 0; + a4_data_delayed_2 <= 0; + a4_data_delayed_3 <= 0; + a4_data_delayed_4 <= 0; + a5_data_delayed_1 <= 0; + a5_data_delayed_2 <= 0; + a5_data_delayed_3 <= 0; + a5_data_delayed_4 <= 0; + a5_data_delayed_5 <= 0; + a6_data_delayed_1 <= 0; + a6_data_delayed_2 <= 0; + a6_data_delayed_3 <= 0; + a6_data_delayed_4 <= 0; + a6_data_delayed_5 <= 0; + a6_data_delayed_6 <= 0; + a7_data_delayed_1 <= 0; + a7_data_delayed_2 <= 0; + a7_data_delayed_3 <= 0; + a7_data_delayed_4 <= 0; + a7_data_delayed_5 <= 0; + a7_data_delayed_6 <= 0; + a7_data_delayed_7 <= 0; + a8_data_delayed_1 <= 0; + a8_data_delayed_2 <= 0; + a8_data_delayed_3 <= 0; + a8_data_delayed_4 <= 0; + a8_data_delayed_5 <= 0; + a8_data_delayed_6 <= 0; + a8_data_delayed_7 <= 0; + a8_data_delayed_8 <= 0; + a9_data_delayed_1 <= 0; + a9_data_delayed_2 <= 0; + a9_data_delayed_3 <= 0; + a9_data_delayed_4 <= 0; + a9_data_delayed_5 <= 0; + a9_data_delayed_6 <= 0; + a9_data_delayed_7 <= 0; + a9_data_delayed_8 <= 0; + a9_data_delayed_9 <= 0; + a10_data_delayed_1 <= 0; + a10_data_delayed_2 <= 0; + a10_data_delayed_3 <= 0; + a10_data_delayed_4 <= 0; + a10_data_delayed_5 <= 0; + a10_data_delayed_6 <= 0; + a10_data_delayed_7 <= 0; + a10_data_delayed_8 <= 0; + a10_data_delayed_9 <= 0; + a10_data_delayed_10 <= 0; + a11_data_delayed_1 <= 0; + a11_data_delayed_2 <= 0; + a11_data_delayed_3 <= 0; + a11_data_delayed_4 <= 0; + a11_data_delayed_5 <= 0; + a11_data_delayed_6 <= 0; + a11_data_delayed_7 <= 0; + a11_data_delayed_8 <= 0; + a11_data_delayed_9 <= 0; + a11_data_delayed_10 <= 0; + a11_data_delayed_11 <= 0; + a12_data_delayed_1 <= 0; + a12_data_delayed_2 <= 0; + a12_data_delayed_3 <= 0; + a12_data_delayed_4 <= 0; + a12_data_delayed_5 <= 0; + a12_data_delayed_6 <= 0; + a12_data_delayed_7 <= 0; + a12_data_delayed_8 <= 0; + a12_data_delayed_9 <= 0; + a12_data_delayed_10 <= 0; + a12_data_delayed_11 <= 0; + a12_data_delayed_12 <= 0; + a13_data_delayed_1 <= 0; + a13_data_delayed_2 <= 0; + a13_data_delayed_3 <= 0; + a13_data_delayed_4 <= 0; + a13_data_delayed_5 <= 0; + a13_data_delayed_6 <= 0; + a13_data_delayed_7 <= 0; + a13_data_delayed_8 <= 0; + a13_data_delayed_9 <= 0; + a13_data_delayed_10 <= 0; + a13_data_delayed_11 <= 0; + a13_data_delayed_12 <= 0; + a13_data_delayed_13 <= 0; + a14_data_delayed_1 <= 0; + a14_data_delayed_2 <= 0; + a14_data_delayed_3 <= 0; + a14_data_delayed_4 <= 0; + a14_data_delayed_5 <= 0; + a14_data_delayed_6 <= 0; + a14_data_delayed_7 <= 0; + a14_data_delayed_8 <= 0; + a14_data_delayed_9 <= 0; + a14_data_delayed_10 <= 0; + a14_data_delayed_11 <= 0; + a14_data_delayed_12 <= 0; + a14_data_delayed_13 <= 0; + a14_data_delayed_14 <= 0; + a15_data_delayed_1 <= 0; + a15_data_delayed_2 <= 0; + a15_data_delayed_3 <= 0; + a15_data_delayed_4 <= 0; + a15_data_delayed_5 <= 0; + a15_data_delayed_6 <= 0; + a15_data_delayed_7 <= 0; + a15_data_delayed_8 <= 0; + a15_data_delayed_9 <= 0; + a15_data_delayed_10 <= 0; + a15_data_delayed_11 <= 0; + a15_data_delayed_12 <= 0; + a15_data_delayed_13 <= 0; + a15_data_delayed_14 <= 0; + a15_data_delayed_15 <= 0; + a16_data_delayed_1 <= 0; + a16_data_delayed_2 <= 0; + a16_data_delayed_3 <= 0; + a16_data_delayed_4 <= 0; + a16_data_delayed_5 <= 0; + a16_data_delayed_6 <= 0; + a16_data_delayed_7 <= 0; + a16_data_delayed_8 <= 0; + a16_data_delayed_9 <= 0; + a16_data_delayed_10 <= 0; + a16_data_delayed_11 <= 0; + a16_data_delayed_12 <= 0; + a16_data_delayed_13 <= 0; + a16_data_delayed_14 <= 0; + a16_data_delayed_15 <= 0; + a16_data_delayed_16 <= 0; + a17_data_delayed_1 <= 0; + a17_data_delayed_2 <= 0; + a17_data_delayed_3 <= 0; + a17_data_delayed_4 <= 0; + a17_data_delayed_5 <= 0; + a17_data_delayed_6 <= 0; + a17_data_delayed_7 <= 0; + a17_data_delayed_8 <= 0; + a17_data_delayed_9 <= 0; + a17_data_delayed_10 <= 0; + a17_data_delayed_11 <= 0; + a17_data_delayed_12 <= 0; + a17_data_delayed_13 <= 0; + a17_data_delayed_14 <= 0; + a17_data_delayed_15 <= 0; + a17_data_delayed_16 <= 0; + a17_data_delayed_17 <= 0; + a18_data_delayed_1 <= 0; + a18_data_delayed_2 <= 0; + a18_data_delayed_3 <= 0; + a18_data_delayed_4 <= 0; + a18_data_delayed_5 <= 0; + a18_data_delayed_6 <= 0; + a18_data_delayed_7 <= 0; + a18_data_delayed_8 <= 0; + a18_data_delayed_9 <= 0; + a18_data_delayed_10 <= 0; + a18_data_delayed_11 <= 0; + a18_data_delayed_12 <= 0; + a18_data_delayed_13 <= 0; + a18_data_delayed_14 <= 0; + a18_data_delayed_15 <= 0; + a18_data_delayed_16 <= 0; + a18_data_delayed_17 <= 0; + a18_data_delayed_18 <= 0; + a19_data_delayed_1 <= 0; + a19_data_delayed_2 <= 0; + a19_data_delayed_3 <= 0; + a19_data_delayed_4 <= 0; + a19_data_delayed_5 <= 0; + a19_data_delayed_6 <= 0; + a19_data_delayed_7 <= 0; + a19_data_delayed_8 <= 0; + a19_data_delayed_9 <= 0; + a19_data_delayed_10 <= 0; + a19_data_delayed_11 <= 0; + a19_data_delayed_12 <= 0; + a19_data_delayed_13 <= 0; + a19_data_delayed_14 <= 0; + a19_data_delayed_15 <= 0; + a19_data_delayed_16 <= 0; + a19_data_delayed_17 <= 0; + a19_data_delayed_18 <= 0; + a19_data_delayed_19 <= 0; + + end + else begin + a1_data_delayed_1 <= a1_data; + a2_data_delayed_1 <= a2_data; + a3_data_delayed_1 <= a3_data; + a4_data_delayed_1 <= a4_data; + a5_data_delayed_1 <= a5_data; + a6_data_delayed_1 <= a6_data; + a7_data_delayed_1 <= a7_data; + a8_data_delayed_1 <= a8_data; + a9_data_delayed_1 <= a9_data; + a10_data_delayed_1 <= a10_data; + a11_data_delayed_1 <= a11_data; + a12_data_delayed_1 <= a12_data; + a13_data_delayed_1 <= a13_data; + a14_data_delayed_1 <= a14_data; + a15_data_delayed_1 <= a15_data; + a16_data_delayed_1 <= a16_data; + a17_data_delayed_1 <= a17_data; + a18_data_delayed_1 <= a18_data; + a19_data_delayed_1 <= a19_data; + a2_data_delayed_2 <= a2_data_delayed_1; + a3_data_delayed_2 <= a3_data_delayed_1; + a3_data_delayed_3 <= a3_data_delayed_2; + a4_data_delayed_2 <= a4_data_delayed_1; + a4_data_delayed_3 <= a4_data_delayed_2; + a4_data_delayed_4 <= a4_data_delayed_3; + a5_data_delayed_2 <= a5_data_delayed_1; + a5_data_delayed_3 <= a5_data_delayed_2; + a5_data_delayed_4 <= a5_data_delayed_3; + a5_data_delayed_5 <= a5_data_delayed_4; + a6_data_delayed_2 <= a6_data_delayed_1; + a6_data_delayed_3 <= a6_data_delayed_2; + a6_data_delayed_4 <= a6_data_delayed_3; + a6_data_delayed_5 <= a6_data_delayed_4; + a6_data_delayed_6 <= a6_data_delayed_5; + a7_data_delayed_2 <= a7_data_delayed_1; + a7_data_delayed_3 <= a7_data_delayed_2; + a7_data_delayed_4 <= a7_data_delayed_3; + a7_data_delayed_5 <= a7_data_delayed_4; + a7_data_delayed_6 <= a7_data_delayed_5; + a7_data_delayed_7 <= a7_data_delayed_6; + a8_data_delayed_2 <= a8_data_delayed_1; + a8_data_delayed_3 <= a8_data_delayed_2; + a8_data_delayed_4 <= a8_data_delayed_3; + a8_data_delayed_5 <= a8_data_delayed_4; + a8_data_delayed_6 <= a8_data_delayed_5; + a8_data_delayed_7 <= a8_data_delayed_6; + a8_data_delayed_8 <= a8_data_delayed_7; + a9_data_delayed_2 <= a9_data_delayed_1; + a9_data_delayed_3 <= a9_data_delayed_2; + a9_data_delayed_4 <= a9_data_delayed_3; + a9_data_delayed_5 <= a9_data_delayed_4; + a9_data_delayed_6 <= a9_data_delayed_5; + a9_data_delayed_7 <= a9_data_delayed_6; + a9_data_delayed_8 <= a9_data_delayed_7; + a9_data_delayed_9 <= a9_data_delayed_8; + a10_data_delayed_2 <= a10_data_delayed_1; + a10_data_delayed_3 <= a10_data_delayed_2; + a10_data_delayed_4 <= a10_data_delayed_3; + a10_data_delayed_5 <= a10_data_delayed_4; + a10_data_delayed_6 <= a10_data_delayed_5; + a10_data_delayed_7 <= a10_data_delayed_6; + a10_data_delayed_8 <= a10_data_delayed_7; + a10_data_delayed_9 <= a10_data_delayed_8; + a10_data_delayed_10 <= a10_data_delayed_9; + a11_data_delayed_2 <= a11_data_delayed_1; + a11_data_delayed_3 <= a11_data_delayed_2; + a11_data_delayed_4 <= a11_data_delayed_3; + a11_data_delayed_5 <= a11_data_delayed_4; + a11_data_delayed_6 <= a11_data_delayed_5; + a11_data_delayed_7 <= a11_data_delayed_6; + a11_data_delayed_8 <= a11_data_delayed_7; + a11_data_delayed_9 <= a11_data_delayed_8; + a11_data_delayed_10 <= a11_data_delayed_9; + a11_data_delayed_11 <= a11_data_delayed_10; + a12_data_delayed_2 <= a12_data_delayed_1; + a12_data_delayed_3 <= a12_data_delayed_2; + a12_data_delayed_4 <= a12_data_delayed_3; + a12_data_delayed_5 <= a12_data_delayed_4; + a12_data_delayed_6 <= a12_data_delayed_5; + a12_data_delayed_7 <= a12_data_delayed_6; + a12_data_delayed_8 <= a12_data_delayed_7; + a12_data_delayed_9 <= a12_data_delayed_8; + a12_data_delayed_10 <= a12_data_delayed_9; + a12_data_delayed_11 <= a12_data_delayed_10; + a12_data_delayed_12 <= a12_data_delayed_11; + a13_data_delayed_2 <= a13_data_delayed_1; + a13_data_delayed_3 <= a13_data_delayed_2; + a13_data_delayed_4 <= a13_data_delayed_3; + a13_data_delayed_5 <= a13_data_delayed_4; + a13_data_delayed_6 <= a13_data_delayed_5; + a13_data_delayed_7 <= a13_data_delayed_6; + a13_data_delayed_8 <= a13_data_delayed_7; + a13_data_delayed_9 <= a13_data_delayed_8; + a13_data_delayed_10 <= a13_data_delayed_9; + a13_data_delayed_11 <= a13_data_delayed_10; + a13_data_delayed_12 <= a13_data_delayed_11; + a13_data_delayed_13 <= a13_data_delayed_12; + a14_data_delayed_2 <= a14_data_delayed_1; + a14_data_delayed_3 <= a14_data_delayed_2; + a14_data_delayed_4 <= a14_data_delayed_3; + a14_data_delayed_5 <= a14_data_delayed_4; + a14_data_delayed_6 <= a14_data_delayed_5; + a14_data_delayed_7 <= a14_data_delayed_6; + a14_data_delayed_8 <= a14_data_delayed_7; + a14_data_delayed_9 <= a14_data_delayed_8; + a14_data_delayed_10 <= a14_data_delayed_9; + a14_data_delayed_11 <= a14_data_delayed_10; + a14_data_delayed_12 <= a14_data_delayed_11; + a14_data_delayed_13 <= a14_data_delayed_12; + a14_data_delayed_14 <= a14_data_delayed_13; + a15_data_delayed_2 <= a15_data_delayed_1; + a15_data_delayed_3 <= a15_data_delayed_2; + a15_data_delayed_4 <= a15_data_delayed_3; + a15_data_delayed_5 <= a15_data_delayed_4; + a15_data_delayed_6 <= a15_data_delayed_5; + a15_data_delayed_7 <= a15_data_delayed_6; + a15_data_delayed_8 <= a15_data_delayed_7; + a15_data_delayed_9 <= a15_data_delayed_8; + a15_data_delayed_10 <= a15_data_delayed_9; + a15_data_delayed_11 <= a15_data_delayed_10; + a15_data_delayed_12 <= a15_data_delayed_11; + a15_data_delayed_13 <= a15_data_delayed_12; + a15_data_delayed_14 <= a15_data_delayed_13; + a15_data_delayed_15 <= a15_data_delayed_14; + a16_data_delayed_2 <= a16_data_delayed_1; + a16_data_delayed_3 <= a16_data_delayed_2; + a16_data_delayed_4 <= a16_data_delayed_3; + a16_data_delayed_5 <= a16_data_delayed_4; + a16_data_delayed_6 <= a16_data_delayed_5; + a16_data_delayed_7 <= a16_data_delayed_6; + a16_data_delayed_8 <= a16_data_delayed_7; + a16_data_delayed_9 <= a16_data_delayed_8; + a16_data_delayed_10 <= a16_data_delayed_9; + a16_data_delayed_11 <= a16_data_delayed_10; + a16_data_delayed_12 <= a16_data_delayed_11; + a16_data_delayed_13 <= a16_data_delayed_12; + a16_data_delayed_14 <= a16_data_delayed_13; + a16_data_delayed_15 <= a16_data_delayed_14; + a16_data_delayed_16 <= a16_data_delayed_15; + a17_data_delayed_2 <= a17_data_delayed_1; + a17_data_delayed_3 <= a17_data_delayed_2; + a17_data_delayed_4 <= a17_data_delayed_3; + a17_data_delayed_5 <= a17_data_delayed_4; + a17_data_delayed_6 <= a17_data_delayed_5; + a17_data_delayed_7 <= a17_data_delayed_6; + a17_data_delayed_8 <= a17_data_delayed_7; + a17_data_delayed_9 <= a17_data_delayed_8; + a17_data_delayed_10 <= a17_data_delayed_9; + a17_data_delayed_11 <= a17_data_delayed_10; + a17_data_delayed_12 <= a17_data_delayed_11; + a17_data_delayed_13 <= a17_data_delayed_12; + a17_data_delayed_14 <= a17_data_delayed_13; + a17_data_delayed_15 <= a17_data_delayed_14; + a17_data_delayed_16 <= a17_data_delayed_15; + a17_data_delayed_17 <= a17_data_delayed_16; + a18_data_delayed_2 <= a18_data_delayed_1; + a18_data_delayed_3 <= a18_data_delayed_2; + a18_data_delayed_4 <= a18_data_delayed_3; + a18_data_delayed_5 <= a18_data_delayed_4; + a18_data_delayed_6 <= a18_data_delayed_5; + a18_data_delayed_7 <= a18_data_delayed_6; + a18_data_delayed_8 <= a18_data_delayed_7; + a18_data_delayed_9 <= a18_data_delayed_8; + a18_data_delayed_10 <= a18_data_delayed_9; + a18_data_delayed_11 <= a18_data_delayed_10; + a18_data_delayed_12 <= a18_data_delayed_11; + a18_data_delayed_13 <= a18_data_delayed_12; + a18_data_delayed_14 <= a18_data_delayed_13; + a18_data_delayed_15 <= a18_data_delayed_14; + a18_data_delayed_16 <= a18_data_delayed_15; + a18_data_delayed_17 <= a18_data_delayed_16; + a18_data_delayed_18 <= a18_data_delayed_17; + a19_data_delayed_2 <= a19_data_delayed_1; + a19_data_delayed_3 <= a19_data_delayed_2; + a19_data_delayed_4 <= a19_data_delayed_3; + a19_data_delayed_5 <= a19_data_delayed_4; + a19_data_delayed_6 <= a19_data_delayed_5; + a19_data_delayed_7 <= a19_data_delayed_6; + a19_data_delayed_8 <= a19_data_delayed_7; + a19_data_delayed_9 <= a19_data_delayed_8; + a19_data_delayed_10 <= a19_data_delayed_9; + a19_data_delayed_11 <= a19_data_delayed_10; + a19_data_delayed_12 <= a19_data_delayed_11; + a19_data_delayed_13 <= a19_data_delayed_12; + a19_data_delayed_14 <= a19_data_delayed_13; + a19_data_delayed_15 <= a19_data_delayed_14; + a19_data_delayed_16 <= a19_data_delayed_15; + a19_data_delayed_17 <= a19_data_delayed_16; + a19_data_delayed_18 <= a19_data_delayed_17; + a19_data_delayed_19 <= a19_data_delayed_18; + + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM B +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] b_addr; +reg b_mem_access; //flag that tells whether the matmul is trying to access memory or not +always @(posedge clk) begin + //else if (clk_cnt >= b_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + + if ((reset || ~start_mat_mul) || (clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)+20)) begin + + b_addr <= address_mat_b - address_stride_b; + + b_mem_access <= 0; + end + //else if ((clk_cnt >= b_loc*`MAT_MUL_SIZE) && (clk_cnt < b_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + + else if ((clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (b_loc<<`LOG2_MAT_MUL_SIZE)+20)) begin + + b_addr <= b_addr + address_stride_b; + + b_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM B +////////////////////////////////////////////////////////////////////////// +reg [7:0] b_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + b_mem_access_counter <= 0; + end + else if (b_mem_access == 1) begin + b_mem_access_counter <= b_mem_access_counter + 1; + end + else begin + b_mem_access_counter <= 0; + end +end + +wire b_data_valid; //flag that tells whether the data from memory is valid +assign b_data_valid = + ((validity_mask_b_rows[0]==1'b0 && b_mem_access_counter==1) || + (validity_mask_b_rows[1]==1'b0 && b_mem_access_counter==2) || + (validity_mask_b_rows[2]==1'b0 && b_mem_access_counter==3) || + (validity_mask_b_rows[3]==1'b0 && b_mem_access_counter==4) || + (validity_mask_b_rows[4]==1'b0 && b_mem_access_counter==5) || + (validity_mask_b_rows[5]==1'b0 && b_mem_access_counter==6) || + (validity_mask_b_rows[6]==1'b0 && b_mem_access_counter==7) || + (validity_mask_b_rows[7]==1'b0 && b_mem_access_counter==8) || + (validity_mask_b_rows[8]==1'b0 && b_mem_access_counter==9) || + (validity_mask_b_rows[9]==1'b0 && b_mem_access_counter==10) || + (validity_mask_b_rows[10]==1'b0 && b_mem_access_counter==11) || + (validity_mask_b_rows[11]==1'b0 && b_mem_access_counter==12) || + (validity_mask_b_rows[12]==1'b0 && b_mem_access_counter==13) || + (validity_mask_b_rows[13]==1'b0 && b_mem_access_counter==14) || + (validity_mask_b_rows[14]==1'b0 && b_mem_access_counter==15) || + (validity_mask_b_rows[15]==1'b0 && b_mem_access_counter==16) || + (validity_mask_b_rows[16]==1'b0 && b_mem_access_counter==17) || + (validity_mask_b_rows[17]==1'b0 && b_mem_access_counter==18) || + (validity_mask_b_rows[18]==1'b0 && b_mem_access_counter==19) || + (validity_mask_b_rows[19]==1'b0 && b_mem_access_counter==20)) ? + + 1'b0 : (b_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM B (systolic data setup) +////////////////////////////////////////////////////////////////////////// +assign b0_data = b_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[0]}}; +assign b1_data = b_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[1]}}; +assign b2_data = b_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[2]}}; +assign b3_data = b_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[3]}}; +assign b4_data = b_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[4]}}; +assign b5_data = b_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[5]}}; +assign b6_data = b_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[6]}}; +assign b7_data = b_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[7]}}; +assign b8_data = b_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[8]}}; +assign b9_data = b_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[9]}}; +assign b10_data = b_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[10]}}; +assign b11_data = b_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[11]}}; +assign b12_data = b_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[12]}}; +assign b13_data = b_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[13]}}; +assign b14_data = b_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[14]}}; +assign b15_data = b_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[15]}}; +assign b16_data = b_data[17*`DWIDTH-1:16*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[16]}}; +assign b17_data = b_data[18*`DWIDTH-1:17*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[17]}}; +assign b18_data = b_data[19*`DWIDTH-1:18*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[18]}}; +assign b19_data = b_data[20*`DWIDTH-1:19*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[19]}}; + +reg [`DWIDTH-1:0] b1_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_1; +reg [`DWIDTH-1:0] b3_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_1; +reg [`DWIDTH-1:0] b4_data_delayed_2; +reg [`DWIDTH-1:0] b4_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_1; +reg [`DWIDTH-1:0] b5_data_delayed_2; +reg [`DWIDTH-1:0] b5_data_delayed_3; +reg [`DWIDTH-1:0] b5_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_1; +reg [`DWIDTH-1:0] b6_data_delayed_2; +reg [`DWIDTH-1:0] b6_data_delayed_3; +reg [`DWIDTH-1:0] b6_data_delayed_4; +reg [`DWIDTH-1:0] b6_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_1; +reg [`DWIDTH-1:0] b7_data_delayed_2; +reg [`DWIDTH-1:0] b7_data_delayed_3; +reg [`DWIDTH-1:0] b7_data_delayed_4; +reg [`DWIDTH-1:0] b7_data_delayed_5; +reg [`DWIDTH-1:0] b7_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_1; +reg [`DWIDTH-1:0] b8_data_delayed_2; +reg [`DWIDTH-1:0] b8_data_delayed_3; +reg [`DWIDTH-1:0] b8_data_delayed_4; +reg [`DWIDTH-1:0] b8_data_delayed_5; +reg [`DWIDTH-1:0] b8_data_delayed_6; +reg [`DWIDTH-1:0] b8_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_1; +reg [`DWIDTH-1:0] b9_data_delayed_2; +reg [`DWIDTH-1:0] b9_data_delayed_3; +reg [`DWIDTH-1:0] b9_data_delayed_4; +reg [`DWIDTH-1:0] b9_data_delayed_5; +reg [`DWIDTH-1:0] b9_data_delayed_6; +reg [`DWIDTH-1:0] b9_data_delayed_7; +reg [`DWIDTH-1:0] b9_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_1; +reg [`DWIDTH-1:0] b10_data_delayed_2; +reg [`DWIDTH-1:0] b10_data_delayed_3; +reg [`DWIDTH-1:0] b10_data_delayed_4; +reg [`DWIDTH-1:0] b10_data_delayed_5; +reg [`DWIDTH-1:0] b10_data_delayed_6; +reg [`DWIDTH-1:0] b10_data_delayed_7; +reg [`DWIDTH-1:0] b10_data_delayed_8; +reg [`DWIDTH-1:0] b10_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_1; +reg [`DWIDTH-1:0] b11_data_delayed_2; +reg [`DWIDTH-1:0] b11_data_delayed_3; +reg [`DWIDTH-1:0] b11_data_delayed_4; +reg [`DWIDTH-1:0] b11_data_delayed_5; +reg [`DWIDTH-1:0] b11_data_delayed_6; +reg [`DWIDTH-1:0] b11_data_delayed_7; +reg [`DWIDTH-1:0] b11_data_delayed_8; +reg [`DWIDTH-1:0] b11_data_delayed_9; +reg [`DWIDTH-1:0] b11_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_1; +reg [`DWIDTH-1:0] b12_data_delayed_2; +reg [`DWIDTH-1:0] b12_data_delayed_3; +reg [`DWIDTH-1:0] b12_data_delayed_4; +reg [`DWIDTH-1:0] b12_data_delayed_5; +reg [`DWIDTH-1:0] b12_data_delayed_6; +reg [`DWIDTH-1:0] b12_data_delayed_7; +reg [`DWIDTH-1:0] b12_data_delayed_8; +reg [`DWIDTH-1:0] b12_data_delayed_9; +reg [`DWIDTH-1:0] b12_data_delayed_10; +reg [`DWIDTH-1:0] b12_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_1; +reg [`DWIDTH-1:0] b13_data_delayed_2; +reg [`DWIDTH-1:0] b13_data_delayed_3; +reg [`DWIDTH-1:0] b13_data_delayed_4; +reg [`DWIDTH-1:0] b13_data_delayed_5; +reg [`DWIDTH-1:0] b13_data_delayed_6; +reg [`DWIDTH-1:0] b13_data_delayed_7; +reg [`DWIDTH-1:0] b13_data_delayed_8; +reg [`DWIDTH-1:0] b13_data_delayed_9; +reg [`DWIDTH-1:0] b13_data_delayed_10; +reg [`DWIDTH-1:0] b13_data_delayed_11; +reg [`DWIDTH-1:0] b13_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_1; +reg [`DWIDTH-1:0] b14_data_delayed_2; +reg [`DWIDTH-1:0] b14_data_delayed_3; +reg [`DWIDTH-1:0] b14_data_delayed_4; +reg [`DWIDTH-1:0] b14_data_delayed_5; +reg [`DWIDTH-1:0] b14_data_delayed_6; +reg [`DWIDTH-1:0] b14_data_delayed_7; +reg [`DWIDTH-1:0] b14_data_delayed_8; +reg [`DWIDTH-1:0] b14_data_delayed_9; +reg [`DWIDTH-1:0] b14_data_delayed_10; +reg [`DWIDTH-1:0] b14_data_delayed_11; +reg [`DWIDTH-1:0] b14_data_delayed_12; +reg [`DWIDTH-1:0] b14_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_1; +reg [`DWIDTH-1:0] b15_data_delayed_2; +reg [`DWIDTH-1:0] b15_data_delayed_3; +reg [`DWIDTH-1:0] b15_data_delayed_4; +reg [`DWIDTH-1:0] b15_data_delayed_5; +reg [`DWIDTH-1:0] b15_data_delayed_6; +reg [`DWIDTH-1:0] b15_data_delayed_7; +reg [`DWIDTH-1:0] b15_data_delayed_8; +reg [`DWIDTH-1:0] b15_data_delayed_9; +reg [`DWIDTH-1:0] b15_data_delayed_10; +reg [`DWIDTH-1:0] b15_data_delayed_11; +reg [`DWIDTH-1:0] b15_data_delayed_12; +reg [`DWIDTH-1:0] b15_data_delayed_13; +reg [`DWIDTH-1:0] b15_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_15; +reg [`DWIDTH-1:0] b16_data_delayed_1; +reg [`DWIDTH-1:0] b16_data_delayed_2; +reg [`DWIDTH-1:0] b16_data_delayed_3; +reg [`DWIDTH-1:0] b16_data_delayed_4; +reg [`DWIDTH-1:0] b16_data_delayed_5; +reg [`DWIDTH-1:0] b16_data_delayed_6; +reg [`DWIDTH-1:0] b16_data_delayed_7; +reg [`DWIDTH-1:0] b16_data_delayed_8; +reg [`DWIDTH-1:0] b16_data_delayed_9; +reg [`DWIDTH-1:0] b16_data_delayed_10; +reg [`DWIDTH-1:0] b16_data_delayed_11; +reg [`DWIDTH-1:0] b16_data_delayed_12; +reg [`DWIDTH-1:0] b16_data_delayed_13; +reg [`DWIDTH-1:0] b16_data_delayed_14; +reg [`DWIDTH-1:0] b16_data_delayed_15; +reg [`DWIDTH-1:0] b16_data_delayed_16; +reg [`DWIDTH-1:0] b17_data_delayed_1; +reg [`DWIDTH-1:0] b17_data_delayed_2; +reg [`DWIDTH-1:0] b17_data_delayed_3; +reg [`DWIDTH-1:0] b17_data_delayed_4; +reg [`DWIDTH-1:0] b17_data_delayed_5; +reg [`DWIDTH-1:0] b17_data_delayed_6; +reg [`DWIDTH-1:0] b17_data_delayed_7; +reg [`DWIDTH-1:0] b17_data_delayed_8; +reg [`DWIDTH-1:0] b17_data_delayed_9; +reg [`DWIDTH-1:0] b17_data_delayed_10; +reg [`DWIDTH-1:0] b17_data_delayed_11; +reg [`DWIDTH-1:0] b17_data_delayed_12; +reg [`DWIDTH-1:0] b17_data_delayed_13; +reg [`DWIDTH-1:0] b17_data_delayed_14; +reg [`DWIDTH-1:0] b17_data_delayed_15; +reg [`DWIDTH-1:0] b17_data_delayed_16; +reg [`DWIDTH-1:0] b17_data_delayed_17; +reg [`DWIDTH-1:0] b18_data_delayed_1; +reg [`DWIDTH-1:0] b18_data_delayed_2; +reg [`DWIDTH-1:0] b18_data_delayed_3; +reg [`DWIDTH-1:0] b18_data_delayed_4; +reg [`DWIDTH-1:0] b18_data_delayed_5; +reg [`DWIDTH-1:0] b18_data_delayed_6; +reg [`DWIDTH-1:0] b18_data_delayed_7; +reg [`DWIDTH-1:0] b18_data_delayed_8; +reg [`DWIDTH-1:0] b18_data_delayed_9; +reg [`DWIDTH-1:0] b18_data_delayed_10; +reg [`DWIDTH-1:0] b18_data_delayed_11; +reg [`DWIDTH-1:0] b18_data_delayed_12; +reg [`DWIDTH-1:0] b18_data_delayed_13; +reg [`DWIDTH-1:0] b18_data_delayed_14; +reg [`DWIDTH-1:0] b18_data_delayed_15; +reg [`DWIDTH-1:0] b18_data_delayed_16; +reg [`DWIDTH-1:0] b18_data_delayed_17; +reg [`DWIDTH-1:0] b18_data_delayed_18; +reg [`DWIDTH-1:0] b19_data_delayed_1; +reg [`DWIDTH-1:0] b19_data_delayed_2; +reg [`DWIDTH-1:0] b19_data_delayed_3; +reg [`DWIDTH-1:0] b19_data_delayed_4; +reg [`DWIDTH-1:0] b19_data_delayed_5; +reg [`DWIDTH-1:0] b19_data_delayed_6; +reg [`DWIDTH-1:0] b19_data_delayed_7; +reg [`DWIDTH-1:0] b19_data_delayed_8; +reg [`DWIDTH-1:0] b19_data_delayed_9; +reg [`DWIDTH-1:0] b19_data_delayed_10; +reg [`DWIDTH-1:0] b19_data_delayed_11; +reg [`DWIDTH-1:0] b19_data_delayed_12; +reg [`DWIDTH-1:0] b19_data_delayed_13; +reg [`DWIDTH-1:0] b19_data_delayed_14; +reg [`DWIDTH-1:0] b19_data_delayed_15; +reg [`DWIDTH-1:0] b19_data_delayed_16; +reg [`DWIDTH-1:0] b19_data_delayed_17; +reg [`DWIDTH-1:0] b19_data_delayed_18; +reg [`DWIDTH-1:0] b19_data_delayed_19; + + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + b1_data_delayed_1 <= 0; + b2_data_delayed_1 <= 0; + b2_data_delayed_2 <= 0; + b3_data_delayed_1 <= 0; + b3_data_delayed_2 <= 0; + b3_data_delayed_3 <= 0; + b4_data_delayed_1 <= 0; + b4_data_delayed_2 <= 0; + b4_data_delayed_3 <= 0; + b4_data_delayed_4 <= 0; + b5_data_delayed_1 <= 0; + b5_data_delayed_2 <= 0; + b5_data_delayed_3 <= 0; + b5_data_delayed_4 <= 0; + b5_data_delayed_5 <= 0; + b6_data_delayed_1 <= 0; + b6_data_delayed_2 <= 0; + b6_data_delayed_3 <= 0; + b6_data_delayed_4 <= 0; + b6_data_delayed_5 <= 0; + b6_data_delayed_6 <= 0; + b7_data_delayed_1 <= 0; + b7_data_delayed_2 <= 0; + b7_data_delayed_3 <= 0; + b7_data_delayed_4 <= 0; + b7_data_delayed_5 <= 0; + b7_data_delayed_6 <= 0; + b7_data_delayed_7 <= 0; + b8_data_delayed_1 <= 0; + b8_data_delayed_2 <= 0; + b8_data_delayed_3 <= 0; + b8_data_delayed_4 <= 0; + b8_data_delayed_5 <= 0; + b8_data_delayed_6 <= 0; + b8_data_delayed_7 <= 0; + b8_data_delayed_8 <= 0; + b9_data_delayed_1 <= 0; + b9_data_delayed_2 <= 0; + b9_data_delayed_3 <= 0; + b9_data_delayed_4 <= 0; + b9_data_delayed_5 <= 0; + b9_data_delayed_6 <= 0; + b9_data_delayed_7 <= 0; + b9_data_delayed_8 <= 0; + b9_data_delayed_9 <= 0; + b10_data_delayed_1 <= 0; + b10_data_delayed_2 <= 0; + b10_data_delayed_3 <= 0; + b10_data_delayed_4 <= 0; + b10_data_delayed_5 <= 0; + b10_data_delayed_6 <= 0; + b10_data_delayed_7 <= 0; + b10_data_delayed_8 <= 0; + b10_data_delayed_9 <= 0; + b10_data_delayed_10 <= 0; + b11_data_delayed_1 <= 0; + b11_data_delayed_2 <= 0; + b11_data_delayed_3 <= 0; + b11_data_delayed_4 <= 0; + b11_data_delayed_5 <= 0; + b11_data_delayed_6 <= 0; + b11_data_delayed_7 <= 0; + b11_data_delayed_8 <= 0; + b11_data_delayed_9 <= 0; + b11_data_delayed_10 <= 0; + b11_data_delayed_11 <= 0; + b12_data_delayed_1 <= 0; + b12_data_delayed_2 <= 0; + b12_data_delayed_3 <= 0; + b12_data_delayed_4 <= 0; + b12_data_delayed_5 <= 0; + b12_data_delayed_6 <= 0; + b12_data_delayed_7 <= 0; + b12_data_delayed_8 <= 0; + b12_data_delayed_9 <= 0; + b12_data_delayed_10 <= 0; + b12_data_delayed_11 <= 0; + b12_data_delayed_12 <= 0; + b13_data_delayed_1 <= 0; + b13_data_delayed_2 <= 0; + b13_data_delayed_3 <= 0; + b13_data_delayed_4 <= 0; + b13_data_delayed_5 <= 0; + b13_data_delayed_6 <= 0; + b13_data_delayed_7 <= 0; + b13_data_delayed_8 <= 0; + b13_data_delayed_9 <= 0; + b13_data_delayed_10 <= 0; + b13_data_delayed_11 <= 0; + b13_data_delayed_12 <= 0; + b13_data_delayed_13 <= 0; + b14_data_delayed_1 <= 0; + b14_data_delayed_2 <= 0; + b14_data_delayed_3 <= 0; + b14_data_delayed_4 <= 0; + b14_data_delayed_5 <= 0; + b14_data_delayed_6 <= 0; + b14_data_delayed_7 <= 0; + b14_data_delayed_8 <= 0; + b14_data_delayed_9 <= 0; + b14_data_delayed_10 <= 0; + b14_data_delayed_11 <= 0; + b14_data_delayed_12 <= 0; + b14_data_delayed_13 <= 0; + b14_data_delayed_14 <= 0; + b15_data_delayed_1 <= 0; + b15_data_delayed_2 <= 0; + b15_data_delayed_3 <= 0; + b15_data_delayed_4 <= 0; + b15_data_delayed_5 <= 0; + b15_data_delayed_6 <= 0; + b15_data_delayed_7 <= 0; + b15_data_delayed_8 <= 0; + b15_data_delayed_9 <= 0; + b15_data_delayed_10 <= 0; + b15_data_delayed_11 <= 0; + b15_data_delayed_12 <= 0; + b15_data_delayed_13 <= 0; + b15_data_delayed_14 <= 0; + b15_data_delayed_15 <= 0; + b16_data_delayed_1 <= 0; + b16_data_delayed_2 <= 0; + b16_data_delayed_3 <= 0; + b16_data_delayed_4 <= 0; + b16_data_delayed_5 <= 0; + b16_data_delayed_6 <= 0; + b16_data_delayed_7 <= 0; + b16_data_delayed_8 <= 0; + b16_data_delayed_9 <= 0; + b16_data_delayed_10 <= 0; + b16_data_delayed_11 <= 0; + b16_data_delayed_12 <= 0; + b16_data_delayed_13 <= 0; + b16_data_delayed_14 <= 0; + b16_data_delayed_15 <= 0; + b16_data_delayed_16 <= 0; + b17_data_delayed_1 <= 0; + b17_data_delayed_2 <= 0; + b17_data_delayed_3 <= 0; + b17_data_delayed_4 <= 0; + b17_data_delayed_5 <= 0; + b17_data_delayed_6 <= 0; + b17_data_delayed_7 <= 0; + b17_data_delayed_8 <= 0; + b17_data_delayed_9 <= 0; + b17_data_delayed_10 <= 0; + b17_data_delayed_11 <= 0; + b17_data_delayed_12 <= 0; + b17_data_delayed_13 <= 0; + b17_data_delayed_14 <= 0; + b17_data_delayed_15 <= 0; + b17_data_delayed_16 <= 0; + b17_data_delayed_17 <= 0; + b18_data_delayed_1 <= 0; + b18_data_delayed_2 <= 0; + b18_data_delayed_3 <= 0; + b18_data_delayed_4 <= 0; + b18_data_delayed_5 <= 0; + b18_data_delayed_6 <= 0; + b18_data_delayed_7 <= 0; + b18_data_delayed_8 <= 0; + b18_data_delayed_9 <= 0; + b18_data_delayed_10 <= 0; + b18_data_delayed_11 <= 0; + b18_data_delayed_12 <= 0; + b18_data_delayed_13 <= 0; + b18_data_delayed_14 <= 0; + b18_data_delayed_15 <= 0; + b18_data_delayed_16 <= 0; + b18_data_delayed_17 <= 0; + b18_data_delayed_18 <= 0; + b19_data_delayed_1 <= 0; + b19_data_delayed_2 <= 0; + b19_data_delayed_3 <= 0; + b19_data_delayed_4 <= 0; + b19_data_delayed_5 <= 0; + b19_data_delayed_6 <= 0; + b19_data_delayed_7 <= 0; + b19_data_delayed_8 <= 0; + b19_data_delayed_9 <= 0; + b19_data_delayed_10 <= 0; + b19_data_delayed_11 <= 0; + b19_data_delayed_12 <= 0; + b19_data_delayed_13 <= 0; + b19_data_delayed_14 <= 0; + b19_data_delayed_15 <= 0; + b19_data_delayed_16 <= 0; + b19_data_delayed_17 <= 0; + b19_data_delayed_18 <= 0; + b19_data_delayed_19 <= 0; + + end + else begin + b1_data_delayed_1 <= b1_data; + b2_data_delayed_1 <= b2_data; + b3_data_delayed_1 <= b3_data; + b4_data_delayed_1 <= b4_data; + b5_data_delayed_1 <= b5_data; + b6_data_delayed_1 <= b6_data; + b7_data_delayed_1 <= b7_data; + b8_data_delayed_1 <= b8_data; + b9_data_delayed_1 <= b9_data; + b10_data_delayed_1 <= b10_data; + b11_data_delayed_1 <= b11_data; + b12_data_delayed_1 <= b12_data; + b13_data_delayed_1 <= b13_data; + b14_data_delayed_1 <= b14_data; + b15_data_delayed_1 <= b15_data; + b16_data_delayed_1 <= b16_data; + b17_data_delayed_1 <= b17_data; + b18_data_delayed_1 <= b18_data; + b19_data_delayed_1 <= b19_data; + b2_data_delayed_2 <= b2_data_delayed_1; + b3_data_delayed_2 <= b3_data_delayed_1; + b3_data_delayed_3 <= b3_data_delayed_2; + b4_data_delayed_2 <= b4_data_delayed_1; + b4_data_delayed_3 <= b4_data_delayed_2; + b4_data_delayed_4 <= b4_data_delayed_3; + b5_data_delayed_2 <= b5_data_delayed_1; + b5_data_delayed_3 <= b5_data_delayed_2; + b5_data_delayed_4 <= b5_data_delayed_3; + b5_data_delayed_5 <= b5_data_delayed_4; + b6_data_delayed_2 <= b6_data_delayed_1; + b6_data_delayed_3 <= b6_data_delayed_2; + b6_data_delayed_4 <= b6_data_delayed_3; + b6_data_delayed_5 <= b6_data_delayed_4; + b6_data_delayed_6 <= b6_data_delayed_5; + b7_data_delayed_2 <= b7_data_delayed_1; + b7_data_delayed_3 <= b7_data_delayed_2; + b7_data_delayed_4 <= b7_data_delayed_3; + b7_data_delayed_5 <= b7_data_delayed_4; + b7_data_delayed_6 <= b7_data_delayed_5; + b7_data_delayed_7 <= b7_data_delayed_6; + b8_data_delayed_2 <= b8_data_delayed_1; + b8_data_delayed_3 <= b8_data_delayed_2; + b8_data_delayed_4 <= b8_data_delayed_3; + b8_data_delayed_5 <= b8_data_delayed_4; + b8_data_delayed_6 <= b8_data_delayed_5; + b8_data_delayed_7 <= b8_data_delayed_6; + b8_data_delayed_8 <= b8_data_delayed_7; + b9_data_delayed_2 <= b9_data_delayed_1; + b9_data_delayed_3 <= b9_data_delayed_2; + b9_data_delayed_4 <= b9_data_delayed_3; + b9_data_delayed_5 <= b9_data_delayed_4; + b9_data_delayed_6 <= b9_data_delayed_5; + b9_data_delayed_7 <= b9_data_delayed_6; + b9_data_delayed_8 <= b9_data_delayed_7; + b9_data_delayed_9 <= b9_data_delayed_8; + b10_data_delayed_2 <= b10_data_delayed_1; + b10_data_delayed_3 <= b10_data_delayed_2; + b10_data_delayed_4 <= b10_data_delayed_3; + b10_data_delayed_5 <= b10_data_delayed_4; + b10_data_delayed_6 <= b10_data_delayed_5; + b10_data_delayed_7 <= b10_data_delayed_6; + b10_data_delayed_8 <= b10_data_delayed_7; + b10_data_delayed_9 <= b10_data_delayed_8; + b10_data_delayed_10 <= b10_data_delayed_9; + b11_data_delayed_2 <= b11_data_delayed_1; + b11_data_delayed_3 <= b11_data_delayed_2; + b11_data_delayed_4 <= b11_data_delayed_3; + b11_data_delayed_5 <= b11_data_delayed_4; + b11_data_delayed_6 <= b11_data_delayed_5; + b11_data_delayed_7 <= b11_data_delayed_6; + b11_data_delayed_8 <= b11_data_delayed_7; + b11_data_delayed_9 <= b11_data_delayed_8; + b11_data_delayed_10 <= b11_data_delayed_9; + b11_data_delayed_11 <= b11_data_delayed_10; + b12_data_delayed_2 <= b12_data_delayed_1; + b12_data_delayed_3 <= b12_data_delayed_2; + b12_data_delayed_4 <= b12_data_delayed_3; + b12_data_delayed_5 <= b12_data_delayed_4; + b12_data_delayed_6 <= b12_data_delayed_5; + b12_data_delayed_7 <= b12_data_delayed_6; + b12_data_delayed_8 <= b12_data_delayed_7; + b12_data_delayed_9 <= b12_data_delayed_8; + b12_data_delayed_10 <= b12_data_delayed_9; + b12_data_delayed_11 <= b12_data_delayed_10; + b12_data_delayed_12 <= b12_data_delayed_11; + b13_data_delayed_2 <= b13_data_delayed_1; + b13_data_delayed_3 <= b13_data_delayed_2; + b13_data_delayed_4 <= b13_data_delayed_3; + b13_data_delayed_5 <= b13_data_delayed_4; + b13_data_delayed_6 <= b13_data_delayed_5; + b13_data_delayed_7 <= b13_data_delayed_6; + b13_data_delayed_8 <= b13_data_delayed_7; + b13_data_delayed_9 <= b13_data_delayed_8; + b13_data_delayed_10 <= b13_data_delayed_9; + b13_data_delayed_11 <= b13_data_delayed_10; + b13_data_delayed_12 <= b13_data_delayed_11; + b13_data_delayed_13 <= b13_data_delayed_12; + b14_data_delayed_2 <= b14_data_delayed_1; + b14_data_delayed_3 <= b14_data_delayed_2; + b14_data_delayed_4 <= b14_data_delayed_3; + b14_data_delayed_5 <= b14_data_delayed_4; + b14_data_delayed_6 <= b14_data_delayed_5; + b14_data_delayed_7 <= b14_data_delayed_6; + b14_data_delayed_8 <= b14_data_delayed_7; + b14_data_delayed_9 <= b14_data_delayed_8; + b14_data_delayed_10 <= b14_data_delayed_9; + b14_data_delayed_11 <= b14_data_delayed_10; + b14_data_delayed_12 <= b14_data_delayed_11; + b14_data_delayed_13 <= b14_data_delayed_12; + b14_data_delayed_14 <= b14_data_delayed_13; + b15_data_delayed_2 <= b15_data_delayed_1; + b15_data_delayed_3 <= b15_data_delayed_2; + b15_data_delayed_4 <= b15_data_delayed_3; + b15_data_delayed_5 <= b15_data_delayed_4; + b15_data_delayed_6 <= b15_data_delayed_5; + b15_data_delayed_7 <= b15_data_delayed_6; + b15_data_delayed_8 <= b15_data_delayed_7; + b15_data_delayed_9 <= b15_data_delayed_8; + b15_data_delayed_10 <= b15_data_delayed_9; + b15_data_delayed_11 <= b15_data_delayed_10; + b15_data_delayed_12 <= b15_data_delayed_11; + b15_data_delayed_13 <= b15_data_delayed_12; + b15_data_delayed_14 <= b15_data_delayed_13; + b15_data_delayed_15 <= b15_data_delayed_14; + b16_data_delayed_2 <= b16_data_delayed_1; + b16_data_delayed_3 <= b16_data_delayed_2; + b16_data_delayed_4 <= b16_data_delayed_3; + b16_data_delayed_5 <= b16_data_delayed_4; + b16_data_delayed_6 <= b16_data_delayed_5; + b16_data_delayed_7 <= b16_data_delayed_6; + b16_data_delayed_8 <= b16_data_delayed_7; + b16_data_delayed_9 <= b16_data_delayed_8; + b16_data_delayed_10 <= b16_data_delayed_9; + b16_data_delayed_11 <= b16_data_delayed_10; + b16_data_delayed_12 <= b16_data_delayed_11; + b16_data_delayed_13 <= b16_data_delayed_12; + b16_data_delayed_14 <= b16_data_delayed_13; + b16_data_delayed_15 <= b16_data_delayed_14; + b16_data_delayed_16 <= b16_data_delayed_15; + b17_data_delayed_2 <= b17_data_delayed_1; + b17_data_delayed_3 <= b17_data_delayed_2; + b17_data_delayed_4 <= b17_data_delayed_3; + b17_data_delayed_5 <= b17_data_delayed_4; + b17_data_delayed_6 <= b17_data_delayed_5; + b17_data_delayed_7 <= b17_data_delayed_6; + b17_data_delayed_8 <= b17_data_delayed_7; + b17_data_delayed_9 <= b17_data_delayed_8; + b17_data_delayed_10 <= b17_data_delayed_9; + b17_data_delayed_11 <= b17_data_delayed_10; + b17_data_delayed_12 <= b17_data_delayed_11; + b17_data_delayed_13 <= b17_data_delayed_12; + b17_data_delayed_14 <= b17_data_delayed_13; + b17_data_delayed_15 <= b17_data_delayed_14; + b17_data_delayed_16 <= b17_data_delayed_15; + b17_data_delayed_17 <= b17_data_delayed_16; + b18_data_delayed_2 <= b18_data_delayed_1; + b18_data_delayed_3 <= b18_data_delayed_2; + b18_data_delayed_4 <= b18_data_delayed_3; + b18_data_delayed_5 <= b18_data_delayed_4; + b18_data_delayed_6 <= b18_data_delayed_5; + b18_data_delayed_7 <= b18_data_delayed_6; + b18_data_delayed_8 <= b18_data_delayed_7; + b18_data_delayed_9 <= b18_data_delayed_8; + b18_data_delayed_10 <= b18_data_delayed_9; + b18_data_delayed_11 <= b18_data_delayed_10; + b18_data_delayed_12 <= b18_data_delayed_11; + b18_data_delayed_13 <= b18_data_delayed_12; + b18_data_delayed_14 <= b18_data_delayed_13; + b18_data_delayed_15 <= b18_data_delayed_14; + b18_data_delayed_16 <= b18_data_delayed_15; + b18_data_delayed_17 <= b18_data_delayed_16; + b18_data_delayed_18 <= b18_data_delayed_17; + b19_data_delayed_2 <= b19_data_delayed_1; + b19_data_delayed_3 <= b19_data_delayed_2; + b19_data_delayed_4 <= b19_data_delayed_3; + b19_data_delayed_5 <= b19_data_delayed_4; + b19_data_delayed_6 <= b19_data_delayed_5; + b19_data_delayed_7 <= b19_data_delayed_6; + b19_data_delayed_8 <= b19_data_delayed_7; + b19_data_delayed_9 <= b19_data_delayed_8; + b19_data_delayed_10 <= b19_data_delayed_9; + b19_data_delayed_11 <= b19_data_delayed_10; + b19_data_delayed_12 <= b19_data_delayed_11; + b19_data_delayed_13 <= b19_data_delayed_12; + b19_data_delayed_14 <= b19_data_delayed_13; + b19_data_delayed_15 <= b19_data_delayed_14; + b19_data_delayed_16 <= b19_data_delayed_15; + b19_data_delayed_17 <= b19_data_delayed_16; + b19_data_delayed_18 <= b19_data_delayed_17; + b19_data_delayed_19 <= b19_data_delayed_18; + + end +end +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolically connected PEs +////////////////////////////////////////////////////////////////////////// +module systolic_pe_matrix( +clk, +reset, +pe_reset, +a0, +a1, +a2, +a3, +a4, +a5, +a6, +a7, +a8, +a9, +a10, +a11, +a12, +a13, +a14, +a15, +a16, +a17, +a18, +a19, +b0, +b1, +b2, +b3, +b4, +b5, +b6, +b7, +b8, +b9, +b10, +b11, +b12, +b13, +b14, +b15, +b16, +b17, +b18, +b19, +matrixC0_0, +matrixC0_1, +matrixC0_2, +matrixC0_3, +matrixC0_4, +matrixC0_5, +matrixC0_6, +matrixC0_7, +matrixC0_8, +matrixC0_9, +matrixC0_10, +matrixC0_11, +matrixC0_12, +matrixC0_13, +matrixC0_14, +matrixC0_15, +matrixC0_16, +matrixC0_17, +matrixC0_18, +matrixC0_19, +matrixC1_0, +matrixC1_1, +matrixC1_2, +matrixC1_3, +matrixC1_4, +matrixC1_5, +matrixC1_6, +matrixC1_7, +matrixC1_8, +matrixC1_9, +matrixC1_10, +matrixC1_11, +matrixC1_12, +matrixC1_13, +matrixC1_14, +matrixC1_15, +matrixC1_16, +matrixC1_17, +matrixC1_18, +matrixC1_19, +matrixC2_0, +matrixC2_1, +matrixC2_2, +matrixC2_3, +matrixC2_4, +matrixC2_5, +matrixC2_6, +matrixC2_7, +matrixC2_8, +matrixC2_9, +matrixC2_10, +matrixC2_11, +matrixC2_12, +matrixC2_13, +matrixC2_14, +matrixC2_15, +matrixC2_16, +matrixC2_17, +matrixC2_18, +matrixC2_19, +matrixC3_0, +matrixC3_1, +matrixC3_2, +matrixC3_3, +matrixC3_4, +matrixC3_5, +matrixC3_6, +matrixC3_7, +matrixC3_8, +matrixC3_9, +matrixC3_10, +matrixC3_11, +matrixC3_12, +matrixC3_13, +matrixC3_14, +matrixC3_15, +matrixC3_16, +matrixC3_17, +matrixC3_18, +matrixC3_19, +matrixC4_0, +matrixC4_1, +matrixC4_2, +matrixC4_3, +matrixC4_4, +matrixC4_5, +matrixC4_6, +matrixC4_7, +matrixC4_8, +matrixC4_9, +matrixC4_10, +matrixC4_11, +matrixC4_12, +matrixC4_13, +matrixC4_14, +matrixC4_15, +matrixC4_16, +matrixC4_17, +matrixC4_18, +matrixC4_19, +matrixC5_0, +matrixC5_1, +matrixC5_2, +matrixC5_3, +matrixC5_4, +matrixC5_5, +matrixC5_6, +matrixC5_7, +matrixC5_8, +matrixC5_9, +matrixC5_10, +matrixC5_11, +matrixC5_12, +matrixC5_13, +matrixC5_14, +matrixC5_15, +matrixC5_16, +matrixC5_17, +matrixC5_18, +matrixC5_19, +matrixC6_0, +matrixC6_1, +matrixC6_2, +matrixC6_3, +matrixC6_4, +matrixC6_5, +matrixC6_6, +matrixC6_7, +matrixC6_8, +matrixC6_9, +matrixC6_10, +matrixC6_11, +matrixC6_12, +matrixC6_13, +matrixC6_14, +matrixC6_15, +matrixC6_16, +matrixC6_17, +matrixC6_18, +matrixC6_19, +matrixC7_0, +matrixC7_1, +matrixC7_2, +matrixC7_3, +matrixC7_4, +matrixC7_5, +matrixC7_6, +matrixC7_7, +matrixC7_8, +matrixC7_9, +matrixC7_10, +matrixC7_11, +matrixC7_12, +matrixC7_13, +matrixC7_14, +matrixC7_15, +matrixC7_16, +matrixC7_17, +matrixC7_18, +matrixC7_19, +matrixC8_0, +matrixC8_1, +matrixC8_2, +matrixC8_3, +matrixC8_4, +matrixC8_5, +matrixC8_6, +matrixC8_7, +matrixC8_8, +matrixC8_9, +matrixC8_10, +matrixC8_11, +matrixC8_12, +matrixC8_13, +matrixC8_14, +matrixC8_15, +matrixC8_16, +matrixC8_17, +matrixC8_18, +matrixC8_19, +matrixC9_0, +matrixC9_1, +matrixC9_2, +matrixC9_3, +matrixC9_4, +matrixC9_5, +matrixC9_6, +matrixC9_7, +matrixC9_8, +matrixC9_9, +matrixC9_10, +matrixC9_11, +matrixC9_12, +matrixC9_13, +matrixC9_14, +matrixC9_15, +matrixC9_16, +matrixC9_17, +matrixC9_18, +matrixC9_19, +matrixC10_0, +matrixC10_1, +matrixC10_2, +matrixC10_3, +matrixC10_4, +matrixC10_5, +matrixC10_6, +matrixC10_7, +matrixC10_8, +matrixC10_9, +matrixC10_10, +matrixC10_11, +matrixC10_12, +matrixC10_13, +matrixC10_14, +matrixC10_15, +matrixC10_16, +matrixC10_17, +matrixC10_18, +matrixC10_19, +matrixC11_0, +matrixC11_1, +matrixC11_2, +matrixC11_3, +matrixC11_4, +matrixC11_5, +matrixC11_6, +matrixC11_7, +matrixC11_8, +matrixC11_9, +matrixC11_10, +matrixC11_11, +matrixC11_12, +matrixC11_13, +matrixC11_14, +matrixC11_15, +matrixC11_16, +matrixC11_17, +matrixC11_18, +matrixC11_19, +matrixC12_0, +matrixC12_1, +matrixC12_2, +matrixC12_3, +matrixC12_4, +matrixC12_5, +matrixC12_6, +matrixC12_7, +matrixC12_8, +matrixC12_9, +matrixC12_10, +matrixC12_11, +matrixC12_12, +matrixC12_13, +matrixC12_14, +matrixC12_15, +matrixC12_16, +matrixC12_17, +matrixC12_18, +matrixC12_19, +matrixC13_0, +matrixC13_1, +matrixC13_2, +matrixC13_3, +matrixC13_4, +matrixC13_5, +matrixC13_6, +matrixC13_7, +matrixC13_8, +matrixC13_9, +matrixC13_10, +matrixC13_11, +matrixC13_12, +matrixC13_13, +matrixC13_14, +matrixC13_15, +matrixC13_16, +matrixC13_17, +matrixC13_18, +matrixC13_19, +matrixC14_0, +matrixC14_1, +matrixC14_2, +matrixC14_3, +matrixC14_4, +matrixC14_5, +matrixC14_6, +matrixC14_7, +matrixC14_8, +matrixC14_9, +matrixC14_10, +matrixC14_11, +matrixC14_12, +matrixC14_13, +matrixC14_14, +matrixC14_15, +matrixC14_16, +matrixC14_17, +matrixC14_18, +matrixC14_19, +matrixC15_0, +matrixC15_1, +matrixC15_2, +matrixC15_3, +matrixC15_4, +matrixC15_5, +matrixC15_6, +matrixC15_7, +matrixC15_8, +matrixC15_9, +matrixC15_10, +matrixC15_11, +matrixC15_12, +matrixC15_13, +matrixC15_14, +matrixC15_15, +matrixC15_16, +matrixC15_17, +matrixC15_18, +matrixC15_19, +matrixC16_0, +matrixC16_1, +matrixC16_2, +matrixC16_3, +matrixC16_4, +matrixC16_5, +matrixC16_6, +matrixC16_7, +matrixC16_8, +matrixC16_9, +matrixC16_10, +matrixC16_11, +matrixC16_12, +matrixC16_13, +matrixC16_14, +matrixC16_15, +matrixC16_16, +matrixC16_17, +matrixC16_18, +matrixC16_19, +matrixC17_0, +matrixC17_1, +matrixC17_2, +matrixC17_3, +matrixC17_4, +matrixC17_5, +matrixC17_6, +matrixC17_7, +matrixC17_8, +matrixC17_9, +matrixC17_10, +matrixC17_11, +matrixC17_12, +matrixC17_13, +matrixC17_14, +matrixC17_15, +matrixC17_16, +matrixC17_17, +matrixC17_18, +matrixC17_19, +matrixC18_0, +matrixC18_1, +matrixC18_2, +matrixC18_3, +matrixC18_4, +matrixC18_5, +matrixC18_6, +matrixC18_7, +matrixC18_8, +matrixC18_9, +matrixC18_10, +matrixC18_11, +matrixC18_12, +matrixC18_13, +matrixC18_14, +matrixC18_15, +matrixC18_16, +matrixC18_17, +matrixC18_18, +matrixC18_19, +matrixC19_0, +matrixC19_1, +matrixC19_2, +matrixC19_3, +matrixC19_4, +matrixC19_5, +matrixC19_6, +matrixC19_7, +matrixC19_8, +matrixC19_9, +matrixC19_10, +matrixC19_11, +matrixC19_12, +matrixC19_13, +matrixC19_14, +matrixC19_15, +matrixC19_16, +matrixC19_17, +matrixC19_18, +matrixC19_19, + +a_data_out, +b_data_out +); + +input clk; +input reset; +input pe_reset; +input [`DWIDTH-1:0] a0; +input [`DWIDTH-1:0] a1; +input [`DWIDTH-1:0] a2; +input [`DWIDTH-1:0] a3; +input [`DWIDTH-1:0] a4; +input [`DWIDTH-1:0] a5; +input [`DWIDTH-1:0] a6; +input [`DWIDTH-1:0] a7; +input [`DWIDTH-1:0] a8; +input [`DWIDTH-1:0] a9; +input [`DWIDTH-1:0] a10; +input [`DWIDTH-1:0] a11; +input [`DWIDTH-1:0] a12; +input [`DWIDTH-1:0] a13; +input [`DWIDTH-1:0] a14; +input [`DWIDTH-1:0] a15; +input [`DWIDTH-1:0] a16; +input [`DWIDTH-1:0] a17; +input [`DWIDTH-1:0] a18; +input [`DWIDTH-1:0] a19; +input [`DWIDTH-1:0] b0; +input [`DWIDTH-1:0] b1; +input [`DWIDTH-1:0] b2; +input [`DWIDTH-1:0] b3; +input [`DWIDTH-1:0] b4; +input [`DWIDTH-1:0] b5; +input [`DWIDTH-1:0] b6; +input [`DWIDTH-1:0] b7; +input [`DWIDTH-1:0] b8; +input [`DWIDTH-1:0] b9; +input [`DWIDTH-1:0] b10; +input [`DWIDTH-1:0] b11; +input [`DWIDTH-1:0] b12; +input [`DWIDTH-1:0] b13; +input [`DWIDTH-1:0] b14; +input [`DWIDTH-1:0] b15; +input [`DWIDTH-1:0] b16; +input [`DWIDTH-1:0] b17; +input [`DWIDTH-1:0] b18; +input [`DWIDTH-1:0] b19; +output [`DWIDTH-1:0] matrixC0_0; +output [`DWIDTH-1:0] matrixC0_1; +output [`DWIDTH-1:0] matrixC0_2; +output [`DWIDTH-1:0] matrixC0_3; +output [`DWIDTH-1:0] matrixC0_4; +output [`DWIDTH-1:0] matrixC0_5; +output [`DWIDTH-1:0] matrixC0_6; +output [`DWIDTH-1:0] matrixC0_7; +output [`DWIDTH-1:0] matrixC0_8; +output [`DWIDTH-1:0] matrixC0_9; +output [`DWIDTH-1:0] matrixC0_10; +output [`DWIDTH-1:0] matrixC0_11; +output [`DWIDTH-1:0] matrixC0_12; +output [`DWIDTH-1:0] matrixC0_13; +output [`DWIDTH-1:0] matrixC0_14; +output [`DWIDTH-1:0] matrixC0_15; +output [`DWIDTH-1:0] matrixC0_16; +output [`DWIDTH-1:0] matrixC0_17; +output [`DWIDTH-1:0] matrixC0_18; +output [`DWIDTH-1:0] matrixC0_19; +output [`DWIDTH-1:0] matrixC1_0; +output [`DWIDTH-1:0] matrixC1_1; +output [`DWIDTH-1:0] matrixC1_2; +output [`DWIDTH-1:0] matrixC1_3; +output [`DWIDTH-1:0] matrixC1_4; +output [`DWIDTH-1:0] matrixC1_5; +output [`DWIDTH-1:0] matrixC1_6; +output [`DWIDTH-1:0] matrixC1_7; +output [`DWIDTH-1:0] matrixC1_8; +output [`DWIDTH-1:0] matrixC1_9; +output [`DWIDTH-1:0] matrixC1_10; +output [`DWIDTH-1:0] matrixC1_11; +output [`DWIDTH-1:0] matrixC1_12; +output [`DWIDTH-1:0] matrixC1_13; +output [`DWIDTH-1:0] matrixC1_14; +output [`DWIDTH-1:0] matrixC1_15; +output [`DWIDTH-1:0] matrixC1_16; +output [`DWIDTH-1:0] matrixC1_17; +output [`DWIDTH-1:0] matrixC1_18; +output [`DWIDTH-1:0] matrixC1_19; +output [`DWIDTH-1:0] matrixC2_0; +output [`DWIDTH-1:0] matrixC2_1; +output [`DWIDTH-1:0] matrixC2_2; +output [`DWIDTH-1:0] matrixC2_3; +output [`DWIDTH-1:0] matrixC2_4; +output [`DWIDTH-1:0] matrixC2_5; +output [`DWIDTH-1:0] matrixC2_6; +output [`DWIDTH-1:0] matrixC2_7; +output [`DWIDTH-1:0] matrixC2_8; +output [`DWIDTH-1:0] matrixC2_9; +output [`DWIDTH-1:0] matrixC2_10; +output [`DWIDTH-1:0] matrixC2_11; +output [`DWIDTH-1:0] matrixC2_12; +output [`DWIDTH-1:0] matrixC2_13; +output [`DWIDTH-1:0] matrixC2_14; +output [`DWIDTH-1:0] matrixC2_15; +output [`DWIDTH-1:0] matrixC2_16; +output [`DWIDTH-1:0] matrixC2_17; +output [`DWIDTH-1:0] matrixC2_18; +output [`DWIDTH-1:0] matrixC2_19; +output [`DWIDTH-1:0] matrixC3_0; +output [`DWIDTH-1:0] matrixC3_1; +output [`DWIDTH-1:0] matrixC3_2; +output [`DWIDTH-1:0] matrixC3_3; +output [`DWIDTH-1:0] matrixC3_4; +output [`DWIDTH-1:0] matrixC3_5; +output [`DWIDTH-1:0] matrixC3_6; +output [`DWIDTH-1:0] matrixC3_7; +output [`DWIDTH-1:0] matrixC3_8; +output [`DWIDTH-1:0] matrixC3_9; +output [`DWIDTH-1:0] matrixC3_10; +output [`DWIDTH-1:0] matrixC3_11; +output [`DWIDTH-1:0] matrixC3_12; +output [`DWIDTH-1:0] matrixC3_13; +output [`DWIDTH-1:0] matrixC3_14; +output [`DWIDTH-1:0] matrixC3_15; +output [`DWIDTH-1:0] matrixC3_16; +output [`DWIDTH-1:0] matrixC3_17; +output [`DWIDTH-1:0] matrixC3_18; +output [`DWIDTH-1:0] matrixC3_19; +output [`DWIDTH-1:0] matrixC4_0; +output [`DWIDTH-1:0] matrixC4_1; +output [`DWIDTH-1:0] matrixC4_2; +output [`DWIDTH-1:0] matrixC4_3; +output [`DWIDTH-1:0] matrixC4_4; +output [`DWIDTH-1:0] matrixC4_5; +output [`DWIDTH-1:0] matrixC4_6; +output [`DWIDTH-1:0] matrixC4_7; +output [`DWIDTH-1:0] matrixC4_8; +output [`DWIDTH-1:0] matrixC4_9; +output [`DWIDTH-1:0] matrixC4_10; +output [`DWIDTH-1:0] matrixC4_11; +output [`DWIDTH-1:0] matrixC4_12; +output [`DWIDTH-1:0] matrixC4_13; +output [`DWIDTH-1:0] matrixC4_14; +output [`DWIDTH-1:0] matrixC4_15; +output [`DWIDTH-1:0] matrixC4_16; +output [`DWIDTH-1:0] matrixC4_17; +output [`DWIDTH-1:0] matrixC4_18; +output [`DWIDTH-1:0] matrixC4_19; +output [`DWIDTH-1:0] matrixC5_0; +output [`DWIDTH-1:0] matrixC5_1; +output [`DWIDTH-1:0] matrixC5_2; +output [`DWIDTH-1:0] matrixC5_3; +output [`DWIDTH-1:0] matrixC5_4; +output [`DWIDTH-1:0] matrixC5_5; +output [`DWIDTH-1:0] matrixC5_6; +output [`DWIDTH-1:0] matrixC5_7; +output [`DWIDTH-1:0] matrixC5_8; +output [`DWIDTH-1:0] matrixC5_9; +output [`DWIDTH-1:0] matrixC5_10; +output [`DWIDTH-1:0] matrixC5_11; +output [`DWIDTH-1:0] matrixC5_12; +output [`DWIDTH-1:0] matrixC5_13; +output [`DWIDTH-1:0] matrixC5_14; +output [`DWIDTH-1:0] matrixC5_15; +output [`DWIDTH-1:0] matrixC5_16; +output [`DWIDTH-1:0] matrixC5_17; +output [`DWIDTH-1:0] matrixC5_18; +output [`DWIDTH-1:0] matrixC5_19; +output [`DWIDTH-1:0] matrixC6_0; +output [`DWIDTH-1:0] matrixC6_1; +output [`DWIDTH-1:0] matrixC6_2; +output [`DWIDTH-1:0] matrixC6_3; +output [`DWIDTH-1:0] matrixC6_4; +output [`DWIDTH-1:0] matrixC6_5; +output [`DWIDTH-1:0] matrixC6_6; +output [`DWIDTH-1:0] matrixC6_7; +output [`DWIDTH-1:0] matrixC6_8; +output [`DWIDTH-1:0] matrixC6_9; +output [`DWIDTH-1:0] matrixC6_10; +output [`DWIDTH-1:0] matrixC6_11; +output [`DWIDTH-1:0] matrixC6_12; +output [`DWIDTH-1:0] matrixC6_13; +output [`DWIDTH-1:0] matrixC6_14; +output [`DWIDTH-1:0] matrixC6_15; +output [`DWIDTH-1:0] matrixC6_16; +output [`DWIDTH-1:0] matrixC6_17; +output [`DWIDTH-1:0] matrixC6_18; +output [`DWIDTH-1:0] matrixC6_19; +output [`DWIDTH-1:0] matrixC7_0; +output [`DWIDTH-1:0] matrixC7_1; +output [`DWIDTH-1:0] matrixC7_2; +output [`DWIDTH-1:0] matrixC7_3; +output [`DWIDTH-1:0] matrixC7_4; +output [`DWIDTH-1:0] matrixC7_5; +output [`DWIDTH-1:0] matrixC7_6; +output [`DWIDTH-1:0] matrixC7_7; +output [`DWIDTH-1:0] matrixC7_8; +output [`DWIDTH-1:0] matrixC7_9; +output [`DWIDTH-1:0] matrixC7_10; +output [`DWIDTH-1:0] matrixC7_11; +output [`DWIDTH-1:0] matrixC7_12; +output [`DWIDTH-1:0] matrixC7_13; +output [`DWIDTH-1:0] matrixC7_14; +output [`DWIDTH-1:0] matrixC7_15; +output [`DWIDTH-1:0] matrixC7_16; +output [`DWIDTH-1:0] matrixC7_17; +output [`DWIDTH-1:0] matrixC7_18; +output [`DWIDTH-1:0] matrixC7_19; +output [`DWIDTH-1:0] matrixC8_0; +output [`DWIDTH-1:0] matrixC8_1; +output [`DWIDTH-1:0] matrixC8_2; +output [`DWIDTH-1:0] matrixC8_3; +output [`DWIDTH-1:0] matrixC8_4; +output [`DWIDTH-1:0] matrixC8_5; +output [`DWIDTH-1:0] matrixC8_6; +output [`DWIDTH-1:0] matrixC8_7; +output [`DWIDTH-1:0] matrixC8_8; +output [`DWIDTH-1:0] matrixC8_9; +output [`DWIDTH-1:0] matrixC8_10; +output [`DWIDTH-1:0] matrixC8_11; +output [`DWIDTH-1:0] matrixC8_12; +output [`DWIDTH-1:0] matrixC8_13; +output [`DWIDTH-1:0] matrixC8_14; +output [`DWIDTH-1:0] matrixC8_15; +output [`DWIDTH-1:0] matrixC8_16; +output [`DWIDTH-1:0] matrixC8_17; +output [`DWIDTH-1:0] matrixC8_18; +output [`DWIDTH-1:0] matrixC8_19; +output [`DWIDTH-1:0] matrixC9_0; +output [`DWIDTH-1:0] matrixC9_1; +output [`DWIDTH-1:0] matrixC9_2; +output [`DWIDTH-1:0] matrixC9_3; +output [`DWIDTH-1:0] matrixC9_4; +output [`DWIDTH-1:0] matrixC9_5; +output [`DWIDTH-1:0] matrixC9_6; +output [`DWIDTH-1:0] matrixC9_7; +output [`DWIDTH-1:0] matrixC9_8; +output [`DWIDTH-1:0] matrixC9_9; +output [`DWIDTH-1:0] matrixC9_10; +output [`DWIDTH-1:0] matrixC9_11; +output [`DWIDTH-1:0] matrixC9_12; +output [`DWIDTH-1:0] matrixC9_13; +output [`DWIDTH-1:0] matrixC9_14; +output [`DWIDTH-1:0] matrixC9_15; +output [`DWIDTH-1:0] matrixC9_16; +output [`DWIDTH-1:0] matrixC9_17; +output [`DWIDTH-1:0] matrixC9_18; +output [`DWIDTH-1:0] matrixC9_19; +output [`DWIDTH-1:0] matrixC10_0; +output [`DWIDTH-1:0] matrixC10_1; +output [`DWIDTH-1:0] matrixC10_2; +output [`DWIDTH-1:0] matrixC10_3; +output [`DWIDTH-1:0] matrixC10_4; +output [`DWIDTH-1:0] matrixC10_5; +output [`DWIDTH-1:0] matrixC10_6; +output [`DWIDTH-1:0] matrixC10_7; +output [`DWIDTH-1:0] matrixC10_8; +output [`DWIDTH-1:0] matrixC10_9; +output [`DWIDTH-1:0] matrixC10_10; +output [`DWIDTH-1:0] matrixC10_11; +output [`DWIDTH-1:0] matrixC10_12; +output [`DWIDTH-1:0] matrixC10_13; +output [`DWIDTH-1:0] matrixC10_14; +output [`DWIDTH-1:0] matrixC10_15; +output [`DWIDTH-1:0] matrixC10_16; +output [`DWIDTH-1:0] matrixC10_17; +output [`DWIDTH-1:0] matrixC10_18; +output [`DWIDTH-1:0] matrixC10_19; +output [`DWIDTH-1:0] matrixC11_0; +output [`DWIDTH-1:0] matrixC11_1; +output [`DWIDTH-1:0] matrixC11_2; +output [`DWIDTH-1:0] matrixC11_3; +output [`DWIDTH-1:0] matrixC11_4; +output [`DWIDTH-1:0] matrixC11_5; +output [`DWIDTH-1:0] matrixC11_6; +output [`DWIDTH-1:0] matrixC11_7; +output [`DWIDTH-1:0] matrixC11_8; +output [`DWIDTH-1:0] matrixC11_9; +output [`DWIDTH-1:0] matrixC11_10; +output [`DWIDTH-1:0] matrixC11_11; +output [`DWIDTH-1:0] matrixC11_12; +output [`DWIDTH-1:0] matrixC11_13; +output [`DWIDTH-1:0] matrixC11_14; +output [`DWIDTH-1:0] matrixC11_15; +output [`DWIDTH-1:0] matrixC11_16; +output [`DWIDTH-1:0] matrixC11_17; +output [`DWIDTH-1:0] matrixC11_18; +output [`DWIDTH-1:0] matrixC11_19; +output [`DWIDTH-1:0] matrixC12_0; +output [`DWIDTH-1:0] matrixC12_1; +output [`DWIDTH-1:0] matrixC12_2; +output [`DWIDTH-1:0] matrixC12_3; +output [`DWIDTH-1:0] matrixC12_4; +output [`DWIDTH-1:0] matrixC12_5; +output [`DWIDTH-1:0] matrixC12_6; +output [`DWIDTH-1:0] matrixC12_7; +output [`DWIDTH-1:0] matrixC12_8; +output [`DWIDTH-1:0] matrixC12_9; +output [`DWIDTH-1:0] matrixC12_10; +output [`DWIDTH-1:0] matrixC12_11; +output [`DWIDTH-1:0] matrixC12_12; +output [`DWIDTH-1:0] matrixC12_13; +output [`DWIDTH-1:0] matrixC12_14; +output [`DWIDTH-1:0] matrixC12_15; +output [`DWIDTH-1:0] matrixC12_16; +output [`DWIDTH-1:0] matrixC12_17; +output [`DWIDTH-1:0] matrixC12_18; +output [`DWIDTH-1:0] matrixC12_19; +output [`DWIDTH-1:0] matrixC13_0; +output [`DWIDTH-1:0] matrixC13_1; +output [`DWIDTH-1:0] matrixC13_2; +output [`DWIDTH-1:0] matrixC13_3; +output [`DWIDTH-1:0] matrixC13_4; +output [`DWIDTH-1:0] matrixC13_5; +output [`DWIDTH-1:0] matrixC13_6; +output [`DWIDTH-1:0] matrixC13_7; +output [`DWIDTH-1:0] matrixC13_8; +output [`DWIDTH-1:0] matrixC13_9; +output [`DWIDTH-1:0] matrixC13_10; +output [`DWIDTH-1:0] matrixC13_11; +output [`DWIDTH-1:0] matrixC13_12; +output [`DWIDTH-1:0] matrixC13_13; +output [`DWIDTH-1:0] matrixC13_14; +output [`DWIDTH-1:0] matrixC13_15; +output [`DWIDTH-1:0] matrixC13_16; +output [`DWIDTH-1:0] matrixC13_17; +output [`DWIDTH-1:0] matrixC13_18; +output [`DWIDTH-1:0] matrixC13_19; +output [`DWIDTH-1:0] matrixC14_0; +output [`DWIDTH-1:0] matrixC14_1; +output [`DWIDTH-1:0] matrixC14_2; +output [`DWIDTH-1:0] matrixC14_3; +output [`DWIDTH-1:0] matrixC14_4; +output [`DWIDTH-1:0] matrixC14_5; +output [`DWIDTH-1:0] matrixC14_6; +output [`DWIDTH-1:0] matrixC14_7; +output [`DWIDTH-1:0] matrixC14_8; +output [`DWIDTH-1:0] matrixC14_9; +output [`DWIDTH-1:0] matrixC14_10; +output [`DWIDTH-1:0] matrixC14_11; +output [`DWIDTH-1:0] matrixC14_12; +output [`DWIDTH-1:0] matrixC14_13; +output [`DWIDTH-1:0] matrixC14_14; +output [`DWIDTH-1:0] matrixC14_15; +output [`DWIDTH-1:0] matrixC14_16; +output [`DWIDTH-1:0] matrixC14_17; +output [`DWIDTH-1:0] matrixC14_18; +output [`DWIDTH-1:0] matrixC14_19; +output [`DWIDTH-1:0] matrixC15_0; +output [`DWIDTH-1:0] matrixC15_1; +output [`DWIDTH-1:0] matrixC15_2; +output [`DWIDTH-1:0] matrixC15_3; +output [`DWIDTH-1:0] matrixC15_4; +output [`DWIDTH-1:0] matrixC15_5; +output [`DWIDTH-1:0] matrixC15_6; +output [`DWIDTH-1:0] matrixC15_7; +output [`DWIDTH-1:0] matrixC15_8; +output [`DWIDTH-1:0] matrixC15_9; +output [`DWIDTH-1:0] matrixC15_10; +output [`DWIDTH-1:0] matrixC15_11; +output [`DWIDTH-1:0] matrixC15_12; +output [`DWIDTH-1:0] matrixC15_13; +output [`DWIDTH-1:0] matrixC15_14; +output [`DWIDTH-1:0] matrixC15_15; +output [`DWIDTH-1:0] matrixC15_16; +output [`DWIDTH-1:0] matrixC15_17; +output [`DWIDTH-1:0] matrixC15_18; +output [`DWIDTH-1:0] matrixC15_19; +output [`DWIDTH-1:0] matrixC16_0; +output [`DWIDTH-1:0] matrixC16_1; +output [`DWIDTH-1:0] matrixC16_2; +output [`DWIDTH-1:0] matrixC16_3; +output [`DWIDTH-1:0] matrixC16_4; +output [`DWIDTH-1:0] matrixC16_5; +output [`DWIDTH-1:0] matrixC16_6; +output [`DWIDTH-1:0] matrixC16_7; +output [`DWIDTH-1:0] matrixC16_8; +output [`DWIDTH-1:0] matrixC16_9; +output [`DWIDTH-1:0] matrixC16_10; +output [`DWIDTH-1:0] matrixC16_11; +output [`DWIDTH-1:0] matrixC16_12; +output [`DWIDTH-1:0] matrixC16_13; +output [`DWIDTH-1:0] matrixC16_14; +output [`DWIDTH-1:0] matrixC16_15; +output [`DWIDTH-1:0] matrixC16_16; +output [`DWIDTH-1:0] matrixC16_17; +output [`DWIDTH-1:0] matrixC16_18; +output [`DWIDTH-1:0] matrixC16_19; +output [`DWIDTH-1:0] matrixC17_0; +output [`DWIDTH-1:0] matrixC17_1; +output [`DWIDTH-1:0] matrixC17_2; +output [`DWIDTH-1:0] matrixC17_3; +output [`DWIDTH-1:0] matrixC17_4; +output [`DWIDTH-1:0] matrixC17_5; +output [`DWIDTH-1:0] matrixC17_6; +output [`DWIDTH-1:0] matrixC17_7; +output [`DWIDTH-1:0] matrixC17_8; +output [`DWIDTH-1:0] matrixC17_9; +output [`DWIDTH-1:0] matrixC17_10; +output [`DWIDTH-1:0] matrixC17_11; +output [`DWIDTH-1:0] matrixC17_12; +output [`DWIDTH-1:0] matrixC17_13; +output [`DWIDTH-1:0] matrixC17_14; +output [`DWIDTH-1:0] matrixC17_15; +output [`DWIDTH-1:0] matrixC17_16; +output [`DWIDTH-1:0] matrixC17_17; +output [`DWIDTH-1:0] matrixC17_18; +output [`DWIDTH-1:0] matrixC17_19; +output [`DWIDTH-1:0] matrixC18_0; +output [`DWIDTH-1:0] matrixC18_1; +output [`DWIDTH-1:0] matrixC18_2; +output [`DWIDTH-1:0] matrixC18_3; +output [`DWIDTH-1:0] matrixC18_4; +output [`DWIDTH-1:0] matrixC18_5; +output [`DWIDTH-1:0] matrixC18_6; +output [`DWIDTH-1:0] matrixC18_7; +output [`DWIDTH-1:0] matrixC18_8; +output [`DWIDTH-1:0] matrixC18_9; +output [`DWIDTH-1:0] matrixC18_10; +output [`DWIDTH-1:0] matrixC18_11; +output [`DWIDTH-1:0] matrixC18_12; +output [`DWIDTH-1:0] matrixC18_13; +output [`DWIDTH-1:0] matrixC18_14; +output [`DWIDTH-1:0] matrixC18_15; +output [`DWIDTH-1:0] matrixC18_16; +output [`DWIDTH-1:0] matrixC18_17; +output [`DWIDTH-1:0] matrixC18_18; +output [`DWIDTH-1:0] matrixC18_19; +output [`DWIDTH-1:0] matrixC19_0; +output [`DWIDTH-1:0] matrixC19_1; +output [`DWIDTH-1:0] matrixC19_2; +output [`DWIDTH-1:0] matrixC19_3; +output [`DWIDTH-1:0] matrixC19_4; +output [`DWIDTH-1:0] matrixC19_5; +output [`DWIDTH-1:0] matrixC19_6; +output [`DWIDTH-1:0] matrixC19_7; +output [`DWIDTH-1:0] matrixC19_8; +output [`DWIDTH-1:0] matrixC19_9; +output [`DWIDTH-1:0] matrixC19_10; +output [`DWIDTH-1:0] matrixC19_11; +output [`DWIDTH-1:0] matrixC19_12; +output [`DWIDTH-1:0] matrixC19_13; +output [`DWIDTH-1:0] matrixC19_14; +output [`DWIDTH-1:0] matrixC19_15; +output [`DWIDTH-1:0] matrixC19_16; +output [`DWIDTH-1:0] matrixC19_17; +output [`DWIDTH-1:0] matrixC19_18; +output [`DWIDTH-1:0] matrixC19_19; + +output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + +wire [`DWIDTH-1:0] a0_0to0_1, a0_1to0_2, a0_2to0_3, a0_3to0_4, a0_4to0_5, a0_5to0_6, a0_6to0_7, a0_7to0_8, a0_8to0_9, a0_9to0_10, a0_10to0_11, a0_11to0_12, a0_12to0_13, a0_13to0_14, a0_14to0_15, a0_15to0_16, a0_16to0_17, a0_17to0_18, a0_18to0_19, a0_19to0_20; +wire [`DWIDTH-1:0] a1_0to1_1, a1_1to1_2, a1_2to1_3, a1_3to1_4, a1_4to1_5, a1_5to1_6, a1_6to1_7, a1_7to1_8, a1_8to1_9, a1_9to1_10, a1_10to1_11, a1_11to1_12, a1_12to1_13, a1_13to1_14, a1_14to1_15, a1_15to1_16, a1_16to1_17, a1_17to1_18, a1_18to1_19, a1_19to1_20; +wire [`DWIDTH-1:0] a2_0to2_1, a2_1to2_2, a2_2to2_3, a2_3to2_4, a2_4to2_5, a2_5to2_6, a2_6to2_7, a2_7to2_8, a2_8to2_9, a2_9to2_10, a2_10to2_11, a2_11to2_12, a2_12to2_13, a2_13to2_14, a2_14to2_15, a2_15to2_16, a2_16to2_17, a2_17to2_18, a2_18to2_19, a2_19to2_20; +wire [`DWIDTH-1:0] a3_0to3_1, a3_1to3_2, a3_2to3_3, a3_3to3_4, a3_4to3_5, a3_5to3_6, a3_6to3_7, a3_7to3_8, a3_8to3_9, a3_9to3_10, a3_10to3_11, a3_11to3_12, a3_12to3_13, a3_13to3_14, a3_14to3_15, a3_15to3_16, a3_16to3_17, a3_17to3_18, a3_18to3_19, a3_19to3_20; +wire [`DWIDTH-1:0] a4_0to4_1, a4_1to4_2, a4_2to4_3, a4_3to4_4, a4_4to4_5, a4_5to4_6, a4_6to4_7, a4_7to4_8, a4_8to4_9, a4_9to4_10, a4_10to4_11, a4_11to4_12, a4_12to4_13, a4_13to4_14, a4_14to4_15, a4_15to4_16, a4_16to4_17, a4_17to4_18, a4_18to4_19, a4_19to4_20; +wire [`DWIDTH-1:0] a5_0to5_1, a5_1to5_2, a5_2to5_3, a5_3to5_4, a5_4to5_5, a5_5to5_6, a5_6to5_7, a5_7to5_8, a5_8to5_9, a5_9to5_10, a5_10to5_11, a5_11to5_12, a5_12to5_13, a5_13to5_14, a5_14to5_15, a5_15to5_16, a5_16to5_17, a5_17to5_18, a5_18to5_19, a5_19to5_20; +wire [`DWIDTH-1:0] a6_0to6_1, a6_1to6_2, a6_2to6_3, a6_3to6_4, a6_4to6_5, a6_5to6_6, a6_6to6_7, a6_7to6_8, a6_8to6_9, a6_9to6_10, a6_10to6_11, a6_11to6_12, a6_12to6_13, a6_13to6_14, a6_14to6_15, a6_15to6_16, a6_16to6_17, a6_17to6_18, a6_18to6_19, a6_19to6_20; +wire [`DWIDTH-1:0] a7_0to7_1, a7_1to7_2, a7_2to7_3, a7_3to7_4, a7_4to7_5, a7_5to7_6, a7_6to7_7, a7_7to7_8, a7_8to7_9, a7_9to7_10, a7_10to7_11, a7_11to7_12, a7_12to7_13, a7_13to7_14, a7_14to7_15, a7_15to7_16, a7_16to7_17, a7_17to7_18, a7_18to7_19, a7_19to7_20; +wire [`DWIDTH-1:0] a8_0to8_1, a8_1to8_2, a8_2to8_3, a8_3to8_4, a8_4to8_5, a8_5to8_6, a8_6to8_7, a8_7to8_8, a8_8to8_9, a8_9to8_10, a8_10to8_11, a8_11to8_12, a8_12to8_13, a8_13to8_14, a8_14to8_15, a8_15to8_16, a8_16to8_17, a8_17to8_18, a8_18to8_19, a8_19to8_20; +wire [`DWIDTH-1:0] a9_0to9_1, a9_1to9_2, a9_2to9_3, a9_3to9_4, a9_4to9_5, a9_5to9_6, a9_6to9_7, a9_7to9_8, a9_8to9_9, a9_9to9_10, a9_10to9_11, a9_11to9_12, a9_12to9_13, a9_13to9_14, a9_14to9_15, a9_15to9_16, a9_16to9_17, a9_17to9_18, a9_18to9_19, a9_19to9_20; +wire [`DWIDTH-1:0] a10_0to10_1, a10_1to10_2, a10_2to10_3, a10_3to10_4, a10_4to10_5, a10_5to10_6, a10_6to10_7, a10_7to10_8, a10_8to10_9, a10_9to10_10, a10_10to10_11, a10_11to10_12, a10_12to10_13, a10_13to10_14, a10_14to10_15, a10_15to10_16, a10_16to10_17, a10_17to10_18, a10_18to10_19, a10_19to10_20; +wire [`DWIDTH-1:0] a11_0to11_1, a11_1to11_2, a11_2to11_3, a11_3to11_4, a11_4to11_5, a11_5to11_6, a11_6to11_7, a11_7to11_8, a11_8to11_9, a11_9to11_10, a11_10to11_11, a11_11to11_12, a11_12to11_13, a11_13to11_14, a11_14to11_15, a11_15to11_16, a11_16to11_17, a11_17to11_18, a11_18to11_19, a11_19to11_20; +wire [`DWIDTH-1:0] a12_0to12_1, a12_1to12_2, a12_2to12_3, a12_3to12_4, a12_4to12_5, a12_5to12_6, a12_6to12_7, a12_7to12_8, a12_8to12_9, a12_9to12_10, a12_10to12_11, a12_11to12_12, a12_12to12_13, a12_13to12_14, a12_14to12_15, a12_15to12_16, a12_16to12_17, a12_17to12_18, a12_18to12_19, a12_19to12_20; +wire [`DWIDTH-1:0] a13_0to13_1, a13_1to13_2, a13_2to13_3, a13_3to13_4, a13_4to13_5, a13_5to13_6, a13_6to13_7, a13_7to13_8, a13_8to13_9, a13_9to13_10, a13_10to13_11, a13_11to13_12, a13_12to13_13, a13_13to13_14, a13_14to13_15, a13_15to13_16, a13_16to13_17, a13_17to13_18, a13_18to13_19, a13_19to13_20; +wire [`DWIDTH-1:0] a14_0to14_1, a14_1to14_2, a14_2to14_3, a14_3to14_4, a14_4to14_5, a14_5to14_6, a14_6to14_7, a14_7to14_8, a14_8to14_9, a14_9to14_10, a14_10to14_11, a14_11to14_12, a14_12to14_13, a14_13to14_14, a14_14to14_15, a14_15to14_16, a14_16to14_17, a14_17to14_18, a14_18to14_19, a14_19to14_20; +wire [`DWIDTH-1:0] a15_0to15_1, a15_1to15_2, a15_2to15_3, a15_3to15_4, a15_4to15_5, a15_5to15_6, a15_6to15_7, a15_7to15_8, a15_8to15_9, a15_9to15_10, a15_10to15_11, a15_11to15_12, a15_12to15_13, a15_13to15_14, a15_14to15_15, a15_15to15_16, a15_16to15_17, a15_17to15_18, a15_18to15_19, a15_19to15_20; +wire [`DWIDTH-1:0] a16_0to16_1, a16_1to16_2, a16_2to16_3, a16_3to16_4, a16_4to16_5, a16_5to16_6, a16_6to16_7, a16_7to16_8, a16_8to16_9, a16_9to16_10, a16_10to16_11, a16_11to16_12, a16_12to16_13, a16_13to16_14, a16_14to16_15, a16_15to16_16, a16_16to16_17, a16_17to16_18, a16_18to16_19, a16_19to16_20; +wire [`DWIDTH-1:0] a17_0to17_1, a17_1to17_2, a17_2to17_3, a17_3to17_4, a17_4to17_5, a17_5to17_6, a17_6to17_7, a17_7to17_8, a17_8to17_9, a17_9to17_10, a17_10to17_11, a17_11to17_12, a17_12to17_13, a17_13to17_14, a17_14to17_15, a17_15to17_16, a17_16to17_17, a17_17to17_18, a17_18to17_19, a17_19to17_20; +wire [`DWIDTH-1:0] a18_0to18_1, a18_1to18_2, a18_2to18_3, a18_3to18_4, a18_4to18_5, a18_5to18_6, a18_6to18_7, a18_7to18_8, a18_8to18_9, a18_9to18_10, a18_10to18_11, a18_11to18_12, a18_12to18_13, a18_13to18_14, a18_14to18_15, a18_15to18_16, a18_16to18_17, a18_17to18_18, a18_18to18_19, a18_19to18_20; +wire [`DWIDTH-1:0] a19_0to19_1, a19_1to19_2, a19_2to19_3, a19_3to19_4, a19_4to19_5, a19_5to19_6, a19_6to19_7, a19_7to19_8, a19_8to19_9, a19_9to19_10, a19_10to19_11, a19_11to19_12, a19_12to19_13, a19_13to19_14, a19_14to19_15, a19_15to19_16, a19_16to19_17, a19_17to19_18, a19_18to19_19, a19_19to19_20; + +wire [`DWIDTH-1:0] b0_0to1_0, b1_0to2_0, b2_0to3_0, b3_0to4_0, b4_0to5_0, b5_0to6_0, b6_0to7_0, b7_0to8_0, b8_0to9_0, b9_0to10_0, b10_0to11_0, b11_0to12_0, b12_0to13_0, b13_0to14_0, b14_0to15_0, b15_0to16_0, b16_0to17_0, b17_0to18_0, b18_0to19_0, b19_0to20_0; +wire [`DWIDTH-1:0] b0_1to1_1, b1_1to2_1, b2_1to3_1, b3_1to4_1, b4_1to5_1, b5_1to6_1, b6_1to7_1, b7_1to8_1, b8_1to9_1, b9_1to10_1, b10_1to11_1, b11_1to12_1, b12_1to13_1, b13_1to14_1, b14_1to15_1, b15_1to16_1, b16_1to17_1, b17_1to18_1, b18_1to19_1, b19_1to20_1; +wire [`DWIDTH-1:0] b0_2to1_2, b1_2to2_2, b2_2to3_2, b3_2to4_2, b4_2to5_2, b5_2to6_2, b6_2to7_2, b7_2to8_2, b8_2to9_2, b9_2to10_2, b10_2to11_2, b11_2to12_2, b12_2to13_2, b13_2to14_2, b14_2to15_2, b15_2to16_2, b16_2to17_2, b17_2to18_2, b18_2to19_2, b19_2to20_2; +wire [`DWIDTH-1:0] b0_3to1_3, b1_3to2_3, b2_3to3_3, b3_3to4_3, b4_3to5_3, b5_3to6_3, b6_3to7_3, b7_3to8_3, b8_3to9_3, b9_3to10_3, b10_3to11_3, b11_3to12_3, b12_3to13_3, b13_3to14_3, b14_3to15_3, b15_3to16_3, b16_3to17_3, b17_3to18_3, b18_3to19_3, b19_3to20_3; +wire [`DWIDTH-1:0] b0_4to1_4, b1_4to2_4, b2_4to3_4, b3_4to4_4, b4_4to5_4, b5_4to6_4, b6_4to7_4, b7_4to8_4, b8_4to9_4, b9_4to10_4, b10_4to11_4, b11_4to12_4, b12_4to13_4, b13_4to14_4, b14_4to15_4, b15_4to16_4, b16_4to17_4, b17_4to18_4, b18_4to19_4, b19_4to20_4; +wire [`DWIDTH-1:0] b0_5to1_5, b1_5to2_5, b2_5to3_5, b3_5to4_5, b4_5to5_5, b5_5to6_5, b6_5to7_5, b7_5to8_5, b8_5to9_5, b9_5to10_5, b10_5to11_5, b11_5to12_5, b12_5to13_5, b13_5to14_5, b14_5to15_5, b15_5to16_5, b16_5to17_5, b17_5to18_5, b18_5to19_5, b19_5to20_5; +wire [`DWIDTH-1:0] b0_6to1_6, b1_6to2_6, b2_6to3_6, b3_6to4_6, b4_6to5_6, b5_6to6_6, b6_6to7_6, b7_6to8_6, b8_6to9_6, b9_6to10_6, b10_6to11_6, b11_6to12_6, b12_6to13_6, b13_6to14_6, b14_6to15_6, b15_6to16_6, b16_6to17_6, b17_6to18_6, b18_6to19_6, b19_6to20_6; +wire [`DWIDTH-1:0] b0_7to1_7, b1_7to2_7, b2_7to3_7, b3_7to4_7, b4_7to5_7, b5_7to6_7, b6_7to7_7, b7_7to8_7, b8_7to9_7, b9_7to10_7, b10_7to11_7, b11_7to12_7, b12_7to13_7, b13_7to14_7, b14_7to15_7, b15_7to16_7, b16_7to17_7, b17_7to18_7, b18_7to19_7, b19_7to20_7; +wire [`DWIDTH-1:0] b0_8to1_8, b1_8to2_8, b2_8to3_8, b3_8to4_8, b4_8to5_8, b5_8to6_8, b6_8to7_8, b7_8to8_8, b8_8to9_8, b9_8to10_8, b10_8to11_8, b11_8to12_8, b12_8to13_8, b13_8to14_8, b14_8to15_8, b15_8to16_8, b16_8to17_8, b17_8to18_8, b18_8to19_8, b19_8to20_8; +wire [`DWIDTH-1:0] b0_9to1_9, b1_9to2_9, b2_9to3_9, b3_9to4_9, b4_9to5_9, b5_9to6_9, b6_9to7_9, b7_9to8_9, b8_9to9_9, b9_9to10_9, b10_9to11_9, b11_9to12_9, b12_9to13_9, b13_9to14_9, b14_9to15_9, b15_9to16_9, b16_9to17_9, b17_9to18_9, b18_9to19_9, b19_9to20_9; +wire [`DWIDTH-1:0] b0_10to1_10, b1_10to2_10, b2_10to3_10, b3_10to4_10, b4_10to5_10, b5_10to6_10, b6_10to7_10, b7_10to8_10, b8_10to9_10, b9_10to10_10, b10_10to11_10, b11_10to12_10, b12_10to13_10, b13_10to14_10, b14_10to15_10, b15_10to16_10, b16_10to17_10, b17_10to18_10, b18_10to19_10, b19_10to20_10; +wire [`DWIDTH-1:0] b0_11to1_11, b1_11to2_11, b2_11to3_11, b3_11to4_11, b4_11to5_11, b5_11to6_11, b6_11to7_11, b7_11to8_11, b8_11to9_11, b9_11to10_11, b10_11to11_11, b11_11to12_11, b12_11to13_11, b13_11to14_11, b14_11to15_11, b15_11to16_11, b16_11to17_11, b17_11to18_11, b18_11to19_11, b19_11to20_11; +wire [`DWIDTH-1:0] b0_12to1_12, b1_12to2_12, b2_12to3_12, b3_12to4_12, b4_12to5_12, b5_12to6_12, b6_12to7_12, b7_12to8_12, b8_12to9_12, b9_12to10_12, b10_12to11_12, b11_12to12_12, b12_12to13_12, b13_12to14_12, b14_12to15_12, b15_12to16_12, b16_12to17_12, b17_12to18_12, b18_12to19_12, b19_12to20_12; +wire [`DWIDTH-1:0] b0_13to1_13, b1_13to2_13, b2_13to3_13, b3_13to4_13, b4_13to5_13, b5_13to6_13, b6_13to7_13, b7_13to8_13, b8_13to9_13, b9_13to10_13, b10_13to11_13, b11_13to12_13, b12_13to13_13, b13_13to14_13, b14_13to15_13, b15_13to16_13, b16_13to17_13, b17_13to18_13, b18_13to19_13, b19_13to20_13; +wire [`DWIDTH-1:0] b0_14to1_14, b1_14to2_14, b2_14to3_14, b3_14to4_14, b4_14to5_14, b5_14to6_14, b6_14to7_14, b7_14to8_14, b8_14to9_14, b9_14to10_14, b10_14to11_14, b11_14to12_14, b12_14to13_14, b13_14to14_14, b14_14to15_14, b15_14to16_14, b16_14to17_14, b17_14to18_14, b18_14to19_14, b19_14to20_14; +wire [`DWIDTH-1:0] b0_15to1_15, b1_15to2_15, b2_15to3_15, b3_15to4_15, b4_15to5_15, b5_15to6_15, b6_15to7_15, b7_15to8_15, b8_15to9_15, b9_15to10_15, b10_15to11_15, b11_15to12_15, b12_15to13_15, b13_15to14_15, b14_15to15_15, b15_15to16_15, b16_15to17_15, b17_15to18_15, b18_15to19_15, b19_15to20_15; +wire [`DWIDTH-1:0] b0_16to1_16, b1_16to2_16, b2_16to3_16, b3_16to4_16, b4_16to5_16, b5_16to6_16, b6_16to7_16, b7_16to8_16, b8_16to9_16, b9_16to10_16, b10_16to11_16, b11_16to12_16, b12_16to13_16, b13_16to14_16, b14_16to15_16, b15_16to16_16, b16_16to17_16, b17_16to18_16, b18_16to19_16, b19_16to20_16; +wire [`DWIDTH-1:0] b0_17to1_17, b1_17to2_17, b2_17to3_17, b3_17to4_17, b4_17to5_17, b5_17to6_17, b6_17to7_17, b7_17to8_17, b8_17to9_17, b9_17to10_17, b10_17to11_17, b11_17to12_17, b12_17to13_17, b13_17to14_17, b14_17to15_17, b15_17to16_17, b16_17to17_17, b17_17to18_17, b18_17to19_17, b19_17to20_17; +wire [`DWIDTH-1:0] b0_18to1_18, b1_18to2_18, b2_18to3_18, b3_18to4_18, b4_18to5_18, b5_18to6_18, b6_18to7_18, b7_18to8_18, b8_18to9_18, b9_18to10_18, b10_18to11_18, b11_18to12_18, b12_18to13_18, b13_18to14_18, b14_18to15_18, b15_18to16_18, b16_18to17_18, b17_18to18_18, b18_18to19_18, b19_18to20_18; +wire [`DWIDTH-1:0] b0_19to1_19, b1_19to2_19, b2_19to3_19, b3_19to4_19, b4_19to5_19, b5_19to6_19, b6_19to7_19, b7_19to8_19, b8_19to9_19, b9_19to10_19, b10_19to11_19, b11_19to12_19, b12_19to13_19, b13_19to14_19, b14_19to15_19, b15_19to16_19, b16_19to17_19, b17_19to18_19, b18_19to19_19, b19_19to20_19; + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +//For larger matmul, more PEs will be needed +wire effective_rst; +assign effective_rst = reset | pe_reset; + +processing_element pe0_0(.reset(effective_rst), .clk(clk), .in_a(a0), .in_b(b0), .out_a(a0_0to0_1), .out_b(b0_0to1_0), .out_c(matrixC0_0)); +processing_element pe0_1(.reset(effective_rst), .clk(clk), .in_a(a0_0to0_1), .in_b(b1), .out_a(a0_1to0_2), .out_b(b0_1to1_1), .out_c(matrixC0_1)); +processing_element pe0_2(.reset(effective_rst), .clk(clk), .in_a(a0_1to0_2), .in_b(b2), .out_a(a0_2to0_3), .out_b(b0_2to1_2), .out_c(matrixC0_2)); +processing_element pe0_3(.reset(effective_rst), .clk(clk), .in_a(a0_2to0_3), .in_b(b3), .out_a(a0_3to0_4), .out_b(b0_3to1_3), .out_c(matrixC0_3)); +processing_element pe0_4(.reset(effective_rst), .clk(clk), .in_a(a0_3to0_4), .in_b(b4), .out_a(a0_4to0_5), .out_b(b0_4to1_4), .out_c(matrixC0_4)); +processing_element pe0_5(.reset(effective_rst), .clk(clk), .in_a(a0_4to0_5), .in_b(b5), .out_a(a0_5to0_6), .out_b(b0_5to1_5), .out_c(matrixC0_5)); +processing_element pe0_6(.reset(effective_rst), .clk(clk), .in_a(a0_5to0_6), .in_b(b6), .out_a(a0_6to0_7), .out_b(b0_6to1_6), .out_c(matrixC0_6)); +processing_element pe0_7(.reset(effective_rst), .clk(clk), .in_a(a0_6to0_7), .in_b(b7), .out_a(a0_7to0_8), .out_b(b0_7to1_7), .out_c(matrixC0_7)); +processing_element pe0_8(.reset(effective_rst), .clk(clk), .in_a(a0_7to0_8), .in_b(b8), .out_a(a0_8to0_9), .out_b(b0_8to1_8), .out_c(matrixC0_8)); +processing_element pe0_9(.reset(effective_rst), .clk(clk), .in_a(a0_8to0_9), .in_b(b9), .out_a(a0_9to0_10), .out_b(b0_9to1_9), .out_c(matrixC0_9)); +processing_element pe0_10(.reset(effective_rst), .clk(clk), .in_a(a0_9to0_10), .in_b(b10), .out_a(a0_10to0_11), .out_b(b0_10to1_10), .out_c(matrixC0_10)); +processing_element pe0_11(.reset(effective_rst), .clk(clk), .in_a(a0_10to0_11), .in_b(b11), .out_a(a0_11to0_12), .out_b(b0_11to1_11), .out_c(matrixC0_11)); +processing_element pe0_12(.reset(effective_rst), .clk(clk), .in_a(a0_11to0_12), .in_b(b12), .out_a(a0_12to0_13), .out_b(b0_12to1_12), .out_c(matrixC0_12)); +processing_element pe0_13(.reset(effective_rst), .clk(clk), .in_a(a0_12to0_13), .in_b(b13), .out_a(a0_13to0_14), .out_b(b0_13to1_13), .out_c(matrixC0_13)); +processing_element pe0_14(.reset(effective_rst), .clk(clk), .in_a(a0_13to0_14), .in_b(b14), .out_a(a0_14to0_15), .out_b(b0_14to1_14), .out_c(matrixC0_14)); +processing_element pe0_15(.reset(effective_rst), .clk(clk), .in_a(a0_14to0_15), .in_b(b15), .out_a(a0_15to0_16), .out_b(b0_15to1_15), .out_c(matrixC0_15)); +processing_element pe0_16(.reset(effective_rst), .clk(clk), .in_a(a0_15to0_16), .in_b(b16), .out_a(a0_16to0_17), .out_b(b0_16to1_16), .out_c(matrixC0_16)); +processing_element pe0_17(.reset(effective_rst), .clk(clk), .in_a(a0_16to0_17), .in_b(b17), .out_a(a0_17to0_18), .out_b(b0_17to1_17), .out_c(matrixC0_17)); +processing_element pe0_18(.reset(effective_rst), .clk(clk), .in_a(a0_17to0_18), .in_b(b18), .out_a(a0_18to0_19), .out_b(b0_18to1_18), .out_c(matrixC0_18)); +processing_element pe0_19(.reset(effective_rst), .clk(clk), .in_a(a0_18to0_19), .in_b(b19), .out_a(a0_19to0_20), .out_b(b0_19to1_19), .out_c(matrixC0_19)); + +processing_element pe1_0(.reset(effective_rst), .clk(clk), .in_a(a1), .in_b(b0_0to1_0), .out_a(a1_0to1_1), .out_b(b1_0to2_0), .out_c(matrixC1_0)); +processing_element pe2_0(.reset(effective_rst), .clk(clk), .in_a(a2), .in_b(b1_0to2_0), .out_a(a2_0to2_1), .out_b(b2_0to3_0), .out_c(matrixC2_0)); +processing_element pe3_0(.reset(effective_rst), .clk(clk), .in_a(a3), .in_b(b2_0to3_0), .out_a(a3_0to3_1), .out_b(b3_0to4_0), .out_c(matrixC3_0)); +processing_element pe4_0(.reset(effective_rst), .clk(clk), .in_a(a4), .in_b(b3_0to4_0), .out_a(a4_0to4_1), .out_b(b4_0to5_0), .out_c(matrixC4_0)); +processing_element pe5_0(.reset(effective_rst), .clk(clk), .in_a(a5), .in_b(b4_0to5_0), .out_a(a5_0to5_1), .out_b(b5_0to6_0), .out_c(matrixC5_0)); +processing_element pe6_0(.reset(effective_rst), .clk(clk), .in_a(a6), .in_b(b5_0to6_0), .out_a(a6_0to6_1), .out_b(b6_0to7_0), .out_c(matrixC6_0)); +processing_element pe7_0(.reset(effective_rst), .clk(clk), .in_a(a7), .in_b(b6_0to7_0), .out_a(a7_0to7_1), .out_b(b7_0to8_0), .out_c(matrixC7_0)); +processing_element pe8_0(.reset(effective_rst), .clk(clk), .in_a(a8), .in_b(b7_0to8_0), .out_a(a8_0to8_1), .out_b(b8_0to9_0), .out_c(matrixC8_0)); +processing_element pe9_0(.reset(effective_rst), .clk(clk), .in_a(a9), .in_b(b8_0to9_0), .out_a(a9_0to9_1), .out_b(b9_0to10_0), .out_c(matrixC9_0)); +processing_element pe10_0(.reset(effective_rst), .clk(clk), .in_a(a10), .in_b(b9_0to10_0), .out_a(a10_0to10_1), .out_b(b10_0to11_0), .out_c(matrixC10_0)); +processing_element pe11_0(.reset(effective_rst), .clk(clk), .in_a(a11), .in_b(b10_0to11_0), .out_a(a11_0to11_1), .out_b(b11_0to12_0), .out_c(matrixC11_0)); +processing_element pe12_0(.reset(effective_rst), .clk(clk), .in_a(a12), .in_b(b11_0to12_0), .out_a(a12_0to12_1), .out_b(b12_0to13_0), .out_c(matrixC12_0)); +processing_element pe13_0(.reset(effective_rst), .clk(clk), .in_a(a13), .in_b(b12_0to13_0), .out_a(a13_0to13_1), .out_b(b13_0to14_0), .out_c(matrixC13_0)); +processing_element pe14_0(.reset(effective_rst), .clk(clk), .in_a(a14), .in_b(b13_0to14_0), .out_a(a14_0to14_1), .out_b(b14_0to15_0), .out_c(matrixC14_0)); +processing_element pe15_0(.reset(effective_rst), .clk(clk), .in_a(a15), .in_b(b14_0to15_0), .out_a(a15_0to15_1), .out_b(b15_0to16_0), .out_c(matrixC15_0)); +processing_element pe16_0(.reset(effective_rst), .clk(clk), .in_a(a16), .in_b(b15_0to16_0), .out_a(a16_0to16_1), .out_b(b16_0to17_0), .out_c(matrixC16_0)); +processing_element pe17_0(.reset(effective_rst), .clk(clk), .in_a(a17), .in_b(b16_0to17_0), .out_a(a17_0to17_1), .out_b(b17_0to18_0), .out_c(matrixC17_0)); +processing_element pe18_0(.reset(effective_rst), .clk(clk), .in_a(a18), .in_b(b17_0to18_0), .out_a(a18_0to18_1), .out_b(b18_0to19_0), .out_c(matrixC18_0)); +processing_element pe19_0(.reset(effective_rst), .clk(clk), .in_a(a19), .in_b(b18_0to19_0), .out_a(a19_0to19_1), .out_b(b19_0to20_0), .out_c(matrixC19_0)); + +processing_element pe1_1(.reset(effective_rst), .clk(clk), .in_a(a1_0to1_1), .in_b(b0_1to1_1), .out_a(a1_1to1_2), .out_b(b1_1to2_1), .out_c(matrixC1_1)); +processing_element pe1_2(.reset(effective_rst), .clk(clk), .in_a(a1_1to1_2), .in_b(b0_2to1_2), .out_a(a1_2to1_3), .out_b(b1_2to2_2), .out_c(matrixC1_2)); +processing_element pe1_3(.reset(effective_rst), .clk(clk), .in_a(a1_2to1_3), .in_b(b0_3to1_3), .out_a(a1_3to1_4), .out_b(b1_3to2_3), .out_c(matrixC1_3)); +processing_element pe1_4(.reset(effective_rst), .clk(clk), .in_a(a1_3to1_4), .in_b(b0_4to1_4), .out_a(a1_4to1_5), .out_b(b1_4to2_4), .out_c(matrixC1_4)); +processing_element pe1_5(.reset(effective_rst), .clk(clk), .in_a(a1_4to1_5), .in_b(b0_5to1_5), .out_a(a1_5to1_6), .out_b(b1_5to2_5), .out_c(matrixC1_5)); +processing_element pe1_6(.reset(effective_rst), .clk(clk), .in_a(a1_5to1_6), .in_b(b0_6to1_6), .out_a(a1_6to1_7), .out_b(b1_6to2_6), .out_c(matrixC1_6)); +processing_element pe1_7(.reset(effective_rst), .clk(clk), .in_a(a1_6to1_7), .in_b(b0_7to1_7), .out_a(a1_7to1_8), .out_b(b1_7to2_7), .out_c(matrixC1_7)); +processing_element pe1_8(.reset(effective_rst), .clk(clk), .in_a(a1_7to1_8), .in_b(b0_8to1_8), .out_a(a1_8to1_9), .out_b(b1_8to2_8), .out_c(matrixC1_8)); +processing_element pe1_9(.reset(effective_rst), .clk(clk), .in_a(a1_8to1_9), .in_b(b0_9to1_9), .out_a(a1_9to1_10), .out_b(b1_9to2_9), .out_c(matrixC1_9)); +processing_element pe1_10(.reset(effective_rst), .clk(clk), .in_a(a1_9to1_10), .in_b(b0_10to1_10), .out_a(a1_10to1_11), .out_b(b1_10to2_10), .out_c(matrixC1_10)); +processing_element pe1_11(.reset(effective_rst), .clk(clk), .in_a(a1_10to1_11), .in_b(b0_11to1_11), .out_a(a1_11to1_12), .out_b(b1_11to2_11), .out_c(matrixC1_11)); +processing_element pe1_12(.reset(effective_rst), .clk(clk), .in_a(a1_11to1_12), .in_b(b0_12to1_12), .out_a(a1_12to1_13), .out_b(b1_12to2_12), .out_c(matrixC1_12)); +processing_element pe1_13(.reset(effective_rst), .clk(clk), .in_a(a1_12to1_13), .in_b(b0_13to1_13), .out_a(a1_13to1_14), .out_b(b1_13to2_13), .out_c(matrixC1_13)); +processing_element pe1_14(.reset(effective_rst), .clk(clk), .in_a(a1_13to1_14), .in_b(b0_14to1_14), .out_a(a1_14to1_15), .out_b(b1_14to2_14), .out_c(matrixC1_14)); +processing_element pe1_15(.reset(effective_rst), .clk(clk), .in_a(a1_14to1_15), .in_b(b0_15to1_15), .out_a(a1_15to1_16), .out_b(b1_15to2_15), .out_c(matrixC1_15)); +processing_element pe1_16(.reset(effective_rst), .clk(clk), .in_a(a1_15to1_16), .in_b(b0_16to1_16), .out_a(a1_16to1_17), .out_b(b1_16to2_16), .out_c(matrixC1_16)); +processing_element pe1_17(.reset(effective_rst), .clk(clk), .in_a(a1_16to1_17), .in_b(b0_17to1_17), .out_a(a1_17to1_18), .out_b(b1_17to2_17), .out_c(matrixC1_17)); +processing_element pe1_18(.reset(effective_rst), .clk(clk), .in_a(a1_17to1_18), .in_b(b0_18to1_18), .out_a(a1_18to1_19), .out_b(b1_18to2_18), .out_c(matrixC1_18)); +processing_element pe1_19(.reset(effective_rst), .clk(clk), .in_a(a1_18to1_19), .in_b(b0_19to1_19), .out_a(a1_19to1_20), .out_b(b1_19to2_19), .out_c(matrixC1_19)); +processing_element pe2_1(.reset(effective_rst), .clk(clk), .in_a(a2_0to2_1), .in_b(b1_1to2_1), .out_a(a2_1to2_2), .out_b(b2_1to3_1), .out_c(matrixC2_1)); +processing_element pe2_2(.reset(effective_rst), .clk(clk), .in_a(a2_1to2_2), .in_b(b1_2to2_2), .out_a(a2_2to2_3), .out_b(b2_2to3_2), .out_c(matrixC2_2)); +processing_element pe2_3(.reset(effective_rst), .clk(clk), .in_a(a2_2to2_3), .in_b(b1_3to2_3), .out_a(a2_3to2_4), .out_b(b2_3to3_3), .out_c(matrixC2_3)); +processing_element pe2_4(.reset(effective_rst), .clk(clk), .in_a(a2_3to2_4), .in_b(b1_4to2_4), .out_a(a2_4to2_5), .out_b(b2_4to3_4), .out_c(matrixC2_4)); +processing_element pe2_5(.reset(effective_rst), .clk(clk), .in_a(a2_4to2_5), .in_b(b1_5to2_5), .out_a(a2_5to2_6), .out_b(b2_5to3_5), .out_c(matrixC2_5)); +processing_element pe2_6(.reset(effective_rst), .clk(clk), .in_a(a2_5to2_6), .in_b(b1_6to2_6), .out_a(a2_6to2_7), .out_b(b2_6to3_6), .out_c(matrixC2_6)); +processing_element pe2_7(.reset(effective_rst), .clk(clk), .in_a(a2_6to2_7), .in_b(b1_7to2_7), .out_a(a2_7to2_8), .out_b(b2_7to3_7), .out_c(matrixC2_7)); +processing_element pe2_8(.reset(effective_rst), .clk(clk), .in_a(a2_7to2_8), .in_b(b1_8to2_8), .out_a(a2_8to2_9), .out_b(b2_8to3_8), .out_c(matrixC2_8)); +processing_element pe2_9(.reset(effective_rst), .clk(clk), .in_a(a2_8to2_9), .in_b(b1_9to2_9), .out_a(a2_9to2_10), .out_b(b2_9to3_9), .out_c(matrixC2_9)); +processing_element pe2_10(.reset(effective_rst), .clk(clk), .in_a(a2_9to2_10), .in_b(b1_10to2_10), .out_a(a2_10to2_11), .out_b(b2_10to3_10), .out_c(matrixC2_10)); +processing_element pe2_11(.reset(effective_rst), .clk(clk), .in_a(a2_10to2_11), .in_b(b1_11to2_11), .out_a(a2_11to2_12), .out_b(b2_11to3_11), .out_c(matrixC2_11)); +processing_element pe2_12(.reset(effective_rst), .clk(clk), .in_a(a2_11to2_12), .in_b(b1_12to2_12), .out_a(a2_12to2_13), .out_b(b2_12to3_12), .out_c(matrixC2_12)); +processing_element pe2_13(.reset(effective_rst), .clk(clk), .in_a(a2_12to2_13), .in_b(b1_13to2_13), .out_a(a2_13to2_14), .out_b(b2_13to3_13), .out_c(matrixC2_13)); +processing_element pe2_14(.reset(effective_rst), .clk(clk), .in_a(a2_13to2_14), .in_b(b1_14to2_14), .out_a(a2_14to2_15), .out_b(b2_14to3_14), .out_c(matrixC2_14)); +processing_element pe2_15(.reset(effective_rst), .clk(clk), .in_a(a2_14to2_15), .in_b(b1_15to2_15), .out_a(a2_15to2_16), .out_b(b2_15to3_15), .out_c(matrixC2_15)); +processing_element pe2_16(.reset(effective_rst), .clk(clk), .in_a(a2_15to2_16), .in_b(b1_16to2_16), .out_a(a2_16to2_17), .out_b(b2_16to3_16), .out_c(matrixC2_16)); +processing_element pe2_17(.reset(effective_rst), .clk(clk), .in_a(a2_16to2_17), .in_b(b1_17to2_17), .out_a(a2_17to2_18), .out_b(b2_17to3_17), .out_c(matrixC2_17)); +processing_element pe2_18(.reset(effective_rst), .clk(clk), .in_a(a2_17to2_18), .in_b(b1_18to2_18), .out_a(a2_18to2_19), .out_b(b2_18to3_18), .out_c(matrixC2_18)); +processing_element pe2_19(.reset(effective_rst), .clk(clk), .in_a(a2_18to2_19), .in_b(b1_19to2_19), .out_a(a2_19to2_20), .out_b(b2_19to3_19), .out_c(matrixC2_19)); +processing_element pe3_1(.reset(effective_rst), .clk(clk), .in_a(a3_0to3_1), .in_b(b2_1to3_1), .out_a(a3_1to3_2), .out_b(b3_1to4_1), .out_c(matrixC3_1)); +processing_element pe3_2(.reset(effective_rst), .clk(clk), .in_a(a3_1to3_2), .in_b(b2_2to3_2), .out_a(a3_2to3_3), .out_b(b3_2to4_2), .out_c(matrixC3_2)); +processing_element pe3_3(.reset(effective_rst), .clk(clk), .in_a(a3_2to3_3), .in_b(b2_3to3_3), .out_a(a3_3to3_4), .out_b(b3_3to4_3), .out_c(matrixC3_3)); +processing_element pe3_4(.reset(effective_rst), .clk(clk), .in_a(a3_3to3_4), .in_b(b2_4to3_4), .out_a(a3_4to3_5), .out_b(b3_4to4_4), .out_c(matrixC3_4)); +processing_element pe3_5(.reset(effective_rst), .clk(clk), .in_a(a3_4to3_5), .in_b(b2_5to3_5), .out_a(a3_5to3_6), .out_b(b3_5to4_5), .out_c(matrixC3_5)); +processing_element pe3_6(.reset(effective_rst), .clk(clk), .in_a(a3_5to3_6), .in_b(b2_6to3_6), .out_a(a3_6to3_7), .out_b(b3_6to4_6), .out_c(matrixC3_6)); +processing_element pe3_7(.reset(effective_rst), .clk(clk), .in_a(a3_6to3_7), .in_b(b2_7to3_7), .out_a(a3_7to3_8), .out_b(b3_7to4_7), .out_c(matrixC3_7)); +processing_element pe3_8(.reset(effective_rst), .clk(clk), .in_a(a3_7to3_8), .in_b(b2_8to3_8), .out_a(a3_8to3_9), .out_b(b3_8to4_8), .out_c(matrixC3_8)); +processing_element pe3_9(.reset(effective_rst), .clk(clk), .in_a(a3_8to3_9), .in_b(b2_9to3_9), .out_a(a3_9to3_10), .out_b(b3_9to4_9), .out_c(matrixC3_9)); +processing_element pe3_10(.reset(effective_rst), .clk(clk), .in_a(a3_9to3_10), .in_b(b2_10to3_10), .out_a(a3_10to3_11), .out_b(b3_10to4_10), .out_c(matrixC3_10)); +processing_element pe3_11(.reset(effective_rst), .clk(clk), .in_a(a3_10to3_11), .in_b(b2_11to3_11), .out_a(a3_11to3_12), .out_b(b3_11to4_11), .out_c(matrixC3_11)); +processing_element pe3_12(.reset(effective_rst), .clk(clk), .in_a(a3_11to3_12), .in_b(b2_12to3_12), .out_a(a3_12to3_13), .out_b(b3_12to4_12), .out_c(matrixC3_12)); +processing_element pe3_13(.reset(effective_rst), .clk(clk), .in_a(a3_12to3_13), .in_b(b2_13to3_13), .out_a(a3_13to3_14), .out_b(b3_13to4_13), .out_c(matrixC3_13)); +processing_element pe3_14(.reset(effective_rst), .clk(clk), .in_a(a3_13to3_14), .in_b(b2_14to3_14), .out_a(a3_14to3_15), .out_b(b3_14to4_14), .out_c(matrixC3_14)); +processing_element pe3_15(.reset(effective_rst), .clk(clk), .in_a(a3_14to3_15), .in_b(b2_15to3_15), .out_a(a3_15to3_16), .out_b(b3_15to4_15), .out_c(matrixC3_15)); +processing_element pe3_16(.reset(effective_rst), .clk(clk), .in_a(a3_15to3_16), .in_b(b2_16to3_16), .out_a(a3_16to3_17), .out_b(b3_16to4_16), .out_c(matrixC3_16)); +processing_element pe3_17(.reset(effective_rst), .clk(clk), .in_a(a3_16to3_17), .in_b(b2_17to3_17), .out_a(a3_17to3_18), .out_b(b3_17to4_17), .out_c(matrixC3_17)); +processing_element pe3_18(.reset(effective_rst), .clk(clk), .in_a(a3_17to3_18), .in_b(b2_18to3_18), .out_a(a3_18to3_19), .out_b(b3_18to4_18), .out_c(matrixC3_18)); +processing_element pe3_19(.reset(effective_rst), .clk(clk), .in_a(a3_18to3_19), .in_b(b2_19to3_19), .out_a(a3_19to3_20), .out_b(b3_19to4_19), .out_c(matrixC3_19)); +processing_element pe4_1(.reset(effective_rst), .clk(clk), .in_a(a4_0to4_1), .in_b(b3_1to4_1), .out_a(a4_1to4_2), .out_b(b4_1to5_1), .out_c(matrixC4_1)); +processing_element pe4_2(.reset(effective_rst), .clk(clk), .in_a(a4_1to4_2), .in_b(b3_2to4_2), .out_a(a4_2to4_3), .out_b(b4_2to5_2), .out_c(matrixC4_2)); +processing_element pe4_3(.reset(effective_rst), .clk(clk), .in_a(a4_2to4_3), .in_b(b3_3to4_3), .out_a(a4_3to4_4), .out_b(b4_3to5_3), .out_c(matrixC4_3)); +processing_element pe4_4(.reset(effective_rst), .clk(clk), .in_a(a4_3to4_4), .in_b(b3_4to4_4), .out_a(a4_4to4_5), .out_b(b4_4to5_4), .out_c(matrixC4_4)); +processing_element pe4_5(.reset(effective_rst), .clk(clk), .in_a(a4_4to4_5), .in_b(b3_5to4_5), .out_a(a4_5to4_6), .out_b(b4_5to5_5), .out_c(matrixC4_5)); +processing_element pe4_6(.reset(effective_rst), .clk(clk), .in_a(a4_5to4_6), .in_b(b3_6to4_6), .out_a(a4_6to4_7), .out_b(b4_6to5_6), .out_c(matrixC4_6)); +processing_element pe4_7(.reset(effective_rst), .clk(clk), .in_a(a4_6to4_7), .in_b(b3_7to4_7), .out_a(a4_7to4_8), .out_b(b4_7to5_7), .out_c(matrixC4_7)); +processing_element pe4_8(.reset(effective_rst), .clk(clk), .in_a(a4_7to4_8), .in_b(b3_8to4_8), .out_a(a4_8to4_9), .out_b(b4_8to5_8), .out_c(matrixC4_8)); +processing_element pe4_9(.reset(effective_rst), .clk(clk), .in_a(a4_8to4_9), .in_b(b3_9to4_9), .out_a(a4_9to4_10), .out_b(b4_9to5_9), .out_c(matrixC4_9)); +processing_element pe4_10(.reset(effective_rst), .clk(clk), .in_a(a4_9to4_10), .in_b(b3_10to4_10), .out_a(a4_10to4_11), .out_b(b4_10to5_10), .out_c(matrixC4_10)); +processing_element pe4_11(.reset(effective_rst), .clk(clk), .in_a(a4_10to4_11), .in_b(b3_11to4_11), .out_a(a4_11to4_12), .out_b(b4_11to5_11), .out_c(matrixC4_11)); +processing_element pe4_12(.reset(effective_rst), .clk(clk), .in_a(a4_11to4_12), .in_b(b3_12to4_12), .out_a(a4_12to4_13), .out_b(b4_12to5_12), .out_c(matrixC4_12)); +processing_element pe4_13(.reset(effective_rst), .clk(clk), .in_a(a4_12to4_13), .in_b(b3_13to4_13), .out_a(a4_13to4_14), .out_b(b4_13to5_13), .out_c(matrixC4_13)); +processing_element pe4_14(.reset(effective_rst), .clk(clk), .in_a(a4_13to4_14), .in_b(b3_14to4_14), .out_a(a4_14to4_15), .out_b(b4_14to5_14), .out_c(matrixC4_14)); +processing_element pe4_15(.reset(effective_rst), .clk(clk), .in_a(a4_14to4_15), .in_b(b3_15to4_15), .out_a(a4_15to4_16), .out_b(b4_15to5_15), .out_c(matrixC4_15)); +processing_element pe4_16(.reset(effective_rst), .clk(clk), .in_a(a4_15to4_16), .in_b(b3_16to4_16), .out_a(a4_16to4_17), .out_b(b4_16to5_16), .out_c(matrixC4_16)); +processing_element pe4_17(.reset(effective_rst), .clk(clk), .in_a(a4_16to4_17), .in_b(b3_17to4_17), .out_a(a4_17to4_18), .out_b(b4_17to5_17), .out_c(matrixC4_17)); +processing_element pe4_18(.reset(effective_rst), .clk(clk), .in_a(a4_17to4_18), .in_b(b3_18to4_18), .out_a(a4_18to4_19), .out_b(b4_18to5_18), .out_c(matrixC4_18)); +processing_element pe4_19(.reset(effective_rst), .clk(clk), .in_a(a4_18to4_19), .in_b(b3_19to4_19), .out_a(a4_19to4_20), .out_b(b4_19to5_19), .out_c(matrixC4_19)); +processing_element pe5_1(.reset(effective_rst), .clk(clk), .in_a(a5_0to5_1), .in_b(b4_1to5_1), .out_a(a5_1to5_2), .out_b(b5_1to6_1), .out_c(matrixC5_1)); +processing_element pe5_2(.reset(effective_rst), .clk(clk), .in_a(a5_1to5_2), .in_b(b4_2to5_2), .out_a(a5_2to5_3), .out_b(b5_2to6_2), .out_c(matrixC5_2)); +processing_element pe5_3(.reset(effective_rst), .clk(clk), .in_a(a5_2to5_3), .in_b(b4_3to5_3), .out_a(a5_3to5_4), .out_b(b5_3to6_3), .out_c(matrixC5_3)); +processing_element pe5_4(.reset(effective_rst), .clk(clk), .in_a(a5_3to5_4), .in_b(b4_4to5_4), .out_a(a5_4to5_5), .out_b(b5_4to6_4), .out_c(matrixC5_4)); +processing_element pe5_5(.reset(effective_rst), .clk(clk), .in_a(a5_4to5_5), .in_b(b4_5to5_5), .out_a(a5_5to5_6), .out_b(b5_5to6_5), .out_c(matrixC5_5)); +processing_element pe5_6(.reset(effective_rst), .clk(clk), .in_a(a5_5to5_6), .in_b(b4_6to5_6), .out_a(a5_6to5_7), .out_b(b5_6to6_6), .out_c(matrixC5_6)); +processing_element pe5_7(.reset(effective_rst), .clk(clk), .in_a(a5_6to5_7), .in_b(b4_7to5_7), .out_a(a5_7to5_8), .out_b(b5_7to6_7), .out_c(matrixC5_7)); +processing_element pe5_8(.reset(effective_rst), .clk(clk), .in_a(a5_7to5_8), .in_b(b4_8to5_8), .out_a(a5_8to5_9), .out_b(b5_8to6_8), .out_c(matrixC5_8)); +processing_element pe5_9(.reset(effective_rst), .clk(clk), .in_a(a5_8to5_9), .in_b(b4_9to5_9), .out_a(a5_9to5_10), .out_b(b5_9to6_9), .out_c(matrixC5_9)); +processing_element pe5_10(.reset(effective_rst), .clk(clk), .in_a(a5_9to5_10), .in_b(b4_10to5_10), .out_a(a5_10to5_11), .out_b(b5_10to6_10), .out_c(matrixC5_10)); +processing_element pe5_11(.reset(effective_rst), .clk(clk), .in_a(a5_10to5_11), .in_b(b4_11to5_11), .out_a(a5_11to5_12), .out_b(b5_11to6_11), .out_c(matrixC5_11)); +processing_element pe5_12(.reset(effective_rst), .clk(clk), .in_a(a5_11to5_12), .in_b(b4_12to5_12), .out_a(a5_12to5_13), .out_b(b5_12to6_12), .out_c(matrixC5_12)); +processing_element pe5_13(.reset(effective_rst), .clk(clk), .in_a(a5_12to5_13), .in_b(b4_13to5_13), .out_a(a5_13to5_14), .out_b(b5_13to6_13), .out_c(matrixC5_13)); +processing_element pe5_14(.reset(effective_rst), .clk(clk), .in_a(a5_13to5_14), .in_b(b4_14to5_14), .out_a(a5_14to5_15), .out_b(b5_14to6_14), .out_c(matrixC5_14)); +processing_element pe5_15(.reset(effective_rst), .clk(clk), .in_a(a5_14to5_15), .in_b(b4_15to5_15), .out_a(a5_15to5_16), .out_b(b5_15to6_15), .out_c(matrixC5_15)); +processing_element pe5_16(.reset(effective_rst), .clk(clk), .in_a(a5_15to5_16), .in_b(b4_16to5_16), .out_a(a5_16to5_17), .out_b(b5_16to6_16), .out_c(matrixC5_16)); +processing_element pe5_17(.reset(effective_rst), .clk(clk), .in_a(a5_16to5_17), .in_b(b4_17to5_17), .out_a(a5_17to5_18), .out_b(b5_17to6_17), .out_c(matrixC5_17)); +processing_element pe5_18(.reset(effective_rst), .clk(clk), .in_a(a5_17to5_18), .in_b(b4_18to5_18), .out_a(a5_18to5_19), .out_b(b5_18to6_18), .out_c(matrixC5_18)); +processing_element pe5_19(.reset(effective_rst), .clk(clk), .in_a(a5_18to5_19), .in_b(b4_19to5_19), .out_a(a5_19to5_20), .out_b(b5_19to6_19), .out_c(matrixC5_19)); +processing_element pe6_1(.reset(effective_rst), .clk(clk), .in_a(a6_0to6_1), .in_b(b5_1to6_1), .out_a(a6_1to6_2), .out_b(b6_1to7_1), .out_c(matrixC6_1)); +processing_element pe6_2(.reset(effective_rst), .clk(clk), .in_a(a6_1to6_2), .in_b(b5_2to6_2), .out_a(a6_2to6_3), .out_b(b6_2to7_2), .out_c(matrixC6_2)); +processing_element pe6_3(.reset(effective_rst), .clk(clk), .in_a(a6_2to6_3), .in_b(b5_3to6_3), .out_a(a6_3to6_4), .out_b(b6_3to7_3), .out_c(matrixC6_3)); +processing_element pe6_4(.reset(effective_rst), .clk(clk), .in_a(a6_3to6_4), .in_b(b5_4to6_4), .out_a(a6_4to6_5), .out_b(b6_4to7_4), .out_c(matrixC6_4)); +processing_element pe6_5(.reset(effective_rst), .clk(clk), .in_a(a6_4to6_5), .in_b(b5_5to6_5), .out_a(a6_5to6_6), .out_b(b6_5to7_5), .out_c(matrixC6_5)); +processing_element pe6_6(.reset(effective_rst), .clk(clk), .in_a(a6_5to6_6), .in_b(b5_6to6_6), .out_a(a6_6to6_7), .out_b(b6_6to7_6), .out_c(matrixC6_6)); +processing_element pe6_7(.reset(effective_rst), .clk(clk), .in_a(a6_6to6_7), .in_b(b5_7to6_7), .out_a(a6_7to6_8), .out_b(b6_7to7_7), .out_c(matrixC6_7)); +processing_element pe6_8(.reset(effective_rst), .clk(clk), .in_a(a6_7to6_8), .in_b(b5_8to6_8), .out_a(a6_8to6_9), .out_b(b6_8to7_8), .out_c(matrixC6_8)); +processing_element pe6_9(.reset(effective_rst), .clk(clk), .in_a(a6_8to6_9), .in_b(b5_9to6_9), .out_a(a6_9to6_10), .out_b(b6_9to7_9), .out_c(matrixC6_9)); +processing_element pe6_10(.reset(effective_rst), .clk(clk), .in_a(a6_9to6_10), .in_b(b5_10to6_10), .out_a(a6_10to6_11), .out_b(b6_10to7_10), .out_c(matrixC6_10)); +processing_element pe6_11(.reset(effective_rst), .clk(clk), .in_a(a6_10to6_11), .in_b(b5_11to6_11), .out_a(a6_11to6_12), .out_b(b6_11to7_11), .out_c(matrixC6_11)); +processing_element pe6_12(.reset(effective_rst), .clk(clk), .in_a(a6_11to6_12), .in_b(b5_12to6_12), .out_a(a6_12to6_13), .out_b(b6_12to7_12), .out_c(matrixC6_12)); +processing_element pe6_13(.reset(effective_rst), .clk(clk), .in_a(a6_12to6_13), .in_b(b5_13to6_13), .out_a(a6_13to6_14), .out_b(b6_13to7_13), .out_c(matrixC6_13)); +processing_element pe6_14(.reset(effective_rst), .clk(clk), .in_a(a6_13to6_14), .in_b(b5_14to6_14), .out_a(a6_14to6_15), .out_b(b6_14to7_14), .out_c(matrixC6_14)); +processing_element pe6_15(.reset(effective_rst), .clk(clk), .in_a(a6_14to6_15), .in_b(b5_15to6_15), .out_a(a6_15to6_16), .out_b(b6_15to7_15), .out_c(matrixC6_15)); +processing_element pe6_16(.reset(effective_rst), .clk(clk), .in_a(a6_15to6_16), .in_b(b5_16to6_16), .out_a(a6_16to6_17), .out_b(b6_16to7_16), .out_c(matrixC6_16)); +processing_element pe6_17(.reset(effective_rst), .clk(clk), .in_a(a6_16to6_17), .in_b(b5_17to6_17), .out_a(a6_17to6_18), .out_b(b6_17to7_17), .out_c(matrixC6_17)); +processing_element pe6_18(.reset(effective_rst), .clk(clk), .in_a(a6_17to6_18), .in_b(b5_18to6_18), .out_a(a6_18to6_19), .out_b(b6_18to7_18), .out_c(matrixC6_18)); +processing_element pe6_19(.reset(effective_rst), .clk(clk), .in_a(a6_18to6_19), .in_b(b5_19to6_19), .out_a(a6_19to6_20), .out_b(b6_19to7_19), .out_c(matrixC6_19)); +processing_element pe7_1(.reset(effective_rst), .clk(clk), .in_a(a7_0to7_1), .in_b(b6_1to7_1), .out_a(a7_1to7_2), .out_b(b7_1to8_1), .out_c(matrixC7_1)); +processing_element pe7_2(.reset(effective_rst), .clk(clk), .in_a(a7_1to7_2), .in_b(b6_2to7_2), .out_a(a7_2to7_3), .out_b(b7_2to8_2), .out_c(matrixC7_2)); +processing_element pe7_3(.reset(effective_rst), .clk(clk), .in_a(a7_2to7_3), .in_b(b6_3to7_3), .out_a(a7_3to7_4), .out_b(b7_3to8_3), .out_c(matrixC7_3)); +processing_element pe7_4(.reset(effective_rst), .clk(clk), .in_a(a7_3to7_4), .in_b(b6_4to7_4), .out_a(a7_4to7_5), .out_b(b7_4to8_4), .out_c(matrixC7_4)); +processing_element pe7_5(.reset(effective_rst), .clk(clk), .in_a(a7_4to7_5), .in_b(b6_5to7_5), .out_a(a7_5to7_6), .out_b(b7_5to8_5), .out_c(matrixC7_5)); +processing_element pe7_6(.reset(effective_rst), .clk(clk), .in_a(a7_5to7_6), .in_b(b6_6to7_6), .out_a(a7_6to7_7), .out_b(b7_6to8_6), .out_c(matrixC7_6)); +processing_element pe7_7(.reset(effective_rst), .clk(clk), .in_a(a7_6to7_7), .in_b(b6_7to7_7), .out_a(a7_7to7_8), .out_b(b7_7to8_7), .out_c(matrixC7_7)); +processing_element pe7_8(.reset(effective_rst), .clk(clk), .in_a(a7_7to7_8), .in_b(b6_8to7_8), .out_a(a7_8to7_9), .out_b(b7_8to8_8), .out_c(matrixC7_8)); +processing_element pe7_9(.reset(effective_rst), .clk(clk), .in_a(a7_8to7_9), .in_b(b6_9to7_9), .out_a(a7_9to7_10), .out_b(b7_9to8_9), .out_c(matrixC7_9)); +processing_element pe7_10(.reset(effective_rst), .clk(clk), .in_a(a7_9to7_10), .in_b(b6_10to7_10), .out_a(a7_10to7_11), .out_b(b7_10to8_10), .out_c(matrixC7_10)); +processing_element pe7_11(.reset(effective_rst), .clk(clk), .in_a(a7_10to7_11), .in_b(b6_11to7_11), .out_a(a7_11to7_12), .out_b(b7_11to8_11), .out_c(matrixC7_11)); +processing_element pe7_12(.reset(effective_rst), .clk(clk), .in_a(a7_11to7_12), .in_b(b6_12to7_12), .out_a(a7_12to7_13), .out_b(b7_12to8_12), .out_c(matrixC7_12)); +processing_element pe7_13(.reset(effective_rst), .clk(clk), .in_a(a7_12to7_13), .in_b(b6_13to7_13), .out_a(a7_13to7_14), .out_b(b7_13to8_13), .out_c(matrixC7_13)); +processing_element pe7_14(.reset(effective_rst), .clk(clk), .in_a(a7_13to7_14), .in_b(b6_14to7_14), .out_a(a7_14to7_15), .out_b(b7_14to8_14), .out_c(matrixC7_14)); +processing_element pe7_15(.reset(effective_rst), .clk(clk), .in_a(a7_14to7_15), .in_b(b6_15to7_15), .out_a(a7_15to7_16), .out_b(b7_15to8_15), .out_c(matrixC7_15)); +processing_element pe7_16(.reset(effective_rst), .clk(clk), .in_a(a7_15to7_16), .in_b(b6_16to7_16), .out_a(a7_16to7_17), .out_b(b7_16to8_16), .out_c(matrixC7_16)); +processing_element pe7_17(.reset(effective_rst), .clk(clk), .in_a(a7_16to7_17), .in_b(b6_17to7_17), .out_a(a7_17to7_18), .out_b(b7_17to8_17), .out_c(matrixC7_17)); +processing_element pe7_18(.reset(effective_rst), .clk(clk), .in_a(a7_17to7_18), .in_b(b6_18to7_18), .out_a(a7_18to7_19), .out_b(b7_18to8_18), .out_c(matrixC7_18)); +processing_element pe7_19(.reset(effective_rst), .clk(clk), .in_a(a7_18to7_19), .in_b(b6_19to7_19), .out_a(a7_19to7_20), .out_b(b7_19to8_19), .out_c(matrixC7_19)); +processing_element pe8_1(.reset(effective_rst), .clk(clk), .in_a(a8_0to8_1), .in_b(b7_1to8_1), .out_a(a8_1to8_2), .out_b(b8_1to9_1), .out_c(matrixC8_1)); +processing_element pe8_2(.reset(effective_rst), .clk(clk), .in_a(a8_1to8_2), .in_b(b7_2to8_2), .out_a(a8_2to8_3), .out_b(b8_2to9_2), .out_c(matrixC8_2)); +processing_element pe8_3(.reset(effective_rst), .clk(clk), .in_a(a8_2to8_3), .in_b(b7_3to8_3), .out_a(a8_3to8_4), .out_b(b8_3to9_3), .out_c(matrixC8_3)); +processing_element pe8_4(.reset(effective_rst), .clk(clk), .in_a(a8_3to8_4), .in_b(b7_4to8_4), .out_a(a8_4to8_5), .out_b(b8_4to9_4), .out_c(matrixC8_4)); +processing_element pe8_5(.reset(effective_rst), .clk(clk), .in_a(a8_4to8_5), .in_b(b7_5to8_5), .out_a(a8_5to8_6), .out_b(b8_5to9_5), .out_c(matrixC8_5)); +processing_element pe8_6(.reset(effective_rst), .clk(clk), .in_a(a8_5to8_6), .in_b(b7_6to8_6), .out_a(a8_6to8_7), .out_b(b8_6to9_6), .out_c(matrixC8_6)); +processing_element pe8_7(.reset(effective_rst), .clk(clk), .in_a(a8_6to8_7), .in_b(b7_7to8_7), .out_a(a8_7to8_8), .out_b(b8_7to9_7), .out_c(matrixC8_7)); +processing_element pe8_8(.reset(effective_rst), .clk(clk), .in_a(a8_7to8_8), .in_b(b7_8to8_8), .out_a(a8_8to8_9), .out_b(b8_8to9_8), .out_c(matrixC8_8)); +processing_element pe8_9(.reset(effective_rst), .clk(clk), .in_a(a8_8to8_9), .in_b(b7_9to8_9), .out_a(a8_9to8_10), .out_b(b8_9to9_9), .out_c(matrixC8_9)); +processing_element pe8_10(.reset(effective_rst), .clk(clk), .in_a(a8_9to8_10), .in_b(b7_10to8_10), .out_a(a8_10to8_11), .out_b(b8_10to9_10), .out_c(matrixC8_10)); +processing_element pe8_11(.reset(effective_rst), .clk(clk), .in_a(a8_10to8_11), .in_b(b7_11to8_11), .out_a(a8_11to8_12), .out_b(b8_11to9_11), .out_c(matrixC8_11)); +processing_element pe8_12(.reset(effective_rst), .clk(clk), .in_a(a8_11to8_12), .in_b(b7_12to8_12), .out_a(a8_12to8_13), .out_b(b8_12to9_12), .out_c(matrixC8_12)); +processing_element pe8_13(.reset(effective_rst), .clk(clk), .in_a(a8_12to8_13), .in_b(b7_13to8_13), .out_a(a8_13to8_14), .out_b(b8_13to9_13), .out_c(matrixC8_13)); +processing_element pe8_14(.reset(effective_rst), .clk(clk), .in_a(a8_13to8_14), .in_b(b7_14to8_14), .out_a(a8_14to8_15), .out_b(b8_14to9_14), .out_c(matrixC8_14)); +processing_element pe8_15(.reset(effective_rst), .clk(clk), .in_a(a8_14to8_15), .in_b(b7_15to8_15), .out_a(a8_15to8_16), .out_b(b8_15to9_15), .out_c(matrixC8_15)); +processing_element pe8_16(.reset(effective_rst), .clk(clk), .in_a(a8_15to8_16), .in_b(b7_16to8_16), .out_a(a8_16to8_17), .out_b(b8_16to9_16), .out_c(matrixC8_16)); +processing_element pe8_17(.reset(effective_rst), .clk(clk), .in_a(a8_16to8_17), .in_b(b7_17to8_17), .out_a(a8_17to8_18), .out_b(b8_17to9_17), .out_c(matrixC8_17)); +processing_element pe8_18(.reset(effective_rst), .clk(clk), .in_a(a8_17to8_18), .in_b(b7_18to8_18), .out_a(a8_18to8_19), .out_b(b8_18to9_18), .out_c(matrixC8_18)); +processing_element pe8_19(.reset(effective_rst), .clk(clk), .in_a(a8_18to8_19), .in_b(b7_19to8_19), .out_a(a8_19to8_20), .out_b(b8_19to9_19), .out_c(matrixC8_19)); +processing_element pe9_1(.reset(effective_rst), .clk(clk), .in_a(a9_0to9_1), .in_b(b8_1to9_1), .out_a(a9_1to9_2), .out_b(b9_1to10_1), .out_c(matrixC9_1)); +processing_element pe9_2(.reset(effective_rst), .clk(clk), .in_a(a9_1to9_2), .in_b(b8_2to9_2), .out_a(a9_2to9_3), .out_b(b9_2to10_2), .out_c(matrixC9_2)); +processing_element pe9_3(.reset(effective_rst), .clk(clk), .in_a(a9_2to9_3), .in_b(b8_3to9_3), .out_a(a9_3to9_4), .out_b(b9_3to10_3), .out_c(matrixC9_3)); +processing_element pe9_4(.reset(effective_rst), .clk(clk), .in_a(a9_3to9_4), .in_b(b8_4to9_4), .out_a(a9_4to9_5), .out_b(b9_4to10_4), .out_c(matrixC9_4)); +processing_element pe9_5(.reset(effective_rst), .clk(clk), .in_a(a9_4to9_5), .in_b(b8_5to9_5), .out_a(a9_5to9_6), .out_b(b9_5to10_5), .out_c(matrixC9_5)); +processing_element pe9_6(.reset(effective_rst), .clk(clk), .in_a(a9_5to9_6), .in_b(b8_6to9_6), .out_a(a9_6to9_7), .out_b(b9_6to10_6), .out_c(matrixC9_6)); +processing_element pe9_7(.reset(effective_rst), .clk(clk), .in_a(a9_6to9_7), .in_b(b8_7to9_7), .out_a(a9_7to9_8), .out_b(b9_7to10_7), .out_c(matrixC9_7)); +processing_element pe9_8(.reset(effective_rst), .clk(clk), .in_a(a9_7to9_8), .in_b(b8_8to9_8), .out_a(a9_8to9_9), .out_b(b9_8to10_8), .out_c(matrixC9_8)); +processing_element pe9_9(.reset(effective_rst), .clk(clk), .in_a(a9_8to9_9), .in_b(b8_9to9_9), .out_a(a9_9to9_10), .out_b(b9_9to10_9), .out_c(matrixC9_9)); +processing_element pe9_10(.reset(effective_rst), .clk(clk), .in_a(a9_9to9_10), .in_b(b8_10to9_10), .out_a(a9_10to9_11), .out_b(b9_10to10_10), .out_c(matrixC9_10)); +processing_element pe9_11(.reset(effective_rst), .clk(clk), .in_a(a9_10to9_11), .in_b(b8_11to9_11), .out_a(a9_11to9_12), .out_b(b9_11to10_11), .out_c(matrixC9_11)); +processing_element pe9_12(.reset(effective_rst), .clk(clk), .in_a(a9_11to9_12), .in_b(b8_12to9_12), .out_a(a9_12to9_13), .out_b(b9_12to10_12), .out_c(matrixC9_12)); +processing_element pe9_13(.reset(effective_rst), .clk(clk), .in_a(a9_12to9_13), .in_b(b8_13to9_13), .out_a(a9_13to9_14), .out_b(b9_13to10_13), .out_c(matrixC9_13)); +processing_element pe9_14(.reset(effective_rst), .clk(clk), .in_a(a9_13to9_14), .in_b(b8_14to9_14), .out_a(a9_14to9_15), .out_b(b9_14to10_14), .out_c(matrixC9_14)); +processing_element pe9_15(.reset(effective_rst), .clk(clk), .in_a(a9_14to9_15), .in_b(b8_15to9_15), .out_a(a9_15to9_16), .out_b(b9_15to10_15), .out_c(matrixC9_15)); +processing_element pe9_16(.reset(effective_rst), .clk(clk), .in_a(a9_15to9_16), .in_b(b8_16to9_16), .out_a(a9_16to9_17), .out_b(b9_16to10_16), .out_c(matrixC9_16)); +processing_element pe9_17(.reset(effective_rst), .clk(clk), .in_a(a9_16to9_17), .in_b(b8_17to9_17), .out_a(a9_17to9_18), .out_b(b9_17to10_17), .out_c(matrixC9_17)); +processing_element pe9_18(.reset(effective_rst), .clk(clk), .in_a(a9_17to9_18), .in_b(b8_18to9_18), .out_a(a9_18to9_19), .out_b(b9_18to10_18), .out_c(matrixC9_18)); +processing_element pe9_19(.reset(effective_rst), .clk(clk), .in_a(a9_18to9_19), .in_b(b8_19to9_19), .out_a(a9_19to9_20), .out_b(b9_19to10_19), .out_c(matrixC9_19)); +processing_element pe10_1(.reset(effective_rst), .clk(clk), .in_a(a10_0to10_1), .in_b(b9_1to10_1), .out_a(a10_1to10_2), .out_b(b10_1to11_1), .out_c(matrixC10_1)); +processing_element pe10_2(.reset(effective_rst), .clk(clk), .in_a(a10_1to10_2), .in_b(b9_2to10_2), .out_a(a10_2to10_3), .out_b(b10_2to11_2), .out_c(matrixC10_2)); +processing_element pe10_3(.reset(effective_rst), .clk(clk), .in_a(a10_2to10_3), .in_b(b9_3to10_3), .out_a(a10_3to10_4), .out_b(b10_3to11_3), .out_c(matrixC10_3)); +processing_element pe10_4(.reset(effective_rst), .clk(clk), .in_a(a10_3to10_4), .in_b(b9_4to10_4), .out_a(a10_4to10_5), .out_b(b10_4to11_4), .out_c(matrixC10_4)); +processing_element pe10_5(.reset(effective_rst), .clk(clk), .in_a(a10_4to10_5), .in_b(b9_5to10_5), .out_a(a10_5to10_6), .out_b(b10_5to11_5), .out_c(matrixC10_5)); +processing_element pe10_6(.reset(effective_rst), .clk(clk), .in_a(a10_5to10_6), .in_b(b9_6to10_6), .out_a(a10_6to10_7), .out_b(b10_6to11_6), .out_c(matrixC10_6)); +processing_element pe10_7(.reset(effective_rst), .clk(clk), .in_a(a10_6to10_7), .in_b(b9_7to10_7), .out_a(a10_7to10_8), .out_b(b10_7to11_7), .out_c(matrixC10_7)); +processing_element pe10_8(.reset(effective_rst), .clk(clk), .in_a(a10_7to10_8), .in_b(b9_8to10_8), .out_a(a10_8to10_9), .out_b(b10_8to11_8), .out_c(matrixC10_8)); +processing_element pe10_9(.reset(effective_rst), .clk(clk), .in_a(a10_8to10_9), .in_b(b9_9to10_9), .out_a(a10_9to10_10), .out_b(b10_9to11_9), .out_c(matrixC10_9)); +processing_element pe10_10(.reset(effective_rst), .clk(clk), .in_a(a10_9to10_10), .in_b(b9_10to10_10), .out_a(a10_10to10_11), .out_b(b10_10to11_10), .out_c(matrixC10_10)); +processing_element pe10_11(.reset(effective_rst), .clk(clk), .in_a(a10_10to10_11), .in_b(b9_11to10_11), .out_a(a10_11to10_12), .out_b(b10_11to11_11), .out_c(matrixC10_11)); +processing_element pe10_12(.reset(effective_rst), .clk(clk), .in_a(a10_11to10_12), .in_b(b9_12to10_12), .out_a(a10_12to10_13), .out_b(b10_12to11_12), .out_c(matrixC10_12)); +processing_element pe10_13(.reset(effective_rst), .clk(clk), .in_a(a10_12to10_13), .in_b(b9_13to10_13), .out_a(a10_13to10_14), .out_b(b10_13to11_13), .out_c(matrixC10_13)); +processing_element pe10_14(.reset(effective_rst), .clk(clk), .in_a(a10_13to10_14), .in_b(b9_14to10_14), .out_a(a10_14to10_15), .out_b(b10_14to11_14), .out_c(matrixC10_14)); +processing_element pe10_15(.reset(effective_rst), .clk(clk), .in_a(a10_14to10_15), .in_b(b9_15to10_15), .out_a(a10_15to10_16), .out_b(b10_15to11_15), .out_c(matrixC10_15)); +processing_element pe10_16(.reset(effective_rst), .clk(clk), .in_a(a10_15to10_16), .in_b(b9_16to10_16), .out_a(a10_16to10_17), .out_b(b10_16to11_16), .out_c(matrixC10_16)); +processing_element pe10_17(.reset(effective_rst), .clk(clk), .in_a(a10_16to10_17), .in_b(b9_17to10_17), .out_a(a10_17to10_18), .out_b(b10_17to11_17), .out_c(matrixC10_17)); +processing_element pe10_18(.reset(effective_rst), .clk(clk), .in_a(a10_17to10_18), .in_b(b9_18to10_18), .out_a(a10_18to10_19), .out_b(b10_18to11_18), .out_c(matrixC10_18)); +processing_element pe10_19(.reset(effective_rst), .clk(clk), .in_a(a10_18to10_19), .in_b(b9_19to10_19), .out_a(a10_19to10_20), .out_b(b10_19to11_19), .out_c(matrixC10_19)); +processing_element pe11_1(.reset(effective_rst), .clk(clk), .in_a(a11_0to11_1), .in_b(b10_1to11_1), .out_a(a11_1to11_2), .out_b(b11_1to12_1), .out_c(matrixC11_1)); +processing_element pe11_2(.reset(effective_rst), .clk(clk), .in_a(a11_1to11_2), .in_b(b10_2to11_2), .out_a(a11_2to11_3), .out_b(b11_2to12_2), .out_c(matrixC11_2)); +processing_element pe11_3(.reset(effective_rst), .clk(clk), .in_a(a11_2to11_3), .in_b(b10_3to11_3), .out_a(a11_3to11_4), .out_b(b11_3to12_3), .out_c(matrixC11_3)); +processing_element pe11_4(.reset(effective_rst), .clk(clk), .in_a(a11_3to11_4), .in_b(b10_4to11_4), .out_a(a11_4to11_5), .out_b(b11_4to12_4), .out_c(matrixC11_4)); +processing_element pe11_5(.reset(effective_rst), .clk(clk), .in_a(a11_4to11_5), .in_b(b10_5to11_5), .out_a(a11_5to11_6), .out_b(b11_5to12_5), .out_c(matrixC11_5)); +processing_element pe11_6(.reset(effective_rst), .clk(clk), .in_a(a11_5to11_6), .in_b(b10_6to11_6), .out_a(a11_6to11_7), .out_b(b11_6to12_6), .out_c(matrixC11_6)); +processing_element pe11_7(.reset(effective_rst), .clk(clk), .in_a(a11_6to11_7), .in_b(b10_7to11_7), .out_a(a11_7to11_8), .out_b(b11_7to12_7), .out_c(matrixC11_7)); +processing_element pe11_8(.reset(effective_rst), .clk(clk), .in_a(a11_7to11_8), .in_b(b10_8to11_8), .out_a(a11_8to11_9), .out_b(b11_8to12_8), .out_c(matrixC11_8)); +processing_element pe11_9(.reset(effective_rst), .clk(clk), .in_a(a11_8to11_9), .in_b(b10_9to11_9), .out_a(a11_9to11_10), .out_b(b11_9to12_9), .out_c(matrixC11_9)); +processing_element pe11_10(.reset(effective_rst), .clk(clk), .in_a(a11_9to11_10), .in_b(b10_10to11_10), .out_a(a11_10to11_11), .out_b(b11_10to12_10), .out_c(matrixC11_10)); +processing_element pe11_11(.reset(effective_rst), .clk(clk), .in_a(a11_10to11_11), .in_b(b10_11to11_11), .out_a(a11_11to11_12), .out_b(b11_11to12_11), .out_c(matrixC11_11)); +processing_element pe11_12(.reset(effective_rst), .clk(clk), .in_a(a11_11to11_12), .in_b(b10_12to11_12), .out_a(a11_12to11_13), .out_b(b11_12to12_12), .out_c(matrixC11_12)); +processing_element pe11_13(.reset(effective_rst), .clk(clk), .in_a(a11_12to11_13), .in_b(b10_13to11_13), .out_a(a11_13to11_14), .out_b(b11_13to12_13), .out_c(matrixC11_13)); +processing_element pe11_14(.reset(effective_rst), .clk(clk), .in_a(a11_13to11_14), .in_b(b10_14to11_14), .out_a(a11_14to11_15), .out_b(b11_14to12_14), .out_c(matrixC11_14)); +processing_element pe11_15(.reset(effective_rst), .clk(clk), .in_a(a11_14to11_15), .in_b(b10_15to11_15), .out_a(a11_15to11_16), .out_b(b11_15to12_15), .out_c(matrixC11_15)); +processing_element pe11_16(.reset(effective_rst), .clk(clk), .in_a(a11_15to11_16), .in_b(b10_16to11_16), .out_a(a11_16to11_17), .out_b(b11_16to12_16), .out_c(matrixC11_16)); +processing_element pe11_17(.reset(effective_rst), .clk(clk), .in_a(a11_16to11_17), .in_b(b10_17to11_17), .out_a(a11_17to11_18), .out_b(b11_17to12_17), .out_c(matrixC11_17)); +processing_element pe11_18(.reset(effective_rst), .clk(clk), .in_a(a11_17to11_18), .in_b(b10_18to11_18), .out_a(a11_18to11_19), .out_b(b11_18to12_18), .out_c(matrixC11_18)); +processing_element pe11_19(.reset(effective_rst), .clk(clk), .in_a(a11_18to11_19), .in_b(b10_19to11_19), .out_a(a11_19to11_20), .out_b(b11_19to12_19), .out_c(matrixC11_19)); +processing_element pe12_1(.reset(effective_rst), .clk(clk), .in_a(a12_0to12_1), .in_b(b11_1to12_1), .out_a(a12_1to12_2), .out_b(b12_1to13_1), .out_c(matrixC12_1)); +processing_element pe12_2(.reset(effective_rst), .clk(clk), .in_a(a12_1to12_2), .in_b(b11_2to12_2), .out_a(a12_2to12_3), .out_b(b12_2to13_2), .out_c(matrixC12_2)); +processing_element pe12_3(.reset(effective_rst), .clk(clk), .in_a(a12_2to12_3), .in_b(b11_3to12_3), .out_a(a12_3to12_4), .out_b(b12_3to13_3), .out_c(matrixC12_3)); +processing_element pe12_4(.reset(effective_rst), .clk(clk), .in_a(a12_3to12_4), .in_b(b11_4to12_4), .out_a(a12_4to12_5), .out_b(b12_4to13_4), .out_c(matrixC12_4)); +processing_element pe12_5(.reset(effective_rst), .clk(clk), .in_a(a12_4to12_5), .in_b(b11_5to12_5), .out_a(a12_5to12_6), .out_b(b12_5to13_5), .out_c(matrixC12_5)); +processing_element pe12_6(.reset(effective_rst), .clk(clk), .in_a(a12_5to12_6), .in_b(b11_6to12_6), .out_a(a12_6to12_7), .out_b(b12_6to13_6), .out_c(matrixC12_6)); +processing_element pe12_7(.reset(effective_rst), .clk(clk), .in_a(a12_6to12_7), .in_b(b11_7to12_7), .out_a(a12_7to12_8), .out_b(b12_7to13_7), .out_c(matrixC12_7)); +processing_element pe12_8(.reset(effective_rst), .clk(clk), .in_a(a12_7to12_8), .in_b(b11_8to12_8), .out_a(a12_8to12_9), .out_b(b12_8to13_8), .out_c(matrixC12_8)); +processing_element pe12_9(.reset(effective_rst), .clk(clk), .in_a(a12_8to12_9), .in_b(b11_9to12_9), .out_a(a12_9to12_10), .out_b(b12_9to13_9), .out_c(matrixC12_9)); +processing_element pe12_10(.reset(effective_rst), .clk(clk), .in_a(a12_9to12_10), .in_b(b11_10to12_10), .out_a(a12_10to12_11), .out_b(b12_10to13_10), .out_c(matrixC12_10)); +processing_element pe12_11(.reset(effective_rst), .clk(clk), .in_a(a12_10to12_11), .in_b(b11_11to12_11), .out_a(a12_11to12_12), .out_b(b12_11to13_11), .out_c(matrixC12_11)); +processing_element pe12_12(.reset(effective_rst), .clk(clk), .in_a(a12_11to12_12), .in_b(b11_12to12_12), .out_a(a12_12to12_13), .out_b(b12_12to13_12), .out_c(matrixC12_12)); +processing_element pe12_13(.reset(effective_rst), .clk(clk), .in_a(a12_12to12_13), .in_b(b11_13to12_13), .out_a(a12_13to12_14), .out_b(b12_13to13_13), .out_c(matrixC12_13)); +processing_element pe12_14(.reset(effective_rst), .clk(clk), .in_a(a12_13to12_14), .in_b(b11_14to12_14), .out_a(a12_14to12_15), .out_b(b12_14to13_14), .out_c(matrixC12_14)); +processing_element pe12_15(.reset(effective_rst), .clk(clk), .in_a(a12_14to12_15), .in_b(b11_15to12_15), .out_a(a12_15to12_16), .out_b(b12_15to13_15), .out_c(matrixC12_15)); +processing_element pe12_16(.reset(effective_rst), .clk(clk), .in_a(a12_15to12_16), .in_b(b11_16to12_16), .out_a(a12_16to12_17), .out_b(b12_16to13_16), .out_c(matrixC12_16)); +processing_element pe12_17(.reset(effective_rst), .clk(clk), .in_a(a12_16to12_17), .in_b(b11_17to12_17), .out_a(a12_17to12_18), .out_b(b12_17to13_17), .out_c(matrixC12_17)); +processing_element pe12_18(.reset(effective_rst), .clk(clk), .in_a(a12_17to12_18), .in_b(b11_18to12_18), .out_a(a12_18to12_19), .out_b(b12_18to13_18), .out_c(matrixC12_18)); +processing_element pe12_19(.reset(effective_rst), .clk(clk), .in_a(a12_18to12_19), .in_b(b11_19to12_19), .out_a(a12_19to12_20), .out_b(b12_19to13_19), .out_c(matrixC12_19)); +processing_element pe13_1(.reset(effective_rst), .clk(clk), .in_a(a13_0to13_1), .in_b(b12_1to13_1), .out_a(a13_1to13_2), .out_b(b13_1to14_1), .out_c(matrixC13_1)); +processing_element pe13_2(.reset(effective_rst), .clk(clk), .in_a(a13_1to13_2), .in_b(b12_2to13_2), .out_a(a13_2to13_3), .out_b(b13_2to14_2), .out_c(matrixC13_2)); +processing_element pe13_3(.reset(effective_rst), .clk(clk), .in_a(a13_2to13_3), .in_b(b12_3to13_3), .out_a(a13_3to13_4), .out_b(b13_3to14_3), .out_c(matrixC13_3)); +processing_element pe13_4(.reset(effective_rst), .clk(clk), .in_a(a13_3to13_4), .in_b(b12_4to13_4), .out_a(a13_4to13_5), .out_b(b13_4to14_4), .out_c(matrixC13_4)); +processing_element pe13_5(.reset(effective_rst), .clk(clk), .in_a(a13_4to13_5), .in_b(b12_5to13_5), .out_a(a13_5to13_6), .out_b(b13_5to14_5), .out_c(matrixC13_5)); +processing_element pe13_6(.reset(effective_rst), .clk(clk), .in_a(a13_5to13_6), .in_b(b12_6to13_6), .out_a(a13_6to13_7), .out_b(b13_6to14_6), .out_c(matrixC13_6)); +processing_element pe13_7(.reset(effective_rst), .clk(clk), .in_a(a13_6to13_7), .in_b(b12_7to13_7), .out_a(a13_7to13_8), .out_b(b13_7to14_7), .out_c(matrixC13_7)); +processing_element pe13_8(.reset(effective_rst), .clk(clk), .in_a(a13_7to13_8), .in_b(b12_8to13_8), .out_a(a13_8to13_9), .out_b(b13_8to14_8), .out_c(matrixC13_8)); +processing_element pe13_9(.reset(effective_rst), .clk(clk), .in_a(a13_8to13_9), .in_b(b12_9to13_9), .out_a(a13_9to13_10), .out_b(b13_9to14_9), .out_c(matrixC13_9)); +processing_element pe13_10(.reset(effective_rst), .clk(clk), .in_a(a13_9to13_10), .in_b(b12_10to13_10), .out_a(a13_10to13_11), .out_b(b13_10to14_10), .out_c(matrixC13_10)); +processing_element pe13_11(.reset(effective_rst), .clk(clk), .in_a(a13_10to13_11), .in_b(b12_11to13_11), .out_a(a13_11to13_12), .out_b(b13_11to14_11), .out_c(matrixC13_11)); +processing_element pe13_12(.reset(effective_rst), .clk(clk), .in_a(a13_11to13_12), .in_b(b12_12to13_12), .out_a(a13_12to13_13), .out_b(b13_12to14_12), .out_c(matrixC13_12)); +processing_element pe13_13(.reset(effective_rst), .clk(clk), .in_a(a13_12to13_13), .in_b(b12_13to13_13), .out_a(a13_13to13_14), .out_b(b13_13to14_13), .out_c(matrixC13_13)); +processing_element pe13_14(.reset(effective_rst), .clk(clk), .in_a(a13_13to13_14), .in_b(b12_14to13_14), .out_a(a13_14to13_15), .out_b(b13_14to14_14), .out_c(matrixC13_14)); +processing_element pe13_15(.reset(effective_rst), .clk(clk), .in_a(a13_14to13_15), .in_b(b12_15to13_15), .out_a(a13_15to13_16), .out_b(b13_15to14_15), .out_c(matrixC13_15)); +processing_element pe13_16(.reset(effective_rst), .clk(clk), .in_a(a13_15to13_16), .in_b(b12_16to13_16), .out_a(a13_16to13_17), .out_b(b13_16to14_16), .out_c(matrixC13_16)); +processing_element pe13_17(.reset(effective_rst), .clk(clk), .in_a(a13_16to13_17), .in_b(b12_17to13_17), .out_a(a13_17to13_18), .out_b(b13_17to14_17), .out_c(matrixC13_17)); +processing_element pe13_18(.reset(effective_rst), .clk(clk), .in_a(a13_17to13_18), .in_b(b12_18to13_18), .out_a(a13_18to13_19), .out_b(b13_18to14_18), .out_c(matrixC13_18)); +processing_element pe13_19(.reset(effective_rst), .clk(clk), .in_a(a13_18to13_19), .in_b(b12_19to13_19), .out_a(a13_19to13_20), .out_b(b13_19to14_19), .out_c(matrixC13_19)); +processing_element pe14_1(.reset(effective_rst), .clk(clk), .in_a(a14_0to14_1), .in_b(b13_1to14_1), .out_a(a14_1to14_2), .out_b(b14_1to15_1), .out_c(matrixC14_1)); +processing_element pe14_2(.reset(effective_rst), .clk(clk), .in_a(a14_1to14_2), .in_b(b13_2to14_2), .out_a(a14_2to14_3), .out_b(b14_2to15_2), .out_c(matrixC14_2)); +processing_element pe14_3(.reset(effective_rst), .clk(clk), .in_a(a14_2to14_3), .in_b(b13_3to14_3), .out_a(a14_3to14_4), .out_b(b14_3to15_3), .out_c(matrixC14_3)); +processing_element pe14_4(.reset(effective_rst), .clk(clk), .in_a(a14_3to14_4), .in_b(b13_4to14_4), .out_a(a14_4to14_5), .out_b(b14_4to15_4), .out_c(matrixC14_4)); +processing_element pe14_5(.reset(effective_rst), .clk(clk), .in_a(a14_4to14_5), .in_b(b13_5to14_5), .out_a(a14_5to14_6), .out_b(b14_5to15_5), .out_c(matrixC14_5)); +processing_element pe14_6(.reset(effective_rst), .clk(clk), .in_a(a14_5to14_6), .in_b(b13_6to14_6), .out_a(a14_6to14_7), .out_b(b14_6to15_6), .out_c(matrixC14_6)); +processing_element pe14_7(.reset(effective_rst), .clk(clk), .in_a(a14_6to14_7), .in_b(b13_7to14_7), .out_a(a14_7to14_8), .out_b(b14_7to15_7), .out_c(matrixC14_7)); +processing_element pe14_8(.reset(effective_rst), .clk(clk), .in_a(a14_7to14_8), .in_b(b13_8to14_8), .out_a(a14_8to14_9), .out_b(b14_8to15_8), .out_c(matrixC14_8)); +processing_element pe14_9(.reset(effective_rst), .clk(clk), .in_a(a14_8to14_9), .in_b(b13_9to14_9), .out_a(a14_9to14_10), .out_b(b14_9to15_9), .out_c(matrixC14_9)); +processing_element pe14_10(.reset(effective_rst), .clk(clk), .in_a(a14_9to14_10), .in_b(b13_10to14_10), .out_a(a14_10to14_11), .out_b(b14_10to15_10), .out_c(matrixC14_10)); +processing_element pe14_11(.reset(effective_rst), .clk(clk), .in_a(a14_10to14_11), .in_b(b13_11to14_11), .out_a(a14_11to14_12), .out_b(b14_11to15_11), .out_c(matrixC14_11)); +processing_element pe14_12(.reset(effective_rst), .clk(clk), .in_a(a14_11to14_12), .in_b(b13_12to14_12), .out_a(a14_12to14_13), .out_b(b14_12to15_12), .out_c(matrixC14_12)); +processing_element pe14_13(.reset(effective_rst), .clk(clk), .in_a(a14_12to14_13), .in_b(b13_13to14_13), .out_a(a14_13to14_14), .out_b(b14_13to15_13), .out_c(matrixC14_13)); +processing_element pe14_14(.reset(effective_rst), .clk(clk), .in_a(a14_13to14_14), .in_b(b13_14to14_14), .out_a(a14_14to14_15), .out_b(b14_14to15_14), .out_c(matrixC14_14)); +processing_element pe14_15(.reset(effective_rst), .clk(clk), .in_a(a14_14to14_15), .in_b(b13_15to14_15), .out_a(a14_15to14_16), .out_b(b14_15to15_15), .out_c(matrixC14_15)); +processing_element pe14_16(.reset(effective_rst), .clk(clk), .in_a(a14_15to14_16), .in_b(b13_16to14_16), .out_a(a14_16to14_17), .out_b(b14_16to15_16), .out_c(matrixC14_16)); +processing_element pe14_17(.reset(effective_rst), .clk(clk), .in_a(a14_16to14_17), .in_b(b13_17to14_17), .out_a(a14_17to14_18), .out_b(b14_17to15_17), .out_c(matrixC14_17)); +processing_element pe14_18(.reset(effective_rst), .clk(clk), .in_a(a14_17to14_18), .in_b(b13_18to14_18), .out_a(a14_18to14_19), .out_b(b14_18to15_18), .out_c(matrixC14_18)); +processing_element pe14_19(.reset(effective_rst), .clk(clk), .in_a(a14_18to14_19), .in_b(b13_19to14_19), .out_a(a14_19to14_20), .out_b(b14_19to15_19), .out_c(matrixC14_19)); +processing_element pe15_1(.reset(effective_rst), .clk(clk), .in_a(a15_0to15_1), .in_b(b14_1to15_1), .out_a(a15_1to15_2), .out_b(b15_1to16_1), .out_c(matrixC15_1)); +processing_element pe15_2(.reset(effective_rst), .clk(clk), .in_a(a15_1to15_2), .in_b(b14_2to15_2), .out_a(a15_2to15_3), .out_b(b15_2to16_2), .out_c(matrixC15_2)); +processing_element pe15_3(.reset(effective_rst), .clk(clk), .in_a(a15_2to15_3), .in_b(b14_3to15_3), .out_a(a15_3to15_4), .out_b(b15_3to16_3), .out_c(matrixC15_3)); +processing_element pe15_4(.reset(effective_rst), .clk(clk), .in_a(a15_3to15_4), .in_b(b14_4to15_4), .out_a(a15_4to15_5), .out_b(b15_4to16_4), .out_c(matrixC15_4)); +processing_element pe15_5(.reset(effective_rst), .clk(clk), .in_a(a15_4to15_5), .in_b(b14_5to15_5), .out_a(a15_5to15_6), .out_b(b15_5to16_5), .out_c(matrixC15_5)); +processing_element pe15_6(.reset(effective_rst), .clk(clk), .in_a(a15_5to15_6), .in_b(b14_6to15_6), .out_a(a15_6to15_7), .out_b(b15_6to16_6), .out_c(matrixC15_6)); +processing_element pe15_7(.reset(effective_rst), .clk(clk), .in_a(a15_6to15_7), .in_b(b14_7to15_7), .out_a(a15_7to15_8), .out_b(b15_7to16_7), .out_c(matrixC15_7)); +processing_element pe15_8(.reset(effective_rst), .clk(clk), .in_a(a15_7to15_8), .in_b(b14_8to15_8), .out_a(a15_8to15_9), .out_b(b15_8to16_8), .out_c(matrixC15_8)); +processing_element pe15_9(.reset(effective_rst), .clk(clk), .in_a(a15_8to15_9), .in_b(b14_9to15_9), .out_a(a15_9to15_10), .out_b(b15_9to16_9), .out_c(matrixC15_9)); +processing_element pe15_10(.reset(effective_rst), .clk(clk), .in_a(a15_9to15_10), .in_b(b14_10to15_10), .out_a(a15_10to15_11), .out_b(b15_10to16_10), .out_c(matrixC15_10)); +processing_element pe15_11(.reset(effective_rst), .clk(clk), .in_a(a15_10to15_11), .in_b(b14_11to15_11), .out_a(a15_11to15_12), .out_b(b15_11to16_11), .out_c(matrixC15_11)); +processing_element pe15_12(.reset(effective_rst), .clk(clk), .in_a(a15_11to15_12), .in_b(b14_12to15_12), .out_a(a15_12to15_13), .out_b(b15_12to16_12), .out_c(matrixC15_12)); +processing_element pe15_13(.reset(effective_rst), .clk(clk), .in_a(a15_12to15_13), .in_b(b14_13to15_13), .out_a(a15_13to15_14), .out_b(b15_13to16_13), .out_c(matrixC15_13)); +processing_element pe15_14(.reset(effective_rst), .clk(clk), .in_a(a15_13to15_14), .in_b(b14_14to15_14), .out_a(a15_14to15_15), .out_b(b15_14to16_14), .out_c(matrixC15_14)); +processing_element pe15_15(.reset(effective_rst), .clk(clk), .in_a(a15_14to15_15), .in_b(b14_15to15_15), .out_a(a15_15to15_16), .out_b(b15_15to16_15), .out_c(matrixC15_15)); +processing_element pe15_16(.reset(effective_rst), .clk(clk), .in_a(a15_15to15_16), .in_b(b14_16to15_16), .out_a(a15_16to15_17), .out_b(b15_16to16_16), .out_c(matrixC15_16)); +processing_element pe15_17(.reset(effective_rst), .clk(clk), .in_a(a15_16to15_17), .in_b(b14_17to15_17), .out_a(a15_17to15_18), .out_b(b15_17to16_17), .out_c(matrixC15_17)); +processing_element pe15_18(.reset(effective_rst), .clk(clk), .in_a(a15_17to15_18), .in_b(b14_18to15_18), .out_a(a15_18to15_19), .out_b(b15_18to16_18), .out_c(matrixC15_18)); +processing_element pe15_19(.reset(effective_rst), .clk(clk), .in_a(a15_18to15_19), .in_b(b14_19to15_19), .out_a(a15_19to15_20), .out_b(b15_19to16_19), .out_c(matrixC15_19)); +processing_element pe16_1(.reset(effective_rst), .clk(clk), .in_a(a16_0to16_1), .in_b(b15_1to16_1), .out_a(a16_1to16_2), .out_b(b16_1to17_1), .out_c(matrixC16_1)); +processing_element pe16_2(.reset(effective_rst), .clk(clk), .in_a(a16_1to16_2), .in_b(b15_2to16_2), .out_a(a16_2to16_3), .out_b(b16_2to17_2), .out_c(matrixC16_2)); +processing_element pe16_3(.reset(effective_rst), .clk(clk), .in_a(a16_2to16_3), .in_b(b15_3to16_3), .out_a(a16_3to16_4), .out_b(b16_3to17_3), .out_c(matrixC16_3)); +processing_element pe16_4(.reset(effective_rst), .clk(clk), .in_a(a16_3to16_4), .in_b(b15_4to16_4), .out_a(a16_4to16_5), .out_b(b16_4to17_4), .out_c(matrixC16_4)); +processing_element pe16_5(.reset(effective_rst), .clk(clk), .in_a(a16_4to16_5), .in_b(b15_5to16_5), .out_a(a16_5to16_6), .out_b(b16_5to17_5), .out_c(matrixC16_5)); +processing_element pe16_6(.reset(effective_rst), .clk(clk), .in_a(a16_5to16_6), .in_b(b15_6to16_6), .out_a(a16_6to16_7), .out_b(b16_6to17_6), .out_c(matrixC16_6)); +processing_element pe16_7(.reset(effective_rst), .clk(clk), .in_a(a16_6to16_7), .in_b(b15_7to16_7), .out_a(a16_7to16_8), .out_b(b16_7to17_7), .out_c(matrixC16_7)); +processing_element pe16_8(.reset(effective_rst), .clk(clk), .in_a(a16_7to16_8), .in_b(b15_8to16_8), .out_a(a16_8to16_9), .out_b(b16_8to17_8), .out_c(matrixC16_8)); +processing_element pe16_9(.reset(effective_rst), .clk(clk), .in_a(a16_8to16_9), .in_b(b15_9to16_9), .out_a(a16_9to16_10), .out_b(b16_9to17_9), .out_c(matrixC16_9)); +processing_element pe16_10(.reset(effective_rst), .clk(clk), .in_a(a16_9to16_10), .in_b(b15_10to16_10), .out_a(a16_10to16_11), .out_b(b16_10to17_10), .out_c(matrixC16_10)); +processing_element pe16_11(.reset(effective_rst), .clk(clk), .in_a(a16_10to16_11), .in_b(b15_11to16_11), .out_a(a16_11to16_12), .out_b(b16_11to17_11), .out_c(matrixC16_11)); +processing_element pe16_12(.reset(effective_rst), .clk(clk), .in_a(a16_11to16_12), .in_b(b15_12to16_12), .out_a(a16_12to16_13), .out_b(b16_12to17_12), .out_c(matrixC16_12)); +processing_element pe16_13(.reset(effective_rst), .clk(clk), .in_a(a16_12to16_13), .in_b(b15_13to16_13), .out_a(a16_13to16_14), .out_b(b16_13to17_13), .out_c(matrixC16_13)); +processing_element pe16_14(.reset(effective_rst), .clk(clk), .in_a(a16_13to16_14), .in_b(b15_14to16_14), .out_a(a16_14to16_15), .out_b(b16_14to17_14), .out_c(matrixC16_14)); +processing_element pe16_15(.reset(effective_rst), .clk(clk), .in_a(a16_14to16_15), .in_b(b15_15to16_15), .out_a(a16_15to16_16), .out_b(b16_15to17_15), .out_c(matrixC16_15)); +processing_element pe16_16(.reset(effective_rst), .clk(clk), .in_a(a16_15to16_16), .in_b(b15_16to16_16), .out_a(a16_16to16_17), .out_b(b16_16to17_16), .out_c(matrixC16_16)); +processing_element pe16_17(.reset(effective_rst), .clk(clk), .in_a(a16_16to16_17), .in_b(b15_17to16_17), .out_a(a16_17to16_18), .out_b(b16_17to17_17), .out_c(matrixC16_17)); +processing_element pe16_18(.reset(effective_rst), .clk(clk), .in_a(a16_17to16_18), .in_b(b15_18to16_18), .out_a(a16_18to16_19), .out_b(b16_18to17_18), .out_c(matrixC16_18)); +processing_element pe16_19(.reset(effective_rst), .clk(clk), .in_a(a16_18to16_19), .in_b(b15_19to16_19), .out_a(a16_19to16_20), .out_b(b16_19to17_19), .out_c(matrixC16_19)); +processing_element pe17_1(.reset(effective_rst), .clk(clk), .in_a(a17_0to17_1), .in_b(b16_1to17_1), .out_a(a17_1to17_2), .out_b(b17_1to18_1), .out_c(matrixC17_1)); +processing_element pe17_2(.reset(effective_rst), .clk(clk), .in_a(a17_1to17_2), .in_b(b16_2to17_2), .out_a(a17_2to17_3), .out_b(b17_2to18_2), .out_c(matrixC17_2)); +processing_element pe17_3(.reset(effective_rst), .clk(clk), .in_a(a17_2to17_3), .in_b(b16_3to17_3), .out_a(a17_3to17_4), .out_b(b17_3to18_3), .out_c(matrixC17_3)); +processing_element pe17_4(.reset(effective_rst), .clk(clk), .in_a(a17_3to17_4), .in_b(b16_4to17_4), .out_a(a17_4to17_5), .out_b(b17_4to18_4), .out_c(matrixC17_4)); +processing_element pe17_5(.reset(effective_rst), .clk(clk), .in_a(a17_4to17_5), .in_b(b16_5to17_5), .out_a(a17_5to17_6), .out_b(b17_5to18_5), .out_c(matrixC17_5)); +processing_element pe17_6(.reset(effective_rst), .clk(clk), .in_a(a17_5to17_6), .in_b(b16_6to17_6), .out_a(a17_6to17_7), .out_b(b17_6to18_6), .out_c(matrixC17_6)); +processing_element pe17_7(.reset(effective_rst), .clk(clk), .in_a(a17_6to17_7), .in_b(b16_7to17_7), .out_a(a17_7to17_8), .out_b(b17_7to18_7), .out_c(matrixC17_7)); +processing_element pe17_8(.reset(effective_rst), .clk(clk), .in_a(a17_7to17_8), .in_b(b16_8to17_8), .out_a(a17_8to17_9), .out_b(b17_8to18_8), .out_c(matrixC17_8)); +processing_element pe17_9(.reset(effective_rst), .clk(clk), .in_a(a17_8to17_9), .in_b(b16_9to17_9), .out_a(a17_9to17_10), .out_b(b17_9to18_9), .out_c(matrixC17_9)); +processing_element pe17_10(.reset(effective_rst), .clk(clk), .in_a(a17_9to17_10), .in_b(b16_10to17_10), .out_a(a17_10to17_11), .out_b(b17_10to18_10), .out_c(matrixC17_10)); +processing_element pe17_11(.reset(effective_rst), .clk(clk), .in_a(a17_10to17_11), .in_b(b16_11to17_11), .out_a(a17_11to17_12), .out_b(b17_11to18_11), .out_c(matrixC17_11)); +processing_element pe17_12(.reset(effective_rst), .clk(clk), .in_a(a17_11to17_12), .in_b(b16_12to17_12), .out_a(a17_12to17_13), .out_b(b17_12to18_12), .out_c(matrixC17_12)); +processing_element pe17_13(.reset(effective_rst), .clk(clk), .in_a(a17_12to17_13), .in_b(b16_13to17_13), .out_a(a17_13to17_14), .out_b(b17_13to18_13), .out_c(matrixC17_13)); +processing_element pe17_14(.reset(effective_rst), .clk(clk), .in_a(a17_13to17_14), .in_b(b16_14to17_14), .out_a(a17_14to17_15), .out_b(b17_14to18_14), .out_c(matrixC17_14)); +processing_element pe17_15(.reset(effective_rst), .clk(clk), .in_a(a17_14to17_15), .in_b(b16_15to17_15), .out_a(a17_15to17_16), .out_b(b17_15to18_15), .out_c(matrixC17_15)); +processing_element pe17_16(.reset(effective_rst), .clk(clk), .in_a(a17_15to17_16), .in_b(b16_16to17_16), .out_a(a17_16to17_17), .out_b(b17_16to18_16), .out_c(matrixC17_16)); +processing_element pe17_17(.reset(effective_rst), .clk(clk), .in_a(a17_16to17_17), .in_b(b16_17to17_17), .out_a(a17_17to17_18), .out_b(b17_17to18_17), .out_c(matrixC17_17)); +processing_element pe17_18(.reset(effective_rst), .clk(clk), .in_a(a17_17to17_18), .in_b(b16_18to17_18), .out_a(a17_18to17_19), .out_b(b17_18to18_18), .out_c(matrixC17_18)); +processing_element pe17_19(.reset(effective_rst), .clk(clk), .in_a(a17_18to17_19), .in_b(b16_19to17_19), .out_a(a17_19to17_20), .out_b(b17_19to18_19), .out_c(matrixC17_19)); +processing_element pe18_1(.reset(effective_rst), .clk(clk), .in_a(a18_0to18_1), .in_b(b17_1to18_1), .out_a(a18_1to18_2), .out_b(b18_1to19_1), .out_c(matrixC18_1)); +processing_element pe18_2(.reset(effective_rst), .clk(clk), .in_a(a18_1to18_2), .in_b(b17_2to18_2), .out_a(a18_2to18_3), .out_b(b18_2to19_2), .out_c(matrixC18_2)); +processing_element pe18_3(.reset(effective_rst), .clk(clk), .in_a(a18_2to18_3), .in_b(b17_3to18_3), .out_a(a18_3to18_4), .out_b(b18_3to19_3), .out_c(matrixC18_3)); +processing_element pe18_4(.reset(effective_rst), .clk(clk), .in_a(a18_3to18_4), .in_b(b17_4to18_4), .out_a(a18_4to18_5), .out_b(b18_4to19_4), .out_c(matrixC18_4)); +processing_element pe18_5(.reset(effective_rst), .clk(clk), .in_a(a18_4to18_5), .in_b(b17_5to18_5), .out_a(a18_5to18_6), .out_b(b18_5to19_5), .out_c(matrixC18_5)); +processing_element pe18_6(.reset(effective_rst), .clk(clk), .in_a(a18_5to18_6), .in_b(b17_6to18_6), .out_a(a18_6to18_7), .out_b(b18_6to19_6), .out_c(matrixC18_6)); +processing_element pe18_7(.reset(effective_rst), .clk(clk), .in_a(a18_6to18_7), .in_b(b17_7to18_7), .out_a(a18_7to18_8), .out_b(b18_7to19_7), .out_c(matrixC18_7)); +processing_element pe18_8(.reset(effective_rst), .clk(clk), .in_a(a18_7to18_8), .in_b(b17_8to18_8), .out_a(a18_8to18_9), .out_b(b18_8to19_8), .out_c(matrixC18_8)); +processing_element pe18_9(.reset(effective_rst), .clk(clk), .in_a(a18_8to18_9), .in_b(b17_9to18_9), .out_a(a18_9to18_10), .out_b(b18_9to19_9), .out_c(matrixC18_9)); +processing_element pe18_10(.reset(effective_rst), .clk(clk), .in_a(a18_9to18_10), .in_b(b17_10to18_10), .out_a(a18_10to18_11), .out_b(b18_10to19_10), .out_c(matrixC18_10)); +processing_element pe18_11(.reset(effective_rst), .clk(clk), .in_a(a18_10to18_11), .in_b(b17_11to18_11), .out_a(a18_11to18_12), .out_b(b18_11to19_11), .out_c(matrixC18_11)); +processing_element pe18_12(.reset(effective_rst), .clk(clk), .in_a(a18_11to18_12), .in_b(b17_12to18_12), .out_a(a18_12to18_13), .out_b(b18_12to19_12), .out_c(matrixC18_12)); +processing_element pe18_13(.reset(effective_rst), .clk(clk), .in_a(a18_12to18_13), .in_b(b17_13to18_13), .out_a(a18_13to18_14), .out_b(b18_13to19_13), .out_c(matrixC18_13)); +processing_element pe18_14(.reset(effective_rst), .clk(clk), .in_a(a18_13to18_14), .in_b(b17_14to18_14), .out_a(a18_14to18_15), .out_b(b18_14to19_14), .out_c(matrixC18_14)); +processing_element pe18_15(.reset(effective_rst), .clk(clk), .in_a(a18_14to18_15), .in_b(b17_15to18_15), .out_a(a18_15to18_16), .out_b(b18_15to19_15), .out_c(matrixC18_15)); +processing_element pe18_16(.reset(effective_rst), .clk(clk), .in_a(a18_15to18_16), .in_b(b17_16to18_16), .out_a(a18_16to18_17), .out_b(b18_16to19_16), .out_c(matrixC18_16)); +processing_element pe18_17(.reset(effective_rst), .clk(clk), .in_a(a18_16to18_17), .in_b(b17_17to18_17), .out_a(a18_17to18_18), .out_b(b18_17to19_17), .out_c(matrixC18_17)); +processing_element pe18_18(.reset(effective_rst), .clk(clk), .in_a(a18_17to18_18), .in_b(b17_18to18_18), .out_a(a18_18to18_19), .out_b(b18_18to19_18), .out_c(matrixC18_18)); +processing_element pe18_19(.reset(effective_rst), .clk(clk), .in_a(a18_18to18_19), .in_b(b17_19to18_19), .out_a(a18_19to18_20), .out_b(b18_19to19_19), .out_c(matrixC18_19)); +processing_element pe19_1(.reset(effective_rst), .clk(clk), .in_a(a19_0to19_1), .in_b(b18_1to19_1), .out_a(a19_1to19_2), .out_b(b19_1to20_1), .out_c(matrixC19_1)); +processing_element pe19_2(.reset(effective_rst), .clk(clk), .in_a(a19_1to19_2), .in_b(b18_2to19_2), .out_a(a19_2to19_3), .out_b(b19_2to20_2), .out_c(matrixC19_2)); +processing_element pe19_3(.reset(effective_rst), .clk(clk), .in_a(a19_2to19_3), .in_b(b18_3to19_3), .out_a(a19_3to19_4), .out_b(b19_3to20_3), .out_c(matrixC19_3)); +processing_element pe19_4(.reset(effective_rst), .clk(clk), .in_a(a19_3to19_4), .in_b(b18_4to19_4), .out_a(a19_4to19_5), .out_b(b19_4to20_4), .out_c(matrixC19_4)); +processing_element pe19_5(.reset(effective_rst), .clk(clk), .in_a(a19_4to19_5), .in_b(b18_5to19_5), .out_a(a19_5to19_6), .out_b(b19_5to20_5), .out_c(matrixC19_5)); +processing_element pe19_6(.reset(effective_rst), .clk(clk), .in_a(a19_5to19_6), .in_b(b18_6to19_6), .out_a(a19_6to19_7), .out_b(b19_6to20_6), .out_c(matrixC19_6)); +processing_element pe19_7(.reset(effective_rst), .clk(clk), .in_a(a19_6to19_7), .in_b(b18_7to19_7), .out_a(a19_7to19_8), .out_b(b19_7to20_7), .out_c(matrixC19_7)); +processing_element pe19_8(.reset(effective_rst), .clk(clk), .in_a(a19_7to19_8), .in_b(b18_8to19_8), .out_a(a19_8to19_9), .out_b(b19_8to20_8), .out_c(matrixC19_8)); +processing_element pe19_9(.reset(effective_rst), .clk(clk), .in_a(a19_8to19_9), .in_b(b18_9to19_9), .out_a(a19_9to19_10), .out_b(b19_9to20_9), .out_c(matrixC19_9)); +processing_element pe19_10(.reset(effective_rst), .clk(clk), .in_a(a19_9to19_10), .in_b(b18_10to19_10), .out_a(a19_10to19_11), .out_b(b19_10to20_10), .out_c(matrixC19_10)); +processing_element pe19_11(.reset(effective_rst), .clk(clk), .in_a(a19_10to19_11), .in_b(b18_11to19_11), .out_a(a19_11to19_12), .out_b(b19_11to20_11), .out_c(matrixC19_11)); +processing_element pe19_12(.reset(effective_rst), .clk(clk), .in_a(a19_11to19_12), .in_b(b18_12to19_12), .out_a(a19_12to19_13), .out_b(b19_12to20_12), .out_c(matrixC19_12)); +processing_element pe19_13(.reset(effective_rst), .clk(clk), .in_a(a19_12to19_13), .in_b(b18_13to19_13), .out_a(a19_13to19_14), .out_b(b19_13to20_13), .out_c(matrixC19_13)); +processing_element pe19_14(.reset(effective_rst), .clk(clk), .in_a(a19_13to19_14), .in_b(b18_14to19_14), .out_a(a19_14to19_15), .out_b(b19_14to20_14), .out_c(matrixC19_14)); +processing_element pe19_15(.reset(effective_rst), .clk(clk), .in_a(a19_14to19_15), .in_b(b18_15to19_15), .out_a(a19_15to19_16), .out_b(b19_15to20_15), .out_c(matrixC19_15)); +processing_element pe19_16(.reset(effective_rst), .clk(clk), .in_a(a19_15to19_16), .in_b(b18_16to19_16), .out_a(a19_16to19_17), .out_b(b19_16to20_16), .out_c(matrixC19_16)); +processing_element pe19_17(.reset(effective_rst), .clk(clk), .in_a(a19_16to19_17), .in_b(b18_17to19_17), .out_a(a19_17to19_18), .out_b(b19_17to20_17), .out_c(matrixC19_17)); +processing_element pe19_18(.reset(effective_rst), .clk(clk), .in_a(a19_17to19_18), .in_b(b18_18to19_18), .out_a(a19_18to19_19), .out_b(b19_18to20_18), .out_c(matrixC19_18)); +processing_element pe19_19(.reset(effective_rst), .clk(clk), .in_a(a19_18to19_19), .in_b(b18_19to19_19), .out_a(a19_19to19_20), .out_b(b19_19to20_19), .out_c(matrixC19_19)); +assign a_data_out = {a19_19to19_20,a18_19to18_20,a17_19to17_20,a16_19to16_20,a15_19to15_20,a14_19to14_20,a13_19to13_20,a12_19to12_20,a11_19to11_20,a10_19to10_20,a9_19to9_20,a8_19to8_20,a7_19to7_20,a6_19to6_20,a5_19to5_20,a4_19to4_20,a3_19to3_20,a2_19to2_20,a1_19to1_20,a0_19to0_20}; +assign b_data_out = {b19_19to20_19,b19_18to20_18,b19_17to20_17,b19_16to20_16,b19_15to20_15,b19_14to20_14,b19_13to20_13,b19_12to20_12,b19_11to20_11,b19_10to20_10,b19_9to20_9,b19_8to20_8,b19_7to20_7,b19_6to20_6,b19_5to20_5,b19_4to20_4,b19_3to20_3,b19_2to20_2,b19_1to20_1,b19_0to20_0}; + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Definition of a processing element (basically a MAC) +////////////////////////////////////////////////////////////////////////// +module processing_element( + reset, + clk, + in_a, + in_b, + out_a, + out_b, + out_c + ); + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [`DWIDTH-1:0] in_b; + output [`DWIDTH-1:0] out_a; + output [`DWIDTH-1:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + reg [`DWIDTH-1:0] out_a; + reg [`DWIDTH-1:0] out_b; + wire [`DWIDTH-1:0] out_c; + + wire [`DWIDTH-1:0] out_mac; + + assign out_c = out_mac; + + `ifdef complex_dsp + mac_fp_16 u_mac(.a(in_a), .b(in_b), .out(out_mac), .reset(reset), .clk(clk)); + `else + seq_mac u_mac(.a(in_a), .b(in_b), .out(out_mac), .reset(reset), .clk(clk)); + `endif + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + out_b<=0; + end + else begin + out_a<=in_a; + out_b<=in_b; + end + end + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Multiply-and-accumulate (MAC) block +////////////////////////////////////////////////////////////////////////// +//module seq_mac(a, b, out, reset, clk); +//input [`DWIDTH-1:0] a; +//input [`DWIDTH-1:0] b; +//input reset; +//input clk; +//output [`DWIDTH-1:0] out; +// +//reg [2*`DWIDTH-1:0] out_temp; +//wire [`DWIDTH-1:0] mul_out; +//wire [2*`DWIDTH-1:0] add_out; +// +//reg [`DWIDTH-1:0] a_flopped; +//reg [`DWIDTH-1:0] b_flopped; +// +//wire [2*`DWIDTH-1:0] mul_out_temp; +//reg [2*`DWIDTH-1:0] mul_out_temp_reg; +// +//always @(posedge clk) begin +// if (reset) begin +// a_flopped <= 0; +// b_flopped <= 0; +// end else begin +// a_flopped <= a; +// b_flopped <= b; +// end +//end +// +////assign mul_out = a * b; +//qmult mult_u1(.i_multiplicand(a_flopped), .i_multiplier(b_flopped), .o_result(mul_out_temp)); +// +//always @(posedge clk) begin +// if (reset) begin +// mul_out_temp_reg <= 0; +// end else begin +// mul_out_temp_reg <= mul_out_temp; +// end +//end +// +////we just truncate the higher bits of the product +////assign add_out = mul_out + out; +//qadd add_u1(.a(out_temp), .b(mul_out_temp_reg), .c(add_out)); +// +//always @(posedge clk) begin +// if (reset) begin +// out_temp <= 0; +// end else begin +// out_temp <= add_out; +// end +//end +// +////down cast the result +//assign out = +// (out_temp[2*`DWIDTH-1] == 0) ? //positive number +// ( +// (|(out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 1, that means overlfow +// {out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b1}}} : //sign bit and then all 1s +// {out_temp[2*`DWIDTH-1] , out_temp[`DWIDTH-2:0]} +// ) +// : //negative number +// ( +// (|(out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 0, that means overlfow +// {out_temp[2*`DWIDTH-1] , out_temp[`DWIDTH-2:0]} : +// {out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b0}}} //sign bit and then all 0s +// ); +// +//endmodule +// +//module qmult(i_multiplicand,i_multiplier,o_result); +//input [`DWIDTH-1:0] i_multiplicand; +//input [`DWIDTH-1:0] i_multiplier; +//output [2*`DWIDTH-1:0] o_result; +// +//assign o_result = i_multiplicand * i_multiplier; +////DW02_mult #(`DWIDTH,`DWIDTH) u_mult(.A(i_multiplicand), .B(i_multiplier), .TC(1'b1), .PRODUCT(o_result)); +// +//endmodule +// +//module qadd(a,b,c); +//input [2*`DWIDTH-1:0] a; +//input [2*`DWIDTH-1:0] b; +//output [2*`DWIDTH-1:0] c; +// +//assign c = a + b; +////DW01_add #(`DWIDTH) u_add(.A(a), .B(b), .CI(1'b0), .SUM(c), .CO()); +//endmodule + +`ifndef complex_dsp + +////////////////////////////////////////////////////////////////////////// +// Multiply-and-accumulate (MAC) block +////////////////////////////////////////////////////////////////////////// +module seq_mac(a, b, out, reset, clk); +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +input reset; +input clk; +output [`DWIDTH-1:0] out; + +reg [2*`DWIDTH-1:0] out_temp; +wire [2*`DWIDTH-1:0] mul_out; +wire [2*`DWIDTH-1:0] add_out; + +reg [`DWIDTH-1:0] a_flopped; +reg [`DWIDTH-1:0] b_flopped; + +wire [2*`DWIDTH-1:0] mul_out_temp; +reg [2*`DWIDTH-1:0] mul_out_temp_reg; + +always @(posedge clk) begin + if (reset) begin + a_flopped <= 0; + b_flopped <= 0; + end else begin + a_flopped <= a; + b_flopped <= b; + end +end + +//assign mul_out = a * b; +qmult mult_u1(.clk(clk), .rst(reset), .i_multiplicand(a_flopped), .i_multiplier(b_flopped), .o_result(mul_out_temp)); + +always @(posedge clk) begin + if (reset) begin + mul_out_temp_reg <= 0; + end else begin + mul_out_temp_reg <= mul_out_temp; + end +end + +assign mul_out = mul_out_temp_reg; + +qadd add_u1(.clk(clk), .rst(reset), .a(out_temp), .b(mul_out), .c(add_out)); + +always @(posedge clk) begin + if (reset) begin + out_temp <= 0; + end else begin + out_temp <= add_out; + end +end + +//fp32 to fp16 conversion +wire [15:0] fpadd_16_result; +fp32_to_fp16 u_32to16 (.a(out_temp), .b(out)); + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Multiplier +////////////////////////////////////////////////////////////////////////// +module qmult(clk,rst,i_multiplicand,i_multiplier,o_result); +input clk; +input rst; +input [`DWIDTH-1:0] i_multiplicand; +input [`DWIDTH-1:0] i_multiplier; +output [2*`DWIDTH-1:0] o_result; + +wire fpmult_16_clk_NC; +wire fpmult_16_rst_NC; +wire [15:0] fpmult_16_result; +wire [4:0] fpmult_16_flags; + +FPMult_16 u_fpmult_16( + .clk(clk), + .rst(rst), + .a(i_multiplicand[15:0]), + .b(i_multiplier[15:0]), + .result(fpmult_16_result), + .flags(fpmult_16_flags) + ); + +//Convert fp16 to fp32 +fp16_to_fp32 u_16to32 (.clk(clk), .a(fpmult_16_result), .b(o_result)); + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Adder +////////////////////////////////////////////////////////////////////////// +module qadd(clk,rst,a,b,c); +input clk; +input rst; +input [2*`DWIDTH-1:0] a; +input [2*`DWIDTH-1:0] b; +output [2*`DWIDTH-1:0] c; + +wire fpadd_32_clk_NC; +wire fpadd_32_rst_NC; +wire [4:0] fpadd_32_flags; + +FPAddSub_single u_fpaddsub_32( + .clk(clk), + .rst(rst), + .a(a), + .b(b), + .operation(1'b0), + .result(c), + .flags(fpadd_32_flags)); + +endmodule +`endif + +`ifndef complex_dsp + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Definition of a 16-bit floating point multiplier +// This is a heavily modified version of: +// https://github.com/fbrosser/DSP48E1-FP/tree/master/src/FPMult +// Original author: Fredrik Brosser +// Abridged by: Samidh Mehta +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// + +module FPMult_16( + clk, + rst, + a, + b, + result, + flags + ); + + // Input Ports + input clk ; // Clock + input rst ; // Reset signal + input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number + + // Output ports + output [`DWIDTH-1:0] result ; // Product, result of the operation, 32-bit FP number + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Internal signals + wire [`DWIDTH-1:0] Z_int ; // Product, result of the operation, 32-bit FP number + wire [4:0] Flags_int ; // Flags indicating exceptions according to IEEE754 + + wire Sa ; // A's sign + wire Sb ; // B's sign + wire Sp ; // Product sign + wire [`EXPONENT-1:0] Ea ; // A's exponent + wire [`EXPONENT-1:0] Eb ; // B's exponent + wire [2*`MANTISSA+1:0] Mp ; // Product mantissa + wire [4:0] InputExc ; // Exceptions in inputs + wire [`MANTISSA-1:0] NormM ; // Normalized mantissa + wire [`EXPONENT:0] NormE ; // Normalized exponent + wire [`MANTISSA:0] RoundM ; // Normalized mantissa + wire [`EXPONENT:0] RoundE ; // Normalized exponent + wire [`MANTISSA:0] RoundMP ; // Normalized mantissa + wire [`EXPONENT:0] RoundEP ; // Normalized exponent + wire GRS ; + + //reg [63:0] pipe_0; // Pipeline register Input->Prep + reg [2*`DWIDTH-1:0] pipe_0; // Pipeline register Input->Prep + + //reg [92:0] pipe_1; // Pipeline register Prep->Execute + //reg [3*`MANTISSA+2*`EXPONENT+7:0] pipe_1; // Pipeline register Prep->Execute + reg [3*`MANTISSA+2*`EXPONENT+18:0] pipe_1; + + //reg [38:0] pipe_2; // Pipeline register Execute->Normalize + reg [`MANTISSA+`EXPONENT+7:0] pipe_2; // Pipeline register Execute->Normalize + + //reg [72:0] pipe_3; // Pipeline register Normalize->Round + reg [2*`MANTISSA+2*`EXPONENT+10:0] pipe_3; // Pipeline register Normalize->Round + + //reg [36:0] pipe_4; // Pipeline register Round->Output + reg [`DWIDTH+4:0] pipe_4; // Pipeline register Round->Output + + assign result = pipe_4[`DWIDTH+4:5] ; + assign flags = pipe_4[4:0] ; + + // Prepare the operands for alignment and check for exceptions + FPMult_PrepModule PrepModule(clk, rst, pipe_0[2*`DWIDTH-1:`DWIDTH], pipe_0[`DWIDTH-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]) ; + + // Perform (unsigned) mantissa multiplication + FPMult_ExecuteModule ExecuteModule(pipe_1[3*`MANTISSA+`EXPONENT*2+7:2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7:2*`MANTISSA+7], pipe_1[2*`MANTISSA+6:5], pipe_1[2*`MANTISSA+2*`EXPONENT+6:2*`MANTISSA+`EXPONENT+7], pipe_1[2*`MANTISSA+`EXPONENT+6:2*`MANTISSA+7], pipe_1[2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7], Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0], GRS) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + FPMult_NormalizeModule NormalizeModule(pipe_2[`MANTISSA-1:0], pipe_2[`MANTISSA+`EXPONENT:`MANTISSA], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + //FPMult_RoundModule RoundModule(pipe_3[47:24], pipe_3[23:0], pipe_3[65:57], pipe_3[56:48], pipe_3[66], pipe_3[67], pipe_3[72:68], Z_int[31:0], Flags_int[4:0]) ; + FPMult_RoundModule RoundModule(pipe_3[2*`MANTISSA+1:`MANTISSA+1], pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+2*`EXPONENT+3:2*`MANTISSA+`EXPONENT+3], pipe_3[2*`MANTISSA+`EXPONENT+2:2*`MANTISSA+2], pipe_3[2*`MANTISSA+2*`EXPONENT+4], pipe_3[2*`MANTISSA+2*`EXPONENT+5], pipe_3[2*`MANTISSA+2*`EXPONENT+10:2*`MANTISSA+2*`EXPONENT+6], Z_int[`DWIDTH-1:0], Flags_int[4:0]) ; + +//adding always@ (*) instead of posedge clock to make design combinational + always @ (posedge clk) begin + if(rst) begin + pipe_0 <= 0; + pipe_1 <= 0; + pipe_2 <= 0; + pipe_3 <= 0; + pipe_4 <= 0; + end + else begin + /* PIPE 0 + [2*`DWIDTH-1:`DWIDTH] A + [`DWIDTH-1:0] B + */ + pipe_0 <= {a, b} ; + + + /* PIPE 1 + [2*`EXPONENT+3*`MANTISSA + 18: 2*`EXPONENT+2*`MANTISSA + 18] //pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH] , mantissa of A + [2*`EXPONENT+2*`MANTISSA + 17 :2*`EXPONENT+2*`MANTISSA + 9] // pipe_0[8:0] + [2*`EXPONENT+2*`MANTISSA + 8] Sa + [2*`EXPONENT+2*`MANTISSA + 7] Sb + [2*`EXPONENT+2*`MANTISSA + 6:`EXPONENT+2*`MANTISSA+7] Ea + [`EXPONENT +2*`MANTISSA+6:2*`MANTISSA+7] Eb + [2*`MANTISSA+1+5:5] Mp + [4:0] InputExc + */ + //pipe_1 <= {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[`MANTISSA_MUL_SPLIT_LSB-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA-1:0], InputExc[4:0]} ; + pipe_1 <= {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[8:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]} ; + + /* PIPE 2 + [`EXPONENT + `MANTISSA + 7:`EXPONENT + `MANTISSA + 3] InputExc + [`EXPONENT + `MANTISSA + 2] GRS + [`EXPONENT + `MANTISSA + 1] Sp + [`EXPONENT + `MANTISSA:`MANTISSA] NormE + [`MANTISSA-1:0] NormM + */ + pipe_2 <= {pipe_1[4:0], GRS, Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0]} ; + /* PIPE 3 + [2*`EXPONENT+2*`MANTISSA+10:2*`EXPONENT+2*`MANTISSA+6] InputExc + [2*`EXPONENT+2*`MANTISSA+5] GRS + [2*`EXPONENT+2*`MANTISSA+4] Sp + [2*`EXPONENT+2*`MANTISSA+3:`EXPONENT+2*`MANTISSA+3] RoundE + [`EXPONENT+2*`MANTISSA+2:2*`MANTISSA+2] RoundEP + [2*`MANTISSA+1:`MANTISSA+1] RoundM + [`MANTISSA:0] RoundMP + */ + pipe_3 <= {pipe_2[`EXPONENT+`MANTISSA+7:`EXPONENT+`MANTISSA+1], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]} ; + /* PIPE 4 + [`DWIDTH+4:5] Z + [4:0] Flags + */ + pipe_4 <= {Z_int[`DWIDTH-1:0], Flags_int[4:0]} ; + end + end + +endmodule + + + +module FPMult_PrepModule ( + clk, + rst, + a, + b, + Sa, + Sb, + Ea, + Eb, + Mp, + InputExc + ); + + // Input ports + input clk ; + input rst ; + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [`EXPONENT-1:0] Ea ; // A's exponent + output [`EXPONENT-1:0] Eb ; // B's exponent + output [2*`MANTISSA+1:0] Mp ; // Mantissa product + output [4:0] InputExc ; // Input numbers are exceptions + + // Internal signals // If signal is high... + wire ANaN ; // A is a signalling NaN + wire BNaN ; // B is a signalling NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`MANTISSA-1:0] Ma; + wire [`MANTISSA-1:0] Mb; + + assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + + // Check for any exceptions and put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + //assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ; + + // Take input numbers apart + assign Sa = a[`DWIDTH-1] ; // A's sign + assign Sb = b[`DWIDTH-1] ; // B's sign + assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception + assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception +// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB]; + // assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB]; + + + + //assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ; + assign Mp = ({1'b1,a[`MANTISSA-1:0]}*{1'b1, b[`MANTISSA-1:0]}) ; + + + //We multiply part of the mantissa here + //Full mantissa of A + //Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B + // wire [`ACTUAL_MANTISSA-1:0] inp_A; + // wire [`ACTUAL_MANTISSA-1:0] inp_B; + // assign inp_A = {1'b1, Ma}; + // assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp)); +endmodule + + +module FPMult_ExecuteModule( + a, + b, + MpC, + Ea, + Eb, + Sa, + Sb, + Sp, + NormE, + NormM, + GRS + ); + + // Input ports + input [`MANTISSA-1:0] a ; + input [2*`EXPONENT:0] b ; + input [2*`MANTISSA+1:0] MpC ; + input [`EXPONENT-1:0] Ea ; // A's exponent + input [`EXPONENT-1:0] Eb ; // B's exponent + input Sa ; // A's sign + input Sb ; // B's sign + + // Output ports + output Sp ; // Product sign + output [`EXPONENT:0] NormE ; // Normalized exponent + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output GRS ; + + wire [2*`MANTISSA+1:0] Mp ; + + assign Sp = (Sa ^ Sb) ; // Equal signs give a positive product + + // wire [`ACTUAL_MANTISSA-1:0] inp_a; + // wire [`ACTUAL_MANTISSA-1:0] inp_b; + // assign inp_a = {1'b1, a}; + // assign inp_b = {{(`MANTISSA-`MANTISSA_MUL_SPLIT_LSB){1'b0}}, 1'b0, b}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_a), .B(inp_b), .TC(1'b0), .PRODUCT(Mp_temp)); + // DW01_add #(2*`ACTUAL_MANTISSA) u_add(.A(Mp_temp), .B(MpC<<`MANTISSA_MUL_SPLIT_LSB), .CI(1'b0), .SUM(Mp), .CO()); + + //assign Mp = (MpC<<(2*`EXPONENT+1)) + ({4'b0001, a[`MANTISSA-1:0]}*{1'b0, b[2*`EXPONENT:0]}) ; + assign Mp = MpC; + + + assign NormM = (Mp[2*`MANTISSA+1] ? Mp[2*`MANTISSA:`MANTISSA+1] : Mp[2*`MANTISSA-1:`MANTISSA]); // Check for overflow + assign NormE = (Ea + Eb + Mp[2*`MANTISSA+1]); // If so, increment exponent + + assign GRS = ((Mp[`MANTISSA]&(Mp[`MANTISSA+1]))|(|Mp[`MANTISSA-1:0])) ; + +endmodule + +module FPMult_NormalizeModule( + NormM, + NormE, + RoundE, + RoundEP, + RoundM, + RoundMP + ); + + // Input Ports + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input [`EXPONENT:0] NormE ; // Normalized exponent + + // Output Ports + output [`EXPONENT:0] RoundE ; + output [`EXPONENT:0] RoundEP ; + output [`MANTISSA:0] RoundM ; + output [`MANTISSA:0] RoundMP ; + +// EXPONENT = 5 +// EXPONENT -1 = 4 +// NEED to subtract 2^4 -1 = 15 + +wire [`EXPONENT-1 : 0] bias; + +assign bias = ((1<< (`EXPONENT -1)) -1); + + assign RoundE = NormE - bias ; + assign RoundEP = NormE - bias -1 ; + assign RoundM = NormM ; + assign RoundMP = NormM ; + +endmodule + +module FPMult_RoundModule( + RoundM, + RoundMP, + RoundE, + RoundEP, + Sp, + GRS, + InputExc, + Z, + Flags + ); + + // Input Ports + input [`MANTISSA:0] RoundM ; // Normalized mantissa + input [`MANTISSA:0] RoundMP ; // Normalized exponent + input [`EXPONENT:0] RoundE ; // Normalized mantissa + 1 + input [`EXPONENT:0] RoundEP ; // Normalized exponent + 1 + input Sp ; // Product sign + input GRS ; + input [4:0] InputExc ; + + // Output Ports + output [`DWIDTH-1:0] Z ; // Final product + output [4:0] Flags ; + + // Internal Signals + wire [`EXPONENT:0] FinalE ; // Rounded exponent + wire [`MANTISSA:0] FinalM; + wire [`MANTISSA:0] PreShiftM; + + assign PreShiftM = GRS ? RoundMP : RoundM ; // Round up if R and (G or S) + + // Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow) + assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]) ; + + assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done + + assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]} ; // Putting the pieces together + assign Flags = InputExc[4:0]; + +endmodule + +`endif + + +////////////////////////////////////////////////////////////////////////// +// A floating point 16-bit to floating point 32-bit converter +////////////////////////////////////////////////////////////////////////// +`ifndef complex_dsp +module fp16_to_fp32 (input clk, input [15:0] a , output [31:0] b); + +reg [31:0]b_temp; +reg [3:0] k_temp; + +always @ (posedge clk) begin + + if (a[14: 0] == 15'b0) begin //signed zero + b_temp [31] <= a[15]; //sign bit + b_temp[30:0] <= 31'b0; + end else begin + if (a[14:10] == 5'b0) begin //denormalized (covert to normalized) + if (a[9] == 1'b1) begin + k_temp <= 4'd0; + end else if (a[8] == 1'b1) begin + k_temp <= 4'd1; + end else if (a[7] == 1'b1) begin + k_temp <= 4'd2; + end else if (a[6] == 1'b1) begin + k_temp <= 4'd3; + end else if (a[5] == 1'b1) begin + k_temp <= 4'd4; + end else if (a[4] == 1'b1) begin + k_temp <= 4'd5; + end else if (a[3] == 1'b1) begin + k_temp <= 4'd6; + end else if (a[2] == 1'b1) begin + k_temp <= 4'd7; + end else if (a[1] == 1'b1) begin + k_temp <= 4'd8; + end else if (a[0] == 1'b1) begin + k_temp <= 4'd9; + end else begin + k_temp <= 4'd0; + end + b_temp [22:0] <= ( (a [9:0] << (k_temp+1'b1)) & 10'h3FF ) << 13; + b_temp [30:23] <= 7'd127 - 4'd15 - k_temp; + b_temp [31] <= a[15]; + end else if (a[14 : 10] == 5'b11111) begin //Infinity/ NAN + b_temp [22:0] <= a [9:0] << 13; + b_temp [30:23] <= 8'hFF; + b_temp [31] <= a[15]; + end else begin //Normalized Number + b_temp [22:0] <= a [9:0] << 13; + b_temp [30:23] <= 7'd127 - 4'd15 + a[14:10]; + b_temp [31] <= a[15]; + end + end +end + +assign b = b_temp; + + +endmodule + +////////////////////////////////////////////////////////////////////////// +// A floating point 32-bit to floating point 16-bit converter +////////////////////////////////////////////////////////////////////////// +module fp32_to_fp16 (input [31:0] a , output [15:0] b); + +reg [15:0]b_temp; +//integer j; +//reg [3:0]k; +always @ (*) begin + +if ( a [30: 0] == 15'b0 ) begin //signed zero + b_temp [15] = a[30]; //sign bit + b_temp [14:0] = 15'b0; +end + +else begin + + if ( a[30 : 23] <= 8'd112 && a[30 : 23] >= 8'd103 ) begin //denormalized (covert to normalized) + + b_temp [9:0] = {1'b1, a[22:13]} >> {8'd112 - a[30 : 23] + 1'b1} ; + b_temp [14:10] = 5'b0; + b_temp [15] = a[31]; + end + + else if ( a[ 30 : 23] == 8'b11111111 ) begin //Infinity/ NAN + b_temp [9:0] = a [22:13]; + b_temp [14:10] = 5'h1F; + b_temp [15] = a[31]; + end + + else begin //Normalized Number + b_temp [9:0] = a [22:13]; + b_temp [14:10] = 4'd15 - 7'd127 + a[30:23]; //number should be in the range which can be depicted by fp16 (exp for fp32: 70h, 8Eh ; normalized exp for fp32: -15 to 15) + b_temp [15] = a[31]; + end +end +end + +assign b = b_temp; + + +endmodule +`endif + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Definition of a 32-bit floating point adder/subtractor +// This is a heavily modified version of: +// https://github.com/fbrosser/DSP48E1-FP/tree/master/src/FP_AddSub +// Original author: Fredrik Brosser +// Abridged by: Samidh Mehta +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// + +`ifndef complex_dsp +module FPAddSub_single( + clk, + rst, + a, + b, + operation, + result, + flags + ); + +// Clock and reset + input clk ; // Clock signal + input rst ; // Reset (active high, resets pipeline registers) + + // Input ports + input [31:0] a ; // Input A, a 32-bit floating point number + input [31:0] b ; // Input B, a 32-bit floating point number + input operation ; // Operation select signal + + // Output ports + output [31:0] result ; // Result of the operation + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + reg [68:0]pipe_1; + reg [54:0]pipe_2; + reg [45:0]pipe_3; + + +//internal module wires + +//output ports + wire Opout; + wire Sa; + wire Sb; + wire MaxAB; + wire [7:0] CExp; + wire [4:0] Shift; + wire [22:0] Mmax; + wire [4:0] InputExc; + wire [23:0] Mmin_3; + + wire [32:0] SumS_5 ; + wire [4:0] Shift_1; + wire PSgn ; + wire Opr ; + + wire [22:0] NormM ; // Normalized mantissa + wire [8:0] NormE ; // Adjusted exponent + wire ZeroSum ; // Zero flag + wire NegE ; // Flag indicating negative exponent + wire R ; // Round bit + wire S ; // Final sticky bit + wire FG ; + +FPAddSub_a M1(a,b,operation,Opout,Sa,Sb,MaxAB,CExp,Shift,Mmax,InputExc,Mmin_3); + +FpAddSub_b M2(pipe_1[51:29],pipe_1[23:0],pipe_1[67],pipe_1[66],pipe_1[65],pipe_1[68],SumS_5,Shift_1,PSgn,Opr); + +FPAddSub_c M3(pipe_2[54:22],pipe_2[21:17],pipe_2[16:9],NormM,NormE,ZeroSum,NegE,R,S,FG); + +FPAddSub_d M4(pipe_3[13],pipe_3[22:14],pipe_3[45:23],pipe_3[11],pipe_3[10],pipe_3[9],pipe_3[8],pipe_3[7],pipe_3[6],pipe_3[5],pipe_3[12],pipe_3[4:0],result,flags ); + + +always @ (posedge clk) begin + if(rst) begin + pipe_1 <= 0; + pipe_2 <= 0; + pipe_3 <= 0; + end + else begin +/* +pipe_1: + [68] Opout; + [67] Sa; + [66] Sb; + [65] MaxAB; + [64:57] CExp; + [56:52] Shift; + [51:29] Mmax; + [28:24] InputExc; + [23:0] Mmin_3; + +*/ + +pipe_1 <= {Opout,Sa,Sb,MaxAB,CExp,Shift,Mmax,InputExc,Mmin_3}; + +/* +pipe_2: + [54:22]SumS_5; + [21:17]Shift; + [16:9]CExp; + [8]Sa; + [7]Sb; + [6]operation; + [5]MaxAB; + [4:0]InputExc +*/ + +pipe_2 <= {SumS_5,Shift_1,pipe_1[64:57], pipe_1[67], pipe_1[66], pipe_1[68], pipe_1[65], pipe_1[28:24] }; + +/* +pipe_3: + [45:23] NormM ; + [22:14] NormE ; + [13]ZeroSum ; + [12]NegE ; + [11]R ; + [10]S ; + [9]FG ; + [8]Sa; + [7]Sb; + [6]operation; + [5]MaxAB; + [4:0]InputExc +*/ + +pipe_3 <= {NormM,NormE,ZeroSum,NegE,R,S,FG, pipe_2[8], pipe_2[7], pipe_2[6], pipe_2[5], pipe_2[4:0] }; + +end +end + +endmodule + +// Prealign + Align + Shift 1 + Shift 2 +module FPAddSub_a( + A, + B, + operation, + Opout, + Sa, + Sb, + MaxAB, + CExp, + Shift, + Mmax, + InputExc, + Mmin_3 + + + ); + + // Input ports + input [31:0] A ; // Input A, a 32-bit floating point number + input [31:0] B ; // Input B, a 32-bit floating point number + input operation ; + + //output ports + output Opout; + output Sa; + output Sb; + output MaxAB; + output [7:0] CExp; + output [4:0] Shift; + output [22:0] Mmax; + output [4:0] InputExc; + output [23:0] Mmin_3; + + wire [9:0] ShiftDet ; + wire [30:0] Aout ; + wire [30:0] Bout ; + + + // Internal signals // If signal is high... + wire ANaN ; // A is a NaN (Not-a-Number) + wire BNaN ; // B is a NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [7:0] DAB ; // ExpA - ExpB + wire [7:0] DBA ; // ExpB - ExpA + + assign ANaN = &(A[30:23]) & |(A[22:0]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(B[30:23]) & |(B[22:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(A[30:23]) & ~|(A[22:0]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(B[30:23]) & ~|(B[22:0]) ; // All one exponent and all zero mantissa - Infinity + + // Put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + + //assign DAB = (A[30:23] - B[30:23]) ; + //assign DBA = (B[30:23] - A[30:23]) ; + assign DAB = (A[30:23] + ~(B[30:23]) + 1) ; + assign DBA = (B[30:23] + ~(A[30:23]) + 1) ; + + assign Sa = A[31] ; // A's sign bit + assign Sb = B[31] ; // B's sign bit + assign ShiftDet = {DBA[4:0], DAB[4:0]} ; // Shift data + assign Opout = operation ; + assign Aout = A[30:0] ; + assign Bout = B[30:0] ; + +///////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Output ports + // Number of steps to smaller mantissa shift right + wire [22:0] Mmin_1 ; // Smaller mantissa + + // Internal signals + //wire BOF ; // Check for shifting overflow if B is larger + //wire AOF ; // Check for shifting overflow if A is larger + + assign MaxAB = (Aout[30:0] < Bout[30:0]) ; + //assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits + //assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits + + // Determine final shift value + //assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ; + + assign Shift = MaxAB ? ShiftDet[9:5] : ShiftDet[4:0] ; + + // Take out smaller mantissa and append shift space + assign Mmin_1 = MaxAB ? Aout[22:0] : Bout[22:0] ; + + // Take out larger mantissa + assign Mmax = MaxAB ? Bout[22:0]: Aout[22:0] ; + + // Common exponent + assign CExp = (MaxAB ? Bout[30:23] : Aout[30:23]) ; + +// Input ports + // Smaller mantissa after 16|12|8|4 shift + wire [2:0] Shift_1 ; // Shift amount + + assign Shift_1 = Shift [4:2]; + + wire [23:0] Mmin_2 ; // The smaller mantissa + + // Internal signals + reg [23:0] Lvl1; + reg [23:0] Lvl2; + wire [47:0] Stage1; + integer i; // Loop variable + + always @(*) begin + // Rotate by 16? + Lvl1 <= Shift_1[2] ? {17'b00000000000000001, Mmin_1[22:16]} : {1'b1, Mmin_1}; + end + + assign Stage1 = {Lvl1, Lvl1}; + + always @(*) begin // Rotate {0 | 4 | 8 | 12} bits + case (Shift_1[1:0]) + // Rotate by 0 + 2'b00: Lvl2 <= Stage1[23:0]; + // Rotate by 4 + 2'b01: Lvl2 <= Stage1[27:4]; + // Rotate by 8 + 2'b10: Lvl2 <= Stage1[31:8]; + // Rotate by 12 + 2'b11: Lvl2 <= Stage1[35:12]; + endcase + end + + // Assign output to next shift stage + assign Mmin_2 = Lvl2; + // Smaller mantissa after 16|12|8|4 shift + wire [1:0] Shift_2 ; // Shift amount + + assign Shift_2 =Shift [1:0] ; + // The smaller mantissa + + // Internal Signal + reg [23:0] Lvl3; + wire [47:0] Stage2; + integer j; // Loop variable + + assign Stage2 = {Mmin_2, Mmin_2}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift_2[1:0]) + // Rotate by 0 + 2'b00: Lvl3 <= Stage2[23:0]; + // Rotate by 1 + 2'b01: Lvl3 <= Stage2[24:1]; + // Rotate by 2 + 2'b10: Lvl3 <= Stage2[25:2]; + // Rotate by 3 + 2'b11: Lvl3 <= Stage2[26:3]; + endcase + end + + // Assign output + assign Mmin_3 = Lvl3; + + +endmodule + +module FpAddSub_b( + Mmax, + Mmin, + Sa, + Sb, + MaxAB, + OpMode, + SumS_5, + Shift, + PSgn, + Opr +); + input [22:0] Mmax ; // The larger mantissa + input [23:0] Mmin ; // The smaller mantissa + input Sa ; // Sign bit of larger number + input Sb ; // Sign bit of smaller number + input MaxAB ; // Indicates the larger number (0/A, 1/B) + input OpMode ; // Operation to be performed (0/Add, 1/Sub) + + // Output ports + wire [32:0] Sum ; + // Output ports + output [32:0] SumS_5 ; // Mantissa after 16|0 shift + output [4:0] Shift ; // Shift amount // The result of the operation + output PSgn ; // The sign for the result + output Opr ; // The effective (performed) operation + + assign Opr = (OpMode^Sa^Sb); // Resolve sign to determine operation + + // Perform effective operation + assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, 8'b00000000} - {Mmin, 8'b00000000}) : ({1'b1, Mmax, 8'b00000000} + {Mmin, 8'b00000000}) ; + // Assign result sign + assign PSgn = (MaxAB ? Sb : Sa) ; + +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + // Determine normalization shift amount by finding leading nought + assign Shift = ( + Sum[32] ? 5'b00000 : + Sum[31] ? 5'b00001 : + Sum[30] ? 5'b00010 : + Sum[29] ? 5'b00011 : + Sum[28] ? 5'b00100 : + Sum[27] ? 5'b00101 : + Sum[26] ? 5'b00110 : + Sum[25] ? 5'b00111 : + Sum[24] ? 5'b01000 : + Sum[23] ? 5'b01001 : + Sum[22] ? 5'b01010 : + Sum[21] ? 5'b01011 : + Sum[20] ? 5'b01100 : + Sum[19] ? 5'b01101 : + Sum[18] ? 5'b01110 : + Sum[17] ? 5'b01111 : + Sum[16] ? 5'b10000 : + Sum[15] ? 5'b10001 : + Sum[14] ? 5'b10010 : + Sum[13] ? 5'b10011 : + Sum[12] ? 5'b10100 : + Sum[11] ? 5'b10101 : + Sum[10] ? 5'b10110 : + Sum[9] ? 5'b10111 : + Sum[8] ? 5'b11000 : + Sum[7] ? 5'b11001 : 5'b11010 + ); + + reg [32:0] Lvl1; + + always @(*) begin + // Rotate by 16? + Lvl1 <= Shift[4] ? {Sum[16:0], 16'b0000000000000000} : Sum; + end + + // Assign outputs + assign SumS_5 = Lvl1; + +endmodule + +module FPAddSub_c( + SumS_5, + Shift, + CExp, + NormM, + NormE, + ZeroSum, + NegE, + R, + S, + FG + ); + + // Input ports + input [32:0] SumS_5 ; // Smaller mantissa after 16|12|8|4 shift + + input [4:0] Shift ; // Shift amount + +// Input ports + + input [7:0] CExp ; + + + // Output ports + output [22:0] NormM ; // Normalized mantissa + output [8:0] NormE ; // Adjusted exponent + output ZeroSum ; // Zero flag + output NegE ; // Flag indicating negative exponent + output R ; // Round bit + output S ; // Final sticky bit + output FG ; + + + wire [3:0]Shift_1; + assign Shift_1 = Shift [3:0]; + // Output ports + wire [32:0] SumS_7 ; // The smaller mantissa + + reg [32:0] Lvl2; + wire [65:0] Stage1; + reg [32:0] Lvl3; + wire [65:0] Stage2; + integer i; // Loop variable + + assign Stage1 = {SumS_5, SumS_5}; + + always @(*) begin // Rotate {0 | 4 | 8 | 12} bits + case (Shift[3:2]) + // Rotate by 0 + 2'b00: Lvl2 <= Stage1[32:0]; + // Rotate by 4 + 2'b01: Lvl2 <= Stage1[61:29]; + // Rotate by 8 + 2'b10: Lvl2 <= Stage1[57:25]; + // Rotate by 12 + 2'b11: Lvl2 <= Stage1[53:21]; + endcase + end + + assign Stage2 = {Lvl2, Lvl2}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift_1[1:0]) + // Rotate by 0 + 2'b00: Lvl3 <= Stage2[32:0]; + // Rotate by 1 + 2'b01: Lvl3 <= Stage2[64:32]; + // Rotate by 2 + 2'b10: Lvl3 <= Stage2[63:31]; + // Rotate by 3 + 2'b11: Lvl3 <= Stage2[62:30]; + endcase + end + + // Assign outputs + assign SumS_7 = Lvl3; // Take out smaller mantissa + + + + + // Internal signals + wire MSBShift ; // Flag indicating that a second shift is needed + wire [8:0] ExpOF ; // MSB set in sum indicates overflow + wire [8:0] ExpOK ; // MSB not set, no adjustment + + // Calculate normalized exponent and mantissa, check for all-zero sum + assign MSBShift = SumS_7[32] ; // Check MSB in unnormalized sum + assign ZeroSum = ~|SumS_7 ; // Check for all zero sum + assign ExpOK = CExp - Shift ; // Adjust exponent for new normalized mantissa + assign NegE = ExpOK[8] ; // Check for exponent overflow + assign ExpOF = CExp - Shift + 1'b1 ; // If MSB set, add one to exponent(x2) + assign NormE = MSBShift ? ExpOF : ExpOK ; // Check for exponent overflow + assign NormM = SumS_7[31:9] ; // The new, normalized mantissa + + // Also need to compute sticky and round bits for the rounding stage + assign FG = SumS_7[8] ; + assign R = SumS_7[7] ; + assign S = |SumS_7[6:0] ; + +endmodule + +module FPAddSub_d( + ZeroSum, + NormE, + NormM, + R, + S, + G, + Sa, + Sb, + Ctrl, + MaxAB, + NegE, + InputExc, + P, + Flags + ); + + // Input ports + input ZeroSum ; // Sum is zero + input [8:0] NormE ; // Normalized exponent + input [22:0] NormM ; // Normalized mantissa + input R ; // Round bit + input S ; // Sticky bit + input G ; + input Sa ; // A's sign bit + input Sb ; // B's sign bit + input Ctrl ; // Control bit (operation) + input MaxAB ; + + + input NegE ; // Negative exponent? + input [4:0] InputExc ; // Exceptions in inputs A and B + + // Output ports + output [31:0] P ; // Final result + output [4:0] Flags ; // Exception flags + + // + wire [31:0] Z ; // Final result + wire EOF ; + + // Internal signals + wire [23:0] RoundUpM ; // Rounded up sum with room for overflow + wire [22:0] RoundM ; // The final rounded sum + wire [8:0] RoundE ; // Rounded exponent (note extra bit due to poential overflow ) + wire RoundUp ; // Flag indicating that the sum should be rounded up + wire ExpAdd ; // May have to add 1 to compensate for overflow + wire RoundOF ; // Rounding overflow + wire FSgn; + // The cases where we need to round upwards (= adding one) in Round to nearest, tie to even + assign RoundUp = (G & ((R | S) | NormM[0])) ; + + // Note that in the other cases (rounding down), the sum is already 'rounded' + assign RoundUpM = (NormM + 1) ; // The sum, rounded up by 1 + assign RoundM = (RoundUp ? RoundUpM[22:0] : NormM) ; // Compute final mantissa + assign RoundOF = RoundUp & RoundUpM[23] ; // Check for overflow when rounding up + + // Calculate post-rounding exponent + assign ExpAdd = (RoundOF ? 1'b1 : 1'b0) ; // Add 1 to exponent to compensate for overflow + assign RoundE = ZeroSum ? 8'b00000000 : (NormE + ExpAdd) ; // Final exponent + + // If zero, need to determine sign according to rounding + assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ; + + // Assign final result + assign Z = {FSgn, RoundE[7:0], RoundM[22:0]} ; + + // Indicate exponent overflow + assign EOF = RoundE[8]; + +///////////////////////////////////////////////////////////////////////////////////////////////////////// + + + + + // Internal signals + wire Overflow ; // Overflow flag + wire Underflow ; // Underflow flag + wire DivideByZero ; // Divide-by-Zero flag (always 0 in Add/Sub) + wire Invalid ; // Invalid inputs or result + wire Inexact ; // Result is inexact because of rounding + + // Exception flags + + // Result is too big to be represented + assign Overflow = EOF | InputExc[1] | InputExc[0] ; + + // Result is too small to be represented + assign Underflow = NegE & (R | S); + + // Infinite result computed exactly from finite operands + assign DivideByZero = &(Z[30:23]) & ~|(Z[30:23]) & ~InputExc[1] & ~InputExc[0]; + + // Invalid inputs or operation + assign Invalid = |(InputExc[4:2]) ; + + // Inexact answer due to rounding, overflow or underflow + assign Inexact = (R | S) | Overflow | Underflow; + + // Put pieces together to form final result + assign P = Z ; + + // Collect exception flags + assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact} ; + +endmodule +`endif + diff --git a/designs/koios/gemm_layer/gemm_random.sv b/designs/koios/gemm_layer/gemm_random.sv new file mode 100644 index 000000000..41fab7207 --- /dev/null +++ b/designs/koios/gemm_layer/gemm_random.sv @@ -0,0 +1,191 @@ +/* +Random I/Os for gemm_layer +*/ + +`include "../../random_number_generator.sv" + +`define BFLOAT16 + +// IEEE Half Precision => EXPONENT = 5, MANTISSA = 10 +// BFLOAT16 => EXPONENT = 8, MANTISSA = 7 + +`ifdef BFLOAT16 +`define EXPONENT 8 +`define MANTISSA 7 +`else // for ieee half precision fp16 +`define EXPONENT 5 +`define MANTISSA 10 +`endif + +`define SIGN 1 +`define DWIDTH (`SIGN+`EXPONENT+`MANTISSA) + +`define AWIDTH 8 +`define MEM_SIZE 256 + +`define MAT_MUL_SIZE 20 +`define MASK_WIDTH 20 +//This define isn't needed for this design, because we set a_loc and b_loc to 0 +`define LOG2_MAT_MUL_SIZE 4 + +`define BB_MAT_MUL_SIZE `MAT_MUL_SIZE +`define NUM_CYCLES_IN_MAC 3 +`define MEM_ACCESS_LATENCY 1 +`define ADDR_STRIDE_WIDTH 8 + +module gemm_random #( + parameter C_S00_AXI_DATA_WIDTH = 32, + parameter C_S00_AXI_ADDR_WIDTH = 6 +)( + // User ports ends + // Do not modify the ports beyond this line + + // Ports of Axi Slave Bus Interface S00_AXI + input wire logic s00_axi_aclk, + input wire logic s00_axi_aresetn, + input wire logic[C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr, + input wire logic[2 : 0] s00_axi_awprot, + input wire logic s00_axi_awvalid, + output logic s00_axi_awready, + input wire logic[C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata, + input wire logic[(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb, + input wire logic s00_axi_wvalid, + output logic s00_axi_wready, + output logic [1 : 0] s00_axi_bresp, + output logic s00_axi_bvalid, + input wire logic s00_axi_bready, + input wire logic[C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr, + input wire logic[2 : 0] s00_axi_arprot, + input wire logic s00_axi_arvalid, + output logic s00_axi_arready, + output logic [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata, + output logic [1 : 0] s00_axi_rresp, + output logic s00_axi_rvalid, + input wire logic s00_axi_rready, + input wire logic [1:0] abc_sel, + input wire logic [5:0] byte_sel, + output logic [14:0] addr_out, + output logic [7:0] data_out, + output logic[`MASK_WIDTH-1:0] mask_out, + output logic en_out +); + +logic[`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata [2:0]; +generate + genvar i; + for (i=0; i<3; i=i+1) begin: gen_rng + RandomNumberGenerator #( + .RANDOM_WIDTH(`MAT_MUL_SIZE*`DWIDTH), + .SEED(i) + ) rng ( + .clk(s00_axi_aclk), + .reset(s00_axi_aresetn), + .random_number(bram_rdata[i]) + ); + end +endgenerate + +logic [14:0] bram_addr [2:0]; +logic [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata [2:0]; +logic[`MASK_WIDTH-1:0] bram_we [2:0]; +logic bram_en [2:0]; + +assign en_out = (abc_sel[1:0] < 3) ? bram_en[abc_sel[1:0]] : 0; +assign addr_out = (abc_sel[1:0] < 3) ? bram_addr[abc_sel[1:0]] : 0; +assign mask_out = (abc_sel[1:0] < 3) ? bram_we[abc_sel[1:0]] : 0; + + +always_comb begin + if (abc_sel[1:0] == 3) begin + data_out = 0; + end + else begin + case(byte_sel[5:0]) + 6'd0: data_out = bram_wdata[abc_sel[1:0]][7:0]; + 6'd1: data_out = bram_wdata[abc_sel[1:0]][15:8]; + 6'd2: data_out = bram_wdata[abc_sel[1:0]][23:16]; + 6'd3: data_out = bram_wdata[abc_sel[1:0]][31:24]; + 6'd4: data_out = bram_wdata[abc_sel[1:0]][39:32]; + 6'd5: data_out = bram_wdata[abc_sel[1:0]][47:40]; + 6'd6: data_out = bram_wdata[abc_sel[1:0]][55:48]; + 6'd7: data_out = bram_wdata[abc_sel[1:0]][63:56]; + 6'd8: data_out = bram_wdata[abc_sel[1:0]][71:64]; + 6'd9: data_out = bram_wdata[abc_sel[1:0]][79:72]; + 6'd10: data_out = bram_wdata[abc_sel[1:0]][87:80]; + 6'd11: data_out = bram_wdata[abc_sel[1:0]][95:88]; + 6'd12: data_out = bram_wdata[abc_sel[1:0]][103:96]; + 6'd13: data_out = bram_wdata[abc_sel[1:0]][111:104]; + 6'd14: data_out = bram_wdata[abc_sel[1:0]][119:112]; + 6'd15: data_out = bram_wdata[abc_sel[1:0]][127:120]; + 6'd16: data_out = bram_wdata[abc_sel[1:0]][135:128]; + 6'd17: data_out = bram_wdata[abc_sel[1:0]][143:136]; + 6'd18: data_out = bram_wdata[abc_sel[1:0]][151:144]; + 6'd19: data_out = bram_wdata[abc_sel[1:0]][159:152]; + 6'd20: data_out = bram_wdata[abc_sel[1:0]][167:160]; + 6'd21: data_out = bram_wdata[abc_sel[1:0]][175:168]; + 6'd22: data_out = bram_wdata[abc_sel[1:0]][183:176]; + 6'd23: data_out = bram_wdata[abc_sel[1:0]][191:184]; + 6'd24: data_out = bram_wdata[abc_sel[1:0]][199:192]; + 6'd25: data_out = bram_wdata[abc_sel[1:0]][207:200]; + 6'd26: data_out = bram_wdata[abc_sel[1:0]][215:208]; + 6'd27: data_out = bram_wdata[abc_sel[1:0]][223:216]; + 6'd28: data_out = bram_wdata[abc_sel[1:0]][231:224]; + 6'd29: data_out = bram_wdata[abc_sel[1:0]][239:232]; + 6'd30: data_out = bram_wdata[abc_sel[1:0]][247:240]; + 6'd31: data_out = bram_wdata[abc_sel[1:0]][255:248]; + 6'd32: data_out = bram_wdata[abc_sel[1:0]][263:256]; + 6'd33: data_out = bram_wdata[abc_sel[1:0]][271:264]; + 6'd34: data_out = bram_wdata[abc_sel[1:0]][279:272]; + 6'd35: data_out = bram_wdata[abc_sel[1:0]][287:280]; + 6'd36: data_out = bram_wdata[abc_sel[1:0]][295:288]; + 6'd37: data_out = {3'b0, bram_wdata[abc_sel[1:0]][300:296]}; + default: data_out = 0; + endcase + end +end + + +gemm_layer #( + .C_S00_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH), + .C_S00_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH) +) gemm( + bram_addr[0], + bram_rdata[0], + bram_wdata[0], + bram_we[0], + bram_en[0], + bram_addr[1], + bram_rdata[1], + bram_wdata[1], + bram_we[1], + bram_en[1], + bram_addr[2], + bram_rdata[2], + bram_wdata[2], + bram_we[2], + bram_en[2], + s00_axi_aclk, + s00_axi_aresetn, + s00_axi_awaddr, + s00_axi_awprot, + s00_axi_awvalid, + s00_axi_awready, + s00_axi_wdata, + s00_axi_wstrb, + s00_axi_wvalid, + s00_axi_wready, + s00_axi_bresp, + s00_axi_bvalid, + s00_axi_bready, + s00_axi_araddr, + s00_axi_arprot, + s00_axi_arvalid, + s00_axi_arready, + s00_axi_rdata, + s00_axi_rresp, + s00_axi_rvalid, + s00_axi_rready +); + + +endmodule \ No newline at end of file diff --git a/designs/koios/lenet/design.yaml b/designs/koios/lenet/design.yaml new file mode 100644 index 000000000..b23d163d1 --- /dev/null +++ b/designs/koios/lenet/design.yaml @@ -0,0 +1 @@ +top: myproject diff --git a/designs/koios/lenet/lenet.v b/designs/koios/lenet/lenet.v new file mode 100644 index 000000000..7ce1f3d3e --- /dev/null +++ b/designs/koios/lenet/lenet.v @@ -0,0 +1,227190 @@ +////////////////////////////////////////////////////////////////////////////// +// HLS generated design for Lenet +////////////////////////////////////////////////////////////////////////////// + +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +////////////////////////////////////////////////////////////////////////////// +// Abridged for VTR by: Aman Arora +////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns / 1 ps + +module cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + p_read, + op_V_assign_out_din, + op_V_assign_out_full_n, + op_V_assign_out_write +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] p_read; +output [7:0] op_V_assign_out_din; +input op_V_assign_out_full_n; +output op_V_assign_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_out_write; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_out_blk_n; +reg ap_block_state1; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_blk_n = op_V_assign_out_full_n; + end else begin + op_V_assign_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_write = 1'b1; + end else begin + op_V_assign_out_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign op_V_assign_out_din = p_read; + +endmodule //cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110 +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + p_read, + op_V_assign_out_din, + op_V_assign_out_full_n, + op_V_assign_out_write +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] p_read; +output [7:0] op_V_assign_out_din; +input op_V_assign_out_full_n; +output op_V_assign_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_out_write; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_out_blk_n; +reg ap_block_state1; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_blk_n = op_V_assign_out_full_n; + end else begin + op_V_assign_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_write = 1'b1; + end else begin + op_V_assign_out_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign op_V_assign_out_din = p_read; + +endmodule //cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111 +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + p_read, + op_V_assign_out_din, + op_V_assign_out_full_n, + op_V_assign_out_write +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] p_read; +output [7:0] op_V_assign_out_din; +input op_V_assign_out_full_n; +output op_V_assign_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_out_write; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_out_blk_n; +reg ap_block_state1; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_blk_n = op_V_assign_out_full_n; + end else begin + op_V_assign_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_write = 1'b1; + end else begin + op_V_assign_out_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign op_V_assign_out_din = p_read; + +endmodule //cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112 +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + p_read, + op_V_assign_out_din, + op_V_assign_out_full_n, + op_V_assign_out_write +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] p_read; +output [7:0] op_V_assign_out_din; +input op_V_assign_out_full_n; +output op_V_assign_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_out_write; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_out_blk_n; +reg ap_block_state1; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_blk_n = op_V_assign_out_full_n; + end else begin + op_V_assign_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_write = 1'b1; + end else begin + op_V_assign_out_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign op_V_assign_out_din = p_read; + +endmodule //cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113 +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + p_read, + op_V_assign_out_din, + op_V_assign_out_full_n, + op_V_assign_out_write +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] p_read; +output [7:0] op_V_assign_out_din; +input op_V_assign_out_full_n; +output op_V_assign_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_out_write; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_out_blk_n; +reg ap_block_state1; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_blk_n = op_V_assign_out_full_n; + end else begin + op_V_assign_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_write = 1'b1; + end else begin + op_V_assign_out_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign op_V_assign_out_din = p_read; + +endmodule //cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114 +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + p_read, + op_V_assign_out_din, + op_V_assign_out_full_n, + op_V_assign_out_write +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] p_read; +output [7:0] op_V_assign_out_din; +input op_V_assign_out_full_n; +output op_V_assign_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_out_write; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_out_blk_n; +reg ap_block_state1; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_blk_n = op_V_assign_out_full_n; + end else begin + op_V_assign_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_write = 1'b1; + end else begin + op_V_assign_out_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign op_V_assign_out_din = p_read; + +endmodule //cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115 +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + p_read, + op_V_assign_out_din, + op_V_assign_out_full_n, + op_V_assign_out_write +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] p_read; +output [7:0] op_V_assign_out_din; +input op_V_assign_out_full_n; +output op_V_assign_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_out_write; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_out_blk_n; +reg ap_block_state1; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_blk_n = op_V_assign_out_full_n; + end else begin + op_V_assign_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_write = 1'b1; + end else begin + op_V_assign_out_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign op_V_assign_out_din = p_read; + +endmodule //cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116 +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + p_read, + op_V_assign_out_din, + op_V_assign_out_full_n, + op_V_assign_out_write +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] p_read; +output [7:0] op_V_assign_out_din; +input op_V_assign_out_full_n; +output op_V_assign_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_out_write; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_out_blk_n; +reg ap_block_state1; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_blk_n = op_V_assign_out_full_n; + end else begin + op_V_assign_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_write = 1'b1; + end else begin + op_V_assign_out_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign op_V_assign_out_din = p_read; + +endmodule //cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117 +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + p_read, + op_V_assign_out_din, + op_V_assign_out_full_n, + op_V_assign_out_write +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] p_read; +output [7:0] op_V_assign_out_din; +input op_V_assign_out_full_n; +output op_V_assign_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_out_write; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_out_blk_n; +reg ap_block_state1; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_blk_n = op_V_assign_out_full_n; + end else begin + op_V_assign_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_out_write = 1'b1; + end else begin + op_V_assign_out_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign op_V_assign_out_din = p_read; + +endmodule //cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118 +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_s ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + p_read, + agg_result_V_din, + agg_result_V_full_n, + agg_result_V_write +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +input [7:0] p_read; +output [7:0] agg_result_V_din; +input agg_result_V_full_n; +output agg_result_V_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg agg_result_V_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg internal_ap_ready; +reg agg_result_V_blk_n; +reg ap_block_state1; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (1'b0 == agg_result_V_full_n) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((internal_ap_ready == 1'b0) & (real_start == 1'b1))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + agg_result_V_blk_n = agg_result_V_full_n; + end else begin + agg_result_V_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (1'b0 == agg_result_V_full_n) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + agg_result_V_write = 1'b1; + end else begin + agg_result_V_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (1'b0 == agg_result_V_full_n) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (real_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (1'b0 == agg_result_V_full_n) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((start_once_reg == 1'b0) & (real_start == 1'b1))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +assign agg_result_V_din = p_read; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (1'b0 == agg_result_V_full_n) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign start_out = real_start; + +endmodule //cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_s +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 8; +parameter AWIDTH = 6; +parameter MEM_SIZE = 37; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd8; +parameter AddressRange = 32'd37; +parameter AddressWidth = 32'd6; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V_ram conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 8; +parameter AWIDTH = 6; +parameter MEM_SIZE = 36; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd8; +parameter AddressRange = 32'd36; +parameter AddressWidth = 32'd6; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V_ram conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V_ram (addr0, ce0, d0, we0, q0, clk); + +parameter DWIDTH = 8; +parameter AWIDTH = 14; +parameter MEM_SIZE = 8400; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V( + reset, + clk, + address0, + ce0, + we0, + d0, + q0); + +parameter DataWidth = 32'd8; +parameter AddressRange = 32'd8400; +parameter AddressWidth = 32'd14; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; + + + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V_ram conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_idle, + ap_ready, + data_0_V_address0, + data_0_V_ce0, + data_0_V_q0, + data_1_V_address0, + data_1_V_ce0, + data_1_V_q0, + data_2_V_address0, + data_2_V_ce0, + data_2_V_q0, + data_3_V_address0, + data_3_V_ce0, + data_3_V_q0, + data_4_V_address0, + data_4_V_ce0, + data_4_V_q0, + data_5_V_address0, + data_5_V_ce0, + data_5_V_q0, + data_6_V_address0, + data_6_V_ce0, + data_6_V_q0, + data_7_V_address0, + data_7_V_ce0, + data_7_V_q0, + data_8_V_address0, + data_8_V_ce0, + data_8_V_q0, + data_9_V_address0, + data_9_V_ce0, + data_9_V_q0, + data_10_V_address0, + data_10_V_ce0, + data_10_V_q0, + data_11_V_address0, + data_11_V_ce0, + data_11_V_q0, + data_12_V_address0, + data_12_V_ce0, + data_12_V_q0, + data_13_V_address0, + data_13_V_ce0, + data_13_V_q0, + data_14_V_address0, + data_14_V_ce0, + data_14_V_q0, + data_15_V_address0, + data_15_V_ce0, + data_15_V_q0, + data_16_V_address0, + data_16_V_ce0, + data_16_V_q0, + data_17_V_address0, + data_17_V_ce0, + data_17_V_q0, + data_18_V_address0, + data_18_V_ce0, + data_18_V_q0, + data_19_V_address0, + data_19_V_ce0, + data_19_V_q0, + data_20_V_address0, + data_20_V_ce0, + data_20_V_q0, + data_21_V_address0, + data_21_V_ce0, + data_21_V_q0, + data_22_V_address0, + data_22_V_ce0, + data_22_V_q0, + data_23_V_address0, + data_23_V_ce0, + data_23_V_q0, + data_24_V_address0, + data_24_V_ce0, + data_24_V_q0, + data_25_V_address0, + data_25_V_ce0, + data_25_V_q0, + data_26_V_address0, + data_26_V_ce0, + data_26_V_q0, + data_27_V_address0, + data_27_V_ce0, + data_27_V_q0, + data_28_V_address0, + data_28_V_ce0, + data_28_V_q0, + data_29_V_address0, + data_29_V_ce0, + data_29_V_q0, + data_30_V_address0, + data_30_V_ce0, + data_30_V_q0, + data_31_V_address0, + data_31_V_ce0, + data_31_V_q0, + data_32_V_address0, + data_32_V_ce0, + data_32_V_q0, + data_33_V_address0, + data_33_V_ce0, + data_33_V_q0, + data_34_V_address0, + data_34_V_ce0, + data_34_V_q0, + data_35_V_address0, + data_35_V_ce0, + data_35_V_q0, + data_36_V_address0, + data_36_V_ce0, + data_36_V_q0, + data_37_V_address0, + data_37_V_ce0, + data_37_V_q0, + data_38_V_address0, + data_38_V_ce0, + data_38_V_q0, + data_39_V_address0, + data_39_V_ce0, + data_39_V_q0, + data_40_V_address0, + data_40_V_ce0, + data_40_V_q0, + data_41_V_address0, + data_41_V_ce0, + data_41_V_q0, + data_42_V_address0, + data_42_V_ce0, + data_42_V_q0, + data_43_V_address0, + data_43_V_ce0, + data_43_V_q0, + data_44_V_address0, + data_44_V_ce0, + data_44_V_q0, + data_45_V_address0, + data_45_V_ce0, + data_45_V_q0, + data_46_V_address0, + data_46_V_ce0, + data_46_V_q0, + data_47_V_address0, + data_47_V_ce0, + data_47_V_q0, + data_48_V_address0, + data_48_V_ce0, + data_48_V_q0, + data_49_V_address0, + data_49_V_ce0, + data_49_V_q0, + data_50_V_address0, + data_50_V_ce0, + data_50_V_q0, + data_51_V_address0, + data_51_V_ce0, + data_51_V_q0, + data_52_V_address0, + data_52_V_ce0, + data_52_V_q0, + data_53_V_address0, + data_53_V_ce0, + data_53_V_q0, + data_54_V_address0, + data_54_V_ce0, + data_54_V_q0, + data_55_V_address0, + data_55_V_ce0, + data_55_V_q0, + data_56_V_address0, + data_56_V_ce0, + data_56_V_q0, + data_57_V_address0, + data_57_V_ce0, + data_57_V_q0, + data_58_V_address0, + data_58_V_ce0, + data_58_V_q0, + data_59_V_address0, + data_59_V_ce0, + data_59_V_q0, + data_60_V_address0, + data_60_V_ce0, + data_60_V_q0, + data_61_V_address0, + data_61_V_ce0, + data_61_V_q0, + data_62_V_address0, + data_62_V_ce0, + data_62_V_q0, + data_63_V_address0, + data_63_V_ce0, + data_63_V_q0, + data_64_V_address0, + data_64_V_ce0, + data_64_V_q0, + data_65_V_address0, + data_65_V_ce0, + data_65_V_q0, + data_66_V_address0, + data_66_V_ce0, + data_66_V_q0, + data_67_V_address0, + data_67_V_ce0, + data_67_V_q0, + data_68_V_address0, + data_68_V_ce0, + data_68_V_q0, + data_69_V_address0, + data_69_V_ce0, + data_69_V_q0, + data_70_V_address0, + data_70_V_ce0, + data_70_V_q0, + data_71_V_address0, + data_71_V_ce0, + data_71_V_q0, + data_72_V_address0, + data_72_V_ce0, + data_72_V_q0, + data_73_V_address0, + data_73_V_ce0, + data_73_V_q0, + data_74_V_address0, + data_74_V_ce0, + data_74_V_q0, + data_75_V_address0, + data_75_V_ce0, + data_75_V_q0, + data_76_V_address0, + data_76_V_ce0, + data_76_V_q0, + data_77_V_address0, + data_77_V_ce0, + data_77_V_q0, + data_78_V_address0, + data_78_V_ce0, + data_78_V_q0, + data_79_V_address0, + data_79_V_ce0, + data_79_V_q0, + data_80_V_address0, + data_80_V_ce0, + data_80_V_q0, + data_81_V_address0, + data_81_V_ce0, + data_81_V_q0, + data_82_V_address0, + data_82_V_ce0, + data_82_V_q0, + data_83_V_address0, + data_83_V_ce0, + data_83_V_q0, + data_84_V_address0, + data_84_V_ce0, + data_84_V_q0, + data_85_V_address0, + data_85_V_ce0, + data_85_V_q0, + data_86_V_address0, + data_86_V_ce0, + data_86_V_q0, + data_87_V_address0, + data_87_V_ce0, + data_87_V_q0, + data_88_V_address0, + data_88_V_ce0, + data_88_V_q0, + data_89_V_address0, + data_89_V_ce0, + data_89_V_q0, + data_90_V_address0, + data_90_V_ce0, + data_90_V_q0, + data_91_V_address0, + data_91_V_ce0, + data_91_V_q0, + data_92_V_address0, + data_92_V_ce0, + data_92_V_q0, + data_93_V_address0, + data_93_V_ce0, + data_93_V_q0, + data_94_V_address0, + data_94_V_ce0, + data_94_V_q0, + data_95_V_address0, + data_95_V_ce0, + data_95_V_q0, + data_96_V_address0, + data_96_V_ce0, + data_96_V_q0, + data_97_V_address0, + data_97_V_ce0, + data_97_V_q0, + data_98_V_address0, + data_98_V_ce0, + data_98_V_q0, + data_99_V_address0, + data_99_V_ce0, + data_99_V_q0, + data_100_V_address0, + data_100_V_ce0, + data_100_V_q0, + data_101_V_address0, + data_101_V_ce0, + data_101_V_q0, + data_102_V_address0, + data_102_V_ce0, + data_102_V_q0, + data_103_V_address0, + data_103_V_ce0, + data_103_V_q0, + data_104_V_address0, + data_104_V_ce0, + data_104_V_q0, + data_105_V_address0, + data_105_V_ce0, + data_105_V_q0, + data_106_V_address0, + data_106_V_ce0, + data_106_V_q0, + data_107_V_address0, + data_107_V_ce0, + data_107_V_q0, + data_108_V_address0, + data_108_V_ce0, + data_108_V_q0, + data_109_V_address0, + data_109_V_ce0, + data_109_V_q0, + data_110_V_address0, + data_110_V_ce0, + data_110_V_q0, + data_111_V_address0, + data_111_V_ce0, + data_111_V_q0, + data_112_V_address0, + data_112_V_ce0, + data_112_V_q0, + data_113_V_address0, + data_113_V_ce0, + data_113_V_q0, + data_114_V_address0, + data_114_V_ce0, + data_114_V_q0, + data_115_V_address0, + data_115_V_ce0, + data_115_V_q0, + data_116_V_address0, + data_116_V_ce0, + data_116_V_q0, + data_117_V_address0, + data_117_V_ce0, + data_117_V_q0, + data_118_V_address0, + data_118_V_ce0, + data_118_V_q0, + data_119_V_address0, + data_119_V_ce0, + data_119_V_q0, + data_120_V_address0, + data_120_V_ce0, + data_120_V_q0, + data_121_V_address0, + data_121_V_ce0, + data_121_V_q0, + data_122_V_address0, + data_122_V_ce0, + data_122_V_q0, + data_123_V_address0, + data_123_V_ce0, + data_123_V_q0, + data_124_V_address0, + data_124_V_ce0, + data_124_V_q0, + data_125_V_address0, + data_125_V_ce0, + data_125_V_q0, + data_126_V_address0, + data_126_V_ce0, + data_126_V_q0, + data_127_V_address0, + data_127_V_ce0, + data_127_V_q0, + res_0_V_address0, + res_0_V_ce0, + res_0_V_we0, + res_0_V_d0, + res_1_V_address0, + res_1_V_ce0, + res_1_V_we0, + res_1_V_d0, + res_2_V_address0, + res_2_V_ce0, + res_2_V_we0, + res_2_V_d0, + res_3_V_address0, + res_3_V_ce0, + res_3_V_we0, + res_3_V_d0, + res_4_V_address0, + res_4_V_ce0, + res_4_V_we0, + res_4_V_d0, + res_5_V_address0, + res_5_V_ce0, + res_5_V_we0, + res_5_V_d0, + res_6_V_address0, + res_6_V_ce0, + res_6_V_we0, + res_6_V_d0, + res_7_V_address0, + res_7_V_ce0, + res_7_V_we0, + res_7_V_d0, + res_8_V_address0, + res_8_V_ce0, + res_8_V_we0, + res_8_V_d0, + res_9_V_address0, + res_9_V_ce0, + res_9_V_we0, + res_9_V_d0, + res_10_V_address0, + res_10_V_ce0, + res_10_V_we0, + res_10_V_d0, + res_11_V_address0, + res_11_V_ce0, + res_11_V_we0, + res_11_V_d0, + res_12_V_address0, + res_12_V_ce0, + res_12_V_we0, + res_12_V_d0, + res_13_V_address0, + res_13_V_ce0, + res_13_V_we0, + res_13_V_d0, + res_14_V_address0, + res_14_V_ce0, + res_14_V_we0, + res_14_V_d0, + res_15_V_address0, + res_15_V_ce0, + res_15_V_we0, + res_15_V_d0, + res_16_V_address0, + res_16_V_ce0, + res_16_V_we0, + res_16_V_d0, + res_17_V_address0, + res_17_V_ce0, + res_17_V_we0, + res_17_V_d0, + res_18_V_address0, + res_18_V_ce0, + res_18_V_we0, + res_18_V_d0, + res_19_V_address0, + res_19_V_ce0, + res_19_V_we0, + res_19_V_d0, + res_20_V_address0, + res_20_V_ce0, + res_20_V_we0, + res_20_V_d0, + res_21_V_address0, + res_21_V_ce0, + res_21_V_we0, + res_21_V_d0, + res_22_V_address0, + res_22_V_ce0, + res_22_V_we0, + res_22_V_d0, + res_23_V_address0, + res_23_V_ce0, + res_23_V_we0, + res_23_V_d0, + res_24_V_address0, + res_24_V_ce0, + res_24_V_we0, + res_24_V_d0, + res_25_V_address0, + res_25_V_ce0, + res_25_V_we0, + res_25_V_d0, + res_26_V_address0, + res_26_V_ce0, + res_26_V_we0, + res_26_V_d0, + res_27_V_address0, + res_27_V_ce0, + res_27_V_we0, + res_27_V_d0, + res_28_V_address0, + res_28_V_ce0, + res_28_V_we0, + res_28_V_d0, + res_29_V_address0, + res_29_V_ce0, + res_29_V_we0, + res_29_V_d0, + res_30_V_address0, + res_30_V_ce0, + res_30_V_we0, + res_30_V_d0, + res_31_V_address0, + res_31_V_ce0, + res_31_V_we0, + res_31_V_d0, + res_32_V_address0, + res_32_V_ce0, + res_32_V_we0, + res_32_V_d0, + res_33_V_address0, + res_33_V_ce0, + res_33_V_we0, + res_33_V_d0, + res_34_V_address0, + res_34_V_ce0, + res_34_V_we0, + res_34_V_d0, + res_35_V_address0, + res_35_V_ce0, + res_35_V_we0, + res_35_V_d0, + res_36_V_address0, + res_36_V_ce0, + res_36_V_we0, + res_36_V_d0, + res_37_V_address0, + res_37_V_ce0, + res_37_V_we0, + res_37_V_d0, + res_38_V_address0, + res_38_V_ce0, + res_38_V_we0, + res_38_V_d0, + res_39_V_address0, + res_39_V_ce0, + res_39_V_we0, + res_39_V_d0, + res_40_V_address0, + res_40_V_ce0, + res_40_V_we0, + res_40_V_d0, + res_41_V_address0, + res_41_V_ce0, + res_41_V_we0, + res_41_V_d0, + res_42_V_address0, + res_42_V_ce0, + res_42_V_we0, + res_42_V_d0, + res_43_V_address0, + res_43_V_ce0, + res_43_V_we0, + res_43_V_d0, + res_44_V_address0, + res_44_V_ce0, + res_44_V_we0, + res_44_V_d0, + res_45_V_address0, + res_45_V_ce0, + res_45_V_we0, + res_45_V_d0, + res_46_V_address0, + res_46_V_ce0, + res_46_V_we0, + res_46_V_d0, + res_47_V_address0, + res_47_V_ce0, + res_47_V_we0, + res_47_V_d0, + res_48_V_address0, + res_48_V_ce0, + res_48_V_we0, + res_48_V_d0, + res_49_V_address0, + res_49_V_ce0, + res_49_V_we0, + res_49_V_d0, + res_50_V_address0, + res_50_V_ce0, + res_50_V_we0, + res_50_V_d0, + res_51_V_address0, + res_51_V_ce0, + res_51_V_we0, + res_51_V_d0, + res_52_V_address0, + res_52_V_ce0, + res_52_V_we0, + res_52_V_d0, + res_53_V_address0, + res_53_V_ce0, + res_53_V_we0, + res_53_V_d0, + res_54_V_address0, + res_54_V_ce0, + res_54_V_we0, + res_54_V_d0, + res_55_V_address0, + res_55_V_ce0, + res_55_V_we0, + res_55_V_d0, + res_56_V_address0, + res_56_V_ce0, + res_56_V_we0, + res_56_V_d0, + res_57_V_address0, + res_57_V_ce0, + res_57_V_we0, + res_57_V_d0, + res_58_V_address0, + res_58_V_ce0, + res_58_V_we0, + res_58_V_d0, + res_59_V_address0, + res_59_V_ce0, + res_59_V_we0, + res_59_V_d0, + res_60_V_address0, + res_60_V_ce0, + res_60_V_we0, + res_60_V_d0, + res_61_V_address0, + res_61_V_ce0, + res_61_V_we0, + res_61_V_d0, + res_62_V_address0, + res_62_V_ce0, + res_62_V_we0, + res_62_V_d0, + res_63_V_address0, + res_63_V_ce0, + res_63_V_we0, + res_63_V_d0, + res_64_V_address0, + res_64_V_ce0, + res_64_V_we0, + res_64_V_d0, + res_65_V_address0, + res_65_V_ce0, + res_65_V_we0, + res_65_V_d0, + res_66_V_address0, + res_66_V_ce0, + res_66_V_we0, + res_66_V_d0, + res_67_V_address0, + res_67_V_ce0, + res_67_V_we0, + res_67_V_d0, + res_68_V_address0, + res_68_V_ce0, + res_68_V_we0, + res_68_V_d0, + res_69_V_address0, + res_69_V_ce0, + res_69_V_we0, + res_69_V_d0, + res_70_V_address0, + res_70_V_ce0, + res_70_V_we0, + res_70_V_d0, + res_71_V_address0, + res_71_V_ce0, + res_71_V_we0, + res_71_V_d0, + res_72_V_address0, + res_72_V_ce0, + res_72_V_we0, + res_72_V_d0, + res_73_V_address0, + res_73_V_ce0, + res_73_V_we0, + res_73_V_d0, + res_74_V_address0, + res_74_V_ce0, + res_74_V_we0, + res_74_V_d0, + res_75_V_address0, + res_75_V_ce0, + res_75_V_we0, + res_75_V_d0, + res_76_V_address0, + res_76_V_ce0, + res_76_V_we0, + res_76_V_d0, + res_77_V_address0, + res_77_V_ce0, + res_77_V_we0, + res_77_V_d0, + res_78_V_address0, + res_78_V_ce0, + res_78_V_we0, + res_78_V_d0, + res_79_V_address0, + res_79_V_ce0, + res_79_V_we0, + res_79_V_d0, + res_80_V_address0, + res_80_V_ce0, + res_80_V_we0, + res_80_V_d0, + res_81_V_address0, + res_81_V_ce0, + res_81_V_we0, + res_81_V_d0, + res_82_V_address0, + res_82_V_ce0, + res_82_V_we0, + res_82_V_d0, + res_83_V_address0, + res_83_V_ce0, + res_83_V_we0, + res_83_V_d0, + res_84_V_address0, + res_84_V_ce0, + res_84_V_we0, + res_84_V_d0, + res_85_V_address0, + res_85_V_ce0, + res_85_V_we0, + res_85_V_d0, + res_86_V_address0, + res_86_V_ce0, + res_86_V_we0, + res_86_V_d0, + res_87_V_address0, + res_87_V_ce0, + res_87_V_we0, + res_87_V_d0, + res_88_V_address0, + res_88_V_ce0, + res_88_V_we0, + res_88_V_d0, + res_89_V_address0, + res_89_V_ce0, + res_89_V_we0, + res_89_V_d0, + res_90_V_address0, + res_90_V_ce0, + res_90_V_we0, + res_90_V_d0, + res_91_V_address0, + res_91_V_ce0, + res_91_V_we0, + res_91_V_d0, + res_92_V_address0, + res_92_V_ce0, + res_92_V_we0, + res_92_V_d0, + res_93_V_address0, + res_93_V_ce0, + res_93_V_we0, + res_93_V_d0, + res_94_V_address0, + res_94_V_ce0, + res_94_V_we0, + res_94_V_d0, + res_95_V_address0, + res_95_V_ce0, + res_95_V_we0, + res_95_V_d0, + res_96_V_address0, + res_96_V_ce0, + res_96_V_we0, + res_96_V_d0, + res_97_V_address0, + res_97_V_ce0, + res_97_V_we0, + res_97_V_d0, + res_98_V_address0, + res_98_V_ce0, + res_98_V_we0, + res_98_V_d0, + res_99_V_address0, + res_99_V_ce0, + res_99_V_we0, + res_99_V_d0, + res_100_V_address0, + res_100_V_ce0, + res_100_V_we0, + res_100_V_d0, + res_101_V_address0, + res_101_V_ce0, + res_101_V_we0, + res_101_V_d0, + res_102_V_address0, + res_102_V_ce0, + res_102_V_we0, + res_102_V_d0, + res_103_V_address0, + res_103_V_ce0, + res_103_V_we0, + res_103_V_d0, + res_104_V_address0, + res_104_V_ce0, + res_104_V_we0, + res_104_V_d0, + res_105_V_address0, + res_105_V_ce0, + res_105_V_we0, + res_105_V_d0, + res_106_V_address0, + res_106_V_ce0, + res_106_V_we0, + res_106_V_d0, + res_107_V_address0, + res_107_V_ce0, + res_107_V_we0, + res_107_V_d0, + res_108_V_address0, + res_108_V_ce0, + res_108_V_we0, + res_108_V_d0, + res_109_V_address0, + res_109_V_ce0, + res_109_V_we0, + res_109_V_d0, + res_110_V_address0, + res_110_V_ce0, + res_110_V_we0, + res_110_V_d0, + res_111_V_address0, + res_111_V_ce0, + res_111_V_we0, + res_111_V_d0, + res_112_V_address0, + res_112_V_ce0, + res_112_V_we0, + res_112_V_d0, + res_113_V_address0, + res_113_V_ce0, + res_113_V_we0, + res_113_V_d0, + res_114_V_address0, + res_114_V_ce0, + res_114_V_we0, + res_114_V_d0, + res_115_V_address0, + res_115_V_ce0, + res_115_V_we0, + res_115_V_d0, + res_116_V_address0, + res_116_V_ce0, + res_116_V_we0, + res_116_V_d0, + res_117_V_address0, + res_117_V_ce0, + res_117_V_we0, + res_117_V_d0, + res_118_V_address0, + res_118_V_ce0, + res_118_V_we0, + res_118_V_d0, + res_119_V_address0, + res_119_V_ce0, + res_119_V_we0, + res_119_V_d0, + res_120_V_address0, + res_120_V_ce0, + res_120_V_we0, + res_120_V_d0, + res_121_V_address0, + res_121_V_ce0, + res_121_V_we0, + res_121_V_d0, + res_122_V_address0, + res_122_V_ce0, + res_122_V_we0, + res_122_V_d0, + res_123_V_address0, + res_123_V_ce0, + res_123_V_we0, + res_123_V_d0, + res_124_V_address0, + res_124_V_ce0, + res_124_V_we0, + res_124_V_d0, + res_125_V_address0, + res_125_V_ce0, + res_125_V_we0, + res_125_V_d0, + res_126_V_address0, + res_126_V_ce0, + res_126_V_we0, + res_126_V_d0, + res_127_V_address0, + res_127_V_ce0, + res_127_V_we0, + res_127_V_d0 +); + +parameter ap_ST_fsm_state1 = 13'd0; +parameter ap_ST_fsm_state2 = 13'd1; +parameter ap_ST_fsm_state3 = 13'd2; +parameter ap_ST_fsm_state4 = 13'd3; +parameter ap_ST_fsm_state5 = 13'd4; +parameter ap_ST_fsm_state6 = 13'd5; +parameter ap_ST_fsm_state7 = 13'd6; +parameter ap_ST_fsm_state8 = 13'd7; +parameter ap_ST_fsm_state9 = 13'd8; +parameter ap_ST_fsm_state10 = 13'd9; +parameter ap_ST_fsm_state11 = 13'd10; +parameter ap_ST_fsm_state12 = 13'd11; +parameter ap_ST_fsm_state13 = 13'd12; +parameter ap_ST_fsm_state14 = 13'd13; +parameter ap_ST_fsm_state15 = 13'd14; +parameter ap_ST_fsm_state16 = 13'd15; +parameter ap_ST_fsm_state17 = 13'd16; +parameter ap_ST_fsm_state18 = 13'd17; +parameter ap_ST_fsm_state19 = 13'd18; +parameter ap_ST_fsm_state20 = 13'd19; +parameter ap_ST_fsm_state21 = 13'd20; +parameter ap_ST_fsm_state22 = 13'd21; +parameter ap_ST_fsm_state23 = 13'd22; +parameter ap_ST_fsm_state24 = 13'd23; +parameter ap_ST_fsm_state25 = 13'd24; +parameter ap_ST_fsm_state26 = 13'd25; +parameter ap_ST_fsm_state27 = 13'd26; +parameter ap_ST_fsm_state28 = 13'd27; +parameter ap_ST_fsm_state29 = 13'd28; +parameter ap_ST_fsm_state30 = 13'd29; +parameter ap_ST_fsm_state31 = 13'd30; +parameter ap_ST_fsm_state32 = 13'd31; +parameter ap_ST_fsm_state33 = 13'd32; +parameter ap_ST_fsm_state34 = 13'd33; +parameter ap_ST_fsm_state35 = 13'd34; +parameter ap_ST_fsm_state36 = 13'd35; +parameter ap_ST_fsm_state37 = 13'd36; +parameter ap_ST_fsm_state38 = 13'd37; +parameter ap_ST_fsm_state39 = 13'd38; +parameter ap_ST_fsm_state40 = 13'd39; +parameter ap_ST_fsm_state41 = 13'd40; +parameter ap_ST_fsm_state42 = 13'd41; +parameter ap_ST_fsm_state43 = 13'd42; +parameter ap_ST_fsm_state44 = 13'd43; +parameter ap_ST_fsm_state45 = 13'd44; +parameter ap_ST_fsm_state46 = 13'd45; +parameter ap_ST_fsm_state47 = 13'd46; +parameter ap_ST_fsm_state48 = 13'd47; +parameter ap_ST_fsm_state49 = 13'd48; +parameter ap_ST_fsm_state50 = 13'd49; +parameter ap_ST_fsm_state51 = 13'd50; +parameter ap_ST_fsm_state52 = 13'd51; +parameter ap_ST_fsm_state53 = 13'd52; +parameter ap_ST_fsm_state54 = 13'd53; +parameter ap_ST_fsm_state55 = 13'd54; +parameter ap_ST_fsm_state56 = 13'd55; +parameter ap_ST_fsm_state57 = 13'd56; +parameter ap_ST_fsm_state58 = 13'd57; +parameter ap_ST_fsm_state59 = 13'd58; +parameter ap_ST_fsm_state60 = 13'd59; +parameter ap_ST_fsm_state61 = 13'd60; +parameter ap_ST_fsm_state62 = 13'd61; +parameter ap_ST_fsm_state63 = 13'd62; +parameter ap_ST_fsm_state64 = 13'd63; +parameter ap_ST_fsm_state65 = 13'd64; +parameter ap_ST_fsm_state66 = 13'd65; +parameter ap_ST_fsm_state67 = 13'd66; +parameter ap_ST_fsm_state68 = 13'd67; +parameter ap_ST_fsm_state69 = 13'd68; +parameter ap_ST_fsm_state70 = 13'd69; +parameter ap_ST_fsm_state71 = 13'd70; +parameter ap_ST_fsm_state72 = 13'd71; +parameter ap_ST_fsm_state73 = 13'd72; +parameter ap_ST_fsm_state74 = 13'd73; +parameter ap_ST_fsm_state75 = 13'd74; +parameter ap_ST_fsm_state76 = 13'd75; +parameter ap_ST_fsm_state77 = 13'd76; +parameter ap_ST_fsm_state78 = 13'd77; +parameter ap_ST_fsm_state79 = 13'd78; +parameter ap_ST_fsm_state80 = 13'd79; +parameter ap_ST_fsm_state81 = 13'd80; +parameter ap_ST_fsm_state82 = 13'd81; +parameter ap_ST_fsm_state83 = 13'd82; +parameter ap_ST_fsm_state84 = 13'd83; +parameter ap_ST_fsm_state85 = 13'd84; +parameter ap_ST_fsm_state86 = 13'd85; +parameter ap_ST_fsm_state87 = 13'd86; +parameter ap_ST_fsm_state88 = 13'd87; +parameter ap_ST_fsm_state89 = 13'd88; +parameter ap_ST_fsm_state90 = 13'd89; +parameter ap_ST_fsm_state91 = 13'd90; +parameter ap_ST_fsm_state92 = 13'd91; +parameter ap_ST_fsm_state93 = 13'd92; +parameter ap_ST_fsm_state94 = 13'd93; +parameter ap_ST_fsm_state95 = 13'd94; +parameter ap_ST_fsm_state96 = 13'd95; +parameter ap_ST_fsm_state97 = 13'd96; +parameter ap_ST_fsm_state98 = 13'd97; +parameter ap_ST_fsm_state99 = 13'd98; +parameter ap_ST_fsm_state100 = 13'd99; +parameter ap_ST_fsm_state101 = 13'd100; +parameter ap_ST_fsm_state102 = 13'd101; +parameter ap_ST_fsm_state103 = 13'd102; +parameter ap_ST_fsm_state104 = 13'd103; +parameter ap_ST_fsm_state105 = 13'd104; +parameter ap_ST_fsm_state106 = 13'd105; +parameter ap_ST_fsm_state107 = 13'd106; +parameter ap_ST_fsm_state108 = 13'd107; +parameter ap_ST_fsm_state109 = 13'd108; +parameter ap_ST_fsm_state110 = 13'd109; +parameter ap_ST_fsm_state111 = 13'd110; +parameter ap_ST_fsm_state112 = 13'd111; +parameter ap_ST_fsm_state113 = 13'd112; +parameter ap_ST_fsm_state114 = 13'd113; +parameter ap_ST_fsm_state115 = 13'd114; +parameter ap_ST_fsm_state116 = 13'd115; +parameter ap_ST_fsm_state117 = 13'd116; +parameter ap_ST_fsm_state118 = 13'd117; +parameter ap_ST_fsm_state119 = 13'd118; +parameter ap_ST_fsm_state120 = 13'd119; +parameter ap_ST_fsm_state121 = 13'd120; +parameter ap_ST_fsm_state122 = 13'd121; +parameter ap_ST_fsm_state123 = 13'd122; +parameter ap_ST_fsm_state124 = 13'd123; +parameter ap_ST_fsm_state125 = 13'd124; +parameter ap_ST_fsm_state126 = 13'd125; +parameter ap_ST_fsm_state127 = 13'd126; +parameter ap_ST_fsm_state128 = 13'd127; +parameter ap_ST_fsm_state129 = 13'd128; +parameter ap_ST_fsm_state130 = 13'd129; +parameter ap_ST_fsm_state131 = 13'd130; +parameter ap_ST_fsm_state132 = 13'd131; +parameter ap_ST_fsm_state133 = 13'd132; +parameter ap_ST_fsm_state134 = 13'd133; +parameter ap_ST_fsm_state135 = 13'd134; +parameter ap_ST_fsm_state136 = 13'd135; +parameter ap_ST_fsm_state137 = 13'd136; +parameter ap_ST_fsm_state138 = 13'd137; +parameter ap_ST_fsm_state139 = 13'd138; +parameter ap_ST_fsm_state140 = 13'd139; +parameter ap_ST_fsm_state141 = 13'd140; +parameter ap_ST_fsm_state142 = 13'd141; +parameter ap_ST_fsm_state143 = 13'd142; +parameter ap_ST_fsm_state144 = 13'd143; +parameter ap_ST_fsm_state145 = 13'd144; +parameter ap_ST_fsm_state146 = 13'd145; +parameter ap_ST_fsm_state147 = 13'd146; +parameter ap_ST_fsm_state148 = 13'd147; +parameter ap_ST_fsm_state149 = 13'd148; +parameter ap_ST_fsm_state150 = 13'd149; +parameter ap_ST_fsm_state151 = 13'd150; +parameter ap_ST_fsm_state152 = 13'd151; +parameter ap_ST_fsm_state153 = 13'd152; +parameter ap_ST_fsm_state154 = 13'd153; +parameter ap_ST_fsm_state155 = 13'd154; +parameter ap_ST_fsm_state156 = 13'd155; +parameter ap_ST_fsm_state157 = 13'd156; +parameter ap_ST_fsm_state158 = 13'd157; +parameter ap_ST_fsm_state159 = 13'd158; +parameter ap_ST_fsm_state160 = 13'd159; +parameter ap_ST_fsm_state161 = 13'd160; +parameter ap_ST_fsm_state162 = 13'd161; +parameter ap_ST_fsm_state163 = 13'd162; +parameter ap_ST_fsm_state164 = 13'd163; +parameter ap_ST_fsm_state165 = 13'd164; +parameter ap_ST_fsm_state166 = 13'd165; +parameter ap_ST_fsm_state167 = 13'd166; +parameter ap_ST_fsm_state168 = 13'd167; +parameter ap_ST_fsm_state169 = 13'd168; +parameter ap_ST_fsm_state170 = 13'd169; +parameter ap_ST_fsm_state171 = 13'd170; +parameter ap_ST_fsm_state172 = 13'd171; +parameter ap_ST_fsm_state173 = 13'd172; +parameter ap_ST_fsm_state174 = 13'd173; +parameter ap_ST_fsm_state175 = 13'd174; +parameter ap_ST_fsm_state176 = 13'd175; +parameter ap_ST_fsm_state177 = 13'd176; +parameter ap_ST_fsm_state178 = 13'd177; +parameter ap_ST_fsm_state179 = 13'd178; +parameter ap_ST_fsm_state180 = 13'd179; +parameter ap_ST_fsm_state181 = 13'd180; +parameter ap_ST_fsm_state182 = 13'd181; +parameter ap_ST_fsm_state183 = 13'd182; +parameter ap_ST_fsm_state184 = 13'd183; +parameter ap_ST_fsm_state185 = 13'd184; +parameter ap_ST_fsm_state186 = 13'd185; +parameter ap_ST_fsm_state187 = 13'd186; +parameter ap_ST_fsm_state188 = 13'd187; +parameter ap_ST_fsm_state189 = 13'd188; +parameter ap_ST_fsm_state190 = 13'd189; +parameter ap_ST_fsm_state191 = 13'd190; +parameter ap_ST_fsm_state192 = 13'd191; +parameter ap_ST_fsm_state193 = 13'd192; +parameter ap_ST_fsm_state194 = 13'd193; +parameter ap_ST_fsm_state195 = 13'd194; +parameter ap_ST_fsm_state196 = 13'd195; +parameter ap_ST_fsm_state197 = 13'd196; +parameter ap_ST_fsm_state198 = 13'd197; +parameter ap_ST_fsm_state199 = 13'd198; +parameter ap_ST_fsm_state200 = 13'd199; +parameter ap_ST_fsm_state201 = 13'd200; +parameter ap_ST_fsm_state202 = 13'd201; +parameter ap_ST_fsm_state203 = 13'd202; +parameter ap_ST_fsm_state204 = 13'd203; +parameter ap_ST_fsm_state205 = 13'd204; +parameter ap_ST_fsm_state206 = 13'd205; +parameter ap_ST_fsm_state207 = 13'd206; +parameter ap_ST_fsm_state208 = 13'd207; +parameter ap_ST_fsm_state209 = 13'd208; +parameter ap_ST_fsm_state210 = 13'd209; +parameter ap_ST_fsm_state211 = 13'd210; +parameter ap_ST_fsm_state212 = 13'd211; +parameter ap_ST_fsm_state213 = 13'd212; +parameter ap_ST_fsm_state214 = 13'd213; +parameter ap_ST_fsm_state215 = 13'd214; +parameter ap_ST_fsm_state216 = 13'd215; +parameter ap_ST_fsm_state217 = 13'd216; +parameter ap_ST_fsm_state218 = 13'd217; +parameter ap_ST_fsm_state219 = 13'd218; +parameter ap_ST_fsm_state220 = 13'd219; +parameter ap_ST_fsm_state221 = 13'd220; +parameter ap_ST_fsm_state222 = 13'd221; +parameter ap_ST_fsm_state223 = 13'd222; +parameter ap_ST_fsm_state224 = 13'd223; +parameter ap_ST_fsm_state225 = 13'd224; +parameter ap_ST_fsm_state226 = 13'd225; +parameter ap_ST_fsm_state227 = 13'd226; +parameter ap_ST_fsm_state228 = 13'd227; +parameter ap_ST_fsm_state229 = 13'd228; +parameter ap_ST_fsm_state230 = 13'd229; +parameter ap_ST_fsm_state231 = 13'd230; +parameter ap_ST_fsm_state232 = 13'd231; +parameter ap_ST_fsm_state233 = 13'd232; +parameter ap_ST_fsm_state234 = 13'd233; +parameter ap_ST_fsm_state235 = 13'd234; +parameter ap_ST_fsm_state236 = 13'd235; +parameter ap_ST_fsm_state237 = 13'd236; +parameter ap_ST_fsm_state238 = 13'd237; +parameter ap_ST_fsm_state239 = 13'd238; +parameter ap_ST_fsm_state240 = 13'd239; +parameter ap_ST_fsm_state241 = 13'd240; +parameter ap_ST_fsm_state242 = 13'd241; +parameter ap_ST_fsm_state243 = 13'd242; +parameter ap_ST_fsm_state244 = 13'd243; +parameter ap_ST_fsm_state245 = 13'd244; +parameter ap_ST_fsm_state246 = 13'd245; +parameter ap_ST_fsm_state247 = 13'd246; +parameter ap_ST_fsm_state248 = 13'd247; +parameter ap_ST_fsm_state249 = 13'd248; +parameter ap_ST_fsm_state250 = 13'd249; +parameter ap_ST_fsm_state251 = 13'd250; +parameter ap_ST_fsm_state252 = 13'd251; +parameter ap_ST_fsm_state253 = 13'd252; +parameter ap_ST_fsm_state254 = 13'd253; +parameter ap_ST_fsm_state255 = 13'd254; +parameter ap_ST_fsm_state256 = 13'd255; +parameter ap_ST_fsm_state257 = 13'd256; +parameter ap_ST_fsm_state258 = 13'd257; +parameter ap_ST_fsm_state259 = 13'd258; +parameter ap_ST_fsm_state260 = 13'd259; +parameter ap_ST_fsm_state261 = 13'd260; +parameter ap_ST_fsm_state262 = 13'd261; +parameter ap_ST_fsm_state263 = 13'd262; +parameter ap_ST_fsm_state264 = 13'd263; +parameter ap_ST_fsm_state265 = 13'd264; +parameter ap_ST_fsm_state266 = 13'd265; +parameter ap_ST_fsm_state267 = 13'd266; +parameter ap_ST_fsm_state268 = 13'd267; +parameter ap_ST_fsm_state269 = 13'd268; +parameter ap_ST_fsm_state270 = 13'd269; +parameter ap_ST_fsm_state271 = 13'd270; +parameter ap_ST_fsm_state272 = 13'd271; +parameter ap_ST_fsm_state273 = 13'd272; +parameter ap_ST_fsm_state274 = 13'd273; +parameter ap_ST_fsm_state275 = 13'd274; +parameter ap_ST_fsm_state276 = 13'd275; +parameter ap_ST_fsm_state277 = 13'd276; +parameter ap_ST_fsm_state278 = 13'd277; +parameter ap_ST_fsm_state279 = 13'd278; +parameter ap_ST_fsm_state280 = 13'd279; +parameter ap_ST_fsm_state281 = 13'd280; +parameter ap_ST_fsm_state282 = 13'd281; +parameter ap_ST_fsm_state283 = 13'd282; +parameter ap_ST_fsm_state284 = 13'd283; +parameter ap_ST_fsm_state285 = 13'd284; +parameter ap_ST_fsm_state286 = 13'd285; +parameter ap_ST_fsm_state287 = 13'd286; +parameter ap_ST_fsm_state288 = 13'd287; +parameter ap_ST_fsm_state289 = 13'd288; +parameter ap_ST_fsm_state290 = 13'd289; +parameter ap_ST_fsm_state291 = 13'd290; +parameter ap_ST_fsm_state292 = 13'd291; +parameter ap_ST_fsm_state293 = 13'd292; +parameter ap_ST_fsm_state294 = 13'd293; +parameter ap_ST_fsm_state295 = 13'd294; +parameter ap_ST_fsm_state296 = 13'd295; +parameter ap_ST_fsm_state297 = 13'd296; +parameter ap_ST_fsm_state298 = 13'd297; +parameter ap_ST_fsm_state299 = 13'd298; +parameter ap_ST_fsm_state300 = 13'd299; +parameter ap_ST_fsm_state301 = 13'd300; +parameter ap_ST_fsm_state302 = 13'd301; +parameter ap_ST_fsm_state303 = 13'd302; +parameter ap_ST_fsm_state304 = 13'd303; +parameter ap_ST_fsm_state305 = 13'd304; +parameter ap_ST_fsm_state306 = 13'd305; +parameter ap_ST_fsm_state307 = 13'd306; +parameter ap_ST_fsm_state308 = 13'd307; +parameter ap_ST_fsm_state309 = 13'd308; +parameter ap_ST_fsm_state310 = 13'd309; +parameter ap_ST_fsm_state311 = 13'd310; +parameter ap_ST_fsm_state312 = 13'd311; +parameter ap_ST_fsm_state313 = 13'd312; +parameter ap_ST_fsm_state314 = 13'd313; +parameter ap_ST_fsm_state315 = 13'd314; +parameter ap_ST_fsm_state316 = 13'd315; +parameter ap_ST_fsm_state317 = 13'd316; +parameter ap_ST_fsm_state318 = 13'd317; +parameter ap_ST_fsm_state319 = 13'd318; +parameter ap_ST_fsm_state320 = 13'd319; +parameter ap_ST_fsm_state321 = 13'd320; +parameter ap_ST_fsm_state322 = 13'd321; +parameter ap_ST_fsm_state323 = 13'd322; +parameter ap_ST_fsm_state324 = 13'd323; +parameter ap_ST_fsm_state325 = 13'd324; +parameter ap_ST_fsm_state326 = 13'd325; +parameter ap_ST_fsm_state327 = 13'd326; +parameter ap_ST_fsm_state328 = 13'd327; +parameter ap_ST_fsm_state329 = 13'd328; +parameter ap_ST_fsm_state330 = 13'd329; +parameter ap_ST_fsm_state331 = 13'd330; +parameter ap_ST_fsm_state332 = 13'd331; +parameter ap_ST_fsm_state333 = 13'd332; +parameter ap_ST_fsm_state334 = 13'd333; +parameter ap_ST_fsm_state335 = 13'd334; +parameter ap_ST_fsm_state336 = 13'd335; +parameter ap_ST_fsm_state337 = 13'd336; +parameter ap_ST_fsm_state338 = 13'd337; +parameter ap_ST_fsm_state339 = 13'd338; +parameter ap_ST_fsm_state340 = 13'd339; +parameter ap_ST_fsm_state341 = 13'd340; +parameter ap_ST_fsm_state342 = 13'd341; +parameter ap_ST_fsm_state343 = 13'd342; +parameter ap_ST_fsm_state344 = 13'd343; +parameter ap_ST_fsm_state345 = 13'd344; +parameter ap_ST_fsm_state346 = 13'd345; +parameter ap_ST_fsm_state347 = 13'd346; +parameter ap_ST_fsm_state348 = 13'd347; +parameter ap_ST_fsm_state349 = 13'd348; +parameter ap_ST_fsm_state350 = 13'd349; +parameter ap_ST_fsm_state351 = 13'd350; +parameter ap_ST_fsm_state352 = 13'd351; +parameter ap_ST_fsm_state353 = 13'd352; +parameter ap_ST_fsm_state354 = 13'd353; +parameter ap_ST_fsm_state355 = 13'd354; +parameter ap_ST_fsm_state356 = 13'd355; +parameter ap_ST_fsm_state357 = 13'd356; +parameter ap_ST_fsm_state358 = 13'd357; +parameter ap_ST_fsm_state359 = 13'd358; +parameter ap_ST_fsm_state360 = 13'd359; +parameter ap_ST_fsm_state361 = 13'd360; +parameter ap_ST_fsm_state362 = 13'd361; +parameter ap_ST_fsm_state363 = 13'd362; +parameter ap_ST_fsm_state364 = 13'd363; +parameter ap_ST_fsm_state365 = 13'd364; +parameter ap_ST_fsm_state366 = 13'd365; +parameter ap_ST_fsm_state367 = 13'd366; +parameter ap_ST_fsm_state368 = 13'd367; +parameter ap_ST_fsm_state369 = 13'd368; +parameter ap_ST_fsm_state370 = 13'd369; +parameter ap_ST_fsm_state371 = 13'd370; +parameter ap_ST_fsm_state372 = 13'd371; +parameter ap_ST_fsm_state373 = 13'd372; +parameter ap_ST_fsm_state374 = 13'd373; +parameter ap_ST_fsm_state375 = 13'd374; +parameter ap_ST_fsm_state376 = 13'd375; +parameter ap_ST_fsm_state377 = 13'd376; +parameter ap_ST_fsm_state378 = 13'd377; +parameter ap_ST_fsm_state379 = 13'd378; +parameter ap_ST_fsm_state380 = 13'd379; +parameter ap_ST_fsm_state381 = 13'd380; +parameter ap_ST_fsm_state382 = 13'd381; +parameter ap_ST_fsm_state383 = 13'd382; +parameter ap_ST_fsm_state384 = 13'd383; +parameter ap_ST_fsm_state385 = 13'd384; +parameter ap_ST_fsm_state386 = 13'd385; +parameter ap_ST_fsm_state387 = 13'd386; +parameter ap_ST_fsm_state388 = 13'd387; +parameter ap_ST_fsm_state389 = 13'd388; +parameter ap_ST_fsm_state390 = 13'd389; +parameter ap_ST_fsm_state391 = 13'd390; +parameter ap_ST_fsm_state392 = 13'd391; +parameter ap_ST_fsm_state393 = 13'd392; +parameter ap_ST_fsm_state394 = 13'd393; +parameter ap_ST_fsm_state395 = 13'd394; +parameter ap_ST_fsm_state396 = 13'd395; +parameter ap_ST_fsm_state397 = 13'd396; +parameter ap_ST_fsm_state398 = 13'd397; +parameter ap_ST_fsm_state399 = 13'd398; +parameter ap_ST_fsm_state400 = 13'd399; +parameter ap_ST_fsm_state401 = 13'd400; +parameter ap_ST_fsm_state402 = 13'd401; +parameter ap_ST_fsm_state403 = 13'd402; +parameter ap_ST_fsm_state404 = 13'd403; +parameter ap_ST_fsm_state405 = 13'd404; +parameter ap_ST_fsm_state406 = 13'd405; +parameter ap_ST_fsm_state407 = 13'd406; +parameter ap_ST_fsm_state408 = 13'd407; +parameter ap_ST_fsm_state409 = 13'd408; +parameter ap_ST_fsm_state410 = 13'd409; +parameter ap_ST_fsm_state411 = 13'd410; +parameter ap_ST_fsm_state412 = 13'd411; +parameter ap_ST_fsm_state413 = 13'd412; +parameter ap_ST_fsm_state414 = 13'd413; +parameter ap_ST_fsm_state415 = 13'd414; +parameter ap_ST_fsm_state416 = 13'd415; +parameter ap_ST_fsm_state417 = 13'd416; +parameter ap_ST_fsm_state418 = 13'd417; +parameter ap_ST_fsm_state419 = 13'd418; +parameter ap_ST_fsm_state420 = 13'd419; +parameter ap_ST_fsm_state421 = 13'd420; +parameter ap_ST_fsm_state422 = 13'd421; +parameter ap_ST_fsm_state423 = 13'd422; +parameter ap_ST_fsm_state424 = 13'd423; +parameter ap_ST_fsm_state425 = 13'd424; +parameter ap_ST_fsm_state426 = 13'd425; +parameter ap_ST_fsm_state427 = 13'd426; +parameter ap_ST_fsm_state428 = 13'd427; +parameter ap_ST_fsm_state429 = 13'd428; +parameter ap_ST_fsm_state430 = 13'd429; +parameter ap_ST_fsm_state431 = 13'd430; +parameter ap_ST_fsm_state432 = 13'd431; +parameter ap_ST_fsm_state433 = 13'd432; +parameter ap_ST_fsm_state434 = 13'd433; +parameter ap_ST_fsm_state435 = 13'd434; +parameter ap_ST_fsm_state436 = 13'd435; +parameter ap_ST_fsm_state437 = 13'd436; +parameter ap_ST_fsm_state438 = 13'd437; +parameter ap_ST_fsm_state439 = 13'd438; +parameter ap_ST_fsm_state440 = 13'd439; +parameter ap_ST_fsm_state441 = 13'd440; +parameter ap_ST_fsm_state442 = 13'd441; +parameter ap_ST_fsm_state443 = 13'd442; +parameter ap_ST_fsm_state444 = 13'd443; +parameter ap_ST_fsm_state445 = 13'd444; +parameter ap_ST_fsm_state446 = 13'd445; +parameter ap_ST_fsm_state447 = 13'd446; +parameter ap_ST_fsm_state448 = 13'd447; +parameter ap_ST_fsm_state449 = 13'd448; +parameter ap_ST_fsm_state450 = 13'd449; +parameter ap_ST_fsm_state451 = 13'd450; +parameter ap_ST_fsm_state452 = 13'd451; +parameter ap_ST_fsm_state453 = 13'd452; +parameter ap_ST_fsm_state454 = 13'd453; +parameter ap_ST_fsm_state455 = 13'd454; +parameter ap_ST_fsm_state456 = 13'd455; +parameter ap_ST_fsm_state457 = 13'd456; +parameter ap_ST_fsm_state458 = 13'd457; +parameter ap_ST_fsm_state459 = 13'd458; +parameter ap_ST_fsm_state460 = 13'd459; +parameter ap_ST_fsm_state461 = 13'd460; +parameter ap_ST_fsm_state462 = 13'd461; +parameter ap_ST_fsm_state463 = 13'd462; +parameter ap_ST_fsm_state464 = 13'd463; +parameter ap_ST_fsm_state465 = 13'd464; +parameter ap_ST_fsm_state466 = 13'd465; +parameter ap_ST_fsm_state467 = 13'd466; +parameter ap_ST_fsm_state468 = 13'd467; +parameter ap_ST_fsm_state469 = 13'd468; +parameter ap_ST_fsm_state470 = 13'd469; +parameter ap_ST_fsm_state471 = 13'd470; +parameter ap_ST_fsm_state472 = 13'd471; +parameter ap_ST_fsm_state473 = 13'd472; +parameter ap_ST_fsm_state474 = 13'd473; +parameter ap_ST_fsm_state475 = 13'd474; +parameter ap_ST_fsm_state476 = 13'd475; +parameter ap_ST_fsm_state477 = 13'd476; +parameter ap_ST_fsm_state478 = 13'd477; +parameter ap_ST_fsm_state479 = 13'd478; +parameter ap_ST_fsm_state480 = 13'd479; +parameter ap_ST_fsm_state481 = 13'd480; +parameter ap_ST_fsm_state482 = 13'd481; +parameter ap_ST_fsm_state483 = 13'd482; +parameter ap_ST_fsm_state484 = 13'd483; +parameter ap_ST_fsm_state485 = 13'd484; +parameter ap_ST_fsm_state486 = 13'd485; +parameter ap_ST_fsm_state487 = 13'd486; +parameter ap_ST_fsm_state488 = 13'd487; +parameter ap_ST_fsm_state489 = 13'd488; +parameter ap_ST_fsm_state490 = 13'd489; +parameter ap_ST_fsm_state491 = 13'd490; +parameter ap_ST_fsm_state492 = 13'd491; +parameter ap_ST_fsm_state493 = 13'd492; +parameter ap_ST_fsm_state494 = 13'd493; +parameter ap_ST_fsm_state495 = 13'd494; +parameter ap_ST_fsm_state496 = 13'd495; +parameter ap_ST_fsm_state497 = 13'd496; +parameter ap_ST_fsm_state498 = 13'd497; +parameter ap_ST_fsm_state499 = 13'd498; +parameter ap_ST_fsm_state500 = 13'd499; +parameter ap_ST_fsm_state501 = 13'd500; +parameter ap_ST_fsm_state502 = 13'd501; +parameter ap_ST_fsm_state503 = 13'd502; +parameter ap_ST_fsm_state504 = 13'd503; +parameter ap_ST_fsm_state505 = 13'd504; +parameter ap_ST_fsm_state506 = 13'd505; +parameter ap_ST_fsm_state507 = 13'd506; +parameter ap_ST_fsm_state508 = 13'd507; +parameter ap_ST_fsm_state509 = 13'd508; +parameter ap_ST_fsm_state510 = 13'd509; +parameter ap_ST_fsm_state511 = 13'd510; +parameter ap_ST_fsm_state512 = 13'd511; +parameter ap_ST_fsm_state513 = 13'd512; +parameter ap_ST_fsm_state514 = 13'd513; +parameter ap_ST_fsm_state515 = 13'd514; +parameter ap_ST_fsm_state516 = 13'd515; +parameter ap_ST_fsm_state517 = 13'd516; +parameter ap_ST_fsm_state518 = 13'd517; +parameter ap_ST_fsm_state519 = 13'd518; +parameter ap_ST_fsm_state520 = 13'd519; +parameter ap_ST_fsm_state521 = 13'd520; +parameter ap_ST_fsm_state522 = 13'd521; +parameter ap_ST_fsm_state523 = 13'd522; +parameter ap_ST_fsm_state524 = 13'd523; +parameter ap_ST_fsm_state525 = 13'd524; +parameter ap_ST_fsm_state526 = 13'd525; +parameter ap_ST_fsm_state527 = 13'd526; +parameter ap_ST_fsm_state528 = 13'd527; +parameter ap_ST_fsm_state529 = 13'd528; +parameter ap_ST_fsm_state530 = 13'd529; +parameter ap_ST_fsm_state531 = 13'd530; +parameter ap_ST_fsm_state532 = 13'd531; +parameter ap_ST_fsm_state533 = 13'd532; +parameter ap_ST_fsm_state534 = 13'd533; +parameter ap_ST_fsm_state535 = 13'd534; +parameter ap_ST_fsm_state536 = 13'd535; +parameter ap_ST_fsm_state537 = 13'd536; +parameter ap_ST_fsm_state538 = 13'd537; +parameter ap_ST_fsm_state539 = 13'd538; +parameter ap_ST_fsm_state540 = 13'd539; +parameter ap_ST_fsm_state541 = 13'd540; +parameter ap_ST_fsm_state542 = 13'd541; +parameter ap_ST_fsm_state543 = 13'd542; +parameter ap_ST_fsm_state544 = 13'd543; +parameter ap_ST_fsm_state545 = 13'd544; +parameter ap_ST_fsm_state546 = 13'd545; +parameter ap_ST_fsm_state547 = 13'd546; +parameter ap_ST_fsm_state548 = 13'd547; +parameter ap_ST_fsm_state549 = 13'd548; +parameter ap_ST_fsm_state550 = 13'd549; +parameter ap_ST_fsm_state551 = 13'd550; +parameter ap_ST_fsm_state552 = 13'd551; +parameter ap_ST_fsm_state553 = 13'd552; +parameter ap_ST_fsm_state554 = 13'd553; +parameter ap_ST_fsm_state555 = 13'd554; +parameter ap_ST_fsm_state556 = 13'd555; +parameter ap_ST_fsm_state557 = 13'd556; +parameter ap_ST_fsm_state558 = 13'd557; +parameter ap_ST_fsm_state559 = 13'd558; +parameter ap_ST_fsm_state560 = 13'd559; +parameter ap_ST_fsm_state561 = 13'd560; +parameter ap_ST_fsm_state562 = 13'd561; +parameter ap_ST_fsm_state563 = 13'd562; +parameter ap_ST_fsm_state564 = 13'd563; +parameter ap_ST_fsm_state565 = 13'd564; +parameter ap_ST_fsm_state566 = 13'd565; +parameter ap_ST_fsm_state567 = 13'd566; +parameter ap_ST_fsm_state568 = 13'd567; +parameter ap_ST_fsm_state569 = 13'd568; +parameter ap_ST_fsm_state570 = 13'd569; +parameter ap_ST_fsm_state571 = 13'd570; +parameter ap_ST_fsm_state572 = 13'd571; +parameter ap_ST_fsm_state573 = 13'd572; +parameter ap_ST_fsm_state574 = 13'd573; +parameter ap_ST_fsm_state575 = 13'd574; +parameter ap_ST_fsm_state576 = 13'd575; +parameter ap_ST_fsm_state577 = 13'd576; +parameter ap_ST_fsm_state578 = 13'd577; +parameter ap_ST_fsm_state579 = 13'd578; +parameter ap_ST_fsm_state580 = 13'd579; +parameter ap_ST_fsm_state581 = 13'd580; +parameter ap_ST_fsm_state582 = 13'd581; +parameter ap_ST_fsm_state583 = 13'd582; +parameter ap_ST_fsm_state584 = 13'd583; +parameter ap_ST_fsm_state585 = 13'd584; +parameter ap_ST_fsm_state586 = 13'd585; +parameter ap_ST_fsm_state587 = 13'd586; +parameter ap_ST_fsm_state588 = 13'd587; +parameter ap_ST_fsm_state589 = 13'd588; +parameter ap_ST_fsm_state590 = 13'd589; +parameter ap_ST_fsm_state591 = 13'd590; +parameter ap_ST_fsm_state592 = 13'd591; +parameter ap_ST_fsm_state593 = 13'd592; +parameter ap_ST_fsm_state594 = 13'd593; +parameter ap_ST_fsm_state595 = 13'd594; +parameter ap_ST_fsm_state596 = 13'd595; +parameter ap_ST_fsm_state597 = 13'd596; +parameter ap_ST_fsm_state598 = 13'd597; +parameter ap_ST_fsm_state599 = 13'd598; +parameter ap_ST_fsm_state600 = 13'd599; +parameter ap_ST_fsm_state601 = 13'd600; +parameter ap_ST_fsm_state602 = 13'd601; +parameter ap_ST_fsm_state603 = 13'd602; +parameter ap_ST_fsm_state604 = 13'd603; +parameter ap_ST_fsm_state605 = 13'd604; +parameter ap_ST_fsm_state606 = 13'd605; +parameter ap_ST_fsm_state607 = 13'd606; +parameter ap_ST_fsm_state608 = 13'd607; +parameter ap_ST_fsm_state609 = 13'd608; +parameter ap_ST_fsm_state610 = 13'd609; +parameter ap_ST_fsm_state611 = 13'd610; +parameter ap_ST_fsm_state612 = 13'd611; +parameter ap_ST_fsm_state613 = 13'd612; +parameter ap_ST_fsm_state614 = 13'd613; +parameter ap_ST_fsm_state615 = 13'd614; +parameter ap_ST_fsm_state616 = 13'd615; +parameter ap_ST_fsm_state617 = 13'd616; +parameter ap_ST_fsm_state618 = 13'd617; +parameter ap_ST_fsm_state619 = 13'd618; +parameter ap_ST_fsm_state620 = 13'd619; +parameter ap_ST_fsm_state621 = 13'd620; +parameter ap_ST_fsm_state622 = 13'd621; +parameter ap_ST_fsm_state623 = 13'd622; +parameter ap_ST_fsm_state624 = 13'd623; +parameter ap_ST_fsm_state625 = 13'd624; +parameter ap_ST_fsm_state626 = 13'd625; +parameter ap_ST_fsm_state627 = 13'd626; +parameter ap_ST_fsm_state628 = 13'd627; +parameter ap_ST_fsm_state629 = 13'd628; +parameter ap_ST_fsm_state630 = 13'd629; +parameter ap_ST_fsm_state631 = 13'd630; +parameter ap_ST_fsm_state632 = 13'd631; +parameter ap_ST_fsm_state633 = 13'd632; +parameter ap_ST_fsm_state634 = 13'd633; +parameter ap_ST_fsm_state635 = 13'd634; +parameter ap_ST_fsm_state636 = 13'd635; +parameter ap_ST_fsm_state637 = 13'd636; +parameter ap_ST_fsm_state638 = 13'd637; +parameter ap_ST_fsm_state639 = 13'd638; +parameter ap_ST_fsm_state640 = 13'd639; +parameter ap_ST_fsm_state641 = 13'd640; +parameter ap_ST_fsm_state642 = 13'd641; +parameter ap_ST_fsm_state643 = 13'd642; +parameter ap_ST_fsm_state644 = 13'd643; +parameter ap_ST_fsm_state645 = 13'd644; +parameter ap_ST_fsm_state646 = 13'd645; +parameter ap_ST_fsm_state647 = 13'd646; +parameter ap_ST_fsm_state648 = 13'd647; +parameter ap_ST_fsm_state649 = 13'd648; +parameter ap_ST_fsm_state650 = 13'd649; +parameter ap_ST_fsm_state651 = 13'd650; +parameter ap_ST_fsm_state652 = 13'd651; +parameter ap_ST_fsm_state653 = 13'd652; +parameter ap_ST_fsm_state654 = 13'd653; +parameter ap_ST_fsm_state655 = 13'd654; +parameter ap_ST_fsm_state656 = 13'd655; +parameter ap_ST_fsm_state657 = 13'd656; +parameter ap_ST_fsm_state658 = 13'd657; +parameter ap_ST_fsm_state659 = 13'd658; +parameter ap_ST_fsm_state660 = 13'd659; +parameter ap_ST_fsm_state661 = 13'd660; +parameter ap_ST_fsm_state662 = 13'd661; +parameter ap_ST_fsm_state663 = 13'd662; +parameter ap_ST_fsm_state664 = 13'd663; +parameter ap_ST_fsm_state665 = 13'd664; +parameter ap_ST_fsm_state666 = 13'd665; +parameter ap_ST_fsm_state667 = 13'd666; +parameter ap_ST_fsm_state668 = 13'd667; +parameter ap_ST_fsm_state669 = 13'd668; +parameter ap_ST_fsm_state670 = 13'd669; +parameter ap_ST_fsm_state671 = 13'd670; +parameter ap_ST_fsm_state672 = 13'd671; +parameter ap_ST_fsm_state673 = 13'd672; +parameter ap_ST_fsm_state674 = 13'd673; +parameter ap_ST_fsm_state675 = 13'd674; +parameter ap_ST_fsm_state676 = 13'd675; +parameter ap_ST_fsm_state677 = 13'd676; +parameter ap_ST_fsm_state678 = 13'd677; +parameter ap_ST_fsm_state679 = 13'd678; +parameter ap_ST_fsm_state680 = 13'd679; +parameter ap_ST_fsm_state681 = 13'd680; +parameter ap_ST_fsm_state682 = 13'd681; +parameter ap_ST_fsm_state683 = 13'd682; +parameter ap_ST_fsm_state684 = 13'd683; +parameter ap_ST_fsm_state685 = 13'd684; +parameter ap_ST_fsm_state686 = 13'd685; +parameter ap_ST_fsm_state687 = 13'd686; +parameter ap_ST_fsm_state688 = 13'd687; +parameter ap_ST_fsm_state689 = 13'd688; +parameter ap_ST_fsm_state690 = 13'd689; +parameter ap_ST_fsm_state691 = 13'd690; +parameter ap_ST_fsm_state692 = 13'd691; +parameter ap_ST_fsm_state693 = 13'd692; +parameter ap_ST_fsm_state694 = 13'd693; +parameter ap_ST_fsm_state695 = 13'd694; +parameter ap_ST_fsm_state696 = 13'd695; +parameter ap_ST_fsm_state697 = 13'd696; +parameter ap_ST_fsm_state698 = 13'd697; +parameter ap_ST_fsm_state699 = 13'd698; +parameter ap_ST_fsm_state700 = 13'd699; +parameter ap_ST_fsm_state701 = 13'd700; +parameter ap_ST_fsm_state702 = 13'd701; +parameter ap_ST_fsm_state703 = 13'd702; +parameter ap_ST_fsm_state704 = 13'd703; +parameter ap_ST_fsm_state705 = 13'd704; +parameter ap_ST_fsm_state706 = 13'd705; +parameter ap_ST_fsm_state707 = 13'd706; +parameter ap_ST_fsm_state708 = 13'd707; +parameter ap_ST_fsm_state709 = 13'd708; +parameter ap_ST_fsm_state710 = 13'd709; +parameter ap_ST_fsm_state711 = 13'd710; +parameter ap_ST_fsm_state712 = 13'd711; +parameter ap_ST_fsm_state713 = 13'd712; +parameter ap_ST_fsm_state714 = 13'd713; +parameter ap_ST_fsm_state715 = 13'd714; +parameter ap_ST_fsm_state716 = 13'd715; +parameter ap_ST_fsm_state717 = 13'd716; +parameter ap_ST_fsm_state718 = 13'd717; +parameter ap_ST_fsm_state719 = 13'd718; +parameter ap_ST_fsm_state720 = 13'd719; +parameter ap_ST_fsm_state721 = 13'd720; +parameter ap_ST_fsm_state722 = 13'd721; +parameter ap_ST_fsm_state723 = 13'd722; +parameter ap_ST_fsm_state724 = 13'd723; +parameter ap_ST_fsm_state725 = 13'd724; +parameter ap_ST_fsm_state726 = 13'd725; +parameter ap_ST_fsm_state727 = 13'd726; +parameter ap_ST_fsm_state728 = 13'd727; +parameter ap_ST_fsm_state729 = 13'd728; +parameter ap_ST_fsm_state730 = 13'd729; +parameter ap_ST_fsm_state731 = 13'd730; +parameter ap_ST_fsm_state732 = 13'd731; +parameter ap_ST_fsm_state733 = 13'd732; +parameter ap_ST_fsm_state734 = 13'd733; +parameter ap_ST_fsm_state735 = 13'd734; +parameter ap_ST_fsm_state736 = 13'd735; +parameter ap_ST_fsm_state737 = 13'd736; +parameter ap_ST_fsm_state738 = 13'd737; +parameter ap_ST_fsm_state739 = 13'd738; +parameter ap_ST_fsm_state740 = 13'd739; +parameter ap_ST_fsm_state741 = 13'd740; +parameter ap_ST_fsm_state742 = 13'd741; +parameter ap_ST_fsm_state743 = 13'd742; +parameter ap_ST_fsm_state744 = 13'd743; +parameter ap_ST_fsm_state745 = 13'd744; +parameter ap_ST_fsm_state746 = 13'd745; +parameter ap_ST_fsm_state747 = 13'd746; +parameter ap_ST_fsm_state748 = 13'd747; +parameter ap_ST_fsm_state749 = 13'd748; +parameter ap_ST_fsm_state750 = 13'd749; +parameter ap_ST_fsm_state751 = 13'd750; +parameter ap_ST_fsm_state752 = 13'd751; +parameter ap_ST_fsm_state753 = 13'd752; +parameter ap_ST_fsm_state754 = 13'd753; +parameter ap_ST_fsm_state755 = 13'd754; +parameter ap_ST_fsm_state756 = 13'd755; +parameter ap_ST_fsm_state757 = 13'd756; +parameter ap_ST_fsm_state758 = 13'd757; +parameter ap_ST_fsm_state759 = 13'd758; +parameter ap_ST_fsm_state760 = 13'd759; +parameter ap_ST_fsm_state761 = 13'd760; +parameter ap_ST_fsm_state762 = 13'd761; +parameter ap_ST_fsm_state763 = 13'd762; +parameter ap_ST_fsm_state764 = 13'd763; +parameter ap_ST_fsm_state765 = 13'd764; +parameter ap_ST_fsm_state766 = 13'd765; +parameter ap_ST_fsm_state767 = 13'd766; +parameter ap_ST_fsm_state768 = 13'd767; +parameter ap_ST_fsm_state769 = 13'd768; +parameter ap_ST_fsm_state770 = 13'd769; +parameter ap_ST_fsm_state771 = 13'd770; +parameter ap_ST_fsm_state772 = 13'd771; +parameter ap_ST_fsm_state773 = 13'd772; +parameter ap_ST_fsm_state774 = 13'd773; +parameter ap_ST_fsm_state775 = 13'd774; +parameter ap_ST_fsm_state776 = 13'd775; +parameter ap_ST_fsm_state777 = 13'd776; +parameter ap_ST_fsm_state778 = 13'd777; +parameter ap_ST_fsm_state779 = 13'd778; +parameter ap_ST_fsm_state780 = 13'd779; +parameter ap_ST_fsm_state781 = 13'd780; +parameter ap_ST_fsm_state782 = 13'd781; +parameter ap_ST_fsm_state783 = 13'd782; +parameter ap_ST_fsm_state784 = 13'd783; +parameter ap_ST_fsm_state785 = 13'd784; +parameter ap_ST_fsm_state786 = 13'd785; +parameter ap_ST_fsm_state787 = 13'd786; +parameter ap_ST_fsm_state788 = 13'd787; +parameter ap_ST_fsm_state789 = 13'd788; +parameter ap_ST_fsm_state790 = 13'd789; +parameter ap_ST_fsm_state791 = 13'd790; +parameter ap_ST_fsm_state792 = 13'd791; +parameter ap_ST_fsm_state793 = 13'd792; +parameter ap_ST_fsm_state794 = 13'd793; +parameter ap_ST_fsm_state795 = 13'd794; +parameter ap_ST_fsm_state796 = 13'd795; +parameter ap_ST_fsm_state797 = 13'd796; +parameter ap_ST_fsm_state798 = 13'd797; +parameter ap_ST_fsm_state799 = 13'd798; +parameter ap_ST_fsm_state800 = 13'd799; +parameter ap_ST_fsm_state801 = 13'd800; +parameter ap_ST_fsm_state802 = 13'd801; +parameter ap_ST_fsm_state803 = 13'd802; +parameter ap_ST_fsm_state804 = 13'd803; +parameter ap_ST_fsm_state805 = 13'd804; +parameter ap_ST_fsm_state806 = 13'd805; +parameter ap_ST_fsm_state807 = 13'd806; +parameter ap_ST_fsm_state808 = 13'd807; +parameter ap_ST_fsm_state809 = 13'd808; +parameter ap_ST_fsm_state810 = 13'd809; +parameter ap_ST_fsm_state811 = 13'd810; +parameter ap_ST_fsm_state812 = 13'd811; +parameter ap_ST_fsm_state813 = 13'd812; +parameter ap_ST_fsm_state814 = 13'd813; +parameter ap_ST_fsm_state815 = 13'd814; +parameter ap_ST_fsm_state816 = 13'd815; +parameter ap_ST_fsm_state817 = 13'd816; +parameter ap_ST_fsm_state818 = 13'd817; +parameter ap_ST_fsm_state819 = 13'd818; +parameter ap_ST_fsm_state820 = 13'd819; +parameter ap_ST_fsm_state821 = 13'd820; +parameter ap_ST_fsm_state822 = 13'd821; +parameter ap_ST_fsm_state823 = 13'd822; +parameter ap_ST_fsm_state824 = 13'd823; +parameter ap_ST_fsm_state825 = 13'd824; +parameter ap_ST_fsm_state826 = 13'd825; +parameter ap_ST_fsm_state827 = 13'd826; +parameter ap_ST_fsm_state828 = 13'd827; +parameter ap_ST_fsm_state829 = 13'd828; +parameter ap_ST_fsm_state830 = 13'd829; +parameter ap_ST_fsm_state831 = 13'd830; +parameter ap_ST_fsm_state832 = 13'd831; +parameter ap_ST_fsm_state833 = 13'd832; +parameter ap_ST_fsm_state834 = 13'd833; +parameter ap_ST_fsm_state835 = 13'd834; +parameter ap_ST_fsm_state836 = 13'd835; +parameter ap_ST_fsm_state837 = 13'd836; +parameter ap_ST_fsm_state838 = 13'd837; +parameter ap_ST_fsm_state839 = 13'd838; +parameter ap_ST_fsm_state840 = 13'd839; +parameter ap_ST_fsm_state841 = 13'd840; +parameter ap_ST_fsm_state842 = 13'd841; +parameter ap_ST_fsm_state843 = 13'd842; +parameter ap_ST_fsm_state844 = 13'd843; +parameter ap_ST_fsm_state845 = 13'd844; +parameter ap_ST_fsm_state846 = 13'd845; +parameter ap_ST_fsm_state847 = 13'd846; +parameter ap_ST_fsm_state848 = 13'd847; +parameter ap_ST_fsm_state849 = 13'd848; +parameter ap_ST_fsm_state850 = 13'd849; +parameter ap_ST_fsm_state851 = 13'd850; +parameter ap_ST_fsm_state852 = 13'd851; +parameter ap_ST_fsm_state853 = 13'd852; +parameter ap_ST_fsm_state854 = 13'd853; +parameter ap_ST_fsm_state855 = 13'd854; +parameter ap_ST_fsm_state856 = 13'd855; +parameter ap_ST_fsm_state857 = 13'd856; +parameter ap_ST_fsm_state858 = 13'd857; +parameter ap_ST_fsm_state859 = 13'd858; +parameter ap_ST_fsm_state860 = 13'd859; +parameter ap_ST_fsm_state861 = 13'd860; +parameter ap_ST_fsm_state862 = 13'd861; +parameter ap_ST_fsm_state863 = 13'd862; +parameter ap_ST_fsm_state864 = 13'd863; +parameter ap_ST_fsm_state865 = 13'd864; +parameter ap_ST_fsm_state866 = 13'd865; +parameter ap_ST_fsm_state867 = 13'd866; +parameter ap_ST_fsm_state868 = 13'd867; +parameter ap_ST_fsm_state869 = 13'd868; +parameter ap_ST_fsm_state870 = 13'd869; +parameter ap_ST_fsm_state871 = 13'd870; +parameter ap_ST_fsm_state872 = 13'd871; +parameter ap_ST_fsm_state873 = 13'd872; +parameter ap_ST_fsm_state874 = 13'd873; +parameter ap_ST_fsm_state875 = 13'd874; +parameter ap_ST_fsm_state876 = 13'd875; +parameter ap_ST_fsm_state877 = 13'd876; +parameter ap_ST_fsm_state878 = 13'd877; +parameter ap_ST_fsm_state879 = 13'd878; +parameter ap_ST_fsm_state880 = 13'd879; +parameter ap_ST_fsm_state881 = 13'd880; +parameter ap_ST_fsm_state882 = 13'd881; +parameter ap_ST_fsm_state883 = 13'd882; +parameter ap_ST_fsm_state884 = 13'd883; +parameter ap_ST_fsm_state885 = 13'd884; +parameter ap_ST_fsm_state886 = 13'd885; +parameter ap_ST_fsm_state887 = 13'd886; +parameter ap_ST_fsm_state888 = 13'd887; +parameter ap_ST_fsm_state889 = 13'd888; +parameter ap_ST_fsm_state890 = 13'd889; +parameter ap_ST_fsm_state891 = 13'd890; +parameter ap_ST_fsm_state892 = 13'd891; +parameter ap_ST_fsm_state893 = 13'd892; +parameter ap_ST_fsm_state894 = 13'd893; +parameter ap_ST_fsm_state895 = 13'd894; +parameter ap_ST_fsm_state896 = 13'd895; +parameter ap_ST_fsm_state897 = 13'd896; +parameter ap_ST_fsm_state898 = 13'd897; +parameter ap_ST_fsm_state899 = 13'd898; +parameter ap_ST_fsm_state900 = 13'd899; +parameter ap_ST_fsm_state901 = 13'd900; +parameter ap_ST_fsm_state902 = 13'd901; +parameter ap_ST_fsm_state903 = 13'd902; +parameter ap_ST_fsm_state904 = 13'd903; +parameter ap_ST_fsm_state905 = 13'd904; +parameter ap_ST_fsm_state906 = 13'd905; +parameter ap_ST_fsm_state907 = 13'd906; +parameter ap_ST_fsm_state908 = 13'd907; +parameter ap_ST_fsm_state909 = 13'd908; +parameter ap_ST_fsm_state910 = 13'd909; +parameter ap_ST_fsm_state911 = 13'd910; +parameter ap_ST_fsm_state912 = 13'd911; +parameter ap_ST_fsm_state913 = 13'd912; +parameter ap_ST_fsm_state914 = 13'd913; +parameter ap_ST_fsm_state915 = 13'd914; +parameter ap_ST_fsm_state916 = 13'd915; +parameter ap_ST_fsm_state917 = 13'd916; +parameter ap_ST_fsm_state918 = 13'd917; +parameter ap_ST_fsm_state919 = 13'd918; +parameter ap_ST_fsm_state920 = 13'd919; +parameter ap_ST_fsm_state921 = 13'd920; +parameter ap_ST_fsm_state922 = 13'd921; +parameter ap_ST_fsm_state923 = 13'd922; +parameter ap_ST_fsm_state924 = 13'd923; +parameter ap_ST_fsm_state925 = 13'd924; +parameter ap_ST_fsm_state926 = 13'd925; +parameter ap_ST_fsm_state927 = 13'd926; +parameter ap_ST_fsm_state928 = 13'd927; +parameter ap_ST_fsm_state929 = 13'd928; +parameter ap_ST_fsm_state930 = 13'd929; +parameter ap_ST_fsm_state931 = 13'd930; +parameter ap_ST_fsm_state932 = 13'd931; +parameter ap_ST_fsm_state933 = 13'd932; +parameter ap_ST_fsm_state934 = 13'd933; +parameter ap_ST_fsm_state935 = 13'd934; +parameter ap_ST_fsm_state936 = 13'd935; +parameter ap_ST_fsm_state937 = 13'd936; +parameter ap_ST_fsm_state938 = 13'd937; +parameter ap_ST_fsm_state939 = 13'd938; +parameter ap_ST_fsm_state940 = 13'd939; +parameter ap_ST_fsm_state941 = 13'd940; +parameter ap_ST_fsm_state942 = 13'd941; +parameter ap_ST_fsm_state943 = 13'd942; +parameter ap_ST_fsm_state944 = 13'd943; +parameter ap_ST_fsm_state945 = 13'd944; +parameter ap_ST_fsm_state946 = 13'd945; +parameter ap_ST_fsm_state947 = 13'd946; +parameter ap_ST_fsm_state948 = 13'd947; +parameter ap_ST_fsm_state949 = 13'd948; +parameter ap_ST_fsm_state950 = 13'd949; +parameter ap_ST_fsm_state951 = 13'd950; +parameter ap_ST_fsm_state952 = 13'd951; +parameter ap_ST_fsm_state953 = 13'd952; +parameter ap_ST_fsm_state954 = 13'd953; +parameter ap_ST_fsm_state955 = 13'd954; +parameter ap_ST_fsm_state956 = 13'd955; +parameter ap_ST_fsm_state957 = 13'd956; +parameter ap_ST_fsm_state958 = 13'd957; +parameter ap_ST_fsm_state959 = 13'd958; +parameter ap_ST_fsm_state960 = 13'd959; +parameter ap_ST_fsm_state961 = 13'd960; +parameter ap_ST_fsm_state962 = 13'd961; +parameter ap_ST_fsm_state963 = 13'd962; +parameter ap_ST_fsm_state964 = 13'd963; +parameter ap_ST_fsm_state965 = 13'd964; +parameter ap_ST_fsm_state966 = 13'd965; +parameter ap_ST_fsm_state967 = 13'd966; +parameter ap_ST_fsm_state968 = 13'd967; +parameter ap_ST_fsm_state969 = 13'd968; +parameter ap_ST_fsm_state970 = 13'd969; +parameter ap_ST_fsm_state971 = 13'd970; +parameter ap_ST_fsm_state972 = 13'd971; +parameter ap_ST_fsm_state973 = 13'd972; +parameter ap_ST_fsm_state974 = 13'd973; +parameter ap_ST_fsm_state975 = 13'd974; +parameter ap_ST_fsm_state976 = 13'd975; +parameter ap_ST_fsm_state977 = 13'd976; +parameter ap_ST_fsm_state978 = 13'd977; +parameter ap_ST_fsm_state979 = 13'd978; +parameter ap_ST_fsm_state980 = 13'd979; +parameter ap_ST_fsm_state981 = 13'd980; +parameter ap_ST_fsm_state982 = 13'd981; +parameter ap_ST_fsm_state983 = 13'd982; +parameter ap_ST_fsm_state984 = 13'd983; +parameter ap_ST_fsm_state985 = 13'd984; +parameter ap_ST_fsm_state986 = 13'd985; +parameter ap_ST_fsm_state987 = 13'd986; +parameter ap_ST_fsm_state988 = 13'd987; +parameter ap_ST_fsm_state989 = 13'd988; +parameter ap_ST_fsm_state990 = 13'd989; +parameter ap_ST_fsm_state991 = 13'd990; +parameter ap_ST_fsm_state992 = 13'd991; +parameter ap_ST_fsm_state993 = 13'd992; +parameter ap_ST_fsm_state994 = 13'd993; +parameter ap_ST_fsm_state995 = 13'd994; +parameter ap_ST_fsm_state996 = 13'd995; +parameter ap_ST_fsm_state997 = 13'd996; +parameter ap_ST_fsm_state998 = 13'd997; +parameter ap_ST_fsm_state999 = 13'd998; +parameter ap_ST_fsm_state1000 = 13'd999; +parameter ap_ST_fsm_state1001 = 13'd1000; +parameter ap_ST_fsm_state1002 = 13'd1001; +parameter ap_ST_fsm_state1003 = 13'd1002; +parameter ap_ST_fsm_state1004 = 13'd1003; +parameter ap_ST_fsm_state1005 = 13'd1004; +parameter ap_ST_fsm_state1006 = 13'd1005; +parameter ap_ST_fsm_state1007 = 13'd1006; +parameter ap_ST_fsm_state1008 = 13'd1007; +parameter ap_ST_fsm_state1009 = 13'd1008; +parameter ap_ST_fsm_state1010 = 13'd1009; +parameter ap_ST_fsm_state1011 = 13'd1010; +parameter ap_ST_fsm_state1012 = 13'd1011; +parameter ap_ST_fsm_state1013 = 13'd1012; +parameter ap_ST_fsm_state1014 = 13'd1013; +parameter ap_ST_fsm_state1015 = 13'd1014; +parameter ap_ST_fsm_state1016 = 13'd1015; +parameter ap_ST_fsm_state1017 = 13'd1016; +parameter ap_ST_fsm_state1018 = 13'd1017; +parameter ap_ST_fsm_state1019 = 13'd1018; +parameter ap_ST_fsm_state1020 = 13'd1019; +parameter ap_ST_fsm_state1021 = 13'd1020; +parameter ap_ST_fsm_state1022 = 13'd1021; +parameter ap_ST_fsm_state1023 = 13'd1022; +parameter ap_ST_fsm_state1024 = 13'd1023; +parameter ap_ST_fsm_state1025 = 13'd1024; +parameter ap_ST_fsm_state1026 = 13'd1025; +parameter ap_ST_fsm_state1027 = 13'd1026; +parameter ap_ST_fsm_state1028 = 13'd1027; +parameter ap_ST_fsm_state1029 = 13'd1028; +parameter ap_ST_fsm_state1030 = 13'd1029; +parameter ap_ST_fsm_state1031 = 13'd1030; +parameter ap_ST_fsm_state1032 = 13'd1031; +parameter ap_ST_fsm_state1033 = 13'd1032; +parameter ap_ST_fsm_state1034 = 13'd1033; +parameter ap_ST_fsm_state1035 = 13'd1034; +parameter ap_ST_fsm_state1036 = 13'd1035; +parameter ap_ST_fsm_state1037 = 13'd1036; +parameter ap_ST_fsm_state1038 = 13'd1037; +parameter ap_ST_fsm_state1039 = 13'd1038; +parameter ap_ST_fsm_state1040 = 13'd1039; +parameter ap_ST_fsm_state1041 = 13'd1040; +parameter ap_ST_fsm_state1042 = 13'd1041; +parameter ap_ST_fsm_state1043 = 13'd1042; +parameter ap_ST_fsm_state1044 = 13'd1043; +parameter ap_ST_fsm_state1045 = 13'd1044; +parameter ap_ST_fsm_state1046 = 13'd1045; +parameter ap_ST_fsm_state1047 = 13'd1046; +parameter ap_ST_fsm_state1048 = 13'd1047; +parameter ap_ST_fsm_state1049 = 13'd1048; +parameter ap_ST_fsm_state1050 = 13'd1049; +parameter ap_ST_fsm_state1051 = 13'd1050; +parameter ap_ST_fsm_state1052 = 13'd1051; +parameter ap_ST_fsm_state1053 = 13'd1052; +parameter ap_ST_fsm_state1054 = 13'd1053; +parameter ap_ST_fsm_state1055 = 13'd1054; +parameter ap_ST_fsm_state1056 = 13'd1055; +parameter ap_ST_fsm_state1057 = 13'd1056; +parameter ap_ST_fsm_state1058 = 13'd1057; +parameter ap_ST_fsm_state1059 = 13'd1058; +parameter ap_ST_fsm_state1060 = 13'd1059; +parameter ap_ST_fsm_state1061 = 13'd1060; +parameter ap_ST_fsm_state1062 = 13'd1061; +parameter ap_ST_fsm_state1063 = 13'd1062; +parameter ap_ST_fsm_state1064 = 13'd1063; +parameter ap_ST_fsm_state1065 = 13'd1064; +parameter ap_ST_fsm_state1066 = 13'd1065; +parameter ap_ST_fsm_state1067 = 13'd1066; +parameter ap_ST_fsm_state1068 = 13'd1067; +parameter ap_ST_fsm_state1069 = 13'd1068; +parameter ap_ST_fsm_state1070 = 13'd1069; +parameter ap_ST_fsm_state1071 = 13'd1070; +parameter ap_ST_fsm_state1072 = 13'd1071; +parameter ap_ST_fsm_state1073 = 13'd1072; +parameter ap_ST_fsm_state1074 = 13'd1073; +parameter ap_ST_fsm_state1075 = 13'd1074; +parameter ap_ST_fsm_state1076 = 13'd1075; +parameter ap_ST_fsm_state1077 = 13'd1076; +parameter ap_ST_fsm_state1078 = 13'd1077; +parameter ap_ST_fsm_state1079 = 13'd1078; +parameter ap_ST_fsm_state1080 = 13'd1079; +parameter ap_ST_fsm_state1081 = 13'd1080; +parameter ap_ST_fsm_state1082 = 13'd1081; +parameter ap_ST_fsm_state1083 = 13'd1082; +parameter ap_ST_fsm_state1084 = 13'd1083; +parameter ap_ST_fsm_state1085 = 13'd1084; +parameter ap_ST_fsm_state1086 = 13'd1085; +parameter ap_ST_fsm_state1087 = 13'd1086; +parameter ap_ST_fsm_state1088 = 13'd1087; +parameter ap_ST_fsm_state1089 = 13'd1088; +parameter ap_ST_fsm_state1090 = 13'd1089; +parameter ap_ST_fsm_state1091 = 13'd1090; +parameter ap_ST_fsm_state1092 = 13'd1091; +parameter ap_ST_fsm_state1093 = 13'd1092; +parameter ap_ST_fsm_state1094 = 13'd1093; +parameter ap_ST_fsm_state1095 = 13'd1094; +parameter ap_ST_fsm_state1096 = 13'd1095; +parameter ap_ST_fsm_state1097 = 13'd1096; +parameter ap_ST_fsm_state1098 = 13'd1097; +parameter ap_ST_fsm_state1099 = 13'd1098; +parameter ap_ST_fsm_state1100 = 13'd1099; +parameter ap_ST_fsm_state1101 = 13'd1100; +parameter ap_ST_fsm_state1102 = 13'd1101; +parameter ap_ST_fsm_state1103 = 13'd1102; +parameter ap_ST_fsm_state1104 = 13'd1103; +parameter ap_ST_fsm_state1105 = 13'd1104; +parameter ap_ST_fsm_state1106 = 13'd1105; +parameter ap_ST_fsm_state1107 = 13'd1106; +parameter ap_ST_fsm_state1108 = 13'd1107; +parameter ap_ST_fsm_state1109 = 13'd1108; +parameter ap_ST_fsm_state1110 = 13'd1109; +parameter ap_ST_fsm_state1111 = 13'd1110; +parameter ap_ST_fsm_state1112 = 13'd1111; +parameter ap_ST_fsm_state1113 = 13'd1112; +parameter ap_ST_fsm_state1114 = 13'd1113; +parameter ap_ST_fsm_state1115 = 13'd1114; +parameter ap_ST_fsm_state1116 = 13'd1115; +parameter ap_ST_fsm_state1117 = 13'd1116; +parameter ap_ST_fsm_state1118 = 13'd1117; +parameter ap_ST_fsm_state1119 = 13'd1118; +parameter ap_ST_fsm_state1120 = 13'd1119; +parameter ap_ST_fsm_state1121 = 13'd1120; +parameter ap_ST_fsm_state1122 = 13'd1121; +parameter ap_ST_fsm_state1123 = 13'd1122; +parameter ap_ST_fsm_state1124 = 13'd1123; +parameter ap_ST_fsm_state1125 = 13'd1124; +parameter ap_ST_fsm_state1126 = 13'd1125; +parameter ap_ST_fsm_state1127 = 13'd1126; +parameter ap_ST_fsm_state1128 = 13'd1127; +parameter ap_ST_fsm_state1129 = 13'd1128; +parameter ap_ST_fsm_state1130 = 13'd1129; +parameter ap_ST_fsm_state1131 = 13'd1130; +parameter ap_ST_fsm_state1132 = 13'd1131; +parameter ap_ST_fsm_state1133 = 13'd1132; +parameter ap_ST_fsm_state1134 = 13'd1133; +parameter ap_ST_fsm_state1135 = 13'd1134; +parameter ap_ST_fsm_state1136 = 13'd1135; +parameter ap_ST_fsm_state1137 = 13'd1136; +parameter ap_ST_fsm_state1138 = 13'd1137; +parameter ap_ST_fsm_state1139 = 13'd1138; +parameter ap_ST_fsm_state1140 = 13'd1139; +parameter ap_ST_fsm_state1141 = 13'd1140; +parameter ap_ST_fsm_state1142 = 13'd1141; +parameter ap_ST_fsm_state1143 = 13'd1142; +parameter ap_ST_fsm_state1144 = 13'd1143; +parameter ap_ST_fsm_state1145 = 13'd1144; +parameter ap_ST_fsm_state1146 = 13'd1145; +parameter ap_ST_fsm_state1147 = 13'd1146; +parameter ap_ST_fsm_state1148 = 13'd1147; +parameter ap_ST_fsm_state1149 = 13'd1148; +parameter ap_ST_fsm_state1150 = 13'd1149; +parameter ap_ST_fsm_state1151 = 13'd1150; +parameter ap_ST_fsm_state1152 = 13'd1151; +parameter ap_ST_fsm_state1153 = 13'd1152; +parameter ap_ST_fsm_state1154 = 13'd1153; +parameter ap_ST_fsm_state1155 = 13'd1154; +parameter ap_ST_fsm_state1156 = 13'd1155; +parameter ap_ST_fsm_state1157 = 13'd1156; +parameter ap_ST_fsm_state1158 = 13'd1157; +parameter ap_ST_fsm_state1159 = 13'd1158; +parameter ap_ST_fsm_state1160 = 13'd1159; +parameter ap_ST_fsm_state1161 = 13'd1160; +parameter ap_ST_fsm_state1162 = 13'd1161; +parameter ap_ST_fsm_state1163 = 13'd1162; +parameter ap_ST_fsm_state1164 = 13'd1163; +parameter ap_ST_fsm_state1165 = 13'd1164; +parameter ap_ST_fsm_state1166 = 13'd1165; +parameter ap_ST_fsm_state1167 = 13'd1166; +parameter ap_ST_fsm_state1168 = 13'd1167; +parameter ap_ST_fsm_state1169 = 13'd1168; +parameter ap_ST_fsm_state1170 = 13'd1169; +parameter ap_ST_fsm_state1171 = 13'd1170; +parameter ap_ST_fsm_state1172 = 13'd1171; +parameter ap_ST_fsm_state1173 = 13'd1172; +parameter ap_ST_fsm_state1174 = 13'd1173; +parameter ap_ST_fsm_state1175 = 13'd1174; +parameter ap_ST_fsm_state1176 = 13'd1175; +parameter ap_ST_fsm_state1177 = 13'd1176; +parameter ap_ST_fsm_state1178 = 13'd1177; +parameter ap_ST_fsm_state1179 = 13'd1178; +parameter ap_ST_fsm_state1180 = 13'd1179; +parameter ap_ST_fsm_state1181 = 13'd1180; +parameter ap_ST_fsm_state1182 = 13'd1181; +parameter ap_ST_fsm_state1183 = 13'd1182; +parameter ap_ST_fsm_state1184 = 13'd1183; +parameter ap_ST_fsm_state1185 = 13'd1184; +parameter ap_ST_fsm_state1186 = 13'd1185; +parameter ap_ST_fsm_state1187 = 13'd1186; +parameter ap_ST_fsm_state1188 = 13'd1187; +parameter ap_ST_fsm_state1189 = 13'd1188; +parameter ap_ST_fsm_state1190 = 13'd1189; +parameter ap_ST_fsm_state1191 = 13'd1190; +parameter ap_ST_fsm_state1192 = 13'd1191; +parameter ap_ST_fsm_state1193 = 13'd1192; +parameter ap_ST_fsm_state1194 = 13'd1193; +parameter ap_ST_fsm_state1195 = 13'd1194; +parameter ap_ST_fsm_state1196 = 13'd1195; +parameter ap_ST_fsm_state1197 = 13'd1196; +parameter ap_ST_fsm_state1198 = 13'd1197; +parameter ap_ST_fsm_state1199 = 13'd1198; +parameter ap_ST_fsm_state1200 = 13'd1199; +parameter ap_ST_fsm_state1201 = 13'd1200; +parameter ap_ST_fsm_state1202 = 13'd1201; +parameter ap_ST_fsm_state1203 = 13'd1202; +parameter ap_ST_fsm_state1204 = 13'd1203; +parameter ap_ST_fsm_state1205 = 13'd1204; +parameter ap_ST_fsm_state1206 = 13'd1205; +parameter ap_ST_fsm_state1207 = 13'd1206; +parameter ap_ST_fsm_state1208 = 13'd1207; +parameter ap_ST_fsm_state1209 = 13'd1208; +parameter ap_ST_fsm_state1210 = 13'd1209; +parameter ap_ST_fsm_state1211 = 13'd1210; +parameter ap_ST_fsm_state1212 = 13'd1211; +parameter ap_ST_fsm_state1213 = 13'd1212; +parameter ap_ST_fsm_state1214 = 13'd1213; +parameter ap_ST_fsm_state1215 = 13'd1214; +parameter ap_ST_fsm_state1216 = 13'd1215; +parameter ap_ST_fsm_state1217 = 13'd1216; +parameter ap_ST_fsm_state1218 = 13'd1217; +parameter ap_ST_fsm_state1219 = 13'd1218; +parameter ap_ST_fsm_state1220 = 13'd1219; +parameter ap_ST_fsm_state1221 = 13'd1220; +parameter ap_ST_fsm_state1222 = 13'd1221; +parameter ap_ST_fsm_state1223 = 13'd1222; +parameter ap_ST_fsm_state1224 = 13'd1223; +parameter ap_ST_fsm_state1225 = 13'd1224; +parameter ap_ST_fsm_state1226 = 13'd1225; +parameter ap_ST_fsm_state1227 = 13'd1226; +parameter ap_ST_fsm_state1228 = 13'd1227; +parameter ap_ST_fsm_state1229 = 13'd1228; +parameter ap_ST_fsm_state1230 = 13'd1229; +parameter ap_ST_fsm_state1231 = 13'd1230; +parameter ap_ST_fsm_state1232 = 13'd1231; +parameter ap_ST_fsm_state1233 = 13'd1232; +parameter ap_ST_fsm_state1234 = 13'd1233; +parameter ap_ST_fsm_state1235 = 13'd1234; +parameter ap_ST_fsm_state1236 = 13'd1235; +parameter ap_ST_fsm_state1237 = 13'd1236; +parameter ap_ST_fsm_state1238 = 13'd1237; +parameter ap_ST_fsm_state1239 = 13'd1238; +parameter ap_ST_fsm_state1240 = 13'd1239; +parameter ap_ST_fsm_state1241 = 13'd1240; +parameter ap_ST_fsm_state1242 = 13'd1241; +parameter ap_ST_fsm_state1243 = 13'd1242; +parameter ap_ST_fsm_state1244 = 13'd1243; +parameter ap_ST_fsm_state1245 = 13'd1244; +parameter ap_ST_fsm_state1246 = 13'd1245; +parameter ap_ST_fsm_state1247 = 13'd1246; +parameter ap_ST_fsm_state1248 = 13'd1247; +parameter ap_ST_fsm_state1249 = 13'd1248; +parameter ap_ST_fsm_state1250 = 13'd1249; +parameter ap_ST_fsm_state1251 = 13'd1250; +parameter ap_ST_fsm_state1252 = 13'd1251; +parameter ap_ST_fsm_state1253 = 13'd1252; +parameter ap_ST_fsm_state1254 = 13'd1253; +parameter ap_ST_fsm_state1255 = 13'd1254; +parameter ap_ST_fsm_state1256 = 13'd1255; +parameter ap_ST_fsm_state1257 = 13'd1256; +parameter ap_ST_fsm_state1258 = 13'd1257; +parameter ap_ST_fsm_state1259 = 13'd1258; +parameter ap_ST_fsm_state1260 = 13'd1259; +parameter ap_ST_fsm_state1261 = 13'd1260; +parameter ap_ST_fsm_state1262 = 13'd1261; +parameter ap_ST_fsm_state1263 = 13'd1262; +parameter ap_ST_fsm_state1264 = 13'd1263; +parameter ap_ST_fsm_state1265 = 13'd1264; +parameter ap_ST_fsm_state1266 = 13'd1265; +parameter ap_ST_fsm_state1267 = 13'd1266; +parameter ap_ST_fsm_state1268 = 13'd1267; +parameter ap_ST_fsm_state1269 = 13'd1268; +parameter ap_ST_fsm_state1270 = 13'd1269; +parameter ap_ST_fsm_state1271 = 13'd1270; +parameter ap_ST_fsm_state1272 = 13'd1271; +parameter ap_ST_fsm_state1273 = 13'd1272; +parameter ap_ST_fsm_state1274 = 13'd1273; +parameter ap_ST_fsm_state1275 = 13'd1274; +parameter ap_ST_fsm_state1276 = 13'd1275; +parameter ap_ST_fsm_state1277 = 13'd1276; +parameter ap_ST_fsm_state1278 = 13'd1277; +parameter ap_ST_fsm_state1279 = 13'd1278; +parameter ap_ST_fsm_state1280 = 13'd1279; +parameter ap_ST_fsm_state1281 = 13'd1280; +parameter ap_ST_fsm_state1282 = 13'd1281; +parameter ap_ST_fsm_state1283 = 13'd1282; +parameter ap_ST_fsm_state1284 = 13'd1283; +parameter ap_ST_fsm_state1285 = 13'd1284; +parameter ap_ST_fsm_state1286 = 13'd1285; +parameter ap_ST_fsm_state1287 = 13'd1286; +parameter ap_ST_fsm_state1288 = 13'd1287; +parameter ap_ST_fsm_state1289 = 13'd1288; +parameter ap_ST_fsm_state1290 = 13'd1289; +parameter ap_ST_fsm_state1291 = 13'd1290; +parameter ap_ST_fsm_state1292 = 13'd1291; +parameter ap_ST_fsm_state1293 = 13'd1292; +parameter ap_ST_fsm_state1294 = 13'd1293; +parameter ap_ST_fsm_state1295 = 13'd1294; +parameter ap_ST_fsm_state1296 = 13'd1295; +parameter ap_ST_fsm_state1297 = 13'd1296; +parameter ap_ST_fsm_state1298 = 13'd1297; +parameter ap_ST_fsm_state1299 = 13'd1298; +parameter ap_ST_fsm_state1300 = 13'd1299; +parameter ap_ST_fsm_state1301 = 13'd1300; +parameter ap_ST_fsm_state1302 = 13'd1301; +parameter ap_ST_fsm_state1303 = 13'd1302; +parameter ap_ST_fsm_state1304 = 13'd1303; +parameter ap_ST_fsm_state1305 = 13'd1304; +parameter ap_ST_fsm_state1306 = 13'd1305; +parameter ap_ST_fsm_state1307 = 13'd1306; +parameter ap_ST_fsm_state1308 = 13'd1307; +parameter ap_ST_fsm_state1309 = 13'd1308; +parameter ap_ST_fsm_state1310 = 13'd1309; +parameter ap_ST_fsm_state1311 = 13'd1310; +parameter ap_ST_fsm_state1312 = 13'd1311; +parameter ap_ST_fsm_state1313 = 13'd1312; +parameter ap_ST_fsm_state1314 = 13'd1313; +parameter ap_ST_fsm_state1315 = 13'd1314; +parameter ap_ST_fsm_state1316 = 13'd1315; +parameter ap_ST_fsm_state1317 = 13'd1316; +parameter ap_ST_fsm_state1318 = 13'd1317; +parameter ap_ST_fsm_state1319 = 13'd1318; +parameter ap_ST_fsm_state1320 = 13'd1319; +parameter ap_ST_fsm_state1321 = 13'd1320; +parameter ap_ST_fsm_state1322 = 13'd1321; +parameter ap_ST_fsm_state1323 = 13'd1322; +parameter ap_ST_fsm_state1324 = 13'd1323; +parameter ap_ST_fsm_state1325 = 13'd1324; +parameter ap_ST_fsm_state1326 = 13'd1325; +parameter ap_ST_fsm_state1327 = 13'd1326; +parameter ap_ST_fsm_state1328 = 13'd1327; +parameter ap_ST_fsm_state1329 = 13'd1328; +parameter ap_ST_fsm_state1330 = 13'd1329; +parameter ap_ST_fsm_state1331 = 13'd1330; +parameter ap_ST_fsm_state1332 = 13'd1331; +parameter ap_ST_fsm_state1333 = 13'd1332; +parameter ap_ST_fsm_state1334 = 13'd1333; +parameter ap_ST_fsm_state1335 = 13'd1334; +parameter ap_ST_fsm_state1336 = 13'd1335; +parameter ap_ST_fsm_state1337 = 13'd1336; +parameter ap_ST_fsm_state1338 = 13'd1337; +parameter ap_ST_fsm_state1339 = 13'd1338; +parameter ap_ST_fsm_state1340 = 13'd1339; +parameter ap_ST_fsm_state1341 = 13'd1340; +parameter ap_ST_fsm_state1342 = 13'd1341; +parameter ap_ST_fsm_state1343 = 13'd1342; +parameter ap_ST_fsm_state1344 = 13'd1343; +parameter ap_ST_fsm_state1345 = 13'd1344; +parameter ap_ST_fsm_state1346 = 13'd1345; +parameter ap_ST_fsm_state1347 = 13'd1346; +parameter ap_ST_fsm_state1348 = 13'd1347; +parameter ap_ST_fsm_state1349 = 13'd1348; +parameter ap_ST_fsm_state1350 = 13'd1349; +parameter ap_ST_fsm_state1351 = 13'd1350; +parameter ap_ST_fsm_state1352 = 13'd1351; +parameter ap_ST_fsm_state1353 = 13'd1352; +parameter ap_ST_fsm_state1354 = 13'd1353; +parameter ap_ST_fsm_state1355 = 13'd1354; +parameter ap_ST_fsm_state1356 = 13'd1355; +parameter ap_ST_fsm_state1357 = 13'd1356; +parameter ap_ST_fsm_state1358 = 13'd1357; +parameter ap_ST_fsm_state1359 = 13'd1358; +parameter ap_ST_fsm_state1360 = 13'd1359; +parameter ap_ST_fsm_state1361 = 13'd1360; +parameter ap_ST_fsm_state1362 = 13'd1361; +parameter ap_ST_fsm_state1363 = 13'd1362; +parameter ap_ST_fsm_state1364 = 13'd1363; +parameter ap_ST_fsm_state1365 = 13'd1364; +parameter ap_ST_fsm_state1366 = 13'd1365; +parameter ap_ST_fsm_state1367 = 13'd1366; +parameter ap_ST_fsm_state1368 = 13'd1367; +parameter ap_ST_fsm_state1369 = 13'd1368; +parameter ap_ST_fsm_state1370 = 13'd1369; +parameter ap_ST_fsm_state1371 = 13'd1370; +parameter ap_ST_fsm_state1372 = 13'd1371; +parameter ap_ST_fsm_state1373 = 13'd1372; +parameter ap_ST_fsm_state1374 = 13'd1373; +parameter ap_ST_fsm_state1375 = 13'd1374; +parameter ap_ST_fsm_state1376 = 13'd1375; +parameter ap_ST_fsm_state1377 = 13'd1376; +parameter ap_ST_fsm_state1378 = 13'd1377; +parameter ap_ST_fsm_state1379 = 13'd1378; +parameter ap_ST_fsm_state1380 = 13'd1379; +parameter ap_ST_fsm_state1381 = 13'd1380; +parameter ap_ST_fsm_state1382 = 13'd1381; +parameter ap_ST_fsm_state1383 = 13'd1382; +parameter ap_ST_fsm_state1384 = 13'd1383; +parameter ap_ST_fsm_state1385 = 13'd1384; +parameter ap_ST_fsm_state1386 = 13'd1385; +parameter ap_ST_fsm_state1387 = 13'd1386; +parameter ap_ST_fsm_state1388 = 13'd1387; +parameter ap_ST_fsm_state1389 = 13'd1388; +parameter ap_ST_fsm_state1390 = 13'd1389; +parameter ap_ST_fsm_state1391 = 13'd1390; +parameter ap_ST_fsm_state1392 = 13'd1391; +parameter ap_ST_fsm_state1393 = 13'd1392; +parameter ap_ST_fsm_state1394 = 13'd1393; +parameter ap_ST_fsm_state1395 = 13'd1394; +parameter ap_ST_fsm_state1396 = 13'd1395; +parameter ap_ST_fsm_state1397 = 13'd1396; +parameter ap_ST_fsm_state1398 = 13'd1397; +parameter ap_ST_fsm_state1399 = 13'd1398; +parameter ap_ST_fsm_state1400 = 13'd1399; +parameter ap_ST_fsm_state1401 = 13'd1400; +parameter ap_ST_fsm_state1402 = 13'd1401; +parameter ap_ST_fsm_state1403 = 13'd1402; +parameter ap_ST_fsm_state1404 = 13'd1403; +parameter ap_ST_fsm_state1405 = 13'd1404; +parameter ap_ST_fsm_state1406 = 13'd1405; +parameter ap_ST_fsm_state1407 = 13'd1406; +parameter ap_ST_fsm_state1408 = 13'd1407; +parameter ap_ST_fsm_state1409 = 13'd1408; +parameter ap_ST_fsm_state1410 = 13'd1409; +parameter ap_ST_fsm_state1411 = 13'd1410; +parameter ap_ST_fsm_state1412 = 13'd1411; +parameter ap_ST_fsm_state1413 = 13'd1412; +parameter ap_ST_fsm_state1414 = 13'd1413; +parameter ap_ST_fsm_state1415 = 13'd1414; +parameter ap_ST_fsm_state1416 = 13'd1415; +parameter ap_ST_fsm_state1417 = 13'd1416; +parameter ap_ST_fsm_state1418 = 13'd1417; +parameter ap_ST_fsm_state1419 = 13'd1418; +parameter ap_ST_fsm_state1420 = 13'd1419; +parameter ap_ST_fsm_state1421 = 13'd1420; +parameter ap_ST_fsm_state1422 = 13'd1421; +parameter ap_ST_fsm_state1423 = 13'd1422; +parameter ap_ST_fsm_state1424 = 13'd1423; +parameter ap_ST_fsm_state1425 = 13'd1424; +parameter ap_ST_fsm_state1426 = 13'd1425; +parameter ap_ST_fsm_state1427 = 13'd1426; +parameter ap_ST_fsm_state1428 = 13'd1427; +parameter ap_ST_fsm_state1429 = 13'd1428; +parameter ap_ST_fsm_state1430 = 13'd1429; +parameter ap_ST_fsm_state1431 = 13'd1430; +parameter ap_ST_fsm_state1432 = 13'd1431; +parameter ap_ST_fsm_state1433 = 13'd1432; +parameter ap_ST_fsm_state1434 = 13'd1433; +parameter ap_ST_fsm_state1435 = 13'd1434; +parameter ap_ST_fsm_state1436 = 13'd1435; +parameter ap_ST_fsm_state1437 = 13'd1436; +parameter ap_ST_fsm_state1438 = 13'd1437; +parameter ap_ST_fsm_state1439 = 13'd1438; +parameter ap_ST_fsm_state1440 = 13'd1439; +parameter ap_ST_fsm_state1441 = 13'd1440; +parameter ap_ST_fsm_state1442 = 13'd1441; +parameter ap_ST_fsm_state1443 = 13'd1442; +parameter ap_ST_fsm_state1444 = 13'd1443; +parameter ap_ST_fsm_state1445 = 13'd1444; +parameter ap_ST_fsm_state1446 = 13'd1445; +parameter ap_ST_fsm_state1447 = 13'd1446; +parameter ap_ST_fsm_state1448 = 13'd1447; +parameter ap_ST_fsm_state1449 = 13'd1448; +parameter ap_ST_fsm_state1450 = 13'd1449; +parameter ap_ST_fsm_state1451 = 13'd1450; +parameter ap_ST_fsm_state1452 = 13'd1451; +parameter ap_ST_fsm_state1453 = 13'd1452; +parameter ap_ST_fsm_state1454 = 13'd1453; +parameter ap_ST_fsm_state1455 = 13'd1454; +parameter ap_ST_fsm_state1456 = 13'd1455; +parameter ap_ST_fsm_state1457 = 13'd1456; +parameter ap_ST_fsm_state1458 = 13'd1457; +parameter ap_ST_fsm_state1459 = 13'd1458; +parameter ap_ST_fsm_state1460 = 13'd1459; +parameter ap_ST_fsm_state1461 = 13'd1460; +parameter ap_ST_fsm_state1462 = 13'd1461; +parameter ap_ST_fsm_state1463 = 13'd1462; +parameter ap_ST_fsm_state1464 = 13'd1463; +parameter ap_ST_fsm_state1465 = 13'd1464; +parameter ap_ST_fsm_state1466 = 13'd1465; +parameter ap_ST_fsm_state1467 = 13'd1466; +parameter ap_ST_fsm_state1468 = 13'd1467; +parameter ap_ST_fsm_state1469 = 13'd1468; +parameter ap_ST_fsm_state1470 = 13'd1469; +parameter ap_ST_fsm_state1471 = 13'd1470; +parameter ap_ST_fsm_state1472 = 13'd1471; +parameter ap_ST_fsm_state1473 = 13'd1472; +parameter ap_ST_fsm_state1474 = 13'd1473; +parameter ap_ST_fsm_state1475 = 13'd1474; +parameter ap_ST_fsm_state1476 = 13'd1475; +parameter ap_ST_fsm_state1477 = 13'd1476; +parameter ap_ST_fsm_state1478 = 13'd1477; +parameter ap_ST_fsm_state1479 = 13'd1478; +parameter ap_ST_fsm_state1480 = 13'd1479; +parameter ap_ST_fsm_state1481 = 13'd1480; +parameter ap_ST_fsm_state1482 = 13'd1481; +parameter ap_ST_fsm_state1483 = 13'd1482; +parameter ap_ST_fsm_state1484 = 13'd1483; +parameter ap_ST_fsm_state1485 = 13'd1484; +parameter ap_ST_fsm_state1486 = 13'd1485; +parameter ap_ST_fsm_state1487 = 13'd1486; +parameter ap_ST_fsm_state1488 = 13'd1487; +parameter ap_ST_fsm_state1489 = 13'd1488; +parameter ap_ST_fsm_state1490 = 13'd1489; +parameter ap_ST_fsm_state1491 = 13'd1490; +parameter ap_ST_fsm_state1492 = 13'd1491; +parameter ap_ST_fsm_state1493 = 13'd1492; +parameter ap_ST_fsm_state1494 = 13'd1493; +parameter ap_ST_fsm_state1495 = 13'd1494; +parameter ap_ST_fsm_state1496 = 13'd1495; +parameter ap_ST_fsm_state1497 = 13'd1496; +parameter ap_ST_fsm_state1498 = 13'd1497; +parameter ap_ST_fsm_state1499 = 13'd1498; +parameter ap_ST_fsm_state1500 = 13'd1499; +parameter ap_ST_fsm_state1501 = 13'd1500; +parameter ap_ST_fsm_state1502 = 13'd1501; +parameter ap_ST_fsm_state1503 = 13'd1502; +parameter ap_ST_fsm_state1504 = 13'd1503; +parameter ap_ST_fsm_state1505 = 13'd1504; +parameter ap_ST_fsm_state1506 = 13'd1505; +parameter ap_ST_fsm_state1507 = 13'd1506; +parameter ap_ST_fsm_state1508 = 13'd1507; +parameter ap_ST_fsm_state1509 = 13'd1508; +parameter ap_ST_fsm_state1510 = 13'd1509; +parameter ap_ST_fsm_state1511 = 13'd1510; +parameter ap_ST_fsm_state1512 = 13'd1511; +parameter ap_ST_fsm_state1513 = 13'd1512; +parameter ap_ST_fsm_state1514 = 13'd1513; +parameter ap_ST_fsm_state1515 = 13'd1514; +parameter ap_ST_fsm_state1516 = 13'd1515; +parameter ap_ST_fsm_state1517 = 13'd1516; +parameter ap_ST_fsm_state1518 = 13'd1517; +parameter ap_ST_fsm_state1519 = 13'd1518; +parameter ap_ST_fsm_state1520 = 13'd1519; +parameter ap_ST_fsm_state1521 = 13'd1520; +parameter ap_ST_fsm_state1522 = 13'd1521; +parameter ap_ST_fsm_state1523 = 13'd1522; +parameter ap_ST_fsm_state1524 = 13'd1523; +parameter ap_ST_fsm_state1525 = 13'd1524; +parameter ap_ST_fsm_state1526 = 13'd1525; +parameter ap_ST_fsm_state1527 = 13'd1526; +parameter ap_ST_fsm_state1528 = 13'd1527; +parameter ap_ST_fsm_state1529 = 13'd1528; +parameter ap_ST_fsm_state1530 = 13'd1529; +parameter ap_ST_fsm_state1531 = 13'd1530; +parameter ap_ST_fsm_state1532 = 13'd1531; +parameter ap_ST_fsm_state1533 = 13'd1532; +parameter ap_ST_fsm_state1534 = 13'd1533; +parameter ap_ST_fsm_state1535 = 13'd1534; +parameter ap_ST_fsm_state1536 = 13'd1535; +parameter ap_ST_fsm_state1537 = 13'd1536; +parameter ap_ST_fsm_state1538 = 13'd1537; +parameter ap_ST_fsm_state1539 = 13'd1538; +parameter ap_ST_fsm_state1540 = 13'd1539; +parameter ap_ST_fsm_state1541 = 13'd1540; +parameter ap_ST_fsm_state1542 = 13'd1541; +parameter ap_ST_fsm_state1543 = 13'd1542; +parameter ap_ST_fsm_state1544 = 13'd1543; +parameter ap_ST_fsm_state1545 = 13'd1544; +parameter ap_ST_fsm_state1546 = 13'd1545; +parameter ap_ST_fsm_state1547 = 13'd1546; +parameter ap_ST_fsm_state1548 = 13'd1547; +parameter ap_ST_fsm_state1549 = 13'd1548; +parameter ap_ST_fsm_state1550 = 13'd1549; +parameter ap_ST_fsm_state1551 = 13'd1550; +parameter ap_ST_fsm_state1552 = 13'd1551; +parameter ap_ST_fsm_state1553 = 13'd1552; +parameter ap_ST_fsm_state1554 = 13'd1553; +parameter ap_ST_fsm_state1555 = 13'd1554; +parameter ap_ST_fsm_state1556 = 13'd1555; +parameter ap_ST_fsm_state1557 = 13'd1556; +parameter ap_ST_fsm_state1558 = 13'd1557; +parameter ap_ST_fsm_state1559 = 13'd1558; +parameter ap_ST_fsm_state1560 = 13'd1559; +parameter ap_ST_fsm_state1561 = 13'd1560; +parameter ap_ST_fsm_state1562 = 13'd1561; +parameter ap_ST_fsm_state1563 = 13'd1562; +parameter ap_ST_fsm_state1564 = 13'd1563; +parameter ap_ST_fsm_state1565 = 13'd1564; +parameter ap_ST_fsm_state1566 = 13'd1565; +parameter ap_ST_fsm_state1567 = 13'd1566; +parameter ap_ST_fsm_state1568 = 13'd1567; +parameter ap_ST_fsm_state1569 = 13'd1568; +parameter ap_ST_fsm_state1570 = 13'd1569; +parameter ap_ST_fsm_state1571 = 13'd1570; +parameter ap_ST_fsm_state1572 = 13'd1571; +parameter ap_ST_fsm_state1573 = 13'd1572; +parameter ap_ST_fsm_state1574 = 13'd1573; +parameter ap_ST_fsm_state1575 = 13'd1574; +parameter ap_ST_fsm_state1576 = 13'd1575; +parameter ap_ST_fsm_state1577 = 13'd1576; +parameter ap_ST_fsm_state1578 = 13'd1577; +parameter ap_ST_fsm_state1579 = 13'd1578; +parameter ap_ST_fsm_state1580 = 13'd1579; +parameter ap_ST_fsm_state1581 = 13'd1580; +parameter ap_ST_fsm_state1582 = 13'd1581; +parameter ap_ST_fsm_state1583 = 13'd1582; +parameter ap_ST_fsm_state1584 = 13'd1583; +parameter ap_ST_fsm_state1585 = 13'd1584; +parameter ap_ST_fsm_state1586 = 13'd1585; +parameter ap_ST_fsm_state1587 = 13'd1586; +parameter ap_ST_fsm_state1588 = 13'd1587; +parameter ap_ST_fsm_state1589 = 13'd1588; +parameter ap_ST_fsm_state1590 = 13'd1589; +parameter ap_ST_fsm_state1591 = 13'd1590; +parameter ap_ST_fsm_state1592 = 13'd1591; +parameter ap_ST_fsm_state1593 = 13'd1592; +parameter ap_ST_fsm_state1594 = 13'd1593; +parameter ap_ST_fsm_state1595 = 13'd1594; +parameter ap_ST_fsm_state1596 = 13'd1595; +parameter ap_ST_fsm_state1597 = 13'd1596; +parameter ap_ST_fsm_state1598 = 13'd1597; +parameter ap_ST_fsm_state1599 = 13'd1598; +parameter ap_ST_fsm_state1600 = 13'd1599; +parameter ap_ST_fsm_state1601 = 13'd1600; +parameter ap_ST_fsm_state1602 = 13'd1601; +parameter ap_ST_fsm_state1603 = 13'd1602; +parameter ap_ST_fsm_state1604 = 13'd1603; +parameter ap_ST_fsm_state1605 = 13'd1604; +parameter ap_ST_fsm_state1606 = 13'd1605; +parameter ap_ST_fsm_state1607 = 13'd1606; +parameter ap_ST_fsm_state1608 = 13'd1607; +parameter ap_ST_fsm_state1609 = 13'd1608; +parameter ap_ST_fsm_state1610 = 13'd1609; +parameter ap_ST_fsm_state1611 = 13'd1610; +parameter ap_ST_fsm_state1612 = 13'd1611; +parameter ap_ST_fsm_state1613 = 13'd1612; +parameter ap_ST_fsm_state1614 = 13'd1613; +parameter ap_ST_fsm_state1615 = 13'd1614; +parameter ap_ST_fsm_state1616 = 13'd1615; +parameter ap_ST_fsm_state1617 = 13'd1616; +parameter ap_ST_fsm_state1618 = 13'd1617; +parameter ap_ST_fsm_state1619 = 13'd1618; +parameter ap_ST_fsm_state1620 = 13'd1619; +parameter ap_ST_fsm_state1621 = 13'd1620; +parameter ap_ST_fsm_state1622 = 13'd1621; +parameter ap_ST_fsm_state1623 = 13'd1622; +parameter ap_ST_fsm_state1624 = 13'd1623; +parameter ap_ST_fsm_state1625 = 13'd1624; +parameter ap_ST_fsm_state1626 = 13'd1625; +parameter ap_ST_fsm_state1627 = 13'd1626; +parameter ap_ST_fsm_state1628 = 13'd1627; +parameter ap_ST_fsm_state1629 = 13'd1628; +parameter ap_ST_fsm_state1630 = 13'd1629; +parameter ap_ST_fsm_state1631 = 13'd1630; +parameter ap_ST_fsm_state1632 = 13'd1631; +parameter ap_ST_fsm_state1633 = 13'd1632; +parameter ap_ST_fsm_state1634 = 13'd1633; +parameter ap_ST_fsm_state1635 = 13'd1634; +parameter ap_ST_fsm_state1636 = 13'd1635; +parameter ap_ST_fsm_state1637 = 13'd1636; +parameter ap_ST_fsm_state1638 = 13'd1637; +parameter ap_ST_fsm_state1639 = 13'd1638; +parameter ap_ST_fsm_state1640 = 13'd1639; +parameter ap_ST_fsm_state1641 = 13'd1640; +parameter ap_ST_fsm_state1642 = 13'd1641; +parameter ap_ST_fsm_state1643 = 13'd1642; +parameter ap_ST_fsm_state1644 = 13'd1643; +parameter ap_ST_fsm_state1645 = 13'd1644; +parameter ap_ST_fsm_state1646 = 13'd1645; +parameter ap_ST_fsm_state1647 = 13'd1646; +parameter ap_ST_fsm_state1648 = 13'd1647; +parameter ap_ST_fsm_state1649 = 13'd1648; +parameter ap_ST_fsm_state1650 = 13'd1649; +parameter ap_ST_fsm_state1651 = 13'd1650; +parameter ap_ST_fsm_state1652 = 13'd1651; +parameter ap_ST_fsm_state1653 = 13'd1652; +parameter ap_ST_fsm_state1654 = 13'd1653; +parameter ap_ST_fsm_state1655 = 13'd1654; +parameter ap_ST_fsm_state1656 = 13'd1655; +parameter ap_ST_fsm_state1657 = 13'd1656; +parameter ap_ST_fsm_state1658 = 13'd1657; +parameter ap_ST_fsm_state1659 = 13'd1658; +parameter ap_ST_fsm_state1660 = 13'd1659; +parameter ap_ST_fsm_state1661 = 13'd1660; +parameter ap_ST_fsm_state1662 = 13'd1661; +parameter ap_ST_fsm_state1663 = 13'd1662; +parameter ap_ST_fsm_state1664 = 13'd1663; +parameter ap_ST_fsm_state1665 = 13'd1664; +parameter ap_ST_fsm_state1666 = 13'd1665; +parameter ap_ST_fsm_state1667 = 13'd1666; +parameter ap_ST_fsm_state1668 = 13'd1667; +parameter ap_ST_fsm_state1669 = 13'd1668; +parameter ap_ST_fsm_state1670 = 13'd1669; +parameter ap_ST_fsm_state1671 = 13'd1670; +parameter ap_ST_fsm_state1672 = 13'd1671; +parameter ap_ST_fsm_state1673 = 13'd1672; +parameter ap_ST_fsm_state1674 = 13'd1673; +parameter ap_ST_fsm_state1675 = 13'd1674; +parameter ap_ST_fsm_state1676 = 13'd1675; +parameter ap_ST_fsm_state1677 = 13'd1676; +parameter ap_ST_fsm_state1678 = 13'd1677; +parameter ap_ST_fsm_state1679 = 13'd1678; +parameter ap_ST_fsm_state1680 = 13'd1679; +parameter ap_ST_fsm_state1681 = 13'd1680; +parameter ap_ST_fsm_state1682 = 13'd1681; +parameter ap_ST_fsm_state1683 = 13'd1682; +parameter ap_ST_fsm_state1684 = 13'd1683; +parameter ap_ST_fsm_state1685 = 13'd1684; +parameter ap_ST_fsm_state1686 = 13'd1685; +parameter ap_ST_fsm_state1687 = 13'd1686; +parameter ap_ST_fsm_state1688 = 13'd1687; +parameter ap_ST_fsm_state1689 = 13'd1688; +parameter ap_ST_fsm_state1690 = 13'd1689; +parameter ap_ST_fsm_state1691 = 13'd1690; +parameter ap_ST_fsm_state1692 = 13'd1691; +parameter ap_ST_fsm_state1693 = 13'd1692; +parameter ap_ST_fsm_state1694 = 13'd1693; +parameter ap_ST_fsm_state1695 = 13'd1694; +parameter ap_ST_fsm_state1696 = 13'd1695; +parameter ap_ST_fsm_state1697 = 13'd1696; +parameter ap_ST_fsm_state1698 = 13'd1697; +parameter ap_ST_fsm_state1699 = 13'd1698; +parameter ap_ST_fsm_state1700 = 13'd1699; +parameter ap_ST_fsm_state1701 = 13'd1700; +parameter ap_ST_fsm_state1702 = 13'd1701; +parameter ap_ST_fsm_state1703 = 13'd1702; +parameter ap_ST_fsm_state1704 = 13'd1703; +parameter ap_ST_fsm_state1705 = 13'd1704; +parameter ap_ST_fsm_state1706 = 13'd1705; +parameter ap_ST_fsm_state1707 = 13'd1706; +parameter ap_ST_fsm_state1708 = 13'd1707; +parameter ap_ST_fsm_state1709 = 13'd1708; +parameter ap_ST_fsm_state1710 = 13'd1709; +parameter ap_ST_fsm_state1711 = 13'd1710; +parameter ap_ST_fsm_state1712 = 13'd1711; +parameter ap_ST_fsm_state1713 = 13'd1712; +parameter ap_ST_fsm_state1714 = 13'd1713; +parameter ap_ST_fsm_state1715 = 13'd1714; +parameter ap_ST_fsm_state1716 = 13'd1715; +parameter ap_ST_fsm_state1717 = 13'd1716; +parameter ap_ST_fsm_state1718 = 13'd1717; +parameter ap_ST_fsm_state1719 = 13'd1718; +parameter ap_ST_fsm_state1720 = 13'd1719; +parameter ap_ST_fsm_state1721 = 13'd1720; +parameter ap_ST_fsm_state1722 = 13'd1721; +parameter ap_ST_fsm_state1723 = 13'd1722; +parameter ap_ST_fsm_state1724 = 13'd1723; +parameter ap_ST_fsm_state1725 = 13'd1724; +parameter ap_ST_fsm_state1726 = 13'd1725; +parameter ap_ST_fsm_state1727 = 13'd1726; +parameter ap_ST_fsm_state1728 = 13'd1727; +parameter ap_ST_fsm_state1729 = 13'd1728; +parameter ap_ST_fsm_state1730 = 13'd1729; +parameter ap_ST_fsm_state1731 = 13'd1730; +parameter ap_ST_fsm_state1732 = 13'd1731; +parameter ap_ST_fsm_state1733 = 13'd1732; +parameter ap_ST_fsm_state1734 = 13'd1733; +parameter ap_ST_fsm_state1735 = 13'd1734; +parameter ap_ST_fsm_state1736 = 13'd1735; +parameter ap_ST_fsm_state1737 = 13'd1736; +parameter ap_ST_fsm_state1738 = 13'd1737; +parameter ap_ST_fsm_state1739 = 13'd1738; +parameter ap_ST_fsm_state1740 = 13'd1739; +parameter ap_ST_fsm_state1741 = 13'd1740; +parameter ap_ST_fsm_state1742 = 13'd1741; +parameter ap_ST_fsm_state1743 = 13'd1742; +parameter ap_ST_fsm_state1744 = 13'd1743; +parameter ap_ST_fsm_state1745 = 13'd1744; +parameter ap_ST_fsm_state1746 = 13'd1745; +parameter ap_ST_fsm_state1747 = 13'd1746; +parameter ap_ST_fsm_state1748 = 13'd1747; +parameter ap_ST_fsm_state1749 = 13'd1748; +parameter ap_ST_fsm_state1750 = 13'd1749; +parameter ap_ST_fsm_state1751 = 13'd1750; +parameter ap_ST_fsm_state1752 = 13'd1751; +parameter ap_ST_fsm_state1753 = 13'd1752; +parameter ap_ST_fsm_state1754 = 13'd1753; +parameter ap_ST_fsm_state1755 = 13'd1754; +parameter ap_ST_fsm_state1756 = 13'd1755; +parameter ap_ST_fsm_state1757 = 13'd1756; +parameter ap_ST_fsm_state1758 = 13'd1757; +parameter ap_ST_fsm_state1759 = 13'd1758; +parameter ap_ST_fsm_state1760 = 13'd1759; +parameter ap_ST_fsm_state1761 = 13'd1760; +parameter ap_ST_fsm_state1762 = 13'd1761; +parameter ap_ST_fsm_state1763 = 13'd1762; +parameter ap_ST_fsm_state1764 = 13'd1763; +parameter ap_ST_fsm_state1765 = 13'd1764; +parameter ap_ST_fsm_state1766 = 13'd1765; +parameter ap_ST_fsm_state1767 = 13'd1766; +parameter ap_ST_fsm_state1768 = 13'd1767; +parameter ap_ST_fsm_state1769 = 13'd1768; +parameter ap_ST_fsm_state1770 = 13'd1769; +parameter ap_ST_fsm_state1771 = 13'd1770; +parameter ap_ST_fsm_state1772 = 13'd1771; +parameter ap_ST_fsm_state1773 = 13'd1772; +parameter ap_ST_fsm_state1774 = 13'd1773; +parameter ap_ST_fsm_state1775 = 13'd1774; +parameter ap_ST_fsm_state1776 = 13'd1775; +parameter ap_ST_fsm_state1777 = 13'd1776; +parameter ap_ST_fsm_state1778 = 13'd1777; +parameter ap_ST_fsm_state1779 = 13'd1778; +parameter ap_ST_fsm_state1780 = 13'd1779; +parameter ap_ST_fsm_state1781 = 13'd1780; +parameter ap_ST_fsm_state1782 = 13'd1781; +parameter ap_ST_fsm_state1783 = 13'd1782; +parameter ap_ST_fsm_state1784 = 13'd1783; +parameter ap_ST_fsm_state1785 = 13'd1784; +parameter ap_ST_fsm_state1786 = 13'd1785; +parameter ap_ST_fsm_state1787 = 13'd1786; +parameter ap_ST_fsm_state1788 = 13'd1787; +parameter ap_ST_fsm_state1789 = 13'd1788; +parameter ap_ST_fsm_state1790 = 13'd1789; +parameter ap_ST_fsm_state1791 = 13'd1790; +parameter ap_ST_fsm_state1792 = 13'd1791; +parameter ap_ST_fsm_state1793 = 13'd1792; +parameter ap_ST_fsm_state1794 = 13'd1793; +parameter ap_ST_fsm_state1795 = 13'd1794; +parameter ap_ST_fsm_state1796 = 13'd1795; +parameter ap_ST_fsm_state1797 = 13'd1796; +parameter ap_ST_fsm_state1798 = 13'd1797; +parameter ap_ST_fsm_state1799 = 13'd1798; +parameter ap_ST_fsm_state1800 = 13'd1799; +parameter ap_ST_fsm_state1801 = 13'd1800; +parameter ap_ST_fsm_state1802 = 13'd1801; +parameter ap_ST_fsm_state1803 = 13'd1802; +parameter ap_ST_fsm_state1804 = 13'd1803; +parameter ap_ST_fsm_state1805 = 13'd1804; +parameter ap_ST_fsm_state1806 = 13'd1805; +parameter ap_ST_fsm_state1807 = 13'd1806; +parameter ap_ST_fsm_state1808 = 13'd1807; +parameter ap_ST_fsm_state1809 = 13'd1808; +parameter ap_ST_fsm_state1810 = 13'd1809; +parameter ap_ST_fsm_state1811 = 13'd1810; +parameter ap_ST_fsm_state1812 = 13'd1811; +parameter ap_ST_fsm_state1813 = 13'd1812; +parameter ap_ST_fsm_state1814 = 13'd1813; +parameter ap_ST_fsm_state1815 = 13'd1814; +parameter ap_ST_fsm_state1816 = 13'd1815; +parameter ap_ST_fsm_state1817 = 13'd1816; +parameter ap_ST_fsm_state1818 = 13'd1817; +parameter ap_ST_fsm_state1819 = 13'd1818; +parameter ap_ST_fsm_state1820 = 13'd1819; +parameter ap_ST_fsm_state1821 = 13'd1820; +parameter ap_ST_fsm_state1822 = 13'd1821; +parameter ap_ST_fsm_state1823 = 13'd1822; +parameter ap_ST_fsm_state1824 = 13'd1823; +parameter ap_ST_fsm_state1825 = 13'd1824; +parameter ap_ST_fsm_state1826 = 13'd1825; +parameter ap_ST_fsm_state1827 = 13'd1826; +parameter ap_ST_fsm_state1828 = 13'd1827; +parameter ap_ST_fsm_state1829 = 13'd1828; +parameter ap_ST_fsm_state1830 = 13'd1829; +parameter ap_ST_fsm_state1831 = 13'd1830; +parameter ap_ST_fsm_state1832 = 13'd1831; +parameter ap_ST_fsm_state1833 = 13'd1832; +parameter ap_ST_fsm_state1834 = 13'd1833; +parameter ap_ST_fsm_state1835 = 13'd1834; +parameter ap_ST_fsm_state1836 = 13'd1835; +parameter ap_ST_fsm_state1837 = 13'd1836; +parameter ap_ST_fsm_state1838 = 13'd1837; +parameter ap_ST_fsm_state1839 = 13'd1838; +parameter ap_ST_fsm_state1840 = 13'd1839; +parameter ap_ST_fsm_state1841 = 13'd1840; +parameter ap_ST_fsm_state1842 = 13'd1841; +parameter ap_ST_fsm_state1843 = 13'd1842; +parameter ap_ST_fsm_state1844 = 13'd1843; +parameter ap_ST_fsm_state1845 = 13'd1844; +parameter ap_ST_fsm_state1846 = 13'd1845; +parameter ap_ST_fsm_state1847 = 13'd1846; +parameter ap_ST_fsm_state1848 = 13'd1847; +parameter ap_ST_fsm_state1849 = 13'd1848; +parameter ap_ST_fsm_state1850 = 13'd1849; +parameter ap_ST_fsm_state1851 = 13'd1850; +parameter ap_ST_fsm_state1852 = 13'd1851; +parameter ap_ST_fsm_state1853 = 13'd1852; +parameter ap_ST_fsm_state1854 = 13'd1853; +parameter ap_ST_fsm_state1855 = 13'd1854; +parameter ap_ST_fsm_state1856 = 13'd1855; +parameter ap_ST_fsm_state1857 = 13'd1856; +parameter ap_ST_fsm_state1858 = 13'd1857; +parameter ap_ST_fsm_state1859 = 13'd1858; +parameter ap_ST_fsm_state1860 = 13'd1859; +parameter ap_ST_fsm_state1861 = 13'd1860; +parameter ap_ST_fsm_state1862 = 13'd1861; +parameter ap_ST_fsm_state1863 = 13'd1862; +parameter ap_ST_fsm_state1864 = 13'd1863; +parameter ap_ST_fsm_state1865 = 13'd1864; +parameter ap_ST_fsm_state1866 = 13'd1865; +parameter ap_ST_fsm_state1867 = 13'd1866; +parameter ap_ST_fsm_state1868 = 13'd1867; +parameter ap_ST_fsm_state1869 = 13'd1868; +parameter ap_ST_fsm_state1870 = 13'd1869; +parameter ap_ST_fsm_state1871 = 13'd1870; +parameter ap_ST_fsm_state1872 = 13'd1871; +parameter ap_ST_fsm_state1873 = 13'd1872; +parameter ap_ST_fsm_state1874 = 13'd1873; +parameter ap_ST_fsm_state1875 = 13'd1874; +parameter ap_ST_fsm_state1876 = 13'd1875; +parameter ap_ST_fsm_state1877 = 13'd1876; +parameter ap_ST_fsm_state1878 = 13'd1877; +parameter ap_ST_fsm_state1879 = 13'd1878; +parameter ap_ST_fsm_state1880 = 13'd1879; +parameter ap_ST_fsm_state1881 = 13'd1880; +parameter ap_ST_fsm_state1882 = 13'd1881; +parameter ap_ST_fsm_state1883 = 13'd1882; +parameter ap_ST_fsm_state1884 = 13'd1883; +parameter ap_ST_fsm_state1885 = 13'd1884; +parameter ap_ST_fsm_state1886 = 13'd1885; +parameter ap_ST_fsm_state1887 = 13'd1886; +parameter ap_ST_fsm_state1888 = 13'd1887; +parameter ap_ST_fsm_state1889 = 13'd1888; +parameter ap_ST_fsm_state1890 = 13'd1889; +parameter ap_ST_fsm_state1891 = 13'd1890; +parameter ap_ST_fsm_state1892 = 13'd1891; +parameter ap_ST_fsm_state1893 = 13'd1892; +parameter ap_ST_fsm_state1894 = 13'd1893; +parameter ap_ST_fsm_state1895 = 13'd1894; +parameter ap_ST_fsm_state1896 = 13'd1895; +parameter ap_ST_fsm_state1897 = 13'd1896; +parameter ap_ST_fsm_state1898 = 13'd1897; +parameter ap_ST_fsm_state1899 = 13'd1898; +parameter ap_ST_fsm_state1900 = 13'd1899; +parameter ap_ST_fsm_state1901 = 13'd1900; +parameter ap_ST_fsm_state1902 = 13'd1901; +parameter ap_ST_fsm_state1903 = 13'd1902; +parameter ap_ST_fsm_state1904 = 13'd1903; +parameter ap_ST_fsm_state1905 = 13'd1904; +parameter ap_ST_fsm_state1906 = 13'd1905; +parameter ap_ST_fsm_state1907 = 13'd1906; +parameter ap_ST_fsm_state1908 = 13'd1907; +parameter ap_ST_fsm_state1909 = 13'd1908; +parameter ap_ST_fsm_state1910 = 13'd1909; +parameter ap_ST_fsm_state1911 = 13'd1910; +parameter ap_ST_fsm_state1912 = 13'd1911; +parameter ap_ST_fsm_state1913 = 13'd1912; +parameter ap_ST_fsm_state1914 = 13'd1913; +parameter ap_ST_fsm_state1915 = 13'd1914; +parameter ap_ST_fsm_state1916 = 13'd1915; +parameter ap_ST_fsm_state1917 = 13'd1916; +parameter ap_ST_fsm_state1918 = 13'd1917; +parameter ap_ST_fsm_state1919 = 13'd1918; +parameter ap_ST_fsm_state1920 = 13'd1919; +parameter ap_ST_fsm_state1921 = 13'd1920; +parameter ap_ST_fsm_state1922 = 13'd1921; +parameter ap_ST_fsm_state1923 = 13'd1922; +parameter ap_ST_fsm_state1924 = 13'd1923; +parameter ap_ST_fsm_state1925 = 13'd1924; +parameter ap_ST_fsm_state1926 = 13'd1925; +parameter ap_ST_fsm_state1927 = 13'd1926; +parameter ap_ST_fsm_state1928 = 13'd1927; +parameter ap_ST_fsm_state1929 = 13'd1928; +parameter ap_ST_fsm_state1930 = 13'd1929; +parameter ap_ST_fsm_state1931 = 13'd1930; +parameter ap_ST_fsm_state1932 = 13'd1931; +parameter ap_ST_fsm_state1933 = 13'd1932; +parameter ap_ST_fsm_state1934 = 13'd1933; +parameter ap_ST_fsm_state1935 = 13'd1934; +parameter ap_ST_fsm_state1936 = 13'd1935; +parameter ap_ST_fsm_state1937 = 13'd1936; +parameter ap_ST_fsm_state1938 = 13'd1937; +parameter ap_ST_fsm_state1939 = 13'd1938; +parameter ap_ST_fsm_state1940 = 13'd1939; +parameter ap_ST_fsm_state1941 = 13'd1940; +parameter ap_ST_fsm_state1942 = 13'd1941; +parameter ap_ST_fsm_state1943 = 13'd1942; +parameter ap_ST_fsm_state1944 = 13'd1943; +parameter ap_ST_fsm_state1945 = 13'd1944; +parameter ap_ST_fsm_state1946 = 13'd1945; +parameter ap_ST_fsm_state1947 = 13'd1946; +parameter ap_ST_fsm_state1948 = 13'd1947; +parameter ap_ST_fsm_state1949 = 13'd1948; +parameter ap_ST_fsm_state1950 = 13'd1949; +parameter ap_ST_fsm_state1951 = 13'd1950; +parameter ap_ST_fsm_state1952 = 13'd1951; +parameter ap_ST_fsm_state1953 = 13'd1952; +parameter ap_ST_fsm_state1954 = 13'd1953; +parameter ap_ST_fsm_state1955 = 13'd1954; +parameter ap_ST_fsm_state1956 = 13'd1955; +parameter ap_ST_fsm_state1957 = 13'd1956; +parameter ap_ST_fsm_state1958 = 13'd1957; +parameter ap_ST_fsm_state1959 = 13'd1958; +parameter ap_ST_fsm_state1960 = 13'd1959; +parameter ap_ST_fsm_state1961 = 13'd1960; +parameter ap_ST_fsm_state1962 = 13'd1961; +parameter ap_ST_fsm_state1963 = 13'd1962; +parameter ap_ST_fsm_state1964 = 13'd1963; +parameter ap_ST_fsm_state1965 = 13'd1964; +parameter ap_ST_fsm_state1966 = 13'd1965; +parameter ap_ST_fsm_state1967 = 13'd1966; +parameter ap_ST_fsm_state1968 = 13'd1967; +parameter ap_ST_fsm_state1969 = 13'd1968; +parameter ap_ST_fsm_state1970 = 13'd1969; +parameter ap_ST_fsm_state1971 = 13'd1970; +parameter ap_ST_fsm_state1972 = 13'd1971; +parameter ap_ST_fsm_state1973 = 13'd1972; +parameter ap_ST_fsm_state1974 = 13'd1973; +parameter ap_ST_fsm_state1975 = 13'd1974; +parameter ap_ST_fsm_state1976 = 13'd1975; +parameter ap_ST_fsm_state1977 = 13'd1976; +parameter ap_ST_fsm_state1978 = 13'd1977; +parameter ap_ST_fsm_state1979 = 13'd1978; +parameter ap_ST_fsm_state1980 = 13'd1979; +parameter ap_ST_fsm_state1981 = 13'd1980; +parameter ap_ST_fsm_state1982 = 13'd1981; +parameter ap_ST_fsm_state1983 = 13'd1982; +parameter ap_ST_fsm_state1984 = 13'd1983; +parameter ap_ST_fsm_state1985 = 13'd1984; +parameter ap_ST_fsm_state1986 = 13'd1985; +parameter ap_ST_fsm_state1987 = 13'd1986; +parameter ap_ST_fsm_state1988 = 13'd1987; +parameter ap_ST_fsm_state1989 = 13'd1988; +parameter ap_ST_fsm_state1990 = 13'd1989; +parameter ap_ST_fsm_state1991 = 13'd1990; +parameter ap_ST_fsm_state1992 = 13'd1991; +parameter ap_ST_fsm_state1993 = 13'd1992; +parameter ap_ST_fsm_state1994 = 13'd1993; +parameter ap_ST_fsm_state1995 = 13'd1994; +parameter ap_ST_fsm_state1996 = 13'd1995; +parameter ap_ST_fsm_state1997 = 13'd1996; +parameter ap_ST_fsm_state1998 = 13'd1997; +parameter ap_ST_fsm_state1999 = 13'd1998; +parameter ap_ST_fsm_state2000 = 13'd1999; +parameter ap_ST_fsm_state2001 = 13'd2000; +parameter ap_ST_fsm_state2002 = 13'd2001; +parameter ap_ST_fsm_state2003 = 13'd2002; +parameter ap_ST_fsm_state2004 = 13'd2003; +parameter ap_ST_fsm_state2005 = 13'd2004; +parameter ap_ST_fsm_state2006 = 13'd2005; +parameter ap_ST_fsm_state2007 = 13'd2006; +parameter ap_ST_fsm_state2008 = 13'd2007; +parameter ap_ST_fsm_state2009 = 13'd2008; +parameter ap_ST_fsm_state2010 = 13'd2009; +parameter ap_ST_fsm_state2011 = 13'd2010; +parameter ap_ST_fsm_state2012 = 13'd2011; +parameter ap_ST_fsm_state2013 = 13'd2012; +parameter ap_ST_fsm_state2014 = 13'd2013; +parameter ap_ST_fsm_state2015 = 13'd2014; +parameter ap_ST_fsm_state2016 = 13'd2015; +parameter ap_ST_fsm_state2017 = 13'd2016; +parameter ap_ST_fsm_state2018 = 13'd2017; +parameter ap_ST_fsm_state2019 = 13'd2018; +parameter ap_ST_fsm_state2020 = 13'd2019; +parameter ap_ST_fsm_state2021 = 13'd2020; +parameter ap_ST_fsm_state2022 = 13'd2021; +parameter ap_ST_fsm_state2023 = 13'd2022; +parameter ap_ST_fsm_state2024 = 13'd2023; +parameter ap_ST_fsm_state2025 = 13'd2024; +parameter ap_ST_fsm_state2026 = 13'd2025; +parameter ap_ST_fsm_state2027 = 13'd2026; +parameter ap_ST_fsm_state2028 = 13'd2027; +parameter ap_ST_fsm_state2029 = 13'd2028; +parameter ap_ST_fsm_state2030 = 13'd2029; +parameter ap_ST_fsm_state2031 = 13'd2030; +parameter ap_ST_fsm_state2032 = 13'd2031; +parameter ap_ST_fsm_state2033 = 13'd2032; +parameter ap_ST_fsm_state2034 = 13'd2033; +parameter ap_ST_fsm_state2035 = 13'd2034; +parameter ap_ST_fsm_state2036 = 13'd2035; +parameter ap_ST_fsm_state2037 = 13'd2036; +parameter ap_ST_fsm_state2038 = 13'd2037; +parameter ap_ST_fsm_state2039 = 13'd2038; +parameter ap_ST_fsm_state2040 = 13'd2039; +parameter ap_ST_fsm_state2041 = 13'd2040; +parameter ap_ST_fsm_state2042 = 13'd2041; +parameter ap_ST_fsm_state2043 = 13'd2042; +parameter ap_ST_fsm_state2044 = 13'd2043; +parameter ap_ST_fsm_state2045 = 13'd2044; +parameter ap_ST_fsm_state2046 = 13'd2045; +parameter ap_ST_fsm_state2047 = 13'd2046; +parameter ap_ST_fsm_state2048 = 13'd2047; +parameter ap_ST_fsm_state2049 = 13'd2048; +parameter ap_ST_fsm_state2050 = 13'd2049; +parameter ap_ST_fsm_state2051 = 13'd2050; +parameter ap_ST_fsm_state2052 = 13'd2051; +parameter ap_ST_fsm_state2053 = 13'd2052; +parameter ap_ST_fsm_state2054 = 13'd2053; +parameter ap_ST_fsm_state2055 = 13'd2054; +parameter ap_ST_fsm_state2056 = 13'd2055; +parameter ap_ST_fsm_state2057 = 13'd2056; +parameter ap_ST_fsm_state2058 = 13'd2057; +parameter ap_ST_fsm_state2059 = 13'd2058; +parameter ap_ST_fsm_state2060 = 13'd2059; +parameter ap_ST_fsm_state2061 = 13'd2060; +parameter ap_ST_fsm_state2062 = 13'd2061; +parameter ap_ST_fsm_state2063 = 13'd2062; +parameter ap_ST_fsm_state2064 = 13'd2063; +parameter ap_ST_fsm_state2065 = 13'd2064; +parameter ap_ST_fsm_state2066 = 13'd2065; +parameter ap_ST_fsm_state2067 = 13'd2066; +parameter ap_ST_fsm_state2068 = 13'd2067; +parameter ap_ST_fsm_state2069 = 13'd2068; +parameter ap_ST_fsm_state2070 = 13'd2069; +parameter ap_ST_fsm_state2071 = 13'd2070; +parameter ap_ST_fsm_state2072 = 13'd2071; +parameter ap_ST_fsm_state2073 = 13'd2072; +parameter ap_ST_fsm_state2074 = 13'd2073; +parameter ap_ST_fsm_state2075 = 13'd2074; +parameter ap_ST_fsm_state2076 = 13'd2075; +parameter ap_ST_fsm_state2077 = 13'd2076; +parameter ap_ST_fsm_state2078 = 13'd2077; +parameter ap_ST_fsm_state2079 = 13'd2078; +parameter ap_ST_fsm_state2080 = 13'd2079; +parameter ap_ST_fsm_state2081 = 13'd2080; +parameter ap_ST_fsm_state2082 = 13'd2081; +parameter ap_ST_fsm_state2083 = 13'd2082; +parameter ap_ST_fsm_state2084 = 13'd2083; +parameter ap_ST_fsm_state2085 = 13'd2084; +parameter ap_ST_fsm_state2086 = 13'd2085; +parameter ap_ST_fsm_state2087 = 13'd2086; +parameter ap_ST_fsm_state2088 = 13'd2087; +parameter ap_ST_fsm_state2089 = 13'd2088; +parameter ap_ST_fsm_state2090 = 13'd2089; +parameter ap_ST_fsm_state2091 = 13'd2090; +parameter ap_ST_fsm_state2092 = 13'd2091; +parameter ap_ST_fsm_state2093 = 13'd2092; +parameter ap_ST_fsm_state2094 = 13'd2093; +parameter ap_ST_fsm_state2095 = 13'd2094; +parameter ap_ST_fsm_state2096 = 13'd2095; +parameter ap_ST_fsm_state2097 = 13'd2096; +parameter ap_ST_fsm_state2098 = 13'd2097; +parameter ap_ST_fsm_state2099 = 13'd2098; +parameter ap_ST_fsm_state2100 = 13'd2099; +parameter ap_ST_fsm_state2101 = 13'd2100; +parameter ap_ST_fsm_state2102 = 13'd2101; +parameter ap_ST_fsm_state2103 = 13'd2102; +parameter ap_ST_fsm_state2104 = 13'd2103; +parameter ap_ST_fsm_state2105 = 13'd2104; +parameter ap_ST_fsm_state2106 = 13'd2105; +parameter ap_ST_fsm_state2107 = 13'd2106; +parameter ap_ST_fsm_state2108 = 13'd2107; +parameter ap_ST_fsm_state2109 = 13'd2108; +parameter ap_ST_fsm_state2110 = 13'd2109; +parameter ap_ST_fsm_state2111 = 13'd2110; +parameter ap_ST_fsm_state2112 = 13'd2111; +parameter ap_ST_fsm_state2113 = 13'd2112; +parameter ap_ST_fsm_state2114 = 13'd2113; +parameter ap_ST_fsm_state2115 = 13'd2114; +parameter ap_ST_fsm_state2116 = 13'd2115; +parameter ap_ST_fsm_state2117 = 13'd2116; +parameter ap_ST_fsm_state2118 = 13'd2117; +parameter ap_ST_fsm_state2119 = 13'd2118; +parameter ap_ST_fsm_state2120 = 13'd2119; +parameter ap_ST_fsm_state2121 = 13'd2120; +parameter ap_ST_fsm_state2122 = 13'd2121; +parameter ap_ST_fsm_state2123 = 13'd2122; +parameter ap_ST_fsm_state2124 = 13'd2123; +parameter ap_ST_fsm_state2125 = 13'd2124; +parameter ap_ST_fsm_state2126 = 13'd2125; +parameter ap_ST_fsm_state2127 = 13'd2126; +parameter ap_ST_fsm_state2128 = 13'd2127; +parameter ap_ST_fsm_state2129 = 13'd2128; +parameter ap_ST_fsm_state2130 = 13'd2129; +parameter ap_ST_fsm_state2131 = 13'd2130; +parameter ap_ST_fsm_state2132 = 13'd2131; +parameter ap_ST_fsm_state2133 = 13'd2132; +parameter ap_ST_fsm_state2134 = 13'd2133; +parameter ap_ST_fsm_state2135 = 13'd2134; +parameter ap_ST_fsm_state2136 = 13'd2135; +parameter ap_ST_fsm_state2137 = 13'd2136; +parameter ap_ST_fsm_state2138 = 13'd2137; +parameter ap_ST_fsm_state2139 = 13'd2138; +parameter ap_ST_fsm_state2140 = 13'd2139; +parameter ap_ST_fsm_state2141 = 13'd2140; +parameter ap_ST_fsm_state2142 = 13'd2141; +parameter ap_ST_fsm_state2143 = 13'd2142; +parameter ap_ST_fsm_state2144 = 13'd2143; +parameter ap_ST_fsm_state2145 = 13'd2144; +parameter ap_ST_fsm_state2146 = 13'd2145; +parameter ap_ST_fsm_state2147 = 13'd2146; +parameter ap_ST_fsm_state2148 = 13'd2147; +parameter ap_ST_fsm_state2149 = 13'd2148; +parameter ap_ST_fsm_state2150 = 13'd2149; +parameter ap_ST_fsm_state2151 = 13'd2150; +parameter ap_ST_fsm_state2152 = 13'd2151; +parameter ap_ST_fsm_state2153 = 13'd2152; +parameter ap_ST_fsm_state2154 = 13'd2153; +parameter ap_ST_fsm_state2155 = 13'd2154; +parameter ap_ST_fsm_state2156 = 13'd2155; +parameter ap_ST_fsm_state2157 = 13'd2156; +parameter ap_ST_fsm_state2158 = 13'd2157; +parameter ap_ST_fsm_state2159 = 13'd2158; +parameter ap_ST_fsm_state2160 = 13'd2159; +parameter ap_ST_fsm_state2161 = 13'd2160; +parameter ap_ST_fsm_state2162 = 13'd2161; +parameter ap_ST_fsm_state2163 = 13'd2162; +parameter ap_ST_fsm_state2164 = 13'd2163; +parameter ap_ST_fsm_state2165 = 13'd2164; +parameter ap_ST_fsm_state2166 = 13'd2165; +parameter ap_ST_fsm_state2167 = 13'd2166; +parameter ap_ST_fsm_state2168 = 13'd2167; +parameter ap_ST_fsm_state2169 = 13'd2168; +parameter ap_ST_fsm_state2170 = 13'd2169; +parameter ap_ST_fsm_state2171 = 13'd2170; +parameter ap_ST_fsm_state2172 = 13'd2171; +parameter ap_ST_fsm_state2173 = 13'd2172; +parameter ap_ST_fsm_state2174 = 13'd2173; +parameter ap_ST_fsm_state2175 = 13'd2174; +parameter ap_ST_fsm_state2176 = 13'd2175; +parameter ap_ST_fsm_state2177 = 13'd2176; +parameter ap_ST_fsm_state2178 = 13'd2177; +parameter ap_ST_fsm_state2179 = 13'd2178; +parameter ap_ST_fsm_state2180 = 13'd2179; +parameter ap_ST_fsm_state2181 = 13'd2180; +parameter ap_ST_fsm_state2182 = 13'd2181; +parameter ap_ST_fsm_state2183 = 13'd2182; +parameter ap_ST_fsm_state2184 = 13'd2183; +parameter ap_ST_fsm_state2185 = 13'd2184; +parameter ap_ST_fsm_state2186 = 13'd2185; +parameter ap_ST_fsm_state2187 = 13'd2186; +parameter ap_ST_fsm_state2188 = 13'd2187; +parameter ap_ST_fsm_state2189 = 13'd2188; +parameter ap_ST_fsm_state2190 = 13'd2189; +parameter ap_ST_fsm_state2191 = 13'd2190; +parameter ap_ST_fsm_state2192 = 13'd2191; +parameter ap_ST_fsm_state2193 = 13'd2192; +parameter ap_ST_fsm_state2194 = 13'd2193; +parameter ap_ST_fsm_state2195 = 13'd2194; +parameter ap_ST_fsm_state2196 = 13'd2195; +parameter ap_ST_fsm_state2197 = 13'd2196; +parameter ap_ST_fsm_state2198 = 13'd2197; +parameter ap_ST_fsm_state2199 = 13'd2198; +parameter ap_ST_fsm_state2200 = 13'd2199; +parameter ap_ST_fsm_state2201 = 13'd2200; +parameter ap_ST_fsm_state2202 = 13'd2201; +parameter ap_ST_fsm_state2203 = 13'd2202; +parameter ap_ST_fsm_state2204 = 13'd2203; +parameter ap_ST_fsm_state2205 = 13'd2204; +parameter ap_ST_fsm_state2206 = 13'd2205; +parameter ap_ST_fsm_state2207 = 13'd2206; +parameter ap_ST_fsm_state2208 = 13'd2207; +parameter ap_ST_fsm_state2209 = 13'd2208; +parameter ap_ST_fsm_state2210 = 13'd2209; +parameter ap_ST_fsm_state2211 = 13'd2210; +parameter ap_ST_fsm_state2212 = 13'd2211; +parameter ap_ST_fsm_state2213 = 13'd2212; +parameter ap_ST_fsm_state2214 = 13'd2213; +parameter ap_ST_fsm_state2215 = 13'd2214; +parameter ap_ST_fsm_state2216 = 13'd2215; +parameter ap_ST_fsm_state2217 = 13'd2216; +parameter ap_ST_fsm_state2218 = 13'd2217; +parameter ap_ST_fsm_state2219 = 13'd2218; +parameter ap_ST_fsm_state2220 = 13'd2219; +parameter ap_ST_fsm_state2221 = 13'd2220; +parameter ap_ST_fsm_state2222 = 13'd2221; +parameter ap_ST_fsm_state2223 = 13'd2222; +parameter ap_ST_fsm_state2224 = 13'd2223; +parameter ap_ST_fsm_state2225 = 13'd2224; +parameter ap_ST_fsm_state2226 = 13'd2225; +parameter ap_ST_fsm_state2227 = 13'd2226; +parameter ap_ST_fsm_state2228 = 13'd2227; +parameter ap_ST_fsm_state2229 = 13'd2228; +parameter ap_ST_fsm_state2230 = 13'd2229; +parameter ap_ST_fsm_state2231 = 13'd2230; +parameter ap_ST_fsm_state2232 = 13'd2231; +parameter ap_ST_fsm_state2233 = 13'd2232; +parameter ap_ST_fsm_state2234 = 13'd2233; +parameter ap_ST_fsm_state2235 = 13'd2234; +parameter ap_ST_fsm_state2236 = 13'd2235; +parameter ap_ST_fsm_state2237 = 13'd2236; +parameter ap_ST_fsm_state2238 = 13'd2237; +parameter ap_ST_fsm_state2239 = 13'd2238; +parameter ap_ST_fsm_state2240 = 13'd2239; +parameter ap_ST_fsm_state2241 = 13'd2240; +parameter ap_ST_fsm_state2242 = 13'd2241; +parameter ap_ST_fsm_state2243 = 13'd2242; +parameter ap_ST_fsm_state2244 = 13'd2243; +parameter ap_ST_fsm_state2245 = 13'd2244; +parameter ap_ST_fsm_state2246 = 13'd2245; +parameter ap_ST_fsm_state2247 = 13'd2246; +parameter ap_ST_fsm_state2248 = 13'd2247; +parameter ap_ST_fsm_state2249 = 13'd2248; +parameter ap_ST_fsm_state2250 = 13'd2249; +parameter ap_ST_fsm_state2251 = 13'd2250; +parameter ap_ST_fsm_state2252 = 13'd2251; +parameter ap_ST_fsm_state2253 = 13'd2252; +parameter ap_ST_fsm_state2254 = 13'd2253; +parameter ap_ST_fsm_state2255 = 13'd2254; +parameter ap_ST_fsm_state2256 = 13'd2255; +parameter ap_ST_fsm_state2257 = 13'd2256; +parameter ap_ST_fsm_state2258 = 13'd2257; +parameter ap_ST_fsm_state2259 = 13'd2258; +parameter ap_ST_fsm_state2260 = 13'd2259; +parameter ap_ST_fsm_state2261 = 13'd2260; +parameter ap_ST_fsm_state2262 = 13'd2261; +parameter ap_ST_fsm_state2263 = 13'd2262; +parameter ap_ST_fsm_state2264 = 13'd2263; +parameter ap_ST_fsm_state2265 = 13'd2264; +parameter ap_ST_fsm_state2266 = 13'd2265; +parameter ap_ST_fsm_state2267 = 13'd2266; +parameter ap_ST_fsm_state2268 = 13'd2267; +parameter ap_ST_fsm_state2269 = 13'd2268; +parameter ap_ST_fsm_state2270 = 13'd2269; +parameter ap_ST_fsm_state2271 = 13'd2270; +parameter ap_ST_fsm_state2272 = 13'd2271; +parameter ap_ST_fsm_state2273 = 13'd2272; +parameter ap_ST_fsm_state2274 = 13'd2273; +parameter ap_ST_fsm_state2275 = 13'd2274; +parameter ap_ST_fsm_state2276 = 13'd2275; +parameter ap_ST_fsm_state2277 = 13'd2276; +parameter ap_ST_fsm_state2278 = 13'd2277; +parameter ap_ST_fsm_state2279 = 13'd2278; +parameter ap_ST_fsm_state2280 = 13'd2279; +parameter ap_ST_fsm_state2281 = 13'd2280; +parameter ap_ST_fsm_state2282 = 13'd2281; +parameter ap_ST_fsm_state2283 = 13'd2282; +parameter ap_ST_fsm_state2284 = 13'd2283; +parameter ap_ST_fsm_state2285 = 13'd2284; +parameter ap_ST_fsm_state2286 = 13'd2285; +parameter ap_ST_fsm_state2287 = 13'd2286; +parameter ap_ST_fsm_state2288 = 13'd2287; +parameter ap_ST_fsm_state2289 = 13'd2288; +parameter ap_ST_fsm_state2290 = 13'd2289; +parameter ap_ST_fsm_state2291 = 13'd2290; +parameter ap_ST_fsm_state2292 = 13'd2291; +parameter ap_ST_fsm_state2293 = 13'd2292; +parameter ap_ST_fsm_state2294 = 13'd2293; +parameter ap_ST_fsm_state2295 = 13'd2294; +parameter ap_ST_fsm_state2296 = 13'd2295; +parameter ap_ST_fsm_state2297 = 13'd2296; +parameter ap_ST_fsm_state2298 = 13'd2297; +parameter ap_ST_fsm_state2299 = 13'd2298; +parameter ap_ST_fsm_state2300 = 13'd2299; +parameter ap_ST_fsm_state2301 = 13'd2300; +parameter ap_ST_fsm_state2302 = 13'd2301; +parameter ap_ST_fsm_state2303 = 13'd2302; +parameter ap_ST_fsm_state2304 = 13'd2303; +parameter ap_ST_fsm_state2305 = 13'd2304; +parameter ap_ST_fsm_state2306 = 13'd2305; +parameter ap_ST_fsm_state2307 = 13'd2306; +parameter ap_ST_fsm_state2308 = 13'd2307; +parameter ap_ST_fsm_state2309 = 13'd2308; +parameter ap_ST_fsm_state2310 = 13'd2309; +parameter ap_ST_fsm_state2311 = 13'd2310; +parameter ap_ST_fsm_state2312 = 13'd2311; +parameter ap_ST_fsm_state2313 = 13'd2312; +parameter ap_ST_fsm_state2314 = 13'd2313; +parameter ap_ST_fsm_state2315 = 13'd2314; +parameter ap_ST_fsm_state2316 = 13'd2315; +parameter ap_ST_fsm_state2317 = 13'd2316; +parameter ap_ST_fsm_state2318 = 13'd2317; +parameter ap_ST_fsm_state2319 = 13'd2318; +parameter ap_ST_fsm_state2320 = 13'd2319; +parameter ap_ST_fsm_state2321 = 13'd2320; +parameter ap_ST_fsm_state2322 = 13'd2321; +parameter ap_ST_fsm_state2323 = 13'd2322; +parameter ap_ST_fsm_state2324 = 13'd2323; +parameter ap_ST_fsm_state2325 = 13'd2324; +parameter ap_ST_fsm_state2326 = 13'd2325; +parameter ap_ST_fsm_state2327 = 13'd2326; +parameter ap_ST_fsm_state2328 = 13'd2327; +parameter ap_ST_fsm_state2329 = 13'd2328; +parameter ap_ST_fsm_state2330 = 13'd2329; +parameter ap_ST_fsm_state2331 = 13'd2330; +parameter ap_ST_fsm_state2332 = 13'd2331; +parameter ap_ST_fsm_state2333 = 13'd2332; +parameter ap_ST_fsm_state2334 = 13'd2333; +parameter ap_ST_fsm_state2335 = 13'd2334; +parameter ap_ST_fsm_state2336 = 13'd2335; +parameter ap_ST_fsm_state2337 = 13'd2336; +parameter ap_ST_fsm_state2338 = 13'd2337; +parameter ap_ST_fsm_state2339 = 13'd2338; +parameter ap_ST_fsm_state2340 = 13'd2339; +parameter ap_ST_fsm_state2341 = 13'd2340; +parameter ap_ST_fsm_state2342 = 13'd2341; +parameter ap_ST_fsm_state2343 = 13'd2342; +parameter ap_ST_fsm_state2344 = 13'd2343; +parameter ap_ST_fsm_state2345 = 13'd2344; +parameter ap_ST_fsm_state2346 = 13'd2345; +parameter ap_ST_fsm_state2347 = 13'd2346; +parameter ap_ST_fsm_state2348 = 13'd2347; +parameter ap_ST_fsm_state2349 = 13'd2348; +parameter ap_ST_fsm_state2350 = 13'd2349; +parameter ap_ST_fsm_state2351 = 13'd2350; +parameter ap_ST_fsm_state2352 = 13'd2351; +parameter ap_ST_fsm_state2353 = 13'd2352; +parameter ap_ST_fsm_state2354 = 13'd2353; +parameter ap_ST_fsm_state2355 = 13'd2354; +parameter ap_ST_fsm_state2356 = 13'd2355; +parameter ap_ST_fsm_state2357 = 13'd2356; +parameter ap_ST_fsm_state2358 = 13'd2357; +parameter ap_ST_fsm_state2359 = 13'd2358; +parameter ap_ST_fsm_state2360 = 13'd2359; +parameter ap_ST_fsm_state2361 = 13'd2360; +parameter ap_ST_fsm_state2362 = 13'd2361; +parameter ap_ST_fsm_state2363 = 13'd2362; +parameter ap_ST_fsm_state2364 = 13'd2363; +parameter ap_ST_fsm_state2365 = 13'd2364; +parameter ap_ST_fsm_state2366 = 13'd2365; +parameter ap_ST_fsm_state2367 = 13'd2366; +parameter ap_ST_fsm_state2368 = 13'd2367; +parameter ap_ST_fsm_state2369 = 13'd2368; +parameter ap_ST_fsm_state2370 = 13'd2369; +parameter ap_ST_fsm_state2371 = 13'd2370; +parameter ap_ST_fsm_state2372 = 13'd2371; +parameter ap_ST_fsm_state2373 = 13'd2372; +parameter ap_ST_fsm_state2374 = 13'd2373; +parameter ap_ST_fsm_state2375 = 13'd2374; +parameter ap_ST_fsm_state2376 = 13'd2375; +parameter ap_ST_fsm_state2377 = 13'd2376; +parameter ap_ST_fsm_state2378 = 13'd2377; +parameter ap_ST_fsm_state2379 = 13'd2378; +parameter ap_ST_fsm_state2380 = 13'd2379; +parameter ap_ST_fsm_state2381 = 13'd2380; +parameter ap_ST_fsm_state2382 = 13'd2381; +parameter ap_ST_fsm_state2383 = 13'd2382; +parameter ap_ST_fsm_state2384 = 13'd2383; +parameter ap_ST_fsm_state2385 = 13'd2384; +parameter ap_ST_fsm_state2386 = 13'd2385; +parameter ap_ST_fsm_state2387 = 13'd2386; +parameter ap_ST_fsm_state2388 = 13'd2387; +parameter ap_ST_fsm_state2389 = 13'd2388; +parameter ap_ST_fsm_state2390 = 13'd2389; +parameter ap_ST_fsm_state2391 = 13'd2390; +parameter ap_ST_fsm_state2392 = 13'd2391; +parameter ap_ST_fsm_state2393 = 13'd2392; +parameter ap_ST_fsm_state2394 = 13'd2393; +parameter ap_ST_fsm_state2395 = 13'd2394; +parameter ap_ST_fsm_state2396 = 13'd2395; +parameter ap_ST_fsm_state2397 = 13'd2396; +parameter ap_ST_fsm_state2398 = 13'd2397; +parameter ap_ST_fsm_state2399 = 13'd2398; +parameter ap_ST_fsm_state2400 = 13'd2399; +parameter ap_ST_fsm_state2401 = 13'd2400; +parameter ap_ST_fsm_state2402 = 13'd2401; +parameter ap_ST_fsm_state2403 = 13'd2402; +parameter ap_ST_fsm_state2404 = 13'd2403; +parameter ap_ST_fsm_state2405 = 13'd2404; +parameter ap_ST_fsm_state2406 = 13'd2405; +parameter ap_ST_fsm_state2407 = 13'd2406; +parameter ap_ST_fsm_state2408 = 13'd2407; +parameter ap_ST_fsm_state2409 = 13'd2408; +parameter ap_ST_fsm_state2410 = 13'd2409; +parameter ap_ST_fsm_state2411 = 13'd2410; +parameter ap_ST_fsm_state2412 = 13'd2411; +parameter ap_ST_fsm_state2413 = 13'd2412; +parameter ap_ST_fsm_state2414 = 13'd2413; +parameter ap_ST_fsm_state2415 = 13'd2414; +parameter ap_ST_fsm_state2416 = 13'd2415; +parameter ap_ST_fsm_state2417 = 13'd2416; +parameter ap_ST_fsm_state2418 = 13'd2417; +parameter ap_ST_fsm_state2419 = 13'd2418; +parameter ap_ST_fsm_state2420 = 13'd2419; +parameter ap_ST_fsm_state2421 = 13'd2420; +parameter ap_ST_fsm_state2422 = 13'd2421; +parameter ap_ST_fsm_state2423 = 13'd2422; +parameter ap_ST_fsm_state2424 = 13'd2423; +parameter ap_ST_fsm_state2425 = 13'd2424; +parameter ap_ST_fsm_state2426 = 13'd2425; +parameter ap_ST_fsm_state2427 = 13'd2426; +parameter ap_ST_fsm_state2428 = 13'd2427; +parameter ap_ST_fsm_state2429 = 13'd2428; +parameter ap_ST_fsm_state2430 = 13'd2429; +parameter ap_ST_fsm_state2431 = 13'd2430; +parameter ap_ST_fsm_state2432 = 13'd2431; +parameter ap_ST_fsm_state2433 = 13'd2432; +parameter ap_ST_fsm_state2434 = 13'd2433; +parameter ap_ST_fsm_state2435 = 13'd2434; +parameter ap_ST_fsm_state2436 = 13'd2435; +parameter ap_ST_fsm_state2437 = 13'd2436; +parameter ap_ST_fsm_state2438 = 13'd2437; +parameter ap_ST_fsm_state2439 = 13'd2438; +parameter ap_ST_fsm_state2440 = 13'd2439; +parameter ap_ST_fsm_state2441 = 13'd2440; +parameter ap_ST_fsm_state2442 = 13'd2441; +parameter ap_ST_fsm_state2443 = 13'd2442; +parameter ap_ST_fsm_state2444 = 13'd2443; +parameter ap_ST_fsm_state2445 = 13'd2444; +parameter ap_ST_fsm_state2446 = 13'd2445; +parameter ap_ST_fsm_state2447 = 13'd2446; +parameter ap_ST_fsm_state2448 = 13'd2447; +parameter ap_ST_fsm_state2449 = 13'd2448; +parameter ap_ST_fsm_state2450 = 13'd2449; +parameter ap_ST_fsm_state2451 = 13'd2450; +parameter ap_ST_fsm_state2452 = 13'd2451; +parameter ap_ST_fsm_state2453 = 13'd2452; +parameter ap_ST_fsm_state2454 = 13'd2453; +parameter ap_ST_fsm_state2455 = 13'd2454; +parameter ap_ST_fsm_state2456 = 13'd2455; +parameter ap_ST_fsm_state2457 = 13'd2456; +parameter ap_ST_fsm_state2458 = 13'd2457; +parameter ap_ST_fsm_state2459 = 13'd2458; +parameter ap_ST_fsm_state2460 = 13'd2459; +parameter ap_ST_fsm_state2461 = 13'd2460; +parameter ap_ST_fsm_state2462 = 13'd2461; +parameter ap_ST_fsm_state2463 = 13'd2462; +parameter ap_ST_fsm_state2464 = 13'd2463; +parameter ap_ST_fsm_state2465 = 13'd2464; +parameter ap_ST_fsm_state2466 = 13'd2465; +parameter ap_ST_fsm_state2467 = 13'd2466; +parameter ap_ST_fsm_state2468 = 13'd2467; +parameter ap_ST_fsm_state2469 = 13'd2468; +parameter ap_ST_fsm_state2470 = 13'd2469; +parameter ap_ST_fsm_state2471 = 13'd2470; +parameter ap_ST_fsm_state2472 = 13'd2471; +parameter ap_ST_fsm_state2473 = 13'd2472; +parameter ap_ST_fsm_state2474 = 13'd2473; +parameter ap_ST_fsm_state2475 = 13'd2474; +parameter ap_ST_fsm_state2476 = 13'd2475; +parameter ap_ST_fsm_state2477 = 13'd2476; +parameter ap_ST_fsm_state2478 = 13'd2477; +parameter ap_ST_fsm_state2479 = 13'd2478; +parameter ap_ST_fsm_state2480 = 13'd2479; +parameter ap_ST_fsm_state2481 = 13'd2480; +parameter ap_ST_fsm_state2482 = 13'd2481; +parameter ap_ST_fsm_state2483 = 13'd2482; +parameter ap_ST_fsm_state2484 = 13'd2483; +parameter ap_ST_fsm_state2485 = 13'd2484; +parameter ap_ST_fsm_state2486 = 13'd2485; +parameter ap_ST_fsm_state2487 = 13'd2486; +parameter ap_ST_fsm_state2488 = 13'd2487; +parameter ap_ST_fsm_state2489 = 13'd2488; +parameter ap_ST_fsm_state2490 = 13'd2489; +parameter ap_ST_fsm_state2491 = 13'd2490; +parameter ap_ST_fsm_state2492 = 13'd2491; +parameter ap_ST_fsm_state2493 = 13'd2492; +parameter ap_ST_fsm_state2494 = 13'd2493; +parameter ap_ST_fsm_state2495 = 13'd2494; +parameter ap_ST_fsm_state2496 = 13'd2495; +parameter ap_ST_fsm_state2497 = 13'd2496; +parameter ap_ST_fsm_state2498 = 13'd2497; +parameter ap_ST_fsm_state2499 = 13'd2498; +parameter ap_ST_fsm_state2500 = 13'd2499; +parameter ap_ST_fsm_state2501 = 13'd2500; +parameter ap_ST_fsm_state2502 = 13'd2501; +parameter ap_ST_fsm_state2503 = 13'd2502; +parameter ap_ST_fsm_state2504 = 13'd2503; +parameter ap_ST_fsm_state2505 = 13'd2504; +parameter ap_ST_fsm_state2506 = 13'd2505; +parameter ap_ST_fsm_state2507 = 13'd2506; +parameter ap_ST_fsm_state2508 = 13'd2507; +parameter ap_ST_fsm_state2509 = 13'd2508; +parameter ap_ST_fsm_state2510 = 13'd2509; +parameter ap_ST_fsm_state2511 = 13'd2510; +parameter ap_ST_fsm_state2512 = 13'd2511; +parameter ap_ST_fsm_state2513 = 13'd2512; +parameter ap_ST_fsm_state2514 = 13'd2513; +parameter ap_ST_fsm_state2515 = 13'd2514; +parameter ap_ST_fsm_state2516 = 13'd2515; +parameter ap_ST_fsm_state2517 = 13'd2516; +parameter ap_ST_fsm_state2518 = 13'd2517; +parameter ap_ST_fsm_state2519 = 13'd2518; +parameter ap_ST_fsm_state2520 = 13'd2519; +parameter ap_ST_fsm_state2521 = 13'd2520; +parameter ap_ST_fsm_state2522 = 13'd2521; +parameter ap_ST_fsm_state2523 = 13'd2522; +parameter ap_ST_fsm_state2524 = 13'd2523; +parameter ap_ST_fsm_state2525 = 13'd2524; +parameter ap_ST_fsm_state2526 = 13'd2525; +parameter ap_ST_fsm_state2527 = 13'd2526; +parameter ap_ST_fsm_state2528 = 13'd2527; +parameter ap_ST_fsm_state2529 = 13'd2528; +parameter ap_ST_fsm_state2530 = 13'd2529; +parameter ap_ST_fsm_state2531 = 13'd2530; +parameter ap_ST_fsm_state2532 = 13'd2531; +parameter ap_ST_fsm_state2533 = 13'd2532; +parameter ap_ST_fsm_state2534 = 13'd2533; +parameter ap_ST_fsm_state2535 = 13'd2534; +parameter ap_ST_fsm_state2536 = 13'd2535; +parameter ap_ST_fsm_state2537 = 13'd2536; +parameter ap_ST_fsm_state2538 = 13'd2537; +parameter ap_ST_fsm_state2539 = 13'd2538; +parameter ap_ST_fsm_state2540 = 13'd2539; +parameter ap_ST_fsm_state2541 = 13'd2540; +parameter ap_ST_fsm_state2542 = 13'd2541; +parameter ap_ST_fsm_state2543 = 13'd2542; +parameter ap_ST_fsm_state2544 = 13'd2543; +parameter ap_ST_fsm_state2545 = 13'd2544; +parameter ap_ST_fsm_state2546 = 13'd2545; +parameter ap_ST_fsm_state2547 = 13'd2546; +parameter ap_ST_fsm_state2548 = 13'd2547; +parameter ap_ST_fsm_state2549 = 13'd2548; +parameter ap_ST_fsm_state2550 = 13'd2549; +parameter ap_ST_fsm_state2551 = 13'd2550; +parameter ap_ST_fsm_state2552 = 13'd2551; +parameter ap_ST_fsm_state2553 = 13'd2552; +parameter ap_ST_fsm_state2554 = 13'd2553; +parameter ap_ST_fsm_state2555 = 13'd2554; +parameter ap_ST_fsm_state2556 = 13'd2555; +parameter ap_ST_fsm_state2557 = 13'd2556; +parameter ap_ST_fsm_state2558 = 13'd2557; +parameter ap_ST_fsm_state2559 = 13'd2558; +parameter ap_ST_fsm_state2560 = 13'd2559; +parameter ap_ST_fsm_state2561 = 13'd2560; +parameter ap_ST_fsm_state2562 = 13'd2561; +parameter ap_ST_fsm_state2563 = 13'd2562; +parameter ap_ST_fsm_state2564 = 13'd2563; +parameter ap_ST_fsm_state2565 = 13'd2564; +parameter ap_ST_fsm_state2566 = 13'd2565; +parameter ap_ST_fsm_state2567 = 13'd2566; +parameter ap_ST_fsm_state2568 = 13'd2567; +parameter ap_ST_fsm_state2569 = 13'd2568; +parameter ap_ST_fsm_state2570 = 13'd2569; +parameter ap_ST_fsm_state2571 = 13'd2570; +parameter ap_ST_fsm_state2572 = 13'd2571; +parameter ap_ST_fsm_state2573 = 13'd2572; +parameter ap_ST_fsm_state2574 = 13'd2573; +parameter ap_ST_fsm_state2575 = 13'd2574; +parameter ap_ST_fsm_state2576 = 13'd2575; +parameter ap_ST_fsm_state2577 = 13'd2576; +parameter ap_ST_fsm_state2578 = 13'd2577; +parameter ap_ST_fsm_state2579 = 13'd2578; +parameter ap_ST_fsm_state2580 = 13'd2579; +parameter ap_ST_fsm_state2581 = 13'd2580; +parameter ap_ST_fsm_state2582 = 13'd2581; +parameter ap_ST_fsm_state2583 = 13'd2582; +parameter ap_ST_fsm_state2584 = 13'd2583; +parameter ap_ST_fsm_state2585 = 13'd2584; +parameter ap_ST_fsm_state2586 = 13'd2585; +parameter ap_ST_fsm_state2587 = 13'd2586; +parameter ap_ST_fsm_state2588 = 13'd2587; +parameter ap_ST_fsm_state2589 = 13'd2588; +parameter ap_ST_fsm_state2590 = 13'd2589; +parameter ap_ST_fsm_state2591 = 13'd2590; +parameter ap_ST_fsm_state2592 = 13'd2591; +parameter ap_ST_fsm_state2593 = 13'd2592; +parameter ap_ST_fsm_state2594 = 13'd2593; +parameter ap_ST_fsm_state2595 = 13'd2594; +parameter ap_ST_fsm_state2596 = 13'd2595; +parameter ap_ST_fsm_state2597 = 13'd2596; +parameter ap_ST_fsm_state2598 = 13'd2597; +parameter ap_ST_fsm_state2599 = 13'd2598; +parameter ap_ST_fsm_state2600 = 13'd2599; +parameter ap_ST_fsm_state2601 = 13'd2600; +parameter ap_ST_fsm_state2602 = 13'd2601; +parameter ap_ST_fsm_state2603 = 13'd2602; +parameter ap_ST_fsm_state2604 = 13'd2603; +parameter ap_ST_fsm_state2605 = 13'd2604; +parameter ap_ST_fsm_state2606 = 13'd2605; +parameter ap_ST_fsm_state2607 = 13'd2606; +parameter ap_ST_fsm_state2608 = 13'd2607; +parameter ap_ST_fsm_state2609 = 13'd2608; +parameter ap_ST_fsm_state2610 = 13'd2609; +parameter ap_ST_fsm_state2611 = 13'd2610; +parameter ap_ST_fsm_state2612 = 13'd2611; +parameter ap_ST_fsm_state2613 = 13'd2612; +parameter ap_ST_fsm_state2614 = 13'd2613; +parameter ap_ST_fsm_state2615 = 13'd2614; +parameter ap_ST_fsm_state2616 = 13'd2615; +parameter ap_ST_fsm_state2617 = 13'd2616; +parameter ap_ST_fsm_state2618 = 13'd2617; +parameter ap_ST_fsm_state2619 = 13'd2618; +parameter ap_ST_fsm_state2620 = 13'd2619; +parameter ap_ST_fsm_state2621 = 13'd2620; +parameter ap_ST_fsm_state2622 = 13'd2621; +parameter ap_ST_fsm_state2623 = 13'd2622; +parameter ap_ST_fsm_state2624 = 13'd2623; +parameter ap_ST_fsm_state2625 = 13'd2624; +parameter ap_ST_fsm_state2626 = 13'd2625; +parameter ap_ST_fsm_state2627 = 13'd2626; +parameter ap_ST_fsm_state2628 = 13'd2627; +parameter ap_ST_fsm_state2629 = 13'd2628; +parameter ap_ST_fsm_state2630 = 13'd2629; +parameter ap_ST_fsm_state2631 = 13'd2630; +parameter ap_ST_fsm_state2632 = 13'd2631; +parameter ap_ST_fsm_state2633 = 13'd2632; +parameter ap_ST_fsm_state2634 = 13'd2633; +parameter ap_ST_fsm_state2635 = 13'd2634; +parameter ap_ST_fsm_state2636 = 13'd2635; +parameter ap_ST_fsm_state2637 = 13'd2636; +parameter ap_ST_fsm_state2638 = 13'd2637; +parameter ap_ST_fsm_state2639 = 13'd2638; +parameter ap_ST_fsm_state2640 = 13'd2639; +parameter ap_ST_fsm_state2641 = 13'd2640; +parameter ap_ST_fsm_state2642 = 13'd2641; +parameter ap_ST_fsm_state2643 = 13'd2642; +parameter ap_ST_fsm_state2644 = 13'd2643; +parameter ap_ST_fsm_state2645 = 13'd2644; +parameter ap_ST_fsm_state2646 = 13'd2645; +parameter ap_ST_fsm_state2647 = 13'd2646; +parameter ap_ST_fsm_state2648 = 13'd2647; +parameter ap_ST_fsm_state2649 = 13'd2648; +parameter ap_ST_fsm_state2650 = 13'd2649; +parameter ap_ST_fsm_state2651 = 13'd2650; +parameter ap_ST_fsm_state2652 = 13'd2651; +parameter ap_ST_fsm_state2653 = 13'd2652; +parameter ap_ST_fsm_state2654 = 13'd2653; +parameter ap_ST_fsm_state2655 = 13'd2654; +parameter ap_ST_fsm_state2656 = 13'd2655; +parameter ap_ST_fsm_state2657 = 13'd2656; +parameter ap_ST_fsm_state2658 = 13'd2657; +parameter ap_ST_fsm_state2659 = 13'd2658; +parameter ap_ST_fsm_state2660 = 13'd2659; +parameter ap_ST_fsm_state2661 = 13'd2660; +parameter ap_ST_fsm_state2662 = 13'd2661; +parameter ap_ST_fsm_state2663 = 13'd2662; +parameter ap_ST_fsm_state2664 = 13'd2663; +parameter ap_ST_fsm_state2665 = 13'd2664; +parameter ap_ST_fsm_state2666 = 13'd2665; +parameter ap_ST_fsm_state2667 = 13'd2666; +parameter ap_ST_fsm_state2668 = 13'd2667; +parameter ap_ST_fsm_state2669 = 13'd2668; +parameter ap_ST_fsm_state2670 = 13'd2669; +parameter ap_ST_fsm_state2671 = 13'd2670; +parameter ap_ST_fsm_state2672 = 13'd2671; +parameter ap_ST_fsm_state2673 = 13'd2672; +parameter ap_ST_fsm_state2674 = 13'd2673; +parameter ap_ST_fsm_state2675 = 13'd2674; +parameter ap_ST_fsm_state2676 = 13'd2675; +parameter ap_ST_fsm_state2677 = 13'd2676; +parameter ap_ST_fsm_state2678 = 13'd2677; +parameter ap_ST_fsm_state2679 = 13'd2678; +parameter ap_ST_fsm_state2680 = 13'd2679; +parameter ap_ST_fsm_state2681 = 13'd2680; +parameter ap_ST_fsm_state2682 = 13'd2681; +parameter ap_ST_fsm_state2683 = 13'd2682; +parameter ap_ST_fsm_state2684 = 13'd2683; +parameter ap_ST_fsm_state2685 = 13'd2684; +parameter ap_ST_fsm_state2686 = 13'd2685; +parameter ap_ST_fsm_state2687 = 13'd2686; +parameter ap_ST_fsm_state2688 = 13'd2687; +parameter ap_ST_fsm_state2689 = 13'd2688; +parameter ap_ST_fsm_state2690 = 13'd2689; +parameter ap_ST_fsm_state2691 = 13'd2690; +parameter ap_ST_fsm_state2692 = 13'd2691; +parameter ap_ST_fsm_state2693 = 13'd2692; +parameter ap_ST_fsm_state2694 = 13'd2693; +parameter ap_ST_fsm_state2695 = 13'd2694; +parameter ap_ST_fsm_state2696 = 13'd2695; +parameter ap_ST_fsm_state2697 = 13'd2696; +parameter ap_ST_fsm_state2698 = 13'd2697; +parameter ap_ST_fsm_state2699 = 13'd2698; +parameter ap_ST_fsm_state2700 = 13'd2699; +parameter ap_ST_fsm_state2701 = 13'd2700; +parameter ap_ST_fsm_state2702 = 13'd2701; +parameter ap_ST_fsm_state2703 = 13'd2702; +parameter ap_ST_fsm_state2704 = 13'd2703; +parameter ap_ST_fsm_state2705 = 13'd2704; +parameter ap_ST_fsm_state2706 = 13'd2705; +parameter ap_ST_fsm_state2707 = 13'd2706; +parameter ap_ST_fsm_state2708 = 13'd2707; +parameter ap_ST_fsm_state2709 = 13'd2708; +parameter ap_ST_fsm_state2710 = 13'd2709; +parameter ap_ST_fsm_state2711 = 13'd2710; +parameter ap_ST_fsm_state2712 = 13'd2711; +parameter ap_ST_fsm_state2713 = 13'd2712; +parameter ap_ST_fsm_state2714 = 13'd2713; +parameter ap_ST_fsm_state2715 = 13'd2714; +parameter ap_ST_fsm_state2716 = 13'd2715; +parameter ap_ST_fsm_state2717 = 13'd2716; +parameter ap_ST_fsm_state2718 = 13'd2717; +parameter ap_ST_fsm_state2719 = 13'd2718; +parameter ap_ST_fsm_state2720 = 13'd2719; +parameter ap_ST_fsm_state2721 = 13'd2720; +parameter ap_ST_fsm_state2722 = 13'd2721; +parameter ap_ST_fsm_state2723 = 13'd2722; +parameter ap_ST_fsm_state2724 = 13'd2723; +parameter ap_ST_fsm_state2725 = 13'd2724; +parameter ap_ST_fsm_state2726 = 13'd2725; +parameter ap_ST_fsm_state2727 = 13'd2726; +parameter ap_ST_fsm_state2728 = 13'd2727; +parameter ap_ST_fsm_state2729 = 13'd2728; +parameter ap_ST_fsm_state2730 = 13'd2729; +parameter ap_ST_fsm_state2731 = 13'd2730; +parameter ap_ST_fsm_state2732 = 13'd2731; +parameter ap_ST_fsm_state2733 = 13'd2732; +parameter ap_ST_fsm_state2734 = 13'd2733; +parameter ap_ST_fsm_state2735 = 13'd2734; +parameter ap_ST_fsm_state2736 = 13'd2735; +parameter ap_ST_fsm_state2737 = 13'd2736; +parameter ap_ST_fsm_state2738 = 13'd2737; +parameter ap_ST_fsm_state2739 = 13'd2738; +parameter ap_ST_fsm_state2740 = 13'd2739; +parameter ap_ST_fsm_state2741 = 13'd2740; +parameter ap_ST_fsm_state2742 = 13'd2741; +parameter ap_ST_fsm_state2743 = 13'd2742; +parameter ap_ST_fsm_state2744 = 13'd2743; +parameter ap_ST_fsm_state2745 = 13'd2744; +parameter ap_ST_fsm_state2746 = 13'd2745; +parameter ap_ST_fsm_state2747 = 13'd2746; +parameter ap_ST_fsm_state2748 = 13'd2747; +parameter ap_ST_fsm_state2749 = 13'd2748; +parameter ap_ST_fsm_state2750 = 13'd2749; +parameter ap_ST_fsm_state2751 = 13'd2750; +parameter ap_ST_fsm_state2752 = 13'd2751; +parameter ap_ST_fsm_state2753 = 13'd2752; +parameter ap_ST_fsm_state2754 = 13'd2753; +parameter ap_ST_fsm_state2755 = 13'd2754; +parameter ap_ST_fsm_state2756 = 13'd2755; +parameter ap_ST_fsm_state2757 = 13'd2756; +parameter ap_ST_fsm_state2758 = 13'd2757; +parameter ap_ST_fsm_state2759 = 13'd2758; +parameter ap_ST_fsm_state2760 = 13'd2759; +parameter ap_ST_fsm_state2761 = 13'd2760; +parameter ap_ST_fsm_state2762 = 13'd2761; +parameter ap_ST_fsm_state2763 = 13'd2762; +parameter ap_ST_fsm_state2764 = 13'd2763; +parameter ap_ST_fsm_state2765 = 13'd2764; +parameter ap_ST_fsm_state2766 = 13'd2765; +parameter ap_ST_fsm_state2767 = 13'd2766; +parameter ap_ST_fsm_state2768 = 13'd2767; +parameter ap_ST_fsm_state2769 = 13'd2768; +parameter ap_ST_fsm_state2770 = 13'd2769; +parameter ap_ST_fsm_state2771 = 13'd2770; +parameter ap_ST_fsm_state2772 = 13'd2771; +parameter ap_ST_fsm_state2773 = 13'd2772; +parameter ap_ST_fsm_state2774 = 13'd2773; +parameter ap_ST_fsm_state2775 = 13'd2774; +parameter ap_ST_fsm_state2776 = 13'd2775; +parameter ap_ST_fsm_state2777 = 13'd2776; +parameter ap_ST_fsm_state2778 = 13'd2777; +parameter ap_ST_fsm_state2779 = 13'd2778; +parameter ap_ST_fsm_state2780 = 13'd2779; +parameter ap_ST_fsm_state2781 = 13'd2780; +parameter ap_ST_fsm_state2782 = 13'd2781; +parameter ap_ST_fsm_state2783 = 13'd2782; +parameter ap_ST_fsm_state2784 = 13'd2783; +parameter ap_ST_fsm_state2785 = 13'd2784; +parameter ap_ST_fsm_state2786 = 13'd2785; +parameter ap_ST_fsm_state2787 = 13'd2786; +parameter ap_ST_fsm_state2788 = 13'd2787; +parameter ap_ST_fsm_state2789 = 13'd2788; +parameter ap_ST_fsm_state2790 = 13'd2789; +parameter ap_ST_fsm_state2791 = 13'd2790; +parameter ap_ST_fsm_state2792 = 13'd2791; +parameter ap_ST_fsm_state2793 = 13'd2792; +parameter ap_ST_fsm_state2794 = 13'd2793; +parameter ap_ST_fsm_state2795 = 13'd2794; +parameter ap_ST_fsm_state2796 = 13'd2795; +parameter ap_ST_fsm_state2797 = 13'd2796; +parameter ap_ST_fsm_state2798 = 13'd2797; +parameter ap_ST_fsm_state2799 = 13'd2798; +parameter ap_ST_fsm_state2800 = 13'd2799; +parameter ap_ST_fsm_state2801 = 13'd2800; +parameter ap_ST_fsm_state2802 = 13'd2801; +parameter ap_ST_fsm_state2803 = 13'd2802; +parameter ap_ST_fsm_state2804 = 13'd2803; +parameter ap_ST_fsm_state2805 = 13'd2804; +parameter ap_ST_fsm_state2806 = 13'd2805; +parameter ap_ST_fsm_state2807 = 13'd2806; +parameter ap_ST_fsm_state2808 = 13'd2807; +parameter ap_ST_fsm_state2809 = 13'd2808; +parameter ap_ST_fsm_state2810 = 13'd2809; +parameter ap_ST_fsm_state2811 = 13'd2810; +parameter ap_ST_fsm_state2812 = 13'd2811; +parameter ap_ST_fsm_state2813 = 13'd2812; +parameter ap_ST_fsm_state2814 = 13'd2813; +parameter ap_ST_fsm_state2815 = 13'd2814; +parameter ap_ST_fsm_state2816 = 13'd2815; +parameter ap_ST_fsm_state2817 = 13'd2816; +parameter ap_ST_fsm_state2818 = 13'd2817; +parameter ap_ST_fsm_state2819 = 13'd2818; +parameter ap_ST_fsm_state2820 = 13'd2819; +parameter ap_ST_fsm_state2821 = 13'd2820; +parameter ap_ST_fsm_state2822 = 13'd2821; +parameter ap_ST_fsm_state2823 = 13'd2822; +parameter ap_ST_fsm_state2824 = 13'd2823; +parameter ap_ST_fsm_state2825 = 13'd2824; +parameter ap_ST_fsm_state2826 = 13'd2825; +parameter ap_ST_fsm_state2827 = 13'd2826; +parameter ap_ST_fsm_state2828 = 13'd2827; +parameter ap_ST_fsm_state2829 = 13'd2828; +parameter ap_ST_fsm_state2830 = 13'd2829; +parameter ap_ST_fsm_state2831 = 13'd2830; +parameter ap_ST_fsm_state2832 = 13'd2831; +parameter ap_ST_fsm_state2833 = 13'd2832; +parameter ap_ST_fsm_state2834 = 13'd2833; +parameter ap_ST_fsm_state2835 = 13'd2834; +parameter ap_ST_fsm_state2836 = 13'd2835; +parameter ap_ST_fsm_state2837 = 13'd2836; +parameter ap_ST_fsm_state2838 = 13'd2837; +parameter ap_ST_fsm_state2839 = 13'd2838; +parameter ap_ST_fsm_state2840 = 13'd2839; +parameter ap_ST_fsm_state2841 = 13'd2840; +parameter ap_ST_fsm_state2842 = 13'd2841; +parameter ap_ST_fsm_state2843 = 13'd2842; +parameter ap_ST_fsm_state2844 = 13'd2843; +parameter ap_ST_fsm_state2845 = 13'd2844; +parameter ap_ST_fsm_state2846 = 13'd2845; +parameter ap_ST_fsm_state2847 = 13'd2846; +parameter ap_ST_fsm_state2848 = 13'd2847; +parameter ap_ST_fsm_state2849 = 13'd2848; +parameter ap_ST_fsm_state2850 = 13'd2849; +parameter ap_ST_fsm_state2851 = 13'd2850; +parameter ap_ST_fsm_state2852 = 13'd2851; +parameter ap_ST_fsm_state2853 = 13'd2852; +parameter ap_ST_fsm_state2854 = 13'd2853; +parameter ap_ST_fsm_state2855 = 13'd2854; +parameter ap_ST_fsm_state2856 = 13'd2855; +parameter ap_ST_fsm_state2857 = 13'd2856; +parameter ap_ST_fsm_state2858 = 13'd2857; +parameter ap_ST_fsm_state2859 = 13'd2858; +parameter ap_ST_fsm_state2860 = 13'd2859; +parameter ap_ST_fsm_state2861 = 13'd2860; +parameter ap_ST_fsm_state2862 = 13'd2861; +parameter ap_ST_fsm_state2863 = 13'd2862; +parameter ap_ST_fsm_state2864 = 13'd2863; +parameter ap_ST_fsm_state2865 = 13'd2864; +parameter ap_ST_fsm_state2866 = 13'd2865; +parameter ap_ST_fsm_state2867 = 13'd2866; +parameter ap_ST_fsm_state2868 = 13'd2867; +parameter ap_ST_fsm_state2869 = 13'd2868; +parameter ap_ST_fsm_state2870 = 13'd2869; +parameter ap_ST_fsm_state2871 = 13'd2870; +parameter ap_ST_fsm_state2872 = 13'd2871; +parameter ap_ST_fsm_state2873 = 13'd2872; +parameter ap_ST_fsm_state2874 = 13'd2873; +parameter ap_ST_fsm_state2875 = 13'd2874; +parameter ap_ST_fsm_state2876 = 13'd2875; +parameter ap_ST_fsm_state2877 = 13'd2876; +parameter ap_ST_fsm_state2878 = 13'd2877; +parameter ap_ST_fsm_state2879 = 13'd2878; +parameter ap_ST_fsm_state2880 = 13'd2879; +parameter ap_ST_fsm_state2881 = 13'd2880; +parameter ap_ST_fsm_state2882 = 13'd2881; +parameter ap_ST_fsm_state2883 = 13'd2882; +parameter ap_ST_fsm_state2884 = 13'd2883; +parameter ap_ST_fsm_state2885 = 13'd2884; +parameter ap_ST_fsm_state2886 = 13'd2885; +parameter ap_ST_fsm_state2887 = 13'd2886; +parameter ap_ST_fsm_state2888 = 13'd2887; +parameter ap_ST_fsm_state2889 = 13'd2888; +parameter ap_ST_fsm_state2890 = 13'd2889; +parameter ap_ST_fsm_state2891 = 13'd2890; +parameter ap_ST_fsm_state2892 = 13'd2891; +parameter ap_ST_fsm_state2893 = 13'd2892; +parameter ap_ST_fsm_state2894 = 13'd2893; +parameter ap_ST_fsm_state2895 = 13'd2894; +parameter ap_ST_fsm_state2896 = 13'd2895; +parameter ap_ST_fsm_state2897 = 13'd2896; +parameter ap_ST_fsm_state2898 = 13'd2897; +parameter ap_ST_fsm_state2899 = 13'd2898; +parameter ap_ST_fsm_state2900 = 13'd2899; +parameter ap_ST_fsm_state2901 = 13'd2900; +parameter ap_ST_fsm_state2902 = 13'd2901; +parameter ap_ST_fsm_state2903 = 13'd2902; +parameter ap_ST_fsm_state2904 = 13'd2903; +parameter ap_ST_fsm_state2905 = 13'd2904; +parameter ap_ST_fsm_state2906 = 13'd2905; +parameter ap_ST_fsm_state2907 = 13'd2906; +parameter ap_ST_fsm_state2908 = 13'd2907; +parameter ap_ST_fsm_state2909 = 13'd2908; +parameter ap_ST_fsm_state2910 = 13'd2909; +parameter ap_ST_fsm_state2911 = 13'd2910; +parameter ap_ST_fsm_state2912 = 13'd2911; +parameter ap_ST_fsm_state2913 = 13'd2912; +parameter ap_ST_fsm_state2914 = 13'd2913; +parameter ap_ST_fsm_state2915 = 13'd2914; +parameter ap_ST_fsm_state2916 = 13'd2915; +parameter ap_ST_fsm_state2917 = 13'd2916; +parameter ap_ST_fsm_state2918 = 13'd2917; +parameter ap_ST_fsm_state2919 = 13'd2918; +parameter ap_ST_fsm_state2920 = 13'd2919; +parameter ap_ST_fsm_state2921 = 13'd2920; +parameter ap_ST_fsm_state2922 = 13'd2921; +parameter ap_ST_fsm_state2923 = 13'd2922; +parameter ap_ST_fsm_state2924 = 13'd2923; +parameter ap_ST_fsm_state2925 = 13'd2924; +parameter ap_ST_fsm_state2926 = 13'd2925; +parameter ap_ST_fsm_state2927 = 13'd2926; +parameter ap_ST_fsm_state2928 = 13'd2927; +parameter ap_ST_fsm_state2929 = 13'd2928; +parameter ap_ST_fsm_state2930 = 13'd2929; +parameter ap_ST_fsm_state2931 = 13'd2930; +parameter ap_ST_fsm_state2932 = 13'd2931; +parameter ap_ST_fsm_state2933 = 13'd2932; +parameter ap_ST_fsm_state2934 = 13'd2933; +parameter ap_ST_fsm_state2935 = 13'd2934; +parameter ap_ST_fsm_state2936 = 13'd2935; +parameter ap_ST_fsm_state2937 = 13'd2936; +parameter ap_ST_fsm_state2938 = 13'd2937; +parameter ap_ST_fsm_state2939 = 13'd2938; +parameter ap_ST_fsm_state2940 = 13'd2939; +parameter ap_ST_fsm_state2941 = 13'd2940; +parameter ap_ST_fsm_state2942 = 13'd2941; +parameter ap_ST_fsm_state2943 = 13'd2942; +parameter ap_ST_fsm_state2944 = 13'd2943; +parameter ap_ST_fsm_state2945 = 13'd2944; +parameter ap_ST_fsm_state2946 = 13'd2945; +parameter ap_ST_fsm_state2947 = 13'd2946; +parameter ap_ST_fsm_state2948 = 13'd2947; +parameter ap_ST_fsm_state2949 = 13'd2948; +parameter ap_ST_fsm_state2950 = 13'd2949; +parameter ap_ST_fsm_state2951 = 13'd2950; +parameter ap_ST_fsm_state2952 = 13'd2951; +parameter ap_ST_fsm_state2953 = 13'd2952; +parameter ap_ST_fsm_state2954 = 13'd2953; +parameter ap_ST_fsm_state2955 = 13'd2954; +parameter ap_ST_fsm_state2956 = 13'd2955; +parameter ap_ST_fsm_state2957 = 13'd2956; +parameter ap_ST_fsm_state2958 = 13'd2957; +parameter ap_ST_fsm_state2959 = 13'd2958; +parameter ap_ST_fsm_state2960 = 13'd2959; +parameter ap_ST_fsm_state2961 = 13'd2960; +parameter ap_ST_fsm_state2962 = 13'd2961; +parameter ap_ST_fsm_state2963 = 13'd2962; +parameter ap_ST_fsm_state2964 = 13'd2963; +parameter ap_ST_fsm_state2965 = 13'd2964; +parameter ap_ST_fsm_state2966 = 13'd2965; +parameter ap_ST_fsm_state2967 = 13'd2966; +parameter ap_ST_fsm_state2968 = 13'd2967; +parameter ap_ST_fsm_state2969 = 13'd2968; +parameter ap_ST_fsm_state2970 = 13'd2969; +parameter ap_ST_fsm_state2971 = 13'd2970; +parameter ap_ST_fsm_state2972 = 13'd2971; +parameter ap_ST_fsm_state2973 = 13'd2972; +parameter ap_ST_fsm_state2974 = 13'd2973; +parameter ap_ST_fsm_state2975 = 13'd2974; +parameter ap_ST_fsm_state2976 = 13'd2975; +parameter ap_ST_fsm_state2977 = 13'd2976; +parameter ap_ST_fsm_state2978 = 13'd2977; +parameter ap_ST_fsm_state2979 = 13'd2978; +parameter ap_ST_fsm_state2980 = 13'd2979; +parameter ap_ST_fsm_state2981 = 13'd2980; +parameter ap_ST_fsm_state2982 = 13'd2981; +parameter ap_ST_fsm_state2983 = 13'd2982; +parameter ap_ST_fsm_state2984 = 13'd2983; +parameter ap_ST_fsm_state2985 = 13'd2984; +parameter ap_ST_fsm_state2986 = 13'd2985; +parameter ap_ST_fsm_state2987 = 13'd2986; +parameter ap_ST_fsm_state2988 = 13'd2987; +parameter ap_ST_fsm_state2989 = 13'd2988; +parameter ap_ST_fsm_state2990 = 13'd2989; +parameter ap_ST_fsm_state2991 = 13'd2990; +parameter ap_ST_fsm_state2992 = 13'd2991; +parameter ap_ST_fsm_state2993 = 13'd2992; +parameter ap_ST_fsm_state2994 = 13'd2993; +parameter ap_ST_fsm_state2995 = 13'd2994; +parameter ap_ST_fsm_state2996 = 13'd2995; +parameter ap_ST_fsm_state2997 = 13'd2996; +parameter ap_ST_fsm_state2998 = 13'd2997; +parameter ap_ST_fsm_state2999 = 13'd2998; +parameter ap_ST_fsm_state3000 = 13'd2999; +parameter ap_ST_fsm_state3001 = 13'd3000; +parameter ap_ST_fsm_state3002 = 13'd3001; +parameter ap_ST_fsm_state3003 = 13'd3002; +parameter ap_ST_fsm_state3004 = 13'd3003; +parameter ap_ST_fsm_state3005 = 13'd3004; +parameter ap_ST_fsm_state3006 = 13'd3005; +parameter ap_ST_fsm_state3007 = 13'd3006; +parameter ap_ST_fsm_state3008 = 13'd3007; +parameter ap_ST_fsm_state3009 = 13'd3008; +parameter ap_ST_fsm_state3010 = 13'd3009; +parameter ap_ST_fsm_state3011 = 13'd3010; +parameter ap_ST_fsm_state3012 = 13'd3011; +parameter ap_ST_fsm_state3013 = 13'd3012; +parameter ap_ST_fsm_state3014 = 13'd3013; +parameter ap_ST_fsm_state3015 = 13'd3014; +parameter ap_ST_fsm_state3016 = 13'd3015; +parameter ap_ST_fsm_state3017 = 13'd3016; +parameter ap_ST_fsm_state3018 = 13'd3017; +parameter ap_ST_fsm_state3019 = 13'd3018; +parameter ap_ST_fsm_state3020 = 13'd3019; +parameter ap_ST_fsm_state3021 = 13'd3020; +parameter ap_ST_fsm_state3022 = 13'd3021; +parameter ap_ST_fsm_state3023 = 13'd3022; +parameter ap_ST_fsm_state3024 = 13'd3023; +parameter ap_ST_fsm_state3025 = 13'd3024; +parameter ap_ST_fsm_state3026 = 13'd3025; +parameter ap_ST_fsm_state3027 = 13'd3026; +parameter ap_ST_fsm_state3028 = 13'd3027; +parameter ap_ST_fsm_state3029 = 13'd3028; +parameter ap_ST_fsm_state3030 = 13'd3029; +parameter ap_ST_fsm_state3031 = 13'd3030; +parameter ap_ST_fsm_state3032 = 13'd3031; +parameter ap_ST_fsm_state3033 = 13'd3032; +parameter ap_ST_fsm_state3034 = 13'd3033; +parameter ap_ST_fsm_state3035 = 13'd3034; +parameter ap_ST_fsm_state3036 = 13'd3035; +parameter ap_ST_fsm_state3037 = 13'd3036; +parameter ap_ST_fsm_state3038 = 13'd3037; +parameter ap_ST_fsm_state3039 = 13'd3038; +parameter ap_ST_fsm_state3040 = 13'd3039; +parameter ap_ST_fsm_state3041 = 13'd3040; +parameter ap_ST_fsm_state3042 = 13'd3041; +parameter ap_ST_fsm_state3043 = 13'd3042; +parameter ap_ST_fsm_state3044 = 13'd3043; +parameter ap_ST_fsm_state3045 = 13'd3044; +parameter ap_ST_fsm_state3046 = 13'd3045; +parameter ap_ST_fsm_state3047 = 13'd3046; +parameter ap_ST_fsm_state3048 = 13'd3047; +parameter ap_ST_fsm_state3049 = 13'd3048; +parameter ap_ST_fsm_state3050 = 13'd3049; +parameter ap_ST_fsm_state3051 = 13'd3050; +parameter ap_ST_fsm_state3052 = 13'd3051; +parameter ap_ST_fsm_state3053 = 13'd3052; +parameter ap_ST_fsm_state3054 = 13'd3053; +parameter ap_ST_fsm_state3055 = 13'd3054; +parameter ap_ST_fsm_state3056 = 13'd3055; +parameter ap_ST_fsm_state3057 = 13'd3056; +parameter ap_ST_fsm_state3058 = 13'd3057; +parameter ap_ST_fsm_state3059 = 13'd3058; +parameter ap_ST_fsm_state3060 = 13'd3059; +parameter ap_ST_fsm_state3061 = 13'd3060; +parameter ap_ST_fsm_state3062 = 13'd3061; +parameter ap_ST_fsm_state3063 = 13'd3062; +parameter ap_ST_fsm_state3064 = 13'd3063; +parameter ap_ST_fsm_state3065 = 13'd3064; +parameter ap_ST_fsm_state3066 = 13'd3065; +parameter ap_ST_fsm_state3067 = 13'd3066; +parameter ap_ST_fsm_state3068 = 13'd3067; +parameter ap_ST_fsm_state3069 = 13'd3068; +parameter ap_ST_fsm_state3070 = 13'd3069; +parameter ap_ST_fsm_state3071 = 13'd3070; +parameter ap_ST_fsm_state3072 = 13'd3071; +parameter ap_ST_fsm_state3073 = 13'd3072; +parameter ap_ST_fsm_state3074 = 13'd3073; +parameter ap_ST_fsm_state3075 = 13'd3074; +parameter ap_ST_fsm_state3076 = 13'd3075; +parameter ap_ST_fsm_state3077 = 13'd3076; +parameter ap_ST_fsm_state3078 = 13'd3077; +parameter ap_ST_fsm_state3079 = 13'd3078; +parameter ap_ST_fsm_state3080 = 13'd3079; +parameter ap_ST_fsm_state3081 = 13'd3080; +parameter ap_ST_fsm_state3082 = 13'd3081; +parameter ap_ST_fsm_state3083 = 13'd3082; +parameter ap_ST_fsm_state3084 = 13'd3083; +parameter ap_ST_fsm_state3085 = 13'd3084; +parameter ap_ST_fsm_state3086 = 13'd3085; +parameter ap_ST_fsm_state3087 = 13'd3086; +parameter ap_ST_fsm_state3088 = 13'd3087; +parameter ap_ST_fsm_state3089 = 13'd3088; +parameter ap_ST_fsm_state3090 = 13'd3089; +parameter ap_ST_fsm_state3091 = 13'd3090; +parameter ap_ST_fsm_state3092 = 13'd3091; +parameter ap_ST_fsm_state3093 = 13'd3092; +parameter ap_ST_fsm_state3094 = 13'd3093; +parameter ap_ST_fsm_state3095 = 13'd3094; +parameter ap_ST_fsm_state3096 = 13'd3095; +parameter ap_ST_fsm_state3097 = 13'd3096; +parameter ap_ST_fsm_state3098 = 13'd3097; +parameter ap_ST_fsm_state3099 = 13'd3098; +parameter ap_ST_fsm_state3100 = 13'd3099; +parameter ap_ST_fsm_state3101 = 13'd3100; +parameter ap_ST_fsm_state3102 = 13'd3101; +parameter ap_ST_fsm_state3103 = 13'd3102; +parameter ap_ST_fsm_state3104 = 13'd3103; +parameter ap_ST_fsm_state3105 = 13'd3104; +parameter ap_ST_fsm_state3106 = 13'd3105; +parameter ap_ST_fsm_state3107 = 13'd3106; +parameter ap_ST_fsm_state3108 = 13'd3107; +parameter ap_ST_fsm_state3109 = 13'd3108; +parameter ap_ST_fsm_state3110 = 13'd3109; +parameter ap_ST_fsm_state3111 = 13'd3110; +parameter ap_ST_fsm_state3112 = 13'd3111; +parameter ap_ST_fsm_state3113 = 13'd3112; +parameter ap_ST_fsm_state3114 = 13'd3113; +parameter ap_ST_fsm_state3115 = 13'd3114; +parameter ap_ST_fsm_state3116 = 13'd3115; +parameter ap_ST_fsm_state3117 = 13'd3116; +parameter ap_ST_fsm_state3118 = 13'd3117; +parameter ap_ST_fsm_state3119 = 13'd3118; +parameter ap_ST_fsm_state3120 = 13'd3119; +parameter ap_ST_fsm_state3121 = 13'd3120; +parameter ap_ST_fsm_state3122 = 13'd3121; +parameter ap_ST_fsm_state3123 = 13'd3122; +parameter ap_ST_fsm_state3124 = 13'd3123; +parameter ap_ST_fsm_state3125 = 13'd3124; +parameter ap_ST_fsm_state3126 = 13'd3125; +parameter ap_ST_fsm_state3127 = 13'd3126; +parameter ap_ST_fsm_state3128 = 13'd3127; +parameter ap_ST_fsm_state3129 = 13'd3128; +parameter ap_ST_fsm_state3130 = 13'd3129; +parameter ap_ST_fsm_state3131 = 13'd3130; +parameter ap_ST_fsm_state3132 = 13'd3131; +parameter ap_ST_fsm_state3133 = 13'd3132; +parameter ap_ST_fsm_state3134 = 13'd3133; +parameter ap_ST_fsm_state3135 = 13'd3134; +parameter ap_ST_fsm_state3136 = 13'd3135; +parameter ap_ST_fsm_state3137 = 13'd3136; +parameter ap_ST_fsm_state3138 = 13'd3137; +parameter ap_ST_fsm_state3139 = 13'd3138; +parameter ap_ST_fsm_state3140 = 13'd3139; +parameter ap_ST_fsm_state3141 = 13'd3140; +parameter ap_ST_fsm_state3142 = 13'd3141; +parameter ap_ST_fsm_state3143 = 13'd3142; +parameter ap_ST_fsm_state3144 = 13'd3143; +parameter ap_ST_fsm_state3145 = 13'd3144; +parameter ap_ST_fsm_state3146 = 13'd3145; +parameter ap_ST_fsm_state3147 = 13'd3146; +parameter ap_ST_fsm_state3148 = 13'd3147; +parameter ap_ST_fsm_state3149 = 13'd3148; +parameter ap_ST_fsm_state3150 = 13'd3149; +parameter ap_ST_fsm_state3151 = 13'd3150; +parameter ap_ST_fsm_state3152 = 13'd3151; +parameter ap_ST_fsm_state3153 = 13'd3152; +parameter ap_ST_fsm_state3154 = 13'd3153; +parameter ap_ST_fsm_state3155 = 13'd3154; +parameter ap_ST_fsm_state3156 = 13'd3155; +parameter ap_ST_fsm_state3157 = 13'd3156; +parameter ap_ST_fsm_state3158 = 13'd3157; +parameter ap_ST_fsm_state3159 = 13'd3158; +parameter ap_ST_fsm_state3160 = 13'd3159; +parameter ap_ST_fsm_state3161 = 13'd3160; +parameter ap_ST_fsm_state3162 = 13'd3161; +parameter ap_ST_fsm_state3163 = 13'd3162; +parameter ap_ST_fsm_state3164 = 13'd3163; +parameter ap_ST_fsm_state3165 = 13'd3164; +parameter ap_ST_fsm_state3166 = 13'd3165; +parameter ap_ST_fsm_state3167 = 13'd3166; +parameter ap_ST_fsm_state3168 = 13'd3167; +parameter ap_ST_fsm_state3169 = 13'd3168; +parameter ap_ST_fsm_state3170 = 13'd3169; +parameter ap_ST_fsm_state3171 = 13'd3170; +parameter ap_ST_fsm_state3172 = 13'd3171; +parameter ap_ST_fsm_state3173 = 13'd3172; +parameter ap_ST_fsm_state3174 = 13'd3173; +parameter ap_ST_fsm_state3175 = 13'd3174; +parameter ap_ST_fsm_state3176 = 13'd3175; +parameter ap_ST_fsm_state3177 = 13'd3176; +parameter ap_ST_fsm_state3178 = 13'd3177; +parameter ap_ST_fsm_state3179 = 13'd3178; +parameter ap_ST_fsm_state3180 = 13'd3179; +parameter ap_ST_fsm_state3181 = 13'd3180; +parameter ap_ST_fsm_state3182 = 13'd3181; +parameter ap_ST_fsm_state3183 = 13'd3182; +parameter ap_ST_fsm_state3184 = 13'd3183; +parameter ap_ST_fsm_state3185 = 13'd3184; +parameter ap_ST_fsm_state3186 = 13'd3185; +parameter ap_ST_fsm_state3187 = 13'd3186; +parameter ap_ST_fsm_state3188 = 13'd3187; +parameter ap_ST_fsm_state3189 = 13'd3188; +parameter ap_ST_fsm_state3190 = 13'd3189; +parameter ap_ST_fsm_state3191 = 13'd3190; +parameter ap_ST_fsm_state3192 = 13'd3191; +parameter ap_ST_fsm_state3193 = 13'd3192; +parameter ap_ST_fsm_state3194 = 13'd3193; +parameter ap_ST_fsm_state3195 = 13'd3194; +parameter ap_ST_fsm_state3196 = 13'd3195; +parameter ap_ST_fsm_state3197 = 13'd3196; +parameter ap_ST_fsm_state3198 = 13'd3197; +parameter ap_ST_fsm_state3199 = 13'd3198; +parameter ap_ST_fsm_state3200 = 13'd3199; +parameter ap_ST_fsm_state3201 = 13'd3200; +parameter ap_ST_fsm_state3202 = 13'd3201; +parameter ap_ST_fsm_state3203 = 13'd3202; +parameter ap_ST_fsm_state3204 = 13'd3203; +parameter ap_ST_fsm_state3205 = 13'd3204; +parameter ap_ST_fsm_state3206 = 13'd3205; +parameter ap_ST_fsm_state3207 = 13'd3206; +parameter ap_ST_fsm_state3208 = 13'd3207; +parameter ap_ST_fsm_state3209 = 13'd3208; +parameter ap_ST_fsm_state3210 = 13'd3209; +parameter ap_ST_fsm_state3211 = 13'd3210; +parameter ap_ST_fsm_state3212 = 13'd3211; +parameter ap_ST_fsm_state3213 = 13'd3212; +parameter ap_ST_fsm_state3214 = 13'd3213; +parameter ap_ST_fsm_state3215 = 13'd3214; +parameter ap_ST_fsm_state3216 = 13'd3215; +parameter ap_ST_fsm_state3217 = 13'd3216; +parameter ap_ST_fsm_state3218 = 13'd3217; +parameter ap_ST_fsm_state3219 = 13'd3218; +parameter ap_ST_fsm_state3220 = 13'd3219; +parameter ap_ST_fsm_state3221 = 13'd3220; +parameter ap_ST_fsm_state3222 = 13'd3221; +parameter ap_ST_fsm_state3223 = 13'd3222; +parameter ap_ST_fsm_state3224 = 13'd3223; +parameter ap_ST_fsm_state3225 = 13'd3224; +parameter ap_ST_fsm_state3226 = 13'd3225; +parameter ap_ST_fsm_state3227 = 13'd3226; +parameter ap_ST_fsm_state3228 = 13'd3227; +parameter ap_ST_fsm_state3229 = 13'd3228; +parameter ap_ST_fsm_state3230 = 13'd3229; +parameter ap_ST_fsm_state3231 = 13'd3230; +parameter ap_ST_fsm_state3232 = 13'd3231; +parameter ap_ST_fsm_state3233 = 13'd3232; +parameter ap_ST_fsm_state3234 = 13'd3233; +parameter ap_ST_fsm_state3235 = 13'd3234; +parameter ap_ST_fsm_state3236 = 13'd3235; +parameter ap_ST_fsm_state3237 = 13'd3236; +parameter ap_ST_fsm_state3238 = 13'd3237; +parameter ap_ST_fsm_state3239 = 13'd3238; +parameter ap_ST_fsm_state3240 = 13'd3239; +parameter ap_ST_fsm_state3241 = 13'd3240; +parameter ap_ST_fsm_state3242 = 13'd3241; +parameter ap_ST_fsm_state3243 = 13'd3242; +parameter ap_ST_fsm_state3244 = 13'd3243; +parameter ap_ST_fsm_state3245 = 13'd3244; +parameter ap_ST_fsm_state3246 = 13'd3245; +parameter ap_ST_fsm_state3247 = 13'd3246; +parameter ap_ST_fsm_state3248 = 13'd3247; +parameter ap_ST_fsm_state3249 = 13'd3248; +parameter ap_ST_fsm_state3250 = 13'd3249; +parameter ap_ST_fsm_state3251 = 13'd3250; +parameter ap_ST_fsm_state3252 = 13'd3251; +parameter ap_ST_fsm_state3253 = 13'd3252; +parameter ap_ST_fsm_state3254 = 13'd3253; +parameter ap_ST_fsm_state3255 = 13'd3254; +parameter ap_ST_fsm_state3256 = 13'd3255; +parameter ap_ST_fsm_state3257 = 13'd3256; +parameter ap_ST_fsm_state3258 = 13'd3257; +parameter ap_ST_fsm_state3259 = 13'd3258; +parameter ap_ST_fsm_state3260 = 13'd3259; +parameter ap_ST_fsm_state3261 = 13'd3260; +parameter ap_ST_fsm_state3262 = 13'd3261; +parameter ap_ST_fsm_state3263 = 13'd3262; +parameter ap_ST_fsm_state3264 = 13'd3263; +parameter ap_ST_fsm_state3265 = 13'd3264; +parameter ap_ST_fsm_state3266 = 13'd3265; +parameter ap_ST_fsm_state3267 = 13'd3266; +parameter ap_ST_fsm_state3268 = 13'd3267; +parameter ap_ST_fsm_state3269 = 13'd3268; +parameter ap_ST_fsm_state3270 = 13'd3269; +parameter ap_ST_fsm_state3271 = 13'd3270; +parameter ap_ST_fsm_state3272 = 13'd3271; +parameter ap_ST_fsm_state3273 = 13'd3272; +parameter ap_ST_fsm_state3274 = 13'd3273; +parameter ap_ST_fsm_state3275 = 13'd3274; +parameter ap_ST_fsm_state3276 = 13'd3275; +parameter ap_ST_fsm_state3277 = 13'd3276; +parameter ap_ST_fsm_state3278 = 13'd3277; +parameter ap_ST_fsm_state3279 = 13'd3278; +parameter ap_ST_fsm_state3280 = 13'd3279; +parameter ap_ST_fsm_state3281 = 13'd3280; +parameter ap_ST_fsm_state3282 = 13'd3281; +parameter ap_ST_fsm_state3283 = 13'd3282; +parameter ap_ST_fsm_state3284 = 13'd3283; +parameter ap_ST_fsm_state3285 = 13'd3284; +parameter ap_ST_fsm_state3286 = 13'd3285; +parameter ap_ST_fsm_state3287 = 13'd3286; +parameter ap_ST_fsm_state3288 = 13'd3287; +parameter ap_ST_fsm_state3289 = 13'd3288; +parameter ap_ST_fsm_state3290 = 13'd3289; +parameter ap_ST_fsm_state3291 = 13'd3290; +parameter ap_ST_fsm_state3292 = 13'd3291; +parameter ap_ST_fsm_state3293 = 13'd3292; +parameter ap_ST_fsm_state3294 = 13'd3293; +parameter ap_ST_fsm_state3295 = 13'd3294; +parameter ap_ST_fsm_state3296 = 13'd3295; +parameter ap_ST_fsm_state3297 = 13'd3296; +parameter ap_ST_fsm_state3298 = 13'd3297; +parameter ap_ST_fsm_state3299 = 13'd3298; +parameter ap_ST_fsm_state3300 = 13'd3299; +parameter ap_ST_fsm_state3301 = 13'd3300; +parameter ap_ST_fsm_state3302 = 13'd3301; +parameter ap_ST_fsm_state3303 = 13'd3302; +parameter ap_ST_fsm_state3304 = 13'd3303; +parameter ap_ST_fsm_state3305 = 13'd3304; +parameter ap_ST_fsm_state3306 = 13'd3305; +parameter ap_ST_fsm_state3307 = 13'd3306; +parameter ap_ST_fsm_state3308 = 13'd3307; +parameter ap_ST_fsm_state3309 = 13'd3308; +parameter ap_ST_fsm_state3310 = 13'd3309; +parameter ap_ST_fsm_state3311 = 13'd3310; +parameter ap_ST_fsm_state3312 = 13'd3311; +parameter ap_ST_fsm_state3313 = 13'd3312; +parameter ap_ST_fsm_state3314 = 13'd3313; +parameter ap_ST_fsm_state3315 = 13'd3314; +parameter ap_ST_fsm_state3316 = 13'd3315; +parameter ap_ST_fsm_state3317 = 13'd3316; +parameter ap_ST_fsm_state3318 = 13'd3317; +parameter ap_ST_fsm_state3319 = 13'd3318; +parameter ap_ST_fsm_state3320 = 13'd3319; +parameter ap_ST_fsm_state3321 = 13'd3320; +parameter ap_ST_fsm_state3322 = 13'd3321; +parameter ap_ST_fsm_state3323 = 13'd3322; +parameter ap_ST_fsm_state3324 = 13'd3323; +parameter ap_ST_fsm_state3325 = 13'd3324; +parameter ap_ST_fsm_state3326 = 13'd3325; +parameter ap_ST_fsm_state3327 = 13'd3326; +parameter ap_ST_fsm_state3328 = 13'd3327; +parameter ap_ST_fsm_state3329 = 13'd3328; +parameter ap_ST_fsm_state3330 = 13'd3329; +parameter ap_ST_fsm_state3331 = 13'd3330; +parameter ap_ST_fsm_state3332 = 13'd3331; +parameter ap_ST_fsm_state3333 = 13'd3332; +parameter ap_ST_fsm_state3334 = 13'd3333; +parameter ap_ST_fsm_state3335 = 13'd3334; +parameter ap_ST_fsm_state3336 = 13'd3335; +parameter ap_ST_fsm_state3337 = 13'd3336; +parameter ap_ST_fsm_state3338 = 13'd3337; +parameter ap_ST_fsm_state3339 = 13'd3338; +parameter ap_ST_fsm_state3340 = 13'd3339; +parameter ap_ST_fsm_state3341 = 13'd3340; +parameter ap_ST_fsm_state3342 = 13'd3341; +parameter ap_ST_fsm_state3343 = 13'd3342; +parameter ap_ST_fsm_state3344 = 13'd3343; +parameter ap_ST_fsm_state3345 = 13'd3344; +parameter ap_ST_fsm_state3346 = 13'd3345; +parameter ap_ST_fsm_state3347 = 13'd3346; +parameter ap_ST_fsm_state3348 = 13'd3347; +parameter ap_ST_fsm_state3349 = 13'd3348; +parameter ap_ST_fsm_state3350 = 13'd3349; +parameter ap_ST_fsm_state3351 = 13'd3350; +parameter ap_ST_fsm_state3352 = 13'd3351; +parameter ap_ST_fsm_state3353 = 13'd3352; +parameter ap_ST_fsm_state3354 = 13'd3353; +parameter ap_ST_fsm_state3355 = 13'd3354; +parameter ap_ST_fsm_state3356 = 13'd3355; +parameter ap_ST_fsm_state3357 = 13'd3356; +parameter ap_ST_fsm_state3358 = 13'd3357; +parameter ap_ST_fsm_state3359 = 13'd3358; +parameter ap_ST_fsm_state3360 = 13'd3359; +parameter ap_ST_fsm_state3361 = 13'd3360; +parameter ap_ST_fsm_state3362 = 13'd3361; +parameter ap_ST_fsm_state3363 = 13'd3362; +parameter ap_ST_fsm_state3364 = 13'd3363; +parameter ap_ST_fsm_state3365 = 13'd3364; +parameter ap_ST_fsm_state3366 = 13'd3365; +parameter ap_ST_fsm_state3367 = 13'd3366; +parameter ap_ST_fsm_state3368 = 13'd3367; +parameter ap_ST_fsm_state3369 = 13'd3368; +parameter ap_ST_fsm_state3370 = 13'd3369; +parameter ap_ST_fsm_state3371 = 13'd3370; +parameter ap_ST_fsm_state3372 = 13'd3371; +parameter ap_ST_fsm_state3373 = 13'd3372; +parameter ap_ST_fsm_state3374 = 13'd3373; +parameter ap_ST_fsm_state3375 = 13'd3374; +parameter ap_ST_fsm_state3376 = 13'd3375; +parameter ap_ST_fsm_state3377 = 13'd3376; +parameter ap_ST_fsm_state3378 = 13'd3377; +parameter ap_ST_fsm_state3379 = 13'd3378; +parameter ap_ST_fsm_state3380 = 13'd3379; +parameter ap_ST_fsm_state3381 = 13'd3380; +parameter ap_ST_fsm_state3382 = 13'd3381; +parameter ap_ST_fsm_state3383 = 13'd3382; +parameter ap_ST_fsm_state3384 = 13'd3383; +parameter ap_ST_fsm_state3385 = 13'd3384; +parameter ap_ST_fsm_state3386 = 13'd3385; +parameter ap_ST_fsm_state3387 = 13'd3386; +parameter ap_ST_fsm_state3388 = 13'd3387; +parameter ap_ST_fsm_state3389 = 13'd3388; +parameter ap_ST_fsm_state3390 = 13'd3389; +parameter ap_ST_fsm_state3391 = 13'd3390; +parameter ap_ST_fsm_state3392 = 13'd3391; +parameter ap_ST_fsm_state3393 = 13'd3392; +parameter ap_ST_fsm_state3394 = 13'd3393; +parameter ap_ST_fsm_state3395 = 13'd3394; +parameter ap_ST_fsm_state3396 = 13'd3395; +parameter ap_ST_fsm_state3397 = 13'd3396; +parameter ap_ST_fsm_state3398 = 13'd3397; +parameter ap_ST_fsm_state3399 = 13'd3398; +parameter ap_ST_fsm_state3400 = 13'd3399; +parameter ap_ST_fsm_state3401 = 13'd3400; +parameter ap_ST_fsm_state3402 = 13'd3401; +parameter ap_ST_fsm_state3403 = 13'd3402; +parameter ap_ST_fsm_state3404 = 13'd3403; +parameter ap_ST_fsm_state3405 = 13'd3404; +parameter ap_ST_fsm_state3406 = 13'd3405; +parameter ap_ST_fsm_state3407 = 13'd3406; +parameter ap_ST_fsm_state3408 = 13'd3407; +parameter ap_ST_fsm_state3409 = 13'd3408; +parameter ap_ST_fsm_state3410 = 13'd3409; +parameter ap_ST_fsm_state3411 = 13'd3410; +parameter ap_ST_fsm_state3412 = 13'd3411; +parameter ap_ST_fsm_state3413 = 13'd3412; +parameter ap_ST_fsm_state3414 = 13'd3413; +parameter ap_ST_fsm_state3415 = 13'd3414; +parameter ap_ST_fsm_state3416 = 13'd3415; +parameter ap_ST_fsm_state3417 = 13'd3416; +parameter ap_ST_fsm_state3418 = 13'd3417; +parameter ap_ST_fsm_state3419 = 13'd3418; +parameter ap_ST_fsm_state3420 = 13'd3419; +parameter ap_ST_fsm_state3421 = 13'd3420; +parameter ap_ST_fsm_state3422 = 13'd3421; +parameter ap_ST_fsm_state3423 = 13'd3422; +parameter ap_ST_fsm_state3424 = 13'd3423; +parameter ap_ST_fsm_state3425 = 13'd3424; +parameter ap_ST_fsm_state3426 = 13'd3425; +parameter ap_ST_fsm_state3427 = 13'd3426; +parameter ap_ST_fsm_state3428 = 13'd3427; +parameter ap_ST_fsm_state3429 = 13'd3428; +parameter ap_ST_fsm_state3430 = 13'd3429; +parameter ap_ST_fsm_state3431 = 13'd3430; +parameter ap_ST_fsm_state3432 = 13'd3431; +parameter ap_ST_fsm_state3433 = 13'd3432; +parameter ap_ST_fsm_state3434 = 13'd3433; +parameter ap_ST_fsm_state3435 = 13'd3434; +parameter ap_ST_fsm_state3436 = 13'd3435; +parameter ap_ST_fsm_state3437 = 13'd3436; +parameter ap_ST_fsm_state3438 = 13'd3437; +parameter ap_ST_fsm_state3439 = 13'd3438; +parameter ap_ST_fsm_state3440 = 13'd3439; +parameter ap_ST_fsm_state3441 = 13'd3440; +parameter ap_ST_fsm_state3442 = 13'd3441; +parameter ap_ST_fsm_state3443 = 13'd3442; +parameter ap_ST_fsm_state3444 = 13'd3443; +parameter ap_ST_fsm_state3445 = 13'd3444; +parameter ap_ST_fsm_state3446 = 13'd3445; +parameter ap_ST_fsm_state3447 = 13'd3446; +parameter ap_ST_fsm_state3448 = 13'd3447; +parameter ap_ST_fsm_state3449 = 13'd3448; +parameter ap_ST_fsm_state3450 = 13'd3449; +parameter ap_ST_fsm_state3451 = 13'd3450; +parameter ap_ST_fsm_state3452 = 13'd3451; +parameter ap_ST_fsm_state3453 = 13'd3452; +parameter ap_ST_fsm_state3454 = 13'd3453; +parameter ap_ST_fsm_state3455 = 13'd3454; +parameter ap_ST_fsm_state3456 = 13'd3455; +parameter ap_ST_fsm_state3457 = 13'd3456; +parameter ap_ST_fsm_state3458 = 13'd3457; +parameter ap_ST_fsm_state3459 = 13'd3458; +parameter ap_ST_fsm_state3460 = 13'd3459; +parameter ap_ST_fsm_state3461 = 13'd3460; +parameter ap_ST_fsm_state3462 = 13'd3461; +parameter ap_ST_fsm_state3463 = 13'd3462; +parameter ap_ST_fsm_state3464 = 13'd3463; +parameter ap_ST_fsm_state3465 = 13'd3464; +parameter ap_ST_fsm_state3466 = 13'd3465; +parameter ap_ST_fsm_state3467 = 13'd3466; +parameter ap_ST_fsm_state3468 = 13'd3467; +parameter ap_ST_fsm_state3469 = 13'd3468; +parameter ap_ST_fsm_state3470 = 13'd3469; +parameter ap_ST_fsm_state3471 = 13'd3470; +parameter ap_ST_fsm_state3472 = 13'd3471; +parameter ap_ST_fsm_state3473 = 13'd3472; +parameter ap_ST_fsm_state3474 = 13'd3473; +parameter ap_ST_fsm_state3475 = 13'd3474; +parameter ap_ST_fsm_state3476 = 13'd3475; +parameter ap_ST_fsm_state3477 = 13'd3476; +parameter ap_ST_fsm_state3478 = 13'd3477; +parameter ap_ST_fsm_state3479 = 13'd3478; +parameter ap_ST_fsm_state3480 = 13'd3479; +parameter ap_ST_fsm_state3481 = 13'd3480; +parameter ap_ST_fsm_state3482 = 13'd3481; +parameter ap_ST_fsm_state3483 = 13'd3482; +parameter ap_ST_fsm_state3484 = 13'd3483; +parameter ap_ST_fsm_state3485 = 13'd3484; +parameter ap_ST_fsm_state3486 = 13'd3485; +parameter ap_ST_fsm_state3487 = 13'd3486; +parameter ap_ST_fsm_state3488 = 13'd3487; +parameter ap_ST_fsm_state3489 = 13'd3488; +parameter ap_ST_fsm_state3490 = 13'd3489; +parameter ap_ST_fsm_state3491 = 13'd3490; +parameter ap_ST_fsm_state3492 = 13'd3491; +parameter ap_ST_fsm_state3493 = 13'd3492; +parameter ap_ST_fsm_state3494 = 13'd3493; +parameter ap_ST_fsm_state3495 = 13'd3494; +parameter ap_ST_fsm_state3496 = 13'd3495; +parameter ap_ST_fsm_state3497 = 13'd3496; +parameter ap_ST_fsm_state3498 = 13'd3497; +parameter ap_ST_fsm_state3499 = 13'd3498; +parameter ap_ST_fsm_state3500 = 13'd3499; +parameter ap_ST_fsm_state3501 = 13'd3500; +parameter ap_ST_fsm_state3502 = 13'd3501; +parameter ap_ST_fsm_state3503 = 13'd3502; +parameter ap_ST_fsm_state3504 = 13'd3503; +parameter ap_ST_fsm_state3505 = 13'd3504; +parameter ap_ST_fsm_state3506 = 13'd3505; +parameter ap_ST_fsm_state3507 = 13'd3506; +parameter ap_ST_fsm_state3508 = 13'd3507; +parameter ap_ST_fsm_state3509 = 13'd3508; +parameter ap_ST_fsm_state3510 = 13'd3509; +parameter ap_ST_fsm_state3511 = 13'd3510; +parameter ap_ST_fsm_state3512 = 13'd3511; +parameter ap_ST_fsm_state3513 = 13'd3512; +parameter ap_ST_fsm_state3514 = 13'd3513; +parameter ap_ST_fsm_state3515 = 13'd3514; +parameter ap_ST_fsm_state3516 = 13'd3515; +parameter ap_ST_fsm_state3517 = 13'd3516; +parameter ap_ST_fsm_state3518 = 13'd3517; +parameter ap_ST_fsm_state3519 = 13'd3518; +parameter ap_ST_fsm_state3520 = 13'd3519; +parameter ap_ST_fsm_state3521 = 13'd3520; +parameter ap_ST_fsm_state3522 = 13'd3521; +parameter ap_ST_fsm_state3523 = 13'd3522; +parameter ap_ST_fsm_state3524 = 13'd3523; +parameter ap_ST_fsm_state3525 = 13'd3524; +parameter ap_ST_fsm_state3526 = 13'd3525; +parameter ap_ST_fsm_state3527 = 13'd3526; +parameter ap_ST_fsm_state3528 = 13'd3527; +parameter ap_ST_fsm_state3529 = 13'd3528; +parameter ap_ST_fsm_state3530 = 13'd3529; +parameter ap_ST_fsm_state3531 = 13'd3530; +parameter ap_ST_fsm_state3532 = 13'd3531; +parameter ap_ST_fsm_state3533 = 13'd3532; +parameter ap_ST_fsm_state3534 = 13'd3533; +parameter ap_ST_fsm_state3535 = 13'd3534; +parameter ap_ST_fsm_state3536 = 13'd3535; +parameter ap_ST_fsm_state3537 = 13'd3536; +parameter ap_ST_fsm_state3538 = 13'd3537; +parameter ap_ST_fsm_state3539 = 13'd3538; +parameter ap_ST_fsm_state3540 = 13'd3539; +parameter ap_ST_fsm_state3541 = 13'd3540; +parameter ap_ST_fsm_state3542 = 13'd3541; +parameter ap_ST_fsm_state3543 = 13'd3542; +parameter ap_ST_fsm_state3544 = 13'd3543; +parameter ap_ST_fsm_state3545 = 13'd3544; +parameter ap_ST_fsm_state3546 = 13'd3545; +parameter ap_ST_fsm_state3547 = 13'd3546; +parameter ap_ST_fsm_state3548 = 13'd3547; +parameter ap_ST_fsm_state3549 = 13'd3548; +parameter ap_ST_fsm_state3550 = 13'd3549; +parameter ap_ST_fsm_state3551 = 13'd3550; +parameter ap_ST_fsm_state3552 = 13'd3551; +parameter ap_ST_fsm_state3553 = 13'd3552; +parameter ap_ST_fsm_state3554 = 13'd3553; +parameter ap_ST_fsm_state3555 = 13'd3554; +parameter ap_ST_fsm_state3556 = 13'd3555; +parameter ap_ST_fsm_state3557 = 13'd3556; +parameter ap_ST_fsm_state3558 = 13'd3557; +parameter ap_ST_fsm_state3559 = 13'd3558; +parameter ap_ST_fsm_state3560 = 13'd3559; +parameter ap_ST_fsm_state3561 = 13'd3560; +parameter ap_ST_fsm_state3562 = 13'd3561; +parameter ap_ST_fsm_state3563 = 13'd3562; +parameter ap_ST_fsm_state3564 = 13'd3563; +parameter ap_ST_fsm_state3565 = 13'd3564; +parameter ap_ST_fsm_state3566 = 13'd3565; +parameter ap_ST_fsm_state3567 = 13'd3566; +parameter ap_ST_fsm_state3568 = 13'd3567; +parameter ap_ST_fsm_state3569 = 13'd3568; +parameter ap_ST_fsm_state3570 = 13'd3569; +parameter ap_ST_fsm_state3571 = 13'd3570; +parameter ap_ST_fsm_state3572 = 13'd3571; +parameter ap_ST_fsm_state3573 = 13'd3572; +parameter ap_ST_fsm_state3574 = 13'd3573; +parameter ap_ST_fsm_state3575 = 13'd3574; +parameter ap_ST_fsm_state3576 = 13'd3575; +parameter ap_ST_fsm_state3577 = 13'd3576; +parameter ap_ST_fsm_state3578 = 13'd3577; +parameter ap_ST_fsm_state3579 = 13'd3578; +parameter ap_ST_fsm_state3580 = 13'd3579; +parameter ap_ST_fsm_state3581 = 13'd3580; +parameter ap_ST_fsm_state3582 = 13'd3581; +parameter ap_ST_fsm_state3583 = 13'd3582; +parameter ap_ST_fsm_state3584 = 13'd3583; +parameter ap_ST_fsm_state3585 = 13'd3584; +parameter ap_ST_fsm_state3586 = 13'd3585; +parameter ap_ST_fsm_state3587 = 13'd3586; +parameter ap_ST_fsm_state3588 = 13'd3587; +parameter ap_ST_fsm_state3589 = 13'd3588; +parameter ap_ST_fsm_state3590 = 13'd3589; +parameter ap_ST_fsm_state3591 = 13'd3590; +parameter ap_ST_fsm_state3592 = 13'd3591; +parameter ap_ST_fsm_state3593 = 13'd3592; +parameter ap_ST_fsm_state3594 = 13'd3593; +parameter ap_ST_fsm_state3595 = 13'd3594; +parameter ap_ST_fsm_state3596 = 13'd3595; +parameter ap_ST_fsm_state3597 = 13'd3596; +parameter ap_ST_fsm_state3598 = 13'd3597; +parameter ap_ST_fsm_state3599 = 13'd3598; +parameter ap_ST_fsm_state3600 = 13'd3599; +parameter ap_ST_fsm_state3601 = 13'd3600; +parameter ap_ST_fsm_state3602 = 13'd3601; +parameter ap_ST_fsm_state3603 = 13'd3602; +parameter ap_ST_fsm_state3604 = 13'd3603; +parameter ap_ST_fsm_state3605 = 13'd3604; +parameter ap_ST_fsm_state3606 = 13'd3605; +parameter ap_ST_fsm_state3607 = 13'd3606; +parameter ap_ST_fsm_state3608 = 13'd3607; +parameter ap_ST_fsm_state3609 = 13'd3608; +parameter ap_ST_fsm_state3610 = 13'd3609; +parameter ap_ST_fsm_state3611 = 13'd3610; +parameter ap_ST_fsm_state3612 = 13'd3611; +parameter ap_ST_fsm_state3613 = 13'd3612; +parameter ap_ST_fsm_state3614 = 13'd3613; +parameter ap_ST_fsm_state3615 = 13'd3614; +parameter ap_ST_fsm_state3616 = 13'd3615; +parameter ap_ST_fsm_state3617 = 13'd3616; +parameter ap_ST_fsm_state3618 = 13'd3617; +parameter ap_ST_fsm_state3619 = 13'd3618; +parameter ap_ST_fsm_state3620 = 13'd3619; +parameter ap_ST_fsm_state3621 = 13'd3620; +parameter ap_ST_fsm_state3622 = 13'd3621; +parameter ap_ST_fsm_state3623 = 13'd3622; +parameter ap_ST_fsm_state3624 = 13'd3623; +parameter ap_ST_fsm_state3625 = 13'd3624; +parameter ap_ST_fsm_state3626 = 13'd3625; +parameter ap_ST_fsm_state3627 = 13'd3626; +parameter ap_ST_fsm_state3628 = 13'd3627; +parameter ap_ST_fsm_state3629 = 13'd3628; +parameter ap_ST_fsm_state3630 = 13'd3629; +parameter ap_ST_fsm_state3631 = 13'd3630; +parameter ap_ST_fsm_state3632 = 13'd3631; +parameter ap_ST_fsm_state3633 = 13'd3632; +parameter ap_ST_fsm_state3634 = 13'd3633; +parameter ap_ST_fsm_state3635 = 13'd3634; +parameter ap_ST_fsm_state3636 = 13'd3635; +parameter ap_ST_fsm_state3637 = 13'd3636; +parameter ap_ST_fsm_state3638 = 13'd3637; +parameter ap_ST_fsm_state3639 = 13'd3638; +parameter ap_ST_fsm_state3640 = 13'd3639; +parameter ap_ST_fsm_state3641 = 13'd3640; +parameter ap_ST_fsm_state3642 = 13'd3641; +parameter ap_ST_fsm_state3643 = 13'd3642; +parameter ap_ST_fsm_state3644 = 13'd3643; +parameter ap_ST_fsm_state3645 = 13'd3644; +parameter ap_ST_fsm_state3646 = 13'd3645; +parameter ap_ST_fsm_state3647 = 13'd3646; +parameter ap_ST_fsm_state3648 = 13'd3647; +parameter ap_ST_fsm_state3649 = 13'd3648; +parameter ap_ST_fsm_state3650 = 13'd3649; +parameter ap_ST_fsm_state3651 = 13'd3650; +parameter ap_ST_fsm_state3652 = 13'd3651; +parameter ap_ST_fsm_state3653 = 13'd3652; +parameter ap_ST_fsm_state3654 = 13'd3653; +parameter ap_ST_fsm_state3655 = 13'd3654; +parameter ap_ST_fsm_state3656 = 13'd3655; +parameter ap_ST_fsm_state3657 = 13'd3656; +parameter ap_ST_fsm_state3658 = 13'd3657; +parameter ap_ST_fsm_state3659 = 13'd3658; +parameter ap_ST_fsm_state3660 = 13'd3659; +parameter ap_ST_fsm_state3661 = 13'd3660; +parameter ap_ST_fsm_state3662 = 13'd3661; +parameter ap_ST_fsm_state3663 = 13'd3662; +parameter ap_ST_fsm_state3664 = 13'd3663; +parameter ap_ST_fsm_state3665 = 13'd3664; +parameter ap_ST_fsm_state3666 = 13'd3665; +parameter ap_ST_fsm_state3667 = 13'd3666; +parameter ap_ST_fsm_state3668 = 13'd3667; +parameter ap_ST_fsm_state3669 = 13'd3668; +parameter ap_ST_fsm_state3670 = 13'd3669; +parameter ap_ST_fsm_state3671 = 13'd3670; +parameter ap_ST_fsm_state3672 = 13'd3671; +parameter ap_ST_fsm_state3673 = 13'd3672; +parameter ap_ST_fsm_state3674 = 13'd3673; +parameter ap_ST_fsm_state3675 = 13'd3674; +parameter ap_ST_fsm_state3676 = 13'd3675; +parameter ap_ST_fsm_state3677 = 13'd3676; +parameter ap_ST_fsm_state3678 = 13'd3677; +parameter ap_ST_fsm_state3679 = 13'd3678; +parameter ap_ST_fsm_state3680 = 13'd3679; +parameter ap_ST_fsm_state3681 = 13'd3680; +parameter ap_ST_fsm_state3682 = 13'd3681; +parameter ap_ST_fsm_state3683 = 13'd3682; +parameter ap_ST_fsm_state3684 = 13'd3683; +parameter ap_ST_fsm_state3685 = 13'd3684; +parameter ap_ST_fsm_state3686 = 13'd3685; +parameter ap_ST_fsm_state3687 = 13'd3686; +parameter ap_ST_fsm_state3688 = 13'd3687; +parameter ap_ST_fsm_state3689 = 13'd3688; +parameter ap_ST_fsm_state3690 = 13'd3689; +parameter ap_ST_fsm_state3691 = 13'd3690; +parameter ap_ST_fsm_state3692 = 13'd3691; +parameter ap_ST_fsm_state3693 = 13'd3692; +parameter ap_ST_fsm_state3694 = 13'd3693; +parameter ap_ST_fsm_state3695 = 13'd3694; +parameter ap_ST_fsm_state3696 = 13'd3695; +parameter ap_ST_fsm_state3697 = 13'd3696; +parameter ap_ST_fsm_state3698 = 13'd3697; +parameter ap_ST_fsm_state3699 = 13'd3698; +parameter ap_ST_fsm_state3700 = 13'd3699; +parameter ap_ST_fsm_state3701 = 13'd3700; +parameter ap_ST_fsm_state3702 = 13'd3701; +parameter ap_ST_fsm_state3703 = 13'd3702; +parameter ap_ST_fsm_state3704 = 13'd3703; +parameter ap_ST_fsm_state3705 = 13'd3704; +parameter ap_ST_fsm_state3706 = 13'd3705; +parameter ap_ST_fsm_state3707 = 13'd3706; +parameter ap_ST_fsm_state3708 = 13'd3707; +parameter ap_ST_fsm_state3709 = 13'd3708; +parameter ap_ST_fsm_state3710 = 13'd3709; +parameter ap_ST_fsm_state3711 = 13'd3710; +parameter ap_ST_fsm_state3712 = 13'd3711; +parameter ap_ST_fsm_state3713 = 13'd3712; +parameter ap_ST_fsm_state3714 = 13'd3713; +parameter ap_ST_fsm_state3715 = 13'd3714; +parameter ap_ST_fsm_state3716 = 13'd3715; +parameter ap_ST_fsm_state3717 = 13'd3716; +parameter ap_ST_fsm_state3718 = 13'd3717; +parameter ap_ST_fsm_state3719 = 13'd3718; +parameter ap_ST_fsm_state3720 = 13'd3719; +parameter ap_ST_fsm_state3721 = 13'd3720; +parameter ap_ST_fsm_state3722 = 13'd3721; +parameter ap_ST_fsm_state3723 = 13'd3722; +parameter ap_ST_fsm_state3724 = 13'd3723; +parameter ap_ST_fsm_state3725 = 13'd3724; +parameter ap_ST_fsm_state3726 = 13'd3725; +parameter ap_ST_fsm_state3727 = 13'd3726; +parameter ap_ST_fsm_state3728 = 13'd3727; +parameter ap_ST_fsm_state3729 = 13'd3728; +parameter ap_ST_fsm_state3730 = 13'd3729; +parameter ap_ST_fsm_state3731 = 13'd3730; +parameter ap_ST_fsm_state3732 = 13'd3731; +parameter ap_ST_fsm_state3733 = 13'd3732; +parameter ap_ST_fsm_state3734 = 13'd3733; +parameter ap_ST_fsm_state3735 = 13'd3734; +parameter ap_ST_fsm_state3736 = 13'd3735; +parameter ap_ST_fsm_state3737 = 13'd3736; +parameter ap_ST_fsm_state3738 = 13'd3737; +parameter ap_ST_fsm_state3739 = 13'd3738; +parameter ap_ST_fsm_state3740 = 13'd3739; +parameter ap_ST_fsm_state3741 = 13'd3740; +parameter ap_ST_fsm_state3742 = 13'd3741; +parameter ap_ST_fsm_state3743 = 13'd3742; +parameter ap_ST_fsm_state3744 = 13'd3743; +parameter ap_ST_fsm_state3745 = 13'd3744; +parameter ap_ST_fsm_state3746 = 13'd3745; +parameter ap_ST_fsm_state3747 = 13'd3746; +parameter ap_ST_fsm_state3748 = 13'd3747; +parameter ap_ST_fsm_state3749 = 13'd3748; +parameter ap_ST_fsm_state3750 = 13'd3749; +parameter ap_ST_fsm_state3751 = 13'd3750; +parameter ap_ST_fsm_state3752 = 13'd3751; +parameter ap_ST_fsm_state3753 = 13'd3752; +parameter ap_ST_fsm_state3754 = 13'd3753; +parameter ap_ST_fsm_state3755 = 13'd3754; +parameter ap_ST_fsm_state3756 = 13'd3755; +parameter ap_ST_fsm_state3757 = 13'd3756; +parameter ap_ST_fsm_state3758 = 13'd3757; +parameter ap_ST_fsm_state3759 = 13'd3758; +parameter ap_ST_fsm_state3760 = 13'd3759; +parameter ap_ST_fsm_state3761 = 13'd3760; +parameter ap_ST_fsm_state3762 = 13'd3761; +parameter ap_ST_fsm_state3763 = 13'd3762; +parameter ap_ST_fsm_state3764 = 13'd3763; +parameter ap_ST_fsm_state3765 = 13'd3764; +parameter ap_ST_fsm_state3766 = 13'd3765; +parameter ap_ST_fsm_state3767 = 13'd3766; +parameter ap_ST_fsm_state3768 = 13'd3767; +parameter ap_ST_fsm_state3769 = 13'd3768; +parameter ap_ST_fsm_state3770 = 13'd3769; +parameter ap_ST_fsm_state3771 = 13'd3770; +parameter ap_ST_fsm_state3772 = 13'd3771; +parameter ap_ST_fsm_state3773 = 13'd3772; +parameter ap_ST_fsm_state3774 = 13'd3773; +parameter ap_ST_fsm_state3775 = 13'd3774; +parameter ap_ST_fsm_state3776 = 13'd3775; +parameter ap_ST_fsm_state3777 = 13'd3776; +parameter ap_ST_fsm_state3778 = 13'd3777; +parameter ap_ST_fsm_state3779 = 13'd3778; +parameter ap_ST_fsm_state3780 = 13'd3779; +parameter ap_ST_fsm_state3781 = 13'd3780; +parameter ap_ST_fsm_state3782 = 13'd3781; +parameter ap_ST_fsm_state3783 = 13'd3782; +parameter ap_ST_fsm_state3784 = 13'd3783; +parameter ap_ST_fsm_state3785 = 13'd3784; +parameter ap_ST_fsm_state3786 = 13'd3785; +parameter ap_ST_fsm_state3787 = 13'd3786; +parameter ap_ST_fsm_state3788 = 13'd3787; +parameter ap_ST_fsm_state3789 = 13'd3788; +parameter ap_ST_fsm_state3790 = 13'd3789; +parameter ap_ST_fsm_state3791 = 13'd3790; +parameter ap_ST_fsm_state3792 = 13'd3791; +parameter ap_ST_fsm_state3793 = 13'd3792; +parameter ap_ST_fsm_state3794 = 13'd3793; +parameter ap_ST_fsm_state3795 = 13'd3794; +parameter ap_ST_fsm_state3796 = 13'd3795; +parameter ap_ST_fsm_state3797 = 13'd3796; +parameter ap_ST_fsm_state3798 = 13'd3797; +parameter ap_ST_fsm_state3799 = 13'd3798; +parameter ap_ST_fsm_state3800 = 13'd3799; +parameter ap_ST_fsm_state3801 = 13'd3800; +parameter ap_ST_fsm_state3802 = 13'd3801; +parameter ap_ST_fsm_state3803 = 13'd3802; +parameter ap_ST_fsm_state3804 = 13'd3803; +parameter ap_ST_fsm_state3805 = 13'd3804; +parameter ap_ST_fsm_state3806 = 13'd3805; +parameter ap_ST_fsm_state3807 = 13'd3806; +parameter ap_ST_fsm_state3808 = 13'd3807; +parameter ap_ST_fsm_state3809 = 13'd3808; +parameter ap_ST_fsm_state3810 = 13'd3809; +parameter ap_ST_fsm_state3811 = 13'd3810; +parameter ap_ST_fsm_state3812 = 13'd3811; +parameter ap_ST_fsm_state3813 = 13'd3812; +parameter ap_ST_fsm_state3814 = 13'd3813; +parameter ap_ST_fsm_state3815 = 13'd3814; +parameter ap_ST_fsm_state3816 = 13'd3815; +parameter ap_ST_fsm_state3817 = 13'd3816; +parameter ap_ST_fsm_state3818 = 13'd3817; +parameter ap_ST_fsm_state3819 = 13'd3818; +parameter ap_ST_fsm_state3820 = 13'd3819; +parameter ap_ST_fsm_state3821 = 13'd3820; +parameter ap_ST_fsm_state3822 = 13'd3821; +parameter ap_ST_fsm_state3823 = 13'd3822; +parameter ap_ST_fsm_state3824 = 13'd3823; +parameter ap_ST_fsm_state3825 = 13'd3824; +parameter ap_ST_fsm_state3826 = 13'd3825; +parameter ap_ST_fsm_state3827 = 13'd3826; +parameter ap_ST_fsm_state3828 = 13'd3827; +parameter ap_ST_fsm_state3829 = 13'd3828; +parameter ap_ST_fsm_state3830 = 13'd3829; +parameter ap_ST_fsm_state3831 = 13'd3830; +parameter ap_ST_fsm_state3832 = 13'd3831; +parameter ap_ST_fsm_state3833 = 13'd3832; +parameter ap_ST_fsm_state3834 = 13'd3833; +parameter ap_ST_fsm_state3835 = 13'd3834; +parameter ap_ST_fsm_state3836 = 13'd3835; +parameter ap_ST_fsm_state3837 = 13'd3836; +parameter ap_ST_fsm_state3838 = 13'd3837; +parameter ap_ST_fsm_state3839 = 13'd3838; +parameter ap_ST_fsm_state3840 = 13'd3839; +parameter ap_ST_fsm_state3841 = 13'd3840; +parameter ap_ST_fsm_state3842 = 13'd3841; +parameter ap_ST_fsm_state3843 = 13'd3842; +parameter ap_ST_fsm_state3844 = 13'd3843; +parameter ap_ST_fsm_state3845 = 13'd3844; +parameter ap_ST_fsm_state3846 = 13'd3845; +parameter ap_ST_fsm_state3847 = 13'd3846; +parameter ap_ST_fsm_state3848 = 13'd3847; +parameter ap_ST_fsm_state3849 = 13'd3848; +parameter ap_ST_fsm_state3850 = 13'd3849; +parameter ap_ST_fsm_state3851 = 13'd3850; +parameter ap_ST_fsm_state3852 = 13'd3851; +parameter ap_ST_fsm_state3853 = 13'd3852; +parameter ap_ST_fsm_state3854 = 13'd3853; +parameter ap_ST_fsm_state3855 = 13'd3854; +parameter ap_ST_fsm_state3856 = 13'd3855; +parameter ap_ST_fsm_state3857 = 13'd3856; +parameter ap_ST_fsm_state3858 = 13'd3857; +parameter ap_ST_fsm_state3859 = 13'd3858; +parameter ap_ST_fsm_state3860 = 13'd3859; +parameter ap_ST_fsm_state3861 = 13'd3860; +parameter ap_ST_fsm_state3862 = 13'd3861; +parameter ap_ST_fsm_state3863 = 13'd3862; +parameter ap_ST_fsm_state3864 = 13'd3863; +parameter ap_ST_fsm_state3865 = 13'd3864; +parameter ap_ST_fsm_state3866 = 13'd3865; +parameter ap_ST_fsm_state3867 = 13'd3866; +parameter ap_ST_fsm_state3868 = 13'd3867; +parameter ap_ST_fsm_state3869 = 13'd3868; +parameter ap_ST_fsm_state3870 = 13'd3869; +parameter ap_ST_fsm_state3871 = 13'd3870; +parameter ap_ST_fsm_state3872 = 13'd3871; +parameter ap_ST_fsm_state3873 = 13'd3872; +parameter ap_ST_fsm_state3874 = 13'd3873; +parameter ap_ST_fsm_state3875 = 13'd3874; +parameter ap_ST_fsm_state3876 = 13'd3875; +parameter ap_ST_fsm_state3877 = 13'd3876; +parameter ap_ST_fsm_state3878 = 13'd3877; +parameter ap_ST_fsm_state3879 = 13'd3878; +parameter ap_ST_fsm_state3880 = 13'd3879; +parameter ap_ST_fsm_state3881 = 13'd3880; +parameter ap_ST_fsm_state3882 = 13'd3881; +parameter ap_ST_fsm_state3883 = 13'd3882; +parameter ap_ST_fsm_state3884 = 13'd3883; +parameter ap_ST_fsm_state3885 = 13'd3884; +parameter ap_ST_fsm_state3886 = 13'd3885; +parameter ap_ST_fsm_state3887 = 13'd3886; +parameter ap_ST_fsm_state3888 = 13'd3887; +parameter ap_ST_fsm_state3889 = 13'd3888; +parameter ap_ST_fsm_state3890 = 13'd3889; +parameter ap_ST_fsm_state3891 = 13'd3890; +parameter ap_ST_fsm_state3892 = 13'd3891; +parameter ap_ST_fsm_state3893 = 13'd3892; +parameter ap_ST_fsm_state3894 = 13'd3893; +parameter ap_ST_fsm_state3895 = 13'd3894; +parameter ap_ST_fsm_state3896 = 13'd3895; +parameter ap_ST_fsm_state3897 = 13'd3896; +parameter ap_ST_fsm_state3898 = 13'd3897; +parameter ap_ST_fsm_state3899 = 13'd3898; +parameter ap_ST_fsm_state3900 = 13'd3899; +parameter ap_ST_fsm_state3901 = 13'd3900; +parameter ap_ST_fsm_state3902 = 13'd3901; +parameter ap_ST_fsm_state3903 = 13'd3902; +parameter ap_ST_fsm_state3904 = 13'd3903; +parameter ap_ST_fsm_state3905 = 13'd3904; +parameter ap_ST_fsm_state3906 = 13'd3905; +parameter ap_ST_fsm_state3907 = 13'd3906; +parameter ap_ST_fsm_state3908 = 13'd3907; +parameter ap_ST_fsm_state3909 = 13'd3908; +parameter ap_ST_fsm_state3910 = 13'd3909; +parameter ap_ST_fsm_state3911 = 13'd3910; +parameter ap_ST_fsm_state3912 = 13'd3911; +parameter ap_ST_fsm_state3913 = 13'd3912; +parameter ap_ST_fsm_state3914 = 13'd3913; +parameter ap_ST_fsm_state3915 = 13'd3914; +parameter ap_ST_fsm_state3916 = 13'd3915; +parameter ap_ST_fsm_state3917 = 13'd3916; +parameter ap_ST_fsm_state3918 = 13'd3917; +parameter ap_ST_fsm_state3919 = 13'd3918; +parameter ap_ST_fsm_state3920 = 13'd3919; +parameter ap_ST_fsm_state3921 = 13'd3920; +parameter ap_ST_fsm_state3922 = 13'd3921; +parameter ap_ST_fsm_state3923 = 13'd3922; +parameter ap_ST_fsm_state3924 = 13'd3923; +parameter ap_ST_fsm_state3925 = 13'd3924; +parameter ap_ST_fsm_state3926 = 13'd3925; +parameter ap_ST_fsm_state3927 = 13'd3926; +parameter ap_ST_fsm_state3928 = 13'd3927; +parameter ap_ST_fsm_state3929 = 13'd3928; +parameter ap_ST_fsm_state3930 = 13'd3929; +parameter ap_ST_fsm_state3931 = 13'd3930; +parameter ap_ST_fsm_state3932 = 13'd3931; +parameter ap_ST_fsm_state3933 = 13'd3932; +parameter ap_ST_fsm_state3934 = 13'd3933; +parameter ap_ST_fsm_state3935 = 13'd3934; +parameter ap_ST_fsm_state3936 = 13'd3935; +parameter ap_ST_fsm_state3937 = 13'd3936; +parameter ap_ST_fsm_state3938 = 13'd3937; +parameter ap_ST_fsm_state3939 = 13'd3938; +parameter ap_ST_fsm_state3940 = 13'd3939; +parameter ap_ST_fsm_state3941 = 13'd3940; +parameter ap_ST_fsm_state3942 = 13'd3941; +parameter ap_ST_fsm_state3943 = 13'd3942; +parameter ap_ST_fsm_state3944 = 13'd3943; +parameter ap_ST_fsm_state3945 = 13'd3944; +parameter ap_ST_fsm_state3946 = 13'd3945; +parameter ap_ST_fsm_state3947 = 13'd3946; +parameter ap_ST_fsm_state3948 = 13'd3947; +parameter ap_ST_fsm_state3949 = 13'd3948; +parameter ap_ST_fsm_state3950 = 13'd3949; +parameter ap_ST_fsm_state3951 = 13'd3950; +parameter ap_ST_fsm_state3952 = 13'd3951; +parameter ap_ST_fsm_state3953 = 13'd3952; +parameter ap_ST_fsm_state3954 = 13'd3953; +parameter ap_ST_fsm_state3955 = 13'd3954; +parameter ap_ST_fsm_state3956 = 13'd3955; +parameter ap_ST_fsm_state3957 = 13'd3956; +parameter ap_ST_fsm_state3958 = 13'd3957; +parameter ap_ST_fsm_state3959 = 13'd3958; +parameter ap_ST_fsm_state3960 = 13'd3959; +parameter ap_ST_fsm_state3961 = 13'd3960; +parameter ap_ST_fsm_state3962 = 13'd3961; +parameter ap_ST_fsm_state3963 = 13'd3962; +parameter ap_ST_fsm_state3964 = 13'd3963; +parameter ap_ST_fsm_state3965 = 13'd3964; +parameter ap_ST_fsm_state3966 = 13'd3965; +parameter ap_ST_fsm_state3967 = 13'd3966; +parameter ap_ST_fsm_state3968 = 13'd3967; +parameter ap_ST_fsm_state3969 = 13'd3968; +parameter ap_ST_fsm_state3970 = 13'd3969; +parameter ap_ST_fsm_state3971 = 13'd3970; +parameter ap_ST_fsm_state3972 = 13'd3971; +parameter ap_ST_fsm_state3973 = 13'd3972; +parameter ap_ST_fsm_state3974 = 13'd3973; +parameter ap_ST_fsm_state3975 = 13'd3974; +parameter ap_ST_fsm_state3976 = 13'd3975; +parameter ap_ST_fsm_state3977 = 13'd3976; +parameter ap_ST_fsm_state3978 = 13'd3977; +parameter ap_ST_fsm_state3979 = 13'd3978; +parameter ap_ST_fsm_state3980 = 13'd3979; +parameter ap_ST_fsm_state3981 = 13'd3980; +parameter ap_ST_fsm_state3982 = 13'd3981; +parameter ap_ST_fsm_state3983 = 13'd3982; +parameter ap_ST_fsm_state3984 = 13'd3983; +parameter ap_ST_fsm_state3985 = 13'd3984; +parameter ap_ST_fsm_state3986 = 13'd3985; +parameter ap_ST_fsm_state3987 = 13'd3986; +parameter ap_ST_fsm_state3988 = 13'd3987; +parameter ap_ST_fsm_state3989 = 13'd3988; +parameter ap_ST_fsm_state3990 = 13'd3989; +parameter ap_ST_fsm_state3991 = 13'd3990; +parameter ap_ST_fsm_state3992 = 13'd3991; +parameter ap_ST_fsm_state3993 = 13'd3992; +parameter ap_ST_fsm_state3994 = 13'd3993; +parameter ap_ST_fsm_state3995 = 13'd3994; +parameter ap_ST_fsm_state3996 = 13'd3995; +parameter ap_ST_fsm_state3997 = 13'd3996; +parameter ap_ST_fsm_state3998 = 13'd3997; +parameter ap_ST_fsm_state3999 = 13'd3998; +parameter ap_ST_fsm_state4000 = 13'd3999; +parameter ap_ST_fsm_state4001 = 13'd4000; +parameter ap_ST_fsm_state4002 = 13'd4001; +parameter ap_ST_fsm_state4003 = 13'd4002; +parameter ap_ST_fsm_state4004 = 13'd4003; +parameter ap_ST_fsm_state4005 = 13'd4004; +parameter ap_ST_fsm_state4006 = 13'd4005; +parameter ap_ST_fsm_state4007 = 13'd4006; +parameter ap_ST_fsm_state4008 = 13'd4007; +parameter ap_ST_fsm_state4009 = 13'd4008; +parameter ap_ST_fsm_state4010 = 13'd4009; +parameter ap_ST_fsm_state4011 = 13'd4010; +parameter ap_ST_fsm_state4012 = 13'd4011; +parameter ap_ST_fsm_state4013 = 13'd4012; +parameter ap_ST_fsm_state4014 = 13'd4013; +parameter ap_ST_fsm_state4015 = 13'd4014; +parameter ap_ST_fsm_state4016 = 13'd4015; +parameter ap_ST_fsm_state4017 = 13'd4016; +parameter ap_ST_fsm_state4018 = 13'd4017; +parameter ap_ST_fsm_state4019 = 13'd4018; +parameter ap_ST_fsm_state4020 = 13'd4019; +parameter ap_ST_fsm_state4021 = 13'd4020; +parameter ap_ST_fsm_state4022 = 13'd4021; +parameter ap_ST_fsm_state4023 = 13'd4022; +parameter ap_ST_fsm_state4024 = 13'd4023; +parameter ap_ST_fsm_state4025 = 13'd4024; +parameter ap_ST_fsm_state4026 = 13'd4025; +parameter ap_ST_fsm_state4027 = 13'd4026; +parameter ap_ST_fsm_state4028 = 13'd4027; +parameter ap_ST_fsm_state4029 = 13'd4028; +parameter ap_ST_fsm_state4030 = 13'd4029; +parameter ap_ST_fsm_state4031 = 13'd4030; +parameter ap_ST_fsm_state4032 = 13'd4031; +parameter ap_ST_fsm_state4033 = 13'd4032; +parameter ap_ST_fsm_state4034 = 13'd4033; +parameter ap_ST_fsm_state4035 = 13'd4034; +parameter ap_ST_fsm_state4036 = 13'd4035; +parameter ap_ST_fsm_state4037 = 13'd4036; +parameter ap_ST_fsm_state4038 = 13'd4037; +parameter ap_ST_fsm_state4039 = 13'd4038; +parameter ap_ST_fsm_state4040 = 13'd4039; +parameter ap_ST_fsm_state4041 = 13'd4040; +parameter ap_ST_fsm_state4042 = 13'd4041; +parameter ap_ST_fsm_state4043 = 13'd4042; +parameter ap_ST_fsm_state4044 = 13'd4043; +parameter ap_ST_fsm_state4045 = 13'd4044; +parameter ap_ST_fsm_state4046 = 13'd4045; +parameter ap_ST_fsm_state4047 = 13'd4046; +parameter ap_ST_fsm_state4048 = 13'd4047; +parameter ap_ST_fsm_state4049 = 13'd4048; +parameter ap_ST_fsm_state4050 = 13'd4049; +parameter ap_ST_fsm_state4051 = 13'd4050; +parameter ap_ST_fsm_state4052 = 13'd4051; +parameter ap_ST_fsm_state4053 = 13'd4052; +parameter ap_ST_fsm_state4054 = 13'd4053; +parameter ap_ST_fsm_state4055 = 13'd4054; +parameter ap_ST_fsm_state4056 = 13'd4055; +parameter ap_ST_fsm_state4057 = 13'd4056; +parameter ap_ST_fsm_state4058 = 13'd4057; +parameter ap_ST_fsm_state4059 = 13'd4058; +parameter ap_ST_fsm_state4060 = 13'd4059; +parameter ap_ST_fsm_state4061 = 13'd4060; +parameter ap_ST_fsm_state4062 = 13'd4061; +parameter ap_ST_fsm_state4063 = 13'd4062; +parameter ap_ST_fsm_state4064 = 13'd4063; +parameter ap_ST_fsm_state4065 = 13'd4064; +parameter ap_ST_fsm_state4066 = 13'd4065; +parameter ap_ST_fsm_state4067 = 13'd4066; +parameter ap_ST_fsm_state4068 = 13'd4067; +parameter ap_ST_fsm_state4069 = 13'd4068; +parameter ap_ST_fsm_state4070 = 13'd4069; +parameter ap_ST_fsm_state4071 = 13'd4070; +parameter ap_ST_fsm_state4072 = 13'd4071; +parameter ap_ST_fsm_state4073 = 13'd4072; +parameter ap_ST_fsm_state4074 = 13'd4073; +parameter ap_ST_fsm_state4075 = 13'd4074; +parameter ap_ST_fsm_state4076 = 13'd4075; +parameter ap_ST_fsm_state4077 = 13'd4076; +parameter ap_ST_fsm_state4078 = 13'd4077; +parameter ap_ST_fsm_state4079 = 13'd4078; +parameter ap_ST_fsm_state4080 = 13'd4079; +parameter ap_ST_fsm_state4081 = 13'd4080; +parameter ap_ST_fsm_state4082 = 13'd4081; +parameter ap_ST_fsm_state4083 = 13'd4082; +parameter ap_ST_fsm_state4084 = 13'd4083; +parameter ap_ST_fsm_state4085 = 13'd4084; +parameter ap_ST_fsm_state4086 = 13'd4085; +parameter ap_ST_fsm_state4087 = 13'd4086; +parameter ap_ST_fsm_state4088 = 13'd4087; +parameter ap_ST_fsm_state4089 = 13'd4088; +parameter ap_ST_fsm_state4090 = 13'd4089; +parameter ap_ST_fsm_state4091 = 13'd4090; +parameter ap_ST_fsm_state4092 = 13'd4091; +parameter ap_ST_fsm_state4093 = 13'd4092; +parameter ap_ST_fsm_state4094 = 13'd4093; +parameter ap_ST_fsm_state4095 = 13'd4094; +parameter ap_ST_fsm_state4096 = 13'd4095; +parameter ap_ST_fsm_state4097 = 13'd4096; +parameter ap_ST_fsm_state4098 = 13'd4097; +parameter ap_ST_fsm_state4099 = 13'd4098; +parameter ap_ST_fsm_state4100 = 13'd4099; +parameter ap_ST_fsm_state4101 = 13'd4100; +parameter ap_ST_fsm_state4102 = 13'd4101; +parameter ap_ST_fsm_state4103 = 13'd4102; +parameter ap_ST_fsm_state4104 = 13'd4103; +parameter ap_ST_fsm_state4105 = 13'd4104; +parameter ap_ST_fsm_state4106 = 13'd4105; +parameter ap_ST_fsm_state4107 = 13'd4106; +parameter ap_ST_fsm_state4108 = 13'd4107; +parameter ap_ST_fsm_state4109 = 13'd4108; +parameter ap_ST_fsm_state4110 = 13'd4109; +parameter ap_ST_fsm_state4111 = 13'd4110; +parameter ap_ST_fsm_state4112 = 13'd4111; +parameter ap_ST_fsm_state4113 = 13'd4112; +parameter ap_ST_fsm_state4114 = 13'd4113; +parameter ap_ST_fsm_state4115 = 13'd4114; +parameter ap_ST_fsm_state4116 = 13'd4115; +parameter ap_ST_fsm_state4117 = 13'd4116; +parameter ap_ST_fsm_state4118 = 13'd4117; +parameter ap_ST_fsm_state4119 = 13'd4118; +parameter ap_ST_fsm_state4120 = 13'd4119; +parameter ap_ST_fsm_state4121 = 13'd4120; +parameter ap_ST_fsm_state4122 = 13'd4121; +parameter ap_ST_fsm_state4123 = 13'd4122; +parameter ap_ST_fsm_state4124 = 13'd4123; +parameter ap_ST_fsm_state4125 = 13'd4124; +parameter ap_ST_fsm_state4126 = 13'd4125; +parameter ap_ST_fsm_state4127 = 13'd4126; +parameter ap_ST_fsm_state4128 = 13'd4127; +parameter ap_ST_fsm_state4129 = 13'd4128; +parameter ap_ST_fsm_state4130 = 13'd4129; +parameter ap_ST_fsm_state4131 = 13'd4130; +parameter ap_ST_fsm_state4132 = 13'd4131; +parameter ap_ST_fsm_state4133 = 13'd4132; +parameter ap_ST_fsm_state4134 = 13'd4133; +parameter ap_ST_fsm_state4135 = 13'd4134; +parameter ap_ST_fsm_state4136 = 13'd4135; +parameter ap_ST_fsm_state4137 = 13'd4136; +parameter ap_ST_fsm_state4138 = 13'd4137; +parameter ap_ST_fsm_state4139 = 13'd4138; +parameter ap_ST_fsm_state4140 = 13'd4139; +parameter ap_ST_fsm_state4141 = 13'd4140; +parameter ap_ST_fsm_state4142 = 13'd4141; +parameter ap_ST_fsm_state4143 = 13'd4142; +parameter ap_ST_fsm_state4144 = 13'd4143; +parameter ap_ST_fsm_state4145 = 13'd4144; +parameter ap_ST_fsm_state4146 = 13'd4145; +parameter ap_ST_fsm_state4147 = 13'd4146; +parameter ap_ST_fsm_state4148 = 13'd4147; +parameter ap_ST_fsm_state4149 = 13'd4148; +parameter ap_ST_fsm_state4150 = 13'd4149; +parameter ap_ST_fsm_state4151 = 13'd4150; +parameter ap_ST_fsm_state4152 = 13'd4151; +parameter ap_ST_fsm_state4153 = 13'd4152; +parameter ap_ST_fsm_state4154 = 13'd4153; +parameter ap_ST_fsm_state4155 = 13'd4154; +parameter ap_ST_fsm_state4156 = 13'd4155; +parameter ap_ST_fsm_state4157 = 13'd4156; +parameter ap_ST_fsm_state4158 = 13'd4157; +parameter ap_ST_fsm_state4159 = 13'd4158; +parameter ap_ST_fsm_state4160 = 13'd4159; +parameter ap_ST_fsm_state4161 = 13'd4160; +parameter ap_ST_fsm_state4162 = 13'd4161; +parameter ap_ST_fsm_state4163 = 13'd4162; +parameter ap_ST_fsm_state4164 = 13'd4163; +parameter ap_ST_fsm_state4165 = 13'd4164; +parameter ap_ST_fsm_state4166 = 13'd4165; +parameter ap_ST_fsm_state4167 = 13'd4166; +parameter ap_ST_fsm_state4168 = 13'd4167; +parameter ap_ST_fsm_state4169 = 13'd4168; +parameter ap_ST_fsm_state4170 = 13'd4169; +parameter ap_ST_fsm_state4171 = 13'd4170; +parameter ap_ST_fsm_state4172 = 13'd4171; +parameter ap_ST_fsm_state4173 = 13'd4172; +parameter ap_ST_fsm_state4174 = 13'd4173; +parameter ap_ST_fsm_state4175 = 13'd4174; +parameter ap_ST_fsm_state4176 = 13'd4175; +parameter ap_ST_fsm_state4177 = 13'd4176; +parameter ap_ST_fsm_state4178 = 13'd4177; +parameter ap_ST_fsm_state4179 = 13'd4178; +parameter ap_ST_fsm_state4180 = 13'd4179; +parameter ap_ST_fsm_state4181 = 13'd4180; +parameter ap_ST_fsm_state4182 = 13'd4181; +parameter ap_ST_fsm_state4183 = 13'd4182; +parameter ap_ST_fsm_state4184 = 13'd4183; +parameter ap_ST_fsm_state4185 = 13'd4184; +parameter ap_ST_fsm_state4186 = 13'd4185; +parameter ap_ST_fsm_state4187 = 13'd4186; +parameter ap_ST_fsm_state4188 = 13'd4187; +parameter ap_ST_fsm_state4189 = 13'd4188; +parameter ap_ST_fsm_state4190 = 13'd4189; +parameter ap_ST_fsm_state4191 = 13'd4190; +parameter ap_ST_fsm_state4192 = 13'd4191; +parameter ap_ST_fsm_state4193 = 13'd4192; +parameter ap_ST_fsm_state4194 = 13'd4193; +parameter ap_ST_fsm_state4195 = 13'd4194; +parameter ap_ST_fsm_state4196 = 13'd4195; +parameter ap_ST_fsm_state4197 = 13'd4196; +parameter ap_ST_fsm_state4198 = 13'd4197; +parameter ap_ST_fsm_state4199 = 13'd4198; +parameter ap_ST_fsm_state4200 = 13'd4199; +parameter ap_ST_fsm_state4201 = 13'd4200; +parameter ap_ST_fsm_state4202 = 13'd4201; +parameter ap_ST_fsm_state4203 = 13'd4202; +parameter ap_ST_fsm_state4204 = 13'd4203; +parameter ap_ST_fsm_state4205 = 13'd4204; +parameter ap_ST_fsm_state4206 = 13'd4205; +parameter ap_ST_fsm_state4207 = 13'd4206; +parameter ap_ST_fsm_state4208 = 13'd4207; +parameter ap_ST_fsm_state4209 = 13'd4208; +parameter ap_ST_fsm_state4210 = 13'd4209; +parameter ap_ST_fsm_state4211 = 13'd4210; +parameter ap_ST_fsm_state4212 = 13'd4211; +parameter ap_ST_fsm_state4213 = 13'd4212; +parameter ap_ST_fsm_state4214 = 13'd4213; +parameter ap_ST_fsm_state4215 = 13'd4214; +parameter ap_ST_fsm_state4216 = 13'd4215; +parameter ap_ST_fsm_state4217 = 13'd4216; +parameter ap_ST_fsm_state4218 = 13'd4217; +parameter ap_ST_fsm_state4219 = 13'd4218; +parameter ap_ST_fsm_state4220 = 13'd4219; +parameter ap_ST_fsm_state4221 = 13'd4220; +parameter ap_ST_fsm_state4222 = 13'd4221; +parameter ap_ST_fsm_state4223 = 13'd4222; +parameter ap_ST_fsm_state4224 = 13'd4223; +parameter ap_ST_fsm_state4225 = 13'd4224; +parameter ap_ST_fsm_state4226 = 13'd4225; +parameter ap_ST_fsm_state4227 = 13'd4226; +parameter ap_ST_fsm_state4228 = 13'd4227; +parameter ap_ST_fsm_state4229 = 13'd4228; +parameter ap_ST_fsm_state4230 = 13'd4229; +parameter ap_ST_fsm_state4231 = 13'd4230; +parameter ap_ST_fsm_state4232 = 13'd4231; +parameter ap_ST_fsm_state4233 = 13'd4232; +parameter ap_ST_fsm_state4234 = 13'd4233; +parameter ap_ST_fsm_state4235 = 13'd4234; +parameter ap_ST_fsm_state4236 = 13'd4235; +parameter ap_ST_fsm_state4237 = 13'd4236; +parameter ap_ST_fsm_state4238 = 13'd4237; +parameter ap_ST_fsm_state4239 = 13'd4238; +parameter ap_ST_fsm_state4240 = 13'd4239; +parameter ap_ST_fsm_state4241 = 13'd4240; +parameter ap_ST_fsm_state4242 = 13'd4241; +parameter ap_ST_fsm_state4243 = 13'd4242; +parameter ap_ST_fsm_state4244 = 13'd4243; +parameter ap_ST_fsm_state4245 = 13'd4244; +parameter ap_ST_fsm_state4246 = 13'd4245; +parameter ap_ST_fsm_state4247 = 13'd4246; +parameter ap_ST_fsm_state4248 = 13'd4247; +parameter ap_ST_fsm_state4249 = 13'd4248; +parameter ap_ST_fsm_state4250 = 13'd4249; +parameter ap_ST_fsm_state4251 = 13'd4250; +parameter ap_ST_fsm_state4252 = 13'd4251; +parameter ap_ST_fsm_state4253 = 13'd4252; +parameter ap_ST_fsm_state4254 = 13'd4253; +parameter ap_ST_fsm_state4255 = 13'd4254; +parameter ap_ST_fsm_state4256 = 13'd4255; +parameter ap_ST_fsm_state4257 = 13'd4256; +parameter ap_ST_fsm_state4258 = 13'd4257; +parameter ap_ST_fsm_state4259 = 13'd4258; +parameter ap_ST_fsm_state4260 = 13'd4259; +parameter ap_ST_fsm_state4261 = 13'd4260; +parameter ap_ST_fsm_state4262 = 13'd4261; +parameter ap_ST_fsm_state4263 = 13'd4262; +parameter ap_ST_fsm_state4264 = 13'd4263; +parameter ap_ST_fsm_state4265 = 13'd4264; +parameter ap_ST_fsm_state4266 = 13'd4265; +parameter ap_ST_fsm_state4267 = 13'd4266; +parameter ap_ST_fsm_state4268 = 13'd4267; +parameter ap_ST_fsm_state4269 = 13'd4268; +parameter ap_ST_fsm_state4270 = 13'd4269; +parameter ap_ST_fsm_state4271 = 13'd4270; +parameter ap_ST_fsm_state4272 = 13'd4271; +parameter ap_ST_fsm_state4273 = 13'd4272; +parameter ap_ST_fsm_state4274 = 13'd4273; +parameter ap_ST_fsm_state4275 = 13'd4274; +parameter ap_ST_fsm_state4276 = 13'd4275; +parameter ap_ST_fsm_state4277 = 13'd4276; +parameter ap_ST_fsm_state4278 = 13'd4277; +parameter ap_ST_fsm_state4279 = 13'd4278; +parameter ap_ST_fsm_state4280 = 13'd4279; +parameter ap_ST_fsm_state4281 = 13'd4280; +parameter ap_ST_fsm_state4282 = 13'd4281; +parameter ap_ST_fsm_state4283 = 13'd4282; +parameter ap_ST_fsm_state4284 = 13'd4283; +parameter ap_ST_fsm_state4285 = 13'd4284; +parameter ap_ST_fsm_state4286 = 13'd4285; +parameter ap_ST_fsm_state4287 = 13'd4286; +parameter ap_ST_fsm_state4288 = 13'd4287; +parameter ap_ST_fsm_state4289 = 13'd4288; +parameter ap_ST_fsm_state4290 = 13'd4289; +parameter ap_ST_fsm_state4291 = 13'd4290; +parameter ap_ST_fsm_state4292 = 13'd4291; +parameter ap_ST_fsm_state4293 = 13'd4292; +parameter ap_ST_fsm_state4294 = 13'd4293; +parameter ap_ST_fsm_state4295 = 13'd4294; +parameter ap_ST_fsm_state4296 = 13'd4295; +parameter ap_ST_fsm_state4297 = 13'd4296; +parameter ap_ST_fsm_state4298 = 13'd4297; +parameter ap_ST_fsm_state4299 = 13'd4298; +parameter ap_ST_fsm_state4300 = 13'd4299; +parameter ap_ST_fsm_state4301 = 13'd4300; +parameter ap_ST_fsm_state4302 = 13'd4301; +parameter ap_ST_fsm_state4303 = 13'd4302; +parameter ap_ST_fsm_state4304 = 13'd4303; +parameter ap_ST_fsm_state4305 = 13'd4304; +parameter ap_ST_fsm_state4306 = 13'd4305; +parameter ap_ST_fsm_state4307 = 13'd4306; +parameter ap_ST_fsm_state4308 = 13'd4307; +parameter ap_ST_fsm_state4309 = 13'd4308; +parameter ap_ST_fsm_state4310 = 13'd4309; +parameter ap_ST_fsm_state4311 = 13'd4310; +parameter ap_ST_fsm_state4312 = 13'd4311; +parameter ap_ST_fsm_state4313 = 13'd4312; +parameter ap_ST_fsm_state4314 = 13'd4313; +parameter ap_ST_fsm_state4315 = 13'd4314; +parameter ap_ST_fsm_state4316 = 13'd4315; +parameter ap_ST_fsm_state4317 = 13'd4316; +parameter ap_ST_fsm_state4318 = 13'd4317; +parameter ap_ST_fsm_state4319 = 13'd4318; +parameter ap_ST_fsm_state4320 = 13'd4319; +parameter ap_ST_fsm_state4321 = 13'd4320; +parameter ap_ST_fsm_state4322 = 13'd4321; +parameter ap_ST_fsm_state4323 = 13'd4322; +parameter ap_ST_fsm_state4324 = 13'd4323; +parameter ap_ST_fsm_state4325 = 13'd4324; +parameter ap_ST_fsm_state4326 = 13'd4325; +parameter ap_ST_fsm_state4327 = 13'd4326; +parameter ap_ST_fsm_state4328 = 13'd4327; +parameter ap_ST_fsm_state4329 = 13'd4328; +parameter ap_ST_fsm_state4330 = 13'd4329; +parameter ap_ST_fsm_state4331 = 13'd4330; +parameter ap_ST_fsm_state4332 = 13'd4331; +parameter ap_ST_fsm_state4333 = 13'd4332; +parameter ap_ST_fsm_state4334 = 13'd4333; +parameter ap_ST_fsm_state4335 = 13'd4334; +parameter ap_ST_fsm_state4336 = 13'd4335; +parameter ap_ST_fsm_state4337 = 13'd4336; +parameter ap_ST_fsm_state4338 = 13'd4337; +parameter ap_ST_fsm_state4339 = 13'd4338; +parameter ap_ST_fsm_state4340 = 13'd4339; +parameter ap_ST_fsm_state4341 = 13'd4340; +parameter ap_ST_fsm_state4342 = 13'd4341; +parameter ap_ST_fsm_state4343 = 13'd4342; +parameter ap_ST_fsm_state4344 = 13'd4343; +parameter ap_ST_fsm_state4345 = 13'd4344; +parameter ap_ST_fsm_state4346 = 13'd4345; +parameter ap_ST_fsm_state4347 = 13'd4346; +parameter ap_ST_fsm_state4348 = 13'd4347; +parameter ap_ST_fsm_state4349 = 13'd4348; +parameter ap_ST_fsm_state4350 = 13'd4349; +parameter ap_ST_fsm_state4351 = 13'd4350; +parameter ap_ST_fsm_state4352 = 13'd4351; +parameter ap_ST_fsm_state4353 = 13'd4352; +parameter ap_ST_fsm_state4354 = 13'd4353; +parameter ap_ST_fsm_state4355 = 13'd4354; +parameter ap_ST_fsm_state4356 = 13'd4355; +parameter ap_ST_fsm_state4357 = 13'd4356; +parameter ap_ST_fsm_state4358 = 13'd4357; +parameter ap_ST_fsm_state4359 = 13'd4358; +parameter ap_ST_fsm_state4360 = 13'd4359; +parameter ap_ST_fsm_state4361 = 13'd4360; +parameter ap_ST_fsm_state4362 = 13'd4361; +parameter ap_ST_fsm_state4363 = 13'd4362; +parameter ap_ST_fsm_state4364 = 13'd4363; +parameter ap_ST_fsm_state4365 = 13'd4364; +parameter ap_ST_fsm_state4366 = 13'd4365; +parameter ap_ST_fsm_state4367 = 13'd4366; +parameter ap_ST_fsm_state4368 = 13'd4367; +parameter ap_ST_fsm_state4369 = 13'd4368; +parameter ap_ST_fsm_state4370 = 13'd4369; +parameter ap_ST_fsm_state4371 = 13'd4370; +parameter ap_ST_fsm_state4372 = 13'd4371; +parameter ap_ST_fsm_state4373 = 13'd4372; +parameter ap_ST_fsm_state4374 = 13'd4373; +parameter ap_ST_fsm_state4375 = 13'd4374; +parameter ap_ST_fsm_state4376 = 13'd4375; +parameter ap_ST_fsm_state4377 = 13'd4376; +parameter ap_ST_fsm_state4378 = 13'd4377; +parameter ap_ST_fsm_state4379 = 13'd4378; +parameter ap_ST_fsm_state4380 = 13'd4379; +parameter ap_ST_fsm_state4381 = 13'd4380; +parameter ap_ST_fsm_state4382 = 13'd4381; +parameter ap_ST_fsm_state4383 = 13'd4382; +parameter ap_ST_fsm_state4384 = 13'd4383; +parameter ap_ST_fsm_state4385 = 13'd4384; +parameter ap_ST_fsm_state4386 = 13'd4385; +parameter ap_ST_fsm_state4387 = 13'd4386; +parameter ap_ST_fsm_state4388 = 13'd4387; +parameter ap_ST_fsm_state4389 = 13'd4388; +parameter ap_ST_fsm_state4390 = 13'd4389; +parameter ap_ST_fsm_state4391 = 13'd4390; +parameter ap_ST_fsm_state4392 = 13'd4391; +parameter ap_ST_fsm_state4393 = 13'd4392; +parameter ap_ST_fsm_state4394 = 13'd4393; +parameter ap_ST_fsm_state4395 = 13'd4394; +parameter ap_ST_fsm_state4396 = 13'd4395; +parameter ap_ST_fsm_state4397 = 13'd4396; +parameter ap_ST_fsm_state4398 = 13'd4397; +parameter ap_ST_fsm_state4399 = 13'd4398; +parameter ap_ST_fsm_state4400 = 13'd4399; +parameter ap_ST_fsm_state4401 = 13'd4400; +parameter ap_ST_fsm_state4402 = 13'd4401; +parameter ap_ST_fsm_state4403 = 13'd4402; +parameter ap_ST_fsm_state4404 = 13'd4403; +parameter ap_ST_fsm_state4405 = 13'd4404; +parameter ap_ST_fsm_state4406 = 13'd4405; +parameter ap_ST_fsm_state4407 = 13'd4406; +parameter ap_ST_fsm_state4408 = 13'd4407; +parameter ap_ST_fsm_state4409 = 13'd4408; +parameter ap_ST_fsm_state4410 = 13'd4409; +parameter ap_ST_fsm_state4411 = 13'd4410; +parameter ap_ST_fsm_state4412 = 13'd4411; +parameter ap_ST_fsm_state4413 = 13'd4412; +parameter ap_ST_fsm_state4414 = 13'd4413; +parameter ap_ST_fsm_state4415 = 13'd4414; +parameter ap_ST_fsm_state4416 = 13'd4415; +parameter ap_ST_fsm_state4417 = 13'd4416; +parameter ap_ST_fsm_state4418 = 13'd4417; +parameter ap_ST_fsm_state4419 = 13'd4418; +parameter ap_ST_fsm_state4420 = 13'd4419; +parameter ap_ST_fsm_state4421 = 13'd4420; +parameter ap_ST_fsm_state4422 = 13'd4421; +parameter ap_ST_fsm_state4423 = 13'd4422; +parameter ap_ST_fsm_state4424 = 13'd4423; +parameter ap_ST_fsm_state4425 = 13'd4424; +parameter ap_ST_fsm_state4426 = 13'd4425; +parameter ap_ST_fsm_state4427 = 13'd4426; +parameter ap_ST_fsm_state4428 = 13'd4427; +parameter ap_ST_fsm_state4429 = 13'd4428; +parameter ap_ST_fsm_state4430 = 13'd4429; +parameter ap_ST_fsm_state4431 = 13'd4430; +parameter ap_ST_fsm_state4432 = 13'd4431; +parameter ap_ST_fsm_state4433 = 13'd4432; +parameter ap_ST_fsm_state4434 = 13'd4433; +parameter ap_ST_fsm_state4435 = 13'd4434; +parameter ap_ST_fsm_state4436 = 13'd4435; +parameter ap_ST_fsm_state4437 = 13'd4436; +parameter ap_ST_fsm_state4438 = 13'd4437; +parameter ap_ST_fsm_state4439 = 13'd4438; +parameter ap_ST_fsm_state4440 = 13'd4439; +parameter ap_ST_fsm_state4441 = 13'd4440; +parameter ap_ST_fsm_state4442 = 13'd4441; +parameter ap_ST_fsm_state4443 = 13'd4442; +parameter ap_ST_fsm_state4444 = 13'd4443; +parameter ap_ST_fsm_state4445 = 13'd4444; +parameter ap_ST_fsm_state4446 = 13'd4445; +parameter ap_ST_fsm_state4447 = 13'd4446; +parameter ap_ST_fsm_state4448 = 13'd4447; +parameter ap_ST_fsm_state4449 = 13'd4448; +parameter ap_ST_fsm_state4450 = 13'd4449; +parameter ap_ST_fsm_state4451 = 13'd4450; +parameter ap_ST_fsm_state4452 = 13'd4451; +parameter ap_ST_fsm_state4453 = 13'd4452; +parameter ap_ST_fsm_state4454 = 13'd4453; +parameter ap_ST_fsm_state4455 = 13'd4454; +parameter ap_ST_fsm_state4456 = 13'd4455; +parameter ap_ST_fsm_state4457 = 13'd4456; +parameter ap_ST_fsm_state4458 = 13'd4457; +parameter ap_ST_fsm_state4459 = 13'd4458; +parameter ap_ST_fsm_state4460 = 13'd4459; +parameter ap_ST_fsm_state4461 = 13'd4460; +parameter ap_ST_fsm_state4462 = 13'd4461; +parameter ap_ST_fsm_state4463 = 13'd4462; +parameter ap_ST_fsm_state4464 = 13'd4463; +parameter ap_ST_fsm_state4465 = 13'd4464; +parameter ap_ST_fsm_state4466 = 13'd4465; +parameter ap_ST_fsm_state4467 = 13'd4466; +parameter ap_ST_fsm_state4468 = 13'd4467; +parameter ap_ST_fsm_state4469 = 13'd4468; +parameter ap_ST_fsm_state4470 = 13'd4469; +parameter ap_ST_fsm_state4471 = 13'd4470; +parameter ap_ST_fsm_state4472 = 13'd4471; +parameter ap_ST_fsm_state4473 = 13'd4472; +parameter ap_ST_fsm_state4474 = 13'd4473; +parameter ap_ST_fsm_state4475 = 13'd4474; +parameter ap_ST_fsm_state4476 = 13'd4475; +parameter ap_ST_fsm_state4477 = 13'd4476; +parameter ap_ST_fsm_state4478 = 13'd4477; +parameter ap_ST_fsm_state4479 = 13'd4478; +parameter ap_ST_fsm_state4480 = 13'd4479; +parameter ap_ST_fsm_state4481 = 13'd4480; +parameter ap_ST_fsm_state4482 = 13'd4481; +parameter ap_ST_fsm_state4483 = 13'd4482; +parameter ap_ST_fsm_state4484 = 13'd4483; +parameter ap_ST_fsm_state4485 = 13'd4484; +parameter ap_ST_fsm_state4486 = 13'd4485; +parameter ap_ST_fsm_state4487 = 13'd4486; +parameter ap_ST_fsm_state4488 = 13'd4487; +parameter ap_ST_fsm_state4489 = 13'd4488; +parameter ap_ST_fsm_state4490 = 13'd4489; +parameter ap_ST_fsm_state4491 = 13'd4490; +parameter ap_ST_fsm_state4492 = 13'd4491; +parameter ap_ST_fsm_state4493 = 13'd4492; +parameter ap_ST_fsm_state4494 = 13'd4493; +parameter ap_ST_fsm_state4495 = 13'd4494; +parameter ap_ST_fsm_state4496 = 13'd4495; +parameter ap_ST_fsm_state4497 = 13'd4496; +parameter ap_ST_fsm_state4498 = 13'd4497; +parameter ap_ST_fsm_state4499 = 13'd4498; +parameter ap_ST_fsm_state4500 = 13'd4499; +parameter ap_ST_fsm_state4501 = 13'd4500; +parameter ap_ST_fsm_state4502 = 13'd4501; +parameter ap_ST_fsm_state4503 = 13'd4502; +parameter ap_ST_fsm_state4504 = 13'd4503; +parameter ap_ST_fsm_state4505 = 13'd4504; +parameter ap_ST_fsm_state4506 = 13'd4505; +parameter ap_ST_fsm_state4507 = 13'd4506; +parameter ap_ST_fsm_state4508 = 13'd4507; +parameter ap_ST_fsm_state4509 = 13'd4508; +parameter ap_ST_fsm_state4510 = 13'd4509; +parameter ap_ST_fsm_state4511 = 13'd4510; +parameter ap_ST_fsm_state4512 = 13'd4511; +parameter ap_ST_fsm_state4513 = 13'd4512; +parameter ap_ST_fsm_state4514 = 13'd4513; +parameter ap_ST_fsm_state4515 = 13'd4514; +parameter ap_ST_fsm_state4516 = 13'd4515; +parameter ap_ST_fsm_state4517 = 13'd4516; +parameter ap_ST_fsm_state4518 = 13'd4517; +parameter ap_ST_fsm_state4519 = 13'd4518; +parameter ap_ST_fsm_state4520 = 13'd4519; +parameter ap_ST_fsm_state4521 = 13'd4520; +parameter ap_ST_fsm_state4522 = 13'd4521; +parameter ap_ST_fsm_state4523 = 13'd4522; +parameter ap_ST_fsm_state4524 = 13'd4523; +parameter ap_ST_fsm_state4525 = 13'd4524; +parameter ap_ST_fsm_state4526 = 13'd4525; +parameter ap_ST_fsm_state4527 = 13'd4526; +parameter ap_ST_fsm_state4528 = 13'd4527; +parameter ap_ST_fsm_state4529 = 13'd4528; +parameter ap_ST_fsm_state4530 = 13'd4529; +parameter ap_ST_fsm_state4531 = 13'd4530; +parameter ap_ST_fsm_state4532 = 13'd4531; +parameter ap_ST_fsm_state4533 = 13'd4532; +parameter ap_ST_fsm_state4534 = 13'd4533; +parameter ap_ST_fsm_state4535 = 13'd4534; +parameter ap_ST_fsm_state4536 = 13'd4535; +parameter ap_ST_fsm_state4537 = 13'd4536; +parameter ap_ST_fsm_state4538 = 13'd4537; +parameter ap_ST_fsm_state4539 = 13'd4538; +parameter ap_ST_fsm_state4540 = 13'd4539; +parameter ap_ST_fsm_state4541 = 13'd4540; +parameter ap_ST_fsm_state4542 = 13'd4541; +parameter ap_ST_fsm_state4543 = 13'd4542; +parameter ap_ST_fsm_state4544 = 13'd4543; +parameter ap_ST_fsm_state4545 = 13'd4544; +parameter ap_ST_fsm_state4546 = 13'd4545; +parameter ap_ST_fsm_state4547 = 13'd4546; +parameter ap_ST_fsm_state4548 = 13'd4547; +parameter ap_ST_fsm_state4549 = 13'd4548; +parameter ap_ST_fsm_state4550 = 13'd4549; +parameter ap_ST_fsm_state4551 = 13'd4550; +parameter ap_ST_fsm_state4552 = 13'd4551; +parameter ap_ST_fsm_state4553 = 13'd4552; +parameter ap_ST_fsm_state4554 = 13'd4553; +parameter ap_ST_fsm_state4555 = 13'd4554; +parameter ap_ST_fsm_state4556 = 13'd4555; +parameter ap_ST_fsm_state4557 = 13'd4556; +parameter ap_ST_fsm_state4558 = 13'd4557; +parameter ap_ST_fsm_state4559 = 13'd4558; +parameter ap_ST_fsm_state4560 = 13'd4559; +parameter ap_ST_fsm_state4561 = 13'd4560; +parameter ap_ST_fsm_state4562 = 13'd4561; +parameter ap_ST_fsm_state4563 = 13'd4562; +parameter ap_ST_fsm_state4564 = 13'd4563; +parameter ap_ST_fsm_state4565 = 13'd4564; +parameter ap_ST_fsm_state4566 = 13'd4565; +parameter ap_ST_fsm_state4567 = 13'd4566; +parameter ap_ST_fsm_state4568 = 13'd4567; +parameter ap_ST_fsm_state4569 = 13'd4568; +parameter ap_ST_fsm_state4570 = 13'd4569; +parameter ap_ST_fsm_state4571 = 13'd4570; +parameter ap_ST_fsm_state4572 = 13'd4571; +parameter ap_ST_fsm_state4573 = 13'd4572; +parameter ap_ST_fsm_state4574 = 13'd4573; +parameter ap_ST_fsm_state4575 = 13'd4574; +parameter ap_ST_fsm_state4576 = 13'd4575; +parameter ap_ST_fsm_state4577 = 13'd4576; +parameter ap_ST_fsm_state4578 = 13'd4577; +parameter ap_ST_fsm_state4579 = 13'd4578; +parameter ap_ST_fsm_state4580 = 13'd4579; +parameter ap_ST_fsm_state4581 = 13'd4580; +parameter ap_ST_fsm_state4582 = 13'd4581; +parameter ap_ST_fsm_state4583 = 13'd4582; +parameter ap_ST_fsm_state4584 = 13'd4583; +parameter ap_ST_fsm_state4585 = 13'd4584; +parameter ap_ST_fsm_state4586 = 13'd4585; +parameter ap_ST_fsm_state4587 = 13'd4586; +parameter ap_ST_fsm_state4588 = 13'd4587; +parameter ap_ST_fsm_state4589 = 13'd4588; +parameter ap_ST_fsm_state4590 = 13'd4589; +parameter ap_ST_fsm_state4591 = 13'd4590; +parameter ap_ST_fsm_state4592 = 13'd4591; +parameter ap_ST_fsm_state4593 = 13'd4592; +parameter ap_ST_fsm_state4594 = 13'd4593; +parameter ap_ST_fsm_state4595 = 13'd4594; +parameter ap_ST_fsm_state4596 = 13'd4595; +parameter ap_ST_fsm_state4597 = 13'd4596; +parameter ap_ST_fsm_state4598 = 13'd4597; +parameter ap_ST_fsm_state4599 = 13'd4598; +parameter ap_ST_fsm_state4600 = 13'd4599; +parameter ap_ST_fsm_state4601 = 13'd4600; +parameter ap_ST_fsm_state4602 = 13'd4601; +parameter ap_ST_fsm_state4603 = 13'd4602; +parameter ap_ST_fsm_state4604 = 13'd4603; +parameter ap_ST_fsm_state4605 = 13'd4604; +parameter ap_ST_fsm_state4606 = 13'd4605; +parameter ap_ST_fsm_state4607 = 13'd4606; +parameter ap_ST_fsm_state4608 = 13'd4607; +parameter ap_ST_fsm_state4609 = 13'd4608; +parameter ap_ST_fsm_state4610 = 13'd4609; +parameter ap_ST_fsm_state4611 = 13'd4610; +parameter ap_ST_fsm_state4612 = 13'd4611; +parameter ap_ST_fsm_state4613 = 13'd4612; +parameter ap_ST_fsm_state4614 = 13'd4613; +parameter ap_ST_fsm_state4615 = 13'd4614; +parameter ap_ST_fsm_state4616 = 13'd4615; +parameter ap_ST_fsm_state4617 = 13'd4616; +parameter ap_ST_fsm_state4618 = 13'd4617; +parameter ap_ST_fsm_state4619 = 13'd4618; +parameter ap_ST_fsm_state4620 = 13'd4619; +parameter ap_ST_fsm_state4621 = 13'd4620; +parameter ap_ST_fsm_state4622 = 13'd4621; +parameter ap_ST_fsm_state4623 = 13'd4622; +parameter ap_ST_fsm_state4624 = 13'd4623; +parameter ap_ST_fsm_state4625 = 13'd4624; +parameter ap_ST_fsm_state4626 = 13'd4625; +parameter ap_ST_fsm_state4627 = 13'd4626; +parameter ap_ST_fsm_state4628 = 13'd4627; +parameter ap_ST_fsm_state4629 = 13'd4628; +parameter ap_ST_fsm_state4630 = 13'd4629; +parameter ap_ST_fsm_state4631 = 13'd4630; +parameter ap_ST_fsm_state4632 = 13'd4631; +parameter ap_ST_fsm_state4633 = 13'd4632; +parameter ap_ST_fsm_state4634 = 13'd4633; +parameter ap_ST_fsm_state4635 = 13'd4634; +parameter ap_ST_fsm_state4636 = 13'd4635; +parameter ap_ST_fsm_state4637 = 13'd4636; +parameter ap_ST_fsm_state4638 = 13'd4637; +parameter ap_ST_fsm_state4639 = 13'd4638; +parameter ap_ST_fsm_state4640 = 13'd4639; +parameter ap_ST_fsm_state4641 = 13'd4640; +parameter ap_ST_fsm_state4642 = 13'd4641; +parameter ap_ST_fsm_state4643 = 13'd4642; +parameter ap_ST_fsm_state4644 = 13'd4643; +parameter ap_ST_fsm_state4645 = 13'd4644; +parameter ap_ST_fsm_state4646 = 13'd4645; +parameter ap_ST_fsm_state4647 = 13'd4646; +parameter ap_ST_fsm_state4648 = 13'd4647; +parameter ap_ST_fsm_state4649 = 13'd4648; +parameter ap_ST_fsm_state4650 = 13'd4649; +parameter ap_ST_fsm_state4651 = 13'd4650; +parameter ap_ST_fsm_state4652 = 13'd4651; +parameter ap_ST_fsm_state4653 = 13'd4652; +parameter ap_ST_fsm_state4654 = 13'd4653; +parameter ap_ST_fsm_state4655 = 13'd4654; +parameter ap_ST_fsm_state4656 = 13'd4655; +parameter ap_ST_fsm_state4657 = 13'd4656; +parameter ap_ST_fsm_state4658 = 13'd4657; +parameter ap_ST_fsm_state4659 = 13'd4658; +parameter ap_ST_fsm_state4660 = 13'd4659; +parameter ap_ST_fsm_state4661 = 13'd4660; +parameter ap_ST_fsm_state4662 = 13'd4661; +parameter ap_ST_fsm_state4663 = 13'd4662; +parameter ap_ST_fsm_state4664 = 13'd4663; +parameter ap_ST_fsm_state4665 = 13'd4664; +parameter ap_ST_fsm_state4666 = 13'd4665; +parameter ap_ST_fsm_state4667 = 13'd4666; +parameter ap_ST_fsm_state4668 = 13'd4667; +parameter ap_ST_fsm_state4669 = 13'd4668; +parameter ap_ST_fsm_state4670 = 13'd4669; +parameter ap_ST_fsm_state4671 = 13'd4670; +parameter ap_ST_fsm_state4672 = 13'd4671; +parameter ap_ST_fsm_state4673 = 13'd4672; +parameter ap_ST_fsm_state4674 = 13'd4673; +parameter ap_ST_fsm_state4675 = 13'd4674; +parameter ap_ST_fsm_state4676 = 13'd4675; +parameter ap_ST_fsm_state4677 = 13'd4676; +parameter ap_ST_fsm_state4678 = 13'd4677; +parameter ap_ST_fsm_state4679 = 13'd4678; +parameter ap_ST_fsm_state4680 = 13'd4679; +parameter ap_ST_fsm_state4681 = 13'd4680; +parameter ap_ST_fsm_state4682 = 13'd4681; +parameter ap_ST_fsm_state4683 = 13'd4682; +parameter ap_ST_fsm_state4684 = 13'd4683; +parameter ap_ST_fsm_state4685 = 13'd4684; +parameter ap_ST_fsm_state4686 = 13'd4685; +parameter ap_ST_fsm_state4687 = 13'd4686; +parameter ap_ST_fsm_state4688 = 13'd4687; +parameter ap_ST_fsm_state4689 = 13'd4688; +parameter ap_ST_fsm_state4690 = 13'd4689; +parameter ap_ST_fsm_state4691 = 13'd4690; +parameter ap_ST_fsm_state4692 = 13'd4691; +parameter ap_ST_fsm_state4693 = 13'd4692; +parameter ap_ST_fsm_state4694 = 13'd4693; +parameter ap_ST_fsm_state4695 = 13'd4694; +parameter ap_ST_fsm_state4696 = 13'd4695; +parameter ap_ST_fsm_state4697 = 13'd4696; +parameter ap_ST_fsm_state4698 = 13'd4697; +parameter ap_ST_fsm_state4699 = 13'd4698; +parameter ap_ST_fsm_state4700 = 13'd4699; +parameter ap_ST_fsm_state4701 = 13'd4700; +parameter ap_ST_fsm_state4702 = 13'd4701; +parameter ap_ST_fsm_state4703 = 13'd4702; +parameter ap_ST_fsm_state4704 = 13'd4703; +parameter ap_ST_fsm_state4705 = 13'd4704; +parameter ap_ST_fsm_state4706 = 13'd4705; +parameter ap_ST_fsm_state4707 = 13'd4706; +parameter ap_ST_fsm_state4708 = 13'd4707; +parameter ap_ST_fsm_state4709 = 13'd4708; +parameter ap_ST_fsm_state4710 = 13'd4709; +parameter ap_ST_fsm_state4711 = 13'd4710; +parameter ap_ST_fsm_state4712 = 13'd4711; +parameter ap_ST_fsm_state4713 = 13'd4712; +parameter ap_ST_fsm_state4714 = 13'd4713; +parameter ap_ST_fsm_state4715 = 13'd4714; +parameter ap_ST_fsm_state4716 = 13'd4715; +parameter ap_ST_fsm_state4717 = 13'd4716; +parameter ap_ST_fsm_state4718 = 13'd4717; +parameter ap_ST_fsm_state4719 = 13'd4718; +parameter ap_ST_fsm_state4720 = 13'd4719; +parameter ap_ST_fsm_state4721 = 13'd4720; +parameter ap_ST_fsm_state4722 = 13'd4721; +parameter ap_ST_fsm_state4723 = 13'd4722; +parameter ap_ST_fsm_state4724 = 13'd4723; +parameter ap_ST_fsm_state4725 = 13'd4724; +parameter ap_ST_fsm_state4726 = 13'd4725; +parameter ap_ST_fsm_state4727 = 13'd4726; +parameter ap_ST_fsm_state4728 = 13'd4727; +parameter ap_ST_fsm_state4729 = 13'd4728; +parameter ap_ST_fsm_state4730 = 13'd4729; +parameter ap_ST_fsm_state4731 = 13'd4730; +parameter ap_ST_fsm_state4732 = 13'd4731; +parameter ap_ST_fsm_state4733 = 13'd4732; +parameter ap_ST_fsm_state4734 = 13'd4733; +parameter ap_ST_fsm_state4735 = 13'd4734; +parameter ap_ST_fsm_state4736 = 13'd4735; +parameter ap_ST_fsm_state4737 = 13'd4736; +parameter ap_ST_fsm_state4738 = 13'd4737; +parameter ap_ST_fsm_state4739 = 13'd4738; +parameter ap_ST_fsm_state4740 = 13'd4739; +parameter ap_ST_fsm_state4741 = 13'd4740; +parameter ap_ST_fsm_state4742 = 13'd4741; +parameter ap_ST_fsm_state4743 = 13'd4742; +parameter ap_ST_fsm_state4744 = 13'd4743; +parameter ap_ST_fsm_state4745 = 13'd4744; +parameter ap_ST_fsm_state4746 = 13'd4745; +parameter ap_ST_fsm_state4747 = 13'd4746; +parameter ap_ST_fsm_state4748 = 13'd4747; +parameter ap_ST_fsm_state4749 = 13'd4748; +parameter ap_ST_fsm_state4750 = 13'd4749; +parameter ap_ST_fsm_state4751 = 13'd4750; +parameter ap_ST_fsm_state4752 = 13'd4751; +parameter ap_ST_fsm_state4753 = 13'd4752; +parameter ap_ST_fsm_state4754 = 13'd4753; +parameter ap_ST_fsm_state4755 = 13'd4754; +parameter ap_ST_fsm_state4756 = 13'd4755; +parameter ap_ST_fsm_state4757 = 13'd4756; +parameter ap_ST_fsm_state4758 = 13'd4757; +parameter ap_ST_fsm_state4759 = 13'd4758; +parameter ap_ST_fsm_state4760 = 13'd4759; +parameter ap_ST_fsm_state4761 = 13'd4760; +parameter ap_ST_fsm_state4762 = 13'd4761; +parameter ap_ST_fsm_state4763 = 13'd4762; +parameter ap_ST_fsm_state4764 = 13'd4763; +parameter ap_ST_fsm_state4765 = 13'd4764; +parameter ap_ST_fsm_state4766 = 13'd4765; +parameter ap_ST_fsm_state4767 = 13'd4766; +parameter ap_ST_fsm_state4768 = 13'd4767; +parameter ap_ST_fsm_state4769 = 13'd4768; +parameter ap_ST_fsm_state4770 = 13'd4769; +parameter ap_ST_fsm_state4771 = 13'd4770; +parameter ap_ST_fsm_state4772 = 13'd4771; +parameter ap_ST_fsm_state4773 = 13'd4772; +parameter ap_ST_fsm_state4774 = 13'd4773; +parameter ap_ST_fsm_state4775 = 13'd4774; +parameter ap_ST_fsm_state4776 = 13'd4775; +parameter ap_ST_fsm_state4777 = 13'd4776; +parameter ap_ST_fsm_state4778 = 13'd4777; +parameter ap_ST_fsm_state4779 = 13'd4778; +parameter ap_ST_fsm_state4780 = 13'd4779; +parameter ap_ST_fsm_state4781 = 13'd4780; +parameter ap_ST_fsm_state4782 = 13'd4781; +parameter ap_ST_fsm_state4783 = 13'd4782; +parameter ap_ST_fsm_state4784 = 13'd4783; +parameter ap_ST_fsm_state4785 = 13'd4784; +parameter ap_ST_fsm_state4786 = 13'd4785; +parameter ap_ST_fsm_state4787 = 13'd4786; +parameter ap_ST_fsm_state4788 = 13'd4787; +parameter ap_ST_fsm_state4789 = 13'd4788; +parameter ap_ST_fsm_state4790 = 13'd4789; +parameter ap_ST_fsm_state4791 = 13'd4790; +parameter ap_ST_fsm_state4792 = 13'd4791; +parameter ap_ST_fsm_state4793 = 13'd4792; +parameter ap_ST_fsm_state4794 = 13'd4793; +parameter ap_ST_fsm_state4795 = 13'd4794; +parameter ap_ST_fsm_state4796 = 13'd4795; +parameter ap_ST_fsm_state4797 = 13'd4796; +parameter ap_ST_fsm_state4798 = 13'd4797; +parameter ap_ST_fsm_state4799 = 13'd4798; +parameter ap_ST_fsm_state4800 = 13'd4799; +parameter ap_ST_fsm_state4801 = 13'd4800; +parameter ap_ST_fsm_state4802 = 13'd4801; +parameter ap_ST_fsm_state4803 = 13'd4802; +parameter ap_ST_fsm_state4804 = 13'd4803; +parameter ap_ST_fsm_state4805 = 13'd4804; +parameter ap_ST_fsm_state4806 = 13'd4805; +parameter ap_ST_fsm_state4807 = 13'd4806; +parameter ap_ST_fsm_state4808 = 13'd4807; +parameter ap_ST_fsm_state4809 = 13'd4808; +parameter ap_ST_fsm_state4810 = 13'd4809; +parameter ap_ST_fsm_state4811 = 13'd4810; +parameter ap_ST_fsm_state4812 = 13'd4811; +parameter ap_ST_fsm_state4813 = 13'd4812; +parameter ap_ST_fsm_state4814 = 13'd4813; +parameter ap_ST_fsm_state4815 = 13'd4814; +parameter ap_ST_fsm_state4816 = 13'd4815; +parameter ap_ST_fsm_state4817 = 13'd4816; +parameter ap_ST_fsm_state4818 = 13'd4817; +parameter ap_ST_fsm_state4819 = 13'd4818; +parameter ap_ST_fsm_state4820 = 13'd4819; +parameter ap_ST_fsm_state4821 = 13'd4820; +parameter ap_ST_fsm_state4822 = 13'd4821; +parameter ap_ST_fsm_state4823 = 13'd4822; +parameter ap_ST_fsm_state4824 = 13'd4823; +parameter ap_ST_fsm_state4825 = 13'd4824; +parameter ap_ST_fsm_state4826 = 13'd4825; +parameter ap_ST_fsm_state4827 = 13'd4826; +parameter ap_ST_fsm_state4828 = 13'd4827; +parameter ap_ST_fsm_state4829 = 13'd4828; +parameter ap_ST_fsm_state4830 = 13'd4829; +parameter ap_ST_fsm_state4831 = 13'd4830; +parameter ap_ST_fsm_state4832 = 13'd4831; +parameter ap_ST_fsm_state4833 = 13'd4832; +parameter ap_ST_fsm_state4834 = 13'd4833; +parameter ap_ST_fsm_state4835 = 13'd4834; +parameter ap_ST_fsm_state4836 = 13'd4835; +parameter ap_ST_fsm_state4837 = 13'd4836; +parameter ap_ST_fsm_state4838 = 13'd4837; +parameter ap_ST_fsm_state4839 = 13'd4838; +parameter ap_ST_fsm_state4840 = 13'd4839; +parameter ap_ST_fsm_state4841 = 13'd4840; +parameter ap_ST_fsm_state4842 = 13'd4841; +parameter ap_ST_fsm_state4843 = 13'd4842; +parameter ap_ST_fsm_state4844 = 13'd4843; +parameter ap_ST_fsm_state4845 = 13'd4844; +parameter ap_ST_fsm_state4846 = 13'd4845; +parameter ap_ST_fsm_state4847 = 13'd4846; +parameter ap_ST_fsm_state4848 = 13'd4847; +parameter ap_ST_fsm_state4849 = 13'd4848; +parameter ap_ST_fsm_state4850 = 13'd4849; +parameter ap_ST_fsm_state4851 = 13'd4850; +parameter ap_ST_fsm_state4852 = 13'd4851; +parameter ap_ST_fsm_state4853 = 13'd4852; +parameter ap_ST_fsm_state4854 = 13'd4853; +parameter ap_ST_fsm_state4855 = 13'd4854; +parameter ap_ST_fsm_state4856 = 13'd4855; +parameter ap_ST_fsm_state4857 = 13'd4856; +parameter ap_ST_fsm_state4858 = 13'd4857; +parameter ap_ST_fsm_state4859 = 13'd4858; +parameter ap_ST_fsm_state4860 = 13'd4859; +parameter ap_ST_fsm_state4861 = 13'd4860; +parameter ap_ST_fsm_state4862 = 13'd4861; +parameter ap_ST_fsm_state4863 = 13'd4862; +parameter ap_ST_fsm_state4864 = 13'd4863; +parameter ap_ST_fsm_state4865 = 13'd4864; +parameter ap_ST_fsm_state4866 = 13'd4865; +parameter ap_ST_fsm_state4867 = 13'd4866; +parameter ap_ST_fsm_state4868 = 13'd4867; +parameter ap_ST_fsm_state4869 = 13'd4868; +parameter ap_ST_fsm_state4870 = 13'd4869; +parameter ap_ST_fsm_state4871 = 13'd4870; +parameter ap_ST_fsm_state4872 = 13'd4871; +parameter ap_ST_fsm_state4873 = 13'd4872; +parameter ap_ST_fsm_state4874 = 13'd4873; +parameter ap_ST_fsm_state4875 = 13'd4874; +parameter ap_ST_fsm_state4876 = 13'd4875; +parameter ap_ST_fsm_state4877 = 13'd4876; +parameter ap_ST_fsm_state4878 = 13'd4877; +parameter ap_ST_fsm_state4879 = 13'd4878; +parameter ap_ST_fsm_state4880 = 13'd4879; +parameter ap_ST_fsm_state4881 = 13'd4880; +parameter ap_ST_fsm_state4882 = 13'd4881; +parameter ap_ST_fsm_state4883 = 13'd4882; +parameter ap_ST_fsm_state4884 = 13'd4883; +parameter ap_ST_fsm_state4885 = 13'd4884; +parameter ap_ST_fsm_state4886 = 13'd4885; +parameter ap_ST_fsm_state4887 = 13'd4886; +parameter ap_ST_fsm_state4888 = 13'd4887; +parameter ap_ST_fsm_state4889 = 13'd4888; +parameter ap_ST_fsm_state4890 = 13'd4889; +parameter ap_ST_fsm_state4891 = 13'd4890; +parameter ap_ST_fsm_state4892 = 13'd4891; +parameter ap_ST_fsm_state4893 = 13'd4892; +parameter ap_ST_fsm_state4894 = 13'd4893; +parameter ap_ST_fsm_state4895 = 13'd4894; +parameter ap_ST_fsm_state4896 = 13'd4895; +parameter ap_ST_fsm_state4897 = 13'd4896; +parameter ap_ST_fsm_state4898 = 13'd4897; +parameter ap_ST_fsm_state4899 = 13'd4898; +parameter ap_ST_fsm_state4900 = 13'd4899; +parameter ap_ST_fsm_state4901 = 13'd4900; +parameter ap_ST_fsm_state4902 = 13'd4901; +parameter ap_ST_fsm_state4903 = 13'd4902; +parameter ap_ST_fsm_state4904 = 13'd4903; +parameter ap_ST_fsm_state4905 = 13'd4904; +parameter ap_ST_fsm_state4906 = 13'd4905; +parameter ap_ST_fsm_state4907 = 13'd4906; +parameter ap_ST_fsm_state4908 = 13'd4907; +parameter ap_ST_fsm_state4909 = 13'd4908; +parameter ap_ST_fsm_state4910 = 13'd4909; +parameter ap_ST_fsm_state4911 = 13'd4910; +parameter ap_ST_fsm_state4912 = 13'd4911; +parameter ap_ST_fsm_state4913 = 13'd4912; +parameter ap_ST_fsm_state4914 = 13'd4913; +parameter ap_ST_fsm_state4915 = 13'd4914; +parameter ap_ST_fsm_state4916 = 13'd4915; +parameter ap_ST_fsm_state4917 = 13'd4916; +parameter ap_ST_fsm_state4918 = 13'd4917; +parameter ap_ST_fsm_state4919 = 13'd4918; +parameter ap_ST_fsm_state4920 = 13'd4919; +parameter ap_ST_fsm_state4921 = 13'd4920; +parameter ap_ST_fsm_state4922 = 13'd4921; +parameter ap_ST_fsm_state4923 = 13'd4922; +parameter ap_ST_fsm_state4924 = 13'd4923; +parameter ap_ST_fsm_state4925 = 13'd4924; +parameter ap_ST_fsm_state4926 = 13'd4925; +parameter ap_ST_fsm_state4927 = 13'd4926; +parameter ap_ST_fsm_state4928 = 13'd4927; +parameter ap_ST_fsm_state4929 = 13'd4928; +parameter ap_ST_fsm_state4930 = 13'd4929; +parameter ap_ST_fsm_state4931 = 13'd4930; +parameter ap_ST_fsm_state4932 = 13'd4931; +parameter ap_ST_fsm_state4933 = 13'd4932; +parameter ap_ST_fsm_state4934 = 13'd4933; +parameter ap_ST_fsm_state4935 = 13'd4934; +parameter ap_ST_fsm_state4936 = 13'd4935; +parameter ap_ST_fsm_state4937 = 13'd4936; +parameter ap_ST_fsm_state4938 = 13'd4937; +parameter ap_ST_fsm_state4939 = 13'd4938; +parameter ap_ST_fsm_state4940 = 13'd4939; +parameter ap_ST_fsm_state4941 = 13'd4940; +parameter ap_ST_fsm_state4942 = 13'd4941; +parameter ap_ST_fsm_state4943 = 13'd4942; +parameter ap_ST_fsm_state4944 = 13'd4943; +parameter ap_ST_fsm_state4945 = 13'd4944; +parameter ap_ST_fsm_state4946 = 13'd4945; +parameter ap_ST_fsm_state4947 = 13'd4946; +parameter ap_ST_fsm_state4948 = 13'd4947; +parameter ap_ST_fsm_state4949 = 13'd4948; +parameter ap_ST_fsm_state4950 = 13'd4949; +parameter ap_ST_fsm_state4951 = 13'd4950; +parameter ap_ST_fsm_state4952 = 13'd4951; +parameter ap_ST_fsm_state4953 = 13'd4952; +parameter ap_ST_fsm_state4954 = 13'd4953; +parameter ap_ST_fsm_state4955 = 13'd4954; +parameter ap_ST_fsm_state4956 = 13'd4955; +parameter ap_ST_fsm_state4957 = 13'd4956; +parameter ap_ST_fsm_state4958 = 13'd4957; +parameter ap_ST_fsm_state4959 = 13'd4958; +parameter ap_ST_fsm_state4960 = 13'd4959; +parameter ap_ST_fsm_state4961 = 13'd4960; +parameter ap_ST_fsm_state4962 = 13'd4961; +parameter ap_ST_fsm_state4963 = 13'd4962; +parameter ap_ST_fsm_state4964 = 13'd4963; +parameter ap_ST_fsm_state4965 = 13'd4964; +parameter ap_ST_fsm_state4966 = 13'd4965; +parameter ap_ST_fsm_state4967 = 13'd4966; +parameter ap_ST_fsm_state4968 = 13'd4967; +parameter ap_ST_fsm_state4969 = 13'd4968; +parameter ap_ST_fsm_state4970 = 13'd4969; +parameter ap_ST_fsm_state4971 = 13'd4970; +parameter ap_ST_fsm_state4972 = 13'd4971; +parameter ap_ST_fsm_state4973 = 13'd4972; +parameter ap_ST_fsm_state4974 = 13'd4973; +parameter ap_ST_fsm_state4975 = 13'd4974; +parameter ap_ST_fsm_state4976 = 13'd4975; +parameter ap_ST_fsm_state4977 = 13'd4976; +parameter ap_ST_fsm_state4978 = 13'd4977; +parameter ap_ST_fsm_state4979 = 13'd4978; +parameter ap_ST_fsm_state4980 = 13'd4979; +parameter ap_ST_fsm_state4981 = 13'd4980; +parameter ap_ST_fsm_state4982 = 13'd4981; +parameter ap_ST_fsm_state4983 = 13'd4982; +parameter ap_ST_fsm_state4984 = 13'd4983; +parameter ap_ST_fsm_state4985 = 13'd4984; +parameter ap_ST_fsm_state4986 = 13'd4985; +parameter ap_ST_fsm_state4987 = 13'd4986; +parameter ap_ST_fsm_state4988 = 13'd4987; +parameter ap_ST_fsm_state4989 = 13'd4988; +parameter ap_ST_fsm_state4990 = 13'd4989; +parameter ap_ST_fsm_state4991 = 13'd4990; +parameter ap_ST_fsm_state4992 = 13'd4991; +parameter ap_ST_fsm_state4993 = 13'd4992; +parameter ap_ST_fsm_state4994 = 13'd4993; +parameter ap_ST_fsm_state4995 = 13'd4994; +parameter ap_ST_fsm_state4996 = 13'd4995; +parameter ap_ST_fsm_state4997 = 13'd4996; +parameter ap_ST_fsm_state4998 = 13'd4997; +parameter ap_ST_fsm_state4999 = 13'd4998; +parameter ap_ST_fsm_state5000 = 13'd4999; +parameter ap_ST_fsm_state5001 = 13'd5000; +parameter ap_ST_fsm_state5002 = 13'd5001; +parameter ap_ST_fsm_state5003 = 13'd5002; +parameter ap_ST_fsm_state5004 = 13'd5003; +parameter ap_ST_fsm_state5005 = 13'd5004; +parameter ap_ST_fsm_state5006 = 13'd5005; +parameter ap_ST_fsm_state5007 = 13'd5006; +parameter ap_ST_fsm_state5008 = 13'd5007; +parameter ap_ST_fsm_state5009 = 13'd5008; +parameter ap_ST_fsm_state5010 = 13'd5009; +parameter ap_ST_fsm_state5011 = 13'd5010; +parameter ap_ST_fsm_state5012 = 13'd5011; +parameter ap_ST_fsm_state5013 = 13'd5012; +parameter ap_ST_fsm_state5014 = 13'd5013; +parameter ap_ST_fsm_state5015 = 13'd5014; +parameter ap_ST_fsm_state5016 = 13'd5015; +parameter ap_ST_fsm_state5017 = 13'd5016; +parameter ap_ST_fsm_state5018 = 13'd5017; +parameter ap_ST_fsm_state5019 = 13'd5018; +parameter ap_ST_fsm_state5020 = 13'd5019; +parameter ap_ST_fsm_state5021 = 13'd5020; +parameter ap_ST_fsm_state5022 = 13'd5021; +parameter ap_ST_fsm_state5023 = 13'd5022; +parameter ap_ST_fsm_state5024 = 13'd5023; +parameter ap_ST_fsm_state5025 = 13'd5024; +parameter ap_ST_fsm_state5026 = 13'd5025; +parameter ap_ST_fsm_state5027 = 13'd5026; +parameter ap_ST_fsm_state5028 = 13'd5027; +parameter ap_ST_fsm_state5029 = 13'd5028; +parameter ap_ST_fsm_state5030 = 13'd5029; +parameter ap_ST_fsm_state5031 = 13'd5030; +parameter ap_ST_fsm_state5032 = 13'd5031; +parameter ap_ST_fsm_state5033 = 13'd5032; +parameter ap_ST_fsm_state5034 = 13'd5033; +parameter ap_ST_fsm_state5035 = 13'd5034; +parameter ap_ST_fsm_state5036 = 13'd5035; +parameter ap_ST_fsm_state5037 = 13'd5036; +parameter ap_ST_fsm_state5038 = 13'd5037; +parameter ap_ST_fsm_state5039 = 13'd5038; +parameter ap_ST_fsm_state5040 = 13'd5039; +parameter ap_ST_fsm_state5041 = 13'd5040; +parameter ap_ST_fsm_state5042 = 13'd5041; +parameter ap_ST_fsm_state5043 = 13'd5042; +parameter ap_ST_fsm_state5044 = 13'd5043; +parameter ap_ST_fsm_state5045 = 13'd5044; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +output [2:0] data_0_V_address0; +output data_0_V_ce0; +input [7:0] data_0_V_q0; +output [2:0] data_1_V_address0; +output data_1_V_ce0; +input [7:0] data_1_V_q0; +output [2:0] data_2_V_address0; +output data_2_V_ce0; +input [7:0] data_2_V_q0; +output [2:0] data_3_V_address0; +output data_3_V_ce0; +input [7:0] data_3_V_q0; +output [2:0] data_4_V_address0; +output data_4_V_ce0; +input [7:0] data_4_V_q0; +output [2:0] data_5_V_address0; +output data_5_V_ce0; +input [7:0] data_5_V_q0; +output [2:0] data_6_V_address0; +output data_6_V_ce0; +input [7:0] data_6_V_q0; +output [2:0] data_7_V_address0; +output data_7_V_ce0; +input [7:0] data_7_V_q0; +output [2:0] data_8_V_address0; +output data_8_V_ce0; +input [7:0] data_8_V_q0; +output [2:0] data_9_V_address0; +output data_9_V_ce0; +input [7:0] data_9_V_q0; +output [2:0] data_10_V_address0; +output data_10_V_ce0; +input [7:0] data_10_V_q0; +output [2:0] data_11_V_address0; +output data_11_V_ce0; +input [7:0] data_11_V_q0; +output [2:0] data_12_V_address0; +output data_12_V_ce0; +input [7:0] data_12_V_q0; +output [2:0] data_13_V_address0; +output data_13_V_ce0; +input [7:0] data_13_V_q0; +output [2:0] data_14_V_address0; +output data_14_V_ce0; +input [7:0] data_14_V_q0; +output [2:0] data_15_V_address0; +output data_15_V_ce0; +input [7:0] data_15_V_q0; +output [2:0] data_16_V_address0; +output data_16_V_ce0; +input [7:0] data_16_V_q0; +output [2:0] data_17_V_address0; +output data_17_V_ce0; +input [7:0] data_17_V_q0; +output [2:0] data_18_V_address0; +output data_18_V_ce0; +input [7:0] data_18_V_q0; +output [2:0] data_19_V_address0; +output data_19_V_ce0; +input [7:0] data_19_V_q0; +output [2:0] data_20_V_address0; +output data_20_V_ce0; +input [7:0] data_20_V_q0; +output [2:0] data_21_V_address0; +output data_21_V_ce0; +input [7:0] data_21_V_q0; +output [2:0] data_22_V_address0; +output data_22_V_ce0; +input [7:0] data_22_V_q0; +output [2:0] data_23_V_address0; +output data_23_V_ce0; +input [7:0] data_23_V_q0; +output [2:0] data_24_V_address0; +output data_24_V_ce0; +input [7:0] data_24_V_q0; +output [2:0] data_25_V_address0; +output data_25_V_ce0; +input [7:0] data_25_V_q0; +output [2:0] data_26_V_address0; +output data_26_V_ce0; +input [7:0] data_26_V_q0; +output [2:0] data_27_V_address0; +output data_27_V_ce0; +input [7:0] data_27_V_q0; +output [2:0] data_28_V_address0; +output data_28_V_ce0; +input [7:0] data_28_V_q0; +output [2:0] data_29_V_address0; +output data_29_V_ce0; +input [7:0] data_29_V_q0; +output [2:0] data_30_V_address0; +output data_30_V_ce0; +input [7:0] data_30_V_q0; +output [2:0] data_31_V_address0; +output data_31_V_ce0; +input [7:0] data_31_V_q0; +output [2:0] data_32_V_address0; +output data_32_V_ce0; +input [7:0] data_32_V_q0; +output [2:0] data_33_V_address0; +output data_33_V_ce0; +input [7:0] data_33_V_q0; +output [2:0] data_34_V_address0; +output data_34_V_ce0; +input [7:0] data_34_V_q0; +output [2:0] data_35_V_address0; +output data_35_V_ce0; +input [7:0] data_35_V_q0; +output [2:0] data_36_V_address0; +output data_36_V_ce0; +input [7:0] data_36_V_q0; +output [2:0] data_37_V_address0; +output data_37_V_ce0; +input [7:0] data_37_V_q0; +output [2:0] data_38_V_address0; +output data_38_V_ce0; +input [7:0] data_38_V_q0; +output [2:0] data_39_V_address0; +output data_39_V_ce0; +input [7:0] data_39_V_q0; +output [2:0] data_40_V_address0; +output data_40_V_ce0; +input [7:0] data_40_V_q0; +output [2:0] data_41_V_address0; +output data_41_V_ce0; +input [7:0] data_41_V_q0; +output [2:0] data_42_V_address0; +output data_42_V_ce0; +input [7:0] data_42_V_q0; +output [2:0] data_43_V_address0; +output data_43_V_ce0; +input [7:0] data_43_V_q0; +output [2:0] data_44_V_address0; +output data_44_V_ce0; +input [7:0] data_44_V_q0; +output [2:0] data_45_V_address0; +output data_45_V_ce0; +input [7:0] data_45_V_q0; +output [2:0] data_46_V_address0; +output data_46_V_ce0; +input [7:0] data_46_V_q0; +output [2:0] data_47_V_address0; +output data_47_V_ce0; +input [7:0] data_47_V_q0; +output [2:0] data_48_V_address0; +output data_48_V_ce0; +input [7:0] data_48_V_q0; +output [2:0] data_49_V_address0; +output data_49_V_ce0; +input [7:0] data_49_V_q0; +output [2:0] data_50_V_address0; +output data_50_V_ce0; +input [7:0] data_50_V_q0; +output [2:0] data_51_V_address0; +output data_51_V_ce0; +input [7:0] data_51_V_q0; +output [2:0] data_52_V_address0; +output data_52_V_ce0; +input [7:0] data_52_V_q0; +output [2:0] data_53_V_address0; +output data_53_V_ce0; +input [7:0] data_53_V_q0; +output [2:0] data_54_V_address0; +output data_54_V_ce0; +input [7:0] data_54_V_q0; +output [2:0] data_55_V_address0; +output data_55_V_ce0; +input [7:0] data_55_V_q0; +output [2:0] data_56_V_address0; +output data_56_V_ce0; +input [7:0] data_56_V_q0; +output [2:0] data_57_V_address0; +output data_57_V_ce0; +input [7:0] data_57_V_q0; +output [2:0] data_58_V_address0; +output data_58_V_ce0; +input [7:0] data_58_V_q0; +output [2:0] data_59_V_address0; +output data_59_V_ce0; +input [7:0] data_59_V_q0; +output [2:0] data_60_V_address0; +output data_60_V_ce0; +input [7:0] data_60_V_q0; +output [2:0] data_61_V_address0; +output data_61_V_ce0; +input [7:0] data_61_V_q0; +output [2:0] data_62_V_address0; +output data_62_V_ce0; +input [7:0] data_62_V_q0; +output [2:0] data_63_V_address0; +output data_63_V_ce0; +input [7:0] data_63_V_q0; +output [2:0] data_64_V_address0; +output data_64_V_ce0; +input [7:0] data_64_V_q0; +output [2:0] data_65_V_address0; +output data_65_V_ce0; +input [7:0] data_65_V_q0; +output [2:0] data_66_V_address0; +output data_66_V_ce0; +input [7:0] data_66_V_q0; +output [2:0] data_67_V_address0; +output data_67_V_ce0; +input [7:0] data_67_V_q0; +output [2:0] data_68_V_address0; +output data_68_V_ce0; +input [7:0] data_68_V_q0; +output [2:0] data_69_V_address0; +output data_69_V_ce0; +input [7:0] data_69_V_q0; +output [2:0] data_70_V_address0; +output data_70_V_ce0; +input [7:0] data_70_V_q0; +output [2:0] data_71_V_address0; +output data_71_V_ce0; +input [7:0] data_71_V_q0; +output [2:0] data_72_V_address0; +output data_72_V_ce0; +input [7:0] data_72_V_q0; +output [2:0] data_73_V_address0; +output data_73_V_ce0; +input [7:0] data_73_V_q0; +output [2:0] data_74_V_address0; +output data_74_V_ce0; +input [7:0] data_74_V_q0; +output [2:0] data_75_V_address0; +output data_75_V_ce0; +input [7:0] data_75_V_q0; +output [2:0] data_76_V_address0; +output data_76_V_ce0; +input [7:0] data_76_V_q0; +output [2:0] data_77_V_address0; +output data_77_V_ce0; +input [7:0] data_77_V_q0; +output [2:0] data_78_V_address0; +output data_78_V_ce0; +input [7:0] data_78_V_q0; +output [2:0] data_79_V_address0; +output data_79_V_ce0; +input [7:0] data_79_V_q0; +output [2:0] data_80_V_address0; +output data_80_V_ce0; +input [7:0] data_80_V_q0; +output [2:0] data_81_V_address0; +output data_81_V_ce0; +input [7:0] data_81_V_q0; +output [2:0] data_82_V_address0; +output data_82_V_ce0; +input [7:0] data_82_V_q0; +output [2:0] data_83_V_address0; +output data_83_V_ce0; +input [7:0] data_83_V_q0; +output [2:0] data_84_V_address0; +output data_84_V_ce0; +input [7:0] data_84_V_q0; +output [2:0] data_85_V_address0; +output data_85_V_ce0; +input [7:0] data_85_V_q0; +output [2:0] data_86_V_address0; +output data_86_V_ce0; +input [7:0] data_86_V_q0; +output [2:0] data_87_V_address0; +output data_87_V_ce0; +input [7:0] data_87_V_q0; +output [2:0] data_88_V_address0; +output data_88_V_ce0; +input [7:0] data_88_V_q0; +output [2:0] data_89_V_address0; +output data_89_V_ce0; +input [7:0] data_89_V_q0; +output [2:0] data_90_V_address0; +output data_90_V_ce0; +input [7:0] data_90_V_q0; +output [2:0] data_91_V_address0; +output data_91_V_ce0; +input [7:0] data_91_V_q0; +output [2:0] data_92_V_address0; +output data_92_V_ce0; +input [7:0] data_92_V_q0; +output [2:0] data_93_V_address0; +output data_93_V_ce0; +input [7:0] data_93_V_q0; +output [2:0] data_94_V_address0; +output data_94_V_ce0; +input [7:0] data_94_V_q0; +output [2:0] data_95_V_address0; +output data_95_V_ce0; +input [7:0] data_95_V_q0; +output [2:0] data_96_V_address0; +output data_96_V_ce0; +input [7:0] data_96_V_q0; +output [2:0] data_97_V_address0; +output data_97_V_ce0; +input [7:0] data_97_V_q0; +output [2:0] data_98_V_address0; +output data_98_V_ce0; +input [7:0] data_98_V_q0; +output [2:0] data_99_V_address0; +output data_99_V_ce0; +input [7:0] data_99_V_q0; +output [2:0] data_100_V_address0; +output data_100_V_ce0; +input [7:0] data_100_V_q0; +output [2:0] data_101_V_address0; +output data_101_V_ce0; +input [7:0] data_101_V_q0; +output [2:0] data_102_V_address0; +output data_102_V_ce0; +input [7:0] data_102_V_q0; +output [2:0] data_103_V_address0; +output data_103_V_ce0; +input [7:0] data_103_V_q0; +output [2:0] data_104_V_address0; +output data_104_V_ce0; +input [7:0] data_104_V_q0; +output [2:0] data_105_V_address0; +output data_105_V_ce0; +input [7:0] data_105_V_q0; +output [2:0] data_106_V_address0; +output data_106_V_ce0; +input [7:0] data_106_V_q0; +output [2:0] data_107_V_address0; +output data_107_V_ce0; +input [7:0] data_107_V_q0; +output [2:0] data_108_V_address0; +output data_108_V_ce0; +input [7:0] data_108_V_q0; +output [2:0] data_109_V_address0; +output data_109_V_ce0; +input [7:0] data_109_V_q0; +output [2:0] data_110_V_address0; +output data_110_V_ce0; +input [7:0] data_110_V_q0; +output [2:0] data_111_V_address0; +output data_111_V_ce0; +input [7:0] data_111_V_q0; +output [2:0] data_112_V_address0; +output data_112_V_ce0; +input [7:0] data_112_V_q0; +output [2:0] data_113_V_address0; +output data_113_V_ce0; +input [7:0] data_113_V_q0; +output [2:0] data_114_V_address0; +output data_114_V_ce0; +input [7:0] data_114_V_q0; +output [2:0] data_115_V_address0; +output data_115_V_ce0; +input [7:0] data_115_V_q0; +output [2:0] data_116_V_address0; +output data_116_V_ce0; +input [7:0] data_116_V_q0; +output [2:0] data_117_V_address0; +output data_117_V_ce0; +input [7:0] data_117_V_q0; +output [2:0] data_118_V_address0; +output data_118_V_ce0; +input [7:0] data_118_V_q0; +output [2:0] data_119_V_address0; +output data_119_V_ce0; +input [7:0] data_119_V_q0; +output [2:0] data_120_V_address0; +output data_120_V_ce0; +input [7:0] data_120_V_q0; +output [2:0] data_121_V_address0; +output data_121_V_ce0; +input [7:0] data_121_V_q0; +output [2:0] data_122_V_address0; +output data_122_V_ce0; +input [7:0] data_122_V_q0; +output [2:0] data_123_V_address0; +output data_123_V_ce0; +input [7:0] data_123_V_q0; +output [2:0] data_124_V_address0; +output data_124_V_ce0; +input [7:0] data_124_V_q0; +output [2:0] data_125_V_address0; +output data_125_V_ce0; +input [7:0] data_125_V_q0; +output [2:0] data_126_V_address0; +output data_126_V_ce0; +input [7:0] data_126_V_q0; +output [2:0] data_127_V_address0; +output data_127_V_ce0; +input [7:0] data_127_V_q0; +output [4:0] res_0_V_address0; +output res_0_V_ce0; +output res_0_V_we0; +output [7:0] res_0_V_d0; +output [4:0] res_1_V_address0; +output res_1_V_ce0; +output res_1_V_we0; +output [7:0] res_1_V_d0; +output [4:0] res_2_V_address0; +output res_2_V_ce0; +output res_2_V_we0; +output [7:0] res_2_V_d0; +output [4:0] res_3_V_address0; +output res_3_V_ce0; +output res_3_V_we0; +output [7:0] res_3_V_d0; +output [4:0] res_4_V_address0; +output res_4_V_ce0; +output res_4_V_we0; +output [7:0] res_4_V_d0; +output [4:0] res_5_V_address0; +output res_5_V_ce0; +output res_5_V_we0; +output [7:0] res_5_V_d0; +output [4:0] res_6_V_address0; +output res_6_V_ce0; +output res_6_V_we0; +output [7:0] res_6_V_d0; +output [4:0] res_7_V_address0; +output res_7_V_ce0; +output res_7_V_we0; +output [7:0] res_7_V_d0; +output [4:0] res_8_V_address0; +output res_8_V_ce0; +output res_8_V_we0; +output [7:0] res_8_V_d0; +output [4:0] res_9_V_address0; +output res_9_V_ce0; +output res_9_V_we0; +output [7:0] res_9_V_d0; +output [4:0] res_10_V_address0; +output res_10_V_ce0; +output res_10_V_we0; +output [7:0] res_10_V_d0; +output [4:0] res_11_V_address0; +output res_11_V_ce0; +output res_11_V_we0; +output [7:0] res_11_V_d0; +output [4:0] res_12_V_address0; +output res_12_V_ce0; +output res_12_V_we0; +output [7:0] res_12_V_d0; +output [4:0] res_13_V_address0; +output res_13_V_ce0; +output res_13_V_we0; +output [7:0] res_13_V_d0; +output [4:0] res_14_V_address0; +output res_14_V_ce0; +output res_14_V_we0; +output [7:0] res_14_V_d0; +output [4:0] res_15_V_address0; +output res_15_V_ce0; +output res_15_V_we0; +output [7:0] res_15_V_d0; +output [4:0] res_16_V_address0; +output res_16_V_ce0; +output res_16_V_we0; +output [7:0] res_16_V_d0; +output [4:0] res_17_V_address0; +output res_17_V_ce0; +output res_17_V_we0; +output [7:0] res_17_V_d0; +output [4:0] res_18_V_address0; +output res_18_V_ce0; +output res_18_V_we0; +output [7:0] res_18_V_d0; +output [4:0] res_19_V_address0; +output res_19_V_ce0; +output res_19_V_we0; +output [7:0] res_19_V_d0; +output [4:0] res_20_V_address0; +output res_20_V_ce0; +output res_20_V_we0; +output [7:0] res_20_V_d0; +output [4:0] res_21_V_address0; +output res_21_V_ce0; +output res_21_V_we0; +output [7:0] res_21_V_d0; +output [4:0] res_22_V_address0; +output res_22_V_ce0; +output res_22_V_we0; +output [7:0] res_22_V_d0; +output [4:0] res_23_V_address0; +output res_23_V_ce0; +output res_23_V_we0; +output [7:0] res_23_V_d0; +output [4:0] res_24_V_address0; +output res_24_V_ce0; +output res_24_V_we0; +output [7:0] res_24_V_d0; +output [4:0] res_25_V_address0; +output res_25_V_ce0; +output res_25_V_we0; +output [7:0] res_25_V_d0; +output [4:0] res_26_V_address0; +output res_26_V_ce0; +output res_26_V_we0; +output [7:0] res_26_V_d0; +output [4:0] res_27_V_address0; +output res_27_V_ce0; +output res_27_V_we0; +output [7:0] res_27_V_d0; +output [4:0] res_28_V_address0; +output res_28_V_ce0; +output res_28_V_we0; +output [7:0] res_28_V_d0; +output [4:0] res_29_V_address0; +output res_29_V_ce0; +output res_29_V_we0; +output [7:0] res_29_V_d0; +output [4:0] res_30_V_address0; +output res_30_V_ce0; +output res_30_V_we0; +output [7:0] res_30_V_d0; +output [4:0] res_31_V_address0; +output res_31_V_ce0; +output res_31_V_we0; +output [7:0] res_31_V_d0; +output [4:0] res_32_V_address0; +output res_32_V_ce0; +output res_32_V_we0; +output [7:0] res_32_V_d0; +output [4:0] res_33_V_address0; +output res_33_V_ce0; +output res_33_V_we0; +output [7:0] res_33_V_d0; +output [4:0] res_34_V_address0; +output res_34_V_ce0; +output res_34_V_we0; +output [7:0] res_34_V_d0; +output [4:0] res_35_V_address0; +output res_35_V_ce0; +output res_35_V_we0; +output [7:0] res_35_V_d0; +output [4:0] res_36_V_address0; +output res_36_V_ce0; +output res_36_V_we0; +output [7:0] res_36_V_d0; +output [4:0] res_37_V_address0; +output res_37_V_ce0; +output res_37_V_we0; +output [7:0] res_37_V_d0; +output [4:0] res_38_V_address0; +output res_38_V_ce0; +output res_38_V_we0; +output [7:0] res_38_V_d0; +output [4:0] res_39_V_address0; +output res_39_V_ce0; +output res_39_V_we0; +output [7:0] res_39_V_d0; +output [4:0] res_40_V_address0; +output res_40_V_ce0; +output res_40_V_we0; +output [7:0] res_40_V_d0; +output [4:0] res_41_V_address0; +output res_41_V_ce0; +output res_41_V_we0; +output [7:0] res_41_V_d0; +output [4:0] res_42_V_address0; +output res_42_V_ce0; +output res_42_V_we0; +output [7:0] res_42_V_d0; +output [4:0] res_43_V_address0; +output res_43_V_ce0; +output res_43_V_we0; +output [7:0] res_43_V_d0; +output [4:0] res_44_V_address0; +output res_44_V_ce0; +output res_44_V_we0; +output [7:0] res_44_V_d0; +output [4:0] res_45_V_address0; +output res_45_V_ce0; +output res_45_V_we0; +output [7:0] res_45_V_d0; +output [4:0] res_46_V_address0; +output res_46_V_ce0; +output res_46_V_we0; +output [7:0] res_46_V_d0; +output [4:0] res_47_V_address0; +output res_47_V_ce0; +output res_47_V_we0; +output [7:0] res_47_V_d0; +output [4:0] res_48_V_address0; +output res_48_V_ce0; +output res_48_V_we0; +output [7:0] res_48_V_d0; +output [4:0] res_49_V_address0; +output res_49_V_ce0; +output res_49_V_we0; +output [7:0] res_49_V_d0; +output [4:0] res_50_V_address0; +output res_50_V_ce0; +output res_50_V_we0; +output [7:0] res_50_V_d0; +output [4:0] res_51_V_address0; +output res_51_V_ce0; +output res_51_V_we0; +output [7:0] res_51_V_d0; +output [4:0] res_52_V_address0; +output res_52_V_ce0; +output res_52_V_we0; +output [7:0] res_52_V_d0; +output [4:0] res_53_V_address0; +output res_53_V_ce0; +output res_53_V_we0; +output [7:0] res_53_V_d0; +output [4:0] res_54_V_address0; +output res_54_V_ce0; +output res_54_V_we0; +output [7:0] res_54_V_d0; +output [4:0] res_55_V_address0; +output res_55_V_ce0; +output res_55_V_we0; +output [7:0] res_55_V_d0; +output [4:0] res_56_V_address0; +output res_56_V_ce0; +output res_56_V_we0; +output [7:0] res_56_V_d0; +output [4:0] res_57_V_address0; +output res_57_V_ce0; +output res_57_V_we0; +output [7:0] res_57_V_d0; +output [4:0] res_58_V_address0; +output res_58_V_ce0; +output res_58_V_we0; +output [7:0] res_58_V_d0; +output [4:0] res_59_V_address0; +output res_59_V_ce0; +output res_59_V_we0; +output [7:0] res_59_V_d0; +output [4:0] res_60_V_address0; +output res_60_V_ce0; +output res_60_V_we0; +output [7:0] res_60_V_d0; +output [4:0] res_61_V_address0; +output res_61_V_ce0; +output res_61_V_we0; +output [7:0] res_61_V_d0; +output [4:0] res_62_V_address0; +output res_62_V_ce0; +output res_62_V_we0; +output [7:0] res_62_V_d0; +output [4:0] res_63_V_address0; +output res_63_V_ce0; +output res_63_V_we0; +output [7:0] res_63_V_d0; +output [4:0] res_64_V_address0; +output res_64_V_ce0; +output res_64_V_we0; +output [7:0] res_64_V_d0; +output [4:0] res_65_V_address0; +output res_65_V_ce0; +output res_65_V_we0; +output [7:0] res_65_V_d0; +output [4:0] res_66_V_address0; +output res_66_V_ce0; +output res_66_V_we0; +output [7:0] res_66_V_d0; +output [4:0] res_67_V_address0; +output res_67_V_ce0; +output res_67_V_we0; +output [7:0] res_67_V_d0; +output [4:0] res_68_V_address0; +output res_68_V_ce0; +output res_68_V_we0; +output [7:0] res_68_V_d0; +output [4:0] res_69_V_address0; +output res_69_V_ce0; +output res_69_V_we0; +output [7:0] res_69_V_d0; +output [4:0] res_70_V_address0; +output res_70_V_ce0; +output res_70_V_we0; +output [7:0] res_70_V_d0; +output [4:0] res_71_V_address0; +output res_71_V_ce0; +output res_71_V_we0; +output [7:0] res_71_V_d0; +output [4:0] res_72_V_address0; +output res_72_V_ce0; +output res_72_V_we0; +output [7:0] res_72_V_d0; +output [4:0] res_73_V_address0; +output res_73_V_ce0; +output res_73_V_we0; +output [7:0] res_73_V_d0; +output [4:0] res_74_V_address0; +output res_74_V_ce0; +output res_74_V_we0; +output [7:0] res_74_V_d0; +output [4:0] res_75_V_address0; +output res_75_V_ce0; +output res_75_V_we0; +output [7:0] res_75_V_d0; +output [4:0] res_76_V_address0; +output res_76_V_ce0; +output res_76_V_we0; +output [7:0] res_76_V_d0; +output [4:0] res_77_V_address0; +output res_77_V_ce0; +output res_77_V_we0; +output [7:0] res_77_V_d0; +output [4:0] res_78_V_address0; +output res_78_V_ce0; +output res_78_V_we0; +output [7:0] res_78_V_d0; +output [4:0] res_79_V_address0; +output res_79_V_ce0; +output res_79_V_we0; +output [7:0] res_79_V_d0; +output [4:0] res_80_V_address0; +output res_80_V_ce0; +output res_80_V_we0; +output [7:0] res_80_V_d0; +output [4:0] res_81_V_address0; +output res_81_V_ce0; +output res_81_V_we0; +output [7:0] res_81_V_d0; +output [4:0] res_82_V_address0; +output res_82_V_ce0; +output res_82_V_we0; +output [7:0] res_82_V_d0; +output [4:0] res_83_V_address0; +output res_83_V_ce0; +output res_83_V_we0; +output [7:0] res_83_V_d0; +output [4:0] res_84_V_address0; +output res_84_V_ce0; +output res_84_V_we0; +output [7:0] res_84_V_d0; +output [4:0] res_85_V_address0; +output res_85_V_ce0; +output res_85_V_we0; +output [7:0] res_85_V_d0; +output [4:0] res_86_V_address0; +output res_86_V_ce0; +output res_86_V_we0; +output [7:0] res_86_V_d0; +output [4:0] res_87_V_address0; +output res_87_V_ce0; +output res_87_V_we0; +output [7:0] res_87_V_d0; +output [4:0] res_88_V_address0; +output res_88_V_ce0; +output res_88_V_we0; +output [7:0] res_88_V_d0; +output [4:0] res_89_V_address0; +output res_89_V_ce0; +output res_89_V_we0; +output [7:0] res_89_V_d0; +output [4:0] res_90_V_address0; +output res_90_V_ce0; +output res_90_V_we0; +output [7:0] res_90_V_d0; +output [4:0] res_91_V_address0; +output res_91_V_ce0; +output res_91_V_we0; +output [7:0] res_91_V_d0; +output [4:0] res_92_V_address0; +output res_92_V_ce0; +output res_92_V_we0; +output [7:0] res_92_V_d0; +output [4:0] res_93_V_address0; +output res_93_V_ce0; +output res_93_V_we0; +output [7:0] res_93_V_d0; +output [4:0] res_94_V_address0; +output res_94_V_ce0; +output res_94_V_we0; +output [7:0] res_94_V_d0; +output [4:0] res_95_V_address0; +output res_95_V_ce0; +output res_95_V_we0; +output [7:0] res_95_V_d0; +output [4:0] res_96_V_address0; +output res_96_V_ce0; +output res_96_V_we0; +output [7:0] res_96_V_d0; +output [4:0] res_97_V_address0; +output res_97_V_ce0; +output res_97_V_we0; +output [7:0] res_97_V_d0; +output [4:0] res_98_V_address0; +output res_98_V_ce0; +output res_98_V_we0; +output [7:0] res_98_V_d0; +output [4:0] res_99_V_address0; +output res_99_V_ce0; +output res_99_V_we0; +output [7:0] res_99_V_d0; +output [4:0] res_100_V_address0; +output res_100_V_ce0; +output res_100_V_we0; +output [7:0] res_100_V_d0; +output [4:0] res_101_V_address0; +output res_101_V_ce0; +output res_101_V_we0; +output [7:0] res_101_V_d0; +output [4:0] res_102_V_address0; +output res_102_V_ce0; +output res_102_V_we0; +output [7:0] res_102_V_d0; +output [4:0] res_103_V_address0; +output res_103_V_ce0; +output res_103_V_we0; +output [7:0] res_103_V_d0; +output [4:0] res_104_V_address0; +output res_104_V_ce0; +output res_104_V_we0; +output [7:0] res_104_V_d0; +output [4:0] res_105_V_address0; +output res_105_V_ce0; +output res_105_V_we0; +output [7:0] res_105_V_d0; +output [4:0] res_106_V_address0; +output res_106_V_ce0; +output res_106_V_we0; +output [7:0] res_106_V_d0; +output [4:0] res_107_V_address0; +output res_107_V_ce0; +output res_107_V_we0; +output [7:0] res_107_V_d0; +output [4:0] res_108_V_address0; +output res_108_V_ce0; +output res_108_V_we0; +output [7:0] res_108_V_d0; +output [4:0] res_109_V_address0; +output res_109_V_ce0; +output res_109_V_we0; +output [7:0] res_109_V_d0; +output [4:0] res_110_V_address0; +output res_110_V_ce0; +output res_110_V_we0; +output [7:0] res_110_V_d0; +output [4:0] res_111_V_address0; +output res_111_V_ce0; +output res_111_V_we0; +output [7:0] res_111_V_d0; +output [4:0] res_112_V_address0; +output res_112_V_ce0; +output res_112_V_we0; +output [7:0] res_112_V_d0; +output [4:0] res_113_V_address0; +output res_113_V_ce0; +output res_113_V_we0; +output [7:0] res_113_V_d0; +output [4:0] res_114_V_address0; +output res_114_V_ce0; +output res_114_V_we0; +output [7:0] res_114_V_d0; +output [4:0] res_115_V_address0; +output res_115_V_ce0; +output res_115_V_we0; +output [7:0] res_115_V_d0; +output [4:0] res_116_V_address0; +output res_116_V_ce0; +output res_116_V_we0; +output [7:0] res_116_V_d0; +output [4:0] res_117_V_address0; +output res_117_V_ce0; +output res_117_V_we0; +output [7:0] res_117_V_d0; +output [4:0] res_118_V_address0; +output res_118_V_ce0; +output res_118_V_we0; +output [7:0] res_118_V_d0; +output [4:0] res_119_V_address0; +output res_119_V_ce0; +output res_119_V_we0; +output [7:0] res_119_V_d0; +output [4:0] res_120_V_address0; +output res_120_V_ce0; +output res_120_V_we0; +output [7:0] res_120_V_d0; +output [4:0] res_121_V_address0; +output res_121_V_ce0; +output res_121_V_we0; +output [7:0] res_121_V_d0; +output [4:0] res_122_V_address0; +output res_122_V_ce0; +output res_122_V_we0; +output [7:0] res_122_V_d0; +output [4:0] res_123_V_address0; +output res_123_V_ce0; +output res_123_V_we0; +output [7:0] res_123_V_d0; +output [4:0] res_124_V_address0; +output res_124_V_ce0; +output res_124_V_we0; +output [7:0] res_124_V_d0; +output [4:0] res_125_V_address0; +output res_125_V_ce0; +output res_125_V_we0; +output [7:0] res_125_V_d0; +output [4:0] res_126_V_address0; +output res_126_V_ce0; +output res_126_V_we0; +output [7:0] res_126_V_d0; +output [4:0] res_127_V_address0; +output res_127_V_ce0; +output res_127_V_we0; +output [7:0] res_127_V_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[2:0] data_0_V_address0; +reg data_0_V_ce0; +reg[2:0] data_1_V_address0; +reg data_1_V_ce0; +reg[2:0] data_2_V_address0; +reg data_2_V_ce0; +reg[2:0] data_3_V_address0; +reg data_3_V_ce0; +reg[2:0] data_4_V_address0; +reg data_4_V_ce0; +reg[2:0] data_5_V_address0; +reg data_5_V_ce0; +reg[2:0] data_6_V_address0; +reg data_6_V_ce0; +reg[2:0] data_7_V_address0; +reg data_7_V_ce0; +reg[2:0] data_8_V_address0; +reg data_8_V_ce0; +reg[2:0] data_9_V_address0; +reg data_9_V_ce0; +reg[2:0] data_10_V_address0; +reg data_10_V_ce0; +reg[2:0] data_11_V_address0; +reg data_11_V_ce0; +reg[2:0] data_12_V_address0; +reg data_12_V_ce0; +reg[2:0] data_13_V_address0; +reg data_13_V_ce0; +reg[2:0] data_14_V_address0; +reg data_14_V_ce0; +reg[2:0] data_15_V_address0; +reg data_15_V_ce0; +reg[2:0] data_16_V_address0; +reg data_16_V_ce0; +reg[2:0] data_17_V_address0; +reg data_17_V_ce0; +reg[2:0] data_18_V_address0; +reg data_18_V_ce0; +reg[2:0] data_19_V_address0; +reg data_19_V_ce0; +reg[2:0] data_20_V_address0; +reg data_20_V_ce0; +reg[2:0] data_21_V_address0; +reg data_21_V_ce0; +reg[2:0] data_22_V_address0; +reg data_22_V_ce0; +reg[2:0] data_23_V_address0; +reg data_23_V_ce0; +reg[2:0] data_24_V_address0; +reg data_24_V_ce0; +reg[2:0] data_25_V_address0; +reg data_25_V_ce0; +reg[2:0] data_26_V_address0; +reg data_26_V_ce0; +reg[2:0] data_27_V_address0; +reg data_27_V_ce0; +reg[2:0] data_28_V_address0; +reg data_28_V_ce0; +reg[2:0] data_29_V_address0; +reg data_29_V_ce0; +reg[2:0] data_30_V_address0; +reg data_30_V_ce0; +reg[2:0] data_31_V_address0; +reg data_31_V_ce0; +reg[2:0] data_32_V_address0; +reg data_32_V_ce0; +reg[2:0] data_33_V_address0; +reg data_33_V_ce0; +reg[2:0] data_34_V_address0; +reg data_34_V_ce0; +reg[2:0] data_35_V_address0; +reg data_35_V_ce0; +reg[2:0] data_36_V_address0; +reg data_36_V_ce0; +reg[2:0] data_37_V_address0; +reg data_37_V_ce0; +reg[2:0] data_38_V_address0; +reg data_38_V_ce0; +reg[2:0] data_39_V_address0; +reg data_39_V_ce0; +reg[2:0] data_40_V_address0; +reg data_40_V_ce0; +reg[2:0] data_41_V_address0; +reg data_41_V_ce0; +reg[2:0] data_42_V_address0; +reg data_42_V_ce0; +reg[2:0] data_43_V_address0; +reg data_43_V_ce0; +reg[2:0] data_44_V_address0; +reg data_44_V_ce0; +reg[2:0] data_45_V_address0; +reg data_45_V_ce0; +reg[2:0] data_46_V_address0; +reg data_46_V_ce0; +reg[2:0] data_47_V_address0; +reg data_47_V_ce0; +reg[2:0] data_48_V_address0; +reg data_48_V_ce0; +reg[2:0] data_49_V_address0; +reg data_49_V_ce0; +reg[2:0] data_50_V_address0; +reg data_50_V_ce0; +reg[2:0] data_51_V_address0; +reg data_51_V_ce0; +reg[2:0] data_52_V_address0; +reg data_52_V_ce0; +reg[2:0] data_53_V_address0; +reg data_53_V_ce0; +reg[2:0] data_54_V_address0; +reg data_54_V_ce0; +reg[2:0] data_55_V_address0; +reg data_55_V_ce0; +reg[2:0] data_56_V_address0; +reg data_56_V_ce0; +reg[2:0] data_57_V_address0; +reg data_57_V_ce0; +reg[2:0] data_58_V_address0; +reg data_58_V_ce0; +reg[2:0] data_59_V_address0; +reg data_59_V_ce0; +reg[2:0] data_60_V_address0; +reg data_60_V_ce0; +reg[2:0] data_61_V_address0; +reg data_61_V_ce0; +reg[2:0] data_62_V_address0; +reg data_62_V_ce0; +reg[2:0] data_63_V_address0; +reg data_63_V_ce0; +reg[2:0] data_64_V_address0; +reg data_64_V_ce0; +reg[2:0] data_65_V_address0; +reg data_65_V_ce0; +reg[2:0] data_66_V_address0; +reg data_66_V_ce0; +reg[2:0] data_67_V_address0; +reg data_67_V_ce0; +reg[2:0] data_68_V_address0; +reg data_68_V_ce0; +reg[2:0] data_69_V_address0; +reg data_69_V_ce0; +reg[2:0] data_70_V_address0; +reg data_70_V_ce0; +reg[2:0] data_71_V_address0; +reg data_71_V_ce0; +reg[2:0] data_72_V_address0; +reg data_72_V_ce0; +reg[2:0] data_73_V_address0; +reg data_73_V_ce0; +reg[2:0] data_74_V_address0; +reg data_74_V_ce0; +reg[2:0] data_75_V_address0; +reg data_75_V_ce0; +reg[2:0] data_76_V_address0; +reg data_76_V_ce0; +reg[2:0] data_77_V_address0; +reg data_77_V_ce0; +reg[2:0] data_78_V_address0; +reg data_78_V_ce0; +reg[2:0] data_79_V_address0; +reg data_79_V_ce0; +reg[2:0] data_80_V_address0; +reg data_80_V_ce0; +reg[2:0] data_81_V_address0; +reg data_81_V_ce0; +reg[2:0] data_82_V_address0; +reg data_82_V_ce0; +reg[2:0] data_83_V_address0; +reg data_83_V_ce0; +reg[2:0] data_84_V_address0; +reg data_84_V_ce0; +reg[2:0] data_85_V_address0; +reg data_85_V_ce0; +reg[2:0] data_86_V_address0; +reg data_86_V_ce0; +reg[2:0] data_87_V_address0; +reg data_87_V_ce0; +reg[2:0] data_88_V_address0; +reg data_88_V_ce0; +reg[2:0] data_89_V_address0; +reg data_89_V_ce0; +reg[2:0] data_90_V_address0; +reg data_90_V_ce0; +reg[2:0] data_91_V_address0; +reg data_91_V_ce0; +reg[2:0] data_92_V_address0; +reg data_92_V_ce0; +reg[2:0] data_93_V_address0; +reg data_93_V_ce0; +reg[2:0] data_94_V_address0; +reg data_94_V_ce0; +reg[2:0] data_95_V_address0; +reg data_95_V_ce0; +reg[2:0] data_96_V_address0; +reg data_96_V_ce0; +reg[2:0] data_97_V_address0; +reg data_97_V_ce0; +reg[2:0] data_98_V_address0; +reg data_98_V_ce0; +reg[2:0] data_99_V_address0; +reg data_99_V_ce0; +reg[2:0] data_100_V_address0; +reg data_100_V_ce0; +reg[2:0] data_101_V_address0; +reg data_101_V_ce0; +reg[2:0] data_102_V_address0; +reg data_102_V_ce0; +reg[2:0] data_103_V_address0; +reg data_103_V_ce0; +reg[2:0] data_104_V_address0; +reg data_104_V_ce0; +reg[2:0] data_105_V_address0; +reg data_105_V_ce0; +reg[2:0] data_106_V_address0; +reg data_106_V_ce0; +reg[2:0] data_107_V_address0; +reg data_107_V_ce0; +reg[2:0] data_108_V_address0; +reg data_108_V_ce0; +reg[2:0] data_109_V_address0; +reg data_109_V_ce0; +reg[2:0] data_110_V_address0; +reg data_110_V_ce0; +reg[2:0] data_111_V_address0; +reg data_111_V_ce0; +reg[2:0] data_112_V_address0; +reg data_112_V_ce0; +reg[2:0] data_113_V_address0; +reg data_113_V_ce0; +reg[2:0] data_114_V_address0; +reg data_114_V_ce0; +reg[2:0] data_115_V_address0; +reg data_115_V_ce0; +reg[2:0] data_116_V_address0; +reg data_116_V_ce0; +reg[2:0] data_117_V_address0; +reg data_117_V_ce0; +reg[2:0] data_118_V_address0; +reg data_118_V_ce0; +reg[2:0] data_119_V_address0; +reg data_119_V_ce0; +reg[2:0] data_120_V_address0; +reg data_120_V_ce0; +reg[2:0] data_121_V_address0; +reg data_121_V_ce0; +reg[2:0] data_122_V_address0; +reg data_122_V_ce0; +reg[2:0] data_123_V_address0; +reg data_123_V_ce0; +reg[2:0] data_124_V_address0; +reg data_124_V_ce0; +reg[2:0] data_125_V_address0; +reg data_125_V_ce0; +reg[2:0] data_126_V_address0; +reg data_126_V_ce0; +reg[2:0] data_127_V_address0; +reg data_127_V_ce0; +reg[4:0] res_0_V_address0; +reg res_0_V_ce0; +reg res_0_V_we0; +reg[4:0] res_1_V_address0; +reg res_1_V_ce0; +reg res_1_V_we0; +reg[4:0] res_2_V_address0; +reg res_2_V_ce0; +reg res_2_V_we0; +reg[4:0] res_3_V_address0; +reg res_3_V_ce0; +reg res_3_V_we0; +reg[4:0] res_4_V_address0; +reg res_4_V_ce0; +reg res_4_V_we0; +reg[4:0] res_5_V_address0; +reg res_5_V_ce0; +reg res_5_V_we0; +reg[4:0] res_6_V_address0; +reg res_6_V_ce0; +reg res_6_V_we0; +reg[4:0] res_7_V_address0; +reg res_7_V_ce0; +reg res_7_V_we0; +reg[4:0] res_8_V_address0; +reg res_8_V_ce0; +reg res_8_V_we0; +reg[4:0] res_9_V_address0; +reg res_9_V_ce0; +reg res_9_V_we0; +reg[4:0] res_10_V_address0; +reg res_10_V_ce0; +reg res_10_V_we0; +reg[4:0] res_11_V_address0; +reg res_11_V_ce0; +reg res_11_V_we0; +reg[4:0] res_12_V_address0; +reg res_12_V_ce0; +reg res_12_V_we0; +reg[4:0] res_13_V_address0; +reg res_13_V_ce0; +reg res_13_V_we0; +reg[4:0] res_14_V_address0; +reg res_14_V_ce0; +reg res_14_V_we0; +reg[4:0] res_15_V_address0; +reg res_15_V_ce0; +reg res_15_V_we0; +reg[4:0] res_16_V_address0; +reg res_16_V_ce0; +reg res_16_V_we0; +reg[4:0] res_17_V_address0; +reg res_17_V_ce0; +reg res_17_V_we0; +reg[4:0] res_18_V_address0; +reg res_18_V_ce0; +reg res_18_V_we0; +reg[4:0] res_19_V_address0; +reg res_19_V_ce0; +reg res_19_V_we0; +reg[4:0] res_20_V_address0; +reg res_20_V_ce0; +reg res_20_V_we0; +reg[4:0] res_21_V_address0; +reg res_21_V_ce0; +reg res_21_V_we0; +reg[4:0] res_22_V_address0; +reg res_22_V_ce0; +reg res_22_V_we0; +reg[4:0] res_23_V_address0; +reg res_23_V_ce0; +reg res_23_V_we0; +reg[4:0] res_24_V_address0; +reg res_24_V_ce0; +reg res_24_V_we0; +reg[4:0] res_25_V_address0; +reg res_25_V_ce0; +reg res_25_V_we0; +reg[4:0] res_26_V_address0; +reg res_26_V_ce0; +reg res_26_V_we0; +reg[4:0] res_27_V_address0; +reg res_27_V_ce0; +reg res_27_V_we0; +reg[4:0] res_28_V_address0; +reg res_28_V_ce0; +reg res_28_V_we0; +reg[4:0] res_29_V_address0; +reg res_29_V_ce0; +reg res_29_V_we0; +reg[4:0] res_30_V_address0; +reg res_30_V_ce0; +reg res_30_V_we0; +reg[4:0] res_31_V_address0; +reg res_31_V_ce0; +reg res_31_V_we0; +reg[4:0] res_32_V_address0; +reg res_32_V_ce0; +reg res_32_V_we0; +reg[4:0] res_33_V_address0; +reg res_33_V_ce0; +reg res_33_V_we0; +reg[4:0] res_34_V_address0; +reg res_34_V_ce0; +reg res_34_V_we0; +reg[4:0] res_35_V_address0; +reg res_35_V_ce0; +reg res_35_V_we0; +reg[4:0] res_36_V_address0; +reg res_36_V_ce0; +reg res_36_V_we0; +reg[4:0] res_37_V_address0; +reg res_37_V_ce0; +reg res_37_V_we0; +reg[4:0] res_38_V_address0; +reg res_38_V_ce0; +reg res_38_V_we0; +reg[4:0] res_39_V_address0; +reg res_39_V_ce0; +reg res_39_V_we0; +reg[4:0] res_40_V_address0; +reg res_40_V_ce0; +reg res_40_V_we0; +reg[4:0] res_41_V_address0; +reg res_41_V_ce0; +reg res_41_V_we0; +reg[4:0] res_42_V_address0; +reg res_42_V_ce0; +reg res_42_V_we0; +reg[4:0] res_43_V_address0; +reg res_43_V_ce0; +reg res_43_V_we0; +reg[4:0] res_44_V_address0; +reg res_44_V_ce0; +reg res_44_V_we0; +reg[4:0] res_45_V_address0; +reg res_45_V_ce0; +reg res_45_V_we0; +reg[4:0] res_46_V_address0; +reg res_46_V_ce0; +reg res_46_V_we0; +reg[4:0] res_47_V_address0; +reg res_47_V_ce0; +reg res_47_V_we0; +reg[4:0] res_48_V_address0; +reg res_48_V_ce0; +reg res_48_V_we0; +reg[4:0] res_49_V_address0; +reg res_49_V_ce0; +reg res_49_V_we0; +reg[4:0] res_50_V_address0; +reg res_50_V_ce0; +reg res_50_V_we0; +reg[4:0] res_51_V_address0; +reg res_51_V_ce0; +reg res_51_V_we0; +reg[4:0] res_52_V_address0; +reg res_52_V_ce0; +reg res_52_V_we0; +reg[4:0] res_53_V_address0; +reg res_53_V_ce0; +reg res_53_V_we0; +reg[4:0] res_54_V_address0; +reg res_54_V_ce0; +reg res_54_V_we0; +reg[4:0] res_55_V_address0; +reg res_55_V_ce0; +reg res_55_V_we0; +reg[4:0] res_56_V_address0; +reg res_56_V_ce0; +reg res_56_V_we0; +reg[4:0] res_57_V_address0; +reg res_57_V_ce0; +reg res_57_V_we0; +reg[4:0] res_58_V_address0; +reg res_58_V_ce0; +reg res_58_V_we0; +reg[4:0] res_59_V_address0; +reg res_59_V_ce0; +reg res_59_V_we0; +reg[4:0] res_60_V_address0; +reg res_60_V_ce0; +reg res_60_V_we0; +reg[4:0] res_61_V_address0; +reg res_61_V_ce0; +reg res_61_V_we0; +reg[4:0] res_62_V_address0; +reg res_62_V_ce0; +reg res_62_V_we0; +reg[4:0] res_63_V_address0; +reg res_63_V_ce0; +reg res_63_V_we0; +reg[4:0] res_64_V_address0; +reg res_64_V_ce0; +reg res_64_V_we0; +reg[4:0] res_65_V_address0; +reg res_65_V_ce0; +reg res_65_V_we0; +reg[4:0] res_66_V_address0; +reg res_66_V_ce0; +reg res_66_V_we0; +reg[4:0] res_67_V_address0; +reg res_67_V_ce0; +reg res_67_V_we0; +reg[4:0] res_68_V_address0; +reg res_68_V_ce0; +reg res_68_V_we0; +reg[4:0] res_69_V_address0; +reg res_69_V_ce0; +reg res_69_V_we0; +reg[4:0] res_70_V_address0; +reg res_70_V_ce0; +reg res_70_V_we0; +reg[4:0] res_71_V_address0; +reg res_71_V_ce0; +reg res_71_V_we0; +reg[4:0] res_72_V_address0; +reg res_72_V_ce0; +reg res_72_V_we0; +reg[4:0] res_73_V_address0; +reg res_73_V_ce0; +reg res_73_V_we0; +reg[4:0] res_74_V_address0; +reg res_74_V_ce0; +reg res_74_V_we0; +reg[4:0] res_75_V_address0; +reg res_75_V_ce0; +reg res_75_V_we0; +reg[4:0] res_76_V_address0; +reg res_76_V_ce0; +reg res_76_V_we0; +reg[4:0] res_77_V_address0; +reg res_77_V_ce0; +reg res_77_V_we0; +reg[4:0] res_78_V_address0; +reg res_78_V_ce0; +reg res_78_V_we0; +reg[4:0] res_79_V_address0; +reg res_79_V_ce0; +reg res_79_V_we0; +reg[4:0] res_80_V_address0; +reg res_80_V_ce0; +reg res_80_V_we0; +reg[4:0] res_81_V_address0; +reg res_81_V_ce0; +reg res_81_V_we0; +reg[4:0] res_82_V_address0; +reg res_82_V_ce0; +reg res_82_V_we0; +reg[4:0] res_83_V_address0; +reg res_83_V_ce0; +reg res_83_V_we0; +reg[4:0] res_84_V_address0; +reg res_84_V_ce0; +reg res_84_V_we0; +reg[4:0] res_85_V_address0; +reg res_85_V_ce0; +reg res_85_V_we0; +reg[4:0] res_86_V_address0; +reg res_86_V_ce0; +reg res_86_V_we0; +reg[4:0] res_87_V_address0; +reg res_87_V_ce0; +reg res_87_V_we0; +reg[4:0] res_88_V_address0; +reg res_88_V_ce0; +reg res_88_V_we0; +reg[4:0] res_89_V_address0; +reg res_89_V_ce0; +reg res_89_V_we0; +reg[4:0] res_90_V_address0; +reg res_90_V_ce0; +reg res_90_V_we0; +reg[4:0] res_91_V_address0; +reg res_91_V_ce0; +reg res_91_V_we0; +reg[4:0] res_92_V_address0; +reg res_92_V_ce0; +reg res_92_V_we0; +reg[4:0] res_93_V_address0; +reg res_93_V_ce0; +reg res_93_V_we0; +reg[4:0] res_94_V_address0; +reg res_94_V_ce0; +reg res_94_V_we0; +reg[4:0] res_95_V_address0; +reg res_95_V_ce0; +reg res_95_V_we0; +reg[4:0] res_96_V_address0; +reg res_96_V_ce0; +reg res_96_V_we0; +reg[4:0] res_97_V_address0; +reg res_97_V_ce0; +reg res_97_V_we0; +reg[4:0] res_98_V_address0; +reg res_98_V_ce0; +reg res_98_V_we0; +reg[4:0] res_99_V_address0; +reg res_99_V_ce0; +reg res_99_V_we0; +reg[4:0] res_100_V_address0; +reg res_100_V_ce0; +reg res_100_V_we0; +reg[4:0] res_101_V_address0; +reg res_101_V_ce0; +reg res_101_V_we0; +reg[4:0] res_102_V_address0; +reg res_102_V_ce0; +reg res_102_V_we0; +reg[4:0] res_103_V_address0; +reg res_103_V_ce0; +reg res_103_V_we0; +reg[4:0] res_104_V_address0; +reg res_104_V_ce0; +reg res_104_V_we0; +reg[4:0] res_105_V_address0; +reg res_105_V_ce0; +reg res_105_V_we0; +reg[4:0] res_106_V_address0; +reg res_106_V_ce0; +reg res_106_V_we0; +reg[4:0] res_107_V_address0; +reg res_107_V_ce0; +reg res_107_V_we0; +reg[4:0] res_108_V_address0; +reg res_108_V_ce0; +reg res_108_V_we0; +reg[4:0] res_109_V_address0; +reg res_109_V_ce0; +reg res_109_V_we0; +reg[4:0] res_110_V_address0; +reg res_110_V_ce0; +reg res_110_V_we0; +reg[4:0] res_111_V_address0; +reg res_111_V_ce0; +reg res_111_V_we0; +reg[4:0] res_112_V_address0; +reg res_112_V_ce0; +reg res_112_V_we0; +reg[4:0] res_113_V_address0; +reg res_113_V_ce0; +reg res_113_V_we0; +reg[4:0] res_114_V_address0; +reg res_114_V_ce0; +reg res_114_V_we0; +reg[4:0] res_115_V_address0; +reg res_115_V_ce0; +reg res_115_V_we0; +reg[4:0] res_116_V_address0; +reg res_116_V_ce0; +reg res_116_V_we0; +reg[4:0] res_117_V_address0; +reg res_117_V_ce0; +reg res_117_V_we0; +reg[4:0] res_118_V_address0; +reg res_118_V_ce0; +reg res_118_V_we0; +reg[4:0] res_119_V_address0; +reg res_119_V_ce0; +reg res_119_V_we0; +reg[4:0] res_120_V_address0; +reg res_120_V_ce0; +reg res_120_V_we0; +reg[4:0] res_121_V_address0; +reg res_121_V_ce0; +reg res_121_V_we0; +reg[4:0] res_122_V_address0; +reg res_122_V_ce0; +reg res_122_V_we0; +reg[4:0] res_123_V_address0; +reg res_123_V_ce0; +reg res_123_V_we0; +reg[4:0] res_124_V_address0; +reg res_124_V_ce0; +reg res_124_V_we0; +reg[4:0] res_125_V_address0; +reg res_125_V_ce0; +reg res_125_V_we0; +reg[4:0] res_126_V_address0; +reg res_126_V_ce0; +reg res_126_V_we0; +reg[4:0] res_127_V_address0; +reg res_127_V_ce0; +reg res_127_V_we0; + + reg [12:0] ap_CS_fsm; +reg [10:0] w5_V_address0; +reg w5_V_ce0; +wire [3:0] w5_V_q0; +wire [31:0] grp_fu_99041_p2; +reg [31:0] reg_99313; +wire [0:0] or_ln223_3_fu_102310_p2; +reg [0:0] or_ln223_reg_131762; +reg [7:0] reg_99318; +reg [6:0] add_ln1116_reg_131809; +reg [6:0] add_ln1116_4_reg_132207; +reg [6:0] add_ln1116_7_reg_132705; +reg [6:0] add_ln1116_16_reg_133103; +reg [6:0] add_ln1116_2_reg_135368; +reg [6:0] add_ln1116_6_reg_135778; +reg [6:0] add_ln1116_11_reg_136276; +reg [6:0] add_ln1116_19_reg_136674; +reg [6:0] add_ln1116_1_reg_138989; +reg [6:0] add_ln1116_5_reg_139399; +reg [6:0] add_ln1116_10_reg_139883; +reg [6:0] add_ln1116_18_reg_140281; +reg [6:0] add_ln1116_3_reg_142532; +reg [6:0] add_ln1116_9_reg_142942; +reg [6:0] add_ln1116_14_reg_143436; +reg [6:0] add_ln1116_23_reg_143834; +reg [7:0] reg_99338; +reg [7:0] reg_99358; +reg [7:0] reg_99378; +reg [7:0] reg_99398; +reg [7:0] reg_99418; +reg [7:0] reg_99438; +reg [7:0] reg_99458; +reg [7:0] reg_99478; +reg [7:0] reg_99498; +reg [7:0] reg_99518; +reg [7:0] reg_99538; +reg [7:0] reg_99558; +reg [7:0] reg_99578; +reg [7:0] reg_99598; +reg [7:0] reg_99618; +reg [7:0] reg_99638; +reg [7:0] reg_99658; +reg [7:0] reg_99678; +reg [7:0] reg_99698; +reg [7:0] reg_99718; +reg [7:0] reg_99738; +reg [7:0] reg_99758; +reg [7:0] reg_99778; +reg [7:0] reg_99798; +reg [7:0] reg_99818; +reg [7:0] reg_99838; +reg [7:0] reg_99858; +reg [7:0] reg_99878; +reg [7:0] reg_99898; +reg [7:0] reg_99918; +reg [7:0] reg_99938; +reg [7:0] reg_99958; +reg [7:0] reg_99978; +reg [7:0] reg_99998; +reg [7:0] reg_100018; +reg [7:0] reg_100038; +reg [7:0] reg_100058; +reg [7:0] reg_100078; +reg [7:0] reg_100098; +reg [7:0] reg_100118; +reg [7:0] reg_100138; +reg [7:0] reg_100158; +reg [7:0] reg_100178; +reg [7:0] reg_100198; +reg [7:0] reg_100218; +reg [7:0] reg_100238; +reg [7:0] reg_100258; +reg [7:0] reg_100278; +reg [7:0] reg_100298; +reg [7:0] reg_100318; +reg [7:0] reg_100338; +reg [7:0] reg_100358; +reg [7:0] reg_100378; +reg [7:0] reg_100398; +reg [7:0] reg_100418; +reg [7:0] reg_100438; +reg [7:0] reg_100458; +reg [7:0] reg_100478; +reg [7:0] reg_100498; +reg [7:0] reg_100518; +reg [7:0] reg_100538; +reg [7:0] reg_100558; +reg [7:0] reg_100578; +reg [7:0] reg_100598; +reg [6:0] add_ln1116_8_reg_133570; +reg [6:0] add_ln1116_17_reg_133975; +reg [6:0] add_ln1116_22_reg_134445; +reg [6:0] add_ln1116_28_reg_134850; +reg [6:0] add_ln1116_13_reg_137141; +reg [6:0] add_ln1116_21_reg_137546; +reg [6:0] add_ln1116_26_reg_138016; +reg [6:0] add_ln1116_30_reg_138421; +reg [6:0] add_ln1116_12_reg_140743; +reg [6:0] add_ln1116_20_reg_141148; +reg [6:0] add_ln1116_25_reg_141608; +reg [6:0] add_ln1116_29_reg_142013; +reg [6:0] add_ln1116_15_reg_144296; +reg [6:0] add_ln1116_24_reg_144701; +reg [6:0] add_ln1116_27_reg_145171; +reg [6:0] add_ln1116_31_reg_145576; +reg [3:0] reg_100634; +wire [31:0] grp_fu_99058_p2; +reg [31:0] reg_100638; +wire [0:0] or_ln223_15_fu_103192_p2; +reg [0:0] or_ln223_8_reg_132680; +reg [7:0] reg_100643; +reg [7:0] reg_100663; +reg [7:0] reg_100683; +reg [7:0] reg_100703; +reg [7:0] reg_100723; +reg [7:0] reg_100743; +reg [7:0] reg_100763; +reg [7:0] reg_100783; +reg [7:0] reg_100803; +reg [7:0] reg_100823; +reg [7:0] reg_100843; +reg [7:0] reg_100863; +reg [7:0] reg_100883; +reg [7:0] reg_100903; +reg [7:0] reg_100923; +reg [7:0] reg_100943; +reg [7:0] reg_100963; +reg [7:0] reg_100983; +reg [7:0] reg_101003; +reg [7:0] reg_101023; +reg [7:0] reg_101043; +reg [7:0] reg_101063; +reg [7:0] reg_101083; +reg [7:0] reg_101103; +reg [7:0] reg_101123; +reg [7:0] reg_101143; +reg [7:0] reg_101163; +reg [7:0] reg_101183; +reg [7:0] reg_101203; +reg [7:0] reg_101223; +reg [7:0] reg_101243; +reg [7:0] reg_101263; +reg [7:0] reg_101283; +reg [7:0] reg_101303; +reg [7:0] reg_101323; +reg [7:0] reg_101343; +reg [7:0] reg_101363; +reg [7:0] reg_101383; +reg [7:0] reg_101403; +reg [7:0] reg_101423; +reg [7:0] reg_101443; +reg [7:0] reg_101463; +reg [7:0] reg_101483; +reg [7:0] reg_101503; +reg [7:0] reg_101523; +reg [7:0] reg_101543; +reg [7:0] reg_101563; +reg [7:0] reg_101583; +reg [7:0] reg_101603; +reg [7:0] reg_101623; +reg [7:0] reg_101643; +reg [7:0] reg_101663; +reg [7:0] reg_101683; +reg [7:0] reg_101703; +reg [7:0] reg_101723; +reg [7:0] reg_101743; +reg [7:0] reg_101763; +reg [7:0] reg_101783; +reg [7:0] reg_101803; +reg [7:0] reg_101823; +reg [7:0] reg_101843; +reg [7:0] reg_101863; +reg [7:0] reg_101883; +wire [31:0] grp_fu_99126_p2; +reg [31:0] reg_101903; +wire [0:0] or_ln223_22_fu_106609_p2; +reg [0:0] or_ln223_13_reg_136251; +wire [31:0] grp_fu_99194_p2; +reg [31:0] reg_101908; +wire [0:0] or_ln223_21_fu_110053_p2; +reg [0:0] or_ln223_11_reg_139731; +wire [31:0] grp_fu_99262_p2; +reg [31:0] reg_101913; +wire [0:0] or_ln223_26_fu_113452_p2; +reg [0:0] or_ln223_19_reg_143411; +wire [31:0] oh_0_0_cast_fu_101918_p1; +reg [31:0] oh_0_0_cast_reg_131618; +wire [17:0] mul_ln201_fu_101932_p2; +reg [17:0] mul_ln201_reg_131633; +wire [0:0] icmp_ln199_fu_101926_p2; +wire [31:0] ow_0_0_0_cast_fu_101938_p1; +reg [31:0] ow_0_0_0_cast_reg_131639; +wire [14:0] mul_ln203_fu_101952_p2; +reg [14:0] mul_ln203_reg_131654; +wire [0:0] icmp_ln201_fu_101946_p2; +wire [31:0] zext_ln199_fu_101964_p1; +reg [31:0] zext_ln199_reg_131659; +wire [18:0] mul_ln201_1_fu_101972_p2; +reg [18:0] mul_ln201_1_reg_131671; +wire [10:0] add_ln203_12_fu_101978_p2; +reg [10:0] add_ln203_12_reg_131677; +wire [6:0] zext_ln203_4_fu_101984_p1; +reg [6:0] zext_ln203_4_reg_131682; +wire [3:0] add_ln203_fu_101994_p2; +reg [3:0] add_ln203_reg_131691; + wire [17:0] add_ln216_1_fu_102013_p2; +reg [17:0] add_ln216_1_reg_131696; +wire [0:0] icmp_ln203_fu_101988_p2; +wire [3:0] or_ln201_fu_102018_p2; +reg [3:0] or_ln201_reg_131702; +wire [31:0] zext_ln201_2_fu_102024_p1; +reg [31:0] zext_ln201_2_reg_131714; +wire [14:0] mul_ln203_2_fu_102032_p2; +reg [14:0] mul_ln203_2_reg_131726; +wire [1:0] trunc_ln221_fu_102048_p1; +reg [1:0] trunc_ln221_reg_131734; +wire [0:0] icmp_ln204_fu_102042_p2; +wire [31:0] sext_ln221_fu_102087_p1; +reg [31:0] sext_ln221_reg_131739; +wire [31:0] zext_ln216_3_fu_102091_p1; +reg [31:0] zext_ln216_3_reg_131745; +wire [10:0] sext_ln231_fu_102102_p1; +reg [10:0] sext_ln231_reg_131751; +wire [6:0] zext_ln231_fu_102114_p1; +reg [6:0] zext_ln231_reg_131757; +wire [0:0] or_ln223_fu_102155_p2; +wire [10:0] trunc_ln231_fu_102179_p1; +reg [10:0] trunc_ln231_reg_131766; +reg [2:0] tmp_4_reg_131771; +wire [31:0] add_ln216_4_fu_102222_p2; +reg [31:0] add_ln216_4_reg_131776; +wire [31:0] add_ln221_3_fu_102228_p2; +reg [31:0] add_ln221_3_reg_131782; +wire [10:0] add_ln231_fu_102233_p2; +reg [10:0] add_ln231_reg_131788; +wire [6:0] or_ln231_8_fu_102237_p4; +reg [6:0] or_ln231_8_reg_131794; +wire [63:0] zext_ln232_fu_102343_p1; +reg [63:0] zext_ln232_reg_131804; +wire [6:0] add_ln1116_fu_102347_p2; +reg [7:0] trunc_ln2_reg_132148; +reg [27:0] tmp_258_reg_132180; +wire [31:0] add_ln216_24_fu_102530_p2; +reg [31:0] add_ln216_24_reg_132191; +wire [0:0] icmp_ln208_fu_102524_p2; +wire [0:0] or_ln223_9_fu_102602_p2; +wire [63:0] zext_ln232_4_fu_102635_p1; +reg [63:0] zext_ln232_4_reg_132202; +wire [6:0] add_ln1116_4_fu_102639_p2; +wire [0:0] icmp_ln223_63_fu_102778_p2; +reg [0:0] icmp_ln223_63_reg_132539; +wire [0:0] icmp_ln206_fu_102733_p2; +wire [0:0] icmp_ln223_64_fu_102794_p2; +reg [0:0] icmp_ln223_64_reg_132544; +wire [31:0] add_ln216_29_fu_102823_p2; +reg [31:0] add_ln216_29_reg_132549; +wire [31:0] add_ln221_17_fu_102829_p2; +reg [31:0] add_ln221_17_reg_132555; +wire [6:0] trunc_ln231_23_fu_102834_p1; +reg [6:0] trunc_ln231_23_reg_132561; +wire [10:0] trunc_ln231_24_fu_102838_p1; +reg [10:0] trunc_ln231_24_reg_132566; +wire [31:0] sext_ln221_4_fu_102886_p1; +reg [31:0] sext_ln221_4_reg_132571; +wire [31:0] zext_ln216_8_fu_102890_p1; +reg [31:0] zext_ln216_8_reg_132577; +wire [2:0] or_ln231_fu_102893_p2; +reg [2:0] or_ln231_reg_132583; +wire [10:0] sext_ln231_4_fu_102907_p1; +reg [10:0] sext_ln231_4_reg_132588; +wire [6:0] zext_ln231_13_fu_102919_p1; +reg [6:0] zext_ln231_13_reg_132594; +reg [27:0] tmp_249_reg_132604; +reg [7:0] trunc_ln708_13_reg_132617; +reg [27:0] tmp_303_reg_132654; +wire [31:0] add_ln208_fu_103056_p2; +reg [27:0] tmp_279_reg_132672; +wire [0:0] or_ln223_8_fu_103116_p2; +wire [10:0] add_ln231_15_fu_103120_p2; +reg [10:0] add_ln231_15_reg_132684; +wire [6:0] add_ln231_16_fu_103124_p2; +reg [6:0] add_ln231_16_reg_132690; +wire [63:0] zext_ln232_7_fu_103225_p1; +reg [63:0] zext_ln232_7_reg_132700; +wire [6:0] add_ln1116_7_fu_103229_p2; +reg [7:0] trunc_ln708_15_reg_133044; +reg [27:0] tmp_329_reg_133076; +wire [31:0] add_ln216_56_fu_103412_p2; +reg [31:0] add_ln216_56_reg_133087; +wire [0:0] icmp_ln208_4_fu_103406_p2; +wire [0:0] or_ln223_28_fu_103484_p2; +wire [63:0] zext_ln232_16_fu_103517_p1; +reg [63:0] zext_ln232_16_reg_133098; +wire [6:0] add_ln1116_16_fu_103521_p2; +wire [31:0] add_ln206_fu_103609_p2; +reg [27:0] tmp_302_reg_133442; +reg [7:0] trunc_ln708_24_reg_133455; +reg [27:0] tmp_401_reg_133492; +wire [31:0] add_ln208_4_fu_103748_p2; +reg [27:0] tmp_378_reg_133510; +wire [0:0] icmp_ln223_67_fu_103823_p2; +reg [0:0] icmp_ln223_67_reg_133518; +wire [0:0] icmp_ln223_68_fu_103839_p2; +reg [0:0] icmp_ln223_68_reg_133523; +wire [10:0] trunc_ln231_25_fu_103863_p1; +reg [10:0] trunc_ln231_25_reg_133528; +wire [6:0] or_ln231_11_fu_103877_p4; +reg [6:0] or_ln231_11_reg_133533; +wire [0:0] or_ln223_10_fu_103910_p2; +reg [0:0] or_ln223_10_reg_133539; +wire [31:0] add_ln216_32_fu_103919_p2; +reg [31:0] add_ln216_32_reg_133543; +wire [31:0] add_ln221_20_fu_103925_p2; +reg [31:0] add_ln221_20_reg_133549; +wire [10:0] add_ln231_18_fu_103930_p2; +reg [10:0] add_ln231_18_reg_133555; +wire [0:0] or_ln223_18_fu_103998_p2; +reg [0:0] or_ln223_18_reg_133561; +wire [63:0] zext_ln232_8_fu_104031_p1; +reg [63:0] zext_ln232_8_reg_133565; +wire [6:0] add_ln1116_8_fu_104035_p2; +wire [31:0] grp_fu_99075_p2; +reg [31:0] add_ln216_82_reg_133894; +reg [31:0] add_ln216_88_reg_133905; +reg [7:0] trunc_ln708_16_reg_133916; +reg [27:0] tmp_338_reg_133948; +wire [31:0] add_ln216_57_fu_104216_p2; +reg [31:0] add_ln216_57_reg_133959; +wire [0:0] icmp_ln208_5_fu_104210_p2; +wire [0:0] or_ln223_30_fu_104288_p2; +wire [63:0] zext_ln232_17_fu_104321_p1; +reg [63:0] zext_ln232_17_reg_133970; +wire [6:0] add_ln1116_17_fu_104325_p2; +wire [0:0] icmp_ln223_105_fu_104463_p2; +reg [0:0] icmp_ln223_105_reg_134302; +wire [0:0] icmp_ln206_4_fu_104418_p2; +wire [0:0] icmp_ln223_106_fu_104479_p2; +reg [0:0] icmp_ln223_106_reg_134307; +wire [31:0] add_ln216_63_fu_104508_p2; +reg [31:0] add_ln216_63_reg_134312; +wire [31:0] add_ln221_44_fu_104514_p2; +reg [31:0] add_ln221_44_reg_134318; +wire [6:0] trunc_ln231_37_fu_104519_p1; +reg [6:0] trunc_ln231_37_reg_134324; +wire [10:0] trunc_ln231_38_fu_104523_p1; +reg [10:0] trunc_ln231_38_reg_134329; +wire [2:0] add_ln204_fu_104527_p2; +reg [27:0] tmp_316_reg_134344; +reg [7:0] trunc_ln708_25_reg_134357; +reg [27:0] tmp_411_reg_134394; +wire [31:0] add_ln208_5_fu_104665_p2; +reg [27:0] tmp_387_reg_134412; +wire [0:0] or_ln223_29_fu_104725_p2; +reg [0:0] or_ln223_29_reg_134420; +wire [10:0] add_ln231_54_fu_104729_p2; +reg [10:0] add_ln231_54_reg_134424; +wire [6:0] add_ln231_55_fu_104733_p2; +reg [6:0] add_ln231_55_reg_134430; +wire [0:0] or_ln223_37_fu_104801_p2; +reg [0:0] or_ln223_37_reg_134436; +wire [63:0] zext_ln232_22_fu_104834_p1; +reg [63:0] zext_ln232_22_reg_134440; +wire [6:0] add_ln1116_22_fu_104838_p2; +wire [31:0] grp_fu_99092_p2; +reg [31:0] add_ln216_97_reg_134769; +reg [31:0] add_ln216_100_reg_134780; +reg [7:0] trunc_ln708_30_reg_134791; +reg [27:0] tmp_432_reg_134823; +wire [31:0] add_ln216_76_fu_105019_p2; +reg [31:0] add_ln216_76_reg_134834; +wire [0:0] icmp_ln208_12_fu_105013_p2; +wire [0:0] or_ln223_44_fu_105091_p2; +reg [0:0] or_ln223_44_reg_134841; +wire [63:0] zext_ln232_28_fu_105124_p1; +reg [63:0] zext_ln232_28_reg_134845; +wire [6:0] add_ln1116_28_fu_105128_p2; +wire [31:0] add_ln206_4_fu_105215_p2; +reg [27:0] tmp_410_reg_135184; +reg [7:0] trunc_ln708_36_reg_135197; +reg [27:0] tmp_458_reg_135234; +wire [31:0] add_ln208_12_fu_105353_p2; +reg [27:0] tmp_451_reg_135252; +wire [10:0] add_ln203_14_fu_105413_p2; +reg [10:0] add_ln203_14_reg_135260; +wire [6:0] zext_ln203_14_fu_105419_p1; +reg [6:0] zext_ln203_14_reg_135265; +wire [3:0] add_ln203_2_fu_105429_p2; +reg [3:0] add_ln203_2_reg_135274; + wire [17:0] add_ln216_8_fu_105448_p2; +reg [17:0] add_ln216_8_reg_135279; +wire [0:0] icmp_ln203_2_fu_105423_p2; +wire [3:0] add_ln201_fu_105453_p2; +wire [1:0] trunc_ln221_2_fu_105469_p1; +reg [1:0] trunc_ln221_2_reg_135293; +wire [0:0] icmp_ln204_2_fu_105463_p2; +wire [31:0] sext_ln221_2_fu_105508_p1; +reg [31:0] sext_ln221_2_reg_135298; +wire [31:0] zext_ln216_6_fu_105512_p1; +reg [31:0] zext_ln216_6_reg_135304; +wire [10:0] sext_ln231_2_fu_105523_p1; +reg [10:0] sext_ln231_2_reg_135310; +wire [6:0] zext_ln231_2_fu_105535_p1; +reg [6:0] zext_ln231_2_reg_135316; +wire [0:0] or_ln223_2_fu_105576_p2; +reg [0:0] or_ln223_2_reg_135321; +wire [10:0] trunc_ln231_20_fu_105600_p1; +reg [10:0] trunc_ln231_20_reg_135325; +reg [2:0] tmp_5_reg_135330; +wire [31:0] add_ln216_16_fu_105643_p2; +reg [31:0] add_ln216_16_reg_135335; +wire [31:0] add_ln221_9_fu_105649_p2; +reg [31:0] add_ln221_9_reg_135341; +wire [10:0] add_ln231_4_fu_105654_p2; +reg [10:0] add_ln231_4_reg_135347; +wire [6:0] or_ln231_s_fu_105658_p4; +reg [6:0] or_ln231_s_reg_135353; +wire [0:0] or_ln223_6_fu_105731_p2; +reg [0:0] or_ln223_6_reg_135359; +wire [63:0] zext_ln232_2_fu_105763_p1; +reg [63:0] zext_ln232_2_reg_135363; +wire [6:0] add_ln1116_2_fu_105767_p2; +wire [31:0] grp_fu_99109_p2; +reg [31:0] add_ln216_55_reg_135697; +reg [31:0] add_ln216_75_reg_135708; +reg [7:0] trunc_ln708_11_reg_135719; +reg [27:0] tmp_264_reg_135751; +wire [31:0] add_ln216_27_fu_105949_p2; +reg [31:0] add_ln216_27_reg_135762; +wire [0:0] icmp_ln208_2_fu_105943_p2; +wire [0:0] or_ln223_14_fu_106021_p2; +wire [63:0] zext_ln232_6_fu_106053_p1; +reg [63:0] zext_ln232_6_reg_135773; +wire [6:0] add_ln1116_6_fu_106057_p2; +wire [0:0] icmp_ln223_73_fu_106196_p2; +reg [0:0] icmp_ln223_73_reg_136110; +wire [0:0] icmp_ln206_2_fu_106151_p2; +wire [0:0] icmp_ln223_74_fu_106212_p2; +reg [0:0] icmp_ln223_74_reg_136115; +wire [31:0] add_ln216_41_fu_106241_p2; +reg [31:0] add_ln216_41_reg_136120; +wire [31:0] add_ln221_25_fu_106247_p2; +reg [31:0] add_ln221_25_reg_136126; +wire [6:0] trunc_ln231_28_fu_106252_p1; +reg [6:0] trunc_ln231_28_reg_136132; +wire [10:0] trunc_ln231_29_fu_106256_p1; +reg [10:0] trunc_ln231_29_reg_136137; +wire [31:0] sext_ln221_6_fu_106304_p1; +reg [31:0] sext_ln221_6_reg_136142; +wire [31:0] zext_ln216_10_fu_106308_p1; +reg [31:0] zext_ln216_10_reg_136148; +wire [2:0] or_ln231_20_fu_106311_p2; +reg [2:0] or_ln231_20_reg_136154; +wire [10:0] sext_ln231_6_fu_106325_p1; +reg [10:0] sext_ln231_6_reg_136159; +wire [6:0] zext_ln231_17_fu_106337_p1; +reg [6:0] zext_ln231_17_reg_136165; +reg [27:0] tmp_257_reg_136175; +reg [7:0] trunc_ln708_s_reg_136188; +reg [27:0] tmp_328_reg_136225; +wire [31:0] add_ln208_2_fu_106473_p2; +reg [27:0] tmp_299_reg_136243; +wire [0:0] or_ln223_13_fu_106533_p2; +wire [10:0] add_ln231_24_fu_106537_p2; +reg [10:0] add_ln231_24_reg_136255; +wire [6:0] add_ln231_25_fu_106541_p2; +reg [6:0] add_ln231_25_reg_136261; +wire [63:0] zext_ln232_11_fu_106641_p1; +reg [63:0] zext_ln232_11_reg_136271; +wire [6:0] add_ln1116_11_fu_106645_p2; +reg [7:0] trunc_ln708_19_reg_136615; +reg [27:0] tmp_348_reg_136647; +wire [31:0] add_ln216_59_fu_106828_p2; +reg [31:0] add_ln216_59_reg_136658; +wire [0:0] icmp_ln208_7_fu_106822_p2; +wire [0:0] or_ln223_32_fu_106900_p2; +wire [63:0] zext_ln232_19_fu_106932_p1; +reg [63:0] zext_ln232_19_reg_136669; +wire [6:0] add_ln1116_19_fu_106936_p2; +wire [31:0] add_ln206_2_fu_107024_p2; +reg [27:0] tmp_327_reg_137013; +reg [7:0] trunc_ln708_27_reg_137026; +reg [27:0] tmp_423_reg_137063; +wire [31:0] add_ln208_7_fu_107163_p2; +reg [27:0] tmp_398_reg_137081; +wire [0:0] icmp_ln223_81_fu_107238_p2; +reg [0:0] icmp_ln223_81_reg_137089; +wire [0:0] icmp_ln223_82_fu_107254_p2; +reg [0:0] icmp_ln223_82_reg_137094; +wire [10:0] trunc_ln231_32_fu_107278_p1; +reg [10:0] trunc_ln231_32_reg_137099; +wire [6:0] or_ln231_16_fu_107292_p4; +reg [6:0] or_ln231_16_reg_137104; +wire [0:0] or_ln223_17_fu_107325_p2; +reg [0:0] or_ln223_17_reg_137110; +wire [31:0] add_ln216_47_fu_107334_p2; +reg [31:0] add_ln216_47_reg_137114; +wire [31:0] add_ln221_31_fu_107340_p2; +reg [31:0] add_ln221_31_reg_137120; +wire [10:0] add_ln231_31_fu_107345_p2; +reg [10:0] add_ln231_31_reg_137126; +wire [0:0] or_ln223_25_fu_107413_p2; +reg [0:0] or_ln223_25_reg_137132; +wire [63:0] zext_ln232_13_fu_107445_p1; +reg [63:0] zext_ln232_13_reg_137136; +wire [6:0] add_ln1116_13_fu_107449_p2; +wire [31:0] grp_fu_99143_p2; +reg [31:0] add_ln216_87_reg_137465; +reg [31:0] add_ln216_94_reg_137476; +reg [7:0] trunc_ln708_21_reg_137487; +reg [27:0] tmp_355_reg_137519; +wire [31:0] add_ln216_62_fu_107630_p2; +reg [31:0] add_ln216_62_reg_137530; +wire [0:0] icmp_ln208_9_fu_107624_p2; +wire [0:0] or_ln223_36_fu_107702_p2; +wire [63:0] zext_ln232_21_fu_107734_p1; +reg [63:0] zext_ln232_21_reg_137541; +wire [6:0] add_ln1116_21_fu_107738_p2; +wire [0:0] icmp_ln223_117_fu_107876_p2; +reg [0:0] icmp_ln223_117_reg_137873; +wire [0:0] icmp_ln206_6_fu_107831_p2; +wire [0:0] icmp_ln223_118_fu_107892_p2; +reg [0:0] icmp_ln223_118_reg_137878; +wire [31:0] add_ln216_71_fu_107921_p2; +reg [31:0] add_ln216_71_reg_137883; +wire [31:0] add_ln221_50_fu_107927_p2; +reg [31:0] add_ln221_50_reg_137889; +wire [6:0] trunc_ln231_41_fu_107932_p1; +reg [6:0] trunc_ln231_41_reg_137895; +wire [10:0] trunc_ln231_42_fu_107936_p1; +reg [10:0] trunc_ln231_42_reg_137900; +wire [2:0] add_ln204_2_fu_107940_p2; +reg [27:0] tmp_337_reg_137915; +reg [7:0] trunc_ln708_29_reg_137928; +reg [27:0] tmp_431_reg_137965; +wire [31:0] add_ln208_9_fu_108078_p2; +reg [27:0] tmp_409_reg_137983; +wire [0:0] or_ln223_35_fu_108138_p2; +reg [0:0] or_ln223_35_reg_137991; +wire [10:0] add_ln231_64_fu_108142_p2; +reg [10:0] add_ln231_64_reg_137995; +wire [6:0] add_ln231_66_fu_108146_p2; +reg [6:0] add_ln231_66_reg_138001; +wire [0:0] or_ln223_42_fu_108214_p2; +reg [0:0] or_ln223_42_reg_138007; +wire [63:0] zext_ln232_26_fu_108246_p1; +reg [63:0] zext_ln232_26_reg_138011; +wire [6:0] add_ln1116_26_fu_108250_p2; +wire [31:0] grp_fu_99160_p2; +reg [31:0] add_ln216_99_reg_138340; +reg [31:0] add_ln216_103_reg_138351; +reg [7:0] trunc_ln708_34_reg_138362; +reg [27:0] tmp_443_reg_138394; +wire [31:0] add_ln216_78_fu_108431_p2; +reg [31:0] add_ln216_78_reg_138405; +wire [0:0] icmp_ln208_14_fu_108425_p2; +wire [0:0] or_ln223_46_fu_108503_p2; +reg [0:0] or_ln223_46_reg_138412; +wire [63:0] zext_ln232_30_fu_108535_p1; +reg [63:0] zext_ln232_30_reg_138416; +wire [6:0] add_ln1116_30_fu_108539_p2; +wire [31:0] add_ln206_6_fu_108626_p2; +reg [27:0] tmp_430_reg_138755; +reg [7:0] trunc_ln708_38_reg_138768; +reg [27:0] tmp_463_reg_138805; +wire [31:0] add_ln208_14_fu_108764_p2; +reg [27:0] tmp_457_reg_138823; +wire [31:0] ow_0_1_0_cast_fu_108824_p1; +reg [31:0] ow_0_1_0_cast_reg_138831; +wire [14:0] mul_ln203_1_fu_108838_p2; +reg [14:0] mul_ln203_1_reg_138846; +wire [0:0] icmp_ln201_1_fu_108832_p2; +wire [3:0] add_ln199_fu_108844_p2; +wire [10:0] add_ln203_13_fu_108850_p2; +reg [10:0] add_ln203_13_reg_138856; +wire [6:0] zext_ln203_9_fu_108856_p1; +reg [6:0] zext_ln203_9_reg_138861; +wire [3:0] add_ln203_1_fu_108866_p2; +reg [3:0] add_ln203_1_reg_138870; + wire [18:0] add_ln216_6_fu_108885_p2; +reg [18:0] add_ln216_6_reg_138875; +wire [0:0] icmp_ln203_1_fu_108860_p2; +wire [3:0] or_ln201_1_fu_108890_p2; +reg [3:0] or_ln201_1_reg_138881; +wire [31:0] zext_ln201_3_fu_108896_p1; +reg [31:0] zext_ln201_3_reg_138893; +wire [14:0] mul_ln203_3_fu_108904_p2; +reg [14:0] mul_ln203_3_reg_138905; +wire [1:0] trunc_ln221_1_fu_108920_p1; +reg [1:0] trunc_ln221_1_reg_138913; +wire [0:0] icmp_ln204_1_fu_108914_p2; +wire [31:0] sext_ln221_1_fu_108959_p1; +reg [31:0] sext_ln221_1_reg_138918; +wire [31:0] zext_ln216_5_fu_108963_p1; +reg [31:0] zext_ln216_5_reg_138924; +wire [6:0] zext_ln231_1_fu_108982_p1; +reg [6:0] zext_ln231_1_reg_138930; +wire [10:0] sext_ln231_1_fu_108986_p1; +reg [10:0] sext_ln231_1_reg_138936; +wire [0:0] or_ln223_1_fu_109027_p2; +reg [0:0] or_ln223_1_reg_138942; +wire [6:0] trunc_ln231_18_fu_109051_p1; +reg [6:0] trunc_ln231_18_reg_138946; +wire [10:0] trunc_ln231_19_fu_109055_p1; +reg [10:0] trunc_ln231_19_reg_138951; +wire [31:0] add_ln216_11_fu_109088_p2; +reg [31:0] add_ln216_11_reg_138956; +wire [31:0] add_ln221_6_fu_109094_p2; +reg [31:0] add_ln221_6_reg_138962; +wire [10:0] add_ln231_1_fu_109099_p2; +reg [10:0] add_ln231_1_reg_138968; +wire [6:0] add_ln231_3_fu_109103_p2; +reg [6:0] add_ln231_3_reg_138974; +wire [0:0] or_ln223_5_fu_109171_p2; +reg [0:0] or_ln223_5_reg_138980; +wire [63:0] zext_ln232_1_fu_109204_p1; +reg [63:0] zext_ln232_1_reg_138984; +wire [6:0] add_ln1116_1_fu_109208_p2; +wire [31:0] grp_fu_99177_p2; +reg [31:0] add_ln216_52_reg_139318; +reg [31:0] add_ln216_72_reg_139329; +reg [7:0] trunc_ln708_10_reg_139340; +reg [27:0] tmp_263_reg_139372; +wire [31:0] add_ln216_26_fu_109390_p2; +reg [31:0] add_ln216_26_reg_139383; +wire [0:0] icmp_ln208_1_fu_109384_p2; +wire [0:0] or_ln223_12_fu_109462_p2; +wire [63:0] zext_ln232_5_fu_109495_p1; +reg [63:0] zext_ln232_5_reg_139394; +wire [6:0] add_ln1116_5_fu_109499_p2; +wire [0:0] or_ln223_11_fu_109660_p2; +wire [0:0] icmp_ln206_1_fu_109593_p2; +wire [31:0] add_ln216_37_fu_109689_p2; +reg [31:0] add_ln216_37_reg_139735; +wire [31:0] add_ln221_23_fu_109695_p2; +reg [31:0] add_ln221_23_reg_139741; +wire [6:0] trunc_ln231_26_fu_109700_p1; +reg [6:0] trunc_ln231_26_reg_139747; +wire [10:0] trunc_ln231_27_fu_109704_p1; +reg [10:0] trunc_ln231_27_reg_139752; +wire [31:0] sext_ln221_5_fu_109752_p1; +reg [31:0] sext_ln221_5_reg_139757; +wire [31:0] zext_ln216_9_fu_109756_p1; +reg [31:0] zext_ln216_9_reg_139763; +wire [6:0] zext_ln231_16_fu_109781_p1; +reg [6:0] zext_ln231_16_reg_139769; +wire [10:0] sext_ln231_5_fu_109785_p1; +reg [10:0] sext_ln231_5_reg_139775; +reg [27:0] tmp_256_reg_139786; +reg [7:0] trunc_ln708_14_reg_139799; +reg [27:0] tmp_324_reg_139836; +wire [31:0] add_ln208_1_fu_109921_p2; +reg [27:0] tmp_296_reg_139854; +wire [10:0] add_ln231_21_fu_109981_p2; +reg [10:0] add_ln231_21_reg_139862; +wire [6:0] add_ln231_22_fu_109985_p2; +reg [6:0] add_ln231_22_reg_139868; +wire [63:0] zext_ln232_10_fu_110086_p1; +reg [63:0] zext_ln232_10_reg_139878; +wire [6:0] add_ln1116_10_fu_110090_p2; +reg [7:0] trunc_ln708_18_reg_140222; +reg [27:0] tmp_347_reg_140254; +wire [31:0] add_ln216_58_fu_110273_p2; +reg [31:0] add_ln216_58_reg_140265; +wire [0:0] icmp_ln208_6_fu_110267_p2; +wire [0:0] or_ln223_31_fu_110345_p2; +wire [63:0] zext_ln232_18_fu_110378_p1; +reg [63:0] zext_ln232_18_reg_140276; +wire [6:0] add_ln1116_18_fu_110382_p2; +wire [31:0] add_ln206_1_fu_110470_p2; +reg [27:0] tmp_323_reg_140620; +reg [7:0] trunc_ln708_26_reg_140633; +reg [27:0] tmp_420_reg_140670; +wire [31:0] add_ln208_6_fu_110609_p2; +reg [27:0] tmp_393_reg_140688; +wire [0:0] or_ln223_16_fu_110706_p2; +reg [0:0] or_ln223_16_reg_140696; +wire [6:0] trunc_ln231_30_fu_110730_p1; +reg [6:0] trunc_ln231_30_reg_140700; +wire [10:0] trunc_ln231_31_fu_110734_p1; +reg [10:0] trunc_ln231_31_reg_140705; +wire [31:0] add_ln216_44_fu_110767_p2; +reg [31:0] add_ln216_44_reg_140710; +wire [31:0] add_ln221_28_fu_110773_p2; +reg [31:0] add_ln221_28_reg_140716; +wire [10:0] add_ln231_27_fu_110778_p2; +reg [10:0] add_ln231_27_reg_140722; +wire [6:0] add_ln231_28_fu_110782_p2; +reg [6:0] add_ln231_28_reg_140728; +wire [0:0] or_ln223_24_fu_110850_p2; +reg [0:0] or_ln223_24_reg_140734; +wire [63:0] zext_ln232_12_fu_110883_p1; +reg [63:0] zext_ln232_12_reg_140738; +wire [6:0] add_ln1116_12_fu_110887_p2; +wire [31:0] grp_fu_99211_p2; +reg [31:0] add_ln216_86_reg_141067; +reg [31:0] add_ln216_93_reg_141078; +reg [7:0] trunc_ln708_20_reg_141089; +reg [27:0] tmp_354_reg_141121; +wire [31:0] add_ln216_61_fu_111068_p2; +reg [31:0] add_ln216_61_reg_141132; +wire [0:0] icmp_ln208_8_fu_111062_p2; +wire [0:0] or_ln223_34_fu_111140_p2; +wire [63:0] zext_ln232_20_fu_111173_p1; +reg [63:0] zext_ln232_20_reg_141143; +wire [6:0] add_ln1116_20_fu_111177_p2; +wire [0:0] or_ln223_33_fu_111337_p2; +reg [0:0] or_ln223_33_reg_141475; +wire [0:0] icmp_ln206_5_fu_111270_p2; +wire [31:0] add_ln216_67_fu_111366_p2; +reg [31:0] add_ln216_67_reg_141479; +wire [31:0] add_ln221_48_fu_111372_p2; +reg [31:0] add_ln221_48_reg_141485; +wire [6:0] trunc_ln231_39_fu_111377_p1; +reg [6:0] trunc_ln231_39_reg_141491; +wire [10:0] trunc_ln231_40_fu_111381_p1; +reg [10:0] trunc_ln231_40_reg_141496; +wire [2:0] add_ln204_1_fu_111385_p2; +reg [27:0] tmp_336_reg_141511; +reg [7:0] trunc_ln708_28_reg_141524; +reg [27:0] tmp_429_reg_141561; +wire [31:0] add_ln208_8_fu_111523_p2; +reg [27:0] tmp_408_reg_141579; +wire [10:0] add_ln231_60_fu_111583_p2; +reg [10:0] add_ln231_60_reg_141587; +wire [6:0] add_ln231_61_fu_111587_p2; +reg [6:0] add_ln231_61_reg_141593; +wire [0:0] or_ln223_41_fu_111655_p2; +reg [0:0] or_ln223_41_reg_141599; +wire [63:0] zext_ln232_25_fu_111688_p1; +reg [63:0] zext_ln232_25_reg_141603; +wire [6:0] add_ln1116_25_fu_111692_p2; +wire [31:0] grp_fu_99228_p2; +reg [31:0] add_ln216_98_reg_141932; +reg [31:0] add_ln216_102_reg_141943; +reg [7:0] trunc_ln708_33_reg_141954; +reg [27:0] tmp_442_reg_141986; +wire [31:0] add_ln216_77_fu_111873_p2; +reg [31:0] add_ln216_77_reg_141997; +wire [0:0] icmp_ln208_13_fu_111867_p2; +wire [0:0] or_ln223_45_fu_111945_p2; +reg [0:0] or_ln223_45_reg_142004; +wire [63:0] zext_ln232_29_fu_111978_p1; +reg [63:0] zext_ln232_29_reg_142008; +wire [6:0] add_ln1116_29_fu_111982_p2; +wire [31:0] add_ln206_5_fu_112069_p2; +reg [27:0] tmp_428_reg_142347; +reg [7:0] trunc_ln708_37_reg_142360; +reg [27:0] tmp_462_reg_142397; +wire [31:0] add_ln208_13_fu_112207_p2; +reg [27:0] tmp_456_reg_142415; +wire [10:0] add_ln203_15_fu_112267_p2; +reg [10:0] add_ln203_15_reg_142423; +wire [6:0] zext_ln203_23_fu_112273_p1; +reg [6:0] zext_ln203_23_reg_142428; +wire [3:0] add_ln203_3_fu_112283_p2; +reg [3:0] add_ln203_3_reg_142437; + wire [18:0] add_ln216_14_fu_112302_p2; +reg [18:0] add_ln216_14_reg_142442; +wire [0:0] icmp_ln203_3_fu_112277_p2; +wire [3:0] add_ln201_1_fu_112307_p2; +wire [1:0] trunc_ln221_3_fu_112323_p1; +reg [1:0] trunc_ln221_3_reg_142456; +wire [0:0] icmp_ln204_3_fu_112317_p2; +wire [31:0] sext_ln221_3_fu_112362_p1; +reg [31:0] sext_ln221_3_reg_142461; +wire [31:0] zext_ln216_7_fu_112366_p1; +reg [31:0] zext_ln216_7_reg_142467; +wire [6:0] zext_ln231_3_fu_112385_p1; +reg [6:0] zext_ln231_3_reg_142473; +wire [10:0] sext_ln231_3_fu_112389_p1; +reg [10:0] sext_ln231_3_reg_142479; +wire [0:0] or_ln223_4_fu_112430_p2; +reg [0:0] or_ln223_4_reg_142485; +wire [6:0] trunc_ln231_21_fu_112454_p1; +reg [6:0] trunc_ln231_21_reg_142489; +wire [10:0] trunc_ln231_22_fu_112458_p1; +reg [10:0] trunc_ln231_22_reg_142494; +wire [31:0] add_ln216_22_fu_112491_p2; +reg [31:0] add_ln216_22_reg_142499; +wire [31:0] add_ln221_12_fu_112497_p2; +reg [31:0] add_ln221_12_reg_142505; +wire [10:0] add_ln231_7_fu_112502_p2; +reg [10:0] add_ln231_7_reg_142511; +wire [6:0] add_ln231_9_fu_112506_p2; +reg [6:0] add_ln231_9_reg_142517; +wire [0:0] or_ln223_7_fu_112574_p2; +reg [0:0] or_ln223_7_reg_142523; +wire [63:0] zext_ln232_3_fu_112606_p1; +reg [63:0] zext_ln232_3_reg_142527; +wire [6:0] add_ln1116_3_fu_112610_p2; +wire [31:0] grp_fu_99245_p2; +reg [31:0] add_ln216_70_reg_142861; +reg [31:0] add_ln216_80_reg_142872; +reg [7:0] trunc_ln708_12_reg_142883; +reg [27:0] tmp_268_reg_142915; +wire [31:0] add_ln216_36_fu_112792_p2; +reg [31:0] add_ln216_36_reg_142926; +wire [0:0] icmp_ln208_3_fu_112786_p2; +wire [0:0] or_ln223_20_fu_112864_p2; +wire [63:0] zext_ln232_9_fu_112896_p1; +reg [63:0] zext_ln232_9_reg_142937; +wire [6:0] add_ln1116_9_fu_112900_p2; +wire [0:0] icmp_ln223_85_fu_113039_p2; +reg [0:0] icmp_ln223_85_reg_143274; +wire [0:0] icmp_ln206_3_fu_112994_p2; +wire [0:0] icmp_ln223_86_fu_113055_p2; +reg [0:0] icmp_ln223_86_reg_143279; +wire [31:0] add_ln216_51_fu_113084_p2; +reg [31:0] add_ln216_51_reg_143284; +wire [31:0] add_ln221_33_fu_113090_p2; +reg [31:0] add_ln221_33_reg_143290; +wire [6:0] trunc_ln231_33_fu_113095_p1; +reg [6:0] trunc_ln231_33_reg_143296; +wire [10:0] trunc_ln231_34_fu_113099_p1; +reg [10:0] trunc_ln231_34_reg_143301; +wire [31:0] sext_ln221_7_fu_113147_p1; +reg [31:0] sext_ln221_7_reg_143306; +wire [31:0] zext_ln216_11_fu_113151_p1; +reg [31:0] zext_ln216_11_reg_143312; +wire [6:0] zext_ln231_24_fu_113176_p1; +reg [6:0] zext_ln231_24_reg_143318; +wire [10:0] sext_ln231_7_fu_113180_p1; +reg [10:0] sext_ln231_7_reg_143324; +reg [27:0] tmp_262_reg_143335; +reg [7:0] trunc_ln708_17_reg_143348; +reg [27:0] tmp_346_reg_143385; +wire [31:0] add_ln208_3_fu_113316_p2; +reg [27:0] tmp_320_reg_143403; +wire [0:0] or_ln223_19_fu_113376_p2; +wire [10:0] add_ln231_36_fu_113380_p2; +reg [10:0] add_ln231_36_reg_143415; +wire [6:0] add_ln231_37_fu_113384_p2; +reg [6:0] add_ln231_37_reg_143421; +wire [63:0] zext_ln232_14_fu_113484_p1; +reg [63:0] zext_ln232_14_reg_143431; +wire [6:0] add_ln1116_14_fu_113488_p2; +reg [7:0] trunc_ln708_22_reg_143775; +reg [27:0] tmp_362_reg_143807; +wire [31:0] add_ln216_65_fu_113671_p2; +reg [31:0] add_ln216_65_reg_143818; +wire [0:0] icmp_ln208_10_fu_113665_p2; +wire [0:0] or_ln223_38_fu_113743_p2; +wire [63:0] zext_ln232_23_fu_113775_p1; +reg [63:0] zext_ln232_23_reg_143829; +wire [6:0] add_ln1116_23_fu_113779_p2; +wire [31:0] add_ln206_3_fu_113867_p2; +reg [27:0] tmp_345_reg_144173; +reg [7:0] trunc_ln708_31_reg_144186; +reg [27:0] tmp_438_reg_144223; +wire [31:0] add_ln208_10_fu_114006_p2; +reg [27:0] tmp_417_reg_144241; +wire [0:0] or_ln223_23_fu_114103_p2; +reg [0:0] or_ln223_23_reg_144249; +wire [6:0] trunc_ln231_35_fu_114127_p1; +reg [6:0] trunc_ln231_35_reg_144253; +wire [10:0] trunc_ln231_36_fu_114131_p1; +reg [10:0] trunc_ln231_36_reg_144258; +wire [31:0] add_ln216_54_fu_114164_p2; +reg [31:0] add_ln216_54_reg_144263; +wire [31:0] add_ln221_36_fu_114170_p2; +reg [31:0] add_ln221_36_reg_144269; +wire [10:0] add_ln231_40_fu_114175_p2; +reg [10:0] add_ln231_40_reg_144275; +wire [6:0] add_ln231_42_fu_114179_p2; +reg [6:0] add_ln231_42_reg_144281; +wire [0:0] or_ln223_27_fu_114247_p2; +reg [0:0] or_ln223_27_reg_144287; +wire [63:0] zext_ln232_15_fu_114279_p1; +reg [63:0] zext_ln232_15_reg_144291; +wire [6:0] add_ln1116_15_fu_114283_p2; +wire [31:0] grp_fu_99279_p2; +reg [31:0] add_ln216_92_reg_144620; +reg [31:0] add_ln216_96_reg_144631; +reg [7:0] trunc_ln708_23_reg_144642; +reg [27:0] tmp_367_reg_144674; +wire [31:0] add_ln216_68_fu_114464_p2; +reg [31:0] add_ln216_68_reg_144685; +wire [0:0] icmp_ln208_11_fu_114458_p2; +wire [0:0] or_ln223_40_fu_114536_p2; +wire [63:0] zext_ln232_24_fu_114568_p1; +reg [63:0] zext_ln232_24_reg_144696; +wire [6:0] add_ln1116_24_fu_114572_p2; +wire [0:0] icmp_ln223_125_fu_114710_p2; +reg [0:0] icmp_ln223_125_reg_145028; +wire [0:0] icmp_ln206_7_fu_114665_p2; +wire [0:0] icmp_ln223_126_fu_114726_p2; +reg [0:0] icmp_ln223_126_reg_145033; +wire [31:0] add_ln216_74_fu_114755_p2; +reg [31:0] add_ln216_74_reg_145038; +wire [31:0] add_ln221_52_fu_114761_p2; +reg [31:0] add_ln221_52_reg_145044; +wire [6:0] trunc_ln231_43_fu_114766_p1; +reg [6:0] trunc_ln231_43_reg_145050; +wire [10:0] trunc_ln231_44_fu_114770_p1; +reg [10:0] trunc_ln231_44_reg_145055; +wire [2:0] add_ln204_3_fu_114774_p2; +reg [27:0] tmp_353_reg_145070; +reg [7:0] trunc_ln708_32_reg_145083; +reg [27:0] tmp_441_reg_145120; +wire [31:0] add_ln208_11_fu_114912_p2; +reg [27:0] tmp_427_reg_145138; +wire [0:0] or_ln223_39_fu_114972_p2; +reg [0:0] or_ln223_39_reg_145146; +wire [10:0] add_ln231_73_fu_114976_p2; +reg [10:0] add_ln231_73_reg_145150; +wire [6:0] add_ln231_75_fu_114980_p2; +reg [6:0] add_ln231_75_reg_145156; +wire [0:0] or_ln223_43_fu_115048_p2; +reg [0:0] or_ln223_43_reg_145162; +wire [63:0] zext_ln232_27_fu_115080_p1; +reg [63:0] zext_ln232_27_reg_145166; +wire [6:0] add_ln1116_27_fu_115084_p2; +wire [31:0] grp_fu_99296_p2; +reg [31:0] add_ln216_101_reg_145495; +reg [31:0] add_ln216_104_reg_145506; +reg [7:0] trunc_ln708_35_reg_145517; +reg [27:0] tmp_447_reg_145549; +wire [31:0] add_ln216_79_fu_115265_p2; +reg [31:0] add_ln216_79_reg_145560; +wire [0:0] icmp_ln208_15_fu_115259_p2; +wire [0:0] or_ln223_47_fu_115337_p2; +reg [0:0] or_ln223_47_reg_145567; +wire [63:0] zext_ln232_31_fu_115369_p1; +reg [63:0] zext_ln232_31_reg_145571; +wire [6:0] add_ln1116_31_fu_115373_p2; +wire [31:0] add_ln206_7_fu_115460_p2; +reg [27:0] tmp_440_reg_145910; +reg [7:0] trunc_ln708_39_reg_145923; +reg [27:0] tmp_464_reg_145960; +wire [31:0] add_ln208_15_fu_115598_p2; +reg [27:0] tmp_461_reg_145978; +wire [12:0] mul_ln250_fu_115668_p2; +reg [12:0] mul_ln250_reg_145989; +wire [0:0] icmp_ln244_fu_115662_p2; +wire [12:0] add_ln250_fu_115714_p2; +reg [12:0] add_ln250_reg_145998; +wire [0:0] icmp_ln246_fu_115674_p2; +wire [5:0] trunc_ln250_fu_115719_p1; +reg [5:0] trunc_ln250_reg_146004; +wire [12:0] mul_ln250_1_fu_115733_p2; +reg [12:0] mul_ln250_1_reg_146010; +wire [12:0] add_ln250_4_fu_115925_p2; +reg [12:0] add_ln250_4_reg_146022; +wire [0:0] icmp_ln248_fu_115743_p2; +wire [5:0] trunc_ln250_5_fu_115930_p1; +reg [5:0] trunc_ln250_5_reg_146028; +wire [7:0] phi_ln203_4_fu_115953_p18; +reg [7:0] phi_ln203_4_reg_146034; +wire [5:0] add_ln203_7_fu_116022_p2; +reg [5:0] add_ln203_7_reg_146071; +reg [5:0] acc_0_V_addr_48_reg_146075; +reg [5:0] acc_2_V_addr_48_reg_146080; +reg [5:0] acc_4_V_addr_48_reg_146085; +reg [5:0] acc_6_V_addr_48_reg_146090; +reg [5:0] acc_8_V_addr_48_reg_146095; +reg [5:0] acc_10_V_addr_48_reg_146100; +reg [5:0] acc_12_V_addr_48_reg_146105; +reg [5:0] acc_14_V_addr_48_reg_146110; +reg [5:0] acc_16_V_addr_48_reg_146115; +reg [5:0] acc_18_V_addr_48_reg_146120; +reg [5:0] acc_20_V_addr_48_reg_146125; +reg [5:0] acc_22_V_addr_48_reg_146130; +reg [5:0] acc_24_V_addr_48_reg_146135; +reg [5:0] acc_26_V_addr_48_reg_146140; +reg [5:0] acc_28_V_addr_48_reg_146145; +reg [5:0] acc_30_V_addr_48_reg_146150; +reg [5:0] acc_32_V_addr_48_reg_146155; +reg [5:0] acc_34_V_addr_48_reg_146160; +reg [5:0] acc_36_V_addr_48_reg_146165; +reg [5:0] acc_38_V_addr_48_reg_146170; +reg [5:0] acc_40_V_addr_48_reg_146175; +reg [5:0] acc_42_V_addr_48_reg_146180; +reg [5:0] acc_44_V_addr_48_reg_146185; +reg [5:0] acc_46_V_addr_48_reg_146190; +reg [5:0] acc_48_V_addr_47_reg_146195; +reg [5:0] acc_50_V_addr_47_reg_146200; +reg [5:0] acc_52_V_addr_47_reg_146205; +reg [5:0] acc_54_V_addr_47_reg_146210; +reg [5:0] acc_56_V_addr_47_reg_146215; +reg [5:0] acc_58_V_addr_47_reg_146220; +reg [5:0] acc_60_V_addr_47_reg_146225; +reg [5:0] acc_62_V_addr_47_reg_146230; +reg [5:0] acc_63_V_addr_47_reg_146235; +wire [3:0] add_ln248_fu_116109_p2; +wire [3:0] add_ln246_fu_116261_p2; +wire [0:0] icmp_ln248_2_fu_116119_p2; +wire [7:0] phi_ln203_6_fu_116286_p18; +reg [7:0] phi_ln203_6_reg_146256; +wire [5:0] add_ln203_10_fu_116355_p2; +reg [5:0] add_ln203_10_reg_146293; +reg [5:0] acc_0_V_addr_51_reg_146297; +reg [5:0] acc_2_V_addr_51_reg_146302; +reg [5:0] acc_4_V_addr_51_reg_146307; +reg [5:0] acc_6_V_addr_51_reg_146312; +reg [5:0] acc_8_V_addr_51_reg_146317; +reg [5:0] acc_10_V_addr_51_reg_146322; +reg [5:0] acc_12_V_addr_51_reg_146327; +reg [5:0] acc_14_V_addr_51_reg_146332; +reg [5:0] acc_16_V_addr_51_reg_146337; +reg [5:0] acc_18_V_addr_51_reg_146342; +reg [5:0] acc_20_V_addr_51_reg_146347; +reg [5:0] acc_22_V_addr_51_reg_146352; +reg [5:0] acc_24_V_addr_51_reg_146357; +reg [5:0] acc_26_V_addr_51_reg_146362; +reg [5:0] acc_28_V_addr_51_reg_146367; +reg [5:0] acc_30_V_addr_51_reg_146372; +reg [5:0] acc_32_V_addr_51_reg_146377; +reg [5:0] acc_34_V_addr_51_reg_146382; +reg [5:0] acc_36_V_addr_51_reg_146387; +reg [5:0] acc_38_V_addr_51_reg_146392; +reg [5:0] acc_40_V_addr_51_reg_146397; +reg [5:0] acc_42_V_addr_51_reg_146402; +reg [5:0] acc_44_V_addr_51_reg_146407; +reg [5:0] acc_46_V_addr_51_reg_146412; +reg [5:0] acc_48_V_addr_50_reg_146417; +reg [5:0] acc_50_V_addr_50_reg_146422; +reg [5:0] acc_52_V_addr_50_reg_146427; +reg [5:0] acc_54_V_addr_50_reg_146432; +reg [5:0] acc_56_V_addr_50_reg_146437; +reg [5:0] acc_58_V_addr_50_reg_146442; +reg [5:0] acc_60_V_addr_50_reg_146447; +reg [5:0] acc_62_V_addr_50_reg_146452; +reg [5:0] acc_63_V_addr_50_reg_146457; +wire [3:0] add_ln248_2_fu_116442_p2; +wire [12:0] add_ln250_2_fu_116488_p2; +reg [12:0] add_ln250_2_reg_146470; +wire [0:0] icmp_ln246_1_fu_116448_p2; +wire [5:0] trunc_ln250_4_fu_116493_p1; +reg [5:0] trunc_ln250_4_reg_146476; +wire [3:0] add_ln244_fu_116497_p2; +wire [12:0] add_ln250_6_fu_116689_p2; +reg [12:0] add_ln250_6_reg_146493; +wire [0:0] icmp_ln248_1_fu_116507_p2; +wire [5:0] trunc_ln250_6_fu_116694_p1; +reg [5:0] trunc_ln250_6_reg_146499; +wire [7:0] phi_ln203_5_fu_116717_p18; +reg [7:0] phi_ln203_5_reg_146505; +wire [5:0] add_ln203_9_fu_116786_p2; +reg [5:0] add_ln203_9_reg_146542; +reg [5:0] acc_0_V_addr_50_reg_146546; +reg [5:0] acc_2_V_addr_50_reg_146551; +reg [5:0] acc_4_V_addr_50_reg_146556; +reg [5:0] acc_6_V_addr_50_reg_146561; +reg [5:0] acc_8_V_addr_50_reg_146566; +reg [5:0] acc_10_V_addr_50_reg_146571; +reg [5:0] acc_12_V_addr_50_reg_146576; +reg [5:0] acc_14_V_addr_50_reg_146581; +reg [5:0] acc_16_V_addr_50_reg_146586; +reg [5:0] acc_18_V_addr_50_reg_146591; +reg [5:0] acc_20_V_addr_50_reg_146596; +reg [5:0] acc_22_V_addr_50_reg_146601; +reg [5:0] acc_24_V_addr_50_reg_146606; +reg [5:0] acc_26_V_addr_50_reg_146611; +reg [5:0] acc_28_V_addr_50_reg_146616; +reg [5:0] acc_30_V_addr_50_reg_146621; +reg [5:0] acc_32_V_addr_50_reg_146626; +reg [5:0] acc_34_V_addr_50_reg_146631; +reg [5:0] acc_36_V_addr_50_reg_146636; +reg [5:0] acc_38_V_addr_50_reg_146641; +reg [5:0] acc_40_V_addr_50_reg_146646; +reg [5:0] acc_42_V_addr_50_reg_146651; +reg [5:0] acc_44_V_addr_50_reg_146656; +reg [5:0] acc_46_V_addr_50_reg_146661; +reg [5:0] acc_48_V_addr_49_reg_146666; +reg [5:0] acc_50_V_addr_49_reg_146671; +reg [5:0] acc_52_V_addr_49_reg_146676; +reg [5:0] acc_54_V_addr_49_reg_146681; +reg [5:0] acc_56_V_addr_49_reg_146686; +reg [5:0] acc_58_V_addr_49_reg_146691; +reg [5:0] acc_60_V_addr_49_reg_146696; +reg [5:0] acc_62_V_addr_49_reg_146701; +reg [5:0] acc_63_V_addr_49_reg_146706; +wire [3:0] add_ln248_1_fu_116873_p2; +wire [3:0] add_ln246_1_fu_117025_p2; +wire [0:0] icmp_ln248_3_fu_116883_p2; +wire [7:0] phi_ln203_7_fu_117050_p18; +reg [7:0] phi_ln203_7_reg_146727; +wire [5:0] add_ln203_11_fu_117119_p2; +reg [5:0] add_ln203_11_reg_146764; +reg [5:0] acc_0_V_addr_52_reg_146768; +reg [5:0] acc_2_V_addr_52_reg_146773; +reg [5:0] acc_4_V_addr_52_reg_146778; +reg [5:0] acc_6_V_addr_52_reg_146783; +reg [5:0] acc_8_V_addr_52_reg_146788; +reg [5:0] acc_10_V_addr_52_reg_146793; +reg [5:0] acc_12_V_addr_52_reg_146798; +reg [5:0] acc_14_V_addr_52_reg_146803; +reg [5:0] acc_16_V_addr_52_reg_146808; +reg [5:0] acc_18_V_addr_52_reg_146813; +reg [5:0] acc_20_V_addr_52_reg_146818; +reg [5:0] acc_22_V_addr_52_reg_146823; +reg [5:0] acc_24_V_addr_52_reg_146828; +reg [5:0] acc_26_V_addr_52_reg_146833; +reg [5:0] acc_28_V_addr_52_reg_146838; +reg [5:0] acc_30_V_addr_52_reg_146843; +reg [5:0] acc_32_V_addr_52_reg_146848; +reg [5:0] acc_34_V_addr_52_reg_146853; +reg [5:0] acc_36_V_addr_52_reg_146858; +reg [5:0] acc_38_V_addr_52_reg_146863; +reg [5:0] acc_40_V_addr_52_reg_146868; +reg [5:0] acc_42_V_addr_52_reg_146873; +reg [5:0] acc_44_V_addr_52_reg_146878; +reg [5:0] acc_46_V_addr_52_reg_146883; +reg [5:0] acc_48_V_addr_51_reg_146888; +reg [5:0] acc_50_V_addr_51_reg_146893; +reg [5:0] acc_52_V_addr_51_reg_146898; +reg [5:0] acc_54_V_addr_51_reg_146903; +reg [5:0] acc_56_V_addr_51_reg_146908; +reg [5:0] acc_58_V_addr_51_reg_146913; +reg [5:0] acc_60_V_addr_51_reg_146918; +reg [5:0] acc_62_V_addr_51_reg_146923; +reg [5:0] acc_63_V_addr_51_reg_146928; +wire [3:0] add_ln248_3_fu_117206_p2; +wire [17:0] mul_ln279_2_fu_117226_p2; +reg [17:0] mul_ln279_2_reg_146941; +wire [0:0] icmp_ln257_fu_117220_p2; +wire [12:0] mul_ln279_fu_117232_p2; +reg [12:0] mul_ln279_reg_146947; +wire [12:0] add_ln279_fu_117282_p2; +reg [12:0] add_ln279_reg_147596; +wire [0:0] icmp_ln259_fu_117242_p2; +wire [5:0] trunc_ln279_fu_117287_p1; +reg [5:0] trunc_ln279_reg_147602; +wire [17:0] grp_fu_131406_p3; +reg [17:0] add_ln276_reg_147608; +wire [18:0] mul_ln279_3_fu_117305_p2; +reg [18:0] mul_ln279_3_reg_147614; +wire [12:0] mul_ln279_1_fu_117311_p2; +reg [12:0] mul_ln279_1_reg_147620; +wire [5:0] add_ln1265_fu_117340_p2; +reg [5:0] add_ln1265_reg_147629; +wire [0:0] icmp_ln261_fu_117325_p2; +reg [5:0] acc_0_V_addr_37_reg_147633; +reg [5:0] acc_1_V_addr_37_reg_147639; +reg [5:0] acc_2_V_addr_37_reg_147644; +reg [5:0] acc_3_V_addr_37_reg_147650; +reg [5:0] acc_4_V_addr_37_reg_147655; +reg [5:0] acc_5_V_addr_37_reg_147661; +reg [5:0] acc_6_V_addr_37_reg_147666; +reg [5:0] acc_7_V_addr_37_reg_147672; +reg [5:0] acc_8_V_addr_37_reg_147677; +reg [5:0] acc_9_V_addr_37_reg_147683; +reg [5:0] acc_10_V_addr_37_reg_147688; +reg [5:0] acc_11_V_addr_37_reg_147694; +reg [5:0] acc_12_V_addr_37_reg_147699; +reg [5:0] acc_13_V_addr_37_reg_147705; +reg [5:0] acc_14_V_addr_37_reg_147710; +reg [5:0] acc_15_V_addr_37_reg_147716; +reg [5:0] acc_16_V_addr_37_reg_147721; +reg [5:0] acc_17_V_addr_37_reg_147727; +reg [5:0] acc_18_V_addr_37_reg_147732; +reg [5:0] acc_19_V_addr_37_reg_147738; +reg [5:0] acc_20_V_addr_37_reg_147743; +reg [5:0] acc_21_V_addr_37_reg_147749; +reg [5:0] acc_22_V_addr_37_reg_147754; +reg [5:0] acc_23_V_addr_37_reg_147760; +reg [5:0] acc_24_V_addr_37_reg_147765; +reg [5:0] acc_25_V_addr_37_reg_147771; +reg [5:0] acc_26_V_addr_37_reg_147776; +reg [5:0] acc_27_V_addr_37_reg_147782; +reg [5:0] acc_28_V_addr_37_reg_147787; +reg [5:0] acc_29_V_addr_37_reg_147793; +reg [5:0] acc_30_V_addr_37_reg_147798; +reg [5:0] acc_31_V_addr_37_reg_147804; +reg [5:0] acc_32_V_addr_37_reg_147809; +reg [5:0] acc_33_V_addr_37_reg_147815; +reg [5:0] acc_34_V_addr_37_reg_147820; +reg [5:0] acc_35_V_addr_37_reg_147826; +reg [5:0] acc_36_V_addr_37_reg_147831; +reg [5:0] acc_37_V_addr_37_reg_147837; +reg [5:0] acc_38_V_addr_37_reg_147842; +reg [5:0] acc_39_V_addr_37_reg_147848; +reg [5:0] acc_40_V_addr_37_reg_147853; +reg [5:0] acc_41_V_addr_37_reg_147859; +reg [5:0] acc_42_V_addr_37_reg_147864; +reg [5:0] acc_43_V_addr_37_reg_147870; +reg [5:0] acc_44_V_addr_37_reg_147875; +reg [5:0] acc_45_V_addr_37_reg_147881; +reg [5:0] acc_46_V_addr_37_reg_147886; +reg [5:0] acc_47_V_addr_37_reg_147892; +reg [5:0] acc_48_V_addr_36_reg_147897; +reg [5:0] acc_49_V_addr_36_reg_147903; +reg [5:0] acc_50_V_addr_36_reg_147908; +reg [5:0] acc_51_V_addr_36_reg_147914; +reg [5:0] acc_52_V_addr_36_reg_147919; +reg [5:0] acc_53_V_addr_36_reg_147925; +reg [5:0] acc_54_V_addr_36_reg_147930; +reg [5:0] acc_55_V_addr_36_reg_147936; +reg [5:0] acc_56_V_addr_36_reg_147941; +reg [5:0] acc_57_V_addr_36_reg_147947; +reg [5:0] acc_58_V_addr_36_reg_147952; +reg [5:0] acc_59_V_addr_36_reg_147958; +reg [5:0] acc_60_V_addr_36_reg_147963; +reg [5:0] acc_61_V_addr_36_reg_147969; +reg [5:0] acc_62_V_addr_36_reg_147974; +reg [5:0] acc_63_V_addr_36_reg_147980; +wire [17:0] grp_fu_131413_p3; +reg [17:0] add_ln276_2_reg_147986; +wire [12:0] add_ln279_4_fu_117471_p2; +reg [12:0] add_ln279_4_reg_147992; +wire [5:0] trunc_ln279_11_fu_117476_p1; +reg [5:0] trunc_ln279_11_reg_147998; +wire [17:0] grp_fu_131420_p3; +reg [17:0] add_ln276_6_reg_148004; +wire [31:0] zext_ln276_fu_117490_p1; +reg [31:0] zext_ln276_reg_148013; +wire [0:0] icmp_ln264_fu_117484_p2; +wire [5:0] add_ln1265_3_fu_117516_p2; +reg [5:0] add_ln1265_3_reg_148019; +reg [5:0] acc_0_V_addr_41_reg_148023; +reg [5:0] acc_1_V_addr_41_reg_148029; +reg [5:0] acc_2_V_addr_41_reg_148035; +reg [5:0] acc_3_V_addr_41_reg_148041; +reg [5:0] acc_4_V_addr_41_reg_148047; +reg [5:0] acc_5_V_addr_41_reg_148053; +reg [5:0] acc_6_V_addr_41_reg_148059; +reg [5:0] acc_7_V_addr_41_reg_148065; +reg [5:0] acc_8_V_addr_41_reg_148071; +reg [5:0] acc_9_V_addr_41_reg_148077; +reg [5:0] acc_10_V_addr_41_reg_148083; +reg [5:0] acc_11_V_addr_41_reg_148089; +reg [5:0] acc_12_V_addr_41_reg_148095; +reg [5:0] acc_13_V_addr_41_reg_148101; +reg [5:0] acc_14_V_addr_41_reg_148107; +reg [5:0] acc_15_V_addr_41_reg_148113; +reg [5:0] acc_16_V_addr_41_reg_148119; +reg [5:0] acc_17_V_addr_41_reg_148125; +reg [5:0] acc_18_V_addr_41_reg_148131; +reg [5:0] acc_19_V_addr_41_reg_148137; +reg [5:0] acc_20_V_addr_41_reg_148143; +reg [5:0] acc_21_V_addr_41_reg_148149; +reg [5:0] acc_22_V_addr_41_reg_148155; +reg [5:0] acc_23_V_addr_41_reg_148161; +reg [5:0] acc_24_V_addr_41_reg_148167; +reg [5:0] acc_25_V_addr_41_reg_148173; +reg [5:0] acc_26_V_addr_41_reg_148179; +reg [5:0] acc_27_V_addr_41_reg_148185; +reg [5:0] acc_28_V_addr_41_reg_148191; +reg [5:0] acc_29_V_addr_41_reg_148197; +reg [5:0] acc_30_V_addr_41_reg_148203; +reg [5:0] acc_31_V_addr_41_reg_148209; +reg [5:0] acc_32_V_addr_41_reg_148215; +reg [5:0] acc_33_V_addr_41_reg_148221; +reg [5:0] acc_34_V_addr_41_reg_148227; +reg [5:0] acc_35_V_addr_41_reg_148233; +reg [5:0] acc_36_V_addr_41_reg_148239; +reg [5:0] acc_37_V_addr_41_reg_148245; +reg [5:0] acc_38_V_addr_41_reg_148251; +reg [5:0] acc_39_V_addr_41_reg_148257; +reg [5:0] acc_40_V_addr_41_reg_148263; +reg [5:0] acc_41_V_addr_41_reg_148269; +reg [5:0] acc_42_V_addr_41_reg_148275; +reg [5:0] acc_43_V_addr_41_reg_148281; +reg [5:0] acc_44_V_addr_41_reg_148287; +reg [5:0] acc_45_V_addr_41_reg_148293; +reg [5:0] acc_46_V_addr_41_reg_148299; +reg [5:0] acc_47_V_addr_41_reg_148305; +reg [5:0] acc_48_V_addr_40_reg_148311; +reg [5:0] acc_49_V_addr_40_reg_148317; +reg [5:0] acc_50_V_addr_40_reg_148323; +reg [5:0] acc_51_V_addr_40_reg_148329; +reg [5:0] acc_52_V_addr_40_reg_148335; +reg [5:0] acc_53_V_addr_40_reg_148341; +reg [5:0] acc_54_V_addr_40_reg_148347; +reg [5:0] acc_55_V_addr_40_reg_148353; +reg [5:0] acc_56_V_addr_40_reg_148359; +reg [5:0] acc_57_V_addr_40_reg_148365; +reg [5:0] acc_58_V_addr_40_reg_148371; +reg [5:0] acc_59_V_addr_40_reg_148377; +reg [5:0] acc_60_V_addr_40_reg_148383; +reg [5:0] acc_61_V_addr_40_reg_148389; +reg [5:0] acc_62_V_addr_40_reg_148395; +reg [5:0] acc_63_V_addr_40_reg_148401; +wire [17:0] grp_fu_131435_p3; +reg [17:0] add_ln276_10_reg_148407; +wire [31:0] add_ln276_4_fu_117614_p2; +reg [31:0] add_ln276_4_reg_148413; +wire [7:0] acc_42_V_q1; +wire [7:0] acc_30_V_q1; +wire [7:0] acc_48_V_q1; +wire [7:0] acc_28_V_q1; +wire [7:0] acc_38_V_q1; +wire [7:0] acc_26_V_q1; +wire [7:0] acc_50_V_q1; +wire [7:0] acc_24_V_q1; +wire [7:0] acc_44_V_q1; +wire [7:0] acc_22_V_q1; +wire [7:0] acc_52_V_q1; +wire [7:0] acc_20_V_q1; +wire [7:0] acc_36_V_q1; +wire [7:0] acc_18_V_q1; +wire [7:0] acc_54_V_q1; +wire [7:0] acc_16_V_q1; +wire [7:0] acc_40_V_q1; +wire [7:0] acc_14_V_q1; +wire [7:0] acc_56_V_q1; +wire [7:0] acc_12_V_q1; +wire [7:0] acc_34_V_q1; +wire [7:0] acc_10_V_q1; +wire [7:0] acc_58_V_q1; +wire [7:0] acc_8_V_q1; +wire [7:0] acc_46_V_q1; +wire [7:0] acc_6_V_q1; +wire [7:0] acc_60_V_q1; +wire [7:0] acc_4_V_q1; +wire [7:0] acc_32_V_q1; +wire [7:0] acc_2_V_q1; +wire [7:0] acc_62_V_q1; +wire [7:0] acc_0_V_q1; +wire [7:0] acc_63_V_q1; +wire [31:0] add_ln276_78_fu_117620_p2; +reg [31:0] add_ln276_78_reg_148584; +reg [27:0] tmp_261_reg_148595; +wire [7:0] tmp_6_fu_117681_p30; +reg [7:0] tmp_6_reg_148740; +wire [7:0] add_ln703_fu_117743_p2; +reg [7:0] add_ln703_reg_148745; +wire [31:0] add_ln276_43_fu_117824_p2; +reg [31:0] add_ln276_43_reg_148753; +wire [0:0] icmp_ln268_fu_117818_p2; +wire [31:0] add_ln276_47_fu_117858_p2; +reg [31:0] add_ln276_47_reg_148762; +wire [0:0] icmp_ln266_fu_117841_p2; +wire [31:0] zext_ln276_8_fu_117878_p1; +reg [31:0] zext_ln276_8_reg_148768; +reg [27:0] tmp_269_reg_148779; +wire [7:0] tmp_10_fu_117931_p30; +reg [7:0] tmp_10_reg_148924; +wire [31:0] add_ln268_fu_118030_p2; +wire [31:0] add_ln276_103_fu_118036_p2; +reg [31:0] add_ln276_103_reg_149099; +reg [27:0] tmp_307_reg_149110; +wire [7:0] tmp_96_fu_118097_p30; +reg [7:0] tmp_96_reg_149255; +wire [7:0] add_ln703_15_fu_118159_p2; +reg [7:0] add_ln703_15_reg_149260; +wire [31:0] add_ln276_104_fu_118240_p2; +reg [31:0] add_ln276_104_reg_149268; +wire [0:0] icmp_ln268_8_fu_118234_p2; +wire [31:0] add_ln266_fu_118251_p2; +reg [27:0] tmp_342_reg_149284; +wire [7:0] tmp_119_fu_118307_p30; +reg [7:0] tmp_119_reg_149429; +wire [31:0] add_ln268_8_fu_118406_p2; +wire [31:0] add_ln276_52_fu_118423_p2; +reg [31:0] add_ln276_52_reg_149439; +wire [31:0] add_ln276_107_fu_118429_p2; +reg [31:0] add_ln276_107_reg_149610; +reg [27:0] tmp_317_reg_149621; +wire [7:0] tmp_105_fu_118490_p30; +reg [7:0] tmp_105_reg_149766; +wire [7:0] add_ln703_16_fu_118552_p2; +reg [7:0] add_ln703_16_reg_149771; +wire [31:0] add_ln276_108_fu_118633_p2; +reg [31:0] add_ln276_108_reg_149779; +wire [0:0] icmp_ln268_9_fu_118627_p2; +wire [31:0] add_ln276_114_fu_118667_p2; +reg [31:0] add_ln276_114_reg_149788; +wire [0:0] icmp_ln266_8_fu_118650_p2; +wire [2:0] add_ln264_fu_118673_p2; +reg [27:0] tmp_352_reg_149804; +wire [7:0] tmp_124_fu_118729_p30; +reg [7:0] tmp_124_reg_149949; +wire [31:0] add_ln268_9_fu_118828_p2; +wire [31:0] add_ln276_161_fu_118834_p2; +reg [31:0] add_ln276_161_reg_150124; +reg [27:0] tmp_382_reg_150135; +wire [7:0] tmp_147_fu_118895_p30; +reg [7:0] tmp_147_reg_150280; +wire [7:0] add_ln703_46_fu_118957_p2; +reg [7:0] add_ln703_46_reg_150285; +wire [31:0] add_ln276_147_fu_119038_p2; +reg [31:0] add_ln276_147_reg_150293; +wire [0:0] icmp_ln268_24_fu_119032_p2; +wire [31:0] add_ln266_8_fu_119049_p2; +reg [27:0] tmp_412_reg_150309; +wire [7:0] tmp_159_fu_119105_p30; +reg [7:0] tmp_159_reg_150454; +wire [31:0] add_ln268_24_fu_119204_p2; +wire [31:0] zext_ln276_3_fu_119220_p1; +reg [31:0] zext_ln276_3_reg_150467; +wire [0:0] icmp_ln264_3_fu_119214_p2; +wire [3:0] add_ln261_fu_119223_p2; +wire [31:0] add_ln276_22_fu_119240_p2; +reg [31:0] add_ln276_22_reg_150478; +wire [7:0] acc_47_V_q0; +wire [7:0] acc_29_V_q0; +wire [7:0] acc_43_V_q0; +wire [7:0] acc_27_V_q0; +wire [7:0] acc_49_V_q0; +wire [7:0] acc_25_V_q0; +wire [7:0] acc_37_V_q0; +wire [7:0] acc_23_V_q0; +wire [7:0] acc_51_V_q0; +wire [7:0] acc_21_V_q0; +wire [7:0] acc_41_V_q0; +wire [7:0] acc_19_V_q0; +wire [7:0] acc_53_V_q0; +wire [7:0] acc_17_V_q0; +wire [7:0] acc_35_V_q0; +wire [7:0] acc_15_V_q0; +wire [7:0] acc_55_V_q0; +wire [7:0] acc_13_V_q0; +wire [7:0] acc_45_V_q0; +wire [7:0] acc_11_V_q0; +wire [7:0] acc_57_V_q0; +wire [7:0] acc_9_V_q0; +wire [7:0] acc_33_V_q0; +wire [7:0] acc_7_V_q0; +wire [7:0] acc_59_V_q0; +wire [7:0] acc_5_V_q0; +wire [7:0] acc_39_V_q0; +wire [7:0] acc_3_V_q0; +wire [7:0] acc_61_V_q0; +wire [7:0] acc_1_V_q0; +wire [7:0] acc_31_V_q0; +wire [7:0] acc_63_V_q0; +wire [31:0] add_ln276_89_fu_119246_p2; +reg [31:0] add_ln276_89_reg_150644; +reg [27:0] tmp_267_reg_150655; +wire [7:0] tmp_9_fu_119307_p30; +reg [7:0] tmp_9_reg_150800; +wire [7:0] add_ln703_3_fu_119369_p2; +reg [7:0] add_ln703_3_reg_150805; +wire [31:0] add_ln276_50_fu_119450_p2; +reg [31:0] add_ln276_50_reg_150813; +wire [0:0] icmp_ln268_3_fu_119444_p2; +wire [31:0] add_ln276_65_fu_119484_p2; +reg [31:0] add_ln276_65_reg_150822; +wire [0:0] icmp_ln266_3_fu_119467_p2; +wire [31:0] zext_ln276_11_fu_119504_p1; +reg [31:0] zext_ln276_11_reg_150828; +reg [27:0] tmp_282_reg_150839; +wire [7:0] tmp_74_fu_119557_p30; +reg [7:0] tmp_74_reg_150984; +wire [31:0] add_ln268_3_fu_119655_p2; +wire [7:0] acc_47_V_q1; +wire [7:0] acc_29_V_q1; +wire [7:0] acc_43_V_q1; +wire [7:0] acc_27_V_q1; +wire [7:0] acc_49_V_q1; +wire [7:0] acc_25_V_q1; +wire [7:0] acc_37_V_q1; +wire [7:0] acc_23_V_q1; +wire [7:0] acc_51_V_q1; +wire [7:0] acc_21_V_q1; +wire [7:0] acc_41_V_q1; +wire [7:0] acc_19_V_q1; +wire [7:0] acc_53_V_q1; +wire [7:0] acc_17_V_q1; +wire [7:0] acc_35_V_q1; +wire [7:0] acc_15_V_q1; +wire [7:0] acc_55_V_q1; +wire [7:0] acc_13_V_q1; +wire [7:0] acc_45_V_q1; +wire [7:0] acc_11_V_q1; +wire [7:0] acc_57_V_q1; +wire [7:0] acc_9_V_q1; +wire [7:0] acc_33_V_q1; +wire [7:0] acc_7_V_q1; +wire [7:0] acc_59_V_q1; +wire [7:0] acc_5_V_q1; +wire [7:0] acc_39_V_q1; +wire [7:0] acc_3_V_q1; +wire [7:0] acc_61_V_q1; +wire [7:0] acc_1_V_q1; +wire [7:0] acc_31_V_q1; +wire [31:0] add_ln276_130_fu_119661_p2; +reg [31:0] add_ln276_130_reg_151154; +reg [27:0] tmp_333_reg_151165; +wire [7:0] tmp_113_fu_119722_p30; +reg [7:0] tmp_113_reg_151310; +wire [7:0] add_ln703_20_fu_119784_p2; +reg [7:0] add_ln703_20_reg_151315; +wire [31:0] add_ln276_112_fu_119865_p2; +reg [31:0] add_ln276_112_reg_151323; +wire [0:0] icmp_ln268_12_fu_119859_p2; +wire [31:0] add_ln266_3_fu_119876_p2; +reg [27:0] tmp_361_reg_151339; +wire [7:0] tmp_130_fu_119932_p30; +reg [7:0] tmp_130_reg_151484; +wire [31:0] add_ln268_12_fu_120030_p2; +wire [31:0] add_ln276_75_fu_120047_p2; +reg [31:0] add_ln276_75_reg_151494; +wire [31:0] add_ln276_142_fu_120053_p2; +reg [31:0] add_ln276_142_reg_151660; +reg [27:0] tmp_341_reg_151671; +wire [7:0] tmp_118_fu_120114_p30; +reg [7:0] tmp_118_reg_151816; +wire [7:0] add_ln703_23_fu_120176_p2; +reg [7:0] add_ln703_23_reg_151821; +wire [31:0] add_ln276_117_fu_120257_p2; +reg [31:0] add_ln276_117_reg_151829; +wire [0:0] icmp_ln268_15_fu_120251_p2; +wire [31:0] add_ln276_127_fu_120291_p2; +reg [31:0] add_ln276_127_reg_151838; +wire [0:0] icmp_ln266_11_fu_120274_p2; +wire [2:0] add_ln264_3_fu_120297_p2; +reg [27:0] tmp_366_reg_151854; +wire [7:0] tmp_135_fu_120353_p30; +reg [7:0] tmp_135_reg_151999; +wire [31:0] add_ln268_15_fu_120451_p2; +wire [31:0] add_ln276_164_fu_120457_p2; +reg [31:0] add_ln276_164_reg_152169; +reg [27:0] tmp_405_reg_152180; +wire [7:0] tmp_157_fu_120518_p30; +reg [7:0] tmp_157_reg_152325; +wire [7:0] add_ln703_51_fu_120580_p2; +reg [7:0] add_ln703_51_reg_152330; +wire [31:0] add_ln276_151_fu_120661_p2; +reg [31:0] add_ln276_151_reg_152338; +wire [0:0] icmp_ln268_27_fu_120655_p2; +wire [31:0] add_ln266_11_fu_120672_p2; +reg [27:0] tmp_435_reg_152354; +wire [7:0] tmp_166_fu_120728_p30; +reg [7:0] tmp_166_reg_152499; +wire [31:0] add_ln268_27_fu_120826_p2; +wire [5:0] add_ln1265_2_fu_120855_p2; +reg [5:0] add_ln1265_2_reg_152512; +wire [0:0] icmp_ln261_2_fu_120840_p2; +reg [5:0] acc_0_V_addr_40_reg_152516; +reg [5:0] acc_1_V_addr_40_reg_152522; +reg [5:0] acc_2_V_addr_40_reg_152528; +reg [5:0] acc_3_V_addr_40_reg_152534; +reg [5:0] acc_4_V_addr_40_reg_152540; +reg [5:0] acc_5_V_addr_40_reg_152546; +reg [5:0] acc_6_V_addr_40_reg_152552; +reg [5:0] acc_7_V_addr_40_reg_152558; +reg [5:0] acc_8_V_addr_40_reg_152564; +reg [5:0] acc_9_V_addr_40_reg_152570; +reg [5:0] acc_10_V_addr_40_reg_152576; +reg [5:0] acc_11_V_addr_40_reg_152582; +reg [5:0] acc_12_V_addr_40_reg_152588; +reg [5:0] acc_13_V_addr_40_reg_152594; +reg [5:0] acc_14_V_addr_40_reg_152600; +reg [5:0] acc_15_V_addr_40_reg_152606; +reg [5:0] acc_16_V_addr_40_reg_152612; +reg [5:0] acc_17_V_addr_40_reg_152618; +reg [5:0] acc_18_V_addr_40_reg_152624; +reg [5:0] acc_19_V_addr_40_reg_152630; +reg [5:0] acc_20_V_addr_40_reg_152636; +reg [5:0] acc_21_V_addr_40_reg_152642; +reg [5:0] acc_22_V_addr_40_reg_152648; +reg [5:0] acc_23_V_addr_40_reg_152654; +reg [5:0] acc_24_V_addr_40_reg_152660; +reg [5:0] acc_25_V_addr_40_reg_152666; +reg [5:0] acc_26_V_addr_40_reg_152672; +reg [5:0] acc_27_V_addr_40_reg_152678; +reg [5:0] acc_28_V_addr_40_reg_152684; +reg [5:0] acc_29_V_addr_40_reg_152690; +reg [5:0] acc_30_V_addr_40_reg_152696; +reg [5:0] acc_31_V_addr_40_reg_152702; +reg [5:0] acc_32_V_addr_40_reg_152708; +reg [5:0] acc_33_V_addr_40_reg_152714; +reg [5:0] acc_34_V_addr_40_reg_152720; +reg [5:0] acc_35_V_addr_40_reg_152726; +reg [5:0] acc_36_V_addr_40_reg_152732; +reg [5:0] acc_37_V_addr_40_reg_152738; +reg [5:0] acc_38_V_addr_40_reg_152744; +reg [5:0] acc_39_V_addr_40_reg_152750; +reg [5:0] acc_40_V_addr_40_reg_152756; +reg [5:0] acc_41_V_addr_40_reg_152762; +reg [5:0] acc_42_V_addr_40_reg_152768; +reg [5:0] acc_43_V_addr_40_reg_152774; +reg [5:0] acc_44_V_addr_40_reg_152780; +reg [5:0] acc_45_V_addr_40_reg_152786; +reg [5:0] acc_46_V_addr_40_reg_152792; +reg [5:0] acc_47_V_addr_40_reg_152798; +reg [5:0] acc_48_V_addr_39_reg_152804; +reg [5:0] acc_49_V_addr_39_reg_152810; +reg [5:0] acc_50_V_addr_39_reg_152816; +reg [5:0] acc_51_V_addr_39_reg_152822; +reg [5:0] acc_52_V_addr_39_reg_152828; +reg [5:0] acc_53_V_addr_39_reg_152834; +reg [5:0] acc_54_V_addr_39_reg_152840; +reg [5:0] acc_55_V_addr_39_reg_152846; +reg [5:0] acc_56_V_addr_39_reg_152852; +reg [5:0] acc_57_V_addr_39_reg_152858; +reg [5:0] acc_58_V_addr_39_reg_152864; +reg [5:0] acc_59_V_addr_39_reg_152870; +reg [5:0] acc_60_V_addr_39_reg_152876; +reg [5:0] acc_61_V_addr_39_reg_152882; +reg [5:0] acc_62_V_addr_39_reg_152888; +reg [5:0] acc_63_V_addr_39_reg_152894; +wire [17:0] grp_fu_131466_p3; +reg [17:0] add_ln276_9_reg_152900; +wire [3:0] add_ln259_fu_120942_p2; +wire [31:0] zext_ln276_2_fu_120958_p1; +reg [31:0] zext_ln276_2_reg_152914; +wire [0:0] icmp_ln264_2_fu_120952_p2; +wire [5:0] add_ln1265_6_fu_120984_p2; +reg [5:0] add_ln1265_6_reg_152920; +reg [5:0] acc_0_V_addr_46_reg_152924; +reg [5:0] acc_1_V_addr_46_reg_152930; +reg [5:0] acc_2_V_addr_46_reg_152936; +reg [5:0] acc_3_V_addr_46_reg_152942; +reg [5:0] acc_4_V_addr_46_reg_152948; +reg [5:0] acc_5_V_addr_46_reg_152954; +reg [5:0] acc_6_V_addr_46_reg_152960; +reg [5:0] acc_7_V_addr_46_reg_152966; +reg [5:0] acc_8_V_addr_46_reg_152972; +reg [5:0] acc_9_V_addr_46_reg_152978; +reg [5:0] acc_10_V_addr_46_reg_152984; +reg [5:0] acc_11_V_addr_46_reg_152990; +reg [5:0] acc_12_V_addr_46_reg_152996; +reg [5:0] acc_13_V_addr_46_reg_153002; +reg [5:0] acc_14_V_addr_46_reg_153008; +reg [5:0] acc_15_V_addr_46_reg_153014; +reg [5:0] acc_16_V_addr_46_reg_153020; +reg [5:0] acc_17_V_addr_46_reg_153026; +reg [5:0] acc_18_V_addr_46_reg_153032; +reg [5:0] acc_19_V_addr_46_reg_153038; +reg [5:0] acc_20_V_addr_46_reg_153044; +reg [5:0] acc_21_V_addr_46_reg_153050; +reg [5:0] acc_22_V_addr_46_reg_153056; +reg [5:0] acc_23_V_addr_46_reg_153062; +reg [5:0] acc_24_V_addr_46_reg_153068; +reg [5:0] acc_25_V_addr_46_reg_153074; +reg [5:0] acc_26_V_addr_46_reg_153080; +reg [5:0] acc_27_V_addr_46_reg_153086; +reg [5:0] acc_28_V_addr_46_reg_153092; +reg [5:0] acc_29_V_addr_46_reg_153098; +reg [5:0] acc_30_V_addr_46_reg_153104; +reg [5:0] acc_31_V_addr_46_reg_153110; +reg [5:0] acc_32_V_addr_46_reg_153116; +reg [5:0] acc_33_V_addr_46_reg_153122; +reg [5:0] acc_34_V_addr_46_reg_153128; +reg [5:0] acc_35_V_addr_46_reg_153134; +reg [5:0] acc_36_V_addr_46_reg_153140; +reg [5:0] acc_37_V_addr_46_reg_153146; +reg [5:0] acc_38_V_addr_46_reg_153152; +reg [5:0] acc_39_V_addr_46_reg_153158; +reg [5:0] acc_40_V_addr_46_reg_153164; +reg [5:0] acc_41_V_addr_46_reg_153170; +reg [5:0] acc_42_V_addr_46_reg_153176; +reg [5:0] acc_43_V_addr_46_reg_153182; +reg [5:0] acc_44_V_addr_46_reg_153188; +reg [5:0] acc_45_V_addr_46_reg_153194; +reg [5:0] acc_46_V_addr_46_reg_153200; +reg [5:0] acc_47_V_addr_46_reg_153206; +reg [5:0] acc_48_V_addr_45_reg_153212; +reg [5:0] acc_49_V_addr_45_reg_153218; +reg [5:0] acc_50_V_addr_45_reg_153224; +reg [5:0] acc_51_V_addr_45_reg_153230; +reg [5:0] acc_52_V_addr_45_reg_153236; +reg [5:0] acc_53_V_addr_45_reg_153242; +reg [5:0] acc_54_V_addr_45_reg_153248; +reg [5:0] acc_55_V_addr_45_reg_153254; +reg [5:0] acc_56_V_addr_45_reg_153260; +reg [5:0] acc_57_V_addr_45_reg_153266; +reg [5:0] acc_58_V_addr_45_reg_153272; +reg [5:0] acc_59_V_addr_45_reg_153278; +reg [5:0] acc_60_V_addr_45_reg_153284; +reg [5:0] acc_61_V_addr_45_reg_153290; +reg [5:0] acc_62_V_addr_45_reg_153296; +reg [5:0] acc_63_V_addr_45_reg_153302; +wire [17:0] grp_fu_131481_p3; +reg [17:0] add_ln276_20_reg_153308; +wire [31:0] add_ln276_17_fu_121082_p2; +reg [31:0] add_ln276_17_reg_153314; +wire [7:0] acc_42_V_q0; +wire [7:0] acc_30_V_q0; +wire [7:0] acc_48_V_q0; +wire [7:0] acc_28_V_q0; +wire [7:0] acc_38_V_q0; +wire [7:0] acc_26_V_q0; +wire [7:0] acc_50_V_q0; +wire [7:0] acc_24_V_q0; +wire [7:0] acc_44_V_q0; +wire [7:0] acc_22_V_q0; +wire [7:0] acc_52_V_q0; +wire [7:0] acc_20_V_q0; +wire [7:0] acc_36_V_q0; +wire [7:0] acc_18_V_q0; +wire [7:0] acc_54_V_q0; +wire [7:0] acc_16_V_q0; +wire [7:0] acc_40_V_q0; +wire [7:0] acc_14_V_q0; +wire [7:0] acc_56_V_q0; +wire [7:0] acc_12_V_q0; +wire [7:0] acc_34_V_q0; +wire [7:0] acc_10_V_q0; +wire [7:0] acc_58_V_q0; +wire [7:0] acc_8_V_q0; +wire [7:0] acc_46_V_q0; +wire [7:0] acc_6_V_q0; +wire [7:0] acc_60_V_q0; +wire [7:0] acc_4_V_q0; +wire [7:0] acc_32_V_q0; +wire [7:0] acc_2_V_q0; +wire [7:0] acc_62_V_q0; +wire [7:0] acc_0_V_q0; +wire [31:0] add_ln276_85_fu_121088_p2; +reg [31:0] add_ln276_85_reg_153485; +reg [27:0] tmp_266_reg_153496; +wire [7:0] tmp_8_fu_121149_p30; +reg [7:0] tmp_8_reg_153641; +wire [7:0] add_ln703_2_fu_121211_p2; +reg [7:0] add_ln703_2_reg_153646; +wire [31:0] add_ln276_49_fu_121292_p2; +reg [31:0] add_ln276_49_reg_153654; +wire [0:0] icmp_ln268_2_fu_121286_p2; +wire [31:0] add_ln276_59_fu_121326_p2; +reg [31:0] add_ln276_59_reg_153663; +wire [0:0] icmp_ln266_2_fu_121309_p2; +wire [31:0] zext_ln276_10_fu_121346_p1; +reg [31:0] zext_ln276_10_reg_153669; +reg [27:0] tmp_281_reg_153680; +wire [7:0] tmp_73_fu_121399_p30; +reg [7:0] tmp_73_reg_153825; +wire [31:0] add_ln268_2_fu_121498_p2; +wire [31:0] add_ln276_118_fu_121504_p2; +reg [31:0] add_ln276_118_reg_154000; +reg [27:0] tmp_332_reg_154011; +wire [7:0] tmp_112_fu_121565_p30; +reg [7:0] tmp_112_reg_154156; +wire [7:0] add_ln703_19_fu_121627_p2; +reg [7:0] add_ln703_19_reg_154161; +wire [31:0] add_ln276_111_fu_121708_p2; +reg [31:0] add_ln276_111_reg_154169; +wire [0:0] icmp_ln268_11_fu_121702_p2; +wire [31:0] add_ln266_2_fu_121719_p2; +reg [27:0] tmp_360_reg_154185; +wire [7:0] tmp_129_fu_121775_p30; +reg [7:0] tmp_129_reg_154330; +wire [31:0] add_ln268_11_fu_121874_p2; +wire [31:0] add_ln276_72_fu_121891_p2; +reg [31:0] add_ln276_72_reg_154340; +wire [31:0] add_ln276_133_fu_121897_p2; +reg [31:0] add_ln276_133_reg_154511; +reg [27:0] tmp_340_reg_154522; +wire [7:0] tmp_117_fu_121958_p30; +reg [7:0] tmp_117_reg_154667; +wire [7:0] add_ln703_22_fu_122020_p2; +reg [7:0] add_ln703_22_reg_154672; +wire [31:0] add_ln276_116_fu_122101_p2; +reg [31:0] add_ln276_116_reg_154680; +wire [0:0] icmp_ln268_14_fu_122095_p2; +wire [31:0] add_ln276_125_fu_122135_p2; +reg [31:0] add_ln276_125_reg_154689; +wire [0:0] icmp_ln266_10_fu_122118_p2; +wire [2:0] add_ln264_2_fu_122141_p2; +reg [27:0] tmp_365_reg_154705; +wire [7:0] tmp_134_fu_122197_p30; +reg [7:0] tmp_134_reg_154850; +wire [31:0] add_ln268_14_fu_122296_p2; +wire [31:0] add_ln276_163_fu_122302_p2; +reg [31:0] add_ln276_163_reg_155025; +reg [27:0] tmp_404_reg_155036; +wire [7:0] tmp_156_fu_122363_p30; +reg [7:0] tmp_156_reg_155181; +wire [7:0] add_ln703_50_fu_122425_p2; +reg [7:0] add_ln703_50_reg_155186; +wire [31:0] add_ln276_150_fu_122506_p2; +reg [31:0] add_ln276_150_reg_155194; +wire [0:0] icmp_ln268_26_fu_122500_p2; +wire [31:0] add_ln266_10_fu_122517_p2; +reg [27:0] tmp_434_reg_155210; +wire [7:0] tmp_165_fu_122573_p30; +reg [7:0] tmp_165_reg_155355; +wire [31:0] add_ln268_26_fu_122672_p2; +wire [31:0] zext_ln276_6_fu_122688_p1; +reg [31:0] zext_ln276_6_reg_155368; +wire [0:0] icmp_ln264_6_fu_122682_p2; +wire [3:0] add_ln261_2_fu_122691_p2; +wire [31:0] add_ln276_38_fu_122708_p2; +reg [31:0] add_ln276_38_reg_155379; +wire [31:0] add_ln276_99_fu_122714_p2; +reg [31:0] add_ln276_99_reg_155545; +reg [27:0] tmp_276_reg_155556; +wire [7:0] tmp_67_fu_122775_p30; +reg [7:0] tmp_67_reg_155701; +wire [7:0] add_ln703_7_fu_122837_p2; +reg [7:0] add_ln703_7_reg_155706; +wire [31:0] add_ln276_67_fu_122918_p2; +reg [31:0] add_ln276_67_reg_155714; +wire [0:0] icmp_ln268_6_fu_122912_p2; +wire [31:0] add_ln276_88_fu_122952_p2; +reg [31:0] add_ln276_88_reg_155723; +wire [0:0] icmp_ln266_6_fu_122935_p2; +wire [31:0] zext_ln276_14_fu_122972_p1; +reg [31:0] zext_ln276_14_reg_155729; +reg [27:0] tmp_306_reg_155740; +wire [7:0] tmp_93_fu_123025_p30; +reg [7:0] tmp_93_reg_155885; +wire [31:0] add_ln268_6_fu_123123_p2; +wire [31:0] add_ln276_148_fu_123129_p2; +reg [31:0] add_ln276_148_reg_156055; +reg [27:0] tmp_351_reg_156066; +wire [7:0] tmp_123_fu_123190_p30; +reg [7:0] tmp_123_reg_156211; +wire [7:0] add_ln703_27_fu_123252_p2; +reg [7:0] add_ln703_27_reg_156216; +wire [31:0] add_ln276_123_fu_123333_p2; +reg [31:0] add_ln276_123_reg_156224; +wire [0:0] icmp_ln268_18_fu_123327_p2; +wire [31:0] add_ln266_6_fu_123344_p2; +reg [27:0] tmp_373_reg_156240; +wire [7:0] tmp_140_fu_123400_p30; +reg [7:0] tmp_140_reg_156385; +wire [31:0] add_ln268_18_fu_123498_p2; +wire [31:0] add_ln276_97_fu_123515_p2; +reg [31:0] add_ln276_97_reg_156395; +wire [31:0] add_ln276_158_fu_123521_p2; +reg [31:0] add_ln276_158_reg_156561; +reg [27:0] tmp_359_reg_156572; +wire [7:0] tmp_128_fu_123582_p30; +reg [7:0] tmp_128_reg_156717; +wire [7:0] add_ln703_32_fu_123644_p2; +reg [7:0] add_ln703_32_reg_156722; +wire [31:0] add_ln276_131_fu_123725_p2; +reg [31:0] add_ln276_131_reg_156730; +wire [0:0] icmp_ln268_21_fu_123719_p2; +wire [31:0] add_ln276_140_fu_123759_p2; +reg [31:0] add_ln276_140_reg_156739; +wire [0:0] icmp_ln266_14_fu_123742_p2; +wire [2:0] add_ln264_6_fu_123765_p2; +reg [27:0] tmp_381_reg_156755; +wire [7:0] tmp_146_fu_123821_p30; +reg [7:0] tmp_146_reg_156900; +wire [31:0] add_ln268_21_fu_123919_p2; +wire [31:0] add_ln276_167_fu_123925_p2; +reg [31:0] add_ln276_167_reg_157070; +reg [27:0] tmp_426_reg_157081; +wire [7:0] tmp_163_fu_123986_p30; +reg [7:0] tmp_163_reg_157226; +wire [7:0] add_ln703_55_fu_124048_p2; +reg [7:0] add_ln703_55_reg_157231; +wire [31:0] add_ln276_154_fu_124129_p2; +reg [31:0] add_ln276_154_reg_157239; +wire [0:0] icmp_ln268_30_fu_124123_p2; +wire [31:0] add_ln266_14_fu_124140_p2; +reg [27:0] tmp_446_reg_157255; +wire [7:0] tmp_170_fu_124196_p30; +reg [7:0] tmp_170_reg_157400; +wire [31:0] add_ln268_30_fu_124294_p2; +wire [12:0] add_ln279_2_fu_124344_p2; +reg [12:0] add_ln279_2_reg_157413; +wire [0:0] icmp_ln259_1_fu_124304_p2; +wire [5:0] trunc_ln279_10_fu_124349_p1; +reg [5:0] trunc_ln279_10_reg_157419; +wire [18:0] grp_fu_131512_p3; +reg [18:0] add_ln276_1_reg_157425; +wire [3:0] add_ln257_fu_124353_p2; +wire [5:0] add_ln1265_1_fu_124382_p2; +reg [5:0] add_ln1265_1_reg_157439; +wire [0:0] icmp_ln261_1_fu_124367_p2; +reg [5:0] acc_0_V_addr_39_reg_157443; +reg [5:0] acc_1_V_addr_39_reg_157449; +reg [5:0] acc_2_V_addr_39_reg_157455; +reg [5:0] acc_3_V_addr_39_reg_157461; +reg [5:0] acc_4_V_addr_39_reg_157467; +reg [5:0] acc_5_V_addr_39_reg_157473; +reg [5:0] acc_6_V_addr_39_reg_157479; +reg [5:0] acc_7_V_addr_39_reg_157485; +reg [5:0] acc_8_V_addr_39_reg_157491; +reg [5:0] acc_9_V_addr_39_reg_157497; +reg [5:0] acc_10_V_addr_39_reg_157503; +reg [5:0] acc_11_V_addr_39_reg_157509; +reg [5:0] acc_12_V_addr_39_reg_157515; +reg [5:0] acc_13_V_addr_39_reg_157521; +reg [5:0] acc_14_V_addr_39_reg_157527; +reg [5:0] acc_15_V_addr_39_reg_157533; +reg [5:0] acc_16_V_addr_39_reg_157539; +reg [5:0] acc_17_V_addr_39_reg_157545; +reg [5:0] acc_18_V_addr_39_reg_157551; +reg [5:0] acc_19_V_addr_39_reg_157557; +reg [5:0] acc_20_V_addr_39_reg_157563; +reg [5:0] acc_21_V_addr_39_reg_157569; +reg [5:0] acc_22_V_addr_39_reg_157575; +reg [5:0] acc_23_V_addr_39_reg_157581; +reg [5:0] acc_24_V_addr_39_reg_157587; +reg [5:0] acc_25_V_addr_39_reg_157593; +reg [5:0] acc_26_V_addr_39_reg_157599; +reg [5:0] acc_27_V_addr_39_reg_157605; +reg [5:0] acc_28_V_addr_39_reg_157611; +reg [5:0] acc_29_V_addr_39_reg_157617; +reg [5:0] acc_30_V_addr_39_reg_157623; +reg [5:0] acc_31_V_addr_39_reg_157629; +reg [5:0] acc_32_V_addr_39_reg_157635; +reg [5:0] acc_33_V_addr_39_reg_157641; +reg [5:0] acc_34_V_addr_39_reg_157647; +reg [5:0] acc_35_V_addr_39_reg_157653; +reg [5:0] acc_36_V_addr_39_reg_157659; +reg [5:0] acc_37_V_addr_39_reg_157665; +reg [5:0] acc_38_V_addr_39_reg_157671; +reg [5:0] acc_39_V_addr_39_reg_157677; +reg [5:0] acc_40_V_addr_39_reg_157683; +reg [5:0] acc_41_V_addr_39_reg_157689; +reg [5:0] acc_42_V_addr_39_reg_157695; +reg [5:0] acc_43_V_addr_39_reg_157701; +reg [5:0] acc_44_V_addr_39_reg_157707; +reg [5:0] acc_45_V_addr_39_reg_157713; +reg [5:0] acc_46_V_addr_39_reg_157719; +reg [5:0] acc_47_V_addr_39_reg_157725; +reg [5:0] acc_48_V_addr_38_reg_157731; +reg [5:0] acc_49_V_addr_38_reg_157737; +reg [5:0] acc_50_V_addr_38_reg_157743; +reg [5:0] acc_51_V_addr_38_reg_157749; +reg [5:0] acc_52_V_addr_38_reg_157755; +reg [5:0] acc_53_V_addr_38_reg_157761; +reg [5:0] acc_54_V_addr_38_reg_157767; +reg [5:0] acc_55_V_addr_38_reg_157773; +reg [5:0] acc_56_V_addr_38_reg_157779; +reg [5:0] acc_57_V_addr_38_reg_157785; +reg [5:0] acc_58_V_addr_38_reg_157791; +reg [5:0] acc_59_V_addr_38_reg_157797; +reg [5:0] acc_60_V_addr_38_reg_157803; +reg [5:0] acc_61_V_addr_38_reg_157809; +reg [5:0] acc_62_V_addr_38_reg_157815; +reg [5:0] acc_63_V_addr_38_reg_157821; +wire [18:0] grp_fu_131519_p3; +reg [18:0] add_ln276_8_reg_157827; +wire [12:0] add_ln279_7_fu_124513_p2; +reg [12:0] add_ln279_7_reg_157833; +wire [5:0] trunc_ln279_12_fu_124518_p1; +reg [5:0] trunc_ln279_12_reg_157839; +wire [18:0] grp_fu_131526_p3; +reg [18:0] add_ln276_7_reg_157845; +wire [31:0] zext_ln276_1_fu_124532_p1; +reg [31:0] zext_ln276_1_reg_157854; +wire [0:0] icmp_ln264_1_fu_124526_p2; +wire [5:0] add_ln1265_5_fu_124558_p2; +reg [5:0] add_ln1265_5_reg_157860; +reg [5:0] acc_0_V_addr_45_reg_157864; +reg [5:0] acc_1_V_addr_45_reg_157870; +reg [5:0] acc_2_V_addr_45_reg_157876; +reg [5:0] acc_3_V_addr_45_reg_157882; +reg [5:0] acc_4_V_addr_45_reg_157888; +reg [5:0] acc_5_V_addr_45_reg_157894; +reg [5:0] acc_6_V_addr_45_reg_157900; +reg [5:0] acc_7_V_addr_45_reg_157906; +reg [5:0] acc_8_V_addr_45_reg_157912; +reg [5:0] acc_9_V_addr_45_reg_157918; +reg [5:0] acc_10_V_addr_45_reg_157924; +reg [5:0] acc_11_V_addr_45_reg_157930; +reg [5:0] acc_12_V_addr_45_reg_157936; +reg [5:0] acc_13_V_addr_45_reg_157942; +reg [5:0] acc_14_V_addr_45_reg_157948; +reg [5:0] acc_15_V_addr_45_reg_157954; +reg [5:0] acc_16_V_addr_45_reg_157960; +reg [5:0] acc_17_V_addr_45_reg_157966; +reg [5:0] acc_18_V_addr_45_reg_157972; +reg [5:0] acc_19_V_addr_45_reg_157978; +reg [5:0] acc_20_V_addr_45_reg_157984; +reg [5:0] acc_21_V_addr_45_reg_157990; +reg [5:0] acc_22_V_addr_45_reg_157996; +reg [5:0] acc_23_V_addr_45_reg_158002; +reg [5:0] acc_24_V_addr_45_reg_158008; +reg [5:0] acc_25_V_addr_45_reg_158014; +reg [5:0] acc_26_V_addr_45_reg_158020; +reg [5:0] acc_27_V_addr_45_reg_158026; +reg [5:0] acc_28_V_addr_45_reg_158032; +reg [5:0] acc_29_V_addr_45_reg_158038; +reg [5:0] acc_30_V_addr_45_reg_158044; +reg [5:0] acc_31_V_addr_45_reg_158050; +reg [5:0] acc_32_V_addr_45_reg_158056; +reg [5:0] acc_33_V_addr_45_reg_158062; +reg [5:0] acc_34_V_addr_45_reg_158068; +reg [5:0] acc_35_V_addr_45_reg_158074; +reg [5:0] acc_36_V_addr_45_reg_158080; +reg [5:0] acc_37_V_addr_45_reg_158086; +reg [5:0] acc_38_V_addr_45_reg_158092; +reg [5:0] acc_39_V_addr_45_reg_158098; +reg [5:0] acc_40_V_addr_45_reg_158104; +reg [5:0] acc_41_V_addr_45_reg_158110; +reg [5:0] acc_42_V_addr_45_reg_158116; +reg [5:0] acc_43_V_addr_45_reg_158122; +reg [5:0] acc_44_V_addr_45_reg_158128; +reg [5:0] acc_45_V_addr_45_reg_158134; +reg [5:0] acc_46_V_addr_45_reg_158140; +reg [5:0] acc_47_V_addr_45_reg_158146; +reg [5:0] acc_48_V_addr_44_reg_158152; +reg [5:0] acc_49_V_addr_44_reg_158158; +reg [5:0] acc_50_V_addr_44_reg_158164; +reg [5:0] acc_51_V_addr_44_reg_158170; +reg [5:0] acc_52_V_addr_44_reg_158176; +reg [5:0] acc_53_V_addr_44_reg_158182; +reg [5:0] acc_54_V_addr_44_reg_158188; +reg [5:0] acc_55_V_addr_44_reg_158194; +reg [5:0] acc_56_V_addr_44_reg_158200; +reg [5:0] acc_57_V_addr_44_reg_158206; +reg [5:0] acc_58_V_addr_44_reg_158212; +reg [5:0] acc_59_V_addr_44_reg_158218; +reg [5:0] acc_60_V_addr_44_reg_158224; +reg [5:0] acc_61_V_addr_44_reg_158230; +reg [5:0] acc_62_V_addr_44_reg_158236; +reg [5:0] acc_63_V_addr_44_reg_158242; +wire [18:0] grp_fu_131541_p3; +reg [18:0] add_ln276_19_reg_158248; +wire [31:0] add_ln276_12_fu_124656_p2; +reg [31:0] add_ln276_12_reg_158254; +wire [31:0] add_ln276_82_fu_124662_p2; +reg [31:0] add_ln276_82_reg_158425; +reg [27:0] tmp_265_reg_158436; +wire [7:0] tmp_7_fu_124723_p30; +reg [7:0] tmp_7_reg_158581; +wire [7:0] add_ln703_1_fu_124785_p2; +reg [7:0] add_ln703_1_reg_158586; +wire [31:0] add_ln276_48_fu_124866_p2; +reg [31:0] add_ln276_48_reg_158594; +wire [0:0] icmp_ln268_1_fu_124860_p2; +wire [31:0] add_ln276_56_fu_124900_p2; +reg [31:0] add_ln276_56_reg_158603; +wire [0:0] icmp_ln266_1_fu_124883_p2; +wire [31:0] zext_ln276_9_fu_124920_p1; +reg [31:0] zext_ln276_9_reg_158609; +reg [27:0] tmp_280_reg_158620; +wire [7:0] tmp_72_fu_124973_p30; +reg [7:0] tmp_72_reg_158765; +wire [31:0] add_ln268_1_fu_125072_p2; +wire [31:0] add_ln276_109_fu_125078_p2; +reg [31:0] add_ln276_109_reg_158940; +reg [27:0] tmp_331_reg_158951; +wire [7:0] tmp_110_fu_125139_p30; +reg [7:0] tmp_110_reg_159096; +wire [7:0] add_ln703_18_fu_125201_p2; +reg [7:0] add_ln703_18_reg_159101; +wire [31:0] add_ln276_110_fu_125282_p2; +reg [31:0] add_ln276_110_reg_159109; +wire [0:0] icmp_ln268_10_fu_125276_p2; +wire [31:0] add_ln266_1_fu_125293_p2; +reg [27:0] tmp_358_reg_159125; +wire [7:0] tmp_127_fu_125349_p30; +reg [7:0] tmp_127_reg_159270; +wire [31:0] add_ln268_10_fu_125448_p2; +wire [31:0] add_ln276_69_fu_125465_p2; +reg [31:0] add_ln276_69_reg_159280; +wire [31:0] add_ln276_132_fu_125471_p2; +reg [31:0] add_ln276_132_reg_159451; +reg [27:0] tmp_339_reg_159462; +wire [7:0] tmp_116_fu_125532_p30; +reg [7:0] tmp_116_reg_159607; +wire [7:0] add_ln703_21_fu_125594_p2; +reg [7:0] add_ln703_21_reg_159612; +wire [31:0] add_ln276_115_fu_125675_p2; +reg [31:0] add_ln276_115_reg_159620; +wire [0:0] icmp_ln268_13_fu_125669_p2; +wire [31:0] add_ln276_122_fu_125709_p2; +reg [31:0] add_ln276_122_reg_159629; +wire [0:0] icmp_ln266_9_fu_125692_p2; +wire [2:0] add_ln264_1_fu_125715_p2; +reg [27:0] tmp_364_reg_159645; +wire [7:0] tmp_133_fu_125771_p30; +reg [7:0] tmp_133_reg_159790; +wire [31:0] add_ln268_13_fu_125870_p2; +wire [31:0] add_ln276_162_fu_125876_p2; +reg [31:0] add_ln276_162_reg_159965; +reg [27:0] tmp_403_reg_159976; +wire [7:0] tmp_155_fu_125937_p30; +reg [7:0] tmp_155_reg_160121; +wire [7:0] add_ln703_49_fu_125999_p2; +reg [7:0] add_ln703_49_reg_160126; +wire [31:0] add_ln276_149_fu_126080_p2; +reg [31:0] add_ln276_149_reg_160134; +wire [0:0] icmp_ln268_25_fu_126074_p2; +wire [31:0] add_ln266_9_fu_126091_p2; +reg [27:0] tmp_433_reg_160150; +wire [7:0] tmp_164_fu_126147_p30; +reg [7:0] tmp_164_reg_160295; +wire [31:0] add_ln268_25_fu_126246_p2; +wire [31:0] zext_ln276_5_fu_126262_p1; +reg [31:0] zext_ln276_5_reg_160308; +wire [0:0] icmp_ln264_5_fu_126256_p2; +wire [3:0] add_ln261_1_fu_126265_p2; +wire [31:0] add_ln276_35_fu_126282_p2; +reg [31:0] add_ln276_35_reg_160319; +wire [31:0] add_ln276_95_fu_126288_p2; +reg [31:0] add_ln276_95_reg_160485; +reg [27:0] tmp_275_reg_160496; +wire [7:0] tmp_66_fu_126349_p30; +reg [7:0] tmp_66_reg_160641; +wire [7:0] add_ln703_6_fu_126411_p2; +reg [7:0] add_ln703_6_reg_160646; +wire [31:0] add_ln276_63_fu_126492_p2; +reg [31:0] add_ln276_63_reg_160654; +wire [0:0] icmp_ln268_5_fu_126486_p2; +wire [31:0] add_ln276_83_fu_126526_p2; +reg [31:0] add_ln276_83_reg_160663; +wire [0:0] icmp_ln266_5_fu_126509_p2; +wire [31:0] zext_ln276_13_fu_126546_p1; +reg [31:0] zext_ln276_13_reg_160669; +reg [27:0] tmp_305_reg_160680; +wire [7:0] tmp_91_fu_126599_p30; +reg [7:0] tmp_91_reg_160825; +wire [31:0] add_ln268_5_fu_126697_p2; +wire [31:0] add_ln276_144_fu_126703_p2; +reg [31:0] add_ln276_144_reg_160995; +reg [27:0] tmp_350_reg_161006; +wire [7:0] tmp_122_fu_126764_p30; +reg [7:0] tmp_122_reg_161151; +wire [7:0] add_ln703_26_fu_126826_p2; +reg [7:0] add_ln703_26_reg_161156; +wire [31:0] add_ln276_120_fu_126907_p2; +reg [31:0] add_ln276_120_reg_161164; +wire [0:0] icmp_ln268_17_fu_126901_p2; +wire [31:0] add_ln266_5_fu_126918_p2; +reg [27:0] tmp_372_reg_161180; +wire [7:0] tmp_138_fu_126974_p30; +reg [7:0] tmp_138_reg_161325; +wire [31:0] add_ln268_17_fu_127072_p2; +wire [31:0] add_ln276_94_fu_127089_p2; +reg [31:0] add_ln276_94_reg_161335; +wire [31:0] add_ln276_157_fu_127095_p2; +reg [31:0] add_ln276_157_reg_161501; +reg [27:0] tmp_357_reg_161512; +wire [7:0] tmp_126_fu_127156_p30; +reg [7:0] tmp_126_reg_161657; +wire [7:0] add_ln703_30_fu_127218_p2; +reg [7:0] add_ln703_30_reg_161662; +wire [31:0] add_ln276_129_fu_127299_p2; +reg [31:0] add_ln276_129_reg_161670; +wire [0:0] icmp_ln268_20_fu_127293_p2; +wire [31:0] add_ln276_138_fu_127333_p2; +reg [31:0] add_ln276_138_reg_161679; +wire [0:0] icmp_ln266_13_fu_127316_p2; +wire [2:0] add_ln264_5_fu_127339_p2; +reg [27:0] tmp_380_reg_161695; +wire [7:0] tmp_145_fu_127395_p30; +reg [7:0] tmp_145_reg_161840; +wire [31:0] add_ln268_20_fu_127493_p2; +wire [31:0] add_ln276_166_fu_127499_p2; +reg [31:0] add_ln276_166_reg_162010; +reg [27:0] tmp_425_reg_162021; +wire [7:0] tmp_162_fu_127560_p30; +reg [7:0] tmp_162_reg_162166; +wire [7:0] add_ln703_54_fu_127622_p2; +reg [7:0] add_ln703_54_reg_162171; +wire [31:0] add_ln276_153_fu_127703_p2; +reg [31:0] add_ln276_153_reg_162179; +wire [0:0] icmp_ln268_29_fu_127697_p2; +wire [31:0] add_ln266_13_fu_127714_p2; +reg [27:0] tmp_445_reg_162195; +wire [7:0] tmp_169_fu_127770_p30; +reg [7:0] tmp_169_reg_162340; +wire [31:0] add_ln268_29_fu_127868_p2; +wire [5:0] add_ln1265_4_fu_127897_p2; +reg [5:0] add_ln1265_4_reg_162353; +wire [0:0] icmp_ln261_3_fu_127882_p2; +reg [5:0] acc_0_V_addr_44_reg_162357; +reg [5:0] acc_1_V_addr_44_reg_162363; +reg [5:0] acc_2_V_addr_44_reg_162369; +reg [5:0] acc_3_V_addr_44_reg_162375; +reg [5:0] acc_4_V_addr_44_reg_162381; +reg [5:0] acc_5_V_addr_44_reg_162387; +reg [5:0] acc_6_V_addr_44_reg_162393; +reg [5:0] acc_7_V_addr_44_reg_162399; +reg [5:0] acc_8_V_addr_44_reg_162405; +reg [5:0] acc_9_V_addr_44_reg_162411; +reg [5:0] acc_10_V_addr_44_reg_162417; +reg [5:0] acc_11_V_addr_44_reg_162423; +reg [5:0] acc_12_V_addr_44_reg_162429; +reg [5:0] acc_13_V_addr_44_reg_162435; +reg [5:0] acc_14_V_addr_44_reg_162441; +reg [5:0] acc_15_V_addr_44_reg_162447; +reg [5:0] acc_16_V_addr_44_reg_162453; +reg [5:0] acc_17_V_addr_44_reg_162459; +reg [5:0] acc_18_V_addr_44_reg_162465; +reg [5:0] acc_19_V_addr_44_reg_162471; +reg [5:0] acc_20_V_addr_44_reg_162477; +reg [5:0] acc_21_V_addr_44_reg_162483; +reg [5:0] acc_22_V_addr_44_reg_162489; +reg [5:0] acc_23_V_addr_44_reg_162495; +reg [5:0] acc_24_V_addr_44_reg_162501; +reg [5:0] acc_25_V_addr_44_reg_162507; +reg [5:0] acc_26_V_addr_44_reg_162513; +reg [5:0] acc_27_V_addr_44_reg_162519; +reg [5:0] acc_28_V_addr_44_reg_162525; +reg [5:0] acc_29_V_addr_44_reg_162531; +reg [5:0] acc_30_V_addr_44_reg_162537; +reg [5:0] acc_31_V_addr_44_reg_162543; +reg [5:0] acc_32_V_addr_44_reg_162549; +reg [5:0] acc_33_V_addr_44_reg_162555; +reg [5:0] acc_34_V_addr_44_reg_162561; +reg [5:0] acc_35_V_addr_44_reg_162567; +reg [5:0] acc_36_V_addr_44_reg_162573; +reg [5:0] acc_37_V_addr_44_reg_162579; +reg [5:0] acc_38_V_addr_44_reg_162585; +reg [5:0] acc_39_V_addr_44_reg_162591; +reg [5:0] acc_40_V_addr_44_reg_162597; +reg [5:0] acc_41_V_addr_44_reg_162603; +reg [5:0] acc_42_V_addr_44_reg_162609; +reg [5:0] acc_43_V_addr_44_reg_162615; +reg [5:0] acc_44_V_addr_44_reg_162621; +reg [5:0] acc_45_V_addr_44_reg_162627; +reg [5:0] acc_46_V_addr_44_reg_162633; +reg [5:0] acc_47_V_addr_44_reg_162639; +reg [5:0] acc_48_V_addr_43_reg_162645; +reg [5:0] acc_49_V_addr_43_reg_162651; +reg [5:0] acc_50_V_addr_43_reg_162657; +reg [5:0] acc_51_V_addr_43_reg_162663; +reg [5:0] acc_52_V_addr_43_reg_162669; +reg [5:0] acc_53_V_addr_43_reg_162675; +reg [5:0] acc_54_V_addr_43_reg_162681; +reg [5:0] acc_55_V_addr_43_reg_162687; +reg [5:0] acc_56_V_addr_43_reg_162693; +reg [5:0] acc_57_V_addr_43_reg_162699; +reg [5:0] acc_58_V_addr_43_reg_162705; +reg [5:0] acc_59_V_addr_43_reg_162711; +reg [5:0] acc_60_V_addr_43_reg_162717; +reg [5:0] acc_61_V_addr_43_reg_162723; +reg [5:0] acc_62_V_addr_43_reg_162729; +reg [5:0] acc_63_V_addr_43_reg_162735; +wire [18:0] grp_fu_131572_p3; +reg [18:0] add_ln276_15_reg_162741; +wire [3:0] add_ln259_1_fu_127984_p2; +wire [31:0] zext_ln276_4_fu_128000_p1; +reg [31:0] zext_ln276_4_reg_162755; +wire [0:0] icmp_ln264_4_fu_127994_p2; +wire [5:0] add_ln1265_7_fu_128026_p2; +reg [5:0] add_ln1265_7_reg_162761; +reg [5:0] acc_0_V_addr_49_reg_162765; +reg [5:0] acc_1_V_addr_48_reg_162771; +reg [5:0] acc_2_V_addr_49_reg_162777; +reg [5:0] acc_3_V_addr_48_reg_162783; +reg [5:0] acc_4_V_addr_49_reg_162789; +reg [5:0] acc_5_V_addr_48_reg_162795; +reg [5:0] acc_6_V_addr_49_reg_162801; +reg [5:0] acc_7_V_addr_48_reg_162807; +reg [5:0] acc_8_V_addr_49_reg_162813; +reg [5:0] acc_9_V_addr_48_reg_162819; +reg [5:0] acc_10_V_addr_49_reg_162825; +reg [5:0] acc_11_V_addr_48_reg_162831; +reg [5:0] acc_12_V_addr_49_reg_162837; +reg [5:0] acc_13_V_addr_48_reg_162843; +reg [5:0] acc_14_V_addr_49_reg_162849; +reg [5:0] acc_15_V_addr_48_reg_162855; +reg [5:0] acc_16_V_addr_49_reg_162861; +reg [5:0] acc_17_V_addr_48_reg_162867; +reg [5:0] acc_18_V_addr_49_reg_162873; +reg [5:0] acc_19_V_addr_48_reg_162879; +reg [5:0] acc_20_V_addr_49_reg_162885; +reg [5:0] acc_21_V_addr_48_reg_162891; +reg [5:0] acc_22_V_addr_49_reg_162897; +reg [5:0] acc_23_V_addr_48_reg_162903; +reg [5:0] acc_24_V_addr_49_reg_162909; +reg [5:0] acc_25_V_addr_48_reg_162915; +reg [5:0] acc_26_V_addr_49_reg_162921; +reg [5:0] acc_27_V_addr_48_reg_162927; +reg [5:0] acc_28_V_addr_49_reg_162933; +reg [5:0] acc_29_V_addr_48_reg_162939; +reg [5:0] acc_30_V_addr_49_reg_162945; +reg [5:0] acc_31_V_addr_48_reg_162951; +reg [5:0] acc_32_V_addr_49_reg_162957; +reg [5:0] acc_33_V_addr_48_reg_162963; +reg [5:0] acc_34_V_addr_49_reg_162969; +reg [5:0] acc_35_V_addr_48_reg_162975; +reg [5:0] acc_36_V_addr_49_reg_162981; +reg [5:0] acc_37_V_addr_48_reg_162987; +reg [5:0] acc_38_V_addr_49_reg_162993; +reg [5:0] acc_39_V_addr_48_reg_162999; +reg [5:0] acc_40_V_addr_49_reg_163005; +reg [5:0] acc_41_V_addr_48_reg_163011; +reg [5:0] acc_42_V_addr_49_reg_163017; +reg [5:0] acc_43_V_addr_48_reg_163023; +reg [5:0] acc_44_V_addr_49_reg_163029; +reg [5:0] acc_45_V_addr_48_reg_163035; +reg [5:0] acc_46_V_addr_49_reg_163041; +reg [5:0] acc_47_V_addr_48_reg_163047; +reg [5:0] acc_48_V_addr_48_reg_163053; +reg [5:0] acc_49_V_addr_47_reg_163059; +reg [5:0] acc_50_V_addr_48_reg_163065; +reg [5:0] acc_51_V_addr_47_reg_163071; +reg [5:0] acc_52_V_addr_48_reg_163077; +reg [5:0] acc_53_V_addr_47_reg_163083; +reg [5:0] acc_54_V_addr_48_reg_163089; +reg [5:0] acc_55_V_addr_47_reg_163095; +reg [5:0] acc_56_V_addr_48_reg_163101; +reg [5:0] acc_57_V_addr_47_reg_163107; +reg [5:0] acc_58_V_addr_48_reg_163113; +reg [5:0] acc_59_V_addr_47_reg_163119; +reg [5:0] acc_60_V_addr_48_reg_163125; +reg [5:0] acc_61_V_addr_47_reg_163131; +reg [5:0] acc_62_V_addr_48_reg_163137; +reg [5:0] acc_63_V_addr_48_reg_163143; +wire [18:0] grp_fu_131587_p3; +reg [18:0] add_ln276_27_reg_163149; +wire [31:0] add_ln276_30_fu_128124_p2; +reg [31:0] add_ln276_30_reg_163155; +wire [31:0] add_ln276_92_fu_128130_p2; +reg [31:0] add_ln276_92_reg_163326; +reg [27:0] tmp_274_reg_163337; +wire [7:0] tmp_65_fu_128191_p30; +reg [7:0] tmp_65_reg_163482; +wire [7:0] add_ln703_5_fu_128253_p2; +reg [7:0] add_ln703_5_reg_163487; +wire [31:0] add_ln276_62_fu_128334_p2; +reg [31:0] add_ln276_62_reg_163495; +wire [0:0] icmp_ln268_4_fu_128328_p2; +wire [31:0] add_ln276_79_fu_128368_p2; +reg [31:0] add_ln276_79_reg_163504; +wire [0:0] icmp_ln266_4_fu_128351_p2; +wire [31:0] zext_ln276_12_fu_128388_p1; +reg [31:0] zext_ln276_12_reg_163510; +reg [27:0] tmp_304_reg_163521; +wire [7:0] tmp_90_fu_128441_p30; +reg [7:0] tmp_90_reg_163666; +wire [31:0] add_ln268_4_fu_128540_p2; +wire [31:0] add_ln276_143_fu_128546_p2; +reg [31:0] add_ln276_143_reg_163841; +reg [27:0] tmp_349_reg_163852; +wire [7:0] tmp_121_fu_128607_p30; +reg [7:0] tmp_121_reg_163997; +wire [7:0] add_ln703_25_fu_128669_p2; +reg [7:0] add_ln703_25_reg_164002; +wire [31:0] add_ln276_119_fu_128750_p2; +reg [31:0] add_ln276_119_reg_164010; +wire [0:0] icmp_ln268_16_fu_128744_p2; +wire [31:0] add_ln266_4_fu_128761_p2; +reg [27:0] tmp_371_reg_164026; +wire [7:0] tmp_137_fu_128817_p30; +reg [7:0] tmp_137_reg_164171; +wire [31:0] add_ln268_16_fu_128916_p2; +wire [31:0] add_ln276_91_fu_128933_p2; +reg [31:0] add_ln276_91_reg_164181; +wire [31:0] add_ln276_156_fu_128939_p2; +reg [31:0] add_ln276_156_reg_164352; +reg [27:0] tmp_356_reg_164363; +wire [7:0] tmp_125_fu_129000_p30; +reg [7:0] tmp_125_reg_164508; +wire [7:0] add_ln703_29_fu_129062_p2; +reg [7:0] add_ln703_29_reg_164513; +wire [31:0] add_ln276_128_fu_129143_p2; +reg [31:0] add_ln276_128_reg_164521; +wire [0:0] icmp_ln268_19_fu_129137_p2; +wire [31:0] add_ln276_136_fu_129177_p2; +reg [31:0] add_ln276_136_reg_164530; +wire [0:0] icmp_ln266_12_fu_129160_p2; +wire [2:0] add_ln264_4_fu_129183_p2; +reg [27:0] tmp_379_reg_164546; +wire [7:0] tmp_144_fu_129239_p30; +reg [7:0] tmp_144_reg_164691; +wire [31:0] add_ln268_19_fu_129338_p2; +wire [31:0] add_ln276_165_fu_129344_p2; +reg [31:0] add_ln276_165_reg_164866; +reg [27:0] tmp_424_reg_164877; +wire [7:0] tmp_161_fu_129405_p30; +reg [7:0] tmp_161_reg_165022; +wire [7:0] add_ln703_53_fu_129467_p2; +reg [7:0] add_ln703_53_reg_165027; +wire [31:0] add_ln276_152_fu_129548_p2; +reg [31:0] add_ln276_152_reg_165035; +wire [0:0] icmp_ln268_28_fu_129542_p2; +wire [31:0] add_ln266_12_fu_129559_p2; +reg [27:0] tmp_444_reg_165051; +wire [7:0] tmp_168_fu_129615_p30; +reg [7:0] tmp_168_reg_165196; +wire [31:0] add_ln268_28_fu_129714_p2; +wire [31:0] zext_ln276_7_fu_129730_p1; +reg [31:0] zext_ln276_7_reg_165209; +wire [0:0] icmp_ln264_7_fu_129724_p2; +wire [3:0] add_ln261_3_fu_129733_p2; +wire [31:0] add_ln276_42_fu_129750_p2; +reg [31:0] add_ln276_42_reg_165220; +wire [31:0] add_ln276_102_fu_129756_p2; +reg [31:0] add_ln276_102_reg_165386; +reg [27:0] tmp_293_reg_165397; +wire [7:0] tmp_80_fu_129817_p30; +reg [7:0] tmp_80_reg_165542; +wire [7:0] add_ln703_11_fu_129879_p2; +reg [7:0] add_ln703_11_reg_165547; +wire [31:0] add_ln276_86_fu_129960_p2; +reg [31:0] add_ln276_86_reg_165555; +wire [0:0] icmp_ln268_7_fu_129954_p2; +wire [31:0] add_ln276_101_fu_129994_p2; +reg [31:0] add_ln276_101_reg_165564; +wire [0:0] icmp_ln266_7_fu_129977_p2; +wire [31:0] zext_ln276_15_fu_130014_p1; +reg [31:0] zext_ln276_15_reg_165570; +reg [27:0] tmp_330_reg_165581; +wire [7:0] tmp_107_fu_130067_p30; +reg [7:0] tmp_107_reg_165726; +wire [31:0] add_ln268_7_fu_130165_p2; +wire [31:0] add_ln276_159_fu_130171_p2; +reg [31:0] add_ln276_159_reg_165896; +reg [27:0] tmp_363_reg_165907; +wire [7:0] tmp_132_fu_130232_p30; +reg [7:0] tmp_132_reg_166052; +wire [7:0] add_ln703_35_fu_130294_p2; +reg [7:0] add_ln703_35_reg_166057; +wire [31:0] add_ln276_134_fu_130375_p2; +reg [31:0] add_ln276_134_reg_166065; +wire [0:0] icmp_ln268_22_fu_130369_p2; +wire [31:0] add_ln266_7_fu_130386_p2; +reg [27:0] tmp_388_reg_166081; +wire [7:0] tmp_148_fu_130442_p30; +reg [7:0] tmp_148_reg_166226; +wire [31:0] add_ln268_22_fu_130540_p2; +wire [31:0] add_ln276_106_fu_130557_p2; +reg [31:0] add_ln276_106_reg_166236; +wire [31:0] add_ln276_160_fu_130563_p2; +reg [31:0] add_ln276_160_reg_166402; +reg [27:0] tmp_370_reg_166413; +wire [7:0] tmp_136_fu_130624_p30; +reg [7:0] tmp_136_reg_166558; +wire [7:0] add_ln703_39_fu_130686_p2; +reg [7:0] add_ln703_39_reg_166563; +wire [31:0] add_ln276_141_fu_130767_p2; +reg [31:0] add_ln276_141_reg_166571; +wire [0:0] icmp_ln268_23_fu_130761_p2; +wire [31:0] add_ln276_146_fu_130801_p2; +reg [31:0] add_ln276_146_reg_166580; +wire [0:0] icmp_ln266_15_fu_130784_p2; +wire [2:0] add_ln264_7_fu_130807_p2; +reg [27:0] tmp_402_reg_166596; +wire [7:0] tmp_154_fu_130863_p30; +reg [7:0] tmp_154_reg_166741; +wire [31:0] add_ln268_23_fu_130961_p2; +wire [31:0] add_ln276_168_fu_130967_p2; +reg [31:0] add_ln276_168_reg_166911; +reg [27:0] tmp_439_reg_166922; +wire [7:0] tmp_167_fu_131028_p30; +reg [7:0] tmp_167_reg_167067; +wire [7:0] add_ln703_59_fu_131090_p2; +reg [7:0] add_ln703_59_reg_167072; +wire [31:0] add_ln276_155_fu_131171_p2; +reg [31:0] add_ln276_155_reg_167080; +wire [0:0] icmp_ln268_31_fu_131165_p2; +wire [31:0] add_ln266_15_fu_131182_p2; +reg [27:0] tmp_448_reg_167096; +wire [7:0] tmp_171_fu_131238_p30; +reg [7:0] tmp_171_reg_167241; +wire [31:0] add_ln268_31_fu_131336_p2; +reg [13:0] mult_0_V_address0; +reg mult_0_V_ce0; +reg mult_0_V_we0; +reg [7:0] mult_0_V_d0; +wire [7:0] mult_0_V_q0; +reg [13:0] mult_1_V_address0; +reg mult_1_V_ce0; +reg mult_1_V_we0; +reg [7:0] mult_1_V_d0; +wire [7:0] mult_1_V_q0; +reg [13:0] mult_2_V_address0; +reg mult_2_V_ce0; +reg mult_2_V_we0; +reg [7:0] mult_2_V_d0; +wire [7:0] mult_2_V_q0; +reg [13:0] mult_3_V_address0; +reg mult_3_V_ce0; +reg mult_3_V_we0; +reg [7:0] mult_3_V_d0; +wire [7:0] mult_3_V_q0; +reg [13:0] mult_4_V_address0; +reg mult_4_V_ce0; +reg mult_4_V_we0; +reg [7:0] mult_4_V_d0; +wire [7:0] mult_4_V_q0; +reg [13:0] mult_5_V_address0; +reg mult_5_V_ce0; +reg mult_5_V_we0; +reg [7:0] mult_5_V_d0; +wire [7:0] mult_5_V_q0; +reg [13:0] mult_6_V_address0; +reg mult_6_V_ce0; +reg mult_6_V_we0; +reg [7:0] mult_6_V_d0; +wire [7:0] mult_6_V_q0; +reg [13:0] mult_7_V_address0; +reg mult_7_V_ce0; +reg mult_7_V_we0; +reg [7:0] mult_7_V_d0; +wire [7:0] mult_7_V_q0; +reg [13:0] mult_8_V_address0; +reg mult_8_V_ce0; +reg mult_8_V_we0; +reg [7:0] mult_8_V_d0; +wire [7:0] mult_8_V_q0; +reg [13:0] mult_9_V_address0; +reg mult_9_V_ce0; +reg mult_9_V_we0; +reg [7:0] mult_9_V_d0; +wire [7:0] mult_9_V_q0; +reg [13:0] mult_10_V_address0; +reg mult_10_V_ce0; +reg mult_10_V_we0; +reg [7:0] mult_10_V_d0; +wire [7:0] mult_10_V_q0; +reg [13:0] mult_11_V_address0; +reg mult_11_V_ce0; +reg mult_11_V_we0; +reg [7:0] mult_11_V_d0; +wire [7:0] mult_11_V_q0; +reg [13:0] mult_12_V_address0; +reg mult_12_V_ce0; +reg mult_12_V_we0; +reg [7:0] mult_12_V_d0; +wire [7:0] mult_12_V_q0; +reg [13:0] mult_13_V_address0; +reg mult_13_V_ce0; +reg mult_13_V_we0; +reg [7:0] mult_13_V_d0; +wire [7:0] mult_13_V_q0; +reg [13:0] mult_14_V_address0; +reg mult_14_V_ce0; +reg mult_14_V_we0; +reg [7:0] mult_14_V_d0; +wire [7:0] mult_14_V_q0; +reg [13:0] mult_15_V_address0; +reg mult_15_V_ce0; +reg mult_15_V_we0; +reg [7:0] mult_15_V_d0; +wire [7:0] mult_15_V_q0; +reg [13:0] mult_16_V_address0; +reg mult_16_V_ce0; +reg mult_16_V_we0; +reg [7:0] mult_16_V_d0; +wire [7:0] mult_16_V_q0; +reg [13:0] mult_17_V_address0; +reg mult_17_V_ce0; +reg mult_17_V_we0; +reg [7:0] mult_17_V_d0; +wire [7:0] mult_17_V_q0; +reg [13:0] mult_18_V_address0; +reg mult_18_V_ce0; +reg mult_18_V_we0; +reg [7:0] mult_18_V_d0; +wire [7:0] mult_18_V_q0; +reg [13:0] mult_19_V_address0; +reg mult_19_V_ce0; +reg mult_19_V_we0; +reg [7:0] mult_19_V_d0; +wire [7:0] mult_19_V_q0; +reg [13:0] mult_20_V_address0; +reg mult_20_V_ce0; +reg mult_20_V_we0; +reg [7:0] mult_20_V_d0; +wire [7:0] mult_20_V_q0; +reg [13:0] mult_21_V_address0; +reg mult_21_V_ce0; +reg mult_21_V_we0; +reg [7:0] mult_21_V_d0; +wire [7:0] mult_21_V_q0; +reg [13:0] mult_22_V_address0; +reg mult_22_V_ce0; +reg mult_22_V_we0; +reg [7:0] mult_22_V_d0; +wire [7:0] mult_22_V_q0; +reg [13:0] mult_23_V_address0; +reg mult_23_V_ce0; +reg mult_23_V_we0; +reg [7:0] mult_23_V_d0; +wire [7:0] mult_23_V_q0; +reg [13:0] mult_24_V_address0; +reg mult_24_V_ce0; +reg mult_24_V_we0; +reg [7:0] mult_24_V_d0; +wire [7:0] mult_24_V_q0; +reg [13:0] mult_25_V_address0; +reg mult_25_V_ce0; +reg mult_25_V_we0; +reg [7:0] mult_25_V_d0; +wire [7:0] mult_25_V_q0; +reg [13:0] mult_26_V_address0; +reg mult_26_V_ce0; +reg mult_26_V_we0; +reg [7:0] mult_26_V_d0; +wire [7:0] mult_26_V_q0; +reg [13:0] mult_27_V_address0; +reg mult_27_V_ce0; +reg mult_27_V_we0; +reg [7:0] mult_27_V_d0; +wire [7:0] mult_27_V_q0; +reg [5:0] acc_0_V_address0; +reg acc_0_V_ce0; +reg acc_0_V_we0; +reg [7:0] acc_0_V_d0; +reg [5:0] acc_0_V_address1; +reg acc_0_V_ce1; +reg acc_0_V_we1; +reg [7:0] acc_0_V_d1; +reg [5:0] acc_1_V_address0; +reg acc_1_V_ce0; +reg acc_1_V_we0; +reg [7:0] acc_1_V_d0; +reg [5:0] acc_1_V_address1; +reg acc_1_V_ce1; +reg acc_1_V_we1; +reg [7:0] acc_1_V_d1; +reg [5:0] acc_2_V_address0; +reg acc_2_V_ce0; +reg acc_2_V_we0; +reg [7:0] acc_2_V_d0; +reg [5:0] acc_2_V_address1; +reg acc_2_V_ce1; +reg acc_2_V_we1; +reg [7:0] acc_2_V_d1; +reg [5:0] acc_3_V_address0; +reg acc_3_V_ce0; +reg acc_3_V_we0; +reg [7:0] acc_3_V_d0; +reg [5:0] acc_3_V_address1; +reg acc_3_V_ce1; +reg acc_3_V_we1; +reg [7:0] acc_3_V_d1; +reg [5:0] acc_4_V_address0; +reg acc_4_V_ce0; +reg acc_4_V_we0; +reg [7:0] acc_4_V_d0; +reg [5:0] acc_4_V_address1; +reg acc_4_V_ce1; +reg acc_4_V_we1; +reg [7:0] acc_4_V_d1; +reg [5:0] acc_5_V_address0; +reg acc_5_V_ce0; +reg acc_5_V_we0; +reg [7:0] acc_5_V_d0; +reg [5:0] acc_5_V_address1; +reg acc_5_V_ce1; +reg acc_5_V_we1; +reg [7:0] acc_5_V_d1; +reg [5:0] acc_6_V_address0; +reg acc_6_V_ce0; +reg acc_6_V_we0; +reg [7:0] acc_6_V_d0; +reg [5:0] acc_6_V_address1; +reg acc_6_V_ce1; +reg acc_6_V_we1; +reg [7:0] acc_6_V_d1; +reg [5:0] acc_7_V_address0; +reg acc_7_V_ce0; +reg acc_7_V_we0; +reg [7:0] acc_7_V_d0; +reg [5:0] acc_7_V_address1; +reg acc_7_V_ce1; +reg acc_7_V_we1; +reg [7:0] acc_7_V_d1; +reg [5:0] acc_8_V_address0; +reg acc_8_V_ce0; +reg acc_8_V_we0; +reg [7:0] acc_8_V_d0; +reg [5:0] acc_8_V_address1; +reg acc_8_V_ce1; +reg acc_8_V_we1; +reg [7:0] acc_8_V_d1; +reg [5:0] acc_9_V_address0; +reg acc_9_V_ce0; +reg acc_9_V_we0; +reg [7:0] acc_9_V_d0; +reg [5:0] acc_9_V_address1; +reg acc_9_V_ce1; +reg acc_9_V_we1; +reg [7:0] acc_9_V_d1; +reg [5:0] acc_10_V_address0; +reg acc_10_V_ce0; +reg acc_10_V_we0; +reg [7:0] acc_10_V_d0; +reg [5:0] acc_10_V_address1; +reg acc_10_V_ce1; +reg acc_10_V_we1; +reg [7:0] acc_10_V_d1; +reg [5:0] acc_11_V_address0; +reg acc_11_V_ce0; +reg acc_11_V_we0; +reg [7:0] acc_11_V_d0; +reg [5:0] acc_11_V_address1; +reg acc_11_V_ce1; +reg acc_11_V_we1; +reg [7:0] acc_11_V_d1; +reg [5:0] acc_12_V_address0; +reg acc_12_V_ce0; +reg acc_12_V_we0; +reg [7:0] acc_12_V_d0; +reg [5:0] acc_12_V_address1; +reg acc_12_V_ce1; +reg acc_12_V_we1; +reg [7:0] acc_12_V_d1; +reg [5:0] acc_13_V_address0; +reg acc_13_V_ce0; +reg acc_13_V_we0; +reg [7:0] acc_13_V_d0; +reg [5:0] acc_13_V_address1; +reg acc_13_V_ce1; +reg acc_13_V_we1; +reg [7:0] acc_13_V_d1; +reg [5:0] acc_14_V_address0; +reg acc_14_V_ce0; +reg acc_14_V_we0; +reg [7:0] acc_14_V_d0; +reg [5:0] acc_14_V_address1; +reg acc_14_V_ce1; +reg acc_14_V_we1; +reg [7:0] acc_14_V_d1; +reg [5:0] acc_15_V_address0; +reg acc_15_V_ce0; +reg acc_15_V_we0; +reg [7:0] acc_15_V_d0; +reg [5:0] acc_15_V_address1; +reg acc_15_V_ce1; +reg acc_15_V_we1; +reg [7:0] acc_15_V_d1; +reg [5:0] acc_16_V_address0; +reg acc_16_V_ce0; +reg acc_16_V_we0; +reg [7:0] acc_16_V_d0; +reg [5:0] acc_16_V_address1; +reg acc_16_V_ce1; +reg acc_16_V_we1; +reg [7:0] acc_16_V_d1; +reg [5:0] acc_17_V_address0; +reg acc_17_V_ce0; +reg acc_17_V_we0; +reg [7:0] acc_17_V_d0; +reg [5:0] acc_17_V_address1; +reg acc_17_V_ce1; +reg acc_17_V_we1; +reg [7:0] acc_17_V_d1; +reg [5:0] acc_18_V_address0; +reg acc_18_V_ce0; +reg acc_18_V_we0; +reg [7:0] acc_18_V_d0; +reg [5:0] acc_18_V_address1; +reg acc_18_V_ce1; +reg acc_18_V_we1; +reg [7:0] acc_18_V_d1; +reg [5:0] acc_19_V_address0; +reg acc_19_V_ce0; +reg acc_19_V_we0; +reg [7:0] acc_19_V_d0; +reg [5:0] acc_19_V_address1; +reg acc_19_V_ce1; +reg acc_19_V_we1; +reg [7:0] acc_19_V_d1; +reg [5:0] acc_20_V_address0; +reg acc_20_V_ce0; +reg acc_20_V_we0; +reg [7:0] acc_20_V_d0; +reg [5:0] acc_20_V_address1; +reg acc_20_V_ce1; +reg acc_20_V_we1; +reg [7:0] acc_20_V_d1; +reg [5:0] acc_21_V_address0; +reg acc_21_V_ce0; +reg acc_21_V_we0; +reg [7:0] acc_21_V_d0; +reg [5:0] acc_21_V_address1; +reg acc_21_V_ce1; +reg acc_21_V_we1; +reg [7:0] acc_21_V_d1; +reg [5:0] acc_22_V_address0; +reg acc_22_V_ce0; +reg acc_22_V_we0; +reg [7:0] acc_22_V_d0; +reg [5:0] acc_22_V_address1; +reg acc_22_V_ce1; +reg acc_22_V_we1; +reg [7:0] acc_22_V_d1; +reg [5:0] acc_23_V_address0; +reg acc_23_V_ce0; +reg acc_23_V_we0; +reg [7:0] acc_23_V_d0; +reg [5:0] acc_23_V_address1; +reg acc_23_V_ce1; +reg acc_23_V_we1; +reg [7:0] acc_23_V_d1; +reg [5:0] acc_24_V_address0; +reg acc_24_V_ce0; +reg acc_24_V_we0; +reg [7:0] acc_24_V_d0; +reg [5:0] acc_24_V_address1; +reg acc_24_V_ce1; +reg acc_24_V_we1; +reg [7:0] acc_24_V_d1; +reg [5:0] acc_25_V_address0; +reg acc_25_V_ce0; +reg acc_25_V_we0; +reg [7:0] acc_25_V_d0; +reg [5:0] acc_25_V_address1; +reg acc_25_V_ce1; +reg acc_25_V_we1; +reg [7:0] acc_25_V_d1; +reg [5:0] acc_26_V_address0; +reg acc_26_V_ce0; +reg acc_26_V_we0; +reg [7:0] acc_26_V_d0; +reg [5:0] acc_26_V_address1; +reg acc_26_V_ce1; +reg acc_26_V_we1; +reg [7:0] acc_26_V_d1; +reg [5:0] acc_27_V_address0; +reg acc_27_V_ce0; +reg acc_27_V_we0; +reg [7:0] acc_27_V_d0; +reg [5:0] acc_27_V_address1; +reg acc_27_V_ce1; +reg acc_27_V_we1; +reg [7:0] acc_27_V_d1; +reg [5:0] acc_28_V_address0; +reg acc_28_V_ce0; +reg acc_28_V_we0; +reg [7:0] acc_28_V_d0; +reg [5:0] acc_28_V_address1; +reg acc_28_V_ce1; +reg acc_28_V_we1; +reg [7:0] acc_28_V_d1; +reg [5:0] acc_29_V_address0; +reg acc_29_V_ce0; +reg acc_29_V_we0; +reg [7:0] acc_29_V_d0; +reg [5:0] acc_29_V_address1; +reg acc_29_V_ce1; +reg acc_29_V_we1; +reg [7:0] acc_29_V_d1; +reg [5:0] acc_30_V_address0; +reg acc_30_V_ce0; +reg acc_30_V_we0; +reg [7:0] acc_30_V_d0; +reg [5:0] acc_30_V_address1; +reg acc_30_V_ce1; +reg acc_30_V_we1; +reg [7:0] acc_30_V_d1; +reg [5:0] acc_31_V_address0; +reg acc_31_V_ce0; +reg acc_31_V_we0; +reg [7:0] acc_31_V_d0; +reg [5:0] acc_31_V_address1; +reg acc_31_V_ce1; +reg acc_31_V_we1; +reg [7:0] acc_31_V_d1; +reg [5:0] acc_32_V_address0; +reg acc_32_V_ce0; +reg acc_32_V_we0; +reg [7:0] acc_32_V_d0; +reg [5:0] acc_32_V_address1; +reg acc_32_V_ce1; +reg acc_32_V_we1; +reg [7:0] acc_32_V_d1; +reg [5:0] acc_33_V_address0; +reg acc_33_V_ce0; +reg acc_33_V_we0; +reg [7:0] acc_33_V_d0; +reg [5:0] acc_33_V_address1; +reg acc_33_V_ce1; +reg acc_33_V_we1; +reg [7:0] acc_33_V_d1; +reg [5:0] acc_34_V_address0; +reg acc_34_V_ce0; +reg acc_34_V_we0; +reg [7:0] acc_34_V_d0; +reg [5:0] acc_34_V_address1; +reg acc_34_V_ce1; +reg acc_34_V_we1; +reg [7:0] acc_34_V_d1; +reg [5:0] acc_35_V_address0; +reg acc_35_V_ce0; +reg acc_35_V_we0; +reg [7:0] acc_35_V_d0; +reg [5:0] acc_35_V_address1; +reg acc_35_V_ce1; +reg acc_35_V_we1; +reg [7:0] acc_35_V_d1; +reg [5:0] acc_36_V_address0; +reg acc_36_V_ce0; +reg acc_36_V_we0; +reg [7:0] acc_36_V_d0; +reg [5:0] acc_36_V_address1; +reg acc_36_V_ce1; +reg acc_36_V_we1; +reg [7:0] acc_36_V_d1; +reg [5:0] acc_37_V_address0; +reg acc_37_V_ce0; +reg acc_37_V_we0; +reg [7:0] acc_37_V_d0; +reg [5:0] acc_37_V_address1; +reg acc_37_V_ce1; +reg acc_37_V_we1; +reg [7:0] acc_37_V_d1; +reg [5:0] acc_38_V_address0; +reg acc_38_V_ce0; +reg acc_38_V_we0; +reg [7:0] acc_38_V_d0; +reg [5:0] acc_38_V_address1; +reg acc_38_V_ce1; +reg acc_38_V_we1; +reg [7:0] acc_38_V_d1; +reg [5:0] acc_39_V_address0; +reg acc_39_V_ce0; +reg acc_39_V_we0; +reg [7:0] acc_39_V_d0; +reg [5:0] acc_39_V_address1; +reg acc_39_V_ce1; +reg acc_39_V_we1; +reg [7:0] acc_39_V_d1; +reg [5:0] acc_40_V_address0; +reg acc_40_V_ce0; +reg acc_40_V_we0; +reg [7:0] acc_40_V_d0; +reg [5:0] acc_40_V_address1; +reg acc_40_V_ce1; +reg acc_40_V_we1; +reg [7:0] acc_40_V_d1; +reg [5:0] acc_41_V_address0; +reg acc_41_V_ce0; +reg acc_41_V_we0; +reg [7:0] acc_41_V_d0; +reg [5:0] acc_41_V_address1; +reg acc_41_V_ce1; +reg acc_41_V_we1; +reg [7:0] acc_41_V_d1; +reg [5:0] acc_42_V_address0; +reg acc_42_V_ce0; +reg acc_42_V_we0; +reg [7:0] acc_42_V_d0; +reg [5:0] acc_42_V_address1; +reg acc_42_V_ce1; +reg acc_42_V_we1; +reg [7:0] acc_42_V_d1; +reg [5:0] acc_43_V_address0; +reg acc_43_V_ce0; +reg acc_43_V_we0; +reg [7:0] acc_43_V_d0; +reg [5:0] acc_43_V_address1; +reg acc_43_V_ce1; +reg acc_43_V_we1; +reg [7:0] acc_43_V_d1; +reg [5:0] acc_44_V_address0; +reg acc_44_V_ce0; +reg acc_44_V_we0; +reg [7:0] acc_44_V_d0; +reg [5:0] acc_44_V_address1; +reg acc_44_V_ce1; +reg acc_44_V_we1; +reg [7:0] acc_44_V_d1; +reg [5:0] acc_45_V_address0; +reg acc_45_V_ce0; +reg acc_45_V_we0; +reg [7:0] acc_45_V_d0; +reg [5:0] acc_45_V_address1; +reg acc_45_V_ce1; +reg acc_45_V_we1; +reg [7:0] acc_45_V_d1; +reg [5:0] acc_46_V_address0; +reg acc_46_V_ce0; +reg acc_46_V_we0; +reg [7:0] acc_46_V_d0; +reg [5:0] acc_46_V_address1; +reg acc_46_V_ce1; +reg acc_46_V_we1; +reg [7:0] acc_46_V_d1; +reg [5:0] acc_47_V_address0; +reg acc_47_V_ce0; +reg acc_47_V_we0; +reg [7:0] acc_47_V_d0; +reg [5:0] acc_47_V_address1; +reg acc_47_V_ce1; +reg acc_47_V_we1; +reg [7:0] acc_47_V_d1; +reg [5:0] acc_48_V_address0; +reg acc_48_V_ce0; +reg acc_48_V_we0; +reg [7:0] acc_48_V_d0; +reg [5:0] acc_48_V_address1; +reg acc_48_V_ce1; +reg acc_48_V_we1; +reg [7:0] acc_48_V_d1; +reg [5:0] acc_49_V_address0; +reg acc_49_V_ce0; +reg acc_49_V_we0; +reg [7:0] acc_49_V_d0; +reg [5:0] acc_49_V_address1; +reg acc_49_V_ce1; +reg acc_49_V_we1; +reg [7:0] acc_49_V_d1; +reg [5:0] acc_50_V_address0; +reg acc_50_V_ce0; +reg acc_50_V_we0; +reg [7:0] acc_50_V_d0; +reg [5:0] acc_50_V_address1; +reg acc_50_V_ce1; +reg acc_50_V_we1; +reg [7:0] acc_50_V_d1; +reg [5:0] acc_51_V_address0; +reg acc_51_V_ce0; +reg acc_51_V_we0; +reg [7:0] acc_51_V_d0; +reg [5:0] acc_51_V_address1; +reg acc_51_V_ce1; +reg acc_51_V_we1; +reg [7:0] acc_51_V_d1; +reg [5:0] acc_52_V_address0; +reg acc_52_V_ce0; +reg acc_52_V_we0; +reg [7:0] acc_52_V_d0; +reg [5:0] acc_52_V_address1; +reg acc_52_V_ce1; +reg acc_52_V_we1; +reg [7:0] acc_52_V_d1; +reg [5:0] acc_53_V_address0; +reg acc_53_V_ce0; +reg acc_53_V_we0; +reg [7:0] acc_53_V_d0; +reg [5:0] acc_53_V_address1; +reg acc_53_V_ce1; +reg acc_53_V_we1; +reg [7:0] acc_53_V_d1; +reg [5:0] acc_54_V_address0; +reg acc_54_V_ce0; +reg acc_54_V_we0; +reg [7:0] acc_54_V_d0; +reg [5:0] acc_54_V_address1; +reg acc_54_V_ce1; +reg acc_54_V_we1; +reg [7:0] acc_54_V_d1; +reg [5:0] acc_55_V_address0; +reg acc_55_V_ce0; +reg acc_55_V_we0; +reg [7:0] acc_55_V_d0; +reg [5:0] acc_55_V_address1; +reg acc_55_V_ce1; +reg acc_55_V_we1; +reg [7:0] acc_55_V_d1; +reg [5:0] acc_56_V_address0; +reg acc_56_V_ce0; +reg acc_56_V_we0; +reg [7:0] acc_56_V_d0; +reg [5:0] acc_56_V_address1; +reg acc_56_V_ce1; +reg acc_56_V_we1; +reg [7:0] acc_56_V_d1; +reg [5:0] acc_57_V_address0; +reg acc_57_V_ce0; +reg acc_57_V_we0; +reg [7:0] acc_57_V_d0; +reg [5:0] acc_57_V_address1; +reg acc_57_V_ce1; +reg acc_57_V_we1; +reg [7:0] acc_57_V_d1; +reg [5:0] acc_58_V_address0; +reg acc_58_V_ce0; +reg acc_58_V_we0; +reg [7:0] acc_58_V_d0; +reg [5:0] acc_58_V_address1; +reg acc_58_V_ce1; +reg acc_58_V_we1; +reg [7:0] acc_58_V_d1; +reg [5:0] acc_59_V_address0; +reg acc_59_V_ce0; +reg acc_59_V_we0; +reg [7:0] acc_59_V_d0; +reg [5:0] acc_59_V_address1; +reg acc_59_V_ce1; +reg acc_59_V_we1; +reg [7:0] acc_59_V_d1; +reg [5:0] acc_60_V_address0; +reg acc_60_V_ce0; +reg acc_60_V_we0; +reg [7:0] acc_60_V_d0; +reg [5:0] acc_60_V_address1; +reg acc_60_V_ce1; +reg acc_60_V_we1; +reg [7:0] acc_60_V_d1; +reg [5:0] acc_61_V_address0; +reg acc_61_V_ce0; +reg acc_61_V_we0; +reg [7:0] acc_61_V_d0; +reg [5:0] acc_61_V_address1; +reg acc_61_V_ce1; +reg acc_61_V_we1; +reg [7:0] acc_61_V_d1; +reg [5:0] acc_62_V_address0; +reg acc_62_V_ce0; +reg acc_62_V_we0; +reg [7:0] acc_62_V_d0; +reg [5:0] acc_62_V_address1; +reg acc_62_V_ce1; +reg acc_62_V_we1; +reg [7:0] acc_62_V_d1; +reg [5:0] acc_63_V_address0; +reg acc_63_V_ce0; +reg acc_63_V_we0; +reg [7:0] acc_63_V_d0; +reg [5:0] acc_63_V_address1; +reg acc_63_V_ce1; +reg acc_63_V_we1; +reg [7:0] acc_63_V_d1; +reg [3:0] oh_0_0_reg_91149; +reg [3:0] ow_0_0_0_reg_91161; +reg [3:0] ff_0_0_0_reg_91173; +reg [10:0] phi_mul_reg_91184; +reg [2:0] cc_0_0_0_0_reg_91195; +reg [31:0] fh_0_0_0_0_0_reg_91207; +wire [31:0] ap_phi_mux_fw_0_0_0_0_0_0_phi_fu_91223_p4; +reg [31:0] fw_0_0_0_0_0_0_reg_91219; +reg [7:0] phi_ln1116_reg_91231; +reg [7:0] phi_ln1116_4_reg_91367; +wire [31:0] ap_phi_mux_fw_0_0_0_0_1_0_phi_fu_91507_p4; +reg [31:0] fw_0_0_0_0_1_0_reg_91503; +reg [7:0] phi_ln1116_7_reg_91515; +reg [7:0] phi_ln1116_16_reg_91651; +reg [31:0] fh_0_0_0_1_0_reg_91787; +wire [31:0] ap_phi_mux_fw_0_0_0_1_0_0_phi_fu_91803_p4; +reg [31:0] fw_0_0_0_1_0_0_reg_91799; +reg [7:0] phi_ln1116_8_reg_91811; +reg [7:0] phi_ln1116_17_reg_91945; +wire [31:0] ap_phi_mux_fw_0_0_0_1_1_0_phi_fu_92083_p4; +reg [31:0] fw_0_0_0_1_1_0_reg_92079; +reg [7:0] phi_ln1116_22_reg_92091; +reg [7:0] phi_ln1116_28_reg_92225; +reg [3:0] ff_0_0_1_reg_92359; +reg [10:0] phi_mul135689_reg_92370; +reg [2:0] cc_0_0_1_0_reg_92381; +reg [31:0] fh_0_0_1_0_0_reg_92393; +wire [31:0] ap_phi_mux_fw_0_0_1_0_0_0_phi_fu_92409_p4; +reg [31:0] fw_0_0_1_0_0_0_reg_92405; +reg [7:0] phi_ln1116_2_reg_92417; +reg [7:0] phi_ln1116_6_reg_92553; +wire [31:0] ap_phi_mux_fw_0_0_1_0_1_0_phi_fu_92693_p4; +reg [31:0] fw_0_0_1_0_1_0_reg_92689; +reg [7:0] phi_ln1116_11_reg_92701; +reg [7:0] phi_ln1116_19_reg_92837; +reg [31:0] fh_0_0_1_1_0_reg_92973; +wire [31:0] ap_phi_mux_fw_0_0_1_1_0_0_phi_fu_92989_p4; +reg [31:0] fw_0_0_1_1_0_0_reg_92985; +reg [7:0] phi_ln1116_13_reg_92997; +reg [7:0] phi_ln1116_21_reg_93131; +wire [31:0] ap_phi_mux_fw_0_0_1_1_1_0_phi_fu_93269_p4; +reg [31:0] fw_0_0_1_1_1_0_reg_93265; +reg [7:0] phi_ln1116_26_reg_93277; +reg [7:0] phi_ln1116_30_reg_93411; +reg [3:0] ow_0_1_0_reg_93545; +reg [3:0] ff_0_1_0_reg_93557; +reg [10:0] phi_mul135708_reg_93568; +reg [2:0] cc_0_1_0_0_reg_93579; +reg [31:0] fh_0_1_0_0_0_reg_93591; +wire [31:0] ap_phi_mux_fw_0_1_0_0_0_0_phi_fu_93607_p4; +reg [31:0] fw_0_1_0_0_0_0_reg_93603; +reg [7:0] phi_ln1116_1_reg_93615; +reg [7:0] phi_ln1116_5_reg_93751; +wire [31:0] ap_phi_mux_fw_0_1_0_0_1_0_phi_fu_93891_p4; +reg [31:0] fw_0_1_0_0_1_0_reg_93887; +reg [7:0] phi_ln1116_10_reg_93899; +reg [7:0] phi_ln1116_18_reg_94035; +reg [31:0] fh_0_1_0_1_0_reg_94171; +wire [31:0] ap_phi_mux_fw_0_1_0_1_0_0_phi_fu_94187_p4; +reg [31:0] fw_0_1_0_1_0_0_reg_94183; +reg [7:0] phi_ln1116_12_reg_94195; +reg [7:0] phi_ln1116_20_reg_94329; +wire [31:0] ap_phi_mux_fw_0_1_0_1_1_0_phi_fu_94467_p4; +reg [31:0] fw_0_1_0_1_1_0_reg_94463; +reg [7:0] phi_ln1116_25_reg_94475; +reg [7:0] phi_ln1116_29_reg_94609; +reg [3:0] ff_0_1_1_reg_94743; +reg [10:0] phi_mul135727_reg_94754; +reg [2:0] cc_0_1_1_0_reg_94765; +reg [31:0] fh_0_1_1_0_0_reg_94777; +wire [31:0] ap_phi_mux_fw_0_1_1_0_0_0_phi_fu_94793_p4; +reg [31:0] fw_0_1_1_0_0_0_reg_94789; +reg [7:0] phi_ln1116_3_reg_94801; +reg [7:0] phi_ln1116_9_reg_94937; +wire [31:0] ap_phi_mux_fw_0_1_1_0_1_0_phi_fu_95077_p4; +reg [31:0] fw_0_1_1_0_1_0_reg_95073; +reg [7:0] phi_ln1116_14_reg_95085; +reg [7:0] phi_ln1116_23_reg_95221; +reg [31:0] fh_0_1_1_1_0_reg_95357; +wire [31:0] ap_phi_mux_fw_0_1_1_1_0_0_phi_fu_95373_p4; +reg [31:0] fw_0_1_1_1_0_0_reg_95369; +reg [7:0] phi_ln1116_15_reg_95381; +reg [7:0] phi_ln1116_24_reg_95515; +wire [31:0] ap_phi_mux_fw_0_1_1_1_1_0_phi_fu_95653_p4; +reg [31:0] fw_0_1_1_1_1_0_reg_95649; +reg [7:0] phi_ln1116_27_reg_95661; +reg [7:0] phi_ln1116_31_reg_95795; +reg [3:0] oh2_0_0_reg_95929; +reg [3:0] ow3_0_0_0_reg_95941; +reg [3:0] ff4_0_0_0_0_reg_95953; +reg [3:0] ff4_0_0_1_0_reg_95965; +reg [3:0] ow3_0_1_0_reg_95977; +reg [3:0] ff4_0_1_0_0_reg_95989; +reg [3:0] ff4_0_1_1_0_reg_96001; +reg [3:0] oh5_0_0_reg_96013; +reg [3:0] ow6_0_0_0_reg_96025; +reg [3:0] ff7_0_0_0_0_reg_96037; +reg [2:0] cc8_0_0_0_0_0_reg_96049; +reg [31:0] fh9_0_0_0_0_0_0_reg_96061; +reg [31:0] fw10_0_0_0_0_0_0_0_reg_96073; +reg [7:0] phi_ln1265_reg_96085; +reg [31:0] fw10_0_0_0_0_0_1_0_reg_96157; +reg [7:0] phi_ln1265_8_reg_96169; +reg [31:0] fh9_0_0_0_0_1_0_reg_96241; +reg [31:0] fw10_0_0_0_0_1_0_0_reg_96253; +reg [7:0] phi_ln1265_9_reg_96265; +reg [31:0] fw10_0_0_0_0_1_1_0_reg_96337; +reg [7:0] phi_ln1265_24_reg_96349; +reg [2:0] cc8_0_0_0_1_0_reg_96421; +reg [31:0] fh9_0_0_0_1_0_0_reg_96433; +reg [31:0] fw10_0_0_0_1_0_0_0_reg_96445; +reg [7:0] phi_ln1265_3_reg_96457; +reg [31:0] fw10_0_0_0_1_0_1_0_reg_96527; +reg [7:0] phi_ln1265_12_reg_96539; +reg [31:0] fh9_0_0_0_1_1_0_reg_96609; +reg [31:0] fw10_0_0_0_1_1_0_0_reg_96621; +reg [7:0] phi_ln1265_15_reg_96633; +reg [31:0] fw10_0_0_0_1_1_1_0_reg_96703; +reg [7:0] phi_ln1265_27_reg_96715; +reg [3:0] ff7_0_0_1_0_reg_96785; +reg [2:0] cc8_0_0_1_0_0_reg_96797; +reg [31:0] fh9_0_0_1_0_0_0_reg_96809; +reg [31:0] fw10_0_0_1_0_0_0_0_reg_96821; +reg [7:0] phi_ln1265_2_reg_96833; +reg [31:0] fw10_0_0_1_0_0_1_0_reg_96905; +reg [7:0] phi_ln1265_11_reg_96917; +reg [31:0] fh9_0_0_1_0_1_0_reg_96989; +reg [31:0] fw10_0_0_1_0_1_0_0_reg_97001; +reg [7:0] phi_ln1265_14_reg_97013; +reg [31:0] fw10_0_0_1_0_1_1_0_reg_97085; +reg [7:0] phi_ln1265_26_reg_97097; +reg [2:0] cc8_0_0_1_1_0_reg_97169; +reg [31:0] fh9_0_0_1_1_0_0_reg_97181; +reg [31:0] fw10_0_0_1_1_0_0_0_reg_97193; +reg [7:0] phi_ln1265_6_reg_97205; +reg [31:0] fw10_0_0_1_1_0_1_0_reg_97275; +reg [7:0] phi_ln1265_18_reg_97287; +reg [31:0] fh9_0_0_1_1_1_0_reg_97357; +reg [31:0] fw10_0_0_1_1_1_0_0_reg_97369; +reg [7:0] phi_ln1265_21_reg_97381; +reg [31:0] fw10_0_0_1_1_1_1_0_reg_97451; +reg [7:0] phi_ln1265_30_reg_97463; +reg [3:0] ow6_0_1_0_reg_97533; +reg [3:0] ff7_0_1_0_0_reg_97545; +reg [2:0] cc8_0_1_0_0_0_reg_97557; +reg [31:0] fh9_0_1_0_0_0_0_reg_97569; +reg [31:0] fw10_0_1_0_0_0_0_0_reg_97581; +reg [7:0] phi_ln1265_1_reg_97593; +reg [31:0] fw10_0_1_0_0_0_1_0_reg_97665; +reg [7:0] phi_ln1265_10_reg_97677; +reg [31:0] fh9_0_1_0_0_1_0_reg_97749; +reg [31:0] fw10_0_1_0_0_1_0_0_reg_97761; +reg [7:0] phi_ln1265_13_reg_97773; +reg [31:0] fw10_0_1_0_0_1_1_0_reg_97845; +reg [7:0] phi_ln1265_25_reg_97857; +reg [2:0] cc8_0_1_0_1_0_reg_97929; +reg [31:0] fh9_0_1_0_1_0_0_reg_97941; +reg [31:0] fw10_0_1_0_1_0_0_0_reg_97953; +reg [7:0] phi_ln1265_5_reg_97965; +reg [31:0] fw10_0_1_0_1_0_1_0_reg_98035; +reg [7:0] phi_ln1265_17_reg_98047; +reg [31:0] fh9_0_1_0_1_1_0_reg_98117; +reg [31:0] fw10_0_1_0_1_1_0_0_reg_98129; +reg [7:0] phi_ln1265_20_reg_98141; +reg [31:0] fw10_0_1_0_1_1_1_0_reg_98211; +reg [7:0] phi_ln1265_29_reg_98223; +reg [3:0] ff7_0_1_1_0_reg_98293; +reg [2:0] cc8_0_1_1_0_0_reg_98305; +reg [31:0] fh9_0_1_1_0_0_0_reg_98317; +reg [31:0] fw10_0_1_1_0_0_0_0_reg_98329; +reg [7:0] phi_ln1265_4_reg_98341; +reg [31:0] fw10_0_1_1_0_0_1_0_reg_98413; +reg [7:0] phi_ln1265_16_reg_98425; +reg [31:0] fh9_0_1_1_0_1_0_reg_98497; +reg [31:0] fw10_0_1_1_0_1_0_0_reg_98509; +reg [7:0] phi_ln1265_19_reg_98521; +reg [31:0] fw10_0_1_1_0_1_1_0_reg_98593; +reg [7:0] phi_ln1265_28_reg_98605; +reg [2:0] cc8_0_1_1_1_0_reg_98677; +reg [31:0] fh9_0_1_1_1_0_0_reg_98689; +reg [31:0] fw10_0_1_1_1_0_0_0_reg_98701; +reg [7:0] phi_ln1265_7_reg_98713; +reg [31:0] fw10_0_1_1_1_0_1_0_reg_98783; +reg [7:0] phi_ln1265_22_reg_98795; +reg [31:0] fh9_0_1_1_1_1_0_reg_98865; +reg [31:0] fw10_0_1_1_1_1_0_0_reg_98877; +reg [7:0] phi_ln1265_23_reg_98889; +reg [31:0] fw10_0_1_1_1_1_1_0_reg_98959; +reg [7:0] phi_ln1265_31_reg_98971; +wire [63:0] zext_ln1116_fu_102366_p1; +wire [63:0] zext_ln203_20_fu_102483_p1; +wire [63:0] zext_ln1116_4_fu_102658_p1; +wire [63:0] zext_ln203_13_fu_102947_p1; +wire [63:0] zext_ln203_34_fu_103025_p1; +wire [63:0] zext_ln203_30_fu_103085_p1; +wire [63:0] zext_ln1116_7_fu_103248_p1; +wire [63:0] zext_ln203_41_fu_103365_p1; +wire [63:0] zext_ln1116_16_fu_103540_p1; +wire [63:0] zext_ln203_33_fu_103639_p1; +wire [63:0] zext_ln203_58_fu_103717_p1; +wire [63:0] zext_ln203_54_fu_103777_p1; +wire [63:0] zext_ln1116_8_fu_104054_p1; +wire [63:0] zext_ln203_44_fu_104169_p1; +wire [63:0] zext_ln1116_17_fu_104344_p1; +wire [63:0] zext_ln203_35_fu_104556_p1; +wire [63:0] zext_ln203_62_fu_104634_p1; +wire [63:0] zext_ln203_55_fu_104694_p1; +wire [63:0] zext_ln1116_22_fu_104857_p1; +wire [63:0] zext_ln203_71_fu_104972_p1; +wire [63:0] zext_ln1116_28_fu_105147_p1; +wire [63:0] zext_ln203_61_fu_105244_p1; +wire [63:0] zext_ln203_81_fu_105322_p1; +wire [63:0] zext_ln203_78_fu_105382_p1; +wire [63:0] zext_ln1116_2_fu_105786_p1; +wire [63:0] zext_ln203_27_fu_105902_p1; +wire [63:0] zext_ln1116_6_fu_106076_p1; +wire [63:0] zext_ln203_19_fu_106364_p1; +wire [63:0] zext_ln203_40_fu_106442_p1; +wire [63:0] zext_ln203_32_fu_106502_p1; +wire [63:0] zext_ln1116_11_fu_106664_p1; +wire [63:0] zext_ln203_48_fu_106781_p1; +wire [63:0] zext_ln1116_19_fu_106955_p1; +wire [63:0] zext_ln203_39_fu_107054_p1; +wire [63:0] zext_ln203_65_fu_107132_p1; +wire [63:0] zext_ln203_57_fu_107192_p1; +wire [63:0] zext_ln1116_13_fu_107468_p1; +wire [63:0] zext_ln203_51_fu_107583_p1; +wire [63:0] zext_ln1116_21_fu_107757_p1; +wire [63:0] zext_ln203_43_fu_107969_p1; +wire [63:0] zext_ln203_70_fu_108047_p1; +wire [63:0] zext_ln203_60_fu_108107_p1; +wire [63:0] zext_ln1116_26_fu_108269_p1; +wire [63:0] zext_ln203_76_fu_108384_p1; +wire [63:0] zext_ln1116_30_fu_108558_p1; +wire [63:0] zext_ln203_69_fu_108655_p1; +wire [63:0] zext_ln203_84_fu_108733_p1; +wire [63:0] zext_ln203_80_fu_108793_p1; +wire [63:0] zext_ln1116_1_fu_109227_p1; +wire [63:0] zext_ln203_26_fu_109343_p1; +wire [63:0] zext_ln1116_5_fu_109518_p1; +wire [63:0] zext_ln203_18_fu_109812_p1; +wire [63:0] zext_ln203_38_fu_109890_p1; +wire [63:0] zext_ln203_31_fu_109950_p1; +wire [63:0] zext_ln1116_10_fu_110109_p1; +wire [63:0] zext_ln203_47_fu_110226_p1; +wire [63:0] zext_ln1116_18_fu_110401_p1; +wire [63:0] zext_ln203_37_fu_110500_p1; +wire [63:0] zext_ln203_64_fu_110578_p1; +wire [63:0] zext_ln203_56_fu_110638_p1; +wire [63:0] zext_ln1116_12_fu_110906_p1; +wire [63:0] zext_ln203_50_fu_111021_p1; +wire [63:0] zext_ln1116_20_fu_111196_p1; +wire [63:0] zext_ln203_42_fu_111414_p1; +wire [63:0] zext_ln203_68_fu_111492_p1; +wire [63:0] zext_ln203_59_fu_111552_p1; +wire [63:0] zext_ln1116_25_fu_111711_p1; +wire [63:0] zext_ln203_75_fu_111826_p1; +wire [63:0] zext_ln1116_29_fu_112001_p1; +wire [63:0] zext_ln203_67_fu_112098_p1; +wire [63:0] zext_ln203_83_fu_112176_p1; +wire [63:0] zext_ln203_79_fu_112236_p1; +wire [63:0] zext_ln1116_3_fu_112629_p1; +wire [63:0] zext_ln203_29_fu_112745_p1; +wire [63:0] zext_ln1116_9_fu_112919_p1; +wire [63:0] zext_ln203_25_fu_113207_p1; +wire [63:0] zext_ln203_46_fu_113285_p1; +wire [63:0] zext_ln203_36_fu_113345_p1; +wire [63:0] zext_ln1116_14_fu_113507_p1; +wire [63:0] zext_ln203_52_fu_113624_p1; +wire [63:0] zext_ln1116_23_fu_113798_p1; +wire [63:0] zext_ln203_45_fu_113897_p1; +wire [63:0] zext_ln203_72_fu_113975_p1; +wire [63:0] zext_ln203_63_fu_114035_p1; +wire [63:0] zext_ln1116_15_fu_114302_p1; +wire [63:0] zext_ln203_53_fu_114417_p1; +wire [63:0] zext_ln1116_24_fu_114591_p1; +wire [63:0] zext_ln203_49_fu_114803_p1; +wire [63:0] zext_ln203_74_fu_114881_p1; +wire [63:0] zext_ln203_66_fu_114941_p1; +wire [63:0] zext_ln1116_27_fu_115103_p1; +wire [63:0] zext_ln203_77_fu_115218_p1; +wire [63:0] zext_ln1116_31_fu_115392_p1; +wire [63:0] zext_ln203_73_fu_115489_p1; +wire [63:0] zext_ln203_85_fu_115567_p1; +wire [63:0] zext_ln203_82_fu_115627_p1; +wire [63:0] zext_ln203_8_fu_115848_p1; +wire [63:0] zext_ln203_17_fu_116041_p1; +wire [63:0] zext_ln203_12_fu_116224_p1; +wire [63:0] zext_ln203_24_fu_116374_p1; +wire [63:0] zext_ln203_10_fu_116612_p1; +wire [63:0] zext_ln203_22_fu_116805_p1; +wire [63:0] zext_ln203_15_fu_116988_p1; +wire [63:0] zext_ln203_28_fu_117138_p1; +wire [63:0] zext_ln1265_fu_117359_p1; +wire [63:0] zext_ln1265_3_fu_117535_p1; +wire [63:0] zext_ln1265_8_fu_117650_p1; +wire [63:0] zext_ln1265_12_fu_117900_p1; +wire [63:0] zext_ln1265_23_fu_118066_p1; +wire [63:0] zext_ln1265_32_fu_118276_p1; +wire [63:0] zext_ln1265_24_fu_118459_p1; +wire [63:0] zext_ln1265_36_fu_118698_p1; +wire [63:0] zext_ln1265_54_fu_118864_p1; +wire [63:0] zext_ln1265_60_fu_119074_p1; +wire [63:0] zext_ln1265_11_fu_119276_p1; +wire [63:0] zext_ln1265_18_fu_119526_p1; +wire [63:0] zext_ln1265_28_fu_119691_p1; +wire [63:0] zext_ln1265_42_fu_119901_p1; +wire [63:0] zext_ln1265_31_fu_120083_p1; +wire [63:0] zext_ln1265_46_fu_120322_p1; +wire [63:0] zext_ln1265_59_fu_120487_p1; +wire [63:0] zext_ln1265_66_fu_120697_p1; +wire [63:0] zext_ln1265_2_fu_120874_p1; +wire [63:0] zext_ln1265_6_fu_121003_p1; +wire [63:0] zext_ln1265_10_fu_121118_p1; +wire [63:0] zext_ln1265_17_fu_121368_p1; +wire [63:0] zext_ln1265_27_fu_121534_p1; +wire [63:0] zext_ln1265_41_fu_121744_p1; +wire [63:0] zext_ln1265_30_fu_121927_p1; +wire [63:0] zext_ln1265_45_fu_122166_p1; +wire [63:0] zext_ln1265_58_fu_122332_p1; +wire [63:0] zext_ln1265_65_fu_122542_p1; +wire [63:0] zext_ln1265_15_fu_122744_p1; +wire [63:0] zext_ln1265_22_fu_122994_p1; +wire [63:0] zext_ln1265_35_fu_123159_p1; +wire [63:0] zext_ln1265_50_fu_123369_p1; +wire [63:0] zext_ln1265_40_fu_123551_p1; +wire [63:0] zext_ln1265_53_fu_123790_p1; +wire [63:0] zext_ln1265_63_fu_123955_p1; +wire [63:0] zext_ln1265_70_fu_124165_p1; +wire [63:0] zext_ln1265_1_fu_124401_p1; +wire [63:0] zext_ln1265_5_fu_124577_p1; +wire [63:0] zext_ln1265_9_fu_124692_p1; +wire [63:0] zext_ln1265_16_fu_124942_p1; +wire [63:0] zext_ln1265_26_fu_125108_p1; +wire [63:0] zext_ln1265_39_fu_125318_p1; +wire [63:0] zext_ln1265_29_fu_125501_p1; +wire [63:0] zext_ln1265_44_fu_125740_p1; +wire [63:0] zext_ln1265_57_fu_125906_p1; +wire [63:0] zext_ln1265_64_fu_126116_p1; +wire [63:0] zext_ln1265_14_fu_126318_p1; +wire [63:0] zext_ln1265_21_fu_126568_p1; +wire [63:0] zext_ln1265_34_fu_126733_p1; +wire [63:0] zext_ln1265_49_fu_126943_p1; +wire [63:0] zext_ln1265_38_fu_127125_p1; +wire [63:0] zext_ln1265_52_fu_127364_p1; +wire [63:0] zext_ln1265_62_fu_127529_p1; +wire [63:0] zext_ln1265_69_fu_127739_p1; +wire [63:0] zext_ln1265_4_fu_127916_p1; +wire [63:0] zext_ln1265_7_fu_128045_p1; +wire [63:0] zext_ln1265_13_fu_128160_p1; +wire [63:0] zext_ln1265_20_fu_128410_p1; +wire [63:0] zext_ln1265_33_fu_128576_p1; +wire [63:0] zext_ln1265_48_fu_128786_p1; +wire [63:0] zext_ln1265_37_fu_128969_p1; +wire [63:0] zext_ln1265_51_fu_129208_p1; +wire [63:0] zext_ln1265_61_fu_129374_p1; +wire [63:0] zext_ln1265_68_fu_129584_p1; +wire [63:0] zext_ln1265_19_fu_129786_p1; +wire [63:0] zext_ln1265_25_fu_130036_p1; +wire [63:0] zext_ln1265_43_fu_130201_p1; +wire [63:0] zext_ln1265_55_fu_130411_p1; +wire [63:0] zext_ln1265_47_fu_130593_p1; +wire [63:0] zext_ln1265_56_fu_130832_p1; +wire [63:0] zext_ln1265_67_fu_130997_p1; +wire [63:0] zext_ln1265_71_fu_131207_p1; +wire [5:0] trunc_ln203_39_fu_102479_p1; +wire [5:0] trunc_ln203_fu_102943_p1; +wire [5:0] trunc_ln203_48_fu_103021_p1; +wire [5:0] trunc_ln203_44_fu_103081_p1; +wire [5:0] trunc_ln203_55_fu_103361_p1; +wire [5:0] trunc_ln203_47_fu_103635_p1; +wire [5:0] trunc_ln203_72_fu_103713_p1; +wire [5:0] trunc_ln203_68_fu_103773_p1; +wire [5:0] trunc_ln203_58_fu_104165_p1; +wire [5:0] trunc_ln203_49_fu_104552_p1; +wire [5:0] trunc_ln203_76_fu_104630_p1; +wire [5:0] trunc_ln203_69_fu_104690_p1; +wire [5:0] trunc_ln203_85_fu_104968_p1; +wire [5:0] trunc_ln203_75_fu_105240_p1; +wire [5:0] trunc_ln203_95_fu_105318_p1; +wire [5:0] trunc_ln203_92_fu_105378_p1; +wire [5:0] trunc_ln203_42_fu_105898_p1; +wire [5:0] trunc_ln203_38_fu_106360_p1; +wire [5:0] trunc_ln203_54_fu_106438_p1; +wire [5:0] trunc_ln203_46_fu_106498_p1; +wire [5:0] trunc_ln203_62_fu_106777_p1; +wire [5:0] trunc_ln203_53_fu_107050_p1; +wire [5:0] trunc_ln203_79_fu_107128_p1; +wire [5:0] trunc_ln203_71_fu_107188_p1; +wire [5:0] trunc_ln203_65_fu_107579_p1; +wire [5:0] trunc_ln203_57_fu_107965_p1; +wire [5:0] trunc_ln203_84_fu_108043_p1; +wire [5:0] trunc_ln203_74_fu_108103_p1; +wire [5:0] trunc_ln203_90_fu_108380_p1; +wire [5:0] trunc_ln203_83_fu_108651_p1; +wire [5:0] trunc_ln203_98_fu_108729_p1; +wire [5:0] trunc_ln203_94_fu_108789_p1; +wire [5:0] trunc_ln203_41_fu_109339_p1; +wire [5:0] trunc_ln203_37_fu_109808_p1; +wire [5:0] trunc_ln203_52_fu_109886_p1; +wire [5:0] trunc_ln203_45_fu_109946_p1; +wire [5:0] trunc_ln203_61_fu_110222_p1; +wire [5:0] trunc_ln203_51_fu_110496_p1; +wire [5:0] trunc_ln203_78_fu_110574_p1; +wire [5:0] trunc_ln203_70_fu_110634_p1; +wire [5:0] trunc_ln203_64_fu_111017_p1; +wire [5:0] trunc_ln203_56_fu_111410_p1; +wire [5:0] trunc_ln203_82_fu_111488_p1; +wire [5:0] trunc_ln203_73_fu_111548_p1; +wire [5:0] trunc_ln203_89_fu_111822_p1; +wire [5:0] trunc_ln203_81_fu_112094_p1; +wire [5:0] trunc_ln203_97_fu_112172_p1; +wire [5:0] trunc_ln203_93_fu_112232_p1; +wire [5:0] trunc_ln203_43_fu_112741_p1; +wire [5:0] trunc_ln203_40_fu_113203_p1; +wire [5:0] trunc_ln203_60_fu_113281_p1; +wire [5:0] trunc_ln203_50_fu_113341_p1; +wire [5:0] trunc_ln203_66_fu_113620_p1; +wire [5:0] trunc_ln203_59_fu_113893_p1; +wire [5:0] trunc_ln203_86_fu_113971_p1; +wire [5:0] trunc_ln203_77_fu_114031_p1; +wire [5:0] trunc_ln203_67_fu_114413_p1; +wire [5:0] trunc_ln203_63_fu_114799_p1; +wire [5:0] trunc_ln203_88_fu_114877_p1; +wire [5:0] trunc_ln203_80_fu_114937_p1; +wire [5:0] trunc_ln203_91_fu_115214_p1; +wire [5:0] trunc_ln203_87_fu_115485_p1; +wire [5:0] trunc_ln203_99_fu_115563_p1; +wire [5:0] trunc_ln203_96_fu_115623_p1; +wire [5:0] add_ln203_4_fu_115829_p2; +wire [7:0] phi_ln_fu_115758_p18; +wire [5:0] add_ln203_6_fu_116205_p2; +wire [7:0] phi_ln203_2_fu_116134_p18; +wire [5:0] add_ln203_5_fu_116593_p2; +wire [7:0] phi_ln203_1_fu_116522_p18; +wire [5:0] add_ln203_8_fu_116969_p2; +wire [7:0] phi_ln203_3_fu_116898_p18; +wire [7:0] add_ln703_4_fu_117993_p2; +wire [7:0] add_ln703_24_fu_118369_p2; +wire [7:0] add_ln703_28_fu_118791_p2; +wire [7:0] add_ln703_52_fu_119167_p2; +wire [7:0] add_ln703_9_fu_121461_p2; +wire [7:0] add_ln703_33_fu_121837_p2; +wire [7:0] add_ln703_37_fu_122259_p2; +wire [7:0] add_ln703_57_fu_122635_p2; +wire [7:0] add_ln703_8_fu_125035_p2; +wire [7:0] add_ln703_31_fu_125411_p2; +wire [7:0] add_ln703_36_fu_125833_p2; +wire [7:0] add_ln703_56_fu_126209_p2; +wire [7:0] add_ln703_12_fu_128503_p2; +wire [7:0] add_ln703_40_fu_128879_p2; +wire [7:0] add_ln703_43_fu_129301_p2; +wire [7:0] add_ln703_60_fu_129677_p2; +wire [7:0] add_ln703_10_fu_119619_p2; +wire [7:0] add_ln703_34_fu_119994_p2; +wire [7:0] add_ln703_38_fu_120415_p2; +wire [7:0] add_ln703_58_fu_120790_p2; +wire [7:0] add_ln703_14_fu_123087_p2; +wire [7:0] add_ln703_42_fu_123462_p2; +wire [7:0] add_ln703_45_fu_123883_p2; +wire [7:0] add_ln703_62_fu_124258_p2; +wire [7:0] add_ln703_13_fu_126661_p2; +wire [7:0] add_ln703_41_fu_127036_p2; +wire [7:0] add_ln703_44_fu_127457_p2; +wire [7:0] add_ln703_61_fu_127832_p2; +wire [7:0] add_ln703_17_fu_130129_p2; +wire [7:0] add_ln703_47_fu_130504_p2; +wire [7:0] add_ln703_48_fu_130925_p2; +wire [7:0] add_ln703_63_fu_131300_p2; +reg [31:0] grp_fu_99041_p1; +wire [31:0] grp_fu_99047_p0; +wire [5:0] grp_fu_99047_p1; +reg [31:0] grp_fu_99053_p0; +wire [5:0] grp_fu_99053_p1; +reg [31:0] grp_fu_99058_p1; +wire [31:0] grp_fu_99064_p0; +wire [5:0] grp_fu_99064_p1; +reg [31:0] grp_fu_99070_p0; +wire [5:0] grp_fu_99070_p1; +reg [31:0] grp_fu_99075_p1; +wire [31:0] grp_fu_99081_p0; +wire [5:0] grp_fu_99081_p1; +reg [31:0] grp_fu_99087_p0; +wire [5:0] grp_fu_99087_p1; +reg [31:0] grp_fu_99092_p1; +wire [31:0] grp_fu_99098_p0; +wire [5:0] grp_fu_99098_p1; +reg [31:0] grp_fu_99104_p0; +wire [5:0] grp_fu_99104_p1; +reg [31:0] grp_fu_99109_p1; +wire [31:0] grp_fu_99115_p0; +wire [5:0] grp_fu_99115_p1; +reg [31:0] grp_fu_99121_p0; +wire [5:0] grp_fu_99121_p1; +reg [31:0] grp_fu_99126_p1; +wire [31:0] grp_fu_99132_p0; +wire [5:0] grp_fu_99132_p1; +reg [31:0] grp_fu_99138_p0; +wire [5:0] grp_fu_99138_p1; +reg [31:0] grp_fu_99143_p1; +wire [31:0] grp_fu_99149_p0; +wire [5:0] grp_fu_99149_p1; +reg [31:0] grp_fu_99155_p0; +wire [5:0] grp_fu_99155_p1; +reg [31:0] grp_fu_99160_p1; +wire [31:0] grp_fu_99166_p0; +wire [5:0] grp_fu_99166_p1; +reg [31:0] grp_fu_99172_p0; +wire [5:0] grp_fu_99172_p1; +reg [31:0] grp_fu_99177_p1; +wire [31:0] grp_fu_99183_p0; +wire [5:0] grp_fu_99183_p1; +reg [31:0] grp_fu_99189_p0; +wire [5:0] grp_fu_99189_p1; +reg [31:0] grp_fu_99194_p1; +wire [31:0] grp_fu_99200_p0; +wire [5:0] grp_fu_99200_p1; +reg [31:0] grp_fu_99206_p0; +wire [5:0] grp_fu_99206_p1; +reg [31:0] grp_fu_99211_p1; +wire [31:0] grp_fu_99217_p0; +wire [5:0] grp_fu_99217_p1; +reg [31:0] grp_fu_99223_p0; +wire [5:0] grp_fu_99223_p1; +reg [31:0] grp_fu_99228_p1; +wire [31:0] grp_fu_99234_p0; +wire [5:0] grp_fu_99234_p1; +reg [31:0] grp_fu_99240_p0; +wire [5:0] grp_fu_99240_p1; +reg [31:0] grp_fu_99245_p1; +wire [31:0] grp_fu_99251_p0; +wire [5:0] grp_fu_99251_p1; +reg [31:0] grp_fu_99257_p0; +wire [5:0] grp_fu_99257_p1; +reg [31:0] grp_fu_99262_p1; +wire [31:0] grp_fu_99268_p0; +wire [5:0] grp_fu_99268_p1; +reg [31:0] grp_fu_99274_p0; +wire [5:0] grp_fu_99274_p1; +reg [31:0] grp_fu_99279_p1; +wire [31:0] grp_fu_99285_p0; +wire [5:0] grp_fu_99285_p1; +reg [31:0] grp_fu_99291_p0; +wire [5:0] grp_fu_99291_p1; +reg [31:0] grp_fu_99296_p1; +wire [31:0] grp_fu_99302_p0; +wire [5:0] grp_fu_99302_p1; +reg [31:0] grp_fu_99308_p0; +wire [5:0] grp_fu_99308_p1; +wire [3:0] mul_ln201_fu_101932_p0; +wire [3:0] mul_ln203_fu_101952_p0; +wire [3:0] or_ln199_fu_101958_p2; +wire [3:0] mul_ln201_1_fu_101972_p0; +wire [14:0] zext_ln216_fu_102000_p1; +wire [14:0] add_ln216_fu_102004_p2; +wire [17:0] zext_ln216_1_fu_102009_p1; +wire [3:0] mul_ln203_2_fu_102032_p0; +wire [5:0] shl_ln2_fu_102052_p3; +wire [3:0] shl_ln221_1_fu_102064_p3; +wire [6:0] zext_ln221_1_fu_102060_p1; +wire [6:0] zext_ln221_2_fu_102072_p1; +wire [6:0] sub_ln221_fu_102076_p2; +wire [6:0] add_ln221_fu_102082_p2; +wire [17:0] grp_fu_131342_p3; +wire [7:0] or_ln_fu_102094_p3; +wire [3:0] or_ln231_1_fu_102106_p3; +wire [31:0] add_ln223_fu_102118_p2; +wire [30:0] tmp_241_fu_102123_p4; +wire [27:0] tmp_242_fu_102139_p4; +wire [0:0] icmp_ln223_fu_102133_p2; +wire [0:0] icmp_ln223_48_fu_102149_p2; +wire [31:0] shl_ln231_fu_102161_p2; +wire [31:0] shl_ln231_16_fu_102167_p2; +wire [31:0] sub_ln231_fu_102173_p2; +wire [31:0] shl_ln221_fu_102199_p2; +wire [31:0] shl_ln221_24_fu_102205_p2; +wire [31:0] add_ln216_9_fu_102217_p2; +wire [31:0] shl_ln216_fu_102193_p2; +wire [31:0] sub_ln221_1_fu_102211_p2; +wire [31:0] shl_ln221_27_fu_102246_p2; +wire [31:0] shl_ln221_28_fu_102252_p2; +wire [31:0] sub_ln221_4_fu_102258_p2; +wire [31:0] add_ln223_3_fu_102269_p2; +wire [30:0] tmp_247_fu_102278_p4; +wire [27:0] tmp_248_fu_102294_p4; +wire [0:0] icmp_ln223_53_fu_102288_p2; +wire [0:0] icmp_ln223_54_fu_102304_p2; +wire [3:0] trunc_ln223_fu_102274_p1; +wire [3:0] add_ln231_6_fu_102316_p2; +wire [5:0] shl_ln231_6_fu_102322_p3; +wire [10:0] zext_ln231_5_fu_102330_p1; +wire [31:0] add_ln221_4_fu_102264_p2; +wire [6:0] zext_ln231_6_fu_102334_p1; +wire [10:0] add_ln231_2_fu_102338_p2; +wire [3:0] trunc_ln1_fu_102352_p4; +wire [24:0] sext_ln1116_fu_102362_p1; +wire [33:0] grp_fu_102439_p0; +wire [31:0] grp_fu_102439_p1; +wire [3:0] mul_ln1118_fu_102453_p0; +wire [7:0] mul_ln1118_fu_102453_p1; +wire [11:0] mul_ln1118_fu_102453_p2; +wire [64:0] grp_fu_102439_p2; +wire [5:0] grp_fu_99047_p2; +wire [31:0] or_ln208_fu_102518_p2; +wire [31:0] shl_ln221_45_fu_102536_p2; +wire [31:0] shl_ln221_46_fu_102542_p2; +wire [31:0] sub_ln221_12_fu_102548_p2; +wire [3:0] trunc_ln223_4_fu_102514_p1; +wire [31:0] add_ln223_9_fu_102565_p2; +wire [30:0] tmp_272_fu_102570_p4; +wire [27:0] tmp_273_fu_102586_p4; +wire [0:0] icmp_ln223_65_fu_102580_p2; +wire [0:0] icmp_ln223_66_fu_102596_p2; +wire [3:0] or_ln223_48_fu_102559_p2; +wire [3:0] add_ln231_19_fu_102608_p2; +wire [5:0] shl_ln231_2_fu_102614_p3; +wire [10:0] zext_ln231_14_fu_102622_p1; +wire [31:0] add_ln221_14_fu_102554_p2; +wire [6:0] zext_ln231_15_fu_102626_p1; +wire [10:0] add_ln231_14_fu_102630_p2; +wire [3:0] trunc_ln1116_4_fu_102644_p4; +wire [24:0] sext_ln1116_4_fu_102654_p1; +wire [31:0] or_ln206_fu_102727_p2; +wire [31:0] shl_ln221_47_fu_102745_p2; +wire [31:0] shl_ln221_48_fu_102751_p2; +wire [31:0] add_ln223_8_fu_102763_p2; +wire [30:0] tmp_270_fu_102768_p4; +wire [27:0] tmp_271_fu_102784_p4; +wire [31:0] shl_ln231_24_fu_102800_p2; +wire [31:0] shl_ln231_27_fu_102806_p2; +wire [31:0] add_ln216_28_fu_102818_p2; +wire [31:0] shl_ln216_11_fu_102739_p2; +wire [31:0] sub_ln221_14_fu_102757_p2; +wire [31:0] sub_ln231_4_fu_102812_p2; +wire [1:0] or_ln204_fu_102842_p2; +wire [5:0] shl_ln221_3_fu_102851_p3; +wire [3:0] shl_ln221_8_fu_102863_p3; +wire [6:0] zext_ln221_13_fu_102859_p1; +wire [6:0] zext_ln221_14_fu_102871_p1; +wire [6:0] sub_ln221_13_fu_102875_p2; +wire [6:0] add_ln221_19_fu_102881_p2; +wire [17:0] grp_fu_131350_p3; +wire [7:0] or_ln231_9_fu_102899_p3; +wire [3:0] or_ln231_10_fu_102911_p3; +wire [33:0] grp_fu_102927_p0; +wire [31:0] grp_fu_102927_p1; +wire [64:0] grp_fu_102927_p2; +wire [3:0] mul_ln1118_13_fu_102986_p0; +wire [7:0] mul_ln1118_13_fu_102986_p1; +wire [11:0] mul_ln1118_13_fu_102986_p2; +wire [33:0] grp_fu_103005_p0; +wire [31:0] grp_fu_103005_p1; +wire [64:0] grp_fu_103005_p2; +wire [5:0] grp_fu_99053_p2; +wire [33:0] grp_fu_103065_p0; +wire [31:0] grp_fu_103065_p1; +wire [64:0] grp_fu_103065_p2; +wire [31:0] shl_ln221_55_fu_103128_p2; +wire [31:0] shl_ln221_56_fu_103134_p2; +wire [31:0] sub_ln221_18_fu_103140_p2; +wire [31:0] add_ln223_15_fu_103151_p2; +wire [30:0] tmp_291_fu_103160_p4; +wire [27:0] tmp_292_fu_103176_p4; +wire [0:0] icmp_ln223_77_fu_103170_p2; +wire [0:0] icmp_ln223_78_fu_103186_p2; +wire [3:0] trunc_ln223_8_fu_103156_p1; +wire [3:0] add_ln231_34_fu_103198_p2; +wire [5:0] shl_ln231_5_fu_103204_p3; +wire [10:0] zext_ln231_22_fu_103212_p1; +wire [31:0] add_ln221_18_fu_103146_p2; +wire [6:0] zext_ln231_23_fu_103216_p1; +wire [10:0] add_ln231_23_fu_103220_p2; +wire [3:0] trunc_ln1116_7_fu_103234_p4; +wire [24:0] sext_ln1116_7_fu_103244_p1; +wire [33:0] grp_fu_103321_p0; +wire [31:0] grp_fu_103321_p1; +wire [3:0] mul_ln1118_16_fu_103335_p0; +wire [7:0] mul_ln1118_16_fu_103335_p1; +wire [11:0] mul_ln1118_16_fu_103335_p2; +wire [64:0] grp_fu_103321_p2; +wire [5:0] grp_fu_99064_p2; +wire [31:0] or_ln208_4_fu_103400_p2; +wire [31:0] shl_ln221_87_fu_103418_p2; +wire [31:0] shl_ln221_88_fu_103424_p2; +wire [31:0] sub_ln221_36_fu_103430_p2; +wire [3:0] trunc_ln223_16_fu_103396_p1; +wire [31:0] add_ln223_28_fu_103447_p2; +wire [30:0] tmp_368_fu_103452_p4; +wire [27:0] tmp_369_fu_103468_p4; +wire [0:0] icmp_ln223_103_fu_103462_p2; +wire [0:0] icmp_ln223_104_fu_103478_p2; +wire [3:0] or_ln223_52_fu_103441_p2; +wire [3:0] add_ln231_57_fu_103490_p2; +wire [5:0] shl_ln231_22_fu_103496_p3; +wire [10:0] zext_ln231_41_fu_103504_p1; +wire [31:0] add_ln221_38_fu_103436_p2; +wire [6:0] zext_ln231_42_fu_103508_p1; +wire [10:0] add_ln231_50_fu_103512_p2; +wire [3:0] trunc_ln1116_15_fu_103526_p4; +wire [24:0] sext_ln1116_16_fu_103536_p1; +wire [33:0] grp_fu_103619_p0; +wire [31:0] grp_fu_103619_p1; +wire [64:0] grp_fu_103619_p2; +wire [3:0] mul_ln1118_25_fu_103678_p0; +wire [7:0] mul_ln1118_25_fu_103678_p1; +wire [11:0] mul_ln1118_25_fu_103678_p2; +wire [33:0] grp_fu_103697_p0; +wire [31:0] grp_fu_103697_p1; +wire [64:0] grp_fu_103697_p2; +wire [5:0] grp_fu_99070_p2; +wire [33:0] grp_fu_103757_p0; +wire [31:0] grp_fu_103757_p1; +wire [64:0] grp_fu_103757_p2; +wire [31:0] add_ln223_10_fu_103808_p2; +wire [30:0] tmp_277_fu_103813_p4; +wire [27:0] tmp_278_fu_103829_p4; +wire [31:0] shl_ln231_28_fu_103845_p2; +wire [31:0] shl_ln231_30_fu_103851_p2; +wire [31:0] sub_ln231_5_fu_103857_p2; +wire [2:0] tmp_71_fu_103867_p4; +wire [31:0] shl_ln221_53_fu_103892_p2; +wire [31:0] shl_ln221_54_fu_103898_p2; +wire [31:0] add_ln216_31_fu_103914_p2; +wire [31:0] shl_ln216_12_fu_103886_p2; +wire [31:0] sub_ln221_17_fu_103904_p2; +wire [31:0] shl_ln221_63_fu_103934_p2; +wire [31:0] shl_ln221_64_fu_103940_p2; +wire [31:0] sub_ln221_23_fu_103946_p2; +wire [31:0] add_ln223_18_fu_103957_p2; +wire [30:0] tmp_300_fu_103966_p4; +wire [27:0] tmp_301_fu_103982_p4; +wire [0:0] icmp_ln223_83_fu_103976_p2; +wire [0:0] icmp_ln223_84_fu_103992_p2; +wire [3:0] trunc_ln223_9_fu_103962_p1; +wire [3:0] add_ln231_39_fu_104004_p2; +wire [5:0] shl_ln231_7_fu_104010_p3; +wire [10:0] zext_ln231_25_fu_104018_p1; +wire [31:0] add_ln221_21_fu_103952_p2; +wire [6:0] zext_ln231_26_fu_104022_p1; +wire [10:0] add_ln231_26_fu_104026_p2; +wire [3:0] trunc_ln1116_8_fu_104040_p4; +wire [24:0] sext_ln1116_8_fu_104050_p1; +wire [33:0] grp_fu_104125_p0; +wire [31:0] grp_fu_104125_p1; +wire [3:0] mul_ln1118_17_fu_104139_p0; +wire [7:0] mul_ln1118_17_fu_104139_p1; +wire [11:0] mul_ln1118_17_fu_104139_p2; +wire [64:0] grp_fu_104125_p2; +wire [5:0] grp_fu_99081_p2; +wire [31:0] or_ln208_5_fu_104204_p2; +wire [31:0] shl_ln221_89_fu_104222_p2; +wire [31:0] shl_ln221_90_fu_104228_p2; +wire [31:0] sub_ln221_37_fu_104234_p2; +wire [3:0] trunc_ln223_17_fu_104200_p1; +wire [31:0] add_ln223_30_fu_104251_p2; +wire [30:0] tmp_376_fu_104256_p4; +wire [27:0] tmp_377_fu_104272_p4; +wire [0:0] icmp_ln223_107_fu_104266_p2; +wire [0:0] icmp_ln223_108_fu_104282_p2; +wire [3:0] or_ln223_53_fu_104245_p2; +wire [3:0] add_ln231_58_fu_104294_p2; +wire [5:0] shl_ln231_25_fu_104300_p3; +wire [10:0] zext_ln231_43_fu_104308_p1; +wire [31:0] add_ln221_39_fu_104240_p2; +wire [6:0] zext_ln231_44_fu_104312_p1; +wire [10:0] add_ln231_53_fu_104316_p2; +wire [3:0] trunc_ln1116_16_fu_104330_p4; +wire [24:0] sext_ln1116_17_fu_104340_p1; +wire [31:0] or_ln206_4_fu_104412_p2; +wire [31:0] shl_ln221_95_fu_104430_p2; +wire [31:0] shl_ln221_96_fu_104436_p2; +wire [31:0] add_ln223_29_fu_104448_p2; +wire [30:0] tmp_374_fu_104453_p4; +wire [27:0] tmp_375_fu_104469_p4; +wire [31:0] shl_ln231_66_fu_104485_p2; +wire [31:0] shl_ln231_67_fu_104491_p2; +wire [31:0] add_ln216_60_fu_104503_p2; +wire [31:0] shl_ln216_19_fu_104424_p2; +wire [31:0] sub_ln221_40_fu_104442_p2; +wire [31:0] sub_ln231_12_fu_104497_p2; +wire [33:0] grp_fu_104536_p0; +wire [31:0] grp_fu_104536_p1; +wire [64:0] grp_fu_104536_p2; +wire [3:0] mul_ln1118_26_fu_104595_p0; +wire [7:0] mul_ln1118_26_fu_104595_p1; +wire [11:0] mul_ln1118_26_fu_104595_p2; +wire [33:0] grp_fu_104614_p0; +wire [31:0] grp_fu_104614_p1; +wire [64:0] grp_fu_104614_p2; +wire [5:0] grp_fu_99087_p2; +wire [33:0] grp_fu_104674_p0; +wire [31:0] grp_fu_104674_p1; +wire [64:0] grp_fu_104674_p2; +wire [31:0] shl_ln221_101_fu_104737_p2; +wire [31:0] shl_ln221_102_fu_104743_p2; +wire [31:0] sub_ln221_43_fu_104749_p2; +wire [31:0] add_ln223_37_fu_104760_p2; +wire [30:0] tmp_399_fu_104769_p4; +wire [27:0] tmp_400_fu_104785_p4; +wire [0:0] icmp_ln223_121_fu_104779_p2; +wire [0:0] icmp_ln223_122_fu_104795_p2; +wire [3:0] trunc_ln223_24_fu_104765_p1; +wire [3:0] add_ln231_72_fu_104807_p2; +wire [5:0] shl_ln231_34_fu_104813_p3; +wire [10:0] zext_ln231_53_fu_104821_p1; +wire [31:0] add_ln221_45_fu_104755_p2; +wire [6:0] zext_ln231_54_fu_104825_p1; +wire [10:0] add_ln231_68_fu_104829_p2; +wire [3:0] trunc_ln1116_21_fu_104843_p4; +wire [24:0] sext_ln1116_22_fu_104853_p1; +wire [33:0] grp_fu_104928_p0; +wire [31:0] grp_fu_104928_p1; +wire [3:0] mul_ln1118_31_fu_104942_p0; +wire [7:0] mul_ln1118_31_fu_104942_p1; +wire [11:0] mul_ln1118_31_fu_104942_p2; +wire [64:0] grp_fu_104928_p2; +wire [5:0] grp_fu_99098_p2; +wire [31:0] or_ln208_12_fu_105007_p2; +wire [31:0] shl_ln221_119_fu_105025_p2; +wire [31:0] shl_ln221_120_fu_105031_p2; +wire [31:0] sub_ln221_52_fu_105037_p2; +wire [3:0] trunc_ln223_28_fu_105003_p1; +wire [31:0] add_ln223_44_fu_105054_p2; +wire [30:0] tmp_449_fu_105059_p4; +wire [27:0] tmp_450_fu_105075_p4; +wire [0:0] icmp_ln223_135_fu_105069_p2; +wire [0:0] icmp_ln223_136_fu_105085_p2; +wire [3:0] or_ln223_60_fu_105048_p2; +wire [3:0] add_ln231_88_fu_105097_p2; +wire [5:0] shl_ln231_42_fu_105103_p3; +wire [10:0] zext_ln231_65_fu_105111_p1; +wire [31:0] add_ln221_54_fu_105043_p2; +wire [6:0] zext_ln231_66_fu_105115_p1; +wire [10:0] add_ln231_84_fu_105119_p2; +wire [3:0] trunc_ln1116_27_fu_105133_p4; +wire [24:0] sext_ln1116_28_fu_105143_p1; +wire [33:0] grp_fu_105224_p0; +wire [31:0] grp_fu_105224_p1; +wire [64:0] grp_fu_105224_p2; +wire [3:0] mul_ln1118_37_fu_105283_p0; +wire [7:0] mul_ln1118_37_fu_105283_p1; +wire [11:0] mul_ln1118_37_fu_105283_p2; +wire [33:0] grp_fu_105302_p0; +wire [31:0] grp_fu_105302_p1; +wire [64:0] grp_fu_105302_p2; +wire [5:0] grp_fu_99104_p2; +wire [33:0] grp_fu_105362_p0; +wire [31:0] grp_fu_105362_p1; +wire [64:0] grp_fu_105362_p2; +wire [14:0] zext_ln216_12_fu_105435_p1; +wire [14:0] add_ln216_7_fu_105439_p2; +wire [17:0] zext_ln216_13_fu_105444_p1; +wire [5:0] shl_ln221_6_fu_105473_p3; +wire [3:0] shl_ln221_7_fu_105485_p3; +wire [6:0] zext_ln221_7_fu_105481_p1; +wire [6:0] zext_ln221_8_fu_105493_p1; +wire [6:0] sub_ln221_3_fu_105497_p2; +wire [6:0] add_ln221_8_fu_105503_p2; +wire [17:0] grp_fu_131358_p3; +wire [7:0] or_ln231_4_fu_105515_p3; +wire [3:0] or_ln231_5_fu_105527_p3; +wire [31:0] add_ln223_2_fu_105539_p2; +wire [30:0] tmp_245_fu_105544_p4; +wire [27:0] tmp_246_fu_105560_p4; +wire [0:0] icmp_ln223_51_fu_105554_p2; +wire [0:0] icmp_ln223_52_fu_105570_p2; +wire [31:0] shl_ln231_19_fu_105582_p2; +wire [31:0] shl_ln231_20_fu_105588_p2; +wire [31:0] sub_ln231_2_fu_105594_p2; +wire [31:0] shl_ln221_31_fu_105620_p2; +wire [31:0] shl_ln221_32_fu_105626_p2; +wire [31:0] add_ln216_19_fu_105638_p2; +wire [31:0] shl_ln216_9_fu_105614_p2; +wire [31:0] sub_ln221_6_fu_105632_p2; +wire [31:0] shl_ln221_35_fu_105667_p2; +wire [31:0] shl_ln221_36_fu_105673_p2; +wire [31:0] sub_ln221_9_fu_105679_p2; +wire [31:0] add_ln223_6_fu_105690_p2; +wire [30:0] tmp_254_fu_105699_p4; +wire [27:0] tmp_255_fu_105715_p4; +wire [0:0] icmp_ln223_59_fu_105709_p2; +wire [0:0] icmp_ln223_60_fu_105725_p2; +wire [3:0] trunc_ln223_2_fu_105695_p1; +wire [3:0] add_ln231_12_fu_105737_p2; +wire [5:0] shl_ln231_s_fu_105742_p3; +wire [10:0] zext_ln231_9_fu_105750_p1; +wire [31:0] add_ln221_10_fu_105685_p2; +wire [6:0] zext_ln231_10_fu_105754_p1; +wire [10:0] add_ln231_8_fu_105758_p2; +wire [3:0] trunc_ln1116_2_fu_105772_p4; +wire [24:0] sext_ln1116_2_fu_105782_p1; +wire [33:0] grp_fu_105858_p0; +wire [31:0] grp_fu_105858_p1; +wire [3:0] mul_ln1118_11_fu_105872_p0; +wire [7:0] mul_ln1118_11_fu_105872_p1; +wire [11:0] mul_ln1118_11_fu_105872_p2; +wire [64:0] grp_fu_105858_p2; +wire [5:0] grp_fu_99115_p2; +wire [31:0] or_ln208_2_fu_105937_p2; +wire [31:0] shl_ln221_51_fu_105955_p2; +wire [31:0] shl_ln221_52_fu_105961_p2; +wire [31:0] sub_ln221_16_fu_105967_p2; +wire [3:0] trunc_ln223_6_fu_105933_p1; +wire [31:0] add_ln223_14_fu_105984_p2; +wire [30:0] tmp_289_fu_105989_p4; +wire [27:0] tmp_290_fu_106005_p4; +wire [0:0] icmp_ln223_75_fu_105999_p2; +wire [0:0] icmp_ln223_76_fu_106015_p2; +wire [3:0] or_ln223_50_fu_105978_p2; +wire [3:0] add_ln231_33_fu_106027_p2; +wire [5:0] shl_ln231_4_fu_106032_p3; +wire [10:0] zext_ln231_20_fu_106040_p1; +wire [31:0] add_ln221_16_fu_105973_p2; +wire [6:0] zext_ln231_21_fu_106044_p1; +wire [10:0] add_ln231_20_fu_106048_p2; +wire [3:0] trunc_ln1116_6_fu_106062_p4; +wire [24:0] sext_ln1116_6_fu_106072_p1; +wire [31:0] or_ln206_2_fu_106145_p2; +wire [31:0] shl_ln221_61_fu_106163_p2; +wire [31:0] shl_ln221_62_fu_106169_p2; +wire [31:0] add_ln223_13_fu_106181_p2; +wire [30:0] tmp_287_fu_106186_p4; +wire [27:0] tmp_288_fu_106202_p4; +wire [31:0] shl_ln231_40_fu_106218_p2; +wire [31:0] shl_ln231_43_fu_106224_p2; +wire [31:0] add_ln216_40_fu_106236_p2; +wire [31:0] shl_ln216_14_fu_106157_p2; +wire [31:0] sub_ln221_22_fu_106175_p2; +wire [31:0] sub_ln231_7_fu_106230_p2; +wire [1:0] or_ln204_2_fu_106260_p2; +wire [5:0] shl_ln221_11_fu_106269_p3; +wire [3:0] shl_ln221_12_fu_106281_p3; +wire [6:0] zext_ln221_19_fu_106277_p1; +wire [6:0] zext_ln221_20_fu_106289_p1; +wire [6:0] sub_ln221_21_fu_106293_p2; +wire [6:0] add_ln221_30_fu_106299_p2; +wire [17:0] grp_fu_131366_p3; +wire [7:0] or_ln231_14_fu_106317_p3; +wire [3:0] or_ln231_15_fu_106329_p3; +wire [33:0] grp_fu_106344_p0; +wire [31:0] grp_fu_106344_p1; +wire [64:0] grp_fu_106344_p2; +wire [3:0] mul_ln1118_15_fu_106403_p0; +wire [7:0] mul_ln1118_15_fu_106403_p1; +wire [11:0] mul_ln1118_15_fu_106403_p2; +wire [33:0] grp_fu_106422_p0; +wire [31:0] grp_fu_106422_p1; +wire [64:0] grp_fu_106422_p2; +wire [5:0] grp_fu_99121_p2; +wire [33:0] grp_fu_106482_p0; +wire [31:0] grp_fu_106482_p1; +wire [64:0] grp_fu_106482_p2; +wire [31:0] shl_ln221_73_fu_106545_p2; +wire [31:0] shl_ln221_74_fu_106551_p2; +wire [31:0] sub_ln221_28_fu_106557_p2; +wire [31:0] add_ln223_22_fu_106568_p2; +wire [30:0] tmp_314_fu_106577_p4; +wire [27:0] tmp_315_fu_106593_p4; +wire [0:0] icmp_ln223_91_fu_106587_p2; +wire [0:0] icmp_ln223_92_fu_106603_p2; +wire [3:0] trunc_ln223_11_fu_106573_p1; +wire [3:0] add_ln231_46_fu_106615_p2; +wire [5:0] shl_ln231_11_fu_106620_p3; +wire [10:0] zext_ln231_31_fu_106628_p1; +wire [31:0] add_ln221_26_fu_106563_p2; +wire [6:0] zext_ln231_32_fu_106632_p1; +wire [10:0] add_ln231_35_fu_106636_p2; +wire [3:0] trunc_ln1116_11_fu_106650_p4; +wire [24:0] sext_ln1116_11_fu_106660_p1; +wire [33:0] grp_fu_106737_p0; +wire [31:0] grp_fu_106737_p1; +wire [3:0] mul_ln1118_20_fu_106751_p0; +wire [7:0] mul_ln1118_20_fu_106751_p1; +wire [11:0] mul_ln1118_20_fu_106751_p2; +wire [64:0] grp_fu_106737_p2; +wire [5:0] grp_fu_99132_p2; +wire [31:0] or_ln208_7_fu_106816_p2; +wire [31:0] shl_ln221_93_fu_106834_p2; +wire [31:0] shl_ln221_94_fu_106840_p2; +wire [31:0] sub_ln221_39_fu_106846_p2; +wire [3:0] trunc_ln223_19_fu_106812_p1; +wire [31:0] add_ln223_32_fu_106863_p2; +wire [30:0] tmp_385_fu_106868_p4; +wire [27:0] tmp_386_fu_106884_p4; +wire [0:0] icmp_ln223_111_fu_106878_p2; +wire [0:0] icmp_ln223_112_fu_106894_p2; +wire [3:0] or_ln223_55_fu_106857_p2; +wire [3:0] add_ln231_67_fu_106906_p2; +wire [5:0] shl_ln231_29_fu_106911_p3; +wire [10:0] zext_ln231_47_fu_106919_p1; +wire [31:0] add_ln221_41_fu_106852_p2; +wire [6:0] zext_ln231_48_fu_106923_p1; +wire [10:0] add_ln231_59_fu_106927_p2; +wire [3:0] trunc_ln1116_18_fu_106941_p4; +wire [24:0] sext_ln1116_19_fu_106951_p1; +wire [33:0] grp_fu_107034_p0; +wire [31:0] grp_fu_107034_p1; +wire [64:0] grp_fu_107034_p2; +wire [3:0] mul_ln1118_28_fu_107093_p0; +wire [7:0] mul_ln1118_28_fu_107093_p1; +wire [11:0] mul_ln1118_28_fu_107093_p2; +wire [33:0] grp_fu_107112_p0; +wire [31:0] grp_fu_107112_p1; +wire [64:0] grp_fu_107112_p2; +wire [5:0] grp_fu_99138_p2; +wire [33:0] grp_fu_107172_p0; +wire [31:0] grp_fu_107172_p1; +wire [64:0] grp_fu_107172_p2; +wire [31:0] add_ln223_17_fu_107223_p2; +wire [30:0] tmp_297_fu_107228_p4; +wire [27:0] tmp_298_fu_107244_p4; +wire [31:0] shl_ln231_47_fu_107260_p2; +wire [31:0] shl_ln231_52_fu_107266_p2; +wire [31:0] sub_ln231_9_fu_107272_p2; +wire [2:0] tmp_89_fu_107282_p4; +wire [31:0] shl_ln221_71_fu_107307_p2; +wire [31:0] shl_ln221_72_fu_107313_p2; +wire [31:0] add_ln216_45_fu_107329_p2; +wire [31:0] shl_ln216_16_fu_107301_p2; +wire [31:0] sub_ln221_27_fu_107319_p2; +wire [31:0] shl_ln221_79_fu_107349_p2; +wire [31:0] shl_ln221_80_fu_107355_p2; +wire [31:0] sub_ln221_32_fu_107361_p2; +wire [31:0] add_ln223_25_fu_107372_p2; +wire [30:0] tmp_325_fu_107381_p4; +wire [27:0] tmp_326_fu_107397_p4; +wire [0:0] icmp_ln223_97_fu_107391_p2; +wire [0:0] icmp_ln223_98_fu_107407_p2; +wire [3:0] trunc_ln223_13_fu_107377_p1; +wire [3:0] add_ln231_49_fu_107419_p2; +wire [5:0] shl_ln231_13_fu_107424_p3; +wire [10:0] zext_ln231_35_fu_107432_p1; +wire [31:0] add_ln221_32_fu_107367_p2; +wire [6:0] zext_ln231_36_fu_107436_p1; +wire [10:0] add_ln231_41_fu_107440_p2; +wire [3:0] trunc_ln1116_s_fu_107454_p4; +wire [24:0] sext_ln1116_13_fu_107464_p1; +wire [33:0] grp_fu_107539_p0; +wire [31:0] grp_fu_107539_p1; +wire [3:0] mul_ln1118_22_fu_107553_p0; +wire [7:0] mul_ln1118_22_fu_107553_p1; +wire [11:0] mul_ln1118_22_fu_107553_p2; +wire [64:0] grp_fu_107539_p2; +wire [5:0] grp_fu_99149_p2; +wire [31:0] or_ln208_9_fu_107618_p2; +wire [31:0] shl_ln221_99_fu_107636_p2; +wire [31:0] shl_ln221_100_fu_107642_p2; +wire [31:0] sub_ln221_42_fu_107648_p2; +wire [3:0] trunc_ln223_21_fu_107614_p1; +wire [31:0] add_ln223_36_fu_107665_p2; +wire [30:0] tmp_396_fu_107670_p4; +wire [27:0] tmp_397_fu_107686_p4; +wire [0:0] icmp_ln223_119_fu_107680_p2; +wire [0:0] icmp_ln223_120_fu_107696_p2; +wire [3:0] or_ln223_57_fu_107659_p2; +wire [3:0] add_ln231_70_fu_107708_p2; +wire [5:0] shl_ln231_33_fu_107713_p3; +wire [10:0] zext_ln231_51_fu_107721_p1; +wire [31:0] add_ln221_43_fu_107654_p2; +wire [6:0] zext_ln231_52_fu_107725_p1; +wire [10:0] add_ln231_65_fu_107729_p2; +wire [3:0] trunc_ln1116_20_fu_107743_p4; +wire [24:0] sext_ln1116_21_fu_107753_p1; +wire [31:0] or_ln206_6_fu_107825_p2; +wire [31:0] shl_ln221_107_fu_107843_p2; +wire [31:0] shl_ln221_108_fu_107849_p2; +wire [31:0] add_ln223_35_fu_107861_p2; +wire [30:0] tmp_394_fu_107866_p4; +wire [27:0] tmp_395_fu_107882_p4; +wire [31:0] shl_ln231_70_fu_107898_p2; +wire [31:0] shl_ln231_71_fu_107904_p2; +wire [31:0] add_ln216_69_fu_107916_p2; +wire [31:0] shl_ln216_21_fu_107837_p2; +wire [31:0] sub_ln221_46_fu_107855_p2; +wire [31:0] sub_ln231_14_fu_107910_p2; +wire [33:0] grp_fu_107949_p0; +wire [31:0] grp_fu_107949_p1; +wire [64:0] grp_fu_107949_p2; +wire [3:0] mul_ln1118_30_fu_108008_p0; +wire [7:0] mul_ln1118_30_fu_108008_p1; +wire [11:0] mul_ln1118_30_fu_108008_p2; +wire [33:0] grp_fu_108027_p0; +wire [31:0] grp_fu_108027_p1; +wire [64:0] grp_fu_108027_p2; +wire [5:0] grp_fu_99155_p2; +wire [33:0] grp_fu_108087_p0; +wire [31:0] grp_fu_108087_p1; +wire [64:0] grp_fu_108087_p2; +wire [31:0] shl_ln221_113_fu_108150_p2; +wire [31:0] shl_ln221_114_fu_108156_p2; +wire [31:0] sub_ln221_49_fu_108162_p2; +wire [31:0] add_ln223_42_fu_108173_p2; +wire [30:0] tmp_421_fu_108182_p4; +wire [27:0] tmp_422_fu_108198_p4; +wire [0:0] icmp_ln223_131_fu_108192_p2; +wire [0:0] icmp_ln223_132_fu_108208_p2; +wire [3:0] trunc_ln223_26_fu_108178_p1; +wire [3:0] add_ln231_81_fu_108220_p2; +wire [5:0] shl_ln231_38_fu_108225_p3; +wire [10:0] zext_ln231_61_fu_108233_p1; +wire [31:0] add_ln221_51_fu_108168_p2; +wire [6:0] zext_ln231_62_fu_108237_p1; +wire [10:0] add_ln231_80_fu_108241_p2; +wire [3:0] trunc_ln1116_25_fu_108255_p4; +wire [24:0] sext_ln1116_26_fu_108265_p1; +wire [33:0] grp_fu_108340_p0; +wire [31:0] grp_fu_108340_p1; +wire [3:0] mul_ln1118_35_fu_108354_p0; +wire [7:0] mul_ln1118_35_fu_108354_p1; +wire [11:0] mul_ln1118_35_fu_108354_p2; +wire [64:0] grp_fu_108340_p2; +wire [5:0] grp_fu_99166_p2; +wire [31:0] or_ln208_14_fu_108419_p2; +wire [31:0] shl_ln221_123_fu_108437_p2; +wire [31:0] shl_ln221_124_fu_108443_p2; +wire [31:0] sub_ln221_54_fu_108449_p2; +wire [3:0] trunc_ln223_30_fu_108415_p1; +wire [31:0] add_ln223_46_fu_108466_p2; +wire [30:0] tmp_454_fu_108471_p4; +wire [27:0] tmp_455_fu_108487_p4; +wire [0:0] icmp_ln223_139_fu_108481_p2; +wire [0:0] icmp_ln223_140_fu_108497_p2; +wire [3:0] or_ln223_62_fu_108460_p2; +wire [3:0] add_ln231_90_fu_108509_p2; +wire [5:0] shl_ln231_48_fu_108514_p3; +wire [10:0] zext_ln231_69_fu_108522_p1; +wire [31:0] add_ln221_56_fu_108455_p2; +wire [6:0] zext_ln231_70_fu_108526_p1; +wire [10:0] add_ln231_86_fu_108530_p2; +wire [3:0] trunc_ln1116_29_fu_108544_p4; +wire [24:0] sext_ln1116_30_fu_108554_p1; +wire [33:0] grp_fu_108635_p0; +wire [31:0] grp_fu_108635_p1; +wire [64:0] grp_fu_108635_p2; +wire [3:0] mul_ln1118_39_fu_108694_p0; +wire [7:0] mul_ln1118_39_fu_108694_p1; +wire [11:0] mul_ln1118_39_fu_108694_p2; +wire [33:0] grp_fu_108713_p0; +wire [31:0] grp_fu_108713_p1; +wire [64:0] grp_fu_108713_p2; +wire [5:0] grp_fu_99172_p2; +wire [33:0] grp_fu_108773_p0; +wire [31:0] grp_fu_108773_p1; +wire [64:0] grp_fu_108773_p2; +wire [3:0] mul_ln203_1_fu_108838_p0; +wire [14:0] zext_ln216_2_fu_108872_p1; +wire [14:0] add_ln216_2_fu_108876_p2; +wire [18:0] zext_ln216_4_fu_108881_p1; +wire [3:0] mul_ln203_3_fu_108904_p0; +wire [5:0] shl_ln221_4_fu_108924_p3; +wire [3:0] shl_ln221_5_fu_108936_p3; +wire [6:0] zext_ln221_4_fu_108932_p1; +wire [6:0] zext_ln221_5_fu_108944_p1; +wire [6:0] sub_ln221_2_fu_108948_p2; +wire [6:0] add_ln221_5_fu_108954_p2; +wire [18:0] grp_fu_131374_p3; +wire [3:0] or_ln231_3_fu_108974_p3; +wire [7:0] or_ln231_2_fu_108966_p3; +wire [31:0] add_ln223_1_fu_108990_p2; +wire [30:0] tmp_243_fu_108995_p4; +wire [27:0] tmp_244_fu_109011_p4; +wire [0:0] icmp_ln223_49_fu_109005_p2; +wire [0:0] icmp_ln223_50_fu_109021_p2; +wire [31:0] shl_ln231_17_fu_109033_p2; +wire [31:0] shl_ln231_18_fu_109039_p2; +wire [31:0] sub_ln231_1_fu_109045_p2; +wire [31:0] shl_ln221_29_fu_109065_p2; +wire [31:0] shl_ln221_30_fu_109071_p2; +wire [31:0] add_ln216_18_fu_109083_p2; +wire [31:0] shl_ln216_8_fu_109059_p2; +wire [31:0] sub_ln221_5_fu_109077_p2; +wire [31:0] shl_ln221_33_fu_109107_p2; +wire [31:0] shl_ln221_34_fu_109113_p2; +wire [31:0] sub_ln221_8_fu_109119_p2; +wire [31:0] add_ln223_5_fu_109130_p2; +wire [30:0] tmp_252_fu_109139_p4; +wire [27:0] tmp_253_fu_109155_p4; +wire [0:0] icmp_ln223_57_fu_109149_p2; +wire [0:0] icmp_ln223_58_fu_109165_p2; +wire [3:0] trunc_ln223_1_fu_109135_p1; +wire [3:0] add_ln231_10_fu_109177_p2; +wire [5:0] shl_ln231_9_fu_109183_p3; +wire [10:0] zext_ln231_7_fu_109191_p1; +wire [31:0] add_ln221_7_fu_109125_p2; +wire [6:0] zext_ln231_8_fu_109195_p1; +wire [10:0] add_ln231_5_fu_109199_p2; +wire [3:0] trunc_ln1116_1_fu_109213_p4; +wire [24:0] sext_ln1116_1_fu_109223_p1; +wire [33:0] grp_fu_109299_p0; +wire [31:0] grp_fu_109299_p1; +wire [3:0] mul_ln1118_10_fu_109313_p0; +wire [7:0] mul_ln1118_10_fu_109313_p1; +wire [11:0] mul_ln1118_10_fu_109313_p2; +wire [64:0] grp_fu_109299_p2; +wire [5:0] grp_fu_99183_p2; +wire [31:0] or_ln208_1_fu_109378_p2; +wire [31:0] shl_ln221_49_fu_109396_p2; +wire [31:0] shl_ln221_50_fu_109402_p2; +wire [31:0] sub_ln221_15_fu_109408_p2; +wire [3:0] trunc_ln223_5_fu_109374_p1; +wire [31:0] add_ln223_12_fu_109425_p2; +wire [30:0] tmp_285_fu_109430_p4; +wire [27:0] tmp_286_fu_109446_p4; +wire [0:0] icmp_ln223_71_fu_109440_p2; +wire [0:0] icmp_ln223_72_fu_109456_p2; +wire [3:0] or_ln223_49_fu_109419_p2; +wire [3:0] add_ln231_30_fu_109468_p2; +wire [5:0] shl_ln231_3_fu_109474_p3; +wire [10:0] zext_ln231_18_fu_109482_p1; +wire [31:0] add_ln221_15_fu_109414_p2; +wire [6:0] zext_ln231_19_fu_109486_p1; +wire [10:0] add_ln231_17_fu_109490_p2; +wire [3:0] trunc_ln1116_5_fu_109504_p4; +wire [24:0] sext_ln1116_5_fu_109514_p1; +wire [31:0] or_ln206_1_fu_109587_p2; +wire [31:0] shl_ln221_59_fu_109605_p2; +wire [31:0] shl_ln221_60_fu_109611_p2; +wire [31:0] add_ln223_11_fu_109623_p2; +wire [30:0] tmp_283_fu_109628_p4; +wire [27:0] tmp_284_fu_109644_p4; +wire [0:0] icmp_ln223_69_fu_109638_p2; +wire [0:0] icmp_ln223_70_fu_109654_p2; +wire [31:0] shl_ln231_31_fu_109666_p2; +wire [31:0] shl_ln231_39_fu_109672_p2; +wire [31:0] add_ln216_34_fu_109684_p2; +wire [31:0] shl_ln216_13_fu_109599_p2; +wire [31:0] sub_ln221_20_fu_109617_p2; +wire [31:0] sub_ln231_6_fu_109678_p2; +wire [1:0] or_ln204_1_fu_109708_p2; +wire [5:0] shl_ln221_9_fu_109717_p3; +wire [3:0] shl_ln221_10_fu_109729_p3; +wire [6:0] zext_ln221_16_fu_109725_p1; +wire [6:0] zext_ln221_17_fu_109737_p1; +wire [6:0] sub_ln221_19_fu_109741_p2; +wire [6:0] add_ln221_27_fu_109747_p2; +wire [18:0] grp_fu_131382_p3; +wire [2:0] or_ln231_19_fu_109759_p2; +wire [3:0] or_ln231_13_fu_109773_p3; +wire [7:0] or_ln231_12_fu_109765_p3; +wire [33:0] grp_fu_109792_p0; +wire [31:0] grp_fu_109792_p1; +wire [64:0] grp_fu_109792_p2; +wire [3:0] mul_ln1118_14_fu_109851_p0; +wire [7:0] mul_ln1118_14_fu_109851_p1; +wire [11:0] mul_ln1118_14_fu_109851_p2; +wire [33:0] grp_fu_109870_p0; +wire [31:0] grp_fu_109870_p1; +wire [64:0] grp_fu_109870_p2; +wire [5:0] grp_fu_99189_p2; +wire [33:0] grp_fu_109930_p0; +wire [31:0] grp_fu_109930_p1; +wire [64:0] grp_fu_109930_p2; +wire [31:0] shl_ln221_69_fu_109989_p2; +wire [31:0] shl_ln221_70_fu_109995_p2; +wire [31:0] sub_ln221_26_fu_110001_p2; +wire [31:0] add_ln223_21_fu_110012_p2; +wire [30:0] tmp_312_fu_110021_p4; +wire [27:0] tmp_313_fu_110037_p4; +wire [0:0] icmp_ln223_89_fu_110031_p2; +wire [0:0] icmp_ln223_90_fu_110047_p2; +wire [3:0] trunc_ln223_10_fu_110017_p1; +wire [3:0] add_ln231_45_fu_110059_p2; +wire [5:0] shl_ln231_10_fu_110065_p3; +wire [10:0] zext_ln231_29_fu_110073_p1; +wire [31:0] add_ln221_24_fu_110007_p2; +wire [6:0] zext_ln231_30_fu_110077_p1; +wire [10:0] add_ln231_32_fu_110081_p2; +wire [3:0] trunc_ln1116_10_fu_110095_p4; +wire [24:0] sext_ln1116_10_fu_110105_p1; +wire [33:0] grp_fu_110182_p0; +wire [31:0] grp_fu_110182_p1; +wire [3:0] mul_ln1118_19_fu_110196_p0; +wire [7:0] mul_ln1118_19_fu_110196_p1; +wire [11:0] mul_ln1118_19_fu_110196_p2; +wire [64:0] grp_fu_110182_p2; +wire [5:0] grp_fu_99200_p2; +wire [31:0] or_ln208_6_fu_110261_p2; +wire [31:0] shl_ln221_91_fu_110279_p2; +wire [31:0] shl_ln221_92_fu_110285_p2; +wire [31:0] sub_ln221_38_fu_110291_p2; +wire [3:0] trunc_ln223_18_fu_110257_p1; +wire [31:0] add_ln223_31_fu_110308_p2; +wire [30:0] tmp_383_fu_110313_p4; +wire [27:0] tmp_384_fu_110329_p4; +wire [0:0] icmp_ln223_109_fu_110323_p2; +wire [0:0] icmp_ln223_110_fu_110339_p2; +wire [3:0] or_ln223_54_fu_110302_p2; +wire [3:0] add_ln231_63_fu_110351_p2; +wire [5:0] shl_ln231_26_fu_110357_p3; +wire [10:0] zext_ln231_45_fu_110365_p1; +wire [31:0] add_ln221_40_fu_110297_p2; +wire [6:0] zext_ln231_46_fu_110369_p1; +wire [10:0] add_ln231_56_fu_110373_p2; +wire [3:0] trunc_ln1116_17_fu_110387_p4; +wire [24:0] sext_ln1116_18_fu_110397_p1; +wire [33:0] grp_fu_110480_p0; +wire [31:0] grp_fu_110480_p1; +wire [64:0] grp_fu_110480_p2; +wire [3:0] mul_ln1118_27_fu_110539_p0; +wire [7:0] mul_ln1118_27_fu_110539_p1; +wire [11:0] mul_ln1118_27_fu_110539_p2; +wire [33:0] grp_fu_110558_p0; +wire [31:0] grp_fu_110558_p1; +wire [64:0] grp_fu_110558_p2; +wire [5:0] grp_fu_99206_p2; +wire [33:0] grp_fu_110618_p0; +wire [31:0] grp_fu_110618_p1; +wire [64:0] grp_fu_110618_p2; +wire [31:0] add_ln223_16_fu_110669_p2; +wire [30:0] tmp_294_fu_110674_p4; +wire [27:0] tmp_295_fu_110690_p4; +wire [0:0] icmp_ln223_79_fu_110684_p2; +wire [0:0] icmp_ln223_80_fu_110700_p2; +wire [31:0] shl_ln231_44_fu_110712_p2; +wire [31:0] shl_ln231_46_fu_110718_p2; +wire [31:0] sub_ln231_8_fu_110724_p2; +wire [31:0] shl_ln221_67_fu_110744_p2; +wire [31:0] shl_ln221_68_fu_110750_p2; +wire [31:0] add_ln216_43_fu_110762_p2; +wire [31:0] shl_ln216_15_fu_110738_p2; +wire [31:0] sub_ln221_25_fu_110756_p2; +wire [31:0] shl_ln221_77_fu_110786_p2; +wire [31:0] shl_ln221_78_fu_110792_p2; +wire [31:0] sub_ln221_31_fu_110798_p2; +wire [31:0] add_ln223_24_fu_110809_p2; +wire [30:0] tmp_321_fu_110818_p4; +wire [27:0] tmp_322_fu_110834_p4; +wire [0:0] icmp_ln223_95_fu_110828_p2; +wire [0:0] icmp_ln223_96_fu_110844_p2; +wire [3:0] trunc_ln223_12_fu_110814_p1; +wire [3:0] add_ln231_48_fu_110856_p2; +wire [5:0] shl_ln231_12_fu_110862_p3; +wire [10:0] zext_ln231_33_fu_110870_p1; +wire [31:0] add_ln221_29_fu_110804_p2; +wire [6:0] zext_ln231_34_fu_110874_p1; +wire [10:0] add_ln231_38_fu_110878_p2; +wire [3:0] trunc_ln1116_12_fu_110892_p4; +wire [24:0] sext_ln1116_12_fu_110902_p1; +wire [33:0] grp_fu_110977_p0; +wire [31:0] grp_fu_110977_p1; +wire [3:0] mul_ln1118_21_fu_110991_p0; +wire [7:0] mul_ln1118_21_fu_110991_p1; +wire [11:0] mul_ln1118_21_fu_110991_p2; +wire [64:0] grp_fu_110977_p2; +wire [5:0] grp_fu_99217_p2; +wire [31:0] or_ln208_8_fu_111056_p2; +wire [31:0] shl_ln221_97_fu_111074_p2; +wire [31:0] shl_ln221_98_fu_111080_p2; +wire [31:0] sub_ln221_41_fu_111086_p2; +wire [3:0] trunc_ln223_20_fu_111052_p1; +wire [31:0] add_ln223_34_fu_111103_p2; +wire [30:0] tmp_391_fu_111108_p4; +wire [27:0] tmp_392_fu_111124_p4; +wire [0:0] icmp_ln223_115_fu_111118_p2; +wire [0:0] icmp_ln223_116_fu_111134_p2; +wire [3:0] or_ln223_56_fu_111097_p2; +wire [3:0] add_ln231_69_fu_111146_p2; +wire [5:0] shl_ln231_32_fu_111152_p3; +wire [10:0] zext_ln231_49_fu_111160_p1; +wire [31:0] add_ln221_42_fu_111092_p2; +wire [6:0] zext_ln231_50_fu_111164_p1; +wire [10:0] add_ln231_62_fu_111168_p2; +wire [3:0] trunc_ln1116_19_fu_111182_p4; +wire [24:0] sext_ln1116_20_fu_111192_p1; +wire [31:0] or_ln206_5_fu_111264_p2; +wire [31:0] shl_ln221_105_fu_111282_p2; +wire [31:0] shl_ln221_106_fu_111288_p2; +wire [31:0] add_ln223_33_fu_111300_p2; +wire [30:0] tmp_389_fu_111305_p4; +wire [27:0] tmp_390_fu_111321_p4; +wire [0:0] icmp_ln223_113_fu_111315_p2; +wire [0:0] icmp_ln223_114_fu_111331_p2; +wire [31:0] shl_ln231_68_fu_111343_p2; +wire [31:0] shl_ln231_69_fu_111349_p2; +wire [31:0] add_ln216_66_fu_111361_p2; +wire [31:0] shl_ln216_20_fu_111276_p2; +wire [31:0] sub_ln221_45_fu_111294_p2; +wire [31:0] sub_ln231_13_fu_111355_p2; +wire [33:0] grp_fu_111394_p0; +wire [31:0] grp_fu_111394_p1; +wire [64:0] grp_fu_111394_p2; +wire [3:0] mul_ln1118_29_fu_111453_p0; +wire [7:0] mul_ln1118_29_fu_111453_p1; +wire [11:0] mul_ln1118_29_fu_111453_p2; +wire [33:0] grp_fu_111472_p0; +wire [31:0] grp_fu_111472_p1; +wire [64:0] grp_fu_111472_p2; +wire [5:0] grp_fu_99223_p2; +wire [33:0] grp_fu_111532_p0; +wire [31:0] grp_fu_111532_p1; +wire [64:0] grp_fu_111532_p2; +wire [31:0] shl_ln221_111_fu_111591_p2; +wire [31:0] shl_ln221_112_fu_111597_p2; +wire [31:0] sub_ln221_48_fu_111603_p2; +wire [31:0] add_ln223_41_fu_111614_p2; +wire [30:0] tmp_418_fu_111623_p4; +wire [27:0] tmp_419_fu_111639_p4; +wire [0:0] icmp_ln223_129_fu_111633_p2; +wire [0:0] icmp_ln223_130_fu_111649_p2; +wire [3:0] trunc_ln223_25_fu_111619_p1; +wire [3:0] add_ln231_79_fu_111661_p2; +wire [5:0] shl_ln231_37_fu_111667_p3; +wire [10:0] zext_ln231_59_fu_111675_p1; +wire [31:0] add_ln221_49_fu_111609_p2; +wire [6:0] zext_ln231_60_fu_111679_p1; +wire [10:0] add_ln231_77_fu_111683_p2; +wire [3:0] trunc_ln1116_24_fu_111697_p4; +wire [24:0] sext_ln1116_25_fu_111707_p1; +wire [33:0] grp_fu_111782_p0; +wire [31:0] grp_fu_111782_p1; +wire [3:0] mul_ln1118_34_fu_111796_p0; +wire [7:0] mul_ln1118_34_fu_111796_p1; +wire [11:0] mul_ln1118_34_fu_111796_p2; +wire [64:0] grp_fu_111782_p2; +wire [5:0] grp_fu_99234_p2; +wire [31:0] or_ln208_13_fu_111861_p2; +wire [31:0] shl_ln221_121_fu_111879_p2; +wire [31:0] shl_ln221_122_fu_111885_p2; +wire [31:0] sub_ln221_53_fu_111891_p2; +wire [3:0] trunc_ln223_29_fu_111857_p1; +wire [31:0] add_ln223_45_fu_111908_p2; +wire [30:0] tmp_452_fu_111913_p4; +wire [27:0] tmp_453_fu_111929_p4; +wire [0:0] icmp_ln223_137_fu_111923_p2; +wire [0:0] icmp_ln223_138_fu_111939_p2; +wire [3:0] or_ln223_61_fu_111902_p2; +wire [3:0] add_ln231_89_fu_111951_p2; +wire [5:0] shl_ln231_45_fu_111957_p3; +wire [10:0] zext_ln231_67_fu_111965_p1; +wire [31:0] add_ln221_55_fu_111897_p2; +wire [6:0] zext_ln231_68_fu_111969_p1; +wire [10:0] add_ln231_85_fu_111973_p2; +wire [3:0] trunc_ln1116_28_fu_111987_p4; +wire [24:0] sext_ln1116_29_fu_111997_p1; +wire [33:0] grp_fu_112078_p0; +wire [31:0] grp_fu_112078_p1; +wire [64:0] grp_fu_112078_p2; +wire [3:0] mul_ln1118_38_fu_112137_p0; +wire [7:0] mul_ln1118_38_fu_112137_p1; +wire [11:0] mul_ln1118_38_fu_112137_p2; +wire [33:0] grp_fu_112156_p0; +wire [31:0] grp_fu_112156_p1; +wire [64:0] grp_fu_112156_p2; +wire [5:0] grp_fu_99240_p2; +wire [33:0] grp_fu_112216_p0; +wire [31:0] grp_fu_112216_p1; +wire [64:0] grp_fu_112216_p2; +wire [14:0] zext_ln216_14_fu_112289_p1; +wire [14:0] add_ln216_13_fu_112293_p2; +wire [18:0] zext_ln216_15_fu_112298_p1; +wire [5:0] shl_ln221_s_fu_112327_p3; +wire [3:0] shl_ln221_2_fu_112339_p3; +wire [6:0] zext_ln221_10_fu_112335_p1; +wire [6:0] zext_ln221_11_fu_112347_p1; +wire [6:0] sub_ln221_7_fu_112351_p2; +wire [6:0] add_ln221_11_fu_112357_p2; +wire [18:0] grp_fu_131390_p3; +wire [3:0] or_ln231_7_fu_112377_p3; +wire [7:0] or_ln231_6_fu_112369_p3; +wire [31:0] add_ln223_4_fu_112393_p2; +wire [30:0] tmp_250_fu_112398_p4; +wire [27:0] tmp_251_fu_112414_p4; +wire [0:0] icmp_ln223_55_fu_112408_p2; +wire [0:0] icmp_ln223_56_fu_112424_p2; +wire [31:0] shl_ln231_21_fu_112436_p2; +wire [31:0] shl_ln231_23_fu_112442_p2; +wire [31:0] sub_ln231_3_fu_112448_p2; +wire [31:0] shl_ln221_39_fu_112468_p2; +wire [31:0] shl_ln221_40_fu_112474_p2; +wire [31:0] add_ln216_21_fu_112486_p2; +wire [31:0] shl_ln216_10_fu_112462_p2; +wire [31:0] sub_ln221_10_fu_112480_p2; +wire [31:0] shl_ln221_43_fu_112510_p2; +wire [31:0] shl_ln221_44_fu_112516_p2; +wire [31:0] sub_ln221_11_fu_112522_p2; +wire [31:0] add_ln223_7_fu_112533_p2; +wire [30:0] tmp_259_fu_112542_p4; +wire [27:0] tmp_260_fu_112558_p4; +wire [0:0] icmp_ln223_61_fu_112552_p2; +wire [0:0] icmp_ln223_62_fu_112568_p2; +wire [3:0] trunc_ln223_3_fu_112538_p1; +wire [3:0] add_ln231_13_fu_112580_p2; +wire [5:0] shl_ln231_1_fu_112585_p3; +wire [10:0] zext_ln231_11_fu_112593_p1; +wire [31:0] add_ln221_13_fu_112528_p2; +wire [6:0] zext_ln231_12_fu_112597_p1; +wire [10:0] add_ln231_11_fu_112601_p2; +wire [3:0] trunc_ln1116_3_fu_112615_p4; +wire [24:0] sext_ln1116_3_fu_112625_p1; +wire [33:0] grp_fu_112701_p0; +wire [31:0] grp_fu_112701_p1; +wire [3:0] mul_ln1118_12_fu_112715_p0; +wire [7:0] mul_ln1118_12_fu_112715_p1; +wire [11:0] mul_ln1118_12_fu_112715_p2; +wire [64:0] grp_fu_112701_p2; +wire [5:0] grp_fu_99251_p2; +wire [31:0] or_ln208_3_fu_112780_p2; +wire [31:0] shl_ln221_65_fu_112798_p2; +wire [31:0] shl_ln221_66_fu_112804_p2; +wire [31:0] sub_ln221_24_fu_112810_p2; +wire [3:0] trunc_ln223_7_fu_112776_p1; +wire [31:0] add_ln223_20_fu_112827_p2; +wire [30:0] tmp_310_fu_112832_p4; +wire [27:0] tmp_311_fu_112848_p4; +wire [0:0] icmp_ln223_87_fu_112842_p2; +wire [0:0] icmp_ln223_88_fu_112858_p2; +wire [3:0] or_ln223_51_fu_112821_p2; +wire [3:0] add_ln231_43_fu_112870_p2; +wire [5:0] shl_ln231_8_fu_112875_p3; +wire [10:0] zext_ln231_27_fu_112883_p1; +wire [31:0] add_ln221_22_fu_112816_p2; +wire [6:0] zext_ln231_28_fu_112887_p1; +wire [10:0] add_ln231_29_fu_112891_p2; +wire [3:0] trunc_ln1116_9_fu_112905_p4; +wire [24:0] sext_ln1116_9_fu_112915_p1; +wire [31:0] or_ln206_3_fu_112988_p2; +wire [31:0] shl_ln221_75_fu_113006_p2; +wire [31:0] shl_ln221_76_fu_113012_p2; +wire [31:0] add_ln223_19_fu_113024_p2; +wire [30:0] tmp_308_fu_113029_p4; +wire [27:0] tmp_309_fu_113045_p4; +wire [31:0] shl_ln231_53_fu_113061_p2; +wire [31:0] shl_ln231_63_fu_113067_p2; +wire [31:0] add_ln216_50_fu_113079_p2; +wire [31:0] shl_ln216_17_fu_113000_p2; +wire [31:0] sub_ln221_30_fu_113018_p2; +wire [31:0] sub_ln231_10_fu_113073_p2; +wire [1:0] or_ln204_3_fu_113103_p2; +wire [5:0] shl_ln221_13_fu_113112_p3; +wire [3:0] shl_ln221_14_fu_113124_p3; +wire [6:0] zext_ln221_22_fu_113120_p1; +wire [6:0] zext_ln221_23_fu_113132_p1; +wire [6:0] sub_ln221_29_fu_113136_p2; +wire [6:0] add_ln221_35_fu_113142_p2; +wire [18:0] grp_fu_131398_p3; +wire [2:0] or_ln231_21_fu_113154_p2; +wire [3:0] or_ln231_18_fu_113168_p3; +wire [7:0] or_ln231_17_fu_113160_p3; +wire [33:0] grp_fu_113187_p0; +wire [31:0] grp_fu_113187_p1; +wire [64:0] grp_fu_113187_p2; +wire [3:0] mul_ln1118_18_fu_113246_p0; +wire [7:0] mul_ln1118_18_fu_113246_p1; +wire [11:0] mul_ln1118_18_fu_113246_p2; +wire [33:0] grp_fu_113265_p0; +wire [31:0] grp_fu_113265_p1; +wire [64:0] grp_fu_113265_p2; +wire [5:0] grp_fu_99257_p2; +wire [33:0] grp_fu_113325_p0; +wire [31:0] grp_fu_113325_p1; +wire [64:0] grp_fu_113325_p2; +wire [31:0] shl_ln221_83_fu_113388_p2; +wire [31:0] shl_ln221_84_fu_113394_p2; +wire [31:0] sub_ln221_34_fu_113400_p2; +wire [31:0] add_ln223_26_fu_113411_p2; +wire [30:0] tmp_334_fu_113420_p4; +wire [27:0] tmp_335_fu_113436_p4; +wire [0:0] icmp_ln223_99_fu_113430_p2; +wire [0:0] icmp_ln223_100_fu_113446_p2; +wire [3:0] trunc_ln223_14_fu_113416_p1; +wire [3:0] add_ln231_51_fu_113458_p2; +wire [5:0] shl_ln231_14_fu_113463_p3; +wire [10:0] zext_ln231_37_fu_113471_p1; +wire [31:0] add_ln221_34_fu_113406_p2; +wire [6:0] zext_ln231_38_fu_113475_p1; +wire [10:0] add_ln231_44_fu_113479_p2; +wire [3:0] trunc_ln1116_13_fu_113493_p4; +wire [24:0] sext_ln1116_14_fu_113503_p1; +wire [33:0] grp_fu_113580_p0; +wire [31:0] grp_fu_113580_p1; +wire [3:0] mul_ln1118_23_fu_113594_p0; +wire [7:0] mul_ln1118_23_fu_113594_p1; +wire [11:0] mul_ln1118_23_fu_113594_p2; +wire [64:0] grp_fu_113580_p2; +wire [5:0] grp_fu_99268_p2; +wire [31:0] or_ln208_10_fu_113659_p2; +wire [31:0] shl_ln221_103_fu_113677_p2; +wire [31:0] shl_ln221_104_fu_113683_p2; +wire [31:0] sub_ln221_44_fu_113689_p2; +wire [3:0] trunc_ln223_22_fu_113655_p1; +wire [31:0] add_ln223_38_fu_113706_p2; +wire [30:0] tmp_406_fu_113711_p4; +wire [27:0] tmp_407_fu_113727_p4; +wire [0:0] icmp_ln223_123_fu_113721_p2; +wire [0:0] icmp_ln223_124_fu_113737_p2; +wire [3:0] or_ln223_58_fu_113700_p2; +wire [3:0] add_ln231_76_fu_113749_p2; +wire [5:0] shl_ln231_35_fu_113754_p3; +wire [10:0] zext_ln231_55_fu_113762_p1; +wire [31:0] add_ln221_46_fu_113695_p2; +wire [6:0] zext_ln231_56_fu_113766_p1; +wire [10:0] add_ln231_71_fu_113770_p2; +wire [3:0] trunc_ln1116_22_fu_113784_p4; +wire [24:0] sext_ln1116_23_fu_113794_p1; +wire [33:0] grp_fu_113877_p0; +wire [31:0] grp_fu_113877_p1; +wire [64:0] grp_fu_113877_p2; +wire [3:0] mul_ln1118_32_fu_113936_p0; +wire [7:0] mul_ln1118_32_fu_113936_p1; +wire [11:0] mul_ln1118_32_fu_113936_p2; +wire [33:0] grp_fu_113955_p0; +wire [31:0] grp_fu_113955_p1; +wire [64:0] grp_fu_113955_p2; +wire [5:0] grp_fu_99274_p2; +wire [33:0] grp_fu_114015_p0; +wire [31:0] grp_fu_114015_p1; +wire [64:0] grp_fu_114015_p2; +wire [31:0] add_ln223_23_fu_114066_p2; +wire [30:0] tmp_318_fu_114071_p4; +wire [27:0] tmp_319_fu_114087_p4; +wire [0:0] icmp_ln223_93_fu_114081_p2; +wire [0:0] icmp_ln223_94_fu_114097_p2; +wire [31:0] shl_ln231_64_fu_114109_p2; +wire [31:0] shl_ln231_65_fu_114115_p2; +wire [31:0] sub_ln231_11_fu_114121_p2; +wire [31:0] shl_ln221_81_fu_114141_p2; +wire [31:0] shl_ln221_82_fu_114147_p2; +wire [31:0] add_ln216_53_fu_114159_p2; +wire [31:0] shl_ln216_18_fu_114135_p2; +wire [31:0] sub_ln221_33_fu_114153_p2; +wire [31:0] shl_ln221_85_fu_114183_p2; +wire [31:0] shl_ln221_86_fu_114189_p2; +wire [31:0] sub_ln221_35_fu_114195_p2; +wire [31:0] add_ln223_27_fu_114206_p2; +wire [30:0] tmp_343_fu_114215_p4; +wire [27:0] tmp_344_fu_114231_p4; +wire [0:0] icmp_ln223_101_fu_114225_p2; +wire [0:0] icmp_ln223_102_fu_114241_p2; +wire [3:0] trunc_ln223_15_fu_114211_p1; +wire [3:0] add_ln231_52_fu_114253_p2; +wire [5:0] shl_ln231_15_fu_114258_p3; +wire [10:0] zext_ln231_39_fu_114266_p1; +wire [31:0] add_ln221_37_fu_114201_p2; +wire [6:0] zext_ln231_40_fu_114270_p1; +wire [10:0] add_ln231_47_fu_114274_p2; +wire [3:0] trunc_ln1116_14_fu_114288_p4; +wire [24:0] sext_ln1116_15_fu_114298_p1; +wire [33:0] grp_fu_114373_p0; +wire [31:0] grp_fu_114373_p1; +wire [3:0] mul_ln1118_24_fu_114387_p0; +wire [7:0] mul_ln1118_24_fu_114387_p1; +wire [11:0] mul_ln1118_24_fu_114387_p2; +wire [64:0] grp_fu_114373_p2; +wire [5:0] grp_fu_99285_p2; +wire [31:0] or_ln208_11_fu_114452_p2; +wire [31:0] shl_ln221_109_fu_114470_p2; +wire [31:0] shl_ln221_110_fu_114476_p2; +wire [31:0] sub_ln221_47_fu_114482_p2; +wire [3:0] trunc_ln223_23_fu_114448_p1; +wire [31:0] add_ln223_40_fu_114499_p2; +wire [30:0] tmp_415_fu_114504_p4; +wire [27:0] tmp_416_fu_114520_p4; +wire [0:0] icmp_ln223_127_fu_114514_p2; +wire [0:0] icmp_ln223_128_fu_114530_p2; +wire [3:0] or_ln223_59_fu_114493_p2; +wire [3:0] add_ln231_78_fu_114542_p2; +wire [5:0] shl_ln231_36_fu_114547_p3; +wire [10:0] zext_ln231_57_fu_114555_p1; +wire [31:0] add_ln221_47_fu_114488_p2; +wire [6:0] zext_ln231_58_fu_114559_p1; +wire [10:0] add_ln231_74_fu_114563_p2; +wire [3:0] trunc_ln1116_23_fu_114577_p4; +wire [24:0] sext_ln1116_24_fu_114587_p1; +wire [31:0] or_ln206_7_fu_114659_p2; +wire [31:0] shl_ln221_115_fu_114677_p2; +wire [31:0] shl_ln221_116_fu_114683_p2; +wire [31:0] add_ln223_39_fu_114695_p2; +wire [30:0] tmp_413_fu_114700_p4; +wire [27:0] tmp_414_fu_114716_p4; +wire [31:0] shl_ln231_72_fu_114732_p2; +wire [31:0] shl_ln231_73_fu_114738_p2; +wire [31:0] add_ln216_73_fu_114750_p2; +wire [31:0] shl_ln216_22_fu_114671_p2; +wire [31:0] sub_ln221_50_fu_114689_p2; +wire [31:0] sub_ln231_15_fu_114744_p2; +wire [33:0] grp_fu_114783_p0; +wire [31:0] grp_fu_114783_p1; +wire [64:0] grp_fu_114783_p2; +wire [3:0] mul_ln1118_33_fu_114842_p0; +wire [7:0] mul_ln1118_33_fu_114842_p1; +wire [11:0] mul_ln1118_33_fu_114842_p2; +wire [33:0] grp_fu_114861_p0; +wire [31:0] grp_fu_114861_p1; +wire [64:0] grp_fu_114861_p2; +wire [5:0] grp_fu_99291_p2; +wire [33:0] grp_fu_114921_p0; +wire [31:0] grp_fu_114921_p1; +wire [64:0] grp_fu_114921_p2; +wire [31:0] shl_ln221_117_fu_114984_p2; +wire [31:0] shl_ln221_118_fu_114990_p2; +wire [31:0] sub_ln221_51_fu_114996_p2; +wire [31:0] add_ln223_43_fu_115007_p2; +wire [30:0] tmp_436_fu_115016_p4; +wire [27:0] tmp_437_fu_115032_p4; +wire [0:0] icmp_ln223_133_fu_115026_p2; +wire [0:0] icmp_ln223_134_fu_115042_p2; +wire [3:0] trunc_ln223_27_fu_115012_p1; +wire [3:0] add_ln231_82_fu_115054_p2; +wire [5:0] shl_ln231_41_fu_115059_p3; +wire [10:0] zext_ln231_63_fu_115067_p1; +wire [31:0] add_ln221_53_fu_115002_p2; +wire [6:0] zext_ln231_64_fu_115071_p1; +wire [10:0] add_ln231_83_fu_115075_p2; +wire [3:0] trunc_ln1116_26_fu_115089_p4; +wire [24:0] sext_ln1116_27_fu_115099_p1; +wire [33:0] grp_fu_115174_p0; +wire [31:0] grp_fu_115174_p1; +wire [3:0] mul_ln1118_36_fu_115188_p0; +wire [7:0] mul_ln1118_36_fu_115188_p1; +wire [11:0] mul_ln1118_36_fu_115188_p2; +wire [64:0] grp_fu_115174_p2; +wire [5:0] grp_fu_99302_p2; +wire [31:0] or_ln208_15_fu_115253_p2; +wire [31:0] shl_ln221_125_fu_115271_p2; +wire [31:0] shl_ln221_126_fu_115277_p2; +wire [31:0] sub_ln221_55_fu_115283_p2; +wire [3:0] trunc_ln223_31_fu_115249_p1; +wire [31:0] add_ln223_47_fu_115300_p2; +wire [30:0] tmp_459_fu_115305_p4; +wire [27:0] tmp_460_fu_115321_p4; +wire [0:0] icmp_ln223_141_fu_115315_p2; +wire [0:0] icmp_ln223_142_fu_115331_p2; +wire [3:0] or_ln223_63_fu_115294_p2; +wire [3:0] add_ln231_91_fu_115343_p2; +wire [5:0] shl_ln231_49_fu_115348_p3; +wire [10:0] zext_ln231_71_fu_115356_p1; +wire [31:0] add_ln221_57_fu_115289_p2; +wire [6:0] zext_ln231_72_fu_115360_p1; +wire [10:0] add_ln231_87_fu_115364_p2; +wire [3:0] trunc_ln1116_30_fu_115378_p4; +wire [24:0] sext_ln1116_31_fu_115388_p1; +wire [33:0] grp_fu_115469_p0; +wire [31:0] grp_fu_115469_p1; +wire [64:0] grp_fu_115469_p2; +wire [3:0] mul_ln1118_40_fu_115528_p0; +wire [7:0] mul_ln1118_40_fu_115528_p1; +wire [11:0] mul_ln1118_40_fu_115528_p2; +wire [33:0] grp_fu_115547_p0; +wire [31:0] grp_fu_115547_p1; +wire [64:0] grp_fu_115547_p2; +wire [5:0] grp_fu_99308_p2; +wire [33:0] grp_fu_115607_p0; +wire [31:0] grp_fu_115607_p1; +wire [64:0] grp_fu_115607_p2; +wire [3:0] mul_ln250_fu_115668_p0; +wire [7:0] shl_ln_fu_115680_p3; +wire [5:0] shl_ln250_1_fu_115692_p3; +wire [8:0] zext_ln250_fu_115688_p1; +wire [8:0] zext_ln250_1_fu_115700_p1; +wire [8:0] sub_ln250_fu_115704_p2; +wire [12:0] sext_ln250_fu_115710_p1; +wire [3:0] or_ln244_fu_115723_p2; +wire [3:0] mul_ln250_1_fu_115733_p0; +wire [12:0] ff4_0_0_0_0_cast42_fu_115739_p1; +wire [5:0] zext_ln250_6_fu_115749_p1; +wire [12:0] add_ln250_1_fu_115753_p2; +wire [6:0] trunc_ln203_s_fu_115834_p4; +wire [25:0] sext_ln203_fu_115844_p1; +wire [3:0] or_ln246_fu_115885_p2; +wire [7:0] shl_ln250_4_fu_115891_p3; +wire [5:0] shl_ln250_5_fu_115903_p3; +wire [8:0] zext_ln250_4_fu_115899_p1; +wire [8:0] zext_ln250_5_fu_115911_p1; +wire [8:0] sub_ln250_2_fu_115915_p2; +wire [12:0] sext_ln250_2_fu_115921_p1; +wire [3:0] or_ln248_fu_115934_p2; +wire [12:0] zext_ln248_fu_115940_p1; +wire [5:0] zext_ln250_11_fu_115944_p1; +wire [12:0] add_ln250_8_fu_115948_p2; +wire [6:0] trunc_ln203_3_fu_116027_p4; +wire [25:0] sext_ln203_5_fu_116037_p1; +wire [12:0] ff4_0_0_1_0_cast39_fu_116115_p1; +wire [5:0] zext_ln250_10_fu_116125_p1; +wire [12:0] add_ln250_5_fu_116129_p2; +wire [6:0] trunc_ln203_2_fu_116210_p4; +wire [25:0] sext_ln203_4_fu_116220_p1; +wire [3:0] or_ln248_2_fu_116267_p2; +wire [12:0] zext_ln248_2_fu_116273_p1; +wire [5:0] zext_ln250_14_fu_116277_p1; +wire [12:0] add_ln250_10_fu_116281_p2; +wire [6:0] trunc_ln203_6_fu_116360_p4; +wire [25:0] sext_ln203_8_fu_116370_p1; +wire [7:0] shl_ln250_2_fu_116454_p3; +wire [5:0] shl_ln250_3_fu_116466_p3; +wire [8:0] zext_ln250_2_fu_116462_p1; +wire [8:0] zext_ln250_3_fu_116474_p1; +wire [8:0] sub_ln250_1_fu_116478_p2; +wire [12:0] sext_ln250_1_fu_116484_p1; +wire [12:0] ff4_0_1_0_0_cast36_fu_116503_p1; +wire [5:0] zext_ln250_9_fu_116513_p1; +wire [12:0] add_ln250_3_fu_116517_p2; +wire [6:0] trunc_ln203_1_fu_116598_p4; +wire [25:0] sext_ln203_3_fu_116608_p1; +wire [3:0] or_ln246_1_fu_116649_p2; +wire [7:0] shl_ln250_6_fu_116655_p3; +wire [5:0] shl_ln250_7_fu_116667_p3; +wire [8:0] zext_ln250_7_fu_116663_p1; +wire [8:0] zext_ln250_8_fu_116675_p1; +wire [8:0] sub_ln250_3_fu_116679_p2; +wire [12:0] sext_ln250_3_fu_116685_p1; +wire [3:0] or_ln248_1_fu_116698_p2; +wire [12:0] zext_ln248_1_fu_116704_p1; +wire [5:0] zext_ln250_13_fu_116708_p1; +wire [12:0] add_ln250_9_fu_116712_p2; +wire [6:0] trunc_ln203_5_fu_116791_p4; +wire [25:0] sext_ln203_7_fu_116801_p1; +wire [12:0] ff4_0_1_1_0_cast33_fu_116879_p1; +wire [5:0] zext_ln250_12_fu_116889_p1; +wire [12:0] add_ln250_7_fu_116893_p2; +wire [6:0] trunc_ln203_4_fu_116974_p4; +wire [25:0] sext_ln203_6_fu_116984_p1; +wire [3:0] or_ln248_3_fu_117031_p2; +wire [12:0] zext_ln248_3_fu_117037_p1; +wire [5:0] zext_ln250_15_fu_117041_p1; +wire [12:0] add_ln250_11_fu_117045_p2; +wire [6:0] trunc_ln203_7_fu_117124_p4; +wire [25:0] sext_ln203_9_fu_117134_p1; +wire [3:0] mul_ln279_2_fu_117226_p0; +wire [3:0] mul_ln279_fu_117232_p0; +wire [7:0] shl_ln1_fu_117248_p3; +wire [5:0] shl_ln279_1_fu_117260_p3; +wire [8:0] zext_ln279_3_fu_117256_p1; +wire [8:0] zext_ln279_4_fu_117268_p1; +wire [8:0] sub_ln279_fu_117272_p2; +wire [12:0] sext_ln279_fu_117278_p1; +wire [3:0] or_ln257_fu_117291_p2; +wire [3:0] mul_ln279_3_fu_117305_p0; +wire [3:0] mul_ln279_1_fu_117311_p0; +wire [12:0] ff7_0_0_0_0_cast29_fu_117317_p1; +wire [5:0] zext_ln279_12_fu_117331_p1; +wire [12:0] add_ln279_1_fu_117335_p2; +wire [6:0] trunc_ln_fu_117345_p4; +wire [25:0] sext_ln1265_fu_117355_p1; +wire [3:0] or_ln259_fu_117427_p2; +wire [7:0] shl_ln279_4_fu_117437_p3; +wire [5:0] shl_ln279_5_fu_117449_p3; +wire [8:0] zext_ln279_9_fu_117445_p1; +wire [8:0] zext_ln279_10_fu_117457_p1; +wire [8:0] sub_ln279_2_fu_117461_p2; +wire [12:0] sext_ln279_2_fu_117467_p1; +wire [17:0] grp_fu_131427_p3; +wire [3:0] or_ln261_fu_117493_p2; +wire [12:0] zext_ln261_1_fu_117503_p1; +wire [5:0] zext_ln279_21_fu_117507_p1; +wire [12:0] add_ln279_6_fu_117511_p2; +wire [6:0] trunc_ln1265_3_fu_117521_p4; +wire [25:0] sext_ln1265_3_fu_117531_p1; +wire [31:0] add_ln276_14_fu_117609_p2; +wire [31:0] shl_ln276_fu_117603_p2; +wire [31:0] grp_fu_117625_p0; +wire [5:0] grp_fu_117625_p1; +wire [31:0] grp_fu_117634_p0; +wire [33:0] grp_fu_117634_p1; +wire [64:0] grp_fu_117634_p2; +wire [31:0] grp_fu_117625_p2; +wire [31:0] or_ln268_fu_117812_p2; +wire [31:0] grp_fu_117829_p0; +wire [5:0] grp_fu_117829_p1; +wire [31:0] or_ln266_fu_117835_p2; +wire [31:0] add_ln276_46_fu_117853_p2; +wire [31:0] shl_ln276_23_fu_117847_p2; +wire [1:0] empty_319_fu_117864_p1; +wire [1:0] or_ln264_fu_117868_p2; +wire [17:0] grp_fu_131442_p3; +wire [31:0] grp_fu_117884_p0; +wire [33:0] grp_fu_117884_p1; +wire [64:0] grp_fu_117884_p2; +wire [31:0] grp_fu_117829_p2; +wire [31:0] grp_fu_118041_p0; +wire [5:0] grp_fu_118041_p1; +wire [31:0] grp_fu_118050_p0; +wire [33:0] grp_fu_118050_p1; +wire [64:0] grp_fu_118050_p2; +wire [31:0] grp_fu_118041_p2; +wire [31:0] or_ln268_8_fu_118228_p2; +wire [31:0] grp_fu_118245_p0; +wire [5:0] grp_fu_118245_p1; +wire [31:0] grp_fu_118260_p0; +wire [33:0] grp_fu_118260_p1; +wire [64:0] grp_fu_118260_p2; +wire [31:0] grp_fu_118245_p2; +wire [31:0] add_ln276_51_fu_118418_p2; +wire [31:0] shl_ln276_24_fu_118412_p2; +wire [31:0] grp_fu_118434_p0; +wire [5:0] grp_fu_118434_p1; +wire [31:0] grp_fu_118443_p0; +wire [33:0] grp_fu_118443_p1; +wire [64:0] grp_fu_118443_p2; +wire [31:0] grp_fu_118434_p2; +wire [31:0] or_ln268_9_fu_118621_p2; +wire [31:0] grp_fu_118638_p0; +wire [5:0] grp_fu_118638_p1; +wire [31:0] or_ln266_8_fu_118644_p2; +wire [31:0] add_ln276_113_fu_118662_p2; +wire [31:0] shl_ln276_39_fu_118656_p2; +wire [31:0] grp_fu_118682_p0; +wire [33:0] grp_fu_118682_p1; +wire [64:0] grp_fu_118682_p2; +wire [31:0] grp_fu_118638_p2; +wire [31:0] grp_fu_118839_p0; +wire [5:0] grp_fu_118839_p1; +wire [31:0] grp_fu_118848_p0; +wire [33:0] grp_fu_118848_p1; +wire [64:0] grp_fu_118848_p2; +wire [31:0] grp_fu_118839_p2; +wire [31:0] or_ln268_24_fu_119026_p2; +wire [31:0] grp_fu_119043_p0; +wire [5:0] grp_fu_119043_p1; +wire [31:0] grp_fu_119058_p0; +wire [33:0] grp_fu_119058_p1; +wire [64:0] grp_fu_119058_p2; +wire [31:0] grp_fu_119043_p2; +wire [17:0] grp_fu_131450_p3; +wire [31:0] add_ln276_26_fu_119235_p2; +wire [31:0] shl_ln276_18_fu_119229_p2; +wire [31:0] grp_fu_119251_p0; +wire [5:0] grp_fu_119251_p1; +wire [31:0] grp_fu_119260_p0; +wire [33:0] grp_fu_119260_p1; +wire [64:0] grp_fu_119260_p2; +wire [31:0] grp_fu_119251_p2; +wire [31:0] or_ln268_3_fu_119438_p2; +wire [31:0] grp_fu_119455_p0; +wire [5:0] grp_fu_119455_p1; +wire [31:0] or_ln266_3_fu_119461_p2; +wire [31:0] add_ln276_64_fu_119479_p2; +wire [31:0] shl_ln276_27_fu_119473_p2; +wire [1:0] empty_334_fu_119490_p1; +wire [1:0] or_ln264_3_fu_119494_p2; +wire [17:0] grp_fu_131458_p3; +wire [31:0] grp_fu_119510_p0; +wire [33:0] grp_fu_119510_p1; +wire [64:0] grp_fu_119510_p2; +wire [31:0] grp_fu_119455_p2; +wire [31:0] grp_fu_119666_p0; +wire [5:0] grp_fu_119666_p1; +wire [31:0] grp_fu_119675_p0; +wire [33:0] grp_fu_119675_p1; +wire [64:0] grp_fu_119675_p2; +wire [31:0] grp_fu_119666_p2; +wire [31:0] or_ln268_12_fu_119853_p2; +wire [31:0] grp_fu_119870_p0; +wire [5:0] grp_fu_119870_p1; +wire [31:0] grp_fu_119885_p0; +wire [33:0] grp_fu_119885_p1; +wire [64:0] grp_fu_119885_p2; +wire [31:0] grp_fu_119870_p2; +wire [31:0] add_ln276_74_fu_120042_p2; +wire [31:0] shl_ln276_30_fu_120036_p2; +wire [31:0] grp_fu_120058_p0; +wire [5:0] grp_fu_120058_p1; +wire [31:0] grp_fu_120067_p0; +wire [33:0] grp_fu_120067_p1; +wire [64:0] grp_fu_120067_p2; +wire [31:0] grp_fu_120058_p2; +wire [31:0] or_ln268_15_fu_120245_p2; +wire [31:0] grp_fu_120262_p0; +wire [5:0] grp_fu_120262_p1; +wire [31:0] or_ln266_11_fu_120268_p2; +wire [31:0] add_ln276_126_fu_120286_p2; +wire [31:0] shl_ln276_42_fu_120280_p2; +wire [31:0] grp_fu_120306_p0; +wire [33:0] grp_fu_120306_p1; +wire [64:0] grp_fu_120306_p2; +wire [31:0] grp_fu_120262_p2; +wire [31:0] grp_fu_120462_p0; +wire [5:0] grp_fu_120462_p1; +wire [31:0] grp_fu_120471_p0; +wire [33:0] grp_fu_120471_p1; +wire [64:0] grp_fu_120471_p2; +wire [31:0] grp_fu_120462_p2; +wire [31:0] or_ln268_27_fu_120649_p2; +wire [31:0] grp_fu_120666_p0; +wire [5:0] grp_fu_120666_p1; +wire [31:0] grp_fu_120681_p0; +wire [33:0] grp_fu_120681_p1; +wire [64:0] grp_fu_120681_p2; +wire [31:0] grp_fu_120666_p2; +wire [12:0] ff7_0_0_1_0_cast21_fu_120832_p1; +wire [5:0] zext_ln279_19_fu_120846_p1; +wire [12:0] add_ln279_5_fu_120850_p2; +wire [6:0] trunc_ln1265_2_fu_120860_p4; +wire [25:0] sext_ln1265_2_fu_120870_p1; +wire [17:0] grp_fu_131473_p3; +wire [3:0] or_ln261_2_fu_120961_p2; +wire [12:0] zext_ln261_5_fu_120971_p1; +wire [5:0] zext_ln279_27_fu_120975_p1; +wire [12:0] add_ln279_10_fu_120979_p2; +wire [6:0] trunc_ln1265_6_fu_120989_p4; +wire [25:0] sext_ln1265_6_fu_120999_p1; +wire [31:0] add_ln276_25_fu_121077_p2; +wire [31:0] shl_ln276_17_fu_121071_p2; +wire [31:0] grp_fu_121093_p0; +wire [5:0] grp_fu_121093_p1; +wire [31:0] grp_fu_121102_p0; +wire [33:0] grp_fu_121102_p1; +wire [64:0] grp_fu_121102_p2; +wire [31:0] grp_fu_121093_p2; +wire [31:0] or_ln268_2_fu_121280_p2; +wire [31:0] grp_fu_121297_p0; +wire [5:0] grp_fu_121297_p1; +wire [31:0] or_ln266_2_fu_121303_p2; +wire [31:0] add_ln276_58_fu_121321_p2; +wire [31:0] shl_ln276_26_fu_121315_p2; +wire [1:0] empty_351_fu_121332_p1; +wire [1:0] or_ln264_2_fu_121336_p2; +wire [17:0] grp_fu_131488_p3; +wire [31:0] grp_fu_121352_p0; +wire [33:0] grp_fu_121352_p1; +wire [64:0] grp_fu_121352_p2; +wire [31:0] grp_fu_121297_p2; +wire [31:0] grp_fu_121509_p0; +wire [5:0] grp_fu_121509_p1; +wire [31:0] grp_fu_121518_p0; +wire [33:0] grp_fu_121518_p1; +wire [64:0] grp_fu_121518_p2; +wire [31:0] grp_fu_121509_p2; +wire [31:0] or_ln268_11_fu_121696_p2; +wire [31:0] grp_fu_121713_p0; +wire [5:0] grp_fu_121713_p1; +wire [31:0] grp_fu_121728_p0; +wire [33:0] grp_fu_121728_p1; +wire [64:0] grp_fu_121728_p2; +wire [31:0] grp_fu_121713_p2; +wire [31:0] add_ln276_71_fu_121886_p2; +wire [31:0] shl_ln276_29_fu_121880_p2; +wire [31:0] grp_fu_121902_p0; +wire [5:0] grp_fu_121902_p1; +wire [31:0] grp_fu_121911_p0; +wire [33:0] grp_fu_121911_p1; +wire [64:0] grp_fu_121911_p2; +wire [31:0] grp_fu_121902_p2; +wire [31:0] or_ln268_14_fu_122089_p2; +wire [31:0] grp_fu_122106_p0; +wire [5:0] grp_fu_122106_p1; +wire [31:0] or_ln266_10_fu_122112_p2; +wire [31:0] add_ln276_124_fu_122130_p2; +wire [31:0] shl_ln276_41_fu_122124_p2; +wire [31:0] grp_fu_122150_p0; +wire [33:0] grp_fu_122150_p1; +wire [64:0] grp_fu_122150_p2; +wire [31:0] grp_fu_122106_p2; +wire [31:0] grp_fu_122307_p0; +wire [5:0] grp_fu_122307_p1; +wire [31:0] grp_fu_122316_p0; +wire [33:0] grp_fu_122316_p1; +wire [64:0] grp_fu_122316_p2; +wire [31:0] grp_fu_122307_p2; +wire [31:0] or_ln268_26_fu_122494_p2; +wire [31:0] grp_fu_122511_p0; +wire [5:0] grp_fu_122511_p1; +wire [31:0] grp_fu_122526_p0; +wire [33:0] grp_fu_122526_p1; +wire [64:0] grp_fu_122526_p2; +wire [31:0] grp_fu_122511_p2; +wire [17:0] grp_fu_131496_p3; +wire [31:0] add_ln276_37_fu_122703_p2; +wire [31:0] shl_ln276_21_fu_122697_p2; +wire [31:0] grp_fu_122719_p0; +wire [5:0] grp_fu_122719_p1; +wire [31:0] grp_fu_122728_p0; +wire [33:0] grp_fu_122728_p1; +wire [64:0] grp_fu_122728_p2; +wire [31:0] grp_fu_122719_p2; +wire [31:0] or_ln268_6_fu_122906_p2; +wire [31:0] grp_fu_122923_p0; +wire [5:0] grp_fu_122923_p1; +wire [31:0] or_ln266_6_fu_122929_p2; +wire [31:0] add_ln276_87_fu_122947_p2; +wire [31:0] shl_ln276_33_fu_122941_p2; +wire [1:0] empty_366_fu_122958_p1; +wire [1:0] or_ln264_6_fu_122962_p2; +wire [17:0] grp_fu_131504_p3; +wire [31:0] grp_fu_122978_p0; +wire [33:0] grp_fu_122978_p1; +wire [64:0] grp_fu_122978_p2; +wire [31:0] grp_fu_122923_p2; +wire [31:0] grp_fu_123134_p0; +wire [5:0] grp_fu_123134_p1; +wire [31:0] grp_fu_123143_p0; +wire [33:0] grp_fu_123143_p1; +wire [64:0] grp_fu_123143_p2; +wire [31:0] grp_fu_123134_p2; +wire [31:0] or_ln268_18_fu_123321_p2; +wire [31:0] grp_fu_123338_p0; +wire [5:0] grp_fu_123338_p1; +wire [31:0] grp_fu_123353_p0; +wire [33:0] grp_fu_123353_p1; +wire [64:0] grp_fu_123353_p2; +wire [31:0] grp_fu_123338_p2; +wire [31:0] add_ln276_96_fu_123510_p2; +wire [31:0] shl_ln276_36_fu_123504_p2; +wire [31:0] grp_fu_123526_p0; +wire [5:0] grp_fu_123526_p1; +wire [31:0] grp_fu_123535_p0; +wire [33:0] grp_fu_123535_p1; +wire [64:0] grp_fu_123535_p2; +wire [31:0] grp_fu_123526_p2; +wire [31:0] or_ln268_21_fu_123713_p2; +wire [31:0] grp_fu_123730_p0; +wire [5:0] grp_fu_123730_p1; +wire [31:0] or_ln266_14_fu_123736_p2; +wire [31:0] add_ln276_139_fu_123754_p2; +wire [31:0] shl_ln276_45_fu_123748_p2; +wire [31:0] grp_fu_123774_p0; +wire [33:0] grp_fu_123774_p1; +wire [64:0] grp_fu_123774_p2; +wire [31:0] grp_fu_123730_p2; +wire [31:0] grp_fu_123930_p0; +wire [5:0] grp_fu_123930_p1; +wire [31:0] grp_fu_123939_p0; +wire [33:0] grp_fu_123939_p1; +wire [64:0] grp_fu_123939_p2; +wire [31:0] grp_fu_123930_p2; +wire [31:0] or_ln268_30_fu_124117_p2; +wire [31:0] grp_fu_124134_p0; +wire [5:0] grp_fu_124134_p1; +wire [31:0] grp_fu_124149_p0; +wire [33:0] grp_fu_124149_p1; +wire [64:0] grp_fu_124149_p2; +wire [31:0] grp_fu_124134_p2; +wire [7:0] shl_ln279_2_fu_124310_p3; +wire [5:0] shl_ln279_3_fu_124322_p3; +wire [8:0] zext_ln279_6_fu_124318_p1; +wire [8:0] zext_ln279_7_fu_124330_p1; +wire [8:0] sub_ln279_1_fu_124334_p2; +wire [12:0] sext_ln279_1_fu_124340_p1; +wire [12:0] ff7_0_1_0_0_cast13_fu_124359_p1; +wire [5:0] zext_ln279_17_fu_124373_p1; +wire [12:0] add_ln279_3_fu_124377_p2; +wire [6:0] trunc_ln1265_1_fu_124387_p4; +wire [25:0] sext_ln1265_1_fu_124397_p1; +wire [3:0] or_ln259_1_fu_124469_p2; +wire [7:0] shl_ln279_6_fu_124479_p3; +wire [5:0] shl_ln279_7_fu_124491_p3; +wire [8:0] zext_ln279_14_fu_124487_p1; +wire [8:0] zext_ln279_15_fu_124499_p1; +wire [8:0] sub_ln279_3_fu_124503_p2; +wire [12:0] sext_ln279_3_fu_124509_p1; +wire [18:0] grp_fu_131533_p3; +wire [3:0] or_ln261_1_fu_124535_p2; +wire [12:0] zext_ln261_3_fu_124545_p1; +wire [5:0] zext_ln279_25_fu_124549_p1; +wire [12:0] add_ln279_9_fu_124553_p2; +wire [6:0] trunc_ln1265_5_fu_124563_p4; +wire [25:0] sext_ln1265_5_fu_124573_p1; +wire [31:0] add_ln276_24_fu_124651_p2; +wire [31:0] shl_ln276_16_fu_124645_p2; +wire [31:0] grp_fu_124667_p0; +wire [5:0] grp_fu_124667_p1; +wire [31:0] grp_fu_124676_p0; +wire [33:0] grp_fu_124676_p1; +wire [64:0] grp_fu_124676_p2; +wire [31:0] grp_fu_124667_p2; +wire [31:0] or_ln268_1_fu_124854_p2; +wire [31:0] grp_fu_124871_p0; +wire [5:0] grp_fu_124871_p1; +wire [31:0] or_ln266_1_fu_124877_p2; +wire [31:0] add_ln276_55_fu_124895_p2; +wire [31:0] shl_ln276_25_fu_124889_p2; +wire [1:0] empty_385_fu_124906_p1; +wire [1:0] or_ln264_1_fu_124910_p2; +wire [18:0] grp_fu_131548_p3; +wire [31:0] grp_fu_124926_p0; +wire [33:0] grp_fu_124926_p1; +wire [64:0] grp_fu_124926_p2; +wire [31:0] grp_fu_124871_p2; +wire [31:0] grp_fu_125083_p0; +wire [5:0] grp_fu_125083_p1; +wire [31:0] grp_fu_125092_p0; +wire [33:0] grp_fu_125092_p1; +wire [64:0] grp_fu_125092_p2; +wire [31:0] grp_fu_125083_p2; +wire [31:0] or_ln268_10_fu_125270_p2; +wire [31:0] grp_fu_125287_p0; +wire [5:0] grp_fu_125287_p1; +wire [31:0] grp_fu_125302_p0; +wire [33:0] grp_fu_125302_p1; +wire [64:0] grp_fu_125302_p2; +wire [31:0] grp_fu_125287_p2; +wire [31:0] add_ln276_68_fu_125460_p2; +wire [31:0] shl_ln276_28_fu_125454_p2; +wire [31:0] grp_fu_125476_p0; +wire [5:0] grp_fu_125476_p1; +wire [31:0] grp_fu_125485_p0; +wire [33:0] grp_fu_125485_p1; +wire [64:0] grp_fu_125485_p2; +wire [31:0] grp_fu_125476_p2; +wire [31:0] or_ln268_13_fu_125663_p2; +wire [31:0] grp_fu_125680_p0; +wire [5:0] grp_fu_125680_p1; +wire [31:0] or_ln266_9_fu_125686_p2; +wire [31:0] add_ln276_121_fu_125704_p2; +wire [31:0] shl_ln276_40_fu_125698_p2; +wire [31:0] grp_fu_125724_p0; +wire [33:0] grp_fu_125724_p1; +wire [64:0] grp_fu_125724_p2; +wire [31:0] grp_fu_125680_p2; +wire [31:0] grp_fu_125881_p0; +wire [5:0] grp_fu_125881_p1; +wire [31:0] grp_fu_125890_p0; +wire [33:0] grp_fu_125890_p1; +wire [64:0] grp_fu_125890_p2; +wire [31:0] grp_fu_125881_p2; +wire [31:0] or_ln268_25_fu_126068_p2; +wire [31:0] grp_fu_126085_p0; +wire [5:0] grp_fu_126085_p1; +wire [31:0] grp_fu_126100_p0; +wire [33:0] grp_fu_126100_p1; +wire [64:0] grp_fu_126100_p2; +wire [31:0] grp_fu_126085_p2; +wire [18:0] grp_fu_131556_p3; +wire [31:0] add_ln276_34_fu_126277_p2; +wire [31:0] shl_ln276_20_fu_126271_p2; +wire [31:0] grp_fu_126293_p0; +wire [5:0] grp_fu_126293_p1; +wire [31:0] grp_fu_126302_p0; +wire [33:0] grp_fu_126302_p1; +wire [64:0] grp_fu_126302_p2; +wire [31:0] grp_fu_126293_p2; +wire [31:0] or_ln268_5_fu_126480_p2; +wire [31:0] grp_fu_126497_p0; +wire [5:0] grp_fu_126497_p1; +wire [31:0] or_ln266_5_fu_126503_p2; +wire [31:0] add_ln276_81_fu_126521_p2; +wire [31:0] shl_ln276_32_fu_126515_p2; +wire [1:0] empty_400_fu_126532_p1; +wire [1:0] or_ln264_5_fu_126536_p2; +wire [18:0] grp_fu_131564_p3; +wire [31:0] grp_fu_126552_p0; +wire [33:0] grp_fu_126552_p1; +wire [64:0] grp_fu_126552_p2; +wire [31:0] grp_fu_126497_p2; +wire [31:0] grp_fu_126708_p0; +wire [5:0] grp_fu_126708_p1; +wire [31:0] grp_fu_126717_p0; +wire [33:0] grp_fu_126717_p1; +wire [64:0] grp_fu_126717_p2; +wire [31:0] grp_fu_126708_p2; +wire [31:0] or_ln268_17_fu_126895_p2; +wire [31:0] grp_fu_126912_p0; +wire [5:0] grp_fu_126912_p1; +wire [31:0] grp_fu_126927_p0; +wire [33:0] grp_fu_126927_p1; +wire [64:0] grp_fu_126927_p2; +wire [31:0] grp_fu_126912_p2; +wire [31:0] add_ln276_93_fu_127084_p2; +wire [31:0] shl_ln276_35_fu_127078_p2; +wire [31:0] grp_fu_127100_p0; +wire [5:0] grp_fu_127100_p1; +wire [31:0] grp_fu_127109_p0; +wire [33:0] grp_fu_127109_p1; +wire [64:0] grp_fu_127109_p2; +wire [31:0] grp_fu_127100_p2; +wire [31:0] or_ln268_20_fu_127287_p2; +wire [31:0] grp_fu_127304_p0; +wire [5:0] grp_fu_127304_p1; +wire [31:0] or_ln266_13_fu_127310_p2; +wire [31:0] add_ln276_137_fu_127328_p2; +wire [31:0] shl_ln276_44_fu_127322_p2; +wire [31:0] grp_fu_127348_p0; +wire [33:0] grp_fu_127348_p1; +wire [64:0] grp_fu_127348_p2; +wire [31:0] grp_fu_127304_p2; +wire [31:0] grp_fu_127504_p0; +wire [5:0] grp_fu_127504_p1; +wire [31:0] grp_fu_127513_p0; +wire [33:0] grp_fu_127513_p1; +wire [64:0] grp_fu_127513_p2; +wire [31:0] grp_fu_127504_p2; +wire [31:0] or_ln268_29_fu_127691_p2; +wire [31:0] grp_fu_127708_p0; +wire [5:0] grp_fu_127708_p1; +wire [31:0] grp_fu_127723_p0; +wire [33:0] grp_fu_127723_p1; +wire [64:0] grp_fu_127723_p2; +wire [31:0] grp_fu_127708_p2; +wire [12:0] ff7_0_1_1_0_cast5_fu_127874_p1; +wire [5:0] zext_ln279_23_fu_127888_p1; +wire [12:0] add_ln279_8_fu_127892_p2; +wire [6:0] trunc_ln1265_4_fu_127902_p4; +wire [25:0] sext_ln1265_4_fu_127912_p1; +wire [18:0] grp_fu_131579_p3; +wire [3:0] or_ln261_3_fu_128003_p2; +wire [12:0] zext_ln261_7_fu_128013_p1; +wire [5:0] zext_ln279_29_fu_128017_p1; +wire [12:0] add_ln279_11_fu_128021_p2; +wire [6:0] trunc_ln1265_7_fu_128031_p4; +wire [25:0] sext_ln1265_7_fu_128041_p1; +wire [31:0] add_ln276_33_fu_128119_p2; +wire [31:0] shl_ln276_19_fu_128113_p2; +wire [31:0] grp_fu_128135_p0; +wire [5:0] grp_fu_128135_p1; +wire [31:0] grp_fu_128144_p0; +wire [33:0] grp_fu_128144_p1; +wire [64:0] grp_fu_128144_p2; +wire [31:0] grp_fu_128135_p2; +wire [31:0] or_ln268_4_fu_128322_p2; +wire [31:0] grp_fu_128339_p0; +wire [5:0] grp_fu_128339_p1; +wire [31:0] or_ln266_4_fu_128345_p2; +wire [31:0] add_ln276_77_fu_128363_p2; +wire [31:0] shl_ln276_31_fu_128357_p2; +wire [1:0] empty_417_fu_128374_p1; +wire [1:0] or_ln264_4_fu_128378_p2; +wire [18:0] grp_fu_131594_p3; +wire [31:0] grp_fu_128394_p0; +wire [33:0] grp_fu_128394_p1; +wire [64:0] grp_fu_128394_p2; +wire [31:0] grp_fu_128339_p2; +wire [31:0] grp_fu_128551_p0; +wire [5:0] grp_fu_128551_p1; +wire [31:0] grp_fu_128560_p0; +wire [33:0] grp_fu_128560_p1; +wire [64:0] grp_fu_128560_p2; +wire [31:0] grp_fu_128551_p2; +wire [31:0] or_ln268_16_fu_128738_p2; +wire [31:0] grp_fu_128755_p0; +wire [5:0] grp_fu_128755_p1; +wire [31:0] grp_fu_128770_p0; +wire [33:0] grp_fu_128770_p1; +wire [64:0] grp_fu_128770_p2; +wire [31:0] grp_fu_128755_p2; +wire [31:0] add_ln276_90_fu_128928_p2; +wire [31:0] shl_ln276_34_fu_128922_p2; +wire [31:0] grp_fu_128944_p0; +wire [5:0] grp_fu_128944_p1; +wire [31:0] grp_fu_128953_p0; +wire [33:0] grp_fu_128953_p1; +wire [64:0] grp_fu_128953_p2; +wire [31:0] grp_fu_128944_p2; +wire [31:0] or_ln268_19_fu_129131_p2; +wire [31:0] grp_fu_129148_p0; +wire [5:0] grp_fu_129148_p1; +wire [31:0] or_ln266_12_fu_129154_p2; +wire [31:0] add_ln276_135_fu_129172_p2; +wire [31:0] shl_ln276_43_fu_129166_p2; +wire [31:0] grp_fu_129192_p0; +wire [33:0] grp_fu_129192_p1; +wire [64:0] grp_fu_129192_p2; +wire [31:0] grp_fu_129148_p2; +wire [31:0] grp_fu_129349_p0; +wire [5:0] grp_fu_129349_p1; +wire [31:0] grp_fu_129358_p0; +wire [33:0] grp_fu_129358_p1; +wire [64:0] grp_fu_129358_p2; +wire [31:0] grp_fu_129349_p2; +wire [31:0] or_ln268_28_fu_129536_p2; +wire [31:0] grp_fu_129553_p0; +wire [5:0] grp_fu_129553_p1; +wire [31:0] grp_fu_129568_p0; +wire [33:0] grp_fu_129568_p1; +wire [64:0] grp_fu_129568_p2; +wire [31:0] grp_fu_129553_p2; +wire [18:0] grp_fu_131602_p3; +wire [31:0] add_ln276_41_fu_129745_p2; +wire [31:0] shl_ln276_22_fu_129739_p2; +wire [31:0] grp_fu_129761_p0; +wire [5:0] grp_fu_129761_p1; +wire [31:0] grp_fu_129770_p0; +wire [33:0] grp_fu_129770_p1; +wire [64:0] grp_fu_129770_p2; +wire [31:0] grp_fu_129761_p2; +wire [31:0] or_ln268_7_fu_129948_p2; +wire [31:0] grp_fu_129965_p0; +wire [5:0] grp_fu_129965_p1; +wire [31:0] or_ln266_7_fu_129971_p2; +wire [31:0] add_ln276_100_fu_129989_p2; +wire [31:0] shl_ln276_37_fu_129983_p2; +wire [1:0] empty_432_fu_130000_p1; +wire [1:0] or_ln264_7_fu_130004_p2; +wire [18:0] grp_fu_131610_p3; +wire [31:0] grp_fu_130020_p0; +wire [33:0] grp_fu_130020_p1; +wire [64:0] grp_fu_130020_p2; +wire [31:0] grp_fu_129965_p2; +wire [31:0] grp_fu_130176_p0; +wire [5:0] grp_fu_130176_p1; +wire [31:0] grp_fu_130185_p0; +wire [33:0] grp_fu_130185_p1; +wire [64:0] grp_fu_130185_p2; +wire [31:0] grp_fu_130176_p2; +wire [31:0] or_ln268_22_fu_130363_p2; +wire [31:0] grp_fu_130380_p0; +wire [5:0] grp_fu_130380_p1; +wire [31:0] grp_fu_130395_p0; +wire [33:0] grp_fu_130395_p1; +wire [64:0] grp_fu_130395_p2; +wire [31:0] grp_fu_130380_p2; +wire [31:0] add_ln276_105_fu_130552_p2; +wire [31:0] shl_ln276_38_fu_130546_p2; +wire [31:0] grp_fu_130568_p0; +wire [5:0] grp_fu_130568_p1; +wire [31:0] grp_fu_130577_p0; +wire [33:0] grp_fu_130577_p1; +wire [64:0] grp_fu_130577_p2; +wire [31:0] grp_fu_130568_p2; +wire [31:0] or_ln268_23_fu_130755_p2; +wire [31:0] grp_fu_130772_p0; +wire [5:0] grp_fu_130772_p1; +wire [31:0] or_ln266_15_fu_130778_p2; +wire [31:0] add_ln276_145_fu_130796_p2; +wire [31:0] shl_ln276_46_fu_130790_p2; +wire [31:0] grp_fu_130816_p0; +wire [33:0] grp_fu_130816_p1; +wire [64:0] grp_fu_130816_p2; +wire [31:0] grp_fu_130772_p2; +wire [31:0] grp_fu_130972_p0; +wire [5:0] grp_fu_130972_p1; +wire [31:0] grp_fu_130981_p0; +wire [33:0] grp_fu_130981_p1; +wire [64:0] grp_fu_130981_p2; +wire [31:0] grp_fu_130972_p2; +wire [31:0] or_ln268_31_fu_131159_p2; +wire [31:0] grp_fu_131176_p0; +wire [5:0] grp_fu_131176_p1; +wire [31:0] grp_fu_131191_p0; +wire [33:0] grp_fu_131191_p1; +wire [64:0] grp_fu_131191_p2; +wire [31:0] grp_fu_131176_p2; +wire [5:0] grp_fu_131342_p0; +wire [2:0] grp_fu_131342_p1; +wire [1:0] grp_fu_131350_p0; +wire [5:0] grp_fu_131350_p1; +wire [5:0] grp_fu_131358_p0; +wire [2:0] grp_fu_131358_p1; +wire [1:0] grp_fu_131366_p0; +wire [5:0] grp_fu_131366_p1; +wire [5:0] grp_fu_131374_p0; +wire [2:0] grp_fu_131374_p1; +wire [1:0] grp_fu_131382_p0; +wire [5:0] grp_fu_131382_p1; +wire [5:0] grp_fu_131390_p0; +wire [2:0] grp_fu_131390_p1; +wire [1:0] grp_fu_131398_p0; +wire [5:0] grp_fu_131398_p1; +wire [11:0] grp_fu_131406_p0; +wire [3:0] grp_fu_131406_p1; +wire [3:0] grp_fu_131413_p0; +wire [7:0] grp_fu_131413_p1; +wire [11:0] grp_fu_131420_p0; +wire [3:0] grp_fu_131420_p1; +wire [2:0] grp_fu_131427_p0; +wire [5:0] grp_fu_131427_p1; +wire [3:0] grp_fu_131435_p0; +wire [7:0] grp_fu_131435_p1; +wire [5:0] grp_fu_131442_p0; +wire [1:0] grp_fu_131442_p1; +wire [2:0] grp_fu_131450_p0; +wire [5:0] grp_fu_131450_p1; +wire [5:0] grp_fu_131458_p0; +wire [1:0] grp_fu_131458_p1; +wire [3:0] grp_fu_131466_p0; +wire [7:0] grp_fu_131466_p1; +wire [2:0] grp_fu_131473_p0; +wire [5:0] grp_fu_131473_p1; +wire [3:0] grp_fu_131481_p0; +wire [7:0] grp_fu_131481_p1; +wire [5:0] grp_fu_131488_p0; +wire [1:0] grp_fu_131488_p1; +wire [2:0] grp_fu_131496_p0; +wire [5:0] grp_fu_131496_p1; +wire [5:0] grp_fu_131504_p0; +wire [1:0] grp_fu_131504_p1; +wire [11:0] grp_fu_131512_p0; +wire [3:0] grp_fu_131512_p1; +wire [3:0] grp_fu_131519_p0; +wire [7:0] grp_fu_131519_p1; +wire [11:0] grp_fu_131526_p0; +wire [3:0] grp_fu_131526_p1; +wire [2:0] grp_fu_131533_p0; +wire [5:0] grp_fu_131533_p1; +wire [3:0] grp_fu_131541_p0; +wire [7:0] grp_fu_131541_p1; +wire [5:0] grp_fu_131548_p0; +wire [1:0] grp_fu_131548_p1; +wire [2:0] grp_fu_131556_p0; +wire [5:0] grp_fu_131556_p1; +wire [5:0] grp_fu_131564_p0; +wire [1:0] grp_fu_131564_p1; +wire [3:0] grp_fu_131572_p0; +wire [7:0] grp_fu_131572_p1; +wire [2:0] grp_fu_131579_p0; +wire [5:0] grp_fu_131579_p1; +wire [3:0] grp_fu_131587_p0; +wire [7:0] grp_fu_131587_p1; +wire [5:0] grp_fu_131594_p0; +wire [1:0] grp_fu_131594_p1; +wire [2:0] grp_fu_131602_p0; +wire [5:0] grp_fu_131602_p1; +wire [5:0] grp_fu_131610_p0; +wire [1:0] grp_fu_131610_p1; +reg grp_fu_99047_ap_start; +wire grp_fu_99047_ap_done; +reg grp_fu_99053_ap_start; +wire grp_fu_99053_ap_done; +reg grp_fu_99064_ap_start; +wire grp_fu_99064_ap_done; +reg grp_fu_99070_ap_start; +wire grp_fu_99070_ap_done; +reg grp_fu_99081_ap_start; +wire grp_fu_99081_ap_done; +reg grp_fu_99087_ap_start; +wire grp_fu_99087_ap_done; +reg grp_fu_99098_ap_start; +wire grp_fu_99098_ap_done; +reg grp_fu_99104_ap_start; +wire grp_fu_99104_ap_done; +reg grp_fu_99115_ap_start; +wire grp_fu_99115_ap_done; +reg grp_fu_99121_ap_start; +wire grp_fu_99121_ap_done; +reg grp_fu_99132_ap_start; +wire grp_fu_99132_ap_done; +reg grp_fu_99138_ap_start; +wire grp_fu_99138_ap_done; +reg grp_fu_99149_ap_start; +wire grp_fu_99149_ap_done; +reg grp_fu_99155_ap_start; +wire grp_fu_99155_ap_done; +reg grp_fu_99166_ap_start; +wire grp_fu_99166_ap_done; +reg grp_fu_99172_ap_start; +wire grp_fu_99172_ap_done; +reg grp_fu_99183_ap_start; +wire grp_fu_99183_ap_done; +reg grp_fu_99189_ap_start; +wire grp_fu_99189_ap_done; +reg grp_fu_99200_ap_start; +wire grp_fu_99200_ap_done; +reg grp_fu_99206_ap_start; +wire grp_fu_99206_ap_done; +reg grp_fu_99217_ap_start; +wire grp_fu_99217_ap_done; +reg grp_fu_99223_ap_start; +wire grp_fu_99223_ap_done; +reg grp_fu_99234_ap_start; +wire grp_fu_99234_ap_done; +reg grp_fu_99240_ap_start; +wire grp_fu_99240_ap_done; +reg grp_fu_99251_ap_start; +wire grp_fu_99251_ap_done; +reg grp_fu_99257_ap_start; +wire grp_fu_99257_ap_done; +reg grp_fu_99268_ap_start; +wire grp_fu_99268_ap_done; +reg grp_fu_99274_ap_start; +wire grp_fu_99274_ap_done; +reg grp_fu_99285_ap_start; +wire grp_fu_99285_ap_done; +reg grp_fu_99291_ap_start; +wire grp_fu_99291_ap_done; +reg grp_fu_99302_ap_start; +wire grp_fu_99302_ap_done; +reg grp_fu_99308_ap_start; +wire grp_fu_99308_ap_done; +reg grp_fu_117625_ap_start; +wire grp_fu_117625_ap_done; +reg grp_fu_117829_ap_start; +wire grp_fu_117829_ap_done; +reg grp_fu_118041_ap_start; +wire grp_fu_118041_ap_done; +reg grp_fu_118245_ap_start; +wire grp_fu_118245_ap_done; +reg grp_fu_118434_ap_start; +wire grp_fu_118434_ap_done; +reg grp_fu_118638_ap_start; +wire grp_fu_118638_ap_done; +reg grp_fu_118839_ap_start; +wire grp_fu_118839_ap_done; +reg grp_fu_119043_ap_start; +wire grp_fu_119043_ap_done; +reg grp_fu_119251_ap_start; +wire grp_fu_119251_ap_done; +reg grp_fu_119455_ap_start; +wire grp_fu_119455_ap_done; +reg grp_fu_119666_ap_start; +wire grp_fu_119666_ap_done; +reg grp_fu_119870_ap_start; +wire grp_fu_119870_ap_done; +reg grp_fu_120058_ap_start; +wire grp_fu_120058_ap_done; +reg grp_fu_120262_ap_start; +wire grp_fu_120262_ap_done; +reg grp_fu_120462_ap_start; +wire grp_fu_120462_ap_done; +reg grp_fu_120666_ap_start; +wire grp_fu_120666_ap_done; +reg grp_fu_121093_ap_start; +wire grp_fu_121093_ap_done; +reg grp_fu_121297_ap_start; +wire grp_fu_121297_ap_done; +reg grp_fu_121509_ap_start; +wire grp_fu_121509_ap_done; +reg grp_fu_121713_ap_start; +wire grp_fu_121713_ap_done; +reg grp_fu_121902_ap_start; +wire grp_fu_121902_ap_done; +reg grp_fu_122106_ap_start; +wire grp_fu_122106_ap_done; +reg grp_fu_122307_ap_start; +wire grp_fu_122307_ap_done; +reg grp_fu_122511_ap_start; +wire grp_fu_122511_ap_done; +reg grp_fu_122719_ap_start; +wire grp_fu_122719_ap_done; +reg grp_fu_122923_ap_start; +wire grp_fu_122923_ap_done; +reg grp_fu_123134_ap_start; +wire grp_fu_123134_ap_done; +reg grp_fu_123338_ap_start; +wire grp_fu_123338_ap_done; +reg grp_fu_123526_ap_start; +wire grp_fu_123526_ap_done; +reg grp_fu_123730_ap_start; +wire grp_fu_123730_ap_done; +reg grp_fu_123930_ap_start; +wire grp_fu_123930_ap_done; +reg grp_fu_124134_ap_start; +wire grp_fu_124134_ap_done; +reg grp_fu_124667_ap_start; +wire grp_fu_124667_ap_done; +reg grp_fu_124871_ap_start; +wire grp_fu_124871_ap_done; +reg grp_fu_125083_ap_start; +wire grp_fu_125083_ap_done; +reg grp_fu_125287_ap_start; +wire grp_fu_125287_ap_done; +reg grp_fu_125476_ap_start; +wire grp_fu_125476_ap_done; +reg grp_fu_125680_ap_start; +wire grp_fu_125680_ap_done; +reg grp_fu_125881_ap_start; +wire grp_fu_125881_ap_done; +reg grp_fu_126085_ap_start; +wire grp_fu_126085_ap_done; +reg grp_fu_126293_ap_start; +wire grp_fu_126293_ap_done; +reg grp_fu_126497_ap_start; +wire grp_fu_126497_ap_done; +reg grp_fu_126708_ap_start; +wire grp_fu_126708_ap_done; +reg grp_fu_126912_ap_start; +wire grp_fu_126912_ap_done; +reg grp_fu_127100_ap_start; +wire grp_fu_127100_ap_done; +reg grp_fu_127304_ap_start; +wire grp_fu_127304_ap_done; +reg grp_fu_127504_ap_start; +wire grp_fu_127504_ap_done; +reg grp_fu_127708_ap_start; +wire grp_fu_127708_ap_done; +reg grp_fu_128135_ap_start; +wire grp_fu_128135_ap_done; +reg grp_fu_128339_ap_start; +wire grp_fu_128339_ap_done; +reg grp_fu_128551_ap_start; +wire grp_fu_128551_ap_done; +reg grp_fu_128755_ap_start; +wire grp_fu_128755_ap_done; +reg grp_fu_128944_ap_start; +wire grp_fu_128944_ap_done; +reg grp_fu_129148_ap_start; +wire grp_fu_129148_ap_done; +reg grp_fu_129349_ap_start; +wire grp_fu_129349_ap_done; +reg grp_fu_129553_ap_start; +wire grp_fu_129553_ap_done; +reg grp_fu_129761_ap_start; +wire grp_fu_129761_ap_done; +reg grp_fu_129965_ap_start; +wire grp_fu_129965_ap_done; +reg grp_fu_130176_ap_start; +wire grp_fu_130176_ap_done; +reg grp_fu_130380_ap_start; +wire grp_fu_130380_ap_done; +reg grp_fu_130568_ap_start; +wire grp_fu_130568_ap_done; +reg grp_fu_130772_ap_start; +wire grp_fu_130772_ap_done; +reg grp_fu_130972_ap_start; +wire grp_fu_130972_ap_done; +reg grp_fu_131176_ap_start; +wire grp_fu_131176_ap_done; +reg [12:0] ap_NS_fsm; +wire [64:0] grp_fu_102439_p10; +wire [64:0] grp_fu_102927_p10; +wire [64:0] grp_fu_103005_p10; +wire [64:0] grp_fu_103065_p10; +wire [64:0] grp_fu_103321_p10; +wire [64:0] grp_fu_103619_p10; +wire [64:0] grp_fu_103697_p10; +wire [64:0] grp_fu_103757_p10; +wire [64:0] grp_fu_104125_p10; +wire [64:0] grp_fu_104536_p10; +wire [64:0] grp_fu_104614_p10; +wire [64:0] grp_fu_104674_p10; +wire [64:0] grp_fu_104928_p10; +wire [64:0] grp_fu_105224_p10; +wire [64:0] grp_fu_105302_p10; +wire [64:0] grp_fu_105362_p10; +wire [64:0] grp_fu_105858_p10; +wire [64:0] grp_fu_106344_p10; +wire [64:0] grp_fu_106422_p10; +wire [64:0] grp_fu_106482_p10; +wire [64:0] grp_fu_106737_p10; +wire [64:0] grp_fu_107034_p10; +wire [64:0] grp_fu_107112_p10; +wire [64:0] grp_fu_107172_p10; +wire [64:0] grp_fu_107539_p10; +wire [64:0] grp_fu_107949_p10; +wire [64:0] grp_fu_108027_p10; +wire [64:0] grp_fu_108087_p10; +wire [64:0] grp_fu_108340_p10; +wire [64:0] grp_fu_108635_p10; +wire [64:0] grp_fu_108713_p10; +wire [64:0] grp_fu_108773_p10; +wire [64:0] grp_fu_109299_p10; +wire [64:0] grp_fu_109792_p10; +wire [64:0] grp_fu_109870_p10; +wire [64:0] grp_fu_109930_p10; +wire [64:0] grp_fu_110182_p10; +wire [64:0] grp_fu_110480_p10; +wire [64:0] grp_fu_110558_p10; +wire [64:0] grp_fu_110618_p10; +wire [64:0] grp_fu_110977_p10; +wire [64:0] grp_fu_111394_p10; +wire [64:0] grp_fu_111472_p10; +wire [64:0] grp_fu_111532_p10; +wire [64:0] grp_fu_111782_p10; +wire [64:0] grp_fu_112078_p10; +wire [64:0] grp_fu_112156_p10; +wire [64:0] grp_fu_112216_p10; +wire [64:0] grp_fu_112701_p10; +wire [64:0] grp_fu_113187_p10; +wire [64:0] grp_fu_113265_p10; +wire [64:0] grp_fu_113325_p10; +wire [64:0] grp_fu_113580_p10; +wire [64:0] grp_fu_113877_p10; +wire [64:0] grp_fu_113955_p10; +wire [64:0] grp_fu_114015_p10; +wire [64:0] grp_fu_114373_p10; +wire [64:0] grp_fu_114783_p10; +wire [64:0] grp_fu_114861_p10; +wire [64:0] grp_fu_114921_p10; +wire [64:0] grp_fu_115174_p10; +wire [64:0] grp_fu_115469_p10; +wire [64:0] grp_fu_115547_p10; +wire [64:0] grp_fu_115607_p10; +wire [64:0] grp_fu_117634_p00; +wire [64:0] grp_fu_117884_p00; +wire [64:0] grp_fu_118050_p00; +wire [64:0] grp_fu_118260_p00; +wire [64:0] grp_fu_118443_p00; +wire [64:0] grp_fu_118682_p00; +wire [64:0] grp_fu_118848_p00; +wire [64:0] grp_fu_119058_p00; +wire [64:0] grp_fu_119260_p00; +wire [64:0] grp_fu_119510_p00; +wire [64:0] grp_fu_119675_p00; +wire [64:0] grp_fu_119885_p00; +wire [64:0] grp_fu_120067_p00; +wire [64:0] grp_fu_120306_p00; +wire [64:0] grp_fu_120471_p00; +wire [64:0] grp_fu_120681_p00; +wire [64:0] grp_fu_121102_p00; +wire [64:0] grp_fu_121352_p00; +wire [64:0] grp_fu_121518_p00; +wire [64:0] grp_fu_121728_p00; +wire [64:0] grp_fu_121911_p00; +wire [64:0] grp_fu_122150_p00; +wire [64:0] grp_fu_122316_p00; +wire [64:0] grp_fu_122526_p00; +wire [64:0] grp_fu_122728_p00; +wire [64:0] grp_fu_122978_p00; +wire [64:0] grp_fu_123143_p00; +wire [64:0] grp_fu_123353_p00; +wire [64:0] grp_fu_123535_p00; +wire [64:0] grp_fu_123774_p00; +wire [64:0] grp_fu_123939_p00; +wire [64:0] grp_fu_124149_p00; +wire [64:0] grp_fu_124676_p00; +wire [64:0] grp_fu_124926_p00; +wire [64:0] grp_fu_125092_p00; +wire [64:0] grp_fu_125302_p00; +wire [64:0] grp_fu_125485_p00; +wire [64:0] grp_fu_125724_p00; +wire [64:0] grp_fu_125890_p00; +wire [64:0] grp_fu_126100_p00; +wire [64:0] grp_fu_126302_p00; +wire [64:0] grp_fu_126552_p00; +wire [64:0] grp_fu_126717_p00; +wire [64:0] grp_fu_126927_p00; +wire [64:0] grp_fu_127109_p00; +wire [64:0] grp_fu_127348_p00; +wire [64:0] grp_fu_127513_p00; +wire [64:0] grp_fu_127723_p00; +wire [64:0] grp_fu_128144_p00; +wire [64:0] grp_fu_128394_p00; +wire [64:0] grp_fu_128560_p00; +wire [64:0] grp_fu_128770_p00; +wire [64:0] grp_fu_128953_p00; +wire [64:0] grp_fu_129192_p00; +wire [64:0] grp_fu_129358_p00; +wire [64:0] grp_fu_129568_p00; +wire [64:0] grp_fu_129770_p00; +wire [64:0] grp_fu_130020_p00; +wire [64:0] grp_fu_130185_p00; +wire [64:0] grp_fu_130395_p00; +wire [64:0] grp_fu_130577_p00; +wire [64:0] grp_fu_130816_p00; +wire [64:0] grp_fu_130981_p00; +wire [64:0] grp_fu_131191_p00; +wire [8:0] grp_fu_131342_p10; +wire [7:0] grp_fu_131350_p00; +wire [8:0] grp_fu_131358_p10; +wire [7:0] grp_fu_131366_p00; +wire [8:0] grp_fu_131374_p10; +wire [7:0] grp_fu_131382_p00; +wire [8:0] grp_fu_131390_p10; +wire [7:0] grp_fu_131398_p00; +wire [15:0] grp_fu_131406_p10; +wire [11:0] grp_fu_131413_p00; +wire [15:0] grp_fu_131420_p10; +wire [8:0] grp_fu_131427_p00; +wire [11:0] grp_fu_131435_p00; +wire [7:0] grp_fu_131442_p10; +wire [8:0] grp_fu_131450_p00; +wire [7:0] grp_fu_131458_p10; +wire [11:0] grp_fu_131466_p00; +wire [8:0] grp_fu_131473_p00; +wire [11:0] grp_fu_131481_p00; +wire [7:0] grp_fu_131488_p10; +wire [8:0] grp_fu_131496_p00; +wire [7:0] grp_fu_131504_p10; +wire [15:0] grp_fu_131512_p10; +wire [11:0] grp_fu_131519_p00; +wire [15:0] grp_fu_131526_p10; +wire [8:0] grp_fu_131533_p00; +wire [11:0] grp_fu_131541_p00; +wire [7:0] grp_fu_131548_p10; +wire [8:0] grp_fu_131556_p00; +wire [7:0] grp_fu_131564_p10; +wire [11:0] grp_fu_131572_p00; +wire [8:0] grp_fu_131579_p00; +wire [11:0] grp_fu_131587_p00; +wire [7:0] grp_fu_131594_p10; +wire [8:0] grp_fu_131602_p00; +wire [7:0] grp_fu_131610_p10; +wire [18:0] mul_ln201_1_fu_101972_p00; +wire [17:0] mul_ln201_fu_101932_p00; +wire [14:0] mul_ln203_1_fu_108838_p00; +wire [14:0] mul_ln203_2_fu_102032_p00; +wire [14:0] mul_ln203_3_fu_108904_p00; +wire [14:0] mul_ln203_fu_101952_p00; +wire [12:0] mul_ln250_1_fu_115733_p00; +wire [12:0] mul_ln250_fu_115668_p00; +wire [12:0] mul_ln279_1_fu_117311_p00; +wire [17:0] mul_ln279_2_fu_117226_p00; +wire [18:0] mul_ln279_3_fu_117305_p00; +wire [12:0] mul_ln279_fu_117232_p00; +reg ap_condition_12927; +reg ap_condition_11643; +reg ap_condition_13248; +reg ap_condition_11964; +reg ap_condition_14211; +reg ap_condition_14532; +reg ap_condition_10425; +reg ap_condition_10872; +reg ap_condition_13056; +reg ap_condition_11772; +reg ap_condition_12669; +reg ap_condition_13440; +reg ap_condition_12156; +reg ap_condition_11064; +reg ap_condition_14340; +reg ap_condition_14724; +reg ap_condition_13632; +reg ap_condition_12348; +reg ap_condition_14916; +reg ap_condition_11256; +reg ap_condition_13824; +reg ap_condition_11385; +reg ap_condition_12540; +reg ap_condition_15108; +reg ap_condition_13953; +reg ap_condition_10167; +reg ap_condition_12798; +reg ap_condition_11514; +reg ap_condition_10296; +reg ap_condition_10680; +reg ap_condition_14082; +reg ap_condition_10039; +reg ap_condition_28817; +reg ap_condition_26549; +reg ap_condition_25226; +reg ap_condition_31067; +reg ap_condition_29808; +reg ap_condition_27540; +reg ap_condition_32057; +reg ap_condition_24171; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 13'd0; +end + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_w5_V #( + .DataWidth( 4 ), + .AddressRange( 1200 ), + .AddressWidth( 11 )) +w5_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(w5_V_address0), + .ce0(w5_V_ce0), + .q0(w5_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_0_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_0_V_address0), + .ce0(mult_0_V_ce0), + .we0(mult_0_V_we0), + .d0(mult_0_V_d0), + .q0(mult_0_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_1_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_1_V_address0), + .ce0(mult_1_V_ce0), + .we0(mult_1_V_we0), + .d0(mult_1_V_d0), + .q0(mult_1_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_2_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_2_V_address0), + .ce0(mult_2_V_ce0), + .we0(mult_2_V_we0), + .d0(mult_2_V_d0), + .q0(mult_2_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_3_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_3_V_address0), + .ce0(mult_3_V_ce0), + .we0(mult_3_V_we0), + .d0(mult_3_V_d0), + .q0(mult_3_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_4_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_4_V_address0), + .ce0(mult_4_V_ce0), + .we0(mult_4_V_we0), + .d0(mult_4_V_d0), + .q0(mult_4_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_5_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_5_V_address0), + .ce0(mult_5_V_ce0), + .we0(mult_5_V_we0), + .d0(mult_5_V_d0), + .q0(mult_5_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_6_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_6_V_address0), + .ce0(mult_6_V_ce0), + .we0(mult_6_V_we0), + .d0(mult_6_V_d0), + .q0(mult_6_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_7_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_7_V_address0), + .ce0(mult_7_V_ce0), + .we0(mult_7_V_we0), + .d0(mult_7_V_d0), + .q0(mult_7_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_8_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_8_V_address0), + .ce0(mult_8_V_ce0), + .we0(mult_8_V_we0), + .d0(mult_8_V_d0), + .q0(mult_8_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_9_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_9_V_address0), + .ce0(mult_9_V_ce0), + .we0(mult_9_V_we0), + .d0(mult_9_V_d0), + .q0(mult_9_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_10_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_10_V_address0), + .ce0(mult_10_V_ce0), + .we0(mult_10_V_we0), + .d0(mult_10_V_d0), + .q0(mult_10_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_11_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_11_V_address0), + .ce0(mult_11_V_ce0), + .we0(mult_11_V_we0), + .d0(mult_11_V_d0), + .q0(mult_11_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_12_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_12_V_address0), + .ce0(mult_12_V_ce0), + .we0(mult_12_V_we0), + .d0(mult_12_V_d0), + .q0(mult_12_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_13_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_13_V_address0), + .ce0(mult_13_V_ce0), + .we0(mult_13_V_we0), + .d0(mult_13_V_d0), + .q0(mult_13_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_14_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_14_V_address0), + .ce0(mult_14_V_ce0), + .we0(mult_14_V_we0), + .d0(mult_14_V_d0), + .q0(mult_14_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_15_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_15_V_address0), + .ce0(mult_15_V_ce0), + .we0(mult_15_V_we0), + .d0(mult_15_V_d0), + .q0(mult_15_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_16_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_16_V_address0), + .ce0(mult_16_V_ce0), + .we0(mult_16_V_we0), + .d0(mult_16_V_d0), + .q0(mult_16_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_17_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_17_V_address0), + .ce0(mult_17_V_ce0), + .we0(mult_17_V_we0), + .d0(mult_17_V_d0), + .q0(mult_17_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_18_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_18_V_address0), + .ce0(mult_18_V_ce0), + .we0(mult_18_V_we0), + .d0(mult_18_V_d0), + .q0(mult_18_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_19_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_19_V_address0), + .ce0(mult_19_V_ce0), + .we0(mult_19_V_we0), + .d0(mult_19_V_d0), + .q0(mult_19_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_20_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_20_V_address0), + .ce0(mult_20_V_ce0), + .we0(mult_20_V_we0), + .d0(mult_20_V_d0), + .q0(mult_20_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_21_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_21_V_address0), + .ce0(mult_21_V_ce0), + .we0(mult_21_V_we0), + .d0(mult_21_V_d0), + .q0(mult_21_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_22_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_22_V_address0), + .ce0(mult_22_V_ce0), + .we0(mult_22_V_we0), + .d0(mult_22_V_d0), + .q0(mult_22_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_23_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_23_V_address0), + .ce0(mult_23_V_ce0), + .we0(mult_23_V_we0), + .d0(mult_23_V_d0), + .q0(mult_23_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_24_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_24_V_address0), + .ce0(mult_24_V_ce0), + .we0(mult_24_V_we0), + .d0(mult_24_V_d0), + .q0(mult_24_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_25_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_25_V_address0), + .ce0(mult_25_V_ce0), + .we0(mult_25_V_we0), + .d0(mult_25_V_d0), + .q0(mult_25_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_26_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_26_V_address0), + .ce0(mult_26_V_ce0), + .we0(mult_26_V_we0), + .d0(mult_26_V_d0), + .q0(mult_26_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_mult_0_V #( + .DataWidth( 8 ), + .AddressRange( 8400 ), + .AddressWidth( 14 )) +mult_27_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_27_V_address0), + .ce0(mult_27_V_ce0), + .we0(mult_27_V_we0), + .d0(mult_27_V_d0), + .q0(mult_27_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_0_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_0_V_address0), + .ce0(acc_0_V_ce0), + .we0(acc_0_V_we0), + .d0(acc_0_V_d0), + .q0(acc_0_V_q0), + .address1(acc_0_V_address1), + .ce1(acc_0_V_ce1), + .we1(acc_0_V_we1), + .d1(acc_0_V_d1), + .q1(acc_0_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_1_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_1_V_address0), + .ce0(acc_1_V_ce0), + .we0(acc_1_V_we0), + .d0(acc_1_V_d0), + .q0(acc_1_V_q0), + .address1(acc_1_V_address1), + .ce1(acc_1_V_ce1), + .we1(acc_1_V_we1), + .d1(acc_1_V_d1), + .q1(acc_1_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_2_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_2_V_address0), + .ce0(acc_2_V_ce0), + .we0(acc_2_V_we0), + .d0(acc_2_V_d0), + .q0(acc_2_V_q0), + .address1(acc_2_V_address1), + .ce1(acc_2_V_ce1), + .we1(acc_2_V_we1), + .d1(acc_2_V_d1), + .q1(acc_2_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_3_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_3_V_address0), + .ce0(acc_3_V_ce0), + .we0(acc_3_V_we0), + .d0(acc_3_V_d0), + .q0(acc_3_V_q0), + .address1(acc_3_V_address1), + .ce1(acc_3_V_ce1), + .we1(acc_3_V_we1), + .d1(acc_3_V_d1), + .q1(acc_3_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_4_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_4_V_address0), + .ce0(acc_4_V_ce0), + .we0(acc_4_V_we0), + .d0(acc_4_V_d0), + .q0(acc_4_V_q0), + .address1(acc_4_V_address1), + .ce1(acc_4_V_ce1), + .we1(acc_4_V_we1), + .d1(acc_4_V_d1), + .q1(acc_4_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_5_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_5_V_address0), + .ce0(acc_5_V_ce0), + .we0(acc_5_V_we0), + .d0(acc_5_V_d0), + .q0(acc_5_V_q0), + .address1(acc_5_V_address1), + .ce1(acc_5_V_ce1), + .we1(acc_5_V_we1), + .d1(acc_5_V_d1), + .q1(acc_5_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_6_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_6_V_address0), + .ce0(acc_6_V_ce0), + .we0(acc_6_V_we0), + .d0(acc_6_V_d0), + .q0(acc_6_V_q0), + .address1(acc_6_V_address1), + .ce1(acc_6_V_ce1), + .we1(acc_6_V_we1), + .d1(acc_6_V_d1), + .q1(acc_6_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_7_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_7_V_address0), + .ce0(acc_7_V_ce0), + .we0(acc_7_V_we0), + .d0(acc_7_V_d0), + .q0(acc_7_V_q0), + .address1(acc_7_V_address1), + .ce1(acc_7_V_ce1), + .we1(acc_7_V_we1), + .d1(acc_7_V_d1), + .q1(acc_7_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_8_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_8_V_address0), + .ce0(acc_8_V_ce0), + .we0(acc_8_V_we0), + .d0(acc_8_V_d0), + .q0(acc_8_V_q0), + .address1(acc_8_V_address1), + .ce1(acc_8_V_ce1), + .we1(acc_8_V_we1), + .d1(acc_8_V_d1), + .q1(acc_8_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_9_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_9_V_address0), + .ce0(acc_9_V_ce0), + .we0(acc_9_V_we0), + .d0(acc_9_V_d0), + .q0(acc_9_V_q0), + .address1(acc_9_V_address1), + .ce1(acc_9_V_ce1), + .we1(acc_9_V_we1), + .d1(acc_9_V_d1), + .q1(acc_9_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_10_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_10_V_address0), + .ce0(acc_10_V_ce0), + .we0(acc_10_V_we0), + .d0(acc_10_V_d0), + .q0(acc_10_V_q0), + .address1(acc_10_V_address1), + .ce1(acc_10_V_ce1), + .we1(acc_10_V_we1), + .d1(acc_10_V_d1), + .q1(acc_10_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_11_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_11_V_address0), + .ce0(acc_11_V_ce0), + .we0(acc_11_V_we0), + .d0(acc_11_V_d0), + .q0(acc_11_V_q0), + .address1(acc_11_V_address1), + .ce1(acc_11_V_ce1), + .we1(acc_11_V_we1), + .d1(acc_11_V_d1), + .q1(acc_11_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_12_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_12_V_address0), + .ce0(acc_12_V_ce0), + .we0(acc_12_V_we0), + .d0(acc_12_V_d0), + .q0(acc_12_V_q0), + .address1(acc_12_V_address1), + .ce1(acc_12_V_ce1), + .we1(acc_12_V_we1), + .d1(acc_12_V_d1), + .q1(acc_12_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_13_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_13_V_address0), + .ce0(acc_13_V_ce0), + .we0(acc_13_V_we0), + .d0(acc_13_V_d0), + .q0(acc_13_V_q0), + .address1(acc_13_V_address1), + .ce1(acc_13_V_ce1), + .we1(acc_13_V_we1), + .d1(acc_13_V_d1), + .q1(acc_13_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_14_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_14_V_address0), + .ce0(acc_14_V_ce0), + .we0(acc_14_V_we0), + .d0(acc_14_V_d0), + .q0(acc_14_V_q0), + .address1(acc_14_V_address1), + .ce1(acc_14_V_ce1), + .we1(acc_14_V_we1), + .d1(acc_14_V_d1), + .q1(acc_14_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_15_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_15_V_address0), + .ce0(acc_15_V_ce0), + .we0(acc_15_V_we0), + .d0(acc_15_V_d0), + .q0(acc_15_V_q0), + .address1(acc_15_V_address1), + .ce1(acc_15_V_ce1), + .we1(acc_15_V_we1), + .d1(acc_15_V_d1), + .q1(acc_15_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_16_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_16_V_address0), + .ce0(acc_16_V_ce0), + .we0(acc_16_V_we0), + .d0(acc_16_V_d0), + .q0(acc_16_V_q0), + .address1(acc_16_V_address1), + .ce1(acc_16_V_ce1), + .we1(acc_16_V_we1), + .d1(acc_16_V_d1), + .q1(acc_16_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_17_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_17_V_address0), + .ce0(acc_17_V_ce0), + .we0(acc_17_V_we0), + .d0(acc_17_V_d0), + .q0(acc_17_V_q0), + .address1(acc_17_V_address1), + .ce1(acc_17_V_ce1), + .we1(acc_17_V_we1), + .d1(acc_17_V_d1), + .q1(acc_17_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_18_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_18_V_address0), + .ce0(acc_18_V_ce0), + .we0(acc_18_V_we0), + .d0(acc_18_V_d0), + .q0(acc_18_V_q0), + .address1(acc_18_V_address1), + .ce1(acc_18_V_ce1), + .we1(acc_18_V_we1), + .d1(acc_18_V_d1), + .q1(acc_18_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_19_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_19_V_address0), + .ce0(acc_19_V_ce0), + .we0(acc_19_V_we0), + .d0(acc_19_V_d0), + .q0(acc_19_V_q0), + .address1(acc_19_V_address1), + .ce1(acc_19_V_ce1), + .we1(acc_19_V_we1), + .d1(acc_19_V_d1), + .q1(acc_19_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_20_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_20_V_address0), + .ce0(acc_20_V_ce0), + .we0(acc_20_V_we0), + .d0(acc_20_V_d0), + .q0(acc_20_V_q0), + .address1(acc_20_V_address1), + .ce1(acc_20_V_ce1), + .we1(acc_20_V_we1), + .d1(acc_20_V_d1), + .q1(acc_20_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_21_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_21_V_address0), + .ce0(acc_21_V_ce0), + .we0(acc_21_V_we0), + .d0(acc_21_V_d0), + .q0(acc_21_V_q0), + .address1(acc_21_V_address1), + .ce1(acc_21_V_ce1), + .we1(acc_21_V_we1), + .d1(acc_21_V_d1), + .q1(acc_21_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_22_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_22_V_address0), + .ce0(acc_22_V_ce0), + .we0(acc_22_V_we0), + .d0(acc_22_V_d0), + .q0(acc_22_V_q0), + .address1(acc_22_V_address1), + .ce1(acc_22_V_ce1), + .we1(acc_22_V_we1), + .d1(acc_22_V_d1), + .q1(acc_22_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_23_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_23_V_address0), + .ce0(acc_23_V_ce0), + .we0(acc_23_V_we0), + .d0(acc_23_V_d0), + .q0(acc_23_V_q0), + .address1(acc_23_V_address1), + .ce1(acc_23_V_ce1), + .we1(acc_23_V_we1), + .d1(acc_23_V_d1), + .q1(acc_23_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_24_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_24_V_address0), + .ce0(acc_24_V_ce0), + .we0(acc_24_V_we0), + .d0(acc_24_V_d0), + .q0(acc_24_V_q0), + .address1(acc_24_V_address1), + .ce1(acc_24_V_ce1), + .we1(acc_24_V_we1), + .d1(acc_24_V_d1), + .q1(acc_24_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_25_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_25_V_address0), + .ce0(acc_25_V_ce0), + .we0(acc_25_V_we0), + .d0(acc_25_V_d0), + .q0(acc_25_V_q0), + .address1(acc_25_V_address1), + .ce1(acc_25_V_ce1), + .we1(acc_25_V_we1), + .d1(acc_25_V_d1), + .q1(acc_25_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_26_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_26_V_address0), + .ce0(acc_26_V_ce0), + .we0(acc_26_V_we0), + .d0(acc_26_V_d0), + .q0(acc_26_V_q0), + .address1(acc_26_V_address1), + .ce1(acc_26_V_ce1), + .we1(acc_26_V_we1), + .d1(acc_26_V_d1), + .q1(acc_26_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_27_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_27_V_address0), + .ce0(acc_27_V_ce0), + .we0(acc_27_V_we0), + .d0(acc_27_V_d0), + .q0(acc_27_V_q0), + .address1(acc_27_V_address1), + .ce1(acc_27_V_ce1), + .we1(acc_27_V_we1), + .d1(acc_27_V_d1), + .q1(acc_27_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_28_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_28_V_address0), + .ce0(acc_28_V_ce0), + .we0(acc_28_V_we0), + .d0(acc_28_V_d0), + .q0(acc_28_V_q0), + .address1(acc_28_V_address1), + .ce1(acc_28_V_ce1), + .we1(acc_28_V_we1), + .d1(acc_28_V_d1), + .q1(acc_28_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_29_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_29_V_address0), + .ce0(acc_29_V_ce0), + .we0(acc_29_V_we0), + .d0(acc_29_V_d0), + .q0(acc_29_V_q0), + .address1(acc_29_V_address1), + .ce1(acc_29_V_ce1), + .we1(acc_29_V_we1), + .d1(acc_29_V_d1), + .q1(acc_29_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_30_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_30_V_address0), + .ce0(acc_30_V_ce0), + .we0(acc_30_V_we0), + .d0(acc_30_V_d0), + .q0(acc_30_V_q0), + .address1(acc_30_V_address1), + .ce1(acc_30_V_ce1), + .we1(acc_30_V_we1), + .d1(acc_30_V_d1), + .q1(acc_30_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_31_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_31_V_address0), + .ce0(acc_31_V_ce0), + .we0(acc_31_V_we0), + .d0(acc_31_V_d0), + .q0(acc_31_V_q0), + .address1(acc_31_V_address1), + .ce1(acc_31_V_ce1), + .we1(acc_31_V_we1), + .d1(acc_31_V_d1), + .q1(acc_31_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_32_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_32_V_address0), + .ce0(acc_32_V_ce0), + .we0(acc_32_V_we0), + .d0(acc_32_V_d0), + .q0(acc_32_V_q0), + .address1(acc_32_V_address1), + .ce1(acc_32_V_ce1), + .we1(acc_32_V_we1), + .d1(acc_32_V_d1), + .q1(acc_32_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_33_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_33_V_address0), + .ce0(acc_33_V_ce0), + .we0(acc_33_V_we0), + .d0(acc_33_V_d0), + .q0(acc_33_V_q0), + .address1(acc_33_V_address1), + .ce1(acc_33_V_ce1), + .we1(acc_33_V_we1), + .d1(acc_33_V_d1), + .q1(acc_33_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_34_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_34_V_address0), + .ce0(acc_34_V_ce0), + .we0(acc_34_V_we0), + .d0(acc_34_V_d0), + .q0(acc_34_V_q0), + .address1(acc_34_V_address1), + .ce1(acc_34_V_ce1), + .we1(acc_34_V_we1), + .d1(acc_34_V_d1), + .q1(acc_34_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_35_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_35_V_address0), + .ce0(acc_35_V_ce0), + .we0(acc_35_V_we0), + .d0(acc_35_V_d0), + .q0(acc_35_V_q0), + .address1(acc_35_V_address1), + .ce1(acc_35_V_ce1), + .we1(acc_35_V_we1), + .d1(acc_35_V_d1), + .q1(acc_35_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_36_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_36_V_address0), + .ce0(acc_36_V_ce0), + .we0(acc_36_V_we0), + .d0(acc_36_V_d0), + .q0(acc_36_V_q0), + .address1(acc_36_V_address1), + .ce1(acc_36_V_ce1), + .we1(acc_36_V_we1), + .d1(acc_36_V_d1), + .q1(acc_36_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_37_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_37_V_address0), + .ce0(acc_37_V_ce0), + .we0(acc_37_V_we0), + .d0(acc_37_V_d0), + .q0(acc_37_V_q0), + .address1(acc_37_V_address1), + .ce1(acc_37_V_ce1), + .we1(acc_37_V_we1), + .d1(acc_37_V_d1), + .q1(acc_37_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_38_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_38_V_address0), + .ce0(acc_38_V_ce0), + .we0(acc_38_V_we0), + .d0(acc_38_V_d0), + .q0(acc_38_V_q0), + .address1(acc_38_V_address1), + .ce1(acc_38_V_ce1), + .we1(acc_38_V_we1), + .d1(acc_38_V_d1), + .q1(acc_38_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_39_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_39_V_address0), + .ce0(acc_39_V_ce0), + .we0(acc_39_V_we0), + .d0(acc_39_V_d0), + .q0(acc_39_V_q0), + .address1(acc_39_V_address1), + .ce1(acc_39_V_ce1), + .we1(acc_39_V_we1), + .d1(acc_39_V_d1), + .q1(acc_39_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_40_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_40_V_address0), + .ce0(acc_40_V_ce0), + .we0(acc_40_V_we0), + .d0(acc_40_V_d0), + .q0(acc_40_V_q0), + .address1(acc_40_V_address1), + .ce1(acc_40_V_ce1), + .we1(acc_40_V_we1), + .d1(acc_40_V_d1), + .q1(acc_40_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_41_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_41_V_address0), + .ce0(acc_41_V_ce0), + .we0(acc_41_V_we0), + .d0(acc_41_V_d0), + .q0(acc_41_V_q0), + .address1(acc_41_V_address1), + .ce1(acc_41_V_ce1), + .we1(acc_41_V_we1), + .d1(acc_41_V_d1), + .q1(acc_41_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_42_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_42_V_address0), + .ce0(acc_42_V_ce0), + .we0(acc_42_V_we0), + .d0(acc_42_V_d0), + .q0(acc_42_V_q0), + .address1(acc_42_V_address1), + .ce1(acc_42_V_ce1), + .we1(acc_42_V_we1), + .d1(acc_42_V_d1), + .q1(acc_42_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_43_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_43_V_address0), + .ce0(acc_43_V_ce0), + .we0(acc_43_V_we0), + .d0(acc_43_V_d0), + .q0(acc_43_V_q0), + .address1(acc_43_V_address1), + .ce1(acc_43_V_ce1), + .we1(acc_43_V_we1), + .d1(acc_43_V_d1), + .q1(acc_43_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_44_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_44_V_address0), + .ce0(acc_44_V_ce0), + .we0(acc_44_V_we0), + .d0(acc_44_V_d0), + .q0(acc_44_V_q0), + .address1(acc_44_V_address1), + .ce1(acc_44_V_ce1), + .we1(acc_44_V_we1), + .d1(acc_44_V_d1), + .q1(acc_44_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_45_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_45_V_address0), + .ce0(acc_45_V_ce0), + .we0(acc_45_V_we0), + .d0(acc_45_V_d0), + .q0(acc_45_V_q0), + .address1(acc_45_V_address1), + .ce1(acc_45_V_ce1), + .we1(acc_45_V_we1), + .d1(acc_45_V_d1), + .q1(acc_45_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_46_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_46_V_address0), + .ce0(acc_46_V_ce0), + .we0(acc_46_V_we0), + .d0(acc_46_V_d0), + .q0(acc_46_V_q0), + .address1(acc_46_V_address1), + .ce1(acc_46_V_ce1), + .we1(acc_46_V_we1), + .d1(acc_46_V_d1), + .q1(acc_46_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_0_V #( + .DataWidth( 8 ), + .AddressRange( 37 ), + .AddressWidth( 6 )) +acc_47_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_47_V_address0), + .ce0(acc_47_V_ce0), + .we0(acc_47_V_we0), + .d0(acc_47_V_d0), + .q0(acc_47_V_q0), + .address1(acc_47_V_address1), + .ce1(acc_47_V_ce1), + .we1(acc_47_V_we1), + .d1(acc_47_V_d1), + .q1(acc_47_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_48_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_48_V_address0), + .ce0(acc_48_V_ce0), + .we0(acc_48_V_we0), + .d0(acc_48_V_d0), + .q0(acc_48_V_q0), + .address1(acc_48_V_address1), + .ce1(acc_48_V_ce1), + .we1(acc_48_V_we1), + .d1(acc_48_V_d1), + .q1(acc_48_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_49_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_49_V_address0), + .ce0(acc_49_V_ce0), + .we0(acc_49_V_we0), + .d0(acc_49_V_d0), + .q0(acc_49_V_q0), + .address1(acc_49_V_address1), + .ce1(acc_49_V_ce1), + .we1(acc_49_V_we1), + .d1(acc_49_V_d1), + .q1(acc_49_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_50_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_50_V_address0), + .ce0(acc_50_V_ce0), + .we0(acc_50_V_we0), + .d0(acc_50_V_d0), + .q0(acc_50_V_q0), + .address1(acc_50_V_address1), + .ce1(acc_50_V_ce1), + .we1(acc_50_V_we1), + .d1(acc_50_V_d1), + .q1(acc_50_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_51_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_51_V_address0), + .ce0(acc_51_V_ce0), + .we0(acc_51_V_we0), + .d0(acc_51_V_d0), + .q0(acc_51_V_q0), + .address1(acc_51_V_address1), + .ce1(acc_51_V_ce1), + .we1(acc_51_V_we1), + .d1(acc_51_V_d1), + .q1(acc_51_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_52_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_52_V_address0), + .ce0(acc_52_V_ce0), + .we0(acc_52_V_we0), + .d0(acc_52_V_d0), + .q0(acc_52_V_q0), + .address1(acc_52_V_address1), + .ce1(acc_52_V_ce1), + .we1(acc_52_V_we1), + .d1(acc_52_V_d1), + .q1(acc_52_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_53_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_53_V_address0), + .ce0(acc_53_V_ce0), + .we0(acc_53_V_we0), + .d0(acc_53_V_d0), + .q0(acc_53_V_q0), + .address1(acc_53_V_address1), + .ce1(acc_53_V_ce1), + .we1(acc_53_V_we1), + .d1(acc_53_V_d1), + .q1(acc_53_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_54_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_54_V_address0), + .ce0(acc_54_V_ce0), + .we0(acc_54_V_we0), + .d0(acc_54_V_d0), + .q0(acc_54_V_q0), + .address1(acc_54_V_address1), + .ce1(acc_54_V_ce1), + .we1(acc_54_V_we1), + .d1(acc_54_V_d1), + .q1(acc_54_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_55_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_55_V_address0), + .ce0(acc_55_V_ce0), + .we0(acc_55_V_we0), + .d0(acc_55_V_d0), + .q0(acc_55_V_q0), + .address1(acc_55_V_address1), + .ce1(acc_55_V_ce1), + .we1(acc_55_V_we1), + .d1(acc_55_V_d1), + .q1(acc_55_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_56_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_56_V_address0), + .ce0(acc_56_V_ce0), + .we0(acc_56_V_we0), + .d0(acc_56_V_d0), + .q0(acc_56_V_q0), + .address1(acc_56_V_address1), + .ce1(acc_56_V_ce1), + .we1(acc_56_V_we1), + .d1(acc_56_V_d1), + .q1(acc_56_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_57_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_57_V_address0), + .ce0(acc_57_V_ce0), + .we0(acc_57_V_we0), + .d0(acc_57_V_d0), + .q0(acc_57_V_q0), + .address1(acc_57_V_address1), + .ce1(acc_57_V_ce1), + .we1(acc_57_V_we1), + .d1(acc_57_V_d1), + .q1(acc_57_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_58_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_58_V_address0), + .ce0(acc_58_V_ce0), + .we0(acc_58_V_we0), + .d0(acc_58_V_d0), + .q0(acc_58_V_q0), + .address1(acc_58_V_address1), + .ce1(acc_58_V_ce1), + .we1(acc_58_V_we1), + .d1(acc_58_V_d1), + .q1(acc_58_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_59_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_59_V_address0), + .ce0(acc_59_V_ce0), + .we0(acc_59_V_we0), + .d0(acc_59_V_d0), + .q0(acc_59_V_q0), + .address1(acc_59_V_address1), + .ce1(acc_59_V_ce1), + .we1(acc_59_V_we1), + .d1(acc_59_V_d1), + .q1(acc_59_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_60_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_60_V_address0), + .ce0(acc_60_V_ce0), + .we0(acc_60_V_we0), + .d0(acc_60_V_d0), + .q0(acc_60_V_q0), + .address1(acc_60_V_address1), + .ce1(acc_60_V_ce1), + .we1(acc_60_V_we1), + .d1(acc_60_V_d1), + .q1(acc_60_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_61_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_61_V_address0), + .ce0(acc_61_V_ce0), + .we0(acc_61_V_we0), + .d0(acc_61_V_d0), + .q0(acc_61_V_q0), + .address1(acc_61_V_address1), + .ce1(acc_61_V_ce1), + .we1(acc_61_V_we1), + .d1(acc_61_V_d1), + .q1(acc_61_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_62_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_62_V_address0), + .ce0(acc_62_V_ce0), + .we0(acc_62_V_we0), + .d0(acc_62_V_d0), + .q0(acc_62_V_q0), + .address1(acc_62_V_address1), + .ce1(acc_62_V_ce1), + .we1(acc_62_V_we1), + .d1(acc_62_V_d1), + .q1(acc_62_V_q1) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_acc_48_V #( + .DataWidth( 8 ), + .AddressRange( 36 ), + .AddressWidth( 6 )) +acc_63_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_63_V_address0), + .ce0(acc_63_V_ce0), + .we0(acc_63_V_we0), + .d0(acc_63_V_d0), + .q0(acc_63_V_q0), + .address1(acc_63_V_address1), + .ce1(acc_63_V_ce1), + .we1(acc_63_V_we1), + .d1(acc_63_V_d1), + .q1(acc_63_V_q1) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U576( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99047_ap_start), + .done(grp_fu_99047_ap_done), + .din0(grp_fu_99047_p0), + .din1(grp_fu_99047_p1), + .ce(1'b1), + .dout(grp_fu_99047_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U577( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99053_ap_start), + .done(grp_fu_99053_ap_done), + .din0(grp_fu_99053_p0), + .din1(grp_fu_99053_p1), + .ce(1'b1), + .dout(grp_fu_99053_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U578( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99064_ap_start), + .done(grp_fu_99064_ap_done), + .din0(grp_fu_99064_p0), + .din1(grp_fu_99064_p1), + .ce(1'b1), + .dout(grp_fu_99064_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U579( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99070_ap_start), + .done(grp_fu_99070_ap_done), + .din0(grp_fu_99070_p0), + .din1(grp_fu_99070_p1), + .ce(1'b1), + .dout(grp_fu_99070_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U580( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99081_ap_start), + .done(grp_fu_99081_ap_done), + .din0(grp_fu_99081_p0), + .din1(grp_fu_99081_p1), + .ce(1'b1), + .dout(grp_fu_99081_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U581( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99087_ap_start), + .done(grp_fu_99087_ap_done), + .din0(grp_fu_99087_p0), + .din1(grp_fu_99087_p1), + .ce(1'b1), + .dout(grp_fu_99087_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U582( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99098_ap_start), + .done(grp_fu_99098_ap_done), + .din0(grp_fu_99098_p0), + .din1(grp_fu_99098_p1), + .ce(1'b1), + .dout(grp_fu_99098_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U583( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99104_ap_start), + .done(grp_fu_99104_ap_done), + .din0(grp_fu_99104_p0), + .din1(grp_fu_99104_p1), + .ce(1'b1), + .dout(grp_fu_99104_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U584( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99115_ap_start), + .done(grp_fu_99115_ap_done), + .din0(grp_fu_99115_p0), + .din1(grp_fu_99115_p1), + .ce(1'b1), + .dout(grp_fu_99115_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U585( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99121_ap_start), + .done(grp_fu_99121_ap_done), + .din0(grp_fu_99121_p0), + .din1(grp_fu_99121_p1), + .ce(1'b1), + .dout(grp_fu_99121_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U586( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99132_ap_start), + .done(grp_fu_99132_ap_done), + .din0(grp_fu_99132_p0), + .din1(grp_fu_99132_p1), + .ce(1'b1), + .dout(grp_fu_99132_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U587( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99138_ap_start), + .done(grp_fu_99138_ap_done), + .din0(grp_fu_99138_p0), + .din1(grp_fu_99138_p1), + .ce(1'b1), + .dout(grp_fu_99138_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U588( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99149_ap_start), + .done(grp_fu_99149_ap_done), + .din0(grp_fu_99149_p0), + .din1(grp_fu_99149_p1), + .ce(1'b1), + .dout(grp_fu_99149_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U589( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99155_ap_start), + .done(grp_fu_99155_ap_done), + .din0(grp_fu_99155_p0), + .din1(grp_fu_99155_p1), + .ce(1'b1), + .dout(grp_fu_99155_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U590( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99166_ap_start), + .done(grp_fu_99166_ap_done), + .din0(grp_fu_99166_p0), + .din1(grp_fu_99166_p1), + .ce(1'b1), + .dout(grp_fu_99166_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U591( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99172_ap_start), + .done(grp_fu_99172_ap_done), + .din0(grp_fu_99172_p0), + .din1(grp_fu_99172_p1), + .ce(1'b1), + .dout(grp_fu_99172_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U592( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99183_ap_start), + .done(grp_fu_99183_ap_done), + .din0(grp_fu_99183_p0), + .din1(grp_fu_99183_p1), + .ce(1'b1), + .dout(grp_fu_99183_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U593( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99189_ap_start), + .done(grp_fu_99189_ap_done), + .din0(grp_fu_99189_p0), + .din1(grp_fu_99189_p1), + .ce(1'b1), + .dout(grp_fu_99189_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U594( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99200_ap_start), + .done(grp_fu_99200_ap_done), + .din0(grp_fu_99200_p0), + .din1(grp_fu_99200_p1), + .ce(1'b1), + .dout(grp_fu_99200_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U595( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99206_ap_start), + .done(grp_fu_99206_ap_done), + .din0(grp_fu_99206_p0), + .din1(grp_fu_99206_p1), + .ce(1'b1), + .dout(grp_fu_99206_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U596( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99217_ap_start), + .done(grp_fu_99217_ap_done), + .din0(grp_fu_99217_p0), + .din1(grp_fu_99217_p1), + .ce(1'b1), + .dout(grp_fu_99217_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U597( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99223_ap_start), + .done(grp_fu_99223_ap_done), + .din0(grp_fu_99223_p0), + .din1(grp_fu_99223_p1), + .ce(1'b1), + .dout(grp_fu_99223_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U598( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99234_ap_start), + .done(grp_fu_99234_ap_done), + .din0(grp_fu_99234_p0), + .din1(grp_fu_99234_p1), + .ce(1'b1), + .dout(grp_fu_99234_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U599( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99240_ap_start), + .done(grp_fu_99240_ap_done), + .din0(grp_fu_99240_p0), + .din1(grp_fu_99240_p1), + .ce(1'b1), + .dout(grp_fu_99240_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U600( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99251_ap_start), + .done(grp_fu_99251_ap_done), + .din0(grp_fu_99251_p0), + .din1(grp_fu_99251_p1), + .ce(1'b1), + .dout(grp_fu_99251_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U601( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99257_ap_start), + .done(grp_fu_99257_ap_done), + .din0(grp_fu_99257_p0), + .din1(grp_fu_99257_p1), + .ce(1'b1), + .dout(grp_fu_99257_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U602( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99268_ap_start), + .done(grp_fu_99268_ap_done), + .din0(grp_fu_99268_p0), + .din1(grp_fu_99268_p1), + .ce(1'b1), + .dout(grp_fu_99268_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U603( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99274_ap_start), + .done(grp_fu_99274_ap_done), + .din0(grp_fu_99274_p0), + .din1(grp_fu_99274_p1), + .ce(1'b1), + .dout(grp_fu_99274_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U604( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99285_ap_start), + .done(grp_fu_99285_ap_done), + .din0(grp_fu_99285_p0), + .din1(grp_fu_99285_p1), + .ce(1'b1), + .dout(grp_fu_99285_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U605( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99291_ap_start), + .done(grp_fu_99291_ap_done), + .din0(grp_fu_99291_p0), + .din1(grp_fu_99291_p1), + .ce(1'b1), + .dout(grp_fu_99291_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U606( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99302_ap_start), + .done(grp_fu_99302_ap_done), + .din0(grp_fu_99302_p0), + .din1(grp_fu_99302_p1), + .ce(1'b1), + .dout(grp_fu_99302_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U607( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_99308_ap_start), + .done(grp_fu_99308_ap_done), + .din0(grp_fu_99308_p0), + .din1(grp_fu_99308_p1), + .ce(1'b1), + .dout(grp_fu_99308_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U608( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_102439_p0), + .din1(grp_fu_102439_p1), + .ce(1'b1), + .dout(grp_fu_102439_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U609( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_102927_p0), + .din1(grp_fu_102927_p1), + .ce(1'b1), + .dout(grp_fu_102927_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U610( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_103005_p0), + .din1(grp_fu_103005_p1), + .ce(1'b1), + .dout(grp_fu_103005_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U611( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_103065_p0), + .din1(grp_fu_103065_p1), + .ce(1'b1), + .dout(grp_fu_103065_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U612( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_103321_p0), + .din1(grp_fu_103321_p1), + .ce(1'b1), + .dout(grp_fu_103321_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U613( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_103619_p0), + .din1(grp_fu_103619_p1), + .ce(1'b1), + .dout(grp_fu_103619_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U614( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_103697_p0), + .din1(grp_fu_103697_p1), + .ce(1'b1), + .dout(grp_fu_103697_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U615( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_103757_p0), + .din1(grp_fu_103757_p1), + .ce(1'b1), + .dout(grp_fu_103757_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U616( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_104125_p0), + .din1(grp_fu_104125_p1), + .ce(1'b1), + .dout(grp_fu_104125_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U617( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_104536_p0), + .din1(grp_fu_104536_p1), + .ce(1'b1), + .dout(grp_fu_104536_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U618( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_104614_p0), + .din1(grp_fu_104614_p1), + .ce(1'b1), + .dout(grp_fu_104614_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U619( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_104674_p0), + .din1(grp_fu_104674_p1), + .ce(1'b1), + .dout(grp_fu_104674_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U620( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_104928_p0), + .din1(grp_fu_104928_p1), + .ce(1'b1), + .dout(grp_fu_104928_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U621( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_105224_p0), + .din1(grp_fu_105224_p1), + .ce(1'b1), + .dout(grp_fu_105224_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U622( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_105302_p0), + .din1(grp_fu_105302_p1), + .ce(1'b1), + .dout(grp_fu_105302_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U623( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_105362_p0), + .din1(grp_fu_105362_p1), + .ce(1'b1), + .dout(grp_fu_105362_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U624( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_105858_p0), + .din1(grp_fu_105858_p1), + .ce(1'b1), + .dout(grp_fu_105858_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U625( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_106344_p0), + .din1(grp_fu_106344_p1), + .ce(1'b1), + .dout(grp_fu_106344_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U626( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_106422_p0), + .din1(grp_fu_106422_p1), + .ce(1'b1), + .dout(grp_fu_106422_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U627( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_106482_p0), + .din1(grp_fu_106482_p1), + .ce(1'b1), + .dout(grp_fu_106482_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U628( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_106737_p0), + .din1(grp_fu_106737_p1), + .ce(1'b1), + .dout(grp_fu_106737_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U629( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_107034_p0), + .din1(grp_fu_107034_p1), + .ce(1'b1), + .dout(grp_fu_107034_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U630( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_107112_p0), + .din1(grp_fu_107112_p1), + .ce(1'b1), + .dout(grp_fu_107112_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U631( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_107172_p0), + .din1(grp_fu_107172_p1), + .ce(1'b1), + .dout(grp_fu_107172_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U632( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_107539_p0), + .din1(grp_fu_107539_p1), + .ce(1'b1), + .dout(grp_fu_107539_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U633( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_107949_p0), + .din1(grp_fu_107949_p1), + .ce(1'b1), + .dout(grp_fu_107949_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U634( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_108027_p0), + .din1(grp_fu_108027_p1), + .ce(1'b1), + .dout(grp_fu_108027_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U635( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_108087_p0), + .din1(grp_fu_108087_p1), + .ce(1'b1), + .dout(grp_fu_108087_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U636( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_108340_p0), + .din1(grp_fu_108340_p1), + .ce(1'b1), + .dout(grp_fu_108340_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U637( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_108635_p0), + .din1(grp_fu_108635_p1), + .ce(1'b1), + .dout(grp_fu_108635_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U638( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_108713_p0), + .din1(grp_fu_108713_p1), + .ce(1'b1), + .dout(grp_fu_108713_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U639( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_108773_p0), + .din1(grp_fu_108773_p1), + .ce(1'b1), + .dout(grp_fu_108773_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U640( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_109299_p0), + .din1(grp_fu_109299_p1), + .ce(1'b1), + .dout(grp_fu_109299_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U641( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_109792_p0), + .din1(grp_fu_109792_p1), + .ce(1'b1), + .dout(grp_fu_109792_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U642( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_109870_p0), + .din1(grp_fu_109870_p1), + .ce(1'b1), + .dout(grp_fu_109870_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U643( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_109930_p0), + .din1(grp_fu_109930_p1), + .ce(1'b1), + .dout(grp_fu_109930_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U644( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_110182_p0), + .din1(grp_fu_110182_p1), + .ce(1'b1), + .dout(grp_fu_110182_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U645( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_110480_p0), + .din1(grp_fu_110480_p1), + .ce(1'b1), + .dout(grp_fu_110480_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U646( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_110558_p0), + .din1(grp_fu_110558_p1), + .ce(1'b1), + .dout(grp_fu_110558_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U647( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_110618_p0), + .din1(grp_fu_110618_p1), + .ce(1'b1), + .dout(grp_fu_110618_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U648( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_110977_p0), + .din1(grp_fu_110977_p1), + .ce(1'b1), + .dout(grp_fu_110977_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U649( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_111394_p0), + .din1(grp_fu_111394_p1), + .ce(1'b1), + .dout(grp_fu_111394_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U650( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_111472_p0), + .din1(grp_fu_111472_p1), + .ce(1'b1), + .dout(grp_fu_111472_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U651( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_111532_p0), + .din1(grp_fu_111532_p1), + .ce(1'b1), + .dout(grp_fu_111532_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U652( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_111782_p0), + .din1(grp_fu_111782_p1), + .ce(1'b1), + .dout(grp_fu_111782_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U653( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_112078_p0), + .din1(grp_fu_112078_p1), + .ce(1'b1), + .dout(grp_fu_112078_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U654( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_112156_p0), + .din1(grp_fu_112156_p1), + .ce(1'b1), + .dout(grp_fu_112156_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U655( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_112216_p0), + .din1(grp_fu_112216_p1), + .ce(1'b1), + .dout(grp_fu_112216_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U656( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_112701_p0), + .din1(grp_fu_112701_p1), + .ce(1'b1), + .dout(grp_fu_112701_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U657( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_113187_p0), + .din1(grp_fu_113187_p1), + .ce(1'b1), + .dout(grp_fu_113187_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U658( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_113265_p0), + .din1(grp_fu_113265_p1), + .ce(1'b1), + .dout(grp_fu_113265_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U659( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_113325_p0), + .din1(grp_fu_113325_p1), + .ce(1'b1), + .dout(grp_fu_113325_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U660( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_113580_p0), + .din1(grp_fu_113580_p1), + .ce(1'b1), + .dout(grp_fu_113580_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U661( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_113877_p0), + .din1(grp_fu_113877_p1), + .ce(1'b1), + .dout(grp_fu_113877_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U662( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_113955_p0), + .din1(grp_fu_113955_p1), + .ce(1'b1), + .dout(grp_fu_113955_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U663( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_114015_p0), + .din1(grp_fu_114015_p1), + .ce(1'b1), + .dout(grp_fu_114015_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U664( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_114373_p0), + .din1(grp_fu_114373_p1), + .ce(1'b1), + .dout(grp_fu_114373_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U665( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_114783_p0), + .din1(grp_fu_114783_p1), + .ce(1'b1), + .dout(grp_fu_114783_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U666( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_114861_p0), + .din1(grp_fu_114861_p1), + .ce(1'b1), + .dout(grp_fu_114861_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U667( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_114921_p0), + .din1(grp_fu_114921_p1), + .ce(1'b1), + .dout(grp_fu_114921_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U668( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_115174_p0), + .din1(grp_fu_115174_p1), + .ce(1'b1), + .dout(grp_fu_115174_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U669( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_115469_p0), + .din1(grp_fu_115469_p1), + .ce(1'b1), + .dout(grp_fu_115469_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U670( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_115547_p0), + .din1(grp_fu_115547_p1), + .ce(1'b1), + .dout(grp_fu_115547_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U671( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_115607_p0), + .din1(grp_fu_115607_p1), + .ce(1'b1), + .dout(grp_fu_115607_p2) +); + +myproject_mux_164_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 4 ), + .dout_WIDTH( 8 )) +myproject_mux_164_8_1_1_U672( + .din0(8'd1), + .din1(8'd255), + .din2(8'd255), + .din3(8'd255), + .din4(8'd255), + .din5(8'd255), + .din6(8'd0), + .din7(8'd255), + .din8(8'd0), + .din9(8'd255), + .din10(8'd255), + .din11(8'd255), + .din12(8'd255), + .din13(8'd255), + .din14(8'd255), + .din15(8'd255), + .din16(ff4_0_0_0_0_reg_95953), + .dout(phi_ln_fu_115758_p18) +); + +myproject_mux_164_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 4 ), + .dout_WIDTH( 8 )) +myproject_mux_164_8_1_1_U673( + .din0(8'd0), + .din1(8'd255), + .din2(8'd0), + .din3(8'd0), + .din4(8'd0), + .din5(8'd255), + .din6(8'd0), + .din7(8'd255), + .din8(8'd0), + .din9(8'd254), + .din10(8'd0), + .din11(8'd0), + .din12(8'd0), + .din13(8'd0), + .din14(8'd0), + .din15(8'd0), + .din16(or_ln248_fu_115934_p2), + .dout(phi_ln203_4_fu_115953_p18) +); + +myproject_mux_164_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 4 ), + .dout_WIDTH( 8 )) +myproject_mux_164_8_1_1_U674( + .din0(8'd1), + .din1(8'd255), + .din2(8'd255), + .din3(8'd255), + .din4(8'd255), + .din5(8'd255), + .din6(8'd0), + .din7(8'd255), + .din8(8'd0), + .din9(8'd255), + .din10(8'd255), + .din11(8'd255), + .din12(8'd255), + .din13(8'd255), + .din14(8'd255), + .din15(8'd255), + .din16(ff4_0_0_1_0_reg_95965), + .dout(phi_ln203_2_fu_116134_p18) +); + +myproject_mux_164_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 4 ), + .dout_WIDTH( 8 )) +myproject_mux_164_8_1_1_U675( + .din0(8'd0), + .din1(8'd255), + .din2(8'd0), + .din3(8'd0), + .din4(8'd0), + .din5(8'd255), + .din6(8'd0), + .din7(8'd255), + .din8(8'd0), + .din9(8'd254), + .din10(8'd0), + .din11(8'd0), + .din12(8'd0), + .din13(8'd0), + .din14(8'd0), + .din15(8'd0), + .din16(or_ln248_2_fu_116267_p2), + .dout(phi_ln203_6_fu_116286_p18) +); + +myproject_mux_164_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 4 ), + .dout_WIDTH( 8 )) +myproject_mux_164_8_1_1_U676( + .din0(8'd1), + .din1(8'd255), + .din2(8'd255), + .din3(8'd255), + .din4(8'd255), + .din5(8'd255), + .din6(8'd0), + .din7(8'd255), + .din8(8'd0), + .din9(8'd255), + .din10(8'd255), + .din11(8'd255), + .din12(8'd255), + .din13(8'd255), + .din14(8'd255), + .din15(8'd255), + .din16(ff4_0_1_0_0_reg_95989), + .dout(phi_ln203_1_fu_116522_p18) +); + +myproject_mux_164_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 4 ), + .dout_WIDTH( 8 )) +myproject_mux_164_8_1_1_U677( + .din0(8'd0), + .din1(8'd255), + .din2(8'd0), + .din3(8'd0), + .din4(8'd0), + .din5(8'd255), + .din6(8'd0), + .din7(8'd255), + .din8(8'd0), + .din9(8'd254), + .din10(8'd0), + .din11(8'd0), + .din12(8'd0), + .din13(8'd0), + .din14(8'd0), + .din15(8'd0), + .din16(or_ln248_1_fu_116698_p2), + .dout(phi_ln203_5_fu_116717_p18) +); + +myproject_mux_164_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 4 ), + .dout_WIDTH( 8 )) +myproject_mux_164_8_1_1_U678( + .din0(8'd1), + .din1(8'd255), + .din2(8'd255), + .din3(8'd255), + .din4(8'd255), + .din5(8'd255), + .din6(8'd0), + .din7(8'd255), + .din8(8'd0), + .din9(8'd255), + .din10(8'd255), + .din11(8'd255), + .din12(8'd255), + .din13(8'd255), + .din14(8'd255), + .din15(8'd255), + .din16(ff4_0_1_1_0_reg_96001), + .dout(phi_ln203_3_fu_116898_p18) +); + +myproject_mux_164_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 4 ), + .dout_WIDTH( 8 )) +myproject_mux_164_8_1_1_U679( + .din0(8'd0), + .din1(8'd255), + .din2(8'd0), + .din3(8'd0), + .din4(8'd0), + .din5(8'd255), + .din6(8'd0), + .din7(8'd255), + .din8(8'd0), + .din9(8'd254), + .din10(8'd0), + .din11(8'd0), + .din12(8'd0), + .din13(8'd0), + .din14(8'd0), + .din15(8'd0), + .din16(or_ln248_3_fu_117031_p2), + .dout(phi_ln203_7_fu_117050_p18) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U680( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_117625_ap_start), + .done(grp_fu_117625_ap_done), + .din0(grp_fu_117625_p0), + .din1(grp_fu_117625_p1), + .ce(1'b1), + .dout(grp_fu_117625_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U681( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_117634_p0), + .din1(grp_fu_117634_p1), + .ce(1'b1), + .dout(grp_fu_117634_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U682( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_117625_p2), + .dout(tmp_6_fu_117681_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U683( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_117829_ap_start), + .done(grp_fu_117829_ap_done), + .din0(grp_fu_117829_p0), + .din1(grp_fu_117829_p1), + .ce(1'b1), + .dout(grp_fu_117829_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U684( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_117884_p0), + .din1(grp_fu_117884_p1), + .ce(1'b1), + .dout(grp_fu_117884_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U685( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_117829_p2), + .dout(tmp_10_fu_117931_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U686( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_118041_ap_start), + .done(grp_fu_118041_ap_done), + .din0(grp_fu_118041_p0), + .din1(grp_fu_118041_p1), + .ce(1'b1), + .dout(grp_fu_118041_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U687( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_118050_p0), + .din1(grp_fu_118050_p1), + .ce(1'b1), + .dout(grp_fu_118050_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U688( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_118041_p2), + .dout(tmp_96_fu_118097_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U689( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_118245_ap_start), + .done(grp_fu_118245_ap_done), + .din0(grp_fu_118245_p0), + .din1(grp_fu_118245_p1), + .ce(1'b1), + .dout(grp_fu_118245_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U690( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_118260_p0), + .din1(grp_fu_118260_p1), + .ce(1'b1), + .dout(grp_fu_118260_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U691( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_118245_p2), + .dout(tmp_119_fu_118307_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U692( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_118434_ap_start), + .done(grp_fu_118434_ap_done), + .din0(grp_fu_118434_p0), + .din1(grp_fu_118434_p1), + .ce(1'b1), + .dout(grp_fu_118434_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U693( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_118443_p0), + .din1(grp_fu_118443_p1), + .ce(1'b1), + .dout(grp_fu_118443_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U694( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_118434_p2), + .dout(tmp_105_fu_118490_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U695( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_118638_ap_start), + .done(grp_fu_118638_ap_done), + .din0(grp_fu_118638_p0), + .din1(grp_fu_118638_p1), + .ce(1'b1), + .dout(grp_fu_118638_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U696( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_118682_p0), + .din1(grp_fu_118682_p1), + .ce(1'b1), + .dout(grp_fu_118682_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U697( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_118638_p2), + .dout(tmp_124_fu_118729_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U698( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_118839_ap_start), + .done(grp_fu_118839_ap_done), + .din0(grp_fu_118839_p0), + .din1(grp_fu_118839_p1), + .ce(1'b1), + .dout(grp_fu_118839_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U699( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_118848_p0), + .din1(grp_fu_118848_p1), + .ce(1'b1), + .dout(grp_fu_118848_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U700( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_118839_p2), + .dout(tmp_147_fu_118895_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U701( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_119043_ap_start), + .done(grp_fu_119043_ap_done), + .din0(grp_fu_119043_p0), + .din1(grp_fu_119043_p1), + .ce(1'b1), + .dout(grp_fu_119043_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U702( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_119058_p0), + .din1(grp_fu_119058_p1), + .ce(1'b1), + .dout(grp_fu_119058_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U703( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_119043_p2), + .dout(tmp_159_fu_119105_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U704( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_119251_ap_start), + .done(grp_fu_119251_ap_done), + .din0(grp_fu_119251_p0), + .din1(grp_fu_119251_p1), + .ce(1'b1), + .dout(grp_fu_119251_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U705( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_119260_p0), + .din1(grp_fu_119260_p1), + .ce(1'b1), + .dout(grp_fu_119260_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U706( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_119251_p2), + .dout(tmp_9_fu_119307_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U707( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_119455_ap_start), + .done(grp_fu_119455_ap_done), + .din0(grp_fu_119455_p0), + .din1(grp_fu_119455_p1), + .ce(1'b1), + .dout(grp_fu_119455_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U708( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_119510_p0), + .din1(grp_fu_119510_p1), + .ce(1'b1), + .dout(grp_fu_119510_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U709( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_119455_p2), + .dout(tmp_74_fu_119557_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U710( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_119666_ap_start), + .done(grp_fu_119666_ap_done), + .din0(grp_fu_119666_p0), + .din1(grp_fu_119666_p1), + .ce(1'b1), + .dout(grp_fu_119666_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U711( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_119675_p0), + .din1(grp_fu_119675_p1), + .ce(1'b1), + .dout(grp_fu_119675_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U712( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_119666_p2), + .dout(tmp_113_fu_119722_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U713( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_119870_ap_start), + .done(grp_fu_119870_ap_done), + .din0(grp_fu_119870_p0), + .din1(grp_fu_119870_p1), + .ce(1'b1), + .dout(grp_fu_119870_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U714( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_119885_p0), + .din1(grp_fu_119885_p1), + .ce(1'b1), + .dout(grp_fu_119885_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U715( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_119870_p2), + .dout(tmp_130_fu_119932_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U716( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_120058_ap_start), + .done(grp_fu_120058_ap_done), + .din0(grp_fu_120058_p0), + .din1(grp_fu_120058_p1), + .ce(1'b1), + .dout(grp_fu_120058_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U717( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_120067_p0), + .din1(grp_fu_120067_p1), + .ce(1'b1), + .dout(grp_fu_120067_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U718( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_120058_p2), + .dout(tmp_118_fu_120114_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U719( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_120262_ap_start), + .done(grp_fu_120262_ap_done), + .din0(grp_fu_120262_p0), + .din1(grp_fu_120262_p1), + .ce(1'b1), + .dout(grp_fu_120262_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U720( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_120306_p0), + .din1(grp_fu_120306_p1), + .ce(1'b1), + .dout(grp_fu_120306_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U721( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_120262_p2), + .dout(tmp_135_fu_120353_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U722( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_120462_ap_start), + .done(grp_fu_120462_ap_done), + .din0(grp_fu_120462_p0), + .din1(grp_fu_120462_p1), + .ce(1'b1), + .dout(grp_fu_120462_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U723( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_120471_p0), + .din1(grp_fu_120471_p1), + .ce(1'b1), + .dout(grp_fu_120471_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U724( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_120462_p2), + .dout(tmp_157_fu_120518_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U725( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_120666_ap_start), + .done(grp_fu_120666_ap_done), + .din0(grp_fu_120666_p0), + .din1(grp_fu_120666_p1), + .ce(1'b1), + .dout(grp_fu_120666_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U726( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_120681_p0), + .din1(grp_fu_120681_p1), + .ce(1'b1), + .dout(grp_fu_120681_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U727( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_120666_p2), + .dout(tmp_166_fu_120728_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U728( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_121093_ap_start), + .done(grp_fu_121093_ap_done), + .din0(grp_fu_121093_p0), + .din1(grp_fu_121093_p1), + .ce(1'b1), + .dout(grp_fu_121093_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U729( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_121102_p0), + .din1(grp_fu_121102_p1), + .ce(1'b1), + .dout(grp_fu_121102_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U730( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_121093_p2), + .dout(tmp_8_fu_121149_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U731( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_121297_ap_start), + .done(grp_fu_121297_ap_done), + .din0(grp_fu_121297_p0), + .din1(grp_fu_121297_p1), + .ce(1'b1), + .dout(grp_fu_121297_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U732( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_121352_p0), + .din1(grp_fu_121352_p1), + .ce(1'b1), + .dout(grp_fu_121352_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U733( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_121297_p2), + .dout(tmp_73_fu_121399_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U734( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_121509_ap_start), + .done(grp_fu_121509_ap_done), + .din0(grp_fu_121509_p0), + .din1(grp_fu_121509_p1), + .ce(1'b1), + .dout(grp_fu_121509_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U735( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_121518_p0), + .din1(grp_fu_121518_p1), + .ce(1'b1), + .dout(grp_fu_121518_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U736( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_121509_p2), + .dout(tmp_112_fu_121565_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U737( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_121713_ap_start), + .done(grp_fu_121713_ap_done), + .din0(grp_fu_121713_p0), + .din1(grp_fu_121713_p1), + .ce(1'b1), + .dout(grp_fu_121713_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U738( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_121728_p0), + .din1(grp_fu_121728_p1), + .ce(1'b1), + .dout(grp_fu_121728_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U739( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_121713_p2), + .dout(tmp_129_fu_121775_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U740( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_121902_ap_start), + .done(grp_fu_121902_ap_done), + .din0(grp_fu_121902_p0), + .din1(grp_fu_121902_p1), + .ce(1'b1), + .dout(grp_fu_121902_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U741( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_121911_p0), + .din1(grp_fu_121911_p1), + .ce(1'b1), + .dout(grp_fu_121911_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U742( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_121902_p2), + .dout(tmp_117_fu_121958_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U743( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_122106_ap_start), + .done(grp_fu_122106_ap_done), + .din0(grp_fu_122106_p0), + .din1(grp_fu_122106_p1), + .ce(1'b1), + .dout(grp_fu_122106_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U744( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_122150_p0), + .din1(grp_fu_122150_p1), + .ce(1'b1), + .dout(grp_fu_122150_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U745( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_122106_p2), + .dout(tmp_134_fu_122197_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U746( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_122307_ap_start), + .done(grp_fu_122307_ap_done), + .din0(grp_fu_122307_p0), + .din1(grp_fu_122307_p1), + .ce(1'b1), + .dout(grp_fu_122307_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U747( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_122316_p0), + .din1(grp_fu_122316_p1), + .ce(1'b1), + .dout(grp_fu_122316_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U748( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_122307_p2), + .dout(tmp_156_fu_122363_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U749( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_122511_ap_start), + .done(grp_fu_122511_ap_done), + .din0(grp_fu_122511_p0), + .din1(grp_fu_122511_p1), + .ce(1'b1), + .dout(grp_fu_122511_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U750( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_122526_p0), + .din1(grp_fu_122526_p1), + .ce(1'b1), + .dout(grp_fu_122526_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U751( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_122511_p2), + .dout(tmp_165_fu_122573_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U752( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_122719_ap_start), + .done(grp_fu_122719_ap_done), + .din0(grp_fu_122719_p0), + .din1(grp_fu_122719_p1), + .ce(1'b1), + .dout(grp_fu_122719_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U753( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_122728_p0), + .din1(grp_fu_122728_p1), + .ce(1'b1), + .dout(grp_fu_122728_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U754( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_122719_p2), + .dout(tmp_67_fu_122775_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U755( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_122923_ap_start), + .done(grp_fu_122923_ap_done), + .din0(grp_fu_122923_p0), + .din1(grp_fu_122923_p1), + .ce(1'b1), + .dout(grp_fu_122923_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U756( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_122978_p0), + .din1(grp_fu_122978_p1), + .ce(1'b1), + .dout(grp_fu_122978_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U757( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_122923_p2), + .dout(tmp_93_fu_123025_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U758( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_123134_ap_start), + .done(grp_fu_123134_ap_done), + .din0(grp_fu_123134_p0), + .din1(grp_fu_123134_p1), + .ce(1'b1), + .dout(grp_fu_123134_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U759( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_123143_p0), + .din1(grp_fu_123143_p1), + .ce(1'b1), + .dout(grp_fu_123143_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U760( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_123134_p2), + .dout(tmp_123_fu_123190_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U761( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_123338_ap_start), + .done(grp_fu_123338_ap_done), + .din0(grp_fu_123338_p0), + .din1(grp_fu_123338_p1), + .ce(1'b1), + .dout(grp_fu_123338_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U762( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_123353_p0), + .din1(grp_fu_123353_p1), + .ce(1'b1), + .dout(grp_fu_123353_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U763( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_123338_p2), + .dout(tmp_140_fu_123400_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U764( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_123526_ap_start), + .done(grp_fu_123526_ap_done), + .din0(grp_fu_123526_p0), + .din1(grp_fu_123526_p1), + .ce(1'b1), + .dout(grp_fu_123526_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U765( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_123535_p0), + .din1(grp_fu_123535_p1), + .ce(1'b1), + .dout(grp_fu_123535_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U766( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_123526_p2), + .dout(tmp_128_fu_123582_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U767( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_123730_ap_start), + .done(grp_fu_123730_ap_done), + .din0(grp_fu_123730_p0), + .din1(grp_fu_123730_p1), + .ce(1'b1), + .dout(grp_fu_123730_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U768( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_123774_p0), + .din1(grp_fu_123774_p1), + .ce(1'b1), + .dout(grp_fu_123774_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U769( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_123730_p2), + .dout(tmp_146_fu_123821_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U770( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_123930_ap_start), + .done(grp_fu_123930_ap_done), + .din0(grp_fu_123930_p0), + .din1(grp_fu_123930_p1), + .ce(1'b1), + .dout(grp_fu_123930_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U771( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_123939_p0), + .din1(grp_fu_123939_p1), + .ce(1'b1), + .dout(grp_fu_123939_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U772( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_123930_p2), + .dout(tmp_163_fu_123986_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U773( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_124134_ap_start), + .done(grp_fu_124134_ap_done), + .din0(grp_fu_124134_p0), + .din1(grp_fu_124134_p1), + .ce(1'b1), + .dout(grp_fu_124134_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U774( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_124149_p0), + .din1(grp_fu_124149_p1), + .ce(1'b1), + .dout(grp_fu_124149_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U775( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_124134_p2), + .dout(tmp_170_fu_124196_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U776( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_124667_ap_start), + .done(grp_fu_124667_ap_done), + .din0(grp_fu_124667_p0), + .din1(grp_fu_124667_p1), + .ce(1'b1), + .dout(grp_fu_124667_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U777( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_124676_p0), + .din1(grp_fu_124676_p1), + .ce(1'b1), + .dout(grp_fu_124676_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U778( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_124667_p2), + .dout(tmp_7_fu_124723_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U779( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_124871_ap_start), + .done(grp_fu_124871_ap_done), + .din0(grp_fu_124871_p0), + .din1(grp_fu_124871_p1), + .ce(1'b1), + .dout(grp_fu_124871_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U780( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_124926_p0), + .din1(grp_fu_124926_p1), + .ce(1'b1), + .dout(grp_fu_124926_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U781( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_124871_p2), + .dout(tmp_72_fu_124973_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U782( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_125083_ap_start), + .done(grp_fu_125083_ap_done), + .din0(grp_fu_125083_p0), + .din1(grp_fu_125083_p1), + .ce(1'b1), + .dout(grp_fu_125083_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U783( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_125092_p0), + .din1(grp_fu_125092_p1), + .ce(1'b1), + .dout(grp_fu_125092_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U784( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_125083_p2), + .dout(tmp_110_fu_125139_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U785( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_125287_ap_start), + .done(grp_fu_125287_ap_done), + .din0(grp_fu_125287_p0), + .din1(grp_fu_125287_p1), + .ce(1'b1), + .dout(grp_fu_125287_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U786( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_125302_p0), + .din1(grp_fu_125302_p1), + .ce(1'b1), + .dout(grp_fu_125302_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U787( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_125287_p2), + .dout(tmp_127_fu_125349_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U788( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_125476_ap_start), + .done(grp_fu_125476_ap_done), + .din0(grp_fu_125476_p0), + .din1(grp_fu_125476_p1), + .ce(1'b1), + .dout(grp_fu_125476_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U789( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_125485_p0), + .din1(grp_fu_125485_p1), + .ce(1'b1), + .dout(grp_fu_125485_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U790( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_125476_p2), + .dout(tmp_116_fu_125532_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U791( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_125680_ap_start), + .done(grp_fu_125680_ap_done), + .din0(grp_fu_125680_p0), + .din1(grp_fu_125680_p1), + .ce(1'b1), + .dout(grp_fu_125680_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U792( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_125724_p0), + .din1(grp_fu_125724_p1), + .ce(1'b1), + .dout(grp_fu_125724_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U793( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_125680_p2), + .dout(tmp_133_fu_125771_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U794( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_125881_ap_start), + .done(grp_fu_125881_ap_done), + .din0(grp_fu_125881_p0), + .din1(grp_fu_125881_p1), + .ce(1'b1), + .dout(grp_fu_125881_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U795( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_125890_p0), + .din1(grp_fu_125890_p1), + .ce(1'b1), + .dout(grp_fu_125890_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U796( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_125881_p2), + .dout(tmp_155_fu_125937_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U797( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_126085_ap_start), + .done(grp_fu_126085_ap_done), + .din0(grp_fu_126085_p0), + .din1(grp_fu_126085_p1), + .ce(1'b1), + .dout(grp_fu_126085_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U798( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_126100_p0), + .din1(grp_fu_126100_p1), + .ce(1'b1), + .dout(grp_fu_126100_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U799( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_126085_p2), + .dout(tmp_164_fu_126147_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U800( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_126293_ap_start), + .done(grp_fu_126293_ap_done), + .din0(grp_fu_126293_p0), + .din1(grp_fu_126293_p1), + .ce(1'b1), + .dout(grp_fu_126293_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U801( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_126302_p0), + .din1(grp_fu_126302_p1), + .ce(1'b1), + .dout(grp_fu_126302_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U802( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_126293_p2), + .dout(tmp_66_fu_126349_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U803( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_126497_ap_start), + .done(grp_fu_126497_ap_done), + .din0(grp_fu_126497_p0), + .din1(grp_fu_126497_p1), + .ce(1'b1), + .dout(grp_fu_126497_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U804( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_126552_p0), + .din1(grp_fu_126552_p1), + .ce(1'b1), + .dout(grp_fu_126552_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U805( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_126497_p2), + .dout(tmp_91_fu_126599_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U806( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_126708_ap_start), + .done(grp_fu_126708_ap_done), + .din0(grp_fu_126708_p0), + .din1(grp_fu_126708_p1), + .ce(1'b1), + .dout(grp_fu_126708_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U807( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_126717_p0), + .din1(grp_fu_126717_p1), + .ce(1'b1), + .dout(grp_fu_126717_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U808( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_126708_p2), + .dout(tmp_122_fu_126764_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U809( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_126912_ap_start), + .done(grp_fu_126912_ap_done), + .din0(grp_fu_126912_p0), + .din1(grp_fu_126912_p1), + .ce(1'b1), + .dout(grp_fu_126912_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U810( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_126927_p0), + .din1(grp_fu_126927_p1), + .ce(1'b1), + .dout(grp_fu_126927_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U811( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_126912_p2), + .dout(tmp_138_fu_126974_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U812( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_127100_ap_start), + .done(grp_fu_127100_ap_done), + .din0(grp_fu_127100_p0), + .din1(grp_fu_127100_p1), + .ce(1'b1), + .dout(grp_fu_127100_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U813( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_127109_p0), + .din1(grp_fu_127109_p1), + .ce(1'b1), + .dout(grp_fu_127109_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U814( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_127100_p2), + .dout(tmp_126_fu_127156_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U815( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_127304_ap_start), + .done(grp_fu_127304_ap_done), + .din0(grp_fu_127304_p0), + .din1(grp_fu_127304_p1), + .ce(1'b1), + .dout(grp_fu_127304_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U816( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_127348_p0), + .din1(grp_fu_127348_p1), + .ce(1'b1), + .dout(grp_fu_127348_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U817( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_127304_p2), + .dout(tmp_145_fu_127395_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U818( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_127504_ap_start), + .done(grp_fu_127504_ap_done), + .din0(grp_fu_127504_p0), + .din1(grp_fu_127504_p1), + .ce(1'b1), + .dout(grp_fu_127504_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U819( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_127513_p0), + .din1(grp_fu_127513_p1), + .ce(1'b1), + .dout(grp_fu_127513_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U820( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_127504_p2), + .dout(tmp_162_fu_127560_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U821( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_127708_ap_start), + .done(grp_fu_127708_ap_done), + .din0(grp_fu_127708_p0), + .din1(grp_fu_127708_p1), + .ce(1'b1), + .dout(grp_fu_127708_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U822( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_127723_p0), + .din1(grp_fu_127723_p1), + .ce(1'b1), + .dout(grp_fu_127723_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U823( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_127708_p2), + .dout(tmp_169_fu_127770_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U824( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_128135_ap_start), + .done(grp_fu_128135_ap_done), + .din0(grp_fu_128135_p0), + .din1(grp_fu_128135_p1), + .ce(1'b1), + .dout(grp_fu_128135_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U825( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_128144_p0), + .din1(grp_fu_128144_p1), + .ce(1'b1), + .dout(grp_fu_128144_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U826( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_128135_p2), + .dout(tmp_65_fu_128191_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U827( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_128339_ap_start), + .done(grp_fu_128339_ap_done), + .din0(grp_fu_128339_p0), + .din1(grp_fu_128339_p1), + .ce(1'b1), + .dout(grp_fu_128339_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U828( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_128394_p0), + .din1(grp_fu_128394_p1), + .ce(1'b1), + .dout(grp_fu_128394_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U829( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_128339_p2), + .dout(tmp_90_fu_128441_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U830( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_128551_ap_start), + .done(grp_fu_128551_ap_done), + .din0(grp_fu_128551_p0), + .din1(grp_fu_128551_p1), + .ce(1'b1), + .dout(grp_fu_128551_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U831( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_128560_p0), + .din1(grp_fu_128560_p1), + .ce(1'b1), + .dout(grp_fu_128560_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U832( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_128551_p2), + .dout(tmp_121_fu_128607_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U833( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_128755_ap_start), + .done(grp_fu_128755_ap_done), + .din0(grp_fu_128755_p0), + .din1(grp_fu_128755_p1), + .ce(1'b1), + .dout(grp_fu_128755_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U834( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_128770_p0), + .din1(grp_fu_128770_p1), + .ce(1'b1), + .dout(grp_fu_128770_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U835( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_128755_p2), + .dout(tmp_137_fu_128817_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U836( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_128944_ap_start), + .done(grp_fu_128944_ap_done), + .din0(grp_fu_128944_p0), + .din1(grp_fu_128944_p1), + .ce(1'b1), + .dout(grp_fu_128944_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U837( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_128953_p0), + .din1(grp_fu_128953_p1), + .ce(1'b1), + .dout(grp_fu_128953_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U838( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_128944_p2), + .dout(tmp_125_fu_129000_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U839( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_129148_ap_start), + .done(grp_fu_129148_ap_done), + .din0(grp_fu_129148_p0), + .din1(grp_fu_129148_p1), + .ce(1'b1), + .dout(grp_fu_129148_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U840( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_129192_p0), + .din1(grp_fu_129192_p1), + .ce(1'b1), + .dout(grp_fu_129192_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U841( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_129148_p2), + .dout(tmp_144_fu_129239_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U842( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_129349_ap_start), + .done(grp_fu_129349_ap_done), + .din0(grp_fu_129349_p0), + .din1(grp_fu_129349_p1), + .ce(1'b1), + .dout(grp_fu_129349_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U843( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_129358_p0), + .din1(grp_fu_129358_p1), + .ce(1'b1), + .dout(grp_fu_129358_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U844( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_129349_p2), + .dout(tmp_161_fu_129405_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U845( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_129553_ap_start), + .done(grp_fu_129553_ap_done), + .din0(grp_fu_129553_p0), + .din1(grp_fu_129553_p1), + .ce(1'b1), + .dout(grp_fu_129553_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U846( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_129568_p0), + .din1(grp_fu_129568_p1), + .ce(1'b1), + .dout(grp_fu_129568_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U847( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_129553_p2), + .dout(tmp_168_fu_129615_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U848( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_129761_ap_start), + .done(grp_fu_129761_ap_done), + .din0(grp_fu_129761_p0), + .din1(grp_fu_129761_p1), + .ce(1'b1), + .dout(grp_fu_129761_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U849( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_129770_p0), + .din1(grp_fu_129770_p1), + .ce(1'b1), + .dout(grp_fu_129770_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U850( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_129761_p2), + .dout(tmp_80_fu_129817_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U851( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_129965_ap_start), + .done(grp_fu_129965_ap_done), + .din0(grp_fu_129965_p0), + .din1(grp_fu_129965_p1), + .ce(1'b1), + .dout(grp_fu_129965_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U852( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_130020_p0), + .din1(grp_fu_130020_p1), + .ce(1'b1), + .dout(grp_fu_130020_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U853( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_129965_p2), + .dout(tmp_107_fu_130067_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U854( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_130176_ap_start), + .done(grp_fu_130176_ap_done), + .din0(grp_fu_130176_p0), + .din1(grp_fu_130176_p1), + .ce(1'b1), + .dout(grp_fu_130176_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U855( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_130185_p0), + .din1(grp_fu_130185_p1), + .ce(1'b1), + .dout(grp_fu_130185_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U856( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_130176_p2), + .dout(tmp_132_fu_130232_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U857( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_130380_ap_start), + .done(grp_fu_130380_ap_done), + .din0(grp_fu_130380_p0), + .din1(grp_fu_130380_p1), + .ce(1'b1), + .dout(grp_fu_130380_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U858( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_130395_p0), + .din1(grp_fu_130395_p1), + .ce(1'b1), + .dout(grp_fu_130395_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U859( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_130380_p2), + .dout(tmp_148_fu_130442_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U860( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_130568_ap_start), + .done(grp_fu_130568_ap_done), + .din0(grp_fu_130568_p0), + .din1(grp_fu_130568_p1), + .ce(1'b1), + .dout(grp_fu_130568_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U861( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_130577_p0), + .din1(grp_fu_130577_p1), + .ce(1'b1), + .dout(grp_fu_130577_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U862( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_130568_p2), + .dout(tmp_136_fu_130624_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U863( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_130772_ap_start), + .done(grp_fu_130772_ap_done), + .din0(grp_fu_130772_p0), + .din1(grp_fu_130772_p1), + .ce(1'b1), + .dout(grp_fu_130772_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U864( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_130816_p0), + .din1(grp_fu_130816_p1), + .ce(1'b1), + .dout(grp_fu_130816_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U865( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_130772_p2), + .dout(tmp_154_fu_130863_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U866( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_130972_ap_start), + .done(grp_fu_130972_ap_done), + .din0(grp_fu_130972_p0), + .din1(grp_fu_130972_p1), + .ce(1'b1), + .dout(grp_fu_130972_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U867( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_130981_p0), + .din1(grp_fu_130981_p1), + .ce(1'b1), + .dout(grp_fu_130981_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U868( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_130972_p2), + .dout(tmp_167_fu_131028_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U869( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_131176_ap_start), + .done(grp_fu_131176_ap_done), + .din0(grp_fu_131176_p0), + .din1(grp_fu_131176_p1), + .ce(1'b1), + .dout(grp_fu_131176_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U870( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_131191_p0), + .din1(grp_fu_131191_p1), + .ce(1'b1), + .dout(grp_fu_131191_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U871( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_131176_p2), + .dout(tmp_171_fu_131238_p30) +); + +myproject_mac_muladd_6ns_3ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 3 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_6ns_3ns_18ns_18_1_1_U872( + .din0(grp_fu_131342_p0), + .din1(grp_fu_131342_p1), + .din2(add_ln216_1_reg_131696), + .dout(grp_fu_131342_p3) +); + +myproject_mac_muladd_2ns_6ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 2 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_2ns_6ns_18ns_18_1_1_U873( + .din0(grp_fu_131350_p0), + .din1(grp_fu_131350_p1), + .din2(add_ln216_1_reg_131696), + .dout(grp_fu_131350_p3) +); + +myproject_mac_muladd_6ns_3ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 3 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_6ns_3ns_18ns_18_1_1_U874( + .din0(grp_fu_131358_p0), + .din1(grp_fu_131358_p1), + .din2(add_ln216_8_reg_135279), + .dout(grp_fu_131358_p3) +); + +myproject_mac_muladd_2ns_6ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 2 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_2ns_6ns_18ns_18_1_1_U875( + .din0(grp_fu_131366_p0), + .din1(grp_fu_131366_p1), + .din2(add_ln216_8_reg_135279), + .dout(grp_fu_131366_p3) +); + +myproject_mac_muladd_6ns_3ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 3 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_6ns_3ns_19ns_19_1_1_U876( + .din0(grp_fu_131374_p0), + .din1(grp_fu_131374_p1), + .din2(add_ln216_6_reg_138875), + .dout(grp_fu_131374_p3) +); + +myproject_mac_muladd_2ns_6ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 2 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_2ns_6ns_19ns_19_1_1_U877( + .din0(grp_fu_131382_p0), + .din1(grp_fu_131382_p1), + .din2(add_ln216_6_reg_138875), + .dout(grp_fu_131382_p3) +); + +myproject_mac_muladd_6ns_3ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 3 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_6ns_3ns_19ns_19_1_1_U878( + .din0(grp_fu_131390_p0), + .din1(grp_fu_131390_p1), + .din2(add_ln216_14_reg_142442), + .dout(grp_fu_131390_p3) +); + +myproject_mac_muladd_2ns_6ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 2 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_2ns_6ns_19ns_19_1_1_U879( + .din0(grp_fu_131398_p0), + .din1(grp_fu_131398_p1), + .din2(add_ln216_14_reg_142442), + .dout(grp_fu_131398_p3) +); + +myproject_mac_muladd_12ns_4ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 12 ), + .din1_WIDTH( 4 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_12ns_4ns_18ns_18_1_1_U880( + .din0(grp_fu_131406_p0), + .din1(grp_fu_131406_p1), + .din2(mul_ln279_2_reg_146941), + .dout(grp_fu_131406_p3) +); + +myproject_mac_muladd_4ns_8ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 4 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_4ns_8ns_18ns_18_1_1_U881( + .din0(grp_fu_131413_p0), + .din1(grp_fu_131413_p1), + .din2(add_ln276_reg_147608), + .dout(grp_fu_131413_p3) +); + +myproject_mac_muladd_12ns_4ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 12 ), + .din1_WIDTH( 4 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_12ns_4ns_18ns_18_1_1_U882( + .din0(grp_fu_131420_p0), + .din1(grp_fu_131420_p1), + .din2(mul_ln279_2_reg_146941), + .dout(grp_fu_131420_p3) +); + +myproject_mac_muladd_3ns_6ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 3 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_3ns_6ns_18ns_18_1_1_U883( + .din0(grp_fu_131427_p0), + .din1(grp_fu_131427_p1), + .din2(add_ln276_2_reg_147986), + .dout(grp_fu_131427_p3) +); + +myproject_mac_muladd_4ns_8ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 4 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_4ns_8ns_18ns_18_1_1_U884( + .din0(grp_fu_131435_p0), + .din1(grp_fu_131435_p1), + .din2(add_ln276_reg_147608), + .dout(grp_fu_131435_p3) +); + +myproject_mac_muladd_6ns_2ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 2 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_6ns_2ns_18ns_18_1_1_U885( + .din0(grp_fu_131442_p0), + .din1(grp_fu_131442_p1), + .din2(add_ln276_2_reg_147986), + .dout(grp_fu_131442_p3) +); + +myproject_mac_muladd_3ns_6ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 3 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_3ns_6ns_18ns_18_1_1_U886( + .din0(grp_fu_131450_p0), + .din1(grp_fu_131450_p1), + .din2(add_ln276_10_reg_148407), + .dout(grp_fu_131450_p3) +); + +myproject_mac_muladd_6ns_2ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 2 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_6ns_2ns_18ns_18_1_1_U887( + .din0(grp_fu_131458_p0), + .din1(grp_fu_131458_p1), + .din2(add_ln276_10_reg_148407), + .dout(grp_fu_131458_p3) +); + +myproject_mac_muladd_4ns_8ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 4 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_4ns_8ns_18ns_18_1_1_U888( + .din0(grp_fu_131466_p0), + .din1(grp_fu_131466_p1), + .din2(add_ln276_6_reg_148004), + .dout(grp_fu_131466_p3) +); + +myproject_mac_muladd_3ns_6ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 3 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_3ns_6ns_18ns_18_1_1_U889( + .din0(grp_fu_131473_p0), + .din1(grp_fu_131473_p1), + .din2(add_ln276_9_reg_152900), + .dout(grp_fu_131473_p3) +); + +myproject_mac_muladd_4ns_8ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 4 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_4ns_8ns_18ns_18_1_1_U890( + .din0(grp_fu_131481_p0), + .din1(grp_fu_131481_p1), + .din2(add_ln276_6_reg_148004), + .dout(grp_fu_131481_p3) +); + +myproject_mac_muladd_6ns_2ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 2 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_6ns_2ns_18ns_18_1_1_U891( + .din0(grp_fu_131488_p0), + .din1(grp_fu_131488_p1), + .din2(add_ln276_9_reg_152900), + .dout(grp_fu_131488_p3) +); + +myproject_mac_muladd_3ns_6ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 3 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_3ns_6ns_18ns_18_1_1_U892( + .din0(grp_fu_131496_p0), + .din1(grp_fu_131496_p1), + .din2(add_ln276_20_reg_153308), + .dout(grp_fu_131496_p3) +); + +myproject_mac_muladd_6ns_2ns_18ns_18_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 2 ), + .din2_WIDTH( 18 ), + .dout_WIDTH( 18 )) +myproject_mac_muladd_6ns_2ns_18ns_18_1_1_U893( + .din0(grp_fu_131504_p0), + .din1(grp_fu_131504_p1), + .din2(add_ln276_20_reg_153308), + .dout(grp_fu_131504_p3) +); + +myproject_mac_muladd_12ns_4ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 12 ), + .din1_WIDTH( 4 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_12ns_4ns_19ns_19_1_1_U894( + .din0(grp_fu_131512_p0), + .din1(grp_fu_131512_p1), + .din2(mul_ln279_3_reg_147614), + .dout(grp_fu_131512_p3) +); + +myproject_mac_muladd_4ns_8ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 4 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_4ns_8ns_19ns_19_1_1_U895( + .din0(grp_fu_131519_p0), + .din1(grp_fu_131519_p1), + .din2(add_ln276_1_reg_157425), + .dout(grp_fu_131519_p3) +); + +myproject_mac_muladd_12ns_4ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 12 ), + .din1_WIDTH( 4 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_12ns_4ns_19ns_19_1_1_U896( + .din0(grp_fu_131526_p0), + .din1(grp_fu_131526_p1), + .din2(mul_ln279_3_reg_147614), + .dout(grp_fu_131526_p3) +); + +myproject_mac_muladd_3ns_6ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 3 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_3ns_6ns_19ns_19_1_1_U897( + .din0(grp_fu_131533_p0), + .din1(grp_fu_131533_p1), + .din2(add_ln276_8_reg_157827), + .dout(grp_fu_131533_p3) +); + +myproject_mac_muladd_4ns_8ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 4 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_4ns_8ns_19ns_19_1_1_U898( + .din0(grp_fu_131541_p0), + .din1(grp_fu_131541_p1), + .din2(add_ln276_1_reg_157425), + .dout(grp_fu_131541_p3) +); + +myproject_mac_muladd_6ns_2ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 2 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_6ns_2ns_19ns_19_1_1_U899( + .din0(grp_fu_131548_p0), + .din1(grp_fu_131548_p1), + .din2(add_ln276_8_reg_157827), + .dout(grp_fu_131548_p3) +); + +myproject_mac_muladd_3ns_6ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 3 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_3ns_6ns_19ns_19_1_1_U900( + .din0(grp_fu_131556_p0), + .din1(grp_fu_131556_p1), + .din2(add_ln276_19_reg_158248), + .dout(grp_fu_131556_p3) +); + +myproject_mac_muladd_6ns_2ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 2 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_6ns_2ns_19ns_19_1_1_U901( + .din0(grp_fu_131564_p0), + .din1(grp_fu_131564_p1), + .din2(add_ln276_19_reg_158248), + .dout(grp_fu_131564_p3) +); + +myproject_mac_muladd_4ns_8ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 4 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_4ns_8ns_19ns_19_1_1_U902( + .din0(grp_fu_131572_p0), + .din1(grp_fu_131572_p1), + .din2(add_ln276_7_reg_157845), + .dout(grp_fu_131572_p3) +); + +myproject_mac_muladd_3ns_6ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 3 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_3ns_6ns_19ns_19_1_1_U903( + .din0(grp_fu_131579_p0), + .din1(grp_fu_131579_p1), + .din2(add_ln276_15_reg_162741), + .dout(grp_fu_131579_p3) +); + +myproject_mac_muladd_4ns_8ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 4 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_4ns_8ns_19ns_19_1_1_U904( + .din0(grp_fu_131587_p0), + .din1(grp_fu_131587_p1), + .din2(add_ln276_7_reg_157845), + .dout(grp_fu_131587_p3) +); + +myproject_mac_muladd_6ns_2ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 2 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_6ns_2ns_19ns_19_1_1_U905( + .din0(grp_fu_131594_p0), + .din1(grp_fu_131594_p1), + .din2(add_ln276_15_reg_162741), + .dout(grp_fu_131594_p3) +); + +myproject_mac_muladd_3ns_6ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 3 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_3ns_6ns_19ns_19_1_1_U906( + .din0(grp_fu_131602_p0), + .din1(grp_fu_131602_p1), + .din2(add_ln276_27_reg_163149), + .dout(grp_fu_131602_p3) +); + +myproject_mac_muladd_6ns_2ns_19ns_19_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 2 ), + .din2_WIDTH( 19 ), + .dout_WIDTH( 19 )) +myproject_mac_muladd_6ns_2ns_19ns_19_1_1_U907( + .din0(grp_fu_131610_p0), + .din1(grp_fu_131610_p1), + .din2(add_ln276_27_reg_163149), + .dout(grp_fu_131610_p3) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_8_fu_118650_p2 == 1'd1) & (icmp_ln268_9_fu_118627_p2 == 1'd1) & (ap_ST_fsm_state2767 == ap_CS_fsm))) begin + cc8_0_0_0_0_0_reg_96049 <= add_ln264_fu_118673_p2; + end else if (((ap_ST_fsm_state2570 == ap_CS_fsm) & (icmp_ln261_fu_117325_p2 == 1'd0))) begin + cc8_0_0_0_0_0_reg_96049 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_11_fu_120274_p2 == 1'd1) & (icmp_ln268_15_fu_120251_p2 == 1'd1) & (ap_ST_fsm_state3074 == ap_CS_fsm))) begin + cc8_0_0_0_1_0_reg_96421 <= add_ln264_3_fu_120297_p2; + end else if (((icmp_ln264_fu_117484_p2 == 1'd1) & (ap_ST_fsm_state2571 == ap_CS_fsm))) begin + cc8_0_0_0_1_0_reg_96421 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_10_fu_122118_p2 == 1'd1) & (icmp_ln268_14_fu_122095_p2 == 1'd1) & (ap_ST_fsm_state3382 == ap_CS_fsm))) begin + cc8_0_0_1_0_0_reg_96797 <= add_ln264_2_fu_122141_p2; + end else if (((ap_ST_fsm_state3186 == ap_CS_fsm) & (icmp_ln261_2_fu_120840_p2 == 1'd0))) begin + cc8_0_0_1_0_0_reg_96797 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_14_fu_123742_p2 == 1'd1) & (icmp_ln268_21_fu_123719_p2 == 1'd1) & (ap_ST_fsm_state3688 == ap_CS_fsm))) begin + cc8_0_0_1_1_0_reg_97169 <= add_ln264_6_fu_123765_p2; + end else if (((icmp_ln264_2_fu_120952_p2 == 1'd1) & (ap_ST_fsm_state3187 == ap_CS_fsm))) begin + cc8_0_0_1_1_0_reg_97169 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_9_fu_125692_p2 == 1'd1) & (icmp_ln268_13_fu_125669_p2 == 1'd1) & (ap_ST_fsm_state3997 == ap_CS_fsm))) begin + cc8_0_1_0_0_0_reg_97557 <= add_ln264_1_fu_125715_p2; + end else if (((ap_ST_fsm_state3801 == ap_CS_fsm) & (icmp_ln261_1_fu_124367_p2 == 1'd0))) begin + cc8_0_1_0_0_0_reg_97557 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_13_fu_127316_p2 == 1'd1) & (icmp_ln268_20_fu_127293_p2 == 1'd1) & (ap_ST_fsm_state4303 == ap_CS_fsm))) begin + cc8_0_1_0_1_0_reg_97929 <= add_ln264_5_fu_127339_p2; + end else if (((icmp_ln264_1_fu_124526_p2 == 1'd1) & (ap_ST_fsm_state3802 == ap_CS_fsm))) begin + cc8_0_1_0_1_0_reg_97929 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_12_fu_129160_p2 == 1'd1) & (icmp_ln268_19_fu_129137_p2 == 1'd1) & (ap_ST_fsm_state4610 == ap_CS_fsm))) begin + cc8_0_1_1_0_0_reg_98305 <= add_ln264_4_fu_129183_p2; + end else if (((ap_ST_fsm_state4415 == ap_CS_fsm) & (icmp_ln261_3_fu_127882_p2 == 1'd0))) begin + cc8_0_1_1_0_0_reg_98305 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_15_fu_130784_p2 == 1'd1) & (icmp_ln268_23_fu_130761_p2 == 1'd1) & (ap_ST_fsm_state4915 == ap_CS_fsm))) begin + cc8_0_1_1_1_0_reg_98677 <= add_ln264_7_fu_130807_p2; + end else if (((icmp_ln264_4_fu_127994_p2 == 1'd1) & (ap_ST_fsm_state4416 == ap_CS_fsm))) begin + cc8_0_1_1_1_0_reg_98677 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_4_fu_104418_p2 == 1'd1) & (icmp_ln208_5_fu_104210_p2 == 1'd1) & (ap_ST_fsm_state350 == ap_CS_fsm))) begin + cc_0_0_0_0_reg_91195 <= add_ln204_fu_104527_p2; + end else if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln203_fu_101988_p2 == 1'd0))) begin + cc_0_0_0_0_reg_91195 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) & (icmp_ln206_6_fu_107831_p2 == 1'd1) & (icmp_ln208_9_fu_107624_p2 == 1'd1))) begin + cc_0_0_1_0_reg_92381 <= add_ln204_2_fu_107940_p2; + end else if (((ap_ST_fsm_state610 == ap_CS_fsm) & (icmp_ln203_2_fu_105423_p2 == 1'd0))) begin + cc_0_0_1_0_reg_92381 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_5_fu_111270_p2 == 1'd1) & (icmp_ln208_8_fu_111062_p2 == 1'd1) & (ap_ST_fsm_state1561 == ap_CS_fsm))) begin + cc_0_1_0_0_reg_93579 <= add_ln204_1_fu_111385_p2; + end else if (((icmp_ln203_1_fu_108860_p2 == 1'd0) & (ap_ST_fsm_state1216 == ap_CS_fsm))) begin + cc_0_1_0_0_reg_93579 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_7_fu_114665_p2 == 1'd1) & (icmp_ln208_11_fu_114458_p2 == 1'd1) & (ap_ST_fsm_state2165 == ap_CS_fsm))) begin + cc_0_1_1_0_reg_94765 <= add_ln204_3_fu_114774_p2; + end else if (((ap_ST_fsm_state1821 == ap_CS_fsm) & (icmp_ln203_3_fu_112277_p2 == 1'd0))) begin + cc_0_1_1_0_reg_94765 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2461 == ap_CS_fsm)) begin + ff4_0_0_0_0_reg_95953 <= add_ln248_fu_116109_p2; + end else if (((ap_ST_fsm_state2426 == ap_CS_fsm) & (icmp_ln246_fu_115674_p2 == 1'd0))) begin + ff4_0_0_0_0_reg_95953 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2496 == ap_CS_fsm)) begin + ff4_0_0_1_0_reg_95965 <= add_ln248_2_fu_116442_p2; + end else if (((icmp_ln248_fu_115743_p2 == 1'd1) & (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + ff4_0_0_1_0_reg_95965 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2532 == ap_CS_fsm)) begin + ff4_0_1_0_0_reg_95989 <= add_ln248_1_fu_116873_p2; + end else if (((ap_ST_fsm_state2497 == ap_CS_fsm) & (icmp_ln246_1_fu_116448_p2 == 1'd0))) begin + ff4_0_1_0_0_reg_95989 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2567 == ap_CS_fsm)) begin + ff4_0_1_1_0_reg_96001 <= add_ln248_3_fu_117206_p2; + end else if (((icmp_ln248_1_fu_116507_p2 == 1'd1) & (ap_ST_fsm_state2498 == ap_CS_fsm))) begin + ff4_0_1_1_0_reg_96001 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln264_3_fu_119214_p2 == 1'd1) & (ap_ST_fsm_state2879 == ap_CS_fsm))) begin + ff7_0_0_0_0_reg_96037 <= add_ln261_fu_119223_p2; + end else if (((ap_ST_fsm_state2569 == ap_CS_fsm) & (icmp_ln259_fu_117242_p2 == 1'd0))) begin + ff7_0_0_0_0_reg_96037 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln264_6_fu_122682_p2 == 1'd1) & (ap_ST_fsm_state3494 == ap_CS_fsm))) begin + ff7_0_0_1_0_reg_96785 <= add_ln261_2_fu_122691_p2; + end else if (((icmp_ln261_fu_117325_p2 == 1'd1) & (ap_ST_fsm_state2570 == ap_CS_fsm))) begin + ff7_0_0_1_0_reg_96785 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln264_5_fu_126256_p2 == 1'd1) & (ap_ST_fsm_state4109 == ap_CS_fsm))) begin + ff7_0_1_0_0_reg_97545 <= add_ln261_1_fu_126265_p2; + end else if (((ap_ST_fsm_state3800 == ap_CS_fsm) & (icmp_ln259_1_fu_124304_p2 == 1'd0))) begin + ff7_0_1_0_0_reg_97545 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln264_7_fu_129724_p2 == 1'd1) & (ap_ST_fsm_state4722 == ap_CS_fsm))) begin + ff7_0_1_1_0_reg_98293 <= add_ln261_3_fu_129733_p2; + end else if (((icmp_ln261_1_fu_124367_p2 == 1'd1) & (ap_ST_fsm_state3801 == ap_CS_fsm))) begin + ff7_0_1_1_0_reg_98293 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state5 == ap_CS_fsm) & (icmp_ln204_fu_102042_p2 == 1'd1))) begin + ff_0_0_0_reg_91173 <= add_ln203_reg_131691; + end else if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln201_fu_101946_p2 == 1'd0))) begin + ff_0_0_0_reg_91173 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln204_2_fu_105463_p2 == 1'd1) & (ap_ST_fsm_state611 == ap_CS_fsm))) begin + ff_0_0_1_reg_92359 <= add_ln203_2_reg_135274; + end else if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln203_fu_101988_p2 == 1'd1))) begin + ff_0_0_1_reg_92359 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln204_1_fu_108914_p2 == 1'd1) & (ap_ST_fsm_state1217 == ap_CS_fsm))) begin + ff_0_1_0_reg_93557 <= add_ln203_1_reg_138870; + end else if (((icmp_ln201_1_fu_108832_p2 == 1'd0) & (ap_ST_fsm_state1215 == ap_CS_fsm))) begin + ff_0_1_0_reg_93557 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln204_3_fu_112317_p2 == 1'd1) & (ap_ST_fsm_state1822 == ap_CS_fsm))) begin + ff_0_1_1_reg_94743 <= add_ln203_3_reg_142437; + end else if (((icmp_ln203_1_fu_108860_p2 == 1'd1) & (ap_ST_fsm_state1216 == ap_CS_fsm))) begin + ff_0_1_1_reg_94743 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_8_fu_118234_p2 == 1'd1) & (ap_ST_fsm_state2689 == ap_CS_fsm))) begin + fh9_0_0_0_0_0_0_reg_96061 <= add_ln266_fu_118251_p2; + end else if (((ap_ST_fsm_state2571 == ap_CS_fsm) & (icmp_ln264_fu_117484_p2 == 1'd0))) begin + fh9_0_0_0_0_0_0_reg_96061 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_24_fu_119032_p2 == 1'd1) & (ap_ST_fsm_state2842 == ap_CS_fsm))) begin + fh9_0_0_0_0_1_0_reg_96241 <= add_ln266_8_fu_119049_p2; + end else if (((icmp_ln266_fu_117841_p2 == 1'd1) & (icmp_ln268_fu_117818_p2 == 1'd1) & (ap_ST_fsm_state2612 == ap_CS_fsm))) begin + fh9_0_0_0_0_1_0_reg_96241 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_12_fu_119859_p2 == 1'd1) & (ap_ST_fsm_state2997 == ap_CS_fsm))) begin + fh9_0_0_0_1_0_0_reg_96433 <= add_ln266_3_fu_119876_p2; + end else if (((ap_ST_fsm_state2879 == ap_CS_fsm) & (icmp_ln264_3_fu_119214_p2 == 1'd0))) begin + fh9_0_0_0_1_0_0_reg_96433 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_27_fu_120655_p2 == 1'd1) & (ap_ST_fsm_state3149 == ap_CS_fsm))) begin + fh9_0_0_0_1_1_0_reg_96609 <= add_ln266_11_fu_120672_p2; + end else if (((icmp_ln266_3_fu_119467_p2 == 1'd1) & (icmp_ln268_3_fu_119444_p2 == 1'd1) & (ap_ST_fsm_state2920 == ap_CS_fsm))) begin + fh9_0_0_0_1_1_0_reg_96609 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_11_fu_121702_p2 == 1'd1) & (ap_ST_fsm_state3305 == ap_CS_fsm))) begin + fh9_0_0_1_0_0_0_reg_96809 <= add_ln266_2_fu_121719_p2; + end else if (((ap_ST_fsm_state3187 == ap_CS_fsm) & (icmp_ln264_2_fu_120952_p2 == 1'd0))) begin + fh9_0_0_1_0_0_0_reg_96809 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_26_fu_122500_p2 == 1'd1) & (ap_ST_fsm_state3457 == ap_CS_fsm))) begin + fh9_0_0_1_0_1_0_reg_96989 <= add_ln266_10_fu_122517_p2; + end else if (((icmp_ln266_2_fu_121309_p2 == 1'd1) & (icmp_ln268_2_fu_121286_p2 == 1'd1) & (ap_ST_fsm_state3228 == ap_CS_fsm))) begin + fh9_0_0_1_0_1_0_reg_96989 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_18_fu_123327_p2 == 1'd1) & (ap_ST_fsm_state3612 == ap_CS_fsm))) begin + fh9_0_0_1_1_0_0_reg_97181 <= add_ln266_6_fu_123344_p2; + end else if (((ap_ST_fsm_state3494 == ap_CS_fsm) & (icmp_ln264_6_fu_122682_p2 == 1'd0))) begin + fh9_0_0_1_1_0_0_reg_97181 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_30_fu_124123_p2 == 1'd1) & (ap_ST_fsm_state3763 == ap_CS_fsm))) begin + fh9_0_0_1_1_1_0_reg_97357 <= add_ln266_14_fu_124140_p2; + end else if (((icmp_ln266_6_fu_122935_p2 == 1'd1) & (icmp_ln268_6_fu_122912_p2 == 1'd1) & (ap_ST_fsm_state3535 == ap_CS_fsm))) begin + fh9_0_0_1_1_1_0_reg_97357 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_10_fu_125276_p2 == 1'd1) & (ap_ST_fsm_state3920 == ap_CS_fsm))) begin + fh9_0_1_0_0_0_0_reg_97569 <= add_ln266_1_fu_125293_p2; + end else if (((ap_ST_fsm_state3802 == ap_CS_fsm) & (icmp_ln264_1_fu_124526_p2 == 1'd0))) begin + fh9_0_1_0_0_0_0_reg_97569 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_25_fu_126074_p2 == 1'd1) & (ap_ST_fsm_state4072 == ap_CS_fsm))) begin + fh9_0_1_0_0_1_0_reg_97749 <= add_ln266_9_fu_126091_p2; + end else if (((icmp_ln266_1_fu_124883_p2 == 1'd1) & (icmp_ln268_1_fu_124860_p2 == 1'd1) & (ap_ST_fsm_state3843 == ap_CS_fsm))) begin + fh9_0_1_0_0_1_0_reg_97749 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_17_fu_126901_p2 == 1'd1) & (ap_ST_fsm_state4227 == ap_CS_fsm))) begin + fh9_0_1_0_1_0_0_reg_97941 <= add_ln266_5_fu_126918_p2; + end else if (((ap_ST_fsm_state4109 == ap_CS_fsm) & (icmp_ln264_5_fu_126256_p2 == 1'd0))) begin + fh9_0_1_0_1_0_0_reg_97941 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_29_fu_127697_p2 == 1'd1) & (ap_ST_fsm_state4378 == ap_CS_fsm))) begin + fh9_0_1_0_1_1_0_reg_98117 <= add_ln266_13_fu_127714_p2; + end else if (((icmp_ln266_5_fu_126509_p2 == 1'd1) & (icmp_ln268_5_fu_126486_p2 == 1'd1) & (ap_ST_fsm_state4150 == ap_CS_fsm))) begin + fh9_0_1_0_1_1_0_reg_98117 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_16_fu_128744_p2 == 1'd1) & (ap_ST_fsm_state4534 == ap_CS_fsm))) begin + fh9_0_1_1_0_0_0_reg_98317 <= add_ln266_4_fu_128761_p2; + end else if (((ap_ST_fsm_state4416 == ap_CS_fsm) & (icmp_ln264_4_fu_127994_p2 == 1'd0))) begin + fh9_0_1_1_0_0_0_reg_98317 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_28_fu_129542_p2 == 1'd1) & (ap_ST_fsm_state4685 == ap_CS_fsm))) begin + fh9_0_1_1_0_1_0_reg_98497 <= add_ln266_12_fu_129559_p2; + end else if (((icmp_ln266_4_fu_128351_p2 == 1'd1) & (icmp_ln268_4_fu_128328_p2 == 1'd1) & (ap_ST_fsm_state4457 == ap_CS_fsm))) begin + fh9_0_1_1_0_1_0_reg_98497 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_22_fu_130369_p2 == 1'd1) & (ap_ST_fsm_state4839 == ap_CS_fsm))) begin + fh9_0_1_1_1_0_0_reg_98689 <= add_ln266_7_fu_130386_p2; + end else if (((ap_ST_fsm_state4722 == ap_CS_fsm) & (icmp_ln264_7_fu_129724_p2 == 1'd0))) begin + fh9_0_1_1_1_0_0_reg_98689 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_31_fu_131165_p2 == 1'd1) & (ap_ST_fsm_state4990 == ap_CS_fsm))) begin + fh9_0_1_1_1_1_0_reg_98865 <= add_ln266_15_fu_131182_p2; + end else if (((icmp_ln266_7_fu_129977_p2 == 1'd1) & (icmp_ln268_7_fu_129954_p2 == 1'd1) & (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + fh9_0_1_1_1_1_0_reg_98865 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_4_fu_103406_p2 == 1'd1) & (ap_ST_fsm_state199 == ap_CS_fsm))) begin + fh_0_0_0_0_0_reg_91207 <= add_ln206_fu_103609_p2; + end else if (((ap_ST_fsm_state5 == ap_CS_fsm) & (icmp_ln204_fu_102042_p2 == 1'd0))) begin + fh_0_0_0_0_0_reg_91207 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_12_fu_105013_p2 == 1'd1) & (ap_ST_fsm_state500 == ap_CS_fsm))) begin + fh_0_0_0_1_0_reg_91787 <= add_ln206_4_fu_105215_p2; + end else if (((icmp_ln206_fu_102733_p2 == 1'd1) & (icmp_ln208_fu_102524_p2 == 1'd1) & (ap_ST_fsm_state47 == ap_CS_fsm))) begin + fh_0_0_0_1_0_reg_91787 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) & (icmp_ln208_7_fu_106822_p2 == 1'd1))) begin + fh_0_0_1_0_0_reg_92393 <= add_ln206_2_fu_107024_p2; + end else if (((ap_ST_fsm_state611 == ap_CS_fsm) & (icmp_ln204_2_fu_105463_p2 == 1'd0))) begin + fh_0_0_1_0_0_reg_92393 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_14_fu_108425_p2 == 1'd1) & (ap_ST_fsm_state1105 == ap_CS_fsm))) begin + fh_0_0_1_1_0_reg_92973 <= add_ln206_6_fu_108626_p2; + end else if (((icmp_ln206_2_fu_106151_p2 == 1'd1) & (icmp_ln208_2_fu_105943_p2 == 1'd1) & (ap_ST_fsm_state652 == ap_CS_fsm))) begin + fh_0_0_1_1_0_reg_92973 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_6_fu_110267_p2 == 1'd1) & (ap_ST_fsm_state1410 == ap_CS_fsm))) begin + fh_0_1_0_0_0_reg_93591 <= add_ln206_1_fu_110470_p2; + end else if (((icmp_ln204_1_fu_108914_p2 == 1'd0) & (ap_ST_fsm_state1217 == ap_CS_fsm))) begin + fh_0_1_0_0_0_reg_93591 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_13_fu_111867_p2 == 1'd1) & (ap_ST_fsm_state1711 == ap_CS_fsm))) begin + fh_0_1_0_1_0_reg_94171 <= add_ln206_5_fu_112069_p2; + end else if (((icmp_ln206_1_fu_109593_p2 == 1'd1) & (icmp_ln208_1_fu_109384_p2 == 1'd1) & (ap_ST_fsm_state1258 == ap_CS_fsm))) begin + fh_0_1_0_1_0_reg_94171 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_10_fu_113665_p2 == 1'd1) & (ap_ST_fsm_state2014 == ap_CS_fsm))) begin + fh_0_1_1_0_0_reg_94777 <= add_ln206_3_fu_113867_p2; + end else if (((ap_ST_fsm_state1822 == ap_CS_fsm) & (icmp_ln204_3_fu_112317_p2 == 1'd0))) begin + fh_0_1_1_0_0_reg_94777 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_15_fu_115259_p2 == 1'd1) & (ap_ST_fsm_state2315 == ap_CS_fsm))) begin + fh_0_1_1_1_0_reg_95357 <= add_ln206_7_fu_115460_p2; + end else if (((icmp_ln206_3_fu_112994_p2 == 1'd1) & (icmp_ln208_3_fu_112786_p2 == 1'd1) & (ap_ST_fsm_state1862 == ap_CS_fsm))) begin + fh_0_1_1_1_0_reg_95357 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2649 == ap_CS_fsm)) begin + fw10_0_0_0_0_0_0_0_reg_96073 <= add_ln268_fu_118030_p2; + end else if ((ap_ST_fsm_state2572 == ap_CS_fsm)) begin + fw10_0_0_0_0_0_0_0_reg_96073 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2726 == ap_CS_fsm)) begin + fw10_0_0_0_0_0_1_0_reg_96157 <= add_ln268_8_fu_118406_p2; + end else if (((icmp_ln268_fu_117818_p2 == 1'd1) & (ap_ST_fsm_state2612 == ap_CS_fsm) & (icmp_ln266_fu_117841_p2 == 1'd0))) begin + fw10_0_0_0_0_0_1_0_reg_96157 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2804 == ap_CS_fsm)) begin + fw10_0_0_0_0_1_0_0_reg_96253 <= add_ln268_9_fu_118828_p2; + end else if ((ap_ST_fsm_state2727 == ap_CS_fsm)) begin + fw10_0_0_0_0_1_0_0_reg_96253 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + fw10_0_0_0_0_1_1_0_reg_96337 <= add_ln268_24_fu_119204_p2; + end else if (((icmp_ln268_9_fu_118627_p2 == 1'd1) & (ap_ST_fsm_state2767 == ap_CS_fsm) & (icmp_ln266_8_fu_118650_p2 == 1'd0))) begin + fw10_0_0_0_0_1_1_0_reg_96337 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2957 == ap_CS_fsm)) begin + fw10_0_0_0_1_0_0_0_reg_96445 <= add_ln268_3_fu_119655_p2; + end else if ((ap_ST_fsm_state2880 == ap_CS_fsm)) begin + fw10_0_0_0_1_0_0_0_reg_96445 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3034 == ap_CS_fsm)) begin + fw10_0_0_0_1_0_1_0_reg_96527 <= add_ln268_12_fu_120030_p2; + end else if (((icmp_ln268_3_fu_119444_p2 == 1'd1) & (ap_ST_fsm_state2920 == ap_CS_fsm) & (icmp_ln266_3_fu_119467_p2 == 1'd0))) begin + fw10_0_0_0_1_0_1_0_reg_96527 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3111 == ap_CS_fsm)) begin + fw10_0_0_0_1_1_0_0_reg_96621 <= add_ln268_15_fu_120451_p2; + end else if ((ap_ST_fsm_state3035 == ap_CS_fsm)) begin + fw10_0_0_0_1_1_0_0_reg_96621 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + fw10_0_0_0_1_1_1_0_reg_96703 <= add_ln268_27_fu_120826_p2; + end else if (((icmp_ln268_15_fu_120251_p2 == 1'd1) & (ap_ST_fsm_state3074 == ap_CS_fsm) & (icmp_ln266_11_fu_120274_p2 == 1'd0))) begin + fw10_0_0_0_1_1_1_0_reg_96703 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3265 == ap_CS_fsm)) begin + fw10_0_0_1_0_0_0_0_reg_96821 <= add_ln268_2_fu_121498_p2; + end else if ((ap_ST_fsm_state3188 == ap_CS_fsm)) begin + fw10_0_0_1_0_0_0_0_reg_96821 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3342 == ap_CS_fsm)) begin + fw10_0_0_1_0_0_1_0_reg_96905 <= add_ln268_11_fu_121874_p2; + end else if (((icmp_ln268_2_fu_121286_p2 == 1'd1) & (ap_ST_fsm_state3228 == ap_CS_fsm) & (icmp_ln266_2_fu_121309_p2 == 1'd0))) begin + fw10_0_0_1_0_0_1_0_reg_96905 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3419 == ap_CS_fsm)) begin + fw10_0_0_1_0_1_0_0_reg_97001 <= add_ln268_14_fu_122296_p2; + end else if ((ap_ST_fsm_state3343 == ap_CS_fsm)) begin + fw10_0_0_1_0_1_0_0_reg_97001 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + fw10_0_0_1_0_1_1_0_reg_97085 <= add_ln268_26_fu_122672_p2; + end else if (((icmp_ln268_14_fu_122095_p2 == 1'd1) & (ap_ST_fsm_state3382 == ap_CS_fsm) & (icmp_ln266_10_fu_122118_p2 == 1'd0))) begin + fw10_0_0_1_0_1_1_0_reg_97085 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3572 == ap_CS_fsm)) begin + fw10_0_0_1_1_0_0_0_reg_97193 <= add_ln268_6_fu_123123_p2; + end else if ((ap_ST_fsm_state3495 == ap_CS_fsm)) begin + fw10_0_0_1_1_0_0_0_reg_97193 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3649 == ap_CS_fsm)) begin + fw10_0_0_1_1_0_1_0_reg_97275 <= add_ln268_18_fu_123498_p2; + end else if (((icmp_ln268_6_fu_122912_p2 == 1'd1) & (ap_ST_fsm_state3535 == ap_CS_fsm) & (icmp_ln266_6_fu_122935_p2 == 1'd0))) begin + fw10_0_0_1_1_0_1_0_reg_97275 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3725 == ap_CS_fsm)) begin + fw10_0_0_1_1_1_0_0_reg_97369 <= add_ln268_21_fu_123919_p2; + end else if ((ap_ST_fsm_state3650 == ap_CS_fsm)) begin + fw10_0_0_1_1_1_0_0_reg_97369 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + fw10_0_0_1_1_1_1_0_reg_97451 <= add_ln268_30_fu_124294_p2; + end else if (((icmp_ln268_21_fu_123719_p2 == 1'd1) & (ap_ST_fsm_state3688 == ap_CS_fsm) & (icmp_ln266_14_fu_123742_p2 == 1'd0))) begin + fw10_0_0_1_1_1_1_0_reg_97451 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3880 == ap_CS_fsm)) begin + fw10_0_1_0_0_0_0_0_reg_97581 <= add_ln268_1_fu_125072_p2; + end else if ((ap_ST_fsm_state3803 == ap_CS_fsm)) begin + fw10_0_1_0_0_0_0_0_reg_97581 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3957 == ap_CS_fsm)) begin + fw10_0_1_0_0_0_1_0_reg_97665 <= add_ln268_10_fu_125448_p2; + end else if (((icmp_ln268_1_fu_124860_p2 == 1'd1) & (ap_ST_fsm_state3843 == ap_CS_fsm) & (icmp_ln266_1_fu_124883_p2 == 1'd0))) begin + fw10_0_1_0_0_0_1_0_reg_97665 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4034 == ap_CS_fsm)) begin + fw10_0_1_0_0_1_0_0_reg_97761 <= add_ln268_13_fu_125870_p2; + end else if ((ap_ST_fsm_state3958 == ap_CS_fsm)) begin + fw10_0_1_0_0_1_0_0_reg_97761 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + fw10_0_1_0_0_1_1_0_reg_97845 <= add_ln268_25_fu_126246_p2; + end else if (((icmp_ln268_13_fu_125669_p2 == 1'd1) & (ap_ST_fsm_state3997 == ap_CS_fsm) & (icmp_ln266_9_fu_125692_p2 == 1'd0))) begin + fw10_0_1_0_0_1_1_0_reg_97845 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4187 == ap_CS_fsm)) begin + fw10_0_1_0_1_0_0_0_reg_97953 <= add_ln268_5_fu_126697_p2; + end else if ((ap_ST_fsm_state4110 == ap_CS_fsm)) begin + fw10_0_1_0_1_0_0_0_reg_97953 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4264 == ap_CS_fsm)) begin + fw10_0_1_0_1_0_1_0_reg_98035 <= add_ln268_17_fu_127072_p2; + end else if (((icmp_ln268_5_fu_126486_p2 == 1'd1) & (ap_ST_fsm_state4150 == ap_CS_fsm) & (icmp_ln266_5_fu_126509_p2 == 1'd0))) begin + fw10_0_1_0_1_0_1_0_reg_98035 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4340 == ap_CS_fsm)) begin + fw10_0_1_0_1_1_0_0_reg_98129 <= add_ln268_20_fu_127493_p2; + end else if ((ap_ST_fsm_state4265 == ap_CS_fsm)) begin + fw10_0_1_0_1_1_0_0_reg_98129 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + fw10_0_1_0_1_1_1_0_reg_98211 <= add_ln268_29_fu_127868_p2; + end else if (((icmp_ln268_20_fu_127293_p2 == 1'd1) & (ap_ST_fsm_state4303 == ap_CS_fsm) & (icmp_ln266_13_fu_127316_p2 == 1'd0))) begin + fw10_0_1_0_1_1_1_0_reg_98211 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4494 == ap_CS_fsm)) begin + fw10_0_1_1_0_0_0_0_reg_98329 <= add_ln268_4_fu_128540_p2; + end else if ((ap_ST_fsm_state4417 == ap_CS_fsm)) begin + fw10_0_1_1_0_0_0_0_reg_98329 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4571 == ap_CS_fsm)) begin + fw10_0_1_1_0_0_1_0_reg_98413 <= add_ln268_16_fu_128916_p2; + end else if (((icmp_ln268_4_fu_128328_p2 == 1'd1) & (ap_ST_fsm_state4457 == ap_CS_fsm) & (icmp_ln266_4_fu_128351_p2 == 1'd0))) begin + fw10_0_1_1_0_0_1_0_reg_98413 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4647 == ap_CS_fsm)) begin + fw10_0_1_1_0_1_0_0_reg_98509 <= add_ln268_19_fu_129338_p2; + end else if ((ap_ST_fsm_state4572 == ap_CS_fsm)) begin + fw10_0_1_1_0_1_0_0_reg_98509 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + fw10_0_1_1_0_1_1_0_reg_98593 <= add_ln268_28_fu_129714_p2; + end else if (((icmp_ln268_19_fu_129137_p2 == 1'd1) & (ap_ST_fsm_state4610 == ap_CS_fsm) & (icmp_ln266_12_fu_129160_p2 == 1'd0))) begin + fw10_0_1_1_0_1_1_0_reg_98593 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4799 == ap_CS_fsm)) begin + fw10_0_1_1_1_0_0_0_reg_98701 <= add_ln268_7_fu_130165_p2; + end else if ((ap_ST_fsm_state4723 == ap_CS_fsm)) begin + fw10_0_1_1_1_0_0_0_reg_98701 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4876 == ap_CS_fsm)) begin + fw10_0_1_1_1_0_1_0_reg_98783 <= add_ln268_22_fu_130540_p2; + end else if (((icmp_ln268_7_fu_129954_p2 == 1'd1) & (ap_ST_fsm_state4762 == ap_CS_fsm) & (icmp_ln266_7_fu_129977_p2 == 1'd0))) begin + fw10_0_1_1_1_0_1_0_reg_98783 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4952 == ap_CS_fsm)) begin + fw10_0_1_1_1_1_0_0_reg_98877 <= add_ln268_23_fu_130961_p2; + end else if ((ap_ST_fsm_state4877 == ap_CS_fsm)) begin + fw10_0_1_1_1_1_0_0_reg_98877 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + fw10_0_1_1_1_1_1_0_reg_98959 <= add_ln268_31_fu_131336_p2; + end else if (((icmp_ln268_23_fu_130761_p2 == 1'd1) & (ap_ST_fsm_state4915 == ap_CS_fsm) & (icmp_ln266_15_fu_130784_p2 == 1'd0))) begin + fw10_0_1_1_1_1_1_0_reg_98959 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state122 == ap_CS_fsm)) begin + fw_0_0_0_0_0_0_reg_91219 <= add_ln208_fu_103056_p2; + end else if ((ap_ST_fsm_state7 == ap_CS_fsm)) begin + fw_0_0_0_0_0_0_reg_91219 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state274 == ap_CS_fsm)) begin + fw_0_0_0_0_1_0_reg_91503 <= add_ln208_4_fu_103748_p2; + end else if ((ap_ST_fsm_state159 == ap_CS_fsm)) begin + fw_0_0_0_0_1_0_reg_91503 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state425 == ap_CS_fsm)) begin + fw_0_0_0_1_0_0_reg_91799 <= add_ln208_5_fu_104665_p2; + end else if ((ap_ST_fsm_state312 == ap_CS_fsm)) begin + fw_0_0_0_1_0_0_reg_91799 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + fw_0_0_0_1_1_0_reg_92079 <= add_ln208_12_fu_105353_p2; + end else if ((ap_ST_fsm_state462 == ap_CS_fsm)) begin + fw_0_0_0_1_1_0_reg_92079 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state727 == ap_CS_fsm)) begin + fw_0_0_1_0_0_0_reg_92405 <= add_ln208_2_fu_106473_p2; + end else if ((ap_ST_fsm_state613 == ap_CS_fsm)) begin + fw_0_0_1_0_0_0_reg_92405 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state879 == ap_CS_fsm)) begin + fw_0_0_1_0_1_0_reg_92689 <= add_ln208_7_fu_107163_p2; + end else if ((ap_ST_fsm_state764 == ap_CS_fsm)) begin + fw_0_0_1_0_1_0_reg_92689 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1030 == ap_CS_fsm)) begin + fw_0_0_1_1_0_0_reg_92985 <= add_ln208_9_fu_108078_p2; + end else if ((ap_ST_fsm_state917 == ap_CS_fsm)) begin + fw_0_0_1_1_0_0_reg_92985 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + fw_0_0_1_1_1_0_reg_93265 <= add_ln208_14_fu_108764_p2; + end else if ((ap_ST_fsm_state1067 == ap_CS_fsm)) begin + fw_0_0_1_1_1_0_reg_93265 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1333 == ap_CS_fsm)) begin + fw_0_1_0_0_0_0_reg_93603 <= add_ln208_1_fu_109921_p2; + end else if ((ap_ST_fsm_state1219 == ap_CS_fsm)) begin + fw_0_1_0_0_0_0_reg_93603 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1485 == ap_CS_fsm)) begin + fw_0_1_0_0_1_0_reg_93887 <= add_ln208_6_fu_110609_p2; + end else if ((ap_ST_fsm_state1370 == ap_CS_fsm)) begin + fw_0_1_0_0_1_0_reg_93887 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1636 == ap_CS_fsm)) begin + fw_0_1_0_1_0_0_reg_94183 <= add_ln208_8_fu_111523_p2; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + fw_0_1_0_1_0_0_reg_94183 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + fw_0_1_0_1_1_0_reg_94463 <= add_ln208_13_fu_112207_p2; + end else if ((ap_ST_fsm_state1673 == ap_CS_fsm)) begin + fw_0_1_0_1_1_0_reg_94463 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1937 == ap_CS_fsm)) begin + fw_0_1_1_0_0_0_reg_94789 <= add_ln208_3_fu_113316_p2; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + fw_0_1_1_0_0_0_reg_94789 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2089 == ap_CS_fsm)) begin + fw_0_1_1_0_1_0_reg_95073 <= add_ln208_10_fu_114006_p2; + end else if ((ap_ST_fsm_state1974 == ap_CS_fsm)) begin + fw_0_1_1_0_1_0_reg_95073 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2240 == ap_CS_fsm)) begin + fw_0_1_1_1_0_0_reg_95369 <= add_ln208_11_fu_114912_p2; + end else if ((ap_ST_fsm_state2127 == ap_CS_fsm)) begin + fw_0_1_1_1_0_0_reg_95369 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + fw_0_1_1_1_1_0_reg_95649 <= add_ln208_15_fu_115598_p2; + end else if ((ap_ST_fsm_state2277 == ap_CS_fsm)) begin + fw_0_1_1_1_1_0_reg_95649 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln199_fu_101926_p2 == 1'd1) & (ap_ST_fsm_state2 == ap_CS_fsm))) begin + oh2_0_0_reg_95929 <= 4'd0; + end else if (((icmp_ln246_1_fu_116448_p2 == 1'd1) & (ap_ST_fsm_state2497 == ap_CS_fsm))) begin + oh2_0_0_reg_95929 <= add_ln244_fu_116497_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln244_fu_115662_p2 == 1'd1) & (ap_ST_fsm_state2425 == ap_CS_fsm))) begin + oh5_0_0_reg_96013 <= 4'd0; + end else if (((icmp_ln259_1_fu_124304_p2 == 1'd1) & (ap_ST_fsm_state3800 == ap_CS_fsm))) begin + oh5_0_0_reg_96013 <= add_ln257_fu_124353_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln201_1_fu_108832_p2 == 1'd1) & (ap_ST_fsm_state1215 == ap_CS_fsm))) begin + oh_0_0_reg_91149 <= add_ln199_fu_108844_p2; + end else if (((ap_start == 1'b1) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + oh_0_0_reg_91149 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln248_2_fu_116119_p2 == 1'd1) & (ap_ST_fsm_state2462 == ap_CS_fsm))) begin + ow3_0_0_0_reg_95941 <= add_ln246_fu_116261_p2; + end else if (((ap_ST_fsm_state2425 == ap_CS_fsm) & (icmp_ln244_fu_115662_p2 == 1'd0))) begin + ow3_0_0_0_reg_95941 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln248_3_fu_116883_p2 == 1'd1) & (ap_ST_fsm_state2533 == ap_CS_fsm))) begin + ow3_0_1_0_reg_95977 <= add_ln246_1_fu_117025_p2; + end else if (((icmp_ln246_fu_115674_p2 == 1'd1) & (ap_ST_fsm_state2426 == ap_CS_fsm))) begin + ow3_0_1_0_reg_95977 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln261_2_fu_120840_p2 == 1'd1) & (ap_ST_fsm_state3186 == ap_CS_fsm))) begin + ow6_0_0_0_reg_96025 <= add_ln259_fu_120942_p2; + end else if (((ap_ST_fsm_state2568 == ap_CS_fsm) & (icmp_ln257_fu_117220_p2 == 1'd0))) begin + ow6_0_0_0_reg_96025 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln261_3_fu_127882_p2 == 1'd1) & (ap_ST_fsm_state4415 == ap_CS_fsm))) begin + ow6_0_1_0_reg_97533 <= add_ln259_1_fu_127984_p2; + end else if (((icmp_ln259_fu_117242_p2 == 1'd1) & (ap_ST_fsm_state2569 == ap_CS_fsm))) begin + ow6_0_1_0_reg_97533 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln203_2_fu_105423_p2 == 1'd1) & (ap_ST_fsm_state610 == ap_CS_fsm))) begin + ow_0_0_0_reg_91161 <= add_ln201_fu_105453_p2; + end else if (((ap_ST_fsm_state2 == ap_CS_fsm) & (icmp_ln199_fu_101926_p2 == 1'd0))) begin + ow_0_0_0_reg_91161 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln203_3_fu_112277_p2 == 1'd1) & (ap_ST_fsm_state1821 == ap_CS_fsm))) begin + ow_0_1_0_reg_93545 <= add_ln201_1_fu_112307_p2; + end else if (((icmp_ln201_fu_101946_p2 == 1'd1) & (ap_ST_fsm_state3 == ap_CS_fsm))) begin + ow_0_1_0_reg_93545 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_12927)) begin + phi_ln1116_10_reg_93899 <= reg_100598; + end else if ((7'd126 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100558; + end else if ((7'd124 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100478; + end else if ((7'd122 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100398; + end else if ((7'd120 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100318; + end else if ((7'd118 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100238; + end else if ((7'd116 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100158; + end else if ((7'd114 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100078; + end else if ((7'd112 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99998; + end else if ((7'd110 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99918; + end else if ((7'd108 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99838; + end else if ((7'd106 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99758; + end else if ((7'd104 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99678; + end else if ((7'd102 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99598; + end else if ((7'd100 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99518; + end else if ((7'd98 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99438; + end else if ((7'd96 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99358; + end else if ((7'd94 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100438; + end else if ((7'd92 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100118; + end else if ((7'd90 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99798; + end else if ((7'd88 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99478; + end else if ((7'd86 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99958; + end else if ((7'd84 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99318; + end else if ((7'd82 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99638; + end else if ((7'd80 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100278; + end else if ((7'd78 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99398; + end else if ((7'd76 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99558; + end else if ((7'd74 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99718; + end else if ((7'd72 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99878; + end else if ((7'd70 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100038; + end else if ((7'd68 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100198; + end else if ((7'd66 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100358; + end else if ((7'd64 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100518; + end else if ((7'd62 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99338; + end else if ((7'd60 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99378; + end else if ((7'd58 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99418; + end else if ((7'd56 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99458; + end else if ((7'd54 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99498; + end else if ((7'd52 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99538; + end else if ((7'd50 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99578; + end else if ((7'd48 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99618; + end else if ((7'd46 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99658; + end else if ((7'd44 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99698; + end else if ((7'd42 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99738; + end else if ((7'd40 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99778; + end else if ((7'd38 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99818; + end else if ((7'd36 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99858; + end else if ((7'd34 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99898; + end else if ((7'd32 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99938; + end else if ((7'd30 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_99978; + end else if ((7'd28 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100018; + end else if ((7'd26 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100058; + end else if ((7'd24 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100098; + end else if ((7'd22 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100138; + end else if ((7'd20 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100178; + end else if ((7'd18 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100218; + end else if ((7'd16 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100258; + end else if ((7'd14 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100298; + end else if ((7'd12 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100338; + end else if ((7'd10 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100378; + end else if ((7'd8 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100418; + end else if ((7'd6 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100458; + end else if ((7'd4 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100498; + end else if ((7'd2 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100538; + end else if ((7'd0 == add_ln1116_10_reg_139883)) begin + phi_ln1116_10_reg_93899 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_11643)) begin + phi_ln1116_11_reg_92701 <= reg_100598; + end else if ((7'd126 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100558; + end else if ((7'd124 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100478; + end else if ((7'd122 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100398; + end else if ((7'd120 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100318; + end else if ((7'd118 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100238; + end else if ((7'd116 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100158; + end else if ((7'd114 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100078; + end else if ((7'd112 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99998; + end else if ((7'd110 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99918; + end else if ((7'd108 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99838; + end else if ((7'd106 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99758; + end else if ((7'd104 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99678; + end else if ((7'd102 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99598; + end else if ((7'd100 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99518; + end else if ((7'd98 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99438; + end else if ((7'd96 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99358; + end else if ((7'd94 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100438; + end else if ((7'd92 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100118; + end else if ((7'd90 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99798; + end else if ((7'd88 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99478; + end else if ((7'd86 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99958; + end else if ((7'd84 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99318; + end else if ((7'd82 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99638; + end else if ((7'd80 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100278; + end else if ((7'd78 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99398; + end else if ((7'd76 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99558; + end else if ((7'd74 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99718; + end else if ((7'd72 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99878; + end else if ((7'd70 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100038; + end else if ((7'd68 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100198; + end else if ((7'd66 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100358; + end else if ((7'd64 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100518; + end else if ((7'd62 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99338; + end else if ((7'd60 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99378; + end else if ((7'd58 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99418; + end else if ((7'd56 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99458; + end else if ((7'd54 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99498; + end else if ((7'd52 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99538; + end else if ((7'd50 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99578; + end else if ((7'd48 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99618; + end else if ((7'd46 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99658; + end else if ((7'd44 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99698; + end else if ((7'd42 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99738; + end else if ((7'd40 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99778; + end else if ((7'd38 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99818; + end else if ((7'd36 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99858; + end else if ((7'd34 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99898; + end else if ((7'd32 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99938; + end else if ((7'd30 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_99978; + end else if ((7'd28 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100018; + end else if ((7'd26 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100058; + end else if ((7'd24 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100098; + end else if ((7'd22 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100138; + end else if ((7'd20 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100178; + end else if ((7'd18 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100218; + end else if ((7'd16 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100258; + end else if ((7'd14 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100298; + end else if ((7'd12 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100338; + end else if ((7'd10 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100378; + end else if ((7'd8 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100418; + end else if ((7'd6 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100458; + end else if ((7'd4 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100498; + end else if ((7'd2 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100538; + end else if ((7'd0 == add_ln1116_11_reg_136276)) begin + phi_ln1116_11_reg_92701 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1526 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_13248)) begin + phi_ln1116_12_reg_94195 <= reg_100598; + end else if ((7'd125 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101843; + end else if ((7'd123 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101763; + end else if ((7'd121 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101683; + end else if ((7'd119 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101603; + end else if ((7'd117 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101523; + end else if ((7'd115 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101443; + end else if ((7'd113 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101363; + end else if ((7'd111 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101283; + end else if ((7'd109 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101203; + end else if ((7'd107 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101123; + end else if ((7'd105 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101043; + end else if ((7'd103 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100963; + end else if ((7'd101 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100883; + end else if ((7'd99 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100803; + end else if ((7'd97 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100723; + end else if ((7'd95 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100643; + end else if ((7'd93 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101643; + end else if ((7'd91 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101323; + end else if ((7'd89 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101003; + end else if ((7'd87 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100683; + end else if ((7'd85 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100843; + end else if ((7'd83 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101483; + end else if ((7'd81 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101163; + end else if ((7'd79 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101803; + end else if ((7'd77 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100763; + end else if ((7'd75 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100923; + end else if ((7'd73 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101083; + end else if ((7'd71 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101243; + end else if ((7'd69 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101403; + end else if ((7'd67 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101563; + end else if ((7'd65 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101723; + end else if ((7'd63 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101883; + end else if ((7'd61 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100663; + end else if ((7'd59 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100703; + end else if ((7'd57 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100743; + end else if ((7'd55 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100783; + end else if ((7'd53 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100823; + end else if ((7'd51 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100863; + end else if ((7'd49 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100903; + end else if ((7'd47 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100943; + end else if ((7'd45 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_100983; + end else if ((7'd43 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101023; + end else if ((7'd41 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101063; + end else if ((7'd39 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101103; + end else if ((7'd37 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101143; + end else if ((7'd35 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101183; + end else if ((7'd33 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101223; + end else if ((7'd31 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101263; + end else if ((7'd29 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101303; + end else if ((7'd27 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101343; + end else if ((7'd25 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101383; + end else if ((7'd23 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101423; + end else if ((7'd21 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101463; + end else if ((7'd19 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101503; + end else if ((7'd17 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101543; + end else if ((7'd15 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101583; + end else if ((7'd13 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101623; + end else if ((7'd11 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101663; + end else if ((7'd9 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101703; + end else if ((7'd7 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101743; + end else if ((7'd5 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101783; + end else if ((7'd3 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101823; + end else if ((7'd1 == add_ln1116_12_reg_140743)) begin + phi_ln1116_12_reg_94195 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state920 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_11964)) begin + phi_ln1116_13_reg_92997 <= reg_100598; + end else if ((7'd125 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101843; + end else if ((7'd123 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101763; + end else if ((7'd121 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101683; + end else if ((7'd119 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101603; + end else if ((7'd117 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101523; + end else if ((7'd115 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101443; + end else if ((7'd113 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101363; + end else if ((7'd111 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101283; + end else if ((7'd109 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101203; + end else if ((7'd107 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101123; + end else if ((7'd105 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101043; + end else if ((7'd103 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100963; + end else if ((7'd101 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100883; + end else if ((7'd99 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100803; + end else if ((7'd97 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100723; + end else if ((7'd95 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100643; + end else if ((7'd93 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101643; + end else if ((7'd91 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101323; + end else if ((7'd89 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101003; + end else if ((7'd87 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100683; + end else if ((7'd85 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100843; + end else if ((7'd83 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101483; + end else if ((7'd81 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101163; + end else if ((7'd79 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101803; + end else if ((7'd77 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100763; + end else if ((7'd75 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100923; + end else if ((7'd73 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101083; + end else if ((7'd71 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101243; + end else if ((7'd69 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101403; + end else if ((7'd67 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101563; + end else if ((7'd65 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101723; + end else if ((7'd63 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101883; + end else if ((7'd61 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100663; + end else if ((7'd59 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100703; + end else if ((7'd57 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100743; + end else if ((7'd55 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100783; + end else if ((7'd53 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100823; + end else if ((7'd51 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100863; + end else if ((7'd49 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100903; + end else if ((7'd47 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100943; + end else if ((7'd45 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_100983; + end else if ((7'd43 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101023; + end else if ((7'd41 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101063; + end else if ((7'd39 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101103; + end else if ((7'd37 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101143; + end else if ((7'd35 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101183; + end else if ((7'd33 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101223; + end else if ((7'd31 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101263; + end else if ((7'd29 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101303; + end else if ((7'd27 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101343; + end else if ((7'd25 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101383; + end else if ((7'd23 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101423; + end else if ((7'd21 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101463; + end else if ((7'd19 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101503; + end else if ((7'd17 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101543; + end else if ((7'd15 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101583; + end else if ((7'd13 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101623; + end else if ((7'd11 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101663; + end else if ((7'd9 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101703; + end else if ((7'd7 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101743; + end else if ((7'd5 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101783; + end else if ((7'd3 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101823; + end else if ((7'd1 == add_ln1116_13_reg_137141)) begin + phi_ln1116_13_reg_92997 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_14211)) begin + phi_ln1116_14_reg_95085 <= reg_100598; + end else if ((7'd126 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100558; + end else if ((7'd124 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100478; + end else if ((7'd122 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100398; + end else if ((7'd120 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100318; + end else if ((7'd118 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100238; + end else if ((7'd116 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100158; + end else if ((7'd114 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100078; + end else if ((7'd112 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99998; + end else if ((7'd110 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99918; + end else if ((7'd108 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99838; + end else if ((7'd106 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99758; + end else if ((7'd104 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99678; + end else if ((7'd102 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99598; + end else if ((7'd100 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99518; + end else if ((7'd98 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99438; + end else if ((7'd96 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99358; + end else if ((7'd94 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100438; + end else if ((7'd92 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100118; + end else if ((7'd90 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99798; + end else if ((7'd88 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99478; + end else if ((7'd86 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99958; + end else if ((7'd84 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99318; + end else if ((7'd82 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99638; + end else if ((7'd80 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100278; + end else if ((7'd78 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99398; + end else if ((7'd76 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99558; + end else if ((7'd74 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99718; + end else if ((7'd72 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99878; + end else if ((7'd70 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100038; + end else if ((7'd68 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100198; + end else if ((7'd66 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100358; + end else if ((7'd64 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100518; + end else if ((7'd62 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99338; + end else if ((7'd60 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99378; + end else if ((7'd58 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99418; + end else if ((7'd56 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99458; + end else if ((7'd54 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99498; + end else if ((7'd52 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99538; + end else if ((7'd50 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99578; + end else if ((7'd48 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99618; + end else if ((7'd46 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99658; + end else if ((7'd44 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99698; + end else if ((7'd42 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99738; + end else if ((7'd40 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99778; + end else if ((7'd38 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99818; + end else if ((7'd36 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99858; + end else if ((7'd34 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99898; + end else if ((7'd32 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99938; + end else if ((7'd30 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_99978; + end else if ((7'd28 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100018; + end else if ((7'd26 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100058; + end else if ((7'd24 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100098; + end else if ((7'd22 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100138; + end else if ((7'd20 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100178; + end else if ((7'd18 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100218; + end else if ((7'd16 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100258; + end else if ((7'd14 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100298; + end else if ((7'd12 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100338; + end else if ((7'd10 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100378; + end else if ((7'd8 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100418; + end else if ((7'd6 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100458; + end else if ((7'd4 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100498; + end else if ((7'd2 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100538; + end else if ((7'd0 == add_ln1116_14_reg_143436)) begin + phi_ln1116_14_reg_95085 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2130 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_14532)) begin + phi_ln1116_15_reg_95381 <= reg_100598; + end else if ((7'd125 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101843; + end else if ((7'd123 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101763; + end else if ((7'd121 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101683; + end else if ((7'd119 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101603; + end else if ((7'd117 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101523; + end else if ((7'd115 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101443; + end else if ((7'd113 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101363; + end else if ((7'd111 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101283; + end else if ((7'd109 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101203; + end else if ((7'd107 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101123; + end else if ((7'd105 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101043; + end else if ((7'd103 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100963; + end else if ((7'd101 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100883; + end else if ((7'd99 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100803; + end else if ((7'd97 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100723; + end else if ((7'd95 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100643; + end else if ((7'd93 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101643; + end else if ((7'd91 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101323; + end else if ((7'd89 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101003; + end else if ((7'd87 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100683; + end else if ((7'd85 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100843; + end else if ((7'd83 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101483; + end else if ((7'd81 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101163; + end else if ((7'd79 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101803; + end else if ((7'd77 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100763; + end else if ((7'd75 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100923; + end else if ((7'd73 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101083; + end else if ((7'd71 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101243; + end else if ((7'd69 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101403; + end else if ((7'd67 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101563; + end else if ((7'd65 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101723; + end else if ((7'd63 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101883; + end else if ((7'd61 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100663; + end else if ((7'd59 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100703; + end else if ((7'd57 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100743; + end else if ((7'd55 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100783; + end else if ((7'd53 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100823; + end else if ((7'd51 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100863; + end else if ((7'd49 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100903; + end else if ((7'd47 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100943; + end else if ((7'd45 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_100983; + end else if ((7'd43 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101023; + end else if ((7'd41 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101063; + end else if ((7'd39 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101103; + end else if ((7'd37 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101143; + end else if ((7'd35 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101183; + end else if ((7'd33 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101223; + end else if ((7'd31 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101263; + end else if ((7'd29 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101303; + end else if ((7'd27 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101343; + end else if ((7'd25 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101383; + end else if ((7'd23 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101423; + end else if ((7'd21 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101463; + end else if ((7'd19 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101503; + end else if ((7'd17 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101543; + end else if ((7'd15 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101583; + end else if ((7'd13 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101623; + end else if ((7'd11 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101663; + end else if ((7'd9 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101703; + end else if ((7'd7 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101743; + end else if ((7'd5 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101783; + end else if ((7'd3 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101823; + end else if ((7'd1 == add_ln1116_15_reg_144296)) begin + phi_ln1116_15_reg_95381 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state237 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_10425)) begin + phi_ln1116_16_reg_91651 <= reg_100598; + end else if ((7'd126 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100558; + end else if ((7'd124 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100478; + end else if ((7'd122 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100398; + end else if ((7'd120 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100318; + end else if ((7'd118 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100238; + end else if ((7'd116 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100158; + end else if ((7'd114 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100078; + end else if ((7'd112 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99998; + end else if ((7'd110 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99918; + end else if ((7'd108 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99838; + end else if ((7'd106 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99758; + end else if ((7'd104 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99678; + end else if ((7'd102 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99598; + end else if ((7'd100 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99518; + end else if ((7'd98 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99438; + end else if ((7'd96 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99358; + end else if ((7'd94 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100438; + end else if ((7'd92 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100118; + end else if ((7'd90 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99798; + end else if ((7'd88 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99478; + end else if ((7'd86 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99958; + end else if ((7'd84 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99318; + end else if ((7'd82 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99638; + end else if ((7'd80 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100278; + end else if ((7'd78 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99398; + end else if ((7'd76 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99558; + end else if ((7'd74 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99718; + end else if ((7'd72 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99878; + end else if ((7'd70 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100038; + end else if ((7'd68 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100198; + end else if ((7'd66 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100358; + end else if ((7'd64 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100518; + end else if ((7'd62 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99338; + end else if ((7'd60 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99378; + end else if ((7'd58 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99418; + end else if ((7'd56 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99458; + end else if ((7'd54 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99498; + end else if ((7'd52 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99538; + end else if ((7'd50 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99578; + end else if ((7'd48 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99618; + end else if ((7'd46 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99658; + end else if ((7'd44 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99698; + end else if ((7'd42 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99738; + end else if ((7'd40 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99778; + end else if ((7'd38 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99818; + end else if ((7'd36 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99858; + end else if ((7'd34 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99898; + end else if ((7'd32 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99938; + end else if ((7'd30 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_99978; + end else if ((7'd28 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100018; + end else if ((7'd26 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100058; + end else if ((7'd24 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100098; + end else if ((7'd22 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100138; + end else if ((7'd20 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100178; + end else if ((7'd18 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100218; + end else if ((7'd16 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100258; + end else if ((7'd14 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100298; + end else if ((7'd12 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100338; + end else if ((7'd10 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100378; + end else if ((7'd8 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100418; + end else if ((7'd6 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100458; + end else if ((7'd4 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100498; + end else if ((7'd2 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100538; + end else if ((7'd0 == add_ln1116_16_reg_133103)) begin + phi_ln1116_16_reg_91651 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state388 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_10872)) begin + phi_ln1116_17_reg_91945 <= reg_100598; + end else if ((7'd125 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101843; + end else if ((7'd123 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101763; + end else if ((7'd121 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101683; + end else if ((7'd119 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101603; + end else if ((7'd117 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101523; + end else if ((7'd115 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101443; + end else if ((7'd113 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101363; + end else if ((7'd111 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101283; + end else if ((7'd109 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101203; + end else if ((7'd107 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101123; + end else if ((7'd105 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101043; + end else if ((7'd103 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100963; + end else if ((7'd101 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100883; + end else if ((7'd99 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100803; + end else if ((7'd97 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100723; + end else if ((7'd95 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100643; + end else if ((7'd93 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101643; + end else if ((7'd91 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101323; + end else if ((7'd89 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101003; + end else if ((7'd87 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100683; + end else if ((7'd85 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100843; + end else if ((7'd83 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101483; + end else if ((7'd81 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101163; + end else if ((7'd79 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101803; + end else if ((7'd77 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100763; + end else if ((7'd75 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100923; + end else if ((7'd73 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101083; + end else if ((7'd71 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101243; + end else if ((7'd69 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101403; + end else if ((7'd67 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101563; + end else if ((7'd65 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101723; + end else if ((7'd63 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101883; + end else if ((7'd61 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100663; + end else if ((7'd59 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100703; + end else if ((7'd57 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100743; + end else if ((7'd55 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100783; + end else if ((7'd53 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100823; + end else if ((7'd51 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100863; + end else if ((7'd49 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100903; + end else if ((7'd47 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100943; + end else if ((7'd45 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_100983; + end else if ((7'd43 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101023; + end else if ((7'd41 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101063; + end else if ((7'd39 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101103; + end else if ((7'd37 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101143; + end else if ((7'd35 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101183; + end else if ((7'd33 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101223; + end else if ((7'd31 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101263; + end else if ((7'd29 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101303; + end else if ((7'd27 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101343; + end else if ((7'd25 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101383; + end else if ((7'd23 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101423; + end else if ((7'd21 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101463; + end else if ((7'd19 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101503; + end else if ((7'd17 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101543; + end else if ((7'd15 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101583; + end else if ((7'd13 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101623; + end else if ((7'd11 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101663; + end else if ((7'd9 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101703; + end else if ((7'd7 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101743; + end else if ((7'd5 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101783; + end else if ((7'd3 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101823; + end else if ((7'd1 == add_ln1116_17_reg_133975)) begin + phi_ln1116_17_reg_91945 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_13056)) begin + phi_ln1116_18_reg_94035 <= reg_100598; + end else if ((7'd126 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100558; + end else if ((7'd124 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100478; + end else if ((7'd122 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100398; + end else if ((7'd120 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100318; + end else if ((7'd118 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100238; + end else if ((7'd116 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100158; + end else if ((7'd114 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100078; + end else if ((7'd112 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99998; + end else if ((7'd110 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99918; + end else if ((7'd108 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99838; + end else if ((7'd106 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99758; + end else if ((7'd104 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99678; + end else if ((7'd102 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99598; + end else if ((7'd100 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99518; + end else if ((7'd98 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99438; + end else if ((7'd96 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99358; + end else if ((7'd94 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100438; + end else if ((7'd92 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100118; + end else if ((7'd90 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99798; + end else if ((7'd88 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99478; + end else if ((7'd86 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99958; + end else if ((7'd84 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99318; + end else if ((7'd82 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99638; + end else if ((7'd80 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100278; + end else if ((7'd78 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99398; + end else if ((7'd76 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99558; + end else if ((7'd74 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99718; + end else if ((7'd72 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99878; + end else if ((7'd70 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100038; + end else if ((7'd68 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100198; + end else if ((7'd66 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100358; + end else if ((7'd64 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100518; + end else if ((7'd62 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99338; + end else if ((7'd60 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99378; + end else if ((7'd58 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99418; + end else if ((7'd56 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99458; + end else if ((7'd54 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99498; + end else if ((7'd52 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99538; + end else if ((7'd50 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99578; + end else if ((7'd48 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99618; + end else if ((7'd46 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99658; + end else if ((7'd44 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99698; + end else if ((7'd42 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99738; + end else if ((7'd40 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99778; + end else if ((7'd38 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99818; + end else if ((7'd36 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99858; + end else if ((7'd34 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99898; + end else if ((7'd32 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99938; + end else if ((7'd30 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_99978; + end else if ((7'd28 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100018; + end else if ((7'd26 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100058; + end else if ((7'd24 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100098; + end else if ((7'd22 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100138; + end else if ((7'd20 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100178; + end else if ((7'd18 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100218; + end else if ((7'd16 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100258; + end else if ((7'd14 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100298; + end else if ((7'd12 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100338; + end else if ((7'd10 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100378; + end else if ((7'd8 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100418; + end else if ((7'd6 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100458; + end else if ((7'd4 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100498; + end else if ((7'd2 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100538; + end else if ((7'd0 == add_ln1116_18_reg_140281)) begin + phi_ln1116_18_reg_94035 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state842 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_11772)) begin + phi_ln1116_19_reg_92837 <= reg_100598; + end else if ((7'd126 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100558; + end else if ((7'd124 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100478; + end else if ((7'd122 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100398; + end else if ((7'd120 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100318; + end else if ((7'd118 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100238; + end else if ((7'd116 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100158; + end else if ((7'd114 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100078; + end else if ((7'd112 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99998; + end else if ((7'd110 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99918; + end else if ((7'd108 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99838; + end else if ((7'd106 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99758; + end else if ((7'd104 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99678; + end else if ((7'd102 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99598; + end else if ((7'd100 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99518; + end else if ((7'd98 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99438; + end else if ((7'd96 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99358; + end else if ((7'd94 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100438; + end else if ((7'd92 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100118; + end else if ((7'd90 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99798; + end else if ((7'd88 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99478; + end else if ((7'd86 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99958; + end else if ((7'd84 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99318; + end else if ((7'd82 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99638; + end else if ((7'd80 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100278; + end else if ((7'd78 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99398; + end else if ((7'd76 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99558; + end else if ((7'd74 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99718; + end else if ((7'd72 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99878; + end else if ((7'd70 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100038; + end else if ((7'd68 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100198; + end else if ((7'd66 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100358; + end else if ((7'd64 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100518; + end else if ((7'd62 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99338; + end else if ((7'd60 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99378; + end else if ((7'd58 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99418; + end else if ((7'd56 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99458; + end else if ((7'd54 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99498; + end else if ((7'd52 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99538; + end else if ((7'd50 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99578; + end else if ((7'd48 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99618; + end else if ((7'd46 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99658; + end else if ((7'd44 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99698; + end else if ((7'd42 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99738; + end else if ((7'd40 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99778; + end else if ((7'd38 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99818; + end else if ((7'd36 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99858; + end else if ((7'd34 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99898; + end else if ((7'd32 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99938; + end else if ((7'd30 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_99978; + end else if ((7'd28 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100018; + end else if ((7'd26 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100058; + end else if ((7'd24 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100098; + end else if ((7'd22 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100138; + end else if ((7'd20 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100178; + end else if ((7'd18 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100218; + end else if ((7'd16 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100258; + end else if ((7'd14 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100298; + end else if ((7'd12 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100338; + end else if ((7'd10 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100378; + end else if ((7'd8 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100418; + end else if ((7'd6 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100458; + end else if ((7'd4 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100498; + end else if ((7'd2 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100538; + end else if ((7'd0 == add_ln1116_19_reg_136674)) begin + phi_ln1116_19_reg_92837 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_12669)) begin + phi_ln1116_1_reg_93615 <= reg_100598; + end else if ((7'd126 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100558; + end else if ((7'd124 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100478; + end else if ((7'd122 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100398; + end else if ((7'd120 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100318; + end else if ((7'd118 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100238; + end else if ((7'd116 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100158; + end else if ((7'd114 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100078; + end else if ((7'd112 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99998; + end else if ((7'd110 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99918; + end else if ((7'd108 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99838; + end else if ((7'd106 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99758; + end else if ((7'd104 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99678; + end else if ((7'd102 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99598; + end else if ((7'd100 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99518; + end else if ((7'd98 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99438; + end else if ((7'd96 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99358; + end else if ((7'd94 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100438; + end else if ((7'd92 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100118; + end else if ((7'd90 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99798; + end else if ((7'd88 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99478; + end else if ((7'd86 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99958; + end else if ((7'd84 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99318; + end else if ((7'd82 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99638; + end else if ((7'd80 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100278; + end else if ((7'd78 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99398; + end else if ((7'd76 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99558; + end else if ((7'd74 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99718; + end else if ((7'd72 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99878; + end else if ((7'd70 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100038; + end else if ((7'd68 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100198; + end else if ((7'd66 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100358; + end else if ((7'd64 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100518; + end else if ((7'd62 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99338; + end else if ((7'd60 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99378; + end else if ((7'd58 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99418; + end else if ((7'd56 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99458; + end else if ((7'd54 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99498; + end else if ((7'd52 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99538; + end else if ((7'd50 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99578; + end else if ((7'd48 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99618; + end else if ((7'd46 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99658; + end else if ((7'd44 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99698; + end else if ((7'd42 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99738; + end else if ((7'd40 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99778; + end else if ((7'd38 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99818; + end else if ((7'd36 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99858; + end else if ((7'd34 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99898; + end else if ((7'd32 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99938; + end else if ((7'd30 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_99978; + end else if ((7'd28 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100018; + end else if ((7'd26 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100058; + end else if ((7'd24 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100098; + end else if ((7'd22 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100138; + end else if ((7'd20 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100178; + end else if ((7'd18 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100218; + end else if ((7'd16 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100258; + end else if ((7'd14 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100298; + end else if ((7'd12 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100338; + end else if ((7'd10 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100378; + end else if ((7'd8 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100418; + end else if ((7'd6 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100458; + end else if ((7'd4 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100498; + end else if ((7'd2 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100538; + end else if ((7'd0 == add_ln1116_1_reg_138989)) begin + phi_ln1116_1_reg_93615 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1599 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_13440)) begin + phi_ln1116_20_reg_94329 <= reg_100598; + end else if ((7'd125 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101843; + end else if ((7'd123 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101763; + end else if ((7'd121 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101683; + end else if ((7'd119 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101603; + end else if ((7'd117 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101523; + end else if ((7'd115 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101443; + end else if ((7'd113 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101363; + end else if ((7'd111 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101283; + end else if ((7'd109 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101203; + end else if ((7'd107 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101123; + end else if ((7'd105 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101043; + end else if ((7'd103 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100963; + end else if ((7'd101 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100883; + end else if ((7'd99 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100803; + end else if ((7'd97 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100723; + end else if ((7'd95 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100643; + end else if ((7'd93 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101643; + end else if ((7'd91 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101323; + end else if ((7'd89 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101003; + end else if ((7'd87 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100683; + end else if ((7'd85 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100843; + end else if ((7'd83 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101483; + end else if ((7'd81 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101163; + end else if ((7'd79 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101803; + end else if ((7'd77 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100763; + end else if ((7'd75 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100923; + end else if ((7'd73 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101083; + end else if ((7'd71 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101243; + end else if ((7'd69 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101403; + end else if ((7'd67 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101563; + end else if ((7'd65 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101723; + end else if ((7'd63 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101883; + end else if ((7'd61 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100663; + end else if ((7'd59 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100703; + end else if ((7'd57 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100743; + end else if ((7'd55 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100783; + end else if ((7'd53 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100823; + end else if ((7'd51 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100863; + end else if ((7'd49 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100903; + end else if ((7'd47 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100943; + end else if ((7'd45 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_100983; + end else if ((7'd43 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101023; + end else if ((7'd41 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101063; + end else if ((7'd39 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101103; + end else if ((7'd37 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101143; + end else if ((7'd35 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101183; + end else if ((7'd33 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101223; + end else if ((7'd31 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101263; + end else if ((7'd29 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101303; + end else if ((7'd27 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101343; + end else if ((7'd25 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101383; + end else if ((7'd23 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101423; + end else if ((7'd21 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101463; + end else if ((7'd19 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101503; + end else if ((7'd17 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101543; + end else if ((7'd15 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101583; + end else if ((7'd13 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101623; + end else if ((7'd11 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101663; + end else if ((7'd9 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101703; + end else if ((7'd7 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101743; + end else if ((7'd5 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101783; + end else if ((7'd3 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101823; + end else if ((7'd1 == add_ln1116_20_reg_141148)) begin + phi_ln1116_20_reg_94329 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state993 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_12156)) begin + phi_ln1116_21_reg_93131 <= reg_100598; + end else if ((7'd125 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101843; + end else if ((7'd123 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101763; + end else if ((7'd121 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101683; + end else if ((7'd119 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101603; + end else if ((7'd117 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101523; + end else if ((7'd115 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101443; + end else if ((7'd113 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101363; + end else if ((7'd111 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101283; + end else if ((7'd109 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101203; + end else if ((7'd107 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101123; + end else if ((7'd105 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101043; + end else if ((7'd103 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100963; + end else if ((7'd101 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100883; + end else if ((7'd99 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100803; + end else if ((7'd97 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100723; + end else if ((7'd95 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100643; + end else if ((7'd93 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101643; + end else if ((7'd91 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101323; + end else if ((7'd89 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101003; + end else if ((7'd87 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100683; + end else if ((7'd85 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100843; + end else if ((7'd83 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101483; + end else if ((7'd81 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101163; + end else if ((7'd79 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101803; + end else if ((7'd77 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100763; + end else if ((7'd75 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100923; + end else if ((7'd73 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101083; + end else if ((7'd71 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101243; + end else if ((7'd69 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101403; + end else if ((7'd67 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101563; + end else if ((7'd65 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101723; + end else if ((7'd63 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101883; + end else if ((7'd61 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100663; + end else if ((7'd59 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100703; + end else if ((7'd57 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100743; + end else if ((7'd55 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100783; + end else if ((7'd53 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100823; + end else if ((7'd51 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100863; + end else if ((7'd49 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100903; + end else if ((7'd47 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100943; + end else if ((7'd45 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_100983; + end else if ((7'd43 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101023; + end else if ((7'd41 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101063; + end else if ((7'd39 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101103; + end else if ((7'd37 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101143; + end else if ((7'd35 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101183; + end else if ((7'd33 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101223; + end else if ((7'd31 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101263; + end else if ((7'd29 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101303; + end else if ((7'd27 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101343; + end else if ((7'd25 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101383; + end else if ((7'd23 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101423; + end else if ((7'd21 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101463; + end else if ((7'd19 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101503; + end else if ((7'd17 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101543; + end else if ((7'd15 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101583; + end else if ((7'd13 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101623; + end else if ((7'd11 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101663; + end else if ((7'd9 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101703; + end else if ((7'd7 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101743; + end else if ((7'd5 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101783; + end else if ((7'd3 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101823; + end else if ((7'd1 == add_ln1116_21_reg_137546)) begin + phi_ln1116_21_reg_93131 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state465 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_11064)) begin + phi_ln1116_22_reg_92091 <= reg_100598; + end else if ((7'd125 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101843; + end else if ((7'd123 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101763; + end else if ((7'd121 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101683; + end else if ((7'd119 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101603; + end else if ((7'd117 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101523; + end else if ((7'd115 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101443; + end else if ((7'd113 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101363; + end else if ((7'd111 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101283; + end else if ((7'd109 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101203; + end else if ((7'd107 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101123; + end else if ((7'd105 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101043; + end else if ((7'd103 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100963; + end else if ((7'd101 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100883; + end else if ((7'd99 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100803; + end else if ((7'd97 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100723; + end else if ((7'd95 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100643; + end else if ((7'd93 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101643; + end else if ((7'd91 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101323; + end else if ((7'd89 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101003; + end else if ((7'd87 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100683; + end else if ((7'd85 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100843; + end else if ((7'd83 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101483; + end else if ((7'd81 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101163; + end else if ((7'd79 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101803; + end else if ((7'd77 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100763; + end else if ((7'd75 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100923; + end else if ((7'd73 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101083; + end else if ((7'd71 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101243; + end else if ((7'd69 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101403; + end else if ((7'd67 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101563; + end else if ((7'd65 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101723; + end else if ((7'd63 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101883; + end else if ((7'd61 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100663; + end else if ((7'd59 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100703; + end else if ((7'd57 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100743; + end else if ((7'd55 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100783; + end else if ((7'd53 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100823; + end else if ((7'd51 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100863; + end else if ((7'd49 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100903; + end else if ((7'd47 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100943; + end else if ((7'd45 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_100983; + end else if ((7'd43 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101023; + end else if ((7'd41 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101063; + end else if ((7'd39 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101103; + end else if ((7'd37 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101143; + end else if ((7'd35 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101183; + end else if ((7'd33 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101223; + end else if ((7'd31 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101263; + end else if ((7'd29 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101303; + end else if ((7'd27 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101343; + end else if ((7'd25 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101383; + end else if ((7'd23 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101423; + end else if ((7'd21 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101463; + end else if ((7'd19 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101503; + end else if ((7'd17 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101543; + end else if ((7'd15 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101583; + end else if ((7'd13 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101623; + end else if ((7'd11 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101663; + end else if ((7'd9 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101703; + end else if ((7'd7 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101743; + end else if ((7'd5 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101783; + end else if ((7'd3 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101823; + end else if ((7'd1 == add_ln1116_22_reg_134445)) begin + phi_ln1116_22_reg_92091 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2052 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_14340)) begin + phi_ln1116_23_reg_95221 <= reg_100598; + end else if ((7'd126 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100558; + end else if ((7'd124 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100478; + end else if ((7'd122 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100398; + end else if ((7'd120 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100318; + end else if ((7'd118 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100238; + end else if ((7'd116 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100158; + end else if ((7'd114 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100078; + end else if ((7'd112 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99998; + end else if ((7'd110 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99918; + end else if ((7'd108 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99838; + end else if ((7'd106 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99758; + end else if ((7'd104 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99678; + end else if ((7'd102 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99598; + end else if ((7'd100 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99518; + end else if ((7'd98 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99438; + end else if ((7'd96 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99358; + end else if ((7'd94 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100438; + end else if ((7'd92 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100118; + end else if ((7'd90 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99798; + end else if ((7'd88 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99478; + end else if ((7'd86 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99958; + end else if ((7'd84 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99318; + end else if ((7'd82 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99638; + end else if ((7'd80 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100278; + end else if ((7'd78 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99398; + end else if ((7'd76 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99558; + end else if ((7'd74 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99718; + end else if ((7'd72 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99878; + end else if ((7'd70 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100038; + end else if ((7'd68 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100198; + end else if ((7'd66 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100358; + end else if ((7'd64 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100518; + end else if ((7'd62 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99338; + end else if ((7'd60 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99378; + end else if ((7'd58 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99418; + end else if ((7'd56 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99458; + end else if ((7'd54 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99498; + end else if ((7'd52 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99538; + end else if ((7'd50 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99578; + end else if ((7'd48 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99618; + end else if ((7'd46 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99658; + end else if ((7'd44 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99698; + end else if ((7'd42 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99738; + end else if ((7'd40 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99778; + end else if ((7'd38 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99818; + end else if ((7'd36 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99858; + end else if ((7'd34 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99898; + end else if ((7'd32 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99938; + end else if ((7'd30 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_99978; + end else if ((7'd28 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100018; + end else if ((7'd26 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100058; + end else if ((7'd24 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100098; + end else if ((7'd22 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100138; + end else if ((7'd20 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100178; + end else if ((7'd18 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100218; + end else if ((7'd16 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100258; + end else if ((7'd14 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100298; + end else if ((7'd12 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100338; + end else if ((7'd10 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100378; + end else if ((7'd8 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100418; + end else if ((7'd6 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100458; + end else if ((7'd4 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100498; + end else if ((7'd2 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100538; + end else if ((7'd0 == add_ln1116_23_reg_143834)) begin + phi_ln1116_23_reg_95221 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2203 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_14724)) begin + phi_ln1116_24_reg_95515 <= reg_100598; + end else if ((7'd125 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101843; + end else if ((7'd123 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101763; + end else if ((7'd121 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101683; + end else if ((7'd119 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101603; + end else if ((7'd117 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101523; + end else if ((7'd115 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101443; + end else if ((7'd113 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101363; + end else if ((7'd111 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101283; + end else if ((7'd109 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101203; + end else if ((7'd107 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101123; + end else if ((7'd105 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101043; + end else if ((7'd103 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100963; + end else if ((7'd101 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100883; + end else if ((7'd99 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100803; + end else if ((7'd97 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100723; + end else if ((7'd95 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100643; + end else if ((7'd93 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101643; + end else if ((7'd91 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101323; + end else if ((7'd89 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101003; + end else if ((7'd87 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100683; + end else if ((7'd85 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100843; + end else if ((7'd83 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101483; + end else if ((7'd81 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101163; + end else if ((7'd79 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101803; + end else if ((7'd77 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100763; + end else if ((7'd75 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100923; + end else if ((7'd73 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101083; + end else if ((7'd71 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101243; + end else if ((7'd69 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101403; + end else if ((7'd67 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101563; + end else if ((7'd65 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101723; + end else if ((7'd63 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101883; + end else if ((7'd61 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100663; + end else if ((7'd59 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100703; + end else if ((7'd57 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100743; + end else if ((7'd55 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100783; + end else if ((7'd53 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100823; + end else if ((7'd51 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100863; + end else if ((7'd49 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100903; + end else if ((7'd47 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100943; + end else if ((7'd45 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_100983; + end else if ((7'd43 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101023; + end else if ((7'd41 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101063; + end else if ((7'd39 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101103; + end else if ((7'd37 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101143; + end else if ((7'd35 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101183; + end else if ((7'd33 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101223; + end else if ((7'd31 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101263; + end else if ((7'd29 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101303; + end else if ((7'd27 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101343; + end else if ((7'd25 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101383; + end else if ((7'd23 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101423; + end else if ((7'd21 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101463; + end else if ((7'd19 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101503; + end else if ((7'd17 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101543; + end else if ((7'd15 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101583; + end else if ((7'd13 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101623; + end else if ((7'd11 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101663; + end else if ((7'd9 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101703; + end else if ((7'd7 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101743; + end else if ((7'd5 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101783; + end else if ((7'd3 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101823; + end else if ((7'd1 == add_ln1116_24_reg_144701)) begin + phi_ln1116_24_reg_95515 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_13632)) begin + phi_ln1116_25_reg_94475 <= reg_100598; + end else if ((7'd125 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101843; + end else if ((7'd123 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101763; + end else if ((7'd121 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101683; + end else if ((7'd119 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101603; + end else if ((7'd117 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101523; + end else if ((7'd115 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101443; + end else if ((7'd113 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101363; + end else if ((7'd111 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101283; + end else if ((7'd109 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101203; + end else if ((7'd107 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101123; + end else if ((7'd105 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101043; + end else if ((7'd103 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100963; + end else if ((7'd101 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100883; + end else if ((7'd99 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100803; + end else if ((7'd97 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100723; + end else if ((7'd95 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100643; + end else if ((7'd93 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101643; + end else if ((7'd91 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101323; + end else if ((7'd89 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101003; + end else if ((7'd87 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100683; + end else if ((7'd85 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100843; + end else if ((7'd83 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101483; + end else if ((7'd81 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101163; + end else if ((7'd79 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101803; + end else if ((7'd77 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100763; + end else if ((7'd75 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100923; + end else if ((7'd73 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101083; + end else if ((7'd71 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101243; + end else if ((7'd69 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101403; + end else if ((7'd67 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101563; + end else if ((7'd65 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101723; + end else if ((7'd63 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101883; + end else if ((7'd61 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100663; + end else if ((7'd59 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100703; + end else if ((7'd57 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100743; + end else if ((7'd55 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100783; + end else if ((7'd53 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100823; + end else if ((7'd51 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100863; + end else if ((7'd49 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100903; + end else if ((7'd47 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100943; + end else if ((7'd45 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_100983; + end else if ((7'd43 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101023; + end else if ((7'd41 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101063; + end else if ((7'd39 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101103; + end else if ((7'd37 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101143; + end else if ((7'd35 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101183; + end else if ((7'd33 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101223; + end else if ((7'd31 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101263; + end else if ((7'd29 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101303; + end else if ((7'd27 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101343; + end else if ((7'd25 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101383; + end else if ((7'd23 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101423; + end else if ((7'd21 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101463; + end else if ((7'd19 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101503; + end else if ((7'd17 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101543; + end else if ((7'd15 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101583; + end else if ((7'd13 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101623; + end else if ((7'd11 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101663; + end else if ((7'd9 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101703; + end else if ((7'd7 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101743; + end else if ((7'd5 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101783; + end else if ((7'd3 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101823; + end else if ((7'd1 == add_ln1116_25_reg_141608)) begin + phi_ln1116_25_reg_94475 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1070 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_12348)) begin + phi_ln1116_26_reg_93277 <= reg_100598; + end else if ((7'd125 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101843; + end else if ((7'd123 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101763; + end else if ((7'd121 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101683; + end else if ((7'd119 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101603; + end else if ((7'd117 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101523; + end else if ((7'd115 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101443; + end else if ((7'd113 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101363; + end else if ((7'd111 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101283; + end else if ((7'd109 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101203; + end else if ((7'd107 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101123; + end else if ((7'd105 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101043; + end else if ((7'd103 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100963; + end else if ((7'd101 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100883; + end else if ((7'd99 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100803; + end else if ((7'd97 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100723; + end else if ((7'd95 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100643; + end else if ((7'd93 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101643; + end else if ((7'd91 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101323; + end else if ((7'd89 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101003; + end else if ((7'd87 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100683; + end else if ((7'd85 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100843; + end else if ((7'd83 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101483; + end else if ((7'd81 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101163; + end else if ((7'd79 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101803; + end else if ((7'd77 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100763; + end else if ((7'd75 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100923; + end else if ((7'd73 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101083; + end else if ((7'd71 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101243; + end else if ((7'd69 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101403; + end else if ((7'd67 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101563; + end else if ((7'd65 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101723; + end else if ((7'd63 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101883; + end else if ((7'd61 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100663; + end else if ((7'd59 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100703; + end else if ((7'd57 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100743; + end else if ((7'd55 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100783; + end else if ((7'd53 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100823; + end else if ((7'd51 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100863; + end else if ((7'd49 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100903; + end else if ((7'd47 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100943; + end else if ((7'd45 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_100983; + end else if ((7'd43 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101023; + end else if ((7'd41 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101063; + end else if ((7'd39 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101103; + end else if ((7'd37 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101143; + end else if ((7'd35 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101183; + end else if ((7'd33 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101223; + end else if ((7'd31 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101263; + end else if ((7'd29 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101303; + end else if ((7'd27 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101343; + end else if ((7'd25 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101383; + end else if ((7'd23 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101423; + end else if ((7'd21 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101463; + end else if ((7'd19 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101503; + end else if ((7'd17 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101543; + end else if ((7'd15 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101583; + end else if ((7'd13 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101623; + end else if ((7'd11 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101663; + end else if ((7'd9 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101703; + end else if ((7'd7 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101743; + end else if ((7'd5 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101783; + end else if ((7'd3 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101823; + end else if ((7'd1 == add_ln1116_26_reg_138016)) begin + phi_ln1116_26_reg_93277 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2280 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_14916)) begin + phi_ln1116_27_reg_95661 <= reg_100598; + end else if ((7'd125 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101843; + end else if ((7'd123 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101763; + end else if ((7'd121 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101683; + end else if ((7'd119 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101603; + end else if ((7'd117 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101523; + end else if ((7'd115 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101443; + end else if ((7'd113 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101363; + end else if ((7'd111 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101283; + end else if ((7'd109 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101203; + end else if ((7'd107 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101123; + end else if ((7'd105 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101043; + end else if ((7'd103 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100963; + end else if ((7'd101 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100883; + end else if ((7'd99 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100803; + end else if ((7'd97 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100723; + end else if ((7'd95 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100643; + end else if ((7'd93 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101643; + end else if ((7'd91 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101323; + end else if ((7'd89 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101003; + end else if ((7'd87 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100683; + end else if ((7'd85 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100843; + end else if ((7'd83 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101483; + end else if ((7'd81 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101163; + end else if ((7'd79 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101803; + end else if ((7'd77 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100763; + end else if ((7'd75 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100923; + end else if ((7'd73 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101083; + end else if ((7'd71 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101243; + end else if ((7'd69 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101403; + end else if ((7'd67 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101563; + end else if ((7'd65 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101723; + end else if ((7'd63 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101883; + end else if ((7'd61 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100663; + end else if ((7'd59 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100703; + end else if ((7'd57 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100743; + end else if ((7'd55 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100783; + end else if ((7'd53 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100823; + end else if ((7'd51 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100863; + end else if ((7'd49 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100903; + end else if ((7'd47 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100943; + end else if ((7'd45 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_100983; + end else if ((7'd43 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101023; + end else if ((7'd41 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101063; + end else if ((7'd39 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101103; + end else if ((7'd37 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101143; + end else if ((7'd35 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101183; + end else if ((7'd33 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101223; + end else if ((7'd31 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101263; + end else if ((7'd29 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101303; + end else if ((7'd27 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101343; + end else if ((7'd25 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101383; + end else if ((7'd23 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101423; + end else if ((7'd21 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101463; + end else if ((7'd19 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101503; + end else if ((7'd17 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101543; + end else if ((7'd15 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101583; + end else if ((7'd13 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101623; + end else if ((7'd11 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101663; + end else if ((7'd9 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101703; + end else if ((7'd7 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101743; + end else if ((7'd5 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101783; + end else if ((7'd3 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101823; + end else if ((7'd1 == add_ln1116_27_reg_145171)) begin + phi_ln1116_27_reg_95661 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state538 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_11256)) begin + phi_ln1116_28_reg_92225 <= reg_100598; + end else if ((7'd125 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101843; + end else if ((7'd123 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101763; + end else if ((7'd121 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101683; + end else if ((7'd119 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101603; + end else if ((7'd117 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101523; + end else if ((7'd115 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101443; + end else if ((7'd113 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101363; + end else if ((7'd111 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101283; + end else if ((7'd109 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101203; + end else if ((7'd107 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101123; + end else if ((7'd105 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101043; + end else if ((7'd103 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100963; + end else if ((7'd101 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100883; + end else if ((7'd99 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100803; + end else if ((7'd97 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100723; + end else if ((7'd95 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100643; + end else if ((7'd93 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101643; + end else if ((7'd91 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101323; + end else if ((7'd89 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101003; + end else if ((7'd87 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100683; + end else if ((7'd85 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100843; + end else if ((7'd83 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101483; + end else if ((7'd81 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101163; + end else if ((7'd79 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101803; + end else if ((7'd77 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100763; + end else if ((7'd75 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100923; + end else if ((7'd73 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101083; + end else if ((7'd71 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101243; + end else if ((7'd69 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101403; + end else if ((7'd67 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101563; + end else if ((7'd65 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101723; + end else if ((7'd63 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101883; + end else if ((7'd61 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100663; + end else if ((7'd59 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100703; + end else if ((7'd57 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100743; + end else if ((7'd55 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100783; + end else if ((7'd53 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100823; + end else if ((7'd51 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100863; + end else if ((7'd49 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100903; + end else if ((7'd47 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100943; + end else if ((7'd45 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_100983; + end else if ((7'd43 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101023; + end else if ((7'd41 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101063; + end else if ((7'd39 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101103; + end else if ((7'd37 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101143; + end else if ((7'd35 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101183; + end else if ((7'd33 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101223; + end else if ((7'd31 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101263; + end else if ((7'd29 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101303; + end else if ((7'd27 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101343; + end else if ((7'd25 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101383; + end else if ((7'd23 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101423; + end else if ((7'd21 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101463; + end else if ((7'd19 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101503; + end else if ((7'd17 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101543; + end else if ((7'd15 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101583; + end else if ((7'd13 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101623; + end else if ((7'd11 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101663; + end else if ((7'd9 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101703; + end else if ((7'd7 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101743; + end else if ((7'd5 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101783; + end else if ((7'd3 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101823; + end else if ((7'd1 == add_ln1116_28_reg_134850)) begin + phi_ln1116_28_reg_92225 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1749 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_13824)) begin + phi_ln1116_29_reg_94609 <= reg_100598; + end else if ((7'd125 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101843; + end else if ((7'd123 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101763; + end else if ((7'd121 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101683; + end else if ((7'd119 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101603; + end else if ((7'd117 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101523; + end else if ((7'd115 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101443; + end else if ((7'd113 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101363; + end else if ((7'd111 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101283; + end else if ((7'd109 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101203; + end else if ((7'd107 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101123; + end else if ((7'd105 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101043; + end else if ((7'd103 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100963; + end else if ((7'd101 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100883; + end else if ((7'd99 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100803; + end else if ((7'd97 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100723; + end else if ((7'd95 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100643; + end else if ((7'd93 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101643; + end else if ((7'd91 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101323; + end else if ((7'd89 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101003; + end else if ((7'd87 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100683; + end else if ((7'd85 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100843; + end else if ((7'd83 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101483; + end else if ((7'd81 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101163; + end else if ((7'd79 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101803; + end else if ((7'd77 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100763; + end else if ((7'd75 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100923; + end else if ((7'd73 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101083; + end else if ((7'd71 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101243; + end else if ((7'd69 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101403; + end else if ((7'd67 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101563; + end else if ((7'd65 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101723; + end else if ((7'd63 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101883; + end else if ((7'd61 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100663; + end else if ((7'd59 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100703; + end else if ((7'd57 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100743; + end else if ((7'd55 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100783; + end else if ((7'd53 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100823; + end else if ((7'd51 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100863; + end else if ((7'd49 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100903; + end else if ((7'd47 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100943; + end else if ((7'd45 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_100983; + end else if ((7'd43 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101023; + end else if ((7'd41 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101063; + end else if ((7'd39 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101103; + end else if ((7'd37 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101143; + end else if ((7'd35 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101183; + end else if ((7'd33 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101223; + end else if ((7'd31 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101263; + end else if ((7'd29 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101303; + end else if ((7'd27 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101343; + end else if ((7'd25 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101383; + end else if ((7'd23 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101423; + end else if ((7'd21 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101463; + end else if ((7'd19 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101503; + end else if ((7'd17 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101543; + end else if ((7'd15 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101583; + end else if ((7'd13 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101623; + end else if ((7'd11 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101663; + end else if ((7'd9 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101703; + end else if ((7'd7 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101743; + end else if ((7'd5 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101783; + end else if ((7'd3 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101823; + end else if ((7'd1 == add_ln1116_29_reg_142013)) begin + phi_ln1116_29_reg_94609 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state616 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_11385)) begin + phi_ln1116_2_reg_92417 <= reg_100598; + end else if ((7'd126 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100558; + end else if ((7'd124 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100478; + end else if ((7'd122 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100398; + end else if ((7'd120 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100318; + end else if ((7'd118 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100238; + end else if ((7'd116 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100158; + end else if ((7'd114 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100078; + end else if ((7'd112 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99998; + end else if ((7'd110 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99918; + end else if ((7'd108 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99838; + end else if ((7'd106 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99758; + end else if ((7'd104 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99678; + end else if ((7'd102 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99598; + end else if ((7'd100 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99518; + end else if ((7'd98 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99438; + end else if ((7'd96 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99358; + end else if ((7'd94 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100438; + end else if ((7'd92 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100118; + end else if ((7'd90 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99798; + end else if ((7'd88 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99478; + end else if ((7'd86 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99958; + end else if ((7'd84 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99318; + end else if ((7'd82 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99638; + end else if ((7'd80 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100278; + end else if ((7'd78 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99398; + end else if ((7'd76 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99558; + end else if ((7'd74 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99718; + end else if ((7'd72 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99878; + end else if ((7'd70 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100038; + end else if ((7'd68 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100198; + end else if ((7'd66 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100358; + end else if ((7'd64 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100518; + end else if ((7'd62 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99338; + end else if ((7'd60 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99378; + end else if ((7'd58 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99418; + end else if ((7'd56 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99458; + end else if ((7'd54 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99498; + end else if ((7'd52 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99538; + end else if ((7'd50 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99578; + end else if ((7'd48 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99618; + end else if ((7'd46 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99658; + end else if ((7'd44 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99698; + end else if ((7'd42 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99738; + end else if ((7'd40 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99778; + end else if ((7'd38 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99818; + end else if ((7'd36 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99858; + end else if ((7'd34 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99898; + end else if ((7'd32 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99938; + end else if ((7'd30 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_99978; + end else if ((7'd28 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100018; + end else if ((7'd26 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100058; + end else if ((7'd24 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100098; + end else if ((7'd22 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100138; + end else if ((7'd20 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100178; + end else if ((7'd18 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100218; + end else if ((7'd16 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100258; + end else if ((7'd14 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100298; + end else if ((7'd12 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100338; + end else if ((7'd10 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100378; + end else if ((7'd8 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100418; + end else if ((7'd6 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100458; + end else if ((7'd4 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100498; + end else if ((7'd2 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100538; + end else if ((7'd0 == add_ln1116_2_reg_135368)) begin + phi_ln1116_2_reg_92417 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1143 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_12540)) begin + phi_ln1116_30_reg_93411 <= reg_100598; + end else if ((7'd125 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101843; + end else if ((7'd123 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101763; + end else if ((7'd121 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101683; + end else if ((7'd119 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101603; + end else if ((7'd117 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101523; + end else if ((7'd115 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101443; + end else if ((7'd113 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101363; + end else if ((7'd111 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101283; + end else if ((7'd109 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101203; + end else if ((7'd107 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101123; + end else if ((7'd105 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101043; + end else if ((7'd103 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100963; + end else if ((7'd101 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100883; + end else if ((7'd99 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100803; + end else if ((7'd97 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100723; + end else if ((7'd95 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100643; + end else if ((7'd93 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101643; + end else if ((7'd91 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101323; + end else if ((7'd89 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101003; + end else if ((7'd87 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100683; + end else if ((7'd85 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100843; + end else if ((7'd83 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101483; + end else if ((7'd81 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101163; + end else if ((7'd79 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101803; + end else if ((7'd77 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100763; + end else if ((7'd75 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100923; + end else if ((7'd73 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101083; + end else if ((7'd71 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101243; + end else if ((7'd69 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101403; + end else if ((7'd67 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101563; + end else if ((7'd65 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101723; + end else if ((7'd63 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101883; + end else if ((7'd61 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100663; + end else if ((7'd59 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100703; + end else if ((7'd57 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100743; + end else if ((7'd55 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100783; + end else if ((7'd53 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100823; + end else if ((7'd51 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100863; + end else if ((7'd49 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100903; + end else if ((7'd47 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100943; + end else if ((7'd45 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_100983; + end else if ((7'd43 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101023; + end else if ((7'd41 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101063; + end else if ((7'd39 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101103; + end else if ((7'd37 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101143; + end else if ((7'd35 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101183; + end else if ((7'd33 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101223; + end else if ((7'd31 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101263; + end else if ((7'd29 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101303; + end else if ((7'd27 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101343; + end else if ((7'd25 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101383; + end else if ((7'd23 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101423; + end else if ((7'd21 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101463; + end else if ((7'd19 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101503; + end else if ((7'd17 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101543; + end else if ((7'd15 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101583; + end else if ((7'd13 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101623; + end else if ((7'd11 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101663; + end else if ((7'd9 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101703; + end else if ((7'd7 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101743; + end else if ((7'd5 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101783; + end else if ((7'd3 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101823; + end else if ((7'd1 == add_ln1116_30_reg_138421)) begin + phi_ln1116_30_reg_93411 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2353 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_15108)) begin + phi_ln1116_31_reg_95795 <= reg_100598; + end else if ((7'd125 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101843; + end else if ((7'd123 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101763; + end else if ((7'd121 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101683; + end else if ((7'd119 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101603; + end else if ((7'd117 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101523; + end else if ((7'd115 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101443; + end else if ((7'd113 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101363; + end else if ((7'd111 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101283; + end else if ((7'd109 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101203; + end else if ((7'd107 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101123; + end else if ((7'd105 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101043; + end else if ((7'd103 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100963; + end else if ((7'd101 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100883; + end else if ((7'd99 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100803; + end else if ((7'd97 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100723; + end else if ((7'd95 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100643; + end else if ((7'd93 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101643; + end else if ((7'd91 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101323; + end else if ((7'd89 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101003; + end else if ((7'd87 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100683; + end else if ((7'd85 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100843; + end else if ((7'd83 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101483; + end else if ((7'd81 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101163; + end else if ((7'd79 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101803; + end else if ((7'd77 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100763; + end else if ((7'd75 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100923; + end else if ((7'd73 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101083; + end else if ((7'd71 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101243; + end else if ((7'd69 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101403; + end else if ((7'd67 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101563; + end else if ((7'd65 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101723; + end else if ((7'd63 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101883; + end else if ((7'd61 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100663; + end else if ((7'd59 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100703; + end else if ((7'd57 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100743; + end else if ((7'd55 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100783; + end else if ((7'd53 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100823; + end else if ((7'd51 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100863; + end else if ((7'd49 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100903; + end else if ((7'd47 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100943; + end else if ((7'd45 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_100983; + end else if ((7'd43 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101023; + end else if ((7'd41 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101063; + end else if ((7'd39 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101103; + end else if ((7'd37 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101143; + end else if ((7'd35 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101183; + end else if ((7'd33 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101223; + end else if ((7'd31 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101263; + end else if ((7'd29 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101303; + end else if ((7'd27 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101343; + end else if ((7'd25 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101383; + end else if ((7'd23 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101423; + end else if ((7'd21 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101463; + end else if ((7'd19 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101503; + end else if ((7'd17 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101543; + end else if ((7'd15 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101583; + end else if ((7'd13 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101623; + end else if ((7'd11 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101663; + end else if ((7'd9 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101703; + end else if ((7'd7 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101743; + end else if ((7'd5 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101783; + end else if ((7'd3 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101823; + end else if ((7'd1 == add_ln1116_31_reg_145576)) begin + phi_ln1116_31_reg_95795 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1827 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_13953)) begin + phi_ln1116_3_reg_94801 <= reg_100598; + end else if ((7'd126 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100558; + end else if ((7'd124 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100478; + end else if ((7'd122 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100398; + end else if ((7'd120 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100318; + end else if ((7'd118 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100238; + end else if ((7'd116 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100158; + end else if ((7'd114 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100078; + end else if ((7'd112 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99998; + end else if ((7'd110 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99918; + end else if ((7'd108 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99838; + end else if ((7'd106 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99758; + end else if ((7'd104 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99678; + end else if ((7'd102 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99598; + end else if ((7'd100 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99518; + end else if ((7'd98 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99438; + end else if ((7'd96 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99358; + end else if ((7'd94 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100438; + end else if ((7'd92 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100118; + end else if ((7'd90 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99798; + end else if ((7'd88 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99478; + end else if ((7'd86 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99958; + end else if ((7'd84 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99318; + end else if ((7'd82 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99638; + end else if ((7'd80 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100278; + end else if ((7'd78 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99398; + end else if ((7'd76 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99558; + end else if ((7'd74 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99718; + end else if ((7'd72 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99878; + end else if ((7'd70 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100038; + end else if ((7'd68 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100198; + end else if ((7'd66 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100358; + end else if ((7'd64 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100518; + end else if ((7'd62 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99338; + end else if ((7'd60 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99378; + end else if ((7'd58 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99418; + end else if ((7'd56 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99458; + end else if ((7'd54 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99498; + end else if ((7'd52 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99538; + end else if ((7'd50 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99578; + end else if ((7'd48 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99618; + end else if ((7'd46 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99658; + end else if ((7'd44 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99698; + end else if ((7'd42 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99738; + end else if ((7'd40 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99778; + end else if ((7'd38 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99818; + end else if ((7'd36 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99858; + end else if ((7'd34 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99898; + end else if ((7'd32 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99938; + end else if ((7'd30 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_99978; + end else if ((7'd28 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100018; + end else if ((7'd26 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100058; + end else if ((7'd24 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100098; + end else if ((7'd22 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100138; + end else if ((7'd20 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100178; + end else if ((7'd18 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100218; + end else if ((7'd16 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100258; + end else if ((7'd14 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100298; + end else if ((7'd12 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100338; + end else if ((7'd10 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100378; + end else if ((7'd8 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100418; + end else if ((7'd6 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100458; + end else if ((7'd4 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100498; + end else if ((7'd2 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100538; + end else if ((7'd0 == add_ln1116_3_reg_142532)) begin + phi_ln1116_3_reg_94801 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state85 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_10167)) begin + phi_ln1116_4_reg_91367 <= reg_100598; + end else if ((7'd126 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100558; + end else if ((7'd124 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100478; + end else if ((7'd122 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100398; + end else if ((7'd120 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100318; + end else if ((7'd118 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100238; + end else if ((7'd116 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100158; + end else if ((7'd114 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100078; + end else if ((7'd112 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99998; + end else if ((7'd110 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99918; + end else if ((7'd108 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99838; + end else if ((7'd106 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99758; + end else if ((7'd104 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99678; + end else if ((7'd102 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99598; + end else if ((7'd100 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99518; + end else if ((7'd98 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99438; + end else if ((7'd96 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99358; + end else if ((7'd94 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100438; + end else if ((7'd92 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100118; + end else if ((7'd90 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99798; + end else if ((7'd88 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99478; + end else if ((7'd86 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99958; + end else if ((7'd84 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99318; + end else if ((7'd82 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99638; + end else if ((7'd80 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100278; + end else if ((7'd78 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99398; + end else if ((7'd76 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99558; + end else if ((7'd74 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99718; + end else if ((7'd72 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99878; + end else if ((7'd70 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100038; + end else if ((7'd68 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100198; + end else if ((7'd66 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100358; + end else if ((7'd64 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100518; + end else if ((7'd62 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99338; + end else if ((7'd60 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99378; + end else if ((7'd58 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99418; + end else if ((7'd56 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99458; + end else if ((7'd54 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99498; + end else if ((7'd52 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99538; + end else if ((7'd50 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99578; + end else if ((7'd48 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99618; + end else if ((7'd46 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99658; + end else if ((7'd44 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99698; + end else if ((7'd42 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99738; + end else if ((7'd40 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99778; + end else if ((7'd38 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99818; + end else if ((7'd36 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99858; + end else if ((7'd34 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99898; + end else if ((7'd32 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99938; + end else if ((7'd30 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_99978; + end else if ((7'd28 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100018; + end else if ((7'd26 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100058; + end else if ((7'd24 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100098; + end else if ((7'd22 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100138; + end else if ((7'd20 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100178; + end else if ((7'd18 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100218; + end else if ((7'd16 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100258; + end else if ((7'd14 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100298; + end else if ((7'd12 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100338; + end else if ((7'd10 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100378; + end else if ((7'd8 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100418; + end else if ((7'd6 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100458; + end else if ((7'd4 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100498; + end else if ((7'd2 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100538; + end else if ((7'd0 == add_ln1116_4_reg_132207)) begin + phi_ln1116_4_reg_91367 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1296 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_12798)) begin + phi_ln1116_5_reg_93751 <= reg_100598; + end else if ((7'd126 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100558; + end else if ((7'd124 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100478; + end else if ((7'd122 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100398; + end else if ((7'd120 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100318; + end else if ((7'd118 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100238; + end else if ((7'd116 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100158; + end else if ((7'd114 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100078; + end else if ((7'd112 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99998; + end else if ((7'd110 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99918; + end else if ((7'd108 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99838; + end else if ((7'd106 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99758; + end else if ((7'd104 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99678; + end else if ((7'd102 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99598; + end else if ((7'd100 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99518; + end else if ((7'd98 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99438; + end else if ((7'd96 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99358; + end else if ((7'd94 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100438; + end else if ((7'd92 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100118; + end else if ((7'd90 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99798; + end else if ((7'd88 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99478; + end else if ((7'd86 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99958; + end else if ((7'd84 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99318; + end else if ((7'd82 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99638; + end else if ((7'd80 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100278; + end else if ((7'd78 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99398; + end else if ((7'd76 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99558; + end else if ((7'd74 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99718; + end else if ((7'd72 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99878; + end else if ((7'd70 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100038; + end else if ((7'd68 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100198; + end else if ((7'd66 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100358; + end else if ((7'd64 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100518; + end else if ((7'd62 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99338; + end else if ((7'd60 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99378; + end else if ((7'd58 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99418; + end else if ((7'd56 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99458; + end else if ((7'd54 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99498; + end else if ((7'd52 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99538; + end else if ((7'd50 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99578; + end else if ((7'd48 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99618; + end else if ((7'd46 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99658; + end else if ((7'd44 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99698; + end else if ((7'd42 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99738; + end else if ((7'd40 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99778; + end else if ((7'd38 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99818; + end else if ((7'd36 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99858; + end else if ((7'd34 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99898; + end else if ((7'd32 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99938; + end else if ((7'd30 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_99978; + end else if ((7'd28 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100018; + end else if ((7'd26 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100058; + end else if ((7'd24 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100098; + end else if ((7'd22 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100138; + end else if ((7'd20 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100178; + end else if ((7'd18 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100218; + end else if ((7'd16 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100258; + end else if ((7'd14 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100298; + end else if ((7'd12 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100338; + end else if ((7'd10 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100378; + end else if ((7'd8 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100418; + end else if ((7'd6 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100458; + end else if ((7'd4 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100498; + end else if ((7'd2 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100538; + end else if ((7'd0 == add_ln1116_5_reg_139399)) begin + phi_ln1116_5_reg_93751 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state690 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_11514)) begin + phi_ln1116_6_reg_92553 <= reg_100598; + end else if ((7'd126 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100558; + end else if ((7'd124 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100478; + end else if ((7'd122 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100398; + end else if ((7'd120 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100318; + end else if ((7'd118 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100238; + end else if ((7'd116 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100158; + end else if ((7'd114 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100078; + end else if ((7'd112 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99998; + end else if ((7'd110 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99918; + end else if ((7'd108 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99838; + end else if ((7'd106 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99758; + end else if ((7'd104 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99678; + end else if ((7'd102 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99598; + end else if ((7'd100 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99518; + end else if ((7'd98 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99438; + end else if ((7'd96 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99358; + end else if ((7'd94 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100438; + end else if ((7'd92 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100118; + end else if ((7'd90 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99798; + end else if ((7'd88 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99478; + end else if ((7'd86 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99958; + end else if ((7'd84 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99318; + end else if ((7'd82 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99638; + end else if ((7'd80 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100278; + end else if ((7'd78 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99398; + end else if ((7'd76 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99558; + end else if ((7'd74 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99718; + end else if ((7'd72 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99878; + end else if ((7'd70 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100038; + end else if ((7'd68 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100198; + end else if ((7'd66 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100358; + end else if ((7'd64 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100518; + end else if ((7'd62 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99338; + end else if ((7'd60 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99378; + end else if ((7'd58 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99418; + end else if ((7'd56 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99458; + end else if ((7'd54 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99498; + end else if ((7'd52 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99538; + end else if ((7'd50 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99578; + end else if ((7'd48 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99618; + end else if ((7'd46 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99658; + end else if ((7'd44 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99698; + end else if ((7'd42 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99738; + end else if ((7'd40 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99778; + end else if ((7'd38 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99818; + end else if ((7'd36 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99858; + end else if ((7'd34 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99898; + end else if ((7'd32 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99938; + end else if ((7'd30 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_99978; + end else if ((7'd28 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100018; + end else if ((7'd26 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100058; + end else if ((7'd24 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100098; + end else if ((7'd22 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100138; + end else if ((7'd20 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100178; + end else if ((7'd18 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100218; + end else if ((7'd16 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100258; + end else if ((7'd14 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100298; + end else if ((7'd12 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100338; + end else if ((7'd10 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100378; + end else if ((7'd8 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100418; + end else if ((7'd6 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100458; + end else if ((7'd4 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100498; + end else if ((7'd2 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100538; + end else if ((7'd0 == add_ln1116_6_reg_135778)) begin + phi_ln1116_6_reg_92553 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state162 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_10296)) begin + phi_ln1116_7_reg_91515 <= reg_100598; + end else if ((7'd126 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100558; + end else if ((7'd124 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100478; + end else if ((7'd122 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100398; + end else if ((7'd120 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100318; + end else if ((7'd118 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100238; + end else if ((7'd116 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100158; + end else if ((7'd114 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100078; + end else if ((7'd112 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99998; + end else if ((7'd110 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99918; + end else if ((7'd108 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99838; + end else if ((7'd106 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99758; + end else if ((7'd104 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99678; + end else if ((7'd102 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99598; + end else if ((7'd100 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99518; + end else if ((7'd98 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99438; + end else if ((7'd96 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99358; + end else if ((7'd94 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100438; + end else if ((7'd92 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100118; + end else if ((7'd90 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99798; + end else if ((7'd88 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99478; + end else if ((7'd86 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99958; + end else if ((7'd84 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99318; + end else if ((7'd82 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99638; + end else if ((7'd80 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100278; + end else if ((7'd78 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99398; + end else if ((7'd76 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99558; + end else if ((7'd74 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99718; + end else if ((7'd72 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99878; + end else if ((7'd70 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100038; + end else if ((7'd68 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100198; + end else if ((7'd66 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100358; + end else if ((7'd64 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100518; + end else if ((7'd62 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99338; + end else if ((7'd60 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99378; + end else if ((7'd58 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99418; + end else if ((7'd56 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99458; + end else if ((7'd54 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99498; + end else if ((7'd52 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99538; + end else if ((7'd50 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99578; + end else if ((7'd48 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99618; + end else if ((7'd46 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99658; + end else if ((7'd44 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99698; + end else if ((7'd42 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99738; + end else if ((7'd40 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99778; + end else if ((7'd38 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99818; + end else if ((7'd36 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99858; + end else if ((7'd34 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99898; + end else if ((7'd32 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99938; + end else if ((7'd30 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_99978; + end else if ((7'd28 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100018; + end else if ((7'd26 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100058; + end else if ((7'd24 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100098; + end else if ((7'd22 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100138; + end else if ((7'd20 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100178; + end else if ((7'd18 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100218; + end else if ((7'd16 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100258; + end else if ((7'd14 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100298; + end else if ((7'd12 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100338; + end else if ((7'd10 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100378; + end else if ((7'd8 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100418; + end else if ((7'd6 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100458; + end else if ((7'd4 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100498; + end else if ((7'd2 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100538; + end else if ((7'd0 == add_ln1116_7_reg_132705)) begin + phi_ln1116_7_reg_91515 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state315 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_10680)) begin + phi_ln1116_8_reg_91811 <= reg_100598; + end else if ((7'd125 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101843; + end else if ((7'd123 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101763; + end else if ((7'd121 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101683; + end else if ((7'd119 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101603; + end else if ((7'd117 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101523; + end else if ((7'd115 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101443; + end else if ((7'd113 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101363; + end else if ((7'd111 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101283; + end else if ((7'd109 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101203; + end else if ((7'd107 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101123; + end else if ((7'd105 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101043; + end else if ((7'd103 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100963; + end else if ((7'd101 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100883; + end else if ((7'd99 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100803; + end else if ((7'd97 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100723; + end else if ((7'd95 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100643; + end else if ((7'd93 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101643; + end else if ((7'd91 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101323; + end else if ((7'd89 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101003; + end else if ((7'd87 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100683; + end else if ((7'd85 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100843; + end else if ((7'd83 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101483; + end else if ((7'd81 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101163; + end else if ((7'd79 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101803; + end else if ((7'd77 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100763; + end else if ((7'd75 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100923; + end else if ((7'd73 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101083; + end else if ((7'd71 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101243; + end else if ((7'd69 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101403; + end else if ((7'd67 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101563; + end else if ((7'd65 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101723; + end else if ((7'd63 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101883; + end else if ((7'd61 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100663; + end else if ((7'd59 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100703; + end else if ((7'd57 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100743; + end else if ((7'd55 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100783; + end else if ((7'd53 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100823; + end else if ((7'd51 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100863; + end else if ((7'd49 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100903; + end else if ((7'd47 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100943; + end else if ((7'd45 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_100983; + end else if ((7'd43 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101023; + end else if ((7'd41 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101063; + end else if ((7'd39 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101103; + end else if ((7'd37 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101143; + end else if ((7'd35 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101183; + end else if ((7'd33 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101223; + end else if ((7'd31 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101263; + end else if ((7'd29 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101303; + end else if ((7'd27 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101343; + end else if ((7'd25 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101383; + end else if ((7'd23 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101423; + end else if ((7'd21 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101463; + end else if ((7'd19 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101503; + end else if ((7'd17 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101543; + end else if ((7'd15 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101583; + end else if ((7'd13 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101623; + end else if ((7'd11 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101663; + end else if ((7'd9 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101703; + end else if ((7'd7 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101743; + end else if ((7'd5 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101783; + end else if ((7'd3 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101823; + end else if ((7'd1 == add_ln1116_8_reg_133570)) begin + phi_ln1116_8_reg_91811 <= reg_101863; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1900 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_14082)) begin + phi_ln1116_9_reg_94937 <= reg_100598; + end else if ((7'd126 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100558; + end else if ((7'd124 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100478; + end else if ((7'd122 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100398; + end else if ((7'd120 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100318; + end else if ((7'd118 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100238; + end else if ((7'd116 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100158; + end else if ((7'd114 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100078; + end else if ((7'd112 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99998; + end else if ((7'd110 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99918; + end else if ((7'd108 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99838; + end else if ((7'd106 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99758; + end else if ((7'd104 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99678; + end else if ((7'd102 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99598; + end else if ((7'd100 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99518; + end else if ((7'd98 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99438; + end else if ((7'd96 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99358; + end else if ((7'd94 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100438; + end else if ((7'd92 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100118; + end else if ((7'd90 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99798; + end else if ((7'd88 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99478; + end else if ((7'd86 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99958; + end else if ((7'd84 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99318; + end else if ((7'd82 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99638; + end else if ((7'd80 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100278; + end else if ((7'd78 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99398; + end else if ((7'd76 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99558; + end else if ((7'd74 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99718; + end else if ((7'd72 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99878; + end else if ((7'd70 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100038; + end else if ((7'd68 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100198; + end else if ((7'd66 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100358; + end else if ((7'd64 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100518; + end else if ((7'd62 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99338; + end else if ((7'd60 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99378; + end else if ((7'd58 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99418; + end else if ((7'd56 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99458; + end else if ((7'd54 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99498; + end else if ((7'd52 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99538; + end else if ((7'd50 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99578; + end else if ((7'd48 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99618; + end else if ((7'd46 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99658; + end else if ((7'd44 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99698; + end else if ((7'd42 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99738; + end else if ((7'd40 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99778; + end else if ((7'd38 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99818; + end else if ((7'd36 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99858; + end else if ((7'd34 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99898; + end else if ((7'd32 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99938; + end else if ((7'd30 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_99978; + end else if ((7'd28 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100018; + end else if ((7'd26 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100058; + end else if ((7'd24 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100098; + end else if ((7'd22 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100138; + end else if ((7'd20 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100178; + end else if ((7'd18 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100218; + end else if ((7'd16 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100258; + end else if ((7'd14 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100298; + end else if ((7'd12 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100338; + end else if ((7'd10 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100378; + end else if ((7'd8 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100418; + end else if ((7'd6 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100458; + end else if ((7'd4 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100498; + end else if ((7'd2 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100538; + end else if ((7'd0 == add_ln1116_9_reg_142942)) begin + phi_ln1116_9_reg_94937 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_10039)) begin + phi_ln1116_reg_91231 <= reg_100598; + end else if ((7'd126 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100558; + end else if ((7'd124 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100478; + end else if ((7'd122 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100398; + end else if ((7'd120 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100318; + end else if ((7'd118 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100238; + end else if ((7'd116 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100158; + end else if ((7'd114 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100078; + end else if ((7'd112 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99998; + end else if ((7'd110 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99918; + end else if ((7'd108 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99838; + end else if ((7'd106 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99758; + end else if ((7'd104 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99678; + end else if ((7'd102 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99598; + end else if ((7'd100 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99518; + end else if ((7'd98 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99438; + end else if ((7'd96 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99358; + end else if ((7'd94 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100438; + end else if ((7'd92 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100118; + end else if ((7'd90 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99798; + end else if ((7'd88 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99478; + end else if ((7'd86 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99958; + end else if ((7'd84 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99318; + end else if ((7'd82 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99638; + end else if ((7'd80 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100278; + end else if ((7'd78 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99398; + end else if ((7'd76 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99558; + end else if ((7'd74 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99718; + end else if ((7'd72 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99878; + end else if ((7'd70 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100038; + end else if ((7'd68 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100198; + end else if ((7'd66 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100358; + end else if ((7'd64 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100518; + end else if ((7'd62 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99338; + end else if ((7'd60 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99378; + end else if ((7'd58 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99418; + end else if ((7'd56 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99458; + end else if ((7'd54 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99498; + end else if ((7'd52 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99538; + end else if ((7'd50 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99578; + end else if ((7'd48 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99618; + end else if ((7'd46 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99658; + end else if ((7'd44 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99698; + end else if ((7'd42 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99738; + end else if ((7'd40 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99778; + end else if ((7'd38 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99818; + end else if ((7'd36 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99858; + end else if ((7'd34 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99898; + end else if ((7'd32 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99938; + end else if ((7'd30 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_99978; + end else if ((7'd28 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100018; + end else if ((7'd26 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100058; + end else if ((7'd24 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100098; + end else if ((7'd22 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100138; + end else if ((7'd20 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100178; + end else if ((7'd18 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100218; + end else if ((7'd16 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100258; + end else if ((7'd14 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100298; + end else if ((7'd12 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100338; + end else if ((7'd10 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100378; + end else if ((7'd8 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100418; + end else if ((7'd6 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100458; + end else if ((7'd4 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100498; + end else if ((7'd2 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100538; + end else if ((7'd0 == add_ln1116_reg_131809)) begin + phi_ln1116_reg_91231 <= reg_100578; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3882 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_28817)) begin + phi_ln1265_10_reg_97677 <= acc_63_V_q1; + end else if ((6'd62 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_62_V_q1; + end else if ((6'd60 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_60_V_q1; + end else if ((6'd58 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_58_V_q1; + end else if ((6'd56 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_56_V_q1; + end else if ((6'd54 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_54_V_q1; + end else if ((6'd52 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_52_V_q1; + end else if ((6'd50 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_50_V_q1; + end else if ((6'd48 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_48_V_q1; + end else if ((6'd46 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_46_V_q1; + end else if ((6'd44 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_44_V_q1; + end else if ((6'd42 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_42_V_q1; + end else if ((6'd40 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_40_V_q1; + end else if ((6'd38 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_38_V_q1; + end else if ((6'd36 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_36_V_q1; + end else if ((6'd34 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_34_V_q1; + end else if ((6'd32 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_32_V_q1; + end else if ((6'd30 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_30_V_q1; + end else if ((6'd28 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_28_V_q1; + end else if ((6'd26 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_26_V_q1; + end else if ((6'd24 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_24_V_q1; + end else if ((6'd22 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_22_V_q1; + end else if ((6'd20 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_20_V_q1; + end else if ((6'd18 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_18_V_q1; + end else if ((6'd16 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_16_V_q1; + end else if ((6'd14 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_14_V_q1; + end else if ((6'd12 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_12_V_q1; + end else if ((6'd10 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_10_V_q1; + end else if ((6'd8 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_8_V_q1; + end else if ((6'd6 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_6_V_q1; + end else if ((6'd4 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_4_V_q1; + end else if ((6'd2 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_2_V_q1; + end else if ((6'd0 == add_ln1265_1_reg_157439)) begin + phi_ln1265_10_reg_97677 <= acc_0_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3267 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_26549)) begin + phi_ln1265_11_reg_96917 <= acc_63_V_q1; + end else if ((6'd62 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_62_V_q1; + end else if ((6'd60 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_60_V_q1; + end else if ((6'd58 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_58_V_q1; + end else if ((6'd56 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_56_V_q1; + end else if ((6'd54 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_54_V_q1; + end else if ((6'd52 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_52_V_q1; + end else if ((6'd50 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_50_V_q1; + end else if ((6'd48 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_48_V_q1; + end else if ((6'd46 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_46_V_q1; + end else if ((6'd44 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_44_V_q1; + end else if ((6'd42 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_42_V_q1; + end else if ((6'd40 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_40_V_q1; + end else if ((6'd38 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_38_V_q1; + end else if ((6'd36 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_36_V_q1; + end else if ((6'd34 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_34_V_q1; + end else if ((6'd32 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_32_V_q1; + end else if ((6'd30 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_30_V_q1; + end else if ((6'd28 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_28_V_q1; + end else if ((6'd26 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_26_V_q1; + end else if ((6'd24 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_24_V_q1; + end else if ((6'd22 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_22_V_q1; + end else if ((6'd20 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_20_V_q1; + end else if ((6'd18 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_18_V_q1; + end else if ((6'd16 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_16_V_q1; + end else if ((6'd14 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_14_V_q1; + end else if ((6'd12 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_12_V_q1; + end else if ((6'd10 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_10_V_q1; + end else if ((6'd8 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_8_V_q1; + end else if ((6'd6 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_6_V_q1; + end else if ((6'd4 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_4_V_q1; + end else if ((6'd2 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_2_V_q1; + end else if ((6'd0 == add_ln1265_2_reg_152512)) begin + phi_ln1265_11_reg_96917 <= acc_0_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2959 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_25226)) begin + phi_ln1265_12_reg_96539 <= acc_63_V_q1; + end else if ((6'd61 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_61_V_q1; + end else if ((6'd59 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_59_V_q1; + end else if ((6'd57 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_57_V_q1; + end else if ((6'd55 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_55_V_q1; + end else if ((6'd53 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_53_V_q1; + end else if ((6'd51 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_51_V_q1; + end else if ((6'd49 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_49_V_q1; + end else if ((6'd47 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_47_V_q1; + end else if ((6'd45 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_45_V_q1; + end else if ((6'd43 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_43_V_q1; + end else if ((6'd41 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_41_V_q1; + end else if ((6'd39 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_39_V_q1; + end else if ((6'd37 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_37_V_q1; + end else if ((6'd35 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_35_V_q1; + end else if ((6'd33 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_33_V_q1; + end else if ((6'd31 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_31_V_q1; + end else if ((6'd29 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_29_V_q1; + end else if ((6'd27 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_27_V_q1; + end else if ((6'd25 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_25_V_q1; + end else if ((6'd23 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_23_V_q1; + end else if ((6'd21 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_21_V_q1; + end else if ((6'd19 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_19_V_q1; + end else if ((6'd17 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_17_V_q1; + end else if ((6'd15 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_15_V_q1; + end else if ((6'd13 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_13_V_q1; + end else if ((6'd11 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_11_V_q1; + end else if ((6'd9 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_9_V_q1; + end else if ((6'd7 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_7_V_q1; + end else if ((6'd5 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_5_V_q1; + end else if ((6'd3 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_3_V_q1; + end else if ((6'd1 == add_ln1265_3_reg_148019)) begin + phi_ln1265_12_reg_96539 <= acc_1_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3960 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_28817)) begin + phi_ln1265_13_reg_97773 <= acc_63_V_q0; + end else if ((6'd62 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_62_V_q0; + end else if ((6'd60 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_60_V_q0; + end else if ((6'd58 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_58_V_q0; + end else if ((6'd56 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_56_V_q0; + end else if ((6'd54 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_54_V_q0; + end else if ((6'd52 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_52_V_q0; + end else if ((6'd50 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_50_V_q0; + end else if ((6'd48 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_48_V_q0; + end else if ((6'd46 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_46_V_q0; + end else if ((6'd44 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_44_V_q0; + end else if ((6'd42 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_42_V_q0; + end else if ((6'd40 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_40_V_q0; + end else if ((6'd38 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_38_V_q0; + end else if ((6'd36 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_36_V_q0; + end else if ((6'd34 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_34_V_q0; + end else if ((6'd32 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_32_V_q0; + end else if ((6'd30 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_30_V_q0; + end else if ((6'd28 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_28_V_q0; + end else if ((6'd26 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_26_V_q0; + end else if ((6'd24 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_24_V_q0; + end else if ((6'd22 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_22_V_q0; + end else if ((6'd20 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_20_V_q0; + end else if ((6'd18 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_18_V_q0; + end else if ((6'd16 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_16_V_q0; + end else if ((6'd14 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_14_V_q0; + end else if ((6'd12 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_12_V_q0; + end else if ((6'd10 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_10_V_q0; + end else if ((6'd8 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_8_V_q0; + end else if ((6'd6 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_6_V_q0; + end else if ((6'd4 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_4_V_q0; + end else if ((6'd2 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_2_V_q0; + end else if ((6'd0 == add_ln1265_1_reg_157439)) begin + phi_ln1265_13_reg_97773 <= acc_0_V_q0; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3345 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_26549)) begin + phi_ln1265_14_reg_97013 <= acc_63_V_q0; + end else if ((6'd62 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_62_V_q0; + end else if ((6'd60 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_60_V_q0; + end else if ((6'd58 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_58_V_q0; + end else if ((6'd56 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_56_V_q0; + end else if ((6'd54 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_54_V_q0; + end else if ((6'd52 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_52_V_q0; + end else if ((6'd50 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_50_V_q0; + end else if ((6'd48 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_48_V_q0; + end else if ((6'd46 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_46_V_q0; + end else if ((6'd44 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_44_V_q0; + end else if ((6'd42 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_42_V_q0; + end else if ((6'd40 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_40_V_q0; + end else if ((6'd38 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_38_V_q0; + end else if ((6'd36 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_36_V_q0; + end else if ((6'd34 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_34_V_q0; + end else if ((6'd32 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_32_V_q0; + end else if ((6'd30 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_30_V_q0; + end else if ((6'd28 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_28_V_q0; + end else if ((6'd26 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_26_V_q0; + end else if ((6'd24 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_24_V_q0; + end else if ((6'd22 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_22_V_q0; + end else if ((6'd20 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_20_V_q0; + end else if ((6'd18 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_18_V_q0; + end else if ((6'd16 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_16_V_q0; + end else if ((6'd14 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_14_V_q0; + end else if ((6'd12 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_12_V_q0; + end else if ((6'd10 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_10_V_q0; + end else if ((6'd8 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_8_V_q0; + end else if ((6'd6 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_6_V_q0; + end else if ((6'd4 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_4_V_q0; + end else if ((6'd2 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_2_V_q0; + end else if ((6'd0 == add_ln1265_2_reg_152512)) begin + phi_ln1265_14_reg_97013 <= acc_0_V_q0; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3037 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_25226)) begin + phi_ln1265_15_reg_96633 <= acc_63_V_q0; + end else if ((6'd61 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_61_V_q0; + end else if ((6'd59 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_59_V_q0; + end else if ((6'd57 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_57_V_q0; + end else if ((6'd55 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_55_V_q0; + end else if ((6'd53 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_53_V_q0; + end else if ((6'd51 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_51_V_q0; + end else if ((6'd49 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_49_V_q0; + end else if ((6'd47 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_47_V_q0; + end else if ((6'd45 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_45_V_q0; + end else if ((6'd43 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_43_V_q0; + end else if ((6'd41 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_41_V_q0; + end else if ((6'd39 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_39_V_q0; + end else if ((6'd37 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_37_V_q0; + end else if ((6'd35 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_35_V_q0; + end else if ((6'd33 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_33_V_q0; + end else if ((6'd31 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_31_V_q0; + end else if ((6'd29 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_29_V_q0; + end else if ((6'd27 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_27_V_q0; + end else if ((6'd25 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_25_V_q0; + end else if ((6'd23 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_23_V_q0; + end else if ((6'd21 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_21_V_q0; + end else if ((6'd19 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_19_V_q0; + end else if ((6'd17 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_17_V_q0; + end else if ((6'd15 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_15_V_q0; + end else if ((6'd13 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_13_V_q0; + end else if ((6'd11 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_11_V_q0; + end else if ((6'd9 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_9_V_q0; + end else if ((6'd7 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_7_V_q0; + end else if ((6'd5 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_5_V_q0; + end else if ((6'd3 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_3_V_q0; + end else if ((6'd1 == add_ln1265_3_reg_148019)) begin + phi_ln1265_15_reg_96633 <= acc_1_V_q0; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4496 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_31067)) begin + phi_ln1265_16_reg_98425 <= acc_63_V_q1; + end else if ((6'd62 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_62_V_q1; + end else if ((6'd60 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_60_V_q1; + end else if ((6'd58 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_58_V_q1; + end else if ((6'd56 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_56_V_q1; + end else if ((6'd54 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_54_V_q1; + end else if ((6'd52 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_52_V_q1; + end else if ((6'd50 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_50_V_q1; + end else if ((6'd48 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_48_V_q1; + end else if ((6'd46 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_46_V_q1; + end else if ((6'd44 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_44_V_q1; + end else if ((6'd42 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_42_V_q1; + end else if ((6'd40 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_40_V_q1; + end else if ((6'd38 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_38_V_q1; + end else if ((6'd36 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_36_V_q1; + end else if ((6'd34 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_34_V_q1; + end else if ((6'd32 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_32_V_q1; + end else if ((6'd30 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_30_V_q1; + end else if ((6'd28 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_28_V_q1; + end else if ((6'd26 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_26_V_q1; + end else if ((6'd24 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_24_V_q1; + end else if ((6'd22 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_22_V_q1; + end else if ((6'd20 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_20_V_q1; + end else if ((6'd18 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_18_V_q1; + end else if ((6'd16 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_16_V_q1; + end else if ((6'd14 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_14_V_q1; + end else if ((6'd12 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_12_V_q1; + end else if ((6'd10 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_10_V_q1; + end else if ((6'd8 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_8_V_q1; + end else if ((6'd6 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_6_V_q1; + end else if ((6'd4 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_4_V_q1; + end else if ((6'd2 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_2_V_q1; + end else if ((6'd0 == add_ln1265_4_reg_162353)) begin + phi_ln1265_16_reg_98425 <= acc_0_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4189 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_29808)) begin + phi_ln1265_17_reg_98047 <= acc_63_V_q1; + end else if ((6'd61 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_61_V_q1; + end else if ((6'd59 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_59_V_q1; + end else if ((6'd57 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_57_V_q1; + end else if ((6'd55 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_55_V_q1; + end else if ((6'd53 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_53_V_q1; + end else if ((6'd51 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_51_V_q1; + end else if ((6'd49 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_49_V_q1; + end else if ((6'd47 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_47_V_q1; + end else if ((6'd45 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_45_V_q1; + end else if ((6'd43 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_43_V_q1; + end else if ((6'd41 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_41_V_q1; + end else if ((6'd39 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_39_V_q1; + end else if ((6'd37 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_37_V_q1; + end else if ((6'd35 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_35_V_q1; + end else if ((6'd33 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_33_V_q1; + end else if ((6'd31 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_31_V_q1; + end else if ((6'd29 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_29_V_q1; + end else if ((6'd27 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_27_V_q1; + end else if ((6'd25 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_25_V_q1; + end else if ((6'd23 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_23_V_q1; + end else if ((6'd21 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_21_V_q1; + end else if ((6'd19 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_19_V_q1; + end else if ((6'd17 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_17_V_q1; + end else if ((6'd15 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_15_V_q1; + end else if ((6'd13 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_13_V_q1; + end else if ((6'd11 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_11_V_q1; + end else if ((6'd9 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_9_V_q1; + end else if ((6'd7 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_7_V_q1; + end else if ((6'd5 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_5_V_q1; + end else if ((6'd3 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_3_V_q1; + end else if ((6'd1 == add_ln1265_5_reg_157860)) begin + phi_ln1265_17_reg_98047 <= acc_1_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3574 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_27540)) begin + phi_ln1265_18_reg_97287 <= acc_63_V_q1; + end else if ((6'd61 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_61_V_q1; + end else if ((6'd59 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_59_V_q1; + end else if ((6'd57 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_57_V_q1; + end else if ((6'd55 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_55_V_q1; + end else if ((6'd53 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_53_V_q1; + end else if ((6'd51 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_51_V_q1; + end else if ((6'd49 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_49_V_q1; + end else if ((6'd47 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_47_V_q1; + end else if ((6'd45 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_45_V_q1; + end else if ((6'd43 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_43_V_q1; + end else if ((6'd41 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_41_V_q1; + end else if ((6'd39 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_39_V_q1; + end else if ((6'd37 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_37_V_q1; + end else if ((6'd35 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_35_V_q1; + end else if ((6'd33 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_33_V_q1; + end else if ((6'd31 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_31_V_q1; + end else if ((6'd29 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_29_V_q1; + end else if ((6'd27 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_27_V_q1; + end else if ((6'd25 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_25_V_q1; + end else if ((6'd23 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_23_V_q1; + end else if ((6'd21 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_21_V_q1; + end else if ((6'd19 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_19_V_q1; + end else if ((6'd17 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_17_V_q1; + end else if ((6'd15 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_15_V_q1; + end else if ((6'd13 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_13_V_q1; + end else if ((6'd11 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_11_V_q1; + end else if ((6'd9 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_9_V_q1; + end else if ((6'd7 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_7_V_q1; + end else if ((6'd5 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_5_V_q1; + end else if ((6'd3 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_3_V_q1; + end else if ((6'd1 == add_ln1265_6_reg_152920)) begin + phi_ln1265_18_reg_97287 <= acc_1_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4574 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_31067)) begin + phi_ln1265_19_reg_98521 <= acc_63_V_q0; + end else if ((6'd62 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_62_V_q0; + end else if ((6'd60 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_60_V_q0; + end else if ((6'd58 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_58_V_q0; + end else if ((6'd56 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_56_V_q0; + end else if ((6'd54 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_54_V_q0; + end else if ((6'd52 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_52_V_q0; + end else if ((6'd50 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_50_V_q0; + end else if ((6'd48 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_48_V_q0; + end else if ((6'd46 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_46_V_q0; + end else if ((6'd44 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_44_V_q0; + end else if ((6'd42 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_42_V_q0; + end else if ((6'd40 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_40_V_q0; + end else if ((6'd38 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_38_V_q0; + end else if ((6'd36 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_36_V_q0; + end else if ((6'd34 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_34_V_q0; + end else if ((6'd32 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_32_V_q0; + end else if ((6'd30 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_30_V_q0; + end else if ((6'd28 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_28_V_q0; + end else if ((6'd26 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_26_V_q0; + end else if ((6'd24 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_24_V_q0; + end else if ((6'd22 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_22_V_q0; + end else if ((6'd20 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_20_V_q0; + end else if ((6'd18 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_18_V_q0; + end else if ((6'd16 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_16_V_q0; + end else if ((6'd14 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_14_V_q0; + end else if ((6'd12 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_12_V_q0; + end else if ((6'd10 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_10_V_q0; + end else if ((6'd8 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_8_V_q0; + end else if ((6'd6 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_6_V_q0; + end else if ((6'd4 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_4_V_q0; + end else if ((6'd2 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_2_V_q0; + end else if ((6'd0 == add_ln1265_4_reg_162353)) begin + phi_ln1265_19_reg_98521 <= acc_0_V_q0; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3805 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_28817)) begin + phi_ln1265_1_reg_97593 <= acc_63_V_q0; + end else if ((6'd62 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_62_V_q0; + end else if ((6'd60 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_60_V_q0; + end else if ((6'd58 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_58_V_q0; + end else if ((6'd56 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_56_V_q0; + end else if ((6'd54 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_54_V_q0; + end else if ((6'd52 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_52_V_q0; + end else if ((6'd50 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_50_V_q0; + end else if ((6'd48 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_48_V_q0; + end else if ((6'd46 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_46_V_q0; + end else if ((6'd44 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_44_V_q0; + end else if ((6'd42 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_42_V_q0; + end else if ((6'd40 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_40_V_q0; + end else if ((6'd38 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_38_V_q0; + end else if ((6'd36 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_36_V_q0; + end else if ((6'd34 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_34_V_q0; + end else if ((6'd32 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_32_V_q0; + end else if ((6'd30 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_30_V_q0; + end else if ((6'd28 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_28_V_q0; + end else if ((6'd26 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_26_V_q0; + end else if ((6'd24 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_24_V_q0; + end else if ((6'd22 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_22_V_q0; + end else if ((6'd20 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_20_V_q0; + end else if ((6'd18 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_18_V_q0; + end else if ((6'd16 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_16_V_q0; + end else if ((6'd14 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_14_V_q0; + end else if ((6'd12 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_12_V_q0; + end else if ((6'd10 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_10_V_q0; + end else if ((6'd8 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_8_V_q0; + end else if ((6'd6 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_6_V_q0; + end else if ((6'd4 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_4_V_q0; + end else if ((6'd2 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_2_V_q0; + end else if ((6'd0 == add_ln1265_1_reg_157439)) begin + phi_ln1265_1_reg_97593 <= acc_0_V_q0; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4267 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_29808)) begin + phi_ln1265_20_reg_98141 <= acc_63_V_q0; + end else if ((6'd61 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_61_V_q0; + end else if ((6'd59 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_59_V_q0; + end else if ((6'd57 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_57_V_q0; + end else if ((6'd55 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_55_V_q0; + end else if ((6'd53 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_53_V_q0; + end else if ((6'd51 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_51_V_q0; + end else if ((6'd49 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_49_V_q0; + end else if ((6'd47 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_47_V_q0; + end else if ((6'd45 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_45_V_q0; + end else if ((6'd43 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_43_V_q0; + end else if ((6'd41 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_41_V_q0; + end else if ((6'd39 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_39_V_q0; + end else if ((6'd37 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_37_V_q0; + end else if ((6'd35 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_35_V_q0; + end else if ((6'd33 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_33_V_q0; + end else if ((6'd31 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_31_V_q0; + end else if ((6'd29 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_29_V_q0; + end else if ((6'd27 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_27_V_q0; + end else if ((6'd25 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_25_V_q0; + end else if ((6'd23 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_23_V_q0; + end else if ((6'd21 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_21_V_q0; + end else if ((6'd19 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_19_V_q0; + end else if ((6'd17 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_17_V_q0; + end else if ((6'd15 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_15_V_q0; + end else if ((6'd13 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_13_V_q0; + end else if ((6'd11 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_11_V_q0; + end else if ((6'd9 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_9_V_q0; + end else if ((6'd7 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_7_V_q0; + end else if ((6'd5 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_5_V_q0; + end else if ((6'd3 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_3_V_q0; + end else if ((6'd1 == add_ln1265_5_reg_157860)) begin + phi_ln1265_20_reg_98141 <= acc_1_V_q0; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3652 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_27540)) begin + phi_ln1265_21_reg_97381 <= acc_63_V_q0; + end else if ((6'd61 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_61_V_q0; + end else if ((6'd59 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_59_V_q0; + end else if ((6'd57 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_57_V_q0; + end else if ((6'd55 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_55_V_q0; + end else if ((6'd53 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_53_V_q0; + end else if ((6'd51 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_51_V_q0; + end else if ((6'd49 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_49_V_q0; + end else if ((6'd47 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_47_V_q0; + end else if ((6'd45 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_45_V_q0; + end else if ((6'd43 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_43_V_q0; + end else if ((6'd41 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_41_V_q0; + end else if ((6'd39 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_39_V_q0; + end else if ((6'd37 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_37_V_q0; + end else if ((6'd35 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_35_V_q0; + end else if ((6'd33 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_33_V_q0; + end else if ((6'd31 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_31_V_q0; + end else if ((6'd29 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_29_V_q0; + end else if ((6'd27 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_27_V_q0; + end else if ((6'd25 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_25_V_q0; + end else if ((6'd23 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_23_V_q0; + end else if ((6'd21 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_21_V_q0; + end else if ((6'd19 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_19_V_q0; + end else if ((6'd17 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_17_V_q0; + end else if ((6'd15 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_15_V_q0; + end else if ((6'd13 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_13_V_q0; + end else if ((6'd11 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_11_V_q0; + end else if ((6'd9 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_9_V_q0; + end else if ((6'd7 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_7_V_q0; + end else if ((6'd5 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_5_V_q0; + end else if ((6'd3 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_3_V_q0; + end else if ((6'd1 == add_ln1265_6_reg_152920)) begin + phi_ln1265_21_reg_97381 <= acc_1_V_q0; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4801 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_32057)) begin + phi_ln1265_22_reg_98795 <= acc_63_V_q1; + end else if ((6'd61 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_61_V_q1; + end else if ((6'd59 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_59_V_q1; + end else if ((6'd57 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_57_V_q1; + end else if ((6'd55 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_55_V_q1; + end else if ((6'd53 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_53_V_q1; + end else if ((6'd51 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_51_V_q1; + end else if ((6'd49 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_49_V_q1; + end else if ((6'd47 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_47_V_q1; + end else if ((6'd45 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_45_V_q1; + end else if ((6'd43 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_43_V_q1; + end else if ((6'd41 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_41_V_q1; + end else if ((6'd39 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_39_V_q1; + end else if ((6'd37 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_37_V_q1; + end else if ((6'd35 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_35_V_q1; + end else if ((6'd33 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_33_V_q1; + end else if ((6'd31 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_31_V_q1; + end else if ((6'd29 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_29_V_q1; + end else if ((6'd27 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_27_V_q1; + end else if ((6'd25 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_25_V_q1; + end else if ((6'd23 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_23_V_q1; + end else if ((6'd21 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_21_V_q1; + end else if ((6'd19 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_19_V_q1; + end else if ((6'd17 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_17_V_q1; + end else if ((6'd15 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_15_V_q1; + end else if ((6'd13 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_13_V_q1; + end else if ((6'd11 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_11_V_q1; + end else if ((6'd9 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_9_V_q1; + end else if ((6'd7 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_7_V_q1; + end else if ((6'd5 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_5_V_q1; + end else if ((6'd3 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_3_V_q1; + end else if ((6'd1 == add_ln1265_7_reg_162761)) begin + phi_ln1265_22_reg_98795 <= acc_1_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4879 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_32057)) begin + phi_ln1265_23_reg_98889 <= acc_63_V_q0; + end else if ((6'd61 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_61_V_q0; + end else if ((6'd59 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_59_V_q0; + end else if ((6'd57 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_57_V_q0; + end else if ((6'd55 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_55_V_q0; + end else if ((6'd53 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_53_V_q0; + end else if ((6'd51 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_51_V_q0; + end else if ((6'd49 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_49_V_q0; + end else if ((6'd47 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_47_V_q0; + end else if ((6'd45 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_45_V_q0; + end else if ((6'd43 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_43_V_q0; + end else if ((6'd41 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_41_V_q0; + end else if ((6'd39 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_39_V_q0; + end else if ((6'd37 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_37_V_q0; + end else if ((6'd35 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_35_V_q0; + end else if ((6'd33 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_33_V_q0; + end else if ((6'd31 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_31_V_q0; + end else if ((6'd29 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_29_V_q0; + end else if ((6'd27 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_27_V_q0; + end else if ((6'd25 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_25_V_q0; + end else if ((6'd23 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_23_V_q0; + end else if ((6'd21 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_21_V_q0; + end else if ((6'd19 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_19_V_q0; + end else if ((6'd17 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_17_V_q0; + end else if ((6'd15 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_15_V_q0; + end else if ((6'd13 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_13_V_q0; + end else if ((6'd11 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_11_V_q0; + end else if ((6'd9 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_9_V_q0; + end else if ((6'd7 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_7_V_q0; + end else if ((6'd5 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_5_V_q0; + end else if ((6'd3 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_3_V_q0; + end else if ((6'd1 == add_ln1265_7_reg_162761)) begin + phi_ln1265_23_reg_98889 <= acc_1_V_q0; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2806 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_24171)) begin + phi_ln1265_24_reg_96349 <= acc_63_V_q1; + end else if ((6'd62 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_62_V_q1; + end else if ((6'd60 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_60_V_q1; + end else if ((6'd58 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_58_V_q1; + end else if ((6'd56 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_56_V_q1; + end else if ((6'd54 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_54_V_q1; + end else if ((6'd52 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_52_V_q1; + end else if ((6'd50 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_50_V_q1; + end else if ((6'd48 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_48_V_q1; + end else if ((6'd46 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_46_V_q1; + end else if ((6'd44 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_44_V_q1; + end else if ((6'd42 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_42_V_q1; + end else if ((6'd40 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_40_V_q1; + end else if ((6'd38 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_38_V_q1; + end else if ((6'd36 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_36_V_q1; + end else if ((6'd34 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_34_V_q1; + end else if ((6'd32 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_32_V_q1; + end else if ((6'd30 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_30_V_q1; + end else if ((6'd28 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_28_V_q1; + end else if ((6'd26 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_26_V_q1; + end else if ((6'd24 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_24_V_q1; + end else if ((6'd22 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_22_V_q1; + end else if ((6'd20 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_20_V_q1; + end else if ((6'd18 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_18_V_q1; + end else if ((6'd16 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_16_V_q1; + end else if ((6'd14 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_14_V_q1; + end else if ((6'd12 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_12_V_q1; + end else if ((6'd10 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_10_V_q1; + end else if ((6'd8 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_8_V_q1; + end else if ((6'd6 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_6_V_q1; + end else if ((6'd4 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_4_V_q1; + end else if ((6'd2 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_2_V_q1; + end else if ((6'd0 == add_ln1265_reg_147629)) begin + phi_ln1265_24_reg_96349 <= acc_0_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4036 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_28817)) begin + phi_ln1265_25_reg_97857 <= acc_63_V_q1; + end else if ((6'd62 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_62_V_q1; + end else if ((6'd60 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_60_V_q1; + end else if ((6'd58 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_58_V_q1; + end else if ((6'd56 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_56_V_q1; + end else if ((6'd54 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_54_V_q1; + end else if ((6'd52 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_52_V_q1; + end else if ((6'd50 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_50_V_q1; + end else if ((6'd48 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_48_V_q1; + end else if ((6'd46 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_46_V_q1; + end else if ((6'd44 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_44_V_q1; + end else if ((6'd42 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_42_V_q1; + end else if ((6'd40 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_40_V_q1; + end else if ((6'd38 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_38_V_q1; + end else if ((6'd36 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_36_V_q1; + end else if ((6'd34 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_34_V_q1; + end else if ((6'd32 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_32_V_q1; + end else if ((6'd30 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_30_V_q1; + end else if ((6'd28 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_28_V_q1; + end else if ((6'd26 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_26_V_q1; + end else if ((6'd24 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_24_V_q1; + end else if ((6'd22 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_22_V_q1; + end else if ((6'd20 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_20_V_q1; + end else if ((6'd18 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_18_V_q1; + end else if ((6'd16 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_16_V_q1; + end else if ((6'd14 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_14_V_q1; + end else if ((6'd12 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_12_V_q1; + end else if ((6'd10 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_10_V_q1; + end else if ((6'd8 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_8_V_q1; + end else if ((6'd6 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_6_V_q1; + end else if ((6'd4 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_4_V_q1; + end else if ((6'd2 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_2_V_q1; + end else if ((6'd0 == add_ln1265_1_reg_157439)) begin + phi_ln1265_25_reg_97857 <= acc_0_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3421 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_26549)) begin + phi_ln1265_26_reg_97097 <= acc_63_V_q1; + end else if ((6'd62 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_62_V_q1; + end else if ((6'd60 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_60_V_q1; + end else if ((6'd58 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_58_V_q1; + end else if ((6'd56 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_56_V_q1; + end else if ((6'd54 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_54_V_q1; + end else if ((6'd52 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_52_V_q1; + end else if ((6'd50 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_50_V_q1; + end else if ((6'd48 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_48_V_q1; + end else if ((6'd46 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_46_V_q1; + end else if ((6'd44 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_44_V_q1; + end else if ((6'd42 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_42_V_q1; + end else if ((6'd40 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_40_V_q1; + end else if ((6'd38 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_38_V_q1; + end else if ((6'd36 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_36_V_q1; + end else if ((6'd34 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_34_V_q1; + end else if ((6'd32 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_32_V_q1; + end else if ((6'd30 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_30_V_q1; + end else if ((6'd28 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_28_V_q1; + end else if ((6'd26 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_26_V_q1; + end else if ((6'd24 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_24_V_q1; + end else if ((6'd22 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_22_V_q1; + end else if ((6'd20 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_20_V_q1; + end else if ((6'd18 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_18_V_q1; + end else if ((6'd16 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_16_V_q1; + end else if ((6'd14 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_14_V_q1; + end else if ((6'd12 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_12_V_q1; + end else if ((6'd10 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_10_V_q1; + end else if ((6'd8 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_8_V_q1; + end else if ((6'd6 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_6_V_q1; + end else if ((6'd4 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_4_V_q1; + end else if ((6'd2 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_2_V_q1; + end else if ((6'd0 == add_ln1265_2_reg_152512)) begin + phi_ln1265_26_reg_97097 <= acc_0_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3113 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_25226)) begin + phi_ln1265_27_reg_96715 <= acc_63_V_q1; + end else if ((6'd61 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_61_V_q1; + end else if ((6'd59 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_59_V_q1; + end else if ((6'd57 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_57_V_q1; + end else if ((6'd55 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_55_V_q1; + end else if ((6'd53 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_53_V_q1; + end else if ((6'd51 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_51_V_q1; + end else if ((6'd49 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_49_V_q1; + end else if ((6'd47 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_47_V_q1; + end else if ((6'd45 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_45_V_q1; + end else if ((6'd43 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_43_V_q1; + end else if ((6'd41 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_41_V_q1; + end else if ((6'd39 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_39_V_q1; + end else if ((6'd37 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_37_V_q1; + end else if ((6'd35 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_35_V_q1; + end else if ((6'd33 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_33_V_q1; + end else if ((6'd31 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_31_V_q1; + end else if ((6'd29 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_29_V_q1; + end else if ((6'd27 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_27_V_q1; + end else if ((6'd25 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_25_V_q1; + end else if ((6'd23 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_23_V_q1; + end else if ((6'd21 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_21_V_q1; + end else if ((6'd19 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_19_V_q1; + end else if ((6'd17 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_17_V_q1; + end else if ((6'd15 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_15_V_q1; + end else if ((6'd13 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_13_V_q1; + end else if ((6'd11 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_11_V_q1; + end else if ((6'd9 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_9_V_q1; + end else if ((6'd7 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_7_V_q1; + end else if ((6'd5 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_5_V_q1; + end else if ((6'd3 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_3_V_q1; + end else if ((6'd1 == add_ln1265_3_reg_148019)) begin + phi_ln1265_27_reg_96715 <= acc_1_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4649 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_31067)) begin + phi_ln1265_28_reg_98605 <= acc_63_V_q1; + end else if ((6'd62 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_62_V_q1; + end else if ((6'd60 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_60_V_q1; + end else if ((6'd58 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_58_V_q1; + end else if ((6'd56 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_56_V_q1; + end else if ((6'd54 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_54_V_q1; + end else if ((6'd52 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_52_V_q1; + end else if ((6'd50 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_50_V_q1; + end else if ((6'd48 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_48_V_q1; + end else if ((6'd46 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_46_V_q1; + end else if ((6'd44 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_44_V_q1; + end else if ((6'd42 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_42_V_q1; + end else if ((6'd40 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_40_V_q1; + end else if ((6'd38 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_38_V_q1; + end else if ((6'd36 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_36_V_q1; + end else if ((6'd34 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_34_V_q1; + end else if ((6'd32 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_32_V_q1; + end else if ((6'd30 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_30_V_q1; + end else if ((6'd28 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_28_V_q1; + end else if ((6'd26 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_26_V_q1; + end else if ((6'd24 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_24_V_q1; + end else if ((6'd22 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_22_V_q1; + end else if ((6'd20 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_20_V_q1; + end else if ((6'd18 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_18_V_q1; + end else if ((6'd16 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_16_V_q1; + end else if ((6'd14 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_14_V_q1; + end else if ((6'd12 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_12_V_q1; + end else if ((6'd10 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_10_V_q1; + end else if ((6'd8 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_8_V_q1; + end else if ((6'd6 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_6_V_q1; + end else if ((6'd4 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_4_V_q1; + end else if ((6'd2 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_2_V_q1; + end else if ((6'd0 == add_ln1265_4_reg_162353)) begin + phi_ln1265_28_reg_98605 <= acc_0_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4342 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_29808)) begin + phi_ln1265_29_reg_98223 <= acc_63_V_q1; + end else if ((6'd61 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_61_V_q1; + end else if ((6'd59 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_59_V_q1; + end else if ((6'd57 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_57_V_q1; + end else if ((6'd55 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_55_V_q1; + end else if ((6'd53 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_53_V_q1; + end else if ((6'd51 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_51_V_q1; + end else if ((6'd49 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_49_V_q1; + end else if ((6'd47 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_47_V_q1; + end else if ((6'd45 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_45_V_q1; + end else if ((6'd43 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_43_V_q1; + end else if ((6'd41 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_41_V_q1; + end else if ((6'd39 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_39_V_q1; + end else if ((6'd37 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_37_V_q1; + end else if ((6'd35 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_35_V_q1; + end else if ((6'd33 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_33_V_q1; + end else if ((6'd31 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_31_V_q1; + end else if ((6'd29 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_29_V_q1; + end else if ((6'd27 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_27_V_q1; + end else if ((6'd25 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_25_V_q1; + end else if ((6'd23 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_23_V_q1; + end else if ((6'd21 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_21_V_q1; + end else if ((6'd19 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_19_V_q1; + end else if ((6'd17 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_17_V_q1; + end else if ((6'd15 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_15_V_q1; + end else if ((6'd13 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_13_V_q1; + end else if ((6'd11 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_11_V_q1; + end else if ((6'd9 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_9_V_q1; + end else if ((6'd7 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_7_V_q1; + end else if ((6'd5 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_5_V_q1; + end else if ((6'd3 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_3_V_q1; + end else if ((6'd1 == add_ln1265_5_reg_157860)) begin + phi_ln1265_29_reg_98223 <= acc_1_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3190 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_26549)) begin + phi_ln1265_2_reg_96833 <= acc_63_V_q0; + end else if ((6'd62 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_62_V_q0; + end else if ((6'd60 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_60_V_q0; + end else if ((6'd58 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_58_V_q0; + end else if ((6'd56 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_56_V_q0; + end else if ((6'd54 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_54_V_q0; + end else if ((6'd52 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_52_V_q0; + end else if ((6'd50 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_50_V_q0; + end else if ((6'd48 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_48_V_q0; + end else if ((6'd46 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_46_V_q0; + end else if ((6'd44 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_44_V_q0; + end else if ((6'd42 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_42_V_q0; + end else if ((6'd40 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_40_V_q0; + end else if ((6'd38 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_38_V_q0; + end else if ((6'd36 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_36_V_q0; + end else if ((6'd34 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_34_V_q0; + end else if ((6'd32 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_32_V_q0; + end else if ((6'd30 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_30_V_q0; + end else if ((6'd28 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_28_V_q0; + end else if ((6'd26 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_26_V_q0; + end else if ((6'd24 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_24_V_q0; + end else if ((6'd22 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_22_V_q0; + end else if ((6'd20 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_20_V_q0; + end else if ((6'd18 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_18_V_q0; + end else if ((6'd16 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_16_V_q0; + end else if ((6'd14 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_14_V_q0; + end else if ((6'd12 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_12_V_q0; + end else if ((6'd10 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_10_V_q0; + end else if ((6'd8 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_8_V_q0; + end else if ((6'd6 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_6_V_q0; + end else if ((6'd4 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_4_V_q0; + end else if ((6'd2 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_2_V_q0; + end else if ((6'd0 == add_ln1265_2_reg_152512)) begin + phi_ln1265_2_reg_96833 <= acc_0_V_q0; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3727 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_27540)) begin + phi_ln1265_30_reg_97463 <= acc_63_V_q1; + end else if ((6'd61 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_61_V_q1; + end else if ((6'd59 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_59_V_q1; + end else if ((6'd57 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_57_V_q1; + end else if ((6'd55 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_55_V_q1; + end else if ((6'd53 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_53_V_q1; + end else if ((6'd51 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_51_V_q1; + end else if ((6'd49 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_49_V_q1; + end else if ((6'd47 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_47_V_q1; + end else if ((6'd45 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_45_V_q1; + end else if ((6'd43 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_43_V_q1; + end else if ((6'd41 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_41_V_q1; + end else if ((6'd39 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_39_V_q1; + end else if ((6'd37 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_37_V_q1; + end else if ((6'd35 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_35_V_q1; + end else if ((6'd33 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_33_V_q1; + end else if ((6'd31 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_31_V_q1; + end else if ((6'd29 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_29_V_q1; + end else if ((6'd27 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_27_V_q1; + end else if ((6'd25 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_25_V_q1; + end else if ((6'd23 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_23_V_q1; + end else if ((6'd21 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_21_V_q1; + end else if ((6'd19 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_19_V_q1; + end else if ((6'd17 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_17_V_q1; + end else if ((6'd15 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_15_V_q1; + end else if ((6'd13 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_13_V_q1; + end else if ((6'd11 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_11_V_q1; + end else if ((6'd9 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_9_V_q1; + end else if ((6'd7 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_7_V_q1; + end else if ((6'd5 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_5_V_q1; + end else if ((6'd3 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_3_V_q1; + end else if ((6'd1 == add_ln1265_6_reg_152920)) begin + phi_ln1265_30_reg_97463 <= acc_1_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4954 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_32057)) begin + phi_ln1265_31_reg_98971 <= acc_63_V_q1; + end else if ((6'd61 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_61_V_q1; + end else if ((6'd59 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_59_V_q1; + end else if ((6'd57 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_57_V_q1; + end else if ((6'd55 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_55_V_q1; + end else if ((6'd53 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_53_V_q1; + end else if ((6'd51 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_51_V_q1; + end else if ((6'd49 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_49_V_q1; + end else if ((6'd47 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_47_V_q1; + end else if ((6'd45 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_45_V_q1; + end else if ((6'd43 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_43_V_q1; + end else if ((6'd41 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_41_V_q1; + end else if ((6'd39 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_39_V_q1; + end else if ((6'd37 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_37_V_q1; + end else if ((6'd35 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_35_V_q1; + end else if ((6'd33 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_33_V_q1; + end else if ((6'd31 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_31_V_q1; + end else if ((6'd29 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_29_V_q1; + end else if ((6'd27 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_27_V_q1; + end else if ((6'd25 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_25_V_q1; + end else if ((6'd23 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_23_V_q1; + end else if ((6'd21 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_21_V_q1; + end else if ((6'd19 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_19_V_q1; + end else if ((6'd17 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_17_V_q1; + end else if ((6'd15 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_15_V_q1; + end else if ((6'd13 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_13_V_q1; + end else if ((6'd11 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_11_V_q1; + end else if ((6'd9 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_9_V_q1; + end else if ((6'd7 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_7_V_q1; + end else if ((6'd5 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_5_V_q1; + end else if ((6'd3 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_3_V_q1; + end else if ((6'd1 == add_ln1265_7_reg_162761)) begin + phi_ln1265_31_reg_98971 <= acc_1_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2882 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_25226)) begin + phi_ln1265_3_reg_96457 <= acc_63_V_q0; + end else if ((6'd61 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_61_V_q0; + end else if ((6'd59 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_59_V_q0; + end else if ((6'd57 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_57_V_q0; + end else if ((6'd55 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_55_V_q0; + end else if ((6'd53 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_53_V_q0; + end else if ((6'd51 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_51_V_q0; + end else if ((6'd49 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_49_V_q0; + end else if ((6'd47 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_47_V_q0; + end else if ((6'd45 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_45_V_q0; + end else if ((6'd43 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_43_V_q0; + end else if ((6'd41 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_41_V_q0; + end else if ((6'd39 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_39_V_q0; + end else if ((6'd37 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_37_V_q0; + end else if ((6'd35 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_35_V_q0; + end else if ((6'd33 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_33_V_q0; + end else if ((6'd31 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_31_V_q0; + end else if ((6'd29 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_29_V_q0; + end else if ((6'd27 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_27_V_q0; + end else if ((6'd25 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_25_V_q0; + end else if ((6'd23 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_23_V_q0; + end else if ((6'd21 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_21_V_q0; + end else if ((6'd19 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_19_V_q0; + end else if ((6'd17 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_17_V_q0; + end else if ((6'd15 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_15_V_q0; + end else if ((6'd13 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_13_V_q0; + end else if ((6'd11 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_11_V_q0; + end else if ((6'd9 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_9_V_q0; + end else if ((6'd7 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_7_V_q0; + end else if ((6'd5 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_5_V_q0; + end else if ((6'd3 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_3_V_q0; + end else if ((6'd1 == add_ln1265_3_reg_148019)) begin + phi_ln1265_3_reg_96457 <= acc_1_V_q0; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4419 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_31067)) begin + phi_ln1265_4_reg_98341 <= acc_63_V_q0; + end else if ((6'd62 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_62_V_q0; + end else if ((6'd60 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_60_V_q0; + end else if ((6'd58 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_58_V_q0; + end else if ((6'd56 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_56_V_q0; + end else if ((6'd54 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_54_V_q0; + end else if ((6'd52 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_52_V_q0; + end else if ((6'd50 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_50_V_q0; + end else if ((6'd48 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_48_V_q0; + end else if ((6'd46 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_46_V_q0; + end else if ((6'd44 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_44_V_q0; + end else if ((6'd42 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_42_V_q0; + end else if ((6'd40 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_40_V_q0; + end else if ((6'd38 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_38_V_q0; + end else if ((6'd36 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_36_V_q0; + end else if ((6'd34 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_34_V_q0; + end else if ((6'd32 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_32_V_q0; + end else if ((6'd30 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_30_V_q0; + end else if ((6'd28 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_28_V_q0; + end else if ((6'd26 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_26_V_q0; + end else if ((6'd24 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_24_V_q0; + end else if ((6'd22 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_22_V_q0; + end else if ((6'd20 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_20_V_q0; + end else if ((6'd18 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_18_V_q0; + end else if ((6'd16 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_16_V_q0; + end else if ((6'd14 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_14_V_q0; + end else if ((6'd12 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_12_V_q0; + end else if ((6'd10 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_10_V_q0; + end else if ((6'd8 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_8_V_q0; + end else if ((6'd6 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_6_V_q0; + end else if ((6'd4 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_4_V_q0; + end else if ((6'd2 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_2_V_q0; + end else if ((6'd0 == add_ln1265_4_reg_162353)) begin + phi_ln1265_4_reg_98341 <= acc_0_V_q0; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4112 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_29808)) begin + phi_ln1265_5_reg_97965 <= acc_63_V_q0; + end else if ((6'd61 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_61_V_q0; + end else if ((6'd59 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_59_V_q0; + end else if ((6'd57 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_57_V_q0; + end else if ((6'd55 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_55_V_q0; + end else if ((6'd53 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_53_V_q0; + end else if ((6'd51 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_51_V_q0; + end else if ((6'd49 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_49_V_q0; + end else if ((6'd47 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_47_V_q0; + end else if ((6'd45 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_45_V_q0; + end else if ((6'd43 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_43_V_q0; + end else if ((6'd41 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_41_V_q0; + end else if ((6'd39 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_39_V_q0; + end else if ((6'd37 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_37_V_q0; + end else if ((6'd35 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_35_V_q0; + end else if ((6'd33 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_33_V_q0; + end else if ((6'd31 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_31_V_q0; + end else if ((6'd29 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_29_V_q0; + end else if ((6'd27 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_27_V_q0; + end else if ((6'd25 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_25_V_q0; + end else if ((6'd23 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_23_V_q0; + end else if ((6'd21 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_21_V_q0; + end else if ((6'd19 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_19_V_q0; + end else if ((6'd17 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_17_V_q0; + end else if ((6'd15 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_15_V_q0; + end else if ((6'd13 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_13_V_q0; + end else if ((6'd11 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_11_V_q0; + end else if ((6'd9 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_9_V_q0; + end else if ((6'd7 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_7_V_q0; + end else if ((6'd5 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_5_V_q0; + end else if ((6'd3 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_3_V_q0; + end else if ((6'd1 == add_ln1265_5_reg_157860)) begin + phi_ln1265_5_reg_97965 <= acc_1_V_q0; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3497 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_27540)) begin + phi_ln1265_6_reg_97205 <= acc_63_V_q0; + end else if ((6'd61 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_61_V_q0; + end else if ((6'd59 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_59_V_q0; + end else if ((6'd57 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_57_V_q0; + end else if ((6'd55 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_55_V_q0; + end else if ((6'd53 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_53_V_q0; + end else if ((6'd51 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_51_V_q0; + end else if ((6'd49 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_49_V_q0; + end else if ((6'd47 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_47_V_q0; + end else if ((6'd45 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_45_V_q0; + end else if ((6'd43 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_43_V_q0; + end else if ((6'd41 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_41_V_q0; + end else if ((6'd39 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_39_V_q0; + end else if ((6'd37 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_37_V_q0; + end else if ((6'd35 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_35_V_q0; + end else if ((6'd33 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_33_V_q0; + end else if ((6'd31 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_31_V_q0; + end else if ((6'd29 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_29_V_q0; + end else if ((6'd27 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_27_V_q0; + end else if ((6'd25 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_25_V_q0; + end else if ((6'd23 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_23_V_q0; + end else if ((6'd21 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_21_V_q0; + end else if ((6'd19 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_19_V_q0; + end else if ((6'd17 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_17_V_q0; + end else if ((6'd15 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_15_V_q0; + end else if ((6'd13 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_13_V_q0; + end else if ((6'd11 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_11_V_q0; + end else if ((6'd9 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_9_V_q0; + end else if ((6'd7 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_7_V_q0; + end else if ((6'd5 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_5_V_q0; + end else if ((6'd3 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_3_V_q0; + end else if ((6'd1 == add_ln1265_6_reg_152920)) begin + phi_ln1265_6_reg_97205 <= acc_1_V_q0; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4725 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_32057)) begin + phi_ln1265_7_reg_98713 <= acc_63_V_q0; + end else if ((6'd61 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_61_V_q0; + end else if ((6'd59 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_59_V_q0; + end else if ((6'd57 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_57_V_q0; + end else if ((6'd55 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_55_V_q0; + end else if ((6'd53 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_53_V_q0; + end else if ((6'd51 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_51_V_q0; + end else if ((6'd49 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_49_V_q0; + end else if ((6'd47 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_47_V_q0; + end else if ((6'd45 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_45_V_q0; + end else if ((6'd43 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_43_V_q0; + end else if ((6'd41 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_41_V_q0; + end else if ((6'd39 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_39_V_q0; + end else if ((6'd37 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_37_V_q0; + end else if ((6'd35 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_35_V_q0; + end else if ((6'd33 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_33_V_q0; + end else if ((6'd31 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_31_V_q0; + end else if ((6'd29 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_29_V_q0; + end else if ((6'd27 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_27_V_q0; + end else if ((6'd25 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_25_V_q0; + end else if ((6'd23 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_23_V_q0; + end else if ((6'd21 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_21_V_q0; + end else if ((6'd19 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_19_V_q0; + end else if ((6'd17 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_17_V_q0; + end else if ((6'd15 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_15_V_q0; + end else if ((6'd13 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_13_V_q0; + end else if ((6'd11 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_11_V_q0; + end else if ((6'd9 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_9_V_q0; + end else if ((6'd7 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_7_V_q0; + end else if ((6'd5 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_5_V_q0; + end else if ((6'd3 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_3_V_q0; + end else if ((6'd1 == add_ln1265_7_reg_162761)) begin + phi_ln1265_7_reg_98713 <= acc_1_V_q0; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2651 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_24171)) begin + phi_ln1265_8_reg_96169 <= acc_63_V_q1; + end else if ((6'd62 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_62_V_q1; + end else if ((6'd60 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_60_V_q1; + end else if ((6'd58 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_58_V_q1; + end else if ((6'd56 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_56_V_q1; + end else if ((6'd54 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_54_V_q1; + end else if ((6'd52 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_52_V_q1; + end else if ((6'd50 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_50_V_q1; + end else if ((6'd48 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_48_V_q1; + end else if ((6'd46 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_46_V_q1; + end else if ((6'd44 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_44_V_q1; + end else if ((6'd42 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_42_V_q1; + end else if ((6'd40 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_40_V_q1; + end else if ((6'd38 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_38_V_q1; + end else if ((6'd36 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_36_V_q1; + end else if ((6'd34 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_34_V_q1; + end else if ((6'd32 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_32_V_q1; + end else if ((6'd30 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_30_V_q1; + end else if ((6'd28 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_28_V_q1; + end else if ((6'd26 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_26_V_q1; + end else if ((6'd24 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_24_V_q1; + end else if ((6'd22 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_22_V_q1; + end else if ((6'd20 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_20_V_q1; + end else if ((6'd18 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_18_V_q1; + end else if ((6'd16 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_16_V_q1; + end else if ((6'd14 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_14_V_q1; + end else if ((6'd12 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_12_V_q1; + end else if ((6'd10 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_10_V_q1; + end else if ((6'd8 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_8_V_q1; + end else if ((6'd6 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_6_V_q1; + end else if ((6'd4 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_4_V_q1; + end else if ((6'd2 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_2_V_q1; + end else if ((6'd0 == add_ln1265_reg_147629)) begin + phi_ln1265_8_reg_96169 <= acc_0_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2729 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_24171)) begin + phi_ln1265_9_reg_96265 <= acc_63_V_q1; + end else if ((6'd62 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_62_V_q1; + end else if ((6'd60 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_60_V_q1; + end else if ((6'd58 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_58_V_q1; + end else if ((6'd56 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_56_V_q1; + end else if ((6'd54 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_54_V_q1; + end else if ((6'd52 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_52_V_q1; + end else if ((6'd50 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_50_V_q1; + end else if ((6'd48 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_48_V_q1; + end else if ((6'd46 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_46_V_q1; + end else if ((6'd44 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_44_V_q1; + end else if ((6'd42 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_42_V_q1; + end else if ((6'd40 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_40_V_q1; + end else if ((6'd38 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_38_V_q1; + end else if ((6'd36 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_36_V_q1; + end else if ((6'd34 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_34_V_q1; + end else if ((6'd32 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_32_V_q1; + end else if ((6'd30 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_30_V_q1; + end else if ((6'd28 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_28_V_q1; + end else if ((6'd26 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_26_V_q1; + end else if ((6'd24 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_24_V_q1; + end else if ((6'd22 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_22_V_q1; + end else if ((6'd20 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_20_V_q1; + end else if ((6'd18 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_18_V_q1; + end else if ((6'd16 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_16_V_q1; + end else if ((6'd14 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_14_V_q1; + end else if ((6'd12 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_12_V_q1; + end else if ((6'd10 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_10_V_q1; + end else if ((6'd8 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_8_V_q1; + end else if ((6'd6 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_6_V_q1; + end else if ((6'd4 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_4_V_q1; + end else if ((6'd2 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_2_V_q1; + end else if ((6'd0 == add_ln1265_reg_147629)) begin + phi_ln1265_9_reg_96265 <= acc_0_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2574 == ap_CS_fsm)) begin + if ((1'b1 == ap_condition_24171)) begin + phi_ln1265_reg_96085 <= acc_63_V_q1; + end else if ((6'd62 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_62_V_q1; + end else if ((6'd60 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_60_V_q1; + end else if ((6'd58 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_58_V_q1; + end else if ((6'd56 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_56_V_q1; + end else if ((6'd54 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_54_V_q1; + end else if ((6'd52 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_52_V_q1; + end else if ((6'd50 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_50_V_q1; + end else if ((6'd48 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_48_V_q1; + end else if ((6'd46 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_46_V_q1; + end else if ((6'd44 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_44_V_q1; + end else if ((6'd42 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_42_V_q1; + end else if ((6'd40 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_40_V_q1; + end else if ((6'd38 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_38_V_q1; + end else if ((6'd36 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_36_V_q1; + end else if ((6'd34 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_34_V_q1; + end else if ((6'd32 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_32_V_q1; + end else if ((6'd30 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_30_V_q1; + end else if ((6'd28 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_28_V_q1; + end else if ((6'd26 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_26_V_q1; + end else if ((6'd24 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_24_V_q1; + end else if ((6'd22 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_22_V_q1; + end else if ((6'd20 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_20_V_q1; + end else if ((6'd18 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_18_V_q1; + end else if ((6'd16 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_16_V_q1; + end else if ((6'd14 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_14_V_q1; + end else if ((6'd12 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_12_V_q1; + end else if ((6'd10 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_10_V_q1; + end else if ((6'd8 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_8_V_q1; + end else if ((6'd6 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_6_V_q1; + end else if ((6'd4 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_4_V_q1; + end else if ((6'd2 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_2_V_q1; + end else if ((6'd0 == add_ln1265_reg_147629)) begin + phi_ln1265_reg_96085 <= acc_0_V_q1; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln204_2_fu_105463_p2 == 1'd1) & (ap_ST_fsm_state611 == ap_CS_fsm))) begin + phi_mul135689_reg_92370 <= add_ln203_14_reg_135260; + end else if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln203_fu_101988_p2 == 1'd1))) begin + phi_mul135689_reg_92370 <= 11'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln204_1_fu_108914_p2 == 1'd1) & (ap_ST_fsm_state1217 == ap_CS_fsm))) begin + phi_mul135708_reg_93568 <= add_ln203_13_reg_138856; + end else if (((icmp_ln201_1_fu_108832_p2 == 1'd0) & (ap_ST_fsm_state1215 == ap_CS_fsm))) begin + phi_mul135708_reg_93568 <= 11'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln204_3_fu_112317_p2 == 1'd1) & (ap_ST_fsm_state1822 == ap_CS_fsm))) begin + phi_mul135727_reg_94754 <= add_ln203_15_reg_142423; + end else if (((icmp_ln203_1_fu_108860_p2 == 1'd1) & (ap_ST_fsm_state1216 == ap_CS_fsm))) begin + phi_mul135727_reg_94754 <= 11'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state5 == ap_CS_fsm) & (icmp_ln204_fu_102042_p2 == 1'd1))) begin + phi_mul_reg_91184 <= add_ln203_12_reg_131677; + end else if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln201_fu_101946_p2 == 1'd0))) begin + phi_mul_reg_91184 <= 11'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2570 == ap_CS_fsm) & (icmp_ln261_fu_117325_p2 == 1'd0))) begin + acc_0_V_addr_37_reg_147633 <= zext_ln1265_fu_117359_p1; + acc_10_V_addr_37_reg_147688 <= zext_ln1265_fu_117359_p1; + acc_11_V_addr_37_reg_147694 <= zext_ln1265_fu_117359_p1; + acc_12_V_addr_37_reg_147699 <= zext_ln1265_fu_117359_p1; + acc_13_V_addr_37_reg_147705 <= zext_ln1265_fu_117359_p1; + acc_14_V_addr_37_reg_147710 <= zext_ln1265_fu_117359_p1; + acc_15_V_addr_37_reg_147716 <= zext_ln1265_fu_117359_p1; + acc_16_V_addr_37_reg_147721 <= zext_ln1265_fu_117359_p1; + acc_17_V_addr_37_reg_147727 <= zext_ln1265_fu_117359_p1; + acc_18_V_addr_37_reg_147732 <= zext_ln1265_fu_117359_p1; + acc_19_V_addr_37_reg_147738 <= zext_ln1265_fu_117359_p1; + acc_1_V_addr_37_reg_147639 <= zext_ln1265_fu_117359_p1; + acc_20_V_addr_37_reg_147743 <= zext_ln1265_fu_117359_p1; + acc_21_V_addr_37_reg_147749 <= zext_ln1265_fu_117359_p1; + acc_22_V_addr_37_reg_147754 <= zext_ln1265_fu_117359_p1; + acc_23_V_addr_37_reg_147760 <= zext_ln1265_fu_117359_p1; + acc_24_V_addr_37_reg_147765 <= zext_ln1265_fu_117359_p1; + acc_25_V_addr_37_reg_147771 <= zext_ln1265_fu_117359_p1; + acc_26_V_addr_37_reg_147776 <= zext_ln1265_fu_117359_p1; + acc_27_V_addr_37_reg_147782 <= zext_ln1265_fu_117359_p1; + acc_28_V_addr_37_reg_147787 <= zext_ln1265_fu_117359_p1; + acc_29_V_addr_37_reg_147793 <= zext_ln1265_fu_117359_p1; + acc_2_V_addr_37_reg_147644 <= zext_ln1265_fu_117359_p1; + acc_30_V_addr_37_reg_147798 <= zext_ln1265_fu_117359_p1; + acc_31_V_addr_37_reg_147804 <= zext_ln1265_fu_117359_p1; + acc_32_V_addr_37_reg_147809 <= zext_ln1265_fu_117359_p1; + acc_33_V_addr_37_reg_147815 <= zext_ln1265_fu_117359_p1; + acc_34_V_addr_37_reg_147820 <= zext_ln1265_fu_117359_p1; + acc_35_V_addr_37_reg_147826 <= zext_ln1265_fu_117359_p1; + acc_36_V_addr_37_reg_147831 <= zext_ln1265_fu_117359_p1; + acc_37_V_addr_37_reg_147837 <= zext_ln1265_fu_117359_p1; + acc_38_V_addr_37_reg_147842 <= zext_ln1265_fu_117359_p1; + acc_39_V_addr_37_reg_147848 <= zext_ln1265_fu_117359_p1; + acc_3_V_addr_37_reg_147650 <= zext_ln1265_fu_117359_p1; + acc_40_V_addr_37_reg_147853 <= zext_ln1265_fu_117359_p1; + acc_41_V_addr_37_reg_147859 <= zext_ln1265_fu_117359_p1; + acc_42_V_addr_37_reg_147864 <= zext_ln1265_fu_117359_p1; + acc_43_V_addr_37_reg_147870 <= zext_ln1265_fu_117359_p1; + acc_44_V_addr_37_reg_147875 <= zext_ln1265_fu_117359_p1; + acc_45_V_addr_37_reg_147881 <= zext_ln1265_fu_117359_p1; + acc_46_V_addr_37_reg_147886 <= zext_ln1265_fu_117359_p1; + acc_47_V_addr_37_reg_147892 <= zext_ln1265_fu_117359_p1; + acc_48_V_addr_36_reg_147897 <= zext_ln1265_fu_117359_p1; + acc_49_V_addr_36_reg_147903 <= zext_ln1265_fu_117359_p1; + acc_4_V_addr_37_reg_147655 <= zext_ln1265_fu_117359_p1; + acc_50_V_addr_36_reg_147908 <= zext_ln1265_fu_117359_p1; + acc_51_V_addr_36_reg_147914 <= zext_ln1265_fu_117359_p1; + acc_52_V_addr_36_reg_147919 <= zext_ln1265_fu_117359_p1; + acc_53_V_addr_36_reg_147925 <= zext_ln1265_fu_117359_p1; + acc_54_V_addr_36_reg_147930 <= zext_ln1265_fu_117359_p1; + acc_55_V_addr_36_reg_147936 <= zext_ln1265_fu_117359_p1; + acc_56_V_addr_36_reg_147941 <= zext_ln1265_fu_117359_p1; + acc_57_V_addr_36_reg_147947 <= zext_ln1265_fu_117359_p1; + acc_58_V_addr_36_reg_147952 <= zext_ln1265_fu_117359_p1; + acc_59_V_addr_36_reg_147958 <= zext_ln1265_fu_117359_p1; + acc_5_V_addr_37_reg_147661 <= zext_ln1265_fu_117359_p1; + acc_60_V_addr_36_reg_147963 <= zext_ln1265_fu_117359_p1; + acc_61_V_addr_36_reg_147969 <= zext_ln1265_fu_117359_p1; + acc_62_V_addr_36_reg_147974 <= zext_ln1265_fu_117359_p1; + acc_63_V_addr_36_reg_147980 <= zext_ln1265_fu_117359_p1; + acc_6_V_addr_37_reg_147666 <= zext_ln1265_fu_117359_p1; + acc_7_V_addr_37_reg_147672 <= zext_ln1265_fu_117359_p1; + acc_8_V_addr_37_reg_147677 <= zext_ln1265_fu_117359_p1; + acc_9_V_addr_37_reg_147683 <= zext_ln1265_fu_117359_p1; + add_ln1265_reg_147629 <= add_ln1265_fu_117340_p2; + add_ln276_2_reg_147986 <= grp_fu_131413_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3801 == ap_CS_fsm) & (icmp_ln261_1_fu_124367_p2 == 1'd0))) begin + acc_0_V_addr_39_reg_157443 <= zext_ln1265_1_fu_124401_p1; + acc_10_V_addr_39_reg_157503 <= zext_ln1265_1_fu_124401_p1; + acc_11_V_addr_39_reg_157509 <= zext_ln1265_1_fu_124401_p1; + acc_12_V_addr_39_reg_157515 <= zext_ln1265_1_fu_124401_p1; + acc_13_V_addr_39_reg_157521 <= zext_ln1265_1_fu_124401_p1; + acc_14_V_addr_39_reg_157527 <= zext_ln1265_1_fu_124401_p1; + acc_15_V_addr_39_reg_157533 <= zext_ln1265_1_fu_124401_p1; + acc_16_V_addr_39_reg_157539 <= zext_ln1265_1_fu_124401_p1; + acc_17_V_addr_39_reg_157545 <= zext_ln1265_1_fu_124401_p1; + acc_18_V_addr_39_reg_157551 <= zext_ln1265_1_fu_124401_p1; + acc_19_V_addr_39_reg_157557 <= zext_ln1265_1_fu_124401_p1; + acc_1_V_addr_39_reg_157449 <= zext_ln1265_1_fu_124401_p1; + acc_20_V_addr_39_reg_157563 <= zext_ln1265_1_fu_124401_p1; + acc_21_V_addr_39_reg_157569 <= zext_ln1265_1_fu_124401_p1; + acc_22_V_addr_39_reg_157575 <= zext_ln1265_1_fu_124401_p1; + acc_23_V_addr_39_reg_157581 <= zext_ln1265_1_fu_124401_p1; + acc_24_V_addr_39_reg_157587 <= zext_ln1265_1_fu_124401_p1; + acc_25_V_addr_39_reg_157593 <= zext_ln1265_1_fu_124401_p1; + acc_26_V_addr_39_reg_157599 <= zext_ln1265_1_fu_124401_p1; + acc_27_V_addr_39_reg_157605 <= zext_ln1265_1_fu_124401_p1; + acc_28_V_addr_39_reg_157611 <= zext_ln1265_1_fu_124401_p1; + acc_29_V_addr_39_reg_157617 <= zext_ln1265_1_fu_124401_p1; + acc_2_V_addr_39_reg_157455 <= zext_ln1265_1_fu_124401_p1; + acc_30_V_addr_39_reg_157623 <= zext_ln1265_1_fu_124401_p1; + acc_31_V_addr_39_reg_157629 <= zext_ln1265_1_fu_124401_p1; + acc_32_V_addr_39_reg_157635 <= zext_ln1265_1_fu_124401_p1; + acc_33_V_addr_39_reg_157641 <= zext_ln1265_1_fu_124401_p1; + acc_34_V_addr_39_reg_157647 <= zext_ln1265_1_fu_124401_p1; + acc_35_V_addr_39_reg_157653 <= zext_ln1265_1_fu_124401_p1; + acc_36_V_addr_39_reg_157659 <= zext_ln1265_1_fu_124401_p1; + acc_37_V_addr_39_reg_157665 <= zext_ln1265_1_fu_124401_p1; + acc_38_V_addr_39_reg_157671 <= zext_ln1265_1_fu_124401_p1; + acc_39_V_addr_39_reg_157677 <= zext_ln1265_1_fu_124401_p1; + acc_3_V_addr_39_reg_157461 <= zext_ln1265_1_fu_124401_p1; + acc_40_V_addr_39_reg_157683 <= zext_ln1265_1_fu_124401_p1; + acc_41_V_addr_39_reg_157689 <= zext_ln1265_1_fu_124401_p1; + acc_42_V_addr_39_reg_157695 <= zext_ln1265_1_fu_124401_p1; + acc_43_V_addr_39_reg_157701 <= zext_ln1265_1_fu_124401_p1; + acc_44_V_addr_39_reg_157707 <= zext_ln1265_1_fu_124401_p1; + acc_45_V_addr_39_reg_157713 <= zext_ln1265_1_fu_124401_p1; + acc_46_V_addr_39_reg_157719 <= zext_ln1265_1_fu_124401_p1; + acc_47_V_addr_39_reg_157725 <= zext_ln1265_1_fu_124401_p1; + acc_48_V_addr_38_reg_157731 <= zext_ln1265_1_fu_124401_p1; + acc_49_V_addr_38_reg_157737 <= zext_ln1265_1_fu_124401_p1; + acc_4_V_addr_39_reg_157467 <= zext_ln1265_1_fu_124401_p1; + acc_50_V_addr_38_reg_157743 <= zext_ln1265_1_fu_124401_p1; + acc_51_V_addr_38_reg_157749 <= zext_ln1265_1_fu_124401_p1; + acc_52_V_addr_38_reg_157755 <= zext_ln1265_1_fu_124401_p1; + acc_53_V_addr_38_reg_157761 <= zext_ln1265_1_fu_124401_p1; + acc_54_V_addr_38_reg_157767 <= zext_ln1265_1_fu_124401_p1; + acc_55_V_addr_38_reg_157773 <= zext_ln1265_1_fu_124401_p1; + acc_56_V_addr_38_reg_157779 <= zext_ln1265_1_fu_124401_p1; + acc_57_V_addr_38_reg_157785 <= zext_ln1265_1_fu_124401_p1; + acc_58_V_addr_38_reg_157791 <= zext_ln1265_1_fu_124401_p1; + acc_59_V_addr_38_reg_157797 <= zext_ln1265_1_fu_124401_p1; + acc_5_V_addr_39_reg_157473 <= zext_ln1265_1_fu_124401_p1; + acc_60_V_addr_38_reg_157803 <= zext_ln1265_1_fu_124401_p1; + acc_61_V_addr_38_reg_157809 <= zext_ln1265_1_fu_124401_p1; + acc_62_V_addr_38_reg_157815 <= zext_ln1265_1_fu_124401_p1; + acc_63_V_addr_38_reg_157821 <= zext_ln1265_1_fu_124401_p1; + acc_6_V_addr_39_reg_157479 <= zext_ln1265_1_fu_124401_p1; + acc_7_V_addr_39_reg_157485 <= zext_ln1265_1_fu_124401_p1; + acc_8_V_addr_39_reg_157491 <= zext_ln1265_1_fu_124401_p1; + acc_9_V_addr_39_reg_157497 <= zext_ln1265_1_fu_124401_p1; + add_ln1265_1_reg_157439 <= add_ln1265_1_fu_124382_p2; + add_ln276_8_reg_157827 <= grp_fu_131519_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3186 == ap_CS_fsm) & (icmp_ln261_2_fu_120840_p2 == 1'd0))) begin + acc_0_V_addr_40_reg_152516 <= zext_ln1265_2_fu_120874_p1; + acc_10_V_addr_40_reg_152576 <= zext_ln1265_2_fu_120874_p1; + acc_11_V_addr_40_reg_152582 <= zext_ln1265_2_fu_120874_p1; + acc_12_V_addr_40_reg_152588 <= zext_ln1265_2_fu_120874_p1; + acc_13_V_addr_40_reg_152594 <= zext_ln1265_2_fu_120874_p1; + acc_14_V_addr_40_reg_152600 <= zext_ln1265_2_fu_120874_p1; + acc_15_V_addr_40_reg_152606 <= zext_ln1265_2_fu_120874_p1; + acc_16_V_addr_40_reg_152612 <= zext_ln1265_2_fu_120874_p1; + acc_17_V_addr_40_reg_152618 <= zext_ln1265_2_fu_120874_p1; + acc_18_V_addr_40_reg_152624 <= zext_ln1265_2_fu_120874_p1; + acc_19_V_addr_40_reg_152630 <= zext_ln1265_2_fu_120874_p1; + acc_1_V_addr_40_reg_152522 <= zext_ln1265_2_fu_120874_p1; + acc_20_V_addr_40_reg_152636 <= zext_ln1265_2_fu_120874_p1; + acc_21_V_addr_40_reg_152642 <= zext_ln1265_2_fu_120874_p1; + acc_22_V_addr_40_reg_152648 <= zext_ln1265_2_fu_120874_p1; + acc_23_V_addr_40_reg_152654 <= zext_ln1265_2_fu_120874_p1; + acc_24_V_addr_40_reg_152660 <= zext_ln1265_2_fu_120874_p1; + acc_25_V_addr_40_reg_152666 <= zext_ln1265_2_fu_120874_p1; + acc_26_V_addr_40_reg_152672 <= zext_ln1265_2_fu_120874_p1; + acc_27_V_addr_40_reg_152678 <= zext_ln1265_2_fu_120874_p1; + acc_28_V_addr_40_reg_152684 <= zext_ln1265_2_fu_120874_p1; + acc_29_V_addr_40_reg_152690 <= zext_ln1265_2_fu_120874_p1; + acc_2_V_addr_40_reg_152528 <= zext_ln1265_2_fu_120874_p1; + acc_30_V_addr_40_reg_152696 <= zext_ln1265_2_fu_120874_p1; + acc_31_V_addr_40_reg_152702 <= zext_ln1265_2_fu_120874_p1; + acc_32_V_addr_40_reg_152708 <= zext_ln1265_2_fu_120874_p1; + acc_33_V_addr_40_reg_152714 <= zext_ln1265_2_fu_120874_p1; + acc_34_V_addr_40_reg_152720 <= zext_ln1265_2_fu_120874_p1; + acc_35_V_addr_40_reg_152726 <= zext_ln1265_2_fu_120874_p1; + acc_36_V_addr_40_reg_152732 <= zext_ln1265_2_fu_120874_p1; + acc_37_V_addr_40_reg_152738 <= zext_ln1265_2_fu_120874_p1; + acc_38_V_addr_40_reg_152744 <= zext_ln1265_2_fu_120874_p1; + acc_39_V_addr_40_reg_152750 <= zext_ln1265_2_fu_120874_p1; + acc_3_V_addr_40_reg_152534 <= zext_ln1265_2_fu_120874_p1; + acc_40_V_addr_40_reg_152756 <= zext_ln1265_2_fu_120874_p1; + acc_41_V_addr_40_reg_152762 <= zext_ln1265_2_fu_120874_p1; + acc_42_V_addr_40_reg_152768 <= zext_ln1265_2_fu_120874_p1; + acc_43_V_addr_40_reg_152774 <= zext_ln1265_2_fu_120874_p1; + acc_44_V_addr_40_reg_152780 <= zext_ln1265_2_fu_120874_p1; + acc_45_V_addr_40_reg_152786 <= zext_ln1265_2_fu_120874_p1; + acc_46_V_addr_40_reg_152792 <= zext_ln1265_2_fu_120874_p1; + acc_47_V_addr_40_reg_152798 <= zext_ln1265_2_fu_120874_p1; + acc_48_V_addr_39_reg_152804 <= zext_ln1265_2_fu_120874_p1; + acc_49_V_addr_39_reg_152810 <= zext_ln1265_2_fu_120874_p1; + acc_4_V_addr_40_reg_152540 <= zext_ln1265_2_fu_120874_p1; + acc_50_V_addr_39_reg_152816 <= zext_ln1265_2_fu_120874_p1; + acc_51_V_addr_39_reg_152822 <= zext_ln1265_2_fu_120874_p1; + acc_52_V_addr_39_reg_152828 <= zext_ln1265_2_fu_120874_p1; + acc_53_V_addr_39_reg_152834 <= zext_ln1265_2_fu_120874_p1; + acc_54_V_addr_39_reg_152840 <= zext_ln1265_2_fu_120874_p1; + acc_55_V_addr_39_reg_152846 <= zext_ln1265_2_fu_120874_p1; + acc_56_V_addr_39_reg_152852 <= zext_ln1265_2_fu_120874_p1; + acc_57_V_addr_39_reg_152858 <= zext_ln1265_2_fu_120874_p1; + acc_58_V_addr_39_reg_152864 <= zext_ln1265_2_fu_120874_p1; + acc_59_V_addr_39_reg_152870 <= zext_ln1265_2_fu_120874_p1; + acc_5_V_addr_40_reg_152546 <= zext_ln1265_2_fu_120874_p1; + acc_60_V_addr_39_reg_152876 <= zext_ln1265_2_fu_120874_p1; + acc_61_V_addr_39_reg_152882 <= zext_ln1265_2_fu_120874_p1; + acc_62_V_addr_39_reg_152888 <= zext_ln1265_2_fu_120874_p1; + acc_63_V_addr_39_reg_152894 <= zext_ln1265_2_fu_120874_p1; + acc_6_V_addr_40_reg_152552 <= zext_ln1265_2_fu_120874_p1; + acc_7_V_addr_40_reg_152558 <= zext_ln1265_2_fu_120874_p1; + acc_8_V_addr_40_reg_152564 <= zext_ln1265_2_fu_120874_p1; + acc_9_V_addr_40_reg_152570 <= zext_ln1265_2_fu_120874_p1; + add_ln1265_2_reg_152512 <= add_ln1265_2_fu_120855_p2; + add_ln276_9_reg_152900 <= grp_fu_131466_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln264_fu_117484_p2 == 1'd1) & (ap_ST_fsm_state2571 == ap_CS_fsm))) begin + acc_0_V_addr_41_reg_148023 <= zext_ln1265_3_fu_117535_p1; + acc_10_V_addr_41_reg_148083 <= zext_ln1265_3_fu_117535_p1; + acc_11_V_addr_41_reg_148089 <= zext_ln1265_3_fu_117535_p1; + acc_12_V_addr_41_reg_148095 <= zext_ln1265_3_fu_117535_p1; + acc_13_V_addr_41_reg_148101 <= zext_ln1265_3_fu_117535_p1; + acc_14_V_addr_41_reg_148107 <= zext_ln1265_3_fu_117535_p1; + acc_15_V_addr_41_reg_148113 <= zext_ln1265_3_fu_117535_p1; + acc_16_V_addr_41_reg_148119 <= zext_ln1265_3_fu_117535_p1; + acc_17_V_addr_41_reg_148125 <= zext_ln1265_3_fu_117535_p1; + acc_18_V_addr_41_reg_148131 <= zext_ln1265_3_fu_117535_p1; + acc_19_V_addr_41_reg_148137 <= zext_ln1265_3_fu_117535_p1; + acc_1_V_addr_41_reg_148029 <= zext_ln1265_3_fu_117535_p1; + acc_20_V_addr_41_reg_148143 <= zext_ln1265_3_fu_117535_p1; + acc_21_V_addr_41_reg_148149 <= zext_ln1265_3_fu_117535_p1; + acc_22_V_addr_41_reg_148155 <= zext_ln1265_3_fu_117535_p1; + acc_23_V_addr_41_reg_148161 <= zext_ln1265_3_fu_117535_p1; + acc_24_V_addr_41_reg_148167 <= zext_ln1265_3_fu_117535_p1; + acc_25_V_addr_41_reg_148173 <= zext_ln1265_3_fu_117535_p1; + acc_26_V_addr_41_reg_148179 <= zext_ln1265_3_fu_117535_p1; + acc_27_V_addr_41_reg_148185 <= zext_ln1265_3_fu_117535_p1; + acc_28_V_addr_41_reg_148191 <= zext_ln1265_3_fu_117535_p1; + acc_29_V_addr_41_reg_148197 <= zext_ln1265_3_fu_117535_p1; + acc_2_V_addr_41_reg_148035 <= zext_ln1265_3_fu_117535_p1; + acc_30_V_addr_41_reg_148203 <= zext_ln1265_3_fu_117535_p1; + acc_31_V_addr_41_reg_148209 <= zext_ln1265_3_fu_117535_p1; + acc_32_V_addr_41_reg_148215 <= zext_ln1265_3_fu_117535_p1; + acc_33_V_addr_41_reg_148221 <= zext_ln1265_3_fu_117535_p1; + acc_34_V_addr_41_reg_148227 <= zext_ln1265_3_fu_117535_p1; + acc_35_V_addr_41_reg_148233 <= zext_ln1265_3_fu_117535_p1; + acc_36_V_addr_41_reg_148239 <= zext_ln1265_3_fu_117535_p1; + acc_37_V_addr_41_reg_148245 <= zext_ln1265_3_fu_117535_p1; + acc_38_V_addr_41_reg_148251 <= zext_ln1265_3_fu_117535_p1; + acc_39_V_addr_41_reg_148257 <= zext_ln1265_3_fu_117535_p1; + acc_3_V_addr_41_reg_148041 <= zext_ln1265_3_fu_117535_p1; + acc_40_V_addr_41_reg_148263 <= zext_ln1265_3_fu_117535_p1; + acc_41_V_addr_41_reg_148269 <= zext_ln1265_3_fu_117535_p1; + acc_42_V_addr_41_reg_148275 <= zext_ln1265_3_fu_117535_p1; + acc_43_V_addr_41_reg_148281 <= zext_ln1265_3_fu_117535_p1; + acc_44_V_addr_41_reg_148287 <= zext_ln1265_3_fu_117535_p1; + acc_45_V_addr_41_reg_148293 <= zext_ln1265_3_fu_117535_p1; + acc_46_V_addr_41_reg_148299 <= zext_ln1265_3_fu_117535_p1; + acc_47_V_addr_41_reg_148305 <= zext_ln1265_3_fu_117535_p1; + acc_48_V_addr_40_reg_148311 <= zext_ln1265_3_fu_117535_p1; + acc_49_V_addr_40_reg_148317 <= zext_ln1265_3_fu_117535_p1; + acc_4_V_addr_41_reg_148047 <= zext_ln1265_3_fu_117535_p1; + acc_50_V_addr_40_reg_148323 <= zext_ln1265_3_fu_117535_p1; + acc_51_V_addr_40_reg_148329 <= zext_ln1265_3_fu_117535_p1; + acc_52_V_addr_40_reg_148335 <= zext_ln1265_3_fu_117535_p1; + acc_53_V_addr_40_reg_148341 <= zext_ln1265_3_fu_117535_p1; + acc_54_V_addr_40_reg_148347 <= zext_ln1265_3_fu_117535_p1; + acc_55_V_addr_40_reg_148353 <= zext_ln1265_3_fu_117535_p1; + acc_56_V_addr_40_reg_148359 <= zext_ln1265_3_fu_117535_p1; + acc_57_V_addr_40_reg_148365 <= zext_ln1265_3_fu_117535_p1; + acc_58_V_addr_40_reg_148371 <= zext_ln1265_3_fu_117535_p1; + acc_59_V_addr_40_reg_148377 <= zext_ln1265_3_fu_117535_p1; + acc_5_V_addr_41_reg_148053 <= zext_ln1265_3_fu_117535_p1; + acc_60_V_addr_40_reg_148383 <= zext_ln1265_3_fu_117535_p1; + acc_61_V_addr_40_reg_148389 <= zext_ln1265_3_fu_117535_p1; + acc_62_V_addr_40_reg_148395 <= zext_ln1265_3_fu_117535_p1; + acc_63_V_addr_40_reg_148401 <= zext_ln1265_3_fu_117535_p1; + acc_6_V_addr_41_reg_148059 <= zext_ln1265_3_fu_117535_p1; + acc_7_V_addr_41_reg_148065 <= zext_ln1265_3_fu_117535_p1; + acc_8_V_addr_41_reg_148071 <= zext_ln1265_3_fu_117535_p1; + acc_9_V_addr_41_reg_148077 <= zext_ln1265_3_fu_117535_p1; + add_ln1265_3_reg_148019[5 : 1] <= add_ln1265_3_fu_117516_p2[5 : 1]; + add_ln276_10_reg_148407 <= grp_fu_131435_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4415 == ap_CS_fsm) & (icmp_ln261_3_fu_127882_p2 == 1'd0))) begin + acc_0_V_addr_44_reg_162357 <= zext_ln1265_4_fu_127916_p1; + acc_10_V_addr_44_reg_162417 <= zext_ln1265_4_fu_127916_p1; + acc_11_V_addr_44_reg_162423 <= zext_ln1265_4_fu_127916_p1; + acc_12_V_addr_44_reg_162429 <= zext_ln1265_4_fu_127916_p1; + acc_13_V_addr_44_reg_162435 <= zext_ln1265_4_fu_127916_p1; + acc_14_V_addr_44_reg_162441 <= zext_ln1265_4_fu_127916_p1; + acc_15_V_addr_44_reg_162447 <= zext_ln1265_4_fu_127916_p1; + acc_16_V_addr_44_reg_162453 <= zext_ln1265_4_fu_127916_p1; + acc_17_V_addr_44_reg_162459 <= zext_ln1265_4_fu_127916_p1; + acc_18_V_addr_44_reg_162465 <= zext_ln1265_4_fu_127916_p1; + acc_19_V_addr_44_reg_162471 <= zext_ln1265_4_fu_127916_p1; + acc_1_V_addr_44_reg_162363 <= zext_ln1265_4_fu_127916_p1; + acc_20_V_addr_44_reg_162477 <= zext_ln1265_4_fu_127916_p1; + acc_21_V_addr_44_reg_162483 <= zext_ln1265_4_fu_127916_p1; + acc_22_V_addr_44_reg_162489 <= zext_ln1265_4_fu_127916_p1; + acc_23_V_addr_44_reg_162495 <= zext_ln1265_4_fu_127916_p1; + acc_24_V_addr_44_reg_162501 <= zext_ln1265_4_fu_127916_p1; + acc_25_V_addr_44_reg_162507 <= zext_ln1265_4_fu_127916_p1; + acc_26_V_addr_44_reg_162513 <= zext_ln1265_4_fu_127916_p1; + acc_27_V_addr_44_reg_162519 <= zext_ln1265_4_fu_127916_p1; + acc_28_V_addr_44_reg_162525 <= zext_ln1265_4_fu_127916_p1; + acc_29_V_addr_44_reg_162531 <= zext_ln1265_4_fu_127916_p1; + acc_2_V_addr_44_reg_162369 <= zext_ln1265_4_fu_127916_p1; + acc_30_V_addr_44_reg_162537 <= zext_ln1265_4_fu_127916_p1; + acc_31_V_addr_44_reg_162543 <= zext_ln1265_4_fu_127916_p1; + acc_32_V_addr_44_reg_162549 <= zext_ln1265_4_fu_127916_p1; + acc_33_V_addr_44_reg_162555 <= zext_ln1265_4_fu_127916_p1; + acc_34_V_addr_44_reg_162561 <= zext_ln1265_4_fu_127916_p1; + acc_35_V_addr_44_reg_162567 <= zext_ln1265_4_fu_127916_p1; + acc_36_V_addr_44_reg_162573 <= zext_ln1265_4_fu_127916_p1; + acc_37_V_addr_44_reg_162579 <= zext_ln1265_4_fu_127916_p1; + acc_38_V_addr_44_reg_162585 <= zext_ln1265_4_fu_127916_p1; + acc_39_V_addr_44_reg_162591 <= zext_ln1265_4_fu_127916_p1; + acc_3_V_addr_44_reg_162375 <= zext_ln1265_4_fu_127916_p1; + acc_40_V_addr_44_reg_162597 <= zext_ln1265_4_fu_127916_p1; + acc_41_V_addr_44_reg_162603 <= zext_ln1265_4_fu_127916_p1; + acc_42_V_addr_44_reg_162609 <= zext_ln1265_4_fu_127916_p1; + acc_43_V_addr_44_reg_162615 <= zext_ln1265_4_fu_127916_p1; + acc_44_V_addr_44_reg_162621 <= zext_ln1265_4_fu_127916_p1; + acc_45_V_addr_44_reg_162627 <= zext_ln1265_4_fu_127916_p1; + acc_46_V_addr_44_reg_162633 <= zext_ln1265_4_fu_127916_p1; + acc_47_V_addr_44_reg_162639 <= zext_ln1265_4_fu_127916_p1; + acc_48_V_addr_43_reg_162645 <= zext_ln1265_4_fu_127916_p1; + acc_49_V_addr_43_reg_162651 <= zext_ln1265_4_fu_127916_p1; + acc_4_V_addr_44_reg_162381 <= zext_ln1265_4_fu_127916_p1; + acc_50_V_addr_43_reg_162657 <= zext_ln1265_4_fu_127916_p1; + acc_51_V_addr_43_reg_162663 <= zext_ln1265_4_fu_127916_p1; + acc_52_V_addr_43_reg_162669 <= zext_ln1265_4_fu_127916_p1; + acc_53_V_addr_43_reg_162675 <= zext_ln1265_4_fu_127916_p1; + acc_54_V_addr_43_reg_162681 <= zext_ln1265_4_fu_127916_p1; + acc_55_V_addr_43_reg_162687 <= zext_ln1265_4_fu_127916_p1; + acc_56_V_addr_43_reg_162693 <= zext_ln1265_4_fu_127916_p1; + acc_57_V_addr_43_reg_162699 <= zext_ln1265_4_fu_127916_p1; + acc_58_V_addr_43_reg_162705 <= zext_ln1265_4_fu_127916_p1; + acc_59_V_addr_43_reg_162711 <= zext_ln1265_4_fu_127916_p1; + acc_5_V_addr_44_reg_162387 <= zext_ln1265_4_fu_127916_p1; + acc_60_V_addr_43_reg_162717 <= zext_ln1265_4_fu_127916_p1; + acc_61_V_addr_43_reg_162723 <= zext_ln1265_4_fu_127916_p1; + acc_62_V_addr_43_reg_162729 <= zext_ln1265_4_fu_127916_p1; + acc_63_V_addr_43_reg_162735 <= zext_ln1265_4_fu_127916_p1; + acc_6_V_addr_44_reg_162393 <= zext_ln1265_4_fu_127916_p1; + acc_7_V_addr_44_reg_162399 <= zext_ln1265_4_fu_127916_p1; + acc_8_V_addr_44_reg_162405 <= zext_ln1265_4_fu_127916_p1; + acc_9_V_addr_44_reg_162411 <= zext_ln1265_4_fu_127916_p1; + add_ln1265_4_reg_162353 <= add_ln1265_4_fu_127897_p2; + add_ln276_15_reg_162741 <= grp_fu_131572_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln264_1_fu_124526_p2 == 1'd1) & (ap_ST_fsm_state3802 == ap_CS_fsm))) begin + acc_0_V_addr_45_reg_157864 <= zext_ln1265_5_fu_124577_p1; + acc_10_V_addr_45_reg_157924 <= zext_ln1265_5_fu_124577_p1; + acc_11_V_addr_45_reg_157930 <= zext_ln1265_5_fu_124577_p1; + acc_12_V_addr_45_reg_157936 <= zext_ln1265_5_fu_124577_p1; + acc_13_V_addr_45_reg_157942 <= zext_ln1265_5_fu_124577_p1; + acc_14_V_addr_45_reg_157948 <= zext_ln1265_5_fu_124577_p1; + acc_15_V_addr_45_reg_157954 <= zext_ln1265_5_fu_124577_p1; + acc_16_V_addr_45_reg_157960 <= zext_ln1265_5_fu_124577_p1; + acc_17_V_addr_45_reg_157966 <= zext_ln1265_5_fu_124577_p1; + acc_18_V_addr_45_reg_157972 <= zext_ln1265_5_fu_124577_p1; + acc_19_V_addr_45_reg_157978 <= zext_ln1265_5_fu_124577_p1; + acc_1_V_addr_45_reg_157870 <= zext_ln1265_5_fu_124577_p1; + acc_20_V_addr_45_reg_157984 <= zext_ln1265_5_fu_124577_p1; + acc_21_V_addr_45_reg_157990 <= zext_ln1265_5_fu_124577_p1; + acc_22_V_addr_45_reg_157996 <= zext_ln1265_5_fu_124577_p1; + acc_23_V_addr_45_reg_158002 <= zext_ln1265_5_fu_124577_p1; + acc_24_V_addr_45_reg_158008 <= zext_ln1265_5_fu_124577_p1; + acc_25_V_addr_45_reg_158014 <= zext_ln1265_5_fu_124577_p1; + acc_26_V_addr_45_reg_158020 <= zext_ln1265_5_fu_124577_p1; + acc_27_V_addr_45_reg_158026 <= zext_ln1265_5_fu_124577_p1; + acc_28_V_addr_45_reg_158032 <= zext_ln1265_5_fu_124577_p1; + acc_29_V_addr_45_reg_158038 <= zext_ln1265_5_fu_124577_p1; + acc_2_V_addr_45_reg_157876 <= zext_ln1265_5_fu_124577_p1; + acc_30_V_addr_45_reg_158044 <= zext_ln1265_5_fu_124577_p1; + acc_31_V_addr_45_reg_158050 <= zext_ln1265_5_fu_124577_p1; + acc_32_V_addr_45_reg_158056 <= zext_ln1265_5_fu_124577_p1; + acc_33_V_addr_45_reg_158062 <= zext_ln1265_5_fu_124577_p1; + acc_34_V_addr_45_reg_158068 <= zext_ln1265_5_fu_124577_p1; + acc_35_V_addr_45_reg_158074 <= zext_ln1265_5_fu_124577_p1; + acc_36_V_addr_45_reg_158080 <= zext_ln1265_5_fu_124577_p1; + acc_37_V_addr_45_reg_158086 <= zext_ln1265_5_fu_124577_p1; + acc_38_V_addr_45_reg_158092 <= zext_ln1265_5_fu_124577_p1; + acc_39_V_addr_45_reg_158098 <= zext_ln1265_5_fu_124577_p1; + acc_3_V_addr_45_reg_157882 <= zext_ln1265_5_fu_124577_p1; + acc_40_V_addr_45_reg_158104 <= zext_ln1265_5_fu_124577_p1; + acc_41_V_addr_45_reg_158110 <= zext_ln1265_5_fu_124577_p1; + acc_42_V_addr_45_reg_158116 <= zext_ln1265_5_fu_124577_p1; + acc_43_V_addr_45_reg_158122 <= zext_ln1265_5_fu_124577_p1; + acc_44_V_addr_45_reg_158128 <= zext_ln1265_5_fu_124577_p1; + acc_45_V_addr_45_reg_158134 <= zext_ln1265_5_fu_124577_p1; + acc_46_V_addr_45_reg_158140 <= zext_ln1265_5_fu_124577_p1; + acc_47_V_addr_45_reg_158146 <= zext_ln1265_5_fu_124577_p1; + acc_48_V_addr_44_reg_158152 <= zext_ln1265_5_fu_124577_p1; + acc_49_V_addr_44_reg_158158 <= zext_ln1265_5_fu_124577_p1; + acc_4_V_addr_45_reg_157888 <= zext_ln1265_5_fu_124577_p1; + acc_50_V_addr_44_reg_158164 <= zext_ln1265_5_fu_124577_p1; + acc_51_V_addr_44_reg_158170 <= zext_ln1265_5_fu_124577_p1; + acc_52_V_addr_44_reg_158176 <= zext_ln1265_5_fu_124577_p1; + acc_53_V_addr_44_reg_158182 <= zext_ln1265_5_fu_124577_p1; + acc_54_V_addr_44_reg_158188 <= zext_ln1265_5_fu_124577_p1; + acc_55_V_addr_44_reg_158194 <= zext_ln1265_5_fu_124577_p1; + acc_56_V_addr_44_reg_158200 <= zext_ln1265_5_fu_124577_p1; + acc_57_V_addr_44_reg_158206 <= zext_ln1265_5_fu_124577_p1; + acc_58_V_addr_44_reg_158212 <= zext_ln1265_5_fu_124577_p1; + acc_59_V_addr_44_reg_158218 <= zext_ln1265_5_fu_124577_p1; + acc_5_V_addr_45_reg_157894 <= zext_ln1265_5_fu_124577_p1; + acc_60_V_addr_44_reg_158224 <= zext_ln1265_5_fu_124577_p1; + acc_61_V_addr_44_reg_158230 <= zext_ln1265_5_fu_124577_p1; + acc_62_V_addr_44_reg_158236 <= zext_ln1265_5_fu_124577_p1; + acc_63_V_addr_44_reg_158242 <= zext_ln1265_5_fu_124577_p1; + acc_6_V_addr_45_reg_157900 <= zext_ln1265_5_fu_124577_p1; + acc_7_V_addr_45_reg_157906 <= zext_ln1265_5_fu_124577_p1; + acc_8_V_addr_45_reg_157912 <= zext_ln1265_5_fu_124577_p1; + acc_9_V_addr_45_reg_157918 <= zext_ln1265_5_fu_124577_p1; + add_ln1265_5_reg_157860[5 : 1] <= add_ln1265_5_fu_124558_p2[5 : 1]; + add_ln276_19_reg_158248 <= grp_fu_131541_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln264_2_fu_120952_p2 == 1'd1) & (ap_ST_fsm_state3187 == ap_CS_fsm))) begin + acc_0_V_addr_46_reg_152924 <= zext_ln1265_6_fu_121003_p1; + acc_10_V_addr_46_reg_152984 <= zext_ln1265_6_fu_121003_p1; + acc_11_V_addr_46_reg_152990 <= zext_ln1265_6_fu_121003_p1; + acc_12_V_addr_46_reg_152996 <= zext_ln1265_6_fu_121003_p1; + acc_13_V_addr_46_reg_153002 <= zext_ln1265_6_fu_121003_p1; + acc_14_V_addr_46_reg_153008 <= zext_ln1265_6_fu_121003_p1; + acc_15_V_addr_46_reg_153014 <= zext_ln1265_6_fu_121003_p1; + acc_16_V_addr_46_reg_153020 <= zext_ln1265_6_fu_121003_p1; + acc_17_V_addr_46_reg_153026 <= zext_ln1265_6_fu_121003_p1; + acc_18_V_addr_46_reg_153032 <= zext_ln1265_6_fu_121003_p1; + acc_19_V_addr_46_reg_153038 <= zext_ln1265_6_fu_121003_p1; + acc_1_V_addr_46_reg_152930 <= zext_ln1265_6_fu_121003_p1; + acc_20_V_addr_46_reg_153044 <= zext_ln1265_6_fu_121003_p1; + acc_21_V_addr_46_reg_153050 <= zext_ln1265_6_fu_121003_p1; + acc_22_V_addr_46_reg_153056 <= zext_ln1265_6_fu_121003_p1; + acc_23_V_addr_46_reg_153062 <= zext_ln1265_6_fu_121003_p1; + acc_24_V_addr_46_reg_153068 <= zext_ln1265_6_fu_121003_p1; + acc_25_V_addr_46_reg_153074 <= zext_ln1265_6_fu_121003_p1; + acc_26_V_addr_46_reg_153080 <= zext_ln1265_6_fu_121003_p1; + acc_27_V_addr_46_reg_153086 <= zext_ln1265_6_fu_121003_p1; + acc_28_V_addr_46_reg_153092 <= zext_ln1265_6_fu_121003_p1; + acc_29_V_addr_46_reg_153098 <= zext_ln1265_6_fu_121003_p1; + acc_2_V_addr_46_reg_152936 <= zext_ln1265_6_fu_121003_p1; + acc_30_V_addr_46_reg_153104 <= zext_ln1265_6_fu_121003_p1; + acc_31_V_addr_46_reg_153110 <= zext_ln1265_6_fu_121003_p1; + acc_32_V_addr_46_reg_153116 <= zext_ln1265_6_fu_121003_p1; + acc_33_V_addr_46_reg_153122 <= zext_ln1265_6_fu_121003_p1; + acc_34_V_addr_46_reg_153128 <= zext_ln1265_6_fu_121003_p1; + acc_35_V_addr_46_reg_153134 <= zext_ln1265_6_fu_121003_p1; + acc_36_V_addr_46_reg_153140 <= zext_ln1265_6_fu_121003_p1; + acc_37_V_addr_46_reg_153146 <= zext_ln1265_6_fu_121003_p1; + acc_38_V_addr_46_reg_153152 <= zext_ln1265_6_fu_121003_p1; + acc_39_V_addr_46_reg_153158 <= zext_ln1265_6_fu_121003_p1; + acc_3_V_addr_46_reg_152942 <= zext_ln1265_6_fu_121003_p1; + acc_40_V_addr_46_reg_153164 <= zext_ln1265_6_fu_121003_p1; + acc_41_V_addr_46_reg_153170 <= zext_ln1265_6_fu_121003_p1; + acc_42_V_addr_46_reg_153176 <= zext_ln1265_6_fu_121003_p1; + acc_43_V_addr_46_reg_153182 <= zext_ln1265_6_fu_121003_p1; + acc_44_V_addr_46_reg_153188 <= zext_ln1265_6_fu_121003_p1; + acc_45_V_addr_46_reg_153194 <= zext_ln1265_6_fu_121003_p1; + acc_46_V_addr_46_reg_153200 <= zext_ln1265_6_fu_121003_p1; + acc_47_V_addr_46_reg_153206 <= zext_ln1265_6_fu_121003_p1; + acc_48_V_addr_45_reg_153212 <= zext_ln1265_6_fu_121003_p1; + acc_49_V_addr_45_reg_153218 <= zext_ln1265_6_fu_121003_p1; + acc_4_V_addr_46_reg_152948 <= zext_ln1265_6_fu_121003_p1; + acc_50_V_addr_45_reg_153224 <= zext_ln1265_6_fu_121003_p1; + acc_51_V_addr_45_reg_153230 <= zext_ln1265_6_fu_121003_p1; + acc_52_V_addr_45_reg_153236 <= zext_ln1265_6_fu_121003_p1; + acc_53_V_addr_45_reg_153242 <= zext_ln1265_6_fu_121003_p1; + acc_54_V_addr_45_reg_153248 <= zext_ln1265_6_fu_121003_p1; + acc_55_V_addr_45_reg_153254 <= zext_ln1265_6_fu_121003_p1; + acc_56_V_addr_45_reg_153260 <= zext_ln1265_6_fu_121003_p1; + acc_57_V_addr_45_reg_153266 <= zext_ln1265_6_fu_121003_p1; + acc_58_V_addr_45_reg_153272 <= zext_ln1265_6_fu_121003_p1; + acc_59_V_addr_45_reg_153278 <= zext_ln1265_6_fu_121003_p1; + acc_5_V_addr_46_reg_152954 <= zext_ln1265_6_fu_121003_p1; + acc_60_V_addr_45_reg_153284 <= zext_ln1265_6_fu_121003_p1; + acc_61_V_addr_45_reg_153290 <= zext_ln1265_6_fu_121003_p1; + acc_62_V_addr_45_reg_153296 <= zext_ln1265_6_fu_121003_p1; + acc_63_V_addr_45_reg_153302 <= zext_ln1265_6_fu_121003_p1; + acc_6_V_addr_46_reg_152960 <= zext_ln1265_6_fu_121003_p1; + acc_7_V_addr_46_reg_152966 <= zext_ln1265_6_fu_121003_p1; + acc_8_V_addr_46_reg_152972 <= zext_ln1265_6_fu_121003_p1; + acc_9_V_addr_46_reg_152978 <= zext_ln1265_6_fu_121003_p1; + add_ln1265_6_reg_152920[5 : 1] <= add_ln1265_6_fu_120984_p2[5 : 1]; + add_ln276_20_reg_153308 <= grp_fu_131481_p3; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_0_V_addr_48_reg_146075 <= zext_ln203_17_fu_116041_p1; + acc_10_V_addr_48_reg_146100 <= zext_ln203_17_fu_116041_p1; + acc_12_V_addr_48_reg_146105 <= zext_ln203_17_fu_116041_p1; + acc_14_V_addr_48_reg_146110 <= zext_ln203_17_fu_116041_p1; + acc_16_V_addr_48_reg_146115 <= zext_ln203_17_fu_116041_p1; + acc_18_V_addr_48_reg_146120 <= zext_ln203_17_fu_116041_p1; + acc_20_V_addr_48_reg_146125 <= zext_ln203_17_fu_116041_p1; + acc_22_V_addr_48_reg_146130 <= zext_ln203_17_fu_116041_p1; + acc_24_V_addr_48_reg_146135 <= zext_ln203_17_fu_116041_p1; + acc_26_V_addr_48_reg_146140 <= zext_ln203_17_fu_116041_p1; + acc_28_V_addr_48_reg_146145 <= zext_ln203_17_fu_116041_p1; + acc_2_V_addr_48_reg_146080 <= zext_ln203_17_fu_116041_p1; + acc_30_V_addr_48_reg_146150 <= zext_ln203_17_fu_116041_p1; + acc_32_V_addr_48_reg_146155 <= zext_ln203_17_fu_116041_p1; + acc_34_V_addr_48_reg_146160 <= zext_ln203_17_fu_116041_p1; + acc_36_V_addr_48_reg_146165 <= zext_ln203_17_fu_116041_p1; + acc_38_V_addr_48_reg_146170 <= zext_ln203_17_fu_116041_p1; + acc_40_V_addr_48_reg_146175 <= zext_ln203_17_fu_116041_p1; + acc_42_V_addr_48_reg_146180 <= zext_ln203_17_fu_116041_p1; + acc_44_V_addr_48_reg_146185 <= zext_ln203_17_fu_116041_p1; + acc_46_V_addr_48_reg_146190 <= zext_ln203_17_fu_116041_p1; + acc_48_V_addr_47_reg_146195 <= zext_ln203_17_fu_116041_p1; + acc_4_V_addr_48_reg_146085 <= zext_ln203_17_fu_116041_p1; + acc_50_V_addr_47_reg_146200 <= zext_ln203_17_fu_116041_p1; + acc_52_V_addr_47_reg_146205 <= zext_ln203_17_fu_116041_p1; + acc_54_V_addr_47_reg_146210 <= zext_ln203_17_fu_116041_p1; + acc_56_V_addr_47_reg_146215 <= zext_ln203_17_fu_116041_p1; + acc_58_V_addr_47_reg_146220 <= zext_ln203_17_fu_116041_p1; + acc_60_V_addr_47_reg_146225 <= zext_ln203_17_fu_116041_p1; + acc_62_V_addr_47_reg_146230 <= zext_ln203_17_fu_116041_p1; + acc_63_V_addr_47_reg_146235 <= zext_ln203_17_fu_116041_p1; + acc_6_V_addr_48_reg_146090 <= zext_ln203_17_fu_116041_p1; + acc_8_V_addr_48_reg_146095 <= zext_ln203_17_fu_116041_p1; + add_ln203_7_reg_146071[5 : 1] <= add_ln203_7_fu_116022_p2[5 : 1]; + phi_ln203_4_reg_146034 <= phi_ln203_4_fu_115953_p18; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln264_4_fu_127994_p2 == 1'd1) & (ap_ST_fsm_state4416 == ap_CS_fsm))) begin + acc_0_V_addr_49_reg_162765 <= zext_ln1265_7_fu_128045_p1; + acc_10_V_addr_49_reg_162825 <= zext_ln1265_7_fu_128045_p1; + acc_11_V_addr_48_reg_162831 <= zext_ln1265_7_fu_128045_p1; + acc_12_V_addr_49_reg_162837 <= zext_ln1265_7_fu_128045_p1; + acc_13_V_addr_48_reg_162843 <= zext_ln1265_7_fu_128045_p1; + acc_14_V_addr_49_reg_162849 <= zext_ln1265_7_fu_128045_p1; + acc_15_V_addr_48_reg_162855 <= zext_ln1265_7_fu_128045_p1; + acc_16_V_addr_49_reg_162861 <= zext_ln1265_7_fu_128045_p1; + acc_17_V_addr_48_reg_162867 <= zext_ln1265_7_fu_128045_p1; + acc_18_V_addr_49_reg_162873 <= zext_ln1265_7_fu_128045_p1; + acc_19_V_addr_48_reg_162879 <= zext_ln1265_7_fu_128045_p1; + acc_1_V_addr_48_reg_162771 <= zext_ln1265_7_fu_128045_p1; + acc_20_V_addr_49_reg_162885 <= zext_ln1265_7_fu_128045_p1; + acc_21_V_addr_48_reg_162891 <= zext_ln1265_7_fu_128045_p1; + acc_22_V_addr_49_reg_162897 <= zext_ln1265_7_fu_128045_p1; + acc_23_V_addr_48_reg_162903 <= zext_ln1265_7_fu_128045_p1; + acc_24_V_addr_49_reg_162909 <= zext_ln1265_7_fu_128045_p1; + acc_25_V_addr_48_reg_162915 <= zext_ln1265_7_fu_128045_p1; + acc_26_V_addr_49_reg_162921 <= zext_ln1265_7_fu_128045_p1; + acc_27_V_addr_48_reg_162927 <= zext_ln1265_7_fu_128045_p1; + acc_28_V_addr_49_reg_162933 <= zext_ln1265_7_fu_128045_p1; + acc_29_V_addr_48_reg_162939 <= zext_ln1265_7_fu_128045_p1; + acc_2_V_addr_49_reg_162777 <= zext_ln1265_7_fu_128045_p1; + acc_30_V_addr_49_reg_162945 <= zext_ln1265_7_fu_128045_p1; + acc_31_V_addr_48_reg_162951 <= zext_ln1265_7_fu_128045_p1; + acc_32_V_addr_49_reg_162957 <= zext_ln1265_7_fu_128045_p1; + acc_33_V_addr_48_reg_162963 <= zext_ln1265_7_fu_128045_p1; + acc_34_V_addr_49_reg_162969 <= zext_ln1265_7_fu_128045_p1; + acc_35_V_addr_48_reg_162975 <= zext_ln1265_7_fu_128045_p1; + acc_36_V_addr_49_reg_162981 <= zext_ln1265_7_fu_128045_p1; + acc_37_V_addr_48_reg_162987 <= zext_ln1265_7_fu_128045_p1; + acc_38_V_addr_49_reg_162993 <= zext_ln1265_7_fu_128045_p1; + acc_39_V_addr_48_reg_162999 <= zext_ln1265_7_fu_128045_p1; + acc_3_V_addr_48_reg_162783 <= zext_ln1265_7_fu_128045_p1; + acc_40_V_addr_49_reg_163005 <= zext_ln1265_7_fu_128045_p1; + acc_41_V_addr_48_reg_163011 <= zext_ln1265_7_fu_128045_p1; + acc_42_V_addr_49_reg_163017 <= zext_ln1265_7_fu_128045_p1; + acc_43_V_addr_48_reg_163023 <= zext_ln1265_7_fu_128045_p1; + acc_44_V_addr_49_reg_163029 <= zext_ln1265_7_fu_128045_p1; + acc_45_V_addr_48_reg_163035 <= zext_ln1265_7_fu_128045_p1; + acc_46_V_addr_49_reg_163041 <= zext_ln1265_7_fu_128045_p1; + acc_47_V_addr_48_reg_163047 <= zext_ln1265_7_fu_128045_p1; + acc_48_V_addr_48_reg_163053 <= zext_ln1265_7_fu_128045_p1; + acc_49_V_addr_47_reg_163059 <= zext_ln1265_7_fu_128045_p1; + acc_4_V_addr_49_reg_162789 <= zext_ln1265_7_fu_128045_p1; + acc_50_V_addr_48_reg_163065 <= zext_ln1265_7_fu_128045_p1; + acc_51_V_addr_47_reg_163071 <= zext_ln1265_7_fu_128045_p1; + acc_52_V_addr_48_reg_163077 <= zext_ln1265_7_fu_128045_p1; + acc_53_V_addr_47_reg_163083 <= zext_ln1265_7_fu_128045_p1; + acc_54_V_addr_48_reg_163089 <= zext_ln1265_7_fu_128045_p1; + acc_55_V_addr_47_reg_163095 <= zext_ln1265_7_fu_128045_p1; + acc_56_V_addr_48_reg_163101 <= zext_ln1265_7_fu_128045_p1; + acc_57_V_addr_47_reg_163107 <= zext_ln1265_7_fu_128045_p1; + acc_58_V_addr_48_reg_163113 <= zext_ln1265_7_fu_128045_p1; + acc_59_V_addr_47_reg_163119 <= zext_ln1265_7_fu_128045_p1; + acc_5_V_addr_48_reg_162795 <= zext_ln1265_7_fu_128045_p1; + acc_60_V_addr_48_reg_163125 <= zext_ln1265_7_fu_128045_p1; + acc_61_V_addr_47_reg_163131 <= zext_ln1265_7_fu_128045_p1; + acc_62_V_addr_48_reg_163137 <= zext_ln1265_7_fu_128045_p1; + acc_63_V_addr_48_reg_163143 <= zext_ln1265_7_fu_128045_p1; + acc_6_V_addr_49_reg_162801 <= zext_ln1265_7_fu_128045_p1; + acc_7_V_addr_48_reg_162807 <= zext_ln1265_7_fu_128045_p1; + acc_8_V_addr_49_reg_162813 <= zext_ln1265_7_fu_128045_p1; + acc_9_V_addr_48_reg_162819 <= zext_ln1265_7_fu_128045_p1; + add_ln1265_7_reg_162761[5 : 1] <= add_ln1265_7_fu_128026_p2[5 : 1]; + add_ln276_27_reg_163149 <= grp_fu_131587_p3; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_0_V_addr_50_reg_146546 <= zext_ln203_22_fu_116805_p1; + acc_10_V_addr_50_reg_146571 <= zext_ln203_22_fu_116805_p1; + acc_12_V_addr_50_reg_146576 <= zext_ln203_22_fu_116805_p1; + acc_14_V_addr_50_reg_146581 <= zext_ln203_22_fu_116805_p1; + acc_16_V_addr_50_reg_146586 <= zext_ln203_22_fu_116805_p1; + acc_18_V_addr_50_reg_146591 <= zext_ln203_22_fu_116805_p1; + acc_20_V_addr_50_reg_146596 <= zext_ln203_22_fu_116805_p1; + acc_22_V_addr_50_reg_146601 <= zext_ln203_22_fu_116805_p1; + acc_24_V_addr_50_reg_146606 <= zext_ln203_22_fu_116805_p1; + acc_26_V_addr_50_reg_146611 <= zext_ln203_22_fu_116805_p1; + acc_28_V_addr_50_reg_146616 <= zext_ln203_22_fu_116805_p1; + acc_2_V_addr_50_reg_146551 <= zext_ln203_22_fu_116805_p1; + acc_30_V_addr_50_reg_146621 <= zext_ln203_22_fu_116805_p1; + acc_32_V_addr_50_reg_146626 <= zext_ln203_22_fu_116805_p1; + acc_34_V_addr_50_reg_146631 <= zext_ln203_22_fu_116805_p1; + acc_36_V_addr_50_reg_146636 <= zext_ln203_22_fu_116805_p1; + acc_38_V_addr_50_reg_146641 <= zext_ln203_22_fu_116805_p1; + acc_40_V_addr_50_reg_146646 <= zext_ln203_22_fu_116805_p1; + acc_42_V_addr_50_reg_146651 <= zext_ln203_22_fu_116805_p1; + acc_44_V_addr_50_reg_146656 <= zext_ln203_22_fu_116805_p1; + acc_46_V_addr_50_reg_146661 <= zext_ln203_22_fu_116805_p1; + acc_48_V_addr_49_reg_146666 <= zext_ln203_22_fu_116805_p1; + acc_4_V_addr_50_reg_146556 <= zext_ln203_22_fu_116805_p1; + acc_50_V_addr_49_reg_146671 <= zext_ln203_22_fu_116805_p1; + acc_52_V_addr_49_reg_146676 <= zext_ln203_22_fu_116805_p1; + acc_54_V_addr_49_reg_146681 <= zext_ln203_22_fu_116805_p1; + acc_56_V_addr_49_reg_146686 <= zext_ln203_22_fu_116805_p1; + acc_58_V_addr_49_reg_146691 <= zext_ln203_22_fu_116805_p1; + acc_60_V_addr_49_reg_146696 <= zext_ln203_22_fu_116805_p1; + acc_62_V_addr_49_reg_146701 <= zext_ln203_22_fu_116805_p1; + acc_63_V_addr_49_reg_146706 <= zext_ln203_22_fu_116805_p1; + acc_6_V_addr_50_reg_146561 <= zext_ln203_22_fu_116805_p1; + acc_8_V_addr_50_reg_146566 <= zext_ln203_22_fu_116805_p1; + add_ln203_9_reg_146542[5 : 1] <= add_ln203_9_fu_116786_p2[5 : 1]; + phi_ln203_5_reg_146505 <= phi_ln203_5_fu_116717_p18; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_0_V_addr_51_reg_146297 <= zext_ln203_24_fu_116374_p1; + acc_10_V_addr_51_reg_146322 <= zext_ln203_24_fu_116374_p1; + acc_12_V_addr_51_reg_146327 <= zext_ln203_24_fu_116374_p1; + acc_14_V_addr_51_reg_146332 <= zext_ln203_24_fu_116374_p1; + acc_16_V_addr_51_reg_146337 <= zext_ln203_24_fu_116374_p1; + acc_18_V_addr_51_reg_146342 <= zext_ln203_24_fu_116374_p1; + acc_20_V_addr_51_reg_146347 <= zext_ln203_24_fu_116374_p1; + acc_22_V_addr_51_reg_146352 <= zext_ln203_24_fu_116374_p1; + acc_24_V_addr_51_reg_146357 <= zext_ln203_24_fu_116374_p1; + acc_26_V_addr_51_reg_146362 <= zext_ln203_24_fu_116374_p1; + acc_28_V_addr_51_reg_146367 <= zext_ln203_24_fu_116374_p1; + acc_2_V_addr_51_reg_146302 <= zext_ln203_24_fu_116374_p1; + acc_30_V_addr_51_reg_146372 <= zext_ln203_24_fu_116374_p1; + acc_32_V_addr_51_reg_146377 <= zext_ln203_24_fu_116374_p1; + acc_34_V_addr_51_reg_146382 <= zext_ln203_24_fu_116374_p1; + acc_36_V_addr_51_reg_146387 <= zext_ln203_24_fu_116374_p1; + acc_38_V_addr_51_reg_146392 <= zext_ln203_24_fu_116374_p1; + acc_40_V_addr_51_reg_146397 <= zext_ln203_24_fu_116374_p1; + acc_42_V_addr_51_reg_146402 <= zext_ln203_24_fu_116374_p1; + acc_44_V_addr_51_reg_146407 <= zext_ln203_24_fu_116374_p1; + acc_46_V_addr_51_reg_146412 <= zext_ln203_24_fu_116374_p1; + acc_48_V_addr_50_reg_146417 <= zext_ln203_24_fu_116374_p1; + acc_4_V_addr_51_reg_146307 <= zext_ln203_24_fu_116374_p1; + acc_50_V_addr_50_reg_146422 <= zext_ln203_24_fu_116374_p1; + acc_52_V_addr_50_reg_146427 <= zext_ln203_24_fu_116374_p1; + acc_54_V_addr_50_reg_146432 <= zext_ln203_24_fu_116374_p1; + acc_56_V_addr_50_reg_146437 <= zext_ln203_24_fu_116374_p1; + acc_58_V_addr_50_reg_146442 <= zext_ln203_24_fu_116374_p1; + acc_60_V_addr_50_reg_146447 <= zext_ln203_24_fu_116374_p1; + acc_62_V_addr_50_reg_146452 <= zext_ln203_24_fu_116374_p1; + acc_63_V_addr_50_reg_146457 <= zext_ln203_24_fu_116374_p1; + acc_6_V_addr_51_reg_146312 <= zext_ln203_24_fu_116374_p1; + acc_8_V_addr_51_reg_146317 <= zext_ln203_24_fu_116374_p1; + add_ln203_10_reg_146293[5 : 1] <= add_ln203_10_fu_116355_p2[5 : 1]; + phi_ln203_6_reg_146256 <= phi_ln203_6_fu_116286_p18; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_0_V_addr_52_reg_146768 <= zext_ln203_28_fu_117138_p1; + acc_10_V_addr_52_reg_146793 <= zext_ln203_28_fu_117138_p1; + acc_12_V_addr_52_reg_146798 <= zext_ln203_28_fu_117138_p1; + acc_14_V_addr_52_reg_146803 <= zext_ln203_28_fu_117138_p1; + acc_16_V_addr_52_reg_146808 <= zext_ln203_28_fu_117138_p1; + acc_18_V_addr_52_reg_146813 <= zext_ln203_28_fu_117138_p1; + acc_20_V_addr_52_reg_146818 <= zext_ln203_28_fu_117138_p1; + acc_22_V_addr_52_reg_146823 <= zext_ln203_28_fu_117138_p1; + acc_24_V_addr_52_reg_146828 <= zext_ln203_28_fu_117138_p1; + acc_26_V_addr_52_reg_146833 <= zext_ln203_28_fu_117138_p1; + acc_28_V_addr_52_reg_146838 <= zext_ln203_28_fu_117138_p1; + acc_2_V_addr_52_reg_146773 <= zext_ln203_28_fu_117138_p1; + acc_30_V_addr_52_reg_146843 <= zext_ln203_28_fu_117138_p1; + acc_32_V_addr_52_reg_146848 <= zext_ln203_28_fu_117138_p1; + acc_34_V_addr_52_reg_146853 <= zext_ln203_28_fu_117138_p1; + acc_36_V_addr_52_reg_146858 <= zext_ln203_28_fu_117138_p1; + acc_38_V_addr_52_reg_146863 <= zext_ln203_28_fu_117138_p1; + acc_40_V_addr_52_reg_146868 <= zext_ln203_28_fu_117138_p1; + acc_42_V_addr_52_reg_146873 <= zext_ln203_28_fu_117138_p1; + acc_44_V_addr_52_reg_146878 <= zext_ln203_28_fu_117138_p1; + acc_46_V_addr_52_reg_146883 <= zext_ln203_28_fu_117138_p1; + acc_48_V_addr_51_reg_146888 <= zext_ln203_28_fu_117138_p1; + acc_4_V_addr_52_reg_146778 <= zext_ln203_28_fu_117138_p1; + acc_50_V_addr_51_reg_146893 <= zext_ln203_28_fu_117138_p1; + acc_52_V_addr_51_reg_146898 <= zext_ln203_28_fu_117138_p1; + acc_54_V_addr_51_reg_146903 <= zext_ln203_28_fu_117138_p1; + acc_56_V_addr_51_reg_146908 <= zext_ln203_28_fu_117138_p1; + acc_58_V_addr_51_reg_146913 <= zext_ln203_28_fu_117138_p1; + acc_60_V_addr_51_reg_146918 <= zext_ln203_28_fu_117138_p1; + acc_62_V_addr_51_reg_146923 <= zext_ln203_28_fu_117138_p1; + acc_63_V_addr_51_reg_146928 <= zext_ln203_28_fu_117138_p1; + acc_6_V_addr_52_reg_146783 <= zext_ln203_28_fu_117138_p1; + acc_8_V_addr_52_reg_146788 <= zext_ln203_28_fu_117138_p1; + add_ln203_11_reg_146764[5 : 1] <= add_ln203_11_fu_117119_p2[5 : 1]; + phi_ln203_7_reg_146727 <= phi_ln203_7_fu_117050_p18; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_11_reg_139731 == 1'd0) & (or_ln223_21_fu_110053_p2 == 1'd0) & (ap_ST_fsm_state1371 == ap_CS_fsm))) begin + add_ln1116_10_reg_139883 <= add_ln1116_10_fu_110090_p2; + zext_ln232_10_reg_139878[31 : 0] <= zext_ln232_10_fu_110086_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state765 == ap_CS_fsm) & (or_ln223_13_reg_136251 == 1'd0) & (or_ln223_22_fu_106609_p2 == 1'd0))) begin + add_ln1116_11_reg_136276 <= add_ln1116_11_fu_106645_p2; + zext_ln232_11_reg_136271[31 : 0] <= zext_ln232_11_fu_106641_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_24_fu_110850_p2 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1524 == ap_CS_fsm))) begin + add_ln1116_12_reg_140743[6 : 1] <= add_ln1116_12_fu_110887_p2[6 : 1]; + zext_ln232_12_reg_140738[31 : 0] <= zext_ln232_12_fu_110883_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state918 == ap_CS_fsm) & (or_ln223_25_fu_107413_p2 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0))) begin + add_ln1116_13_reg_137141[6 : 1] <= add_ln1116_13_fu_107449_p2[6 : 1]; + zext_ln232_13_reg_137136[31 : 0] <= zext_ln232_13_fu_107445_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state1975 == ap_CS_fsm) & (or_ln223_19_reg_143411 == 1'd0) & (or_ln223_26_fu_113452_p2 == 1'd0))) begin + add_ln1116_14_reg_143436 <= add_ln1116_14_fu_113488_p2; + zext_ln232_14_reg_143431[31 : 0] <= zext_ln232_14_fu_113484_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2128 == ap_CS_fsm) & (or_ln223_27_fu_114247_p2 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0))) begin + add_ln1116_15_reg_144296[6 : 1] <= add_ln1116_15_fu_114283_p2[6 : 1]; + zext_ln232_15_reg_144291[31 : 0] <= zext_ln232_15_fu_114279_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state199 == ap_CS_fsm) & (or_ln223_28_fu_103484_p2 == 1'd0) & (icmp_ln208_4_fu_103406_p2 == 1'd0) & (or_ln223_8_reg_132680 == 1'd0))) begin + add_ln1116_16_reg_133103 <= add_ln1116_16_fu_103521_p2; + zext_ln232_16_reg_133098[31 : 0] <= zext_ln232_16_fu_103517_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state350 == ap_CS_fsm) & (or_ln223_30_fu_104288_p2 == 1'd0) & (icmp_ln208_5_fu_104210_p2 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0))) begin + add_ln1116_17_reg_133975[6 : 1] <= add_ln1116_17_fu_104325_p2[6 : 1]; + zext_ln232_17_reg_133970[31 : 0] <= zext_ln232_17_fu_104321_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_31_fu_110345_p2 == 1'd0) & (icmp_ln208_6_fu_110267_p2 == 1'd0) & (or_ln223_11_reg_139731 == 1'd0) & (ap_ST_fsm_state1410 == ap_CS_fsm))) begin + add_ln1116_18_reg_140281 <= add_ln1116_18_fu_110382_p2; + zext_ln232_18_reg_140276[31 : 0] <= zext_ln232_18_fu_110378_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) & (or_ln223_32_fu_106900_p2 == 1'd0) & (icmp_ln208_7_fu_106822_p2 == 1'd0) & (or_ln223_13_reg_136251 == 1'd0))) begin + add_ln1116_19_reg_136674 <= add_ln1116_19_fu_106936_p2; + zext_ln232_19_reg_136669[31 : 0] <= zext_ln232_19_fu_106932_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_5_fu_109171_p2 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1220 == ap_CS_fsm))) begin + add_ln1116_1_reg_138989 <= add_ln1116_1_fu_109208_p2; + zext_ln232_1_reg_138984[31 : 0] <= zext_ln232_1_fu_109204_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_34_fu_111140_p2 == 1'd0) & (icmp_ln208_8_fu_111062_p2 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm))) begin + add_ln1116_20_reg_141148[6 : 1] <= add_ln1116_20_fu_111177_p2[6 : 1]; + zext_ln232_20_reg_141143[31 : 0] <= zext_ln232_20_fu_111173_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) & (or_ln223_36_fu_107702_p2 == 1'd0) & (icmp_ln208_9_fu_107624_p2 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0))) begin + add_ln1116_21_reg_137546[6 : 1] <= add_ln1116_21_fu_107738_p2[6 : 1]; + zext_ln232_21_reg_137541[31 : 0] <= zext_ln232_21_fu_107734_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state463 == ap_CS_fsm) & (or_ln223_37_fu_104801_p2 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0))) begin + add_ln1116_22_reg_134445[6 : 1] <= add_ln1116_22_fu_104838_p2[6 : 1]; + zext_ln232_22_reg_134440[31 : 0] <= zext_ln232_22_fu_104834_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2014 == ap_CS_fsm) & (or_ln223_38_fu_113743_p2 == 1'd0) & (icmp_ln208_10_fu_113665_p2 == 1'd0) & (or_ln223_19_reg_143411 == 1'd0))) begin + add_ln1116_23_reg_143834 <= add_ln1116_23_fu_113779_p2; + zext_ln232_23_reg_143829[31 : 0] <= zext_ln232_23_fu_113775_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_40_fu_114536_p2 == 1'd0) & (icmp_ln208_11_fu_114458_p2 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0))) begin + add_ln1116_24_reg_144701[6 : 1] <= add_ln1116_24_fu_114572_p2[6 : 1]; + zext_ln232_24_reg_144696[31 : 0] <= zext_ln232_24_fu_114568_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_41_fu_111655_p2 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + add_ln1116_25_reg_141608[6 : 1] <= add_ln1116_25_fu_111692_p2[6 : 1]; + zext_ln232_25_reg_141603[31 : 0] <= zext_ln232_25_fu_111688_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_42_fu_108214_p2 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + add_ln1116_26_reg_138016[6 : 1] <= add_ln1116_26_fu_108250_p2[6 : 1]; + zext_ln232_26_reg_138011[31 : 0] <= zext_ln232_26_fu_108246_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2278 == ap_CS_fsm) & (or_ln223_43_fu_115048_p2 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0))) begin + add_ln1116_27_reg_145171[6 : 1] <= add_ln1116_27_fu_115084_p2[6 : 1]; + zext_ln232_27_reg_145166[31 : 0] <= zext_ln232_27_fu_115080_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state500 == ap_CS_fsm) & (or_ln223_44_fu_105091_p2 == 1'd0) & (icmp_ln208_12_fu_105013_p2 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0))) begin + add_ln1116_28_reg_134850[6 : 1] <= add_ln1116_28_fu_105128_p2[6 : 1]; + zext_ln232_28_reg_134845[31 : 0] <= zext_ln232_28_fu_105124_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_45_fu_111945_p2 == 1'd0) & (icmp_ln208_13_fu_111867_p2 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm))) begin + add_ln1116_29_reg_142013[6 : 1] <= add_ln1116_29_fu_111982_p2[6 : 1]; + zext_ln232_29_reg_142008[31 : 0] <= zext_ln232_29_fu_111978_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state614 == ap_CS_fsm) & (or_ln223_6_fu_105731_p2 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0))) begin + add_ln1116_2_reg_135368 <= add_ln1116_2_fu_105767_p2; + zext_ln232_2_reg_135363[31 : 0] <= zext_ln232_2_fu_105763_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_46_fu_108503_p2 == 1'd0) & (icmp_ln208_14_fu_108425_p2 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm))) begin + add_ln1116_30_reg_138421[6 : 1] <= add_ln1116_30_fu_108539_p2[6 : 1]; + zext_ln232_30_reg_138416[31 : 0] <= zext_ln232_30_fu_108535_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_47_fu_115337_p2 == 1'd0) & (icmp_ln208_15_fu_115259_p2 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0))) begin + add_ln1116_31_reg_145576[6 : 1] <= add_ln1116_31_fu_115373_p2[6 : 1]; + zext_ln232_31_reg_145571[31 : 0] <= zext_ln232_31_fu_115369_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state1825 == ap_CS_fsm) & (or_ln223_7_fu_112574_p2 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0))) begin + add_ln1116_3_reg_142532 <= add_ln1116_3_fu_112610_p2; + zext_ln232_3_reg_142527[31 : 0] <= zext_ln232_3_fu_112606_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_reg_131762 == 1'd0) & (ap_ST_fsm_state47 == ap_CS_fsm) & (or_ln223_9_fu_102602_p2 == 1'd0) & (icmp_ln208_fu_102524_p2 == 1'd0))) begin + add_ln1116_4_reg_132207 <= add_ln1116_4_fu_102639_p2; + zext_ln232_4_reg_132202[31 : 0] <= zext_ln232_4_fu_102635_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_12_fu_109462_p2 == 1'd0) & (icmp_ln208_1_fu_109384_p2 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm))) begin + add_ln1116_5_reg_139399 <= add_ln1116_5_fu_109499_p2; + zext_ln232_5_reg_139394[31 : 0] <= zext_ln232_5_fu_109495_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state652 == ap_CS_fsm) & (or_ln223_14_fu_106021_p2 == 1'd0) & (icmp_ln208_2_fu_105943_p2 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0))) begin + add_ln1116_6_reg_135778 <= add_ln1116_6_fu_106057_p2; + zext_ln232_6_reg_135773[31 : 0] <= zext_ln232_6_fu_106053_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state160 == ap_CS_fsm) & (or_ln223_8_reg_132680 == 1'd0) & (or_ln223_15_fu_103192_p2 == 1'd0))) begin + add_ln1116_7_reg_132705 <= add_ln1116_7_fu_103229_p2; + zext_ln232_7_reg_132700[31 : 0] <= zext_ln232_7_fu_103225_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state313 == ap_CS_fsm) & (or_ln223_18_fu_103998_p2 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0))) begin + add_ln1116_8_reg_133570[6 : 1] <= add_ln1116_8_fu_104035_p2[6 : 1]; + zext_ln232_8_reg_133565[31 : 0] <= zext_ln232_8_fu_104031_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_20_fu_112864_p2 == 1'd0) & (icmp_ln208_3_fu_112786_p2 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0))) begin + add_ln1116_9_reg_142942 <= add_ln1116_9_fu_112900_p2; + zext_ln232_9_reg_142937[31 : 0] <= zext_ln232_9_fu_112896_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_reg_131762 == 1'd0) & (or_ln223_3_fu_102310_p2 == 1'd0) & (ap_ST_fsm_state8 == ap_CS_fsm))) begin + add_ln1116_reg_131809 <= add_ln1116_fu_102347_p2; + zext_ln232_reg_131804[31 : 0] <= zext_ln232_fu_102343_p1[31 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + add_ln203_12_reg_131677 <= add_ln203_12_fu_101978_p2; + add_ln203_reg_131691 <= add_ln203_fu_101994_p2; + zext_ln203_4_reg_131682[3 : 0] <= zext_ln203_4_fu_101984_p1[3 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1216 == ap_CS_fsm)) begin + add_ln203_13_reg_138856 <= add_ln203_13_fu_108850_p2; + add_ln203_1_reg_138870 <= add_ln203_1_fu_108866_p2; + zext_ln203_9_reg_138861[3 : 0] <= zext_ln203_9_fu_108856_p1[3 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state610 == ap_CS_fsm)) begin + add_ln203_14_reg_135260 <= add_ln203_14_fu_105413_p2; + add_ln203_2_reg_135274 <= add_ln203_2_fu_105429_p2; + zext_ln203_14_reg_135265[3 : 0] <= zext_ln203_14_fu_105419_p1[3 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1821 == ap_CS_fsm)) begin + add_ln203_15_reg_142423 <= add_ln203_15_fu_112267_p2; + add_ln203_3_reg_142437 <= add_ln203_3_fu_112283_p2; + zext_ln203_23_reg_142428[3 : 0] <= zext_ln203_23_fu_112273_p1[3 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state465 == ap_CS_fsm)) begin + add_ln216_100_reg_134780 <= grp_fu_99092_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2278 == ap_CS_fsm) & ((or_ln223_43_fu_115048_p2 == 1'd1) | (or_ln223_39_reg_145146 == 1'd1)))) begin + add_ln216_101_reg_145495 <= grp_fu_99296_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + add_ln216_102_reg_141943 <= grp_fu_99228_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1070 == ap_CS_fsm)) begin + add_ln216_103_reg_138351 <= grp_fu_99160_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2280 == ap_CS_fsm)) begin + add_ln216_104_reg_145506 <= grp_fu_99296_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1219 == ap_CS_fsm)) begin + add_ln216_11_reg_138956 <= add_ln216_11_fu_109088_p2; + add_ln221_6_reg_138962 <= add_ln221_6_fu_109094_p2; + add_ln231_1_reg_138968 <= add_ln231_1_fu_109099_p2; + add_ln231_3_reg_138974 <= add_ln231_3_fu_109103_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state1821 == ap_CS_fsm) & (icmp_ln203_3_fu_112277_p2 == 1'd0))) begin + add_ln216_14_reg_142442 <= add_ln216_14_fu_112302_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state613 == ap_CS_fsm)) begin + add_ln216_16_reg_135335 <= add_ln216_16_fu_105643_p2; + add_ln221_9_reg_135341 <= add_ln221_9_fu_105649_p2; + add_ln231_4_reg_135347 <= add_ln231_4_fu_105654_p2; + or_ln231_s_reg_135353[2 : 0] <= or_ln231_s_fu_105658_p4[2 : 0]; +or_ln231_s_reg_135353[6 : 4] <= or_ln231_s_fu_105658_p4[6 : 4]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln203_fu_101988_p2 == 1'd0))) begin + add_ln216_1_reg_131696 <= add_ln216_1_fu_102013_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + add_ln216_22_reg_142499 <= add_ln216_22_fu_112491_p2; + add_ln221_12_reg_142505 <= add_ln221_12_fu_112497_p2; + add_ln231_7_reg_142511 <= add_ln231_7_fu_112502_p2; + add_ln231_9_reg_142517 <= add_ln231_9_fu_112506_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state47 == ap_CS_fsm) & (icmp_ln208_fu_102524_p2 == 1'd0))) begin + add_ln216_24_reg_132191 <= add_ln216_24_fu_102530_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_1_fu_109384_p2 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm))) begin + add_ln216_26_reg_139383 <= add_ln216_26_fu_109390_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state652 == ap_CS_fsm) & (icmp_ln208_2_fu_105943_p2 == 1'd0))) begin + add_ln216_27_reg_135762 <= add_ln216_27_fu_105949_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_fu_102524_p2 == 1'd1) & (ap_ST_fsm_state47 == ap_CS_fsm) & (icmp_ln206_fu_102733_p2 == 1'd0))) begin + add_ln216_29_reg_132549 <= add_ln216_29_fu_102823_p2; + add_ln221_17_reg_132555 <= add_ln221_17_fu_102829_p2; + icmp_ln223_63_reg_132539 <= icmp_ln223_63_fu_102778_p2; + icmp_ln223_64_reg_132544 <= icmp_ln223_64_fu_102794_p2; + trunc_ln231_23_reg_132561[6 : 3] <= trunc_ln231_23_fu_102834_p1[6 : 3]; + trunc_ln231_24_reg_132566[10 : 3] <= trunc_ln231_24_fu_102838_p1[10 : 3]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state312 == ap_CS_fsm)) begin + add_ln216_32_reg_133543 <= add_ln216_32_fu_103919_p2; + add_ln221_20_reg_133549 <= add_ln221_20_fu_103925_p2; + add_ln231_18_reg_133555[10 : 1] <= add_ln231_18_fu_103930_p2[10 : 1]; + or_ln223_10_reg_133539 <= or_ln223_10_fu_103910_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state1862 == ap_CS_fsm) & (icmp_ln208_3_fu_112786_p2 == 1'd0))) begin + add_ln216_36_reg_142926 <= add_ln216_36_fu_112792_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_1_fu_109384_p2 == 1'd1) & (icmp_ln206_1_fu_109593_p2 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm))) begin + add_ln216_37_reg_139735 <= add_ln216_37_fu_109689_p2; + add_ln221_23_reg_139741 <= add_ln221_23_fu_109695_p2; + or_ln223_11_reg_139731 <= or_ln223_11_fu_109660_p2; + trunc_ln231_26_reg_139747[6 : 4] <= trunc_ln231_26_fu_109700_p1[6 : 4]; + trunc_ln231_27_reg_139752[10 : 4] <= trunc_ln231_27_fu_109704_p1[10 : 4]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_2_fu_105943_p2 == 1'd1) & (ap_ST_fsm_state652 == ap_CS_fsm) & (icmp_ln206_2_fu_106151_p2 == 1'd0))) begin + add_ln216_41_reg_136120 <= add_ln216_41_fu_106241_p2; + add_ln221_25_reg_136126 <= add_ln221_25_fu_106247_p2; + icmp_ln223_73_reg_136110 <= icmp_ln223_73_fu_106196_p2; + icmp_ln223_74_reg_136115 <= icmp_ln223_74_fu_106212_p2; + trunc_ln231_28_reg_136132[6 : 3] <= trunc_ln231_28_fu_106252_p1[6 : 3]; + trunc_ln231_29_reg_136137[10 : 3] <= trunc_ln231_29_fu_106256_p1[10 : 3]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + add_ln216_44_reg_140710 <= add_ln216_44_fu_110767_p2; + add_ln221_28_reg_140716 <= add_ln221_28_fu_110773_p2; + add_ln231_27_reg_140722[10 : 1] <= add_ln231_27_fu_110778_p2[10 : 1]; + add_ln231_28_reg_140728[6 : 1] <= add_ln231_28_fu_110782_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state917 == ap_CS_fsm)) begin + add_ln216_47_reg_137114 <= add_ln216_47_fu_107334_p2; + add_ln221_31_reg_137120 <= add_ln221_31_fu_107340_p2; + add_ln231_31_reg_137126[10 : 1] <= add_ln231_31_fu_107345_p2[10 : 1]; + or_ln223_17_reg_137110 <= or_ln223_17_fu_107325_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state7 == ap_CS_fsm)) begin + add_ln216_4_reg_131776 <= add_ln216_4_fu_102222_p2; + add_ln221_3_reg_131782 <= add_ln221_3_fu_102228_p2; + add_ln231_reg_131788 <= add_ln231_fu_102233_p2; + or_ln231_8_reg_131794[2 : 0] <= or_ln231_8_fu_102237_p4[2 : 0]; +or_ln231_8_reg_131794[6 : 4] <= or_ln231_8_fu_102237_p4[6 : 4]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_3_fu_112786_p2 == 1'd1) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (icmp_ln206_3_fu_112994_p2 == 1'd0))) begin + add_ln216_51_reg_143284 <= add_ln216_51_fu_113084_p2; + add_ln221_33_reg_143290 <= add_ln221_33_fu_113090_p2; + icmp_ln223_85_reg_143274 <= icmp_ln223_85_fu_113039_p2; + icmp_ln223_86_reg_143279 <= icmp_ln223_86_fu_113055_p2; + trunc_ln231_33_reg_143296[6 : 4] <= trunc_ln231_33_fu_113095_p1[6 : 4]; + trunc_ln231_34_reg_143301[10 : 4] <= trunc_ln231_34_fu_113099_p1[10 : 4]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state1220 == ap_CS_fsm) & ((or_ln223_5_fu_109171_p2 == 1'd1) | (or_ln223_1_reg_138942 == 1'd1)))) begin + add_ln216_52_reg_139318 <= grp_fu_99177_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2127 == ap_CS_fsm)) begin + add_ln216_54_reg_144263 <= add_ln216_54_fu_114164_p2; + add_ln221_36_reg_144269 <= add_ln221_36_fu_114170_p2; + add_ln231_40_reg_144275[10 : 1] <= add_ln231_40_fu_114175_p2[10 : 1]; + add_ln231_42_reg_144281[6 : 1] <= add_ln231_42_fu_114179_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state614 == ap_CS_fsm) & ((or_ln223_6_fu_105731_p2 == 1'd1) | (or_ln223_2_reg_135321 == 1'd1)))) begin + add_ln216_55_reg_135697 <= grp_fu_99109_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state199 == ap_CS_fsm) & (icmp_ln208_4_fu_103406_p2 == 1'd0))) begin + add_ln216_56_reg_133087 <= add_ln216_56_fu_103412_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state350 == ap_CS_fsm) & (icmp_ln208_5_fu_104210_p2 == 1'd0))) begin + add_ln216_57_reg_133959 <= add_ln216_57_fu_104216_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_6_fu_110267_p2 == 1'd0) & (ap_ST_fsm_state1410 == ap_CS_fsm))) begin + add_ln216_58_reg_140265 <= add_ln216_58_fu_110273_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) & (icmp_ln208_7_fu_106822_p2 == 1'd0))) begin + add_ln216_59_reg_136658 <= add_ln216_59_fu_106828_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_8_fu_111062_p2 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm))) begin + add_ln216_61_reg_141132 <= add_ln216_61_fu_111068_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) & (icmp_ln208_9_fu_107624_p2 == 1'd0))) begin + add_ln216_62_reg_137530 <= add_ln216_62_fu_107630_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_5_fu_104210_p2 == 1'd1) & (ap_ST_fsm_state350 == ap_CS_fsm) & (icmp_ln206_4_fu_104418_p2 == 1'd0))) begin + add_ln216_63_reg_134312 <= add_ln216_63_fu_104508_p2; + add_ln221_44_reg_134318 <= add_ln221_44_fu_104514_p2; + icmp_ln223_105_reg_134302 <= icmp_ln223_105_fu_104463_p2; + icmp_ln223_106_reg_134307 <= icmp_ln223_106_fu_104479_p2; + trunc_ln231_37_reg_134324[6 : 3] <= trunc_ln231_37_fu_104519_p1[6 : 3]; + trunc_ln231_38_reg_134329[10 : 3] <= trunc_ln231_38_fu_104523_p1[10 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2014 == ap_CS_fsm) & (icmp_ln208_10_fu_113665_p2 == 1'd0))) begin + add_ln216_65_reg_143818 <= add_ln216_65_fu_113671_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_8_fu_111062_p2 == 1'd1) & (icmp_ln206_5_fu_111270_p2 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm))) begin + add_ln216_67_reg_141479 <= add_ln216_67_fu_111366_p2; + add_ln221_48_reg_141485 <= add_ln221_48_fu_111372_p2; + or_ln223_33_reg_141475 <= or_ln223_33_fu_111337_p2; + trunc_ln231_39_reg_141491[6 : 4] <= trunc_ln231_39_fu_111377_p1[6 : 4]; + trunc_ln231_40_reg_141496[10 : 4] <= trunc_ln231_40_fu_111381_p1[10 : 4]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2165 == ap_CS_fsm) & (icmp_ln208_11_fu_114458_p2 == 1'd0))) begin + add_ln216_68_reg_144685 <= add_ln216_68_fu_114464_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln203_1_fu_108860_p2 == 1'd0) & (ap_ST_fsm_state1216 == ap_CS_fsm))) begin + add_ln216_6_reg_138875 <= add_ln216_6_fu_108885_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state1825 == ap_CS_fsm) & ((or_ln223_7_fu_112574_p2 == 1'd1) | (or_ln223_4_reg_142485 == 1'd1)))) begin + add_ln216_70_reg_142861 <= grp_fu_99245_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) & (icmp_ln208_9_fu_107624_p2 == 1'd1) & (icmp_ln206_6_fu_107831_p2 == 1'd0))) begin + add_ln216_71_reg_137883 <= add_ln216_71_fu_107921_p2; + add_ln221_50_reg_137889 <= add_ln221_50_fu_107927_p2; + icmp_ln223_117_reg_137873 <= icmp_ln223_117_fu_107876_p2; + icmp_ln223_118_reg_137878 <= icmp_ln223_118_fu_107892_p2; + trunc_ln231_41_reg_137895[6 : 3] <= trunc_ln231_41_fu_107932_p1[6 : 3]; + trunc_ln231_42_reg_137900[10 : 3] <= trunc_ln231_42_fu_107936_p1[10 : 3]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1223 == ap_CS_fsm)) begin + add_ln216_72_reg_139329 <= grp_fu_99177_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_11_fu_114458_p2 == 1'd1) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (icmp_ln206_7_fu_114665_p2 == 1'd0))) begin + add_ln216_74_reg_145038 <= add_ln216_74_fu_114755_p2; + add_ln221_52_reg_145044 <= add_ln221_52_fu_114761_p2; + icmp_ln223_125_reg_145028 <= icmp_ln223_125_fu_114710_p2; + icmp_ln223_126_reg_145033 <= icmp_ln223_126_fu_114726_p2; + trunc_ln231_43_reg_145050[6 : 4] <= trunc_ln231_43_fu_114766_p1[6 : 4]; + trunc_ln231_44_reg_145055[10 : 4] <= trunc_ln231_44_fu_114770_p1[10 : 4]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state617 == ap_CS_fsm)) begin + add_ln216_75_reg_135708 <= grp_fu_99109_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state500 == ap_CS_fsm) & (icmp_ln208_12_fu_105013_p2 == 1'd0))) begin + add_ln216_76_reg_134834 <= add_ln216_76_fu_105019_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_13_fu_111867_p2 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm))) begin + add_ln216_77_reg_141997 <= add_ln216_77_fu_111873_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_14_fu_108425_p2 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm))) begin + add_ln216_78_reg_138405 <= add_ln216_78_fu_108431_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2315 == ap_CS_fsm) & (icmp_ln208_15_fu_115259_p2 == 1'd0))) begin + add_ln216_79_reg_145560 <= add_ln216_79_fu_115265_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1827 == ap_CS_fsm)) begin + add_ln216_80_reg_142872 <= grp_fu_99245_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state313 == ap_CS_fsm) & ((or_ln223_18_fu_103998_p2 == 1'd1) | (or_ln223_10_reg_133539 == 1'd1)))) begin + add_ln216_82_reg_133894 <= grp_fu_99075_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state1524 == ap_CS_fsm) & ((or_ln223_24_fu_110850_p2 == 1'd1) | (or_ln223_16_reg_140696 == 1'd1)))) begin + add_ln216_86_reg_141067 <= grp_fu_99211_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state918 == ap_CS_fsm) & ((or_ln223_25_fu_107413_p2 == 1'd1) | (or_ln223_17_reg_137110 == 1'd1)))) begin + add_ln216_87_reg_137465 <= grp_fu_99143_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state315 == ap_CS_fsm)) begin + add_ln216_88_reg_133905 <= grp_fu_99075_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state610 == ap_CS_fsm) & (icmp_ln203_2_fu_105423_p2 == 1'd0))) begin + add_ln216_8_reg_135279 <= add_ln216_8_fu_105448_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2128 == ap_CS_fsm) & ((or_ln223_27_fu_114247_p2 == 1'd1) | (or_ln223_23_reg_144249 == 1'd1)))) begin + add_ln216_92_reg_144620 <= grp_fu_99279_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1526 == ap_CS_fsm)) begin + add_ln216_93_reg_141078 <= grp_fu_99211_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state920 == ap_CS_fsm)) begin + add_ln216_94_reg_137476 <= grp_fu_99143_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2130 == ap_CS_fsm)) begin + add_ln216_96_reg_144631 <= grp_fu_99279_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state463 == ap_CS_fsm) & ((or_ln223_37_fu_104801_p2 == 1'd1) | (or_ln223_29_reg_134420 == 1'd1)))) begin + add_ln216_97_reg_134769 <= grp_fu_99092_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state1674 == ap_CS_fsm) & ((or_ln223_41_fu_111655_p2 == 1'd1) | (or_ln223_33_reg_141475 == 1'd1)))) begin + add_ln216_98_reg_141932 <= grp_fu_99228_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state1068 == ap_CS_fsm) & ((or_ln223_42_fu_108214_p2 == 1'd1) | (or_ln223_35_reg_137991 == 1'd1)))) begin + add_ln216_99_reg_138340 <= grp_fu_99160_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state159 == ap_CS_fsm)) begin + add_ln231_15_reg_132684 <= add_ln231_15_fu_103120_p2; + add_ln231_16_reg_132690 <= add_ln231_16_fu_103124_p2; + or_ln223_8_reg_132680 <= or_ln223_8_fu_103116_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1370 == ap_CS_fsm)) begin + add_ln231_21_reg_139862 <= add_ln231_21_fu_109981_p2; + add_ln231_22_reg_139868 <= add_ln231_22_fu_109985_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state764 == ap_CS_fsm)) begin + add_ln231_24_reg_136255 <= add_ln231_24_fu_106537_p2; + add_ln231_25_reg_136261 <= add_ln231_25_fu_106541_p2; + or_ln223_13_reg_136251 <= or_ln223_13_fu_106533_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1974 == ap_CS_fsm)) begin + add_ln231_36_reg_143415 <= add_ln231_36_fu_113380_p2; + add_ln231_37_reg_143421 <= add_ln231_37_fu_113384_p2; + or_ln223_19_reg_143411 <= or_ln223_19_fu_113376_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state462 == ap_CS_fsm)) begin + add_ln231_54_reg_134424[10 : 1] <= add_ln231_54_fu_104729_p2[10 : 1]; + add_ln231_55_reg_134430[6 : 1] <= add_ln231_55_fu_104733_p2[6 : 1]; + or_ln223_29_reg_134420 <= or_ln223_29_fu_104725_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1673 == ap_CS_fsm)) begin + add_ln231_60_reg_141587[10 : 1] <= add_ln231_60_fu_111583_p2[10 : 1]; + add_ln231_61_reg_141593[6 : 1] <= add_ln231_61_fu_111587_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1067 == ap_CS_fsm)) begin + add_ln231_64_reg_137995[10 : 1] <= add_ln231_64_fu_108142_p2[10 : 1]; + add_ln231_66_reg_138001[6 : 1] <= add_ln231_66_fu_108146_p2[6 : 1]; + or_ln223_35_reg_137991 <= or_ln223_35_fu_108138_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2277 == ap_CS_fsm)) begin + add_ln231_73_reg_145150[10 : 1] <= add_ln231_73_fu_114976_p2[10 : 1]; + add_ln231_75_reg_145156[6 : 1] <= add_ln231_75_fu_114980_p2[6 : 1]; + or_ln223_39_reg_145146 <= or_ln223_39_fu_114972_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2497 == ap_CS_fsm) & (icmp_ln246_1_fu_116448_p2 == 1'd0))) begin + add_ln250_2_reg_146470[12 : 2] <= add_ln250_2_fu_116488_p2[12 : 2]; + trunc_ln250_4_reg_146476[5 : 2] <= trunc_ln250_4_fu_116493_p1[5 : 2]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln248_fu_115743_p2 == 1'd1) & (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + add_ln250_4_reg_146022[12 : 3] <= add_ln250_4_fu_115925_p2[12 : 3]; + trunc_ln250_5_reg_146028[5 : 3] <= trunc_ln250_5_fu_115930_p1[5 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln248_1_fu_116507_p2 == 1'd1) & (ap_ST_fsm_state2498 == ap_CS_fsm))) begin + add_ln250_6_reg_146493[12 : 3] <= add_ln250_6_fu_116689_p2[12 : 3]; + trunc_ln250_6_reg_146499[5 : 3] <= trunc_ln250_6_fu_116694_p1[5 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2426 == ap_CS_fsm) & (icmp_ln246_fu_115674_p2 == 1'd0))) begin + add_ln250_reg_145998[12 : 2] <= add_ln250_fu_115714_p2[12 : 2]; + trunc_ln250_reg_146004[5 : 2] <= trunc_ln250_fu_115719_p1[5 : 2]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_7_fu_129954_p2 == 1'd1) & (ap_ST_fsm_state4762 == ap_CS_fsm) & (icmp_ln266_7_fu_129977_p2 == 1'd0))) begin + add_ln276_101_reg_165564 <= add_ln276_101_fu_129994_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4726 == ap_CS_fsm)) begin + add_ln276_102_reg_165386 <= add_ln276_102_fu_129756_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2652 == ap_CS_fsm)) begin + add_ln276_103_reg_149099 <= add_ln276_103_fu_118036_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2689 == ap_CS_fsm) & (icmp_ln268_8_fu_118234_p2 == 1'd0))) begin + add_ln276_104_reg_149268 <= add_ln276_104_fu_118240_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4877 == ap_CS_fsm)) begin + add_ln276_106_reg_166236 <= add_ln276_106_fu_130557_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2730 == ap_CS_fsm)) begin + add_ln276_107_reg_149610 <= add_ln276_107_fu_118429_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2767 == ap_CS_fsm) & (icmp_ln268_9_fu_118627_p2 == 1'd0))) begin + add_ln276_108_reg_149779 <= add_ln276_108_fu_118633_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3883 == ap_CS_fsm)) begin + add_ln276_109_reg_158940 <= add_ln276_109_fu_125078_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3920 == ap_CS_fsm) & (icmp_ln268_10_fu_125276_p2 == 1'd0))) begin + add_ln276_110_reg_159109 <= add_ln276_110_fu_125282_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3305 == ap_CS_fsm) & (icmp_ln268_11_fu_121702_p2 == 1'd0))) begin + add_ln276_111_reg_154169 <= add_ln276_111_fu_121708_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2997 == ap_CS_fsm) & (icmp_ln268_12_fu_119859_p2 == 1'd0))) begin + add_ln276_112_reg_151323 <= add_ln276_112_fu_119865_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_9_fu_118627_p2 == 1'd1) & (ap_ST_fsm_state2767 == ap_CS_fsm) & (icmp_ln266_8_fu_118650_p2 == 1'd0))) begin + add_ln276_114_reg_149788 <= add_ln276_114_fu_118667_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3997 == ap_CS_fsm) & (icmp_ln268_13_fu_125669_p2 == 1'd0))) begin + add_ln276_115_reg_159620 <= add_ln276_115_fu_125675_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3382 == ap_CS_fsm) & (icmp_ln268_14_fu_122095_p2 == 1'd0))) begin + add_ln276_116_reg_154680 <= add_ln276_116_fu_122101_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3074 == ap_CS_fsm) & (icmp_ln268_15_fu_120251_p2 == 1'd0))) begin + add_ln276_117_reg_151829 <= add_ln276_117_fu_120257_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3268 == ap_CS_fsm)) begin + add_ln276_118_reg_154000 <= add_ln276_118_fu_121504_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4534 == ap_CS_fsm) & (icmp_ln268_16_fu_128744_p2 == 1'd0))) begin + add_ln276_119_reg_164010 <= add_ln276_119_fu_128750_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4227 == ap_CS_fsm) & (icmp_ln268_17_fu_126901_p2 == 1'd0))) begin + add_ln276_120_reg_161164 <= add_ln276_120_fu_126907_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_13_fu_125669_p2 == 1'd1) & (ap_ST_fsm_state3997 == ap_CS_fsm) & (icmp_ln266_9_fu_125692_p2 == 1'd0))) begin + add_ln276_122_reg_159629 <= add_ln276_122_fu_125709_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3612 == ap_CS_fsm) & (icmp_ln268_18_fu_123327_p2 == 1'd0))) begin + add_ln276_123_reg_156224 <= add_ln276_123_fu_123333_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_14_fu_122095_p2 == 1'd1) & (ap_ST_fsm_state3382 == ap_CS_fsm) & (icmp_ln266_10_fu_122118_p2 == 1'd0))) begin + add_ln276_125_reg_154689 <= add_ln276_125_fu_122135_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_15_fu_120251_p2 == 1'd1) & (ap_ST_fsm_state3074 == ap_CS_fsm) & (icmp_ln266_11_fu_120274_p2 == 1'd0))) begin + add_ln276_127_reg_151838 <= add_ln276_127_fu_120291_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4610 == ap_CS_fsm) & (icmp_ln268_19_fu_129137_p2 == 1'd0))) begin + add_ln276_128_reg_164521 <= add_ln276_128_fu_129143_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4303 == ap_CS_fsm) & (icmp_ln268_20_fu_127293_p2 == 1'd0))) begin + add_ln276_129_reg_161670 <= add_ln276_129_fu_127299_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3803 == ap_CS_fsm)) begin + add_ln276_12_reg_158254 <= add_ln276_12_fu_124656_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2960 == ap_CS_fsm)) begin + add_ln276_130_reg_151154 <= add_ln276_130_fu_119661_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3688 == ap_CS_fsm) & (icmp_ln268_21_fu_123719_p2 == 1'd0))) begin + add_ln276_131_reg_156730 <= add_ln276_131_fu_123725_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3961 == ap_CS_fsm)) begin + add_ln276_132_reg_159451 <= add_ln276_132_fu_125471_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3346 == ap_CS_fsm)) begin + add_ln276_133_reg_154511 <= add_ln276_133_fu_121897_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4839 == ap_CS_fsm) & (icmp_ln268_22_fu_130369_p2 == 1'd0))) begin + add_ln276_134_reg_166065 <= add_ln276_134_fu_130375_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_19_fu_129137_p2 == 1'd1) & (ap_ST_fsm_state4610 == ap_CS_fsm) & (icmp_ln266_12_fu_129160_p2 == 1'd0))) begin + add_ln276_136_reg_164530 <= add_ln276_136_fu_129177_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_20_fu_127293_p2 == 1'd1) & (ap_ST_fsm_state4303 == ap_CS_fsm) & (icmp_ln266_13_fu_127316_p2 == 1'd0))) begin + add_ln276_138_reg_161679 <= add_ln276_138_fu_127333_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_21_fu_123719_p2 == 1'd1) & (ap_ST_fsm_state3688 == ap_CS_fsm) & (icmp_ln266_14_fu_123742_p2 == 1'd0))) begin + add_ln276_140_reg_156739 <= add_ln276_140_fu_123759_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4915 == ap_CS_fsm) & (icmp_ln268_23_fu_130761_p2 == 1'd0))) begin + add_ln276_141_reg_166571 <= add_ln276_141_fu_130767_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3038 == ap_CS_fsm)) begin + add_ln276_142_reg_151660 <= add_ln276_142_fu_120053_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4497 == ap_CS_fsm)) begin + add_ln276_143_reg_163841 <= add_ln276_143_fu_128546_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4190 == ap_CS_fsm)) begin + add_ln276_144_reg_160995 <= add_ln276_144_fu_126703_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_23_fu_130761_p2 == 1'd1) & (ap_ST_fsm_state4915 == ap_CS_fsm) & (icmp_ln266_15_fu_130784_p2 == 1'd0))) begin + add_ln276_146_reg_166580 <= add_ln276_146_fu_130801_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2842 == ap_CS_fsm) & (icmp_ln268_24_fu_119032_p2 == 1'd0))) begin + add_ln276_147_reg_150293 <= add_ln276_147_fu_119038_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3575 == ap_CS_fsm)) begin + add_ln276_148_reg_156055 <= add_ln276_148_fu_123129_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4072 == ap_CS_fsm) & (icmp_ln268_25_fu_126074_p2 == 1'd0))) begin + add_ln276_149_reg_160134 <= add_ln276_149_fu_126080_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3457 == ap_CS_fsm) & (icmp_ln268_26_fu_122500_p2 == 1'd0))) begin + add_ln276_150_reg_155194 <= add_ln276_150_fu_122506_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3149 == ap_CS_fsm) & (icmp_ln268_27_fu_120655_p2 == 1'd0))) begin + add_ln276_151_reg_152338 <= add_ln276_151_fu_120661_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4685 == ap_CS_fsm) & (icmp_ln268_28_fu_129542_p2 == 1'd0))) begin + add_ln276_152_reg_165035 <= add_ln276_152_fu_129548_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4378 == ap_CS_fsm) & (icmp_ln268_29_fu_127697_p2 == 1'd0))) begin + add_ln276_153_reg_162179 <= add_ln276_153_fu_127703_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3763 == ap_CS_fsm) & (icmp_ln268_30_fu_124123_p2 == 1'd0))) begin + add_ln276_154_reg_157239 <= add_ln276_154_fu_124129_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4990 == ap_CS_fsm) & (icmp_ln268_31_fu_131165_p2 == 1'd0))) begin + add_ln276_155_reg_167080 <= add_ln276_155_fu_131171_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4574 == ap_CS_fsm)) begin + add_ln276_156_reg_164352 <= add_ln276_156_fu_128939_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4267 == ap_CS_fsm)) begin + add_ln276_157_reg_161501 <= add_ln276_157_fu_127095_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3652 == ap_CS_fsm)) begin + add_ln276_158_reg_156561 <= add_ln276_158_fu_123521_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4802 == ap_CS_fsm)) begin + add_ln276_159_reg_165896 <= add_ln276_159_fu_130171_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4879 == ap_CS_fsm)) begin + add_ln276_160_reg_166402 <= add_ln276_160_fu_130563_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2806 == ap_CS_fsm)) begin + add_ln276_161_reg_150124 <= add_ln276_161_fu_118834_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4036 == ap_CS_fsm)) begin + add_ln276_162_reg_159965 <= add_ln276_162_fu_125876_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3421 == ap_CS_fsm)) begin + add_ln276_163_reg_155025 <= add_ln276_163_fu_122302_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3113 == ap_CS_fsm)) begin + add_ln276_164_reg_152169 <= add_ln276_164_fu_120457_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4649 == ap_CS_fsm)) begin + add_ln276_165_reg_164866 <= add_ln276_165_fu_129344_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4342 == ap_CS_fsm)) begin + add_ln276_166_reg_162010 <= add_ln276_166_fu_127499_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3727 == ap_CS_fsm)) begin + add_ln276_167_reg_157070 <= add_ln276_167_fu_123925_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4954 == ap_CS_fsm)) begin + add_ln276_168_reg_166911 <= add_ln276_168_fu_130967_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3188 == ap_CS_fsm)) begin + add_ln276_17_reg_153314 <= add_ln276_17_fu_121082_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3800 == ap_CS_fsm) & (icmp_ln259_1_fu_124304_p2 == 1'd0))) begin + add_ln276_1_reg_157425 <= grp_fu_131512_p3; + add_ln279_2_reg_157413[12 : 2] <= add_ln279_2_fu_124344_p2[12 : 2]; + trunc_ln279_10_reg_157419[5 : 2] <= trunc_ln279_10_fu_124349_p1[5 : 2]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2880 == ap_CS_fsm)) begin + add_ln276_22_reg_150478 <= add_ln276_22_fu_119240_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4417 == ap_CS_fsm)) begin + add_ln276_30_reg_163155 <= add_ln276_30_fu_128124_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4110 == ap_CS_fsm)) begin + add_ln276_35_reg_160319 <= add_ln276_35_fu_126282_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3495 == ap_CS_fsm)) begin + add_ln276_38_reg_155379 <= add_ln276_38_fu_122708_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4723 == ap_CS_fsm)) begin + add_ln276_42_reg_165220 <= add_ln276_42_fu_129750_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2612 == ap_CS_fsm) & (icmp_ln268_fu_117818_p2 == 1'd0))) begin + add_ln276_43_reg_148753 <= add_ln276_43_fu_117824_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_fu_117818_p2 == 1'd1) & (ap_ST_fsm_state2612 == ap_CS_fsm) & (icmp_ln266_fu_117841_p2 == 1'd0))) begin + add_ln276_47_reg_148762 <= add_ln276_47_fu_117858_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3843 == ap_CS_fsm) & (icmp_ln268_1_fu_124860_p2 == 1'd0))) begin + add_ln276_48_reg_158594 <= add_ln276_48_fu_124866_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3228 == ap_CS_fsm) & (icmp_ln268_2_fu_121286_p2 == 1'd0))) begin + add_ln276_49_reg_153654 <= add_ln276_49_fu_121292_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2572 == ap_CS_fsm)) begin + add_ln276_4_reg_148413 <= add_ln276_4_fu_117614_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2920 == ap_CS_fsm) & (icmp_ln268_3_fu_119444_p2 == 1'd0))) begin + add_ln276_50_reg_150813 <= add_ln276_50_fu_119450_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2727 == ap_CS_fsm)) begin + add_ln276_52_reg_149439 <= add_ln276_52_fu_118423_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_1_fu_124860_p2 == 1'd1) & (ap_ST_fsm_state3843 == ap_CS_fsm) & (icmp_ln266_1_fu_124883_p2 == 1'd0))) begin + add_ln276_56_reg_158603 <= add_ln276_56_fu_124900_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_2_fu_121286_p2 == 1'd1) & (ap_ST_fsm_state3228 == ap_CS_fsm) & (icmp_ln266_2_fu_121309_p2 == 1'd0))) begin + add_ln276_59_reg_153663 <= add_ln276_59_fu_121326_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4457 == ap_CS_fsm) & (icmp_ln268_4_fu_128328_p2 == 1'd0))) begin + add_ln276_62_reg_163495 <= add_ln276_62_fu_128334_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4150 == ap_CS_fsm) & (icmp_ln268_5_fu_126486_p2 == 1'd0))) begin + add_ln276_63_reg_160654 <= add_ln276_63_fu_126492_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_3_fu_119444_p2 == 1'd1) & (ap_ST_fsm_state2920 == ap_CS_fsm) & (icmp_ln266_3_fu_119467_p2 == 1'd0))) begin + add_ln276_65_reg_150822 <= add_ln276_65_fu_119484_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3535 == ap_CS_fsm) & (icmp_ln268_6_fu_122912_p2 == 1'd0))) begin + add_ln276_67_reg_155714 <= add_ln276_67_fu_122918_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3958 == ap_CS_fsm)) begin + add_ln276_69_reg_159280 <= add_ln276_69_fu_125465_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln261_fu_117325_p2 == 1'd1) & (ap_ST_fsm_state2570 == ap_CS_fsm))) begin + add_ln276_6_reg_148004 <= grp_fu_131420_p3; + add_ln279_4_reg_147992[12 : 3] <= add_ln279_4_fu_117471_p2[12 : 3]; + trunc_ln279_11_reg_147998[5 : 3] <= trunc_ln279_11_fu_117476_p1[5 : 3]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3343 == ap_CS_fsm)) begin + add_ln276_72_reg_154340 <= add_ln276_72_fu_121891_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3035 == ap_CS_fsm)) begin + add_ln276_75_reg_151494 <= add_ln276_75_fu_120047_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2575 == ap_CS_fsm)) begin + add_ln276_78_reg_148584 <= add_ln276_78_fu_117620_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_4_fu_128328_p2 == 1'd1) & (ap_ST_fsm_state4457 == ap_CS_fsm) & (icmp_ln266_4_fu_128351_p2 == 1'd0))) begin + add_ln276_79_reg_163504 <= add_ln276_79_fu_128368_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln261_1_fu_124367_p2 == 1'd1) & (ap_ST_fsm_state3801 == ap_CS_fsm))) begin + add_ln276_7_reg_157845 <= grp_fu_131526_p3; + add_ln279_7_reg_157833[12 : 3] <= add_ln279_7_fu_124513_p2[12 : 3]; + trunc_ln279_12_reg_157839[5 : 3] <= trunc_ln279_12_fu_124518_p1[5 : 3]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3806 == ap_CS_fsm)) begin + add_ln276_82_reg_158425 <= add_ln276_82_fu_124662_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_5_fu_126486_p2 == 1'd1) & (ap_ST_fsm_state4150 == ap_CS_fsm) & (icmp_ln266_5_fu_126509_p2 == 1'd0))) begin + add_ln276_83_reg_160663 <= add_ln276_83_fu_126526_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3191 == ap_CS_fsm)) begin + add_ln276_85_reg_153485 <= add_ln276_85_fu_121088_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4762 == ap_CS_fsm) & (icmp_ln268_7_fu_129954_p2 == 1'd0))) begin + add_ln276_86_reg_165555 <= add_ln276_86_fu_129960_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_6_fu_122912_p2 == 1'd1) & (ap_ST_fsm_state3535 == ap_CS_fsm) & (icmp_ln266_6_fu_122935_p2 == 1'd0))) begin + add_ln276_88_reg_155723 <= add_ln276_88_fu_122952_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2883 == ap_CS_fsm)) begin + add_ln276_89_reg_150644 <= add_ln276_89_fu_119246_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4572 == ap_CS_fsm)) begin + add_ln276_91_reg_164181 <= add_ln276_91_fu_128933_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4420 == ap_CS_fsm)) begin + add_ln276_92_reg_163326 <= add_ln276_92_fu_128130_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4265 == ap_CS_fsm)) begin + add_ln276_94_reg_161335 <= add_ln276_94_fu_127089_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4113 == ap_CS_fsm)) begin + add_ln276_95_reg_160485 <= add_ln276_95_fu_126288_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3650 == ap_CS_fsm)) begin + add_ln276_97_reg_156395 <= add_ln276_97_fu_123515_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3498 == ap_CS_fsm)) begin + add_ln276_99_reg_155545 <= add_ln276_99_fu_122714_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2569 == ap_CS_fsm) & (icmp_ln259_fu_117242_p2 == 1'd0))) begin + add_ln276_reg_147608 <= grp_fu_131406_p3; + add_ln279_reg_147596[12 : 2] <= add_ln279_fu_117282_p2[12 : 2]; + trunc_ln279_reg_147602[5 : 2] <= trunc_ln279_fu_117287_p1[5 : 2]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + add_ln703_11_reg_165547 <= add_ln703_11_fu_129879_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + add_ln703_15_reg_149260 <= add_ln703_15_fu_118159_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + add_ln703_16_reg_149771 <= add_ln703_16_fu_118552_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + add_ln703_18_reg_159101 <= add_ln703_18_fu_125201_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + add_ln703_19_reg_154161 <= add_ln703_19_fu_121627_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + add_ln703_1_reg_158586 <= add_ln703_1_fu_124785_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + add_ln703_20_reg_151315 <= add_ln703_20_fu_119784_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + add_ln703_21_reg_159612 <= add_ln703_21_fu_125594_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + add_ln703_22_reg_154672 <= add_ln703_22_fu_122020_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + add_ln703_23_reg_151821 <= add_ln703_23_fu_120176_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + add_ln703_25_reg_164002 <= add_ln703_25_fu_128669_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + add_ln703_26_reg_161156 <= add_ln703_26_fu_126826_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + add_ln703_27_reg_156216 <= add_ln703_27_fu_123252_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + add_ln703_29_reg_164513 <= add_ln703_29_fu_129062_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + add_ln703_2_reg_153646 <= add_ln703_2_fu_121211_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + add_ln703_30_reg_161662 <= add_ln703_30_fu_127218_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + add_ln703_32_reg_156722 <= add_ln703_32_fu_123644_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + add_ln703_35_reg_166057 <= add_ln703_35_fu_130294_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + add_ln703_39_reg_166563 <= add_ln703_39_fu_130686_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + add_ln703_3_reg_150805 <= add_ln703_3_fu_119369_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + add_ln703_46_reg_150285 <= add_ln703_46_fu_118957_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + add_ln703_49_reg_160126 <= add_ln703_49_fu_125999_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + add_ln703_50_reg_155186 <= add_ln703_50_fu_122425_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + add_ln703_51_reg_152330 <= add_ln703_51_fu_120580_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + add_ln703_53_reg_165027 <= add_ln703_53_fu_129467_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + add_ln703_54_reg_162171 <= add_ln703_54_fu_127622_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + add_ln703_55_reg_157231 <= add_ln703_55_fu_124048_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + add_ln703_59_reg_167072 <= add_ln703_59_fu_131090_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + add_ln703_5_reg_163487 <= add_ln703_5_fu_128253_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + add_ln703_6_reg_160646 <= add_ln703_6_fu_126411_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + add_ln703_7_reg_155706 <= add_ln703_7_fu_122837_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + add_ln703_reg_148745 <= add_ln703_fu_117743_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state311 == ap_CS_fsm)) begin + icmp_ln223_67_reg_133518 <= icmp_ln223_67_fu_103823_p2; + icmp_ln223_68_reg_133523 <= icmp_ln223_68_fu_103839_p2; + or_ln231_11_reg_133533[2 : 1] <= or_ln231_11_fu_103877_p4[2 : 1]; +or_ln231_11_reg_133533[6 : 4] <= or_ln231_11_fu_103877_p4[6 : 4]; + trunc_ln231_25_reg_133528[10 : 3] <= trunc_ln231_25_fu_103863_p1[10 : 3]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state916 == ap_CS_fsm)) begin + icmp_ln223_81_reg_137089 <= icmp_ln223_81_fu_107238_p2; + icmp_ln223_82_reg_137094 <= icmp_ln223_82_fu_107254_p2; + or_ln231_16_reg_137104[2 : 1] <= or_ln231_16_fu_107292_p4[2 : 1]; +or_ln231_16_reg_137104[6 : 4] <= or_ln231_16_fu_107292_p4[6 : 4]; + trunc_ln231_32_reg_137099[10 : 3] <= trunc_ln231_32_fu_107278_p1[10 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln201_fu_101946_p2 == 1'd1) & (ap_ST_fsm_state3 == ap_CS_fsm))) begin + mul_ln201_1_reg_131671[18 : 5] <= mul_ln201_1_fu_101972_p2[18 : 5]; + zext_ln199_reg_131659[3 : 1] <= zext_ln199_fu_101964_p1[3 : 1]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2 == ap_CS_fsm) & (icmp_ln199_fu_101926_p2 == 1'd0))) begin + mul_ln201_reg_131633[17 : 5] <= mul_ln201_fu_101932_p2[17 : 5]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln201_1_fu_108832_p2 == 1'd0) & (ap_ST_fsm_state1215 == ap_CS_fsm))) begin + mul_ln203_1_reg_138846[14 : 4] <= mul_ln203_1_fu_108838_p2[14 : 4]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln203_fu_101988_p2 == 1'd1))) begin + mul_ln203_2_reg_131726[14 : 4] <= mul_ln203_2_fu_102032_p2[14 : 4]; + or_ln201_reg_131702[3 : 1] <= or_ln201_fu_102018_p2[3 : 1]; + zext_ln201_2_reg_131714[3 : 1] <= zext_ln201_2_fu_102024_p1[3 : 1]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln203_1_fu_108860_p2 == 1'd1) & (ap_ST_fsm_state1216 == ap_CS_fsm))) begin + mul_ln203_3_reg_138905[14 : 4] <= mul_ln203_3_fu_108904_p2[14 : 4]; + or_ln201_1_reg_138881[3 : 1] <= or_ln201_1_fu_108890_p2[3 : 1]; + zext_ln201_3_reg_138893[3 : 1] <= zext_ln201_3_fu_108896_p1[3 : 1]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln201_fu_101946_p2 == 1'd0))) begin + mul_ln203_reg_131654[14 : 4] <= mul_ln203_fu_101952_p2[14 : 4]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln246_fu_115674_p2 == 1'd1) & (ap_ST_fsm_state2426 == ap_CS_fsm))) begin + mul_ln250_1_reg_146010[12 : 3] <= mul_ln250_1_fu_115733_p2[12 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2425 == ap_CS_fsm) & (icmp_ln244_fu_115662_p2 == 1'd0))) begin + mul_ln250_reg_145989[12 : 3] <= mul_ln250_fu_115668_p2[12 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln259_fu_117242_p2 == 1'd1) & (ap_ST_fsm_state2569 == ap_CS_fsm))) begin + mul_ln279_1_reg_147620[12 : 3] <= mul_ln279_1_fu_117311_p2[12 : 3]; + mul_ln279_3_reg_147614[18 : 5] <= mul_ln279_3_fu_117305_p2[18 : 5]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2568 == ap_CS_fsm) & (icmp_ln257_fu_117220_p2 == 1'd0))) begin + mul_ln279_2_reg_146941[17 : 5] <= mul_ln279_2_fu_117226_p2[17 : 5]; + mul_ln279_reg_146947[12 : 3] <= mul_ln279_fu_117232_p2[12 : 3]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + oh_0_0_cast_reg_131618[3 : 0] <= oh_0_0_cast_fu_101918_p1[3 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1522 == ap_CS_fsm)) begin + or_ln223_16_reg_140696 <= or_ln223_16_fu_110706_p2; + trunc_ln231_30_reg_140700[6 : 3] <= trunc_ln231_30_fu_110730_p1[6 : 3]; + trunc_ln231_31_reg_140705[10 : 3] <= trunc_ln231_31_fu_110734_p1[10 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state313 == ap_CS_fsm) & (or_ln223_10_reg_133539 == 1'd0))) begin + or_ln223_18_reg_133561 <= or_ln223_18_fu_103998_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1218 == ap_CS_fsm)) begin + or_ln223_1_reg_138942 <= or_ln223_1_fu_109027_p2; + trunc_ln231_18_reg_138946[6 : 3] <= trunc_ln231_18_fu_109051_p1[6 : 3]; + trunc_ln231_19_reg_138951[10 : 3] <= trunc_ln231_19_fu_109055_p1[10 : 3]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + or_ln223_23_reg_144249 <= or_ln223_23_fu_114103_p2; + trunc_ln231_35_reg_144253[6 : 3] <= trunc_ln231_35_fu_114127_p1[6 : 3]; + trunc_ln231_36_reg_144258[10 : 3] <= trunc_ln231_36_fu_114131_p1[10 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1524 == ap_CS_fsm))) begin + or_ln223_24_reg_140734 <= or_ln223_24_fu_110850_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state918 == ap_CS_fsm) & (or_ln223_17_reg_137110 == 1'd0))) begin + or_ln223_25_reg_137132 <= or_ln223_25_fu_107413_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2128 == ap_CS_fsm) & (or_ln223_23_reg_144249 == 1'd0))) begin + or_ln223_27_reg_144287 <= or_ln223_27_fu_114247_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state612 == ap_CS_fsm)) begin + or_ln223_2_reg_135321 <= or_ln223_2_fu_105576_p2; + tmp_5_reg_135330 <= {{sub_ln231_2_fu_105594_p2[6:4]}}; + trunc_ln231_20_reg_135325[10 : 3] <= trunc_ln231_20_fu_105600_p1[10 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state463 == ap_CS_fsm) & (or_ln223_29_reg_134420 == 1'd0))) begin + or_ln223_37_reg_134436 <= or_ln223_37_fu_104801_p2; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + or_ln223_41_reg_141599 <= or_ln223_41_fu_111655_p2; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + or_ln223_42_reg_138007 <= or_ln223_42_fu_108214_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2278 == ap_CS_fsm) & (or_ln223_39_reg_145146 == 1'd0))) begin + or_ln223_43_reg_145162 <= or_ln223_43_fu_115048_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state500 == ap_CS_fsm) & (icmp_ln208_12_fu_105013_p2 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0))) begin + or_ln223_44_reg_134841 <= or_ln223_44_fu_105091_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_13_fu_111867_p2 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm))) begin + or_ln223_45_reg_142004 <= or_ln223_45_fu_111945_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_14_fu_108425_p2 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm))) begin + or_ln223_46_reg_138412 <= or_ln223_46_fu_108503_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2315 == ap_CS_fsm) & (icmp_ln208_15_fu_115259_p2 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0))) begin + or_ln223_47_reg_145567 <= or_ln223_47_fu_115337_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1823 == ap_CS_fsm)) begin + or_ln223_4_reg_142485 <= or_ln223_4_fu_112430_p2; + trunc_ln231_21_reg_142489[6 : 3] <= trunc_ln231_21_fu_112454_p1[6 : 3]; + trunc_ln231_22_reg_142494[10 : 3] <= trunc_ln231_22_fu_112458_p1[10 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1220 == ap_CS_fsm))) begin + or_ln223_5_reg_138980 <= or_ln223_5_fu_109171_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state614 == ap_CS_fsm) & (or_ln223_2_reg_135321 == 1'd0))) begin + or_ln223_6_reg_135359 <= or_ln223_6_fu_105731_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state1825 == ap_CS_fsm) & (or_ln223_4_reg_142485 == 1'd0))) begin + or_ln223_7_reg_142523 <= or_ln223_7_fu_112574_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + or_ln223_reg_131762 <= or_ln223_fu_102155_p2; + tmp_4_reg_131771 <= {{sub_ln231_fu_102173_p2[6:4]}}; + trunc_ln231_reg_131766[10 : 3] <= trunc_ln231_fu_102179_p1[10 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_2_fu_106151_p2 == 1'd1) & (icmp_ln208_2_fu_105943_p2 == 1'd1) & (ap_ST_fsm_state652 == ap_CS_fsm))) begin + or_ln231_20_reg_136154[2 : 1] <= or_ln231_20_fu_106311_p2[2 : 1]; + sext_ln221_6_reg_136142 <= sext_ln221_6_fu_106304_p1; + sext_ln231_6_reg_136159[2 : 1] <= sext_ln231_6_fu_106325_p1[2 : 1]; + zext_ln216_10_reg_136148[17 : 0] <= zext_ln216_10_fu_106308_p1[17 : 0]; + zext_ln231_17_reg_136165[2 : 1] <= zext_ln231_17_fu_106337_p1[2 : 1]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_102733_p2 == 1'd1) & (icmp_ln208_fu_102524_p2 == 1'd1) & (ap_ST_fsm_state47 == ap_CS_fsm))) begin + or_ln231_reg_132583[2 : 1] <= or_ln231_fu_102893_p2[2 : 1]; + sext_ln221_4_reg_132571 <= sext_ln221_4_fu_102886_p1; + sext_ln231_4_reg_132588[2 : 1] <= sext_ln231_4_fu_102907_p1[2 : 1]; + zext_ln216_8_reg_132577[17 : 0] <= zext_ln216_8_fu_102890_p1[17 : 0]; + zext_ln231_13_reg_132594[2 : 1] <= zext_ln231_13_fu_102919_p1[2 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3 == ap_CS_fsm)) begin + ow_0_0_0_cast_reg_131639[3 : 0] <= ow_0_0_0_cast_fu_101938_p1[3 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1215 == ap_CS_fsm)) begin + ow_0_1_0_cast_reg_138831[3 : 0] <= ow_0_1_0_cast_fu_108824_p1[3 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd28 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd28 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd28 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd28 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd28 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd28 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd28 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd28 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd28 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd28 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd28 == add_ln1116_6_reg_135778)) | ((7'd28 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd28 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd28 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd28 == add_ln1116_4_reg_132207)) | ((7'd28 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100018 <= data_28_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd70 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd70 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd70 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd70 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd70 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd70 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd70 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd70 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd70 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd70 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd70 == add_ln1116_6_reg_135778)) | ((7'd70 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd70 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd70 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd70 == add_ln1116_4_reg_132207)) | ((7'd70 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100038 <= data_70_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd26 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd26 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd26 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd26 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd26 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd26 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd26 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd26 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd26 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd26 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd26 == add_ln1116_6_reg_135778)) | ((7'd26 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd26 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd26 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd26 == add_ln1116_4_reg_132207)) | ((7'd26 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100058 <= data_26_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd114 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd114 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd114 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd114 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd114 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd114 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd114 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd114 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd114 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd114 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd114 == add_ln1116_6_reg_135778)) | ((7'd114 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd114 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd114 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd114 == add_ln1116_4_reg_132207)) | ((7'd114 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100078 <= data_114_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd24 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd24 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd24 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd24 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd24 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd24 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd24 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd24 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd24 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd24 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd24 == add_ln1116_6_reg_135778)) | ((7'd24 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd24 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd24 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd24 == add_ln1116_4_reg_132207)) | ((7'd24 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100098 <= data_24_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd92 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd92 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd92 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd92 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd92 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd92 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd92 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd92 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd92 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd92 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd92 == add_ln1116_6_reg_135778)) | ((7'd92 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd92 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd92 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd92 == add_ln1116_4_reg_132207)) | ((7'd92 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100118 <= data_92_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd22 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd22 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd22 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd22 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd22 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd22 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd22 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd22 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd22 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd22 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd22 == add_ln1116_6_reg_135778)) | ((7'd22 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd22 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd22 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd22 == add_ln1116_4_reg_132207)) | ((7'd22 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100138 <= data_22_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd116 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd116 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd116 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd116 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd116 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd116 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd116 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd116 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd116 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd116 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd116 == add_ln1116_6_reg_135778)) | ((7'd116 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd116 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd116 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd116 == add_ln1116_4_reg_132207)) | ((7'd116 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100158 <= data_116_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd20 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd20 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd20 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd20 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd20 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd20 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd20 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd20 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd20 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd20 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd20 == add_ln1116_6_reg_135778)) | ((7'd20 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd20 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd20 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd20 == add_ln1116_4_reg_132207)) | ((7'd20 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100178 <= data_20_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd68 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd68 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd68 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd68 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd68 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd68 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd68 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd68 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd68 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd68 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd68 == add_ln1116_6_reg_135778)) | ((7'd68 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd68 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd68 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd68 == add_ln1116_4_reg_132207)) | ((7'd68 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100198 <= data_68_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd18 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd18 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd18 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd18 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd18 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd18 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd18 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd18 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd18 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd18 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd18 == add_ln1116_6_reg_135778)) | ((7'd18 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd18 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd18 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd18 == add_ln1116_4_reg_132207)) | ((7'd18 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100218 <= data_18_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd118 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd118 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd118 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd118 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd118 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd118 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd118 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd118 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd118 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd118 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd118 == add_ln1116_6_reg_135778)) | ((7'd118 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd118 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd118 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd118 == add_ln1116_4_reg_132207)) | ((7'd118 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100238 <= data_118_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd16 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd16 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd16 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd16 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd16 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd16 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd16 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd16 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd16 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd16 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd16 == add_ln1116_6_reg_135778)) | ((7'd16 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd16 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd16 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd16 == add_ln1116_4_reg_132207)) | ((7'd16 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100258 <= data_16_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd80 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd80 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd80 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd80 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd80 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd80 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd80 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd80 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd80 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd80 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd80 == add_ln1116_6_reg_135778)) | ((7'd80 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd80 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd80 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd80 == add_ln1116_4_reg_132207)) | ((7'd80 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100278 <= data_80_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd14 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd14 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd14 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd14 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd14 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd14 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd14 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd14 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd14 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd14 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd14 == add_ln1116_6_reg_135778)) | ((7'd14 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd14 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd14 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd14 == add_ln1116_4_reg_132207)) | ((7'd14 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100298 <= data_14_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd120 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd120 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd120 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd120 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd120 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd120 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd120 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd120 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd120 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd120 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd120 == add_ln1116_6_reg_135778)) | ((7'd120 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd120 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd120 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd120 == add_ln1116_4_reg_132207)) | ((7'd120 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100318 <= data_120_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd12 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd12 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd12 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd12 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd12 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd12 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd12 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd12 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd12 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd12 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd12 == add_ln1116_6_reg_135778)) | ((7'd12 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd12 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd12 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd12 == add_ln1116_4_reg_132207)) | ((7'd12 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100338 <= data_12_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd66 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd66 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd66 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd66 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd66 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd66 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd66 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd66 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd66 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd66 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd66 == add_ln1116_6_reg_135778)) | ((7'd66 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd66 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd66 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd66 == add_ln1116_4_reg_132207)) | ((7'd66 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100358 <= data_66_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd10 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd10 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd10 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd10 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd10 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd10 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd10 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd10 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd10 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd10 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd10 == add_ln1116_6_reg_135778)) | ((7'd10 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd10 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd10 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd10 == add_ln1116_4_reg_132207)) | ((7'd10 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100378 <= data_10_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd122 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd122 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd122 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd122 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd122 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd122 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd122 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd122 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd122 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd122 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd122 == add_ln1116_6_reg_135778)) | ((7'd122 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd122 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd122 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd122 == add_ln1116_4_reg_132207)) | ((7'd122 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100398 <= data_122_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd8 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd8 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd8 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd8 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd8 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd8 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd8 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd8 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd8 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd8 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd8 == add_ln1116_6_reg_135778)) | ((7'd8 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd8 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd8 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd8 == add_ln1116_4_reg_132207)) | ((7'd8 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100418 <= data_8_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd94 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd94 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd94 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd94 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd94 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd94 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd94 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd94 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd94 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd94 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd94 == add_ln1116_6_reg_135778)) | ((7'd94 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd94 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd94 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd94 == add_ln1116_4_reg_132207)) | ((7'd94 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100438 <= data_94_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd6 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd6 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd6 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd6 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd6 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd6 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd6 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd6 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd6 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd6 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd6 == add_ln1116_6_reg_135778)) | ((7'd6 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd6 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd6 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd6 == add_ln1116_4_reg_132207)) | ((7'd6 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100458 <= data_6_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd124 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd124 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd124 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd124 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd124 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd124 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd124 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd124 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd124 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd124 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd124 == add_ln1116_6_reg_135778)) | ((7'd124 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd124 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd124 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd124 == add_ln1116_4_reg_132207)) | ((7'd124 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100478 <= data_124_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd4 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd4 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd4 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd4 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd4 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd4 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd4 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd4 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd4 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd4 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd4 == add_ln1116_6_reg_135778)) | ((7'd4 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd4 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd4 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd4 == add_ln1116_4_reg_132207)) | ((7'd4 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100498 <= data_4_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd64 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd64 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd64 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd64 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd64 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd64 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd64 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd64 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd64 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd64 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd64 == add_ln1116_6_reg_135778)) | ((7'd64 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd64 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd64 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd64 == add_ln1116_4_reg_132207)) | ((7'd64 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100518 <= data_64_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd2 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd2 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd2 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd2 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd2 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd2 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd2 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd2 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd2 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd2 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd2 == add_ln1116_6_reg_135778)) | ((7'd2 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd2 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd2 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd2 == add_ln1116_4_reg_132207)) | ((7'd2 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100538 <= data_2_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd126 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd126 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd126 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd126 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd126 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd126 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd126 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd126 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd126 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd126 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd126 == add_ln1116_6_reg_135778)) | ((7'd126 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd126 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd126 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd126 == add_ln1116_4_reg_132207)) | ((7'd126 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100558 <= data_126_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd0 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd0 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd0 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd0 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd0 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd0 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd0 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd0 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd0 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd0 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd0 == add_ln1116_6_reg_135778)) | ((7'd0 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd0 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd0 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd0 == add_ln1116_4_reg_132207)) | ((7'd0 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_100578 <= data_0_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((~(7'd0 == add_ln1116_23_reg_143834) & ~(7'd126 == add_ln1116_23_reg_143834) & ~(7'd2 == add_ln1116_23_reg_143834) & ~(7'd64 == add_ln1116_23_reg_143834) & ~(7'd4 == add_ln1116_23_reg_143834) & ~(7'd124 == add_ln1116_23_reg_143834) & ~(7'd6 == add_ln1116_23_reg_143834) & ~(7'd94 == add_ln1116_23_reg_143834) & ~(7'd8 == add_ln1116_23_reg_143834) & ~(7'd122 == add_ln1116_23_reg_143834) & ~(7'd10 == add_ln1116_23_reg_143834) & ~(7'd66 == add_ln1116_23_reg_143834) & ~(7'd12 == add_ln1116_23_reg_143834) & ~(7'd120 == add_ln1116_23_reg_143834) & ~(7'd14 == add_ln1116_23_reg_143834) & ~(7'd80 == add_ln1116_23_reg_143834) & ~(7'd16 == add_ln1116_23_reg_143834) & ~(7'd118 == add_ln1116_23_reg_143834) & ~(7'd18 == add_ln1116_23_reg_143834) & ~(7'd68 == add_ln1116_23_reg_143834) & ~(7'd20 == add_ln1116_23_reg_143834) & ~(7'd116 == add_ln1116_23_reg_143834) & ~(7'd22 == add_ln1116_23_reg_143834) & ~(7'd92 == add_ln1116_23_reg_143834) & ~(7'd24 == add_ln1116_23_reg_143834) & ~(7'd114 == add_ln1116_23_reg_143834) & ~(7'd26 == add_ln1116_23_reg_143834) & ~(7'd70 == add_ln1116_23_reg_143834) & ~(7'd28 == add_ln1116_23_reg_143834) & ~(7'd112 == add_ln1116_23_reg_143834) & ~(7'd30 == add_ln1116_23_reg_143834) & ~(7'd86 == add_ln1116_23_reg_143834) & ~(7'd32 == add_ln1116_23_reg_143834) & ~(7'd110 == add_ln1116_23_reg_143834) & ~(7'd34 == add_ln1116_23_reg_143834) & ~(7'd72 == add_ln1116_23_reg_143834) & ~(7'd36 == add_ln1116_23_reg_143834) & ~(7'd108 == add_ln1116_23_reg_143834) & ~(7'd38 == add_ln1116_23_reg_143834) & ~(7'd90 == add_ln1116_23_reg_143834) & ~(7'd40 == add_ln1116_23_reg_143834) & ~(7'd106 == add_ln1116_23_reg_143834) & ~(7'd42 == add_ln1116_23_reg_143834) & ~(7'd74 == add_ln1116_23_reg_143834) & ~(7'd44 == add_ln1116_23_reg_143834) & ~(7'd104 == add_ln1116_23_reg_143834) & ~(7'd46 == add_ln1116_23_reg_143834) & ~(7'd82 == add_ln1116_23_reg_143834) & ~(7'd48 == add_ln1116_23_reg_143834) & ~(7'd102 == add_ln1116_23_reg_143834) & ~(7'd50 == add_ln1116_23_reg_143834) & ~(7'd76 == add_ln1116_23_reg_143834) & ~(7'd52 == add_ln1116_23_reg_143834) & ~(7'd100 == add_ln1116_23_reg_143834) & ~(7'd54 == add_ln1116_23_reg_143834) & ~(7'd88 == add_ln1116_23_reg_143834) & ~(7'd56 == add_ln1116_23_reg_143834) & ~(7'd98 == add_ln1116_23_reg_143834) & ~(7'd58 == add_ln1116_23_reg_143834) & ~(7'd78 == add_ln1116_23_reg_143834) & ~(7'd60 == add_ln1116_23_reg_143834) & ~(7'd96 == add_ln1116_23_reg_143834) & ~(7'd62 == add_ln1116_23_reg_143834) & ~(7'd84 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | (~(7'd0 == add_ln1116_14_reg_143436) & ~(7'd126 == add_ln1116_14_reg_143436) & ~(7'd2 == add_ln1116_14_reg_143436) & ~(7'd64 == add_ln1116_14_reg_143436) & ~(7'd4 == add_ln1116_14_reg_143436) & ~(7'd124 == add_ln1116_14_reg_143436) & ~(7'd6 == add_ln1116_14_reg_143436) & ~(7'd94 == add_ln1116_14_reg_143436) & ~(7'd8 == add_ln1116_14_reg_143436) & ~(7'd122 == add_ln1116_14_reg_143436) & ~(7'd10 == add_ln1116_14_reg_143436) & ~(7'd66 == add_ln1116_14_reg_143436) & ~(7'd12 == add_ln1116_14_reg_143436) & ~(7'd120 == add_ln1116_14_reg_143436) & ~(7'd14 == add_ln1116_14_reg_143436) & ~(7'd80 == add_ln1116_14_reg_143436) & ~(7'd16 == add_ln1116_14_reg_143436) & ~(7'd118 == add_ln1116_14_reg_143436) & ~(7'd18 == add_ln1116_14_reg_143436) & ~(7'd68 == add_ln1116_14_reg_143436) & ~(7'd20 == add_ln1116_14_reg_143436) & ~(7'd116 == add_ln1116_14_reg_143436) & ~(7'd22 == add_ln1116_14_reg_143436) & ~(7'd92 == add_ln1116_14_reg_143436) & ~(7'd24 == add_ln1116_14_reg_143436) & ~(7'd114 == add_ln1116_14_reg_143436) & ~(7'd26 == add_ln1116_14_reg_143436) & ~(7'd70 == add_ln1116_14_reg_143436) & ~(7'd28 == add_ln1116_14_reg_143436) & ~(7'd112 == add_ln1116_14_reg_143436) & ~(7'd30 == add_ln1116_14_reg_143436) & ~(7'd86 == add_ln1116_14_reg_143436) & ~(7'd32 == add_ln1116_14_reg_143436) & ~(7'd110 == add_ln1116_14_reg_143436) & ~(7'd34 == add_ln1116_14_reg_143436) & ~(7'd72 == add_ln1116_14_reg_143436) & ~(7'd36 == add_ln1116_14_reg_143436) & ~(7'd108 == add_ln1116_14_reg_143436) & ~(7'd38 == add_ln1116_14_reg_143436) & ~(7'd90 == add_ln1116_14_reg_143436) & ~(7'd40 == add_ln1116_14_reg_143436) & ~(7'd106 == add_ln1116_14_reg_143436) & ~(7'd42 == add_ln1116_14_reg_143436) & ~(7'd74 == add_ln1116_14_reg_143436) & ~(7'd44 == add_ln1116_14_reg_143436) & ~(7'd104 == add_ln1116_14_reg_143436) & ~(7'd46 == add_ln1116_14_reg_143436) & ~(7'd82 == add_ln1116_14_reg_143436) & ~(7'd48 == add_ln1116_14_reg_143436) & ~(7'd102 == add_ln1116_14_reg_143436) & ~(7'd50 == add_ln1116_14_reg_143436) & ~(7'd76 == add_ln1116_14_reg_143436) & ~(7'd52 == add_ln1116_14_reg_143436) & ~(7'd100 == add_ln1116_14_reg_143436) & ~(7'd54 == add_ln1116_14_reg_143436) & ~(7'd88 == add_ln1116_14_reg_143436) & ~(7'd56 == add_ln1116_14_reg_143436) & ~(7'd98 == add_ln1116_14_reg_143436) & ~(7'd58 == add_ln1116_14_reg_143436) & ~(7'd78 == add_ln1116_14_reg_143436) & ~(7'd60 == add_ln1116_14_reg_143436) & ~(7'd96 == add_ln1116_14_reg_143436) & ~(7'd62 == add_ln1116_14_reg_143436) & ~(7'd84 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | (~(7'd0 == add_ln1116_9_reg_142942) & ~(7'd126 == add_ln1116_9_reg_142942) & ~(7'd2 == add_ln1116_9_reg_142942) & ~(7'd64 == add_ln1116_9_reg_142942) & ~(7'd4 == add_ln1116_9_reg_142942) & ~(7'd124 == add_ln1116_9_reg_142942) & ~(7'd6 == add_ln1116_9_reg_142942) & ~(7'd94 == add_ln1116_9_reg_142942) & ~(7'd8 == add_ln1116_9_reg_142942) & ~(7'd122 == add_ln1116_9_reg_142942) & ~(7'd10 == add_ln1116_9_reg_142942) & ~(7'd66 == add_ln1116_9_reg_142942) & ~(7'd12 == add_ln1116_9_reg_142942) & ~(7'd120 == add_ln1116_9_reg_142942) & ~(7'd14 == add_ln1116_9_reg_142942) & ~(7'd80 == add_ln1116_9_reg_142942) & ~(7'd16 == add_ln1116_9_reg_142942) & ~(7'd118 == add_ln1116_9_reg_142942) & ~(7'd18 == add_ln1116_9_reg_142942) & ~(7'd68 == add_ln1116_9_reg_142942) & ~(7'd20 == add_ln1116_9_reg_142942) & ~(7'd116 == add_ln1116_9_reg_142942) & ~(7'd22 == add_ln1116_9_reg_142942) & ~(7'd92 == add_ln1116_9_reg_142942) & ~(7'd24 == add_ln1116_9_reg_142942) & ~(7'd114 == add_ln1116_9_reg_142942) & ~(7'd26 == add_ln1116_9_reg_142942) & ~(7'd70 == add_ln1116_9_reg_142942) & ~(7'd28 == add_ln1116_9_reg_142942) & ~(7'd112 == add_ln1116_9_reg_142942) & ~(7'd30 == add_ln1116_9_reg_142942) & ~(7'd86 == add_ln1116_9_reg_142942) & ~(7'd32 == add_ln1116_9_reg_142942) & ~(7'd110 == add_ln1116_9_reg_142942) & ~(7'd34 == add_ln1116_9_reg_142942) & ~(7'd72 == add_ln1116_9_reg_142942) & ~(7'd36 == add_ln1116_9_reg_142942) & ~(7'd108 == add_ln1116_9_reg_142942) & ~(7'd38 == add_ln1116_9_reg_142942) & ~(7'd90 == add_ln1116_9_reg_142942) & ~(7'd40 == add_ln1116_9_reg_142942) & ~(7'd106 == add_ln1116_9_reg_142942) & ~(7'd42 == add_ln1116_9_reg_142942) & ~(7'd74 == add_ln1116_9_reg_142942) & ~(7'd44 == add_ln1116_9_reg_142942) & ~(7'd104 == add_ln1116_9_reg_142942) & ~(7'd46 == add_ln1116_9_reg_142942) & ~(7'd82 == add_ln1116_9_reg_142942) & ~(7'd48 == add_ln1116_9_reg_142942) & ~(7'd102 == add_ln1116_9_reg_142942) & ~(7'd50 == add_ln1116_9_reg_142942) & ~(7'd76 == add_ln1116_9_reg_142942) & ~(7'd52 == add_ln1116_9_reg_142942) & ~(7'd100 == add_ln1116_9_reg_142942) & ~(7'd54 == add_ln1116_9_reg_142942) & ~(7'd88 == add_ln1116_9_reg_142942) & ~(7'd56 == add_ln1116_9_reg_142942) & ~(7'd98 == add_ln1116_9_reg_142942) & ~(7'd58 == add_ln1116_9_reg_142942) & ~(7'd78 == add_ln1116_9_reg_142942) & ~(7'd60 == add_ln1116_9_reg_142942) & ~(7'd96 == add_ln1116_9_reg_142942) & ~(7'd62 == add_ln1116_9_reg_142942) & ~(7'd84 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | (~(7'd0 == add_ln1116_3_reg_142532) & ~(7'd126 == add_ln1116_3_reg_142532) & ~(7'd2 == add_ln1116_3_reg_142532) & ~(7'd64 == add_ln1116_3_reg_142532) & ~(7'd4 == add_ln1116_3_reg_142532) & ~(7'd124 == add_ln1116_3_reg_142532) & ~(7'd6 == add_ln1116_3_reg_142532) & ~(7'd94 == add_ln1116_3_reg_142532) & ~(7'd8 == add_ln1116_3_reg_142532) & ~(7'd122 == add_ln1116_3_reg_142532) & ~(7'd10 == add_ln1116_3_reg_142532) & ~(7'd66 == add_ln1116_3_reg_142532) & ~(7'd12 == add_ln1116_3_reg_142532) & ~(7'd120 == add_ln1116_3_reg_142532) & ~(7'd14 == add_ln1116_3_reg_142532) & ~(7'd80 == add_ln1116_3_reg_142532) & ~(7'd16 == add_ln1116_3_reg_142532) & ~(7'd118 == add_ln1116_3_reg_142532) & ~(7'd18 == add_ln1116_3_reg_142532) & ~(7'd68 == add_ln1116_3_reg_142532) & ~(7'd20 == add_ln1116_3_reg_142532) & ~(7'd116 == add_ln1116_3_reg_142532) & ~(7'd22 == add_ln1116_3_reg_142532) & ~(7'd92 == add_ln1116_3_reg_142532) & ~(7'd24 == add_ln1116_3_reg_142532) & ~(7'd114 == add_ln1116_3_reg_142532) & ~(7'd26 == add_ln1116_3_reg_142532) & ~(7'd70 == add_ln1116_3_reg_142532) & ~(7'd28 == add_ln1116_3_reg_142532) & ~(7'd112 == add_ln1116_3_reg_142532) & ~(7'd30 == add_ln1116_3_reg_142532) & ~(7'd86 == add_ln1116_3_reg_142532) & ~(7'd32 == add_ln1116_3_reg_142532) & ~(7'd110 == add_ln1116_3_reg_142532) & ~(7'd34 == add_ln1116_3_reg_142532) & ~(7'd72 == add_ln1116_3_reg_142532) & ~(7'd36 == add_ln1116_3_reg_142532) & ~(7'd108 == add_ln1116_3_reg_142532) & ~(7'd38 == add_ln1116_3_reg_142532) & ~(7'd90 == add_ln1116_3_reg_142532) & ~(7'd40 == add_ln1116_3_reg_142532) & ~(7'd106 == add_ln1116_3_reg_142532) & ~(7'd42 == add_ln1116_3_reg_142532) & ~(7'd74 == add_ln1116_3_reg_142532) & ~(7'd44 == add_ln1116_3_reg_142532) & ~(7'd104 == add_ln1116_3_reg_142532) & ~(7'd46 == add_ln1116_3_reg_142532) & ~(7'd82 == add_ln1116_3_reg_142532) & ~(7'd48 == add_ln1116_3_reg_142532) & ~(7'd102 == add_ln1116_3_reg_142532) & ~(7'd50 == add_ln1116_3_reg_142532) & ~(7'd76 == add_ln1116_3_reg_142532) & ~(7'd52 == add_ln1116_3_reg_142532) & ~(7'd100 == add_ln1116_3_reg_142532) & ~(7'd54 == add_ln1116_3_reg_142532) & ~(7'd88 == add_ln1116_3_reg_142532) & ~(7'd56 == add_ln1116_3_reg_142532) & ~(7'd98 == add_ln1116_3_reg_142532) & ~(7'd58 == add_ln1116_3_reg_142532) & ~(7'd78 == add_ln1116_3_reg_142532) & ~(7'd60 == add_ln1116_3_reg_142532) & ~(7'd96 == add_ln1116_3_reg_142532) & ~(7'd62 == add_ln1116_3_reg_142532) & ~(7'd84 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | (~(7'd0 == add_ln1116_18_reg_140281) & ~(7'd126 == add_ln1116_18_reg_140281) & ~(7'd2 == add_ln1116_18_reg_140281) & ~(7'd64 == add_ln1116_18_reg_140281) & ~(7'd4 == add_ln1116_18_reg_140281) & ~(7'd124 == add_ln1116_18_reg_140281) & ~(7'd6 == add_ln1116_18_reg_140281) & ~(7'd94 == add_ln1116_18_reg_140281) & ~(7'd8 == add_ln1116_18_reg_140281) & ~(7'd122 == add_ln1116_18_reg_140281) & ~(7'd10 == add_ln1116_18_reg_140281) & ~(7'd66 == add_ln1116_18_reg_140281) & ~(7'd12 == add_ln1116_18_reg_140281) & ~(7'd120 == add_ln1116_18_reg_140281) & ~(7'd14 == add_ln1116_18_reg_140281) & ~(7'd80 == add_ln1116_18_reg_140281) & ~(7'd16 == add_ln1116_18_reg_140281) & ~(7'd118 == add_ln1116_18_reg_140281) & ~(7'd18 == add_ln1116_18_reg_140281) & ~(7'd68 == add_ln1116_18_reg_140281) & ~(7'd20 == add_ln1116_18_reg_140281) & ~(7'd116 == add_ln1116_18_reg_140281) & ~(7'd22 == add_ln1116_18_reg_140281) & ~(7'd92 == add_ln1116_18_reg_140281) & ~(7'd24 == add_ln1116_18_reg_140281) & ~(7'd114 == add_ln1116_18_reg_140281) & ~(7'd26 == add_ln1116_18_reg_140281) & ~(7'd70 == add_ln1116_18_reg_140281) & ~(7'd28 == add_ln1116_18_reg_140281) & ~(7'd112 == add_ln1116_18_reg_140281) & ~(7'd30 == add_ln1116_18_reg_140281) & ~(7'd86 == add_ln1116_18_reg_140281) & ~(7'd32 == add_ln1116_18_reg_140281) & ~(7'd110 == add_ln1116_18_reg_140281) & ~(7'd34 == add_ln1116_18_reg_140281) & ~(7'd72 == add_ln1116_18_reg_140281) & ~(7'd36 == add_ln1116_18_reg_140281) & ~(7'd108 == add_ln1116_18_reg_140281) & ~(7'd38 == add_ln1116_18_reg_140281) & ~(7'd90 == add_ln1116_18_reg_140281) & ~(7'd40 == add_ln1116_18_reg_140281) & ~(7'd106 == add_ln1116_18_reg_140281) & ~(7'd42 == add_ln1116_18_reg_140281) & ~(7'd74 == add_ln1116_18_reg_140281) & ~(7'd44 == add_ln1116_18_reg_140281) & ~(7'd104 == add_ln1116_18_reg_140281) & ~(7'd46 == add_ln1116_18_reg_140281) & ~(7'd82 == add_ln1116_18_reg_140281) & ~(7'd48 == add_ln1116_18_reg_140281) & ~(7'd102 == add_ln1116_18_reg_140281) & ~(7'd50 == add_ln1116_18_reg_140281) & ~(7'd76 == add_ln1116_18_reg_140281) & ~(7'd52 == add_ln1116_18_reg_140281) & ~(7'd100 == add_ln1116_18_reg_140281) & ~(7'd54 == add_ln1116_18_reg_140281) & ~(7'd88 == add_ln1116_18_reg_140281) & ~(7'd56 == add_ln1116_18_reg_140281) & ~(7'd98 == add_ln1116_18_reg_140281) & ~(7'd58 == add_ln1116_18_reg_140281) & ~(7'd78 == add_ln1116_18_reg_140281) & ~(7'd60 == add_ln1116_18_reg_140281) & ~(7'd96 == add_ln1116_18_reg_140281) & ~(7'd62 == add_ln1116_18_reg_140281) & ~(7'd84 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | (~(7'd0 == add_ln1116_10_reg_139883) & ~(7'd126 == add_ln1116_10_reg_139883) & ~(7'd2 == add_ln1116_10_reg_139883) & ~(7'd64 == add_ln1116_10_reg_139883) & ~(7'd4 == add_ln1116_10_reg_139883) & ~(7'd124 == add_ln1116_10_reg_139883) & ~(7'd6 == add_ln1116_10_reg_139883) & ~(7'd94 == add_ln1116_10_reg_139883) & ~(7'd8 == add_ln1116_10_reg_139883) & ~(7'd122 == add_ln1116_10_reg_139883) & ~(7'd10 == add_ln1116_10_reg_139883) & ~(7'd66 == add_ln1116_10_reg_139883) & ~(7'd12 == add_ln1116_10_reg_139883) & ~(7'd120 == add_ln1116_10_reg_139883) & ~(7'd14 == add_ln1116_10_reg_139883) & ~(7'd80 == add_ln1116_10_reg_139883) & ~(7'd16 == add_ln1116_10_reg_139883) & ~(7'd118 == add_ln1116_10_reg_139883) & ~(7'd18 == add_ln1116_10_reg_139883) & ~(7'd68 == add_ln1116_10_reg_139883) & ~(7'd20 == add_ln1116_10_reg_139883) & ~(7'd116 == add_ln1116_10_reg_139883) & ~(7'd22 == add_ln1116_10_reg_139883) & ~(7'd92 == add_ln1116_10_reg_139883) & ~(7'd24 == add_ln1116_10_reg_139883) & ~(7'd114 == add_ln1116_10_reg_139883) & ~(7'd26 == add_ln1116_10_reg_139883) & ~(7'd70 == add_ln1116_10_reg_139883) & ~(7'd28 == add_ln1116_10_reg_139883) & ~(7'd112 == add_ln1116_10_reg_139883) & ~(7'd30 == add_ln1116_10_reg_139883) & ~(7'd86 == add_ln1116_10_reg_139883) & ~(7'd32 == add_ln1116_10_reg_139883) & ~(7'd110 == add_ln1116_10_reg_139883) & ~(7'd34 == add_ln1116_10_reg_139883) & ~(7'd72 == add_ln1116_10_reg_139883) & ~(7'd36 == add_ln1116_10_reg_139883) & ~(7'd108 == add_ln1116_10_reg_139883) & ~(7'd38 == add_ln1116_10_reg_139883) & ~(7'd90 == add_ln1116_10_reg_139883) & ~(7'd40 == add_ln1116_10_reg_139883) & ~(7'd106 == add_ln1116_10_reg_139883) & ~(7'd42 == add_ln1116_10_reg_139883) & ~(7'd74 == add_ln1116_10_reg_139883) & ~(7'd44 == add_ln1116_10_reg_139883) & ~(7'd104 == add_ln1116_10_reg_139883) & ~(7'd46 == add_ln1116_10_reg_139883) & ~(7'd82 == add_ln1116_10_reg_139883) & ~(7'd48 == add_ln1116_10_reg_139883) & ~(7'd102 == add_ln1116_10_reg_139883) & ~(7'd50 == add_ln1116_10_reg_139883) & ~(7'd76 == add_ln1116_10_reg_139883) & ~(7'd52 == add_ln1116_10_reg_139883) & ~(7'd100 == add_ln1116_10_reg_139883) & ~(7'd54 == add_ln1116_10_reg_139883) & ~(7'd88 == add_ln1116_10_reg_139883) & ~(7'd56 == add_ln1116_10_reg_139883) & ~(7'd98 == add_ln1116_10_reg_139883) & ~(7'd58 == add_ln1116_10_reg_139883) & ~(7'd78 == add_ln1116_10_reg_139883) & ~(7'd60 == add_ln1116_10_reg_139883) & ~(7'd96 == add_ln1116_10_reg_139883) & ~(7'd62 == add_ln1116_10_reg_139883) & ~(7'd84 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | (~(7'd0 == add_ln1116_5_reg_139399) & ~(7'd126 == add_ln1116_5_reg_139399) & ~(7'd2 == add_ln1116_5_reg_139399) & ~(7'd64 == add_ln1116_5_reg_139399) & ~(7'd4 == add_ln1116_5_reg_139399) & ~(7'd124 == add_ln1116_5_reg_139399) & ~(7'd6 == add_ln1116_5_reg_139399) & ~(7'd94 == add_ln1116_5_reg_139399) & ~(7'd8 == add_ln1116_5_reg_139399) & ~(7'd122 == add_ln1116_5_reg_139399) & ~(7'd10 == add_ln1116_5_reg_139399) & ~(7'd66 == add_ln1116_5_reg_139399) & ~(7'd12 == add_ln1116_5_reg_139399) & ~(7'd120 == add_ln1116_5_reg_139399) & ~(7'd14 == add_ln1116_5_reg_139399) & ~(7'd80 == add_ln1116_5_reg_139399) & ~(7'd16 == add_ln1116_5_reg_139399) & ~(7'd118 == add_ln1116_5_reg_139399) & ~(7'd18 == add_ln1116_5_reg_139399) & ~(7'd68 == add_ln1116_5_reg_139399) & ~(7'd20 == add_ln1116_5_reg_139399) & ~(7'd116 == add_ln1116_5_reg_139399) & ~(7'd22 == add_ln1116_5_reg_139399) & ~(7'd92 == add_ln1116_5_reg_139399) & ~(7'd24 == add_ln1116_5_reg_139399) & ~(7'd114 == add_ln1116_5_reg_139399) & ~(7'd26 == add_ln1116_5_reg_139399) & ~(7'd70 == add_ln1116_5_reg_139399) & ~(7'd28 == add_ln1116_5_reg_139399) & ~(7'd112 == add_ln1116_5_reg_139399) & ~(7'd30 == add_ln1116_5_reg_139399) & ~(7'd86 == add_ln1116_5_reg_139399) & ~(7'd32 == add_ln1116_5_reg_139399) & ~(7'd110 == add_ln1116_5_reg_139399) & ~(7'd34 == add_ln1116_5_reg_139399) & ~(7'd72 == add_ln1116_5_reg_139399) & ~(7'd36 == add_ln1116_5_reg_139399) & ~(7'd108 == add_ln1116_5_reg_139399) & ~(7'd38 == add_ln1116_5_reg_139399) & ~(7'd90 == add_ln1116_5_reg_139399) & ~(7'd40 == add_ln1116_5_reg_139399) & ~(7'd106 == add_ln1116_5_reg_139399) & ~(7'd42 == add_ln1116_5_reg_139399) & ~(7'd74 == add_ln1116_5_reg_139399) & ~(7'd44 == add_ln1116_5_reg_139399) & ~(7'd104 == add_ln1116_5_reg_139399) & ~(7'd46 == add_ln1116_5_reg_139399) & ~(7'd82 == add_ln1116_5_reg_139399) & ~(7'd48 == add_ln1116_5_reg_139399) & ~(7'd102 == add_ln1116_5_reg_139399) & ~(7'd50 == add_ln1116_5_reg_139399) & ~(7'd76 == add_ln1116_5_reg_139399) & ~(7'd52 == add_ln1116_5_reg_139399) & ~(7'd100 == add_ln1116_5_reg_139399) & ~(7'd54 == add_ln1116_5_reg_139399) & ~(7'd88 == add_ln1116_5_reg_139399) & ~(7'd56 == add_ln1116_5_reg_139399) & ~(7'd98 == add_ln1116_5_reg_139399) & ~(7'd58 == add_ln1116_5_reg_139399) & ~(7'd78 == add_ln1116_5_reg_139399) & ~(7'd60 == add_ln1116_5_reg_139399) & ~(7'd96 == add_ln1116_5_reg_139399) & ~(7'd62 == add_ln1116_5_reg_139399) & ~(7'd84 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | (~(7'd0 == add_ln1116_1_reg_138989) & ~(7'd126 == add_ln1116_1_reg_138989) & ~(7'd2 == add_ln1116_1_reg_138989) & ~(7'd64 == add_ln1116_1_reg_138989) & ~(7'd4 == add_ln1116_1_reg_138989) & ~(7'd124 == add_ln1116_1_reg_138989) & ~(7'd6 == add_ln1116_1_reg_138989) & ~(7'd94 == add_ln1116_1_reg_138989) & ~(7'd8 == add_ln1116_1_reg_138989) & ~(7'd122 == add_ln1116_1_reg_138989) & ~(7'd10 == add_ln1116_1_reg_138989) & ~(7'd66 == add_ln1116_1_reg_138989) & ~(7'd12 == add_ln1116_1_reg_138989) & ~(7'd120 == add_ln1116_1_reg_138989) & ~(7'd14 == add_ln1116_1_reg_138989) & ~(7'd80 == add_ln1116_1_reg_138989) & ~(7'd16 == add_ln1116_1_reg_138989) & ~(7'd118 == add_ln1116_1_reg_138989) & ~(7'd18 == add_ln1116_1_reg_138989) & ~(7'd68 == add_ln1116_1_reg_138989) & ~(7'd20 == add_ln1116_1_reg_138989) & ~(7'd116 == add_ln1116_1_reg_138989) & ~(7'd22 == add_ln1116_1_reg_138989) & ~(7'd92 == add_ln1116_1_reg_138989) & ~(7'd24 == add_ln1116_1_reg_138989) & ~(7'd114 == add_ln1116_1_reg_138989) & ~(7'd26 == add_ln1116_1_reg_138989) & ~(7'd70 == add_ln1116_1_reg_138989) & ~(7'd28 == add_ln1116_1_reg_138989) & ~(7'd112 == add_ln1116_1_reg_138989) & ~(7'd30 == add_ln1116_1_reg_138989) & ~(7'd86 == add_ln1116_1_reg_138989) & ~(7'd32 == add_ln1116_1_reg_138989) & ~(7'd110 == add_ln1116_1_reg_138989) & ~(7'd34 == add_ln1116_1_reg_138989) & ~(7'd72 == add_ln1116_1_reg_138989) & ~(7'd36 == add_ln1116_1_reg_138989) & ~(7'd108 == add_ln1116_1_reg_138989) & ~(7'd38 == add_ln1116_1_reg_138989) & ~(7'd90 == add_ln1116_1_reg_138989) & ~(7'd40 == add_ln1116_1_reg_138989) & ~(7'd106 == add_ln1116_1_reg_138989) & ~(7'd42 == add_ln1116_1_reg_138989) & ~(7'd74 == add_ln1116_1_reg_138989) & ~(7'd44 == add_ln1116_1_reg_138989) & ~(7'd104 == add_ln1116_1_reg_138989) & ~(7'd46 == add_ln1116_1_reg_138989) & ~(7'd82 == add_ln1116_1_reg_138989) & ~(7'd48 == add_ln1116_1_reg_138989) & ~(7'd102 == add_ln1116_1_reg_138989) & ~(7'd50 == add_ln1116_1_reg_138989) & ~(7'd76 == add_ln1116_1_reg_138989) & ~(7'd52 == add_ln1116_1_reg_138989) & ~(7'd100 == add_ln1116_1_reg_138989) & ~(7'd54 == add_ln1116_1_reg_138989) & ~(7'd88 == add_ln1116_1_reg_138989) & ~(7'd56 == add_ln1116_1_reg_138989) & ~(7'd98 == add_ln1116_1_reg_138989) & ~(7'd58 == add_ln1116_1_reg_138989) & ~(7'd78 == add_ln1116_1_reg_138989) & ~(7'd60 == add_ln1116_1_reg_138989) & ~(7'd96 == add_ln1116_1_reg_138989) & ~(7'd62 == add_ln1116_1_reg_138989) & ~(7'd84 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | (~(7'd0 == add_ln1116_19_reg_136674) & ~(7'd126 == add_ln1116_19_reg_136674) & ~(7'd2 == add_ln1116_19_reg_136674) & ~(7'd64 == add_ln1116_19_reg_136674) & ~(7'd4 == add_ln1116_19_reg_136674) & ~(7'd124 == add_ln1116_19_reg_136674) & ~(7'd6 == add_ln1116_19_reg_136674) & ~(7'd94 == add_ln1116_19_reg_136674) & ~(7'd8 == add_ln1116_19_reg_136674) & ~(7'd122 == add_ln1116_19_reg_136674) & ~(7'd10 == add_ln1116_19_reg_136674) & ~(7'd66 == add_ln1116_19_reg_136674) & ~(7'd12 == add_ln1116_19_reg_136674) & ~(7'd120 == add_ln1116_19_reg_136674) & ~(7'd14 == add_ln1116_19_reg_136674) & ~(7'd80 == add_ln1116_19_reg_136674) & ~(7'd16 == add_ln1116_19_reg_136674) & ~(7'd118 == add_ln1116_19_reg_136674) & ~(7'd18 == add_ln1116_19_reg_136674) & ~(7'd68 == add_ln1116_19_reg_136674) & ~(7'd20 == add_ln1116_19_reg_136674) & ~(7'd116 == add_ln1116_19_reg_136674) & ~(7'd22 == add_ln1116_19_reg_136674) & ~(7'd92 == add_ln1116_19_reg_136674) & ~(7'd24 == add_ln1116_19_reg_136674) & ~(7'd114 == add_ln1116_19_reg_136674) & ~(7'd26 == add_ln1116_19_reg_136674) & ~(7'd70 == add_ln1116_19_reg_136674) & ~(7'd28 == add_ln1116_19_reg_136674) & ~(7'd112 == add_ln1116_19_reg_136674) & ~(7'd30 == add_ln1116_19_reg_136674) & ~(7'd86 == add_ln1116_19_reg_136674) & ~(7'd32 == add_ln1116_19_reg_136674) & ~(7'd110 == add_ln1116_19_reg_136674) & ~(7'd34 == add_ln1116_19_reg_136674) & ~(7'd72 == add_ln1116_19_reg_136674) & ~(7'd36 == add_ln1116_19_reg_136674) & ~(7'd108 == add_ln1116_19_reg_136674) & ~(7'd38 == add_ln1116_19_reg_136674) & ~(7'd90 == add_ln1116_19_reg_136674) & ~(7'd40 == add_ln1116_19_reg_136674) & ~(7'd106 == add_ln1116_19_reg_136674) & ~(7'd42 == add_ln1116_19_reg_136674) & ~(7'd74 == add_ln1116_19_reg_136674) & ~(7'd44 == add_ln1116_19_reg_136674) & ~(7'd104 == add_ln1116_19_reg_136674) & ~(7'd46 == add_ln1116_19_reg_136674) & ~(7'd82 == add_ln1116_19_reg_136674) & ~(7'd48 == add_ln1116_19_reg_136674) & ~(7'd102 == add_ln1116_19_reg_136674) & ~(7'd50 == add_ln1116_19_reg_136674) & ~(7'd76 == add_ln1116_19_reg_136674) & ~(7'd52 == add_ln1116_19_reg_136674) & ~(7'd100 == add_ln1116_19_reg_136674) & ~(7'd54 == add_ln1116_19_reg_136674) & ~(7'd88 == add_ln1116_19_reg_136674) & ~(7'd56 == add_ln1116_19_reg_136674) & ~(7'd98 == add_ln1116_19_reg_136674) & ~(7'd58 == add_ln1116_19_reg_136674) & ~(7'd78 == add_ln1116_19_reg_136674) & ~(7'd60 == add_ln1116_19_reg_136674) & ~(7'd96 == add_ln1116_19_reg_136674) & ~(7'd62 == add_ln1116_19_reg_136674) & ~(7'd84 == add_ln1116_19_reg_136674) & (ap_ST_fsm_state841 == ap_CS_fsm)) | (~(7'd0 == add_ln1116_11_reg_136276) & ~(7'd126 == add_ln1116_11_reg_136276) & ~(7'd2 == add_ln1116_11_reg_136276) & ~(7'd64 == add_ln1116_11_reg_136276) & ~(7'd4 == add_ln1116_11_reg_136276) & ~(7'd124 == add_ln1116_11_reg_136276) & ~(7'd6 == add_ln1116_11_reg_136276) & ~(7'd94 == add_ln1116_11_reg_136276) & ~(7'd8 == add_ln1116_11_reg_136276) & ~(7'd122 == add_ln1116_11_reg_136276) & ~(7'd10 == add_ln1116_11_reg_136276) & ~(7'd66 == add_ln1116_11_reg_136276) & ~(7'd12 == add_ln1116_11_reg_136276) & ~(7'd120 == add_ln1116_11_reg_136276) & ~(7'd14 == add_ln1116_11_reg_136276) & ~(7'd80 == add_ln1116_11_reg_136276) & ~(7'd16 == add_ln1116_11_reg_136276) & ~(7'd118 == add_ln1116_11_reg_136276) & ~(7'd18 == add_ln1116_11_reg_136276) & ~(7'd68 == add_ln1116_11_reg_136276) & ~(7'd20 == add_ln1116_11_reg_136276) & ~(7'd116 == add_ln1116_11_reg_136276) & ~(7'd22 == add_ln1116_11_reg_136276) & ~(7'd92 == add_ln1116_11_reg_136276) & ~(7'd24 == add_ln1116_11_reg_136276) & ~(7'd114 == add_ln1116_11_reg_136276) & ~(7'd26 == add_ln1116_11_reg_136276) & ~(7'd70 == add_ln1116_11_reg_136276) & ~(7'd28 == add_ln1116_11_reg_136276) & ~(7'd112 == add_ln1116_11_reg_136276) & ~(7'd30 == add_ln1116_11_reg_136276) & ~(7'd86 == add_ln1116_11_reg_136276) & ~(7'd32 == add_ln1116_11_reg_136276) & ~(7'd110 == add_ln1116_11_reg_136276) & ~(7'd34 == add_ln1116_11_reg_136276) & ~(7'd72 == add_ln1116_11_reg_136276) & ~(7'd36 == add_ln1116_11_reg_136276) & ~(7'd108 == add_ln1116_11_reg_136276) & ~(7'd38 == add_ln1116_11_reg_136276) & ~(7'd90 == add_ln1116_11_reg_136276) & ~(7'd40 == add_ln1116_11_reg_136276) & ~(7'd106 == add_ln1116_11_reg_136276) & ~(7'd42 == add_ln1116_11_reg_136276) & ~(7'd74 == add_ln1116_11_reg_136276) & ~(7'd44 == add_ln1116_11_reg_136276) & ~(7'd104 == add_ln1116_11_reg_136276) & ~(7'd46 == add_ln1116_11_reg_136276) & ~(7'd82 == add_ln1116_11_reg_136276) & ~(7'd48 == add_ln1116_11_reg_136276) & ~(7'd102 == add_ln1116_11_reg_136276) & ~(7'd50 == add_ln1116_11_reg_136276) & ~(7'd76 == add_ln1116_11_reg_136276) & ~(7'd52 == add_ln1116_11_reg_136276) & ~(7'd100 == add_ln1116_11_reg_136276) & ~(7'd54 == add_ln1116_11_reg_136276) & ~(7'd88 == add_ln1116_11_reg_136276) & ~(7'd56 == add_ln1116_11_reg_136276) & ~(7'd98 == add_ln1116_11_reg_136276) & ~(7'd58 == add_ln1116_11_reg_136276) & ~(7'd78 == add_ln1116_11_reg_136276) & ~(7'd60 == add_ln1116_11_reg_136276) & ~(7'd96 == add_ln1116_11_reg_136276) & ~(7'd62 == add_ln1116_11_reg_136276) & ~(7'd84 == add_ln1116_11_reg_136276) & (ap_ST_fsm_state766 == ap_CS_fsm)) | (~(7'd0 == add_ln1116_6_reg_135778) & ~(7'd126 == add_ln1116_6_reg_135778) & ~(7'd2 == add_ln1116_6_reg_135778) & ~(7'd64 == add_ln1116_6_reg_135778) & ~(7'd4 == add_ln1116_6_reg_135778) & ~(7'd124 == add_ln1116_6_reg_135778) & ~(7'd6 == add_ln1116_6_reg_135778) & ~(7'd94 == add_ln1116_6_reg_135778) & ~(7'd8 == add_ln1116_6_reg_135778) & ~(7'd122 == add_ln1116_6_reg_135778) & ~(7'd10 == add_ln1116_6_reg_135778) & ~(7'd66 == add_ln1116_6_reg_135778) & ~(7'd12 == add_ln1116_6_reg_135778) & ~(7'd120 == add_ln1116_6_reg_135778) & ~(7'd14 == add_ln1116_6_reg_135778) & ~(7'd80 == add_ln1116_6_reg_135778) & ~(7'd16 == add_ln1116_6_reg_135778) & ~(7'd118 == add_ln1116_6_reg_135778) & ~(7'd18 == add_ln1116_6_reg_135778) & ~(7'd68 == add_ln1116_6_reg_135778) & ~(7'd20 == add_ln1116_6_reg_135778) & ~(7'd116 == add_ln1116_6_reg_135778) & ~(7'd22 == add_ln1116_6_reg_135778) & ~(7'd92 == add_ln1116_6_reg_135778) & ~(7'd24 == add_ln1116_6_reg_135778) & ~(7'd114 == add_ln1116_6_reg_135778) & ~(7'd26 == add_ln1116_6_reg_135778) & ~(7'd70 == add_ln1116_6_reg_135778) & ~(7'd28 == add_ln1116_6_reg_135778) & ~(7'd112 == add_ln1116_6_reg_135778) & ~(7'd30 == add_ln1116_6_reg_135778) & ~(7'd86 == add_ln1116_6_reg_135778) & ~(7'd32 == add_ln1116_6_reg_135778) & ~(7'd110 == add_ln1116_6_reg_135778) & ~(7'd34 == add_ln1116_6_reg_135778) & ~(7'd72 == add_ln1116_6_reg_135778) & ~(7'd36 == add_ln1116_6_reg_135778) & ~(7'd108 == add_ln1116_6_reg_135778) & ~(7'd38 == add_ln1116_6_reg_135778) & ~(7'd90 == add_ln1116_6_reg_135778) & ~(7'd40 == add_ln1116_6_reg_135778) & ~(7'd106 == add_ln1116_6_reg_135778) & ~(7'd42 == add_ln1116_6_reg_135778) & ~(7'd74 == add_ln1116_6_reg_135778) & ~(7'd44 == add_ln1116_6_reg_135778) & ~(7'd104 == add_ln1116_6_reg_135778) & ~(7'd46 == add_ln1116_6_reg_135778) & ~(7'd82 == add_ln1116_6_reg_135778) & ~(7'd48 == add_ln1116_6_reg_135778) & ~(7'd102 == add_ln1116_6_reg_135778) & ~(7'd50 == add_ln1116_6_reg_135778) & ~(7'd76 == add_ln1116_6_reg_135778) & ~(7'd52 == add_ln1116_6_reg_135778) & ~(7'd100 == add_ln1116_6_reg_135778) & ~(7'd54 == add_ln1116_6_reg_135778) & ~(7'd88 == add_ln1116_6_reg_135778) & ~(7'd56 == add_ln1116_6_reg_135778) & ~(7'd98 == add_ln1116_6_reg_135778) & ~(7'd58 == add_ln1116_6_reg_135778) & ~(7'd78 == add_ln1116_6_reg_135778) & ~(7'd60 == add_ln1116_6_reg_135778) & ~(7'd96 == add_ln1116_6_reg_135778) & ~(7'd62 == add_ln1116_6_reg_135778) & ~(7'd84 == add_ln1116_6_reg_135778) & (ap_ST_fsm_state689 == ap_CS_fsm)) | (~(7'd0 == add_ln1116_2_reg_135368) & ~(7'd126 == add_ln1116_2_reg_135368) & ~(7'd2 == add_ln1116_2_reg_135368) & ~(7'd64 == add_ln1116_2_reg_135368) & ~(7'd4 == add_ln1116_2_reg_135368) & ~(7'd124 == add_ln1116_2_reg_135368) & ~(7'd6 == add_ln1116_2_reg_135368) & ~(7'd94 == add_ln1116_2_reg_135368) & ~(7'd8 == add_ln1116_2_reg_135368) & ~(7'd122 == add_ln1116_2_reg_135368) & ~(7'd10 == add_ln1116_2_reg_135368) & ~(7'd66 == add_ln1116_2_reg_135368) & ~(7'd12 == add_ln1116_2_reg_135368) & ~(7'd120 == add_ln1116_2_reg_135368) & ~(7'd14 == add_ln1116_2_reg_135368) & ~(7'd80 == add_ln1116_2_reg_135368) & ~(7'd16 == add_ln1116_2_reg_135368) & ~(7'd118 == add_ln1116_2_reg_135368) & ~(7'd18 == add_ln1116_2_reg_135368) & ~(7'd68 == add_ln1116_2_reg_135368) & ~(7'd20 == add_ln1116_2_reg_135368) & ~(7'd116 == add_ln1116_2_reg_135368) & ~(7'd22 == add_ln1116_2_reg_135368) & ~(7'd92 == add_ln1116_2_reg_135368) & ~(7'd24 == add_ln1116_2_reg_135368) & ~(7'd114 == add_ln1116_2_reg_135368) & ~(7'd26 == add_ln1116_2_reg_135368) & ~(7'd70 == add_ln1116_2_reg_135368) & ~(7'd28 == add_ln1116_2_reg_135368) & ~(7'd112 == add_ln1116_2_reg_135368) & ~(7'd30 == add_ln1116_2_reg_135368) & ~(7'd86 == add_ln1116_2_reg_135368) & ~(7'd32 == add_ln1116_2_reg_135368) & ~(7'd110 == add_ln1116_2_reg_135368) & ~(7'd34 == add_ln1116_2_reg_135368) & ~(7'd72 == add_ln1116_2_reg_135368) & ~(7'd36 == add_ln1116_2_reg_135368) & ~(7'd108 == add_ln1116_2_reg_135368) & ~(7'd38 == add_ln1116_2_reg_135368) & ~(7'd90 == add_ln1116_2_reg_135368) & ~(7'd40 == add_ln1116_2_reg_135368) & ~(7'd106 == add_ln1116_2_reg_135368) & ~(7'd42 == add_ln1116_2_reg_135368) & ~(7'd74 == add_ln1116_2_reg_135368) & ~(7'd44 == add_ln1116_2_reg_135368) & ~(7'd104 == add_ln1116_2_reg_135368) & ~(7'd46 == add_ln1116_2_reg_135368) & ~(7'd82 == add_ln1116_2_reg_135368) & ~(7'd48 == add_ln1116_2_reg_135368) & ~(7'd102 == add_ln1116_2_reg_135368) & ~(7'd50 == add_ln1116_2_reg_135368) & ~(7'd76 == add_ln1116_2_reg_135368) & ~(7'd52 == add_ln1116_2_reg_135368) & ~(7'd100 == add_ln1116_2_reg_135368) & ~(7'd54 == add_ln1116_2_reg_135368) & ~(7'd88 == add_ln1116_2_reg_135368) & ~(7'd56 == add_ln1116_2_reg_135368) & ~(7'd98 == add_ln1116_2_reg_135368) & ~(7'd58 == add_ln1116_2_reg_135368) & ~(7'd78 == add_ln1116_2_reg_135368) & ~(7'd60 == add_ln1116_2_reg_135368) & ~(7'd96 == add_ln1116_2_reg_135368) & ~(7'd62 == add_ln1116_2_reg_135368) & ~(7'd84 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | (~(7'd0 == add_ln1116_16_reg_133103) & ~(7'd126 == add_ln1116_16_reg_133103) & ~(7'd2 == add_ln1116_16_reg_133103) & ~(7'd64 == add_ln1116_16_reg_133103) & ~(7'd4 == add_ln1116_16_reg_133103) & ~(7'd124 == add_ln1116_16_reg_133103) & ~(7'd6 == add_ln1116_16_reg_133103) & ~(7'd94 == add_ln1116_16_reg_133103) & ~(7'd8 == add_ln1116_16_reg_133103) & ~(7'd122 == add_ln1116_16_reg_133103) & ~(7'd10 == add_ln1116_16_reg_133103) & ~(7'd66 == add_ln1116_16_reg_133103) & ~(7'd12 == add_ln1116_16_reg_133103) & ~(7'd120 == add_ln1116_16_reg_133103) & ~(7'd14 == add_ln1116_16_reg_133103) & ~(7'd80 == add_ln1116_16_reg_133103) & ~(7'd16 == add_ln1116_16_reg_133103) & ~(7'd118 == add_ln1116_16_reg_133103) & ~(7'd18 == add_ln1116_16_reg_133103) & ~(7'd68 == add_ln1116_16_reg_133103) & ~(7'd20 == add_ln1116_16_reg_133103) & ~(7'd116 == add_ln1116_16_reg_133103) & ~(7'd22 == add_ln1116_16_reg_133103) & ~(7'd92 == add_ln1116_16_reg_133103) & ~(7'd24 == add_ln1116_16_reg_133103) & ~(7'd114 == add_ln1116_16_reg_133103) & ~(7'd26 == add_ln1116_16_reg_133103) & ~(7'd70 == add_ln1116_16_reg_133103) & ~(7'd28 == add_ln1116_16_reg_133103) & ~(7'd112 == add_ln1116_16_reg_133103) & ~(7'd30 == add_ln1116_16_reg_133103) & ~(7'd86 == add_ln1116_16_reg_133103) & ~(7'd32 == add_ln1116_16_reg_133103) & ~(7'd110 == add_ln1116_16_reg_133103) & ~(7'd34 == add_ln1116_16_reg_133103) & ~(7'd72 == add_ln1116_16_reg_133103) & ~(7'd36 == add_ln1116_16_reg_133103) & ~(7'd108 == add_ln1116_16_reg_133103) & ~(7'd38 == add_ln1116_16_reg_133103) & ~(7'd90 == add_ln1116_16_reg_133103) & ~(7'd40 == add_ln1116_16_reg_133103) & ~(7'd106 == add_ln1116_16_reg_133103) & ~(7'd42 == add_ln1116_16_reg_133103) & ~(7'd74 == add_ln1116_16_reg_133103) & ~(7'd44 == add_ln1116_16_reg_133103) & ~(7'd104 == add_ln1116_16_reg_133103) & ~(7'd46 == add_ln1116_16_reg_133103) & ~(7'd82 == add_ln1116_16_reg_133103) & ~(7'd48 == add_ln1116_16_reg_133103) & ~(7'd102 == add_ln1116_16_reg_133103) & ~(7'd50 == add_ln1116_16_reg_133103) & ~(7'd76 == add_ln1116_16_reg_133103) & ~(7'd52 == add_ln1116_16_reg_133103) & ~(7'd100 == add_ln1116_16_reg_133103) & ~(7'd54 == add_ln1116_16_reg_133103) & ~(7'd88 == add_ln1116_16_reg_133103) & ~(7'd56 == add_ln1116_16_reg_133103) & ~(7'd98 == add_ln1116_16_reg_133103) & ~(7'd58 == add_ln1116_16_reg_133103) & ~(7'd78 == add_ln1116_16_reg_133103) & ~(7'd60 == add_ln1116_16_reg_133103) & ~(7'd96 == add_ln1116_16_reg_133103) & ~(7'd62 == add_ln1116_16_reg_133103) & ~(7'd84 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | (~(7'd0 == add_ln1116_7_reg_132705) & ~(7'd126 == add_ln1116_7_reg_132705) & ~(7'd2 == add_ln1116_7_reg_132705) & ~(7'd64 == add_ln1116_7_reg_132705) & ~(7'd4 == add_ln1116_7_reg_132705) & ~(7'd124 == add_ln1116_7_reg_132705) & ~(7'd6 == add_ln1116_7_reg_132705) & ~(7'd94 == add_ln1116_7_reg_132705) & ~(7'd8 == add_ln1116_7_reg_132705) & ~(7'd122 == add_ln1116_7_reg_132705) & ~(7'd10 == add_ln1116_7_reg_132705) & ~(7'd66 == add_ln1116_7_reg_132705) & ~(7'd12 == add_ln1116_7_reg_132705) & ~(7'd120 == add_ln1116_7_reg_132705) & ~(7'd14 == add_ln1116_7_reg_132705) & ~(7'd80 == add_ln1116_7_reg_132705) & ~(7'd16 == add_ln1116_7_reg_132705) & ~(7'd118 == add_ln1116_7_reg_132705) & ~(7'd18 == add_ln1116_7_reg_132705) & ~(7'd68 == add_ln1116_7_reg_132705) & ~(7'd20 == add_ln1116_7_reg_132705) & ~(7'd116 == add_ln1116_7_reg_132705) & ~(7'd22 == add_ln1116_7_reg_132705) & ~(7'd92 == add_ln1116_7_reg_132705) & ~(7'd24 == add_ln1116_7_reg_132705) & ~(7'd114 == add_ln1116_7_reg_132705) & ~(7'd26 == add_ln1116_7_reg_132705) & ~(7'd70 == add_ln1116_7_reg_132705) & ~(7'd28 == add_ln1116_7_reg_132705) & ~(7'd112 == add_ln1116_7_reg_132705) & ~(7'd30 == add_ln1116_7_reg_132705) & ~(7'd86 == add_ln1116_7_reg_132705) & ~(7'd32 == add_ln1116_7_reg_132705) & ~(7'd110 == add_ln1116_7_reg_132705) & ~(7'd34 == add_ln1116_7_reg_132705) & ~(7'd72 == add_ln1116_7_reg_132705) & ~(7'd36 == add_ln1116_7_reg_132705) & ~(7'd108 == add_ln1116_7_reg_132705) & ~(7'd38 == add_ln1116_7_reg_132705) & ~(7'd90 == add_ln1116_7_reg_132705) & ~(7'd40 == add_ln1116_7_reg_132705) & ~(7'd106 == add_ln1116_7_reg_132705) & ~(7'd42 == add_ln1116_7_reg_132705) & ~(7'd74 == add_ln1116_7_reg_132705) & ~(7'd44 == add_ln1116_7_reg_132705) & ~(7'd104 == add_ln1116_7_reg_132705) & ~(7'd46 == add_ln1116_7_reg_132705) & ~(7'd82 == add_ln1116_7_reg_132705) & ~(7'd48 == add_ln1116_7_reg_132705) & ~(7'd102 == add_ln1116_7_reg_132705) & ~(7'd50 == add_ln1116_7_reg_132705) & ~(7'd76 == add_ln1116_7_reg_132705) & ~(7'd52 == add_ln1116_7_reg_132705) & ~(7'd100 == add_ln1116_7_reg_132705) & ~(7'd54 == add_ln1116_7_reg_132705) & ~(7'd88 == add_ln1116_7_reg_132705) & ~(7'd56 == add_ln1116_7_reg_132705) & ~(7'd98 == add_ln1116_7_reg_132705) & ~(7'd58 == add_ln1116_7_reg_132705) & ~(7'd78 == add_ln1116_7_reg_132705) & ~(7'd60 == add_ln1116_7_reg_132705) & ~(7'd96 == add_ln1116_7_reg_132705) & ~(7'd62 == add_ln1116_7_reg_132705) & ~(7'd84 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | (~(7'd0 == add_ln1116_4_reg_132207) & ~(7'd126 == add_ln1116_4_reg_132207) & ~(7'd2 == add_ln1116_4_reg_132207) & ~(7'd64 == add_ln1116_4_reg_132207) & ~(7'd4 == add_ln1116_4_reg_132207) & ~(7'd124 == add_ln1116_4_reg_132207) & ~(7'd6 == add_ln1116_4_reg_132207) & ~(7'd94 == add_ln1116_4_reg_132207) & ~(7'd8 == add_ln1116_4_reg_132207) & ~(7'd122 == add_ln1116_4_reg_132207) & ~(7'd10 == add_ln1116_4_reg_132207) & ~(7'd66 == add_ln1116_4_reg_132207) & ~(7'd12 == add_ln1116_4_reg_132207) & ~(7'd120 == add_ln1116_4_reg_132207) & ~(7'd14 == add_ln1116_4_reg_132207) & ~(7'd80 == add_ln1116_4_reg_132207) & ~(7'd16 == add_ln1116_4_reg_132207) & ~(7'd118 == add_ln1116_4_reg_132207) & ~(7'd18 == add_ln1116_4_reg_132207) & ~(7'd68 == add_ln1116_4_reg_132207) & ~(7'd20 == add_ln1116_4_reg_132207) & ~(7'd116 == add_ln1116_4_reg_132207) & ~(7'd22 == add_ln1116_4_reg_132207) & ~(7'd92 == add_ln1116_4_reg_132207) & ~(7'd24 == add_ln1116_4_reg_132207) & ~(7'd114 == add_ln1116_4_reg_132207) & ~(7'd26 == add_ln1116_4_reg_132207) & ~(7'd70 == add_ln1116_4_reg_132207) & ~(7'd28 == add_ln1116_4_reg_132207) & ~(7'd112 == add_ln1116_4_reg_132207) & ~(7'd30 == add_ln1116_4_reg_132207) & ~(7'd86 == add_ln1116_4_reg_132207) & ~(7'd32 == add_ln1116_4_reg_132207) & ~(7'd110 == add_ln1116_4_reg_132207) & ~(7'd34 == add_ln1116_4_reg_132207) & ~(7'd72 == add_ln1116_4_reg_132207) & ~(7'd36 == add_ln1116_4_reg_132207) & ~(7'd108 == add_ln1116_4_reg_132207) & ~(7'd38 == add_ln1116_4_reg_132207) & ~(7'd90 == add_ln1116_4_reg_132207) & ~(7'd40 == add_ln1116_4_reg_132207) & ~(7'd106 == add_ln1116_4_reg_132207) & ~(7'd42 == add_ln1116_4_reg_132207) & ~(7'd74 == add_ln1116_4_reg_132207) & ~(7'd44 == add_ln1116_4_reg_132207) & ~(7'd104 == add_ln1116_4_reg_132207) & ~(7'd46 == add_ln1116_4_reg_132207) & ~(7'd82 == add_ln1116_4_reg_132207) & ~(7'd48 == add_ln1116_4_reg_132207) & ~(7'd102 == add_ln1116_4_reg_132207) & ~(7'd50 == add_ln1116_4_reg_132207) & ~(7'd76 == add_ln1116_4_reg_132207) & ~(7'd52 == add_ln1116_4_reg_132207) & ~(7'd100 == add_ln1116_4_reg_132207) & ~(7'd54 == add_ln1116_4_reg_132207) & ~(7'd88 == add_ln1116_4_reg_132207) & ~(7'd56 == add_ln1116_4_reg_132207) & ~(7'd98 == add_ln1116_4_reg_132207) & ~(7'd58 == add_ln1116_4_reg_132207) & ~(7'd78 == add_ln1116_4_reg_132207) & ~(7'd60 == add_ln1116_4_reg_132207) & ~(7'd96 == add_ln1116_4_reg_132207) & ~(7'd62 == add_ln1116_4_reg_132207) & ~(7'd84 == add_ln1116_4_reg_132207) & (ap_ST_fsm_state84 == ap_CS_fsm)) | (~(7'd0 == add_ln1116_reg_131809) & ~(7'd126 == add_ln1116_reg_131809) & ~(7'd2 == add_ln1116_reg_131809) & ~(7'd64 == add_ln1116_reg_131809) & ~(7'd4 == add_ln1116_reg_131809) & ~(7'd124 == add_ln1116_reg_131809) & ~(7'd6 == add_ln1116_reg_131809) & ~(7'd94 == add_ln1116_reg_131809) & ~(7'd8 == add_ln1116_reg_131809) & ~(7'd122 == add_ln1116_reg_131809) & ~(7'd10 == add_ln1116_reg_131809) & ~(7'd66 == add_ln1116_reg_131809) & ~(7'd12 == add_ln1116_reg_131809) & ~(7'd120 == add_ln1116_reg_131809) & ~(7'd14 == add_ln1116_reg_131809) & ~(7'd80 == add_ln1116_reg_131809) & ~(7'd16 == add_ln1116_reg_131809) & ~(7'd118 == add_ln1116_reg_131809) & ~(7'd18 == add_ln1116_reg_131809) & ~(7'd68 == add_ln1116_reg_131809) & ~(7'd20 == add_ln1116_reg_131809) & ~(7'd116 == add_ln1116_reg_131809) & ~(7'd22 == add_ln1116_reg_131809) & ~(7'd92 == add_ln1116_reg_131809) & ~(7'd24 == add_ln1116_reg_131809) & ~(7'd114 == add_ln1116_reg_131809) & ~(7'd26 == add_ln1116_reg_131809) & ~(7'd70 == add_ln1116_reg_131809) & ~(7'd28 == add_ln1116_reg_131809) & ~(7'd112 == add_ln1116_reg_131809) & ~(7'd30 == add_ln1116_reg_131809) & ~(7'd86 == add_ln1116_reg_131809) & ~(7'd32 == add_ln1116_reg_131809) & ~(7'd110 == add_ln1116_reg_131809) & ~(7'd34 == add_ln1116_reg_131809) & ~(7'd72 == add_ln1116_reg_131809) & ~(7'd36 == add_ln1116_reg_131809) & ~(7'd108 == add_ln1116_reg_131809) & ~(7'd38 == add_ln1116_reg_131809) & ~(7'd90 == add_ln1116_reg_131809) & ~(7'd40 == add_ln1116_reg_131809) & ~(7'd106 == add_ln1116_reg_131809) & ~(7'd42 == add_ln1116_reg_131809) & ~(7'd74 == add_ln1116_reg_131809) & ~(7'd44 == add_ln1116_reg_131809) & ~(7'd104 == add_ln1116_reg_131809) & ~(7'd46 == add_ln1116_reg_131809) & ~(7'd82 == add_ln1116_reg_131809) & ~(7'd48 == add_ln1116_reg_131809) & ~(7'd102 == add_ln1116_reg_131809) & ~(7'd50 == add_ln1116_reg_131809) & ~(7'd76 == add_ln1116_reg_131809) & ~(7'd52 == add_ln1116_reg_131809) & ~(7'd100 == add_ln1116_reg_131809) & ~(7'd54 == add_ln1116_reg_131809) & ~(7'd88 == add_ln1116_reg_131809) & ~(7'd56 == add_ln1116_reg_131809) & ~(7'd98 == add_ln1116_reg_131809) & ~(7'd58 == add_ln1116_reg_131809) & ~(7'd78 == add_ln1116_reg_131809) & ~(7'd60 == add_ln1116_reg_131809) & ~(7'd96 == add_ln1116_reg_131809) & ~(7'd62 == add_ln1116_reg_131809) & ~(7'd84 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_31_reg_145576) & ~(7'd61 == add_ln1116_31_reg_145576) & ~(7'd87 == add_ln1116_31_reg_145576) & ~(7'd59 == add_ln1116_31_reg_145576) & ~(7'd97 == add_ln1116_31_reg_145576) & ~(7'd57 == add_ln1116_31_reg_145576) & ~(7'd77 == add_ln1116_31_reg_145576) & ~(7'd55 == add_ln1116_31_reg_145576) & ~(7'd99 == add_ln1116_31_reg_145576) & ~(7'd53 == add_ln1116_31_reg_145576) & ~(7'd85 == add_ln1116_31_reg_145576) & ~(7'd51 == add_ln1116_31_reg_145576) & ~(7'd101 == add_ln1116_31_reg_145576) & ~(7'd49 == add_ln1116_31_reg_145576) & ~(7'd75 == add_ln1116_31_reg_145576) & ~(7'd47 == add_ln1116_31_reg_145576) & ~(7'd103 == add_ln1116_31_reg_145576) & ~(7'd45 == add_ln1116_31_reg_145576) & ~(7'd89 == add_ln1116_31_reg_145576) & ~(7'd43 == add_ln1116_31_reg_145576) & ~(7'd105 == add_ln1116_31_reg_145576) & ~(7'd41 == add_ln1116_31_reg_145576) & ~(7'd73 == add_ln1116_31_reg_145576) & ~(7'd39 == add_ln1116_31_reg_145576) & ~(7'd107 == add_ln1116_31_reg_145576) & ~(7'd37 == add_ln1116_31_reg_145576) & ~(7'd81 == add_ln1116_31_reg_145576) & ~(7'd35 == add_ln1116_31_reg_145576) & ~(7'd109 == add_ln1116_31_reg_145576) & ~(7'd33 == add_ln1116_31_reg_145576) & ~(7'd71 == add_ln1116_31_reg_145576) & ~(7'd31 == add_ln1116_31_reg_145576) & ~(7'd111 == add_ln1116_31_reg_145576) & ~(7'd29 == add_ln1116_31_reg_145576) & ~(7'd91 == add_ln1116_31_reg_145576) & ~(7'd27 == add_ln1116_31_reg_145576) & ~(7'd113 == add_ln1116_31_reg_145576) & ~(7'd25 == add_ln1116_31_reg_145576) & ~(7'd69 == add_ln1116_31_reg_145576) & ~(7'd23 == add_ln1116_31_reg_145576) & ~(7'd115 == add_ln1116_31_reg_145576) & ~(7'd21 == add_ln1116_31_reg_145576) & ~(7'd83 == add_ln1116_31_reg_145576) & ~(7'd19 == add_ln1116_31_reg_145576) & ~(7'd117 == add_ln1116_31_reg_145576) & ~(7'd17 == add_ln1116_31_reg_145576) & ~(7'd67 == add_ln1116_31_reg_145576) & ~(7'd15 == add_ln1116_31_reg_145576) & ~(7'd119 == add_ln1116_31_reg_145576) & ~(7'd13 == add_ln1116_31_reg_145576) & ~(7'd93 == add_ln1116_31_reg_145576) & ~(7'd11 == add_ln1116_31_reg_145576) & ~(7'd121 == add_ln1116_31_reg_145576) & ~(7'd9 == add_ln1116_31_reg_145576) & ~(7'd65 == add_ln1116_31_reg_145576) & ~(7'd7 == add_ln1116_31_reg_145576) & ~(7'd123 == add_ln1116_31_reg_145576) & ~(7'd5 == add_ln1116_31_reg_145576) & ~(7'd79 == add_ln1116_31_reg_145576) & ~(7'd3 == add_ln1116_31_reg_145576) & ~(7'd125 == add_ln1116_31_reg_145576) & ~(7'd1 == add_ln1116_31_reg_145576) & ~(7'd63 == add_ln1116_31_reg_145576) & (ap_ST_fsm_state2352 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_27_reg_145171) & ~(7'd61 == add_ln1116_27_reg_145171) & ~(7'd87 == add_ln1116_27_reg_145171) & ~(7'd59 == add_ln1116_27_reg_145171) & ~(7'd97 == add_ln1116_27_reg_145171) & ~(7'd57 == add_ln1116_27_reg_145171) & ~(7'd77 == add_ln1116_27_reg_145171) & ~(7'd55 == add_ln1116_27_reg_145171) & ~(7'd99 == add_ln1116_27_reg_145171) & ~(7'd53 == add_ln1116_27_reg_145171) & ~(7'd85 == add_ln1116_27_reg_145171) & ~(7'd51 == add_ln1116_27_reg_145171) & ~(7'd101 == add_ln1116_27_reg_145171) & ~(7'd49 == add_ln1116_27_reg_145171) & ~(7'd75 == add_ln1116_27_reg_145171) & ~(7'd47 == add_ln1116_27_reg_145171) & ~(7'd103 == add_ln1116_27_reg_145171) & ~(7'd45 == add_ln1116_27_reg_145171) & ~(7'd89 == add_ln1116_27_reg_145171) & ~(7'd43 == add_ln1116_27_reg_145171) & ~(7'd105 == add_ln1116_27_reg_145171) & ~(7'd41 == add_ln1116_27_reg_145171) & ~(7'd73 == add_ln1116_27_reg_145171) & ~(7'd39 == add_ln1116_27_reg_145171) & ~(7'd107 == add_ln1116_27_reg_145171) & ~(7'd37 == add_ln1116_27_reg_145171) & ~(7'd81 == add_ln1116_27_reg_145171) & ~(7'd35 == add_ln1116_27_reg_145171) & ~(7'd109 == add_ln1116_27_reg_145171) & ~(7'd33 == add_ln1116_27_reg_145171) & ~(7'd71 == add_ln1116_27_reg_145171) & ~(7'd31 == add_ln1116_27_reg_145171) & ~(7'd111 == add_ln1116_27_reg_145171) & ~(7'd29 == add_ln1116_27_reg_145171) & ~(7'd91 == add_ln1116_27_reg_145171) & ~(7'd27 == add_ln1116_27_reg_145171) & ~(7'd113 == add_ln1116_27_reg_145171) & ~(7'd25 == add_ln1116_27_reg_145171) & ~(7'd69 == add_ln1116_27_reg_145171) & ~(7'd23 == add_ln1116_27_reg_145171) & ~(7'd115 == add_ln1116_27_reg_145171) & ~(7'd21 == add_ln1116_27_reg_145171) & ~(7'd83 == add_ln1116_27_reg_145171) & ~(7'd19 == add_ln1116_27_reg_145171) & ~(7'd117 == add_ln1116_27_reg_145171) & ~(7'd17 == add_ln1116_27_reg_145171) & ~(7'd67 == add_ln1116_27_reg_145171) & ~(7'd15 == add_ln1116_27_reg_145171) & ~(7'd119 == add_ln1116_27_reg_145171) & ~(7'd13 == add_ln1116_27_reg_145171) & ~(7'd93 == add_ln1116_27_reg_145171) & ~(7'd11 == add_ln1116_27_reg_145171) & ~(7'd121 == add_ln1116_27_reg_145171) & ~(7'd9 == add_ln1116_27_reg_145171) & ~(7'd65 == add_ln1116_27_reg_145171) & ~(7'd7 == add_ln1116_27_reg_145171) & ~(7'd123 == add_ln1116_27_reg_145171) & ~(7'd5 == add_ln1116_27_reg_145171) & ~(7'd79 == add_ln1116_27_reg_145171) & ~(7'd3 == add_ln1116_27_reg_145171) & ~(7'd125 == add_ln1116_27_reg_145171) & ~(7'd1 == add_ln1116_27_reg_145171) & ~(7'd63 == add_ln1116_27_reg_145171) & (ap_ST_fsm_state2279 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_24_reg_144701) & ~(7'd61 == add_ln1116_24_reg_144701) & ~(7'd87 == add_ln1116_24_reg_144701) & ~(7'd59 == add_ln1116_24_reg_144701) & ~(7'd97 == add_ln1116_24_reg_144701) & ~(7'd57 == add_ln1116_24_reg_144701) & ~(7'd77 == add_ln1116_24_reg_144701) & ~(7'd55 == add_ln1116_24_reg_144701) & ~(7'd99 == add_ln1116_24_reg_144701) & ~(7'd53 == add_ln1116_24_reg_144701) & ~(7'd85 == add_ln1116_24_reg_144701) & ~(7'd51 == add_ln1116_24_reg_144701) & ~(7'd101 == add_ln1116_24_reg_144701) & ~(7'd49 == add_ln1116_24_reg_144701) & ~(7'd75 == add_ln1116_24_reg_144701) & ~(7'd47 == add_ln1116_24_reg_144701) & ~(7'd103 == add_ln1116_24_reg_144701) & ~(7'd45 == add_ln1116_24_reg_144701) & ~(7'd89 == add_ln1116_24_reg_144701) & ~(7'd43 == add_ln1116_24_reg_144701) & ~(7'd105 == add_ln1116_24_reg_144701) & ~(7'd41 == add_ln1116_24_reg_144701) & ~(7'd73 == add_ln1116_24_reg_144701) & ~(7'd39 == add_ln1116_24_reg_144701) & ~(7'd107 == add_ln1116_24_reg_144701) & ~(7'd37 == add_ln1116_24_reg_144701) & ~(7'd81 == add_ln1116_24_reg_144701) & ~(7'd35 == add_ln1116_24_reg_144701) & ~(7'd109 == add_ln1116_24_reg_144701) & ~(7'd33 == add_ln1116_24_reg_144701) & ~(7'd71 == add_ln1116_24_reg_144701) & ~(7'd31 == add_ln1116_24_reg_144701) & ~(7'd111 == add_ln1116_24_reg_144701) & ~(7'd29 == add_ln1116_24_reg_144701) & ~(7'd91 == add_ln1116_24_reg_144701) & ~(7'd27 == add_ln1116_24_reg_144701) & ~(7'd113 == add_ln1116_24_reg_144701) & ~(7'd25 == add_ln1116_24_reg_144701) & ~(7'd69 == add_ln1116_24_reg_144701) & ~(7'd23 == add_ln1116_24_reg_144701) & ~(7'd115 == add_ln1116_24_reg_144701) & ~(7'd21 == add_ln1116_24_reg_144701) & ~(7'd83 == add_ln1116_24_reg_144701) & ~(7'd19 == add_ln1116_24_reg_144701) & ~(7'd117 == add_ln1116_24_reg_144701) & ~(7'd17 == add_ln1116_24_reg_144701) & ~(7'd67 == add_ln1116_24_reg_144701) & ~(7'd15 == add_ln1116_24_reg_144701) & ~(7'd119 == add_ln1116_24_reg_144701) & ~(7'd13 == add_ln1116_24_reg_144701) & ~(7'd93 == add_ln1116_24_reg_144701) & ~(7'd11 == add_ln1116_24_reg_144701) & ~(7'd121 == add_ln1116_24_reg_144701) & ~(7'd9 == add_ln1116_24_reg_144701) & ~(7'd65 == add_ln1116_24_reg_144701) & ~(7'd7 == add_ln1116_24_reg_144701) & ~(7'd123 == add_ln1116_24_reg_144701) & ~(7'd5 == add_ln1116_24_reg_144701) & ~(7'd79 == add_ln1116_24_reg_144701) & ~(7'd3 == add_ln1116_24_reg_144701) & ~(7'd125 == add_ln1116_24_reg_144701) & ~(7'd1 == add_ln1116_24_reg_144701) & ~(7'd63 == add_ln1116_24_reg_144701) & (ap_ST_fsm_state2202 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_15_reg_144296) & ~(7'd61 == add_ln1116_15_reg_144296) & ~(7'd87 == add_ln1116_15_reg_144296) & ~(7'd59 == add_ln1116_15_reg_144296) & ~(7'd97 == add_ln1116_15_reg_144296) & ~(7'd57 == add_ln1116_15_reg_144296) & ~(7'd77 == add_ln1116_15_reg_144296) & ~(7'd55 == add_ln1116_15_reg_144296) & ~(7'd99 == add_ln1116_15_reg_144296) & ~(7'd53 == add_ln1116_15_reg_144296) & ~(7'd85 == add_ln1116_15_reg_144296) & ~(7'd51 == add_ln1116_15_reg_144296) & ~(7'd101 == add_ln1116_15_reg_144296) & ~(7'd49 == add_ln1116_15_reg_144296) & ~(7'd75 == add_ln1116_15_reg_144296) & ~(7'd47 == add_ln1116_15_reg_144296) & ~(7'd103 == add_ln1116_15_reg_144296) & ~(7'd45 == add_ln1116_15_reg_144296) & ~(7'd89 == add_ln1116_15_reg_144296) & ~(7'd43 == add_ln1116_15_reg_144296) & ~(7'd105 == add_ln1116_15_reg_144296) & ~(7'd41 == add_ln1116_15_reg_144296) & ~(7'd73 == add_ln1116_15_reg_144296) & ~(7'd39 == add_ln1116_15_reg_144296) & ~(7'd107 == add_ln1116_15_reg_144296) & ~(7'd37 == add_ln1116_15_reg_144296) & ~(7'd81 == add_ln1116_15_reg_144296) & ~(7'd35 == add_ln1116_15_reg_144296) & ~(7'd109 == add_ln1116_15_reg_144296) & ~(7'd33 == add_ln1116_15_reg_144296) & ~(7'd71 == add_ln1116_15_reg_144296) & ~(7'd31 == add_ln1116_15_reg_144296) & ~(7'd111 == add_ln1116_15_reg_144296) & ~(7'd29 == add_ln1116_15_reg_144296) & ~(7'd91 == add_ln1116_15_reg_144296) & ~(7'd27 == add_ln1116_15_reg_144296) & ~(7'd113 == add_ln1116_15_reg_144296) & ~(7'd25 == add_ln1116_15_reg_144296) & ~(7'd69 == add_ln1116_15_reg_144296) & ~(7'd23 == add_ln1116_15_reg_144296) & ~(7'd115 == add_ln1116_15_reg_144296) & ~(7'd21 == add_ln1116_15_reg_144296) & ~(7'd83 == add_ln1116_15_reg_144296) & ~(7'd19 == add_ln1116_15_reg_144296) & ~(7'd117 == add_ln1116_15_reg_144296) & ~(7'd17 == add_ln1116_15_reg_144296) & ~(7'd67 == add_ln1116_15_reg_144296) & ~(7'd15 == add_ln1116_15_reg_144296) & ~(7'd119 == add_ln1116_15_reg_144296) & ~(7'd13 == add_ln1116_15_reg_144296) & ~(7'd93 == add_ln1116_15_reg_144296) & ~(7'd11 == add_ln1116_15_reg_144296) & ~(7'd121 == add_ln1116_15_reg_144296) & ~(7'd9 == add_ln1116_15_reg_144296) & ~(7'd65 == add_ln1116_15_reg_144296) & ~(7'd7 == add_ln1116_15_reg_144296) & ~(7'd123 == add_ln1116_15_reg_144296) & ~(7'd5 == add_ln1116_15_reg_144296) & ~(7'd79 == add_ln1116_15_reg_144296) & ~(7'd3 == add_ln1116_15_reg_144296) & ~(7'd125 == add_ln1116_15_reg_144296) & ~(7'd1 == add_ln1116_15_reg_144296) & ~(7'd63 == add_ln1116_15_reg_144296) & (ap_ST_fsm_state2129 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_29_reg_142013) & ~(7'd61 == add_ln1116_29_reg_142013) & ~(7'd87 == add_ln1116_29_reg_142013) & ~(7'd59 == add_ln1116_29_reg_142013) & ~(7'd97 == add_ln1116_29_reg_142013) & ~(7'd57 == add_ln1116_29_reg_142013) & ~(7'd77 == add_ln1116_29_reg_142013) & ~(7'd55 == add_ln1116_29_reg_142013) & ~(7'd99 == add_ln1116_29_reg_142013) & ~(7'd53 == add_ln1116_29_reg_142013) & ~(7'd85 == add_ln1116_29_reg_142013) & ~(7'd51 == add_ln1116_29_reg_142013) & ~(7'd101 == add_ln1116_29_reg_142013) & ~(7'd49 == add_ln1116_29_reg_142013) & ~(7'd75 == add_ln1116_29_reg_142013) & ~(7'd47 == add_ln1116_29_reg_142013) & ~(7'd103 == add_ln1116_29_reg_142013) & ~(7'd45 == add_ln1116_29_reg_142013) & ~(7'd89 == add_ln1116_29_reg_142013) & ~(7'd43 == add_ln1116_29_reg_142013) & ~(7'd105 == add_ln1116_29_reg_142013) & ~(7'd41 == add_ln1116_29_reg_142013) & ~(7'd73 == add_ln1116_29_reg_142013) & ~(7'd39 == add_ln1116_29_reg_142013) & ~(7'd107 == add_ln1116_29_reg_142013) & ~(7'd37 == add_ln1116_29_reg_142013) & ~(7'd81 == add_ln1116_29_reg_142013) & ~(7'd35 == add_ln1116_29_reg_142013) & ~(7'd109 == add_ln1116_29_reg_142013) & ~(7'd33 == add_ln1116_29_reg_142013) & ~(7'd71 == add_ln1116_29_reg_142013) & ~(7'd31 == add_ln1116_29_reg_142013) & ~(7'd111 == add_ln1116_29_reg_142013) & ~(7'd29 == add_ln1116_29_reg_142013) & ~(7'd91 == add_ln1116_29_reg_142013) & ~(7'd27 == add_ln1116_29_reg_142013) & ~(7'd113 == add_ln1116_29_reg_142013) & ~(7'd25 == add_ln1116_29_reg_142013) & ~(7'd69 == add_ln1116_29_reg_142013) & ~(7'd23 == add_ln1116_29_reg_142013) & ~(7'd115 == add_ln1116_29_reg_142013) & ~(7'd21 == add_ln1116_29_reg_142013) & ~(7'd83 == add_ln1116_29_reg_142013) & ~(7'd19 == add_ln1116_29_reg_142013) & ~(7'd117 == add_ln1116_29_reg_142013) & ~(7'd17 == add_ln1116_29_reg_142013) & ~(7'd67 == add_ln1116_29_reg_142013) & ~(7'd15 == add_ln1116_29_reg_142013) & ~(7'd119 == add_ln1116_29_reg_142013) & ~(7'd13 == add_ln1116_29_reg_142013) & ~(7'd93 == add_ln1116_29_reg_142013) & ~(7'd11 == add_ln1116_29_reg_142013) & ~(7'd121 == add_ln1116_29_reg_142013) & ~(7'd9 == add_ln1116_29_reg_142013) & ~(7'd65 == add_ln1116_29_reg_142013) & ~(7'd7 == add_ln1116_29_reg_142013) & ~(7'd123 == add_ln1116_29_reg_142013) & ~(7'd5 == add_ln1116_29_reg_142013) & ~(7'd79 == add_ln1116_29_reg_142013) & ~(7'd3 == add_ln1116_29_reg_142013) & ~(7'd125 == add_ln1116_29_reg_142013) & ~(7'd1 == add_ln1116_29_reg_142013) & ~(7'd63 == add_ln1116_29_reg_142013) & (ap_ST_fsm_state1748 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_25_reg_141608) & ~(7'd61 == add_ln1116_25_reg_141608) & ~(7'd87 == add_ln1116_25_reg_141608) & ~(7'd59 == add_ln1116_25_reg_141608) & ~(7'd97 == add_ln1116_25_reg_141608) & ~(7'd57 == add_ln1116_25_reg_141608) & ~(7'd77 == add_ln1116_25_reg_141608) & ~(7'd55 == add_ln1116_25_reg_141608) & ~(7'd99 == add_ln1116_25_reg_141608) & ~(7'd53 == add_ln1116_25_reg_141608) & ~(7'd85 == add_ln1116_25_reg_141608) & ~(7'd51 == add_ln1116_25_reg_141608) & ~(7'd101 == add_ln1116_25_reg_141608) & ~(7'd49 == add_ln1116_25_reg_141608) & ~(7'd75 == add_ln1116_25_reg_141608) & ~(7'd47 == add_ln1116_25_reg_141608) & ~(7'd103 == add_ln1116_25_reg_141608) & ~(7'd45 == add_ln1116_25_reg_141608) & ~(7'd89 == add_ln1116_25_reg_141608) & ~(7'd43 == add_ln1116_25_reg_141608) & ~(7'd105 == add_ln1116_25_reg_141608) & ~(7'd41 == add_ln1116_25_reg_141608) & ~(7'd73 == add_ln1116_25_reg_141608) & ~(7'd39 == add_ln1116_25_reg_141608) & ~(7'd107 == add_ln1116_25_reg_141608) & ~(7'd37 == add_ln1116_25_reg_141608) & ~(7'd81 == add_ln1116_25_reg_141608) & ~(7'd35 == add_ln1116_25_reg_141608) & ~(7'd109 == add_ln1116_25_reg_141608) & ~(7'd33 == add_ln1116_25_reg_141608) & ~(7'd71 == add_ln1116_25_reg_141608) & ~(7'd31 == add_ln1116_25_reg_141608) & ~(7'd111 == add_ln1116_25_reg_141608) & ~(7'd29 == add_ln1116_25_reg_141608) & ~(7'd91 == add_ln1116_25_reg_141608) & ~(7'd27 == add_ln1116_25_reg_141608) & ~(7'd113 == add_ln1116_25_reg_141608) & ~(7'd25 == add_ln1116_25_reg_141608) & ~(7'd69 == add_ln1116_25_reg_141608) & ~(7'd23 == add_ln1116_25_reg_141608) & ~(7'd115 == add_ln1116_25_reg_141608) & ~(7'd21 == add_ln1116_25_reg_141608) & ~(7'd83 == add_ln1116_25_reg_141608) & ~(7'd19 == add_ln1116_25_reg_141608) & ~(7'd117 == add_ln1116_25_reg_141608) & ~(7'd17 == add_ln1116_25_reg_141608) & ~(7'd67 == add_ln1116_25_reg_141608) & ~(7'd15 == add_ln1116_25_reg_141608) & ~(7'd119 == add_ln1116_25_reg_141608) & ~(7'd13 == add_ln1116_25_reg_141608) & ~(7'd93 == add_ln1116_25_reg_141608) & ~(7'd11 == add_ln1116_25_reg_141608) & ~(7'd121 == add_ln1116_25_reg_141608) & ~(7'd9 == add_ln1116_25_reg_141608) & ~(7'd65 == add_ln1116_25_reg_141608) & ~(7'd7 == add_ln1116_25_reg_141608) & ~(7'd123 == add_ln1116_25_reg_141608) & ~(7'd5 == add_ln1116_25_reg_141608) & ~(7'd79 == add_ln1116_25_reg_141608) & ~(7'd3 == add_ln1116_25_reg_141608) & ~(7'd125 == add_ln1116_25_reg_141608) & ~(7'd1 == add_ln1116_25_reg_141608) & ~(7'd63 == add_ln1116_25_reg_141608) & (ap_ST_fsm_state1675 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_20_reg_141148) & ~(7'd61 == add_ln1116_20_reg_141148) & ~(7'd87 == add_ln1116_20_reg_141148) & ~(7'd59 == add_ln1116_20_reg_141148) & ~(7'd97 == add_ln1116_20_reg_141148) & ~(7'd57 == add_ln1116_20_reg_141148) & ~(7'd77 == add_ln1116_20_reg_141148) & ~(7'd55 == add_ln1116_20_reg_141148) & ~(7'd99 == add_ln1116_20_reg_141148) & ~(7'd53 == add_ln1116_20_reg_141148) & ~(7'd85 == add_ln1116_20_reg_141148) & ~(7'd51 == add_ln1116_20_reg_141148) & ~(7'd101 == add_ln1116_20_reg_141148) & ~(7'd49 == add_ln1116_20_reg_141148) & ~(7'd75 == add_ln1116_20_reg_141148) & ~(7'd47 == add_ln1116_20_reg_141148) & ~(7'd103 == add_ln1116_20_reg_141148) & ~(7'd45 == add_ln1116_20_reg_141148) & ~(7'd89 == add_ln1116_20_reg_141148) & ~(7'd43 == add_ln1116_20_reg_141148) & ~(7'd105 == add_ln1116_20_reg_141148) & ~(7'd41 == add_ln1116_20_reg_141148) & ~(7'd73 == add_ln1116_20_reg_141148) & ~(7'd39 == add_ln1116_20_reg_141148) & ~(7'd107 == add_ln1116_20_reg_141148) & ~(7'd37 == add_ln1116_20_reg_141148) & ~(7'd81 == add_ln1116_20_reg_141148) & ~(7'd35 == add_ln1116_20_reg_141148) & ~(7'd109 == add_ln1116_20_reg_141148) & ~(7'd33 == add_ln1116_20_reg_141148) & ~(7'd71 == add_ln1116_20_reg_141148) & ~(7'd31 == add_ln1116_20_reg_141148) & ~(7'd111 == add_ln1116_20_reg_141148) & ~(7'd29 == add_ln1116_20_reg_141148) & ~(7'd91 == add_ln1116_20_reg_141148) & ~(7'd27 == add_ln1116_20_reg_141148) & ~(7'd113 == add_ln1116_20_reg_141148) & ~(7'd25 == add_ln1116_20_reg_141148) & ~(7'd69 == add_ln1116_20_reg_141148) & ~(7'd23 == add_ln1116_20_reg_141148) & ~(7'd115 == add_ln1116_20_reg_141148) & ~(7'd21 == add_ln1116_20_reg_141148) & ~(7'd83 == add_ln1116_20_reg_141148) & ~(7'd19 == add_ln1116_20_reg_141148) & ~(7'd117 == add_ln1116_20_reg_141148) & ~(7'd17 == add_ln1116_20_reg_141148) & ~(7'd67 == add_ln1116_20_reg_141148) & ~(7'd15 == add_ln1116_20_reg_141148) & ~(7'd119 == add_ln1116_20_reg_141148) & ~(7'd13 == add_ln1116_20_reg_141148) & ~(7'd93 == add_ln1116_20_reg_141148) & ~(7'd11 == add_ln1116_20_reg_141148) & ~(7'd121 == add_ln1116_20_reg_141148) & ~(7'd9 == add_ln1116_20_reg_141148) & ~(7'd65 == add_ln1116_20_reg_141148) & ~(7'd7 == add_ln1116_20_reg_141148) & ~(7'd123 == add_ln1116_20_reg_141148) & ~(7'd5 == add_ln1116_20_reg_141148) & ~(7'd79 == add_ln1116_20_reg_141148) & ~(7'd3 == add_ln1116_20_reg_141148) & ~(7'd125 == add_ln1116_20_reg_141148) & ~(7'd1 == add_ln1116_20_reg_141148) & ~(7'd63 == add_ln1116_20_reg_141148) & (ap_ST_fsm_state1598 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_12_reg_140743) & ~(7'd61 == add_ln1116_12_reg_140743) & ~(7'd87 == add_ln1116_12_reg_140743) & ~(7'd59 == add_ln1116_12_reg_140743) & ~(7'd97 == add_ln1116_12_reg_140743) & ~(7'd57 == add_ln1116_12_reg_140743) & ~(7'd77 == add_ln1116_12_reg_140743) & ~(7'd55 == add_ln1116_12_reg_140743) & ~(7'd99 == add_ln1116_12_reg_140743) & ~(7'd53 == add_ln1116_12_reg_140743) & ~(7'd85 == add_ln1116_12_reg_140743) & ~(7'd51 == add_ln1116_12_reg_140743) & ~(7'd101 == add_ln1116_12_reg_140743) & ~(7'd49 == add_ln1116_12_reg_140743) & ~(7'd75 == add_ln1116_12_reg_140743) & ~(7'd47 == add_ln1116_12_reg_140743) & ~(7'd103 == add_ln1116_12_reg_140743) & ~(7'd45 == add_ln1116_12_reg_140743) & ~(7'd89 == add_ln1116_12_reg_140743) & ~(7'd43 == add_ln1116_12_reg_140743) & ~(7'd105 == add_ln1116_12_reg_140743) & ~(7'd41 == add_ln1116_12_reg_140743) & ~(7'd73 == add_ln1116_12_reg_140743) & ~(7'd39 == add_ln1116_12_reg_140743) & ~(7'd107 == add_ln1116_12_reg_140743) & ~(7'd37 == add_ln1116_12_reg_140743) & ~(7'd81 == add_ln1116_12_reg_140743) & ~(7'd35 == add_ln1116_12_reg_140743) & ~(7'd109 == add_ln1116_12_reg_140743) & ~(7'd33 == add_ln1116_12_reg_140743) & ~(7'd71 == add_ln1116_12_reg_140743) & ~(7'd31 == add_ln1116_12_reg_140743) & ~(7'd111 == add_ln1116_12_reg_140743) & ~(7'd29 == add_ln1116_12_reg_140743) & ~(7'd91 == add_ln1116_12_reg_140743) & ~(7'd27 == add_ln1116_12_reg_140743) & ~(7'd113 == add_ln1116_12_reg_140743) & ~(7'd25 == add_ln1116_12_reg_140743) & ~(7'd69 == add_ln1116_12_reg_140743) & ~(7'd23 == add_ln1116_12_reg_140743) & ~(7'd115 == add_ln1116_12_reg_140743) & ~(7'd21 == add_ln1116_12_reg_140743) & ~(7'd83 == add_ln1116_12_reg_140743) & ~(7'd19 == add_ln1116_12_reg_140743) & ~(7'd117 == add_ln1116_12_reg_140743) & ~(7'd17 == add_ln1116_12_reg_140743) & ~(7'd67 == add_ln1116_12_reg_140743) & ~(7'd15 == add_ln1116_12_reg_140743) & ~(7'd119 == add_ln1116_12_reg_140743) & ~(7'd13 == add_ln1116_12_reg_140743) & ~(7'd93 == add_ln1116_12_reg_140743) & ~(7'd11 == add_ln1116_12_reg_140743) & ~(7'd121 == add_ln1116_12_reg_140743) & ~(7'd9 == add_ln1116_12_reg_140743) & ~(7'd65 == add_ln1116_12_reg_140743) & ~(7'd7 == add_ln1116_12_reg_140743) & ~(7'd123 == add_ln1116_12_reg_140743) & ~(7'd5 == add_ln1116_12_reg_140743) & ~(7'd79 == add_ln1116_12_reg_140743) & ~(7'd3 == add_ln1116_12_reg_140743) & ~(7'd125 == add_ln1116_12_reg_140743) & ~(7'd1 == add_ln1116_12_reg_140743) & ~(7'd63 == add_ln1116_12_reg_140743) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_30_reg_138421) & ~(7'd61 == add_ln1116_30_reg_138421) & ~(7'd87 == add_ln1116_30_reg_138421) & ~(7'd59 == add_ln1116_30_reg_138421) & ~(7'd97 == add_ln1116_30_reg_138421) & ~(7'd57 == add_ln1116_30_reg_138421) & ~(7'd77 == add_ln1116_30_reg_138421) & ~(7'd55 == add_ln1116_30_reg_138421) & ~(7'd99 == add_ln1116_30_reg_138421) & ~(7'd53 == add_ln1116_30_reg_138421) & ~(7'd85 == add_ln1116_30_reg_138421) & ~(7'd51 == add_ln1116_30_reg_138421) & ~(7'd101 == add_ln1116_30_reg_138421) & ~(7'd49 == add_ln1116_30_reg_138421) & ~(7'd75 == add_ln1116_30_reg_138421) & ~(7'd47 == add_ln1116_30_reg_138421) & ~(7'd103 == add_ln1116_30_reg_138421) & ~(7'd45 == add_ln1116_30_reg_138421) & ~(7'd89 == add_ln1116_30_reg_138421) & ~(7'd43 == add_ln1116_30_reg_138421) & ~(7'd105 == add_ln1116_30_reg_138421) & ~(7'd41 == add_ln1116_30_reg_138421) & ~(7'd73 == add_ln1116_30_reg_138421) & ~(7'd39 == add_ln1116_30_reg_138421) & ~(7'd107 == add_ln1116_30_reg_138421) & ~(7'd37 == add_ln1116_30_reg_138421) & ~(7'd81 == add_ln1116_30_reg_138421) & ~(7'd35 == add_ln1116_30_reg_138421) & ~(7'd109 == add_ln1116_30_reg_138421) & ~(7'd33 == add_ln1116_30_reg_138421) & ~(7'd71 == add_ln1116_30_reg_138421) & ~(7'd31 == add_ln1116_30_reg_138421) & ~(7'd111 == add_ln1116_30_reg_138421) & ~(7'd29 == add_ln1116_30_reg_138421) & ~(7'd91 == add_ln1116_30_reg_138421) & ~(7'd27 == add_ln1116_30_reg_138421) & ~(7'd113 == add_ln1116_30_reg_138421) & ~(7'd25 == add_ln1116_30_reg_138421) & ~(7'd69 == add_ln1116_30_reg_138421) & ~(7'd23 == add_ln1116_30_reg_138421) & ~(7'd115 == add_ln1116_30_reg_138421) & ~(7'd21 == add_ln1116_30_reg_138421) & ~(7'd83 == add_ln1116_30_reg_138421) & ~(7'd19 == add_ln1116_30_reg_138421) & ~(7'd117 == add_ln1116_30_reg_138421) & ~(7'd17 == add_ln1116_30_reg_138421) & ~(7'd67 == add_ln1116_30_reg_138421) & ~(7'd15 == add_ln1116_30_reg_138421) & ~(7'd119 == add_ln1116_30_reg_138421) & ~(7'd13 == add_ln1116_30_reg_138421) & ~(7'd93 == add_ln1116_30_reg_138421) & ~(7'd11 == add_ln1116_30_reg_138421) & ~(7'd121 == add_ln1116_30_reg_138421) & ~(7'd9 == add_ln1116_30_reg_138421) & ~(7'd65 == add_ln1116_30_reg_138421) & ~(7'd7 == add_ln1116_30_reg_138421) & ~(7'd123 == add_ln1116_30_reg_138421) & ~(7'd5 == add_ln1116_30_reg_138421) & ~(7'd79 == add_ln1116_30_reg_138421) & ~(7'd3 == add_ln1116_30_reg_138421) & ~(7'd125 == add_ln1116_30_reg_138421) & ~(7'd1 == add_ln1116_30_reg_138421) & ~(7'd63 == add_ln1116_30_reg_138421) & (ap_ST_fsm_state1142 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_26_reg_138016) & ~(7'd61 == add_ln1116_26_reg_138016) & ~(7'd87 == add_ln1116_26_reg_138016) & ~(7'd59 == add_ln1116_26_reg_138016) & ~(7'd97 == add_ln1116_26_reg_138016) & ~(7'd57 == add_ln1116_26_reg_138016) & ~(7'd77 == add_ln1116_26_reg_138016) & ~(7'd55 == add_ln1116_26_reg_138016) & ~(7'd99 == add_ln1116_26_reg_138016) & ~(7'd53 == add_ln1116_26_reg_138016) & ~(7'd85 == add_ln1116_26_reg_138016) & ~(7'd51 == add_ln1116_26_reg_138016) & ~(7'd101 == add_ln1116_26_reg_138016) & ~(7'd49 == add_ln1116_26_reg_138016) & ~(7'd75 == add_ln1116_26_reg_138016) & ~(7'd47 == add_ln1116_26_reg_138016) & ~(7'd103 == add_ln1116_26_reg_138016) & ~(7'd45 == add_ln1116_26_reg_138016) & ~(7'd89 == add_ln1116_26_reg_138016) & ~(7'd43 == add_ln1116_26_reg_138016) & ~(7'd105 == add_ln1116_26_reg_138016) & ~(7'd41 == add_ln1116_26_reg_138016) & ~(7'd73 == add_ln1116_26_reg_138016) & ~(7'd39 == add_ln1116_26_reg_138016) & ~(7'd107 == add_ln1116_26_reg_138016) & ~(7'd37 == add_ln1116_26_reg_138016) & ~(7'd81 == add_ln1116_26_reg_138016) & ~(7'd35 == add_ln1116_26_reg_138016) & ~(7'd109 == add_ln1116_26_reg_138016) & ~(7'd33 == add_ln1116_26_reg_138016) & ~(7'd71 == add_ln1116_26_reg_138016) & ~(7'd31 == add_ln1116_26_reg_138016) & ~(7'd111 == add_ln1116_26_reg_138016) & ~(7'd29 == add_ln1116_26_reg_138016) & ~(7'd91 == add_ln1116_26_reg_138016) & ~(7'd27 == add_ln1116_26_reg_138016) & ~(7'd113 == add_ln1116_26_reg_138016) & ~(7'd25 == add_ln1116_26_reg_138016) & ~(7'd69 == add_ln1116_26_reg_138016) & ~(7'd23 == add_ln1116_26_reg_138016) & ~(7'd115 == add_ln1116_26_reg_138016) & ~(7'd21 == add_ln1116_26_reg_138016) & ~(7'd83 == add_ln1116_26_reg_138016) & ~(7'd19 == add_ln1116_26_reg_138016) & ~(7'd117 == add_ln1116_26_reg_138016) & ~(7'd17 == add_ln1116_26_reg_138016) & ~(7'd67 == add_ln1116_26_reg_138016) & ~(7'd15 == add_ln1116_26_reg_138016) & ~(7'd119 == add_ln1116_26_reg_138016) & ~(7'd13 == add_ln1116_26_reg_138016) & ~(7'd93 == add_ln1116_26_reg_138016) & ~(7'd11 == add_ln1116_26_reg_138016) & ~(7'd121 == add_ln1116_26_reg_138016) & ~(7'd9 == add_ln1116_26_reg_138016) & ~(7'd65 == add_ln1116_26_reg_138016) & ~(7'd7 == add_ln1116_26_reg_138016) & ~(7'd123 == add_ln1116_26_reg_138016) & ~(7'd5 == add_ln1116_26_reg_138016) & ~(7'd79 == add_ln1116_26_reg_138016) & ~(7'd3 == add_ln1116_26_reg_138016) & ~(7'd125 == add_ln1116_26_reg_138016) & ~(7'd1 == add_ln1116_26_reg_138016) & ~(7'd63 == add_ln1116_26_reg_138016) & (ap_ST_fsm_state1069 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_21_reg_137546) & ~(7'd61 == add_ln1116_21_reg_137546) & ~(7'd87 == add_ln1116_21_reg_137546) & ~(7'd59 == add_ln1116_21_reg_137546) & ~(7'd97 == add_ln1116_21_reg_137546) & ~(7'd57 == add_ln1116_21_reg_137546) & ~(7'd77 == add_ln1116_21_reg_137546) & ~(7'd55 == add_ln1116_21_reg_137546) & ~(7'd99 == add_ln1116_21_reg_137546) & ~(7'd53 == add_ln1116_21_reg_137546) & ~(7'd85 == add_ln1116_21_reg_137546) & ~(7'd51 == add_ln1116_21_reg_137546) & ~(7'd101 == add_ln1116_21_reg_137546) & ~(7'd49 == add_ln1116_21_reg_137546) & ~(7'd75 == add_ln1116_21_reg_137546) & ~(7'd47 == add_ln1116_21_reg_137546) & ~(7'd103 == add_ln1116_21_reg_137546) & ~(7'd45 == add_ln1116_21_reg_137546) & ~(7'd89 == add_ln1116_21_reg_137546) & ~(7'd43 == add_ln1116_21_reg_137546) & ~(7'd105 == add_ln1116_21_reg_137546) & ~(7'd41 == add_ln1116_21_reg_137546) & ~(7'd73 == add_ln1116_21_reg_137546) & ~(7'd39 == add_ln1116_21_reg_137546) & ~(7'd107 == add_ln1116_21_reg_137546) & ~(7'd37 == add_ln1116_21_reg_137546) & ~(7'd81 == add_ln1116_21_reg_137546) & ~(7'd35 == add_ln1116_21_reg_137546) & ~(7'd109 == add_ln1116_21_reg_137546) & ~(7'd33 == add_ln1116_21_reg_137546) & ~(7'd71 == add_ln1116_21_reg_137546) & ~(7'd31 == add_ln1116_21_reg_137546) & ~(7'd111 == add_ln1116_21_reg_137546) & ~(7'd29 == add_ln1116_21_reg_137546) & ~(7'd91 == add_ln1116_21_reg_137546) & ~(7'd27 == add_ln1116_21_reg_137546) & ~(7'd113 == add_ln1116_21_reg_137546) & ~(7'd25 == add_ln1116_21_reg_137546) & ~(7'd69 == add_ln1116_21_reg_137546) & ~(7'd23 == add_ln1116_21_reg_137546) & ~(7'd115 == add_ln1116_21_reg_137546) & ~(7'd21 == add_ln1116_21_reg_137546) & ~(7'd83 == add_ln1116_21_reg_137546) & ~(7'd19 == add_ln1116_21_reg_137546) & ~(7'd117 == add_ln1116_21_reg_137546) & ~(7'd17 == add_ln1116_21_reg_137546) & ~(7'd67 == add_ln1116_21_reg_137546) & ~(7'd15 == add_ln1116_21_reg_137546) & ~(7'd119 == add_ln1116_21_reg_137546) & ~(7'd13 == add_ln1116_21_reg_137546) & ~(7'd93 == add_ln1116_21_reg_137546) & ~(7'd11 == add_ln1116_21_reg_137546) & ~(7'd121 == add_ln1116_21_reg_137546) & ~(7'd9 == add_ln1116_21_reg_137546) & ~(7'd65 == add_ln1116_21_reg_137546) & ~(7'd7 == add_ln1116_21_reg_137546) & ~(7'd123 == add_ln1116_21_reg_137546) & ~(7'd5 == add_ln1116_21_reg_137546) & ~(7'd79 == add_ln1116_21_reg_137546) & ~(7'd3 == add_ln1116_21_reg_137546) & ~(7'd125 == add_ln1116_21_reg_137546) & ~(7'd1 == add_ln1116_21_reg_137546) & ~(7'd63 == add_ln1116_21_reg_137546) & (ap_ST_fsm_state992 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_13_reg_137141) & ~(7'd61 == add_ln1116_13_reg_137141) & ~(7'd87 == add_ln1116_13_reg_137141) & ~(7'd59 == add_ln1116_13_reg_137141) & ~(7'd97 == add_ln1116_13_reg_137141) & ~(7'd57 == add_ln1116_13_reg_137141) & ~(7'd77 == add_ln1116_13_reg_137141) & ~(7'd55 == add_ln1116_13_reg_137141) & ~(7'd99 == add_ln1116_13_reg_137141) & ~(7'd53 == add_ln1116_13_reg_137141) & ~(7'd85 == add_ln1116_13_reg_137141) & ~(7'd51 == add_ln1116_13_reg_137141) & ~(7'd101 == add_ln1116_13_reg_137141) & ~(7'd49 == add_ln1116_13_reg_137141) & ~(7'd75 == add_ln1116_13_reg_137141) & ~(7'd47 == add_ln1116_13_reg_137141) & ~(7'd103 == add_ln1116_13_reg_137141) & ~(7'd45 == add_ln1116_13_reg_137141) & ~(7'd89 == add_ln1116_13_reg_137141) & ~(7'd43 == add_ln1116_13_reg_137141) & ~(7'd105 == add_ln1116_13_reg_137141) & ~(7'd41 == add_ln1116_13_reg_137141) & ~(7'd73 == add_ln1116_13_reg_137141) & ~(7'd39 == add_ln1116_13_reg_137141) & ~(7'd107 == add_ln1116_13_reg_137141) & ~(7'd37 == add_ln1116_13_reg_137141) & ~(7'd81 == add_ln1116_13_reg_137141) & ~(7'd35 == add_ln1116_13_reg_137141) & ~(7'd109 == add_ln1116_13_reg_137141) & ~(7'd33 == add_ln1116_13_reg_137141) & ~(7'd71 == add_ln1116_13_reg_137141) & ~(7'd31 == add_ln1116_13_reg_137141) & ~(7'd111 == add_ln1116_13_reg_137141) & ~(7'd29 == add_ln1116_13_reg_137141) & ~(7'd91 == add_ln1116_13_reg_137141) & ~(7'd27 == add_ln1116_13_reg_137141) & ~(7'd113 == add_ln1116_13_reg_137141) & ~(7'd25 == add_ln1116_13_reg_137141) & ~(7'd69 == add_ln1116_13_reg_137141) & ~(7'd23 == add_ln1116_13_reg_137141) & ~(7'd115 == add_ln1116_13_reg_137141) & ~(7'd21 == add_ln1116_13_reg_137141) & ~(7'd83 == add_ln1116_13_reg_137141) & ~(7'd19 == add_ln1116_13_reg_137141) & ~(7'd117 == add_ln1116_13_reg_137141) & ~(7'd17 == add_ln1116_13_reg_137141) & ~(7'd67 == add_ln1116_13_reg_137141) & ~(7'd15 == add_ln1116_13_reg_137141) & ~(7'd119 == add_ln1116_13_reg_137141) & ~(7'd13 == add_ln1116_13_reg_137141) & ~(7'd93 == add_ln1116_13_reg_137141) & ~(7'd11 == add_ln1116_13_reg_137141) & ~(7'd121 == add_ln1116_13_reg_137141) & ~(7'd9 == add_ln1116_13_reg_137141) & ~(7'd65 == add_ln1116_13_reg_137141) & ~(7'd7 == add_ln1116_13_reg_137141) & ~(7'd123 == add_ln1116_13_reg_137141) & ~(7'd5 == add_ln1116_13_reg_137141) & ~(7'd79 == add_ln1116_13_reg_137141) & ~(7'd3 == add_ln1116_13_reg_137141) & ~(7'd125 == add_ln1116_13_reg_137141) & ~(7'd1 == add_ln1116_13_reg_137141) & ~(7'd63 == add_ln1116_13_reg_137141) & (ap_ST_fsm_state919 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_28_reg_134850) & ~(7'd61 == add_ln1116_28_reg_134850) & ~(7'd87 == add_ln1116_28_reg_134850) & ~(7'd59 == add_ln1116_28_reg_134850) & ~(7'd97 == add_ln1116_28_reg_134850) & ~(7'd57 == add_ln1116_28_reg_134850) & ~(7'd77 == add_ln1116_28_reg_134850) & ~(7'd55 == add_ln1116_28_reg_134850) & ~(7'd99 == add_ln1116_28_reg_134850) & ~(7'd53 == add_ln1116_28_reg_134850) & ~(7'd85 == add_ln1116_28_reg_134850) & ~(7'd51 == add_ln1116_28_reg_134850) & ~(7'd101 == add_ln1116_28_reg_134850) & ~(7'd49 == add_ln1116_28_reg_134850) & ~(7'd75 == add_ln1116_28_reg_134850) & ~(7'd47 == add_ln1116_28_reg_134850) & ~(7'd103 == add_ln1116_28_reg_134850) & ~(7'd45 == add_ln1116_28_reg_134850) & ~(7'd89 == add_ln1116_28_reg_134850) & ~(7'd43 == add_ln1116_28_reg_134850) & ~(7'd105 == add_ln1116_28_reg_134850) & ~(7'd41 == add_ln1116_28_reg_134850) & ~(7'd73 == add_ln1116_28_reg_134850) & ~(7'd39 == add_ln1116_28_reg_134850) & ~(7'd107 == add_ln1116_28_reg_134850) & ~(7'd37 == add_ln1116_28_reg_134850) & ~(7'd81 == add_ln1116_28_reg_134850) & ~(7'd35 == add_ln1116_28_reg_134850) & ~(7'd109 == add_ln1116_28_reg_134850) & ~(7'd33 == add_ln1116_28_reg_134850) & ~(7'd71 == add_ln1116_28_reg_134850) & ~(7'd31 == add_ln1116_28_reg_134850) & ~(7'd111 == add_ln1116_28_reg_134850) & ~(7'd29 == add_ln1116_28_reg_134850) & ~(7'd91 == add_ln1116_28_reg_134850) & ~(7'd27 == add_ln1116_28_reg_134850) & ~(7'd113 == add_ln1116_28_reg_134850) & ~(7'd25 == add_ln1116_28_reg_134850) & ~(7'd69 == add_ln1116_28_reg_134850) & ~(7'd23 == add_ln1116_28_reg_134850) & ~(7'd115 == add_ln1116_28_reg_134850) & ~(7'd21 == add_ln1116_28_reg_134850) & ~(7'd83 == add_ln1116_28_reg_134850) & ~(7'd19 == add_ln1116_28_reg_134850) & ~(7'd117 == add_ln1116_28_reg_134850) & ~(7'd17 == add_ln1116_28_reg_134850) & ~(7'd67 == add_ln1116_28_reg_134850) & ~(7'd15 == add_ln1116_28_reg_134850) & ~(7'd119 == add_ln1116_28_reg_134850) & ~(7'd13 == add_ln1116_28_reg_134850) & ~(7'd93 == add_ln1116_28_reg_134850) & ~(7'd11 == add_ln1116_28_reg_134850) & ~(7'd121 == add_ln1116_28_reg_134850) & ~(7'd9 == add_ln1116_28_reg_134850) & ~(7'd65 == add_ln1116_28_reg_134850) & ~(7'd7 == add_ln1116_28_reg_134850) & ~(7'd123 == add_ln1116_28_reg_134850) & ~(7'd5 == add_ln1116_28_reg_134850) & ~(7'd79 == add_ln1116_28_reg_134850) & ~(7'd3 == add_ln1116_28_reg_134850) & ~(7'd125 == add_ln1116_28_reg_134850) & ~(7'd1 == add_ln1116_28_reg_134850) & ~(7'd63 == add_ln1116_28_reg_134850) & (ap_ST_fsm_state537 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_22_reg_134445) & ~(7'd61 == add_ln1116_22_reg_134445) & ~(7'd87 == add_ln1116_22_reg_134445) & ~(7'd59 == add_ln1116_22_reg_134445) & ~(7'd97 == add_ln1116_22_reg_134445) & ~(7'd57 == add_ln1116_22_reg_134445) & ~(7'd77 == add_ln1116_22_reg_134445) & ~(7'd55 == add_ln1116_22_reg_134445) & ~(7'd99 == add_ln1116_22_reg_134445) & ~(7'd53 == add_ln1116_22_reg_134445) & ~(7'd85 == add_ln1116_22_reg_134445) & ~(7'd51 == add_ln1116_22_reg_134445) & ~(7'd101 == add_ln1116_22_reg_134445) & ~(7'd49 == add_ln1116_22_reg_134445) & ~(7'd75 == add_ln1116_22_reg_134445) & ~(7'd47 == add_ln1116_22_reg_134445) & ~(7'd103 == add_ln1116_22_reg_134445) & ~(7'd45 == add_ln1116_22_reg_134445) & ~(7'd89 == add_ln1116_22_reg_134445) & ~(7'd43 == add_ln1116_22_reg_134445) & ~(7'd105 == add_ln1116_22_reg_134445) & ~(7'd41 == add_ln1116_22_reg_134445) & ~(7'd73 == add_ln1116_22_reg_134445) & ~(7'd39 == add_ln1116_22_reg_134445) & ~(7'd107 == add_ln1116_22_reg_134445) & ~(7'd37 == add_ln1116_22_reg_134445) & ~(7'd81 == add_ln1116_22_reg_134445) & ~(7'd35 == add_ln1116_22_reg_134445) & ~(7'd109 == add_ln1116_22_reg_134445) & ~(7'd33 == add_ln1116_22_reg_134445) & ~(7'd71 == add_ln1116_22_reg_134445) & ~(7'd31 == add_ln1116_22_reg_134445) & ~(7'd111 == add_ln1116_22_reg_134445) & ~(7'd29 == add_ln1116_22_reg_134445) & ~(7'd91 == add_ln1116_22_reg_134445) & ~(7'd27 == add_ln1116_22_reg_134445) & ~(7'd113 == add_ln1116_22_reg_134445) & ~(7'd25 == add_ln1116_22_reg_134445) & ~(7'd69 == add_ln1116_22_reg_134445) & ~(7'd23 == add_ln1116_22_reg_134445) & ~(7'd115 == add_ln1116_22_reg_134445) & ~(7'd21 == add_ln1116_22_reg_134445) & ~(7'd83 == add_ln1116_22_reg_134445) & ~(7'd19 == add_ln1116_22_reg_134445) & ~(7'd117 == add_ln1116_22_reg_134445) & ~(7'd17 == add_ln1116_22_reg_134445) & ~(7'd67 == add_ln1116_22_reg_134445) & ~(7'd15 == add_ln1116_22_reg_134445) & ~(7'd119 == add_ln1116_22_reg_134445) & ~(7'd13 == add_ln1116_22_reg_134445) & ~(7'd93 == add_ln1116_22_reg_134445) & ~(7'd11 == add_ln1116_22_reg_134445) & ~(7'd121 == add_ln1116_22_reg_134445) & ~(7'd9 == add_ln1116_22_reg_134445) & ~(7'd65 == add_ln1116_22_reg_134445) & ~(7'd7 == add_ln1116_22_reg_134445) & ~(7'd123 == add_ln1116_22_reg_134445) & ~(7'd5 == add_ln1116_22_reg_134445) & ~(7'd79 == add_ln1116_22_reg_134445) & ~(7'd3 == add_ln1116_22_reg_134445) & ~(7'd125 == add_ln1116_22_reg_134445) & ~(7'd1 == add_ln1116_22_reg_134445) & ~(7'd63 == add_ln1116_22_reg_134445) & (ap_ST_fsm_state464 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_17_reg_133975) & ~(7'd61 == add_ln1116_17_reg_133975) & ~(7'd87 == add_ln1116_17_reg_133975) & ~(7'd59 == add_ln1116_17_reg_133975) & ~(7'd97 == add_ln1116_17_reg_133975) & ~(7'd57 == add_ln1116_17_reg_133975) & ~(7'd77 == add_ln1116_17_reg_133975) & ~(7'd55 == add_ln1116_17_reg_133975) & ~(7'd99 == add_ln1116_17_reg_133975) & ~(7'd53 == add_ln1116_17_reg_133975) & ~(7'd85 == add_ln1116_17_reg_133975) & ~(7'd51 == add_ln1116_17_reg_133975) & ~(7'd101 == add_ln1116_17_reg_133975) & ~(7'd49 == add_ln1116_17_reg_133975) & ~(7'd75 == add_ln1116_17_reg_133975) & ~(7'd47 == add_ln1116_17_reg_133975) & ~(7'd103 == add_ln1116_17_reg_133975) & ~(7'd45 == add_ln1116_17_reg_133975) & ~(7'd89 == add_ln1116_17_reg_133975) & ~(7'd43 == add_ln1116_17_reg_133975) & ~(7'd105 == add_ln1116_17_reg_133975) & ~(7'd41 == add_ln1116_17_reg_133975) & ~(7'd73 == add_ln1116_17_reg_133975) & ~(7'd39 == add_ln1116_17_reg_133975) & ~(7'd107 == add_ln1116_17_reg_133975) & ~(7'd37 == add_ln1116_17_reg_133975) & ~(7'd81 == add_ln1116_17_reg_133975) & ~(7'd35 == add_ln1116_17_reg_133975) & ~(7'd109 == add_ln1116_17_reg_133975) & ~(7'd33 == add_ln1116_17_reg_133975) & ~(7'd71 == add_ln1116_17_reg_133975) & ~(7'd31 == add_ln1116_17_reg_133975) & ~(7'd111 == add_ln1116_17_reg_133975) & ~(7'd29 == add_ln1116_17_reg_133975) & ~(7'd91 == add_ln1116_17_reg_133975) & ~(7'd27 == add_ln1116_17_reg_133975) & ~(7'd113 == add_ln1116_17_reg_133975) & ~(7'd25 == add_ln1116_17_reg_133975) & ~(7'd69 == add_ln1116_17_reg_133975) & ~(7'd23 == add_ln1116_17_reg_133975) & ~(7'd115 == add_ln1116_17_reg_133975) & ~(7'd21 == add_ln1116_17_reg_133975) & ~(7'd83 == add_ln1116_17_reg_133975) & ~(7'd19 == add_ln1116_17_reg_133975) & ~(7'd117 == add_ln1116_17_reg_133975) & ~(7'd17 == add_ln1116_17_reg_133975) & ~(7'd67 == add_ln1116_17_reg_133975) & ~(7'd15 == add_ln1116_17_reg_133975) & ~(7'd119 == add_ln1116_17_reg_133975) & ~(7'd13 == add_ln1116_17_reg_133975) & ~(7'd93 == add_ln1116_17_reg_133975) & ~(7'd11 == add_ln1116_17_reg_133975) & ~(7'd121 == add_ln1116_17_reg_133975) & ~(7'd9 == add_ln1116_17_reg_133975) & ~(7'd65 == add_ln1116_17_reg_133975) & ~(7'd7 == add_ln1116_17_reg_133975) & ~(7'd123 == add_ln1116_17_reg_133975) & ~(7'd5 == add_ln1116_17_reg_133975) & ~(7'd79 == add_ln1116_17_reg_133975) & ~(7'd3 == add_ln1116_17_reg_133975) & ~(7'd125 == add_ln1116_17_reg_133975) & ~(7'd1 == add_ln1116_17_reg_133975) & ~(7'd63 == add_ln1116_17_reg_133975) & (ap_ST_fsm_state387 == ap_CS_fsm)) | (~(7'd95 == add_ln1116_8_reg_133570) & ~(7'd61 == add_ln1116_8_reg_133570) & ~(7'd87 == add_ln1116_8_reg_133570) & ~(7'd59 == add_ln1116_8_reg_133570) & ~(7'd97 == add_ln1116_8_reg_133570) & ~(7'd57 == add_ln1116_8_reg_133570) & ~(7'd77 == add_ln1116_8_reg_133570) & ~(7'd55 == add_ln1116_8_reg_133570) & ~(7'd99 == add_ln1116_8_reg_133570) & ~(7'd53 == add_ln1116_8_reg_133570) & ~(7'd85 == add_ln1116_8_reg_133570) & ~(7'd51 == add_ln1116_8_reg_133570) & ~(7'd101 == add_ln1116_8_reg_133570) & ~(7'd49 == add_ln1116_8_reg_133570) & ~(7'd75 == add_ln1116_8_reg_133570) & ~(7'd47 == add_ln1116_8_reg_133570) & ~(7'd103 == add_ln1116_8_reg_133570) & ~(7'd45 == add_ln1116_8_reg_133570) & ~(7'd89 == add_ln1116_8_reg_133570) & ~(7'd43 == add_ln1116_8_reg_133570) & ~(7'd105 == add_ln1116_8_reg_133570) & ~(7'd41 == add_ln1116_8_reg_133570) & ~(7'd73 == add_ln1116_8_reg_133570) & ~(7'd39 == add_ln1116_8_reg_133570) & ~(7'd107 == add_ln1116_8_reg_133570) & ~(7'd37 == add_ln1116_8_reg_133570) & ~(7'd81 == add_ln1116_8_reg_133570) & ~(7'd35 == add_ln1116_8_reg_133570) & ~(7'd109 == add_ln1116_8_reg_133570) & ~(7'd33 == add_ln1116_8_reg_133570) & ~(7'd71 == add_ln1116_8_reg_133570) & ~(7'd31 == add_ln1116_8_reg_133570) & ~(7'd111 == add_ln1116_8_reg_133570) & ~(7'd29 == add_ln1116_8_reg_133570) & ~(7'd91 == add_ln1116_8_reg_133570) & ~(7'd27 == add_ln1116_8_reg_133570) & ~(7'd113 == add_ln1116_8_reg_133570) & ~(7'd25 == add_ln1116_8_reg_133570) & ~(7'd69 == add_ln1116_8_reg_133570) & ~(7'd23 == add_ln1116_8_reg_133570) & ~(7'd115 == add_ln1116_8_reg_133570) & ~(7'd21 == add_ln1116_8_reg_133570) & ~(7'd83 == add_ln1116_8_reg_133570) & ~(7'd19 == add_ln1116_8_reg_133570) & ~(7'd117 == add_ln1116_8_reg_133570) & ~(7'd17 == add_ln1116_8_reg_133570) & ~(7'd67 == add_ln1116_8_reg_133570) & ~(7'd15 == add_ln1116_8_reg_133570) & ~(7'd119 == add_ln1116_8_reg_133570) & ~(7'd13 == add_ln1116_8_reg_133570) & ~(7'd93 == add_ln1116_8_reg_133570) & ~(7'd11 == add_ln1116_8_reg_133570) & ~(7'd121 == add_ln1116_8_reg_133570) & ~(7'd9 == add_ln1116_8_reg_133570) & ~(7'd65 == add_ln1116_8_reg_133570) & ~(7'd7 == add_ln1116_8_reg_133570) & ~(7'd123 == add_ln1116_8_reg_133570) & ~(7'd5 == add_ln1116_8_reg_133570) & ~(7'd79 == add_ln1116_8_reg_133570) & ~(7'd3 == add_ln1116_8_reg_133570) & ~(7'd125 == add_ln1116_8_reg_133570) & ~(7'd1 == add_ln1116_8_reg_133570) & ~(7'd63 == add_ln1116_8_reg_133570) & (ap_ST_fsm_state314 == ap_CS_fsm)))) begin + reg_100598 <= data_127_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state995 == ap_CS_fsm) | (ap_ST_fsm_state921 == ap_CS_fsm) | (ap_ST_fsm_state87 == ap_CS_fsm) | (ap_ST_fsm_state844 == ap_CS_fsm) | (ap_ST_fsm_state769 == ap_CS_fsm) | (ap_ST_fsm_state692 == ap_CS_fsm) | (ap_ST_fsm_state618 == ap_CS_fsm) | (ap_ST_fsm_state539 == ap_CS_fsm) | (ap_ST_fsm_state466 == ap_CS_fsm) | (ap_ST_fsm_state390 == ap_CS_fsm) | (ap_ST_fsm_state316 == ap_CS_fsm) | (ap_ST_fsm_state239 == ap_CS_fsm) | (ap_ST_fsm_state2354 == ap_CS_fsm) | (ap_ST_fsm_state2281 == ap_CS_fsm) | (ap_ST_fsm_state2205 == ap_CS_fsm) | (ap_ST_fsm_state2131 == ap_CS_fsm) | (ap_ST_fsm_state2054 == ap_CS_fsm) | (ap_ST_fsm_state1979 == ap_CS_fsm) | (ap_ST_fsm_state1902 == ap_CS_fsm) | (ap_ST_fsm_state1828 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1677 == ap_CS_fsm) | (ap_ST_fsm_state164 == ap_CS_fsm) | (ap_ST_fsm_state1601 == ap_CS_fsm) | (ap_ST_fsm_state1527 == ap_CS_fsm) | (ap_ST_fsm_state12 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1298 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1144 == ap_CS_fsm) | (ap_ST_fsm_state1071 == ap_CS_fsm))) begin + reg_100634 <= w5_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state163 == ap_CS_fsm) | ((ap_ST_fsm_state160 == ap_CS_fsm) & ((or_ln223_8_reg_132680 == 1'd1) | (or_ln223_15_fu_103192_p2 == 1'd1))))) begin + reg_100638 <= grp_fu_99058_p2; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd95 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd95 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd95 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd95 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd95 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd95 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd95 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd95 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd95 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd95 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd95 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd95 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd95 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd95 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd95 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd95 == add_ln1116_8_reg_133570)))) begin + reg_100643 <= data_95_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd61 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd61 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd61 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd61 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd61 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd61 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd61 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd61 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd61 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd61 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd61 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd61 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd61 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd61 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd61 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd61 == add_ln1116_8_reg_133570)))) begin + reg_100663 <= data_61_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd87 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd87 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd87 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd87 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd87 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd87 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd87 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd87 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd87 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd87 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd87 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd87 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd87 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd87 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd87 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd87 == add_ln1116_8_reg_133570)))) begin + reg_100683 <= data_87_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd59 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd59 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd59 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd59 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd59 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd59 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd59 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd59 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd59 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd59 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd59 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd59 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd59 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd59 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd59 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd59 == add_ln1116_8_reg_133570)))) begin + reg_100703 <= data_59_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd97 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd97 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd97 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd97 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd97 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd97 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd97 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd97 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd97 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd97 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd97 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd97 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd97 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd97 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd97 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd97 == add_ln1116_8_reg_133570)))) begin + reg_100723 <= data_97_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd57 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd57 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd57 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd57 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd57 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd57 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd57 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd57 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd57 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd57 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd57 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd57 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd57 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd57 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd57 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd57 == add_ln1116_8_reg_133570)))) begin + reg_100743 <= data_57_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd77 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd77 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd77 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd77 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd77 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd77 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd77 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd77 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd77 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd77 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd77 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd77 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd77 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd77 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd77 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd77 == add_ln1116_8_reg_133570)))) begin + reg_100763 <= data_77_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd55 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd55 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd55 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd55 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd55 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd55 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd55 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd55 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd55 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd55 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd55 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd55 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd55 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd55 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd55 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd55 == add_ln1116_8_reg_133570)))) begin + reg_100783 <= data_55_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd99 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd99 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd99 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd99 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd99 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd99 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd99 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd99 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd99 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd99 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd99 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd99 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd99 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd99 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd99 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd99 == add_ln1116_8_reg_133570)))) begin + reg_100803 <= data_99_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd53 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd53 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd53 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd53 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd53 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd53 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd53 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd53 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd53 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd53 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd53 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd53 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd53 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd53 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd53 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd53 == add_ln1116_8_reg_133570)))) begin + reg_100823 <= data_53_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd85 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd85 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd85 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd85 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd85 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd85 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd85 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd85 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd85 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd85 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd85 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd85 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd85 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd85 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd85 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd85 == add_ln1116_8_reg_133570)))) begin + reg_100843 <= data_85_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd51 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd51 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd51 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd51 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd51 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd51 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd51 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd51 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd51 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd51 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd51 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd51 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd51 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd51 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd51 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd51 == add_ln1116_8_reg_133570)))) begin + reg_100863 <= data_51_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd101 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd101 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd101 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd101 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd101 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd101 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd101 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd101 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd101 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd101 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd101 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd101 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd101 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd101 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd101 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd101 == add_ln1116_8_reg_133570)))) begin + reg_100883 <= data_101_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd49 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd49 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd49 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd49 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd49 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd49 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd49 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd49 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd49 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd49 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd49 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd49 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd49 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd49 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd49 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd49 == add_ln1116_8_reg_133570)))) begin + reg_100903 <= data_49_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd75 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd75 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd75 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd75 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd75 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd75 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd75 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd75 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd75 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd75 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd75 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd75 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd75 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd75 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd75 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd75 == add_ln1116_8_reg_133570)))) begin + reg_100923 <= data_75_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd47 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd47 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd47 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd47 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd47 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd47 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd47 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd47 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd47 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd47 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd47 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd47 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd47 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd47 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd47 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd47 == add_ln1116_8_reg_133570)))) begin + reg_100943 <= data_47_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd103 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd103 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd103 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd103 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd103 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd103 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd103 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd103 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd103 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd103 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd103 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd103 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd103 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd103 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd103 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd103 == add_ln1116_8_reg_133570)))) begin + reg_100963 <= data_103_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd45 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd45 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd45 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd45 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd45 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd45 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd45 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd45 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd45 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd45 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd45 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd45 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd45 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd45 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd45 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd45 == add_ln1116_8_reg_133570)))) begin + reg_100983 <= data_45_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd89 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd89 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd89 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd89 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd89 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd89 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd89 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd89 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd89 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd89 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd89 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd89 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd89 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd89 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd89 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd89 == add_ln1116_8_reg_133570)))) begin + reg_101003 <= data_89_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd43 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd43 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd43 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd43 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd43 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd43 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd43 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd43 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd43 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd43 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd43 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd43 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd43 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd43 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd43 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd43 == add_ln1116_8_reg_133570)))) begin + reg_101023 <= data_43_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd105 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd105 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd105 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd105 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd105 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd105 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd105 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd105 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd105 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd105 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd105 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd105 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd105 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd105 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd105 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd105 == add_ln1116_8_reg_133570)))) begin + reg_101043 <= data_105_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd41 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd41 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd41 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd41 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd41 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd41 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd41 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd41 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd41 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd41 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd41 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd41 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd41 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd41 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd41 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd41 == add_ln1116_8_reg_133570)))) begin + reg_101063 <= data_41_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd73 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd73 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd73 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd73 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd73 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd73 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd73 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd73 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd73 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd73 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd73 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd73 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd73 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd73 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd73 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd73 == add_ln1116_8_reg_133570)))) begin + reg_101083 <= data_73_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd39 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd39 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd39 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd39 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd39 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd39 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd39 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd39 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd39 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd39 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd39 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd39 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd39 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd39 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd39 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd39 == add_ln1116_8_reg_133570)))) begin + reg_101103 <= data_39_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd107 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd107 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd107 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd107 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd107 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd107 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd107 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd107 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd107 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd107 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd107 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd107 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd107 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd107 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd107 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd107 == add_ln1116_8_reg_133570)))) begin + reg_101123 <= data_107_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd37 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd37 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd37 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd37 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd37 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd37 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd37 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd37 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd37 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd37 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd37 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd37 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd37 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd37 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd37 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd37 == add_ln1116_8_reg_133570)))) begin + reg_101143 <= data_37_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd81 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd81 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd81 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd81 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd81 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd81 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd81 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd81 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd81 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd81 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd81 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd81 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd81 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd81 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd81 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd81 == add_ln1116_8_reg_133570)))) begin + reg_101163 <= data_81_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd35 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd35 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd35 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd35 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd35 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd35 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd35 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd35 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd35 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd35 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd35 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd35 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd35 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd35 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd35 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd35 == add_ln1116_8_reg_133570)))) begin + reg_101183 <= data_35_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd109 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd109 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd109 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd109 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd109 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd109 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd109 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd109 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd109 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd109 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd109 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd109 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd109 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd109 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd109 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd109 == add_ln1116_8_reg_133570)))) begin + reg_101203 <= data_109_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd33 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd33 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd33 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd33 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd33 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd33 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd33 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd33 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd33 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd33 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd33 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd33 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd33 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd33 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd33 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd33 == add_ln1116_8_reg_133570)))) begin + reg_101223 <= data_33_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd71 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd71 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd71 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd71 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd71 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd71 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd71 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd71 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd71 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd71 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd71 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd71 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd71 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd71 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd71 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd71 == add_ln1116_8_reg_133570)))) begin + reg_101243 <= data_71_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd31 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd31 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd31 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd31 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd31 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd31 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd31 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd31 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd31 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd31 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd31 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd31 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd31 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd31 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd31 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd31 == add_ln1116_8_reg_133570)))) begin + reg_101263 <= data_31_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd111 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd111 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd111 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd111 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd111 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd111 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd111 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd111 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd111 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd111 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd111 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd111 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd111 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd111 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd111 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd111 == add_ln1116_8_reg_133570)))) begin + reg_101283 <= data_111_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd29 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd29 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd29 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd29 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd29 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd29 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd29 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd29 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd29 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd29 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd29 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd29 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd29 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd29 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd29 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd29 == add_ln1116_8_reg_133570)))) begin + reg_101303 <= data_29_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd91 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd91 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd91 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd91 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd91 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd91 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd91 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd91 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd91 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd91 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd91 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd91 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd91 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd91 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd91 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd91 == add_ln1116_8_reg_133570)))) begin + reg_101323 <= data_91_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd27 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd27 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd27 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd27 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd27 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd27 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd27 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd27 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd27 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd27 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd27 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd27 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd27 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd27 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd27 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd27 == add_ln1116_8_reg_133570)))) begin + reg_101343 <= data_27_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd113 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd113 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd113 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd113 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd113 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd113 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd113 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd113 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd113 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd113 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd113 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd113 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd113 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd113 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd113 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd113 == add_ln1116_8_reg_133570)))) begin + reg_101363 <= data_113_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd25 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd25 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd25 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd25 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd25 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd25 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd25 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd25 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd25 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd25 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd25 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd25 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd25 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd25 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd25 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd25 == add_ln1116_8_reg_133570)))) begin + reg_101383 <= data_25_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd69 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd69 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd69 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd69 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd69 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd69 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd69 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd69 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd69 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd69 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd69 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd69 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd69 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd69 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd69 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd69 == add_ln1116_8_reg_133570)))) begin + reg_101403 <= data_69_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd23 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd23 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd23 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd23 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd23 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd23 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd23 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd23 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd23 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd23 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd23 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd23 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd23 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd23 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd23 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd23 == add_ln1116_8_reg_133570)))) begin + reg_101423 <= data_23_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd115 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd115 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd115 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd115 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd115 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd115 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd115 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd115 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd115 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd115 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd115 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd115 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd115 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd115 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd115 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd115 == add_ln1116_8_reg_133570)))) begin + reg_101443 <= data_115_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd21 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd21 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd21 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd21 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd21 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd21 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd21 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd21 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd21 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd21 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd21 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd21 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd21 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd21 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd21 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd21 == add_ln1116_8_reg_133570)))) begin + reg_101463 <= data_21_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd83 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd83 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd83 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd83 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd83 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd83 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd83 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd83 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd83 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd83 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd83 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd83 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd83 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd83 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd83 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd83 == add_ln1116_8_reg_133570)))) begin + reg_101483 <= data_83_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd19 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd19 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd19 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd19 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd19 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd19 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd19 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd19 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd19 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd19 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd19 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd19 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd19 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd19 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd19 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd19 == add_ln1116_8_reg_133570)))) begin + reg_101503 <= data_19_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd117 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd117 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd117 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd117 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd117 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd117 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd117 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd117 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd117 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd117 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd117 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd117 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd117 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd117 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd117 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd117 == add_ln1116_8_reg_133570)))) begin + reg_101523 <= data_117_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd17 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd17 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd17 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd17 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd17 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd17 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd17 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd17 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd17 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd17 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd17 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd17 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd17 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd17 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd17 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd17 == add_ln1116_8_reg_133570)))) begin + reg_101543 <= data_17_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd67 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd67 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd67 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd67 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd67 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd67 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd67 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd67 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd67 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd67 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd67 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd67 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd67 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd67 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd67 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd67 == add_ln1116_8_reg_133570)))) begin + reg_101563 <= data_67_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd15 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd15 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd15 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd15 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd15 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd15 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd15 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd15 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd15 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd15 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd15 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd15 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd15 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd15 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd15 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd15 == add_ln1116_8_reg_133570)))) begin + reg_101583 <= data_15_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd119 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd119 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd119 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd119 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd119 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd119 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd119 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd119 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd119 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd119 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd119 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd119 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd119 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd119 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd119 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd119 == add_ln1116_8_reg_133570)))) begin + reg_101603 <= data_119_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd13 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd13 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd13 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd13 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd13 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd13 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd13 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd13 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd13 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd13 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd13 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd13 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd13 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd13 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd13 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd13 == add_ln1116_8_reg_133570)))) begin + reg_101623 <= data_13_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd93 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd93 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd93 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd93 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd93 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd93 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd93 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd93 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd93 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd93 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd93 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd93 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd93 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd93 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd93 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd93 == add_ln1116_8_reg_133570)))) begin + reg_101643 <= data_93_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd11 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd11 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd11 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd11 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd11 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd11 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd11 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd11 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd11 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd11 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd11 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd11 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd11 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd11 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd11 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd11 == add_ln1116_8_reg_133570)))) begin + reg_101663 <= data_11_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd121 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd121 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd121 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd121 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd121 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd121 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd121 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd121 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd121 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd121 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd121 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd121 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd121 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd121 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd121 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd121 == add_ln1116_8_reg_133570)))) begin + reg_101683 <= data_121_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd9 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd9 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd9 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd9 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd9 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd9 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd9 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd9 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd9 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd9 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd9 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd9 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd9 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd9 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd9 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd9 == add_ln1116_8_reg_133570)))) begin + reg_101703 <= data_9_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd65 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd65 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd65 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd65 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd65 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd65 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd65 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd65 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd65 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd65 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd65 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd65 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd65 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd65 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd65 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd65 == add_ln1116_8_reg_133570)))) begin + reg_101723 <= data_65_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd7 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd7 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd7 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd7 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd7 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd7 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd7 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd7 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd7 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd7 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd7 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd7 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd7 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd7 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd7 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd7 == add_ln1116_8_reg_133570)))) begin + reg_101743 <= data_7_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd123 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd123 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd123 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd123 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd123 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd123 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd123 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd123 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd123 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd123 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd123 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd123 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd123 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd123 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd123 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd123 == add_ln1116_8_reg_133570)))) begin + reg_101763 <= data_123_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd5 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd5 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd5 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd5 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd5 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd5 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd5 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd5 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd5 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd5 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd5 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd5 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd5 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd5 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd5 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd5 == add_ln1116_8_reg_133570)))) begin + reg_101783 <= data_5_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd79 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd79 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd79 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd79 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd79 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd79 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd79 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd79 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd79 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd79 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd79 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd79 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd79 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd79 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd79 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd79 == add_ln1116_8_reg_133570)))) begin + reg_101803 <= data_79_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd3 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd3 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd3 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd3 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd3 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd3 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd3 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd3 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd3 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd3 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd3 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd3 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd3 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd3 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd3 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd3 == add_ln1116_8_reg_133570)))) begin + reg_101823 <= data_3_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd125 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd125 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd125 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd125 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd125 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd125 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd125 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd125 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd125 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd125 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd125 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd125 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd125 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd125 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd125 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd125 == add_ln1116_8_reg_133570)))) begin + reg_101843 <= data_125_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd1 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd1 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd1 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd1 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd1 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd1 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd1 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd1 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd1 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd1 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd1 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd1 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd1 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd1 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd1 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd1 == add_ln1116_8_reg_133570)))) begin + reg_101863 <= data_1_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state2352 == ap_CS_fsm) & (7'd63 == add_ln1116_31_reg_145576)) | ((ap_ST_fsm_state2279 == ap_CS_fsm) & (7'd63 == add_ln1116_27_reg_145171)) | ((ap_ST_fsm_state2202 == ap_CS_fsm) & (7'd63 == add_ln1116_24_reg_144701)) | ((ap_ST_fsm_state2129 == ap_CS_fsm) & (7'd63 == add_ln1116_15_reg_144296)) | ((ap_ST_fsm_state1748 == ap_CS_fsm) & (7'd63 == add_ln1116_29_reg_142013)) | ((ap_ST_fsm_state1675 == ap_CS_fsm) & (7'd63 == add_ln1116_25_reg_141608)) | ((ap_ST_fsm_state1598 == ap_CS_fsm) & (7'd63 == add_ln1116_20_reg_141148)) | ((ap_ST_fsm_state1525 == ap_CS_fsm) & (7'd63 == add_ln1116_12_reg_140743)) | ((ap_ST_fsm_state1142 == ap_CS_fsm) & (7'd63 == add_ln1116_30_reg_138421)) | ((ap_ST_fsm_state1069 == ap_CS_fsm) & (7'd63 == add_ln1116_26_reg_138016)) | ((ap_ST_fsm_state992 == ap_CS_fsm) & (7'd63 == add_ln1116_21_reg_137546)) | ((ap_ST_fsm_state919 == ap_CS_fsm) & (7'd63 == add_ln1116_13_reg_137141)) | ((ap_ST_fsm_state537 == ap_CS_fsm) & (7'd63 == add_ln1116_28_reg_134850)) | ((ap_ST_fsm_state464 == ap_CS_fsm) & (7'd63 == add_ln1116_22_reg_134445)) | ((ap_ST_fsm_state387 == ap_CS_fsm) & (7'd63 == add_ln1116_17_reg_133975)) | ((ap_ST_fsm_state314 == ap_CS_fsm) & (7'd63 == add_ln1116_8_reg_133570)))) begin + reg_101883 <= data_63_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state768 == ap_CS_fsm) | ((ap_ST_fsm_state765 == ap_CS_fsm) & ((or_ln223_13_reg_136251 == 1'd1) | (or_ln223_22_fu_106609_p2 == 1'd1))))) begin + reg_101903 <= grp_fu_99126_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state1374 == ap_CS_fsm) | ((ap_ST_fsm_state1371 == ap_CS_fsm) & ((or_ln223_11_reg_139731 == 1'd1) | (or_ln223_21_fu_110053_p2 == 1'd1))))) begin + reg_101908 <= grp_fu_99194_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state1978 == ap_CS_fsm) | ((ap_ST_fsm_state1975 == ap_CS_fsm) & ((or_ln223_19_reg_143411 == 1'd1) | (or_ln223_26_fu_113452_p2 == 1'd1))))) begin + reg_101913 <= grp_fu_99262_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state11 == ap_CS_fsm) | ((ap_ST_fsm_state8 == ap_CS_fsm) & ((or_ln223_reg_131762 == 1'd1) | (or_ln223_3_fu_102310_p2 == 1'd1))))) begin + reg_99313 <= grp_fu_99041_p2; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd84 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd84 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd84 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd84 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd84 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd84 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd84 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd84 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd84 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd84 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd84 == add_ln1116_6_reg_135778)) | ((7'd84 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd84 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd84 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd84 == add_ln1116_4_reg_132207)) | ((7'd84 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99318 <= data_84_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd62 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd62 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd62 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd62 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd62 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd62 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd62 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd62 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd62 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd62 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd62 == add_ln1116_6_reg_135778)) | ((7'd62 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd62 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd62 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd62 == add_ln1116_4_reg_132207)) | ((7'd62 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99338 <= data_62_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd96 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd96 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd96 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd96 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd96 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd96 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd96 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd96 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd96 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd96 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd96 == add_ln1116_6_reg_135778)) | ((7'd96 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd96 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd96 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd96 == add_ln1116_4_reg_132207)) | ((7'd96 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99358 <= data_96_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd60 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd60 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd60 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd60 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd60 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd60 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd60 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd60 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd60 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd60 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd60 == add_ln1116_6_reg_135778)) | ((7'd60 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd60 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd60 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd60 == add_ln1116_4_reg_132207)) | ((7'd60 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99378 <= data_60_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd78 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd78 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd78 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd78 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd78 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd78 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd78 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd78 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd78 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd78 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd78 == add_ln1116_6_reg_135778)) | ((7'd78 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd78 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd78 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd78 == add_ln1116_4_reg_132207)) | ((7'd78 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99398 <= data_78_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd58 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd58 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd58 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd58 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd58 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd58 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd58 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd58 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd58 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd58 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd58 == add_ln1116_6_reg_135778)) | ((7'd58 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd58 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd58 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd58 == add_ln1116_4_reg_132207)) | ((7'd58 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99418 <= data_58_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd98 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd98 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd98 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd98 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd98 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd98 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd98 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd98 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd98 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd98 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd98 == add_ln1116_6_reg_135778)) | ((7'd98 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd98 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd98 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd98 == add_ln1116_4_reg_132207)) | ((7'd98 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99438 <= data_98_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd56 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd56 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd56 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd56 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd56 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd56 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd56 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd56 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd56 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd56 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd56 == add_ln1116_6_reg_135778)) | ((7'd56 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd56 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd56 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd56 == add_ln1116_4_reg_132207)) | ((7'd56 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99458 <= data_56_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd88 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd88 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd88 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd88 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd88 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd88 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd88 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd88 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd88 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd88 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd88 == add_ln1116_6_reg_135778)) | ((7'd88 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd88 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd88 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd88 == add_ln1116_4_reg_132207)) | ((7'd88 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99478 <= data_88_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd54 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd54 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd54 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd54 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd54 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd54 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd54 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd54 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd54 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd54 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd54 == add_ln1116_6_reg_135778)) | ((7'd54 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd54 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd54 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd54 == add_ln1116_4_reg_132207)) | ((7'd54 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99498 <= data_54_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd100 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd100 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd100 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd100 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd100 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd100 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd100 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd100 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd100 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd100 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd100 == add_ln1116_6_reg_135778)) | ((7'd100 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd100 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd100 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd100 == add_ln1116_4_reg_132207)) | ((7'd100 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99518 <= data_100_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd52 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd52 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd52 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd52 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd52 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd52 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd52 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd52 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd52 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd52 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd52 == add_ln1116_6_reg_135778)) | ((7'd52 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd52 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd52 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd52 == add_ln1116_4_reg_132207)) | ((7'd52 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99538 <= data_52_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd76 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd76 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd76 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd76 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd76 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd76 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd76 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd76 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd76 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd76 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd76 == add_ln1116_6_reg_135778)) | ((7'd76 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd76 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd76 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd76 == add_ln1116_4_reg_132207)) | ((7'd76 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99558 <= data_76_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd50 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd50 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd50 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd50 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd50 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd50 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd50 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd50 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd50 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd50 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd50 == add_ln1116_6_reg_135778)) | ((7'd50 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd50 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd50 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd50 == add_ln1116_4_reg_132207)) | ((7'd50 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99578 <= data_50_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd102 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd102 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd102 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd102 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd102 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd102 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd102 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd102 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd102 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd102 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd102 == add_ln1116_6_reg_135778)) | ((7'd102 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd102 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd102 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd102 == add_ln1116_4_reg_132207)) | ((7'd102 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99598 <= data_102_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd48 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd48 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd48 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd48 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd48 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd48 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd48 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd48 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd48 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd48 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd48 == add_ln1116_6_reg_135778)) | ((7'd48 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd48 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd48 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd48 == add_ln1116_4_reg_132207)) | ((7'd48 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99618 <= data_48_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd82 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd82 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd82 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd82 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd82 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd82 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd82 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd82 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd82 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd82 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd82 == add_ln1116_6_reg_135778)) | ((7'd82 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd82 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd82 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd82 == add_ln1116_4_reg_132207)) | ((7'd82 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99638 <= data_82_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd46 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd46 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd46 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd46 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd46 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd46 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd46 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd46 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd46 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd46 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd46 == add_ln1116_6_reg_135778)) | ((7'd46 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd46 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd46 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd46 == add_ln1116_4_reg_132207)) | ((7'd46 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99658 <= data_46_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd104 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd104 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd104 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd104 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd104 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd104 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd104 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd104 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd104 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd104 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd104 == add_ln1116_6_reg_135778)) | ((7'd104 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd104 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd104 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd104 == add_ln1116_4_reg_132207)) | ((7'd104 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99678 <= data_104_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd44 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd44 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd44 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd44 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd44 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd44 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd44 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd44 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd44 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd44 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd44 == add_ln1116_6_reg_135778)) | ((7'd44 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd44 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd44 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd44 == add_ln1116_4_reg_132207)) | ((7'd44 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99698 <= data_44_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd74 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd74 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd74 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd74 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd74 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd74 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd74 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd74 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd74 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd74 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd74 == add_ln1116_6_reg_135778)) | ((7'd74 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd74 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd74 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd74 == add_ln1116_4_reg_132207)) | ((7'd74 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99718 <= data_74_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd42 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd42 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd42 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd42 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd42 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd42 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd42 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd42 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd42 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd42 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd42 == add_ln1116_6_reg_135778)) | ((7'd42 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd42 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd42 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd42 == add_ln1116_4_reg_132207)) | ((7'd42 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99738 <= data_42_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd106 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd106 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd106 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd106 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd106 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd106 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd106 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd106 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd106 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd106 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd106 == add_ln1116_6_reg_135778)) | ((7'd106 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd106 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd106 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd106 == add_ln1116_4_reg_132207)) | ((7'd106 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99758 <= data_106_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd40 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd40 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd40 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd40 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd40 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd40 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd40 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd40 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd40 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd40 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd40 == add_ln1116_6_reg_135778)) | ((7'd40 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd40 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd40 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd40 == add_ln1116_4_reg_132207)) | ((7'd40 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99778 <= data_40_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd90 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd90 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd90 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd90 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd90 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd90 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd90 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd90 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd90 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd90 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd90 == add_ln1116_6_reg_135778)) | ((7'd90 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd90 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd90 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd90 == add_ln1116_4_reg_132207)) | ((7'd90 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99798 <= data_90_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd38 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd38 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd38 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd38 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd38 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd38 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd38 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd38 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd38 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd38 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd38 == add_ln1116_6_reg_135778)) | ((7'd38 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd38 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd38 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd38 == add_ln1116_4_reg_132207)) | ((7'd38 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99818 <= data_38_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd108 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd108 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd108 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd108 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd108 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd108 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd108 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd108 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd108 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd108 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd108 == add_ln1116_6_reg_135778)) | ((7'd108 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd108 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd108 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd108 == add_ln1116_4_reg_132207)) | ((7'd108 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99838 <= data_108_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd36 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd36 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd36 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd36 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd36 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd36 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd36 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd36 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd36 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd36 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd36 == add_ln1116_6_reg_135778)) | ((7'd36 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd36 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd36 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd36 == add_ln1116_4_reg_132207)) | ((7'd36 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99858 <= data_36_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd72 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd72 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd72 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd72 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd72 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd72 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd72 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd72 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd72 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd72 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd72 == add_ln1116_6_reg_135778)) | ((7'd72 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd72 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd72 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd72 == add_ln1116_4_reg_132207)) | ((7'd72 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99878 <= data_72_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd34 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd34 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd34 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd34 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd34 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd34 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd34 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd34 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd34 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd34 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd34 == add_ln1116_6_reg_135778)) | ((7'd34 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd34 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd34 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd34 == add_ln1116_4_reg_132207)) | ((7'd34 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99898 <= data_34_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd110 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd110 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd110 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd110 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd110 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd110 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd110 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd110 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd110 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd110 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd110 == add_ln1116_6_reg_135778)) | ((7'd110 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd110 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd110 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd110 == add_ln1116_4_reg_132207)) | ((7'd110 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99918 <= data_110_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd32 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd32 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd32 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd32 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd32 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd32 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd32 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd32 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd32 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd32 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd32 == add_ln1116_6_reg_135778)) | ((7'd32 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd32 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd32 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd32 == add_ln1116_4_reg_132207)) | ((7'd32 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99938 <= data_32_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd86 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd86 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd86 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd86 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd86 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd86 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd86 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd86 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd86 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd86 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd86 == add_ln1116_6_reg_135778)) | ((7'd86 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd86 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd86 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd86 == add_ln1116_4_reg_132207)) | ((7'd86 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99958 <= data_86_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd30 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd30 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd30 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd30 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd30 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd30 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd30 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd30 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd30 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd30 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd30 == add_ln1116_6_reg_135778)) | ((7'd30 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd30 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd30 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd30 == add_ln1116_4_reg_132207)) | ((7'd30 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99978 <= data_30_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((7'd112 == add_ln1116_23_reg_143834) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((7'd112 == add_ln1116_14_reg_143436) & (ap_ST_fsm_state1976 == ap_CS_fsm)) | ((7'd112 == add_ln1116_9_reg_142942) & (ap_ST_fsm_state1899 == ap_CS_fsm)) | ((7'd112 == add_ln1116_3_reg_142532) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((7'd112 == add_ln1116_18_reg_140281) & (ap_ST_fsm_state1447 == ap_CS_fsm)) | ((7'd112 == add_ln1116_10_reg_139883) & (ap_ST_fsm_state1372 == ap_CS_fsm)) | ((7'd112 == add_ln1116_5_reg_139399) & (ap_ST_fsm_state1295 == ap_CS_fsm)) | ((7'd112 == add_ln1116_1_reg_138989) & (ap_ST_fsm_state1221 == ap_CS_fsm)) | ((ap_ST_fsm_state841 == ap_CS_fsm) & (7'd112 == add_ln1116_19_reg_136674)) | ((ap_ST_fsm_state766 == ap_CS_fsm) & (7'd112 == add_ln1116_11_reg_136276)) | ((ap_ST_fsm_state689 == ap_CS_fsm) & (7'd112 == add_ln1116_6_reg_135778)) | ((7'd112 == add_ln1116_2_reg_135368) & (ap_ST_fsm_state615 == ap_CS_fsm)) | ((7'd112 == add_ln1116_16_reg_133103) & (ap_ST_fsm_state236 == ap_CS_fsm)) | ((7'd112 == add_ln1116_7_reg_132705) & (ap_ST_fsm_state161 == ap_CS_fsm)) | ((ap_ST_fsm_state84 == ap_CS_fsm) & (7'd112 == add_ln1116_4_reg_132207)) | ((7'd112 == add_ln1116_reg_131809) & (ap_ST_fsm_state9 == ap_CS_fsm)))) begin + reg_99998 <= data_112_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln204_1_fu_108914_p2 == 1'd0) & (ap_ST_fsm_state1217 == ap_CS_fsm))) begin + sext_ln221_1_reg_138918 <= sext_ln221_1_fu_108959_p1; + sext_ln231_1_reg_138936[2 : 0] <= sext_ln231_1_fu_108986_p1[2 : 0]; + trunc_ln221_1_reg_138913 <= trunc_ln221_1_fu_108920_p1; + zext_ln216_5_reg_138924[18 : 0] <= zext_ln216_5_fu_108963_p1[18 : 0]; + zext_ln231_1_reg_138930[2 : 0] <= zext_ln231_1_fu_108982_p1[2 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state611 == ap_CS_fsm) & (icmp_ln204_2_fu_105463_p2 == 1'd0))) begin + sext_ln221_2_reg_135298 <= sext_ln221_2_fu_105508_p1; + sext_ln231_2_reg_135310[2 : 0] <= sext_ln231_2_fu_105523_p1[2 : 0]; + trunc_ln221_2_reg_135293 <= trunc_ln221_2_fu_105469_p1; + zext_ln216_6_reg_135304[17 : 0] <= zext_ln216_6_fu_105512_p1[17 : 0]; + zext_ln231_2_reg_135316[2 : 0] <= zext_ln231_2_fu_105535_p1[2 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state1822 == ap_CS_fsm) & (icmp_ln204_3_fu_112317_p2 == 1'd0))) begin + sext_ln221_3_reg_142461 <= sext_ln221_3_fu_112362_p1; + sext_ln231_3_reg_142479[2 : 0] <= sext_ln231_3_fu_112389_p1[2 : 0]; + trunc_ln221_3_reg_142456 <= trunc_ln221_3_fu_112323_p1; + zext_ln216_7_reg_142467[18 : 0] <= zext_ln216_7_fu_112366_p1[18 : 0]; + zext_ln231_3_reg_142473[2 : 0] <= zext_ln231_3_fu_112385_p1[2 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_1_fu_109593_p2 == 1'd1) & (icmp_ln208_1_fu_109384_p2 == 1'd1) & (ap_ST_fsm_state1258 == ap_CS_fsm))) begin + sext_ln221_5_reg_139757 <= sext_ln221_5_fu_109752_p1; + sext_ln231_5_reg_139775[2 : 1] <= sext_ln231_5_fu_109785_p1[2 : 1]; + zext_ln216_9_reg_139763[18 : 0] <= zext_ln216_9_fu_109756_p1[18 : 0]; + zext_ln231_16_reg_139769[2 : 1] <= zext_ln231_16_fu_109781_p1[2 : 1]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_3_fu_112994_p2 == 1'd1) & (icmp_ln208_3_fu_112786_p2 == 1'd1) & (ap_ST_fsm_state1862 == ap_CS_fsm))) begin + sext_ln221_7_reg_143306 <= sext_ln221_7_fu_113147_p1; + sext_ln231_7_reg_143324[2 : 1] <= sext_ln231_7_fu_113180_p1[2 : 1]; + zext_ln216_11_reg_143312[18 : 0] <= zext_ln216_11_fu_113151_p1[18 : 0]; + zext_ln231_24_reg_143318[2 : 1] <= zext_ln231_24_fu_113176_p1[2 : 1]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state5 == ap_CS_fsm) & (icmp_ln204_fu_102042_p2 == 1'd0))) begin + sext_ln221_reg_131739 <= sext_ln221_fu_102087_p1; + sext_ln231_reg_131751[2 : 0] <= sext_ln231_fu_102102_p1[2 : 0]; + trunc_ln221_reg_131734 <= trunc_ln221_fu_102048_p1; + zext_ln216_3_reg_131745[17 : 0] <= zext_ln216_3_fu_102091_p1[17 : 0]; + zext_ln231_reg_131757[2 : 0] <= zext_ln231_fu_102114_p1[2 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2765 == ap_CS_fsm)) begin + tmp_105_reg_149766 <= tmp_105_fu_118490_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4797 == ap_CS_fsm)) begin + tmp_107_reg_165726 <= tmp_107_fu_130067_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2647 == ap_CS_fsm)) begin + tmp_10_reg_148924 <= tmp_10_fu_117931_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3918 == ap_CS_fsm)) begin + tmp_110_reg_159096 <= tmp_110_fu_125139_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3303 == ap_CS_fsm)) begin + tmp_112_reg_154156 <= tmp_112_fu_121565_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2995 == ap_CS_fsm)) begin + tmp_113_reg_151310 <= tmp_113_fu_119722_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3996 == ap_CS_fsm)) begin + tmp_116_reg_159607 <= tmp_116_fu_125532_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3381 == ap_CS_fsm)) begin + tmp_117_reg_154667 <= tmp_117_fu_121958_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3073 == ap_CS_fsm)) begin + tmp_118_reg_151816 <= tmp_118_fu_120114_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2724 == ap_CS_fsm)) begin + tmp_119_reg_149429 <= tmp_119_fu_118307_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4532 == ap_CS_fsm)) begin + tmp_121_reg_163997 <= tmp_121_fu_128607_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4225 == ap_CS_fsm)) begin + tmp_122_reg_161151 <= tmp_122_fu_126764_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3610 == ap_CS_fsm)) begin + tmp_123_reg_156211 <= tmp_123_fu_123190_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2802 == ap_CS_fsm)) begin + tmp_124_reg_149949 <= tmp_124_fu_118729_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4609 == ap_CS_fsm)) begin + tmp_125_reg_164508 <= tmp_125_fu_129000_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4302 == ap_CS_fsm)) begin + tmp_126_reg_161657 <= tmp_126_fu_127156_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3955 == ap_CS_fsm)) begin + tmp_127_reg_159270 <= tmp_127_fu_125349_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3687 == ap_CS_fsm)) begin + tmp_128_reg_156717 <= tmp_128_fu_123582_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3340 == ap_CS_fsm)) begin + tmp_129_reg_154330 <= tmp_129_fu_121775_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3032 == ap_CS_fsm)) begin + tmp_130_reg_151484 <= tmp_130_fu_119932_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4837 == ap_CS_fsm)) begin + tmp_132_reg_166052 <= tmp_132_fu_130232_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4032 == ap_CS_fsm)) begin + tmp_133_reg_159790 <= tmp_133_fu_125771_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3417 == ap_CS_fsm)) begin + tmp_134_reg_154850 <= tmp_134_fu_122197_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3109 == ap_CS_fsm)) begin + tmp_135_reg_151999 <= tmp_135_fu_120353_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4914 == ap_CS_fsm)) begin + tmp_136_reg_166558 <= tmp_136_fu_130624_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4569 == ap_CS_fsm)) begin + tmp_137_reg_164171 <= tmp_137_fu_128817_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4262 == ap_CS_fsm)) begin + tmp_138_reg_161325 <= tmp_138_fu_126974_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3647 == ap_CS_fsm)) begin + tmp_140_reg_156385 <= tmp_140_fu_123400_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4645 == ap_CS_fsm)) begin + tmp_144_reg_164691 <= tmp_144_fu_129239_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4338 == ap_CS_fsm)) begin + tmp_145_reg_161840 <= tmp_145_fu_127395_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3723 == ap_CS_fsm)) begin + tmp_146_reg_156900 <= tmp_146_fu_123821_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2841 == ap_CS_fsm)) begin + tmp_147_reg_150280 <= tmp_147_fu_118895_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4874 == ap_CS_fsm)) begin + tmp_148_reg_166226 <= tmp_148_fu_130442_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4950 == ap_CS_fsm)) begin + tmp_154_reg_166741 <= tmp_154_fu_130863_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4071 == ap_CS_fsm)) begin + tmp_155_reg_160121 <= tmp_155_fu_125937_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3456 == ap_CS_fsm)) begin + tmp_156_reg_155181 <= tmp_156_fu_122363_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3148 == ap_CS_fsm)) begin + tmp_157_reg_152325 <= tmp_157_fu_120518_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2877 == ap_CS_fsm)) begin + tmp_159_reg_150454 <= tmp_159_fu_119105_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4684 == ap_CS_fsm)) begin + tmp_161_reg_165022 <= tmp_161_fu_129405_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4377 == ap_CS_fsm)) begin + tmp_162_reg_162166 <= tmp_162_fu_127560_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3762 == ap_CS_fsm)) begin + tmp_163_reg_157226 <= tmp_163_fu_123986_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4107 == ap_CS_fsm)) begin + tmp_164_reg_160295 <= tmp_164_fu_126147_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3492 == ap_CS_fsm)) begin + tmp_165_reg_155355 <= tmp_165_fu_122573_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3184 == ap_CS_fsm)) begin + tmp_166_reg_152499 <= tmp_166_fu_120728_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4989 == ap_CS_fsm)) begin + tmp_167_reg_167067 <= tmp_167_fu_131028_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4720 == ap_CS_fsm)) begin + tmp_168_reg_165196 <= tmp_168_fu_129615_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4413 == ap_CS_fsm)) begin + tmp_169_reg_162340 <= tmp_169_fu_127770_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3798 == ap_CS_fsm)) begin + tmp_170_reg_157400 <= tmp_170_fu_124196_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state5025 == ap_CS_fsm)) begin + tmp_171_reg_167241 <= tmp_171_fu_131238_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state49 == ap_CS_fsm)) begin + tmp_249_reg_132604 <= {{grp_fu_102927_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1260 == ap_CS_fsm)) begin + tmp_256_reg_139786 <= {{grp_fu_109792_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state654 == ap_CS_fsm)) begin + tmp_257_reg_136175 <= {{grp_fu_106344_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + tmp_258_reg_132180 <= {{grp_fu_102439_p2[64:37]}}; + trunc_ln2_reg_132148 <= {{mul_ln1118_fu_102453_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2577 == ap_CS_fsm)) begin + tmp_261_reg_148595 <= {{grp_fu_117634_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1864 == ap_CS_fsm)) begin + tmp_262_reg_143335 <= {{grp_fu_113187_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1225 == ap_CS_fsm)) begin + tmp_263_reg_139372 <= {{grp_fu_109299_p2[64:37]}}; + trunc_ln708_10_reg_139340 <= {{mul_ln1118_10_fu_109313_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state619 == ap_CS_fsm)) begin + tmp_264_reg_135751 <= {{grp_fu_105858_p2[64:37]}}; + trunc_ln708_11_reg_135719 <= {{mul_ln1118_11_fu_105872_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3808 == ap_CS_fsm)) begin + tmp_265_reg_158436 <= {{grp_fu_124676_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3193 == ap_CS_fsm)) begin + tmp_266_reg_153496 <= {{grp_fu_121102_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2885 == ap_CS_fsm)) begin + tmp_267_reg_150655 <= {{grp_fu_119260_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1829 == ap_CS_fsm)) begin + tmp_268_reg_142915 <= {{grp_fu_112701_p2[64:37]}}; + trunc_ln708_12_reg_142883 <= {{mul_ln1118_12_fu_112715_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2614 == ap_CS_fsm)) begin + tmp_269_reg_148779 <= {{grp_fu_117884_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4422 == ap_CS_fsm)) begin + tmp_274_reg_163337 <= {{grp_fu_128144_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4115 == ap_CS_fsm)) begin + tmp_275_reg_160496 <= {{grp_fu_126302_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3500 == ap_CS_fsm)) begin + tmp_276_reg_155556 <= {{grp_fu_122728_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state156 == ap_CS_fsm)) begin + tmp_279_reg_132672 <= {{grp_fu_103065_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3845 == ap_CS_fsm)) begin + tmp_280_reg_158620 <= {{grp_fu_124926_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3230 == ap_CS_fsm)) begin + tmp_281_reg_153680 <= {{grp_fu_121352_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2922 == ap_CS_fsm)) begin + tmp_282_reg_150839 <= {{grp_fu_119510_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4728 == ap_CS_fsm)) begin + tmp_293_reg_165397 <= {{grp_fu_129770_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1367 == ap_CS_fsm)) begin + tmp_296_reg_139854 <= {{grp_fu_109930_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state761 == ap_CS_fsm)) begin + tmp_299_reg_136243 <= {{grp_fu_106482_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state201 == ap_CS_fsm)) begin + tmp_302_reg_133442 <= {{grp_fu_103619_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state117 == ap_CS_fsm)) begin + tmp_303_reg_132654 <= {{grp_fu_103005_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4459 == ap_CS_fsm)) begin + tmp_304_reg_163521 <= {{grp_fu_128394_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4152 == ap_CS_fsm)) begin + tmp_305_reg_160680 <= {{grp_fu_126552_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3537 == ap_CS_fsm)) begin + tmp_306_reg_155740 <= {{grp_fu_122978_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2654 == ap_CS_fsm)) begin + tmp_307_reg_149110 <= {{grp_fu_118050_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state352 == ap_CS_fsm)) begin + tmp_316_reg_134344 <= {{grp_fu_104536_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2732 == ap_CS_fsm)) begin + tmp_317_reg_149621 <= {{grp_fu_118443_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1971 == ap_CS_fsm)) begin + tmp_320_reg_143403 <= {{grp_fu_113325_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + tmp_323_reg_140620 <= {{grp_fu_110480_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1328 == ap_CS_fsm)) begin + tmp_324_reg_139836 <= {{grp_fu_109870_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state806 == ap_CS_fsm)) begin + tmp_327_reg_137013 <= {{grp_fu_107034_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state722 == ap_CS_fsm)) begin + tmp_328_reg_136225 <= {{grp_fu_106422_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state165 == ap_CS_fsm)) begin + tmp_329_reg_133076 <= {{grp_fu_103321_p2[64:37]}}; + trunc_ln708_15_reg_133044 <= {{mul_ln1118_16_fu_103335_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4764 == ap_CS_fsm)) begin + tmp_330_reg_165581 <= {{grp_fu_130020_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3885 == ap_CS_fsm)) begin + tmp_331_reg_158951 <= {{grp_fu_125092_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3270 == ap_CS_fsm)) begin + tmp_332_reg_154011 <= {{grp_fu_121518_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2962 == ap_CS_fsm)) begin + tmp_333_reg_151165 <= {{grp_fu_119675_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1563 == ap_CS_fsm)) begin + tmp_336_reg_141511 <= {{grp_fu_111394_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state957 == ap_CS_fsm)) begin + tmp_337_reg_137915 <= {{grp_fu_107949_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state317 == ap_CS_fsm)) begin + tmp_338_reg_133948 <= {{grp_fu_104125_p2[64:37]}}; + trunc_ln708_16_reg_133916 <= {{mul_ln1118_17_fu_104139_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3963 == ap_CS_fsm)) begin + tmp_339_reg_159462 <= {{grp_fu_125485_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3348 == ap_CS_fsm)) begin + tmp_340_reg_154522 <= {{grp_fu_121911_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3040 == ap_CS_fsm)) begin + tmp_341_reg_151671 <= {{grp_fu_120067_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2691 == ap_CS_fsm)) begin + tmp_342_reg_149284 <= {{grp_fu_118260_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2016 == ap_CS_fsm)) begin + tmp_345_reg_144173 <= {{grp_fu_113877_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1932 == ap_CS_fsm)) begin + tmp_346_reg_143385 <= {{grp_fu_113265_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1376 == ap_CS_fsm)) begin + tmp_347_reg_140254 <= {{grp_fu_110182_p2[64:37]}}; + trunc_ln708_18_reg_140222 <= {{mul_ln1118_19_fu_110196_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state770 == ap_CS_fsm)) begin + tmp_348_reg_136647 <= {{grp_fu_106737_p2[64:37]}}; + trunc_ln708_19_reg_136615 <= {{mul_ln1118_20_fu_106751_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4499 == ap_CS_fsm)) begin + tmp_349_reg_163852 <= {{grp_fu_128560_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4192 == ap_CS_fsm)) begin + tmp_350_reg_161006 <= {{grp_fu_126717_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3577 == ap_CS_fsm)) begin + tmp_351_reg_156066 <= {{grp_fu_123143_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2769 == ap_CS_fsm)) begin + tmp_352_reg_149804 <= {{grp_fu_118682_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2167 == ap_CS_fsm)) begin + tmp_353_reg_145070 <= {{grp_fu_114783_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1528 == ap_CS_fsm)) begin + tmp_354_reg_141121 <= {{grp_fu_110977_p2[64:37]}}; + trunc_ln708_20_reg_141089 <= {{mul_ln1118_21_fu_110991_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state922 == ap_CS_fsm)) begin + tmp_355_reg_137519 <= {{grp_fu_107539_p2[64:37]}}; + trunc_ln708_21_reg_137487 <= {{mul_ln1118_22_fu_107553_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4576 == ap_CS_fsm)) begin + tmp_356_reg_164363 <= {{grp_fu_128953_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4269 == ap_CS_fsm)) begin + tmp_357_reg_161512 <= {{grp_fu_127109_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3922 == ap_CS_fsm)) begin + tmp_358_reg_159125 <= {{grp_fu_125302_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3654 == ap_CS_fsm)) begin + tmp_359_reg_156572 <= {{grp_fu_123535_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3307 == ap_CS_fsm)) begin + tmp_360_reg_154185 <= {{grp_fu_121728_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2999 == ap_CS_fsm)) begin + tmp_361_reg_151339 <= {{grp_fu_119885_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1980 == ap_CS_fsm)) begin + tmp_362_reg_143807 <= {{grp_fu_113580_p2[64:37]}}; + trunc_ln708_22_reg_143775 <= {{mul_ln1118_23_fu_113594_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4804 == ap_CS_fsm)) begin + tmp_363_reg_165907 <= {{grp_fu_130185_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3999 == ap_CS_fsm)) begin + tmp_364_reg_159645 <= {{grp_fu_125724_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3384 == ap_CS_fsm)) begin + tmp_365_reg_154705 <= {{grp_fu_122150_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3076 == ap_CS_fsm)) begin + tmp_366_reg_151854 <= {{grp_fu_120306_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2132 == ap_CS_fsm)) begin + tmp_367_reg_144674 <= {{grp_fu_114373_p2[64:37]}}; + trunc_ln708_23_reg_144642 <= {{mul_ln1118_24_fu_114387_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4881 == ap_CS_fsm)) begin + tmp_370_reg_166413 <= {{grp_fu_130577_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4536 == ap_CS_fsm)) begin + tmp_371_reg_164026 <= {{grp_fu_128770_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4229 == ap_CS_fsm)) begin + tmp_372_reg_161180 <= {{grp_fu_126927_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3614 == ap_CS_fsm)) begin + tmp_373_reg_156240 <= {{grp_fu_123353_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state308 == ap_CS_fsm)) begin + tmp_378_reg_133510 <= {{grp_fu_103757_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4612 == ap_CS_fsm)) begin + tmp_379_reg_164546 <= {{grp_fu_129192_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4305 == ap_CS_fsm)) begin + tmp_380_reg_161695 <= {{grp_fu_127348_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3690 == ap_CS_fsm)) begin + tmp_381_reg_156755 <= {{grp_fu_123774_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2808 == ap_CS_fsm)) begin + tmp_382_reg_150135 <= {{grp_fu_118848_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state459 == ap_CS_fsm)) begin + tmp_387_reg_134412 <= {{grp_fu_104674_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4841 == ap_CS_fsm)) begin + tmp_388_reg_166081 <= {{grp_fu_130395_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1519 == ap_CS_fsm)) begin + tmp_393_reg_140688 <= {{grp_fu_110618_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + tmp_398_reg_137081 <= {{grp_fu_107172_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state269 == ap_CS_fsm)) begin + tmp_401_reg_133492 <= {{grp_fu_103697_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4917 == ap_CS_fsm)) begin + tmp_402_reg_166596 <= {{grp_fu_130816_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4038 == ap_CS_fsm)) begin + tmp_403_reg_159976 <= {{grp_fu_125890_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3423 == ap_CS_fsm)) begin + tmp_404_reg_155036 <= {{grp_fu_122316_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3115 == ap_CS_fsm)) begin + tmp_405_reg_152180 <= {{grp_fu_120471_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1670 == ap_CS_fsm)) begin + tmp_408_reg_141579 <= {{grp_fu_111532_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1064 == ap_CS_fsm)) begin + tmp_409_reg_137983 <= {{grp_fu_108087_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state502 == ap_CS_fsm)) begin + tmp_410_reg_135184 <= {{grp_fu_105224_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state420 == ap_CS_fsm)) begin + tmp_411_reg_134394 <= {{grp_fu_104614_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2844 == ap_CS_fsm)) begin + tmp_412_reg_150309 <= {{grp_fu_119058_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2123 == ap_CS_fsm)) begin + tmp_417_reg_144241 <= {{grp_fu_114015_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1480 == ap_CS_fsm)) begin + tmp_420_reg_140670 <= {{grp_fu_110558_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + tmp_423_reg_137063 <= {{grp_fu_107112_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4651 == ap_CS_fsm)) begin + tmp_424_reg_164877 <= {{grp_fu_129358_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4344 == ap_CS_fsm)) begin + tmp_425_reg_162021 <= {{grp_fu_127513_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3729 == ap_CS_fsm)) begin + tmp_426_reg_157081 <= {{grp_fu_123939_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + tmp_427_reg_145138 <= {{grp_fu_114921_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1713 == ap_CS_fsm)) begin + tmp_428_reg_142347 <= {{grp_fu_112078_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1631 == ap_CS_fsm)) begin + tmp_429_reg_141561 <= {{grp_fu_111472_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1107 == ap_CS_fsm)) begin + tmp_430_reg_138755 <= {{grp_fu_108635_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1025 == ap_CS_fsm)) begin + tmp_431_reg_137965 <= {{grp_fu_108027_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state467 == ap_CS_fsm)) begin + tmp_432_reg_134823 <= {{grp_fu_104928_p2[64:37]}}; + trunc_ln708_30_reg_134791 <= {{mul_ln1118_31_fu_104942_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4074 == ap_CS_fsm)) begin + tmp_433_reg_160150 <= {{grp_fu_126100_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3459 == ap_CS_fsm)) begin + tmp_434_reg_155210 <= {{grp_fu_122526_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3151 == ap_CS_fsm)) begin + tmp_435_reg_152354 <= {{grp_fu_120681_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2084 == ap_CS_fsm)) begin + tmp_438_reg_144223 <= {{grp_fu_113955_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4956 == ap_CS_fsm)) begin + tmp_439_reg_166922 <= {{grp_fu_130981_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2317 == ap_CS_fsm)) begin + tmp_440_reg_145910 <= {{grp_fu_115469_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + tmp_441_reg_145120 <= {{grp_fu_114861_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1678 == ap_CS_fsm)) begin + tmp_442_reg_141986 <= {{grp_fu_111782_p2[64:37]}}; + trunc_ln708_33_reg_141954 <= {{mul_ln1118_34_fu_111796_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1072 == ap_CS_fsm)) begin + tmp_443_reg_138394 <= {{grp_fu_108340_p2[64:37]}}; + trunc_ln708_34_reg_138362 <= {{mul_ln1118_35_fu_108354_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4687 == ap_CS_fsm)) begin + tmp_444_reg_165051 <= {{grp_fu_129568_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4380 == ap_CS_fsm)) begin + tmp_445_reg_162195 <= {{grp_fu_127723_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3765 == ap_CS_fsm)) begin + tmp_446_reg_157255 <= {{grp_fu_124149_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2282 == ap_CS_fsm)) begin + tmp_447_reg_145549 <= {{grp_fu_115174_p2[64:37]}}; + trunc_ln708_35_reg_145517 <= {{mul_ln1118_36_fu_115188_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4992 == ap_CS_fsm)) begin + tmp_448_reg_167096 <= {{grp_fu_131191_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state607 == ap_CS_fsm)) begin + tmp_451_reg_135252 <= {{grp_fu_105362_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1818 == ap_CS_fsm)) begin + tmp_456_reg_142415 <= {{grp_fu_112216_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1212 == ap_CS_fsm)) begin + tmp_457_reg_138823 <= {{grp_fu_108773_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state570 == ap_CS_fsm)) begin + tmp_458_reg_135234 <= {{grp_fu_105302_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2422 == ap_CS_fsm)) begin + tmp_461_reg_145978 <= {{grp_fu_115607_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1781 == ap_CS_fsm)) begin + tmp_462_reg_142397 <= {{grp_fu_112156_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1175 == ap_CS_fsm)) begin + tmp_463_reg_138805 <= {{grp_fu_108713_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2385 == ap_CS_fsm)) begin + tmp_464_reg_145960 <= {{grp_fu_115547_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4455 == ap_CS_fsm)) begin + tmp_65_reg_163482 <= tmp_65_fu_128191_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4148 == ap_CS_fsm)) begin + tmp_66_reg_160641 <= tmp_66_fu_126349_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3533 == ap_CS_fsm)) begin + tmp_67_reg_155701 <= tmp_67_fu_122775_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2610 == ap_CS_fsm)) begin + tmp_6_reg_148740 <= tmp_6_fu_117681_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3878 == ap_CS_fsm)) begin + tmp_72_reg_158765 <= tmp_72_fu_124973_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3263 == ap_CS_fsm)) begin + tmp_73_reg_153825 <= tmp_73_fu_121399_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2955 == ap_CS_fsm)) begin + tmp_74_reg_150984 <= tmp_74_fu_119557_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3841 == ap_CS_fsm)) begin + tmp_7_reg_158581 <= tmp_7_fu_124723_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4761 == ap_CS_fsm)) begin + tmp_80_reg_165542 <= tmp_80_fu_129817_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3226 == ap_CS_fsm)) begin + tmp_8_reg_153641 <= tmp_8_fu_121149_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4492 == ap_CS_fsm)) begin + tmp_90_reg_163666 <= tmp_90_fu_128441_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4185 == ap_CS_fsm)) begin + tmp_91_reg_160825 <= tmp_91_fu_126599_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3570 == ap_CS_fsm)) begin + tmp_93_reg_155885 <= tmp_93_fu_123025_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2687 == ap_CS_fsm)) begin + tmp_96_reg_149255 <= tmp_96_fu_118097_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2918 == ap_CS_fsm)) begin + tmp_9_reg_150800 <= tmp_9_fu_119307_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state88 == ap_CS_fsm)) begin + trunc_ln708_13_reg_132617 <= {{mul_ln1118_13_fu_102986_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + trunc_ln708_14_reg_139799 <= {{mul_ln1118_14_fu_109851_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1903 == ap_CS_fsm)) begin + trunc_ln708_17_reg_143348 <= {{mul_ln1118_18_fu_113246_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state240 == ap_CS_fsm)) begin + trunc_ln708_24_reg_133455 <= {{mul_ln1118_25_fu_103678_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state391 == ap_CS_fsm)) begin + trunc_ln708_25_reg_134357 <= {{mul_ln1118_26_fu_104595_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1451 == ap_CS_fsm)) begin + trunc_ln708_26_reg_140633 <= {{mul_ln1118_27_fu_110539_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state845 == ap_CS_fsm)) begin + trunc_ln708_27_reg_137026 <= {{mul_ln1118_28_fu_107093_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1602 == ap_CS_fsm)) begin + trunc_ln708_28_reg_141524 <= {{mul_ln1118_29_fu_111453_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state996 == ap_CS_fsm)) begin + trunc_ln708_29_reg_137928 <= {{mul_ln1118_30_fu_108008_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2055 == ap_CS_fsm)) begin + trunc_ln708_31_reg_144186 <= {{mul_ln1118_32_fu_113936_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2206 == ap_CS_fsm)) begin + trunc_ln708_32_reg_145083 <= {{mul_ln1118_33_fu_114842_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state540 == ap_CS_fsm)) begin + trunc_ln708_36_reg_135197 <= {{mul_ln1118_37_fu_105283_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1751 == ap_CS_fsm)) begin + trunc_ln708_37_reg_142360 <= {{mul_ln1118_38_fu_112137_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1145 == ap_CS_fsm)) begin + trunc_ln708_38_reg_138768 <= {{mul_ln1118_39_fu_108694_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2355 == ap_CS_fsm)) begin + trunc_ln708_39_reg_145923 <= {{mul_ln1118_40_fu_115528_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state693 == ap_CS_fsm)) begin + trunc_ln708_s_reg_136188 <= {{mul_ln1118_15_fu_106403_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_2_fu_121309_p2 == 1'd1) & (icmp_ln268_2_fu_121286_p2 == 1'd1) & (ap_ST_fsm_state3228 == ap_CS_fsm))) begin + zext_ln276_10_reg_153669[17 : 0] <= zext_ln276_10_fu_121346_p1[17 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_3_fu_119467_p2 == 1'd1) & (icmp_ln268_3_fu_119444_p2 == 1'd1) & (ap_ST_fsm_state2920 == ap_CS_fsm))) begin + zext_ln276_11_reg_150828[17 : 0] <= zext_ln276_11_fu_119504_p1[17 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_4_fu_128351_p2 == 1'd1) & (icmp_ln268_4_fu_128328_p2 == 1'd1) & (ap_ST_fsm_state4457 == ap_CS_fsm))) begin + zext_ln276_12_reg_163510[18 : 0] <= zext_ln276_12_fu_128388_p1[18 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_5_fu_126509_p2 == 1'd1) & (icmp_ln268_5_fu_126486_p2 == 1'd1) & (ap_ST_fsm_state4150 == ap_CS_fsm))) begin + zext_ln276_13_reg_160669[18 : 0] <= zext_ln276_13_fu_126546_p1[18 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_6_fu_122935_p2 == 1'd1) & (icmp_ln268_6_fu_122912_p2 == 1'd1) & (ap_ST_fsm_state3535 == ap_CS_fsm))) begin + zext_ln276_14_reg_155729[17 : 0] <= zext_ln276_14_fu_122972_p1[17 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_7_fu_129977_p2 == 1'd1) & (icmp_ln268_7_fu_129954_p2 == 1'd1) & (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + zext_ln276_15_reg_165570[18 : 0] <= zext_ln276_15_fu_130014_p1[18 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3802 == ap_CS_fsm) & (icmp_ln264_1_fu_124526_p2 == 1'd0))) begin + zext_ln276_1_reg_157854[18 : 0] <= zext_ln276_1_fu_124532_p1[18 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3187 == ap_CS_fsm) & (icmp_ln264_2_fu_120952_p2 == 1'd0))) begin + zext_ln276_2_reg_152914[17 : 0] <= zext_ln276_2_fu_120958_p1[17 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2879 == ap_CS_fsm) & (icmp_ln264_3_fu_119214_p2 == 1'd0))) begin + zext_ln276_3_reg_150467[17 : 0] <= zext_ln276_3_fu_119220_p1[17 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4416 == ap_CS_fsm) & (icmp_ln264_4_fu_127994_p2 == 1'd0))) begin + zext_ln276_4_reg_162755[18 : 0] <= zext_ln276_4_fu_128000_p1[18 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4109 == ap_CS_fsm) & (icmp_ln264_5_fu_126256_p2 == 1'd0))) begin + zext_ln276_5_reg_160308[18 : 0] <= zext_ln276_5_fu_126262_p1[18 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3494 == ap_CS_fsm) & (icmp_ln264_6_fu_122682_p2 == 1'd0))) begin + zext_ln276_6_reg_155368[17 : 0] <= zext_ln276_6_fu_122688_p1[17 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4722 == ap_CS_fsm) & (icmp_ln264_7_fu_129724_p2 == 1'd0))) begin + zext_ln276_7_reg_165209[18 : 0] <= zext_ln276_7_fu_129730_p1[18 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_fu_117841_p2 == 1'd1) & (icmp_ln268_fu_117818_p2 == 1'd1) & (ap_ST_fsm_state2612 == ap_CS_fsm))) begin + zext_ln276_8_reg_148768[17 : 0] <= zext_ln276_8_fu_117878_p1[17 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_1_fu_124883_p2 == 1'd1) & (icmp_ln268_1_fu_124860_p2 == 1'd1) & (ap_ST_fsm_state3843 == ap_CS_fsm))) begin + zext_ln276_9_reg_158609[18 : 0] <= zext_ln276_9_fu_124920_p1[18 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2571 == ap_CS_fsm) & (icmp_ln264_fu_117484_p2 == 1'd0))) begin + zext_ln276_reg_148013[17 : 0] <= zext_ln276_fu_117490_p1[17 : 0]; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_0_V_address0 = acc_0_V_addr_49_reg_162765; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_0_V_address0 = acc_0_V_addr_44_reg_162357; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_0_V_address0 = acc_0_V_addr_45_reg_157864; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_0_V_address0 = acc_0_V_addr_39_reg_157443; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_0_V_address0 = acc_0_V_addr_46_reg_152924; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_0_V_address0 = acc_0_V_addr_40_reg_152516; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_0_V_address0 = acc_0_V_addr_41_reg_148023; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_0_V_address0 = acc_0_V_addr_37_reg_147633; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2566 == ap_CS_fsm)) begin + acc_0_V_address0 = acc_0_V_addr_52_reg_146768; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_0_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2531 == ap_CS_fsm)) begin + acc_0_V_address0 = acc_0_V_addr_50_reg_146546; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_0_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2495 == ap_CS_fsm)) begin + acc_0_V_address0 = acc_0_V_addr_51_reg_146297; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_0_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2460 == ap_CS_fsm)) begin + acc_0_V_address0 = acc_0_V_addr_48_reg_146075; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_0_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_0_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_0_V_address1 = acc_0_V_addr_49_reg_162765; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_0_V_address1 = acc_0_V_addr_44_reg_162357; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_0_V_address1 = acc_0_V_addr_45_reg_157864; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_0_V_address1 = acc_0_V_addr_39_reg_157443; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_0_V_address1 = acc_0_V_addr_46_reg_152924; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_0_V_address1 = acc_0_V_addr_40_reg_152516; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_0_V_address1 = acc_0_V_addr_41_reg_148023; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_0_V_address1 = acc_0_V_addr_37_reg_147633; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd1; + end else begin + acc_0_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2566 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2531 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2495 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2460 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_0_V_ce0 = 1'b1; + end else begin + acc_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_0_V_ce1 = 1'b1; + end else begin + acc_0_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2566 == ap_CS_fsm)) begin + acc_0_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_0_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2531 == ap_CS_fsm)) begin + acc_0_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_0_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2495 == ap_CS_fsm)) begin + acc_0_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_0_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2460 == ap_CS_fsm)) begin + acc_0_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_0_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_0_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_0_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2566 == ap_CS_fsm) & (6'd0 == add_ln203_11_reg_146764)) | ((ap_ST_fsm_state2531 == ap_CS_fsm) & (6'd0 == add_ln203_9_reg_146542)) | ((ap_ST_fsm_state2495 == ap_CS_fsm) & (6'd0 == add_ln203_10_reg_146293)) | ((ap_ST_fsm_state2460 == ap_CS_fsm) & (6'd0 == add_ln203_7_reg_146071)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd0 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd0 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd0 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd0 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd0 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd0 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd0 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd0 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd0 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd0 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd0 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd0 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd0 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd0 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd0 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd0 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd0 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd0 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd0 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd0 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd0 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd0 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd0 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd0 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd0 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd0 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_0_V_we0 = 1'b1; + end else begin + acc_0_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd0 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd0 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd0 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd0 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd0 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd0 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd0 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd0 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd0 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd0 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd0 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd0 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd0 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd0 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd0 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd0 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd0 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd0 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd0 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd0 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd0 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd0 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd0 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd0 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd0 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd0 == add_ln1265_reg_147629)))) begin + acc_0_V_we1 = 1'b1; + end else begin + acc_0_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_10_V_address0 = acc_10_V_addr_49_reg_162825; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_10_V_address0 = acc_10_V_addr_44_reg_162417; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_10_V_address0 = acc_10_V_addr_45_reg_157924; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_10_V_address0 = acc_10_V_addr_39_reg_157503; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_10_V_address0 = acc_10_V_addr_46_reg_152984; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_10_V_address0 = acc_10_V_addr_40_reg_152576; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_10_V_address0 = acc_10_V_addr_41_reg_148083; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_10_V_address0 = acc_10_V_addr_37_reg_147688; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2561 == ap_CS_fsm)) begin + acc_10_V_address0 = acc_10_V_addr_52_reg_146793; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_10_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2526 == ap_CS_fsm)) begin + acc_10_V_address0 = acc_10_V_addr_50_reg_146571; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_10_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2490 == ap_CS_fsm)) begin + acc_10_V_address0 = acc_10_V_addr_51_reg_146322; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_10_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2455 == ap_CS_fsm)) begin + acc_10_V_address0 = acc_10_V_addr_48_reg_146100; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_10_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_10_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_10_V_address1 = acc_10_V_addr_49_reg_162825; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_10_V_address1 = acc_10_V_addr_44_reg_162417; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_10_V_address1 = acc_10_V_addr_45_reg_157924; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_10_V_address1 = acc_10_V_addr_39_reg_157503; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_10_V_address1 = acc_10_V_addr_46_reg_152984; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_10_V_address1 = acc_10_V_addr_40_reg_152576; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_10_V_address1 = acc_10_V_addr_41_reg_148083; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_10_V_address1 = acc_10_V_addr_37_reg_147688; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd1; + end else begin + acc_10_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2561 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2526 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2490 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2455 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_10_V_ce0 = 1'b1; + end else begin + acc_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_10_V_ce1 = 1'b1; + end else begin + acc_10_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2561 == ap_CS_fsm)) begin + acc_10_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_10_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2526 == ap_CS_fsm)) begin + acc_10_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_10_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2490 == ap_CS_fsm)) begin + acc_10_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_10_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2455 == ap_CS_fsm)) begin + acc_10_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_10_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_10_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_10_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2561 == ap_CS_fsm) | (ap_ST_fsm_state2526 == ap_CS_fsm) | (ap_ST_fsm_state2490 == ap_CS_fsm) | (ap_ST_fsm_state2455 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd10 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd10 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd10 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd10 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd10 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd10 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd10 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd10 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd10 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd10 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd10 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd10 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd10 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd10 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd10 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd10 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd10 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd10 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd10 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd10 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd10 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd10 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd10 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd10 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd10 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd10 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_10_V_we0 = 1'b1; + end else begin + acc_10_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd10 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd10 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd10 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd10 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd10 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd10 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd10 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd10 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd10 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd10 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd10 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd10 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd10 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd10 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd10 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd10 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd10 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd10 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd10 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd10 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd10 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd10 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd10 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd10 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd10 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd10 == add_ln1265_reg_147629)))) begin + acc_10_V_we1 = 1'b1; + end else begin + acc_10_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_11_V_address0 = acc_11_V_addr_48_reg_162831; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_11_V_address0 = acc_11_V_addr_44_reg_162423; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_11_V_address0 = acc_11_V_addr_45_reg_157930; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_11_V_address0 = acc_11_V_addr_39_reg_157509; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_11_V_address0 = acc_11_V_addr_46_reg_152990; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_11_V_address0 = acc_11_V_addr_40_reg_152582; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_11_V_address0 = acc_11_V_addr_41_reg_148089; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_11_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_11_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_11_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_11_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_11_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_11_V_address1 = acc_11_V_addr_48_reg_162831; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_11_V_address1 = acc_11_V_addr_44_reg_162423; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_11_V_address1 = acc_11_V_addr_45_reg_157930; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_11_V_address1 = acc_11_V_addr_39_reg_157509; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_11_V_address1 = acc_11_V_addr_46_reg_152990; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_11_V_address1 = acc_11_V_addr_40_reg_152582; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_11_V_address1 = acc_11_V_addr_41_reg_148089; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_11_V_address1 = acc_11_V_addr_37_reg_147694; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd1; + end else begin + acc_11_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_11_V_ce0 = 1'b1; + end else begin + acc_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_11_V_ce1 = 1'b1; + end else begin + acc_11_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_11_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_11_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_11_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_11_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_11_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_11_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd11 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd11 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd11 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd11 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd11 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd11 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd11 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd11 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd11 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd11 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd11 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd11 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd11 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd11 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd11 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd11 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd11 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd11 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd11 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd11 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd11 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd11 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd11 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd11 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd11 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd11 == add_ln203_7_fu_116022_p2)))) begin + acc_11_V_we0 = 1'b1; + end else begin + acc_11_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd11 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd11 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd11 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd11 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd11 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd11 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd11 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd11 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd11 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd11 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd11 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd11 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd11 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd11 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd11 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd11 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd11 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd11 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd11 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd11 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd11 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd11 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd11 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd11 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd11 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd11 == add_ln1265_reg_147629)))) begin + acc_11_V_we1 = 1'b1; + end else begin + acc_11_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_12_V_address0 = acc_12_V_addr_49_reg_162837; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_12_V_address0 = acc_12_V_addr_44_reg_162429; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_12_V_address0 = acc_12_V_addr_45_reg_157936; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_12_V_address0 = acc_12_V_addr_39_reg_157515; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_12_V_address0 = acc_12_V_addr_46_reg_152996; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_12_V_address0 = acc_12_V_addr_40_reg_152588; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_12_V_address0 = acc_12_V_addr_41_reg_148095; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_12_V_address0 = acc_12_V_addr_37_reg_147699; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2560 == ap_CS_fsm)) begin + acc_12_V_address0 = acc_12_V_addr_52_reg_146798; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_12_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2525 == ap_CS_fsm)) begin + acc_12_V_address0 = acc_12_V_addr_50_reg_146576; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_12_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2489 == ap_CS_fsm)) begin + acc_12_V_address0 = acc_12_V_addr_51_reg_146327; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_12_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2454 == ap_CS_fsm)) begin + acc_12_V_address0 = acc_12_V_addr_48_reg_146105; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_12_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_12_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_12_V_address1 = acc_12_V_addr_49_reg_162837; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_12_V_address1 = acc_12_V_addr_44_reg_162429; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_12_V_address1 = acc_12_V_addr_45_reg_157936; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_12_V_address1 = acc_12_V_addr_39_reg_157515; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_12_V_address1 = acc_12_V_addr_46_reg_152996; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_12_V_address1 = acc_12_V_addr_40_reg_152588; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_12_V_address1 = acc_12_V_addr_41_reg_148095; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_12_V_address1 = acc_12_V_addr_37_reg_147699; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd1; + end else begin + acc_12_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2560 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2525 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2489 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2454 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_12_V_ce0 = 1'b1; + end else begin + acc_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_12_V_ce1 = 1'b1; + end else begin + acc_12_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2560 == ap_CS_fsm)) begin + acc_12_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_12_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2525 == ap_CS_fsm)) begin + acc_12_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_12_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2489 == ap_CS_fsm)) begin + acc_12_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_12_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2454 == ap_CS_fsm)) begin + acc_12_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_12_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_12_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_12_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2560 == ap_CS_fsm) | (ap_ST_fsm_state2525 == ap_CS_fsm) | (ap_ST_fsm_state2489 == ap_CS_fsm) | (ap_ST_fsm_state2454 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd12 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd12 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd12 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd12 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd12 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd12 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd12 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd12 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd12 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd12 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd12 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd12 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd12 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd12 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd12 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd12 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd12 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd12 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd12 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd12 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd12 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd12 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd12 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd12 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd12 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd12 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_12_V_we0 = 1'b1; + end else begin + acc_12_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd12 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd12 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd12 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd12 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd12 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd12 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd12 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd12 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd12 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd12 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd12 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd12 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd12 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd12 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd12 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd12 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd12 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd12 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd12 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd12 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd12 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd12 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd12 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd12 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd12 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd12 == add_ln1265_reg_147629)))) begin + acc_12_V_we1 = 1'b1; + end else begin + acc_12_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_13_V_address0 = acc_13_V_addr_48_reg_162843; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_13_V_address0 = acc_13_V_addr_44_reg_162435; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_13_V_address0 = acc_13_V_addr_45_reg_157942; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_13_V_address0 = acc_13_V_addr_39_reg_157521; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_13_V_address0 = acc_13_V_addr_46_reg_153002; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_13_V_address0 = acc_13_V_addr_40_reg_152594; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_13_V_address0 = acc_13_V_addr_41_reg_148101; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_13_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_13_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_13_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_13_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_13_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_13_V_address1 = acc_13_V_addr_48_reg_162843; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_13_V_address1 = acc_13_V_addr_44_reg_162435; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_13_V_address1 = acc_13_V_addr_45_reg_157942; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_13_V_address1 = acc_13_V_addr_39_reg_157521; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_13_V_address1 = acc_13_V_addr_46_reg_153002; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_13_V_address1 = acc_13_V_addr_40_reg_152594; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_13_V_address1 = acc_13_V_addr_41_reg_148101; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_13_V_address1 = acc_13_V_addr_37_reg_147705; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd1; + end else begin + acc_13_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_13_V_ce0 = 1'b1; + end else begin + acc_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_13_V_ce1 = 1'b1; + end else begin + acc_13_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_13_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_13_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_13_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_13_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_13_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_13_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd13 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd13 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd13 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd13 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd13 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd13 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd13 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd13 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd13 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd13 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd13 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd13 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd13 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd13 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd13 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd13 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd13 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd13 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd13 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd13 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd13 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd13 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd13 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd13 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd13 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd13 == add_ln203_7_fu_116022_p2)))) begin + acc_13_V_we0 = 1'b1; + end else begin + acc_13_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd13 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd13 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd13 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd13 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd13 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd13 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd13 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd13 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd13 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd13 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd13 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd13 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd13 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd13 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd13 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd13 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd13 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd13 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd13 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd13 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd13 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd13 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd13 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd13 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd13 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd13 == add_ln1265_reg_147629)))) begin + acc_13_V_we1 = 1'b1; + end else begin + acc_13_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_14_V_address0 = acc_14_V_addr_49_reg_162849; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_14_V_address0 = acc_14_V_addr_44_reg_162441; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_14_V_address0 = acc_14_V_addr_45_reg_157948; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_14_V_address0 = acc_14_V_addr_39_reg_157527; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_14_V_address0 = acc_14_V_addr_46_reg_153008; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_14_V_address0 = acc_14_V_addr_40_reg_152600; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_14_V_address0 = acc_14_V_addr_41_reg_148107; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_14_V_address0 = acc_14_V_addr_37_reg_147710; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2559 == ap_CS_fsm)) begin + acc_14_V_address0 = acc_14_V_addr_52_reg_146803; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_14_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2524 == ap_CS_fsm)) begin + acc_14_V_address0 = acc_14_V_addr_50_reg_146581; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_14_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2488 == ap_CS_fsm)) begin + acc_14_V_address0 = acc_14_V_addr_51_reg_146332; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_14_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2453 == ap_CS_fsm)) begin + acc_14_V_address0 = acc_14_V_addr_48_reg_146110; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_14_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_14_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_14_V_address1 = acc_14_V_addr_49_reg_162849; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_14_V_address1 = acc_14_V_addr_44_reg_162441; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_14_V_address1 = acc_14_V_addr_45_reg_157948; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_14_V_address1 = acc_14_V_addr_39_reg_157527; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_14_V_address1 = acc_14_V_addr_46_reg_153008; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_14_V_address1 = acc_14_V_addr_40_reg_152600; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_14_V_address1 = acc_14_V_addr_41_reg_148107; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_14_V_address1 = acc_14_V_addr_37_reg_147710; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd1; + end else begin + acc_14_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2559 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2524 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2488 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2453 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_14_V_ce0 = 1'b1; + end else begin + acc_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_14_V_ce1 = 1'b1; + end else begin + acc_14_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2559 == ap_CS_fsm)) begin + acc_14_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_14_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2524 == ap_CS_fsm)) begin + acc_14_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_14_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2488 == ap_CS_fsm)) begin + acc_14_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_14_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2453 == ap_CS_fsm)) begin + acc_14_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_14_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_14_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_14_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2559 == ap_CS_fsm) | (ap_ST_fsm_state2524 == ap_CS_fsm) | (ap_ST_fsm_state2488 == ap_CS_fsm) | (ap_ST_fsm_state2453 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd14 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd14 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd14 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd14 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd14 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd14 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd14 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd14 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd14 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd14 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd14 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd14 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd14 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd14 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd14 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd14 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd14 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd14 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd14 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd14 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd14 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd14 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd14 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd14 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd14 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd14 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_14_V_we0 = 1'b1; + end else begin + acc_14_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd14 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd14 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd14 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd14 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd14 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd14 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd14 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd14 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd14 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd14 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd14 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd14 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd14 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd14 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd14 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd14 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd14 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd14 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd14 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd14 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd14 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd14 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd14 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd14 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd14 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd14 == add_ln1265_reg_147629)))) begin + acc_14_V_we1 = 1'b1; + end else begin + acc_14_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_15_V_address0 = acc_15_V_addr_48_reg_162855; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_15_V_address0 = acc_15_V_addr_44_reg_162447; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_15_V_address0 = acc_15_V_addr_45_reg_157954; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_15_V_address0 = acc_15_V_addr_39_reg_157533; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_15_V_address0 = acc_15_V_addr_46_reg_153014; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_15_V_address0 = acc_15_V_addr_40_reg_152606; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_15_V_address0 = acc_15_V_addr_41_reg_148113; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_15_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_15_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_15_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_15_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_15_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_15_V_address1 = acc_15_V_addr_48_reg_162855; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_15_V_address1 = acc_15_V_addr_44_reg_162447; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_15_V_address1 = acc_15_V_addr_45_reg_157954; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_15_V_address1 = acc_15_V_addr_39_reg_157533; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_15_V_address1 = acc_15_V_addr_46_reg_153014; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_15_V_address1 = acc_15_V_addr_40_reg_152606; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_15_V_address1 = acc_15_V_addr_41_reg_148113; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_15_V_address1 = acc_15_V_addr_37_reg_147716; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd1; + end else begin + acc_15_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_15_V_ce0 = 1'b1; + end else begin + acc_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_15_V_ce1 = 1'b1; + end else begin + acc_15_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_15_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_15_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_15_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_15_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_15_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_15_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd15 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd15 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd15 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd15 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd15 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd15 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd15 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd15 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd15 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd15 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd15 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd15 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd15 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd15 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd15 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd15 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd15 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd15 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd15 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd15 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd15 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd15 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd15 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd15 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd15 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd15 == add_ln203_7_fu_116022_p2)))) begin + acc_15_V_we0 = 1'b1; + end else begin + acc_15_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd15 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd15 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd15 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd15 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd15 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd15 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd15 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd15 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd15 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd15 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd15 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd15 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd15 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd15 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd15 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd15 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd15 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd15 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd15 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd15 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd15 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd15 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd15 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd15 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd15 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd15 == add_ln1265_reg_147629)))) begin + acc_15_V_we1 = 1'b1; + end else begin + acc_15_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_16_V_address0 = acc_16_V_addr_49_reg_162861; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_16_V_address0 = acc_16_V_addr_44_reg_162453; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_16_V_address0 = acc_16_V_addr_45_reg_157960; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_16_V_address0 = acc_16_V_addr_39_reg_157539; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_16_V_address0 = acc_16_V_addr_46_reg_153020; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_16_V_address0 = acc_16_V_addr_40_reg_152612; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_16_V_address0 = acc_16_V_addr_41_reg_148119; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_16_V_address0 = acc_16_V_addr_37_reg_147721; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2558 == ap_CS_fsm)) begin + acc_16_V_address0 = acc_16_V_addr_52_reg_146808; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_16_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2523 == ap_CS_fsm)) begin + acc_16_V_address0 = acc_16_V_addr_50_reg_146586; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_16_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2487 == ap_CS_fsm)) begin + acc_16_V_address0 = acc_16_V_addr_51_reg_146337; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_16_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2452 == ap_CS_fsm)) begin + acc_16_V_address0 = acc_16_V_addr_48_reg_146115; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_16_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_16_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_16_V_address1 = acc_16_V_addr_49_reg_162861; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_16_V_address1 = acc_16_V_addr_44_reg_162453; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_16_V_address1 = acc_16_V_addr_45_reg_157960; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_16_V_address1 = acc_16_V_addr_39_reg_157539; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_16_V_address1 = acc_16_V_addr_46_reg_153020; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_16_V_address1 = acc_16_V_addr_40_reg_152612; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_16_V_address1 = acc_16_V_addr_41_reg_148119; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_16_V_address1 = acc_16_V_addr_37_reg_147721; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd1; + end else begin + acc_16_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2558 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2523 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2487 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2452 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_16_V_ce0 = 1'b1; + end else begin + acc_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_16_V_ce1 = 1'b1; + end else begin + acc_16_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2558 == ap_CS_fsm)) begin + acc_16_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_16_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2523 == ap_CS_fsm)) begin + acc_16_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_16_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2487 == ap_CS_fsm)) begin + acc_16_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_16_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2452 == ap_CS_fsm)) begin + acc_16_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_16_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_16_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_16_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2558 == ap_CS_fsm) | (ap_ST_fsm_state2523 == ap_CS_fsm) | (ap_ST_fsm_state2487 == ap_CS_fsm) | (ap_ST_fsm_state2452 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd16 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd16 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd16 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd16 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd16 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd16 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd16 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd16 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd16 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd16 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd16 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd16 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd16 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd16 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd16 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd16 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd16 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd16 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd16 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd16 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd16 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd16 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd16 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd16 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd16 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd16 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_16_V_we0 = 1'b1; + end else begin + acc_16_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd16 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd16 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd16 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd16 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd16 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd16 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd16 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd16 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd16 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd16 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd16 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd16 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd16 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd16 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd16 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd16 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd16 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd16 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd16 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd16 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd16 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd16 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd16 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd16 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd16 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd16 == add_ln1265_reg_147629)))) begin + acc_16_V_we1 = 1'b1; + end else begin + acc_16_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_17_V_address0 = acc_17_V_addr_48_reg_162867; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_17_V_address0 = acc_17_V_addr_44_reg_162459; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_17_V_address0 = acc_17_V_addr_45_reg_157966; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_17_V_address0 = acc_17_V_addr_39_reg_157545; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_17_V_address0 = acc_17_V_addr_46_reg_153026; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_17_V_address0 = acc_17_V_addr_40_reg_152618; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_17_V_address0 = acc_17_V_addr_41_reg_148125; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_17_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_17_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_17_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_17_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_17_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_17_V_address1 = acc_17_V_addr_48_reg_162867; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_17_V_address1 = acc_17_V_addr_44_reg_162459; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_17_V_address1 = acc_17_V_addr_45_reg_157966; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_17_V_address1 = acc_17_V_addr_39_reg_157545; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_17_V_address1 = acc_17_V_addr_46_reg_153026; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_17_V_address1 = acc_17_V_addr_40_reg_152618; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_17_V_address1 = acc_17_V_addr_41_reg_148125; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_17_V_address1 = acc_17_V_addr_37_reg_147727; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd1; + end else begin + acc_17_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_17_V_ce0 = 1'b1; + end else begin + acc_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_17_V_ce1 = 1'b1; + end else begin + acc_17_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_17_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_17_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_17_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_17_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_17_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_17_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd17 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd17 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd17 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd17 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd17 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd17 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd17 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd17 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd17 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd17 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd17 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd17 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd17 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd17 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd17 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd17 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd17 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd17 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd17 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd17 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd17 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd17 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd17 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd17 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd17 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd17 == add_ln203_7_fu_116022_p2)))) begin + acc_17_V_we0 = 1'b1; + end else begin + acc_17_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd17 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd17 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd17 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd17 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd17 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd17 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd17 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd17 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd17 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd17 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd17 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd17 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd17 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd17 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd17 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd17 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd17 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd17 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd17 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd17 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd17 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd17 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd17 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd17 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd17 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd17 == add_ln1265_reg_147629)))) begin + acc_17_V_we1 = 1'b1; + end else begin + acc_17_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_18_V_address0 = acc_18_V_addr_49_reg_162873; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_18_V_address0 = acc_18_V_addr_44_reg_162465; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_18_V_address0 = acc_18_V_addr_45_reg_157972; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_18_V_address0 = acc_18_V_addr_39_reg_157551; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_18_V_address0 = acc_18_V_addr_46_reg_153032; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_18_V_address0 = acc_18_V_addr_40_reg_152624; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_18_V_address0 = acc_18_V_addr_41_reg_148131; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_18_V_address0 = acc_18_V_addr_37_reg_147732; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2557 == ap_CS_fsm)) begin + acc_18_V_address0 = acc_18_V_addr_52_reg_146813; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_18_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2522 == ap_CS_fsm)) begin + acc_18_V_address0 = acc_18_V_addr_50_reg_146591; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_18_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2486 == ap_CS_fsm)) begin + acc_18_V_address0 = acc_18_V_addr_51_reg_146342; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_18_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2451 == ap_CS_fsm)) begin + acc_18_V_address0 = acc_18_V_addr_48_reg_146120; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_18_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_18_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_18_V_address1 = acc_18_V_addr_49_reg_162873; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_18_V_address1 = acc_18_V_addr_44_reg_162465; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_18_V_address1 = acc_18_V_addr_45_reg_157972; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_18_V_address1 = acc_18_V_addr_39_reg_157551; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_18_V_address1 = acc_18_V_addr_46_reg_153032; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_18_V_address1 = acc_18_V_addr_40_reg_152624; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_18_V_address1 = acc_18_V_addr_41_reg_148131; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_18_V_address1 = acc_18_V_addr_37_reg_147732; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd1; + end else begin + acc_18_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2557 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2522 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2486 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2451 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_18_V_ce0 = 1'b1; + end else begin + acc_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_18_V_ce1 = 1'b1; + end else begin + acc_18_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2557 == ap_CS_fsm)) begin + acc_18_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_18_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2522 == ap_CS_fsm)) begin + acc_18_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_18_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2486 == ap_CS_fsm)) begin + acc_18_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_18_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2451 == ap_CS_fsm)) begin + acc_18_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_18_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_18_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_18_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2557 == ap_CS_fsm) | (ap_ST_fsm_state2522 == ap_CS_fsm) | (ap_ST_fsm_state2486 == ap_CS_fsm) | (ap_ST_fsm_state2451 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd18 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd18 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd18 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd18 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd18 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd18 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd18 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd18 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd18 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd18 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd18 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd18 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd18 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd18 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd18 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd18 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd18 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd18 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd18 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd18 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd18 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd18 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd18 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd18 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd18 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd18 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_18_V_we0 = 1'b1; + end else begin + acc_18_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd18 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd18 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd18 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd18 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd18 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd18 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd18 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd18 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd18 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd18 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd18 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd18 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd18 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd18 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd18 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd18 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd18 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd18 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd18 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd18 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd18 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd18 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd18 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd18 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd18 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd18 == add_ln1265_reg_147629)))) begin + acc_18_V_we1 = 1'b1; + end else begin + acc_18_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_19_V_address0 = acc_19_V_addr_48_reg_162879; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_19_V_address0 = acc_19_V_addr_44_reg_162471; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_19_V_address0 = acc_19_V_addr_45_reg_157978; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_19_V_address0 = acc_19_V_addr_39_reg_157557; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_19_V_address0 = acc_19_V_addr_46_reg_153038; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_19_V_address0 = acc_19_V_addr_40_reg_152630; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_19_V_address0 = acc_19_V_addr_41_reg_148137; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_19_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_19_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_19_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_19_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_19_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_19_V_address1 = acc_19_V_addr_48_reg_162879; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_19_V_address1 = acc_19_V_addr_44_reg_162471; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_19_V_address1 = acc_19_V_addr_45_reg_157978; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_19_V_address1 = acc_19_V_addr_39_reg_157557; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_19_V_address1 = acc_19_V_addr_46_reg_153038; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_19_V_address1 = acc_19_V_addr_40_reg_152630; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_19_V_address1 = acc_19_V_addr_41_reg_148137; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_19_V_address1 = acc_19_V_addr_37_reg_147738; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd1; + end else begin + acc_19_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_19_V_ce0 = 1'b1; + end else begin + acc_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_19_V_ce1 = 1'b1; + end else begin + acc_19_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_19_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_19_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_19_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_19_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_19_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_19_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd19 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd19 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd19 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd19 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd19 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd19 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd19 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd19 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd19 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd19 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd19 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd19 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd19 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd19 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd19 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd19 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd19 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd19 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd19 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd19 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd19 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd19 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd19 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd19 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd19 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd19 == add_ln203_7_fu_116022_p2)))) begin + acc_19_V_we0 = 1'b1; + end else begin + acc_19_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd19 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd19 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd19 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd19 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd19 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd19 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd19 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd19 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd19 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd19 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd19 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd19 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd19 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd19 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd19 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd19 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd19 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd19 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd19 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd19 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd19 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd19 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd19 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd19 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd19 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd19 == add_ln1265_reg_147629)))) begin + acc_19_V_we1 = 1'b1; + end else begin + acc_19_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_1_V_address0 = acc_1_V_addr_48_reg_162771; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_1_V_address0 = acc_1_V_addr_44_reg_162363; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_1_V_address0 = acc_1_V_addr_45_reg_157870; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_1_V_address0 = acc_1_V_addr_39_reg_157449; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_1_V_address0 = acc_1_V_addr_46_reg_152930; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_1_V_address0 = acc_1_V_addr_40_reg_152522; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_1_V_address0 = acc_1_V_addr_41_reg_148029; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_1_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_1_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_1_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_1_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_1_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_1_V_address1 = acc_1_V_addr_48_reg_162771; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_1_V_address1 = acc_1_V_addr_44_reg_162363; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_1_V_address1 = acc_1_V_addr_45_reg_157870; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_1_V_address1 = acc_1_V_addr_39_reg_157449; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_1_V_address1 = acc_1_V_addr_46_reg_152930; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_1_V_address1 = acc_1_V_addr_40_reg_152522; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_1_V_address1 = acc_1_V_addr_41_reg_148029; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_1_V_address1 = acc_1_V_addr_37_reg_147639; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd1; + end else begin + acc_1_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_1_V_ce0 = 1'b1; + end else begin + acc_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_1_V_ce1 = 1'b1; + end else begin + acc_1_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_1_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_1_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_1_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_1_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_1_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_1_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd1 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd1 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd1 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd1 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd1 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd1 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd1 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd1 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd1 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd1 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd1 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd1 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd1 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd1 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd1 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd1 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd1 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd1 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd1 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd1 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd1 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd1 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd1 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd1 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd1 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd1 == add_ln203_7_fu_116022_p2)))) begin + acc_1_V_we0 = 1'b1; + end else begin + acc_1_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd1 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd1 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd1 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd1 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd1 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd1 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd1 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd1 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd1 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd1 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd1 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd1 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd1 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd1 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd1 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd1 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd1 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd1 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd1 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd1 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd1 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd1 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd1 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd1 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd1 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd1 == add_ln1265_reg_147629)))) begin + acc_1_V_we1 = 1'b1; + end else begin + acc_1_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_20_V_address0 = acc_20_V_addr_49_reg_162885; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_20_V_address0 = acc_20_V_addr_44_reg_162477; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_20_V_address0 = acc_20_V_addr_45_reg_157984; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_20_V_address0 = acc_20_V_addr_39_reg_157563; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_20_V_address0 = acc_20_V_addr_46_reg_153044; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_20_V_address0 = acc_20_V_addr_40_reg_152636; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_20_V_address0 = acc_20_V_addr_41_reg_148143; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_20_V_address0 = acc_20_V_addr_37_reg_147743; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2556 == ap_CS_fsm)) begin + acc_20_V_address0 = acc_20_V_addr_52_reg_146818; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_20_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2521 == ap_CS_fsm)) begin + acc_20_V_address0 = acc_20_V_addr_50_reg_146596; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_20_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2485 == ap_CS_fsm)) begin + acc_20_V_address0 = acc_20_V_addr_51_reg_146347; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_20_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2450 == ap_CS_fsm)) begin + acc_20_V_address0 = acc_20_V_addr_48_reg_146125; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_20_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_20_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_20_V_address1 = acc_20_V_addr_49_reg_162885; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_20_V_address1 = acc_20_V_addr_44_reg_162477; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_20_V_address1 = acc_20_V_addr_45_reg_157984; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_20_V_address1 = acc_20_V_addr_39_reg_157563; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_20_V_address1 = acc_20_V_addr_46_reg_153044; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_20_V_address1 = acc_20_V_addr_40_reg_152636; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_20_V_address1 = acc_20_V_addr_41_reg_148143; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_20_V_address1 = acc_20_V_addr_37_reg_147743; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd1; + end else begin + acc_20_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2556 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2521 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2485 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2450 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_20_V_ce0 = 1'b1; + end else begin + acc_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_20_V_ce1 = 1'b1; + end else begin + acc_20_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2556 == ap_CS_fsm)) begin + acc_20_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_20_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2521 == ap_CS_fsm)) begin + acc_20_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_20_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2485 == ap_CS_fsm)) begin + acc_20_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_20_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2450 == ap_CS_fsm)) begin + acc_20_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_20_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_20_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_20_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2556 == ap_CS_fsm) | (ap_ST_fsm_state2521 == ap_CS_fsm) | (ap_ST_fsm_state2485 == ap_CS_fsm) | (ap_ST_fsm_state2450 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd20 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd20 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd20 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd20 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd20 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd20 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd20 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd20 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd20 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd20 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd20 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd20 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd20 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd20 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd20 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd20 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd20 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd20 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd20 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd20 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd20 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd20 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd20 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd20 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd20 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd20 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_20_V_we0 = 1'b1; + end else begin + acc_20_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd20 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd20 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd20 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd20 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd20 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd20 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd20 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd20 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd20 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd20 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd20 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd20 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd20 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd20 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd20 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd20 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd20 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd20 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd20 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd20 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd20 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd20 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd20 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd20 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd20 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd20 == add_ln1265_reg_147629)))) begin + acc_20_V_we1 = 1'b1; + end else begin + acc_20_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_21_V_address0 = acc_21_V_addr_48_reg_162891; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_21_V_address0 = acc_21_V_addr_44_reg_162483; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_21_V_address0 = acc_21_V_addr_45_reg_157990; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_21_V_address0 = acc_21_V_addr_39_reg_157569; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_21_V_address0 = acc_21_V_addr_46_reg_153050; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_21_V_address0 = acc_21_V_addr_40_reg_152642; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_21_V_address0 = acc_21_V_addr_41_reg_148149; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_21_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_21_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_21_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_21_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_21_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_21_V_address1 = acc_21_V_addr_48_reg_162891; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_21_V_address1 = acc_21_V_addr_44_reg_162483; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_21_V_address1 = acc_21_V_addr_45_reg_157990; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_21_V_address1 = acc_21_V_addr_39_reg_157569; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_21_V_address1 = acc_21_V_addr_46_reg_153050; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_21_V_address1 = acc_21_V_addr_40_reg_152642; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_21_V_address1 = acc_21_V_addr_41_reg_148149; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_21_V_address1 = acc_21_V_addr_37_reg_147749; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd1; + end else begin + acc_21_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_21_V_ce0 = 1'b1; + end else begin + acc_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_21_V_ce1 = 1'b1; + end else begin + acc_21_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_21_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_21_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_21_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_21_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_21_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_21_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd21 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd21 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd21 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd21 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd21 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd21 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd21 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd21 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd21 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd21 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd21 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd21 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd21 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd21 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd21 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd21 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd21 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd21 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd21 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd21 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd21 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd21 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd21 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd21 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd21 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd21 == add_ln203_7_fu_116022_p2)))) begin + acc_21_V_we0 = 1'b1; + end else begin + acc_21_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd21 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd21 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd21 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd21 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd21 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd21 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd21 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd21 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd21 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd21 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd21 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd21 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd21 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd21 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd21 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd21 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd21 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd21 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd21 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd21 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd21 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd21 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd21 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd21 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd21 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd21 == add_ln1265_reg_147629)))) begin + acc_21_V_we1 = 1'b1; + end else begin + acc_21_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_22_V_address0 = acc_22_V_addr_49_reg_162897; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_22_V_address0 = acc_22_V_addr_44_reg_162489; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_22_V_address0 = acc_22_V_addr_45_reg_157996; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_22_V_address0 = acc_22_V_addr_39_reg_157575; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_22_V_address0 = acc_22_V_addr_46_reg_153056; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_22_V_address0 = acc_22_V_addr_40_reg_152648; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_22_V_address0 = acc_22_V_addr_41_reg_148155; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_22_V_address0 = acc_22_V_addr_37_reg_147754; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2555 == ap_CS_fsm)) begin + acc_22_V_address0 = acc_22_V_addr_52_reg_146823; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_22_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2520 == ap_CS_fsm)) begin + acc_22_V_address0 = acc_22_V_addr_50_reg_146601; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_22_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2484 == ap_CS_fsm)) begin + acc_22_V_address0 = acc_22_V_addr_51_reg_146352; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_22_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2449 == ap_CS_fsm)) begin + acc_22_V_address0 = acc_22_V_addr_48_reg_146130; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_22_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_22_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_22_V_address1 = acc_22_V_addr_49_reg_162897; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_22_V_address1 = acc_22_V_addr_44_reg_162489; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_22_V_address1 = acc_22_V_addr_45_reg_157996; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_22_V_address1 = acc_22_V_addr_39_reg_157575; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_22_V_address1 = acc_22_V_addr_46_reg_153056; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_22_V_address1 = acc_22_V_addr_40_reg_152648; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_22_V_address1 = acc_22_V_addr_41_reg_148155; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_22_V_address1 = acc_22_V_addr_37_reg_147754; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd1; + end else begin + acc_22_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2555 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2520 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2484 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2449 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_22_V_ce0 = 1'b1; + end else begin + acc_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_22_V_ce1 = 1'b1; + end else begin + acc_22_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2555 == ap_CS_fsm)) begin + acc_22_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_22_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2520 == ap_CS_fsm)) begin + acc_22_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_22_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2484 == ap_CS_fsm)) begin + acc_22_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_22_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2449 == ap_CS_fsm)) begin + acc_22_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_22_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_22_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_22_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2555 == ap_CS_fsm) | (ap_ST_fsm_state2520 == ap_CS_fsm) | (ap_ST_fsm_state2484 == ap_CS_fsm) | (ap_ST_fsm_state2449 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd22 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd22 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd22 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd22 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd22 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd22 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd22 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd22 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd22 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd22 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd22 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd22 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd22 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd22 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd22 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd22 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd22 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd22 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd22 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd22 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd22 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd22 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd22 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd22 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd22 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd22 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_22_V_we0 = 1'b1; + end else begin + acc_22_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd22 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd22 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd22 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd22 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd22 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd22 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd22 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd22 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd22 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd22 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd22 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd22 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd22 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd22 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd22 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd22 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd22 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd22 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd22 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd22 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd22 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd22 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd22 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd22 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd22 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd22 == add_ln1265_reg_147629)))) begin + acc_22_V_we1 = 1'b1; + end else begin + acc_22_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_23_V_address0 = acc_23_V_addr_48_reg_162903; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_23_V_address0 = acc_23_V_addr_44_reg_162495; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_23_V_address0 = acc_23_V_addr_45_reg_158002; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_23_V_address0 = acc_23_V_addr_39_reg_157581; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_23_V_address0 = acc_23_V_addr_46_reg_153062; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_23_V_address0 = acc_23_V_addr_40_reg_152654; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_23_V_address0 = acc_23_V_addr_41_reg_148161; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_23_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_23_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_23_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_23_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_23_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_23_V_address1 = acc_23_V_addr_48_reg_162903; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_23_V_address1 = acc_23_V_addr_44_reg_162495; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_23_V_address1 = acc_23_V_addr_45_reg_158002; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_23_V_address1 = acc_23_V_addr_39_reg_157581; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_23_V_address1 = acc_23_V_addr_46_reg_153062; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_23_V_address1 = acc_23_V_addr_40_reg_152654; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_23_V_address1 = acc_23_V_addr_41_reg_148161; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_23_V_address1 = acc_23_V_addr_37_reg_147760; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd1; + end else begin + acc_23_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_23_V_ce0 = 1'b1; + end else begin + acc_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_23_V_ce1 = 1'b1; + end else begin + acc_23_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_23_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_23_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_23_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_23_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_23_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_23_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd23 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd23 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd23 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd23 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd23 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd23 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd23 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd23 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd23 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd23 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd23 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd23 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd23 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd23 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd23 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd23 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd23 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd23 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd23 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd23 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd23 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd23 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd23 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd23 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd23 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd23 == add_ln203_7_fu_116022_p2)))) begin + acc_23_V_we0 = 1'b1; + end else begin + acc_23_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd23 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd23 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd23 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd23 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd23 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd23 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd23 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd23 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd23 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd23 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd23 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd23 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd23 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd23 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd23 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd23 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd23 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd23 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd23 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd23 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd23 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd23 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd23 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd23 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd23 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd23 == add_ln1265_reg_147629)))) begin + acc_23_V_we1 = 1'b1; + end else begin + acc_23_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_24_V_address0 = acc_24_V_addr_49_reg_162909; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_24_V_address0 = acc_24_V_addr_44_reg_162501; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_24_V_address0 = acc_24_V_addr_45_reg_158008; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_24_V_address0 = acc_24_V_addr_39_reg_157587; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_24_V_address0 = acc_24_V_addr_46_reg_153068; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_24_V_address0 = acc_24_V_addr_40_reg_152660; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_24_V_address0 = acc_24_V_addr_41_reg_148167; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_24_V_address0 = acc_24_V_addr_37_reg_147765; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2554 == ap_CS_fsm)) begin + acc_24_V_address0 = acc_24_V_addr_52_reg_146828; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_24_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2519 == ap_CS_fsm)) begin + acc_24_V_address0 = acc_24_V_addr_50_reg_146606; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_24_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2483 == ap_CS_fsm)) begin + acc_24_V_address0 = acc_24_V_addr_51_reg_146357; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_24_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2448 == ap_CS_fsm)) begin + acc_24_V_address0 = acc_24_V_addr_48_reg_146135; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_24_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_24_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_24_V_address1 = acc_24_V_addr_49_reg_162909; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_24_V_address1 = acc_24_V_addr_44_reg_162501; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_24_V_address1 = acc_24_V_addr_45_reg_158008; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_24_V_address1 = acc_24_V_addr_39_reg_157587; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_24_V_address1 = acc_24_V_addr_46_reg_153068; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_24_V_address1 = acc_24_V_addr_40_reg_152660; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_24_V_address1 = acc_24_V_addr_41_reg_148167; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_24_V_address1 = acc_24_V_addr_37_reg_147765; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd1; + end else begin + acc_24_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2554 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2519 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2483 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2448 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_24_V_ce0 = 1'b1; + end else begin + acc_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_24_V_ce1 = 1'b1; + end else begin + acc_24_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2554 == ap_CS_fsm)) begin + acc_24_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_24_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2519 == ap_CS_fsm)) begin + acc_24_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_24_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2483 == ap_CS_fsm)) begin + acc_24_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_24_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2448 == ap_CS_fsm)) begin + acc_24_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_24_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_24_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_24_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2554 == ap_CS_fsm) | (ap_ST_fsm_state2519 == ap_CS_fsm) | (ap_ST_fsm_state2483 == ap_CS_fsm) | (ap_ST_fsm_state2448 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd24 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd24 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd24 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd24 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd24 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd24 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd24 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd24 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd24 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd24 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd24 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd24 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd24 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd24 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd24 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd24 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd24 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd24 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd24 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd24 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd24 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd24 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd24 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd24 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd24 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd24 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_24_V_we0 = 1'b1; + end else begin + acc_24_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd24 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd24 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd24 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd24 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd24 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd24 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd24 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd24 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd24 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd24 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd24 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd24 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd24 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd24 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd24 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd24 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd24 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd24 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd24 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd24 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd24 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd24 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd24 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd24 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd24 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd24 == add_ln1265_reg_147629)))) begin + acc_24_V_we1 = 1'b1; + end else begin + acc_24_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_25_V_address0 = acc_25_V_addr_48_reg_162915; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_25_V_address0 = acc_25_V_addr_44_reg_162507; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_25_V_address0 = acc_25_V_addr_45_reg_158014; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_25_V_address0 = acc_25_V_addr_39_reg_157593; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_25_V_address0 = acc_25_V_addr_46_reg_153074; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_25_V_address0 = acc_25_V_addr_40_reg_152666; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_25_V_address0 = acc_25_V_addr_41_reg_148173; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_25_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_25_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_25_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_25_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_25_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_25_V_address1 = acc_25_V_addr_48_reg_162915; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_25_V_address1 = acc_25_V_addr_44_reg_162507; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_25_V_address1 = acc_25_V_addr_45_reg_158014; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_25_V_address1 = acc_25_V_addr_39_reg_157593; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_25_V_address1 = acc_25_V_addr_46_reg_153074; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_25_V_address1 = acc_25_V_addr_40_reg_152666; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_25_V_address1 = acc_25_V_addr_41_reg_148173; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_25_V_address1 = acc_25_V_addr_37_reg_147771; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd1; + end else begin + acc_25_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_25_V_ce0 = 1'b1; + end else begin + acc_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_25_V_ce1 = 1'b1; + end else begin + acc_25_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_25_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_25_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_25_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_25_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_25_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_25_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd25 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd25 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd25 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd25 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd25 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd25 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd25 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd25 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd25 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd25 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd25 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd25 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd25 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd25 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd25 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd25 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd25 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd25 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd25 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd25 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd25 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd25 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd25 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd25 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd25 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd25 == add_ln203_7_fu_116022_p2)))) begin + acc_25_V_we0 = 1'b1; + end else begin + acc_25_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd25 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd25 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd25 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd25 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd25 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd25 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd25 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd25 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd25 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd25 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd25 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd25 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd25 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd25 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd25 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd25 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd25 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd25 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd25 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd25 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd25 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd25 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd25 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd25 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd25 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd25 == add_ln1265_reg_147629)))) begin + acc_25_V_we1 = 1'b1; + end else begin + acc_25_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_26_V_address0 = acc_26_V_addr_49_reg_162921; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_26_V_address0 = acc_26_V_addr_44_reg_162513; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_26_V_address0 = acc_26_V_addr_45_reg_158020; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_26_V_address0 = acc_26_V_addr_39_reg_157599; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_26_V_address0 = acc_26_V_addr_46_reg_153080; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_26_V_address0 = acc_26_V_addr_40_reg_152672; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_26_V_address0 = acc_26_V_addr_41_reg_148179; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_26_V_address0 = acc_26_V_addr_37_reg_147776; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2553 == ap_CS_fsm)) begin + acc_26_V_address0 = acc_26_V_addr_52_reg_146833; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_26_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2518 == ap_CS_fsm)) begin + acc_26_V_address0 = acc_26_V_addr_50_reg_146611; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_26_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2482 == ap_CS_fsm)) begin + acc_26_V_address0 = acc_26_V_addr_51_reg_146362; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_26_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2447 == ap_CS_fsm)) begin + acc_26_V_address0 = acc_26_V_addr_48_reg_146140; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_26_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_26_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_26_V_address1 = acc_26_V_addr_49_reg_162921; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_26_V_address1 = acc_26_V_addr_44_reg_162513; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_26_V_address1 = acc_26_V_addr_45_reg_158020; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_26_V_address1 = acc_26_V_addr_39_reg_157599; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_26_V_address1 = acc_26_V_addr_46_reg_153080; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_26_V_address1 = acc_26_V_addr_40_reg_152672; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_26_V_address1 = acc_26_V_addr_41_reg_148179; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_26_V_address1 = acc_26_V_addr_37_reg_147776; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd1; + end else begin + acc_26_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2553 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2518 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2482 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2447 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_26_V_ce0 = 1'b1; + end else begin + acc_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_26_V_ce1 = 1'b1; + end else begin + acc_26_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2553 == ap_CS_fsm)) begin + acc_26_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_26_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2518 == ap_CS_fsm)) begin + acc_26_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_26_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2482 == ap_CS_fsm)) begin + acc_26_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_26_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2447 == ap_CS_fsm)) begin + acc_26_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_26_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_26_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_26_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2553 == ap_CS_fsm) | (ap_ST_fsm_state2518 == ap_CS_fsm) | (ap_ST_fsm_state2482 == ap_CS_fsm) | (ap_ST_fsm_state2447 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd26 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd26 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd26 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd26 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd26 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd26 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd26 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd26 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd26 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd26 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd26 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd26 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd26 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd26 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd26 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd26 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd26 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd26 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd26 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd26 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd26 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd26 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd26 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd26 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd26 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd26 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_26_V_we0 = 1'b1; + end else begin + acc_26_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd26 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd26 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd26 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd26 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd26 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd26 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd26 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd26 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd26 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd26 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd26 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd26 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd26 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd26 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd26 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd26 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd26 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd26 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd26 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd26 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd26 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd26 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd26 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd26 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd26 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd26 == add_ln1265_reg_147629)))) begin + acc_26_V_we1 = 1'b1; + end else begin + acc_26_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_27_V_address0 = acc_27_V_addr_48_reg_162927; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_27_V_address0 = acc_27_V_addr_44_reg_162519; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_27_V_address0 = acc_27_V_addr_45_reg_158026; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_27_V_address0 = acc_27_V_addr_39_reg_157605; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_27_V_address0 = acc_27_V_addr_46_reg_153086; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_27_V_address0 = acc_27_V_addr_40_reg_152678; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_27_V_address0 = acc_27_V_addr_41_reg_148185; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_27_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_27_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_27_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_27_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_27_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_27_V_address1 = acc_27_V_addr_48_reg_162927; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_27_V_address1 = acc_27_V_addr_44_reg_162519; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_27_V_address1 = acc_27_V_addr_45_reg_158026; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_27_V_address1 = acc_27_V_addr_39_reg_157605; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_27_V_address1 = acc_27_V_addr_46_reg_153086; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_27_V_address1 = acc_27_V_addr_40_reg_152678; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_27_V_address1 = acc_27_V_addr_41_reg_148185; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_27_V_address1 = acc_27_V_addr_37_reg_147782; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd1; + end else begin + acc_27_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_27_V_ce0 = 1'b1; + end else begin + acc_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_27_V_ce1 = 1'b1; + end else begin + acc_27_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_27_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_27_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_27_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_27_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_27_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_27_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd27 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd27 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd27 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd27 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd27 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd27 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd27 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd27 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd27 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd27 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd27 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd27 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd27 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd27 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd27 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd27 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd27 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd27 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd27 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd27 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd27 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd27 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd27 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd27 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd27 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd27 == add_ln203_7_fu_116022_p2)))) begin + acc_27_V_we0 = 1'b1; + end else begin + acc_27_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd27 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd27 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd27 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd27 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd27 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd27 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd27 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd27 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd27 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd27 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd27 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd27 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd27 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd27 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd27 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd27 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd27 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd27 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd27 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd27 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd27 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd27 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd27 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd27 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd27 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd27 == add_ln1265_reg_147629)))) begin + acc_27_V_we1 = 1'b1; + end else begin + acc_27_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_28_V_address0 = acc_28_V_addr_49_reg_162933; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_28_V_address0 = acc_28_V_addr_44_reg_162525; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_28_V_address0 = acc_28_V_addr_45_reg_158032; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_28_V_address0 = acc_28_V_addr_39_reg_157611; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_28_V_address0 = acc_28_V_addr_46_reg_153092; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_28_V_address0 = acc_28_V_addr_40_reg_152684; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_28_V_address0 = acc_28_V_addr_41_reg_148191; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_28_V_address0 = acc_28_V_addr_37_reg_147787; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2552 == ap_CS_fsm)) begin + acc_28_V_address0 = acc_28_V_addr_52_reg_146838; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_28_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2517 == ap_CS_fsm)) begin + acc_28_V_address0 = acc_28_V_addr_50_reg_146616; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_28_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2481 == ap_CS_fsm)) begin + acc_28_V_address0 = acc_28_V_addr_51_reg_146367; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_28_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2446 == ap_CS_fsm)) begin + acc_28_V_address0 = acc_28_V_addr_48_reg_146145; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_28_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_28_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_28_V_address1 = acc_28_V_addr_49_reg_162933; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_28_V_address1 = acc_28_V_addr_44_reg_162525; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_28_V_address1 = acc_28_V_addr_45_reg_158032; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_28_V_address1 = acc_28_V_addr_39_reg_157611; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_28_V_address1 = acc_28_V_addr_46_reg_153092; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_28_V_address1 = acc_28_V_addr_40_reg_152684; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_28_V_address1 = acc_28_V_addr_41_reg_148191; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_28_V_address1 = acc_28_V_addr_37_reg_147787; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd1; + end else begin + acc_28_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2552 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2517 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2481 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2446 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_28_V_ce0 = 1'b1; + end else begin + acc_28_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_28_V_ce1 = 1'b1; + end else begin + acc_28_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2552 == ap_CS_fsm)) begin + acc_28_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_28_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2517 == ap_CS_fsm)) begin + acc_28_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_28_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2481 == ap_CS_fsm)) begin + acc_28_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_28_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2446 == ap_CS_fsm)) begin + acc_28_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_28_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_28_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_28_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2552 == ap_CS_fsm) | (ap_ST_fsm_state2517 == ap_CS_fsm) | (ap_ST_fsm_state2481 == ap_CS_fsm) | (ap_ST_fsm_state2446 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd28 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd28 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd28 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd28 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd28 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd28 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd28 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd28 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd28 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd28 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd28 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd28 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd28 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd28 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd28 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd28 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd28 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd28 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd28 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd28 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd28 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd28 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd28 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd28 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd28 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd28 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_28_V_we0 = 1'b1; + end else begin + acc_28_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd28 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd28 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd28 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd28 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd28 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd28 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd28 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd28 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd28 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd28 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd28 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd28 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd28 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd28 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd28 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd28 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd28 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd28 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd28 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd28 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd28 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd28 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd28 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd28 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd28 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd28 == add_ln1265_reg_147629)))) begin + acc_28_V_we1 = 1'b1; + end else begin + acc_28_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_29_V_address0 = acc_29_V_addr_48_reg_162939; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_29_V_address0 = acc_29_V_addr_44_reg_162531; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_29_V_address0 = acc_29_V_addr_45_reg_158038; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_29_V_address0 = acc_29_V_addr_39_reg_157617; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_29_V_address0 = acc_29_V_addr_46_reg_153098; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_29_V_address0 = acc_29_V_addr_40_reg_152690; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_29_V_address0 = acc_29_V_addr_41_reg_148197; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_29_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_29_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_29_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_29_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_29_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_29_V_address1 = acc_29_V_addr_48_reg_162939; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_29_V_address1 = acc_29_V_addr_44_reg_162531; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_29_V_address1 = acc_29_V_addr_45_reg_158038; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_29_V_address1 = acc_29_V_addr_39_reg_157617; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_29_V_address1 = acc_29_V_addr_46_reg_153098; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_29_V_address1 = acc_29_V_addr_40_reg_152690; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_29_V_address1 = acc_29_V_addr_41_reg_148197; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_29_V_address1 = acc_29_V_addr_37_reg_147793; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd1; + end else begin + acc_29_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_29_V_ce0 = 1'b1; + end else begin + acc_29_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_29_V_ce1 = 1'b1; + end else begin + acc_29_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_29_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_29_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_29_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_29_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_29_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_29_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd29 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd29 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd29 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd29 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd29 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd29 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd29 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd29 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd29 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd29 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd29 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd29 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd29 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd29 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd29 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd29 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd29 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd29 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd29 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd29 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd29 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd29 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd29 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd29 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd29 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd29 == add_ln203_7_fu_116022_p2)))) begin + acc_29_V_we0 = 1'b1; + end else begin + acc_29_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd29 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd29 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd29 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd29 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd29 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd29 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd29 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd29 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd29 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd29 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd29 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd29 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd29 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd29 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd29 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd29 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd29 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd29 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd29 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd29 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd29 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd29 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd29 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd29 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd29 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd29 == add_ln1265_reg_147629)))) begin + acc_29_V_we1 = 1'b1; + end else begin + acc_29_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_2_V_address0 = acc_2_V_addr_49_reg_162777; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_2_V_address0 = acc_2_V_addr_44_reg_162369; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_2_V_address0 = acc_2_V_addr_45_reg_157876; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_2_V_address0 = acc_2_V_addr_39_reg_157455; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_2_V_address0 = acc_2_V_addr_46_reg_152936; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_2_V_address0 = acc_2_V_addr_40_reg_152528; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_2_V_address0 = acc_2_V_addr_41_reg_148035; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_2_V_address0 = acc_2_V_addr_37_reg_147644; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2565 == ap_CS_fsm)) begin + acc_2_V_address0 = acc_2_V_addr_52_reg_146773; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_2_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2530 == ap_CS_fsm)) begin + acc_2_V_address0 = acc_2_V_addr_50_reg_146551; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_2_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2494 == ap_CS_fsm)) begin + acc_2_V_address0 = acc_2_V_addr_51_reg_146302; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_2_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2459 == ap_CS_fsm)) begin + acc_2_V_address0 = acc_2_V_addr_48_reg_146080; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_2_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_2_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_2_V_address1 = acc_2_V_addr_49_reg_162777; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_2_V_address1 = acc_2_V_addr_44_reg_162369; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_2_V_address1 = acc_2_V_addr_45_reg_157876; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_2_V_address1 = acc_2_V_addr_39_reg_157455; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_2_V_address1 = acc_2_V_addr_46_reg_152936; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_2_V_address1 = acc_2_V_addr_40_reg_152528; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_2_V_address1 = acc_2_V_addr_41_reg_148035; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_2_V_address1 = acc_2_V_addr_37_reg_147644; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd1; + end else begin + acc_2_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2565 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2530 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2494 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2459 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_2_V_ce0 = 1'b1; + end else begin + acc_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_2_V_ce1 = 1'b1; + end else begin + acc_2_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2565 == ap_CS_fsm)) begin + acc_2_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_2_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2530 == ap_CS_fsm)) begin + acc_2_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_2_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2494 == ap_CS_fsm)) begin + acc_2_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_2_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2459 == ap_CS_fsm)) begin + acc_2_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_2_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_2_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_2_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2565 == ap_CS_fsm) | (ap_ST_fsm_state2530 == ap_CS_fsm) | (ap_ST_fsm_state2494 == ap_CS_fsm) | (ap_ST_fsm_state2459 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd2 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd2 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd2 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd2 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd2 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd2 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd2 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd2 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd2 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd2 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd2 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd2 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd2 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd2 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd2 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd2 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd2 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd2 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd2 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd2 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd2 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd2 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd2 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd2 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd2 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd2 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_2_V_we0 = 1'b1; + end else begin + acc_2_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd2 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd2 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd2 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd2 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd2 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd2 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd2 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd2 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd2 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd2 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd2 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd2 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd2 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd2 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd2 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd2 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd2 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd2 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd2 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd2 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd2 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd2 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd2 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd2 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd2 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd2 == add_ln1265_reg_147629)))) begin + acc_2_V_we1 = 1'b1; + end else begin + acc_2_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_30_V_address0 = acc_30_V_addr_49_reg_162945; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_30_V_address0 = acc_30_V_addr_44_reg_162537; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_30_V_address0 = acc_30_V_addr_45_reg_158044; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_30_V_address0 = acc_30_V_addr_39_reg_157623; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_30_V_address0 = acc_30_V_addr_46_reg_153104; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_30_V_address0 = acc_30_V_addr_40_reg_152696; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_30_V_address0 = acc_30_V_addr_41_reg_148203; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_30_V_address0 = acc_30_V_addr_37_reg_147798; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2551 == ap_CS_fsm)) begin + acc_30_V_address0 = acc_30_V_addr_52_reg_146843; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_30_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2516 == ap_CS_fsm)) begin + acc_30_V_address0 = acc_30_V_addr_50_reg_146621; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_30_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2480 == ap_CS_fsm)) begin + acc_30_V_address0 = acc_30_V_addr_51_reg_146372; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_30_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2445 == ap_CS_fsm)) begin + acc_30_V_address0 = acc_30_V_addr_48_reg_146150; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_30_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_30_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_30_V_address1 = acc_30_V_addr_49_reg_162945; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_30_V_address1 = acc_30_V_addr_44_reg_162537; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_30_V_address1 = acc_30_V_addr_45_reg_158044; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_30_V_address1 = acc_30_V_addr_39_reg_157623; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_30_V_address1 = acc_30_V_addr_46_reg_153104; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_30_V_address1 = acc_30_V_addr_40_reg_152696; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_30_V_address1 = acc_30_V_addr_41_reg_148203; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_30_V_address1 = acc_30_V_addr_37_reg_147798; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd1; + end else begin + acc_30_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2551 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2516 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2480 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2445 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_30_V_ce0 = 1'b1; + end else begin + acc_30_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_30_V_ce1 = 1'b1; + end else begin + acc_30_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2551 == ap_CS_fsm)) begin + acc_30_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_30_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2516 == ap_CS_fsm)) begin + acc_30_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_30_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2480 == ap_CS_fsm)) begin + acc_30_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_30_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2445 == ap_CS_fsm)) begin + acc_30_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_30_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_30_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_30_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2551 == ap_CS_fsm) | (ap_ST_fsm_state2516 == ap_CS_fsm) | (ap_ST_fsm_state2480 == ap_CS_fsm) | (ap_ST_fsm_state2445 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd30 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd30 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd30 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd30 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd30 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd30 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd30 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd30 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd30 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd30 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd30 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd30 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd30 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd30 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd30 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd30 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd30 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd30 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd30 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd30 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd30 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd30 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd30 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd30 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd30 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd30 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_30_V_we0 = 1'b1; + end else begin + acc_30_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd30 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd30 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd30 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd30 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd30 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd30 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd30 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd30 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd30 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd30 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd30 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd30 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd30 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd30 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd30 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd30 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd30 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd30 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd30 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd30 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd30 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd30 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd30 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd30 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd30 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd30 == add_ln1265_reg_147629)))) begin + acc_30_V_we1 = 1'b1; + end else begin + acc_30_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_31_V_address0 = acc_31_V_addr_48_reg_162951; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_31_V_address0 = acc_31_V_addr_44_reg_162543; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_31_V_address0 = acc_31_V_addr_45_reg_158050; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_31_V_address0 = acc_31_V_addr_39_reg_157629; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_31_V_address0 = acc_31_V_addr_46_reg_153110; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_31_V_address0 = acc_31_V_addr_40_reg_152702; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_31_V_address0 = acc_31_V_addr_41_reg_148209; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_31_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_31_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_31_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_31_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_31_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_31_V_address1 = acc_31_V_addr_48_reg_162951; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_31_V_address1 = acc_31_V_addr_44_reg_162543; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_31_V_address1 = acc_31_V_addr_45_reg_158050; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_31_V_address1 = acc_31_V_addr_39_reg_157629; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_31_V_address1 = acc_31_V_addr_46_reg_153110; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_31_V_address1 = acc_31_V_addr_40_reg_152702; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_31_V_address1 = acc_31_V_addr_41_reg_148209; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_31_V_address1 = acc_31_V_addr_37_reg_147804; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd1; + end else begin + acc_31_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_31_V_ce0 = 1'b1; + end else begin + acc_31_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_31_V_ce1 = 1'b1; + end else begin + acc_31_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_31_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_31_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_31_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_31_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_31_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_31_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd31 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd31 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd31 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd31 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd31 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd31 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd31 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd31 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd31 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd31 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd31 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd31 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd31 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd31 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd31 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd31 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd31 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd31 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd31 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd31 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd31 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd31 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd31 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd31 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd31 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd31 == add_ln203_7_fu_116022_p2)))) begin + acc_31_V_we0 = 1'b1; + end else begin + acc_31_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd31 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd31 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd31 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd31 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd31 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd31 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd31 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd31 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd31 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd31 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd31 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd31 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd31 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd31 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd31 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd31 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd31 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd31 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd31 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd31 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd31 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd31 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd31 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd31 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd31 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd31 == add_ln1265_reg_147629)))) begin + acc_31_V_we1 = 1'b1; + end else begin + acc_31_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_32_V_address0 = acc_32_V_addr_49_reg_162957; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_32_V_address0 = acc_32_V_addr_44_reg_162549; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_32_V_address0 = acc_32_V_addr_45_reg_158056; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_32_V_address0 = acc_32_V_addr_39_reg_157635; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_32_V_address0 = acc_32_V_addr_46_reg_153116; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_32_V_address0 = acc_32_V_addr_40_reg_152708; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_32_V_address0 = acc_32_V_addr_41_reg_148215; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_32_V_address0 = acc_32_V_addr_37_reg_147809; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2550 == ap_CS_fsm)) begin + acc_32_V_address0 = acc_32_V_addr_52_reg_146848; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_32_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2515 == ap_CS_fsm)) begin + acc_32_V_address0 = acc_32_V_addr_50_reg_146626; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_32_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2479 == ap_CS_fsm)) begin + acc_32_V_address0 = acc_32_V_addr_51_reg_146377; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_32_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2444 == ap_CS_fsm)) begin + acc_32_V_address0 = acc_32_V_addr_48_reg_146155; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_32_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_32_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_32_V_address1 = acc_32_V_addr_49_reg_162957; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_32_V_address1 = acc_32_V_addr_44_reg_162549; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_32_V_address1 = acc_32_V_addr_45_reg_158056; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_32_V_address1 = acc_32_V_addr_39_reg_157635; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_32_V_address1 = acc_32_V_addr_46_reg_153116; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_32_V_address1 = acc_32_V_addr_40_reg_152708; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_32_V_address1 = acc_32_V_addr_41_reg_148215; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_32_V_address1 = acc_32_V_addr_37_reg_147809; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd1; + end else begin + acc_32_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2550 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2515 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2479 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2444 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_32_V_ce0 = 1'b1; + end else begin + acc_32_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_32_V_ce1 = 1'b1; + end else begin + acc_32_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2550 == ap_CS_fsm)) begin + acc_32_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_32_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2515 == ap_CS_fsm)) begin + acc_32_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_32_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2479 == ap_CS_fsm)) begin + acc_32_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_32_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2444 == ap_CS_fsm)) begin + acc_32_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_32_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_32_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_32_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2550 == ap_CS_fsm) | (ap_ST_fsm_state2515 == ap_CS_fsm) | (ap_ST_fsm_state2479 == ap_CS_fsm) | (ap_ST_fsm_state2444 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd32 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd32 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd32 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd32 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd32 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd32 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd32 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd32 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd32 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd32 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd32 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd32 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd32 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd32 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd32 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd32 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd32 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd32 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd32 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd32 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd32 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd32 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd32 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd32 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd32 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd32 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_32_V_we0 = 1'b1; + end else begin + acc_32_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd32 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd32 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd32 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd32 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd32 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd32 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd32 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd32 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd32 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd32 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd32 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd32 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd32 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd32 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd32 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd32 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd32 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd32 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd32 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd32 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd32 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd32 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd32 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd32 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd32 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd32 == add_ln1265_reg_147629)))) begin + acc_32_V_we1 = 1'b1; + end else begin + acc_32_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_33_V_address0 = acc_33_V_addr_48_reg_162963; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_33_V_address0 = acc_33_V_addr_44_reg_162555; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_33_V_address0 = acc_33_V_addr_45_reg_158062; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_33_V_address0 = acc_33_V_addr_39_reg_157641; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_33_V_address0 = acc_33_V_addr_46_reg_153122; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_33_V_address0 = acc_33_V_addr_40_reg_152714; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_33_V_address0 = acc_33_V_addr_41_reg_148221; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_33_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_33_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_33_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_33_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_33_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_33_V_address1 = acc_33_V_addr_48_reg_162963; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_33_V_address1 = acc_33_V_addr_44_reg_162555; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_33_V_address1 = acc_33_V_addr_45_reg_158062; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_33_V_address1 = acc_33_V_addr_39_reg_157641; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_33_V_address1 = acc_33_V_addr_46_reg_153122; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_33_V_address1 = acc_33_V_addr_40_reg_152714; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_33_V_address1 = acc_33_V_addr_41_reg_148221; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_33_V_address1 = acc_33_V_addr_37_reg_147815; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd1; + end else begin + acc_33_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_33_V_ce0 = 1'b1; + end else begin + acc_33_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_33_V_ce1 = 1'b1; + end else begin + acc_33_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_33_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_33_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_33_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_33_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_33_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_33_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd33 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd33 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd33 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd33 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd33 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd33 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd33 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd33 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd33 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd33 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd33 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd33 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd33 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd33 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd33 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd33 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd33 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd33 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd33 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd33 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd33 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd33 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd33 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd33 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd33 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd33 == add_ln203_7_fu_116022_p2)))) begin + acc_33_V_we0 = 1'b1; + end else begin + acc_33_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd33 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd33 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd33 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd33 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd33 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd33 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd33 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd33 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd33 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd33 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd33 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd33 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd33 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd33 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd33 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd33 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd33 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd33 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd33 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd33 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd33 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd33 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd33 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd33 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd33 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd33 == add_ln1265_reg_147629)))) begin + acc_33_V_we1 = 1'b1; + end else begin + acc_33_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_34_V_address0 = acc_34_V_addr_49_reg_162969; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_34_V_address0 = acc_34_V_addr_44_reg_162561; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_34_V_address0 = acc_34_V_addr_45_reg_158068; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_34_V_address0 = acc_34_V_addr_39_reg_157647; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_34_V_address0 = acc_34_V_addr_46_reg_153128; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_34_V_address0 = acc_34_V_addr_40_reg_152720; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_34_V_address0 = acc_34_V_addr_41_reg_148227; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_34_V_address0 = acc_34_V_addr_37_reg_147820; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2549 == ap_CS_fsm)) begin + acc_34_V_address0 = acc_34_V_addr_52_reg_146853; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_34_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2514 == ap_CS_fsm)) begin + acc_34_V_address0 = acc_34_V_addr_50_reg_146631; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_34_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2478 == ap_CS_fsm)) begin + acc_34_V_address0 = acc_34_V_addr_51_reg_146382; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_34_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2443 == ap_CS_fsm)) begin + acc_34_V_address0 = acc_34_V_addr_48_reg_146160; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_34_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_34_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_34_V_address1 = acc_34_V_addr_49_reg_162969; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_34_V_address1 = acc_34_V_addr_44_reg_162561; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_34_V_address1 = acc_34_V_addr_45_reg_158068; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_34_V_address1 = acc_34_V_addr_39_reg_157647; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_34_V_address1 = acc_34_V_addr_46_reg_153128; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_34_V_address1 = acc_34_V_addr_40_reg_152720; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_34_V_address1 = acc_34_V_addr_41_reg_148227; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_34_V_address1 = acc_34_V_addr_37_reg_147820; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd1; + end else begin + acc_34_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2549 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2514 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2478 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2443 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_34_V_ce0 = 1'b1; + end else begin + acc_34_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_34_V_ce1 = 1'b1; + end else begin + acc_34_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2549 == ap_CS_fsm)) begin + acc_34_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_34_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2514 == ap_CS_fsm)) begin + acc_34_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_34_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2478 == ap_CS_fsm)) begin + acc_34_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_34_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2443 == ap_CS_fsm)) begin + acc_34_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_34_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_34_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_34_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2549 == ap_CS_fsm) | (ap_ST_fsm_state2514 == ap_CS_fsm) | (ap_ST_fsm_state2478 == ap_CS_fsm) | (ap_ST_fsm_state2443 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd34 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd34 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd34 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd34 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd34 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd34 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd34 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd34 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd34 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd34 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd34 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd34 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd34 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd34 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd34 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd34 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd34 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd34 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd34 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd34 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd34 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd34 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd34 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd34 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd34 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd34 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_34_V_we0 = 1'b1; + end else begin + acc_34_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd34 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd34 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd34 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd34 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd34 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd34 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd34 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd34 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd34 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd34 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd34 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd34 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd34 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd34 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd34 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd34 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd34 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd34 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd34 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd34 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd34 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd34 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd34 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd34 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd34 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd34 == add_ln1265_reg_147629)))) begin + acc_34_V_we1 = 1'b1; + end else begin + acc_34_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_35_V_address0 = acc_35_V_addr_48_reg_162975; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_35_V_address0 = acc_35_V_addr_44_reg_162567; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_35_V_address0 = acc_35_V_addr_45_reg_158074; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_35_V_address0 = acc_35_V_addr_39_reg_157653; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_35_V_address0 = acc_35_V_addr_46_reg_153134; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_35_V_address0 = acc_35_V_addr_40_reg_152726; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_35_V_address0 = acc_35_V_addr_41_reg_148233; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_35_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_35_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_35_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_35_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_35_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_35_V_address1 = acc_35_V_addr_48_reg_162975; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_35_V_address1 = acc_35_V_addr_44_reg_162567; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_35_V_address1 = acc_35_V_addr_45_reg_158074; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_35_V_address1 = acc_35_V_addr_39_reg_157653; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_35_V_address1 = acc_35_V_addr_46_reg_153134; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_35_V_address1 = acc_35_V_addr_40_reg_152726; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_35_V_address1 = acc_35_V_addr_41_reg_148233; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_35_V_address1 = acc_35_V_addr_37_reg_147826; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd1; + end else begin + acc_35_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_35_V_ce0 = 1'b1; + end else begin + acc_35_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_35_V_ce1 = 1'b1; + end else begin + acc_35_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_35_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_35_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_35_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_35_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_35_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_35_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd35 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd35 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd35 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd35 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd35 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd35 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd35 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd35 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd35 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd35 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd35 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd35 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd35 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd35 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd35 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd35 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd35 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd35 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd35 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd35 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd35 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd35 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd35 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd35 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd35 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd35 == add_ln203_7_fu_116022_p2)))) begin + acc_35_V_we0 = 1'b1; + end else begin + acc_35_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd35 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd35 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd35 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd35 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd35 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd35 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd35 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd35 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd35 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd35 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd35 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd35 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd35 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd35 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd35 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd35 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd35 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd35 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd35 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd35 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd35 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd35 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd35 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd35 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd35 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd35 == add_ln1265_reg_147629)))) begin + acc_35_V_we1 = 1'b1; + end else begin + acc_35_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_36_V_address0 = acc_36_V_addr_49_reg_162981; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_36_V_address0 = acc_36_V_addr_44_reg_162573; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_36_V_address0 = acc_36_V_addr_45_reg_158080; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_36_V_address0 = acc_36_V_addr_39_reg_157659; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_36_V_address0 = acc_36_V_addr_46_reg_153140; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_36_V_address0 = acc_36_V_addr_40_reg_152732; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_36_V_address0 = acc_36_V_addr_41_reg_148239; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_36_V_address0 = acc_36_V_addr_37_reg_147831; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2548 == ap_CS_fsm)) begin + acc_36_V_address0 = acc_36_V_addr_52_reg_146858; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_36_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2513 == ap_CS_fsm)) begin + acc_36_V_address0 = acc_36_V_addr_50_reg_146636; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_36_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2477 == ap_CS_fsm)) begin + acc_36_V_address0 = acc_36_V_addr_51_reg_146387; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_36_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2442 == ap_CS_fsm)) begin + acc_36_V_address0 = acc_36_V_addr_48_reg_146165; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_36_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_36_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_36_V_address1 = acc_36_V_addr_49_reg_162981; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_36_V_address1 = acc_36_V_addr_44_reg_162573; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_36_V_address1 = acc_36_V_addr_45_reg_158080; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_36_V_address1 = acc_36_V_addr_39_reg_157659; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_36_V_address1 = acc_36_V_addr_46_reg_153140; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_36_V_address1 = acc_36_V_addr_40_reg_152732; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_36_V_address1 = acc_36_V_addr_41_reg_148239; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_36_V_address1 = acc_36_V_addr_37_reg_147831; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd1; + end else begin + acc_36_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2548 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2513 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2477 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2442 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_36_V_ce0 = 1'b1; + end else begin + acc_36_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_36_V_ce1 = 1'b1; + end else begin + acc_36_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2548 == ap_CS_fsm)) begin + acc_36_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_36_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2513 == ap_CS_fsm)) begin + acc_36_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_36_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2477 == ap_CS_fsm)) begin + acc_36_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_36_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2442 == ap_CS_fsm)) begin + acc_36_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_36_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_36_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_36_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2548 == ap_CS_fsm) | (ap_ST_fsm_state2513 == ap_CS_fsm) | (ap_ST_fsm_state2477 == ap_CS_fsm) | (ap_ST_fsm_state2442 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd36 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd36 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd36 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd36 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd36 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd36 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd36 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd36 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd36 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd36 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd36 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd36 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd36 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd36 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd36 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd36 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd36 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd36 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd36 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd36 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd36 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd36 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd36 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd36 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd36 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd36 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_36_V_we0 = 1'b1; + end else begin + acc_36_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd36 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd36 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd36 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd36 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd36 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd36 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd36 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd36 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd36 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd36 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd36 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd36 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd36 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd36 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd36 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd36 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd36 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd36 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd36 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd36 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd36 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd36 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd36 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd36 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd36 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd36 == add_ln1265_reg_147629)))) begin + acc_36_V_we1 = 1'b1; + end else begin + acc_36_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_37_V_address0 = acc_37_V_addr_48_reg_162987; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_37_V_address0 = acc_37_V_addr_44_reg_162579; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_37_V_address0 = acc_37_V_addr_45_reg_158086; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_37_V_address0 = acc_37_V_addr_39_reg_157665; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_37_V_address0 = acc_37_V_addr_46_reg_153146; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_37_V_address0 = acc_37_V_addr_40_reg_152738; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_37_V_address0 = acc_37_V_addr_41_reg_148245; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_37_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_37_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_37_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_37_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_37_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_37_V_address1 = acc_37_V_addr_48_reg_162987; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_37_V_address1 = acc_37_V_addr_44_reg_162579; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_37_V_address1 = acc_37_V_addr_45_reg_158086; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_37_V_address1 = acc_37_V_addr_39_reg_157665; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_37_V_address1 = acc_37_V_addr_46_reg_153146; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_37_V_address1 = acc_37_V_addr_40_reg_152738; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_37_V_address1 = acc_37_V_addr_41_reg_148245; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_37_V_address1 = acc_37_V_addr_37_reg_147837; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd1; + end else begin + acc_37_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_37_V_ce0 = 1'b1; + end else begin + acc_37_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_37_V_ce1 = 1'b1; + end else begin + acc_37_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_37_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_37_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_37_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_37_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_37_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_37_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd37 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd37 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd37 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd37 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd37 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd37 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd37 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd37 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd37 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd37 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd37 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd37 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd37 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd37 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd37 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd37 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd37 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd37 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd37 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd37 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd37 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd37 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd37 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd37 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd37 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd37 == add_ln203_7_fu_116022_p2)))) begin + acc_37_V_we0 = 1'b1; + end else begin + acc_37_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd37 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd37 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd37 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd37 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd37 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd37 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd37 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd37 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd37 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd37 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd37 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd37 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd37 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd37 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd37 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd37 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd37 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd37 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd37 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd37 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd37 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd37 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd37 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd37 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd37 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd37 == add_ln1265_reg_147629)))) begin + acc_37_V_we1 = 1'b1; + end else begin + acc_37_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_38_V_address0 = acc_38_V_addr_49_reg_162993; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_38_V_address0 = acc_38_V_addr_44_reg_162585; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_38_V_address0 = acc_38_V_addr_45_reg_158092; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_38_V_address0 = acc_38_V_addr_39_reg_157671; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_38_V_address0 = acc_38_V_addr_46_reg_153152; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_38_V_address0 = acc_38_V_addr_40_reg_152744; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_38_V_address0 = acc_38_V_addr_41_reg_148251; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_38_V_address0 = acc_38_V_addr_37_reg_147842; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2547 == ap_CS_fsm)) begin + acc_38_V_address0 = acc_38_V_addr_52_reg_146863; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_38_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2512 == ap_CS_fsm)) begin + acc_38_V_address0 = acc_38_V_addr_50_reg_146641; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_38_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2476 == ap_CS_fsm)) begin + acc_38_V_address0 = acc_38_V_addr_51_reg_146392; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_38_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2441 == ap_CS_fsm)) begin + acc_38_V_address0 = acc_38_V_addr_48_reg_146170; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_38_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_38_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_38_V_address1 = acc_38_V_addr_49_reg_162993; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_38_V_address1 = acc_38_V_addr_44_reg_162585; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_38_V_address1 = acc_38_V_addr_45_reg_158092; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_38_V_address1 = acc_38_V_addr_39_reg_157671; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_38_V_address1 = acc_38_V_addr_46_reg_153152; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_38_V_address1 = acc_38_V_addr_40_reg_152744; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_38_V_address1 = acc_38_V_addr_41_reg_148251; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_38_V_address1 = acc_38_V_addr_37_reg_147842; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd1; + end else begin + acc_38_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2547 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2512 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2476 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2441 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_38_V_ce0 = 1'b1; + end else begin + acc_38_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_38_V_ce1 = 1'b1; + end else begin + acc_38_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2547 == ap_CS_fsm)) begin + acc_38_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_38_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2512 == ap_CS_fsm)) begin + acc_38_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_38_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2476 == ap_CS_fsm)) begin + acc_38_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_38_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2441 == ap_CS_fsm)) begin + acc_38_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_38_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_38_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_38_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2547 == ap_CS_fsm) | (ap_ST_fsm_state2512 == ap_CS_fsm) | (ap_ST_fsm_state2476 == ap_CS_fsm) | (ap_ST_fsm_state2441 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd38 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd38 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd38 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd38 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd38 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd38 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd38 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd38 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd38 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd38 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd38 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd38 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd38 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd38 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd38 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd38 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd38 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd38 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd38 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd38 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd38 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd38 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd38 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd38 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd38 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd38 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_38_V_we0 = 1'b1; + end else begin + acc_38_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd38 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd38 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd38 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd38 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd38 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd38 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd38 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd38 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd38 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd38 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd38 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd38 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd38 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd38 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd38 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd38 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd38 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd38 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd38 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd38 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd38 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd38 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd38 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd38 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd38 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd38 == add_ln1265_reg_147629)))) begin + acc_38_V_we1 = 1'b1; + end else begin + acc_38_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_39_V_address0 = acc_39_V_addr_48_reg_162999; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_39_V_address0 = acc_39_V_addr_44_reg_162591; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_39_V_address0 = acc_39_V_addr_45_reg_158098; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_39_V_address0 = acc_39_V_addr_39_reg_157677; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_39_V_address0 = acc_39_V_addr_46_reg_153158; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_39_V_address0 = acc_39_V_addr_40_reg_152750; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_39_V_address0 = acc_39_V_addr_41_reg_148257; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_39_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_39_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_39_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_39_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_39_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_39_V_address1 = acc_39_V_addr_48_reg_162999; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_39_V_address1 = acc_39_V_addr_44_reg_162591; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_39_V_address1 = acc_39_V_addr_45_reg_158098; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_39_V_address1 = acc_39_V_addr_39_reg_157677; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_39_V_address1 = acc_39_V_addr_46_reg_153158; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_39_V_address1 = acc_39_V_addr_40_reg_152750; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_39_V_address1 = acc_39_V_addr_41_reg_148257; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_39_V_address1 = acc_39_V_addr_37_reg_147848; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd1; + end else begin + acc_39_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_39_V_ce0 = 1'b1; + end else begin + acc_39_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_39_V_ce1 = 1'b1; + end else begin + acc_39_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_39_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_39_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_39_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_39_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_39_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_39_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd39 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd39 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd39 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd39 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd39 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd39 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd39 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd39 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd39 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd39 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd39 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd39 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd39 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd39 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd39 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd39 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd39 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd39 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd39 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd39 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd39 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd39 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd39 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd39 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd39 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd39 == add_ln203_7_fu_116022_p2)))) begin + acc_39_V_we0 = 1'b1; + end else begin + acc_39_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd39 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd39 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd39 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd39 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd39 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd39 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd39 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd39 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd39 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd39 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd39 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd39 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd39 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd39 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd39 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd39 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd39 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd39 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd39 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd39 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd39 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd39 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd39 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd39 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd39 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd39 == add_ln1265_reg_147629)))) begin + acc_39_V_we1 = 1'b1; + end else begin + acc_39_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_3_V_address0 = acc_3_V_addr_48_reg_162783; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_3_V_address0 = acc_3_V_addr_44_reg_162375; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_3_V_address0 = acc_3_V_addr_45_reg_157882; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_3_V_address0 = acc_3_V_addr_39_reg_157461; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_3_V_address0 = acc_3_V_addr_46_reg_152942; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_3_V_address0 = acc_3_V_addr_40_reg_152534; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_3_V_address0 = acc_3_V_addr_41_reg_148041; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_3_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_3_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_3_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_3_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_3_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_3_V_address1 = acc_3_V_addr_48_reg_162783; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_3_V_address1 = acc_3_V_addr_44_reg_162375; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_3_V_address1 = acc_3_V_addr_45_reg_157882; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_3_V_address1 = acc_3_V_addr_39_reg_157461; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_3_V_address1 = acc_3_V_addr_46_reg_152942; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_3_V_address1 = acc_3_V_addr_40_reg_152534; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_3_V_address1 = acc_3_V_addr_41_reg_148041; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_3_V_address1 = acc_3_V_addr_37_reg_147650; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd1; + end else begin + acc_3_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_3_V_ce0 = 1'b1; + end else begin + acc_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_3_V_ce1 = 1'b1; + end else begin + acc_3_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_3_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_3_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_3_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_3_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_3_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_3_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd3 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd3 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd3 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd3 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd3 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd3 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd3 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd3 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd3 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd3 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd3 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd3 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd3 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd3 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd3 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd3 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd3 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd3 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd3 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd3 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd3 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd3 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd3 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd3 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd3 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd3 == add_ln203_7_fu_116022_p2)))) begin + acc_3_V_we0 = 1'b1; + end else begin + acc_3_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd3 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd3 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd3 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd3 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd3 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd3 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd3 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd3 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd3 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd3 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd3 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd3 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd3 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd3 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd3 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd3 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd3 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd3 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd3 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd3 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd3 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd3 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd3 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd3 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd3 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd3 == add_ln1265_reg_147629)))) begin + acc_3_V_we1 = 1'b1; + end else begin + acc_3_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_40_V_address0 = acc_40_V_addr_49_reg_163005; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_40_V_address0 = acc_40_V_addr_44_reg_162597; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_40_V_address0 = acc_40_V_addr_45_reg_158104; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_40_V_address0 = acc_40_V_addr_39_reg_157683; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_40_V_address0 = acc_40_V_addr_46_reg_153164; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_40_V_address0 = acc_40_V_addr_40_reg_152756; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_40_V_address0 = acc_40_V_addr_41_reg_148263; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_40_V_address0 = acc_40_V_addr_37_reg_147853; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2546 == ap_CS_fsm)) begin + acc_40_V_address0 = acc_40_V_addr_52_reg_146868; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_40_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2511 == ap_CS_fsm)) begin + acc_40_V_address0 = acc_40_V_addr_50_reg_146646; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_40_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2475 == ap_CS_fsm)) begin + acc_40_V_address0 = acc_40_V_addr_51_reg_146397; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_40_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2440 == ap_CS_fsm)) begin + acc_40_V_address0 = acc_40_V_addr_48_reg_146175; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_40_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_40_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_40_V_address1 = acc_40_V_addr_49_reg_163005; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_40_V_address1 = acc_40_V_addr_44_reg_162597; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_40_V_address1 = acc_40_V_addr_45_reg_158104; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_40_V_address1 = acc_40_V_addr_39_reg_157683; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_40_V_address1 = acc_40_V_addr_46_reg_153164; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_40_V_address1 = acc_40_V_addr_40_reg_152756; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_40_V_address1 = acc_40_V_addr_41_reg_148263; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_40_V_address1 = acc_40_V_addr_37_reg_147853; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd1; + end else begin + acc_40_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2546 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2511 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2475 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2440 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_40_V_ce0 = 1'b1; + end else begin + acc_40_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_40_V_ce1 = 1'b1; + end else begin + acc_40_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2546 == ap_CS_fsm)) begin + acc_40_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_40_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2511 == ap_CS_fsm)) begin + acc_40_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_40_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2475 == ap_CS_fsm)) begin + acc_40_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_40_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2440 == ap_CS_fsm)) begin + acc_40_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_40_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_40_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_40_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2546 == ap_CS_fsm) | (ap_ST_fsm_state2511 == ap_CS_fsm) | (ap_ST_fsm_state2475 == ap_CS_fsm) | (ap_ST_fsm_state2440 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd40 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd40 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd40 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd40 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd40 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd40 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd40 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd40 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd40 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd40 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd40 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd40 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd40 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd40 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd40 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd40 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd40 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd40 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd40 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd40 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd40 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd40 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd40 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd40 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd40 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd40 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_40_V_we0 = 1'b1; + end else begin + acc_40_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd40 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd40 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd40 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd40 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd40 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd40 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd40 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd40 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd40 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd40 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd40 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd40 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd40 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd40 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd40 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd40 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd40 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd40 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd40 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd40 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd40 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd40 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd40 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd40 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd40 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd40 == add_ln1265_reg_147629)))) begin + acc_40_V_we1 = 1'b1; + end else begin + acc_40_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_41_V_address0 = acc_41_V_addr_48_reg_163011; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_41_V_address0 = acc_41_V_addr_44_reg_162603; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_41_V_address0 = acc_41_V_addr_45_reg_158110; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_41_V_address0 = acc_41_V_addr_39_reg_157689; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_41_V_address0 = acc_41_V_addr_46_reg_153170; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_41_V_address0 = acc_41_V_addr_40_reg_152762; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_41_V_address0 = acc_41_V_addr_41_reg_148269; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_41_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_41_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_41_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_41_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_41_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_41_V_address1 = acc_41_V_addr_48_reg_163011; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_41_V_address1 = acc_41_V_addr_44_reg_162603; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_41_V_address1 = acc_41_V_addr_45_reg_158110; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_41_V_address1 = acc_41_V_addr_39_reg_157689; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_41_V_address1 = acc_41_V_addr_46_reg_153170; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_41_V_address1 = acc_41_V_addr_40_reg_152762; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_41_V_address1 = acc_41_V_addr_41_reg_148269; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_41_V_address1 = acc_41_V_addr_37_reg_147859; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd1; + end else begin + acc_41_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_41_V_ce0 = 1'b1; + end else begin + acc_41_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_41_V_ce1 = 1'b1; + end else begin + acc_41_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_41_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_41_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_41_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_41_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_41_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_41_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd41 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd41 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd41 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd41 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd41 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd41 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd41 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd41 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd41 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd41 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd41 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd41 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd41 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd41 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd41 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd41 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd41 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd41 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd41 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd41 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd41 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd41 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd41 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd41 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd41 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd41 == add_ln203_7_fu_116022_p2)))) begin + acc_41_V_we0 = 1'b1; + end else begin + acc_41_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd41 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd41 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd41 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd41 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd41 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd41 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd41 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd41 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd41 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd41 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd41 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd41 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd41 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd41 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd41 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd41 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd41 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd41 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd41 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd41 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd41 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd41 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd41 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd41 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd41 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd41 == add_ln1265_reg_147629)))) begin + acc_41_V_we1 = 1'b1; + end else begin + acc_41_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_42_V_address0 = acc_42_V_addr_49_reg_163017; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_42_V_address0 = acc_42_V_addr_44_reg_162609; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_42_V_address0 = acc_42_V_addr_45_reg_158116; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_42_V_address0 = acc_42_V_addr_39_reg_157695; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_42_V_address0 = acc_42_V_addr_46_reg_153176; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_42_V_address0 = acc_42_V_addr_40_reg_152768; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_42_V_address0 = acc_42_V_addr_41_reg_148275; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_42_V_address0 = acc_42_V_addr_37_reg_147864; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2545 == ap_CS_fsm)) begin + acc_42_V_address0 = acc_42_V_addr_52_reg_146873; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_42_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2510 == ap_CS_fsm)) begin + acc_42_V_address0 = acc_42_V_addr_50_reg_146651; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_42_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2474 == ap_CS_fsm)) begin + acc_42_V_address0 = acc_42_V_addr_51_reg_146402; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_42_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2439 == ap_CS_fsm)) begin + acc_42_V_address0 = acc_42_V_addr_48_reg_146180; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_42_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_42_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_42_V_address1 = acc_42_V_addr_49_reg_163017; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_42_V_address1 = acc_42_V_addr_44_reg_162609; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_42_V_address1 = acc_42_V_addr_45_reg_158116; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_42_V_address1 = acc_42_V_addr_39_reg_157695; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_42_V_address1 = acc_42_V_addr_46_reg_153176; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_42_V_address1 = acc_42_V_addr_40_reg_152768; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_42_V_address1 = acc_42_V_addr_41_reg_148275; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_42_V_address1 = acc_42_V_addr_37_reg_147864; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd1; + end else begin + acc_42_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2545 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2510 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2474 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2439 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_42_V_ce0 = 1'b1; + end else begin + acc_42_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_42_V_ce1 = 1'b1; + end else begin + acc_42_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2545 == ap_CS_fsm)) begin + acc_42_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_42_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2510 == ap_CS_fsm)) begin + acc_42_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_42_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2474 == ap_CS_fsm)) begin + acc_42_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_42_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2439 == ap_CS_fsm)) begin + acc_42_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_42_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_42_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_42_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2545 == ap_CS_fsm) | (ap_ST_fsm_state2510 == ap_CS_fsm) | (ap_ST_fsm_state2474 == ap_CS_fsm) | (ap_ST_fsm_state2439 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd42 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd42 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd42 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd42 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd42 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd42 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd42 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd42 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd42 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd42 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd42 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd42 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd42 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd42 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd42 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd42 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd42 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd42 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd42 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd42 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd42 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd42 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd42 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd42 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd42 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd42 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_42_V_we0 = 1'b1; + end else begin + acc_42_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd42 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd42 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd42 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd42 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd42 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd42 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd42 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd42 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd42 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd42 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd42 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd42 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd42 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd42 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd42 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd42 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd42 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd42 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd42 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd42 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd42 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd42 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd42 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd42 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd42 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd42 == add_ln1265_reg_147629)))) begin + acc_42_V_we1 = 1'b1; + end else begin + acc_42_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_43_V_address0 = acc_43_V_addr_48_reg_163023; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_43_V_address0 = acc_43_V_addr_44_reg_162615; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_43_V_address0 = acc_43_V_addr_45_reg_158122; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_43_V_address0 = acc_43_V_addr_39_reg_157701; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_43_V_address0 = acc_43_V_addr_46_reg_153182; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_43_V_address0 = acc_43_V_addr_40_reg_152774; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_43_V_address0 = acc_43_V_addr_41_reg_148281; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_43_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_43_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_43_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_43_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_43_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_43_V_address1 = acc_43_V_addr_48_reg_163023; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_43_V_address1 = acc_43_V_addr_44_reg_162615; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_43_V_address1 = acc_43_V_addr_45_reg_158122; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_43_V_address1 = acc_43_V_addr_39_reg_157701; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_43_V_address1 = acc_43_V_addr_46_reg_153182; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_43_V_address1 = acc_43_V_addr_40_reg_152774; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_43_V_address1 = acc_43_V_addr_41_reg_148281; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_43_V_address1 = acc_43_V_addr_37_reg_147870; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd1; + end else begin + acc_43_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_43_V_ce0 = 1'b1; + end else begin + acc_43_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_43_V_ce1 = 1'b1; + end else begin + acc_43_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_43_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_43_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_43_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_43_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_43_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_43_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd43 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd43 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd43 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd43 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd43 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd43 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd43 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd43 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd43 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd43 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd43 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd43 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd43 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd43 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd43 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd43 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd43 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd43 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd43 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd43 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd43 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd43 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd43 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd43 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd43 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd43 == add_ln203_7_fu_116022_p2)))) begin + acc_43_V_we0 = 1'b1; + end else begin + acc_43_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd43 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd43 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd43 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd43 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd43 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd43 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd43 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd43 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd43 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd43 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd43 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd43 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd43 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd43 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd43 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd43 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd43 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd43 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd43 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd43 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd43 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd43 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd43 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd43 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd43 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd43 == add_ln1265_reg_147629)))) begin + acc_43_V_we1 = 1'b1; + end else begin + acc_43_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_44_V_address0 = acc_44_V_addr_49_reg_163029; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_44_V_address0 = acc_44_V_addr_44_reg_162621; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_44_V_address0 = acc_44_V_addr_45_reg_158128; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_44_V_address0 = acc_44_V_addr_39_reg_157707; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_44_V_address0 = acc_44_V_addr_46_reg_153188; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_44_V_address0 = acc_44_V_addr_40_reg_152780; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_44_V_address0 = acc_44_V_addr_41_reg_148287; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_44_V_address0 = acc_44_V_addr_37_reg_147875; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2544 == ap_CS_fsm)) begin + acc_44_V_address0 = acc_44_V_addr_52_reg_146878; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_44_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2509 == ap_CS_fsm)) begin + acc_44_V_address0 = acc_44_V_addr_50_reg_146656; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_44_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2473 == ap_CS_fsm)) begin + acc_44_V_address0 = acc_44_V_addr_51_reg_146407; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_44_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2438 == ap_CS_fsm)) begin + acc_44_V_address0 = acc_44_V_addr_48_reg_146185; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_44_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_44_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_44_V_address1 = acc_44_V_addr_49_reg_163029; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_44_V_address1 = acc_44_V_addr_44_reg_162621; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_44_V_address1 = acc_44_V_addr_45_reg_158128; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_44_V_address1 = acc_44_V_addr_39_reg_157707; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_44_V_address1 = acc_44_V_addr_46_reg_153188; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_44_V_address1 = acc_44_V_addr_40_reg_152780; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_44_V_address1 = acc_44_V_addr_41_reg_148287; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_44_V_address1 = acc_44_V_addr_37_reg_147875; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd1; + end else begin + acc_44_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2544 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2509 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2473 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2438 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_44_V_ce0 = 1'b1; + end else begin + acc_44_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_44_V_ce1 = 1'b1; + end else begin + acc_44_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2544 == ap_CS_fsm)) begin + acc_44_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_44_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2509 == ap_CS_fsm)) begin + acc_44_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_44_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2473 == ap_CS_fsm)) begin + acc_44_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_44_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2438 == ap_CS_fsm)) begin + acc_44_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_44_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_44_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_44_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2544 == ap_CS_fsm) | (ap_ST_fsm_state2509 == ap_CS_fsm) | (ap_ST_fsm_state2473 == ap_CS_fsm) | (ap_ST_fsm_state2438 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd44 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd44 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd44 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd44 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd44 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd44 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd44 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd44 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd44 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd44 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd44 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd44 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd44 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd44 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd44 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd44 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd44 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd44 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd44 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd44 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd44 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd44 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd44 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd44 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd44 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd44 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_44_V_we0 = 1'b1; + end else begin + acc_44_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd44 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd44 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd44 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd44 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd44 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd44 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd44 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd44 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd44 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd44 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd44 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd44 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd44 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd44 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd44 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd44 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd44 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd44 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd44 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd44 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd44 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd44 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd44 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd44 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd44 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd44 == add_ln1265_reg_147629)))) begin + acc_44_V_we1 = 1'b1; + end else begin + acc_44_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_45_V_address0 = acc_45_V_addr_48_reg_163035; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_45_V_address0 = acc_45_V_addr_44_reg_162627; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_45_V_address0 = acc_45_V_addr_45_reg_158134; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_45_V_address0 = acc_45_V_addr_39_reg_157713; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_45_V_address0 = acc_45_V_addr_46_reg_153194; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_45_V_address0 = acc_45_V_addr_40_reg_152786; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_45_V_address0 = acc_45_V_addr_41_reg_148293; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_45_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_45_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_45_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_45_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_45_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_45_V_address1 = acc_45_V_addr_48_reg_163035; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_45_V_address1 = acc_45_V_addr_44_reg_162627; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_45_V_address1 = acc_45_V_addr_45_reg_158134; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_45_V_address1 = acc_45_V_addr_39_reg_157713; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_45_V_address1 = acc_45_V_addr_46_reg_153194; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_45_V_address1 = acc_45_V_addr_40_reg_152786; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_45_V_address1 = acc_45_V_addr_41_reg_148293; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_45_V_address1 = acc_45_V_addr_37_reg_147881; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd1; + end else begin + acc_45_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_45_V_ce0 = 1'b1; + end else begin + acc_45_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_45_V_ce1 = 1'b1; + end else begin + acc_45_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_45_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_45_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_45_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_45_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_45_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_45_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd45 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd45 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd45 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd45 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd45 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd45 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd45 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd45 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd45 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd45 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd45 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd45 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd45 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd45 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd45 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd45 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd45 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd45 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd45 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd45 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd45 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd45 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd45 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd45 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd45 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd45 == add_ln203_7_fu_116022_p2)))) begin + acc_45_V_we0 = 1'b1; + end else begin + acc_45_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd45 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd45 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd45 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd45 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd45 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd45 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd45 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd45 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd45 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd45 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd45 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd45 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd45 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd45 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd45 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd45 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd45 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd45 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd45 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd45 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd45 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd45 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd45 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd45 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd45 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd45 == add_ln1265_reg_147629)))) begin + acc_45_V_we1 = 1'b1; + end else begin + acc_45_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_46_V_address0 = acc_46_V_addr_49_reg_163041; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_46_V_address0 = acc_46_V_addr_44_reg_162633; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_46_V_address0 = acc_46_V_addr_45_reg_158140; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_46_V_address0 = acc_46_V_addr_39_reg_157719; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_46_V_address0 = acc_46_V_addr_46_reg_153200; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_46_V_address0 = acc_46_V_addr_40_reg_152792; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_46_V_address0 = acc_46_V_addr_41_reg_148299; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_46_V_address0 = acc_46_V_addr_37_reg_147886; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2543 == ap_CS_fsm)) begin + acc_46_V_address0 = acc_46_V_addr_52_reg_146883; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_46_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2508 == ap_CS_fsm)) begin + acc_46_V_address0 = acc_46_V_addr_50_reg_146661; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_46_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2472 == ap_CS_fsm)) begin + acc_46_V_address0 = acc_46_V_addr_51_reg_146412; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_46_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2437 == ap_CS_fsm)) begin + acc_46_V_address0 = acc_46_V_addr_48_reg_146190; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_46_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_46_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_46_V_address1 = acc_46_V_addr_49_reg_163041; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_46_V_address1 = acc_46_V_addr_44_reg_162633; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_46_V_address1 = acc_46_V_addr_45_reg_158140; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_46_V_address1 = acc_46_V_addr_39_reg_157719; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_46_V_address1 = acc_46_V_addr_46_reg_153200; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_46_V_address1 = acc_46_V_addr_40_reg_152792; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_46_V_address1 = acc_46_V_addr_41_reg_148299; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_46_V_address1 = acc_46_V_addr_37_reg_147886; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd1; + end else begin + acc_46_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2543 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2508 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2472 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2437 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_46_V_ce0 = 1'b1; + end else begin + acc_46_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_46_V_ce1 = 1'b1; + end else begin + acc_46_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2543 == ap_CS_fsm)) begin + acc_46_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_46_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2508 == ap_CS_fsm)) begin + acc_46_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_46_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2472 == ap_CS_fsm)) begin + acc_46_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_46_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2437 == ap_CS_fsm)) begin + acc_46_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_46_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_46_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_46_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2543 == ap_CS_fsm) | (ap_ST_fsm_state2508 == ap_CS_fsm) | (ap_ST_fsm_state2472 == ap_CS_fsm) | (ap_ST_fsm_state2437 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd46 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd46 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd46 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd46 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd46 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd46 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd46 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd46 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd46 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd46 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd46 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd46 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd46 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd46 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd46 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd46 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd46 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd46 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd46 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd46 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd46 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd46 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd46 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd46 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd46 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd46 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_46_V_we0 = 1'b1; + end else begin + acc_46_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd46 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd46 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd46 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd46 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd46 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd46 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd46 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd46 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd46 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd46 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd46 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd46 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd46 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd46 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd46 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd46 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd46 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd46 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd46 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd46 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd46 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd46 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd46 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd46 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd46 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd46 == add_ln1265_reg_147629)))) begin + acc_46_V_we1 = 1'b1; + end else begin + acc_46_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_47_V_address0 = acc_47_V_addr_48_reg_163047; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_47_V_address0 = acc_47_V_addr_44_reg_162639; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_47_V_address0 = acc_47_V_addr_45_reg_158146; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_47_V_address0 = acc_47_V_addr_39_reg_157725; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_47_V_address0 = acc_47_V_addr_46_reg_153206; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_47_V_address0 = acc_47_V_addr_40_reg_152798; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_47_V_address0 = acc_47_V_addr_41_reg_148305; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_47_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_47_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_47_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_47_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_47_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_47_V_address1 = acc_47_V_addr_48_reg_163047; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_47_V_address1 = acc_47_V_addr_44_reg_162639; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_47_V_address1 = acc_47_V_addr_45_reg_158146; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_47_V_address1 = acc_47_V_addr_39_reg_157725; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_47_V_address1 = acc_47_V_addr_46_reg_153206; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_47_V_address1 = acc_47_V_addr_40_reg_152798; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_47_V_address1 = acc_47_V_addr_41_reg_148305; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_47_V_address1 = acc_47_V_addr_37_reg_147892; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd1; + end else begin + acc_47_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_47_V_ce0 = 1'b1; + end else begin + acc_47_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_47_V_ce1 = 1'b1; + end else begin + acc_47_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_47_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_47_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_47_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_47_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_47_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_47_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd47 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd47 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd47 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd47 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd47 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd47 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd47 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd47 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd47 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd47 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd47 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd47 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd47 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd47 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd47 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd47 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd47 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd47 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd47 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd47 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd47 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd47 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd47 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd47 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd47 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd47 == add_ln203_7_fu_116022_p2)))) begin + acc_47_V_we0 = 1'b1; + end else begin + acc_47_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd47 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd47 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd47 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd47 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd47 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd47 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd47 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd47 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd47 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd47 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd47 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd47 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd47 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd47 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd47 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd47 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd47 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd47 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd47 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd47 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd47 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd47 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd47 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd47 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd47 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd47 == add_ln1265_reg_147629)))) begin + acc_47_V_we1 = 1'b1; + end else begin + acc_47_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_48_V_address0 = acc_48_V_addr_48_reg_163053; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_48_V_address0 = acc_48_V_addr_43_reg_162645; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_48_V_address0 = acc_48_V_addr_44_reg_158152; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_48_V_address0 = acc_48_V_addr_38_reg_157731; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_48_V_address0 = acc_48_V_addr_45_reg_153212; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_48_V_address0 = acc_48_V_addr_39_reg_152804; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_48_V_address0 = acc_48_V_addr_40_reg_148311; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_48_V_address0 = acc_48_V_addr_36_reg_147897; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2542 == ap_CS_fsm)) begin + acc_48_V_address0 = acc_48_V_addr_51_reg_146888; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_48_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2507 == ap_CS_fsm)) begin + acc_48_V_address0 = acc_48_V_addr_49_reg_146666; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_48_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2471 == ap_CS_fsm)) begin + acc_48_V_address0 = acc_48_V_addr_50_reg_146417; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_48_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2436 == ap_CS_fsm)) begin + acc_48_V_address0 = acc_48_V_addr_47_reg_146195; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_48_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_48_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_48_V_address1 = acc_48_V_addr_48_reg_163053; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_48_V_address1 = acc_48_V_addr_43_reg_162645; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_48_V_address1 = acc_48_V_addr_44_reg_158152; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_48_V_address1 = acc_48_V_addr_38_reg_157731; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_48_V_address1 = acc_48_V_addr_45_reg_153212; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_48_V_address1 = acc_48_V_addr_39_reg_152804; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_48_V_address1 = acc_48_V_addr_40_reg_148311; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_48_V_address1 = acc_48_V_addr_36_reg_147897; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd1; + end else begin + acc_48_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2542 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2507 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2471 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2436 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_48_V_ce0 = 1'b1; + end else begin + acc_48_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_48_V_ce1 = 1'b1; + end else begin + acc_48_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2542 == ap_CS_fsm)) begin + acc_48_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_48_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2507 == ap_CS_fsm)) begin + acc_48_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_48_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2471 == ap_CS_fsm)) begin + acc_48_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_48_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2436 == ap_CS_fsm)) begin + acc_48_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_48_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_48_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_48_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2542 == ap_CS_fsm) | (ap_ST_fsm_state2507 == ap_CS_fsm) | (ap_ST_fsm_state2471 == ap_CS_fsm) | (ap_ST_fsm_state2436 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd48 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd48 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd48 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd48 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd48 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd48 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd48 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd48 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd48 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd48 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd48 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd48 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd48 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd48 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd48 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd48 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd48 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd48 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd48 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd48 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd48 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd48 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd48 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd48 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd48 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd48 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_48_V_we0 = 1'b1; + end else begin + acc_48_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd48 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd48 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd48 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd48 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd48 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd48 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd48 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd48 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd48 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd48 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd48 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd48 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd48 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd48 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd48 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd48 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd48 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd48 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd48 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd48 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd48 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd48 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd48 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd48 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd48 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd48 == add_ln1265_reg_147629)))) begin + acc_48_V_we1 = 1'b1; + end else begin + acc_48_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_49_V_address0 = acc_49_V_addr_47_reg_163059; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_49_V_address0 = acc_49_V_addr_43_reg_162651; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_49_V_address0 = acc_49_V_addr_44_reg_158158; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_49_V_address0 = acc_49_V_addr_38_reg_157737; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_49_V_address0 = acc_49_V_addr_45_reg_153218; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_49_V_address0 = acc_49_V_addr_39_reg_152810; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_49_V_address0 = acc_49_V_addr_40_reg_148317; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_49_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_49_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_49_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_49_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_49_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_49_V_address1 = acc_49_V_addr_47_reg_163059; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_49_V_address1 = acc_49_V_addr_43_reg_162651; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_49_V_address1 = acc_49_V_addr_44_reg_158158; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_49_V_address1 = acc_49_V_addr_38_reg_157737; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_49_V_address1 = acc_49_V_addr_45_reg_153218; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_49_V_address1 = acc_49_V_addr_39_reg_152810; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_49_V_address1 = acc_49_V_addr_40_reg_148317; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_49_V_address1 = acc_49_V_addr_36_reg_147903; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd1; + end else begin + acc_49_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_49_V_ce0 = 1'b1; + end else begin + acc_49_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_49_V_ce1 = 1'b1; + end else begin + acc_49_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_49_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_49_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_49_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_49_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_49_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_49_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd49 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd49 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd49 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd49 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd49 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd49 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd49 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd49 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd49 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd49 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd49 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd49 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd49 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd49 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd49 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd49 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd49 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd49 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd49 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd49 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd49 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd49 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd49 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd49 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd49 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd49 == add_ln203_7_fu_116022_p2)))) begin + acc_49_V_we0 = 1'b1; + end else begin + acc_49_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd49 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd49 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd49 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd49 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd49 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd49 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd49 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd49 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd49 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd49 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd49 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd49 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd49 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd49 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd49 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd49 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd49 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd49 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd49 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd49 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd49 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd49 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd49 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd49 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd49 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd49 == add_ln1265_reg_147629)))) begin + acc_49_V_we1 = 1'b1; + end else begin + acc_49_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_4_V_address0 = acc_4_V_addr_49_reg_162789; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_4_V_address0 = acc_4_V_addr_44_reg_162381; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_4_V_address0 = acc_4_V_addr_45_reg_157888; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_4_V_address0 = acc_4_V_addr_39_reg_157467; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_4_V_address0 = acc_4_V_addr_46_reg_152948; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_4_V_address0 = acc_4_V_addr_40_reg_152540; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_4_V_address0 = acc_4_V_addr_41_reg_148047; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_4_V_address0 = acc_4_V_addr_37_reg_147655; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2564 == ap_CS_fsm)) begin + acc_4_V_address0 = acc_4_V_addr_52_reg_146778; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_4_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2529 == ap_CS_fsm)) begin + acc_4_V_address0 = acc_4_V_addr_50_reg_146556; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_4_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2493 == ap_CS_fsm)) begin + acc_4_V_address0 = acc_4_V_addr_51_reg_146307; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_4_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2458 == ap_CS_fsm)) begin + acc_4_V_address0 = acc_4_V_addr_48_reg_146085; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_4_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_4_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_4_V_address1 = acc_4_V_addr_49_reg_162789; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_4_V_address1 = acc_4_V_addr_44_reg_162381; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_4_V_address1 = acc_4_V_addr_45_reg_157888; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_4_V_address1 = acc_4_V_addr_39_reg_157467; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_4_V_address1 = acc_4_V_addr_46_reg_152948; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_4_V_address1 = acc_4_V_addr_40_reg_152540; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_4_V_address1 = acc_4_V_addr_41_reg_148047; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_4_V_address1 = acc_4_V_addr_37_reg_147655; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd1; + end else begin + acc_4_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2564 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2529 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2493 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2458 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_4_V_ce0 = 1'b1; + end else begin + acc_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_4_V_ce1 = 1'b1; + end else begin + acc_4_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2564 == ap_CS_fsm)) begin + acc_4_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_4_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2529 == ap_CS_fsm)) begin + acc_4_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_4_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2493 == ap_CS_fsm)) begin + acc_4_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_4_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2458 == ap_CS_fsm)) begin + acc_4_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_4_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_4_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_4_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2564 == ap_CS_fsm) | (ap_ST_fsm_state2529 == ap_CS_fsm) | (ap_ST_fsm_state2493 == ap_CS_fsm) | (ap_ST_fsm_state2458 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd4 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd4 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd4 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd4 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd4 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd4 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd4 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd4 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd4 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd4 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd4 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd4 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd4 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd4 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd4 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd4 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd4 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd4 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd4 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd4 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd4 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd4 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd4 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd4 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd4 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd4 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_4_V_we0 = 1'b1; + end else begin + acc_4_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd4 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd4 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd4 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd4 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd4 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd4 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd4 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd4 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd4 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd4 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd4 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd4 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd4 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd4 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd4 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd4 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd4 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd4 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd4 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd4 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd4 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd4 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd4 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd4 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd4 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd4 == add_ln1265_reg_147629)))) begin + acc_4_V_we1 = 1'b1; + end else begin + acc_4_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_50_V_address0 = acc_50_V_addr_48_reg_163065; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_50_V_address0 = acc_50_V_addr_43_reg_162657; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_50_V_address0 = acc_50_V_addr_44_reg_158164; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_50_V_address0 = acc_50_V_addr_38_reg_157743; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_50_V_address0 = acc_50_V_addr_45_reg_153224; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_50_V_address0 = acc_50_V_addr_39_reg_152816; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_50_V_address0 = acc_50_V_addr_40_reg_148323; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_50_V_address0 = acc_50_V_addr_36_reg_147908; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2541 == ap_CS_fsm)) begin + acc_50_V_address0 = acc_50_V_addr_51_reg_146893; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_50_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2506 == ap_CS_fsm)) begin + acc_50_V_address0 = acc_50_V_addr_49_reg_146671; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_50_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2470 == ap_CS_fsm)) begin + acc_50_V_address0 = acc_50_V_addr_50_reg_146422; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_50_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2435 == ap_CS_fsm)) begin + acc_50_V_address0 = acc_50_V_addr_47_reg_146200; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_50_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_50_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_50_V_address1 = acc_50_V_addr_48_reg_163065; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_50_V_address1 = acc_50_V_addr_43_reg_162657; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_50_V_address1 = acc_50_V_addr_44_reg_158164; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_50_V_address1 = acc_50_V_addr_38_reg_157743; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_50_V_address1 = acc_50_V_addr_45_reg_153224; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_50_V_address1 = acc_50_V_addr_39_reg_152816; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_50_V_address1 = acc_50_V_addr_40_reg_148323; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_50_V_address1 = acc_50_V_addr_36_reg_147908; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd1; + end else begin + acc_50_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2541 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2506 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2470 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2435 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_50_V_ce0 = 1'b1; + end else begin + acc_50_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_50_V_ce1 = 1'b1; + end else begin + acc_50_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2541 == ap_CS_fsm)) begin + acc_50_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_50_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2506 == ap_CS_fsm)) begin + acc_50_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_50_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2470 == ap_CS_fsm)) begin + acc_50_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_50_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2435 == ap_CS_fsm)) begin + acc_50_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_50_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_50_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_50_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2541 == ap_CS_fsm) | (ap_ST_fsm_state2506 == ap_CS_fsm) | (ap_ST_fsm_state2470 == ap_CS_fsm) | (ap_ST_fsm_state2435 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd50 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd50 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd50 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd50 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd50 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd50 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd50 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd50 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd50 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd50 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd50 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd50 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd50 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd50 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd50 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd50 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd50 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd50 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd50 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd50 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd50 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd50 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd50 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd50 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd50 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd50 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_50_V_we0 = 1'b1; + end else begin + acc_50_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd50 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd50 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd50 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd50 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd50 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd50 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd50 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd50 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd50 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd50 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd50 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd50 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd50 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd50 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd50 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd50 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd50 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd50 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd50 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd50 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd50 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd50 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd50 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd50 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd50 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd50 == add_ln1265_reg_147629)))) begin + acc_50_V_we1 = 1'b1; + end else begin + acc_50_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_51_V_address0 = acc_51_V_addr_47_reg_163071; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_51_V_address0 = acc_51_V_addr_43_reg_162663; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_51_V_address0 = acc_51_V_addr_44_reg_158170; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_51_V_address0 = acc_51_V_addr_38_reg_157749; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_51_V_address0 = acc_51_V_addr_45_reg_153230; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_51_V_address0 = acc_51_V_addr_39_reg_152822; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_51_V_address0 = acc_51_V_addr_40_reg_148329; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_51_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_51_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_51_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_51_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_51_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_51_V_address1 = acc_51_V_addr_47_reg_163071; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_51_V_address1 = acc_51_V_addr_43_reg_162663; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_51_V_address1 = acc_51_V_addr_44_reg_158170; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_51_V_address1 = acc_51_V_addr_38_reg_157749; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_51_V_address1 = acc_51_V_addr_45_reg_153230; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_51_V_address1 = acc_51_V_addr_39_reg_152822; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_51_V_address1 = acc_51_V_addr_40_reg_148329; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_51_V_address1 = acc_51_V_addr_36_reg_147914; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd1; + end else begin + acc_51_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_51_V_ce0 = 1'b1; + end else begin + acc_51_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_51_V_ce1 = 1'b1; + end else begin + acc_51_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_51_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_51_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_51_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_51_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_51_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_51_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd51 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd51 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd51 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd51 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd51 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd51 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd51 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd51 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd51 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd51 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd51 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd51 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd51 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd51 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd51 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd51 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd51 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd51 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd51 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd51 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd51 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd51 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd51 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd51 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd51 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd51 == add_ln203_7_fu_116022_p2)))) begin + acc_51_V_we0 = 1'b1; + end else begin + acc_51_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd51 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd51 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd51 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd51 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd51 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd51 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd51 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd51 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd51 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd51 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd51 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd51 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd51 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd51 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd51 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd51 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd51 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd51 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd51 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd51 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd51 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd51 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd51 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd51 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd51 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd51 == add_ln1265_reg_147629)))) begin + acc_51_V_we1 = 1'b1; + end else begin + acc_51_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_52_V_address0 = acc_52_V_addr_48_reg_163077; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_52_V_address0 = acc_52_V_addr_43_reg_162669; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_52_V_address0 = acc_52_V_addr_44_reg_158176; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_52_V_address0 = acc_52_V_addr_38_reg_157755; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_52_V_address0 = acc_52_V_addr_45_reg_153236; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_52_V_address0 = acc_52_V_addr_39_reg_152828; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_52_V_address0 = acc_52_V_addr_40_reg_148335; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_52_V_address0 = acc_52_V_addr_36_reg_147919; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2540 == ap_CS_fsm)) begin + acc_52_V_address0 = acc_52_V_addr_51_reg_146898; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_52_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2505 == ap_CS_fsm)) begin + acc_52_V_address0 = acc_52_V_addr_49_reg_146676; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_52_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2469 == ap_CS_fsm)) begin + acc_52_V_address0 = acc_52_V_addr_50_reg_146427; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_52_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2434 == ap_CS_fsm)) begin + acc_52_V_address0 = acc_52_V_addr_47_reg_146205; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_52_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_52_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_52_V_address1 = acc_52_V_addr_48_reg_163077; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_52_V_address1 = acc_52_V_addr_43_reg_162669; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_52_V_address1 = acc_52_V_addr_44_reg_158176; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_52_V_address1 = acc_52_V_addr_38_reg_157755; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_52_V_address1 = acc_52_V_addr_45_reg_153236; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_52_V_address1 = acc_52_V_addr_39_reg_152828; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_52_V_address1 = acc_52_V_addr_40_reg_148335; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_52_V_address1 = acc_52_V_addr_36_reg_147919; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd1; + end else begin + acc_52_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2540 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2505 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2469 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2434 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_52_V_ce0 = 1'b1; + end else begin + acc_52_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_52_V_ce1 = 1'b1; + end else begin + acc_52_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2540 == ap_CS_fsm)) begin + acc_52_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_52_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2505 == ap_CS_fsm)) begin + acc_52_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_52_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2469 == ap_CS_fsm)) begin + acc_52_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_52_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2434 == ap_CS_fsm)) begin + acc_52_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_52_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_52_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_52_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2540 == ap_CS_fsm) | (ap_ST_fsm_state2505 == ap_CS_fsm) | (ap_ST_fsm_state2469 == ap_CS_fsm) | (ap_ST_fsm_state2434 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd52 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd52 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd52 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd52 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd52 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd52 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd52 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd52 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd52 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd52 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd52 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd52 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd52 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd52 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd52 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd52 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd52 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd52 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd52 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd52 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd52 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd52 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd52 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd52 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd52 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd52 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_52_V_we0 = 1'b1; + end else begin + acc_52_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd52 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd52 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd52 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd52 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd52 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd52 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd52 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd52 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd52 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd52 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd52 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd52 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd52 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd52 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd52 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd52 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd52 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd52 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd52 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd52 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd52 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd52 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd52 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd52 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd52 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd52 == add_ln1265_reg_147629)))) begin + acc_52_V_we1 = 1'b1; + end else begin + acc_52_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_53_V_address0 = acc_53_V_addr_47_reg_163083; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_53_V_address0 = acc_53_V_addr_43_reg_162675; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_53_V_address0 = acc_53_V_addr_44_reg_158182; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_53_V_address0 = acc_53_V_addr_38_reg_157761; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_53_V_address0 = acc_53_V_addr_45_reg_153242; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_53_V_address0 = acc_53_V_addr_39_reg_152834; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_53_V_address0 = acc_53_V_addr_40_reg_148341; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_53_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_53_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_53_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_53_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_53_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_53_V_address1 = acc_53_V_addr_47_reg_163083; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_53_V_address1 = acc_53_V_addr_43_reg_162675; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_53_V_address1 = acc_53_V_addr_44_reg_158182; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_53_V_address1 = acc_53_V_addr_38_reg_157761; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_53_V_address1 = acc_53_V_addr_45_reg_153242; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_53_V_address1 = acc_53_V_addr_39_reg_152834; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_53_V_address1 = acc_53_V_addr_40_reg_148341; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_53_V_address1 = acc_53_V_addr_36_reg_147925; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd1; + end else begin + acc_53_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_53_V_ce0 = 1'b1; + end else begin + acc_53_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_53_V_ce1 = 1'b1; + end else begin + acc_53_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_53_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_53_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_53_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_53_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_53_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_53_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd53 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd53 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd53 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd53 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd53 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd53 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd53 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd53 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd53 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd53 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd53 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd53 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd53 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd53 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd53 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd53 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd53 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd53 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd53 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd53 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd53 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd53 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd53 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd53 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd53 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd53 == add_ln203_7_fu_116022_p2)))) begin + acc_53_V_we0 = 1'b1; + end else begin + acc_53_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd53 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd53 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd53 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd53 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd53 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd53 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd53 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd53 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd53 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd53 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd53 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd53 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd53 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd53 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd53 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd53 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd53 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd53 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd53 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd53 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd53 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd53 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd53 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd53 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd53 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd53 == add_ln1265_reg_147629)))) begin + acc_53_V_we1 = 1'b1; + end else begin + acc_53_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_54_V_address0 = acc_54_V_addr_48_reg_163089; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_54_V_address0 = acc_54_V_addr_43_reg_162681; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_54_V_address0 = acc_54_V_addr_44_reg_158188; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_54_V_address0 = acc_54_V_addr_38_reg_157767; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_54_V_address0 = acc_54_V_addr_45_reg_153248; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_54_V_address0 = acc_54_V_addr_39_reg_152840; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_54_V_address0 = acc_54_V_addr_40_reg_148347; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_54_V_address0 = acc_54_V_addr_36_reg_147930; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2539 == ap_CS_fsm)) begin + acc_54_V_address0 = acc_54_V_addr_51_reg_146903; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_54_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2504 == ap_CS_fsm)) begin + acc_54_V_address0 = acc_54_V_addr_49_reg_146681; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_54_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2468 == ap_CS_fsm)) begin + acc_54_V_address0 = acc_54_V_addr_50_reg_146432; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_54_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2433 == ap_CS_fsm)) begin + acc_54_V_address0 = acc_54_V_addr_47_reg_146210; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_54_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_54_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_54_V_address1 = acc_54_V_addr_48_reg_163089; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_54_V_address1 = acc_54_V_addr_43_reg_162681; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_54_V_address1 = acc_54_V_addr_44_reg_158188; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_54_V_address1 = acc_54_V_addr_38_reg_157767; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_54_V_address1 = acc_54_V_addr_45_reg_153248; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_54_V_address1 = acc_54_V_addr_39_reg_152840; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_54_V_address1 = acc_54_V_addr_40_reg_148347; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_54_V_address1 = acc_54_V_addr_36_reg_147930; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd1; + end else begin + acc_54_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2539 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2504 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2468 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2433 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_54_V_ce0 = 1'b1; + end else begin + acc_54_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_54_V_ce1 = 1'b1; + end else begin + acc_54_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2539 == ap_CS_fsm)) begin + acc_54_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_54_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2504 == ap_CS_fsm)) begin + acc_54_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_54_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2468 == ap_CS_fsm)) begin + acc_54_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_54_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2433 == ap_CS_fsm)) begin + acc_54_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_54_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_54_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_54_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2539 == ap_CS_fsm) | (ap_ST_fsm_state2504 == ap_CS_fsm) | (ap_ST_fsm_state2468 == ap_CS_fsm) | (ap_ST_fsm_state2433 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd54 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd54 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd54 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd54 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd54 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd54 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd54 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd54 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd54 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd54 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd54 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd54 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd54 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd54 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd54 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd54 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd54 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd54 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd54 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd54 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd54 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd54 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd54 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd54 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd54 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd54 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_54_V_we0 = 1'b1; + end else begin + acc_54_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd54 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd54 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd54 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd54 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd54 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd54 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd54 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd54 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd54 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd54 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd54 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd54 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd54 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd54 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd54 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd54 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd54 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd54 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd54 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd54 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd54 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd54 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd54 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd54 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd54 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd54 == add_ln1265_reg_147629)))) begin + acc_54_V_we1 = 1'b1; + end else begin + acc_54_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_55_V_address0 = acc_55_V_addr_47_reg_163095; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_55_V_address0 = acc_55_V_addr_43_reg_162687; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_55_V_address0 = acc_55_V_addr_44_reg_158194; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_55_V_address0 = acc_55_V_addr_38_reg_157773; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_55_V_address0 = acc_55_V_addr_45_reg_153254; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_55_V_address0 = acc_55_V_addr_39_reg_152846; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_55_V_address0 = acc_55_V_addr_40_reg_148353; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_55_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_55_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_55_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_55_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_55_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_55_V_address1 = acc_55_V_addr_47_reg_163095; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_55_V_address1 = acc_55_V_addr_43_reg_162687; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_55_V_address1 = acc_55_V_addr_44_reg_158194; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_55_V_address1 = acc_55_V_addr_38_reg_157773; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_55_V_address1 = acc_55_V_addr_45_reg_153254; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_55_V_address1 = acc_55_V_addr_39_reg_152846; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_55_V_address1 = acc_55_V_addr_40_reg_148353; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_55_V_address1 = acc_55_V_addr_36_reg_147936; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd1; + end else begin + acc_55_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_55_V_ce0 = 1'b1; + end else begin + acc_55_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_55_V_ce1 = 1'b1; + end else begin + acc_55_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_55_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_55_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_55_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_55_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_55_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_55_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd55 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd55 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd55 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd55 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd55 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd55 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd55 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd55 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd55 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd55 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd55 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd55 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd55 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd55 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd55 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd55 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd55 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd55 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd55 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd55 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd55 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd55 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd55 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd55 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd55 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd55 == add_ln203_7_fu_116022_p2)))) begin + acc_55_V_we0 = 1'b1; + end else begin + acc_55_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd55 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd55 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd55 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd55 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd55 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd55 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd55 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd55 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd55 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd55 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd55 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd55 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd55 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd55 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd55 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd55 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd55 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd55 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd55 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd55 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd55 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd55 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd55 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd55 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd55 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd55 == add_ln1265_reg_147629)))) begin + acc_55_V_we1 = 1'b1; + end else begin + acc_55_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_56_V_address0 = acc_56_V_addr_48_reg_163101; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_56_V_address0 = acc_56_V_addr_43_reg_162693; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_56_V_address0 = acc_56_V_addr_44_reg_158200; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_56_V_address0 = acc_56_V_addr_38_reg_157779; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_56_V_address0 = acc_56_V_addr_45_reg_153260; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_56_V_address0 = acc_56_V_addr_39_reg_152852; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_56_V_address0 = acc_56_V_addr_40_reg_148359; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_56_V_address0 = acc_56_V_addr_36_reg_147941; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2538 == ap_CS_fsm)) begin + acc_56_V_address0 = acc_56_V_addr_51_reg_146908; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_56_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2503 == ap_CS_fsm)) begin + acc_56_V_address0 = acc_56_V_addr_49_reg_146686; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_56_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2467 == ap_CS_fsm)) begin + acc_56_V_address0 = acc_56_V_addr_50_reg_146437; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_56_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2432 == ap_CS_fsm)) begin + acc_56_V_address0 = acc_56_V_addr_47_reg_146215; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_56_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_56_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_56_V_address1 = acc_56_V_addr_48_reg_163101; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_56_V_address1 = acc_56_V_addr_43_reg_162693; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_56_V_address1 = acc_56_V_addr_44_reg_158200; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_56_V_address1 = acc_56_V_addr_38_reg_157779; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_56_V_address1 = acc_56_V_addr_45_reg_153260; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_56_V_address1 = acc_56_V_addr_39_reg_152852; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_56_V_address1 = acc_56_V_addr_40_reg_148359; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_56_V_address1 = acc_56_V_addr_36_reg_147941; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd1; + end else begin + acc_56_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2538 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2503 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2467 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2432 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_56_V_ce0 = 1'b1; + end else begin + acc_56_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_56_V_ce1 = 1'b1; + end else begin + acc_56_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2538 == ap_CS_fsm)) begin + acc_56_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_56_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2503 == ap_CS_fsm)) begin + acc_56_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_56_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2467 == ap_CS_fsm)) begin + acc_56_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_56_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2432 == ap_CS_fsm)) begin + acc_56_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_56_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_56_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_56_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2538 == ap_CS_fsm) | (ap_ST_fsm_state2503 == ap_CS_fsm) | (ap_ST_fsm_state2467 == ap_CS_fsm) | (ap_ST_fsm_state2432 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd56 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd56 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd56 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd56 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd56 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd56 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd56 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd56 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd56 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd56 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd56 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd56 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd56 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd56 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd56 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd56 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd56 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd56 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd56 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd56 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd56 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd56 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd56 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd56 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd56 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd56 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_56_V_we0 = 1'b1; + end else begin + acc_56_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd56 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd56 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd56 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd56 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd56 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd56 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd56 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd56 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd56 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd56 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd56 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd56 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd56 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd56 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd56 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd56 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd56 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd56 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd56 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd56 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd56 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd56 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd56 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd56 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd56 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd56 == add_ln1265_reg_147629)))) begin + acc_56_V_we1 = 1'b1; + end else begin + acc_56_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_57_V_address0 = acc_57_V_addr_47_reg_163107; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_57_V_address0 = acc_57_V_addr_43_reg_162699; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_57_V_address0 = acc_57_V_addr_44_reg_158206; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_57_V_address0 = acc_57_V_addr_38_reg_157785; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_57_V_address0 = acc_57_V_addr_45_reg_153266; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_57_V_address0 = acc_57_V_addr_39_reg_152858; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_57_V_address0 = acc_57_V_addr_40_reg_148365; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_57_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_57_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_57_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_57_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_57_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_57_V_address1 = acc_57_V_addr_47_reg_163107; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_57_V_address1 = acc_57_V_addr_43_reg_162699; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_57_V_address1 = acc_57_V_addr_44_reg_158206; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_57_V_address1 = acc_57_V_addr_38_reg_157785; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_57_V_address1 = acc_57_V_addr_45_reg_153266; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_57_V_address1 = acc_57_V_addr_39_reg_152858; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_57_V_address1 = acc_57_V_addr_40_reg_148365; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_57_V_address1 = acc_57_V_addr_36_reg_147947; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd1; + end else begin + acc_57_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_57_V_ce0 = 1'b1; + end else begin + acc_57_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_57_V_ce1 = 1'b1; + end else begin + acc_57_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_57_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_57_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_57_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_57_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_57_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_57_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd57 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd57 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd57 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd57 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd57 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd57 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd57 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd57 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd57 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd57 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd57 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd57 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd57 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd57 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd57 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd57 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd57 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd57 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd57 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd57 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd57 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd57 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd57 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd57 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd57 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd57 == add_ln203_7_fu_116022_p2)))) begin + acc_57_V_we0 = 1'b1; + end else begin + acc_57_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd57 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd57 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd57 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd57 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd57 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd57 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd57 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd57 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd57 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd57 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd57 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd57 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd57 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd57 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd57 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd57 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd57 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd57 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd57 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd57 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd57 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd57 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd57 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd57 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd57 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd57 == add_ln1265_reg_147629)))) begin + acc_57_V_we1 = 1'b1; + end else begin + acc_57_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_58_V_address0 = acc_58_V_addr_48_reg_163113; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_58_V_address0 = acc_58_V_addr_43_reg_162705; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_58_V_address0 = acc_58_V_addr_44_reg_158212; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_58_V_address0 = acc_58_V_addr_38_reg_157791; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_58_V_address0 = acc_58_V_addr_45_reg_153272; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_58_V_address0 = acc_58_V_addr_39_reg_152864; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_58_V_address0 = acc_58_V_addr_40_reg_148371; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_58_V_address0 = acc_58_V_addr_36_reg_147952; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2537 == ap_CS_fsm)) begin + acc_58_V_address0 = acc_58_V_addr_51_reg_146913; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_58_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2502 == ap_CS_fsm)) begin + acc_58_V_address0 = acc_58_V_addr_49_reg_146691; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_58_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2466 == ap_CS_fsm)) begin + acc_58_V_address0 = acc_58_V_addr_50_reg_146442; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_58_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2431 == ap_CS_fsm)) begin + acc_58_V_address0 = acc_58_V_addr_47_reg_146220; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_58_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_58_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_58_V_address1 = acc_58_V_addr_48_reg_163113; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_58_V_address1 = acc_58_V_addr_43_reg_162705; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_58_V_address1 = acc_58_V_addr_44_reg_158212; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_58_V_address1 = acc_58_V_addr_38_reg_157791; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_58_V_address1 = acc_58_V_addr_45_reg_153272; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_58_V_address1 = acc_58_V_addr_39_reg_152864; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_58_V_address1 = acc_58_V_addr_40_reg_148371; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_58_V_address1 = acc_58_V_addr_36_reg_147952; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd1; + end else begin + acc_58_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2537 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2502 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2466 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2431 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_58_V_ce0 = 1'b1; + end else begin + acc_58_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_58_V_ce1 = 1'b1; + end else begin + acc_58_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2537 == ap_CS_fsm)) begin + acc_58_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_58_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2502 == ap_CS_fsm)) begin + acc_58_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_58_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2466 == ap_CS_fsm)) begin + acc_58_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_58_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2431 == ap_CS_fsm)) begin + acc_58_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_58_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_58_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_58_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2537 == ap_CS_fsm) | (ap_ST_fsm_state2502 == ap_CS_fsm) | (ap_ST_fsm_state2466 == ap_CS_fsm) | (ap_ST_fsm_state2431 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd58 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd58 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd58 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd58 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd58 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd58 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd58 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd58 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd58 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd58 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd58 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd58 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd58 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd58 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd58 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd58 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd58 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd58 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd58 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd58 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd58 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd58 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd58 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd58 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd58 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd58 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_58_V_we0 = 1'b1; + end else begin + acc_58_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd58 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd58 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd58 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd58 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd58 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd58 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd58 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd58 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd58 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd58 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd58 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd58 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd58 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd58 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd58 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd58 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd58 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd58 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd58 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd58 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd58 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd58 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd58 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd58 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd58 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd58 == add_ln1265_reg_147629)))) begin + acc_58_V_we1 = 1'b1; + end else begin + acc_58_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_59_V_address0 = acc_59_V_addr_47_reg_163119; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_59_V_address0 = acc_59_V_addr_43_reg_162711; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_59_V_address0 = acc_59_V_addr_44_reg_158218; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_59_V_address0 = acc_59_V_addr_38_reg_157797; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_59_V_address0 = acc_59_V_addr_45_reg_153278; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_59_V_address0 = acc_59_V_addr_39_reg_152870; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_59_V_address0 = acc_59_V_addr_40_reg_148377; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_59_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_59_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_59_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_59_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_59_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_59_V_address1 = acc_59_V_addr_47_reg_163119; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_59_V_address1 = acc_59_V_addr_43_reg_162711; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_59_V_address1 = acc_59_V_addr_44_reg_158218; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_59_V_address1 = acc_59_V_addr_38_reg_157797; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_59_V_address1 = acc_59_V_addr_45_reg_153278; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_59_V_address1 = acc_59_V_addr_39_reg_152870; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_59_V_address1 = acc_59_V_addr_40_reg_148377; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_59_V_address1 = acc_59_V_addr_36_reg_147958; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd1; + end else begin + acc_59_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_59_V_ce0 = 1'b1; + end else begin + acc_59_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_59_V_ce1 = 1'b1; + end else begin + acc_59_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_59_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_59_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_59_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_59_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_59_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_59_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd59 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd59 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd59 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd59 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd59 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd59 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd59 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd59 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd59 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd59 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd59 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd59 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd59 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd59 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd59 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd59 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd59 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd59 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd59 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd59 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd59 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd59 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd59 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd59 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd59 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd59 == add_ln203_7_fu_116022_p2)))) begin + acc_59_V_we0 = 1'b1; + end else begin + acc_59_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd59 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd59 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd59 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd59 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd59 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd59 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd59 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd59 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd59 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd59 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd59 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd59 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd59 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd59 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd59 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd59 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd59 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd59 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd59 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd59 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd59 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd59 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd59 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd59 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd59 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd59 == add_ln1265_reg_147629)))) begin + acc_59_V_we1 = 1'b1; + end else begin + acc_59_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_5_V_address0 = acc_5_V_addr_48_reg_162795; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_5_V_address0 = acc_5_V_addr_44_reg_162387; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_5_V_address0 = acc_5_V_addr_45_reg_157894; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_5_V_address0 = acc_5_V_addr_39_reg_157473; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_5_V_address0 = acc_5_V_addr_46_reg_152954; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_5_V_address0 = acc_5_V_addr_40_reg_152546; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_5_V_address0 = acc_5_V_addr_41_reg_148053; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_5_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_5_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_5_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_5_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_5_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_5_V_address1 = acc_5_V_addr_48_reg_162795; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_5_V_address1 = acc_5_V_addr_44_reg_162387; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_5_V_address1 = acc_5_V_addr_45_reg_157894; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_5_V_address1 = acc_5_V_addr_39_reg_157473; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_5_V_address1 = acc_5_V_addr_46_reg_152954; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_5_V_address1 = acc_5_V_addr_40_reg_152546; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_5_V_address1 = acc_5_V_addr_41_reg_148053; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_5_V_address1 = acc_5_V_addr_37_reg_147661; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd1; + end else begin + acc_5_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_5_V_ce0 = 1'b1; + end else begin + acc_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_5_V_ce1 = 1'b1; + end else begin + acc_5_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_5_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_5_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_5_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_5_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_5_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_5_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd5 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd5 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd5 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd5 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd5 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd5 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd5 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd5 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd5 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd5 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd5 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd5 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd5 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd5 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd5 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd5 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd5 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd5 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd5 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd5 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd5 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd5 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd5 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd5 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd5 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd5 == add_ln203_7_fu_116022_p2)))) begin + acc_5_V_we0 = 1'b1; + end else begin + acc_5_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd5 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd5 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd5 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd5 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd5 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd5 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd5 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd5 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd5 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd5 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd5 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd5 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd5 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd5 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd5 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd5 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd5 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd5 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd5 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd5 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd5 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd5 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd5 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd5 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd5 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd5 == add_ln1265_reg_147629)))) begin + acc_5_V_we1 = 1'b1; + end else begin + acc_5_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_60_V_address0 = acc_60_V_addr_48_reg_163125; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_60_V_address0 = acc_60_V_addr_43_reg_162717; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_60_V_address0 = acc_60_V_addr_44_reg_158224; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_60_V_address0 = acc_60_V_addr_38_reg_157803; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_60_V_address0 = acc_60_V_addr_45_reg_153284; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_60_V_address0 = acc_60_V_addr_39_reg_152876; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_60_V_address0 = acc_60_V_addr_40_reg_148383; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_60_V_address0 = acc_60_V_addr_36_reg_147963; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2536 == ap_CS_fsm)) begin + acc_60_V_address0 = acc_60_V_addr_51_reg_146918; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_60_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2501 == ap_CS_fsm)) begin + acc_60_V_address0 = acc_60_V_addr_49_reg_146696; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_60_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2465 == ap_CS_fsm)) begin + acc_60_V_address0 = acc_60_V_addr_50_reg_146447; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_60_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2430 == ap_CS_fsm)) begin + acc_60_V_address0 = acc_60_V_addr_47_reg_146225; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_60_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_60_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_60_V_address1 = acc_60_V_addr_48_reg_163125; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_60_V_address1 = acc_60_V_addr_43_reg_162717; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_60_V_address1 = acc_60_V_addr_44_reg_158224; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_60_V_address1 = acc_60_V_addr_38_reg_157803; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_60_V_address1 = acc_60_V_addr_45_reg_153284; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_60_V_address1 = acc_60_V_addr_39_reg_152876; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_60_V_address1 = acc_60_V_addr_40_reg_148383; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_60_V_address1 = acc_60_V_addr_36_reg_147963; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd1; + end else begin + acc_60_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2536 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2501 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2465 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2430 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_60_V_ce0 = 1'b1; + end else begin + acc_60_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_60_V_ce1 = 1'b1; + end else begin + acc_60_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2536 == ap_CS_fsm)) begin + acc_60_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_60_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2501 == ap_CS_fsm)) begin + acc_60_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_60_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2465 == ap_CS_fsm)) begin + acc_60_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_60_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2430 == ap_CS_fsm)) begin + acc_60_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_60_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_60_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_60_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2536 == ap_CS_fsm) | (ap_ST_fsm_state2501 == ap_CS_fsm) | (ap_ST_fsm_state2465 == ap_CS_fsm) | (ap_ST_fsm_state2430 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd60 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd60 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd60 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd60 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd60 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd60 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd60 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd60 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd60 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd60 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd60 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd60 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd60 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd60 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd60 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd60 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd60 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd60 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd60 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd60 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd60 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd60 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd60 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd60 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd60 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd60 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_60_V_we0 = 1'b1; + end else begin + acc_60_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd60 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd60 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd60 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd60 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd60 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd60 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd60 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd60 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd60 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd60 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd60 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd60 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd60 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd60 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd60 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd60 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd60 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd60 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd60 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd60 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd60 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd60 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd60 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd60 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd60 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd60 == add_ln1265_reg_147629)))) begin + acc_60_V_we1 = 1'b1; + end else begin + acc_60_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_61_V_address0 = acc_61_V_addr_47_reg_163131; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_61_V_address0 = acc_61_V_addr_43_reg_162723; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_61_V_address0 = acc_61_V_addr_44_reg_158230; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_61_V_address0 = acc_61_V_addr_38_reg_157809; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_61_V_address0 = acc_61_V_addr_45_reg_153290; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_61_V_address0 = acc_61_V_addr_39_reg_152882; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_61_V_address0 = acc_61_V_addr_40_reg_148389; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_61_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_61_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_61_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_61_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_61_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_61_V_address1 = acc_61_V_addr_47_reg_163131; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_61_V_address1 = acc_61_V_addr_43_reg_162723; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_61_V_address1 = acc_61_V_addr_44_reg_158230; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_61_V_address1 = acc_61_V_addr_38_reg_157809; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_61_V_address1 = acc_61_V_addr_45_reg_153290; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_61_V_address1 = acc_61_V_addr_39_reg_152882; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_61_V_address1 = acc_61_V_addr_40_reg_148389; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_61_V_address1 = acc_61_V_addr_36_reg_147969; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd1; + end else begin + acc_61_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_61_V_ce0 = 1'b1; + end else begin + acc_61_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_61_V_ce1 = 1'b1; + end else begin + acc_61_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_61_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_61_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_61_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_61_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_61_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_61_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd61 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd61 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd61 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd61 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd61 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd61 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd61 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd61 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd61 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd61 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd61 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd61 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd61 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd61 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd61 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd61 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd61 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd61 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd61 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd61 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd61 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd61 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd61 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd61 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd61 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd61 == add_ln203_7_fu_116022_p2)))) begin + acc_61_V_we0 = 1'b1; + end else begin + acc_61_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd61 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd61 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd61 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd61 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd61 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd61 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd61 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd61 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd61 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd61 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd61 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd61 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd61 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd61 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd61 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd61 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd61 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd61 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd61 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd61 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd61 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd61 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd61 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd61 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd61 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd61 == add_ln1265_reg_147629)))) begin + acc_61_V_we1 = 1'b1; + end else begin + acc_61_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_62_V_address0 = acc_62_V_addr_48_reg_163137; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_62_V_address0 = acc_62_V_addr_43_reg_162729; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_62_V_address0 = acc_62_V_addr_44_reg_158236; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_62_V_address0 = acc_62_V_addr_38_reg_157815; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_62_V_address0 = acc_62_V_addr_45_reg_153296; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_62_V_address0 = acc_62_V_addr_39_reg_152888; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_62_V_address0 = acc_62_V_addr_40_reg_148395; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_62_V_address0 = acc_62_V_addr_36_reg_147974; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2535 == ap_CS_fsm)) begin + acc_62_V_address0 = acc_62_V_addr_51_reg_146923; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_62_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2500 == ap_CS_fsm)) begin + acc_62_V_address0 = acc_62_V_addr_49_reg_146701; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_62_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2464 == ap_CS_fsm)) begin + acc_62_V_address0 = acc_62_V_addr_50_reg_146452; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_62_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2429 == ap_CS_fsm)) begin + acc_62_V_address0 = acc_62_V_addr_47_reg_146230; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_62_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_62_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_62_V_address1 = acc_62_V_addr_48_reg_163137; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_62_V_address1 = acc_62_V_addr_43_reg_162729; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_62_V_address1 = acc_62_V_addr_44_reg_158236; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_62_V_address1 = acc_62_V_addr_38_reg_157815; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_62_V_address1 = acc_62_V_addr_45_reg_153296; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_62_V_address1 = acc_62_V_addr_39_reg_152888; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_62_V_address1 = acc_62_V_addr_40_reg_148395; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_62_V_address1 = acc_62_V_addr_36_reg_147974; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd1; + end else begin + acc_62_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2535 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2500 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2464 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2429 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_62_V_ce0 = 1'b1; + end else begin + acc_62_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_62_V_ce1 = 1'b1; + end else begin + acc_62_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2535 == ap_CS_fsm)) begin + acc_62_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_62_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2500 == ap_CS_fsm)) begin + acc_62_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_62_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2464 == ap_CS_fsm)) begin + acc_62_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_62_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2429 == ap_CS_fsm)) begin + acc_62_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_62_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_62_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_62_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2535 == ap_CS_fsm) | (ap_ST_fsm_state2500 == ap_CS_fsm) | (ap_ST_fsm_state2464 == ap_CS_fsm) | (ap_ST_fsm_state2429 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd62 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd62 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd62 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd62 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd62 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd62 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd62 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd62 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd62 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd62 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd62 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd62 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd62 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd62 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd62 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd62 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd62 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd62 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd62 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd62 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd62 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd62 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd62 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd62 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd62 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd62 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_62_V_we0 = 1'b1; + end else begin + acc_62_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd62 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd62 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd62 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd62 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd62 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd62 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd62 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd62 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd62 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd62 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd62 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd62 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd62 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd62 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd62 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd62 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd62 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd62 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd62 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd62 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd62 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd62 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd62 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd62 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd62 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd62 == add_ln1265_reg_147629)))) begin + acc_62_V_we1 = 1'b1; + end else begin + acc_62_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_48_reg_163143; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_43_reg_162735; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_44_reg_158242; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_38_reg_157821; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_45_reg_153302; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_39_reg_152894; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_40_reg_148401; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_36_reg_147980; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2566 == ap_CS_fsm)) begin + acc_63_V_address0 = acc_63_V_addr_51_reg_146928; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_63_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2531 == ap_CS_fsm)) begin + acc_63_V_address0 = acc_63_V_addr_49_reg_146706; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_63_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2495 == ap_CS_fsm)) begin + acc_63_V_address0 = acc_63_V_addr_50_reg_146457; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_63_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2460 == ap_CS_fsm)) begin + acc_63_V_address0 = acc_63_V_addr_47_reg_146235; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_63_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_63_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_63_V_address1 = acc_63_V_addr_48_reg_163143; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_63_V_address1 = acc_63_V_addr_43_reg_162735; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_63_V_address1 = acc_63_V_addr_44_reg_158242; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_63_V_address1 = acc_63_V_addr_38_reg_157821; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_63_V_address1 = acc_63_V_addr_45_reg_153302; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_63_V_address1 = acc_63_V_addr_39_reg_152894; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_63_V_address1 = acc_63_V_addr_40_reg_148401; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_63_V_address1 = acc_63_V_addr_36_reg_147980; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd1; + end else begin + acc_63_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2566 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2531 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2495 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2460 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_63_V_ce0 = 1'b1; + end else begin + acc_63_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_63_V_ce1 = 1'b1; + end else begin + acc_63_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2566 == ap_CS_fsm)) begin + acc_63_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_63_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2531 == ap_CS_fsm)) begin + acc_63_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_63_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2495 == ap_CS_fsm)) begin + acc_63_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_63_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2460 == ap_CS_fsm)) begin + acc_63_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_63_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_63_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_63_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2566 == ap_CS_fsm) & (6'd63 == add_ln203_11_reg_146764)) | ((ap_ST_fsm_state2531 == ap_CS_fsm) & (6'd63 == add_ln203_9_reg_146542)) | ((ap_ST_fsm_state2495 == ap_CS_fsm) & (6'd63 == add_ln203_10_reg_146293)) | ((ap_ST_fsm_state2460 == ap_CS_fsm) & (6'd63 == add_ln203_7_reg_146071)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd63 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd63 == add_ln1265_7_reg_162761)) | (~(6'd31 == add_ln1265_7_reg_162761) & ~(6'd1 == add_ln1265_7_reg_162761) & ~(6'd61 == add_ln1265_7_reg_162761) & ~(6'd3 == add_ln1265_7_reg_162761) & ~(6'd39 == add_ln1265_7_reg_162761) & ~(6'd5 == add_ln1265_7_reg_162761) & ~(6'd59 == add_ln1265_7_reg_162761) & ~(6'd7 == add_ln1265_7_reg_162761) & ~(6'd33 == add_ln1265_7_reg_162761) & ~(6'd9 == add_ln1265_7_reg_162761) & ~(6'd57 == add_ln1265_7_reg_162761) & ~(6'd11 == add_ln1265_7_reg_162761) & ~(6'd45 == add_ln1265_7_reg_162761) & ~(6'd13 == add_ln1265_7_reg_162761) & ~(6'd55 == add_ln1265_7_reg_162761) & ~(6'd15 == add_ln1265_7_reg_162761) & ~(6'd35 == add_ln1265_7_reg_162761) & ~(6'd17 == add_ln1265_7_reg_162761) & ~(6'd53 == add_ln1265_7_reg_162761) & ~(6'd19 == add_ln1265_7_reg_162761) & ~(6'd41 == add_ln1265_7_reg_162761) & ~(6'd21 == add_ln1265_7_reg_162761) & ~(6'd51 == add_ln1265_7_reg_162761) & ~(6'd23 == add_ln1265_7_reg_162761) & ~(6'd37 == add_ln1265_7_reg_162761) & ~(6'd25 == add_ln1265_7_reg_162761) & ~(6'd49 == add_ln1265_7_reg_162761) & ~(6'd27 == add_ln1265_7_reg_162761) & ~(6'd43 == add_ln1265_7_reg_162761) & ~(6'd29 == add_ln1265_7_reg_162761) & ~(6'd47 == add_ln1265_7_reg_162761) & (ap_ST_fsm_state4951 == ap_CS_fsm)) | (~(6'd31 == add_ln1265_7_reg_162761) & ~(6'd1 == add_ln1265_7_reg_162761) & ~(6'd61 == add_ln1265_7_reg_162761) & ~(6'd3 == add_ln1265_7_reg_162761) & ~(6'd39 == add_ln1265_7_reg_162761) & ~(6'd5 == add_ln1265_7_reg_162761) & ~(6'd59 == add_ln1265_7_reg_162761) & ~(6'd7 == add_ln1265_7_reg_162761) & ~(6'd33 == add_ln1265_7_reg_162761) & ~(6'd9 == add_ln1265_7_reg_162761) & ~(6'd57 == add_ln1265_7_reg_162761) & ~(6'd11 == add_ln1265_7_reg_162761) & ~(6'd45 == add_ln1265_7_reg_162761) & ~(6'd13 == add_ln1265_7_reg_162761) & ~(6'd55 == add_ln1265_7_reg_162761) & ~(6'd15 == add_ln1265_7_reg_162761) & ~(6'd35 == add_ln1265_7_reg_162761) & ~(6'd17 == add_ln1265_7_reg_162761) & ~(6'd53 == add_ln1265_7_reg_162761) & ~(6'd19 == add_ln1265_7_reg_162761) & ~(6'd41 == add_ln1265_7_reg_162761) & ~(6'd21 == add_ln1265_7_reg_162761) & ~(6'd51 == add_ln1265_7_reg_162761) & ~(6'd23 == add_ln1265_7_reg_162761) & ~(6'd37 == add_ln1265_7_reg_162761) & ~(6'd25 == add_ln1265_7_reg_162761) & ~(6'd49 == add_ln1265_7_reg_162761) & ~(6'd27 == add_ln1265_7_reg_162761) & ~(6'd43 == add_ln1265_7_reg_162761) & ~(6'd29 == add_ln1265_7_reg_162761) & ~(6'd47 == add_ln1265_7_reg_162761) & (ap_ST_fsm_state4798 == ap_CS_fsm)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd63 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd63 == add_ln1265_4_reg_162353)) | (~(6'd0 == add_ln1265_4_reg_162353) & ~(6'd62 == add_ln1265_4_reg_162353) & ~(6'd2 == add_ln1265_4_reg_162353) & ~(6'd32 == add_ln1265_4_reg_162353) & ~(6'd4 == add_ln1265_4_reg_162353) & ~(6'd60 == add_ln1265_4_reg_162353) & ~(6'd6 == add_ln1265_4_reg_162353) & ~(6'd46 == add_ln1265_4_reg_162353) & ~(6'd8 == add_ln1265_4_reg_162353) & ~(6'd58 == add_ln1265_4_reg_162353) & ~(6'd10 == add_ln1265_4_reg_162353) & ~(6'd34 == add_ln1265_4_reg_162353) & ~(6'd12 == add_ln1265_4_reg_162353) & ~(6'd56 == add_ln1265_4_reg_162353) & ~(6'd14 == add_ln1265_4_reg_162353) & ~(6'd40 == add_ln1265_4_reg_162353) & ~(6'd16 == add_ln1265_4_reg_162353) & ~(6'd54 == add_ln1265_4_reg_162353) & ~(6'd18 == add_ln1265_4_reg_162353) & ~(6'd36 == add_ln1265_4_reg_162353) & ~(6'd20 == add_ln1265_4_reg_162353) & ~(6'd52 == add_ln1265_4_reg_162353) & ~(6'd22 == add_ln1265_4_reg_162353) & ~(6'd44 == add_ln1265_4_reg_162353) & ~(6'd24 == add_ln1265_4_reg_162353) & ~(6'd50 == add_ln1265_4_reg_162353) & ~(6'd26 == add_ln1265_4_reg_162353) & ~(6'd38 == add_ln1265_4_reg_162353) & ~(6'd28 == add_ln1265_4_reg_162353) & ~(6'd48 == add_ln1265_4_reg_162353) & ~(6'd30 == add_ln1265_4_reg_162353) & ~(6'd42 == add_ln1265_4_reg_162353) & (ap_ST_fsm_state4646 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_4_reg_162353) & ~(6'd62 == add_ln1265_4_reg_162353) & ~(6'd2 == add_ln1265_4_reg_162353) & ~(6'd32 == add_ln1265_4_reg_162353) & ~(6'd4 == add_ln1265_4_reg_162353) & ~(6'd60 == add_ln1265_4_reg_162353) & ~(6'd6 == add_ln1265_4_reg_162353) & ~(6'd46 == add_ln1265_4_reg_162353) & ~(6'd8 == add_ln1265_4_reg_162353) & ~(6'd58 == add_ln1265_4_reg_162353) & ~(6'd10 == add_ln1265_4_reg_162353) & ~(6'd34 == add_ln1265_4_reg_162353) & ~(6'd12 == add_ln1265_4_reg_162353) & ~(6'd56 == add_ln1265_4_reg_162353) & ~(6'd14 == add_ln1265_4_reg_162353) & ~(6'd40 == add_ln1265_4_reg_162353) & ~(6'd16 == add_ln1265_4_reg_162353) & ~(6'd54 == add_ln1265_4_reg_162353) & ~(6'd18 == add_ln1265_4_reg_162353) & ~(6'd36 == add_ln1265_4_reg_162353) & ~(6'd20 == add_ln1265_4_reg_162353) & ~(6'd52 == add_ln1265_4_reg_162353) & ~(6'd22 == add_ln1265_4_reg_162353) & ~(6'd44 == add_ln1265_4_reg_162353) & ~(6'd24 == add_ln1265_4_reg_162353) & ~(6'd50 == add_ln1265_4_reg_162353) & ~(6'd26 == add_ln1265_4_reg_162353) & ~(6'd38 == add_ln1265_4_reg_162353) & ~(6'd28 == add_ln1265_4_reg_162353) & ~(6'd48 == add_ln1265_4_reg_162353) & ~(6'd30 == add_ln1265_4_reg_162353) & ~(6'd42 == add_ln1265_4_reg_162353) & (ap_ST_fsm_state4493 == ap_CS_fsm)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd63 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd63 == add_ln1265_5_reg_157860)) | (~(6'd31 == add_ln1265_5_reg_157860) & ~(6'd1 == add_ln1265_5_reg_157860) & ~(6'd61 == add_ln1265_5_reg_157860) & ~(6'd3 == add_ln1265_5_reg_157860) & ~(6'd39 == add_ln1265_5_reg_157860) & ~(6'd5 == add_ln1265_5_reg_157860) & ~(6'd59 == add_ln1265_5_reg_157860) & ~(6'd7 == add_ln1265_5_reg_157860) & ~(6'd33 == add_ln1265_5_reg_157860) & ~(6'd9 == add_ln1265_5_reg_157860) & ~(6'd57 == add_ln1265_5_reg_157860) & ~(6'd11 == add_ln1265_5_reg_157860) & ~(6'd45 == add_ln1265_5_reg_157860) & ~(6'd13 == add_ln1265_5_reg_157860) & ~(6'd55 == add_ln1265_5_reg_157860) & ~(6'd15 == add_ln1265_5_reg_157860) & ~(6'd35 == add_ln1265_5_reg_157860) & ~(6'd17 == add_ln1265_5_reg_157860) & ~(6'd53 == add_ln1265_5_reg_157860) & ~(6'd19 == add_ln1265_5_reg_157860) & ~(6'd41 == add_ln1265_5_reg_157860) & ~(6'd21 == add_ln1265_5_reg_157860) & ~(6'd51 == add_ln1265_5_reg_157860) & ~(6'd23 == add_ln1265_5_reg_157860) & ~(6'd37 == add_ln1265_5_reg_157860) & ~(6'd25 == add_ln1265_5_reg_157860) & ~(6'd49 == add_ln1265_5_reg_157860) & ~(6'd27 == add_ln1265_5_reg_157860) & ~(6'd43 == add_ln1265_5_reg_157860) & ~(6'd29 == add_ln1265_5_reg_157860) & ~(6'd47 == add_ln1265_5_reg_157860) & (ap_ST_fsm_state4339 == ap_CS_fsm)) | (~(6'd31 == add_ln1265_5_reg_157860) & ~(6'd1 == add_ln1265_5_reg_157860) & ~(6'd61 == add_ln1265_5_reg_157860) & ~(6'd3 == add_ln1265_5_reg_157860) & ~(6'd39 == add_ln1265_5_reg_157860) & ~(6'd5 == add_ln1265_5_reg_157860) & ~(6'd59 == add_ln1265_5_reg_157860) & ~(6'd7 == add_ln1265_5_reg_157860) & ~(6'd33 == add_ln1265_5_reg_157860) & ~(6'd9 == add_ln1265_5_reg_157860) & ~(6'd57 == add_ln1265_5_reg_157860) & ~(6'd11 == add_ln1265_5_reg_157860) & ~(6'd45 == add_ln1265_5_reg_157860) & ~(6'd13 == add_ln1265_5_reg_157860) & ~(6'd55 == add_ln1265_5_reg_157860) & ~(6'd15 == add_ln1265_5_reg_157860) & ~(6'd35 == add_ln1265_5_reg_157860) & ~(6'd17 == add_ln1265_5_reg_157860) & ~(6'd53 == add_ln1265_5_reg_157860) & ~(6'd19 == add_ln1265_5_reg_157860) & ~(6'd41 == add_ln1265_5_reg_157860) & ~(6'd21 == add_ln1265_5_reg_157860) & ~(6'd51 == add_ln1265_5_reg_157860) & ~(6'd23 == add_ln1265_5_reg_157860) & ~(6'd37 == add_ln1265_5_reg_157860) & ~(6'd25 == add_ln1265_5_reg_157860) & ~(6'd49 == add_ln1265_5_reg_157860) & ~(6'd27 == add_ln1265_5_reg_157860) & ~(6'd43 == add_ln1265_5_reg_157860) & ~(6'd29 == add_ln1265_5_reg_157860) & ~(6'd47 == add_ln1265_5_reg_157860) & (ap_ST_fsm_state4186 == ap_CS_fsm)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd63 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd63 == add_ln1265_1_reg_157439)) | (~(6'd0 == add_ln1265_1_reg_157439) & ~(6'd62 == add_ln1265_1_reg_157439) & ~(6'd2 == add_ln1265_1_reg_157439) & ~(6'd32 == add_ln1265_1_reg_157439) & ~(6'd4 == add_ln1265_1_reg_157439) & ~(6'd60 == add_ln1265_1_reg_157439) & ~(6'd6 == add_ln1265_1_reg_157439) & ~(6'd46 == add_ln1265_1_reg_157439) & ~(6'd8 == add_ln1265_1_reg_157439) & ~(6'd58 == add_ln1265_1_reg_157439) & ~(6'd10 == add_ln1265_1_reg_157439) & ~(6'd34 == add_ln1265_1_reg_157439) & ~(6'd12 == add_ln1265_1_reg_157439) & ~(6'd56 == add_ln1265_1_reg_157439) & ~(6'd14 == add_ln1265_1_reg_157439) & ~(6'd40 == add_ln1265_1_reg_157439) & ~(6'd16 == add_ln1265_1_reg_157439) & ~(6'd54 == add_ln1265_1_reg_157439) & ~(6'd18 == add_ln1265_1_reg_157439) & ~(6'd36 == add_ln1265_1_reg_157439) & ~(6'd20 == add_ln1265_1_reg_157439) & ~(6'd52 == add_ln1265_1_reg_157439) & ~(6'd22 == add_ln1265_1_reg_157439) & ~(6'd44 == add_ln1265_1_reg_157439) & ~(6'd24 == add_ln1265_1_reg_157439) & ~(6'd50 == add_ln1265_1_reg_157439) & ~(6'd26 == add_ln1265_1_reg_157439) & ~(6'd38 == add_ln1265_1_reg_157439) & ~(6'd28 == add_ln1265_1_reg_157439) & ~(6'd48 == add_ln1265_1_reg_157439) & ~(6'd30 == add_ln1265_1_reg_157439) & ~(6'd42 == add_ln1265_1_reg_157439) & (ap_ST_fsm_state4033 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_1_reg_157439) & ~(6'd62 == add_ln1265_1_reg_157439) & ~(6'd2 == add_ln1265_1_reg_157439) & ~(6'd32 == add_ln1265_1_reg_157439) & ~(6'd4 == add_ln1265_1_reg_157439) & ~(6'd60 == add_ln1265_1_reg_157439) & ~(6'd6 == add_ln1265_1_reg_157439) & ~(6'd46 == add_ln1265_1_reg_157439) & ~(6'd8 == add_ln1265_1_reg_157439) & ~(6'd58 == add_ln1265_1_reg_157439) & ~(6'd10 == add_ln1265_1_reg_157439) & ~(6'd34 == add_ln1265_1_reg_157439) & ~(6'd12 == add_ln1265_1_reg_157439) & ~(6'd56 == add_ln1265_1_reg_157439) & ~(6'd14 == add_ln1265_1_reg_157439) & ~(6'd40 == add_ln1265_1_reg_157439) & ~(6'd16 == add_ln1265_1_reg_157439) & ~(6'd54 == add_ln1265_1_reg_157439) & ~(6'd18 == add_ln1265_1_reg_157439) & ~(6'd36 == add_ln1265_1_reg_157439) & ~(6'd20 == add_ln1265_1_reg_157439) & ~(6'd52 == add_ln1265_1_reg_157439) & ~(6'd22 == add_ln1265_1_reg_157439) & ~(6'd44 == add_ln1265_1_reg_157439) & ~(6'd24 == add_ln1265_1_reg_157439) & ~(6'd50 == add_ln1265_1_reg_157439) & ~(6'd26 == add_ln1265_1_reg_157439) & ~(6'd38 == add_ln1265_1_reg_157439) & ~(6'd28 == add_ln1265_1_reg_157439) & ~(6'd48 == add_ln1265_1_reg_157439) & ~(6'd30 == add_ln1265_1_reg_157439) & ~(6'd42 == add_ln1265_1_reg_157439) & (ap_ST_fsm_state3879 == ap_CS_fsm)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd63 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd63 == add_ln1265_6_reg_152920)) | (~(6'd31 == add_ln1265_6_reg_152920) & ~(6'd1 == add_ln1265_6_reg_152920) & ~(6'd61 == add_ln1265_6_reg_152920) & ~(6'd3 == add_ln1265_6_reg_152920) & ~(6'd39 == add_ln1265_6_reg_152920) & ~(6'd5 == add_ln1265_6_reg_152920) & ~(6'd59 == add_ln1265_6_reg_152920) & ~(6'd7 == add_ln1265_6_reg_152920) & ~(6'd33 == add_ln1265_6_reg_152920) & ~(6'd9 == add_ln1265_6_reg_152920) & ~(6'd57 == add_ln1265_6_reg_152920) & ~(6'd11 == add_ln1265_6_reg_152920) & ~(6'd45 == add_ln1265_6_reg_152920) & ~(6'd13 == add_ln1265_6_reg_152920) & ~(6'd55 == add_ln1265_6_reg_152920) & ~(6'd15 == add_ln1265_6_reg_152920) & ~(6'd35 == add_ln1265_6_reg_152920) & ~(6'd17 == add_ln1265_6_reg_152920) & ~(6'd53 == add_ln1265_6_reg_152920) & ~(6'd19 == add_ln1265_6_reg_152920) & ~(6'd41 == add_ln1265_6_reg_152920) & ~(6'd21 == add_ln1265_6_reg_152920) & ~(6'd51 == add_ln1265_6_reg_152920) & ~(6'd23 == add_ln1265_6_reg_152920) & ~(6'd37 == add_ln1265_6_reg_152920) & ~(6'd25 == add_ln1265_6_reg_152920) & ~(6'd49 == add_ln1265_6_reg_152920) & ~(6'd27 == add_ln1265_6_reg_152920) & ~(6'd43 == add_ln1265_6_reg_152920) & ~(6'd29 == add_ln1265_6_reg_152920) & ~(6'd47 == add_ln1265_6_reg_152920) & (ap_ST_fsm_state3724 == ap_CS_fsm)) | (~(6'd31 == add_ln1265_6_reg_152920) & ~(6'd1 == add_ln1265_6_reg_152920) & ~(6'd61 == add_ln1265_6_reg_152920) & ~(6'd3 == add_ln1265_6_reg_152920) & ~(6'd39 == add_ln1265_6_reg_152920) & ~(6'd5 == add_ln1265_6_reg_152920) & ~(6'd59 == add_ln1265_6_reg_152920) & ~(6'd7 == add_ln1265_6_reg_152920) & ~(6'd33 == add_ln1265_6_reg_152920) & ~(6'd9 == add_ln1265_6_reg_152920) & ~(6'd57 == add_ln1265_6_reg_152920) & ~(6'd11 == add_ln1265_6_reg_152920) & ~(6'd45 == add_ln1265_6_reg_152920) & ~(6'd13 == add_ln1265_6_reg_152920) & ~(6'd55 == add_ln1265_6_reg_152920) & ~(6'd15 == add_ln1265_6_reg_152920) & ~(6'd35 == add_ln1265_6_reg_152920) & ~(6'd17 == add_ln1265_6_reg_152920) & ~(6'd53 == add_ln1265_6_reg_152920) & ~(6'd19 == add_ln1265_6_reg_152920) & ~(6'd41 == add_ln1265_6_reg_152920) & ~(6'd21 == add_ln1265_6_reg_152920) & ~(6'd51 == add_ln1265_6_reg_152920) & ~(6'd23 == add_ln1265_6_reg_152920) & ~(6'd37 == add_ln1265_6_reg_152920) & ~(6'd25 == add_ln1265_6_reg_152920) & ~(6'd49 == add_ln1265_6_reg_152920) & ~(6'd27 == add_ln1265_6_reg_152920) & ~(6'd43 == add_ln1265_6_reg_152920) & ~(6'd29 == add_ln1265_6_reg_152920) & ~(6'd47 == add_ln1265_6_reg_152920) & (ap_ST_fsm_state3571 == ap_CS_fsm)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd63 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd63 == add_ln1265_2_reg_152512)) | (~(6'd0 == add_ln1265_2_reg_152512) & ~(6'd62 == add_ln1265_2_reg_152512) & ~(6'd2 == add_ln1265_2_reg_152512) & ~(6'd32 == add_ln1265_2_reg_152512) & ~(6'd4 == add_ln1265_2_reg_152512) & ~(6'd60 == add_ln1265_2_reg_152512) & ~(6'd6 == add_ln1265_2_reg_152512) & ~(6'd46 == add_ln1265_2_reg_152512) & ~(6'd8 == add_ln1265_2_reg_152512) & ~(6'd58 == add_ln1265_2_reg_152512) & ~(6'd10 == add_ln1265_2_reg_152512) & ~(6'd34 == add_ln1265_2_reg_152512) & ~(6'd12 == add_ln1265_2_reg_152512) & ~(6'd56 == add_ln1265_2_reg_152512) & ~(6'd14 == add_ln1265_2_reg_152512) & ~(6'd40 == add_ln1265_2_reg_152512) & ~(6'd16 == add_ln1265_2_reg_152512) & ~(6'd54 == add_ln1265_2_reg_152512) & ~(6'd18 == add_ln1265_2_reg_152512) & ~(6'd36 == add_ln1265_2_reg_152512) & ~(6'd20 == add_ln1265_2_reg_152512) & ~(6'd52 == add_ln1265_2_reg_152512) & ~(6'd22 == add_ln1265_2_reg_152512) & ~(6'd44 == add_ln1265_2_reg_152512) & ~(6'd24 == add_ln1265_2_reg_152512) & ~(6'd50 == add_ln1265_2_reg_152512) & ~(6'd26 == add_ln1265_2_reg_152512) & ~(6'd38 == add_ln1265_2_reg_152512) & ~(6'd28 == add_ln1265_2_reg_152512) & ~(6'd48 == add_ln1265_2_reg_152512) & ~(6'd30 == add_ln1265_2_reg_152512) & ~(6'd42 == add_ln1265_2_reg_152512) & (ap_ST_fsm_state3418 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_2_reg_152512) & ~(6'd62 == add_ln1265_2_reg_152512) & ~(6'd2 == add_ln1265_2_reg_152512) & ~(6'd32 == add_ln1265_2_reg_152512) & ~(6'd4 == add_ln1265_2_reg_152512) & ~(6'd60 == add_ln1265_2_reg_152512) & ~(6'd6 == add_ln1265_2_reg_152512) & ~(6'd46 == add_ln1265_2_reg_152512) & ~(6'd8 == add_ln1265_2_reg_152512) & ~(6'd58 == add_ln1265_2_reg_152512) & ~(6'd10 == add_ln1265_2_reg_152512) & ~(6'd34 == add_ln1265_2_reg_152512) & ~(6'd12 == add_ln1265_2_reg_152512) & ~(6'd56 == add_ln1265_2_reg_152512) & ~(6'd14 == add_ln1265_2_reg_152512) & ~(6'd40 == add_ln1265_2_reg_152512) & ~(6'd16 == add_ln1265_2_reg_152512) & ~(6'd54 == add_ln1265_2_reg_152512) & ~(6'd18 == add_ln1265_2_reg_152512) & ~(6'd36 == add_ln1265_2_reg_152512) & ~(6'd20 == add_ln1265_2_reg_152512) & ~(6'd52 == add_ln1265_2_reg_152512) & ~(6'd22 == add_ln1265_2_reg_152512) & ~(6'd44 == add_ln1265_2_reg_152512) & ~(6'd24 == add_ln1265_2_reg_152512) & ~(6'd50 == add_ln1265_2_reg_152512) & ~(6'd26 == add_ln1265_2_reg_152512) & ~(6'd38 == add_ln1265_2_reg_152512) & ~(6'd28 == add_ln1265_2_reg_152512) & ~(6'd48 == add_ln1265_2_reg_152512) & ~(6'd30 == add_ln1265_2_reg_152512) & ~(6'd42 == add_ln1265_2_reg_152512) & (ap_ST_fsm_state3264 == ap_CS_fsm)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd63 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd63 == add_ln1265_3_reg_148019)) | (~(6'd31 == add_ln1265_3_reg_148019) & ~(6'd1 == add_ln1265_3_reg_148019) & ~(6'd61 == add_ln1265_3_reg_148019) & ~(6'd3 == add_ln1265_3_reg_148019) & ~(6'd39 == add_ln1265_3_reg_148019) & ~(6'd5 == add_ln1265_3_reg_148019) & ~(6'd59 == add_ln1265_3_reg_148019) & ~(6'd7 == add_ln1265_3_reg_148019) & ~(6'd33 == add_ln1265_3_reg_148019) & ~(6'd9 == add_ln1265_3_reg_148019) & ~(6'd57 == add_ln1265_3_reg_148019) & ~(6'd11 == add_ln1265_3_reg_148019) & ~(6'd45 == add_ln1265_3_reg_148019) & ~(6'd13 == add_ln1265_3_reg_148019) & ~(6'd55 == add_ln1265_3_reg_148019) & ~(6'd15 == add_ln1265_3_reg_148019) & ~(6'd35 == add_ln1265_3_reg_148019) & ~(6'd17 == add_ln1265_3_reg_148019) & ~(6'd53 == add_ln1265_3_reg_148019) & ~(6'd19 == add_ln1265_3_reg_148019) & ~(6'd41 == add_ln1265_3_reg_148019) & ~(6'd21 == add_ln1265_3_reg_148019) & ~(6'd51 == add_ln1265_3_reg_148019) & ~(6'd23 == add_ln1265_3_reg_148019) & ~(6'd37 == add_ln1265_3_reg_148019) & ~(6'd25 == add_ln1265_3_reg_148019) & ~(6'd49 == add_ln1265_3_reg_148019) & ~(6'd27 == add_ln1265_3_reg_148019) & ~(6'd43 == add_ln1265_3_reg_148019) & ~(6'd29 == add_ln1265_3_reg_148019) & ~(6'd47 == add_ln1265_3_reg_148019) & (ap_ST_fsm_state3110 == ap_CS_fsm)) | (~(6'd31 == add_ln1265_3_reg_148019) & ~(6'd1 == add_ln1265_3_reg_148019) & ~(6'd61 == add_ln1265_3_reg_148019) & ~(6'd3 == add_ln1265_3_reg_148019) & ~(6'd39 == add_ln1265_3_reg_148019) & ~(6'd5 == add_ln1265_3_reg_148019) & ~(6'd59 == add_ln1265_3_reg_148019) & ~(6'd7 == add_ln1265_3_reg_148019) & ~(6'd33 == add_ln1265_3_reg_148019) & ~(6'd9 == add_ln1265_3_reg_148019) & ~(6'd57 == add_ln1265_3_reg_148019) & ~(6'd11 == add_ln1265_3_reg_148019) & ~(6'd45 == add_ln1265_3_reg_148019) & ~(6'd13 == add_ln1265_3_reg_148019) & ~(6'd55 == add_ln1265_3_reg_148019) & ~(6'd15 == add_ln1265_3_reg_148019) & ~(6'd35 == add_ln1265_3_reg_148019) & ~(6'd17 == add_ln1265_3_reg_148019) & ~(6'd53 == add_ln1265_3_reg_148019) & ~(6'd19 == add_ln1265_3_reg_148019) & ~(6'd41 == add_ln1265_3_reg_148019) & ~(6'd21 == add_ln1265_3_reg_148019) & ~(6'd51 == add_ln1265_3_reg_148019) & ~(6'd23 == add_ln1265_3_reg_148019) & ~(6'd37 == add_ln1265_3_reg_148019) & ~(6'd25 == add_ln1265_3_reg_148019) & ~(6'd49 == add_ln1265_3_reg_148019) & ~(6'd27 == add_ln1265_3_reg_148019) & ~(6'd43 == add_ln1265_3_reg_148019) & ~(6'd29 == add_ln1265_3_reg_148019) & ~(6'd47 == add_ln1265_3_reg_148019) & (ap_ST_fsm_state2956 == ap_CS_fsm)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd63 == add_ln1265_reg_147629)) | (~(6'd0 == add_ln1265_reg_147629) & ~(6'd62 == add_ln1265_reg_147629) & ~(6'd2 == add_ln1265_reg_147629) & ~(6'd32 == add_ln1265_reg_147629) & ~(6'd4 == add_ln1265_reg_147629) & ~(6'd60 == add_ln1265_reg_147629) & ~(6'd6 == add_ln1265_reg_147629) & ~(6'd46 == add_ln1265_reg_147629) & ~(6'd8 == add_ln1265_reg_147629) & ~(6'd58 == add_ln1265_reg_147629) & ~(6'd10 == add_ln1265_reg_147629) & ~(6'd34 == add_ln1265_reg_147629) & ~(6'd12 == add_ln1265_reg_147629) & ~(6'd56 == add_ln1265_reg_147629) & ~(6'd14 == add_ln1265_reg_147629) & ~(6'd40 == add_ln1265_reg_147629) & ~(6'd16 == add_ln1265_reg_147629) & ~(6'd54 == add_ln1265_reg_147629) & ~(6'd18 == add_ln1265_reg_147629) & ~(6'd36 == add_ln1265_reg_147629) & ~(6'd20 == add_ln1265_reg_147629) & ~(6'd52 == add_ln1265_reg_147629) & ~(6'd22 == add_ln1265_reg_147629) & ~(6'd44 == add_ln1265_reg_147629) & ~(6'd24 == add_ln1265_reg_147629) & ~(6'd50 == add_ln1265_reg_147629) & ~(6'd26 == add_ln1265_reg_147629) & ~(6'd38 == add_ln1265_reg_147629) & ~(6'd28 == add_ln1265_reg_147629) & ~(6'd48 == add_ln1265_reg_147629) & ~(6'd30 == add_ln1265_reg_147629) & ~(6'd42 == add_ln1265_reg_147629) & (ap_ST_fsm_state2803 == ap_CS_fsm)) | (~(6'd0 == add_ln203_8_fu_116969_p2) & ~(6'd62 == add_ln203_8_fu_116969_p2) & ~(6'd2 == add_ln203_8_fu_116969_p2) & ~(6'd32 == add_ln203_8_fu_116969_p2) & ~(6'd4 == add_ln203_8_fu_116969_p2) & ~(6'd60 == add_ln203_8_fu_116969_p2) & ~(6'd6 == add_ln203_8_fu_116969_p2) & ~(6'd46 == add_ln203_8_fu_116969_p2) & ~(6'd8 == add_ln203_8_fu_116969_p2) & ~(6'd58 == add_ln203_8_fu_116969_p2) & ~(6'd10 == add_ln203_8_fu_116969_p2) & ~(6'd34 == add_ln203_8_fu_116969_p2) & ~(6'd12 == add_ln203_8_fu_116969_p2) & ~(6'd56 == add_ln203_8_fu_116969_p2) & ~(6'd14 == add_ln203_8_fu_116969_p2) & ~(6'd40 == add_ln203_8_fu_116969_p2) & ~(6'd16 == add_ln203_8_fu_116969_p2) & ~(6'd54 == add_ln203_8_fu_116969_p2) & ~(6'd18 == add_ln203_8_fu_116969_p2) & ~(6'd36 == add_ln203_8_fu_116969_p2) & ~(6'd20 == add_ln203_8_fu_116969_p2) & ~(6'd52 == add_ln203_8_fu_116969_p2) & ~(6'd22 == add_ln203_8_fu_116969_p2) & ~(6'd44 == add_ln203_8_fu_116969_p2) & ~(6'd24 == add_ln203_8_fu_116969_p2) & ~(6'd50 == add_ln203_8_fu_116969_p2) & ~(6'd26 == add_ln203_8_fu_116969_p2) & ~(6'd38 == add_ln203_8_fu_116969_p2) & ~(6'd28 == add_ln203_8_fu_116969_p2) & ~(6'd48 == add_ln203_8_fu_116969_p2) & ~(6'd30 == add_ln203_8_fu_116969_p2) & ~(6'd42 == add_ln203_8_fu_116969_p2) & (ap_ST_fsm_state2533 == ap_CS_fsm) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | (~(6'd0 == add_ln203_5_fu_116593_p2) & ~(6'd62 == add_ln203_5_fu_116593_p2) & ~(6'd2 == add_ln203_5_fu_116593_p2) & ~(6'd32 == add_ln203_5_fu_116593_p2) & ~(6'd4 == add_ln203_5_fu_116593_p2) & ~(6'd60 == add_ln203_5_fu_116593_p2) & ~(6'd6 == add_ln203_5_fu_116593_p2) & ~(6'd46 == add_ln203_5_fu_116593_p2) & ~(6'd8 == add_ln203_5_fu_116593_p2) & ~(6'd58 == add_ln203_5_fu_116593_p2) & ~(6'd10 == add_ln203_5_fu_116593_p2) & ~(6'd34 == add_ln203_5_fu_116593_p2) & ~(6'd12 == add_ln203_5_fu_116593_p2) & ~(6'd56 == add_ln203_5_fu_116593_p2) & ~(6'd14 == add_ln203_5_fu_116593_p2) & ~(6'd40 == add_ln203_5_fu_116593_p2) & ~(6'd16 == add_ln203_5_fu_116593_p2) & ~(6'd54 == add_ln203_5_fu_116593_p2) & ~(6'd18 == add_ln203_5_fu_116593_p2) & ~(6'd36 == add_ln203_5_fu_116593_p2) & ~(6'd20 == add_ln203_5_fu_116593_p2) & ~(6'd52 == add_ln203_5_fu_116593_p2) & ~(6'd22 == add_ln203_5_fu_116593_p2) & ~(6'd44 == add_ln203_5_fu_116593_p2) & ~(6'd24 == add_ln203_5_fu_116593_p2) & ~(6'd50 == add_ln203_5_fu_116593_p2) & ~(6'd26 == add_ln203_5_fu_116593_p2) & ~(6'd38 == add_ln203_5_fu_116593_p2) & ~(6'd28 == add_ln203_5_fu_116593_p2) & ~(6'd48 == add_ln203_5_fu_116593_p2) & ~(6'd30 == add_ln203_5_fu_116593_p2) & ~(6'd42 == add_ln203_5_fu_116593_p2) & (ap_ST_fsm_state2498 == ap_CS_fsm) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | (~(6'd0 == add_ln203_6_fu_116205_p2) & ~(6'd62 == add_ln203_6_fu_116205_p2) & ~(6'd2 == add_ln203_6_fu_116205_p2) & ~(6'd32 == add_ln203_6_fu_116205_p2) & ~(6'd4 == add_ln203_6_fu_116205_p2) & ~(6'd60 == add_ln203_6_fu_116205_p2) & ~(6'd6 == add_ln203_6_fu_116205_p2) & ~(6'd46 == add_ln203_6_fu_116205_p2) & ~(6'd8 == add_ln203_6_fu_116205_p2) & ~(6'd58 == add_ln203_6_fu_116205_p2) & ~(6'd10 == add_ln203_6_fu_116205_p2) & ~(6'd34 == add_ln203_6_fu_116205_p2) & ~(6'd12 == add_ln203_6_fu_116205_p2) & ~(6'd56 == add_ln203_6_fu_116205_p2) & ~(6'd14 == add_ln203_6_fu_116205_p2) & ~(6'd40 == add_ln203_6_fu_116205_p2) & ~(6'd16 == add_ln203_6_fu_116205_p2) & ~(6'd54 == add_ln203_6_fu_116205_p2) & ~(6'd18 == add_ln203_6_fu_116205_p2) & ~(6'd36 == add_ln203_6_fu_116205_p2) & ~(6'd20 == add_ln203_6_fu_116205_p2) & ~(6'd52 == add_ln203_6_fu_116205_p2) & ~(6'd22 == add_ln203_6_fu_116205_p2) & ~(6'd44 == add_ln203_6_fu_116205_p2) & ~(6'd24 == add_ln203_6_fu_116205_p2) & ~(6'd50 == add_ln203_6_fu_116205_p2) & ~(6'd26 == add_ln203_6_fu_116205_p2) & ~(6'd38 == add_ln203_6_fu_116205_p2) & ~(6'd28 == add_ln203_6_fu_116205_p2) & ~(6'd48 == add_ln203_6_fu_116205_p2) & ~(6'd30 == add_ln203_6_fu_116205_p2) & ~(6'd42 == add_ln203_6_fu_116205_p2) & (ap_ST_fsm_state2462 == ap_CS_fsm) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | (~(6'd0 == add_ln203_4_fu_115829_p2) & ~(6'd62 == add_ln203_4_fu_115829_p2) & ~(6'd2 == add_ln203_4_fu_115829_p2) & ~(6'd32 == add_ln203_4_fu_115829_p2) & ~(6'd4 == add_ln203_4_fu_115829_p2) & ~(6'd60 == add_ln203_4_fu_115829_p2) & ~(6'd6 == add_ln203_4_fu_115829_p2) & ~(6'd46 == add_ln203_4_fu_115829_p2) & ~(6'd8 == add_ln203_4_fu_115829_p2) & ~(6'd58 == add_ln203_4_fu_115829_p2) & ~(6'd10 == add_ln203_4_fu_115829_p2) & ~(6'd34 == add_ln203_4_fu_115829_p2) & ~(6'd12 == add_ln203_4_fu_115829_p2) & ~(6'd56 == add_ln203_4_fu_115829_p2) & ~(6'd14 == add_ln203_4_fu_115829_p2) & ~(6'd40 == add_ln203_4_fu_115829_p2) & ~(6'd16 == add_ln203_4_fu_115829_p2) & ~(6'd54 == add_ln203_4_fu_115829_p2) & ~(6'd18 == add_ln203_4_fu_115829_p2) & ~(6'd36 == add_ln203_4_fu_115829_p2) & ~(6'd20 == add_ln203_4_fu_115829_p2) & ~(6'd52 == add_ln203_4_fu_115829_p2) & ~(6'd22 == add_ln203_4_fu_115829_p2) & ~(6'd44 == add_ln203_4_fu_115829_p2) & ~(6'd24 == add_ln203_4_fu_115829_p2) & ~(6'd50 == add_ln203_4_fu_115829_p2) & ~(6'd26 == add_ln203_4_fu_115829_p2) & ~(6'd38 == add_ln203_4_fu_115829_p2) & ~(6'd28 == add_ln203_4_fu_115829_p2) & ~(6'd48 == add_ln203_4_fu_115829_p2) & ~(6'd30 == add_ln203_4_fu_115829_p2) & ~(6'd42 == add_ln203_4_fu_115829_p2) & (ap_ST_fsm_state2427 == ap_CS_fsm) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_63_V_we0 = 1'b1; + end else begin + acc_63_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd63 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd63 == add_ln1265_7_reg_162761)) | (~(6'd31 == add_ln1265_7_reg_162761) & ~(6'd1 == add_ln1265_7_reg_162761) & ~(6'd61 == add_ln1265_7_reg_162761) & ~(6'd3 == add_ln1265_7_reg_162761) & ~(6'd39 == add_ln1265_7_reg_162761) & ~(6'd5 == add_ln1265_7_reg_162761) & ~(6'd59 == add_ln1265_7_reg_162761) & ~(6'd7 == add_ln1265_7_reg_162761) & ~(6'd33 == add_ln1265_7_reg_162761) & ~(6'd9 == add_ln1265_7_reg_162761) & ~(6'd57 == add_ln1265_7_reg_162761) & ~(6'd11 == add_ln1265_7_reg_162761) & ~(6'd45 == add_ln1265_7_reg_162761) & ~(6'd13 == add_ln1265_7_reg_162761) & ~(6'd55 == add_ln1265_7_reg_162761) & ~(6'd15 == add_ln1265_7_reg_162761) & ~(6'd35 == add_ln1265_7_reg_162761) & ~(6'd17 == add_ln1265_7_reg_162761) & ~(6'd53 == add_ln1265_7_reg_162761) & ~(6'd19 == add_ln1265_7_reg_162761) & ~(6'd41 == add_ln1265_7_reg_162761) & ~(6'd21 == add_ln1265_7_reg_162761) & ~(6'd51 == add_ln1265_7_reg_162761) & ~(6'd23 == add_ln1265_7_reg_162761) & ~(6'd37 == add_ln1265_7_reg_162761) & ~(6'd25 == add_ln1265_7_reg_162761) & ~(6'd49 == add_ln1265_7_reg_162761) & ~(6'd27 == add_ln1265_7_reg_162761) & ~(6'd43 == add_ln1265_7_reg_162761) & ~(6'd29 == add_ln1265_7_reg_162761) & ~(6'd47 == add_ln1265_7_reg_162761) & (ap_ST_fsm_state4875 == ap_CS_fsm)) | (~(6'd31 == add_ln1265_7_reg_162761) & ~(6'd1 == add_ln1265_7_reg_162761) & ~(6'd61 == add_ln1265_7_reg_162761) & ~(6'd3 == add_ln1265_7_reg_162761) & ~(6'd39 == add_ln1265_7_reg_162761) & ~(6'd5 == add_ln1265_7_reg_162761) & ~(6'd59 == add_ln1265_7_reg_162761) & ~(6'd7 == add_ln1265_7_reg_162761) & ~(6'd33 == add_ln1265_7_reg_162761) & ~(6'd9 == add_ln1265_7_reg_162761) & ~(6'd57 == add_ln1265_7_reg_162761) & ~(6'd11 == add_ln1265_7_reg_162761) & ~(6'd45 == add_ln1265_7_reg_162761) & ~(6'd13 == add_ln1265_7_reg_162761) & ~(6'd55 == add_ln1265_7_reg_162761) & ~(6'd15 == add_ln1265_7_reg_162761) & ~(6'd35 == add_ln1265_7_reg_162761) & ~(6'd17 == add_ln1265_7_reg_162761) & ~(6'd53 == add_ln1265_7_reg_162761) & ~(6'd19 == add_ln1265_7_reg_162761) & ~(6'd41 == add_ln1265_7_reg_162761) & ~(6'd21 == add_ln1265_7_reg_162761) & ~(6'd51 == add_ln1265_7_reg_162761) & ~(6'd23 == add_ln1265_7_reg_162761) & ~(6'd37 == add_ln1265_7_reg_162761) & ~(6'd25 == add_ln1265_7_reg_162761) & ~(6'd49 == add_ln1265_7_reg_162761) & ~(6'd27 == add_ln1265_7_reg_162761) & ~(6'd43 == add_ln1265_7_reg_162761) & ~(6'd29 == add_ln1265_7_reg_162761) & ~(6'd47 == add_ln1265_7_reg_162761) & (ap_ST_fsm_state5026 == ap_CS_fsm)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd63 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd63 == add_ln1265_4_reg_162353)) | (~(6'd0 == add_ln1265_4_reg_162353) & ~(6'd62 == add_ln1265_4_reg_162353) & ~(6'd2 == add_ln1265_4_reg_162353) & ~(6'd32 == add_ln1265_4_reg_162353) & ~(6'd4 == add_ln1265_4_reg_162353) & ~(6'd60 == add_ln1265_4_reg_162353) & ~(6'd6 == add_ln1265_4_reg_162353) & ~(6'd46 == add_ln1265_4_reg_162353) & ~(6'd8 == add_ln1265_4_reg_162353) & ~(6'd58 == add_ln1265_4_reg_162353) & ~(6'd10 == add_ln1265_4_reg_162353) & ~(6'd34 == add_ln1265_4_reg_162353) & ~(6'd12 == add_ln1265_4_reg_162353) & ~(6'd56 == add_ln1265_4_reg_162353) & ~(6'd14 == add_ln1265_4_reg_162353) & ~(6'd40 == add_ln1265_4_reg_162353) & ~(6'd16 == add_ln1265_4_reg_162353) & ~(6'd54 == add_ln1265_4_reg_162353) & ~(6'd18 == add_ln1265_4_reg_162353) & ~(6'd36 == add_ln1265_4_reg_162353) & ~(6'd20 == add_ln1265_4_reg_162353) & ~(6'd52 == add_ln1265_4_reg_162353) & ~(6'd22 == add_ln1265_4_reg_162353) & ~(6'd44 == add_ln1265_4_reg_162353) & ~(6'd24 == add_ln1265_4_reg_162353) & ~(6'd50 == add_ln1265_4_reg_162353) & ~(6'd26 == add_ln1265_4_reg_162353) & ~(6'd38 == add_ln1265_4_reg_162353) & ~(6'd28 == add_ln1265_4_reg_162353) & ~(6'd48 == add_ln1265_4_reg_162353) & ~(6'd30 == add_ln1265_4_reg_162353) & ~(6'd42 == add_ln1265_4_reg_162353) & (ap_ST_fsm_state4570 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_4_reg_162353) & ~(6'd62 == add_ln1265_4_reg_162353) & ~(6'd2 == add_ln1265_4_reg_162353) & ~(6'd32 == add_ln1265_4_reg_162353) & ~(6'd4 == add_ln1265_4_reg_162353) & ~(6'd60 == add_ln1265_4_reg_162353) & ~(6'd6 == add_ln1265_4_reg_162353) & ~(6'd46 == add_ln1265_4_reg_162353) & ~(6'd8 == add_ln1265_4_reg_162353) & ~(6'd58 == add_ln1265_4_reg_162353) & ~(6'd10 == add_ln1265_4_reg_162353) & ~(6'd34 == add_ln1265_4_reg_162353) & ~(6'd12 == add_ln1265_4_reg_162353) & ~(6'd56 == add_ln1265_4_reg_162353) & ~(6'd14 == add_ln1265_4_reg_162353) & ~(6'd40 == add_ln1265_4_reg_162353) & ~(6'd16 == add_ln1265_4_reg_162353) & ~(6'd54 == add_ln1265_4_reg_162353) & ~(6'd18 == add_ln1265_4_reg_162353) & ~(6'd36 == add_ln1265_4_reg_162353) & ~(6'd20 == add_ln1265_4_reg_162353) & ~(6'd52 == add_ln1265_4_reg_162353) & ~(6'd22 == add_ln1265_4_reg_162353) & ~(6'd44 == add_ln1265_4_reg_162353) & ~(6'd24 == add_ln1265_4_reg_162353) & ~(6'd50 == add_ln1265_4_reg_162353) & ~(6'd26 == add_ln1265_4_reg_162353) & ~(6'd38 == add_ln1265_4_reg_162353) & ~(6'd28 == add_ln1265_4_reg_162353) & ~(6'd48 == add_ln1265_4_reg_162353) & ~(6'd30 == add_ln1265_4_reg_162353) & ~(6'd42 == add_ln1265_4_reg_162353) & (ap_ST_fsm_state4721 == ap_CS_fsm)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd63 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd63 == add_ln1265_5_reg_157860)) | (~(6'd31 == add_ln1265_5_reg_157860) & ~(6'd1 == add_ln1265_5_reg_157860) & ~(6'd61 == add_ln1265_5_reg_157860) & ~(6'd3 == add_ln1265_5_reg_157860) & ~(6'd39 == add_ln1265_5_reg_157860) & ~(6'd5 == add_ln1265_5_reg_157860) & ~(6'd59 == add_ln1265_5_reg_157860) & ~(6'd7 == add_ln1265_5_reg_157860) & ~(6'd33 == add_ln1265_5_reg_157860) & ~(6'd9 == add_ln1265_5_reg_157860) & ~(6'd57 == add_ln1265_5_reg_157860) & ~(6'd11 == add_ln1265_5_reg_157860) & ~(6'd45 == add_ln1265_5_reg_157860) & ~(6'd13 == add_ln1265_5_reg_157860) & ~(6'd55 == add_ln1265_5_reg_157860) & ~(6'd15 == add_ln1265_5_reg_157860) & ~(6'd35 == add_ln1265_5_reg_157860) & ~(6'd17 == add_ln1265_5_reg_157860) & ~(6'd53 == add_ln1265_5_reg_157860) & ~(6'd19 == add_ln1265_5_reg_157860) & ~(6'd41 == add_ln1265_5_reg_157860) & ~(6'd21 == add_ln1265_5_reg_157860) & ~(6'd51 == add_ln1265_5_reg_157860) & ~(6'd23 == add_ln1265_5_reg_157860) & ~(6'd37 == add_ln1265_5_reg_157860) & ~(6'd25 == add_ln1265_5_reg_157860) & ~(6'd49 == add_ln1265_5_reg_157860) & ~(6'd27 == add_ln1265_5_reg_157860) & ~(6'd43 == add_ln1265_5_reg_157860) & ~(6'd29 == add_ln1265_5_reg_157860) & ~(6'd47 == add_ln1265_5_reg_157860) & (ap_ST_fsm_state4263 == ap_CS_fsm)) | (~(6'd31 == add_ln1265_5_reg_157860) & ~(6'd1 == add_ln1265_5_reg_157860) & ~(6'd61 == add_ln1265_5_reg_157860) & ~(6'd3 == add_ln1265_5_reg_157860) & ~(6'd39 == add_ln1265_5_reg_157860) & ~(6'd5 == add_ln1265_5_reg_157860) & ~(6'd59 == add_ln1265_5_reg_157860) & ~(6'd7 == add_ln1265_5_reg_157860) & ~(6'd33 == add_ln1265_5_reg_157860) & ~(6'd9 == add_ln1265_5_reg_157860) & ~(6'd57 == add_ln1265_5_reg_157860) & ~(6'd11 == add_ln1265_5_reg_157860) & ~(6'd45 == add_ln1265_5_reg_157860) & ~(6'd13 == add_ln1265_5_reg_157860) & ~(6'd55 == add_ln1265_5_reg_157860) & ~(6'd15 == add_ln1265_5_reg_157860) & ~(6'd35 == add_ln1265_5_reg_157860) & ~(6'd17 == add_ln1265_5_reg_157860) & ~(6'd53 == add_ln1265_5_reg_157860) & ~(6'd19 == add_ln1265_5_reg_157860) & ~(6'd41 == add_ln1265_5_reg_157860) & ~(6'd21 == add_ln1265_5_reg_157860) & ~(6'd51 == add_ln1265_5_reg_157860) & ~(6'd23 == add_ln1265_5_reg_157860) & ~(6'd37 == add_ln1265_5_reg_157860) & ~(6'd25 == add_ln1265_5_reg_157860) & ~(6'd49 == add_ln1265_5_reg_157860) & ~(6'd27 == add_ln1265_5_reg_157860) & ~(6'd43 == add_ln1265_5_reg_157860) & ~(6'd29 == add_ln1265_5_reg_157860) & ~(6'd47 == add_ln1265_5_reg_157860) & (ap_ST_fsm_state4414 == ap_CS_fsm)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd63 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd63 == add_ln1265_1_reg_157439)) | (~(6'd0 == add_ln1265_1_reg_157439) & ~(6'd62 == add_ln1265_1_reg_157439) & ~(6'd2 == add_ln1265_1_reg_157439) & ~(6'd32 == add_ln1265_1_reg_157439) & ~(6'd4 == add_ln1265_1_reg_157439) & ~(6'd60 == add_ln1265_1_reg_157439) & ~(6'd6 == add_ln1265_1_reg_157439) & ~(6'd46 == add_ln1265_1_reg_157439) & ~(6'd8 == add_ln1265_1_reg_157439) & ~(6'd58 == add_ln1265_1_reg_157439) & ~(6'd10 == add_ln1265_1_reg_157439) & ~(6'd34 == add_ln1265_1_reg_157439) & ~(6'd12 == add_ln1265_1_reg_157439) & ~(6'd56 == add_ln1265_1_reg_157439) & ~(6'd14 == add_ln1265_1_reg_157439) & ~(6'd40 == add_ln1265_1_reg_157439) & ~(6'd16 == add_ln1265_1_reg_157439) & ~(6'd54 == add_ln1265_1_reg_157439) & ~(6'd18 == add_ln1265_1_reg_157439) & ~(6'd36 == add_ln1265_1_reg_157439) & ~(6'd20 == add_ln1265_1_reg_157439) & ~(6'd52 == add_ln1265_1_reg_157439) & ~(6'd22 == add_ln1265_1_reg_157439) & ~(6'd44 == add_ln1265_1_reg_157439) & ~(6'd24 == add_ln1265_1_reg_157439) & ~(6'd50 == add_ln1265_1_reg_157439) & ~(6'd26 == add_ln1265_1_reg_157439) & ~(6'd38 == add_ln1265_1_reg_157439) & ~(6'd28 == add_ln1265_1_reg_157439) & ~(6'd48 == add_ln1265_1_reg_157439) & ~(6'd30 == add_ln1265_1_reg_157439) & ~(6'd42 == add_ln1265_1_reg_157439) & (ap_ST_fsm_state3956 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_1_reg_157439) & ~(6'd62 == add_ln1265_1_reg_157439) & ~(6'd2 == add_ln1265_1_reg_157439) & ~(6'd32 == add_ln1265_1_reg_157439) & ~(6'd4 == add_ln1265_1_reg_157439) & ~(6'd60 == add_ln1265_1_reg_157439) & ~(6'd6 == add_ln1265_1_reg_157439) & ~(6'd46 == add_ln1265_1_reg_157439) & ~(6'd8 == add_ln1265_1_reg_157439) & ~(6'd58 == add_ln1265_1_reg_157439) & ~(6'd10 == add_ln1265_1_reg_157439) & ~(6'd34 == add_ln1265_1_reg_157439) & ~(6'd12 == add_ln1265_1_reg_157439) & ~(6'd56 == add_ln1265_1_reg_157439) & ~(6'd14 == add_ln1265_1_reg_157439) & ~(6'd40 == add_ln1265_1_reg_157439) & ~(6'd16 == add_ln1265_1_reg_157439) & ~(6'd54 == add_ln1265_1_reg_157439) & ~(6'd18 == add_ln1265_1_reg_157439) & ~(6'd36 == add_ln1265_1_reg_157439) & ~(6'd20 == add_ln1265_1_reg_157439) & ~(6'd52 == add_ln1265_1_reg_157439) & ~(6'd22 == add_ln1265_1_reg_157439) & ~(6'd44 == add_ln1265_1_reg_157439) & ~(6'd24 == add_ln1265_1_reg_157439) & ~(6'd50 == add_ln1265_1_reg_157439) & ~(6'd26 == add_ln1265_1_reg_157439) & ~(6'd38 == add_ln1265_1_reg_157439) & ~(6'd28 == add_ln1265_1_reg_157439) & ~(6'd48 == add_ln1265_1_reg_157439) & ~(6'd30 == add_ln1265_1_reg_157439) & ~(6'd42 == add_ln1265_1_reg_157439) & (ap_ST_fsm_state4108 == ap_CS_fsm)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd63 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd63 == add_ln1265_6_reg_152920)) | (~(6'd31 == add_ln1265_6_reg_152920) & ~(6'd1 == add_ln1265_6_reg_152920) & ~(6'd61 == add_ln1265_6_reg_152920) & ~(6'd3 == add_ln1265_6_reg_152920) & ~(6'd39 == add_ln1265_6_reg_152920) & ~(6'd5 == add_ln1265_6_reg_152920) & ~(6'd59 == add_ln1265_6_reg_152920) & ~(6'd7 == add_ln1265_6_reg_152920) & ~(6'd33 == add_ln1265_6_reg_152920) & ~(6'd9 == add_ln1265_6_reg_152920) & ~(6'd57 == add_ln1265_6_reg_152920) & ~(6'd11 == add_ln1265_6_reg_152920) & ~(6'd45 == add_ln1265_6_reg_152920) & ~(6'd13 == add_ln1265_6_reg_152920) & ~(6'd55 == add_ln1265_6_reg_152920) & ~(6'd15 == add_ln1265_6_reg_152920) & ~(6'd35 == add_ln1265_6_reg_152920) & ~(6'd17 == add_ln1265_6_reg_152920) & ~(6'd53 == add_ln1265_6_reg_152920) & ~(6'd19 == add_ln1265_6_reg_152920) & ~(6'd41 == add_ln1265_6_reg_152920) & ~(6'd21 == add_ln1265_6_reg_152920) & ~(6'd51 == add_ln1265_6_reg_152920) & ~(6'd23 == add_ln1265_6_reg_152920) & ~(6'd37 == add_ln1265_6_reg_152920) & ~(6'd25 == add_ln1265_6_reg_152920) & ~(6'd49 == add_ln1265_6_reg_152920) & ~(6'd27 == add_ln1265_6_reg_152920) & ~(6'd43 == add_ln1265_6_reg_152920) & ~(6'd29 == add_ln1265_6_reg_152920) & ~(6'd47 == add_ln1265_6_reg_152920) & (ap_ST_fsm_state3648 == ap_CS_fsm)) | (~(6'd31 == add_ln1265_6_reg_152920) & ~(6'd1 == add_ln1265_6_reg_152920) & ~(6'd61 == add_ln1265_6_reg_152920) & ~(6'd3 == add_ln1265_6_reg_152920) & ~(6'd39 == add_ln1265_6_reg_152920) & ~(6'd5 == add_ln1265_6_reg_152920) & ~(6'd59 == add_ln1265_6_reg_152920) & ~(6'd7 == add_ln1265_6_reg_152920) & ~(6'd33 == add_ln1265_6_reg_152920) & ~(6'd9 == add_ln1265_6_reg_152920) & ~(6'd57 == add_ln1265_6_reg_152920) & ~(6'd11 == add_ln1265_6_reg_152920) & ~(6'd45 == add_ln1265_6_reg_152920) & ~(6'd13 == add_ln1265_6_reg_152920) & ~(6'd55 == add_ln1265_6_reg_152920) & ~(6'd15 == add_ln1265_6_reg_152920) & ~(6'd35 == add_ln1265_6_reg_152920) & ~(6'd17 == add_ln1265_6_reg_152920) & ~(6'd53 == add_ln1265_6_reg_152920) & ~(6'd19 == add_ln1265_6_reg_152920) & ~(6'd41 == add_ln1265_6_reg_152920) & ~(6'd21 == add_ln1265_6_reg_152920) & ~(6'd51 == add_ln1265_6_reg_152920) & ~(6'd23 == add_ln1265_6_reg_152920) & ~(6'd37 == add_ln1265_6_reg_152920) & ~(6'd25 == add_ln1265_6_reg_152920) & ~(6'd49 == add_ln1265_6_reg_152920) & ~(6'd27 == add_ln1265_6_reg_152920) & ~(6'd43 == add_ln1265_6_reg_152920) & ~(6'd29 == add_ln1265_6_reg_152920) & ~(6'd47 == add_ln1265_6_reg_152920) & (ap_ST_fsm_state3799 == ap_CS_fsm)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd63 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd63 == add_ln1265_2_reg_152512)) | (~(6'd0 == add_ln1265_2_reg_152512) & ~(6'd62 == add_ln1265_2_reg_152512) & ~(6'd2 == add_ln1265_2_reg_152512) & ~(6'd32 == add_ln1265_2_reg_152512) & ~(6'd4 == add_ln1265_2_reg_152512) & ~(6'd60 == add_ln1265_2_reg_152512) & ~(6'd6 == add_ln1265_2_reg_152512) & ~(6'd46 == add_ln1265_2_reg_152512) & ~(6'd8 == add_ln1265_2_reg_152512) & ~(6'd58 == add_ln1265_2_reg_152512) & ~(6'd10 == add_ln1265_2_reg_152512) & ~(6'd34 == add_ln1265_2_reg_152512) & ~(6'd12 == add_ln1265_2_reg_152512) & ~(6'd56 == add_ln1265_2_reg_152512) & ~(6'd14 == add_ln1265_2_reg_152512) & ~(6'd40 == add_ln1265_2_reg_152512) & ~(6'd16 == add_ln1265_2_reg_152512) & ~(6'd54 == add_ln1265_2_reg_152512) & ~(6'd18 == add_ln1265_2_reg_152512) & ~(6'd36 == add_ln1265_2_reg_152512) & ~(6'd20 == add_ln1265_2_reg_152512) & ~(6'd52 == add_ln1265_2_reg_152512) & ~(6'd22 == add_ln1265_2_reg_152512) & ~(6'd44 == add_ln1265_2_reg_152512) & ~(6'd24 == add_ln1265_2_reg_152512) & ~(6'd50 == add_ln1265_2_reg_152512) & ~(6'd26 == add_ln1265_2_reg_152512) & ~(6'd38 == add_ln1265_2_reg_152512) & ~(6'd28 == add_ln1265_2_reg_152512) & ~(6'd48 == add_ln1265_2_reg_152512) & ~(6'd30 == add_ln1265_2_reg_152512) & ~(6'd42 == add_ln1265_2_reg_152512) & (ap_ST_fsm_state3341 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_2_reg_152512) & ~(6'd62 == add_ln1265_2_reg_152512) & ~(6'd2 == add_ln1265_2_reg_152512) & ~(6'd32 == add_ln1265_2_reg_152512) & ~(6'd4 == add_ln1265_2_reg_152512) & ~(6'd60 == add_ln1265_2_reg_152512) & ~(6'd6 == add_ln1265_2_reg_152512) & ~(6'd46 == add_ln1265_2_reg_152512) & ~(6'd8 == add_ln1265_2_reg_152512) & ~(6'd58 == add_ln1265_2_reg_152512) & ~(6'd10 == add_ln1265_2_reg_152512) & ~(6'd34 == add_ln1265_2_reg_152512) & ~(6'd12 == add_ln1265_2_reg_152512) & ~(6'd56 == add_ln1265_2_reg_152512) & ~(6'd14 == add_ln1265_2_reg_152512) & ~(6'd40 == add_ln1265_2_reg_152512) & ~(6'd16 == add_ln1265_2_reg_152512) & ~(6'd54 == add_ln1265_2_reg_152512) & ~(6'd18 == add_ln1265_2_reg_152512) & ~(6'd36 == add_ln1265_2_reg_152512) & ~(6'd20 == add_ln1265_2_reg_152512) & ~(6'd52 == add_ln1265_2_reg_152512) & ~(6'd22 == add_ln1265_2_reg_152512) & ~(6'd44 == add_ln1265_2_reg_152512) & ~(6'd24 == add_ln1265_2_reg_152512) & ~(6'd50 == add_ln1265_2_reg_152512) & ~(6'd26 == add_ln1265_2_reg_152512) & ~(6'd38 == add_ln1265_2_reg_152512) & ~(6'd28 == add_ln1265_2_reg_152512) & ~(6'd48 == add_ln1265_2_reg_152512) & ~(6'd30 == add_ln1265_2_reg_152512) & ~(6'd42 == add_ln1265_2_reg_152512) & (ap_ST_fsm_state3493 == ap_CS_fsm)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd63 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd63 == add_ln1265_3_reg_148019)) | (~(6'd31 == add_ln1265_3_reg_148019) & ~(6'd1 == add_ln1265_3_reg_148019) & ~(6'd61 == add_ln1265_3_reg_148019) & ~(6'd3 == add_ln1265_3_reg_148019) & ~(6'd39 == add_ln1265_3_reg_148019) & ~(6'd5 == add_ln1265_3_reg_148019) & ~(6'd59 == add_ln1265_3_reg_148019) & ~(6'd7 == add_ln1265_3_reg_148019) & ~(6'd33 == add_ln1265_3_reg_148019) & ~(6'd9 == add_ln1265_3_reg_148019) & ~(6'd57 == add_ln1265_3_reg_148019) & ~(6'd11 == add_ln1265_3_reg_148019) & ~(6'd45 == add_ln1265_3_reg_148019) & ~(6'd13 == add_ln1265_3_reg_148019) & ~(6'd55 == add_ln1265_3_reg_148019) & ~(6'd15 == add_ln1265_3_reg_148019) & ~(6'd35 == add_ln1265_3_reg_148019) & ~(6'd17 == add_ln1265_3_reg_148019) & ~(6'd53 == add_ln1265_3_reg_148019) & ~(6'd19 == add_ln1265_3_reg_148019) & ~(6'd41 == add_ln1265_3_reg_148019) & ~(6'd21 == add_ln1265_3_reg_148019) & ~(6'd51 == add_ln1265_3_reg_148019) & ~(6'd23 == add_ln1265_3_reg_148019) & ~(6'd37 == add_ln1265_3_reg_148019) & ~(6'd25 == add_ln1265_3_reg_148019) & ~(6'd49 == add_ln1265_3_reg_148019) & ~(6'd27 == add_ln1265_3_reg_148019) & ~(6'd43 == add_ln1265_3_reg_148019) & ~(6'd29 == add_ln1265_3_reg_148019) & ~(6'd47 == add_ln1265_3_reg_148019) & (ap_ST_fsm_state3033 == ap_CS_fsm)) | (~(6'd31 == add_ln1265_3_reg_148019) & ~(6'd1 == add_ln1265_3_reg_148019) & ~(6'd61 == add_ln1265_3_reg_148019) & ~(6'd3 == add_ln1265_3_reg_148019) & ~(6'd39 == add_ln1265_3_reg_148019) & ~(6'd5 == add_ln1265_3_reg_148019) & ~(6'd59 == add_ln1265_3_reg_148019) & ~(6'd7 == add_ln1265_3_reg_148019) & ~(6'd33 == add_ln1265_3_reg_148019) & ~(6'd9 == add_ln1265_3_reg_148019) & ~(6'd57 == add_ln1265_3_reg_148019) & ~(6'd11 == add_ln1265_3_reg_148019) & ~(6'd45 == add_ln1265_3_reg_148019) & ~(6'd13 == add_ln1265_3_reg_148019) & ~(6'd55 == add_ln1265_3_reg_148019) & ~(6'd15 == add_ln1265_3_reg_148019) & ~(6'd35 == add_ln1265_3_reg_148019) & ~(6'd17 == add_ln1265_3_reg_148019) & ~(6'd53 == add_ln1265_3_reg_148019) & ~(6'd19 == add_ln1265_3_reg_148019) & ~(6'd41 == add_ln1265_3_reg_148019) & ~(6'd21 == add_ln1265_3_reg_148019) & ~(6'd51 == add_ln1265_3_reg_148019) & ~(6'd23 == add_ln1265_3_reg_148019) & ~(6'd37 == add_ln1265_3_reg_148019) & ~(6'd25 == add_ln1265_3_reg_148019) & ~(6'd49 == add_ln1265_3_reg_148019) & ~(6'd27 == add_ln1265_3_reg_148019) & ~(6'd43 == add_ln1265_3_reg_148019) & ~(6'd29 == add_ln1265_3_reg_148019) & ~(6'd47 == add_ln1265_3_reg_148019) & (ap_ST_fsm_state3185 == ap_CS_fsm)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd63 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd63 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd63 == add_ln1265_reg_147629)) | (~(6'd0 == add_ln1265_reg_147629) & ~(6'd62 == add_ln1265_reg_147629) & ~(6'd2 == add_ln1265_reg_147629) & ~(6'd32 == add_ln1265_reg_147629) & ~(6'd4 == add_ln1265_reg_147629) & ~(6'd60 == add_ln1265_reg_147629) & ~(6'd6 == add_ln1265_reg_147629) & ~(6'd46 == add_ln1265_reg_147629) & ~(6'd8 == add_ln1265_reg_147629) & ~(6'd58 == add_ln1265_reg_147629) & ~(6'd10 == add_ln1265_reg_147629) & ~(6'd34 == add_ln1265_reg_147629) & ~(6'd12 == add_ln1265_reg_147629) & ~(6'd56 == add_ln1265_reg_147629) & ~(6'd14 == add_ln1265_reg_147629) & ~(6'd40 == add_ln1265_reg_147629) & ~(6'd16 == add_ln1265_reg_147629) & ~(6'd54 == add_ln1265_reg_147629) & ~(6'd18 == add_ln1265_reg_147629) & ~(6'd36 == add_ln1265_reg_147629) & ~(6'd20 == add_ln1265_reg_147629) & ~(6'd52 == add_ln1265_reg_147629) & ~(6'd22 == add_ln1265_reg_147629) & ~(6'd44 == add_ln1265_reg_147629) & ~(6'd24 == add_ln1265_reg_147629) & ~(6'd50 == add_ln1265_reg_147629) & ~(6'd26 == add_ln1265_reg_147629) & ~(6'd38 == add_ln1265_reg_147629) & ~(6'd28 == add_ln1265_reg_147629) & ~(6'd48 == add_ln1265_reg_147629) & ~(6'd30 == add_ln1265_reg_147629) & ~(6'd42 == add_ln1265_reg_147629) & (ap_ST_fsm_state2725 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_reg_147629) & ~(6'd62 == add_ln1265_reg_147629) & ~(6'd2 == add_ln1265_reg_147629) & ~(6'd32 == add_ln1265_reg_147629) & ~(6'd4 == add_ln1265_reg_147629) & ~(6'd60 == add_ln1265_reg_147629) & ~(6'd6 == add_ln1265_reg_147629) & ~(6'd46 == add_ln1265_reg_147629) & ~(6'd8 == add_ln1265_reg_147629) & ~(6'd58 == add_ln1265_reg_147629) & ~(6'd10 == add_ln1265_reg_147629) & ~(6'd34 == add_ln1265_reg_147629) & ~(6'd12 == add_ln1265_reg_147629) & ~(6'd56 == add_ln1265_reg_147629) & ~(6'd14 == add_ln1265_reg_147629) & ~(6'd40 == add_ln1265_reg_147629) & ~(6'd16 == add_ln1265_reg_147629) & ~(6'd54 == add_ln1265_reg_147629) & ~(6'd18 == add_ln1265_reg_147629) & ~(6'd36 == add_ln1265_reg_147629) & ~(6'd20 == add_ln1265_reg_147629) & ~(6'd52 == add_ln1265_reg_147629) & ~(6'd22 == add_ln1265_reg_147629) & ~(6'd44 == add_ln1265_reg_147629) & ~(6'd24 == add_ln1265_reg_147629) & ~(6'd50 == add_ln1265_reg_147629) & ~(6'd26 == add_ln1265_reg_147629) & ~(6'd38 == add_ln1265_reg_147629) & ~(6'd28 == add_ln1265_reg_147629) & ~(6'd48 == add_ln1265_reg_147629) & ~(6'd30 == add_ln1265_reg_147629) & ~(6'd42 == add_ln1265_reg_147629) & (ap_ST_fsm_state2648 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_reg_147629) & ~(6'd62 == add_ln1265_reg_147629) & ~(6'd2 == add_ln1265_reg_147629) & ~(6'd32 == add_ln1265_reg_147629) & ~(6'd4 == add_ln1265_reg_147629) & ~(6'd60 == add_ln1265_reg_147629) & ~(6'd6 == add_ln1265_reg_147629) & ~(6'd46 == add_ln1265_reg_147629) & ~(6'd8 == add_ln1265_reg_147629) & ~(6'd58 == add_ln1265_reg_147629) & ~(6'd10 == add_ln1265_reg_147629) & ~(6'd34 == add_ln1265_reg_147629) & ~(6'd12 == add_ln1265_reg_147629) & ~(6'd56 == add_ln1265_reg_147629) & ~(6'd14 == add_ln1265_reg_147629) & ~(6'd40 == add_ln1265_reg_147629) & ~(6'd16 == add_ln1265_reg_147629) & ~(6'd54 == add_ln1265_reg_147629) & ~(6'd18 == add_ln1265_reg_147629) & ~(6'd36 == add_ln1265_reg_147629) & ~(6'd20 == add_ln1265_reg_147629) & ~(6'd52 == add_ln1265_reg_147629) & ~(6'd22 == add_ln1265_reg_147629) & ~(6'd44 == add_ln1265_reg_147629) & ~(6'd24 == add_ln1265_reg_147629) & ~(6'd50 == add_ln1265_reg_147629) & ~(6'd26 == add_ln1265_reg_147629) & ~(6'd38 == add_ln1265_reg_147629) & ~(6'd28 == add_ln1265_reg_147629) & ~(6'd48 == add_ln1265_reg_147629) & ~(6'd30 == add_ln1265_reg_147629) & ~(6'd42 == add_ln1265_reg_147629) & (ap_ST_fsm_state2878 == ap_CS_fsm)))) begin + acc_63_V_we1 = 1'b1; + end else begin + acc_63_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_6_V_address0 = acc_6_V_addr_49_reg_162801; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_6_V_address0 = acc_6_V_addr_44_reg_162393; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_6_V_address0 = acc_6_V_addr_45_reg_157900; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_6_V_address0 = acc_6_V_addr_39_reg_157479; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_6_V_address0 = acc_6_V_addr_46_reg_152960; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_6_V_address0 = acc_6_V_addr_40_reg_152552; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_6_V_address0 = acc_6_V_addr_41_reg_148059; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_6_V_address0 = acc_6_V_addr_37_reg_147666; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2563 == ap_CS_fsm)) begin + acc_6_V_address0 = acc_6_V_addr_52_reg_146783; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_6_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2528 == ap_CS_fsm)) begin + acc_6_V_address0 = acc_6_V_addr_50_reg_146561; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_6_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2492 == ap_CS_fsm)) begin + acc_6_V_address0 = acc_6_V_addr_51_reg_146312; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_6_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2457 == ap_CS_fsm)) begin + acc_6_V_address0 = acc_6_V_addr_48_reg_146090; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_6_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_6_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_6_V_address1 = acc_6_V_addr_49_reg_162801; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_6_V_address1 = acc_6_V_addr_44_reg_162393; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_6_V_address1 = acc_6_V_addr_45_reg_157900; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_6_V_address1 = acc_6_V_addr_39_reg_157479; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_6_V_address1 = acc_6_V_addr_46_reg_152960; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_6_V_address1 = acc_6_V_addr_40_reg_152552; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_6_V_address1 = acc_6_V_addr_41_reg_148059; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_6_V_address1 = acc_6_V_addr_37_reg_147666; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd1; + end else begin + acc_6_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2563 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2528 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2492 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2457 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_6_V_ce0 = 1'b1; + end else begin + acc_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_6_V_ce1 = 1'b1; + end else begin + acc_6_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2563 == ap_CS_fsm)) begin + acc_6_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_6_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2528 == ap_CS_fsm)) begin + acc_6_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_6_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2492 == ap_CS_fsm)) begin + acc_6_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_6_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2457 == ap_CS_fsm)) begin + acc_6_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_6_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_6_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_6_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2563 == ap_CS_fsm) | (ap_ST_fsm_state2528 == ap_CS_fsm) | (ap_ST_fsm_state2492 == ap_CS_fsm) | (ap_ST_fsm_state2457 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd6 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd6 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd6 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd6 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd6 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd6 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd6 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd6 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd6 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd6 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd6 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd6 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd6 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd6 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd6 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd6 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd6 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd6 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd6 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd6 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd6 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd6 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd6 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd6 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd6 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd6 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_6_V_we0 = 1'b1; + end else begin + acc_6_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd6 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd6 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd6 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd6 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd6 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd6 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd6 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd6 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd6 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd6 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd6 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd6 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd6 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd6 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd6 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd6 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd6 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd6 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd6 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd6 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd6 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd6 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd6 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd6 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd6 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd6 == add_ln1265_reg_147629)))) begin + acc_6_V_we1 = 1'b1; + end else begin + acc_6_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_7_V_address0 = acc_7_V_addr_48_reg_162807; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_7_V_address0 = acc_7_V_addr_44_reg_162399; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_7_V_address0 = acc_7_V_addr_45_reg_157906; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_7_V_address0 = acc_7_V_addr_39_reg_157485; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_7_V_address0 = acc_7_V_addr_46_reg_152966; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_7_V_address0 = acc_7_V_addr_40_reg_152558; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_7_V_address0 = acc_7_V_addr_41_reg_148065; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_7_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_7_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_7_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_7_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_7_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_7_V_address1 = acc_7_V_addr_48_reg_162807; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_7_V_address1 = acc_7_V_addr_44_reg_162399; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_7_V_address1 = acc_7_V_addr_45_reg_157906; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_7_V_address1 = acc_7_V_addr_39_reg_157485; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_7_V_address1 = acc_7_V_addr_46_reg_152966; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_7_V_address1 = acc_7_V_addr_40_reg_152558; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_7_V_address1 = acc_7_V_addr_41_reg_148065; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_7_V_address1 = acc_7_V_addr_37_reg_147672; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd1; + end else begin + acc_7_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_7_V_ce0 = 1'b1; + end else begin + acc_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_7_V_ce1 = 1'b1; + end else begin + acc_7_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_7_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_7_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_7_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_7_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_7_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_7_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd7 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd7 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd7 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd7 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd7 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd7 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd7 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd7 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd7 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd7 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd7 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd7 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd7 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd7 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd7 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd7 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd7 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd7 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd7 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd7 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd7 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd7 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd7 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd7 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd7 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd7 == add_ln203_7_fu_116022_p2)))) begin + acc_7_V_we0 = 1'b1; + end else begin + acc_7_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd7 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd7 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd7 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd7 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd7 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd7 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd7 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd7 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd7 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd7 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd7 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd7 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd7 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd7 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd7 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd7 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd7 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd7 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd7 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd7 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd7 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd7 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd7 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd7 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd7 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd7 == add_ln1265_reg_147629)))) begin + acc_7_V_we1 = 1'b1; + end else begin + acc_7_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_8_V_address0 = acc_8_V_addr_49_reg_162813; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm))) begin + acc_8_V_address0 = acc_8_V_addr_44_reg_162405; + end else if (((ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_8_V_address0 = acc_8_V_addr_45_reg_157912; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm))) begin + acc_8_V_address0 = acc_8_V_addr_39_reg_157491; + end else if (((ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_8_V_address0 = acc_8_V_addr_46_reg_152972; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm))) begin + acc_8_V_address0 = acc_8_V_addr_40_reg_152564; + end else if (((ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_8_V_address0 = acc_8_V_addr_41_reg_148071; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm))) begin + acc_8_V_address0 = acc_8_V_addr_37_reg_147677; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2562 == ap_CS_fsm)) begin + acc_8_V_address0 = acc_8_V_addr_52_reg_146788; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_8_V_address0 = zext_ln203_15_fu_116988_p1; + end else if ((ap_ST_fsm_state2527 == ap_CS_fsm)) begin + acc_8_V_address0 = acc_8_V_addr_50_reg_146566; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_8_V_address0 = zext_ln203_10_fu_116612_p1; + end else if ((ap_ST_fsm_state2491 == ap_CS_fsm)) begin + acc_8_V_address0 = acc_8_V_addr_51_reg_146317; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_8_V_address0 = zext_ln203_12_fu_116224_p1; + end else if ((ap_ST_fsm_state2456 == ap_CS_fsm)) begin + acc_8_V_address0 = acc_8_V_addr_48_reg_146095; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_8_V_address0 = zext_ln203_8_fu_115848_p1; + end else begin + acc_8_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm))) begin + acc_8_V_address1 = acc_8_V_addr_49_reg_162813; + end else if (((ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_8_V_address1 = acc_8_V_addr_44_reg_162405; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm))) begin + acc_8_V_address1 = acc_8_V_addr_45_reg_157912; + end else if (((ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_8_V_address1 = acc_8_V_addr_39_reg_157491; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm))) begin + acc_8_V_address1 = acc_8_V_addr_46_reg_152972; + end else if (((ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_8_V_address1 = acc_8_V_addr_40_reg_152564; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm))) begin + acc_8_V_address1 = acc_8_V_addr_41_reg_148071; + end else if (((ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm))) begin + acc_8_V_address1 = acc_8_V_addr_37_reg_147677; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd1; + end else begin + acc_8_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4646 == ap_CS_fsm) | (ap_ST_fsm_state4573 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4493 == ap_CS_fsm) | (ap_ST_fsm_state4418 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state4033 == ap_CS_fsm) | (ap_ST_fsm_state3959 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3879 == ap_CS_fsm) | (ap_ST_fsm_state3804 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3418 == ap_CS_fsm) | (ap_ST_fsm_state3344 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3264 == ap_CS_fsm) | (ap_ST_fsm_state3189 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2803 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2562 == ap_CS_fsm) | (ap_ST_fsm_state2533 == ap_CS_fsm) | (ap_ST_fsm_state2527 == ap_CS_fsm) | (ap_ST_fsm_state2498 == ap_CS_fsm) | (ap_ST_fsm_state2491 == ap_CS_fsm) | (ap_ST_fsm_state2462 == ap_CS_fsm) | (ap_ST_fsm_state2456 == ap_CS_fsm) | (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + acc_8_V_ce0 = 1'b1; + end else begin + acc_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4721 == ap_CS_fsm) | (ap_ST_fsm_state4648 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4570 == ap_CS_fsm) | (ap_ST_fsm_state4495 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4108 == ap_CS_fsm) | (ap_ST_fsm_state4035 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3956 == ap_CS_fsm) | (ap_ST_fsm_state3881 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3493 == ap_CS_fsm) | (ap_ST_fsm_state3420 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3341 == ap_CS_fsm) | (ap_ST_fsm_state3266 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2878 == ap_CS_fsm) | (ap_ST_fsm_state2805 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2728 == ap_CS_fsm) | (ap_ST_fsm_state2725 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2650 == ap_CS_fsm) | (ap_ST_fsm_state2648 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2573 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_8_V_ce1 = 1'b1; + end else begin + acc_8_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4646 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_43_fu_129301_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4493 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_12_fu_128503_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state4033 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_36_fu_125833_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3879 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_8_fu_125035_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3418 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_37_fu_122259_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3264 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_9_fu_121461_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2803 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_28_fu_118791_p2; + end else if ((ap_ST_fsm_state2562 == ap_CS_fsm)) begin + acc_8_V_d0 = phi_ln203_7_reg_146727; + end else if ((ap_ST_fsm_state2533 == ap_CS_fsm)) begin + acc_8_V_d0 = phi_ln203_3_fu_116898_p18; + end else if ((ap_ST_fsm_state2527 == ap_CS_fsm)) begin + acc_8_V_d0 = phi_ln203_5_reg_146505; + end else if ((ap_ST_fsm_state2498 == ap_CS_fsm)) begin + acc_8_V_d0 = phi_ln203_1_fu_116522_p18; + end else if ((ap_ST_fsm_state2491 == ap_CS_fsm)) begin + acc_8_V_d0 = phi_ln203_6_reg_146256; + end else if ((ap_ST_fsm_state2462 == ap_CS_fsm)) begin + acc_8_V_d0 = phi_ln203_2_fu_116134_p18; + end else if ((ap_ST_fsm_state2456 == ap_CS_fsm)) begin + acc_8_V_d0 = phi_ln203_4_reg_146034; + end else if ((ap_ST_fsm_state2427 == ap_CS_fsm)) begin + acc_8_V_d0 = phi_ln_fu_115758_p18; + end else begin + acc_8_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4721 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_60_fu_129677_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4570 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_40_fu_128879_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4108 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_56_fu_126209_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3956 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_31_fu_125411_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3493 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_57_fu_122635_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3341 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_33_fu_121837_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2878 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_52_fu_119167_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2725 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_24_fu_118369_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2648 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_4_fu_117993_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_8_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2562 == ap_CS_fsm) | (ap_ST_fsm_state2527 == ap_CS_fsm) | (ap_ST_fsm_state2491 == ap_CS_fsm) | (ap_ST_fsm_state2456 == ap_CS_fsm) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd8 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd8 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4646 == ap_CS_fsm) & (6'd8 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4493 == ap_CS_fsm) & (6'd8 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd8 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd8 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd8 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd8 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4033 == ap_CS_fsm) & (6'd8 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3879 == ap_CS_fsm) & (6'd8 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd8 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd8 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd8 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd8 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3418 == ap_CS_fsm) & (6'd8 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3264 == ap_CS_fsm) & (6'd8 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd8 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd8 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd8 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd8 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2803 == ap_CS_fsm) & (6'd8 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd8 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2533 == ap_CS_fsm) & (6'd8 == add_ln203_8_fu_116969_p2) & (icmp_ln248_3_fu_116883_p2 == 1'd0)) | ((ap_ST_fsm_state2498 == ap_CS_fsm) & (6'd8 == add_ln203_5_fu_116593_p2) & (icmp_ln248_1_fu_116507_p2 == 1'd0)) | ((ap_ST_fsm_state2462 == ap_CS_fsm) & (6'd8 == add_ln203_6_fu_116205_p2) & (icmp_ln248_2_fu_116119_p2 == 1'd0)) | ((ap_ST_fsm_state2427 == ap_CS_fsm) & (6'd8 == add_ln203_4_fu_115829_p2) & (icmp_ln248_fu_115743_p2 == 1'd0)))) begin + acc_8_V_we0 = 1'b1; + end else begin + acc_8_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd8 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd8 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4570 == ap_CS_fsm) & (6'd8 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4721 == ap_CS_fsm) & (6'd8 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd8 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd8 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd8 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd8 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3956 == ap_CS_fsm) & (6'd8 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state4108 == ap_CS_fsm) & (6'd8 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd8 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd8 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd8 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd8 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3341 == ap_CS_fsm) & (6'd8 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3493 == ap_CS_fsm) & (6'd8 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd8 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd8 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd8 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd8 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2725 == ap_CS_fsm) & (6'd8 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2648 == ap_CS_fsm) & (6'd8 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2878 == ap_CS_fsm) & (6'd8 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd8 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd8 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd8 == add_ln1265_reg_147629)))) begin + acc_8_V_we1 = 1'b1; + end else begin + acc_8_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm))) begin + acc_9_V_address0 = acc_9_V_addr_48_reg_162819; + end else if (((ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm))) begin + acc_9_V_address0 = acc_9_V_addr_44_reg_162411; + end else if (((ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm))) begin + acc_9_V_address0 = acc_9_V_addr_45_reg_157918; + end else if (((ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm))) begin + acc_9_V_address0 = acc_9_V_addr_39_reg_157497; + end else if (((ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm))) begin + acc_9_V_address0 = acc_9_V_addr_46_reg_152978; + end else if (((ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm))) begin + acc_9_V_address0 = acc_9_V_addr_40_reg_152570; + end else if (((ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm))) begin + acc_9_V_address0 = acc_9_V_addr_41_reg_148077; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_9_V_address0 = zext_ln203_28_fu_117138_p1; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_9_V_address0 = zext_ln203_22_fu_116805_p1; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_9_V_address0 = zext_ln203_24_fu_116374_p1; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_9_V_address0 = zext_ln203_17_fu_116041_p1; + end else begin + acc_9_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + acc_9_V_address1 = acc_9_V_addr_48_reg_162819; + end else if (((ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm))) begin + acc_9_V_address1 = acc_9_V_addr_44_reg_162411; + end else if (((ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm))) begin + acc_9_V_address1 = acc_9_V_addr_45_reg_157918; + end else if (((ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm))) begin + acc_9_V_address1 = acc_9_V_addr_39_reg_157497; + end else if (((ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm))) begin + acc_9_V_address1 = acc_9_V_addr_46_reg_152978; + end else if (((ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm))) begin + acc_9_V_address1 = acc_9_V_addr_40_reg_152570; + end else if (((ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm))) begin + acc_9_V_address1 = acc_9_V_addr_41_reg_148077; + end else if (((ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm))) begin + acc_9_V_address1 = acc_9_V_addr_37_reg_147683; + end else if ((ap_ST_fsm_state2568 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd1; + end else begin + acc_9_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state4990 == ap_CS_fsm) | (ap_ST_fsm_state4951 == ap_CS_fsm) | (ap_ST_fsm_state4878 == ap_CS_fsm) | (ap_ST_fsm_state4838 == ap_CS_fsm) | (ap_ST_fsm_state4798 == ap_CS_fsm) | (ap_ST_fsm_state4724 == ap_CS_fsm) | (ap_ST_fsm_state4610 == ap_CS_fsm) | (ap_ST_fsm_state4456 == ap_CS_fsm) | (ap_ST_fsm_state4378 == ap_CS_fsm) | (ap_ST_fsm_state4339 == ap_CS_fsm) | (ap_ST_fsm_state4266 == ap_CS_fsm) | (ap_ST_fsm_state4226 == ap_CS_fsm) | (ap_ST_fsm_state4186 == ap_CS_fsm) | (ap_ST_fsm_state4111 == ap_CS_fsm) | (ap_ST_fsm_state3997 == ap_CS_fsm) | (ap_ST_fsm_state3842 == ap_CS_fsm) | (ap_ST_fsm_state3763 == ap_CS_fsm) | (ap_ST_fsm_state3724 == ap_CS_fsm) | (ap_ST_fsm_state3651 == ap_CS_fsm) | (ap_ST_fsm_state3611 == ap_CS_fsm) | (ap_ST_fsm_state3571 == ap_CS_fsm) | (ap_ST_fsm_state3496 == ap_CS_fsm) | (ap_ST_fsm_state3382 == ap_CS_fsm) | (ap_ST_fsm_state3227 == ap_CS_fsm) | (ap_ST_fsm_state3149 == ap_CS_fsm) | (ap_ST_fsm_state3110 == ap_CS_fsm) | (ap_ST_fsm_state3036 == ap_CS_fsm) | (ap_ST_fsm_state2996 == ap_CS_fsm) | (ap_ST_fsm_state2956 == ap_CS_fsm) | (ap_ST_fsm_state2881 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm) | (ap_ST_fsm_state2534 == ap_CS_fsm) | (ap_ST_fsm_state2499 == ap_CS_fsm) | (ap_ST_fsm_state2463 == ap_CS_fsm) | (ap_ST_fsm_state2428 == ap_CS_fsm))) begin + acc_9_V_ce0 = 1'b1; + end else begin + acc_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm) | (ap_ST_fsm_state5026 == ap_CS_fsm) | (ap_ST_fsm_state4953 == ap_CS_fsm) | (ap_ST_fsm_state4915 == ap_CS_fsm) | (ap_ST_fsm_state4875 == ap_CS_fsm) | (ap_ST_fsm_state4800 == ap_CS_fsm) | (ap_ST_fsm_state4762 == ap_CS_fsm) | (ap_ST_fsm_state4685 == ap_CS_fsm) | (ap_ST_fsm_state4533 == ap_CS_fsm) | (ap_ST_fsm_state4414 == ap_CS_fsm) | (ap_ST_fsm_state4341 == ap_CS_fsm) | (ap_ST_fsm_state4303 == ap_CS_fsm) | (ap_ST_fsm_state4263 == ap_CS_fsm) | (ap_ST_fsm_state4188 == ap_CS_fsm) | (ap_ST_fsm_state4149 == ap_CS_fsm) | (ap_ST_fsm_state4072 == ap_CS_fsm) | (ap_ST_fsm_state3919 == ap_CS_fsm) | (ap_ST_fsm_state3799 == ap_CS_fsm) | (ap_ST_fsm_state3726 == ap_CS_fsm) | (ap_ST_fsm_state3688 == ap_CS_fsm) | (ap_ST_fsm_state3648 == ap_CS_fsm) | (ap_ST_fsm_state3573 == ap_CS_fsm) | (ap_ST_fsm_state3534 == ap_CS_fsm) | (ap_ST_fsm_state3457 == ap_CS_fsm) | (ap_ST_fsm_state3304 == ap_CS_fsm) | (ap_ST_fsm_state3185 == ap_CS_fsm) | (ap_ST_fsm_state3112 == ap_CS_fsm) | (ap_ST_fsm_state3074 == ap_CS_fsm) | (ap_ST_fsm_state3033 == ap_CS_fsm) | (ap_ST_fsm_state2958 == ap_CS_fsm) | (ap_ST_fsm_state2919 == ap_CS_fsm) | (ap_ST_fsm_state2842 == ap_CS_fsm) | (ap_ST_fsm_state2766 == ap_CS_fsm) | (ap_ST_fsm_state2688 == ap_CS_fsm) | (ap_ST_fsm_state2611 == ap_CS_fsm) | (ap_ST_fsm_state2568 == ap_CS_fsm))) begin + acc_9_V_ce1 = 1'b1; + end else begin + acc_9_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4990 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_59_fu_131090_p2; + end else if ((ap_ST_fsm_state4951 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_48_fu_130925_p2; + end else if ((ap_ST_fsm_state4838 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_35_fu_130294_p2; + end else if ((ap_ST_fsm_state4798 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_17_fu_130129_p2; + end else if ((ap_ST_fsm_state4610 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_29_fu_129062_p2; + end else if ((ap_ST_fsm_state4456 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_5_fu_128253_p2; + end else if ((ap_ST_fsm_state4378 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_54_fu_127622_p2; + end else if ((ap_ST_fsm_state4339 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_44_fu_127457_p2; + end else if ((ap_ST_fsm_state4226 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_26_fu_126826_p2; + end else if ((ap_ST_fsm_state4186 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_13_fu_126661_p2; + end else if ((ap_ST_fsm_state3997 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_21_fu_125594_p2; + end else if ((ap_ST_fsm_state3842 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_1_fu_124785_p2; + end else if ((ap_ST_fsm_state3763 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_55_fu_124048_p2; + end else if ((ap_ST_fsm_state3724 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_45_fu_123883_p2; + end else if ((ap_ST_fsm_state3611 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_27_fu_123252_p2; + end else if ((ap_ST_fsm_state3571 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_14_fu_123087_p2; + end else if ((ap_ST_fsm_state3382 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_22_fu_122020_p2; + end else if ((ap_ST_fsm_state3227 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_2_fu_121211_p2; + end else if ((ap_ST_fsm_state3149 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_51_fu_120580_p2; + end else if ((ap_ST_fsm_state3110 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_38_fu_120415_p2; + end else if ((ap_ST_fsm_state2996 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_20_fu_119784_p2; + end else if ((ap_ST_fsm_state2956 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_10_fu_119619_p2; + end else if ((ap_ST_fsm_state2534 == ap_CS_fsm)) begin + acc_9_V_d0 = phi_ln203_7_fu_117050_p18; + end else if ((ap_ST_fsm_state2499 == ap_CS_fsm)) begin + acc_9_V_d0 = phi_ln203_5_fu_116717_p18; + end else if ((ap_ST_fsm_state2463 == ap_CS_fsm)) begin + acc_9_V_d0 = phi_ln203_6_fu_116286_p18; + end else if ((ap_ST_fsm_state2428 == ap_CS_fsm)) begin + acc_9_V_d0 = phi_ln203_4_fu_115953_p18; + end else begin + acc_9_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5026 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_63_fu_131300_p2; + end else if ((ap_ST_fsm_state4915 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_39_fu_130686_p2; + end else if ((ap_ST_fsm_state4875 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_47_fu_130504_p2; + end else if ((ap_ST_fsm_state4762 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_11_fu_129879_p2; + end else if ((ap_ST_fsm_state4685 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_53_fu_129467_p2; + end else if ((ap_ST_fsm_state4533 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_25_fu_128669_p2; + end else if ((ap_ST_fsm_state4414 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_61_fu_127832_p2; + end else if ((ap_ST_fsm_state4303 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_30_fu_127218_p2; + end else if ((ap_ST_fsm_state4263 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_41_fu_127036_p2; + end else if ((ap_ST_fsm_state4149 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_6_fu_126411_p2; + end else if ((ap_ST_fsm_state4072 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_49_fu_125999_p2; + end else if ((ap_ST_fsm_state3919 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_18_fu_125201_p2; + end else if ((ap_ST_fsm_state3799 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_62_fu_124258_p2; + end else if ((ap_ST_fsm_state3688 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_32_fu_123644_p2; + end else if ((ap_ST_fsm_state3648 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_42_fu_123462_p2; + end else if ((ap_ST_fsm_state3534 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_7_fu_122837_p2; + end else if ((ap_ST_fsm_state3457 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_50_fu_122425_p2; + end else if ((ap_ST_fsm_state3304 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_19_fu_121627_p2; + end else if ((ap_ST_fsm_state3185 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_58_fu_120790_p2; + end else if ((ap_ST_fsm_state3074 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_23_fu_120176_p2; + end else if ((ap_ST_fsm_state3033 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_34_fu_119994_p2; + end else if ((ap_ST_fsm_state2919 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_3_fu_119369_p2; + end else if ((ap_ST_fsm_state2842 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_46_fu_118957_p2; + end else if ((ap_ST_fsm_state2766 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_16_fu_118552_p2; + end else if ((ap_ST_fsm_state2688 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_15_fu_118159_p2; + end else if ((ap_ST_fsm_state2611 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_fu_117743_p2; + end else begin + acc_9_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4951 == ap_CS_fsm) & (6'd9 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4798 == ap_CS_fsm) & (6'd9 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4990 == ap_CS_fsm) & (6'd9 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4838 == ap_CS_fsm) & (6'd9 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4610 == ap_CS_fsm) & (6'd9 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4456 == ap_CS_fsm) & (6'd9 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4339 == ap_CS_fsm) & (6'd9 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4186 == ap_CS_fsm) & (6'd9 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4378 == ap_CS_fsm) & (6'd9 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4226 == ap_CS_fsm) & (6'd9 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state3997 == ap_CS_fsm) & (6'd9 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3842 == ap_CS_fsm) & (6'd9 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3724 == ap_CS_fsm) & (6'd9 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3571 == ap_CS_fsm) & (6'd9 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3763 == ap_CS_fsm) & (6'd9 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3611 == ap_CS_fsm) & (6'd9 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3382 == ap_CS_fsm) & (6'd9 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3227 == ap_CS_fsm) & (6'd9 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3110 == ap_CS_fsm) & (6'd9 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2956 == ap_CS_fsm) & (6'd9 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3149 == ap_CS_fsm) & (6'd9 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2996 == ap_CS_fsm) & (6'd9 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd9 == add_ln203_11_fu_117119_p2)) | ((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd9 == add_ln203_9_fu_116786_p2)) | ((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd9 == add_ln203_10_fu_116355_p2)) | ((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd9 == add_ln203_7_fu_116022_p2)))) begin + acc_9_V_we0 = 1'b1; + end else begin + acc_9_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state4875 == ap_CS_fsm) & (6'd9 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state5026 == ap_CS_fsm) & (6'd9 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4915 == ap_CS_fsm) & (6'd9 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4762 == ap_CS_fsm) & (6'd9 == add_ln1265_7_reg_162761)) | ((ap_ST_fsm_state4685 == ap_CS_fsm) & (6'd9 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4533 == ap_CS_fsm) & (6'd9 == add_ln1265_4_reg_162353)) | ((ap_ST_fsm_state4263 == ap_CS_fsm) & (6'd9 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4414 == ap_CS_fsm) & (6'd9 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4303 == ap_CS_fsm) & (6'd9 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4149 == ap_CS_fsm) & (6'd9 == add_ln1265_5_reg_157860)) | ((ap_ST_fsm_state4072 == ap_CS_fsm) & (6'd9 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3919 == ap_CS_fsm) & (6'd9 == add_ln1265_1_reg_157439)) | ((ap_ST_fsm_state3648 == ap_CS_fsm) & (6'd9 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3799 == ap_CS_fsm) & (6'd9 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3688 == ap_CS_fsm) & (6'd9 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3534 == ap_CS_fsm) & (6'd9 == add_ln1265_6_reg_152920)) | ((ap_ST_fsm_state3457 == ap_CS_fsm) & (6'd9 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3304 == ap_CS_fsm) & (6'd9 == add_ln1265_2_reg_152512)) | ((ap_ST_fsm_state3033 == ap_CS_fsm) & (6'd9 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3185 == ap_CS_fsm) & (6'd9 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state3074 == ap_CS_fsm) & (6'd9 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2919 == ap_CS_fsm) & (6'd9 == add_ln1265_3_reg_148019)) | ((ap_ST_fsm_state2842 == ap_CS_fsm) & (6'd9 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2766 == ap_CS_fsm) & (6'd9 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2688 == ap_CS_fsm) & (6'd9 == add_ln1265_reg_147629)) | ((ap_ST_fsm_state2611 == ap_CS_fsm) & (6'd9 == add_ln1265_reg_147629)))) begin + acc_9_V_we1 = 1'b1; + end else begin + acc_9_V_we1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | ((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0)))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_0_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_0_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_0_V_ce0 = 1'b1; + end else begin + data_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_100_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_100_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_100_V_ce0 = 1'b1; + end else begin + data_100_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_101_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_101_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_101_V_ce0 = 1'b1; + end else begin + data_101_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_102_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_102_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_102_V_ce0 = 1'b1; + end else begin + data_102_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_103_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_103_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_103_V_ce0 = 1'b1; + end else begin + data_103_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_104_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_104_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_104_V_ce0 = 1'b1; + end else begin + data_104_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_105_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_105_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_105_V_ce0 = 1'b1; + end else begin + data_105_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_106_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_106_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_106_V_ce0 = 1'b1; + end else begin + data_106_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_107_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_107_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_107_V_ce0 = 1'b1; + end else begin + data_107_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_108_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_108_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_108_V_ce0 = 1'b1; + end else begin + data_108_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_109_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_109_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_109_V_ce0 = 1'b1; + end else begin + data_109_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_10_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_10_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_10_V_ce0 = 1'b1; + end else begin + data_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_110_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_110_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_110_V_ce0 = 1'b1; + end else begin + data_110_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_111_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_111_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_111_V_ce0 = 1'b1; + end else begin + data_111_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_112_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_112_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_112_V_ce0 = 1'b1; + end else begin + data_112_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_113_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_113_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_113_V_ce0 = 1'b1; + end else begin + data_113_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_114_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_114_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_114_V_ce0 = 1'b1; + end else begin + data_114_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_115_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_115_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_115_V_ce0 = 1'b1; + end else begin + data_115_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_116_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_116_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_116_V_ce0 = 1'b1; + end else begin + data_116_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_117_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_117_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_117_V_ce0 = 1'b1; + end else begin + data_117_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_118_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_118_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_118_V_ce0 = 1'b1; + end else begin + data_118_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_119_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_119_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_119_V_ce0 = 1'b1; + end else begin + data_119_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_11_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_11_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_11_V_ce0 = 1'b1; + end else begin + data_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_120_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_120_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_120_V_ce0 = 1'b1; + end else begin + data_120_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_121_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_121_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_121_V_ce0 = 1'b1; + end else begin + data_121_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_122_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_122_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_122_V_ce0 = 1'b1; + end else begin + data_122_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_123_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_123_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_123_V_ce0 = 1'b1; + end else begin + data_123_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_124_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_124_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_124_V_ce0 = 1'b1; + end else begin + data_124_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_125_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_125_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_125_V_ce0 = 1'b1; + end else begin + data_125_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_126_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_126_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_126_V_ce0 = 1'b1; + end else begin + data_126_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_8_fu_104054_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_127_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_127_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_127_V_ce0 = 1'b1; + end else begin + data_127_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_12_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_12_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_12_V_ce0 = 1'b1; + end else begin + data_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_13_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_13_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_13_V_ce0 = 1'b1; + end else begin + data_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_14_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_14_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_14_V_ce0 = 1'b1; + end else begin + data_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_15_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_15_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_15_V_ce0 = 1'b1; + end else begin + data_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_16_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_16_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_16_V_ce0 = 1'b1; + end else begin + data_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_17_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_17_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_17_V_ce0 = 1'b1; + end else begin + data_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_18_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_18_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_18_V_ce0 = 1'b1; + end else begin + data_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_19_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_19_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_19_V_ce0 = 1'b1; + end else begin + data_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_1_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_1_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_1_V_ce0 = 1'b1; + end else begin + data_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_20_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_20_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_20_V_ce0 = 1'b1; + end else begin + data_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_21_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_21_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_21_V_ce0 = 1'b1; + end else begin + data_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_22_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_22_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_22_V_ce0 = 1'b1; + end else begin + data_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_23_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_23_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_23_V_ce0 = 1'b1; + end else begin + data_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_24_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_24_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_24_V_ce0 = 1'b1; + end else begin + data_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_25_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_25_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_25_V_ce0 = 1'b1; + end else begin + data_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_26_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_26_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_26_V_ce0 = 1'b1; + end else begin + data_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_27_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_27_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_27_V_ce0 = 1'b1; + end else begin + data_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_28_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_28_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_28_V_ce0 = 1'b1; + end else begin + data_28_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_29_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_29_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_29_V_ce0 = 1'b1; + end else begin + data_29_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_2_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_2_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_2_V_ce0 = 1'b1; + end else begin + data_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_30_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_30_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_30_V_ce0 = 1'b1; + end else begin + data_30_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_31_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_31_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_31_V_ce0 = 1'b1; + end else begin + data_31_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_32_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_32_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_32_V_ce0 = 1'b1; + end else begin + data_32_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_33_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_33_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_33_V_ce0 = 1'b1; + end else begin + data_33_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_34_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_34_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_34_V_ce0 = 1'b1; + end else begin + data_34_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_35_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_35_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_35_V_ce0 = 1'b1; + end else begin + data_35_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_36_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_36_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_36_V_ce0 = 1'b1; + end else begin + data_36_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_37_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_37_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_37_V_ce0 = 1'b1; + end else begin + data_37_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_38_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_38_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_38_V_ce0 = 1'b1; + end else begin + data_38_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_39_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_39_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_39_V_ce0 = 1'b1; + end else begin + data_39_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_3_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_3_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_3_V_ce0 = 1'b1; + end else begin + data_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_40_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_40_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_40_V_ce0 = 1'b1; + end else begin + data_40_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_41_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_41_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_41_V_ce0 = 1'b1; + end else begin + data_41_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_42_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_42_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_42_V_ce0 = 1'b1; + end else begin + data_42_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_43_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_43_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_43_V_ce0 = 1'b1; + end else begin + data_43_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_44_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_44_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_44_V_ce0 = 1'b1; + end else begin + data_44_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_45_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_45_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_45_V_ce0 = 1'b1; + end else begin + data_45_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_46_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_46_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_46_V_ce0 = 1'b1; + end else begin + data_46_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_47_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_47_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_47_V_ce0 = 1'b1; + end else begin + data_47_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_48_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_48_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_48_V_ce0 = 1'b1; + end else begin + data_48_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_49_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_49_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_49_V_ce0 = 1'b1; + end else begin + data_49_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_4_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_4_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_4_V_ce0 = 1'b1; + end else begin + data_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_50_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_50_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_50_V_ce0 = 1'b1; + end else begin + data_50_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_51_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_51_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_51_V_ce0 = 1'b1; + end else begin + data_51_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_52_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_52_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_52_V_ce0 = 1'b1; + end else begin + data_52_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_53_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_53_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_53_V_ce0 = 1'b1; + end else begin + data_53_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_54_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_54_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_54_V_ce0 = 1'b1; + end else begin + data_54_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_55_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_55_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_55_V_ce0 = 1'b1; + end else begin + data_55_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_56_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_56_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_56_V_ce0 = 1'b1; + end else begin + data_56_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_57_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_57_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_57_V_ce0 = 1'b1; + end else begin + data_57_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_58_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_58_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_58_V_ce0 = 1'b1; + end else begin + data_58_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_59_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_59_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_59_V_ce0 = 1'b1; + end else begin + data_59_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_5_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_5_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_5_V_ce0 = 1'b1; + end else begin + data_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_60_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_60_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_60_V_ce0 = 1'b1; + end else begin + data_60_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_61_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_61_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_61_V_ce0 = 1'b1; + end else begin + data_61_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_62_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_62_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_62_V_ce0 = 1'b1; + end else begin + data_62_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_63_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_63_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_63_V_ce0 = 1'b1; + end else begin + data_63_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_64_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_64_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_64_V_ce0 = 1'b1; + end else begin + data_64_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_65_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_65_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_65_V_ce0 = 1'b1; + end else begin + data_65_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_66_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_66_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_66_V_ce0 = 1'b1; + end else begin + data_66_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_67_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_67_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_67_V_ce0 = 1'b1; + end else begin + data_67_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_68_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_68_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_68_V_ce0 = 1'b1; + end else begin + data_68_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_69_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_69_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_69_V_ce0 = 1'b1; + end else begin + data_69_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_6_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_6_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_6_V_ce0 = 1'b1; + end else begin + data_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_70_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_70_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_70_V_ce0 = 1'b1; + end else begin + data_70_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_71_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_71_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_71_V_ce0 = 1'b1; + end else begin + data_71_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_72_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_72_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_72_V_ce0 = 1'b1; + end else begin + data_72_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_73_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_73_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_73_V_ce0 = 1'b1; + end else begin + data_73_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_74_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_74_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_74_V_ce0 = 1'b1; + end else begin + data_74_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_75_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_75_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_75_V_ce0 = 1'b1; + end else begin + data_75_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_76_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_76_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_76_V_ce0 = 1'b1; + end else begin + data_76_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_77_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_77_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_77_V_ce0 = 1'b1; + end else begin + data_77_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_78_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_78_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_78_V_ce0 = 1'b1; + end else begin + data_78_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_79_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_79_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_79_V_ce0 = 1'b1; + end else begin + data_79_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_7_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_7_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_7_V_ce0 = 1'b1; + end else begin + data_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_80_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_80_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_80_V_ce0 = 1'b1; + end else begin + data_80_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_81_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_81_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_81_V_ce0 = 1'b1; + end else begin + data_81_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_82_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_82_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_82_V_ce0 = 1'b1; + end else begin + data_82_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_83_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_83_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_83_V_ce0 = 1'b1; + end else begin + data_83_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_84_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_84_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_84_V_ce0 = 1'b1; + end else begin + data_84_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_85_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_85_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_85_V_ce0 = 1'b1; + end else begin + data_85_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_86_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_86_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_86_V_ce0 = 1'b1; + end else begin + data_86_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_87_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_87_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_87_V_ce0 = 1'b1; + end else begin + data_87_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_88_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_88_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_88_V_ce0 = 1'b1; + end else begin + data_88_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_89_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_89_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_89_V_ce0 = 1'b1; + end else begin + data_89_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_8_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_8_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_8_V_ce0 = 1'b1; + end else begin + data_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_90_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_90_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_90_V_ce0 = 1'b1; + end else begin + data_90_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_91_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_91_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_91_V_ce0 = 1'b1; + end else begin + data_91_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_92_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_92_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_92_V_ce0 = 1'b1; + end else begin + data_92_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_93_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_93_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_93_V_ce0 = 1'b1; + end else begin + data_93_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_94_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_94_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_94_V_ce0 = 1'b1; + end else begin + data_94_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_95_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_95_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_95_V_ce0 = 1'b1; + end else begin + data_95_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_96_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_96_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_96_V_ce0 = 1'b1; + end else begin + data_96_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_97_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_97_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_97_V_ce0 = 1'b1; + end else begin + data_97_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_23_fu_113798_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_14_fu_113507_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_9_fu_112919_p1; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_3_fu_112629_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_18_fu_110401_p1; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_10_fu_110109_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_5_fu_109518_p1; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_1_fu_109227_p1; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_19_fu_106955_p1; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_11_fu_106664_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_6_fu_106076_p1; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_2_fu_105786_p1; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_16_fu_103540_p1; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_7_fu_103248_p1; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_4_fu_102658_p1; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_98_V_address0 = zext_ln1116_fu_102366_p1; + end else begin + data_98_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state765 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state614 == ap_CS_fsm) | (ap_ST_fsm_state47 == ap_CS_fsm) | (ap_ST_fsm_state199 == ap_CS_fsm) | (ap_ST_fsm_state2014 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1825 == ap_CS_fsm) | (ap_ST_fsm_state160 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1371 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state1220 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm))) begin + data_98_V_ce0 = 1'b1; + end else begin + data_98_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_99_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_99_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_99_V_ce0 = 1'b1; + end else begin + data_99_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_31_fu_115392_p1; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_27_fu_115103_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_24_fu_114591_p1; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_15_fu_114302_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_29_fu_112001_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_25_fu_111711_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_20_fu_111196_p1; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_12_fu_110906_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_30_fu_108558_p1; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_26_fu_108269_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_21_fu_107757_p1; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_13_fu_107468_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_28_fu_105147_p1; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_22_fu_104857_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_17_fu_104344_p1; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + data_9_V_address0 = zext_ln1116_8_fu_104054_p1; + end else begin + data_9_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state918 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state463 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state313 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2278 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2128 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1524 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + data_9_V_ce0 = 1'b1; + end else begin + data_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2575 == ap_CS_fsm)) begin + grp_fu_117625_ap_start = 1'b1; + end else begin + grp_fu_117625_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2612 == ap_CS_fsm) & (icmp_ln268_fu_117818_p2 == 1'd0))) begin + grp_fu_117829_ap_start = 1'b1; + end else begin + grp_fu_117829_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2652 == ap_CS_fsm)) begin + grp_fu_118041_ap_start = 1'b1; + end else begin + grp_fu_118041_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2689 == ap_CS_fsm) & (icmp_ln268_8_fu_118234_p2 == 1'd0))) begin + grp_fu_118245_ap_start = 1'b1; + end else begin + grp_fu_118245_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2730 == ap_CS_fsm)) begin + grp_fu_118434_ap_start = 1'b1; + end else begin + grp_fu_118434_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2767 == ap_CS_fsm) & (icmp_ln268_9_fu_118627_p2 == 1'd0))) begin + grp_fu_118638_ap_start = 1'b1; + end else begin + grp_fu_118638_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2806 == ap_CS_fsm)) begin + grp_fu_118839_ap_start = 1'b1; + end else begin + grp_fu_118839_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2842 == ap_CS_fsm) & (icmp_ln268_24_fu_119032_p2 == 1'd0))) begin + grp_fu_119043_ap_start = 1'b1; + end else begin + grp_fu_119043_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2883 == ap_CS_fsm)) begin + grp_fu_119251_ap_start = 1'b1; + end else begin + grp_fu_119251_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2920 == ap_CS_fsm) & (icmp_ln268_3_fu_119444_p2 == 1'd0))) begin + grp_fu_119455_ap_start = 1'b1; + end else begin + grp_fu_119455_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2960 == ap_CS_fsm)) begin + grp_fu_119666_ap_start = 1'b1; + end else begin + grp_fu_119666_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2997 == ap_CS_fsm) & (icmp_ln268_12_fu_119859_p2 == 1'd0))) begin + grp_fu_119870_ap_start = 1'b1; + end else begin + grp_fu_119870_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state3038 == ap_CS_fsm)) begin + grp_fu_120058_ap_start = 1'b1; + end else begin + grp_fu_120058_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state3074 == ap_CS_fsm) & (icmp_ln268_15_fu_120251_p2 == 1'd0))) begin + grp_fu_120262_ap_start = 1'b1; + end else begin + grp_fu_120262_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state3113 == ap_CS_fsm)) begin + grp_fu_120462_ap_start = 1'b1; + end else begin + grp_fu_120462_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state3149 == ap_CS_fsm) & (icmp_ln268_27_fu_120655_p2 == 1'd0))) begin + grp_fu_120666_ap_start = 1'b1; + end else begin + grp_fu_120666_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state3191 == ap_CS_fsm)) begin + grp_fu_121093_ap_start = 1'b1; + end else begin + grp_fu_121093_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state3228 == ap_CS_fsm) & (icmp_ln268_2_fu_121286_p2 == 1'd0))) begin + grp_fu_121297_ap_start = 1'b1; + end else begin + grp_fu_121297_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state3268 == ap_CS_fsm)) begin + grp_fu_121509_ap_start = 1'b1; + end else begin + grp_fu_121509_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state3305 == ap_CS_fsm) & (icmp_ln268_11_fu_121702_p2 == 1'd0))) begin + grp_fu_121713_ap_start = 1'b1; + end else begin + grp_fu_121713_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state3346 == ap_CS_fsm)) begin + grp_fu_121902_ap_start = 1'b1; + end else begin + grp_fu_121902_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state3382 == ap_CS_fsm) & (icmp_ln268_14_fu_122095_p2 == 1'd0))) begin + grp_fu_122106_ap_start = 1'b1; + end else begin + grp_fu_122106_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state3421 == ap_CS_fsm)) begin + grp_fu_122307_ap_start = 1'b1; + end else begin + grp_fu_122307_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state3457 == ap_CS_fsm) & (icmp_ln268_26_fu_122500_p2 == 1'd0))) begin + grp_fu_122511_ap_start = 1'b1; + end else begin + grp_fu_122511_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state3498 == ap_CS_fsm)) begin + grp_fu_122719_ap_start = 1'b1; + end else begin + grp_fu_122719_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state3535 == ap_CS_fsm) & (icmp_ln268_6_fu_122912_p2 == 1'd0))) begin + grp_fu_122923_ap_start = 1'b1; + end else begin + grp_fu_122923_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state3575 == ap_CS_fsm)) begin + grp_fu_123134_ap_start = 1'b1; + end else begin + grp_fu_123134_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state3612 == ap_CS_fsm) & (icmp_ln268_18_fu_123327_p2 == 1'd0))) begin + grp_fu_123338_ap_start = 1'b1; + end else begin + grp_fu_123338_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state3652 == ap_CS_fsm)) begin + grp_fu_123526_ap_start = 1'b1; + end else begin + grp_fu_123526_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state3688 == ap_CS_fsm) & (icmp_ln268_21_fu_123719_p2 == 1'd0))) begin + grp_fu_123730_ap_start = 1'b1; + end else begin + grp_fu_123730_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state3727 == ap_CS_fsm)) begin + grp_fu_123930_ap_start = 1'b1; + end else begin + grp_fu_123930_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state3763 == ap_CS_fsm) & (icmp_ln268_30_fu_124123_p2 == 1'd0))) begin + grp_fu_124134_ap_start = 1'b1; + end else begin + grp_fu_124134_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state3806 == ap_CS_fsm)) begin + grp_fu_124667_ap_start = 1'b1; + end else begin + grp_fu_124667_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state3843 == ap_CS_fsm) & (icmp_ln268_1_fu_124860_p2 == 1'd0))) begin + grp_fu_124871_ap_start = 1'b1; + end else begin + grp_fu_124871_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state3883 == ap_CS_fsm)) begin + grp_fu_125083_ap_start = 1'b1; + end else begin + grp_fu_125083_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state3920 == ap_CS_fsm) & (icmp_ln268_10_fu_125276_p2 == 1'd0))) begin + grp_fu_125287_ap_start = 1'b1; + end else begin + grp_fu_125287_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state3961 == ap_CS_fsm)) begin + grp_fu_125476_ap_start = 1'b1; + end else begin + grp_fu_125476_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state3997 == ap_CS_fsm) & (icmp_ln268_13_fu_125669_p2 == 1'd0))) begin + grp_fu_125680_ap_start = 1'b1; + end else begin + grp_fu_125680_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4036 == ap_CS_fsm)) begin + grp_fu_125881_ap_start = 1'b1; + end else begin + grp_fu_125881_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state4072 == ap_CS_fsm) & (icmp_ln268_25_fu_126074_p2 == 1'd0))) begin + grp_fu_126085_ap_start = 1'b1; + end else begin + grp_fu_126085_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4113 == ap_CS_fsm)) begin + grp_fu_126293_ap_start = 1'b1; + end else begin + grp_fu_126293_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state4150 == ap_CS_fsm) & (icmp_ln268_5_fu_126486_p2 == 1'd0))) begin + grp_fu_126497_ap_start = 1'b1; + end else begin + grp_fu_126497_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4190 == ap_CS_fsm)) begin + grp_fu_126708_ap_start = 1'b1; + end else begin + grp_fu_126708_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state4227 == ap_CS_fsm) & (icmp_ln268_17_fu_126901_p2 == 1'd0))) begin + grp_fu_126912_ap_start = 1'b1; + end else begin + grp_fu_126912_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4267 == ap_CS_fsm)) begin + grp_fu_127100_ap_start = 1'b1; + end else begin + grp_fu_127100_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state4303 == ap_CS_fsm) & (icmp_ln268_20_fu_127293_p2 == 1'd0))) begin + grp_fu_127304_ap_start = 1'b1; + end else begin + grp_fu_127304_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4342 == ap_CS_fsm)) begin + grp_fu_127504_ap_start = 1'b1; + end else begin + grp_fu_127504_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state4378 == ap_CS_fsm) & (icmp_ln268_29_fu_127697_p2 == 1'd0))) begin + grp_fu_127708_ap_start = 1'b1; + end else begin + grp_fu_127708_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4420 == ap_CS_fsm)) begin + grp_fu_128135_ap_start = 1'b1; + end else begin + grp_fu_128135_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state4457 == ap_CS_fsm) & (icmp_ln268_4_fu_128328_p2 == 1'd0))) begin + grp_fu_128339_ap_start = 1'b1; + end else begin + grp_fu_128339_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4497 == ap_CS_fsm)) begin + grp_fu_128551_ap_start = 1'b1; + end else begin + grp_fu_128551_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state4534 == ap_CS_fsm) & (icmp_ln268_16_fu_128744_p2 == 1'd0))) begin + grp_fu_128755_ap_start = 1'b1; + end else begin + grp_fu_128755_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4574 == ap_CS_fsm)) begin + grp_fu_128944_ap_start = 1'b1; + end else begin + grp_fu_128944_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state4610 == ap_CS_fsm) & (icmp_ln268_19_fu_129137_p2 == 1'd0))) begin + grp_fu_129148_ap_start = 1'b1; + end else begin + grp_fu_129148_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4649 == ap_CS_fsm)) begin + grp_fu_129349_ap_start = 1'b1; + end else begin + grp_fu_129349_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state4685 == ap_CS_fsm) & (icmp_ln268_28_fu_129542_p2 == 1'd0))) begin + grp_fu_129553_ap_start = 1'b1; + end else begin + grp_fu_129553_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4726 == ap_CS_fsm)) begin + grp_fu_129761_ap_start = 1'b1; + end else begin + grp_fu_129761_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state4762 == ap_CS_fsm) & (icmp_ln268_7_fu_129954_p2 == 1'd0))) begin + grp_fu_129965_ap_start = 1'b1; + end else begin + grp_fu_129965_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4802 == ap_CS_fsm)) begin + grp_fu_130176_ap_start = 1'b1; + end else begin + grp_fu_130176_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state4839 == ap_CS_fsm) & (icmp_ln268_22_fu_130369_p2 == 1'd0))) begin + grp_fu_130380_ap_start = 1'b1; + end else begin + grp_fu_130380_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4879 == ap_CS_fsm)) begin + grp_fu_130568_ap_start = 1'b1; + end else begin + grp_fu_130568_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state4915 == ap_CS_fsm) & (icmp_ln268_23_fu_130761_p2 == 1'd0))) begin + grp_fu_130772_ap_start = 1'b1; + end else begin + grp_fu_130772_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4954 == ap_CS_fsm)) begin + grp_fu_130972_ap_start = 1'b1; + end else begin + grp_fu_130972_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state4990 == ap_CS_fsm) & (icmp_ln268_31_fu_131165_p2 == 1'd0))) begin + grp_fu_131176_ap_start = 1'b1; + end else begin + grp_fu_131176_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + grp_fu_99041_p1 = fw_0_0_0_0_0_0_reg_91219; + end else if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + grp_fu_99041_p1 = ap_phi_mux_fw_0_0_0_0_0_0_phi_fu_91223_p4; + end else begin + grp_fu_99041_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state11 == ap_CS_fsm) | ((ap_ST_fsm_state8 == ap_CS_fsm) & ((or_ln223_reg_131762 == 1'd1) | (or_ln223_3_fu_102310_p2 == 1'd1))))) begin + grp_fu_99047_ap_start = 1'b1; + end else begin + grp_fu_99047_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state86 == ap_CS_fsm) | ((ap_ST_fsm_state47 == ap_CS_fsm) & (((or_ln223_reg_131762 == 1'd1) & (icmp_ln208_fu_102524_p2 == 1'd0)) | ((or_ln223_9_fu_102602_p2 == 1'd1) & (icmp_ln208_fu_102524_p2 == 1'd0)))))) begin + grp_fu_99053_ap_start = 1'b1; + end else begin + grp_fu_99053_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state86 == ap_CS_fsm)) begin + grp_fu_99053_p0 = add_ln216_24_reg_132191; + end else if ((ap_ST_fsm_state47 == ap_CS_fsm)) begin + grp_fu_99053_p0 = add_ln216_24_fu_102530_p2; + end else begin + grp_fu_99053_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state163 == ap_CS_fsm)) begin + grp_fu_99058_p1 = fw_0_0_0_0_1_0_reg_91503; + end else if ((ap_ST_fsm_state160 == ap_CS_fsm)) begin + grp_fu_99058_p1 = ap_phi_mux_fw_0_0_0_0_1_0_phi_fu_91507_p4; + end else begin + grp_fu_99058_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state163 == ap_CS_fsm) | ((ap_ST_fsm_state160 == ap_CS_fsm) & ((or_ln223_8_reg_132680 == 1'd1) | (or_ln223_15_fu_103192_p2 == 1'd1))))) begin + grp_fu_99064_ap_start = 1'b1; + end else begin + grp_fu_99064_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state238 == ap_CS_fsm) | ((ap_ST_fsm_state199 == ap_CS_fsm) & (((or_ln223_28_fu_103484_p2 == 1'd1) & (icmp_ln208_4_fu_103406_p2 == 1'd0)) | ((or_ln223_8_reg_132680 == 1'd1) & (icmp_ln208_4_fu_103406_p2 == 1'd0)))))) begin + grp_fu_99070_ap_start = 1'b1; + end else begin + grp_fu_99070_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state238 == ap_CS_fsm)) begin + grp_fu_99070_p0 = add_ln216_56_reg_133087; + end else if ((ap_ST_fsm_state199 == ap_CS_fsm)) begin + grp_fu_99070_p0 = add_ln216_56_fu_103412_p2; + end else begin + grp_fu_99070_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state315 == ap_CS_fsm)) begin + grp_fu_99075_p1 = fw_0_0_0_1_0_0_reg_91799; + end else if ((ap_ST_fsm_state313 == ap_CS_fsm)) begin + grp_fu_99075_p1 = ap_phi_mux_fw_0_0_0_1_0_0_phi_fu_91803_p4; + end else begin + grp_fu_99075_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state315 == ap_CS_fsm) | ((ap_ST_fsm_state313 == ap_CS_fsm) & ((or_ln223_18_fu_103998_p2 == 1'd1) | (or_ln223_10_reg_133539 == 1'd1))))) begin + grp_fu_99081_ap_start = 1'b1; + end else begin + grp_fu_99081_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state389 == ap_CS_fsm) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (((or_ln223_30_fu_104288_p2 == 1'd1) & (icmp_ln208_5_fu_104210_p2 == 1'd0)) | ((or_ln223_10_reg_133539 == 1'd1) & (icmp_ln208_5_fu_104210_p2 == 1'd0)))))) begin + grp_fu_99087_ap_start = 1'b1; + end else begin + grp_fu_99087_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state389 == ap_CS_fsm)) begin + grp_fu_99087_p0 = add_ln216_57_reg_133959; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + grp_fu_99087_p0 = add_ln216_57_fu_104216_p2; + end else begin + grp_fu_99087_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state465 == ap_CS_fsm)) begin + grp_fu_99092_p1 = fw_0_0_0_1_1_0_reg_92079; + end else if ((ap_ST_fsm_state463 == ap_CS_fsm)) begin + grp_fu_99092_p1 = ap_phi_mux_fw_0_0_0_1_1_0_phi_fu_92083_p4; + end else begin + grp_fu_99092_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state465 == ap_CS_fsm) | ((ap_ST_fsm_state463 == ap_CS_fsm) & ((or_ln223_37_fu_104801_p2 == 1'd1) | (or_ln223_29_reg_134420 == 1'd1))))) begin + grp_fu_99098_ap_start = 1'b1; + end else begin + grp_fu_99098_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state538 == ap_CS_fsm) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (((or_ln223_44_fu_105091_p2 == 1'd1) & (icmp_ln208_12_fu_105013_p2 == 1'd0)) | ((or_ln223_29_reg_134420 == 1'd1) & (icmp_ln208_12_fu_105013_p2 == 1'd0)))))) begin + grp_fu_99104_ap_start = 1'b1; + end else begin + grp_fu_99104_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state538 == ap_CS_fsm)) begin + grp_fu_99104_p0 = add_ln216_76_reg_134834; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + grp_fu_99104_p0 = add_ln216_76_fu_105019_p2; + end else begin + grp_fu_99104_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state617 == ap_CS_fsm)) begin + grp_fu_99109_p1 = fw_0_0_1_0_0_0_reg_92405; + end else if ((ap_ST_fsm_state614 == ap_CS_fsm)) begin + grp_fu_99109_p1 = ap_phi_mux_fw_0_0_1_0_0_0_phi_fu_92409_p4; + end else begin + grp_fu_99109_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state617 == ap_CS_fsm) | ((ap_ST_fsm_state614 == ap_CS_fsm) & ((or_ln223_6_fu_105731_p2 == 1'd1) | (or_ln223_2_reg_135321 == 1'd1))))) begin + grp_fu_99115_ap_start = 1'b1; + end else begin + grp_fu_99115_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state691 == ap_CS_fsm) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (((or_ln223_14_fu_106021_p2 == 1'd1) & (icmp_ln208_2_fu_105943_p2 == 1'd0)) | ((or_ln223_2_reg_135321 == 1'd1) & (icmp_ln208_2_fu_105943_p2 == 1'd0)))))) begin + grp_fu_99121_ap_start = 1'b1; + end else begin + grp_fu_99121_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state691 == ap_CS_fsm)) begin + grp_fu_99121_p0 = add_ln216_27_reg_135762; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + grp_fu_99121_p0 = add_ln216_27_fu_105949_p2; + end else begin + grp_fu_99121_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state768 == ap_CS_fsm)) begin + grp_fu_99126_p1 = fw_0_0_1_0_1_0_reg_92689; + end else if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + grp_fu_99126_p1 = ap_phi_mux_fw_0_0_1_0_1_0_phi_fu_92693_p4; + end else begin + grp_fu_99126_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state768 == ap_CS_fsm) | ((ap_ST_fsm_state765 == ap_CS_fsm) & ((or_ln223_13_reg_136251 == 1'd1) | (or_ln223_22_fu_106609_p2 == 1'd1))))) begin + grp_fu_99132_ap_start = 1'b1; + end else begin + grp_fu_99132_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state843 == ap_CS_fsm) | ((ap_ST_fsm_state804 == ap_CS_fsm) & (((or_ln223_32_fu_106900_p2 == 1'd1) & (icmp_ln208_7_fu_106822_p2 == 1'd0)) | ((or_ln223_13_reg_136251 == 1'd1) & (icmp_ln208_7_fu_106822_p2 == 1'd0)))))) begin + grp_fu_99138_ap_start = 1'b1; + end else begin + grp_fu_99138_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state843 == ap_CS_fsm)) begin + grp_fu_99138_p0 = add_ln216_59_reg_136658; + end else if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + grp_fu_99138_p0 = add_ln216_59_fu_106828_p2; + end else begin + grp_fu_99138_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state920 == ap_CS_fsm)) begin + grp_fu_99143_p1 = fw_0_0_1_1_0_0_reg_92985; + end else if ((ap_ST_fsm_state918 == ap_CS_fsm)) begin + grp_fu_99143_p1 = ap_phi_mux_fw_0_0_1_1_0_0_phi_fu_92989_p4; + end else begin + grp_fu_99143_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state920 == ap_CS_fsm) | ((ap_ST_fsm_state918 == ap_CS_fsm) & ((or_ln223_25_fu_107413_p2 == 1'd1) | (or_ln223_17_reg_137110 == 1'd1))))) begin + grp_fu_99149_ap_start = 1'b1; + end else begin + grp_fu_99149_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state994 == ap_CS_fsm) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (((or_ln223_36_fu_107702_p2 == 1'd1) & (icmp_ln208_9_fu_107624_p2 == 1'd0)) | ((or_ln223_17_reg_137110 == 1'd1) & (icmp_ln208_9_fu_107624_p2 == 1'd0)))))) begin + grp_fu_99155_ap_start = 1'b1; + end else begin + grp_fu_99155_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state994 == ap_CS_fsm)) begin + grp_fu_99155_p0 = add_ln216_62_reg_137530; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + grp_fu_99155_p0 = add_ln216_62_fu_107630_p2; + end else begin + grp_fu_99155_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1070 == ap_CS_fsm)) begin + grp_fu_99160_p1 = fw_0_0_1_1_1_0_reg_93265; + end else if ((ap_ST_fsm_state1068 == ap_CS_fsm)) begin + grp_fu_99160_p1 = ap_phi_mux_fw_0_0_1_1_1_0_phi_fu_93269_p4; + end else begin + grp_fu_99160_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1070 == ap_CS_fsm) | ((ap_ST_fsm_state1068 == ap_CS_fsm) & ((or_ln223_42_fu_108214_p2 == 1'd1) | (or_ln223_35_reg_137991 == 1'd1))))) begin + grp_fu_99166_ap_start = 1'b1; + end else begin + grp_fu_99166_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1143 == ap_CS_fsm) | ((ap_ST_fsm_state1105 == ap_CS_fsm) & (((or_ln223_46_fu_108503_p2 == 1'd1) & (icmp_ln208_14_fu_108425_p2 == 1'd0)) | ((or_ln223_35_reg_137991 == 1'd1) & (icmp_ln208_14_fu_108425_p2 == 1'd0)))))) begin + grp_fu_99172_ap_start = 1'b1; + end else begin + grp_fu_99172_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1143 == ap_CS_fsm)) begin + grp_fu_99172_p0 = add_ln216_78_reg_138405; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + grp_fu_99172_p0 = add_ln216_78_fu_108431_p2; + end else begin + grp_fu_99172_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1223 == ap_CS_fsm)) begin + grp_fu_99177_p1 = fw_0_1_0_0_0_0_reg_93603; + end else if ((ap_ST_fsm_state1220 == ap_CS_fsm)) begin + grp_fu_99177_p1 = ap_phi_mux_fw_0_1_0_0_0_0_phi_fu_93607_p4; + end else begin + grp_fu_99177_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1223 == ap_CS_fsm) | ((ap_ST_fsm_state1220 == ap_CS_fsm) & ((or_ln223_5_fu_109171_p2 == 1'd1) | (or_ln223_1_reg_138942 == 1'd1))))) begin + grp_fu_99183_ap_start = 1'b1; + end else begin + grp_fu_99183_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1297 == ap_CS_fsm) | ((ap_ST_fsm_state1258 == ap_CS_fsm) & (((or_ln223_12_fu_109462_p2 == 1'd1) & (icmp_ln208_1_fu_109384_p2 == 1'd0)) | ((or_ln223_1_reg_138942 == 1'd1) & (icmp_ln208_1_fu_109384_p2 == 1'd0)))))) begin + grp_fu_99189_ap_start = 1'b1; + end else begin + grp_fu_99189_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + grp_fu_99189_p0 = add_ln216_26_reg_139383; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + grp_fu_99189_p0 = add_ln216_26_fu_109390_p2; + end else begin + grp_fu_99189_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1374 == ap_CS_fsm)) begin + grp_fu_99194_p1 = fw_0_1_0_0_1_0_reg_93887; + end else if ((ap_ST_fsm_state1371 == ap_CS_fsm)) begin + grp_fu_99194_p1 = ap_phi_mux_fw_0_1_0_0_1_0_phi_fu_93891_p4; + end else begin + grp_fu_99194_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1374 == ap_CS_fsm) | ((ap_ST_fsm_state1371 == ap_CS_fsm) & ((or_ln223_11_reg_139731 == 1'd1) | (or_ln223_21_fu_110053_p2 == 1'd1))))) begin + grp_fu_99200_ap_start = 1'b1; + end else begin + grp_fu_99200_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1449 == ap_CS_fsm) | ((ap_ST_fsm_state1410 == ap_CS_fsm) & (((or_ln223_31_fu_110345_p2 == 1'd1) & (icmp_ln208_6_fu_110267_p2 == 1'd0)) | ((or_ln223_11_reg_139731 == 1'd1) & (icmp_ln208_6_fu_110267_p2 == 1'd0)))))) begin + grp_fu_99206_ap_start = 1'b1; + end else begin + grp_fu_99206_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1449 == ap_CS_fsm)) begin + grp_fu_99206_p0 = add_ln216_58_reg_140265; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + grp_fu_99206_p0 = add_ln216_58_fu_110273_p2; + end else begin + grp_fu_99206_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1526 == ap_CS_fsm)) begin + grp_fu_99211_p1 = fw_0_1_0_1_0_0_reg_94183; + end else if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + grp_fu_99211_p1 = ap_phi_mux_fw_0_1_0_1_0_0_phi_fu_94187_p4; + end else begin + grp_fu_99211_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1526 == ap_CS_fsm) | ((ap_ST_fsm_state1524 == ap_CS_fsm) & ((or_ln223_24_fu_110850_p2 == 1'd1) | (or_ln223_16_reg_140696 == 1'd1))))) begin + grp_fu_99217_ap_start = 1'b1; + end else begin + grp_fu_99217_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1600 == ap_CS_fsm) | ((ap_ST_fsm_state1561 == ap_CS_fsm) & (((or_ln223_34_fu_111140_p2 == 1'd1) & (icmp_ln208_8_fu_111062_p2 == 1'd0)) | ((or_ln223_16_reg_140696 == 1'd1) & (icmp_ln208_8_fu_111062_p2 == 1'd0)))))) begin + grp_fu_99223_ap_start = 1'b1; + end else begin + grp_fu_99223_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + grp_fu_99223_p0 = add_ln216_61_reg_141132; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + grp_fu_99223_p0 = add_ln216_61_fu_111068_p2; + end else begin + grp_fu_99223_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + grp_fu_99228_p1 = fw_0_1_0_1_1_0_reg_94463; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + grp_fu_99228_p1 = ap_phi_mux_fw_0_1_0_1_1_0_phi_fu_94467_p4; + end else begin + grp_fu_99228_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1676 == ap_CS_fsm) | ((ap_ST_fsm_state1674 == ap_CS_fsm) & ((or_ln223_41_fu_111655_p2 == 1'd1) | (or_ln223_33_reg_141475 == 1'd1))))) begin + grp_fu_99234_ap_start = 1'b1; + end else begin + grp_fu_99234_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1749 == ap_CS_fsm) | ((ap_ST_fsm_state1711 == ap_CS_fsm) & (((or_ln223_45_fu_111945_p2 == 1'd1) & (icmp_ln208_13_fu_111867_p2 == 1'd0)) | ((or_ln223_33_reg_141475 == 1'd1) & (icmp_ln208_13_fu_111867_p2 == 1'd0)))))) begin + grp_fu_99240_ap_start = 1'b1; + end else begin + grp_fu_99240_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1749 == ap_CS_fsm)) begin + grp_fu_99240_p0 = add_ln216_77_reg_141997; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + grp_fu_99240_p0 = add_ln216_77_fu_111873_p2; + end else begin + grp_fu_99240_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1827 == ap_CS_fsm)) begin + grp_fu_99245_p1 = fw_0_1_1_0_0_0_reg_94789; + end else if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + grp_fu_99245_p1 = ap_phi_mux_fw_0_1_1_0_0_0_phi_fu_94793_p4; + end else begin + grp_fu_99245_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1827 == ap_CS_fsm) | ((ap_ST_fsm_state1825 == ap_CS_fsm) & ((or_ln223_7_fu_112574_p2 == 1'd1) | (or_ln223_4_reg_142485 == 1'd1))))) begin + grp_fu_99251_ap_start = 1'b1; + end else begin + grp_fu_99251_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1901 == ap_CS_fsm) | ((ap_ST_fsm_state1862 == ap_CS_fsm) & (((or_ln223_20_fu_112864_p2 == 1'd1) & (icmp_ln208_3_fu_112786_p2 == 1'd0)) | ((or_ln223_4_reg_142485 == 1'd1) & (icmp_ln208_3_fu_112786_p2 == 1'd0)))))) begin + grp_fu_99257_ap_start = 1'b1; + end else begin + grp_fu_99257_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + grp_fu_99257_p0 = add_ln216_36_reg_142926; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + grp_fu_99257_p0 = add_ln216_36_fu_112792_p2; + end else begin + grp_fu_99257_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1978 == ap_CS_fsm)) begin + grp_fu_99262_p1 = fw_0_1_1_0_1_0_reg_95073; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + grp_fu_99262_p1 = ap_phi_mux_fw_0_1_1_0_1_0_phi_fu_95077_p4; + end else begin + grp_fu_99262_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1978 == ap_CS_fsm) | ((ap_ST_fsm_state1975 == ap_CS_fsm) & ((or_ln223_19_reg_143411 == 1'd1) | (or_ln223_26_fu_113452_p2 == 1'd1))))) begin + grp_fu_99268_ap_start = 1'b1; + end else begin + grp_fu_99268_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2053 == ap_CS_fsm) | ((ap_ST_fsm_state2014 == ap_CS_fsm) & (((or_ln223_38_fu_113743_p2 == 1'd1) & (icmp_ln208_10_fu_113665_p2 == 1'd0)) | ((or_ln223_19_reg_143411 == 1'd1) & (icmp_ln208_10_fu_113665_p2 == 1'd0)))))) begin + grp_fu_99274_ap_start = 1'b1; + end else begin + grp_fu_99274_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2053 == ap_CS_fsm)) begin + grp_fu_99274_p0 = add_ln216_65_reg_143818; + end else if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + grp_fu_99274_p0 = add_ln216_65_fu_113671_p2; + end else begin + grp_fu_99274_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2130 == ap_CS_fsm)) begin + grp_fu_99279_p1 = fw_0_1_1_1_0_0_reg_95369; + end else if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + grp_fu_99279_p1 = ap_phi_mux_fw_0_1_1_1_0_0_phi_fu_95373_p4; + end else begin + grp_fu_99279_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2130 == ap_CS_fsm) | ((ap_ST_fsm_state2128 == ap_CS_fsm) & ((or_ln223_27_fu_114247_p2 == 1'd1) | (or_ln223_23_reg_144249 == 1'd1))))) begin + grp_fu_99285_ap_start = 1'b1; + end else begin + grp_fu_99285_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2204 == ap_CS_fsm) | ((ap_ST_fsm_state2165 == ap_CS_fsm) & (((or_ln223_40_fu_114536_p2 == 1'd1) & (icmp_ln208_11_fu_114458_p2 == 1'd0)) | ((or_ln223_23_reg_144249 == 1'd1) & (icmp_ln208_11_fu_114458_p2 == 1'd0)))))) begin + grp_fu_99291_ap_start = 1'b1; + end else begin + grp_fu_99291_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2204 == ap_CS_fsm)) begin + grp_fu_99291_p0 = add_ln216_68_reg_144685; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + grp_fu_99291_p0 = add_ln216_68_fu_114464_p2; + end else begin + grp_fu_99291_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2280 == ap_CS_fsm)) begin + grp_fu_99296_p1 = fw_0_1_1_1_1_0_reg_95649; + end else if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + grp_fu_99296_p1 = ap_phi_mux_fw_0_1_1_1_1_0_phi_fu_95653_p4; + end else begin + grp_fu_99296_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2280 == ap_CS_fsm) | ((ap_ST_fsm_state2278 == ap_CS_fsm) & ((or_ln223_43_fu_115048_p2 == 1'd1) | (or_ln223_39_reg_145146 == 1'd1))))) begin + grp_fu_99302_ap_start = 1'b1; + end else begin + grp_fu_99302_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2353 == ap_CS_fsm) | ((ap_ST_fsm_state2315 == ap_CS_fsm) & (((or_ln223_47_fu_115337_p2 == 1'd1) & (icmp_ln208_15_fu_115259_p2 == 1'd0)) | ((or_ln223_39_reg_145146 == 1'd1) & (icmp_ln208_15_fu_115259_p2 == 1'd0)))))) begin + grp_fu_99308_ap_start = 1'b1; + end else begin + grp_fu_99308_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2353 == ap_CS_fsm)) begin + grp_fu_99308_p0 = add_ln216_79_reg_145560; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + grp_fu_99308_p0 = add_ln216_79_fu_115265_p2; + end else begin + grp_fu_99308_p0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_0_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_0_V_ce0 = 1'b1; + end else begin + mult_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_0_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_0_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2423 == ap_CS_fsm) & (trunc_ln203_96_fu_115623_p1 == 6'd0)) | ((trunc_ln203_87_fu_115485_p1 == 6'd0) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd0) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd0) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd0) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd0) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd0) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd0) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd0) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd0) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd0) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd0) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd0) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd0) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd0) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd0) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd0) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd0) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd0) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd0) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd0) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd0) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd0) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd0) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd0) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd0) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd0) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd0) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd0)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd0)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd0)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd0)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd0)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd0)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd0)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd0)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd0)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd0)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd0)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd0)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd0)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd0)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd0)) | ((trunc_ln203_47_fu_103635_p1 == 6'd0) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd0) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd0) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd0) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd0)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd0)) | ((trunc_ln203_99_fu_115563_p1 == 6'd0) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd0) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd0) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd0) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd0) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd0) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd0) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd0) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd0) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd0) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd0) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd0) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd0) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd0) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd0) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_0_V_we0 = 1'b1; + end else begin + mult_0_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_10_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_10_V_ce0 = 1'b1; + end else begin + mult_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_10_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_10_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2423 == ap_CS_fsm) & (trunc_ln203_96_fu_115623_p1 == 6'd10)) | ((trunc_ln203_87_fu_115485_p1 == 6'd10) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd10) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd10) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd10) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd10) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd10) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd10) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd10) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd10) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd10) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd10) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd10) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd10) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd10) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd10) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd10) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd10) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd10) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd10) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd10) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd10) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd10) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd10) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd10) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd10) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd10) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd10) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd10)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd10)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd10)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd10)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd10)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd10)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd10)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd10)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd10)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd10)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd10)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd10)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd10)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd10)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd10)) | ((trunc_ln203_47_fu_103635_p1 == 6'd10) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd10) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd10) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd10) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd10)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd10)) | ((trunc_ln203_99_fu_115563_p1 == 6'd10) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd10) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd10) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd10) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd10) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd10) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd10) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd10) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd10) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd10) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd10) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd10) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd10) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd10) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd10) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_10_V_we0 = 1'b1; + end else begin + mult_10_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_11_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_11_V_ce0 = 1'b1; + end else begin + mult_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_11_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_11_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_96_fu_115623_p1 == 6'd11) & (ap_ST_fsm_state2423 == ap_CS_fsm)) | ((trunc_ln203_87_fu_115485_p1 == 6'd11) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd11) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd11) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd11) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd11) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd11) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd11) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd11) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd11) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd11) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd11) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd11) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd11) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd11) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd11) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd11) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd11) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd11) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd11) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd11) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd11) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd11) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd11) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd11) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd11) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd11) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd11) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd11)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd11)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd11)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd11)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd11)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd11)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd11)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd11)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd11)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd11)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd11)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd11)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd11)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd11)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd11)) | ((trunc_ln203_47_fu_103635_p1 == 6'd11) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd11) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd11) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd11) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd11)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd11)) | ((trunc_ln203_99_fu_115563_p1 == 6'd11) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd11) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd11) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd11) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd11) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd11) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd11) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd11) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd11) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd11) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd11) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd11) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd11) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd11) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd11) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_11_V_we0 = 1'b1; + end else begin + mult_11_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_12_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_12_V_ce0 = 1'b1; + end else begin + mult_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_12_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_12_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2423 == ap_CS_fsm) & (trunc_ln203_96_fu_115623_p1 == 6'd12)) | ((trunc_ln203_87_fu_115485_p1 == 6'd12) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd12) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd12) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd12) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd12) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd12) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd12) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd12) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd12) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd12) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd12) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd12) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd12) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd12) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd12) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd12) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd12) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd12) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd12) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd12) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd12) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd12) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd12) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd12) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd12) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd12) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd12) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd12)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd12)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd12)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd12)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd12)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd12)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd12)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd12)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd12)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd12)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd12)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd12)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd12)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd12)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd12)) | ((trunc_ln203_47_fu_103635_p1 == 6'd12) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd12) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd12) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd12) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd12)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd12)) | ((trunc_ln203_99_fu_115563_p1 == 6'd12) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd12) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd12) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd12) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd12) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd12) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd12) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd12) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd12) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd12) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd12) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd12) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd12) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd12) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd12) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_12_V_we0 = 1'b1; + end else begin + mult_12_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_13_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_13_V_ce0 = 1'b1; + end else begin + mult_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_13_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_13_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_96_fu_115623_p1 == 6'd13) & (ap_ST_fsm_state2423 == ap_CS_fsm)) | ((trunc_ln203_87_fu_115485_p1 == 6'd13) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd13) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd13) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd13) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd13) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd13) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd13) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd13) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd13) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd13) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd13) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd13) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd13) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd13) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd13) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd13) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd13) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd13) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd13) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd13) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd13) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd13) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd13) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd13) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd13) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd13) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd13) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd13)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd13)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd13)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd13)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd13)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd13)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd13)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd13)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd13)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd13)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd13)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd13)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd13)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd13)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd13)) | ((trunc_ln203_47_fu_103635_p1 == 6'd13) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd13) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd13) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd13) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd13)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd13)) | ((trunc_ln203_99_fu_115563_p1 == 6'd13) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd13) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd13) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd13) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd13) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd13) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd13) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd13) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd13) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd13) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd13) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd13) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd13) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd13) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd13) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_13_V_we0 = 1'b1; + end else begin + mult_13_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_14_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_14_V_ce0 = 1'b1; + end else begin + mult_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_14_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_14_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2423 == ap_CS_fsm) & (trunc_ln203_96_fu_115623_p1 == 6'd14)) | ((trunc_ln203_87_fu_115485_p1 == 6'd14) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd14) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd14) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd14) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd14) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd14) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd14) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd14) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd14) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd14) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd14) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd14) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd14) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd14) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd14) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd14) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd14) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd14) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd14) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd14) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd14) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd14) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd14) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd14) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd14) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd14) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd14) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd14)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd14)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd14)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd14)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd14)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd14)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd14)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd14)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd14)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd14)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd14)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd14)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd14)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd14)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd14)) | ((trunc_ln203_47_fu_103635_p1 == 6'd14) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd14) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd14) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd14) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd14)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd14)) | ((trunc_ln203_99_fu_115563_p1 == 6'd14) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd14) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd14) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd14) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd14) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd14) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd14) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd14) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd14) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd14) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd14) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd14) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd14) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd14) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd14) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_14_V_we0 = 1'b1; + end else begin + mult_14_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_15_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_15_V_ce0 = 1'b1; + end else begin + mult_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_15_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_15_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_96_fu_115623_p1 == 6'd15) & (ap_ST_fsm_state2423 == ap_CS_fsm)) | ((trunc_ln203_87_fu_115485_p1 == 6'd15) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd15) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd15) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd15) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd15) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd15) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd15) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd15) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd15) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd15) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd15) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd15) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd15) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd15) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd15) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd15) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd15) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd15) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd15) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd15) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd15) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd15) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd15) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd15) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd15) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd15) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd15) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd15)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd15)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd15)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd15)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd15)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd15)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd15)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd15)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd15)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd15)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd15)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd15)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd15)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd15)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd15)) | ((trunc_ln203_47_fu_103635_p1 == 6'd15) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd15) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd15) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd15) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd15)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd15)) | ((trunc_ln203_99_fu_115563_p1 == 6'd15) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd15) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd15) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd15) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd15) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd15) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd15) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd15) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd15) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd15) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd15) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd15) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd15) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd15) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd15) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_15_V_we0 = 1'b1; + end else begin + mult_15_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_16_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_16_V_ce0 = 1'b1; + end else begin + mult_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_16_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_16_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2423 == ap_CS_fsm) & (trunc_ln203_96_fu_115623_p1 == 6'd16)) | ((trunc_ln203_87_fu_115485_p1 == 6'd16) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd16) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd16) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd16) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd16) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd16) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd16) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd16) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd16) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd16) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd16) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd16) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd16) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd16) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd16) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd16) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd16) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd16) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd16) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd16) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd16) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd16) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd16) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd16) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd16) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd16) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd16) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd16)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd16)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd16)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd16)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd16)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd16)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd16)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd16)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd16)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd16)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd16)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd16)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd16)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd16)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd16)) | ((trunc_ln203_47_fu_103635_p1 == 6'd16) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd16) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd16) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd16) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd16)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd16)) | ((trunc_ln203_99_fu_115563_p1 == 6'd16) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd16) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd16) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd16) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd16) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd16) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd16) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd16) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd16) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd16) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd16) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd16) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd16) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd16) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd16) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_16_V_we0 = 1'b1; + end else begin + mult_16_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_17_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_17_V_ce0 = 1'b1; + end else begin + mult_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_17_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_17_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_96_fu_115623_p1 == 6'd17) & (ap_ST_fsm_state2423 == ap_CS_fsm)) | ((trunc_ln203_87_fu_115485_p1 == 6'd17) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd17) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd17) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd17) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd17) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd17) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd17) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd17) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd17) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd17) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd17) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd17) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd17) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd17) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd17) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd17) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd17) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd17) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd17) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd17) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd17) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd17) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd17) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd17) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd17) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd17) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd17) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd17)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd17)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd17)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd17)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd17)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd17)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd17)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd17)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd17)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd17)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd17)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd17)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd17)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd17)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd17)) | ((trunc_ln203_47_fu_103635_p1 == 6'd17) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd17) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd17) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd17) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd17)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd17)) | ((trunc_ln203_99_fu_115563_p1 == 6'd17) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd17) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd17) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd17) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd17) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd17) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd17) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd17) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd17) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd17) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd17) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd17) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd17) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd17) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd17) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_17_V_we0 = 1'b1; + end else begin + mult_17_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_18_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_18_V_ce0 = 1'b1; + end else begin + mult_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_18_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_18_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2423 == ap_CS_fsm) & (trunc_ln203_96_fu_115623_p1 == 6'd18)) | ((trunc_ln203_87_fu_115485_p1 == 6'd18) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd18) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd18) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd18) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd18) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd18) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd18) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd18) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd18) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd18) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd18) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd18) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd18) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd18) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd18) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd18) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd18) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd18) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd18) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd18) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd18) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd18) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd18) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd18) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd18) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd18) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd18) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd18)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd18)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd18)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd18)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd18)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd18)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd18)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd18)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd18)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd18)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd18)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd18)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd18)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd18)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd18)) | ((trunc_ln203_47_fu_103635_p1 == 6'd18) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd18) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd18) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd18) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd18)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd18)) | ((trunc_ln203_99_fu_115563_p1 == 6'd18) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd18) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd18) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd18) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd18) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd18) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd18) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd18) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd18) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd18) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd18) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd18) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd18) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd18) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd18) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_18_V_we0 = 1'b1; + end else begin + mult_18_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_19_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_19_V_ce0 = 1'b1; + end else begin + mult_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_19_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_19_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_96_fu_115623_p1 == 6'd19) & (ap_ST_fsm_state2423 == ap_CS_fsm)) | ((trunc_ln203_87_fu_115485_p1 == 6'd19) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd19) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd19) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd19) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd19) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd19) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd19) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd19) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd19) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd19) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd19) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd19) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd19) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd19) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd19) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd19) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd19) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd19) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd19) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd19) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd19) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd19) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd19) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd19) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd19) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd19) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd19) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd19)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd19)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd19)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd19)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd19)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd19)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd19)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd19)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd19)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd19)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd19)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd19)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd19)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd19)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd19)) | ((trunc_ln203_47_fu_103635_p1 == 6'd19) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd19) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd19) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd19) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd19)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd19)) | ((trunc_ln203_99_fu_115563_p1 == 6'd19) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd19) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd19) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd19) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd19) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd19) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd19) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd19) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd19) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd19) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd19) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd19) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd19) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd19) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd19) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_19_V_we0 = 1'b1; + end else begin + mult_19_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_1_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_1_V_ce0 = 1'b1; + end else begin + mult_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_1_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_1_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_96_fu_115623_p1 == 6'd1) & (ap_ST_fsm_state2423 == ap_CS_fsm)) | ((trunc_ln203_87_fu_115485_p1 == 6'd1) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd1) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd1) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd1) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd1) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd1) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd1) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd1) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd1) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd1) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd1) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd1) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd1) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd1) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd1) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd1) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd1) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd1) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd1) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd1) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd1) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd1) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd1) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd1) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd1) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd1) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd1) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd1)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd1)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd1)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd1)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd1)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd1)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd1)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd1)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd1)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd1)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd1)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd1)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd1)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd1)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd1)) | ((trunc_ln203_47_fu_103635_p1 == 6'd1) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd1) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd1) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd1) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd1)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd1)) | ((trunc_ln203_99_fu_115563_p1 == 6'd1) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd1) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd1) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd1) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd1) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd1) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd1) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd1) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd1) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd1) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd1) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd1) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd1) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd1) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd1) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_1_V_we0 = 1'b1; + end else begin + mult_1_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_20_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_20_V_ce0 = 1'b1; + end else begin + mult_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_20_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_20_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2423 == ap_CS_fsm) & (trunc_ln203_96_fu_115623_p1 == 6'd20)) | ((trunc_ln203_87_fu_115485_p1 == 6'd20) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd20) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd20) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd20) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd20) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd20) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd20) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd20) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd20) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd20) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd20) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd20) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd20) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd20) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd20) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd20) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd20) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd20) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd20) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd20) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd20) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd20) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd20) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd20) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd20) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd20) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd20) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd20)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd20)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd20)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd20)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd20)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd20)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd20)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd20)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd20)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd20)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd20)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd20)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd20)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd20)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd20)) | ((trunc_ln203_47_fu_103635_p1 == 6'd20) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd20) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd20) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd20) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd20)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd20)) | ((trunc_ln203_99_fu_115563_p1 == 6'd20) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd20) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd20) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd20) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd20) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd20) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd20) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd20) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd20) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd20) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd20) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd20) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd20) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd20) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd20) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_20_V_we0 = 1'b1; + end else begin + mult_20_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_21_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_21_V_ce0 = 1'b1; + end else begin + mult_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_21_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_21_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_96_fu_115623_p1 == 6'd21) & (ap_ST_fsm_state2423 == ap_CS_fsm)) | ((trunc_ln203_87_fu_115485_p1 == 6'd21) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd21) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd21) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd21) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd21) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd21) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd21) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd21) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd21) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd21) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd21) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd21) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd21) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd21) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd21) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd21) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd21) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd21) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd21) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd21) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd21) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd21) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd21) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd21) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd21) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd21) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd21) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd21)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd21)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd21)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd21)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd21)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd21)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd21)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd21)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd21)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd21)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd21)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd21)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd21)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd21)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd21)) | ((trunc_ln203_47_fu_103635_p1 == 6'd21) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd21) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd21) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd21) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd21)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd21)) | ((trunc_ln203_99_fu_115563_p1 == 6'd21) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd21) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd21) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd21) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd21) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd21) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd21) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd21) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd21) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd21) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd21) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd21) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd21) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd21) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd21) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_21_V_we0 = 1'b1; + end else begin + mult_21_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_22_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_22_V_ce0 = 1'b1; + end else begin + mult_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_22_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_22_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2423 == ap_CS_fsm) & (trunc_ln203_96_fu_115623_p1 == 6'd22)) | ((trunc_ln203_87_fu_115485_p1 == 6'd22) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd22) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd22) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd22) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd22) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd22) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd22) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd22) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd22) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd22) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd22) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd22) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd22) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd22) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd22) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd22) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd22) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd22) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd22) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd22) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd22) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd22) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd22) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd22) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd22) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd22) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd22) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd22)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd22)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd22)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd22)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd22)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd22)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd22)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd22)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd22)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd22)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd22)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd22)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd22)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd22)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd22)) | ((trunc_ln203_47_fu_103635_p1 == 6'd22) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd22) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd22) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd22) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd22)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd22)) | ((trunc_ln203_99_fu_115563_p1 == 6'd22) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd22) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd22) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd22) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd22) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd22) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd22) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd22) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd22) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd22) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd22) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd22) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd22) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd22) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd22) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_22_V_we0 = 1'b1; + end else begin + mult_22_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_23_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_23_V_ce0 = 1'b1; + end else begin + mult_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_23_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_23_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_96_fu_115623_p1 == 6'd23) & (ap_ST_fsm_state2423 == ap_CS_fsm)) | ((trunc_ln203_87_fu_115485_p1 == 6'd23) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd23) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd23) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd23) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd23) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd23) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd23) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd23) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd23) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd23) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd23) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd23) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd23) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd23) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd23) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd23) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd23) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd23) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd23) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd23) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd23) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd23) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd23) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd23) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd23) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd23) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd23) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd23)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd23)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd23)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd23)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd23)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd23)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd23)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd23)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd23)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd23)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd23)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd23)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd23)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd23)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd23)) | ((trunc_ln203_47_fu_103635_p1 == 6'd23) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd23) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd23) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd23) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd23)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd23)) | ((trunc_ln203_99_fu_115563_p1 == 6'd23) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd23) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd23) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd23) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd23) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd23) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd23) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd23) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd23) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd23) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd23) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd23) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd23) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd23) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd23) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_23_V_we0 = 1'b1; + end else begin + mult_23_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_24_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_24_V_ce0 = 1'b1; + end else begin + mult_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_24_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_24_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2423 == ap_CS_fsm) & (trunc_ln203_96_fu_115623_p1 == 6'd24)) | ((trunc_ln203_87_fu_115485_p1 == 6'd24) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd24) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd24) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd24) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd24) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd24) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd24) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd24) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd24) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd24) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd24) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd24) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd24) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd24) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd24) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd24) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd24) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd24) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd24) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd24) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd24) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd24) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd24) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd24) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd24) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd24) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd24) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd24)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd24)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd24)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd24)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd24)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd24)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd24)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd24)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd24)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd24)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd24)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd24)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd24)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd24)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd24)) | ((trunc_ln203_47_fu_103635_p1 == 6'd24) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd24) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd24) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd24) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd24)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd24)) | ((trunc_ln203_99_fu_115563_p1 == 6'd24) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd24) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd24) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd24) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd24) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd24) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd24) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd24) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd24) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd24) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd24) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd24) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd24) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd24) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd24) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_24_V_we0 = 1'b1; + end else begin + mult_24_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_25_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_25_V_ce0 = 1'b1; + end else begin + mult_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_25_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_25_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_96_fu_115623_p1 == 6'd25) & (ap_ST_fsm_state2423 == ap_CS_fsm)) | ((trunc_ln203_87_fu_115485_p1 == 6'd25) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd25) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd25) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd25) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd25) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd25) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd25) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd25) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd25) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd25) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd25) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd25) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd25) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd25) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd25) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd25) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd25) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd25) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd25) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd25) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd25) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd25) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd25) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd25) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd25) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd25) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd25) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd25)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd25)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd25)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd25)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd25)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd25)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd25)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd25)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd25)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd25)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd25)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd25)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd25)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd25)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd25)) | ((trunc_ln203_47_fu_103635_p1 == 6'd25) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd25) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd25) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd25) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd25)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd25)) | ((trunc_ln203_99_fu_115563_p1 == 6'd25) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd25) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd25) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd25) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd25) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd25) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd25) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd25) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd25) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd25) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd25) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd25) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd25) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd25) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd25) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_25_V_we0 = 1'b1; + end else begin + mult_25_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_26_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_26_V_ce0 = 1'b1; + end else begin + mult_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_26_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_26_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2423 == ap_CS_fsm) & (trunc_ln203_96_fu_115623_p1 == 6'd26)) | ((trunc_ln203_87_fu_115485_p1 == 6'd26) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd26) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd26) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd26) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd26) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd26) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd26) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd26) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd26) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd26) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd26) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd26) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd26) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd26) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd26) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd26) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd26) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd26) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd26) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd26) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd26) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd26) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd26) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd26) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd26) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd26) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd26) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd26)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd26)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd26)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd26)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd26)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd26)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd26)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd26)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd26)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd26)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd26)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd26)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd26)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd26)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd26)) | ((trunc_ln203_47_fu_103635_p1 == 6'd26) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd26) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd26) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd26) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd26)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd26)) | ((trunc_ln203_99_fu_115563_p1 == 6'd26) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd26) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd26) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd26) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd26) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd26) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd26) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd26) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd26) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd26) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd26) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd26) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd26) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd26) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd26) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_26_V_we0 = 1'b1; + end else begin + mult_26_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_27_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_27_V_ce0 = 1'b1; + end else begin + mult_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_27_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_27_V_d0 = 'b0; + end +end + +always @ (*) begin + if (((~(trunc_ln203_96_fu_115623_p1 == 6'd0) & ~(trunc_ln203_96_fu_115623_p1 == 6'd1) & ~(trunc_ln203_96_fu_115623_p1 == 6'd2) & ~(trunc_ln203_96_fu_115623_p1 == 6'd3) & ~(trunc_ln203_96_fu_115623_p1 == 6'd4) & ~(trunc_ln203_96_fu_115623_p1 == 6'd5) & ~(trunc_ln203_96_fu_115623_p1 == 6'd6) & ~(trunc_ln203_96_fu_115623_p1 == 6'd7) & ~(trunc_ln203_96_fu_115623_p1 == 6'd8) & ~(trunc_ln203_96_fu_115623_p1 == 6'd9) & ~(trunc_ln203_96_fu_115623_p1 == 6'd10) & ~(trunc_ln203_96_fu_115623_p1 == 6'd11) & ~(trunc_ln203_96_fu_115623_p1 == 6'd12) & ~(trunc_ln203_96_fu_115623_p1 == 6'd13) & ~(trunc_ln203_96_fu_115623_p1 == 6'd14) & ~(trunc_ln203_96_fu_115623_p1 == 6'd15) & ~(trunc_ln203_96_fu_115623_p1 == 6'd16) & ~(trunc_ln203_96_fu_115623_p1 == 6'd17) & ~(trunc_ln203_96_fu_115623_p1 == 6'd18) & ~(trunc_ln203_96_fu_115623_p1 == 6'd19) & ~(trunc_ln203_96_fu_115623_p1 == 6'd20) & ~(trunc_ln203_96_fu_115623_p1 == 6'd21) & ~(trunc_ln203_96_fu_115623_p1 == 6'd22) & ~(trunc_ln203_96_fu_115623_p1 == 6'd23) & ~(trunc_ln203_96_fu_115623_p1 == 6'd24) & ~(trunc_ln203_96_fu_115623_p1 == 6'd25) & ~(trunc_ln203_96_fu_115623_p1 == 6'd26) & (ap_ST_fsm_state2423 == ap_CS_fsm)) | (~(trunc_ln203_87_fu_115485_p1 == 6'd0) & ~(trunc_ln203_87_fu_115485_p1 == 6'd1) & ~(trunc_ln203_87_fu_115485_p1 == 6'd2) & ~(trunc_ln203_87_fu_115485_p1 == 6'd3) & ~(trunc_ln203_87_fu_115485_p1 == 6'd4) & ~(trunc_ln203_87_fu_115485_p1 == 6'd5) & ~(trunc_ln203_87_fu_115485_p1 == 6'd6) & ~(trunc_ln203_87_fu_115485_p1 == 6'd7) & ~(trunc_ln203_87_fu_115485_p1 == 6'd8) & ~(trunc_ln203_87_fu_115485_p1 == 6'd9) & ~(trunc_ln203_87_fu_115485_p1 == 6'd10) & ~(trunc_ln203_87_fu_115485_p1 == 6'd11) & ~(trunc_ln203_87_fu_115485_p1 == 6'd12) & ~(trunc_ln203_87_fu_115485_p1 == 6'd13) & ~(trunc_ln203_87_fu_115485_p1 == 6'd14) & ~(trunc_ln203_87_fu_115485_p1 == 6'd15) & ~(trunc_ln203_87_fu_115485_p1 == 6'd16) & ~(trunc_ln203_87_fu_115485_p1 == 6'd17) & ~(trunc_ln203_87_fu_115485_p1 == 6'd18) & ~(trunc_ln203_87_fu_115485_p1 == 6'd19) & ~(trunc_ln203_87_fu_115485_p1 == 6'd20) & ~(trunc_ln203_87_fu_115485_p1 == 6'd21) & ~(trunc_ln203_87_fu_115485_p1 == 6'd22) & ~(trunc_ln203_87_fu_115485_p1 == 6'd23) & ~(trunc_ln203_87_fu_115485_p1 == 6'd24) & ~(trunc_ln203_87_fu_115485_p1 == 6'd25) & ~(trunc_ln203_87_fu_115485_p1 == 6'd26) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | (~(trunc_ln203_80_fu_114937_p1 == 6'd0) & ~(trunc_ln203_80_fu_114937_p1 == 6'd1) & ~(trunc_ln203_80_fu_114937_p1 == 6'd2) & ~(trunc_ln203_80_fu_114937_p1 == 6'd3) & ~(trunc_ln203_80_fu_114937_p1 == 6'd4) & ~(trunc_ln203_80_fu_114937_p1 == 6'd5) & ~(trunc_ln203_80_fu_114937_p1 == 6'd6) & ~(trunc_ln203_80_fu_114937_p1 == 6'd7) & ~(trunc_ln203_80_fu_114937_p1 == 6'd8) & ~(trunc_ln203_80_fu_114937_p1 == 6'd9) & ~(trunc_ln203_80_fu_114937_p1 == 6'd10) & ~(trunc_ln203_80_fu_114937_p1 == 6'd11) & ~(trunc_ln203_80_fu_114937_p1 == 6'd12) & ~(trunc_ln203_80_fu_114937_p1 == 6'd13) & ~(trunc_ln203_80_fu_114937_p1 == 6'd14) & ~(trunc_ln203_80_fu_114937_p1 == 6'd15) & ~(trunc_ln203_80_fu_114937_p1 == 6'd16) & ~(trunc_ln203_80_fu_114937_p1 == 6'd17) & ~(trunc_ln203_80_fu_114937_p1 == 6'd18) & ~(trunc_ln203_80_fu_114937_p1 == 6'd19) & ~(trunc_ln203_80_fu_114937_p1 == 6'd20) & ~(trunc_ln203_80_fu_114937_p1 == 6'd21) & ~(trunc_ln203_80_fu_114937_p1 == 6'd22) & ~(trunc_ln203_80_fu_114937_p1 == 6'd23) & ~(trunc_ln203_80_fu_114937_p1 == 6'd24) & ~(trunc_ln203_80_fu_114937_p1 == 6'd25) & ~(trunc_ln203_80_fu_114937_p1 == 6'd26) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | (~(trunc_ln203_88_fu_114877_p1 == 6'd0) & ~(trunc_ln203_88_fu_114877_p1 == 6'd1) & ~(trunc_ln203_88_fu_114877_p1 == 6'd2) & ~(trunc_ln203_88_fu_114877_p1 == 6'd3) & ~(trunc_ln203_88_fu_114877_p1 == 6'd4) & ~(trunc_ln203_88_fu_114877_p1 == 6'd5) & ~(trunc_ln203_88_fu_114877_p1 == 6'd6) & ~(trunc_ln203_88_fu_114877_p1 == 6'd7) & ~(trunc_ln203_88_fu_114877_p1 == 6'd8) & ~(trunc_ln203_88_fu_114877_p1 == 6'd9) & ~(trunc_ln203_88_fu_114877_p1 == 6'd10) & ~(trunc_ln203_88_fu_114877_p1 == 6'd11) & ~(trunc_ln203_88_fu_114877_p1 == 6'd12) & ~(trunc_ln203_88_fu_114877_p1 == 6'd13) & ~(trunc_ln203_88_fu_114877_p1 == 6'd14) & ~(trunc_ln203_88_fu_114877_p1 == 6'd15) & ~(trunc_ln203_88_fu_114877_p1 == 6'd16) & ~(trunc_ln203_88_fu_114877_p1 == 6'd17) & ~(trunc_ln203_88_fu_114877_p1 == 6'd18) & ~(trunc_ln203_88_fu_114877_p1 == 6'd19) & ~(trunc_ln203_88_fu_114877_p1 == 6'd20) & ~(trunc_ln203_88_fu_114877_p1 == 6'd21) & ~(trunc_ln203_88_fu_114877_p1 == 6'd22) & ~(trunc_ln203_88_fu_114877_p1 == 6'd23) & ~(trunc_ln203_88_fu_114877_p1 == 6'd24) & ~(trunc_ln203_88_fu_114877_p1 == 6'd25) & ~(trunc_ln203_88_fu_114877_p1 == 6'd26) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | (~(trunc_ln203_63_fu_114799_p1 == 6'd0) & ~(trunc_ln203_63_fu_114799_p1 == 6'd1) & ~(trunc_ln203_63_fu_114799_p1 == 6'd2) & ~(trunc_ln203_63_fu_114799_p1 == 6'd3) & ~(trunc_ln203_63_fu_114799_p1 == 6'd4) & ~(trunc_ln203_63_fu_114799_p1 == 6'd5) & ~(trunc_ln203_63_fu_114799_p1 == 6'd6) & ~(trunc_ln203_63_fu_114799_p1 == 6'd7) & ~(trunc_ln203_63_fu_114799_p1 == 6'd8) & ~(trunc_ln203_63_fu_114799_p1 == 6'd9) & ~(trunc_ln203_63_fu_114799_p1 == 6'd10) & ~(trunc_ln203_63_fu_114799_p1 == 6'd11) & ~(trunc_ln203_63_fu_114799_p1 == 6'd12) & ~(trunc_ln203_63_fu_114799_p1 == 6'd13) & ~(trunc_ln203_63_fu_114799_p1 == 6'd14) & ~(trunc_ln203_63_fu_114799_p1 == 6'd15) & ~(trunc_ln203_63_fu_114799_p1 == 6'd16) & ~(trunc_ln203_63_fu_114799_p1 == 6'd17) & ~(trunc_ln203_63_fu_114799_p1 == 6'd18) & ~(trunc_ln203_63_fu_114799_p1 == 6'd19) & ~(trunc_ln203_63_fu_114799_p1 == 6'd20) & ~(trunc_ln203_63_fu_114799_p1 == 6'd21) & ~(trunc_ln203_63_fu_114799_p1 == 6'd22) & ~(trunc_ln203_63_fu_114799_p1 == 6'd23) & ~(trunc_ln203_63_fu_114799_p1 == 6'd24) & ~(trunc_ln203_63_fu_114799_p1 == 6'd25) & ~(trunc_ln203_63_fu_114799_p1 == 6'd26) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | (~(trunc_ln203_77_fu_114031_p1 == 6'd0) & ~(trunc_ln203_77_fu_114031_p1 == 6'd1) & ~(trunc_ln203_77_fu_114031_p1 == 6'd2) & ~(trunc_ln203_77_fu_114031_p1 == 6'd3) & ~(trunc_ln203_77_fu_114031_p1 == 6'd4) & ~(trunc_ln203_77_fu_114031_p1 == 6'd5) & ~(trunc_ln203_77_fu_114031_p1 == 6'd6) & ~(trunc_ln203_77_fu_114031_p1 == 6'd7) & ~(trunc_ln203_77_fu_114031_p1 == 6'd8) & ~(trunc_ln203_77_fu_114031_p1 == 6'd9) & ~(trunc_ln203_77_fu_114031_p1 == 6'd10) & ~(trunc_ln203_77_fu_114031_p1 == 6'd11) & ~(trunc_ln203_77_fu_114031_p1 == 6'd12) & ~(trunc_ln203_77_fu_114031_p1 == 6'd13) & ~(trunc_ln203_77_fu_114031_p1 == 6'd14) & ~(trunc_ln203_77_fu_114031_p1 == 6'd15) & ~(trunc_ln203_77_fu_114031_p1 == 6'd16) & ~(trunc_ln203_77_fu_114031_p1 == 6'd17) & ~(trunc_ln203_77_fu_114031_p1 == 6'd18) & ~(trunc_ln203_77_fu_114031_p1 == 6'd19) & ~(trunc_ln203_77_fu_114031_p1 == 6'd20) & ~(trunc_ln203_77_fu_114031_p1 == 6'd21) & ~(trunc_ln203_77_fu_114031_p1 == 6'd22) & ~(trunc_ln203_77_fu_114031_p1 == 6'd23) & ~(trunc_ln203_77_fu_114031_p1 == 6'd24) & ~(trunc_ln203_77_fu_114031_p1 == 6'd25) & ~(trunc_ln203_77_fu_114031_p1 == 6'd26) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | (~(trunc_ln203_86_fu_113971_p1 == 6'd0) & ~(trunc_ln203_86_fu_113971_p1 == 6'd1) & ~(trunc_ln203_86_fu_113971_p1 == 6'd2) & ~(trunc_ln203_86_fu_113971_p1 == 6'd3) & ~(trunc_ln203_86_fu_113971_p1 == 6'd4) & ~(trunc_ln203_86_fu_113971_p1 == 6'd5) & ~(trunc_ln203_86_fu_113971_p1 == 6'd6) & ~(trunc_ln203_86_fu_113971_p1 == 6'd7) & ~(trunc_ln203_86_fu_113971_p1 == 6'd8) & ~(trunc_ln203_86_fu_113971_p1 == 6'd9) & ~(trunc_ln203_86_fu_113971_p1 == 6'd10) & ~(trunc_ln203_86_fu_113971_p1 == 6'd11) & ~(trunc_ln203_86_fu_113971_p1 == 6'd12) & ~(trunc_ln203_86_fu_113971_p1 == 6'd13) & ~(trunc_ln203_86_fu_113971_p1 == 6'd14) & ~(trunc_ln203_86_fu_113971_p1 == 6'd15) & ~(trunc_ln203_86_fu_113971_p1 == 6'd16) & ~(trunc_ln203_86_fu_113971_p1 == 6'd17) & ~(trunc_ln203_86_fu_113971_p1 == 6'd18) & ~(trunc_ln203_86_fu_113971_p1 == 6'd19) & ~(trunc_ln203_86_fu_113971_p1 == 6'd20) & ~(trunc_ln203_86_fu_113971_p1 == 6'd21) & ~(trunc_ln203_86_fu_113971_p1 == 6'd22) & ~(trunc_ln203_86_fu_113971_p1 == 6'd23) & ~(trunc_ln203_86_fu_113971_p1 == 6'd24) & ~(trunc_ln203_86_fu_113971_p1 == 6'd25) & ~(trunc_ln203_86_fu_113971_p1 == 6'd26) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | (~(trunc_ln203_59_fu_113893_p1 == 6'd0) & ~(trunc_ln203_59_fu_113893_p1 == 6'd1) & ~(trunc_ln203_59_fu_113893_p1 == 6'd2) & ~(trunc_ln203_59_fu_113893_p1 == 6'd3) & ~(trunc_ln203_59_fu_113893_p1 == 6'd4) & ~(trunc_ln203_59_fu_113893_p1 == 6'd5) & ~(trunc_ln203_59_fu_113893_p1 == 6'd6) & ~(trunc_ln203_59_fu_113893_p1 == 6'd7) & ~(trunc_ln203_59_fu_113893_p1 == 6'd8) & ~(trunc_ln203_59_fu_113893_p1 == 6'd9) & ~(trunc_ln203_59_fu_113893_p1 == 6'd10) & ~(trunc_ln203_59_fu_113893_p1 == 6'd11) & ~(trunc_ln203_59_fu_113893_p1 == 6'd12) & ~(trunc_ln203_59_fu_113893_p1 == 6'd13) & ~(trunc_ln203_59_fu_113893_p1 == 6'd14) & ~(trunc_ln203_59_fu_113893_p1 == 6'd15) & ~(trunc_ln203_59_fu_113893_p1 == 6'd16) & ~(trunc_ln203_59_fu_113893_p1 == 6'd17) & ~(trunc_ln203_59_fu_113893_p1 == 6'd18) & ~(trunc_ln203_59_fu_113893_p1 == 6'd19) & ~(trunc_ln203_59_fu_113893_p1 == 6'd20) & ~(trunc_ln203_59_fu_113893_p1 == 6'd21) & ~(trunc_ln203_59_fu_113893_p1 == 6'd22) & ~(trunc_ln203_59_fu_113893_p1 == 6'd23) & ~(trunc_ln203_59_fu_113893_p1 == 6'd24) & ~(trunc_ln203_59_fu_113893_p1 == 6'd25) & ~(trunc_ln203_59_fu_113893_p1 == 6'd26) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | (~(trunc_ln203_66_fu_113620_p1 == 6'd0) & ~(trunc_ln203_66_fu_113620_p1 == 6'd1) & ~(trunc_ln203_66_fu_113620_p1 == 6'd2) & ~(trunc_ln203_66_fu_113620_p1 == 6'd3) & ~(trunc_ln203_66_fu_113620_p1 == 6'd4) & ~(trunc_ln203_66_fu_113620_p1 == 6'd5) & ~(trunc_ln203_66_fu_113620_p1 == 6'd6) & ~(trunc_ln203_66_fu_113620_p1 == 6'd7) & ~(trunc_ln203_66_fu_113620_p1 == 6'd8) & ~(trunc_ln203_66_fu_113620_p1 == 6'd9) & ~(trunc_ln203_66_fu_113620_p1 == 6'd10) & ~(trunc_ln203_66_fu_113620_p1 == 6'd11) & ~(trunc_ln203_66_fu_113620_p1 == 6'd12) & ~(trunc_ln203_66_fu_113620_p1 == 6'd13) & ~(trunc_ln203_66_fu_113620_p1 == 6'd14) & ~(trunc_ln203_66_fu_113620_p1 == 6'd15) & ~(trunc_ln203_66_fu_113620_p1 == 6'd16) & ~(trunc_ln203_66_fu_113620_p1 == 6'd17) & ~(trunc_ln203_66_fu_113620_p1 == 6'd18) & ~(trunc_ln203_66_fu_113620_p1 == 6'd19) & ~(trunc_ln203_66_fu_113620_p1 == 6'd20) & ~(trunc_ln203_66_fu_113620_p1 == 6'd21) & ~(trunc_ln203_66_fu_113620_p1 == 6'd22) & ~(trunc_ln203_66_fu_113620_p1 == 6'd23) & ~(trunc_ln203_66_fu_113620_p1 == 6'd24) & ~(trunc_ln203_66_fu_113620_p1 == 6'd25) & ~(trunc_ln203_66_fu_113620_p1 == 6'd26) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | (~(trunc_ln203_50_fu_113341_p1 == 6'd0) & ~(trunc_ln203_50_fu_113341_p1 == 6'd1) & ~(trunc_ln203_50_fu_113341_p1 == 6'd2) & ~(trunc_ln203_50_fu_113341_p1 == 6'd3) & ~(trunc_ln203_50_fu_113341_p1 == 6'd4) & ~(trunc_ln203_50_fu_113341_p1 == 6'd5) & ~(trunc_ln203_50_fu_113341_p1 == 6'd6) & ~(trunc_ln203_50_fu_113341_p1 == 6'd7) & ~(trunc_ln203_50_fu_113341_p1 == 6'd8) & ~(trunc_ln203_50_fu_113341_p1 == 6'd9) & ~(trunc_ln203_50_fu_113341_p1 == 6'd10) & ~(trunc_ln203_50_fu_113341_p1 == 6'd11) & ~(trunc_ln203_50_fu_113341_p1 == 6'd12) & ~(trunc_ln203_50_fu_113341_p1 == 6'd13) & ~(trunc_ln203_50_fu_113341_p1 == 6'd14) & ~(trunc_ln203_50_fu_113341_p1 == 6'd15) & ~(trunc_ln203_50_fu_113341_p1 == 6'd16) & ~(trunc_ln203_50_fu_113341_p1 == 6'd17) & ~(trunc_ln203_50_fu_113341_p1 == 6'd18) & ~(trunc_ln203_50_fu_113341_p1 == 6'd19) & ~(trunc_ln203_50_fu_113341_p1 == 6'd20) & ~(trunc_ln203_50_fu_113341_p1 == 6'd21) & ~(trunc_ln203_50_fu_113341_p1 == 6'd22) & ~(trunc_ln203_50_fu_113341_p1 == 6'd23) & ~(trunc_ln203_50_fu_113341_p1 == 6'd24) & ~(trunc_ln203_50_fu_113341_p1 == 6'd25) & ~(trunc_ln203_50_fu_113341_p1 == 6'd26) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | (~(trunc_ln203_60_fu_113281_p1 == 6'd0) & ~(trunc_ln203_60_fu_113281_p1 == 6'd1) & ~(trunc_ln203_60_fu_113281_p1 == 6'd2) & ~(trunc_ln203_60_fu_113281_p1 == 6'd3) & ~(trunc_ln203_60_fu_113281_p1 == 6'd4) & ~(trunc_ln203_60_fu_113281_p1 == 6'd5) & ~(trunc_ln203_60_fu_113281_p1 == 6'd6) & ~(trunc_ln203_60_fu_113281_p1 == 6'd7) & ~(trunc_ln203_60_fu_113281_p1 == 6'd8) & ~(trunc_ln203_60_fu_113281_p1 == 6'd9) & ~(trunc_ln203_60_fu_113281_p1 == 6'd10) & ~(trunc_ln203_60_fu_113281_p1 == 6'd11) & ~(trunc_ln203_60_fu_113281_p1 == 6'd12) & ~(trunc_ln203_60_fu_113281_p1 == 6'd13) & ~(trunc_ln203_60_fu_113281_p1 == 6'd14) & ~(trunc_ln203_60_fu_113281_p1 == 6'd15) & ~(trunc_ln203_60_fu_113281_p1 == 6'd16) & ~(trunc_ln203_60_fu_113281_p1 == 6'd17) & ~(trunc_ln203_60_fu_113281_p1 == 6'd18) & ~(trunc_ln203_60_fu_113281_p1 == 6'd19) & ~(trunc_ln203_60_fu_113281_p1 == 6'd20) & ~(trunc_ln203_60_fu_113281_p1 == 6'd21) & ~(trunc_ln203_60_fu_113281_p1 == 6'd22) & ~(trunc_ln203_60_fu_113281_p1 == 6'd23) & ~(trunc_ln203_60_fu_113281_p1 == 6'd24) & ~(trunc_ln203_60_fu_113281_p1 == 6'd25) & ~(trunc_ln203_60_fu_113281_p1 == 6'd26) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | (~(trunc_ln203_40_fu_113203_p1 == 6'd0) & ~(trunc_ln203_40_fu_113203_p1 == 6'd1) & ~(trunc_ln203_40_fu_113203_p1 == 6'd2) & ~(trunc_ln203_40_fu_113203_p1 == 6'd3) & ~(trunc_ln203_40_fu_113203_p1 == 6'd4) & ~(trunc_ln203_40_fu_113203_p1 == 6'd5) & ~(trunc_ln203_40_fu_113203_p1 == 6'd6) & ~(trunc_ln203_40_fu_113203_p1 == 6'd7) & ~(trunc_ln203_40_fu_113203_p1 == 6'd8) & ~(trunc_ln203_40_fu_113203_p1 == 6'd9) & ~(trunc_ln203_40_fu_113203_p1 == 6'd10) & ~(trunc_ln203_40_fu_113203_p1 == 6'd11) & ~(trunc_ln203_40_fu_113203_p1 == 6'd12) & ~(trunc_ln203_40_fu_113203_p1 == 6'd13) & ~(trunc_ln203_40_fu_113203_p1 == 6'd14) & ~(trunc_ln203_40_fu_113203_p1 == 6'd15) & ~(trunc_ln203_40_fu_113203_p1 == 6'd16) & ~(trunc_ln203_40_fu_113203_p1 == 6'd17) & ~(trunc_ln203_40_fu_113203_p1 == 6'd18) & ~(trunc_ln203_40_fu_113203_p1 == 6'd19) & ~(trunc_ln203_40_fu_113203_p1 == 6'd20) & ~(trunc_ln203_40_fu_113203_p1 == 6'd21) & ~(trunc_ln203_40_fu_113203_p1 == 6'd22) & ~(trunc_ln203_40_fu_113203_p1 == 6'd23) & ~(trunc_ln203_40_fu_113203_p1 == 6'd24) & ~(trunc_ln203_40_fu_113203_p1 == 6'd25) & ~(trunc_ln203_40_fu_113203_p1 == 6'd26) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | (~(trunc_ln203_93_fu_112232_p1 == 6'd0) & ~(trunc_ln203_93_fu_112232_p1 == 6'd1) & ~(trunc_ln203_93_fu_112232_p1 == 6'd2) & ~(trunc_ln203_93_fu_112232_p1 == 6'd3) & ~(trunc_ln203_93_fu_112232_p1 == 6'd4) & ~(trunc_ln203_93_fu_112232_p1 == 6'd5) & ~(trunc_ln203_93_fu_112232_p1 == 6'd6) & ~(trunc_ln203_93_fu_112232_p1 == 6'd7) & ~(trunc_ln203_93_fu_112232_p1 == 6'd8) & ~(trunc_ln203_93_fu_112232_p1 == 6'd9) & ~(trunc_ln203_93_fu_112232_p1 == 6'd10) & ~(trunc_ln203_93_fu_112232_p1 == 6'd11) & ~(trunc_ln203_93_fu_112232_p1 == 6'd12) & ~(trunc_ln203_93_fu_112232_p1 == 6'd13) & ~(trunc_ln203_93_fu_112232_p1 == 6'd14) & ~(trunc_ln203_93_fu_112232_p1 == 6'd15) & ~(trunc_ln203_93_fu_112232_p1 == 6'd16) & ~(trunc_ln203_93_fu_112232_p1 == 6'd17) & ~(trunc_ln203_93_fu_112232_p1 == 6'd18) & ~(trunc_ln203_93_fu_112232_p1 == 6'd19) & ~(trunc_ln203_93_fu_112232_p1 == 6'd20) & ~(trunc_ln203_93_fu_112232_p1 == 6'd21) & ~(trunc_ln203_93_fu_112232_p1 == 6'd22) & ~(trunc_ln203_93_fu_112232_p1 == 6'd23) & ~(trunc_ln203_93_fu_112232_p1 == 6'd24) & ~(trunc_ln203_93_fu_112232_p1 == 6'd25) & ~(trunc_ln203_93_fu_112232_p1 == 6'd26) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | (~(trunc_ln203_81_fu_112094_p1 == 6'd0) & ~(trunc_ln203_81_fu_112094_p1 == 6'd1) & ~(trunc_ln203_81_fu_112094_p1 == 6'd2) & ~(trunc_ln203_81_fu_112094_p1 == 6'd3) & ~(trunc_ln203_81_fu_112094_p1 == 6'd4) & ~(trunc_ln203_81_fu_112094_p1 == 6'd5) & ~(trunc_ln203_81_fu_112094_p1 == 6'd6) & ~(trunc_ln203_81_fu_112094_p1 == 6'd7) & ~(trunc_ln203_81_fu_112094_p1 == 6'd8) & ~(trunc_ln203_81_fu_112094_p1 == 6'd9) & ~(trunc_ln203_81_fu_112094_p1 == 6'd10) & ~(trunc_ln203_81_fu_112094_p1 == 6'd11) & ~(trunc_ln203_81_fu_112094_p1 == 6'd12) & ~(trunc_ln203_81_fu_112094_p1 == 6'd13) & ~(trunc_ln203_81_fu_112094_p1 == 6'd14) & ~(trunc_ln203_81_fu_112094_p1 == 6'd15) & ~(trunc_ln203_81_fu_112094_p1 == 6'd16) & ~(trunc_ln203_81_fu_112094_p1 == 6'd17) & ~(trunc_ln203_81_fu_112094_p1 == 6'd18) & ~(trunc_ln203_81_fu_112094_p1 == 6'd19) & ~(trunc_ln203_81_fu_112094_p1 == 6'd20) & ~(trunc_ln203_81_fu_112094_p1 == 6'd21) & ~(trunc_ln203_81_fu_112094_p1 == 6'd22) & ~(trunc_ln203_81_fu_112094_p1 == 6'd23) & ~(trunc_ln203_81_fu_112094_p1 == 6'd24) & ~(trunc_ln203_81_fu_112094_p1 == 6'd25) & ~(trunc_ln203_81_fu_112094_p1 == 6'd26) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | (~(trunc_ln203_73_fu_111548_p1 == 6'd0) & ~(trunc_ln203_73_fu_111548_p1 == 6'd1) & ~(trunc_ln203_73_fu_111548_p1 == 6'd2) & ~(trunc_ln203_73_fu_111548_p1 == 6'd3) & ~(trunc_ln203_73_fu_111548_p1 == 6'd4) & ~(trunc_ln203_73_fu_111548_p1 == 6'd5) & ~(trunc_ln203_73_fu_111548_p1 == 6'd6) & ~(trunc_ln203_73_fu_111548_p1 == 6'd7) & ~(trunc_ln203_73_fu_111548_p1 == 6'd8) & ~(trunc_ln203_73_fu_111548_p1 == 6'd9) & ~(trunc_ln203_73_fu_111548_p1 == 6'd10) & ~(trunc_ln203_73_fu_111548_p1 == 6'd11) & ~(trunc_ln203_73_fu_111548_p1 == 6'd12) & ~(trunc_ln203_73_fu_111548_p1 == 6'd13) & ~(trunc_ln203_73_fu_111548_p1 == 6'd14) & ~(trunc_ln203_73_fu_111548_p1 == 6'd15) & ~(trunc_ln203_73_fu_111548_p1 == 6'd16) & ~(trunc_ln203_73_fu_111548_p1 == 6'd17) & ~(trunc_ln203_73_fu_111548_p1 == 6'd18) & ~(trunc_ln203_73_fu_111548_p1 == 6'd19) & ~(trunc_ln203_73_fu_111548_p1 == 6'd20) & ~(trunc_ln203_73_fu_111548_p1 == 6'd21) & ~(trunc_ln203_73_fu_111548_p1 == 6'd22) & ~(trunc_ln203_73_fu_111548_p1 == 6'd23) & ~(trunc_ln203_73_fu_111548_p1 == 6'd24) & ~(trunc_ln203_73_fu_111548_p1 == 6'd25) & ~(trunc_ln203_73_fu_111548_p1 == 6'd26) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | (~(trunc_ln203_82_fu_111488_p1 == 6'd0) & ~(trunc_ln203_82_fu_111488_p1 == 6'd1) & ~(trunc_ln203_82_fu_111488_p1 == 6'd2) & ~(trunc_ln203_82_fu_111488_p1 == 6'd3) & ~(trunc_ln203_82_fu_111488_p1 == 6'd4) & ~(trunc_ln203_82_fu_111488_p1 == 6'd5) & ~(trunc_ln203_82_fu_111488_p1 == 6'd6) & ~(trunc_ln203_82_fu_111488_p1 == 6'd7) & ~(trunc_ln203_82_fu_111488_p1 == 6'd8) & ~(trunc_ln203_82_fu_111488_p1 == 6'd9) & ~(trunc_ln203_82_fu_111488_p1 == 6'd10) & ~(trunc_ln203_82_fu_111488_p1 == 6'd11) & ~(trunc_ln203_82_fu_111488_p1 == 6'd12) & ~(trunc_ln203_82_fu_111488_p1 == 6'd13) & ~(trunc_ln203_82_fu_111488_p1 == 6'd14) & ~(trunc_ln203_82_fu_111488_p1 == 6'd15) & ~(trunc_ln203_82_fu_111488_p1 == 6'd16) & ~(trunc_ln203_82_fu_111488_p1 == 6'd17) & ~(trunc_ln203_82_fu_111488_p1 == 6'd18) & ~(trunc_ln203_82_fu_111488_p1 == 6'd19) & ~(trunc_ln203_82_fu_111488_p1 == 6'd20) & ~(trunc_ln203_82_fu_111488_p1 == 6'd21) & ~(trunc_ln203_82_fu_111488_p1 == 6'd22) & ~(trunc_ln203_82_fu_111488_p1 == 6'd23) & ~(trunc_ln203_82_fu_111488_p1 == 6'd24) & ~(trunc_ln203_82_fu_111488_p1 == 6'd25) & ~(trunc_ln203_82_fu_111488_p1 == 6'd26) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | (~(trunc_ln203_56_fu_111410_p1 == 6'd0) & ~(trunc_ln203_56_fu_111410_p1 == 6'd1) & ~(trunc_ln203_56_fu_111410_p1 == 6'd2) & ~(trunc_ln203_56_fu_111410_p1 == 6'd3) & ~(trunc_ln203_56_fu_111410_p1 == 6'd4) & ~(trunc_ln203_56_fu_111410_p1 == 6'd5) & ~(trunc_ln203_56_fu_111410_p1 == 6'd6) & ~(trunc_ln203_56_fu_111410_p1 == 6'd7) & ~(trunc_ln203_56_fu_111410_p1 == 6'd8) & ~(trunc_ln203_56_fu_111410_p1 == 6'd9) & ~(trunc_ln203_56_fu_111410_p1 == 6'd10) & ~(trunc_ln203_56_fu_111410_p1 == 6'd11) & ~(trunc_ln203_56_fu_111410_p1 == 6'd12) & ~(trunc_ln203_56_fu_111410_p1 == 6'd13) & ~(trunc_ln203_56_fu_111410_p1 == 6'd14) & ~(trunc_ln203_56_fu_111410_p1 == 6'd15) & ~(trunc_ln203_56_fu_111410_p1 == 6'd16) & ~(trunc_ln203_56_fu_111410_p1 == 6'd17) & ~(trunc_ln203_56_fu_111410_p1 == 6'd18) & ~(trunc_ln203_56_fu_111410_p1 == 6'd19) & ~(trunc_ln203_56_fu_111410_p1 == 6'd20) & ~(trunc_ln203_56_fu_111410_p1 == 6'd21) & ~(trunc_ln203_56_fu_111410_p1 == 6'd22) & ~(trunc_ln203_56_fu_111410_p1 == 6'd23) & ~(trunc_ln203_56_fu_111410_p1 == 6'd24) & ~(trunc_ln203_56_fu_111410_p1 == 6'd25) & ~(trunc_ln203_56_fu_111410_p1 == 6'd26) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | (~(trunc_ln203_70_fu_110634_p1 == 6'd0) & ~(trunc_ln203_70_fu_110634_p1 == 6'd1) & ~(trunc_ln203_70_fu_110634_p1 == 6'd2) & ~(trunc_ln203_70_fu_110634_p1 == 6'd3) & ~(trunc_ln203_70_fu_110634_p1 == 6'd4) & ~(trunc_ln203_70_fu_110634_p1 == 6'd5) & ~(trunc_ln203_70_fu_110634_p1 == 6'd6) & ~(trunc_ln203_70_fu_110634_p1 == 6'd7) & ~(trunc_ln203_70_fu_110634_p1 == 6'd8) & ~(trunc_ln203_70_fu_110634_p1 == 6'd9) & ~(trunc_ln203_70_fu_110634_p1 == 6'd10) & ~(trunc_ln203_70_fu_110634_p1 == 6'd11) & ~(trunc_ln203_70_fu_110634_p1 == 6'd12) & ~(trunc_ln203_70_fu_110634_p1 == 6'd13) & ~(trunc_ln203_70_fu_110634_p1 == 6'd14) & ~(trunc_ln203_70_fu_110634_p1 == 6'd15) & ~(trunc_ln203_70_fu_110634_p1 == 6'd16) & ~(trunc_ln203_70_fu_110634_p1 == 6'd17) & ~(trunc_ln203_70_fu_110634_p1 == 6'd18) & ~(trunc_ln203_70_fu_110634_p1 == 6'd19) & ~(trunc_ln203_70_fu_110634_p1 == 6'd20) & ~(trunc_ln203_70_fu_110634_p1 == 6'd21) & ~(trunc_ln203_70_fu_110634_p1 == 6'd22) & ~(trunc_ln203_70_fu_110634_p1 == 6'd23) & ~(trunc_ln203_70_fu_110634_p1 == 6'd24) & ~(trunc_ln203_70_fu_110634_p1 == 6'd25) & ~(trunc_ln203_70_fu_110634_p1 == 6'd26) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | (~(trunc_ln203_78_fu_110574_p1 == 6'd0) & ~(trunc_ln203_78_fu_110574_p1 == 6'd1) & ~(trunc_ln203_78_fu_110574_p1 == 6'd2) & ~(trunc_ln203_78_fu_110574_p1 == 6'd3) & ~(trunc_ln203_78_fu_110574_p1 == 6'd4) & ~(trunc_ln203_78_fu_110574_p1 == 6'd5) & ~(trunc_ln203_78_fu_110574_p1 == 6'd6) & ~(trunc_ln203_78_fu_110574_p1 == 6'd7) & ~(trunc_ln203_78_fu_110574_p1 == 6'd8) & ~(trunc_ln203_78_fu_110574_p1 == 6'd9) & ~(trunc_ln203_78_fu_110574_p1 == 6'd10) & ~(trunc_ln203_78_fu_110574_p1 == 6'd11) & ~(trunc_ln203_78_fu_110574_p1 == 6'd12) & ~(trunc_ln203_78_fu_110574_p1 == 6'd13) & ~(trunc_ln203_78_fu_110574_p1 == 6'd14) & ~(trunc_ln203_78_fu_110574_p1 == 6'd15) & ~(trunc_ln203_78_fu_110574_p1 == 6'd16) & ~(trunc_ln203_78_fu_110574_p1 == 6'd17) & ~(trunc_ln203_78_fu_110574_p1 == 6'd18) & ~(trunc_ln203_78_fu_110574_p1 == 6'd19) & ~(trunc_ln203_78_fu_110574_p1 == 6'd20) & ~(trunc_ln203_78_fu_110574_p1 == 6'd21) & ~(trunc_ln203_78_fu_110574_p1 == 6'd22) & ~(trunc_ln203_78_fu_110574_p1 == 6'd23) & ~(trunc_ln203_78_fu_110574_p1 == 6'd24) & ~(trunc_ln203_78_fu_110574_p1 == 6'd25) & ~(trunc_ln203_78_fu_110574_p1 == 6'd26) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | (~(trunc_ln203_51_fu_110496_p1 == 6'd0) & ~(trunc_ln203_51_fu_110496_p1 == 6'd1) & ~(trunc_ln203_51_fu_110496_p1 == 6'd2) & ~(trunc_ln203_51_fu_110496_p1 == 6'd3) & ~(trunc_ln203_51_fu_110496_p1 == 6'd4) & ~(trunc_ln203_51_fu_110496_p1 == 6'd5) & ~(trunc_ln203_51_fu_110496_p1 == 6'd6) & ~(trunc_ln203_51_fu_110496_p1 == 6'd7) & ~(trunc_ln203_51_fu_110496_p1 == 6'd8) & ~(trunc_ln203_51_fu_110496_p1 == 6'd9) & ~(trunc_ln203_51_fu_110496_p1 == 6'd10) & ~(trunc_ln203_51_fu_110496_p1 == 6'd11) & ~(trunc_ln203_51_fu_110496_p1 == 6'd12) & ~(trunc_ln203_51_fu_110496_p1 == 6'd13) & ~(trunc_ln203_51_fu_110496_p1 == 6'd14) & ~(trunc_ln203_51_fu_110496_p1 == 6'd15) & ~(trunc_ln203_51_fu_110496_p1 == 6'd16) & ~(trunc_ln203_51_fu_110496_p1 == 6'd17) & ~(trunc_ln203_51_fu_110496_p1 == 6'd18) & ~(trunc_ln203_51_fu_110496_p1 == 6'd19) & ~(trunc_ln203_51_fu_110496_p1 == 6'd20) & ~(trunc_ln203_51_fu_110496_p1 == 6'd21) & ~(trunc_ln203_51_fu_110496_p1 == 6'd22) & ~(trunc_ln203_51_fu_110496_p1 == 6'd23) & ~(trunc_ln203_51_fu_110496_p1 == 6'd24) & ~(trunc_ln203_51_fu_110496_p1 == 6'd25) & ~(trunc_ln203_51_fu_110496_p1 == 6'd26) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | (~(trunc_ln203_61_fu_110222_p1 == 6'd0) & ~(trunc_ln203_61_fu_110222_p1 == 6'd1) & ~(trunc_ln203_61_fu_110222_p1 == 6'd2) & ~(trunc_ln203_61_fu_110222_p1 == 6'd3) & ~(trunc_ln203_61_fu_110222_p1 == 6'd4) & ~(trunc_ln203_61_fu_110222_p1 == 6'd5) & ~(trunc_ln203_61_fu_110222_p1 == 6'd6) & ~(trunc_ln203_61_fu_110222_p1 == 6'd7) & ~(trunc_ln203_61_fu_110222_p1 == 6'd8) & ~(trunc_ln203_61_fu_110222_p1 == 6'd9) & ~(trunc_ln203_61_fu_110222_p1 == 6'd10) & ~(trunc_ln203_61_fu_110222_p1 == 6'd11) & ~(trunc_ln203_61_fu_110222_p1 == 6'd12) & ~(trunc_ln203_61_fu_110222_p1 == 6'd13) & ~(trunc_ln203_61_fu_110222_p1 == 6'd14) & ~(trunc_ln203_61_fu_110222_p1 == 6'd15) & ~(trunc_ln203_61_fu_110222_p1 == 6'd16) & ~(trunc_ln203_61_fu_110222_p1 == 6'd17) & ~(trunc_ln203_61_fu_110222_p1 == 6'd18) & ~(trunc_ln203_61_fu_110222_p1 == 6'd19) & ~(trunc_ln203_61_fu_110222_p1 == 6'd20) & ~(trunc_ln203_61_fu_110222_p1 == 6'd21) & ~(trunc_ln203_61_fu_110222_p1 == 6'd22) & ~(trunc_ln203_61_fu_110222_p1 == 6'd23) & ~(trunc_ln203_61_fu_110222_p1 == 6'd24) & ~(trunc_ln203_61_fu_110222_p1 == 6'd25) & ~(trunc_ln203_61_fu_110222_p1 == 6'd26) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | (~(trunc_ln203_45_fu_109946_p1 == 6'd0) & ~(trunc_ln203_45_fu_109946_p1 == 6'd1) & ~(trunc_ln203_45_fu_109946_p1 == 6'd2) & ~(trunc_ln203_45_fu_109946_p1 == 6'd3) & ~(trunc_ln203_45_fu_109946_p1 == 6'd4) & ~(trunc_ln203_45_fu_109946_p1 == 6'd5) & ~(trunc_ln203_45_fu_109946_p1 == 6'd6) & ~(trunc_ln203_45_fu_109946_p1 == 6'd7) & ~(trunc_ln203_45_fu_109946_p1 == 6'd8) & ~(trunc_ln203_45_fu_109946_p1 == 6'd9) & ~(trunc_ln203_45_fu_109946_p1 == 6'd10) & ~(trunc_ln203_45_fu_109946_p1 == 6'd11) & ~(trunc_ln203_45_fu_109946_p1 == 6'd12) & ~(trunc_ln203_45_fu_109946_p1 == 6'd13) & ~(trunc_ln203_45_fu_109946_p1 == 6'd14) & ~(trunc_ln203_45_fu_109946_p1 == 6'd15) & ~(trunc_ln203_45_fu_109946_p1 == 6'd16) & ~(trunc_ln203_45_fu_109946_p1 == 6'd17) & ~(trunc_ln203_45_fu_109946_p1 == 6'd18) & ~(trunc_ln203_45_fu_109946_p1 == 6'd19) & ~(trunc_ln203_45_fu_109946_p1 == 6'd20) & ~(trunc_ln203_45_fu_109946_p1 == 6'd21) & ~(trunc_ln203_45_fu_109946_p1 == 6'd22) & ~(trunc_ln203_45_fu_109946_p1 == 6'd23) & ~(trunc_ln203_45_fu_109946_p1 == 6'd24) & ~(trunc_ln203_45_fu_109946_p1 == 6'd25) & ~(trunc_ln203_45_fu_109946_p1 == 6'd26) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | (~(trunc_ln203_52_fu_109886_p1 == 6'd0) & ~(trunc_ln203_52_fu_109886_p1 == 6'd1) & ~(trunc_ln203_52_fu_109886_p1 == 6'd2) & ~(trunc_ln203_52_fu_109886_p1 == 6'd3) & ~(trunc_ln203_52_fu_109886_p1 == 6'd4) & ~(trunc_ln203_52_fu_109886_p1 == 6'd5) & ~(trunc_ln203_52_fu_109886_p1 == 6'd6) & ~(trunc_ln203_52_fu_109886_p1 == 6'd7) & ~(trunc_ln203_52_fu_109886_p1 == 6'd8) & ~(trunc_ln203_52_fu_109886_p1 == 6'd9) & ~(trunc_ln203_52_fu_109886_p1 == 6'd10) & ~(trunc_ln203_52_fu_109886_p1 == 6'd11) & ~(trunc_ln203_52_fu_109886_p1 == 6'd12) & ~(trunc_ln203_52_fu_109886_p1 == 6'd13) & ~(trunc_ln203_52_fu_109886_p1 == 6'd14) & ~(trunc_ln203_52_fu_109886_p1 == 6'd15) & ~(trunc_ln203_52_fu_109886_p1 == 6'd16) & ~(trunc_ln203_52_fu_109886_p1 == 6'd17) & ~(trunc_ln203_52_fu_109886_p1 == 6'd18) & ~(trunc_ln203_52_fu_109886_p1 == 6'd19) & ~(trunc_ln203_52_fu_109886_p1 == 6'd20) & ~(trunc_ln203_52_fu_109886_p1 == 6'd21) & ~(trunc_ln203_52_fu_109886_p1 == 6'd22) & ~(trunc_ln203_52_fu_109886_p1 == 6'd23) & ~(trunc_ln203_52_fu_109886_p1 == 6'd24) & ~(trunc_ln203_52_fu_109886_p1 == 6'd25) & ~(trunc_ln203_52_fu_109886_p1 == 6'd26) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | (~(trunc_ln203_37_fu_109808_p1 == 6'd0) & ~(trunc_ln203_37_fu_109808_p1 == 6'd1) & ~(trunc_ln203_37_fu_109808_p1 == 6'd2) & ~(trunc_ln203_37_fu_109808_p1 == 6'd3) & ~(trunc_ln203_37_fu_109808_p1 == 6'd4) & ~(trunc_ln203_37_fu_109808_p1 == 6'd5) & ~(trunc_ln203_37_fu_109808_p1 == 6'd6) & ~(trunc_ln203_37_fu_109808_p1 == 6'd7) & ~(trunc_ln203_37_fu_109808_p1 == 6'd8) & ~(trunc_ln203_37_fu_109808_p1 == 6'd9) & ~(trunc_ln203_37_fu_109808_p1 == 6'd10) & ~(trunc_ln203_37_fu_109808_p1 == 6'd11) & ~(trunc_ln203_37_fu_109808_p1 == 6'd12) & ~(trunc_ln203_37_fu_109808_p1 == 6'd13) & ~(trunc_ln203_37_fu_109808_p1 == 6'd14) & ~(trunc_ln203_37_fu_109808_p1 == 6'd15) & ~(trunc_ln203_37_fu_109808_p1 == 6'd16) & ~(trunc_ln203_37_fu_109808_p1 == 6'd17) & ~(trunc_ln203_37_fu_109808_p1 == 6'd18) & ~(trunc_ln203_37_fu_109808_p1 == 6'd19) & ~(trunc_ln203_37_fu_109808_p1 == 6'd20) & ~(trunc_ln203_37_fu_109808_p1 == 6'd21) & ~(trunc_ln203_37_fu_109808_p1 == 6'd22) & ~(trunc_ln203_37_fu_109808_p1 == 6'd23) & ~(trunc_ln203_37_fu_109808_p1 == 6'd24) & ~(trunc_ln203_37_fu_109808_p1 == 6'd25) & ~(trunc_ln203_37_fu_109808_p1 == 6'd26) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | (~(trunc_ln203_94_fu_108789_p1 == 6'd0) & ~(trunc_ln203_94_fu_108789_p1 == 6'd1) & ~(trunc_ln203_94_fu_108789_p1 == 6'd2) & ~(trunc_ln203_94_fu_108789_p1 == 6'd3) & ~(trunc_ln203_94_fu_108789_p1 == 6'd4) & ~(trunc_ln203_94_fu_108789_p1 == 6'd5) & ~(trunc_ln203_94_fu_108789_p1 == 6'd6) & ~(trunc_ln203_94_fu_108789_p1 == 6'd7) & ~(trunc_ln203_94_fu_108789_p1 == 6'd8) & ~(trunc_ln203_94_fu_108789_p1 == 6'd9) & ~(trunc_ln203_94_fu_108789_p1 == 6'd10) & ~(trunc_ln203_94_fu_108789_p1 == 6'd11) & ~(trunc_ln203_94_fu_108789_p1 == 6'd12) & ~(trunc_ln203_94_fu_108789_p1 == 6'd13) & ~(trunc_ln203_94_fu_108789_p1 == 6'd14) & ~(trunc_ln203_94_fu_108789_p1 == 6'd15) & ~(trunc_ln203_94_fu_108789_p1 == 6'd16) & ~(trunc_ln203_94_fu_108789_p1 == 6'd17) & ~(trunc_ln203_94_fu_108789_p1 == 6'd18) & ~(trunc_ln203_94_fu_108789_p1 == 6'd19) & ~(trunc_ln203_94_fu_108789_p1 == 6'd20) & ~(trunc_ln203_94_fu_108789_p1 == 6'd21) & ~(trunc_ln203_94_fu_108789_p1 == 6'd22) & ~(trunc_ln203_94_fu_108789_p1 == 6'd23) & ~(trunc_ln203_94_fu_108789_p1 == 6'd24) & ~(trunc_ln203_94_fu_108789_p1 == 6'd25) & ~(trunc_ln203_94_fu_108789_p1 == 6'd26) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | (~(trunc_ln203_83_fu_108651_p1 == 6'd0) & ~(trunc_ln203_83_fu_108651_p1 == 6'd1) & ~(trunc_ln203_83_fu_108651_p1 == 6'd2) & ~(trunc_ln203_83_fu_108651_p1 == 6'd3) & ~(trunc_ln203_83_fu_108651_p1 == 6'd4) & ~(trunc_ln203_83_fu_108651_p1 == 6'd5) & ~(trunc_ln203_83_fu_108651_p1 == 6'd6) & ~(trunc_ln203_83_fu_108651_p1 == 6'd7) & ~(trunc_ln203_83_fu_108651_p1 == 6'd8) & ~(trunc_ln203_83_fu_108651_p1 == 6'd9) & ~(trunc_ln203_83_fu_108651_p1 == 6'd10) & ~(trunc_ln203_83_fu_108651_p1 == 6'd11) & ~(trunc_ln203_83_fu_108651_p1 == 6'd12) & ~(trunc_ln203_83_fu_108651_p1 == 6'd13) & ~(trunc_ln203_83_fu_108651_p1 == 6'd14) & ~(trunc_ln203_83_fu_108651_p1 == 6'd15) & ~(trunc_ln203_83_fu_108651_p1 == 6'd16) & ~(trunc_ln203_83_fu_108651_p1 == 6'd17) & ~(trunc_ln203_83_fu_108651_p1 == 6'd18) & ~(trunc_ln203_83_fu_108651_p1 == 6'd19) & ~(trunc_ln203_83_fu_108651_p1 == 6'd20) & ~(trunc_ln203_83_fu_108651_p1 == 6'd21) & ~(trunc_ln203_83_fu_108651_p1 == 6'd22) & ~(trunc_ln203_83_fu_108651_p1 == 6'd23) & ~(trunc_ln203_83_fu_108651_p1 == 6'd24) & ~(trunc_ln203_83_fu_108651_p1 == 6'd25) & ~(trunc_ln203_83_fu_108651_p1 == 6'd26) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | (~(trunc_ln203_74_fu_108103_p1 == 6'd0) & ~(trunc_ln203_74_fu_108103_p1 == 6'd1) & ~(trunc_ln203_74_fu_108103_p1 == 6'd2) & ~(trunc_ln203_74_fu_108103_p1 == 6'd3) & ~(trunc_ln203_74_fu_108103_p1 == 6'd4) & ~(trunc_ln203_74_fu_108103_p1 == 6'd5) & ~(trunc_ln203_74_fu_108103_p1 == 6'd6) & ~(trunc_ln203_74_fu_108103_p1 == 6'd7) & ~(trunc_ln203_74_fu_108103_p1 == 6'd8) & ~(trunc_ln203_74_fu_108103_p1 == 6'd9) & ~(trunc_ln203_74_fu_108103_p1 == 6'd10) & ~(trunc_ln203_74_fu_108103_p1 == 6'd11) & ~(trunc_ln203_74_fu_108103_p1 == 6'd12) & ~(trunc_ln203_74_fu_108103_p1 == 6'd13) & ~(trunc_ln203_74_fu_108103_p1 == 6'd14) & ~(trunc_ln203_74_fu_108103_p1 == 6'd15) & ~(trunc_ln203_74_fu_108103_p1 == 6'd16) & ~(trunc_ln203_74_fu_108103_p1 == 6'd17) & ~(trunc_ln203_74_fu_108103_p1 == 6'd18) & ~(trunc_ln203_74_fu_108103_p1 == 6'd19) & ~(trunc_ln203_74_fu_108103_p1 == 6'd20) & ~(trunc_ln203_74_fu_108103_p1 == 6'd21) & ~(trunc_ln203_74_fu_108103_p1 == 6'd22) & ~(trunc_ln203_74_fu_108103_p1 == 6'd23) & ~(trunc_ln203_74_fu_108103_p1 == 6'd24) & ~(trunc_ln203_74_fu_108103_p1 == 6'd25) & ~(trunc_ln203_74_fu_108103_p1 == 6'd26) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | (~(trunc_ln203_84_fu_108043_p1 == 6'd0) & ~(trunc_ln203_84_fu_108043_p1 == 6'd1) & ~(trunc_ln203_84_fu_108043_p1 == 6'd2) & ~(trunc_ln203_84_fu_108043_p1 == 6'd3) & ~(trunc_ln203_84_fu_108043_p1 == 6'd4) & ~(trunc_ln203_84_fu_108043_p1 == 6'd5) & ~(trunc_ln203_84_fu_108043_p1 == 6'd6) & ~(trunc_ln203_84_fu_108043_p1 == 6'd7) & ~(trunc_ln203_84_fu_108043_p1 == 6'd8) & ~(trunc_ln203_84_fu_108043_p1 == 6'd9) & ~(trunc_ln203_84_fu_108043_p1 == 6'd10) & ~(trunc_ln203_84_fu_108043_p1 == 6'd11) & ~(trunc_ln203_84_fu_108043_p1 == 6'd12) & ~(trunc_ln203_84_fu_108043_p1 == 6'd13) & ~(trunc_ln203_84_fu_108043_p1 == 6'd14) & ~(trunc_ln203_84_fu_108043_p1 == 6'd15) & ~(trunc_ln203_84_fu_108043_p1 == 6'd16) & ~(trunc_ln203_84_fu_108043_p1 == 6'd17) & ~(trunc_ln203_84_fu_108043_p1 == 6'd18) & ~(trunc_ln203_84_fu_108043_p1 == 6'd19) & ~(trunc_ln203_84_fu_108043_p1 == 6'd20) & ~(trunc_ln203_84_fu_108043_p1 == 6'd21) & ~(trunc_ln203_84_fu_108043_p1 == 6'd22) & ~(trunc_ln203_84_fu_108043_p1 == 6'd23) & ~(trunc_ln203_84_fu_108043_p1 == 6'd24) & ~(trunc_ln203_84_fu_108043_p1 == 6'd25) & ~(trunc_ln203_84_fu_108043_p1 == 6'd26) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | (~(trunc_ln203_57_fu_107965_p1 == 6'd0) & ~(trunc_ln203_57_fu_107965_p1 == 6'd1) & ~(trunc_ln203_57_fu_107965_p1 == 6'd2) & ~(trunc_ln203_57_fu_107965_p1 == 6'd3) & ~(trunc_ln203_57_fu_107965_p1 == 6'd4) & ~(trunc_ln203_57_fu_107965_p1 == 6'd5) & ~(trunc_ln203_57_fu_107965_p1 == 6'd6) & ~(trunc_ln203_57_fu_107965_p1 == 6'd7) & ~(trunc_ln203_57_fu_107965_p1 == 6'd8) & ~(trunc_ln203_57_fu_107965_p1 == 6'd9) & ~(trunc_ln203_57_fu_107965_p1 == 6'd10) & ~(trunc_ln203_57_fu_107965_p1 == 6'd11) & ~(trunc_ln203_57_fu_107965_p1 == 6'd12) & ~(trunc_ln203_57_fu_107965_p1 == 6'd13) & ~(trunc_ln203_57_fu_107965_p1 == 6'd14) & ~(trunc_ln203_57_fu_107965_p1 == 6'd15) & ~(trunc_ln203_57_fu_107965_p1 == 6'd16) & ~(trunc_ln203_57_fu_107965_p1 == 6'd17) & ~(trunc_ln203_57_fu_107965_p1 == 6'd18) & ~(trunc_ln203_57_fu_107965_p1 == 6'd19) & ~(trunc_ln203_57_fu_107965_p1 == 6'd20) & ~(trunc_ln203_57_fu_107965_p1 == 6'd21) & ~(trunc_ln203_57_fu_107965_p1 == 6'd22) & ~(trunc_ln203_57_fu_107965_p1 == 6'd23) & ~(trunc_ln203_57_fu_107965_p1 == 6'd24) & ~(trunc_ln203_57_fu_107965_p1 == 6'd25) & ~(trunc_ln203_57_fu_107965_p1 == 6'd26) & (ap_ST_fsm_state990 == ap_CS_fsm)) | (~(trunc_ln203_71_fu_107188_p1 == 6'd0) & ~(trunc_ln203_71_fu_107188_p1 == 6'd1) & ~(trunc_ln203_71_fu_107188_p1 == 6'd2) & ~(trunc_ln203_71_fu_107188_p1 == 6'd3) & ~(trunc_ln203_71_fu_107188_p1 == 6'd4) & ~(trunc_ln203_71_fu_107188_p1 == 6'd5) & ~(trunc_ln203_71_fu_107188_p1 == 6'd6) & ~(trunc_ln203_71_fu_107188_p1 == 6'd7) & ~(trunc_ln203_71_fu_107188_p1 == 6'd8) & ~(trunc_ln203_71_fu_107188_p1 == 6'd9) & ~(trunc_ln203_71_fu_107188_p1 == 6'd10) & ~(trunc_ln203_71_fu_107188_p1 == 6'd11) & ~(trunc_ln203_71_fu_107188_p1 == 6'd12) & ~(trunc_ln203_71_fu_107188_p1 == 6'd13) & ~(trunc_ln203_71_fu_107188_p1 == 6'd14) & ~(trunc_ln203_71_fu_107188_p1 == 6'd15) & ~(trunc_ln203_71_fu_107188_p1 == 6'd16) & ~(trunc_ln203_71_fu_107188_p1 == 6'd17) & ~(trunc_ln203_71_fu_107188_p1 == 6'd18) & ~(trunc_ln203_71_fu_107188_p1 == 6'd19) & ~(trunc_ln203_71_fu_107188_p1 == 6'd20) & ~(trunc_ln203_71_fu_107188_p1 == 6'd21) & ~(trunc_ln203_71_fu_107188_p1 == 6'd22) & ~(trunc_ln203_71_fu_107188_p1 == 6'd23) & ~(trunc_ln203_71_fu_107188_p1 == 6'd24) & ~(trunc_ln203_71_fu_107188_p1 == 6'd25) & ~(trunc_ln203_71_fu_107188_p1 == 6'd26) & (ap_ST_fsm_state914 == ap_CS_fsm)) | (~(trunc_ln203_79_fu_107128_p1 == 6'd0) & ~(trunc_ln203_79_fu_107128_p1 == 6'd1) & ~(trunc_ln203_79_fu_107128_p1 == 6'd2) & ~(trunc_ln203_79_fu_107128_p1 == 6'd3) & ~(trunc_ln203_79_fu_107128_p1 == 6'd4) & ~(trunc_ln203_79_fu_107128_p1 == 6'd5) & ~(trunc_ln203_79_fu_107128_p1 == 6'd6) & ~(trunc_ln203_79_fu_107128_p1 == 6'd7) & ~(trunc_ln203_79_fu_107128_p1 == 6'd8) & ~(trunc_ln203_79_fu_107128_p1 == 6'd9) & ~(trunc_ln203_79_fu_107128_p1 == 6'd10) & ~(trunc_ln203_79_fu_107128_p1 == 6'd11) & ~(trunc_ln203_79_fu_107128_p1 == 6'd12) & ~(trunc_ln203_79_fu_107128_p1 == 6'd13) & ~(trunc_ln203_79_fu_107128_p1 == 6'd14) & ~(trunc_ln203_79_fu_107128_p1 == 6'd15) & ~(trunc_ln203_79_fu_107128_p1 == 6'd16) & ~(trunc_ln203_79_fu_107128_p1 == 6'd17) & ~(trunc_ln203_79_fu_107128_p1 == 6'd18) & ~(trunc_ln203_79_fu_107128_p1 == 6'd19) & ~(trunc_ln203_79_fu_107128_p1 == 6'd20) & ~(trunc_ln203_79_fu_107128_p1 == 6'd21) & ~(trunc_ln203_79_fu_107128_p1 == 6'd22) & ~(trunc_ln203_79_fu_107128_p1 == 6'd23) & ~(trunc_ln203_79_fu_107128_p1 == 6'd24) & ~(trunc_ln203_79_fu_107128_p1 == 6'd25) & ~(trunc_ln203_79_fu_107128_p1 == 6'd26) & (ap_ST_fsm_state878 == ap_CS_fsm)) | (~(trunc_ln203_53_fu_107050_p1 == 6'd0) & ~(trunc_ln203_53_fu_107050_p1 == 6'd1) & ~(trunc_ln203_53_fu_107050_p1 == 6'd2) & ~(trunc_ln203_53_fu_107050_p1 == 6'd3) & ~(trunc_ln203_53_fu_107050_p1 == 6'd4) & ~(trunc_ln203_53_fu_107050_p1 == 6'd5) & ~(trunc_ln203_53_fu_107050_p1 == 6'd6) & ~(trunc_ln203_53_fu_107050_p1 == 6'd7) & ~(trunc_ln203_53_fu_107050_p1 == 6'd8) & ~(trunc_ln203_53_fu_107050_p1 == 6'd9) & ~(trunc_ln203_53_fu_107050_p1 == 6'd10) & ~(trunc_ln203_53_fu_107050_p1 == 6'd11) & ~(trunc_ln203_53_fu_107050_p1 == 6'd12) & ~(trunc_ln203_53_fu_107050_p1 == 6'd13) & ~(trunc_ln203_53_fu_107050_p1 == 6'd14) & ~(trunc_ln203_53_fu_107050_p1 == 6'd15) & ~(trunc_ln203_53_fu_107050_p1 == 6'd16) & ~(trunc_ln203_53_fu_107050_p1 == 6'd17) & ~(trunc_ln203_53_fu_107050_p1 == 6'd18) & ~(trunc_ln203_53_fu_107050_p1 == 6'd19) & ~(trunc_ln203_53_fu_107050_p1 == 6'd20) & ~(trunc_ln203_53_fu_107050_p1 == 6'd21) & ~(trunc_ln203_53_fu_107050_p1 == 6'd22) & ~(trunc_ln203_53_fu_107050_p1 == 6'd23) & ~(trunc_ln203_53_fu_107050_p1 == 6'd24) & ~(trunc_ln203_53_fu_107050_p1 == 6'd25) & ~(trunc_ln203_53_fu_107050_p1 == 6'd26) & (ap_ST_fsm_state839 == ap_CS_fsm)) | (~(trunc_ln203_62_fu_106777_p1 == 6'd0) & ~(trunc_ln203_62_fu_106777_p1 == 6'd1) & ~(trunc_ln203_62_fu_106777_p1 == 6'd2) & ~(trunc_ln203_62_fu_106777_p1 == 6'd3) & ~(trunc_ln203_62_fu_106777_p1 == 6'd4) & ~(trunc_ln203_62_fu_106777_p1 == 6'd5) & ~(trunc_ln203_62_fu_106777_p1 == 6'd6) & ~(trunc_ln203_62_fu_106777_p1 == 6'd7) & ~(trunc_ln203_62_fu_106777_p1 == 6'd8) & ~(trunc_ln203_62_fu_106777_p1 == 6'd9) & ~(trunc_ln203_62_fu_106777_p1 == 6'd10) & ~(trunc_ln203_62_fu_106777_p1 == 6'd11) & ~(trunc_ln203_62_fu_106777_p1 == 6'd12) & ~(trunc_ln203_62_fu_106777_p1 == 6'd13) & ~(trunc_ln203_62_fu_106777_p1 == 6'd14) & ~(trunc_ln203_62_fu_106777_p1 == 6'd15) & ~(trunc_ln203_62_fu_106777_p1 == 6'd16) & ~(trunc_ln203_62_fu_106777_p1 == 6'd17) & ~(trunc_ln203_62_fu_106777_p1 == 6'd18) & ~(trunc_ln203_62_fu_106777_p1 == 6'd19) & ~(trunc_ln203_62_fu_106777_p1 == 6'd20) & ~(trunc_ln203_62_fu_106777_p1 == 6'd21) & ~(trunc_ln203_62_fu_106777_p1 == 6'd22) & ~(trunc_ln203_62_fu_106777_p1 == 6'd23) & ~(trunc_ln203_62_fu_106777_p1 == 6'd24) & ~(trunc_ln203_62_fu_106777_p1 == 6'd25) & ~(trunc_ln203_62_fu_106777_p1 == 6'd26) & (ap_ST_fsm_state803 == ap_CS_fsm)) | (~(trunc_ln203_46_fu_106498_p1 == 6'd0) & ~(trunc_ln203_46_fu_106498_p1 == 6'd1) & ~(trunc_ln203_46_fu_106498_p1 == 6'd2) & ~(trunc_ln203_46_fu_106498_p1 == 6'd3) & ~(trunc_ln203_46_fu_106498_p1 == 6'd4) & ~(trunc_ln203_46_fu_106498_p1 == 6'd5) & ~(trunc_ln203_46_fu_106498_p1 == 6'd6) & ~(trunc_ln203_46_fu_106498_p1 == 6'd7) & ~(trunc_ln203_46_fu_106498_p1 == 6'd8) & ~(trunc_ln203_46_fu_106498_p1 == 6'd9) & ~(trunc_ln203_46_fu_106498_p1 == 6'd10) & ~(trunc_ln203_46_fu_106498_p1 == 6'd11) & ~(trunc_ln203_46_fu_106498_p1 == 6'd12) & ~(trunc_ln203_46_fu_106498_p1 == 6'd13) & ~(trunc_ln203_46_fu_106498_p1 == 6'd14) & ~(trunc_ln203_46_fu_106498_p1 == 6'd15) & ~(trunc_ln203_46_fu_106498_p1 == 6'd16) & ~(trunc_ln203_46_fu_106498_p1 == 6'd17) & ~(trunc_ln203_46_fu_106498_p1 == 6'd18) & ~(trunc_ln203_46_fu_106498_p1 == 6'd19) & ~(trunc_ln203_46_fu_106498_p1 == 6'd20) & ~(trunc_ln203_46_fu_106498_p1 == 6'd21) & ~(trunc_ln203_46_fu_106498_p1 == 6'd22) & ~(trunc_ln203_46_fu_106498_p1 == 6'd23) & ~(trunc_ln203_46_fu_106498_p1 == 6'd24) & ~(trunc_ln203_46_fu_106498_p1 == 6'd25) & ~(trunc_ln203_46_fu_106498_p1 == 6'd26) & (ap_ST_fsm_state762 == ap_CS_fsm)) | (~(trunc_ln203_54_fu_106438_p1 == 6'd0) & ~(trunc_ln203_54_fu_106438_p1 == 6'd1) & ~(trunc_ln203_54_fu_106438_p1 == 6'd2) & ~(trunc_ln203_54_fu_106438_p1 == 6'd3) & ~(trunc_ln203_54_fu_106438_p1 == 6'd4) & ~(trunc_ln203_54_fu_106438_p1 == 6'd5) & ~(trunc_ln203_54_fu_106438_p1 == 6'd6) & ~(trunc_ln203_54_fu_106438_p1 == 6'd7) & ~(trunc_ln203_54_fu_106438_p1 == 6'd8) & ~(trunc_ln203_54_fu_106438_p1 == 6'd9) & ~(trunc_ln203_54_fu_106438_p1 == 6'd10) & ~(trunc_ln203_54_fu_106438_p1 == 6'd11) & ~(trunc_ln203_54_fu_106438_p1 == 6'd12) & ~(trunc_ln203_54_fu_106438_p1 == 6'd13) & ~(trunc_ln203_54_fu_106438_p1 == 6'd14) & ~(trunc_ln203_54_fu_106438_p1 == 6'd15) & ~(trunc_ln203_54_fu_106438_p1 == 6'd16) & ~(trunc_ln203_54_fu_106438_p1 == 6'd17) & ~(trunc_ln203_54_fu_106438_p1 == 6'd18) & ~(trunc_ln203_54_fu_106438_p1 == 6'd19) & ~(trunc_ln203_54_fu_106438_p1 == 6'd20) & ~(trunc_ln203_54_fu_106438_p1 == 6'd21) & ~(trunc_ln203_54_fu_106438_p1 == 6'd22) & ~(trunc_ln203_54_fu_106438_p1 == 6'd23) & ~(trunc_ln203_54_fu_106438_p1 == 6'd24) & ~(trunc_ln203_54_fu_106438_p1 == 6'd25) & ~(trunc_ln203_54_fu_106438_p1 == 6'd26) & (ap_ST_fsm_state726 == ap_CS_fsm)) | (~(trunc_ln203_38_fu_106360_p1 == 6'd0) & ~(trunc_ln203_38_fu_106360_p1 == 6'd1) & ~(trunc_ln203_38_fu_106360_p1 == 6'd2) & ~(trunc_ln203_38_fu_106360_p1 == 6'd3) & ~(trunc_ln203_38_fu_106360_p1 == 6'd4) & ~(trunc_ln203_38_fu_106360_p1 == 6'd5) & ~(trunc_ln203_38_fu_106360_p1 == 6'd6) & ~(trunc_ln203_38_fu_106360_p1 == 6'd7) & ~(trunc_ln203_38_fu_106360_p1 == 6'd8) & ~(trunc_ln203_38_fu_106360_p1 == 6'd9) & ~(trunc_ln203_38_fu_106360_p1 == 6'd10) & ~(trunc_ln203_38_fu_106360_p1 == 6'd11) & ~(trunc_ln203_38_fu_106360_p1 == 6'd12) & ~(trunc_ln203_38_fu_106360_p1 == 6'd13) & ~(trunc_ln203_38_fu_106360_p1 == 6'd14) & ~(trunc_ln203_38_fu_106360_p1 == 6'd15) & ~(trunc_ln203_38_fu_106360_p1 == 6'd16) & ~(trunc_ln203_38_fu_106360_p1 == 6'd17) & ~(trunc_ln203_38_fu_106360_p1 == 6'd18) & ~(trunc_ln203_38_fu_106360_p1 == 6'd19) & ~(trunc_ln203_38_fu_106360_p1 == 6'd20) & ~(trunc_ln203_38_fu_106360_p1 == 6'd21) & ~(trunc_ln203_38_fu_106360_p1 == 6'd22) & ~(trunc_ln203_38_fu_106360_p1 == 6'd23) & ~(trunc_ln203_38_fu_106360_p1 == 6'd24) & ~(trunc_ln203_38_fu_106360_p1 == 6'd25) & ~(trunc_ln203_38_fu_106360_p1 == 6'd26) & (ap_ST_fsm_state687 == ap_CS_fsm)) | (~(trunc_ln203_92_fu_105378_p1 == 6'd0) & ~(trunc_ln203_92_fu_105378_p1 == 6'd1) & ~(trunc_ln203_92_fu_105378_p1 == 6'd2) & ~(trunc_ln203_92_fu_105378_p1 == 6'd3) & ~(trunc_ln203_92_fu_105378_p1 == 6'd4) & ~(trunc_ln203_92_fu_105378_p1 == 6'd5) & ~(trunc_ln203_92_fu_105378_p1 == 6'd6) & ~(trunc_ln203_92_fu_105378_p1 == 6'd7) & ~(trunc_ln203_92_fu_105378_p1 == 6'd8) & ~(trunc_ln203_92_fu_105378_p1 == 6'd9) & ~(trunc_ln203_92_fu_105378_p1 == 6'd10) & ~(trunc_ln203_92_fu_105378_p1 == 6'd11) & ~(trunc_ln203_92_fu_105378_p1 == 6'd12) & ~(trunc_ln203_92_fu_105378_p1 == 6'd13) & ~(trunc_ln203_92_fu_105378_p1 == 6'd14) & ~(trunc_ln203_92_fu_105378_p1 == 6'd15) & ~(trunc_ln203_92_fu_105378_p1 == 6'd16) & ~(trunc_ln203_92_fu_105378_p1 == 6'd17) & ~(trunc_ln203_92_fu_105378_p1 == 6'd18) & ~(trunc_ln203_92_fu_105378_p1 == 6'd19) & ~(trunc_ln203_92_fu_105378_p1 == 6'd20) & ~(trunc_ln203_92_fu_105378_p1 == 6'd21) & ~(trunc_ln203_92_fu_105378_p1 == 6'd22) & ~(trunc_ln203_92_fu_105378_p1 == 6'd23) & ~(trunc_ln203_92_fu_105378_p1 == 6'd24) & ~(trunc_ln203_92_fu_105378_p1 == 6'd25) & ~(trunc_ln203_92_fu_105378_p1 == 6'd26) & (ap_ST_fsm_state608 == ap_CS_fsm)) | (~(trunc_ln203_75_fu_105240_p1 == 6'd0) & ~(trunc_ln203_75_fu_105240_p1 == 6'd1) & ~(trunc_ln203_75_fu_105240_p1 == 6'd2) & ~(trunc_ln203_75_fu_105240_p1 == 6'd3) & ~(trunc_ln203_75_fu_105240_p1 == 6'd4) & ~(trunc_ln203_75_fu_105240_p1 == 6'd5) & ~(trunc_ln203_75_fu_105240_p1 == 6'd6) & ~(trunc_ln203_75_fu_105240_p1 == 6'd7) & ~(trunc_ln203_75_fu_105240_p1 == 6'd8) & ~(trunc_ln203_75_fu_105240_p1 == 6'd9) & ~(trunc_ln203_75_fu_105240_p1 == 6'd10) & ~(trunc_ln203_75_fu_105240_p1 == 6'd11) & ~(trunc_ln203_75_fu_105240_p1 == 6'd12) & ~(trunc_ln203_75_fu_105240_p1 == 6'd13) & ~(trunc_ln203_75_fu_105240_p1 == 6'd14) & ~(trunc_ln203_75_fu_105240_p1 == 6'd15) & ~(trunc_ln203_75_fu_105240_p1 == 6'd16) & ~(trunc_ln203_75_fu_105240_p1 == 6'd17) & ~(trunc_ln203_75_fu_105240_p1 == 6'd18) & ~(trunc_ln203_75_fu_105240_p1 == 6'd19) & ~(trunc_ln203_75_fu_105240_p1 == 6'd20) & ~(trunc_ln203_75_fu_105240_p1 == 6'd21) & ~(trunc_ln203_75_fu_105240_p1 == 6'd22) & ~(trunc_ln203_75_fu_105240_p1 == 6'd23) & ~(trunc_ln203_75_fu_105240_p1 == 6'd24) & ~(trunc_ln203_75_fu_105240_p1 == 6'd25) & ~(trunc_ln203_75_fu_105240_p1 == 6'd26) & (ap_ST_fsm_state535 == ap_CS_fsm)) | (~(trunc_ln203_69_fu_104690_p1 == 6'd0) & ~(trunc_ln203_69_fu_104690_p1 == 6'd1) & ~(trunc_ln203_69_fu_104690_p1 == 6'd2) & ~(trunc_ln203_69_fu_104690_p1 == 6'd3) & ~(trunc_ln203_69_fu_104690_p1 == 6'd4) & ~(trunc_ln203_69_fu_104690_p1 == 6'd5) & ~(trunc_ln203_69_fu_104690_p1 == 6'd6) & ~(trunc_ln203_69_fu_104690_p1 == 6'd7) & ~(trunc_ln203_69_fu_104690_p1 == 6'd8) & ~(trunc_ln203_69_fu_104690_p1 == 6'd9) & ~(trunc_ln203_69_fu_104690_p1 == 6'd10) & ~(trunc_ln203_69_fu_104690_p1 == 6'd11) & ~(trunc_ln203_69_fu_104690_p1 == 6'd12) & ~(trunc_ln203_69_fu_104690_p1 == 6'd13) & ~(trunc_ln203_69_fu_104690_p1 == 6'd14) & ~(trunc_ln203_69_fu_104690_p1 == 6'd15) & ~(trunc_ln203_69_fu_104690_p1 == 6'd16) & ~(trunc_ln203_69_fu_104690_p1 == 6'd17) & ~(trunc_ln203_69_fu_104690_p1 == 6'd18) & ~(trunc_ln203_69_fu_104690_p1 == 6'd19) & ~(trunc_ln203_69_fu_104690_p1 == 6'd20) & ~(trunc_ln203_69_fu_104690_p1 == 6'd21) & ~(trunc_ln203_69_fu_104690_p1 == 6'd22) & ~(trunc_ln203_69_fu_104690_p1 == 6'd23) & ~(trunc_ln203_69_fu_104690_p1 == 6'd24) & ~(trunc_ln203_69_fu_104690_p1 == 6'd25) & ~(trunc_ln203_69_fu_104690_p1 == 6'd26) & (ap_ST_fsm_state460 == ap_CS_fsm)) | (~(trunc_ln203_76_fu_104630_p1 == 6'd0) & ~(trunc_ln203_76_fu_104630_p1 == 6'd1) & ~(trunc_ln203_76_fu_104630_p1 == 6'd2) & ~(trunc_ln203_76_fu_104630_p1 == 6'd3) & ~(trunc_ln203_76_fu_104630_p1 == 6'd4) & ~(trunc_ln203_76_fu_104630_p1 == 6'd5) & ~(trunc_ln203_76_fu_104630_p1 == 6'd6) & ~(trunc_ln203_76_fu_104630_p1 == 6'd7) & ~(trunc_ln203_76_fu_104630_p1 == 6'd8) & ~(trunc_ln203_76_fu_104630_p1 == 6'd9) & ~(trunc_ln203_76_fu_104630_p1 == 6'd10) & ~(trunc_ln203_76_fu_104630_p1 == 6'd11) & ~(trunc_ln203_76_fu_104630_p1 == 6'd12) & ~(trunc_ln203_76_fu_104630_p1 == 6'd13) & ~(trunc_ln203_76_fu_104630_p1 == 6'd14) & ~(trunc_ln203_76_fu_104630_p1 == 6'd15) & ~(trunc_ln203_76_fu_104630_p1 == 6'd16) & ~(trunc_ln203_76_fu_104630_p1 == 6'd17) & ~(trunc_ln203_76_fu_104630_p1 == 6'd18) & ~(trunc_ln203_76_fu_104630_p1 == 6'd19) & ~(trunc_ln203_76_fu_104630_p1 == 6'd20) & ~(trunc_ln203_76_fu_104630_p1 == 6'd21) & ~(trunc_ln203_76_fu_104630_p1 == 6'd22) & ~(trunc_ln203_76_fu_104630_p1 == 6'd23) & ~(trunc_ln203_76_fu_104630_p1 == 6'd24) & ~(trunc_ln203_76_fu_104630_p1 == 6'd25) & ~(trunc_ln203_76_fu_104630_p1 == 6'd26) & (ap_ST_fsm_state424 == ap_CS_fsm)) | (~(trunc_ln203_49_fu_104552_p1 == 6'd0) & ~(trunc_ln203_49_fu_104552_p1 == 6'd1) & ~(trunc_ln203_49_fu_104552_p1 == 6'd2) & ~(trunc_ln203_49_fu_104552_p1 == 6'd3) & ~(trunc_ln203_49_fu_104552_p1 == 6'd4) & ~(trunc_ln203_49_fu_104552_p1 == 6'd5) & ~(trunc_ln203_49_fu_104552_p1 == 6'd6) & ~(trunc_ln203_49_fu_104552_p1 == 6'd7) & ~(trunc_ln203_49_fu_104552_p1 == 6'd8) & ~(trunc_ln203_49_fu_104552_p1 == 6'd9) & ~(trunc_ln203_49_fu_104552_p1 == 6'd10) & ~(trunc_ln203_49_fu_104552_p1 == 6'd11) & ~(trunc_ln203_49_fu_104552_p1 == 6'd12) & ~(trunc_ln203_49_fu_104552_p1 == 6'd13) & ~(trunc_ln203_49_fu_104552_p1 == 6'd14) & ~(trunc_ln203_49_fu_104552_p1 == 6'd15) & ~(trunc_ln203_49_fu_104552_p1 == 6'd16) & ~(trunc_ln203_49_fu_104552_p1 == 6'd17) & ~(trunc_ln203_49_fu_104552_p1 == 6'd18) & ~(trunc_ln203_49_fu_104552_p1 == 6'd19) & ~(trunc_ln203_49_fu_104552_p1 == 6'd20) & ~(trunc_ln203_49_fu_104552_p1 == 6'd21) & ~(trunc_ln203_49_fu_104552_p1 == 6'd22) & ~(trunc_ln203_49_fu_104552_p1 == 6'd23) & ~(trunc_ln203_49_fu_104552_p1 == 6'd24) & ~(trunc_ln203_49_fu_104552_p1 == 6'd25) & ~(trunc_ln203_49_fu_104552_p1 == 6'd26) & (ap_ST_fsm_state385 == ap_CS_fsm)) | (~(trunc_ln203_68_fu_103773_p1 == 6'd0) & ~(trunc_ln203_68_fu_103773_p1 == 6'd1) & ~(trunc_ln203_68_fu_103773_p1 == 6'd2) & ~(trunc_ln203_68_fu_103773_p1 == 6'd3) & ~(trunc_ln203_68_fu_103773_p1 == 6'd4) & ~(trunc_ln203_68_fu_103773_p1 == 6'd5) & ~(trunc_ln203_68_fu_103773_p1 == 6'd6) & ~(trunc_ln203_68_fu_103773_p1 == 6'd7) & ~(trunc_ln203_68_fu_103773_p1 == 6'd8) & ~(trunc_ln203_68_fu_103773_p1 == 6'd9) & ~(trunc_ln203_68_fu_103773_p1 == 6'd10) & ~(trunc_ln203_68_fu_103773_p1 == 6'd11) & ~(trunc_ln203_68_fu_103773_p1 == 6'd12) & ~(trunc_ln203_68_fu_103773_p1 == 6'd13) & ~(trunc_ln203_68_fu_103773_p1 == 6'd14) & ~(trunc_ln203_68_fu_103773_p1 == 6'd15) & ~(trunc_ln203_68_fu_103773_p1 == 6'd16) & ~(trunc_ln203_68_fu_103773_p1 == 6'd17) & ~(trunc_ln203_68_fu_103773_p1 == 6'd18) & ~(trunc_ln203_68_fu_103773_p1 == 6'd19) & ~(trunc_ln203_68_fu_103773_p1 == 6'd20) & ~(trunc_ln203_68_fu_103773_p1 == 6'd21) & ~(trunc_ln203_68_fu_103773_p1 == 6'd22) & ~(trunc_ln203_68_fu_103773_p1 == 6'd23) & ~(trunc_ln203_68_fu_103773_p1 == 6'd24) & ~(trunc_ln203_68_fu_103773_p1 == 6'd25) & ~(trunc_ln203_68_fu_103773_p1 == 6'd26) & (ap_ST_fsm_state309 == ap_CS_fsm)) | (~(trunc_ln203_72_fu_103713_p1 == 6'd0) & ~(trunc_ln203_72_fu_103713_p1 == 6'd1) & ~(trunc_ln203_72_fu_103713_p1 == 6'd2) & ~(trunc_ln203_72_fu_103713_p1 == 6'd3) & ~(trunc_ln203_72_fu_103713_p1 == 6'd4) & ~(trunc_ln203_72_fu_103713_p1 == 6'd5) & ~(trunc_ln203_72_fu_103713_p1 == 6'd6) & ~(trunc_ln203_72_fu_103713_p1 == 6'd7) & ~(trunc_ln203_72_fu_103713_p1 == 6'd8) & ~(trunc_ln203_72_fu_103713_p1 == 6'd9) & ~(trunc_ln203_72_fu_103713_p1 == 6'd10) & ~(trunc_ln203_72_fu_103713_p1 == 6'd11) & ~(trunc_ln203_72_fu_103713_p1 == 6'd12) & ~(trunc_ln203_72_fu_103713_p1 == 6'd13) & ~(trunc_ln203_72_fu_103713_p1 == 6'd14) & ~(trunc_ln203_72_fu_103713_p1 == 6'd15) & ~(trunc_ln203_72_fu_103713_p1 == 6'd16) & ~(trunc_ln203_72_fu_103713_p1 == 6'd17) & ~(trunc_ln203_72_fu_103713_p1 == 6'd18) & ~(trunc_ln203_72_fu_103713_p1 == 6'd19) & ~(trunc_ln203_72_fu_103713_p1 == 6'd20) & ~(trunc_ln203_72_fu_103713_p1 == 6'd21) & ~(trunc_ln203_72_fu_103713_p1 == 6'd22) & ~(trunc_ln203_72_fu_103713_p1 == 6'd23) & ~(trunc_ln203_72_fu_103713_p1 == 6'd24) & ~(trunc_ln203_72_fu_103713_p1 == 6'd25) & ~(trunc_ln203_72_fu_103713_p1 == 6'd26) & (ap_ST_fsm_state273 == ap_CS_fsm)) | (~(trunc_ln203_47_fu_103635_p1 == 6'd0) & ~(trunc_ln203_47_fu_103635_p1 == 6'd1) & ~(trunc_ln203_47_fu_103635_p1 == 6'd2) & ~(trunc_ln203_47_fu_103635_p1 == 6'd3) & ~(trunc_ln203_47_fu_103635_p1 == 6'd4) & ~(trunc_ln203_47_fu_103635_p1 == 6'd5) & ~(trunc_ln203_47_fu_103635_p1 == 6'd6) & ~(trunc_ln203_47_fu_103635_p1 == 6'd7) & ~(trunc_ln203_47_fu_103635_p1 == 6'd8) & ~(trunc_ln203_47_fu_103635_p1 == 6'd9) & ~(trunc_ln203_47_fu_103635_p1 == 6'd10) & ~(trunc_ln203_47_fu_103635_p1 == 6'd11) & ~(trunc_ln203_47_fu_103635_p1 == 6'd12) & ~(trunc_ln203_47_fu_103635_p1 == 6'd13) & ~(trunc_ln203_47_fu_103635_p1 == 6'd14) & ~(trunc_ln203_47_fu_103635_p1 == 6'd15) & ~(trunc_ln203_47_fu_103635_p1 == 6'd16) & ~(trunc_ln203_47_fu_103635_p1 == 6'd17) & ~(trunc_ln203_47_fu_103635_p1 == 6'd18) & ~(trunc_ln203_47_fu_103635_p1 == 6'd19) & ~(trunc_ln203_47_fu_103635_p1 == 6'd20) & ~(trunc_ln203_47_fu_103635_p1 == 6'd21) & ~(trunc_ln203_47_fu_103635_p1 == 6'd22) & ~(trunc_ln203_47_fu_103635_p1 == 6'd23) & ~(trunc_ln203_47_fu_103635_p1 == 6'd24) & ~(trunc_ln203_47_fu_103635_p1 == 6'd25) & ~(trunc_ln203_47_fu_103635_p1 == 6'd26) & (ap_ST_fsm_state234 == ap_CS_fsm)) | (~(trunc_ln203_55_fu_103361_p1 == 6'd0) & ~(trunc_ln203_55_fu_103361_p1 == 6'd1) & ~(trunc_ln203_55_fu_103361_p1 == 6'd2) & ~(trunc_ln203_55_fu_103361_p1 == 6'd3) & ~(trunc_ln203_55_fu_103361_p1 == 6'd4) & ~(trunc_ln203_55_fu_103361_p1 == 6'd5) & ~(trunc_ln203_55_fu_103361_p1 == 6'd6) & ~(trunc_ln203_55_fu_103361_p1 == 6'd7) & ~(trunc_ln203_55_fu_103361_p1 == 6'd8) & ~(trunc_ln203_55_fu_103361_p1 == 6'd9) & ~(trunc_ln203_55_fu_103361_p1 == 6'd10) & ~(trunc_ln203_55_fu_103361_p1 == 6'd11) & ~(trunc_ln203_55_fu_103361_p1 == 6'd12) & ~(trunc_ln203_55_fu_103361_p1 == 6'd13) & ~(trunc_ln203_55_fu_103361_p1 == 6'd14) & ~(trunc_ln203_55_fu_103361_p1 == 6'd15) & ~(trunc_ln203_55_fu_103361_p1 == 6'd16) & ~(trunc_ln203_55_fu_103361_p1 == 6'd17) & ~(trunc_ln203_55_fu_103361_p1 == 6'd18) & ~(trunc_ln203_55_fu_103361_p1 == 6'd19) & ~(trunc_ln203_55_fu_103361_p1 == 6'd20) & ~(trunc_ln203_55_fu_103361_p1 == 6'd21) & ~(trunc_ln203_55_fu_103361_p1 == 6'd22) & ~(trunc_ln203_55_fu_103361_p1 == 6'd23) & ~(trunc_ln203_55_fu_103361_p1 == 6'd24) & ~(trunc_ln203_55_fu_103361_p1 == 6'd25) & ~(trunc_ln203_55_fu_103361_p1 == 6'd26) & (ap_ST_fsm_state198 == ap_CS_fsm)) | (~(trunc_ln203_44_fu_103081_p1 == 6'd0) & ~(trunc_ln203_44_fu_103081_p1 == 6'd1) & ~(trunc_ln203_44_fu_103081_p1 == 6'd2) & ~(trunc_ln203_44_fu_103081_p1 == 6'd3) & ~(trunc_ln203_44_fu_103081_p1 == 6'd4) & ~(trunc_ln203_44_fu_103081_p1 == 6'd5) & ~(trunc_ln203_44_fu_103081_p1 == 6'd6) & ~(trunc_ln203_44_fu_103081_p1 == 6'd7) & ~(trunc_ln203_44_fu_103081_p1 == 6'd8) & ~(trunc_ln203_44_fu_103081_p1 == 6'd9) & ~(trunc_ln203_44_fu_103081_p1 == 6'd10) & ~(trunc_ln203_44_fu_103081_p1 == 6'd11) & ~(trunc_ln203_44_fu_103081_p1 == 6'd12) & ~(trunc_ln203_44_fu_103081_p1 == 6'd13) & ~(trunc_ln203_44_fu_103081_p1 == 6'd14) & ~(trunc_ln203_44_fu_103081_p1 == 6'd15) & ~(trunc_ln203_44_fu_103081_p1 == 6'd16) & ~(trunc_ln203_44_fu_103081_p1 == 6'd17) & ~(trunc_ln203_44_fu_103081_p1 == 6'd18) & ~(trunc_ln203_44_fu_103081_p1 == 6'd19) & ~(trunc_ln203_44_fu_103081_p1 == 6'd20) & ~(trunc_ln203_44_fu_103081_p1 == 6'd21) & ~(trunc_ln203_44_fu_103081_p1 == 6'd22) & ~(trunc_ln203_44_fu_103081_p1 == 6'd23) & ~(trunc_ln203_44_fu_103081_p1 == 6'd24) & ~(trunc_ln203_44_fu_103081_p1 == 6'd25) & ~(trunc_ln203_44_fu_103081_p1 == 6'd26) & (ap_ST_fsm_state157 == ap_CS_fsm)) | (~(trunc_ln203_48_fu_103021_p1 == 6'd0) & ~(trunc_ln203_48_fu_103021_p1 == 6'd1) & ~(trunc_ln203_48_fu_103021_p1 == 6'd2) & ~(trunc_ln203_48_fu_103021_p1 == 6'd3) & ~(trunc_ln203_48_fu_103021_p1 == 6'd4) & ~(trunc_ln203_48_fu_103021_p1 == 6'd5) & ~(trunc_ln203_48_fu_103021_p1 == 6'd6) & ~(trunc_ln203_48_fu_103021_p1 == 6'd7) & ~(trunc_ln203_48_fu_103021_p1 == 6'd8) & ~(trunc_ln203_48_fu_103021_p1 == 6'd9) & ~(trunc_ln203_48_fu_103021_p1 == 6'd10) & ~(trunc_ln203_48_fu_103021_p1 == 6'd11) & ~(trunc_ln203_48_fu_103021_p1 == 6'd12) & ~(trunc_ln203_48_fu_103021_p1 == 6'd13) & ~(trunc_ln203_48_fu_103021_p1 == 6'd14) & ~(trunc_ln203_48_fu_103021_p1 == 6'd15) & ~(trunc_ln203_48_fu_103021_p1 == 6'd16) & ~(trunc_ln203_48_fu_103021_p1 == 6'd17) & ~(trunc_ln203_48_fu_103021_p1 == 6'd18) & ~(trunc_ln203_48_fu_103021_p1 == 6'd19) & ~(trunc_ln203_48_fu_103021_p1 == 6'd20) & ~(trunc_ln203_48_fu_103021_p1 == 6'd21) & ~(trunc_ln203_48_fu_103021_p1 == 6'd22) & ~(trunc_ln203_48_fu_103021_p1 == 6'd23) & ~(trunc_ln203_48_fu_103021_p1 == 6'd24) & ~(trunc_ln203_48_fu_103021_p1 == 6'd25) & ~(trunc_ln203_48_fu_103021_p1 == 6'd26) & (ap_ST_fsm_state121 == ap_CS_fsm)) | (~(trunc_ln203_fu_102943_p1 == 6'd0) & ~(trunc_ln203_fu_102943_p1 == 6'd1) & ~(trunc_ln203_fu_102943_p1 == 6'd2) & ~(trunc_ln203_fu_102943_p1 == 6'd3) & ~(trunc_ln203_fu_102943_p1 == 6'd4) & ~(trunc_ln203_fu_102943_p1 == 6'd5) & ~(trunc_ln203_fu_102943_p1 == 6'd6) & ~(trunc_ln203_fu_102943_p1 == 6'd7) & ~(trunc_ln203_fu_102943_p1 == 6'd8) & ~(trunc_ln203_fu_102943_p1 == 6'd9) & ~(trunc_ln203_fu_102943_p1 == 6'd10) & ~(trunc_ln203_fu_102943_p1 == 6'd11) & ~(trunc_ln203_fu_102943_p1 == 6'd12) & ~(trunc_ln203_fu_102943_p1 == 6'd13) & ~(trunc_ln203_fu_102943_p1 == 6'd14) & ~(trunc_ln203_fu_102943_p1 == 6'd15) & ~(trunc_ln203_fu_102943_p1 == 6'd16) & ~(trunc_ln203_fu_102943_p1 == 6'd17) & ~(trunc_ln203_fu_102943_p1 == 6'd18) & ~(trunc_ln203_fu_102943_p1 == 6'd19) & ~(trunc_ln203_fu_102943_p1 == 6'd20) & ~(trunc_ln203_fu_102943_p1 == 6'd21) & ~(trunc_ln203_fu_102943_p1 == 6'd22) & ~(trunc_ln203_fu_102943_p1 == 6'd23) & ~(trunc_ln203_fu_102943_p1 == 6'd24) & ~(trunc_ln203_fu_102943_p1 == 6'd25) & ~(trunc_ln203_fu_102943_p1 == 6'd26) & (ap_ST_fsm_state82 == ap_CS_fsm)) | (~(trunc_ln203_39_fu_102479_p1 == 6'd0) & ~(trunc_ln203_39_fu_102479_p1 == 6'd1) & ~(trunc_ln203_39_fu_102479_p1 == 6'd2) & ~(trunc_ln203_39_fu_102479_p1 == 6'd3) & ~(trunc_ln203_39_fu_102479_p1 == 6'd4) & ~(trunc_ln203_39_fu_102479_p1 == 6'd5) & ~(trunc_ln203_39_fu_102479_p1 == 6'd6) & ~(trunc_ln203_39_fu_102479_p1 == 6'd7) & ~(trunc_ln203_39_fu_102479_p1 == 6'd8) & ~(trunc_ln203_39_fu_102479_p1 == 6'd9) & ~(trunc_ln203_39_fu_102479_p1 == 6'd10) & ~(trunc_ln203_39_fu_102479_p1 == 6'd11) & ~(trunc_ln203_39_fu_102479_p1 == 6'd12) & ~(trunc_ln203_39_fu_102479_p1 == 6'd13) & ~(trunc_ln203_39_fu_102479_p1 == 6'd14) & ~(trunc_ln203_39_fu_102479_p1 == 6'd15) & ~(trunc_ln203_39_fu_102479_p1 == 6'd16) & ~(trunc_ln203_39_fu_102479_p1 == 6'd17) & ~(trunc_ln203_39_fu_102479_p1 == 6'd18) & ~(trunc_ln203_39_fu_102479_p1 == 6'd19) & ~(trunc_ln203_39_fu_102479_p1 == 6'd20) & ~(trunc_ln203_39_fu_102479_p1 == 6'd21) & ~(trunc_ln203_39_fu_102479_p1 == 6'd22) & ~(trunc_ln203_39_fu_102479_p1 == 6'd23) & ~(trunc_ln203_39_fu_102479_p1 == 6'd24) & ~(trunc_ln203_39_fu_102479_p1 == 6'd25) & ~(trunc_ln203_39_fu_102479_p1 == 6'd26) & (ap_ST_fsm_state46 == ap_CS_fsm)) | (~(trunc_ln203_99_fu_115563_p1 == 6'd0) & ~(trunc_ln203_99_fu_115563_p1 == 6'd1) & ~(trunc_ln203_99_fu_115563_p1 == 6'd2) & ~(trunc_ln203_99_fu_115563_p1 == 6'd3) & ~(trunc_ln203_99_fu_115563_p1 == 6'd4) & ~(trunc_ln203_99_fu_115563_p1 == 6'd5) & ~(trunc_ln203_99_fu_115563_p1 == 6'd6) & ~(trunc_ln203_99_fu_115563_p1 == 6'd7) & ~(trunc_ln203_99_fu_115563_p1 == 6'd8) & ~(trunc_ln203_99_fu_115563_p1 == 6'd9) & ~(trunc_ln203_99_fu_115563_p1 == 6'd10) & ~(trunc_ln203_99_fu_115563_p1 == 6'd11) & ~(trunc_ln203_99_fu_115563_p1 == 6'd12) & ~(trunc_ln203_99_fu_115563_p1 == 6'd13) & ~(trunc_ln203_99_fu_115563_p1 == 6'd14) & ~(trunc_ln203_99_fu_115563_p1 == 6'd15) & ~(trunc_ln203_99_fu_115563_p1 == 6'd16) & ~(trunc_ln203_99_fu_115563_p1 == 6'd17) & ~(trunc_ln203_99_fu_115563_p1 == 6'd18) & ~(trunc_ln203_99_fu_115563_p1 == 6'd19) & ~(trunc_ln203_99_fu_115563_p1 == 6'd20) & ~(trunc_ln203_99_fu_115563_p1 == 6'd21) & ~(trunc_ln203_99_fu_115563_p1 == 6'd22) & ~(trunc_ln203_99_fu_115563_p1 == 6'd23) & ~(trunc_ln203_99_fu_115563_p1 == 6'd24) & ~(trunc_ln203_99_fu_115563_p1 == 6'd25) & ~(trunc_ln203_99_fu_115563_p1 == 6'd26) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | (~(trunc_ln203_91_fu_115214_p1 == 6'd0) & ~(trunc_ln203_91_fu_115214_p1 == 6'd1) & ~(trunc_ln203_91_fu_115214_p1 == 6'd2) & ~(trunc_ln203_91_fu_115214_p1 == 6'd3) & ~(trunc_ln203_91_fu_115214_p1 == 6'd4) & ~(trunc_ln203_91_fu_115214_p1 == 6'd5) & ~(trunc_ln203_91_fu_115214_p1 == 6'd6) & ~(trunc_ln203_91_fu_115214_p1 == 6'd7) & ~(trunc_ln203_91_fu_115214_p1 == 6'd8) & ~(trunc_ln203_91_fu_115214_p1 == 6'd9) & ~(trunc_ln203_91_fu_115214_p1 == 6'd10) & ~(trunc_ln203_91_fu_115214_p1 == 6'd11) & ~(trunc_ln203_91_fu_115214_p1 == 6'd12) & ~(trunc_ln203_91_fu_115214_p1 == 6'd13) & ~(trunc_ln203_91_fu_115214_p1 == 6'd14) & ~(trunc_ln203_91_fu_115214_p1 == 6'd15) & ~(trunc_ln203_91_fu_115214_p1 == 6'd16) & ~(trunc_ln203_91_fu_115214_p1 == 6'd17) & ~(trunc_ln203_91_fu_115214_p1 == 6'd18) & ~(trunc_ln203_91_fu_115214_p1 == 6'd19) & ~(trunc_ln203_91_fu_115214_p1 == 6'd20) & ~(trunc_ln203_91_fu_115214_p1 == 6'd21) & ~(trunc_ln203_91_fu_115214_p1 == 6'd22) & ~(trunc_ln203_91_fu_115214_p1 == 6'd23) & ~(trunc_ln203_91_fu_115214_p1 == 6'd24) & ~(trunc_ln203_91_fu_115214_p1 == 6'd25) & ~(trunc_ln203_91_fu_115214_p1 == 6'd26) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | (~(trunc_ln203_67_fu_114413_p1 == 6'd0) & ~(trunc_ln203_67_fu_114413_p1 == 6'd1) & ~(trunc_ln203_67_fu_114413_p1 == 6'd2) & ~(trunc_ln203_67_fu_114413_p1 == 6'd3) & ~(trunc_ln203_67_fu_114413_p1 == 6'd4) & ~(trunc_ln203_67_fu_114413_p1 == 6'd5) & ~(trunc_ln203_67_fu_114413_p1 == 6'd6) & ~(trunc_ln203_67_fu_114413_p1 == 6'd7) & ~(trunc_ln203_67_fu_114413_p1 == 6'd8) & ~(trunc_ln203_67_fu_114413_p1 == 6'd9) & ~(trunc_ln203_67_fu_114413_p1 == 6'd10) & ~(trunc_ln203_67_fu_114413_p1 == 6'd11) & ~(trunc_ln203_67_fu_114413_p1 == 6'd12) & ~(trunc_ln203_67_fu_114413_p1 == 6'd13) & ~(trunc_ln203_67_fu_114413_p1 == 6'd14) & ~(trunc_ln203_67_fu_114413_p1 == 6'd15) & ~(trunc_ln203_67_fu_114413_p1 == 6'd16) & ~(trunc_ln203_67_fu_114413_p1 == 6'd17) & ~(trunc_ln203_67_fu_114413_p1 == 6'd18) & ~(trunc_ln203_67_fu_114413_p1 == 6'd19) & ~(trunc_ln203_67_fu_114413_p1 == 6'd20) & ~(trunc_ln203_67_fu_114413_p1 == 6'd21) & ~(trunc_ln203_67_fu_114413_p1 == 6'd22) & ~(trunc_ln203_67_fu_114413_p1 == 6'd23) & ~(trunc_ln203_67_fu_114413_p1 == 6'd24) & ~(trunc_ln203_67_fu_114413_p1 == 6'd25) & ~(trunc_ln203_67_fu_114413_p1 == 6'd26) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | (~(trunc_ln203_43_fu_112741_p1 == 6'd0) & ~(trunc_ln203_43_fu_112741_p1 == 6'd1) & ~(trunc_ln203_43_fu_112741_p1 == 6'd2) & ~(trunc_ln203_43_fu_112741_p1 == 6'd3) & ~(trunc_ln203_43_fu_112741_p1 == 6'd4) & ~(trunc_ln203_43_fu_112741_p1 == 6'd5) & ~(trunc_ln203_43_fu_112741_p1 == 6'd6) & ~(trunc_ln203_43_fu_112741_p1 == 6'd7) & ~(trunc_ln203_43_fu_112741_p1 == 6'd8) & ~(trunc_ln203_43_fu_112741_p1 == 6'd9) & ~(trunc_ln203_43_fu_112741_p1 == 6'd10) & ~(trunc_ln203_43_fu_112741_p1 == 6'd11) & ~(trunc_ln203_43_fu_112741_p1 == 6'd12) & ~(trunc_ln203_43_fu_112741_p1 == 6'd13) & ~(trunc_ln203_43_fu_112741_p1 == 6'd14) & ~(trunc_ln203_43_fu_112741_p1 == 6'd15) & ~(trunc_ln203_43_fu_112741_p1 == 6'd16) & ~(trunc_ln203_43_fu_112741_p1 == 6'd17) & ~(trunc_ln203_43_fu_112741_p1 == 6'd18) & ~(trunc_ln203_43_fu_112741_p1 == 6'd19) & ~(trunc_ln203_43_fu_112741_p1 == 6'd20) & ~(trunc_ln203_43_fu_112741_p1 == 6'd21) & ~(trunc_ln203_43_fu_112741_p1 == 6'd22) & ~(trunc_ln203_43_fu_112741_p1 == 6'd23) & ~(trunc_ln203_43_fu_112741_p1 == 6'd24) & ~(trunc_ln203_43_fu_112741_p1 == 6'd25) & ~(trunc_ln203_43_fu_112741_p1 == 6'd26) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | (~(trunc_ln203_97_fu_112172_p1 == 6'd0) & ~(trunc_ln203_97_fu_112172_p1 == 6'd1) & ~(trunc_ln203_97_fu_112172_p1 == 6'd2) & ~(trunc_ln203_97_fu_112172_p1 == 6'd3) & ~(trunc_ln203_97_fu_112172_p1 == 6'd4) & ~(trunc_ln203_97_fu_112172_p1 == 6'd5) & ~(trunc_ln203_97_fu_112172_p1 == 6'd6) & ~(trunc_ln203_97_fu_112172_p1 == 6'd7) & ~(trunc_ln203_97_fu_112172_p1 == 6'd8) & ~(trunc_ln203_97_fu_112172_p1 == 6'd9) & ~(trunc_ln203_97_fu_112172_p1 == 6'd10) & ~(trunc_ln203_97_fu_112172_p1 == 6'd11) & ~(trunc_ln203_97_fu_112172_p1 == 6'd12) & ~(trunc_ln203_97_fu_112172_p1 == 6'd13) & ~(trunc_ln203_97_fu_112172_p1 == 6'd14) & ~(trunc_ln203_97_fu_112172_p1 == 6'd15) & ~(trunc_ln203_97_fu_112172_p1 == 6'd16) & ~(trunc_ln203_97_fu_112172_p1 == 6'd17) & ~(trunc_ln203_97_fu_112172_p1 == 6'd18) & ~(trunc_ln203_97_fu_112172_p1 == 6'd19) & ~(trunc_ln203_97_fu_112172_p1 == 6'd20) & ~(trunc_ln203_97_fu_112172_p1 == 6'd21) & ~(trunc_ln203_97_fu_112172_p1 == 6'd22) & ~(trunc_ln203_97_fu_112172_p1 == 6'd23) & ~(trunc_ln203_97_fu_112172_p1 == 6'd24) & ~(trunc_ln203_97_fu_112172_p1 == 6'd25) & ~(trunc_ln203_97_fu_112172_p1 == 6'd26) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | (~(trunc_ln203_89_fu_111822_p1 == 6'd0) & ~(trunc_ln203_89_fu_111822_p1 == 6'd1) & ~(trunc_ln203_89_fu_111822_p1 == 6'd2) & ~(trunc_ln203_89_fu_111822_p1 == 6'd3) & ~(trunc_ln203_89_fu_111822_p1 == 6'd4) & ~(trunc_ln203_89_fu_111822_p1 == 6'd5) & ~(trunc_ln203_89_fu_111822_p1 == 6'd6) & ~(trunc_ln203_89_fu_111822_p1 == 6'd7) & ~(trunc_ln203_89_fu_111822_p1 == 6'd8) & ~(trunc_ln203_89_fu_111822_p1 == 6'd9) & ~(trunc_ln203_89_fu_111822_p1 == 6'd10) & ~(trunc_ln203_89_fu_111822_p1 == 6'd11) & ~(trunc_ln203_89_fu_111822_p1 == 6'd12) & ~(trunc_ln203_89_fu_111822_p1 == 6'd13) & ~(trunc_ln203_89_fu_111822_p1 == 6'd14) & ~(trunc_ln203_89_fu_111822_p1 == 6'd15) & ~(trunc_ln203_89_fu_111822_p1 == 6'd16) & ~(trunc_ln203_89_fu_111822_p1 == 6'd17) & ~(trunc_ln203_89_fu_111822_p1 == 6'd18) & ~(trunc_ln203_89_fu_111822_p1 == 6'd19) & ~(trunc_ln203_89_fu_111822_p1 == 6'd20) & ~(trunc_ln203_89_fu_111822_p1 == 6'd21) & ~(trunc_ln203_89_fu_111822_p1 == 6'd22) & ~(trunc_ln203_89_fu_111822_p1 == 6'd23) & ~(trunc_ln203_89_fu_111822_p1 == 6'd24) & ~(trunc_ln203_89_fu_111822_p1 == 6'd25) & ~(trunc_ln203_89_fu_111822_p1 == 6'd26) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | (~(trunc_ln203_64_fu_111017_p1 == 6'd0) & ~(trunc_ln203_64_fu_111017_p1 == 6'd1) & ~(trunc_ln203_64_fu_111017_p1 == 6'd2) & ~(trunc_ln203_64_fu_111017_p1 == 6'd3) & ~(trunc_ln203_64_fu_111017_p1 == 6'd4) & ~(trunc_ln203_64_fu_111017_p1 == 6'd5) & ~(trunc_ln203_64_fu_111017_p1 == 6'd6) & ~(trunc_ln203_64_fu_111017_p1 == 6'd7) & ~(trunc_ln203_64_fu_111017_p1 == 6'd8) & ~(trunc_ln203_64_fu_111017_p1 == 6'd9) & ~(trunc_ln203_64_fu_111017_p1 == 6'd10) & ~(trunc_ln203_64_fu_111017_p1 == 6'd11) & ~(trunc_ln203_64_fu_111017_p1 == 6'd12) & ~(trunc_ln203_64_fu_111017_p1 == 6'd13) & ~(trunc_ln203_64_fu_111017_p1 == 6'd14) & ~(trunc_ln203_64_fu_111017_p1 == 6'd15) & ~(trunc_ln203_64_fu_111017_p1 == 6'd16) & ~(trunc_ln203_64_fu_111017_p1 == 6'd17) & ~(trunc_ln203_64_fu_111017_p1 == 6'd18) & ~(trunc_ln203_64_fu_111017_p1 == 6'd19) & ~(trunc_ln203_64_fu_111017_p1 == 6'd20) & ~(trunc_ln203_64_fu_111017_p1 == 6'd21) & ~(trunc_ln203_64_fu_111017_p1 == 6'd22) & ~(trunc_ln203_64_fu_111017_p1 == 6'd23) & ~(trunc_ln203_64_fu_111017_p1 == 6'd24) & ~(trunc_ln203_64_fu_111017_p1 == 6'd25) & ~(trunc_ln203_64_fu_111017_p1 == 6'd26) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | (~(trunc_ln203_41_fu_109339_p1 == 6'd0) & ~(trunc_ln203_41_fu_109339_p1 == 6'd1) & ~(trunc_ln203_41_fu_109339_p1 == 6'd2) & ~(trunc_ln203_41_fu_109339_p1 == 6'd3) & ~(trunc_ln203_41_fu_109339_p1 == 6'd4) & ~(trunc_ln203_41_fu_109339_p1 == 6'd5) & ~(trunc_ln203_41_fu_109339_p1 == 6'd6) & ~(trunc_ln203_41_fu_109339_p1 == 6'd7) & ~(trunc_ln203_41_fu_109339_p1 == 6'd8) & ~(trunc_ln203_41_fu_109339_p1 == 6'd9) & ~(trunc_ln203_41_fu_109339_p1 == 6'd10) & ~(trunc_ln203_41_fu_109339_p1 == 6'd11) & ~(trunc_ln203_41_fu_109339_p1 == 6'd12) & ~(trunc_ln203_41_fu_109339_p1 == 6'd13) & ~(trunc_ln203_41_fu_109339_p1 == 6'd14) & ~(trunc_ln203_41_fu_109339_p1 == 6'd15) & ~(trunc_ln203_41_fu_109339_p1 == 6'd16) & ~(trunc_ln203_41_fu_109339_p1 == 6'd17) & ~(trunc_ln203_41_fu_109339_p1 == 6'd18) & ~(trunc_ln203_41_fu_109339_p1 == 6'd19) & ~(trunc_ln203_41_fu_109339_p1 == 6'd20) & ~(trunc_ln203_41_fu_109339_p1 == 6'd21) & ~(trunc_ln203_41_fu_109339_p1 == 6'd22) & ~(trunc_ln203_41_fu_109339_p1 == 6'd23) & ~(trunc_ln203_41_fu_109339_p1 == 6'd24) & ~(trunc_ln203_41_fu_109339_p1 == 6'd25) & ~(trunc_ln203_41_fu_109339_p1 == 6'd26) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | (~(trunc_ln203_98_fu_108729_p1 == 6'd0) & ~(trunc_ln203_98_fu_108729_p1 == 6'd1) & ~(trunc_ln203_98_fu_108729_p1 == 6'd2) & ~(trunc_ln203_98_fu_108729_p1 == 6'd3) & ~(trunc_ln203_98_fu_108729_p1 == 6'd4) & ~(trunc_ln203_98_fu_108729_p1 == 6'd5) & ~(trunc_ln203_98_fu_108729_p1 == 6'd6) & ~(trunc_ln203_98_fu_108729_p1 == 6'd7) & ~(trunc_ln203_98_fu_108729_p1 == 6'd8) & ~(trunc_ln203_98_fu_108729_p1 == 6'd9) & ~(trunc_ln203_98_fu_108729_p1 == 6'd10) & ~(trunc_ln203_98_fu_108729_p1 == 6'd11) & ~(trunc_ln203_98_fu_108729_p1 == 6'd12) & ~(trunc_ln203_98_fu_108729_p1 == 6'd13) & ~(trunc_ln203_98_fu_108729_p1 == 6'd14) & ~(trunc_ln203_98_fu_108729_p1 == 6'd15) & ~(trunc_ln203_98_fu_108729_p1 == 6'd16) & ~(trunc_ln203_98_fu_108729_p1 == 6'd17) & ~(trunc_ln203_98_fu_108729_p1 == 6'd18) & ~(trunc_ln203_98_fu_108729_p1 == 6'd19) & ~(trunc_ln203_98_fu_108729_p1 == 6'd20) & ~(trunc_ln203_98_fu_108729_p1 == 6'd21) & ~(trunc_ln203_98_fu_108729_p1 == 6'd22) & ~(trunc_ln203_98_fu_108729_p1 == 6'd23) & ~(trunc_ln203_98_fu_108729_p1 == 6'd24) & ~(trunc_ln203_98_fu_108729_p1 == 6'd25) & ~(trunc_ln203_98_fu_108729_p1 == 6'd26) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | (~(trunc_ln203_90_fu_108380_p1 == 6'd0) & ~(trunc_ln203_90_fu_108380_p1 == 6'd1) & ~(trunc_ln203_90_fu_108380_p1 == 6'd2) & ~(trunc_ln203_90_fu_108380_p1 == 6'd3) & ~(trunc_ln203_90_fu_108380_p1 == 6'd4) & ~(trunc_ln203_90_fu_108380_p1 == 6'd5) & ~(trunc_ln203_90_fu_108380_p1 == 6'd6) & ~(trunc_ln203_90_fu_108380_p1 == 6'd7) & ~(trunc_ln203_90_fu_108380_p1 == 6'd8) & ~(trunc_ln203_90_fu_108380_p1 == 6'd9) & ~(trunc_ln203_90_fu_108380_p1 == 6'd10) & ~(trunc_ln203_90_fu_108380_p1 == 6'd11) & ~(trunc_ln203_90_fu_108380_p1 == 6'd12) & ~(trunc_ln203_90_fu_108380_p1 == 6'd13) & ~(trunc_ln203_90_fu_108380_p1 == 6'd14) & ~(trunc_ln203_90_fu_108380_p1 == 6'd15) & ~(trunc_ln203_90_fu_108380_p1 == 6'd16) & ~(trunc_ln203_90_fu_108380_p1 == 6'd17) & ~(trunc_ln203_90_fu_108380_p1 == 6'd18) & ~(trunc_ln203_90_fu_108380_p1 == 6'd19) & ~(trunc_ln203_90_fu_108380_p1 == 6'd20) & ~(trunc_ln203_90_fu_108380_p1 == 6'd21) & ~(trunc_ln203_90_fu_108380_p1 == 6'd22) & ~(trunc_ln203_90_fu_108380_p1 == 6'd23) & ~(trunc_ln203_90_fu_108380_p1 == 6'd24) & ~(trunc_ln203_90_fu_108380_p1 == 6'd25) & ~(trunc_ln203_90_fu_108380_p1 == 6'd26) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | (~(trunc_ln203_65_fu_107579_p1 == 6'd0) & ~(trunc_ln203_65_fu_107579_p1 == 6'd1) & ~(trunc_ln203_65_fu_107579_p1 == 6'd2) & ~(trunc_ln203_65_fu_107579_p1 == 6'd3) & ~(trunc_ln203_65_fu_107579_p1 == 6'd4) & ~(trunc_ln203_65_fu_107579_p1 == 6'd5) & ~(trunc_ln203_65_fu_107579_p1 == 6'd6) & ~(trunc_ln203_65_fu_107579_p1 == 6'd7) & ~(trunc_ln203_65_fu_107579_p1 == 6'd8) & ~(trunc_ln203_65_fu_107579_p1 == 6'd9) & ~(trunc_ln203_65_fu_107579_p1 == 6'd10) & ~(trunc_ln203_65_fu_107579_p1 == 6'd11) & ~(trunc_ln203_65_fu_107579_p1 == 6'd12) & ~(trunc_ln203_65_fu_107579_p1 == 6'd13) & ~(trunc_ln203_65_fu_107579_p1 == 6'd14) & ~(trunc_ln203_65_fu_107579_p1 == 6'd15) & ~(trunc_ln203_65_fu_107579_p1 == 6'd16) & ~(trunc_ln203_65_fu_107579_p1 == 6'd17) & ~(trunc_ln203_65_fu_107579_p1 == 6'd18) & ~(trunc_ln203_65_fu_107579_p1 == 6'd19) & ~(trunc_ln203_65_fu_107579_p1 == 6'd20) & ~(trunc_ln203_65_fu_107579_p1 == 6'd21) & ~(trunc_ln203_65_fu_107579_p1 == 6'd22) & ~(trunc_ln203_65_fu_107579_p1 == 6'd23) & ~(trunc_ln203_65_fu_107579_p1 == 6'd24) & ~(trunc_ln203_65_fu_107579_p1 == 6'd25) & ~(trunc_ln203_65_fu_107579_p1 == 6'd26) & (ap_ST_fsm_state955 == ap_CS_fsm) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | (~(trunc_ln203_42_fu_105898_p1 == 6'd0) & ~(trunc_ln203_42_fu_105898_p1 == 6'd1) & ~(trunc_ln203_42_fu_105898_p1 == 6'd2) & ~(trunc_ln203_42_fu_105898_p1 == 6'd3) & ~(trunc_ln203_42_fu_105898_p1 == 6'd4) & ~(trunc_ln203_42_fu_105898_p1 == 6'd5) & ~(trunc_ln203_42_fu_105898_p1 == 6'd6) & ~(trunc_ln203_42_fu_105898_p1 == 6'd7) & ~(trunc_ln203_42_fu_105898_p1 == 6'd8) & ~(trunc_ln203_42_fu_105898_p1 == 6'd9) & ~(trunc_ln203_42_fu_105898_p1 == 6'd10) & ~(trunc_ln203_42_fu_105898_p1 == 6'd11) & ~(trunc_ln203_42_fu_105898_p1 == 6'd12) & ~(trunc_ln203_42_fu_105898_p1 == 6'd13) & ~(trunc_ln203_42_fu_105898_p1 == 6'd14) & ~(trunc_ln203_42_fu_105898_p1 == 6'd15) & ~(trunc_ln203_42_fu_105898_p1 == 6'd16) & ~(trunc_ln203_42_fu_105898_p1 == 6'd17) & ~(trunc_ln203_42_fu_105898_p1 == 6'd18) & ~(trunc_ln203_42_fu_105898_p1 == 6'd19) & ~(trunc_ln203_42_fu_105898_p1 == 6'd20) & ~(trunc_ln203_42_fu_105898_p1 == 6'd21) & ~(trunc_ln203_42_fu_105898_p1 == 6'd22) & ~(trunc_ln203_42_fu_105898_p1 == 6'd23) & ~(trunc_ln203_42_fu_105898_p1 == 6'd24) & ~(trunc_ln203_42_fu_105898_p1 == 6'd25) & ~(trunc_ln203_42_fu_105898_p1 == 6'd26) & (ap_ST_fsm_state652 == ap_CS_fsm) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | (~(trunc_ln203_95_fu_105318_p1 == 6'd0) & ~(trunc_ln203_95_fu_105318_p1 == 6'd1) & ~(trunc_ln203_95_fu_105318_p1 == 6'd2) & ~(trunc_ln203_95_fu_105318_p1 == 6'd3) & ~(trunc_ln203_95_fu_105318_p1 == 6'd4) & ~(trunc_ln203_95_fu_105318_p1 == 6'd5) & ~(trunc_ln203_95_fu_105318_p1 == 6'd6) & ~(trunc_ln203_95_fu_105318_p1 == 6'd7) & ~(trunc_ln203_95_fu_105318_p1 == 6'd8) & ~(trunc_ln203_95_fu_105318_p1 == 6'd9) & ~(trunc_ln203_95_fu_105318_p1 == 6'd10) & ~(trunc_ln203_95_fu_105318_p1 == 6'd11) & ~(trunc_ln203_95_fu_105318_p1 == 6'd12) & ~(trunc_ln203_95_fu_105318_p1 == 6'd13) & ~(trunc_ln203_95_fu_105318_p1 == 6'd14) & ~(trunc_ln203_95_fu_105318_p1 == 6'd15) & ~(trunc_ln203_95_fu_105318_p1 == 6'd16) & ~(trunc_ln203_95_fu_105318_p1 == 6'd17) & ~(trunc_ln203_95_fu_105318_p1 == 6'd18) & ~(trunc_ln203_95_fu_105318_p1 == 6'd19) & ~(trunc_ln203_95_fu_105318_p1 == 6'd20) & ~(trunc_ln203_95_fu_105318_p1 == 6'd21) & ~(trunc_ln203_95_fu_105318_p1 == 6'd22) & ~(trunc_ln203_95_fu_105318_p1 == 6'd23) & ~(trunc_ln203_95_fu_105318_p1 == 6'd24) & ~(trunc_ln203_95_fu_105318_p1 == 6'd25) & ~(trunc_ln203_95_fu_105318_p1 == 6'd26) & (ap_ST_fsm_state573 == ap_CS_fsm) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | (~(trunc_ln203_85_fu_104968_p1 == 6'd0) & ~(trunc_ln203_85_fu_104968_p1 == 6'd1) & ~(trunc_ln203_85_fu_104968_p1 == 6'd2) & ~(trunc_ln203_85_fu_104968_p1 == 6'd3) & ~(trunc_ln203_85_fu_104968_p1 == 6'd4) & ~(trunc_ln203_85_fu_104968_p1 == 6'd5) & ~(trunc_ln203_85_fu_104968_p1 == 6'd6) & ~(trunc_ln203_85_fu_104968_p1 == 6'd7) & ~(trunc_ln203_85_fu_104968_p1 == 6'd8) & ~(trunc_ln203_85_fu_104968_p1 == 6'd9) & ~(trunc_ln203_85_fu_104968_p1 == 6'd10) & ~(trunc_ln203_85_fu_104968_p1 == 6'd11) & ~(trunc_ln203_85_fu_104968_p1 == 6'd12) & ~(trunc_ln203_85_fu_104968_p1 == 6'd13) & ~(trunc_ln203_85_fu_104968_p1 == 6'd14) & ~(trunc_ln203_85_fu_104968_p1 == 6'd15) & ~(trunc_ln203_85_fu_104968_p1 == 6'd16) & ~(trunc_ln203_85_fu_104968_p1 == 6'd17) & ~(trunc_ln203_85_fu_104968_p1 == 6'd18) & ~(trunc_ln203_85_fu_104968_p1 == 6'd19) & ~(trunc_ln203_85_fu_104968_p1 == 6'd20) & ~(trunc_ln203_85_fu_104968_p1 == 6'd21) & ~(trunc_ln203_85_fu_104968_p1 == 6'd22) & ~(trunc_ln203_85_fu_104968_p1 == 6'd23) & ~(trunc_ln203_85_fu_104968_p1 == 6'd24) & ~(trunc_ln203_85_fu_104968_p1 == 6'd25) & ~(trunc_ln203_85_fu_104968_p1 == 6'd26) & (ap_ST_fsm_state500 == ap_CS_fsm) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | (~(trunc_ln203_58_fu_104165_p1 == 6'd0) & ~(trunc_ln203_58_fu_104165_p1 == 6'd1) & ~(trunc_ln203_58_fu_104165_p1 == 6'd2) & ~(trunc_ln203_58_fu_104165_p1 == 6'd3) & ~(trunc_ln203_58_fu_104165_p1 == 6'd4) & ~(trunc_ln203_58_fu_104165_p1 == 6'd5) & ~(trunc_ln203_58_fu_104165_p1 == 6'd6) & ~(trunc_ln203_58_fu_104165_p1 == 6'd7) & ~(trunc_ln203_58_fu_104165_p1 == 6'd8) & ~(trunc_ln203_58_fu_104165_p1 == 6'd9) & ~(trunc_ln203_58_fu_104165_p1 == 6'd10) & ~(trunc_ln203_58_fu_104165_p1 == 6'd11) & ~(trunc_ln203_58_fu_104165_p1 == 6'd12) & ~(trunc_ln203_58_fu_104165_p1 == 6'd13) & ~(trunc_ln203_58_fu_104165_p1 == 6'd14) & ~(trunc_ln203_58_fu_104165_p1 == 6'd15) & ~(trunc_ln203_58_fu_104165_p1 == 6'd16) & ~(trunc_ln203_58_fu_104165_p1 == 6'd17) & ~(trunc_ln203_58_fu_104165_p1 == 6'd18) & ~(trunc_ln203_58_fu_104165_p1 == 6'd19) & ~(trunc_ln203_58_fu_104165_p1 == 6'd20) & ~(trunc_ln203_58_fu_104165_p1 == 6'd21) & ~(trunc_ln203_58_fu_104165_p1 == 6'd22) & ~(trunc_ln203_58_fu_104165_p1 == 6'd23) & ~(trunc_ln203_58_fu_104165_p1 == 6'd24) & ~(trunc_ln203_58_fu_104165_p1 == 6'd25) & ~(trunc_ln203_58_fu_104165_p1 == 6'd26) & (ap_ST_fsm_state350 == ap_CS_fsm) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_27_V_we0 = 1'b1; + end else begin + mult_27_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_2_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_2_V_ce0 = 1'b1; + end else begin + mult_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_2_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_2_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2423 == ap_CS_fsm) & (trunc_ln203_96_fu_115623_p1 == 6'd2)) | ((trunc_ln203_87_fu_115485_p1 == 6'd2) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd2) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd2) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd2) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd2) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd2) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd2) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd2) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd2) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd2) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd2) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd2) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd2) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd2) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd2) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd2) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd2) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd2) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd2) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd2) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd2) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd2) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd2) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd2) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd2) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd2) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd2) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd2)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd2)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd2)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd2)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd2)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd2)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd2)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd2)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd2)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd2)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd2)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd2)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd2)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd2)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd2)) | ((trunc_ln203_47_fu_103635_p1 == 6'd2) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd2) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd2) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd2) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd2)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd2)) | ((trunc_ln203_99_fu_115563_p1 == 6'd2) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd2) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd2) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd2) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd2) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd2) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd2) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd2) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd2) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd2) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd2) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd2) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd2) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd2) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd2) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_2_V_we0 = 1'b1; + end else begin + mult_2_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_3_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_3_V_ce0 = 1'b1; + end else begin + mult_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_3_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_3_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_96_fu_115623_p1 == 6'd3) & (ap_ST_fsm_state2423 == ap_CS_fsm)) | ((trunc_ln203_87_fu_115485_p1 == 6'd3) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd3) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd3) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd3) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd3) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd3) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd3) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd3) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd3) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd3) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd3) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd3) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd3) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd3) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd3) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd3) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd3) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd3) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd3) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd3) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd3) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd3) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd3) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd3) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd3) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd3) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd3) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd3)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd3)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd3)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd3)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd3)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd3)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd3)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd3)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd3)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd3)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd3)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd3)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd3)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd3)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd3)) | ((trunc_ln203_47_fu_103635_p1 == 6'd3) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd3) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd3) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd3) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd3)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd3)) | ((trunc_ln203_99_fu_115563_p1 == 6'd3) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd3) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd3) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd3) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd3) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd3) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd3) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd3) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd3) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd3) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd3) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd3) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd3) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd3) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd3) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_3_V_we0 = 1'b1; + end else begin + mult_3_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_4_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_4_V_ce0 = 1'b1; + end else begin + mult_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_4_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_4_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2423 == ap_CS_fsm) & (trunc_ln203_96_fu_115623_p1 == 6'd4)) | ((trunc_ln203_87_fu_115485_p1 == 6'd4) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd4) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd4) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd4) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd4) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd4) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd4) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd4) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd4) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd4) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd4) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd4) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd4) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd4) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd4) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd4) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd4) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd4) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd4) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd4) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd4) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd4) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd4) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd4) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd4) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd4) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd4) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd4)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd4)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd4)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd4)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd4)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd4)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd4)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd4)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd4)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd4)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd4)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd4)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd4)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd4)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd4)) | ((trunc_ln203_47_fu_103635_p1 == 6'd4) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd4) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd4) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd4) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd4)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd4)) | ((trunc_ln203_99_fu_115563_p1 == 6'd4) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd4) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd4) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd4) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd4) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd4) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd4) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd4) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd4) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd4) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd4) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd4) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd4) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd4) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd4) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_4_V_we0 = 1'b1; + end else begin + mult_4_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_5_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_5_V_ce0 = 1'b1; + end else begin + mult_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_5_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_5_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_96_fu_115623_p1 == 6'd5) & (ap_ST_fsm_state2423 == ap_CS_fsm)) | ((trunc_ln203_87_fu_115485_p1 == 6'd5) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd5) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd5) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd5) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd5) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd5) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd5) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd5) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd5) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd5) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd5) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd5) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd5) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd5) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd5) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd5) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd5) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd5) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd5) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd5) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd5) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd5) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd5) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd5) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd5) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd5) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd5) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd5)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd5)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd5)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd5)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd5)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd5)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd5)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd5)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd5)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd5)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd5)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd5)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd5)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd5)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd5)) | ((trunc_ln203_47_fu_103635_p1 == 6'd5) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd5) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd5) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd5) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd5)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd5)) | ((trunc_ln203_99_fu_115563_p1 == 6'd5) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd5) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd5) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd5) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd5) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd5) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd5) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd5) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd5) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd5) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd5) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd5) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd5) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd5) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd5) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_5_V_we0 = 1'b1; + end else begin + mult_5_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_6_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_6_V_ce0 = 1'b1; + end else begin + mult_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_6_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_6_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2423 == ap_CS_fsm) & (trunc_ln203_96_fu_115623_p1 == 6'd6)) | ((trunc_ln203_87_fu_115485_p1 == 6'd6) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd6) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd6) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd6) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd6) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd6) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd6) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd6) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd6) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd6) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd6) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd6) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd6) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd6) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd6) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd6) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd6) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd6) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd6) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd6) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd6) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd6) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd6) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd6) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd6) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd6) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd6) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd6)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd6)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd6)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd6)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd6)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd6)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd6)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd6)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd6)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd6)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd6)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd6)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd6)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd6)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd6)) | ((trunc_ln203_47_fu_103635_p1 == 6'd6) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd6) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd6) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd6) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd6)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd6)) | ((trunc_ln203_99_fu_115563_p1 == 6'd6) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd6) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd6) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd6) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd6) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd6) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd6) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd6) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd6) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd6) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd6) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd6) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd6) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd6) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd6) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_6_V_we0 = 1'b1; + end else begin + mult_6_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_7_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_7_V_ce0 = 1'b1; + end else begin + mult_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_7_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_7_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_96_fu_115623_p1 == 6'd7) & (ap_ST_fsm_state2423 == ap_CS_fsm)) | ((trunc_ln203_87_fu_115485_p1 == 6'd7) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd7) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd7) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd7) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd7) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd7) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd7) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd7) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd7) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd7) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd7) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd7) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd7) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd7) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd7) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd7) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd7) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd7) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd7) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd7) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd7) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd7) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd7) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd7) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd7) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd7) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd7) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd7)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd7)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd7)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd7)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd7)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd7)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd7)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd7)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd7)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd7)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd7)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd7)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd7)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd7)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd7)) | ((trunc_ln203_47_fu_103635_p1 == 6'd7) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd7) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd7) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd7) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd7)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd7)) | ((trunc_ln203_99_fu_115563_p1 == 6'd7) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd7) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd7) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd7) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd7) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd7) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd7) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd7) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd7) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd7) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd7) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd7) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd7) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd7) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd7) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_7_V_we0 = 1'b1; + end else begin + mult_7_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_8_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_8_V_ce0 = 1'b1; + end else begin + mult_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_8_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_8_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state2423 == ap_CS_fsm) & (trunc_ln203_96_fu_115623_p1 == 6'd8)) | ((trunc_ln203_87_fu_115485_p1 == 6'd8) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd8) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd8) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd8) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd8) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd8) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd8) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd8) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd8) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd8) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd8) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd8) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd8) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd8) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd8) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd8) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd8) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd8) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd8) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd8) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd8) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd8) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd8) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd8) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd8) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd8) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd8) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd8)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd8)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd8)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd8)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd8)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd8)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd8)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd8)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd8)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd8)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd8)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd8)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd8)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd8)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd8)) | ((trunc_ln203_47_fu_103635_p1 == 6'd8) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd8) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd8) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd8) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd8)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd8)) | ((trunc_ln203_99_fu_115563_p1 == 6'd8) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd8) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd8) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd8) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd8) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd8) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd8) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd8) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd8) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd8) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd8) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd8) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd8) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd8) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd8) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_8_V_we0 = 1'b1; + end else begin + mult_8_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5024 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_71_fu_131207_p1; + end else if ((ap_ST_fsm_state4988 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_67_fu_130997_p1; + end else if ((ap_ST_fsm_state4949 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_56_fu_130832_p1; + end else if ((ap_ST_fsm_state4913 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_47_fu_130593_p1; + end else if ((ap_ST_fsm_state4873 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_55_fu_130411_p1; + end else if ((ap_ST_fsm_state4836 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_43_fu_130201_p1; + end else if ((ap_ST_fsm_state4796 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_25_fu_130036_p1; + end else if ((ap_ST_fsm_state4760 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_19_fu_129786_p1; + end else if ((ap_ST_fsm_state4719 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_68_fu_129584_p1; + end else if ((ap_ST_fsm_state4683 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_61_fu_129374_p1; + end else if ((ap_ST_fsm_state4644 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_51_fu_129208_p1; + end else if ((ap_ST_fsm_state4608 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_37_fu_128969_p1; + end else if ((ap_ST_fsm_state4568 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_48_fu_128786_p1; + end else if ((ap_ST_fsm_state4531 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_33_fu_128576_p1; + end else if ((ap_ST_fsm_state4491 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_20_fu_128410_p1; + end else if ((ap_ST_fsm_state4454 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_13_fu_128160_p1; + end else if ((ap_ST_fsm_state4412 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_69_fu_127739_p1; + end else if ((ap_ST_fsm_state4376 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_62_fu_127529_p1; + end else if ((ap_ST_fsm_state4337 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_52_fu_127364_p1; + end else if ((ap_ST_fsm_state4301 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_38_fu_127125_p1; + end else if ((ap_ST_fsm_state4261 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_49_fu_126943_p1; + end else if ((ap_ST_fsm_state4224 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_34_fu_126733_p1; + end else if ((ap_ST_fsm_state4184 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_21_fu_126568_p1; + end else if ((ap_ST_fsm_state4147 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_14_fu_126318_p1; + end else if ((ap_ST_fsm_state4106 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_64_fu_126116_p1; + end else if ((ap_ST_fsm_state4070 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_57_fu_125906_p1; + end else if ((ap_ST_fsm_state4031 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_44_fu_125740_p1; + end else if ((ap_ST_fsm_state3995 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_29_fu_125501_p1; + end else if ((ap_ST_fsm_state3954 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_39_fu_125318_p1; + end else if ((ap_ST_fsm_state3917 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_26_fu_125108_p1; + end else if ((ap_ST_fsm_state3877 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_16_fu_124942_p1; + end else if ((ap_ST_fsm_state3840 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_9_fu_124692_p1; + end else if ((ap_ST_fsm_state3797 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_70_fu_124165_p1; + end else if ((ap_ST_fsm_state3761 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_63_fu_123955_p1; + end else if ((ap_ST_fsm_state3722 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_53_fu_123790_p1; + end else if ((ap_ST_fsm_state3686 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_40_fu_123551_p1; + end else if ((ap_ST_fsm_state3646 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_50_fu_123369_p1; + end else if ((ap_ST_fsm_state3609 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_35_fu_123159_p1; + end else if ((ap_ST_fsm_state3569 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_22_fu_122994_p1; + end else if ((ap_ST_fsm_state3532 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_15_fu_122744_p1; + end else if ((ap_ST_fsm_state3491 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_65_fu_122542_p1; + end else if ((ap_ST_fsm_state3455 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_58_fu_122332_p1; + end else if ((ap_ST_fsm_state3416 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_45_fu_122166_p1; + end else if ((ap_ST_fsm_state3380 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_30_fu_121927_p1; + end else if ((ap_ST_fsm_state3339 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_41_fu_121744_p1; + end else if ((ap_ST_fsm_state3302 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_27_fu_121534_p1; + end else if ((ap_ST_fsm_state3262 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_17_fu_121368_p1; + end else if ((ap_ST_fsm_state3225 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_10_fu_121118_p1; + end else if ((ap_ST_fsm_state3183 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_66_fu_120697_p1; + end else if ((ap_ST_fsm_state3147 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_59_fu_120487_p1; + end else if ((ap_ST_fsm_state3108 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_46_fu_120322_p1; + end else if ((ap_ST_fsm_state3072 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_31_fu_120083_p1; + end else if ((ap_ST_fsm_state3031 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_42_fu_119901_p1; + end else if ((ap_ST_fsm_state2994 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_28_fu_119691_p1; + end else if ((ap_ST_fsm_state2954 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_18_fu_119526_p1; + end else if ((ap_ST_fsm_state2917 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_11_fu_119276_p1; + end else if ((ap_ST_fsm_state2876 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_60_fu_119074_p1; + end else if ((ap_ST_fsm_state2840 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_54_fu_118864_p1; + end else if ((ap_ST_fsm_state2801 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_36_fu_118698_p1; + end else if ((ap_ST_fsm_state2764 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_24_fu_118459_p1; + end else if ((ap_ST_fsm_state2723 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_32_fu_118276_p1; + end else if ((ap_ST_fsm_state2686 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_23_fu_118066_p1; + end else if ((ap_ST_fsm_state2646 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_12_fu_117900_p1; + end else if ((ap_ST_fsm_state2609 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_8_fu_117650_p1; + end else if ((ap_ST_fsm_state2423 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_82_fu_115627_p1; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_85_fu_115567_p1; + end else if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_73_fu_115489_p1; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_77_fu_115218_p1; + end else if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_66_fu_114941_p1; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_74_fu_114881_p1; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_49_fu_114803_p1; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_53_fu_114417_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_63_fu_114035_p1; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_72_fu_113975_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_45_fu_113897_p1; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_52_fu_113624_p1; + end else if ((ap_ST_fsm_state1972 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_36_fu_113345_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_46_fu_113285_p1; + end else if ((ap_ST_fsm_state1897 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_25_fu_113207_p1; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_29_fu_112745_p1; + end else if ((ap_ST_fsm_state1819 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_79_fu_112236_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_83_fu_112176_p1; + end else if ((ap_ST_fsm_state1746 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_67_fu_112098_p1; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_75_fu_111826_p1; + end else if ((ap_ST_fsm_state1671 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_59_fu_111552_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_68_fu_111492_p1; + end else if ((ap_ST_fsm_state1596 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_42_fu_111414_p1; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_50_fu_111021_p1; + end else if ((ap_ST_fsm_state1520 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_56_fu_110638_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_64_fu_110578_p1; + end else if ((ap_ST_fsm_state1445 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_37_fu_110500_p1; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_47_fu_110226_p1; + end else if ((ap_ST_fsm_state1368 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_31_fu_109950_p1; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_38_fu_109890_p1; + end else if ((ap_ST_fsm_state1293 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_18_fu_109812_p1; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_26_fu_109343_p1; + end else if ((ap_ST_fsm_state1213 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_80_fu_108793_p1; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_84_fu_108733_p1; + end else if ((ap_ST_fsm_state1140 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_69_fu_108655_p1; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_76_fu_108384_p1; + end else if ((ap_ST_fsm_state1065 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_60_fu_108107_p1; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_70_fu_108047_p1; + end else if ((ap_ST_fsm_state990 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_43_fu_107969_p1; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_51_fu_107583_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_57_fu_107192_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_65_fu_107132_p1; + end else if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_39_fu_107054_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_48_fu_106781_p1; + end else if ((ap_ST_fsm_state762 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_32_fu_106502_p1; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_40_fu_106442_p1; + end else if ((ap_ST_fsm_state687 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_19_fu_106364_p1; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_27_fu_105902_p1; + end else if ((ap_ST_fsm_state608 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_78_fu_105382_p1; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_81_fu_105322_p1; + end else if ((ap_ST_fsm_state535 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_61_fu_105244_p1; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_71_fu_104972_p1; + end else if ((ap_ST_fsm_state460 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_55_fu_104694_p1; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_62_fu_104634_p1; + end else if ((ap_ST_fsm_state385 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_35_fu_104556_p1; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_44_fu_104169_p1; + end else if ((ap_ST_fsm_state309 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_54_fu_103777_p1; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_58_fu_103717_p1; + end else if ((ap_ST_fsm_state234 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_33_fu_103639_p1; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_41_fu_103365_p1; + end else if ((ap_ST_fsm_state157 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_30_fu_103085_p1; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_34_fu_103025_p1; + end else if ((ap_ST_fsm_state82 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_13_fu_102947_p1; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_20_fu_102483_p1; + end else begin + mult_9_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state955 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state726 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state652 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state573 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state500 == ap_CS_fsm) | (ap_ST_fsm_state5024 == ap_CS_fsm) | (ap_ST_fsm_state4988 == ap_CS_fsm) | (ap_ST_fsm_state4949 == ap_CS_fsm) | (ap_ST_fsm_state4913 == ap_CS_fsm) | (ap_ST_fsm_state46 == ap_CS_fsm) | (ap_ST_fsm_state4873 == ap_CS_fsm) | (ap_ST_fsm_state4836 == ap_CS_fsm) | (ap_ST_fsm_state4796 == ap_CS_fsm) | (ap_ST_fsm_state4760 == ap_CS_fsm) | (ap_ST_fsm_state4719 == ap_CS_fsm) | (ap_ST_fsm_state4683 == ap_CS_fsm) | (ap_ST_fsm_state4644 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state4608 == ap_CS_fsm) | (ap_ST_fsm_state4568 == ap_CS_fsm) | (ap_ST_fsm_state4531 == ap_CS_fsm) | (ap_ST_fsm_state4491 == ap_CS_fsm) | (ap_ST_fsm_state4454 == ap_CS_fsm) | (ap_ST_fsm_state4412 == ap_CS_fsm) | (ap_ST_fsm_state4376 == ap_CS_fsm) | (ap_ST_fsm_state4337 == ap_CS_fsm) | (ap_ST_fsm_state4301 == ap_CS_fsm) | (ap_ST_fsm_state424 == ap_CS_fsm) | (ap_ST_fsm_state4261 == ap_CS_fsm) | (ap_ST_fsm_state4224 == ap_CS_fsm) | (ap_ST_fsm_state4184 == ap_CS_fsm) | (ap_ST_fsm_state4147 == ap_CS_fsm) | (ap_ST_fsm_state4106 == ap_CS_fsm) | (ap_ST_fsm_state4070 == ap_CS_fsm) | (ap_ST_fsm_state4031 == ap_CS_fsm) | (ap_ST_fsm_state3995 == ap_CS_fsm) | (ap_ST_fsm_state3954 == ap_CS_fsm) | (ap_ST_fsm_state3917 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state3877 == ap_CS_fsm) | (ap_ST_fsm_state3840 == ap_CS_fsm) | (ap_ST_fsm_state3797 == ap_CS_fsm) | (ap_ST_fsm_state3761 == ap_CS_fsm) | (ap_ST_fsm_state3722 == ap_CS_fsm) | (ap_ST_fsm_state3686 == ap_CS_fsm) | (ap_ST_fsm_state3646 == ap_CS_fsm) | (ap_ST_fsm_state3609 == ap_CS_fsm) | (ap_ST_fsm_state3569 == ap_CS_fsm) | (ap_ST_fsm_state3532 == ap_CS_fsm) | (ap_ST_fsm_state350 == ap_CS_fsm) | (ap_ST_fsm_state3491 == ap_CS_fsm) | (ap_ST_fsm_state3455 == ap_CS_fsm) | (ap_ST_fsm_state3416 == ap_CS_fsm) | (ap_ST_fsm_state3380 == ap_CS_fsm) | (ap_ST_fsm_state3339 == ap_CS_fsm) | (ap_ST_fsm_state3302 == ap_CS_fsm) | (ap_ST_fsm_state3262 == ap_CS_fsm) | (ap_ST_fsm_state3225 == ap_CS_fsm) | (ap_ST_fsm_state3183 == ap_CS_fsm) | (ap_ST_fsm_state3147 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state3108 == ap_CS_fsm) | (ap_ST_fsm_state3072 == ap_CS_fsm) | (ap_ST_fsm_state3031 == ap_CS_fsm) | (ap_ST_fsm_state2994 == ap_CS_fsm) | (ap_ST_fsm_state2954 == ap_CS_fsm) | (ap_ST_fsm_state2917 == ap_CS_fsm) | (ap_ST_fsm_state2876 == ap_CS_fsm) | (ap_ST_fsm_state2840 == ap_CS_fsm) | (ap_ST_fsm_state2801 == ap_CS_fsm) | (ap_ST_fsm_state2764 == ap_CS_fsm) | (ap_ST_fsm_state273 == ap_CS_fsm) | (ap_ST_fsm_state2723 == ap_CS_fsm) | (ap_ST_fsm_state2686 == ap_CS_fsm) | (ap_ST_fsm_state2646 == ap_CS_fsm) | (ap_ST_fsm_state2609 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2315 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2239 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2165 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2088 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state198 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1862 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1711 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1561 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1409 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1332 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1258 == ap_CS_fsm) | (ap_ST_fsm_state121 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1105 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm) | (ap_ST_fsm_state1029 == ap_CS_fsm))) begin + mult_9_V_ce0 = 1'b1; + end else begin + mult_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_39_reg_145923; + end else if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_35_reg_145517; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_32_reg_145083; + end else if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_23_reg_144642; + end else if ((ap_ST_fsm_state2088 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_31_reg_144186; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_22_reg_143775; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_17_reg_143348; + end else if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_12_reg_142883; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_37_reg_142360; + end else if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_33_reg_141954; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_28_reg_141524; + end else if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_20_reg_141089; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_26_reg_140633; + end else if ((ap_ST_fsm_state1409 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_18_reg_140222; + end else if ((ap_ST_fsm_state1332 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_14_reg_139799; + end else if ((ap_ST_fsm_state1258 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_10_reg_139340; + end else if ((ap_ST_fsm_state1178 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_38_reg_138768; + end else if ((ap_ST_fsm_state1105 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_34_reg_138362; + end else if ((ap_ST_fsm_state1029 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_29_reg_137928; + end else if ((ap_ST_fsm_state955 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_21_reg_137487; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_27_reg_137026; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_19_reg_136615; + end else if ((ap_ST_fsm_state726 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_s_reg_136188; + end else if ((ap_ST_fsm_state652 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_11_reg_135719; + end else if ((ap_ST_fsm_state573 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_36_reg_135197; + end else if ((ap_ST_fsm_state500 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_30_reg_134791; + end else if ((ap_ST_fsm_state424 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_25_reg_134357; + end else if ((ap_ST_fsm_state350 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_16_reg_133916; + end else if ((ap_ST_fsm_state273 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_24_reg_133455; + end else if ((ap_ST_fsm_state198 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_15_reg_133044; + end else if ((ap_ST_fsm_state121 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_13_reg_132617; + end else if (((ap_ST_fsm_state990 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state82 == ap_CS_fsm) | (ap_ST_fsm_state839 == ap_CS_fsm) | (ap_ST_fsm_state762 == ap_CS_fsm) | (ap_ST_fsm_state687 == ap_CS_fsm) | (ap_ST_fsm_state608 == ap_CS_fsm) | (ap_ST_fsm_state535 == ap_CS_fsm) | (ap_ST_fsm_state460 == ap_CS_fsm) | (ap_ST_fsm_state385 == ap_CS_fsm) | (ap_ST_fsm_state309 == ap_CS_fsm) | (ap_ST_fsm_state2423 == ap_CS_fsm) | (ap_ST_fsm_state234 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2275 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state1972 == ap_CS_fsm) | (ap_ST_fsm_state1897 == ap_CS_fsm) | (ap_ST_fsm_state1819 == ap_CS_fsm) | (ap_ST_fsm_state1746 == ap_CS_fsm) | (ap_ST_fsm_state1671 == ap_CS_fsm) | (ap_ST_fsm_state157 == ap_CS_fsm) | (ap_ST_fsm_state1596 == ap_CS_fsm) | (ap_ST_fsm_state1520 == ap_CS_fsm) | (ap_ST_fsm_state1445 == ap_CS_fsm) | (ap_ST_fsm_state1368 == ap_CS_fsm) | (ap_ST_fsm_state1293 == ap_CS_fsm) | (ap_ST_fsm_state1213 == ap_CS_fsm) | (ap_ST_fsm_state1140 == ap_CS_fsm) | (ap_ST_fsm_state1065 == ap_CS_fsm))) begin + mult_9_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state46 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln2_reg_132148; + end else begin + mult_9_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_96_fu_115623_p1 == 6'd9) & (ap_ST_fsm_state2423 == ap_CS_fsm)) | ((trunc_ln203_87_fu_115485_p1 == 6'd9) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((trunc_ln203_80_fu_114937_p1 == 6'd9) & (ap_ST_fsm_state2275 == ap_CS_fsm)) | ((trunc_ln203_88_fu_114877_p1 == 6'd9) & (ap_ST_fsm_state2239 == ap_CS_fsm)) | ((trunc_ln203_63_fu_114799_p1 == 6'd9) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((trunc_ln203_77_fu_114031_p1 == 6'd9) & (ap_ST_fsm_state2124 == ap_CS_fsm)) | ((trunc_ln203_86_fu_113971_p1 == 6'd9) & (ap_ST_fsm_state2088 == ap_CS_fsm)) | ((trunc_ln203_59_fu_113893_p1 == 6'd9) & (ap_ST_fsm_state2049 == ap_CS_fsm)) | ((trunc_ln203_66_fu_113620_p1 == 6'd9) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((trunc_ln203_50_fu_113341_p1 == 6'd9) & (ap_ST_fsm_state1972 == ap_CS_fsm)) | ((trunc_ln203_60_fu_113281_p1 == 6'd9) & (ap_ST_fsm_state1936 == ap_CS_fsm)) | ((trunc_ln203_40_fu_113203_p1 == 6'd9) & (ap_ST_fsm_state1897 == ap_CS_fsm)) | ((trunc_ln203_93_fu_112232_p1 == 6'd9) & (ap_ST_fsm_state1819 == ap_CS_fsm)) | ((trunc_ln203_81_fu_112094_p1 == 6'd9) & (ap_ST_fsm_state1746 == ap_CS_fsm)) | ((trunc_ln203_73_fu_111548_p1 == 6'd9) & (ap_ST_fsm_state1671 == ap_CS_fsm)) | ((trunc_ln203_82_fu_111488_p1 == 6'd9) & (ap_ST_fsm_state1635 == ap_CS_fsm)) | ((trunc_ln203_56_fu_111410_p1 == 6'd9) & (ap_ST_fsm_state1596 == ap_CS_fsm)) | ((trunc_ln203_70_fu_110634_p1 == 6'd9) & (ap_ST_fsm_state1520 == ap_CS_fsm)) | ((trunc_ln203_78_fu_110574_p1 == 6'd9) & (ap_ST_fsm_state1484 == ap_CS_fsm)) | ((trunc_ln203_51_fu_110496_p1 == 6'd9) & (ap_ST_fsm_state1445 == ap_CS_fsm)) | ((trunc_ln203_61_fu_110222_p1 == 6'd9) & (ap_ST_fsm_state1409 == ap_CS_fsm)) | ((trunc_ln203_45_fu_109946_p1 == 6'd9) & (ap_ST_fsm_state1368 == ap_CS_fsm)) | ((trunc_ln203_52_fu_109886_p1 == 6'd9) & (ap_ST_fsm_state1332 == ap_CS_fsm)) | ((trunc_ln203_37_fu_109808_p1 == 6'd9) & (ap_ST_fsm_state1293 == ap_CS_fsm)) | ((trunc_ln203_94_fu_108789_p1 == 6'd9) & (ap_ST_fsm_state1213 == ap_CS_fsm)) | ((trunc_ln203_83_fu_108651_p1 == 6'd9) & (ap_ST_fsm_state1140 == ap_CS_fsm)) | ((trunc_ln203_74_fu_108103_p1 == 6'd9) & (ap_ST_fsm_state1065 == ap_CS_fsm)) | ((trunc_ln203_84_fu_108043_p1 == 6'd9) & (ap_ST_fsm_state1029 == ap_CS_fsm)) | ((ap_ST_fsm_state990 == ap_CS_fsm) & (trunc_ln203_57_fu_107965_p1 == 6'd9)) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (trunc_ln203_71_fu_107188_p1 == 6'd9)) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (trunc_ln203_79_fu_107128_p1 == 6'd9)) | ((ap_ST_fsm_state839 == ap_CS_fsm) & (trunc_ln203_53_fu_107050_p1 == 6'd9)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_62_fu_106777_p1 == 6'd9)) | ((ap_ST_fsm_state762 == ap_CS_fsm) & (trunc_ln203_46_fu_106498_p1 == 6'd9)) | ((ap_ST_fsm_state726 == ap_CS_fsm) & (trunc_ln203_54_fu_106438_p1 == 6'd9)) | ((ap_ST_fsm_state687 == ap_CS_fsm) & (trunc_ln203_38_fu_106360_p1 == 6'd9)) | ((ap_ST_fsm_state608 == ap_CS_fsm) & (trunc_ln203_92_fu_105378_p1 == 6'd9)) | ((ap_ST_fsm_state535 == ap_CS_fsm) & (trunc_ln203_75_fu_105240_p1 == 6'd9)) | ((ap_ST_fsm_state460 == ap_CS_fsm) & (trunc_ln203_69_fu_104690_p1 == 6'd9)) | ((ap_ST_fsm_state424 == ap_CS_fsm) & (trunc_ln203_76_fu_104630_p1 == 6'd9)) | ((ap_ST_fsm_state385 == ap_CS_fsm) & (trunc_ln203_49_fu_104552_p1 == 6'd9)) | ((ap_ST_fsm_state309 == ap_CS_fsm) & (trunc_ln203_68_fu_103773_p1 == 6'd9)) | ((ap_ST_fsm_state273 == ap_CS_fsm) & (trunc_ln203_72_fu_103713_p1 == 6'd9)) | ((trunc_ln203_47_fu_103635_p1 == 6'd9) & (ap_ST_fsm_state234 == ap_CS_fsm)) | ((trunc_ln203_55_fu_103361_p1 == 6'd9) & (ap_ST_fsm_state198 == ap_CS_fsm)) | ((trunc_ln203_44_fu_103081_p1 == 6'd9) & (ap_ST_fsm_state157 == ap_CS_fsm)) | ((trunc_ln203_48_fu_103021_p1 == 6'd9) & (ap_ST_fsm_state121 == ap_CS_fsm)) | ((ap_ST_fsm_state82 == ap_CS_fsm) & (trunc_ln203_fu_102943_p1 == 6'd9)) | ((ap_ST_fsm_state46 == ap_CS_fsm) & (trunc_ln203_39_fu_102479_p1 == 6'd9)) | ((trunc_ln203_99_fu_115563_p1 == 6'd9) & (ap_ST_fsm_state2388 == ap_CS_fsm) & (or_ln223_47_reg_145567 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_91_fu_115214_p1 == 6'd9) & (ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_43_reg_145162 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0)) | ((trunc_ln203_67_fu_114413_p1 == 6'd9) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_27_reg_144287 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0)) | ((trunc_ln203_43_fu_112741_p1 == 6'd9) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_7_reg_142523 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0)) | ((trunc_ln203_97_fu_112172_p1 == 6'd9) & (ap_ST_fsm_state1784 == ap_CS_fsm) & (or_ln223_45_reg_142004 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0)) | ((trunc_ln203_89_fu_111822_p1 == 6'd9) & (or_ln223_41_reg_141599 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm)) | ((trunc_ln203_64_fu_111017_p1 == 6'd9) & (or_ln223_24_reg_140734 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm)) | ((trunc_ln203_41_fu_109339_p1 == 6'd9) & (or_ln223_5_reg_138980 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm)) | ((trunc_ln203_98_fu_108729_p1 == 6'd9) & (or_ln223_46_reg_138412 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1178 == ap_CS_fsm)) | ((trunc_ln203_90_fu_108380_p1 == 6'd9) & (or_ln223_42_reg_138007 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm)) | ((ap_ST_fsm_state955 == ap_CS_fsm) & (trunc_ln203_65_fu_107579_p1 == 6'd9) & (or_ln223_25_reg_137132 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0)) | ((ap_ST_fsm_state652 == ap_CS_fsm) & (trunc_ln203_42_fu_105898_p1 == 6'd9) & (or_ln223_6_reg_135359 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0)) | ((ap_ST_fsm_state573 == ap_CS_fsm) & (trunc_ln203_95_fu_105318_p1 == 6'd9) & (or_ln223_44_reg_134841 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state500 == ap_CS_fsm) & (trunc_ln203_85_fu_104968_p1 == 6'd9) & (or_ln223_37_reg_134436 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0)) | ((ap_ST_fsm_state350 == ap_CS_fsm) & (trunc_ln203_58_fu_104165_p1 == 6'd9) & (or_ln223_18_reg_133561 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0)))) begin + mult_9_V_we0 = 1'b1; + end else begin + mult_9_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd0; + end else begin + res_0_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_0_V_ce0 = 1'b1; + end else begin + res_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_0_V_we0 = 1'b1; + end else begin + res_0_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd0; + end else begin + res_100_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_100_V_ce0 = 1'b1; + end else begin + res_100_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_100_V_we0 = 1'b1; + end else begin + res_100_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd0; + end else begin + res_101_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_101_V_ce0 = 1'b1; + end else begin + res_101_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_101_V_we0 = 1'b1; + end else begin + res_101_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd0; + end else begin + res_102_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_102_V_ce0 = 1'b1; + end else begin + res_102_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_102_V_we0 = 1'b1; + end else begin + res_102_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd0; + end else begin + res_103_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_103_V_ce0 = 1'b1; + end else begin + res_103_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_103_V_we0 = 1'b1; + end else begin + res_103_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd0; + end else begin + res_104_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_104_V_ce0 = 1'b1; + end else begin + res_104_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_104_V_we0 = 1'b1; + end else begin + res_104_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd0; + end else begin + res_105_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_105_V_ce0 = 1'b1; + end else begin + res_105_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_105_V_we0 = 1'b1; + end else begin + res_105_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd0; + end else begin + res_106_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_106_V_ce0 = 1'b1; + end else begin + res_106_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_106_V_we0 = 1'b1; + end else begin + res_106_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd0; + end else begin + res_107_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_107_V_ce0 = 1'b1; + end else begin + res_107_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_107_V_we0 = 1'b1; + end else begin + res_107_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd0; + end else begin + res_108_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_108_V_ce0 = 1'b1; + end else begin + res_108_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_108_V_we0 = 1'b1; + end else begin + res_108_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd0; + end else begin + res_109_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_109_V_ce0 = 1'b1; + end else begin + res_109_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_109_V_we0 = 1'b1; + end else begin + res_109_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd0; + end else begin + res_10_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_10_V_ce0 = 1'b1; + end else begin + res_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_10_V_we0 = 1'b1; + end else begin + res_10_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd0; + end else begin + res_110_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_110_V_ce0 = 1'b1; + end else begin + res_110_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_110_V_we0 = 1'b1; + end else begin + res_110_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd0; + end else begin + res_111_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_111_V_ce0 = 1'b1; + end else begin + res_111_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_111_V_we0 = 1'b1; + end else begin + res_111_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd0; + end else begin + res_112_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_112_V_ce0 = 1'b1; + end else begin + res_112_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_112_V_we0 = 1'b1; + end else begin + res_112_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd0; + end else begin + res_113_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_113_V_ce0 = 1'b1; + end else begin + res_113_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_113_V_we0 = 1'b1; + end else begin + res_113_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd0; + end else begin + res_114_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_114_V_ce0 = 1'b1; + end else begin + res_114_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_114_V_we0 = 1'b1; + end else begin + res_114_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd0; + end else begin + res_115_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_115_V_ce0 = 1'b1; + end else begin + res_115_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_115_V_we0 = 1'b1; + end else begin + res_115_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd0; + end else begin + res_116_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_116_V_ce0 = 1'b1; + end else begin + res_116_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_116_V_we0 = 1'b1; + end else begin + res_116_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd0; + end else begin + res_117_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_117_V_ce0 = 1'b1; + end else begin + res_117_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_117_V_we0 = 1'b1; + end else begin + res_117_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd0; + end else begin + res_118_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_118_V_ce0 = 1'b1; + end else begin + res_118_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_118_V_we0 = 1'b1; + end else begin + res_118_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd0; + end else begin + res_119_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_119_V_ce0 = 1'b1; + end else begin + res_119_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_119_V_we0 = 1'b1; + end else begin + res_119_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd0; + end else begin + res_11_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_11_V_ce0 = 1'b1; + end else begin + res_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_11_V_we0 = 1'b1; + end else begin + res_11_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd0; + end else begin + res_120_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_120_V_ce0 = 1'b1; + end else begin + res_120_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_120_V_we0 = 1'b1; + end else begin + res_120_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd0; + end else begin + res_121_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_121_V_ce0 = 1'b1; + end else begin + res_121_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_121_V_we0 = 1'b1; + end else begin + res_121_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd0; + end else begin + res_122_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_122_V_ce0 = 1'b1; + end else begin + res_122_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_122_V_we0 = 1'b1; + end else begin + res_122_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd0; + end else begin + res_123_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_123_V_ce0 = 1'b1; + end else begin + res_123_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_123_V_we0 = 1'b1; + end else begin + res_123_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd0; + end else begin + res_124_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_124_V_ce0 = 1'b1; + end else begin + res_124_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_124_V_we0 = 1'b1; + end else begin + res_124_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd0; + end else begin + res_125_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_125_V_ce0 = 1'b1; + end else begin + res_125_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_125_V_we0 = 1'b1; + end else begin + res_125_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd0; + end else begin + res_126_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_126_V_ce0 = 1'b1; + end else begin + res_126_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_126_V_we0 = 1'b1; + end else begin + res_126_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd0; + end else begin + res_127_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_127_V_ce0 = 1'b1; + end else begin + res_127_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_127_V_we0 = 1'b1; + end else begin + res_127_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd0; + end else begin + res_12_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_12_V_ce0 = 1'b1; + end else begin + res_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_12_V_we0 = 1'b1; + end else begin + res_12_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd0; + end else begin + res_13_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_13_V_ce0 = 1'b1; + end else begin + res_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_13_V_we0 = 1'b1; + end else begin + res_13_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd0; + end else begin + res_14_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_14_V_ce0 = 1'b1; + end else begin + res_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_14_V_we0 = 1'b1; + end else begin + res_14_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd0; + end else begin + res_15_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_15_V_ce0 = 1'b1; + end else begin + res_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_15_V_we0 = 1'b1; + end else begin + res_15_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd0; + end else begin + res_16_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_16_V_ce0 = 1'b1; + end else begin + res_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_16_V_we0 = 1'b1; + end else begin + res_16_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd0; + end else begin + res_17_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_17_V_ce0 = 1'b1; + end else begin + res_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_17_V_we0 = 1'b1; + end else begin + res_17_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd0; + end else begin + res_18_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_18_V_ce0 = 1'b1; + end else begin + res_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_18_V_we0 = 1'b1; + end else begin + res_18_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd0; + end else begin + res_19_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_19_V_ce0 = 1'b1; + end else begin + res_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_19_V_we0 = 1'b1; + end else begin + res_19_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd0; + end else begin + res_1_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_1_V_ce0 = 1'b1; + end else begin + res_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_1_V_we0 = 1'b1; + end else begin + res_1_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd0; + end else begin + res_20_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_20_V_ce0 = 1'b1; + end else begin + res_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_20_V_we0 = 1'b1; + end else begin + res_20_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd0; + end else begin + res_21_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_21_V_ce0 = 1'b1; + end else begin + res_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_21_V_we0 = 1'b1; + end else begin + res_21_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd0; + end else begin + res_22_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_22_V_ce0 = 1'b1; + end else begin + res_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_22_V_we0 = 1'b1; + end else begin + res_22_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd0; + end else begin + res_23_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_23_V_ce0 = 1'b1; + end else begin + res_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_23_V_we0 = 1'b1; + end else begin + res_23_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd0; + end else begin + res_24_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_24_V_ce0 = 1'b1; + end else begin + res_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_24_V_we0 = 1'b1; + end else begin + res_24_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd0; + end else begin + res_25_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_25_V_ce0 = 1'b1; + end else begin + res_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_25_V_we0 = 1'b1; + end else begin + res_25_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd0; + end else begin + res_26_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_26_V_ce0 = 1'b1; + end else begin + res_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_26_V_we0 = 1'b1; + end else begin + res_26_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd0; + end else begin + res_27_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_27_V_ce0 = 1'b1; + end else begin + res_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_27_V_we0 = 1'b1; + end else begin + res_27_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd0; + end else begin + res_28_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_28_V_ce0 = 1'b1; + end else begin + res_28_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_28_V_we0 = 1'b1; + end else begin + res_28_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd0; + end else begin + res_29_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_29_V_ce0 = 1'b1; + end else begin + res_29_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_29_V_we0 = 1'b1; + end else begin + res_29_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd0; + end else begin + res_2_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_2_V_ce0 = 1'b1; + end else begin + res_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_2_V_we0 = 1'b1; + end else begin + res_2_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd0; + end else begin + res_30_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_30_V_ce0 = 1'b1; + end else begin + res_30_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_30_V_we0 = 1'b1; + end else begin + res_30_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd0; + end else begin + res_31_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_31_V_ce0 = 1'b1; + end else begin + res_31_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_31_V_we0 = 1'b1; + end else begin + res_31_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd0; + end else begin + res_32_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_32_V_ce0 = 1'b1; + end else begin + res_32_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_32_V_we0 = 1'b1; + end else begin + res_32_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd0; + end else begin + res_33_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_33_V_ce0 = 1'b1; + end else begin + res_33_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_33_V_we0 = 1'b1; + end else begin + res_33_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd0; + end else begin + res_34_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_34_V_ce0 = 1'b1; + end else begin + res_34_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_34_V_we0 = 1'b1; + end else begin + res_34_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd0; + end else begin + res_35_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_35_V_ce0 = 1'b1; + end else begin + res_35_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_35_V_we0 = 1'b1; + end else begin + res_35_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd0; + end else begin + res_36_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_36_V_ce0 = 1'b1; + end else begin + res_36_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_36_V_we0 = 1'b1; + end else begin + res_36_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd0; + end else begin + res_37_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_37_V_ce0 = 1'b1; + end else begin + res_37_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_37_V_we0 = 1'b1; + end else begin + res_37_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd0; + end else begin + res_38_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_38_V_ce0 = 1'b1; + end else begin + res_38_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_38_V_we0 = 1'b1; + end else begin + res_38_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd0; + end else begin + res_39_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_39_V_ce0 = 1'b1; + end else begin + res_39_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_39_V_we0 = 1'b1; + end else begin + res_39_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd0; + end else begin + res_3_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_3_V_ce0 = 1'b1; + end else begin + res_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_3_V_we0 = 1'b1; + end else begin + res_3_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd0; + end else begin + res_40_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_40_V_ce0 = 1'b1; + end else begin + res_40_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_40_V_we0 = 1'b1; + end else begin + res_40_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd0; + end else begin + res_41_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_41_V_ce0 = 1'b1; + end else begin + res_41_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_41_V_we0 = 1'b1; + end else begin + res_41_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd0; + end else begin + res_42_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_42_V_ce0 = 1'b1; + end else begin + res_42_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_42_V_we0 = 1'b1; + end else begin + res_42_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd0; + end else begin + res_43_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_43_V_ce0 = 1'b1; + end else begin + res_43_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_43_V_we0 = 1'b1; + end else begin + res_43_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd0; + end else begin + res_44_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_44_V_ce0 = 1'b1; + end else begin + res_44_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_44_V_we0 = 1'b1; + end else begin + res_44_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd0; + end else begin + res_45_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_45_V_ce0 = 1'b1; + end else begin + res_45_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_45_V_we0 = 1'b1; + end else begin + res_45_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd0; + end else begin + res_46_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_46_V_ce0 = 1'b1; + end else begin + res_46_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_46_V_we0 = 1'b1; + end else begin + res_46_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd0; + end else begin + res_47_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_47_V_ce0 = 1'b1; + end else begin + res_47_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_47_V_we0 = 1'b1; + end else begin + res_47_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd0; + end else begin + res_48_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_48_V_ce0 = 1'b1; + end else begin + res_48_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_48_V_we0 = 1'b1; + end else begin + res_48_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd0; + end else begin + res_49_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_49_V_ce0 = 1'b1; + end else begin + res_49_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_49_V_we0 = 1'b1; + end else begin + res_49_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd0; + end else begin + res_4_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_4_V_ce0 = 1'b1; + end else begin + res_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_4_V_we0 = 1'b1; + end else begin + res_4_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd0; + end else begin + res_50_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_50_V_ce0 = 1'b1; + end else begin + res_50_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_50_V_we0 = 1'b1; + end else begin + res_50_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd0; + end else begin + res_51_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_51_V_ce0 = 1'b1; + end else begin + res_51_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_51_V_we0 = 1'b1; + end else begin + res_51_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd0; + end else begin + res_52_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_52_V_ce0 = 1'b1; + end else begin + res_52_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_52_V_we0 = 1'b1; + end else begin + res_52_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd0; + end else begin + res_53_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_53_V_ce0 = 1'b1; + end else begin + res_53_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_53_V_we0 = 1'b1; + end else begin + res_53_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd0; + end else begin + res_54_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_54_V_ce0 = 1'b1; + end else begin + res_54_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_54_V_we0 = 1'b1; + end else begin + res_54_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd0; + end else begin + res_55_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_55_V_ce0 = 1'b1; + end else begin + res_55_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_55_V_we0 = 1'b1; + end else begin + res_55_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd0; + end else begin + res_56_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_56_V_ce0 = 1'b1; + end else begin + res_56_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_56_V_we0 = 1'b1; + end else begin + res_56_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd0; + end else begin + res_57_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_57_V_ce0 = 1'b1; + end else begin + res_57_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_57_V_we0 = 1'b1; + end else begin + res_57_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd0; + end else begin + res_58_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_58_V_ce0 = 1'b1; + end else begin + res_58_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_58_V_we0 = 1'b1; + end else begin + res_58_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd0; + end else begin + res_59_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_59_V_ce0 = 1'b1; + end else begin + res_59_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_59_V_we0 = 1'b1; + end else begin + res_59_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd0; + end else begin + res_5_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_5_V_ce0 = 1'b1; + end else begin + res_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_5_V_we0 = 1'b1; + end else begin + res_5_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd0; + end else begin + res_60_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_60_V_ce0 = 1'b1; + end else begin + res_60_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_60_V_we0 = 1'b1; + end else begin + res_60_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd0; + end else begin + res_61_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_61_V_ce0 = 1'b1; + end else begin + res_61_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_61_V_we0 = 1'b1; + end else begin + res_61_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd0; + end else begin + res_62_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_62_V_ce0 = 1'b1; + end else begin + res_62_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_62_V_we0 = 1'b1; + end else begin + res_62_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd0; + end else begin + res_63_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_63_V_ce0 = 1'b1; + end else begin + res_63_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_63_V_we0 = 1'b1; + end else begin + res_63_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd0; + end else begin + res_64_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_64_V_ce0 = 1'b1; + end else begin + res_64_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_64_V_we0 = 1'b1; + end else begin + res_64_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd0; + end else begin + res_65_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_65_V_ce0 = 1'b1; + end else begin + res_65_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_65_V_we0 = 1'b1; + end else begin + res_65_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd0; + end else begin + res_66_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_66_V_ce0 = 1'b1; + end else begin + res_66_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_66_V_we0 = 1'b1; + end else begin + res_66_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd0; + end else begin + res_67_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_67_V_ce0 = 1'b1; + end else begin + res_67_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_67_V_we0 = 1'b1; + end else begin + res_67_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd0; + end else begin + res_68_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_68_V_ce0 = 1'b1; + end else begin + res_68_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_68_V_we0 = 1'b1; + end else begin + res_68_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd0; + end else begin + res_69_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_69_V_ce0 = 1'b1; + end else begin + res_69_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_69_V_we0 = 1'b1; + end else begin + res_69_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd0; + end else begin + res_6_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_6_V_ce0 = 1'b1; + end else begin + res_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_6_V_we0 = 1'b1; + end else begin + res_6_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd0; + end else begin + res_70_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_70_V_ce0 = 1'b1; + end else begin + res_70_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_70_V_we0 = 1'b1; + end else begin + res_70_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd0; + end else begin + res_71_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_71_V_ce0 = 1'b1; + end else begin + res_71_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_71_V_we0 = 1'b1; + end else begin + res_71_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd0; + end else begin + res_72_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_72_V_ce0 = 1'b1; + end else begin + res_72_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_72_V_we0 = 1'b1; + end else begin + res_72_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd0; + end else begin + res_73_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_73_V_ce0 = 1'b1; + end else begin + res_73_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_73_V_we0 = 1'b1; + end else begin + res_73_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd0; + end else begin + res_74_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_74_V_ce0 = 1'b1; + end else begin + res_74_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_74_V_we0 = 1'b1; + end else begin + res_74_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd0; + end else begin + res_75_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_75_V_ce0 = 1'b1; + end else begin + res_75_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_75_V_we0 = 1'b1; + end else begin + res_75_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd0; + end else begin + res_76_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_76_V_ce0 = 1'b1; + end else begin + res_76_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_76_V_we0 = 1'b1; + end else begin + res_76_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd0; + end else begin + res_77_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_77_V_ce0 = 1'b1; + end else begin + res_77_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_77_V_we0 = 1'b1; + end else begin + res_77_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd0; + end else begin + res_78_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_78_V_ce0 = 1'b1; + end else begin + res_78_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_78_V_we0 = 1'b1; + end else begin + res_78_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd0; + end else begin + res_79_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_79_V_ce0 = 1'b1; + end else begin + res_79_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_79_V_we0 = 1'b1; + end else begin + res_79_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd0; + end else begin + res_7_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_7_V_ce0 = 1'b1; + end else begin + res_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_7_V_we0 = 1'b1; + end else begin + res_7_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd0; + end else begin + res_80_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_80_V_ce0 = 1'b1; + end else begin + res_80_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_80_V_we0 = 1'b1; + end else begin + res_80_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd0; + end else begin + res_81_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_81_V_ce0 = 1'b1; + end else begin + res_81_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_81_V_we0 = 1'b1; + end else begin + res_81_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd0; + end else begin + res_82_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_82_V_ce0 = 1'b1; + end else begin + res_82_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_82_V_we0 = 1'b1; + end else begin + res_82_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd0; + end else begin + res_83_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_83_V_ce0 = 1'b1; + end else begin + res_83_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_83_V_we0 = 1'b1; + end else begin + res_83_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd0; + end else begin + res_84_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_84_V_ce0 = 1'b1; + end else begin + res_84_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_84_V_we0 = 1'b1; + end else begin + res_84_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd0; + end else begin + res_85_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_85_V_ce0 = 1'b1; + end else begin + res_85_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_85_V_we0 = 1'b1; + end else begin + res_85_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd0; + end else begin + res_86_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_86_V_ce0 = 1'b1; + end else begin + res_86_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_86_V_we0 = 1'b1; + end else begin + res_86_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd0; + end else begin + res_87_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_87_V_ce0 = 1'b1; + end else begin + res_87_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_87_V_we0 = 1'b1; + end else begin + res_87_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd0; + end else begin + res_88_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_88_V_ce0 = 1'b1; + end else begin + res_88_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_88_V_we0 = 1'b1; + end else begin + res_88_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd0; + end else begin + res_89_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_89_V_ce0 = 1'b1; + end else begin + res_89_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_89_V_we0 = 1'b1; + end else begin + res_89_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd0; + end else begin + res_8_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_8_V_ce0 = 1'b1; + end else begin + res_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_8_V_we0 = 1'b1; + end else begin + res_8_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd0; + end else begin + res_90_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_90_V_ce0 = 1'b1; + end else begin + res_90_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_90_V_we0 = 1'b1; + end else begin + res_90_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd0; + end else begin + res_91_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_91_V_ce0 = 1'b1; + end else begin + res_91_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_91_V_we0 = 1'b1; + end else begin + res_91_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd0; + end else begin + res_92_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_92_V_ce0 = 1'b1; + end else begin + res_92_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_92_V_we0 = 1'b1; + end else begin + res_92_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd0; + end else begin + res_93_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_93_V_ce0 = 1'b1; + end else begin + res_93_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_93_V_we0 = 1'b1; + end else begin + res_93_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd0; + end else begin + res_94_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_94_V_ce0 = 1'b1; + end else begin + res_94_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_94_V_we0 = 1'b1; + end else begin + res_94_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd0; + end else begin + res_95_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_95_V_ce0 = 1'b1; + end else begin + res_95_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_95_V_we0 = 1'b1; + end else begin + res_95_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd0; + end else begin + res_96_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_96_V_ce0 = 1'b1; + end else begin + res_96_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_96_V_we0 = 1'b1; + end else begin + res_96_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd0; + end else begin + res_97_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_97_V_ce0 = 1'b1; + end else begin + res_97_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_97_V_we0 = 1'b1; + end else begin + res_97_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd0; + end else begin + res_98_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_98_V_ce0 = 1'b1; + end else begin + res_98_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_98_V_we0 = 1'b1; + end else begin + res_98_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd0; + end else begin + res_99_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_99_V_ce0 = 1'b1; + end else begin + res_99_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_99_V_we0 = 1'b1; + end else begin + res_99_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state5045 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state5044 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state5043 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state5042 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state5041 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state5040 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state5039 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state5038 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state5037 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state5036 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state5035 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state5034 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state5033 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state5032 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state5031 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state5030 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state5029 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state5028 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state5027 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd0; + end else begin + res_9_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_9_V_ce0 = 1'b1; + end else begin + res_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state5045 == ap_CS_fsm) | (ap_ST_fsm_state5044 == ap_CS_fsm) | (ap_ST_fsm_state5043 == ap_CS_fsm) | (ap_ST_fsm_state5042 == ap_CS_fsm) | (ap_ST_fsm_state5041 == ap_CS_fsm) | (ap_ST_fsm_state5040 == ap_CS_fsm) | (ap_ST_fsm_state5039 == ap_CS_fsm) | (ap_ST_fsm_state5038 == ap_CS_fsm) | (ap_ST_fsm_state5037 == ap_CS_fsm) | (ap_ST_fsm_state5036 == ap_CS_fsm) | (ap_ST_fsm_state5035 == ap_CS_fsm) | (ap_ST_fsm_state5034 == ap_CS_fsm) | (ap_ST_fsm_state5033 == ap_CS_fsm) | (ap_ST_fsm_state5032 == ap_CS_fsm) | (ap_ST_fsm_state5031 == ap_CS_fsm) | (ap_ST_fsm_state5030 == ap_CS_fsm) | (ap_ST_fsm_state5029 == ap_CS_fsm) | (ap_ST_fsm_state5028 == ap_CS_fsm) | (ap_ST_fsm_state5027 == ap_CS_fsm))) begin + res_9_V_we0 = 1'b1; + end else begin + res_9_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2353 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_31_reg_145571; + end else if ((ap_ST_fsm_state2280 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_27_reg_145166; + end else if ((ap_ST_fsm_state2204 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_24_reg_144696; + end else if ((ap_ST_fsm_state2130 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_15_reg_144291; + end else if ((ap_ST_fsm_state2053 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_23_reg_143829; + end else if ((ap_ST_fsm_state1978 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_14_reg_143431; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_9_reg_142937; + end else if ((ap_ST_fsm_state1827 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_3_reg_142527; + end else if ((ap_ST_fsm_state1749 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_29_reg_142008; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_25_reg_141603; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_20_reg_141143; + end else if ((ap_ST_fsm_state1526 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_12_reg_140738; + end else if ((ap_ST_fsm_state1449 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_18_reg_140276; + end else if ((ap_ST_fsm_state1374 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_10_reg_139878; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_5_reg_139394; + end else if ((ap_ST_fsm_state1223 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_1_reg_138984; + end else if ((ap_ST_fsm_state1143 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_30_reg_138416; + end else if ((ap_ST_fsm_state1070 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_26_reg_138011; + end else if ((ap_ST_fsm_state994 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_21_reg_137541; + end else if ((ap_ST_fsm_state920 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_13_reg_137136; + end else if ((ap_ST_fsm_state843 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_19_reg_136669; + end else if ((ap_ST_fsm_state768 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_11_reg_136271; + end else if ((ap_ST_fsm_state691 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_6_reg_135773; + end else if ((ap_ST_fsm_state617 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_2_reg_135363; + end else if ((ap_ST_fsm_state538 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_28_reg_134845; + end else if ((ap_ST_fsm_state465 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_22_reg_134440; + end else if ((ap_ST_fsm_state389 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_17_reg_133970; + end else if ((ap_ST_fsm_state315 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_8_reg_133565; + end else if ((ap_ST_fsm_state238 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_16_reg_133098; + end else if ((ap_ST_fsm_state163 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_7_reg_132700; + end else if ((ap_ST_fsm_state86 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_4_reg_132202; + end else if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + w5_V_address0 = zext_ln232_reg_131804; + end else begin + w5_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state994 == ap_CS_fsm) | (ap_ST_fsm_state920 == ap_CS_fsm) | (ap_ST_fsm_state86 == ap_CS_fsm) | (ap_ST_fsm_state843 == ap_CS_fsm) | (ap_ST_fsm_state768 == ap_CS_fsm) | (ap_ST_fsm_state691 == ap_CS_fsm) | (ap_ST_fsm_state617 == ap_CS_fsm) | (ap_ST_fsm_state538 == ap_CS_fsm) | (ap_ST_fsm_state465 == ap_CS_fsm) | (ap_ST_fsm_state389 == ap_CS_fsm) | (ap_ST_fsm_state315 == ap_CS_fsm) | (ap_ST_fsm_state238 == ap_CS_fsm) | (ap_ST_fsm_state2353 == ap_CS_fsm) | (ap_ST_fsm_state2280 == ap_CS_fsm) | (ap_ST_fsm_state2204 == ap_CS_fsm) | (ap_ST_fsm_state2130 == ap_CS_fsm) | (ap_ST_fsm_state2053 == ap_CS_fsm) | (ap_ST_fsm_state1978 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1827 == ap_CS_fsm) | (ap_ST_fsm_state1749 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state163 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1526 == ap_CS_fsm) | (ap_ST_fsm_state1449 == ap_CS_fsm) | (ap_ST_fsm_state11 == ap_CS_fsm) | (ap_ST_fsm_state1374 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1223 == ap_CS_fsm) | (ap_ST_fsm_state1143 == ap_CS_fsm) | (ap_ST_fsm_state1070 == ap_CS_fsm))) begin + w5_V_ce0 = 1'b1; + end else begin + w5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if (((ap_start == 1'b1) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln199_fu_101926_p2 == 1'd1) & (ap_ST_fsm_state2 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2425; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + if (((icmp_ln201_fu_101946_p2 == 1'd1) & (ap_ST_fsm_state3 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1215; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + ap_ST_fsm_state4 : begin + if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln203_fu_101988_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state610; + end else begin + ap_NS_fsm = ap_ST_fsm_state5; + end + end + ap_ST_fsm_state5 : begin + if (((ap_ST_fsm_state5 == ap_CS_fsm) & (icmp_ln204_fu_102042_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else begin + ap_NS_fsm = ap_ST_fsm_state6; + end + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + if (((or_ln223_reg_131762 == 1'd0) & (or_ln223_3_fu_102310_p2 == 1'd0) & (ap_ST_fsm_state8 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state9; + end else begin + ap_NS_fsm = ap_ST_fsm_state48; + end + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state18; + end + ap_ST_fsm_state18 : begin + ap_NS_fsm = ap_ST_fsm_state19; + end + ap_ST_fsm_state19 : begin + ap_NS_fsm = ap_ST_fsm_state20; + end + ap_ST_fsm_state20 : begin + ap_NS_fsm = ap_ST_fsm_state21; + end + ap_ST_fsm_state21 : begin + ap_NS_fsm = ap_ST_fsm_state22; + end + ap_ST_fsm_state22 : begin + ap_NS_fsm = ap_ST_fsm_state23; + end + ap_ST_fsm_state23 : begin + ap_NS_fsm = ap_ST_fsm_state24; + end + ap_ST_fsm_state24 : begin + ap_NS_fsm = ap_ST_fsm_state25; + end + ap_ST_fsm_state25 : begin + ap_NS_fsm = ap_ST_fsm_state26; + end + ap_ST_fsm_state26 : begin + ap_NS_fsm = ap_ST_fsm_state27; + end + ap_ST_fsm_state27 : begin + ap_NS_fsm = ap_ST_fsm_state28; + end + ap_ST_fsm_state28 : begin + ap_NS_fsm = ap_ST_fsm_state29; + end + ap_ST_fsm_state29 : begin + ap_NS_fsm = ap_ST_fsm_state30; + end + ap_ST_fsm_state30 : begin + ap_NS_fsm = ap_ST_fsm_state31; + end + ap_ST_fsm_state31 : begin + ap_NS_fsm = ap_ST_fsm_state32; + end + ap_ST_fsm_state32 : begin + ap_NS_fsm = ap_ST_fsm_state33; + end + ap_ST_fsm_state33 : begin + ap_NS_fsm = ap_ST_fsm_state34; + end + ap_ST_fsm_state34 : begin + ap_NS_fsm = ap_ST_fsm_state35; + end + ap_ST_fsm_state35 : begin + ap_NS_fsm = ap_ST_fsm_state36; + end + ap_ST_fsm_state36 : begin + ap_NS_fsm = ap_ST_fsm_state37; + end + ap_ST_fsm_state37 : begin + ap_NS_fsm = ap_ST_fsm_state38; + end + ap_ST_fsm_state38 : begin + ap_NS_fsm = ap_ST_fsm_state39; + end + ap_ST_fsm_state39 : begin + ap_NS_fsm = ap_ST_fsm_state40; + end + ap_ST_fsm_state40 : begin + ap_NS_fsm = ap_ST_fsm_state41; + end + ap_ST_fsm_state41 : begin + ap_NS_fsm = ap_ST_fsm_state42; + end + ap_ST_fsm_state42 : begin + ap_NS_fsm = ap_ST_fsm_state43; + end + ap_ST_fsm_state43 : begin + ap_NS_fsm = ap_ST_fsm_state44; + end + ap_ST_fsm_state44 : begin + ap_NS_fsm = ap_ST_fsm_state45; + end + ap_ST_fsm_state45 : begin + ap_NS_fsm = ap_ST_fsm_state46; + end + ap_ST_fsm_state46 : begin + ap_NS_fsm = ap_ST_fsm_state47; + end + ap_ST_fsm_state47 : begin + if (((icmp_ln206_fu_102733_p2 == 1'd1) & (icmp_ln208_fu_102524_p2 == 1'd1) & (ap_ST_fsm_state47 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state311; + end else if (((icmp_ln208_fu_102524_p2 == 1'd1) & (ap_ST_fsm_state47 == ap_CS_fsm) & (icmp_ln206_fu_102733_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state159; + end else if (((or_ln223_reg_131762 == 1'd0) & (ap_ST_fsm_state47 == ap_CS_fsm) & (or_ln223_9_fu_102602_p2 == 1'd0) & (icmp_ln208_fu_102524_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state84; + end else begin + ap_NS_fsm = ap_ST_fsm_state123; + end + end + ap_ST_fsm_state48 : begin + ap_NS_fsm = ap_ST_fsm_state49; + end + ap_ST_fsm_state49 : begin + ap_NS_fsm = ap_ST_fsm_state50; + end + ap_ST_fsm_state50 : begin + ap_NS_fsm = ap_ST_fsm_state51; + end + ap_ST_fsm_state51 : begin + ap_NS_fsm = ap_ST_fsm_state52; + end + ap_ST_fsm_state52 : begin + ap_NS_fsm = ap_ST_fsm_state53; + end + ap_ST_fsm_state53 : begin + ap_NS_fsm = ap_ST_fsm_state54; + end + ap_ST_fsm_state54 : begin + ap_NS_fsm = ap_ST_fsm_state55; + end + ap_ST_fsm_state55 : begin + ap_NS_fsm = ap_ST_fsm_state56; + end + ap_ST_fsm_state56 : begin + ap_NS_fsm = ap_ST_fsm_state57; + end + ap_ST_fsm_state57 : begin + ap_NS_fsm = ap_ST_fsm_state58; + end + ap_ST_fsm_state58 : begin + ap_NS_fsm = ap_ST_fsm_state59; + end + ap_ST_fsm_state59 : begin + ap_NS_fsm = ap_ST_fsm_state60; + end + ap_ST_fsm_state60 : begin + ap_NS_fsm = ap_ST_fsm_state61; + end + ap_ST_fsm_state61 : begin + ap_NS_fsm = ap_ST_fsm_state62; + end + ap_ST_fsm_state62 : begin + ap_NS_fsm = ap_ST_fsm_state63; + end + ap_ST_fsm_state63 : begin + ap_NS_fsm = ap_ST_fsm_state64; + end + ap_ST_fsm_state64 : begin + ap_NS_fsm = ap_ST_fsm_state65; + end + ap_ST_fsm_state65 : begin + ap_NS_fsm = ap_ST_fsm_state66; + end + ap_ST_fsm_state66 : begin + ap_NS_fsm = ap_ST_fsm_state67; + end + ap_ST_fsm_state67 : begin + ap_NS_fsm = ap_ST_fsm_state68; + end + ap_ST_fsm_state68 : begin + ap_NS_fsm = ap_ST_fsm_state69; + end + ap_ST_fsm_state69 : begin + ap_NS_fsm = ap_ST_fsm_state70; + end + ap_ST_fsm_state70 : begin + ap_NS_fsm = ap_ST_fsm_state71; + end + ap_ST_fsm_state71 : begin + ap_NS_fsm = ap_ST_fsm_state72; + end + ap_ST_fsm_state72 : begin + ap_NS_fsm = ap_ST_fsm_state73; + end + ap_ST_fsm_state73 : begin + ap_NS_fsm = ap_ST_fsm_state74; + end + ap_ST_fsm_state74 : begin + ap_NS_fsm = ap_ST_fsm_state75; + end + ap_ST_fsm_state75 : begin + ap_NS_fsm = ap_ST_fsm_state76; + end + ap_ST_fsm_state76 : begin + ap_NS_fsm = ap_ST_fsm_state77; + end + ap_ST_fsm_state77 : begin + ap_NS_fsm = ap_ST_fsm_state78; + end + ap_ST_fsm_state78 : begin + ap_NS_fsm = ap_ST_fsm_state79; + end + ap_ST_fsm_state79 : begin + ap_NS_fsm = ap_ST_fsm_state80; + end + ap_ST_fsm_state80 : begin + ap_NS_fsm = ap_ST_fsm_state81; + end + ap_ST_fsm_state81 : begin + ap_NS_fsm = ap_ST_fsm_state82; + end + ap_ST_fsm_state82 : begin + ap_NS_fsm = ap_ST_fsm_state83; + end + ap_ST_fsm_state83 : begin + ap_NS_fsm = ap_ST_fsm_state47; + end + ap_ST_fsm_state84 : begin + ap_NS_fsm = ap_ST_fsm_state85; + end + ap_ST_fsm_state85 : begin + ap_NS_fsm = ap_ST_fsm_state86; + end + ap_ST_fsm_state86 : begin + ap_NS_fsm = ap_ST_fsm_state87; + end + ap_ST_fsm_state87 : begin + ap_NS_fsm = ap_ST_fsm_state88; + end + ap_ST_fsm_state88 : begin + ap_NS_fsm = ap_ST_fsm_state89; + end + ap_ST_fsm_state89 : begin + ap_NS_fsm = ap_ST_fsm_state90; + end + ap_ST_fsm_state90 : begin + ap_NS_fsm = ap_ST_fsm_state91; + end + ap_ST_fsm_state91 : begin + ap_NS_fsm = ap_ST_fsm_state92; + end + ap_ST_fsm_state92 : begin + ap_NS_fsm = ap_ST_fsm_state93; + end + ap_ST_fsm_state93 : begin + ap_NS_fsm = ap_ST_fsm_state94; + end + ap_ST_fsm_state94 : begin + ap_NS_fsm = ap_ST_fsm_state95; + end + ap_ST_fsm_state95 : begin + ap_NS_fsm = ap_ST_fsm_state96; + end + ap_ST_fsm_state96 : begin + ap_NS_fsm = ap_ST_fsm_state97; + end + ap_ST_fsm_state97 : begin + ap_NS_fsm = ap_ST_fsm_state98; + end + ap_ST_fsm_state98 : begin + ap_NS_fsm = ap_ST_fsm_state99; + end + ap_ST_fsm_state99 : begin + ap_NS_fsm = ap_ST_fsm_state100; + end + ap_ST_fsm_state100 : begin + ap_NS_fsm = ap_ST_fsm_state101; + end + ap_ST_fsm_state101 : begin + ap_NS_fsm = ap_ST_fsm_state102; + end + ap_ST_fsm_state102 : begin + ap_NS_fsm = ap_ST_fsm_state103; + end + ap_ST_fsm_state103 : begin + ap_NS_fsm = ap_ST_fsm_state104; + end + ap_ST_fsm_state104 : begin + ap_NS_fsm = ap_ST_fsm_state105; + end + ap_ST_fsm_state105 : begin + ap_NS_fsm = ap_ST_fsm_state106; + end + ap_ST_fsm_state106 : begin + ap_NS_fsm = ap_ST_fsm_state107; + end + ap_ST_fsm_state107 : begin + ap_NS_fsm = ap_ST_fsm_state108; + end + ap_ST_fsm_state108 : begin + ap_NS_fsm = ap_ST_fsm_state109; + end + ap_ST_fsm_state109 : begin + ap_NS_fsm = ap_ST_fsm_state110; + end + ap_ST_fsm_state110 : begin + ap_NS_fsm = ap_ST_fsm_state111; + end + ap_ST_fsm_state111 : begin + ap_NS_fsm = ap_ST_fsm_state112; + end + ap_ST_fsm_state112 : begin + ap_NS_fsm = ap_ST_fsm_state113; + end + ap_ST_fsm_state113 : begin + ap_NS_fsm = ap_ST_fsm_state114; + end + ap_ST_fsm_state114 : begin + ap_NS_fsm = ap_ST_fsm_state115; + end + ap_ST_fsm_state115 : begin + ap_NS_fsm = ap_ST_fsm_state116; + end + ap_ST_fsm_state116 : begin + ap_NS_fsm = ap_ST_fsm_state117; + end + ap_ST_fsm_state117 : begin + ap_NS_fsm = ap_ST_fsm_state118; + end + ap_ST_fsm_state118 : begin + ap_NS_fsm = ap_ST_fsm_state119; + end + ap_ST_fsm_state119 : begin + ap_NS_fsm = ap_ST_fsm_state120; + end + ap_ST_fsm_state120 : begin + ap_NS_fsm = ap_ST_fsm_state121; + end + ap_ST_fsm_state121 : begin + ap_NS_fsm = ap_ST_fsm_state122; + end + ap_ST_fsm_state122 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state123 : begin + ap_NS_fsm = ap_ST_fsm_state124; + end + ap_ST_fsm_state124 : begin + ap_NS_fsm = ap_ST_fsm_state125; + end + ap_ST_fsm_state125 : begin + ap_NS_fsm = ap_ST_fsm_state126; + end + ap_ST_fsm_state126 : begin + ap_NS_fsm = ap_ST_fsm_state127; + end + ap_ST_fsm_state127 : begin + ap_NS_fsm = ap_ST_fsm_state128; + end + ap_ST_fsm_state128 : begin + ap_NS_fsm = ap_ST_fsm_state129; + end + ap_ST_fsm_state129 : begin + ap_NS_fsm = ap_ST_fsm_state130; + end + ap_ST_fsm_state130 : begin + ap_NS_fsm = ap_ST_fsm_state131; + end + ap_ST_fsm_state131 : begin + ap_NS_fsm = ap_ST_fsm_state132; + end + ap_ST_fsm_state132 : begin + ap_NS_fsm = ap_ST_fsm_state133; + end + ap_ST_fsm_state133 : begin + ap_NS_fsm = ap_ST_fsm_state134; + end + ap_ST_fsm_state134 : begin + ap_NS_fsm = ap_ST_fsm_state135; + end + ap_ST_fsm_state135 : begin + ap_NS_fsm = ap_ST_fsm_state136; + end + ap_ST_fsm_state136 : begin + ap_NS_fsm = ap_ST_fsm_state137; + end + ap_ST_fsm_state137 : begin + ap_NS_fsm = ap_ST_fsm_state138; + end + ap_ST_fsm_state138 : begin + ap_NS_fsm = ap_ST_fsm_state139; + end + ap_ST_fsm_state139 : begin + ap_NS_fsm = ap_ST_fsm_state140; + end + ap_ST_fsm_state140 : begin + ap_NS_fsm = ap_ST_fsm_state141; + end + ap_ST_fsm_state141 : begin + ap_NS_fsm = ap_ST_fsm_state142; + end + ap_ST_fsm_state142 : begin + ap_NS_fsm = ap_ST_fsm_state143; + end + ap_ST_fsm_state143 : begin + ap_NS_fsm = ap_ST_fsm_state144; + end + ap_ST_fsm_state144 : begin + ap_NS_fsm = ap_ST_fsm_state145; + end + ap_ST_fsm_state145 : begin + ap_NS_fsm = ap_ST_fsm_state146; + end + ap_ST_fsm_state146 : begin + ap_NS_fsm = ap_ST_fsm_state147; + end + ap_ST_fsm_state147 : begin + ap_NS_fsm = ap_ST_fsm_state148; + end + ap_ST_fsm_state148 : begin + ap_NS_fsm = ap_ST_fsm_state149; + end + ap_ST_fsm_state149 : begin + ap_NS_fsm = ap_ST_fsm_state150; + end + ap_ST_fsm_state150 : begin + ap_NS_fsm = ap_ST_fsm_state151; + end + ap_ST_fsm_state151 : begin + ap_NS_fsm = ap_ST_fsm_state152; + end + ap_ST_fsm_state152 : begin + ap_NS_fsm = ap_ST_fsm_state153; + end + ap_ST_fsm_state153 : begin + ap_NS_fsm = ap_ST_fsm_state154; + end + ap_ST_fsm_state154 : begin + ap_NS_fsm = ap_ST_fsm_state155; + end + ap_ST_fsm_state155 : begin + ap_NS_fsm = ap_ST_fsm_state156; + end + ap_ST_fsm_state156 : begin + ap_NS_fsm = ap_ST_fsm_state157; + end + ap_ST_fsm_state157 : begin + ap_NS_fsm = ap_ST_fsm_state158; + end + ap_ST_fsm_state158 : begin + ap_NS_fsm = ap_ST_fsm_state122; + end + ap_ST_fsm_state159 : begin + ap_NS_fsm = ap_ST_fsm_state160; + end + ap_ST_fsm_state160 : begin + if (((ap_ST_fsm_state160 == ap_CS_fsm) & (or_ln223_8_reg_132680 == 1'd0) & (or_ln223_15_fu_103192_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state161; + end else begin + ap_NS_fsm = ap_ST_fsm_state200; + end + end + ap_ST_fsm_state161 : begin + ap_NS_fsm = ap_ST_fsm_state162; + end + ap_ST_fsm_state162 : begin + ap_NS_fsm = ap_ST_fsm_state163; + end + ap_ST_fsm_state163 : begin + ap_NS_fsm = ap_ST_fsm_state164; + end + ap_ST_fsm_state164 : begin + ap_NS_fsm = ap_ST_fsm_state165; + end + ap_ST_fsm_state165 : begin + ap_NS_fsm = ap_ST_fsm_state166; + end + ap_ST_fsm_state166 : begin + ap_NS_fsm = ap_ST_fsm_state167; + end + ap_ST_fsm_state167 : begin + ap_NS_fsm = ap_ST_fsm_state168; + end + ap_ST_fsm_state168 : begin + ap_NS_fsm = ap_ST_fsm_state169; + end + ap_ST_fsm_state169 : begin + ap_NS_fsm = ap_ST_fsm_state170; + end + ap_ST_fsm_state170 : begin + ap_NS_fsm = ap_ST_fsm_state171; + end + ap_ST_fsm_state171 : begin + ap_NS_fsm = ap_ST_fsm_state172; + end + ap_ST_fsm_state172 : begin + ap_NS_fsm = ap_ST_fsm_state173; + end + ap_ST_fsm_state173 : begin + ap_NS_fsm = ap_ST_fsm_state174; + end + ap_ST_fsm_state174 : begin + ap_NS_fsm = ap_ST_fsm_state175; + end + ap_ST_fsm_state175 : begin + ap_NS_fsm = ap_ST_fsm_state176; + end + ap_ST_fsm_state176 : begin + ap_NS_fsm = ap_ST_fsm_state177; + end + ap_ST_fsm_state177 : begin + ap_NS_fsm = ap_ST_fsm_state178; + end + ap_ST_fsm_state178 : begin + ap_NS_fsm = ap_ST_fsm_state179; + end + ap_ST_fsm_state179 : begin + ap_NS_fsm = ap_ST_fsm_state180; + end + ap_ST_fsm_state180 : begin + ap_NS_fsm = ap_ST_fsm_state181; + end + ap_ST_fsm_state181 : begin + ap_NS_fsm = ap_ST_fsm_state182; + end + ap_ST_fsm_state182 : begin + ap_NS_fsm = ap_ST_fsm_state183; + end + ap_ST_fsm_state183 : begin + ap_NS_fsm = ap_ST_fsm_state184; + end + ap_ST_fsm_state184 : begin + ap_NS_fsm = ap_ST_fsm_state185; + end + ap_ST_fsm_state185 : begin + ap_NS_fsm = ap_ST_fsm_state186; + end + ap_ST_fsm_state186 : begin + ap_NS_fsm = ap_ST_fsm_state187; + end + ap_ST_fsm_state187 : begin + ap_NS_fsm = ap_ST_fsm_state188; + end + ap_ST_fsm_state188 : begin + ap_NS_fsm = ap_ST_fsm_state189; + end + ap_ST_fsm_state189 : begin + ap_NS_fsm = ap_ST_fsm_state190; + end + ap_ST_fsm_state190 : begin + ap_NS_fsm = ap_ST_fsm_state191; + end + ap_ST_fsm_state191 : begin + ap_NS_fsm = ap_ST_fsm_state192; + end + ap_ST_fsm_state192 : begin + ap_NS_fsm = ap_ST_fsm_state193; + end + ap_ST_fsm_state193 : begin + ap_NS_fsm = ap_ST_fsm_state194; + end + ap_ST_fsm_state194 : begin + ap_NS_fsm = ap_ST_fsm_state195; + end + ap_ST_fsm_state195 : begin + ap_NS_fsm = ap_ST_fsm_state196; + end + ap_ST_fsm_state196 : begin + ap_NS_fsm = ap_ST_fsm_state197; + end + ap_ST_fsm_state197 : begin + ap_NS_fsm = ap_ST_fsm_state198; + end + ap_ST_fsm_state198 : begin + ap_NS_fsm = ap_ST_fsm_state199; + end + ap_ST_fsm_state199 : begin + if (((icmp_ln208_4_fu_103406_p2 == 1'd1) & (ap_ST_fsm_state199 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state6; + end else if (((ap_ST_fsm_state199 == ap_CS_fsm) & (or_ln223_28_fu_103484_p2 == 1'd0) & (icmp_ln208_4_fu_103406_p2 == 1'd0) & (or_ln223_8_reg_132680 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state236; + end else begin + ap_NS_fsm = ap_ST_fsm_state275; + end + end + ap_ST_fsm_state200 : begin + ap_NS_fsm = ap_ST_fsm_state201; + end + ap_ST_fsm_state201 : begin + ap_NS_fsm = ap_ST_fsm_state202; + end + ap_ST_fsm_state202 : begin + ap_NS_fsm = ap_ST_fsm_state203; + end + ap_ST_fsm_state203 : begin + ap_NS_fsm = ap_ST_fsm_state204; + end + ap_ST_fsm_state204 : begin + ap_NS_fsm = ap_ST_fsm_state205; + end + ap_ST_fsm_state205 : begin + ap_NS_fsm = ap_ST_fsm_state206; + end + ap_ST_fsm_state206 : begin + ap_NS_fsm = ap_ST_fsm_state207; + end + ap_ST_fsm_state207 : begin + ap_NS_fsm = ap_ST_fsm_state208; + end + ap_ST_fsm_state208 : begin + ap_NS_fsm = ap_ST_fsm_state209; + end + ap_ST_fsm_state209 : begin + ap_NS_fsm = ap_ST_fsm_state210; + end + ap_ST_fsm_state210 : begin + ap_NS_fsm = ap_ST_fsm_state211; + end + ap_ST_fsm_state211 : begin + ap_NS_fsm = ap_ST_fsm_state212; + end + ap_ST_fsm_state212 : begin + ap_NS_fsm = ap_ST_fsm_state213; + end + ap_ST_fsm_state213 : begin + ap_NS_fsm = ap_ST_fsm_state214; + end + ap_ST_fsm_state214 : begin + ap_NS_fsm = ap_ST_fsm_state215; + end + ap_ST_fsm_state215 : begin + ap_NS_fsm = ap_ST_fsm_state216; + end + ap_ST_fsm_state216 : begin + ap_NS_fsm = ap_ST_fsm_state217; + end + ap_ST_fsm_state217 : begin + ap_NS_fsm = ap_ST_fsm_state218; + end + ap_ST_fsm_state218 : begin + ap_NS_fsm = ap_ST_fsm_state219; + end + ap_ST_fsm_state219 : begin + ap_NS_fsm = ap_ST_fsm_state220; + end + ap_ST_fsm_state220 : begin + ap_NS_fsm = ap_ST_fsm_state221; + end + ap_ST_fsm_state221 : begin + ap_NS_fsm = ap_ST_fsm_state222; + end + ap_ST_fsm_state222 : begin + ap_NS_fsm = ap_ST_fsm_state223; + end + ap_ST_fsm_state223 : begin + ap_NS_fsm = ap_ST_fsm_state224; + end + ap_ST_fsm_state224 : begin + ap_NS_fsm = ap_ST_fsm_state225; + end + ap_ST_fsm_state225 : begin + ap_NS_fsm = ap_ST_fsm_state226; + end + ap_ST_fsm_state226 : begin + ap_NS_fsm = ap_ST_fsm_state227; + end + ap_ST_fsm_state227 : begin + ap_NS_fsm = ap_ST_fsm_state228; + end + ap_ST_fsm_state228 : begin + ap_NS_fsm = ap_ST_fsm_state229; + end + ap_ST_fsm_state229 : begin + ap_NS_fsm = ap_ST_fsm_state230; + end + ap_ST_fsm_state230 : begin + ap_NS_fsm = ap_ST_fsm_state231; + end + ap_ST_fsm_state231 : begin + ap_NS_fsm = ap_ST_fsm_state232; + end + ap_ST_fsm_state232 : begin + ap_NS_fsm = ap_ST_fsm_state233; + end + ap_ST_fsm_state233 : begin + ap_NS_fsm = ap_ST_fsm_state234; + end + ap_ST_fsm_state234 : begin + ap_NS_fsm = ap_ST_fsm_state235; + end + ap_ST_fsm_state235 : begin + ap_NS_fsm = ap_ST_fsm_state199; + end + ap_ST_fsm_state236 : begin + ap_NS_fsm = ap_ST_fsm_state237; + end + ap_ST_fsm_state237 : begin + ap_NS_fsm = ap_ST_fsm_state238; + end + ap_ST_fsm_state238 : begin + ap_NS_fsm = ap_ST_fsm_state239; + end + ap_ST_fsm_state239 : begin + ap_NS_fsm = ap_ST_fsm_state240; + end + ap_ST_fsm_state240 : begin + ap_NS_fsm = ap_ST_fsm_state241; + end + ap_ST_fsm_state241 : begin + ap_NS_fsm = ap_ST_fsm_state242; + end + ap_ST_fsm_state242 : begin + ap_NS_fsm = ap_ST_fsm_state243; + end + ap_ST_fsm_state243 : begin + ap_NS_fsm = ap_ST_fsm_state244; + end + ap_ST_fsm_state244 : begin + ap_NS_fsm = ap_ST_fsm_state245; + end + ap_ST_fsm_state245 : begin + ap_NS_fsm = ap_ST_fsm_state246; + end + ap_ST_fsm_state246 : begin + ap_NS_fsm = ap_ST_fsm_state247; + end + ap_ST_fsm_state247 : begin + ap_NS_fsm = ap_ST_fsm_state248; + end + ap_ST_fsm_state248 : begin + ap_NS_fsm = ap_ST_fsm_state249; + end + ap_ST_fsm_state249 : begin + ap_NS_fsm = ap_ST_fsm_state250; + end + ap_ST_fsm_state250 : begin + ap_NS_fsm = ap_ST_fsm_state251; + end + ap_ST_fsm_state251 : begin + ap_NS_fsm = ap_ST_fsm_state252; + end + ap_ST_fsm_state252 : begin + ap_NS_fsm = ap_ST_fsm_state253; + end + ap_ST_fsm_state253 : begin + ap_NS_fsm = ap_ST_fsm_state254; + end + ap_ST_fsm_state254 : begin + ap_NS_fsm = ap_ST_fsm_state255; + end + ap_ST_fsm_state255 : begin + ap_NS_fsm = ap_ST_fsm_state256; + end + ap_ST_fsm_state256 : begin + ap_NS_fsm = ap_ST_fsm_state257; + end + ap_ST_fsm_state257 : begin + ap_NS_fsm = ap_ST_fsm_state258; + end + ap_ST_fsm_state258 : begin + ap_NS_fsm = ap_ST_fsm_state259; + end + ap_ST_fsm_state259 : begin + ap_NS_fsm = ap_ST_fsm_state260; + end + ap_ST_fsm_state260 : begin + ap_NS_fsm = ap_ST_fsm_state261; + end + ap_ST_fsm_state261 : begin + ap_NS_fsm = ap_ST_fsm_state262; + end + ap_ST_fsm_state262 : begin + ap_NS_fsm = ap_ST_fsm_state263; + end + ap_ST_fsm_state263 : begin + ap_NS_fsm = ap_ST_fsm_state264; + end + ap_ST_fsm_state264 : begin + ap_NS_fsm = ap_ST_fsm_state265; + end + ap_ST_fsm_state265 : begin + ap_NS_fsm = ap_ST_fsm_state266; + end + ap_ST_fsm_state266 : begin + ap_NS_fsm = ap_ST_fsm_state267; + end + ap_ST_fsm_state267 : begin + ap_NS_fsm = ap_ST_fsm_state268; + end + ap_ST_fsm_state268 : begin + ap_NS_fsm = ap_ST_fsm_state269; + end + ap_ST_fsm_state269 : begin + ap_NS_fsm = ap_ST_fsm_state270; + end + ap_ST_fsm_state270 : begin + ap_NS_fsm = ap_ST_fsm_state271; + end + ap_ST_fsm_state271 : begin + ap_NS_fsm = ap_ST_fsm_state272; + end + ap_ST_fsm_state272 : begin + ap_NS_fsm = ap_ST_fsm_state273; + end + ap_ST_fsm_state273 : begin + ap_NS_fsm = ap_ST_fsm_state274; + end + ap_ST_fsm_state274 : begin + ap_NS_fsm = ap_ST_fsm_state160; + end + ap_ST_fsm_state275 : begin + ap_NS_fsm = ap_ST_fsm_state276; + end + ap_ST_fsm_state276 : begin + ap_NS_fsm = ap_ST_fsm_state277; + end + ap_ST_fsm_state277 : begin + ap_NS_fsm = ap_ST_fsm_state278; + end + ap_ST_fsm_state278 : begin + ap_NS_fsm = ap_ST_fsm_state279; + end + ap_ST_fsm_state279 : begin + ap_NS_fsm = ap_ST_fsm_state280; + end + ap_ST_fsm_state280 : begin + ap_NS_fsm = ap_ST_fsm_state281; + end + ap_ST_fsm_state281 : begin + ap_NS_fsm = ap_ST_fsm_state282; + end + ap_ST_fsm_state282 : begin + ap_NS_fsm = ap_ST_fsm_state283; + end + ap_ST_fsm_state283 : begin + ap_NS_fsm = ap_ST_fsm_state284; + end + ap_ST_fsm_state284 : begin + ap_NS_fsm = ap_ST_fsm_state285; + end + ap_ST_fsm_state285 : begin + ap_NS_fsm = ap_ST_fsm_state286; + end + ap_ST_fsm_state286 : begin + ap_NS_fsm = ap_ST_fsm_state287; + end + ap_ST_fsm_state287 : begin + ap_NS_fsm = ap_ST_fsm_state288; + end + ap_ST_fsm_state288 : begin + ap_NS_fsm = ap_ST_fsm_state289; + end + ap_ST_fsm_state289 : begin + ap_NS_fsm = ap_ST_fsm_state290; + end + ap_ST_fsm_state290 : begin + ap_NS_fsm = ap_ST_fsm_state291; + end + ap_ST_fsm_state291 : begin + ap_NS_fsm = ap_ST_fsm_state292; + end + ap_ST_fsm_state292 : begin + ap_NS_fsm = ap_ST_fsm_state293; + end + ap_ST_fsm_state293 : begin + ap_NS_fsm = ap_ST_fsm_state294; + end + ap_ST_fsm_state294 : begin + ap_NS_fsm = ap_ST_fsm_state295; + end + ap_ST_fsm_state295 : begin + ap_NS_fsm = ap_ST_fsm_state296; + end + ap_ST_fsm_state296 : begin + ap_NS_fsm = ap_ST_fsm_state297; + end + ap_ST_fsm_state297 : begin + ap_NS_fsm = ap_ST_fsm_state298; + end + ap_ST_fsm_state298 : begin + ap_NS_fsm = ap_ST_fsm_state299; + end + ap_ST_fsm_state299 : begin + ap_NS_fsm = ap_ST_fsm_state300; + end + ap_ST_fsm_state300 : begin + ap_NS_fsm = ap_ST_fsm_state301; + end + ap_ST_fsm_state301 : begin + ap_NS_fsm = ap_ST_fsm_state302; + end + ap_ST_fsm_state302 : begin + ap_NS_fsm = ap_ST_fsm_state303; + end + ap_ST_fsm_state303 : begin + ap_NS_fsm = ap_ST_fsm_state304; + end + ap_ST_fsm_state304 : begin + ap_NS_fsm = ap_ST_fsm_state305; + end + ap_ST_fsm_state305 : begin + ap_NS_fsm = ap_ST_fsm_state306; + end + ap_ST_fsm_state306 : begin + ap_NS_fsm = ap_ST_fsm_state307; + end + ap_ST_fsm_state307 : begin + ap_NS_fsm = ap_ST_fsm_state308; + end + ap_ST_fsm_state308 : begin + ap_NS_fsm = ap_ST_fsm_state309; + end + ap_ST_fsm_state309 : begin + ap_NS_fsm = ap_ST_fsm_state310; + end + ap_ST_fsm_state310 : begin + ap_NS_fsm = ap_ST_fsm_state274; + end + ap_ST_fsm_state311 : begin + ap_NS_fsm = ap_ST_fsm_state312; + end + ap_ST_fsm_state312 : begin + ap_NS_fsm = ap_ST_fsm_state313; + end + ap_ST_fsm_state313 : begin + if (((ap_ST_fsm_state313 == ap_CS_fsm) & (or_ln223_18_fu_103998_p2 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state314; + end else begin + ap_NS_fsm = ap_ST_fsm_state351; + end + end + ap_ST_fsm_state314 : begin + ap_NS_fsm = ap_ST_fsm_state315; + end + ap_ST_fsm_state315 : begin + ap_NS_fsm = ap_ST_fsm_state316; + end + ap_ST_fsm_state316 : begin + ap_NS_fsm = ap_ST_fsm_state317; + end + ap_ST_fsm_state317 : begin + ap_NS_fsm = ap_ST_fsm_state318; + end + ap_ST_fsm_state318 : begin + ap_NS_fsm = ap_ST_fsm_state319; + end + ap_ST_fsm_state319 : begin + ap_NS_fsm = ap_ST_fsm_state320; + end + ap_ST_fsm_state320 : begin + ap_NS_fsm = ap_ST_fsm_state321; + end + ap_ST_fsm_state321 : begin + ap_NS_fsm = ap_ST_fsm_state322; + end + ap_ST_fsm_state322 : begin + ap_NS_fsm = ap_ST_fsm_state323; + end + ap_ST_fsm_state323 : begin + ap_NS_fsm = ap_ST_fsm_state324; + end + ap_ST_fsm_state324 : begin + ap_NS_fsm = ap_ST_fsm_state325; + end + ap_ST_fsm_state325 : begin + ap_NS_fsm = ap_ST_fsm_state326; + end + ap_ST_fsm_state326 : begin + ap_NS_fsm = ap_ST_fsm_state327; + end + ap_ST_fsm_state327 : begin + ap_NS_fsm = ap_ST_fsm_state328; + end + ap_ST_fsm_state328 : begin + ap_NS_fsm = ap_ST_fsm_state329; + end + ap_ST_fsm_state329 : begin + ap_NS_fsm = ap_ST_fsm_state330; + end + ap_ST_fsm_state330 : begin + ap_NS_fsm = ap_ST_fsm_state331; + end + ap_ST_fsm_state331 : begin + ap_NS_fsm = ap_ST_fsm_state332; + end + ap_ST_fsm_state332 : begin + ap_NS_fsm = ap_ST_fsm_state333; + end + ap_ST_fsm_state333 : begin + ap_NS_fsm = ap_ST_fsm_state334; + end + ap_ST_fsm_state334 : begin + ap_NS_fsm = ap_ST_fsm_state335; + end + ap_ST_fsm_state335 : begin + ap_NS_fsm = ap_ST_fsm_state336; + end + ap_ST_fsm_state336 : begin + ap_NS_fsm = ap_ST_fsm_state337; + end + ap_ST_fsm_state337 : begin + ap_NS_fsm = ap_ST_fsm_state338; + end + ap_ST_fsm_state338 : begin + ap_NS_fsm = ap_ST_fsm_state339; + end + ap_ST_fsm_state339 : begin + ap_NS_fsm = ap_ST_fsm_state340; + end + ap_ST_fsm_state340 : begin + ap_NS_fsm = ap_ST_fsm_state341; + end + ap_ST_fsm_state341 : begin + ap_NS_fsm = ap_ST_fsm_state342; + end + ap_ST_fsm_state342 : begin + ap_NS_fsm = ap_ST_fsm_state343; + end + ap_ST_fsm_state343 : begin + ap_NS_fsm = ap_ST_fsm_state344; + end + ap_ST_fsm_state344 : begin + ap_NS_fsm = ap_ST_fsm_state345; + end + ap_ST_fsm_state345 : begin + ap_NS_fsm = ap_ST_fsm_state346; + end + ap_ST_fsm_state346 : begin + ap_NS_fsm = ap_ST_fsm_state347; + end + ap_ST_fsm_state347 : begin + ap_NS_fsm = ap_ST_fsm_state348; + end + ap_ST_fsm_state348 : begin + ap_NS_fsm = ap_ST_fsm_state349; + end + ap_ST_fsm_state349 : begin + ap_NS_fsm = ap_ST_fsm_state350; + end + ap_ST_fsm_state350 : begin + if (((icmp_ln206_4_fu_104418_p2 == 1'd1) & (icmp_ln208_5_fu_104210_p2 == 1'd1) & (ap_ST_fsm_state350 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state5; + end else if (((icmp_ln208_5_fu_104210_p2 == 1'd1) & (ap_ST_fsm_state350 == ap_CS_fsm) & (icmp_ln206_4_fu_104418_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state462; + end else if (((ap_ST_fsm_state350 == ap_CS_fsm) & (or_ln223_30_fu_104288_p2 == 1'd0) & (icmp_ln208_5_fu_104210_p2 == 1'd0) & (or_ln223_10_reg_133539 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state387; + end else begin + ap_NS_fsm = ap_ST_fsm_state426; + end + end + ap_ST_fsm_state351 : begin + ap_NS_fsm = ap_ST_fsm_state352; + end + ap_ST_fsm_state352 : begin + ap_NS_fsm = ap_ST_fsm_state353; + end + ap_ST_fsm_state353 : begin + ap_NS_fsm = ap_ST_fsm_state354; + end + ap_ST_fsm_state354 : begin + ap_NS_fsm = ap_ST_fsm_state355; + end + ap_ST_fsm_state355 : begin + ap_NS_fsm = ap_ST_fsm_state356; + end + ap_ST_fsm_state356 : begin + ap_NS_fsm = ap_ST_fsm_state357; + end + ap_ST_fsm_state357 : begin + ap_NS_fsm = ap_ST_fsm_state358; + end + ap_ST_fsm_state358 : begin + ap_NS_fsm = ap_ST_fsm_state359; + end + ap_ST_fsm_state359 : begin + ap_NS_fsm = ap_ST_fsm_state360; + end + ap_ST_fsm_state360 : begin + ap_NS_fsm = ap_ST_fsm_state361; + end + ap_ST_fsm_state361 : begin + ap_NS_fsm = ap_ST_fsm_state362; + end + ap_ST_fsm_state362 : begin + ap_NS_fsm = ap_ST_fsm_state363; + end + ap_ST_fsm_state363 : begin + ap_NS_fsm = ap_ST_fsm_state364; + end + ap_ST_fsm_state364 : begin + ap_NS_fsm = ap_ST_fsm_state365; + end + ap_ST_fsm_state365 : begin + ap_NS_fsm = ap_ST_fsm_state366; + end + ap_ST_fsm_state366 : begin + ap_NS_fsm = ap_ST_fsm_state367; + end + ap_ST_fsm_state367 : begin + ap_NS_fsm = ap_ST_fsm_state368; + end + ap_ST_fsm_state368 : begin + ap_NS_fsm = ap_ST_fsm_state369; + end + ap_ST_fsm_state369 : begin + ap_NS_fsm = ap_ST_fsm_state370; + end + ap_ST_fsm_state370 : begin + ap_NS_fsm = ap_ST_fsm_state371; + end + ap_ST_fsm_state371 : begin + ap_NS_fsm = ap_ST_fsm_state372; + end + ap_ST_fsm_state372 : begin + ap_NS_fsm = ap_ST_fsm_state373; + end + ap_ST_fsm_state373 : begin + ap_NS_fsm = ap_ST_fsm_state374; + end + ap_ST_fsm_state374 : begin + ap_NS_fsm = ap_ST_fsm_state375; + end + ap_ST_fsm_state375 : begin + ap_NS_fsm = ap_ST_fsm_state376; + end + ap_ST_fsm_state376 : begin + ap_NS_fsm = ap_ST_fsm_state377; + end + ap_ST_fsm_state377 : begin + ap_NS_fsm = ap_ST_fsm_state378; + end + ap_ST_fsm_state378 : begin + ap_NS_fsm = ap_ST_fsm_state379; + end + ap_ST_fsm_state379 : begin + ap_NS_fsm = ap_ST_fsm_state380; + end + ap_ST_fsm_state380 : begin + ap_NS_fsm = ap_ST_fsm_state381; + end + ap_ST_fsm_state381 : begin + ap_NS_fsm = ap_ST_fsm_state382; + end + ap_ST_fsm_state382 : begin + ap_NS_fsm = ap_ST_fsm_state383; + end + ap_ST_fsm_state383 : begin + ap_NS_fsm = ap_ST_fsm_state384; + end + ap_ST_fsm_state384 : begin + ap_NS_fsm = ap_ST_fsm_state385; + end + ap_ST_fsm_state385 : begin + ap_NS_fsm = ap_ST_fsm_state386; + end + ap_ST_fsm_state386 : begin + ap_NS_fsm = ap_ST_fsm_state350; + end + ap_ST_fsm_state387 : begin + ap_NS_fsm = ap_ST_fsm_state388; + end + ap_ST_fsm_state388 : begin + ap_NS_fsm = ap_ST_fsm_state389; + end + ap_ST_fsm_state389 : begin + ap_NS_fsm = ap_ST_fsm_state390; + end + ap_ST_fsm_state390 : begin + ap_NS_fsm = ap_ST_fsm_state391; + end + ap_ST_fsm_state391 : begin + ap_NS_fsm = ap_ST_fsm_state392; + end + ap_ST_fsm_state392 : begin + ap_NS_fsm = ap_ST_fsm_state393; + end + ap_ST_fsm_state393 : begin + ap_NS_fsm = ap_ST_fsm_state394; + end + ap_ST_fsm_state394 : begin + ap_NS_fsm = ap_ST_fsm_state395; + end + ap_ST_fsm_state395 : begin + ap_NS_fsm = ap_ST_fsm_state396; + end + ap_ST_fsm_state396 : begin + ap_NS_fsm = ap_ST_fsm_state397; + end + ap_ST_fsm_state397 : begin + ap_NS_fsm = ap_ST_fsm_state398; + end + ap_ST_fsm_state398 : begin + ap_NS_fsm = ap_ST_fsm_state399; + end + ap_ST_fsm_state399 : begin + ap_NS_fsm = ap_ST_fsm_state400; + end + ap_ST_fsm_state400 : begin + ap_NS_fsm = ap_ST_fsm_state401; + end + ap_ST_fsm_state401 : begin + ap_NS_fsm = ap_ST_fsm_state402; + end + ap_ST_fsm_state402 : begin + ap_NS_fsm = ap_ST_fsm_state403; + end + ap_ST_fsm_state403 : begin + ap_NS_fsm = ap_ST_fsm_state404; + end + ap_ST_fsm_state404 : begin + ap_NS_fsm = ap_ST_fsm_state405; + end + ap_ST_fsm_state405 : begin + ap_NS_fsm = ap_ST_fsm_state406; + end + ap_ST_fsm_state406 : begin + ap_NS_fsm = ap_ST_fsm_state407; + end + ap_ST_fsm_state407 : begin + ap_NS_fsm = ap_ST_fsm_state408; + end + ap_ST_fsm_state408 : begin + ap_NS_fsm = ap_ST_fsm_state409; + end + ap_ST_fsm_state409 : begin + ap_NS_fsm = ap_ST_fsm_state410; + end + ap_ST_fsm_state410 : begin + ap_NS_fsm = ap_ST_fsm_state411; + end + ap_ST_fsm_state411 : begin + ap_NS_fsm = ap_ST_fsm_state412; + end + ap_ST_fsm_state412 : begin + ap_NS_fsm = ap_ST_fsm_state413; + end + ap_ST_fsm_state413 : begin + ap_NS_fsm = ap_ST_fsm_state414; + end + ap_ST_fsm_state414 : begin + ap_NS_fsm = ap_ST_fsm_state415; + end + ap_ST_fsm_state415 : begin + ap_NS_fsm = ap_ST_fsm_state416; + end + ap_ST_fsm_state416 : begin + ap_NS_fsm = ap_ST_fsm_state417; + end + ap_ST_fsm_state417 : begin + ap_NS_fsm = ap_ST_fsm_state418; + end + ap_ST_fsm_state418 : begin + ap_NS_fsm = ap_ST_fsm_state419; + end + ap_ST_fsm_state419 : begin + ap_NS_fsm = ap_ST_fsm_state420; + end + ap_ST_fsm_state420 : begin + ap_NS_fsm = ap_ST_fsm_state421; + end + ap_ST_fsm_state421 : begin + ap_NS_fsm = ap_ST_fsm_state422; + end + ap_ST_fsm_state422 : begin + ap_NS_fsm = ap_ST_fsm_state423; + end + ap_ST_fsm_state423 : begin + ap_NS_fsm = ap_ST_fsm_state424; + end + ap_ST_fsm_state424 : begin + ap_NS_fsm = ap_ST_fsm_state425; + end + ap_ST_fsm_state425 : begin + ap_NS_fsm = ap_ST_fsm_state313; + end + ap_ST_fsm_state426 : begin + ap_NS_fsm = ap_ST_fsm_state427; + end + ap_ST_fsm_state427 : begin + ap_NS_fsm = ap_ST_fsm_state428; + end + ap_ST_fsm_state428 : begin + ap_NS_fsm = ap_ST_fsm_state429; + end + ap_ST_fsm_state429 : begin + ap_NS_fsm = ap_ST_fsm_state430; + end + ap_ST_fsm_state430 : begin + ap_NS_fsm = ap_ST_fsm_state431; + end + ap_ST_fsm_state431 : begin + ap_NS_fsm = ap_ST_fsm_state432; + end + ap_ST_fsm_state432 : begin + ap_NS_fsm = ap_ST_fsm_state433; + end + ap_ST_fsm_state433 : begin + ap_NS_fsm = ap_ST_fsm_state434; + end + ap_ST_fsm_state434 : begin + ap_NS_fsm = ap_ST_fsm_state435; + end + ap_ST_fsm_state435 : begin + ap_NS_fsm = ap_ST_fsm_state436; + end + ap_ST_fsm_state436 : begin + ap_NS_fsm = ap_ST_fsm_state437; + end + ap_ST_fsm_state437 : begin + ap_NS_fsm = ap_ST_fsm_state438; + end + ap_ST_fsm_state438 : begin + ap_NS_fsm = ap_ST_fsm_state439; + end + ap_ST_fsm_state439 : begin + ap_NS_fsm = ap_ST_fsm_state440; + end + ap_ST_fsm_state440 : begin + ap_NS_fsm = ap_ST_fsm_state441; + end + ap_ST_fsm_state441 : begin + ap_NS_fsm = ap_ST_fsm_state442; + end + ap_ST_fsm_state442 : begin + ap_NS_fsm = ap_ST_fsm_state443; + end + ap_ST_fsm_state443 : begin + ap_NS_fsm = ap_ST_fsm_state444; + end + ap_ST_fsm_state444 : begin + ap_NS_fsm = ap_ST_fsm_state445; + end + ap_ST_fsm_state445 : begin + ap_NS_fsm = ap_ST_fsm_state446; + end + ap_ST_fsm_state446 : begin + ap_NS_fsm = ap_ST_fsm_state447; + end + ap_ST_fsm_state447 : begin + ap_NS_fsm = ap_ST_fsm_state448; + end + ap_ST_fsm_state448 : begin + ap_NS_fsm = ap_ST_fsm_state449; + end + ap_ST_fsm_state449 : begin + ap_NS_fsm = ap_ST_fsm_state450; + end + ap_ST_fsm_state450 : begin + ap_NS_fsm = ap_ST_fsm_state451; + end + ap_ST_fsm_state451 : begin + ap_NS_fsm = ap_ST_fsm_state452; + end + ap_ST_fsm_state452 : begin + ap_NS_fsm = ap_ST_fsm_state453; + end + ap_ST_fsm_state453 : begin + ap_NS_fsm = ap_ST_fsm_state454; + end + ap_ST_fsm_state454 : begin + ap_NS_fsm = ap_ST_fsm_state455; + end + ap_ST_fsm_state455 : begin + ap_NS_fsm = ap_ST_fsm_state456; + end + ap_ST_fsm_state456 : begin + ap_NS_fsm = ap_ST_fsm_state457; + end + ap_ST_fsm_state457 : begin + ap_NS_fsm = ap_ST_fsm_state458; + end + ap_ST_fsm_state458 : begin + ap_NS_fsm = ap_ST_fsm_state459; + end + ap_ST_fsm_state459 : begin + ap_NS_fsm = ap_ST_fsm_state460; + end + ap_ST_fsm_state460 : begin + ap_NS_fsm = ap_ST_fsm_state461; + end + ap_ST_fsm_state461 : begin + ap_NS_fsm = ap_ST_fsm_state425; + end + ap_ST_fsm_state462 : begin + ap_NS_fsm = ap_ST_fsm_state463; + end + ap_ST_fsm_state463 : begin + if (((ap_ST_fsm_state463 == ap_CS_fsm) & (or_ln223_37_fu_104801_p2 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state464; + end else begin + ap_NS_fsm = ap_ST_fsm_state501; + end + end + ap_ST_fsm_state464 : begin + ap_NS_fsm = ap_ST_fsm_state465; + end + ap_ST_fsm_state465 : begin + ap_NS_fsm = ap_ST_fsm_state466; + end + ap_ST_fsm_state466 : begin + ap_NS_fsm = ap_ST_fsm_state467; + end + ap_ST_fsm_state467 : begin + ap_NS_fsm = ap_ST_fsm_state468; + end + ap_ST_fsm_state468 : begin + ap_NS_fsm = ap_ST_fsm_state469; + end + ap_ST_fsm_state469 : begin + ap_NS_fsm = ap_ST_fsm_state470; + end + ap_ST_fsm_state470 : begin + ap_NS_fsm = ap_ST_fsm_state471; + end + ap_ST_fsm_state471 : begin + ap_NS_fsm = ap_ST_fsm_state472; + end + ap_ST_fsm_state472 : begin + ap_NS_fsm = ap_ST_fsm_state473; + end + ap_ST_fsm_state473 : begin + ap_NS_fsm = ap_ST_fsm_state474; + end + ap_ST_fsm_state474 : begin + ap_NS_fsm = ap_ST_fsm_state475; + end + ap_ST_fsm_state475 : begin + ap_NS_fsm = ap_ST_fsm_state476; + end + ap_ST_fsm_state476 : begin + ap_NS_fsm = ap_ST_fsm_state477; + end + ap_ST_fsm_state477 : begin + ap_NS_fsm = ap_ST_fsm_state478; + end + ap_ST_fsm_state478 : begin + ap_NS_fsm = ap_ST_fsm_state479; + end + ap_ST_fsm_state479 : begin + ap_NS_fsm = ap_ST_fsm_state480; + end + ap_ST_fsm_state480 : begin + ap_NS_fsm = ap_ST_fsm_state481; + end + ap_ST_fsm_state481 : begin + ap_NS_fsm = ap_ST_fsm_state482; + end + ap_ST_fsm_state482 : begin + ap_NS_fsm = ap_ST_fsm_state483; + end + ap_ST_fsm_state483 : begin + ap_NS_fsm = ap_ST_fsm_state484; + end + ap_ST_fsm_state484 : begin + ap_NS_fsm = ap_ST_fsm_state485; + end + ap_ST_fsm_state485 : begin + ap_NS_fsm = ap_ST_fsm_state486; + end + ap_ST_fsm_state486 : begin + ap_NS_fsm = ap_ST_fsm_state487; + end + ap_ST_fsm_state487 : begin + ap_NS_fsm = ap_ST_fsm_state488; + end + ap_ST_fsm_state488 : begin + ap_NS_fsm = ap_ST_fsm_state489; + end + ap_ST_fsm_state489 : begin + ap_NS_fsm = ap_ST_fsm_state490; + end + ap_ST_fsm_state490 : begin + ap_NS_fsm = ap_ST_fsm_state491; + end + ap_ST_fsm_state491 : begin + ap_NS_fsm = ap_ST_fsm_state492; + end + ap_ST_fsm_state492 : begin + ap_NS_fsm = ap_ST_fsm_state493; + end + ap_ST_fsm_state493 : begin + ap_NS_fsm = ap_ST_fsm_state494; + end + ap_ST_fsm_state494 : begin + ap_NS_fsm = ap_ST_fsm_state495; + end + ap_ST_fsm_state495 : begin + ap_NS_fsm = ap_ST_fsm_state496; + end + ap_ST_fsm_state496 : begin + ap_NS_fsm = ap_ST_fsm_state497; + end + ap_ST_fsm_state497 : begin + ap_NS_fsm = ap_ST_fsm_state498; + end + ap_ST_fsm_state498 : begin + ap_NS_fsm = ap_ST_fsm_state499; + end + ap_ST_fsm_state499 : begin + ap_NS_fsm = ap_ST_fsm_state500; + end + ap_ST_fsm_state500 : begin + if (((icmp_ln208_12_fu_105013_p2 == 1'd1) & (ap_ST_fsm_state500 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state311; + end else if (((ap_ST_fsm_state500 == ap_CS_fsm) & (or_ln223_44_fu_105091_p2 == 1'd0) & (icmp_ln208_12_fu_105013_p2 == 1'd0) & (or_ln223_29_reg_134420 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state537; + end else begin + ap_NS_fsm = ap_ST_fsm_state574; + end + end + ap_ST_fsm_state501 : begin + ap_NS_fsm = ap_ST_fsm_state502; + end + ap_ST_fsm_state502 : begin + ap_NS_fsm = ap_ST_fsm_state503; + end + ap_ST_fsm_state503 : begin + ap_NS_fsm = ap_ST_fsm_state504; + end + ap_ST_fsm_state504 : begin + ap_NS_fsm = ap_ST_fsm_state505; + end + ap_ST_fsm_state505 : begin + ap_NS_fsm = ap_ST_fsm_state506; + end + ap_ST_fsm_state506 : begin + ap_NS_fsm = ap_ST_fsm_state507; + end + ap_ST_fsm_state507 : begin + ap_NS_fsm = ap_ST_fsm_state508; + end + ap_ST_fsm_state508 : begin + ap_NS_fsm = ap_ST_fsm_state509; + end + ap_ST_fsm_state509 : begin + ap_NS_fsm = ap_ST_fsm_state510; + end + ap_ST_fsm_state510 : begin + ap_NS_fsm = ap_ST_fsm_state511; + end + ap_ST_fsm_state511 : begin + ap_NS_fsm = ap_ST_fsm_state512; + end + ap_ST_fsm_state512 : begin + ap_NS_fsm = ap_ST_fsm_state513; + end + ap_ST_fsm_state513 : begin + ap_NS_fsm = ap_ST_fsm_state514; + end + ap_ST_fsm_state514 : begin + ap_NS_fsm = ap_ST_fsm_state515; + end + ap_ST_fsm_state515 : begin + ap_NS_fsm = ap_ST_fsm_state516; + end + ap_ST_fsm_state516 : begin + ap_NS_fsm = ap_ST_fsm_state517; + end + ap_ST_fsm_state517 : begin + ap_NS_fsm = ap_ST_fsm_state518; + end + ap_ST_fsm_state518 : begin + ap_NS_fsm = ap_ST_fsm_state519; + end + ap_ST_fsm_state519 : begin + ap_NS_fsm = ap_ST_fsm_state520; + end + ap_ST_fsm_state520 : begin + ap_NS_fsm = ap_ST_fsm_state521; + end + ap_ST_fsm_state521 : begin + ap_NS_fsm = ap_ST_fsm_state522; + end + ap_ST_fsm_state522 : begin + ap_NS_fsm = ap_ST_fsm_state523; + end + ap_ST_fsm_state523 : begin + ap_NS_fsm = ap_ST_fsm_state524; + end + ap_ST_fsm_state524 : begin + ap_NS_fsm = ap_ST_fsm_state525; + end + ap_ST_fsm_state525 : begin + ap_NS_fsm = ap_ST_fsm_state526; + end + ap_ST_fsm_state526 : begin + ap_NS_fsm = ap_ST_fsm_state527; + end + ap_ST_fsm_state527 : begin + ap_NS_fsm = ap_ST_fsm_state528; + end + ap_ST_fsm_state528 : begin + ap_NS_fsm = ap_ST_fsm_state529; + end + ap_ST_fsm_state529 : begin + ap_NS_fsm = ap_ST_fsm_state530; + end + ap_ST_fsm_state530 : begin + ap_NS_fsm = ap_ST_fsm_state531; + end + ap_ST_fsm_state531 : begin + ap_NS_fsm = ap_ST_fsm_state532; + end + ap_ST_fsm_state532 : begin + ap_NS_fsm = ap_ST_fsm_state533; + end + ap_ST_fsm_state533 : begin + ap_NS_fsm = ap_ST_fsm_state534; + end + ap_ST_fsm_state534 : begin + ap_NS_fsm = ap_ST_fsm_state535; + end + ap_ST_fsm_state535 : begin + ap_NS_fsm = ap_ST_fsm_state536; + end + ap_ST_fsm_state536 : begin + ap_NS_fsm = ap_ST_fsm_state500; + end + ap_ST_fsm_state537 : begin + ap_NS_fsm = ap_ST_fsm_state538; + end + ap_ST_fsm_state538 : begin + ap_NS_fsm = ap_ST_fsm_state539; + end + ap_ST_fsm_state539 : begin + ap_NS_fsm = ap_ST_fsm_state540; + end + ap_ST_fsm_state540 : begin + ap_NS_fsm = ap_ST_fsm_state541; + end + ap_ST_fsm_state541 : begin + ap_NS_fsm = ap_ST_fsm_state542; + end + ap_ST_fsm_state542 : begin + ap_NS_fsm = ap_ST_fsm_state543; + end + ap_ST_fsm_state543 : begin + ap_NS_fsm = ap_ST_fsm_state544; + end + ap_ST_fsm_state544 : begin + ap_NS_fsm = ap_ST_fsm_state545; + end + ap_ST_fsm_state545 : begin + ap_NS_fsm = ap_ST_fsm_state546; + end + ap_ST_fsm_state546 : begin + ap_NS_fsm = ap_ST_fsm_state547; + end + ap_ST_fsm_state547 : begin + ap_NS_fsm = ap_ST_fsm_state548; + end + ap_ST_fsm_state548 : begin + ap_NS_fsm = ap_ST_fsm_state549; + end + ap_ST_fsm_state549 : begin + ap_NS_fsm = ap_ST_fsm_state550; + end + ap_ST_fsm_state550 : begin + ap_NS_fsm = ap_ST_fsm_state551; + end + ap_ST_fsm_state551 : begin + ap_NS_fsm = ap_ST_fsm_state552; + end + ap_ST_fsm_state552 : begin + ap_NS_fsm = ap_ST_fsm_state553; + end + ap_ST_fsm_state553 : begin + ap_NS_fsm = ap_ST_fsm_state554; + end + ap_ST_fsm_state554 : begin + ap_NS_fsm = ap_ST_fsm_state555; + end + ap_ST_fsm_state555 : begin + ap_NS_fsm = ap_ST_fsm_state556; + end + ap_ST_fsm_state556 : begin + ap_NS_fsm = ap_ST_fsm_state557; + end + ap_ST_fsm_state557 : begin + ap_NS_fsm = ap_ST_fsm_state558; + end + ap_ST_fsm_state558 : begin + ap_NS_fsm = ap_ST_fsm_state559; + end + ap_ST_fsm_state559 : begin + ap_NS_fsm = ap_ST_fsm_state560; + end + ap_ST_fsm_state560 : begin + ap_NS_fsm = ap_ST_fsm_state561; + end + ap_ST_fsm_state561 : begin + ap_NS_fsm = ap_ST_fsm_state562; + end + ap_ST_fsm_state562 : begin + ap_NS_fsm = ap_ST_fsm_state563; + end + ap_ST_fsm_state563 : begin + ap_NS_fsm = ap_ST_fsm_state564; + end + ap_ST_fsm_state564 : begin + ap_NS_fsm = ap_ST_fsm_state565; + end + ap_ST_fsm_state565 : begin + ap_NS_fsm = ap_ST_fsm_state566; + end + ap_ST_fsm_state566 : begin + ap_NS_fsm = ap_ST_fsm_state567; + end + ap_ST_fsm_state567 : begin + ap_NS_fsm = ap_ST_fsm_state568; + end + ap_ST_fsm_state568 : begin + ap_NS_fsm = ap_ST_fsm_state569; + end + ap_ST_fsm_state569 : begin + ap_NS_fsm = ap_ST_fsm_state570; + end + ap_ST_fsm_state570 : begin + ap_NS_fsm = ap_ST_fsm_state571; + end + ap_ST_fsm_state571 : begin + ap_NS_fsm = ap_ST_fsm_state572; + end + ap_ST_fsm_state572 : begin + ap_NS_fsm = ap_ST_fsm_state573; + end + ap_ST_fsm_state573 : begin + ap_NS_fsm = ap_ST_fsm_state463; + end + ap_ST_fsm_state574 : begin + ap_NS_fsm = ap_ST_fsm_state575; + end + ap_ST_fsm_state575 : begin + ap_NS_fsm = ap_ST_fsm_state576; + end + ap_ST_fsm_state576 : begin + ap_NS_fsm = ap_ST_fsm_state577; + end + ap_ST_fsm_state577 : begin + ap_NS_fsm = ap_ST_fsm_state578; + end + ap_ST_fsm_state578 : begin + ap_NS_fsm = ap_ST_fsm_state579; + end + ap_ST_fsm_state579 : begin + ap_NS_fsm = ap_ST_fsm_state580; + end + ap_ST_fsm_state580 : begin + ap_NS_fsm = ap_ST_fsm_state581; + end + ap_ST_fsm_state581 : begin + ap_NS_fsm = ap_ST_fsm_state582; + end + ap_ST_fsm_state582 : begin + ap_NS_fsm = ap_ST_fsm_state583; + end + ap_ST_fsm_state583 : begin + ap_NS_fsm = ap_ST_fsm_state584; + end + ap_ST_fsm_state584 : begin + ap_NS_fsm = ap_ST_fsm_state585; + end + ap_ST_fsm_state585 : begin + ap_NS_fsm = ap_ST_fsm_state586; + end + ap_ST_fsm_state586 : begin + ap_NS_fsm = ap_ST_fsm_state587; + end + ap_ST_fsm_state587 : begin + ap_NS_fsm = ap_ST_fsm_state588; + end + ap_ST_fsm_state588 : begin + ap_NS_fsm = ap_ST_fsm_state589; + end + ap_ST_fsm_state589 : begin + ap_NS_fsm = ap_ST_fsm_state590; + end + ap_ST_fsm_state590 : begin + ap_NS_fsm = ap_ST_fsm_state591; + end + ap_ST_fsm_state591 : begin + ap_NS_fsm = ap_ST_fsm_state592; + end + ap_ST_fsm_state592 : begin + ap_NS_fsm = ap_ST_fsm_state593; + end + ap_ST_fsm_state593 : begin + ap_NS_fsm = ap_ST_fsm_state594; + end + ap_ST_fsm_state594 : begin + ap_NS_fsm = ap_ST_fsm_state595; + end + ap_ST_fsm_state595 : begin + ap_NS_fsm = ap_ST_fsm_state596; + end + ap_ST_fsm_state596 : begin + ap_NS_fsm = ap_ST_fsm_state597; + end + ap_ST_fsm_state597 : begin + ap_NS_fsm = ap_ST_fsm_state598; + end + ap_ST_fsm_state598 : begin + ap_NS_fsm = ap_ST_fsm_state599; + end + ap_ST_fsm_state599 : begin + ap_NS_fsm = ap_ST_fsm_state600; + end + ap_ST_fsm_state600 : begin + ap_NS_fsm = ap_ST_fsm_state601; + end + ap_ST_fsm_state601 : begin + ap_NS_fsm = ap_ST_fsm_state602; + end + ap_ST_fsm_state602 : begin + ap_NS_fsm = ap_ST_fsm_state603; + end + ap_ST_fsm_state603 : begin + ap_NS_fsm = ap_ST_fsm_state604; + end + ap_ST_fsm_state604 : begin + ap_NS_fsm = ap_ST_fsm_state605; + end + ap_ST_fsm_state605 : begin + ap_NS_fsm = ap_ST_fsm_state606; + end + ap_ST_fsm_state606 : begin + ap_NS_fsm = ap_ST_fsm_state607; + end + ap_ST_fsm_state607 : begin + ap_NS_fsm = ap_ST_fsm_state608; + end + ap_ST_fsm_state608 : begin + ap_NS_fsm = ap_ST_fsm_state609; + end + ap_ST_fsm_state609 : begin + ap_NS_fsm = ap_ST_fsm_state573; + end + ap_ST_fsm_state610 : begin + if (((icmp_ln203_2_fu_105423_p2 == 1'd1) & (ap_ST_fsm_state610 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3; + end else begin + ap_NS_fsm = ap_ST_fsm_state611; + end + end + ap_ST_fsm_state611 : begin + if (((icmp_ln204_2_fu_105463_p2 == 1'd1) & (ap_ST_fsm_state611 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state610; + end else begin + ap_NS_fsm = ap_ST_fsm_state612; + end + end + ap_ST_fsm_state612 : begin + ap_NS_fsm = ap_ST_fsm_state613; + end + ap_ST_fsm_state613 : begin + ap_NS_fsm = ap_ST_fsm_state614; + end + ap_ST_fsm_state614 : begin + if (((ap_ST_fsm_state614 == ap_CS_fsm) & (or_ln223_6_fu_105731_p2 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state615; + end else begin + ap_NS_fsm = ap_ST_fsm_state653; + end + end + ap_ST_fsm_state615 : begin + ap_NS_fsm = ap_ST_fsm_state616; + end + ap_ST_fsm_state616 : begin + ap_NS_fsm = ap_ST_fsm_state617; + end + ap_ST_fsm_state617 : begin + ap_NS_fsm = ap_ST_fsm_state618; + end + ap_ST_fsm_state618 : begin + ap_NS_fsm = ap_ST_fsm_state619; + end + ap_ST_fsm_state619 : begin + ap_NS_fsm = ap_ST_fsm_state620; + end + ap_ST_fsm_state620 : begin + ap_NS_fsm = ap_ST_fsm_state621; + end + ap_ST_fsm_state621 : begin + ap_NS_fsm = ap_ST_fsm_state622; + end + ap_ST_fsm_state622 : begin + ap_NS_fsm = ap_ST_fsm_state623; + end + ap_ST_fsm_state623 : begin + ap_NS_fsm = ap_ST_fsm_state624; + end + ap_ST_fsm_state624 : begin + ap_NS_fsm = ap_ST_fsm_state625; + end + ap_ST_fsm_state625 : begin + ap_NS_fsm = ap_ST_fsm_state626; + end + ap_ST_fsm_state626 : begin + ap_NS_fsm = ap_ST_fsm_state627; + end + ap_ST_fsm_state627 : begin + ap_NS_fsm = ap_ST_fsm_state628; + end + ap_ST_fsm_state628 : begin + ap_NS_fsm = ap_ST_fsm_state629; + end + ap_ST_fsm_state629 : begin + ap_NS_fsm = ap_ST_fsm_state630; + end + ap_ST_fsm_state630 : begin + ap_NS_fsm = ap_ST_fsm_state631; + end + ap_ST_fsm_state631 : begin + ap_NS_fsm = ap_ST_fsm_state632; + end + ap_ST_fsm_state632 : begin + ap_NS_fsm = ap_ST_fsm_state633; + end + ap_ST_fsm_state633 : begin + ap_NS_fsm = ap_ST_fsm_state634; + end + ap_ST_fsm_state634 : begin + ap_NS_fsm = ap_ST_fsm_state635; + end + ap_ST_fsm_state635 : begin + ap_NS_fsm = ap_ST_fsm_state636; + end + ap_ST_fsm_state636 : begin + ap_NS_fsm = ap_ST_fsm_state637; + end + ap_ST_fsm_state637 : begin + ap_NS_fsm = ap_ST_fsm_state638; + end + ap_ST_fsm_state638 : begin + ap_NS_fsm = ap_ST_fsm_state639; + end + ap_ST_fsm_state639 : begin + ap_NS_fsm = ap_ST_fsm_state640; + end + ap_ST_fsm_state640 : begin + ap_NS_fsm = ap_ST_fsm_state641; + end + ap_ST_fsm_state641 : begin + ap_NS_fsm = ap_ST_fsm_state642; + end + ap_ST_fsm_state642 : begin + ap_NS_fsm = ap_ST_fsm_state643; + end + ap_ST_fsm_state643 : begin + ap_NS_fsm = ap_ST_fsm_state644; + end + ap_ST_fsm_state644 : begin + ap_NS_fsm = ap_ST_fsm_state645; + end + ap_ST_fsm_state645 : begin + ap_NS_fsm = ap_ST_fsm_state646; + end + ap_ST_fsm_state646 : begin + ap_NS_fsm = ap_ST_fsm_state647; + end + ap_ST_fsm_state647 : begin + ap_NS_fsm = ap_ST_fsm_state648; + end + ap_ST_fsm_state648 : begin + ap_NS_fsm = ap_ST_fsm_state649; + end + ap_ST_fsm_state649 : begin + ap_NS_fsm = ap_ST_fsm_state650; + end + ap_ST_fsm_state650 : begin + ap_NS_fsm = ap_ST_fsm_state651; + end + ap_ST_fsm_state651 : begin + ap_NS_fsm = ap_ST_fsm_state652; + end + ap_ST_fsm_state652 : begin + if (((icmp_ln206_2_fu_106151_p2 == 1'd1) & (icmp_ln208_2_fu_105943_p2 == 1'd1) & (ap_ST_fsm_state652 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state916; + end else if (((icmp_ln208_2_fu_105943_p2 == 1'd1) & (ap_ST_fsm_state652 == ap_CS_fsm) & (icmp_ln206_2_fu_106151_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state764; + end else if (((ap_ST_fsm_state652 == ap_CS_fsm) & (or_ln223_14_fu_106021_p2 == 1'd0) & (icmp_ln208_2_fu_105943_p2 == 1'd0) & (or_ln223_2_reg_135321 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state689; + end else begin + ap_NS_fsm = ap_ST_fsm_state728; + end + end + ap_ST_fsm_state653 : begin + ap_NS_fsm = ap_ST_fsm_state654; + end + ap_ST_fsm_state654 : begin + ap_NS_fsm = ap_ST_fsm_state655; + end + ap_ST_fsm_state655 : begin + ap_NS_fsm = ap_ST_fsm_state656; + end + ap_ST_fsm_state656 : begin + ap_NS_fsm = ap_ST_fsm_state657; + end + ap_ST_fsm_state657 : begin + ap_NS_fsm = ap_ST_fsm_state658; + end + ap_ST_fsm_state658 : begin + ap_NS_fsm = ap_ST_fsm_state659; + end + ap_ST_fsm_state659 : begin + ap_NS_fsm = ap_ST_fsm_state660; + end + ap_ST_fsm_state660 : begin + ap_NS_fsm = ap_ST_fsm_state661; + end + ap_ST_fsm_state661 : begin + ap_NS_fsm = ap_ST_fsm_state662; + end + ap_ST_fsm_state662 : begin + ap_NS_fsm = ap_ST_fsm_state663; + end + ap_ST_fsm_state663 : begin + ap_NS_fsm = ap_ST_fsm_state664; + end + ap_ST_fsm_state664 : begin + ap_NS_fsm = ap_ST_fsm_state665; + end + ap_ST_fsm_state665 : begin + ap_NS_fsm = ap_ST_fsm_state666; + end + ap_ST_fsm_state666 : begin + ap_NS_fsm = ap_ST_fsm_state667; + end + ap_ST_fsm_state667 : begin + ap_NS_fsm = ap_ST_fsm_state668; + end + ap_ST_fsm_state668 : begin + ap_NS_fsm = ap_ST_fsm_state669; + end + ap_ST_fsm_state669 : begin + ap_NS_fsm = ap_ST_fsm_state670; + end + ap_ST_fsm_state670 : begin + ap_NS_fsm = ap_ST_fsm_state671; + end + ap_ST_fsm_state671 : begin + ap_NS_fsm = ap_ST_fsm_state672; + end + ap_ST_fsm_state672 : begin + ap_NS_fsm = ap_ST_fsm_state673; + end + ap_ST_fsm_state673 : begin + ap_NS_fsm = ap_ST_fsm_state674; + end + ap_ST_fsm_state674 : begin + ap_NS_fsm = ap_ST_fsm_state675; + end + ap_ST_fsm_state675 : begin + ap_NS_fsm = ap_ST_fsm_state676; + end + ap_ST_fsm_state676 : begin + ap_NS_fsm = ap_ST_fsm_state677; + end + ap_ST_fsm_state677 : begin + ap_NS_fsm = ap_ST_fsm_state678; + end + ap_ST_fsm_state678 : begin + ap_NS_fsm = ap_ST_fsm_state679; + end + ap_ST_fsm_state679 : begin + ap_NS_fsm = ap_ST_fsm_state680; + end + ap_ST_fsm_state680 : begin + ap_NS_fsm = ap_ST_fsm_state681; + end + ap_ST_fsm_state681 : begin + ap_NS_fsm = ap_ST_fsm_state682; + end + ap_ST_fsm_state682 : begin + ap_NS_fsm = ap_ST_fsm_state683; + end + ap_ST_fsm_state683 : begin + ap_NS_fsm = ap_ST_fsm_state684; + end + ap_ST_fsm_state684 : begin + ap_NS_fsm = ap_ST_fsm_state685; + end + ap_ST_fsm_state685 : begin + ap_NS_fsm = ap_ST_fsm_state686; + end + ap_ST_fsm_state686 : begin + ap_NS_fsm = ap_ST_fsm_state687; + end + ap_ST_fsm_state687 : begin + ap_NS_fsm = ap_ST_fsm_state688; + end + ap_ST_fsm_state688 : begin + ap_NS_fsm = ap_ST_fsm_state652; + end + ap_ST_fsm_state689 : begin + ap_NS_fsm = ap_ST_fsm_state690; + end + ap_ST_fsm_state690 : begin + ap_NS_fsm = ap_ST_fsm_state691; + end + ap_ST_fsm_state691 : begin + ap_NS_fsm = ap_ST_fsm_state692; + end + ap_ST_fsm_state692 : begin + ap_NS_fsm = ap_ST_fsm_state693; + end + ap_ST_fsm_state693 : begin + ap_NS_fsm = ap_ST_fsm_state694; + end + ap_ST_fsm_state694 : begin + ap_NS_fsm = ap_ST_fsm_state695; + end + ap_ST_fsm_state695 : begin + ap_NS_fsm = ap_ST_fsm_state696; + end + ap_ST_fsm_state696 : begin + ap_NS_fsm = ap_ST_fsm_state697; + end + ap_ST_fsm_state697 : begin + ap_NS_fsm = ap_ST_fsm_state698; + end + ap_ST_fsm_state698 : begin + ap_NS_fsm = ap_ST_fsm_state699; + end + ap_ST_fsm_state699 : begin + ap_NS_fsm = ap_ST_fsm_state700; + end + ap_ST_fsm_state700 : begin + ap_NS_fsm = ap_ST_fsm_state701; + end + ap_ST_fsm_state701 : begin + ap_NS_fsm = ap_ST_fsm_state702; + end + ap_ST_fsm_state702 : begin + ap_NS_fsm = ap_ST_fsm_state703; + end + ap_ST_fsm_state703 : begin + ap_NS_fsm = ap_ST_fsm_state704; + end + ap_ST_fsm_state704 : begin + ap_NS_fsm = ap_ST_fsm_state705; + end + ap_ST_fsm_state705 : begin + ap_NS_fsm = ap_ST_fsm_state706; + end + ap_ST_fsm_state706 : begin + ap_NS_fsm = ap_ST_fsm_state707; + end + ap_ST_fsm_state707 : begin + ap_NS_fsm = ap_ST_fsm_state708; + end + ap_ST_fsm_state708 : begin + ap_NS_fsm = ap_ST_fsm_state709; + end + ap_ST_fsm_state709 : begin + ap_NS_fsm = ap_ST_fsm_state710; + end + ap_ST_fsm_state710 : begin + ap_NS_fsm = ap_ST_fsm_state711; + end + ap_ST_fsm_state711 : begin + ap_NS_fsm = ap_ST_fsm_state712; + end + ap_ST_fsm_state712 : begin + ap_NS_fsm = ap_ST_fsm_state713; + end + ap_ST_fsm_state713 : begin + ap_NS_fsm = ap_ST_fsm_state714; + end + ap_ST_fsm_state714 : begin + ap_NS_fsm = ap_ST_fsm_state715; + end + ap_ST_fsm_state715 : begin + ap_NS_fsm = ap_ST_fsm_state716; + end + ap_ST_fsm_state716 : begin + ap_NS_fsm = ap_ST_fsm_state717; + end + ap_ST_fsm_state717 : begin + ap_NS_fsm = ap_ST_fsm_state718; + end + ap_ST_fsm_state718 : begin + ap_NS_fsm = ap_ST_fsm_state719; + end + ap_ST_fsm_state719 : begin + ap_NS_fsm = ap_ST_fsm_state720; + end + ap_ST_fsm_state720 : begin + ap_NS_fsm = ap_ST_fsm_state721; + end + ap_ST_fsm_state721 : begin + ap_NS_fsm = ap_ST_fsm_state722; + end + ap_ST_fsm_state722 : begin + ap_NS_fsm = ap_ST_fsm_state723; + end + ap_ST_fsm_state723 : begin + ap_NS_fsm = ap_ST_fsm_state724; + end + ap_ST_fsm_state724 : begin + ap_NS_fsm = ap_ST_fsm_state725; + end + ap_ST_fsm_state725 : begin + ap_NS_fsm = ap_ST_fsm_state726; + end + ap_ST_fsm_state726 : begin + ap_NS_fsm = ap_ST_fsm_state727; + end + ap_ST_fsm_state727 : begin + ap_NS_fsm = ap_ST_fsm_state614; + end + ap_ST_fsm_state728 : begin + ap_NS_fsm = ap_ST_fsm_state729; + end + ap_ST_fsm_state729 : begin + ap_NS_fsm = ap_ST_fsm_state730; + end + ap_ST_fsm_state730 : begin + ap_NS_fsm = ap_ST_fsm_state731; + end + ap_ST_fsm_state731 : begin + ap_NS_fsm = ap_ST_fsm_state732; + end + ap_ST_fsm_state732 : begin + ap_NS_fsm = ap_ST_fsm_state733; + end + ap_ST_fsm_state733 : begin + ap_NS_fsm = ap_ST_fsm_state734; + end + ap_ST_fsm_state734 : begin + ap_NS_fsm = ap_ST_fsm_state735; + end + ap_ST_fsm_state735 : begin + ap_NS_fsm = ap_ST_fsm_state736; + end + ap_ST_fsm_state736 : begin + ap_NS_fsm = ap_ST_fsm_state737; + end + ap_ST_fsm_state737 : begin + ap_NS_fsm = ap_ST_fsm_state738; + end + ap_ST_fsm_state738 : begin + ap_NS_fsm = ap_ST_fsm_state739; + end + ap_ST_fsm_state739 : begin + ap_NS_fsm = ap_ST_fsm_state740; + end + ap_ST_fsm_state740 : begin + ap_NS_fsm = ap_ST_fsm_state741; + end + ap_ST_fsm_state741 : begin + ap_NS_fsm = ap_ST_fsm_state742; + end + ap_ST_fsm_state742 : begin + ap_NS_fsm = ap_ST_fsm_state743; + end + ap_ST_fsm_state743 : begin + ap_NS_fsm = ap_ST_fsm_state744; + end + ap_ST_fsm_state744 : begin + ap_NS_fsm = ap_ST_fsm_state745; + end + ap_ST_fsm_state745 : begin + ap_NS_fsm = ap_ST_fsm_state746; + end + ap_ST_fsm_state746 : begin + ap_NS_fsm = ap_ST_fsm_state747; + end + ap_ST_fsm_state747 : begin + ap_NS_fsm = ap_ST_fsm_state748; + end + ap_ST_fsm_state748 : begin + ap_NS_fsm = ap_ST_fsm_state749; + end + ap_ST_fsm_state749 : begin + ap_NS_fsm = ap_ST_fsm_state750; + end + ap_ST_fsm_state750 : begin + ap_NS_fsm = ap_ST_fsm_state751; + end + ap_ST_fsm_state751 : begin + ap_NS_fsm = ap_ST_fsm_state752; + end + ap_ST_fsm_state752 : begin + ap_NS_fsm = ap_ST_fsm_state753; + end + ap_ST_fsm_state753 : begin + ap_NS_fsm = ap_ST_fsm_state754; + end + ap_ST_fsm_state754 : begin + ap_NS_fsm = ap_ST_fsm_state755; + end + ap_ST_fsm_state755 : begin + ap_NS_fsm = ap_ST_fsm_state756; + end + ap_ST_fsm_state756 : begin + ap_NS_fsm = ap_ST_fsm_state757; + end + ap_ST_fsm_state757 : begin + ap_NS_fsm = ap_ST_fsm_state758; + end + ap_ST_fsm_state758 : begin + ap_NS_fsm = ap_ST_fsm_state759; + end + ap_ST_fsm_state759 : begin + ap_NS_fsm = ap_ST_fsm_state760; + end + ap_ST_fsm_state760 : begin + ap_NS_fsm = ap_ST_fsm_state761; + end + ap_ST_fsm_state761 : begin + ap_NS_fsm = ap_ST_fsm_state762; + end + ap_ST_fsm_state762 : begin + ap_NS_fsm = ap_ST_fsm_state763; + end + ap_ST_fsm_state763 : begin + ap_NS_fsm = ap_ST_fsm_state727; + end + ap_ST_fsm_state764 : begin + ap_NS_fsm = ap_ST_fsm_state765; + end + ap_ST_fsm_state765 : begin + if (((ap_ST_fsm_state765 == ap_CS_fsm) & (or_ln223_13_reg_136251 == 1'd0) & (or_ln223_22_fu_106609_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state766; + end else begin + ap_NS_fsm = ap_ST_fsm_state805; + end + end + ap_ST_fsm_state766 : begin + ap_NS_fsm = ap_ST_fsm_state767; + end + ap_ST_fsm_state767 : begin + ap_NS_fsm = ap_ST_fsm_state768; + end + ap_ST_fsm_state768 : begin + ap_NS_fsm = ap_ST_fsm_state769; + end + ap_ST_fsm_state769 : begin + ap_NS_fsm = ap_ST_fsm_state770; + end + ap_ST_fsm_state770 : begin + ap_NS_fsm = ap_ST_fsm_state771; + end + ap_ST_fsm_state771 : begin + ap_NS_fsm = ap_ST_fsm_state772; + end + ap_ST_fsm_state772 : begin + ap_NS_fsm = ap_ST_fsm_state773; + end + ap_ST_fsm_state773 : begin + ap_NS_fsm = ap_ST_fsm_state774; + end + ap_ST_fsm_state774 : begin + ap_NS_fsm = ap_ST_fsm_state775; + end + ap_ST_fsm_state775 : begin + ap_NS_fsm = ap_ST_fsm_state776; + end + ap_ST_fsm_state776 : begin + ap_NS_fsm = ap_ST_fsm_state777; + end + ap_ST_fsm_state777 : begin + ap_NS_fsm = ap_ST_fsm_state778; + end + ap_ST_fsm_state778 : begin + ap_NS_fsm = ap_ST_fsm_state779; + end + ap_ST_fsm_state779 : begin + ap_NS_fsm = ap_ST_fsm_state780; + end + ap_ST_fsm_state780 : begin + ap_NS_fsm = ap_ST_fsm_state781; + end + ap_ST_fsm_state781 : begin + ap_NS_fsm = ap_ST_fsm_state782; + end + ap_ST_fsm_state782 : begin + ap_NS_fsm = ap_ST_fsm_state783; + end + ap_ST_fsm_state783 : begin + ap_NS_fsm = ap_ST_fsm_state784; + end + ap_ST_fsm_state784 : begin + ap_NS_fsm = ap_ST_fsm_state785; + end + ap_ST_fsm_state785 : begin + ap_NS_fsm = ap_ST_fsm_state786; + end + ap_ST_fsm_state786 : begin + ap_NS_fsm = ap_ST_fsm_state787; + end + ap_ST_fsm_state787 : begin + ap_NS_fsm = ap_ST_fsm_state788; + end + ap_ST_fsm_state788 : begin + ap_NS_fsm = ap_ST_fsm_state789; + end + ap_ST_fsm_state789 : begin + ap_NS_fsm = ap_ST_fsm_state790; + end + ap_ST_fsm_state790 : begin + ap_NS_fsm = ap_ST_fsm_state791; + end + ap_ST_fsm_state791 : begin + ap_NS_fsm = ap_ST_fsm_state792; + end + ap_ST_fsm_state792 : begin + ap_NS_fsm = ap_ST_fsm_state793; + end + ap_ST_fsm_state793 : begin + ap_NS_fsm = ap_ST_fsm_state794; + end + ap_ST_fsm_state794 : begin + ap_NS_fsm = ap_ST_fsm_state795; + end + ap_ST_fsm_state795 : begin + ap_NS_fsm = ap_ST_fsm_state796; + end + ap_ST_fsm_state796 : begin + ap_NS_fsm = ap_ST_fsm_state797; + end + ap_ST_fsm_state797 : begin + ap_NS_fsm = ap_ST_fsm_state798; + end + ap_ST_fsm_state798 : begin + ap_NS_fsm = ap_ST_fsm_state799; + end + ap_ST_fsm_state799 : begin + ap_NS_fsm = ap_ST_fsm_state800; + end + ap_ST_fsm_state800 : begin + ap_NS_fsm = ap_ST_fsm_state801; + end + ap_ST_fsm_state801 : begin + ap_NS_fsm = ap_ST_fsm_state802; + end + ap_ST_fsm_state802 : begin + ap_NS_fsm = ap_ST_fsm_state803; + end + ap_ST_fsm_state803 : begin + ap_NS_fsm = ap_ST_fsm_state804; + end + ap_ST_fsm_state804 : begin + if (((ap_ST_fsm_state804 == ap_CS_fsm) & (icmp_ln208_7_fu_106822_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state612; + end else if (((ap_ST_fsm_state804 == ap_CS_fsm) & (or_ln223_32_fu_106900_p2 == 1'd0) & (icmp_ln208_7_fu_106822_p2 == 1'd0) & (or_ln223_13_reg_136251 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state841; + end else begin + ap_NS_fsm = ap_ST_fsm_state880; + end + end + ap_ST_fsm_state805 : begin + ap_NS_fsm = ap_ST_fsm_state806; + end + ap_ST_fsm_state806 : begin + ap_NS_fsm = ap_ST_fsm_state807; + end + ap_ST_fsm_state807 : begin + ap_NS_fsm = ap_ST_fsm_state808; + end + ap_ST_fsm_state808 : begin + ap_NS_fsm = ap_ST_fsm_state809; + end + ap_ST_fsm_state809 : begin + ap_NS_fsm = ap_ST_fsm_state810; + end + ap_ST_fsm_state810 : begin + ap_NS_fsm = ap_ST_fsm_state811; + end + ap_ST_fsm_state811 : begin + ap_NS_fsm = ap_ST_fsm_state812; + end + ap_ST_fsm_state812 : begin + ap_NS_fsm = ap_ST_fsm_state813; + end + ap_ST_fsm_state813 : begin + ap_NS_fsm = ap_ST_fsm_state814; + end + ap_ST_fsm_state814 : begin + ap_NS_fsm = ap_ST_fsm_state815; + end + ap_ST_fsm_state815 : begin + ap_NS_fsm = ap_ST_fsm_state816; + end + ap_ST_fsm_state816 : begin + ap_NS_fsm = ap_ST_fsm_state817; + end + ap_ST_fsm_state817 : begin + ap_NS_fsm = ap_ST_fsm_state818; + end + ap_ST_fsm_state818 : begin + ap_NS_fsm = ap_ST_fsm_state819; + end + ap_ST_fsm_state819 : begin + ap_NS_fsm = ap_ST_fsm_state820; + end + ap_ST_fsm_state820 : begin + ap_NS_fsm = ap_ST_fsm_state821; + end + ap_ST_fsm_state821 : begin + ap_NS_fsm = ap_ST_fsm_state822; + end + ap_ST_fsm_state822 : begin + ap_NS_fsm = ap_ST_fsm_state823; + end + ap_ST_fsm_state823 : begin + ap_NS_fsm = ap_ST_fsm_state824; + end + ap_ST_fsm_state824 : begin + ap_NS_fsm = ap_ST_fsm_state825; + end + ap_ST_fsm_state825 : begin + ap_NS_fsm = ap_ST_fsm_state826; + end + ap_ST_fsm_state826 : begin + ap_NS_fsm = ap_ST_fsm_state827; + end + ap_ST_fsm_state827 : begin + ap_NS_fsm = ap_ST_fsm_state828; + end + ap_ST_fsm_state828 : begin + ap_NS_fsm = ap_ST_fsm_state829; + end + ap_ST_fsm_state829 : begin + ap_NS_fsm = ap_ST_fsm_state830; + end + ap_ST_fsm_state830 : begin + ap_NS_fsm = ap_ST_fsm_state831; + end + ap_ST_fsm_state831 : begin + ap_NS_fsm = ap_ST_fsm_state832; + end + ap_ST_fsm_state832 : begin + ap_NS_fsm = ap_ST_fsm_state833; + end + ap_ST_fsm_state833 : begin + ap_NS_fsm = ap_ST_fsm_state834; + end + ap_ST_fsm_state834 : begin + ap_NS_fsm = ap_ST_fsm_state835; + end + ap_ST_fsm_state835 : begin + ap_NS_fsm = ap_ST_fsm_state836; + end + ap_ST_fsm_state836 : begin + ap_NS_fsm = ap_ST_fsm_state837; + end + ap_ST_fsm_state837 : begin + ap_NS_fsm = ap_ST_fsm_state838; + end + ap_ST_fsm_state838 : begin + ap_NS_fsm = ap_ST_fsm_state839; + end + ap_ST_fsm_state839 : begin + ap_NS_fsm = ap_ST_fsm_state840; + end + ap_ST_fsm_state840 : begin + ap_NS_fsm = ap_ST_fsm_state804; + end + ap_ST_fsm_state841 : begin + ap_NS_fsm = ap_ST_fsm_state842; + end + ap_ST_fsm_state842 : begin + ap_NS_fsm = ap_ST_fsm_state843; + end + ap_ST_fsm_state843 : begin + ap_NS_fsm = ap_ST_fsm_state844; + end + ap_ST_fsm_state844 : begin + ap_NS_fsm = ap_ST_fsm_state845; + end + ap_ST_fsm_state845 : begin + ap_NS_fsm = ap_ST_fsm_state846; + end + ap_ST_fsm_state846 : begin + ap_NS_fsm = ap_ST_fsm_state847; + end + ap_ST_fsm_state847 : begin + ap_NS_fsm = ap_ST_fsm_state848; + end + ap_ST_fsm_state848 : begin + ap_NS_fsm = ap_ST_fsm_state849; + end + ap_ST_fsm_state849 : begin + ap_NS_fsm = ap_ST_fsm_state850; + end + ap_ST_fsm_state850 : begin + ap_NS_fsm = ap_ST_fsm_state851; + end + ap_ST_fsm_state851 : begin + ap_NS_fsm = ap_ST_fsm_state852; + end + ap_ST_fsm_state852 : begin + ap_NS_fsm = ap_ST_fsm_state853; + end + ap_ST_fsm_state853 : begin + ap_NS_fsm = ap_ST_fsm_state854; + end + ap_ST_fsm_state854 : begin + ap_NS_fsm = ap_ST_fsm_state855; + end + ap_ST_fsm_state855 : begin + ap_NS_fsm = ap_ST_fsm_state856; + end + ap_ST_fsm_state856 : begin + ap_NS_fsm = ap_ST_fsm_state857; + end + ap_ST_fsm_state857 : begin + ap_NS_fsm = ap_ST_fsm_state858; + end + ap_ST_fsm_state858 : begin + ap_NS_fsm = ap_ST_fsm_state859; + end + ap_ST_fsm_state859 : begin + ap_NS_fsm = ap_ST_fsm_state860; + end + ap_ST_fsm_state860 : begin + ap_NS_fsm = ap_ST_fsm_state861; + end + ap_ST_fsm_state861 : begin + ap_NS_fsm = ap_ST_fsm_state862; + end + ap_ST_fsm_state862 : begin + ap_NS_fsm = ap_ST_fsm_state863; + end + ap_ST_fsm_state863 : begin + ap_NS_fsm = ap_ST_fsm_state864; + end + ap_ST_fsm_state864 : begin + ap_NS_fsm = ap_ST_fsm_state865; + end + ap_ST_fsm_state865 : begin + ap_NS_fsm = ap_ST_fsm_state866; + end + ap_ST_fsm_state866 : begin + ap_NS_fsm = ap_ST_fsm_state867; + end + ap_ST_fsm_state867 : begin + ap_NS_fsm = ap_ST_fsm_state868; + end + ap_ST_fsm_state868 : begin + ap_NS_fsm = ap_ST_fsm_state869; + end + ap_ST_fsm_state869 : begin + ap_NS_fsm = ap_ST_fsm_state870; + end + ap_ST_fsm_state870 : begin + ap_NS_fsm = ap_ST_fsm_state871; + end + ap_ST_fsm_state871 : begin + ap_NS_fsm = ap_ST_fsm_state872; + end + ap_ST_fsm_state872 : begin + ap_NS_fsm = ap_ST_fsm_state873; + end + ap_ST_fsm_state873 : begin + ap_NS_fsm = ap_ST_fsm_state874; + end + ap_ST_fsm_state874 : begin + ap_NS_fsm = ap_ST_fsm_state875; + end + ap_ST_fsm_state875 : begin + ap_NS_fsm = ap_ST_fsm_state876; + end + ap_ST_fsm_state876 : begin + ap_NS_fsm = ap_ST_fsm_state877; + end + ap_ST_fsm_state877 : begin + ap_NS_fsm = ap_ST_fsm_state878; + end + ap_ST_fsm_state878 : begin + ap_NS_fsm = ap_ST_fsm_state879; + end + ap_ST_fsm_state879 : begin + ap_NS_fsm = ap_ST_fsm_state765; + end + ap_ST_fsm_state880 : begin + ap_NS_fsm = ap_ST_fsm_state881; + end + ap_ST_fsm_state881 : begin + ap_NS_fsm = ap_ST_fsm_state882; + end + ap_ST_fsm_state882 : begin + ap_NS_fsm = ap_ST_fsm_state883; + end + ap_ST_fsm_state883 : begin + ap_NS_fsm = ap_ST_fsm_state884; + end + ap_ST_fsm_state884 : begin + ap_NS_fsm = ap_ST_fsm_state885; + end + ap_ST_fsm_state885 : begin + ap_NS_fsm = ap_ST_fsm_state886; + end + ap_ST_fsm_state886 : begin + ap_NS_fsm = ap_ST_fsm_state887; + end + ap_ST_fsm_state887 : begin + ap_NS_fsm = ap_ST_fsm_state888; + end + ap_ST_fsm_state888 : begin + ap_NS_fsm = ap_ST_fsm_state889; + end + ap_ST_fsm_state889 : begin + ap_NS_fsm = ap_ST_fsm_state890; + end + ap_ST_fsm_state890 : begin + ap_NS_fsm = ap_ST_fsm_state891; + end + ap_ST_fsm_state891 : begin + ap_NS_fsm = ap_ST_fsm_state892; + end + ap_ST_fsm_state892 : begin + ap_NS_fsm = ap_ST_fsm_state893; + end + ap_ST_fsm_state893 : begin + ap_NS_fsm = ap_ST_fsm_state894; + end + ap_ST_fsm_state894 : begin + ap_NS_fsm = ap_ST_fsm_state895; + end + ap_ST_fsm_state895 : begin + ap_NS_fsm = ap_ST_fsm_state896; + end + ap_ST_fsm_state896 : begin + ap_NS_fsm = ap_ST_fsm_state897; + end + ap_ST_fsm_state897 : begin + ap_NS_fsm = ap_ST_fsm_state898; + end + ap_ST_fsm_state898 : begin + ap_NS_fsm = ap_ST_fsm_state899; + end + ap_ST_fsm_state899 : begin + ap_NS_fsm = ap_ST_fsm_state900; + end + ap_ST_fsm_state900 : begin + ap_NS_fsm = ap_ST_fsm_state901; + end + ap_ST_fsm_state901 : begin + ap_NS_fsm = ap_ST_fsm_state902; + end + ap_ST_fsm_state902 : begin + ap_NS_fsm = ap_ST_fsm_state903; + end + ap_ST_fsm_state903 : begin + ap_NS_fsm = ap_ST_fsm_state904; + end + ap_ST_fsm_state904 : begin + ap_NS_fsm = ap_ST_fsm_state905; + end + ap_ST_fsm_state905 : begin + ap_NS_fsm = ap_ST_fsm_state906; + end + ap_ST_fsm_state906 : begin + ap_NS_fsm = ap_ST_fsm_state907; + end + ap_ST_fsm_state907 : begin + ap_NS_fsm = ap_ST_fsm_state908; + end + ap_ST_fsm_state908 : begin + ap_NS_fsm = ap_ST_fsm_state909; + end + ap_ST_fsm_state909 : begin + ap_NS_fsm = ap_ST_fsm_state910; + end + ap_ST_fsm_state910 : begin + ap_NS_fsm = ap_ST_fsm_state911; + end + ap_ST_fsm_state911 : begin + ap_NS_fsm = ap_ST_fsm_state912; + end + ap_ST_fsm_state912 : begin + ap_NS_fsm = ap_ST_fsm_state913; + end + ap_ST_fsm_state913 : begin + ap_NS_fsm = ap_ST_fsm_state914; + end + ap_ST_fsm_state914 : begin + ap_NS_fsm = ap_ST_fsm_state915; + end + ap_ST_fsm_state915 : begin + ap_NS_fsm = ap_ST_fsm_state879; + end + ap_ST_fsm_state916 : begin + ap_NS_fsm = ap_ST_fsm_state917; + end + ap_ST_fsm_state917 : begin + ap_NS_fsm = ap_ST_fsm_state918; + end + ap_ST_fsm_state918 : begin + if (((ap_ST_fsm_state918 == ap_CS_fsm) & (or_ln223_25_fu_107413_p2 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state919; + end else begin + ap_NS_fsm = ap_ST_fsm_state956; + end + end + ap_ST_fsm_state919 : begin + ap_NS_fsm = ap_ST_fsm_state920; + end + ap_ST_fsm_state920 : begin + ap_NS_fsm = ap_ST_fsm_state921; + end + ap_ST_fsm_state921 : begin + ap_NS_fsm = ap_ST_fsm_state922; + end + ap_ST_fsm_state922 : begin + ap_NS_fsm = ap_ST_fsm_state923; + end + ap_ST_fsm_state923 : begin + ap_NS_fsm = ap_ST_fsm_state924; + end + ap_ST_fsm_state924 : begin + ap_NS_fsm = ap_ST_fsm_state925; + end + ap_ST_fsm_state925 : begin + ap_NS_fsm = ap_ST_fsm_state926; + end + ap_ST_fsm_state926 : begin + ap_NS_fsm = ap_ST_fsm_state927; + end + ap_ST_fsm_state927 : begin + ap_NS_fsm = ap_ST_fsm_state928; + end + ap_ST_fsm_state928 : begin + ap_NS_fsm = ap_ST_fsm_state929; + end + ap_ST_fsm_state929 : begin + ap_NS_fsm = ap_ST_fsm_state930; + end + ap_ST_fsm_state930 : begin + ap_NS_fsm = ap_ST_fsm_state931; + end + ap_ST_fsm_state931 : begin + ap_NS_fsm = ap_ST_fsm_state932; + end + ap_ST_fsm_state932 : begin + ap_NS_fsm = ap_ST_fsm_state933; + end + ap_ST_fsm_state933 : begin + ap_NS_fsm = ap_ST_fsm_state934; + end + ap_ST_fsm_state934 : begin + ap_NS_fsm = ap_ST_fsm_state935; + end + ap_ST_fsm_state935 : begin + ap_NS_fsm = ap_ST_fsm_state936; + end + ap_ST_fsm_state936 : begin + ap_NS_fsm = ap_ST_fsm_state937; + end + ap_ST_fsm_state937 : begin + ap_NS_fsm = ap_ST_fsm_state938; + end + ap_ST_fsm_state938 : begin + ap_NS_fsm = ap_ST_fsm_state939; + end + ap_ST_fsm_state939 : begin + ap_NS_fsm = ap_ST_fsm_state940; + end + ap_ST_fsm_state940 : begin + ap_NS_fsm = ap_ST_fsm_state941; + end + ap_ST_fsm_state941 : begin + ap_NS_fsm = ap_ST_fsm_state942; + end + ap_ST_fsm_state942 : begin + ap_NS_fsm = ap_ST_fsm_state943; + end + ap_ST_fsm_state943 : begin + ap_NS_fsm = ap_ST_fsm_state944; + end + ap_ST_fsm_state944 : begin + ap_NS_fsm = ap_ST_fsm_state945; + end + ap_ST_fsm_state945 : begin + ap_NS_fsm = ap_ST_fsm_state946; + end + ap_ST_fsm_state946 : begin + ap_NS_fsm = ap_ST_fsm_state947; + end + ap_ST_fsm_state947 : begin + ap_NS_fsm = ap_ST_fsm_state948; + end + ap_ST_fsm_state948 : begin + ap_NS_fsm = ap_ST_fsm_state949; + end + ap_ST_fsm_state949 : begin + ap_NS_fsm = ap_ST_fsm_state950; + end + ap_ST_fsm_state950 : begin + ap_NS_fsm = ap_ST_fsm_state951; + end + ap_ST_fsm_state951 : begin + ap_NS_fsm = ap_ST_fsm_state952; + end + ap_ST_fsm_state952 : begin + ap_NS_fsm = ap_ST_fsm_state953; + end + ap_ST_fsm_state953 : begin + ap_NS_fsm = ap_ST_fsm_state954; + end + ap_ST_fsm_state954 : begin + ap_NS_fsm = ap_ST_fsm_state955; + end + ap_ST_fsm_state955 : begin + if (((ap_ST_fsm_state955 == ap_CS_fsm) & (icmp_ln206_6_fu_107831_p2 == 1'd1) & (icmp_ln208_9_fu_107624_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state611; + end else if (((ap_ST_fsm_state955 == ap_CS_fsm) & (icmp_ln208_9_fu_107624_p2 == 1'd1) & (icmp_ln206_6_fu_107831_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state1067; + end else if (((ap_ST_fsm_state955 == ap_CS_fsm) & (or_ln223_36_fu_107702_p2 == 1'd0) & (icmp_ln208_9_fu_107624_p2 == 1'd0) & (or_ln223_17_reg_137110 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state992; + end else begin + ap_NS_fsm = ap_ST_fsm_state1031; + end + end + ap_ST_fsm_state956 : begin + ap_NS_fsm = ap_ST_fsm_state957; + end + ap_ST_fsm_state957 : begin + ap_NS_fsm = ap_ST_fsm_state958; + end + ap_ST_fsm_state958 : begin + ap_NS_fsm = ap_ST_fsm_state959; + end + ap_ST_fsm_state959 : begin + ap_NS_fsm = ap_ST_fsm_state960; + end + ap_ST_fsm_state960 : begin + ap_NS_fsm = ap_ST_fsm_state961; + end + ap_ST_fsm_state961 : begin + ap_NS_fsm = ap_ST_fsm_state962; + end + ap_ST_fsm_state962 : begin + ap_NS_fsm = ap_ST_fsm_state963; + end + ap_ST_fsm_state963 : begin + ap_NS_fsm = ap_ST_fsm_state964; + end + ap_ST_fsm_state964 : begin + ap_NS_fsm = ap_ST_fsm_state965; + end + ap_ST_fsm_state965 : begin + ap_NS_fsm = ap_ST_fsm_state966; + end + ap_ST_fsm_state966 : begin + ap_NS_fsm = ap_ST_fsm_state967; + end + ap_ST_fsm_state967 : begin + ap_NS_fsm = ap_ST_fsm_state968; + end + ap_ST_fsm_state968 : begin + ap_NS_fsm = ap_ST_fsm_state969; + end + ap_ST_fsm_state969 : begin + ap_NS_fsm = ap_ST_fsm_state970; + end + ap_ST_fsm_state970 : begin + ap_NS_fsm = ap_ST_fsm_state971; + end + ap_ST_fsm_state971 : begin + ap_NS_fsm = ap_ST_fsm_state972; + end + ap_ST_fsm_state972 : begin + ap_NS_fsm = ap_ST_fsm_state973; + end + ap_ST_fsm_state973 : begin + ap_NS_fsm = ap_ST_fsm_state974; + end + ap_ST_fsm_state974 : begin + ap_NS_fsm = ap_ST_fsm_state975; + end + ap_ST_fsm_state975 : begin + ap_NS_fsm = ap_ST_fsm_state976; + end + ap_ST_fsm_state976 : begin + ap_NS_fsm = ap_ST_fsm_state977; + end + ap_ST_fsm_state977 : begin + ap_NS_fsm = ap_ST_fsm_state978; + end + ap_ST_fsm_state978 : begin + ap_NS_fsm = ap_ST_fsm_state979; + end + ap_ST_fsm_state979 : begin + ap_NS_fsm = ap_ST_fsm_state980; + end + ap_ST_fsm_state980 : begin + ap_NS_fsm = ap_ST_fsm_state981; + end + ap_ST_fsm_state981 : begin + ap_NS_fsm = ap_ST_fsm_state982; + end + ap_ST_fsm_state982 : begin + ap_NS_fsm = ap_ST_fsm_state983; + end + ap_ST_fsm_state983 : begin + ap_NS_fsm = ap_ST_fsm_state984; + end + ap_ST_fsm_state984 : begin + ap_NS_fsm = ap_ST_fsm_state985; + end + ap_ST_fsm_state985 : begin + ap_NS_fsm = ap_ST_fsm_state986; + end + ap_ST_fsm_state986 : begin + ap_NS_fsm = ap_ST_fsm_state987; + end + ap_ST_fsm_state987 : begin + ap_NS_fsm = ap_ST_fsm_state988; + end + ap_ST_fsm_state988 : begin + ap_NS_fsm = ap_ST_fsm_state989; + end + ap_ST_fsm_state989 : begin + ap_NS_fsm = ap_ST_fsm_state990; + end + ap_ST_fsm_state990 : begin + ap_NS_fsm = ap_ST_fsm_state991; + end + ap_ST_fsm_state991 : begin + ap_NS_fsm = ap_ST_fsm_state955; + end + ap_ST_fsm_state992 : begin + ap_NS_fsm = ap_ST_fsm_state993; + end + ap_ST_fsm_state993 : begin + ap_NS_fsm = ap_ST_fsm_state994; + end + ap_ST_fsm_state994 : begin + ap_NS_fsm = ap_ST_fsm_state995; + end + ap_ST_fsm_state995 : begin + ap_NS_fsm = ap_ST_fsm_state996; + end + ap_ST_fsm_state996 : begin + ap_NS_fsm = ap_ST_fsm_state997; + end + ap_ST_fsm_state997 : begin + ap_NS_fsm = ap_ST_fsm_state998; + end + ap_ST_fsm_state998 : begin + ap_NS_fsm = ap_ST_fsm_state999; + end + ap_ST_fsm_state999 : begin + ap_NS_fsm = ap_ST_fsm_state1000; + end + ap_ST_fsm_state1000 : begin + ap_NS_fsm = ap_ST_fsm_state1001; + end + ap_ST_fsm_state1001 : begin + ap_NS_fsm = ap_ST_fsm_state1002; + end + ap_ST_fsm_state1002 : begin + ap_NS_fsm = ap_ST_fsm_state1003; + end + ap_ST_fsm_state1003 : begin + ap_NS_fsm = ap_ST_fsm_state1004; + end + ap_ST_fsm_state1004 : begin + ap_NS_fsm = ap_ST_fsm_state1005; + end + ap_ST_fsm_state1005 : begin + ap_NS_fsm = ap_ST_fsm_state1006; + end + ap_ST_fsm_state1006 : begin + ap_NS_fsm = ap_ST_fsm_state1007; + end + ap_ST_fsm_state1007 : begin + ap_NS_fsm = ap_ST_fsm_state1008; + end + ap_ST_fsm_state1008 : begin + ap_NS_fsm = ap_ST_fsm_state1009; + end + ap_ST_fsm_state1009 : begin + ap_NS_fsm = ap_ST_fsm_state1010; + end + ap_ST_fsm_state1010 : begin + ap_NS_fsm = ap_ST_fsm_state1011; + end + ap_ST_fsm_state1011 : begin + ap_NS_fsm = ap_ST_fsm_state1012; + end + ap_ST_fsm_state1012 : begin + ap_NS_fsm = ap_ST_fsm_state1013; + end + ap_ST_fsm_state1013 : begin + ap_NS_fsm = ap_ST_fsm_state1014; + end + ap_ST_fsm_state1014 : begin + ap_NS_fsm = ap_ST_fsm_state1015; + end + ap_ST_fsm_state1015 : begin + ap_NS_fsm = ap_ST_fsm_state1016; + end + ap_ST_fsm_state1016 : begin + ap_NS_fsm = ap_ST_fsm_state1017; + end + ap_ST_fsm_state1017 : begin + ap_NS_fsm = ap_ST_fsm_state1018; + end + ap_ST_fsm_state1018 : begin + ap_NS_fsm = ap_ST_fsm_state1019; + end + ap_ST_fsm_state1019 : begin + ap_NS_fsm = ap_ST_fsm_state1020; + end + ap_ST_fsm_state1020 : begin + ap_NS_fsm = ap_ST_fsm_state1021; + end + ap_ST_fsm_state1021 : begin + ap_NS_fsm = ap_ST_fsm_state1022; + end + ap_ST_fsm_state1022 : begin + ap_NS_fsm = ap_ST_fsm_state1023; + end + ap_ST_fsm_state1023 : begin + ap_NS_fsm = ap_ST_fsm_state1024; + end + ap_ST_fsm_state1024 : begin + ap_NS_fsm = ap_ST_fsm_state1025; + end + ap_ST_fsm_state1025 : begin + ap_NS_fsm = ap_ST_fsm_state1026; + end + ap_ST_fsm_state1026 : begin + ap_NS_fsm = ap_ST_fsm_state1027; + end + ap_ST_fsm_state1027 : begin + ap_NS_fsm = ap_ST_fsm_state1028; + end + ap_ST_fsm_state1028 : begin + ap_NS_fsm = ap_ST_fsm_state1029; + end + ap_ST_fsm_state1029 : begin + ap_NS_fsm = ap_ST_fsm_state1030; + end + ap_ST_fsm_state1030 : begin + ap_NS_fsm = ap_ST_fsm_state918; + end + ap_ST_fsm_state1031 : begin + ap_NS_fsm = ap_ST_fsm_state1032; + end + ap_ST_fsm_state1032 : begin + ap_NS_fsm = ap_ST_fsm_state1033; + end + ap_ST_fsm_state1033 : begin + ap_NS_fsm = ap_ST_fsm_state1034; + end + ap_ST_fsm_state1034 : begin + ap_NS_fsm = ap_ST_fsm_state1035; + end + ap_ST_fsm_state1035 : begin + ap_NS_fsm = ap_ST_fsm_state1036; + end + ap_ST_fsm_state1036 : begin + ap_NS_fsm = ap_ST_fsm_state1037; + end + ap_ST_fsm_state1037 : begin + ap_NS_fsm = ap_ST_fsm_state1038; + end + ap_ST_fsm_state1038 : begin + ap_NS_fsm = ap_ST_fsm_state1039; + end + ap_ST_fsm_state1039 : begin + ap_NS_fsm = ap_ST_fsm_state1040; + end + ap_ST_fsm_state1040 : begin + ap_NS_fsm = ap_ST_fsm_state1041; + end + ap_ST_fsm_state1041 : begin + ap_NS_fsm = ap_ST_fsm_state1042; + end + ap_ST_fsm_state1042 : begin + ap_NS_fsm = ap_ST_fsm_state1043; + end + ap_ST_fsm_state1043 : begin + ap_NS_fsm = ap_ST_fsm_state1044; + end + ap_ST_fsm_state1044 : begin + ap_NS_fsm = ap_ST_fsm_state1045; + end + ap_ST_fsm_state1045 : begin + ap_NS_fsm = ap_ST_fsm_state1046; + end + ap_ST_fsm_state1046 : begin + ap_NS_fsm = ap_ST_fsm_state1047; + end + ap_ST_fsm_state1047 : begin + ap_NS_fsm = ap_ST_fsm_state1048; + end + ap_ST_fsm_state1048 : begin + ap_NS_fsm = ap_ST_fsm_state1049; + end + ap_ST_fsm_state1049 : begin + ap_NS_fsm = ap_ST_fsm_state1050; + end + ap_ST_fsm_state1050 : begin + ap_NS_fsm = ap_ST_fsm_state1051; + end + ap_ST_fsm_state1051 : begin + ap_NS_fsm = ap_ST_fsm_state1052; + end + ap_ST_fsm_state1052 : begin + ap_NS_fsm = ap_ST_fsm_state1053; + end + ap_ST_fsm_state1053 : begin + ap_NS_fsm = ap_ST_fsm_state1054; + end + ap_ST_fsm_state1054 : begin + ap_NS_fsm = ap_ST_fsm_state1055; + end + ap_ST_fsm_state1055 : begin + ap_NS_fsm = ap_ST_fsm_state1056; + end + ap_ST_fsm_state1056 : begin + ap_NS_fsm = ap_ST_fsm_state1057; + end + ap_ST_fsm_state1057 : begin + ap_NS_fsm = ap_ST_fsm_state1058; + end + ap_ST_fsm_state1058 : begin + ap_NS_fsm = ap_ST_fsm_state1059; + end + ap_ST_fsm_state1059 : begin + ap_NS_fsm = ap_ST_fsm_state1060; + end + ap_ST_fsm_state1060 : begin + ap_NS_fsm = ap_ST_fsm_state1061; + end + ap_ST_fsm_state1061 : begin + ap_NS_fsm = ap_ST_fsm_state1062; + end + ap_ST_fsm_state1062 : begin + ap_NS_fsm = ap_ST_fsm_state1063; + end + ap_ST_fsm_state1063 : begin + ap_NS_fsm = ap_ST_fsm_state1064; + end + ap_ST_fsm_state1064 : begin + ap_NS_fsm = ap_ST_fsm_state1065; + end + ap_ST_fsm_state1065 : begin + ap_NS_fsm = ap_ST_fsm_state1066; + end + ap_ST_fsm_state1066 : begin + ap_NS_fsm = ap_ST_fsm_state1030; + end + ap_ST_fsm_state1067 : begin + ap_NS_fsm = ap_ST_fsm_state1068; + end + ap_ST_fsm_state1068 : begin + if (((or_ln223_42_fu_108214_p2 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1068 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1069; + end else begin + ap_NS_fsm = ap_ST_fsm_state1106; + end + end + ap_ST_fsm_state1069 : begin + ap_NS_fsm = ap_ST_fsm_state1070; + end + ap_ST_fsm_state1070 : begin + ap_NS_fsm = ap_ST_fsm_state1071; + end + ap_ST_fsm_state1071 : begin + ap_NS_fsm = ap_ST_fsm_state1072; + end + ap_ST_fsm_state1072 : begin + ap_NS_fsm = ap_ST_fsm_state1073; + end + ap_ST_fsm_state1073 : begin + ap_NS_fsm = ap_ST_fsm_state1074; + end + ap_ST_fsm_state1074 : begin + ap_NS_fsm = ap_ST_fsm_state1075; + end + ap_ST_fsm_state1075 : begin + ap_NS_fsm = ap_ST_fsm_state1076; + end + ap_ST_fsm_state1076 : begin + ap_NS_fsm = ap_ST_fsm_state1077; + end + ap_ST_fsm_state1077 : begin + ap_NS_fsm = ap_ST_fsm_state1078; + end + ap_ST_fsm_state1078 : begin + ap_NS_fsm = ap_ST_fsm_state1079; + end + ap_ST_fsm_state1079 : begin + ap_NS_fsm = ap_ST_fsm_state1080; + end + ap_ST_fsm_state1080 : begin + ap_NS_fsm = ap_ST_fsm_state1081; + end + ap_ST_fsm_state1081 : begin + ap_NS_fsm = ap_ST_fsm_state1082; + end + ap_ST_fsm_state1082 : begin + ap_NS_fsm = ap_ST_fsm_state1083; + end + ap_ST_fsm_state1083 : begin + ap_NS_fsm = ap_ST_fsm_state1084; + end + ap_ST_fsm_state1084 : begin + ap_NS_fsm = ap_ST_fsm_state1085; + end + ap_ST_fsm_state1085 : begin + ap_NS_fsm = ap_ST_fsm_state1086; + end + ap_ST_fsm_state1086 : begin + ap_NS_fsm = ap_ST_fsm_state1087; + end + ap_ST_fsm_state1087 : begin + ap_NS_fsm = ap_ST_fsm_state1088; + end + ap_ST_fsm_state1088 : begin + ap_NS_fsm = ap_ST_fsm_state1089; + end + ap_ST_fsm_state1089 : begin + ap_NS_fsm = ap_ST_fsm_state1090; + end + ap_ST_fsm_state1090 : begin + ap_NS_fsm = ap_ST_fsm_state1091; + end + ap_ST_fsm_state1091 : begin + ap_NS_fsm = ap_ST_fsm_state1092; + end + ap_ST_fsm_state1092 : begin + ap_NS_fsm = ap_ST_fsm_state1093; + end + ap_ST_fsm_state1093 : begin + ap_NS_fsm = ap_ST_fsm_state1094; + end + ap_ST_fsm_state1094 : begin + ap_NS_fsm = ap_ST_fsm_state1095; + end + ap_ST_fsm_state1095 : begin + ap_NS_fsm = ap_ST_fsm_state1096; + end + ap_ST_fsm_state1096 : begin + ap_NS_fsm = ap_ST_fsm_state1097; + end + ap_ST_fsm_state1097 : begin + ap_NS_fsm = ap_ST_fsm_state1098; + end + ap_ST_fsm_state1098 : begin + ap_NS_fsm = ap_ST_fsm_state1099; + end + ap_ST_fsm_state1099 : begin + ap_NS_fsm = ap_ST_fsm_state1100; + end + ap_ST_fsm_state1100 : begin + ap_NS_fsm = ap_ST_fsm_state1101; + end + ap_ST_fsm_state1101 : begin + ap_NS_fsm = ap_ST_fsm_state1102; + end + ap_ST_fsm_state1102 : begin + ap_NS_fsm = ap_ST_fsm_state1103; + end + ap_ST_fsm_state1103 : begin + ap_NS_fsm = ap_ST_fsm_state1104; + end + ap_ST_fsm_state1104 : begin + ap_NS_fsm = ap_ST_fsm_state1105; + end + ap_ST_fsm_state1105 : begin + if (((icmp_ln208_14_fu_108425_p2 == 1'd1) & (ap_ST_fsm_state1105 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state916; + end else if (((or_ln223_46_fu_108503_p2 == 1'd0) & (icmp_ln208_14_fu_108425_p2 == 1'd0) & (or_ln223_35_reg_137991 == 1'd0) & (ap_ST_fsm_state1105 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1142; + end else begin + ap_NS_fsm = ap_ST_fsm_state1179; + end + end + ap_ST_fsm_state1106 : begin + ap_NS_fsm = ap_ST_fsm_state1107; + end + ap_ST_fsm_state1107 : begin + ap_NS_fsm = ap_ST_fsm_state1108; + end + ap_ST_fsm_state1108 : begin + ap_NS_fsm = ap_ST_fsm_state1109; + end + ap_ST_fsm_state1109 : begin + ap_NS_fsm = ap_ST_fsm_state1110; + end + ap_ST_fsm_state1110 : begin + ap_NS_fsm = ap_ST_fsm_state1111; + end + ap_ST_fsm_state1111 : begin + ap_NS_fsm = ap_ST_fsm_state1112; + end + ap_ST_fsm_state1112 : begin + ap_NS_fsm = ap_ST_fsm_state1113; + end + ap_ST_fsm_state1113 : begin + ap_NS_fsm = ap_ST_fsm_state1114; + end + ap_ST_fsm_state1114 : begin + ap_NS_fsm = ap_ST_fsm_state1115; + end + ap_ST_fsm_state1115 : begin + ap_NS_fsm = ap_ST_fsm_state1116; + end + ap_ST_fsm_state1116 : begin + ap_NS_fsm = ap_ST_fsm_state1117; + end + ap_ST_fsm_state1117 : begin + ap_NS_fsm = ap_ST_fsm_state1118; + end + ap_ST_fsm_state1118 : begin + ap_NS_fsm = ap_ST_fsm_state1119; + end + ap_ST_fsm_state1119 : begin + ap_NS_fsm = ap_ST_fsm_state1120; + end + ap_ST_fsm_state1120 : begin + ap_NS_fsm = ap_ST_fsm_state1121; + end + ap_ST_fsm_state1121 : begin + ap_NS_fsm = ap_ST_fsm_state1122; + end + ap_ST_fsm_state1122 : begin + ap_NS_fsm = ap_ST_fsm_state1123; + end + ap_ST_fsm_state1123 : begin + ap_NS_fsm = ap_ST_fsm_state1124; + end + ap_ST_fsm_state1124 : begin + ap_NS_fsm = ap_ST_fsm_state1125; + end + ap_ST_fsm_state1125 : begin + ap_NS_fsm = ap_ST_fsm_state1126; + end + ap_ST_fsm_state1126 : begin + ap_NS_fsm = ap_ST_fsm_state1127; + end + ap_ST_fsm_state1127 : begin + ap_NS_fsm = ap_ST_fsm_state1128; + end + ap_ST_fsm_state1128 : begin + ap_NS_fsm = ap_ST_fsm_state1129; + end + ap_ST_fsm_state1129 : begin + ap_NS_fsm = ap_ST_fsm_state1130; + end + ap_ST_fsm_state1130 : begin + ap_NS_fsm = ap_ST_fsm_state1131; + end + ap_ST_fsm_state1131 : begin + ap_NS_fsm = ap_ST_fsm_state1132; + end + ap_ST_fsm_state1132 : begin + ap_NS_fsm = ap_ST_fsm_state1133; + end + ap_ST_fsm_state1133 : begin + ap_NS_fsm = ap_ST_fsm_state1134; + end + ap_ST_fsm_state1134 : begin + ap_NS_fsm = ap_ST_fsm_state1135; + end + ap_ST_fsm_state1135 : begin + ap_NS_fsm = ap_ST_fsm_state1136; + end + ap_ST_fsm_state1136 : begin + ap_NS_fsm = ap_ST_fsm_state1137; + end + ap_ST_fsm_state1137 : begin + ap_NS_fsm = ap_ST_fsm_state1138; + end + ap_ST_fsm_state1138 : begin + ap_NS_fsm = ap_ST_fsm_state1139; + end + ap_ST_fsm_state1139 : begin + ap_NS_fsm = ap_ST_fsm_state1140; + end + ap_ST_fsm_state1140 : begin + ap_NS_fsm = ap_ST_fsm_state1141; + end + ap_ST_fsm_state1141 : begin + ap_NS_fsm = ap_ST_fsm_state1105; + end + ap_ST_fsm_state1142 : begin + ap_NS_fsm = ap_ST_fsm_state1143; + end + ap_ST_fsm_state1143 : begin + ap_NS_fsm = ap_ST_fsm_state1144; + end + ap_ST_fsm_state1144 : begin + ap_NS_fsm = ap_ST_fsm_state1145; + end + ap_ST_fsm_state1145 : begin + ap_NS_fsm = ap_ST_fsm_state1146; + end + ap_ST_fsm_state1146 : begin + ap_NS_fsm = ap_ST_fsm_state1147; + end + ap_ST_fsm_state1147 : begin + ap_NS_fsm = ap_ST_fsm_state1148; + end + ap_ST_fsm_state1148 : begin + ap_NS_fsm = ap_ST_fsm_state1149; + end + ap_ST_fsm_state1149 : begin + ap_NS_fsm = ap_ST_fsm_state1150; + end + ap_ST_fsm_state1150 : begin + ap_NS_fsm = ap_ST_fsm_state1151; + end + ap_ST_fsm_state1151 : begin + ap_NS_fsm = ap_ST_fsm_state1152; + end + ap_ST_fsm_state1152 : begin + ap_NS_fsm = ap_ST_fsm_state1153; + end + ap_ST_fsm_state1153 : begin + ap_NS_fsm = ap_ST_fsm_state1154; + end + ap_ST_fsm_state1154 : begin + ap_NS_fsm = ap_ST_fsm_state1155; + end + ap_ST_fsm_state1155 : begin + ap_NS_fsm = ap_ST_fsm_state1156; + end + ap_ST_fsm_state1156 : begin + ap_NS_fsm = ap_ST_fsm_state1157; + end + ap_ST_fsm_state1157 : begin + ap_NS_fsm = ap_ST_fsm_state1158; + end + ap_ST_fsm_state1158 : begin + ap_NS_fsm = ap_ST_fsm_state1159; + end + ap_ST_fsm_state1159 : begin + ap_NS_fsm = ap_ST_fsm_state1160; + end + ap_ST_fsm_state1160 : begin + ap_NS_fsm = ap_ST_fsm_state1161; + end + ap_ST_fsm_state1161 : begin + ap_NS_fsm = ap_ST_fsm_state1162; + end + ap_ST_fsm_state1162 : begin + ap_NS_fsm = ap_ST_fsm_state1163; + end + ap_ST_fsm_state1163 : begin + ap_NS_fsm = ap_ST_fsm_state1164; + end + ap_ST_fsm_state1164 : begin + ap_NS_fsm = ap_ST_fsm_state1165; + end + ap_ST_fsm_state1165 : begin + ap_NS_fsm = ap_ST_fsm_state1166; + end + ap_ST_fsm_state1166 : begin + ap_NS_fsm = ap_ST_fsm_state1167; + end + ap_ST_fsm_state1167 : begin + ap_NS_fsm = ap_ST_fsm_state1168; + end + ap_ST_fsm_state1168 : begin + ap_NS_fsm = ap_ST_fsm_state1169; + end + ap_ST_fsm_state1169 : begin + ap_NS_fsm = ap_ST_fsm_state1170; + end + ap_ST_fsm_state1170 : begin + ap_NS_fsm = ap_ST_fsm_state1171; + end + ap_ST_fsm_state1171 : begin + ap_NS_fsm = ap_ST_fsm_state1172; + end + ap_ST_fsm_state1172 : begin + ap_NS_fsm = ap_ST_fsm_state1173; + end + ap_ST_fsm_state1173 : begin + ap_NS_fsm = ap_ST_fsm_state1174; + end + ap_ST_fsm_state1174 : begin + ap_NS_fsm = ap_ST_fsm_state1175; + end + ap_ST_fsm_state1175 : begin + ap_NS_fsm = ap_ST_fsm_state1176; + end + ap_ST_fsm_state1176 : begin + ap_NS_fsm = ap_ST_fsm_state1177; + end + ap_ST_fsm_state1177 : begin + ap_NS_fsm = ap_ST_fsm_state1178; + end + ap_ST_fsm_state1178 : begin + ap_NS_fsm = ap_ST_fsm_state1068; + end + ap_ST_fsm_state1179 : begin + ap_NS_fsm = ap_ST_fsm_state1180; + end + ap_ST_fsm_state1180 : begin + ap_NS_fsm = ap_ST_fsm_state1181; + end + ap_ST_fsm_state1181 : begin + ap_NS_fsm = ap_ST_fsm_state1182; + end + ap_ST_fsm_state1182 : begin + ap_NS_fsm = ap_ST_fsm_state1183; + end + ap_ST_fsm_state1183 : begin + ap_NS_fsm = ap_ST_fsm_state1184; + end + ap_ST_fsm_state1184 : begin + ap_NS_fsm = ap_ST_fsm_state1185; + end + ap_ST_fsm_state1185 : begin + ap_NS_fsm = ap_ST_fsm_state1186; + end + ap_ST_fsm_state1186 : begin + ap_NS_fsm = ap_ST_fsm_state1187; + end + ap_ST_fsm_state1187 : begin + ap_NS_fsm = ap_ST_fsm_state1188; + end + ap_ST_fsm_state1188 : begin + ap_NS_fsm = ap_ST_fsm_state1189; + end + ap_ST_fsm_state1189 : begin + ap_NS_fsm = ap_ST_fsm_state1190; + end + ap_ST_fsm_state1190 : begin + ap_NS_fsm = ap_ST_fsm_state1191; + end + ap_ST_fsm_state1191 : begin + ap_NS_fsm = ap_ST_fsm_state1192; + end + ap_ST_fsm_state1192 : begin + ap_NS_fsm = ap_ST_fsm_state1193; + end + ap_ST_fsm_state1193 : begin + ap_NS_fsm = ap_ST_fsm_state1194; + end + ap_ST_fsm_state1194 : begin + ap_NS_fsm = ap_ST_fsm_state1195; + end + ap_ST_fsm_state1195 : begin + ap_NS_fsm = ap_ST_fsm_state1196; + end + ap_ST_fsm_state1196 : begin + ap_NS_fsm = ap_ST_fsm_state1197; + end + ap_ST_fsm_state1197 : begin + ap_NS_fsm = ap_ST_fsm_state1198; + end + ap_ST_fsm_state1198 : begin + ap_NS_fsm = ap_ST_fsm_state1199; + end + ap_ST_fsm_state1199 : begin + ap_NS_fsm = ap_ST_fsm_state1200; + end + ap_ST_fsm_state1200 : begin + ap_NS_fsm = ap_ST_fsm_state1201; + end + ap_ST_fsm_state1201 : begin + ap_NS_fsm = ap_ST_fsm_state1202; + end + ap_ST_fsm_state1202 : begin + ap_NS_fsm = ap_ST_fsm_state1203; + end + ap_ST_fsm_state1203 : begin + ap_NS_fsm = ap_ST_fsm_state1204; + end + ap_ST_fsm_state1204 : begin + ap_NS_fsm = ap_ST_fsm_state1205; + end + ap_ST_fsm_state1205 : begin + ap_NS_fsm = ap_ST_fsm_state1206; + end + ap_ST_fsm_state1206 : begin + ap_NS_fsm = ap_ST_fsm_state1207; + end + ap_ST_fsm_state1207 : begin + ap_NS_fsm = ap_ST_fsm_state1208; + end + ap_ST_fsm_state1208 : begin + ap_NS_fsm = ap_ST_fsm_state1209; + end + ap_ST_fsm_state1209 : begin + ap_NS_fsm = ap_ST_fsm_state1210; + end + ap_ST_fsm_state1210 : begin + ap_NS_fsm = ap_ST_fsm_state1211; + end + ap_ST_fsm_state1211 : begin + ap_NS_fsm = ap_ST_fsm_state1212; + end + ap_ST_fsm_state1212 : begin + ap_NS_fsm = ap_ST_fsm_state1213; + end + ap_ST_fsm_state1213 : begin + ap_NS_fsm = ap_ST_fsm_state1214; + end + ap_ST_fsm_state1214 : begin + ap_NS_fsm = ap_ST_fsm_state1178; + end + ap_ST_fsm_state1215 : begin + if (((icmp_ln201_1_fu_108832_p2 == 1'd1) & (ap_ST_fsm_state1215 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1216; + end + end + ap_ST_fsm_state1216 : begin + if (((icmp_ln203_1_fu_108860_p2 == 1'd1) & (ap_ST_fsm_state1216 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1821; + end else begin + ap_NS_fsm = ap_ST_fsm_state1217; + end + end + ap_ST_fsm_state1217 : begin + if (((icmp_ln204_1_fu_108914_p2 == 1'd1) & (ap_ST_fsm_state1217 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1216; + end else begin + ap_NS_fsm = ap_ST_fsm_state1218; + end + end + ap_ST_fsm_state1218 : begin + ap_NS_fsm = ap_ST_fsm_state1219; + end + ap_ST_fsm_state1219 : begin + ap_NS_fsm = ap_ST_fsm_state1220; + end + ap_ST_fsm_state1220 : begin + if (((or_ln223_5_fu_109171_p2 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1220 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1221; + end else begin + ap_NS_fsm = ap_ST_fsm_state1259; + end + end + ap_ST_fsm_state1221 : begin + ap_NS_fsm = ap_ST_fsm_state1222; + end + ap_ST_fsm_state1222 : begin + ap_NS_fsm = ap_ST_fsm_state1223; + end + ap_ST_fsm_state1223 : begin + ap_NS_fsm = ap_ST_fsm_state1224; + end + ap_ST_fsm_state1224 : begin + ap_NS_fsm = ap_ST_fsm_state1225; + end + ap_ST_fsm_state1225 : begin + ap_NS_fsm = ap_ST_fsm_state1226; + end + ap_ST_fsm_state1226 : begin + ap_NS_fsm = ap_ST_fsm_state1227; + end + ap_ST_fsm_state1227 : begin + ap_NS_fsm = ap_ST_fsm_state1228; + end + ap_ST_fsm_state1228 : begin + ap_NS_fsm = ap_ST_fsm_state1229; + end + ap_ST_fsm_state1229 : begin + ap_NS_fsm = ap_ST_fsm_state1230; + end + ap_ST_fsm_state1230 : begin + ap_NS_fsm = ap_ST_fsm_state1231; + end + ap_ST_fsm_state1231 : begin + ap_NS_fsm = ap_ST_fsm_state1232; + end + ap_ST_fsm_state1232 : begin + ap_NS_fsm = ap_ST_fsm_state1233; + end + ap_ST_fsm_state1233 : begin + ap_NS_fsm = ap_ST_fsm_state1234; + end + ap_ST_fsm_state1234 : begin + ap_NS_fsm = ap_ST_fsm_state1235; + end + ap_ST_fsm_state1235 : begin + ap_NS_fsm = ap_ST_fsm_state1236; + end + ap_ST_fsm_state1236 : begin + ap_NS_fsm = ap_ST_fsm_state1237; + end + ap_ST_fsm_state1237 : begin + ap_NS_fsm = ap_ST_fsm_state1238; + end + ap_ST_fsm_state1238 : begin + ap_NS_fsm = ap_ST_fsm_state1239; + end + ap_ST_fsm_state1239 : begin + ap_NS_fsm = ap_ST_fsm_state1240; + end + ap_ST_fsm_state1240 : begin + ap_NS_fsm = ap_ST_fsm_state1241; + end + ap_ST_fsm_state1241 : begin + ap_NS_fsm = ap_ST_fsm_state1242; + end + ap_ST_fsm_state1242 : begin + ap_NS_fsm = ap_ST_fsm_state1243; + end + ap_ST_fsm_state1243 : begin + ap_NS_fsm = ap_ST_fsm_state1244; + end + ap_ST_fsm_state1244 : begin + ap_NS_fsm = ap_ST_fsm_state1245; + end + ap_ST_fsm_state1245 : begin + ap_NS_fsm = ap_ST_fsm_state1246; + end + ap_ST_fsm_state1246 : begin + ap_NS_fsm = ap_ST_fsm_state1247; + end + ap_ST_fsm_state1247 : begin + ap_NS_fsm = ap_ST_fsm_state1248; + end + ap_ST_fsm_state1248 : begin + ap_NS_fsm = ap_ST_fsm_state1249; + end + ap_ST_fsm_state1249 : begin + ap_NS_fsm = ap_ST_fsm_state1250; + end + ap_ST_fsm_state1250 : begin + ap_NS_fsm = ap_ST_fsm_state1251; + end + ap_ST_fsm_state1251 : begin + ap_NS_fsm = ap_ST_fsm_state1252; + end + ap_ST_fsm_state1252 : begin + ap_NS_fsm = ap_ST_fsm_state1253; + end + ap_ST_fsm_state1253 : begin + ap_NS_fsm = ap_ST_fsm_state1254; + end + ap_ST_fsm_state1254 : begin + ap_NS_fsm = ap_ST_fsm_state1255; + end + ap_ST_fsm_state1255 : begin + ap_NS_fsm = ap_ST_fsm_state1256; + end + ap_ST_fsm_state1256 : begin + ap_NS_fsm = ap_ST_fsm_state1257; + end + ap_ST_fsm_state1257 : begin + ap_NS_fsm = ap_ST_fsm_state1258; + end + ap_ST_fsm_state1258 : begin + if (((icmp_ln206_1_fu_109593_p2 == 1'd1) & (icmp_ln208_1_fu_109384_p2 == 1'd1) & (ap_ST_fsm_state1258 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1522; + end else if (((icmp_ln208_1_fu_109384_p2 == 1'd1) & (icmp_ln206_1_fu_109593_p2 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1370; + end else if (((or_ln223_12_fu_109462_p2 == 1'd0) & (icmp_ln208_1_fu_109384_p2 == 1'd0) & (or_ln223_1_reg_138942 == 1'd0) & (ap_ST_fsm_state1258 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1295; + end else begin + ap_NS_fsm = ap_ST_fsm_state1334; + end + end + ap_ST_fsm_state1259 : begin + ap_NS_fsm = ap_ST_fsm_state1260; + end + ap_ST_fsm_state1260 : begin + ap_NS_fsm = ap_ST_fsm_state1261; + end + ap_ST_fsm_state1261 : begin + ap_NS_fsm = ap_ST_fsm_state1262; + end + ap_ST_fsm_state1262 : begin + ap_NS_fsm = ap_ST_fsm_state1263; + end + ap_ST_fsm_state1263 : begin + ap_NS_fsm = ap_ST_fsm_state1264; + end + ap_ST_fsm_state1264 : begin + ap_NS_fsm = ap_ST_fsm_state1265; + end + ap_ST_fsm_state1265 : begin + ap_NS_fsm = ap_ST_fsm_state1266; + end + ap_ST_fsm_state1266 : begin + ap_NS_fsm = ap_ST_fsm_state1267; + end + ap_ST_fsm_state1267 : begin + ap_NS_fsm = ap_ST_fsm_state1268; + end + ap_ST_fsm_state1268 : begin + ap_NS_fsm = ap_ST_fsm_state1269; + end + ap_ST_fsm_state1269 : begin + ap_NS_fsm = ap_ST_fsm_state1270; + end + ap_ST_fsm_state1270 : begin + ap_NS_fsm = ap_ST_fsm_state1271; + end + ap_ST_fsm_state1271 : begin + ap_NS_fsm = ap_ST_fsm_state1272; + end + ap_ST_fsm_state1272 : begin + ap_NS_fsm = ap_ST_fsm_state1273; + end + ap_ST_fsm_state1273 : begin + ap_NS_fsm = ap_ST_fsm_state1274; + end + ap_ST_fsm_state1274 : begin + ap_NS_fsm = ap_ST_fsm_state1275; + end + ap_ST_fsm_state1275 : begin + ap_NS_fsm = ap_ST_fsm_state1276; + end + ap_ST_fsm_state1276 : begin + ap_NS_fsm = ap_ST_fsm_state1277; + end + ap_ST_fsm_state1277 : begin + ap_NS_fsm = ap_ST_fsm_state1278; + end + ap_ST_fsm_state1278 : begin + ap_NS_fsm = ap_ST_fsm_state1279; + end + ap_ST_fsm_state1279 : begin + ap_NS_fsm = ap_ST_fsm_state1280; + end + ap_ST_fsm_state1280 : begin + ap_NS_fsm = ap_ST_fsm_state1281; + end + ap_ST_fsm_state1281 : begin + ap_NS_fsm = ap_ST_fsm_state1282; + end + ap_ST_fsm_state1282 : begin + ap_NS_fsm = ap_ST_fsm_state1283; + end + ap_ST_fsm_state1283 : begin + ap_NS_fsm = ap_ST_fsm_state1284; + end + ap_ST_fsm_state1284 : begin + ap_NS_fsm = ap_ST_fsm_state1285; + end + ap_ST_fsm_state1285 : begin + ap_NS_fsm = ap_ST_fsm_state1286; + end + ap_ST_fsm_state1286 : begin + ap_NS_fsm = ap_ST_fsm_state1287; + end + ap_ST_fsm_state1287 : begin + ap_NS_fsm = ap_ST_fsm_state1288; + end + ap_ST_fsm_state1288 : begin + ap_NS_fsm = ap_ST_fsm_state1289; + end + ap_ST_fsm_state1289 : begin + ap_NS_fsm = ap_ST_fsm_state1290; + end + ap_ST_fsm_state1290 : begin + ap_NS_fsm = ap_ST_fsm_state1291; + end + ap_ST_fsm_state1291 : begin + ap_NS_fsm = ap_ST_fsm_state1292; + end + ap_ST_fsm_state1292 : begin + ap_NS_fsm = ap_ST_fsm_state1293; + end + ap_ST_fsm_state1293 : begin + ap_NS_fsm = ap_ST_fsm_state1294; + end + ap_ST_fsm_state1294 : begin + ap_NS_fsm = ap_ST_fsm_state1258; + end + ap_ST_fsm_state1295 : begin + ap_NS_fsm = ap_ST_fsm_state1296; + end + ap_ST_fsm_state1296 : begin + ap_NS_fsm = ap_ST_fsm_state1297; + end + ap_ST_fsm_state1297 : begin + ap_NS_fsm = ap_ST_fsm_state1298; + end + ap_ST_fsm_state1298 : begin + ap_NS_fsm = ap_ST_fsm_state1299; + end + ap_ST_fsm_state1299 : begin + ap_NS_fsm = ap_ST_fsm_state1300; + end + ap_ST_fsm_state1300 : begin + ap_NS_fsm = ap_ST_fsm_state1301; + end + ap_ST_fsm_state1301 : begin + ap_NS_fsm = ap_ST_fsm_state1302; + end + ap_ST_fsm_state1302 : begin + ap_NS_fsm = ap_ST_fsm_state1303; + end + ap_ST_fsm_state1303 : begin + ap_NS_fsm = ap_ST_fsm_state1304; + end + ap_ST_fsm_state1304 : begin + ap_NS_fsm = ap_ST_fsm_state1305; + end + ap_ST_fsm_state1305 : begin + ap_NS_fsm = ap_ST_fsm_state1306; + end + ap_ST_fsm_state1306 : begin + ap_NS_fsm = ap_ST_fsm_state1307; + end + ap_ST_fsm_state1307 : begin + ap_NS_fsm = ap_ST_fsm_state1308; + end + ap_ST_fsm_state1308 : begin + ap_NS_fsm = ap_ST_fsm_state1309; + end + ap_ST_fsm_state1309 : begin + ap_NS_fsm = ap_ST_fsm_state1310; + end + ap_ST_fsm_state1310 : begin + ap_NS_fsm = ap_ST_fsm_state1311; + end + ap_ST_fsm_state1311 : begin + ap_NS_fsm = ap_ST_fsm_state1312; + end + ap_ST_fsm_state1312 : begin + ap_NS_fsm = ap_ST_fsm_state1313; + end + ap_ST_fsm_state1313 : begin + ap_NS_fsm = ap_ST_fsm_state1314; + end + ap_ST_fsm_state1314 : begin + ap_NS_fsm = ap_ST_fsm_state1315; + end + ap_ST_fsm_state1315 : begin + ap_NS_fsm = ap_ST_fsm_state1316; + end + ap_ST_fsm_state1316 : begin + ap_NS_fsm = ap_ST_fsm_state1317; + end + ap_ST_fsm_state1317 : begin + ap_NS_fsm = ap_ST_fsm_state1318; + end + ap_ST_fsm_state1318 : begin + ap_NS_fsm = ap_ST_fsm_state1319; + end + ap_ST_fsm_state1319 : begin + ap_NS_fsm = ap_ST_fsm_state1320; + end + ap_ST_fsm_state1320 : begin + ap_NS_fsm = ap_ST_fsm_state1321; + end + ap_ST_fsm_state1321 : begin + ap_NS_fsm = ap_ST_fsm_state1322; + end + ap_ST_fsm_state1322 : begin + ap_NS_fsm = ap_ST_fsm_state1323; + end + ap_ST_fsm_state1323 : begin + ap_NS_fsm = ap_ST_fsm_state1324; + end + ap_ST_fsm_state1324 : begin + ap_NS_fsm = ap_ST_fsm_state1325; + end + ap_ST_fsm_state1325 : begin + ap_NS_fsm = ap_ST_fsm_state1326; + end + ap_ST_fsm_state1326 : begin + ap_NS_fsm = ap_ST_fsm_state1327; + end + ap_ST_fsm_state1327 : begin + ap_NS_fsm = ap_ST_fsm_state1328; + end + ap_ST_fsm_state1328 : begin + ap_NS_fsm = ap_ST_fsm_state1329; + end + ap_ST_fsm_state1329 : begin + ap_NS_fsm = ap_ST_fsm_state1330; + end + ap_ST_fsm_state1330 : begin + ap_NS_fsm = ap_ST_fsm_state1331; + end + ap_ST_fsm_state1331 : begin + ap_NS_fsm = ap_ST_fsm_state1332; + end + ap_ST_fsm_state1332 : begin + ap_NS_fsm = ap_ST_fsm_state1333; + end + ap_ST_fsm_state1333 : begin + ap_NS_fsm = ap_ST_fsm_state1220; + end + ap_ST_fsm_state1334 : begin + ap_NS_fsm = ap_ST_fsm_state1335; + end + ap_ST_fsm_state1335 : begin + ap_NS_fsm = ap_ST_fsm_state1336; + end + ap_ST_fsm_state1336 : begin + ap_NS_fsm = ap_ST_fsm_state1337; + end + ap_ST_fsm_state1337 : begin + ap_NS_fsm = ap_ST_fsm_state1338; + end + ap_ST_fsm_state1338 : begin + ap_NS_fsm = ap_ST_fsm_state1339; + end + ap_ST_fsm_state1339 : begin + ap_NS_fsm = ap_ST_fsm_state1340; + end + ap_ST_fsm_state1340 : begin + ap_NS_fsm = ap_ST_fsm_state1341; + end + ap_ST_fsm_state1341 : begin + ap_NS_fsm = ap_ST_fsm_state1342; + end + ap_ST_fsm_state1342 : begin + ap_NS_fsm = ap_ST_fsm_state1343; + end + ap_ST_fsm_state1343 : begin + ap_NS_fsm = ap_ST_fsm_state1344; + end + ap_ST_fsm_state1344 : begin + ap_NS_fsm = ap_ST_fsm_state1345; + end + ap_ST_fsm_state1345 : begin + ap_NS_fsm = ap_ST_fsm_state1346; + end + ap_ST_fsm_state1346 : begin + ap_NS_fsm = ap_ST_fsm_state1347; + end + ap_ST_fsm_state1347 : begin + ap_NS_fsm = ap_ST_fsm_state1348; + end + ap_ST_fsm_state1348 : begin + ap_NS_fsm = ap_ST_fsm_state1349; + end + ap_ST_fsm_state1349 : begin + ap_NS_fsm = ap_ST_fsm_state1350; + end + ap_ST_fsm_state1350 : begin + ap_NS_fsm = ap_ST_fsm_state1351; + end + ap_ST_fsm_state1351 : begin + ap_NS_fsm = ap_ST_fsm_state1352; + end + ap_ST_fsm_state1352 : begin + ap_NS_fsm = ap_ST_fsm_state1353; + end + ap_ST_fsm_state1353 : begin + ap_NS_fsm = ap_ST_fsm_state1354; + end + ap_ST_fsm_state1354 : begin + ap_NS_fsm = ap_ST_fsm_state1355; + end + ap_ST_fsm_state1355 : begin + ap_NS_fsm = ap_ST_fsm_state1356; + end + ap_ST_fsm_state1356 : begin + ap_NS_fsm = ap_ST_fsm_state1357; + end + ap_ST_fsm_state1357 : begin + ap_NS_fsm = ap_ST_fsm_state1358; + end + ap_ST_fsm_state1358 : begin + ap_NS_fsm = ap_ST_fsm_state1359; + end + ap_ST_fsm_state1359 : begin + ap_NS_fsm = ap_ST_fsm_state1360; + end + ap_ST_fsm_state1360 : begin + ap_NS_fsm = ap_ST_fsm_state1361; + end + ap_ST_fsm_state1361 : begin + ap_NS_fsm = ap_ST_fsm_state1362; + end + ap_ST_fsm_state1362 : begin + ap_NS_fsm = ap_ST_fsm_state1363; + end + ap_ST_fsm_state1363 : begin + ap_NS_fsm = ap_ST_fsm_state1364; + end + ap_ST_fsm_state1364 : begin + ap_NS_fsm = ap_ST_fsm_state1365; + end + ap_ST_fsm_state1365 : begin + ap_NS_fsm = ap_ST_fsm_state1366; + end + ap_ST_fsm_state1366 : begin + ap_NS_fsm = ap_ST_fsm_state1367; + end + ap_ST_fsm_state1367 : begin + ap_NS_fsm = ap_ST_fsm_state1368; + end + ap_ST_fsm_state1368 : begin + ap_NS_fsm = ap_ST_fsm_state1369; + end + ap_ST_fsm_state1369 : begin + ap_NS_fsm = ap_ST_fsm_state1333; + end + ap_ST_fsm_state1370 : begin + ap_NS_fsm = ap_ST_fsm_state1371; + end + ap_ST_fsm_state1371 : begin + if (((or_ln223_11_reg_139731 == 1'd0) & (or_ln223_21_fu_110053_p2 == 1'd0) & (ap_ST_fsm_state1371 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1372; + end else begin + ap_NS_fsm = ap_ST_fsm_state1411; + end + end + ap_ST_fsm_state1372 : begin + ap_NS_fsm = ap_ST_fsm_state1373; + end + ap_ST_fsm_state1373 : begin + ap_NS_fsm = ap_ST_fsm_state1374; + end + ap_ST_fsm_state1374 : begin + ap_NS_fsm = ap_ST_fsm_state1375; + end + ap_ST_fsm_state1375 : begin + ap_NS_fsm = ap_ST_fsm_state1376; + end + ap_ST_fsm_state1376 : begin + ap_NS_fsm = ap_ST_fsm_state1377; + end + ap_ST_fsm_state1377 : begin + ap_NS_fsm = ap_ST_fsm_state1378; + end + ap_ST_fsm_state1378 : begin + ap_NS_fsm = ap_ST_fsm_state1379; + end + ap_ST_fsm_state1379 : begin + ap_NS_fsm = ap_ST_fsm_state1380; + end + ap_ST_fsm_state1380 : begin + ap_NS_fsm = ap_ST_fsm_state1381; + end + ap_ST_fsm_state1381 : begin + ap_NS_fsm = ap_ST_fsm_state1382; + end + ap_ST_fsm_state1382 : begin + ap_NS_fsm = ap_ST_fsm_state1383; + end + ap_ST_fsm_state1383 : begin + ap_NS_fsm = ap_ST_fsm_state1384; + end + ap_ST_fsm_state1384 : begin + ap_NS_fsm = ap_ST_fsm_state1385; + end + ap_ST_fsm_state1385 : begin + ap_NS_fsm = ap_ST_fsm_state1386; + end + ap_ST_fsm_state1386 : begin + ap_NS_fsm = ap_ST_fsm_state1387; + end + ap_ST_fsm_state1387 : begin + ap_NS_fsm = ap_ST_fsm_state1388; + end + ap_ST_fsm_state1388 : begin + ap_NS_fsm = ap_ST_fsm_state1389; + end + ap_ST_fsm_state1389 : begin + ap_NS_fsm = ap_ST_fsm_state1390; + end + ap_ST_fsm_state1390 : begin + ap_NS_fsm = ap_ST_fsm_state1391; + end + ap_ST_fsm_state1391 : begin + ap_NS_fsm = ap_ST_fsm_state1392; + end + ap_ST_fsm_state1392 : begin + ap_NS_fsm = ap_ST_fsm_state1393; + end + ap_ST_fsm_state1393 : begin + ap_NS_fsm = ap_ST_fsm_state1394; + end + ap_ST_fsm_state1394 : begin + ap_NS_fsm = ap_ST_fsm_state1395; + end + ap_ST_fsm_state1395 : begin + ap_NS_fsm = ap_ST_fsm_state1396; + end + ap_ST_fsm_state1396 : begin + ap_NS_fsm = ap_ST_fsm_state1397; + end + ap_ST_fsm_state1397 : begin + ap_NS_fsm = ap_ST_fsm_state1398; + end + ap_ST_fsm_state1398 : begin + ap_NS_fsm = ap_ST_fsm_state1399; + end + ap_ST_fsm_state1399 : begin + ap_NS_fsm = ap_ST_fsm_state1400; + end + ap_ST_fsm_state1400 : begin + ap_NS_fsm = ap_ST_fsm_state1401; + end + ap_ST_fsm_state1401 : begin + ap_NS_fsm = ap_ST_fsm_state1402; + end + ap_ST_fsm_state1402 : begin + ap_NS_fsm = ap_ST_fsm_state1403; + end + ap_ST_fsm_state1403 : begin + ap_NS_fsm = ap_ST_fsm_state1404; + end + ap_ST_fsm_state1404 : begin + ap_NS_fsm = ap_ST_fsm_state1405; + end + ap_ST_fsm_state1405 : begin + ap_NS_fsm = ap_ST_fsm_state1406; + end + ap_ST_fsm_state1406 : begin + ap_NS_fsm = ap_ST_fsm_state1407; + end + ap_ST_fsm_state1407 : begin + ap_NS_fsm = ap_ST_fsm_state1408; + end + ap_ST_fsm_state1408 : begin + ap_NS_fsm = ap_ST_fsm_state1409; + end + ap_ST_fsm_state1409 : begin + ap_NS_fsm = ap_ST_fsm_state1410; + end + ap_ST_fsm_state1410 : begin + if (((icmp_ln208_6_fu_110267_p2 == 1'd1) & (ap_ST_fsm_state1410 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1218; + end else if (((or_ln223_31_fu_110345_p2 == 1'd0) & (icmp_ln208_6_fu_110267_p2 == 1'd0) & (or_ln223_11_reg_139731 == 1'd0) & (ap_ST_fsm_state1410 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1447; + end else begin + ap_NS_fsm = ap_ST_fsm_state1486; + end + end + ap_ST_fsm_state1411 : begin + ap_NS_fsm = ap_ST_fsm_state1412; + end + ap_ST_fsm_state1412 : begin + ap_NS_fsm = ap_ST_fsm_state1413; + end + ap_ST_fsm_state1413 : begin + ap_NS_fsm = ap_ST_fsm_state1414; + end + ap_ST_fsm_state1414 : begin + ap_NS_fsm = ap_ST_fsm_state1415; + end + ap_ST_fsm_state1415 : begin + ap_NS_fsm = ap_ST_fsm_state1416; + end + ap_ST_fsm_state1416 : begin + ap_NS_fsm = ap_ST_fsm_state1417; + end + ap_ST_fsm_state1417 : begin + ap_NS_fsm = ap_ST_fsm_state1418; + end + ap_ST_fsm_state1418 : begin + ap_NS_fsm = ap_ST_fsm_state1419; + end + ap_ST_fsm_state1419 : begin + ap_NS_fsm = ap_ST_fsm_state1420; + end + ap_ST_fsm_state1420 : begin + ap_NS_fsm = ap_ST_fsm_state1421; + end + ap_ST_fsm_state1421 : begin + ap_NS_fsm = ap_ST_fsm_state1422; + end + ap_ST_fsm_state1422 : begin + ap_NS_fsm = ap_ST_fsm_state1423; + end + ap_ST_fsm_state1423 : begin + ap_NS_fsm = ap_ST_fsm_state1424; + end + ap_ST_fsm_state1424 : begin + ap_NS_fsm = ap_ST_fsm_state1425; + end + ap_ST_fsm_state1425 : begin + ap_NS_fsm = ap_ST_fsm_state1426; + end + ap_ST_fsm_state1426 : begin + ap_NS_fsm = ap_ST_fsm_state1427; + end + ap_ST_fsm_state1427 : begin + ap_NS_fsm = ap_ST_fsm_state1428; + end + ap_ST_fsm_state1428 : begin + ap_NS_fsm = ap_ST_fsm_state1429; + end + ap_ST_fsm_state1429 : begin + ap_NS_fsm = ap_ST_fsm_state1430; + end + ap_ST_fsm_state1430 : begin + ap_NS_fsm = ap_ST_fsm_state1431; + end + ap_ST_fsm_state1431 : begin + ap_NS_fsm = ap_ST_fsm_state1432; + end + ap_ST_fsm_state1432 : begin + ap_NS_fsm = ap_ST_fsm_state1433; + end + ap_ST_fsm_state1433 : begin + ap_NS_fsm = ap_ST_fsm_state1434; + end + ap_ST_fsm_state1434 : begin + ap_NS_fsm = ap_ST_fsm_state1435; + end + ap_ST_fsm_state1435 : begin + ap_NS_fsm = ap_ST_fsm_state1436; + end + ap_ST_fsm_state1436 : begin + ap_NS_fsm = ap_ST_fsm_state1437; + end + ap_ST_fsm_state1437 : begin + ap_NS_fsm = ap_ST_fsm_state1438; + end + ap_ST_fsm_state1438 : begin + ap_NS_fsm = ap_ST_fsm_state1439; + end + ap_ST_fsm_state1439 : begin + ap_NS_fsm = ap_ST_fsm_state1440; + end + ap_ST_fsm_state1440 : begin + ap_NS_fsm = ap_ST_fsm_state1441; + end + ap_ST_fsm_state1441 : begin + ap_NS_fsm = ap_ST_fsm_state1442; + end + ap_ST_fsm_state1442 : begin + ap_NS_fsm = ap_ST_fsm_state1443; + end + ap_ST_fsm_state1443 : begin + ap_NS_fsm = ap_ST_fsm_state1444; + end + ap_ST_fsm_state1444 : begin + ap_NS_fsm = ap_ST_fsm_state1445; + end + ap_ST_fsm_state1445 : begin + ap_NS_fsm = ap_ST_fsm_state1446; + end + ap_ST_fsm_state1446 : begin + ap_NS_fsm = ap_ST_fsm_state1410; + end + ap_ST_fsm_state1447 : begin + ap_NS_fsm = ap_ST_fsm_state1448; + end + ap_ST_fsm_state1448 : begin + ap_NS_fsm = ap_ST_fsm_state1449; + end + ap_ST_fsm_state1449 : begin + ap_NS_fsm = ap_ST_fsm_state1450; + end + ap_ST_fsm_state1450 : begin + ap_NS_fsm = ap_ST_fsm_state1451; + end + ap_ST_fsm_state1451 : begin + ap_NS_fsm = ap_ST_fsm_state1452; + end + ap_ST_fsm_state1452 : begin + ap_NS_fsm = ap_ST_fsm_state1453; + end + ap_ST_fsm_state1453 : begin + ap_NS_fsm = ap_ST_fsm_state1454; + end + ap_ST_fsm_state1454 : begin + ap_NS_fsm = ap_ST_fsm_state1455; + end + ap_ST_fsm_state1455 : begin + ap_NS_fsm = ap_ST_fsm_state1456; + end + ap_ST_fsm_state1456 : begin + ap_NS_fsm = ap_ST_fsm_state1457; + end + ap_ST_fsm_state1457 : begin + ap_NS_fsm = ap_ST_fsm_state1458; + end + ap_ST_fsm_state1458 : begin + ap_NS_fsm = ap_ST_fsm_state1459; + end + ap_ST_fsm_state1459 : begin + ap_NS_fsm = ap_ST_fsm_state1460; + end + ap_ST_fsm_state1460 : begin + ap_NS_fsm = ap_ST_fsm_state1461; + end + ap_ST_fsm_state1461 : begin + ap_NS_fsm = ap_ST_fsm_state1462; + end + ap_ST_fsm_state1462 : begin + ap_NS_fsm = ap_ST_fsm_state1463; + end + ap_ST_fsm_state1463 : begin + ap_NS_fsm = ap_ST_fsm_state1464; + end + ap_ST_fsm_state1464 : begin + ap_NS_fsm = ap_ST_fsm_state1465; + end + ap_ST_fsm_state1465 : begin + ap_NS_fsm = ap_ST_fsm_state1466; + end + ap_ST_fsm_state1466 : begin + ap_NS_fsm = ap_ST_fsm_state1467; + end + ap_ST_fsm_state1467 : begin + ap_NS_fsm = ap_ST_fsm_state1468; + end + ap_ST_fsm_state1468 : begin + ap_NS_fsm = ap_ST_fsm_state1469; + end + ap_ST_fsm_state1469 : begin + ap_NS_fsm = ap_ST_fsm_state1470; + end + ap_ST_fsm_state1470 : begin + ap_NS_fsm = ap_ST_fsm_state1471; + end + ap_ST_fsm_state1471 : begin + ap_NS_fsm = ap_ST_fsm_state1472; + end + ap_ST_fsm_state1472 : begin + ap_NS_fsm = ap_ST_fsm_state1473; + end + ap_ST_fsm_state1473 : begin + ap_NS_fsm = ap_ST_fsm_state1474; + end + ap_ST_fsm_state1474 : begin + ap_NS_fsm = ap_ST_fsm_state1475; + end + ap_ST_fsm_state1475 : begin + ap_NS_fsm = ap_ST_fsm_state1476; + end + ap_ST_fsm_state1476 : begin + ap_NS_fsm = ap_ST_fsm_state1477; + end + ap_ST_fsm_state1477 : begin + ap_NS_fsm = ap_ST_fsm_state1478; + end + ap_ST_fsm_state1478 : begin + ap_NS_fsm = ap_ST_fsm_state1479; + end + ap_ST_fsm_state1479 : begin + ap_NS_fsm = ap_ST_fsm_state1480; + end + ap_ST_fsm_state1480 : begin + ap_NS_fsm = ap_ST_fsm_state1481; + end + ap_ST_fsm_state1481 : begin + ap_NS_fsm = ap_ST_fsm_state1482; + end + ap_ST_fsm_state1482 : begin + ap_NS_fsm = ap_ST_fsm_state1483; + end + ap_ST_fsm_state1483 : begin + ap_NS_fsm = ap_ST_fsm_state1484; + end + ap_ST_fsm_state1484 : begin + ap_NS_fsm = ap_ST_fsm_state1485; + end + ap_ST_fsm_state1485 : begin + ap_NS_fsm = ap_ST_fsm_state1371; + end + ap_ST_fsm_state1486 : begin + ap_NS_fsm = ap_ST_fsm_state1487; + end + ap_ST_fsm_state1487 : begin + ap_NS_fsm = ap_ST_fsm_state1488; + end + ap_ST_fsm_state1488 : begin + ap_NS_fsm = ap_ST_fsm_state1489; + end + ap_ST_fsm_state1489 : begin + ap_NS_fsm = ap_ST_fsm_state1490; + end + ap_ST_fsm_state1490 : begin + ap_NS_fsm = ap_ST_fsm_state1491; + end + ap_ST_fsm_state1491 : begin + ap_NS_fsm = ap_ST_fsm_state1492; + end + ap_ST_fsm_state1492 : begin + ap_NS_fsm = ap_ST_fsm_state1493; + end + ap_ST_fsm_state1493 : begin + ap_NS_fsm = ap_ST_fsm_state1494; + end + ap_ST_fsm_state1494 : begin + ap_NS_fsm = ap_ST_fsm_state1495; + end + ap_ST_fsm_state1495 : begin + ap_NS_fsm = ap_ST_fsm_state1496; + end + ap_ST_fsm_state1496 : begin + ap_NS_fsm = ap_ST_fsm_state1497; + end + ap_ST_fsm_state1497 : begin + ap_NS_fsm = ap_ST_fsm_state1498; + end + ap_ST_fsm_state1498 : begin + ap_NS_fsm = ap_ST_fsm_state1499; + end + ap_ST_fsm_state1499 : begin + ap_NS_fsm = ap_ST_fsm_state1500; + end + ap_ST_fsm_state1500 : begin + ap_NS_fsm = ap_ST_fsm_state1501; + end + ap_ST_fsm_state1501 : begin + ap_NS_fsm = ap_ST_fsm_state1502; + end + ap_ST_fsm_state1502 : begin + ap_NS_fsm = ap_ST_fsm_state1503; + end + ap_ST_fsm_state1503 : begin + ap_NS_fsm = ap_ST_fsm_state1504; + end + ap_ST_fsm_state1504 : begin + ap_NS_fsm = ap_ST_fsm_state1505; + end + ap_ST_fsm_state1505 : begin + ap_NS_fsm = ap_ST_fsm_state1506; + end + ap_ST_fsm_state1506 : begin + ap_NS_fsm = ap_ST_fsm_state1507; + end + ap_ST_fsm_state1507 : begin + ap_NS_fsm = ap_ST_fsm_state1508; + end + ap_ST_fsm_state1508 : begin + ap_NS_fsm = ap_ST_fsm_state1509; + end + ap_ST_fsm_state1509 : begin + ap_NS_fsm = ap_ST_fsm_state1510; + end + ap_ST_fsm_state1510 : begin + ap_NS_fsm = ap_ST_fsm_state1511; + end + ap_ST_fsm_state1511 : begin + ap_NS_fsm = ap_ST_fsm_state1512; + end + ap_ST_fsm_state1512 : begin + ap_NS_fsm = ap_ST_fsm_state1513; + end + ap_ST_fsm_state1513 : begin + ap_NS_fsm = ap_ST_fsm_state1514; + end + ap_ST_fsm_state1514 : begin + ap_NS_fsm = ap_ST_fsm_state1515; + end + ap_ST_fsm_state1515 : begin + ap_NS_fsm = ap_ST_fsm_state1516; + end + ap_ST_fsm_state1516 : begin + ap_NS_fsm = ap_ST_fsm_state1517; + end + ap_ST_fsm_state1517 : begin + ap_NS_fsm = ap_ST_fsm_state1518; + end + ap_ST_fsm_state1518 : begin + ap_NS_fsm = ap_ST_fsm_state1519; + end + ap_ST_fsm_state1519 : begin + ap_NS_fsm = ap_ST_fsm_state1520; + end + ap_ST_fsm_state1520 : begin + ap_NS_fsm = ap_ST_fsm_state1521; + end + ap_ST_fsm_state1521 : begin + ap_NS_fsm = ap_ST_fsm_state1485; + end + ap_ST_fsm_state1522 : begin + ap_NS_fsm = ap_ST_fsm_state1523; + end + ap_ST_fsm_state1523 : begin + ap_NS_fsm = ap_ST_fsm_state1524; + end + ap_ST_fsm_state1524 : begin + if (((or_ln223_24_fu_110850_p2 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1524 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1525; + end else begin + ap_NS_fsm = ap_ST_fsm_state1562; + end + end + ap_ST_fsm_state1525 : begin + ap_NS_fsm = ap_ST_fsm_state1526; + end + ap_ST_fsm_state1526 : begin + ap_NS_fsm = ap_ST_fsm_state1527; + end + ap_ST_fsm_state1527 : begin + ap_NS_fsm = ap_ST_fsm_state1528; + end + ap_ST_fsm_state1528 : begin + ap_NS_fsm = ap_ST_fsm_state1529; + end + ap_ST_fsm_state1529 : begin + ap_NS_fsm = ap_ST_fsm_state1530; + end + ap_ST_fsm_state1530 : begin + ap_NS_fsm = ap_ST_fsm_state1531; + end + ap_ST_fsm_state1531 : begin + ap_NS_fsm = ap_ST_fsm_state1532; + end + ap_ST_fsm_state1532 : begin + ap_NS_fsm = ap_ST_fsm_state1533; + end + ap_ST_fsm_state1533 : begin + ap_NS_fsm = ap_ST_fsm_state1534; + end + ap_ST_fsm_state1534 : begin + ap_NS_fsm = ap_ST_fsm_state1535; + end + ap_ST_fsm_state1535 : begin + ap_NS_fsm = ap_ST_fsm_state1536; + end + ap_ST_fsm_state1536 : begin + ap_NS_fsm = ap_ST_fsm_state1537; + end + ap_ST_fsm_state1537 : begin + ap_NS_fsm = ap_ST_fsm_state1538; + end + ap_ST_fsm_state1538 : begin + ap_NS_fsm = ap_ST_fsm_state1539; + end + ap_ST_fsm_state1539 : begin + ap_NS_fsm = ap_ST_fsm_state1540; + end + ap_ST_fsm_state1540 : begin + ap_NS_fsm = ap_ST_fsm_state1541; + end + ap_ST_fsm_state1541 : begin + ap_NS_fsm = ap_ST_fsm_state1542; + end + ap_ST_fsm_state1542 : begin + ap_NS_fsm = ap_ST_fsm_state1543; + end + ap_ST_fsm_state1543 : begin + ap_NS_fsm = ap_ST_fsm_state1544; + end + ap_ST_fsm_state1544 : begin + ap_NS_fsm = ap_ST_fsm_state1545; + end + ap_ST_fsm_state1545 : begin + ap_NS_fsm = ap_ST_fsm_state1546; + end + ap_ST_fsm_state1546 : begin + ap_NS_fsm = ap_ST_fsm_state1547; + end + ap_ST_fsm_state1547 : begin + ap_NS_fsm = ap_ST_fsm_state1548; + end + ap_ST_fsm_state1548 : begin + ap_NS_fsm = ap_ST_fsm_state1549; + end + ap_ST_fsm_state1549 : begin + ap_NS_fsm = ap_ST_fsm_state1550; + end + ap_ST_fsm_state1550 : begin + ap_NS_fsm = ap_ST_fsm_state1551; + end + ap_ST_fsm_state1551 : begin + ap_NS_fsm = ap_ST_fsm_state1552; + end + ap_ST_fsm_state1552 : begin + ap_NS_fsm = ap_ST_fsm_state1553; + end + ap_ST_fsm_state1553 : begin + ap_NS_fsm = ap_ST_fsm_state1554; + end + ap_ST_fsm_state1554 : begin + ap_NS_fsm = ap_ST_fsm_state1555; + end + ap_ST_fsm_state1555 : begin + ap_NS_fsm = ap_ST_fsm_state1556; + end + ap_ST_fsm_state1556 : begin + ap_NS_fsm = ap_ST_fsm_state1557; + end + ap_ST_fsm_state1557 : begin + ap_NS_fsm = ap_ST_fsm_state1558; + end + ap_ST_fsm_state1558 : begin + ap_NS_fsm = ap_ST_fsm_state1559; + end + ap_ST_fsm_state1559 : begin + ap_NS_fsm = ap_ST_fsm_state1560; + end + ap_ST_fsm_state1560 : begin + ap_NS_fsm = ap_ST_fsm_state1561; + end + ap_ST_fsm_state1561 : begin + if (((icmp_ln206_5_fu_111270_p2 == 1'd1) & (icmp_ln208_8_fu_111062_p2 == 1'd1) & (ap_ST_fsm_state1561 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1217; + end else if (((icmp_ln208_8_fu_111062_p2 == 1'd1) & (icmp_ln206_5_fu_111270_p2 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1673; + end else if (((or_ln223_34_fu_111140_p2 == 1'd0) & (icmp_ln208_8_fu_111062_p2 == 1'd0) & (or_ln223_16_reg_140696 == 1'd0) & (ap_ST_fsm_state1561 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1598; + end else begin + ap_NS_fsm = ap_ST_fsm_state1637; + end + end + ap_ST_fsm_state1562 : begin + ap_NS_fsm = ap_ST_fsm_state1563; + end + ap_ST_fsm_state1563 : begin + ap_NS_fsm = ap_ST_fsm_state1564; + end + ap_ST_fsm_state1564 : begin + ap_NS_fsm = ap_ST_fsm_state1565; + end + ap_ST_fsm_state1565 : begin + ap_NS_fsm = ap_ST_fsm_state1566; + end + ap_ST_fsm_state1566 : begin + ap_NS_fsm = ap_ST_fsm_state1567; + end + ap_ST_fsm_state1567 : begin + ap_NS_fsm = ap_ST_fsm_state1568; + end + ap_ST_fsm_state1568 : begin + ap_NS_fsm = ap_ST_fsm_state1569; + end + ap_ST_fsm_state1569 : begin + ap_NS_fsm = ap_ST_fsm_state1570; + end + ap_ST_fsm_state1570 : begin + ap_NS_fsm = ap_ST_fsm_state1571; + end + ap_ST_fsm_state1571 : begin + ap_NS_fsm = ap_ST_fsm_state1572; + end + ap_ST_fsm_state1572 : begin + ap_NS_fsm = ap_ST_fsm_state1573; + end + ap_ST_fsm_state1573 : begin + ap_NS_fsm = ap_ST_fsm_state1574; + end + ap_ST_fsm_state1574 : begin + ap_NS_fsm = ap_ST_fsm_state1575; + end + ap_ST_fsm_state1575 : begin + ap_NS_fsm = ap_ST_fsm_state1576; + end + ap_ST_fsm_state1576 : begin + ap_NS_fsm = ap_ST_fsm_state1577; + end + ap_ST_fsm_state1577 : begin + ap_NS_fsm = ap_ST_fsm_state1578; + end + ap_ST_fsm_state1578 : begin + ap_NS_fsm = ap_ST_fsm_state1579; + end + ap_ST_fsm_state1579 : begin + ap_NS_fsm = ap_ST_fsm_state1580; + end + ap_ST_fsm_state1580 : begin + ap_NS_fsm = ap_ST_fsm_state1581; + end + ap_ST_fsm_state1581 : begin + ap_NS_fsm = ap_ST_fsm_state1582; + end + ap_ST_fsm_state1582 : begin + ap_NS_fsm = ap_ST_fsm_state1583; + end + ap_ST_fsm_state1583 : begin + ap_NS_fsm = ap_ST_fsm_state1584; + end + ap_ST_fsm_state1584 : begin + ap_NS_fsm = ap_ST_fsm_state1585; + end + ap_ST_fsm_state1585 : begin + ap_NS_fsm = ap_ST_fsm_state1586; + end + ap_ST_fsm_state1586 : begin + ap_NS_fsm = ap_ST_fsm_state1587; + end + ap_ST_fsm_state1587 : begin + ap_NS_fsm = ap_ST_fsm_state1588; + end + ap_ST_fsm_state1588 : begin + ap_NS_fsm = ap_ST_fsm_state1589; + end + ap_ST_fsm_state1589 : begin + ap_NS_fsm = ap_ST_fsm_state1590; + end + ap_ST_fsm_state1590 : begin + ap_NS_fsm = ap_ST_fsm_state1591; + end + ap_ST_fsm_state1591 : begin + ap_NS_fsm = ap_ST_fsm_state1592; + end + ap_ST_fsm_state1592 : begin + ap_NS_fsm = ap_ST_fsm_state1593; + end + ap_ST_fsm_state1593 : begin + ap_NS_fsm = ap_ST_fsm_state1594; + end + ap_ST_fsm_state1594 : begin + ap_NS_fsm = ap_ST_fsm_state1595; + end + ap_ST_fsm_state1595 : begin + ap_NS_fsm = ap_ST_fsm_state1596; + end + ap_ST_fsm_state1596 : begin + ap_NS_fsm = ap_ST_fsm_state1597; + end + ap_ST_fsm_state1597 : begin + ap_NS_fsm = ap_ST_fsm_state1561; + end + ap_ST_fsm_state1598 : begin + ap_NS_fsm = ap_ST_fsm_state1599; + end + ap_ST_fsm_state1599 : begin + ap_NS_fsm = ap_ST_fsm_state1600; + end + ap_ST_fsm_state1600 : begin + ap_NS_fsm = ap_ST_fsm_state1601; + end + ap_ST_fsm_state1601 : begin + ap_NS_fsm = ap_ST_fsm_state1602; + end + ap_ST_fsm_state1602 : begin + ap_NS_fsm = ap_ST_fsm_state1603; + end + ap_ST_fsm_state1603 : begin + ap_NS_fsm = ap_ST_fsm_state1604; + end + ap_ST_fsm_state1604 : begin + ap_NS_fsm = ap_ST_fsm_state1605; + end + ap_ST_fsm_state1605 : begin + ap_NS_fsm = ap_ST_fsm_state1606; + end + ap_ST_fsm_state1606 : begin + ap_NS_fsm = ap_ST_fsm_state1607; + end + ap_ST_fsm_state1607 : begin + ap_NS_fsm = ap_ST_fsm_state1608; + end + ap_ST_fsm_state1608 : begin + ap_NS_fsm = ap_ST_fsm_state1609; + end + ap_ST_fsm_state1609 : begin + ap_NS_fsm = ap_ST_fsm_state1610; + end + ap_ST_fsm_state1610 : begin + ap_NS_fsm = ap_ST_fsm_state1611; + end + ap_ST_fsm_state1611 : begin + ap_NS_fsm = ap_ST_fsm_state1612; + end + ap_ST_fsm_state1612 : begin + ap_NS_fsm = ap_ST_fsm_state1613; + end + ap_ST_fsm_state1613 : begin + ap_NS_fsm = ap_ST_fsm_state1614; + end + ap_ST_fsm_state1614 : begin + ap_NS_fsm = ap_ST_fsm_state1615; + end + ap_ST_fsm_state1615 : begin + ap_NS_fsm = ap_ST_fsm_state1616; + end + ap_ST_fsm_state1616 : begin + ap_NS_fsm = ap_ST_fsm_state1617; + end + ap_ST_fsm_state1617 : begin + ap_NS_fsm = ap_ST_fsm_state1618; + end + ap_ST_fsm_state1618 : begin + ap_NS_fsm = ap_ST_fsm_state1619; + end + ap_ST_fsm_state1619 : begin + ap_NS_fsm = ap_ST_fsm_state1620; + end + ap_ST_fsm_state1620 : begin + ap_NS_fsm = ap_ST_fsm_state1621; + end + ap_ST_fsm_state1621 : begin + ap_NS_fsm = ap_ST_fsm_state1622; + end + ap_ST_fsm_state1622 : begin + ap_NS_fsm = ap_ST_fsm_state1623; + end + ap_ST_fsm_state1623 : begin + ap_NS_fsm = ap_ST_fsm_state1624; + end + ap_ST_fsm_state1624 : begin + ap_NS_fsm = ap_ST_fsm_state1625; + end + ap_ST_fsm_state1625 : begin + ap_NS_fsm = ap_ST_fsm_state1626; + end + ap_ST_fsm_state1626 : begin + ap_NS_fsm = ap_ST_fsm_state1627; + end + ap_ST_fsm_state1627 : begin + ap_NS_fsm = ap_ST_fsm_state1628; + end + ap_ST_fsm_state1628 : begin + ap_NS_fsm = ap_ST_fsm_state1629; + end + ap_ST_fsm_state1629 : begin + ap_NS_fsm = ap_ST_fsm_state1630; + end + ap_ST_fsm_state1630 : begin + ap_NS_fsm = ap_ST_fsm_state1631; + end + ap_ST_fsm_state1631 : begin + ap_NS_fsm = ap_ST_fsm_state1632; + end + ap_ST_fsm_state1632 : begin + ap_NS_fsm = ap_ST_fsm_state1633; + end + ap_ST_fsm_state1633 : begin + ap_NS_fsm = ap_ST_fsm_state1634; + end + ap_ST_fsm_state1634 : begin + ap_NS_fsm = ap_ST_fsm_state1635; + end + ap_ST_fsm_state1635 : begin + ap_NS_fsm = ap_ST_fsm_state1636; + end + ap_ST_fsm_state1636 : begin + ap_NS_fsm = ap_ST_fsm_state1524; + end + ap_ST_fsm_state1637 : begin + ap_NS_fsm = ap_ST_fsm_state1638; + end + ap_ST_fsm_state1638 : begin + ap_NS_fsm = ap_ST_fsm_state1639; + end + ap_ST_fsm_state1639 : begin + ap_NS_fsm = ap_ST_fsm_state1640; + end + ap_ST_fsm_state1640 : begin + ap_NS_fsm = ap_ST_fsm_state1641; + end + ap_ST_fsm_state1641 : begin + ap_NS_fsm = ap_ST_fsm_state1642; + end + ap_ST_fsm_state1642 : begin + ap_NS_fsm = ap_ST_fsm_state1643; + end + ap_ST_fsm_state1643 : begin + ap_NS_fsm = ap_ST_fsm_state1644; + end + ap_ST_fsm_state1644 : begin + ap_NS_fsm = ap_ST_fsm_state1645; + end + ap_ST_fsm_state1645 : begin + ap_NS_fsm = ap_ST_fsm_state1646; + end + ap_ST_fsm_state1646 : begin + ap_NS_fsm = ap_ST_fsm_state1647; + end + ap_ST_fsm_state1647 : begin + ap_NS_fsm = ap_ST_fsm_state1648; + end + ap_ST_fsm_state1648 : begin + ap_NS_fsm = ap_ST_fsm_state1649; + end + ap_ST_fsm_state1649 : begin + ap_NS_fsm = ap_ST_fsm_state1650; + end + ap_ST_fsm_state1650 : begin + ap_NS_fsm = ap_ST_fsm_state1651; + end + ap_ST_fsm_state1651 : begin + ap_NS_fsm = ap_ST_fsm_state1652; + end + ap_ST_fsm_state1652 : begin + ap_NS_fsm = ap_ST_fsm_state1653; + end + ap_ST_fsm_state1653 : begin + ap_NS_fsm = ap_ST_fsm_state1654; + end + ap_ST_fsm_state1654 : begin + ap_NS_fsm = ap_ST_fsm_state1655; + end + ap_ST_fsm_state1655 : begin + ap_NS_fsm = ap_ST_fsm_state1656; + end + ap_ST_fsm_state1656 : begin + ap_NS_fsm = ap_ST_fsm_state1657; + end + ap_ST_fsm_state1657 : begin + ap_NS_fsm = ap_ST_fsm_state1658; + end + ap_ST_fsm_state1658 : begin + ap_NS_fsm = ap_ST_fsm_state1659; + end + ap_ST_fsm_state1659 : begin + ap_NS_fsm = ap_ST_fsm_state1660; + end + ap_ST_fsm_state1660 : begin + ap_NS_fsm = ap_ST_fsm_state1661; + end + ap_ST_fsm_state1661 : begin + ap_NS_fsm = ap_ST_fsm_state1662; + end + ap_ST_fsm_state1662 : begin + ap_NS_fsm = ap_ST_fsm_state1663; + end + ap_ST_fsm_state1663 : begin + ap_NS_fsm = ap_ST_fsm_state1664; + end + ap_ST_fsm_state1664 : begin + ap_NS_fsm = ap_ST_fsm_state1665; + end + ap_ST_fsm_state1665 : begin + ap_NS_fsm = ap_ST_fsm_state1666; + end + ap_ST_fsm_state1666 : begin + ap_NS_fsm = ap_ST_fsm_state1667; + end + ap_ST_fsm_state1667 : begin + ap_NS_fsm = ap_ST_fsm_state1668; + end + ap_ST_fsm_state1668 : begin + ap_NS_fsm = ap_ST_fsm_state1669; + end + ap_ST_fsm_state1669 : begin + ap_NS_fsm = ap_ST_fsm_state1670; + end + ap_ST_fsm_state1670 : begin + ap_NS_fsm = ap_ST_fsm_state1671; + end + ap_ST_fsm_state1671 : begin + ap_NS_fsm = ap_ST_fsm_state1672; + end + ap_ST_fsm_state1672 : begin + ap_NS_fsm = ap_ST_fsm_state1636; + end + ap_ST_fsm_state1673 : begin + ap_NS_fsm = ap_ST_fsm_state1674; + end + ap_ST_fsm_state1674 : begin + if (((or_ln223_41_fu_111655_p2 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1675; + end else begin + ap_NS_fsm = ap_ST_fsm_state1712; + end + end + ap_ST_fsm_state1675 : begin + ap_NS_fsm = ap_ST_fsm_state1676; + end + ap_ST_fsm_state1676 : begin + ap_NS_fsm = ap_ST_fsm_state1677; + end + ap_ST_fsm_state1677 : begin + ap_NS_fsm = ap_ST_fsm_state1678; + end + ap_ST_fsm_state1678 : begin + ap_NS_fsm = ap_ST_fsm_state1679; + end + ap_ST_fsm_state1679 : begin + ap_NS_fsm = ap_ST_fsm_state1680; + end + ap_ST_fsm_state1680 : begin + ap_NS_fsm = ap_ST_fsm_state1681; + end + ap_ST_fsm_state1681 : begin + ap_NS_fsm = ap_ST_fsm_state1682; + end + ap_ST_fsm_state1682 : begin + ap_NS_fsm = ap_ST_fsm_state1683; + end + ap_ST_fsm_state1683 : begin + ap_NS_fsm = ap_ST_fsm_state1684; + end + ap_ST_fsm_state1684 : begin + ap_NS_fsm = ap_ST_fsm_state1685; + end + ap_ST_fsm_state1685 : begin + ap_NS_fsm = ap_ST_fsm_state1686; + end + ap_ST_fsm_state1686 : begin + ap_NS_fsm = ap_ST_fsm_state1687; + end + ap_ST_fsm_state1687 : begin + ap_NS_fsm = ap_ST_fsm_state1688; + end + ap_ST_fsm_state1688 : begin + ap_NS_fsm = ap_ST_fsm_state1689; + end + ap_ST_fsm_state1689 : begin + ap_NS_fsm = ap_ST_fsm_state1690; + end + ap_ST_fsm_state1690 : begin + ap_NS_fsm = ap_ST_fsm_state1691; + end + ap_ST_fsm_state1691 : begin + ap_NS_fsm = ap_ST_fsm_state1692; + end + ap_ST_fsm_state1692 : begin + ap_NS_fsm = ap_ST_fsm_state1693; + end + ap_ST_fsm_state1693 : begin + ap_NS_fsm = ap_ST_fsm_state1694; + end + ap_ST_fsm_state1694 : begin + ap_NS_fsm = ap_ST_fsm_state1695; + end + ap_ST_fsm_state1695 : begin + ap_NS_fsm = ap_ST_fsm_state1696; + end + ap_ST_fsm_state1696 : begin + ap_NS_fsm = ap_ST_fsm_state1697; + end + ap_ST_fsm_state1697 : begin + ap_NS_fsm = ap_ST_fsm_state1698; + end + ap_ST_fsm_state1698 : begin + ap_NS_fsm = ap_ST_fsm_state1699; + end + ap_ST_fsm_state1699 : begin + ap_NS_fsm = ap_ST_fsm_state1700; + end + ap_ST_fsm_state1700 : begin + ap_NS_fsm = ap_ST_fsm_state1701; + end + ap_ST_fsm_state1701 : begin + ap_NS_fsm = ap_ST_fsm_state1702; + end + ap_ST_fsm_state1702 : begin + ap_NS_fsm = ap_ST_fsm_state1703; + end + ap_ST_fsm_state1703 : begin + ap_NS_fsm = ap_ST_fsm_state1704; + end + ap_ST_fsm_state1704 : begin + ap_NS_fsm = ap_ST_fsm_state1705; + end + ap_ST_fsm_state1705 : begin + ap_NS_fsm = ap_ST_fsm_state1706; + end + ap_ST_fsm_state1706 : begin + ap_NS_fsm = ap_ST_fsm_state1707; + end + ap_ST_fsm_state1707 : begin + ap_NS_fsm = ap_ST_fsm_state1708; + end + ap_ST_fsm_state1708 : begin + ap_NS_fsm = ap_ST_fsm_state1709; + end + ap_ST_fsm_state1709 : begin + ap_NS_fsm = ap_ST_fsm_state1710; + end + ap_ST_fsm_state1710 : begin + ap_NS_fsm = ap_ST_fsm_state1711; + end + ap_ST_fsm_state1711 : begin + if (((icmp_ln208_13_fu_111867_p2 == 1'd1) & (ap_ST_fsm_state1711 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1522; + end else if (((or_ln223_45_fu_111945_p2 == 1'd0) & (icmp_ln208_13_fu_111867_p2 == 1'd0) & (or_ln223_33_reg_141475 == 1'd0) & (ap_ST_fsm_state1711 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1748; + end else begin + ap_NS_fsm = ap_ST_fsm_state1785; + end + end + ap_ST_fsm_state1712 : begin + ap_NS_fsm = ap_ST_fsm_state1713; + end + ap_ST_fsm_state1713 : begin + ap_NS_fsm = ap_ST_fsm_state1714; + end + ap_ST_fsm_state1714 : begin + ap_NS_fsm = ap_ST_fsm_state1715; + end + ap_ST_fsm_state1715 : begin + ap_NS_fsm = ap_ST_fsm_state1716; + end + ap_ST_fsm_state1716 : begin + ap_NS_fsm = ap_ST_fsm_state1717; + end + ap_ST_fsm_state1717 : begin + ap_NS_fsm = ap_ST_fsm_state1718; + end + ap_ST_fsm_state1718 : begin + ap_NS_fsm = ap_ST_fsm_state1719; + end + ap_ST_fsm_state1719 : begin + ap_NS_fsm = ap_ST_fsm_state1720; + end + ap_ST_fsm_state1720 : begin + ap_NS_fsm = ap_ST_fsm_state1721; + end + ap_ST_fsm_state1721 : begin + ap_NS_fsm = ap_ST_fsm_state1722; + end + ap_ST_fsm_state1722 : begin + ap_NS_fsm = ap_ST_fsm_state1723; + end + ap_ST_fsm_state1723 : begin + ap_NS_fsm = ap_ST_fsm_state1724; + end + ap_ST_fsm_state1724 : begin + ap_NS_fsm = ap_ST_fsm_state1725; + end + ap_ST_fsm_state1725 : begin + ap_NS_fsm = ap_ST_fsm_state1726; + end + ap_ST_fsm_state1726 : begin + ap_NS_fsm = ap_ST_fsm_state1727; + end + ap_ST_fsm_state1727 : begin + ap_NS_fsm = ap_ST_fsm_state1728; + end + ap_ST_fsm_state1728 : begin + ap_NS_fsm = ap_ST_fsm_state1729; + end + ap_ST_fsm_state1729 : begin + ap_NS_fsm = ap_ST_fsm_state1730; + end + ap_ST_fsm_state1730 : begin + ap_NS_fsm = ap_ST_fsm_state1731; + end + ap_ST_fsm_state1731 : begin + ap_NS_fsm = ap_ST_fsm_state1732; + end + ap_ST_fsm_state1732 : begin + ap_NS_fsm = ap_ST_fsm_state1733; + end + ap_ST_fsm_state1733 : begin + ap_NS_fsm = ap_ST_fsm_state1734; + end + ap_ST_fsm_state1734 : begin + ap_NS_fsm = ap_ST_fsm_state1735; + end + ap_ST_fsm_state1735 : begin + ap_NS_fsm = ap_ST_fsm_state1736; + end + ap_ST_fsm_state1736 : begin + ap_NS_fsm = ap_ST_fsm_state1737; + end + ap_ST_fsm_state1737 : begin + ap_NS_fsm = ap_ST_fsm_state1738; + end + ap_ST_fsm_state1738 : begin + ap_NS_fsm = ap_ST_fsm_state1739; + end + ap_ST_fsm_state1739 : begin + ap_NS_fsm = ap_ST_fsm_state1740; + end + ap_ST_fsm_state1740 : begin + ap_NS_fsm = ap_ST_fsm_state1741; + end + ap_ST_fsm_state1741 : begin + ap_NS_fsm = ap_ST_fsm_state1742; + end + ap_ST_fsm_state1742 : begin + ap_NS_fsm = ap_ST_fsm_state1743; + end + ap_ST_fsm_state1743 : begin + ap_NS_fsm = ap_ST_fsm_state1744; + end + ap_ST_fsm_state1744 : begin + ap_NS_fsm = ap_ST_fsm_state1745; + end + ap_ST_fsm_state1745 : begin + ap_NS_fsm = ap_ST_fsm_state1746; + end + ap_ST_fsm_state1746 : begin + ap_NS_fsm = ap_ST_fsm_state1747; + end + ap_ST_fsm_state1747 : begin + ap_NS_fsm = ap_ST_fsm_state1711; + end + ap_ST_fsm_state1748 : begin + ap_NS_fsm = ap_ST_fsm_state1749; + end + ap_ST_fsm_state1749 : begin + ap_NS_fsm = ap_ST_fsm_state1750; + end + ap_ST_fsm_state1750 : begin + ap_NS_fsm = ap_ST_fsm_state1751; + end + ap_ST_fsm_state1751 : begin + ap_NS_fsm = ap_ST_fsm_state1752; + end + ap_ST_fsm_state1752 : begin + ap_NS_fsm = ap_ST_fsm_state1753; + end + ap_ST_fsm_state1753 : begin + ap_NS_fsm = ap_ST_fsm_state1754; + end + ap_ST_fsm_state1754 : begin + ap_NS_fsm = ap_ST_fsm_state1755; + end + ap_ST_fsm_state1755 : begin + ap_NS_fsm = ap_ST_fsm_state1756; + end + ap_ST_fsm_state1756 : begin + ap_NS_fsm = ap_ST_fsm_state1757; + end + ap_ST_fsm_state1757 : begin + ap_NS_fsm = ap_ST_fsm_state1758; + end + ap_ST_fsm_state1758 : begin + ap_NS_fsm = ap_ST_fsm_state1759; + end + ap_ST_fsm_state1759 : begin + ap_NS_fsm = ap_ST_fsm_state1760; + end + ap_ST_fsm_state1760 : begin + ap_NS_fsm = ap_ST_fsm_state1761; + end + ap_ST_fsm_state1761 : begin + ap_NS_fsm = ap_ST_fsm_state1762; + end + ap_ST_fsm_state1762 : begin + ap_NS_fsm = ap_ST_fsm_state1763; + end + ap_ST_fsm_state1763 : begin + ap_NS_fsm = ap_ST_fsm_state1764; + end + ap_ST_fsm_state1764 : begin + ap_NS_fsm = ap_ST_fsm_state1765; + end + ap_ST_fsm_state1765 : begin + ap_NS_fsm = ap_ST_fsm_state1766; + end + ap_ST_fsm_state1766 : begin + ap_NS_fsm = ap_ST_fsm_state1767; + end + ap_ST_fsm_state1767 : begin + ap_NS_fsm = ap_ST_fsm_state1768; + end + ap_ST_fsm_state1768 : begin + ap_NS_fsm = ap_ST_fsm_state1769; + end + ap_ST_fsm_state1769 : begin + ap_NS_fsm = ap_ST_fsm_state1770; + end + ap_ST_fsm_state1770 : begin + ap_NS_fsm = ap_ST_fsm_state1771; + end + ap_ST_fsm_state1771 : begin + ap_NS_fsm = ap_ST_fsm_state1772; + end + ap_ST_fsm_state1772 : begin + ap_NS_fsm = ap_ST_fsm_state1773; + end + ap_ST_fsm_state1773 : begin + ap_NS_fsm = ap_ST_fsm_state1774; + end + ap_ST_fsm_state1774 : begin + ap_NS_fsm = ap_ST_fsm_state1775; + end + ap_ST_fsm_state1775 : begin + ap_NS_fsm = ap_ST_fsm_state1776; + end + ap_ST_fsm_state1776 : begin + ap_NS_fsm = ap_ST_fsm_state1777; + end + ap_ST_fsm_state1777 : begin + ap_NS_fsm = ap_ST_fsm_state1778; + end + ap_ST_fsm_state1778 : begin + ap_NS_fsm = ap_ST_fsm_state1779; + end + ap_ST_fsm_state1779 : begin + ap_NS_fsm = ap_ST_fsm_state1780; + end + ap_ST_fsm_state1780 : begin + ap_NS_fsm = ap_ST_fsm_state1781; + end + ap_ST_fsm_state1781 : begin + ap_NS_fsm = ap_ST_fsm_state1782; + end + ap_ST_fsm_state1782 : begin + ap_NS_fsm = ap_ST_fsm_state1783; + end + ap_ST_fsm_state1783 : begin + ap_NS_fsm = ap_ST_fsm_state1784; + end + ap_ST_fsm_state1784 : begin + ap_NS_fsm = ap_ST_fsm_state1674; + end + ap_ST_fsm_state1785 : begin + ap_NS_fsm = ap_ST_fsm_state1786; + end + ap_ST_fsm_state1786 : begin + ap_NS_fsm = ap_ST_fsm_state1787; + end + ap_ST_fsm_state1787 : begin + ap_NS_fsm = ap_ST_fsm_state1788; + end + ap_ST_fsm_state1788 : begin + ap_NS_fsm = ap_ST_fsm_state1789; + end + ap_ST_fsm_state1789 : begin + ap_NS_fsm = ap_ST_fsm_state1790; + end + ap_ST_fsm_state1790 : begin + ap_NS_fsm = ap_ST_fsm_state1791; + end + ap_ST_fsm_state1791 : begin + ap_NS_fsm = ap_ST_fsm_state1792; + end + ap_ST_fsm_state1792 : begin + ap_NS_fsm = ap_ST_fsm_state1793; + end + ap_ST_fsm_state1793 : begin + ap_NS_fsm = ap_ST_fsm_state1794; + end + ap_ST_fsm_state1794 : begin + ap_NS_fsm = ap_ST_fsm_state1795; + end + ap_ST_fsm_state1795 : begin + ap_NS_fsm = ap_ST_fsm_state1796; + end + ap_ST_fsm_state1796 : begin + ap_NS_fsm = ap_ST_fsm_state1797; + end + ap_ST_fsm_state1797 : begin + ap_NS_fsm = ap_ST_fsm_state1798; + end + ap_ST_fsm_state1798 : begin + ap_NS_fsm = ap_ST_fsm_state1799; + end + ap_ST_fsm_state1799 : begin + ap_NS_fsm = ap_ST_fsm_state1800; + end + ap_ST_fsm_state1800 : begin + ap_NS_fsm = ap_ST_fsm_state1801; + end + ap_ST_fsm_state1801 : begin + ap_NS_fsm = ap_ST_fsm_state1802; + end + ap_ST_fsm_state1802 : begin + ap_NS_fsm = ap_ST_fsm_state1803; + end + ap_ST_fsm_state1803 : begin + ap_NS_fsm = ap_ST_fsm_state1804; + end + ap_ST_fsm_state1804 : begin + ap_NS_fsm = ap_ST_fsm_state1805; + end + ap_ST_fsm_state1805 : begin + ap_NS_fsm = ap_ST_fsm_state1806; + end + ap_ST_fsm_state1806 : begin + ap_NS_fsm = ap_ST_fsm_state1807; + end + ap_ST_fsm_state1807 : begin + ap_NS_fsm = ap_ST_fsm_state1808; + end + ap_ST_fsm_state1808 : begin + ap_NS_fsm = ap_ST_fsm_state1809; + end + ap_ST_fsm_state1809 : begin + ap_NS_fsm = ap_ST_fsm_state1810; + end + ap_ST_fsm_state1810 : begin + ap_NS_fsm = ap_ST_fsm_state1811; + end + ap_ST_fsm_state1811 : begin + ap_NS_fsm = ap_ST_fsm_state1812; + end + ap_ST_fsm_state1812 : begin + ap_NS_fsm = ap_ST_fsm_state1813; + end + ap_ST_fsm_state1813 : begin + ap_NS_fsm = ap_ST_fsm_state1814; + end + ap_ST_fsm_state1814 : begin + ap_NS_fsm = ap_ST_fsm_state1815; + end + ap_ST_fsm_state1815 : begin + ap_NS_fsm = ap_ST_fsm_state1816; + end + ap_ST_fsm_state1816 : begin + ap_NS_fsm = ap_ST_fsm_state1817; + end + ap_ST_fsm_state1817 : begin + ap_NS_fsm = ap_ST_fsm_state1818; + end + ap_ST_fsm_state1818 : begin + ap_NS_fsm = ap_ST_fsm_state1819; + end + ap_ST_fsm_state1819 : begin + ap_NS_fsm = ap_ST_fsm_state1820; + end + ap_ST_fsm_state1820 : begin + ap_NS_fsm = ap_ST_fsm_state1784; + end + ap_ST_fsm_state1821 : begin + if (((icmp_ln203_3_fu_112277_p2 == 1'd1) & (ap_ST_fsm_state1821 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1215; + end else begin + ap_NS_fsm = ap_ST_fsm_state1822; + end + end + ap_ST_fsm_state1822 : begin + if (((icmp_ln204_3_fu_112317_p2 == 1'd1) & (ap_ST_fsm_state1822 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1821; + end else begin + ap_NS_fsm = ap_ST_fsm_state1823; + end + end + ap_ST_fsm_state1823 : begin + ap_NS_fsm = ap_ST_fsm_state1824; + end + ap_ST_fsm_state1824 : begin + ap_NS_fsm = ap_ST_fsm_state1825; + end + ap_ST_fsm_state1825 : begin + if (((ap_ST_fsm_state1825 == ap_CS_fsm) & (or_ln223_7_fu_112574_p2 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state1826; + end else begin + ap_NS_fsm = ap_ST_fsm_state1863; + end + end + ap_ST_fsm_state1826 : begin + ap_NS_fsm = ap_ST_fsm_state1827; + end + ap_ST_fsm_state1827 : begin + ap_NS_fsm = ap_ST_fsm_state1828; + end + ap_ST_fsm_state1828 : begin + ap_NS_fsm = ap_ST_fsm_state1829; + end + ap_ST_fsm_state1829 : begin + ap_NS_fsm = ap_ST_fsm_state1830; + end + ap_ST_fsm_state1830 : begin + ap_NS_fsm = ap_ST_fsm_state1831; + end + ap_ST_fsm_state1831 : begin + ap_NS_fsm = ap_ST_fsm_state1832; + end + ap_ST_fsm_state1832 : begin + ap_NS_fsm = ap_ST_fsm_state1833; + end + ap_ST_fsm_state1833 : begin + ap_NS_fsm = ap_ST_fsm_state1834; + end + ap_ST_fsm_state1834 : begin + ap_NS_fsm = ap_ST_fsm_state1835; + end + ap_ST_fsm_state1835 : begin + ap_NS_fsm = ap_ST_fsm_state1836; + end + ap_ST_fsm_state1836 : begin + ap_NS_fsm = ap_ST_fsm_state1837; + end + ap_ST_fsm_state1837 : begin + ap_NS_fsm = ap_ST_fsm_state1838; + end + ap_ST_fsm_state1838 : begin + ap_NS_fsm = ap_ST_fsm_state1839; + end + ap_ST_fsm_state1839 : begin + ap_NS_fsm = ap_ST_fsm_state1840; + end + ap_ST_fsm_state1840 : begin + ap_NS_fsm = ap_ST_fsm_state1841; + end + ap_ST_fsm_state1841 : begin + ap_NS_fsm = ap_ST_fsm_state1842; + end + ap_ST_fsm_state1842 : begin + ap_NS_fsm = ap_ST_fsm_state1843; + end + ap_ST_fsm_state1843 : begin + ap_NS_fsm = ap_ST_fsm_state1844; + end + ap_ST_fsm_state1844 : begin + ap_NS_fsm = ap_ST_fsm_state1845; + end + ap_ST_fsm_state1845 : begin + ap_NS_fsm = ap_ST_fsm_state1846; + end + ap_ST_fsm_state1846 : begin + ap_NS_fsm = ap_ST_fsm_state1847; + end + ap_ST_fsm_state1847 : begin + ap_NS_fsm = ap_ST_fsm_state1848; + end + ap_ST_fsm_state1848 : begin + ap_NS_fsm = ap_ST_fsm_state1849; + end + ap_ST_fsm_state1849 : begin + ap_NS_fsm = ap_ST_fsm_state1850; + end + ap_ST_fsm_state1850 : begin + ap_NS_fsm = ap_ST_fsm_state1851; + end + ap_ST_fsm_state1851 : begin + ap_NS_fsm = ap_ST_fsm_state1852; + end + ap_ST_fsm_state1852 : begin + ap_NS_fsm = ap_ST_fsm_state1853; + end + ap_ST_fsm_state1853 : begin + ap_NS_fsm = ap_ST_fsm_state1854; + end + ap_ST_fsm_state1854 : begin + ap_NS_fsm = ap_ST_fsm_state1855; + end + ap_ST_fsm_state1855 : begin + ap_NS_fsm = ap_ST_fsm_state1856; + end + ap_ST_fsm_state1856 : begin + ap_NS_fsm = ap_ST_fsm_state1857; + end + ap_ST_fsm_state1857 : begin + ap_NS_fsm = ap_ST_fsm_state1858; + end + ap_ST_fsm_state1858 : begin + ap_NS_fsm = ap_ST_fsm_state1859; + end + ap_ST_fsm_state1859 : begin + ap_NS_fsm = ap_ST_fsm_state1860; + end + ap_ST_fsm_state1860 : begin + ap_NS_fsm = ap_ST_fsm_state1861; + end + ap_ST_fsm_state1861 : begin + ap_NS_fsm = ap_ST_fsm_state1862; + end + ap_ST_fsm_state1862 : begin + if (((icmp_ln206_3_fu_112994_p2 == 1'd1) & (icmp_ln208_3_fu_112786_p2 == 1'd1) & (ap_ST_fsm_state1862 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2126; + end else if (((icmp_ln208_3_fu_112786_p2 == 1'd1) & (ap_ST_fsm_state1862 == ap_CS_fsm) & (icmp_ln206_3_fu_112994_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state1974; + end else if (((ap_ST_fsm_state1862 == ap_CS_fsm) & (or_ln223_20_fu_112864_p2 == 1'd0) & (icmp_ln208_3_fu_112786_p2 == 1'd0) & (or_ln223_4_reg_142485 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state1899; + end else begin + ap_NS_fsm = ap_ST_fsm_state1938; + end + end + ap_ST_fsm_state1863 : begin + ap_NS_fsm = ap_ST_fsm_state1864; + end + ap_ST_fsm_state1864 : begin + ap_NS_fsm = ap_ST_fsm_state1865; + end + ap_ST_fsm_state1865 : begin + ap_NS_fsm = ap_ST_fsm_state1866; + end + ap_ST_fsm_state1866 : begin + ap_NS_fsm = ap_ST_fsm_state1867; + end + ap_ST_fsm_state1867 : begin + ap_NS_fsm = ap_ST_fsm_state1868; + end + ap_ST_fsm_state1868 : begin + ap_NS_fsm = ap_ST_fsm_state1869; + end + ap_ST_fsm_state1869 : begin + ap_NS_fsm = ap_ST_fsm_state1870; + end + ap_ST_fsm_state1870 : begin + ap_NS_fsm = ap_ST_fsm_state1871; + end + ap_ST_fsm_state1871 : begin + ap_NS_fsm = ap_ST_fsm_state1872; + end + ap_ST_fsm_state1872 : begin + ap_NS_fsm = ap_ST_fsm_state1873; + end + ap_ST_fsm_state1873 : begin + ap_NS_fsm = ap_ST_fsm_state1874; + end + ap_ST_fsm_state1874 : begin + ap_NS_fsm = ap_ST_fsm_state1875; + end + ap_ST_fsm_state1875 : begin + ap_NS_fsm = ap_ST_fsm_state1876; + end + ap_ST_fsm_state1876 : begin + ap_NS_fsm = ap_ST_fsm_state1877; + end + ap_ST_fsm_state1877 : begin + ap_NS_fsm = ap_ST_fsm_state1878; + end + ap_ST_fsm_state1878 : begin + ap_NS_fsm = ap_ST_fsm_state1879; + end + ap_ST_fsm_state1879 : begin + ap_NS_fsm = ap_ST_fsm_state1880; + end + ap_ST_fsm_state1880 : begin + ap_NS_fsm = ap_ST_fsm_state1881; + end + ap_ST_fsm_state1881 : begin + ap_NS_fsm = ap_ST_fsm_state1882; + end + ap_ST_fsm_state1882 : begin + ap_NS_fsm = ap_ST_fsm_state1883; + end + ap_ST_fsm_state1883 : begin + ap_NS_fsm = ap_ST_fsm_state1884; + end + ap_ST_fsm_state1884 : begin + ap_NS_fsm = ap_ST_fsm_state1885; + end + ap_ST_fsm_state1885 : begin + ap_NS_fsm = ap_ST_fsm_state1886; + end + ap_ST_fsm_state1886 : begin + ap_NS_fsm = ap_ST_fsm_state1887; + end + ap_ST_fsm_state1887 : begin + ap_NS_fsm = ap_ST_fsm_state1888; + end + ap_ST_fsm_state1888 : begin + ap_NS_fsm = ap_ST_fsm_state1889; + end + ap_ST_fsm_state1889 : begin + ap_NS_fsm = ap_ST_fsm_state1890; + end + ap_ST_fsm_state1890 : begin + ap_NS_fsm = ap_ST_fsm_state1891; + end + ap_ST_fsm_state1891 : begin + ap_NS_fsm = ap_ST_fsm_state1892; + end + ap_ST_fsm_state1892 : begin + ap_NS_fsm = ap_ST_fsm_state1893; + end + ap_ST_fsm_state1893 : begin + ap_NS_fsm = ap_ST_fsm_state1894; + end + ap_ST_fsm_state1894 : begin + ap_NS_fsm = ap_ST_fsm_state1895; + end + ap_ST_fsm_state1895 : begin + ap_NS_fsm = ap_ST_fsm_state1896; + end + ap_ST_fsm_state1896 : begin + ap_NS_fsm = ap_ST_fsm_state1897; + end + ap_ST_fsm_state1897 : begin + ap_NS_fsm = ap_ST_fsm_state1898; + end + ap_ST_fsm_state1898 : begin + ap_NS_fsm = ap_ST_fsm_state1862; + end + ap_ST_fsm_state1899 : begin + ap_NS_fsm = ap_ST_fsm_state1900; + end + ap_ST_fsm_state1900 : begin + ap_NS_fsm = ap_ST_fsm_state1901; + end + ap_ST_fsm_state1901 : begin + ap_NS_fsm = ap_ST_fsm_state1902; + end + ap_ST_fsm_state1902 : begin + ap_NS_fsm = ap_ST_fsm_state1903; + end + ap_ST_fsm_state1903 : begin + ap_NS_fsm = ap_ST_fsm_state1904; + end + ap_ST_fsm_state1904 : begin + ap_NS_fsm = ap_ST_fsm_state1905; + end + ap_ST_fsm_state1905 : begin + ap_NS_fsm = ap_ST_fsm_state1906; + end + ap_ST_fsm_state1906 : begin + ap_NS_fsm = ap_ST_fsm_state1907; + end + ap_ST_fsm_state1907 : begin + ap_NS_fsm = ap_ST_fsm_state1908; + end + ap_ST_fsm_state1908 : begin + ap_NS_fsm = ap_ST_fsm_state1909; + end + ap_ST_fsm_state1909 : begin + ap_NS_fsm = ap_ST_fsm_state1910; + end + ap_ST_fsm_state1910 : begin + ap_NS_fsm = ap_ST_fsm_state1911; + end + ap_ST_fsm_state1911 : begin + ap_NS_fsm = ap_ST_fsm_state1912; + end + ap_ST_fsm_state1912 : begin + ap_NS_fsm = ap_ST_fsm_state1913; + end + ap_ST_fsm_state1913 : begin + ap_NS_fsm = ap_ST_fsm_state1914; + end + ap_ST_fsm_state1914 : begin + ap_NS_fsm = ap_ST_fsm_state1915; + end + ap_ST_fsm_state1915 : begin + ap_NS_fsm = ap_ST_fsm_state1916; + end + ap_ST_fsm_state1916 : begin + ap_NS_fsm = ap_ST_fsm_state1917; + end + ap_ST_fsm_state1917 : begin + ap_NS_fsm = ap_ST_fsm_state1918; + end + ap_ST_fsm_state1918 : begin + ap_NS_fsm = ap_ST_fsm_state1919; + end + ap_ST_fsm_state1919 : begin + ap_NS_fsm = ap_ST_fsm_state1920; + end + ap_ST_fsm_state1920 : begin + ap_NS_fsm = ap_ST_fsm_state1921; + end + ap_ST_fsm_state1921 : begin + ap_NS_fsm = ap_ST_fsm_state1922; + end + ap_ST_fsm_state1922 : begin + ap_NS_fsm = ap_ST_fsm_state1923; + end + ap_ST_fsm_state1923 : begin + ap_NS_fsm = ap_ST_fsm_state1924; + end + ap_ST_fsm_state1924 : begin + ap_NS_fsm = ap_ST_fsm_state1925; + end + ap_ST_fsm_state1925 : begin + ap_NS_fsm = ap_ST_fsm_state1926; + end + ap_ST_fsm_state1926 : begin + ap_NS_fsm = ap_ST_fsm_state1927; + end + ap_ST_fsm_state1927 : begin + ap_NS_fsm = ap_ST_fsm_state1928; + end + ap_ST_fsm_state1928 : begin + ap_NS_fsm = ap_ST_fsm_state1929; + end + ap_ST_fsm_state1929 : begin + ap_NS_fsm = ap_ST_fsm_state1930; + end + ap_ST_fsm_state1930 : begin + ap_NS_fsm = ap_ST_fsm_state1931; + end + ap_ST_fsm_state1931 : begin + ap_NS_fsm = ap_ST_fsm_state1932; + end + ap_ST_fsm_state1932 : begin + ap_NS_fsm = ap_ST_fsm_state1933; + end + ap_ST_fsm_state1933 : begin + ap_NS_fsm = ap_ST_fsm_state1934; + end + ap_ST_fsm_state1934 : begin + ap_NS_fsm = ap_ST_fsm_state1935; + end + ap_ST_fsm_state1935 : begin + ap_NS_fsm = ap_ST_fsm_state1936; + end + ap_ST_fsm_state1936 : begin + ap_NS_fsm = ap_ST_fsm_state1937; + end + ap_ST_fsm_state1937 : begin + ap_NS_fsm = ap_ST_fsm_state1825; + end + ap_ST_fsm_state1938 : begin + ap_NS_fsm = ap_ST_fsm_state1939; + end + ap_ST_fsm_state1939 : begin + ap_NS_fsm = ap_ST_fsm_state1940; + end + ap_ST_fsm_state1940 : begin + ap_NS_fsm = ap_ST_fsm_state1941; + end + ap_ST_fsm_state1941 : begin + ap_NS_fsm = ap_ST_fsm_state1942; + end + ap_ST_fsm_state1942 : begin + ap_NS_fsm = ap_ST_fsm_state1943; + end + ap_ST_fsm_state1943 : begin + ap_NS_fsm = ap_ST_fsm_state1944; + end + ap_ST_fsm_state1944 : begin + ap_NS_fsm = ap_ST_fsm_state1945; + end + ap_ST_fsm_state1945 : begin + ap_NS_fsm = ap_ST_fsm_state1946; + end + ap_ST_fsm_state1946 : begin + ap_NS_fsm = ap_ST_fsm_state1947; + end + ap_ST_fsm_state1947 : begin + ap_NS_fsm = ap_ST_fsm_state1948; + end + ap_ST_fsm_state1948 : begin + ap_NS_fsm = ap_ST_fsm_state1949; + end + ap_ST_fsm_state1949 : begin + ap_NS_fsm = ap_ST_fsm_state1950; + end + ap_ST_fsm_state1950 : begin + ap_NS_fsm = ap_ST_fsm_state1951; + end + ap_ST_fsm_state1951 : begin + ap_NS_fsm = ap_ST_fsm_state1952; + end + ap_ST_fsm_state1952 : begin + ap_NS_fsm = ap_ST_fsm_state1953; + end + ap_ST_fsm_state1953 : begin + ap_NS_fsm = ap_ST_fsm_state1954; + end + ap_ST_fsm_state1954 : begin + ap_NS_fsm = ap_ST_fsm_state1955; + end + ap_ST_fsm_state1955 : begin + ap_NS_fsm = ap_ST_fsm_state1956; + end + ap_ST_fsm_state1956 : begin + ap_NS_fsm = ap_ST_fsm_state1957; + end + ap_ST_fsm_state1957 : begin + ap_NS_fsm = ap_ST_fsm_state1958; + end + ap_ST_fsm_state1958 : begin + ap_NS_fsm = ap_ST_fsm_state1959; + end + ap_ST_fsm_state1959 : begin + ap_NS_fsm = ap_ST_fsm_state1960; + end + ap_ST_fsm_state1960 : begin + ap_NS_fsm = ap_ST_fsm_state1961; + end + ap_ST_fsm_state1961 : begin + ap_NS_fsm = ap_ST_fsm_state1962; + end + ap_ST_fsm_state1962 : begin + ap_NS_fsm = ap_ST_fsm_state1963; + end + ap_ST_fsm_state1963 : begin + ap_NS_fsm = ap_ST_fsm_state1964; + end + ap_ST_fsm_state1964 : begin + ap_NS_fsm = ap_ST_fsm_state1965; + end + ap_ST_fsm_state1965 : begin + ap_NS_fsm = ap_ST_fsm_state1966; + end + ap_ST_fsm_state1966 : begin + ap_NS_fsm = ap_ST_fsm_state1967; + end + ap_ST_fsm_state1967 : begin + ap_NS_fsm = ap_ST_fsm_state1968; + end + ap_ST_fsm_state1968 : begin + ap_NS_fsm = ap_ST_fsm_state1969; + end + ap_ST_fsm_state1969 : begin + ap_NS_fsm = ap_ST_fsm_state1970; + end + ap_ST_fsm_state1970 : begin + ap_NS_fsm = ap_ST_fsm_state1971; + end + ap_ST_fsm_state1971 : begin + ap_NS_fsm = ap_ST_fsm_state1972; + end + ap_ST_fsm_state1972 : begin + ap_NS_fsm = ap_ST_fsm_state1973; + end + ap_ST_fsm_state1973 : begin + ap_NS_fsm = ap_ST_fsm_state1937; + end + ap_ST_fsm_state1974 : begin + ap_NS_fsm = ap_ST_fsm_state1975; + end + ap_ST_fsm_state1975 : begin + if (((ap_ST_fsm_state1975 == ap_CS_fsm) & (or_ln223_19_reg_143411 == 1'd0) & (or_ln223_26_fu_113452_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state1976; + end else begin + ap_NS_fsm = ap_ST_fsm_state2015; + end + end + ap_ST_fsm_state1976 : begin + ap_NS_fsm = ap_ST_fsm_state1977; + end + ap_ST_fsm_state1977 : begin + ap_NS_fsm = ap_ST_fsm_state1978; + end + ap_ST_fsm_state1978 : begin + ap_NS_fsm = ap_ST_fsm_state1979; + end + ap_ST_fsm_state1979 : begin + ap_NS_fsm = ap_ST_fsm_state1980; + end + ap_ST_fsm_state1980 : begin + ap_NS_fsm = ap_ST_fsm_state1981; + end + ap_ST_fsm_state1981 : begin + ap_NS_fsm = ap_ST_fsm_state1982; + end + ap_ST_fsm_state1982 : begin + ap_NS_fsm = ap_ST_fsm_state1983; + end + ap_ST_fsm_state1983 : begin + ap_NS_fsm = ap_ST_fsm_state1984; + end + ap_ST_fsm_state1984 : begin + ap_NS_fsm = ap_ST_fsm_state1985; + end + ap_ST_fsm_state1985 : begin + ap_NS_fsm = ap_ST_fsm_state1986; + end + ap_ST_fsm_state1986 : begin + ap_NS_fsm = ap_ST_fsm_state1987; + end + ap_ST_fsm_state1987 : begin + ap_NS_fsm = ap_ST_fsm_state1988; + end + ap_ST_fsm_state1988 : begin + ap_NS_fsm = ap_ST_fsm_state1989; + end + ap_ST_fsm_state1989 : begin + ap_NS_fsm = ap_ST_fsm_state1990; + end + ap_ST_fsm_state1990 : begin + ap_NS_fsm = ap_ST_fsm_state1991; + end + ap_ST_fsm_state1991 : begin + ap_NS_fsm = ap_ST_fsm_state1992; + end + ap_ST_fsm_state1992 : begin + ap_NS_fsm = ap_ST_fsm_state1993; + end + ap_ST_fsm_state1993 : begin + ap_NS_fsm = ap_ST_fsm_state1994; + end + ap_ST_fsm_state1994 : begin + ap_NS_fsm = ap_ST_fsm_state1995; + end + ap_ST_fsm_state1995 : begin + ap_NS_fsm = ap_ST_fsm_state1996; + end + ap_ST_fsm_state1996 : begin + ap_NS_fsm = ap_ST_fsm_state1997; + end + ap_ST_fsm_state1997 : begin + ap_NS_fsm = ap_ST_fsm_state1998; + end + ap_ST_fsm_state1998 : begin + ap_NS_fsm = ap_ST_fsm_state1999; + end + ap_ST_fsm_state1999 : begin + ap_NS_fsm = ap_ST_fsm_state2000; + end + ap_ST_fsm_state2000 : begin + ap_NS_fsm = ap_ST_fsm_state2001; + end + ap_ST_fsm_state2001 : begin + ap_NS_fsm = ap_ST_fsm_state2002; + end + ap_ST_fsm_state2002 : begin + ap_NS_fsm = ap_ST_fsm_state2003; + end + ap_ST_fsm_state2003 : begin + ap_NS_fsm = ap_ST_fsm_state2004; + end + ap_ST_fsm_state2004 : begin + ap_NS_fsm = ap_ST_fsm_state2005; + end + ap_ST_fsm_state2005 : begin + ap_NS_fsm = ap_ST_fsm_state2006; + end + ap_ST_fsm_state2006 : begin + ap_NS_fsm = ap_ST_fsm_state2007; + end + ap_ST_fsm_state2007 : begin + ap_NS_fsm = ap_ST_fsm_state2008; + end + ap_ST_fsm_state2008 : begin + ap_NS_fsm = ap_ST_fsm_state2009; + end + ap_ST_fsm_state2009 : begin + ap_NS_fsm = ap_ST_fsm_state2010; + end + ap_ST_fsm_state2010 : begin + ap_NS_fsm = ap_ST_fsm_state2011; + end + ap_ST_fsm_state2011 : begin + ap_NS_fsm = ap_ST_fsm_state2012; + end + ap_ST_fsm_state2012 : begin + ap_NS_fsm = ap_ST_fsm_state2013; + end + ap_ST_fsm_state2013 : begin + ap_NS_fsm = ap_ST_fsm_state2014; + end + ap_ST_fsm_state2014 : begin + if (((icmp_ln208_10_fu_113665_p2 == 1'd1) & (ap_ST_fsm_state2014 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1823; + end else if (((ap_ST_fsm_state2014 == ap_CS_fsm) & (or_ln223_38_fu_113743_p2 == 1'd0) & (icmp_ln208_10_fu_113665_p2 == 1'd0) & (or_ln223_19_reg_143411 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state2051; + end else begin + ap_NS_fsm = ap_ST_fsm_state2090; + end + end + ap_ST_fsm_state2015 : begin + ap_NS_fsm = ap_ST_fsm_state2016; + end + ap_ST_fsm_state2016 : begin + ap_NS_fsm = ap_ST_fsm_state2017; + end + ap_ST_fsm_state2017 : begin + ap_NS_fsm = ap_ST_fsm_state2018; + end + ap_ST_fsm_state2018 : begin + ap_NS_fsm = ap_ST_fsm_state2019; + end + ap_ST_fsm_state2019 : begin + ap_NS_fsm = ap_ST_fsm_state2020; + end + ap_ST_fsm_state2020 : begin + ap_NS_fsm = ap_ST_fsm_state2021; + end + ap_ST_fsm_state2021 : begin + ap_NS_fsm = ap_ST_fsm_state2022; + end + ap_ST_fsm_state2022 : begin + ap_NS_fsm = ap_ST_fsm_state2023; + end + ap_ST_fsm_state2023 : begin + ap_NS_fsm = ap_ST_fsm_state2024; + end + ap_ST_fsm_state2024 : begin + ap_NS_fsm = ap_ST_fsm_state2025; + end + ap_ST_fsm_state2025 : begin + ap_NS_fsm = ap_ST_fsm_state2026; + end + ap_ST_fsm_state2026 : begin + ap_NS_fsm = ap_ST_fsm_state2027; + end + ap_ST_fsm_state2027 : begin + ap_NS_fsm = ap_ST_fsm_state2028; + end + ap_ST_fsm_state2028 : begin + ap_NS_fsm = ap_ST_fsm_state2029; + end + ap_ST_fsm_state2029 : begin + ap_NS_fsm = ap_ST_fsm_state2030; + end + ap_ST_fsm_state2030 : begin + ap_NS_fsm = ap_ST_fsm_state2031; + end + ap_ST_fsm_state2031 : begin + ap_NS_fsm = ap_ST_fsm_state2032; + end + ap_ST_fsm_state2032 : begin + ap_NS_fsm = ap_ST_fsm_state2033; + end + ap_ST_fsm_state2033 : begin + ap_NS_fsm = ap_ST_fsm_state2034; + end + ap_ST_fsm_state2034 : begin + ap_NS_fsm = ap_ST_fsm_state2035; + end + ap_ST_fsm_state2035 : begin + ap_NS_fsm = ap_ST_fsm_state2036; + end + ap_ST_fsm_state2036 : begin + ap_NS_fsm = ap_ST_fsm_state2037; + end + ap_ST_fsm_state2037 : begin + ap_NS_fsm = ap_ST_fsm_state2038; + end + ap_ST_fsm_state2038 : begin + ap_NS_fsm = ap_ST_fsm_state2039; + end + ap_ST_fsm_state2039 : begin + ap_NS_fsm = ap_ST_fsm_state2040; + end + ap_ST_fsm_state2040 : begin + ap_NS_fsm = ap_ST_fsm_state2041; + end + ap_ST_fsm_state2041 : begin + ap_NS_fsm = ap_ST_fsm_state2042; + end + ap_ST_fsm_state2042 : begin + ap_NS_fsm = ap_ST_fsm_state2043; + end + ap_ST_fsm_state2043 : begin + ap_NS_fsm = ap_ST_fsm_state2044; + end + ap_ST_fsm_state2044 : begin + ap_NS_fsm = ap_ST_fsm_state2045; + end + ap_ST_fsm_state2045 : begin + ap_NS_fsm = ap_ST_fsm_state2046; + end + ap_ST_fsm_state2046 : begin + ap_NS_fsm = ap_ST_fsm_state2047; + end + ap_ST_fsm_state2047 : begin + ap_NS_fsm = ap_ST_fsm_state2048; + end + ap_ST_fsm_state2048 : begin + ap_NS_fsm = ap_ST_fsm_state2049; + end + ap_ST_fsm_state2049 : begin + ap_NS_fsm = ap_ST_fsm_state2050; + end + ap_ST_fsm_state2050 : begin + ap_NS_fsm = ap_ST_fsm_state2014; + end + ap_ST_fsm_state2051 : begin + ap_NS_fsm = ap_ST_fsm_state2052; + end + ap_ST_fsm_state2052 : begin + ap_NS_fsm = ap_ST_fsm_state2053; + end + ap_ST_fsm_state2053 : begin + ap_NS_fsm = ap_ST_fsm_state2054; + end + ap_ST_fsm_state2054 : begin + ap_NS_fsm = ap_ST_fsm_state2055; + end + ap_ST_fsm_state2055 : begin + ap_NS_fsm = ap_ST_fsm_state2056; + end + ap_ST_fsm_state2056 : begin + ap_NS_fsm = ap_ST_fsm_state2057; + end + ap_ST_fsm_state2057 : begin + ap_NS_fsm = ap_ST_fsm_state2058; + end + ap_ST_fsm_state2058 : begin + ap_NS_fsm = ap_ST_fsm_state2059; + end + ap_ST_fsm_state2059 : begin + ap_NS_fsm = ap_ST_fsm_state2060; + end + ap_ST_fsm_state2060 : begin + ap_NS_fsm = ap_ST_fsm_state2061; + end + ap_ST_fsm_state2061 : begin + ap_NS_fsm = ap_ST_fsm_state2062; + end + ap_ST_fsm_state2062 : begin + ap_NS_fsm = ap_ST_fsm_state2063; + end + ap_ST_fsm_state2063 : begin + ap_NS_fsm = ap_ST_fsm_state2064; + end + ap_ST_fsm_state2064 : begin + ap_NS_fsm = ap_ST_fsm_state2065; + end + ap_ST_fsm_state2065 : begin + ap_NS_fsm = ap_ST_fsm_state2066; + end + ap_ST_fsm_state2066 : begin + ap_NS_fsm = ap_ST_fsm_state2067; + end + ap_ST_fsm_state2067 : begin + ap_NS_fsm = ap_ST_fsm_state2068; + end + ap_ST_fsm_state2068 : begin + ap_NS_fsm = ap_ST_fsm_state2069; + end + ap_ST_fsm_state2069 : begin + ap_NS_fsm = ap_ST_fsm_state2070; + end + ap_ST_fsm_state2070 : begin + ap_NS_fsm = ap_ST_fsm_state2071; + end + ap_ST_fsm_state2071 : begin + ap_NS_fsm = ap_ST_fsm_state2072; + end + ap_ST_fsm_state2072 : begin + ap_NS_fsm = ap_ST_fsm_state2073; + end + ap_ST_fsm_state2073 : begin + ap_NS_fsm = ap_ST_fsm_state2074; + end + ap_ST_fsm_state2074 : begin + ap_NS_fsm = ap_ST_fsm_state2075; + end + ap_ST_fsm_state2075 : begin + ap_NS_fsm = ap_ST_fsm_state2076; + end + ap_ST_fsm_state2076 : begin + ap_NS_fsm = ap_ST_fsm_state2077; + end + ap_ST_fsm_state2077 : begin + ap_NS_fsm = ap_ST_fsm_state2078; + end + ap_ST_fsm_state2078 : begin + ap_NS_fsm = ap_ST_fsm_state2079; + end + ap_ST_fsm_state2079 : begin + ap_NS_fsm = ap_ST_fsm_state2080; + end + ap_ST_fsm_state2080 : begin + ap_NS_fsm = ap_ST_fsm_state2081; + end + ap_ST_fsm_state2081 : begin + ap_NS_fsm = ap_ST_fsm_state2082; + end + ap_ST_fsm_state2082 : begin + ap_NS_fsm = ap_ST_fsm_state2083; + end + ap_ST_fsm_state2083 : begin + ap_NS_fsm = ap_ST_fsm_state2084; + end + ap_ST_fsm_state2084 : begin + ap_NS_fsm = ap_ST_fsm_state2085; + end + ap_ST_fsm_state2085 : begin + ap_NS_fsm = ap_ST_fsm_state2086; + end + ap_ST_fsm_state2086 : begin + ap_NS_fsm = ap_ST_fsm_state2087; + end + ap_ST_fsm_state2087 : begin + ap_NS_fsm = ap_ST_fsm_state2088; + end + ap_ST_fsm_state2088 : begin + ap_NS_fsm = ap_ST_fsm_state2089; + end + ap_ST_fsm_state2089 : begin + ap_NS_fsm = ap_ST_fsm_state1975; + end + ap_ST_fsm_state2090 : begin + ap_NS_fsm = ap_ST_fsm_state2091; + end + ap_ST_fsm_state2091 : begin + ap_NS_fsm = ap_ST_fsm_state2092; + end + ap_ST_fsm_state2092 : begin + ap_NS_fsm = ap_ST_fsm_state2093; + end + ap_ST_fsm_state2093 : begin + ap_NS_fsm = ap_ST_fsm_state2094; + end + ap_ST_fsm_state2094 : begin + ap_NS_fsm = ap_ST_fsm_state2095; + end + ap_ST_fsm_state2095 : begin + ap_NS_fsm = ap_ST_fsm_state2096; + end + ap_ST_fsm_state2096 : begin + ap_NS_fsm = ap_ST_fsm_state2097; + end + ap_ST_fsm_state2097 : begin + ap_NS_fsm = ap_ST_fsm_state2098; + end + ap_ST_fsm_state2098 : begin + ap_NS_fsm = ap_ST_fsm_state2099; + end + ap_ST_fsm_state2099 : begin + ap_NS_fsm = ap_ST_fsm_state2100; + end + ap_ST_fsm_state2100 : begin + ap_NS_fsm = ap_ST_fsm_state2101; + end + ap_ST_fsm_state2101 : begin + ap_NS_fsm = ap_ST_fsm_state2102; + end + ap_ST_fsm_state2102 : begin + ap_NS_fsm = ap_ST_fsm_state2103; + end + ap_ST_fsm_state2103 : begin + ap_NS_fsm = ap_ST_fsm_state2104; + end + ap_ST_fsm_state2104 : begin + ap_NS_fsm = ap_ST_fsm_state2105; + end + ap_ST_fsm_state2105 : begin + ap_NS_fsm = ap_ST_fsm_state2106; + end + ap_ST_fsm_state2106 : begin + ap_NS_fsm = ap_ST_fsm_state2107; + end + ap_ST_fsm_state2107 : begin + ap_NS_fsm = ap_ST_fsm_state2108; + end + ap_ST_fsm_state2108 : begin + ap_NS_fsm = ap_ST_fsm_state2109; + end + ap_ST_fsm_state2109 : begin + ap_NS_fsm = ap_ST_fsm_state2110; + end + ap_ST_fsm_state2110 : begin + ap_NS_fsm = ap_ST_fsm_state2111; + end + ap_ST_fsm_state2111 : begin + ap_NS_fsm = ap_ST_fsm_state2112; + end + ap_ST_fsm_state2112 : begin + ap_NS_fsm = ap_ST_fsm_state2113; + end + ap_ST_fsm_state2113 : begin + ap_NS_fsm = ap_ST_fsm_state2114; + end + ap_ST_fsm_state2114 : begin + ap_NS_fsm = ap_ST_fsm_state2115; + end + ap_ST_fsm_state2115 : begin + ap_NS_fsm = ap_ST_fsm_state2116; + end + ap_ST_fsm_state2116 : begin + ap_NS_fsm = ap_ST_fsm_state2117; + end + ap_ST_fsm_state2117 : begin + ap_NS_fsm = ap_ST_fsm_state2118; + end + ap_ST_fsm_state2118 : begin + ap_NS_fsm = ap_ST_fsm_state2119; + end + ap_ST_fsm_state2119 : begin + ap_NS_fsm = ap_ST_fsm_state2120; + end + ap_ST_fsm_state2120 : begin + ap_NS_fsm = ap_ST_fsm_state2121; + end + ap_ST_fsm_state2121 : begin + ap_NS_fsm = ap_ST_fsm_state2122; + end + ap_ST_fsm_state2122 : begin + ap_NS_fsm = ap_ST_fsm_state2123; + end + ap_ST_fsm_state2123 : begin + ap_NS_fsm = ap_ST_fsm_state2124; + end + ap_ST_fsm_state2124 : begin + ap_NS_fsm = ap_ST_fsm_state2125; + end + ap_ST_fsm_state2125 : begin + ap_NS_fsm = ap_ST_fsm_state2089; + end + ap_ST_fsm_state2126 : begin + ap_NS_fsm = ap_ST_fsm_state2127; + end + ap_ST_fsm_state2127 : begin + ap_NS_fsm = ap_ST_fsm_state2128; + end + ap_ST_fsm_state2128 : begin + if (((ap_ST_fsm_state2128 == ap_CS_fsm) & (or_ln223_27_fu_114247_p2 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state2129; + end else begin + ap_NS_fsm = ap_ST_fsm_state2166; + end + end + ap_ST_fsm_state2129 : begin + ap_NS_fsm = ap_ST_fsm_state2130; + end + ap_ST_fsm_state2130 : begin + ap_NS_fsm = ap_ST_fsm_state2131; + end + ap_ST_fsm_state2131 : begin + ap_NS_fsm = ap_ST_fsm_state2132; + end + ap_ST_fsm_state2132 : begin + ap_NS_fsm = ap_ST_fsm_state2133; + end + ap_ST_fsm_state2133 : begin + ap_NS_fsm = ap_ST_fsm_state2134; + end + ap_ST_fsm_state2134 : begin + ap_NS_fsm = ap_ST_fsm_state2135; + end + ap_ST_fsm_state2135 : begin + ap_NS_fsm = ap_ST_fsm_state2136; + end + ap_ST_fsm_state2136 : begin + ap_NS_fsm = ap_ST_fsm_state2137; + end + ap_ST_fsm_state2137 : begin + ap_NS_fsm = ap_ST_fsm_state2138; + end + ap_ST_fsm_state2138 : begin + ap_NS_fsm = ap_ST_fsm_state2139; + end + ap_ST_fsm_state2139 : begin + ap_NS_fsm = ap_ST_fsm_state2140; + end + ap_ST_fsm_state2140 : begin + ap_NS_fsm = ap_ST_fsm_state2141; + end + ap_ST_fsm_state2141 : begin + ap_NS_fsm = ap_ST_fsm_state2142; + end + ap_ST_fsm_state2142 : begin + ap_NS_fsm = ap_ST_fsm_state2143; + end + ap_ST_fsm_state2143 : begin + ap_NS_fsm = ap_ST_fsm_state2144; + end + ap_ST_fsm_state2144 : begin + ap_NS_fsm = ap_ST_fsm_state2145; + end + ap_ST_fsm_state2145 : begin + ap_NS_fsm = ap_ST_fsm_state2146; + end + ap_ST_fsm_state2146 : begin + ap_NS_fsm = ap_ST_fsm_state2147; + end + ap_ST_fsm_state2147 : begin + ap_NS_fsm = ap_ST_fsm_state2148; + end + ap_ST_fsm_state2148 : begin + ap_NS_fsm = ap_ST_fsm_state2149; + end + ap_ST_fsm_state2149 : begin + ap_NS_fsm = ap_ST_fsm_state2150; + end + ap_ST_fsm_state2150 : begin + ap_NS_fsm = ap_ST_fsm_state2151; + end + ap_ST_fsm_state2151 : begin + ap_NS_fsm = ap_ST_fsm_state2152; + end + ap_ST_fsm_state2152 : begin + ap_NS_fsm = ap_ST_fsm_state2153; + end + ap_ST_fsm_state2153 : begin + ap_NS_fsm = ap_ST_fsm_state2154; + end + ap_ST_fsm_state2154 : begin + ap_NS_fsm = ap_ST_fsm_state2155; + end + ap_ST_fsm_state2155 : begin + ap_NS_fsm = ap_ST_fsm_state2156; + end + ap_ST_fsm_state2156 : begin + ap_NS_fsm = ap_ST_fsm_state2157; + end + ap_ST_fsm_state2157 : begin + ap_NS_fsm = ap_ST_fsm_state2158; + end + ap_ST_fsm_state2158 : begin + ap_NS_fsm = ap_ST_fsm_state2159; + end + ap_ST_fsm_state2159 : begin + ap_NS_fsm = ap_ST_fsm_state2160; + end + ap_ST_fsm_state2160 : begin + ap_NS_fsm = ap_ST_fsm_state2161; + end + ap_ST_fsm_state2161 : begin + ap_NS_fsm = ap_ST_fsm_state2162; + end + ap_ST_fsm_state2162 : begin + ap_NS_fsm = ap_ST_fsm_state2163; + end + ap_ST_fsm_state2163 : begin + ap_NS_fsm = ap_ST_fsm_state2164; + end + ap_ST_fsm_state2164 : begin + ap_NS_fsm = ap_ST_fsm_state2165; + end + ap_ST_fsm_state2165 : begin + if (((icmp_ln206_7_fu_114665_p2 == 1'd1) & (icmp_ln208_11_fu_114458_p2 == 1'd1) & (ap_ST_fsm_state2165 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1822; + end else if (((icmp_ln208_11_fu_114458_p2 == 1'd1) & (ap_ST_fsm_state2165 == ap_CS_fsm) & (icmp_ln206_7_fu_114665_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state2277; + end else if (((ap_ST_fsm_state2165 == ap_CS_fsm) & (or_ln223_40_fu_114536_p2 == 1'd0) & (icmp_ln208_11_fu_114458_p2 == 1'd0) & (or_ln223_23_reg_144249 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state2202; + end else begin + ap_NS_fsm = ap_ST_fsm_state2241; + end + end + ap_ST_fsm_state2166 : begin + ap_NS_fsm = ap_ST_fsm_state2167; + end + ap_ST_fsm_state2167 : begin + ap_NS_fsm = ap_ST_fsm_state2168; + end + ap_ST_fsm_state2168 : begin + ap_NS_fsm = ap_ST_fsm_state2169; + end + ap_ST_fsm_state2169 : begin + ap_NS_fsm = ap_ST_fsm_state2170; + end + ap_ST_fsm_state2170 : begin + ap_NS_fsm = ap_ST_fsm_state2171; + end + ap_ST_fsm_state2171 : begin + ap_NS_fsm = ap_ST_fsm_state2172; + end + ap_ST_fsm_state2172 : begin + ap_NS_fsm = ap_ST_fsm_state2173; + end + ap_ST_fsm_state2173 : begin + ap_NS_fsm = ap_ST_fsm_state2174; + end + ap_ST_fsm_state2174 : begin + ap_NS_fsm = ap_ST_fsm_state2175; + end + ap_ST_fsm_state2175 : begin + ap_NS_fsm = ap_ST_fsm_state2176; + end + ap_ST_fsm_state2176 : begin + ap_NS_fsm = ap_ST_fsm_state2177; + end + ap_ST_fsm_state2177 : begin + ap_NS_fsm = ap_ST_fsm_state2178; + end + ap_ST_fsm_state2178 : begin + ap_NS_fsm = ap_ST_fsm_state2179; + end + ap_ST_fsm_state2179 : begin + ap_NS_fsm = ap_ST_fsm_state2180; + end + ap_ST_fsm_state2180 : begin + ap_NS_fsm = ap_ST_fsm_state2181; + end + ap_ST_fsm_state2181 : begin + ap_NS_fsm = ap_ST_fsm_state2182; + end + ap_ST_fsm_state2182 : begin + ap_NS_fsm = ap_ST_fsm_state2183; + end + ap_ST_fsm_state2183 : begin + ap_NS_fsm = ap_ST_fsm_state2184; + end + ap_ST_fsm_state2184 : begin + ap_NS_fsm = ap_ST_fsm_state2185; + end + ap_ST_fsm_state2185 : begin + ap_NS_fsm = ap_ST_fsm_state2186; + end + ap_ST_fsm_state2186 : begin + ap_NS_fsm = ap_ST_fsm_state2187; + end + ap_ST_fsm_state2187 : begin + ap_NS_fsm = ap_ST_fsm_state2188; + end + ap_ST_fsm_state2188 : begin + ap_NS_fsm = ap_ST_fsm_state2189; + end + ap_ST_fsm_state2189 : begin + ap_NS_fsm = ap_ST_fsm_state2190; + end + ap_ST_fsm_state2190 : begin + ap_NS_fsm = ap_ST_fsm_state2191; + end + ap_ST_fsm_state2191 : begin + ap_NS_fsm = ap_ST_fsm_state2192; + end + ap_ST_fsm_state2192 : begin + ap_NS_fsm = ap_ST_fsm_state2193; + end + ap_ST_fsm_state2193 : begin + ap_NS_fsm = ap_ST_fsm_state2194; + end + ap_ST_fsm_state2194 : begin + ap_NS_fsm = ap_ST_fsm_state2195; + end + ap_ST_fsm_state2195 : begin + ap_NS_fsm = ap_ST_fsm_state2196; + end + ap_ST_fsm_state2196 : begin + ap_NS_fsm = ap_ST_fsm_state2197; + end + ap_ST_fsm_state2197 : begin + ap_NS_fsm = ap_ST_fsm_state2198; + end + ap_ST_fsm_state2198 : begin + ap_NS_fsm = ap_ST_fsm_state2199; + end + ap_ST_fsm_state2199 : begin + ap_NS_fsm = ap_ST_fsm_state2200; + end + ap_ST_fsm_state2200 : begin + ap_NS_fsm = ap_ST_fsm_state2201; + end + ap_ST_fsm_state2201 : begin + ap_NS_fsm = ap_ST_fsm_state2165; + end + ap_ST_fsm_state2202 : begin + ap_NS_fsm = ap_ST_fsm_state2203; + end + ap_ST_fsm_state2203 : begin + ap_NS_fsm = ap_ST_fsm_state2204; + end + ap_ST_fsm_state2204 : begin + ap_NS_fsm = ap_ST_fsm_state2205; + end + ap_ST_fsm_state2205 : begin + ap_NS_fsm = ap_ST_fsm_state2206; + end + ap_ST_fsm_state2206 : begin + ap_NS_fsm = ap_ST_fsm_state2207; + end + ap_ST_fsm_state2207 : begin + ap_NS_fsm = ap_ST_fsm_state2208; + end + ap_ST_fsm_state2208 : begin + ap_NS_fsm = ap_ST_fsm_state2209; + end + ap_ST_fsm_state2209 : begin + ap_NS_fsm = ap_ST_fsm_state2210; + end + ap_ST_fsm_state2210 : begin + ap_NS_fsm = ap_ST_fsm_state2211; + end + ap_ST_fsm_state2211 : begin + ap_NS_fsm = ap_ST_fsm_state2212; + end + ap_ST_fsm_state2212 : begin + ap_NS_fsm = ap_ST_fsm_state2213; + end + ap_ST_fsm_state2213 : begin + ap_NS_fsm = ap_ST_fsm_state2214; + end + ap_ST_fsm_state2214 : begin + ap_NS_fsm = ap_ST_fsm_state2215; + end + ap_ST_fsm_state2215 : begin + ap_NS_fsm = ap_ST_fsm_state2216; + end + ap_ST_fsm_state2216 : begin + ap_NS_fsm = ap_ST_fsm_state2217; + end + ap_ST_fsm_state2217 : begin + ap_NS_fsm = ap_ST_fsm_state2218; + end + ap_ST_fsm_state2218 : begin + ap_NS_fsm = ap_ST_fsm_state2219; + end + ap_ST_fsm_state2219 : begin + ap_NS_fsm = ap_ST_fsm_state2220; + end + ap_ST_fsm_state2220 : begin + ap_NS_fsm = ap_ST_fsm_state2221; + end + ap_ST_fsm_state2221 : begin + ap_NS_fsm = ap_ST_fsm_state2222; + end + ap_ST_fsm_state2222 : begin + ap_NS_fsm = ap_ST_fsm_state2223; + end + ap_ST_fsm_state2223 : begin + ap_NS_fsm = ap_ST_fsm_state2224; + end + ap_ST_fsm_state2224 : begin + ap_NS_fsm = ap_ST_fsm_state2225; + end + ap_ST_fsm_state2225 : begin + ap_NS_fsm = ap_ST_fsm_state2226; + end + ap_ST_fsm_state2226 : begin + ap_NS_fsm = ap_ST_fsm_state2227; + end + ap_ST_fsm_state2227 : begin + ap_NS_fsm = ap_ST_fsm_state2228; + end + ap_ST_fsm_state2228 : begin + ap_NS_fsm = ap_ST_fsm_state2229; + end + ap_ST_fsm_state2229 : begin + ap_NS_fsm = ap_ST_fsm_state2230; + end + ap_ST_fsm_state2230 : begin + ap_NS_fsm = ap_ST_fsm_state2231; + end + ap_ST_fsm_state2231 : begin + ap_NS_fsm = ap_ST_fsm_state2232; + end + ap_ST_fsm_state2232 : begin + ap_NS_fsm = ap_ST_fsm_state2233; + end + ap_ST_fsm_state2233 : begin + ap_NS_fsm = ap_ST_fsm_state2234; + end + ap_ST_fsm_state2234 : begin + ap_NS_fsm = ap_ST_fsm_state2235; + end + ap_ST_fsm_state2235 : begin + ap_NS_fsm = ap_ST_fsm_state2236; + end + ap_ST_fsm_state2236 : begin + ap_NS_fsm = ap_ST_fsm_state2237; + end + ap_ST_fsm_state2237 : begin + ap_NS_fsm = ap_ST_fsm_state2238; + end + ap_ST_fsm_state2238 : begin + ap_NS_fsm = ap_ST_fsm_state2239; + end + ap_ST_fsm_state2239 : begin + ap_NS_fsm = ap_ST_fsm_state2240; + end + ap_ST_fsm_state2240 : begin + ap_NS_fsm = ap_ST_fsm_state2128; + end + ap_ST_fsm_state2241 : begin + ap_NS_fsm = ap_ST_fsm_state2242; + end + ap_ST_fsm_state2242 : begin + ap_NS_fsm = ap_ST_fsm_state2243; + end + ap_ST_fsm_state2243 : begin + ap_NS_fsm = ap_ST_fsm_state2244; + end + ap_ST_fsm_state2244 : begin + ap_NS_fsm = ap_ST_fsm_state2245; + end + ap_ST_fsm_state2245 : begin + ap_NS_fsm = ap_ST_fsm_state2246; + end + ap_ST_fsm_state2246 : begin + ap_NS_fsm = ap_ST_fsm_state2247; + end + ap_ST_fsm_state2247 : begin + ap_NS_fsm = ap_ST_fsm_state2248; + end + ap_ST_fsm_state2248 : begin + ap_NS_fsm = ap_ST_fsm_state2249; + end + ap_ST_fsm_state2249 : begin + ap_NS_fsm = ap_ST_fsm_state2250; + end + ap_ST_fsm_state2250 : begin + ap_NS_fsm = ap_ST_fsm_state2251; + end + ap_ST_fsm_state2251 : begin + ap_NS_fsm = ap_ST_fsm_state2252; + end + ap_ST_fsm_state2252 : begin + ap_NS_fsm = ap_ST_fsm_state2253; + end + ap_ST_fsm_state2253 : begin + ap_NS_fsm = ap_ST_fsm_state2254; + end + ap_ST_fsm_state2254 : begin + ap_NS_fsm = ap_ST_fsm_state2255; + end + ap_ST_fsm_state2255 : begin + ap_NS_fsm = ap_ST_fsm_state2256; + end + ap_ST_fsm_state2256 : begin + ap_NS_fsm = ap_ST_fsm_state2257; + end + ap_ST_fsm_state2257 : begin + ap_NS_fsm = ap_ST_fsm_state2258; + end + ap_ST_fsm_state2258 : begin + ap_NS_fsm = ap_ST_fsm_state2259; + end + ap_ST_fsm_state2259 : begin + ap_NS_fsm = ap_ST_fsm_state2260; + end + ap_ST_fsm_state2260 : begin + ap_NS_fsm = ap_ST_fsm_state2261; + end + ap_ST_fsm_state2261 : begin + ap_NS_fsm = ap_ST_fsm_state2262; + end + ap_ST_fsm_state2262 : begin + ap_NS_fsm = ap_ST_fsm_state2263; + end + ap_ST_fsm_state2263 : begin + ap_NS_fsm = ap_ST_fsm_state2264; + end + ap_ST_fsm_state2264 : begin + ap_NS_fsm = ap_ST_fsm_state2265; + end + ap_ST_fsm_state2265 : begin + ap_NS_fsm = ap_ST_fsm_state2266; + end + ap_ST_fsm_state2266 : begin + ap_NS_fsm = ap_ST_fsm_state2267; + end + ap_ST_fsm_state2267 : begin + ap_NS_fsm = ap_ST_fsm_state2268; + end + ap_ST_fsm_state2268 : begin + ap_NS_fsm = ap_ST_fsm_state2269; + end + ap_ST_fsm_state2269 : begin + ap_NS_fsm = ap_ST_fsm_state2270; + end + ap_ST_fsm_state2270 : begin + ap_NS_fsm = ap_ST_fsm_state2271; + end + ap_ST_fsm_state2271 : begin + ap_NS_fsm = ap_ST_fsm_state2272; + end + ap_ST_fsm_state2272 : begin + ap_NS_fsm = ap_ST_fsm_state2273; + end + ap_ST_fsm_state2273 : begin + ap_NS_fsm = ap_ST_fsm_state2274; + end + ap_ST_fsm_state2274 : begin + ap_NS_fsm = ap_ST_fsm_state2275; + end + ap_ST_fsm_state2275 : begin + ap_NS_fsm = ap_ST_fsm_state2276; + end + ap_ST_fsm_state2276 : begin + ap_NS_fsm = ap_ST_fsm_state2240; + end + ap_ST_fsm_state2277 : begin + ap_NS_fsm = ap_ST_fsm_state2278; + end + ap_ST_fsm_state2278 : begin + if (((ap_ST_fsm_state2278 == ap_CS_fsm) & (or_ln223_43_fu_115048_p2 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state2279; + end else begin + ap_NS_fsm = ap_ST_fsm_state2316; + end + end + ap_ST_fsm_state2279 : begin + ap_NS_fsm = ap_ST_fsm_state2280; + end + ap_ST_fsm_state2280 : begin + ap_NS_fsm = ap_ST_fsm_state2281; + end + ap_ST_fsm_state2281 : begin + ap_NS_fsm = ap_ST_fsm_state2282; + end + ap_ST_fsm_state2282 : begin + ap_NS_fsm = ap_ST_fsm_state2283; + end + ap_ST_fsm_state2283 : begin + ap_NS_fsm = ap_ST_fsm_state2284; + end + ap_ST_fsm_state2284 : begin + ap_NS_fsm = ap_ST_fsm_state2285; + end + ap_ST_fsm_state2285 : begin + ap_NS_fsm = ap_ST_fsm_state2286; + end + ap_ST_fsm_state2286 : begin + ap_NS_fsm = ap_ST_fsm_state2287; + end + ap_ST_fsm_state2287 : begin + ap_NS_fsm = ap_ST_fsm_state2288; + end + ap_ST_fsm_state2288 : begin + ap_NS_fsm = ap_ST_fsm_state2289; + end + ap_ST_fsm_state2289 : begin + ap_NS_fsm = ap_ST_fsm_state2290; + end + ap_ST_fsm_state2290 : begin + ap_NS_fsm = ap_ST_fsm_state2291; + end + ap_ST_fsm_state2291 : begin + ap_NS_fsm = ap_ST_fsm_state2292; + end + ap_ST_fsm_state2292 : begin + ap_NS_fsm = ap_ST_fsm_state2293; + end + ap_ST_fsm_state2293 : begin + ap_NS_fsm = ap_ST_fsm_state2294; + end + ap_ST_fsm_state2294 : begin + ap_NS_fsm = ap_ST_fsm_state2295; + end + ap_ST_fsm_state2295 : begin + ap_NS_fsm = ap_ST_fsm_state2296; + end + ap_ST_fsm_state2296 : begin + ap_NS_fsm = ap_ST_fsm_state2297; + end + ap_ST_fsm_state2297 : begin + ap_NS_fsm = ap_ST_fsm_state2298; + end + ap_ST_fsm_state2298 : begin + ap_NS_fsm = ap_ST_fsm_state2299; + end + ap_ST_fsm_state2299 : begin + ap_NS_fsm = ap_ST_fsm_state2300; + end + ap_ST_fsm_state2300 : begin + ap_NS_fsm = ap_ST_fsm_state2301; + end + ap_ST_fsm_state2301 : begin + ap_NS_fsm = ap_ST_fsm_state2302; + end + ap_ST_fsm_state2302 : begin + ap_NS_fsm = ap_ST_fsm_state2303; + end + ap_ST_fsm_state2303 : begin + ap_NS_fsm = ap_ST_fsm_state2304; + end + ap_ST_fsm_state2304 : begin + ap_NS_fsm = ap_ST_fsm_state2305; + end + ap_ST_fsm_state2305 : begin + ap_NS_fsm = ap_ST_fsm_state2306; + end + ap_ST_fsm_state2306 : begin + ap_NS_fsm = ap_ST_fsm_state2307; + end + ap_ST_fsm_state2307 : begin + ap_NS_fsm = ap_ST_fsm_state2308; + end + ap_ST_fsm_state2308 : begin + ap_NS_fsm = ap_ST_fsm_state2309; + end + ap_ST_fsm_state2309 : begin + ap_NS_fsm = ap_ST_fsm_state2310; + end + ap_ST_fsm_state2310 : begin + ap_NS_fsm = ap_ST_fsm_state2311; + end + ap_ST_fsm_state2311 : begin + ap_NS_fsm = ap_ST_fsm_state2312; + end + ap_ST_fsm_state2312 : begin + ap_NS_fsm = ap_ST_fsm_state2313; + end + ap_ST_fsm_state2313 : begin + ap_NS_fsm = ap_ST_fsm_state2314; + end + ap_ST_fsm_state2314 : begin + ap_NS_fsm = ap_ST_fsm_state2315; + end + ap_ST_fsm_state2315 : begin + if (((icmp_ln208_15_fu_115259_p2 == 1'd1) & (ap_ST_fsm_state2315 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2126; + end else if (((ap_ST_fsm_state2315 == ap_CS_fsm) & (or_ln223_47_fu_115337_p2 == 1'd0) & (icmp_ln208_15_fu_115259_p2 == 1'd0) & (or_ln223_39_reg_145146 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state2352; + end else begin + ap_NS_fsm = ap_ST_fsm_state2389; + end + end + ap_ST_fsm_state2316 : begin + ap_NS_fsm = ap_ST_fsm_state2317; + end + ap_ST_fsm_state2317 : begin + ap_NS_fsm = ap_ST_fsm_state2318; + end + ap_ST_fsm_state2318 : begin + ap_NS_fsm = ap_ST_fsm_state2319; + end + ap_ST_fsm_state2319 : begin + ap_NS_fsm = ap_ST_fsm_state2320; + end + ap_ST_fsm_state2320 : begin + ap_NS_fsm = ap_ST_fsm_state2321; + end + ap_ST_fsm_state2321 : begin + ap_NS_fsm = ap_ST_fsm_state2322; + end + ap_ST_fsm_state2322 : begin + ap_NS_fsm = ap_ST_fsm_state2323; + end + ap_ST_fsm_state2323 : begin + ap_NS_fsm = ap_ST_fsm_state2324; + end + ap_ST_fsm_state2324 : begin + ap_NS_fsm = ap_ST_fsm_state2325; + end + ap_ST_fsm_state2325 : begin + ap_NS_fsm = ap_ST_fsm_state2326; + end + ap_ST_fsm_state2326 : begin + ap_NS_fsm = ap_ST_fsm_state2327; + end + ap_ST_fsm_state2327 : begin + ap_NS_fsm = ap_ST_fsm_state2328; + end + ap_ST_fsm_state2328 : begin + ap_NS_fsm = ap_ST_fsm_state2329; + end + ap_ST_fsm_state2329 : begin + ap_NS_fsm = ap_ST_fsm_state2330; + end + ap_ST_fsm_state2330 : begin + ap_NS_fsm = ap_ST_fsm_state2331; + end + ap_ST_fsm_state2331 : begin + ap_NS_fsm = ap_ST_fsm_state2332; + end + ap_ST_fsm_state2332 : begin + ap_NS_fsm = ap_ST_fsm_state2333; + end + ap_ST_fsm_state2333 : begin + ap_NS_fsm = ap_ST_fsm_state2334; + end + ap_ST_fsm_state2334 : begin + ap_NS_fsm = ap_ST_fsm_state2335; + end + ap_ST_fsm_state2335 : begin + ap_NS_fsm = ap_ST_fsm_state2336; + end + ap_ST_fsm_state2336 : begin + ap_NS_fsm = ap_ST_fsm_state2337; + end + ap_ST_fsm_state2337 : begin + ap_NS_fsm = ap_ST_fsm_state2338; + end + ap_ST_fsm_state2338 : begin + ap_NS_fsm = ap_ST_fsm_state2339; + end + ap_ST_fsm_state2339 : begin + ap_NS_fsm = ap_ST_fsm_state2340; + end + ap_ST_fsm_state2340 : begin + ap_NS_fsm = ap_ST_fsm_state2341; + end + ap_ST_fsm_state2341 : begin + ap_NS_fsm = ap_ST_fsm_state2342; + end + ap_ST_fsm_state2342 : begin + ap_NS_fsm = ap_ST_fsm_state2343; + end + ap_ST_fsm_state2343 : begin + ap_NS_fsm = ap_ST_fsm_state2344; + end + ap_ST_fsm_state2344 : begin + ap_NS_fsm = ap_ST_fsm_state2345; + end + ap_ST_fsm_state2345 : begin + ap_NS_fsm = ap_ST_fsm_state2346; + end + ap_ST_fsm_state2346 : begin + ap_NS_fsm = ap_ST_fsm_state2347; + end + ap_ST_fsm_state2347 : begin + ap_NS_fsm = ap_ST_fsm_state2348; + end + ap_ST_fsm_state2348 : begin + ap_NS_fsm = ap_ST_fsm_state2349; + end + ap_ST_fsm_state2349 : begin + ap_NS_fsm = ap_ST_fsm_state2350; + end + ap_ST_fsm_state2350 : begin + ap_NS_fsm = ap_ST_fsm_state2351; + end + ap_ST_fsm_state2351 : begin + ap_NS_fsm = ap_ST_fsm_state2315; + end + ap_ST_fsm_state2352 : begin + ap_NS_fsm = ap_ST_fsm_state2353; + end + ap_ST_fsm_state2353 : begin + ap_NS_fsm = ap_ST_fsm_state2354; + end + ap_ST_fsm_state2354 : begin + ap_NS_fsm = ap_ST_fsm_state2355; + end + ap_ST_fsm_state2355 : begin + ap_NS_fsm = ap_ST_fsm_state2356; + end + ap_ST_fsm_state2356 : begin + ap_NS_fsm = ap_ST_fsm_state2357; + end + ap_ST_fsm_state2357 : begin + ap_NS_fsm = ap_ST_fsm_state2358; + end + ap_ST_fsm_state2358 : begin + ap_NS_fsm = ap_ST_fsm_state2359; + end + ap_ST_fsm_state2359 : begin + ap_NS_fsm = ap_ST_fsm_state2360; + end + ap_ST_fsm_state2360 : begin + ap_NS_fsm = ap_ST_fsm_state2361; + end + ap_ST_fsm_state2361 : begin + ap_NS_fsm = ap_ST_fsm_state2362; + end + ap_ST_fsm_state2362 : begin + ap_NS_fsm = ap_ST_fsm_state2363; + end + ap_ST_fsm_state2363 : begin + ap_NS_fsm = ap_ST_fsm_state2364; + end + ap_ST_fsm_state2364 : begin + ap_NS_fsm = ap_ST_fsm_state2365; + end + ap_ST_fsm_state2365 : begin + ap_NS_fsm = ap_ST_fsm_state2366; + end + ap_ST_fsm_state2366 : begin + ap_NS_fsm = ap_ST_fsm_state2367; + end + ap_ST_fsm_state2367 : begin + ap_NS_fsm = ap_ST_fsm_state2368; + end + ap_ST_fsm_state2368 : begin + ap_NS_fsm = ap_ST_fsm_state2369; + end + ap_ST_fsm_state2369 : begin + ap_NS_fsm = ap_ST_fsm_state2370; + end + ap_ST_fsm_state2370 : begin + ap_NS_fsm = ap_ST_fsm_state2371; + end + ap_ST_fsm_state2371 : begin + ap_NS_fsm = ap_ST_fsm_state2372; + end + ap_ST_fsm_state2372 : begin + ap_NS_fsm = ap_ST_fsm_state2373; + end + ap_ST_fsm_state2373 : begin + ap_NS_fsm = ap_ST_fsm_state2374; + end + ap_ST_fsm_state2374 : begin + ap_NS_fsm = ap_ST_fsm_state2375; + end + ap_ST_fsm_state2375 : begin + ap_NS_fsm = ap_ST_fsm_state2376; + end + ap_ST_fsm_state2376 : begin + ap_NS_fsm = ap_ST_fsm_state2377; + end + ap_ST_fsm_state2377 : begin + ap_NS_fsm = ap_ST_fsm_state2378; + end + ap_ST_fsm_state2378 : begin + ap_NS_fsm = ap_ST_fsm_state2379; + end + ap_ST_fsm_state2379 : begin + ap_NS_fsm = ap_ST_fsm_state2380; + end + ap_ST_fsm_state2380 : begin + ap_NS_fsm = ap_ST_fsm_state2381; + end + ap_ST_fsm_state2381 : begin + ap_NS_fsm = ap_ST_fsm_state2382; + end + ap_ST_fsm_state2382 : begin + ap_NS_fsm = ap_ST_fsm_state2383; + end + ap_ST_fsm_state2383 : begin + ap_NS_fsm = ap_ST_fsm_state2384; + end + ap_ST_fsm_state2384 : begin + ap_NS_fsm = ap_ST_fsm_state2385; + end + ap_ST_fsm_state2385 : begin + ap_NS_fsm = ap_ST_fsm_state2386; + end + ap_ST_fsm_state2386 : begin + ap_NS_fsm = ap_ST_fsm_state2387; + end + ap_ST_fsm_state2387 : begin + ap_NS_fsm = ap_ST_fsm_state2388; + end + ap_ST_fsm_state2388 : begin + ap_NS_fsm = ap_ST_fsm_state2278; + end + ap_ST_fsm_state2389 : begin + ap_NS_fsm = ap_ST_fsm_state2390; + end + ap_ST_fsm_state2390 : begin + ap_NS_fsm = ap_ST_fsm_state2391; + end + ap_ST_fsm_state2391 : begin + ap_NS_fsm = ap_ST_fsm_state2392; + end + ap_ST_fsm_state2392 : begin + ap_NS_fsm = ap_ST_fsm_state2393; + end + ap_ST_fsm_state2393 : begin + ap_NS_fsm = ap_ST_fsm_state2394; + end + ap_ST_fsm_state2394 : begin + ap_NS_fsm = ap_ST_fsm_state2395; + end + ap_ST_fsm_state2395 : begin + ap_NS_fsm = ap_ST_fsm_state2396; + end + ap_ST_fsm_state2396 : begin + ap_NS_fsm = ap_ST_fsm_state2397; + end + ap_ST_fsm_state2397 : begin + ap_NS_fsm = ap_ST_fsm_state2398; + end + ap_ST_fsm_state2398 : begin + ap_NS_fsm = ap_ST_fsm_state2399; + end + ap_ST_fsm_state2399 : begin + ap_NS_fsm = ap_ST_fsm_state2400; + end + ap_ST_fsm_state2400 : begin + ap_NS_fsm = ap_ST_fsm_state2401; + end + ap_ST_fsm_state2401 : begin + ap_NS_fsm = ap_ST_fsm_state2402; + end + ap_ST_fsm_state2402 : begin + ap_NS_fsm = ap_ST_fsm_state2403; + end + ap_ST_fsm_state2403 : begin + ap_NS_fsm = ap_ST_fsm_state2404; + end + ap_ST_fsm_state2404 : begin + ap_NS_fsm = ap_ST_fsm_state2405; + end + ap_ST_fsm_state2405 : begin + ap_NS_fsm = ap_ST_fsm_state2406; + end + ap_ST_fsm_state2406 : begin + ap_NS_fsm = ap_ST_fsm_state2407; + end + ap_ST_fsm_state2407 : begin + ap_NS_fsm = ap_ST_fsm_state2408; + end + ap_ST_fsm_state2408 : begin + ap_NS_fsm = ap_ST_fsm_state2409; + end + ap_ST_fsm_state2409 : begin + ap_NS_fsm = ap_ST_fsm_state2410; + end + ap_ST_fsm_state2410 : begin + ap_NS_fsm = ap_ST_fsm_state2411; + end + ap_ST_fsm_state2411 : begin + ap_NS_fsm = ap_ST_fsm_state2412; + end + ap_ST_fsm_state2412 : begin + ap_NS_fsm = ap_ST_fsm_state2413; + end + ap_ST_fsm_state2413 : begin + ap_NS_fsm = ap_ST_fsm_state2414; + end + ap_ST_fsm_state2414 : begin + ap_NS_fsm = ap_ST_fsm_state2415; + end + ap_ST_fsm_state2415 : begin + ap_NS_fsm = ap_ST_fsm_state2416; + end + ap_ST_fsm_state2416 : begin + ap_NS_fsm = ap_ST_fsm_state2417; + end + ap_ST_fsm_state2417 : begin + ap_NS_fsm = ap_ST_fsm_state2418; + end + ap_ST_fsm_state2418 : begin + ap_NS_fsm = ap_ST_fsm_state2419; + end + ap_ST_fsm_state2419 : begin + ap_NS_fsm = ap_ST_fsm_state2420; + end + ap_ST_fsm_state2420 : begin + ap_NS_fsm = ap_ST_fsm_state2421; + end + ap_ST_fsm_state2421 : begin + ap_NS_fsm = ap_ST_fsm_state2422; + end + ap_ST_fsm_state2422 : begin + ap_NS_fsm = ap_ST_fsm_state2423; + end + ap_ST_fsm_state2423 : begin + ap_NS_fsm = ap_ST_fsm_state2424; + end + ap_ST_fsm_state2424 : begin + ap_NS_fsm = ap_ST_fsm_state2388; + end + ap_ST_fsm_state2425 : begin + if (((icmp_ln244_fu_115662_p2 == 1'd1) & (ap_ST_fsm_state2425 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2568; + end else begin + ap_NS_fsm = ap_ST_fsm_state2426; + end + end + ap_ST_fsm_state2426 : begin + if (((icmp_ln246_fu_115674_p2 == 1'd1) & (ap_ST_fsm_state2426 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2497; + end else begin + ap_NS_fsm = ap_ST_fsm_state2427; + end + end + ap_ST_fsm_state2427 : begin + if (((icmp_ln248_fu_115743_p2 == 1'd1) & (ap_ST_fsm_state2427 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2462; + end else begin + ap_NS_fsm = ap_ST_fsm_state2428; + end + end + ap_ST_fsm_state2428 : begin + if (((ap_ST_fsm_state2428 == ap_CS_fsm) & ((6'd1 == add_ln203_7_fu_116022_p2) | ((6'd3 == add_ln203_7_fu_116022_p2) | ((6'd5 == add_ln203_7_fu_116022_p2) | ((6'd7 == add_ln203_7_fu_116022_p2) | ((6'd9 == add_ln203_7_fu_116022_p2) | ((6'd11 == add_ln203_7_fu_116022_p2) | ((6'd13 == add_ln203_7_fu_116022_p2) | ((6'd15 == add_ln203_7_fu_116022_p2) | ((6'd17 == add_ln203_7_fu_116022_p2) | ((6'd19 == add_ln203_7_fu_116022_p2) | ((6'd21 == add_ln203_7_fu_116022_p2) | ((6'd23 == add_ln203_7_fu_116022_p2) | ((6'd25 == add_ln203_7_fu_116022_p2) | ((6'd27 == add_ln203_7_fu_116022_p2) | ((6'd29 == add_ln203_7_fu_116022_p2) | ((6'd31 == add_ln203_7_fu_116022_p2) | ((6'd33 == add_ln203_7_fu_116022_p2) | ((6'd35 == add_ln203_7_fu_116022_p2) | ((6'd37 == add_ln203_7_fu_116022_p2) | ((6'd39 == add_ln203_7_fu_116022_p2) | ((6'd41 == add_ln203_7_fu_116022_p2) | ((6'd43 == add_ln203_7_fu_116022_p2) | ((6'd45 == add_ln203_7_fu_116022_p2) | ((6'd47 == add_ln203_7_fu_116022_p2) | ((6'd49 == add_ln203_7_fu_116022_p2) | ((6'd51 == add_ln203_7_fu_116022_p2) | ((6'd53 == add_ln203_7_fu_116022_p2) | ((6'd55 == add_ln203_7_fu_116022_p2) | ((6'd57 == add_ln203_7_fu_116022_p2) | ((6'd61 == add_ln203_7_fu_116022_p2) | (6'd59 == add_ln203_7_fu_116022_p2))))))))))))))))))))))))))))))))) begin + ap_NS_fsm = ap_ST_fsm_state2461; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & ((6'd63 == add_ln203_7_fu_116022_p2) | (6'd0 == add_ln203_7_fu_116022_p2)))) begin + ap_NS_fsm = ap_ST_fsm_state2460; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd2 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2459; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd4 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2458; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd6 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2457; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd8 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2456; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd10 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2455; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd12 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2454; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd14 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2453; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd16 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2452; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd18 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2451; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd20 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2450; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd22 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2449; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd24 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2448; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd26 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2447; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd28 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2446; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd30 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2445; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd32 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2444; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd34 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2443; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd36 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2442; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd38 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2441; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd40 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2440; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd42 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2439; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd44 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2438; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd46 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2437; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd48 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2436; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd50 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2435; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd52 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2434; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd54 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2433; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd56 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2432; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd58 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2431; + end else if (((ap_ST_fsm_state2428 == ap_CS_fsm) & (6'd60 == add_ln203_7_fu_116022_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2430; + end else begin + ap_NS_fsm = ap_ST_fsm_state2429; + end + end + ap_ST_fsm_state2429 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2430 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2431 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2432 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2433 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2434 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2435 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2436 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2437 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2438 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2439 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2440 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2441 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2442 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2443 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2444 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2445 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2446 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2447 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2448 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2449 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2450 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2451 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2452 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2453 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2454 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2455 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2456 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2457 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2458 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2459 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2460 : begin + ap_NS_fsm = ap_ST_fsm_state2461; + end + ap_ST_fsm_state2461 : begin + ap_NS_fsm = ap_ST_fsm_state2427; + end + ap_ST_fsm_state2462 : begin + if (((icmp_ln248_2_fu_116119_p2 == 1'd1) & (ap_ST_fsm_state2462 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2426; + end else begin + ap_NS_fsm = ap_ST_fsm_state2463; + end + end + ap_ST_fsm_state2463 : begin + if (((ap_ST_fsm_state2463 == ap_CS_fsm) & ((6'd1 == add_ln203_10_fu_116355_p2) | ((6'd3 == add_ln203_10_fu_116355_p2) | ((6'd5 == add_ln203_10_fu_116355_p2) | ((6'd7 == add_ln203_10_fu_116355_p2) | ((6'd9 == add_ln203_10_fu_116355_p2) | ((6'd11 == add_ln203_10_fu_116355_p2) | ((6'd13 == add_ln203_10_fu_116355_p2) | ((6'd15 == add_ln203_10_fu_116355_p2) | ((6'd17 == add_ln203_10_fu_116355_p2) | ((6'd19 == add_ln203_10_fu_116355_p2) | ((6'd21 == add_ln203_10_fu_116355_p2) | ((6'd23 == add_ln203_10_fu_116355_p2) | ((6'd25 == add_ln203_10_fu_116355_p2) | ((6'd27 == add_ln203_10_fu_116355_p2) | ((6'd29 == add_ln203_10_fu_116355_p2) | ((6'd31 == add_ln203_10_fu_116355_p2) | ((6'd33 == add_ln203_10_fu_116355_p2) | ((6'd35 == add_ln203_10_fu_116355_p2) | ((6'd37 == add_ln203_10_fu_116355_p2) | ((6'd39 == add_ln203_10_fu_116355_p2) | ((6'd41 == add_ln203_10_fu_116355_p2) | ((6'd43 == add_ln203_10_fu_116355_p2) | ((6'd45 == add_ln203_10_fu_116355_p2) | ((6'd47 == add_ln203_10_fu_116355_p2) | ((6'd49 == add_ln203_10_fu_116355_p2) | ((6'd51 == add_ln203_10_fu_116355_p2) | ((6'd53 == add_ln203_10_fu_116355_p2) | ((6'd55 == add_ln203_10_fu_116355_p2) | ((6'd57 == add_ln203_10_fu_116355_p2) | ((6'd61 == add_ln203_10_fu_116355_p2) | (6'd59 == add_ln203_10_fu_116355_p2))))))))))))))))))))))))))))))))) begin + ap_NS_fsm = ap_ST_fsm_state2496; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & ((6'd63 == add_ln203_10_fu_116355_p2) | (6'd0 == add_ln203_10_fu_116355_p2)))) begin + ap_NS_fsm = ap_ST_fsm_state2495; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd2 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2494; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd4 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2493; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd6 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2492; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd8 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2491; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd10 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2490; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd12 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2489; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd14 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2488; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd16 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2487; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd18 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2486; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd20 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2485; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd22 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2484; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd24 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2483; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd26 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2482; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd28 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2481; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd30 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2480; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd32 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2479; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd34 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2478; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd36 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2477; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd38 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2476; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd40 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2475; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd42 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2474; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd44 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2473; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd46 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2472; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd48 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2471; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd50 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2470; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd52 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2469; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd54 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2468; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd56 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2467; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd58 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2466; + end else if (((ap_ST_fsm_state2463 == ap_CS_fsm) & (6'd60 == add_ln203_10_fu_116355_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2465; + end else begin + ap_NS_fsm = ap_ST_fsm_state2464; + end + end + ap_ST_fsm_state2464 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2465 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2466 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2467 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2468 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2469 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2470 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2471 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2472 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2473 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2474 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2475 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2476 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2477 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2478 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2479 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2480 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2481 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2482 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2483 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2484 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2485 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2486 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2487 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2488 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2489 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2490 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2491 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2492 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2493 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2494 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2495 : begin + ap_NS_fsm = ap_ST_fsm_state2496; + end + ap_ST_fsm_state2496 : begin + ap_NS_fsm = ap_ST_fsm_state2462; + end + ap_ST_fsm_state2497 : begin + if (((icmp_ln246_1_fu_116448_p2 == 1'd1) & (ap_ST_fsm_state2497 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2425; + end else begin + ap_NS_fsm = ap_ST_fsm_state2498; + end + end + ap_ST_fsm_state2498 : begin + if (((icmp_ln248_1_fu_116507_p2 == 1'd1) & (ap_ST_fsm_state2498 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2533; + end else begin + ap_NS_fsm = ap_ST_fsm_state2499; + end + end + ap_ST_fsm_state2499 : begin + if (((ap_ST_fsm_state2499 == ap_CS_fsm) & ((6'd1 == add_ln203_9_fu_116786_p2) | ((6'd3 == add_ln203_9_fu_116786_p2) | ((6'd5 == add_ln203_9_fu_116786_p2) | ((6'd7 == add_ln203_9_fu_116786_p2) | ((6'd9 == add_ln203_9_fu_116786_p2) | ((6'd11 == add_ln203_9_fu_116786_p2) | ((6'd13 == add_ln203_9_fu_116786_p2) | ((6'd15 == add_ln203_9_fu_116786_p2) | ((6'd17 == add_ln203_9_fu_116786_p2) | ((6'd19 == add_ln203_9_fu_116786_p2) | ((6'd21 == add_ln203_9_fu_116786_p2) | ((6'd23 == add_ln203_9_fu_116786_p2) | ((6'd25 == add_ln203_9_fu_116786_p2) | ((6'd27 == add_ln203_9_fu_116786_p2) | ((6'd29 == add_ln203_9_fu_116786_p2) | ((6'd31 == add_ln203_9_fu_116786_p2) | ((6'd33 == add_ln203_9_fu_116786_p2) | ((6'd35 == add_ln203_9_fu_116786_p2) | ((6'd37 == add_ln203_9_fu_116786_p2) | ((6'd39 == add_ln203_9_fu_116786_p2) | ((6'd41 == add_ln203_9_fu_116786_p2) | ((6'd43 == add_ln203_9_fu_116786_p2) | ((6'd45 == add_ln203_9_fu_116786_p2) | ((6'd47 == add_ln203_9_fu_116786_p2) | ((6'd49 == add_ln203_9_fu_116786_p2) | ((6'd51 == add_ln203_9_fu_116786_p2) | ((6'd53 == add_ln203_9_fu_116786_p2) | ((6'd55 == add_ln203_9_fu_116786_p2) | ((6'd57 == add_ln203_9_fu_116786_p2) | ((6'd61 == add_ln203_9_fu_116786_p2) | (6'd59 == add_ln203_9_fu_116786_p2))))))))))))))))))))))))))))))))) begin + ap_NS_fsm = ap_ST_fsm_state2532; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & ((6'd63 == add_ln203_9_fu_116786_p2) | (6'd0 == add_ln203_9_fu_116786_p2)))) begin + ap_NS_fsm = ap_ST_fsm_state2531; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd2 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2530; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd4 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2529; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd6 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2528; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd8 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2527; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd10 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2526; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd12 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2525; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd14 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2524; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd16 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2523; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd18 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2522; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd20 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2521; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd22 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2520; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd24 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2519; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd26 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2518; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd28 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2517; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd30 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2516; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd32 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2515; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd34 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2514; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd36 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2513; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd38 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2512; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd40 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2511; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd42 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2510; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd44 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2509; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd46 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2508; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd48 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2507; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd50 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2506; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd52 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2505; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd54 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2504; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd56 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2503; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd58 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2502; + end else if (((ap_ST_fsm_state2499 == ap_CS_fsm) & (6'd60 == add_ln203_9_fu_116786_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2501; + end else begin + ap_NS_fsm = ap_ST_fsm_state2500; + end + end + ap_ST_fsm_state2500 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2501 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2502 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2503 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2504 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2505 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2506 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2507 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2508 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2509 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2510 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2511 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2512 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2513 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2514 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2515 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2516 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2517 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2518 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2519 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2520 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2521 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2522 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2523 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2524 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2525 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2526 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2527 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2528 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2529 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2530 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2531 : begin + ap_NS_fsm = ap_ST_fsm_state2532; + end + ap_ST_fsm_state2532 : begin + ap_NS_fsm = ap_ST_fsm_state2498; + end + ap_ST_fsm_state2533 : begin + if (((icmp_ln248_3_fu_116883_p2 == 1'd1) & (ap_ST_fsm_state2533 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2497; + end else begin + ap_NS_fsm = ap_ST_fsm_state2534; + end + end + ap_ST_fsm_state2534 : begin + if (((ap_ST_fsm_state2534 == ap_CS_fsm) & ((6'd1 == add_ln203_11_fu_117119_p2) | ((6'd3 == add_ln203_11_fu_117119_p2) | ((6'd5 == add_ln203_11_fu_117119_p2) | ((6'd7 == add_ln203_11_fu_117119_p2) | ((6'd9 == add_ln203_11_fu_117119_p2) | ((6'd11 == add_ln203_11_fu_117119_p2) | ((6'd13 == add_ln203_11_fu_117119_p2) | ((6'd15 == add_ln203_11_fu_117119_p2) | ((6'd17 == add_ln203_11_fu_117119_p2) | ((6'd19 == add_ln203_11_fu_117119_p2) | ((6'd21 == add_ln203_11_fu_117119_p2) | ((6'd23 == add_ln203_11_fu_117119_p2) | ((6'd25 == add_ln203_11_fu_117119_p2) | ((6'd27 == add_ln203_11_fu_117119_p2) | ((6'd29 == add_ln203_11_fu_117119_p2) | ((6'd31 == add_ln203_11_fu_117119_p2) | ((6'd33 == add_ln203_11_fu_117119_p2) | ((6'd35 == add_ln203_11_fu_117119_p2) | ((6'd37 == add_ln203_11_fu_117119_p2) | ((6'd39 == add_ln203_11_fu_117119_p2) | ((6'd41 == add_ln203_11_fu_117119_p2) | ((6'd43 == add_ln203_11_fu_117119_p2) | ((6'd45 == add_ln203_11_fu_117119_p2) | ((6'd47 == add_ln203_11_fu_117119_p2) | ((6'd49 == add_ln203_11_fu_117119_p2) | ((6'd51 == add_ln203_11_fu_117119_p2) | ((6'd53 == add_ln203_11_fu_117119_p2) | ((6'd55 == add_ln203_11_fu_117119_p2) | ((6'd57 == add_ln203_11_fu_117119_p2) | ((6'd61 == add_ln203_11_fu_117119_p2) | (6'd59 == add_ln203_11_fu_117119_p2))))))))))))))))))))))))))))))))) begin + ap_NS_fsm = ap_ST_fsm_state2567; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & ((6'd63 == add_ln203_11_fu_117119_p2) | (6'd0 == add_ln203_11_fu_117119_p2)))) begin + ap_NS_fsm = ap_ST_fsm_state2566; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd2 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2565; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd4 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2564; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd6 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2563; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd8 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2562; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd10 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2561; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd12 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2560; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd14 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2559; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd16 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2558; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd18 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2557; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd20 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2556; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd22 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2555; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd24 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2554; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd26 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2553; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd28 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2552; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd30 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2551; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd32 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2550; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd34 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2549; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd36 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2548; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd38 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2547; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd40 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2546; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd42 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2545; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd44 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2544; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd46 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2543; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd48 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2542; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd50 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2541; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd52 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2540; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd54 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2539; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd56 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2538; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd58 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2537; + end else if (((ap_ST_fsm_state2534 == ap_CS_fsm) & (6'd60 == add_ln203_11_fu_117119_p2))) begin + ap_NS_fsm = ap_ST_fsm_state2536; + end else begin + ap_NS_fsm = ap_ST_fsm_state2535; + end + end + ap_ST_fsm_state2535 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2536 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2537 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2538 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2539 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2540 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2541 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2542 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2543 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2544 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2545 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2546 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2547 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2548 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2549 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2550 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2551 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2552 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2553 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2554 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2555 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2556 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2557 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2558 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2559 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2560 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2561 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2562 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2563 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2564 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2565 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2566 : begin + ap_NS_fsm = ap_ST_fsm_state2567; + end + ap_ST_fsm_state2567 : begin + ap_NS_fsm = ap_ST_fsm_state2533; + end + ap_ST_fsm_state2568 : begin + if (((ap_ST_fsm_state2568 == ap_CS_fsm) & (icmp_ln257_fu_117220_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state2569; + end else begin + ap_NS_fsm = ap_ST_fsm_state5027; + end + end + ap_ST_fsm_state2569 : begin + if (((icmp_ln259_fu_117242_p2 == 1'd1) & (ap_ST_fsm_state2569 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3800; + end else begin + ap_NS_fsm = ap_ST_fsm_state2570; + end + end + ap_ST_fsm_state2570 : begin + if (((icmp_ln261_fu_117325_p2 == 1'd1) & (ap_ST_fsm_state2570 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3186; + end else begin + ap_NS_fsm = ap_ST_fsm_state2571; + end + end + ap_ST_fsm_state2571 : begin + if (((icmp_ln264_fu_117484_p2 == 1'd1) & (ap_ST_fsm_state2571 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2879; + end else begin + ap_NS_fsm = ap_ST_fsm_state2572; + end + end + ap_ST_fsm_state2572 : begin + ap_NS_fsm = ap_ST_fsm_state2573; + end + ap_ST_fsm_state2573 : begin + ap_NS_fsm = ap_ST_fsm_state2574; + end + ap_ST_fsm_state2574 : begin + ap_NS_fsm = ap_ST_fsm_state2575; + end + ap_ST_fsm_state2575 : begin + ap_NS_fsm = ap_ST_fsm_state2576; + end + ap_ST_fsm_state2576 : begin + ap_NS_fsm = ap_ST_fsm_state2577; + end + ap_ST_fsm_state2577 : begin + ap_NS_fsm = ap_ST_fsm_state2578; + end + ap_ST_fsm_state2578 : begin + ap_NS_fsm = ap_ST_fsm_state2579; + end + ap_ST_fsm_state2579 : begin + ap_NS_fsm = ap_ST_fsm_state2580; + end + ap_ST_fsm_state2580 : begin + ap_NS_fsm = ap_ST_fsm_state2581; + end + ap_ST_fsm_state2581 : begin + ap_NS_fsm = ap_ST_fsm_state2582; + end + ap_ST_fsm_state2582 : begin + ap_NS_fsm = ap_ST_fsm_state2583; + end + ap_ST_fsm_state2583 : begin + ap_NS_fsm = ap_ST_fsm_state2584; + end + ap_ST_fsm_state2584 : begin + ap_NS_fsm = ap_ST_fsm_state2585; + end + ap_ST_fsm_state2585 : begin + ap_NS_fsm = ap_ST_fsm_state2586; + end + ap_ST_fsm_state2586 : begin + ap_NS_fsm = ap_ST_fsm_state2587; + end + ap_ST_fsm_state2587 : begin + ap_NS_fsm = ap_ST_fsm_state2588; + end + ap_ST_fsm_state2588 : begin + ap_NS_fsm = ap_ST_fsm_state2589; + end + ap_ST_fsm_state2589 : begin + ap_NS_fsm = ap_ST_fsm_state2590; + end + ap_ST_fsm_state2590 : begin + ap_NS_fsm = ap_ST_fsm_state2591; + end + ap_ST_fsm_state2591 : begin + ap_NS_fsm = ap_ST_fsm_state2592; + end + ap_ST_fsm_state2592 : begin + ap_NS_fsm = ap_ST_fsm_state2593; + end + ap_ST_fsm_state2593 : begin + ap_NS_fsm = ap_ST_fsm_state2594; + end + ap_ST_fsm_state2594 : begin + ap_NS_fsm = ap_ST_fsm_state2595; + end + ap_ST_fsm_state2595 : begin + ap_NS_fsm = ap_ST_fsm_state2596; + end + ap_ST_fsm_state2596 : begin + ap_NS_fsm = ap_ST_fsm_state2597; + end + ap_ST_fsm_state2597 : begin + ap_NS_fsm = ap_ST_fsm_state2598; + end + ap_ST_fsm_state2598 : begin + ap_NS_fsm = ap_ST_fsm_state2599; + end + ap_ST_fsm_state2599 : begin + ap_NS_fsm = ap_ST_fsm_state2600; + end + ap_ST_fsm_state2600 : begin + ap_NS_fsm = ap_ST_fsm_state2601; + end + ap_ST_fsm_state2601 : begin + ap_NS_fsm = ap_ST_fsm_state2602; + end + ap_ST_fsm_state2602 : begin + ap_NS_fsm = ap_ST_fsm_state2603; + end + ap_ST_fsm_state2603 : begin + ap_NS_fsm = ap_ST_fsm_state2604; + end + ap_ST_fsm_state2604 : begin + ap_NS_fsm = ap_ST_fsm_state2605; + end + ap_ST_fsm_state2605 : begin + ap_NS_fsm = ap_ST_fsm_state2606; + end + ap_ST_fsm_state2606 : begin + ap_NS_fsm = ap_ST_fsm_state2607; + end + ap_ST_fsm_state2607 : begin + ap_NS_fsm = ap_ST_fsm_state2608; + end + ap_ST_fsm_state2608 : begin + ap_NS_fsm = ap_ST_fsm_state2609; + end + ap_ST_fsm_state2609 : begin + ap_NS_fsm = ap_ST_fsm_state2610; + end + ap_ST_fsm_state2610 : begin + ap_NS_fsm = ap_ST_fsm_state2611; + end + ap_ST_fsm_state2611 : begin + ap_NS_fsm = ap_ST_fsm_state2612; + end + ap_ST_fsm_state2612 : begin + if (((icmp_ln266_fu_117841_p2 == 1'd1) & (icmp_ln268_fu_117818_p2 == 1'd1) & (ap_ST_fsm_state2612 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2727; + end else if (((icmp_ln268_fu_117818_p2 == 1'd1) & (ap_ST_fsm_state2612 == ap_CS_fsm) & (icmp_ln266_fu_117841_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state2650; + end else begin + ap_NS_fsm = ap_ST_fsm_state2613; + end + end + ap_ST_fsm_state2613 : begin + ap_NS_fsm = ap_ST_fsm_state2614; + end + ap_ST_fsm_state2614 : begin + ap_NS_fsm = ap_ST_fsm_state2615; + end + ap_ST_fsm_state2615 : begin + ap_NS_fsm = ap_ST_fsm_state2616; + end + ap_ST_fsm_state2616 : begin + ap_NS_fsm = ap_ST_fsm_state2617; + end + ap_ST_fsm_state2617 : begin + ap_NS_fsm = ap_ST_fsm_state2618; + end + ap_ST_fsm_state2618 : begin + ap_NS_fsm = ap_ST_fsm_state2619; + end + ap_ST_fsm_state2619 : begin + ap_NS_fsm = ap_ST_fsm_state2620; + end + ap_ST_fsm_state2620 : begin + ap_NS_fsm = ap_ST_fsm_state2621; + end + ap_ST_fsm_state2621 : begin + ap_NS_fsm = ap_ST_fsm_state2622; + end + ap_ST_fsm_state2622 : begin + ap_NS_fsm = ap_ST_fsm_state2623; + end + ap_ST_fsm_state2623 : begin + ap_NS_fsm = ap_ST_fsm_state2624; + end + ap_ST_fsm_state2624 : begin + ap_NS_fsm = ap_ST_fsm_state2625; + end + ap_ST_fsm_state2625 : begin + ap_NS_fsm = ap_ST_fsm_state2626; + end + ap_ST_fsm_state2626 : begin + ap_NS_fsm = ap_ST_fsm_state2627; + end + ap_ST_fsm_state2627 : begin + ap_NS_fsm = ap_ST_fsm_state2628; + end + ap_ST_fsm_state2628 : begin + ap_NS_fsm = ap_ST_fsm_state2629; + end + ap_ST_fsm_state2629 : begin + ap_NS_fsm = ap_ST_fsm_state2630; + end + ap_ST_fsm_state2630 : begin + ap_NS_fsm = ap_ST_fsm_state2631; + end + ap_ST_fsm_state2631 : begin + ap_NS_fsm = ap_ST_fsm_state2632; + end + ap_ST_fsm_state2632 : begin + ap_NS_fsm = ap_ST_fsm_state2633; + end + ap_ST_fsm_state2633 : begin + ap_NS_fsm = ap_ST_fsm_state2634; + end + ap_ST_fsm_state2634 : begin + ap_NS_fsm = ap_ST_fsm_state2635; + end + ap_ST_fsm_state2635 : begin + ap_NS_fsm = ap_ST_fsm_state2636; + end + ap_ST_fsm_state2636 : begin + ap_NS_fsm = ap_ST_fsm_state2637; + end + ap_ST_fsm_state2637 : begin + ap_NS_fsm = ap_ST_fsm_state2638; + end + ap_ST_fsm_state2638 : begin + ap_NS_fsm = ap_ST_fsm_state2639; + end + ap_ST_fsm_state2639 : begin + ap_NS_fsm = ap_ST_fsm_state2640; + end + ap_ST_fsm_state2640 : begin + ap_NS_fsm = ap_ST_fsm_state2641; + end + ap_ST_fsm_state2641 : begin + ap_NS_fsm = ap_ST_fsm_state2642; + end + ap_ST_fsm_state2642 : begin + ap_NS_fsm = ap_ST_fsm_state2643; + end + ap_ST_fsm_state2643 : begin + ap_NS_fsm = ap_ST_fsm_state2644; + end + ap_ST_fsm_state2644 : begin + ap_NS_fsm = ap_ST_fsm_state2645; + end + ap_ST_fsm_state2645 : begin + ap_NS_fsm = ap_ST_fsm_state2646; + end + ap_ST_fsm_state2646 : begin + ap_NS_fsm = ap_ST_fsm_state2647; + end + ap_ST_fsm_state2647 : begin + ap_NS_fsm = ap_ST_fsm_state2648; + end + ap_ST_fsm_state2648 : begin + ap_NS_fsm = ap_ST_fsm_state2649; + end + ap_ST_fsm_state2649 : begin + ap_NS_fsm = ap_ST_fsm_state2573; + end + ap_ST_fsm_state2650 : begin + ap_NS_fsm = ap_ST_fsm_state2651; + end + ap_ST_fsm_state2651 : begin + ap_NS_fsm = ap_ST_fsm_state2652; + end + ap_ST_fsm_state2652 : begin + ap_NS_fsm = ap_ST_fsm_state2653; + end + ap_ST_fsm_state2653 : begin + ap_NS_fsm = ap_ST_fsm_state2654; + end + ap_ST_fsm_state2654 : begin + ap_NS_fsm = ap_ST_fsm_state2655; + end + ap_ST_fsm_state2655 : begin + ap_NS_fsm = ap_ST_fsm_state2656; + end + ap_ST_fsm_state2656 : begin + ap_NS_fsm = ap_ST_fsm_state2657; + end + ap_ST_fsm_state2657 : begin + ap_NS_fsm = ap_ST_fsm_state2658; + end + ap_ST_fsm_state2658 : begin + ap_NS_fsm = ap_ST_fsm_state2659; + end + ap_ST_fsm_state2659 : begin + ap_NS_fsm = ap_ST_fsm_state2660; + end + ap_ST_fsm_state2660 : begin + ap_NS_fsm = ap_ST_fsm_state2661; + end + ap_ST_fsm_state2661 : begin + ap_NS_fsm = ap_ST_fsm_state2662; + end + ap_ST_fsm_state2662 : begin + ap_NS_fsm = ap_ST_fsm_state2663; + end + ap_ST_fsm_state2663 : begin + ap_NS_fsm = ap_ST_fsm_state2664; + end + ap_ST_fsm_state2664 : begin + ap_NS_fsm = ap_ST_fsm_state2665; + end + ap_ST_fsm_state2665 : begin + ap_NS_fsm = ap_ST_fsm_state2666; + end + ap_ST_fsm_state2666 : begin + ap_NS_fsm = ap_ST_fsm_state2667; + end + ap_ST_fsm_state2667 : begin + ap_NS_fsm = ap_ST_fsm_state2668; + end + ap_ST_fsm_state2668 : begin + ap_NS_fsm = ap_ST_fsm_state2669; + end + ap_ST_fsm_state2669 : begin + ap_NS_fsm = ap_ST_fsm_state2670; + end + ap_ST_fsm_state2670 : begin + ap_NS_fsm = ap_ST_fsm_state2671; + end + ap_ST_fsm_state2671 : begin + ap_NS_fsm = ap_ST_fsm_state2672; + end + ap_ST_fsm_state2672 : begin + ap_NS_fsm = ap_ST_fsm_state2673; + end + ap_ST_fsm_state2673 : begin + ap_NS_fsm = ap_ST_fsm_state2674; + end + ap_ST_fsm_state2674 : begin + ap_NS_fsm = ap_ST_fsm_state2675; + end + ap_ST_fsm_state2675 : begin + ap_NS_fsm = ap_ST_fsm_state2676; + end + ap_ST_fsm_state2676 : begin + ap_NS_fsm = ap_ST_fsm_state2677; + end + ap_ST_fsm_state2677 : begin + ap_NS_fsm = ap_ST_fsm_state2678; + end + ap_ST_fsm_state2678 : begin + ap_NS_fsm = ap_ST_fsm_state2679; + end + ap_ST_fsm_state2679 : begin + ap_NS_fsm = ap_ST_fsm_state2680; + end + ap_ST_fsm_state2680 : begin + ap_NS_fsm = ap_ST_fsm_state2681; + end + ap_ST_fsm_state2681 : begin + ap_NS_fsm = ap_ST_fsm_state2682; + end + ap_ST_fsm_state2682 : begin + ap_NS_fsm = ap_ST_fsm_state2683; + end + ap_ST_fsm_state2683 : begin + ap_NS_fsm = ap_ST_fsm_state2684; + end + ap_ST_fsm_state2684 : begin + ap_NS_fsm = ap_ST_fsm_state2685; + end + ap_ST_fsm_state2685 : begin + ap_NS_fsm = ap_ST_fsm_state2686; + end + ap_ST_fsm_state2686 : begin + ap_NS_fsm = ap_ST_fsm_state2687; + end + ap_ST_fsm_state2687 : begin + ap_NS_fsm = ap_ST_fsm_state2688; + end + ap_ST_fsm_state2688 : begin + ap_NS_fsm = ap_ST_fsm_state2689; + end + ap_ST_fsm_state2689 : begin + if (((icmp_ln268_8_fu_118234_p2 == 1'd1) & (ap_ST_fsm_state2689 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2572; + end else begin + ap_NS_fsm = ap_ST_fsm_state2690; + end + end + ap_ST_fsm_state2690 : begin + ap_NS_fsm = ap_ST_fsm_state2691; + end + ap_ST_fsm_state2691 : begin + ap_NS_fsm = ap_ST_fsm_state2692; + end + ap_ST_fsm_state2692 : begin + ap_NS_fsm = ap_ST_fsm_state2693; + end + ap_ST_fsm_state2693 : begin + ap_NS_fsm = ap_ST_fsm_state2694; + end + ap_ST_fsm_state2694 : begin + ap_NS_fsm = ap_ST_fsm_state2695; + end + ap_ST_fsm_state2695 : begin + ap_NS_fsm = ap_ST_fsm_state2696; + end + ap_ST_fsm_state2696 : begin + ap_NS_fsm = ap_ST_fsm_state2697; + end + ap_ST_fsm_state2697 : begin + ap_NS_fsm = ap_ST_fsm_state2698; + end + ap_ST_fsm_state2698 : begin + ap_NS_fsm = ap_ST_fsm_state2699; + end + ap_ST_fsm_state2699 : begin + ap_NS_fsm = ap_ST_fsm_state2700; + end + ap_ST_fsm_state2700 : begin + ap_NS_fsm = ap_ST_fsm_state2701; + end + ap_ST_fsm_state2701 : begin + ap_NS_fsm = ap_ST_fsm_state2702; + end + ap_ST_fsm_state2702 : begin + ap_NS_fsm = ap_ST_fsm_state2703; + end + ap_ST_fsm_state2703 : begin + ap_NS_fsm = ap_ST_fsm_state2704; + end + ap_ST_fsm_state2704 : begin + ap_NS_fsm = ap_ST_fsm_state2705; + end + ap_ST_fsm_state2705 : begin + ap_NS_fsm = ap_ST_fsm_state2706; + end + ap_ST_fsm_state2706 : begin + ap_NS_fsm = ap_ST_fsm_state2707; + end + ap_ST_fsm_state2707 : begin + ap_NS_fsm = ap_ST_fsm_state2708; + end + ap_ST_fsm_state2708 : begin + ap_NS_fsm = ap_ST_fsm_state2709; + end + ap_ST_fsm_state2709 : begin + ap_NS_fsm = ap_ST_fsm_state2710; + end + ap_ST_fsm_state2710 : begin + ap_NS_fsm = ap_ST_fsm_state2711; + end + ap_ST_fsm_state2711 : begin + ap_NS_fsm = ap_ST_fsm_state2712; + end + ap_ST_fsm_state2712 : begin + ap_NS_fsm = ap_ST_fsm_state2713; + end + ap_ST_fsm_state2713 : begin + ap_NS_fsm = ap_ST_fsm_state2714; + end + ap_ST_fsm_state2714 : begin + ap_NS_fsm = ap_ST_fsm_state2715; + end + ap_ST_fsm_state2715 : begin + ap_NS_fsm = ap_ST_fsm_state2716; + end + ap_ST_fsm_state2716 : begin + ap_NS_fsm = ap_ST_fsm_state2717; + end + ap_ST_fsm_state2717 : begin + ap_NS_fsm = ap_ST_fsm_state2718; + end + ap_ST_fsm_state2718 : begin + ap_NS_fsm = ap_ST_fsm_state2719; + end + ap_ST_fsm_state2719 : begin + ap_NS_fsm = ap_ST_fsm_state2720; + end + ap_ST_fsm_state2720 : begin + ap_NS_fsm = ap_ST_fsm_state2721; + end + ap_ST_fsm_state2721 : begin + ap_NS_fsm = ap_ST_fsm_state2722; + end + ap_ST_fsm_state2722 : begin + ap_NS_fsm = ap_ST_fsm_state2723; + end + ap_ST_fsm_state2723 : begin + ap_NS_fsm = ap_ST_fsm_state2724; + end + ap_ST_fsm_state2724 : begin + ap_NS_fsm = ap_ST_fsm_state2725; + end + ap_ST_fsm_state2725 : begin + ap_NS_fsm = ap_ST_fsm_state2726; + end + ap_ST_fsm_state2726 : begin + ap_NS_fsm = ap_ST_fsm_state2650; + end + ap_ST_fsm_state2727 : begin + ap_NS_fsm = ap_ST_fsm_state2728; + end + ap_ST_fsm_state2728 : begin + ap_NS_fsm = ap_ST_fsm_state2729; + end + ap_ST_fsm_state2729 : begin + ap_NS_fsm = ap_ST_fsm_state2730; + end + ap_ST_fsm_state2730 : begin + ap_NS_fsm = ap_ST_fsm_state2731; + end + ap_ST_fsm_state2731 : begin + ap_NS_fsm = ap_ST_fsm_state2732; + end + ap_ST_fsm_state2732 : begin + ap_NS_fsm = ap_ST_fsm_state2733; + end + ap_ST_fsm_state2733 : begin + ap_NS_fsm = ap_ST_fsm_state2734; + end + ap_ST_fsm_state2734 : begin + ap_NS_fsm = ap_ST_fsm_state2735; + end + ap_ST_fsm_state2735 : begin + ap_NS_fsm = ap_ST_fsm_state2736; + end + ap_ST_fsm_state2736 : begin + ap_NS_fsm = ap_ST_fsm_state2737; + end + ap_ST_fsm_state2737 : begin + ap_NS_fsm = ap_ST_fsm_state2738; + end + ap_ST_fsm_state2738 : begin + ap_NS_fsm = ap_ST_fsm_state2739; + end + ap_ST_fsm_state2739 : begin + ap_NS_fsm = ap_ST_fsm_state2740; + end + ap_ST_fsm_state2740 : begin + ap_NS_fsm = ap_ST_fsm_state2741; + end + ap_ST_fsm_state2741 : begin + ap_NS_fsm = ap_ST_fsm_state2742; + end + ap_ST_fsm_state2742 : begin + ap_NS_fsm = ap_ST_fsm_state2743; + end + ap_ST_fsm_state2743 : begin + ap_NS_fsm = ap_ST_fsm_state2744; + end + ap_ST_fsm_state2744 : begin + ap_NS_fsm = ap_ST_fsm_state2745; + end + ap_ST_fsm_state2745 : begin + ap_NS_fsm = ap_ST_fsm_state2746; + end + ap_ST_fsm_state2746 : begin + ap_NS_fsm = ap_ST_fsm_state2747; + end + ap_ST_fsm_state2747 : begin + ap_NS_fsm = ap_ST_fsm_state2748; + end + ap_ST_fsm_state2748 : begin + ap_NS_fsm = ap_ST_fsm_state2749; + end + ap_ST_fsm_state2749 : begin + ap_NS_fsm = ap_ST_fsm_state2750; + end + ap_ST_fsm_state2750 : begin + ap_NS_fsm = ap_ST_fsm_state2751; + end + ap_ST_fsm_state2751 : begin + ap_NS_fsm = ap_ST_fsm_state2752; + end + ap_ST_fsm_state2752 : begin + ap_NS_fsm = ap_ST_fsm_state2753; + end + ap_ST_fsm_state2753 : begin + ap_NS_fsm = ap_ST_fsm_state2754; + end + ap_ST_fsm_state2754 : begin + ap_NS_fsm = ap_ST_fsm_state2755; + end + ap_ST_fsm_state2755 : begin + ap_NS_fsm = ap_ST_fsm_state2756; + end + ap_ST_fsm_state2756 : begin + ap_NS_fsm = ap_ST_fsm_state2757; + end + ap_ST_fsm_state2757 : begin + ap_NS_fsm = ap_ST_fsm_state2758; + end + ap_ST_fsm_state2758 : begin + ap_NS_fsm = ap_ST_fsm_state2759; + end + ap_ST_fsm_state2759 : begin + ap_NS_fsm = ap_ST_fsm_state2760; + end + ap_ST_fsm_state2760 : begin + ap_NS_fsm = ap_ST_fsm_state2761; + end + ap_ST_fsm_state2761 : begin + ap_NS_fsm = ap_ST_fsm_state2762; + end + ap_ST_fsm_state2762 : begin + ap_NS_fsm = ap_ST_fsm_state2763; + end + ap_ST_fsm_state2763 : begin + ap_NS_fsm = ap_ST_fsm_state2764; + end + ap_ST_fsm_state2764 : begin + ap_NS_fsm = ap_ST_fsm_state2765; + end + ap_ST_fsm_state2765 : begin + ap_NS_fsm = ap_ST_fsm_state2766; + end + ap_ST_fsm_state2766 : begin + ap_NS_fsm = ap_ST_fsm_state2767; + end + ap_ST_fsm_state2767 : begin + if (((icmp_ln266_8_fu_118650_p2 == 1'd1) & (icmp_ln268_9_fu_118627_p2 == 1'd1) & (ap_ST_fsm_state2767 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2571; + end else if (((icmp_ln268_9_fu_118627_p2 == 1'd1) & (ap_ST_fsm_state2767 == ap_CS_fsm) & (icmp_ln266_8_fu_118650_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state2805; + end else begin + ap_NS_fsm = ap_ST_fsm_state2768; + end + end + ap_ST_fsm_state2768 : begin + ap_NS_fsm = ap_ST_fsm_state2769; + end + ap_ST_fsm_state2769 : begin + ap_NS_fsm = ap_ST_fsm_state2770; + end + ap_ST_fsm_state2770 : begin + ap_NS_fsm = ap_ST_fsm_state2771; + end + ap_ST_fsm_state2771 : begin + ap_NS_fsm = ap_ST_fsm_state2772; + end + ap_ST_fsm_state2772 : begin + ap_NS_fsm = ap_ST_fsm_state2773; + end + ap_ST_fsm_state2773 : begin + ap_NS_fsm = ap_ST_fsm_state2774; + end + ap_ST_fsm_state2774 : begin + ap_NS_fsm = ap_ST_fsm_state2775; + end + ap_ST_fsm_state2775 : begin + ap_NS_fsm = ap_ST_fsm_state2776; + end + ap_ST_fsm_state2776 : begin + ap_NS_fsm = ap_ST_fsm_state2777; + end + ap_ST_fsm_state2777 : begin + ap_NS_fsm = ap_ST_fsm_state2778; + end + ap_ST_fsm_state2778 : begin + ap_NS_fsm = ap_ST_fsm_state2779; + end + ap_ST_fsm_state2779 : begin + ap_NS_fsm = ap_ST_fsm_state2780; + end + ap_ST_fsm_state2780 : begin + ap_NS_fsm = ap_ST_fsm_state2781; + end + ap_ST_fsm_state2781 : begin + ap_NS_fsm = ap_ST_fsm_state2782; + end + ap_ST_fsm_state2782 : begin + ap_NS_fsm = ap_ST_fsm_state2783; + end + ap_ST_fsm_state2783 : begin + ap_NS_fsm = ap_ST_fsm_state2784; + end + ap_ST_fsm_state2784 : begin + ap_NS_fsm = ap_ST_fsm_state2785; + end + ap_ST_fsm_state2785 : begin + ap_NS_fsm = ap_ST_fsm_state2786; + end + ap_ST_fsm_state2786 : begin + ap_NS_fsm = ap_ST_fsm_state2787; + end + ap_ST_fsm_state2787 : begin + ap_NS_fsm = ap_ST_fsm_state2788; + end + ap_ST_fsm_state2788 : begin + ap_NS_fsm = ap_ST_fsm_state2789; + end + ap_ST_fsm_state2789 : begin + ap_NS_fsm = ap_ST_fsm_state2790; + end + ap_ST_fsm_state2790 : begin + ap_NS_fsm = ap_ST_fsm_state2791; + end + ap_ST_fsm_state2791 : begin + ap_NS_fsm = ap_ST_fsm_state2792; + end + ap_ST_fsm_state2792 : begin + ap_NS_fsm = ap_ST_fsm_state2793; + end + ap_ST_fsm_state2793 : begin + ap_NS_fsm = ap_ST_fsm_state2794; + end + ap_ST_fsm_state2794 : begin + ap_NS_fsm = ap_ST_fsm_state2795; + end + ap_ST_fsm_state2795 : begin + ap_NS_fsm = ap_ST_fsm_state2796; + end + ap_ST_fsm_state2796 : begin + ap_NS_fsm = ap_ST_fsm_state2797; + end + ap_ST_fsm_state2797 : begin + ap_NS_fsm = ap_ST_fsm_state2798; + end + ap_ST_fsm_state2798 : begin + ap_NS_fsm = ap_ST_fsm_state2799; + end + ap_ST_fsm_state2799 : begin + ap_NS_fsm = ap_ST_fsm_state2800; + end + ap_ST_fsm_state2800 : begin + ap_NS_fsm = ap_ST_fsm_state2801; + end + ap_ST_fsm_state2801 : begin + ap_NS_fsm = ap_ST_fsm_state2802; + end + ap_ST_fsm_state2802 : begin + ap_NS_fsm = ap_ST_fsm_state2803; + end + ap_ST_fsm_state2803 : begin + ap_NS_fsm = ap_ST_fsm_state2804; + end + ap_ST_fsm_state2804 : begin + ap_NS_fsm = ap_ST_fsm_state2728; + end + ap_ST_fsm_state2805 : begin + ap_NS_fsm = ap_ST_fsm_state2806; + end + ap_ST_fsm_state2806 : begin + ap_NS_fsm = ap_ST_fsm_state2807; + end + ap_ST_fsm_state2807 : begin + ap_NS_fsm = ap_ST_fsm_state2808; + end + ap_ST_fsm_state2808 : begin + ap_NS_fsm = ap_ST_fsm_state2809; + end + ap_ST_fsm_state2809 : begin + ap_NS_fsm = ap_ST_fsm_state2810; + end + ap_ST_fsm_state2810 : begin + ap_NS_fsm = ap_ST_fsm_state2811; + end + ap_ST_fsm_state2811 : begin + ap_NS_fsm = ap_ST_fsm_state2812; + end + ap_ST_fsm_state2812 : begin + ap_NS_fsm = ap_ST_fsm_state2813; + end + ap_ST_fsm_state2813 : begin + ap_NS_fsm = ap_ST_fsm_state2814; + end + ap_ST_fsm_state2814 : begin + ap_NS_fsm = ap_ST_fsm_state2815; + end + ap_ST_fsm_state2815 : begin + ap_NS_fsm = ap_ST_fsm_state2816; + end + ap_ST_fsm_state2816 : begin + ap_NS_fsm = ap_ST_fsm_state2817; + end + ap_ST_fsm_state2817 : begin + ap_NS_fsm = ap_ST_fsm_state2818; + end + ap_ST_fsm_state2818 : begin + ap_NS_fsm = ap_ST_fsm_state2819; + end + ap_ST_fsm_state2819 : begin + ap_NS_fsm = ap_ST_fsm_state2820; + end + ap_ST_fsm_state2820 : begin + ap_NS_fsm = ap_ST_fsm_state2821; + end + ap_ST_fsm_state2821 : begin + ap_NS_fsm = ap_ST_fsm_state2822; + end + ap_ST_fsm_state2822 : begin + ap_NS_fsm = ap_ST_fsm_state2823; + end + ap_ST_fsm_state2823 : begin + ap_NS_fsm = ap_ST_fsm_state2824; + end + ap_ST_fsm_state2824 : begin + ap_NS_fsm = ap_ST_fsm_state2825; + end + ap_ST_fsm_state2825 : begin + ap_NS_fsm = ap_ST_fsm_state2826; + end + ap_ST_fsm_state2826 : begin + ap_NS_fsm = ap_ST_fsm_state2827; + end + ap_ST_fsm_state2827 : begin + ap_NS_fsm = ap_ST_fsm_state2828; + end + ap_ST_fsm_state2828 : begin + ap_NS_fsm = ap_ST_fsm_state2829; + end + ap_ST_fsm_state2829 : begin + ap_NS_fsm = ap_ST_fsm_state2830; + end + ap_ST_fsm_state2830 : begin + ap_NS_fsm = ap_ST_fsm_state2831; + end + ap_ST_fsm_state2831 : begin + ap_NS_fsm = ap_ST_fsm_state2832; + end + ap_ST_fsm_state2832 : begin + ap_NS_fsm = ap_ST_fsm_state2833; + end + ap_ST_fsm_state2833 : begin + ap_NS_fsm = ap_ST_fsm_state2834; + end + ap_ST_fsm_state2834 : begin + ap_NS_fsm = ap_ST_fsm_state2835; + end + ap_ST_fsm_state2835 : begin + ap_NS_fsm = ap_ST_fsm_state2836; + end + ap_ST_fsm_state2836 : begin + ap_NS_fsm = ap_ST_fsm_state2837; + end + ap_ST_fsm_state2837 : begin + ap_NS_fsm = ap_ST_fsm_state2838; + end + ap_ST_fsm_state2838 : begin + ap_NS_fsm = ap_ST_fsm_state2839; + end + ap_ST_fsm_state2839 : begin + ap_NS_fsm = ap_ST_fsm_state2840; + end + ap_ST_fsm_state2840 : begin + ap_NS_fsm = ap_ST_fsm_state2841; + end + ap_ST_fsm_state2841 : begin + ap_NS_fsm = ap_ST_fsm_state2842; + end + ap_ST_fsm_state2842 : begin + if (((icmp_ln268_24_fu_119032_p2 == 1'd1) & (ap_ST_fsm_state2842 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2727; + end else begin + ap_NS_fsm = ap_ST_fsm_state2843; + end + end + ap_ST_fsm_state2843 : begin + ap_NS_fsm = ap_ST_fsm_state2844; + end + ap_ST_fsm_state2844 : begin + ap_NS_fsm = ap_ST_fsm_state2845; + end + ap_ST_fsm_state2845 : begin + ap_NS_fsm = ap_ST_fsm_state2846; + end + ap_ST_fsm_state2846 : begin + ap_NS_fsm = ap_ST_fsm_state2847; + end + ap_ST_fsm_state2847 : begin + ap_NS_fsm = ap_ST_fsm_state2848; + end + ap_ST_fsm_state2848 : begin + ap_NS_fsm = ap_ST_fsm_state2849; + end + ap_ST_fsm_state2849 : begin + ap_NS_fsm = ap_ST_fsm_state2850; + end + ap_ST_fsm_state2850 : begin + ap_NS_fsm = ap_ST_fsm_state2851; + end + ap_ST_fsm_state2851 : begin + ap_NS_fsm = ap_ST_fsm_state2852; + end + ap_ST_fsm_state2852 : begin + ap_NS_fsm = ap_ST_fsm_state2853; + end + ap_ST_fsm_state2853 : begin + ap_NS_fsm = ap_ST_fsm_state2854; + end + ap_ST_fsm_state2854 : begin + ap_NS_fsm = ap_ST_fsm_state2855; + end + ap_ST_fsm_state2855 : begin + ap_NS_fsm = ap_ST_fsm_state2856; + end + ap_ST_fsm_state2856 : begin + ap_NS_fsm = ap_ST_fsm_state2857; + end + ap_ST_fsm_state2857 : begin + ap_NS_fsm = ap_ST_fsm_state2858; + end + ap_ST_fsm_state2858 : begin + ap_NS_fsm = ap_ST_fsm_state2859; + end + ap_ST_fsm_state2859 : begin + ap_NS_fsm = ap_ST_fsm_state2860; + end + ap_ST_fsm_state2860 : begin + ap_NS_fsm = ap_ST_fsm_state2861; + end + ap_ST_fsm_state2861 : begin + ap_NS_fsm = ap_ST_fsm_state2862; + end + ap_ST_fsm_state2862 : begin + ap_NS_fsm = ap_ST_fsm_state2863; + end + ap_ST_fsm_state2863 : begin + ap_NS_fsm = ap_ST_fsm_state2864; + end + ap_ST_fsm_state2864 : begin + ap_NS_fsm = ap_ST_fsm_state2865; + end + ap_ST_fsm_state2865 : begin + ap_NS_fsm = ap_ST_fsm_state2866; + end + ap_ST_fsm_state2866 : begin + ap_NS_fsm = ap_ST_fsm_state2867; + end + ap_ST_fsm_state2867 : begin + ap_NS_fsm = ap_ST_fsm_state2868; + end + ap_ST_fsm_state2868 : begin + ap_NS_fsm = ap_ST_fsm_state2869; + end + ap_ST_fsm_state2869 : begin + ap_NS_fsm = ap_ST_fsm_state2870; + end + ap_ST_fsm_state2870 : begin + ap_NS_fsm = ap_ST_fsm_state2871; + end + ap_ST_fsm_state2871 : begin + ap_NS_fsm = ap_ST_fsm_state2872; + end + ap_ST_fsm_state2872 : begin + ap_NS_fsm = ap_ST_fsm_state2873; + end + ap_ST_fsm_state2873 : begin + ap_NS_fsm = ap_ST_fsm_state2874; + end + ap_ST_fsm_state2874 : begin + ap_NS_fsm = ap_ST_fsm_state2875; + end + ap_ST_fsm_state2875 : begin + ap_NS_fsm = ap_ST_fsm_state2876; + end + ap_ST_fsm_state2876 : begin + ap_NS_fsm = ap_ST_fsm_state2877; + end + ap_ST_fsm_state2877 : begin + ap_NS_fsm = ap_ST_fsm_state2878; + end + ap_ST_fsm_state2878 : begin + ap_NS_fsm = ap_ST_fsm_state2805; + end + ap_ST_fsm_state2879 : begin + if (((icmp_ln264_3_fu_119214_p2 == 1'd1) & (ap_ST_fsm_state2879 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2570; + end else begin + ap_NS_fsm = ap_ST_fsm_state2880; + end + end + ap_ST_fsm_state2880 : begin + ap_NS_fsm = ap_ST_fsm_state2881; + end + ap_ST_fsm_state2881 : begin + ap_NS_fsm = ap_ST_fsm_state2882; + end + ap_ST_fsm_state2882 : begin + ap_NS_fsm = ap_ST_fsm_state2883; + end + ap_ST_fsm_state2883 : begin + ap_NS_fsm = ap_ST_fsm_state2884; + end + ap_ST_fsm_state2884 : begin + ap_NS_fsm = ap_ST_fsm_state2885; + end + ap_ST_fsm_state2885 : begin + ap_NS_fsm = ap_ST_fsm_state2886; + end + ap_ST_fsm_state2886 : begin + ap_NS_fsm = ap_ST_fsm_state2887; + end + ap_ST_fsm_state2887 : begin + ap_NS_fsm = ap_ST_fsm_state2888; + end + ap_ST_fsm_state2888 : begin + ap_NS_fsm = ap_ST_fsm_state2889; + end + ap_ST_fsm_state2889 : begin + ap_NS_fsm = ap_ST_fsm_state2890; + end + ap_ST_fsm_state2890 : begin + ap_NS_fsm = ap_ST_fsm_state2891; + end + ap_ST_fsm_state2891 : begin + ap_NS_fsm = ap_ST_fsm_state2892; + end + ap_ST_fsm_state2892 : begin + ap_NS_fsm = ap_ST_fsm_state2893; + end + ap_ST_fsm_state2893 : begin + ap_NS_fsm = ap_ST_fsm_state2894; + end + ap_ST_fsm_state2894 : begin + ap_NS_fsm = ap_ST_fsm_state2895; + end + ap_ST_fsm_state2895 : begin + ap_NS_fsm = ap_ST_fsm_state2896; + end + ap_ST_fsm_state2896 : begin + ap_NS_fsm = ap_ST_fsm_state2897; + end + ap_ST_fsm_state2897 : begin + ap_NS_fsm = ap_ST_fsm_state2898; + end + ap_ST_fsm_state2898 : begin + ap_NS_fsm = ap_ST_fsm_state2899; + end + ap_ST_fsm_state2899 : begin + ap_NS_fsm = ap_ST_fsm_state2900; + end + ap_ST_fsm_state2900 : begin + ap_NS_fsm = ap_ST_fsm_state2901; + end + ap_ST_fsm_state2901 : begin + ap_NS_fsm = ap_ST_fsm_state2902; + end + ap_ST_fsm_state2902 : begin + ap_NS_fsm = ap_ST_fsm_state2903; + end + ap_ST_fsm_state2903 : begin + ap_NS_fsm = ap_ST_fsm_state2904; + end + ap_ST_fsm_state2904 : begin + ap_NS_fsm = ap_ST_fsm_state2905; + end + ap_ST_fsm_state2905 : begin + ap_NS_fsm = ap_ST_fsm_state2906; + end + ap_ST_fsm_state2906 : begin + ap_NS_fsm = ap_ST_fsm_state2907; + end + ap_ST_fsm_state2907 : begin + ap_NS_fsm = ap_ST_fsm_state2908; + end + ap_ST_fsm_state2908 : begin + ap_NS_fsm = ap_ST_fsm_state2909; + end + ap_ST_fsm_state2909 : begin + ap_NS_fsm = ap_ST_fsm_state2910; + end + ap_ST_fsm_state2910 : begin + ap_NS_fsm = ap_ST_fsm_state2911; + end + ap_ST_fsm_state2911 : begin + ap_NS_fsm = ap_ST_fsm_state2912; + end + ap_ST_fsm_state2912 : begin + ap_NS_fsm = ap_ST_fsm_state2913; + end + ap_ST_fsm_state2913 : begin + ap_NS_fsm = ap_ST_fsm_state2914; + end + ap_ST_fsm_state2914 : begin + ap_NS_fsm = ap_ST_fsm_state2915; + end + ap_ST_fsm_state2915 : begin + ap_NS_fsm = ap_ST_fsm_state2916; + end + ap_ST_fsm_state2916 : begin + ap_NS_fsm = ap_ST_fsm_state2917; + end + ap_ST_fsm_state2917 : begin + ap_NS_fsm = ap_ST_fsm_state2918; + end + ap_ST_fsm_state2918 : begin + ap_NS_fsm = ap_ST_fsm_state2919; + end + ap_ST_fsm_state2919 : begin + ap_NS_fsm = ap_ST_fsm_state2920; + end + ap_ST_fsm_state2920 : begin + if (((icmp_ln266_3_fu_119467_p2 == 1'd1) & (icmp_ln268_3_fu_119444_p2 == 1'd1) & (ap_ST_fsm_state2920 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3035; + end else if (((icmp_ln268_3_fu_119444_p2 == 1'd1) & (ap_ST_fsm_state2920 == ap_CS_fsm) & (icmp_ln266_3_fu_119467_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state2958; + end else begin + ap_NS_fsm = ap_ST_fsm_state2921; + end + end + ap_ST_fsm_state2921 : begin + ap_NS_fsm = ap_ST_fsm_state2922; + end + ap_ST_fsm_state2922 : begin + ap_NS_fsm = ap_ST_fsm_state2923; + end + ap_ST_fsm_state2923 : begin + ap_NS_fsm = ap_ST_fsm_state2924; + end + ap_ST_fsm_state2924 : begin + ap_NS_fsm = ap_ST_fsm_state2925; + end + ap_ST_fsm_state2925 : begin + ap_NS_fsm = ap_ST_fsm_state2926; + end + ap_ST_fsm_state2926 : begin + ap_NS_fsm = ap_ST_fsm_state2927; + end + ap_ST_fsm_state2927 : begin + ap_NS_fsm = ap_ST_fsm_state2928; + end + ap_ST_fsm_state2928 : begin + ap_NS_fsm = ap_ST_fsm_state2929; + end + ap_ST_fsm_state2929 : begin + ap_NS_fsm = ap_ST_fsm_state2930; + end + ap_ST_fsm_state2930 : begin + ap_NS_fsm = ap_ST_fsm_state2931; + end + ap_ST_fsm_state2931 : begin + ap_NS_fsm = ap_ST_fsm_state2932; + end + ap_ST_fsm_state2932 : begin + ap_NS_fsm = ap_ST_fsm_state2933; + end + ap_ST_fsm_state2933 : begin + ap_NS_fsm = ap_ST_fsm_state2934; + end + ap_ST_fsm_state2934 : begin + ap_NS_fsm = ap_ST_fsm_state2935; + end + ap_ST_fsm_state2935 : begin + ap_NS_fsm = ap_ST_fsm_state2936; + end + ap_ST_fsm_state2936 : begin + ap_NS_fsm = ap_ST_fsm_state2937; + end + ap_ST_fsm_state2937 : begin + ap_NS_fsm = ap_ST_fsm_state2938; + end + ap_ST_fsm_state2938 : begin + ap_NS_fsm = ap_ST_fsm_state2939; + end + ap_ST_fsm_state2939 : begin + ap_NS_fsm = ap_ST_fsm_state2940; + end + ap_ST_fsm_state2940 : begin + ap_NS_fsm = ap_ST_fsm_state2941; + end + ap_ST_fsm_state2941 : begin + ap_NS_fsm = ap_ST_fsm_state2942; + end + ap_ST_fsm_state2942 : begin + ap_NS_fsm = ap_ST_fsm_state2943; + end + ap_ST_fsm_state2943 : begin + ap_NS_fsm = ap_ST_fsm_state2944; + end + ap_ST_fsm_state2944 : begin + ap_NS_fsm = ap_ST_fsm_state2945; + end + ap_ST_fsm_state2945 : begin + ap_NS_fsm = ap_ST_fsm_state2946; + end + ap_ST_fsm_state2946 : begin + ap_NS_fsm = ap_ST_fsm_state2947; + end + ap_ST_fsm_state2947 : begin + ap_NS_fsm = ap_ST_fsm_state2948; + end + ap_ST_fsm_state2948 : begin + ap_NS_fsm = ap_ST_fsm_state2949; + end + ap_ST_fsm_state2949 : begin + ap_NS_fsm = ap_ST_fsm_state2950; + end + ap_ST_fsm_state2950 : begin + ap_NS_fsm = ap_ST_fsm_state2951; + end + ap_ST_fsm_state2951 : begin + ap_NS_fsm = ap_ST_fsm_state2952; + end + ap_ST_fsm_state2952 : begin + ap_NS_fsm = ap_ST_fsm_state2953; + end + ap_ST_fsm_state2953 : begin + ap_NS_fsm = ap_ST_fsm_state2954; + end + ap_ST_fsm_state2954 : begin + ap_NS_fsm = ap_ST_fsm_state2955; + end + ap_ST_fsm_state2955 : begin + ap_NS_fsm = ap_ST_fsm_state2956; + end + ap_ST_fsm_state2956 : begin + ap_NS_fsm = ap_ST_fsm_state2957; + end + ap_ST_fsm_state2957 : begin + ap_NS_fsm = ap_ST_fsm_state2881; + end + ap_ST_fsm_state2958 : begin + ap_NS_fsm = ap_ST_fsm_state2959; + end + ap_ST_fsm_state2959 : begin + ap_NS_fsm = ap_ST_fsm_state2960; + end + ap_ST_fsm_state2960 : begin + ap_NS_fsm = ap_ST_fsm_state2961; + end + ap_ST_fsm_state2961 : begin + ap_NS_fsm = ap_ST_fsm_state2962; + end + ap_ST_fsm_state2962 : begin + ap_NS_fsm = ap_ST_fsm_state2963; + end + ap_ST_fsm_state2963 : begin + ap_NS_fsm = ap_ST_fsm_state2964; + end + ap_ST_fsm_state2964 : begin + ap_NS_fsm = ap_ST_fsm_state2965; + end + ap_ST_fsm_state2965 : begin + ap_NS_fsm = ap_ST_fsm_state2966; + end + ap_ST_fsm_state2966 : begin + ap_NS_fsm = ap_ST_fsm_state2967; + end + ap_ST_fsm_state2967 : begin + ap_NS_fsm = ap_ST_fsm_state2968; + end + ap_ST_fsm_state2968 : begin + ap_NS_fsm = ap_ST_fsm_state2969; + end + ap_ST_fsm_state2969 : begin + ap_NS_fsm = ap_ST_fsm_state2970; + end + ap_ST_fsm_state2970 : begin + ap_NS_fsm = ap_ST_fsm_state2971; + end + ap_ST_fsm_state2971 : begin + ap_NS_fsm = ap_ST_fsm_state2972; + end + ap_ST_fsm_state2972 : begin + ap_NS_fsm = ap_ST_fsm_state2973; + end + ap_ST_fsm_state2973 : begin + ap_NS_fsm = ap_ST_fsm_state2974; + end + ap_ST_fsm_state2974 : begin + ap_NS_fsm = ap_ST_fsm_state2975; + end + ap_ST_fsm_state2975 : begin + ap_NS_fsm = ap_ST_fsm_state2976; + end + ap_ST_fsm_state2976 : begin + ap_NS_fsm = ap_ST_fsm_state2977; + end + ap_ST_fsm_state2977 : begin + ap_NS_fsm = ap_ST_fsm_state2978; + end + ap_ST_fsm_state2978 : begin + ap_NS_fsm = ap_ST_fsm_state2979; + end + ap_ST_fsm_state2979 : begin + ap_NS_fsm = ap_ST_fsm_state2980; + end + ap_ST_fsm_state2980 : begin + ap_NS_fsm = ap_ST_fsm_state2981; + end + ap_ST_fsm_state2981 : begin + ap_NS_fsm = ap_ST_fsm_state2982; + end + ap_ST_fsm_state2982 : begin + ap_NS_fsm = ap_ST_fsm_state2983; + end + ap_ST_fsm_state2983 : begin + ap_NS_fsm = ap_ST_fsm_state2984; + end + ap_ST_fsm_state2984 : begin + ap_NS_fsm = ap_ST_fsm_state2985; + end + ap_ST_fsm_state2985 : begin + ap_NS_fsm = ap_ST_fsm_state2986; + end + ap_ST_fsm_state2986 : begin + ap_NS_fsm = ap_ST_fsm_state2987; + end + ap_ST_fsm_state2987 : begin + ap_NS_fsm = ap_ST_fsm_state2988; + end + ap_ST_fsm_state2988 : begin + ap_NS_fsm = ap_ST_fsm_state2989; + end + ap_ST_fsm_state2989 : begin + ap_NS_fsm = ap_ST_fsm_state2990; + end + ap_ST_fsm_state2990 : begin + ap_NS_fsm = ap_ST_fsm_state2991; + end + ap_ST_fsm_state2991 : begin + ap_NS_fsm = ap_ST_fsm_state2992; + end + ap_ST_fsm_state2992 : begin + ap_NS_fsm = ap_ST_fsm_state2993; + end + ap_ST_fsm_state2993 : begin + ap_NS_fsm = ap_ST_fsm_state2994; + end + ap_ST_fsm_state2994 : begin + ap_NS_fsm = ap_ST_fsm_state2995; + end + ap_ST_fsm_state2995 : begin + ap_NS_fsm = ap_ST_fsm_state2996; + end + ap_ST_fsm_state2996 : begin + ap_NS_fsm = ap_ST_fsm_state2997; + end + ap_ST_fsm_state2997 : begin + if (((icmp_ln268_12_fu_119859_p2 == 1'd1) & (ap_ST_fsm_state2997 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2880; + end else begin + ap_NS_fsm = ap_ST_fsm_state2998; + end + end + ap_ST_fsm_state2998 : begin + ap_NS_fsm = ap_ST_fsm_state2999; + end + ap_ST_fsm_state2999 : begin + ap_NS_fsm = ap_ST_fsm_state3000; + end + ap_ST_fsm_state3000 : begin + ap_NS_fsm = ap_ST_fsm_state3001; + end + ap_ST_fsm_state3001 : begin + ap_NS_fsm = ap_ST_fsm_state3002; + end + ap_ST_fsm_state3002 : begin + ap_NS_fsm = ap_ST_fsm_state3003; + end + ap_ST_fsm_state3003 : begin + ap_NS_fsm = ap_ST_fsm_state3004; + end + ap_ST_fsm_state3004 : begin + ap_NS_fsm = ap_ST_fsm_state3005; + end + ap_ST_fsm_state3005 : begin + ap_NS_fsm = ap_ST_fsm_state3006; + end + ap_ST_fsm_state3006 : begin + ap_NS_fsm = ap_ST_fsm_state3007; + end + ap_ST_fsm_state3007 : begin + ap_NS_fsm = ap_ST_fsm_state3008; + end + ap_ST_fsm_state3008 : begin + ap_NS_fsm = ap_ST_fsm_state3009; + end + ap_ST_fsm_state3009 : begin + ap_NS_fsm = ap_ST_fsm_state3010; + end + ap_ST_fsm_state3010 : begin + ap_NS_fsm = ap_ST_fsm_state3011; + end + ap_ST_fsm_state3011 : begin + ap_NS_fsm = ap_ST_fsm_state3012; + end + ap_ST_fsm_state3012 : begin + ap_NS_fsm = ap_ST_fsm_state3013; + end + ap_ST_fsm_state3013 : begin + ap_NS_fsm = ap_ST_fsm_state3014; + end + ap_ST_fsm_state3014 : begin + ap_NS_fsm = ap_ST_fsm_state3015; + end + ap_ST_fsm_state3015 : begin + ap_NS_fsm = ap_ST_fsm_state3016; + end + ap_ST_fsm_state3016 : begin + ap_NS_fsm = ap_ST_fsm_state3017; + end + ap_ST_fsm_state3017 : begin + ap_NS_fsm = ap_ST_fsm_state3018; + end + ap_ST_fsm_state3018 : begin + ap_NS_fsm = ap_ST_fsm_state3019; + end + ap_ST_fsm_state3019 : begin + ap_NS_fsm = ap_ST_fsm_state3020; + end + ap_ST_fsm_state3020 : begin + ap_NS_fsm = ap_ST_fsm_state3021; + end + ap_ST_fsm_state3021 : begin + ap_NS_fsm = ap_ST_fsm_state3022; + end + ap_ST_fsm_state3022 : begin + ap_NS_fsm = ap_ST_fsm_state3023; + end + ap_ST_fsm_state3023 : begin + ap_NS_fsm = ap_ST_fsm_state3024; + end + ap_ST_fsm_state3024 : begin + ap_NS_fsm = ap_ST_fsm_state3025; + end + ap_ST_fsm_state3025 : begin + ap_NS_fsm = ap_ST_fsm_state3026; + end + ap_ST_fsm_state3026 : begin + ap_NS_fsm = ap_ST_fsm_state3027; + end + ap_ST_fsm_state3027 : begin + ap_NS_fsm = ap_ST_fsm_state3028; + end + ap_ST_fsm_state3028 : begin + ap_NS_fsm = ap_ST_fsm_state3029; + end + ap_ST_fsm_state3029 : begin + ap_NS_fsm = ap_ST_fsm_state3030; + end + ap_ST_fsm_state3030 : begin + ap_NS_fsm = ap_ST_fsm_state3031; + end + ap_ST_fsm_state3031 : begin + ap_NS_fsm = ap_ST_fsm_state3032; + end + ap_ST_fsm_state3032 : begin + ap_NS_fsm = ap_ST_fsm_state3033; + end + ap_ST_fsm_state3033 : begin + ap_NS_fsm = ap_ST_fsm_state3034; + end + ap_ST_fsm_state3034 : begin + ap_NS_fsm = ap_ST_fsm_state2958; + end + ap_ST_fsm_state3035 : begin + ap_NS_fsm = ap_ST_fsm_state3036; + end + ap_ST_fsm_state3036 : begin + ap_NS_fsm = ap_ST_fsm_state3037; + end + ap_ST_fsm_state3037 : begin + ap_NS_fsm = ap_ST_fsm_state3038; + end + ap_ST_fsm_state3038 : begin + ap_NS_fsm = ap_ST_fsm_state3039; + end + ap_ST_fsm_state3039 : begin + ap_NS_fsm = ap_ST_fsm_state3040; + end + ap_ST_fsm_state3040 : begin + ap_NS_fsm = ap_ST_fsm_state3041; + end + ap_ST_fsm_state3041 : begin + ap_NS_fsm = ap_ST_fsm_state3042; + end + ap_ST_fsm_state3042 : begin + ap_NS_fsm = ap_ST_fsm_state3043; + end + ap_ST_fsm_state3043 : begin + ap_NS_fsm = ap_ST_fsm_state3044; + end + ap_ST_fsm_state3044 : begin + ap_NS_fsm = ap_ST_fsm_state3045; + end + ap_ST_fsm_state3045 : begin + ap_NS_fsm = ap_ST_fsm_state3046; + end + ap_ST_fsm_state3046 : begin + ap_NS_fsm = ap_ST_fsm_state3047; + end + ap_ST_fsm_state3047 : begin + ap_NS_fsm = ap_ST_fsm_state3048; + end + ap_ST_fsm_state3048 : begin + ap_NS_fsm = ap_ST_fsm_state3049; + end + ap_ST_fsm_state3049 : begin + ap_NS_fsm = ap_ST_fsm_state3050; + end + ap_ST_fsm_state3050 : begin + ap_NS_fsm = ap_ST_fsm_state3051; + end + ap_ST_fsm_state3051 : begin + ap_NS_fsm = ap_ST_fsm_state3052; + end + ap_ST_fsm_state3052 : begin + ap_NS_fsm = ap_ST_fsm_state3053; + end + ap_ST_fsm_state3053 : begin + ap_NS_fsm = ap_ST_fsm_state3054; + end + ap_ST_fsm_state3054 : begin + ap_NS_fsm = ap_ST_fsm_state3055; + end + ap_ST_fsm_state3055 : begin + ap_NS_fsm = ap_ST_fsm_state3056; + end + ap_ST_fsm_state3056 : begin + ap_NS_fsm = ap_ST_fsm_state3057; + end + ap_ST_fsm_state3057 : begin + ap_NS_fsm = ap_ST_fsm_state3058; + end + ap_ST_fsm_state3058 : begin + ap_NS_fsm = ap_ST_fsm_state3059; + end + ap_ST_fsm_state3059 : begin + ap_NS_fsm = ap_ST_fsm_state3060; + end + ap_ST_fsm_state3060 : begin + ap_NS_fsm = ap_ST_fsm_state3061; + end + ap_ST_fsm_state3061 : begin + ap_NS_fsm = ap_ST_fsm_state3062; + end + ap_ST_fsm_state3062 : begin + ap_NS_fsm = ap_ST_fsm_state3063; + end + ap_ST_fsm_state3063 : begin + ap_NS_fsm = ap_ST_fsm_state3064; + end + ap_ST_fsm_state3064 : begin + ap_NS_fsm = ap_ST_fsm_state3065; + end + ap_ST_fsm_state3065 : begin + ap_NS_fsm = ap_ST_fsm_state3066; + end + ap_ST_fsm_state3066 : begin + ap_NS_fsm = ap_ST_fsm_state3067; + end + ap_ST_fsm_state3067 : begin + ap_NS_fsm = ap_ST_fsm_state3068; + end + ap_ST_fsm_state3068 : begin + ap_NS_fsm = ap_ST_fsm_state3069; + end + ap_ST_fsm_state3069 : begin + ap_NS_fsm = ap_ST_fsm_state3070; + end + ap_ST_fsm_state3070 : begin + ap_NS_fsm = ap_ST_fsm_state3071; + end + ap_ST_fsm_state3071 : begin + ap_NS_fsm = ap_ST_fsm_state3072; + end + ap_ST_fsm_state3072 : begin + ap_NS_fsm = ap_ST_fsm_state3073; + end + ap_ST_fsm_state3073 : begin + ap_NS_fsm = ap_ST_fsm_state3074; + end + ap_ST_fsm_state3074 : begin + if (((icmp_ln266_11_fu_120274_p2 == 1'd1) & (icmp_ln268_15_fu_120251_p2 == 1'd1) & (ap_ST_fsm_state3074 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2879; + end else if (((icmp_ln268_15_fu_120251_p2 == 1'd1) & (ap_ST_fsm_state3074 == ap_CS_fsm) & (icmp_ln266_11_fu_120274_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state3112; + end else begin + ap_NS_fsm = ap_ST_fsm_state3075; + end + end + ap_ST_fsm_state3075 : begin + ap_NS_fsm = ap_ST_fsm_state3076; + end + ap_ST_fsm_state3076 : begin + ap_NS_fsm = ap_ST_fsm_state3077; + end + ap_ST_fsm_state3077 : begin + ap_NS_fsm = ap_ST_fsm_state3078; + end + ap_ST_fsm_state3078 : begin + ap_NS_fsm = ap_ST_fsm_state3079; + end + ap_ST_fsm_state3079 : begin + ap_NS_fsm = ap_ST_fsm_state3080; + end + ap_ST_fsm_state3080 : begin + ap_NS_fsm = ap_ST_fsm_state3081; + end + ap_ST_fsm_state3081 : begin + ap_NS_fsm = ap_ST_fsm_state3082; + end + ap_ST_fsm_state3082 : begin + ap_NS_fsm = ap_ST_fsm_state3083; + end + ap_ST_fsm_state3083 : begin + ap_NS_fsm = ap_ST_fsm_state3084; + end + ap_ST_fsm_state3084 : begin + ap_NS_fsm = ap_ST_fsm_state3085; + end + ap_ST_fsm_state3085 : begin + ap_NS_fsm = ap_ST_fsm_state3086; + end + ap_ST_fsm_state3086 : begin + ap_NS_fsm = ap_ST_fsm_state3087; + end + ap_ST_fsm_state3087 : begin + ap_NS_fsm = ap_ST_fsm_state3088; + end + ap_ST_fsm_state3088 : begin + ap_NS_fsm = ap_ST_fsm_state3089; + end + ap_ST_fsm_state3089 : begin + ap_NS_fsm = ap_ST_fsm_state3090; + end + ap_ST_fsm_state3090 : begin + ap_NS_fsm = ap_ST_fsm_state3091; + end + ap_ST_fsm_state3091 : begin + ap_NS_fsm = ap_ST_fsm_state3092; + end + ap_ST_fsm_state3092 : begin + ap_NS_fsm = ap_ST_fsm_state3093; + end + ap_ST_fsm_state3093 : begin + ap_NS_fsm = ap_ST_fsm_state3094; + end + ap_ST_fsm_state3094 : begin + ap_NS_fsm = ap_ST_fsm_state3095; + end + ap_ST_fsm_state3095 : begin + ap_NS_fsm = ap_ST_fsm_state3096; + end + ap_ST_fsm_state3096 : begin + ap_NS_fsm = ap_ST_fsm_state3097; + end + ap_ST_fsm_state3097 : begin + ap_NS_fsm = ap_ST_fsm_state3098; + end + ap_ST_fsm_state3098 : begin + ap_NS_fsm = ap_ST_fsm_state3099; + end + ap_ST_fsm_state3099 : begin + ap_NS_fsm = ap_ST_fsm_state3100; + end + ap_ST_fsm_state3100 : begin + ap_NS_fsm = ap_ST_fsm_state3101; + end + ap_ST_fsm_state3101 : begin + ap_NS_fsm = ap_ST_fsm_state3102; + end + ap_ST_fsm_state3102 : begin + ap_NS_fsm = ap_ST_fsm_state3103; + end + ap_ST_fsm_state3103 : begin + ap_NS_fsm = ap_ST_fsm_state3104; + end + ap_ST_fsm_state3104 : begin + ap_NS_fsm = ap_ST_fsm_state3105; + end + ap_ST_fsm_state3105 : begin + ap_NS_fsm = ap_ST_fsm_state3106; + end + ap_ST_fsm_state3106 : begin + ap_NS_fsm = ap_ST_fsm_state3107; + end + ap_ST_fsm_state3107 : begin + ap_NS_fsm = ap_ST_fsm_state3108; + end + ap_ST_fsm_state3108 : begin + ap_NS_fsm = ap_ST_fsm_state3109; + end + ap_ST_fsm_state3109 : begin + ap_NS_fsm = ap_ST_fsm_state3110; + end + ap_ST_fsm_state3110 : begin + ap_NS_fsm = ap_ST_fsm_state3111; + end + ap_ST_fsm_state3111 : begin + ap_NS_fsm = ap_ST_fsm_state3036; + end + ap_ST_fsm_state3112 : begin + ap_NS_fsm = ap_ST_fsm_state3113; + end + ap_ST_fsm_state3113 : begin + ap_NS_fsm = ap_ST_fsm_state3114; + end + ap_ST_fsm_state3114 : begin + ap_NS_fsm = ap_ST_fsm_state3115; + end + ap_ST_fsm_state3115 : begin + ap_NS_fsm = ap_ST_fsm_state3116; + end + ap_ST_fsm_state3116 : begin + ap_NS_fsm = ap_ST_fsm_state3117; + end + ap_ST_fsm_state3117 : begin + ap_NS_fsm = ap_ST_fsm_state3118; + end + ap_ST_fsm_state3118 : begin + ap_NS_fsm = ap_ST_fsm_state3119; + end + ap_ST_fsm_state3119 : begin + ap_NS_fsm = ap_ST_fsm_state3120; + end + ap_ST_fsm_state3120 : begin + ap_NS_fsm = ap_ST_fsm_state3121; + end + ap_ST_fsm_state3121 : begin + ap_NS_fsm = ap_ST_fsm_state3122; + end + ap_ST_fsm_state3122 : begin + ap_NS_fsm = ap_ST_fsm_state3123; + end + ap_ST_fsm_state3123 : begin + ap_NS_fsm = ap_ST_fsm_state3124; + end + ap_ST_fsm_state3124 : begin + ap_NS_fsm = ap_ST_fsm_state3125; + end + ap_ST_fsm_state3125 : begin + ap_NS_fsm = ap_ST_fsm_state3126; + end + ap_ST_fsm_state3126 : begin + ap_NS_fsm = ap_ST_fsm_state3127; + end + ap_ST_fsm_state3127 : begin + ap_NS_fsm = ap_ST_fsm_state3128; + end + ap_ST_fsm_state3128 : begin + ap_NS_fsm = ap_ST_fsm_state3129; + end + ap_ST_fsm_state3129 : begin + ap_NS_fsm = ap_ST_fsm_state3130; + end + ap_ST_fsm_state3130 : begin + ap_NS_fsm = ap_ST_fsm_state3131; + end + ap_ST_fsm_state3131 : begin + ap_NS_fsm = ap_ST_fsm_state3132; + end + ap_ST_fsm_state3132 : begin + ap_NS_fsm = ap_ST_fsm_state3133; + end + ap_ST_fsm_state3133 : begin + ap_NS_fsm = ap_ST_fsm_state3134; + end + ap_ST_fsm_state3134 : begin + ap_NS_fsm = ap_ST_fsm_state3135; + end + ap_ST_fsm_state3135 : begin + ap_NS_fsm = ap_ST_fsm_state3136; + end + ap_ST_fsm_state3136 : begin + ap_NS_fsm = ap_ST_fsm_state3137; + end + ap_ST_fsm_state3137 : begin + ap_NS_fsm = ap_ST_fsm_state3138; + end + ap_ST_fsm_state3138 : begin + ap_NS_fsm = ap_ST_fsm_state3139; + end + ap_ST_fsm_state3139 : begin + ap_NS_fsm = ap_ST_fsm_state3140; + end + ap_ST_fsm_state3140 : begin + ap_NS_fsm = ap_ST_fsm_state3141; + end + ap_ST_fsm_state3141 : begin + ap_NS_fsm = ap_ST_fsm_state3142; + end + ap_ST_fsm_state3142 : begin + ap_NS_fsm = ap_ST_fsm_state3143; + end + ap_ST_fsm_state3143 : begin + ap_NS_fsm = ap_ST_fsm_state3144; + end + ap_ST_fsm_state3144 : begin + ap_NS_fsm = ap_ST_fsm_state3145; + end + ap_ST_fsm_state3145 : begin + ap_NS_fsm = ap_ST_fsm_state3146; + end + ap_ST_fsm_state3146 : begin + ap_NS_fsm = ap_ST_fsm_state3147; + end + ap_ST_fsm_state3147 : begin + ap_NS_fsm = ap_ST_fsm_state3148; + end + ap_ST_fsm_state3148 : begin + ap_NS_fsm = ap_ST_fsm_state3149; + end + ap_ST_fsm_state3149 : begin + if (((icmp_ln268_27_fu_120655_p2 == 1'd1) & (ap_ST_fsm_state3149 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3035; + end else begin + ap_NS_fsm = ap_ST_fsm_state3150; + end + end + ap_ST_fsm_state3150 : begin + ap_NS_fsm = ap_ST_fsm_state3151; + end + ap_ST_fsm_state3151 : begin + ap_NS_fsm = ap_ST_fsm_state3152; + end + ap_ST_fsm_state3152 : begin + ap_NS_fsm = ap_ST_fsm_state3153; + end + ap_ST_fsm_state3153 : begin + ap_NS_fsm = ap_ST_fsm_state3154; + end + ap_ST_fsm_state3154 : begin + ap_NS_fsm = ap_ST_fsm_state3155; + end + ap_ST_fsm_state3155 : begin + ap_NS_fsm = ap_ST_fsm_state3156; + end + ap_ST_fsm_state3156 : begin + ap_NS_fsm = ap_ST_fsm_state3157; + end + ap_ST_fsm_state3157 : begin + ap_NS_fsm = ap_ST_fsm_state3158; + end + ap_ST_fsm_state3158 : begin + ap_NS_fsm = ap_ST_fsm_state3159; + end + ap_ST_fsm_state3159 : begin + ap_NS_fsm = ap_ST_fsm_state3160; + end + ap_ST_fsm_state3160 : begin + ap_NS_fsm = ap_ST_fsm_state3161; + end + ap_ST_fsm_state3161 : begin + ap_NS_fsm = ap_ST_fsm_state3162; + end + ap_ST_fsm_state3162 : begin + ap_NS_fsm = ap_ST_fsm_state3163; + end + ap_ST_fsm_state3163 : begin + ap_NS_fsm = ap_ST_fsm_state3164; + end + ap_ST_fsm_state3164 : begin + ap_NS_fsm = ap_ST_fsm_state3165; + end + ap_ST_fsm_state3165 : begin + ap_NS_fsm = ap_ST_fsm_state3166; + end + ap_ST_fsm_state3166 : begin + ap_NS_fsm = ap_ST_fsm_state3167; + end + ap_ST_fsm_state3167 : begin + ap_NS_fsm = ap_ST_fsm_state3168; + end + ap_ST_fsm_state3168 : begin + ap_NS_fsm = ap_ST_fsm_state3169; + end + ap_ST_fsm_state3169 : begin + ap_NS_fsm = ap_ST_fsm_state3170; + end + ap_ST_fsm_state3170 : begin + ap_NS_fsm = ap_ST_fsm_state3171; + end + ap_ST_fsm_state3171 : begin + ap_NS_fsm = ap_ST_fsm_state3172; + end + ap_ST_fsm_state3172 : begin + ap_NS_fsm = ap_ST_fsm_state3173; + end + ap_ST_fsm_state3173 : begin + ap_NS_fsm = ap_ST_fsm_state3174; + end + ap_ST_fsm_state3174 : begin + ap_NS_fsm = ap_ST_fsm_state3175; + end + ap_ST_fsm_state3175 : begin + ap_NS_fsm = ap_ST_fsm_state3176; + end + ap_ST_fsm_state3176 : begin + ap_NS_fsm = ap_ST_fsm_state3177; + end + ap_ST_fsm_state3177 : begin + ap_NS_fsm = ap_ST_fsm_state3178; + end + ap_ST_fsm_state3178 : begin + ap_NS_fsm = ap_ST_fsm_state3179; + end + ap_ST_fsm_state3179 : begin + ap_NS_fsm = ap_ST_fsm_state3180; + end + ap_ST_fsm_state3180 : begin + ap_NS_fsm = ap_ST_fsm_state3181; + end + ap_ST_fsm_state3181 : begin + ap_NS_fsm = ap_ST_fsm_state3182; + end + ap_ST_fsm_state3182 : begin + ap_NS_fsm = ap_ST_fsm_state3183; + end + ap_ST_fsm_state3183 : begin + ap_NS_fsm = ap_ST_fsm_state3184; + end + ap_ST_fsm_state3184 : begin + ap_NS_fsm = ap_ST_fsm_state3185; + end + ap_ST_fsm_state3185 : begin + ap_NS_fsm = ap_ST_fsm_state3112; + end + ap_ST_fsm_state3186 : begin + if (((icmp_ln261_2_fu_120840_p2 == 1'd1) & (ap_ST_fsm_state3186 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2569; + end else begin + ap_NS_fsm = ap_ST_fsm_state3187; + end + end + ap_ST_fsm_state3187 : begin + if (((icmp_ln264_2_fu_120952_p2 == 1'd1) & (ap_ST_fsm_state3187 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3494; + end else begin + ap_NS_fsm = ap_ST_fsm_state3188; + end + end + ap_ST_fsm_state3188 : begin + ap_NS_fsm = ap_ST_fsm_state3189; + end + ap_ST_fsm_state3189 : begin + ap_NS_fsm = ap_ST_fsm_state3190; + end + ap_ST_fsm_state3190 : begin + ap_NS_fsm = ap_ST_fsm_state3191; + end + ap_ST_fsm_state3191 : begin + ap_NS_fsm = ap_ST_fsm_state3192; + end + ap_ST_fsm_state3192 : begin + ap_NS_fsm = ap_ST_fsm_state3193; + end + ap_ST_fsm_state3193 : begin + ap_NS_fsm = ap_ST_fsm_state3194; + end + ap_ST_fsm_state3194 : begin + ap_NS_fsm = ap_ST_fsm_state3195; + end + ap_ST_fsm_state3195 : begin + ap_NS_fsm = ap_ST_fsm_state3196; + end + ap_ST_fsm_state3196 : begin + ap_NS_fsm = ap_ST_fsm_state3197; + end + ap_ST_fsm_state3197 : begin + ap_NS_fsm = ap_ST_fsm_state3198; + end + ap_ST_fsm_state3198 : begin + ap_NS_fsm = ap_ST_fsm_state3199; + end + ap_ST_fsm_state3199 : begin + ap_NS_fsm = ap_ST_fsm_state3200; + end + ap_ST_fsm_state3200 : begin + ap_NS_fsm = ap_ST_fsm_state3201; + end + ap_ST_fsm_state3201 : begin + ap_NS_fsm = ap_ST_fsm_state3202; + end + ap_ST_fsm_state3202 : begin + ap_NS_fsm = ap_ST_fsm_state3203; + end + ap_ST_fsm_state3203 : begin + ap_NS_fsm = ap_ST_fsm_state3204; + end + ap_ST_fsm_state3204 : begin + ap_NS_fsm = ap_ST_fsm_state3205; + end + ap_ST_fsm_state3205 : begin + ap_NS_fsm = ap_ST_fsm_state3206; + end + ap_ST_fsm_state3206 : begin + ap_NS_fsm = ap_ST_fsm_state3207; + end + ap_ST_fsm_state3207 : begin + ap_NS_fsm = ap_ST_fsm_state3208; + end + ap_ST_fsm_state3208 : begin + ap_NS_fsm = ap_ST_fsm_state3209; + end + ap_ST_fsm_state3209 : begin + ap_NS_fsm = ap_ST_fsm_state3210; + end + ap_ST_fsm_state3210 : begin + ap_NS_fsm = ap_ST_fsm_state3211; + end + ap_ST_fsm_state3211 : begin + ap_NS_fsm = ap_ST_fsm_state3212; + end + ap_ST_fsm_state3212 : begin + ap_NS_fsm = ap_ST_fsm_state3213; + end + ap_ST_fsm_state3213 : begin + ap_NS_fsm = ap_ST_fsm_state3214; + end + ap_ST_fsm_state3214 : begin + ap_NS_fsm = ap_ST_fsm_state3215; + end + ap_ST_fsm_state3215 : begin + ap_NS_fsm = ap_ST_fsm_state3216; + end + ap_ST_fsm_state3216 : begin + ap_NS_fsm = ap_ST_fsm_state3217; + end + ap_ST_fsm_state3217 : begin + ap_NS_fsm = ap_ST_fsm_state3218; + end + ap_ST_fsm_state3218 : begin + ap_NS_fsm = ap_ST_fsm_state3219; + end + ap_ST_fsm_state3219 : begin + ap_NS_fsm = ap_ST_fsm_state3220; + end + ap_ST_fsm_state3220 : begin + ap_NS_fsm = ap_ST_fsm_state3221; + end + ap_ST_fsm_state3221 : begin + ap_NS_fsm = ap_ST_fsm_state3222; + end + ap_ST_fsm_state3222 : begin + ap_NS_fsm = ap_ST_fsm_state3223; + end + ap_ST_fsm_state3223 : begin + ap_NS_fsm = ap_ST_fsm_state3224; + end + ap_ST_fsm_state3224 : begin + ap_NS_fsm = ap_ST_fsm_state3225; + end + ap_ST_fsm_state3225 : begin + ap_NS_fsm = ap_ST_fsm_state3226; + end + ap_ST_fsm_state3226 : begin + ap_NS_fsm = ap_ST_fsm_state3227; + end + ap_ST_fsm_state3227 : begin + ap_NS_fsm = ap_ST_fsm_state3228; + end + ap_ST_fsm_state3228 : begin + if (((icmp_ln266_2_fu_121309_p2 == 1'd1) & (icmp_ln268_2_fu_121286_p2 == 1'd1) & (ap_ST_fsm_state3228 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3343; + end else if (((icmp_ln268_2_fu_121286_p2 == 1'd1) & (ap_ST_fsm_state3228 == ap_CS_fsm) & (icmp_ln266_2_fu_121309_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state3266; + end else begin + ap_NS_fsm = ap_ST_fsm_state3229; + end + end + ap_ST_fsm_state3229 : begin + ap_NS_fsm = ap_ST_fsm_state3230; + end + ap_ST_fsm_state3230 : begin + ap_NS_fsm = ap_ST_fsm_state3231; + end + ap_ST_fsm_state3231 : begin + ap_NS_fsm = ap_ST_fsm_state3232; + end + ap_ST_fsm_state3232 : begin + ap_NS_fsm = ap_ST_fsm_state3233; + end + ap_ST_fsm_state3233 : begin + ap_NS_fsm = ap_ST_fsm_state3234; + end + ap_ST_fsm_state3234 : begin + ap_NS_fsm = ap_ST_fsm_state3235; + end + ap_ST_fsm_state3235 : begin + ap_NS_fsm = ap_ST_fsm_state3236; + end + ap_ST_fsm_state3236 : begin + ap_NS_fsm = ap_ST_fsm_state3237; + end + ap_ST_fsm_state3237 : begin + ap_NS_fsm = ap_ST_fsm_state3238; + end + ap_ST_fsm_state3238 : begin + ap_NS_fsm = ap_ST_fsm_state3239; + end + ap_ST_fsm_state3239 : begin + ap_NS_fsm = ap_ST_fsm_state3240; + end + ap_ST_fsm_state3240 : begin + ap_NS_fsm = ap_ST_fsm_state3241; + end + ap_ST_fsm_state3241 : begin + ap_NS_fsm = ap_ST_fsm_state3242; + end + ap_ST_fsm_state3242 : begin + ap_NS_fsm = ap_ST_fsm_state3243; + end + ap_ST_fsm_state3243 : begin + ap_NS_fsm = ap_ST_fsm_state3244; + end + ap_ST_fsm_state3244 : begin + ap_NS_fsm = ap_ST_fsm_state3245; + end + ap_ST_fsm_state3245 : begin + ap_NS_fsm = ap_ST_fsm_state3246; + end + ap_ST_fsm_state3246 : begin + ap_NS_fsm = ap_ST_fsm_state3247; + end + ap_ST_fsm_state3247 : begin + ap_NS_fsm = ap_ST_fsm_state3248; + end + ap_ST_fsm_state3248 : begin + ap_NS_fsm = ap_ST_fsm_state3249; + end + ap_ST_fsm_state3249 : begin + ap_NS_fsm = ap_ST_fsm_state3250; + end + ap_ST_fsm_state3250 : begin + ap_NS_fsm = ap_ST_fsm_state3251; + end + ap_ST_fsm_state3251 : begin + ap_NS_fsm = ap_ST_fsm_state3252; + end + ap_ST_fsm_state3252 : begin + ap_NS_fsm = ap_ST_fsm_state3253; + end + ap_ST_fsm_state3253 : begin + ap_NS_fsm = ap_ST_fsm_state3254; + end + ap_ST_fsm_state3254 : begin + ap_NS_fsm = ap_ST_fsm_state3255; + end + ap_ST_fsm_state3255 : begin + ap_NS_fsm = ap_ST_fsm_state3256; + end + ap_ST_fsm_state3256 : begin + ap_NS_fsm = ap_ST_fsm_state3257; + end + ap_ST_fsm_state3257 : begin + ap_NS_fsm = ap_ST_fsm_state3258; + end + ap_ST_fsm_state3258 : begin + ap_NS_fsm = ap_ST_fsm_state3259; + end + ap_ST_fsm_state3259 : begin + ap_NS_fsm = ap_ST_fsm_state3260; + end + ap_ST_fsm_state3260 : begin + ap_NS_fsm = ap_ST_fsm_state3261; + end + ap_ST_fsm_state3261 : begin + ap_NS_fsm = ap_ST_fsm_state3262; + end + ap_ST_fsm_state3262 : begin + ap_NS_fsm = ap_ST_fsm_state3263; + end + ap_ST_fsm_state3263 : begin + ap_NS_fsm = ap_ST_fsm_state3264; + end + ap_ST_fsm_state3264 : begin + ap_NS_fsm = ap_ST_fsm_state3265; + end + ap_ST_fsm_state3265 : begin + ap_NS_fsm = ap_ST_fsm_state3189; + end + ap_ST_fsm_state3266 : begin + ap_NS_fsm = ap_ST_fsm_state3267; + end + ap_ST_fsm_state3267 : begin + ap_NS_fsm = ap_ST_fsm_state3268; + end + ap_ST_fsm_state3268 : begin + ap_NS_fsm = ap_ST_fsm_state3269; + end + ap_ST_fsm_state3269 : begin + ap_NS_fsm = ap_ST_fsm_state3270; + end + ap_ST_fsm_state3270 : begin + ap_NS_fsm = ap_ST_fsm_state3271; + end + ap_ST_fsm_state3271 : begin + ap_NS_fsm = ap_ST_fsm_state3272; + end + ap_ST_fsm_state3272 : begin + ap_NS_fsm = ap_ST_fsm_state3273; + end + ap_ST_fsm_state3273 : begin + ap_NS_fsm = ap_ST_fsm_state3274; + end + ap_ST_fsm_state3274 : begin + ap_NS_fsm = ap_ST_fsm_state3275; + end + ap_ST_fsm_state3275 : begin + ap_NS_fsm = ap_ST_fsm_state3276; + end + ap_ST_fsm_state3276 : begin + ap_NS_fsm = ap_ST_fsm_state3277; + end + ap_ST_fsm_state3277 : begin + ap_NS_fsm = ap_ST_fsm_state3278; + end + ap_ST_fsm_state3278 : begin + ap_NS_fsm = ap_ST_fsm_state3279; + end + ap_ST_fsm_state3279 : begin + ap_NS_fsm = ap_ST_fsm_state3280; + end + ap_ST_fsm_state3280 : begin + ap_NS_fsm = ap_ST_fsm_state3281; + end + ap_ST_fsm_state3281 : begin + ap_NS_fsm = ap_ST_fsm_state3282; + end + ap_ST_fsm_state3282 : begin + ap_NS_fsm = ap_ST_fsm_state3283; + end + ap_ST_fsm_state3283 : begin + ap_NS_fsm = ap_ST_fsm_state3284; + end + ap_ST_fsm_state3284 : begin + ap_NS_fsm = ap_ST_fsm_state3285; + end + ap_ST_fsm_state3285 : begin + ap_NS_fsm = ap_ST_fsm_state3286; + end + ap_ST_fsm_state3286 : begin + ap_NS_fsm = ap_ST_fsm_state3287; + end + ap_ST_fsm_state3287 : begin + ap_NS_fsm = ap_ST_fsm_state3288; + end + ap_ST_fsm_state3288 : begin + ap_NS_fsm = ap_ST_fsm_state3289; + end + ap_ST_fsm_state3289 : begin + ap_NS_fsm = ap_ST_fsm_state3290; + end + ap_ST_fsm_state3290 : begin + ap_NS_fsm = ap_ST_fsm_state3291; + end + ap_ST_fsm_state3291 : begin + ap_NS_fsm = ap_ST_fsm_state3292; + end + ap_ST_fsm_state3292 : begin + ap_NS_fsm = ap_ST_fsm_state3293; + end + ap_ST_fsm_state3293 : begin + ap_NS_fsm = ap_ST_fsm_state3294; + end + ap_ST_fsm_state3294 : begin + ap_NS_fsm = ap_ST_fsm_state3295; + end + ap_ST_fsm_state3295 : begin + ap_NS_fsm = ap_ST_fsm_state3296; + end + ap_ST_fsm_state3296 : begin + ap_NS_fsm = ap_ST_fsm_state3297; + end + ap_ST_fsm_state3297 : begin + ap_NS_fsm = ap_ST_fsm_state3298; + end + ap_ST_fsm_state3298 : begin + ap_NS_fsm = ap_ST_fsm_state3299; + end + ap_ST_fsm_state3299 : begin + ap_NS_fsm = ap_ST_fsm_state3300; + end + ap_ST_fsm_state3300 : begin + ap_NS_fsm = ap_ST_fsm_state3301; + end + ap_ST_fsm_state3301 : begin + ap_NS_fsm = ap_ST_fsm_state3302; + end + ap_ST_fsm_state3302 : begin + ap_NS_fsm = ap_ST_fsm_state3303; + end + ap_ST_fsm_state3303 : begin + ap_NS_fsm = ap_ST_fsm_state3304; + end + ap_ST_fsm_state3304 : begin + ap_NS_fsm = ap_ST_fsm_state3305; + end + ap_ST_fsm_state3305 : begin + if (((icmp_ln268_11_fu_121702_p2 == 1'd1) & (ap_ST_fsm_state3305 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3188; + end else begin + ap_NS_fsm = ap_ST_fsm_state3306; + end + end + ap_ST_fsm_state3306 : begin + ap_NS_fsm = ap_ST_fsm_state3307; + end + ap_ST_fsm_state3307 : begin + ap_NS_fsm = ap_ST_fsm_state3308; + end + ap_ST_fsm_state3308 : begin + ap_NS_fsm = ap_ST_fsm_state3309; + end + ap_ST_fsm_state3309 : begin + ap_NS_fsm = ap_ST_fsm_state3310; + end + ap_ST_fsm_state3310 : begin + ap_NS_fsm = ap_ST_fsm_state3311; + end + ap_ST_fsm_state3311 : begin + ap_NS_fsm = ap_ST_fsm_state3312; + end + ap_ST_fsm_state3312 : begin + ap_NS_fsm = ap_ST_fsm_state3313; + end + ap_ST_fsm_state3313 : begin + ap_NS_fsm = ap_ST_fsm_state3314; + end + ap_ST_fsm_state3314 : begin + ap_NS_fsm = ap_ST_fsm_state3315; + end + ap_ST_fsm_state3315 : begin + ap_NS_fsm = ap_ST_fsm_state3316; + end + ap_ST_fsm_state3316 : begin + ap_NS_fsm = ap_ST_fsm_state3317; + end + ap_ST_fsm_state3317 : begin + ap_NS_fsm = ap_ST_fsm_state3318; + end + ap_ST_fsm_state3318 : begin + ap_NS_fsm = ap_ST_fsm_state3319; + end + ap_ST_fsm_state3319 : begin + ap_NS_fsm = ap_ST_fsm_state3320; + end + ap_ST_fsm_state3320 : begin + ap_NS_fsm = ap_ST_fsm_state3321; + end + ap_ST_fsm_state3321 : begin + ap_NS_fsm = ap_ST_fsm_state3322; + end + ap_ST_fsm_state3322 : begin + ap_NS_fsm = ap_ST_fsm_state3323; + end + ap_ST_fsm_state3323 : begin + ap_NS_fsm = ap_ST_fsm_state3324; + end + ap_ST_fsm_state3324 : begin + ap_NS_fsm = ap_ST_fsm_state3325; + end + ap_ST_fsm_state3325 : begin + ap_NS_fsm = ap_ST_fsm_state3326; + end + ap_ST_fsm_state3326 : begin + ap_NS_fsm = ap_ST_fsm_state3327; + end + ap_ST_fsm_state3327 : begin + ap_NS_fsm = ap_ST_fsm_state3328; + end + ap_ST_fsm_state3328 : begin + ap_NS_fsm = ap_ST_fsm_state3329; + end + ap_ST_fsm_state3329 : begin + ap_NS_fsm = ap_ST_fsm_state3330; + end + ap_ST_fsm_state3330 : begin + ap_NS_fsm = ap_ST_fsm_state3331; + end + ap_ST_fsm_state3331 : begin + ap_NS_fsm = ap_ST_fsm_state3332; + end + ap_ST_fsm_state3332 : begin + ap_NS_fsm = ap_ST_fsm_state3333; + end + ap_ST_fsm_state3333 : begin + ap_NS_fsm = ap_ST_fsm_state3334; + end + ap_ST_fsm_state3334 : begin + ap_NS_fsm = ap_ST_fsm_state3335; + end + ap_ST_fsm_state3335 : begin + ap_NS_fsm = ap_ST_fsm_state3336; + end + ap_ST_fsm_state3336 : begin + ap_NS_fsm = ap_ST_fsm_state3337; + end + ap_ST_fsm_state3337 : begin + ap_NS_fsm = ap_ST_fsm_state3338; + end + ap_ST_fsm_state3338 : begin + ap_NS_fsm = ap_ST_fsm_state3339; + end + ap_ST_fsm_state3339 : begin + ap_NS_fsm = ap_ST_fsm_state3340; + end + ap_ST_fsm_state3340 : begin + ap_NS_fsm = ap_ST_fsm_state3341; + end + ap_ST_fsm_state3341 : begin + ap_NS_fsm = ap_ST_fsm_state3342; + end + ap_ST_fsm_state3342 : begin + ap_NS_fsm = ap_ST_fsm_state3266; + end + ap_ST_fsm_state3343 : begin + ap_NS_fsm = ap_ST_fsm_state3344; + end + ap_ST_fsm_state3344 : begin + ap_NS_fsm = ap_ST_fsm_state3345; + end + ap_ST_fsm_state3345 : begin + ap_NS_fsm = ap_ST_fsm_state3346; + end + ap_ST_fsm_state3346 : begin + ap_NS_fsm = ap_ST_fsm_state3347; + end + ap_ST_fsm_state3347 : begin + ap_NS_fsm = ap_ST_fsm_state3348; + end + ap_ST_fsm_state3348 : begin + ap_NS_fsm = ap_ST_fsm_state3349; + end + ap_ST_fsm_state3349 : begin + ap_NS_fsm = ap_ST_fsm_state3350; + end + ap_ST_fsm_state3350 : begin + ap_NS_fsm = ap_ST_fsm_state3351; + end + ap_ST_fsm_state3351 : begin + ap_NS_fsm = ap_ST_fsm_state3352; + end + ap_ST_fsm_state3352 : begin + ap_NS_fsm = ap_ST_fsm_state3353; + end + ap_ST_fsm_state3353 : begin + ap_NS_fsm = ap_ST_fsm_state3354; + end + ap_ST_fsm_state3354 : begin + ap_NS_fsm = ap_ST_fsm_state3355; + end + ap_ST_fsm_state3355 : begin + ap_NS_fsm = ap_ST_fsm_state3356; + end + ap_ST_fsm_state3356 : begin + ap_NS_fsm = ap_ST_fsm_state3357; + end + ap_ST_fsm_state3357 : begin + ap_NS_fsm = ap_ST_fsm_state3358; + end + ap_ST_fsm_state3358 : begin + ap_NS_fsm = ap_ST_fsm_state3359; + end + ap_ST_fsm_state3359 : begin + ap_NS_fsm = ap_ST_fsm_state3360; + end + ap_ST_fsm_state3360 : begin + ap_NS_fsm = ap_ST_fsm_state3361; + end + ap_ST_fsm_state3361 : begin + ap_NS_fsm = ap_ST_fsm_state3362; + end + ap_ST_fsm_state3362 : begin + ap_NS_fsm = ap_ST_fsm_state3363; + end + ap_ST_fsm_state3363 : begin + ap_NS_fsm = ap_ST_fsm_state3364; + end + ap_ST_fsm_state3364 : begin + ap_NS_fsm = ap_ST_fsm_state3365; + end + ap_ST_fsm_state3365 : begin + ap_NS_fsm = ap_ST_fsm_state3366; + end + ap_ST_fsm_state3366 : begin + ap_NS_fsm = ap_ST_fsm_state3367; + end + ap_ST_fsm_state3367 : begin + ap_NS_fsm = ap_ST_fsm_state3368; + end + ap_ST_fsm_state3368 : begin + ap_NS_fsm = ap_ST_fsm_state3369; + end + ap_ST_fsm_state3369 : begin + ap_NS_fsm = ap_ST_fsm_state3370; + end + ap_ST_fsm_state3370 : begin + ap_NS_fsm = ap_ST_fsm_state3371; + end + ap_ST_fsm_state3371 : begin + ap_NS_fsm = ap_ST_fsm_state3372; + end + ap_ST_fsm_state3372 : begin + ap_NS_fsm = ap_ST_fsm_state3373; + end + ap_ST_fsm_state3373 : begin + ap_NS_fsm = ap_ST_fsm_state3374; + end + ap_ST_fsm_state3374 : begin + ap_NS_fsm = ap_ST_fsm_state3375; + end + ap_ST_fsm_state3375 : begin + ap_NS_fsm = ap_ST_fsm_state3376; + end + ap_ST_fsm_state3376 : begin + ap_NS_fsm = ap_ST_fsm_state3377; + end + ap_ST_fsm_state3377 : begin + ap_NS_fsm = ap_ST_fsm_state3378; + end + ap_ST_fsm_state3378 : begin + ap_NS_fsm = ap_ST_fsm_state3379; + end + ap_ST_fsm_state3379 : begin + ap_NS_fsm = ap_ST_fsm_state3380; + end + ap_ST_fsm_state3380 : begin + ap_NS_fsm = ap_ST_fsm_state3381; + end + ap_ST_fsm_state3381 : begin + ap_NS_fsm = ap_ST_fsm_state3382; + end + ap_ST_fsm_state3382 : begin + if (((icmp_ln266_10_fu_122118_p2 == 1'd1) & (icmp_ln268_14_fu_122095_p2 == 1'd1) & (ap_ST_fsm_state3382 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3187; + end else if (((icmp_ln268_14_fu_122095_p2 == 1'd1) & (ap_ST_fsm_state3382 == ap_CS_fsm) & (icmp_ln266_10_fu_122118_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state3420; + end else begin + ap_NS_fsm = ap_ST_fsm_state3383; + end + end + ap_ST_fsm_state3383 : begin + ap_NS_fsm = ap_ST_fsm_state3384; + end + ap_ST_fsm_state3384 : begin + ap_NS_fsm = ap_ST_fsm_state3385; + end + ap_ST_fsm_state3385 : begin + ap_NS_fsm = ap_ST_fsm_state3386; + end + ap_ST_fsm_state3386 : begin + ap_NS_fsm = ap_ST_fsm_state3387; + end + ap_ST_fsm_state3387 : begin + ap_NS_fsm = ap_ST_fsm_state3388; + end + ap_ST_fsm_state3388 : begin + ap_NS_fsm = ap_ST_fsm_state3389; + end + ap_ST_fsm_state3389 : begin + ap_NS_fsm = ap_ST_fsm_state3390; + end + ap_ST_fsm_state3390 : begin + ap_NS_fsm = ap_ST_fsm_state3391; + end + ap_ST_fsm_state3391 : begin + ap_NS_fsm = ap_ST_fsm_state3392; + end + ap_ST_fsm_state3392 : begin + ap_NS_fsm = ap_ST_fsm_state3393; + end + ap_ST_fsm_state3393 : begin + ap_NS_fsm = ap_ST_fsm_state3394; + end + ap_ST_fsm_state3394 : begin + ap_NS_fsm = ap_ST_fsm_state3395; + end + ap_ST_fsm_state3395 : begin + ap_NS_fsm = ap_ST_fsm_state3396; + end + ap_ST_fsm_state3396 : begin + ap_NS_fsm = ap_ST_fsm_state3397; + end + ap_ST_fsm_state3397 : begin + ap_NS_fsm = ap_ST_fsm_state3398; + end + ap_ST_fsm_state3398 : begin + ap_NS_fsm = ap_ST_fsm_state3399; + end + ap_ST_fsm_state3399 : begin + ap_NS_fsm = ap_ST_fsm_state3400; + end + ap_ST_fsm_state3400 : begin + ap_NS_fsm = ap_ST_fsm_state3401; + end + ap_ST_fsm_state3401 : begin + ap_NS_fsm = ap_ST_fsm_state3402; + end + ap_ST_fsm_state3402 : begin + ap_NS_fsm = ap_ST_fsm_state3403; + end + ap_ST_fsm_state3403 : begin + ap_NS_fsm = ap_ST_fsm_state3404; + end + ap_ST_fsm_state3404 : begin + ap_NS_fsm = ap_ST_fsm_state3405; + end + ap_ST_fsm_state3405 : begin + ap_NS_fsm = ap_ST_fsm_state3406; + end + ap_ST_fsm_state3406 : begin + ap_NS_fsm = ap_ST_fsm_state3407; + end + ap_ST_fsm_state3407 : begin + ap_NS_fsm = ap_ST_fsm_state3408; + end + ap_ST_fsm_state3408 : begin + ap_NS_fsm = ap_ST_fsm_state3409; + end + ap_ST_fsm_state3409 : begin + ap_NS_fsm = ap_ST_fsm_state3410; + end + ap_ST_fsm_state3410 : begin + ap_NS_fsm = ap_ST_fsm_state3411; + end + ap_ST_fsm_state3411 : begin + ap_NS_fsm = ap_ST_fsm_state3412; + end + ap_ST_fsm_state3412 : begin + ap_NS_fsm = ap_ST_fsm_state3413; + end + ap_ST_fsm_state3413 : begin + ap_NS_fsm = ap_ST_fsm_state3414; + end + ap_ST_fsm_state3414 : begin + ap_NS_fsm = ap_ST_fsm_state3415; + end + ap_ST_fsm_state3415 : begin + ap_NS_fsm = ap_ST_fsm_state3416; + end + ap_ST_fsm_state3416 : begin + ap_NS_fsm = ap_ST_fsm_state3417; + end + ap_ST_fsm_state3417 : begin + ap_NS_fsm = ap_ST_fsm_state3418; + end + ap_ST_fsm_state3418 : begin + ap_NS_fsm = ap_ST_fsm_state3419; + end + ap_ST_fsm_state3419 : begin + ap_NS_fsm = ap_ST_fsm_state3344; + end + ap_ST_fsm_state3420 : begin + ap_NS_fsm = ap_ST_fsm_state3421; + end + ap_ST_fsm_state3421 : begin + ap_NS_fsm = ap_ST_fsm_state3422; + end + ap_ST_fsm_state3422 : begin + ap_NS_fsm = ap_ST_fsm_state3423; + end + ap_ST_fsm_state3423 : begin + ap_NS_fsm = ap_ST_fsm_state3424; + end + ap_ST_fsm_state3424 : begin + ap_NS_fsm = ap_ST_fsm_state3425; + end + ap_ST_fsm_state3425 : begin + ap_NS_fsm = ap_ST_fsm_state3426; + end + ap_ST_fsm_state3426 : begin + ap_NS_fsm = ap_ST_fsm_state3427; + end + ap_ST_fsm_state3427 : begin + ap_NS_fsm = ap_ST_fsm_state3428; + end + ap_ST_fsm_state3428 : begin + ap_NS_fsm = ap_ST_fsm_state3429; + end + ap_ST_fsm_state3429 : begin + ap_NS_fsm = ap_ST_fsm_state3430; + end + ap_ST_fsm_state3430 : begin + ap_NS_fsm = ap_ST_fsm_state3431; + end + ap_ST_fsm_state3431 : begin + ap_NS_fsm = ap_ST_fsm_state3432; + end + ap_ST_fsm_state3432 : begin + ap_NS_fsm = ap_ST_fsm_state3433; + end + ap_ST_fsm_state3433 : begin + ap_NS_fsm = ap_ST_fsm_state3434; + end + ap_ST_fsm_state3434 : begin + ap_NS_fsm = ap_ST_fsm_state3435; + end + ap_ST_fsm_state3435 : begin + ap_NS_fsm = ap_ST_fsm_state3436; + end + ap_ST_fsm_state3436 : begin + ap_NS_fsm = ap_ST_fsm_state3437; + end + ap_ST_fsm_state3437 : begin + ap_NS_fsm = ap_ST_fsm_state3438; + end + ap_ST_fsm_state3438 : begin + ap_NS_fsm = ap_ST_fsm_state3439; + end + ap_ST_fsm_state3439 : begin + ap_NS_fsm = ap_ST_fsm_state3440; + end + ap_ST_fsm_state3440 : begin + ap_NS_fsm = ap_ST_fsm_state3441; + end + ap_ST_fsm_state3441 : begin + ap_NS_fsm = ap_ST_fsm_state3442; + end + ap_ST_fsm_state3442 : begin + ap_NS_fsm = ap_ST_fsm_state3443; + end + ap_ST_fsm_state3443 : begin + ap_NS_fsm = ap_ST_fsm_state3444; + end + ap_ST_fsm_state3444 : begin + ap_NS_fsm = ap_ST_fsm_state3445; + end + ap_ST_fsm_state3445 : begin + ap_NS_fsm = ap_ST_fsm_state3446; + end + ap_ST_fsm_state3446 : begin + ap_NS_fsm = ap_ST_fsm_state3447; + end + ap_ST_fsm_state3447 : begin + ap_NS_fsm = ap_ST_fsm_state3448; + end + ap_ST_fsm_state3448 : begin + ap_NS_fsm = ap_ST_fsm_state3449; + end + ap_ST_fsm_state3449 : begin + ap_NS_fsm = ap_ST_fsm_state3450; + end + ap_ST_fsm_state3450 : begin + ap_NS_fsm = ap_ST_fsm_state3451; + end + ap_ST_fsm_state3451 : begin + ap_NS_fsm = ap_ST_fsm_state3452; + end + ap_ST_fsm_state3452 : begin + ap_NS_fsm = ap_ST_fsm_state3453; + end + ap_ST_fsm_state3453 : begin + ap_NS_fsm = ap_ST_fsm_state3454; + end + ap_ST_fsm_state3454 : begin + ap_NS_fsm = ap_ST_fsm_state3455; + end + ap_ST_fsm_state3455 : begin + ap_NS_fsm = ap_ST_fsm_state3456; + end + ap_ST_fsm_state3456 : begin + ap_NS_fsm = ap_ST_fsm_state3457; + end + ap_ST_fsm_state3457 : begin + if (((icmp_ln268_26_fu_122500_p2 == 1'd1) & (ap_ST_fsm_state3457 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3343; + end else begin + ap_NS_fsm = ap_ST_fsm_state3458; + end + end + ap_ST_fsm_state3458 : begin + ap_NS_fsm = ap_ST_fsm_state3459; + end + ap_ST_fsm_state3459 : begin + ap_NS_fsm = ap_ST_fsm_state3460; + end + ap_ST_fsm_state3460 : begin + ap_NS_fsm = ap_ST_fsm_state3461; + end + ap_ST_fsm_state3461 : begin + ap_NS_fsm = ap_ST_fsm_state3462; + end + ap_ST_fsm_state3462 : begin + ap_NS_fsm = ap_ST_fsm_state3463; + end + ap_ST_fsm_state3463 : begin + ap_NS_fsm = ap_ST_fsm_state3464; + end + ap_ST_fsm_state3464 : begin + ap_NS_fsm = ap_ST_fsm_state3465; + end + ap_ST_fsm_state3465 : begin + ap_NS_fsm = ap_ST_fsm_state3466; + end + ap_ST_fsm_state3466 : begin + ap_NS_fsm = ap_ST_fsm_state3467; + end + ap_ST_fsm_state3467 : begin + ap_NS_fsm = ap_ST_fsm_state3468; + end + ap_ST_fsm_state3468 : begin + ap_NS_fsm = ap_ST_fsm_state3469; + end + ap_ST_fsm_state3469 : begin + ap_NS_fsm = ap_ST_fsm_state3470; + end + ap_ST_fsm_state3470 : begin + ap_NS_fsm = ap_ST_fsm_state3471; + end + ap_ST_fsm_state3471 : begin + ap_NS_fsm = ap_ST_fsm_state3472; + end + ap_ST_fsm_state3472 : begin + ap_NS_fsm = ap_ST_fsm_state3473; + end + ap_ST_fsm_state3473 : begin + ap_NS_fsm = ap_ST_fsm_state3474; + end + ap_ST_fsm_state3474 : begin + ap_NS_fsm = ap_ST_fsm_state3475; + end + ap_ST_fsm_state3475 : begin + ap_NS_fsm = ap_ST_fsm_state3476; + end + ap_ST_fsm_state3476 : begin + ap_NS_fsm = ap_ST_fsm_state3477; + end + ap_ST_fsm_state3477 : begin + ap_NS_fsm = ap_ST_fsm_state3478; + end + ap_ST_fsm_state3478 : begin + ap_NS_fsm = ap_ST_fsm_state3479; + end + ap_ST_fsm_state3479 : begin + ap_NS_fsm = ap_ST_fsm_state3480; + end + ap_ST_fsm_state3480 : begin + ap_NS_fsm = ap_ST_fsm_state3481; + end + ap_ST_fsm_state3481 : begin + ap_NS_fsm = ap_ST_fsm_state3482; + end + ap_ST_fsm_state3482 : begin + ap_NS_fsm = ap_ST_fsm_state3483; + end + ap_ST_fsm_state3483 : begin + ap_NS_fsm = ap_ST_fsm_state3484; + end + ap_ST_fsm_state3484 : begin + ap_NS_fsm = ap_ST_fsm_state3485; + end + ap_ST_fsm_state3485 : begin + ap_NS_fsm = ap_ST_fsm_state3486; + end + ap_ST_fsm_state3486 : begin + ap_NS_fsm = ap_ST_fsm_state3487; + end + ap_ST_fsm_state3487 : begin + ap_NS_fsm = ap_ST_fsm_state3488; + end + ap_ST_fsm_state3488 : begin + ap_NS_fsm = ap_ST_fsm_state3489; + end + ap_ST_fsm_state3489 : begin + ap_NS_fsm = ap_ST_fsm_state3490; + end + ap_ST_fsm_state3490 : begin + ap_NS_fsm = ap_ST_fsm_state3491; + end + ap_ST_fsm_state3491 : begin + ap_NS_fsm = ap_ST_fsm_state3492; + end + ap_ST_fsm_state3492 : begin + ap_NS_fsm = ap_ST_fsm_state3493; + end + ap_ST_fsm_state3493 : begin + ap_NS_fsm = ap_ST_fsm_state3420; + end + ap_ST_fsm_state3494 : begin + if (((icmp_ln264_6_fu_122682_p2 == 1'd1) & (ap_ST_fsm_state3494 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3186; + end else begin + ap_NS_fsm = ap_ST_fsm_state3495; + end + end + ap_ST_fsm_state3495 : begin + ap_NS_fsm = ap_ST_fsm_state3496; + end + ap_ST_fsm_state3496 : begin + ap_NS_fsm = ap_ST_fsm_state3497; + end + ap_ST_fsm_state3497 : begin + ap_NS_fsm = ap_ST_fsm_state3498; + end + ap_ST_fsm_state3498 : begin + ap_NS_fsm = ap_ST_fsm_state3499; + end + ap_ST_fsm_state3499 : begin + ap_NS_fsm = ap_ST_fsm_state3500; + end + ap_ST_fsm_state3500 : begin + ap_NS_fsm = ap_ST_fsm_state3501; + end + ap_ST_fsm_state3501 : begin + ap_NS_fsm = ap_ST_fsm_state3502; + end + ap_ST_fsm_state3502 : begin + ap_NS_fsm = ap_ST_fsm_state3503; + end + ap_ST_fsm_state3503 : begin + ap_NS_fsm = ap_ST_fsm_state3504; + end + ap_ST_fsm_state3504 : begin + ap_NS_fsm = ap_ST_fsm_state3505; + end + ap_ST_fsm_state3505 : begin + ap_NS_fsm = ap_ST_fsm_state3506; + end + ap_ST_fsm_state3506 : begin + ap_NS_fsm = ap_ST_fsm_state3507; + end + ap_ST_fsm_state3507 : begin + ap_NS_fsm = ap_ST_fsm_state3508; + end + ap_ST_fsm_state3508 : begin + ap_NS_fsm = ap_ST_fsm_state3509; + end + ap_ST_fsm_state3509 : begin + ap_NS_fsm = ap_ST_fsm_state3510; + end + ap_ST_fsm_state3510 : begin + ap_NS_fsm = ap_ST_fsm_state3511; + end + ap_ST_fsm_state3511 : begin + ap_NS_fsm = ap_ST_fsm_state3512; + end + ap_ST_fsm_state3512 : begin + ap_NS_fsm = ap_ST_fsm_state3513; + end + ap_ST_fsm_state3513 : begin + ap_NS_fsm = ap_ST_fsm_state3514; + end + ap_ST_fsm_state3514 : begin + ap_NS_fsm = ap_ST_fsm_state3515; + end + ap_ST_fsm_state3515 : begin + ap_NS_fsm = ap_ST_fsm_state3516; + end + ap_ST_fsm_state3516 : begin + ap_NS_fsm = ap_ST_fsm_state3517; + end + ap_ST_fsm_state3517 : begin + ap_NS_fsm = ap_ST_fsm_state3518; + end + ap_ST_fsm_state3518 : begin + ap_NS_fsm = ap_ST_fsm_state3519; + end + ap_ST_fsm_state3519 : begin + ap_NS_fsm = ap_ST_fsm_state3520; + end + ap_ST_fsm_state3520 : begin + ap_NS_fsm = ap_ST_fsm_state3521; + end + ap_ST_fsm_state3521 : begin + ap_NS_fsm = ap_ST_fsm_state3522; + end + ap_ST_fsm_state3522 : begin + ap_NS_fsm = ap_ST_fsm_state3523; + end + ap_ST_fsm_state3523 : begin + ap_NS_fsm = ap_ST_fsm_state3524; + end + ap_ST_fsm_state3524 : begin + ap_NS_fsm = ap_ST_fsm_state3525; + end + ap_ST_fsm_state3525 : begin + ap_NS_fsm = ap_ST_fsm_state3526; + end + ap_ST_fsm_state3526 : begin + ap_NS_fsm = ap_ST_fsm_state3527; + end + ap_ST_fsm_state3527 : begin + ap_NS_fsm = ap_ST_fsm_state3528; + end + ap_ST_fsm_state3528 : begin + ap_NS_fsm = ap_ST_fsm_state3529; + end + ap_ST_fsm_state3529 : begin + ap_NS_fsm = ap_ST_fsm_state3530; + end + ap_ST_fsm_state3530 : begin + ap_NS_fsm = ap_ST_fsm_state3531; + end + ap_ST_fsm_state3531 : begin + ap_NS_fsm = ap_ST_fsm_state3532; + end + ap_ST_fsm_state3532 : begin + ap_NS_fsm = ap_ST_fsm_state3533; + end + ap_ST_fsm_state3533 : begin + ap_NS_fsm = ap_ST_fsm_state3534; + end + ap_ST_fsm_state3534 : begin + ap_NS_fsm = ap_ST_fsm_state3535; + end + ap_ST_fsm_state3535 : begin + if (((icmp_ln266_6_fu_122935_p2 == 1'd1) & (icmp_ln268_6_fu_122912_p2 == 1'd1) & (ap_ST_fsm_state3535 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3650; + end else if (((icmp_ln268_6_fu_122912_p2 == 1'd1) & (ap_ST_fsm_state3535 == ap_CS_fsm) & (icmp_ln266_6_fu_122935_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state3573; + end else begin + ap_NS_fsm = ap_ST_fsm_state3536; + end + end + ap_ST_fsm_state3536 : begin + ap_NS_fsm = ap_ST_fsm_state3537; + end + ap_ST_fsm_state3537 : begin + ap_NS_fsm = ap_ST_fsm_state3538; + end + ap_ST_fsm_state3538 : begin + ap_NS_fsm = ap_ST_fsm_state3539; + end + ap_ST_fsm_state3539 : begin + ap_NS_fsm = ap_ST_fsm_state3540; + end + ap_ST_fsm_state3540 : begin + ap_NS_fsm = ap_ST_fsm_state3541; + end + ap_ST_fsm_state3541 : begin + ap_NS_fsm = ap_ST_fsm_state3542; + end + ap_ST_fsm_state3542 : begin + ap_NS_fsm = ap_ST_fsm_state3543; + end + ap_ST_fsm_state3543 : begin + ap_NS_fsm = ap_ST_fsm_state3544; + end + ap_ST_fsm_state3544 : begin + ap_NS_fsm = ap_ST_fsm_state3545; + end + ap_ST_fsm_state3545 : begin + ap_NS_fsm = ap_ST_fsm_state3546; + end + ap_ST_fsm_state3546 : begin + ap_NS_fsm = ap_ST_fsm_state3547; + end + ap_ST_fsm_state3547 : begin + ap_NS_fsm = ap_ST_fsm_state3548; + end + ap_ST_fsm_state3548 : begin + ap_NS_fsm = ap_ST_fsm_state3549; + end + ap_ST_fsm_state3549 : begin + ap_NS_fsm = ap_ST_fsm_state3550; + end + ap_ST_fsm_state3550 : begin + ap_NS_fsm = ap_ST_fsm_state3551; + end + ap_ST_fsm_state3551 : begin + ap_NS_fsm = ap_ST_fsm_state3552; + end + ap_ST_fsm_state3552 : begin + ap_NS_fsm = ap_ST_fsm_state3553; + end + ap_ST_fsm_state3553 : begin + ap_NS_fsm = ap_ST_fsm_state3554; + end + ap_ST_fsm_state3554 : begin + ap_NS_fsm = ap_ST_fsm_state3555; + end + ap_ST_fsm_state3555 : begin + ap_NS_fsm = ap_ST_fsm_state3556; + end + ap_ST_fsm_state3556 : begin + ap_NS_fsm = ap_ST_fsm_state3557; + end + ap_ST_fsm_state3557 : begin + ap_NS_fsm = ap_ST_fsm_state3558; + end + ap_ST_fsm_state3558 : begin + ap_NS_fsm = ap_ST_fsm_state3559; + end + ap_ST_fsm_state3559 : begin + ap_NS_fsm = ap_ST_fsm_state3560; + end + ap_ST_fsm_state3560 : begin + ap_NS_fsm = ap_ST_fsm_state3561; + end + ap_ST_fsm_state3561 : begin + ap_NS_fsm = ap_ST_fsm_state3562; + end + ap_ST_fsm_state3562 : begin + ap_NS_fsm = ap_ST_fsm_state3563; + end + ap_ST_fsm_state3563 : begin + ap_NS_fsm = ap_ST_fsm_state3564; + end + ap_ST_fsm_state3564 : begin + ap_NS_fsm = ap_ST_fsm_state3565; + end + ap_ST_fsm_state3565 : begin + ap_NS_fsm = ap_ST_fsm_state3566; + end + ap_ST_fsm_state3566 : begin + ap_NS_fsm = ap_ST_fsm_state3567; + end + ap_ST_fsm_state3567 : begin + ap_NS_fsm = ap_ST_fsm_state3568; + end + ap_ST_fsm_state3568 : begin + ap_NS_fsm = ap_ST_fsm_state3569; + end + ap_ST_fsm_state3569 : begin + ap_NS_fsm = ap_ST_fsm_state3570; + end + ap_ST_fsm_state3570 : begin + ap_NS_fsm = ap_ST_fsm_state3571; + end + ap_ST_fsm_state3571 : begin + ap_NS_fsm = ap_ST_fsm_state3572; + end + ap_ST_fsm_state3572 : begin + ap_NS_fsm = ap_ST_fsm_state3496; + end + ap_ST_fsm_state3573 : begin + ap_NS_fsm = ap_ST_fsm_state3574; + end + ap_ST_fsm_state3574 : begin + ap_NS_fsm = ap_ST_fsm_state3575; + end + ap_ST_fsm_state3575 : begin + ap_NS_fsm = ap_ST_fsm_state3576; + end + ap_ST_fsm_state3576 : begin + ap_NS_fsm = ap_ST_fsm_state3577; + end + ap_ST_fsm_state3577 : begin + ap_NS_fsm = ap_ST_fsm_state3578; + end + ap_ST_fsm_state3578 : begin + ap_NS_fsm = ap_ST_fsm_state3579; + end + ap_ST_fsm_state3579 : begin + ap_NS_fsm = ap_ST_fsm_state3580; + end + ap_ST_fsm_state3580 : begin + ap_NS_fsm = ap_ST_fsm_state3581; + end + ap_ST_fsm_state3581 : begin + ap_NS_fsm = ap_ST_fsm_state3582; + end + ap_ST_fsm_state3582 : begin + ap_NS_fsm = ap_ST_fsm_state3583; + end + ap_ST_fsm_state3583 : begin + ap_NS_fsm = ap_ST_fsm_state3584; + end + ap_ST_fsm_state3584 : begin + ap_NS_fsm = ap_ST_fsm_state3585; + end + ap_ST_fsm_state3585 : begin + ap_NS_fsm = ap_ST_fsm_state3586; + end + ap_ST_fsm_state3586 : begin + ap_NS_fsm = ap_ST_fsm_state3587; + end + ap_ST_fsm_state3587 : begin + ap_NS_fsm = ap_ST_fsm_state3588; + end + ap_ST_fsm_state3588 : begin + ap_NS_fsm = ap_ST_fsm_state3589; + end + ap_ST_fsm_state3589 : begin + ap_NS_fsm = ap_ST_fsm_state3590; + end + ap_ST_fsm_state3590 : begin + ap_NS_fsm = ap_ST_fsm_state3591; + end + ap_ST_fsm_state3591 : begin + ap_NS_fsm = ap_ST_fsm_state3592; + end + ap_ST_fsm_state3592 : begin + ap_NS_fsm = ap_ST_fsm_state3593; + end + ap_ST_fsm_state3593 : begin + ap_NS_fsm = ap_ST_fsm_state3594; + end + ap_ST_fsm_state3594 : begin + ap_NS_fsm = ap_ST_fsm_state3595; + end + ap_ST_fsm_state3595 : begin + ap_NS_fsm = ap_ST_fsm_state3596; + end + ap_ST_fsm_state3596 : begin + ap_NS_fsm = ap_ST_fsm_state3597; + end + ap_ST_fsm_state3597 : begin + ap_NS_fsm = ap_ST_fsm_state3598; + end + ap_ST_fsm_state3598 : begin + ap_NS_fsm = ap_ST_fsm_state3599; + end + ap_ST_fsm_state3599 : begin + ap_NS_fsm = ap_ST_fsm_state3600; + end + ap_ST_fsm_state3600 : begin + ap_NS_fsm = ap_ST_fsm_state3601; + end + ap_ST_fsm_state3601 : begin + ap_NS_fsm = ap_ST_fsm_state3602; + end + ap_ST_fsm_state3602 : begin + ap_NS_fsm = ap_ST_fsm_state3603; + end + ap_ST_fsm_state3603 : begin + ap_NS_fsm = ap_ST_fsm_state3604; + end + ap_ST_fsm_state3604 : begin + ap_NS_fsm = ap_ST_fsm_state3605; + end + ap_ST_fsm_state3605 : begin + ap_NS_fsm = ap_ST_fsm_state3606; + end + ap_ST_fsm_state3606 : begin + ap_NS_fsm = ap_ST_fsm_state3607; + end + ap_ST_fsm_state3607 : begin + ap_NS_fsm = ap_ST_fsm_state3608; + end + ap_ST_fsm_state3608 : begin + ap_NS_fsm = ap_ST_fsm_state3609; + end + ap_ST_fsm_state3609 : begin + ap_NS_fsm = ap_ST_fsm_state3610; + end + ap_ST_fsm_state3610 : begin + ap_NS_fsm = ap_ST_fsm_state3611; + end + ap_ST_fsm_state3611 : begin + ap_NS_fsm = ap_ST_fsm_state3612; + end + ap_ST_fsm_state3612 : begin + if (((icmp_ln268_18_fu_123327_p2 == 1'd1) & (ap_ST_fsm_state3612 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3495; + end else begin + ap_NS_fsm = ap_ST_fsm_state3613; + end + end + ap_ST_fsm_state3613 : begin + ap_NS_fsm = ap_ST_fsm_state3614; + end + ap_ST_fsm_state3614 : begin + ap_NS_fsm = ap_ST_fsm_state3615; + end + ap_ST_fsm_state3615 : begin + ap_NS_fsm = ap_ST_fsm_state3616; + end + ap_ST_fsm_state3616 : begin + ap_NS_fsm = ap_ST_fsm_state3617; + end + ap_ST_fsm_state3617 : begin + ap_NS_fsm = ap_ST_fsm_state3618; + end + ap_ST_fsm_state3618 : begin + ap_NS_fsm = ap_ST_fsm_state3619; + end + ap_ST_fsm_state3619 : begin + ap_NS_fsm = ap_ST_fsm_state3620; + end + ap_ST_fsm_state3620 : begin + ap_NS_fsm = ap_ST_fsm_state3621; + end + ap_ST_fsm_state3621 : begin + ap_NS_fsm = ap_ST_fsm_state3622; + end + ap_ST_fsm_state3622 : begin + ap_NS_fsm = ap_ST_fsm_state3623; + end + ap_ST_fsm_state3623 : begin + ap_NS_fsm = ap_ST_fsm_state3624; + end + ap_ST_fsm_state3624 : begin + ap_NS_fsm = ap_ST_fsm_state3625; + end + ap_ST_fsm_state3625 : begin + ap_NS_fsm = ap_ST_fsm_state3626; + end + ap_ST_fsm_state3626 : begin + ap_NS_fsm = ap_ST_fsm_state3627; + end + ap_ST_fsm_state3627 : begin + ap_NS_fsm = ap_ST_fsm_state3628; + end + ap_ST_fsm_state3628 : begin + ap_NS_fsm = ap_ST_fsm_state3629; + end + ap_ST_fsm_state3629 : begin + ap_NS_fsm = ap_ST_fsm_state3630; + end + ap_ST_fsm_state3630 : begin + ap_NS_fsm = ap_ST_fsm_state3631; + end + ap_ST_fsm_state3631 : begin + ap_NS_fsm = ap_ST_fsm_state3632; + end + ap_ST_fsm_state3632 : begin + ap_NS_fsm = ap_ST_fsm_state3633; + end + ap_ST_fsm_state3633 : begin + ap_NS_fsm = ap_ST_fsm_state3634; + end + ap_ST_fsm_state3634 : begin + ap_NS_fsm = ap_ST_fsm_state3635; + end + ap_ST_fsm_state3635 : begin + ap_NS_fsm = ap_ST_fsm_state3636; + end + ap_ST_fsm_state3636 : begin + ap_NS_fsm = ap_ST_fsm_state3637; + end + ap_ST_fsm_state3637 : begin + ap_NS_fsm = ap_ST_fsm_state3638; + end + ap_ST_fsm_state3638 : begin + ap_NS_fsm = ap_ST_fsm_state3639; + end + ap_ST_fsm_state3639 : begin + ap_NS_fsm = ap_ST_fsm_state3640; + end + ap_ST_fsm_state3640 : begin + ap_NS_fsm = ap_ST_fsm_state3641; + end + ap_ST_fsm_state3641 : begin + ap_NS_fsm = ap_ST_fsm_state3642; + end + ap_ST_fsm_state3642 : begin + ap_NS_fsm = ap_ST_fsm_state3643; + end + ap_ST_fsm_state3643 : begin + ap_NS_fsm = ap_ST_fsm_state3644; + end + ap_ST_fsm_state3644 : begin + ap_NS_fsm = ap_ST_fsm_state3645; + end + ap_ST_fsm_state3645 : begin + ap_NS_fsm = ap_ST_fsm_state3646; + end + ap_ST_fsm_state3646 : begin + ap_NS_fsm = ap_ST_fsm_state3647; + end + ap_ST_fsm_state3647 : begin + ap_NS_fsm = ap_ST_fsm_state3648; + end + ap_ST_fsm_state3648 : begin + ap_NS_fsm = ap_ST_fsm_state3649; + end + ap_ST_fsm_state3649 : begin + ap_NS_fsm = ap_ST_fsm_state3573; + end + ap_ST_fsm_state3650 : begin + ap_NS_fsm = ap_ST_fsm_state3651; + end + ap_ST_fsm_state3651 : begin + ap_NS_fsm = ap_ST_fsm_state3652; + end + ap_ST_fsm_state3652 : begin + ap_NS_fsm = ap_ST_fsm_state3653; + end + ap_ST_fsm_state3653 : begin + ap_NS_fsm = ap_ST_fsm_state3654; + end + ap_ST_fsm_state3654 : begin + ap_NS_fsm = ap_ST_fsm_state3655; + end + ap_ST_fsm_state3655 : begin + ap_NS_fsm = ap_ST_fsm_state3656; + end + ap_ST_fsm_state3656 : begin + ap_NS_fsm = ap_ST_fsm_state3657; + end + ap_ST_fsm_state3657 : begin + ap_NS_fsm = ap_ST_fsm_state3658; + end + ap_ST_fsm_state3658 : begin + ap_NS_fsm = ap_ST_fsm_state3659; + end + ap_ST_fsm_state3659 : begin + ap_NS_fsm = ap_ST_fsm_state3660; + end + ap_ST_fsm_state3660 : begin + ap_NS_fsm = ap_ST_fsm_state3661; + end + ap_ST_fsm_state3661 : begin + ap_NS_fsm = ap_ST_fsm_state3662; + end + ap_ST_fsm_state3662 : begin + ap_NS_fsm = ap_ST_fsm_state3663; + end + ap_ST_fsm_state3663 : begin + ap_NS_fsm = ap_ST_fsm_state3664; + end + ap_ST_fsm_state3664 : begin + ap_NS_fsm = ap_ST_fsm_state3665; + end + ap_ST_fsm_state3665 : begin + ap_NS_fsm = ap_ST_fsm_state3666; + end + ap_ST_fsm_state3666 : begin + ap_NS_fsm = ap_ST_fsm_state3667; + end + ap_ST_fsm_state3667 : begin + ap_NS_fsm = ap_ST_fsm_state3668; + end + ap_ST_fsm_state3668 : begin + ap_NS_fsm = ap_ST_fsm_state3669; + end + ap_ST_fsm_state3669 : begin + ap_NS_fsm = ap_ST_fsm_state3670; + end + ap_ST_fsm_state3670 : begin + ap_NS_fsm = ap_ST_fsm_state3671; + end + ap_ST_fsm_state3671 : begin + ap_NS_fsm = ap_ST_fsm_state3672; + end + ap_ST_fsm_state3672 : begin + ap_NS_fsm = ap_ST_fsm_state3673; + end + ap_ST_fsm_state3673 : begin + ap_NS_fsm = ap_ST_fsm_state3674; + end + ap_ST_fsm_state3674 : begin + ap_NS_fsm = ap_ST_fsm_state3675; + end + ap_ST_fsm_state3675 : begin + ap_NS_fsm = ap_ST_fsm_state3676; + end + ap_ST_fsm_state3676 : begin + ap_NS_fsm = ap_ST_fsm_state3677; + end + ap_ST_fsm_state3677 : begin + ap_NS_fsm = ap_ST_fsm_state3678; + end + ap_ST_fsm_state3678 : begin + ap_NS_fsm = ap_ST_fsm_state3679; + end + ap_ST_fsm_state3679 : begin + ap_NS_fsm = ap_ST_fsm_state3680; + end + ap_ST_fsm_state3680 : begin + ap_NS_fsm = ap_ST_fsm_state3681; + end + ap_ST_fsm_state3681 : begin + ap_NS_fsm = ap_ST_fsm_state3682; + end + ap_ST_fsm_state3682 : begin + ap_NS_fsm = ap_ST_fsm_state3683; + end + ap_ST_fsm_state3683 : begin + ap_NS_fsm = ap_ST_fsm_state3684; + end + ap_ST_fsm_state3684 : begin + ap_NS_fsm = ap_ST_fsm_state3685; + end + ap_ST_fsm_state3685 : begin + ap_NS_fsm = ap_ST_fsm_state3686; + end + ap_ST_fsm_state3686 : begin + ap_NS_fsm = ap_ST_fsm_state3687; + end + ap_ST_fsm_state3687 : begin + ap_NS_fsm = ap_ST_fsm_state3688; + end + ap_ST_fsm_state3688 : begin + if (((icmp_ln266_14_fu_123742_p2 == 1'd1) & (icmp_ln268_21_fu_123719_p2 == 1'd1) & (ap_ST_fsm_state3688 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3494; + end else if (((icmp_ln268_21_fu_123719_p2 == 1'd1) & (ap_ST_fsm_state3688 == ap_CS_fsm) & (icmp_ln266_14_fu_123742_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state3726; + end else begin + ap_NS_fsm = ap_ST_fsm_state3689; + end + end + ap_ST_fsm_state3689 : begin + ap_NS_fsm = ap_ST_fsm_state3690; + end + ap_ST_fsm_state3690 : begin + ap_NS_fsm = ap_ST_fsm_state3691; + end + ap_ST_fsm_state3691 : begin + ap_NS_fsm = ap_ST_fsm_state3692; + end + ap_ST_fsm_state3692 : begin + ap_NS_fsm = ap_ST_fsm_state3693; + end + ap_ST_fsm_state3693 : begin + ap_NS_fsm = ap_ST_fsm_state3694; + end + ap_ST_fsm_state3694 : begin + ap_NS_fsm = ap_ST_fsm_state3695; + end + ap_ST_fsm_state3695 : begin + ap_NS_fsm = ap_ST_fsm_state3696; + end + ap_ST_fsm_state3696 : begin + ap_NS_fsm = ap_ST_fsm_state3697; + end + ap_ST_fsm_state3697 : begin + ap_NS_fsm = ap_ST_fsm_state3698; + end + ap_ST_fsm_state3698 : begin + ap_NS_fsm = ap_ST_fsm_state3699; + end + ap_ST_fsm_state3699 : begin + ap_NS_fsm = ap_ST_fsm_state3700; + end + ap_ST_fsm_state3700 : begin + ap_NS_fsm = ap_ST_fsm_state3701; + end + ap_ST_fsm_state3701 : begin + ap_NS_fsm = ap_ST_fsm_state3702; + end + ap_ST_fsm_state3702 : begin + ap_NS_fsm = ap_ST_fsm_state3703; + end + ap_ST_fsm_state3703 : begin + ap_NS_fsm = ap_ST_fsm_state3704; + end + ap_ST_fsm_state3704 : begin + ap_NS_fsm = ap_ST_fsm_state3705; + end + ap_ST_fsm_state3705 : begin + ap_NS_fsm = ap_ST_fsm_state3706; + end + ap_ST_fsm_state3706 : begin + ap_NS_fsm = ap_ST_fsm_state3707; + end + ap_ST_fsm_state3707 : begin + ap_NS_fsm = ap_ST_fsm_state3708; + end + ap_ST_fsm_state3708 : begin + ap_NS_fsm = ap_ST_fsm_state3709; + end + ap_ST_fsm_state3709 : begin + ap_NS_fsm = ap_ST_fsm_state3710; + end + ap_ST_fsm_state3710 : begin + ap_NS_fsm = ap_ST_fsm_state3711; + end + ap_ST_fsm_state3711 : begin + ap_NS_fsm = ap_ST_fsm_state3712; + end + ap_ST_fsm_state3712 : begin + ap_NS_fsm = ap_ST_fsm_state3713; + end + ap_ST_fsm_state3713 : begin + ap_NS_fsm = ap_ST_fsm_state3714; + end + ap_ST_fsm_state3714 : begin + ap_NS_fsm = ap_ST_fsm_state3715; + end + ap_ST_fsm_state3715 : begin + ap_NS_fsm = ap_ST_fsm_state3716; + end + ap_ST_fsm_state3716 : begin + ap_NS_fsm = ap_ST_fsm_state3717; + end + ap_ST_fsm_state3717 : begin + ap_NS_fsm = ap_ST_fsm_state3718; + end + ap_ST_fsm_state3718 : begin + ap_NS_fsm = ap_ST_fsm_state3719; + end + ap_ST_fsm_state3719 : begin + ap_NS_fsm = ap_ST_fsm_state3720; + end + ap_ST_fsm_state3720 : begin + ap_NS_fsm = ap_ST_fsm_state3721; + end + ap_ST_fsm_state3721 : begin + ap_NS_fsm = ap_ST_fsm_state3722; + end + ap_ST_fsm_state3722 : begin + ap_NS_fsm = ap_ST_fsm_state3723; + end + ap_ST_fsm_state3723 : begin + ap_NS_fsm = ap_ST_fsm_state3724; + end + ap_ST_fsm_state3724 : begin + ap_NS_fsm = ap_ST_fsm_state3725; + end + ap_ST_fsm_state3725 : begin + ap_NS_fsm = ap_ST_fsm_state3651; + end + ap_ST_fsm_state3726 : begin + ap_NS_fsm = ap_ST_fsm_state3727; + end + ap_ST_fsm_state3727 : begin + ap_NS_fsm = ap_ST_fsm_state3728; + end + ap_ST_fsm_state3728 : begin + ap_NS_fsm = ap_ST_fsm_state3729; + end + ap_ST_fsm_state3729 : begin + ap_NS_fsm = ap_ST_fsm_state3730; + end + ap_ST_fsm_state3730 : begin + ap_NS_fsm = ap_ST_fsm_state3731; + end + ap_ST_fsm_state3731 : begin + ap_NS_fsm = ap_ST_fsm_state3732; + end + ap_ST_fsm_state3732 : begin + ap_NS_fsm = ap_ST_fsm_state3733; + end + ap_ST_fsm_state3733 : begin + ap_NS_fsm = ap_ST_fsm_state3734; + end + ap_ST_fsm_state3734 : begin + ap_NS_fsm = ap_ST_fsm_state3735; + end + ap_ST_fsm_state3735 : begin + ap_NS_fsm = ap_ST_fsm_state3736; + end + ap_ST_fsm_state3736 : begin + ap_NS_fsm = ap_ST_fsm_state3737; + end + ap_ST_fsm_state3737 : begin + ap_NS_fsm = ap_ST_fsm_state3738; + end + ap_ST_fsm_state3738 : begin + ap_NS_fsm = ap_ST_fsm_state3739; + end + ap_ST_fsm_state3739 : begin + ap_NS_fsm = ap_ST_fsm_state3740; + end + ap_ST_fsm_state3740 : begin + ap_NS_fsm = ap_ST_fsm_state3741; + end + ap_ST_fsm_state3741 : begin + ap_NS_fsm = ap_ST_fsm_state3742; + end + ap_ST_fsm_state3742 : begin + ap_NS_fsm = ap_ST_fsm_state3743; + end + ap_ST_fsm_state3743 : begin + ap_NS_fsm = ap_ST_fsm_state3744; + end + ap_ST_fsm_state3744 : begin + ap_NS_fsm = ap_ST_fsm_state3745; + end + ap_ST_fsm_state3745 : begin + ap_NS_fsm = ap_ST_fsm_state3746; + end + ap_ST_fsm_state3746 : begin + ap_NS_fsm = ap_ST_fsm_state3747; + end + ap_ST_fsm_state3747 : begin + ap_NS_fsm = ap_ST_fsm_state3748; + end + ap_ST_fsm_state3748 : begin + ap_NS_fsm = ap_ST_fsm_state3749; + end + ap_ST_fsm_state3749 : begin + ap_NS_fsm = ap_ST_fsm_state3750; + end + ap_ST_fsm_state3750 : begin + ap_NS_fsm = ap_ST_fsm_state3751; + end + ap_ST_fsm_state3751 : begin + ap_NS_fsm = ap_ST_fsm_state3752; + end + ap_ST_fsm_state3752 : begin + ap_NS_fsm = ap_ST_fsm_state3753; + end + ap_ST_fsm_state3753 : begin + ap_NS_fsm = ap_ST_fsm_state3754; + end + ap_ST_fsm_state3754 : begin + ap_NS_fsm = ap_ST_fsm_state3755; + end + ap_ST_fsm_state3755 : begin + ap_NS_fsm = ap_ST_fsm_state3756; + end + ap_ST_fsm_state3756 : begin + ap_NS_fsm = ap_ST_fsm_state3757; + end + ap_ST_fsm_state3757 : begin + ap_NS_fsm = ap_ST_fsm_state3758; + end + ap_ST_fsm_state3758 : begin + ap_NS_fsm = ap_ST_fsm_state3759; + end + ap_ST_fsm_state3759 : begin + ap_NS_fsm = ap_ST_fsm_state3760; + end + ap_ST_fsm_state3760 : begin + ap_NS_fsm = ap_ST_fsm_state3761; + end + ap_ST_fsm_state3761 : begin + ap_NS_fsm = ap_ST_fsm_state3762; + end + ap_ST_fsm_state3762 : begin + ap_NS_fsm = ap_ST_fsm_state3763; + end + ap_ST_fsm_state3763 : begin + if (((icmp_ln268_30_fu_124123_p2 == 1'd1) & (ap_ST_fsm_state3763 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3650; + end else begin + ap_NS_fsm = ap_ST_fsm_state3764; + end + end + ap_ST_fsm_state3764 : begin + ap_NS_fsm = ap_ST_fsm_state3765; + end + ap_ST_fsm_state3765 : begin + ap_NS_fsm = ap_ST_fsm_state3766; + end + ap_ST_fsm_state3766 : begin + ap_NS_fsm = ap_ST_fsm_state3767; + end + ap_ST_fsm_state3767 : begin + ap_NS_fsm = ap_ST_fsm_state3768; + end + ap_ST_fsm_state3768 : begin + ap_NS_fsm = ap_ST_fsm_state3769; + end + ap_ST_fsm_state3769 : begin + ap_NS_fsm = ap_ST_fsm_state3770; + end + ap_ST_fsm_state3770 : begin + ap_NS_fsm = ap_ST_fsm_state3771; + end + ap_ST_fsm_state3771 : begin + ap_NS_fsm = ap_ST_fsm_state3772; + end + ap_ST_fsm_state3772 : begin + ap_NS_fsm = ap_ST_fsm_state3773; + end + ap_ST_fsm_state3773 : begin + ap_NS_fsm = ap_ST_fsm_state3774; + end + ap_ST_fsm_state3774 : begin + ap_NS_fsm = ap_ST_fsm_state3775; + end + ap_ST_fsm_state3775 : begin + ap_NS_fsm = ap_ST_fsm_state3776; + end + ap_ST_fsm_state3776 : begin + ap_NS_fsm = ap_ST_fsm_state3777; + end + ap_ST_fsm_state3777 : begin + ap_NS_fsm = ap_ST_fsm_state3778; + end + ap_ST_fsm_state3778 : begin + ap_NS_fsm = ap_ST_fsm_state3779; + end + ap_ST_fsm_state3779 : begin + ap_NS_fsm = ap_ST_fsm_state3780; + end + ap_ST_fsm_state3780 : begin + ap_NS_fsm = ap_ST_fsm_state3781; + end + ap_ST_fsm_state3781 : begin + ap_NS_fsm = ap_ST_fsm_state3782; + end + ap_ST_fsm_state3782 : begin + ap_NS_fsm = ap_ST_fsm_state3783; + end + ap_ST_fsm_state3783 : begin + ap_NS_fsm = ap_ST_fsm_state3784; + end + ap_ST_fsm_state3784 : begin + ap_NS_fsm = ap_ST_fsm_state3785; + end + ap_ST_fsm_state3785 : begin + ap_NS_fsm = ap_ST_fsm_state3786; + end + ap_ST_fsm_state3786 : begin + ap_NS_fsm = ap_ST_fsm_state3787; + end + ap_ST_fsm_state3787 : begin + ap_NS_fsm = ap_ST_fsm_state3788; + end + ap_ST_fsm_state3788 : begin + ap_NS_fsm = ap_ST_fsm_state3789; + end + ap_ST_fsm_state3789 : begin + ap_NS_fsm = ap_ST_fsm_state3790; + end + ap_ST_fsm_state3790 : begin + ap_NS_fsm = ap_ST_fsm_state3791; + end + ap_ST_fsm_state3791 : begin + ap_NS_fsm = ap_ST_fsm_state3792; + end + ap_ST_fsm_state3792 : begin + ap_NS_fsm = ap_ST_fsm_state3793; + end + ap_ST_fsm_state3793 : begin + ap_NS_fsm = ap_ST_fsm_state3794; + end + ap_ST_fsm_state3794 : begin + ap_NS_fsm = ap_ST_fsm_state3795; + end + ap_ST_fsm_state3795 : begin + ap_NS_fsm = ap_ST_fsm_state3796; + end + ap_ST_fsm_state3796 : begin + ap_NS_fsm = ap_ST_fsm_state3797; + end + ap_ST_fsm_state3797 : begin + ap_NS_fsm = ap_ST_fsm_state3798; + end + ap_ST_fsm_state3798 : begin + ap_NS_fsm = ap_ST_fsm_state3799; + end + ap_ST_fsm_state3799 : begin + ap_NS_fsm = ap_ST_fsm_state3726; + end + ap_ST_fsm_state3800 : begin + if (((icmp_ln259_1_fu_124304_p2 == 1'd1) & (ap_ST_fsm_state3800 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2568; + end else begin + ap_NS_fsm = ap_ST_fsm_state3801; + end + end + ap_ST_fsm_state3801 : begin + if (((icmp_ln261_1_fu_124367_p2 == 1'd1) & (ap_ST_fsm_state3801 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4415; + end else begin + ap_NS_fsm = ap_ST_fsm_state3802; + end + end + ap_ST_fsm_state3802 : begin + if (((icmp_ln264_1_fu_124526_p2 == 1'd1) & (ap_ST_fsm_state3802 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4109; + end else begin + ap_NS_fsm = ap_ST_fsm_state3803; + end + end + ap_ST_fsm_state3803 : begin + ap_NS_fsm = ap_ST_fsm_state3804; + end + ap_ST_fsm_state3804 : begin + ap_NS_fsm = ap_ST_fsm_state3805; + end + ap_ST_fsm_state3805 : begin + ap_NS_fsm = ap_ST_fsm_state3806; + end + ap_ST_fsm_state3806 : begin + ap_NS_fsm = ap_ST_fsm_state3807; + end + ap_ST_fsm_state3807 : begin + ap_NS_fsm = ap_ST_fsm_state3808; + end + ap_ST_fsm_state3808 : begin + ap_NS_fsm = ap_ST_fsm_state3809; + end + ap_ST_fsm_state3809 : begin + ap_NS_fsm = ap_ST_fsm_state3810; + end + ap_ST_fsm_state3810 : begin + ap_NS_fsm = ap_ST_fsm_state3811; + end + ap_ST_fsm_state3811 : begin + ap_NS_fsm = ap_ST_fsm_state3812; + end + ap_ST_fsm_state3812 : begin + ap_NS_fsm = ap_ST_fsm_state3813; + end + ap_ST_fsm_state3813 : begin + ap_NS_fsm = ap_ST_fsm_state3814; + end + ap_ST_fsm_state3814 : begin + ap_NS_fsm = ap_ST_fsm_state3815; + end + ap_ST_fsm_state3815 : begin + ap_NS_fsm = ap_ST_fsm_state3816; + end + ap_ST_fsm_state3816 : begin + ap_NS_fsm = ap_ST_fsm_state3817; + end + ap_ST_fsm_state3817 : begin + ap_NS_fsm = ap_ST_fsm_state3818; + end + ap_ST_fsm_state3818 : begin + ap_NS_fsm = ap_ST_fsm_state3819; + end + ap_ST_fsm_state3819 : begin + ap_NS_fsm = ap_ST_fsm_state3820; + end + ap_ST_fsm_state3820 : begin + ap_NS_fsm = ap_ST_fsm_state3821; + end + ap_ST_fsm_state3821 : begin + ap_NS_fsm = ap_ST_fsm_state3822; + end + ap_ST_fsm_state3822 : begin + ap_NS_fsm = ap_ST_fsm_state3823; + end + ap_ST_fsm_state3823 : begin + ap_NS_fsm = ap_ST_fsm_state3824; + end + ap_ST_fsm_state3824 : begin + ap_NS_fsm = ap_ST_fsm_state3825; + end + ap_ST_fsm_state3825 : begin + ap_NS_fsm = ap_ST_fsm_state3826; + end + ap_ST_fsm_state3826 : begin + ap_NS_fsm = ap_ST_fsm_state3827; + end + ap_ST_fsm_state3827 : begin + ap_NS_fsm = ap_ST_fsm_state3828; + end + ap_ST_fsm_state3828 : begin + ap_NS_fsm = ap_ST_fsm_state3829; + end + ap_ST_fsm_state3829 : begin + ap_NS_fsm = ap_ST_fsm_state3830; + end + ap_ST_fsm_state3830 : begin + ap_NS_fsm = ap_ST_fsm_state3831; + end + ap_ST_fsm_state3831 : begin + ap_NS_fsm = ap_ST_fsm_state3832; + end + ap_ST_fsm_state3832 : begin + ap_NS_fsm = ap_ST_fsm_state3833; + end + ap_ST_fsm_state3833 : begin + ap_NS_fsm = ap_ST_fsm_state3834; + end + ap_ST_fsm_state3834 : begin + ap_NS_fsm = ap_ST_fsm_state3835; + end + ap_ST_fsm_state3835 : begin + ap_NS_fsm = ap_ST_fsm_state3836; + end + ap_ST_fsm_state3836 : begin + ap_NS_fsm = ap_ST_fsm_state3837; + end + ap_ST_fsm_state3837 : begin + ap_NS_fsm = ap_ST_fsm_state3838; + end + ap_ST_fsm_state3838 : begin + ap_NS_fsm = ap_ST_fsm_state3839; + end + ap_ST_fsm_state3839 : begin + ap_NS_fsm = ap_ST_fsm_state3840; + end + ap_ST_fsm_state3840 : begin + ap_NS_fsm = ap_ST_fsm_state3841; + end + ap_ST_fsm_state3841 : begin + ap_NS_fsm = ap_ST_fsm_state3842; + end + ap_ST_fsm_state3842 : begin + ap_NS_fsm = ap_ST_fsm_state3843; + end + ap_ST_fsm_state3843 : begin + if (((icmp_ln266_1_fu_124883_p2 == 1'd1) & (icmp_ln268_1_fu_124860_p2 == 1'd1) & (ap_ST_fsm_state3843 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3958; + end else if (((icmp_ln268_1_fu_124860_p2 == 1'd1) & (ap_ST_fsm_state3843 == ap_CS_fsm) & (icmp_ln266_1_fu_124883_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state3881; + end else begin + ap_NS_fsm = ap_ST_fsm_state3844; + end + end + ap_ST_fsm_state3844 : begin + ap_NS_fsm = ap_ST_fsm_state3845; + end + ap_ST_fsm_state3845 : begin + ap_NS_fsm = ap_ST_fsm_state3846; + end + ap_ST_fsm_state3846 : begin + ap_NS_fsm = ap_ST_fsm_state3847; + end + ap_ST_fsm_state3847 : begin + ap_NS_fsm = ap_ST_fsm_state3848; + end + ap_ST_fsm_state3848 : begin + ap_NS_fsm = ap_ST_fsm_state3849; + end + ap_ST_fsm_state3849 : begin + ap_NS_fsm = ap_ST_fsm_state3850; + end + ap_ST_fsm_state3850 : begin + ap_NS_fsm = ap_ST_fsm_state3851; + end + ap_ST_fsm_state3851 : begin + ap_NS_fsm = ap_ST_fsm_state3852; + end + ap_ST_fsm_state3852 : begin + ap_NS_fsm = ap_ST_fsm_state3853; + end + ap_ST_fsm_state3853 : begin + ap_NS_fsm = ap_ST_fsm_state3854; + end + ap_ST_fsm_state3854 : begin + ap_NS_fsm = ap_ST_fsm_state3855; + end + ap_ST_fsm_state3855 : begin + ap_NS_fsm = ap_ST_fsm_state3856; + end + ap_ST_fsm_state3856 : begin + ap_NS_fsm = ap_ST_fsm_state3857; + end + ap_ST_fsm_state3857 : begin + ap_NS_fsm = ap_ST_fsm_state3858; + end + ap_ST_fsm_state3858 : begin + ap_NS_fsm = ap_ST_fsm_state3859; + end + ap_ST_fsm_state3859 : begin + ap_NS_fsm = ap_ST_fsm_state3860; + end + ap_ST_fsm_state3860 : begin + ap_NS_fsm = ap_ST_fsm_state3861; + end + ap_ST_fsm_state3861 : begin + ap_NS_fsm = ap_ST_fsm_state3862; + end + ap_ST_fsm_state3862 : begin + ap_NS_fsm = ap_ST_fsm_state3863; + end + ap_ST_fsm_state3863 : begin + ap_NS_fsm = ap_ST_fsm_state3864; + end + ap_ST_fsm_state3864 : begin + ap_NS_fsm = ap_ST_fsm_state3865; + end + ap_ST_fsm_state3865 : begin + ap_NS_fsm = ap_ST_fsm_state3866; + end + ap_ST_fsm_state3866 : begin + ap_NS_fsm = ap_ST_fsm_state3867; + end + ap_ST_fsm_state3867 : begin + ap_NS_fsm = ap_ST_fsm_state3868; + end + ap_ST_fsm_state3868 : begin + ap_NS_fsm = ap_ST_fsm_state3869; + end + ap_ST_fsm_state3869 : begin + ap_NS_fsm = ap_ST_fsm_state3870; + end + ap_ST_fsm_state3870 : begin + ap_NS_fsm = ap_ST_fsm_state3871; + end + ap_ST_fsm_state3871 : begin + ap_NS_fsm = ap_ST_fsm_state3872; + end + ap_ST_fsm_state3872 : begin + ap_NS_fsm = ap_ST_fsm_state3873; + end + ap_ST_fsm_state3873 : begin + ap_NS_fsm = ap_ST_fsm_state3874; + end + ap_ST_fsm_state3874 : begin + ap_NS_fsm = ap_ST_fsm_state3875; + end + ap_ST_fsm_state3875 : begin + ap_NS_fsm = ap_ST_fsm_state3876; + end + ap_ST_fsm_state3876 : begin + ap_NS_fsm = ap_ST_fsm_state3877; + end + ap_ST_fsm_state3877 : begin + ap_NS_fsm = ap_ST_fsm_state3878; + end + ap_ST_fsm_state3878 : begin + ap_NS_fsm = ap_ST_fsm_state3879; + end + ap_ST_fsm_state3879 : begin + ap_NS_fsm = ap_ST_fsm_state3880; + end + ap_ST_fsm_state3880 : begin + ap_NS_fsm = ap_ST_fsm_state3804; + end + ap_ST_fsm_state3881 : begin + ap_NS_fsm = ap_ST_fsm_state3882; + end + ap_ST_fsm_state3882 : begin + ap_NS_fsm = ap_ST_fsm_state3883; + end + ap_ST_fsm_state3883 : begin + ap_NS_fsm = ap_ST_fsm_state3884; + end + ap_ST_fsm_state3884 : begin + ap_NS_fsm = ap_ST_fsm_state3885; + end + ap_ST_fsm_state3885 : begin + ap_NS_fsm = ap_ST_fsm_state3886; + end + ap_ST_fsm_state3886 : begin + ap_NS_fsm = ap_ST_fsm_state3887; + end + ap_ST_fsm_state3887 : begin + ap_NS_fsm = ap_ST_fsm_state3888; + end + ap_ST_fsm_state3888 : begin + ap_NS_fsm = ap_ST_fsm_state3889; + end + ap_ST_fsm_state3889 : begin + ap_NS_fsm = ap_ST_fsm_state3890; + end + ap_ST_fsm_state3890 : begin + ap_NS_fsm = ap_ST_fsm_state3891; + end + ap_ST_fsm_state3891 : begin + ap_NS_fsm = ap_ST_fsm_state3892; + end + ap_ST_fsm_state3892 : begin + ap_NS_fsm = ap_ST_fsm_state3893; + end + ap_ST_fsm_state3893 : begin + ap_NS_fsm = ap_ST_fsm_state3894; + end + ap_ST_fsm_state3894 : begin + ap_NS_fsm = ap_ST_fsm_state3895; + end + ap_ST_fsm_state3895 : begin + ap_NS_fsm = ap_ST_fsm_state3896; + end + ap_ST_fsm_state3896 : begin + ap_NS_fsm = ap_ST_fsm_state3897; + end + ap_ST_fsm_state3897 : begin + ap_NS_fsm = ap_ST_fsm_state3898; + end + ap_ST_fsm_state3898 : begin + ap_NS_fsm = ap_ST_fsm_state3899; + end + ap_ST_fsm_state3899 : begin + ap_NS_fsm = ap_ST_fsm_state3900; + end + ap_ST_fsm_state3900 : begin + ap_NS_fsm = ap_ST_fsm_state3901; + end + ap_ST_fsm_state3901 : begin + ap_NS_fsm = ap_ST_fsm_state3902; + end + ap_ST_fsm_state3902 : begin + ap_NS_fsm = ap_ST_fsm_state3903; + end + ap_ST_fsm_state3903 : begin + ap_NS_fsm = ap_ST_fsm_state3904; + end + ap_ST_fsm_state3904 : begin + ap_NS_fsm = ap_ST_fsm_state3905; + end + ap_ST_fsm_state3905 : begin + ap_NS_fsm = ap_ST_fsm_state3906; + end + ap_ST_fsm_state3906 : begin + ap_NS_fsm = ap_ST_fsm_state3907; + end + ap_ST_fsm_state3907 : begin + ap_NS_fsm = ap_ST_fsm_state3908; + end + ap_ST_fsm_state3908 : begin + ap_NS_fsm = ap_ST_fsm_state3909; + end + ap_ST_fsm_state3909 : begin + ap_NS_fsm = ap_ST_fsm_state3910; + end + ap_ST_fsm_state3910 : begin + ap_NS_fsm = ap_ST_fsm_state3911; + end + ap_ST_fsm_state3911 : begin + ap_NS_fsm = ap_ST_fsm_state3912; + end + ap_ST_fsm_state3912 : begin + ap_NS_fsm = ap_ST_fsm_state3913; + end + ap_ST_fsm_state3913 : begin + ap_NS_fsm = ap_ST_fsm_state3914; + end + ap_ST_fsm_state3914 : begin + ap_NS_fsm = ap_ST_fsm_state3915; + end + ap_ST_fsm_state3915 : begin + ap_NS_fsm = ap_ST_fsm_state3916; + end + ap_ST_fsm_state3916 : begin + ap_NS_fsm = ap_ST_fsm_state3917; + end + ap_ST_fsm_state3917 : begin + ap_NS_fsm = ap_ST_fsm_state3918; + end + ap_ST_fsm_state3918 : begin + ap_NS_fsm = ap_ST_fsm_state3919; + end + ap_ST_fsm_state3919 : begin + ap_NS_fsm = ap_ST_fsm_state3920; + end + ap_ST_fsm_state3920 : begin + if (((icmp_ln268_10_fu_125276_p2 == 1'd1) & (ap_ST_fsm_state3920 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3803; + end else begin + ap_NS_fsm = ap_ST_fsm_state3921; + end + end + ap_ST_fsm_state3921 : begin + ap_NS_fsm = ap_ST_fsm_state3922; + end + ap_ST_fsm_state3922 : begin + ap_NS_fsm = ap_ST_fsm_state3923; + end + ap_ST_fsm_state3923 : begin + ap_NS_fsm = ap_ST_fsm_state3924; + end + ap_ST_fsm_state3924 : begin + ap_NS_fsm = ap_ST_fsm_state3925; + end + ap_ST_fsm_state3925 : begin + ap_NS_fsm = ap_ST_fsm_state3926; + end + ap_ST_fsm_state3926 : begin + ap_NS_fsm = ap_ST_fsm_state3927; + end + ap_ST_fsm_state3927 : begin + ap_NS_fsm = ap_ST_fsm_state3928; + end + ap_ST_fsm_state3928 : begin + ap_NS_fsm = ap_ST_fsm_state3929; + end + ap_ST_fsm_state3929 : begin + ap_NS_fsm = ap_ST_fsm_state3930; + end + ap_ST_fsm_state3930 : begin + ap_NS_fsm = ap_ST_fsm_state3931; + end + ap_ST_fsm_state3931 : begin + ap_NS_fsm = ap_ST_fsm_state3932; + end + ap_ST_fsm_state3932 : begin + ap_NS_fsm = ap_ST_fsm_state3933; + end + ap_ST_fsm_state3933 : begin + ap_NS_fsm = ap_ST_fsm_state3934; + end + ap_ST_fsm_state3934 : begin + ap_NS_fsm = ap_ST_fsm_state3935; + end + ap_ST_fsm_state3935 : begin + ap_NS_fsm = ap_ST_fsm_state3936; + end + ap_ST_fsm_state3936 : begin + ap_NS_fsm = ap_ST_fsm_state3937; + end + ap_ST_fsm_state3937 : begin + ap_NS_fsm = ap_ST_fsm_state3938; + end + ap_ST_fsm_state3938 : begin + ap_NS_fsm = ap_ST_fsm_state3939; + end + ap_ST_fsm_state3939 : begin + ap_NS_fsm = ap_ST_fsm_state3940; + end + ap_ST_fsm_state3940 : begin + ap_NS_fsm = ap_ST_fsm_state3941; + end + ap_ST_fsm_state3941 : begin + ap_NS_fsm = ap_ST_fsm_state3942; + end + ap_ST_fsm_state3942 : begin + ap_NS_fsm = ap_ST_fsm_state3943; + end + ap_ST_fsm_state3943 : begin + ap_NS_fsm = ap_ST_fsm_state3944; + end + ap_ST_fsm_state3944 : begin + ap_NS_fsm = ap_ST_fsm_state3945; + end + ap_ST_fsm_state3945 : begin + ap_NS_fsm = ap_ST_fsm_state3946; + end + ap_ST_fsm_state3946 : begin + ap_NS_fsm = ap_ST_fsm_state3947; + end + ap_ST_fsm_state3947 : begin + ap_NS_fsm = ap_ST_fsm_state3948; + end + ap_ST_fsm_state3948 : begin + ap_NS_fsm = ap_ST_fsm_state3949; + end + ap_ST_fsm_state3949 : begin + ap_NS_fsm = ap_ST_fsm_state3950; + end + ap_ST_fsm_state3950 : begin + ap_NS_fsm = ap_ST_fsm_state3951; + end + ap_ST_fsm_state3951 : begin + ap_NS_fsm = ap_ST_fsm_state3952; + end + ap_ST_fsm_state3952 : begin + ap_NS_fsm = ap_ST_fsm_state3953; + end + ap_ST_fsm_state3953 : begin + ap_NS_fsm = ap_ST_fsm_state3954; + end + ap_ST_fsm_state3954 : begin + ap_NS_fsm = ap_ST_fsm_state3955; + end + ap_ST_fsm_state3955 : begin + ap_NS_fsm = ap_ST_fsm_state3956; + end + ap_ST_fsm_state3956 : begin + ap_NS_fsm = ap_ST_fsm_state3957; + end + ap_ST_fsm_state3957 : begin + ap_NS_fsm = ap_ST_fsm_state3881; + end + ap_ST_fsm_state3958 : begin + ap_NS_fsm = ap_ST_fsm_state3959; + end + ap_ST_fsm_state3959 : begin + ap_NS_fsm = ap_ST_fsm_state3960; + end + ap_ST_fsm_state3960 : begin + ap_NS_fsm = ap_ST_fsm_state3961; + end + ap_ST_fsm_state3961 : begin + ap_NS_fsm = ap_ST_fsm_state3962; + end + ap_ST_fsm_state3962 : begin + ap_NS_fsm = ap_ST_fsm_state3963; + end + ap_ST_fsm_state3963 : begin + ap_NS_fsm = ap_ST_fsm_state3964; + end + ap_ST_fsm_state3964 : begin + ap_NS_fsm = ap_ST_fsm_state3965; + end + ap_ST_fsm_state3965 : begin + ap_NS_fsm = ap_ST_fsm_state3966; + end + ap_ST_fsm_state3966 : begin + ap_NS_fsm = ap_ST_fsm_state3967; + end + ap_ST_fsm_state3967 : begin + ap_NS_fsm = ap_ST_fsm_state3968; + end + ap_ST_fsm_state3968 : begin + ap_NS_fsm = ap_ST_fsm_state3969; + end + ap_ST_fsm_state3969 : begin + ap_NS_fsm = ap_ST_fsm_state3970; + end + ap_ST_fsm_state3970 : begin + ap_NS_fsm = ap_ST_fsm_state3971; + end + ap_ST_fsm_state3971 : begin + ap_NS_fsm = ap_ST_fsm_state3972; + end + ap_ST_fsm_state3972 : begin + ap_NS_fsm = ap_ST_fsm_state3973; + end + ap_ST_fsm_state3973 : begin + ap_NS_fsm = ap_ST_fsm_state3974; + end + ap_ST_fsm_state3974 : begin + ap_NS_fsm = ap_ST_fsm_state3975; + end + ap_ST_fsm_state3975 : begin + ap_NS_fsm = ap_ST_fsm_state3976; + end + ap_ST_fsm_state3976 : begin + ap_NS_fsm = ap_ST_fsm_state3977; + end + ap_ST_fsm_state3977 : begin + ap_NS_fsm = ap_ST_fsm_state3978; + end + ap_ST_fsm_state3978 : begin + ap_NS_fsm = ap_ST_fsm_state3979; + end + ap_ST_fsm_state3979 : begin + ap_NS_fsm = ap_ST_fsm_state3980; + end + ap_ST_fsm_state3980 : begin + ap_NS_fsm = ap_ST_fsm_state3981; + end + ap_ST_fsm_state3981 : begin + ap_NS_fsm = ap_ST_fsm_state3982; + end + ap_ST_fsm_state3982 : begin + ap_NS_fsm = ap_ST_fsm_state3983; + end + ap_ST_fsm_state3983 : begin + ap_NS_fsm = ap_ST_fsm_state3984; + end + ap_ST_fsm_state3984 : begin + ap_NS_fsm = ap_ST_fsm_state3985; + end + ap_ST_fsm_state3985 : begin + ap_NS_fsm = ap_ST_fsm_state3986; + end + ap_ST_fsm_state3986 : begin + ap_NS_fsm = ap_ST_fsm_state3987; + end + ap_ST_fsm_state3987 : begin + ap_NS_fsm = ap_ST_fsm_state3988; + end + ap_ST_fsm_state3988 : begin + ap_NS_fsm = ap_ST_fsm_state3989; + end + ap_ST_fsm_state3989 : begin + ap_NS_fsm = ap_ST_fsm_state3990; + end + ap_ST_fsm_state3990 : begin + ap_NS_fsm = ap_ST_fsm_state3991; + end + ap_ST_fsm_state3991 : begin + ap_NS_fsm = ap_ST_fsm_state3992; + end + ap_ST_fsm_state3992 : begin + ap_NS_fsm = ap_ST_fsm_state3993; + end + ap_ST_fsm_state3993 : begin + ap_NS_fsm = ap_ST_fsm_state3994; + end + ap_ST_fsm_state3994 : begin + ap_NS_fsm = ap_ST_fsm_state3995; + end + ap_ST_fsm_state3995 : begin + ap_NS_fsm = ap_ST_fsm_state3996; + end + ap_ST_fsm_state3996 : begin + ap_NS_fsm = ap_ST_fsm_state3997; + end + ap_ST_fsm_state3997 : begin + if (((icmp_ln266_9_fu_125692_p2 == 1'd1) & (icmp_ln268_13_fu_125669_p2 == 1'd1) & (ap_ST_fsm_state3997 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3802; + end else if (((icmp_ln268_13_fu_125669_p2 == 1'd1) & (ap_ST_fsm_state3997 == ap_CS_fsm) & (icmp_ln266_9_fu_125692_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state4035; + end else begin + ap_NS_fsm = ap_ST_fsm_state3998; + end + end + ap_ST_fsm_state3998 : begin + ap_NS_fsm = ap_ST_fsm_state3999; + end + ap_ST_fsm_state3999 : begin + ap_NS_fsm = ap_ST_fsm_state4000; + end + ap_ST_fsm_state4000 : begin + ap_NS_fsm = ap_ST_fsm_state4001; + end + ap_ST_fsm_state4001 : begin + ap_NS_fsm = ap_ST_fsm_state4002; + end + ap_ST_fsm_state4002 : begin + ap_NS_fsm = ap_ST_fsm_state4003; + end + ap_ST_fsm_state4003 : begin + ap_NS_fsm = ap_ST_fsm_state4004; + end + ap_ST_fsm_state4004 : begin + ap_NS_fsm = ap_ST_fsm_state4005; + end + ap_ST_fsm_state4005 : begin + ap_NS_fsm = ap_ST_fsm_state4006; + end + ap_ST_fsm_state4006 : begin + ap_NS_fsm = ap_ST_fsm_state4007; + end + ap_ST_fsm_state4007 : begin + ap_NS_fsm = ap_ST_fsm_state4008; + end + ap_ST_fsm_state4008 : begin + ap_NS_fsm = ap_ST_fsm_state4009; + end + ap_ST_fsm_state4009 : begin + ap_NS_fsm = ap_ST_fsm_state4010; + end + ap_ST_fsm_state4010 : begin + ap_NS_fsm = ap_ST_fsm_state4011; + end + ap_ST_fsm_state4011 : begin + ap_NS_fsm = ap_ST_fsm_state4012; + end + ap_ST_fsm_state4012 : begin + ap_NS_fsm = ap_ST_fsm_state4013; + end + ap_ST_fsm_state4013 : begin + ap_NS_fsm = ap_ST_fsm_state4014; + end + ap_ST_fsm_state4014 : begin + ap_NS_fsm = ap_ST_fsm_state4015; + end + ap_ST_fsm_state4015 : begin + ap_NS_fsm = ap_ST_fsm_state4016; + end + ap_ST_fsm_state4016 : begin + ap_NS_fsm = ap_ST_fsm_state4017; + end + ap_ST_fsm_state4017 : begin + ap_NS_fsm = ap_ST_fsm_state4018; + end + ap_ST_fsm_state4018 : begin + ap_NS_fsm = ap_ST_fsm_state4019; + end + ap_ST_fsm_state4019 : begin + ap_NS_fsm = ap_ST_fsm_state4020; + end + ap_ST_fsm_state4020 : begin + ap_NS_fsm = ap_ST_fsm_state4021; + end + ap_ST_fsm_state4021 : begin + ap_NS_fsm = ap_ST_fsm_state4022; + end + ap_ST_fsm_state4022 : begin + ap_NS_fsm = ap_ST_fsm_state4023; + end + ap_ST_fsm_state4023 : begin + ap_NS_fsm = ap_ST_fsm_state4024; + end + ap_ST_fsm_state4024 : begin + ap_NS_fsm = ap_ST_fsm_state4025; + end + ap_ST_fsm_state4025 : begin + ap_NS_fsm = ap_ST_fsm_state4026; + end + ap_ST_fsm_state4026 : begin + ap_NS_fsm = ap_ST_fsm_state4027; + end + ap_ST_fsm_state4027 : begin + ap_NS_fsm = ap_ST_fsm_state4028; + end + ap_ST_fsm_state4028 : begin + ap_NS_fsm = ap_ST_fsm_state4029; + end + ap_ST_fsm_state4029 : begin + ap_NS_fsm = ap_ST_fsm_state4030; + end + ap_ST_fsm_state4030 : begin + ap_NS_fsm = ap_ST_fsm_state4031; + end + ap_ST_fsm_state4031 : begin + ap_NS_fsm = ap_ST_fsm_state4032; + end + ap_ST_fsm_state4032 : begin + ap_NS_fsm = ap_ST_fsm_state4033; + end + ap_ST_fsm_state4033 : begin + ap_NS_fsm = ap_ST_fsm_state4034; + end + ap_ST_fsm_state4034 : begin + ap_NS_fsm = ap_ST_fsm_state3959; + end + ap_ST_fsm_state4035 : begin + ap_NS_fsm = ap_ST_fsm_state4036; + end + ap_ST_fsm_state4036 : begin + ap_NS_fsm = ap_ST_fsm_state4037; + end + ap_ST_fsm_state4037 : begin + ap_NS_fsm = ap_ST_fsm_state4038; + end + ap_ST_fsm_state4038 : begin + ap_NS_fsm = ap_ST_fsm_state4039; + end + ap_ST_fsm_state4039 : begin + ap_NS_fsm = ap_ST_fsm_state4040; + end + ap_ST_fsm_state4040 : begin + ap_NS_fsm = ap_ST_fsm_state4041; + end + ap_ST_fsm_state4041 : begin + ap_NS_fsm = ap_ST_fsm_state4042; + end + ap_ST_fsm_state4042 : begin + ap_NS_fsm = ap_ST_fsm_state4043; + end + ap_ST_fsm_state4043 : begin + ap_NS_fsm = ap_ST_fsm_state4044; + end + ap_ST_fsm_state4044 : begin + ap_NS_fsm = ap_ST_fsm_state4045; + end + ap_ST_fsm_state4045 : begin + ap_NS_fsm = ap_ST_fsm_state4046; + end + ap_ST_fsm_state4046 : begin + ap_NS_fsm = ap_ST_fsm_state4047; + end + ap_ST_fsm_state4047 : begin + ap_NS_fsm = ap_ST_fsm_state4048; + end + ap_ST_fsm_state4048 : begin + ap_NS_fsm = ap_ST_fsm_state4049; + end + ap_ST_fsm_state4049 : begin + ap_NS_fsm = ap_ST_fsm_state4050; + end + ap_ST_fsm_state4050 : begin + ap_NS_fsm = ap_ST_fsm_state4051; + end + ap_ST_fsm_state4051 : begin + ap_NS_fsm = ap_ST_fsm_state4052; + end + ap_ST_fsm_state4052 : begin + ap_NS_fsm = ap_ST_fsm_state4053; + end + ap_ST_fsm_state4053 : begin + ap_NS_fsm = ap_ST_fsm_state4054; + end + ap_ST_fsm_state4054 : begin + ap_NS_fsm = ap_ST_fsm_state4055; + end + ap_ST_fsm_state4055 : begin + ap_NS_fsm = ap_ST_fsm_state4056; + end + ap_ST_fsm_state4056 : begin + ap_NS_fsm = ap_ST_fsm_state4057; + end + ap_ST_fsm_state4057 : begin + ap_NS_fsm = ap_ST_fsm_state4058; + end + ap_ST_fsm_state4058 : begin + ap_NS_fsm = ap_ST_fsm_state4059; + end + ap_ST_fsm_state4059 : begin + ap_NS_fsm = ap_ST_fsm_state4060; + end + ap_ST_fsm_state4060 : begin + ap_NS_fsm = ap_ST_fsm_state4061; + end + ap_ST_fsm_state4061 : begin + ap_NS_fsm = ap_ST_fsm_state4062; + end + ap_ST_fsm_state4062 : begin + ap_NS_fsm = ap_ST_fsm_state4063; + end + ap_ST_fsm_state4063 : begin + ap_NS_fsm = ap_ST_fsm_state4064; + end + ap_ST_fsm_state4064 : begin + ap_NS_fsm = ap_ST_fsm_state4065; + end + ap_ST_fsm_state4065 : begin + ap_NS_fsm = ap_ST_fsm_state4066; + end + ap_ST_fsm_state4066 : begin + ap_NS_fsm = ap_ST_fsm_state4067; + end + ap_ST_fsm_state4067 : begin + ap_NS_fsm = ap_ST_fsm_state4068; + end + ap_ST_fsm_state4068 : begin + ap_NS_fsm = ap_ST_fsm_state4069; + end + ap_ST_fsm_state4069 : begin + ap_NS_fsm = ap_ST_fsm_state4070; + end + ap_ST_fsm_state4070 : begin + ap_NS_fsm = ap_ST_fsm_state4071; + end + ap_ST_fsm_state4071 : begin + ap_NS_fsm = ap_ST_fsm_state4072; + end + ap_ST_fsm_state4072 : begin + if (((icmp_ln268_25_fu_126074_p2 == 1'd1) & (ap_ST_fsm_state4072 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3958; + end else begin + ap_NS_fsm = ap_ST_fsm_state4073; + end + end + ap_ST_fsm_state4073 : begin + ap_NS_fsm = ap_ST_fsm_state4074; + end + ap_ST_fsm_state4074 : begin + ap_NS_fsm = ap_ST_fsm_state4075; + end + ap_ST_fsm_state4075 : begin + ap_NS_fsm = ap_ST_fsm_state4076; + end + ap_ST_fsm_state4076 : begin + ap_NS_fsm = ap_ST_fsm_state4077; + end + ap_ST_fsm_state4077 : begin + ap_NS_fsm = ap_ST_fsm_state4078; + end + ap_ST_fsm_state4078 : begin + ap_NS_fsm = ap_ST_fsm_state4079; + end + ap_ST_fsm_state4079 : begin + ap_NS_fsm = ap_ST_fsm_state4080; + end + ap_ST_fsm_state4080 : begin + ap_NS_fsm = ap_ST_fsm_state4081; + end + ap_ST_fsm_state4081 : begin + ap_NS_fsm = ap_ST_fsm_state4082; + end + ap_ST_fsm_state4082 : begin + ap_NS_fsm = ap_ST_fsm_state4083; + end + ap_ST_fsm_state4083 : begin + ap_NS_fsm = ap_ST_fsm_state4084; + end + ap_ST_fsm_state4084 : begin + ap_NS_fsm = ap_ST_fsm_state4085; + end + ap_ST_fsm_state4085 : begin + ap_NS_fsm = ap_ST_fsm_state4086; + end + ap_ST_fsm_state4086 : begin + ap_NS_fsm = ap_ST_fsm_state4087; + end + ap_ST_fsm_state4087 : begin + ap_NS_fsm = ap_ST_fsm_state4088; + end + ap_ST_fsm_state4088 : begin + ap_NS_fsm = ap_ST_fsm_state4089; + end + ap_ST_fsm_state4089 : begin + ap_NS_fsm = ap_ST_fsm_state4090; + end + ap_ST_fsm_state4090 : begin + ap_NS_fsm = ap_ST_fsm_state4091; + end + ap_ST_fsm_state4091 : begin + ap_NS_fsm = ap_ST_fsm_state4092; + end + ap_ST_fsm_state4092 : begin + ap_NS_fsm = ap_ST_fsm_state4093; + end + ap_ST_fsm_state4093 : begin + ap_NS_fsm = ap_ST_fsm_state4094; + end + ap_ST_fsm_state4094 : begin + ap_NS_fsm = ap_ST_fsm_state4095; + end + ap_ST_fsm_state4095 : begin + ap_NS_fsm = ap_ST_fsm_state4096; + end + ap_ST_fsm_state4096 : begin + ap_NS_fsm = ap_ST_fsm_state4097; + end + ap_ST_fsm_state4097 : begin + ap_NS_fsm = ap_ST_fsm_state4098; + end + ap_ST_fsm_state4098 : begin + ap_NS_fsm = ap_ST_fsm_state4099; + end + ap_ST_fsm_state4099 : begin + ap_NS_fsm = ap_ST_fsm_state4100; + end + ap_ST_fsm_state4100 : begin + ap_NS_fsm = ap_ST_fsm_state4101; + end + ap_ST_fsm_state4101 : begin + ap_NS_fsm = ap_ST_fsm_state4102; + end + ap_ST_fsm_state4102 : begin + ap_NS_fsm = ap_ST_fsm_state4103; + end + ap_ST_fsm_state4103 : begin + ap_NS_fsm = ap_ST_fsm_state4104; + end + ap_ST_fsm_state4104 : begin + ap_NS_fsm = ap_ST_fsm_state4105; + end + ap_ST_fsm_state4105 : begin + ap_NS_fsm = ap_ST_fsm_state4106; + end + ap_ST_fsm_state4106 : begin + ap_NS_fsm = ap_ST_fsm_state4107; + end + ap_ST_fsm_state4107 : begin + ap_NS_fsm = ap_ST_fsm_state4108; + end + ap_ST_fsm_state4108 : begin + ap_NS_fsm = ap_ST_fsm_state4035; + end + ap_ST_fsm_state4109 : begin + if (((icmp_ln264_5_fu_126256_p2 == 1'd1) & (ap_ST_fsm_state4109 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3801; + end else begin + ap_NS_fsm = ap_ST_fsm_state4110; + end + end + ap_ST_fsm_state4110 : begin + ap_NS_fsm = ap_ST_fsm_state4111; + end + ap_ST_fsm_state4111 : begin + ap_NS_fsm = ap_ST_fsm_state4112; + end + ap_ST_fsm_state4112 : begin + ap_NS_fsm = ap_ST_fsm_state4113; + end + ap_ST_fsm_state4113 : begin + ap_NS_fsm = ap_ST_fsm_state4114; + end + ap_ST_fsm_state4114 : begin + ap_NS_fsm = ap_ST_fsm_state4115; + end + ap_ST_fsm_state4115 : begin + ap_NS_fsm = ap_ST_fsm_state4116; + end + ap_ST_fsm_state4116 : begin + ap_NS_fsm = ap_ST_fsm_state4117; + end + ap_ST_fsm_state4117 : begin + ap_NS_fsm = ap_ST_fsm_state4118; + end + ap_ST_fsm_state4118 : begin + ap_NS_fsm = ap_ST_fsm_state4119; + end + ap_ST_fsm_state4119 : begin + ap_NS_fsm = ap_ST_fsm_state4120; + end + ap_ST_fsm_state4120 : begin + ap_NS_fsm = ap_ST_fsm_state4121; + end + ap_ST_fsm_state4121 : begin + ap_NS_fsm = ap_ST_fsm_state4122; + end + ap_ST_fsm_state4122 : begin + ap_NS_fsm = ap_ST_fsm_state4123; + end + ap_ST_fsm_state4123 : begin + ap_NS_fsm = ap_ST_fsm_state4124; + end + ap_ST_fsm_state4124 : begin + ap_NS_fsm = ap_ST_fsm_state4125; + end + ap_ST_fsm_state4125 : begin + ap_NS_fsm = ap_ST_fsm_state4126; + end + ap_ST_fsm_state4126 : begin + ap_NS_fsm = ap_ST_fsm_state4127; + end + ap_ST_fsm_state4127 : begin + ap_NS_fsm = ap_ST_fsm_state4128; + end + ap_ST_fsm_state4128 : begin + ap_NS_fsm = ap_ST_fsm_state4129; + end + ap_ST_fsm_state4129 : begin + ap_NS_fsm = ap_ST_fsm_state4130; + end + ap_ST_fsm_state4130 : begin + ap_NS_fsm = ap_ST_fsm_state4131; + end + ap_ST_fsm_state4131 : begin + ap_NS_fsm = ap_ST_fsm_state4132; + end + ap_ST_fsm_state4132 : begin + ap_NS_fsm = ap_ST_fsm_state4133; + end + ap_ST_fsm_state4133 : begin + ap_NS_fsm = ap_ST_fsm_state4134; + end + ap_ST_fsm_state4134 : begin + ap_NS_fsm = ap_ST_fsm_state4135; + end + ap_ST_fsm_state4135 : begin + ap_NS_fsm = ap_ST_fsm_state4136; + end + ap_ST_fsm_state4136 : begin + ap_NS_fsm = ap_ST_fsm_state4137; + end + ap_ST_fsm_state4137 : begin + ap_NS_fsm = ap_ST_fsm_state4138; + end + ap_ST_fsm_state4138 : begin + ap_NS_fsm = ap_ST_fsm_state4139; + end + ap_ST_fsm_state4139 : begin + ap_NS_fsm = ap_ST_fsm_state4140; + end + ap_ST_fsm_state4140 : begin + ap_NS_fsm = ap_ST_fsm_state4141; + end + ap_ST_fsm_state4141 : begin + ap_NS_fsm = ap_ST_fsm_state4142; + end + ap_ST_fsm_state4142 : begin + ap_NS_fsm = ap_ST_fsm_state4143; + end + ap_ST_fsm_state4143 : begin + ap_NS_fsm = ap_ST_fsm_state4144; + end + ap_ST_fsm_state4144 : begin + ap_NS_fsm = ap_ST_fsm_state4145; + end + ap_ST_fsm_state4145 : begin + ap_NS_fsm = ap_ST_fsm_state4146; + end + ap_ST_fsm_state4146 : begin + ap_NS_fsm = ap_ST_fsm_state4147; + end + ap_ST_fsm_state4147 : begin + ap_NS_fsm = ap_ST_fsm_state4148; + end + ap_ST_fsm_state4148 : begin + ap_NS_fsm = ap_ST_fsm_state4149; + end + ap_ST_fsm_state4149 : begin + ap_NS_fsm = ap_ST_fsm_state4150; + end + ap_ST_fsm_state4150 : begin + if (((icmp_ln266_5_fu_126509_p2 == 1'd1) & (icmp_ln268_5_fu_126486_p2 == 1'd1) & (ap_ST_fsm_state4150 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4265; + end else if (((icmp_ln268_5_fu_126486_p2 == 1'd1) & (ap_ST_fsm_state4150 == ap_CS_fsm) & (icmp_ln266_5_fu_126509_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state4188; + end else begin + ap_NS_fsm = ap_ST_fsm_state4151; + end + end + ap_ST_fsm_state4151 : begin + ap_NS_fsm = ap_ST_fsm_state4152; + end + ap_ST_fsm_state4152 : begin + ap_NS_fsm = ap_ST_fsm_state4153; + end + ap_ST_fsm_state4153 : begin + ap_NS_fsm = ap_ST_fsm_state4154; + end + ap_ST_fsm_state4154 : begin + ap_NS_fsm = ap_ST_fsm_state4155; + end + ap_ST_fsm_state4155 : begin + ap_NS_fsm = ap_ST_fsm_state4156; + end + ap_ST_fsm_state4156 : begin + ap_NS_fsm = ap_ST_fsm_state4157; + end + ap_ST_fsm_state4157 : begin + ap_NS_fsm = ap_ST_fsm_state4158; + end + ap_ST_fsm_state4158 : begin + ap_NS_fsm = ap_ST_fsm_state4159; + end + ap_ST_fsm_state4159 : begin + ap_NS_fsm = ap_ST_fsm_state4160; + end + ap_ST_fsm_state4160 : begin + ap_NS_fsm = ap_ST_fsm_state4161; + end + ap_ST_fsm_state4161 : begin + ap_NS_fsm = ap_ST_fsm_state4162; + end + ap_ST_fsm_state4162 : begin + ap_NS_fsm = ap_ST_fsm_state4163; + end + ap_ST_fsm_state4163 : begin + ap_NS_fsm = ap_ST_fsm_state4164; + end + ap_ST_fsm_state4164 : begin + ap_NS_fsm = ap_ST_fsm_state4165; + end + ap_ST_fsm_state4165 : begin + ap_NS_fsm = ap_ST_fsm_state4166; + end + ap_ST_fsm_state4166 : begin + ap_NS_fsm = ap_ST_fsm_state4167; + end + ap_ST_fsm_state4167 : begin + ap_NS_fsm = ap_ST_fsm_state4168; + end + ap_ST_fsm_state4168 : begin + ap_NS_fsm = ap_ST_fsm_state4169; + end + ap_ST_fsm_state4169 : begin + ap_NS_fsm = ap_ST_fsm_state4170; + end + ap_ST_fsm_state4170 : begin + ap_NS_fsm = ap_ST_fsm_state4171; + end + ap_ST_fsm_state4171 : begin + ap_NS_fsm = ap_ST_fsm_state4172; + end + ap_ST_fsm_state4172 : begin + ap_NS_fsm = ap_ST_fsm_state4173; + end + ap_ST_fsm_state4173 : begin + ap_NS_fsm = ap_ST_fsm_state4174; + end + ap_ST_fsm_state4174 : begin + ap_NS_fsm = ap_ST_fsm_state4175; + end + ap_ST_fsm_state4175 : begin + ap_NS_fsm = ap_ST_fsm_state4176; + end + ap_ST_fsm_state4176 : begin + ap_NS_fsm = ap_ST_fsm_state4177; + end + ap_ST_fsm_state4177 : begin + ap_NS_fsm = ap_ST_fsm_state4178; + end + ap_ST_fsm_state4178 : begin + ap_NS_fsm = ap_ST_fsm_state4179; + end + ap_ST_fsm_state4179 : begin + ap_NS_fsm = ap_ST_fsm_state4180; + end + ap_ST_fsm_state4180 : begin + ap_NS_fsm = ap_ST_fsm_state4181; + end + ap_ST_fsm_state4181 : begin + ap_NS_fsm = ap_ST_fsm_state4182; + end + ap_ST_fsm_state4182 : begin + ap_NS_fsm = ap_ST_fsm_state4183; + end + ap_ST_fsm_state4183 : begin + ap_NS_fsm = ap_ST_fsm_state4184; + end + ap_ST_fsm_state4184 : begin + ap_NS_fsm = ap_ST_fsm_state4185; + end + ap_ST_fsm_state4185 : begin + ap_NS_fsm = ap_ST_fsm_state4186; + end + ap_ST_fsm_state4186 : begin + ap_NS_fsm = ap_ST_fsm_state4187; + end + ap_ST_fsm_state4187 : begin + ap_NS_fsm = ap_ST_fsm_state4111; + end + ap_ST_fsm_state4188 : begin + ap_NS_fsm = ap_ST_fsm_state4189; + end + ap_ST_fsm_state4189 : begin + ap_NS_fsm = ap_ST_fsm_state4190; + end + ap_ST_fsm_state4190 : begin + ap_NS_fsm = ap_ST_fsm_state4191; + end + ap_ST_fsm_state4191 : begin + ap_NS_fsm = ap_ST_fsm_state4192; + end + ap_ST_fsm_state4192 : begin + ap_NS_fsm = ap_ST_fsm_state4193; + end + ap_ST_fsm_state4193 : begin + ap_NS_fsm = ap_ST_fsm_state4194; + end + ap_ST_fsm_state4194 : begin + ap_NS_fsm = ap_ST_fsm_state4195; + end + ap_ST_fsm_state4195 : begin + ap_NS_fsm = ap_ST_fsm_state4196; + end + ap_ST_fsm_state4196 : begin + ap_NS_fsm = ap_ST_fsm_state4197; + end + ap_ST_fsm_state4197 : begin + ap_NS_fsm = ap_ST_fsm_state4198; + end + ap_ST_fsm_state4198 : begin + ap_NS_fsm = ap_ST_fsm_state4199; + end + ap_ST_fsm_state4199 : begin + ap_NS_fsm = ap_ST_fsm_state4200; + end + ap_ST_fsm_state4200 : begin + ap_NS_fsm = ap_ST_fsm_state4201; + end + ap_ST_fsm_state4201 : begin + ap_NS_fsm = ap_ST_fsm_state4202; + end + ap_ST_fsm_state4202 : begin + ap_NS_fsm = ap_ST_fsm_state4203; + end + ap_ST_fsm_state4203 : begin + ap_NS_fsm = ap_ST_fsm_state4204; + end + ap_ST_fsm_state4204 : begin + ap_NS_fsm = ap_ST_fsm_state4205; + end + ap_ST_fsm_state4205 : begin + ap_NS_fsm = ap_ST_fsm_state4206; + end + ap_ST_fsm_state4206 : begin + ap_NS_fsm = ap_ST_fsm_state4207; + end + ap_ST_fsm_state4207 : begin + ap_NS_fsm = ap_ST_fsm_state4208; + end + ap_ST_fsm_state4208 : begin + ap_NS_fsm = ap_ST_fsm_state4209; + end + ap_ST_fsm_state4209 : begin + ap_NS_fsm = ap_ST_fsm_state4210; + end + ap_ST_fsm_state4210 : begin + ap_NS_fsm = ap_ST_fsm_state4211; + end + ap_ST_fsm_state4211 : begin + ap_NS_fsm = ap_ST_fsm_state4212; + end + ap_ST_fsm_state4212 : begin + ap_NS_fsm = ap_ST_fsm_state4213; + end + ap_ST_fsm_state4213 : begin + ap_NS_fsm = ap_ST_fsm_state4214; + end + ap_ST_fsm_state4214 : begin + ap_NS_fsm = ap_ST_fsm_state4215; + end + ap_ST_fsm_state4215 : begin + ap_NS_fsm = ap_ST_fsm_state4216; + end + ap_ST_fsm_state4216 : begin + ap_NS_fsm = ap_ST_fsm_state4217; + end + ap_ST_fsm_state4217 : begin + ap_NS_fsm = ap_ST_fsm_state4218; + end + ap_ST_fsm_state4218 : begin + ap_NS_fsm = ap_ST_fsm_state4219; + end + ap_ST_fsm_state4219 : begin + ap_NS_fsm = ap_ST_fsm_state4220; + end + ap_ST_fsm_state4220 : begin + ap_NS_fsm = ap_ST_fsm_state4221; + end + ap_ST_fsm_state4221 : begin + ap_NS_fsm = ap_ST_fsm_state4222; + end + ap_ST_fsm_state4222 : begin + ap_NS_fsm = ap_ST_fsm_state4223; + end + ap_ST_fsm_state4223 : begin + ap_NS_fsm = ap_ST_fsm_state4224; + end + ap_ST_fsm_state4224 : begin + ap_NS_fsm = ap_ST_fsm_state4225; + end + ap_ST_fsm_state4225 : begin + ap_NS_fsm = ap_ST_fsm_state4226; + end + ap_ST_fsm_state4226 : begin + ap_NS_fsm = ap_ST_fsm_state4227; + end + ap_ST_fsm_state4227 : begin + if (((icmp_ln268_17_fu_126901_p2 == 1'd1) & (ap_ST_fsm_state4227 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4110; + end else begin + ap_NS_fsm = ap_ST_fsm_state4228; + end + end + ap_ST_fsm_state4228 : begin + ap_NS_fsm = ap_ST_fsm_state4229; + end + ap_ST_fsm_state4229 : begin + ap_NS_fsm = ap_ST_fsm_state4230; + end + ap_ST_fsm_state4230 : begin + ap_NS_fsm = ap_ST_fsm_state4231; + end + ap_ST_fsm_state4231 : begin + ap_NS_fsm = ap_ST_fsm_state4232; + end + ap_ST_fsm_state4232 : begin + ap_NS_fsm = ap_ST_fsm_state4233; + end + ap_ST_fsm_state4233 : begin + ap_NS_fsm = ap_ST_fsm_state4234; + end + ap_ST_fsm_state4234 : begin + ap_NS_fsm = ap_ST_fsm_state4235; + end + ap_ST_fsm_state4235 : begin + ap_NS_fsm = ap_ST_fsm_state4236; + end + ap_ST_fsm_state4236 : begin + ap_NS_fsm = ap_ST_fsm_state4237; + end + ap_ST_fsm_state4237 : begin + ap_NS_fsm = ap_ST_fsm_state4238; + end + ap_ST_fsm_state4238 : begin + ap_NS_fsm = ap_ST_fsm_state4239; + end + ap_ST_fsm_state4239 : begin + ap_NS_fsm = ap_ST_fsm_state4240; + end + ap_ST_fsm_state4240 : begin + ap_NS_fsm = ap_ST_fsm_state4241; + end + ap_ST_fsm_state4241 : begin + ap_NS_fsm = ap_ST_fsm_state4242; + end + ap_ST_fsm_state4242 : begin + ap_NS_fsm = ap_ST_fsm_state4243; + end + ap_ST_fsm_state4243 : begin + ap_NS_fsm = ap_ST_fsm_state4244; + end + ap_ST_fsm_state4244 : begin + ap_NS_fsm = ap_ST_fsm_state4245; + end + ap_ST_fsm_state4245 : begin + ap_NS_fsm = ap_ST_fsm_state4246; + end + ap_ST_fsm_state4246 : begin + ap_NS_fsm = ap_ST_fsm_state4247; + end + ap_ST_fsm_state4247 : begin + ap_NS_fsm = ap_ST_fsm_state4248; + end + ap_ST_fsm_state4248 : begin + ap_NS_fsm = ap_ST_fsm_state4249; + end + ap_ST_fsm_state4249 : begin + ap_NS_fsm = ap_ST_fsm_state4250; + end + ap_ST_fsm_state4250 : begin + ap_NS_fsm = ap_ST_fsm_state4251; + end + ap_ST_fsm_state4251 : begin + ap_NS_fsm = ap_ST_fsm_state4252; + end + ap_ST_fsm_state4252 : begin + ap_NS_fsm = ap_ST_fsm_state4253; + end + ap_ST_fsm_state4253 : begin + ap_NS_fsm = ap_ST_fsm_state4254; + end + ap_ST_fsm_state4254 : begin + ap_NS_fsm = ap_ST_fsm_state4255; + end + ap_ST_fsm_state4255 : begin + ap_NS_fsm = ap_ST_fsm_state4256; + end + ap_ST_fsm_state4256 : begin + ap_NS_fsm = ap_ST_fsm_state4257; + end + ap_ST_fsm_state4257 : begin + ap_NS_fsm = ap_ST_fsm_state4258; + end + ap_ST_fsm_state4258 : begin + ap_NS_fsm = ap_ST_fsm_state4259; + end + ap_ST_fsm_state4259 : begin + ap_NS_fsm = ap_ST_fsm_state4260; + end + ap_ST_fsm_state4260 : begin + ap_NS_fsm = ap_ST_fsm_state4261; + end + ap_ST_fsm_state4261 : begin + ap_NS_fsm = ap_ST_fsm_state4262; + end + ap_ST_fsm_state4262 : begin + ap_NS_fsm = ap_ST_fsm_state4263; + end + ap_ST_fsm_state4263 : begin + ap_NS_fsm = ap_ST_fsm_state4264; + end + ap_ST_fsm_state4264 : begin + ap_NS_fsm = ap_ST_fsm_state4188; + end + ap_ST_fsm_state4265 : begin + ap_NS_fsm = ap_ST_fsm_state4266; + end + ap_ST_fsm_state4266 : begin + ap_NS_fsm = ap_ST_fsm_state4267; + end + ap_ST_fsm_state4267 : begin + ap_NS_fsm = ap_ST_fsm_state4268; + end + ap_ST_fsm_state4268 : begin + ap_NS_fsm = ap_ST_fsm_state4269; + end + ap_ST_fsm_state4269 : begin + ap_NS_fsm = ap_ST_fsm_state4270; + end + ap_ST_fsm_state4270 : begin + ap_NS_fsm = ap_ST_fsm_state4271; + end + ap_ST_fsm_state4271 : begin + ap_NS_fsm = ap_ST_fsm_state4272; + end + ap_ST_fsm_state4272 : begin + ap_NS_fsm = ap_ST_fsm_state4273; + end + ap_ST_fsm_state4273 : begin + ap_NS_fsm = ap_ST_fsm_state4274; + end + ap_ST_fsm_state4274 : begin + ap_NS_fsm = ap_ST_fsm_state4275; + end + ap_ST_fsm_state4275 : begin + ap_NS_fsm = ap_ST_fsm_state4276; + end + ap_ST_fsm_state4276 : begin + ap_NS_fsm = ap_ST_fsm_state4277; + end + ap_ST_fsm_state4277 : begin + ap_NS_fsm = ap_ST_fsm_state4278; + end + ap_ST_fsm_state4278 : begin + ap_NS_fsm = ap_ST_fsm_state4279; + end + ap_ST_fsm_state4279 : begin + ap_NS_fsm = ap_ST_fsm_state4280; + end + ap_ST_fsm_state4280 : begin + ap_NS_fsm = ap_ST_fsm_state4281; + end + ap_ST_fsm_state4281 : begin + ap_NS_fsm = ap_ST_fsm_state4282; + end + ap_ST_fsm_state4282 : begin + ap_NS_fsm = ap_ST_fsm_state4283; + end + ap_ST_fsm_state4283 : begin + ap_NS_fsm = ap_ST_fsm_state4284; + end + ap_ST_fsm_state4284 : begin + ap_NS_fsm = ap_ST_fsm_state4285; + end + ap_ST_fsm_state4285 : begin + ap_NS_fsm = ap_ST_fsm_state4286; + end + ap_ST_fsm_state4286 : begin + ap_NS_fsm = ap_ST_fsm_state4287; + end + ap_ST_fsm_state4287 : begin + ap_NS_fsm = ap_ST_fsm_state4288; + end + ap_ST_fsm_state4288 : begin + ap_NS_fsm = ap_ST_fsm_state4289; + end + ap_ST_fsm_state4289 : begin + ap_NS_fsm = ap_ST_fsm_state4290; + end + ap_ST_fsm_state4290 : begin + ap_NS_fsm = ap_ST_fsm_state4291; + end + ap_ST_fsm_state4291 : begin + ap_NS_fsm = ap_ST_fsm_state4292; + end + ap_ST_fsm_state4292 : begin + ap_NS_fsm = ap_ST_fsm_state4293; + end + ap_ST_fsm_state4293 : begin + ap_NS_fsm = ap_ST_fsm_state4294; + end + ap_ST_fsm_state4294 : begin + ap_NS_fsm = ap_ST_fsm_state4295; + end + ap_ST_fsm_state4295 : begin + ap_NS_fsm = ap_ST_fsm_state4296; + end + ap_ST_fsm_state4296 : begin + ap_NS_fsm = ap_ST_fsm_state4297; + end + ap_ST_fsm_state4297 : begin + ap_NS_fsm = ap_ST_fsm_state4298; + end + ap_ST_fsm_state4298 : begin + ap_NS_fsm = ap_ST_fsm_state4299; + end + ap_ST_fsm_state4299 : begin + ap_NS_fsm = ap_ST_fsm_state4300; + end + ap_ST_fsm_state4300 : begin + ap_NS_fsm = ap_ST_fsm_state4301; + end + ap_ST_fsm_state4301 : begin + ap_NS_fsm = ap_ST_fsm_state4302; + end + ap_ST_fsm_state4302 : begin + ap_NS_fsm = ap_ST_fsm_state4303; + end + ap_ST_fsm_state4303 : begin + if (((icmp_ln266_13_fu_127316_p2 == 1'd1) & (icmp_ln268_20_fu_127293_p2 == 1'd1) & (ap_ST_fsm_state4303 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4109; + end else if (((icmp_ln268_20_fu_127293_p2 == 1'd1) & (ap_ST_fsm_state4303 == ap_CS_fsm) & (icmp_ln266_13_fu_127316_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state4341; + end else begin + ap_NS_fsm = ap_ST_fsm_state4304; + end + end + ap_ST_fsm_state4304 : begin + ap_NS_fsm = ap_ST_fsm_state4305; + end + ap_ST_fsm_state4305 : begin + ap_NS_fsm = ap_ST_fsm_state4306; + end + ap_ST_fsm_state4306 : begin + ap_NS_fsm = ap_ST_fsm_state4307; + end + ap_ST_fsm_state4307 : begin + ap_NS_fsm = ap_ST_fsm_state4308; + end + ap_ST_fsm_state4308 : begin + ap_NS_fsm = ap_ST_fsm_state4309; + end + ap_ST_fsm_state4309 : begin + ap_NS_fsm = ap_ST_fsm_state4310; + end + ap_ST_fsm_state4310 : begin + ap_NS_fsm = ap_ST_fsm_state4311; + end + ap_ST_fsm_state4311 : begin + ap_NS_fsm = ap_ST_fsm_state4312; + end + ap_ST_fsm_state4312 : begin + ap_NS_fsm = ap_ST_fsm_state4313; + end + ap_ST_fsm_state4313 : begin + ap_NS_fsm = ap_ST_fsm_state4314; + end + ap_ST_fsm_state4314 : begin + ap_NS_fsm = ap_ST_fsm_state4315; + end + ap_ST_fsm_state4315 : begin + ap_NS_fsm = ap_ST_fsm_state4316; + end + ap_ST_fsm_state4316 : begin + ap_NS_fsm = ap_ST_fsm_state4317; + end + ap_ST_fsm_state4317 : begin + ap_NS_fsm = ap_ST_fsm_state4318; + end + ap_ST_fsm_state4318 : begin + ap_NS_fsm = ap_ST_fsm_state4319; + end + ap_ST_fsm_state4319 : begin + ap_NS_fsm = ap_ST_fsm_state4320; + end + ap_ST_fsm_state4320 : begin + ap_NS_fsm = ap_ST_fsm_state4321; + end + ap_ST_fsm_state4321 : begin + ap_NS_fsm = ap_ST_fsm_state4322; + end + ap_ST_fsm_state4322 : begin + ap_NS_fsm = ap_ST_fsm_state4323; + end + ap_ST_fsm_state4323 : begin + ap_NS_fsm = ap_ST_fsm_state4324; + end + ap_ST_fsm_state4324 : begin + ap_NS_fsm = ap_ST_fsm_state4325; + end + ap_ST_fsm_state4325 : begin + ap_NS_fsm = ap_ST_fsm_state4326; + end + ap_ST_fsm_state4326 : begin + ap_NS_fsm = ap_ST_fsm_state4327; + end + ap_ST_fsm_state4327 : begin + ap_NS_fsm = ap_ST_fsm_state4328; + end + ap_ST_fsm_state4328 : begin + ap_NS_fsm = ap_ST_fsm_state4329; + end + ap_ST_fsm_state4329 : begin + ap_NS_fsm = ap_ST_fsm_state4330; + end + ap_ST_fsm_state4330 : begin + ap_NS_fsm = ap_ST_fsm_state4331; + end + ap_ST_fsm_state4331 : begin + ap_NS_fsm = ap_ST_fsm_state4332; + end + ap_ST_fsm_state4332 : begin + ap_NS_fsm = ap_ST_fsm_state4333; + end + ap_ST_fsm_state4333 : begin + ap_NS_fsm = ap_ST_fsm_state4334; + end + ap_ST_fsm_state4334 : begin + ap_NS_fsm = ap_ST_fsm_state4335; + end + ap_ST_fsm_state4335 : begin + ap_NS_fsm = ap_ST_fsm_state4336; + end + ap_ST_fsm_state4336 : begin + ap_NS_fsm = ap_ST_fsm_state4337; + end + ap_ST_fsm_state4337 : begin + ap_NS_fsm = ap_ST_fsm_state4338; + end + ap_ST_fsm_state4338 : begin + ap_NS_fsm = ap_ST_fsm_state4339; + end + ap_ST_fsm_state4339 : begin + ap_NS_fsm = ap_ST_fsm_state4340; + end + ap_ST_fsm_state4340 : begin + ap_NS_fsm = ap_ST_fsm_state4266; + end + ap_ST_fsm_state4341 : begin + ap_NS_fsm = ap_ST_fsm_state4342; + end + ap_ST_fsm_state4342 : begin + ap_NS_fsm = ap_ST_fsm_state4343; + end + ap_ST_fsm_state4343 : begin + ap_NS_fsm = ap_ST_fsm_state4344; + end + ap_ST_fsm_state4344 : begin + ap_NS_fsm = ap_ST_fsm_state4345; + end + ap_ST_fsm_state4345 : begin + ap_NS_fsm = ap_ST_fsm_state4346; + end + ap_ST_fsm_state4346 : begin + ap_NS_fsm = ap_ST_fsm_state4347; + end + ap_ST_fsm_state4347 : begin + ap_NS_fsm = ap_ST_fsm_state4348; + end + ap_ST_fsm_state4348 : begin + ap_NS_fsm = ap_ST_fsm_state4349; + end + ap_ST_fsm_state4349 : begin + ap_NS_fsm = ap_ST_fsm_state4350; + end + ap_ST_fsm_state4350 : begin + ap_NS_fsm = ap_ST_fsm_state4351; + end + ap_ST_fsm_state4351 : begin + ap_NS_fsm = ap_ST_fsm_state4352; + end + ap_ST_fsm_state4352 : begin + ap_NS_fsm = ap_ST_fsm_state4353; + end + ap_ST_fsm_state4353 : begin + ap_NS_fsm = ap_ST_fsm_state4354; + end + ap_ST_fsm_state4354 : begin + ap_NS_fsm = ap_ST_fsm_state4355; + end + ap_ST_fsm_state4355 : begin + ap_NS_fsm = ap_ST_fsm_state4356; + end + ap_ST_fsm_state4356 : begin + ap_NS_fsm = ap_ST_fsm_state4357; + end + ap_ST_fsm_state4357 : begin + ap_NS_fsm = ap_ST_fsm_state4358; + end + ap_ST_fsm_state4358 : begin + ap_NS_fsm = ap_ST_fsm_state4359; + end + ap_ST_fsm_state4359 : begin + ap_NS_fsm = ap_ST_fsm_state4360; + end + ap_ST_fsm_state4360 : begin + ap_NS_fsm = ap_ST_fsm_state4361; + end + ap_ST_fsm_state4361 : begin + ap_NS_fsm = ap_ST_fsm_state4362; + end + ap_ST_fsm_state4362 : begin + ap_NS_fsm = ap_ST_fsm_state4363; + end + ap_ST_fsm_state4363 : begin + ap_NS_fsm = ap_ST_fsm_state4364; + end + ap_ST_fsm_state4364 : begin + ap_NS_fsm = ap_ST_fsm_state4365; + end + ap_ST_fsm_state4365 : begin + ap_NS_fsm = ap_ST_fsm_state4366; + end + ap_ST_fsm_state4366 : begin + ap_NS_fsm = ap_ST_fsm_state4367; + end + ap_ST_fsm_state4367 : begin + ap_NS_fsm = ap_ST_fsm_state4368; + end + ap_ST_fsm_state4368 : begin + ap_NS_fsm = ap_ST_fsm_state4369; + end + ap_ST_fsm_state4369 : begin + ap_NS_fsm = ap_ST_fsm_state4370; + end + ap_ST_fsm_state4370 : begin + ap_NS_fsm = ap_ST_fsm_state4371; + end + ap_ST_fsm_state4371 : begin + ap_NS_fsm = ap_ST_fsm_state4372; + end + ap_ST_fsm_state4372 : begin + ap_NS_fsm = ap_ST_fsm_state4373; + end + ap_ST_fsm_state4373 : begin + ap_NS_fsm = ap_ST_fsm_state4374; + end + ap_ST_fsm_state4374 : begin + ap_NS_fsm = ap_ST_fsm_state4375; + end + ap_ST_fsm_state4375 : begin + ap_NS_fsm = ap_ST_fsm_state4376; + end + ap_ST_fsm_state4376 : begin + ap_NS_fsm = ap_ST_fsm_state4377; + end + ap_ST_fsm_state4377 : begin + ap_NS_fsm = ap_ST_fsm_state4378; + end + ap_ST_fsm_state4378 : begin + if (((icmp_ln268_29_fu_127697_p2 == 1'd1) & (ap_ST_fsm_state4378 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4265; + end else begin + ap_NS_fsm = ap_ST_fsm_state4379; + end + end + ap_ST_fsm_state4379 : begin + ap_NS_fsm = ap_ST_fsm_state4380; + end + ap_ST_fsm_state4380 : begin + ap_NS_fsm = ap_ST_fsm_state4381; + end + ap_ST_fsm_state4381 : begin + ap_NS_fsm = ap_ST_fsm_state4382; + end + ap_ST_fsm_state4382 : begin + ap_NS_fsm = ap_ST_fsm_state4383; + end + ap_ST_fsm_state4383 : begin + ap_NS_fsm = ap_ST_fsm_state4384; + end + ap_ST_fsm_state4384 : begin + ap_NS_fsm = ap_ST_fsm_state4385; + end + ap_ST_fsm_state4385 : begin + ap_NS_fsm = ap_ST_fsm_state4386; + end + ap_ST_fsm_state4386 : begin + ap_NS_fsm = ap_ST_fsm_state4387; + end + ap_ST_fsm_state4387 : begin + ap_NS_fsm = ap_ST_fsm_state4388; + end + ap_ST_fsm_state4388 : begin + ap_NS_fsm = ap_ST_fsm_state4389; + end + ap_ST_fsm_state4389 : begin + ap_NS_fsm = ap_ST_fsm_state4390; + end + ap_ST_fsm_state4390 : begin + ap_NS_fsm = ap_ST_fsm_state4391; + end + ap_ST_fsm_state4391 : begin + ap_NS_fsm = ap_ST_fsm_state4392; + end + ap_ST_fsm_state4392 : begin + ap_NS_fsm = ap_ST_fsm_state4393; + end + ap_ST_fsm_state4393 : begin + ap_NS_fsm = ap_ST_fsm_state4394; + end + ap_ST_fsm_state4394 : begin + ap_NS_fsm = ap_ST_fsm_state4395; + end + ap_ST_fsm_state4395 : begin + ap_NS_fsm = ap_ST_fsm_state4396; + end + ap_ST_fsm_state4396 : begin + ap_NS_fsm = ap_ST_fsm_state4397; + end + ap_ST_fsm_state4397 : begin + ap_NS_fsm = ap_ST_fsm_state4398; + end + ap_ST_fsm_state4398 : begin + ap_NS_fsm = ap_ST_fsm_state4399; + end + ap_ST_fsm_state4399 : begin + ap_NS_fsm = ap_ST_fsm_state4400; + end + ap_ST_fsm_state4400 : begin + ap_NS_fsm = ap_ST_fsm_state4401; + end + ap_ST_fsm_state4401 : begin + ap_NS_fsm = ap_ST_fsm_state4402; + end + ap_ST_fsm_state4402 : begin + ap_NS_fsm = ap_ST_fsm_state4403; + end + ap_ST_fsm_state4403 : begin + ap_NS_fsm = ap_ST_fsm_state4404; + end + ap_ST_fsm_state4404 : begin + ap_NS_fsm = ap_ST_fsm_state4405; + end + ap_ST_fsm_state4405 : begin + ap_NS_fsm = ap_ST_fsm_state4406; + end + ap_ST_fsm_state4406 : begin + ap_NS_fsm = ap_ST_fsm_state4407; + end + ap_ST_fsm_state4407 : begin + ap_NS_fsm = ap_ST_fsm_state4408; + end + ap_ST_fsm_state4408 : begin + ap_NS_fsm = ap_ST_fsm_state4409; + end + ap_ST_fsm_state4409 : begin + ap_NS_fsm = ap_ST_fsm_state4410; + end + ap_ST_fsm_state4410 : begin + ap_NS_fsm = ap_ST_fsm_state4411; + end + ap_ST_fsm_state4411 : begin + ap_NS_fsm = ap_ST_fsm_state4412; + end + ap_ST_fsm_state4412 : begin + ap_NS_fsm = ap_ST_fsm_state4413; + end + ap_ST_fsm_state4413 : begin + ap_NS_fsm = ap_ST_fsm_state4414; + end + ap_ST_fsm_state4414 : begin + ap_NS_fsm = ap_ST_fsm_state4341; + end + ap_ST_fsm_state4415 : begin + if (((icmp_ln261_3_fu_127882_p2 == 1'd1) & (ap_ST_fsm_state4415 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3800; + end else begin + ap_NS_fsm = ap_ST_fsm_state4416; + end + end + ap_ST_fsm_state4416 : begin + if (((icmp_ln264_4_fu_127994_p2 == 1'd1) & (ap_ST_fsm_state4416 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4722; + end else begin + ap_NS_fsm = ap_ST_fsm_state4417; + end + end + ap_ST_fsm_state4417 : begin + ap_NS_fsm = ap_ST_fsm_state4418; + end + ap_ST_fsm_state4418 : begin + ap_NS_fsm = ap_ST_fsm_state4419; + end + ap_ST_fsm_state4419 : begin + ap_NS_fsm = ap_ST_fsm_state4420; + end + ap_ST_fsm_state4420 : begin + ap_NS_fsm = ap_ST_fsm_state4421; + end + ap_ST_fsm_state4421 : begin + ap_NS_fsm = ap_ST_fsm_state4422; + end + ap_ST_fsm_state4422 : begin + ap_NS_fsm = ap_ST_fsm_state4423; + end + ap_ST_fsm_state4423 : begin + ap_NS_fsm = ap_ST_fsm_state4424; + end + ap_ST_fsm_state4424 : begin + ap_NS_fsm = ap_ST_fsm_state4425; + end + ap_ST_fsm_state4425 : begin + ap_NS_fsm = ap_ST_fsm_state4426; + end + ap_ST_fsm_state4426 : begin + ap_NS_fsm = ap_ST_fsm_state4427; + end + ap_ST_fsm_state4427 : begin + ap_NS_fsm = ap_ST_fsm_state4428; + end + ap_ST_fsm_state4428 : begin + ap_NS_fsm = ap_ST_fsm_state4429; + end + ap_ST_fsm_state4429 : begin + ap_NS_fsm = ap_ST_fsm_state4430; + end + ap_ST_fsm_state4430 : begin + ap_NS_fsm = ap_ST_fsm_state4431; + end + ap_ST_fsm_state4431 : begin + ap_NS_fsm = ap_ST_fsm_state4432; + end + ap_ST_fsm_state4432 : begin + ap_NS_fsm = ap_ST_fsm_state4433; + end + ap_ST_fsm_state4433 : begin + ap_NS_fsm = ap_ST_fsm_state4434; + end + ap_ST_fsm_state4434 : begin + ap_NS_fsm = ap_ST_fsm_state4435; + end + ap_ST_fsm_state4435 : begin + ap_NS_fsm = ap_ST_fsm_state4436; + end + ap_ST_fsm_state4436 : begin + ap_NS_fsm = ap_ST_fsm_state4437; + end + ap_ST_fsm_state4437 : begin + ap_NS_fsm = ap_ST_fsm_state4438; + end + ap_ST_fsm_state4438 : begin + ap_NS_fsm = ap_ST_fsm_state4439; + end + ap_ST_fsm_state4439 : begin + ap_NS_fsm = ap_ST_fsm_state4440; + end + ap_ST_fsm_state4440 : begin + ap_NS_fsm = ap_ST_fsm_state4441; + end + ap_ST_fsm_state4441 : begin + ap_NS_fsm = ap_ST_fsm_state4442; + end + ap_ST_fsm_state4442 : begin + ap_NS_fsm = ap_ST_fsm_state4443; + end + ap_ST_fsm_state4443 : begin + ap_NS_fsm = ap_ST_fsm_state4444; + end + ap_ST_fsm_state4444 : begin + ap_NS_fsm = ap_ST_fsm_state4445; + end + ap_ST_fsm_state4445 : begin + ap_NS_fsm = ap_ST_fsm_state4446; + end + ap_ST_fsm_state4446 : begin + ap_NS_fsm = ap_ST_fsm_state4447; + end + ap_ST_fsm_state4447 : begin + ap_NS_fsm = ap_ST_fsm_state4448; + end + ap_ST_fsm_state4448 : begin + ap_NS_fsm = ap_ST_fsm_state4449; + end + ap_ST_fsm_state4449 : begin + ap_NS_fsm = ap_ST_fsm_state4450; + end + ap_ST_fsm_state4450 : begin + ap_NS_fsm = ap_ST_fsm_state4451; + end + ap_ST_fsm_state4451 : begin + ap_NS_fsm = ap_ST_fsm_state4452; + end + ap_ST_fsm_state4452 : begin + ap_NS_fsm = ap_ST_fsm_state4453; + end + ap_ST_fsm_state4453 : begin + ap_NS_fsm = ap_ST_fsm_state4454; + end + ap_ST_fsm_state4454 : begin + ap_NS_fsm = ap_ST_fsm_state4455; + end + ap_ST_fsm_state4455 : begin + ap_NS_fsm = ap_ST_fsm_state4456; + end + ap_ST_fsm_state4456 : begin + ap_NS_fsm = ap_ST_fsm_state4457; + end + ap_ST_fsm_state4457 : begin + if (((icmp_ln266_4_fu_128351_p2 == 1'd1) & (icmp_ln268_4_fu_128328_p2 == 1'd1) & (ap_ST_fsm_state4457 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4572; + end else if (((icmp_ln268_4_fu_128328_p2 == 1'd1) & (ap_ST_fsm_state4457 == ap_CS_fsm) & (icmp_ln266_4_fu_128351_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state4495; + end else begin + ap_NS_fsm = ap_ST_fsm_state4458; + end + end + ap_ST_fsm_state4458 : begin + ap_NS_fsm = ap_ST_fsm_state4459; + end + ap_ST_fsm_state4459 : begin + ap_NS_fsm = ap_ST_fsm_state4460; + end + ap_ST_fsm_state4460 : begin + ap_NS_fsm = ap_ST_fsm_state4461; + end + ap_ST_fsm_state4461 : begin + ap_NS_fsm = ap_ST_fsm_state4462; + end + ap_ST_fsm_state4462 : begin + ap_NS_fsm = ap_ST_fsm_state4463; + end + ap_ST_fsm_state4463 : begin + ap_NS_fsm = ap_ST_fsm_state4464; + end + ap_ST_fsm_state4464 : begin + ap_NS_fsm = ap_ST_fsm_state4465; + end + ap_ST_fsm_state4465 : begin + ap_NS_fsm = ap_ST_fsm_state4466; + end + ap_ST_fsm_state4466 : begin + ap_NS_fsm = ap_ST_fsm_state4467; + end + ap_ST_fsm_state4467 : begin + ap_NS_fsm = ap_ST_fsm_state4468; + end + ap_ST_fsm_state4468 : begin + ap_NS_fsm = ap_ST_fsm_state4469; + end + ap_ST_fsm_state4469 : begin + ap_NS_fsm = ap_ST_fsm_state4470; + end + ap_ST_fsm_state4470 : begin + ap_NS_fsm = ap_ST_fsm_state4471; + end + ap_ST_fsm_state4471 : begin + ap_NS_fsm = ap_ST_fsm_state4472; + end + ap_ST_fsm_state4472 : begin + ap_NS_fsm = ap_ST_fsm_state4473; + end + ap_ST_fsm_state4473 : begin + ap_NS_fsm = ap_ST_fsm_state4474; + end + ap_ST_fsm_state4474 : begin + ap_NS_fsm = ap_ST_fsm_state4475; + end + ap_ST_fsm_state4475 : begin + ap_NS_fsm = ap_ST_fsm_state4476; + end + ap_ST_fsm_state4476 : begin + ap_NS_fsm = ap_ST_fsm_state4477; + end + ap_ST_fsm_state4477 : begin + ap_NS_fsm = ap_ST_fsm_state4478; + end + ap_ST_fsm_state4478 : begin + ap_NS_fsm = ap_ST_fsm_state4479; + end + ap_ST_fsm_state4479 : begin + ap_NS_fsm = ap_ST_fsm_state4480; + end + ap_ST_fsm_state4480 : begin + ap_NS_fsm = ap_ST_fsm_state4481; + end + ap_ST_fsm_state4481 : begin + ap_NS_fsm = ap_ST_fsm_state4482; + end + ap_ST_fsm_state4482 : begin + ap_NS_fsm = ap_ST_fsm_state4483; + end + ap_ST_fsm_state4483 : begin + ap_NS_fsm = ap_ST_fsm_state4484; + end + ap_ST_fsm_state4484 : begin + ap_NS_fsm = ap_ST_fsm_state4485; + end + ap_ST_fsm_state4485 : begin + ap_NS_fsm = ap_ST_fsm_state4486; + end + ap_ST_fsm_state4486 : begin + ap_NS_fsm = ap_ST_fsm_state4487; + end + ap_ST_fsm_state4487 : begin + ap_NS_fsm = ap_ST_fsm_state4488; + end + ap_ST_fsm_state4488 : begin + ap_NS_fsm = ap_ST_fsm_state4489; + end + ap_ST_fsm_state4489 : begin + ap_NS_fsm = ap_ST_fsm_state4490; + end + ap_ST_fsm_state4490 : begin + ap_NS_fsm = ap_ST_fsm_state4491; + end + ap_ST_fsm_state4491 : begin + ap_NS_fsm = ap_ST_fsm_state4492; + end + ap_ST_fsm_state4492 : begin + ap_NS_fsm = ap_ST_fsm_state4493; + end + ap_ST_fsm_state4493 : begin + ap_NS_fsm = ap_ST_fsm_state4494; + end + ap_ST_fsm_state4494 : begin + ap_NS_fsm = ap_ST_fsm_state4418; + end + ap_ST_fsm_state4495 : begin + ap_NS_fsm = ap_ST_fsm_state4496; + end + ap_ST_fsm_state4496 : begin + ap_NS_fsm = ap_ST_fsm_state4497; + end + ap_ST_fsm_state4497 : begin + ap_NS_fsm = ap_ST_fsm_state4498; + end + ap_ST_fsm_state4498 : begin + ap_NS_fsm = ap_ST_fsm_state4499; + end + ap_ST_fsm_state4499 : begin + ap_NS_fsm = ap_ST_fsm_state4500; + end + ap_ST_fsm_state4500 : begin + ap_NS_fsm = ap_ST_fsm_state4501; + end + ap_ST_fsm_state4501 : begin + ap_NS_fsm = ap_ST_fsm_state4502; + end + ap_ST_fsm_state4502 : begin + ap_NS_fsm = ap_ST_fsm_state4503; + end + ap_ST_fsm_state4503 : begin + ap_NS_fsm = ap_ST_fsm_state4504; + end + ap_ST_fsm_state4504 : begin + ap_NS_fsm = ap_ST_fsm_state4505; + end + ap_ST_fsm_state4505 : begin + ap_NS_fsm = ap_ST_fsm_state4506; + end + ap_ST_fsm_state4506 : begin + ap_NS_fsm = ap_ST_fsm_state4507; + end + ap_ST_fsm_state4507 : begin + ap_NS_fsm = ap_ST_fsm_state4508; + end + ap_ST_fsm_state4508 : begin + ap_NS_fsm = ap_ST_fsm_state4509; + end + ap_ST_fsm_state4509 : begin + ap_NS_fsm = ap_ST_fsm_state4510; + end + ap_ST_fsm_state4510 : begin + ap_NS_fsm = ap_ST_fsm_state4511; + end + ap_ST_fsm_state4511 : begin + ap_NS_fsm = ap_ST_fsm_state4512; + end + ap_ST_fsm_state4512 : begin + ap_NS_fsm = ap_ST_fsm_state4513; + end + ap_ST_fsm_state4513 : begin + ap_NS_fsm = ap_ST_fsm_state4514; + end + ap_ST_fsm_state4514 : begin + ap_NS_fsm = ap_ST_fsm_state4515; + end + ap_ST_fsm_state4515 : begin + ap_NS_fsm = ap_ST_fsm_state4516; + end + ap_ST_fsm_state4516 : begin + ap_NS_fsm = ap_ST_fsm_state4517; + end + ap_ST_fsm_state4517 : begin + ap_NS_fsm = ap_ST_fsm_state4518; + end + ap_ST_fsm_state4518 : begin + ap_NS_fsm = ap_ST_fsm_state4519; + end + ap_ST_fsm_state4519 : begin + ap_NS_fsm = ap_ST_fsm_state4520; + end + ap_ST_fsm_state4520 : begin + ap_NS_fsm = ap_ST_fsm_state4521; + end + ap_ST_fsm_state4521 : begin + ap_NS_fsm = ap_ST_fsm_state4522; + end + ap_ST_fsm_state4522 : begin + ap_NS_fsm = ap_ST_fsm_state4523; + end + ap_ST_fsm_state4523 : begin + ap_NS_fsm = ap_ST_fsm_state4524; + end + ap_ST_fsm_state4524 : begin + ap_NS_fsm = ap_ST_fsm_state4525; + end + ap_ST_fsm_state4525 : begin + ap_NS_fsm = ap_ST_fsm_state4526; + end + ap_ST_fsm_state4526 : begin + ap_NS_fsm = ap_ST_fsm_state4527; + end + ap_ST_fsm_state4527 : begin + ap_NS_fsm = ap_ST_fsm_state4528; + end + ap_ST_fsm_state4528 : begin + ap_NS_fsm = ap_ST_fsm_state4529; + end + ap_ST_fsm_state4529 : begin + ap_NS_fsm = ap_ST_fsm_state4530; + end + ap_ST_fsm_state4530 : begin + ap_NS_fsm = ap_ST_fsm_state4531; + end + ap_ST_fsm_state4531 : begin + ap_NS_fsm = ap_ST_fsm_state4532; + end + ap_ST_fsm_state4532 : begin + ap_NS_fsm = ap_ST_fsm_state4533; + end + ap_ST_fsm_state4533 : begin + ap_NS_fsm = ap_ST_fsm_state4534; + end + ap_ST_fsm_state4534 : begin + if (((icmp_ln268_16_fu_128744_p2 == 1'd1) & (ap_ST_fsm_state4534 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4417; + end else begin + ap_NS_fsm = ap_ST_fsm_state4535; + end + end + ap_ST_fsm_state4535 : begin + ap_NS_fsm = ap_ST_fsm_state4536; + end + ap_ST_fsm_state4536 : begin + ap_NS_fsm = ap_ST_fsm_state4537; + end + ap_ST_fsm_state4537 : begin + ap_NS_fsm = ap_ST_fsm_state4538; + end + ap_ST_fsm_state4538 : begin + ap_NS_fsm = ap_ST_fsm_state4539; + end + ap_ST_fsm_state4539 : begin + ap_NS_fsm = ap_ST_fsm_state4540; + end + ap_ST_fsm_state4540 : begin + ap_NS_fsm = ap_ST_fsm_state4541; + end + ap_ST_fsm_state4541 : begin + ap_NS_fsm = ap_ST_fsm_state4542; + end + ap_ST_fsm_state4542 : begin + ap_NS_fsm = ap_ST_fsm_state4543; + end + ap_ST_fsm_state4543 : begin + ap_NS_fsm = ap_ST_fsm_state4544; + end + ap_ST_fsm_state4544 : begin + ap_NS_fsm = ap_ST_fsm_state4545; + end + ap_ST_fsm_state4545 : begin + ap_NS_fsm = ap_ST_fsm_state4546; + end + ap_ST_fsm_state4546 : begin + ap_NS_fsm = ap_ST_fsm_state4547; + end + ap_ST_fsm_state4547 : begin + ap_NS_fsm = ap_ST_fsm_state4548; + end + ap_ST_fsm_state4548 : begin + ap_NS_fsm = ap_ST_fsm_state4549; + end + ap_ST_fsm_state4549 : begin + ap_NS_fsm = ap_ST_fsm_state4550; + end + ap_ST_fsm_state4550 : begin + ap_NS_fsm = ap_ST_fsm_state4551; + end + ap_ST_fsm_state4551 : begin + ap_NS_fsm = ap_ST_fsm_state4552; + end + ap_ST_fsm_state4552 : begin + ap_NS_fsm = ap_ST_fsm_state4553; + end + ap_ST_fsm_state4553 : begin + ap_NS_fsm = ap_ST_fsm_state4554; + end + ap_ST_fsm_state4554 : begin + ap_NS_fsm = ap_ST_fsm_state4555; + end + ap_ST_fsm_state4555 : begin + ap_NS_fsm = ap_ST_fsm_state4556; + end + ap_ST_fsm_state4556 : begin + ap_NS_fsm = ap_ST_fsm_state4557; + end + ap_ST_fsm_state4557 : begin + ap_NS_fsm = ap_ST_fsm_state4558; + end + ap_ST_fsm_state4558 : begin + ap_NS_fsm = ap_ST_fsm_state4559; + end + ap_ST_fsm_state4559 : begin + ap_NS_fsm = ap_ST_fsm_state4560; + end + ap_ST_fsm_state4560 : begin + ap_NS_fsm = ap_ST_fsm_state4561; + end + ap_ST_fsm_state4561 : begin + ap_NS_fsm = ap_ST_fsm_state4562; + end + ap_ST_fsm_state4562 : begin + ap_NS_fsm = ap_ST_fsm_state4563; + end + ap_ST_fsm_state4563 : begin + ap_NS_fsm = ap_ST_fsm_state4564; + end + ap_ST_fsm_state4564 : begin + ap_NS_fsm = ap_ST_fsm_state4565; + end + ap_ST_fsm_state4565 : begin + ap_NS_fsm = ap_ST_fsm_state4566; + end + ap_ST_fsm_state4566 : begin + ap_NS_fsm = ap_ST_fsm_state4567; + end + ap_ST_fsm_state4567 : begin + ap_NS_fsm = ap_ST_fsm_state4568; + end + ap_ST_fsm_state4568 : begin + ap_NS_fsm = ap_ST_fsm_state4569; + end + ap_ST_fsm_state4569 : begin + ap_NS_fsm = ap_ST_fsm_state4570; + end + ap_ST_fsm_state4570 : begin + ap_NS_fsm = ap_ST_fsm_state4571; + end + ap_ST_fsm_state4571 : begin + ap_NS_fsm = ap_ST_fsm_state4495; + end + ap_ST_fsm_state4572 : begin + ap_NS_fsm = ap_ST_fsm_state4573; + end + ap_ST_fsm_state4573 : begin + ap_NS_fsm = ap_ST_fsm_state4574; + end + ap_ST_fsm_state4574 : begin + ap_NS_fsm = ap_ST_fsm_state4575; + end + ap_ST_fsm_state4575 : begin + ap_NS_fsm = ap_ST_fsm_state4576; + end + ap_ST_fsm_state4576 : begin + ap_NS_fsm = ap_ST_fsm_state4577; + end + ap_ST_fsm_state4577 : begin + ap_NS_fsm = ap_ST_fsm_state4578; + end + ap_ST_fsm_state4578 : begin + ap_NS_fsm = ap_ST_fsm_state4579; + end + ap_ST_fsm_state4579 : begin + ap_NS_fsm = ap_ST_fsm_state4580; + end + ap_ST_fsm_state4580 : begin + ap_NS_fsm = ap_ST_fsm_state4581; + end + ap_ST_fsm_state4581 : begin + ap_NS_fsm = ap_ST_fsm_state4582; + end + ap_ST_fsm_state4582 : begin + ap_NS_fsm = ap_ST_fsm_state4583; + end + ap_ST_fsm_state4583 : begin + ap_NS_fsm = ap_ST_fsm_state4584; + end + ap_ST_fsm_state4584 : begin + ap_NS_fsm = ap_ST_fsm_state4585; + end + ap_ST_fsm_state4585 : begin + ap_NS_fsm = ap_ST_fsm_state4586; + end + ap_ST_fsm_state4586 : begin + ap_NS_fsm = ap_ST_fsm_state4587; + end + ap_ST_fsm_state4587 : begin + ap_NS_fsm = ap_ST_fsm_state4588; + end + ap_ST_fsm_state4588 : begin + ap_NS_fsm = ap_ST_fsm_state4589; + end + ap_ST_fsm_state4589 : begin + ap_NS_fsm = ap_ST_fsm_state4590; + end + ap_ST_fsm_state4590 : begin + ap_NS_fsm = ap_ST_fsm_state4591; + end + ap_ST_fsm_state4591 : begin + ap_NS_fsm = ap_ST_fsm_state4592; + end + ap_ST_fsm_state4592 : begin + ap_NS_fsm = ap_ST_fsm_state4593; + end + ap_ST_fsm_state4593 : begin + ap_NS_fsm = ap_ST_fsm_state4594; + end + ap_ST_fsm_state4594 : begin + ap_NS_fsm = ap_ST_fsm_state4595; + end + ap_ST_fsm_state4595 : begin + ap_NS_fsm = ap_ST_fsm_state4596; + end + ap_ST_fsm_state4596 : begin + ap_NS_fsm = ap_ST_fsm_state4597; + end + ap_ST_fsm_state4597 : begin + ap_NS_fsm = ap_ST_fsm_state4598; + end + ap_ST_fsm_state4598 : begin + ap_NS_fsm = ap_ST_fsm_state4599; + end + ap_ST_fsm_state4599 : begin + ap_NS_fsm = ap_ST_fsm_state4600; + end + ap_ST_fsm_state4600 : begin + ap_NS_fsm = ap_ST_fsm_state4601; + end + ap_ST_fsm_state4601 : begin + ap_NS_fsm = ap_ST_fsm_state4602; + end + ap_ST_fsm_state4602 : begin + ap_NS_fsm = ap_ST_fsm_state4603; + end + ap_ST_fsm_state4603 : begin + ap_NS_fsm = ap_ST_fsm_state4604; + end + ap_ST_fsm_state4604 : begin + ap_NS_fsm = ap_ST_fsm_state4605; + end + ap_ST_fsm_state4605 : begin + ap_NS_fsm = ap_ST_fsm_state4606; + end + ap_ST_fsm_state4606 : begin + ap_NS_fsm = ap_ST_fsm_state4607; + end + ap_ST_fsm_state4607 : begin + ap_NS_fsm = ap_ST_fsm_state4608; + end + ap_ST_fsm_state4608 : begin + ap_NS_fsm = ap_ST_fsm_state4609; + end + ap_ST_fsm_state4609 : begin + ap_NS_fsm = ap_ST_fsm_state4610; + end + ap_ST_fsm_state4610 : begin + if (((icmp_ln266_12_fu_129160_p2 == 1'd1) & (icmp_ln268_19_fu_129137_p2 == 1'd1) & (ap_ST_fsm_state4610 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4416; + end else if (((icmp_ln268_19_fu_129137_p2 == 1'd1) & (ap_ST_fsm_state4610 == ap_CS_fsm) & (icmp_ln266_12_fu_129160_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state4648; + end else begin + ap_NS_fsm = ap_ST_fsm_state4611; + end + end + ap_ST_fsm_state4611 : begin + ap_NS_fsm = ap_ST_fsm_state4612; + end + ap_ST_fsm_state4612 : begin + ap_NS_fsm = ap_ST_fsm_state4613; + end + ap_ST_fsm_state4613 : begin + ap_NS_fsm = ap_ST_fsm_state4614; + end + ap_ST_fsm_state4614 : begin + ap_NS_fsm = ap_ST_fsm_state4615; + end + ap_ST_fsm_state4615 : begin + ap_NS_fsm = ap_ST_fsm_state4616; + end + ap_ST_fsm_state4616 : begin + ap_NS_fsm = ap_ST_fsm_state4617; + end + ap_ST_fsm_state4617 : begin + ap_NS_fsm = ap_ST_fsm_state4618; + end + ap_ST_fsm_state4618 : begin + ap_NS_fsm = ap_ST_fsm_state4619; + end + ap_ST_fsm_state4619 : begin + ap_NS_fsm = ap_ST_fsm_state4620; + end + ap_ST_fsm_state4620 : begin + ap_NS_fsm = ap_ST_fsm_state4621; + end + ap_ST_fsm_state4621 : begin + ap_NS_fsm = ap_ST_fsm_state4622; + end + ap_ST_fsm_state4622 : begin + ap_NS_fsm = ap_ST_fsm_state4623; + end + ap_ST_fsm_state4623 : begin + ap_NS_fsm = ap_ST_fsm_state4624; + end + ap_ST_fsm_state4624 : begin + ap_NS_fsm = ap_ST_fsm_state4625; + end + ap_ST_fsm_state4625 : begin + ap_NS_fsm = ap_ST_fsm_state4626; + end + ap_ST_fsm_state4626 : begin + ap_NS_fsm = ap_ST_fsm_state4627; + end + ap_ST_fsm_state4627 : begin + ap_NS_fsm = ap_ST_fsm_state4628; + end + ap_ST_fsm_state4628 : begin + ap_NS_fsm = ap_ST_fsm_state4629; + end + ap_ST_fsm_state4629 : begin + ap_NS_fsm = ap_ST_fsm_state4630; + end + ap_ST_fsm_state4630 : begin + ap_NS_fsm = ap_ST_fsm_state4631; + end + ap_ST_fsm_state4631 : begin + ap_NS_fsm = ap_ST_fsm_state4632; + end + ap_ST_fsm_state4632 : begin + ap_NS_fsm = ap_ST_fsm_state4633; + end + ap_ST_fsm_state4633 : begin + ap_NS_fsm = ap_ST_fsm_state4634; + end + ap_ST_fsm_state4634 : begin + ap_NS_fsm = ap_ST_fsm_state4635; + end + ap_ST_fsm_state4635 : begin + ap_NS_fsm = ap_ST_fsm_state4636; + end + ap_ST_fsm_state4636 : begin + ap_NS_fsm = ap_ST_fsm_state4637; + end + ap_ST_fsm_state4637 : begin + ap_NS_fsm = ap_ST_fsm_state4638; + end + ap_ST_fsm_state4638 : begin + ap_NS_fsm = ap_ST_fsm_state4639; + end + ap_ST_fsm_state4639 : begin + ap_NS_fsm = ap_ST_fsm_state4640; + end + ap_ST_fsm_state4640 : begin + ap_NS_fsm = ap_ST_fsm_state4641; + end + ap_ST_fsm_state4641 : begin + ap_NS_fsm = ap_ST_fsm_state4642; + end + ap_ST_fsm_state4642 : begin + ap_NS_fsm = ap_ST_fsm_state4643; + end + ap_ST_fsm_state4643 : begin + ap_NS_fsm = ap_ST_fsm_state4644; + end + ap_ST_fsm_state4644 : begin + ap_NS_fsm = ap_ST_fsm_state4645; + end + ap_ST_fsm_state4645 : begin + ap_NS_fsm = ap_ST_fsm_state4646; + end + ap_ST_fsm_state4646 : begin + ap_NS_fsm = ap_ST_fsm_state4647; + end + ap_ST_fsm_state4647 : begin + ap_NS_fsm = ap_ST_fsm_state4573; + end + ap_ST_fsm_state4648 : begin + ap_NS_fsm = ap_ST_fsm_state4649; + end + ap_ST_fsm_state4649 : begin + ap_NS_fsm = ap_ST_fsm_state4650; + end + ap_ST_fsm_state4650 : begin + ap_NS_fsm = ap_ST_fsm_state4651; + end + ap_ST_fsm_state4651 : begin + ap_NS_fsm = ap_ST_fsm_state4652; + end + ap_ST_fsm_state4652 : begin + ap_NS_fsm = ap_ST_fsm_state4653; + end + ap_ST_fsm_state4653 : begin + ap_NS_fsm = ap_ST_fsm_state4654; + end + ap_ST_fsm_state4654 : begin + ap_NS_fsm = ap_ST_fsm_state4655; + end + ap_ST_fsm_state4655 : begin + ap_NS_fsm = ap_ST_fsm_state4656; + end + ap_ST_fsm_state4656 : begin + ap_NS_fsm = ap_ST_fsm_state4657; + end + ap_ST_fsm_state4657 : begin + ap_NS_fsm = ap_ST_fsm_state4658; + end + ap_ST_fsm_state4658 : begin + ap_NS_fsm = ap_ST_fsm_state4659; + end + ap_ST_fsm_state4659 : begin + ap_NS_fsm = ap_ST_fsm_state4660; + end + ap_ST_fsm_state4660 : begin + ap_NS_fsm = ap_ST_fsm_state4661; + end + ap_ST_fsm_state4661 : begin + ap_NS_fsm = ap_ST_fsm_state4662; + end + ap_ST_fsm_state4662 : begin + ap_NS_fsm = ap_ST_fsm_state4663; + end + ap_ST_fsm_state4663 : begin + ap_NS_fsm = ap_ST_fsm_state4664; + end + ap_ST_fsm_state4664 : begin + ap_NS_fsm = ap_ST_fsm_state4665; + end + ap_ST_fsm_state4665 : begin + ap_NS_fsm = ap_ST_fsm_state4666; + end + ap_ST_fsm_state4666 : begin + ap_NS_fsm = ap_ST_fsm_state4667; + end + ap_ST_fsm_state4667 : begin + ap_NS_fsm = ap_ST_fsm_state4668; + end + ap_ST_fsm_state4668 : begin + ap_NS_fsm = ap_ST_fsm_state4669; + end + ap_ST_fsm_state4669 : begin + ap_NS_fsm = ap_ST_fsm_state4670; + end + ap_ST_fsm_state4670 : begin + ap_NS_fsm = ap_ST_fsm_state4671; + end + ap_ST_fsm_state4671 : begin + ap_NS_fsm = ap_ST_fsm_state4672; + end + ap_ST_fsm_state4672 : begin + ap_NS_fsm = ap_ST_fsm_state4673; + end + ap_ST_fsm_state4673 : begin + ap_NS_fsm = ap_ST_fsm_state4674; + end + ap_ST_fsm_state4674 : begin + ap_NS_fsm = ap_ST_fsm_state4675; + end + ap_ST_fsm_state4675 : begin + ap_NS_fsm = ap_ST_fsm_state4676; + end + ap_ST_fsm_state4676 : begin + ap_NS_fsm = ap_ST_fsm_state4677; + end + ap_ST_fsm_state4677 : begin + ap_NS_fsm = ap_ST_fsm_state4678; + end + ap_ST_fsm_state4678 : begin + ap_NS_fsm = ap_ST_fsm_state4679; + end + ap_ST_fsm_state4679 : begin + ap_NS_fsm = ap_ST_fsm_state4680; + end + ap_ST_fsm_state4680 : begin + ap_NS_fsm = ap_ST_fsm_state4681; + end + ap_ST_fsm_state4681 : begin + ap_NS_fsm = ap_ST_fsm_state4682; + end + ap_ST_fsm_state4682 : begin + ap_NS_fsm = ap_ST_fsm_state4683; + end + ap_ST_fsm_state4683 : begin + ap_NS_fsm = ap_ST_fsm_state4684; + end + ap_ST_fsm_state4684 : begin + ap_NS_fsm = ap_ST_fsm_state4685; + end + ap_ST_fsm_state4685 : begin + if (((icmp_ln268_28_fu_129542_p2 == 1'd1) & (ap_ST_fsm_state4685 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4572; + end else begin + ap_NS_fsm = ap_ST_fsm_state4686; + end + end + ap_ST_fsm_state4686 : begin + ap_NS_fsm = ap_ST_fsm_state4687; + end + ap_ST_fsm_state4687 : begin + ap_NS_fsm = ap_ST_fsm_state4688; + end + ap_ST_fsm_state4688 : begin + ap_NS_fsm = ap_ST_fsm_state4689; + end + ap_ST_fsm_state4689 : begin + ap_NS_fsm = ap_ST_fsm_state4690; + end + ap_ST_fsm_state4690 : begin + ap_NS_fsm = ap_ST_fsm_state4691; + end + ap_ST_fsm_state4691 : begin + ap_NS_fsm = ap_ST_fsm_state4692; + end + ap_ST_fsm_state4692 : begin + ap_NS_fsm = ap_ST_fsm_state4693; + end + ap_ST_fsm_state4693 : begin + ap_NS_fsm = ap_ST_fsm_state4694; + end + ap_ST_fsm_state4694 : begin + ap_NS_fsm = ap_ST_fsm_state4695; + end + ap_ST_fsm_state4695 : begin + ap_NS_fsm = ap_ST_fsm_state4696; + end + ap_ST_fsm_state4696 : begin + ap_NS_fsm = ap_ST_fsm_state4697; + end + ap_ST_fsm_state4697 : begin + ap_NS_fsm = ap_ST_fsm_state4698; + end + ap_ST_fsm_state4698 : begin + ap_NS_fsm = ap_ST_fsm_state4699; + end + ap_ST_fsm_state4699 : begin + ap_NS_fsm = ap_ST_fsm_state4700; + end + ap_ST_fsm_state4700 : begin + ap_NS_fsm = ap_ST_fsm_state4701; + end + ap_ST_fsm_state4701 : begin + ap_NS_fsm = ap_ST_fsm_state4702; + end + ap_ST_fsm_state4702 : begin + ap_NS_fsm = ap_ST_fsm_state4703; + end + ap_ST_fsm_state4703 : begin + ap_NS_fsm = ap_ST_fsm_state4704; + end + ap_ST_fsm_state4704 : begin + ap_NS_fsm = ap_ST_fsm_state4705; + end + ap_ST_fsm_state4705 : begin + ap_NS_fsm = ap_ST_fsm_state4706; + end + ap_ST_fsm_state4706 : begin + ap_NS_fsm = ap_ST_fsm_state4707; + end + ap_ST_fsm_state4707 : begin + ap_NS_fsm = ap_ST_fsm_state4708; + end + ap_ST_fsm_state4708 : begin + ap_NS_fsm = ap_ST_fsm_state4709; + end + ap_ST_fsm_state4709 : begin + ap_NS_fsm = ap_ST_fsm_state4710; + end + ap_ST_fsm_state4710 : begin + ap_NS_fsm = ap_ST_fsm_state4711; + end + ap_ST_fsm_state4711 : begin + ap_NS_fsm = ap_ST_fsm_state4712; + end + ap_ST_fsm_state4712 : begin + ap_NS_fsm = ap_ST_fsm_state4713; + end + ap_ST_fsm_state4713 : begin + ap_NS_fsm = ap_ST_fsm_state4714; + end + ap_ST_fsm_state4714 : begin + ap_NS_fsm = ap_ST_fsm_state4715; + end + ap_ST_fsm_state4715 : begin + ap_NS_fsm = ap_ST_fsm_state4716; + end + ap_ST_fsm_state4716 : begin + ap_NS_fsm = ap_ST_fsm_state4717; + end + ap_ST_fsm_state4717 : begin + ap_NS_fsm = ap_ST_fsm_state4718; + end + ap_ST_fsm_state4718 : begin + ap_NS_fsm = ap_ST_fsm_state4719; + end + ap_ST_fsm_state4719 : begin + ap_NS_fsm = ap_ST_fsm_state4720; + end + ap_ST_fsm_state4720 : begin + ap_NS_fsm = ap_ST_fsm_state4721; + end + ap_ST_fsm_state4721 : begin + ap_NS_fsm = ap_ST_fsm_state4648; + end + ap_ST_fsm_state4722 : begin + if (((icmp_ln264_7_fu_129724_p2 == 1'd1) & (ap_ST_fsm_state4722 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4415; + end else begin + ap_NS_fsm = ap_ST_fsm_state4723; + end + end + ap_ST_fsm_state4723 : begin + ap_NS_fsm = ap_ST_fsm_state4724; + end + ap_ST_fsm_state4724 : begin + ap_NS_fsm = ap_ST_fsm_state4725; + end + ap_ST_fsm_state4725 : begin + ap_NS_fsm = ap_ST_fsm_state4726; + end + ap_ST_fsm_state4726 : begin + ap_NS_fsm = ap_ST_fsm_state4727; + end + ap_ST_fsm_state4727 : begin + ap_NS_fsm = ap_ST_fsm_state4728; + end + ap_ST_fsm_state4728 : begin + ap_NS_fsm = ap_ST_fsm_state4729; + end + ap_ST_fsm_state4729 : begin + ap_NS_fsm = ap_ST_fsm_state4730; + end + ap_ST_fsm_state4730 : begin + ap_NS_fsm = ap_ST_fsm_state4731; + end + ap_ST_fsm_state4731 : begin + ap_NS_fsm = ap_ST_fsm_state4732; + end + ap_ST_fsm_state4732 : begin + ap_NS_fsm = ap_ST_fsm_state4733; + end + ap_ST_fsm_state4733 : begin + ap_NS_fsm = ap_ST_fsm_state4734; + end + ap_ST_fsm_state4734 : begin + ap_NS_fsm = ap_ST_fsm_state4735; + end + ap_ST_fsm_state4735 : begin + ap_NS_fsm = ap_ST_fsm_state4736; + end + ap_ST_fsm_state4736 : begin + ap_NS_fsm = ap_ST_fsm_state4737; + end + ap_ST_fsm_state4737 : begin + ap_NS_fsm = ap_ST_fsm_state4738; + end + ap_ST_fsm_state4738 : begin + ap_NS_fsm = ap_ST_fsm_state4739; + end + ap_ST_fsm_state4739 : begin + ap_NS_fsm = ap_ST_fsm_state4740; + end + ap_ST_fsm_state4740 : begin + ap_NS_fsm = ap_ST_fsm_state4741; + end + ap_ST_fsm_state4741 : begin + ap_NS_fsm = ap_ST_fsm_state4742; + end + ap_ST_fsm_state4742 : begin + ap_NS_fsm = ap_ST_fsm_state4743; + end + ap_ST_fsm_state4743 : begin + ap_NS_fsm = ap_ST_fsm_state4744; + end + ap_ST_fsm_state4744 : begin + ap_NS_fsm = ap_ST_fsm_state4745; + end + ap_ST_fsm_state4745 : begin + ap_NS_fsm = ap_ST_fsm_state4746; + end + ap_ST_fsm_state4746 : begin + ap_NS_fsm = ap_ST_fsm_state4747; + end + ap_ST_fsm_state4747 : begin + ap_NS_fsm = ap_ST_fsm_state4748; + end + ap_ST_fsm_state4748 : begin + ap_NS_fsm = ap_ST_fsm_state4749; + end + ap_ST_fsm_state4749 : begin + ap_NS_fsm = ap_ST_fsm_state4750; + end + ap_ST_fsm_state4750 : begin + ap_NS_fsm = ap_ST_fsm_state4751; + end + ap_ST_fsm_state4751 : begin + ap_NS_fsm = ap_ST_fsm_state4752; + end + ap_ST_fsm_state4752 : begin + ap_NS_fsm = ap_ST_fsm_state4753; + end + ap_ST_fsm_state4753 : begin + ap_NS_fsm = ap_ST_fsm_state4754; + end + ap_ST_fsm_state4754 : begin + ap_NS_fsm = ap_ST_fsm_state4755; + end + ap_ST_fsm_state4755 : begin + ap_NS_fsm = ap_ST_fsm_state4756; + end + ap_ST_fsm_state4756 : begin + ap_NS_fsm = ap_ST_fsm_state4757; + end + ap_ST_fsm_state4757 : begin + ap_NS_fsm = ap_ST_fsm_state4758; + end + ap_ST_fsm_state4758 : begin + ap_NS_fsm = ap_ST_fsm_state4759; + end + ap_ST_fsm_state4759 : begin + ap_NS_fsm = ap_ST_fsm_state4760; + end + ap_ST_fsm_state4760 : begin + ap_NS_fsm = ap_ST_fsm_state4761; + end + ap_ST_fsm_state4761 : begin + ap_NS_fsm = ap_ST_fsm_state4762; + end + ap_ST_fsm_state4762 : begin + if (((icmp_ln266_7_fu_129977_p2 == 1'd1) & (icmp_ln268_7_fu_129954_p2 == 1'd1) & (ap_ST_fsm_state4762 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4877; + end else if (((icmp_ln268_7_fu_129954_p2 == 1'd1) & (ap_ST_fsm_state4762 == ap_CS_fsm) & (icmp_ln266_7_fu_129977_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state4800; + end else begin + ap_NS_fsm = ap_ST_fsm_state4763; + end + end + ap_ST_fsm_state4763 : begin + ap_NS_fsm = ap_ST_fsm_state4764; + end + ap_ST_fsm_state4764 : begin + ap_NS_fsm = ap_ST_fsm_state4765; + end + ap_ST_fsm_state4765 : begin + ap_NS_fsm = ap_ST_fsm_state4766; + end + ap_ST_fsm_state4766 : begin + ap_NS_fsm = ap_ST_fsm_state4767; + end + ap_ST_fsm_state4767 : begin + ap_NS_fsm = ap_ST_fsm_state4768; + end + ap_ST_fsm_state4768 : begin + ap_NS_fsm = ap_ST_fsm_state4769; + end + ap_ST_fsm_state4769 : begin + ap_NS_fsm = ap_ST_fsm_state4770; + end + ap_ST_fsm_state4770 : begin + ap_NS_fsm = ap_ST_fsm_state4771; + end + ap_ST_fsm_state4771 : begin + ap_NS_fsm = ap_ST_fsm_state4772; + end + ap_ST_fsm_state4772 : begin + ap_NS_fsm = ap_ST_fsm_state4773; + end + ap_ST_fsm_state4773 : begin + ap_NS_fsm = ap_ST_fsm_state4774; + end + ap_ST_fsm_state4774 : begin + ap_NS_fsm = ap_ST_fsm_state4775; + end + ap_ST_fsm_state4775 : begin + ap_NS_fsm = ap_ST_fsm_state4776; + end + ap_ST_fsm_state4776 : begin + ap_NS_fsm = ap_ST_fsm_state4777; + end + ap_ST_fsm_state4777 : begin + ap_NS_fsm = ap_ST_fsm_state4778; + end + ap_ST_fsm_state4778 : begin + ap_NS_fsm = ap_ST_fsm_state4779; + end + ap_ST_fsm_state4779 : begin + ap_NS_fsm = ap_ST_fsm_state4780; + end + ap_ST_fsm_state4780 : begin + ap_NS_fsm = ap_ST_fsm_state4781; + end + ap_ST_fsm_state4781 : begin + ap_NS_fsm = ap_ST_fsm_state4782; + end + ap_ST_fsm_state4782 : begin + ap_NS_fsm = ap_ST_fsm_state4783; + end + ap_ST_fsm_state4783 : begin + ap_NS_fsm = ap_ST_fsm_state4784; + end + ap_ST_fsm_state4784 : begin + ap_NS_fsm = ap_ST_fsm_state4785; + end + ap_ST_fsm_state4785 : begin + ap_NS_fsm = ap_ST_fsm_state4786; + end + ap_ST_fsm_state4786 : begin + ap_NS_fsm = ap_ST_fsm_state4787; + end + ap_ST_fsm_state4787 : begin + ap_NS_fsm = ap_ST_fsm_state4788; + end + ap_ST_fsm_state4788 : begin + ap_NS_fsm = ap_ST_fsm_state4789; + end + ap_ST_fsm_state4789 : begin + ap_NS_fsm = ap_ST_fsm_state4790; + end + ap_ST_fsm_state4790 : begin + ap_NS_fsm = ap_ST_fsm_state4791; + end + ap_ST_fsm_state4791 : begin + ap_NS_fsm = ap_ST_fsm_state4792; + end + ap_ST_fsm_state4792 : begin + ap_NS_fsm = ap_ST_fsm_state4793; + end + ap_ST_fsm_state4793 : begin + ap_NS_fsm = ap_ST_fsm_state4794; + end + ap_ST_fsm_state4794 : begin + ap_NS_fsm = ap_ST_fsm_state4795; + end + ap_ST_fsm_state4795 : begin + ap_NS_fsm = ap_ST_fsm_state4796; + end + ap_ST_fsm_state4796 : begin + ap_NS_fsm = ap_ST_fsm_state4797; + end + ap_ST_fsm_state4797 : begin + ap_NS_fsm = ap_ST_fsm_state4798; + end + ap_ST_fsm_state4798 : begin + ap_NS_fsm = ap_ST_fsm_state4799; + end + ap_ST_fsm_state4799 : begin + ap_NS_fsm = ap_ST_fsm_state4724; + end + ap_ST_fsm_state4800 : begin + ap_NS_fsm = ap_ST_fsm_state4801; + end + ap_ST_fsm_state4801 : begin + ap_NS_fsm = ap_ST_fsm_state4802; + end + ap_ST_fsm_state4802 : begin + ap_NS_fsm = ap_ST_fsm_state4803; + end + ap_ST_fsm_state4803 : begin + ap_NS_fsm = ap_ST_fsm_state4804; + end + ap_ST_fsm_state4804 : begin + ap_NS_fsm = ap_ST_fsm_state4805; + end + ap_ST_fsm_state4805 : begin + ap_NS_fsm = ap_ST_fsm_state4806; + end + ap_ST_fsm_state4806 : begin + ap_NS_fsm = ap_ST_fsm_state4807; + end + ap_ST_fsm_state4807 : begin + ap_NS_fsm = ap_ST_fsm_state4808; + end + ap_ST_fsm_state4808 : begin + ap_NS_fsm = ap_ST_fsm_state4809; + end + ap_ST_fsm_state4809 : begin + ap_NS_fsm = ap_ST_fsm_state4810; + end + ap_ST_fsm_state4810 : begin + ap_NS_fsm = ap_ST_fsm_state4811; + end + ap_ST_fsm_state4811 : begin + ap_NS_fsm = ap_ST_fsm_state4812; + end + ap_ST_fsm_state4812 : begin + ap_NS_fsm = ap_ST_fsm_state4813; + end + ap_ST_fsm_state4813 : begin + ap_NS_fsm = ap_ST_fsm_state4814; + end + ap_ST_fsm_state4814 : begin + ap_NS_fsm = ap_ST_fsm_state4815; + end + ap_ST_fsm_state4815 : begin + ap_NS_fsm = ap_ST_fsm_state4816; + end + ap_ST_fsm_state4816 : begin + ap_NS_fsm = ap_ST_fsm_state4817; + end + ap_ST_fsm_state4817 : begin + ap_NS_fsm = ap_ST_fsm_state4818; + end + ap_ST_fsm_state4818 : begin + ap_NS_fsm = ap_ST_fsm_state4819; + end + ap_ST_fsm_state4819 : begin + ap_NS_fsm = ap_ST_fsm_state4820; + end + ap_ST_fsm_state4820 : begin + ap_NS_fsm = ap_ST_fsm_state4821; + end + ap_ST_fsm_state4821 : begin + ap_NS_fsm = ap_ST_fsm_state4822; + end + ap_ST_fsm_state4822 : begin + ap_NS_fsm = ap_ST_fsm_state4823; + end + ap_ST_fsm_state4823 : begin + ap_NS_fsm = ap_ST_fsm_state4824; + end + ap_ST_fsm_state4824 : begin + ap_NS_fsm = ap_ST_fsm_state4825; + end + ap_ST_fsm_state4825 : begin + ap_NS_fsm = ap_ST_fsm_state4826; + end + ap_ST_fsm_state4826 : begin + ap_NS_fsm = ap_ST_fsm_state4827; + end + ap_ST_fsm_state4827 : begin + ap_NS_fsm = ap_ST_fsm_state4828; + end + ap_ST_fsm_state4828 : begin + ap_NS_fsm = ap_ST_fsm_state4829; + end + ap_ST_fsm_state4829 : begin + ap_NS_fsm = ap_ST_fsm_state4830; + end + ap_ST_fsm_state4830 : begin + ap_NS_fsm = ap_ST_fsm_state4831; + end + ap_ST_fsm_state4831 : begin + ap_NS_fsm = ap_ST_fsm_state4832; + end + ap_ST_fsm_state4832 : begin + ap_NS_fsm = ap_ST_fsm_state4833; + end + ap_ST_fsm_state4833 : begin + ap_NS_fsm = ap_ST_fsm_state4834; + end + ap_ST_fsm_state4834 : begin + ap_NS_fsm = ap_ST_fsm_state4835; + end + ap_ST_fsm_state4835 : begin + ap_NS_fsm = ap_ST_fsm_state4836; + end + ap_ST_fsm_state4836 : begin + ap_NS_fsm = ap_ST_fsm_state4837; + end + ap_ST_fsm_state4837 : begin + ap_NS_fsm = ap_ST_fsm_state4838; + end + ap_ST_fsm_state4838 : begin + ap_NS_fsm = ap_ST_fsm_state4839; + end + ap_ST_fsm_state4839 : begin + if (((icmp_ln268_22_fu_130369_p2 == 1'd1) & (ap_ST_fsm_state4839 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4723; + end else begin + ap_NS_fsm = ap_ST_fsm_state4840; + end + end + ap_ST_fsm_state4840 : begin + ap_NS_fsm = ap_ST_fsm_state4841; + end + ap_ST_fsm_state4841 : begin + ap_NS_fsm = ap_ST_fsm_state4842; + end + ap_ST_fsm_state4842 : begin + ap_NS_fsm = ap_ST_fsm_state4843; + end + ap_ST_fsm_state4843 : begin + ap_NS_fsm = ap_ST_fsm_state4844; + end + ap_ST_fsm_state4844 : begin + ap_NS_fsm = ap_ST_fsm_state4845; + end + ap_ST_fsm_state4845 : begin + ap_NS_fsm = ap_ST_fsm_state4846; + end + ap_ST_fsm_state4846 : begin + ap_NS_fsm = ap_ST_fsm_state4847; + end + ap_ST_fsm_state4847 : begin + ap_NS_fsm = ap_ST_fsm_state4848; + end + ap_ST_fsm_state4848 : begin + ap_NS_fsm = ap_ST_fsm_state4849; + end + ap_ST_fsm_state4849 : begin + ap_NS_fsm = ap_ST_fsm_state4850; + end + ap_ST_fsm_state4850 : begin + ap_NS_fsm = ap_ST_fsm_state4851; + end + ap_ST_fsm_state4851 : begin + ap_NS_fsm = ap_ST_fsm_state4852; + end + ap_ST_fsm_state4852 : begin + ap_NS_fsm = ap_ST_fsm_state4853; + end + ap_ST_fsm_state4853 : begin + ap_NS_fsm = ap_ST_fsm_state4854; + end + ap_ST_fsm_state4854 : begin + ap_NS_fsm = ap_ST_fsm_state4855; + end + ap_ST_fsm_state4855 : begin + ap_NS_fsm = ap_ST_fsm_state4856; + end + ap_ST_fsm_state4856 : begin + ap_NS_fsm = ap_ST_fsm_state4857; + end + ap_ST_fsm_state4857 : begin + ap_NS_fsm = ap_ST_fsm_state4858; + end + ap_ST_fsm_state4858 : begin + ap_NS_fsm = ap_ST_fsm_state4859; + end + ap_ST_fsm_state4859 : begin + ap_NS_fsm = ap_ST_fsm_state4860; + end + ap_ST_fsm_state4860 : begin + ap_NS_fsm = ap_ST_fsm_state4861; + end + ap_ST_fsm_state4861 : begin + ap_NS_fsm = ap_ST_fsm_state4862; + end + ap_ST_fsm_state4862 : begin + ap_NS_fsm = ap_ST_fsm_state4863; + end + ap_ST_fsm_state4863 : begin + ap_NS_fsm = ap_ST_fsm_state4864; + end + ap_ST_fsm_state4864 : begin + ap_NS_fsm = ap_ST_fsm_state4865; + end + ap_ST_fsm_state4865 : begin + ap_NS_fsm = ap_ST_fsm_state4866; + end + ap_ST_fsm_state4866 : begin + ap_NS_fsm = ap_ST_fsm_state4867; + end + ap_ST_fsm_state4867 : begin + ap_NS_fsm = ap_ST_fsm_state4868; + end + ap_ST_fsm_state4868 : begin + ap_NS_fsm = ap_ST_fsm_state4869; + end + ap_ST_fsm_state4869 : begin + ap_NS_fsm = ap_ST_fsm_state4870; + end + ap_ST_fsm_state4870 : begin + ap_NS_fsm = ap_ST_fsm_state4871; + end + ap_ST_fsm_state4871 : begin + ap_NS_fsm = ap_ST_fsm_state4872; + end + ap_ST_fsm_state4872 : begin + ap_NS_fsm = ap_ST_fsm_state4873; + end + ap_ST_fsm_state4873 : begin + ap_NS_fsm = ap_ST_fsm_state4874; + end + ap_ST_fsm_state4874 : begin + ap_NS_fsm = ap_ST_fsm_state4875; + end + ap_ST_fsm_state4875 : begin + ap_NS_fsm = ap_ST_fsm_state4876; + end + ap_ST_fsm_state4876 : begin + ap_NS_fsm = ap_ST_fsm_state4800; + end + ap_ST_fsm_state4877 : begin + ap_NS_fsm = ap_ST_fsm_state4878; + end + ap_ST_fsm_state4878 : begin + ap_NS_fsm = ap_ST_fsm_state4879; + end + ap_ST_fsm_state4879 : begin + ap_NS_fsm = ap_ST_fsm_state4880; + end + ap_ST_fsm_state4880 : begin + ap_NS_fsm = ap_ST_fsm_state4881; + end + ap_ST_fsm_state4881 : begin + ap_NS_fsm = ap_ST_fsm_state4882; + end + ap_ST_fsm_state4882 : begin + ap_NS_fsm = ap_ST_fsm_state4883; + end + ap_ST_fsm_state4883 : begin + ap_NS_fsm = ap_ST_fsm_state4884; + end + ap_ST_fsm_state4884 : begin + ap_NS_fsm = ap_ST_fsm_state4885; + end + ap_ST_fsm_state4885 : begin + ap_NS_fsm = ap_ST_fsm_state4886; + end + ap_ST_fsm_state4886 : begin + ap_NS_fsm = ap_ST_fsm_state4887; + end + ap_ST_fsm_state4887 : begin + ap_NS_fsm = ap_ST_fsm_state4888; + end + ap_ST_fsm_state4888 : begin + ap_NS_fsm = ap_ST_fsm_state4889; + end + ap_ST_fsm_state4889 : begin + ap_NS_fsm = ap_ST_fsm_state4890; + end + ap_ST_fsm_state4890 : begin + ap_NS_fsm = ap_ST_fsm_state4891; + end + ap_ST_fsm_state4891 : begin + ap_NS_fsm = ap_ST_fsm_state4892; + end + ap_ST_fsm_state4892 : begin + ap_NS_fsm = ap_ST_fsm_state4893; + end + ap_ST_fsm_state4893 : begin + ap_NS_fsm = ap_ST_fsm_state4894; + end + ap_ST_fsm_state4894 : begin + ap_NS_fsm = ap_ST_fsm_state4895; + end + ap_ST_fsm_state4895 : begin + ap_NS_fsm = ap_ST_fsm_state4896; + end + ap_ST_fsm_state4896 : begin + ap_NS_fsm = ap_ST_fsm_state4897; + end + ap_ST_fsm_state4897 : begin + ap_NS_fsm = ap_ST_fsm_state4898; + end + ap_ST_fsm_state4898 : begin + ap_NS_fsm = ap_ST_fsm_state4899; + end + ap_ST_fsm_state4899 : begin + ap_NS_fsm = ap_ST_fsm_state4900; + end + ap_ST_fsm_state4900 : begin + ap_NS_fsm = ap_ST_fsm_state4901; + end + ap_ST_fsm_state4901 : begin + ap_NS_fsm = ap_ST_fsm_state4902; + end + ap_ST_fsm_state4902 : begin + ap_NS_fsm = ap_ST_fsm_state4903; + end + ap_ST_fsm_state4903 : begin + ap_NS_fsm = ap_ST_fsm_state4904; + end + ap_ST_fsm_state4904 : begin + ap_NS_fsm = ap_ST_fsm_state4905; + end + ap_ST_fsm_state4905 : begin + ap_NS_fsm = ap_ST_fsm_state4906; + end + ap_ST_fsm_state4906 : begin + ap_NS_fsm = ap_ST_fsm_state4907; + end + ap_ST_fsm_state4907 : begin + ap_NS_fsm = ap_ST_fsm_state4908; + end + ap_ST_fsm_state4908 : begin + ap_NS_fsm = ap_ST_fsm_state4909; + end + ap_ST_fsm_state4909 : begin + ap_NS_fsm = ap_ST_fsm_state4910; + end + ap_ST_fsm_state4910 : begin + ap_NS_fsm = ap_ST_fsm_state4911; + end + ap_ST_fsm_state4911 : begin + ap_NS_fsm = ap_ST_fsm_state4912; + end + ap_ST_fsm_state4912 : begin + ap_NS_fsm = ap_ST_fsm_state4913; + end + ap_ST_fsm_state4913 : begin + ap_NS_fsm = ap_ST_fsm_state4914; + end + ap_ST_fsm_state4914 : begin + ap_NS_fsm = ap_ST_fsm_state4915; + end + ap_ST_fsm_state4915 : begin + if (((icmp_ln266_15_fu_130784_p2 == 1'd1) & (icmp_ln268_23_fu_130761_p2 == 1'd1) & (ap_ST_fsm_state4915 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4722; + end else if (((icmp_ln268_23_fu_130761_p2 == 1'd1) & (ap_ST_fsm_state4915 == ap_CS_fsm) & (icmp_ln266_15_fu_130784_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state4953; + end else begin + ap_NS_fsm = ap_ST_fsm_state4916; + end + end + ap_ST_fsm_state4916 : begin + ap_NS_fsm = ap_ST_fsm_state4917; + end + ap_ST_fsm_state4917 : begin + ap_NS_fsm = ap_ST_fsm_state4918; + end + ap_ST_fsm_state4918 : begin + ap_NS_fsm = ap_ST_fsm_state4919; + end + ap_ST_fsm_state4919 : begin + ap_NS_fsm = ap_ST_fsm_state4920; + end + ap_ST_fsm_state4920 : begin + ap_NS_fsm = ap_ST_fsm_state4921; + end + ap_ST_fsm_state4921 : begin + ap_NS_fsm = ap_ST_fsm_state4922; + end + ap_ST_fsm_state4922 : begin + ap_NS_fsm = ap_ST_fsm_state4923; + end + ap_ST_fsm_state4923 : begin + ap_NS_fsm = ap_ST_fsm_state4924; + end + ap_ST_fsm_state4924 : begin + ap_NS_fsm = ap_ST_fsm_state4925; + end + ap_ST_fsm_state4925 : begin + ap_NS_fsm = ap_ST_fsm_state4926; + end + ap_ST_fsm_state4926 : begin + ap_NS_fsm = ap_ST_fsm_state4927; + end + ap_ST_fsm_state4927 : begin + ap_NS_fsm = ap_ST_fsm_state4928; + end + ap_ST_fsm_state4928 : begin + ap_NS_fsm = ap_ST_fsm_state4929; + end + ap_ST_fsm_state4929 : begin + ap_NS_fsm = ap_ST_fsm_state4930; + end + ap_ST_fsm_state4930 : begin + ap_NS_fsm = ap_ST_fsm_state4931; + end + ap_ST_fsm_state4931 : begin + ap_NS_fsm = ap_ST_fsm_state4932; + end + ap_ST_fsm_state4932 : begin + ap_NS_fsm = ap_ST_fsm_state4933; + end + ap_ST_fsm_state4933 : begin + ap_NS_fsm = ap_ST_fsm_state4934; + end + ap_ST_fsm_state4934 : begin + ap_NS_fsm = ap_ST_fsm_state4935; + end + ap_ST_fsm_state4935 : begin + ap_NS_fsm = ap_ST_fsm_state4936; + end + ap_ST_fsm_state4936 : begin + ap_NS_fsm = ap_ST_fsm_state4937; + end + ap_ST_fsm_state4937 : begin + ap_NS_fsm = ap_ST_fsm_state4938; + end + ap_ST_fsm_state4938 : begin + ap_NS_fsm = ap_ST_fsm_state4939; + end + ap_ST_fsm_state4939 : begin + ap_NS_fsm = ap_ST_fsm_state4940; + end + ap_ST_fsm_state4940 : begin + ap_NS_fsm = ap_ST_fsm_state4941; + end + ap_ST_fsm_state4941 : begin + ap_NS_fsm = ap_ST_fsm_state4942; + end + ap_ST_fsm_state4942 : begin + ap_NS_fsm = ap_ST_fsm_state4943; + end + ap_ST_fsm_state4943 : begin + ap_NS_fsm = ap_ST_fsm_state4944; + end + ap_ST_fsm_state4944 : begin + ap_NS_fsm = ap_ST_fsm_state4945; + end + ap_ST_fsm_state4945 : begin + ap_NS_fsm = ap_ST_fsm_state4946; + end + ap_ST_fsm_state4946 : begin + ap_NS_fsm = ap_ST_fsm_state4947; + end + ap_ST_fsm_state4947 : begin + ap_NS_fsm = ap_ST_fsm_state4948; + end + ap_ST_fsm_state4948 : begin + ap_NS_fsm = ap_ST_fsm_state4949; + end + ap_ST_fsm_state4949 : begin + ap_NS_fsm = ap_ST_fsm_state4950; + end + ap_ST_fsm_state4950 : begin + ap_NS_fsm = ap_ST_fsm_state4951; + end + ap_ST_fsm_state4951 : begin + ap_NS_fsm = ap_ST_fsm_state4952; + end + ap_ST_fsm_state4952 : begin + ap_NS_fsm = ap_ST_fsm_state4878; + end + ap_ST_fsm_state4953 : begin + ap_NS_fsm = ap_ST_fsm_state4954; + end + ap_ST_fsm_state4954 : begin + ap_NS_fsm = ap_ST_fsm_state4955; + end + ap_ST_fsm_state4955 : begin + ap_NS_fsm = ap_ST_fsm_state4956; + end + ap_ST_fsm_state4956 : begin + ap_NS_fsm = ap_ST_fsm_state4957; + end + ap_ST_fsm_state4957 : begin + ap_NS_fsm = ap_ST_fsm_state4958; + end + ap_ST_fsm_state4958 : begin + ap_NS_fsm = ap_ST_fsm_state4959; + end + ap_ST_fsm_state4959 : begin + ap_NS_fsm = ap_ST_fsm_state4960; + end + ap_ST_fsm_state4960 : begin + ap_NS_fsm = ap_ST_fsm_state4961; + end + ap_ST_fsm_state4961 : begin + ap_NS_fsm = ap_ST_fsm_state4962; + end + ap_ST_fsm_state4962 : begin + ap_NS_fsm = ap_ST_fsm_state4963; + end + ap_ST_fsm_state4963 : begin + ap_NS_fsm = ap_ST_fsm_state4964; + end + ap_ST_fsm_state4964 : begin + ap_NS_fsm = ap_ST_fsm_state4965; + end + ap_ST_fsm_state4965 : begin + ap_NS_fsm = ap_ST_fsm_state4966; + end + ap_ST_fsm_state4966 : begin + ap_NS_fsm = ap_ST_fsm_state4967; + end + ap_ST_fsm_state4967 : begin + ap_NS_fsm = ap_ST_fsm_state4968; + end + ap_ST_fsm_state4968 : begin + ap_NS_fsm = ap_ST_fsm_state4969; + end + ap_ST_fsm_state4969 : begin + ap_NS_fsm = ap_ST_fsm_state4970; + end + ap_ST_fsm_state4970 : begin + ap_NS_fsm = ap_ST_fsm_state4971; + end + ap_ST_fsm_state4971 : begin + ap_NS_fsm = ap_ST_fsm_state4972; + end + ap_ST_fsm_state4972 : begin + ap_NS_fsm = ap_ST_fsm_state4973; + end + ap_ST_fsm_state4973 : begin + ap_NS_fsm = ap_ST_fsm_state4974; + end + ap_ST_fsm_state4974 : begin + ap_NS_fsm = ap_ST_fsm_state4975; + end + ap_ST_fsm_state4975 : begin + ap_NS_fsm = ap_ST_fsm_state4976; + end + ap_ST_fsm_state4976 : begin + ap_NS_fsm = ap_ST_fsm_state4977; + end + ap_ST_fsm_state4977 : begin + ap_NS_fsm = ap_ST_fsm_state4978; + end + ap_ST_fsm_state4978 : begin + ap_NS_fsm = ap_ST_fsm_state4979; + end + ap_ST_fsm_state4979 : begin + ap_NS_fsm = ap_ST_fsm_state4980; + end + ap_ST_fsm_state4980 : begin + ap_NS_fsm = ap_ST_fsm_state4981; + end + ap_ST_fsm_state4981 : begin + ap_NS_fsm = ap_ST_fsm_state4982; + end + ap_ST_fsm_state4982 : begin + ap_NS_fsm = ap_ST_fsm_state4983; + end + ap_ST_fsm_state4983 : begin + ap_NS_fsm = ap_ST_fsm_state4984; + end + ap_ST_fsm_state4984 : begin + ap_NS_fsm = ap_ST_fsm_state4985; + end + ap_ST_fsm_state4985 : begin + ap_NS_fsm = ap_ST_fsm_state4986; + end + ap_ST_fsm_state4986 : begin + ap_NS_fsm = ap_ST_fsm_state4987; + end + ap_ST_fsm_state4987 : begin + ap_NS_fsm = ap_ST_fsm_state4988; + end + ap_ST_fsm_state4988 : begin + ap_NS_fsm = ap_ST_fsm_state4989; + end + ap_ST_fsm_state4989 : begin + ap_NS_fsm = ap_ST_fsm_state4990; + end + ap_ST_fsm_state4990 : begin + if (((icmp_ln268_31_fu_131165_p2 == 1'd1) & (ap_ST_fsm_state4990 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state4877; + end else begin + ap_NS_fsm = ap_ST_fsm_state4991; + end + end + ap_ST_fsm_state4991 : begin + ap_NS_fsm = ap_ST_fsm_state4992; + end + ap_ST_fsm_state4992 : begin + ap_NS_fsm = ap_ST_fsm_state4993; + end + ap_ST_fsm_state4993 : begin + ap_NS_fsm = ap_ST_fsm_state4994; + end + ap_ST_fsm_state4994 : begin + ap_NS_fsm = ap_ST_fsm_state4995; + end + ap_ST_fsm_state4995 : begin + ap_NS_fsm = ap_ST_fsm_state4996; + end + ap_ST_fsm_state4996 : begin + ap_NS_fsm = ap_ST_fsm_state4997; + end + ap_ST_fsm_state4997 : begin + ap_NS_fsm = ap_ST_fsm_state4998; + end + ap_ST_fsm_state4998 : begin + ap_NS_fsm = ap_ST_fsm_state4999; + end + ap_ST_fsm_state4999 : begin + ap_NS_fsm = ap_ST_fsm_state5000; + end + ap_ST_fsm_state5000 : begin + ap_NS_fsm = ap_ST_fsm_state5001; + end + ap_ST_fsm_state5001 : begin + ap_NS_fsm = ap_ST_fsm_state5002; + end + ap_ST_fsm_state5002 : begin + ap_NS_fsm = ap_ST_fsm_state5003; + end + ap_ST_fsm_state5003 : begin + ap_NS_fsm = ap_ST_fsm_state5004; + end + ap_ST_fsm_state5004 : begin + ap_NS_fsm = ap_ST_fsm_state5005; + end + ap_ST_fsm_state5005 : begin + ap_NS_fsm = ap_ST_fsm_state5006; + end + ap_ST_fsm_state5006 : begin + ap_NS_fsm = ap_ST_fsm_state5007; + end + ap_ST_fsm_state5007 : begin + ap_NS_fsm = ap_ST_fsm_state5008; + end + ap_ST_fsm_state5008 : begin + ap_NS_fsm = ap_ST_fsm_state5009; + end + ap_ST_fsm_state5009 : begin + ap_NS_fsm = ap_ST_fsm_state5010; + end + ap_ST_fsm_state5010 : begin + ap_NS_fsm = ap_ST_fsm_state5011; + end + ap_ST_fsm_state5011 : begin + ap_NS_fsm = ap_ST_fsm_state5012; + end + ap_ST_fsm_state5012 : begin + ap_NS_fsm = ap_ST_fsm_state5013; + end + ap_ST_fsm_state5013 : begin + ap_NS_fsm = ap_ST_fsm_state5014; + end + ap_ST_fsm_state5014 : begin + ap_NS_fsm = ap_ST_fsm_state5015; + end + ap_ST_fsm_state5015 : begin + ap_NS_fsm = ap_ST_fsm_state5016; + end + ap_ST_fsm_state5016 : begin + ap_NS_fsm = ap_ST_fsm_state5017; + end + ap_ST_fsm_state5017 : begin + ap_NS_fsm = ap_ST_fsm_state5018; + end + ap_ST_fsm_state5018 : begin + ap_NS_fsm = ap_ST_fsm_state5019; + end + ap_ST_fsm_state5019 : begin + ap_NS_fsm = ap_ST_fsm_state5020; + end + ap_ST_fsm_state5020 : begin + ap_NS_fsm = ap_ST_fsm_state5021; + end + ap_ST_fsm_state5021 : begin + ap_NS_fsm = ap_ST_fsm_state5022; + end + ap_ST_fsm_state5022 : begin + ap_NS_fsm = ap_ST_fsm_state5023; + end + ap_ST_fsm_state5023 : begin + ap_NS_fsm = ap_ST_fsm_state5024; + end + ap_ST_fsm_state5024 : begin + ap_NS_fsm = ap_ST_fsm_state5025; + end + ap_ST_fsm_state5025 : begin + ap_NS_fsm = ap_ST_fsm_state5026; + end + ap_ST_fsm_state5026 : begin + ap_NS_fsm = ap_ST_fsm_state4953; + end + ap_ST_fsm_state5027 : begin + ap_NS_fsm = ap_ST_fsm_state5028; + end + ap_ST_fsm_state5028 : begin + ap_NS_fsm = ap_ST_fsm_state5029; + end + ap_ST_fsm_state5029 : begin + ap_NS_fsm = ap_ST_fsm_state5030; + end + ap_ST_fsm_state5030 : begin + ap_NS_fsm = ap_ST_fsm_state5031; + end + ap_ST_fsm_state5031 : begin + ap_NS_fsm = ap_ST_fsm_state5032; + end + ap_ST_fsm_state5032 : begin + ap_NS_fsm = ap_ST_fsm_state5033; + end + ap_ST_fsm_state5033 : begin + ap_NS_fsm = ap_ST_fsm_state5034; + end + ap_ST_fsm_state5034 : begin + ap_NS_fsm = ap_ST_fsm_state5035; + end + ap_ST_fsm_state5035 : begin + ap_NS_fsm = ap_ST_fsm_state5036; + end + ap_ST_fsm_state5036 : begin + ap_NS_fsm = ap_ST_fsm_state5037; + end + ap_ST_fsm_state5037 : begin + ap_NS_fsm = ap_ST_fsm_state5038; + end + ap_ST_fsm_state5038 : begin + ap_NS_fsm = ap_ST_fsm_state5039; + end + ap_ST_fsm_state5039 : begin + ap_NS_fsm = ap_ST_fsm_state5040; + end + ap_ST_fsm_state5040 : begin + ap_NS_fsm = ap_ST_fsm_state5041; + end + ap_ST_fsm_state5041 : begin + ap_NS_fsm = ap_ST_fsm_state5042; + end + ap_ST_fsm_state5042 : begin + ap_NS_fsm = ap_ST_fsm_state5043; + end + ap_ST_fsm_state5043 : begin + ap_NS_fsm = ap_ST_fsm_state5044; + end + ap_ST_fsm_state5044 : begin + ap_NS_fsm = ap_ST_fsm_state5045; + end + ap_ST_fsm_state5045 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +assign add_ln1116_10_fu_110090_p2 = (zext_ln231_30_fu_110077_p1 + add_ln231_22_reg_139868); + +assign add_ln1116_11_fu_106645_p2 = (zext_ln231_32_fu_106632_p1 + add_ln231_25_reg_136261); + +assign add_ln1116_12_fu_110887_p2 = (zext_ln231_34_fu_110874_p1 + add_ln231_28_reg_140728); + +assign add_ln1116_13_fu_107449_p2 = (zext_ln231_36_fu_107436_p1 + or_ln231_16_reg_137104); + +assign add_ln1116_14_fu_113488_p2 = (zext_ln231_38_fu_113475_p1 + add_ln231_37_reg_143421); + +assign add_ln1116_15_fu_114283_p2 = (zext_ln231_40_fu_114270_p1 + add_ln231_42_reg_144281); + +assign add_ln1116_16_fu_103521_p2 = (zext_ln231_42_fu_103508_p1 + add_ln231_16_reg_132690); + +assign add_ln1116_17_fu_104325_p2 = (zext_ln231_44_fu_104312_p1 + or_ln231_11_reg_133533); + +assign add_ln1116_18_fu_110382_p2 = (zext_ln231_46_fu_110369_p1 + add_ln231_22_reg_139868); + +assign add_ln1116_19_fu_106936_p2 = (zext_ln231_48_fu_106923_p1 + add_ln231_25_reg_136261); + +assign add_ln1116_1_fu_109208_p2 = (zext_ln231_8_fu_109195_p1 + add_ln231_3_reg_138974); + +assign add_ln1116_20_fu_111177_p2 = (zext_ln231_50_fu_111164_p1 + add_ln231_28_reg_140728); + +assign add_ln1116_21_fu_107738_p2 = (zext_ln231_52_fu_107725_p1 + or_ln231_16_reg_137104); + +assign add_ln1116_22_fu_104838_p2 = (zext_ln231_54_fu_104825_p1 + add_ln231_55_reg_134430); + +assign add_ln1116_23_fu_113779_p2 = (zext_ln231_56_fu_113766_p1 + add_ln231_37_reg_143421); + +assign add_ln1116_24_fu_114572_p2 = (zext_ln231_58_fu_114559_p1 + add_ln231_42_reg_144281); + +assign add_ln1116_25_fu_111692_p2 = (zext_ln231_60_fu_111679_p1 + add_ln231_61_reg_141593); + +assign add_ln1116_26_fu_108250_p2 = (zext_ln231_62_fu_108237_p1 + add_ln231_66_reg_138001); + +assign add_ln1116_27_fu_115084_p2 = (zext_ln231_64_fu_115071_p1 + add_ln231_75_reg_145156); + +assign add_ln1116_28_fu_105128_p2 = (zext_ln231_66_fu_105115_p1 + add_ln231_55_reg_134430); + +assign add_ln1116_29_fu_111982_p2 = (zext_ln231_68_fu_111969_p1 + add_ln231_61_reg_141593); + +assign add_ln1116_2_fu_105767_p2 = (zext_ln231_10_fu_105754_p1 + or_ln231_s_reg_135353); + +assign add_ln1116_30_fu_108539_p2 = (zext_ln231_70_fu_108526_p1 + add_ln231_66_reg_138001); + +assign add_ln1116_31_fu_115373_p2 = (zext_ln231_72_fu_115360_p1 + add_ln231_75_reg_145156); + +assign add_ln1116_3_fu_112610_p2 = (zext_ln231_12_fu_112597_p1 + add_ln231_9_reg_142517); + +assign add_ln1116_4_fu_102639_p2 = (zext_ln231_15_fu_102626_p1 + or_ln231_8_reg_131794); + +assign add_ln1116_5_fu_109499_p2 = (zext_ln231_19_fu_109486_p1 + add_ln231_3_reg_138974); + +assign add_ln1116_6_fu_106057_p2 = (zext_ln231_21_fu_106044_p1 + or_ln231_s_reg_135353); + +assign add_ln1116_7_fu_103229_p2 = (zext_ln231_23_fu_103216_p1 + add_ln231_16_reg_132690); + +assign add_ln1116_8_fu_104035_p2 = (zext_ln231_26_fu_104022_p1 + or_ln231_11_reg_133533); + +assign add_ln1116_9_fu_112900_p2 = (zext_ln231_28_fu_112887_p1 + add_ln231_9_reg_142517); + +assign add_ln1116_fu_102347_p2 = (zext_ln231_6_fu_102334_p1 + or_ln231_8_reg_131794); + +assign add_ln1265_1_fu_124382_p2 = (trunc_ln279_10_reg_157419 + zext_ln279_17_fu_124373_p1); + +assign add_ln1265_2_fu_120855_p2 = (trunc_ln279_11_reg_147998 + zext_ln279_19_fu_120846_p1); + +assign add_ln1265_3_fu_117516_p2 = (trunc_ln279_reg_147602 + zext_ln279_21_fu_117507_p1); + +assign add_ln1265_4_fu_127897_p2 = (trunc_ln279_12_reg_157839 + zext_ln279_23_fu_127888_p1); + +assign add_ln1265_5_fu_124558_p2 = (trunc_ln279_10_reg_157419 + zext_ln279_25_fu_124549_p1); + +assign add_ln1265_6_fu_120984_p2 = (trunc_ln279_11_reg_147998 + zext_ln279_27_fu_120975_p1); + +assign add_ln1265_7_fu_128026_p2 = (trunc_ln279_12_reg_157839 + zext_ln279_29_fu_128017_p1); + +assign add_ln1265_fu_117340_p2 = (trunc_ln279_reg_147602 + zext_ln279_12_fu_117331_p1); + +assign add_ln199_fu_108844_p2 = (oh_0_0_reg_91149 + 4'd2); + +assign add_ln201_1_fu_112307_p2 = (ow_0_1_0_reg_93545 + 4'd2); + +assign add_ln201_fu_105453_p2 = (ow_0_0_0_reg_91161 + 4'd2); + +assign add_ln203_10_fu_116355_p2 = (trunc_ln250_5_reg_146028 + zext_ln250_14_fu_116277_p1); + +assign add_ln203_11_fu_117119_p2 = (trunc_ln250_6_reg_146499 + zext_ln250_15_fu_117041_p1); + +assign add_ln203_12_fu_101978_p2 = (phi_mul_reg_91184 + 11'd100); + +assign add_ln203_13_fu_108850_p2 = (phi_mul135708_reg_93568 + 11'd100); + +assign add_ln203_14_fu_105413_p2 = (phi_mul135689_reg_92370 + 11'd100); + +assign add_ln203_15_fu_112267_p2 = (phi_mul135727_reg_94754 + 11'd100); + +assign add_ln203_1_fu_108866_p2 = (ff_0_1_0_reg_93557 + 4'd1); + +assign add_ln203_2_fu_105429_p2 = (ff_0_0_1_reg_92359 + 4'd1); + +assign add_ln203_3_fu_112283_p2 = (ff_0_1_1_reg_94743 + 4'd1); + +assign add_ln203_4_fu_115829_p2 = (trunc_ln250_reg_146004 + zext_ln250_6_fu_115749_p1); + +assign add_ln203_5_fu_116593_p2 = (trunc_ln250_4_reg_146476 + zext_ln250_9_fu_116513_p1); + +assign add_ln203_6_fu_116205_p2 = (trunc_ln250_5_reg_146028 + zext_ln250_10_fu_116125_p1); + +assign add_ln203_7_fu_116022_p2 = (trunc_ln250_reg_146004 + zext_ln250_11_fu_115944_p1); + +assign add_ln203_8_fu_116969_p2 = (trunc_ln250_6_reg_146499 + zext_ln250_12_fu_116889_p1); + +assign add_ln203_9_fu_116786_p2 = (trunc_ln250_4_reg_146476 + zext_ln250_13_fu_116708_p1); + +assign add_ln203_fu_101994_p2 = (ff_0_0_0_reg_91173 + 4'd1); + +assign add_ln204_1_fu_111385_p2 = (cc_0_1_0_0_reg_93579 + 3'd2); + +assign add_ln204_2_fu_107940_p2 = (cc_0_0_1_0_reg_92381 + 3'd2); + +assign add_ln204_3_fu_114774_p2 = (cc_0_1_1_0_reg_94765 + 3'd2); + +assign add_ln204_fu_104527_p2 = (cc_0_0_0_0_reg_91195 + 3'd2); + +assign add_ln206_1_fu_110470_p2 = (fh_0_1_0_0_0_reg_93591 + 32'd2); + +assign add_ln206_2_fu_107024_p2 = (fh_0_0_1_0_0_reg_92393 + 32'd2); + +assign add_ln206_3_fu_113867_p2 = (fh_0_1_1_0_0_reg_94777 + 32'd2); + +assign add_ln206_4_fu_105215_p2 = (fh_0_0_0_1_0_reg_91787 + 32'd2); + +assign add_ln206_5_fu_112069_p2 = (fh_0_1_0_1_0_reg_94171 + 32'd2); + +assign add_ln206_6_fu_108626_p2 = (fh_0_0_1_1_0_reg_92973 + 32'd2); + +assign add_ln206_7_fu_115460_p2 = (fh_0_1_1_1_0_reg_95357 + 32'd2); + +assign add_ln206_fu_103609_p2 = (fh_0_0_0_0_0_reg_91207 + 32'd2); + +assign add_ln208_10_fu_114006_p2 = (fw_0_1_1_0_1_0_reg_95073 + 32'd2); + +assign add_ln208_11_fu_114912_p2 = (fw_0_1_1_1_0_0_reg_95369 + 32'd2); + +assign add_ln208_12_fu_105353_p2 = (fw_0_0_0_1_1_0_reg_92079 + 32'd2); + +assign add_ln208_13_fu_112207_p2 = (fw_0_1_0_1_1_0_reg_94463 + 32'd2); + +assign add_ln208_14_fu_108764_p2 = (fw_0_0_1_1_1_0_reg_93265 + 32'd2); + +assign add_ln208_15_fu_115598_p2 = (fw_0_1_1_1_1_0_reg_95649 + 32'd2); + +assign add_ln208_1_fu_109921_p2 = (fw_0_1_0_0_0_0_reg_93603 + 32'd2); + +assign add_ln208_2_fu_106473_p2 = (fw_0_0_1_0_0_0_reg_92405 + 32'd2); + +assign add_ln208_3_fu_113316_p2 = (fw_0_1_1_0_0_0_reg_94789 + 32'd2); + +assign add_ln208_4_fu_103748_p2 = (fw_0_0_0_0_1_0_reg_91503 + 32'd2); + +assign add_ln208_5_fu_104665_p2 = (fw_0_0_0_1_0_0_reg_91799 + 32'd2); + +assign add_ln208_6_fu_110609_p2 = (fw_0_1_0_0_1_0_reg_93887 + 32'd2); + +assign add_ln208_7_fu_107163_p2 = (fw_0_0_1_0_1_0_reg_92689 + 32'd2); + +assign add_ln208_8_fu_111523_p2 = (fw_0_1_0_1_0_0_reg_94183 + 32'd2); + +assign add_ln208_9_fu_108078_p2 = (fw_0_0_1_1_0_0_reg_92985 + 32'd2); + +assign add_ln208_fu_103056_p2 = (fw_0_0_0_0_0_0_reg_91219 + 32'd2); + +assign add_ln216_11_fu_109088_p2 = (add_ln216_18_fu_109083_p2 + shl_ln216_8_fu_109059_p2); + +assign add_ln216_13_fu_112293_p2 = (zext_ln216_14_fu_112289_p1 + mul_ln203_3_reg_138905); + +assign add_ln216_14_fu_112302_p2 = (mul_ln201_1_reg_131671 + zext_ln216_15_fu_112298_p1); + +assign add_ln216_16_fu_105643_p2 = (add_ln216_19_fu_105638_p2 + shl_ln216_9_fu_105614_p2); + +assign add_ln216_18_fu_109083_p2 = (fh_0_1_0_0_0_reg_93591 + zext_ln216_5_reg_138924); + +assign add_ln216_19_fu_105638_p2 = (fh_0_0_1_0_0_reg_92393 + zext_ln216_6_reg_135304); + +assign add_ln216_1_fu_102013_p2 = (mul_ln201_reg_131633 + zext_ln216_1_fu_102009_p1); + +assign add_ln216_21_fu_112486_p2 = (fh_0_1_1_0_0_reg_94777 + zext_ln216_7_reg_142467); + +assign add_ln216_22_fu_112491_p2 = (add_ln216_21_fu_112486_p2 + shl_ln216_10_fu_112462_p2); + +assign add_ln216_24_fu_102530_p2 = (or_ln208_fu_102518_p2 + add_ln216_4_reg_131776); + +assign add_ln216_26_fu_109390_p2 = (or_ln208_1_fu_109378_p2 + add_ln216_11_reg_138956); + +assign add_ln216_27_fu_105949_p2 = (or_ln208_2_fu_105937_p2 + add_ln216_16_reg_135335); + +assign add_ln216_28_fu_102818_p2 = (or_ln206_fu_102727_p2 + zext_ln216_3_reg_131745); + +assign add_ln216_29_fu_102823_p2 = (add_ln216_28_fu_102818_p2 + shl_ln216_11_fu_102739_p2); + +assign add_ln216_2_fu_108876_p2 = (zext_ln216_2_fu_108872_p1 + mul_ln203_1_reg_138846); + +assign add_ln216_31_fu_103914_p2 = (fh_0_0_0_1_0_reg_91787 + zext_ln216_8_reg_132577); + +assign add_ln216_32_fu_103919_p2 = (add_ln216_31_fu_103914_p2 + shl_ln216_12_fu_103886_p2); + +assign add_ln216_34_fu_109684_p2 = (or_ln206_1_fu_109587_p2 + zext_ln216_5_reg_138924); + +assign add_ln216_36_fu_112792_p2 = (or_ln208_3_fu_112780_p2 + add_ln216_22_reg_142499); + +assign add_ln216_37_fu_109689_p2 = (add_ln216_34_fu_109684_p2 + shl_ln216_13_fu_109599_p2); + +assign add_ln216_40_fu_106236_p2 = (or_ln206_2_fu_106145_p2 + zext_ln216_6_reg_135304); + +assign add_ln216_41_fu_106241_p2 = (add_ln216_40_fu_106236_p2 + shl_ln216_14_fu_106157_p2); + +assign add_ln216_43_fu_110762_p2 = (fh_0_1_0_1_0_reg_94171 + zext_ln216_9_reg_139763); + +assign add_ln216_44_fu_110767_p2 = (add_ln216_43_fu_110762_p2 + shl_ln216_15_fu_110738_p2); + +assign add_ln216_45_fu_107329_p2 = (fh_0_0_1_1_0_reg_92973 + zext_ln216_10_reg_136148); + +assign add_ln216_47_fu_107334_p2 = (add_ln216_45_fu_107329_p2 + shl_ln216_16_fu_107301_p2); + +assign add_ln216_4_fu_102222_p2 = (add_ln216_9_fu_102217_p2 + shl_ln216_fu_102193_p2); + +assign add_ln216_50_fu_113079_p2 = (or_ln206_3_fu_112988_p2 + zext_ln216_7_reg_142467); + +assign add_ln216_51_fu_113084_p2 = (add_ln216_50_fu_113079_p2 + shl_ln216_17_fu_113000_p2); + +assign add_ln216_53_fu_114159_p2 = (fh_0_1_1_1_0_reg_95357 + zext_ln216_11_reg_143312); + +assign add_ln216_54_fu_114164_p2 = (add_ln216_53_fu_114159_p2 + shl_ln216_18_fu_114135_p2); + +assign add_ln216_56_fu_103412_p2 = (or_ln208_4_fu_103400_p2 + add_ln216_29_reg_132549); + +assign add_ln216_57_fu_104216_p2 = (or_ln208_5_fu_104204_p2 + add_ln216_32_reg_133543); + +assign add_ln216_58_fu_110273_p2 = (or_ln208_6_fu_110261_p2 + add_ln216_37_reg_139735); + +assign add_ln216_59_fu_106828_p2 = (or_ln208_7_fu_106816_p2 + add_ln216_41_reg_136120); + +assign add_ln216_60_fu_104503_p2 = (or_ln206_4_fu_104412_p2 + zext_ln216_8_reg_132577); + +assign add_ln216_61_fu_111068_p2 = (or_ln208_8_fu_111056_p2 + add_ln216_44_reg_140710); + +assign add_ln216_62_fu_107630_p2 = (or_ln208_9_fu_107618_p2 + add_ln216_47_reg_137114); + +assign add_ln216_63_fu_104508_p2 = (add_ln216_60_fu_104503_p2 + shl_ln216_19_fu_104424_p2); + +assign add_ln216_65_fu_113671_p2 = (or_ln208_10_fu_113659_p2 + add_ln216_51_reg_143284); + +assign add_ln216_66_fu_111361_p2 = (or_ln206_5_fu_111264_p2 + zext_ln216_9_reg_139763); + +assign add_ln216_67_fu_111366_p2 = (add_ln216_66_fu_111361_p2 + shl_ln216_20_fu_111276_p2); + +assign add_ln216_68_fu_114464_p2 = (or_ln208_11_fu_114452_p2 + add_ln216_54_reg_144263); + +assign add_ln216_69_fu_107916_p2 = (or_ln206_6_fu_107825_p2 + zext_ln216_10_reg_136148); + +assign add_ln216_6_fu_108885_p2 = (mul_ln201_1_reg_131671 + zext_ln216_4_fu_108881_p1); + +assign add_ln216_71_fu_107921_p2 = (add_ln216_69_fu_107916_p2 + shl_ln216_21_fu_107837_p2); + +assign add_ln216_73_fu_114750_p2 = (or_ln206_7_fu_114659_p2 + zext_ln216_11_reg_143312); + +assign add_ln216_74_fu_114755_p2 = (add_ln216_73_fu_114750_p2 + shl_ln216_22_fu_114671_p2); + +assign add_ln216_76_fu_105019_p2 = (or_ln208_12_fu_105007_p2 + add_ln216_63_reg_134312); + +assign add_ln216_77_fu_111873_p2 = (or_ln208_13_fu_111861_p2 + add_ln216_67_reg_141479); + +assign add_ln216_78_fu_108431_p2 = (or_ln208_14_fu_108419_p2 + add_ln216_71_reg_137883); + +assign add_ln216_79_fu_115265_p2 = (or_ln208_15_fu_115253_p2 + add_ln216_74_reg_145038); + +assign add_ln216_7_fu_105439_p2 = (zext_ln216_12_fu_105435_p1 + mul_ln203_2_reg_131726); + +assign add_ln216_8_fu_105448_p2 = (mul_ln201_reg_131633 + zext_ln216_13_fu_105444_p1); + +assign add_ln216_9_fu_102217_p2 = (fh_0_0_0_0_0_reg_91207 + zext_ln216_3_reg_131745); + +assign add_ln216_fu_102004_p2 = (zext_ln216_fu_102000_p1 + mul_ln203_reg_131654); + +assign add_ln221_10_fu_105685_p2 = (sub_ln221_9_fu_105679_p2 + add_ln221_9_reg_135341); + +assign add_ln221_11_fu_112357_p2 = (zext_ln203_23_reg_142428 + sub_ln221_7_fu_112351_p2); + +assign add_ln221_12_fu_112497_p2 = ((sub_ln221_10_fu_112480_p2) + (sext_ln221_3_reg_142461)); + +assign add_ln221_13_fu_112528_p2 = (sub_ln221_11_fu_112522_p2 + add_ln221_12_reg_142505); + +assign add_ln221_14_fu_102554_p2 = (sub_ln221_12_fu_102548_p2 + add_ln221_3_reg_131782); + +assign add_ln221_15_fu_109414_p2 = (sub_ln221_15_fu_109408_p2 + add_ln221_6_reg_138962); + +assign add_ln221_16_fu_105973_p2 = (sub_ln221_16_fu_105967_p2 + add_ln221_9_reg_135341); + +assign add_ln221_17_fu_102829_p2 = ((sub_ln221_14_fu_102757_p2) + (sext_ln221_reg_131739)); + +assign add_ln221_18_fu_103146_p2 = (sub_ln221_18_fu_103140_p2 + add_ln221_17_reg_132555); + +assign add_ln221_19_fu_102881_p2 = (zext_ln203_4_reg_131682 + sub_ln221_13_fu_102875_p2); + +assign add_ln221_20_fu_103925_p2 = ((sub_ln221_17_fu_103904_p2) + (sext_ln221_4_reg_132571)); + +assign add_ln221_21_fu_103952_p2 = (sub_ln221_23_fu_103946_p2 + add_ln221_20_reg_133549); + +assign add_ln221_22_fu_112816_p2 = (sub_ln221_24_fu_112810_p2 + add_ln221_12_reg_142505); + +assign add_ln221_23_fu_109695_p2 = ((sub_ln221_20_fu_109617_p2) + (sext_ln221_1_reg_138918)); + +assign add_ln221_24_fu_110007_p2 = (sub_ln221_26_fu_110001_p2 + add_ln221_23_reg_139741); + +assign add_ln221_25_fu_106247_p2 = ((sub_ln221_22_fu_106175_p2) + (sext_ln221_2_reg_135298)); + +assign add_ln221_26_fu_106563_p2 = (sub_ln221_28_fu_106557_p2 + add_ln221_25_reg_136126); + +assign add_ln221_27_fu_109747_p2 = (zext_ln203_9_reg_138861 + sub_ln221_19_fu_109741_p2); + +assign add_ln221_28_fu_110773_p2 = ((sub_ln221_25_fu_110756_p2) + (sext_ln221_5_reg_139757)); + +assign add_ln221_29_fu_110804_p2 = (sub_ln221_31_fu_110798_p2 + add_ln221_28_reg_140716); + +assign add_ln221_30_fu_106299_p2 = (zext_ln203_14_reg_135265 + sub_ln221_21_fu_106293_p2); + +assign add_ln221_31_fu_107340_p2 = ((sub_ln221_27_fu_107319_p2) + (sext_ln221_6_reg_136142)); + +assign add_ln221_32_fu_107367_p2 = (sub_ln221_32_fu_107361_p2 + add_ln221_31_reg_137120); + +assign add_ln221_33_fu_113090_p2 = ((sub_ln221_30_fu_113018_p2) + (sext_ln221_3_reg_142461)); + +assign add_ln221_34_fu_113406_p2 = (sub_ln221_34_fu_113400_p2 + add_ln221_33_reg_143290); + +assign add_ln221_35_fu_113142_p2 = (zext_ln203_23_reg_142428 + sub_ln221_29_fu_113136_p2); + +assign add_ln221_36_fu_114170_p2 = ((sub_ln221_33_fu_114153_p2) + (sext_ln221_7_reg_143306)); + +assign add_ln221_37_fu_114201_p2 = (sub_ln221_35_fu_114195_p2 + add_ln221_36_reg_144269); + +assign add_ln221_38_fu_103436_p2 = (sub_ln221_36_fu_103430_p2 + add_ln221_17_reg_132555); + +assign add_ln221_39_fu_104240_p2 = (sub_ln221_37_fu_104234_p2 + add_ln221_20_reg_133549); + +assign add_ln221_3_fu_102228_p2 = ((sub_ln221_1_fu_102211_p2) + (sext_ln221_reg_131739)); + +assign add_ln221_40_fu_110297_p2 = (sub_ln221_38_fu_110291_p2 + add_ln221_23_reg_139741); + +assign add_ln221_41_fu_106852_p2 = (sub_ln221_39_fu_106846_p2 + add_ln221_25_reg_136126); + +assign add_ln221_42_fu_111092_p2 = (sub_ln221_41_fu_111086_p2 + add_ln221_28_reg_140716); + +assign add_ln221_43_fu_107654_p2 = (sub_ln221_42_fu_107648_p2 + add_ln221_31_reg_137120); + +assign add_ln221_44_fu_104514_p2 = ((sub_ln221_40_fu_104442_p2) + (sext_ln221_4_reg_132571)); + +assign add_ln221_45_fu_104755_p2 = (sub_ln221_43_fu_104749_p2 + add_ln221_44_reg_134318); + +assign add_ln221_46_fu_113695_p2 = (sub_ln221_44_fu_113689_p2 + add_ln221_33_reg_143290); + +assign add_ln221_47_fu_114488_p2 = (sub_ln221_47_fu_114482_p2 + add_ln221_36_reg_144269); + +assign add_ln221_48_fu_111372_p2 = ((sub_ln221_45_fu_111294_p2) + (sext_ln221_5_reg_139757)); + +assign add_ln221_49_fu_111609_p2 = (sub_ln221_48_fu_111603_p2 + add_ln221_48_reg_141485); + +assign add_ln221_4_fu_102264_p2 = (sub_ln221_4_fu_102258_p2 + add_ln221_3_reg_131782); + +assign add_ln221_50_fu_107927_p2 = ((sub_ln221_46_fu_107855_p2) + (sext_ln221_6_reg_136142)); + +assign add_ln221_51_fu_108168_p2 = (sub_ln221_49_fu_108162_p2 + add_ln221_50_reg_137889); + +assign add_ln221_52_fu_114761_p2 = ((sub_ln221_50_fu_114689_p2) + (sext_ln221_7_reg_143306)); + +assign add_ln221_53_fu_115002_p2 = (sub_ln221_51_fu_114996_p2 + add_ln221_52_reg_145044); + +assign add_ln221_54_fu_105043_p2 = (sub_ln221_52_fu_105037_p2 + add_ln221_44_reg_134318); + +assign add_ln221_55_fu_111897_p2 = (sub_ln221_53_fu_111891_p2 + add_ln221_48_reg_141485); + +assign add_ln221_56_fu_108455_p2 = (sub_ln221_54_fu_108449_p2 + add_ln221_50_reg_137889); + +assign add_ln221_57_fu_115289_p2 = (sub_ln221_55_fu_115283_p2 + add_ln221_52_reg_145044); + +assign add_ln221_5_fu_108954_p2 = (zext_ln203_9_reg_138861 + sub_ln221_2_fu_108948_p2); + +assign add_ln221_6_fu_109094_p2 = ((sub_ln221_5_fu_109077_p2) + (sext_ln221_1_reg_138918)); + +assign add_ln221_7_fu_109125_p2 = (sub_ln221_8_fu_109119_p2 + add_ln221_6_reg_138962); + +assign add_ln221_8_fu_105503_p2 = (zext_ln203_14_reg_135265 + sub_ln221_3_fu_105497_p2); + +assign add_ln221_9_fu_105649_p2 = ((sub_ln221_6_fu_105632_p2) + (sext_ln221_2_reg_135298)); + +assign add_ln221_fu_102082_p2 = (zext_ln203_4_reg_131682 + sub_ln221_fu_102076_p2); + +assign add_ln223_10_fu_103808_p2 = (fh_0_0_0_1_0_reg_91787 + oh_0_0_cast_reg_131618); + +assign add_ln223_11_fu_109623_p2 = (or_ln206_1_fu_109587_p2 + zext_ln199_reg_131659); + +assign add_ln223_12_fu_109425_p2 = (or_ln208_1_fu_109378_p2 + ow_0_1_0_cast_reg_138831); + +assign add_ln223_13_fu_106181_p2 = (or_ln206_2_fu_106145_p2 + oh_0_0_cast_reg_131618); + +assign add_ln223_14_fu_105984_p2 = (or_ln208_2_fu_105937_p2 + zext_ln201_2_reg_131714); + +assign add_ln223_15_fu_103151_p2 = (fw_0_0_0_0_1_0_reg_91503 + ow_0_0_0_cast_reg_131639); + +assign add_ln223_16_fu_110669_p2 = (fh_0_1_0_1_0_reg_94171 + zext_ln199_reg_131659); + +assign add_ln223_17_fu_107223_p2 = (fh_0_0_1_1_0_reg_92973 + oh_0_0_cast_reg_131618); + +assign add_ln223_18_fu_103957_p2 = (fw_0_0_0_1_0_0_reg_91799 + ow_0_0_0_cast_reg_131639); + +assign add_ln223_19_fu_113024_p2 = (or_ln206_3_fu_112988_p2 + zext_ln199_reg_131659); + +assign add_ln223_1_fu_108990_p2 = (fh_0_1_0_0_0_reg_93591 + zext_ln199_reg_131659); + +assign add_ln223_20_fu_112827_p2 = (or_ln208_3_fu_112780_p2 + zext_ln201_3_reg_138893); + +assign add_ln223_21_fu_110012_p2 = (fw_0_1_0_0_1_0_reg_93887 + ow_0_1_0_cast_reg_138831); + +assign add_ln223_22_fu_106568_p2 = (fw_0_0_1_0_1_0_reg_92689 + zext_ln201_2_reg_131714); + +assign add_ln223_23_fu_114066_p2 = (fh_0_1_1_1_0_reg_95357 + zext_ln199_reg_131659); + +assign add_ln223_24_fu_110809_p2 = (fw_0_1_0_1_0_0_reg_94183 + ow_0_1_0_cast_reg_138831); + +assign add_ln223_25_fu_107372_p2 = (fw_0_0_1_1_0_0_reg_92985 + zext_ln201_2_reg_131714); + +assign add_ln223_26_fu_113411_p2 = (fw_0_1_1_0_1_0_reg_95073 + zext_ln201_3_reg_138893); + +assign add_ln223_27_fu_114206_p2 = (fw_0_1_1_1_0_0_reg_95369 + zext_ln201_3_reg_138893); + +assign add_ln223_28_fu_103447_p2 = (or_ln208_4_fu_103400_p2 + ow_0_0_0_cast_reg_131639); + +assign add_ln223_29_fu_104448_p2 = (or_ln206_4_fu_104412_p2 + oh_0_0_cast_reg_131618); + +assign add_ln223_2_fu_105539_p2 = (fh_0_0_1_0_0_reg_92393 + oh_0_0_cast_reg_131618); + +assign add_ln223_30_fu_104251_p2 = (or_ln208_5_fu_104204_p2 + ow_0_0_0_cast_reg_131639); + +assign add_ln223_31_fu_110308_p2 = (or_ln208_6_fu_110261_p2 + ow_0_1_0_cast_reg_138831); + +assign add_ln223_32_fu_106863_p2 = (or_ln208_7_fu_106816_p2 + zext_ln201_2_reg_131714); + +assign add_ln223_33_fu_111300_p2 = (or_ln206_5_fu_111264_p2 + zext_ln199_reg_131659); + +assign add_ln223_34_fu_111103_p2 = (or_ln208_8_fu_111056_p2 + ow_0_1_0_cast_reg_138831); + +assign add_ln223_35_fu_107861_p2 = (or_ln206_6_fu_107825_p2 + oh_0_0_cast_reg_131618); + +assign add_ln223_36_fu_107665_p2 = (or_ln208_9_fu_107618_p2 + zext_ln201_2_reg_131714); + +assign add_ln223_37_fu_104760_p2 = (fw_0_0_0_1_1_0_reg_92079 + ow_0_0_0_cast_reg_131639); + +assign add_ln223_38_fu_113706_p2 = (or_ln208_10_fu_113659_p2 + zext_ln201_3_reg_138893); + +assign add_ln223_39_fu_114695_p2 = (or_ln206_7_fu_114659_p2 + zext_ln199_reg_131659); + +assign add_ln223_3_fu_102269_p2 = (fw_0_0_0_0_0_0_reg_91219 + ow_0_0_0_cast_reg_131639); + +assign add_ln223_40_fu_114499_p2 = (or_ln208_11_fu_114452_p2 + zext_ln201_3_reg_138893); + +assign add_ln223_41_fu_111614_p2 = (fw_0_1_0_1_1_0_reg_94463 + ow_0_1_0_cast_reg_138831); + +assign add_ln223_42_fu_108173_p2 = (fw_0_0_1_1_1_0_reg_93265 + zext_ln201_2_reg_131714); + +assign add_ln223_43_fu_115007_p2 = (fw_0_1_1_1_1_0_reg_95649 + zext_ln201_3_reg_138893); + +assign add_ln223_44_fu_105054_p2 = (or_ln208_12_fu_105007_p2 + ow_0_0_0_cast_reg_131639); + +assign add_ln223_45_fu_111908_p2 = (or_ln208_13_fu_111861_p2 + ow_0_1_0_cast_reg_138831); + +assign add_ln223_46_fu_108466_p2 = (or_ln208_14_fu_108419_p2 + zext_ln201_2_reg_131714); + +assign add_ln223_47_fu_115300_p2 = (or_ln208_15_fu_115253_p2 + zext_ln201_3_reg_138893); + +assign add_ln223_4_fu_112393_p2 = (fh_0_1_1_0_0_reg_94777 + zext_ln199_reg_131659); + +assign add_ln223_5_fu_109130_p2 = (fw_0_1_0_0_0_0_reg_93603 + ow_0_1_0_cast_reg_138831); + +assign add_ln223_6_fu_105690_p2 = (fw_0_0_1_0_0_0_reg_92405 + zext_ln201_2_reg_131714); + +assign add_ln223_7_fu_112533_p2 = (fw_0_1_1_0_0_0_reg_94789 + zext_ln201_3_reg_138893); + +assign add_ln223_8_fu_102763_p2 = (or_ln206_fu_102727_p2 + oh_0_0_cast_reg_131618); + +assign add_ln223_9_fu_102565_p2 = (or_ln208_fu_102518_p2 + ow_0_0_0_cast_reg_131639); + +assign add_ln223_fu_102118_p2 = (fh_0_0_0_0_0_reg_91207 + oh_0_0_cast_reg_131618); + +assign add_ln231_10_fu_109177_p2 = (trunc_ln223_1_fu_109135_p1 + ow_0_1_0_reg_93545); + +assign add_ln231_11_fu_112601_p2 = (zext_ln231_11_fu_112593_p1 + add_ln231_7_reg_142511); + +assign add_ln231_12_fu_105737_p2 = (trunc_ln223_2_fu_105695_p1 + or_ln201_reg_131702); + +assign add_ln231_13_fu_112580_p2 = (trunc_ln223_3_fu_112538_p1 + or_ln201_1_reg_138881); + +assign add_ln231_14_fu_102630_p2 = (zext_ln231_14_fu_102622_p1 + add_ln231_reg_131788); + +assign add_ln231_15_fu_103120_p2 = ((trunc_ln231_24_reg_132566) + (sext_ln231_reg_131751)); + +assign add_ln231_16_fu_103124_p2 = (trunc_ln231_23_reg_132561 + zext_ln231_reg_131757); + +assign add_ln231_17_fu_109490_p2 = (zext_ln231_18_fu_109482_p1 + add_ln231_1_reg_138968); + +assign add_ln231_18_fu_103930_p2 = ((trunc_ln231_25_reg_133528) + (sext_ln231_4_reg_132588)); + +assign add_ln231_19_fu_102608_p2 = (ow_0_0_0_reg_91161 + or_ln223_48_fu_102559_p2); + +assign add_ln231_1_fu_109099_p2 = ((trunc_ln231_19_reg_138951) + (sext_ln231_1_reg_138936)); + +assign add_ln231_20_fu_106048_p2 = (zext_ln231_20_fu_106040_p1 + add_ln231_4_reg_135347); + +assign add_ln231_21_fu_109981_p2 = ((trunc_ln231_27_reg_139752) + (sext_ln231_1_reg_138936)); + +assign add_ln231_22_fu_109985_p2 = (trunc_ln231_26_reg_139747 + zext_ln231_1_reg_138930); + +assign add_ln231_23_fu_103220_p2 = (zext_ln231_22_fu_103212_p1 + add_ln231_15_reg_132684); + +assign add_ln231_24_fu_106537_p2 = ((trunc_ln231_29_reg_136137) + (sext_ln231_2_reg_135310)); + +assign add_ln231_25_fu_106541_p2 = (trunc_ln231_28_reg_136132 + zext_ln231_2_reg_135316); + +assign add_ln231_26_fu_104026_p2 = (zext_ln231_25_fu_104018_p1 + add_ln231_18_reg_133555); + +assign add_ln231_27_fu_110778_p2 = ((trunc_ln231_31_reg_140705) + (sext_ln231_5_reg_139775)); + +assign add_ln231_28_fu_110782_p2 = (trunc_ln231_30_reg_140700 + zext_ln231_16_reg_139769); + +assign add_ln231_29_fu_112891_p2 = (zext_ln231_27_fu_112883_p1 + add_ln231_7_reg_142511); + +assign add_ln231_2_fu_102338_p2 = (zext_ln231_5_fu_102330_p1 + add_ln231_reg_131788); + +assign add_ln231_30_fu_109468_p2 = (ow_0_1_0_reg_93545 + or_ln223_49_fu_109419_p2); + +assign add_ln231_31_fu_107345_p2 = ((trunc_ln231_32_reg_137099) + (sext_ln231_6_reg_136159)); + +assign add_ln231_32_fu_110081_p2 = (zext_ln231_29_fu_110073_p1 + add_ln231_21_reg_139862); + +assign add_ln231_33_fu_106027_p2 = (or_ln201_reg_131702 + or_ln223_50_fu_105978_p2); + +assign add_ln231_34_fu_103198_p2 = (trunc_ln223_8_fu_103156_p1 + ow_0_0_0_reg_91161); + +assign add_ln231_35_fu_106636_p2 = (zext_ln231_31_fu_106628_p1 + add_ln231_24_reg_136255); + +assign add_ln231_36_fu_113380_p2 = ((trunc_ln231_34_reg_143301) + (sext_ln231_3_reg_142479)); + +assign add_ln231_37_fu_113384_p2 = (trunc_ln231_33_reg_143296 + zext_ln231_3_reg_142473); + +assign add_ln231_38_fu_110878_p2 = (zext_ln231_33_fu_110870_p1 + add_ln231_27_reg_140722); + +assign add_ln231_39_fu_104004_p2 = (trunc_ln223_9_fu_103962_p1 + ow_0_0_0_reg_91161); + +assign add_ln231_3_fu_109103_p2 = (trunc_ln231_18_reg_138946 + zext_ln231_1_reg_138930); + +assign add_ln231_40_fu_114175_p2 = ((trunc_ln231_36_reg_144258) + (sext_ln231_7_reg_143324)); + +assign add_ln231_41_fu_107440_p2 = (zext_ln231_35_fu_107432_p1 + add_ln231_31_reg_137126); + +assign add_ln231_42_fu_114179_p2 = (trunc_ln231_35_reg_144253 + zext_ln231_24_reg_143318); + +assign add_ln231_43_fu_112870_p2 = (or_ln201_1_reg_138881 + or_ln223_51_fu_112821_p2); + +assign add_ln231_44_fu_113479_p2 = (zext_ln231_37_fu_113471_p1 + add_ln231_36_reg_143415); + +assign add_ln231_45_fu_110059_p2 = (trunc_ln223_10_fu_110017_p1 + ow_0_1_0_reg_93545); + +assign add_ln231_46_fu_106615_p2 = (trunc_ln223_11_fu_106573_p1 + or_ln201_reg_131702); + +assign add_ln231_47_fu_114274_p2 = (zext_ln231_39_fu_114266_p1 + add_ln231_40_reg_144275); + +assign add_ln231_48_fu_110856_p2 = (trunc_ln223_12_fu_110814_p1 + ow_0_1_0_reg_93545); + +assign add_ln231_49_fu_107419_p2 = (trunc_ln223_13_fu_107377_p1 + or_ln201_reg_131702); + +assign add_ln231_4_fu_105654_p2 = ((trunc_ln231_20_reg_135325) + (sext_ln231_2_reg_135310)); + +assign add_ln231_50_fu_103512_p2 = (zext_ln231_41_fu_103504_p1 + add_ln231_15_reg_132684); + +assign add_ln231_51_fu_113458_p2 = (trunc_ln223_14_fu_113416_p1 + or_ln201_1_reg_138881); + +assign add_ln231_52_fu_114253_p2 = (trunc_ln223_15_fu_114211_p1 + or_ln201_1_reg_138881); + +assign add_ln231_53_fu_104316_p2 = (zext_ln231_43_fu_104308_p1 + add_ln231_18_reg_133555); + +assign add_ln231_54_fu_104729_p2 = ((trunc_ln231_38_reg_134329) + (sext_ln231_4_reg_132588)); + +assign add_ln231_55_fu_104733_p2 = (trunc_ln231_37_reg_134324 + zext_ln231_13_reg_132594); + +assign add_ln231_56_fu_110373_p2 = (zext_ln231_45_fu_110365_p1 + add_ln231_21_reg_139862); + +assign add_ln231_57_fu_103490_p2 = (ow_0_0_0_reg_91161 + or_ln223_52_fu_103441_p2); + +assign add_ln231_58_fu_104294_p2 = (ow_0_0_0_reg_91161 + or_ln223_53_fu_104245_p2); + +assign add_ln231_59_fu_106927_p2 = (zext_ln231_47_fu_106919_p1 + add_ln231_24_reg_136255); + +assign add_ln231_5_fu_109199_p2 = (zext_ln231_7_fu_109191_p1 + add_ln231_1_reg_138968); + +assign add_ln231_60_fu_111583_p2 = ((trunc_ln231_40_reg_141496) + (sext_ln231_5_reg_139775)); + +assign add_ln231_61_fu_111587_p2 = (trunc_ln231_39_reg_141491 + zext_ln231_16_reg_139769); + +assign add_ln231_62_fu_111168_p2 = (zext_ln231_49_fu_111160_p1 + add_ln231_27_reg_140722); + +assign add_ln231_63_fu_110351_p2 = (ow_0_1_0_reg_93545 + or_ln223_54_fu_110302_p2); + +assign add_ln231_64_fu_108142_p2 = ((trunc_ln231_42_reg_137900) + (sext_ln231_6_reg_136159)); + +assign add_ln231_65_fu_107729_p2 = (zext_ln231_51_fu_107721_p1 + add_ln231_31_reg_137126); + +assign add_ln231_66_fu_108146_p2 = (trunc_ln231_41_reg_137895 + zext_ln231_17_reg_136165); + +assign add_ln231_67_fu_106906_p2 = (or_ln201_reg_131702 + or_ln223_55_fu_106857_p2); + +assign add_ln231_68_fu_104829_p2 = (zext_ln231_53_fu_104821_p1 + add_ln231_54_reg_134424); + +assign add_ln231_69_fu_111146_p2 = (ow_0_1_0_reg_93545 + or_ln223_56_fu_111097_p2); + +assign add_ln231_6_fu_102316_p2 = (trunc_ln223_fu_102274_p1 + ow_0_0_0_reg_91161); + +assign add_ln231_70_fu_107708_p2 = (or_ln201_reg_131702 + or_ln223_57_fu_107659_p2); + +assign add_ln231_71_fu_113770_p2 = (zext_ln231_55_fu_113762_p1 + add_ln231_36_reg_143415); + +assign add_ln231_72_fu_104807_p2 = (trunc_ln223_24_fu_104765_p1 + ow_0_0_0_reg_91161); + +assign add_ln231_73_fu_114976_p2 = ((trunc_ln231_44_reg_145055) + (sext_ln231_7_reg_143324)); + +assign add_ln231_74_fu_114563_p2 = (zext_ln231_57_fu_114555_p1 + add_ln231_40_reg_144275); + +assign add_ln231_75_fu_114980_p2 = (trunc_ln231_43_reg_145050 + zext_ln231_24_reg_143318); + +assign add_ln231_76_fu_113749_p2 = (or_ln201_1_reg_138881 + or_ln223_58_fu_113700_p2); + +assign add_ln231_77_fu_111683_p2 = (zext_ln231_59_fu_111675_p1 + add_ln231_60_reg_141587); + +assign add_ln231_78_fu_114542_p2 = (or_ln201_1_reg_138881 + or_ln223_59_fu_114493_p2); + +assign add_ln231_79_fu_111661_p2 = (trunc_ln223_25_fu_111619_p1 + ow_0_1_0_reg_93545); + +assign add_ln231_7_fu_112502_p2 = ((trunc_ln231_22_reg_142494) + (sext_ln231_3_reg_142479)); + +assign add_ln231_80_fu_108241_p2 = (zext_ln231_61_fu_108233_p1 + add_ln231_64_reg_137995); + +assign add_ln231_81_fu_108220_p2 = (trunc_ln223_26_fu_108178_p1 + or_ln201_reg_131702); + +assign add_ln231_82_fu_115054_p2 = (trunc_ln223_27_fu_115012_p1 + or_ln201_1_reg_138881); + +assign add_ln231_83_fu_115075_p2 = (zext_ln231_63_fu_115067_p1 + add_ln231_73_reg_145150); + +assign add_ln231_84_fu_105119_p2 = (zext_ln231_65_fu_105111_p1 + add_ln231_54_reg_134424); + +assign add_ln231_85_fu_111973_p2 = (zext_ln231_67_fu_111965_p1 + add_ln231_60_reg_141587); + +assign add_ln231_86_fu_108530_p2 = (zext_ln231_69_fu_108522_p1 + add_ln231_64_reg_137995); + +assign add_ln231_87_fu_115364_p2 = (zext_ln231_71_fu_115356_p1 + add_ln231_73_reg_145150); + +assign add_ln231_88_fu_105097_p2 = (ow_0_0_0_reg_91161 + or_ln223_60_fu_105048_p2); + +assign add_ln231_89_fu_111951_p2 = (ow_0_1_0_reg_93545 + or_ln223_61_fu_111902_p2); + +assign add_ln231_8_fu_105758_p2 = (zext_ln231_9_fu_105750_p1 + add_ln231_4_reg_135347); + +assign add_ln231_90_fu_108509_p2 = (or_ln201_reg_131702 + or_ln223_62_fu_108460_p2); + +assign add_ln231_91_fu_115343_p2 = (or_ln201_1_reg_138881 + or_ln223_63_fu_115294_p2); + +assign add_ln231_9_fu_112506_p2 = (trunc_ln231_21_reg_142489 + zext_ln231_3_reg_142473); + +assign add_ln231_fu_102233_p2 = ((trunc_ln231_reg_131766) + (sext_ln231_reg_131751)); + +assign add_ln244_fu_116497_p2 = (oh2_0_0_reg_95929 + 4'd2); + +assign add_ln246_1_fu_117025_p2 = (ow3_0_1_0_reg_95977 + 4'd2); + +assign add_ln246_fu_116261_p2 = (ow3_0_0_0_reg_95941 + 4'd2); + +assign add_ln248_1_fu_116873_p2 = (ff4_0_1_0_0_reg_95989 + 4'd2); + +assign add_ln248_2_fu_116442_p2 = (ff4_0_0_1_0_reg_95965 + 4'd2); + +assign add_ln248_3_fu_117206_p2 = (ff4_0_1_1_0_reg_96001 + 4'd2); + +assign add_ln248_fu_116109_p2 = (ff4_0_0_0_0_reg_95953 + 4'd2); + +assign add_ln250_10_fu_116281_p2 = (add_ln250_4_reg_146022 + zext_ln248_2_fu_116273_p1); + +assign add_ln250_11_fu_117045_p2 = (add_ln250_6_reg_146493 + zext_ln248_3_fu_117037_p1); + +assign add_ln250_1_fu_115753_p2 = (add_ln250_reg_145998 + ff4_0_0_0_0_cast42_fu_115739_p1); + +assign add_ln250_2_fu_116488_p2 = ((mul_ln250_1_reg_146010) + (sext_ln250_1_fu_116484_p1)); + +assign add_ln250_3_fu_116517_p2 = (add_ln250_2_reg_146470 + ff4_0_1_0_0_cast36_fu_116503_p1); + +assign add_ln250_4_fu_115925_p2 = ((mul_ln250_reg_145989) + (sext_ln250_2_fu_115921_p1)); + +assign add_ln250_5_fu_116129_p2 = (add_ln250_4_reg_146022 + ff4_0_0_1_0_cast39_fu_116115_p1); + +assign add_ln250_6_fu_116689_p2 = ((mul_ln250_1_reg_146010) + (sext_ln250_3_fu_116685_p1)); + +assign add_ln250_7_fu_116893_p2 = (add_ln250_6_reg_146493 + ff4_0_1_1_0_cast33_fu_116879_p1); + +assign add_ln250_8_fu_115948_p2 = (add_ln250_reg_145998 + zext_ln248_fu_115940_p1); + +assign add_ln250_9_fu_116712_p2 = (add_ln250_2_reg_146470 + zext_ln248_1_fu_116704_p1); + +assign add_ln250_fu_115714_p2 = ((mul_ln250_reg_145989) + (sext_ln250_fu_115710_p1)); + +assign add_ln257_fu_124353_p2 = (oh5_0_0_reg_96013 + 4'd2); + +assign add_ln259_1_fu_127984_p2 = (ow6_0_1_0_reg_97533 + 4'd2); + +assign add_ln259_fu_120942_p2 = (ow6_0_0_0_reg_96025 + 4'd2); + +assign add_ln261_1_fu_126265_p2 = (ff7_0_1_0_0_reg_97545 + 4'd2); + +assign add_ln261_2_fu_122691_p2 = (ff7_0_0_1_0_reg_96785 + 4'd2); + +assign add_ln261_3_fu_129733_p2 = (ff7_0_1_1_0_reg_98293 + 4'd2); + +assign add_ln261_fu_119223_p2 = (ff7_0_0_0_0_reg_96037 + 4'd2); + +assign add_ln264_1_fu_125715_p2 = (cc8_0_1_0_0_0_reg_97557 + 3'd2); + +assign add_ln264_2_fu_122141_p2 = (cc8_0_0_1_0_0_reg_96797 + 3'd2); + +assign add_ln264_3_fu_120297_p2 = (cc8_0_0_0_1_0_reg_96421 + 3'd2); + +assign add_ln264_4_fu_129183_p2 = (cc8_0_1_1_0_0_reg_98305 + 3'd2); + +assign add_ln264_5_fu_127339_p2 = (cc8_0_1_0_1_0_reg_97929 + 3'd2); + +assign add_ln264_6_fu_123765_p2 = (cc8_0_0_1_1_0_reg_97169 + 3'd2); + +assign add_ln264_7_fu_130807_p2 = (cc8_0_1_1_1_0_reg_98677 + 3'd2); + +assign add_ln264_fu_118673_p2 = (cc8_0_0_0_0_0_reg_96049 + 3'd2); + +assign add_ln266_10_fu_122517_p2 = (fh9_0_0_1_0_1_0_reg_96989 + 32'd2); + +assign add_ln266_11_fu_120672_p2 = (fh9_0_0_0_1_1_0_reg_96609 + 32'd2); + +assign add_ln266_12_fu_129559_p2 = (fh9_0_1_1_0_1_0_reg_98497 + 32'd2); + +assign add_ln266_13_fu_127714_p2 = (fh9_0_1_0_1_1_0_reg_98117 + 32'd2); + +assign add_ln266_14_fu_124140_p2 = (fh9_0_0_1_1_1_0_reg_97357 + 32'd2); + +assign add_ln266_15_fu_131182_p2 = (fh9_0_1_1_1_1_0_reg_98865 + 32'd2); + +assign add_ln266_1_fu_125293_p2 = (fh9_0_1_0_0_0_0_reg_97569 + 32'd2); + +assign add_ln266_2_fu_121719_p2 = (fh9_0_0_1_0_0_0_reg_96809 + 32'd2); + +assign add_ln266_3_fu_119876_p2 = (fh9_0_0_0_1_0_0_reg_96433 + 32'd2); + +assign add_ln266_4_fu_128761_p2 = (fh9_0_1_1_0_0_0_reg_98317 + 32'd2); + +assign add_ln266_5_fu_126918_p2 = (fh9_0_1_0_1_0_0_reg_97941 + 32'd2); + +assign add_ln266_6_fu_123344_p2 = (fh9_0_0_1_1_0_0_reg_97181 + 32'd2); + +assign add_ln266_7_fu_130386_p2 = (fh9_0_1_1_1_0_0_reg_98689 + 32'd2); + +assign add_ln266_8_fu_119049_p2 = (fh9_0_0_0_0_1_0_reg_96241 + 32'd2); + +assign add_ln266_9_fu_126091_p2 = (fh9_0_1_0_0_1_0_reg_97749 + 32'd2); + +assign add_ln266_fu_118251_p2 = (fh9_0_0_0_0_0_0_reg_96061 + 32'd2); + +assign add_ln268_10_fu_125448_p2 = (fw10_0_1_0_0_0_1_0_reg_97665 + 32'd2); + +assign add_ln268_11_fu_121874_p2 = (fw10_0_0_1_0_0_1_0_reg_96905 + 32'd2); + +assign add_ln268_12_fu_120030_p2 = (fw10_0_0_0_1_0_1_0_reg_96527 + 32'd2); + +assign add_ln268_13_fu_125870_p2 = (fw10_0_1_0_0_1_0_0_reg_97761 + 32'd2); + +assign add_ln268_14_fu_122296_p2 = (fw10_0_0_1_0_1_0_0_reg_97001 + 32'd2); + +assign add_ln268_15_fu_120451_p2 = (fw10_0_0_0_1_1_0_0_reg_96621 + 32'd2); + +assign add_ln268_16_fu_128916_p2 = (fw10_0_1_1_0_0_1_0_reg_98413 + 32'd2); + +assign add_ln268_17_fu_127072_p2 = (fw10_0_1_0_1_0_1_0_reg_98035 + 32'd2); + +assign add_ln268_18_fu_123498_p2 = (fw10_0_0_1_1_0_1_0_reg_97275 + 32'd2); + +assign add_ln268_19_fu_129338_p2 = (fw10_0_1_1_0_1_0_0_reg_98509 + 32'd2); + +assign add_ln268_1_fu_125072_p2 = (fw10_0_1_0_0_0_0_0_reg_97581 + 32'd2); + +assign add_ln268_20_fu_127493_p2 = (fw10_0_1_0_1_1_0_0_reg_98129 + 32'd2); + +assign add_ln268_21_fu_123919_p2 = (fw10_0_0_1_1_1_0_0_reg_97369 + 32'd2); + +assign add_ln268_22_fu_130540_p2 = (fw10_0_1_1_1_0_1_0_reg_98783 + 32'd2); + +assign add_ln268_23_fu_130961_p2 = (fw10_0_1_1_1_1_0_0_reg_98877 + 32'd2); + +assign add_ln268_24_fu_119204_p2 = (fw10_0_0_0_0_1_1_0_reg_96337 + 32'd2); + +assign add_ln268_25_fu_126246_p2 = (fw10_0_1_0_0_1_1_0_reg_97845 + 32'd2); + +assign add_ln268_26_fu_122672_p2 = (fw10_0_0_1_0_1_1_0_reg_97085 + 32'd2); + +assign add_ln268_27_fu_120826_p2 = (fw10_0_0_0_1_1_1_0_reg_96703 + 32'd2); + +assign add_ln268_28_fu_129714_p2 = (fw10_0_1_1_0_1_1_0_reg_98593 + 32'd2); + +assign add_ln268_29_fu_127868_p2 = (fw10_0_1_0_1_1_1_0_reg_98211 + 32'd2); + +assign add_ln268_2_fu_121498_p2 = (fw10_0_0_1_0_0_0_0_reg_96821 + 32'd2); + +assign add_ln268_30_fu_124294_p2 = (fw10_0_0_1_1_1_1_0_reg_97451 + 32'd2); + +assign add_ln268_31_fu_131336_p2 = (fw10_0_1_1_1_1_1_0_reg_98959 + 32'd2); + +assign add_ln268_3_fu_119655_p2 = (fw10_0_0_0_1_0_0_0_reg_96445 + 32'd2); + +assign add_ln268_4_fu_128540_p2 = (fw10_0_1_1_0_0_0_0_reg_98329 + 32'd2); + +assign add_ln268_5_fu_126697_p2 = (fw10_0_1_0_1_0_0_0_reg_97953 + 32'd2); + +assign add_ln268_6_fu_123123_p2 = (fw10_0_0_1_1_0_0_0_reg_97193 + 32'd2); + +assign add_ln268_7_fu_130165_p2 = (fw10_0_1_1_1_0_0_0_reg_98701 + 32'd2); + +assign add_ln268_8_fu_118406_p2 = (fw10_0_0_0_0_0_1_0_reg_96157 + 32'd2); + +assign add_ln268_9_fu_118828_p2 = (fw10_0_0_0_0_1_0_0_reg_96253 + 32'd2); + +assign add_ln268_fu_118030_p2 = (fw10_0_0_0_0_0_0_0_reg_96073 + 32'd2); + +assign add_ln276_100_fu_129989_p2 = (or_ln266_7_fu_129971_p2 + zext_ln276_7_reg_165209); + +assign add_ln276_101_fu_129994_p2 = (add_ln276_100_fu_129989_p2 + shl_ln276_37_fu_129983_p2); + +assign add_ln276_102_fu_129756_p2 = (fw10_0_1_1_1_0_0_0_reg_98701 + add_ln276_42_reg_165220); + +assign add_ln276_103_fu_118036_p2 = (fw10_0_0_0_0_0_1_0_reg_96157 + add_ln276_47_reg_148762); + +assign add_ln276_104_fu_118240_p2 = (add_ln276_47_reg_148762 + or_ln268_8_fu_118228_p2); + +assign add_ln276_105_fu_130552_p2 = (fh9_0_1_1_1_1_0_reg_98865 + zext_ln276_15_reg_165570); + +assign add_ln276_106_fu_130557_p2 = (add_ln276_105_fu_130552_p2 + shl_ln276_38_fu_130546_p2); + +assign add_ln276_107_fu_118429_p2 = (fw10_0_0_0_0_1_0_0_reg_96253 + add_ln276_52_reg_149439); + +assign add_ln276_108_fu_118633_p2 = (add_ln276_52_reg_149439 + or_ln268_9_fu_118621_p2); + +assign add_ln276_109_fu_125078_p2 = (fw10_0_1_0_0_0_1_0_reg_97665 + add_ln276_56_reg_158603); + +assign add_ln276_110_fu_125282_p2 = (add_ln276_56_reg_158603 + or_ln268_10_fu_125270_p2); + +assign add_ln276_111_fu_121708_p2 = (add_ln276_59_reg_153663 + or_ln268_11_fu_121696_p2); + +assign add_ln276_112_fu_119865_p2 = (add_ln276_65_reg_150822 + or_ln268_12_fu_119853_p2); + +assign add_ln276_113_fu_118662_p2 = (or_ln266_8_fu_118644_p2 + zext_ln276_8_reg_148768); + +assign add_ln276_114_fu_118667_p2 = (add_ln276_113_fu_118662_p2 + shl_ln276_39_fu_118656_p2); + +assign add_ln276_115_fu_125675_p2 = (add_ln276_69_reg_159280 + or_ln268_13_fu_125663_p2); + +assign add_ln276_116_fu_122101_p2 = (add_ln276_72_reg_154340 + or_ln268_14_fu_122089_p2); + +assign add_ln276_117_fu_120257_p2 = (add_ln276_75_reg_151494 + or_ln268_15_fu_120245_p2); + +assign add_ln276_118_fu_121504_p2 = (fw10_0_0_1_0_0_1_0_reg_96905 + add_ln276_59_reg_153663); + +assign add_ln276_119_fu_128750_p2 = (add_ln276_79_reg_163504 + or_ln268_16_fu_128738_p2); + +assign add_ln276_120_fu_126907_p2 = (add_ln276_83_reg_160663 + or_ln268_17_fu_126895_p2); + +assign add_ln276_121_fu_125704_p2 = (or_ln266_9_fu_125686_p2 + zext_ln276_9_reg_158609); + +assign add_ln276_122_fu_125709_p2 = (add_ln276_121_fu_125704_p2 + shl_ln276_40_fu_125698_p2); + +assign add_ln276_123_fu_123333_p2 = (add_ln276_88_reg_155723 + or_ln268_18_fu_123321_p2); + +assign add_ln276_124_fu_122130_p2 = (or_ln266_10_fu_122112_p2 + zext_ln276_10_reg_153669); + +assign add_ln276_125_fu_122135_p2 = (add_ln276_124_fu_122130_p2 + shl_ln276_41_fu_122124_p2); + +assign add_ln276_126_fu_120286_p2 = (or_ln266_11_fu_120268_p2 + zext_ln276_11_reg_150828); + +assign add_ln276_127_fu_120291_p2 = (add_ln276_126_fu_120286_p2 + shl_ln276_42_fu_120280_p2); + +assign add_ln276_128_fu_129143_p2 = (add_ln276_91_reg_164181 + or_ln268_19_fu_129131_p2); + +assign add_ln276_129_fu_127299_p2 = (add_ln276_94_reg_161335 + or_ln268_20_fu_127287_p2); + +assign add_ln276_12_fu_124656_p2 = (add_ln276_24_fu_124651_p2 + shl_ln276_16_fu_124645_p2); + +assign add_ln276_130_fu_119661_p2 = (fw10_0_0_0_1_0_1_0_reg_96527 + add_ln276_65_reg_150822); + +assign add_ln276_131_fu_123725_p2 = (add_ln276_97_reg_156395 + or_ln268_21_fu_123713_p2); + +assign add_ln276_132_fu_125471_p2 = (fw10_0_1_0_0_1_0_0_reg_97761 + add_ln276_69_reg_159280); + +assign add_ln276_133_fu_121897_p2 = (fw10_0_0_1_0_1_0_0_reg_97001 + add_ln276_72_reg_154340); + +assign add_ln276_134_fu_130375_p2 = (add_ln276_101_reg_165564 + or_ln268_22_fu_130363_p2); + +assign add_ln276_135_fu_129172_p2 = (or_ln266_12_fu_129154_p2 + zext_ln276_12_reg_163510); + +assign add_ln276_136_fu_129177_p2 = (add_ln276_135_fu_129172_p2 + shl_ln276_43_fu_129166_p2); + +assign add_ln276_137_fu_127328_p2 = (or_ln266_13_fu_127310_p2 + zext_ln276_13_reg_160669); + +assign add_ln276_138_fu_127333_p2 = (add_ln276_137_fu_127328_p2 + shl_ln276_44_fu_127322_p2); + +assign add_ln276_139_fu_123754_p2 = (or_ln266_14_fu_123736_p2 + zext_ln276_14_reg_155729); + +assign add_ln276_140_fu_123759_p2 = (add_ln276_139_fu_123754_p2 + shl_ln276_45_fu_123748_p2); + +assign add_ln276_141_fu_130767_p2 = (add_ln276_106_reg_166236 + or_ln268_23_fu_130755_p2); + +assign add_ln276_142_fu_120053_p2 = (fw10_0_0_0_1_1_0_0_reg_96621 + add_ln276_75_reg_151494); + +assign add_ln276_143_fu_128546_p2 = (fw10_0_1_1_0_0_1_0_reg_98413 + add_ln276_79_reg_163504); + +assign add_ln276_144_fu_126703_p2 = (fw10_0_1_0_1_0_1_0_reg_98035 + add_ln276_83_reg_160663); + +assign add_ln276_145_fu_130796_p2 = (or_ln266_15_fu_130778_p2 + zext_ln276_15_reg_165570); + +assign add_ln276_146_fu_130801_p2 = (add_ln276_145_fu_130796_p2 + shl_ln276_46_fu_130790_p2); + +assign add_ln276_147_fu_119038_p2 = (add_ln276_114_reg_149788 + or_ln268_24_fu_119026_p2); + +assign add_ln276_148_fu_123129_p2 = (fw10_0_0_1_1_0_1_0_reg_97275 + add_ln276_88_reg_155723); + +assign add_ln276_149_fu_126080_p2 = (add_ln276_122_reg_159629 + or_ln268_25_fu_126068_p2); + +assign add_ln276_14_fu_117609_p2 = (fh9_0_0_0_0_0_0_reg_96061 + zext_ln276_reg_148013); + +assign add_ln276_150_fu_122506_p2 = (add_ln276_125_reg_154689 + or_ln268_26_fu_122494_p2); + +assign add_ln276_151_fu_120661_p2 = (add_ln276_127_reg_151838 + or_ln268_27_fu_120649_p2); + +assign add_ln276_152_fu_129548_p2 = (add_ln276_136_reg_164530 + or_ln268_28_fu_129536_p2); + +assign add_ln276_153_fu_127703_p2 = (add_ln276_138_reg_161679 + or_ln268_29_fu_127691_p2); + +assign add_ln276_154_fu_124129_p2 = (add_ln276_140_reg_156739 + or_ln268_30_fu_124117_p2); + +assign add_ln276_155_fu_131171_p2 = (add_ln276_146_reg_166580 + or_ln268_31_fu_131159_p2); + +assign add_ln276_156_fu_128939_p2 = (fw10_0_1_1_0_1_0_0_reg_98509 + add_ln276_91_reg_164181); + +assign add_ln276_157_fu_127095_p2 = (fw10_0_1_0_1_1_0_0_reg_98129 + add_ln276_94_reg_161335); + +assign add_ln276_158_fu_123521_p2 = (fw10_0_0_1_1_1_0_0_reg_97369 + add_ln276_97_reg_156395); + +assign add_ln276_159_fu_130171_p2 = (fw10_0_1_1_1_0_1_0_reg_98783 + add_ln276_101_reg_165564); + +assign add_ln276_160_fu_130563_p2 = (fw10_0_1_1_1_1_0_0_reg_98877 + add_ln276_106_reg_166236); + +assign add_ln276_161_fu_118834_p2 = (fw10_0_0_0_0_1_1_0_reg_96337 + add_ln276_114_reg_149788); + +assign add_ln276_162_fu_125876_p2 = (fw10_0_1_0_0_1_1_0_reg_97845 + add_ln276_122_reg_159629); + +assign add_ln276_163_fu_122302_p2 = (fw10_0_0_1_0_1_1_0_reg_97085 + add_ln276_125_reg_154689); + +assign add_ln276_164_fu_120457_p2 = (fw10_0_0_0_1_1_1_0_reg_96703 + add_ln276_127_reg_151838); + +assign add_ln276_165_fu_129344_p2 = (fw10_0_1_1_0_1_1_0_reg_98593 + add_ln276_136_reg_164530); + +assign add_ln276_166_fu_127499_p2 = (fw10_0_1_0_1_1_1_0_reg_98211 + add_ln276_138_reg_161679); + +assign add_ln276_167_fu_123925_p2 = (fw10_0_0_1_1_1_1_0_reg_97451 + add_ln276_140_reg_156739); + +assign add_ln276_168_fu_130967_p2 = (fw10_0_1_1_1_1_1_0_reg_98959 + add_ln276_146_reg_166580); + +assign add_ln276_17_fu_121082_p2 = (add_ln276_25_fu_121077_p2 + shl_ln276_17_fu_121071_p2); + +assign add_ln276_22_fu_119240_p2 = (add_ln276_26_fu_119235_p2 + shl_ln276_18_fu_119229_p2); + +assign add_ln276_24_fu_124651_p2 = (fh9_0_1_0_0_0_0_reg_97569 + zext_ln276_1_reg_157854); + +assign add_ln276_25_fu_121077_p2 = (fh9_0_0_1_0_0_0_reg_96809 + zext_ln276_2_reg_152914); + +assign add_ln276_26_fu_119235_p2 = (fh9_0_0_0_1_0_0_reg_96433 + zext_ln276_3_reg_150467); + +assign add_ln276_30_fu_128124_p2 = (add_ln276_33_fu_128119_p2 + shl_ln276_19_fu_128113_p2); + +assign add_ln276_33_fu_128119_p2 = (fh9_0_1_1_0_0_0_reg_98317 + zext_ln276_4_reg_162755); + +assign add_ln276_34_fu_126277_p2 = (fh9_0_1_0_1_0_0_reg_97941 + zext_ln276_5_reg_160308); + +assign add_ln276_35_fu_126282_p2 = (add_ln276_34_fu_126277_p2 + shl_ln276_20_fu_126271_p2); + +assign add_ln276_37_fu_122703_p2 = (fh9_0_0_1_1_0_0_reg_97181 + zext_ln276_6_reg_155368); + +assign add_ln276_38_fu_122708_p2 = (add_ln276_37_fu_122703_p2 + shl_ln276_21_fu_122697_p2); + +assign add_ln276_41_fu_129745_p2 = (fh9_0_1_1_1_0_0_reg_98689 + zext_ln276_7_reg_165209); + +assign add_ln276_42_fu_129750_p2 = (add_ln276_41_fu_129745_p2 + shl_ln276_22_fu_129739_p2); + +assign add_ln276_43_fu_117824_p2 = (add_ln276_4_reg_148413 + or_ln268_fu_117812_p2); + +assign add_ln276_46_fu_117853_p2 = (or_ln266_fu_117835_p2 + zext_ln276_reg_148013); + +assign add_ln276_47_fu_117858_p2 = (add_ln276_46_fu_117853_p2 + shl_ln276_23_fu_117847_p2); + +assign add_ln276_48_fu_124866_p2 = (add_ln276_12_reg_158254 + or_ln268_1_fu_124854_p2); + +assign add_ln276_49_fu_121292_p2 = (add_ln276_17_reg_153314 + or_ln268_2_fu_121280_p2); + +assign add_ln276_4_fu_117614_p2 = (add_ln276_14_fu_117609_p2 + shl_ln276_fu_117603_p2); + +assign add_ln276_50_fu_119450_p2 = (add_ln276_22_reg_150478 + or_ln268_3_fu_119438_p2); + +assign add_ln276_51_fu_118418_p2 = (fh9_0_0_0_0_1_0_reg_96241 + zext_ln276_8_reg_148768); + +assign add_ln276_52_fu_118423_p2 = (add_ln276_51_fu_118418_p2 + shl_ln276_24_fu_118412_p2); + +assign add_ln276_55_fu_124895_p2 = (or_ln266_1_fu_124877_p2 + zext_ln276_1_reg_157854); + +assign add_ln276_56_fu_124900_p2 = (add_ln276_55_fu_124895_p2 + shl_ln276_25_fu_124889_p2); + +assign add_ln276_58_fu_121321_p2 = (or_ln266_2_fu_121303_p2 + zext_ln276_2_reg_152914); + +assign add_ln276_59_fu_121326_p2 = (add_ln276_58_fu_121321_p2 + shl_ln276_26_fu_121315_p2); + +assign add_ln276_62_fu_128334_p2 = (add_ln276_30_reg_163155 + or_ln268_4_fu_128322_p2); + +assign add_ln276_63_fu_126492_p2 = (add_ln276_35_reg_160319 + or_ln268_5_fu_126480_p2); + +assign add_ln276_64_fu_119479_p2 = (or_ln266_3_fu_119461_p2 + zext_ln276_3_reg_150467); + +assign add_ln276_65_fu_119484_p2 = (add_ln276_64_fu_119479_p2 + shl_ln276_27_fu_119473_p2); + +assign add_ln276_67_fu_122918_p2 = (add_ln276_38_reg_155379 + or_ln268_6_fu_122906_p2); + +assign add_ln276_68_fu_125460_p2 = (fh9_0_1_0_0_1_0_reg_97749 + zext_ln276_9_reg_158609); + +assign add_ln276_69_fu_125465_p2 = (add_ln276_68_fu_125460_p2 + shl_ln276_28_fu_125454_p2); + +assign add_ln276_71_fu_121886_p2 = (fh9_0_0_1_0_1_0_reg_96989 + zext_ln276_10_reg_153669); + +assign add_ln276_72_fu_121891_p2 = (add_ln276_71_fu_121886_p2 + shl_ln276_29_fu_121880_p2); + +assign add_ln276_74_fu_120042_p2 = (fh9_0_0_0_1_1_0_reg_96609 + zext_ln276_11_reg_150828); + +assign add_ln276_75_fu_120047_p2 = (add_ln276_74_fu_120042_p2 + shl_ln276_30_fu_120036_p2); + +assign add_ln276_77_fu_128363_p2 = (or_ln266_4_fu_128345_p2 + zext_ln276_4_reg_162755); + +assign add_ln276_78_fu_117620_p2 = (fw10_0_0_0_0_0_0_0_reg_96073 + add_ln276_4_reg_148413); + +assign add_ln276_79_fu_128368_p2 = (add_ln276_77_fu_128363_p2 + shl_ln276_31_fu_128357_p2); + +assign add_ln276_81_fu_126521_p2 = (or_ln266_5_fu_126503_p2 + zext_ln276_5_reg_160308); + +assign add_ln276_82_fu_124662_p2 = (fw10_0_1_0_0_0_0_0_reg_97581 + add_ln276_12_reg_158254); + +assign add_ln276_83_fu_126526_p2 = (add_ln276_81_fu_126521_p2 + shl_ln276_32_fu_126515_p2); + +assign add_ln276_85_fu_121088_p2 = (fw10_0_0_1_0_0_0_0_reg_96821 + add_ln276_17_reg_153314); + +assign add_ln276_86_fu_129960_p2 = (add_ln276_42_reg_165220 + or_ln268_7_fu_129948_p2); + +assign add_ln276_87_fu_122947_p2 = (or_ln266_6_fu_122929_p2 + zext_ln276_6_reg_155368); + +assign add_ln276_88_fu_122952_p2 = (add_ln276_87_fu_122947_p2 + shl_ln276_33_fu_122941_p2); + +assign add_ln276_89_fu_119246_p2 = (fw10_0_0_0_1_0_0_0_reg_96445 + add_ln276_22_reg_150478); + +assign add_ln276_90_fu_128928_p2 = (fh9_0_1_1_0_1_0_reg_98497 + zext_ln276_12_reg_163510); + +assign add_ln276_91_fu_128933_p2 = (add_ln276_90_fu_128928_p2 + shl_ln276_34_fu_128922_p2); + +assign add_ln276_92_fu_128130_p2 = (fw10_0_1_1_0_0_0_0_reg_98329 + add_ln276_30_reg_163155); + +assign add_ln276_93_fu_127084_p2 = (fh9_0_1_0_1_1_0_reg_98117 + zext_ln276_13_reg_160669); + +assign add_ln276_94_fu_127089_p2 = (add_ln276_93_fu_127084_p2 + shl_ln276_35_fu_127078_p2); + +assign add_ln276_95_fu_126288_p2 = (fw10_0_1_0_1_0_0_0_reg_97953 + add_ln276_35_reg_160319); + +assign add_ln276_96_fu_123510_p2 = (fh9_0_0_1_1_1_0_reg_97357 + zext_ln276_14_reg_155729); + +assign add_ln276_97_fu_123515_p2 = (add_ln276_96_fu_123510_p2 + shl_ln276_36_fu_123504_p2); + +assign add_ln276_99_fu_122714_p2 = (fw10_0_0_1_1_0_0_0_reg_97193 + add_ln276_38_reg_155379); + +assign add_ln279_10_fu_120979_p2 = (add_ln279_4_reg_147992 + zext_ln261_5_fu_120971_p1); + +assign add_ln279_11_fu_128021_p2 = (add_ln279_7_reg_157833 + zext_ln261_7_fu_128013_p1); + +assign add_ln279_1_fu_117335_p2 = (add_ln279_reg_147596 + ff7_0_0_0_0_cast29_fu_117317_p1); + +assign add_ln279_2_fu_124344_p2 = ((mul_ln279_1_reg_147620) + (sext_ln279_1_fu_124340_p1)); + +assign add_ln279_3_fu_124377_p2 = (add_ln279_2_reg_157413 + ff7_0_1_0_0_cast13_fu_124359_p1); + +assign add_ln279_4_fu_117471_p2 = ((mul_ln279_reg_146947) + (sext_ln279_2_fu_117467_p1)); + +assign add_ln279_5_fu_120850_p2 = (add_ln279_4_reg_147992 + ff7_0_0_1_0_cast21_fu_120832_p1); + +assign add_ln279_6_fu_117511_p2 = (add_ln279_reg_147596 + zext_ln261_1_fu_117503_p1); + +assign add_ln279_7_fu_124513_p2 = ((mul_ln279_1_reg_147620) + (sext_ln279_3_fu_124509_p1)); + +assign add_ln279_8_fu_127892_p2 = (add_ln279_7_reg_157833 + ff7_0_1_1_0_cast5_fu_127874_p1); + +assign add_ln279_9_fu_124553_p2 = (add_ln279_2_reg_157413 + zext_ln261_3_fu_124545_p1); + +assign add_ln279_fu_117282_p2 = ((mul_ln279_reg_146947) + (sext_ln279_fu_117278_p1)); + +assign add_ln703_10_fu_119619_p2 = (tmp_74_reg_150984 + add_ln703_3_reg_150805); + +assign add_ln703_11_fu_129879_p2 = (tmp_80_reg_165542 + phi_ln1265_7_reg_98713); + +assign add_ln703_12_fu_128503_p2 = (tmp_90_reg_163666 + add_ln703_5_reg_163487); + +assign add_ln703_13_fu_126661_p2 = (tmp_91_reg_160825 + add_ln703_6_reg_160646); + +assign add_ln703_14_fu_123087_p2 = (tmp_93_reg_155885 + add_ln703_7_reg_155706); + +assign add_ln703_15_fu_118159_p2 = (tmp_96_reg_149255 + phi_ln1265_8_reg_96169); + +assign add_ln703_16_fu_118552_p2 = (tmp_105_reg_149766 + phi_ln1265_9_reg_96265); + +assign add_ln703_17_fu_130129_p2 = (tmp_107_reg_165726 + add_ln703_11_reg_165547); + +assign add_ln703_18_fu_125201_p2 = (tmp_110_reg_159096 + phi_ln1265_10_reg_97677); + +assign add_ln703_19_fu_121627_p2 = (tmp_112_reg_154156 + phi_ln1265_11_reg_96917); + +assign add_ln703_1_fu_124785_p2 = (tmp_7_reg_158581 + phi_ln1265_1_reg_97593); + +assign add_ln703_20_fu_119784_p2 = (tmp_113_reg_151310 + phi_ln1265_12_reg_96539); + +assign add_ln703_21_fu_125594_p2 = (tmp_116_reg_159607 + phi_ln1265_13_reg_97773); + +assign add_ln703_22_fu_122020_p2 = (tmp_117_reg_154667 + phi_ln1265_14_reg_97013); + +assign add_ln703_23_fu_120176_p2 = (tmp_118_reg_151816 + phi_ln1265_15_reg_96633); + +assign add_ln703_24_fu_118369_p2 = (tmp_119_reg_149429 + add_ln703_15_reg_149260); + +assign add_ln703_25_fu_128669_p2 = (tmp_121_reg_163997 + phi_ln1265_16_reg_98425); + +assign add_ln703_26_fu_126826_p2 = (tmp_122_reg_161151 + phi_ln1265_17_reg_98047); + +assign add_ln703_27_fu_123252_p2 = (tmp_123_reg_156211 + phi_ln1265_18_reg_97287); + +assign add_ln703_28_fu_118791_p2 = (tmp_124_reg_149949 + add_ln703_16_reg_149771); + +assign add_ln703_29_fu_129062_p2 = (tmp_125_reg_164508 + phi_ln1265_19_reg_98521); + +assign add_ln703_2_fu_121211_p2 = (tmp_8_reg_153641 + phi_ln1265_2_reg_96833); + +assign add_ln703_30_fu_127218_p2 = (tmp_126_reg_161657 + phi_ln1265_20_reg_98141); + +assign add_ln703_31_fu_125411_p2 = (tmp_127_reg_159270 + add_ln703_18_reg_159101); + +assign add_ln703_32_fu_123644_p2 = (tmp_128_reg_156717 + phi_ln1265_21_reg_97381); + +assign add_ln703_33_fu_121837_p2 = (tmp_129_reg_154330 + add_ln703_19_reg_154161); + +assign add_ln703_34_fu_119994_p2 = (tmp_130_reg_151484 + add_ln703_20_reg_151315); + +assign add_ln703_35_fu_130294_p2 = (tmp_132_reg_166052 + phi_ln1265_22_reg_98795); + +assign add_ln703_36_fu_125833_p2 = (tmp_133_reg_159790 + add_ln703_21_reg_159612); + +assign add_ln703_37_fu_122259_p2 = (tmp_134_reg_154850 + add_ln703_22_reg_154672); + +assign add_ln703_38_fu_120415_p2 = (tmp_135_reg_151999 + add_ln703_23_reg_151821); + +assign add_ln703_39_fu_130686_p2 = (tmp_136_reg_166558 + phi_ln1265_23_reg_98889); + +assign add_ln703_3_fu_119369_p2 = (tmp_9_reg_150800 + phi_ln1265_3_reg_96457); + +assign add_ln703_40_fu_128879_p2 = (tmp_137_reg_164171 + add_ln703_25_reg_164002); + +assign add_ln703_41_fu_127036_p2 = (tmp_138_reg_161325 + add_ln703_26_reg_161156); + +assign add_ln703_42_fu_123462_p2 = (tmp_140_reg_156385 + add_ln703_27_reg_156216); + +assign add_ln703_43_fu_129301_p2 = (tmp_144_reg_164691 + add_ln703_29_reg_164513); + +assign add_ln703_44_fu_127457_p2 = (tmp_145_reg_161840 + add_ln703_30_reg_161662); + +assign add_ln703_45_fu_123883_p2 = (tmp_146_reg_156900 + add_ln703_32_reg_156722); + +assign add_ln703_46_fu_118957_p2 = (tmp_147_reg_150280 + phi_ln1265_24_reg_96349); + +assign add_ln703_47_fu_130504_p2 = (tmp_148_reg_166226 + add_ln703_35_reg_166057); + +assign add_ln703_48_fu_130925_p2 = (tmp_154_reg_166741 + add_ln703_39_reg_166563); + +assign add_ln703_49_fu_125999_p2 = (tmp_155_reg_160121 + phi_ln1265_25_reg_97857); + +assign add_ln703_4_fu_117993_p2 = (tmp_10_reg_148924 + add_ln703_reg_148745); + +assign add_ln703_50_fu_122425_p2 = (tmp_156_reg_155181 + phi_ln1265_26_reg_97097); + +assign add_ln703_51_fu_120580_p2 = (tmp_157_reg_152325 + phi_ln1265_27_reg_96715); + +assign add_ln703_52_fu_119167_p2 = (tmp_159_reg_150454 + add_ln703_46_reg_150285); + +assign add_ln703_53_fu_129467_p2 = (tmp_161_reg_165022 + phi_ln1265_28_reg_98605); + +assign add_ln703_54_fu_127622_p2 = (tmp_162_reg_162166 + phi_ln1265_29_reg_98223); + +assign add_ln703_55_fu_124048_p2 = (tmp_163_reg_157226 + phi_ln1265_30_reg_97463); + +assign add_ln703_56_fu_126209_p2 = (tmp_164_reg_160295 + add_ln703_49_reg_160126); + +assign add_ln703_57_fu_122635_p2 = (tmp_165_reg_155355 + add_ln703_50_reg_155186); + +assign add_ln703_58_fu_120790_p2 = (tmp_166_reg_152499 + add_ln703_51_reg_152330); + +assign add_ln703_59_fu_131090_p2 = (tmp_167_reg_167067 + phi_ln1265_31_reg_98971); + +assign add_ln703_5_fu_128253_p2 = (tmp_65_reg_163482 + phi_ln1265_4_reg_98341); + +assign add_ln703_60_fu_129677_p2 = (tmp_168_reg_165196 + add_ln703_53_reg_165027); + +assign add_ln703_61_fu_127832_p2 = (tmp_169_reg_162340 + add_ln703_54_reg_162171); + +assign add_ln703_62_fu_124258_p2 = (tmp_170_reg_157400 + add_ln703_55_reg_157231); + +assign add_ln703_63_fu_131300_p2 = (tmp_171_reg_167241 + add_ln703_59_reg_167072); + +assign add_ln703_6_fu_126411_p2 = (tmp_66_reg_160641 + phi_ln1265_5_reg_97965); + +assign add_ln703_7_fu_122837_p2 = (tmp_67_reg_155701 + phi_ln1265_6_reg_97205); + +assign add_ln703_8_fu_125035_p2 = (tmp_72_reg_158765 + add_ln703_1_reg_158586); + +assign add_ln703_9_fu_121461_p2 = (tmp_73_reg_153825 + add_ln703_2_reg_153646); + +assign add_ln703_fu_117743_p2 = (tmp_6_reg_148740 + phi_ln1265_reg_96085); + +always @ (*) begin + ap_condition_10039 = (~(7'd0 == add_ln1116_reg_131809) & ~(7'd126 == add_ln1116_reg_131809) & ~(7'd2 == add_ln1116_reg_131809) & ~(7'd64 == add_ln1116_reg_131809) & ~(7'd4 == add_ln1116_reg_131809) & ~(7'd124 == add_ln1116_reg_131809) & ~(7'd6 == add_ln1116_reg_131809) & ~(7'd94 == add_ln1116_reg_131809) & ~(7'd8 == add_ln1116_reg_131809) & ~(7'd122 == add_ln1116_reg_131809) & ~(7'd10 == add_ln1116_reg_131809) & ~(7'd66 == add_ln1116_reg_131809) & ~(7'd12 == add_ln1116_reg_131809) & ~(7'd120 == add_ln1116_reg_131809) & ~(7'd14 == add_ln1116_reg_131809) & ~(7'd80 == add_ln1116_reg_131809) & ~(7'd16 == add_ln1116_reg_131809) & ~(7'd118 == add_ln1116_reg_131809) & ~(7'd18 == add_ln1116_reg_131809) & ~(7'd68 == add_ln1116_reg_131809) & ~(7'd20 == add_ln1116_reg_131809) & ~(7'd116 == add_ln1116_reg_131809) & ~(7'd22 == add_ln1116_reg_131809) & ~(7'd92 == add_ln1116_reg_131809) & ~(7'd24 == add_ln1116_reg_131809) & ~(7'd114 == add_ln1116_reg_131809) & ~(7'd26 == add_ln1116_reg_131809) & ~(7'd70 == add_ln1116_reg_131809) & ~(7'd28 == add_ln1116_reg_131809) & ~(7'd112 == add_ln1116_reg_131809) & ~(7'd30 == add_ln1116_reg_131809) & ~(7'd86 == add_ln1116_reg_131809) & ~(7'd32 == add_ln1116_reg_131809) & ~(7'd110 == add_ln1116_reg_131809) & ~(7'd34 == add_ln1116_reg_131809) & ~(7'd72 == add_ln1116_reg_131809) & ~(7'd36 == add_ln1116_reg_131809) & ~(7'd108 == add_ln1116_reg_131809) & ~(7'd38 == add_ln1116_reg_131809) & ~(7'd90 == add_ln1116_reg_131809) & ~(7'd40 == add_ln1116_reg_131809) & ~(7'd106 == add_ln1116_reg_131809) & ~(7'd42 == add_ln1116_reg_131809) & ~(7'd74 == add_ln1116_reg_131809) & ~(7'd44 == add_ln1116_reg_131809) & ~(7'd104 == add_ln1116_reg_131809) & ~(7'd46 == add_ln1116_reg_131809) & ~(7'd82 == add_ln1116_reg_131809) & ~(7'd48 == add_ln1116_reg_131809) & ~(7'd102 == add_ln1116_reg_131809) & ~(7'd50 == add_ln1116_reg_131809) & ~(7'd76 == add_ln1116_reg_131809) & ~(7'd52 == add_ln1116_reg_131809) & ~(7'd100 == add_ln1116_reg_131809) & ~(7'd54 == add_ln1116_reg_131809) & ~(7'd88 == add_ln1116_reg_131809) & ~(7'd56 == add_ln1116_reg_131809) & ~(7'd98 == add_ln1116_reg_131809) & ~(7'd58 == add_ln1116_reg_131809) & ~(7'd78 == add_ln1116_reg_131809) & ~(7'd60 == add_ln1116_reg_131809) & ~(7'd96 == add_ln1116_reg_131809) & ~(7'd62 == add_ln1116_reg_131809) & ~(7'd84 == add_ln1116_reg_131809)); +end + +always @ (*) begin + ap_condition_10167 = (~(7'd0 == add_ln1116_4_reg_132207) & ~(7'd126 == add_ln1116_4_reg_132207) & ~(7'd2 == add_ln1116_4_reg_132207) & ~(7'd64 == add_ln1116_4_reg_132207) & ~(7'd4 == add_ln1116_4_reg_132207) & ~(7'd124 == add_ln1116_4_reg_132207) & ~(7'd6 == add_ln1116_4_reg_132207) & ~(7'd94 == add_ln1116_4_reg_132207) & ~(7'd8 == add_ln1116_4_reg_132207) & ~(7'd122 == add_ln1116_4_reg_132207) & ~(7'd10 == add_ln1116_4_reg_132207) & ~(7'd66 == add_ln1116_4_reg_132207) & ~(7'd12 == add_ln1116_4_reg_132207) & ~(7'd120 == add_ln1116_4_reg_132207) & ~(7'd14 == add_ln1116_4_reg_132207) & ~(7'd80 == add_ln1116_4_reg_132207) & ~(7'd16 == add_ln1116_4_reg_132207) & ~(7'd118 == add_ln1116_4_reg_132207) & ~(7'd18 == add_ln1116_4_reg_132207) & ~(7'd68 == add_ln1116_4_reg_132207) & ~(7'd20 == add_ln1116_4_reg_132207) & ~(7'd116 == add_ln1116_4_reg_132207) & ~(7'd22 == add_ln1116_4_reg_132207) & ~(7'd92 == add_ln1116_4_reg_132207) & ~(7'd24 == add_ln1116_4_reg_132207) & ~(7'd114 == add_ln1116_4_reg_132207) & ~(7'd26 == add_ln1116_4_reg_132207) & ~(7'd70 == add_ln1116_4_reg_132207) & ~(7'd28 == add_ln1116_4_reg_132207) & ~(7'd112 == add_ln1116_4_reg_132207) & ~(7'd30 == add_ln1116_4_reg_132207) & ~(7'd86 == add_ln1116_4_reg_132207) & ~(7'd32 == add_ln1116_4_reg_132207) & ~(7'd110 == add_ln1116_4_reg_132207) & ~(7'd34 == add_ln1116_4_reg_132207) & ~(7'd72 == add_ln1116_4_reg_132207) & ~(7'd36 == add_ln1116_4_reg_132207) & ~(7'd108 == add_ln1116_4_reg_132207) & ~(7'd38 == add_ln1116_4_reg_132207) & ~(7'd90 == add_ln1116_4_reg_132207) & ~(7'd40 == add_ln1116_4_reg_132207) & ~(7'd106 == add_ln1116_4_reg_132207) & ~(7'd42 == add_ln1116_4_reg_132207) & ~(7'd74 == add_ln1116_4_reg_132207) & ~(7'd44 == add_ln1116_4_reg_132207) & ~(7'd104 == add_ln1116_4_reg_132207) & ~(7'd46 == add_ln1116_4_reg_132207) & ~(7'd82 == add_ln1116_4_reg_132207) & ~(7'd48 == add_ln1116_4_reg_132207) & ~(7'd102 == add_ln1116_4_reg_132207) & ~(7'd50 == add_ln1116_4_reg_132207) & ~(7'd76 == add_ln1116_4_reg_132207) & ~(7'd52 == add_ln1116_4_reg_132207) & ~(7'd100 == add_ln1116_4_reg_132207) & ~(7'd54 == add_ln1116_4_reg_132207) & ~(7'd88 == add_ln1116_4_reg_132207) & ~(7'd56 == add_ln1116_4_reg_132207) & ~(7'd98 == add_ln1116_4_reg_132207) & ~(7'd58 == add_ln1116_4_reg_132207) & ~(7'd78 == add_ln1116_4_reg_132207) & ~(7'd60 == add_ln1116_4_reg_132207) & ~(7'd96 == add_ln1116_4_reg_132207) & ~(7'd62 == add_ln1116_4_reg_132207) & ~(7'd84 == add_ln1116_4_reg_132207)); +end + +always @ (*) begin + ap_condition_10296 = (~(7'd0 == add_ln1116_7_reg_132705) & ~(7'd126 == add_ln1116_7_reg_132705) & ~(7'd2 == add_ln1116_7_reg_132705) & ~(7'd64 == add_ln1116_7_reg_132705) & ~(7'd4 == add_ln1116_7_reg_132705) & ~(7'd124 == add_ln1116_7_reg_132705) & ~(7'd6 == add_ln1116_7_reg_132705) & ~(7'd94 == add_ln1116_7_reg_132705) & ~(7'd8 == add_ln1116_7_reg_132705) & ~(7'd122 == add_ln1116_7_reg_132705) & ~(7'd10 == add_ln1116_7_reg_132705) & ~(7'd66 == add_ln1116_7_reg_132705) & ~(7'd12 == add_ln1116_7_reg_132705) & ~(7'd120 == add_ln1116_7_reg_132705) & ~(7'd14 == add_ln1116_7_reg_132705) & ~(7'd80 == add_ln1116_7_reg_132705) & ~(7'd16 == add_ln1116_7_reg_132705) & ~(7'd118 == add_ln1116_7_reg_132705) & ~(7'd18 == add_ln1116_7_reg_132705) & ~(7'd68 == add_ln1116_7_reg_132705) & ~(7'd20 == add_ln1116_7_reg_132705) & ~(7'd116 == add_ln1116_7_reg_132705) & ~(7'd22 == add_ln1116_7_reg_132705) & ~(7'd92 == add_ln1116_7_reg_132705) & ~(7'd24 == add_ln1116_7_reg_132705) & ~(7'd114 == add_ln1116_7_reg_132705) & ~(7'd26 == add_ln1116_7_reg_132705) & ~(7'd70 == add_ln1116_7_reg_132705) & ~(7'd28 == add_ln1116_7_reg_132705) & ~(7'd112 == add_ln1116_7_reg_132705) & ~(7'd30 == add_ln1116_7_reg_132705) & ~(7'd86 == add_ln1116_7_reg_132705) & ~(7'd32 == add_ln1116_7_reg_132705) & ~(7'd110 == add_ln1116_7_reg_132705) & ~(7'd34 == add_ln1116_7_reg_132705) & ~(7'd72 == add_ln1116_7_reg_132705) & ~(7'd36 == add_ln1116_7_reg_132705) & ~(7'd108 == add_ln1116_7_reg_132705) & ~(7'd38 == add_ln1116_7_reg_132705) & ~(7'd90 == add_ln1116_7_reg_132705) & ~(7'd40 == add_ln1116_7_reg_132705) & ~(7'd106 == add_ln1116_7_reg_132705) & ~(7'd42 == add_ln1116_7_reg_132705) & ~(7'd74 == add_ln1116_7_reg_132705) & ~(7'd44 == add_ln1116_7_reg_132705) & ~(7'd104 == add_ln1116_7_reg_132705) & ~(7'd46 == add_ln1116_7_reg_132705) & ~(7'd82 == add_ln1116_7_reg_132705) & ~(7'd48 == add_ln1116_7_reg_132705) & ~(7'd102 == add_ln1116_7_reg_132705) & ~(7'd50 == add_ln1116_7_reg_132705) & ~(7'd76 == add_ln1116_7_reg_132705) & ~(7'd52 == add_ln1116_7_reg_132705) & ~(7'd100 == add_ln1116_7_reg_132705) & ~(7'd54 == add_ln1116_7_reg_132705) & ~(7'd88 == add_ln1116_7_reg_132705) & ~(7'd56 == add_ln1116_7_reg_132705) & ~(7'd98 == add_ln1116_7_reg_132705) & ~(7'd58 == add_ln1116_7_reg_132705) & ~(7'd78 == add_ln1116_7_reg_132705) & ~(7'd60 == add_ln1116_7_reg_132705) & ~(7'd96 == add_ln1116_7_reg_132705) & ~(7'd62 == add_ln1116_7_reg_132705) & ~(7'd84 == add_ln1116_7_reg_132705)); +end + +always @ (*) begin + ap_condition_10425 = (~(7'd0 == add_ln1116_16_reg_133103) & ~(7'd126 == add_ln1116_16_reg_133103) & ~(7'd2 == add_ln1116_16_reg_133103) & ~(7'd64 == add_ln1116_16_reg_133103) & ~(7'd4 == add_ln1116_16_reg_133103) & ~(7'd124 == add_ln1116_16_reg_133103) & ~(7'd6 == add_ln1116_16_reg_133103) & ~(7'd94 == add_ln1116_16_reg_133103) & ~(7'd8 == add_ln1116_16_reg_133103) & ~(7'd122 == add_ln1116_16_reg_133103) & ~(7'd10 == add_ln1116_16_reg_133103) & ~(7'd66 == add_ln1116_16_reg_133103) & ~(7'd12 == add_ln1116_16_reg_133103) & ~(7'd120 == add_ln1116_16_reg_133103) & ~(7'd14 == add_ln1116_16_reg_133103) & ~(7'd80 == add_ln1116_16_reg_133103) & ~(7'd16 == add_ln1116_16_reg_133103) & ~(7'd118 == add_ln1116_16_reg_133103) & ~(7'd18 == add_ln1116_16_reg_133103) & ~(7'd68 == add_ln1116_16_reg_133103) & ~(7'd20 == add_ln1116_16_reg_133103) & ~(7'd116 == add_ln1116_16_reg_133103) & ~(7'd22 == add_ln1116_16_reg_133103) & ~(7'd92 == add_ln1116_16_reg_133103) & ~(7'd24 == add_ln1116_16_reg_133103) & ~(7'd114 == add_ln1116_16_reg_133103) & ~(7'd26 == add_ln1116_16_reg_133103) & ~(7'd70 == add_ln1116_16_reg_133103) & ~(7'd28 == add_ln1116_16_reg_133103) & ~(7'd112 == add_ln1116_16_reg_133103) & ~(7'd30 == add_ln1116_16_reg_133103) & ~(7'd86 == add_ln1116_16_reg_133103) & ~(7'd32 == add_ln1116_16_reg_133103) & ~(7'd110 == add_ln1116_16_reg_133103) & ~(7'd34 == add_ln1116_16_reg_133103) & ~(7'd72 == add_ln1116_16_reg_133103) & ~(7'd36 == add_ln1116_16_reg_133103) & ~(7'd108 == add_ln1116_16_reg_133103) & ~(7'd38 == add_ln1116_16_reg_133103) & ~(7'd90 == add_ln1116_16_reg_133103) & ~(7'd40 == add_ln1116_16_reg_133103) & ~(7'd106 == add_ln1116_16_reg_133103) & ~(7'd42 == add_ln1116_16_reg_133103) & ~(7'd74 == add_ln1116_16_reg_133103) & ~(7'd44 == add_ln1116_16_reg_133103) & ~(7'd104 == add_ln1116_16_reg_133103) & ~(7'd46 == add_ln1116_16_reg_133103) & ~(7'd82 == add_ln1116_16_reg_133103) & ~(7'd48 == add_ln1116_16_reg_133103) & ~(7'd102 == add_ln1116_16_reg_133103) & ~(7'd50 == add_ln1116_16_reg_133103) & ~(7'd76 == add_ln1116_16_reg_133103) & ~(7'd52 == add_ln1116_16_reg_133103) & ~(7'd100 == add_ln1116_16_reg_133103) & ~(7'd54 == add_ln1116_16_reg_133103) & ~(7'd88 == add_ln1116_16_reg_133103) & ~(7'd56 == add_ln1116_16_reg_133103) & ~(7'd98 == add_ln1116_16_reg_133103) & ~(7'd58 == add_ln1116_16_reg_133103) & ~(7'd78 == add_ln1116_16_reg_133103) & ~(7'd60 == add_ln1116_16_reg_133103) & ~(7'd96 == add_ln1116_16_reg_133103) & ~(7'd62 == add_ln1116_16_reg_133103) & ~(7'd84 == add_ln1116_16_reg_133103)); +end + +always @ (*) begin + ap_condition_10680 = (~(7'd95 == add_ln1116_8_reg_133570) & ~(7'd61 == add_ln1116_8_reg_133570) & ~(7'd87 == add_ln1116_8_reg_133570) & ~(7'd59 == add_ln1116_8_reg_133570) & ~(7'd97 == add_ln1116_8_reg_133570) & ~(7'd57 == add_ln1116_8_reg_133570) & ~(7'd77 == add_ln1116_8_reg_133570) & ~(7'd55 == add_ln1116_8_reg_133570) & ~(7'd99 == add_ln1116_8_reg_133570) & ~(7'd53 == add_ln1116_8_reg_133570) & ~(7'd85 == add_ln1116_8_reg_133570) & ~(7'd51 == add_ln1116_8_reg_133570) & ~(7'd101 == add_ln1116_8_reg_133570) & ~(7'd49 == add_ln1116_8_reg_133570) & ~(7'd75 == add_ln1116_8_reg_133570) & ~(7'd47 == add_ln1116_8_reg_133570) & ~(7'd103 == add_ln1116_8_reg_133570) & ~(7'd45 == add_ln1116_8_reg_133570) & ~(7'd89 == add_ln1116_8_reg_133570) & ~(7'd43 == add_ln1116_8_reg_133570) & ~(7'd105 == add_ln1116_8_reg_133570) & ~(7'd41 == add_ln1116_8_reg_133570) & ~(7'd73 == add_ln1116_8_reg_133570) & ~(7'd39 == add_ln1116_8_reg_133570) & ~(7'd107 == add_ln1116_8_reg_133570) & ~(7'd37 == add_ln1116_8_reg_133570) & ~(7'd81 == add_ln1116_8_reg_133570) & ~(7'd35 == add_ln1116_8_reg_133570) & ~(7'd109 == add_ln1116_8_reg_133570) & ~(7'd33 == add_ln1116_8_reg_133570) & ~(7'd71 == add_ln1116_8_reg_133570) & ~(7'd31 == add_ln1116_8_reg_133570) & ~(7'd111 == add_ln1116_8_reg_133570) & ~(7'd29 == add_ln1116_8_reg_133570) & ~(7'd91 == add_ln1116_8_reg_133570) & ~(7'd27 == add_ln1116_8_reg_133570) & ~(7'd113 == add_ln1116_8_reg_133570) & ~(7'd25 == add_ln1116_8_reg_133570) & ~(7'd69 == add_ln1116_8_reg_133570) & ~(7'd23 == add_ln1116_8_reg_133570) & ~(7'd115 == add_ln1116_8_reg_133570) & ~(7'd21 == add_ln1116_8_reg_133570) & ~(7'd83 == add_ln1116_8_reg_133570) & ~(7'd19 == add_ln1116_8_reg_133570) & ~(7'd117 == add_ln1116_8_reg_133570) & ~(7'd17 == add_ln1116_8_reg_133570) & ~(7'd67 == add_ln1116_8_reg_133570) & ~(7'd15 == add_ln1116_8_reg_133570) & ~(7'd119 == add_ln1116_8_reg_133570) & ~(7'd13 == add_ln1116_8_reg_133570) & ~(7'd93 == add_ln1116_8_reg_133570) & ~(7'd11 == add_ln1116_8_reg_133570) & ~(7'd121 == add_ln1116_8_reg_133570) & ~(7'd9 == add_ln1116_8_reg_133570) & ~(7'd65 == add_ln1116_8_reg_133570) & ~(7'd7 == add_ln1116_8_reg_133570) & ~(7'd123 == add_ln1116_8_reg_133570) & ~(7'd5 == add_ln1116_8_reg_133570) & ~(7'd79 == add_ln1116_8_reg_133570) & ~(7'd3 == add_ln1116_8_reg_133570) & ~(7'd125 == add_ln1116_8_reg_133570) & ~(7'd1 == add_ln1116_8_reg_133570) & ~(7'd63 == add_ln1116_8_reg_133570)); +end + +always @ (*) begin + ap_condition_10872 = (~(7'd95 == add_ln1116_17_reg_133975) & ~(7'd61 == add_ln1116_17_reg_133975) & ~(7'd87 == add_ln1116_17_reg_133975) & ~(7'd59 == add_ln1116_17_reg_133975) & ~(7'd97 == add_ln1116_17_reg_133975) & ~(7'd57 == add_ln1116_17_reg_133975) & ~(7'd77 == add_ln1116_17_reg_133975) & ~(7'd55 == add_ln1116_17_reg_133975) & ~(7'd99 == add_ln1116_17_reg_133975) & ~(7'd53 == add_ln1116_17_reg_133975) & ~(7'd85 == add_ln1116_17_reg_133975) & ~(7'd51 == add_ln1116_17_reg_133975) & ~(7'd101 == add_ln1116_17_reg_133975) & ~(7'd49 == add_ln1116_17_reg_133975) & ~(7'd75 == add_ln1116_17_reg_133975) & ~(7'd47 == add_ln1116_17_reg_133975) & ~(7'd103 == add_ln1116_17_reg_133975) & ~(7'd45 == add_ln1116_17_reg_133975) & ~(7'd89 == add_ln1116_17_reg_133975) & ~(7'd43 == add_ln1116_17_reg_133975) & ~(7'd105 == add_ln1116_17_reg_133975) & ~(7'd41 == add_ln1116_17_reg_133975) & ~(7'd73 == add_ln1116_17_reg_133975) & ~(7'd39 == add_ln1116_17_reg_133975) & ~(7'd107 == add_ln1116_17_reg_133975) & ~(7'd37 == add_ln1116_17_reg_133975) & ~(7'd81 == add_ln1116_17_reg_133975) & ~(7'd35 == add_ln1116_17_reg_133975) & ~(7'd109 == add_ln1116_17_reg_133975) & ~(7'd33 == add_ln1116_17_reg_133975) & ~(7'd71 == add_ln1116_17_reg_133975) & ~(7'd31 == add_ln1116_17_reg_133975) & ~(7'd111 == add_ln1116_17_reg_133975) & ~(7'd29 == add_ln1116_17_reg_133975) & ~(7'd91 == add_ln1116_17_reg_133975) & ~(7'd27 == add_ln1116_17_reg_133975) & ~(7'd113 == add_ln1116_17_reg_133975) & ~(7'd25 == add_ln1116_17_reg_133975) & ~(7'd69 == add_ln1116_17_reg_133975) & ~(7'd23 == add_ln1116_17_reg_133975) & ~(7'd115 == add_ln1116_17_reg_133975) & ~(7'd21 == add_ln1116_17_reg_133975) & ~(7'd83 == add_ln1116_17_reg_133975) & ~(7'd19 == add_ln1116_17_reg_133975) & ~(7'd117 == add_ln1116_17_reg_133975) & ~(7'd17 == add_ln1116_17_reg_133975) & ~(7'd67 == add_ln1116_17_reg_133975) & ~(7'd15 == add_ln1116_17_reg_133975) & ~(7'd119 == add_ln1116_17_reg_133975) & ~(7'd13 == add_ln1116_17_reg_133975) & ~(7'd93 == add_ln1116_17_reg_133975) & ~(7'd11 == add_ln1116_17_reg_133975) & ~(7'd121 == add_ln1116_17_reg_133975) & ~(7'd9 == add_ln1116_17_reg_133975) & ~(7'd65 == add_ln1116_17_reg_133975) & ~(7'd7 == add_ln1116_17_reg_133975) & ~(7'd123 == add_ln1116_17_reg_133975) & ~(7'd5 == add_ln1116_17_reg_133975) & ~(7'd79 == add_ln1116_17_reg_133975) & ~(7'd3 == add_ln1116_17_reg_133975) & ~(7'd125 == add_ln1116_17_reg_133975) & ~(7'd1 == add_ln1116_17_reg_133975) & ~(7'd63 == add_ln1116_17_reg_133975)); +end + +always @ (*) begin + ap_condition_11064 = (~(7'd95 == add_ln1116_22_reg_134445) & ~(7'd61 == add_ln1116_22_reg_134445) & ~(7'd87 == add_ln1116_22_reg_134445) & ~(7'd59 == add_ln1116_22_reg_134445) & ~(7'd97 == add_ln1116_22_reg_134445) & ~(7'd57 == add_ln1116_22_reg_134445) & ~(7'd77 == add_ln1116_22_reg_134445) & ~(7'd55 == add_ln1116_22_reg_134445) & ~(7'd99 == add_ln1116_22_reg_134445) & ~(7'd53 == add_ln1116_22_reg_134445) & ~(7'd85 == add_ln1116_22_reg_134445) & ~(7'd51 == add_ln1116_22_reg_134445) & ~(7'd101 == add_ln1116_22_reg_134445) & ~(7'd49 == add_ln1116_22_reg_134445) & ~(7'd75 == add_ln1116_22_reg_134445) & ~(7'd47 == add_ln1116_22_reg_134445) & ~(7'd103 == add_ln1116_22_reg_134445) & ~(7'd45 == add_ln1116_22_reg_134445) & ~(7'd89 == add_ln1116_22_reg_134445) & ~(7'd43 == add_ln1116_22_reg_134445) & ~(7'd105 == add_ln1116_22_reg_134445) & ~(7'd41 == add_ln1116_22_reg_134445) & ~(7'd73 == add_ln1116_22_reg_134445) & ~(7'd39 == add_ln1116_22_reg_134445) & ~(7'd107 == add_ln1116_22_reg_134445) & ~(7'd37 == add_ln1116_22_reg_134445) & ~(7'd81 == add_ln1116_22_reg_134445) & ~(7'd35 == add_ln1116_22_reg_134445) & ~(7'd109 == add_ln1116_22_reg_134445) & ~(7'd33 == add_ln1116_22_reg_134445) & ~(7'd71 == add_ln1116_22_reg_134445) & ~(7'd31 == add_ln1116_22_reg_134445) & ~(7'd111 == add_ln1116_22_reg_134445) & ~(7'd29 == add_ln1116_22_reg_134445) & ~(7'd91 == add_ln1116_22_reg_134445) & ~(7'd27 == add_ln1116_22_reg_134445) & ~(7'd113 == add_ln1116_22_reg_134445) & ~(7'd25 == add_ln1116_22_reg_134445) & ~(7'd69 == add_ln1116_22_reg_134445) & ~(7'd23 == add_ln1116_22_reg_134445) & ~(7'd115 == add_ln1116_22_reg_134445) & ~(7'd21 == add_ln1116_22_reg_134445) & ~(7'd83 == add_ln1116_22_reg_134445) & ~(7'd19 == add_ln1116_22_reg_134445) & ~(7'd117 == add_ln1116_22_reg_134445) & ~(7'd17 == add_ln1116_22_reg_134445) & ~(7'd67 == add_ln1116_22_reg_134445) & ~(7'd15 == add_ln1116_22_reg_134445) & ~(7'd119 == add_ln1116_22_reg_134445) & ~(7'd13 == add_ln1116_22_reg_134445) & ~(7'd93 == add_ln1116_22_reg_134445) & ~(7'd11 == add_ln1116_22_reg_134445) & ~(7'd121 == add_ln1116_22_reg_134445) & ~(7'd9 == add_ln1116_22_reg_134445) & ~(7'd65 == add_ln1116_22_reg_134445) & ~(7'd7 == add_ln1116_22_reg_134445) & ~(7'd123 == add_ln1116_22_reg_134445) & ~(7'd5 == add_ln1116_22_reg_134445) & ~(7'd79 == add_ln1116_22_reg_134445) & ~(7'd3 == add_ln1116_22_reg_134445) & ~(7'd125 == add_ln1116_22_reg_134445) & ~(7'd1 == add_ln1116_22_reg_134445) & ~(7'd63 == add_ln1116_22_reg_134445)); +end + +always @ (*) begin + ap_condition_11256 = (~(7'd95 == add_ln1116_28_reg_134850) & ~(7'd61 == add_ln1116_28_reg_134850) & ~(7'd87 == add_ln1116_28_reg_134850) & ~(7'd59 == add_ln1116_28_reg_134850) & ~(7'd97 == add_ln1116_28_reg_134850) & ~(7'd57 == add_ln1116_28_reg_134850) & ~(7'd77 == add_ln1116_28_reg_134850) & ~(7'd55 == add_ln1116_28_reg_134850) & ~(7'd99 == add_ln1116_28_reg_134850) & ~(7'd53 == add_ln1116_28_reg_134850) & ~(7'd85 == add_ln1116_28_reg_134850) & ~(7'd51 == add_ln1116_28_reg_134850) & ~(7'd101 == add_ln1116_28_reg_134850) & ~(7'd49 == add_ln1116_28_reg_134850) & ~(7'd75 == add_ln1116_28_reg_134850) & ~(7'd47 == add_ln1116_28_reg_134850) & ~(7'd103 == add_ln1116_28_reg_134850) & ~(7'd45 == add_ln1116_28_reg_134850) & ~(7'd89 == add_ln1116_28_reg_134850) & ~(7'd43 == add_ln1116_28_reg_134850) & ~(7'd105 == add_ln1116_28_reg_134850) & ~(7'd41 == add_ln1116_28_reg_134850) & ~(7'd73 == add_ln1116_28_reg_134850) & ~(7'd39 == add_ln1116_28_reg_134850) & ~(7'd107 == add_ln1116_28_reg_134850) & ~(7'd37 == add_ln1116_28_reg_134850) & ~(7'd81 == add_ln1116_28_reg_134850) & ~(7'd35 == add_ln1116_28_reg_134850) & ~(7'd109 == add_ln1116_28_reg_134850) & ~(7'd33 == add_ln1116_28_reg_134850) & ~(7'd71 == add_ln1116_28_reg_134850) & ~(7'd31 == add_ln1116_28_reg_134850) & ~(7'd111 == add_ln1116_28_reg_134850) & ~(7'd29 == add_ln1116_28_reg_134850) & ~(7'd91 == add_ln1116_28_reg_134850) & ~(7'd27 == add_ln1116_28_reg_134850) & ~(7'd113 == add_ln1116_28_reg_134850) & ~(7'd25 == add_ln1116_28_reg_134850) & ~(7'd69 == add_ln1116_28_reg_134850) & ~(7'd23 == add_ln1116_28_reg_134850) & ~(7'd115 == add_ln1116_28_reg_134850) & ~(7'd21 == add_ln1116_28_reg_134850) & ~(7'd83 == add_ln1116_28_reg_134850) & ~(7'd19 == add_ln1116_28_reg_134850) & ~(7'd117 == add_ln1116_28_reg_134850) & ~(7'd17 == add_ln1116_28_reg_134850) & ~(7'd67 == add_ln1116_28_reg_134850) & ~(7'd15 == add_ln1116_28_reg_134850) & ~(7'd119 == add_ln1116_28_reg_134850) & ~(7'd13 == add_ln1116_28_reg_134850) & ~(7'd93 == add_ln1116_28_reg_134850) & ~(7'd11 == add_ln1116_28_reg_134850) & ~(7'd121 == add_ln1116_28_reg_134850) & ~(7'd9 == add_ln1116_28_reg_134850) & ~(7'd65 == add_ln1116_28_reg_134850) & ~(7'd7 == add_ln1116_28_reg_134850) & ~(7'd123 == add_ln1116_28_reg_134850) & ~(7'd5 == add_ln1116_28_reg_134850) & ~(7'd79 == add_ln1116_28_reg_134850) & ~(7'd3 == add_ln1116_28_reg_134850) & ~(7'd125 == add_ln1116_28_reg_134850) & ~(7'd1 == add_ln1116_28_reg_134850) & ~(7'd63 == add_ln1116_28_reg_134850)); +end + +always @ (*) begin + ap_condition_11385 = (~(7'd0 == add_ln1116_2_reg_135368) & ~(7'd126 == add_ln1116_2_reg_135368) & ~(7'd2 == add_ln1116_2_reg_135368) & ~(7'd64 == add_ln1116_2_reg_135368) & ~(7'd4 == add_ln1116_2_reg_135368) & ~(7'd124 == add_ln1116_2_reg_135368) & ~(7'd6 == add_ln1116_2_reg_135368) & ~(7'd94 == add_ln1116_2_reg_135368) & ~(7'd8 == add_ln1116_2_reg_135368) & ~(7'd122 == add_ln1116_2_reg_135368) & ~(7'd10 == add_ln1116_2_reg_135368) & ~(7'd66 == add_ln1116_2_reg_135368) & ~(7'd12 == add_ln1116_2_reg_135368) & ~(7'd120 == add_ln1116_2_reg_135368) & ~(7'd14 == add_ln1116_2_reg_135368) & ~(7'd80 == add_ln1116_2_reg_135368) & ~(7'd16 == add_ln1116_2_reg_135368) & ~(7'd118 == add_ln1116_2_reg_135368) & ~(7'd18 == add_ln1116_2_reg_135368) & ~(7'd68 == add_ln1116_2_reg_135368) & ~(7'd20 == add_ln1116_2_reg_135368) & ~(7'd116 == add_ln1116_2_reg_135368) & ~(7'd22 == add_ln1116_2_reg_135368) & ~(7'd92 == add_ln1116_2_reg_135368) & ~(7'd24 == add_ln1116_2_reg_135368) & ~(7'd114 == add_ln1116_2_reg_135368) & ~(7'd26 == add_ln1116_2_reg_135368) & ~(7'd70 == add_ln1116_2_reg_135368) & ~(7'd28 == add_ln1116_2_reg_135368) & ~(7'd112 == add_ln1116_2_reg_135368) & ~(7'd30 == add_ln1116_2_reg_135368) & ~(7'd86 == add_ln1116_2_reg_135368) & ~(7'd32 == add_ln1116_2_reg_135368) & ~(7'd110 == add_ln1116_2_reg_135368) & ~(7'd34 == add_ln1116_2_reg_135368) & ~(7'd72 == add_ln1116_2_reg_135368) & ~(7'd36 == add_ln1116_2_reg_135368) & ~(7'd108 == add_ln1116_2_reg_135368) & ~(7'd38 == add_ln1116_2_reg_135368) & ~(7'd90 == add_ln1116_2_reg_135368) & ~(7'd40 == add_ln1116_2_reg_135368) & ~(7'd106 == add_ln1116_2_reg_135368) & ~(7'd42 == add_ln1116_2_reg_135368) & ~(7'd74 == add_ln1116_2_reg_135368) & ~(7'd44 == add_ln1116_2_reg_135368) & ~(7'd104 == add_ln1116_2_reg_135368) & ~(7'd46 == add_ln1116_2_reg_135368) & ~(7'd82 == add_ln1116_2_reg_135368) & ~(7'd48 == add_ln1116_2_reg_135368) & ~(7'd102 == add_ln1116_2_reg_135368) & ~(7'd50 == add_ln1116_2_reg_135368) & ~(7'd76 == add_ln1116_2_reg_135368) & ~(7'd52 == add_ln1116_2_reg_135368) & ~(7'd100 == add_ln1116_2_reg_135368) & ~(7'd54 == add_ln1116_2_reg_135368) & ~(7'd88 == add_ln1116_2_reg_135368) & ~(7'd56 == add_ln1116_2_reg_135368) & ~(7'd98 == add_ln1116_2_reg_135368) & ~(7'd58 == add_ln1116_2_reg_135368) & ~(7'd78 == add_ln1116_2_reg_135368) & ~(7'd60 == add_ln1116_2_reg_135368) & ~(7'd96 == add_ln1116_2_reg_135368) & ~(7'd62 == add_ln1116_2_reg_135368) & ~(7'd84 == add_ln1116_2_reg_135368)); +end + +always @ (*) begin + ap_condition_11514 = (~(7'd0 == add_ln1116_6_reg_135778) & ~(7'd126 == add_ln1116_6_reg_135778) & ~(7'd2 == add_ln1116_6_reg_135778) & ~(7'd64 == add_ln1116_6_reg_135778) & ~(7'd4 == add_ln1116_6_reg_135778) & ~(7'd124 == add_ln1116_6_reg_135778) & ~(7'd6 == add_ln1116_6_reg_135778) & ~(7'd94 == add_ln1116_6_reg_135778) & ~(7'd8 == add_ln1116_6_reg_135778) & ~(7'd122 == add_ln1116_6_reg_135778) & ~(7'd10 == add_ln1116_6_reg_135778) & ~(7'd66 == add_ln1116_6_reg_135778) & ~(7'd12 == add_ln1116_6_reg_135778) & ~(7'd120 == add_ln1116_6_reg_135778) & ~(7'd14 == add_ln1116_6_reg_135778) & ~(7'd80 == add_ln1116_6_reg_135778) & ~(7'd16 == add_ln1116_6_reg_135778) & ~(7'd118 == add_ln1116_6_reg_135778) & ~(7'd18 == add_ln1116_6_reg_135778) & ~(7'd68 == add_ln1116_6_reg_135778) & ~(7'd20 == add_ln1116_6_reg_135778) & ~(7'd116 == add_ln1116_6_reg_135778) & ~(7'd22 == add_ln1116_6_reg_135778) & ~(7'd92 == add_ln1116_6_reg_135778) & ~(7'd24 == add_ln1116_6_reg_135778) & ~(7'd114 == add_ln1116_6_reg_135778) & ~(7'd26 == add_ln1116_6_reg_135778) & ~(7'd70 == add_ln1116_6_reg_135778) & ~(7'd28 == add_ln1116_6_reg_135778) & ~(7'd112 == add_ln1116_6_reg_135778) & ~(7'd30 == add_ln1116_6_reg_135778) & ~(7'd86 == add_ln1116_6_reg_135778) & ~(7'd32 == add_ln1116_6_reg_135778) & ~(7'd110 == add_ln1116_6_reg_135778) & ~(7'd34 == add_ln1116_6_reg_135778) & ~(7'd72 == add_ln1116_6_reg_135778) & ~(7'd36 == add_ln1116_6_reg_135778) & ~(7'd108 == add_ln1116_6_reg_135778) & ~(7'd38 == add_ln1116_6_reg_135778) & ~(7'd90 == add_ln1116_6_reg_135778) & ~(7'd40 == add_ln1116_6_reg_135778) & ~(7'd106 == add_ln1116_6_reg_135778) & ~(7'd42 == add_ln1116_6_reg_135778) & ~(7'd74 == add_ln1116_6_reg_135778) & ~(7'd44 == add_ln1116_6_reg_135778) & ~(7'd104 == add_ln1116_6_reg_135778) & ~(7'd46 == add_ln1116_6_reg_135778) & ~(7'd82 == add_ln1116_6_reg_135778) & ~(7'd48 == add_ln1116_6_reg_135778) & ~(7'd102 == add_ln1116_6_reg_135778) & ~(7'd50 == add_ln1116_6_reg_135778) & ~(7'd76 == add_ln1116_6_reg_135778) & ~(7'd52 == add_ln1116_6_reg_135778) & ~(7'd100 == add_ln1116_6_reg_135778) & ~(7'd54 == add_ln1116_6_reg_135778) & ~(7'd88 == add_ln1116_6_reg_135778) & ~(7'd56 == add_ln1116_6_reg_135778) & ~(7'd98 == add_ln1116_6_reg_135778) & ~(7'd58 == add_ln1116_6_reg_135778) & ~(7'd78 == add_ln1116_6_reg_135778) & ~(7'd60 == add_ln1116_6_reg_135778) & ~(7'd96 == add_ln1116_6_reg_135778) & ~(7'd62 == add_ln1116_6_reg_135778) & ~(7'd84 == add_ln1116_6_reg_135778)); +end + +always @ (*) begin + ap_condition_11643 = (~(7'd0 == add_ln1116_11_reg_136276) & ~(7'd126 == add_ln1116_11_reg_136276) & ~(7'd2 == add_ln1116_11_reg_136276) & ~(7'd64 == add_ln1116_11_reg_136276) & ~(7'd4 == add_ln1116_11_reg_136276) & ~(7'd124 == add_ln1116_11_reg_136276) & ~(7'd6 == add_ln1116_11_reg_136276) & ~(7'd94 == add_ln1116_11_reg_136276) & ~(7'd8 == add_ln1116_11_reg_136276) & ~(7'd122 == add_ln1116_11_reg_136276) & ~(7'd10 == add_ln1116_11_reg_136276) & ~(7'd66 == add_ln1116_11_reg_136276) & ~(7'd12 == add_ln1116_11_reg_136276) & ~(7'd120 == add_ln1116_11_reg_136276) & ~(7'd14 == add_ln1116_11_reg_136276) & ~(7'd80 == add_ln1116_11_reg_136276) & ~(7'd16 == add_ln1116_11_reg_136276) & ~(7'd118 == add_ln1116_11_reg_136276) & ~(7'd18 == add_ln1116_11_reg_136276) & ~(7'd68 == add_ln1116_11_reg_136276) & ~(7'd20 == add_ln1116_11_reg_136276) & ~(7'd116 == add_ln1116_11_reg_136276) & ~(7'd22 == add_ln1116_11_reg_136276) & ~(7'd92 == add_ln1116_11_reg_136276) & ~(7'd24 == add_ln1116_11_reg_136276) & ~(7'd114 == add_ln1116_11_reg_136276) & ~(7'd26 == add_ln1116_11_reg_136276) & ~(7'd70 == add_ln1116_11_reg_136276) & ~(7'd28 == add_ln1116_11_reg_136276) & ~(7'd112 == add_ln1116_11_reg_136276) & ~(7'd30 == add_ln1116_11_reg_136276) & ~(7'd86 == add_ln1116_11_reg_136276) & ~(7'd32 == add_ln1116_11_reg_136276) & ~(7'd110 == add_ln1116_11_reg_136276) & ~(7'd34 == add_ln1116_11_reg_136276) & ~(7'd72 == add_ln1116_11_reg_136276) & ~(7'd36 == add_ln1116_11_reg_136276) & ~(7'd108 == add_ln1116_11_reg_136276) & ~(7'd38 == add_ln1116_11_reg_136276) & ~(7'd90 == add_ln1116_11_reg_136276) & ~(7'd40 == add_ln1116_11_reg_136276) & ~(7'd106 == add_ln1116_11_reg_136276) & ~(7'd42 == add_ln1116_11_reg_136276) & ~(7'd74 == add_ln1116_11_reg_136276) & ~(7'd44 == add_ln1116_11_reg_136276) & ~(7'd104 == add_ln1116_11_reg_136276) & ~(7'd46 == add_ln1116_11_reg_136276) & ~(7'd82 == add_ln1116_11_reg_136276) & ~(7'd48 == add_ln1116_11_reg_136276) & ~(7'd102 == add_ln1116_11_reg_136276) & ~(7'd50 == add_ln1116_11_reg_136276) & ~(7'd76 == add_ln1116_11_reg_136276) & ~(7'd52 == add_ln1116_11_reg_136276) & ~(7'd100 == add_ln1116_11_reg_136276) & ~(7'd54 == add_ln1116_11_reg_136276) & ~(7'd88 == add_ln1116_11_reg_136276) & ~(7'd56 == add_ln1116_11_reg_136276) & ~(7'd98 == add_ln1116_11_reg_136276) & ~(7'd58 == add_ln1116_11_reg_136276) & ~(7'd78 == add_ln1116_11_reg_136276) & ~(7'd60 == add_ln1116_11_reg_136276) & ~(7'd96 == add_ln1116_11_reg_136276) & ~(7'd62 == add_ln1116_11_reg_136276) & ~(7'd84 == add_ln1116_11_reg_136276)); +end + +always @ (*) begin + ap_condition_11772 = (~(7'd0 == add_ln1116_19_reg_136674) & ~(7'd126 == add_ln1116_19_reg_136674) & ~(7'd2 == add_ln1116_19_reg_136674) & ~(7'd64 == add_ln1116_19_reg_136674) & ~(7'd4 == add_ln1116_19_reg_136674) & ~(7'd124 == add_ln1116_19_reg_136674) & ~(7'd6 == add_ln1116_19_reg_136674) & ~(7'd94 == add_ln1116_19_reg_136674) & ~(7'd8 == add_ln1116_19_reg_136674) & ~(7'd122 == add_ln1116_19_reg_136674) & ~(7'd10 == add_ln1116_19_reg_136674) & ~(7'd66 == add_ln1116_19_reg_136674) & ~(7'd12 == add_ln1116_19_reg_136674) & ~(7'd120 == add_ln1116_19_reg_136674) & ~(7'd14 == add_ln1116_19_reg_136674) & ~(7'd80 == add_ln1116_19_reg_136674) & ~(7'd16 == add_ln1116_19_reg_136674) & ~(7'd118 == add_ln1116_19_reg_136674) & ~(7'd18 == add_ln1116_19_reg_136674) & ~(7'd68 == add_ln1116_19_reg_136674) & ~(7'd20 == add_ln1116_19_reg_136674) & ~(7'd116 == add_ln1116_19_reg_136674) & ~(7'd22 == add_ln1116_19_reg_136674) & ~(7'd92 == add_ln1116_19_reg_136674) & ~(7'd24 == add_ln1116_19_reg_136674) & ~(7'd114 == add_ln1116_19_reg_136674) & ~(7'd26 == add_ln1116_19_reg_136674) & ~(7'd70 == add_ln1116_19_reg_136674) & ~(7'd28 == add_ln1116_19_reg_136674) & ~(7'd112 == add_ln1116_19_reg_136674) & ~(7'd30 == add_ln1116_19_reg_136674) & ~(7'd86 == add_ln1116_19_reg_136674) & ~(7'd32 == add_ln1116_19_reg_136674) & ~(7'd110 == add_ln1116_19_reg_136674) & ~(7'd34 == add_ln1116_19_reg_136674) & ~(7'd72 == add_ln1116_19_reg_136674) & ~(7'd36 == add_ln1116_19_reg_136674) & ~(7'd108 == add_ln1116_19_reg_136674) & ~(7'd38 == add_ln1116_19_reg_136674) & ~(7'd90 == add_ln1116_19_reg_136674) & ~(7'd40 == add_ln1116_19_reg_136674) & ~(7'd106 == add_ln1116_19_reg_136674) & ~(7'd42 == add_ln1116_19_reg_136674) & ~(7'd74 == add_ln1116_19_reg_136674) & ~(7'd44 == add_ln1116_19_reg_136674) & ~(7'd104 == add_ln1116_19_reg_136674) & ~(7'd46 == add_ln1116_19_reg_136674) & ~(7'd82 == add_ln1116_19_reg_136674) & ~(7'd48 == add_ln1116_19_reg_136674) & ~(7'd102 == add_ln1116_19_reg_136674) & ~(7'd50 == add_ln1116_19_reg_136674) & ~(7'd76 == add_ln1116_19_reg_136674) & ~(7'd52 == add_ln1116_19_reg_136674) & ~(7'd100 == add_ln1116_19_reg_136674) & ~(7'd54 == add_ln1116_19_reg_136674) & ~(7'd88 == add_ln1116_19_reg_136674) & ~(7'd56 == add_ln1116_19_reg_136674) & ~(7'd98 == add_ln1116_19_reg_136674) & ~(7'd58 == add_ln1116_19_reg_136674) & ~(7'd78 == add_ln1116_19_reg_136674) & ~(7'd60 == add_ln1116_19_reg_136674) & ~(7'd96 == add_ln1116_19_reg_136674) & ~(7'd62 == add_ln1116_19_reg_136674) & ~(7'd84 == add_ln1116_19_reg_136674)); +end + +always @ (*) begin + ap_condition_11964 = (~(7'd95 == add_ln1116_13_reg_137141) & ~(7'd61 == add_ln1116_13_reg_137141) & ~(7'd87 == add_ln1116_13_reg_137141) & ~(7'd59 == add_ln1116_13_reg_137141) & ~(7'd97 == add_ln1116_13_reg_137141) & ~(7'd57 == add_ln1116_13_reg_137141) & ~(7'd77 == add_ln1116_13_reg_137141) & ~(7'd55 == add_ln1116_13_reg_137141) & ~(7'd99 == add_ln1116_13_reg_137141) & ~(7'd53 == add_ln1116_13_reg_137141) & ~(7'd85 == add_ln1116_13_reg_137141) & ~(7'd51 == add_ln1116_13_reg_137141) & ~(7'd101 == add_ln1116_13_reg_137141) & ~(7'd49 == add_ln1116_13_reg_137141) & ~(7'd75 == add_ln1116_13_reg_137141) & ~(7'd47 == add_ln1116_13_reg_137141) & ~(7'd103 == add_ln1116_13_reg_137141) & ~(7'd45 == add_ln1116_13_reg_137141) & ~(7'd89 == add_ln1116_13_reg_137141) & ~(7'd43 == add_ln1116_13_reg_137141) & ~(7'd105 == add_ln1116_13_reg_137141) & ~(7'd41 == add_ln1116_13_reg_137141) & ~(7'd73 == add_ln1116_13_reg_137141) & ~(7'd39 == add_ln1116_13_reg_137141) & ~(7'd107 == add_ln1116_13_reg_137141) & ~(7'd37 == add_ln1116_13_reg_137141) & ~(7'd81 == add_ln1116_13_reg_137141) & ~(7'd35 == add_ln1116_13_reg_137141) & ~(7'd109 == add_ln1116_13_reg_137141) & ~(7'd33 == add_ln1116_13_reg_137141) & ~(7'd71 == add_ln1116_13_reg_137141) & ~(7'd31 == add_ln1116_13_reg_137141) & ~(7'd111 == add_ln1116_13_reg_137141) & ~(7'd29 == add_ln1116_13_reg_137141) & ~(7'd91 == add_ln1116_13_reg_137141) & ~(7'd27 == add_ln1116_13_reg_137141) & ~(7'd113 == add_ln1116_13_reg_137141) & ~(7'd25 == add_ln1116_13_reg_137141) & ~(7'd69 == add_ln1116_13_reg_137141) & ~(7'd23 == add_ln1116_13_reg_137141) & ~(7'd115 == add_ln1116_13_reg_137141) & ~(7'd21 == add_ln1116_13_reg_137141) & ~(7'd83 == add_ln1116_13_reg_137141) & ~(7'd19 == add_ln1116_13_reg_137141) & ~(7'd117 == add_ln1116_13_reg_137141) & ~(7'd17 == add_ln1116_13_reg_137141) & ~(7'd67 == add_ln1116_13_reg_137141) & ~(7'd15 == add_ln1116_13_reg_137141) & ~(7'd119 == add_ln1116_13_reg_137141) & ~(7'd13 == add_ln1116_13_reg_137141) & ~(7'd93 == add_ln1116_13_reg_137141) & ~(7'd11 == add_ln1116_13_reg_137141) & ~(7'd121 == add_ln1116_13_reg_137141) & ~(7'd9 == add_ln1116_13_reg_137141) & ~(7'd65 == add_ln1116_13_reg_137141) & ~(7'd7 == add_ln1116_13_reg_137141) & ~(7'd123 == add_ln1116_13_reg_137141) & ~(7'd5 == add_ln1116_13_reg_137141) & ~(7'd79 == add_ln1116_13_reg_137141) & ~(7'd3 == add_ln1116_13_reg_137141) & ~(7'd125 == add_ln1116_13_reg_137141) & ~(7'd1 == add_ln1116_13_reg_137141) & ~(7'd63 == add_ln1116_13_reg_137141)); +end + +always @ (*) begin + ap_condition_12156 = (~(7'd95 == add_ln1116_21_reg_137546) & ~(7'd61 == add_ln1116_21_reg_137546) & ~(7'd87 == add_ln1116_21_reg_137546) & ~(7'd59 == add_ln1116_21_reg_137546) & ~(7'd97 == add_ln1116_21_reg_137546) & ~(7'd57 == add_ln1116_21_reg_137546) & ~(7'd77 == add_ln1116_21_reg_137546) & ~(7'd55 == add_ln1116_21_reg_137546) & ~(7'd99 == add_ln1116_21_reg_137546) & ~(7'd53 == add_ln1116_21_reg_137546) & ~(7'd85 == add_ln1116_21_reg_137546) & ~(7'd51 == add_ln1116_21_reg_137546) & ~(7'd101 == add_ln1116_21_reg_137546) & ~(7'd49 == add_ln1116_21_reg_137546) & ~(7'd75 == add_ln1116_21_reg_137546) & ~(7'd47 == add_ln1116_21_reg_137546) & ~(7'd103 == add_ln1116_21_reg_137546) & ~(7'd45 == add_ln1116_21_reg_137546) & ~(7'd89 == add_ln1116_21_reg_137546) & ~(7'd43 == add_ln1116_21_reg_137546) & ~(7'd105 == add_ln1116_21_reg_137546) & ~(7'd41 == add_ln1116_21_reg_137546) & ~(7'd73 == add_ln1116_21_reg_137546) & ~(7'd39 == add_ln1116_21_reg_137546) & ~(7'd107 == add_ln1116_21_reg_137546) & ~(7'd37 == add_ln1116_21_reg_137546) & ~(7'd81 == add_ln1116_21_reg_137546) & ~(7'd35 == add_ln1116_21_reg_137546) & ~(7'd109 == add_ln1116_21_reg_137546) & ~(7'd33 == add_ln1116_21_reg_137546) & ~(7'd71 == add_ln1116_21_reg_137546) & ~(7'd31 == add_ln1116_21_reg_137546) & ~(7'd111 == add_ln1116_21_reg_137546) & ~(7'd29 == add_ln1116_21_reg_137546) & ~(7'd91 == add_ln1116_21_reg_137546) & ~(7'd27 == add_ln1116_21_reg_137546) & ~(7'd113 == add_ln1116_21_reg_137546) & ~(7'd25 == add_ln1116_21_reg_137546) & ~(7'd69 == add_ln1116_21_reg_137546) & ~(7'd23 == add_ln1116_21_reg_137546) & ~(7'd115 == add_ln1116_21_reg_137546) & ~(7'd21 == add_ln1116_21_reg_137546) & ~(7'd83 == add_ln1116_21_reg_137546) & ~(7'd19 == add_ln1116_21_reg_137546) & ~(7'd117 == add_ln1116_21_reg_137546) & ~(7'd17 == add_ln1116_21_reg_137546) & ~(7'd67 == add_ln1116_21_reg_137546) & ~(7'd15 == add_ln1116_21_reg_137546) & ~(7'd119 == add_ln1116_21_reg_137546) & ~(7'd13 == add_ln1116_21_reg_137546) & ~(7'd93 == add_ln1116_21_reg_137546) & ~(7'd11 == add_ln1116_21_reg_137546) & ~(7'd121 == add_ln1116_21_reg_137546) & ~(7'd9 == add_ln1116_21_reg_137546) & ~(7'd65 == add_ln1116_21_reg_137546) & ~(7'd7 == add_ln1116_21_reg_137546) & ~(7'd123 == add_ln1116_21_reg_137546) & ~(7'd5 == add_ln1116_21_reg_137546) & ~(7'd79 == add_ln1116_21_reg_137546) & ~(7'd3 == add_ln1116_21_reg_137546) & ~(7'd125 == add_ln1116_21_reg_137546) & ~(7'd1 == add_ln1116_21_reg_137546) & ~(7'd63 == add_ln1116_21_reg_137546)); +end + +always @ (*) begin + ap_condition_12348 = (~(7'd95 == add_ln1116_26_reg_138016) & ~(7'd61 == add_ln1116_26_reg_138016) & ~(7'd87 == add_ln1116_26_reg_138016) & ~(7'd59 == add_ln1116_26_reg_138016) & ~(7'd97 == add_ln1116_26_reg_138016) & ~(7'd57 == add_ln1116_26_reg_138016) & ~(7'd77 == add_ln1116_26_reg_138016) & ~(7'd55 == add_ln1116_26_reg_138016) & ~(7'd99 == add_ln1116_26_reg_138016) & ~(7'd53 == add_ln1116_26_reg_138016) & ~(7'd85 == add_ln1116_26_reg_138016) & ~(7'd51 == add_ln1116_26_reg_138016) & ~(7'd101 == add_ln1116_26_reg_138016) & ~(7'd49 == add_ln1116_26_reg_138016) & ~(7'd75 == add_ln1116_26_reg_138016) & ~(7'd47 == add_ln1116_26_reg_138016) & ~(7'd103 == add_ln1116_26_reg_138016) & ~(7'd45 == add_ln1116_26_reg_138016) & ~(7'd89 == add_ln1116_26_reg_138016) & ~(7'd43 == add_ln1116_26_reg_138016) & ~(7'd105 == add_ln1116_26_reg_138016) & ~(7'd41 == add_ln1116_26_reg_138016) & ~(7'd73 == add_ln1116_26_reg_138016) & ~(7'd39 == add_ln1116_26_reg_138016) & ~(7'd107 == add_ln1116_26_reg_138016) & ~(7'd37 == add_ln1116_26_reg_138016) & ~(7'd81 == add_ln1116_26_reg_138016) & ~(7'd35 == add_ln1116_26_reg_138016) & ~(7'd109 == add_ln1116_26_reg_138016) & ~(7'd33 == add_ln1116_26_reg_138016) & ~(7'd71 == add_ln1116_26_reg_138016) & ~(7'd31 == add_ln1116_26_reg_138016) & ~(7'd111 == add_ln1116_26_reg_138016) & ~(7'd29 == add_ln1116_26_reg_138016) & ~(7'd91 == add_ln1116_26_reg_138016) & ~(7'd27 == add_ln1116_26_reg_138016) & ~(7'd113 == add_ln1116_26_reg_138016) & ~(7'd25 == add_ln1116_26_reg_138016) & ~(7'd69 == add_ln1116_26_reg_138016) & ~(7'd23 == add_ln1116_26_reg_138016) & ~(7'd115 == add_ln1116_26_reg_138016) & ~(7'd21 == add_ln1116_26_reg_138016) & ~(7'd83 == add_ln1116_26_reg_138016) & ~(7'd19 == add_ln1116_26_reg_138016) & ~(7'd117 == add_ln1116_26_reg_138016) & ~(7'd17 == add_ln1116_26_reg_138016) & ~(7'd67 == add_ln1116_26_reg_138016) & ~(7'd15 == add_ln1116_26_reg_138016) & ~(7'd119 == add_ln1116_26_reg_138016) & ~(7'd13 == add_ln1116_26_reg_138016) & ~(7'd93 == add_ln1116_26_reg_138016) & ~(7'd11 == add_ln1116_26_reg_138016) & ~(7'd121 == add_ln1116_26_reg_138016) & ~(7'd9 == add_ln1116_26_reg_138016) & ~(7'd65 == add_ln1116_26_reg_138016) & ~(7'd7 == add_ln1116_26_reg_138016) & ~(7'd123 == add_ln1116_26_reg_138016) & ~(7'd5 == add_ln1116_26_reg_138016) & ~(7'd79 == add_ln1116_26_reg_138016) & ~(7'd3 == add_ln1116_26_reg_138016) & ~(7'd125 == add_ln1116_26_reg_138016) & ~(7'd1 == add_ln1116_26_reg_138016) & ~(7'd63 == add_ln1116_26_reg_138016)); +end + +always @ (*) begin + ap_condition_12540 = (~(7'd95 == add_ln1116_30_reg_138421) & ~(7'd61 == add_ln1116_30_reg_138421) & ~(7'd87 == add_ln1116_30_reg_138421) & ~(7'd59 == add_ln1116_30_reg_138421) & ~(7'd97 == add_ln1116_30_reg_138421) & ~(7'd57 == add_ln1116_30_reg_138421) & ~(7'd77 == add_ln1116_30_reg_138421) & ~(7'd55 == add_ln1116_30_reg_138421) & ~(7'd99 == add_ln1116_30_reg_138421) & ~(7'd53 == add_ln1116_30_reg_138421) & ~(7'd85 == add_ln1116_30_reg_138421) & ~(7'd51 == add_ln1116_30_reg_138421) & ~(7'd101 == add_ln1116_30_reg_138421) & ~(7'd49 == add_ln1116_30_reg_138421) & ~(7'd75 == add_ln1116_30_reg_138421) & ~(7'd47 == add_ln1116_30_reg_138421) & ~(7'd103 == add_ln1116_30_reg_138421) & ~(7'd45 == add_ln1116_30_reg_138421) & ~(7'd89 == add_ln1116_30_reg_138421) & ~(7'd43 == add_ln1116_30_reg_138421) & ~(7'd105 == add_ln1116_30_reg_138421) & ~(7'd41 == add_ln1116_30_reg_138421) & ~(7'd73 == add_ln1116_30_reg_138421) & ~(7'd39 == add_ln1116_30_reg_138421) & ~(7'd107 == add_ln1116_30_reg_138421) & ~(7'd37 == add_ln1116_30_reg_138421) & ~(7'd81 == add_ln1116_30_reg_138421) & ~(7'd35 == add_ln1116_30_reg_138421) & ~(7'd109 == add_ln1116_30_reg_138421) & ~(7'd33 == add_ln1116_30_reg_138421) & ~(7'd71 == add_ln1116_30_reg_138421) & ~(7'd31 == add_ln1116_30_reg_138421) & ~(7'd111 == add_ln1116_30_reg_138421) & ~(7'd29 == add_ln1116_30_reg_138421) & ~(7'd91 == add_ln1116_30_reg_138421) & ~(7'd27 == add_ln1116_30_reg_138421) & ~(7'd113 == add_ln1116_30_reg_138421) & ~(7'd25 == add_ln1116_30_reg_138421) & ~(7'd69 == add_ln1116_30_reg_138421) & ~(7'd23 == add_ln1116_30_reg_138421) & ~(7'd115 == add_ln1116_30_reg_138421) & ~(7'd21 == add_ln1116_30_reg_138421) & ~(7'd83 == add_ln1116_30_reg_138421) & ~(7'd19 == add_ln1116_30_reg_138421) & ~(7'd117 == add_ln1116_30_reg_138421) & ~(7'd17 == add_ln1116_30_reg_138421) & ~(7'd67 == add_ln1116_30_reg_138421) & ~(7'd15 == add_ln1116_30_reg_138421) & ~(7'd119 == add_ln1116_30_reg_138421) & ~(7'd13 == add_ln1116_30_reg_138421) & ~(7'd93 == add_ln1116_30_reg_138421) & ~(7'd11 == add_ln1116_30_reg_138421) & ~(7'd121 == add_ln1116_30_reg_138421) & ~(7'd9 == add_ln1116_30_reg_138421) & ~(7'd65 == add_ln1116_30_reg_138421) & ~(7'd7 == add_ln1116_30_reg_138421) & ~(7'd123 == add_ln1116_30_reg_138421) & ~(7'd5 == add_ln1116_30_reg_138421) & ~(7'd79 == add_ln1116_30_reg_138421) & ~(7'd3 == add_ln1116_30_reg_138421) & ~(7'd125 == add_ln1116_30_reg_138421) & ~(7'd1 == add_ln1116_30_reg_138421) & ~(7'd63 == add_ln1116_30_reg_138421)); +end + +always @ (*) begin + ap_condition_12669 = (~(7'd0 == add_ln1116_1_reg_138989) & ~(7'd126 == add_ln1116_1_reg_138989) & ~(7'd2 == add_ln1116_1_reg_138989) & ~(7'd64 == add_ln1116_1_reg_138989) & ~(7'd4 == add_ln1116_1_reg_138989) & ~(7'd124 == add_ln1116_1_reg_138989) & ~(7'd6 == add_ln1116_1_reg_138989) & ~(7'd94 == add_ln1116_1_reg_138989) & ~(7'd8 == add_ln1116_1_reg_138989) & ~(7'd122 == add_ln1116_1_reg_138989) & ~(7'd10 == add_ln1116_1_reg_138989) & ~(7'd66 == add_ln1116_1_reg_138989) & ~(7'd12 == add_ln1116_1_reg_138989) & ~(7'd120 == add_ln1116_1_reg_138989) & ~(7'd14 == add_ln1116_1_reg_138989) & ~(7'd80 == add_ln1116_1_reg_138989) & ~(7'd16 == add_ln1116_1_reg_138989) & ~(7'd118 == add_ln1116_1_reg_138989) & ~(7'd18 == add_ln1116_1_reg_138989) & ~(7'd68 == add_ln1116_1_reg_138989) & ~(7'd20 == add_ln1116_1_reg_138989) & ~(7'd116 == add_ln1116_1_reg_138989) & ~(7'd22 == add_ln1116_1_reg_138989) & ~(7'd92 == add_ln1116_1_reg_138989) & ~(7'd24 == add_ln1116_1_reg_138989) & ~(7'd114 == add_ln1116_1_reg_138989) & ~(7'd26 == add_ln1116_1_reg_138989) & ~(7'd70 == add_ln1116_1_reg_138989) & ~(7'd28 == add_ln1116_1_reg_138989) & ~(7'd112 == add_ln1116_1_reg_138989) & ~(7'd30 == add_ln1116_1_reg_138989) & ~(7'd86 == add_ln1116_1_reg_138989) & ~(7'd32 == add_ln1116_1_reg_138989) & ~(7'd110 == add_ln1116_1_reg_138989) & ~(7'd34 == add_ln1116_1_reg_138989) & ~(7'd72 == add_ln1116_1_reg_138989) & ~(7'd36 == add_ln1116_1_reg_138989) & ~(7'd108 == add_ln1116_1_reg_138989) & ~(7'd38 == add_ln1116_1_reg_138989) & ~(7'd90 == add_ln1116_1_reg_138989) & ~(7'd40 == add_ln1116_1_reg_138989) & ~(7'd106 == add_ln1116_1_reg_138989) & ~(7'd42 == add_ln1116_1_reg_138989) & ~(7'd74 == add_ln1116_1_reg_138989) & ~(7'd44 == add_ln1116_1_reg_138989) & ~(7'd104 == add_ln1116_1_reg_138989) & ~(7'd46 == add_ln1116_1_reg_138989) & ~(7'd82 == add_ln1116_1_reg_138989) & ~(7'd48 == add_ln1116_1_reg_138989) & ~(7'd102 == add_ln1116_1_reg_138989) & ~(7'd50 == add_ln1116_1_reg_138989) & ~(7'd76 == add_ln1116_1_reg_138989) & ~(7'd52 == add_ln1116_1_reg_138989) & ~(7'd100 == add_ln1116_1_reg_138989) & ~(7'd54 == add_ln1116_1_reg_138989) & ~(7'd88 == add_ln1116_1_reg_138989) & ~(7'd56 == add_ln1116_1_reg_138989) & ~(7'd98 == add_ln1116_1_reg_138989) & ~(7'd58 == add_ln1116_1_reg_138989) & ~(7'd78 == add_ln1116_1_reg_138989) & ~(7'd60 == add_ln1116_1_reg_138989) & ~(7'd96 == add_ln1116_1_reg_138989) & ~(7'd62 == add_ln1116_1_reg_138989) & ~(7'd84 == add_ln1116_1_reg_138989)); +end + +always @ (*) begin + ap_condition_12798 = (~(7'd0 == add_ln1116_5_reg_139399) & ~(7'd126 == add_ln1116_5_reg_139399) & ~(7'd2 == add_ln1116_5_reg_139399) & ~(7'd64 == add_ln1116_5_reg_139399) & ~(7'd4 == add_ln1116_5_reg_139399) & ~(7'd124 == add_ln1116_5_reg_139399) & ~(7'd6 == add_ln1116_5_reg_139399) & ~(7'd94 == add_ln1116_5_reg_139399) & ~(7'd8 == add_ln1116_5_reg_139399) & ~(7'd122 == add_ln1116_5_reg_139399) & ~(7'd10 == add_ln1116_5_reg_139399) & ~(7'd66 == add_ln1116_5_reg_139399) & ~(7'd12 == add_ln1116_5_reg_139399) & ~(7'd120 == add_ln1116_5_reg_139399) & ~(7'd14 == add_ln1116_5_reg_139399) & ~(7'd80 == add_ln1116_5_reg_139399) & ~(7'd16 == add_ln1116_5_reg_139399) & ~(7'd118 == add_ln1116_5_reg_139399) & ~(7'd18 == add_ln1116_5_reg_139399) & ~(7'd68 == add_ln1116_5_reg_139399) & ~(7'd20 == add_ln1116_5_reg_139399) & ~(7'd116 == add_ln1116_5_reg_139399) & ~(7'd22 == add_ln1116_5_reg_139399) & ~(7'd92 == add_ln1116_5_reg_139399) & ~(7'd24 == add_ln1116_5_reg_139399) & ~(7'd114 == add_ln1116_5_reg_139399) & ~(7'd26 == add_ln1116_5_reg_139399) & ~(7'd70 == add_ln1116_5_reg_139399) & ~(7'd28 == add_ln1116_5_reg_139399) & ~(7'd112 == add_ln1116_5_reg_139399) & ~(7'd30 == add_ln1116_5_reg_139399) & ~(7'd86 == add_ln1116_5_reg_139399) & ~(7'd32 == add_ln1116_5_reg_139399) & ~(7'd110 == add_ln1116_5_reg_139399) & ~(7'd34 == add_ln1116_5_reg_139399) & ~(7'd72 == add_ln1116_5_reg_139399) & ~(7'd36 == add_ln1116_5_reg_139399) & ~(7'd108 == add_ln1116_5_reg_139399) & ~(7'd38 == add_ln1116_5_reg_139399) & ~(7'd90 == add_ln1116_5_reg_139399) & ~(7'd40 == add_ln1116_5_reg_139399) & ~(7'd106 == add_ln1116_5_reg_139399) & ~(7'd42 == add_ln1116_5_reg_139399) & ~(7'd74 == add_ln1116_5_reg_139399) & ~(7'd44 == add_ln1116_5_reg_139399) & ~(7'd104 == add_ln1116_5_reg_139399) & ~(7'd46 == add_ln1116_5_reg_139399) & ~(7'd82 == add_ln1116_5_reg_139399) & ~(7'd48 == add_ln1116_5_reg_139399) & ~(7'd102 == add_ln1116_5_reg_139399) & ~(7'd50 == add_ln1116_5_reg_139399) & ~(7'd76 == add_ln1116_5_reg_139399) & ~(7'd52 == add_ln1116_5_reg_139399) & ~(7'd100 == add_ln1116_5_reg_139399) & ~(7'd54 == add_ln1116_5_reg_139399) & ~(7'd88 == add_ln1116_5_reg_139399) & ~(7'd56 == add_ln1116_5_reg_139399) & ~(7'd98 == add_ln1116_5_reg_139399) & ~(7'd58 == add_ln1116_5_reg_139399) & ~(7'd78 == add_ln1116_5_reg_139399) & ~(7'd60 == add_ln1116_5_reg_139399) & ~(7'd96 == add_ln1116_5_reg_139399) & ~(7'd62 == add_ln1116_5_reg_139399) & ~(7'd84 == add_ln1116_5_reg_139399)); +end + +always @ (*) begin + ap_condition_12927 = (~(7'd0 == add_ln1116_10_reg_139883) & ~(7'd126 == add_ln1116_10_reg_139883) & ~(7'd2 == add_ln1116_10_reg_139883) & ~(7'd64 == add_ln1116_10_reg_139883) & ~(7'd4 == add_ln1116_10_reg_139883) & ~(7'd124 == add_ln1116_10_reg_139883) & ~(7'd6 == add_ln1116_10_reg_139883) & ~(7'd94 == add_ln1116_10_reg_139883) & ~(7'd8 == add_ln1116_10_reg_139883) & ~(7'd122 == add_ln1116_10_reg_139883) & ~(7'd10 == add_ln1116_10_reg_139883) & ~(7'd66 == add_ln1116_10_reg_139883) & ~(7'd12 == add_ln1116_10_reg_139883) & ~(7'd120 == add_ln1116_10_reg_139883) & ~(7'd14 == add_ln1116_10_reg_139883) & ~(7'd80 == add_ln1116_10_reg_139883) & ~(7'd16 == add_ln1116_10_reg_139883) & ~(7'd118 == add_ln1116_10_reg_139883) & ~(7'd18 == add_ln1116_10_reg_139883) & ~(7'd68 == add_ln1116_10_reg_139883) & ~(7'd20 == add_ln1116_10_reg_139883) & ~(7'd116 == add_ln1116_10_reg_139883) & ~(7'd22 == add_ln1116_10_reg_139883) & ~(7'd92 == add_ln1116_10_reg_139883) & ~(7'd24 == add_ln1116_10_reg_139883) & ~(7'd114 == add_ln1116_10_reg_139883) & ~(7'd26 == add_ln1116_10_reg_139883) & ~(7'd70 == add_ln1116_10_reg_139883) & ~(7'd28 == add_ln1116_10_reg_139883) & ~(7'd112 == add_ln1116_10_reg_139883) & ~(7'd30 == add_ln1116_10_reg_139883) & ~(7'd86 == add_ln1116_10_reg_139883) & ~(7'd32 == add_ln1116_10_reg_139883) & ~(7'd110 == add_ln1116_10_reg_139883) & ~(7'd34 == add_ln1116_10_reg_139883) & ~(7'd72 == add_ln1116_10_reg_139883) & ~(7'd36 == add_ln1116_10_reg_139883) & ~(7'd108 == add_ln1116_10_reg_139883) & ~(7'd38 == add_ln1116_10_reg_139883) & ~(7'd90 == add_ln1116_10_reg_139883) & ~(7'd40 == add_ln1116_10_reg_139883) & ~(7'd106 == add_ln1116_10_reg_139883) & ~(7'd42 == add_ln1116_10_reg_139883) & ~(7'd74 == add_ln1116_10_reg_139883) & ~(7'd44 == add_ln1116_10_reg_139883) & ~(7'd104 == add_ln1116_10_reg_139883) & ~(7'd46 == add_ln1116_10_reg_139883) & ~(7'd82 == add_ln1116_10_reg_139883) & ~(7'd48 == add_ln1116_10_reg_139883) & ~(7'd102 == add_ln1116_10_reg_139883) & ~(7'd50 == add_ln1116_10_reg_139883) & ~(7'd76 == add_ln1116_10_reg_139883) & ~(7'd52 == add_ln1116_10_reg_139883) & ~(7'd100 == add_ln1116_10_reg_139883) & ~(7'd54 == add_ln1116_10_reg_139883) & ~(7'd88 == add_ln1116_10_reg_139883) & ~(7'd56 == add_ln1116_10_reg_139883) & ~(7'd98 == add_ln1116_10_reg_139883) & ~(7'd58 == add_ln1116_10_reg_139883) & ~(7'd78 == add_ln1116_10_reg_139883) & ~(7'd60 == add_ln1116_10_reg_139883) & ~(7'd96 == add_ln1116_10_reg_139883) & ~(7'd62 == add_ln1116_10_reg_139883) & ~(7'd84 == add_ln1116_10_reg_139883)); +end + +always @ (*) begin + ap_condition_13056 = (~(7'd0 == add_ln1116_18_reg_140281) & ~(7'd126 == add_ln1116_18_reg_140281) & ~(7'd2 == add_ln1116_18_reg_140281) & ~(7'd64 == add_ln1116_18_reg_140281) & ~(7'd4 == add_ln1116_18_reg_140281) & ~(7'd124 == add_ln1116_18_reg_140281) & ~(7'd6 == add_ln1116_18_reg_140281) & ~(7'd94 == add_ln1116_18_reg_140281) & ~(7'd8 == add_ln1116_18_reg_140281) & ~(7'd122 == add_ln1116_18_reg_140281) & ~(7'd10 == add_ln1116_18_reg_140281) & ~(7'd66 == add_ln1116_18_reg_140281) & ~(7'd12 == add_ln1116_18_reg_140281) & ~(7'd120 == add_ln1116_18_reg_140281) & ~(7'd14 == add_ln1116_18_reg_140281) & ~(7'd80 == add_ln1116_18_reg_140281) & ~(7'd16 == add_ln1116_18_reg_140281) & ~(7'd118 == add_ln1116_18_reg_140281) & ~(7'd18 == add_ln1116_18_reg_140281) & ~(7'd68 == add_ln1116_18_reg_140281) & ~(7'd20 == add_ln1116_18_reg_140281) & ~(7'd116 == add_ln1116_18_reg_140281) & ~(7'd22 == add_ln1116_18_reg_140281) & ~(7'd92 == add_ln1116_18_reg_140281) & ~(7'd24 == add_ln1116_18_reg_140281) & ~(7'd114 == add_ln1116_18_reg_140281) & ~(7'd26 == add_ln1116_18_reg_140281) & ~(7'd70 == add_ln1116_18_reg_140281) & ~(7'd28 == add_ln1116_18_reg_140281) & ~(7'd112 == add_ln1116_18_reg_140281) & ~(7'd30 == add_ln1116_18_reg_140281) & ~(7'd86 == add_ln1116_18_reg_140281) & ~(7'd32 == add_ln1116_18_reg_140281) & ~(7'd110 == add_ln1116_18_reg_140281) & ~(7'd34 == add_ln1116_18_reg_140281) & ~(7'd72 == add_ln1116_18_reg_140281) & ~(7'd36 == add_ln1116_18_reg_140281) & ~(7'd108 == add_ln1116_18_reg_140281) & ~(7'd38 == add_ln1116_18_reg_140281) & ~(7'd90 == add_ln1116_18_reg_140281) & ~(7'd40 == add_ln1116_18_reg_140281) & ~(7'd106 == add_ln1116_18_reg_140281) & ~(7'd42 == add_ln1116_18_reg_140281) & ~(7'd74 == add_ln1116_18_reg_140281) & ~(7'd44 == add_ln1116_18_reg_140281) & ~(7'd104 == add_ln1116_18_reg_140281) & ~(7'd46 == add_ln1116_18_reg_140281) & ~(7'd82 == add_ln1116_18_reg_140281) & ~(7'd48 == add_ln1116_18_reg_140281) & ~(7'd102 == add_ln1116_18_reg_140281) & ~(7'd50 == add_ln1116_18_reg_140281) & ~(7'd76 == add_ln1116_18_reg_140281) & ~(7'd52 == add_ln1116_18_reg_140281) & ~(7'd100 == add_ln1116_18_reg_140281) & ~(7'd54 == add_ln1116_18_reg_140281) & ~(7'd88 == add_ln1116_18_reg_140281) & ~(7'd56 == add_ln1116_18_reg_140281) & ~(7'd98 == add_ln1116_18_reg_140281) & ~(7'd58 == add_ln1116_18_reg_140281) & ~(7'd78 == add_ln1116_18_reg_140281) & ~(7'd60 == add_ln1116_18_reg_140281) & ~(7'd96 == add_ln1116_18_reg_140281) & ~(7'd62 == add_ln1116_18_reg_140281) & ~(7'd84 == add_ln1116_18_reg_140281)); +end + +always @ (*) begin + ap_condition_13248 = (~(7'd95 == add_ln1116_12_reg_140743) & ~(7'd61 == add_ln1116_12_reg_140743) & ~(7'd87 == add_ln1116_12_reg_140743) & ~(7'd59 == add_ln1116_12_reg_140743) & ~(7'd97 == add_ln1116_12_reg_140743) & ~(7'd57 == add_ln1116_12_reg_140743) & ~(7'd77 == add_ln1116_12_reg_140743) & ~(7'd55 == add_ln1116_12_reg_140743) & ~(7'd99 == add_ln1116_12_reg_140743) & ~(7'd53 == add_ln1116_12_reg_140743) & ~(7'd85 == add_ln1116_12_reg_140743) & ~(7'd51 == add_ln1116_12_reg_140743) & ~(7'd101 == add_ln1116_12_reg_140743) & ~(7'd49 == add_ln1116_12_reg_140743) & ~(7'd75 == add_ln1116_12_reg_140743) & ~(7'd47 == add_ln1116_12_reg_140743) & ~(7'd103 == add_ln1116_12_reg_140743) & ~(7'd45 == add_ln1116_12_reg_140743) & ~(7'd89 == add_ln1116_12_reg_140743) & ~(7'd43 == add_ln1116_12_reg_140743) & ~(7'd105 == add_ln1116_12_reg_140743) & ~(7'd41 == add_ln1116_12_reg_140743) & ~(7'd73 == add_ln1116_12_reg_140743) & ~(7'd39 == add_ln1116_12_reg_140743) & ~(7'd107 == add_ln1116_12_reg_140743) & ~(7'd37 == add_ln1116_12_reg_140743) & ~(7'd81 == add_ln1116_12_reg_140743) & ~(7'd35 == add_ln1116_12_reg_140743) & ~(7'd109 == add_ln1116_12_reg_140743) & ~(7'd33 == add_ln1116_12_reg_140743) & ~(7'd71 == add_ln1116_12_reg_140743) & ~(7'd31 == add_ln1116_12_reg_140743) & ~(7'd111 == add_ln1116_12_reg_140743) & ~(7'd29 == add_ln1116_12_reg_140743) & ~(7'd91 == add_ln1116_12_reg_140743) & ~(7'd27 == add_ln1116_12_reg_140743) & ~(7'd113 == add_ln1116_12_reg_140743) & ~(7'd25 == add_ln1116_12_reg_140743) & ~(7'd69 == add_ln1116_12_reg_140743) & ~(7'd23 == add_ln1116_12_reg_140743) & ~(7'd115 == add_ln1116_12_reg_140743) & ~(7'd21 == add_ln1116_12_reg_140743) & ~(7'd83 == add_ln1116_12_reg_140743) & ~(7'd19 == add_ln1116_12_reg_140743) & ~(7'd117 == add_ln1116_12_reg_140743) & ~(7'd17 == add_ln1116_12_reg_140743) & ~(7'd67 == add_ln1116_12_reg_140743) & ~(7'd15 == add_ln1116_12_reg_140743) & ~(7'd119 == add_ln1116_12_reg_140743) & ~(7'd13 == add_ln1116_12_reg_140743) & ~(7'd93 == add_ln1116_12_reg_140743) & ~(7'd11 == add_ln1116_12_reg_140743) & ~(7'd121 == add_ln1116_12_reg_140743) & ~(7'd9 == add_ln1116_12_reg_140743) & ~(7'd65 == add_ln1116_12_reg_140743) & ~(7'd7 == add_ln1116_12_reg_140743) & ~(7'd123 == add_ln1116_12_reg_140743) & ~(7'd5 == add_ln1116_12_reg_140743) & ~(7'd79 == add_ln1116_12_reg_140743) & ~(7'd3 == add_ln1116_12_reg_140743) & ~(7'd125 == add_ln1116_12_reg_140743) & ~(7'd1 == add_ln1116_12_reg_140743) & ~(7'd63 == add_ln1116_12_reg_140743)); +end + +always @ (*) begin + ap_condition_13440 = (~(7'd95 == add_ln1116_20_reg_141148) & ~(7'd61 == add_ln1116_20_reg_141148) & ~(7'd87 == add_ln1116_20_reg_141148) & ~(7'd59 == add_ln1116_20_reg_141148) & ~(7'd97 == add_ln1116_20_reg_141148) & ~(7'd57 == add_ln1116_20_reg_141148) & ~(7'd77 == add_ln1116_20_reg_141148) & ~(7'd55 == add_ln1116_20_reg_141148) & ~(7'd99 == add_ln1116_20_reg_141148) & ~(7'd53 == add_ln1116_20_reg_141148) & ~(7'd85 == add_ln1116_20_reg_141148) & ~(7'd51 == add_ln1116_20_reg_141148) & ~(7'd101 == add_ln1116_20_reg_141148) & ~(7'd49 == add_ln1116_20_reg_141148) & ~(7'd75 == add_ln1116_20_reg_141148) & ~(7'd47 == add_ln1116_20_reg_141148) & ~(7'd103 == add_ln1116_20_reg_141148) & ~(7'd45 == add_ln1116_20_reg_141148) & ~(7'd89 == add_ln1116_20_reg_141148) & ~(7'd43 == add_ln1116_20_reg_141148) & ~(7'd105 == add_ln1116_20_reg_141148) & ~(7'd41 == add_ln1116_20_reg_141148) & ~(7'd73 == add_ln1116_20_reg_141148) & ~(7'd39 == add_ln1116_20_reg_141148) & ~(7'd107 == add_ln1116_20_reg_141148) & ~(7'd37 == add_ln1116_20_reg_141148) & ~(7'd81 == add_ln1116_20_reg_141148) & ~(7'd35 == add_ln1116_20_reg_141148) & ~(7'd109 == add_ln1116_20_reg_141148) & ~(7'd33 == add_ln1116_20_reg_141148) & ~(7'd71 == add_ln1116_20_reg_141148) & ~(7'd31 == add_ln1116_20_reg_141148) & ~(7'd111 == add_ln1116_20_reg_141148) & ~(7'd29 == add_ln1116_20_reg_141148) & ~(7'd91 == add_ln1116_20_reg_141148) & ~(7'd27 == add_ln1116_20_reg_141148) & ~(7'd113 == add_ln1116_20_reg_141148) & ~(7'd25 == add_ln1116_20_reg_141148) & ~(7'd69 == add_ln1116_20_reg_141148) & ~(7'd23 == add_ln1116_20_reg_141148) & ~(7'd115 == add_ln1116_20_reg_141148) & ~(7'd21 == add_ln1116_20_reg_141148) & ~(7'd83 == add_ln1116_20_reg_141148) & ~(7'd19 == add_ln1116_20_reg_141148) & ~(7'd117 == add_ln1116_20_reg_141148) & ~(7'd17 == add_ln1116_20_reg_141148) & ~(7'd67 == add_ln1116_20_reg_141148) & ~(7'd15 == add_ln1116_20_reg_141148) & ~(7'd119 == add_ln1116_20_reg_141148) & ~(7'd13 == add_ln1116_20_reg_141148) & ~(7'd93 == add_ln1116_20_reg_141148) & ~(7'd11 == add_ln1116_20_reg_141148) & ~(7'd121 == add_ln1116_20_reg_141148) & ~(7'd9 == add_ln1116_20_reg_141148) & ~(7'd65 == add_ln1116_20_reg_141148) & ~(7'd7 == add_ln1116_20_reg_141148) & ~(7'd123 == add_ln1116_20_reg_141148) & ~(7'd5 == add_ln1116_20_reg_141148) & ~(7'd79 == add_ln1116_20_reg_141148) & ~(7'd3 == add_ln1116_20_reg_141148) & ~(7'd125 == add_ln1116_20_reg_141148) & ~(7'd1 == add_ln1116_20_reg_141148) & ~(7'd63 == add_ln1116_20_reg_141148)); +end + +always @ (*) begin + ap_condition_13632 = (~(7'd95 == add_ln1116_25_reg_141608) & ~(7'd61 == add_ln1116_25_reg_141608) & ~(7'd87 == add_ln1116_25_reg_141608) & ~(7'd59 == add_ln1116_25_reg_141608) & ~(7'd97 == add_ln1116_25_reg_141608) & ~(7'd57 == add_ln1116_25_reg_141608) & ~(7'd77 == add_ln1116_25_reg_141608) & ~(7'd55 == add_ln1116_25_reg_141608) & ~(7'd99 == add_ln1116_25_reg_141608) & ~(7'd53 == add_ln1116_25_reg_141608) & ~(7'd85 == add_ln1116_25_reg_141608) & ~(7'd51 == add_ln1116_25_reg_141608) & ~(7'd101 == add_ln1116_25_reg_141608) & ~(7'd49 == add_ln1116_25_reg_141608) & ~(7'd75 == add_ln1116_25_reg_141608) & ~(7'd47 == add_ln1116_25_reg_141608) & ~(7'd103 == add_ln1116_25_reg_141608) & ~(7'd45 == add_ln1116_25_reg_141608) & ~(7'd89 == add_ln1116_25_reg_141608) & ~(7'd43 == add_ln1116_25_reg_141608) & ~(7'd105 == add_ln1116_25_reg_141608) & ~(7'd41 == add_ln1116_25_reg_141608) & ~(7'd73 == add_ln1116_25_reg_141608) & ~(7'd39 == add_ln1116_25_reg_141608) & ~(7'd107 == add_ln1116_25_reg_141608) & ~(7'd37 == add_ln1116_25_reg_141608) & ~(7'd81 == add_ln1116_25_reg_141608) & ~(7'd35 == add_ln1116_25_reg_141608) & ~(7'd109 == add_ln1116_25_reg_141608) & ~(7'd33 == add_ln1116_25_reg_141608) & ~(7'd71 == add_ln1116_25_reg_141608) & ~(7'd31 == add_ln1116_25_reg_141608) & ~(7'd111 == add_ln1116_25_reg_141608) & ~(7'd29 == add_ln1116_25_reg_141608) & ~(7'd91 == add_ln1116_25_reg_141608) & ~(7'd27 == add_ln1116_25_reg_141608) & ~(7'd113 == add_ln1116_25_reg_141608) & ~(7'd25 == add_ln1116_25_reg_141608) & ~(7'd69 == add_ln1116_25_reg_141608) & ~(7'd23 == add_ln1116_25_reg_141608) & ~(7'd115 == add_ln1116_25_reg_141608) & ~(7'd21 == add_ln1116_25_reg_141608) & ~(7'd83 == add_ln1116_25_reg_141608) & ~(7'd19 == add_ln1116_25_reg_141608) & ~(7'd117 == add_ln1116_25_reg_141608) & ~(7'd17 == add_ln1116_25_reg_141608) & ~(7'd67 == add_ln1116_25_reg_141608) & ~(7'd15 == add_ln1116_25_reg_141608) & ~(7'd119 == add_ln1116_25_reg_141608) & ~(7'd13 == add_ln1116_25_reg_141608) & ~(7'd93 == add_ln1116_25_reg_141608) & ~(7'd11 == add_ln1116_25_reg_141608) & ~(7'd121 == add_ln1116_25_reg_141608) & ~(7'd9 == add_ln1116_25_reg_141608) & ~(7'd65 == add_ln1116_25_reg_141608) & ~(7'd7 == add_ln1116_25_reg_141608) & ~(7'd123 == add_ln1116_25_reg_141608) & ~(7'd5 == add_ln1116_25_reg_141608) & ~(7'd79 == add_ln1116_25_reg_141608) & ~(7'd3 == add_ln1116_25_reg_141608) & ~(7'd125 == add_ln1116_25_reg_141608) & ~(7'd1 == add_ln1116_25_reg_141608) & ~(7'd63 == add_ln1116_25_reg_141608)); +end + +always @ (*) begin + ap_condition_13824 = (~(7'd95 == add_ln1116_29_reg_142013) & ~(7'd61 == add_ln1116_29_reg_142013) & ~(7'd87 == add_ln1116_29_reg_142013) & ~(7'd59 == add_ln1116_29_reg_142013) & ~(7'd97 == add_ln1116_29_reg_142013) & ~(7'd57 == add_ln1116_29_reg_142013) & ~(7'd77 == add_ln1116_29_reg_142013) & ~(7'd55 == add_ln1116_29_reg_142013) & ~(7'd99 == add_ln1116_29_reg_142013) & ~(7'd53 == add_ln1116_29_reg_142013) & ~(7'd85 == add_ln1116_29_reg_142013) & ~(7'd51 == add_ln1116_29_reg_142013) & ~(7'd101 == add_ln1116_29_reg_142013) & ~(7'd49 == add_ln1116_29_reg_142013) & ~(7'd75 == add_ln1116_29_reg_142013) & ~(7'd47 == add_ln1116_29_reg_142013) & ~(7'd103 == add_ln1116_29_reg_142013) & ~(7'd45 == add_ln1116_29_reg_142013) & ~(7'd89 == add_ln1116_29_reg_142013) & ~(7'd43 == add_ln1116_29_reg_142013) & ~(7'd105 == add_ln1116_29_reg_142013) & ~(7'd41 == add_ln1116_29_reg_142013) & ~(7'd73 == add_ln1116_29_reg_142013) & ~(7'd39 == add_ln1116_29_reg_142013) & ~(7'd107 == add_ln1116_29_reg_142013) & ~(7'd37 == add_ln1116_29_reg_142013) & ~(7'd81 == add_ln1116_29_reg_142013) & ~(7'd35 == add_ln1116_29_reg_142013) & ~(7'd109 == add_ln1116_29_reg_142013) & ~(7'd33 == add_ln1116_29_reg_142013) & ~(7'd71 == add_ln1116_29_reg_142013) & ~(7'd31 == add_ln1116_29_reg_142013) & ~(7'd111 == add_ln1116_29_reg_142013) & ~(7'd29 == add_ln1116_29_reg_142013) & ~(7'd91 == add_ln1116_29_reg_142013) & ~(7'd27 == add_ln1116_29_reg_142013) & ~(7'd113 == add_ln1116_29_reg_142013) & ~(7'd25 == add_ln1116_29_reg_142013) & ~(7'd69 == add_ln1116_29_reg_142013) & ~(7'd23 == add_ln1116_29_reg_142013) & ~(7'd115 == add_ln1116_29_reg_142013) & ~(7'd21 == add_ln1116_29_reg_142013) & ~(7'd83 == add_ln1116_29_reg_142013) & ~(7'd19 == add_ln1116_29_reg_142013) & ~(7'd117 == add_ln1116_29_reg_142013) & ~(7'd17 == add_ln1116_29_reg_142013) & ~(7'd67 == add_ln1116_29_reg_142013) & ~(7'd15 == add_ln1116_29_reg_142013) & ~(7'd119 == add_ln1116_29_reg_142013) & ~(7'd13 == add_ln1116_29_reg_142013) & ~(7'd93 == add_ln1116_29_reg_142013) & ~(7'd11 == add_ln1116_29_reg_142013) & ~(7'd121 == add_ln1116_29_reg_142013) & ~(7'd9 == add_ln1116_29_reg_142013) & ~(7'd65 == add_ln1116_29_reg_142013) & ~(7'd7 == add_ln1116_29_reg_142013) & ~(7'd123 == add_ln1116_29_reg_142013) & ~(7'd5 == add_ln1116_29_reg_142013) & ~(7'd79 == add_ln1116_29_reg_142013) & ~(7'd3 == add_ln1116_29_reg_142013) & ~(7'd125 == add_ln1116_29_reg_142013) & ~(7'd1 == add_ln1116_29_reg_142013) & ~(7'd63 == add_ln1116_29_reg_142013)); +end + +always @ (*) begin + ap_condition_13953 = (~(7'd0 == add_ln1116_3_reg_142532) & ~(7'd126 == add_ln1116_3_reg_142532) & ~(7'd2 == add_ln1116_3_reg_142532) & ~(7'd64 == add_ln1116_3_reg_142532) & ~(7'd4 == add_ln1116_3_reg_142532) & ~(7'd124 == add_ln1116_3_reg_142532) & ~(7'd6 == add_ln1116_3_reg_142532) & ~(7'd94 == add_ln1116_3_reg_142532) & ~(7'd8 == add_ln1116_3_reg_142532) & ~(7'd122 == add_ln1116_3_reg_142532) & ~(7'd10 == add_ln1116_3_reg_142532) & ~(7'd66 == add_ln1116_3_reg_142532) & ~(7'd12 == add_ln1116_3_reg_142532) & ~(7'd120 == add_ln1116_3_reg_142532) & ~(7'd14 == add_ln1116_3_reg_142532) & ~(7'd80 == add_ln1116_3_reg_142532) & ~(7'd16 == add_ln1116_3_reg_142532) & ~(7'd118 == add_ln1116_3_reg_142532) & ~(7'd18 == add_ln1116_3_reg_142532) & ~(7'd68 == add_ln1116_3_reg_142532) & ~(7'd20 == add_ln1116_3_reg_142532) & ~(7'd116 == add_ln1116_3_reg_142532) & ~(7'd22 == add_ln1116_3_reg_142532) & ~(7'd92 == add_ln1116_3_reg_142532) & ~(7'd24 == add_ln1116_3_reg_142532) & ~(7'd114 == add_ln1116_3_reg_142532) & ~(7'd26 == add_ln1116_3_reg_142532) & ~(7'd70 == add_ln1116_3_reg_142532) & ~(7'd28 == add_ln1116_3_reg_142532) & ~(7'd112 == add_ln1116_3_reg_142532) & ~(7'd30 == add_ln1116_3_reg_142532) & ~(7'd86 == add_ln1116_3_reg_142532) & ~(7'd32 == add_ln1116_3_reg_142532) & ~(7'd110 == add_ln1116_3_reg_142532) & ~(7'd34 == add_ln1116_3_reg_142532) & ~(7'd72 == add_ln1116_3_reg_142532) & ~(7'd36 == add_ln1116_3_reg_142532) & ~(7'd108 == add_ln1116_3_reg_142532) & ~(7'd38 == add_ln1116_3_reg_142532) & ~(7'd90 == add_ln1116_3_reg_142532) & ~(7'd40 == add_ln1116_3_reg_142532) & ~(7'd106 == add_ln1116_3_reg_142532) & ~(7'd42 == add_ln1116_3_reg_142532) & ~(7'd74 == add_ln1116_3_reg_142532) & ~(7'd44 == add_ln1116_3_reg_142532) & ~(7'd104 == add_ln1116_3_reg_142532) & ~(7'd46 == add_ln1116_3_reg_142532) & ~(7'd82 == add_ln1116_3_reg_142532) & ~(7'd48 == add_ln1116_3_reg_142532) & ~(7'd102 == add_ln1116_3_reg_142532) & ~(7'd50 == add_ln1116_3_reg_142532) & ~(7'd76 == add_ln1116_3_reg_142532) & ~(7'd52 == add_ln1116_3_reg_142532) & ~(7'd100 == add_ln1116_3_reg_142532) & ~(7'd54 == add_ln1116_3_reg_142532) & ~(7'd88 == add_ln1116_3_reg_142532) & ~(7'd56 == add_ln1116_3_reg_142532) & ~(7'd98 == add_ln1116_3_reg_142532) & ~(7'd58 == add_ln1116_3_reg_142532) & ~(7'd78 == add_ln1116_3_reg_142532) & ~(7'd60 == add_ln1116_3_reg_142532) & ~(7'd96 == add_ln1116_3_reg_142532) & ~(7'd62 == add_ln1116_3_reg_142532) & ~(7'd84 == add_ln1116_3_reg_142532)); +end + +always @ (*) begin + ap_condition_14082 = (~(7'd0 == add_ln1116_9_reg_142942) & ~(7'd126 == add_ln1116_9_reg_142942) & ~(7'd2 == add_ln1116_9_reg_142942) & ~(7'd64 == add_ln1116_9_reg_142942) & ~(7'd4 == add_ln1116_9_reg_142942) & ~(7'd124 == add_ln1116_9_reg_142942) & ~(7'd6 == add_ln1116_9_reg_142942) & ~(7'd94 == add_ln1116_9_reg_142942) & ~(7'd8 == add_ln1116_9_reg_142942) & ~(7'd122 == add_ln1116_9_reg_142942) & ~(7'd10 == add_ln1116_9_reg_142942) & ~(7'd66 == add_ln1116_9_reg_142942) & ~(7'd12 == add_ln1116_9_reg_142942) & ~(7'd120 == add_ln1116_9_reg_142942) & ~(7'd14 == add_ln1116_9_reg_142942) & ~(7'd80 == add_ln1116_9_reg_142942) & ~(7'd16 == add_ln1116_9_reg_142942) & ~(7'd118 == add_ln1116_9_reg_142942) & ~(7'd18 == add_ln1116_9_reg_142942) & ~(7'd68 == add_ln1116_9_reg_142942) & ~(7'd20 == add_ln1116_9_reg_142942) & ~(7'd116 == add_ln1116_9_reg_142942) & ~(7'd22 == add_ln1116_9_reg_142942) & ~(7'd92 == add_ln1116_9_reg_142942) & ~(7'd24 == add_ln1116_9_reg_142942) & ~(7'd114 == add_ln1116_9_reg_142942) & ~(7'd26 == add_ln1116_9_reg_142942) & ~(7'd70 == add_ln1116_9_reg_142942) & ~(7'd28 == add_ln1116_9_reg_142942) & ~(7'd112 == add_ln1116_9_reg_142942) & ~(7'd30 == add_ln1116_9_reg_142942) & ~(7'd86 == add_ln1116_9_reg_142942) & ~(7'd32 == add_ln1116_9_reg_142942) & ~(7'd110 == add_ln1116_9_reg_142942) & ~(7'd34 == add_ln1116_9_reg_142942) & ~(7'd72 == add_ln1116_9_reg_142942) & ~(7'd36 == add_ln1116_9_reg_142942) & ~(7'd108 == add_ln1116_9_reg_142942) & ~(7'd38 == add_ln1116_9_reg_142942) & ~(7'd90 == add_ln1116_9_reg_142942) & ~(7'd40 == add_ln1116_9_reg_142942) & ~(7'd106 == add_ln1116_9_reg_142942) & ~(7'd42 == add_ln1116_9_reg_142942) & ~(7'd74 == add_ln1116_9_reg_142942) & ~(7'd44 == add_ln1116_9_reg_142942) & ~(7'd104 == add_ln1116_9_reg_142942) & ~(7'd46 == add_ln1116_9_reg_142942) & ~(7'd82 == add_ln1116_9_reg_142942) & ~(7'd48 == add_ln1116_9_reg_142942) & ~(7'd102 == add_ln1116_9_reg_142942) & ~(7'd50 == add_ln1116_9_reg_142942) & ~(7'd76 == add_ln1116_9_reg_142942) & ~(7'd52 == add_ln1116_9_reg_142942) & ~(7'd100 == add_ln1116_9_reg_142942) & ~(7'd54 == add_ln1116_9_reg_142942) & ~(7'd88 == add_ln1116_9_reg_142942) & ~(7'd56 == add_ln1116_9_reg_142942) & ~(7'd98 == add_ln1116_9_reg_142942) & ~(7'd58 == add_ln1116_9_reg_142942) & ~(7'd78 == add_ln1116_9_reg_142942) & ~(7'd60 == add_ln1116_9_reg_142942) & ~(7'd96 == add_ln1116_9_reg_142942) & ~(7'd62 == add_ln1116_9_reg_142942) & ~(7'd84 == add_ln1116_9_reg_142942)); +end + +always @ (*) begin + ap_condition_14211 = (~(7'd0 == add_ln1116_14_reg_143436) & ~(7'd126 == add_ln1116_14_reg_143436) & ~(7'd2 == add_ln1116_14_reg_143436) & ~(7'd64 == add_ln1116_14_reg_143436) & ~(7'd4 == add_ln1116_14_reg_143436) & ~(7'd124 == add_ln1116_14_reg_143436) & ~(7'd6 == add_ln1116_14_reg_143436) & ~(7'd94 == add_ln1116_14_reg_143436) & ~(7'd8 == add_ln1116_14_reg_143436) & ~(7'd122 == add_ln1116_14_reg_143436) & ~(7'd10 == add_ln1116_14_reg_143436) & ~(7'd66 == add_ln1116_14_reg_143436) & ~(7'd12 == add_ln1116_14_reg_143436) & ~(7'd120 == add_ln1116_14_reg_143436) & ~(7'd14 == add_ln1116_14_reg_143436) & ~(7'd80 == add_ln1116_14_reg_143436) & ~(7'd16 == add_ln1116_14_reg_143436) & ~(7'd118 == add_ln1116_14_reg_143436) & ~(7'd18 == add_ln1116_14_reg_143436) & ~(7'd68 == add_ln1116_14_reg_143436) & ~(7'd20 == add_ln1116_14_reg_143436) & ~(7'd116 == add_ln1116_14_reg_143436) & ~(7'd22 == add_ln1116_14_reg_143436) & ~(7'd92 == add_ln1116_14_reg_143436) & ~(7'd24 == add_ln1116_14_reg_143436) & ~(7'd114 == add_ln1116_14_reg_143436) & ~(7'd26 == add_ln1116_14_reg_143436) & ~(7'd70 == add_ln1116_14_reg_143436) & ~(7'd28 == add_ln1116_14_reg_143436) & ~(7'd112 == add_ln1116_14_reg_143436) & ~(7'd30 == add_ln1116_14_reg_143436) & ~(7'd86 == add_ln1116_14_reg_143436) & ~(7'd32 == add_ln1116_14_reg_143436) & ~(7'd110 == add_ln1116_14_reg_143436) & ~(7'd34 == add_ln1116_14_reg_143436) & ~(7'd72 == add_ln1116_14_reg_143436) & ~(7'd36 == add_ln1116_14_reg_143436) & ~(7'd108 == add_ln1116_14_reg_143436) & ~(7'd38 == add_ln1116_14_reg_143436) & ~(7'd90 == add_ln1116_14_reg_143436) & ~(7'd40 == add_ln1116_14_reg_143436) & ~(7'd106 == add_ln1116_14_reg_143436) & ~(7'd42 == add_ln1116_14_reg_143436) & ~(7'd74 == add_ln1116_14_reg_143436) & ~(7'd44 == add_ln1116_14_reg_143436) & ~(7'd104 == add_ln1116_14_reg_143436) & ~(7'd46 == add_ln1116_14_reg_143436) & ~(7'd82 == add_ln1116_14_reg_143436) & ~(7'd48 == add_ln1116_14_reg_143436) & ~(7'd102 == add_ln1116_14_reg_143436) & ~(7'd50 == add_ln1116_14_reg_143436) & ~(7'd76 == add_ln1116_14_reg_143436) & ~(7'd52 == add_ln1116_14_reg_143436) & ~(7'd100 == add_ln1116_14_reg_143436) & ~(7'd54 == add_ln1116_14_reg_143436) & ~(7'd88 == add_ln1116_14_reg_143436) & ~(7'd56 == add_ln1116_14_reg_143436) & ~(7'd98 == add_ln1116_14_reg_143436) & ~(7'd58 == add_ln1116_14_reg_143436) & ~(7'd78 == add_ln1116_14_reg_143436) & ~(7'd60 == add_ln1116_14_reg_143436) & ~(7'd96 == add_ln1116_14_reg_143436) & ~(7'd62 == add_ln1116_14_reg_143436) & ~(7'd84 == add_ln1116_14_reg_143436)); +end + +always @ (*) begin + ap_condition_14340 = (~(7'd0 == add_ln1116_23_reg_143834) & ~(7'd126 == add_ln1116_23_reg_143834) & ~(7'd2 == add_ln1116_23_reg_143834) & ~(7'd64 == add_ln1116_23_reg_143834) & ~(7'd4 == add_ln1116_23_reg_143834) & ~(7'd124 == add_ln1116_23_reg_143834) & ~(7'd6 == add_ln1116_23_reg_143834) & ~(7'd94 == add_ln1116_23_reg_143834) & ~(7'd8 == add_ln1116_23_reg_143834) & ~(7'd122 == add_ln1116_23_reg_143834) & ~(7'd10 == add_ln1116_23_reg_143834) & ~(7'd66 == add_ln1116_23_reg_143834) & ~(7'd12 == add_ln1116_23_reg_143834) & ~(7'd120 == add_ln1116_23_reg_143834) & ~(7'd14 == add_ln1116_23_reg_143834) & ~(7'd80 == add_ln1116_23_reg_143834) & ~(7'd16 == add_ln1116_23_reg_143834) & ~(7'd118 == add_ln1116_23_reg_143834) & ~(7'd18 == add_ln1116_23_reg_143834) & ~(7'd68 == add_ln1116_23_reg_143834) & ~(7'd20 == add_ln1116_23_reg_143834) & ~(7'd116 == add_ln1116_23_reg_143834) & ~(7'd22 == add_ln1116_23_reg_143834) & ~(7'd92 == add_ln1116_23_reg_143834) & ~(7'd24 == add_ln1116_23_reg_143834) & ~(7'd114 == add_ln1116_23_reg_143834) & ~(7'd26 == add_ln1116_23_reg_143834) & ~(7'd70 == add_ln1116_23_reg_143834) & ~(7'd28 == add_ln1116_23_reg_143834) & ~(7'd112 == add_ln1116_23_reg_143834) & ~(7'd30 == add_ln1116_23_reg_143834) & ~(7'd86 == add_ln1116_23_reg_143834) & ~(7'd32 == add_ln1116_23_reg_143834) & ~(7'd110 == add_ln1116_23_reg_143834) & ~(7'd34 == add_ln1116_23_reg_143834) & ~(7'd72 == add_ln1116_23_reg_143834) & ~(7'd36 == add_ln1116_23_reg_143834) & ~(7'd108 == add_ln1116_23_reg_143834) & ~(7'd38 == add_ln1116_23_reg_143834) & ~(7'd90 == add_ln1116_23_reg_143834) & ~(7'd40 == add_ln1116_23_reg_143834) & ~(7'd106 == add_ln1116_23_reg_143834) & ~(7'd42 == add_ln1116_23_reg_143834) & ~(7'd74 == add_ln1116_23_reg_143834) & ~(7'd44 == add_ln1116_23_reg_143834) & ~(7'd104 == add_ln1116_23_reg_143834) & ~(7'd46 == add_ln1116_23_reg_143834) & ~(7'd82 == add_ln1116_23_reg_143834) & ~(7'd48 == add_ln1116_23_reg_143834) & ~(7'd102 == add_ln1116_23_reg_143834) & ~(7'd50 == add_ln1116_23_reg_143834) & ~(7'd76 == add_ln1116_23_reg_143834) & ~(7'd52 == add_ln1116_23_reg_143834) & ~(7'd100 == add_ln1116_23_reg_143834) & ~(7'd54 == add_ln1116_23_reg_143834) & ~(7'd88 == add_ln1116_23_reg_143834) & ~(7'd56 == add_ln1116_23_reg_143834) & ~(7'd98 == add_ln1116_23_reg_143834) & ~(7'd58 == add_ln1116_23_reg_143834) & ~(7'd78 == add_ln1116_23_reg_143834) & ~(7'd60 == add_ln1116_23_reg_143834) & ~(7'd96 == add_ln1116_23_reg_143834) & ~(7'd62 == add_ln1116_23_reg_143834) & ~(7'd84 == add_ln1116_23_reg_143834)); +end + +always @ (*) begin + ap_condition_14532 = (~(7'd95 == add_ln1116_15_reg_144296) & ~(7'd61 == add_ln1116_15_reg_144296) & ~(7'd87 == add_ln1116_15_reg_144296) & ~(7'd59 == add_ln1116_15_reg_144296) & ~(7'd97 == add_ln1116_15_reg_144296) & ~(7'd57 == add_ln1116_15_reg_144296) & ~(7'd77 == add_ln1116_15_reg_144296) & ~(7'd55 == add_ln1116_15_reg_144296) & ~(7'd99 == add_ln1116_15_reg_144296) & ~(7'd53 == add_ln1116_15_reg_144296) & ~(7'd85 == add_ln1116_15_reg_144296) & ~(7'd51 == add_ln1116_15_reg_144296) & ~(7'd101 == add_ln1116_15_reg_144296) & ~(7'd49 == add_ln1116_15_reg_144296) & ~(7'd75 == add_ln1116_15_reg_144296) & ~(7'd47 == add_ln1116_15_reg_144296) & ~(7'd103 == add_ln1116_15_reg_144296) & ~(7'd45 == add_ln1116_15_reg_144296) & ~(7'd89 == add_ln1116_15_reg_144296) & ~(7'd43 == add_ln1116_15_reg_144296) & ~(7'd105 == add_ln1116_15_reg_144296) & ~(7'd41 == add_ln1116_15_reg_144296) & ~(7'd73 == add_ln1116_15_reg_144296) & ~(7'd39 == add_ln1116_15_reg_144296) & ~(7'd107 == add_ln1116_15_reg_144296) & ~(7'd37 == add_ln1116_15_reg_144296) & ~(7'd81 == add_ln1116_15_reg_144296) & ~(7'd35 == add_ln1116_15_reg_144296) & ~(7'd109 == add_ln1116_15_reg_144296) & ~(7'd33 == add_ln1116_15_reg_144296) & ~(7'd71 == add_ln1116_15_reg_144296) & ~(7'd31 == add_ln1116_15_reg_144296) & ~(7'd111 == add_ln1116_15_reg_144296) & ~(7'd29 == add_ln1116_15_reg_144296) & ~(7'd91 == add_ln1116_15_reg_144296) & ~(7'd27 == add_ln1116_15_reg_144296) & ~(7'd113 == add_ln1116_15_reg_144296) & ~(7'd25 == add_ln1116_15_reg_144296) & ~(7'd69 == add_ln1116_15_reg_144296) & ~(7'd23 == add_ln1116_15_reg_144296) & ~(7'd115 == add_ln1116_15_reg_144296) & ~(7'd21 == add_ln1116_15_reg_144296) & ~(7'd83 == add_ln1116_15_reg_144296) & ~(7'd19 == add_ln1116_15_reg_144296) & ~(7'd117 == add_ln1116_15_reg_144296) & ~(7'd17 == add_ln1116_15_reg_144296) & ~(7'd67 == add_ln1116_15_reg_144296) & ~(7'd15 == add_ln1116_15_reg_144296) & ~(7'd119 == add_ln1116_15_reg_144296) & ~(7'd13 == add_ln1116_15_reg_144296) & ~(7'd93 == add_ln1116_15_reg_144296) & ~(7'd11 == add_ln1116_15_reg_144296) & ~(7'd121 == add_ln1116_15_reg_144296) & ~(7'd9 == add_ln1116_15_reg_144296) & ~(7'd65 == add_ln1116_15_reg_144296) & ~(7'd7 == add_ln1116_15_reg_144296) & ~(7'd123 == add_ln1116_15_reg_144296) & ~(7'd5 == add_ln1116_15_reg_144296) & ~(7'd79 == add_ln1116_15_reg_144296) & ~(7'd3 == add_ln1116_15_reg_144296) & ~(7'd125 == add_ln1116_15_reg_144296) & ~(7'd1 == add_ln1116_15_reg_144296) & ~(7'd63 == add_ln1116_15_reg_144296)); +end + +always @ (*) begin + ap_condition_14724 = (~(7'd95 == add_ln1116_24_reg_144701) & ~(7'd61 == add_ln1116_24_reg_144701) & ~(7'd87 == add_ln1116_24_reg_144701) & ~(7'd59 == add_ln1116_24_reg_144701) & ~(7'd97 == add_ln1116_24_reg_144701) & ~(7'd57 == add_ln1116_24_reg_144701) & ~(7'd77 == add_ln1116_24_reg_144701) & ~(7'd55 == add_ln1116_24_reg_144701) & ~(7'd99 == add_ln1116_24_reg_144701) & ~(7'd53 == add_ln1116_24_reg_144701) & ~(7'd85 == add_ln1116_24_reg_144701) & ~(7'd51 == add_ln1116_24_reg_144701) & ~(7'd101 == add_ln1116_24_reg_144701) & ~(7'd49 == add_ln1116_24_reg_144701) & ~(7'd75 == add_ln1116_24_reg_144701) & ~(7'd47 == add_ln1116_24_reg_144701) & ~(7'd103 == add_ln1116_24_reg_144701) & ~(7'd45 == add_ln1116_24_reg_144701) & ~(7'd89 == add_ln1116_24_reg_144701) & ~(7'd43 == add_ln1116_24_reg_144701) & ~(7'd105 == add_ln1116_24_reg_144701) & ~(7'd41 == add_ln1116_24_reg_144701) & ~(7'd73 == add_ln1116_24_reg_144701) & ~(7'd39 == add_ln1116_24_reg_144701) & ~(7'd107 == add_ln1116_24_reg_144701) & ~(7'd37 == add_ln1116_24_reg_144701) & ~(7'd81 == add_ln1116_24_reg_144701) & ~(7'd35 == add_ln1116_24_reg_144701) & ~(7'd109 == add_ln1116_24_reg_144701) & ~(7'd33 == add_ln1116_24_reg_144701) & ~(7'd71 == add_ln1116_24_reg_144701) & ~(7'd31 == add_ln1116_24_reg_144701) & ~(7'd111 == add_ln1116_24_reg_144701) & ~(7'd29 == add_ln1116_24_reg_144701) & ~(7'd91 == add_ln1116_24_reg_144701) & ~(7'd27 == add_ln1116_24_reg_144701) & ~(7'd113 == add_ln1116_24_reg_144701) & ~(7'd25 == add_ln1116_24_reg_144701) & ~(7'd69 == add_ln1116_24_reg_144701) & ~(7'd23 == add_ln1116_24_reg_144701) & ~(7'd115 == add_ln1116_24_reg_144701) & ~(7'd21 == add_ln1116_24_reg_144701) & ~(7'd83 == add_ln1116_24_reg_144701) & ~(7'd19 == add_ln1116_24_reg_144701) & ~(7'd117 == add_ln1116_24_reg_144701) & ~(7'd17 == add_ln1116_24_reg_144701) & ~(7'd67 == add_ln1116_24_reg_144701) & ~(7'd15 == add_ln1116_24_reg_144701) & ~(7'd119 == add_ln1116_24_reg_144701) & ~(7'd13 == add_ln1116_24_reg_144701) & ~(7'd93 == add_ln1116_24_reg_144701) & ~(7'd11 == add_ln1116_24_reg_144701) & ~(7'd121 == add_ln1116_24_reg_144701) & ~(7'd9 == add_ln1116_24_reg_144701) & ~(7'd65 == add_ln1116_24_reg_144701) & ~(7'd7 == add_ln1116_24_reg_144701) & ~(7'd123 == add_ln1116_24_reg_144701) & ~(7'd5 == add_ln1116_24_reg_144701) & ~(7'd79 == add_ln1116_24_reg_144701) & ~(7'd3 == add_ln1116_24_reg_144701) & ~(7'd125 == add_ln1116_24_reg_144701) & ~(7'd1 == add_ln1116_24_reg_144701) & ~(7'd63 == add_ln1116_24_reg_144701)); +end + +always @ (*) begin + ap_condition_14916 = (~(7'd95 == add_ln1116_27_reg_145171) & ~(7'd61 == add_ln1116_27_reg_145171) & ~(7'd87 == add_ln1116_27_reg_145171) & ~(7'd59 == add_ln1116_27_reg_145171) & ~(7'd97 == add_ln1116_27_reg_145171) & ~(7'd57 == add_ln1116_27_reg_145171) & ~(7'd77 == add_ln1116_27_reg_145171) & ~(7'd55 == add_ln1116_27_reg_145171) & ~(7'd99 == add_ln1116_27_reg_145171) & ~(7'd53 == add_ln1116_27_reg_145171) & ~(7'd85 == add_ln1116_27_reg_145171) & ~(7'd51 == add_ln1116_27_reg_145171) & ~(7'd101 == add_ln1116_27_reg_145171) & ~(7'd49 == add_ln1116_27_reg_145171) & ~(7'd75 == add_ln1116_27_reg_145171) & ~(7'd47 == add_ln1116_27_reg_145171) & ~(7'd103 == add_ln1116_27_reg_145171) & ~(7'd45 == add_ln1116_27_reg_145171) & ~(7'd89 == add_ln1116_27_reg_145171) & ~(7'd43 == add_ln1116_27_reg_145171) & ~(7'd105 == add_ln1116_27_reg_145171) & ~(7'd41 == add_ln1116_27_reg_145171) & ~(7'd73 == add_ln1116_27_reg_145171) & ~(7'd39 == add_ln1116_27_reg_145171) & ~(7'd107 == add_ln1116_27_reg_145171) & ~(7'd37 == add_ln1116_27_reg_145171) & ~(7'd81 == add_ln1116_27_reg_145171) & ~(7'd35 == add_ln1116_27_reg_145171) & ~(7'd109 == add_ln1116_27_reg_145171) & ~(7'd33 == add_ln1116_27_reg_145171) & ~(7'd71 == add_ln1116_27_reg_145171) & ~(7'd31 == add_ln1116_27_reg_145171) & ~(7'd111 == add_ln1116_27_reg_145171) & ~(7'd29 == add_ln1116_27_reg_145171) & ~(7'd91 == add_ln1116_27_reg_145171) & ~(7'd27 == add_ln1116_27_reg_145171) & ~(7'd113 == add_ln1116_27_reg_145171) & ~(7'd25 == add_ln1116_27_reg_145171) & ~(7'd69 == add_ln1116_27_reg_145171) & ~(7'd23 == add_ln1116_27_reg_145171) & ~(7'd115 == add_ln1116_27_reg_145171) & ~(7'd21 == add_ln1116_27_reg_145171) & ~(7'd83 == add_ln1116_27_reg_145171) & ~(7'd19 == add_ln1116_27_reg_145171) & ~(7'd117 == add_ln1116_27_reg_145171) & ~(7'd17 == add_ln1116_27_reg_145171) & ~(7'd67 == add_ln1116_27_reg_145171) & ~(7'd15 == add_ln1116_27_reg_145171) & ~(7'd119 == add_ln1116_27_reg_145171) & ~(7'd13 == add_ln1116_27_reg_145171) & ~(7'd93 == add_ln1116_27_reg_145171) & ~(7'd11 == add_ln1116_27_reg_145171) & ~(7'd121 == add_ln1116_27_reg_145171) & ~(7'd9 == add_ln1116_27_reg_145171) & ~(7'd65 == add_ln1116_27_reg_145171) & ~(7'd7 == add_ln1116_27_reg_145171) & ~(7'd123 == add_ln1116_27_reg_145171) & ~(7'd5 == add_ln1116_27_reg_145171) & ~(7'd79 == add_ln1116_27_reg_145171) & ~(7'd3 == add_ln1116_27_reg_145171) & ~(7'd125 == add_ln1116_27_reg_145171) & ~(7'd1 == add_ln1116_27_reg_145171) & ~(7'd63 == add_ln1116_27_reg_145171)); +end + +always @ (*) begin + ap_condition_15108 = (~(7'd95 == add_ln1116_31_reg_145576) & ~(7'd61 == add_ln1116_31_reg_145576) & ~(7'd87 == add_ln1116_31_reg_145576) & ~(7'd59 == add_ln1116_31_reg_145576) & ~(7'd97 == add_ln1116_31_reg_145576) & ~(7'd57 == add_ln1116_31_reg_145576) & ~(7'd77 == add_ln1116_31_reg_145576) & ~(7'd55 == add_ln1116_31_reg_145576) & ~(7'd99 == add_ln1116_31_reg_145576) & ~(7'd53 == add_ln1116_31_reg_145576) & ~(7'd85 == add_ln1116_31_reg_145576) & ~(7'd51 == add_ln1116_31_reg_145576) & ~(7'd101 == add_ln1116_31_reg_145576) & ~(7'd49 == add_ln1116_31_reg_145576) & ~(7'd75 == add_ln1116_31_reg_145576) & ~(7'd47 == add_ln1116_31_reg_145576) & ~(7'd103 == add_ln1116_31_reg_145576) & ~(7'd45 == add_ln1116_31_reg_145576) & ~(7'd89 == add_ln1116_31_reg_145576) & ~(7'd43 == add_ln1116_31_reg_145576) & ~(7'd105 == add_ln1116_31_reg_145576) & ~(7'd41 == add_ln1116_31_reg_145576) & ~(7'd73 == add_ln1116_31_reg_145576) & ~(7'd39 == add_ln1116_31_reg_145576) & ~(7'd107 == add_ln1116_31_reg_145576) & ~(7'd37 == add_ln1116_31_reg_145576) & ~(7'd81 == add_ln1116_31_reg_145576) & ~(7'd35 == add_ln1116_31_reg_145576) & ~(7'd109 == add_ln1116_31_reg_145576) & ~(7'd33 == add_ln1116_31_reg_145576) & ~(7'd71 == add_ln1116_31_reg_145576) & ~(7'd31 == add_ln1116_31_reg_145576) & ~(7'd111 == add_ln1116_31_reg_145576) & ~(7'd29 == add_ln1116_31_reg_145576) & ~(7'd91 == add_ln1116_31_reg_145576) & ~(7'd27 == add_ln1116_31_reg_145576) & ~(7'd113 == add_ln1116_31_reg_145576) & ~(7'd25 == add_ln1116_31_reg_145576) & ~(7'd69 == add_ln1116_31_reg_145576) & ~(7'd23 == add_ln1116_31_reg_145576) & ~(7'd115 == add_ln1116_31_reg_145576) & ~(7'd21 == add_ln1116_31_reg_145576) & ~(7'd83 == add_ln1116_31_reg_145576) & ~(7'd19 == add_ln1116_31_reg_145576) & ~(7'd117 == add_ln1116_31_reg_145576) & ~(7'd17 == add_ln1116_31_reg_145576) & ~(7'd67 == add_ln1116_31_reg_145576) & ~(7'd15 == add_ln1116_31_reg_145576) & ~(7'd119 == add_ln1116_31_reg_145576) & ~(7'd13 == add_ln1116_31_reg_145576) & ~(7'd93 == add_ln1116_31_reg_145576) & ~(7'd11 == add_ln1116_31_reg_145576) & ~(7'd121 == add_ln1116_31_reg_145576) & ~(7'd9 == add_ln1116_31_reg_145576) & ~(7'd65 == add_ln1116_31_reg_145576) & ~(7'd7 == add_ln1116_31_reg_145576) & ~(7'd123 == add_ln1116_31_reg_145576) & ~(7'd5 == add_ln1116_31_reg_145576) & ~(7'd79 == add_ln1116_31_reg_145576) & ~(7'd3 == add_ln1116_31_reg_145576) & ~(7'd125 == add_ln1116_31_reg_145576) & ~(7'd1 == add_ln1116_31_reg_145576) & ~(7'd63 == add_ln1116_31_reg_145576)); +end + +always @ (*) begin + ap_condition_24171 = (~(6'd0 == add_ln1265_reg_147629) & ~(6'd62 == add_ln1265_reg_147629) & ~(6'd2 == add_ln1265_reg_147629) & ~(6'd32 == add_ln1265_reg_147629) & ~(6'd4 == add_ln1265_reg_147629) & ~(6'd60 == add_ln1265_reg_147629) & ~(6'd6 == add_ln1265_reg_147629) & ~(6'd46 == add_ln1265_reg_147629) & ~(6'd8 == add_ln1265_reg_147629) & ~(6'd58 == add_ln1265_reg_147629) & ~(6'd10 == add_ln1265_reg_147629) & ~(6'd34 == add_ln1265_reg_147629) & ~(6'd12 == add_ln1265_reg_147629) & ~(6'd56 == add_ln1265_reg_147629) & ~(6'd14 == add_ln1265_reg_147629) & ~(6'd40 == add_ln1265_reg_147629) & ~(6'd16 == add_ln1265_reg_147629) & ~(6'd54 == add_ln1265_reg_147629) & ~(6'd18 == add_ln1265_reg_147629) & ~(6'd36 == add_ln1265_reg_147629) & ~(6'd20 == add_ln1265_reg_147629) & ~(6'd52 == add_ln1265_reg_147629) & ~(6'd22 == add_ln1265_reg_147629) & ~(6'd44 == add_ln1265_reg_147629) & ~(6'd24 == add_ln1265_reg_147629) & ~(6'd50 == add_ln1265_reg_147629) & ~(6'd26 == add_ln1265_reg_147629) & ~(6'd38 == add_ln1265_reg_147629) & ~(6'd28 == add_ln1265_reg_147629) & ~(6'd48 == add_ln1265_reg_147629) & ~(6'd30 == add_ln1265_reg_147629) & ~(6'd42 == add_ln1265_reg_147629)); +end + +always @ (*) begin + ap_condition_25226 = (~(6'd31 == add_ln1265_3_reg_148019) & ~(6'd1 == add_ln1265_3_reg_148019) & ~(6'd61 == add_ln1265_3_reg_148019) & ~(6'd3 == add_ln1265_3_reg_148019) & ~(6'd39 == add_ln1265_3_reg_148019) & ~(6'd5 == add_ln1265_3_reg_148019) & ~(6'd59 == add_ln1265_3_reg_148019) & ~(6'd7 == add_ln1265_3_reg_148019) & ~(6'd33 == add_ln1265_3_reg_148019) & ~(6'd9 == add_ln1265_3_reg_148019) & ~(6'd57 == add_ln1265_3_reg_148019) & ~(6'd11 == add_ln1265_3_reg_148019) & ~(6'd45 == add_ln1265_3_reg_148019) & ~(6'd13 == add_ln1265_3_reg_148019) & ~(6'd55 == add_ln1265_3_reg_148019) & ~(6'd15 == add_ln1265_3_reg_148019) & ~(6'd35 == add_ln1265_3_reg_148019) & ~(6'd17 == add_ln1265_3_reg_148019) & ~(6'd53 == add_ln1265_3_reg_148019) & ~(6'd19 == add_ln1265_3_reg_148019) & ~(6'd41 == add_ln1265_3_reg_148019) & ~(6'd21 == add_ln1265_3_reg_148019) & ~(6'd51 == add_ln1265_3_reg_148019) & ~(6'd23 == add_ln1265_3_reg_148019) & ~(6'd37 == add_ln1265_3_reg_148019) & ~(6'd25 == add_ln1265_3_reg_148019) & ~(6'd49 == add_ln1265_3_reg_148019) & ~(6'd27 == add_ln1265_3_reg_148019) & ~(6'd43 == add_ln1265_3_reg_148019) & ~(6'd29 == add_ln1265_3_reg_148019) & ~(6'd47 == add_ln1265_3_reg_148019)); +end + +always @ (*) begin + ap_condition_26549 = (~(6'd0 == add_ln1265_2_reg_152512) & ~(6'd62 == add_ln1265_2_reg_152512) & ~(6'd2 == add_ln1265_2_reg_152512) & ~(6'd32 == add_ln1265_2_reg_152512) & ~(6'd4 == add_ln1265_2_reg_152512) & ~(6'd60 == add_ln1265_2_reg_152512) & ~(6'd6 == add_ln1265_2_reg_152512) & ~(6'd46 == add_ln1265_2_reg_152512) & ~(6'd8 == add_ln1265_2_reg_152512) & ~(6'd58 == add_ln1265_2_reg_152512) & ~(6'd10 == add_ln1265_2_reg_152512) & ~(6'd34 == add_ln1265_2_reg_152512) & ~(6'd12 == add_ln1265_2_reg_152512) & ~(6'd56 == add_ln1265_2_reg_152512) & ~(6'd14 == add_ln1265_2_reg_152512) & ~(6'd40 == add_ln1265_2_reg_152512) & ~(6'd16 == add_ln1265_2_reg_152512) & ~(6'd54 == add_ln1265_2_reg_152512) & ~(6'd18 == add_ln1265_2_reg_152512) & ~(6'd36 == add_ln1265_2_reg_152512) & ~(6'd20 == add_ln1265_2_reg_152512) & ~(6'd52 == add_ln1265_2_reg_152512) & ~(6'd22 == add_ln1265_2_reg_152512) & ~(6'd44 == add_ln1265_2_reg_152512) & ~(6'd24 == add_ln1265_2_reg_152512) & ~(6'd50 == add_ln1265_2_reg_152512) & ~(6'd26 == add_ln1265_2_reg_152512) & ~(6'd38 == add_ln1265_2_reg_152512) & ~(6'd28 == add_ln1265_2_reg_152512) & ~(6'd48 == add_ln1265_2_reg_152512) & ~(6'd30 == add_ln1265_2_reg_152512) & ~(6'd42 == add_ln1265_2_reg_152512)); +end + +always @ (*) begin + ap_condition_27540 = (~(6'd31 == add_ln1265_6_reg_152920) & ~(6'd1 == add_ln1265_6_reg_152920) & ~(6'd61 == add_ln1265_6_reg_152920) & ~(6'd3 == add_ln1265_6_reg_152920) & ~(6'd39 == add_ln1265_6_reg_152920) & ~(6'd5 == add_ln1265_6_reg_152920) & ~(6'd59 == add_ln1265_6_reg_152920) & ~(6'd7 == add_ln1265_6_reg_152920) & ~(6'd33 == add_ln1265_6_reg_152920) & ~(6'd9 == add_ln1265_6_reg_152920) & ~(6'd57 == add_ln1265_6_reg_152920) & ~(6'd11 == add_ln1265_6_reg_152920) & ~(6'd45 == add_ln1265_6_reg_152920) & ~(6'd13 == add_ln1265_6_reg_152920) & ~(6'd55 == add_ln1265_6_reg_152920) & ~(6'd15 == add_ln1265_6_reg_152920) & ~(6'd35 == add_ln1265_6_reg_152920) & ~(6'd17 == add_ln1265_6_reg_152920) & ~(6'd53 == add_ln1265_6_reg_152920) & ~(6'd19 == add_ln1265_6_reg_152920) & ~(6'd41 == add_ln1265_6_reg_152920) & ~(6'd21 == add_ln1265_6_reg_152920) & ~(6'd51 == add_ln1265_6_reg_152920) & ~(6'd23 == add_ln1265_6_reg_152920) & ~(6'd37 == add_ln1265_6_reg_152920) & ~(6'd25 == add_ln1265_6_reg_152920) & ~(6'd49 == add_ln1265_6_reg_152920) & ~(6'd27 == add_ln1265_6_reg_152920) & ~(6'd43 == add_ln1265_6_reg_152920) & ~(6'd29 == add_ln1265_6_reg_152920) & ~(6'd47 == add_ln1265_6_reg_152920)); +end + +always @ (*) begin + ap_condition_28817 = (~(6'd0 == add_ln1265_1_reg_157439) & ~(6'd62 == add_ln1265_1_reg_157439) & ~(6'd2 == add_ln1265_1_reg_157439) & ~(6'd32 == add_ln1265_1_reg_157439) & ~(6'd4 == add_ln1265_1_reg_157439) & ~(6'd60 == add_ln1265_1_reg_157439) & ~(6'd6 == add_ln1265_1_reg_157439) & ~(6'd46 == add_ln1265_1_reg_157439) & ~(6'd8 == add_ln1265_1_reg_157439) & ~(6'd58 == add_ln1265_1_reg_157439) & ~(6'd10 == add_ln1265_1_reg_157439) & ~(6'd34 == add_ln1265_1_reg_157439) & ~(6'd12 == add_ln1265_1_reg_157439) & ~(6'd56 == add_ln1265_1_reg_157439) & ~(6'd14 == add_ln1265_1_reg_157439) & ~(6'd40 == add_ln1265_1_reg_157439) & ~(6'd16 == add_ln1265_1_reg_157439) & ~(6'd54 == add_ln1265_1_reg_157439) & ~(6'd18 == add_ln1265_1_reg_157439) & ~(6'd36 == add_ln1265_1_reg_157439) & ~(6'd20 == add_ln1265_1_reg_157439) & ~(6'd52 == add_ln1265_1_reg_157439) & ~(6'd22 == add_ln1265_1_reg_157439) & ~(6'd44 == add_ln1265_1_reg_157439) & ~(6'd24 == add_ln1265_1_reg_157439) & ~(6'd50 == add_ln1265_1_reg_157439) & ~(6'd26 == add_ln1265_1_reg_157439) & ~(6'd38 == add_ln1265_1_reg_157439) & ~(6'd28 == add_ln1265_1_reg_157439) & ~(6'd48 == add_ln1265_1_reg_157439) & ~(6'd30 == add_ln1265_1_reg_157439) & ~(6'd42 == add_ln1265_1_reg_157439)); +end + +always @ (*) begin + ap_condition_29808 = (~(6'd31 == add_ln1265_5_reg_157860) & ~(6'd1 == add_ln1265_5_reg_157860) & ~(6'd61 == add_ln1265_5_reg_157860) & ~(6'd3 == add_ln1265_5_reg_157860) & ~(6'd39 == add_ln1265_5_reg_157860) & ~(6'd5 == add_ln1265_5_reg_157860) & ~(6'd59 == add_ln1265_5_reg_157860) & ~(6'd7 == add_ln1265_5_reg_157860) & ~(6'd33 == add_ln1265_5_reg_157860) & ~(6'd9 == add_ln1265_5_reg_157860) & ~(6'd57 == add_ln1265_5_reg_157860) & ~(6'd11 == add_ln1265_5_reg_157860) & ~(6'd45 == add_ln1265_5_reg_157860) & ~(6'd13 == add_ln1265_5_reg_157860) & ~(6'd55 == add_ln1265_5_reg_157860) & ~(6'd15 == add_ln1265_5_reg_157860) & ~(6'd35 == add_ln1265_5_reg_157860) & ~(6'd17 == add_ln1265_5_reg_157860) & ~(6'd53 == add_ln1265_5_reg_157860) & ~(6'd19 == add_ln1265_5_reg_157860) & ~(6'd41 == add_ln1265_5_reg_157860) & ~(6'd21 == add_ln1265_5_reg_157860) & ~(6'd51 == add_ln1265_5_reg_157860) & ~(6'd23 == add_ln1265_5_reg_157860) & ~(6'd37 == add_ln1265_5_reg_157860) & ~(6'd25 == add_ln1265_5_reg_157860) & ~(6'd49 == add_ln1265_5_reg_157860) & ~(6'd27 == add_ln1265_5_reg_157860) & ~(6'd43 == add_ln1265_5_reg_157860) & ~(6'd29 == add_ln1265_5_reg_157860) & ~(6'd47 == add_ln1265_5_reg_157860)); +end + +always @ (*) begin + ap_condition_31067 = (~(6'd0 == add_ln1265_4_reg_162353) & ~(6'd62 == add_ln1265_4_reg_162353) & ~(6'd2 == add_ln1265_4_reg_162353) & ~(6'd32 == add_ln1265_4_reg_162353) & ~(6'd4 == add_ln1265_4_reg_162353) & ~(6'd60 == add_ln1265_4_reg_162353) & ~(6'd6 == add_ln1265_4_reg_162353) & ~(6'd46 == add_ln1265_4_reg_162353) & ~(6'd8 == add_ln1265_4_reg_162353) & ~(6'd58 == add_ln1265_4_reg_162353) & ~(6'd10 == add_ln1265_4_reg_162353) & ~(6'd34 == add_ln1265_4_reg_162353) & ~(6'd12 == add_ln1265_4_reg_162353) & ~(6'd56 == add_ln1265_4_reg_162353) & ~(6'd14 == add_ln1265_4_reg_162353) & ~(6'd40 == add_ln1265_4_reg_162353) & ~(6'd16 == add_ln1265_4_reg_162353) & ~(6'd54 == add_ln1265_4_reg_162353) & ~(6'd18 == add_ln1265_4_reg_162353) & ~(6'd36 == add_ln1265_4_reg_162353) & ~(6'd20 == add_ln1265_4_reg_162353) & ~(6'd52 == add_ln1265_4_reg_162353) & ~(6'd22 == add_ln1265_4_reg_162353) & ~(6'd44 == add_ln1265_4_reg_162353) & ~(6'd24 == add_ln1265_4_reg_162353) & ~(6'd50 == add_ln1265_4_reg_162353) & ~(6'd26 == add_ln1265_4_reg_162353) & ~(6'd38 == add_ln1265_4_reg_162353) & ~(6'd28 == add_ln1265_4_reg_162353) & ~(6'd48 == add_ln1265_4_reg_162353) & ~(6'd30 == add_ln1265_4_reg_162353) & ~(6'd42 == add_ln1265_4_reg_162353)); +end + +always @ (*) begin + ap_condition_32057 = (~(6'd31 == add_ln1265_7_reg_162761) & ~(6'd1 == add_ln1265_7_reg_162761) & ~(6'd61 == add_ln1265_7_reg_162761) & ~(6'd3 == add_ln1265_7_reg_162761) & ~(6'd39 == add_ln1265_7_reg_162761) & ~(6'd5 == add_ln1265_7_reg_162761) & ~(6'd59 == add_ln1265_7_reg_162761) & ~(6'd7 == add_ln1265_7_reg_162761) & ~(6'd33 == add_ln1265_7_reg_162761) & ~(6'd9 == add_ln1265_7_reg_162761) & ~(6'd57 == add_ln1265_7_reg_162761) & ~(6'd11 == add_ln1265_7_reg_162761) & ~(6'd45 == add_ln1265_7_reg_162761) & ~(6'd13 == add_ln1265_7_reg_162761) & ~(6'd55 == add_ln1265_7_reg_162761) & ~(6'd15 == add_ln1265_7_reg_162761) & ~(6'd35 == add_ln1265_7_reg_162761) & ~(6'd17 == add_ln1265_7_reg_162761) & ~(6'd53 == add_ln1265_7_reg_162761) & ~(6'd19 == add_ln1265_7_reg_162761) & ~(6'd41 == add_ln1265_7_reg_162761) & ~(6'd21 == add_ln1265_7_reg_162761) & ~(6'd51 == add_ln1265_7_reg_162761) & ~(6'd23 == add_ln1265_7_reg_162761) & ~(6'd37 == add_ln1265_7_reg_162761) & ~(6'd25 == add_ln1265_7_reg_162761) & ~(6'd49 == add_ln1265_7_reg_162761) & ~(6'd27 == add_ln1265_7_reg_162761) & ~(6'd43 == add_ln1265_7_reg_162761) & ~(6'd29 == add_ln1265_7_reg_162761) & ~(6'd47 == add_ln1265_7_reg_162761)); +end + +assign ap_phi_mux_fw_0_0_0_0_0_0_phi_fu_91223_p4 = fw_0_0_0_0_0_0_reg_91219; + +assign ap_phi_mux_fw_0_0_0_0_1_0_phi_fu_91507_p4 = fw_0_0_0_0_1_0_reg_91503; + +assign ap_phi_mux_fw_0_0_0_1_0_0_phi_fu_91803_p4 = fw_0_0_0_1_0_0_reg_91799; + +assign ap_phi_mux_fw_0_0_0_1_1_0_phi_fu_92083_p4 = fw_0_0_0_1_1_0_reg_92079; + +assign ap_phi_mux_fw_0_0_1_0_0_0_phi_fu_92409_p4 = fw_0_0_1_0_0_0_reg_92405; + +assign ap_phi_mux_fw_0_0_1_0_1_0_phi_fu_92693_p4 = fw_0_0_1_0_1_0_reg_92689; + +assign ap_phi_mux_fw_0_0_1_1_0_0_phi_fu_92989_p4 = fw_0_0_1_1_0_0_reg_92985; + +assign ap_phi_mux_fw_0_0_1_1_1_0_phi_fu_93269_p4 = fw_0_0_1_1_1_0_reg_93265; + +assign ap_phi_mux_fw_0_1_0_0_0_0_phi_fu_93607_p4 = fw_0_1_0_0_0_0_reg_93603; + +assign ap_phi_mux_fw_0_1_0_0_1_0_phi_fu_93891_p4 = fw_0_1_0_0_1_0_reg_93887; + +assign ap_phi_mux_fw_0_1_0_1_0_0_phi_fu_94187_p4 = fw_0_1_0_1_0_0_reg_94183; + +assign ap_phi_mux_fw_0_1_0_1_1_0_phi_fu_94467_p4 = fw_0_1_0_1_1_0_reg_94463; + +assign ap_phi_mux_fw_0_1_1_0_0_0_phi_fu_94793_p4 = fw_0_1_1_0_0_0_reg_94789; + +assign ap_phi_mux_fw_0_1_1_0_1_0_phi_fu_95077_p4 = fw_0_1_1_0_1_0_reg_95073; + +assign ap_phi_mux_fw_0_1_1_1_0_0_phi_fu_95373_p4 = fw_0_1_1_1_0_0_reg_95369; + +assign ap_phi_mux_fw_0_1_1_1_1_0_phi_fu_95653_p4 = fw_0_1_1_1_1_0_reg_95649; + +assign empty_319_fu_117864_p1 = cc8_0_0_0_0_0_reg_96049[1:0]; + +assign empty_334_fu_119490_p1 = cc8_0_0_0_1_0_reg_96421[1:0]; + +assign empty_351_fu_121332_p1 = cc8_0_0_1_0_0_reg_96797[1:0]; + +assign empty_366_fu_122958_p1 = cc8_0_0_1_1_0_reg_97169[1:0]; + +assign empty_385_fu_124906_p1 = cc8_0_1_0_0_0_reg_97557[1:0]; + +assign empty_400_fu_126532_p1 = cc8_0_1_0_1_0_reg_97929[1:0]; + +assign empty_417_fu_128374_p1 = cc8_0_1_1_0_0_reg_98305[1:0]; + +assign empty_432_fu_130000_p1 = cc8_0_1_1_1_0_reg_98677[1:0]; + +assign ff4_0_0_0_0_cast42_fu_115739_p1 = ff4_0_0_0_0_reg_95953; + +assign ff4_0_0_1_0_cast39_fu_116115_p1 = ff4_0_0_1_0_reg_95965; + +assign ff4_0_1_0_0_cast36_fu_116503_p1 = ff4_0_1_0_0_reg_95989; + +assign ff4_0_1_1_0_cast33_fu_116879_p1 = ff4_0_1_1_0_reg_96001; + +assign ff7_0_0_0_0_cast29_fu_117317_p1 = ff7_0_0_0_0_reg_96037; + +assign ff7_0_0_1_0_cast21_fu_120832_p1 = ff7_0_0_1_0_reg_96785; + +assign ff7_0_1_0_0_cast13_fu_124359_p1 = ff7_0_1_0_0_reg_97545; + +assign ff7_0_1_1_0_cast5_fu_127874_p1 = ff7_0_1_1_0_reg_98293; + +assign grp_fu_102439_p0 = 65'd4908534053; + +assign grp_fu_102439_p1 = grp_fu_102439_p10; + +assign grp_fu_102439_p10 = reg_99313; + +assign grp_fu_102927_p0 = 65'd4908534053; + +assign grp_fu_102927_p1 = grp_fu_102927_p10; + +assign grp_fu_102927_p10 = reg_99313; + +assign grp_fu_103005_p0 = 65'd4908534053; + +assign grp_fu_103005_p1 = grp_fu_103005_p10; + +assign grp_fu_103005_p10 = add_ln216_24_reg_132191; + +assign grp_fu_103065_p0 = 65'd4908534053; + +assign grp_fu_103065_p1 = grp_fu_103065_p10; + +assign grp_fu_103065_p10 = add_ln216_24_reg_132191; + +assign grp_fu_103321_p0 = 65'd4908534053; + +assign grp_fu_103321_p1 = grp_fu_103321_p10; + +assign grp_fu_103321_p10 = reg_100638; + +assign grp_fu_103619_p0 = 65'd4908534053; + +assign grp_fu_103619_p1 = grp_fu_103619_p10; + +assign grp_fu_103619_p10 = reg_100638; + +assign grp_fu_103697_p0 = 65'd4908534053; + +assign grp_fu_103697_p1 = grp_fu_103697_p10; + +assign grp_fu_103697_p10 = add_ln216_56_reg_133087; + +assign grp_fu_103757_p0 = 65'd4908534053; + +assign grp_fu_103757_p1 = grp_fu_103757_p10; + +assign grp_fu_103757_p10 = add_ln216_56_reg_133087; + +assign grp_fu_104125_p0 = 65'd4908534053; + +assign grp_fu_104125_p1 = grp_fu_104125_p10; + +assign grp_fu_104125_p10 = add_ln216_88_reg_133905; + +assign grp_fu_104536_p0 = 65'd4908534053; + +assign grp_fu_104536_p1 = grp_fu_104536_p10; + +assign grp_fu_104536_p10 = add_ln216_82_reg_133894; + +assign grp_fu_104614_p0 = 65'd4908534053; + +assign grp_fu_104614_p1 = grp_fu_104614_p10; + +assign grp_fu_104614_p10 = add_ln216_57_reg_133959; + +assign grp_fu_104674_p0 = 65'd4908534053; + +assign grp_fu_104674_p1 = grp_fu_104674_p10; + +assign grp_fu_104674_p10 = add_ln216_57_reg_133959; + +assign grp_fu_104928_p0 = 65'd4908534053; + +assign grp_fu_104928_p1 = grp_fu_104928_p10; + +assign grp_fu_104928_p10 = add_ln216_100_reg_134780; + +assign grp_fu_105224_p0 = 65'd4908534053; + +assign grp_fu_105224_p1 = grp_fu_105224_p10; + +assign grp_fu_105224_p10 = add_ln216_97_reg_134769; + +assign grp_fu_105302_p0 = 65'd4908534053; + +assign grp_fu_105302_p1 = grp_fu_105302_p10; + +assign grp_fu_105302_p10 = add_ln216_76_reg_134834; + +assign grp_fu_105362_p0 = 65'd4908534053; + +assign grp_fu_105362_p1 = grp_fu_105362_p10; + +assign grp_fu_105362_p10 = add_ln216_76_reg_134834; + +assign grp_fu_105858_p0 = 65'd4908534053; + +assign grp_fu_105858_p1 = grp_fu_105858_p10; + +assign grp_fu_105858_p10 = add_ln216_75_reg_135708; + +assign grp_fu_106344_p0 = 65'd4908534053; + +assign grp_fu_106344_p1 = grp_fu_106344_p10; + +assign grp_fu_106344_p10 = add_ln216_55_reg_135697; + +assign grp_fu_106422_p0 = 65'd4908534053; + +assign grp_fu_106422_p1 = grp_fu_106422_p10; + +assign grp_fu_106422_p10 = add_ln216_27_reg_135762; + +assign grp_fu_106482_p0 = 65'd4908534053; + +assign grp_fu_106482_p1 = grp_fu_106482_p10; + +assign grp_fu_106482_p10 = add_ln216_27_reg_135762; + +assign grp_fu_106737_p0 = 65'd4908534053; + +assign grp_fu_106737_p1 = grp_fu_106737_p10; + +assign grp_fu_106737_p10 = reg_101903; + +assign grp_fu_107034_p0 = 65'd4908534053; + +assign grp_fu_107034_p1 = grp_fu_107034_p10; + +assign grp_fu_107034_p10 = reg_101903; + +assign grp_fu_107112_p0 = 65'd4908534053; + +assign grp_fu_107112_p1 = grp_fu_107112_p10; + +assign grp_fu_107112_p10 = add_ln216_59_reg_136658; + +assign grp_fu_107172_p0 = 65'd4908534053; + +assign grp_fu_107172_p1 = grp_fu_107172_p10; + +assign grp_fu_107172_p10 = add_ln216_59_reg_136658; + +assign grp_fu_107539_p0 = 65'd4908534053; + +assign grp_fu_107539_p1 = grp_fu_107539_p10; + +assign grp_fu_107539_p10 = add_ln216_94_reg_137476; + +assign grp_fu_107949_p0 = 65'd4908534053; + +assign grp_fu_107949_p1 = grp_fu_107949_p10; + +assign grp_fu_107949_p10 = add_ln216_87_reg_137465; + +assign grp_fu_108027_p0 = 65'd4908534053; + +assign grp_fu_108027_p1 = grp_fu_108027_p10; + +assign grp_fu_108027_p10 = add_ln216_62_reg_137530; + +assign grp_fu_108087_p0 = 65'd4908534053; + +assign grp_fu_108087_p1 = grp_fu_108087_p10; + +assign grp_fu_108087_p10 = add_ln216_62_reg_137530; + +assign grp_fu_108340_p0 = 65'd4908534053; + +assign grp_fu_108340_p1 = grp_fu_108340_p10; + +assign grp_fu_108340_p10 = add_ln216_103_reg_138351; + +assign grp_fu_108635_p0 = 65'd4908534053; + +assign grp_fu_108635_p1 = grp_fu_108635_p10; + +assign grp_fu_108635_p10 = add_ln216_99_reg_138340; + +assign grp_fu_108713_p0 = 65'd4908534053; + +assign grp_fu_108713_p1 = grp_fu_108713_p10; + +assign grp_fu_108713_p10 = add_ln216_78_reg_138405; + +assign grp_fu_108773_p0 = 65'd4908534053; + +assign grp_fu_108773_p1 = grp_fu_108773_p10; + +assign grp_fu_108773_p10 = add_ln216_78_reg_138405; + +assign grp_fu_109299_p0 = 65'd4908534053; + +assign grp_fu_109299_p1 = grp_fu_109299_p10; + +assign grp_fu_109299_p10 = add_ln216_72_reg_139329; + +assign grp_fu_109792_p0 = 65'd4908534053; + +assign grp_fu_109792_p1 = grp_fu_109792_p10; + +assign grp_fu_109792_p10 = add_ln216_52_reg_139318; + +assign grp_fu_109870_p0 = 65'd4908534053; + +assign grp_fu_109870_p1 = grp_fu_109870_p10; + +assign grp_fu_109870_p10 = add_ln216_26_reg_139383; + +assign grp_fu_109930_p0 = 65'd4908534053; + +assign grp_fu_109930_p1 = grp_fu_109930_p10; + +assign grp_fu_109930_p10 = add_ln216_26_reg_139383; + +assign grp_fu_110182_p0 = 65'd4908534053; + +assign grp_fu_110182_p1 = grp_fu_110182_p10; + +assign grp_fu_110182_p10 = reg_101908; + +assign grp_fu_110480_p0 = 65'd4908534053; + +assign grp_fu_110480_p1 = grp_fu_110480_p10; + +assign grp_fu_110480_p10 = reg_101908; + +assign grp_fu_110558_p0 = 65'd4908534053; + +assign grp_fu_110558_p1 = grp_fu_110558_p10; + +assign grp_fu_110558_p10 = add_ln216_58_reg_140265; + +assign grp_fu_110618_p0 = 65'd4908534053; + +assign grp_fu_110618_p1 = grp_fu_110618_p10; + +assign grp_fu_110618_p10 = add_ln216_58_reg_140265; + +assign grp_fu_110977_p0 = 65'd4908534053; + +assign grp_fu_110977_p1 = grp_fu_110977_p10; + +assign grp_fu_110977_p10 = add_ln216_93_reg_141078; + +assign grp_fu_111394_p0 = 65'd4908534053; + +assign grp_fu_111394_p1 = grp_fu_111394_p10; + +assign grp_fu_111394_p10 = add_ln216_86_reg_141067; + +assign grp_fu_111472_p0 = 65'd4908534053; + +assign grp_fu_111472_p1 = grp_fu_111472_p10; + +assign grp_fu_111472_p10 = add_ln216_61_reg_141132; + +assign grp_fu_111532_p0 = 65'd4908534053; + +assign grp_fu_111532_p1 = grp_fu_111532_p10; + +assign grp_fu_111532_p10 = add_ln216_61_reg_141132; + +assign grp_fu_111782_p0 = 65'd4908534053; + +assign grp_fu_111782_p1 = grp_fu_111782_p10; + +assign grp_fu_111782_p10 = add_ln216_102_reg_141943; + +assign grp_fu_112078_p0 = 65'd4908534053; + +assign grp_fu_112078_p1 = grp_fu_112078_p10; + +assign grp_fu_112078_p10 = add_ln216_98_reg_141932; + +assign grp_fu_112156_p0 = 65'd4908534053; + +assign grp_fu_112156_p1 = grp_fu_112156_p10; + +assign grp_fu_112156_p10 = add_ln216_77_reg_141997; + +assign grp_fu_112216_p0 = 65'd4908534053; + +assign grp_fu_112216_p1 = grp_fu_112216_p10; + +assign grp_fu_112216_p10 = add_ln216_77_reg_141997; + +assign grp_fu_112701_p0 = 65'd4908534053; + +assign grp_fu_112701_p1 = grp_fu_112701_p10; + +assign grp_fu_112701_p10 = add_ln216_80_reg_142872; + +assign grp_fu_113187_p0 = 65'd4908534053; + +assign grp_fu_113187_p1 = grp_fu_113187_p10; + +assign grp_fu_113187_p10 = add_ln216_70_reg_142861; + +assign grp_fu_113265_p0 = 65'd4908534053; + +assign grp_fu_113265_p1 = grp_fu_113265_p10; + +assign grp_fu_113265_p10 = add_ln216_36_reg_142926; + +assign grp_fu_113325_p0 = 65'd4908534053; + +assign grp_fu_113325_p1 = grp_fu_113325_p10; + +assign grp_fu_113325_p10 = add_ln216_36_reg_142926; + +assign grp_fu_113580_p0 = 65'd4908534053; + +assign grp_fu_113580_p1 = grp_fu_113580_p10; + +assign grp_fu_113580_p10 = reg_101913; + +assign grp_fu_113877_p0 = 65'd4908534053; + +assign grp_fu_113877_p1 = grp_fu_113877_p10; + +assign grp_fu_113877_p10 = reg_101913; + +assign grp_fu_113955_p0 = 65'd4908534053; + +assign grp_fu_113955_p1 = grp_fu_113955_p10; + +assign grp_fu_113955_p10 = add_ln216_65_reg_143818; + +assign grp_fu_114015_p0 = 65'd4908534053; + +assign grp_fu_114015_p1 = grp_fu_114015_p10; + +assign grp_fu_114015_p10 = add_ln216_65_reg_143818; + +assign grp_fu_114373_p0 = 65'd4908534053; + +assign grp_fu_114373_p1 = grp_fu_114373_p10; + +assign grp_fu_114373_p10 = add_ln216_96_reg_144631; + +assign grp_fu_114783_p0 = 65'd4908534053; + +assign grp_fu_114783_p1 = grp_fu_114783_p10; + +assign grp_fu_114783_p10 = add_ln216_92_reg_144620; + +assign grp_fu_114861_p0 = 65'd4908534053; + +assign grp_fu_114861_p1 = grp_fu_114861_p10; + +assign grp_fu_114861_p10 = add_ln216_68_reg_144685; + +assign grp_fu_114921_p0 = 65'd4908534053; + +assign grp_fu_114921_p1 = grp_fu_114921_p10; + +assign grp_fu_114921_p10 = add_ln216_68_reg_144685; + +assign grp_fu_115174_p0 = 65'd4908534053; + +assign grp_fu_115174_p1 = grp_fu_115174_p10; + +assign grp_fu_115174_p10 = add_ln216_104_reg_145506; + +assign grp_fu_115469_p0 = 65'd4908534053; + +assign grp_fu_115469_p1 = grp_fu_115469_p10; + +assign grp_fu_115469_p10 = add_ln216_101_reg_145495; + +assign grp_fu_115547_p0 = 65'd4908534053; + +assign grp_fu_115547_p1 = grp_fu_115547_p10; + +assign grp_fu_115547_p10 = add_ln216_79_reg_145560; + +assign grp_fu_115607_p0 = 65'd4908534053; + +assign grp_fu_115607_p1 = grp_fu_115607_p10; + +assign grp_fu_115607_p10 = add_ln216_79_reg_145560; + +assign grp_fu_117625_p0 = (fw10_0_0_0_0_0_0_0_reg_96073 + add_ln276_4_reg_148413); + +assign grp_fu_117625_p1 = 32'd28; + +assign grp_fu_117634_p0 = grp_fu_117634_p00; + +assign grp_fu_117634_p00 = add_ln276_78_reg_148584; + +assign grp_fu_117634_p1 = 65'd4908534053; + +assign grp_fu_117829_p0 = (add_ln276_4_reg_148413 + or_ln268_fu_117812_p2); + +assign grp_fu_117829_p1 = 32'd28; + +assign grp_fu_117884_p0 = grp_fu_117884_p00; + +assign grp_fu_117884_p00 = add_ln276_43_reg_148753; + +assign grp_fu_117884_p1 = 65'd4908534053; + +assign grp_fu_118041_p0 = (fw10_0_0_0_0_0_1_0_reg_96157 + add_ln276_47_reg_148762); + +assign grp_fu_118041_p1 = 32'd28; + +assign grp_fu_118050_p0 = grp_fu_118050_p00; + +assign grp_fu_118050_p00 = add_ln276_103_reg_149099; + +assign grp_fu_118050_p1 = 65'd4908534053; + +assign grp_fu_118245_p0 = (add_ln276_47_reg_148762 + or_ln268_8_fu_118228_p2); + +assign grp_fu_118245_p1 = 32'd28; + +assign grp_fu_118260_p0 = grp_fu_118260_p00; + +assign grp_fu_118260_p00 = add_ln276_104_reg_149268; + +assign grp_fu_118260_p1 = 65'd4908534053; + +assign grp_fu_118434_p0 = (fw10_0_0_0_0_1_0_0_reg_96253 + add_ln276_52_reg_149439); + +assign grp_fu_118434_p1 = 32'd28; + +assign grp_fu_118443_p0 = grp_fu_118443_p00; + +assign grp_fu_118443_p00 = add_ln276_107_reg_149610; + +assign grp_fu_118443_p1 = 65'd4908534053; + +assign grp_fu_118638_p0 = (add_ln276_52_reg_149439 + or_ln268_9_fu_118621_p2); + +assign grp_fu_118638_p1 = 32'd28; + +assign grp_fu_118682_p0 = grp_fu_118682_p00; + +assign grp_fu_118682_p00 = add_ln276_108_reg_149779; + +assign grp_fu_118682_p1 = 65'd4908534053; + +assign grp_fu_118839_p0 = (fw10_0_0_0_0_1_1_0_reg_96337 + add_ln276_114_reg_149788); + +assign grp_fu_118839_p1 = 32'd28; + +assign grp_fu_118848_p0 = grp_fu_118848_p00; + +assign grp_fu_118848_p00 = add_ln276_161_reg_150124; + +assign grp_fu_118848_p1 = 65'd4908534053; + +assign grp_fu_119043_p0 = (add_ln276_114_reg_149788 + or_ln268_24_fu_119026_p2); + +assign grp_fu_119043_p1 = 32'd28; + +assign grp_fu_119058_p0 = grp_fu_119058_p00; + +assign grp_fu_119058_p00 = add_ln276_147_reg_150293; + +assign grp_fu_119058_p1 = 65'd4908534053; + +assign grp_fu_119251_p0 = (fw10_0_0_0_1_0_0_0_reg_96445 + add_ln276_22_reg_150478); + +assign grp_fu_119251_p1 = 32'd28; + +assign grp_fu_119260_p0 = grp_fu_119260_p00; + +assign grp_fu_119260_p00 = add_ln276_89_reg_150644; + +assign grp_fu_119260_p1 = 65'd4908534053; + +assign grp_fu_119455_p0 = (add_ln276_22_reg_150478 + or_ln268_3_fu_119438_p2); + +assign grp_fu_119455_p1 = 32'd28; + +assign grp_fu_119510_p0 = grp_fu_119510_p00; + +assign grp_fu_119510_p00 = add_ln276_50_reg_150813; + +assign grp_fu_119510_p1 = 65'd4908534053; + +assign grp_fu_119666_p0 = (fw10_0_0_0_1_0_1_0_reg_96527 + add_ln276_65_reg_150822); + +assign grp_fu_119666_p1 = 32'd28; + +assign grp_fu_119675_p0 = grp_fu_119675_p00; + +assign grp_fu_119675_p00 = add_ln276_130_reg_151154; + +assign grp_fu_119675_p1 = 65'd4908534053; + +assign grp_fu_119870_p0 = (add_ln276_65_reg_150822 + or_ln268_12_fu_119853_p2); + +assign grp_fu_119870_p1 = 32'd28; + +assign grp_fu_119885_p0 = grp_fu_119885_p00; + +assign grp_fu_119885_p00 = add_ln276_112_reg_151323; + +assign grp_fu_119885_p1 = 65'd4908534053; + +assign grp_fu_120058_p0 = (fw10_0_0_0_1_1_0_0_reg_96621 + add_ln276_75_reg_151494); + +assign grp_fu_120058_p1 = 32'd28; + +assign grp_fu_120067_p0 = grp_fu_120067_p00; + +assign grp_fu_120067_p00 = add_ln276_142_reg_151660; + +assign grp_fu_120067_p1 = 65'd4908534053; + +assign grp_fu_120262_p0 = (add_ln276_75_reg_151494 + or_ln268_15_fu_120245_p2); + +assign grp_fu_120262_p1 = 32'd28; + +assign grp_fu_120306_p0 = grp_fu_120306_p00; + +assign grp_fu_120306_p00 = add_ln276_117_reg_151829; + +assign grp_fu_120306_p1 = 65'd4908534053; + +assign grp_fu_120462_p0 = (fw10_0_0_0_1_1_1_0_reg_96703 + add_ln276_127_reg_151838); + +assign grp_fu_120462_p1 = 32'd28; + +assign grp_fu_120471_p0 = grp_fu_120471_p00; + +assign grp_fu_120471_p00 = add_ln276_164_reg_152169; + +assign grp_fu_120471_p1 = 65'd4908534053; + +assign grp_fu_120666_p0 = (add_ln276_127_reg_151838 + or_ln268_27_fu_120649_p2); + +assign grp_fu_120666_p1 = 32'd28; + +assign grp_fu_120681_p0 = grp_fu_120681_p00; + +assign grp_fu_120681_p00 = add_ln276_151_reg_152338; + +assign grp_fu_120681_p1 = 65'd4908534053; + +assign grp_fu_121093_p0 = (fw10_0_0_1_0_0_0_0_reg_96821 + add_ln276_17_reg_153314); + +assign grp_fu_121093_p1 = 32'd28; + +assign grp_fu_121102_p0 = grp_fu_121102_p00; + +assign grp_fu_121102_p00 = add_ln276_85_reg_153485; + +assign grp_fu_121102_p1 = 65'd4908534053; + +assign grp_fu_121297_p0 = (add_ln276_17_reg_153314 + or_ln268_2_fu_121280_p2); + +assign grp_fu_121297_p1 = 32'd28; + +assign grp_fu_121352_p0 = grp_fu_121352_p00; + +assign grp_fu_121352_p00 = add_ln276_49_reg_153654; + +assign grp_fu_121352_p1 = 65'd4908534053; + +assign grp_fu_121509_p0 = (fw10_0_0_1_0_0_1_0_reg_96905 + add_ln276_59_reg_153663); + +assign grp_fu_121509_p1 = 32'd28; + +assign grp_fu_121518_p0 = grp_fu_121518_p00; + +assign grp_fu_121518_p00 = add_ln276_118_reg_154000; + +assign grp_fu_121518_p1 = 65'd4908534053; + +assign grp_fu_121713_p0 = (add_ln276_59_reg_153663 + or_ln268_11_fu_121696_p2); + +assign grp_fu_121713_p1 = 32'd28; + +assign grp_fu_121728_p0 = grp_fu_121728_p00; + +assign grp_fu_121728_p00 = add_ln276_111_reg_154169; + +assign grp_fu_121728_p1 = 65'd4908534053; + +assign grp_fu_121902_p0 = (fw10_0_0_1_0_1_0_0_reg_97001 + add_ln276_72_reg_154340); + +assign grp_fu_121902_p1 = 32'd28; + +assign grp_fu_121911_p0 = grp_fu_121911_p00; + +assign grp_fu_121911_p00 = add_ln276_133_reg_154511; + +assign grp_fu_121911_p1 = 65'd4908534053; + +assign grp_fu_122106_p0 = (add_ln276_72_reg_154340 + or_ln268_14_fu_122089_p2); + +assign grp_fu_122106_p1 = 32'd28; + +assign grp_fu_122150_p0 = grp_fu_122150_p00; + +assign grp_fu_122150_p00 = add_ln276_116_reg_154680; + +assign grp_fu_122150_p1 = 65'd4908534053; + +assign grp_fu_122307_p0 = (fw10_0_0_1_0_1_1_0_reg_97085 + add_ln276_125_reg_154689); + +assign grp_fu_122307_p1 = 32'd28; + +assign grp_fu_122316_p0 = grp_fu_122316_p00; + +assign grp_fu_122316_p00 = add_ln276_163_reg_155025; + +assign grp_fu_122316_p1 = 65'd4908534053; + +assign grp_fu_122511_p0 = (add_ln276_125_reg_154689 + or_ln268_26_fu_122494_p2); + +assign grp_fu_122511_p1 = 32'd28; + +assign grp_fu_122526_p0 = grp_fu_122526_p00; + +assign grp_fu_122526_p00 = add_ln276_150_reg_155194; + +assign grp_fu_122526_p1 = 65'd4908534053; + +assign grp_fu_122719_p0 = (fw10_0_0_1_1_0_0_0_reg_97193 + add_ln276_38_reg_155379); + +assign grp_fu_122719_p1 = 32'd28; + +assign grp_fu_122728_p0 = grp_fu_122728_p00; + +assign grp_fu_122728_p00 = add_ln276_99_reg_155545; + +assign grp_fu_122728_p1 = 65'd4908534053; + +assign grp_fu_122923_p0 = (add_ln276_38_reg_155379 + or_ln268_6_fu_122906_p2); + +assign grp_fu_122923_p1 = 32'd28; + +assign grp_fu_122978_p0 = grp_fu_122978_p00; + +assign grp_fu_122978_p00 = add_ln276_67_reg_155714; + +assign grp_fu_122978_p1 = 65'd4908534053; + +assign grp_fu_123134_p0 = (fw10_0_0_1_1_0_1_0_reg_97275 + add_ln276_88_reg_155723); + +assign grp_fu_123134_p1 = 32'd28; + +assign grp_fu_123143_p0 = grp_fu_123143_p00; + +assign grp_fu_123143_p00 = add_ln276_148_reg_156055; + +assign grp_fu_123143_p1 = 65'd4908534053; + +assign grp_fu_123338_p0 = (add_ln276_88_reg_155723 + or_ln268_18_fu_123321_p2); + +assign grp_fu_123338_p1 = 32'd28; + +assign grp_fu_123353_p0 = grp_fu_123353_p00; + +assign grp_fu_123353_p00 = add_ln276_123_reg_156224; + +assign grp_fu_123353_p1 = 65'd4908534053; + +assign grp_fu_123526_p0 = (fw10_0_0_1_1_1_0_0_reg_97369 + add_ln276_97_reg_156395); + +assign grp_fu_123526_p1 = 32'd28; + +assign grp_fu_123535_p0 = grp_fu_123535_p00; + +assign grp_fu_123535_p00 = add_ln276_158_reg_156561; + +assign grp_fu_123535_p1 = 65'd4908534053; + +assign grp_fu_123730_p0 = (add_ln276_97_reg_156395 + or_ln268_21_fu_123713_p2); + +assign grp_fu_123730_p1 = 32'd28; + +assign grp_fu_123774_p0 = grp_fu_123774_p00; + +assign grp_fu_123774_p00 = add_ln276_131_reg_156730; + +assign grp_fu_123774_p1 = 65'd4908534053; + +assign grp_fu_123930_p0 = (fw10_0_0_1_1_1_1_0_reg_97451 + add_ln276_140_reg_156739); + +assign grp_fu_123930_p1 = 32'd28; + +assign grp_fu_123939_p0 = grp_fu_123939_p00; + +assign grp_fu_123939_p00 = add_ln276_167_reg_157070; + +assign grp_fu_123939_p1 = 65'd4908534053; + +assign grp_fu_124134_p0 = (add_ln276_140_reg_156739 + or_ln268_30_fu_124117_p2); + +assign grp_fu_124134_p1 = 32'd28; + +assign grp_fu_124149_p0 = grp_fu_124149_p00; + +assign grp_fu_124149_p00 = add_ln276_154_reg_157239; + +assign grp_fu_124149_p1 = 65'd4908534053; + +assign grp_fu_124667_p0 = (fw10_0_1_0_0_0_0_0_reg_97581 + add_ln276_12_reg_158254); + +assign grp_fu_124667_p1 = 32'd28; + +assign grp_fu_124676_p0 = grp_fu_124676_p00; + +assign grp_fu_124676_p00 = add_ln276_82_reg_158425; + +assign grp_fu_124676_p1 = 65'd4908534053; + +assign grp_fu_124871_p0 = (add_ln276_12_reg_158254 + or_ln268_1_fu_124854_p2); + +assign grp_fu_124871_p1 = 32'd28; + +assign grp_fu_124926_p0 = grp_fu_124926_p00; + +assign grp_fu_124926_p00 = add_ln276_48_reg_158594; + +assign grp_fu_124926_p1 = 65'd4908534053; + +assign grp_fu_125083_p0 = (fw10_0_1_0_0_0_1_0_reg_97665 + add_ln276_56_reg_158603); + +assign grp_fu_125083_p1 = 32'd28; + +assign grp_fu_125092_p0 = grp_fu_125092_p00; + +assign grp_fu_125092_p00 = add_ln276_109_reg_158940; + +assign grp_fu_125092_p1 = 65'd4908534053; + +assign grp_fu_125287_p0 = (add_ln276_56_reg_158603 + or_ln268_10_fu_125270_p2); + +assign grp_fu_125287_p1 = 32'd28; + +assign grp_fu_125302_p0 = grp_fu_125302_p00; + +assign grp_fu_125302_p00 = add_ln276_110_reg_159109; + +assign grp_fu_125302_p1 = 65'd4908534053; + +assign grp_fu_125476_p0 = (fw10_0_1_0_0_1_0_0_reg_97761 + add_ln276_69_reg_159280); + +assign grp_fu_125476_p1 = 32'd28; + +assign grp_fu_125485_p0 = grp_fu_125485_p00; + +assign grp_fu_125485_p00 = add_ln276_132_reg_159451; + +assign grp_fu_125485_p1 = 65'd4908534053; + +assign grp_fu_125680_p0 = (add_ln276_69_reg_159280 + or_ln268_13_fu_125663_p2); + +assign grp_fu_125680_p1 = 32'd28; + +assign grp_fu_125724_p0 = grp_fu_125724_p00; + +assign grp_fu_125724_p00 = add_ln276_115_reg_159620; + +assign grp_fu_125724_p1 = 65'd4908534053; + +assign grp_fu_125881_p0 = (fw10_0_1_0_0_1_1_0_reg_97845 + add_ln276_122_reg_159629); + +assign grp_fu_125881_p1 = 32'd28; + +assign grp_fu_125890_p0 = grp_fu_125890_p00; + +assign grp_fu_125890_p00 = add_ln276_162_reg_159965; + +assign grp_fu_125890_p1 = 65'd4908534053; + +assign grp_fu_126085_p0 = (add_ln276_122_reg_159629 + or_ln268_25_fu_126068_p2); + +assign grp_fu_126085_p1 = 32'd28; + +assign grp_fu_126100_p0 = grp_fu_126100_p00; + +assign grp_fu_126100_p00 = add_ln276_149_reg_160134; + +assign grp_fu_126100_p1 = 65'd4908534053; + +assign grp_fu_126293_p0 = (fw10_0_1_0_1_0_0_0_reg_97953 + add_ln276_35_reg_160319); + +assign grp_fu_126293_p1 = 32'd28; + +assign grp_fu_126302_p0 = grp_fu_126302_p00; + +assign grp_fu_126302_p00 = add_ln276_95_reg_160485; + +assign grp_fu_126302_p1 = 65'd4908534053; + +assign grp_fu_126497_p0 = (add_ln276_35_reg_160319 + or_ln268_5_fu_126480_p2); + +assign grp_fu_126497_p1 = 32'd28; + +assign grp_fu_126552_p0 = grp_fu_126552_p00; + +assign grp_fu_126552_p00 = add_ln276_63_reg_160654; + +assign grp_fu_126552_p1 = 65'd4908534053; + +assign grp_fu_126708_p0 = (fw10_0_1_0_1_0_1_0_reg_98035 + add_ln276_83_reg_160663); + +assign grp_fu_126708_p1 = 32'd28; + +assign grp_fu_126717_p0 = grp_fu_126717_p00; + +assign grp_fu_126717_p00 = add_ln276_144_reg_160995; + +assign grp_fu_126717_p1 = 65'd4908534053; + +assign grp_fu_126912_p0 = (add_ln276_83_reg_160663 + or_ln268_17_fu_126895_p2); + +assign grp_fu_126912_p1 = 32'd28; + +assign grp_fu_126927_p0 = grp_fu_126927_p00; + +assign grp_fu_126927_p00 = add_ln276_120_reg_161164; + +assign grp_fu_126927_p1 = 65'd4908534053; + +assign grp_fu_127100_p0 = (fw10_0_1_0_1_1_0_0_reg_98129 + add_ln276_94_reg_161335); + +assign grp_fu_127100_p1 = 32'd28; + +assign grp_fu_127109_p0 = grp_fu_127109_p00; + +assign grp_fu_127109_p00 = add_ln276_157_reg_161501; + +assign grp_fu_127109_p1 = 65'd4908534053; + +assign grp_fu_127304_p0 = (add_ln276_94_reg_161335 + or_ln268_20_fu_127287_p2); + +assign grp_fu_127304_p1 = 32'd28; + +assign grp_fu_127348_p0 = grp_fu_127348_p00; + +assign grp_fu_127348_p00 = add_ln276_129_reg_161670; + +assign grp_fu_127348_p1 = 65'd4908534053; + +assign grp_fu_127504_p0 = (fw10_0_1_0_1_1_1_0_reg_98211 + add_ln276_138_reg_161679); + +assign grp_fu_127504_p1 = 32'd28; + +assign grp_fu_127513_p0 = grp_fu_127513_p00; + +assign grp_fu_127513_p00 = add_ln276_166_reg_162010; + +assign grp_fu_127513_p1 = 65'd4908534053; + +assign grp_fu_127708_p0 = (add_ln276_138_reg_161679 + or_ln268_29_fu_127691_p2); + +assign grp_fu_127708_p1 = 32'd28; + +assign grp_fu_127723_p0 = grp_fu_127723_p00; + +assign grp_fu_127723_p00 = add_ln276_153_reg_162179; + +assign grp_fu_127723_p1 = 65'd4908534053; + +assign grp_fu_128135_p0 = (fw10_0_1_1_0_0_0_0_reg_98329 + add_ln276_30_reg_163155); + +assign grp_fu_128135_p1 = 32'd28; + +assign grp_fu_128144_p0 = grp_fu_128144_p00; + +assign grp_fu_128144_p00 = add_ln276_92_reg_163326; + +assign grp_fu_128144_p1 = 65'd4908534053; + +assign grp_fu_128339_p0 = (add_ln276_30_reg_163155 + or_ln268_4_fu_128322_p2); + +assign grp_fu_128339_p1 = 32'd28; + +assign grp_fu_128394_p0 = grp_fu_128394_p00; + +assign grp_fu_128394_p00 = add_ln276_62_reg_163495; + +assign grp_fu_128394_p1 = 65'd4908534053; + +assign grp_fu_128551_p0 = (fw10_0_1_1_0_0_1_0_reg_98413 + add_ln276_79_reg_163504); + +assign grp_fu_128551_p1 = 32'd28; + +assign grp_fu_128560_p0 = grp_fu_128560_p00; + +assign grp_fu_128560_p00 = add_ln276_143_reg_163841; + +assign grp_fu_128560_p1 = 65'd4908534053; + +assign grp_fu_128755_p0 = (add_ln276_79_reg_163504 + or_ln268_16_fu_128738_p2); + +assign grp_fu_128755_p1 = 32'd28; + +assign grp_fu_128770_p0 = grp_fu_128770_p00; + +assign grp_fu_128770_p00 = add_ln276_119_reg_164010; + +assign grp_fu_128770_p1 = 65'd4908534053; + +assign grp_fu_128944_p0 = (fw10_0_1_1_0_1_0_0_reg_98509 + add_ln276_91_reg_164181); + +assign grp_fu_128944_p1 = 32'd28; + +assign grp_fu_128953_p0 = grp_fu_128953_p00; + +assign grp_fu_128953_p00 = add_ln276_156_reg_164352; + +assign grp_fu_128953_p1 = 65'd4908534053; + +assign grp_fu_129148_p0 = (add_ln276_91_reg_164181 + or_ln268_19_fu_129131_p2); + +assign grp_fu_129148_p1 = 32'd28; + +assign grp_fu_129192_p0 = grp_fu_129192_p00; + +assign grp_fu_129192_p00 = add_ln276_128_reg_164521; + +assign grp_fu_129192_p1 = 65'd4908534053; + +assign grp_fu_129349_p0 = (fw10_0_1_1_0_1_1_0_reg_98593 + add_ln276_136_reg_164530); + +assign grp_fu_129349_p1 = 32'd28; + +assign grp_fu_129358_p0 = grp_fu_129358_p00; + +assign grp_fu_129358_p00 = add_ln276_165_reg_164866; + +assign grp_fu_129358_p1 = 65'd4908534053; + +assign grp_fu_129553_p0 = (add_ln276_136_reg_164530 + or_ln268_28_fu_129536_p2); + +assign grp_fu_129553_p1 = 32'd28; + +assign grp_fu_129568_p0 = grp_fu_129568_p00; + +assign grp_fu_129568_p00 = add_ln276_152_reg_165035; + +assign grp_fu_129568_p1 = 65'd4908534053; + +assign grp_fu_129761_p0 = (fw10_0_1_1_1_0_0_0_reg_98701 + add_ln276_42_reg_165220); + +assign grp_fu_129761_p1 = 32'd28; + +assign grp_fu_129770_p0 = grp_fu_129770_p00; + +assign grp_fu_129770_p00 = add_ln276_102_reg_165386; + +assign grp_fu_129770_p1 = 65'd4908534053; + +assign grp_fu_129965_p0 = (add_ln276_42_reg_165220 + or_ln268_7_fu_129948_p2); + +assign grp_fu_129965_p1 = 32'd28; + +assign grp_fu_130020_p0 = grp_fu_130020_p00; + +assign grp_fu_130020_p00 = add_ln276_86_reg_165555; + +assign grp_fu_130020_p1 = 65'd4908534053; + +assign grp_fu_130176_p0 = (fw10_0_1_1_1_0_1_0_reg_98783 + add_ln276_101_reg_165564); + +assign grp_fu_130176_p1 = 32'd28; + +assign grp_fu_130185_p0 = grp_fu_130185_p00; + +assign grp_fu_130185_p00 = add_ln276_159_reg_165896; + +assign grp_fu_130185_p1 = 65'd4908534053; + +assign grp_fu_130380_p0 = (add_ln276_101_reg_165564 + or_ln268_22_fu_130363_p2); + +assign grp_fu_130380_p1 = 32'd28; + +assign grp_fu_130395_p0 = grp_fu_130395_p00; + +assign grp_fu_130395_p00 = add_ln276_134_reg_166065; + +assign grp_fu_130395_p1 = 65'd4908534053; + +assign grp_fu_130568_p0 = (fw10_0_1_1_1_1_0_0_reg_98877 + add_ln276_106_reg_166236); + +assign grp_fu_130568_p1 = 32'd28; + +assign grp_fu_130577_p0 = grp_fu_130577_p00; + +assign grp_fu_130577_p00 = add_ln276_160_reg_166402; + +assign grp_fu_130577_p1 = 65'd4908534053; + +assign grp_fu_130772_p0 = (add_ln276_106_reg_166236 + or_ln268_23_fu_130755_p2); + +assign grp_fu_130772_p1 = 32'd28; + +assign grp_fu_130816_p0 = grp_fu_130816_p00; + +assign grp_fu_130816_p00 = add_ln276_141_reg_166571; + +assign grp_fu_130816_p1 = 65'd4908534053; + +assign grp_fu_130972_p0 = (fw10_0_1_1_1_1_1_0_reg_98959 + add_ln276_146_reg_166580); + +assign grp_fu_130972_p1 = 32'd28; + +assign grp_fu_130981_p0 = grp_fu_130981_p00; + +assign grp_fu_130981_p00 = add_ln276_168_reg_166911; + +assign grp_fu_130981_p1 = 65'd4908534053; + +assign grp_fu_131176_p0 = (add_ln276_146_reg_166580 + or_ln268_31_fu_131159_p2); + +assign grp_fu_131176_p1 = 32'd28; + +assign grp_fu_131191_p0 = grp_fu_131191_p00; + +assign grp_fu_131191_p00 = add_ln276_155_reg_167080; + +assign grp_fu_131191_p1 = 65'd4908534053; + +assign grp_fu_131342_p0 = 9'd25; + +assign grp_fu_131342_p1 = grp_fu_131342_p10; + +assign grp_fu_131342_p10 = cc_0_0_0_0_reg_91195; + +assign grp_fu_131350_p0 = grp_fu_131350_p00; + +assign grp_fu_131350_p00 = or_ln204_fu_102842_p2; + +assign grp_fu_131350_p1 = 8'd25; + +assign grp_fu_131358_p0 = 9'd25; + +assign grp_fu_131358_p1 = grp_fu_131358_p10; + +assign grp_fu_131358_p10 = cc_0_0_1_0_reg_92381; + +assign grp_fu_131366_p0 = grp_fu_131366_p00; + +assign grp_fu_131366_p00 = or_ln204_2_fu_106260_p2; + +assign grp_fu_131366_p1 = 8'd25; + +assign grp_fu_131374_p0 = 9'd25; + +assign grp_fu_131374_p1 = grp_fu_131374_p10; + +assign grp_fu_131374_p10 = cc_0_1_0_0_reg_93579; + +assign grp_fu_131382_p0 = grp_fu_131382_p00; + +assign grp_fu_131382_p00 = or_ln204_1_fu_109708_p2; + +assign grp_fu_131382_p1 = 8'd25; + +assign grp_fu_131390_p0 = 9'd25; + +assign grp_fu_131390_p1 = grp_fu_131390_p10; + +assign grp_fu_131390_p10 = cc_0_1_1_0_reg_94765; + +assign grp_fu_131398_p0 = grp_fu_131398_p00; + +assign grp_fu_131398_p00 = or_ln204_3_fu_113103_p2; + +assign grp_fu_131398_p1 = 8'd25; + +assign grp_fu_131406_p0 = 16'd1200; + +assign grp_fu_131406_p1 = grp_fu_131406_p10; + +assign grp_fu_131406_p10 = ow6_0_0_0_reg_96025; + +assign grp_fu_131413_p0 = grp_fu_131413_p00; + +assign grp_fu_131413_p00 = ff7_0_0_0_0_reg_96037; + +assign grp_fu_131413_p1 = 12'd100; + +assign grp_fu_131420_p0 = 16'd1200; + +assign grp_fu_131420_p1 = grp_fu_131420_p10; + +assign grp_fu_131420_p10 = or_ln259_fu_117427_p2; + +assign grp_fu_131427_p0 = grp_fu_131427_p00; + +assign grp_fu_131427_p00 = cc8_0_0_0_0_0_reg_96049; + +assign grp_fu_131427_p1 = 9'd25; + +assign grp_fu_131435_p0 = grp_fu_131435_p00; + +assign grp_fu_131435_p00 = or_ln261_fu_117493_p2; + +assign grp_fu_131435_p1 = 12'd100; + +assign grp_fu_131442_p0 = 8'd25; + +assign grp_fu_131442_p1 = grp_fu_131442_p10; + +assign grp_fu_131442_p10 = or_ln264_fu_117868_p2; + +assign grp_fu_131450_p0 = grp_fu_131450_p00; + +assign grp_fu_131450_p00 = cc8_0_0_0_1_0_reg_96421; + +assign grp_fu_131450_p1 = 9'd25; + +assign grp_fu_131458_p0 = 8'd25; + +assign grp_fu_131458_p1 = grp_fu_131458_p10; + +assign grp_fu_131458_p10 = or_ln264_3_fu_119494_p2; + +assign grp_fu_131466_p0 = grp_fu_131466_p00; + +assign grp_fu_131466_p00 = ff7_0_0_1_0_reg_96785; + +assign grp_fu_131466_p1 = 12'd100; + +assign grp_fu_131473_p0 = grp_fu_131473_p00; + +assign grp_fu_131473_p00 = cc8_0_0_1_0_0_reg_96797; + +assign grp_fu_131473_p1 = 9'd25; + +assign grp_fu_131481_p0 = grp_fu_131481_p00; + +assign grp_fu_131481_p00 = or_ln261_2_fu_120961_p2; + +assign grp_fu_131481_p1 = 12'd100; + +assign grp_fu_131488_p0 = 8'd25; + +assign grp_fu_131488_p1 = grp_fu_131488_p10; + +assign grp_fu_131488_p10 = or_ln264_2_fu_121336_p2; + +assign grp_fu_131496_p0 = grp_fu_131496_p00; + +assign grp_fu_131496_p00 = cc8_0_0_1_1_0_reg_97169; + +assign grp_fu_131496_p1 = 9'd25; + +assign grp_fu_131504_p0 = 8'd25; + +assign grp_fu_131504_p1 = grp_fu_131504_p10; + +assign grp_fu_131504_p10 = or_ln264_6_fu_122962_p2; + +assign grp_fu_131512_p0 = 16'd1200; + +assign grp_fu_131512_p1 = grp_fu_131512_p10; + +assign grp_fu_131512_p10 = ow6_0_1_0_reg_97533; + +assign grp_fu_131519_p0 = grp_fu_131519_p00; + +assign grp_fu_131519_p00 = ff7_0_1_0_0_reg_97545; + +assign grp_fu_131519_p1 = 12'd100; + +assign grp_fu_131526_p0 = 16'd1200; + +assign grp_fu_131526_p1 = grp_fu_131526_p10; + +assign grp_fu_131526_p10 = or_ln259_1_fu_124469_p2; + +assign grp_fu_131533_p0 = grp_fu_131533_p00; + +assign grp_fu_131533_p00 = cc8_0_1_0_0_0_reg_97557; + +assign grp_fu_131533_p1 = 9'd25; + +assign grp_fu_131541_p0 = grp_fu_131541_p00; + +assign grp_fu_131541_p00 = or_ln261_1_fu_124535_p2; + +assign grp_fu_131541_p1 = 12'd100; + +assign grp_fu_131548_p0 = 8'd25; + +assign grp_fu_131548_p1 = grp_fu_131548_p10; + +assign grp_fu_131548_p10 = or_ln264_1_fu_124910_p2; + +assign grp_fu_131556_p0 = grp_fu_131556_p00; + +assign grp_fu_131556_p00 = cc8_0_1_0_1_0_reg_97929; + +assign grp_fu_131556_p1 = 9'd25; + +assign grp_fu_131564_p0 = 8'd25; + +assign grp_fu_131564_p1 = grp_fu_131564_p10; + +assign grp_fu_131564_p10 = or_ln264_5_fu_126536_p2; + +assign grp_fu_131572_p0 = grp_fu_131572_p00; + +assign grp_fu_131572_p00 = ff7_0_1_1_0_reg_98293; + +assign grp_fu_131572_p1 = 12'd100; + +assign grp_fu_131579_p0 = grp_fu_131579_p00; + +assign grp_fu_131579_p00 = cc8_0_1_1_0_0_reg_98305; + +assign grp_fu_131579_p1 = 9'd25; + +assign grp_fu_131587_p0 = grp_fu_131587_p00; + +assign grp_fu_131587_p00 = or_ln261_3_fu_128003_p2; + +assign grp_fu_131587_p1 = 12'd100; + +assign grp_fu_131594_p0 = 8'd25; + +assign grp_fu_131594_p1 = grp_fu_131594_p10; + +assign grp_fu_131594_p10 = or_ln264_4_fu_128378_p2; + +assign grp_fu_131602_p0 = grp_fu_131602_p00; + +assign grp_fu_131602_p00 = cc8_0_1_1_1_0_reg_98677; + +assign grp_fu_131602_p1 = 9'd25; + +assign grp_fu_131610_p0 = 8'd25; + +assign grp_fu_131610_p1 = grp_fu_131610_p10; + +assign grp_fu_131610_p10 = or_ln264_7_fu_130004_p2; + +assign grp_fu_99041_p2 = (add_ln216_4_reg_131776 + grp_fu_99041_p1); + +assign grp_fu_99047_p0 = (add_ln216_4_reg_131776 + grp_fu_99041_p1); + +assign grp_fu_99047_p1 = 32'd28; + +assign grp_fu_99053_p1 = 32'd28; + +assign grp_fu_99058_p2 = (add_ln216_29_reg_132549 + grp_fu_99058_p1); + +assign grp_fu_99064_p0 = (add_ln216_29_reg_132549 + grp_fu_99058_p1); + +assign grp_fu_99064_p1 = 32'd28; + +assign grp_fu_99070_p1 = 32'd28; + +assign grp_fu_99075_p2 = (add_ln216_32_reg_133543 + grp_fu_99075_p1); + +assign grp_fu_99081_p0 = (add_ln216_32_reg_133543 + grp_fu_99075_p1); + +assign grp_fu_99081_p1 = 32'd28; + +assign grp_fu_99087_p1 = 32'd28; + +assign grp_fu_99092_p2 = (add_ln216_63_reg_134312 + grp_fu_99092_p1); + +assign grp_fu_99098_p0 = (add_ln216_63_reg_134312 + grp_fu_99092_p1); + +assign grp_fu_99098_p1 = 32'd28; + +assign grp_fu_99104_p1 = 32'd28; + +assign grp_fu_99109_p2 = (add_ln216_16_reg_135335 + grp_fu_99109_p1); + +assign grp_fu_99115_p0 = (add_ln216_16_reg_135335 + grp_fu_99109_p1); + +assign grp_fu_99115_p1 = 32'd28; + +assign grp_fu_99121_p1 = 32'd28; + +assign grp_fu_99126_p2 = (add_ln216_41_reg_136120 + grp_fu_99126_p1); + +assign grp_fu_99132_p0 = (add_ln216_41_reg_136120 + grp_fu_99126_p1); + +assign grp_fu_99132_p1 = 32'd28; + +assign grp_fu_99138_p1 = 32'd28; + +assign grp_fu_99143_p2 = (add_ln216_47_reg_137114 + grp_fu_99143_p1); + +assign grp_fu_99149_p0 = (add_ln216_47_reg_137114 + grp_fu_99143_p1); + +assign grp_fu_99149_p1 = 32'd28; + +assign grp_fu_99155_p1 = 32'd28; + +assign grp_fu_99160_p2 = (add_ln216_71_reg_137883 + grp_fu_99160_p1); + +assign grp_fu_99166_p0 = (add_ln216_71_reg_137883 + grp_fu_99160_p1); + +assign grp_fu_99166_p1 = 32'd28; + +assign grp_fu_99172_p1 = 32'd28; + +assign grp_fu_99177_p2 = (add_ln216_11_reg_138956 + grp_fu_99177_p1); + +assign grp_fu_99183_p0 = (add_ln216_11_reg_138956 + grp_fu_99177_p1); + +assign grp_fu_99183_p1 = 32'd28; + +assign grp_fu_99189_p1 = 32'd28; + +assign grp_fu_99194_p2 = (add_ln216_37_reg_139735 + grp_fu_99194_p1); + +assign grp_fu_99200_p0 = (add_ln216_37_reg_139735 + grp_fu_99194_p1); + +assign grp_fu_99200_p1 = 32'd28; + +assign grp_fu_99206_p1 = 32'd28; + +assign grp_fu_99211_p2 = (add_ln216_44_reg_140710 + grp_fu_99211_p1); + +assign grp_fu_99217_p0 = (add_ln216_44_reg_140710 + grp_fu_99211_p1); + +assign grp_fu_99217_p1 = 32'd28; + +assign grp_fu_99223_p1 = 32'd28; + +assign grp_fu_99228_p2 = (add_ln216_67_reg_141479 + grp_fu_99228_p1); + +assign grp_fu_99234_p0 = (add_ln216_67_reg_141479 + grp_fu_99228_p1); + +assign grp_fu_99234_p1 = 32'd28; + +assign grp_fu_99240_p1 = 32'd28; + +assign grp_fu_99245_p2 = (add_ln216_22_reg_142499 + grp_fu_99245_p1); + +assign grp_fu_99251_p0 = (add_ln216_22_reg_142499 + grp_fu_99245_p1); + +assign grp_fu_99251_p1 = 32'd28; + +assign grp_fu_99257_p1 = 32'd28; + +assign grp_fu_99262_p2 = (add_ln216_51_reg_143284 + grp_fu_99262_p1); + +assign grp_fu_99268_p0 = (add_ln216_51_reg_143284 + grp_fu_99262_p1); + +assign grp_fu_99268_p1 = 32'd28; + +assign grp_fu_99274_p1 = 32'd28; + +assign grp_fu_99279_p2 = (add_ln216_54_reg_144263 + grp_fu_99279_p1); + +assign grp_fu_99285_p0 = (add_ln216_54_reg_144263 + grp_fu_99279_p1); + +assign grp_fu_99285_p1 = 32'd28; + +assign grp_fu_99291_p1 = 32'd28; + +assign grp_fu_99296_p2 = (add_ln216_74_reg_145038 + grp_fu_99296_p1); + +assign grp_fu_99302_p0 = (add_ln216_74_reg_145038 + grp_fu_99296_p1); + +assign grp_fu_99302_p1 = 32'd28; + +assign grp_fu_99308_p1 = 32'd28; + +assign icmp_ln199_fu_101926_p2 = ((oh_0_0_reg_91149 == 4'd14) ? 1'b1 : 1'b0); + +assign icmp_ln201_1_fu_108832_p2 = ((ow_0_1_0_reg_93545 == 4'd14) ? 1'b1 : 1'b0); + +assign icmp_ln201_fu_101946_p2 = ((ow_0_0_0_reg_91161 == 4'd14) ? 1'b1 : 1'b0); + +assign icmp_ln203_1_fu_108860_p2 = ((ff_0_1_0_reg_93557 == 4'd12) ? 1'b1 : 1'b0); + +assign icmp_ln203_2_fu_105423_p2 = ((ff_0_0_1_reg_92359 == 4'd12) ? 1'b1 : 1'b0); + +assign icmp_ln203_3_fu_112277_p2 = ((ff_0_1_1_reg_94743 == 4'd12) ? 1'b1 : 1'b0); + +assign icmp_ln203_fu_101988_p2 = ((ff_0_0_0_reg_91173 == 4'd12) ? 1'b1 : 1'b0); + +assign icmp_ln204_1_fu_108914_p2 = ((cc_0_1_0_0_reg_93579 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln204_2_fu_105463_p2 = ((cc_0_0_1_0_reg_92381 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln204_3_fu_112317_p2 = ((cc_0_1_1_0_reg_94765 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln204_fu_102042_p2 = ((cc_0_0_0_0_reg_91195 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln206_1_fu_109593_p2 = ((or_ln206_1_fu_109587_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln206_2_fu_106151_p2 = ((or_ln206_2_fu_106145_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln206_3_fu_112994_p2 = ((or_ln206_3_fu_112988_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln206_4_fu_104418_p2 = ((or_ln206_4_fu_104412_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln206_5_fu_111270_p2 = ((or_ln206_5_fu_111264_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln206_6_fu_107831_p2 = ((or_ln206_6_fu_107825_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln206_7_fu_114665_p2 = ((or_ln206_7_fu_114659_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln206_fu_102733_p2 = ((or_ln206_fu_102727_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_10_fu_113665_p2 = ((or_ln208_10_fu_113659_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_11_fu_114458_p2 = ((or_ln208_11_fu_114452_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_12_fu_105013_p2 = ((or_ln208_12_fu_105007_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_13_fu_111867_p2 = ((or_ln208_13_fu_111861_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_14_fu_108425_p2 = ((or_ln208_14_fu_108419_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_15_fu_115259_p2 = ((or_ln208_15_fu_115253_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_1_fu_109384_p2 = ((or_ln208_1_fu_109378_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_2_fu_105943_p2 = ((or_ln208_2_fu_105937_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_3_fu_112786_p2 = ((or_ln208_3_fu_112780_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_4_fu_103406_p2 = ((or_ln208_4_fu_103400_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_5_fu_104210_p2 = ((or_ln208_5_fu_104204_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_6_fu_110267_p2 = ((or_ln208_6_fu_110261_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_7_fu_106822_p2 = ((or_ln208_7_fu_106816_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_8_fu_111062_p2 = ((or_ln208_8_fu_111056_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_9_fu_107624_p2 = ((or_ln208_9_fu_107618_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_fu_102524_p2 = ((or_ln208_fu_102518_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln223_100_fu_113446_p2 = ((tmp_335_fu_113436_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_101_fu_114225_p2 = ((tmp_343_fu_114215_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_102_fu_114241_p2 = ((tmp_344_fu_114231_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_103_fu_103462_p2 = ((tmp_368_fu_103452_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_104_fu_103478_p2 = ((tmp_369_fu_103468_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_105_fu_104463_p2 = ((tmp_374_fu_104453_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_106_fu_104479_p2 = ((tmp_375_fu_104469_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_107_fu_104266_p2 = ((tmp_376_fu_104256_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_108_fu_104282_p2 = ((tmp_377_fu_104272_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_109_fu_110323_p2 = ((tmp_383_fu_110313_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_110_fu_110339_p2 = ((tmp_384_fu_110329_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_111_fu_106878_p2 = ((tmp_385_fu_106868_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_112_fu_106894_p2 = ((tmp_386_fu_106884_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_113_fu_111315_p2 = ((tmp_389_fu_111305_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_114_fu_111331_p2 = ((tmp_390_fu_111321_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_115_fu_111118_p2 = ((tmp_391_fu_111108_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_116_fu_111134_p2 = ((tmp_392_fu_111124_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_117_fu_107876_p2 = ((tmp_394_fu_107866_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_118_fu_107892_p2 = ((tmp_395_fu_107882_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_119_fu_107680_p2 = ((tmp_396_fu_107670_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_120_fu_107696_p2 = ((tmp_397_fu_107686_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_121_fu_104779_p2 = ((tmp_399_fu_104769_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_122_fu_104795_p2 = ((tmp_400_fu_104785_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_123_fu_113721_p2 = ((tmp_406_fu_113711_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_124_fu_113737_p2 = ((tmp_407_fu_113727_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_125_fu_114710_p2 = ((tmp_413_fu_114700_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_126_fu_114726_p2 = ((tmp_414_fu_114716_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_127_fu_114514_p2 = ((tmp_415_fu_114504_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_128_fu_114530_p2 = ((tmp_416_fu_114520_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_129_fu_111633_p2 = ((tmp_418_fu_111623_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_130_fu_111649_p2 = ((tmp_419_fu_111639_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_131_fu_108192_p2 = ((tmp_421_fu_108182_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_132_fu_108208_p2 = ((tmp_422_fu_108198_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_133_fu_115026_p2 = ((tmp_436_fu_115016_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_134_fu_115042_p2 = ((tmp_437_fu_115032_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_135_fu_105069_p2 = ((tmp_449_fu_105059_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_136_fu_105085_p2 = ((tmp_450_fu_105075_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_137_fu_111923_p2 = ((tmp_452_fu_111913_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_138_fu_111939_p2 = ((tmp_453_fu_111929_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_139_fu_108481_p2 = ((tmp_454_fu_108471_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_140_fu_108497_p2 = ((tmp_455_fu_108487_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_141_fu_115315_p2 = ((tmp_459_fu_115305_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_142_fu_115331_p2 = ((tmp_460_fu_115321_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_48_fu_102149_p2 = ((tmp_242_fu_102139_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_49_fu_109005_p2 = ((tmp_243_fu_108995_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_50_fu_109021_p2 = ((tmp_244_fu_109011_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_51_fu_105554_p2 = ((tmp_245_fu_105544_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_52_fu_105570_p2 = ((tmp_246_fu_105560_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_53_fu_102288_p2 = ((tmp_247_fu_102278_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_54_fu_102304_p2 = ((tmp_248_fu_102294_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_55_fu_112408_p2 = ((tmp_250_fu_112398_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_56_fu_112424_p2 = ((tmp_251_fu_112414_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_57_fu_109149_p2 = ((tmp_252_fu_109139_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_58_fu_109165_p2 = ((tmp_253_fu_109155_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_59_fu_105709_p2 = ((tmp_254_fu_105699_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_60_fu_105725_p2 = ((tmp_255_fu_105715_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_61_fu_112552_p2 = ((tmp_259_fu_112542_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_62_fu_112568_p2 = ((tmp_260_fu_112558_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_63_fu_102778_p2 = ((tmp_270_fu_102768_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_64_fu_102794_p2 = ((tmp_271_fu_102784_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_65_fu_102580_p2 = ((tmp_272_fu_102570_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_66_fu_102596_p2 = ((tmp_273_fu_102586_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_67_fu_103823_p2 = ((tmp_277_fu_103813_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_68_fu_103839_p2 = ((tmp_278_fu_103829_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_69_fu_109638_p2 = ((tmp_283_fu_109628_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_70_fu_109654_p2 = ((tmp_284_fu_109644_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_71_fu_109440_p2 = ((tmp_285_fu_109430_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_72_fu_109456_p2 = ((tmp_286_fu_109446_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_73_fu_106196_p2 = ((tmp_287_fu_106186_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_74_fu_106212_p2 = ((tmp_288_fu_106202_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_75_fu_105999_p2 = ((tmp_289_fu_105989_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_76_fu_106015_p2 = ((tmp_290_fu_106005_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_77_fu_103170_p2 = ((tmp_291_fu_103160_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_78_fu_103186_p2 = ((tmp_292_fu_103176_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_79_fu_110684_p2 = ((tmp_294_fu_110674_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_80_fu_110700_p2 = ((tmp_295_fu_110690_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_81_fu_107238_p2 = ((tmp_297_fu_107228_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_82_fu_107254_p2 = ((tmp_298_fu_107244_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_83_fu_103976_p2 = ((tmp_300_fu_103966_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_84_fu_103992_p2 = ((tmp_301_fu_103982_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_85_fu_113039_p2 = ((tmp_308_fu_113029_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_86_fu_113055_p2 = ((tmp_309_fu_113045_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_87_fu_112842_p2 = ((tmp_310_fu_112832_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_88_fu_112858_p2 = ((tmp_311_fu_112848_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_89_fu_110031_p2 = ((tmp_312_fu_110021_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_90_fu_110047_p2 = ((tmp_313_fu_110037_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_91_fu_106587_p2 = ((tmp_314_fu_106577_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_92_fu_106603_p2 = ((tmp_315_fu_106593_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_93_fu_114081_p2 = ((tmp_318_fu_114071_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_94_fu_114097_p2 = ((tmp_319_fu_114087_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_95_fu_110828_p2 = ((tmp_321_fu_110818_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_96_fu_110844_p2 = ((tmp_322_fu_110834_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_97_fu_107391_p2 = ((tmp_325_fu_107381_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_98_fu_107407_p2 = ((tmp_326_fu_107397_p4 != 28'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_99_fu_113430_p2 = ((tmp_334_fu_113420_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_fu_102133_p2 = ((tmp_241_fu_102123_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln244_fu_115662_p2 = ((oh2_0_0_reg_95929 == 4'd14) ? 1'b1 : 1'b0); + +assign icmp_ln246_1_fu_116448_p2 = ((ow3_0_1_0_reg_95977 == 4'd14) ? 1'b1 : 1'b0); + +assign icmp_ln246_fu_115674_p2 = ((ow3_0_0_0_reg_95941 == 4'd14) ? 1'b1 : 1'b0); + +assign icmp_ln248_1_fu_116507_p2 = ((ff4_0_1_0_0_reg_95989 == 4'd12) ? 1'b1 : 1'b0); + +assign icmp_ln248_2_fu_116119_p2 = ((ff4_0_0_1_0_reg_95965 == 4'd12) ? 1'b1 : 1'b0); + +assign icmp_ln248_3_fu_116883_p2 = ((ff4_0_1_1_0_reg_96001 == 4'd12) ? 1'b1 : 1'b0); + +assign icmp_ln248_fu_115743_p2 = ((ff4_0_0_0_0_reg_95953 == 4'd12) ? 1'b1 : 1'b0); + +assign icmp_ln257_fu_117220_p2 = ((oh5_0_0_reg_96013 == 4'd14) ? 1'b1 : 1'b0); + +assign icmp_ln259_1_fu_124304_p2 = ((ow6_0_1_0_reg_97533 == 4'd14) ? 1'b1 : 1'b0); + +assign icmp_ln259_fu_117242_p2 = ((ow6_0_0_0_reg_96025 == 4'd14) ? 1'b1 : 1'b0); + +assign icmp_ln261_1_fu_124367_p2 = ((ff7_0_1_0_0_reg_97545 == 4'd12) ? 1'b1 : 1'b0); + +assign icmp_ln261_2_fu_120840_p2 = ((ff7_0_0_1_0_reg_96785 == 4'd12) ? 1'b1 : 1'b0); + +assign icmp_ln261_3_fu_127882_p2 = ((ff7_0_1_1_0_reg_98293 == 4'd12) ? 1'b1 : 1'b0); + +assign icmp_ln261_fu_117325_p2 = ((ff7_0_0_0_0_reg_96037 == 4'd12) ? 1'b1 : 1'b0); + +assign icmp_ln264_1_fu_124526_p2 = ((cc8_0_1_0_0_0_reg_97557 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln264_2_fu_120952_p2 = ((cc8_0_0_1_0_0_reg_96797 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln264_3_fu_119214_p2 = ((cc8_0_0_0_1_0_reg_96421 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln264_4_fu_127994_p2 = ((cc8_0_1_1_0_0_reg_98305 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln264_5_fu_126256_p2 = ((cc8_0_1_0_1_0_reg_97929 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln264_6_fu_122682_p2 = ((cc8_0_0_1_1_0_reg_97169 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln264_7_fu_129724_p2 = ((cc8_0_1_1_1_0_reg_98677 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln264_fu_117484_p2 = ((cc8_0_0_0_0_0_reg_96049 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln266_10_fu_122118_p2 = ((or_ln266_10_fu_122112_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_11_fu_120274_p2 = ((or_ln266_11_fu_120268_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_12_fu_129160_p2 = ((or_ln266_12_fu_129154_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_13_fu_127316_p2 = ((or_ln266_13_fu_127310_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_14_fu_123742_p2 = ((or_ln266_14_fu_123736_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_15_fu_130784_p2 = ((or_ln266_15_fu_130778_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_1_fu_124883_p2 = ((or_ln266_1_fu_124877_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_2_fu_121309_p2 = ((or_ln266_2_fu_121303_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_3_fu_119467_p2 = ((or_ln266_3_fu_119461_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_4_fu_128351_p2 = ((or_ln266_4_fu_128345_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_5_fu_126509_p2 = ((or_ln266_5_fu_126503_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_6_fu_122935_p2 = ((or_ln266_6_fu_122929_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_7_fu_129977_p2 = ((or_ln266_7_fu_129971_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_8_fu_118650_p2 = ((or_ln266_8_fu_118644_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_9_fu_125692_p2 = ((or_ln266_9_fu_125686_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_fu_117841_p2 = ((or_ln266_fu_117835_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_10_fu_125276_p2 = ((or_ln268_10_fu_125270_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_11_fu_121702_p2 = ((or_ln268_11_fu_121696_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_12_fu_119859_p2 = ((or_ln268_12_fu_119853_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_13_fu_125669_p2 = ((or_ln268_13_fu_125663_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_14_fu_122095_p2 = ((or_ln268_14_fu_122089_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_15_fu_120251_p2 = ((or_ln268_15_fu_120245_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_16_fu_128744_p2 = ((or_ln268_16_fu_128738_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_17_fu_126901_p2 = ((or_ln268_17_fu_126895_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_18_fu_123327_p2 = ((or_ln268_18_fu_123321_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_19_fu_129137_p2 = ((or_ln268_19_fu_129131_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_1_fu_124860_p2 = ((or_ln268_1_fu_124854_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_20_fu_127293_p2 = ((or_ln268_20_fu_127287_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_21_fu_123719_p2 = ((or_ln268_21_fu_123713_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_22_fu_130369_p2 = ((or_ln268_22_fu_130363_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_23_fu_130761_p2 = ((or_ln268_23_fu_130755_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_24_fu_119032_p2 = ((or_ln268_24_fu_119026_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_25_fu_126074_p2 = ((or_ln268_25_fu_126068_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_26_fu_122500_p2 = ((or_ln268_26_fu_122494_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_27_fu_120655_p2 = ((or_ln268_27_fu_120649_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_28_fu_129542_p2 = ((or_ln268_28_fu_129536_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_29_fu_127697_p2 = ((or_ln268_29_fu_127691_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_2_fu_121286_p2 = ((or_ln268_2_fu_121280_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_30_fu_124123_p2 = ((or_ln268_30_fu_124117_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_31_fu_131165_p2 = ((or_ln268_31_fu_131159_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_3_fu_119444_p2 = ((or_ln268_3_fu_119438_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_4_fu_128328_p2 = ((or_ln268_4_fu_128322_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_5_fu_126486_p2 = ((or_ln268_5_fu_126480_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_6_fu_122912_p2 = ((or_ln268_6_fu_122906_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_7_fu_129954_p2 = ((or_ln268_7_fu_129948_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_8_fu_118234_p2 = ((or_ln268_8_fu_118228_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_9_fu_118627_p2 = ((or_ln268_9_fu_118621_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_fu_117818_p2 = ((or_ln268_fu_117812_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign mul_ln1118_10_fu_109313_p0 = reg_100634; + +assign mul_ln1118_10_fu_109313_p1 = phi_ln1116_1_reg_93615; + +assign mul_ln1118_10_fu_109313_p2 = ((mul_ln1118_10_fu_109313_p0) * (mul_ln1118_10_fu_109313_p1)); + +assign mul_ln1118_11_fu_105872_p0 = reg_100634; + +assign mul_ln1118_11_fu_105872_p1 = phi_ln1116_2_reg_92417; + +assign mul_ln1118_11_fu_105872_p2 = ((mul_ln1118_11_fu_105872_p0) * (mul_ln1118_11_fu_105872_p1)); + +assign mul_ln1118_12_fu_112715_p0 = reg_100634; + +assign mul_ln1118_12_fu_112715_p1 = phi_ln1116_3_reg_94801; + +assign mul_ln1118_12_fu_112715_p2 = ((mul_ln1118_12_fu_112715_p0) * (mul_ln1118_12_fu_112715_p1)); + +assign mul_ln1118_13_fu_102986_p0 = reg_100634; + +assign mul_ln1118_13_fu_102986_p1 = phi_ln1116_4_reg_91367; + +assign mul_ln1118_13_fu_102986_p2 = ((mul_ln1118_13_fu_102986_p0) * (mul_ln1118_13_fu_102986_p1)); + +assign mul_ln1118_14_fu_109851_p0 = reg_100634; + +assign mul_ln1118_14_fu_109851_p1 = phi_ln1116_5_reg_93751; + +assign mul_ln1118_14_fu_109851_p2 = ((mul_ln1118_14_fu_109851_p0) * (mul_ln1118_14_fu_109851_p1)); + +assign mul_ln1118_15_fu_106403_p0 = reg_100634; + +assign mul_ln1118_15_fu_106403_p1 = phi_ln1116_6_reg_92553; + +assign mul_ln1118_15_fu_106403_p2 = ((mul_ln1118_15_fu_106403_p0) * (mul_ln1118_15_fu_106403_p1)); + +assign mul_ln1118_16_fu_103335_p0 = reg_100634; + +assign mul_ln1118_16_fu_103335_p1 = phi_ln1116_7_reg_91515; + +assign mul_ln1118_16_fu_103335_p2 = ((mul_ln1118_16_fu_103335_p0) * (mul_ln1118_16_fu_103335_p1)); + +assign mul_ln1118_17_fu_104139_p0 = reg_100634; + +assign mul_ln1118_17_fu_104139_p1 = phi_ln1116_8_reg_91811; + +assign mul_ln1118_17_fu_104139_p2 = ((mul_ln1118_17_fu_104139_p0) * (mul_ln1118_17_fu_104139_p1)); + +assign mul_ln1118_18_fu_113246_p0 = reg_100634; + +assign mul_ln1118_18_fu_113246_p1 = phi_ln1116_9_reg_94937; + +assign mul_ln1118_18_fu_113246_p2 = ((mul_ln1118_18_fu_113246_p0) * (mul_ln1118_18_fu_113246_p1)); + +assign mul_ln1118_19_fu_110196_p0 = reg_100634; + +assign mul_ln1118_19_fu_110196_p1 = phi_ln1116_10_reg_93899; + +assign mul_ln1118_19_fu_110196_p2 = ((mul_ln1118_19_fu_110196_p0) * (mul_ln1118_19_fu_110196_p1)); + +assign mul_ln1118_20_fu_106751_p0 = reg_100634; + +assign mul_ln1118_20_fu_106751_p1 = phi_ln1116_11_reg_92701; + +assign mul_ln1118_20_fu_106751_p2 = ((mul_ln1118_20_fu_106751_p0) * (mul_ln1118_20_fu_106751_p1)); + +assign mul_ln1118_21_fu_110991_p0 = reg_100634; + +assign mul_ln1118_21_fu_110991_p1 = phi_ln1116_12_reg_94195; + +assign mul_ln1118_21_fu_110991_p2 = ((mul_ln1118_21_fu_110991_p0) * (mul_ln1118_21_fu_110991_p1)); + +assign mul_ln1118_22_fu_107553_p0 = reg_100634; + +assign mul_ln1118_22_fu_107553_p1 = phi_ln1116_13_reg_92997; + +assign mul_ln1118_22_fu_107553_p2 = ((mul_ln1118_22_fu_107553_p0) * (mul_ln1118_22_fu_107553_p1)); + +assign mul_ln1118_23_fu_113594_p0 = reg_100634; + +assign mul_ln1118_23_fu_113594_p1 = phi_ln1116_14_reg_95085; + +assign mul_ln1118_23_fu_113594_p2 = ((mul_ln1118_23_fu_113594_p0) * (mul_ln1118_23_fu_113594_p1)); + +assign mul_ln1118_24_fu_114387_p0 = reg_100634; + +assign mul_ln1118_24_fu_114387_p1 = phi_ln1116_15_reg_95381; + +assign mul_ln1118_24_fu_114387_p2 = ((mul_ln1118_24_fu_114387_p0) * (mul_ln1118_24_fu_114387_p1)); + +assign mul_ln1118_25_fu_103678_p0 = reg_100634; + +assign mul_ln1118_25_fu_103678_p1 = phi_ln1116_16_reg_91651; + +assign mul_ln1118_25_fu_103678_p2 = ((mul_ln1118_25_fu_103678_p0) * (mul_ln1118_25_fu_103678_p1)); + +assign mul_ln1118_26_fu_104595_p0 = reg_100634; + +assign mul_ln1118_26_fu_104595_p1 = phi_ln1116_17_reg_91945; + +assign mul_ln1118_26_fu_104595_p2 = ((mul_ln1118_26_fu_104595_p0) * (mul_ln1118_26_fu_104595_p1)); + +assign mul_ln1118_27_fu_110539_p0 = reg_100634; + +assign mul_ln1118_27_fu_110539_p1 = phi_ln1116_18_reg_94035; + +assign mul_ln1118_27_fu_110539_p2 = ((mul_ln1118_27_fu_110539_p0) * (mul_ln1118_27_fu_110539_p1)); + +assign mul_ln1118_28_fu_107093_p0 = reg_100634; + +assign mul_ln1118_28_fu_107093_p1 = phi_ln1116_19_reg_92837; + +assign mul_ln1118_28_fu_107093_p2 = ((mul_ln1118_28_fu_107093_p0) * (mul_ln1118_28_fu_107093_p1)); + +assign mul_ln1118_29_fu_111453_p0 = reg_100634; + +assign mul_ln1118_29_fu_111453_p1 = phi_ln1116_20_reg_94329; + +assign mul_ln1118_29_fu_111453_p2 = ((mul_ln1118_29_fu_111453_p0) * (mul_ln1118_29_fu_111453_p1)); + +assign mul_ln1118_30_fu_108008_p0 = reg_100634; + +assign mul_ln1118_30_fu_108008_p1 = phi_ln1116_21_reg_93131; + +assign mul_ln1118_30_fu_108008_p2 = ((mul_ln1118_30_fu_108008_p0) * (mul_ln1118_30_fu_108008_p1)); + +assign mul_ln1118_31_fu_104942_p0 = reg_100634; + +assign mul_ln1118_31_fu_104942_p1 = phi_ln1116_22_reg_92091; + +assign mul_ln1118_31_fu_104942_p2 = ((mul_ln1118_31_fu_104942_p0) * (mul_ln1118_31_fu_104942_p1)); + +assign mul_ln1118_32_fu_113936_p0 = reg_100634; + +assign mul_ln1118_32_fu_113936_p1 = phi_ln1116_23_reg_95221; + +assign mul_ln1118_32_fu_113936_p2 = ((mul_ln1118_32_fu_113936_p0) * (mul_ln1118_32_fu_113936_p1)); + +assign mul_ln1118_33_fu_114842_p0 = reg_100634; + +assign mul_ln1118_33_fu_114842_p1 = phi_ln1116_24_reg_95515; + +assign mul_ln1118_33_fu_114842_p2 = ((mul_ln1118_33_fu_114842_p0) * (mul_ln1118_33_fu_114842_p1)); + +assign mul_ln1118_34_fu_111796_p0 = reg_100634; + +assign mul_ln1118_34_fu_111796_p1 = phi_ln1116_25_reg_94475; + +assign mul_ln1118_34_fu_111796_p2 = ((mul_ln1118_34_fu_111796_p0) * (mul_ln1118_34_fu_111796_p1)); + +assign mul_ln1118_35_fu_108354_p0 = reg_100634; + +assign mul_ln1118_35_fu_108354_p1 = phi_ln1116_26_reg_93277; + +assign mul_ln1118_35_fu_108354_p2 = ((mul_ln1118_35_fu_108354_p0) * (mul_ln1118_35_fu_108354_p1)); + +assign mul_ln1118_36_fu_115188_p0 = reg_100634; + +assign mul_ln1118_36_fu_115188_p1 = phi_ln1116_27_reg_95661; + +assign mul_ln1118_36_fu_115188_p2 = ((mul_ln1118_36_fu_115188_p0) * (mul_ln1118_36_fu_115188_p1)); + +assign mul_ln1118_37_fu_105283_p0 = reg_100634; + +assign mul_ln1118_37_fu_105283_p1 = phi_ln1116_28_reg_92225; + +assign mul_ln1118_37_fu_105283_p2 = ((mul_ln1118_37_fu_105283_p0) * (mul_ln1118_37_fu_105283_p1)); + +assign mul_ln1118_38_fu_112137_p0 = reg_100634; + +assign mul_ln1118_38_fu_112137_p1 = phi_ln1116_29_reg_94609; + +assign mul_ln1118_38_fu_112137_p2 = ((mul_ln1118_38_fu_112137_p0) * (mul_ln1118_38_fu_112137_p1)); + +assign mul_ln1118_39_fu_108694_p0 = reg_100634; + +assign mul_ln1118_39_fu_108694_p1 = phi_ln1116_30_reg_93411; + +assign mul_ln1118_39_fu_108694_p2 = ((mul_ln1118_39_fu_108694_p0) * (mul_ln1118_39_fu_108694_p1)); + +assign mul_ln1118_40_fu_115528_p0 = reg_100634; + +assign mul_ln1118_40_fu_115528_p1 = phi_ln1116_31_reg_95795; + +assign mul_ln1118_40_fu_115528_p2 = ((mul_ln1118_40_fu_115528_p0) * (mul_ln1118_40_fu_115528_p1)); + +assign mul_ln1118_fu_102453_p0 = reg_100634; + +assign mul_ln1118_fu_102453_p1 = phi_ln1116_reg_91231; + +assign mul_ln1118_fu_102453_p2 = ((mul_ln1118_fu_102453_p0) * (mul_ln1118_fu_102453_p1)); + +assign mul_ln201_1_fu_101972_p0 = mul_ln201_1_fu_101972_p00; + +assign mul_ln201_1_fu_101972_p00 = or_ln199_fu_101958_p2; + +assign mul_ln201_1_fu_101972_p2 = (mul_ln201_1_fu_101972_p0 * ('h41A0)); + +assign mul_ln201_fu_101932_p0 = mul_ln201_fu_101932_p00; + +assign mul_ln201_fu_101932_p00 = oh_0_0_reg_91149; + +assign mul_ln201_fu_101932_p2 = (mul_ln201_fu_101932_p0 * ('h41A0)); + +assign mul_ln203_1_fu_108838_p0 = mul_ln203_1_fu_108838_p00; + +assign mul_ln203_1_fu_108838_p00 = ow_0_1_0_reg_93545; + +assign mul_ln203_1_fu_108838_p2 = (mul_ln203_1_fu_108838_p0 * ('h4B0)); + +assign mul_ln203_2_fu_102032_p0 = mul_ln203_2_fu_102032_p00; + +assign mul_ln203_2_fu_102032_p00 = or_ln201_fu_102018_p2; + +assign mul_ln203_2_fu_102032_p2 = (mul_ln203_2_fu_102032_p0 * ('h4B0)); + +assign mul_ln203_3_fu_108904_p0 = mul_ln203_3_fu_108904_p00; + +assign mul_ln203_3_fu_108904_p00 = or_ln201_1_fu_108890_p2; + +assign mul_ln203_3_fu_108904_p2 = (mul_ln203_3_fu_108904_p0 * ('h4B0)); + +assign mul_ln203_fu_101952_p0 = mul_ln203_fu_101952_p00; + +assign mul_ln203_fu_101952_p00 = ow_0_0_0_reg_91161; + +assign mul_ln203_fu_101952_p2 = (mul_ln203_fu_101952_p0 * ('h4B0)); + +assign mul_ln250_1_fu_115733_p0 = mul_ln250_1_fu_115733_p00; + +assign mul_ln250_1_fu_115733_p00 = or_ln244_fu_115723_p2; + +assign mul_ln250_1_fu_115733_p2 = (mul_ln250_1_fu_115733_p0 * ('hA8)); + +assign mul_ln250_fu_115668_p0 = mul_ln250_fu_115668_p00; + +assign mul_ln250_fu_115668_p00 = oh2_0_0_reg_95929; + +assign mul_ln250_fu_115668_p2 = (mul_ln250_fu_115668_p0 * ('hA8)); + +assign mul_ln279_1_fu_117311_p0 = mul_ln279_1_fu_117311_p00; + +assign mul_ln279_1_fu_117311_p00 = or_ln257_fu_117291_p2; + +assign mul_ln279_1_fu_117311_p2 = (mul_ln279_1_fu_117311_p0 * ('hA8)); + +assign mul_ln279_2_fu_117226_p0 = mul_ln279_2_fu_117226_p00; + +assign mul_ln279_2_fu_117226_p00 = oh5_0_0_reg_96013; + +assign mul_ln279_2_fu_117226_p2 = (mul_ln279_2_fu_117226_p0 * ('h41A0)); + +assign mul_ln279_3_fu_117305_p0 = mul_ln279_3_fu_117305_p00; + +assign mul_ln279_3_fu_117305_p00 = or_ln257_fu_117291_p2; + +assign mul_ln279_3_fu_117305_p2 = (mul_ln279_3_fu_117305_p0 * ('h41A0)); + +assign mul_ln279_fu_117232_p0 = mul_ln279_fu_117232_p00; + +assign mul_ln279_fu_117232_p00 = oh5_0_0_reg_96013; + +assign mul_ln279_fu_117232_p2 = (mul_ln279_fu_117232_p0 * ('hA8)); + +assign oh_0_0_cast_fu_101918_p1 = oh_0_0_reg_91149; + +assign or_ln199_fu_101958_p2 = (oh_0_0_reg_91149 | 4'd1); + +assign or_ln201_1_fu_108890_p2 = (ow_0_1_0_reg_93545 | 4'd1); + +assign or_ln201_fu_102018_p2 = (ow_0_0_0_reg_91161 | 4'd1); + +assign or_ln204_1_fu_109708_p2 = (trunc_ln221_1_reg_138913 | 2'd1); + +assign or_ln204_2_fu_106260_p2 = (trunc_ln221_2_reg_135293 | 2'd1); + +assign or_ln204_3_fu_113103_p2 = (trunc_ln221_3_reg_142456 | 2'd1); + +assign or_ln204_fu_102842_p2 = (trunc_ln221_reg_131734 | 2'd1); + +assign or_ln206_1_fu_109587_p2 = (fh_0_1_0_0_0_reg_93591 | 32'd1); + +assign or_ln206_2_fu_106145_p2 = (fh_0_0_1_0_0_reg_92393 | 32'd1); + +assign or_ln206_3_fu_112988_p2 = (fh_0_1_1_0_0_reg_94777 | 32'd1); + +assign or_ln206_4_fu_104412_p2 = (fh_0_0_0_1_0_reg_91787 | 32'd1); + +assign or_ln206_5_fu_111264_p2 = (fh_0_1_0_1_0_reg_94171 | 32'd1); + +assign or_ln206_6_fu_107825_p2 = (fh_0_0_1_1_0_reg_92973 | 32'd1); + +assign or_ln206_7_fu_114659_p2 = (fh_0_1_1_1_0_reg_95357 | 32'd1); + +assign or_ln206_fu_102727_p2 = (fh_0_0_0_0_0_reg_91207 | 32'd1); + +assign or_ln208_10_fu_113659_p2 = (fw_0_1_1_0_1_0_reg_95073 | 32'd1); + +assign or_ln208_11_fu_114452_p2 = (fw_0_1_1_1_0_0_reg_95369 | 32'd1); + +assign or_ln208_12_fu_105007_p2 = (fw_0_0_0_1_1_0_reg_92079 | 32'd1); + +assign or_ln208_13_fu_111861_p2 = (fw_0_1_0_1_1_0_reg_94463 | 32'd1); + +assign or_ln208_14_fu_108419_p2 = (fw_0_0_1_1_1_0_reg_93265 | 32'd1); + +assign or_ln208_15_fu_115253_p2 = (fw_0_1_1_1_1_0_reg_95649 | 32'd1); + +assign or_ln208_1_fu_109378_p2 = (fw_0_1_0_0_0_0_reg_93603 | 32'd1); + +assign or_ln208_2_fu_105937_p2 = (fw_0_0_1_0_0_0_reg_92405 | 32'd1); + +assign or_ln208_3_fu_112780_p2 = (fw_0_1_1_0_0_0_reg_94789 | 32'd1); + +assign or_ln208_4_fu_103400_p2 = (fw_0_0_0_0_1_0_reg_91503 | 32'd1); + +assign or_ln208_5_fu_104204_p2 = (fw_0_0_0_1_0_0_reg_91799 | 32'd1); + +assign or_ln208_6_fu_110261_p2 = (fw_0_1_0_0_1_0_reg_93887 | 32'd1); + +assign or_ln208_7_fu_106816_p2 = (fw_0_0_1_0_1_0_reg_92689 | 32'd1); + +assign or_ln208_8_fu_111056_p2 = (fw_0_1_0_1_0_0_reg_94183 | 32'd1); + +assign or_ln208_9_fu_107618_p2 = (fw_0_0_1_1_0_0_reg_92985 | 32'd1); + +assign or_ln208_fu_102518_p2 = (fw_0_0_0_0_0_0_reg_91219 | 32'd1); + +assign or_ln223_10_fu_103910_p2 = (icmp_ln223_68_reg_133523 | icmp_ln223_67_reg_133518); + +assign or_ln223_11_fu_109660_p2 = (icmp_ln223_70_fu_109654_p2 | icmp_ln223_69_fu_109638_p2); + +assign or_ln223_12_fu_109462_p2 = (icmp_ln223_72_fu_109456_p2 | icmp_ln223_71_fu_109440_p2); + +assign or_ln223_13_fu_106533_p2 = (icmp_ln223_74_reg_136115 | icmp_ln223_73_reg_136110); + +assign or_ln223_14_fu_106021_p2 = (icmp_ln223_76_fu_106015_p2 | icmp_ln223_75_fu_105999_p2); + +assign or_ln223_15_fu_103192_p2 = (icmp_ln223_78_fu_103186_p2 | icmp_ln223_77_fu_103170_p2); + +assign or_ln223_16_fu_110706_p2 = (icmp_ln223_80_fu_110700_p2 | icmp_ln223_79_fu_110684_p2); + +assign or_ln223_17_fu_107325_p2 = (icmp_ln223_82_reg_137094 | icmp_ln223_81_reg_137089); + +assign or_ln223_18_fu_103998_p2 = (icmp_ln223_84_fu_103992_p2 | icmp_ln223_83_fu_103976_p2); + +assign or_ln223_19_fu_113376_p2 = (icmp_ln223_86_reg_143279 | icmp_ln223_85_reg_143274); + +assign or_ln223_1_fu_109027_p2 = (icmp_ln223_50_fu_109021_p2 | icmp_ln223_49_fu_109005_p2); + +assign or_ln223_20_fu_112864_p2 = (icmp_ln223_88_fu_112858_p2 | icmp_ln223_87_fu_112842_p2); + +assign or_ln223_21_fu_110053_p2 = (icmp_ln223_90_fu_110047_p2 | icmp_ln223_89_fu_110031_p2); + +assign or_ln223_22_fu_106609_p2 = (icmp_ln223_92_fu_106603_p2 | icmp_ln223_91_fu_106587_p2); + +assign or_ln223_23_fu_114103_p2 = (icmp_ln223_94_fu_114097_p2 | icmp_ln223_93_fu_114081_p2); + +assign or_ln223_24_fu_110850_p2 = (icmp_ln223_96_fu_110844_p2 | icmp_ln223_95_fu_110828_p2); + +assign or_ln223_25_fu_107413_p2 = (icmp_ln223_98_fu_107407_p2 | icmp_ln223_97_fu_107391_p2); + +assign or_ln223_26_fu_113452_p2 = (icmp_ln223_99_fu_113430_p2 | icmp_ln223_100_fu_113446_p2); + +assign or_ln223_27_fu_114247_p2 = (icmp_ln223_102_fu_114241_p2 | icmp_ln223_101_fu_114225_p2); + +assign or_ln223_28_fu_103484_p2 = (icmp_ln223_104_fu_103478_p2 | icmp_ln223_103_fu_103462_p2); + +assign or_ln223_29_fu_104725_p2 = (icmp_ln223_106_reg_134307 | icmp_ln223_105_reg_134302); + +assign or_ln223_2_fu_105576_p2 = (icmp_ln223_52_fu_105570_p2 | icmp_ln223_51_fu_105554_p2); + +assign or_ln223_30_fu_104288_p2 = (icmp_ln223_108_fu_104282_p2 | icmp_ln223_107_fu_104266_p2); + +assign or_ln223_31_fu_110345_p2 = (icmp_ln223_110_fu_110339_p2 | icmp_ln223_109_fu_110323_p2); + +assign or_ln223_32_fu_106900_p2 = (icmp_ln223_112_fu_106894_p2 | icmp_ln223_111_fu_106878_p2); + +assign or_ln223_33_fu_111337_p2 = (icmp_ln223_114_fu_111331_p2 | icmp_ln223_113_fu_111315_p2); + +assign or_ln223_34_fu_111140_p2 = (icmp_ln223_116_fu_111134_p2 | icmp_ln223_115_fu_111118_p2); + +assign or_ln223_35_fu_108138_p2 = (icmp_ln223_118_reg_137878 | icmp_ln223_117_reg_137873); + +assign or_ln223_36_fu_107702_p2 = (icmp_ln223_120_fu_107696_p2 | icmp_ln223_119_fu_107680_p2); + +assign or_ln223_37_fu_104801_p2 = (icmp_ln223_122_fu_104795_p2 | icmp_ln223_121_fu_104779_p2); + +assign or_ln223_38_fu_113743_p2 = (icmp_ln223_124_fu_113737_p2 | icmp_ln223_123_fu_113721_p2); + +assign or_ln223_39_fu_114972_p2 = (icmp_ln223_126_reg_145033 | icmp_ln223_125_reg_145028); + +assign or_ln223_3_fu_102310_p2 = (icmp_ln223_54_fu_102304_p2 | icmp_ln223_53_fu_102288_p2); + +assign or_ln223_40_fu_114536_p2 = (icmp_ln223_128_fu_114530_p2 | icmp_ln223_127_fu_114514_p2); + +assign or_ln223_41_fu_111655_p2 = (icmp_ln223_130_fu_111649_p2 | icmp_ln223_129_fu_111633_p2); + +assign or_ln223_42_fu_108214_p2 = (icmp_ln223_132_fu_108208_p2 | icmp_ln223_131_fu_108192_p2); + +assign or_ln223_43_fu_115048_p2 = (icmp_ln223_134_fu_115042_p2 | icmp_ln223_133_fu_115026_p2); + +assign or_ln223_44_fu_105091_p2 = (icmp_ln223_136_fu_105085_p2 | icmp_ln223_135_fu_105069_p2); + +assign or_ln223_45_fu_111945_p2 = (icmp_ln223_138_fu_111939_p2 | icmp_ln223_137_fu_111923_p2); + +assign or_ln223_46_fu_108503_p2 = (icmp_ln223_140_fu_108497_p2 | icmp_ln223_139_fu_108481_p2); + +assign or_ln223_47_fu_115337_p2 = (icmp_ln223_142_fu_115331_p2 | icmp_ln223_141_fu_115315_p2); + +assign or_ln223_48_fu_102559_p2 = (trunc_ln223_4_fu_102514_p1 | 4'd1); + +assign or_ln223_49_fu_109419_p2 = (trunc_ln223_5_fu_109374_p1 | 4'd1); + +assign or_ln223_4_fu_112430_p2 = (icmp_ln223_56_fu_112424_p2 | icmp_ln223_55_fu_112408_p2); + +assign or_ln223_50_fu_105978_p2 = (trunc_ln223_6_fu_105933_p1 | 4'd1); + +assign or_ln223_51_fu_112821_p2 = (trunc_ln223_7_fu_112776_p1 | 4'd1); + +assign or_ln223_52_fu_103441_p2 = (trunc_ln223_16_fu_103396_p1 | 4'd1); + +assign or_ln223_53_fu_104245_p2 = (trunc_ln223_17_fu_104200_p1 | 4'd1); + +assign or_ln223_54_fu_110302_p2 = (trunc_ln223_18_fu_110257_p1 | 4'd1); + +assign or_ln223_55_fu_106857_p2 = (trunc_ln223_19_fu_106812_p1 | 4'd1); + +assign or_ln223_56_fu_111097_p2 = (trunc_ln223_20_fu_111052_p1 | 4'd1); + +assign or_ln223_57_fu_107659_p2 = (trunc_ln223_21_fu_107614_p1 | 4'd1); + +assign or_ln223_58_fu_113700_p2 = (trunc_ln223_22_fu_113655_p1 | 4'd1); + +assign or_ln223_59_fu_114493_p2 = (trunc_ln223_23_fu_114448_p1 | 4'd1); + +assign or_ln223_5_fu_109171_p2 = (icmp_ln223_58_fu_109165_p2 | icmp_ln223_57_fu_109149_p2); + +assign or_ln223_60_fu_105048_p2 = (trunc_ln223_28_fu_105003_p1 | 4'd1); + +assign or_ln223_61_fu_111902_p2 = (trunc_ln223_29_fu_111857_p1 | 4'd1); + +assign or_ln223_62_fu_108460_p2 = (trunc_ln223_30_fu_108415_p1 | 4'd1); + +assign or_ln223_63_fu_115294_p2 = (trunc_ln223_31_fu_115249_p1 | 4'd1); + +assign or_ln223_6_fu_105731_p2 = (icmp_ln223_60_fu_105725_p2 | icmp_ln223_59_fu_105709_p2); + +assign or_ln223_7_fu_112574_p2 = (icmp_ln223_62_fu_112568_p2 | icmp_ln223_61_fu_112552_p2); + +assign or_ln223_8_fu_103116_p2 = (icmp_ln223_64_reg_132544 | icmp_ln223_63_reg_132539); + +assign or_ln223_9_fu_102602_p2 = (icmp_ln223_66_fu_102596_p2 | icmp_ln223_65_fu_102580_p2); + +assign or_ln223_fu_102155_p2 = (icmp_ln223_fu_102133_p2 | icmp_ln223_48_fu_102149_p2); + +assign or_ln231_10_fu_102911_p3 = {{1'd1}, {or_ln231_fu_102893_p2}}; + +assign or_ln231_11_fu_103877_p4 = {{{tmp_71_fu_103867_p4}, {1'd1}}, {or_ln231_reg_132583}}; + +assign or_ln231_12_fu_109765_p3 = {{5'd17}, {or_ln231_19_fu_109759_p2}}; + +assign or_ln231_13_fu_109773_p3 = {{1'd1}, {or_ln231_19_fu_109759_p2}}; + +assign or_ln231_14_fu_106317_p3 = {{5'd17}, {or_ln231_20_fu_106311_p2}}; + +assign or_ln231_15_fu_106329_p3 = {{1'd1}, {or_ln231_20_fu_106311_p2}}; + +assign or_ln231_16_fu_107292_p4 = {{{tmp_89_fu_107282_p4}, {1'd1}}, {or_ln231_20_reg_136154}}; + +assign or_ln231_17_fu_113160_p3 = {{5'd17}, {or_ln231_21_fu_113154_p2}}; + +assign or_ln231_18_fu_113168_p3 = {{1'd1}, {or_ln231_21_fu_113154_p2}}; + +assign or_ln231_19_fu_109759_p2 = (cc_0_1_0_0_reg_93579 | 3'd1); + +assign or_ln231_1_fu_102106_p3 = {{1'd1}, {cc_0_0_0_0_reg_91195}}; + +assign or_ln231_20_fu_106311_p2 = (cc_0_0_1_0_reg_92381 | 3'd1); + +assign or_ln231_21_fu_113154_p2 = (cc_0_1_1_0_reg_94765 | 3'd1); + +assign or_ln231_2_fu_108966_p3 = {{5'd17}, {cc_0_1_0_0_reg_93579}}; + +assign or_ln231_3_fu_108974_p3 = {{1'd1}, {cc_0_1_0_0_reg_93579}}; + +assign or_ln231_4_fu_105515_p3 = {{5'd17}, {cc_0_0_1_0_reg_92381}}; + +assign or_ln231_5_fu_105527_p3 = {{1'd1}, {cc_0_0_1_0_reg_92381}}; + +assign or_ln231_6_fu_112369_p3 = {{5'd17}, {cc_0_1_1_0_reg_94765}}; + +assign or_ln231_7_fu_112377_p3 = {{1'd1}, {cc_0_1_1_0_reg_94765}}; + +assign or_ln231_8_fu_102237_p4 = {{{tmp_4_reg_131771}, {1'd1}}, {cc_0_0_0_0_reg_91195}}; + +assign or_ln231_9_fu_102899_p3 = {{5'd17}, {or_ln231_fu_102893_p2}}; + +assign or_ln231_fu_102893_p2 = (cc_0_0_0_0_reg_91195 | 3'd1); + +assign or_ln231_s_fu_105658_p4 = {{{tmp_5_reg_135330}, {1'd1}}, {cc_0_0_1_0_reg_92381}}; + +assign or_ln244_fu_115723_p2 = (oh2_0_0_reg_95929 | 4'd1); + +assign or_ln246_1_fu_116649_p2 = (ow3_0_1_0_reg_95977 | 4'd1); + +assign or_ln246_fu_115885_p2 = (ow3_0_0_0_reg_95941 | 4'd1); + +assign or_ln248_1_fu_116698_p2 = (ff4_0_1_0_0_reg_95989 | 4'd1); + +assign or_ln248_2_fu_116267_p2 = (ff4_0_0_1_0_reg_95965 | 4'd1); + +assign or_ln248_3_fu_117031_p2 = (ff4_0_1_1_0_reg_96001 | 4'd1); + +assign or_ln248_fu_115934_p2 = (ff4_0_0_0_0_reg_95953 | 4'd1); + +assign or_ln257_fu_117291_p2 = (oh5_0_0_reg_96013 | 4'd1); + +assign or_ln259_1_fu_124469_p2 = (ow6_0_1_0_reg_97533 | 4'd1); + +assign or_ln259_fu_117427_p2 = (ow6_0_0_0_reg_96025 | 4'd1); + +assign or_ln261_1_fu_124535_p2 = (ff7_0_1_0_0_reg_97545 | 4'd1); + +assign or_ln261_2_fu_120961_p2 = (ff7_0_0_1_0_reg_96785 | 4'd1); + +assign or_ln261_3_fu_128003_p2 = (ff7_0_1_1_0_reg_98293 | 4'd1); + +assign or_ln261_fu_117493_p2 = (ff7_0_0_0_0_reg_96037 | 4'd1); + +assign or_ln264_1_fu_124910_p2 = (empty_385_fu_124906_p1 | 2'd1); + +assign or_ln264_2_fu_121336_p2 = (empty_351_fu_121332_p1 | 2'd1); + +assign or_ln264_3_fu_119494_p2 = (empty_334_fu_119490_p1 | 2'd1); + +assign or_ln264_4_fu_128378_p2 = (empty_417_fu_128374_p1 | 2'd1); + +assign or_ln264_5_fu_126536_p2 = (empty_400_fu_126532_p1 | 2'd1); + +assign or_ln264_6_fu_122962_p2 = (empty_366_fu_122958_p1 | 2'd1); + +assign or_ln264_7_fu_130004_p2 = (empty_432_fu_130000_p1 | 2'd1); + +assign or_ln264_fu_117868_p2 = (empty_319_fu_117864_p1 | 2'd1); + +assign or_ln266_10_fu_122112_p2 = (fh9_0_0_1_0_1_0_reg_96989 | 32'd1); + +assign or_ln266_11_fu_120268_p2 = (fh9_0_0_0_1_1_0_reg_96609 | 32'd1); + +assign or_ln266_12_fu_129154_p2 = (fh9_0_1_1_0_1_0_reg_98497 | 32'd1); + +assign or_ln266_13_fu_127310_p2 = (fh9_0_1_0_1_1_0_reg_98117 | 32'd1); + +assign or_ln266_14_fu_123736_p2 = (fh9_0_0_1_1_1_0_reg_97357 | 32'd1); + +assign or_ln266_15_fu_130778_p2 = (fh9_0_1_1_1_1_0_reg_98865 | 32'd1); + +assign or_ln266_1_fu_124877_p2 = (fh9_0_1_0_0_0_0_reg_97569 | 32'd1); + +assign or_ln266_2_fu_121303_p2 = (fh9_0_0_1_0_0_0_reg_96809 | 32'd1); + +assign or_ln266_3_fu_119461_p2 = (fh9_0_0_0_1_0_0_reg_96433 | 32'd1); + +assign or_ln266_4_fu_128345_p2 = (fh9_0_1_1_0_0_0_reg_98317 | 32'd1); + +assign or_ln266_5_fu_126503_p2 = (fh9_0_1_0_1_0_0_reg_97941 | 32'd1); + +assign or_ln266_6_fu_122929_p2 = (fh9_0_0_1_1_0_0_reg_97181 | 32'd1); + +assign or_ln266_7_fu_129971_p2 = (fh9_0_1_1_1_0_0_reg_98689 | 32'd1); + +assign or_ln266_8_fu_118644_p2 = (fh9_0_0_0_0_1_0_reg_96241 | 32'd1); + +assign or_ln266_9_fu_125686_p2 = (fh9_0_1_0_0_1_0_reg_97749 | 32'd1); + +assign or_ln266_fu_117835_p2 = (fh9_0_0_0_0_0_0_reg_96061 | 32'd1); + +assign or_ln268_10_fu_125270_p2 = (fw10_0_1_0_0_0_1_0_reg_97665 | 32'd1); + +assign or_ln268_11_fu_121696_p2 = (fw10_0_0_1_0_0_1_0_reg_96905 | 32'd1); + +assign or_ln268_12_fu_119853_p2 = (fw10_0_0_0_1_0_1_0_reg_96527 | 32'd1); + +assign or_ln268_13_fu_125663_p2 = (fw10_0_1_0_0_1_0_0_reg_97761 | 32'd1); + +assign or_ln268_14_fu_122089_p2 = (fw10_0_0_1_0_1_0_0_reg_97001 | 32'd1); + +assign or_ln268_15_fu_120245_p2 = (fw10_0_0_0_1_1_0_0_reg_96621 | 32'd1); + +assign or_ln268_16_fu_128738_p2 = (fw10_0_1_1_0_0_1_0_reg_98413 | 32'd1); + +assign or_ln268_17_fu_126895_p2 = (fw10_0_1_0_1_0_1_0_reg_98035 | 32'd1); + +assign or_ln268_18_fu_123321_p2 = (fw10_0_0_1_1_0_1_0_reg_97275 | 32'd1); + +assign or_ln268_19_fu_129131_p2 = (fw10_0_1_1_0_1_0_0_reg_98509 | 32'd1); + +assign or_ln268_1_fu_124854_p2 = (fw10_0_1_0_0_0_0_0_reg_97581 | 32'd1); + +assign or_ln268_20_fu_127287_p2 = (fw10_0_1_0_1_1_0_0_reg_98129 | 32'd1); + +assign or_ln268_21_fu_123713_p2 = (fw10_0_0_1_1_1_0_0_reg_97369 | 32'd1); + +assign or_ln268_22_fu_130363_p2 = (fw10_0_1_1_1_0_1_0_reg_98783 | 32'd1); + +assign or_ln268_23_fu_130755_p2 = (fw10_0_1_1_1_1_0_0_reg_98877 | 32'd1); + +assign or_ln268_24_fu_119026_p2 = (fw10_0_0_0_0_1_1_0_reg_96337 | 32'd1); + +assign or_ln268_25_fu_126068_p2 = (fw10_0_1_0_0_1_1_0_reg_97845 | 32'd1); + +assign or_ln268_26_fu_122494_p2 = (fw10_0_0_1_0_1_1_0_reg_97085 | 32'd1); + +assign or_ln268_27_fu_120649_p2 = (fw10_0_0_0_1_1_1_0_reg_96703 | 32'd1); + +assign or_ln268_28_fu_129536_p2 = (fw10_0_1_1_0_1_1_0_reg_98593 | 32'd1); + +assign or_ln268_29_fu_127691_p2 = (fw10_0_1_0_1_1_1_0_reg_98211 | 32'd1); + +assign or_ln268_2_fu_121280_p2 = (fw10_0_0_1_0_0_0_0_reg_96821 | 32'd1); + +assign or_ln268_30_fu_124117_p2 = (fw10_0_0_1_1_1_1_0_reg_97451 | 32'd1); + +assign or_ln268_31_fu_131159_p2 = (fw10_0_1_1_1_1_1_0_reg_98959 | 32'd1); + +assign or_ln268_3_fu_119438_p2 = (fw10_0_0_0_1_0_0_0_reg_96445 | 32'd1); + +assign or_ln268_4_fu_128322_p2 = (fw10_0_1_1_0_0_0_0_reg_98329 | 32'd1); + +assign or_ln268_5_fu_126480_p2 = (fw10_0_1_0_1_0_0_0_reg_97953 | 32'd1); + +assign or_ln268_6_fu_122906_p2 = (fw10_0_0_1_1_0_0_0_reg_97193 | 32'd1); + +assign or_ln268_7_fu_129948_p2 = (fw10_0_1_1_1_0_0_0_reg_98701 | 32'd1); + +assign or_ln268_8_fu_118228_p2 = (fw10_0_0_0_0_0_1_0_reg_96157 | 32'd1); + +assign or_ln268_9_fu_118621_p2 = (fw10_0_0_0_0_1_0_0_reg_96253 | 32'd1); + +assign or_ln268_fu_117812_p2 = (fw10_0_0_0_0_0_0_0_reg_96073 | 32'd1); + +assign or_ln_fu_102094_p3 = {{5'd17}, {cc_0_0_0_0_reg_91195}}; + +assign ow_0_0_0_cast_fu_101938_p1 = ow_0_0_0_reg_91161; + +assign ow_0_1_0_cast_fu_108824_p1 = ow_0_1_0_reg_93545; + +assign res_0_V_d0 = acc_0_V_q0; + +assign res_100_V_d0 = acc_36_V_q1; + +assign res_101_V_d0 = acc_37_V_q1; + +assign res_102_V_d0 = acc_38_V_q1; + +assign res_103_V_d0 = acc_39_V_q1; + +assign res_104_V_d0 = acc_40_V_q1; + +assign res_105_V_d0 = acc_41_V_q1; + +assign res_106_V_d0 = acc_42_V_q1; + +assign res_107_V_d0 = acc_43_V_q1; + +assign res_108_V_d0 = acc_44_V_q1; + +assign res_109_V_d0 = acc_45_V_q1; + +assign res_10_V_d0 = acc_10_V_q0; + +assign res_110_V_d0 = acc_46_V_q1; + +assign res_111_V_d0 = acc_47_V_q1; + +assign res_112_V_d0 = acc_48_V_q1; + +assign res_113_V_d0 = acc_49_V_q1; + +assign res_114_V_d0 = acc_50_V_q1; + +assign res_115_V_d0 = acc_51_V_q1; + +assign res_116_V_d0 = acc_52_V_q1; + +assign res_117_V_d0 = acc_53_V_q1; + +assign res_118_V_d0 = acc_54_V_q1; + +assign res_119_V_d0 = acc_55_V_q1; + +assign res_11_V_d0 = acc_11_V_q0; + +assign res_120_V_d0 = acc_56_V_q1; + +assign res_121_V_d0 = acc_57_V_q1; + +assign res_122_V_d0 = acc_58_V_q1; + +assign res_123_V_d0 = acc_59_V_q1; + +assign res_124_V_d0 = acc_60_V_q1; + +assign res_125_V_d0 = acc_61_V_q1; + +assign res_126_V_d0 = acc_62_V_q1; + +assign res_127_V_d0 = acc_63_V_q1; + +assign res_12_V_d0 = acc_12_V_q0; + +assign res_13_V_d0 = acc_13_V_q0; + +assign res_14_V_d0 = acc_14_V_q0; + +assign res_15_V_d0 = acc_15_V_q0; + +assign res_16_V_d0 = acc_16_V_q0; + +assign res_17_V_d0 = acc_17_V_q0; + +assign res_18_V_d0 = acc_18_V_q0; + +assign res_19_V_d0 = acc_19_V_q0; + +assign res_1_V_d0 = acc_1_V_q0; + +assign res_20_V_d0 = acc_20_V_q0; + +assign res_21_V_d0 = acc_21_V_q0; + +assign res_22_V_d0 = acc_22_V_q0; + +assign res_23_V_d0 = acc_23_V_q0; + +assign res_24_V_d0 = acc_24_V_q0; + +assign res_25_V_d0 = acc_25_V_q0; + +assign res_26_V_d0 = acc_26_V_q0; + +assign res_27_V_d0 = acc_27_V_q0; + +assign res_28_V_d0 = acc_28_V_q0; + +assign res_29_V_d0 = acc_29_V_q0; + +assign res_2_V_d0 = acc_2_V_q0; + +assign res_30_V_d0 = acc_30_V_q0; + +assign res_31_V_d0 = acc_31_V_q0; + +assign res_32_V_d0 = acc_32_V_q0; + +assign res_33_V_d0 = acc_33_V_q0; + +assign res_34_V_d0 = acc_34_V_q0; + +assign res_35_V_d0 = acc_35_V_q0; + +assign res_36_V_d0 = acc_36_V_q0; + +assign res_37_V_d0 = acc_37_V_q0; + +assign res_38_V_d0 = acc_38_V_q0; + +assign res_39_V_d0 = acc_39_V_q0; + +assign res_3_V_d0 = acc_3_V_q0; + +assign res_40_V_d0 = acc_40_V_q0; + +assign res_41_V_d0 = acc_41_V_q0; + +assign res_42_V_d0 = acc_42_V_q0; + +assign res_43_V_d0 = acc_43_V_q0; + +assign res_44_V_d0 = acc_44_V_q0; + +assign res_45_V_d0 = acc_45_V_q0; + +assign res_46_V_d0 = acc_46_V_q0; + +assign res_47_V_d0 = acc_47_V_q0; + +assign res_48_V_d0 = acc_48_V_q0; + +assign res_49_V_d0 = acc_49_V_q0; + +assign res_4_V_d0 = acc_4_V_q0; + +assign res_50_V_d0 = acc_50_V_q0; + +assign res_51_V_d0 = acc_51_V_q0; + +assign res_52_V_d0 = acc_52_V_q0; + +assign res_53_V_d0 = acc_53_V_q0; + +assign res_54_V_d0 = acc_54_V_q0; + +assign res_55_V_d0 = acc_55_V_q0; + +assign res_56_V_d0 = acc_56_V_q0; + +assign res_57_V_d0 = acc_57_V_q0; + +assign res_58_V_d0 = acc_58_V_q0; + +assign res_59_V_d0 = acc_59_V_q0; + +assign res_5_V_d0 = acc_5_V_q0; + +assign res_60_V_d0 = acc_60_V_q0; + +assign res_61_V_d0 = acc_61_V_q0; + +assign res_62_V_d0 = acc_62_V_q0; + +assign res_63_V_d0 = acc_63_V_q0; + +assign res_64_V_d0 = acc_0_V_q1; + +assign res_65_V_d0 = acc_1_V_q1; + +assign res_66_V_d0 = acc_2_V_q1; + +assign res_67_V_d0 = acc_3_V_q1; + +assign res_68_V_d0 = acc_4_V_q1; + +assign res_69_V_d0 = acc_5_V_q1; + +assign res_6_V_d0 = acc_6_V_q0; + +assign res_70_V_d0 = acc_6_V_q1; + +assign res_71_V_d0 = acc_7_V_q1; + +assign res_72_V_d0 = acc_8_V_q1; + +assign res_73_V_d0 = acc_9_V_q1; + +assign res_74_V_d0 = acc_10_V_q1; + +assign res_75_V_d0 = acc_11_V_q1; + +assign res_76_V_d0 = acc_12_V_q1; + +assign res_77_V_d0 = acc_13_V_q1; + +assign res_78_V_d0 = acc_14_V_q1; + +assign res_79_V_d0 = acc_15_V_q1; + +assign res_7_V_d0 = acc_7_V_q0; + +assign res_80_V_d0 = acc_16_V_q1; + +assign res_81_V_d0 = acc_17_V_q1; + +assign res_82_V_d0 = acc_18_V_q1; + +assign res_83_V_d0 = acc_19_V_q1; + +assign res_84_V_d0 = acc_20_V_q1; + +assign res_85_V_d0 = acc_21_V_q1; + +assign res_86_V_d0 = acc_22_V_q1; + +assign res_87_V_d0 = acc_23_V_q1; + +assign res_88_V_d0 = acc_24_V_q1; + +assign res_89_V_d0 = acc_25_V_q1; + +assign res_8_V_d0 = acc_8_V_q0; + +assign res_90_V_d0 = acc_26_V_q1; + +assign res_91_V_d0 = acc_27_V_q1; + +assign res_92_V_d0 = acc_28_V_q1; + +assign res_93_V_d0 = acc_29_V_q1; + +assign res_94_V_d0 = acc_30_V_q1; + +assign res_95_V_d0 = acc_31_V_q1; + +assign res_96_V_d0 = acc_32_V_q1; + +assign res_97_V_d0 = acc_33_V_q1; + +assign res_98_V_d0 = acc_34_V_q1; + +assign res_99_V_d0 = acc_35_V_q1; + +assign res_9_V_d0 = acc_9_V_q0; + +assign sext_ln1116_10_fu_110105_p1 = (trunc_ln1116_10_fu_110095_p4); + +assign sext_ln1116_11_fu_106660_p1 = (trunc_ln1116_11_fu_106650_p4); + +assign sext_ln1116_12_fu_110902_p1 = (trunc_ln1116_12_fu_110892_p4); + +assign sext_ln1116_13_fu_107464_p1 = (trunc_ln1116_s_fu_107454_p4); + +assign sext_ln1116_14_fu_113503_p1 = (trunc_ln1116_13_fu_113493_p4); + +assign sext_ln1116_15_fu_114298_p1 = (trunc_ln1116_14_fu_114288_p4); + +assign sext_ln1116_16_fu_103536_p1 = (trunc_ln1116_15_fu_103526_p4); + +assign sext_ln1116_17_fu_104340_p1 = (trunc_ln1116_16_fu_104330_p4); + +assign sext_ln1116_18_fu_110397_p1 = (trunc_ln1116_17_fu_110387_p4); + +assign sext_ln1116_19_fu_106951_p1 = (trunc_ln1116_18_fu_106941_p4); + +assign sext_ln1116_1_fu_109223_p1 = (trunc_ln1116_1_fu_109213_p4); + +assign sext_ln1116_20_fu_111192_p1 = (trunc_ln1116_19_fu_111182_p4); + +assign sext_ln1116_21_fu_107753_p1 = (trunc_ln1116_20_fu_107743_p4); + +assign sext_ln1116_22_fu_104853_p1 = (trunc_ln1116_21_fu_104843_p4); + +assign sext_ln1116_23_fu_113794_p1 = (trunc_ln1116_22_fu_113784_p4); + +assign sext_ln1116_24_fu_114587_p1 = (trunc_ln1116_23_fu_114577_p4); + +assign sext_ln1116_25_fu_111707_p1 = (trunc_ln1116_24_fu_111697_p4); + +assign sext_ln1116_26_fu_108265_p1 = (trunc_ln1116_25_fu_108255_p4); + +assign sext_ln1116_27_fu_115099_p1 = (trunc_ln1116_26_fu_115089_p4); + +assign sext_ln1116_28_fu_105143_p1 = (trunc_ln1116_27_fu_105133_p4); + +assign sext_ln1116_29_fu_111997_p1 = (trunc_ln1116_28_fu_111987_p4); + +assign sext_ln1116_2_fu_105782_p1 = (trunc_ln1116_2_fu_105772_p4); + +assign sext_ln1116_30_fu_108554_p1 = (trunc_ln1116_29_fu_108544_p4); + +assign sext_ln1116_31_fu_115388_p1 = (trunc_ln1116_30_fu_115378_p4); + +assign sext_ln1116_3_fu_112625_p1 = (trunc_ln1116_3_fu_112615_p4); + +assign sext_ln1116_4_fu_102654_p1 = (trunc_ln1116_4_fu_102644_p4); + +assign sext_ln1116_5_fu_109514_p1 = (trunc_ln1116_5_fu_109504_p4); + +assign sext_ln1116_6_fu_106072_p1 = (trunc_ln1116_6_fu_106062_p4); + +assign sext_ln1116_7_fu_103244_p1 = (trunc_ln1116_7_fu_103234_p4); + +assign sext_ln1116_8_fu_104050_p1 = (trunc_ln1116_8_fu_104040_p4); + +assign sext_ln1116_9_fu_112915_p1 = (trunc_ln1116_9_fu_112905_p4); + +assign sext_ln1116_fu_102362_p1 = (trunc_ln1_fu_102352_p4); + +assign sext_ln1265_1_fu_124397_p1 = (trunc_ln1265_1_fu_124387_p4); + +assign sext_ln1265_2_fu_120870_p1 = (trunc_ln1265_2_fu_120860_p4); + +assign sext_ln1265_3_fu_117531_p1 = (trunc_ln1265_3_fu_117521_p4); + +assign sext_ln1265_4_fu_127912_p1 = (trunc_ln1265_4_fu_127902_p4); + +assign sext_ln1265_5_fu_124573_p1 = (trunc_ln1265_5_fu_124563_p4); + +assign sext_ln1265_6_fu_120999_p1 = (trunc_ln1265_6_fu_120989_p4); + +assign sext_ln1265_7_fu_128041_p1 = (trunc_ln1265_7_fu_128031_p4); + +assign sext_ln1265_fu_117355_p1 = (trunc_ln_fu_117345_p4); + +assign sext_ln203_3_fu_116608_p1 = (trunc_ln203_1_fu_116598_p4); + +assign sext_ln203_4_fu_116220_p1 = (trunc_ln203_2_fu_116210_p4); + +assign sext_ln203_5_fu_116037_p1 = (trunc_ln203_3_fu_116027_p4); + +assign sext_ln203_6_fu_116984_p1 = (trunc_ln203_4_fu_116974_p4); + +assign sext_ln203_7_fu_116801_p1 = (trunc_ln203_5_fu_116791_p4); + +assign sext_ln203_8_fu_116370_p1 = (trunc_ln203_6_fu_116360_p4); + +assign sext_ln203_9_fu_117134_p1 = (trunc_ln203_7_fu_117124_p4); + +assign sext_ln203_fu_115844_p1 = (trunc_ln203_s_fu_115834_p4); + +assign sext_ln221_1_fu_108959_p1 = (add_ln221_5_fu_108954_p2); + +assign sext_ln221_2_fu_105508_p1 = (add_ln221_8_fu_105503_p2); + +assign sext_ln221_3_fu_112362_p1 = (add_ln221_11_fu_112357_p2); + +assign sext_ln221_4_fu_102886_p1 = (add_ln221_19_fu_102881_p2); + +assign sext_ln221_5_fu_109752_p1 = (add_ln221_27_fu_109747_p2); + +assign sext_ln221_6_fu_106304_p1 = (add_ln221_30_fu_106299_p2); + +assign sext_ln221_7_fu_113147_p1 = (add_ln221_35_fu_113142_p2); + +assign sext_ln221_fu_102087_p1 = (add_ln221_fu_102082_p2); + +assign sext_ln231_1_fu_108986_p1 = (or_ln231_2_fu_108966_p3); + +assign sext_ln231_2_fu_105523_p1 = (or_ln231_4_fu_105515_p3); + +assign sext_ln231_3_fu_112389_p1 = (or_ln231_6_fu_112369_p3); + +assign sext_ln231_4_fu_102907_p1 = (or_ln231_9_fu_102899_p3); + +assign sext_ln231_5_fu_109785_p1 = (or_ln231_12_fu_109765_p3); + +assign sext_ln231_6_fu_106325_p1 = (or_ln231_14_fu_106317_p3); + +assign sext_ln231_7_fu_113180_p1 = (or_ln231_17_fu_113160_p3); + +assign sext_ln231_fu_102102_p1 = (or_ln_fu_102094_p3); + +assign sext_ln250_1_fu_116484_p1 = (sub_ln250_1_fu_116478_p2); + +assign sext_ln250_2_fu_115921_p1 = (sub_ln250_2_fu_115915_p2); + +assign sext_ln250_3_fu_116685_p1 = (sub_ln250_3_fu_116679_p2); + +assign sext_ln250_fu_115710_p1 = (sub_ln250_fu_115704_p2); + +assign sext_ln279_1_fu_124340_p1 = (sub_ln279_1_fu_124334_p2); + +assign sext_ln279_2_fu_117467_p1 = (sub_ln279_2_fu_117461_p2); + +assign sext_ln279_3_fu_124509_p1 = (sub_ln279_3_fu_124503_p2); + +assign sext_ln279_fu_117278_p1 = (sub_ln279_fu_117272_p2); + +assign shl_ln1_fu_117248_p3 = {{ow6_0_0_0_reg_96025}, {4'd0}}; + +assign shl_ln216_10_fu_112462_p2 = fh_0_1_1_0_0_reg_94777 << 32'd2; + +assign shl_ln216_11_fu_102739_p2 = or_ln206_fu_102727_p2 << 32'd2; + +assign shl_ln216_12_fu_103886_p2 = fh_0_0_0_1_0_reg_91787 << 32'd2; + +assign shl_ln216_13_fu_109599_p2 = or_ln206_1_fu_109587_p2 << 32'd2; + +assign shl_ln216_14_fu_106157_p2 = or_ln206_2_fu_106145_p2 << 32'd2; + +assign shl_ln216_15_fu_110738_p2 = fh_0_1_0_1_0_reg_94171 << 32'd2; + +assign shl_ln216_16_fu_107301_p2 = fh_0_0_1_1_0_reg_92973 << 32'd2; + +assign shl_ln216_17_fu_113000_p2 = or_ln206_3_fu_112988_p2 << 32'd2; + +assign shl_ln216_18_fu_114135_p2 = fh_0_1_1_1_0_reg_95357 << 32'd2; + +assign shl_ln216_19_fu_104424_p2 = or_ln206_4_fu_104412_p2 << 32'd2; + +assign shl_ln216_20_fu_111276_p2 = or_ln206_5_fu_111264_p2 << 32'd2; + +assign shl_ln216_21_fu_107837_p2 = or_ln206_6_fu_107825_p2 << 32'd2; + +assign shl_ln216_22_fu_114671_p2 = or_ln206_7_fu_114659_p2 << 32'd2; + +assign shl_ln216_8_fu_109059_p2 = fh_0_1_0_0_0_reg_93591 << 32'd2; + +assign shl_ln216_9_fu_105614_p2 = fh_0_0_1_0_0_reg_92393 << 32'd2; + +assign shl_ln216_fu_102193_p2 = fh_0_0_0_0_0_reg_91207 << 32'd2; + +assign shl_ln221_100_fu_107642_p2 = or_ln208_9_fu_107618_p2 << 32'd4; + +assign shl_ln221_101_fu_104737_p2 = fw_0_0_0_1_1_0_reg_92079 << 32'd6; + +assign shl_ln221_102_fu_104743_p2 = fw_0_0_0_1_1_0_reg_92079 << 32'd4; + +assign shl_ln221_103_fu_113677_p2 = or_ln208_10_fu_113659_p2 << 32'd6; + +assign shl_ln221_104_fu_113683_p2 = or_ln208_10_fu_113659_p2 << 32'd4; + +assign shl_ln221_105_fu_111282_p2 = or_ln206_5_fu_111264_p2 << 32'd8; + +assign shl_ln221_106_fu_111288_p2 = or_ln206_5_fu_111264_p2 << 32'd4; + +assign shl_ln221_107_fu_107843_p2 = or_ln206_6_fu_107825_p2 << 32'd8; + +assign shl_ln221_108_fu_107849_p2 = or_ln206_6_fu_107825_p2 << 32'd4; + +assign shl_ln221_109_fu_114470_p2 = or_ln208_11_fu_114452_p2 << 32'd6; + +assign shl_ln221_10_fu_109729_p3 = {{or_ln204_1_fu_109708_p2}, {2'd0}}; + +assign shl_ln221_110_fu_114476_p2 = or_ln208_11_fu_114452_p2 << 32'd4; + +assign shl_ln221_111_fu_111591_p2 = fw_0_1_0_1_1_0_reg_94463 << 32'd6; + +assign shl_ln221_112_fu_111597_p2 = fw_0_1_0_1_1_0_reg_94463 << 32'd4; + +assign shl_ln221_113_fu_108150_p2 = fw_0_0_1_1_1_0_reg_93265 << 32'd6; + +assign shl_ln221_114_fu_108156_p2 = fw_0_0_1_1_1_0_reg_93265 << 32'd4; + +assign shl_ln221_115_fu_114677_p2 = or_ln206_7_fu_114659_p2 << 32'd8; + +assign shl_ln221_116_fu_114683_p2 = or_ln206_7_fu_114659_p2 << 32'd4; + +assign shl_ln221_117_fu_114984_p2 = fw_0_1_1_1_1_0_reg_95649 << 32'd6; + +assign shl_ln221_118_fu_114990_p2 = fw_0_1_1_1_1_0_reg_95649 << 32'd4; + +assign shl_ln221_119_fu_105025_p2 = or_ln208_12_fu_105007_p2 << 32'd6; + +assign shl_ln221_11_fu_106269_p3 = {{or_ln204_2_fu_106260_p2}, {4'd0}}; + +assign shl_ln221_120_fu_105031_p2 = or_ln208_12_fu_105007_p2 << 32'd4; + +assign shl_ln221_121_fu_111879_p2 = or_ln208_13_fu_111861_p2 << 32'd6; + +assign shl_ln221_122_fu_111885_p2 = or_ln208_13_fu_111861_p2 << 32'd4; + +assign shl_ln221_123_fu_108437_p2 = or_ln208_14_fu_108419_p2 << 32'd6; + +assign shl_ln221_124_fu_108443_p2 = or_ln208_14_fu_108419_p2 << 32'd4; + +assign shl_ln221_125_fu_115271_p2 = or_ln208_15_fu_115253_p2 << 32'd6; + +assign shl_ln221_126_fu_115277_p2 = or_ln208_15_fu_115253_p2 << 32'd4; + +assign shl_ln221_12_fu_106281_p3 = {{or_ln204_2_fu_106260_p2}, {2'd0}}; + +assign shl_ln221_13_fu_113112_p3 = {{or_ln204_3_fu_113103_p2}, {4'd0}}; + +assign shl_ln221_14_fu_113124_p3 = {{or_ln204_3_fu_113103_p2}, {2'd0}}; + +assign shl_ln221_1_fu_102064_p3 = {{trunc_ln221_fu_102048_p1}, {2'd0}}; + +assign shl_ln221_24_fu_102205_p2 = fh_0_0_0_0_0_reg_91207 << 32'd4; + +assign shl_ln221_27_fu_102246_p2 = fw_0_0_0_0_0_0_reg_91219 << 32'd6; + +assign shl_ln221_28_fu_102252_p2 = fw_0_0_0_0_0_0_reg_91219 << 32'd4; + +assign shl_ln221_29_fu_109065_p2 = fh_0_1_0_0_0_reg_93591 << 32'd8; + +assign shl_ln221_2_fu_112339_p3 = {{trunc_ln221_3_fu_112323_p1}, {2'd0}}; + +assign shl_ln221_30_fu_109071_p2 = fh_0_1_0_0_0_reg_93591 << 32'd4; + +assign shl_ln221_31_fu_105620_p2 = fh_0_0_1_0_0_reg_92393 << 32'd8; + +assign shl_ln221_32_fu_105626_p2 = fh_0_0_1_0_0_reg_92393 << 32'd4; + +assign shl_ln221_33_fu_109107_p2 = fw_0_1_0_0_0_0_reg_93603 << 32'd6; + +assign shl_ln221_34_fu_109113_p2 = fw_0_1_0_0_0_0_reg_93603 << 32'd4; + +assign shl_ln221_35_fu_105667_p2 = fw_0_0_1_0_0_0_reg_92405 << 32'd6; + +assign shl_ln221_36_fu_105673_p2 = fw_0_0_1_0_0_0_reg_92405 << 32'd4; + +assign shl_ln221_39_fu_112468_p2 = fh_0_1_1_0_0_reg_94777 << 32'd8; + +assign shl_ln221_3_fu_102851_p3 = {{or_ln204_fu_102842_p2}, {4'd0}}; + +assign shl_ln221_40_fu_112474_p2 = fh_0_1_1_0_0_reg_94777 << 32'd4; + +assign shl_ln221_43_fu_112510_p2 = fw_0_1_1_0_0_0_reg_94789 << 32'd6; + +assign shl_ln221_44_fu_112516_p2 = fw_0_1_1_0_0_0_reg_94789 << 32'd4; + +assign shl_ln221_45_fu_102536_p2 = or_ln208_fu_102518_p2 << 32'd6; + +assign shl_ln221_46_fu_102542_p2 = or_ln208_fu_102518_p2 << 32'd4; + +assign shl_ln221_47_fu_102745_p2 = or_ln206_fu_102727_p2 << 32'd8; + +assign shl_ln221_48_fu_102751_p2 = or_ln206_fu_102727_p2 << 32'd4; + +assign shl_ln221_49_fu_109396_p2 = or_ln208_1_fu_109378_p2 << 32'd6; + +assign shl_ln221_4_fu_108924_p3 = {{trunc_ln221_1_fu_108920_p1}, {4'd0}}; + +assign shl_ln221_50_fu_109402_p2 = or_ln208_1_fu_109378_p2 << 32'd4; + +assign shl_ln221_51_fu_105955_p2 = or_ln208_2_fu_105937_p2 << 32'd6; + +assign shl_ln221_52_fu_105961_p2 = or_ln208_2_fu_105937_p2 << 32'd4; + +assign shl_ln221_53_fu_103892_p2 = fh_0_0_0_1_0_reg_91787 << 32'd8; + +assign shl_ln221_54_fu_103898_p2 = fh_0_0_0_1_0_reg_91787 << 32'd4; + +assign shl_ln221_55_fu_103128_p2 = fw_0_0_0_0_1_0_reg_91503 << 32'd6; + +assign shl_ln221_56_fu_103134_p2 = fw_0_0_0_0_1_0_reg_91503 << 32'd4; + +assign shl_ln221_59_fu_109605_p2 = or_ln206_1_fu_109587_p2 << 32'd8; + +assign shl_ln221_5_fu_108936_p3 = {{trunc_ln221_1_fu_108920_p1}, {2'd0}}; + +assign shl_ln221_60_fu_109611_p2 = or_ln206_1_fu_109587_p2 << 32'd4; + +assign shl_ln221_61_fu_106163_p2 = or_ln206_2_fu_106145_p2 << 32'd8; + +assign shl_ln221_62_fu_106169_p2 = or_ln206_2_fu_106145_p2 << 32'd4; + +assign shl_ln221_63_fu_103934_p2 = fw_0_0_0_1_0_0_reg_91799 << 32'd6; + +assign shl_ln221_64_fu_103940_p2 = fw_0_0_0_1_0_0_reg_91799 << 32'd4; + +assign shl_ln221_65_fu_112798_p2 = or_ln208_3_fu_112780_p2 << 32'd6; + +assign shl_ln221_66_fu_112804_p2 = or_ln208_3_fu_112780_p2 << 32'd4; + +assign shl_ln221_67_fu_110744_p2 = fh_0_1_0_1_0_reg_94171 << 32'd8; + +assign shl_ln221_68_fu_110750_p2 = fh_0_1_0_1_0_reg_94171 << 32'd4; + +assign shl_ln221_69_fu_109989_p2 = fw_0_1_0_0_1_0_reg_93887 << 32'd6; + +assign shl_ln221_6_fu_105473_p3 = {{trunc_ln221_2_fu_105469_p1}, {4'd0}}; + +assign shl_ln221_70_fu_109995_p2 = fw_0_1_0_0_1_0_reg_93887 << 32'd4; + +assign shl_ln221_71_fu_107307_p2 = fh_0_0_1_1_0_reg_92973 << 32'd8; + +assign shl_ln221_72_fu_107313_p2 = fh_0_0_1_1_0_reg_92973 << 32'd4; + +assign shl_ln221_73_fu_106545_p2 = fw_0_0_1_0_1_0_reg_92689 << 32'd6; + +assign shl_ln221_74_fu_106551_p2 = fw_0_0_1_0_1_0_reg_92689 << 32'd4; + +assign shl_ln221_75_fu_113006_p2 = or_ln206_3_fu_112988_p2 << 32'd8; + +assign shl_ln221_76_fu_113012_p2 = or_ln206_3_fu_112988_p2 << 32'd4; + +assign shl_ln221_77_fu_110786_p2 = fw_0_1_0_1_0_0_reg_94183 << 32'd6; + +assign shl_ln221_78_fu_110792_p2 = fw_0_1_0_1_0_0_reg_94183 << 32'd4; + +assign shl_ln221_79_fu_107349_p2 = fw_0_0_1_1_0_0_reg_92985 << 32'd6; + +assign shl_ln221_7_fu_105485_p3 = {{trunc_ln221_2_fu_105469_p1}, {2'd0}}; + +assign shl_ln221_80_fu_107355_p2 = fw_0_0_1_1_0_0_reg_92985 << 32'd4; + +assign shl_ln221_81_fu_114141_p2 = fh_0_1_1_1_0_reg_95357 << 32'd8; + +assign shl_ln221_82_fu_114147_p2 = fh_0_1_1_1_0_reg_95357 << 32'd4; + +assign shl_ln221_83_fu_113388_p2 = fw_0_1_1_0_1_0_reg_95073 << 32'd6; + +assign shl_ln221_84_fu_113394_p2 = fw_0_1_1_0_1_0_reg_95073 << 32'd4; + +assign shl_ln221_85_fu_114183_p2 = fw_0_1_1_1_0_0_reg_95369 << 32'd6; + +assign shl_ln221_86_fu_114189_p2 = fw_0_1_1_1_0_0_reg_95369 << 32'd4; + +assign shl_ln221_87_fu_103418_p2 = or_ln208_4_fu_103400_p2 << 32'd6; + +assign shl_ln221_88_fu_103424_p2 = or_ln208_4_fu_103400_p2 << 32'd4; + +assign shl_ln221_89_fu_104222_p2 = or_ln208_5_fu_104204_p2 << 32'd6; + +assign shl_ln221_8_fu_102863_p3 = {{or_ln204_fu_102842_p2}, {2'd0}}; + +assign shl_ln221_90_fu_104228_p2 = or_ln208_5_fu_104204_p2 << 32'd4; + +assign shl_ln221_91_fu_110279_p2 = or_ln208_6_fu_110261_p2 << 32'd6; + +assign shl_ln221_92_fu_110285_p2 = or_ln208_6_fu_110261_p2 << 32'd4; + +assign shl_ln221_93_fu_106834_p2 = or_ln208_7_fu_106816_p2 << 32'd6; + +assign shl_ln221_94_fu_106840_p2 = or_ln208_7_fu_106816_p2 << 32'd4; + +assign shl_ln221_95_fu_104430_p2 = or_ln206_4_fu_104412_p2 << 32'd8; + +assign shl_ln221_96_fu_104436_p2 = or_ln206_4_fu_104412_p2 << 32'd4; + +assign shl_ln221_97_fu_111074_p2 = or_ln208_8_fu_111056_p2 << 32'd6; + +assign shl_ln221_98_fu_111080_p2 = or_ln208_8_fu_111056_p2 << 32'd4; + +assign shl_ln221_99_fu_107636_p2 = or_ln208_9_fu_107618_p2 << 32'd6; + +assign shl_ln221_9_fu_109717_p3 = {{or_ln204_1_fu_109708_p2}, {4'd0}}; + +assign shl_ln221_fu_102199_p2 = fh_0_0_0_0_0_reg_91207 << 32'd8; + +assign shl_ln221_s_fu_112327_p3 = {{trunc_ln221_3_fu_112323_p1}, {4'd0}}; + +assign shl_ln231_10_fu_110065_p3 = {{add_ln231_45_fu_110059_p2}, {2'd0}}; + +assign shl_ln231_11_fu_106620_p3 = {{add_ln231_46_fu_106615_p2}, {2'd0}}; + +assign shl_ln231_12_fu_110862_p3 = {{add_ln231_48_fu_110856_p2}, {2'd0}}; + +assign shl_ln231_13_fu_107424_p3 = {{add_ln231_49_fu_107419_p2}, {2'd0}}; + +assign shl_ln231_14_fu_113463_p3 = {{add_ln231_51_fu_113458_p2}, {2'd0}}; + +assign shl_ln231_15_fu_114258_p3 = {{add_ln231_52_fu_114253_p2}, {2'd0}}; + +assign shl_ln231_16_fu_102167_p2 = add_ln223_fu_102118_p2 << 32'd3; + +assign shl_ln231_17_fu_109033_p2 = add_ln223_1_fu_108990_p2 << 32'd6; + +assign shl_ln231_18_fu_109039_p2 = add_ln223_1_fu_108990_p2 << 32'd3; + +assign shl_ln231_19_fu_105582_p2 = add_ln223_2_fu_105539_p2 << 32'd6; + +assign shl_ln231_1_fu_112585_p3 = {{add_ln231_13_fu_112580_p2}, {2'd0}}; + +assign shl_ln231_20_fu_105588_p2 = add_ln223_2_fu_105539_p2 << 32'd3; + +assign shl_ln231_21_fu_112436_p2 = add_ln223_4_fu_112393_p2 << 32'd6; + +assign shl_ln231_22_fu_103496_p3 = {{add_ln231_57_fu_103490_p2}, {2'd0}}; + +assign shl_ln231_23_fu_112442_p2 = add_ln223_4_fu_112393_p2 << 32'd3; + +assign shl_ln231_24_fu_102800_p2 = add_ln223_8_fu_102763_p2 << 32'd6; + +assign shl_ln231_25_fu_104300_p3 = {{add_ln231_58_fu_104294_p2}, {2'd0}}; + +assign shl_ln231_26_fu_110357_p3 = {{add_ln231_63_fu_110351_p2}, {2'd0}}; + +assign shl_ln231_27_fu_102806_p2 = add_ln223_8_fu_102763_p2 << 32'd3; + +assign shl_ln231_28_fu_103845_p2 = add_ln223_10_fu_103808_p2 << 32'd6; + +assign shl_ln231_29_fu_106911_p3 = {{add_ln231_67_fu_106906_p2}, {2'd0}}; + +assign shl_ln231_2_fu_102614_p3 = {{add_ln231_19_fu_102608_p2}, {2'd0}}; + +assign shl_ln231_30_fu_103851_p2 = add_ln223_10_fu_103808_p2 << 32'd3; + +assign shl_ln231_31_fu_109666_p2 = add_ln223_11_fu_109623_p2 << 32'd6; + +assign shl_ln231_32_fu_111152_p3 = {{add_ln231_69_fu_111146_p2}, {2'd0}}; + +assign shl_ln231_33_fu_107713_p3 = {{add_ln231_70_fu_107708_p2}, {2'd0}}; + +assign shl_ln231_34_fu_104813_p3 = {{add_ln231_72_fu_104807_p2}, {2'd0}}; + +assign shl_ln231_35_fu_113754_p3 = {{add_ln231_76_fu_113749_p2}, {2'd0}}; + +assign shl_ln231_36_fu_114547_p3 = {{add_ln231_78_fu_114542_p2}, {2'd0}}; + +assign shl_ln231_37_fu_111667_p3 = {{add_ln231_79_fu_111661_p2}, {2'd0}}; + +assign shl_ln231_38_fu_108225_p3 = {{add_ln231_81_fu_108220_p2}, {2'd0}}; + +assign shl_ln231_39_fu_109672_p2 = add_ln223_11_fu_109623_p2 << 32'd3; + +assign shl_ln231_3_fu_109474_p3 = {{add_ln231_30_fu_109468_p2}, {2'd0}}; + +assign shl_ln231_40_fu_106218_p2 = add_ln223_13_fu_106181_p2 << 32'd6; + +assign shl_ln231_41_fu_115059_p3 = {{add_ln231_82_fu_115054_p2}, {2'd0}}; + +assign shl_ln231_42_fu_105103_p3 = {{add_ln231_88_fu_105097_p2}, {2'd0}}; + +assign shl_ln231_43_fu_106224_p2 = add_ln223_13_fu_106181_p2 << 32'd3; + +assign shl_ln231_44_fu_110712_p2 = add_ln223_16_fu_110669_p2 << 32'd6; + +assign shl_ln231_45_fu_111957_p3 = {{add_ln231_89_fu_111951_p2}, {2'd0}}; + +assign shl_ln231_46_fu_110718_p2 = add_ln223_16_fu_110669_p2 << 32'd3; + +assign shl_ln231_47_fu_107260_p2 = add_ln223_17_fu_107223_p2 << 32'd6; + +assign shl_ln231_48_fu_108514_p3 = {{add_ln231_90_fu_108509_p2}, {2'd0}}; + +assign shl_ln231_49_fu_115348_p3 = {{add_ln231_91_fu_115343_p2}, {2'd0}}; + +assign shl_ln231_4_fu_106032_p3 = {{add_ln231_33_fu_106027_p2}, {2'd0}}; + +assign shl_ln231_52_fu_107266_p2 = add_ln223_17_fu_107223_p2 << 32'd3; + +assign shl_ln231_53_fu_113061_p2 = add_ln223_19_fu_113024_p2 << 32'd6; + +assign shl_ln231_5_fu_103204_p3 = {{add_ln231_34_fu_103198_p2}, {2'd0}}; + +assign shl_ln231_63_fu_113067_p2 = add_ln223_19_fu_113024_p2 << 32'd3; + +assign shl_ln231_64_fu_114109_p2 = add_ln223_23_fu_114066_p2 << 32'd6; + +assign shl_ln231_65_fu_114115_p2 = add_ln223_23_fu_114066_p2 << 32'd3; + +assign shl_ln231_66_fu_104485_p2 = add_ln223_29_fu_104448_p2 << 32'd6; + +assign shl_ln231_67_fu_104491_p2 = add_ln223_29_fu_104448_p2 << 32'd3; + +assign shl_ln231_68_fu_111343_p2 = add_ln223_33_fu_111300_p2 << 32'd6; + +assign shl_ln231_69_fu_111349_p2 = add_ln223_33_fu_111300_p2 << 32'd3; + +assign shl_ln231_6_fu_102322_p3 = {{add_ln231_6_fu_102316_p2}, {2'd0}}; + +assign shl_ln231_70_fu_107898_p2 = add_ln223_35_fu_107861_p2 << 32'd6; + +assign shl_ln231_71_fu_107904_p2 = add_ln223_35_fu_107861_p2 << 32'd3; + +assign shl_ln231_72_fu_114732_p2 = add_ln223_39_fu_114695_p2 << 32'd6; + +assign shl_ln231_73_fu_114738_p2 = add_ln223_39_fu_114695_p2 << 32'd3; + +assign shl_ln231_7_fu_104010_p3 = {{add_ln231_39_fu_104004_p2}, {2'd0}}; + +assign shl_ln231_8_fu_112875_p3 = {{add_ln231_43_fu_112870_p2}, {2'd0}}; + +assign shl_ln231_9_fu_109183_p3 = {{add_ln231_10_fu_109177_p2}, {2'd0}}; + +assign shl_ln231_fu_102161_p2 = add_ln223_fu_102118_p2 << 32'd6; + +assign shl_ln231_s_fu_105742_p3 = {{add_ln231_12_fu_105737_p2}, {2'd0}}; + +assign shl_ln250_1_fu_115692_p3 = {{ow3_0_0_0_reg_95941}, {2'd0}}; + +assign shl_ln250_2_fu_116454_p3 = {{ow3_0_1_0_reg_95977}, {4'd0}}; + +assign shl_ln250_3_fu_116466_p3 = {{ow3_0_1_0_reg_95977}, {2'd0}}; + +assign shl_ln250_4_fu_115891_p3 = {{or_ln246_fu_115885_p2}, {4'd0}}; + +assign shl_ln250_5_fu_115903_p3 = {{or_ln246_fu_115885_p2}, {2'd0}}; + +assign shl_ln250_6_fu_116655_p3 = {{or_ln246_1_fu_116649_p2}, {4'd0}}; + +assign shl_ln250_7_fu_116667_p3 = {{or_ln246_1_fu_116649_p2}, {2'd0}}; + +assign shl_ln276_16_fu_124645_p2 = fh9_0_1_0_0_0_0_reg_97569 << 32'd2; + +assign shl_ln276_17_fu_121071_p2 = fh9_0_0_1_0_0_0_reg_96809 << 32'd2; + +assign shl_ln276_18_fu_119229_p2 = fh9_0_0_0_1_0_0_reg_96433 << 32'd2; + +assign shl_ln276_19_fu_128113_p2 = fh9_0_1_1_0_0_0_reg_98317 << 32'd2; + +assign shl_ln276_20_fu_126271_p2 = fh9_0_1_0_1_0_0_reg_97941 << 32'd2; + +assign shl_ln276_21_fu_122697_p2 = fh9_0_0_1_1_0_0_reg_97181 << 32'd2; + +assign shl_ln276_22_fu_129739_p2 = fh9_0_1_1_1_0_0_reg_98689 << 32'd2; + +assign shl_ln276_23_fu_117847_p2 = or_ln266_fu_117835_p2 << 32'd2; + +assign shl_ln276_24_fu_118412_p2 = fh9_0_0_0_0_1_0_reg_96241 << 32'd2; + +assign shl_ln276_25_fu_124889_p2 = or_ln266_1_fu_124877_p2 << 32'd2; + +assign shl_ln276_26_fu_121315_p2 = or_ln266_2_fu_121303_p2 << 32'd2; + +assign shl_ln276_27_fu_119473_p2 = or_ln266_3_fu_119461_p2 << 32'd2; + +assign shl_ln276_28_fu_125454_p2 = fh9_0_1_0_0_1_0_reg_97749 << 32'd2; + +assign shl_ln276_29_fu_121880_p2 = fh9_0_0_1_0_1_0_reg_96989 << 32'd2; + +assign shl_ln276_30_fu_120036_p2 = fh9_0_0_0_1_1_0_reg_96609 << 32'd2; + +assign shl_ln276_31_fu_128357_p2 = or_ln266_4_fu_128345_p2 << 32'd2; + +assign shl_ln276_32_fu_126515_p2 = or_ln266_5_fu_126503_p2 << 32'd2; + +assign shl_ln276_33_fu_122941_p2 = or_ln266_6_fu_122929_p2 << 32'd2; + +assign shl_ln276_34_fu_128922_p2 = fh9_0_1_1_0_1_0_reg_98497 << 32'd2; + +assign shl_ln276_35_fu_127078_p2 = fh9_0_1_0_1_1_0_reg_98117 << 32'd2; + +assign shl_ln276_36_fu_123504_p2 = fh9_0_0_1_1_1_0_reg_97357 << 32'd2; + +assign shl_ln276_37_fu_129983_p2 = or_ln266_7_fu_129971_p2 << 32'd2; + +assign shl_ln276_38_fu_130546_p2 = fh9_0_1_1_1_1_0_reg_98865 << 32'd2; + +assign shl_ln276_39_fu_118656_p2 = or_ln266_8_fu_118644_p2 << 32'd2; + +assign shl_ln276_40_fu_125698_p2 = or_ln266_9_fu_125686_p2 << 32'd2; + +assign shl_ln276_41_fu_122124_p2 = or_ln266_10_fu_122112_p2 << 32'd2; + +assign shl_ln276_42_fu_120280_p2 = or_ln266_11_fu_120268_p2 << 32'd2; + +assign shl_ln276_43_fu_129166_p2 = or_ln266_12_fu_129154_p2 << 32'd2; + +assign shl_ln276_44_fu_127322_p2 = or_ln266_13_fu_127310_p2 << 32'd2; + +assign shl_ln276_45_fu_123748_p2 = or_ln266_14_fu_123736_p2 << 32'd2; + +assign shl_ln276_46_fu_130790_p2 = or_ln266_15_fu_130778_p2 << 32'd2; + +assign shl_ln276_fu_117603_p2 = fh9_0_0_0_0_0_0_reg_96061 << 32'd2; + +assign shl_ln279_1_fu_117260_p3 = {{ow6_0_0_0_reg_96025}, {2'd0}}; + +assign shl_ln279_2_fu_124310_p3 = {{ow6_0_1_0_reg_97533}, {4'd0}}; + +assign shl_ln279_3_fu_124322_p3 = {{ow6_0_1_0_reg_97533}, {2'd0}}; + +assign shl_ln279_4_fu_117437_p3 = {{or_ln259_fu_117427_p2}, {4'd0}}; + +assign shl_ln279_5_fu_117449_p3 = {{or_ln259_fu_117427_p2}, {2'd0}}; + +assign shl_ln279_6_fu_124479_p3 = {{or_ln259_1_fu_124469_p2}, {4'd0}}; + +assign shl_ln279_7_fu_124491_p3 = {{or_ln259_1_fu_124469_p2}, {2'd0}}; + +assign shl_ln2_fu_102052_p3 = {{trunc_ln221_fu_102048_p1}, {4'd0}}; + +assign shl_ln_fu_115680_p3 = {{ow3_0_0_0_reg_95941}, {4'd0}}; + +assign sub_ln221_10_fu_112480_p2 = (shl_ln221_39_fu_112468_p2 - shl_ln221_40_fu_112474_p2); + +assign sub_ln221_11_fu_112522_p2 = (shl_ln221_43_fu_112510_p2 - shl_ln221_44_fu_112516_p2); + +assign sub_ln221_12_fu_102548_p2 = (shl_ln221_45_fu_102536_p2 - shl_ln221_46_fu_102542_p2); + +assign sub_ln221_13_fu_102875_p2 = (zext_ln221_13_fu_102859_p1 - zext_ln221_14_fu_102871_p1); + +assign sub_ln221_14_fu_102757_p2 = (shl_ln221_47_fu_102745_p2 - shl_ln221_48_fu_102751_p2); + +assign sub_ln221_15_fu_109408_p2 = (shl_ln221_49_fu_109396_p2 - shl_ln221_50_fu_109402_p2); + +assign sub_ln221_16_fu_105967_p2 = (shl_ln221_51_fu_105955_p2 - shl_ln221_52_fu_105961_p2); + +assign sub_ln221_17_fu_103904_p2 = (shl_ln221_53_fu_103892_p2 - shl_ln221_54_fu_103898_p2); + +assign sub_ln221_18_fu_103140_p2 = (shl_ln221_55_fu_103128_p2 - shl_ln221_56_fu_103134_p2); + +assign sub_ln221_19_fu_109741_p2 = (zext_ln221_16_fu_109725_p1 - zext_ln221_17_fu_109737_p1); + +assign sub_ln221_1_fu_102211_p2 = (shl_ln221_fu_102199_p2 - shl_ln221_24_fu_102205_p2); + +assign sub_ln221_20_fu_109617_p2 = (shl_ln221_59_fu_109605_p2 - shl_ln221_60_fu_109611_p2); + +assign sub_ln221_21_fu_106293_p2 = (zext_ln221_19_fu_106277_p1 - zext_ln221_20_fu_106289_p1); + +assign sub_ln221_22_fu_106175_p2 = (shl_ln221_61_fu_106163_p2 - shl_ln221_62_fu_106169_p2); + +assign sub_ln221_23_fu_103946_p2 = (shl_ln221_63_fu_103934_p2 - shl_ln221_64_fu_103940_p2); + +assign sub_ln221_24_fu_112810_p2 = (shl_ln221_65_fu_112798_p2 - shl_ln221_66_fu_112804_p2); + +assign sub_ln221_25_fu_110756_p2 = (shl_ln221_67_fu_110744_p2 - shl_ln221_68_fu_110750_p2); + +assign sub_ln221_26_fu_110001_p2 = (shl_ln221_69_fu_109989_p2 - shl_ln221_70_fu_109995_p2); + +assign sub_ln221_27_fu_107319_p2 = (shl_ln221_71_fu_107307_p2 - shl_ln221_72_fu_107313_p2); + +assign sub_ln221_28_fu_106557_p2 = (shl_ln221_73_fu_106545_p2 - shl_ln221_74_fu_106551_p2); + +assign sub_ln221_29_fu_113136_p2 = (zext_ln221_22_fu_113120_p1 - zext_ln221_23_fu_113132_p1); + +assign sub_ln221_2_fu_108948_p2 = (zext_ln221_4_fu_108932_p1 - zext_ln221_5_fu_108944_p1); + +assign sub_ln221_30_fu_113018_p2 = (shl_ln221_75_fu_113006_p2 - shl_ln221_76_fu_113012_p2); + +assign sub_ln221_31_fu_110798_p2 = (shl_ln221_77_fu_110786_p2 - shl_ln221_78_fu_110792_p2); + +assign sub_ln221_32_fu_107361_p2 = (shl_ln221_79_fu_107349_p2 - shl_ln221_80_fu_107355_p2); + +assign sub_ln221_33_fu_114153_p2 = (shl_ln221_81_fu_114141_p2 - shl_ln221_82_fu_114147_p2); + +assign sub_ln221_34_fu_113400_p2 = (shl_ln221_83_fu_113388_p2 - shl_ln221_84_fu_113394_p2); + +assign sub_ln221_35_fu_114195_p2 = (shl_ln221_85_fu_114183_p2 - shl_ln221_86_fu_114189_p2); + +assign sub_ln221_36_fu_103430_p2 = (shl_ln221_87_fu_103418_p2 - shl_ln221_88_fu_103424_p2); + +assign sub_ln221_37_fu_104234_p2 = (shl_ln221_89_fu_104222_p2 - shl_ln221_90_fu_104228_p2); + +assign sub_ln221_38_fu_110291_p2 = (shl_ln221_91_fu_110279_p2 - shl_ln221_92_fu_110285_p2); + +assign sub_ln221_39_fu_106846_p2 = (shl_ln221_93_fu_106834_p2 - shl_ln221_94_fu_106840_p2); + +assign sub_ln221_3_fu_105497_p2 = (zext_ln221_7_fu_105481_p1 - zext_ln221_8_fu_105493_p1); + +assign sub_ln221_40_fu_104442_p2 = (shl_ln221_95_fu_104430_p2 - shl_ln221_96_fu_104436_p2); + +assign sub_ln221_41_fu_111086_p2 = (shl_ln221_97_fu_111074_p2 - shl_ln221_98_fu_111080_p2); + +assign sub_ln221_42_fu_107648_p2 = (shl_ln221_99_fu_107636_p2 - shl_ln221_100_fu_107642_p2); + +assign sub_ln221_43_fu_104749_p2 = (shl_ln221_101_fu_104737_p2 - shl_ln221_102_fu_104743_p2); + +assign sub_ln221_44_fu_113689_p2 = (shl_ln221_103_fu_113677_p2 - shl_ln221_104_fu_113683_p2); + +assign sub_ln221_45_fu_111294_p2 = (shl_ln221_105_fu_111282_p2 - shl_ln221_106_fu_111288_p2); + +assign sub_ln221_46_fu_107855_p2 = (shl_ln221_107_fu_107843_p2 - shl_ln221_108_fu_107849_p2); + +assign sub_ln221_47_fu_114482_p2 = (shl_ln221_109_fu_114470_p2 - shl_ln221_110_fu_114476_p2); + +assign sub_ln221_48_fu_111603_p2 = (shl_ln221_111_fu_111591_p2 - shl_ln221_112_fu_111597_p2); + +assign sub_ln221_49_fu_108162_p2 = (shl_ln221_113_fu_108150_p2 - shl_ln221_114_fu_108156_p2); + +assign sub_ln221_4_fu_102258_p2 = (shl_ln221_27_fu_102246_p2 - shl_ln221_28_fu_102252_p2); + +assign sub_ln221_50_fu_114689_p2 = (shl_ln221_115_fu_114677_p2 - shl_ln221_116_fu_114683_p2); + +assign sub_ln221_51_fu_114996_p2 = (shl_ln221_117_fu_114984_p2 - shl_ln221_118_fu_114990_p2); + +assign sub_ln221_52_fu_105037_p2 = (shl_ln221_119_fu_105025_p2 - shl_ln221_120_fu_105031_p2); + +assign sub_ln221_53_fu_111891_p2 = (shl_ln221_121_fu_111879_p2 - shl_ln221_122_fu_111885_p2); + +assign sub_ln221_54_fu_108449_p2 = (shl_ln221_123_fu_108437_p2 - shl_ln221_124_fu_108443_p2); + +assign sub_ln221_55_fu_115283_p2 = (shl_ln221_125_fu_115271_p2 - shl_ln221_126_fu_115277_p2); + +assign sub_ln221_5_fu_109077_p2 = (shl_ln221_29_fu_109065_p2 - shl_ln221_30_fu_109071_p2); + +assign sub_ln221_6_fu_105632_p2 = (shl_ln221_31_fu_105620_p2 - shl_ln221_32_fu_105626_p2); + +assign sub_ln221_7_fu_112351_p2 = (zext_ln221_10_fu_112335_p1 - zext_ln221_11_fu_112347_p1); + +assign sub_ln221_8_fu_109119_p2 = (shl_ln221_33_fu_109107_p2 - shl_ln221_34_fu_109113_p2); + +assign sub_ln221_9_fu_105679_p2 = (shl_ln221_35_fu_105667_p2 - shl_ln221_36_fu_105673_p2); + +assign sub_ln221_fu_102076_p2 = (zext_ln221_1_fu_102060_p1 - zext_ln221_2_fu_102072_p1); + +assign sub_ln231_10_fu_113073_p2 = (shl_ln231_53_fu_113061_p2 - shl_ln231_63_fu_113067_p2); + +assign sub_ln231_11_fu_114121_p2 = (shl_ln231_64_fu_114109_p2 - shl_ln231_65_fu_114115_p2); + +assign sub_ln231_12_fu_104497_p2 = (shl_ln231_66_fu_104485_p2 - shl_ln231_67_fu_104491_p2); + +assign sub_ln231_13_fu_111355_p2 = (shl_ln231_68_fu_111343_p2 - shl_ln231_69_fu_111349_p2); + +assign sub_ln231_14_fu_107910_p2 = (shl_ln231_70_fu_107898_p2 - shl_ln231_71_fu_107904_p2); + +assign sub_ln231_15_fu_114744_p2 = (shl_ln231_72_fu_114732_p2 - shl_ln231_73_fu_114738_p2); + +assign sub_ln231_1_fu_109045_p2 = (shl_ln231_17_fu_109033_p2 - shl_ln231_18_fu_109039_p2); + +assign sub_ln231_2_fu_105594_p2 = (shl_ln231_19_fu_105582_p2 - shl_ln231_20_fu_105588_p2); + +assign sub_ln231_3_fu_112448_p2 = (shl_ln231_21_fu_112436_p2 - shl_ln231_23_fu_112442_p2); + +assign sub_ln231_4_fu_102812_p2 = (shl_ln231_24_fu_102800_p2 - shl_ln231_27_fu_102806_p2); + +assign sub_ln231_5_fu_103857_p2 = (shl_ln231_28_fu_103845_p2 - shl_ln231_30_fu_103851_p2); + +assign sub_ln231_6_fu_109678_p2 = (shl_ln231_31_fu_109666_p2 - shl_ln231_39_fu_109672_p2); + +assign sub_ln231_7_fu_106230_p2 = (shl_ln231_40_fu_106218_p2 - shl_ln231_43_fu_106224_p2); + +assign sub_ln231_8_fu_110724_p2 = (shl_ln231_44_fu_110712_p2 - shl_ln231_46_fu_110718_p2); + +assign sub_ln231_9_fu_107272_p2 = (shl_ln231_47_fu_107260_p2 - shl_ln231_52_fu_107266_p2); + +assign sub_ln231_fu_102173_p2 = (shl_ln231_fu_102161_p2 - shl_ln231_16_fu_102167_p2); + +assign sub_ln250_1_fu_116478_p2 = (zext_ln250_2_fu_116462_p1 - zext_ln250_3_fu_116474_p1); + +assign sub_ln250_2_fu_115915_p2 = (zext_ln250_4_fu_115899_p1 - zext_ln250_5_fu_115911_p1); + +assign sub_ln250_3_fu_116679_p2 = (zext_ln250_7_fu_116663_p1 - zext_ln250_8_fu_116675_p1); + +assign sub_ln250_fu_115704_p2 = (zext_ln250_fu_115688_p1 - zext_ln250_1_fu_115700_p1); + +assign sub_ln279_1_fu_124334_p2 = (zext_ln279_6_fu_124318_p1 - zext_ln279_7_fu_124330_p1); + +assign sub_ln279_2_fu_117461_p2 = (zext_ln279_9_fu_117445_p1 - zext_ln279_10_fu_117457_p1); + +assign sub_ln279_3_fu_124503_p2 = (zext_ln279_14_fu_124487_p1 - zext_ln279_15_fu_124499_p1); + +assign sub_ln279_fu_117272_p2 = (zext_ln279_3_fu_117256_p1 - zext_ln279_4_fu_117268_p1); + +assign tmp_241_fu_102123_p4 = {{add_ln223_fu_102118_p2[31:1]}}; + +assign tmp_242_fu_102139_p4 = {{add_ln223_fu_102118_p2[31:4]}}; + +assign tmp_243_fu_108995_p4 = {{add_ln223_1_fu_108990_p2[31:1]}}; + +assign tmp_244_fu_109011_p4 = {{add_ln223_1_fu_108990_p2[31:4]}}; + +assign tmp_245_fu_105544_p4 = {{add_ln223_2_fu_105539_p2[31:1]}}; + +assign tmp_246_fu_105560_p4 = {{add_ln223_2_fu_105539_p2[31:4]}}; + +assign tmp_247_fu_102278_p4 = {{add_ln223_3_fu_102269_p2[31:1]}}; + +assign tmp_248_fu_102294_p4 = {{add_ln223_3_fu_102269_p2[31:4]}}; + +assign tmp_250_fu_112398_p4 = {{add_ln223_4_fu_112393_p2[31:1]}}; + +assign tmp_251_fu_112414_p4 = {{add_ln223_4_fu_112393_p2[31:4]}}; + +assign tmp_252_fu_109139_p4 = {{add_ln223_5_fu_109130_p2[31:1]}}; + +assign tmp_253_fu_109155_p4 = {{add_ln223_5_fu_109130_p2[31:4]}}; + +assign tmp_254_fu_105699_p4 = {{add_ln223_6_fu_105690_p2[31:1]}}; + +assign tmp_255_fu_105715_p4 = {{add_ln223_6_fu_105690_p2[31:4]}}; + +assign tmp_259_fu_112542_p4 = {{add_ln223_7_fu_112533_p2[31:1]}}; + +assign tmp_260_fu_112558_p4 = {{add_ln223_7_fu_112533_p2[31:4]}}; + +assign tmp_270_fu_102768_p4 = {{add_ln223_8_fu_102763_p2[31:1]}}; + +assign tmp_271_fu_102784_p4 = {{add_ln223_8_fu_102763_p2[31:4]}}; + +assign tmp_272_fu_102570_p4 = {{add_ln223_9_fu_102565_p2[31:1]}}; + +assign tmp_273_fu_102586_p4 = {{add_ln223_9_fu_102565_p2[31:4]}}; + +assign tmp_277_fu_103813_p4 = {{add_ln223_10_fu_103808_p2[31:1]}}; + +assign tmp_278_fu_103829_p4 = {{add_ln223_10_fu_103808_p2[31:4]}}; + +assign tmp_283_fu_109628_p4 = {{add_ln223_11_fu_109623_p2[31:1]}}; + +assign tmp_284_fu_109644_p4 = {{add_ln223_11_fu_109623_p2[31:4]}}; + +assign tmp_285_fu_109430_p4 = {{add_ln223_12_fu_109425_p2[31:1]}}; + +assign tmp_286_fu_109446_p4 = {{add_ln223_12_fu_109425_p2[31:4]}}; + +assign tmp_287_fu_106186_p4 = {{add_ln223_13_fu_106181_p2[31:1]}}; + +assign tmp_288_fu_106202_p4 = {{add_ln223_13_fu_106181_p2[31:4]}}; + +assign tmp_289_fu_105989_p4 = {{add_ln223_14_fu_105984_p2[31:1]}}; + +assign tmp_290_fu_106005_p4 = {{add_ln223_14_fu_105984_p2[31:4]}}; + +assign tmp_291_fu_103160_p4 = {{add_ln223_15_fu_103151_p2[31:1]}}; + +assign tmp_292_fu_103176_p4 = {{add_ln223_15_fu_103151_p2[31:4]}}; + +assign tmp_294_fu_110674_p4 = {{add_ln223_16_fu_110669_p2[31:1]}}; + +assign tmp_295_fu_110690_p4 = {{add_ln223_16_fu_110669_p2[31:4]}}; + +assign tmp_297_fu_107228_p4 = {{add_ln223_17_fu_107223_p2[31:1]}}; + +assign tmp_298_fu_107244_p4 = {{add_ln223_17_fu_107223_p2[31:4]}}; + +assign tmp_300_fu_103966_p4 = {{add_ln223_18_fu_103957_p2[31:1]}}; + +assign tmp_301_fu_103982_p4 = {{add_ln223_18_fu_103957_p2[31:4]}}; + +assign tmp_308_fu_113029_p4 = {{add_ln223_19_fu_113024_p2[31:1]}}; + +assign tmp_309_fu_113045_p4 = {{add_ln223_19_fu_113024_p2[31:4]}}; + +assign tmp_310_fu_112832_p4 = {{add_ln223_20_fu_112827_p2[31:1]}}; + +assign tmp_311_fu_112848_p4 = {{add_ln223_20_fu_112827_p2[31:4]}}; + +assign tmp_312_fu_110021_p4 = {{add_ln223_21_fu_110012_p2[31:1]}}; + +assign tmp_313_fu_110037_p4 = {{add_ln223_21_fu_110012_p2[31:4]}}; + +assign tmp_314_fu_106577_p4 = {{add_ln223_22_fu_106568_p2[31:1]}}; + +assign tmp_315_fu_106593_p4 = {{add_ln223_22_fu_106568_p2[31:4]}}; + +assign tmp_318_fu_114071_p4 = {{add_ln223_23_fu_114066_p2[31:1]}}; + +assign tmp_319_fu_114087_p4 = {{add_ln223_23_fu_114066_p2[31:4]}}; + +assign tmp_321_fu_110818_p4 = {{add_ln223_24_fu_110809_p2[31:1]}}; + +assign tmp_322_fu_110834_p4 = {{add_ln223_24_fu_110809_p2[31:4]}}; + +assign tmp_325_fu_107381_p4 = {{add_ln223_25_fu_107372_p2[31:1]}}; + +assign tmp_326_fu_107397_p4 = {{add_ln223_25_fu_107372_p2[31:4]}}; + +assign tmp_334_fu_113420_p4 = {{add_ln223_26_fu_113411_p2[31:1]}}; + +assign tmp_335_fu_113436_p4 = {{add_ln223_26_fu_113411_p2[31:4]}}; + +assign tmp_343_fu_114215_p4 = {{add_ln223_27_fu_114206_p2[31:1]}}; + +assign tmp_344_fu_114231_p4 = {{add_ln223_27_fu_114206_p2[31:4]}}; + +assign tmp_368_fu_103452_p4 = {{add_ln223_28_fu_103447_p2[31:1]}}; + +assign tmp_369_fu_103468_p4 = {{add_ln223_28_fu_103447_p2[31:4]}}; + +assign tmp_374_fu_104453_p4 = {{add_ln223_29_fu_104448_p2[31:1]}}; + +assign tmp_375_fu_104469_p4 = {{add_ln223_29_fu_104448_p2[31:4]}}; + +assign tmp_376_fu_104256_p4 = {{add_ln223_30_fu_104251_p2[31:1]}}; + +assign tmp_377_fu_104272_p4 = {{add_ln223_30_fu_104251_p2[31:4]}}; + +assign tmp_383_fu_110313_p4 = {{add_ln223_31_fu_110308_p2[31:1]}}; + +assign tmp_384_fu_110329_p4 = {{add_ln223_31_fu_110308_p2[31:4]}}; + +assign tmp_385_fu_106868_p4 = {{add_ln223_32_fu_106863_p2[31:1]}}; + +assign tmp_386_fu_106884_p4 = {{add_ln223_32_fu_106863_p2[31:4]}}; + +assign tmp_389_fu_111305_p4 = {{add_ln223_33_fu_111300_p2[31:1]}}; + +assign tmp_390_fu_111321_p4 = {{add_ln223_33_fu_111300_p2[31:4]}}; + +assign tmp_391_fu_111108_p4 = {{add_ln223_34_fu_111103_p2[31:1]}}; + +assign tmp_392_fu_111124_p4 = {{add_ln223_34_fu_111103_p2[31:4]}}; + +assign tmp_394_fu_107866_p4 = {{add_ln223_35_fu_107861_p2[31:1]}}; + +assign tmp_395_fu_107882_p4 = {{add_ln223_35_fu_107861_p2[31:4]}}; + +assign tmp_396_fu_107670_p4 = {{add_ln223_36_fu_107665_p2[31:1]}}; + +assign tmp_397_fu_107686_p4 = {{add_ln223_36_fu_107665_p2[31:4]}}; + +assign tmp_399_fu_104769_p4 = {{add_ln223_37_fu_104760_p2[31:1]}}; + +assign tmp_400_fu_104785_p4 = {{add_ln223_37_fu_104760_p2[31:4]}}; + +assign tmp_406_fu_113711_p4 = {{add_ln223_38_fu_113706_p2[31:1]}}; + +assign tmp_407_fu_113727_p4 = {{add_ln223_38_fu_113706_p2[31:4]}}; + +assign tmp_413_fu_114700_p4 = {{add_ln223_39_fu_114695_p2[31:1]}}; + +assign tmp_414_fu_114716_p4 = {{add_ln223_39_fu_114695_p2[31:4]}}; + +assign tmp_415_fu_114504_p4 = {{add_ln223_40_fu_114499_p2[31:1]}}; + +assign tmp_416_fu_114520_p4 = {{add_ln223_40_fu_114499_p2[31:4]}}; + +assign tmp_418_fu_111623_p4 = {{add_ln223_41_fu_111614_p2[31:1]}}; + +assign tmp_419_fu_111639_p4 = {{add_ln223_41_fu_111614_p2[31:4]}}; + +assign tmp_421_fu_108182_p4 = {{add_ln223_42_fu_108173_p2[31:1]}}; + +assign tmp_422_fu_108198_p4 = {{add_ln223_42_fu_108173_p2[31:4]}}; + +assign tmp_436_fu_115016_p4 = {{add_ln223_43_fu_115007_p2[31:1]}}; + +assign tmp_437_fu_115032_p4 = {{add_ln223_43_fu_115007_p2[31:4]}}; + +assign tmp_449_fu_105059_p4 = {{add_ln223_44_fu_105054_p2[31:1]}}; + +assign tmp_450_fu_105075_p4 = {{add_ln223_44_fu_105054_p2[31:4]}}; + +assign tmp_452_fu_111913_p4 = {{add_ln223_45_fu_111908_p2[31:1]}}; + +assign tmp_453_fu_111929_p4 = {{add_ln223_45_fu_111908_p2[31:4]}}; + +assign tmp_454_fu_108471_p4 = {{add_ln223_46_fu_108466_p2[31:1]}}; + +assign tmp_455_fu_108487_p4 = {{add_ln223_46_fu_108466_p2[31:4]}}; + +assign tmp_459_fu_115305_p4 = {{add_ln223_47_fu_115300_p2[31:1]}}; + +assign tmp_460_fu_115321_p4 = {{add_ln223_47_fu_115300_p2[31:4]}}; + +assign tmp_71_fu_103867_p4 = {{sub_ln231_5_fu_103857_p2[6:4]}}; + +assign tmp_89_fu_107282_p4 = {{sub_ln231_9_fu_107272_p2[6:4]}}; + +assign trunc_ln1116_10_fu_110095_p4 = {{add_ln231_32_fu_110081_p2[10:7]}}; + +assign trunc_ln1116_11_fu_106650_p4 = {{add_ln231_35_fu_106636_p2[10:7]}}; + +assign trunc_ln1116_12_fu_110892_p4 = {{add_ln231_38_fu_110878_p2[10:7]}}; + +assign trunc_ln1116_13_fu_113493_p4 = {{add_ln231_44_fu_113479_p2[10:7]}}; + +assign trunc_ln1116_14_fu_114288_p4 = {{add_ln231_47_fu_114274_p2[10:7]}}; + +assign trunc_ln1116_15_fu_103526_p4 = {{add_ln231_50_fu_103512_p2[10:7]}}; + +assign trunc_ln1116_16_fu_104330_p4 = {{add_ln231_53_fu_104316_p2[10:7]}}; + +assign trunc_ln1116_17_fu_110387_p4 = {{add_ln231_56_fu_110373_p2[10:7]}}; + +assign trunc_ln1116_18_fu_106941_p4 = {{add_ln231_59_fu_106927_p2[10:7]}}; + +assign trunc_ln1116_19_fu_111182_p4 = {{add_ln231_62_fu_111168_p2[10:7]}}; + +assign trunc_ln1116_1_fu_109213_p4 = {{add_ln231_5_fu_109199_p2[10:7]}}; + +assign trunc_ln1116_20_fu_107743_p4 = {{add_ln231_65_fu_107729_p2[10:7]}}; + +assign trunc_ln1116_21_fu_104843_p4 = {{add_ln231_68_fu_104829_p2[10:7]}}; + +assign trunc_ln1116_22_fu_113784_p4 = {{add_ln231_71_fu_113770_p2[10:7]}}; + +assign trunc_ln1116_23_fu_114577_p4 = {{add_ln231_74_fu_114563_p2[10:7]}}; + +assign trunc_ln1116_24_fu_111697_p4 = {{add_ln231_77_fu_111683_p2[10:7]}}; + +assign trunc_ln1116_25_fu_108255_p4 = {{add_ln231_80_fu_108241_p2[10:7]}}; + +assign trunc_ln1116_26_fu_115089_p4 = {{add_ln231_83_fu_115075_p2[10:7]}}; + +assign trunc_ln1116_27_fu_105133_p4 = {{add_ln231_84_fu_105119_p2[10:7]}}; + +assign trunc_ln1116_28_fu_111987_p4 = {{add_ln231_85_fu_111973_p2[10:7]}}; + +assign trunc_ln1116_29_fu_108544_p4 = {{add_ln231_86_fu_108530_p2[10:7]}}; + +assign trunc_ln1116_2_fu_105772_p4 = {{add_ln231_8_fu_105758_p2[10:7]}}; + +assign trunc_ln1116_30_fu_115378_p4 = {{add_ln231_87_fu_115364_p2[10:7]}}; + +assign trunc_ln1116_3_fu_112615_p4 = {{add_ln231_11_fu_112601_p2[10:7]}}; + +assign trunc_ln1116_4_fu_102644_p4 = {{add_ln231_14_fu_102630_p2[10:7]}}; + +assign trunc_ln1116_5_fu_109504_p4 = {{add_ln231_17_fu_109490_p2[10:7]}}; + +assign trunc_ln1116_6_fu_106062_p4 = {{add_ln231_20_fu_106048_p2[10:7]}}; + +assign trunc_ln1116_7_fu_103234_p4 = {{add_ln231_23_fu_103220_p2[10:7]}}; + +assign trunc_ln1116_8_fu_104040_p4 = {{add_ln231_26_fu_104026_p2[10:7]}}; + +assign trunc_ln1116_9_fu_112905_p4 = {{add_ln231_29_fu_112891_p2[10:7]}}; + +assign trunc_ln1116_s_fu_107454_p4 = {{add_ln231_41_fu_107440_p2[10:7]}}; + +assign trunc_ln1265_1_fu_124387_p4 = {{add_ln279_3_fu_124377_p2[12:6]}}; + +assign trunc_ln1265_2_fu_120860_p4 = {{add_ln279_5_fu_120850_p2[12:6]}}; + +assign trunc_ln1265_3_fu_117521_p4 = {{add_ln279_6_fu_117511_p2[12:6]}}; + +assign trunc_ln1265_4_fu_127902_p4 = {{add_ln279_8_fu_127892_p2[12:6]}}; + +assign trunc_ln1265_5_fu_124563_p4 = {{add_ln279_9_fu_124553_p2[12:6]}}; + +assign trunc_ln1265_6_fu_120989_p4 = {{add_ln279_10_fu_120979_p2[12:6]}}; + +assign trunc_ln1265_7_fu_128031_p4 = {{add_ln279_11_fu_128021_p2[12:6]}}; + +assign trunc_ln1_fu_102352_p4 = {{add_ln231_2_fu_102338_p2[10:7]}}; + +assign trunc_ln203_1_fu_116598_p4 = {{add_ln250_3_fu_116517_p2[12:6]}}; + +assign trunc_ln203_2_fu_116210_p4 = {{add_ln250_5_fu_116129_p2[12:6]}}; + +assign trunc_ln203_37_fu_109808_p1 = grp_fu_99183_p2[5:0]; + +assign trunc_ln203_38_fu_106360_p1 = grp_fu_99115_p2[5:0]; + +assign trunc_ln203_39_fu_102479_p1 = grp_fu_99047_p2[5:0]; + +assign trunc_ln203_3_fu_116027_p4 = {{add_ln250_8_fu_115948_p2[12:6]}}; + +assign trunc_ln203_40_fu_113203_p1 = grp_fu_99251_p2[5:0]; + +assign trunc_ln203_41_fu_109339_p1 = grp_fu_99183_p2[5:0]; + +assign trunc_ln203_42_fu_105898_p1 = grp_fu_99115_p2[5:0]; + +assign trunc_ln203_43_fu_112741_p1 = grp_fu_99251_p2[5:0]; + +assign trunc_ln203_44_fu_103081_p1 = grp_fu_99053_p2[5:0]; + +assign trunc_ln203_45_fu_109946_p1 = grp_fu_99189_p2[5:0]; + +assign trunc_ln203_46_fu_106498_p1 = grp_fu_99121_p2[5:0]; + +assign trunc_ln203_47_fu_103635_p1 = grp_fu_99064_p2[5:0]; + +assign trunc_ln203_48_fu_103021_p1 = grp_fu_99053_p2[5:0]; + +assign trunc_ln203_49_fu_104552_p1 = grp_fu_99081_p2[5:0]; + +assign trunc_ln203_4_fu_116974_p4 = {{add_ln250_7_fu_116893_p2[12:6]}}; + +assign trunc_ln203_50_fu_113341_p1 = grp_fu_99257_p2[5:0]; + +assign trunc_ln203_51_fu_110496_p1 = grp_fu_99200_p2[5:0]; + +assign trunc_ln203_52_fu_109886_p1 = grp_fu_99189_p2[5:0]; + +assign trunc_ln203_53_fu_107050_p1 = grp_fu_99132_p2[5:0]; + +assign trunc_ln203_54_fu_106438_p1 = grp_fu_99121_p2[5:0]; + +assign trunc_ln203_55_fu_103361_p1 = grp_fu_99064_p2[5:0]; + +assign trunc_ln203_56_fu_111410_p1 = grp_fu_99217_p2[5:0]; + +assign trunc_ln203_57_fu_107965_p1 = grp_fu_99149_p2[5:0]; + +assign trunc_ln203_58_fu_104165_p1 = grp_fu_99081_p2[5:0]; + +assign trunc_ln203_59_fu_113893_p1 = grp_fu_99268_p2[5:0]; + +assign trunc_ln203_5_fu_116791_p4 = {{add_ln250_9_fu_116712_p2[12:6]}}; + +assign trunc_ln203_60_fu_113281_p1 = grp_fu_99257_p2[5:0]; + +assign trunc_ln203_61_fu_110222_p1 = grp_fu_99200_p2[5:0]; + +assign trunc_ln203_62_fu_106777_p1 = grp_fu_99132_p2[5:0]; + +assign trunc_ln203_63_fu_114799_p1 = grp_fu_99285_p2[5:0]; + +assign trunc_ln203_64_fu_111017_p1 = grp_fu_99217_p2[5:0]; + +assign trunc_ln203_65_fu_107579_p1 = grp_fu_99149_p2[5:0]; + +assign trunc_ln203_66_fu_113620_p1 = grp_fu_99268_p2[5:0]; + +assign trunc_ln203_67_fu_114413_p1 = grp_fu_99285_p2[5:0]; + +assign trunc_ln203_68_fu_103773_p1 = grp_fu_99070_p2[5:0]; + +assign trunc_ln203_69_fu_104690_p1 = grp_fu_99087_p2[5:0]; + +assign trunc_ln203_6_fu_116360_p4 = {{add_ln250_10_fu_116281_p2[12:6]}}; + +assign trunc_ln203_70_fu_110634_p1 = grp_fu_99206_p2[5:0]; + +assign trunc_ln203_71_fu_107188_p1 = grp_fu_99138_p2[5:0]; + +assign trunc_ln203_72_fu_103713_p1 = grp_fu_99070_p2[5:0]; + +assign trunc_ln203_73_fu_111548_p1 = grp_fu_99223_p2[5:0]; + +assign trunc_ln203_74_fu_108103_p1 = grp_fu_99155_p2[5:0]; + +assign trunc_ln203_75_fu_105240_p1 = grp_fu_99098_p2[5:0]; + +assign trunc_ln203_76_fu_104630_p1 = grp_fu_99087_p2[5:0]; + +assign trunc_ln203_77_fu_114031_p1 = grp_fu_99274_p2[5:0]; + +assign trunc_ln203_78_fu_110574_p1 = grp_fu_99206_p2[5:0]; + +assign trunc_ln203_79_fu_107128_p1 = grp_fu_99138_p2[5:0]; + +assign trunc_ln203_7_fu_117124_p4 = {{add_ln250_11_fu_117045_p2[12:6]}}; + +assign trunc_ln203_80_fu_114937_p1 = grp_fu_99291_p2[5:0]; + +assign trunc_ln203_81_fu_112094_p1 = grp_fu_99234_p2[5:0]; + +assign trunc_ln203_82_fu_111488_p1 = grp_fu_99223_p2[5:0]; + +assign trunc_ln203_83_fu_108651_p1 = grp_fu_99166_p2[5:0]; + +assign trunc_ln203_84_fu_108043_p1 = grp_fu_99155_p2[5:0]; + +assign trunc_ln203_85_fu_104968_p1 = grp_fu_99098_p2[5:0]; + +assign trunc_ln203_86_fu_113971_p1 = grp_fu_99274_p2[5:0]; + +assign trunc_ln203_87_fu_115485_p1 = grp_fu_99302_p2[5:0]; + +assign trunc_ln203_88_fu_114877_p1 = grp_fu_99291_p2[5:0]; + +assign trunc_ln203_89_fu_111822_p1 = grp_fu_99234_p2[5:0]; + +assign trunc_ln203_90_fu_108380_p1 = grp_fu_99166_p2[5:0]; + +assign trunc_ln203_91_fu_115214_p1 = grp_fu_99302_p2[5:0]; + +assign trunc_ln203_92_fu_105378_p1 = grp_fu_99104_p2[5:0]; + +assign trunc_ln203_93_fu_112232_p1 = grp_fu_99240_p2[5:0]; + +assign trunc_ln203_94_fu_108789_p1 = grp_fu_99172_p2[5:0]; + +assign trunc_ln203_95_fu_105318_p1 = grp_fu_99104_p2[5:0]; + +assign trunc_ln203_96_fu_115623_p1 = grp_fu_99308_p2[5:0]; + +assign trunc_ln203_97_fu_112172_p1 = grp_fu_99240_p2[5:0]; + +assign trunc_ln203_98_fu_108729_p1 = grp_fu_99172_p2[5:0]; + +assign trunc_ln203_99_fu_115563_p1 = grp_fu_99308_p2[5:0]; + +assign trunc_ln203_fu_102943_p1 = grp_fu_99047_p2[5:0]; + +assign trunc_ln203_s_fu_115834_p4 = {{add_ln250_1_fu_115753_p2[12:6]}}; + +assign trunc_ln221_1_fu_108920_p1 = cc_0_1_0_0_reg_93579[1:0]; + +assign trunc_ln221_2_fu_105469_p1 = cc_0_0_1_0_reg_92381[1:0]; + +assign trunc_ln221_3_fu_112323_p1 = cc_0_1_1_0_reg_94765[1:0]; + +assign trunc_ln221_fu_102048_p1 = cc_0_0_0_0_reg_91195[1:0]; + +assign trunc_ln223_10_fu_110017_p1 = fw_0_1_0_0_1_0_reg_93887[3:0]; + +assign trunc_ln223_11_fu_106573_p1 = fw_0_0_1_0_1_0_reg_92689[3:0]; + +assign trunc_ln223_12_fu_110814_p1 = fw_0_1_0_1_0_0_reg_94183[3:0]; + +assign trunc_ln223_13_fu_107377_p1 = fw_0_0_1_1_0_0_reg_92985[3:0]; + +assign trunc_ln223_14_fu_113416_p1 = fw_0_1_1_0_1_0_reg_95073[3:0]; + +assign trunc_ln223_15_fu_114211_p1 = fw_0_1_1_1_0_0_reg_95369[3:0]; + +assign trunc_ln223_16_fu_103396_p1 = fw_0_0_0_0_1_0_reg_91503[3:0]; + +assign trunc_ln223_17_fu_104200_p1 = fw_0_0_0_1_0_0_reg_91799[3:0]; + +assign trunc_ln223_18_fu_110257_p1 = fw_0_1_0_0_1_0_reg_93887[3:0]; + +assign trunc_ln223_19_fu_106812_p1 = fw_0_0_1_0_1_0_reg_92689[3:0]; + +assign trunc_ln223_1_fu_109135_p1 = fw_0_1_0_0_0_0_reg_93603[3:0]; + +assign trunc_ln223_20_fu_111052_p1 = fw_0_1_0_1_0_0_reg_94183[3:0]; + +assign trunc_ln223_21_fu_107614_p1 = fw_0_0_1_1_0_0_reg_92985[3:0]; + +assign trunc_ln223_22_fu_113655_p1 = fw_0_1_1_0_1_0_reg_95073[3:0]; + +assign trunc_ln223_23_fu_114448_p1 = fw_0_1_1_1_0_0_reg_95369[3:0]; + +assign trunc_ln223_24_fu_104765_p1 = fw_0_0_0_1_1_0_reg_92079[3:0]; + +assign trunc_ln223_25_fu_111619_p1 = fw_0_1_0_1_1_0_reg_94463[3:0]; + +assign trunc_ln223_26_fu_108178_p1 = fw_0_0_1_1_1_0_reg_93265[3:0]; + +assign trunc_ln223_27_fu_115012_p1 = fw_0_1_1_1_1_0_reg_95649[3:0]; + +assign trunc_ln223_28_fu_105003_p1 = fw_0_0_0_1_1_0_reg_92079[3:0]; + +assign trunc_ln223_29_fu_111857_p1 = fw_0_1_0_1_1_0_reg_94463[3:0]; + +assign trunc_ln223_2_fu_105695_p1 = fw_0_0_1_0_0_0_reg_92405[3:0]; + +assign trunc_ln223_30_fu_108415_p1 = fw_0_0_1_1_1_0_reg_93265[3:0]; + +assign trunc_ln223_31_fu_115249_p1 = fw_0_1_1_1_1_0_reg_95649[3:0]; + +assign trunc_ln223_3_fu_112538_p1 = fw_0_1_1_0_0_0_reg_94789[3:0]; + +assign trunc_ln223_4_fu_102514_p1 = fw_0_0_0_0_0_0_reg_91219[3:0]; + +assign trunc_ln223_5_fu_109374_p1 = fw_0_1_0_0_0_0_reg_93603[3:0]; + +assign trunc_ln223_6_fu_105933_p1 = fw_0_0_1_0_0_0_reg_92405[3:0]; + +assign trunc_ln223_7_fu_112776_p1 = fw_0_1_1_0_0_0_reg_94789[3:0]; + +assign trunc_ln223_8_fu_103156_p1 = fw_0_0_0_0_1_0_reg_91503[3:0]; + +assign trunc_ln223_9_fu_103962_p1 = fw_0_0_0_1_0_0_reg_91799[3:0]; + +assign trunc_ln223_fu_102274_p1 = fw_0_0_0_0_0_0_reg_91219[3:0]; + +assign trunc_ln231_18_fu_109051_p1 = sub_ln231_1_fu_109045_p2[6:0]; + +assign trunc_ln231_19_fu_109055_p1 = sub_ln231_1_fu_109045_p2[10:0]; + +assign trunc_ln231_20_fu_105600_p1 = sub_ln231_2_fu_105594_p2[10:0]; + +assign trunc_ln231_21_fu_112454_p1 = sub_ln231_3_fu_112448_p2[6:0]; + +assign trunc_ln231_22_fu_112458_p1 = sub_ln231_3_fu_112448_p2[10:0]; + +assign trunc_ln231_23_fu_102834_p1 = sub_ln231_4_fu_102812_p2[6:0]; + +assign trunc_ln231_24_fu_102838_p1 = sub_ln231_4_fu_102812_p2[10:0]; + +assign trunc_ln231_25_fu_103863_p1 = sub_ln231_5_fu_103857_p2[10:0]; + +assign trunc_ln231_26_fu_109700_p1 = sub_ln231_6_fu_109678_p2[6:0]; + +assign trunc_ln231_27_fu_109704_p1 = sub_ln231_6_fu_109678_p2[10:0]; + +assign trunc_ln231_28_fu_106252_p1 = sub_ln231_7_fu_106230_p2[6:0]; + +assign trunc_ln231_29_fu_106256_p1 = sub_ln231_7_fu_106230_p2[10:0]; + +assign trunc_ln231_30_fu_110730_p1 = sub_ln231_8_fu_110724_p2[6:0]; + +assign trunc_ln231_31_fu_110734_p1 = sub_ln231_8_fu_110724_p2[10:0]; + +assign trunc_ln231_32_fu_107278_p1 = sub_ln231_9_fu_107272_p2[10:0]; + +assign trunc_ln231_33_fu_113095_p1 = sub_ln231_10_fu_113073_p2[6:0]; + +assign trunc_ln231_34_fu_113099_p1 = sub_ln231_10_fu_113073_p2[10:0]; + +assign trunc_ln231_35_fu_114127_p1 = sub_ln231_11_fu_114121_p2[6:0]; + +assign trunc_ln231_36_fu_114131_p1 = sub_ln231_11_fu_114121_p2[10:0]; + +assign trunc_ln231_37_fu_104519_p1 = sub_ln231_12_fu_104497_p2[6:0]; + +assign trunc_ln231_38_fu_104523_p1 = sub_ln231_12_fu_104497_p2[10:0]; + +assign trunc_ln231_39_fu_111377_p1 = sub_ln231_13_fu_111355_p2[6:0]; + +assign trunc_ln231_40_fu_111381_p1 = sub_ln231_13_fu_111355_p2[10:0]; + +assign trunc_ln231_41_fu_107932_p1 = sub_ln231_14_fu_107910_p2[6:0]; + +assign trunc_ln231_42_fu_107936_p1 = sub_ln231_14_fu_107910_p2[10:0]; + +assign trunc_ln231_43_fu_114766_p1 = sub_ln231_15_fu_114744_p2[6:0]; + +assign trunc_ln231_44_fu_114770_p1 = sub_ln231_15_fu_114744_p2[10:0]; + +assign trunc_ln231_fu_102179_p1 = sub_ln231_fu_102173_p2[10:0]; + +assign trunc_ln250_4_fu_116493_p1 = add_ln250_2_fu_116488_p2[5:0]; + +assign trunc_ln250_5_fu_115930_p1 = add_ln250_4_fu_115925_p2[5:0]; + +assign trunc_ln250_6_fu_116694_p1 = add_ln250_6_fu_116689_p2[5:0]; + +assign trunc_ln250_fu_115719_p1 = add_ln250_fu_115714_p2[5:0]; + +assign trunc_ln279_10_fu_124349_p1 = add_ln279_2_fu_124344_p2[5:0]; + +assign trunc_ln279_11_fu_117476_p1 = add_ln279_4_fu_117471_p2[5:0]; + +assign trunc_ln279_12_fu_124518_p1 = add_ln279_7_fu_124513_p2[5:0]; + +assign trunc_ln279_fu_117287_p1 = add_ln279_fu_117282_p2[5:0]; + +assign trunc_ln_fu_117345_p4 = {{add_ln279_1_fu_117335_p2[12:6]}}; + +assign zext_ln1116_10_fu_110109_p1 = (sext_ln1116_10_fu_110105_p1); + +assign zext_ln1116_11_fu_106664_p1 = (sext_ln1116_11_fu_106660_p1); + +assign zext_ln1116_12_fu_110906_p1 = (sext_ln1116_12_fu_110902_p1); + +assign zext_ln1116_13_fu_107468_p1 = (sext_ln1116_13_fu_107464_p1); + +assign zext_ln1116_14_fu_113507_p1 = (sext_ln1116_14_fu_113503_p1); + +assign zext_ln1116_15_fu_114302_p1 = (sext_ln1116_15_fu_114298_p1); + +assign zext_ln1116_16_fu_103540_p1 = (sext_ln1116_16_fu_103536_p1); + +assign zext_ln1116_17_fu_104344_p1 = (sext_ln1116_17_fu_104340_p1); + +assign zext_ln1116_18_fu_110401_p1 = (sext_ln1116_18_fu_110397_p1); + +assign zext_ln1116_19_fu_106955_p1 = (sext_ln1116_19_fu_106951_p1); + +assign zext_ln1116_1_fu_109227_p1 = (sext_ln1116_1_fu_109223_p1); + +assign zext_ln1116_20_fu_111196_p1 = (sext_ln1116_20_fu_111192_p1); + +assign zext_ln1116_21_fu_107757_p1 = (sext_ln1116_21_fu_107753_p1); + +assign zext_ln1116_22_fu_104857_p1 = (sext_ln1116_22_fu_104853_p1); + +assign zext_ln1116_23_fu_113798_p1 = (sext_ln1116_23_fu_113794_p1); + +assign zext_ln1116_24_fu_114591_p1 = (sext_ln1116_24_fu_114587_p1); + +assign zext_ln1116_25_fu_111711_p1 = (sext_ln1116_25_fu_111707_p1); + +assign zext_ln1116_26_fu_108269_p1 = (sext_ln1116_26_fu_108265_p1); + +assign zext_ln1116_27_fu_115103_p1 = (sext_ln1116_27_fu_115099_p1); + +assign zext_ln1116_28_fu_105147_p1 = (sext_ln1116_28_fu_105143_p1); + +assign zext_ln1116_29_fu_112001_p1 = (sext_ln1116_29_fu_111997_p1); + +assign zext_ln1116_2_fu_105786_p1 = (sext_ln1116_2_fu_105782_p1); + +assign zext_ln1116_30_fu_108558_p1 = (sext_ln1116_30_fu_108554_p1); + +assign zext_ln1116_31_fu_115392_p1 = (sext_ln1116_31_fu_115388_p1); + +assign zext_ln1116_3_fu_112629_p1 = (sext_ln1116_3_fu_112625_p1); + +assign zext_ln1116_4_fu_102658_p1 = (sext_ln1116_4_fu_102654_p1); + +assign zext_ln1116_5_fu_109518_p1 = (sext_ln1116_5_fu_109514_p1); + +assign zext_ln1116_6_fu_106076_p1 = (sext_ln1116_6_fu_106072_p1); + +assign zext_ln1116_7_fu_103248_p1 = (sext_ln1116_7_fu_103244_p1); + +assign zext_ln1116_8_fu_104054_p1 = (sext_ln1116_8_fu_104050_p1); + +assign zext_ln1116_9_fu_112919_p1 = (sext_ln1116_9_fu_112915_p1); + +assign zext_ln1116_fu_102366_p1 = (sext_ln1116_fu_102362_p1); + +assign zext_ln1265_10_fu_121118_p1 = tmp_266_reg_153496; + +assign zext_ln1265_11_fu_119276_p1 = tmp_267_reg_150655; + +assign zext_ln1265_12_fu_117900_p1 = tmp_269_reg_148779; + +assign zext_ln1265_13_fu_128160_p1 = tmp_274_reg_163337; + +assign zext_ln1265_14_fu_126318_p1 = tmp_275_reg_160496; + +assign zext_ln1265_15_fu_122744_p1 = tmp_276_reg_155556; + +assign zext_ln1265_16_fu_124942_p1 = tmp_280_reg_158620; + +assign zext_ln1265_17_fu_121368_p1 = tmp_281_reg_153680; + +assign zext_ln1265_18_fu_119526_p1 = tmp_282_reg_150839; + +assign zext_ln1265_19_fu_129786_p1 = tmp_293_reg_165397; + +assign zext_ln1265_1_fu_124401_p1 = (sext_ln1265_1_fu_124397_p1); + +assign zext_ln1265_20_fu_128410_p1 = tmp_304_reg_163521; + +assign zext_ln1265_21_fu_126568_p1 = tmp_305_reg_160680; + +assign zext_ln1265_22_fu_122994_p1 = tmp_306_reg_155740; + +assign zext_ln1265_23_fu_118066_p1 = tmp_307_reg_149110; + +assign zext_ln1265_24_fu_118459_p1 = tmp_317_reg_149621; + +assign zext_ln1265_25_fu_130036_p1 = tmp_330_reg_165581; + +assign zext_ln1265_26_fu_125108_p1 = tmp_331_reg_158951; + +assign zext_ln1265_27_fu_121534_p1 = tmp_332_reg_154011; + +assign zext_ln1265_28_fu_119691_p1 = tmp_333_reg_151165; + +assign zext_ln1265_29_fu_125501_p1 = tmp_339_reg_159462; + +assign zext_ln1265_2_fu_120874_p1 = (sext_ln1265_2_fu_120870_p1); + +assign zext_ln1265_30_fu_121927_p1 = tmp_340_reg_154522; + +assign zext_ln1265_31_fu_120083_p1 = tmp_341_reg_151671; + +assign zext_ln1265_32_fu_118276_p1 = tmp_342_reg_149284; + +assign zext_ln1265_33_fu_128576_p1 = tmp_349_reg_163852; + +assign zext_ln1265_34_fu_126733_p1 = tmp_350_reg_161006; + +assign zext_ln1265_35_fu_123159_p1 = tmp_351_reg_156066; + +assign zext_ln1265_36_fu_118698_p1 = tmp_352_reg_149804; + +assign zext_ln1265_37_fu_128969_p1 = tmp_356_reg_164363; + +assign zext_ln1265_38_fu_127125_p1 = tmp_357_reg_161512; + +assign zext_ln1265_39_fu_125318_p1 = tmp_358_reg_159125; + +assign zext_ln1265_3_fu_117535_p1 = (sext_ln1265_3_fu_117531_p1); + +assign zext_ln1265_40_fu_123551_p1 = tmp_359_reg_156572; + +assign zext_ln1265_41_fu_121744_p1 = tmp_360_reg_154185; + +assign zext_ln1265_42_fu_119901_p1 = tmp_361_reg_151339; + +assign zext_ln1265_43_fu_130201_p1 = tmp_363_reg_165907; + +assign zext_ln1265_44_fu_125740_p1 = tmp_364_reg_159645; + +assign zext_ln1265_45_fu_122166_p1 = tmp_365_reg_154705; + +assign zext_ln1265_46_fu_120322_p1 = tmp_366_reg_151854; + +assign zext_ln1265_47_fu_130593_p1 = tmp_370_reg_166413; + +assign zext_ln1265_48_fu_128786_p1 = tmp_371_reg_164026; + +assign zext_ln1265_49_fu_126943_p1 = tmp_372_reg_161180; + +assign zext_ln1265_4_fu_127916_p1 = (sext_ln1265_4_fu_127912_p1); + +assign zext_ln1265_50_fu_123369_p1 = tmp_373_reg_156240; + +assign zext_ln1265_51_fu_129208_p1 = tmp_379_reg_164546; + +assign zext_ln1265_52_fu_127364_p1 = tmp_380_reg_161695; + +assign zext_ln1265_53_fu_123790_p1 = tmp_381_reg_156755; + +assign zext_ln1265_54_fu_118864_p1 = tmp_382_reg_150135; + +assign zext_ln1265_55_fu_130411_p1 = tmp_388_reg_166081; + +assign zext_ln1265_56_fu_130832_p1 = tmp_402_reg_166596; + +assign zext_ln1265_57_fu_125906_p1 = tmp_403_reg_159976; + +assign zext_ln1265_58_fu_122332_p1 = tmp_404_reg_155036; + +assign zext_ln1265_59_fu_120487_p1 = tmp_405_reg_152180; + +assign zext_ln1265_5_fu_124577_p1 = (sext_ln1265_5_fu_124573_p1); + +assign zext_ln1265_60_fu_119074_p1 = tmp_412_reg_150309; + +assign zext_ln1265_61_fu_129374_p1 = tmp_424_reg_164877; + +assign zext_ln1265_62_fu_127529_p1 = tmp_425_reg_162021; + +assign zext_ln1265_63_fu_123955_p1 = tmp_426_reg_157081; + +assign zext_ln1265_64_fu_126116_p1 = tmp_433_reg_160150; + +assign zext_ln1265_65_fu_122542_p1 = tmp_434_reg_155210; + +assign zext_ln1265_66_fu_120697_p1 = tmp_435_reg_152354; + +assign zext_ln1265_67_fu_130997_p1 = tmp_439_reg_166922; + +assign zext_ln1265_68_fu_129584_p1 = tmp_444_reg_165051; + +assign zext_ln1265_69_fu_127739_p1 = tmp_445_reg_162195; + +assign zext_ln1265_6_fu_121003_p1 = (sext_ln1265_6_fu_120999_p1); + +assign zext_ln1265_70_fu_124165_p1 = tmp_446_reg_157255; + +assign zext_ln1265_71_fu_131207_p1 = tmp_448_reg_167096; + +assign zext_ln1265_7_fu_128045_p1 = (sext_ln1265_7_fu_128041_p1); + +assign zext_ln1265_8_fu_117650_p1 = tmp_261_reg_148595; + +assign zext_ln1265_9_fu_124692_p1 = tmp_265_reg_158436; + +assign zext_ln1265_fu_117359_p1 = (sext_ln1265_fu_117355_p1); + +assign zext_ln199_fu_101964_p1 = or_ln199_fu_101958_p2; + +assign zext_ln201_2_fu_102024_p1 = or_ln201_fu_102018_p2; + +assign zext_ln201_3_fu_108896_p1 = or_ln201_1_fu_108890_p2; + +assign zext_ln203_10_fu_116612_p1 = (sext_ln203_3_fu_116608_p1); + +assign zext_ln203_12_fu_116224_p1 = (sext_ln203_4_fu_116220_p1); + +assign zext_ln203_13_fu_102947_p1 = tmp_249_reg_132604; + +assign zext_ln203_14_fu_105419_p1 = ff_0_0_1_reg_92359; + +assign zext_ln203_15_fu_116988_p1 = (sext_ln203_6_fu_116984_p1); + +assign zext_ln203_17_fu_116041_p1 = (sext_ln203_5_fu_116037_p1); + +assign zext_ln203_18_fu_109812_p1 = tmp_256_reg_139786; + +assign zext_ln203_19_fu_106364_p1 = tmp_257_reg_136175; + +assign zext_ln203_20_fu_102483_p1 = tmp_258_reg_132180; + +assign zext_ln203_22_fu_116805_p1 = (sext_ln203_7_fu_116801_p1); + +assign zext_ln203_23_fu_112273_p1 = ff_0_1_1_reg_94743; + +assign zext_ln203_24_fu_116374_p1 = (sext_ln203_8_fu_116370_p1); + +assign zext_ln203_25_fu_113207_p1 = tmp_262_reg_143335; + +assign zext_ln203_26_fu_109343_p1 = tmp_263_reg_139372; + +assign zext_ln203_27_fu_105902_p1 = tmp_264_reg_135751; + +assign zext_ln203_28_fu_117138_p1 = (sext_ln203_9_fu_117134_p1); + +assign zext_ln203_29_fu_112745_p1 = tmp_268_reg_142915; + +assign zext_ln203_30_fu_103085_p1 = tmp_279_reg_132672; + +assign zext_ln203_31_fu_109950_p1 = tmp_296_reg_139854; + +assign zext_ln203_32_fu_106502_p1 = tmp_299_reg_136243; + +assign zext_ln203_33_fu_103639_p1 = tmp_302_reg_133442; + +assign zext_ln203_34_fu_103025_p1 = tmp_303_reg_132654; + +assign zext_ln203_35_fu_104556_p1 = tmp_316_reg_134344; + +assign zext_ln203_36_fu_113345_p1 = tmp_320_reg_143403; + +assign zext_ln203_37_fu_110500_p1 = tmp_323_reg_140620; + +assign zext_ln203_38_fu_109890_p1 = tmp_324_reg_139836; + +assign zext_ln203_39_fu_107054_p1 = tmp_327_reg_137013; + +assign zext_ln203_40_fu_106442_p1 = tmp_328_reg_136225; + +assign zext_ln203_41_fu_103365_p1 = tmp_329_reg_133076; + +assign zext_ln203_42_fu_111414_p1 = tmp_336_reg_141511; + +assign zext_ln203_43_fu_107969_p1 = tmp_337_reg_137915; + +assign zext_ln203_44_fu_104169_p1 = tmp_338_reg_133948; + +assign zext_ln203_45_fu_113897_p1 = tmp_345_reg_144173; + +assign zext_ln203_46_fu_113285_p1 = tmp_346_reg_143385; + +assign zext_ln203_47_fu_110226_p1 = tmp_347_reg_140254; + +assign zext_ln203_48_fu_106781_p1 = tmp_348_reg_136647; + +assign zext_ln203_49_fu_114803_p1 = tmp_353_reg_145070; + +assign zext_ln203_4_fu_101984_p1 = ff_0_0_0_reg_91173; + +assign zext_ln203_50_fu_111021_p1 = tmp_354_reg_141121; + +assign zext_ln203_51_fu_107583_p1 = tmp_355_reg_137519; + +assign zext_ln203_52_fu_113624_p1 = tmp_362_reg_143807; + +assign zext_ln203_53_fu_114417_p1 = tmp_367_reg_144674; + +assign zext_ln203_54_fu_103777_p1 = tmp_378_reg_133510; + +assign zext_ln203_55_fu_104694_p1 = tmp_387_reg_134412; + +assign zext_ln203_56_fu_110638_p1 = tmp_393_reg_140688; + +assign zext_ln203_57_fu_107192_p1 = tmp_398_reg_137081; + +assign zext_ln203_58_fu_103717_p1 = tmp_401_reg_133492; + +assign zext_ln203_59_fu_111552_p1 = tmp_408_reg_141579; + +assign zext_ln203_60_fu_108107_p1 = tmp_409_reg_137983; + +assign zext_ln203_61_fu_105244_p1 = tmp_410_reg_135184; + +assign zext_ln203_62_fu_104634_p1 = tmp_411_reg_134394; + +assign zext_ln203_63_fu_114035_p1 = tmp_417_reg_144241; + +assign zext_ln203_64_fu_110578_p1 = tmp_420_reg_140670; + +assign zext_ln203_65_fu_107132_p1 = tmp_423_reg_137063; + +assign zext_ln203_66_fu_114941_p1 = tmp_427_reg_145138; + +assign zext_ln203_67_fu_112098_p1 = tmp_428_reg_142347; + +assign zext_ln203_68_fu_111492_p1 = tmp_429_reg_141561; + +assign zext_ln203_69_fu_108655_p1 = tmp_430_reg_138755; + +assign zext_ln203_70_fu_108047_p1 = tmp_431_reg_137965; + +assign zext_ln203_71_fu_104972_p1 = tmp_432_reg_134823; + +assign zext_ln203_72_fu_113975_p1 = tmp_438_reg_144223; + +assign zext_ln203_73_fu_115489_p1 = tmp_440_reg_145910; + +assign zext_ln203_74_fu_114881_p1 = tmp_441_reg_145120; + +assign zext_ln203_75_fu_111826_p1 = tmp_442_reg_141986; + +assign zext_ln203_76_fu_108384_p1 = tmp_443_reg_138394; + +assign zext_ln203_77_fu_115218_p1 = tmp_447_reg_145549; + +assign zext_ln203_78_fu_105382_p1 = tmp_451_reg_135252; + +assign zext_ln203_79_fu_112236_p1 = tmp_456_reg_142415; + +assign zext_ln203_80_fu_108793_p1 = tmp_457_reg_138823; + +assign zext_ln203_81_fu_105322_p1 = tmp_458_reg_135234; + +assign zext_ln203_82_fu_115627_p1 = tmp_461_reg_145978; + +assign zext_ln203_83_fu_112176_p1 = tmp_462_reg_142397; + +assign zext_ln203_84_fu_108733_p1 = tmp_463_reg_138805; + +assign zext_ln203_85_fu_115567_p1 = tmp_464_reg_145960; + +assign zext_ln203_8_fu_115848_p1 = (sext_ln203_fu_115844_p1); + +assign zext_ln203_9_fu_108856_p1 = ff_0_1_0_reg_93557; + +assign zext_ln216_10_fu_106308_p1 = grp_fu_131366_p3; + +assign zext_ln216_11_fu_113151_p1 = grp_fu_131398_p3; + +assign zext_ln216_12_fu_105435_p1 = phi_mul135689_reg_92370; + +assign zext_ln216_13_fu_105444_p1 = add_ln216_7_fu_105439_p2; + +assign zext_ln216_14_fu_112289_p1 = phi_mul135727_reg_94754; + +assign zext_ln216_15_fu_112298_p1 = add_ln216_13_fu_112293_p2; + +assign zext_ln216_1_fu_102009_p1 = add_ln216_fu_102004_p2; + +assign zext_ln216_2_fu_108872_p1 = phi_mul135708_reg_93568; + +assign zext_ln216_3_fu_102091_p1 = grp_fu_131342_p3; + +assign zext_ln216_4_fu_108881_p1 = add_ln216_2_fu_108876_p2; + +assign zext_ln216_5_fu_108963_p1 = grp_fu_131374_p3; + +assign zext_ln216_6_fu_105512_p1 = grp_fu_131358_p3; + +assign zext_ln216_7_fu_112366_p1 = grp_fu_131390_p3; + +assign zext_ln216_8_fu_102890_p1 = grp_fu_131350_p3; + +assign zext_ln216_9_fu_109756_p1 = grp_fu_131382_p3; + +assign zext_ln216_fu_102000_p1 = phi_mul_reg_91184; + +assign zext_ln221_10_fu_112335_p1 = shl_ln221_s_fu_112327_p3; + +assign zext_ln221_11_fu_112347_p1 = shl_ln221_2_fu_112339_p3; + +assign zext_ln221_13_fu_102859_p1 = shl_ln221_3_fu_102851_p3; + +assign zext_ln221_14_fu_102871_p1 = shl_ln221_8_fu_102863_p3; + +assign zext_ln221_16_fu_109725_p1 = shl_ln221_9_fu_109717_p3; + +assign zext_ln221_17_fu_109737_p1 = shl_ln221_10_fu_109729_p3; + +assign zext_ln221_19_fu_106277_p1 = shl_ln221_11_fu_106269_p3; + +assign zext_ln221_1_fu_102060_p1 = shl_ln2_fu_102052_p3; + +assign zext_ln221_20_fu_106289_p1 = shl_ln221_12_fu_106281_p3; + +assign zext_ln221_22_fu_113120_p1 = shl_ln221_13_fu_113112_p3; + +assign zext_ln221_23_fu_113132_p1 = shl_ln221_14_fu_113124_p3; + +assign zext_ln221_2_fu_102072_p1 = shl_ln221_1_fu_102064_p3; + +assign zext_ln221_4_fu_108932_p1 = shl_ln221_4_fu_108924_p3; + +assign zext_ln221_5_fu_108944_p1 = shl_ln221_5_fu_108936_p3; + +assign zext_ln221_7_fu_105481_p1 = shl_ln221_6_fu_105473_p3; + +assign zext_ln221_8_fu_105493_p1 = shl_ln221_7_fu_105485_p3; + +assign zext_ln231_10_fu_105754_p1 = shl_ln231_s_fu_105742_p3; + +assign zext_ln231_11_fu_112593_p1 = shl_ln231_1_fu_112585_p3; + +assign zext_ln231_12_fu_112597_p1 = shl_ln231_1_fu_112585_p3; + +assign zext_ln231_13_fu_102919_p1 = or_ln231_10_fu_102911_p3; + +assign zext_ln231_14_fu_102622_p1 = shl_ln231_2_fu_102614_p3; + +assign zext_ln231_15_fu_102626_p1 = shl_ln231_2_fu_102614_p3; + +assign zext_ln231_16_fu_109781_p1 = or_ln231_13_fu_109773_p3; + +assign zext_ln231_17_fu_106337_p1 = or_ln231_15_fu_106329_p3; + +assign zext_ln231_18_fu_109482_p1 = shl_ln231_3_fu_109474_p3; + +assign zext_ln231_19_fu_109486_p1 = shl_ln231_3_fu_109474_p3; + +assign zext_ln231_1_fu_108982_p1 = or_ln231_3_fu_108974_p3; + +assign zext_ln231_20_fu_106040_p1 = shl_ln231_4_fu_106032_p3; + +assign zext_ln231_21_fu_106044_p1 = shl_ln231_4_fu_106032_p3; + +assign zext_ln231_22_fu_103212_p1 = shl_ln231_5_fu_103204_p3; + +assign zext_ln231_23_fu_103216_p1 = shl_ln231_5_fu_103204_p3; + +assign zext_ln231_24_fu_113176_p1 = or_ln231_18_fu_113168_p3; + +assign zext_ln231_25_fu_104018_p1 = shl_ln231_7_fu_104010_p3; + +assign zext_ln231_26_fu_104022_p1 = shl_ln231_7_fu_104010_p3; + +assign zext_ln231_27_fu_112883_p1 = shl_ln231_8_fu_112875_p3; + +assign zext_ln231_28_fu_112887_p1 = shl_ln231_8_fu_112875_p3; + +assign zext_ln231_29_fu_110073_p1 = shl_ln231_10_fu_110065_p3; + +assign zext_ln231_2_fu_105535_p1 = or_ln231_5_fu_105527_p3; + +assign zext_ln231_30_fu_110077_p1 = shl_ln231_10_fu_110065_p3; + +assign zext_ln231_31_fu_106628_p1 = shl_ln231_11_fu_106620_p3; + +assign zext_ln231_32_fu_106632_p1 = shl_ln231_11_fu_106620_p3; + +assign zext_ln231_33_fu_110870_p1 = shl_ln231_12_fu_110862_p3; + +assign zext_ln231_34_fu_110874_p1 = shl_ln231_12_fu_110862_p3; + +assign zext_ln231_35_fu_107432_p1 = shl_ln231_13_fu_107424_p3; + +assign zext_ln231_36_fu_107436_p1 = shl_ln231_13_fu_107424_p3; + +assign zext_ln231_37_fu_113471_p1 = shl_ln231_14_fu_113463_p3; + +assign zext_ln231_38_fu_113475_p1 = shl_ln231_14_fu_113463_p3; + +assign zext_ln231_39_fu_114266_p1 = shl_ln231_15_fu_114258_p3; + +assign zext_ln231_3_fu_112385_p1 = or_ln231_7_fu_112377_p3; + +assign zext_ln231_40_fu_114270_p1 = shl_ln231_15_fu_114258_p3; + +assign zext_ln231_41_fu_103504_p1 = shl_ln231_22_fu_103496_p3; + +assign zext_ln231_42_fu_103508_p1 = shl_ln231_22_fu_103496_p3; + +assign zext_ln231_43_fu_104308_p1 = shl_ln231_25_fu_104300_p3; + +assign zext_ln231_44_fu_104312_p1 = shl_ln231_25_fu_104300_p3; + +assign zext_ln231_45_fu_110365_p1 = shl_ln231_26_fu_110357_p3; + +assign zext_ln231_46_fu_110369_p1 = shl_ln231_26_fu_110357_p3; + +assign zext_ln231_47_fu_106919_p1 = shl_ln231_29_fu_106911_p3; + +assign zext_ln231_48_fu_106923_p1 = shl_ln231_29_fu_106911_p3; + +assign zext_ln231_49_fu_111160_p1 = shl_ln231_32_fu_111152_p3; + +assign zext_ln231_50_fu_111164_p1 = shl_ln231_32_fu_111152_p3; + +assign zext_ln231_51_fu_107721_p1 = shl_ln231_33_fu_107713_p3; + +assign zext_ln231_52_fu_107725_p1 = shl_ln231_33_fu_107713_p3; + +assign zext_ln231_53_fu_104821_p1 = shl_ln231_34_fu_104813_p3; + +assign zext_ln231_54_fu_104825_p1 = shl_ln231_34_fu_104813_p3; + +assign zext_ln231_55_fu_113762_p1 = shl_ln231_35_fu_113754_p3; + +assign zext_ln231_56_fu_113766_p1 = shl_ln231_35_fu_113754_p3; + +assign zext_ln231_57_fu_114555_p1 = shl_ln231_36_fu_114547_p3; + +assign zext_ln231_58_fu_114559_p1 = shl_ln231_36_fu_114547_p3; + +assign zext_ln231_59_fu_111675_p1 = shl_ln231_37_fu_111667_p3; + +assign zext_ln231_5_fu_102330_p1 = shl_ln231_6_fu_102322_p3; + +assign zext_ln231_60_fu_111679_p1 = shl_ln231_37_fu_111667_p3; + +assign zext_ln231_61_fu_108233_p1 = shl_ln231_38_fu_108225_p3; + +assign zext_ln231_62_fu_108237_p1 = shl_ln231_38_fu_108225_p3; + +assign zext_ln231_63_fu_115067_p1 = shl_ln231_41_fu_115059_p3; + +assign zext_ln231_64_fu_115071_p1 = shl_ln231_41_fu_115059_p3; + +assign zext_ln231_65_fu_105111_p1 = shl_ln231_42_fu_105103_p3; + +assign zext_ln231_66_fu_105115_p1 = shl_ln231_42_fu_105103_p3; + +assign zext_ln231_67_fu_111965_p1 = shl_ln231_45_fu_111957_p3; + +assign zext_ln231_68_fu_111969_p1 = shl_ln231_45_fu_111957_p3; + +assign zext_ln231_69_fu_108522_p1 = shl_ln231_48_fu_108514_p3; + +assign zext_ln231_6_fu_102334_p1 = shl_ln231_6_fu_102322_p3; + +assign zext_ln231_70_fu_108526_p1 = shl_ln231_48_fu_108514_p3; + +assign zext_ln231_71_fu_115356_p1 = shl_ln231_49_fu_115348_p3; + +assign zext_ln231_72_fu_115360_p1 = shl_ln231_49_fu_115348_p3; + +assign zext_ln231_7_fu_109191_p1 = shl_ln231_9_fu_109183_p3; + +assign zext_ln231_8_fu_109195_p1 = shl_ln231_9_fu_109183_p3; + +assign zext_ln231_9_fu_105750_p1 = shl_ln231_s_fu_105742_p3; + +assign zext_ln231_fu_102114_p1 = or_ln231_1_fu_102106_p3; + +assign zext_ln232_10_fu_110086_p1 = add_ln221_24_fu_110007_p2; + +assign zext_ln232_11_fu_106641_p1 = add_ln221_26_fu_106563_p2; + +assign zext_ln232_12_fu_110883_p1 = add_ln221_29_fu_110804_p2; + +assign zext_ln232_13_fu_107445_p1 = add_ln221_32_fu_107367_p2; + +assign zext_ln232_14_fu_113484_p1 = add_ln221_34_fu_113406_p2; + +assign zext_ln232_15_fu_114279_p1 = add_ln221_37_fu_114201_p2; + +assign zext_ln232_16_fu_103517_p1 = add_ln221_38_fu_103436_p2; + +assign zext_ln232_17_fu_104321_p1 = add_ln221_39_fu_104240_p2; + +assign zext_ln232_18_fu_110378_p1 = add_ln221_40_fu_110297_p2; + +assign zext_ln232_19_fu_106932_p1 = add_ln221_41_fu_106852_p2; + +assign zext_ln232_1_fu_109204_p1 = add_ln221_7_fu_109125_p2; + +assign zext_ln232_20_fu_111173_p1 = add_ln221_42_fu_111092_p2; + +assign zext_ln232_21_fu_107734_p1 = add_ln221_43_fu_107654_p2; + +assign zext_ln232_22_fu_104834_p1 = add_ln221_45_fu_104755_p2; + +assign zext_ln232_23_fu_113775_p1 = add_ln221_46_fu_113695_p2; + +assign zext_ln232_24_fu_114568_p1 = add_ln221_47_fu_114488_p2; + +assign zext_ln232_25_fu_111688_p1 = add_ln221_49_fu_111609_p2; + +assign zext_ln232_26_fu_108246_p1 = add_ln221_51_fu_108168_p2; + +assign zext_ln232_27_fu_115080_p1 = add_ln221_53_fu_115002_p2; + +assign zext_ln232_28_fu_105124_p1 = add_ln221_54_fu_105043_p2; + +assign zext_ln232_29_fu_111978_p1 = add_ln221_55_fu_111897_p2; + +assign zext_ln232_2_fu_105763_p1 = add_ln221_10_fu_105685_p2; + +assign zext_ln232_30_fu_108535_p1 = add_ln221_56_fu_108455_p2; + +assign zext_ln232_31_fu_115369_p1 = add_ln221_57_fu_115289_p2; + +assign zext_ln232_3_fu_112606_p1 = add_ln221_13_fu_112528_p2; + +assign zext_ln232_4_fu_102635_p1 = add_ln221_14_fu_102554_p2; + +assign zext_ln232_5_fu_109495_p1 = add_ln221_15_fu_109414_p2; + +assign zext_ln232_6_fu_106053_p1 = add_ln221_16_fu_105973_p2; + +assign zext_ln232_7_fu_103225_p1 = add_ln221_18_fu_103146_p2; + +assign zext_ln232_8_fu_104031_p1 = add_ln221_21_fu_103952_p2; + +assign zext_ln232_9_fu_112896_p1 = add_ln221_22_fu_112816_p2; + +assign zext_ln232_fu_102343_p1 = add_ln221_4_fu_102264_p2; + +assign zext_ln248_1_fu_116704_p1 = or_ln248_1_fu_116698_p2; + +assign zext_ln248_2_fu_116273_p1 = or_ln248_2_fu_116267_p2; + +assign zext_ln248_3_fu_117037_p1 = or_ln248_3_fu_117031_p2; + +assign zext_ln248_fu_115940_p1 = or_ln248_fu_115934_p2; + +assign zext_ln250_10_fu_116125_p1 = ff4_0_0_1_0_reg_95965; + +assign zext_ln250_11_fu_115944_p1 = or_ln248_fu_115934_p2; + +assign zext_ln250_12_fu_116889_p1 = ff4_0_1_1_0_reg_96001; + +assign zext_ln250_13_fu_116708_p1 = or_ln248_1_fu_116698_p2; + +assign zext_ln250_14_fu_116277_p1 = or_ln248_2_fu_116267_p2; + +assign zext_ln250_15_fu_117041_p1 = or_ln248_3_fu_117031_p2; + +assign zext_ln250_1_fu_115700_p1 = shl_ln250_1_fu_115692_p3; + +assign zext_ln250_2_fu_116462_p1 = shl_ln250_2_fu_116454_p3; + +assign zext_ln250_3_fu_116474_p1 = shl_ln250_3_fu_116466_p3; + +assign zext_ln250_4_fu_115899_p1 = shl_ln250_4_fu_115891_p3; + +assign zext_ln250_5_fu_115911_p1 = shl_ln250_5_fu_115903_p3; + +assign zext_ln250_6_fu_115749_p1 = ff4_0_0_0_0_reg_95953; + +assign zext_ln250_7_fu_116663_p1 = shl_ln250_6_fu_116655_p3; + +assign zext_ln250_8_fu_116675_p1 = shl_ln250_7_fu_116667_p3; + +assign zext_ln250_9_fu_116513_p1 = ff4_0_1_0_0_reg_95989; + +assign zext_ln250_fu_115688_p1 = shl_ln_fu_115680_p3; + +assign zext_ln261_1_fu_117503_p1 = or_ln261_fu_117493_p2; + +assign zext_ln261_3_fu_124545_p1 = or_ln261_1_fu_124535_p2; + +assign zext_ln261_5_fu_120971_p1 = or_ln261_2_fu_120961_p2; + +assign zext_ln261_7_fu_128013_p1 = or_ln261_3_fu_128003_p2; + +assign zext_ln276_10_fu_121346_p1 = grp_fu_131488_p3; + +assign zext_ln276_11_fu_119504_p1 = grp_fu_131458_p3; + +assign zext_ln276_12_fu_128388_p1 = grp_fu_131594_p3; + +assign zext_ln276_13_fu_126546_p1 = grp_fu_131564_p3; + +assign zext_ln276_14_fu_122972_p1 = grp_fu_131504_p3; + +assign zext_ln276_15_fu_130014_p1 = grp_fu_131610_p3; + +assign zext_ln276_1_fu_124532_p1 = grp_fu_131533_p3; + +assign zext_ln276_2_fu_120958_p1 = grp_fu_131473_p3; + +assign zext_ln276_3_fu_119220_p1 = grp_fu_131450_p3; + +assign zext_ln276_4_fu_128000_p1 = grp_fu_131579_p3; + +assign zext_ln276_5_fu_126262_p1 = grp_fu_131556_p3; + +assign zext_ln276_6_fu_122688_p1 = grp_fu_131496_p3; + +assign zext_ln276_7_fu_129730_p1 = grp_fu_131602_p3; + +assign zext_ln276_8_fu_117878_p1 = grp_fu_131442_p3; + +assign zext_ln276_9_fu_124920_p1 = grp_fu_131548_p3; + +assign zext_ln276_fu_117490_p1 = grp_fu_131427_p3; + +assign zext_ln279_10_fu_117457_p1 = shl_ln279_5_fu_117449_p3; + +assign zext_ln279_12_fu_117331_p1 = ff7_0_0_0_0_reg_96037; + +assign zext_ln279_14_fu_124487_p1 = shl_ln279_6_fu_124479_p3; + +assign zext_ln279_15_fu_124499_p1 = shl_ln279_7_fu_124491_p3; + +assign zext_ln279_17_fu_124373_p1 = ff7_0_1_0_0_reg_97545; + +assign zext_ln279_19_fu_120846_p1 = ff7_0_0_1_0_reg_96785; + +assign zext_ln279_21_fu_117507_p1 = or_ln261_fu_117493_p2; + +assign zext_ln279_23_fu_127888_p1 = ff7_0_1_1_0_reg_98293; + +assign zext_ln279_25_fu_124549_p1 = or_ln261_1_fu_124535_p2; + +assign zext_ln279_27_fu_120975_p1 = or_ln261_2_fu_120961_p2; + +assign zext_ln279_29_fu_128017_p1 = or_ln261_3_fu_128003_p2; + +assign zext_ln279_3_fu_117256_p1 = shl_ln1_fu_117248_p3; + +assign zext_ln279_4_fu_117268_p1 = shl_ln279_1_fu_117260_p3; + +assign zext_ln279_6_fu_124318_p1 = shl_ln279_2_fu_124310_p3; + +assign zext_ln279_7_fu_124330_p1 = shl_ln279_3_fu_124322_p3; + +assign zext_ln279_9_fu_117445_p1 = shl_ln279_4_fu_117437_p3; + +always @ (posedge ap_clk) begin + add_ln1116_8_reg_133570[0] <= 1'b1; + add_ln1116_17_reg_133975[0] <= 1'b1; + add_ln1116_22_reg_134445[0] <= 1'b1; + add_ln1116_28_reg_134850[0] <= 1'b1; + add_ln1116_13_reg_137141[0] <= 1'b1; + add_ln1116_21_reg_137546[0] <= 1'b1; + add_ln1116_26_reg_138016[0] <= 1'b1; + add_ln1116_30_reg_138421[0] <= 1'b1; + add_ln1116_12_reg_140743[0] <= 1'b1; + add_ln1116_20_reg_141148[0] <= 1'b1; + add_ln1116_25_reg_141608[0] <= 1'b1; + add_ln1116_29_reg_142013[0] <= 1'b1; + add_ln1116_15_reg_144296[0] <= 1'b1; + add_ln1116_24_reg_144701[0] <= 1'b1; + add_ln1116_27_reg_145171[0] <= 1'b1; + add_ln1116_31_reg_145576[0] <= 1'b1; + oh_0_0_cast_reg_131618[31:4] <= 28'b0000000000000000000000000000; + mul_ln201_reg_131633[4:0] <= 5'b00000; + ow_0_0_0_cast_reg_131639[31:4] <= 28'b0000000000000000000000000000; + mul_ln203_reg_131654[3:0] <= 4'b0000; + zext_ln199_reg_131659[0] <= 1'b1; + zext_ln199_reg_131659[31:4] <= 28'b0000000000000000000000000000; + mul_ln201_1_reg_131671[4:0] <= 5'b00000; + zext_ln203_4_reg_131682[6:4] <= 3'b000; + or_ln201_reg_131702[0] <= 1'b1; + zext_ln201_2_reg_131714[0] <= 1'b1; + zext_ln201_2_reg_131714[31:4] <= 28'b0000000000000000000000000000; + mul_ln203_2_reg_131726[3:0] <= 4'b0000; + zext_ln216_3_reg_131745[31:18] <= 14'b00000000000000; + sext_ln231_reg_131751[10:3] <= 8'b11110001; + zext_ln231_reg_131757[6:3] <= 4'b0001; + trunc_ln231_reg_131766[2:0] <= 3'b000; + or_ln231_8_reg_131794[3] <= 1'b1; + zext_ln232_reg_131804[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_4_reg_132202[63:32] <= 32'b00000000000000000000000000000000; + trunc_ln231_23_reg_132561[2:0] <= 3'b000; + trunc_ln231_24_reg_132566[2:0] <= 3'b000; + zext_ln216_8_reg_132577[31:18] <= 14'b00000000000000; + or_ln231_reg_132583[0] <= 1'b1; + sext_ln231_4_reg_132588[0] <= 1'b1; + sext_ln231_4_reg_132588[10:3] <= 8'b11110001; + zext_ln231_13_reg_132594[0] <= 1'b1; + zext_ln231_13_reg_132594[6:3] <= 4'b0001; + zext_ln232_7_reg_132700[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_16_reg_133098[63:32] <= 32'b00000000000000000000000000000000; + trunc_ln231_25_reg_133528[2:0] <= 3'b000; + or_ln231_11_reg_133533[0] <= 1'b1; + or_ln231_11_reg_133533[3] <= 1'b1; + add_ln231_18_reg_133555[0] <= 1'b1; + zext_ln232_8_reg_133565[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_17_reg_133970[63:32] <= 32'b00000000000000000000000000000000; + trunc_ln231_37_reg_134324[2:0] <= 3'b000; + trunc_ln231_38_reg_134329[2:0] <= 3'b000; + add_ln231_54_reg_134424[0] <= 1'b1; + add_ln231_55_reg_134430[0] <= 1'b1; + zext_ln232_22_reg_134440[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_28_reg_134845[63:32] <= 32'b00000000000000000000000000000000; + zext_ln203_14_reg_135265[6:4] <= 3'b000; + zext_ln216_6_reg_135304[31:18] <= 14'b00000000000000; + sext_ln231_2_reg_135310[10:3] <= 8'b11110001; + zext_ln231_2_reg_135316[6:3] <= 4'b0001; + trunc_ln231_20_reg_135325[2:0] <= 3'b000; + or_ln231_s_reg_135353[3] <= 1'b1; + zext_ln232_2_reg_135363[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_6_reg_135773[63:32] <= 32'b00000000000000000000000000000000; + trunc_ln231_28_reg_136132[2:0] <= 3'b000; + trunc_ln231_29_reg_136137[2:0] <= 3'b000; + zext_ln216_10_reg_136148[31:18] <= 14'b00000000000000; + or_ln231_20_reg_136154[0] <= 1'b1; + sext_ln231_6_reg_136159[0] <= 1'b1; + sext_ln231_6_reg_136159[10:3] <= 8'b11110001; + zext_ln231_17_reg_136165[0] <= 1'b1; + zext_ln231_17_reg_136165[6:3] <= 4'b0001; + zext_ln232_11_reg_136271[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_19_reg_136669[63:32] <= 32'b00000000000000000000000000000000; + trunc_ln231_32_reg_137099[2:0] <= 3'b000; + or_ln231_16_reg_137104[0] <= 1'b1; + or_ln231_16_reg_137104[3] <= 1'b1; + add_ln231_31_reg_137126[0] <= 1'b1; + zext_ln232_13_reg_137136[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_21_reg_137541[63:32] <= 32'b00000000000000000000000000000000; + trunc_ln231_41_reg_137895[2:0] <= 3'b000; + trunc_ln231_42_reg_137900[2:0] <= 3'b000; + add_ln231_64_reg_137995[0] <= 1'b1; + add_ln231_66_reg_138001[0] <= 1'b1; + zext_ln232_26_reg_138011[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_30_reg_138416[63:32] <= 32'b00000000000000000000000000000000; + ow_0_1_0_cast_reg_138831[31:4] <= 28'b0000000000000000000000000000; + mul_ln203_1_reg_138846[3:0] <= 4'b0000; + zext_ln203_9_reg_138861[6:4] <= 3'b000; + or_ln201_1_reg_138881[0] <= 1'b1; + zext_ln201_3_reg_138893[0] <= 1'b1; + zext_ln201_3_reg_138893[31:4] <= 28'b0000000000000000000000000000; + mul_ln203_3_reg_138905[3:0] <= 4'b0000; + zext_ln216_5_reg_138924[31:19] <= 13'b0000000000000; + zext_ln231_1_reg_138930[6:3] <= 4'b0001; + sext_ln231_1_reg_138936[10:3] <= 8'b11110001; + trunc_ln231_18_reg_138946[2:0] <= 3'b000; + trunc_ln231_19_reg_138951[2:0] <= 3'b000; + zext_ln232_1_reg_138984[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_5_reg_139394[63:32] <= 32'b00000000000000000000000000000000; + trunc_ln231_26_reg_139747[3:0] <= 4'b0000; + trunc_ln231_27_reg_139752[3:0] <= 4'b0000; + zext_ln216_9_reg_139763[31:19] <= 13'b0000000000000; + zext_ln231_16_reg_139769[0] <= 1'b1; + zext_ln231_16_reg_139769[6:3] <= 4'b0001; + sext_ln231_5_reg_139775[0] <= 1'b1; + sext_ln231_5_reg_139775[10:3] <= 8'b11110001; + zext_ln232_10_reg_139878[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_18_reg_140276[63:32] <= 32'b00000000000000000000000000000000; + trunc_ln231_30_reg_140700[2:0] <= 3'b000; + trunc_ln231_31_reg_140705[2:0] <= 3'b000; + add_ln231_27_reg_140722[0] <= 1'b1; + add_ln231_28_reg_140728[0] <= 1'b1; + zext_ln232_12_reg_140738[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_20_reg_141143[63:32] <= 32'b00000000000000000000000000000000; + trunc_ln231_39_reg_141491[3:0] <= 4'b0000; + trunc_ln231_40_reg_141496[3:0] <= 4'b0000; + add_ln231_60_reg_141587[0] <= 1'b1; + add_ln231_61_reg_141593[0] <= 1'b1; + zext_ln232_25_reg_141603[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_29_reg_142008[63:32] <= 32'b00000000000000000000000000000000; + zext_ln203_23_reg_142428[6:4] <= 3'b000; + zext_ln216_7_reg_142467[31:19] <= 13'b0000000000000; + zext_ln231_3_reg_142473[6:3] <= 4'b0001; + sext_ln231_3_reg_142479[10:3] <= 8'b11110001; + trunc_ln231_21_reg_142489[2:0] <= 3'b000; + trunc_ln231_22_reg_142494[2:0] <= 3'b000; + zext_ln232_3_reg_142527[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_9_reg_142937[63:32] <= 32'b00000000000000000000000000000000; + trunc_ln231_33_reg_143296[3:0] <= 4'b0000; + trunc_ln231_34_reg_143301[3:0] <= 4'b0000; + zext_ln216_11_reg_143312[31:19] <= 13'b0000000000000; + zext_ln231_24_reg_143318[0] <= 1'b1; + zext_ln231_24_reg_143318[6:3] <= 4'b0001; + sext_ln231_7_reg_143324[0] <= 1'b1; + sext_ln231_7_reg_143324[10:3] <= 8'b11110001; + zext_ln232_14_reg_143431[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_23_reg_143829[63:32] <= 32'b00000000000000000000000000000000; + trunc_ln231_35_reg_144253[2:0] <= 3'b000; + trunc_ln231_36_reg_144258[2:0] <= 3'b000; + add_ln231_40_reg_144275[0] <= 1'b1; + add_ln231_42_reg_144281[0] <= 1'b1; + zext_ln232_15_reg_144291[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_24_reg_144696[63:32] <= 32'b00000000000000000000000000000000; + trunc_ln231_43_reg_145050[3:0] <= 4'b0000; + trunc_ln231_44_reg_145055[3:0] <= 4'b0000; + add_ln231_73_reg_145150[0] <= 1'b1; + add_ln231_75_reg_145156[0] <= 1'b1; + zext_ln232_27_reg_145166[63:32] <= 32'b00000000000000000000000000000000; + zext_ln232_31_reg_145571[63:32] <= 32'b00000000000000000000000000000000; + mul_ln250_reg_145989[2:0] <= 3'b000; + add_ln250_reg_145998[1:0] <= 2'b00; + trunc_ln250_reg_146004[1:0] <= 2'b00; + mul_ln250_1_reg_146010[2:0] <= 3'b000; + add_ln250_4_reg_146022[2:0] <= 3'b100; + trunc_ln250_5_reg_146028[2:0] <= 3'b100; + add_ln203_7_reg_146071[0] <= 1'b1; + add_ln203_10_reg_146293[0] <= 1'b1; + add_ln250_2_reg_146470[1:0] <= 2'b00; + trunc_ln250_4_reg_146476[1:0] <= 2'b00; + add_ln250_6_reg_146493[2:0] <= 3'b100; + trunc_ln250_6_reg_146499[2:0] <= 3'b100; + add_ln203_9_reg_146542[0] <= 1'b1; + add_ln203_11_reg_146764[0] <= 1'b1; + mul_ln279_2_reg_146941[4:0] <= 5'b00000; + mul_ln279_reg_146947[2:0] <= 3'b000; + add_ln279_reg_147596[1:0] <= 2'b00; + trunc_ln279_reg_147602[1:0] <= 2'b00; + mul_ln279_3_reg_147614[4:0] <= 5'b00000; + mul_ln279_1_reg_147620[2:0] <= 3'b000; + add_ln279_4_reg_147992[2:0] <= 3'b100; + trunc_ln279_11_reg_147998[2:0] <= 3'b100; + zext_ln276_reg_148013[31:18] <= 14'b00000000000000; + add_ln1265_3_reg_148019[0] <= 1'b1; + zext_ln276_8_reg_148768[31:18] <= 14'b00000000000000; + zext_ln276_3_reg_150467[31:18] <= 14'b00000000000000; + zext_ln276_11_reg_150828[31:18] <= 14'b00000000000000; + zext_ln276_2_reg_152914[31:18] <= 14'b00000000000000; + add_ln1265_6_reg_152920[0] <= 1'b1; + zext_ln276_10_reg_153669[31:18] <= 14'b00000000000000; + zext_ln276_6_reg_155368[31:18] <= 14'b00000000000000; + zext_ln276_14_reg_155729[31:18] <= 14'b00000000000000; + add_ln279_2_reg_157413[1:0] <= 2'b00; + trunc_ln279_10_reg_157419[1:0] <= 2'b00; + add_ln279_7_reg_157833[2:0] <= 3'b100; + trunc_ln279_12_reg_157839[2:0] <= 3'b100; + zext_ln276_1_reg_157854[31:19] <= 13'b0000000000000; + add_ln1265_5_reg_157860[0] <= 1'b1; + zext_ln276_9_reg_158609[31:19] <= 13'b0000000000000; + zext_ln276_5_reg_160308[31:19] <= 13'b0000000000000; + zext_ln276_13_reg_160669[31:19] <= 13'b0000000000000; + zext_ln276_4_reg_162755[31:19] <= 13'b0000000000000; + add_ln1265_7_reg_162761[0] <= 1'b1; + zext_ln276_12_reg_163510[31:19] <= 13'b0000000000000; + zext_ln276_7_reg_165209[31:19] <= 13'b0000000000000; + zext_ln276_15_reg_165570[31:19] <= 13'b0000000000000; +end + +endmodule //conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0 +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_w5_V_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 4; +parameter AWIDTH = 11; +parameter MEM_SIZE = 1200; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +`ifdef QUARTUS +initial begin + $readmemh("/home/boutros6/koios++/quartus_runs/rtl/lenet_rom/conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_w5_V_rom.dat", ram); +end +`endif + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_w5_V( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd4; +parameter AddressRange = 32'd1200; +parameter AddressWidth = 32'd11; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_w5_V_rom conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_w5_V_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 8; +parameter AWIDTH = 6; +parameter MEM_SIZE = 49; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd8; +parameter AddressRange = 32'd49; +parameter AddressWidth = 32'd6; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ_ram conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb_ram (addr0, ce0, d0, we0, q0, clk); + +parameter DWIDTH = 8; +parameter AWIDTH = 12; +parameter MEM_SIZE = 2800; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb( + reset, + clk, + address0, + ce0, + we0, + d0, + q0); + +parameter DataWidth = 32'd8; +parameter AddressRange = 32'd2800; +parameter AddressWidth = 32'd12; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; + + + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb_ram conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_idle, + ap_ready, + data_V_address0, + data_V_ce0, + data_V_q0, + res_0_V_address0, + res_0_V_ce0, + res_0_V_we0, + res_0_V_d0, + res_1_V_address0, + res_1_V_ce0, + res_1_V_we0, + res_1_V_d0, + res_2_V_address0, + res_2_V_ce0, + res_2_V_we0, + res_2_V_d0, + res_3_V_address0, + res_3_V_ce0, + res_3_V_we0, + res_3_V_d0, + res_4_V_address0, + res_4_V_ce0, + res_4_V_we0, + res_4_V_d0, + res_5_V_address0, + res_5_V_ce0, + res_5_V_we0, + res_5_V_d0, + res_6_V_address0, + res_6_V_ce0, + res_6_V_we0, + res_6_V_d0, + res_7_V_address0, + res_7_V_ce0, + res_7_V_we0, + res_7_V_d0, + res_8_V_address0, + res_8_V_ce0, + res_8_V_we0, + res_8_V_d0, + res_9_V_address0, + res_9_V_ce0, + res_9_V_we0, + res_9_V_d0, + res_10_V_address0, + res_10_V_ce0, + res_10_V_we0, + res_10_V_d0, + res_11_V_address0, + res_11_V_ce0, + res_11_V_we0, + res_11_V_d0, + res_12_V_address0, + res_12_V_ce0, + res_12_V_we0, + res_12_V_d0, + res_13_V_address0, + res_13_V_ce0, + res_13_V_we0, + res_13_V_d0, + res_14_V_address0, + res_14_V_ce0, + res_14_V_we0, + res_14_V_d0, + res_15_V_address0, + res_15_V_ce0, + res_15_V_we0, + res_15_V_d0, + res_16_V_address0, + res_16_V_ce0, + res_16_V_we0, + res_16_V_d0, + res_17_V_address0, + res_17_V_ce0, + res_17_V_we0, + res_17_V_d0, + res_18_V_address0, + res_18_V_ce0, + res_18_V_we0, + res_18_V_d0, + res_19_V_address0, + res_19_V_ce0, + res_19_V_we0, + res_19_V_d0, + res_20_V_address0, + res_20_V_ce0, + res_20_V_we0, + res_20_V_d0, + res_21_V_address0, + res_21_V_ce0, + res_21_V_we0, + res_21_V_d0, + res_22_V_address0, + res_22_V_ce0, + res_22_V_we0, + res_22_V_d0, + res_23_V_address0, + res_23_V_ce0, + res_23_V_we0, + res_23_V_d0, + res_24_V_address0, + res_24_V_ce0, + res_24_V_we0, + res_24_V_d0, + res_25_V_address0, + res_25_V_ce0, + res_25_V_we0, + res_25_V_d0, + res_26_V_address0, + res_26_V_ce0, + res_26_V_we0, + res_26_V_d0, + res_27_V_address0, + res_27_V_ce0, + res_27_V_we0, + res_27_V_d0, + res_28_V_address0, + res_28_V_ce0, + res_28_V_we0, + res_28_V_d0, + res_29_V_address0, + res_29_V_ce0, + res_29_V_we0, + res_29_V_d0, + res_30_V_address0, + res_30_V_ce0, + res_30_V_we0, + res_30_V_d0, + res_31_V_address0, + res_31_V_ce0, + res_31_V_we0, + res_31_V_d0, + res_32_V_address0, + res_32_V_ce0, + res_32_V_we0, + res_32_V_d0, + res_33_V_address0, + res_33_V_ce0, + res_33_V_we0, + res_33_V_d0, + res_34_V_address0, + res_34_V_ce0, + res_34_V_we0, + res_34_V_d0, + res_35_V_address0, + res_35_V_ce0, + res_35_V_we0, + res_35_V_d0, + res_36_V_address0, + res_36_V_ce0, + res_36_V_we0, + res_36_V_d0, + res_37_V_address0, + res_37_V_ce0, + res_37_V_we0, + res_37_V_d0, + res_38_V_address0, + res_38_V_ce0, + res_38_V_we0, + res_38_V_d0, + res_39_V_address0, + res_39_V_ce0, + res_39_V_we0, + res_39_V_d0, + res_40_V_address0, + res_40_V_ce0, + res_40_V_we0, + res_40_V_d0, + res_41_V_address0, + res_41_V_ce0, + res_41_V_we0, + res_41_V_d0, + res_42_V_address0, + res_42_V_ce0, + res_42_V_we0, + res_42_V_d0, + res_43_V_address0, + res_43_V_ce0, + res_43_V_we0, + res_43_V_d0, + res_44_V_address0, + res_44_V_ce0, + res_44_V_we0, + res_44_V_d0, + res_45_V_address0, + res_45_V_ce0, + res_45_V_we0, + res_45_V_d0, + res_46_V_address0, + res_46_V_ce0, + res_46_V_we0, + res_46_V_d0, + res_47_V_address0, + res_47_V_ce0, + res_47_V_we0, + res_47_V_d0, + res_48_V_address0, + res_48_V_ce0, + res_48_V_we0, + res_48_V_d0, + res_49_V_address0, + res_49_V_ce0, + res_49_V_we0, + res_49_V_d0, + res_50_V_address0, + res_50_V_ce0, + res_50_V_we0, + res_50_V_d0, + res_51_V_address0, + res_51_V_ce0, + res_51_V_we0, + res_51_V_d0, + res_52_V_address0, + res_52_V_ce0, + res_52_V_we0, + res_52_V_d0, + res_53_V_address0, + res_53_V_ce0, + res_53_V_we0, + res_53_V_d0, + res_54_V_address0, + res_54_V_ce0, + res_54_V_we0, + res_54_V_d0, + res_55_V_address0, + res_55_V_ce0, + res_55_V_we0, + res_55_V_d0, + res_56_V_address0, + res_56_V_ce0, + res_56_V_we0, + res_56_V_d0, + res_57_V_address0, + res_57_V_ce0, + res_57_V_we0, + res_57_V_d0, + res_58_V_address0, + res_58_V_ce0, + res_58_V_we0, + res_58_V_d0, + res_59_V_address0, + res_59_V_ce0, + res_59_V_we0, + res_59_V_d0, + res_60_V_address0, + res_60_V_ce0, + res_60_V_we0, + res_60_V_d0, + res_61_V_address0, + res_61_V_ce0, + res_61_V_we0, + res_61_V_d0, + res_62_V_address0, + res_62_V_ce0, + res_62_V_we0, + res_62_V_d0, + res_63_V_address0, + res_63_V_ce0, + res_63_V_we0, + res_63_V_d0, + res_64_V_address0, + res_64_V_ce0, + res_64_V_we0, + res_64_V_d0, + res_65_V_address0, + res_65_V_ce0, + res_65_V_we0, + res_65_V_d0, + res_66_V_address0, + res_66_V_ce0, + res_66_V_we0, + res_66_V_d0, + res_67_V_address0, + res_67_V_ce0, + res_67_V_we0, + res_67_V_d0, + res_68_V_address0, + res_68_V_ce0, + res_68_V_we0, + res_68_V_d0, + res_69_V_address0, + res_69_V_ce0, + res_69_V_we0, + res_69_V_d0, + res_70_V_address0, + res_70_V_ce0, + res_70_V_we0, + res_70_V_d0, + res_71_V_address0, + res_71_V_ce0, + res_71_V_we0, + res_71_V_d0, + res_72_V_address0, + res_72_V_ce0, + res_72_V_we0, + res_72_V_d0, + res_73_V_address0, + res_73_V_ce0, + res_73_V_we0, + res_73_V_d0, + res_74_V_address0, + res_74_V_ce0, + res_74_V_we0, + res_74_V_d0, + res_75_V_address0, + res_75_V_ce0, + res_75_V_we0, + res_75_V_d0, + res_76_V_address0, + res_76_V_ce0, + res_76_V_we0, + res_76_V_d0, + res_77_V_address0, + res_77_V_ce0, + res_77_V_we0, + res_77_V_d0, + res_78_V_address0, + res_78_V_ce0, + res_78_V_we0, + res_78_V_d0, + res_79_V_address0, + res_79_V_ce0, + res_79_V_we0, + res_79_V_d0, + res_80_V_address0, + res_80_V_ce0, + res_80_V_we0, + res_80_V_d0, + res_81_V_address0, + res_81_V_ce0, + res_81_V_we0, + res_81_V_d0, + res_82_V_address0, + res_82_V_ce0, + res_82_V_we0, + res_82_V_d0, + res_83_V_address0, + res_83_V_ce0, + res_83_V_we0, + res_83_V_d0, + res_84_V_address0, + res_84_V_ce0, + res_84_V_we0, + res_84_V_d0, + res_85_V_address0, + res_85_V_ce0, + res_85_V_we0, + res_85_V_d0, + res_86_V_address0, + res_86_V_ce0, + res_86_V_we0, + res_86_V_d0, + res_87_V_address0, + res_87_V_ce0, + res_87_V_we0, + res_87_V_d0, + res_88_V_address0, + res_88_V_ce0, + res_88_V_we0, + res_88_V_d0, + res_89_V_address0, + res_89_V_ce0, + res_89_V_we0, + res_89_V_d0, + res_90_V_address0, + res_90_V_ce0, + res_90_V_we0, + res_90_V_d0, + res_91_V_address0, + res_91_V_ce0, + res_91_V_we0, + res_91_V_d0, + res_92_V_address0, + res_92_V_ce0, + res_92_V_we0, + res_92_V_d0, + res_93_V_address0, + res_93_V_ce0, + res_93_V_we0, + res_93_V_d0, + res_94_V_address0, + res_94_V_ce0, + res_94_V_we0, + res_94_V_d0, + res_95_V_address0, + res_95_V_ce0, + res_95_V_we0, + res_95_V_d0, + res_96_V_address0, + res_96_V_ce0, + res_96_V_we0, + res_96_V_d0, + res_97_V_address0, + res_97_V_ce0, + res_97_V_we0, + res_97_V_d0, + res_98_V_address0, + res_98_V_ce0, + res_98_V_we0, + res_98_V_d0, + res_99_V_address0, + res_99_V_ce0, + res_99_V_we0, + res_99_V_d0, + res_100_V_address0, + res_100_V_ce0, + res_100_V_we0, + res_100_V_d0, + res_101_V_address0, + res_101_V_ce0, + res_101_V_we0, + res_101_V_d0, + res_102_V_address0, + res_102_V_ce0, + res_102_V_we0, + res_102_V_d0, + res_103_V_address0, + res_103_V_ce0, + res_103_V_we0, + res_103_V_d0, + res_104_V_address0, + res_104_V_ce0, + res_104_V_we0, + res_104_V_d0, + res_105_V_address0, + res_105_V_ce0, + res_105_V_we0, + res_105_V_d0, + res_106_V_address0, + res_106_V_ce0, + res_106_V_we0, + res_106_V_d0, + res_107_V_address0, + res_107_V_ce0, + res_107_V_we0, + res_107_V_d0, + res_108_V_address0, + res_108_V_ce0, + res_108_V_we0, + res_108_V_d0, + res_109_V_address0, + res_109_V_ce0, + res_109_V_we0, + res_109_V_d0, + res_110_V_address0, + res_110_V_ce0, + res_110_V_we0, + res_110_V_d0, + res_111_V_address0, + res_111_V_ce0, + res_111_V_we0, + res_111_V_d0, + res_112_V_address0, + res_112_V_ce0, + res_112_V_we0, + res_112_V_d0, + res_113_V_address0, + res_113_V_ce0, + res_113_V_we0, + res_113_V_d0, + res_114_V_address0, + res_114_V_ce0, + res_114_V_we0, + res_114_V_d0, + res_115_V_address0, + res_115_V_ce0, + res_115_V_we0, + res_115_V_d0, + res_116_V_address0, + res_116_V_ce0, + res_116_V_we0, + res_116_V_d0, + res_117_V_address0, + res_117_V_ce0, + res_117_V_we0, + res_117_V_d0, + res_118_V_address0, + res_118_V_ce0, + res_118_V_we0, + res_118_V_d0, + res_119_V_address0, + res_119_V_ce0, + res_119_V_we0, + res_119_V_d0, + res_120_V_address0, + res_120_V_ce0, + res_120_V_we0, + res_120_V_d0, + res_121_V_address0, + res_121_V_ce0, + res_121_V_we0, + res_121_V_d0, + res_122_V_address0, + res_122_V_ce0, + res_122_V_we0, + res_122_V_d0, + res_123_V_address0, + res_123_V_ce0, + res_123_V_we0, + res_123_V_d0, + res_124_V_address0, + res_124_V_ce0, + res_124_V_we0, + res_124_V_d0, + res_125_V_address0, + res_125_V_ce0, + res_125_V_we0, + res_125_V_d0, + res_126_V_address0, + res_126_V_ce0, + res_126_V_we0, + res_126_V_d0, + res_127_V_address0, + res_127_V_ce0, + res_127_V_we0, + res_127_V_d0 +); + +parameter ap_ST_fsm_state1 = 12'd0; +parameter ap_ST_fsm_state2 = 12'd1; +parameter ap_ST_fsm_state3 = 12'd2; +parameter ap_ST_fsm_state4 = 12'd3; +parameter ap_ST_fsm_state5 = 12'd4; +parameter ap_ST_fsm_state6 = 12'd5; +parameter ap_ST_fsm_state7 = 12'd6; +parameter ap_ST_fsm_state8 = 12'd7; +parameter ap_ST_fsm_state9 = 12'd8; +parameter ap_ST_fsm_state10 = 12'd9; +parameter ap_ST_fsm_state11 = 12'd10; +parameter ap_ST_fsm_state12 = 12'd11; +parameter ap_ST_fsm_state13 = 12'd12; +parameter ap_ST_fsm_state14 = 12'd13; +parameter ap_ST_fsm_state15 = 12'd14; +parameter ap_ST_fsm_state16 = 12'd15; +parameter ap_ST_fsm_state17 = 12'd16; +parameter ap_ST_fsm_state18 = 12'd17; +parameter ap_ST_fsm_state19 = 12'd18; +parameter ap_ST_fsm_state20 = 12'd19; +parameter ap_ST_fsm_state21 = 12'd20; +parameter ap_ST_fsm_state22 = 12'd21; +parameter ap_ST_fsm_state23 = 12'd22; +parameter ap_ST_fsm_state24 = 12'd23; +parameter ap_ST_fsm_state25 = 12'd24; +parameter ap_ST_fsm_state26 = 12'd25; +parameter ap_ST_fsm_state27 = 12'd26; +parameter ap_ST_fsm_state28 = 12'd27; +parameter ap_ST_fsm_state29 = 12'd28; +parameter ap_ST_fsm_state30 = 12'd29; +parameter ap_ST_fsm_state31 = 12'd30; +parameter ap_ST_fsm_state32 = 12'd31; +parameter ap_ST_fsm_state33 = 12'd32; +parameter ap_ST_fsm_state34 = 12'd33; +parameter ap_ST_fsm_state35 = 12'd34; +parameter ap_ST_fsm_state36 = 12'd35; +parameter ap_ST_fsm_state37 = 12'd36; +parameter ap_ST_fsm_state38 = 12'd37; +parameter ap_ST_fsm_state39 = 12'd38; +parameter ap_ST_fsm_state40 = 12'd39; +parameter ap_ST_fsm_state41 = 12'd40; +parameter ap_ST_fsm_state42 = 12'd41; +parameter ap_ST_fsm_state43 = 12'd42; +parameter ap_ST_fsm_state44 = 12'd43; +parameter ap_ST_fsm_state45 = 12'd44; +parameter ap_ST_fsm_state46 = 12'd45; +parameter ap_ST_fsm_state47 = 12'd46; +parameter ap_ST_fsm_state48 = 12'd47; +parameter ap_ST_fsm_state49 = 12'd48; +parameter ap_ST_fsm_state50 = 12'd49; +parameter ap_ST_fsm_state51 = 12'd50; +parameter ap_ST_fsm_state52 = 12'd51; +parameter ap_ST_fsm_state53 = 12'd52; +parameter ap_ST_fsm_state54 = 12'd53; +parameter ap_ST_fsm_state55 = 12'd54; +parameter ap_ST_fsm_state56 = 12'd55; +parameter ap_ST_fsm_state57 = 12'd56; +parameter ap_ST_fsm_state58 = 12'd57; +parameter ap_ST_fsm_state59 = 12'd58; +parameter ap_ST_fsm_state60 = 12'd59; +parameter ap_ST_fsm_state61 = 12'd60; +parameter ap_ST_fsm_state62 = 12'd61; +parameter ap_ST_fsm_state63 = 12'd62; +parameter ap_ST_fsm_state64 = 12'd63; +parameter ap_ST_fsm_state65 = 12'd64; +parameter ap_ST_fsm_state66 = 12'd65; +parameter ap_ST_fsm_state67 = 12'd66; +parameter ap_ST_fsm_state68 = 12'd67; +parameter ap_ST_fsm_state69 = 12'd68; +parameter ap_ST_fsm_state70 = 12'd69; +parameter ap_ST_fsm_state71 = 12'd70; +parameter ap_ST_fsm_state72 = 12'd71; +parameter ap_ST_fsm_state73 = 12'd72; +parameter ap_ST_fsm_state74 = 12'd73; +parameter ap_ST_fsm_state75 = 12'd74; +parameter ap_ST_fsm_state76 = 12'd75; +parameter ap_ST_fsm_state77 = 12'd76; +parameter ap_ST_fsm_state78 = 12'd77; +parameter ap_ST_fsm_state79 = 12'd78; +parameter ap_ST_fsm_state80 = 12'd79; +parameter ap_ST_fsm_state81 = 12'd80; +parameter ap_ST_fsm_state82 = 12'd81; +parameter ap_ST_fsm_state83 = 12'd82; +parameter ap_ST_fsm_state84 = 12'd83; +parameter ap_ST_fsm_state85 = 12'd84; +parameter ap_ST_fsm_state86 = 12'd85; +parameter ap_ST_fsm_state87 = 12'd86; +parameter ap_ST_fsm_state88 = 12'd87; +parameter ap_ST_fsm_state89 = 12'd88; +parameter ap_ST_fsm_state90 = 12'd89; +parameter ap_ST_fsm_state91 = 12'd90; +parameter ap_ST_fsm_state92 = 12'd91; +parameter ap_ST_fsm_state93 = 12'd92; +parameter ap_ST_fsm_state94 = 12'd93; +parameter ap_ST_fsm_state95 = 12'd94; +parameter ap_ST_fsm_state96 = 12'd95; +parameter ap_ST_fsm_state97 = 12'd96; +parameter ap_ST_fsm_state98 = 12'd97; +parameter ap_ST_fsm_state99 = 12'd98; +parameter ap_ST_fsm_state100 = 12'd99; +parameter ap_ST_fsm_state101 = 12'd100; +parameter ap_ST_fsm_state102 = 12'd101; +parameter ap_ST_fsm_state103 = 12'd102; +parameter ap_ST_fsm_state104 = 12'd103; +parameter ap_ST_fsm_state105 = 12'd104; +parameter ap_ST_fsm_state106 = 12'd105; +parameter ap_ST_fsm_state107 = 12'd106; +parameter ap_ST_fsm_state108 = 12'd107; +parameter ap_ST_fsm_state109 = 12'd108; +parameter ap_ST_fsm_state110 = 12'd109; +parameter ap_ST_fsm_state111 = 12'd110; +parameter ap_ST_fsm_state112 = 12'd111; +parameter ap_ST_fsm_state113 = 12'd112; +parameter ap_ST_fsm_state114 = 12'd113; +parameter ap_ST_fsm_state115 = 12'd114; +parameter ap_ST_fsm_state116 = 12'd115; +parameter ap_ST_fsm_state117 = 12'd116; +parameter ap_ST_fsm_state118 = 12'd117; +parameter ap_ST_fsm_state119 = 12'd118; +parameter ap_ST_fsm_state120 = 12'd119; +parameter ap_ST_fsm_state121 = 12'd120; +parameter ap_ST_fsm_state122 = 12'd121; +parameter ap_ST_fsm_state123 = 12'd122; +parameter ap_ST_fsm_state124 = 12'd123; +parameter ap_ST_fsm_state125 = 12'd124; +parameter ap_ST_fsm_state126 = 12'd125; +parameter ap_ST_fsm_state127 = 12'd126; +parameter ap_ST_fsm_state128 = 12'd127; +parameter ap_ST_fsm_state129 = 12'd128; +parameter ap_ST_fsm_state130 = 12'd129; +parameter ap_ST_fsm_state131 = 12'd130; +parameter ap_ST_fsm_state132 = 12'd131; +parameter ap_ST_fsm_state133 = 12'd132; +parameter ap_ST_fsm_state134 = 12'd133; +parameter ap_ST_fsm_state135 = 12'd134; +parameter ap_ST_fsm_state136 = 12'd135; +parameter ap_ST_fsm_state137 = 12'd136; +parameter ap_ST_fsm_state138 = 12'd137; +parameter ap_ST_fsm_state139 = 12'd138; +parameter ap_ST_fsm_state140 = 12'd139; +parameter ap_ST_fsm_state141 = 12'd140; +parameter ap_ST_fsm_state142 = 12'd141; +parameter ap_ST_fsm_state143 = 12'd142; +parameter ap_ST_fsm_state144 = 12'd143; +parameter ap_ST_fsm_state145 = 12'd144; +parameter ap_ST_fsm_state146 = 12'd145; +parameter ap_ST_fsm_state147 = 12'd146; +parameter ap_ST_fsm_state148 = 12'd147; +parameter ap_ST_fsm_state149 = 12'd148; +parameter ap_ST_fsm_state150 = 12'd149; +parameter ap_ST_fsm_state151 = 12'd150; +parameter ap_ST_fsm_state152 = 12'd151; +parameter ap_ST_fsm_state153 = 12'd152; +parameter ap_ST_fsm_state154 = 12'd153; +parameter ap_ST_fsm_state155 = 12'd154; +parameter ap_ST_fsm_state156 = 12'd155; +parameter ap_ST_fsm_state157 = 12'd156; +parameter ap_ST_fsm_state158 = 12'd157; +parameter ap_ST_fsm_state159 = 12'd158; +parameter ap_ST_fsm_state160 = 12'd159; +parameter ap_ST_fsm_state161 = 12'd160; +parameter ap_ST_fsm_state162 = 12'd161; +parameter ap_ST_fsm_state163 = 12'd162; +parameter ap_ST_fsm_state164 = 12'd163; +parameter ap_ST_fsm_state165 = 12'd164; +parameter ap_ST_fsm_state166 = 12'd165; +parameter ap_ST_fsm_state167 = 12'd166; +parameter ap_ST_fsm_state168 = 12'd167; +parameter ap_ST_fsm_state169 = 12'd168; +parameter ap_ST_fsm_state170 = 12'd169; +parameter ap_ST_fsm_state171 = 12'd170; +parameter ap_ST_fsm_state172 = 12'd171; +parameter ap_ST_fsm_state173 = 12'd172; +parameter ap_ST_fsm_state174 = 12'd173; +parameter ap_ST_fsm_state175 = 12'd174; +parameter ap_ST_fsm_state176 = 12'd175; +parameter ap_ST_fsm_state177 = 12'd176; +parameter ap_ST_fsm_state178 = 12'd177; +parameter ap_ST_fsm_state179 = 12'd178; +parameter ap_ST_fsm_state180 = 12'd179; +parameter ap_ST_fsm_state181 = 12'd180; +parameter ap_ST_fsm_state182 = 12'd181; +parameter ap_ST_fsm_state183 = 12'd182; +parameter ap_ST_fsm_state184 = 12'd183; +parameter ap_ST_fsm_state185 = 12'd184; +parameter ap_ST_fsm_state186 = 12'd185; +parameter ap_ST_fsm_state187 = 12'd186; +parameter ap_ST_fsm_state188 = 12'd187; +parameter ap_ST_fsm_state189 = 12'd188; +parameter ap_ST_fsm_state190 = 12'd189; +parameter ap_ST_fsm_state191 = 12'd190; +parameter ap_ST_fsm_state192 = 12'd191; +parameter ap_ST_fsm_state193 = 12'd192; +parameter ap_ST_fsm_state194 = 12'd193; +parameter ap_ST_fsm_state195 = 12'd194; +parameter ap_ST_fsm_state196 = 12'd195; +parameter ap_ST_fsm_state197 = 12'd196; +parameter ap_ST_fsm_state198 = 12'd197; +parameter ap_ST_fsm_state199 = 12'd198; +parameter ap_ST_fsm_state200 = 12'd199; +parameter ap_ST_fsm_state201 = 12'd200; +parameter ap_ST_fsm_state202 = 12'd201; +parameter ap_ST_fsm_state203 = 12'd202; +parameter ap_ST_fsm_state204 = 12'd203; +parameter ap_ST_fsm_state205 = 12'd204; +parameter ap_ST_fsm_state206 = 12'd205; +parameter ap_ST_fsm_state207 = 12'd206; +parameter ap_ST_fsm_state208 = 12'd207; +parameter ap_ST_fsm_state209 = 12'd208; +parameter ap_ST_fsm_state210 = 12'd209; +parameter ap_ST_fsm_state211 = 12'd210; +parameter ap_ST_fsm_state212 = 12'd211; +parameter ap_ST_fsm_state213 = 12'd212; +parameter ap_ST_fsm_state214 = 12'd213; +parameter ap_ST_fsm_state215 = 12'd214; +parameter ap_ST_fsm_state216 = 12'd215; +parameter ap_ST_fsm_state217 = 12'd216; +parameter ap_ST_fsm_state218 = 12'd217; +parameter ap_ST_fsm_state219 = 12'd218; +parameter ap_ST_fsm_state220 = 12'd219; +parameter ap_ST_fsm_state221 = 12'd220; +parameter ap_ST_fsm_state222 = 12'd221; +parameter ap_ST_fsm_state223 = 12'd222; +parameter ap_ST_fsm_state224 = 12'd223; +parameter ap_ST_fsm_state225 = 12'd224; +parameter ap_ST_fsm_state226 = 12'd225; +parameter ap_ST_fsm_state227 = 12'd226; +parameter ap_ST_fsm_state228 = 12'd227; +parameter ap_ST_fsm_state229 = 12'd228; +parameter ap_ST_fsm_state230 = 12'd229; +parameter ap_ST_fsm_state231 = 12'd230; +parameter ap_ST_fsm_state232 = 12'd231; +parameter ap_ST_fsm_state233 = 12'd232; +parameter ap_ST_fsm_state234 = 12'd233; +parameter ap_ST_fsm_state235 = 12'd234; +parameter ap_ST_fsm_state236 = 12'd235; +parameter ap_ST_fsm_state237 = 12'd236; +parameter ap_ST_fsm_state238 = 12'd237; +parameter ap_ST_fsm_state239 = 12'd238; +parameter ap_ST_fsm_state240 = 12'd239; +parameter ap_ST_fsm_state241 = 12'd240; +parameter ap_ST_fsm_state242 = 12'd241; +parameter ap_ST_fsm_state243 = 12'd242; +parameter ap_ST_fsm_state244 = 12'd243; +parameter ap_ST_fsm_state245 = 12'd244; +parameter ap_ST_fsm_state246 = 12'd245; +parameter ap_ST_fsm_state247 = 12'd246; +parameter ap_ST_fsm_state248 = 12'd247; +parameter ap_ST_fsm_state249 = 12'd248; +parameter ap_ST_fsm_state250 = 12'd249; +parameter ap_ST_fsm_state251 = 12'd250; +parameter ap_ST_fsm_state252 = 12'd251; +parameter ap_ST_fsm_state253 = 12'd252; +parameter ap_ST_fsm_state254 = 12'd253; +parameter ap_ST_fsm_state255 = 12'd254; +parameter ap_ST_fsm_state256 = 12'd255; +parameter ap_ST_fsm_state257 = 12'd256; +parameter ap_ST_fsm_state258 = 12'd257; +parameter ap_ST_fsm_state259 = 12'd258; +parameter ap_ST_fsm_state260 = 12'd259; +parameter ap_ST_fsm_state261 = 12'd260; +parameter ap_ST_fsm_state262 = 12'd261; +parameter ap_ST_fsm_state263 = 12'd262; +parameter ap_ST_fsm_state264 = 12'd263; +parameter ap_ST_fsm_state265 = 12'd264; +parameter ap_ST_fsm_state266 = 12'd265; +parameter ap_ST_fsm_state267 = 12'd266; +parameter ap_ST_fsm_state268 = 12'd267; +parameter ap_ST_fsm_state269 = 12'd268; +parameter ap_ST_fsm_state270 = 12'd269; +parameter ap_ST_fsm_state271 = 12'd270; +parameter ap_ST_fsm_state272 = 12'd271; +parameter ap_ST_fsm_state273 = 12'd272; +parameter ap_ST_fsm_state274 = 12'd273; +parameter ap_ST_fsm_state275 = 12'd274; +parameter ap_ST_fsm_state276 = 12'd275; +parameter ap_ST_fsm_state277 = 12'd276; +parameter ap_ST_fsm_state278 = 12'd277; +parameter ap_ST_fsm_state279 = 12'd278; +parameter ap_ST_fsm_state280 = 12'd279; +parameter ap_ST_fsm_state281 = 12'd280; +parameter ap_ST_fsm_state282 = 12'd281; +parameter ap_ST_fsm_state283 = 12'd282; +parameter ap_ST_fsm_state284 = 12'd283; +parameter ap_ST_fsm_state285 = 12'd284; +parameter ap_ST_fsm_state286 = 12'd285; +parameter ap_ST_fsm_state287 = 12'd286; +parameter ap_ST_fsm_state288 = 12'd287; +parameter ap_ST_fsm_state289 = 12'd288; +parameter ap_ST_fsm_state290 = 12'd289; +parameter ap_ST_fsm_state291 = 12'd290; +parameter ap_ST_fsm_state292 = 12'd291; +parameter ap_ST_fsm_state293 = 12'd292; +parameter ap_ST_fsm_state294 = 12'd293; +parameter ap_ST_fsm_state295 = 12'd294; +parameter ap_ST_fsm_state296 = 12'd295; +parameter ap_ST_fsm_state297 = 12'd296; +parameter ap_ST_fsm_state298 = 12'd297; +parameter ap_ST_fsm_state299 = 12'd298; +parameter ap_ST_fsm_state300 = 12'd299; +parameter ap_ST_fsm_state301 = 12'd300; +parameter ap_ST_fsm_state302 = 12'd301; +parameter ap_ST_fsm_state303 = 12'd302; +parameter ap_ST_fsm_state304 = 12'd303; +parameter ap_ST_fsm_state305 = 12'd304; +parameter ap_ST_fsm_state306 = 12'd305; +parameter ap_ST_fsm_state307 = 12'd306; +parameter ap_ST_fsm_state308 = 12'd307; +parameter ap_ST_fsm_state309 = 12'd308; +parameter ap_ST_fsm_state310 = 12'd309; +parameter ap_ST_fsm_state311 = 12'd310; +parameter ap_ST_fsm_state312 = 12'd311; +parameter ap_ST_fsm_state313 = 12'd312; +parameter ap_ST_fsm_state314 = 12'd313; +parameter ap_ST_fsm_state315 = 12'd314; +parameter ap_ST_fsm_state316 = 12'd315; +parameter ap_ST_fsm_state317 = 12'd316; +parameter ap_ST_fsm_state318 = 12'd317; +parameter ap_ST_fsm_state319 = 12'd318; +parameter ap_ST_fsm_state320 = 12'd319; +parameter ap_ST_fsm_state321 = 12'd320; +parameter ap_ST_fsm_state322 = 12'd321; +parameter ap_ST_fsm_state323 = 12'd322; +parameter ap_ST_fsm_state324 = 12'd323; +parameter ap_ST_fsm_state325 = 12'd324; +parameter ap_ST_fsm_state326 = 12'd325; +parameter ap_ST_fsm_state327 = 12'd326; +parameter ap_ST_fsm_state328 = 12'd327; +parameter ap_ST_fsm_state329 = 12'd328; +parameter ap_ST_fsm_state330 = 12'd329; +parameter ap_ST_fsm_state331 = 12'd330; +parameter ap_ST_fsm_state332 = 12'd331; +parameter ap_ST_fsm_state333 = 12'd332; +parameter ap_ST_fsm_state334 = 12'd333; +parameter ap_ST_fsm_state335 = 12'd334; +parameter ap_ST_fsm_state336 = 12'd335; +parameter ap_ST_fsm_state337 = 12'd336; +parameter ap_ST_fsm_state338 = 12'd337; +parameter ap_ST_fsm_state339 = 12'd338; +parameter ap_ST_fsm_state340 = 12'd339; +parameter ap_ST_fsm_state341 = 12'd340; +parameter ap_ST_fsm_state342 = 12'd341; +parameter ap_ST_fsm_state343 = 12'd342; +parameter ap_ST_fsm_state344 = 12'd343; +parameter ap_ST_fsm_state345 = 12'd344; +parameter ap_ST_fsm_state346 = 12'd345; +parameter ap_ST_fsm_state347 = 12'd346; +parameter ap_ST_fsm_state348 = 12'd347; +parameter ap_ST_fsm_state349 = 12'd348; +parameter ap_ST_fsm_state350 = 12'd349; +parameter ap_ST_fsm_state351 = 12'd350; +parameter ap_ST_fsm_state352 = 12'd351; +parameter ap_ST_fsm_state353 = 12'd352; +parameter ap_ST_fsm_state354 = 12'd353; +parameter ap_ST_fsm_state355 = 12'd354; +parameter ap_ST_fsm_state356 = 12'd355; +parameter ap_ST_fsm_state357 = 12'd356; +parameter ap_ST_fsm_state358 = 12'd357; +parameter ap_ST_fsm_state359 = 12'd358; +parameter ap_ST_fsm_state360 = 12'd359; +parameter ap_ST_fsm_state361 = 12'd360; +parameter ap_ST_fsm_state362 = 12'd361; +parameter ap_ST_fsm_state363 = 12'd362; +parameter ap_ST_fsm_state364 = 12'd363; +parameter ap_ST_fsm_state365 = 12'd364; +parameter ap_ST_fsm_state366 = 12'd365; +parameter ap_ST_fsm_state367 = 12'd366; +parameter ap_ST_fsm_state368 = 12'd367; +parameter ap_ST_fsm_state369 = 12'd368; +parameter ap_ST_fsm_state370 = 12'd369; +parameter ap_ST_fsm_state371 = 12'd370; +parameter ap_ST_fsm_state372 = 12'd371; +parameter ap_ST_fsm_state373 = 12'd372; +parameter ap_ST_fsm_state374 = 12'd373; +parameter ap_ST_fsm_state375 = 12'd374; +parameter ap_ST_fsm_state376 = 12'd375; +parameter ap_ST_fsm_state377 = 12'd376; +parameter ap_ST_fsm_state378 = 12'd377; +parameter ap_ST_fsm_state379 = 12'd378; +parameter ap_ST_fsm_state380 = 12'd379; +parameter ap_ST_fsm_state381 = 12'd380; +parameter ap_ST_fsm_state382 = 12'd381; +parameter ap_ST_fsm_state383 = 12'd382; +parameter ap_ST_fsm_state384 = 12'd383; +parameter ap_ST_fsm_state385 = 12'd384; +parameter ap_ST_fsm_state386 = 12'd385; +parameter ap_ST_fsm_state387 = 12'd386; +parameter ap_ST_fsm_state388 = 12'd387; +parameter ap_ST_fsm_state389 = 12'd388; +parameter ap_ST_fsm_state390 = 12'd389; +parameter ap_ST_fsm_state391 = 12'd390; +parameter ap_ST_fsm_state392 = 12'd391; +parameter ap_ST_fsm_state393 = 12'd392; +parameter ap_ST_fsm_state394 = 12'd393; +parameter ap_ST_fsm_state395 = 12'd394; +parameter ap_ST_fsm_state396 = 12'd395; +parameter ap_ST_fsm_state397 = 12'd396; +parameter ap_ST_fsm_state398 = 12'd397; +parameter ap_ST_fsm_state399 = 12'd398; +parameter ap_ST_fsm_state400 = 12'd399; +parameter ap_ST_fsm_state401 = 12'd400; +parameter ap_ST_fsm_state402 = 12'd401; +parameter ap_ST_fsm_state403 = 12'd402; +parameter ap_ST_fsm_state404 = 12'd403; +parameter ap_ST_fsm_state405 = 12'd404; +parameter ap_ST_fsm_state406 = 12'd405; +parameter ap_ST_fsm_state407 = 12'd406; +parameter ap_ST_fsm_state408 = 12'd407; +parameter ap_ST_fsm_state409 = 12'd408; +parameter ap_ST_fsm_state410 = 12'd409; +parameter ap_ST_fsm_state411 = 12'd410; +parameter ap_ST_fsm_state412 = 12'd411; +parameter ap_ST_fsm_state413 = 12'd412; +parameter ap_ST_fsm_state414 = 12'd413; +parameter ap_ST_fsm_state415 = 12'd414; +parameter ap_ST_fsm_state416 = 12'd415; +parameter ap_ST_fsm_state417 = 12'd416; +parameter ap_ST_fsm_state418 = 12'd417; +parameter ap_ST_fsm_state419 = 12'd418; +parameter ap_ST_fsm_state420 = 12'd419; +parameter ap_ST_fsm_state421 = 12'd420; +parameter ap_ST_fsm_state422 = 12'd421; +parameter ap_ST_fsm_state423 = 12'd422; +parameter ap_ST_fsm_state424 = 12'd423; +parameter ap_ST_fsm_state425 = 12'd424; +parameter ap_ST_fsm_state426 = 12'd425; +parameter ap_ST_fsm_state427 = 12'd426; +parameter ap_ST_fsm_state428 = 12'd427; +parameter ap_ST_fsm_state429 = 12'd428; +parameter ap_ST_fsm_state430 = 12'd429; +parameter ap_ST_fsm_state431 = 12'd430; +parameter ap_ST_fsm_state432 = 12'd431; +parameter ap_ST_fsm_state433 = 12'd432; +parameter ap_ST_fsm_state434 = 12'd433; +parameter ap_ST_fsm_state435 = 12'd434; +parameter ap_ST_fsm_state436 = 12'd435; +parameter ap_ST_fsm_state437 = 12'd436; +parameter ap_ST_fsm_state438 = 12'd437; +parameter ap_ST_fsm_state439 = 12'd438; +parameter ap_ST_fsm_state440 = 12'd439; +parameter ap_ST_fsm_state441 = 12'd440; +parameter ap_ST_fsm_state442 = 12'd441; +parameter ap_ST_fsm_state443 = 12'd442; +parameter ap_ST_fsm_state444 = 12'd443; +parameter ap_ST_fsm_state445 = 12'd444; +parameter ap_ST_fsm_state446 = 12'd445; +parameter ap_ST_fsm_state447 = 12'd446; +parameter ap_ST_fsm_state448 = 12'd447; +parameter ap_ST_fsm_state449 = 12'd448; +parameter ap_ST_fsm_state450 = 12'd449; +parameter ap_ST_fsm_state451 = 12'd450; +parameter ap_ST_fsm_state452 = 12'd451; +parameter ap_ST_fsm_state453 = 12'd452; +parameter ap_ST_fsm_state454 = 12'd453; +parameter ap_ST_fsm_state455 = 12'd454; +parameter ap_ST_fsm_state456 = 12'd455; +parameter ap_ST_fsm_state457 = 12'd456; +parameter ap_ST_fsm_state458 = 12'd457; +parameter ap_ST_fsm_state459 = 12'd458; +parameter ap_ST_fsm_state460 = 12'd459; +parameter ap_ST_fsm_state461 = 12'd460; +parameter ap_ST_fsm_state462 = 12'd461; +parameter ap_ST_fsm_state463 = 12'd462; +parameter ap_ST_fsm_state464 = 12'd463; +parameter ap_ST_fsm_state465 = 12'd464; +parameter ap_ST_fsm_state466 = 12'd465; +parameter ap_ST_fsm_state467 = 12'd466; +parameter ap_ST_fsm_state468 = 12'd467; +parameter ap_ST_fsm_state469 = 12'd468; +parameter ap_ST_fsm_state470 = 12'd469; +parameter ap_ST_fsm_state471 = 12'd470; +parameter ap_ST_fsm_state472 = 12'd471; +parameter ap_ST_fsm_state473 = 12'd472; +parameter ap_ST_fsm_state474 = 12'd473; +parameter ap_ST_fsm_state475 = 12'd474; +parameter ap_ST_fsm_state476 = 12'd475; +parameter ap_ST_fsm_state477 = 12'd476; +parameter ap_ST_fsm_state478 = 12'd477; +parameter ap_ST_fsm_state479 = 12'd478; +parameter ap_ST_fsm_state480 = 12'd479; +parameter ap_ST_fsm_state481 = 12'd480; +parameter ap_ST_fsm_state482 = 12'd481; +parameter ap_ST_fsm_state483 = 12'd482; +parameter ap_ST_fsm_state484 = 12'd483; +parameter ap_ST_fsm_state485 = 12'd484; +parameter ap_ST_fsm_state486 = 12'd485; +parameter ap_ST_fsm_state487 = 12'd486; +parameter ap_ST_fsm_state488 = 12'd487; +parameter ap_ST_fsm_state489 = 12'd488; +parameter ap_ST_fsm_state490 = 12'd489; +parameter ap_ST_fsm_state491 = 12'd490; +parameter ap_ST_fsm_state492 = 12'd491; +parameter ap_ST_fsm_state493 = 12'd492; +parameter ap_ST_fsm_state494 = 12'd493; +parameter ap_ST_fsm_state495 = 12'd494; +parameter ap_ST_fsm_state496 = 12'd495; +parameter ap_ST_fsm_state497 = 12'd496; +parameter ap_ST_fsm_state498 = 12'd497; +parameter ap_ST_fsm_state499 = 12'd498; +parameter ap_ST_fsm_state500 = 12'd499; +parameter ap_ST_fsm_state501 = 12'd500; +parameter ap_ST_fsm_state502 = 12'd501; +parameter ap_ST_fsm_state503 = 12'd502; +parameter ap_ST_fsm_state504 = 12'd503; +parameter ap_ST_fsm_state505 = 12'd504; +parameter ap_ST_fsm_state506 = 12'd505; +parameter ap_ST_fsm_state507 = 12'd506; +parameter ap_ST_fsm_state508 = 12'd507; +parameter ap_ST_fsm_state509 = 12'd508; +parameter ap_ST_fsm_state510 = 12'd509; +parameter ap_ST_fsm_state511 = 12'd510; +parameter ap_ST_fsm_state512 = 12'd511; +parameter ap_ST_fsm_state513 = 12'd512; +parameter ap_ST_fsm_state514 = 12'd513; +parameter ap_ST_fsm_state515 = 12'd514; +parameter ap_ST_fsm_state516 = 12'd515; +parameter ap_ST_fsm_state517 = 12'd516; +parameter ap_ST_fsm_state518 = 12'd517; +parameter ap_ST_fsm_state519 = 12'd518; +parameter ap_ST_fsm_state520 = 12'd519; +parameter ap_ST_fsm_state521 = 12'd520; +parameter ap_ST_fsm_state522 = 12'd521; +parameter ap_ST_fsm_state523 = 12'd522; +parameter ap_ST_fsm_state524 = 12'd523; +parameter ap_ST_fsm_state525 = 12'd524; +parameter ap_ST_fsm_state526 = 12'd525; +parameter ap_ST_fsm_state527 = 12'd526; +parameter ap_ST_fsm_state528 = 12'd527; +parameter ap_ST_fsm_state529 = 12'd528; +parameter ap_ST_fsm_state530 = 12'd529; +parameter ap_ST_fsm_state531 = 12'd530; +parameter ap_ST_fsm_state532 = 12'd531; +parameter ap_ST_fsm_state533 = 12'd532; +parameter ap_ST_fsm_state534 = 12'd533; +parameter ap_ST_fsm_state535 = 12'd534; +parameter ap_ST_fsm_state536 = 12'd535; +parameter ap_ST_fsm_state537 = 12'd536; +parameter ap_ST_fsm_state538 = 12'd537; +parameter ap_ST_fsm_state539 = 12'd538; +parameter ap_ST_fsm_state540 = 12'd539; +parameter ap_ST_fsm_state541 = 12'd540; +parameter ap_ST_fsm_state542 = 12'd541; +parameter ap_ST_fsm_state543 = 12'd542; +parameter ap_ST_fsm_state544 = 12'd543; +parameter ap_ST_fsm_state545 = 12'd544; +parameter ap_ST_fsm_state546 = 12'd545; +parameter ap_ST_fsm_state547 = 12'd546; +parameter ap_ST_fsm_state548 = 12'd547; +parameter ap_ST_fsm_state549 = 12'd548; +parameter ap_ST_fsm_state550 = 12'd549; +parameter ap_ST_fsm_state551 = 12'd550; +parameter ap_ST_fsm_state552 = 12'd551; +parameter ap_ST_fsm_state553 = 12'd552; +parameter ap_ST_fsm_state554 = 12'd553; +parameter ap_ST_fsm_state555 = 12'd554; +parameter ap_ST_fsm_state556 = 12'd555; +parameter ap_ST_fsm_state557 = 12'd556; +parameter ap_ST_fsm_state558 = 12'd557; +parameter ap_ST_fsm_state559 = 12'd558; +parameter ap_ST_fsm_state560 = 12'd559; +parameter ap_ST_fsm_state561 = 12'd560; +parameter ap_ST_fsm_state562 = 12'd561; +parameter ap_ST_fsm_state563 = 12'd562; +parameter ap_ST_fsm_state564 = 12'd563; +parameter ap_ST_fsm_state565 = 12'd564; +parameter ap_ST_fsm_state566 = 12'd565; +parameter ap_ST_fsm_state567 = 12'd566; +parameter ap_ST_fsm_state568 = 12'd567; +parameter ap_ST_fsm_state569 = 12'd568; +parameter ap_ST_fsm_state570 = 12'd569; +parameter ap_ST_fsm_state571 = 12'd570; +parameter ap_ST_fsm_state572 = 12'd571; +parameter ap_ST_fsm_state573 = 12'd572; +parameter ap_ST_fsm_state574 = 12'd573; +parameter ap_ST_fsm_state575 = 12'd574; +parameter ap_ST_fsm_state576 = 12'd575; +parameter ap_ST_fsm_state577 = 12'd576; +parameter ap_ST_fsm_state578 = 12'd577; +parameter ap_ST_fsm_state579 = 12'd578; +parameter ap_ST_fsm_state580 = 12'd579; +parameter ap_ST_fsm_state581 = 12'd580; +parameter ap_ST_fsm_state582 = 12'd581; +parameter ap_ST_fsm_state583 = 12'd582; +parameter ap_ST_fsm_state584 = 12'd583; +parameter ap_ST_fsm_state585 = 12'd584; +parameter ap_ST_fsm_state586 = 12'd585; +parameter ap_ST_fsm_state587 = 12'd586; +parameter ap_ST_fsm_state588 = 12'd587; +parameter ap_ST_fsm_state589 = 12'd588; +parameter ap_ST_fsm_state590 = 12'd589; +parameter ap_ST_fsm_state591 = 12'd590; +parameter ap_ST_fsm_state592 = 12'd591; +parameter ap_ST_fsm_state593 = 12'd592; +parameter ap_ST_fsm_state594 = 12'd593; +parameter ap_ST_fsm_state595 = 12'd594; +parameter ap_ST_fsm_state596 = 12'd595; +parameter ap_ST_fsm_state597 = 12'd596; +parameter ap_ST_fsm_state598 = 12'd597; +parameter ap_ST_fsm_state599 = 12'd598; +parameter ap_ST_fsm_state600 = 12'd599; +parameter ap_ST_fsm_state601 = 12'd600; +parameter ap_ST_fsm_state602 = 12'd601; +parameter ap_ST_fsm_state603 = 12'd602; +parameter ap_ST_fsm_state604 = 12'd603; +parameter ap_ST_fsm_state605 = 12'd604; +parameter ap_ST_fsm_state606 = 12'd605; +parameter ap_ST_fsm_state607 = 12'd606; +parameter ap_ST_fsm_state608 = 12'd607; +parameter ap_ST_fsm_state609 = 12'd608; +parameter ap_ST_fsm_state610 = 12'd609; +parameter ap_ST_fsm_state611 = 12'd610; +parameter ap_ST_fsm_state612 = 12'd611; +parameter ap_ST_fsm_state613 = 12'd612; +parameter ap_ST_fsm_state614 = 12'd613; +parameter ap_ST_fsm_state615 = 12'd614; +parameter ap_ST_fsm_state616 = 12'd615; +parameter ap_ST_fsm_state617 = 12'd616; +parameter ap_ST_fsm_state618 = 12'd617; +parameter ap_ST_fsm_state619 = 12'd618; +parameter ap_ST_fsm_state620 = 12'd619; +parameter ap_ST_fsm_state621 = 12'd620; +parameter ap_ST_fsm_state622 = 12'd621; +parameter ap_ST_fsm_state623 = 12'd622; +parameter ap_ST_fsm_state624 = 12'd623; +parameter ap_ST_fsm_state625 = 12'd624; +parameter ap_ST_fsm_state626 = 12'd625; +parameter ap_ST_fsm_state627 = 12'd626; +parameter ap_ST_fsm_state628 = 12'd627; +parameter ap_ST_fsm_state629 = 12'd628; +parameter ap_ST_fsm_state630 = 12'd629; +parameter ap_ST_fsm_state631 = 12'd630; +parameter ap_ST_fsm_state632 = 12'd631; +parameter ap_ST_fsm_state633 = 12'd632; +parameter ap_ST_fsm_state634 = 12'd633; +parameter ap_ST_fsm_state635 = 12'd634; +parameter ap_ST_fsm_state636 = 12'd635; +parameter ap_ST_fsm_state637 = 12'd636; +parameter ap_ST_fsm_state638 = 12'd637; +parameter ap_ST_fsm_state639 = 12'd638; +parameter ap_ST_fsm_state640 = 12'd639; +parameter ap_ST_fsm_state641 = 12'd640; +parameter ap_ST_fsm_state642 = 12'd641; +parameter ap_ST_fsm_state643 = 12'd642; +parameter ap_ST_fsm_state644 = 12'd643; +parameter ap_ST_fsm_state645 = 12'd644; +parameter ap_ST_fsm_state646 = 12'd645; +parameter ap_ST_fsm_state647 = 12'd646; +parameter ap_ST_fsm_state648 = 12'd647; +parameter ap_ST_fsm_state649 = 12'd648; +parameter ap_ST_fsm_state650 = 12'd649; +parameter ap_ST_fsm_state651 = 12'd650; +parameter ap_ST_fsm_state652 = 12'd651; +parameter ap_ST_fsm_state653 = 12'd652; +parameter ap_ST_fsm_state654 = 12'd653; +parameter ap_ST_fsm_state655 = 12'd654; +parameter ap_ST_fsm_state656 = 12'd655; +parameter ap_ST_fsm_state657 = 12'd656; +parameter ap_ST_fsm_state658 = 12'd657; +parameter ap_ST_fsm_state659 = 12'd658; +parameter ap_ST_fsm_state660 = 12'd659; +parameter ap_ST_fsm_state661 = 12'd660; +parameter ap_ST_fsm_state662 = 12'd661; +parameter ap_ST_fsm_state663 = 12'd662; +parameter ap_ST_fsm_state664 = 12'd663; +parameter ap_ST_fsm_state665 = 12'd664; +parameter ap_ST_fsm_state666 = 12'd665; +parameter ap_ST_fsm_state667 = 12'd666; +parameter ap_ST_fsm_state668 = 12'd667; +parameter ap_ST_fsm_state669 = 12'd668; +parameter ap_ST_fsm_state670 = 12'd669; +parameter ap_ST_fsm_state671 = 12'd670; +parameter ap_ST_fsm_state672 = 12'd671; +parameter ap_ST_fsm_state673 = 12'd672; +parameter ap_ST_fsm_state674 = 12'd673; +parameter ap_ST_fsm_state675 = 12'd674; +parameter ap_ST_fsm_state676 = 12'd675; +parameter ap_ST_fsm_state677 = 12'd676; +parameter ap_ST_fsm_state678 = 12'd677; +parameter ap_ST_fsm_state679 = 12'd678; +parameter ap_ST_fsm_state680 = 12'd679; +parameter ap_ST_fsm_state681 = 12'd680; +parameter ap_ST_fsm_state682 = 12'd681; +parameter ap_ST_fsm_state683 = 12'd682; +parameter ap_ST_fsm_state684 = 12'd683; +parameter ap_ST_fsm_state685 = 12'd684; +parameter ap_ST_fsm_state686 = 12'd685; +parameter ap_ST_fsm_state687 = 12'd686; +parameter ap_ST_fsm_state688 = 12'd687; +parameter ap_ST_fsm_state689 = 12'd688; +parameter ap_ST_fsm_state690 = 12'd689; +parameter ap_ST_fsm_state691 = 12'd690; +parameter ap_ST_fsm_state692 = 12'd691; +parameter ap_ST_fsm_state693 = 12'd692; +parameter ap_ST_fsm_state694 = 12'd693; +parameter ap_ST_fsm_state695 = 12'd694; +parameter ap_ST_fsm_state696 = 12'd695; +parameter ap_ST_fsm_state697 = 12'd696; +parameter ap_ST_fsm_state698 = 12'd697; +parameter ap_ST_fsm_state699 = 12'd698; +parameter ap_ST_fsm_state700 = 12'd699; +parameter ap_ST_fsm_state701 = 12'd700; +parameter ap_ST_fsm_state702 = 12'd701; +parameter ap_ST_fsm_state703 = 12'd702; +parameter ap_ST_fsm_state704 = 12'd703; +parameter ap_ST_fsm_state705 = 12'd704; +parameter ap_ST_fsm_state706 = 12'd705; +parameter ap_ST_fsm_state707 = 12'd706; +parameter ap_ST_fsm_state708 = 12'd707; +parameter ap_ST_fsm_state709 = 12'd708; +parameter ap_ST_fsm_state710 = 12'd709; +parameter ap_ST_fsm_state711 = 12'd710; +parameter ap_ST_fsm_state712 = 12'd711; +parameter ap_ST_fsm_state713 = 12'd712; +parameter ap_ST_fsm_state714 = 12'd713; +parameter ap_ST_fsm_state715 = 12'd714; +parameter ap_ST_fsm_state716 = 12'd715; +parameter ap_ST_fsm_state717 = 12'd716; +parameter ap_ST_fsm_state718 = 12'd717; +parameter ap_ST_fsm_state719 = 12'd718; +parameter ap_ST_fsm_state720 = 12'd719; +parameter ap_ST_fsm_state721 = 12'd720; +parameter ap_ST_fsm_state722 = 12'd721; +parameter ap_ST_fsm_state723 = 12'd722; +parameter ap_ST_fsm_state724 = 12'd723; +parameter ap_ST_fsm_state725 = 12'd724; +parameter ap_ST_fsm_state726 = 12'd725; +parameter ap_ST_fsm_state727 = 12'd726; +parameter ap_ST_fsm_state728 = 12'd727; +parameter ap_ST_fsm_state729 = 12'd728; +parameter ap_ST_fsm_state730 = 12'd729; +parameter ap_ST_fsm_state731 = 12'd730; +parameter ap_ST_fsm_state732 = 12'd731; +parameter ap_ST_fsm_state733 = 12'd732; +parameter ap_ST_fsm_state734 = 12'd733; +parameter ap_ST_fsm_state735 = 12'd734; +parameter ap_ST_fsm_state736 = 12'd735; +parameter ap_ST_fsm_state737 = 12'd736; +parameter ap_ST_fsm_state738 = 12'd737; +parameter ap_ST_fsm_state739 = 12'd738; +parameter ap_ST_fsm_state740 = 12'd739; +parameter ap_ST_fsm_state741 = 12'd740; +parameter ap_ST_fsm_state742 = 12'd741; +parameter ap_ST_fsm_state743 = 12'd742; +parameter ap_ST_fsm_state744 = 12'd743; +parameter ap_ST_fsm_state745 = 12'd744; +parameter ap_ST_fsm_state746 = 12'd745; +parameter ap_ST_fsm_state747 = 12'd746; +parameter ap_ST_fsm_state748 = 12'd747; +parameter ap_ST_fsm_state749 = 12'd748; +parameter ap_ST_fsm_state750 = 12'd749; +parameter ap_ST_fsm_state751 = 12'd750; +parameter ap_ST_fsm_state752 = 12'd751; +parameter ap_ST_fsm_state753 = 12'd752; +parameter ap_ST_fsm_state754 = 12'd753; +parameter ap_ST_fsm_state755 = 12'd754; +parameter ap_ST_fsm_state756 = 12'd755; +parameter ap_ST_fsm_state757 = 12'd756; +parameter ap_ST_fsm_state758 = 12'd757; +parameter ap_ST_fsm_state759 = 12'd758; +parameter ap_ST_fsm_state760 = 12'd759; +parameter ap_ST_fsm_state761 = 12'd760; +parameter ap_ST_fsm_state762 = 12'd761; +parameter ap_ST_fsm_state763 = 12'd762; +parameter ap_ST_fsm_state764 = 12'd763; +parameter ap_ST_fsm_state765 = 12'd764; +parameter ap_ST_fsm_state766 = 12'd765; +parameter ap_ST_fsm_state767 = 12'd766; +parameter ap_ST_fsm_state768 = 12'd767; +parameter ap_ST_fsm_state769 = 12'd768; +parameter ap_ST_fsm_state770 = 12'd769; +parameter ap_ST_fsm_state771 = 12'd770; +parameter ap_ST_fsm_state772 = 12'd771; +parameter ap_ST_fsm_state773 = 12'd772; +parameter ap_ST_fsm_state774 = 12'd773; +parameter ap_ST_fsm_state775 = 12'd774; +parameter ap_ST_fsm_state776 = 12'd775; +parameter ap_ST_fsm_state777 = 12'd776; +parameter ap_ST_fsm_state778 = 12'd777; +parameter ap_ST_fsm_state779 = 12'd778; +parameter ap_ST_fsm_state780 = 12'd779; +parameter ap_ST_fsm_state781 = 12'd780; +parameter ap_ST_fsm_state782 = 12'd781; +parameter ap_ST_fsm_state783 = 12'd782; +parameter ap_ST_fsm_state784 = 12'd783; +parameter ap_ST_fsm_state785 = 12'd784; +parameter ap_ST_fsm_state786 = 12'd785; +parameter ap_ST_fsm_state787 = 12'd786; +parameter ap_ST_fsm_state788 = 12'd787; +parameter ap_ST_fsm_state789 = 12'd788; +parameter ap_ST_fsm_state790 = 12'd789; +parameter ap_ST_fsm_state791 = 12'd790; +parameter ap_ST_fsm_state792 = 12'd791; +parameter ap_ST_fsm_state793 = 12'd792; +parameter ap_ST_fsm_state794 = 12'd793; +parameter ap_ST_fsm_state795 = 12'd794; +parameter ap_ST_fsm_state796 = 12'd795; +parameter ap_ST_fsm_state797 = 12'd796; +parameter ap_ST_fsm_state798 = 12'd797; +parameter ap_ST_fsm_state799 = 12'd798; +parameter ap_ST_fsm_state800 = 12'd799; +parameter ap_ST_fsm_state801 = 12'd800; +parameter ap_ST_fsm_state802 = 12'd801; +parameter ap_ST_fsm_state803 = 12'd802; +parameter ap_ST_fsm_state804 = 12'd803; +parameter ap_ST_fsm_state805 = 12'd804; +parameter ap_ST_fsm_state806 = 12'd805; +parameter ap_ST_fsm_state807 = 12'd806; +parameter ap_ST_fsm_state808 = 12'd807; +parameter ap_ST_fsm_state809 = 12'd808; +parameter ap_ST_fsm_state810 = 12'd809; +parameter ap_ST_fsm_state811 = 12'd810; +parameter ap_ST_fsm_state812 = 12'd811; +parameter ap_ST_fsm_state813 = 12'd812; +parameter ap_ST_fsm_state814 = 12'd813; +parameter ap_ST_fsm_state815 = 12'd814; +parameter ap_ST_fsm_state816 = 12'd815; +parameter ap_ST_fsm_state817 = 12'd816; +parameter ap_ST_fsm_state818 = 12'd817; +parameter ap_ST_fsm_state819 = 12'd818; +parameter ap_ST_fsm_state820 = 12'd819; +parameter ap_ST_fsm_state821 = 12'd820; +parameter ap_ST_fsm_state822 = 12'd821; +parameter ap_ST_fsm_state823 = 12'd822; +parameter ap_ST_fsm_state824 = 12'd823; +parameter ap_ST_fsm_state825 = 12'd824; +parameter ap_ST_fsm_state826 = 12'd825; +parameter ap_ST_fsm_state827 = 12'd826; +parameter ap_ST_fsm_state828 = 12'd827; +parameter ap_ST_fsm_state829 = 12'd828; +parameter ap_ST_fsm_state830 = 12'd829; +parameter ap_ST_fsm_state831 = 12'd830; +parameter ap_ST_fsm_state832 = 12'd831; +parameter ap_ST_fsm_state833 = 12'd832; +parameter ap_ST_fsm_state834 = 12'd833; +parameter ap_ST_fsm_state835 = 12'd834; +parameter ap_ST_fsm_state836 = 12'd835; +parameter ap_ST_fsm_state837 = 12'd836; +parameter ap_ST_fsm_state838 = 12'd837; +parameter ap_ST_fsm_state839 = 12'd838; +parameter ap_ST_fsm_state840 = 12'd839; +parameter ap_ST_fsm_state841 = 12'd840; +parameter ap_ST_fsm_state842 = 12'd841; +parameter ap_ST_fsm_state843 = 12'd842; +parameter ap_ST_fsm_state844 = 12'd843; +parameter ap_ST_fsm_state845 = 12'd844; +parameter ap_ST_fsm_state846 = 12'd845; +parameter ap_ST_fsm_state847 = 12'd846; +parameter ap_ST_fsm_state848 = 12'd847; +parameter ap_ST_fsm_state849 = 12'd848; +parameter ap_ST_fsm_state850 = 12'd849; +parameter ap_ST_fsm_state851 = 12'd850; +parameter ap_ST_fsm_state852 = 12'd851; +parameter ap_ST_fsm_state853 = 12'd852; +parameter ap_ST_fsm_state854 = 12'd853; +parameter ap_ST_fsm_state855 = 12'd854; +parameter ap_ST_fsm_state856 = 12'd855; +parameter ap_ST_fsm_state857 = 12'd856; +parameter ap_ST_fsm_state858 = 12'd857; +parameter ap_ST_fsm_state859 = 12'd858; +parameter ap_ST_fsm_state860 = 12'd859; +parameter ap_ST_fsm_state861 = 12'd860; +parameter ap_ST_fsm_state862 = 12'd861; +parameter ap_ST_fsm_state863 = 12'd862; +parameter ap_ST_fsm_state864 = 12'd863; +parameter ap_ST_fsm_state865 = 12'd864; +parameter ap_ST_fsm_state866 = 12'd865; +parameter ap_ST_fsm_state867 = 12'd866; +parameter ap_ST_fsm_state868 = 12'd867; +parameter ap_ST_fsm_state869 = 12'd868; +parameter ap_ST_fsm_state870 = 12'd869; +parameter ap_ST_fsm_state871 = 12'd870; +parameter ap_ST_fsm_state872 = 12'd871; +parameter ap_ST_fsm_state873 = 12'd872; +parameter ap_ST_fsm_state874 = 12'd873; +parameter ap_ST_fsm_state875 = 12'd874; +parameter ap_ST_fsm_state876 = 12'd875; +parameter ap_ST_fsm_state877 = 12'd876; +parameter ap_ST_fsm_state878 = 12'd877; +parameter ap_ST_fsm_state879 = 12'd878; +parameter ap_ST_fsm_state880 = 12'd879; +parameter ap_ST_fsm_state881 = 12'd880; +parameter ap_ST_fsm_state882 = 12'd881; +parameter ap_ST_fsm_state883 = 12'd882; +parameter ap_ST_fsm_state884 = 12'd883; +parameter ap_ST_fsm_state885 = 12'd884; +parameter ap_ST_fsm_state886 = 12'd885; +parameter ap_ST_fsm_state887 = 12'd886; +parameter ap_ST_fsm_state888 = 12'd887; +parameter ap_ST_fsm_state889 = 12'd888; +parameter ap_ST_fsm_state890 = 12'd889; +parameter ap_ST_fsm_state891 = 12'd890; +parameter ap_ST_fsm_state892 = 12'd891; +parameter ap_ST_fsm_state893 = 12'd892; +parameter ap_ST_fsm_state894 = 12'd893; +parameter ap_ST_fsm_state895 = 12'd894; +parameter ap_ST_fsm_state896 = 12'd895; +parameter ap_ST_fsm_state897 = 12'd896; +parameter ap_ST_fsm_state898 = 12'd897; +parameter ap_ST_fsm_state899 = 12'd898; +parameter ap_ST_fsm_state900 = 12'd899; +parameter ap_ST_fsm_state901 = 12'd900; +parameter ap_ST_fsm_state902 = 12'd901; +parameter ap_ST_fsm_state903 = 12'd902; +parameter ap_ST_fsm_state904 = 12'd903; +parameter ap_ST_fsm_state905 = 12'd904; +parameter ap_ST_fsm_state906 = 12'd905; +parameter ap_ST_fsm_state907 = 12'd906; +parameter ap_ST_fsm_state908 = 12'd907; +parameter ap_ST_fsm_state909 = 12'd908; +parameter ap_ST_fsm_state910 = 12'd909; +parameter ap_ST_fsm_state911 = 12'd910; +parameter ap_ST_fsm_state912 = 12'd911; +parameter ap_ST_fsm_state913 = 12'd912; +parameter ap_ST_fsm_state914 = 12'd913; +parameter ap_ST_fsm_state915 = 12'd914; +parameter ap_ST_fsm_state916 = 12'd915; +parameter ap_ST_fsm_state917 = 12'd916; +parameter ap_ST_fsm_state918 = 12'd917; +parameter ap_ST_fsm_state919 = 12'd918; +parameter ap_ST_fsm_state920 = 12'd919; +parameter ap_ST_fsm_state921 = 12'd920; +parameter ap_ST_fsm_state922 = 12'd921; +parameter ap_ST_fsm_state923 = 12'd922; +parameter ap_ST_fsm_state924 = 12'd923; +parameter ap_ST_fsm_state925 = 12'd924; +parameter ap_ST_fsm_state926 = 12'd925; +parameter ap_ST_fsm_state927 = 12'd926; +parameter ap_ST_fsm_state928 = 12'd927; +parameter ap_ST_fsm_state929 = 12'd928; +parameter ap_ST_fsm_state930 = 12'd929; +parameter ap_ST_fsm_state931 = 12'd930; +parameter ap_ST_fsm_state932 = 12'd931; +parameter ap_ST_fsm_state933 = 12'd932; +parameter ap_ST_fsm_state934 = 12'd933; +parameter ap_ST_fsm_state935 = 12'd934; +parameter ap_ST_fsm_state936 = 12'd935; +parameter ap_ST_fsm_state937 = 12'd936; +parameter ap_ST_fsm_state938 = 12'd937; +parameter ap_ST_fsm_state939 = 12'd938; +parameter ap_ST_fsm_state940 = 12'd939; +parameter ap_ST_fsm_state941 = 12'd940; +parameter ap_ST_fsm_state942 = 12'd941; +parameter ap_ST_fsm_state943 = 12'd942; +parameter ap_ST_fsm_state944 = 12'd943; +parameter ap_ST_fsm_state945 = 12'd944; +parameter ap_ST_fsm_state946 = 12'd945; +parameter ap_ST_fsm_state947 = 12'd946; +parameter ap_ST_fsm_state948 = 12'd947; +parameter ap_ST_fsm_state949 = 12'd948; +parameter ap_ST_fsm_state950 = 12'd949; +parameter ap_ST_fsm_state951 = 12'd950; +parameter ap_ST_fsm_state952 = 12'd951; +parameter ap_ST_fsm_state953 = 12'd952; +parameter ap_ST_fsm_state954 = 12'd953; +parameter ap_ST_fsm_state955 = 12'd954; +parameter ap_ST_fsm_state956 = 12'd955; +parameter ap_ST_fsm_state957 = 12'd956; +parameter ap_ST_fsm_state958 = 12'd957; +parameter ap_ST_fsm_state959 = 12'd958; +parameter ap_ST_fsm_state960 = 12'd959; +parameter ap_ST_fsm_state961 = 12'd960; +parameter ap_ST_fsm_state962 = 12'd961; +parameter ap_ST_fsm_state963 = 12'd962; +parameter ap_ST_fsm_state964 = 12'd963; +parameter ap_ST_fsm_state965 = 12'd964; +parameter ap_ST_fsm_state966 = 12'd965; +parameter ap_ST_fsm_state967 = 12'd966; +parameter ap_ST_fsm_state968 = 12'd967; +parameter ap_ST_fsm_state969 = 12'd968; +parameter ap_ST_fsm_state970 = 12'd969; +parameter ap_ST_fsm_state971 = 12'd970; +parameter ap_ST_fsm_state972 = 12'd971; +parameter ap_ST_fsm_state973 = 12'd972; +parameter ap_ST_fsm_state974 = 12'd973; +parameter ap_ST_fsm_state975 = 12'd974; +parameter ap_ST_fsm_state976 = 12'd975; +parameter ap_ST_fsm_state977 = 12'd976; +parameter ap_ST_fsm_state978 = 12'd977; +parameter ap_ST_fsm_state979 = 12'd978; +parameter ap_ST_fsm_state980 = 12'd979; +parameter ap_ST_fsm_state981 = 12'd980; +parameter ap_ST_fsm_state982 = 12'd981; +parameter ap_ST_fsm_state983 = 12'd982; +parameter ap_ST_fsm_state984 = 12'd983; +parameter ap_ST_fsm_state985 = 12'd984; +parameter ap_ST_fsm_state986 = 12'd985; +parameter ap_ST_fsm_state987 = 12'd986; +parameter ap_ST_fsm_state988 = 12'd987; +parameter ap_ST_fsm_state989 = 12'd988; +parameter ap_ST_fsm_state990 = 12'd989; +parameter ap_ST_fsm_state991 = 12'd990; +parameter ap_ST_fsm_state992 = 12'd991; +parameter ap_ST_fsm_state993 = 12'd992; +parameter ap_ST_fsm_state994 = 12'd993; +parameter ap_ST_fsm_state995 = 12'd994; +parameter ap_ST_fsm_state996 = 12'd995; +parameter ap_ST_fsm_state997 = 12'd996; +parameter ap_ST_fsm_state998 = 12'd997; +parameter ap_ST_fsm_state999 = 12'd998; +parameter ap_ST_fsm_state1000 = 12'd999; +parameter ap_ST_fsm_state1001 = 12'd1000; +parameter ap_ST_fsm_state1002 = 12'd1001; +parameter ap_ST_fsm_state1003 = 12'd1002; +parameter ap_ST_fsm_state1004 = 12'd1003; +parameter ap_ST_fsm_state1005 = 12'd1004; +parameter ap_ST_fsm_state1006 = 12'd1005; +parameter ap_ST_fsm_state1007 = 12'd1006; +parameter ap_ST_fsm_state1008 = 12'd1007; +parameter ap_ST_fsm_state1009 = 12'd1008; +parameter ap_ST_fsm_state1010 = 12'd1009; +parameter ap_ST_fsm_state1011 = 12'd1010; +parameter ap_ST_fsm_state1012 = 12'd1011; +parameter ap_ST_fsm_state1013 = 12'd1012; +parameter ap_ST_fsm_state1014 = 12'd1013; +parameter ap_ST_fsm_state1015 = 12'd1014; +parameter ap_ST_fsm_state1016 = 12'd1015; +parameter ap_ST_fsm_state1017 = 12'd1016; +parameter ap_ST_fsm_state1018 = 12'd1017; +parameter ap_ST_fsm_state1019 = 12'd1018; +parameter ap_ST_fsm_state1020 = 12'd1019; +parameter ap_ST_fsm_state1021 = 12'd1020; +parameter ap_ST_fsm_state1022 = 12'd1021; +parameter ap_ST_fsm_state1023 = 12'd1022; +parameter ap_ST_fsm_state1024 = 12'd1023; +parameter ap_ST_fsm_state1025 = 12'd1024; +parameter ap_ST_fsm_state1026 = 12'd1025; +parameter ap_ST_fsm_state1027 = 12'd1026; +parameter ap_ST_fsm_state1028 = 12'd1027; +parameter ap_ST_fsm_state1029 = 12'd1028; +parameter ap_ST_fsm_state1030 = 12'd1029; +parameter ap_ST_fsm_state1031 = 12'd1030; +parameter ap_ST_fsm_state1032 = 12'd1031; +parameter ap_ST_fsm_state1033 = 12'd1032; +parameter ap_ST_fsm_state1034 = 12'd1033; +parameter ap_ST_fsm_state1035 = 12'd1034; +parameter ap_ST_fsm_state1036 = 12'd1035; +parameter ap_ST_fsm_state1037 = 12'd1036; +parameter ap_ST_fsm_state1038 = 12'd1037; +parameter ap_ST_fsm_state1039 = 12'd1038; +parameter ap_ST_fsm_state1040 = 12'd1039; +parameter ap_ST_fsm_state1041 = 12'd1040; +parameter ap_ST_fsm_state1042 = 12'd1041; +parameter ap_ST_fsm_state1043 = 12'd1042; +parameter ap_ST_fsm_state1044 = 12'd1043; +parameter ap_ST_fsm_state1045 = 12'd1044; +parameter ap_ST_fsm_state1046 = 12'd1045; +parameter ap_ST_fsm_state1047 = 12'd1046; +parameter ap_ST_fsm_state1048 = 12'd1047; +parameter ap_ST_fsm_state1049 = 12'd1048; +parameter ap_ST_fsm_state1050 = 12'd1049; +parameter ap_ST_fsm_state1051 = 12'd1050; +parameter ap_ST_fsm_state1052 = 12'd1051; +parameter ap_ST_fsm_state1053 = 12'd1052; +parameter ap_ST_fsm_state1054 = 12'd1053; +parameter ap_ST_fsm_state1055 = 12'd1054; +parameter ap_ST_fsm_state1056 = 12'd1055; +parameter ap_ST_fsm_state1057 = 12'd1056; +parameter ap_ST_fsm_state1058 = 12'd1057; +parameter ap_ST_fsm_state1059 = 12'd1058; +parameter ap_ST_fsm_state1060 = 12'd1059; +parameter ap_ST_fsm_state1061 = 12'd1060; +parameter ap_ST_fsm_state1062 = 12'd1061; +parameter ap_ST_fsm_state1063 = 12'd1062; +parameter ap_ST_fsm_state1064 = 12'd1063; +parameter ap_ST_fsm_state1065 = 12'd1064; +parameter ap_ST_fsm_state1066 = 12'd1065; +parameter ap_ST_fsm_state1067 = 12'd1066; +parameter ap_ST_fsm_state1068 = 12'd1067; +parameter ap_ST_fsm_state1069 = 12'd1068; +parameter ap_ST_fsm_state1070 = 12'd1069; +parameter ap_ST_fsm_state1071 = 12'd1070; +parameter ap_ST_fsm_state1072 = 12'd1071; +parameter ap_ST_fsm_state1073 = 12'd1072; +parameter ap_ST_fsm_state1074 = 12'd1073; +parameter ap_ST_fsm_state1075 = 12'd1074; +parameter ap_ST_fsm_state1076 = 12'd1075; +parameter ap_ST_fsm_state1077 = 12'd1076; +parameter ap_ST_fsm_state1078 = 12'd1077; +parameter ap_ST_fsm_state1079 = 12'd1078; +parameter ap_ST_fsm_state1080 = 12'd1079; +parameter ap_ST_fsm_state1081 = 12'd1080; +parameter ap_ST_fsm_state1082 = 12'd1081; +parameter ap_ST_fsm_state1083 = 12'd1082; +parameter ap_ST_fsm_state1084 = 12'd1083; +parameter ap_ST_fsm_state1085 = 12'd1084; +parameter ap_ST_fsm_state1086 = 12'd1085; +parameter ap_ST_fsm_state1087 = 12'd1086; +parameter ap_ST_fsm_state1088 = 12'd1087; +parameter ap_ST_fsm_state1089 = 12'd1088; +parameter ap_ST_fsm_state1090 = 12'd1089; +parameter ap_ST_fsm_state1091 = 12'd1090; +parameter ap_ST_fsm_state1092 = 12'd1091; +parameter ap_ST_fsm_state1093 = 12'd1092; +parameter ap_ST_fsm_state1094 = 12'd1093; +parameter ap_ST_fsm_state1095 = 12'd1094; +parameter ap_ST_fsm_state1096 = 12'd1095; +parameter ap_ST_fsm_state1097 = 12'd1096; +parameter ap_ST_fsm_state1098 = 12'd1097; +parameter ap_ST_fsm_state1099 = 12'd1098; +parameter ap_ST_fsm_state1100 = 12'd1099; +parameter ap_ST_fsm_state1101 = 12'd1100; +parameter ap_ST_fsm_state1102 = 12'd1101; +parameter ap_ST_fsm_state1103 = 12'd1102; +parameter ap_ST_fsm_state1104 = 12'd1103; +parameter ap_ST_fsm_state1105 = 12'd1104; +parameter ap_ST_fsm_state1106 = 12'd1105; +parameter ap_ST_fsm_state1107 = 12'd1106; +parameter ap_ST_fsm_state1108 = 12'd1107; +parameter ap_ST_fsm_state1109 = 12'd1108; +parameter ap_ST_fsm_state1110 = 12'd1109; +parameter ap_ST_fsm_state1111 = 12'd1110; +parameter ap_ST_fsm_state1112 = 12'd1111; +parameter ap_ST_fsm_state1113 = 12'd1112; +parameter ap_ST_fsm_state1114 = 12'd1113; +parameter ap_ST_fsm_state1115 = 12'd1114; +parameter ap_ST_fsm_state1116 = 12'd1115; +parameter ap_ST_fsm_state1117 = 12'd1116; +parameter ap_ST_fsm_state1118 = 12'd1117; +parameter ap_ST_fsm_state1119 = 12'd1118; +parameter ap_ST_fsm_state1120 = 12'd1119; +parameter ap_ST_fsm_state1121 = 12'd1120; +parameter ap_ST_fsm_state1122 = 12'd1121; +parameter ap_ST_fsm_state1123 = 12'd1122; +parameter ap_ST_fsm_state1124 = 12'd1123; +parameter ap_ST_fsm_state1125 = 12'd1124; +parameter ap_ST_fsm_state1126 = 12'd1125; +parameter ap_ST_fsm_state1127 = 12'd1126; +parameter ap_ST_fsm_state1128 = 12'd1127; +parameter ap_ST_fsm_state1129 = 12'd1128; +parameter ap_ST_fsm_state1130 = 12'd1129; +parameter ap_ST_fsm_state1131 = 12'd1130; +parameter ap_ST_fsm_state1132 = 12'd1131; +parameter ap_ST_fsm_state1133 = 12'd1132; +parameter ap_ST_fsm_state1134 = 12'd1133; +parameter ap_ST_fsm_state1135 = 12'd1134; +parameter ap_ST_fsm_state1136 = 12'd1135; +parameter ap_ST_fsm_state1137 = 12'd1136; +parameter ap_ST_fsm_state1138 = 12'd1137; +parameter ap_ST_fsm_state1139 = 12'd1138; +parameter ap_ST_fsm_state1140 = 12'd1139; +parameter ap_ST_fsm_state1141 = 12'd1140; +parameter ap_ST_fsm_state1142 = 12'd1141; +parameter ap_ST_fsm_state1143 = 12'd1142; +parameter ap_ST_fsm_state1144 = 12'd1143; +parameter ap_ST_fsm_state1145 = 12'd1144; +parameter ap_ST_fsm_state1146 = 12'd1145; +parameter ap_ST_fsm_state1147 = 12'd1146; +parameter ap_ST_fsm_state1148 = 12'd1147; +parameter ap_ST_fsm_state1149 = 12'd1148; +parameter ap_ST_fsm_state1150 = 12'd1149; +parameter ap_ST_fsm_state1151 = 12'd1150; +parameter ap_ST_fsm_state1152 = 12'd1151; +parameter ap_ST_fsm_state1153 = 12'd1152; +parameter ap_ST_fsm_state1154 = 12'd1153; +parameter ap_ST_fsm_state1155 = 12'd1154; +parameter ap_ST_fsm_state1156 = 12'd1155; +parameter ap_ST_fsm_state1157 = 12'd1156; +parameter ap_ST_fsm_state1158 = 12'd1157; +parameter ap_ST_fsm_state1159 = 12'd1158; +parameter ap_ST_fsm_state1160 = 12'd1159; +parameter ap_ST_fsm_state1161 = 12'd1160; +parameter ap_ST_fsm_state1162 = 12'd1161; +parameter ap_ST_fsm_state1163 = 12'd1162; +parameter ap_ST_fsm_state1164 = 12'd1163; +parameter ap_ST_fsm_state1165 = 12'd1164; +parameter ap_ST_fsm_state1166 = 12'd1165; +parameter ap_ST_fsm_state1167 = 12'd1166; +parameter ap_ST_fsm_state1168 = 12'd1167; +parameter ap_ST_fsm_state1169 = 12'd1168; +parameter ap_ST_fsm_state1170 = 12'd1169; +parameter ap_ST_fsm_state1171 = 12'd1170; +parameter ap_ST_fsm_state1172 = 12'd1171; +parameter ap_ST_fsm_state1173 = 12'd1172; +parameter ap_ST_fsm_state1174 = 12'd1173; +parameter ap_ST_fsm_state1175 = 12'd1174; +parameter ap_ST_fsm_state1176 = 12'd1175; +parameter ap_ST_fsm_state1177 = 12'd1176; +parameter ap_ST_fsm_state1178 = 12'd1177; +parameter ap_ST_fsm_state1179 = 12'd1178; +parameter ap_ST_fsm_state1180 = 12'd1179; +parameter ap_ST_fsm_state1181 = 12'd1180; +parameter ap_ST_fsm_state1182 = 12'd1181; +parameter ap_ST_fsm_state1183 = 12'd1182; +parameter ap_ST_fsm_state1184 = 12'd1183; +parameter ap_ST_fsm_state1185 = 12'd1184; +parameter ap_ST_fsm_state1186 = 12'd1185; +parameter ap_ST_fsm_state1187 = 12'd1186; +parameter ap_ST_fsm_state1188 = 12'd1187; +parameter ap_ST_fsm_state1189 = 12'd1188; +parameter ap_ST_fsm_state1190 = 12'd1189; +parameter ap_ST_fsm_state1191 = 12'd1190; +parameter ap_ST_fsm_state1192 = 12'd1191; +parameter ap_ST_fsm_state1193 = 12'd1192; +parameter ap_ST_fsm_state1194 = 12'd1193; +parameter ap_ST_fsm_state1195 = 12'd1194; +parameter ap_ST_fsm_state1196 = 12'd1195; +parameter ap_ST_fsm_state1197 = 12'd1196; +parameter ap_ST_fsm_state1198 = 12'd1197; +parameter ap_ST_fsm_state1199 = 12'd1198; +parameter ap_ST_fsm_state1200 = 12'd1199; +parameter ap_ST_fsm_state1201 = 12'd1200; +parameter ap_ST_fsm_state1202 = 12'd1201; +parameter ap_ST_fsm_state1203 = 12'd1202; +parameter ap_ST_fsm_state1204 = 12'd1203; +parameter ap_ST_fsm_state1205 = 12'd1204; +parameter ap_ST_fsm_state1206 = 12'd1205; +parameter ap_ST_fsm_state1207 = 12'd1206; +parameter ap_ST_fsm_state1208 = 12'd1207; +parameter ap_ST_fsm_state1209 = 12'd1208; +parameter ap_ST_fsm_state1210 = 12'd1209; +parameter ap_ST_fsm_state1211 = 12'd1210; +parameter ap_ST_fsm_state1212 = 12'd1211; +parameter ap_ST_fsm_state1213 = 12'd1212; +parameter ap_ST_fsm_state1214 = 12'd1213; +parameter ap_ST_fsm_state1215 = 12'd1214; +parameter ap_ST_fsm_state1216 = 12'd1215; +parameter ap_ST_fsm_state1217 = 12'd1216; +parameter ap_ST_fsm_state1218 = 12'd1217; +parameter ap_ST_fsm_state1219 = 12'd1218; +parameter ap_ST_fsm_state1220 = 12'd1219; +parameter ap_ST_fsm_state1221 = 12'd1220; +parameter ap_ST_fsm_state1222 = 12'd1221; +parameter ap_ST_fsm_state1223 = 12'd1222; +parameter ap_ST_fsm_state1224 = 12'd1223; +parameter ap_ST_fsm_state1225 = 12'd1224; +parameter ap_ST_fsm_state1226 = 12'd1225; +parameter ap_ST_fsm_state1227 = 12'd1226; +parameter ap_ST_fsm_state1228 = 12'd1227; +parameter ap_ST_fsm_state1229 = 12'd1228; +parameter ap_ST_fsm_state1230 = 12'd1229; +parameter ap_ST_fsm_state1231 = 12'd1230; +parameter ap_ST_fsm_state1232 = 12'd1231; +parameter ap_ST_fsm_state1233 = 12'd1232; +parameter ap_ST_fsm_state1234 = 12'd1233; +parameter ap_ST_fsm_state1235 = 12'd1234; +parameter ap_ST_fsm_state1236 = 12'd1235; +parameter ap_ST_fsm_state1237 = 12'd1236; +parameter ap_ST_fsm_state1238 = 12'd1237; +parameter ap_ST_fsm_state1239 = 12'd1238; +parameter ap_ST_fsm_state1240 = 12'd1239; +parameter ap_ST_fsm_state1241 = 12'd1240; +parameter ap_ST_fsm_state1242 = 12'd1241; +parameter ap_ST_fsm_state1243 = 12'd1242; +parameter ap_ST_fsm_state1244 = 12'd1243; +parameter ap_ST_fsm_state1245 = 12'd1244; +parameter ap_ST_fsm_state1246 = 12'd1245; +parameter ap_ST_fsm_state1247 = 12'd1246; +parameter ap_ST_fsm_state1248 = 12'd1247; +parameter ap_ST_fsm_state1249 = 12'd1248; +parameter ap_ST_fsm_state1250 = 12'd1249; +parameter ap_ST_fsm_state1251 = 12'd1250; +parameter ap_ST_fsm_state1252 = 12'd1251; +parameter ap_ST_fsm_state1253 = 12'd1252; +parameter ap_ST_fsm_state1254 = 12'd1253; +parameter ap_ST_fsm_state1255 = 12'd1254; +parameter ap_ST_fsm_state1256 = 12'd1255; +parameter ap_ST_fsm_state1257 = 12'd1256; +parameter ap_ST_fsm_state1258 = 12'd1257; +parameter ap_ST_fsm_state1259 = 12'd1258; +parameter ap_ST_fsm_state1260 = 12'd1259; +parameter ap_ST_fsm_state1261 = 12'd1260; +parameter ap_ST_fsm_state1262 = 12'd1261; +parameter ap_ST_fsm_state1263 = 12'd1262; +parameter ap_ST_fsm_state1264 = 12'd1263; +parameter ap_ST_fsm_state1265 = 12'd1264; +parameter ap_ST_fsm_state1266 = 12'd1265; +parameter ap_ST_fsm_state1267 = 12'd1266; +parameter ap_ST_fsm_state1268 = 12'd1267; +parameter ap_ST_fsm_state1269 = 12'd1268; +parameter ap_ST_fsm_state1270 = 12'd1269; +parameter ap_ST_fsm_state1271 = 12'd1270; +parameter ap_ST_fsm_state1272 = 12'd1271; +parameter ap_ST_fsm_state1273 = 12'd1272; +parameter ap_ST_fsm_state1274 = 12'd1273; +parameter ap_ST_fsm_state1275 = 12'd1274; +parameter ap_ST_fsm_state1276 = 12'd1275; +parameter ap_ST_fsm_state1277 = 12'd1276; +parameter ap_ST_fsm_state1278 = 12'd1277; +parameter ap_ST_fsm_state1279 = 12'd1278; +parameter ap_ST_fsm_state1280 = 12'd1279; +parameter ap_ST_fsm_state1281 = 12'd1280; +parameter ap_ST_fsm_state1282 = 12'd1281; +parameter ap_ST_fsm_state1283 = 12'd1282; +parameter ap_ST_fsm_state1284 = 12'd1283; +parameter ap_ST_fsm_state1285 = 12'd1284; +parameter ap_ST_fsm_state1286 = 12'd1285; +parameter ap_ST_fsm_state1287 = 12'd1286; +parameter ap_ST_fsm_state1288 = 12'd1287; +parameter ap_ST_fsm_state1289 = 12'd1288; +parameter ap_ST_fsm_state1290 = 12'd1289; +parameter ap_ST_fsm_state1291 = 12'd1290; +parameter ap_ST_fsm_state1292 = 12'd1291; +parameter ap_ST_fsm_state1293 = 12'd1292; +parameter ap_ST_fsm_state1294 = 12'd1293; +parameter ap_ST_fsm_state1295 = 12'd1294; +parameter ap_ST_fsm_state1296 = 12'd1295; +parameter ap_ST_fsm_state1297 = 12'd1296; +parameter ap_ST_fsm_state1298 = 12'd1297; +parameter ap_ST_fsm_state1299 = 12'd1298; +parameter ap_ST_fsm_state1300 = 12'd1299; +parameter ap_ST_fsm_state1301 = 12'd1300; +parameter ap_ST_fsm_state1302 = 12'd1301; +parameter ap_ST_fsm_state1303 = 12'd1302; +parameter ap_ST_fsm_state1304 = 12'd1303; +parameter ap_ST_fsm_state1305 = 12'd1304; +parameter ap_ST_fsm_state1306 = 12'd1305; +parameter ap_ST_fsm_state1307 = 12'd1306; +parameter ap_ST_fsm_state1308 = 12'd1307; +parameter ap_ST_fsm_state1309 = 12'd1308; +parameter ap_ST_fsm_state1310 = 12'd1309; +parameter ap_ST_fsm_state1311 = 12'd1310; +parameter ap_ST_fsm_state1312 = 12'd1311; +parameter ap_ST_fsm_state1313 = 12'd1312; +parameter ap_ST_fsm_state1314 = 12'd1313; +parameter ap_ST_fsm_state1315 = 12'd1314; +parameter ap_ST_fsm_state1316 = 12'd1315; +parameter ap_ST_fsm_state1317 = 12'd1316; +parameter ap_ST_fsm_state1318 = 12'd1317; +parameter ap_ST_fsm_state1319 = 12'd1318; +parameter ap_ST_fsm_state1320 = 12'd1319; +parameter ap_ST_fsm_state1321 = 12'd1320; +parameter ap_ST_fsm_state1322 = 12'd1321; +parameter ap_ST_fsm_state1323 = 12'd1322; +parameter ap_ST_fsm_state1324 = 12'd1323; +parameter ap_ST_fsm_state1325 = 12'd1324; +parameter ap_ST_fsm_state1326 = 12'd1325; +parameter ap_ST_fsm_state1327 = 12'd1326; +parameter ap_ST_fsm_state1328 = 12'd1327; +parameter ap_ST_fsm_state1329 = 12'd1328; +parameter ap_ST_fsm_state1330 = 12'd1329; +parameter ap_ST_fsm_state1331 = 12'd1330; +parameter ap_ST_fsm_state1332 = 12'd1331; +parameter ap_ST_fsm_state1333 = 12'd1332; +parameter ap_ST_fsm_state1334 = 12'd1333; +parameter ap_ST_fsm_state1335 = 12'd1334; +parameter ap_ST_fsm_state1336 = 12'd1335; +parameter ap_ST_fsm_state1337 = 12'd1336; +parameter ap_ST_fsm_state1338 = 12'd1337; +parameter ap_ST_fsm_state1339 = 12'd1338; +parameter ap_ST_fsm_state1340 = 12'd1339; +parameter ap_ST_fsm_state1341 = 12'd1340; +parameter ap_ST_fsm_state1342 = 12'd1341; +parameter ap_ST_fsm_state1343 = 12'd1342; +parameter ap_ST_fsm_state1344 = 12'd1343; +parameter ap_ST_fsm_state1345 = 12'd1344; +parameter ap_ST_fsm_state1346 = 12'd1345; +parameter ap_ST_fsm_state1347 = 12'd1346; +parameter ap_ST_fsm_state1348 = 12'd1347; +parameter ap_ST_fsm_state1349 = 12'd1348; +parameter ap_ST_fsm_state1350 = 12'd1349; +parameter ap_ST_fsm_state1351 = 12'd1350; +parameter ap_ST_fsm_state1352 = 12'd1351; +parameter ap_ST_fsm_state1353 = 12'd1352; +parameter ap_ST_fsm_state1354 = 12'd1353; +parameter ap_ST_fsm_state1355 = 12'd1354; +parameter ap_ST_fsm_state1356 = 12'd1355; +parameter ap_ST_fsm_state1357 = 12'd1356; +parameter ap_ST_fsm_state1358 = 12'd1357; +parameter ap_ST_fsm_state1359 = 12'd1358; +parameter ap_ST_fsm_state1360 = 12'd1359; +parameter ap_ST_fsm_state1361 = 12'd1360; +parameter ap_ST_fsm_state1362 = 12'd1361; +parameter ap_ST_fsm_state1363 = 12'd1362; +parameter ap_ST_fsm_state1364 = 12'd1363; +parameter ap_ST_fsm_state1365 = 12'd1364; +parameter ap_ST_fsm_state1366 = 12'd1365; +parameter ap_ST_fsm_state1367 = 12'd1366; +parameter ap_ST_fsm_state1368 = 12'd1367; +parameter ap_ST_fsm_state1369 = 12'd1368; +parameter ap_ST_fsm_state1370 = 12'd1369; +parameter ap_ST_fsm_state1371 = 12'd1370; +parameter ap_ST_fsm_state1372 = 12'd1371; +parameter ap_ST_fsm_state1373 = 12'd1372; +parameter ap_ST_fsm_state1374 = 12'd1373; +parameter ap_ST_fsm_state1375 = 12'd1374; +parameter ap_ST_fsm_state1376 = 12'd1375; +parameter ap_ST_fsm_state1377 = 12'd1376; +parameter ap_ST_fsm_state1378 = 12'd1377; +parameter ap_ST_fsm_state1379 = 12'd1378; +parameter ap_ST_fsm_state1380 = 12'd1379; +parameter ap_ST_fsm_state1381 = 12'd1380; +parameter ap_ST_fsm_state1382 = 12'd1381; +parameter ap_ST_fsm_state1383 = 12'd1382; +parameter ap_ST_fsm_state1384 = 12'd1383; +parameter ap_ST_fsm_state1385 = 12'd1384; +parameter ap_ST_fsm_state1386 = 12'd1385; +parameter ap_ST_fsm_state1387 = 12'd1386; +parameter ap_ST_fsm_state1388 = 12'd1387; +parameter ap_ST_fsm_state1389 = 12'd1388; +parameter ap_ST_fsm_state1390 = 12'd1389; +parameter ap_ST_fsm_state1391 = 12'd1390; +parameter ap_ST_fsm_state1392 = 12'd1391; +parameter ap_ST_fsm_state1393 = 12'd1392; +parameter ap_ST_fsm_state1394 = 12'd1393; +parameter ap_ST_fsm_state1395 = 12'd1394; +parameter ap_ST_fsm_state1396 = 12'd1395; +parameter ap_ST_fsm_state1397 = 12'd1396; +parameter ap_ST_fsm_state1398 = 12'd1397; +parameter ap_ST_fsm_state1399 = 12'd1398; +parameter ap_ST_fsm_state1400 = 12'd1399; +parameter ap_ST_fsm_state1401 = 12'd1400; +parameter ap_ST_fsm_state1402 = 12'd1401; +parameter ap_ST_fsm_state1403 = 12'd1402; +parameter ap_ST_fsm_state1404 = 12'd1403; +parameter ap_ST_fsm_state1405 = 12'd1404; +parameter ap_ST_fsm_state1406 = 12'd1405; +parameter ap_ST_fsm_state1407 = 12'd1406; +parameter ap_ST_fsm_state1408 = 12'd1407; +parameter ap_ST_fsm_state1409 = 12'd1408; +parameter ap_ST_fsm_state1410 = 12'd1409; +parameter ap_ST_fsm_state1411 = 12'd1410; +parameter ap_ST_fsm_state1412 = 12'd1411; +parameter ap_ST_fsm_state1413 = 12'd1412; +parameter ap_ST_fsm_state1414 = 12'd1413; +parameter ap_ST_fsm_state1415 = 12'd1414; +parameter ap_ST_fsm_state1416 = 12'd1415; +parameter ap_ST_fsm_state1417 = 12'd1416; +parameter ap_ST_fsm_state1418 = 12'd1417; +parameter ap_ST_fsm_state1419 = 12'd1418; +parameter ap_ST_fsm_state1420 = 12'd1419; +parameter ap_ST_fsm_state1421 = 12'd1420; +parameter ap_ST_fsm_state1422 = 12'd1421; +parameter ap_ST_fsm_state1423 = 12'd1422; +parameter ap_ST_fsm_state1424 = 12'd1423; +parameter ap_ST_fsm_state1425 = 12'd1424; +parameter ap_ST_fsm_state1426 = 12'd1425; +parameter ap_ST_fsm_state1427 = 12'd1426; +parameter ap_ST_fsm_state1428 = 12'd1427; +parameter ap_ST_fsm_state1429 = 12'd1428; +parameter ap_ST_fsm_state1430 = 12'd1429; +parameter ap_ST_fsm_state1431 = 12'd1430; +parameter ap_ST_fsm_state1432 = 12'd1431; +parameter ap_ST_fsm_state1433 = 12'd1432; +parameter ap_ST_fsm_state1434 = 12'd1433; +parameter ap_ST_fsm_state1435 = 12'd1434; +parameter ap_ST_fsm_state1436 = 12'd1435; +parameter ap_ST_fsm_state1437 = 12'd1436; +parameter ap_ST_fsm_state1438 = 12'd1437; +parameter ap_ST_fsm_state1439 = 12'd1438; +parameter ap_ST_fsm_state1440 = 12'd1439; +parameter ap_ST_fsm_state1441 = 12'd1440; +parameter ap_ST_fsm_state1442 = 12'd1441; +parameter ap_ST_fsm_state1443 = 12'd1442; +parameter ap_ST_fsm_state1444 = 12'd1443; +parameter ap_ST_fsm_state1445 = 12'd1444; +parameter ap_ST_fsm_state1446 = 12'd1445; +parameter ap_ST_fsm_state1447 = 12'd1446; +parameter ap_ST_fsm_state1448 = 12'd1447; +parameter ap_ST_fsm_state1449 = 12'd1448; +parameter ap_ST_fsm_state1450 = 12'd1449; +parameter ap_ST_fsm_state1451 = 12'd1450; +parameter ap_ST_fsm_state1452 = 12'd1451; +parameter ap_ST_fsm_state1453 = 12'd1452; +parameter ap_ST_fsm_state1454 = 12'd1453; +parameter ap_ST_fsm_state1455 = 12'd1454; +parameter ap_ST_fsm_state1456 = 12'd1455; +parameter ap_ST_fsm_state1457 = 12'd1456; +parameter ap_ST_fsm_state1458 = 12'd1457; +parameter ap_ST_fsm_state1459 = 12'd1458; +parameter ap_ST_fsm_state1460 = 12'd1459; +parameter ap_ST_fsm_state1461 = 12'd1460; +parameter ap_ST_fsm_state1462 = 12'd1461; +parameter ap_ST_fsm_state1463 = 12'd1462; +parameter ap_ST_fsm_state1464 = 12'd1463; +parameter ap_ST_fsm_state1465 = 12'd1464; +parameter ap_ST_fsm_state1466 = 12'd1465; +parameter ap_ST_fsm_state1467 = 12'd1466; +parameter ap_ST_fsm_state1468 = 12'd1467; +parameter ap_ST_fsm_state1469 = 12'd1468; +parameter ap_ST_fsm_state1470 = 12'd1469; +parameter ap_ST_fsm_state1471 = 12'd1470; +parameter ap_ST_fsm_state1472 = 12'd1471; +parameter ap_ST_fsm_state1473 = 12'd1472; +parameter ap_ST_fsm_state1474 = 12'd1473; +parameter ap_ST_fsm_state1475 = 12'd1474; +parameter ap_ST_fsm_state1476 = 12'd1475; +parameter ap_ST_fsm_state1477 = 12'd1476; +parameter ap_ST_fsm_state1478 = 12'd1477; +parameter ap_ST_fsm_state1479 = 12'd1478; +parameter ap_ST_fsm_state1480 = 12'd1479; +parameter ap_ST_fsm_state1481 = 12'd1480; +parameter ap_ST_fsm_state1482 = 12'd1481; +parameter ap_ST_fsm_state1483 = 12'd1482; +parameter ap_ST_fsm_state1484 = 12'd1483; +parameter ap_ST_fsm_state1485 = 12'd1484; +parameter ap_ST_fsm_state1486 = 12'd1485; +parameter ap_ST_fsm_state1487 = 12'd1486; +parameter ap_ST_fsm_state1488 = 12'd1487; +parameter ap_ST_fsm_state1489 = 12'd1488; +parameter ap_ST_fsm_state1490 = 12'd1489; +parameter ap_ST_fsm_state1491 = 12'd1490; +parameter ap_ST_fsm_state1492 = 12'd1491; +parameter ap_ST_fsm_state1493 = 12'd1492; +parameter ap_ST_fsm_state1494 = 12'd1493; +parameter ap_ST_fsm_state1495 = 12'd1494; +parameter ap_ST_fsm_state1496 = 12'd1495; +parameter ap_ST_fsm_state1497 = 12'd1496; +parameter ap_ST_fsm_state1498 = 12'd1497; +parameter ap_ST_fsm_state1499 = 12'd1498; +parameter ap_ST_fsm_state1500 = 12'd1499; +parameter ap_ST_fsm_state1501 = 12'd1500; +parameter ap_ST_fsm_state1502 = 12'd1501; +parameter ap_ST_fsm_state1503 = 12'd1502; +parameter ap_ST_fsm_state1504 = 12'd1503; +parameter ap_ST_fsm_state1505 = 12'd1504; +parameter ap_ST_fsm_state1506 = 12'd1505; +parameter ap_ST_fsm_state1507 = 12'd1506; +parameter ap_ST_fsm_state1508 = 12'd1507; +parameter ap_ST_fsm_state1509 = 12'd1508; +parameter ap_ST_fsm_state1510 = 12'd1509; +parameter ap_ST_fsm_state1511 = 12'd1510; +parameter ap_ST_fsm_state1512 = 12'd1511; +parameter ap_ST_fsm_state1513 = 12'd1512; +parameter ap_ST_fsm_state1514 = 12'd1513; +parameter ap_ST_fsm_state1515 = 12'd1514; +parameter ap_ST_fsm_state1516 = 12'd1515; +parameter ap_ST_fsm_state1517 = 12'd1516; +parameter ap_ST_fsm_state1518 = 12'd1517; +parameter ap_ST_fsm_state1519 = 12'd1518; +parameter ap_ST_fsm_state1520 = 12'd1519; +parameter ap_ST_fsm_state1521 = 12'd1520; +parameter ap_ST_fsm_state1522 = 12'd1521; +parameter ap_ST_fsm_state1523 = 12'd1522; +parameter ap_ST_fsm_state1524 = 12'd1523; +parameter ap_ST_fsm_state1525 = 12'd1524; +parameter ap_ST_fsm_state1526 = 12'd1525; +parameter ap_ST_fsm_state1527 = 12'd1526; +parameter ap_ST_fsm_state1528 = 12'd1527; +parameter ap_ST_fsm_state1529 = 12'd1528; +parameter ap_ST_fsm_state1530 = 12'd1529; +parameter ap_ST_fsm_state1531 = 12'd1530; +parameter ap_ST_fsm_state1532 = 12'd1531; +parameter ap_ST_fsm_state1533 = 12'd1532; +parameter ap_ST_fsm_state1534 = 12'd1533; +parameter ap_ST_fsm_state1535 = 12'd1534; +parameter ap_ST_fsm_state1536 = 12'd1535; +parameter ap_ST_fsm_state1537 = 12'd1536; +parameter ap_ST_fsm_state1538 = 12'd1537; +parameter ap_ST_fsm_state1539 = 12'd1538; +parameter ap_ST_fsm_state1540 = 12'd1539; +parameter ap_ST_fsm_state1541 = 12'd1540; +parameter ap_ST_fsm_state1542 = 12'd1541; +parameter ap_ST_fsm_state1543 = 12'd1542; +parameter ap_ST_fsm_state1544 = 12'd1543; +parameter ap_ST_fsm_state1545 = 12'd1544; +parameter ap_ST_fsm_state1546 = 12'd1545; +parameter ap_ST_fsm_state1547 = 12'd1546; +parameter ap_ST_fsm_state1548 = 12'd1547; +parameter ap_ST_fsm_state1549 = 12'd1548; +parameter ap_ST_fsm_state1550 = 12'd1549; +parameter ap_ST_fsm_state1551 = 12'd1550; +parameter ap_ST_fsm_state1552 = 12'd1551; +parameter ap_ST_fsm_state1553 = 12'd1552; +parameter ap_ST_fsm_state1554 = 12'd1553; +parameter ap_ST_fsm_state1555 = 12'd1554; +parameter ap_ST_fsm_state1556 = 12'd1555; +parameter ap_ST_fsm_state1557 = 12'd1556; +parameter ap_ST_fsm_state1558 = 12'd1557; +parameter ap_ST_fsm_state1559 = 12'd1558; +parameter ap_ST_fsm_state1560 = 12'd1559; +parameter ap_ST_fsm_state1561 = 12'd1560; +parameter ap_ST_fsm_state1562 = 12'd1561; +parameter ap_ST_fsm_state1563 = 12'd1562; +parameter ap_ST_fsm_state1564 = 12'd1563; +parameter ap_ST_fsm_state1565 = 12'd1564; +parameter ap_ST_fsm_state1566 = 12'd1565; +parameter ap_ST_fsm_state1567 = 12'd1566; +parameter ap_ST_fsm_state1568 = 12'd1567; +parameter ap_ST_fsm_state1569 = 12'd1568; +parameter ap_ST_fsm_state1570 = 12'd1569; +parameter ap_ST_fsm_state1571 = 12'd1570; +parameter ap_ST_fsm_state1572 = 12'd1571; +parameter ap_ST_fsm_state1573 = 12'd1572; +parameter ap_ST_fsm_state1574 = 12'd1573; +parameter ap_ST_fsm_state1575 = 12'd1574; +parameter ap_ST_fsm_state1576 = 12'd1575; +parameter ap_ST_fsm_state1577 = 12'd1576; +parameter ap_ST_fsm_state1578 = 12'd1577; +parameter ap_ST_fsm_state1579 = 12'd1578; +parameter ap_ST_fsm_state1580 = 12'd1579; +parameter ap_ST_fsm_state1581 = 12'd1580; +parameter ap_ST_fsm_state1582 = 12'd1581; +parameter ap_ST_fsm_state1583 = 12'd1582; +parameter ap_ST_fsm_state1584 = 12'd1583; +parameter ap_ST_fsm_state1585 = 12'd1584; +parameter ap_ST_fsm_state1586 = 12'd1585; +parameter ap_ST_fsm_state1587 = 12'd1586; +parameter ap_ST_fsm_state1588 = 12'd1587; +parameter ap_ST_fsm_state1589 = 12'd1588; +parameter ap_ST_fsm_state1590 = 12'd1589; +parameter ap_ST_fsm_state1591 = 12'd1590; +parameter ap_ST_fsm_state1592 = 12'd1591; +parameter ap_ST_fsm_state1593 = 12'd1592; +parameter ap_ST_fsm_state1594 = 12'd1593; +parameter ap_ST_fsm_state1595 = 12'd1594; +parameter ap_ST_fsm_state1596 = 12'd1595; +parameter ap_ST_fsm_state1597 = 12'd1596; +parameter ap_ST_fsm_state1598 = 12'd1597; +parameter ap_ST_fsm_state1599 = 12'd1598; +parameter ap_ST_fsm_state1600 = 12'd1599; +parameter ap_ST_fsm_state1601 = 12'd1600; +parameter ap_ST_fsm_state1602 = 12'd1601; +parameter ap_ST_fsm_state1603 = 12'd1602; +parameter ap_ST_fsm_state1604 = 12'd1603; +parameter ap_ST_fsm_state1605 = 12'd1604; +parameter ap_ST_fsm_state1606 = 12'd1605; +parameter ap_ST_fsm_state1607 = 12'd1606; +parameter ap_ST_fsm_state1608 = 12'd1607; +parameter ap_ST_fsm_state1609 = 12'd1608; +parameter ap_ST_fsm_state1610 = 12'd1609; +parameter ap_ST_fsm_state1611 = 12'd1610; +parameter ap_ST_fsm_state1612 = 12'd1611; +parameter ap_ST_fsm_state1613 = 12'd1612; +parameter ap_ST_fsm_state1614 = 12'd1613; +parameter ap_ST_fsm_state1615 = 12'd1614; +parameter ap_ST_fsm_state1616 = 12'd1615; +parameter ap_ST_fsm_state1617 = 12'd1616; +parameter ap_ST_fsm_state1618 = 12'd1617; +parameter ap_ST_fsm_state1619 = 12'd1618; +parameter ap_ST_fsm_state1620 = 12'd1619; +parameter ap_ST_fsm_state1621 = 12'd1620; +parameter ap_ST_fsm_state1622 = 12'd1621; +parameter ap_ST_fsm_state1623 = 12'd1622; +parameter ap_ST_fsm_state1624 = 12'd1623; +parameter ap_ST_fsm_state1625 = 12'd1624; +parameter ap_ST_fsm_state1626 = 12'd1625; +parameter ap_ST_fsm_state1627 = 12'd1626; +parameter ap_ST_fsm_state1628 = 12'd1627; +parameter ap_ST_fsm_state1629 = 12'd1628; +parameter ap_ST_fsm_state1630 = 12'd1629; +parameter ap_ST_fsm_state1631 = 12'd1630; +parameter ap_ST_fsm_state1632 = 12'd1631; +parameter ap_ST_fsm_state1633 = 12'd1632; +parameter ap_ST_fsm_state1634 = 12'd1633; +parameter ap_ST_fsm_state1635 = 12'd1634; +parameter ap_ST_fsm_state1636 = 12'd1635; +parameter ap_ST_fsm_state1637 = 12'd1636; +parameter ap_ST_fsm_state1638 = 12'd1637; +parameter ap_ST_fsm_state1639 = 12'd1638; +parameter ap_ST_fsm_state1640 = 12'd1639; +parameter ap_ST_fsm_state1641 = 12'd1640; +parameter ap_ST_fsm_state1642 = 12'd1641; +parameter ap_ST_fsm_state1643 = 12'd1642; +parameter ap_ST_fsm_state1644 = 12'd1643; +parameter ap_ST_fsm_state1645 = 12'd1644; +parameter ap_ST_fsm_state1646 = 12'd1645; +parameter ap_ST_fsm_state1647 = 12'd1646; +parameter ap_ST_fsm_state1648 = 12'd1647; +parameter ap_ST_fsm_state1649 = 12'd1648; +parameter ap_ST_fsm_state1650 = 12'd1649; +parameter ap_ST_fsm_state1651 = 12'd1650; +parameter ap_ST_fsm_state1652 = 12'd1651; +parameter ap_ST_fsm_state1653 = 12'd1652; +parameter ap_ST_fsm_state1654 = 12'd1653; +parameter ap_ST_fsm_state1655 = 12'd1654; +parameter ap_ST_fsm_state1656 = 12'd1655; +parameter ap_ST_fsm_state1657 = 12'd1656; +parameter ap_ST_fsm_state1658 = 12'd1657; +parameter ap_ST_fsm_state1659 = 12'd1658; +parameter ap_ST_fsm_state1660 = 12'd1659; +parameter ap_ST_fsm_state1661 = 12'd1660; +parameter ap_ST_fsm_state1662 = 12'd1661; +parameter ap_ST_fsm_state1663 = 12'd1662; +parameter ap_ST_fsm_state1664 = 12'd1663; +parameter ap_ST_fsm_state1665 = 12'd1664; +parameter ap_ST_fsm_state1666 = 12'd1665; +parameter ap_ST_fsm_state1667 = 12'd1666; +parameter ap_ST_fsm_state1668 = 12'd1667; +parameter ap_ST_fsm_state1669 = 12'd1668; +parameter ap_ST_fsm_state1670 = 12'd1669; +parameter ap_ST_fsm_state1671 = 12'd1670; +parameter ap_ST_fsm_state1672 = 12'd1671; +parameter ap_ST_fsm_state1673 = 12'd1672; +parameter ap_ST_fsm_state1674 = 12'd1673; +parameter ap_ST_fsm_state1675 = 12'd1674; +parameter ap_ST_fsm_state1676 = 12'd1675; +parameter ap_ST_fsm_state1677 = 12'd1676; +parameter ap_ST_fsm_state1678 = 12'd1677; +parameter ap_ST_fsm_state1679 = 12'd1678; +parameter ap_ST_fsm_state1680 = 12'd1679; +parameter ap_ST_fsm_state1681 = 12'd1680; +parameter ap_ST_fsm_state1682 = 12'd1681; +parameter ap_ST_fsm_state1683 = 12'd1682; +parameter ap_ST_fsm_state1684 = 12'd1683; +parameter ap_ST_fsm_state1685 = 12'd1684; +parameter ap_ST_fsm_state1686 = 12'd1685; +parameter ap_ST_fsm_state1687 = 12'd1686; +parameter ap_ST_fsm_state1688 = 12'd1687; +parameter ap_ST_fsm_state1689 = 12'd1688; +parameter ap_ST_fsm_state1690 = 12'd1689; +parameter ap_ST_fsm_state1691 = 12'd1690; +parameter ap_ST_fsm_state1692 = 12'd1691; +parameter ap_ST_fsm_state1693 = 12'd1692; +parameter ap_ST_fsm_state1694 = 12'd1693; +parameter ap_ST_fsm_state1695 = 12'd1694; +parameter ap_ST_fsm_state1696 = 12'd1695; +parameter ap_ST_fsm_state1697 = 12'd1696; +parameter ap_ST_fsm_state1698 = 12'd1697; +parameter ap_ST_fsm_state1699 = 12'd1698; +parameter ap_ST_fsm_state1700 = 12'd1699; +parameter ap_ST_fsm_state1701 = 12'd1700; +parameter ap_ST_fsm_state1702 = 12'd1701; +parameter ap_ST_fsm_state1703 = 12'd1702; +parameter ap_ST_fsm_state1704 = 12'd1703; +parameter ap_ST_fsm_state1705 = 12'd1704; +parameter ap_ST_fsm_state1706 = 12'd1705; +parameter ap_ST_fsm_state1707 = 12'd1706; +parameter ap_ST_fsm_state1708 = 12'd1707; +parameter ap_ST_fsm_state1709 = 12'd1708; +parameter ap_ST_fsm_state1710 = 12'd1709; +parameter ap_ST_fsm_state1711 = 12'd1710; +parameter ap_ST_fsm_state1712 = 12'd1711; +parameter ap_ST_fsm_state1713 = 12'd1712; +parameter ap_ST_fsm_state1714 = 12'd1713; +parameter ap_ST_fsm_state1715 = 12'd1714; +parameter ap_ST_fsm_state1716 = 12'd1715; +parameter ap_ST_fsm_state1717 = 12'd1716; +parameter ap_ST_fsm_state1718 = 12'd1717; +parameter ap_ST_fsm_state1719 = 12'd1718; +parameter ap_ST_fsm_state1720 = 12'd1719; +parameter ap_ST_fsm_state1721 = 12'd1720; +parameter ap_ST_fsm_state1722 = 12'd1721; +parameter ap_ST_fsm_state1723 = 12'd1722; +parameter ap_ST_fsm_state1724 = 12'd1723; +parameter ap_ST_fsm_state1725 = 12'd1724; +parameter ap_ST_fsm_state1726 = 12'd1725; +parameter ap_ST_fsm_state1727 = 12'd1726; +parameter ap_ST_fsm_state1728 = 12'd1727; +parameter ap_ST_fsm_state1729 = 12'd1728; +parameter ap_ST_fsm_state1730 = 12'd1729; +parameter ap_ST_fsm_state1731 = 12'd1730; +parameter ap_ST_fsm_state1732 = 12'd1731; +parameter ap_ST_fsm_state1733 = 12'd1732; +parameter ap_ST_fsm_state1734 = 12'd1733; +parameter ap_ST_fsm_state1735 = 12'd1734; +parameter ap_ST_fsm_state1736 = 12'd1735; +parameter ap_ST_fsm_state1737 = 12'd1736; +parameter ap_ST_fsm_state1738 = 12'd1737; +parameter ap_ST_fsm_state1739 = 12'd1738; +parameter ap_ST_fsm_state1740 = 12'd1739; +parameter ap_ST_fsm_state1741 = 12'd1740; +parameter ap_ST_fsm_state1742 = 12'd1741; +parameter ap_ST_fsm_state1743 = 12'd1742; +parameter ap_ST_fsm_state1744 = 12'd1743; +parameter ap_ST_fsm_state1745 = 12'd1744; +parameter ap_ST_fsm_state1746 = 12'd1745; +parameter ap_ST_fsm_state1747 = 12'd1746; +parameter ap_ST_fsm_state1748 = 12'd1747; +parameter ap_ST_fsm_state1749 = 12'd1748; +parameter ap_ST_fsm_state1750 = 12'd1749; +parameter ap_ST_fsm_state1751 = 12'd1750; +parameter ap_ST_fsm_state1752 = 12'd1751; +parameter ap_ST_fsm_state1753 = 12'd1752; +parameter ap_ST_fsm_state1754 = 12'd1753; +parameter ap_ST_fsm_state1755 = 12'd1754; +parameter ap_ST_fsm_state1756 = 12'd1755; +parameter ap_ST_fsm_state1757 = 12'd1756; +parameter ap_ST_fsm_state1758 = 12'd1757; +parameter ap_ST_fsm_state1759 = 12'd1758; +parameter ap_ST_fsm_state1760 = 12'd1759; +parameter ap_ST_fsm_state1761 = 12'd1760; +parameter ap_ST_fsm_state1762 = 12'd1761; +parameter ap_ST_fsm_state1763 = 12'd1762; +parameter ap_ST_fsm_state1764 = 12'd1763; +parameter ap_ST_fsm_state1765 = 12'd1764; +parameter ap_ST_fsm_state1766 = 12'd1765; +parameter ap_ST_fsm_state1767 = 12'd1766; +parameter ap_ST_fsm_state1768 = 12'd1767; +parameter ap_ST_fsm_state1769 = 12'd1768; +parameter ap_ST_fsm_state1770 = 12'd1769; +parameter ap_ST_fsm_state1771 = 12'd1770; +parameter ap_ST_fsm_state1772 = 12'd1771; +parameter ap_ST_fsm_state1773 = 12'd1772; +parameter ap_ST_fsm_state1774 = 12'd1773; +parameter ap_ST_fsm_state1775 = 12'd1774; +parameter ap_ST_fsm_state1776 = 12'd1775; +parameter ap_ST_fsm_state1777 = 12'd1776; +parameter ap_ST_fsm_state1778 = 12'd1777; +parameter ap_ST_fsm_state1779 = 12'd1778; +parameter ap_ST_fsm_state1780 = 12'd1779; +parameter ap_ST_fsm_state1781 = 12'd1780; +parameter ap_ST_fsm_state1782 = 12'd1781; +parameter ap_ST_fsm_state1783 = 12'd1782; +parameter ap_ST_fsm_state1784 = 12'd1783; +parameter ap_ST_fsm_state1785 = 12'd1784; +parameter ap_ST_fsm_state1786 = 12'd1785; +parameter ap_ST_fsm_state1787 = 12'd1786; +parameter ap_ST_fsm_state1788 = 12'd1787; +parameter ap_ST_fsm_state1789 = 12'd1788; +parameter ap_ST_fsm_state1790 = 12'd1789; +parameter ap_ST_fsm_state1791 = 12'd1790; +parameter ap_ST_fsm_state1792 = 12'd1791; +parameter ap_ST_fsm_state1793 = 12'd1792; +parameter ap_ST_fsm_state1794 = 12'd1793; +parameter ap_ST_fsm_state1795 = 12'd1794; +parameter ap_ST_fsm_state1796 = 12'd1795; +parameter ap_ST_fsm_state1797 = 12'd1796; +parameter ap_ST_fsm_state1798 = 12'd1797; +parameter ap_ST_fsm_state1799 = 12'd1798; +parameter ap_ST_fsm_state1800 = 12'd1799; +parameter ap_ST_fsm_state1801 = 12'd1800; +parameter ap_ST_fsm_state1802 = 12'd1801; +parameter ap_ST_fsm_state1803 = 12'd1802; +parameter ap_ST_fsm_state1804 = 12'd1803; +parameter ap_ST_fsm_state1805 = 12'd1804; +parameter ap_ST_fsm_state1806 = 12'd1805; +parameter ap_ST_fsm_state1807 = 12'd1806; +parameter ap_ST_fsm_state1808 = 12'd1807; +parameter ap_ST_fsm_state1809 = 12'd1808; +parameter ap_ST_fsm_state1810 = 12'd1809; +parameter ap_ST_fsm_state1811 = 12'd1810; +parameter ap_ST_fsm_state1812 = 12'd1811; +parameter ap_ST_fsm_state1813 = 12'd1812; +parameter ap_ST_fsm_state1814 = 12'd1813; +parameter ap_ST_fsm_state1815 = 12'd1814; +parameter ap_ST_fsm_state1816 = 12'd1815; +parameter ap_ST_fsm_state1817 = 12'd1816; +parameter ap_ST_fsm_state1818 = 12'd1817; +parameter ap_ST_fsm_state1819 = 12'd1818; +parameter ap_ST_fsm_state1820 = 12'd1819; +parameter ap_ST_fsm_state1821 = 12'd1820; +parameter ap_ST_fsm_state1822 = 12'd1821; +parameter ap_ST_fsm_state1823 = 12'd1822; +parameter ap_ST_fsm_state1824 = 12'd1823; +parameter ap_ST_fsm_state1825 = 12'd1824; +parameter ap_ST_fsm_state1826 = 12'd1825; +parameter ap_ST_fsm_state1827 = 12'd1826; +parameter ap_ST_fsm_state1828 = 12'd1827; +parameter ap_ST_fsm_state1829 = 12'd1828; +parameter ap_ST_fsm_state1830 = 12'd1829; +parameter ap_ST_fsm_state1831 = 12'd1830; +parameter ap_ST_fsm_state1832 = 12'd1831; +parameter ap_ST_fsm_state1833 = 12'd1832; +parameter ap_ST_fsm_state1834 = 12'd1833; +parameter ap_ST_fsm_state1835 = 12'd1834; +parameter ap_ST_fsm_state1836 = 12'd1835; +parameter ap_ST_fsm_state1837 = 12'd1836; +parameter ap_ST_fsm_state1838 = 12'd1837; +parameter ap_ST_fsm_state1839 = 12'd1838; +parameter ap_ST_fsm_state1840 = 12'd1839; +parameter ap_ST_fsm_state1841 = 12'd1840; +parameter ap_ST_fsm_state1842 = 12'd1841; +parameter ap_ST_fsm_state1843 = 12'd1842; +parameter ap_ST_fsm_state1844 = 12'd1843; +parameter ap_ST_fsm_state1845 = 12'd1844; +parameter ap_ST_fsm_state1846 = 12'd1845; +parameter ap_ST_fsm_state1847 = 12'd1846; +parameter ap_ST_fsm_state1848 = 12'd1847; +parameter ap_ST_fsm_state1849 = 12'd1848; +parameter ap_ST_fsm_state1850 = 12'd1849; +parameter ap_ST_fsm_state1851 = 12'd1850; +parameter ap_ST_fsm_state1852 = 12'd1851; +parameter ap_ST_fsm_state1853 = 12'd1852; +parameter ap_ST_fsm_state1854 = 12'd1853; +parameter ap_ST_fsm_state1855 = 12'd1854; +parameter ap_ST_fsm_state1856 = 12'd1855; +parameter ap_ST_fsm_state1857 = 12'd1856; +parameter ap_ST_fsm_state1858 = 12'd1857; +parameter ap_ST_fsm_state1859 = 12'd1858; +parameter ap_ST_fsm_state1860 = 12'd1859; +parameter ap_ST_fsm_state1861 = 12'd1860; +parameter ap_ST_fsm_state1862 = 12'd1861; +parameter ap_ST_fsm_state1863 = 12'd1862; +parameter ap_ST_fsm_state1864 = 12'd1863; +parameter ap_ST_fsm_state1865 = 12'd1864; +parameter ap_ST_fsm_state1866 = 12'd1865; +parameter ap_ST_fsm_state1867 = 12'd1866; +parameter ap_ST_fsm_state1868 = 12'd1867; +parameter ap_ST_fsm_state1869 = 12'd1868; +parameter ap_ST_fsm_state1870 = 12'd1869; +parameter ap_ST_fsm_state1871 = 12'd1870; +parameter ap_ST_fsm_state1872 = 12'd1871; +parameter ap_ST_fsm_state1873 = 12'd1872; +parameter ap_ST_fsm_state1874 = 12'd1873; +parameter ap_ST_fsm_state1875 = 12'd1874; +parameter ap_ST_fsm_state1876 = 12'd1875; +parameter ap_ST_fsm_state1877 = 12'd1876; +parameter ap_ST_fsm_state1878 = 12'd1877; +parameter ap_ST_fsm_state1879 = 12'd1878; +parameter ap_ST_fsm_state1880 = 12'd1879; +parameter ap_ST_fsm_state1881 = 12'd1880; +parameter ap_ST_fsm_state1882 = 12'd1881; +parameter ap_ST_fsm_state1883 = 12'd1882; +parameter ap_ST_fsm_state1884 = 12'd1883; +parameter ap_ST_fsm_state1885 = 12'd1884; +parameter ap_ST_fsm_state1886 = 12'd1885; +parameter ap_ST_fsm_state1887 = 12'd1886; +parameter ap_ST_fsm_state1888 = 12'd1887; +parameter ap_ST_fsm_state1889 = 12'd1888; +parameter ap_ST_fsm_state1890 = 12'd1889; +parameter ap_ST_fsm_state1891 = 12'd1890; +parameter ap_ST_fsm_state1892 = 12'd1891; +parameter ap_ST_fsm_state1893 = 12'd1892; +parameter ap_ST_fsm_state1894 = 12'd1893; +parameter ap_ST_fsm_state1895 = 12'd1894; +parameter ap_ST_fsm_state1896 = 12'd1895; +parameter ap_ST_fsm_state1897 = 12'd1896; +parameter ap_ST_fsm_state1898 = 12'd1897; +parameter ap_ST_fsm_state1899 = 12'd1898; +parameter ap_ST_fsm_state1900 = 12'd1899; +parameter ap_ST_fsm_state1901 = 12'd1900; +parameter ap_ST_fsm_state1902 = 12'd1901; +parameter ap_ST_fsm_state1903 = 12'd1902; +parameter ap_ST_fsm_state1904 = 12'd1903; +parameter ap_ST_fsm_state1905 = 12'd1904; +parameter ap_ST_fsm_state1906 = 12'd1905; +parameter ap_ST_fsm_state1907 = 12'd1906; +parameter ap_ST_fsm_state1908 = 12'd1907; +parameter ap_ST_fsm_state1909 = 12'd1908; +parameter ap_ST_fsm_state1910 = 12'd1909; +parameter ap_ST_fsm_state1911 = 12'd1910; +parameter ap_ST_fsm_state1912 = 12'd1911; +parameter ap_ST_fsm_state1913 = 12'd1912; +parameter ap_ST_fsm_state1914 = 12'd1913; +parameter ap_ST_fsm_state1915 = 12'd1914; +parameter ap_ST_fsm_state1916 = 12'd1915; +parameter ap_ST_fsm_state1917 = 12'd1916; +parameter ap_ST_fsm_state1918 = 12'd1917; +parameter ap_ST_fsm_state1919 = 12'd1918; +parameter ap_ST_fsm_state1920 = 12'd1919; +parameter ap_ST_fsm_state1921 = 12'd1920; +parameter ap_ST_fsm_state1922 = 12'd1921; +parameter ap_ST_fsm_state1923 = 12'd1922; +parameter ap_ST_fsm_state1924 = 12'd1923; +parameter ap_ST_fsm_state1925 = 12'd1924; +parameter ap_ST_fsm_state1926 = 12'd1925; +parameter ap_ST_fsm_state1927 = 12'd1926; +parameter ap_ST_fsm_state1928 = 12'd1927; +parameter ap_ST_fsm_state1929 = 12'd1928; +parameter ap_ST_fsm_state1930 = 12'd1929; +parameter ap_ST_fsm_state1931 = 12'd1930; +parameter ap_ST_fsm_state1932 = 12'd1931; +parameter ap_ST_fsm_state1933 = 12'd1932; +parameter ap_ST_fsm_state1934 = 12'd1933; +parameter ap_ST_fsm_state1935 = 12'd1934; +parameter ap_ST_fsm_state1936 = 12'd1935; +parameter ap_ST_fsm_state1937 = 12'd1936; +parameter ap_ST_fsm_state1938 = 12'd1937; +parameter ap_ST_fsm_state1939 = 12'd1938; +parameter ap_ST_fsm_state1940 = 12'd1939; +parameter ap_ST_fsm_state1941 = 12'd1940; +parameter ap_ST_fsm_state1942 = 12'd1941; +parameter ap_ST_fsm_state1943 = 12'd1942; +parameter ap_ST_fsm_state1944 = 12'd1943; +parameter ap_ST_fsm_state1945 = 12'd1944; +parameter ap_ST_fsm_state1946 = 12'd1945; +parameter ap_ST_fsm_state1947 = 12'd1946; +parameter ap_ST_fsm_state1948 = 12'd1947; +parameter ap_ST_fsm_state1949 = 12'd1948; +parameter ap_ST_fsm_state1950 = 12'd1949; +parameter ap_ST_fsm_state1951 = 12'd1950; +parameter ap_ST_fsm_state1952 = 12'd1951; +parameter ap_ST_fsm_state1953 = 12'd1952; +parameter ap_ST_fsm_state1954 = 12'd1953; +parameter ap_ST_fsm_state1955 = 12'd1954; +parameter ap_ST_fsm_state1956 = 12'd1955; +parameter ap_ST_fsm_state1957 = 12'd1956; +parameter ap_ST_fsm_state1958 = 12'd1957; +parameter ap_ST_fsm_state1959 = 12'd1958; +parameter ap_ST_fsm_state1960 = 12'd1959; +parameter ap_ST_fsm_state1961 = 12'd1960; +parameter ap_ST_fsm_state1962 = 12'd1961; +parameter ap_ST_fsm_state1963 = 12'd1962; +parameter ap_ST_fsm_state1964 = 12'd1963; +parameter ap_ST_fsm_state1965 = 12'd1964; +parameter ap_ST_fsm_state1966 = 12'd1965; +parameter ap_ST_fsm_state1967 = 12'd1966; +parameter ap_ST_fsm_state1968 = 12'd1967; +parameter ap_ST_fsm_state1969 = 12'd1968; +parameter ap_ST_fsm_state1970 = 12'd1969; +parameter ap_ST_fsm_state1971 = 12'd1970; +parameter ap_ST_fsm_state1972 = 12'd1971; +parameter ap_ST_fsm_state1973 = 12'd1972; +parameter ap_ST_fsm_state1974 = 12'd1973; +parameter ap_ST_fsm_state1975 = 12'd1974; +parameter ap_ST_fsm_state1976 = 12'd1975; +parameter ap_ST_fsm_state1977 = 12'd1976; +parameter ap_ST_fsm_state1978 = 12'd1977; +parameter ap_ST_fsm_state1979 = 12'd1978; +parameter ap_ST_fsm_state1980 = 12'd1979; +parameter ap_ST_fsm_state1981 = 12'd1980; +parameter ap_ST_fsm_state1982 = 12'd1981; +parameter ap_ST_fsm_state1983 = 12'd1982; +parameter ap_ST_fsm_state1984 = 12'd1983; +parameter ap_ST_fsm_state1985 = 12'd1984; +parameter ap_ST_fsm_state1986 = 12'd1985; +parameter ap_ST_fsm_state1987 = 12'd1986; +parameter ap_ST_fsm_state1988 = 12'd1987; +parameter ap_ST_fsm_state1989 = 12'd1988; +parameter ap_ST_fsm_state1990 = 12'd1989; +parameter ap_ST_fsm_state1991 = 12'd1990; +parameter ap_ST_fsm_state1992 = 12'd1991; +parameter ap_ST_fsm_state1993 = 12'd1992; +parameter ap_ST_fsm_state1994 = 12'd1993; +parameter ap_ST_fsm_state1995 = 12'd1994; +parameter ap_ST_fsm_state1996 = 12'd1995; +parameter ap_ST_fsm_state1997 = 12'd1996; +parameter ap_ST_fsm_state1998 = 12'd1997; +parameter ap_ST_fsm_state1999 = 12'd1998; +parameter ap_ST_fsm_state2000 = 12'd1999; +parameter ap_ST_fsm_state2001 = 12'd2000; +parameter ap_ST_fsm_state2002 = 12'd2001; +parameter ap_ST_fsm_state2003 = 12'd2002; +parameter ap_ST_fsm_state2004 = 12'd2003; +parameter ap_ST_fsm_state2005 = 12'd2004; +parameter ap_ST_fsm_state2006 = 12'd2005; +parameter ap_ST_fsm_state2007 = 12'd2006; +parameter ap_ST_fsm_state2008 = 12'd2007; +parameter ap_ST_fsm_state2009 = 12'd2008; +parameter ap_ST_fsm_state2010 = 12'd2009; +parameter ap_ST_fsm_state2011 = 12'd2010; +parameter ap_ST_fsm_state2012 = 12'd2011; +parameter ap_ST_fsm_state2013 = 12'd2012; +parameter ap_ST_fsm_state2014 = 12'd2013; +parameter ap_ST_fsm_state2015 = 12'd2014; +parameter ap_ST_fsm_state2016 = 12'd2015; +parameter ap_ST_fsm_state2017 = 12'd2016; +parameter ap_ST_fsm_state2018 = 12'd2017; +parameter ap_ST_fsm_state2019 = 12'd2018; +parameter ap_ST_fsm_state2020 = 12'd2019; +parameter ap_ST_fsm_state2021 = 12'd2020; +parameter ap_ST_fsm_state2022 = 12'd2021; +parameter ap_ST_fsm_state2023 = 12'd2022; +parameter ap_ST_fsm_state2024 = 12'd2023; +parameter ap_ST_fsm_state2025 = 12'd2024; +parameter ap_ST_fsm_state2026 = 12'd2025; +parameter ap_ST_fsm_state2027 = 12'd2026; +parameter ap_ST_fsm_state2028 = 12'd2027; +parameter ap_ST_fsm_state2029 = 12'd2028; +parameter ap_ST_fsm_state2030 = 12'd2029; +parameter ap_ST_fsm_state2031 = 12'd2030; +parameter ap_ST_fsm_state2032 = 12'd2031; +parameter ap_ST_fsm_state2033 = 12'd2032; +parameter ap_ST_fsm_state2034 = 12'd2033; +parameter ap_ST_fsm_state2035 = 12'd2034; +parameter ap_ST_fsm_state2036 = 12'd2035; +parameter ap_ST_fsm_state2037 = 12'd2036; +parameter ap_ST_fsm_state2038 = 12'd2037; +parameter ap_ST_fsm_state2039 = 12'd2038; +parameter ap_ST_fsm_state2040 = 12'd2039; +parameter ap_ST_fsm_state2041 = 12'd2040; +parameter ap_ST_fsm_state2042 = 12'd2041; +parameter ap_ST_fsm_state2043 = 12'd2042; +parameter ap_ST_fsm_state2044 = 12'd2043; +parameter ap_ST_fsm_state2045 = 12'd2044; +parameter ap_ST_fsm_state2046 = 12'd2045; +parameter ap_ST_fsm_state2047 = 12'd2046; +parameter ap_ST_fsm_state2048 = 12'd2047; +parameter ap_ST_fsm_state2049 = 12'd2048; +parameter ap_ST_fsm_state2050 = 12'd2049; +parameter ap_ST_fsm_state2051 = 12'd2050; +parameter ap_ST_fsm_state2052 = 12'd2051; +parameter ap_ST_fsm_state2053 = 12'd2052; +parameter ap_ST_fsm_state2054 = 12'd2053; +parameter ap_ST_fsm_state2055 = 12'd2054; +parameter ap_ST_fsm_state2056 = 12'd2055; +parameter ap_ST_fsm_state2057 = 12'd2056; +parameter ap_ST_fsm_state2058 = 12'd2057; +parameter ap_ST_fsm_state2059 = 12'd2058; +parameter ap_ST_fsm_state2060 = 12'd2059; +parameter ap_ST_fsm_state2061 = 12'd2060; +parameter ap_ST_fsm_state2062 = 12'd2061; +parameter ap_ST_fsm_state2063 = 12'd2062; +parameter ap_ST_fsm_state2064 = 12'd2063; +parameter ap_ST_fsm_state2065 = 12'd2064; +parameter ap_ST_fsm_state2066 = 12'd2065; +parameter ap_ST_fsm_state2067 = 12'd2066; +parameter ap_ST_fsm_state2068 = 12'd2067; +parameter ap_ST_fsm_state2069 = 12'd2068; +parameter ap_ST_fsm_state2070 = 12'd2069; +parameter ap_ST_fsm_state2071 = 12'd2070; +parameter ap_ST_fsm_state2072 = 12'd2071; +parameter ap_ST_fsm_state2073 = 12'd2072; +parameter ap_ST_fsm_state2074 = 12'd2073; +parameter ap_ST_fsm_state2075 = 12'd2074; +parameter ap_ST_fsm_state2076 = 12'd2075; +parameter ap_ST_fsm_state2077 = 12'd2076; +parameter ap_ST_fsm_state2078 = 12'd2077; +parameter ap_ST_fsm_state2079 = 12'd2078; +parameter ap_ST_fsm_state2080 = 12'd2079; +parameter ap_ST_fsm_state2081 = 12'd2080; +parameter ap_ST_fsm_state2082 = 12'd2081; +parameter ap_ST_fsm_state2083 = 12'd2082; +parameter ap_ST_fsm_state2084 = 12'd2083; +parameter ap_ST_fsm_state2085 = 12'd2084; +parameter ap_ST_fsm_state2086 = 12'd2085; +parameter ap_ST_fsm_state2087 = 12'd2086; +parameter ap_ST_fsm_state2088 = 12'd2087; +parameter ap_ST_fsm_state2089 = 12'd2088; +parameter ap_ST_fsm_state2090 = 12'd2089; +parameter ap_ST_fsm_state2091 = 12'd2090; +parameter ap_ST_fsm_state2092 = 12'd2091; +parameter ap_ST_fsm_state2093 = 12'd2092; +parameter ap_ST_fsm_state2094 = 12'd2093; +parameter ap_ST_fsm_state2095 = 12'd2094; +parameter ap_ST_fsm_state2096 = 12'd2095; +parameter ap_ST_fsm_state2097 = 12'd2096; +parameter ap_ST_fsm_state2098 = 12'd2097; +parameter ap_ST_fsm_state2099 = 12'd2098; +parameter ap_ST_fsm_state2100 = 12'd2099; +parameter ap_ST_fsm_state2101 = 12'd2100; +parameter ap_ST_fsm_state2102 = 12'd2101; +parameter ap_ST_fsm_state2103 = 12'd2102; +parameter ap_ST_fsm_state2104 = 12'd2103; +parameter ap_ST_fsm_state2105 = 12'd2104; +parameter ap_ST_fsm_state2106 = 12'd2105; +parameter ap_ST_fsm_state2107 = 12'd2106; +parameter ap_ST_fsm_state2108 = 12'd2107; +parameter ap_ST_fsm_state2109 = 12'd2108; +parameter ap_ST_fsm_state2110 = 12'd2109; +parameter ap_ST_fsm_state2111 = 12'd2110; +parameter ap_ST_fsm_state2112 = 12'd2111; +parameter ap_ST_fsm_state2113 = 12'd2112; +parameter ap_ST_fsm_state2114 = 12'd2113; +parameter ap_ST_fsm_state2115 = 12'd2114; +parameter ap_ST_fsm_state2116 = 12'd2115; +parameter ap_ST_fsm_state2117 = 12'd2116; +parameter ap_ST_fsm_state2118 = 12'd2117; +parameter ap_ST_fsm_state2119 = 12'd2118; +parameter ap_ST_fsm_state2120 = 12'd2119; +parameter ap_ST_fsm_state2121 = 12'd2120; +parameter ap_ST_fsm_state2122 = 12'd2121; +parameter ap_ST_fsm_state2123 = 12'd2122; +parameter ap_ST_fsm_state2124 = 12'd2123; +parameter ap_ST_fsm_state2125 = 12'd2124; +parameter ap_ST_fsm_state2126 = 12'd2125; +parameter ap_ST_fsm_state2127 = 12'd2126; +parameter ap_ST_fsm_state2128 = 12'd2127; +parameter ap_ST_fsm_state2129 = 12'd2128; +parameter ap_ST_fsm_state2130 = 12'd2129; +parameter ap_ST_fsm_state2131 = 12'd2130; +parameter ap_ST_fsm_state2132 = 12'd2131; +parameter ap_ST_fsm_state2133 = 12'd2132; +parameter ap_ST_fsm_state2134 = 12'd2133; +parameter ap_ST_fsm_state2135 = 12'd2134; +parameter ap_ST_fsm_state2136 = 12'd2135; +parameter ap_ST_fsm_state2137 = 12'd2136; +parameter ap_ST_fsm_state2138 = 12'd2137; +parameter ap_ST_fsm_state2139 = 12'd2138; +parameter ap_ST_fsm_state2140 = 12'd2139; +parameter ap_ST_fsm_state2141 = 12'd2140; +parameter ap_ST_fsm_state2142 = 12'd2141; +parameter ap_ST_fsm_state2143 = 12'd2142; +parameter ap_ST_fsm_state2144 = 12'd2143; +parameter ap_ST_fsm_state2145 = 12'd2144; +parameter ap_ST_fsm_state2146 = 12'd2145; +parameter ap_ST_fsm_state2147 = 12'd2146; +parameter ap_ST_fsm_state2148 = 12'd2147; +parameter ap_ST_fsm_state2149 = 12'd2148; +parameter ap_ST_fsm_state2150 = 12'd2149; +parameter ap_ST_fsm_state2151 = 12'd2150; +parameter ap_ST_fsm_state2152 = 12'd2151; +parameter ap_ST_fsm_state2153 = 12'd2152; +parameter ap_ST_fsm_state2154 = 12'd2153; +parameter ap_ST_fsm_state2155 = 12'd2154; +parameter ap_ST_fsm_state2156 = 12'd2155; +parameter ap_ST_fsm_state2157 = 12'd2156; +parameter ap_ST_fsm_state2158 = 12'd2157; +parameter ap_ST_fsm_state2159 = 12'd2158; +parameter ap_ST_fsm_state2160 = 12'd2159; +parameter ap_ST_fsm_state2161 = 12'd2160; +parameter ap_ST_fsm_state2162 = 12'd2161; +parameter ap_ST_fsm_state2163 = 12'd2162; +parameter ap_ST_fsm_state2164 = 12'd2163; +parameter ap_ST_fsm_state2165 = 12'd2164; +parameter ap_ST_fsm_state2166 = 12'd2165; +parameter ap_ST_fsm_state2167 = 12'd2166; +parameter ap_ST_fsm_state2168 = 12'd2167; +parameter ap_ST_fsm_state2169 = 12'd2168; +parameter ap_ST_fsm_state2170 = 12'd2169; +parameter ap_ST_fsm_state2171 = 12'd2170; +parameter ap_ST_fsm_state2172 = 12'd2171; +parameter ap_ST_fsm_state2173 = 12'd2172; +parameter ap_ST_fsm_state2174 = 12'd2173; +parameter ap_ST_fsm_state2175 = 12'd2174; +parameter ap_ST_fsm_state2176 = 12'd2175; +parameter ap_ST_fsm_state2177 = 12'd2176; +parameter ap_ST_fsm_state2178 = 12'd2177; +parameter ap_ST_fsm_state2179 = 12'd2178; +parameter ap_ST_fsm_state2180 = 12'd2179; +parameter ap_ST_fsm_state2181 = 12'd2180; +parameter ap_ST_fsm_state2182 = 12'd2181; +parameter ap_ST_fsm_state2183 = 12'd2182; +parameter ap_ST_fsm_state2184 = 12'd2183; +parameter ap_ST_fsm_state2185 = 12'd2184; +parameter ap_ST_fsm_state2186 = 12'd2185; +parameter ap_ST_fsm_state2187 = 12'd2186; +parameter ap_ST_fsm_state2188 = 12'd2187; +parameter ap_ST_fsm_state2189 = 12'd2188; +parameter ap_ST_fsm_state2190 = 12'd2189; +parameter ap_ST_fsm_state2191 = 12'd2190; +parameter ap_ST_fsm_state2192 = 12'd2191; +parameter ap_ST_fsm_state2193 = 12'd2192; +parameter ap_ST_fsm_state2194 = 12'd2193; +parameter ap_ST_fsm_state2195 = 12'd2194; +parameter ap_ST_fsm_state2196 = 12'd2195; +parameter ap_ST_fsm_state2197 = 12'd2196; +parameter ap_ST_fsm_state2198 = 12'd2197; +parameter ap_ST_fsm_state2199 = 12'd2198; +parameter ap_ST_fsm_state2200 = 12'd2199; +parameter ap_ST_fsm_state2201 = 12'd2200; +parameter ap_ST_fsm_state2202 = 12'd2201; +parameter ap_ST_fsm_state2203 = 12'd2202; +parameter ap_ST_fsm_state2204 = 12'd2203; +parameter ap_ST_fsm_state2205 = 12'd2204; +parameter ap_ST_fsm_state2206 = 12'd2205; +parameter ap_ST_fsm_state2207 = 12'd2206; +parameter ap_ST_fsm_state2208 = 12'd2207; +parameter ap_ST_fsm_state2209 = 12'd2208; +parameter ap_ST_fsm_state2210 = 12'd2209; +parameter ap_ST_fsm_state2211 = 12'd2210; +parameter ap_ST_fsm_state2212 = 12'd2211; +parameter ap_ST_fsm_state2213 = 12'd2212; +parameter ap_ST_fsm_state2214 = 12'd2213; +parameter ap_ST_fsm_state2215 = 12'd2214; +parameter ap_ST_fsm_state2216 = 12'd2215; +parameter ap_ST_fsm_state2217 = 12'd2216; +parameter ap_ST_fsm_state2218 = 12'd2217; +parameter ap_ST_fsm_state2219 = 12'd2218; +parameter ap_ST_fsm_state2220 = 12'd2219; +parameter ap_ST_fsm_state2221 = 12'd2220; +parameter ap_ST_fsm_state2222 = 12'd2221; +parameter ap_ST_fsm_state2223 = 12'd2222; +parameter ap_ST_fsm_state2224 = 12'd2223; +parameter ap_ST_fsm_state2225 = 12'd2224; +parameter ap_ST_fsm_state2226 = 12'd2225; +parameter ap_ST_fsm_state2227 = 12'd2226; +parameter ap_ST_fsm_state2228 = 12'd2227; +parameter ap_ST_fsm_state2229 = 12'd2228; +parameter ap_ST_fsm_state2230 = 12'd2229; +parameter ap_ST_fsm_state2231 = 12'd2230; +parameter ap_ST_fsm_state2232 = 12'd2231; +parameter ap_ST_fsm_state2233 = 12'd2232; +parameter ap_ST_fsm_state2234 = 12'd2233; +parameter ap_ST_fsm_state2235 = 12'd2234; +parameter ap_ST_fsm_state2236 = 12'd2235; +parameter ap_ST_fsm_state2237 = 12'd2236; +parameter ap_ST_fsm_state2238 = 12'd2237; +parameter ap_ST_fsm_state2239 = 12'd2238; +parameter ap_ST_fsm_state2240 = 12'd2239; +parameter ap_ST_fsm_state2241 = 12'd2240; +parameter ap_ST_fsm_state2242 = 12'd2241; +parameter ap_ST_fsm_state2243 = 12'd2242; +parameter ap_ST_fsm_state2244 = 12'd2243; +parameter ap_ST_fsm_state2245 = 12'd2244; +parameter ap_ST_fsm_state2246 = 12'd2245; +parameter ap_ST_fsm_state2247 = 12'd2246; +parameter ap_ST_fsm_state2248 = 12'd2247; +parameter ap_ST_fsm_state2249 = 12'd2248; +parameter ap_ST_fsm_state2250 = 12'd2249; +parameter ap_ST_fsm_state2251 = 12'd2250; +parameter ap_ST_fsm_state2252 = 12'd2251; +parameter ap_ST_fsm_state2253 = 12'd2252; +parameter ap_ST_fsm_state2254 = 12'd2253; +parameter ap_ST_fsm_state2255 = 12'd2254; +parameter ap_ST_fsm_state2256 = 12'd2255; +parameter ap_ST_fsm_state2257 = 12'd2256; +parameter ap_ST_fsm_state2258 = 12'd2257; +parameter ap_ST_fsm_state2259 = 12'd2258; +parameter ap_ST_fsm_state2260 = 12'd2259; +parameter ap_ST_fsm_state2261 = 12'd2260; +parameter ap_ST_fsm_state2262 = 12'd2261; +parameter ap_ST_fsm_state2263 = 12'd2262; +parameter ap_ST_fsm_state2264 = 12'd2263; +parameter ap_ST_fsm_state2265 = 12'd2264; +parameter ap_ST_fsm_state2266 = 12'd2265; +parameter ap_ST_fsm_state2267 = 12'd2266; +parameter ap_ST_fsm_state2268 = 12'd2267; +parameter ap_ST_fsm_state2269 = 12'd2268; +parameter ap_ST_fsm_state2270 = 12'd2269; +parameter ap_ST_fsm_state2271 = 12'd2270; +parameter ap_ST_fsm_state2272 = 12'd2271; +parameter ap_ST_fsm_state2273 = 12'd2272; +parameter ap_ST_fsm_state2274 = 12'd2273; +parameter ap_ST_fsm_state2275 = 12'd2274; +parameter ap_ST_fsm_state2276 = 12'd2275; +parameter ap_ST_fsm_state2277 = 12'd2276; +parameter ap_ST_fsm_state2278 = 12'd2277; +parameter ap_ST_fsm_state2279 = 12'd2278; +parameter ap_ST_fsm_state2280 = 12'd2279; +parameter ap_ST_fsm_state2281 = 12'd2280; +parameter ap_ST_fsm_state2282 = 12'd2281; +parameter ap_ST_fsm_state2283 = 12'd2282; +parameter ap_ST_fsm_state2284 = 12'd2283; +parameter ap_ST_fsm_state2285 = 12'd2284; +parameter ap_ST_fsm_state2286 = 12'd2285; +parameter ap_ST_fsm_state2287 = 12'd2286; +parameter ap_ST_fsm_state2288 = 12'd2287; +parameter ap_ST_fsm_state2289 = 12'd2288; +parameter ap_ST_fsm_state2290 = 12'd2289; +parameter ap_ST_fsm_state2291 = 12'd2290; +parameter ap_ST_fsm_state2292 = 12'd2291; +parameter ap_ST_fsm_state2293 = 12'd2292; +parameter ap_ST_fsm_state2294 = 12'd2293; +parameter ap_ST_fsm_state2295 = 12'd2294; +parameter ap_ST_fsm_state2296 = 12'd2295; +parameter ap_ST_fsm_state2297 = 12'd2296; +parameter ap_ST_fsm_state2298 = 12'd2297; +parameter ap_ST_fsm_state2299 = 12'd2298; +parameter ap_ST_fsm_state2300 = 12'd2299; +parameter ap_ST_fsm_state2301 = 12'd2300; +parameter ap_ST_fsm_state2302 = 12'd2301; +parameter ap_ST_fsm_state2303 = 12'd2302; +parameter ap_ST_fsm_state2304 = 12'd2303; +parameter ap_ST_fsm_state2305 = 12'd2304; +parameter ap_ST_fsm_state2306 = 12'd2305; +parameter ap_ST_fsm_state2307 = 12'd2306; +parameter ap_ST_fsm_state2308 = 12'd2307; +parameter ap_ST_fsm_state2309 = 12'd2308; +parameter ap_ST_fsm_state2310 = 12'd2309; +parameter ap_ST_fsm_state2311 = 12'd2310; +parameter ap_ST_fsm_state2312 = 12'd2311; +parameter ap_ST_fsm_state2313 = 12'd2312; +parameter ap_ST_fsm_state2314 = 12'd2313; +parameter ap_ST_fsm_state2315 = 12'd2314; +parameter ap_ST_fsm_state2316 = 12'd2315; +parameter ap_ST_fsm_state2317 = 12'd2316; +parameter ap_ST_fsm_state2318 = 12'd2317; +parameter ap_ST_fsm_state2319 = 12'd2318; +parameter ap_ST_fsm_state2320 = 12'd2319; +parameter ap_ST_fsm_state2321 = 12'd2320; +parameter ap_ST_fsm_state2322 = 12'd2321; +parameter ap_ST_fsm_state2323 = 12'd2322; +parameter ap_ST_fsm_state2324 = 12'd2323; +parameter ap_ST_fsm_state2325 = 12'd2324; +parameter ap_ST_fsm_state2326 = 12'd2325; +parameter ap_ST_fsm_state2327 = 12'd2326; +parameter ap_ST_fsm_state2328 = 12'd2327; +parameter ap_ST_fsm_state2329 = 12'd2328; +parameter ap_ST_fsm_state2330 = 12'd2329; +parameter ap_ST_fsm_state2331 = 12'd2330; +parameter ap_ST_fsm_state2332 = 12'd2331; +parameter ap_ST_fsm_state2333 = 12'd2332; +parameter ap_ST_fsm_state2334 = 12'd2333; +parameter ap_ST_fsm_state2335 = 12'd2334; +parameter ap_ST_fsm_state2336 = 12'd2335; +parameter ap_ST_fsm_state2337 = 12'd2336; +parameter ap_ST_fsm_state2338 = 12'd2337; +parameter ap_ST_fsm_state2339 = 12'd2338; +parameter ap_ST_fsm_state2340 = 12'd2339; +parameter ap_ST_fsm_state2341 = 12'd2340; +parameter ap_ST_fsm_state2342 = 12'd2341; +parameter ap_ST_fsm_state2343 = 12'd2342; +parameter ap_ST_fsm_state2344 = 12'd2343; +parameter ap_ST_fsm_state2345 = 12'd2344; +parameter ap_ST_fsm_state2346 = 12'd2345; +parameter ap_ST_fsm_state2347 = 12'd2346; +parameter ap_ST_fsm_state2348 = 12'd2347; +parameter ap_ST_fsm_state2349 = 12'd2348; +parameter ap_ST_fsm_state2350 = 12'd2349; +parameter ap_ST_fsm_state2351 = 12'd2350; +parameter ap_ST_fsm_state2352 = 12'd2351; +parameter ap_ST_fsm_state2353 = 12'd2352; +parameter ap_ST_fsm_state2354 = 12'd2353; +parameter ap_ST_fsm_state2355 = 12'd2354; +parameter ap_ST_fsm_state2356 = 12'd2355; +parameter ap_ST_fsm_state2357 = 12'd2356; +parameter ap_ST_fsm_state2358 = 12'd2357; +parameter ap_ST_fsm_state2359 = 12'd2358; +parameter ap_ST_fsm_state2360 = 12'd2359; +parameter ap_ST_fsm_state2361 = 12'd2360; +parameter ap_ST_fsm_state2362 = 12'd2361; +parameter ap_ST_fsm_state2363 = 12'd2362; +parameter ap_ST_fsm_state2364 = 12'd2363; +parameter ap_ST_fsm_state2365 = 12'd2364; +parameter ap_ST_fsm_state2366 = 12'd2365; +parameter ap_ST_fsm_state2367 = 12'd2366; +parameter ap_ST_fsm_state2368 = 12'd2367; +parameter ap_ST_fsm_state2369 = 12'd2368; +parameter ap_ST_fsm_state2370 = 12'd2369; +parameter ap_ST_fsm_state2371 = 12'd2370; +parameter ap_ST_fsm_state2372 = 12'd2371; +parameter ap_ST_fsm_state2373 = 12'd2372; +parameter ap_ST_fsm_state2374 = 12'd2373; +parameter ap_ST_fsm_state2375 = 12'd2374; +parameter ap_ST_fsm_state2376 = 12'd2375; +parameter ap_ST_fsm_state2377 = 12'd2376; +parameter ap_ST_fsm_state2378 = 12'd2377; +parameter ap_ST_fsm_state2379 = 12'd2378; +parameter ap_ST_fsm_state2380 = 12'd2379; +parameter ap_ST_fsm_state2381 = 12'd2380; +parameter ap_ST_fsm_state2382 = 12'd2381; +parameter ap_ST_fsm_state2383 = 12'd2382; +parameter ap_ST_fsm_state2384 = 12'd2383; +parameter ap_ST_fsm_state2385 = 12'd2384; +parameter ap_ST_fsm_state2386 = 12'd2385; +parameter ap_ST_fsm_state2387 = 12'd2386; +parameter ap_ST_fsm_state2388 = 12'd2387; +parameter ap_ST_fsm_state2389 = 12'd2388; +parameter ap_ST_fsm_state2390 = 12'd2389; +parameter ap_ST_fsm_state2391 = 12'd2390; +parameter ap_ST_fsm_state2392 = 12'd2391; +parameter ap_ST_fsm_state2393 = 12'd2392; +parameter ap_ST_fsm_state2394 = 12'd2393; +parameter ap_ST_fsm_state2395 = 12'd2394; +parameter ap_ST_fsm_state2396 = 12'd2395; +parameter ap_ST_fsm_state2397 = 12'd2396; +parameter ap_ST_fsm_state2398 = 12'd2397; +parameter ap_ST_fsm_state2399 = 12'd2398; +parameter ap_ST_fsm_state2400 = 12'd2399; +parameter ap_ST_fsm_state2401 = 12'd2400; +parameter ap_ST_fsm_state2402 = 12'd2401; +parameter ap_ST_fsm_state2403 = 12'd2402; +parameter ap_ST_fsm_state2404 = 12'd2403; +parameter ap_ST_fsm_state2405 = 12'd2404; +parameter ap_ST_fsm_state2406 = 12'd2405; +parameter ap_ST_fsm_state2407 = 12'd2406; +parameter ap_ST_fsm_state2408 = 12'd2407; +parameter ap_ST_fsm_state2409 = 12'd2408; +parameter ap_ST_fsm_state2410 = 12'd2409; +parameter ap_ST_fsm_state2411 = 12'd2410; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +output [6:0] data_V_address0; +output data_V_ce0; +input [63:0] data_V_q0; +output [4:0] res_0_V_address0; +output res_0_V_ce0; +output res_0_V_we0; +output [7:0] res_0_V_d0; +output [4:0] res_1_V_address0; +output res_1_V_ce0; +output res_1_V_we0; +output [7:0] res_1_V_d0; +output [4:0] res_2_V_address0; +output res_2_V_ce0; +output res_2_V_we0; +output [7:0] res_2_V_d0; +output [4:0] res_3_V_address0; +output res_3_V_ce0; +output res_3_V_we0; +output [7:0] res_3_V_d0; +output [4:0] res_4_V_address0; +output res_4_V_ce0; +output res_4_V_we0; +output [7:0] res_4_V_d0; +output [4:0] res_5_V_address0; +output res_5_V_ce0; +output res_5_V_we0; +output [7:0] res_5_V_d0; +output [4:0] res_6_V_address0; +output res_6_V_ce0; +output res_6_V_we0; +output [7:0] res_6_V_d0; +output [4:0] res_7_V_address0; +output res_7_V_ce0; +output res_7_V_we0; +output [7:0] res_7_V_d0; +output [4:0] res_8_V_address0; +output res_8_V_ce0; +output res_8_V_we0; +output [7:0] res_8_V_d0; +output [4:0] res_9_V_address0; +output res_9_V_ce0; +output res_9_V_we0; +output [7:0] res_9_V_d0; +output [4:0] res_10_V_address0; +output res_10_V_ce0; +output res_10_V_we0; +output [7:0] res_10_V_d0; +output [4:0] res_11_V_address0; +output res_11_V_ce0; +output res_11_V_we0; +output [7:0] res_11_V_d0; +output [4:0] res_12_V_address0; +output res_12_V_ce0; +output res_12_V_we0; +output [7:0] res_12_V_d0; +output [4:0] res_13_V_address0; +output res_13_V_ce0; +output res_13_V_we0; +output [7:0] res_13_V_d0; +output [4:0] res_14_V_address0; +output res_14_V_ce0; +output res_14_V_we0; +output [7:0] res_14_V_d0; +output [4:0] res_15_V_address0; +output res_15_V_ce0; +output res_15_V_we0; +output [7:0] res_15_V_d0; +output [4:0] res_16_V_address0; +output res_16_V_ce0; +output res_16_V_we0; +output [7:0] res_16_V_d0; +output [4:0] res_17_V_address0; +output res_17_V_ce0; +output res_17_V_we0; +output [7:0] res_17_V_d0; +output [4:0] res_18_V_address0; +output res_18_V_ce0; +output res_18_V_we0; +output [7:0] res_18_V_d0; +output [4:0] res_19_V_address0; +output res_19_V_ce0; +output res_19_V_we0; +output [7:0] res_19_V_d0; +output [4:0] res_20_V_address0; +output res_20_V_ce0; +output res_20_V_we0; +output [7:0] res_20_V_d0; +output [4:0] res_21_V_address0; +output res_21_V_ce0; +output res_21_V_we0; +output [7:0] res_21_V_d0; +output [4:0] res_22_V_address0; +output res_22_V_ce0; +output res_22_V_we0; +output [7:0] res_22_V_d0; +output [4:0] res_23_V_address0; +output res_23_V_ce0; +output res_23_V_we0; +output [7:0] res_23_V_d0; +output [4:0] res_24_V_address0; +output res_24_V_ce0; +output res_24_V_we0; +output [7:0] res_24_V_d0; +output [4:0] res_25_V_address0; +output res_25_V_ce0; +output res_25_V_we0; +output [7:0] res_25_V_d0; +output [4:0] res_26_V_address0; +output res_26_V_ce0; +output res_26_V_we0; +output [7:0] res_26_V_d0; +output [4:0] res_27_V_address0; +output res_27_V_ce0; +output res_27_V_we0; +output [7:0] res_27_V_d0; +output [4:0] res_28_V_address0; +output res_28_V_ce0; +output res_28_V_we0; +output [7:0] res_28_V_d0; +output [4:0] res_29_V_address0; +output res_29_V_ce0; +output res_29_V_we0; +output [7:0] res_29_V_d0; +output [4:0] res_30_V_address0; +output res_30_V_ce0; +output res_30_V_we0; +output [7:0] res_30_V_d0; +output [4:0] res_31_V_address0; +output res_31_V_ce0; +output res_31_V_we0; +output [7:0] res_31_V_d0; +output [4:0] res_32_V_address0; +output res_32_V_ce0; +output res_32_V_we0; +output [7:0] res_32_V_d0; +output [4:0] res_33_V_address0; +output res_33_V_ce0; +output res_33_V_we0; +output [7:0] res_33_V_d0; +output [4:0] res_34_V_address0; +output res_34_V_ce0; +output res_34_V_we0; +output [7:0] res_34_V_d0; +output [4:0] res_35_V_address0; +output res_35_V_ce0; +output res_35_V_we0; +output [7:0] res_35_V_d0; +output [4:0] res_36_V_address0; +output res_36_V_ce0; +output res_36_V_we0; +output [7:0] res_36_V_d0; +output [4:0] res_37_V_address0; +output res_37_V_ce0; +output res_37_V_we0; +output [7:0] res_37_V_d0; +output [4:0] res_38_V_address0; +output res_38_V_ce0; +output res_38_V_we0; +output [7:0] res_38_V_d0; +output [4:0] res_39_V_address0; +output res_39_V_ce0; +output res_39_V_we0; +output [7:0] res_39_V_d0; +output [4:0] res_40_V_address0; +output res_40_V_ce0; +output res_40_V_we0; +output [7:0] res_40_V_d0; +output [4:0] res_41_V_address0; +output res_41_V_ce0; +output res_41_V_we0; +output [7:0] res_41_V_d0; +output [4:0] res_42_V_address0; +output res_42_V_ce0; +output res_42_V_we0; +output [7:0] res_42_V_d0; +output [4:0] res_43_V_address0; +output res_43_V_ce0; +output res_43_V_we0; +output [7:0] res_43_V_d0; +output [4:0] res_44_V_address0; +output res_44_V_ce0; +output res_44_V_we0; +output [7:0] res_44_V_d0; +output [4:0] res_45_V_address0; +output res_45_V_ce0; +output res_45_V_we0; +output [7:0] res_45_V_d0; +output [4:0] res_46_V_address0; +output res_46_V_ce0; +output res_46_V_we0; +output [7:0] res_46_V_d0; +output [4:0] res_47_V_address0; +output res_47_V_ce0; +output res_47_V_we0; +output [7:0] res_47_V_d0; +output [4:0] res_48_V_address0; +output res_48_V_ce0; +output res_48_V_we0; +output [7:0] res_48_V_d0; +output [4:0] res_49_V_address0; +output res_49_V_ce0; +output res_49_V_we0; +output [7:0] res_49_V_d0; +output [4:0] res_50_V_address0; +output res_50_V_ce0; +output res_50_V_we0; +output [7:0] res_50_V_d0; +output [4:0] res_51_V_address0; +output res_51_V_ce0; +output res_51_V_we0; +output [7:0] res_51_V_d0; +output [4:0] res_52_V_address0; +output res_52_V_ce0; +output res_52_V_we0; +output [7:0] res_52_V_d0; +output [4:0] res_53_V_address0; +output res_53_V_ce0; +output res_53_V_we0; +output [7:0] res_53_V_d0; +output [4:0] res_54_V_address0; +output res_54_V_ce0; +output res_54_V_we0; +output [7:0] res_54_V_d0; +output [4:0] res_55_V_address0; +output res_55_V_ce0; +output res_55_V_we0; +output [7:0] res_55_V_d0; +output [4:0] res_56_V_address0; +output res_56_V_ce0; +output res_56_V_we0; +output [7:0] res_56_V_d0; +output [4:0] res_57_V_address0; +output res_57_V_ce0; +output res_57_V_we0; +output [7:0] res_57_V_d0; +output [4:0] res_58_V_address0; +output res_58_V_ce0; +output res_58_V_we0; +output [7:0] res_58_V_d0; +output [4:0] res_59_V_address0; +output res_59_V_ce0; +output res_59_V_we0; +output [7:0] res_59_V_d0; +output [4:0] res_60_V_address0; +output res_60_V_ce0; +output res_60_V_we0; +output [7:0] res_60_V_d0; +output [4:0] res_61_V_address0; +output res_61_V_ce0; +output res_61_V_we0; +output [7:0] res_61_V_d0; +output [4:0] res_62_V_address0; +output res_62_V_ce0; +output res_62_V_we0; +output [7:0] res_62_V_d0; +output [4:0] res_63_V_address0; +output res_63_V_ce0; +output res_63_V_we0; +output [7:0] res_63_V_d0; +output [4:0] res_64_V_address0; +output res_64_V_ce0; +output res_64_V_we0; +output [7:0] res_64_V_d0; +output [4:0] res_65_V_address0; +output res_65_V_ce0; +output res_65_V_we0; +output [7:0] res_65_V_d0; +output [4:0] res_66_V_address0; +output res_66_V_ce0; +output res_66_V_we0; +output [7:0] res_66_V_d0; +output [4:0] res_67_V_address0; +output res_67_V_ce0; +output res_67_V_we0; +output [7:0] res_67_V_d0; +output [4:0] res_68_V_address0; +output res_68_V_ce0; +output res_68_V_we0; +output [7:0] res_68_V_d0; +output [4:0] res_69_V_address0; +output res_69_V_ce0; +output res_69_V_we0; +output [7:0] res_69_V_d0; +output [4:0] res_70_V_address0; +output res_70_V_ce0; +output res_70_V_we0; +output [7:0] res_70_V_d0; +output [4:0] res_71_V_address0; +output res_71_V_ce0; +output res_71_V_we0; +output [7:0] res_71_V_d0; +output [4:0] res_72_V_address0; +output res_72_V_ce0; +output res_72_V_we0; +output [7:0] res_72_V_d0; +output [4:0] res_73_V_address0; +output res_73_V_ce0; +output res_73_V_we0; +output [7:0] res_73_V_d0; +output [4:0] res_74_V_address0; +output res_74_V_ce0; +output res_74_V_we0; +output [7:0] res_74_V_d0; +output [4:0] res_75_V_address0; +output res_75_V_ce0; +output res_75_V_we0; +output [7:0] res_75_V_d0; +output [4:0] res_76_V_address0; +output res_76_V_ce0; +output res_76_V_we0; +output [7:0] res_76_V_d0; +output [4:0] res_77_V_address0; +output res_77_V_ce0; +output res_77_V_we0; +output [7:0] res_77_V_d0; +output [4:0] res_78_V_address0; +output res_78_V_ce0; +output res_78_V_we0; +output [7:0] res_78_V_d0; +output [4:0] res_79_V_address0; +output res_79_V_ce0; +output res_79_V_we0; +output [7:0] res_79_V_d0; +output [4:0] res_80_V_address0; +output res_80_V_ce0; +output res_80_V_we0; +output [7:0] res_80_V_d0; +output [4:0] res_81_V_address0; +output res_81_V_ce0; +output res_81_V_we0; +output [7:0] res_81_V_d0; +output [4:0] res_82_V_address0; +output res_82_V_ce0; +output res_82_V_we0; +output [7:0] res_82_V_d0; +output [4:0] res_83_V_address0; +output res_83_V_ce0; +output res_83_V_we0; +output [7:0] res_83_V_d0; +output [4:0] res_84_V_address0; +output res_84_V_ce0; +output res_84_V_we0; +output [7:0] res_84_V_d0; +output [4:0] res_85_V_address0; +output res_85_V_ce0; +output res_85_V_we0; +output [7:0] res_85_V_d0; +output [4:0] res_86_V_address0; +output res_86_V_ce0; +output res_86_V_we0; +output [7:0] res_86_V_d0; +output [4:0] res_87_V_address0; +output res_87_V_ce0; +output res_87_V_we0; +output [7:0] res_87_V_d0; +output [4:0] res_88_V_address0; +output res_88_V_ce0; +output res_88_V_we0; +output [7:0] res_88_V_d0; +output [4:0] res_89_V_address0; +output res_89_V_ce0; +output res_89_V_we0; +output [7:0] res_89_V_d0; +output [4:0] res_90_V_address0; +output res_90_V_ce0; +output res_90_V_we0; +output [7:0] res_90_V_d0; +output [4:0] res_91_V_address0; +output res_91_V_ce0; +output res_91_V_we0; +output [7:0] res_91_V_d0; +output [4:0] res_92_V_address0; +output res_92_V_ce0; +output res_92_V_we0; +output [7:0] res_92_V_d0; +output [4:0] res_93_V_address0; +output res_93_V_ce0; +output res_93_V_we0; +output [7:0] res_93_V_d0; +output [4:0] res_94_V_address0; +output res_94_V_ce0; +output res_94_V_we0; +output [7:0] res_94_V_d0; +output [4:0] res_95_V_address0; +output res_95_V_ce0; +output res_95_V_we0; +output [7:0] res_95_V_d0; +output [4:0] res_96_V_address0; +output res_96_V_ce0; +output res_96_V_we0; +output [7:0] res_96_V_d0; +output [4:0] res_97_V_address0; +output res_97_V_ce0; +output res_97_V_we0; +output [7:0] res_97_V_d0; +output [4:0] res_98_V_address0; +output res_98_V_ce0; +output res_98_V_we0; +output [7:0] res_98_V_d0; +output [4:0] res_99_V_address0; +output res_99_V_ce0; +output res_99_V_we0; +output [7:0] res_99_V_d0; +output [4:0] res_100_V_address0; +output res_100_V_ce0; +output res_100_V_we0; +output [7:0] res_100_V_d0; +output [4:0] res_101_V_address0; +output res_101_V_ce0; +output res_101_V_we0; +output [7:0] res_101_V_d0; +output [4:0] res_102_V_address0; +output res_102_V_ce0; +output res_102_V_we0; +output [7:0] res_102_V_d0; +output [4:0] res_103_V_address0; +output res_103_V_ce0; +output res_103_V_we0; +output [7:0] res_103_V_d0; +output [4:0] res_104_V_address0; +output res_104_V_ce0; +output res_104_V_we0; +output [7:0] res_104_V_d0; +output [4:0] res_105_V_address0; +output res_105_V_ce0; +output res_105_V_we0; +output [7:0] res_105_V_d0; +output [4:0] res_106_V_address0; +output res_106_V_ce0; +output res_106_V_we0; +output [7:0] res_106_V_d0; +output [4:0] res_107_V_address0; +output res_107_V_ce0; +output res_107_V_we0; +output [7:0] res_107_V_d0; +output [4:0] res_108_V_address0; +output res_108_V_ce0; +output res_108_V_we0; +output [7:0] res_108_V_d0; +output [4:0] res_109_V_address0; +output res_109_V_ce0; +output res_109_V_we0; +output [7:0] res_109_V_d0; +output [4:0] res_110_V_address0; +output res_110_V_ce0; +output res_110_V_we0; +output [7:0] res_110_V_d0; +output [4:0] res_111_V_address0; +output res_111_V_ce0; +output res_111_V_we0; +output [7:0] res_111_V_d0; +output [4:0] res_112_V_address0; +output res_112_V_ce0; +output res_112_V_we0; +output [7:0] res_112_V_d0; +output [4:0] res_113_V_address0; +output res_113_V_ce0; +output res_113_V_we0; +output [7:0] res_113_V_d0; +output [4:0] res_114_V_address0; +output res_114_V_ce0; +output res_114_V_we0; +output [7:0] res_114_V_d0; +output [4:0] res_115_V_address0; +output res_115_V_ce0; +output res_115_V_we0; +output [7:0] res_115_V_d0; +output [4:0] res_116_V_address0; +output res_116_V_ce0; +output res_116_V_we0; +output [7:0] res_116_V_d0; +output [4:0] res_117_V_address0; +output res_117_V_ce0; +output res_117_V_we0; +output [7:0] res_117_V_d0; +output [4:0] res_118_V_address0; +output res_118_V_ce0; +output res_118_V_we0; +output [7:0] res_118_V_d0; +output [4:0] res_119_V_address0; +output res_119_V_ce0; +output res_119_V_we0; +output [7:0] res_119_V_d0; +output [4:0] res_120_V_address0; +output res_120_V_ce0; +output res_120_V_we0; +output [7:0] res_120_V_d0; +output [4:0] res_121_V_address0; +output res_121_V_ce0; +output res_121_V_we0; +output [7:0] res_121_V_d0; +output [4:0] res_122_V_address0; +output res_122_V_ce0; +output res_122_V_we0; +output [7:0] res_122_V_d0; +output [4:0] res_123_V_address0; +output res_123_V_ce0; +output res_123_V_we0; +output [7:0] res_123_V_d0; +output [4:0] res_124_V_address0; +output res_124_V_ce0; +output res_124_V_we0; +output [7:0] res_124_V_d0; +output [4:0] res_125_V_address0; +output res_125_V_ce0; +output res_125_V_we0; +output [7:0] res_125_V_d0; +output [4:0] res_126_V_address0; +output res_126_V_ce0; +output res_126_V_we0; +output [7:0] res_126_V_d0; +output [4:0] res_127_V_address0; +output res_127_V_ce0; +output res_127_V_we0; +output [7:0] res_127_V_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[6:0] data_V_address0; +reg data_V_ce0; +reg[4:0] res_0_V_address0; +reg res_0_V_ce0; +reg res_0_V_we0; +reg[4:0] res_1_V_address0; +reg res_1_V_ce0; +reg res_1_V_we0; +reg[4:0] res_2_V_address0; +reg res_2_V_ce0; +reg res_2_V_we0; +reg[4:0] res_3_V_address0; +reg res_3_V_ce0; +reg res_3_V_we0; +reg[4:0] res_4_V_address0; +reg res_4_V_ce0; +reg res_4_V_we0; +reg[4:0] res_5_V_address0; +reg res_5_V_ce0; +reg res_5_V_we0; +reg[4:0] res_6_V_address0; +reg res_6_V_ce0; +reg res_6_V_we0; +reg[4:0] res_7_V_address0; +reg res_7_V_ce0; +reg res_7_V_we0; +reg[4:0] res_8_V_address0; +reg res_8_V_ce0; +reg res_8_V_we0; +reg[4:0] res_9_V_address0; +reg res_9_V_ce0; +reg res_9_V_we0; +reg[4:0] res_10_V_address0; +reg res_10_V_ce0; +reg res_10_V_we0; +reg[4:0] res_11_V_address0; +reg res_11_V_ce0; +reg res_11_V_we0; +reg[4:0] res_12_V_address0; +reg res_12_V_ce0; +reg res_12_V_we0; +reg[4:0] res_13_V_address0; +reg res_13_V_ce0; +reg res_13_V_we0; +reg[4:0] res_14_V_address0; +reg res_14_V_ce0; +reg res_14_V_we0; +reg[4:0] res_15_V_address0; +reg res_15_V_ce0; +reg res_15_V_we0; +reg[4:0] res_16_V_address0; +reg res_16_V_ce0; +reg res_16_V_we0; +reg[4:0] res_17_V_address0; +reg res_17_V_ce0; +reg res_17_V_we0; +reg[4:0] res_18_V_address0; +reg res_18_V_ce0; +reg res_18_V_we0; +reg[4:0] res_19_V_address0; +reg res_19_V_ce0; +reg res_19_V_we0; +reg[4:0] res_20_V_address0; +reg res_20_V_ce0; +reg res_20_V_we0; +reg[4:0] res_21_V_address0; +reg res_21_V_ce0; +reg res_21_V_we0; +reg[4:0] res_22_V_address0; +reg res_22_V_ce0; +reg res_22_V_we0; +reg[4:0] res_23_V_address0; +reg res_23_V_ce0; +reg res_23_V_we0; +reg[4:0] res_24_V_address0; +reg res_24_V_ce0; +reg res_24_V_we0; +reg[4:0] res_25_V_address0; +reg res_25_V_ce0; +reg res_25_V_we0; +reg[4:0] res_26_V_address0; +reg res_26_V_ce0; +reg res_26_V_we0; +reg[4:0] res_27_V_address0; +reg res_27_V_ce0; +reg res_27_V_we0; +reg[4:0] res_28_V_address0; +reg res_28_V_ce0; +reg res_28_V_we0; +reg[4:0] res_29_V_address0; +reg res_29_V_ce0; +reg res_29_V_we0; +reg[4:0] res_30_V_address0; +reg res_30_V_ce0; +reg res_30_V_we0; +reg[4:0] res_31_V_address0; +reg res_31_V_ce0; +reg res_31_V_we0; +reg[4:0] res_32_V_address0; +reg res_32_V_ce0; +reg res_32_V_we0; +reg[4:0] res_33_V_address0; +reg res_33_V_ce0; +reg res_33_V_we0; +reg[4:0] res_34_V_address0; +reg res_34_V_ce0; +reg res_34_V_we0; +reg[4:0] res_35_V_address0; +reg res_35_V_ce0; +reg res_35_V_we0; +reg[4:0] res_36_V_address0; +reg res_36_V_ce0; +reg res_36_V_we0; +reg[4:0] res_37_V_address0; +reg res_37_V_ce0; +reg res_37_V_we0; +reg[4:0] res_38_V_address0; +reg res_38_V_ce0; +reg res_38_V_we0; +reg[4:0] res_39_V_address0; +reg res_39_V_ce0; +reg res_39_V_we0; +reg[4:0] res_40_V_address0; +reg res_40_V_ce0; +reg res_40_V_we0; +reg[4:0] res_41_V_address0; +reg res_41_V_ce0; +reg res_41_V_we0; +reg[4:0] res_42_V_address0; +reg res_42_V_ce0; +reg res_42_V_we0; +reg[4:0] res_43_V_address0; +reg res_43_V_ce0; +reg res_43_V_we0; +reg[4:0] res_44_V_address0; +reg res_44_V_ce0; +reg res_44_V_we0; +reg[4:0] res_45_V_address0; +reg res_45_V_ce0; +reg res_45_V_we0; +reg[4:0] res_46_V_address0; +reg res_46_V_ce0; +reg res_46_V_we0; +reg[4:0] res_47_V_address0; +reg res_47_V_ce0; +reg res_47_V_we0; +reg[4:0] res_48_V_address0; +reg res_48_V_ce0; +reg res_48_V_we0; +reg[4:0] res_49_V_address0; +reg res_49_V_ce0; +reg res_49_V_we0; +reg[4:0] res_50_V_address0; +reg res_50_V_ce0; +reg res_50_V_we0; +reg[4:0] res_51_V_address0; +reg res_51_V_ce0; +reg res_51_V_we0; +reg[4:0] res_52_V_address0; +reg res_52_V_ce0; +reg res_52_V_we0; +reg[4:0] res_53_V_address0; +reg res_53_V_ce0; +reg res_53_V_we0; +reg[4:0] res_54_V_address0; +reg res_54_V_ce0; +reg res_54_V_we0; +reg[4:0] res_55_V_address0; +reg res_55_V_ce0; +reg res_55_V_we0; +reg[4:0] res_56_V_address0; +reg res_56_V_ce0; +reg res_56_V_we0; +reg[4:0] res_57_V_address0; +reg res_57_V_ce0; +reg res_57_V_we0; +reg[4:0] res_58_V_address0; +reg res_58_V_ce0; +reg res_58_V_we0; +reg[4:0] res_59_V_address0; +reg res_59_V_ce0; +reg res_59_V_we0; +reg[4:0] res_60_V_address0; +reg res_60_V_ce0; +reg res_60_V_we0; +reg[4:0] res_61_V_address0; +reg res_61_V_ce0; +reg res_61_V_we0; +reg[4:0] res_62_V_address0; +reg res_62_V_ce0; +reg res_62_V_we0; +reg[4:0] res_63_V_address0; +reg res_63_V_ce0; +reg res_63_V_we0; +reg[4:0] res_64_V_address0; +reg res_64_V_ce0; +reg res_64_V_we0; +reg[4:0] res_65_V_address0; +reg res_65_V_ce0; +reg res_65_V_we0; +reg[4:0] res_66_V_address0; +reg res_66_V_ce0; +reg res_66_V_we0; +reg[4:0] res_67_V_address0; +reg res_67_V_ce0; +reg res_67_V_we0; +reg[4:0] res_68_V_address0; +reg res_68_V_ce0; +reg res_68_V_we0; +reg[4:0] res_69_V_address0; +reg res_69_V_ce0; +reg res_69_V_we0; +reg[4:0] res_70_V_address0; +reg res_70_V_ce0; +reg res_70_V_we0; +reg[4:0] res_71_V_address0; +reg res_71_V_ce0; +reg res_71_V_we0; +reg[4:0] res_72_V_address0; +reg res_72_V_ce0; +reg res_72_V_we0; +reg[4:0] res_73_V_address0; +reg res_73_V_ce0; +reg res_73_V_we0; +reg[4:0] res_74_V_address0; +reg res_74_V_ce0; +reg res_74_V_we0; +reg[4:0] res_75_V_address0; +reg res_75_V_ce0; +reg res_75_V_we0; +reg[4:0] res_76_V_address0; +reg res_76_V_ce0; +reg res_76_V_we0; +reg[4:0] res_77_V_address0; +reg res_77_V_ce0; +reg res_77_V_we0; +reg[4:0] res_78_V_address0; +reg res_78_V_ce0; +reg res_78_V_we0; +reg[4:0] res_79_V_address0; +reg res_79_V_ce0; +reg res_79_V_we0; +reg[4:0] res_80_V_address0; +reg res_80_V_ce0; +reg res_80_V_we0; +reg[4:0] res_81_V_address0; +reg res_81_V_ce0; +reg res_81_V_we0; +reg[4:0] res_82_V_address0; +reg res_82_V_ce0; +reg res_82_V_we0; +reg[4:0] res_83_V_address0; +reg res_83_V_ce0; +reg res_83_V_we0; +reg[4:0] res_84_V_address0; +reg res_84_V_ce0; +reg res_84_V_we0; +reg[4:0] res_85_V_address0; +reg res_85_V_ce0; +reg res_85_V_we0; +reg[4:0] res_86_V_address0; +reg res_86_V_ce0; +reg res_86_V_we0; +reg[4:0] res_87_V_address0; +reg res_87_V_ce0; +reg res_87_V_we0; +reg[4:0] res_88_V_address0; +reg res_88_V_ce0; +reg res_88_V_we0; +reg[4:0] res_89_V_address0; +reg res_89_V_ce0; +reg res_89_V_we0; +reg[4:0] res_90_V_address0; +reg res_90_V_ce0; +reg res_90_V_we0; +reg[4:0] res_91_V_address0; +reg res_91_V_ce0; +reg res_91_V_we0; +reg[4:0] res_92_V_address0; +reg res_92_V_ce0; +reg res_92_V_we0; +reg[4:0] res_93_V_address0; +reg res_93_V_ce0; +reg res_93_V_we0; +reg[4:0] res_94_V_address0; +reg res_94_V_ce0; +reg res_94_V_we0; +reg[4:0] res_95_V_address0; +reg res_95_V_ce0; +reg res_95_V_we0; +reg[4:0] res_96_V_address0; +reg res_96_V_ce0; +reg res_96_V_we0; +reg[4:0] res_97_V_address0; +reg res_97_V_ce0; +reg res_97_V_we0; +reg[4:0] res_98_V_address0; +reg res_98_V_ce0; +reg res_98_V_we0; +reg[4:0] res_99_V_address0; +reg res_99_V_ce0; +reg res_99_V_we0; +reg[4:0] res_100_V_address0; +reg res_100_V_ce0; +reg res_100_V_we0; +reg[4:0] res_101_V_address0; +reg res_101_V_ce0; +reg res_101_V_we0; +reg[4:0] res_102_V_address0; +reg res_102_V_ce0; +reg res_102_V_we0; +reg[4:0] res_103_V_address0; +reg res_103_V_ce0; +reg res_103_V_we0; +reg[4:0] res_104_V_address0; +reg res_104_V_ce0; +reg res_104_V_we0; +reg[4:0] res_105_V_address0; +reg res_105_V_ce0; +reg res_105_V_we0; +reg[4:0] res_106_V_address0; +reg res_106_V_ce0; +reg res_106_V_we0; +reg[4:0] res_107_V_address0; +reg res_107_V_ce0; +reg res_107_V_we0; +reg[4:0] res_108_V_address0; +reg res_108_V_ce0; +reg res_108_V_we0; +reg[4:0] res_109_V_address0; +reg res_109_V_ce0; +reg res_109_V_we0; +reg[4:0] res_110_V_address0; +reg res_110_V_ce0; +reg res_110_V_we0; +reg[4:0] res_111_V_address0; +reg res_111_V_ce0; +reg res_111_V_we0; +reg[4:0] res_112_V_address0; +reg res_112_V_ce0; +reg res_112_V_we0; +reg[4:0] res_113_V_address0; +reg res_113_V_ce0; +reg res_113_V_we0; +reg[4:0] res_114_V_address0; +reg res_114_V_ce0; +reg res_114_V_we0; +reg[4:0] res_115_V_address0; +reg res_115_V_ce0; +reg res_115_V_we0; +reg[4:0] res_116_V_address0; +reg res_116_V_ce0; +reg res_116_V_we0; +reg[4:0] res_117_V_address0; +reg res_117_V_ce0; +reg res_117_V_we0; +reg[4:0] res_118_V_address0; +reg res_118_V_ce0; +reg res_118_V_we0; +reg[4:0] res_119_V_address0; +reg res_119_V_ce0; +reg res_119_V_we0; +reg[4:0] res_120_V_address0; +reg res_120_V_ce0; +reg res_120_V_we0; +reg[4:0] res_121_V_address0; +reg res_121_V_ce0; +reg res_121_V_we0; +reg[4:0] res_122_V_address0; +reg res_122_V_ce0; +reg res_122_V_we0; +reg[4:0] res_123_V_address0; +reg res_123_V_ce0; +reg res_123_V_we0; +reg[4:0] res_124_V_address0; +reg res_124_V_ce0; +reg res_124_V_we0; +reg[4:0] res_125_V_address0; +reg res_125_V_ce0; +reg res_125_V_we0; +reg[4:0] res_126_V_address0; +reg res_126_V_ce0; +reg res_126_V_we0; +reg[4:0] res_127_V_address0; +reg res_127_V_ce0; +reg res_127_V_we0; + + reg [11:0] ap_CS_fsm; +reg [6:0] w2_V_address0; +reg w2_V_ce0; +wire [4:0] w2_V_q0; +wire [31:0] grp_fu_73367_p2; +reg [31:0] reg_73628; +reg [0:0] or_ln223_reg_90189; +wire [0:0] or_ln223_3_fu_73970_p2; +reg [4:0] reg_73633; +wire [31:0] grp_fu_73383_p2; +reg [31:0] reg_73637; +reg [0:0] or_ln223_8_reg_90312; +wire [0:0] or_ln223_14_fu_74795_p2; +wire [31:0] grp_fu_73399_p2; +reg [31:0] reg_73642; +reg [0:0] or_ln223_2_reg_90649; +wire [0:0] or_ln223_6_fu_75670_p2; +wire [31:0] grp_fu_73415_p2; +reg [31:0] reg_73647; +reg [0:0] or_ln223_12_reg_90772; +wire [0:0] or_ln223_18_fu_76485_p2; +wire [31:0] grp_fu_73431_p2; +reg [31:0] reg_73652; +reg [0:0] or_ln223_1_reg_91176; +wire [0:0] or_ln223_5_fu_77432_p2; +wire [31:0] grp_fu_73447_p2; +reg [31:0] reg_73657; +reg [0:0] or_ln223_10_reg_91305; +wire [0:0] or_ln223_17_fu_78255_p2; +wire [31:0] grp_fu_73463_p2; +reg [31:0] reg_73662; +reg [0:0] or_ln223_4_reg_91642; +wire [0:0] or_ln223_7_fu_79134_p2; +wire [31:0] grp_fu_73479_p2; +reg [31:0] reg_73667; +reg [0:0] or_ln223_15_reg_91776; +wire [0:0] or_ln223_19_fu_79946_p2; +wire [7:0] grp_fu_73495_p66; +reg [7:0] reg_73672; +wire [31:0] oh_0_0_cast_fu_73676_p1; +reg [31:0] oh_0_0_cast_reg_90067; +wire [16:0] mul_ln201_fu_89951_p2; +reg [16:0] mul_ln201_reg_90078; +wire [0:0] icmp_ln199_fu_73684_p2; +wire [31:0] ow_0_0_0_cast_fu_73690_p1; +reg [31:0] ow_0_0_0_cast_reg_90084; +wire [11:0] mul_ln231_fu_73704_p2; +reg [11:0] mul_ln231_reg_90095; +wire [0:0] icmp_ln201_fu_73698_p2; +wire [6:0] zext_ln231_fu_73710_p1; +reg [6:0] zext_ln231_reg_90100; +wire [10:0] sext_ln231_fu_73720_p1; +reg [10:0] sext_ln231_reg_90105; +wire [2:0] trunc_ln231_fu_73724_p1; +reg [2:0] trunc_ln231_reg_90111; +wire [2:0] add_ln1116_1_fu_73728_p2; +reg [2:0] add_ln1116_1_reg_90120; +wire [31:0] zext_ln199_fu_73740_p1; +reg [31:0] zext_ln199_reg_90126; +wire [16:0] mul_ln201_1_fu_89957_p2; +reg [16:0] mul_ln201_1_reg_90134; +wire [6:0] add_ln203_8_fu_73748_p2; +reg [6:0] add_ln203_8_reg_90140; +wire [31:0] zext_ln203_fu_73754_p1; +reg [31:0] zext_ln203_reg_90145; +wire [2:0] add_ln203_fu_73764_p2; +reg [2:0] add_ln203_reg_90153; +wire [31:0] zext_ln216_2_fu_73788_p1; +reg [31:0] zext_ln216_2_reg_90158; +wire [0:0] icmp_ln203_fu_73758_p2; +wire [31:0] zext_ln201_2_fu_73798_p1; +reg [31:0] zext_ln201_2_reg_90164; +wire [11:0] mul_ln231_2_fu_73806_p2; +reg [11:0] mul_ln231_2_reg_90172; +wire [10:0] sext_ln231_2_fu_73817_p1; +reg [10:0] sext_ln231_2_reg_90177; +wire [2:0] add_ln1116_2_fu_73821_p2; +reg [2:0] add_ln1116_2_reg_90183; +wire [0:0] or_ln223_fu_73853_p2; +wire [10:0] trunc_ln231_2_fu_73877_p1; +reg [10:0] trunc_ln231_2_reg_90193; +wire [31:0] add_ln216_3_fu_73904_p2; +reg [31:0] add_ln216_3_reg_90198; +wire [31:0] or_ln_fu_73920_p3; +reg [31:0] or_ln_reg_90204; +wire [10:0] add_ln231_3_fu_73928_p2; +reg [10:0] add_ln231_3_reg_90210; +reg [27:0] tmp_7_reg_90230; +wire [6:0] sub_ln1116_2_fu_74130_p2; +reg [6:0] sub_ln1116_2_reg_90240; +wire [63:0] lshr_ln1116_fu_74140_p2; +reg [63:0] lshr_ln1116_reg_90245; +reg [7:0] trunc_ln_reg_90250; +wire [31:0] add_ln216_20_fu_74239_p2; +reg [31:0] add_ln216_20_reg_90288; +wire [0:0] icmp_ln208_fu_74233_p2; +wire [0:0] or_ln223_9_fu_74283_p2; +wire [0:0] or_ln223_8_fu_74371_p2; +wire [0:0] icmp_ln206_fu_74326_p2; +wire [31:0] add_ln216_22_fu_74400_p2; +reg [31:0] add_ln216_22_reg_90316; +wire [31:0] add_ln221_12_fu_74411_p2; +reg [31:0] add_ln221_12_reg_90322; +wire [10:0] trunc_ln231_10_fu_74417_p1; +reg [10:0] trunc_ln231_10_reg_90328; +wire [2:0] trunc_ln1116_6_fu_74421_p1; +reg [2:0] trunc_ln1116_6_reg_90333; +reg [27:0] tmp_5_reg_90344; +wire [6:0] sub_ln1116_14_fu_74581_p2; +reg [6:0] sub_ln1116_14_reg_90352; +wire [63:0] lshr_ln1116_22_fu_74591_p2; +reg [63:0] lshr_ln1116_22_reg_90357; +reg [7:0] trunc_ln708_3_reg_90362; +reg [27:0] tmp_94_reg_90399; +wire [31:0] add_ln208_fu_74693_p2; +reg [27:0] tmp_91_reg_90417; +wire [10:0] add_ln231_8_fu_74753_p2; +reg [10:0] add_ln231_8_reg_90425; +reg [27:0] tmp_131_reg_90445; +wire [6:0] sub_ln1116_23_fu_74954_p2; +reg [6:0] sub_ln1116_23_reg_90455; +wire [63:0] lshr_ln1116_28_fu_74964_p2; +reg [63:0] lshr_ln1116_28_reg_90460; +reg [7:0] trunc_ln708_6_reg_90465; +wire [31:0] add_ln216_36_fu_75063_p2; +reg [31:0] add_ln216_36_reg_90503; +wire [0:0] icmp_ln208_4_fu_75057_p2; +wire [0:0] or_ln223_20_fu_75107_p2; +wire [2:0] trunc_ln1116_566113357_fu_75159_p2; +reg [2:0] trunc_ln1116_566113357_reg_90519; +wire [31:0] add_ln206_fu_75164_p2; +reg [27:0] tmp_127_reg_90539; +wire [6:0] sub_ln1116_38_fu_75304_p2; +reg [6:0] sub_ln1116_38_reg_90547; +wire [63:0] lshr_ln1116_38_fu_75314_p2; +reg [63:0] lshr_ln1116_38_reg_90552; +reg [7:0] trunc_ln708_11_reg_90557; +reg [27:0] tmp_205_reg_90594; +wire [31:0] add_ln208_4_fu_75416_p2; +reg [27:0] tmp_202_reg_90612; +wire [6:0] add_ln203_10_fu_75476_p2; +reg [6:0] add_ln203_10_reg_90620; +wire [31:0] zext_ln203_5_fu_75482_p1; +reg [31:0] zext_ln203_5_reg_90625; +wire [2:0] add_ln203_5_fu_75492_p2; +reg [2:0] add_ln203_5_reg_90633; +wire [31:0] zext_ln216_8_fu_75516_p1; +reg [31:0] zext_ln216_8_reg_90638; +wire [0:0] icmp_ln203_2_fu_75486_p2; +wire [4:0] add_ln201_fu_75520_p2; +wire [0:0] or_ln223_2_fu_75553_p2; +wire [10:0] trunc_ln231_4_fu_75577_p1; +reg [10:0] trunc_ln231_4_reg_90653; +wire [31:0] add_ln216_11_fu_75604_p2; +reg [31:0] add_ln216_11_reg_90658; +wire [31:0] or_ln221_2_fu_75620_p3; +reg [31:0] or_ln221_2_reg_90664; +wire [10:0] add_ln231_6_fu_75628_p2; +reg [10:0] add_ln231_6_reg_90670; +reg [27:0] tmp_63_reg_90690; +wire [6:0] sub_ln1116_8_fu_75820_p2; +reg [6:0] sub_ln1116_8_reg_90700; +wire [63:0] lshr_ln1116_18_fu_75830_p2; +reg [63:0] lshr_ln1116_18_reg_90705; +reg [7:0] trunc_ln708_1_reg_90710; +wire [31:0] add_ln216_24_fu_75929_p2; +reg [31:0] add_ln216_24_reg_90748; +wire [0:0] icmp_ln208_2_fu_75923_p2; +wire [0:0] or_ln223_13_fu_75973_p2; +wire [0:0] or_ln223_12_fu_76061_p2; +wire [0:0] icmp_ln206_2_fu_76016_p2; +wire [31:0] add_ln216_29_fu_76090_p2; +reg [31:0] add_ln216_29_reg_90776; +wire [31:0] add_ln221_19_fu_76101_p2; +reg [31:0] add_ln221_19_reg_90782; +wire [10:0] trunc_ln231_12_fu_76107_p1; +reg [10:0] trunc_ln231_12_reg_90788; +wire [2:0] trunc_ln1116_10_fu_76111_p1; +reg [2:0] trunc_ln1116_10_reg_90793; +reg [27:0] tmp_60_reg_90804; +wire [6:0] sub_ln1116_20_fu_76271_p2; +reg [6:0] sub_ln1116_20_reg_90812; +wire [63:0] lshr_ln1116_26_fu_76281_p2; +reg [63:0] lshr_ln1116_26_reg_90817; +reg [7:0] trunc_ln708_5_reg_90822; +reg [27:0] tmp_126_reg_90859; +wire [31:0] add_ln208_2_fu_76383_p2; +reg [27:0] tmp_123_reg_90877; +wire [10:0] add_ln231_10_fu_76443_p2; +reg [10:0] add_ln231_10_reg_90885; +reg [27:0] tmp_170_reg_90905; +wire [6:0] sub_ln1116_32_fu_76634_p2; +reg [6:0] sub_ln1116_32_reg_90915; +wire [63:0] lshr_ln1116_34_fu_76644_p2; +reg [63:0] lshr_ln1116_34_reg_90920; +reg [7:0] trunc_ln708_9_reg_90925; +wire [31:0] add_ln216_38_fu_76743_p2; +reg [31:0] add_ln216_38_reg_90963; +wire [0:0] icmp_ln208_6_fu_76737_p2; +wire [0:0] or_ln223_22_fu_76787_p2; +wire [2:0] trunc_ln1116_6061134315_fu_76839_p2; +reg [2:0] trunc_ln1116_6061134315_reg_90979; +wire [31:0] add_ln206_2_fu_76844_p2; +reg [27:0] tmp_167_reg_90999; +wire [6:0] sub_ln1116_44_fu_76984_p2; +reg [6:0] sub_ln1116_44_reg_91007; +wire [63:0] lshr_ln1116_42_fu_76994_p2; +reg [63:0] lshr_ln1116_42_reg_91012; +reg [7:0] trunc_ln708_13_reg_91017; +reg [27:0] tmp_226_reg_91054; +wire [31:0] add_ln208_6_fu_77096_p2; +reg [27:0] tmp_223_reg_91072; +wire [31:0] ow_0_1_0_cast_fu_77156_p1; +reg [31:0] ow_0_1_0_cast_reg_91080; +wire [11:0] mul_ln231_1_fu_77170_p2; +reg [11:0] mul_ln231_1_reg_91091; +wire [0:0] icmp_ln201_1_fu_77164_p2; +wire [6:0] zext_ln231_3_fu_77176_p1; +reg [6:0] zext_ln231_3_reg_91096; +wire [10:0] sext_ln231_1_fu_77186_p1; +reg [10:0] sext_ln231_1_reg_91101; +wire [2:0] trunc_ln231_1_fu_77190_p1; +reg [2:0] trunc_ln231_1_reg_91107; +wire [2:0] add_ln1116_fu_77194_p2; +reg [2:0] add_ln1116_reg_91112; +wire [4:0] add_ln199_fu_77200_p2; +wire [6:0] add_ln203_9_fu_77206_p2; +reg [6:0] add_ln203_9_reg_91125; +wire [31:0] zext_ln203_4_fu_77212_p1; +reg [31:0] zext_ln203_4_reg_91130; +wire [2:0] add_ln203_4_fu_77222_p2; +reg [2:0] add_ln203_4_reg_91138; +wire [31:0] zext_ln216_5_fu_77246_p1; +reg [31:0] zext_ln216_5_reg_91143; +wire [0:0] icmp_ln203_1_fu_77216_p2; +wire [31:0] zext_ln201_3_fu_77256_p1; +reg [31:0] zext_ln201_3_reg_91149; +wire [11:0] mul_ln231_3_fu_77264_p2; +reg [11:0] mul_ln231_3_reg_91157; +wire [10:0] sext_ln231_3_fu_77275_p1; +reg [10:0] sext_ln231_3_reg_91162; +wire [2:0] add_ln1116_3_fu_77279_p2; +reg [2:0] add_ln1116_3_reg_91168; +wire [0:0] or_ln223_1_fu_77311_p2; +wire [10:0] trunc_ln231_3_fu_77335_p1; +reg [10:0] trunc_ln231_3_reg_91180; +wire [2:0] trunc_ln1116_fu_77339_p1; +reg [2:0] trunc_ln1116_reg_91185; +wire [31:0] add_ln216_9_fu_77366_p2; +reg [31:0] add_ln216_9_reg_91191; +wire [31:0] or_ln221_1_fu_77382_p3; +reg [31:0] or_ln221_1_reg_91197; +wire [10:0] add_ln231_5_fu_77390_p2; +reg [10:0] add_ln231_5_reg_91203; +reg [27:0] tmp_59_reg_91223; +wire [6:0] sub_ln1116_5_fu_77591_p2; +reg [6:0] sub_ln1116_5_reg_91233; +wire [63:0] lshr_ln1116_16_fu_77601_p2; +reg [63:0] lshr_ln1116_16_reg_91238; +reg [7:0] trunc_ln708_s_reg_91243; +wire [31:0] add_ln216_23_fu_77700_p2; +reg [31:0] add_ln216_23_reg_91281; +wire [0:0] icmp_ln208_1_fu_77694_p2; +wire [0:0] or_ln223_11_fu_77744_p2; +wire [0:0] or_ln223_10_fu_77832_p2; +wire [0:0] icmp_ln206_1_fu_77787_p2; +wire [31:0] add_ln216_27_fu_77861_p2; +reg [31:0] add_ln216_27_reg_91309; +wire [31:0] add_ln221_17_fu_77872_p2; +reg [31:0] add_ln221_17_reg_91315; +wire [10:0] trunc_ln231_11_fu_77878_p1; +reg [10:0] trunc_ln231_11_reg_91321; +wire [2:0] trunc_ln1116_9_fu_77882_p1; +reg [2:0] trunc_ln1116_9_reg_91326; +reg [27:0] tmp_55_reg_91337; +wire [6:0] sub_ln1116_17_fu_78041_p2; +reg [6:0] sub_ln1116_17_reg_91345; +wire [63:0] lshr_ln1116_24_fu_78051_p2; +reg [63:0] lshr_ln1116_24_reg_91350; +reg [7:0] trunc_ln708_4_reg_91355; +reg [27:0] tmp_122_reg_91392; +wire [31:0] add_ln208_1_fu_78153_p2; +reg [27:0] tmp_119_reg_91410; +wire [10:0] add_ln231_9_fu_78213_p2; +reg [10:0] add_ln231_9_reg_91418; +reg [27:0] tmp_166_reg_91438; +wire [6:0] sub_ln1116_29_fu_78414_p2; +reg [6:0] sub_ln1116_29_reg_91448; +wire [63:0] lshr_ln1116_32_fu_78424_p2; +reg [63:0] lshr_ln1116_32_reg_91453; +reg [7:0] trunc_ln708_8_reg_91458; +wire [31:0] add_ln216_37_fu_78523_p2; +reg [31:0] add_ln216_37_reg_91496; +wire [0:0] icmp_ln208_5_fu_78517_p2; +wire [0:0] or_ln223_21_fu_78567_p2; +wire [2:0] trunc_ln1116_5861135123_fu_78619_p2; +reg [2:0] trunc_ln1116_5861135123_reg_91512; +wire [31:0] add_ln206_1_fu_78624_p2; +reg [27:0] tmp_162_reg_91532; +wire [6:0] sub_ln1116_41_fu_78764_p2; +reg [6:0] sub_ln1116_41_reg_91540; +wire [63:0] lshr_ln1116_40_fu_78774_p2; +reg [63:0] lshr_ln1116_40_reg_91545; +reg [7:0] trunc_ln708_12_reg_91550; +reg [27:0] tmp_222_reg_91587; +wire [31:0] add_ln208_5_fu_78876_p2; +reg [27:0] tmp_219_reg_91605; +wire [6:0] add_ln203_11_fu_78936_p2; +reg [6:0] add_ln203_11_reg_91613; +wire [31:0] zext_ln203_8_fu_78942_p1; +reg [31:0] zext_ln203_8_reg_91618; +wire [2:0] add_ln203_6_fu_78952_p2; +reg [2:0] add_ln203_6_reg_91626; +wire [31:0] zext_ln216_11_fu_78976_p1; +reg [31:0] zext_ln216_11_reg_91631; +wire [0:0] icmp_ln203_3_fu_78946_p2; +wire [4:0] add_ln201_1_fu_78980_p2; +wire [0:0] or_ln223_4_fu_79013_p2; +wire [10:0] trunc_ln231_6_fu_79037_p1; +reg [10:0] trunc_ln231_6_reg_91646; +wire [2:0] trunc_ln1116_2_fu_79041_p1; +reg [2:0] trunc_ln1116_2_reg_91651; +wire [31:0] add_ln216_17_fu_79068_p2; +reg [31:0] add_ln216_17_reg_91657; +wire [31:0] or_ln221_3_fu_79084_p3; +reg [31:0] or_ln221_3_reg_91663; +wire [10:0] add_ln231_7_fu_79092_p2; +reg [10:0] add_ln231_7_reg_91669; +reg [27:0] tmp_78_reg_91689; +wire [6:0] sub_ln1116_11_fu_79283_p2; +reg [6:0] sub_ln1116_11_reg_91699; +wire [63:0] lshr_ln1116_20_fu_79293_p2; +reg [63:0] lshr_ln1116_20_reg_91704; +reg [7:0] trunc_ln708_2_reg_91709; +wire [31:0] add_ln216_30_fu_79392_p2; +reg [31:0] add_ln216_30_reg_91747; +wire [0:0] icmp_ln208_3_fu_79386_p2; +wire [0:0] or_ln223_16_fu_79436_p2; +wire [2:0] trunc_ln1116_4861135527_fu_79488_p2; +reg [2:0] trunc_ln1116_4861135527_reg_91763; +wire [0:0] or_ln223_15_fu_79544_p2; +wire [0:0] icmp_ln206_3_fu_79499_p2; +wire [31:0] add_ln216_34_fu_79573_p2; +reg [31:0] add_ln216_34_reg_91780; +wire [31:0] add_ln221_24_fu_79584_p2; +reg [31:0] add_ln221_24_reg_91786; +wire [10:0] trunc_ln231_14_fu_79590_p1; +reg [10:0] trunc_ln231_14_reg_91792; +wire [2:0] trunc_ln1116_16_fu_79594_p1; +reg [2:0] trunc_ln1116_16_reg_91797; +reg [27:0] tmp_75_reg_91808; +wire [6:0] sub_ln1116_26_fu_79732_p2; +reg [6:0] sub_ln1116_26_reg_91816; +wire [63:0] lshr_ln1116_30_fu_79742_p2; +reg [63:0] lshr_ln1116_30_reg_91821; +reg [7:0] trunc_ln708_7_reg_91826; +reg [27:0] tmp_161_reg_91863; +wire [31:0] add_ln208_3_fu_79844_p2; +reg [27:0] tmp_158_reg_91881; +wire [10:0] add_ln231_11_fu_79904_p2; +reg [10:0] add_ln231_11_reg_91889; +reg [27:0] tmp_189_reg_91909; +wire [6:0] sub_ln1116_35_fu_80095_p2; +reg [6:0] sub_ln1116_35_reg_91919; +wire [63:0] lshr_ln1116_36_fu_80105_p2; +reg [63:0] lshr_ln1116_36_reg_91924; +reg [7:0] trunc_ln708_10_reg_91929; +wire [31:0] add_ln216_39_fu_80204_p2; +reg [31:0] add_ln216_39_reg_91967; +wire [0:0] icmp_ln208_7_fu_80198_p2; +wire [0:0] or_ln223_23_fu_80248_p2; +wire [2:0] trunc_ln1116_6261135931_fu_80300_p2; +reg [2:0] trunc_ln1116_6261135931_reg_91983; +wire [31:0] add_ln206_3_fu_80305_p2; +reg [27:0] tmp_186_reg_92003; +wire [6:0] sub_ln1116_47_fu_80445_p2; +reg [6:0] sub_ln1116_47_reg_92011; +wire [63:0] lshr_ln1116_44_fu_80455_p2; +reg [63:0] lshr_ln1116_44_reg_92016; +reg [7:0] trunc_ln708_14_reg_92021; +reg [27:0] tmp_239_reg_92058; +wire [31:0] add_ln208_7_fu_80557_p2; +reg [27:0] tmp_237_reg_92076; +wire [12:0] sub_ln250_fu_80647_p2; +reg [12:0] sub_ln250_reg_92087; +wire [0:0] icmp_ln244_fu_80617_p2; +wire [5:0] trunc_ln250_fu_80653_p1; +reg [5:0] trunc_ln250_reg_92093; +wire [6:0] shl_ln250_1_fu_80663_p3; +reg [6:0] shl_ln250_1_reg_92102; +wire [0:0] icmp_ln246_fu_80657_p2; +wire [5:0] trunc_ln250_8_fu_80679_p3; +reg [5:0] trunc_ln250_8_reg_92107; +wire [5:0] add_ln250_1_fu_80692_p2; +reg [5:0] add_ln250_1_reg_92112; +reg [5:0] acc_0_V_addr_49_reg_92118; +reg [5:0] acc_2_V_addr_49_reg_92123; +reg [5:0] acc_4_V_addr_49_reg_92128; +reg [5:0] acc_6_V_addr_49_reg_92133; +reg [5:0] acc_8_V_addr_49_reg_92138; +reg [5:0] acc_10_V_addr_49_reg_92143; +reg [5:0] acc_12_V_addr_49_reg_92148; +reg [5:0] acc_14_V_addr_49_reg_92153; +reg [5:0] acc_16_V_addr_49_reg_92158; +reg [5:0] acc_18_V_addr_49_reg_92163; +reg [5:0] acc_20_V_addr_49_reg_92168; +reg [5:0] acc_22_V_addr_49_reg_92173; +reg [5:0] acc_24_V_addr_49_reg_92178; +reg [5:0] acc_26_V_addr_49_reg_92183; +reg [5:0] acc_28_V_addr_49_reg_92188; +reg [5:0] acc_30_V_addr_49_reg_92193; +reg [5:0] acc_32_V_addr_49_reg_92198; +reg [5:0] acc_34_V_addr_49_reg_92203; +reg [5:0] acc_36_V_addr_49_reg_92208; +reg [5:0] acc_38_V_addr_49_reg_92213; +reg [5:0] acc_40_V_addr_49_reg_92218; +reg [5:0] acc_42_V_addr_49_reg_92223; +reg [5:0] acc_44_V_addr_49_reg_92228; +reg [5:0] acc_46_V_addr_49_reg_92233; +reg [5:0] acc_48_V_addr_49_reg_92238; +reg [5:0] acc_50_V_addr_49_reg_92243; +reg [5:0] acc_52_V_addr_49_reg_92248; +reg [5:0] acc_54_V_addr_49_reg_92253; +reg [5:0] acc_56_V_addr_49_reg_92258; +reg [5:0] acc_58_V_addr_49_reg_92263; +reg [5:0] acc_60_V_addr_49_reg_92268; +reg [5:0] acc_62_V_addr_49_reg_92273; +reg [5:0] acc_63_V_addr_49_reg_92278; +reg [5:0] acc_1_V_addr_49_reg_92283; +reg [5:0] acc_3_V_addr_49_reg_92288; +reg [5:0] acc_5_V_addr_49_reg_92293; +reg [5:0] acc_7_V_addr_49_reg_92298; +reg [5:0] acc_9_V_addr_49_reg_92303; +reg [5:0] acc_11_V_addr_49_reg_92308; +reg [5:0] acc_13_V_addr_49_reg_92313; +reg [5:0] acc_15_V_addr_49_reg_92318; +reg [5:0] acc_17_V_addr_49_reg_92323; +reg [5:0] acc_19_V_addr_49_reg_92328; +reg [5:0] acc_21_V_addr_49_reg_92333; +reg [5:0] acc_23_V_addr_49_reg_92338; +reg [5:0] acc_25_V_addr_49_reg_92343; +reg [5:0] acc_27_V_addr_49_reg_92348; +reg [5:0] acc_29_V_addr_49_reg_92353; +reg [5:0] acc_31_V_addr_49_reg_92358; +reg [5:0] acc_33_V_addr_49_reg_92363; +reg [5:0] acc_35_V_addr_49_reg_92368; +reg [5:0] acc_37_V_addr_49_reg_92373; +reg [5:0] acc_39_V_addr_49_reg_92378; +reg [5:0] acc_41_V_addr_49_reg_92383; +reg [5:0] acc_43_V_addr_49_reg_92388; +reg [5:0] acc_45_V_addr_49_reg_92393; +reg [5:0] acc_47_V_addr_49_reg_92398; +reg [5:0] acc_49_V_addr_49_reg_92403; +reg [5:0] acc_51_V_addr_49_reg_92408; +reg [5:0] acc_53_V_addr_49_reg_92413; +reg [5:0] acc_55_V_addr_49_reg_92418; +reg [5:0] acc_57_V_addr_49_reg_92423; +reg [5:0] acc_59_V_addr_49_reg_92428; +reg [5:0] acc_61_V_addr_49_reg_92433; +wire [12:0] sub_ln250_1_fu_80809_p2; +reg [12:0] sub_ln250_1_reg_92438; +wire [5:0] trunc_ln250_1_fu_80815_p1; +reg [5:0] trunc_ln250_1_reg_92444; +wire [12:0] add_ln250_4_fu_80856_p2; +reg [12:0] add_ln250_4_reg_92456; +wire [0:0] icmp_ln248_fu_80819_p2; +wire [5:0] add_ln250_5_fu_80861_p2; +reg [5:0] add_ln250_5_reg_92461; +reg [5:0] acc_1_V_addr_52_reg_92467; +reg [5:0] acc_3_V_addr_52_reg_92472; +reg [5:0] acc_5_V_addr_52_reg_92477; +reg [5:0] acc_7_V_addr_52_reg_92482; +reg [5:0] acc_9_V_addr_52_reg_92487; +reg [5:0] acc_11_V_addr_52_reg_92492; +reg [5:0] acc_13_V_addr_52_reg_92497; +reg [5:0] acc_15_V_addr_52_reg_92502; +reg [5:0] acc_17_V_addr_52_reg_92507; +reg [5:0] acc_19_V_addr_52_reg_92512; +reg [5:0] acc_21_V_addr_52_reg_92517; +reg [5:0] acc_23_V_addr_52_reg_92522; +reg [5:0] acc_25_V_addr_52_reg_92527; +reg [5:0] acc_27_V_addr_52_reg_92532; +reg [5:0] acc_29_V_addr_52_reg_92537; +reg [5:0] acc_31_V_addr_52_reg_92542; +reg [5:0] acc_33_V_addr_52_reg_92547; +reg [5:0] acc_35_V_addr_52_reg_92552; +reg [5:0] acc_37_V_addr_52_reg_92557; +reg [5:0] acc_39_V_addr_52_reg_92562; +reg [5:0] acc_41_V_addr_52_reg_92567; +reg [5:0] acc_43_V_addr_52_reg_92572; +reg [5:0] acc_45_V_addr_52_reg_92577; +reg [5:0] acc_47_V_addr_52_reg_92582; +reg [5:0] acc_49_V_addr_52_reg_92587; +reg [5:0] acc_51_V_addr_52_reg_92592; +reg [5:0] acc_53_V_addr_52_reg_92597; +reg [5:0] acc_55_V_addr_52_reg_92602; +reg [5:0] acc_57_V_addr_52_reg_92607; +reg [5:0] acc_59_V_addr_52_reg_92612; +reg [5:0] acc_61_V_addr_52_reg_92617; +reg [5:0] acc_63_V_addr_52_reg_92622; +wire [2:0] add_ln248_fu_80943_p2; +wire [4:0] add_ln246_fu_81024_p2; +wire [0:0] icmp_ln248_2_fu_80953_p2; +wire [2:0] add_ln248_2_fu_81057_p2; +wire [6:0] shl_ln250_2_fu_81069_p3; +reg [6:0] shl_ln250_2_reg_92657; +wire [0:0] icmp_ln246_1_fu_81063_p2; +wire [5:0] trunc_ln250_9_fu_81085_p3; +reg [5:0] trunc_ln250_9_reg_92662; +wire [5:0] add_ln250_3_fu_81098_p2; +reg [5:0] add_ln250_3_reg_92667; +reg [5:0] acc_0_V_addr_51_reg_92673; +reg [5:0] acc_2_V_addr_51_reg_92678; +reg [5:0] acc_4_V_addr_51_reg_92683; +reg [5:0] acc_6_V_addr_51_reg_92688; +reg [5:0] acc_8_V_addr_51_reg_92693; +reg [5:0] acc_10_V_addr_51_reg_92698; +reg [5:0] acc_12_V_addr_51_reg_92703; +reg [5:0] acc_14_V_addr_51_reg_92708; +reg [5:0] acc_16_V_addr_51_reg_92713; +reg [5:0] acc_18_V_addr_51_reg_92718; +reg [5:0] acc_20_V_addr_51_reg_92723; +reg [5:0] acc_22_V_addr_51_reg_92728; +reg [5:0] acc_24_V_addr_51_reg_92733; +reg [5:0] acc_26_V_addr_51_reg_92738; +reg [5:0] acc_28_V_addr_51_reg_92743; +reg [5:0] acc_30_V_addr_51_reg_92748; +reg [5:0] acc_32_V_addr_51_reg_92753; +reg [5:0] acc_34_V_addr_51_reg_92758; +reg [5:0] acc_36_V_addr_51_reg_92763; +reg [5:0] acc_38_V_addr_51_reg_92768; +reg [5:0] acc_40_V_addr_51_reg_92773; +reg [5:0] acc_42_V_addr_51_reg_92778; +reg [5:0] acc_44_V_addr_51_reg_92783; +reg [5:0] acc_46_V_addr_51_reg_92788; +reg [5:0] acc_48_V_addr_51_reg_92793; +reg [5:0] acc_50_V_addr_51_reg_92798; +reg [5:0] acc_52_V_addr_51_reg_92803; +reg [5:0] acc_54_V_addr_51_reg_92808; +reg [5:0] acc_56_V_addr_51_reg_92813; +reg [5:0] acc_58_V_addr_51_reg_92818; +reg [5:0] acc_60_V_addr_51_reg_92823; +reg [5:0] acc_62_V_addr_51_reg_92828; +reg [5:0] acc_63_V_addr_51_reg_92833; +reg [5:0] acc_1_V_addr_51_reg_92838; +reg [5:0] acc_3_V_addr_51_reg_92843; +reg [5:0] acc_5_V_addr_51_reg_92848; +reg [5:0] acc_7_V_addr_51_reg_92853; +reg [5:0] acc_9_V_addr_51_reg_92858; +reg [5:0] acc_11_V_addr_51_reg_92863; +reg [5:0] acc_13_V_addr_51_reg_92868; +reg [5:0] acc_15_V_addr_51_reg_92873; +reg [5:0] acc_17_V_addr_51_reg_92878; +reg [5:0] acc_19_V_addr_51_reg_92883; +reg [5:0] acc_21_V_addr_51_reg_92888; +reg [5:0] acc_23_V_addr_51_reg_92893; +reg [5:0] acc_25_V_addr_51_reg_92898; +reg [5:0] acc_27_V_addr_51_reg_92903; +reg [5:0] acc_29_V_addr_51_reg_92908; +reg [5:0] acc_31_V_addr_51_reg_92913; +reg [5:0] acc_33_V_addr_51_reg_92918; +reg [5:0] acc_35_V_addr_51_reg_92923; +reg [5:0] acc_37_V_addr_51_reg_92928; +reg [5:0] acc_39_V_addr_51_reg_92933; +reg [5:0] acc_41_V_addr_51_reg_92938; +reg [5:0] acc_43_V_addr_51_reg_92943; +reg [5:0] acc_45_V_addr_51_reg_92948; +reg [5:0] acc_47_V_addr_51_reg_92953; +reg [5:0] acc_49_V_addr_51_reg_92958; +reg [5:0] acc_51_V_addr_51_reg_92963; +reg [5:0] acc_53_V_addr_51_reg_92968; +reg [5:0] acc_55_V_addr_51_reg_92973; +reg [5:0] acc_57_V_addr_51_reg_92978; +reg [5:0] acc_59_V_addr_51_reg_92983; +reg [5:0] acc_61_V_addr_51_reg_92988; +wire [4:0] add_ln244_fu_81185_p2; +wire [13:0] sext_ln250_fu_81233_p1; +reg [13:0] sext_ln250_reg_93004; +wire [0:0] icmp_ln248_1_fu_81191_p2; +wire [5:0] add_ln250_7_fu_81237_p2; +reg [5:0] add_ln250_7_reg_93009; +reg [5:0] acc_1_V_addr_55_reg_93015; +reg [5:0] acc_3_V_addr_55_reg_93020; +reg [5:0] acc_5_V_addr_55_reg_93025; +reg [5:0] acc_7_V_addr_55_reg_93030; +reg [5:0] acc_9_V_addr_55_reg_93035; +reg [5:0] acc_11_V_addr_55_reg_93040; +reg [5:0] acc_13_V_addr_55_reg_93045; +reg [5:0] acc_15_V_addr_55_reg_93050; +reg [5:0] acc_17_V_addr_55_reg_93055; +reg [5:0] acc_19_V_addr_55_reg_93060; +reg [5:0] acc_21_V_addr_55_reg_93065; +reg [5:0] acc_23_V_addr_55_reg_93070; +reg [5:0] acc_25_V_addr_55_reg_93075; +reg [5:0] acc_27_V_addr_55_reg_93080; +reg [5:0] acc_29_V_addr_55_reg_93085; +reg [5:0] acc_31_V_addr_55_reg_93090; +reg [5:0] acc_33_V_addr_55_reg_93095; +reg [5:0] acc_35_V_addr_55_reg_93100; +reg [5:0] acc_37_V_addr_55_reg_93105; +reg [5:0] acc_39_V_addr_55_reg_93110; +reg [5:0] acc_41_V_addr_55_reg_93115; +reg [5:0] acc_43_V_addr_55_reg_93120; +reg [5:0] acc_45_V_addr_55_reg_93125; +reg [5:0] acc_47_V_addr_55_reg_93130; +reg [5:0] acc_49_V_addr_55_reg_93135; +reg [5:0] acc_51_V_addr_55_reg_93140; +reg [5:0] acc_53_V_addr_55_reg_93145; +reg [5:0] acc_55_V_addr_55_reg_93150; +reg [5:0] acc_57_V_addr_55_reg_93155; +reg [5:0] acc_59_V_addr_55_reg_93160; +reg [5:0] acc_61_V_addr_55_reg_93165; +reg [5:0] acc_63_V_addr_55_reg_93170; +wire [2:0] add_ln248_1_fu_81319_p2; +wire [4:0] add_ln246_1_fu_81400_p2; +wire [0:0] icmp_ln248_3_fu_81329_p2; +wire [2:0] add_ln248_3_fu_81433_p2; +wire [16:0] mul_ln279_fu_89963_p2; +reg [16:0] mul_ln279_reg_93205; +wire [0:0] icmp_ln257_fu_81443_p2; +wire [12:0] sub_ln279_fu_81473_p2; +reg [12:0] sub_ln279_reg_93211; +wire [5:0] trunc_ln279_fu_81479_p1; +reg [5:0] trunc_ln279_reg_93217; +wire [5:0] add_ln279_1_fu_81522_p2; +reg [5:0] add_ln279_1_reg_93866; +wire [0:0] icmp_ln259_fu_81487_p2; +reg [5:0] acc_0_V_addr_50_reg_93872; +reg [5:0] acc_2_V_addr_50_reg_93878; +reg [5:0] acc_4_V_addr_50_reg_93884; +reg [5:0] acc_6_V_addr_50_reg_93890; +reg [5:0] acc_8_V_addr_50_reg_93896; +reg [5:0] acc_10_V_addr_50_reg_93902; +reg [5:0] acc_12_V_addr_50_reg_93908; +reg [5:0] acc_14_V_addr_50_reg_93914; +reg [5:0] acc_16_V_addr_50_reg_93920; +reg [5:0] acc_18_V_addr_50_reg_93926; +reg [5:0] acc_20_V_addr_50_reg_93932; +reg [5:0] acc_22_V_addr_50_reg_93938; +reg [5:0] acc_24_V_addr_50_reg_93944; +reg [5:0] acc_26_V_addr_50_reg_93950; +reg [5:0] acc_28_V_addr_50_reg_93956; +reg [5:0] acc_30_V_addr_50_reg_93962; +reg [5:0] acc_32_V_addr_50_reg_93968; +reg [5:0] acc_34_V_addr_50_reg_93974; +reg [5:0] acc_36_V_addr_50_reg_93980; +reg [5:0] acc_38_V_addr_50_reg_93986; +reg [5:0] acc_40_V_addr_50_reg_93992; +reg [5:0] acc_42_V_addr_50_reg_93998; +reg [5:0] acc_44_V_addr_50_reg_94004; +reg [5:0] acc_46_V_addr_50_reg_94010; +reg [5:0] acc_48_V_addr_50_reg_94016; +reg [5:0] acc_50_V_addr_50_reg_94022; +reg [5:0] acc_52_V_addr_50_reg_94028; +reg [5:0] acc_54_V_addr_50_reg_94034; +reg [5:0] acc_56_V_addr_50_reg_94040; +reg [5:0] acc_58_V_addr_50_reg_94046; +reg [5:0] acc_60_V_addr_50_reg_94052; +reg [5:0] acc_62_V_addr_50_reg_94058; +reg [5:0] acc_63_V_addr_50_reg_94064; +wire [16:0] grp_fu_89969_p3; +reg [16:0] add_ln276_reg_94070; +reg [5:0] acc_1_V_addr_50_reg_94076; +reg [5:0] acc_3_V_addr_50_reg_94082; +reg [5:0] acc_9_V_addr_50_reg_94088; +reg [5:0] acc_11_V_addr_50_reg_94094; +reg [5:0] acc_17_V_addr_50_reg_94100; +reg [5:0] acc_19_V_addr_50_reg_94106; +reg [5:0] acc_25_V_addr_50_reg_94112; +reg [5:0] acc_27_V_addr_50_reg_94118; +reg [5:0] acc_33_V_addr_50_reg_94124; +reg [5:0] acc_35_V_addr_50_reg_94130; +reg [5:0] acc_41_V_addr_50_reg_94136; +reg [5:0] acc_43_V_addr_50_reg_94142; +reg [5:0] acc_49_V_addr_50_reg_94148; +reg [5:0] acc_51_V_addr_50_reg_94154; +reg [5:0] acc_57_V_addr_50_reg_94160; +reg [5:0] acc_59_V_addr_50_reg_94166; +reg [5:0] acc_61_V_addr_50_reg_94172; +reg [5:0] acc_55_V_addr_50_reg_94177; +reg [5:0] acc_53_V_addr_50_reg_94182; +reg [5:0] acc_47_V_addr_50_reg_94187; +reg [5:0] acc_45_V_addr_50_reg_94192; +reg [5:0] acc_39_V_addr_50_reg_94197; +reg [5:0] acc_37_V_addr_50_reg_94202; +reg [5:0] acc_31_V_addr_50_reg_94207; +reg [5:0] acc_29_V_addr_50_reg_94212; +reg [5:0] acc_23_V_addr_50_reg_94217; +reg [5:0] acc_21_V_addr_50_reg_94222; +reg [5:0] acc_15_V_addr_50_reg_94227; +reg [5:0] acc_13_V_addr_50_reg_94232; +reg [5:0] acc_7_V_addr_50_reg_94237; +reg [5:0] acc_5_V_addr_50_reg_94242; +wire [16:0] mul_ln279_1_fu_89976_p2; +reg [16:0] mul_ln279_1_reg_94247; +wire [12:0] sub_ln279_1_fu_81643_p2; +reg [12:0] sub_ln279_1_reg_94253; +wire [5:0] trunc_ln279_1_fu_81649_p1; +reg [5:0] trunc_ln279_1_reg_94259; +wire [5:0] or_ln3_fu_81672_p3; +reg [5:0] or_ln3_reg_94268; +wire [0:0] icmp_ln261_fu_81657_p2; +wire [31:0] zext_ln1265_fu_81680_p1; +reg [31:0] zext_ln1265_reg_94272; +wire [31:0] zext_ln276_fu_81684_p1; +reg [31:0] zext_ln276_reg_94277; +wire [12:0] add_ln279_4_fu_81721_p2; +reg [12:0] add_ln279_4_reg_94283; +wire [5:0] add_ln279_5_fu_81726_p2; +reg [5:0] add_ln279_5_reg_94288; +wire [16:0] grp_fu_89990_p3; +reg [16:0] add_ln276_2_reg_94294; +reg [5:0] acc_5_V_addr_54_reg_94300; +reg [5:0] acc_7_V_addr_54_reg_94306; +reg [5:0] acc_13_V_addr_54_reg_94312; +reg [5:0] acc_15_V_addr_54_reg_94318; +reg [5:0] acc_21_V_addr_54_reg_94324; +reg [5:0] acc_23_V_addr_54_reg_94330; +reg [5:0] acc_29_V_addr_54_reg_94336; +reg [5:0] acc_31_V_addr_54_reg_94342; +reg [5:0] acc_37_V_addr_54_reg_94348; +reg [5:0] acc_39_V_addr_54_reg_94354; +reg [5:0] acc_45_V_addr_54_reg_94360; +reg [5:0] acc_47_V_addr_54_reg_94366; +reg [5:0] acc_53_V_addr_54_reg_94372; +reg [5:0] acc_55_V_addr_54_reg_94378; +reg [5:0] acc_61_V_addr_54_reg_94384; +reg [5:0] acc_63_V_addr_54_reg_94390; +reg [5:0] acc_62_V_addr_53_reg_94396; +reg [5:0] acc_60_V_addr_53_reg_94402; +reg [5:0] acc_59_V_addr_54_reg_94408; +reg [5:0] acc_58_V_addr_53_reg_94414; +reg [5:0] acc_57_V_addr_54_reg_94420; +reg [5:0] acc_56_V_addr_53_reg_94426; +reg [5:0] acc_54_V_addr_53_reg_94432; +reg [5:0] acc_52_V_addr_53_reg_94438; +reg [5:0] acc_51_V_addr_54_reg_94444; +reg [5:0] acc_50_V_addr_53_reg_94450; +reg [5:0] acc_49_V_addr_54_reg_94456; +reg [5:0] acc_48_V_addr_53_reg_94462; +reg [5:0] acc_46_V_addr_53_reg_94468; +reg [5:0] acc_44_V_addr_53_reg_94474; +reg [5:0] acc_43_V_addr_54_reg_94480; +reg [5:0] acc_42_V_addr_53_reg_94486; +reg [5:0] acc_41_V_addr_54_reg_94492; +reg [5:0] acc_40_V_addr_53_reg_94498; +reg [5:0] acc_38_V_addr_53_reg_94504; +reg [5:0] acc_36_V_addr_53_reg_94510; +reg [5:0] acc_35_V_addr_54_reg_94516; +reg [5:0] acc_34_V_addr_53_reg_94522; +reg [5:0] acc_33_V_addr_54_reg_94528; +reg [5:0] acc_32_V_addr_53_reg_94534; +reg [5:0] acc_30_V_addr_53_reg_94540; +reg [5:0] acc_28_V_addr_53_reg_94546; +reg [5:0] acc_27_V_addr_54_reg_94552; +reg [5:0] acc_26_V_addr_53_reg_94558; +reg [5:0] acc_25_V_addr_54_reg_94564; +reg [5:0] acc_24_V_addr_53_reg_94570; +reg [5:0] acc_22_V_addr_53_reg_94576; +reg [5:0] acc_20_V_addr_53_reg_94582; +reg [5:0] acc_19_V_addr_54_reg_94588; +reg [5:0] acc_18_V_addr_53_reg_94594; +reg [5:0] acc_17_V_addr_54_reg_94600; +reg [5:0] acc_16_V_addr_53_reg_94606; +reg [5:0] acc_14_V_addr_53_reg_94612; +reg [5:0] acc_12_V_addr_53_reg_94618; +reg [5:0] acc_11_V_addr_54_reg_94624; +reg [5:0] acc_10_V_addr_53_reg_94630; +reg [5:0] acc_9_V_addr_54_reg_94636; +reg [5:0] acc_8_V_addr_53_reg_94642; +reg [5:0] acc_6_V_addr_53_reg_94648; +reg [5:0] acc_4_V_addr_53_reg_94654; +reg [5:0] acc_3_V_addr_54_reg_94660; +reg [5:0] acc_2_V_addr_53_reg_94666; +reg [5:0] acc_1_V_addr_54_reg_94672; +reg [5:0] acc_0_V_addr_53_reg_94678; +wire [31:0] add_ln276_5_fu_81824_p2; +reg [31:0] add_ln276_5_reg_94684; +wire [31:0] add_ln276_9_fu_81830_p2; +reg [31:0] add_ln276_9_reg_94690; +reg [27:0] tmp_51_reg_94701; +wire [7:0] tmp_52_fu_81891_p30; +reg [7:0] tmp_52_reg_94846; +wire [7:0] add_ln703_fu_81953_p2; +reg [7:0] add_ln703_reg_94851; +wire [31:0] add_ln276_19_fu_82003_p2; +reg [31:0] add_ln276_19_reg_94859; +wire [0:0] icmp_ln268_fu_81997_p2; +wire [31:0] add_ln276_23_fu_82037_p2; +reg [31:0] add_ln276_23_reg_94868; +wire [0:0] icmp_ln266_fu_82020_p2; +wire [5:0] or_ln1265_2_fu_82066_p3; +reg [5:0] or_ln1265_2_reg_94874; +wire [31:0] zext_ln1265_20_fu_82074_p1; +reg [31:0] zext_ln1265_20_reg_94878; +wire [31:0] zext_ln276_4_fu_82078_p1; +reg [31:0] zext_ln276_4_reg_94884; +reg [27:0] tmp_80_reg_94895; +wire [7:0] tmp_81_fu_82131_p30; +reg [7:0] tmp_81_reg_95040; +wire [31:0] add_ln268_fu_82230_p2; +wire [31:0] add_ln276_28_fu_82236_p2; +reg [31:0] add_ln276_28_reg_95050; +reg [27:0] tmp_101_reg_95061; +wire [7:0] tmp_102_fu_82297_p30; +reg [7:0] tmp_102_reg_95206; +wire [7:0] add_ln703_7_fu_82359_p2; +reg [7:0] add_ln703_7_reg_95211; +wire [31:0] add_ln276_48_fu_82409_p2; +reg [31:0] add_ln276_48_reg_95219; +wire [0:0] icmp_ln268_4_fu_82403_p2; +wire [31:0] add_ln266_fu_82420_p2; +reg [27:0] tmp_156_reg_95235; +wire [7:0] tmp_157_fu_82476_p30; +reg [7:0] tmp_157_reg_95380; +wire [31:0] add_ln268_4_fu_82575_p2; +wire [31:0] add_ln276_27_fu_82592_p2; +reg [31:0] add_ln276_27_reg_95390; +wire [31:0] add_ln276_35_fu_82598_p2; +reg [31:0] add_ln276_35_reg_95396; +reg [27:0] tmp_117_reg_95407; +wire [7:0] tmp_116_fu_82659_p66; +reg [7:0] tmp_116_reg_95552; +wire [7:0] tmp_118_fu_82792_p30; +reg [7:0] tmp_118_reg_95557; +wire [7:0] add_ln703_8_fu_82854_p2; +reg [7:0] add_ln703_8_reg_95562; +wire [31:0] add_ln276_52_fu_82887_p2; +reg [31:0] add_ln276_52_reg_95570; +wire [0:0] icmp_ln268_5_fu_82881_p2; +wire [31:0] add_ln276_57_fu_82921_p2; +reg [31:0] add_ln276_57_reg_95579; +wire [0:0] icmp_ln266_4_fu_82904_p2; +wire [2:0] add_ln261_fu_82927_p2; +reg [27:0] tmp_175_reg_95595; +wire [7:0] tmp_176_fu_82983_p30; +reg [7:0] tmp_176_reg_95740; +wire [31:0] add_ln268_5_fu_83066_p2; +wire [31:0] add_ln276_60_fu_83072_p2; +reg [31:0] add_ln276_60_reg_95750; +wire [7:0] tmp_194_fu_83083_p66; +reg [7:0] tmp_194_reg_95756; +reg [27:0] tmp_195_reg_95766; +wire [7:0] tmp_196_fu_83266_p30; +reg [7:0] tmp_196_reg_95911; +wire [7:0] add_ln703_22_fu_83328_p2; +reg [7:0] add_ln703_22_reg_95916; +wire [31:0] add_ln276_71_fu_83361_p2; +reg [31:0] add_ln276_71_reg_95924; +wire [0:0] icmp_ln268_12_fu_83355_p2; +wire [31:0] add_ln266_4_fu_83372_p2; +reg [27:0] tmp_217_reg_95940; +wire [7:0] tmp_218_fu_83428_p30; +reg [7:0] tmp_218_reg_96085; +wire [31:0] add_ln268_12_fu_83511_p2; +wire [5:0] add_ln1265_fu_83540_p2; +reg [5:0] add_ln1265_reg_96098; +wire [0:0] icmp_ln261_2_fu_83525_p2; +wire [31:0] zext_ln1265_6_fu_83545_p1; +reg [31:0] zext_ln1265_6_reg_96102; +reg [5:0] acc_0_V_addr_56_reg_96108; +reg [5:0] acc_2_V_addr_56_reg_96114; +reg [5:0] acc_4_V_addr_56_reg_96120; +reg [5:0] acc_6_V_addr_56_reg_96126; +reg [5:0] acc_8_V_addr_56_reg_96132; +reg [5:0] acc_10_V_addr_56_reg_96138; +reg [5:0] acc_12_V_addr_56_reg_96144; +reg [5:0] acc_14_V_addr_56_reg_96150; +reg [5:0] acc_16_V_addr_56_reg_96156; +reg [5:0] acc_18_V_addr_56_reg_96162; +reg [5:0] acc_20_V_addr_56_reg_96168; +reg [5:0] acc_22_V_addr_56_reg_96174; +reg [5:0] acc_24_V_addr_56_reg_96180; +reg [5:0] acc_26_V_addr_56_reg_96186; +reg [5:0] acc_28_V_addr_56_reg_96192; +reg [5:0] acc_30_V_addr_56_reg_96198; +reg [5:0] acc_32_V_addr_56_reg_96204; +reg [5:0] acc_34_V_addr_56_reg_96210; +reg [5:0] acc_36_V_addr_56_reg_96216; +reg [5:0] acc_38_V_addr_56_reg_96222; +reg [5:0] acc_40_V_addr_56_reg_96228; +reg [5:0] acc_42_V_addr_56_reg_96234; +reg [5:0] acc_44_V_addr_56_reg_96240; +reg [5:0] acc_46_V_addr_56_reg_96246; +reg [5:0] acc_48_V_addr_56_reg_96252; +reg [5:0] acc_50_V_addr_56_reg_96258; +reg [5:0] acc_52_V_addr_56_reg_96264; +reg [5:0] acc_54_V_addr_56_reg_96270; +reg [5:0] acc_56_V_addr_56_reg_96276; +reg [5:0] acc_58_V_addr_56_reg_96282; +reg [5:0] acc_60_V_addr_56_reg_96288; +reg [5:0] acc_62_V_addr_56_reg_96294; +reg [5:0] acc_63_V_addr_58_reg_96300; +wire [31:0] zext_ln276_2_fu_83631_p1; +reg [31:0] zext_ln276_2_reg_96306; +reg [5:0] acc_61_V_addr_57_reg_96312; +reg [5:0] acc_59_V_addr_57_reg_96318; +reg [5:0] acc_57_V_addr_57_reg_96324; +reg [5:0] acc_55_V_addr_57_reg_96330; +reg [5:0] acc_53_V_addr_57_reg_96336; +reg [5:0] acc_51_V_addr_57_reg_96342; +reg [5:0] acc_49_V_addr_57_reg_96348; +reg [5:0] acc_47_V_addr_57_reg_96354; +reg [5:0] acc_45_V_addr_57_reg_96360; +reg [5:0] acc_43_V_addr_57_reg_96366; +reg [5:0] acc_41_V_addr_57_reg_96372; +reg [5:0] acc_39_V_addr_57_reg_96378; +reg [5:0] acc_37_V_addr_57_reg_96384; +reg [5:0] acc_35_V_addr_57_reg_96390; +reg [5:0] acc_33_V_addr_57_reg_96396; +reg [5:0] acc_31_V_addr_57_reg_96402; +reg [5:0] acc_29_V_addr_57_reg_96408; +reg [5:0] acc_27_V_addr_57_reg_96414; +reg [5:0] acc_25_V_addr_57_reg_96420; +reg [5:0] acc_23_V_addr_57_reg_96426; +reg [5:0] acc_21_V_addr_57_reg_96432; +reg [5:0] acc_19_V_addr_57_reg_96438; +reg [5:0] acc_17_V_addr_57_reg_96444; +reg [5:0] acc_15_V_addr_57_reg_96450; +reg [5:0] acc_13_V_addr_57_reg_96456; +reg [5:0] acc_11_V_addr_57_reg_96462; +reg [5:0] acc_9_V_addr_57_reg_96468; +reg [5:0] acc_7_V_addr_57_reg_96474; +reg [5:0] acc_5_V_addr_57_reg_96480; +reg [5:0] acc_3_V_addr_57_reg_96486; +reg [5:0] acc_1_V_addr_57_reg_96492; +wire [4:0] add_ln259_fu_83634_p2; +wire [31:0] add_ln276_13_fu_83651_p2; +reg [31:0] add_ln276_13_reg_96503; +wire [31:0] add_ln276_16_fu_83657_p2; +reg [31:0] add_ln276_16_reg_96509; +reg [27:0] tmp_72_reg_96520; +wire [7:0] tmp_71_fu_83718_p66; +reg [7:0] tmp_71_reg_96665; +wire [7:0] tmp_73_fu_83851_p30; +reg [7:0] tmp_73_reg_96670; +wire [7:0] add_ln703_2_fu_83913_p2; +reg [7:0] add_ln703_2_reg_96675; +wire [31:0] add_ln276_25_fu_83962_p2; +reg [31:0] add_ln276_25_reg_96683; +wire [0:0] icmp_ln268_2_fu_83956_p2; +wire [31:0] add_ln276_34_fu_83996_p2; +reg [31:0] add_ln276_34_reg_96692; +wire [0:0] icmp_ln266_2_fu_83979_p2; +wire [5:0] or_ln1265_4_fu_84025_p3; +reg [5:0] or_ln1265_4_reg_96698; +wire [31:0] zext_ln1265_28_fu_84033_p1; +reg [31:0] zext_ln1265_28_reg_96702; +wire [31:0] zext_ln276_6_fu_84037_p1; +reg [31:0] zext_ln276_6_reg_96708; +reg [27:0] tmp_97_reg_96719; +wire [7:0] tmp_98_fu_84090_p30; +reg [7:0] tmp_98_reg_96864; +wire [31:0] add_ln268_2_fu_84189_p2; +wire [31:0] add_ln276_42_fu_84195_p2; +reg [31:0] add_ln276_42_reg_96874; +wire [7:0] tmp_139_fu_84206_p66; +reg [7:0] tmp_139_reg_96880; +reg [27:0] tmp_140_reg_96890; +wire [7:0] tmp_141_fu_84389_p30; +reg [7:0] tmp_141_reg_97035; +wire [7:0] add_ln703_11_fu_84451_p2; +reg [7:0] add_ln703_11_reg_97040; +wire [31:0] add_ln276_55_fu_84500_p2; +reg [31:0] add_ln276_55_reg_97048; +wire [0:0] icmp_ln268_7_fu_84494_p2; +wire [31:0] add_ln266_2_fu_84511_p2; +reg [27:0] tmp_183_reg_97064; +wire [7:0] tmp_184_fu_84567_p30; +reg [7:0] tmp_184_reg_97209; +wire [31:0] add_ln268_7_fu_84666_p2; +wire [31:0] add_ln276_41_fu_84683_p2; +reg [31:0] add_ln276_41_reg_97219; +wire [31:0] add_ln276_47_fu_84689_p2; +reg [31:0] add_ln276_47_reg_97225; +reg [27:0] tmp_154_reg_97236; +wire [7:0] tmp_153_fu_84750_p66; +reg [7:0] tmp_153_reg_97381; +wire [7:0] tmp_155_fu_84883_p30; +reg [7:0] tmp_155_reg_97386; +wire [7:0] add_ln703_13_fu_84945_p2; +reg [7:0] add_ln703_13_reg_97391; +wire [31:0] add_ln276_59_fu_84977_p2; +reg [31:0] add_ln276_59_reg_97399; +wire [0:0] icmp_ln268_9_fu_84971_p2; +wire [31:0] add_ln276_65_fu_85011_p2; +reg [31:0] add_ln276_65_reg_97408; +wire [0:0] icmp_ln266_6_fu_84994_p2; +wire [2:0] add_ln261_2_fu_85017_p2; +reg [27:0] tmp_192_reg_97424; +wire [7:0] tmp_193_fu_85073_p30; +reg [7:0] tmp_193_reg_97569; +wire [31:0] add_ln268_9_fu_85155_p2; +wire [31:0] add_ln276_68_fu_85161_p2; +reg [31:0] add_ln276_68_reg_97579; +wire [7:0] tmp_211_fu_85172_p66; +reg [7:0] tmp_211_reg_97585; +reg [27:0] tmp_212_reg_97595; +wire [7:0] tmp_213_fu_85355_p30; +reg [7:0] tmp_213_reg_97740; +wire [7:0] add_ln703_26_fu_85417_p2; +reg [7:0] add_ln703_26_reg_97745; +wire [31:0] add_ln276_74_fu_85449_p2; +reg [31:0] add_ln276_74_reg_97753; +wire [0:0] icmp_ln268_14_fu_85443_p2; +wire [31:0] add_ln266_6_fu_85460_p2; +reg [27:0] tmp_236_reg_97769; +wire [7:0] tmp_231_fu_85516_p30; +reg [7:0] tmp_231_reg_97914; +wire [31:0] add_ln268_14_fu_85598_p2; +wire [5:0] add_ln279_3_fu_85643_p2; +reg [5:0] add_ln279_3_reg_97927; +wire [0:0] icmp_ln259_1_fu_85608_p2; +reg [5:0] acc_0_V_addr_52_reg_97933; +reg [5:0] acc_2_V_addr_52_reg_97939; +reg [5:0] acc_4_V_addr_52_reg_97945; +reg [5:0] acc_6_V_addr_52_reg_97951; +reg [5:0] acc_8_V_addr_52_reg_97957; +reg [5:0] acc_10_V_addr_52_reg_97963; +reg [5:0] acc_12_V_addr_52_reg_97969; +reg [5:0] acc_14_V_addr_52_reg_97975; +reg [5:0] acc_16_V_addr_52_reg_97981; +reg [5:0] acc_18_V_addr_52_reg_97987; +reg [5:0] acc_20_V_addr_52_reg_97993; +reg [5:0] acc_22_V_addr_52_reg_97999; +reg [5:0] acc_24_V_addr_52_reg_98005; +reg [5:0] acc_26_V_addr_52_reg_98011; +reg [5:0] acc_28_V_addr_52_reg_98017; +reg [5:0] acc_30_V_addr_52_reg_98023; +reg [5:0] acc_32_V_addr_52_reg_98029; +reg [5:0] acc_34_V_addr_52_reg_98035; +reg [5:0] acc_36_V_addr_52_reg_98041; +reg [5:0] acc_38_V_addr_52_reg_98047; +reg [5:0] acc_40_V_addr_52_reg_98053; +reg [5:0] acc_42_V_addr_52_reg_98059; +reg [5:0] acc_44_V_addr_52_reg_98065; +reg [5:0] acc_46_V_addr_52_reg_98071; +reg [5:0] acc_48_V_addr_52_reg_98077; +reg [5:0] acc_50_V_addr_52_reg_98083; +reg [5:0] acc_52_V_addr_52_reg_98089; +reg [5:0] acc_54_V_addr_52_reg_98095; +reg [5:0] acc_56_V_addr_52_reg_98101; +reg [5:0] acc_58_V_addr_52_reg_98107; +reg [5:0] acc_60_V_addr_52_reg_98113; +reg [5:0] acc_62_V_addr_52_reg_98119; +reg [5:0] acc_63_V_addr_53_reg_98125; +wire [16:0] grp_fu_90021_p3; +reg [16:0] add_ln276_1_reg_98131; +reg [5:0] acc_1_V_addr_53_reg_98137; +reg [5:0] acc_3_V_addr_53_reg_98143; +reg [5:0] acc_9_V_addr_53_reg_98149; +reg [5:0] acc_11_V_addr_53_reg_98155; +reg [5:0] acc_17_V_addr_53_reg_98161; +reg [5:0] acc_19_V_addr_53_reg_98167; +reg [5:0] acc_25_V_addr_53_reg_98173; +reg [5:0] acc_27_V_addr_53_reg_98179; +reg [5:0] acc_33_V_addr_53_reg_98185; +reg [5:0] acc_35_V_addr_53_reg_98191; +reg [5:0] acc_41_V_addr_53_reg_98197; +reg [5:0] acc_43_V_addr_53_reg_98203; +reg [5:0] acc_49_V_addr_53_reg_98209; +reg [5:0] acc_51_V_addr_53_reg_98215; +reg [5:0] acc_57_V_addr_53_reg_98221; +reg [5:0] acc_59_V_addr_53_reg_98227; +reg [5:0] acc_61_V_addr_53_reg_98233; +reg [5:0] acc_55_V_addr_53_reg_98239; +reg [5:0] acc_53_V_addr_53_reg_98245; +reg [5:0] acc_47_V_addr_53_reg_98251; +reg [5:0] acc_45_V_addr_53_reg_98257; +reg [5:0] acc_39_V_addr_53_reg_98263; +reg [5:0] acc_37_V_addr_53_reg_98269; +reg [5:0] acc_31_V_addr_53_reg_98275; +reg [5:0] acc_29_V_addr_53_reg_98281; +reg [5:0] acc_23_V_addr_53_reg_98287; +reg [5:0] acc_21_V_addr_53_reg_98293; +reg [5:0] acc_15_V_addr_53_reg_98299; +reg [5:0] acc_13_V_addr_53_reg_98305; +reg [5:0] acc_7_V_addr_53_reg_98311; +reg [5:0] acc_5_V_addr_53_reg_98317; +wire [4:0] add_ln257_fu_85730_p2; +wire [5:0] or_ln1265_1_fu_85755_p3; +reg [5:0] or_ln1265_1_reg_98331; +wire [0:0] icmp_ln261_1_fu_85740_p2; +wire [31:0] zext_ln1265_5_fu_85763_p1; +reg [31:0] zext_ln1265_5_reg_98335; +wire [31:0] zext_ln276_1_fu_85767_p1; +reg [31:0] zext_ln276_1_reg_98341; +wire [12:0] add_ln279_6_fu_85804_p2; +reg [12:0] add_ln279_6_reg_98347; +wire [5:0] add_ln279_7_fu_85809_p2; +reg [5:0] add_ln279_7_reg_98352; +wire [16:0] grp_fu_90036_p3; +reg [16:0] add_ln276_6_reg_98358; +reg [5:0] acc_5_V_addr_56_reg_98364; +reg [5:0] acc_7_V_addr_56_reg_98370; +reg [5:0] acc_13_V_addr_56_reg_98376; +reg [5:0] acc_15_V_addr_56_reg_98382; +reg [5:0] acc_21_V_addr_56_reg_98388; +reg [5:0] acc_23_V_addr_56_reg_98394; +reg [5:0] acc_29_V_addr_56_reg_98400; +reg [5:0] acc_31_V_addr_56_reg_98406; +reg [5:0] acc_37_V_addr_56_reg_98412; +reg [5:0] acc_39_V_addr_56_reg_98418; +reg [5:0] acc_45_V_addr_56_reg_98424; +reg [5:0] acc_47_V_addr_56_reg_98430; +reg [5:0] acc_53_V_addr_56_reg_98436; +reg [5:0] acc_55_V_addr_56_reg_98442; +reg [5:0] acc_61_V_addr_56_reg_98448; +reg [5:0] acc_63_V_addr_57_reg_98454; +reg [5:0] acc_62_V_addr_55_reg_98460; +reg [5:0] acc_60_V_addr_55_reg_98466; +reg [5:0] acc_59_V_addr_56_reg_98472; +reg [5:0] acc_58_V_addr_55_reg_98478; +reg [5:0] acc_57_V_addr_56_reg_98484; +reg [5:0] acc_56_V_addr_55_reg_98490; +reg [5:0] acc_54_V_addr_55_reg_98496; +reg [5:0] acc_52_V_addr_55_reg_98502; +reg [5:0] acc_51_V_addr_56_reg_98508; +reg [5:0] acc_50_V_addr_55_reg_98514; +reg [5:0] acc_49_V_addr_56_reg_98520; +reg [5:0] acc_48_V_addr_55_reg_98526; +reg [5:0] acc_46_V_addr_55_reg_98532; +reg [5:0] acc_44_V_addr_55_reg_98538; +reg [5:0] acc_43_V_addr_56_reg_98544; +reg [5:0] acc_42_V_addr_55_reg_98550; +reg [5:0] acc_41_V_addr_56_reg_98556; +reg [5:0] acc_40_V_addr_55_reg_98562; +reg [5:0] acc_38_V_addr_55_reg_98568; +reg [5:0] acc_36_V_addr_55_reg_98574; +reg [5:0] acc_35_V_addr_56_reg_98580; +reg [5:0] acc_34_V_addr_55_reg_98586; +reg [5:0] acc_33_V_addr_56_reg_98592; +reg [5:0] acc_32_V_addr_55_reg_98598; +reg [5:0] acc_30_V_addr_55_reg_98604; +reg [5:0] acc_28_V_addr_55_reg_98610; +reg [5:0] acc_27_V_addr_56_reg_98616; +reg [5:0] acc_26_V_addr_55_reg_98622; +reg [5:0] acc_25_V_addr_56_reg_98628; +reg [5:0] acc_24_V_addr_55_reg_98634; +reg [5:0] acc_22_V_addr_55_reg_98640; +reg [5:0] acc_20_V_addr_55_reg_98646; +reg [5:0] acc_19_V_addr_56_reg_98652; +reg [5:0] acc_18_V_addr_55_reg_98658; +reg [5:0] acc_17_V_addr_56_reg_98664; +reg [5:0] acc_16_V_addr_55_reg_98670; +reg [5:0] acc_14_V_addr_55_reg_98676; +reg [5:0] acc_12_V_addr_55_reg_98682; +reg [5:0] acc_11_V_addr_56_reg_98688; +reg [5:0] acc_10_V_addr_55_reg_98694; +reg [5:0] acc_9_V_addr_56_reg_98700; +reg [5:0] acc_8_V_addr_55_reg_98706; +reg [5:0] acc_6_V_addr_55_reg_98712; +reg [5:0] acc_4_V_addr_55_reg_98718; +reg [5:0] acc_3_V_addr_56_reg_98724; +reg [5:0] acc_2_V_addr_55_reg_98730; +reg [5:0] acc_1_V_addr_56_reg_98736; +reg [5:0] acc_0_V_addr_55_reg_98742; +wire [31:0] add_ln276_11_fu_85907_p2; +reg [31:0] add_ln276_11_reg_98748; +wire [31:0] add_ln276_15_fu_85913_p2; +reg [31:0] add_ln276_15_reg_98754; +reg [27:0] tmp_69_reg_98765; +wire [7:0] tmp_68_fu_85974_p66; +reg [7:0] tmp_68_reg_98910; +wire [7:0] tmp_70_fu_86107_p30; +reg [7:0] tmp_70_reg_98915; +wire [7:0] add_ln703_1_fu_86169_p2; +reg [7:0] add_ln703_1_reg_98920; +wire [31:0] add_ln276_24_fu_86218_p2; +reg [31:0] add_ln276_24_reg_98928; +wire [0:0] icmp_ln268_1_fu_86212_p2; +wire [31:0] add_ln276_31_fu_86252_p2; +reg [31:0] add_ln276_31_reg_98937; +wire [0:0] icmp_ln266_1_fu_86235_p2; +wire [5:0] or_ln1265_3_fu_86281_p3; +reg [5:0] or_ln1265_3_reg_98943; +wire [31:0] zext_ln1265_27_fu_86289_p1; +reg [31:0] zext_ln1265_27_reg_98947; +wire [31:0] zext_ln276_5_fu_86293_p1; +reg [31:0] zext_ln276_5_reg_98953; +reg [27:0] tmp_95_reg_98964; +wire [7:0] tmp_96_fu_86346_p30; +reg [7:0] tmp_96_reg_99109; +wire [31:0] add_ln268_1_fu_86445_p2; +wire [31:0] add_ln276_39_fu_86451_p2; +reg [31:0] add_ln276_39_reg_99119; +wire [7:0] tmp_135_fu_86462_p66; +reg [7:0] tmp_135_reg_99125; +reg [27:0] tmp_136_reg_99135; +wire [7:0] tmp_137_fu_86645_p30; +reg [7:0] tmp_137_reg_99280; +wire [7:0] add_ln703_10_fu_86707_p2; +reg [7:0] add_ln703_10_reg_99285; +wire [31:0] add_ln276_54_fu_86756_p2; +reg [31:0] add_ln276_54_reg_99293; +wire [0:0] icmp_ln268_6_fu_86750_p2; +wire [31:0] add_ln266_1_fu_86767_p2; +reg [27:0] tmp_181_reg_99309; +wire [7:0] tmp_182_fu_86823_p30; +reg [7:0] tmp_182_reg_99454; +wire [31:0] add_ln268_6_fu_86922_p2; +wire [31:0] add_ln276_38_fu_86939_p2; +reg [31:0] add_ln276_38_reg_99464; +wire [31:0] add_ln276_46_fu_86945_p2; +reg [31:0] add_ln276_46_reg_99470; +reg [27:0] tmp_151_reg_99481; +wire [7:0] tmp_150_fu_87006_p66; +reg [7:0] tmp_150_reg_99626; +wire [7:0] tmp_152_fu_87139_p30; +reg [7:0] tmp_152_reg_99631; +wire [7:0] add_ln703_12_fu_87201_p2; +reg [7:0] add_ln703_12_reg_99636; +wire [31:0] add_ln276_58_fu_87234_p2; +reg [31:0] add_ln276_58_reg_99644; +wire [0:0] icmp_ln268_8_fu_87228_p2; +wire [31:0] add_ln276_63_fu_87268_p2; +reg [31:0] add_ln276_63_reg_99653; +wire [0:0] icmp_ln266_5_fu_87251_p2; +wire [2:0] add_ln261_1_fu_87274_p2; +reg [27:0] tmp_190_reg_99669; +wire [7:0] tmp_191_fu_87330_p30; +reg [7:0] tmp_191_reg_99814; +wire [31:0] add_ln268_8_fu_87413_p2; +wire [31:0] add_ln276_67_fu_87419_p2; +reg [31:0] add_ln276_67_reg_99824; +wire [7:0] tmp_208_fu_87430_p66; +reg [7:0] tmp_208_reg_99830; +reg [27:0] tmp_209_reg_99840; +wire [7:0] tmp_210_fu_87613_p30; +reg [7:0] tmp_210_reg_99985; +wire [7:0] add_ln703_25_fu_87675_p2; +reg [7:0] add_ln703_25_reg_99990; +wire [31:0] add_ln276_73_fu_87708_p2; +reg [31:0] add_ln276_73_reg_99998; +wire [0:0] icmp_ln268_13_fu_87702_p2; +wire [31:0] add_ln266_5_fu_87719_p2; +reg [27:0] tmp_235_reg_100014; +wire [7:0] tmp_230_fu_87775_p30; +reg [7:0] tmp_230_reg_100159; +wire [31:0] add_ln268_13_fu_87858_p2; +wire [5:0] add_ln1265_1_fu_87887_p2; +reg [5:0] add_ln1265_1_reg_100172; +wire [0:0] icmp_ln261_3_fu_87872_p2; +wire [31:0] zext_ln1265_10_fu_87892_p1; +reg [31:0] zext_ln1265_10_reg_100176; +reg [5:0] acc_0_V_addr_58_reg_100182; +reg [5:0] acc_2_V_addr_58_reg_100188; +reg [5:0] acc_4_V_addr_58_reg_100194; +reg [5:0] acc_6_V_addr_58_reg_100200; +reg [5:0] acc_8_V_addr_58_reg_100206; +reg [5:0] acc_10_V_addr_58_reg_100212; +reg [5:0] acc_12_V_addr_58_reg_100218; +reg [5:0] acc_14_V_addr_58_reg_100224; +reg [5:0] acc_16_V_addr_58_reg_100230; +reg [5:0] acc_18_V_addr_58_reg_100236; +reg [5:0] acc_20_V_addr_58_reg_100242; +reg [5:0] acc_22_V_addr_58_reg_100248; +reg [5:0] acc_24_V_addr_58_reg_100254; +reg [5:0] acc_26_V_addr_58_reg_100260; +reg [5:0] acc_28_V_addr_58_reg_100266; +reg [5:0] acc_30_V_addr_58_reg_100272; +reg [5:0] acc_32_V_addr_58_reg_100278; +reg [5:0] acc_34_V_addr_58_reg_100284; +reg [5:0] acc_36_V_addr_58_reg_100290; +reg [5:0] acc_38_V_addr_58_reg_100296; +reg [5:0] acc_40_V_addr_58_reg_100302; +reg [5:0] acc_42_V_addr_58_reg_100308; +reg [5:0] acc_44_V_addr_58_reg_100314; +reg [5:0] acc_46_V_addr_58_reg_100320; +reg [5:0] acc_48_V_addr_58_reg_100326; +reg [5:0] acc_50_V_addr_58_reg_100332; +reg [5:0] acc_52_V_addr_58_reg_100338; +reg [5:0] acc_54_V_addr_58_reg_100344; +reg [5:0] acc_56_V_addr_58_reg_100350; +reg [5:0] acc_58_V_addr_58_reg_100356; +reg [5:0] acc_60_V_addr_58_reg_100362; +reg [5:0] acc_62_V_addr_58_reg_100368; +reg [5:0] acc_63_V_addr_60_reg_100374; +wire [31:0] zext_ln276_3_fu_87978_p1; +reg [31:0] zext_ln276_3_reg_100380; +reg [5:0] acc_61_V_addr_58_reg_100386; +reg [5:0] acc_59_V_addr_58_reg_100392; +reg [5:0] acc_57_V_addr_58_reg_100398; +reg [5:0] acc_55_V_addr_58_reg_100404; +reg [5:0] acc_53_V_addr_58_reg_100410; +reg [5:0] acc_51_V_addr_58_reg_100416; +reg [5:0] acc_49_V_addr_58_reg_100422; +reg [5:0] acc_47_V_addr_58_reg_100428; +reg [5:0] acc_45_V_addr_58_reg_100434; +reg [5:0] acc_43_V_addr_58_reg_100440; +reg [5:0] acc_41_V_addr_58_reg_100446; +reg [5:0] acc_39_V_addr_58_reg_100452; +reg [5:0] acc_37_V_addr_58_reg_100458; +reg [5:0] acc_35_V_addr_58_reg_100464; +reg [5:0] acc_33_V_addr_58_reg_100470; +reg [5:0] acc_31_V_addr_58_reg_100476; +reg [5:0] acc_29_V_addr_58_reg_100482; +reg [5:0] acc_27_V_addr_58_reg_100488; +reg [5:0] acc_25_V_addr_58_reg_100494; +reg [5:0] acc_23_V_addr_58_reg_100500; +reg [5:0] acc_21_V_addr_58_reg_100506; +reg [5:0] acc_19_V_addr_58_reg_100512; +reg [5:0] acc_17_V_addr_58_reg_100518; +reg [5:0] acc_15_V_addr_58_reg_100524; +reg [5:0] acc_13_V_addr_58_reg_100530; +reg [5:0] acc_11_V_addr_58_reg_100536; +reg [5:0] acc_9_V_addr_58_reg_100542; +reg [5:0] acc_7_V_addr_58_reg_100548; +reg [5:0] acc_5_V_addr_58_reg_100554; +reg [5:0] acc_3_V_addr_58_reg_100560; +reg [5:0] acc_1_V_addr_58_reg_100566; +wire [4:0] add_ln259_1_fu_87981_p2; +wire [31:0] add_ln276_18_fu_87998_p2; +reg [31:0] add_ln276_18_reg_100577; +wire [31:0] add_ln276_20_fu_88004_p2; +reg [31:0] add_ln276_20_reg_100583; +reg [27:0] tmp_86_reg_100594; +wire [7:0] tmp_85_fu_88065_p66; +reg [7:0] tmp_85_reg_100739; +wire [7:0] tmp_87_fu_88198_p30; +reg [7:0] tmp_87_reg_100744; +wire [7:0] add_ln703_4_fu_88260_p2; +reg [7:0] add_ln703_4_reg_100749; +wire [31:0] add_ln276_36_fu_88309_p2; +reg [31:0] add_ln276_36_reg_100757; +wire [0:0] icmp_ln268_3_fu_88303_p2; +wire [31:0] add_ln276_45_fu_88343_p2; +reg [31:0] add_ln276_45_reg_100766; +wire [0:0] icmp_ln266_3_fu_88326_p2; +wire [5:0] or_ln1265_5_fu_88372_p3; +reg [5:0] or_ln1265_5_reg_100772; +wire [31:0] zext_ln1265_37_fu_88380_p1; +reg [31:0] zext_ln1265_37_reg_100776; +wire [31:0] zext_ln276_7_fu_88384_p1; +reg [31:0] zext_ln276_7_reg_100782; +reg [27:0] tmp_132_reg_100793; +wire [7:0] tmp_133_fu_88437_p30; +reg [7:0] tmp_133_reg_100938; +wire [31:0] add_ln268_3_fu_88536_p2; +wire [31:0] add_ln276_51_fu_88542_p2; +reg [31:0] add_ln276_51_reg_100948; +wire [7:0] tmp_172_fu_88553_p66; +reg [7:0] tmp_172_reg_100954; +reg [27:0] tmp_173_reg_100964; +wire [7:0] tmp_174_fu_88736_p30; +reg [7:0] tmp_174_reg_101109; +wire [7:0] add_ln703_15_fu_88798_p2; +reg [7:0] add_ln703_15_reg_101114; +wire [31:0] add_ln276_61_fu_88847_p2; +reg [31:0] add_ln276_61_reg_101122; +wire [0:0] icmp_ln268_10_fu_88841_p2; +wire [31:0] add_ln266_3_fu_88858_p2; +reg [27:0] tmp_198_reg_101138; +wire [7:0] tmp_199_fu_88914_p30; +reg [7:0] tmp_199_reg_101283; +wire [31:0] add_ln268_10_fu_89013_p2; +wire [31:0] add_ln276_50_fu_89030_p2; +reg [31:0] add_ln276_50_reg_101293; +wire [31:0] add_ln276_53_fu_89036_p2; +reg [31:0] add_ln276_53_reg_101299; +reg [27:0] tmp_179_reg_101310; +wire [7:0] tmp_178_fu_89097_p66; +reg [7:0] tmp_178_reg_101455; +wire [7:0] tmp_180_fu_89230_p30; +reg [7:0] tmp_180_reg_101460; +wire [7:0] add_ln703_17_fu_89292_p2; +reg [7:0] add_ln703_17_reg_101465; +wire [31:0] add_ln276_66_fu_89324_p2; +reg [31:0] add_ln276_66_reg_101473; +wire [0:0] icmp_ln268_11_fu_89318_p2; +wire [31:0] add_ln276_70_fu_89358_p2; +reg [31:0] add_ln276_70_reg_101482; +wire [0:0] icmp_ln266_7_fu_89341_p2; +wire [2:0] add_ln261_3_fu_89364_p2; +reg [27:0] tmp_206_reg_101498; +wire [7:0] tmp_207_fu_89420_p30; +reg [7:0] tmp_207_reg_101643; +wire [31:0] add_ln268_11_fu_89502_p2; +wire [31:0] add_ln276_72_fu_89508_p2; +reg [31:0] add_ln276_72_reg_101653; +wire [7:0] tmp_227_fu_89519_p66; +reg [7:0] tmp_227_reg_101659; +reg [27:0] tmp_228_reg_101669; +wire [7:0] tmp_229_fu_89702_p30; +reg [7:0] tmp_229_reg_101814; +wire [7:0] add_ln703_28_fu_89764_p2; +reg [7:0] add_ln703_28_reg_101819; +wire [31:0] add_ln276_75_fu_89796_p2; +reg [31:0] add_ln276_75_reg_101827; +wire [0:0] icmp_ln268_15_fu_89790_p2; +wire [31:0] add_ln266_7_fu_89807_p2; +reg [27:0] tmp_240_reg_101843; +wire [7:0] tmp_234_fu_89863_p30; +reg [7:0] tmp_234_reg_101988; +wire [31:0] add_ln268_15_fu_89945_p2; +reg [11:0] mult_0_V_address0; +reg mult_0_V_ce0; +reg mult_0_V_we0; +reg [7:0] mult_0_V_d0; +wire [7:0] mult_0_V_q0; +reg [11:0] mult_1_V_address0; +reg mult_1_V_ce0; +reg mult_1_V_we0; +reg [7:0] mult_1_V_d0; +wire [7:0] mult_1_V_q0; +reg [11:0] mult_2_V_address0; +reg mult_2_V_ce0; +reg mult_2_V_we0; +reg [7:0] mult_2_V_d0; +wire [7:0] mult_2_V_q0; +reg [11:0] mult_3_V_address0; +reg mult_3_V_ce0; +reg mult_3_V_we0; +reg [7:0] mult_3_V_d0; +wire [7:0] mult_3_V_q0; +reg [11:0] mult_4_V_address0; +reg mult_4_V_ce0; +reg mult_4_V_we0; +reg [7:0] mult_4_V_d0; +wire [7:0] mult_4_V_q0; +reg [11:0] mult_5_V_address0; +reg mult_5_V_ce0; +reg mult_5_V_we0; +reg [7:0] mult_5_V_d0; +wire [7:0] mult_5_V_q0; +reg [11:0] mult_6_V_address0; +reg mult_6_V_ce0; +reg mult_6_V_we0; +reg [7:0] mult_6_V_d0; +wire [7:0] mult_6_V_q0; +reg [11:0] mult_7_V_address0; +reg mult_7_V_ce0; +reg mult_7_V_we0; +reg [7:0] mult_7_V_d0; +wire [7:0] mult_7_V_q0; +reg [11:0] mult_8_V_address0; +reg mult_8_V_ce0; +reg mult_8_V_we0; +reg [7:0] mult_8_V_d0; +wire [7:0] mult_8_V_q0; +reg [11:0] mult_9_V_address0; +reg mult_9_V_ce0; +reg mult_9_V_we0; +reg [7:0] mult_9_V_d0; +wire [7:0] mult_9_V_q0; +reg [11:0] mult_10_V_address0; +reg mult_10_V_ce0; +reg mult_10_V_we0; +reg [7:0] mult_10_V_d0; +wire [7:0] mult_10_V_q0; +reg [11:0] mult_11_V_address0; +reg mult_11_V_ce0; +reg mult_11_V_we0; +reg [7:0] mult_11_V_d0; +wire [7:0] mult_11_V_q0; +reg [11:0] mult_12_V_address0; +reg mult_12_V_ce0; +reg mult_12_V_we0; +reg [7:0] mult_12_V_d0; +wire [7:0] mult_12_V_q0; +reg [11:0] mult_13_V_address0; +reg mult_13_V_ce0; +reg mult_13_V_we0; +reg [7:0] mult_13_V_d0; +wire [7:0] mult_13_V_q0; +reg [11:0] mult_14_V_address0; +reg mult_14_V_ce0; +reg mult_14_V_we0; +reg [7:0] mult_14_V_d0; +wire [7:0] mult_14_V_q0; +reg [11:0] mult_15_V_address0; +reg mult_15_V_ce0; +reg mult_15_V_we0; +reg [7:0] mult_15_V_d0; +wire [7:0] mult_15_V_q0; +reg [11:0] mult_16_V_address0; +reg mult_16_V_ce0; +reg mult_16_V_we0; +reg [7:0] mult_16_V_d0; +wire [7:0] mult_16_V_q0; +reg [11:0] mult_17_V_address0; +reg mult_17_V_ce0; +reg mult_17_V_we0; +reg [7:0] mult_17_V_d0; +wire [7:0] mult_17_V_q0; +reg [11:0] mult_18_V_address0; +reg mult_18_V_ce0; +reg mult_18_V_we0; +reg [7:0] mult_18_V_d0; +wire [7:0] mult_18_V_q0; +reg [11:0] mult_19_V_address0; +reg mult_19_V_ce0; +reg mult_19_V_we0; +reg [7:0] mult_19_V_d0; +wire [7:0] mult_19_V_q0; +reg [11:0] mult_20_V_address0; +reg mult_20_V_ce0; +reg mult_20_V_we0; +reg [7:0] mult_20_V_d0; +wire [7:0] mult_20_V_q0; +reg [11:0] mult_21_V_address0; +reg mult_21_V_ce0; +reg mult_21_V_we0; +reg [7:0] mult_21_V_d0; +wire [7:0] mult_21_V_q0; +reg [11:0] mult_22_V_address0; +reg mult_22_V_ce0; +reg mult_22_V_we0; +reg [7:0] mult_22_V_d0; +wire [7:0] mult_22_V_q0; +reg [11:0] mult_23_V_address0; +reg mult_23_V_ce0; +reg mult_23_V_we0; +reg [7:0] mult_23_V_d0; +wire [7:0] mult_23_V_q0; +reg [11:0] mult_24_V_address0; +reg mult_24_V_ce0; +reg mult_24_V_we0; +reg [7:0] mult_24_V_d0; +wire [7:0] mult_24_V_q0; +reg [11:0] mult_25_V_address0; +reg mult_25_V_ce0; +reg mult_25_V_we0; +reg [7:0] mult_25_V_d0; +wire [7:0] mult_25_V_q0; +reg [11:0] mult_26_V_address0; +reg mult_26_V_ce0; +reg mult_26_V_we0; +reg [7:0] mult_26_V_d0; +wire [7:0] mult_26_V_q0; +reg [11:0] mult_27_V_address0; +reg mult_27_V_ce0; +reg mult_27_V_we0; +reg [7:0] mult_27_V_d0; +wire [7:0] mult_27_V_q0; +reg [5:0] acc_0_V_address0; +reg acc_0_V_ce0; +reg acc_0_V_we0; +reg [7:0] acc_0_V_d0; +wire [7:0] acc_0_V_q0; +reg [5:0] acc_0_V_address1; +reg acc_0_V_ce1; +reg acc_0_V_we1; +reg [7:0] acc_0_V_d1; +wire [7:0] acc_0_V_q1; +reg [5:0] acc_1_V_address0; +reg acc_1_V_ce0; +reg acc_1_V_we0; +reg [7:0] acc_1_V_d0; +wire [7:0] acc_1_V_q0; +reg [5:0] acc_1_V_address1; +reg acc_1_V_ce1; +reg acc_1_V_we1; +reg [7:0] acc_1_V_d1; +wire [7:0] acc_1_V_q1; +reg [5:0] acc_2_V_address0; +reg acc_2_V_ce0; +reg acc_2_V_we0; +reg [7:0] acc_2_V_d0; +wire [7:0] acc_2_V_q0; +reg [5:0] acc_2_V_address1; +reg acc_2_V_ce1; +reg acc_2_V_we1; +reg [7:0] acc_2_V_d1; +wire [7:0] acc_2_V_q1; +reg [5:0] acc_3_V_address0; +reg acc_3_V_ce0; +reg acc_3_V_we0; +reg [7:0] acc_3_V_d0; +wire [7:0] acc_3_V_q0; +reg [5:0] acc_3_V_address1; +reg acc_3_V_ce1; +reg acc_3_V_we1; +reg [7:0] acc_3_V_d1; +wire [7:0] acc_3_V_q1; +reg [5:0] acc_4_V_address0; +reg acc_4_V_ce0; +reg acc_4_V_we0; +reg [7:0] acc_4_V_d0; +wire [7:0] acc_4_V_q0; +reg [5:0] acc_4_V_address1; +reg acc_4_V_ce1; +reg acc_4_V_we1; +reg [7:0] acc_4_V_d1; +wire [7:0] acc_4_V_q1; +reg [5:0] acc_5_V_address0; +reg acc_5_V_ce0; +reg acc_5_V_we0; +reg [7:0] acc_5_V_d0; +wire [7:0] acc_5_V_q0; +reg [5:0] acc_5_V_address1; +reg acc_5_V_ce1; +reg acc_5_V_we1; +reg [7:0] acc_5_V_d1; +wire [7:0] acc_5_V_q1; +reg [5:0] acc_6_V_address0; +reg acc_6_V_ce0; +reg acc_6_V_we0; +reg [7:0] acc_6_V_d0; +wire [7:0] acc_6_V_q0; +reg [5:0] acc_6_V_address1; +reg acc_6_V_ce1; +reg acc_6_V_we1; +reg [7:0] acc_6_V_d1; +wire [7:0] acc_6_V_q1; +reg [5:0] acc_7_V_address0; +reg acc_7_V_ce0; +reg acc_7_V_we0; +reg [7:0] acc_7_V_d0; +wire [7:0] acc_7_V_q0; +reg [5:0] acc_7_V_address1; +reg acc_7_V_ce1; +reg acc_7_V_we1; +reg [7:0] acc_7_V_d1; +wire [7:0] acc_7_V_q1; +reg [5:0] acc_8_V_address0; +reg acc_8_V_ce0; +reg acc_8_V_we0; +reg [7:0] acc_8_V_d0; +wire [7:0] acc_8_V_q0; +reg [5:0] acc_8_V_address1; +reg acc_8_V_ce1; +reg acc_8_V_we1; +reg [7:0] acc_8_V_d1; +wire [7:0] acc_8_V_q1; +reg [5:0] acc_9_V_address0; +reg acc_9_V_ce0; +reg acc_9_V_we0; +reg [7:0] acc_9_V_d0; +wire [7:0] acc_9_V_q0; +reg [5:0] acc_9_V_address1; +reg acc_9_V_ce1; +reg acc_9_V_we1; +reg [7:0] acc_9_V_d1; +wire [7:0] acc_9_V_q1; +reg [5:0] acc_10_V_address0; +reg acc_10_V_ce0; +reg acc_10_V_we0; +reg [7:0] acc_10_V_d0; +wire [7:0] acc_10_V_q0; +reg [5:0] acc_10_V_address1; +reg acc_10_V_ce1; +reg acc_10_V_we1; +reg [7:0] acc_10_V_d1; +wire [7:0] acc_10_V_q1; +reg [5:0] acc_11_V_address0; +reg acc_11_V_ce0; +reg acc_11_V_we0; +reg [7:0] acc_11_V_d0; +wire [7:0] acc_11_V_q0; +reg [5:0] acc_11_V_address1; +reg acc_11_V_ce1; +reg acc_11_V_we1; +reg [7:0] acc_11_V_d1; +wire [7:0] acc_11_V_q1; +reg [5:0] acc_12_V_address0; +reg acc_12_V_ce0; +reg acc_12_V_we0; +reg [7:0] acc_12_V_d0; +wire [7:0] acc_12_V_q0; +reg [5:0] acc_12_V_address1; +reg acc_12_V_ce1; +reg acc_12_V_we1; +reg [7:0] acc_12_V_d1; +wire [7:0] acc_12_V_q1; +reg [5:0] acc_13_V_address0; +reg acc_13_V_ce0; +reg acc_13_V_we0; +reg [7:0] acc_13_V_d0; +wire [7:0] acc_13_V_q0; +reg [5:0] acc_13_V_address1; +reg acc_13_V_ce1; +reg acc_13_V_we1; +reg [7:0] acc_13_V_d1; +wire [7:0] acc_13_V_q1; +reg [5:0] acc_14_V_address0; +reg acc_14_V_ce0; +reg acc_14_V_we0; +reg [7:0] acc_14_V_d0; +wire [7:0] acc_14_V_q0; +reg [5:0] acc_14_V_address1; +reg acc_14_V_ce1; +reg acc_14_V_we1; +reg [7:0] acc_14_V_d1; +wire [7:0] acc_14_V_q1; +reg [5:0] acc_15_V_address0; +reg acc_15_V_ce0; +reg acc_15_V_we0; +reg [7:0] acc_15_V_d0; +wire [7:0] acc_15_V_q0; +reg [5:0] acc_15_V_address1; +reg acc_15_V_ce1; +reg acc_15_V_we1; +reg [7:0] acc_15_V_d1; +wire [7:0] acc_15_V_q1; +reg [5:0] acc_16_V_address0; +reg acc_16_V_ce0; +reg acc_16_V_we0; +reg [7:0] acc_16_V_d0; +wire [7:0] acc_16_V_q0; +reg [5:0] acc_16_V_address1; +reg acc_16_V_ce1; +reg acc_16_V_we1; +reg [7:0] acc_16_V_d1; +wire [7:0] acc_16_V_q1; +reg [5:0] acc_17_V_address0; +reg acc_17_V_ce0; +reg acc_17_V_we0; +reg [7:0] acc_17_V_d0; +wire [7:0] acc_17_V_q0; +reg [5:0] acc_17_V_address1; +reg acc_17_V_ce1; +reg acc_17_V_we1; +reg [7:0] acc_17_V_d1; +wire [7:0] acc_17_V_q1; +reg [5:0] acc_18_V_address0; +reg acc_18_V_ce0; +reg acc_18_V_we0; +reg [7:0] acc_18_V_d0; +wire [7:0] acc_18_V_q0; +reg [5:0] acc_18_V_address1; +reg acc_18_V_ce1; +reg acc_18_V_we1; +reg [7:0] acc_18_V_d1; +wire [7:0] acc_18_V_q1; +reg [5:0] acc_19_V_address0; +reg acc_19_V_ce0; +reg acc_19_V_we0; +reg [7:0] acc_19_V_d0; +wire [7:0] acc_19_V_q0; +reg [5:0] acc_19_V_address1; +reg acc_19_V_ce1; +reg acc_19_V_we1; +reg [7:0] acc_19_V_d1; +wire [7:0] acc_19_V_q1; +reg [5:0] acc_20_V_address0; +reg acc_20_V_ce0; +reg acc_20_V_we0; +reg [7:0] acc_20_V_d0; +wire [7:0] acc_20_V_q0; +reg [5:0] acc_20_V_address1; +reg acc_20_V_ce1; +reg acc_20_V_we1; +reg [7:0] acc_20_V_d1; +wire [7:0] acc_20_V_q1; +reg [5:0] acc_21_V_address0; +reg acc_21_V_ce0; +reg acc_21_V_we0; +reg [7:0] acc_21_V_d0; +wire [7:0] acc_21_V_q0; +reg [5:0] acc_21_V_address1; +reg acc_21_V_ce1; +reg acc_21_V_we1; +reg [7:0] acc_21_V_d1; +wire [7:0] acc_21_V_q1; +reg [5:0] acc_22_V_address0; +reg acc_22_V_ce0; +reg acc_22_V_we0; +reg [7:0] acc_22_V_d0; +wire [7:0] acc_22_V_q0; +reg [5:0] acc_22_V_address1; +reg acc_22_V_ce1; +reg acc_22_V_we1; +reg [7:0] acc_22_V_d1; +wire [7:0] acc_22_V_q1; +reg [5:0] acc_23_V_address0; +reg acc_23_V_ce0; +reg acc_23_V_we0; +reg [7:0] acc_23_V_d0; +wire [7:0] acc_23_V_q0; +reg [5:0] acc_23_V_address1; +reg acc_23_V_ce1; +reg acc_23_V_we1; +reg [7:0] acc_23_V_d1; +wire [7:0] acc_23_V_q1; +reg [5:0] acc_24_V_address0; +reg acc_24_V_ce0; +reg acc_24_V_we0; +reg [7:0] acc_24_V_d0; +wire [7:0] acc_24_V_q0; +reg [5:0] acc_24_V_address1; +reg acc_24_V_ce1; +reg acc_24_V_we1; +reg [7:0] acc_24_V_d1; +wire [7:0] acc_24_V_q1; +reg [5:0] acc_25_V_address0; +reg acc_25_V_ce0; +reg acc_25_V_we0; +reg [7:0] acc_25_V_d0; +wire [7:0] acc_25_V_q0; +reg [5:0] acc_25_V_address1; +reg acc_25_V_ce1; +reg acc_25_V_we1; +reg [7:0] acc_25_V_d1; +wire [7:0] acc_25_V_q1; +reg [5:0] acc_26_V_address0; +reg acc_26_V_ce0; +reg acc_26_V_we0; +reg [7:0] acc_26_V_d0; +wire [7:0] acc_26_V_q0; +reg [5:0] acc_26_V_address1; +reg acc_26_V_ce1; +reg acc_26_V_we1; +reg [7:0] acc_26_V_d1; +wire [7:0] acc_26_V_q1; +reg [5:0] acc_27_V_address0; +reg acc_27_V_ce0; +reg acc_27_V_we0; +reg [7:0] acc_27_V_d0; +wire [7:0] acc_27_V_q0; +reg [5:0] acc_27_V_address1; +reg acc_27_V_ce1; +reg acc_27_V_we1; +reg [7:0] acc_27_V_d1; +wire [7:0] acc_27_V_q1; +reg [5:0] acc_28_V_address0; +reg acc_28_V_ce0; +reg acc_28_V_we0; +reg [7:0] acc_28_V_d0; +wire [7:0] acc_28_V_q0; +reg [5:0] acc_28_V_address1; +reg acc_28_V_ce1; +reg acc_28_V_we1; +reg [7:0] acc_28_V_d1; +wire [7:0] acc_28_V_q1; +reg [5:0] acc_29_V_address0; +reg acc_29_V_ce0; +reg acc_29_V_we0; +reg [7:0] acc_29_V_d0; +wire [7:0] acc_29_V_q0; +reg [5:0] acc_29_V_address1; +reg acc_29_V_ce1; +reg acc_29_V_we1; +reg [7:0] acc_29_V_d1; +wire [7:0] acc_29_V_q1; +reg [5:0] acc_30_V_address0; +reg acc_30_V_ce0; +reg acc_30_V_we0; +reg [7:0] acc_30_V_d0; +wire [7:0] acc_30_V_q0; +reg [5:0] acc_30_V_address1; +reg acc_30_V_ce1; +reg acc_30_V_we1; +reg [7:0] acc_30_V_d1; +wire [7:0] acc_30_V_q1; +reg [5:0] acc_31_V_address0; +reg acc_31_V_ce0; +reg acc_31_V_we0; +reg [7:0] acc_31_V_d0; +wire [7:0] acc_31_V_q0; +reg [5:0] acc_31_V_address1; +reg acc_31_V_ce1; +reg acc_31_V_we1; +reg [7:0] acc_31_V_d1; +wire [7:0] acc_31_V_q1; +reg [5:0] acc_32_V_address0; +reg acc_32_V_ce0; +reg acc_32_V_we0; +reg [7:0] acc_32_V_d0; +wire [7:0] acc_32_V_q0; +reg [5:0] acc_32_V_address1; +reg acc_32_V_ce1; +reg acc_32_V_we1; +reg [7:0] acc_32_V_d1; +wire [7:0] acc_32_V_q1; +reg [5:0] acc_33_V_address0; +reg acc_33_V_ce0; +reg acc_33_V_we0; +reg [7:0] acc_33_V_d0; +wire [7:0] acc_33_V_q0; +reg [5:0] acc_33_V_address1; +reg acc_33_V_ce1; +reg acc_33_V_we1; +reg [7:0] acc_33_V_d1; +wire [7:0] acc_33_V_q1; +reg [5:0] acc_34_V_address0; +reg acc_34_V_ce0; +reg acc_34_V_we0; +reg [7:0] acc_34_V_d0; +wire [7:0] acc_34_V_q0; +reg [5:0] acc_34_V_address1; +reg acc_34_V_ce1; +reg acc_34_V_we1; +reg [7:0] acc_34_V_d1; +wire [7:0] acc_34_V_q1; +reg [5:0] acc_35_V_address0; +reg acc_35_V_ce0; +reg acc_35_V_we0; +reg [7:0] acc_35_V_d0; +wire [7:0] acc_35_V_q0; +reg [5:0] acc_35_V_address1; +reg acc_35_V_ce1; +reg acc_35_V_we1; +reg [7:0] acc_35_V_d1; +wire [7:0] acc_35_V_q1; +reg [5:0] acc_36_V_address0; +reg acc_36_V_ce0; +reg acc_36_V_we0; +reg [7:0] acc_36_V_d0; +wire [7:0] acc_36_V_q0; +reg [5:0] acc_36_V_address1; +reg acc_36_V_ce1; +reg acc_36_V_we1; +reg [7:0] acc_36_V_d1; +wire [7:0] acc_36_V_q1; +reg [5:0] acc_37_V_address0; +reg acc_37_V_ce0; +reg acc_37_V_we0; +reg [7:0] acc_37_V_d0; +wire [7:0] acc_37_V_q0; +reg [5:0] acc_37_V_address1; +reg acc_37_V_ce1; +reg acc_37_V_we1; +reg [7:0] acc_37_V_d1; +wire [7:0] acc_37_V_q1; +reg [5:0] acc_38_V_address0; +reg acc_38_V_ce0; +reg acc_38_V_we0; +reg [7:0] acc_38_V_d0; +wire [7:0] acc_38_V_q0; +reg [5:0] acc_38_V_address1; +reg acc_38_V_ce1; +reg acc_38_V_we1; +reg [7:0] acc_38_V_d1; +wire [7:0] acc_38_V_q1; +reg [5:0] acc_39_V_address0; +reg acc_39_V_ce0; +reg acc_39_V_we0; +reg [7:0] acc_39_V_d0; +wire [7:0] acc_39_V_q0; +reg [5:0] acc_39_V_address1; +reg acc_39_V_ce1; +reg acc_39_V_we1; +reg [7:0] acc_39_V_d1; +wire [7:0] acc_39_V_q1; +reg [5:0] acc_40_V_address0; +reg acc_40_V_ce0; +reg acc_40_V_we0; +reg [7:0] acc_40_V_d0; +wire [7:0] acc_40_V_q0; +reg [5:0] acc_40_V_address1; +reg acc_40_V_ce1; +reg acc_40_V_we1; +reg [7:0] acc_40_V_d1; +wire [7:0] acc_40_V_q1; +reg [5:0] acc_41_V_address0; +reg acc_41_V_ce0; +reg acc_41_V_we0; +reg [7:0] acc_41_V_d0; +wire [7:0] acc_41_V_q0; +reg [5:0] acc_41_V_address1; +reg acc_41_V_ce1; +reg acc_41_V_we1; +reg [7:0] acc_41_V_d1; +wire [7:0] acc_41_V_q1; +reg [5:0] acc_42_V_address0; +reg acc_42_V_ce0; +reg acc_42_V_we0; +reg [7:0] acc_42_V_d0; +wire [7:0] acc_42_V_q0; +reg [5:0] acc_42_V_address1; +reg acc_42_V_ce1; +reg acc_42_V_we1; +reg [7:0] acc_42_V_d1; +wire [7:0] acc_42_V_q1; +reg [5:0] acc_43_V_address0; +reg acc_43_V_ce0; +reg acc_43_V_we0; +reg [7:0] acc_43_V_d0; +wire [7:0] acc_43_V_q0; +reg [5:0] acc_43_V_address1; +reg acc_43_V_ce1; +reg acc_43_V_we1; +reg [7:0] acc_43_V_d1; +wire [7:0] acc_43_V_q1; +reg [5:0] acc_44_V_address0; +reg acc_44_V_ce0; +reg acc_44_V_we0; +reg [7:0] acc_44_V_d0; +wire [7:0] acc_44_V_q0; +reg [5:0] acc_44_V_address1; +reg acc_44_V_ce1; +reg acc_44_V_we1; +reg [7:0] acc_44_V_d1; +wire [7:0] acc_44_V_q1; +reg [5:0] acc_45_V_address0; +reg acc_45_V_ce0; +reg acc_45_V_we0; +reg [7:0] acc_45_V_d0; +wire [7:0] acc_45_V_q0; +reg [5:0] acc_45_V_address1; +reg acc_45_V_ce1; +reg acc_45_V_we1; +reg [7:0] acc_45_V_d1; +wire [7:0] acc_45_V_q1; +reg [5:0] acc_46_V_address0; +reg acc_46_V_ce0; +reg acc_46_V_we0; +reg [7:0] acc_46_V_d0; +wire [7:0] acc_46_V_q0; +reg [5:0] acc_46_V_address1; +reg acc_46_V_ce1; +reg acc_46_V_we1; +reg [7:0] acc_46_V_d1; +wire [7:0] acc_46_V_q1; +reg [5:0] acc_47_V_address0; +reg acc_47_V_ce0; +reg acc_47_V_we0; +reg [7:0] acc_47_V_d0; +wire [7:0] acc_47_V_q0; +reg [5:0] acc_47_V_address1; +reg acc_47_V_ce1; +reg acc_47_V_we1; +reg [7:0] acc_47_V_d1; +wire [7:0] acc_47_V_q1; +reg [5:0] acc_48_V_address0; +reg acc_48_V_ce0; +reg acc_48_V_we0; +reg [7:0] acc_48_V_d0; +wire [7:0] acc_48_V_q0; +reg [5:0] acc_48_V_address1; +reg acc_48_V_ce1; +reg acc_48_V_we1; +reg [7:0] acc_48_V_d1; +wire [7:0] acc_48_V_q1; +reg [5:0] acc_49_V_address0; +reg acc_49_V_ce0; +reg acc_49_V_we0; +reg [7:0] acc_49_V_d0; +wire [7:0] acc_49_V_q0; +reg [5:0] acc_49_V_address1; +reg acc_49_V_ce1; +reg acc_49_V_we1; +reg [7:0] acc_49_V_d1; +wire [7:0] acc_49_V_q1; +reg [5:0] acc_50_V_address0; +reg acc_50_V_ce0; +reg acc_50_V_we0; +reg [7:0] acc_50_V_d0; +wire [7:0] acc_50_V_q0; +reg [5:0] acc_50_V_address1; +reg acc_50_V_ce1; +reg acc_50_V_we1; +reg [7:0] acc_50_V_d1; +wire [7:0] acc_50_V_q1; +reg [5:0] acc_51_V_address0; +reg acc_51_V_ce0; +reg acc_51_V_we0; +reg [7:0] acc_51_V_d0; +wire [7:0] acc_51_V_q0; +reg [5:0] acc_51_V_address1; +reg acc_51_V_ce1; +reg acc_51_V_we1; +reg [7:0] acc_51_V_d1; +wire [7:0] acc_51_V_q1; +reg [5:0] acc_52_V_address0; +reg acc_52_V_ce0; +reg acc_52_V_we0; +reg [7:0] acc_52_V_d0; +wire [7:0] acc_52_V_q0; +reg [5:0] acc_52_V_address1; +reg acc_52_V_ce1; +reg acc_52_V_we1; +reg [7:0] acc_52_V_d1; +wire [7:0] acc_52_V_q1; +reg [5:0] acc_53_V_address0; +reg acc_53_V_ce0; +reg acc_53_V_we0; +reg [7:0] acc_53_V_d0; +wire [7:0] acc_53_V_q0; +reg [5:0] acc_53_V_address1; +reg acc_53_V_ce1; +reg acc_53_V_we1; +reg [7:0] acc_53_V_d1; +wire [7:0] acc_53_V_q1; +reg [5:0] acc_54_V_address0; +reg acc_54_V_ce0; +reg acc_54_V_we0; +reg [7:0] acc_54_V_d0; +wire [7:0] acc_54_V_q0; +reg [5:0] acc_54_V_address1; +reg acc_54_V_ce1; +reg acc_54_V_we1; +reg [7:0] acc_54_V_d1; +wire [7:0] acc_54_V_q1; +reg [5:0] acc_55_V_address0; +reg acc_55_V_ce0; +reg acc_55_V_we0; +reg [7:0] acc_55_V_d0; +wire [7:0] acc_55_V_q0; +reg [5:0] acc_55_V_address1; +reg acc_55_V_ce1; +reg acc_55_V_we1; +reg [7:0] acc_55_V_d1; +wire [7:0] acc_55_V_q1; +reg [5:0] acc_56_V_address0; +reg acc_56_V_ce0; +reg acc_56_V_we0; +reg [7:0] acc_56_V_d0; +wire [7:0] acc_56_V_q0; +reg [5:0] acc_56_V_address1; +reg acc_56_V_ce1; +reg acc_56_V_we1; +reg [7:0] acc_56_V_d1; +wire [7:0] acc_56_V_q1; +reg [5:0] acc_57_V_address0; +reg acc_57_V_ce0; +reg acc_57_V_we0; +reg [7:0] acc_57_V_d0; +wire [7:0] acc_57_V_q0; +reg [5:0] acc_57_V_address1; +reg acc_57_V_ce1; +reg acc_57_V_we1; +reg [7:0] acc_57_V_d1; +wire [7:0] acc_57_V_q1; +reg [5:0] acc_58_V_address0; +reg acc_58_V_ce0; +reg acc_58_V_we0; +reg [7:0] acc_58_V_d0; +wire [7:0] acc_58_V_q0; +reg [5:0] acc_58_V_address1; +reg acc_58_V_ce1; +reg acc_58_V_we1; +reg [7:0] acc_58_V_d1; +wire [7:0] acc_58_V_q1; +reg [5:0] acc_59_V_address0; +reg acc_59_V_ce0; +reg acc_59_V_we0; +reg [7:0] acc_59_V_d0; +wire [7:0] acc_59_V_q0; +reg [5:0] acc_59_V_address1; +reg acc_59_V_ce1; +reg acc_59_V_we1; +reg [7:0] acc_59_V_d1; +wire [7:0] acc_59_V_q1; +reg [5:0] acc_60_V_address0; +reg acc_60_V_ce0; +reg acc_60_V_we0; +reg [7:0] acc_60_V_d0; +wire [7:0] acc_60_V_q0; +reg [5:0] acc_60_V_address1; +reg acc_60_V_ce1; +reg acc_60_V_we1; +reg [7:0] acc_60_V_d1; +wire [7:0] acc_60_V_q1; +reg [5:0] acc_61_V_address0; +reg acc_61_V_ce0; +reg acc_61_V_we0; +reg [7:0] acc_61_V_d0; +wire [7:0] acc_61_V_q0; +reg [5:0] acc_61_V_address1; +reg acc_61_V_ce1; +reg acc_61_V_we1; +reg [7:0] acc_61_V_d1; +wire [7:0] acc_61_V_q1; +reg [5:0] acc_62_V_address0; +reg acc_62_V_ce0; +reg acc_62_V_we0; +reg [7:0] acc_62_V_d0; +wire [7:0] acc_62_V_q0; +reg [5:0] acc_62_V_address1; +reg acc_62_V_ce1; +reg acc_62_V_we1; +reg [7:0] acc_62_V_d1; +wire [7:0] acc_62_V_q1; +reg [5:0] acc_63_V_address0; +reg acc_63_V_ce0; +reg acc_63_V_we0; +reg [7:0] acc_63_V_d0; +wire [7:0] acc_63_V_q0; +reg [5:0] acc_63_V_address1; +reg acc_63_V_ce1; +reg acc_63_V_we1; +reg [7:0] acc_63_V_d1; +wire [7:0] acc_63_V_q1; +reg [4:0] oh_0_0_reg_72639; +reg [4:0] ow_0_0_0_reg_72651; +reg [2:0] ff_0_0_0_reg_72663; +reg [6:0] phi_mul_reg_72675; +reg [31:0] fh_0_0_0_0_0_reg_72686; +reg [31:0] fw_0_0_0_0_0_0_reg_72698; +reg [31:0] fw_0_0_0_0_1_0_reg_72710; +reg [2:0] ff_0_0_1_reg_72722; +reg [6:0] phi_mul104991_reg_72734; +reg [31:0] fh_0_0_0_1_0_reg_72745; +reg [31:0] fw_0_0_0_1_0_0_reg_72757; +reg [31:0] fw_0_0_0_1_1_0_reg_72769; +reg [4:0] ow_0_1_0_reg_72781; +reg [2:0] ff_0_1_0_reg_72793; +reg [6:0] phi_mul105001_reg_72805; +reg [31:0] fh_0_0_1_0_0_reg_72816; +reg [31:0] fw_0_0_1_0_0_0_reg_72828; +reg [31:0] fw_0_0_1_0_1_0_reg_72840; +reg [2:0] ff_0_1_1_reg_72852; +reg [6:0] phi_mul105011_reg_72864; +reg [31:0] fh_0_0_1_1_0_reg_72875; +reg [31:0] fw_0_0_1_1_0_0_reg_72887; +reg [31:0] fw_0_0_1_1_1_0_reg_72899; +reg [4:0] oh2_0_0_reg_72911; +reg [4:0] ow3_0_0_0_reg_72923; +reg [2:0] ff4_0_0_0_0_reg_72935; +reg [2:0] ff4_0_0_1_0_reg_72947; +reg [4:0] ow3_0_1_0_reg_72959; +reg [2:0] ff4_0_1_0_0_reg_72971; +reg [2:0] ff4_0_1_1_0_reg_72983; +reg [4:0] oh5_0_0_reg_72995; +reg [4:0] ow6_0_0_0_reg_73007; +reg [2:0] ff7_0_0_0_0_reg_73019; +reg [31:0] fh9_0_0_0_0_0_0_reg_73031; +reg [31:0] fw10_0_0_0_0_0_0_0_reg_73043; +reg [31:0] fw10_0_0_0_0_0_1_0_reg_73055; +reg [31:0] fh9_0_0_0_0_1_0_reg_73067; +reg [31:0] fw10_0_0_0_0_1_0_0_reg_73079; +reg [31:0] fw10_0_0_0_0_1_1_0_reg_73091; +reg [2:0] ff7_0_0_1_0_reg_73103; +reg [31:0] fh9_0_0_0_1_0_0_reg_73115; +reg [31:0] fw10_0_0_0_1_0_0_0_reg_73127; +reg [31:0] fw10_0_0_0_1_0_1_0_reg_73139; +reg [31:0] fh9_0_0_0_1_1_0_reg_73151; +reg [31:0] fw10_0_0_0_1_1_0_0_reg_73163; +reg [31:0] fw10_0_0_0_1_1_1_0_reg_73175; +reg [4:0] ow6_0_1_0_reg_73187; +reg [2:0] ff7_0_1_0_0_reg_73199; +reg [31:0] fh9_0_0_1_0_0_0_reg_73211; +reg [31:0] fw10_0_0_1_0_0_0_0_reg_73223; +reg [31:0] fw10_0_0_1_0_0_1_0_reg_73235; +reg [31:0] fh9_0_0_1_0_1_0_reg_73247; +reg [31:0] fw10_0_0_1_0_1_0_0_reg_73259; +reg [31:0] fw10_0_0_1_0_1_1_0_reg_73271; +reg [2:0] ff7_0_1_1_0_reg_73283; +reg [31:0] fh9_0_0_1_1_0_0_reg_73295; +reg [31:0] fw10_0_0_1_1_0_0_0_reg_73307; +reg [31:0] fw10_0_0_1_1_0_1_0_reg_73319; +reg [31:0] fh9_0_0_1_1_1_0_reg_73331; +reg [31:0] fw10_0_0_1_1_1_0_0_reg_73343; +reg [31:0] fw10_0_0_1_1_1_1_0_reg_73355; +wire [63:0] zext_ln232_fu_73976_p1; +wire [63:0] zext_ln1116_fu_74020_p1; +wire [63:0] zext_ln203_14_fu_74192_p1; +wire [63:0] zext_ln1116_4_fu_74315_p1; +wire [63:0] zext_ln232_4_fu_74295_p1; +wire [63:0] zext_ln203_12_fu_74449_p1; +wire [63:0] zext_ln203_31_fu_74662_p1; +wire [63:0] zext_ln203_29_fu_74722_p1; +wire [63:0] zext_ln232_7_fu_74801_p1; +wire [63:0] zext_ln1116_7_fu_74845_p1; +wire [63:0] zext_ln203_43_fu_75016_p1; +wire [63:0] zext_ln1116_12_fu_75143_p1; +wire [63:0] zext_ln232_12_fu_75119_p1; +wire [63:0] zext_ln203_41_fu_75194_p1; +wire [63:0] zext_ln203_63_fu_75385_p1; +wire [63:0] zext_ln203_61_fu_75445_p1; +wire [63:0] zext_ln232_2_fu_75676_p1; +wire [63:0] zext_ln1116_2_fu_75720_p1; +wire [63:0] zext_ln203_23_fu_75882_p1; +wire [63:0] zext_ln1116_6_fu_76005_p1; +wire [63:0] zext_ln232_6_fu_75985_p1; +wire [63:0] zext_ln203_21_fu_76139_p1; +wire [63:0] zext_ln203_39_fu_76352_p1; +wire [63:0] zext_ln203_37_fu_76412_p1; +wire [63:0] zext_ln232_10_fu_76491_p1; +wire [63:0] zext_ln1116_10_fu_76535_p1; +wire [63:0] zext_ln203_55_fu_76696_p1; +wire [63:0] zext_ln1116_14_fu_76823_p1; +wire [63:0] zext_ln232_14_fu_76799_p1; +wire [63:0] zext_ln203_53_fu_76874_p1; +wire [63:0] zext_ln203_71_fu_77065_p1; +wire [63:0] zext_ln203_69_fu_77125_p1; +wire [63:0] zext_ln232_1_fu_77438_p1; +wire [63:0] zext_ln1116_1_fu_77482_p1; +wire [63:0] zext_ln203_19_fu_77653_p1; +wire [63:0] zext_ln1116_5_fu_77776_p1; +wire [63:0] zext_ln232_5_fu_77756_p1; +wire [63:0] zext_ln203_17_fu_77910_p1; +wire [63:0] zext_ln203_35_fu_78122_p1; +wire [63:0] zext_ln203_33_fu_78182_p1; +wire [63:0] zext_ln232_9_fu_78261_p1; +wire [63:0] zext_ln1116_9_fu_78305_p1; +wire [63:0] zext_ln203_51_fu_78476_p1; +wire [63:0] zext_ln1116_13_fu_78603_p1; +wire [63:0] zext_ln232_13_fu_78579_p1; +wire [63:0] zext_ln203_49_fu_78654_p1; +wire [63:0] zext_ln203_67_fu_78845_p1; +wire [63:0] zext_ln203_65_fu_78905_p1; +wire [63:0] zext_ln232_3_fu_79140_p1; +wire [63:0] zext_ln1116_3_fu_79184_p1; +wire [63:0] zext_ln203_27_fu_79345_p1; +wire [63:0] zext_ln1116_8_fu_79472_p1; +wire [63:0] zext_ln232_8_fu_79448_p1; +wire [63:0] zext_ln203_25_fu_79622_p1; +wire [63:0] zext_ln203_47_fu_79813_p1; +wire [63:0] zext_ln203_45_fu_79873_p1; +wire [63:0] zext_ln232_11_fu_79952_p1; +wire [63:0] zext_ln1116_11_fu_79996_p1; +wire [63:0] zext_ln203_59_fu_80157_p1; +wire [63:0] zext_ln1116_15_fu_80284_p1; +wire [63:0] zext_ln232_15_fu_80260_p1; +wire [63:0] zext_ln203_57_fu_80335_p1; +wire [63:0] zext_ln203_75_fu_80526_p1; +wire [63:0] zext_ln203_73_fu_80586_p1; +wire [63:0] zext_ln203_3_fu_80711_p1; +wire [63:0] zext_ln203_7_fu_80880_p1; +wire [63:0] zext_ln203_10_fu_80987_p1; +wire [63:0] zext_ln203_6_fu_81117_p1; +wire [63:0] zext_ln203_9_fu_81256_p1; +wire [63:0] zext_ln203_15_fu_81363_p1; +wire [63:0] zext_ln1265_1_fu_81541_p1; +wire [63:0] zext_ln1265_3_fu_81745_p1; +wire [63:0] zext_ln1265_9_fu_81860_p1; +wire [63:0] zext_ln1265_17_fu_82100_p1; +wire [63:0] zext_ln1265_26_fu_82266_p1; +wire [63:0] zext_ln1265_43_fu_82445_p1; +wire [63:0] zext_ln1265_30_fu_82628_p1; +wire [63:0] zext_ln1265_47_fu_82952_p1; +wire [63:0] zext_ln1265_59_fu_83235_p1; +wire [63:0] zext_ln1265_69_fu_83397_p1; +wire [63:0] zext_ln1265_7_fu_83563_p1; +wire [63:0] zext_ln1265_15_fu_83687_p1; +wire [63:0] zext_ln1265_24_fu_84059_p1; +wire [63:0] zext_ln1265_36_fu_84358_p1; +wire [63:0] zext_ln1265_53_fu_84536_p1; +wire [63:0] zext_ln1265_41_fu_84719_p1; +wire [63:0] zext_ln1265_57_fu_85042_p1; +wire [63:0] zext_ln1265_67_fu_85324_p1; +wire [63:0] zext_ln1265_75_fu_85485_p1; +wire [63:0] zext_ln1265_2_fu_85662_p1; +wire [63:0] zext_ln1265_4_fu_85828_p1; +wire [63:0] zext_ln1265_13_fu_85943_p1; +wire [63:0] zext_ln1265_22_fu_86315_p1; +wire [63:0] zext_ln1265_34_fu_86614_p1; +wire [63:0] zext_ln1265_51_fu_86792_p1; +wire [63:0] zext_ln1265_39_fu_86975_p1; +wire [63:0] zext_ln1265_55_fu_87299_p1; +wire [63:0] zext_ln1265_65_fu_87582_p1; +wire [63:0] zext_ln1265_73_fu_87744_p1; +wire [63:0] zext_ln1265_11_fu_87910_p1; +wire [63:0] zext_ln1265_19_fu_88034_p1; +wire [63:0] zext_ln1265_32_fu_88406_p1; +wire [63:0] zext_ln1265_45_fu_88705_p1; +wire [63:0] zext_ln1265_61_fu_88883_p1; +wire [63:0] zext_ln1265_49_fu_89066_p1; +wire [63:0] zext_ln1265_63_fu_89389_p1; +wire [63:0] zext_ln1265_71_fu_89671_p1; +wire [63:0] zext_ln1265_77_fu_89832_p1; +wire [5:0] trunc_ln203_5_fu_74188_p1; +wire [5:0] trunc_ln203_fu_74445_p1; +wire [5:0] trunc_ln203_14_fu_74658_p1; +wire [5:0] trunc_ln203_13_fu_74718_p1; +wire [5:0] trunc_ln203_20_fu_75012_p1; +wire [5:0] trunc_ln203_19_fu_75190_p1; +wire [5:0] trunc_ln203_30_fu_75381_p1; +wire [5:0] trunc_ln203_29_fu_75441_p1; +wire [5:0] trunc_ln203_10_fu_75878_p1; +wire [5:0] trunc_ln203_9_fu_76135_p1; +wire [5:0] trunc_ln203_18_fu_76348_p1; +wire [5:0] trunc_ln203_17_fu_76408_p1; +wire [5:0] trunc_ln203_26_fu_76692_p1; +wire [5:0] trunc_ln203_25_fu_76870_p1; +wire [5:0] trunc_ln203_34_fu_77061_p1; +wire [5:0] trunc_ln203_33_fu_77121_p1; +wire [5:0] trunc_ln203_8_fu_77649_p1; +wire [5:0] trunc_ln203_7_fu_77906_p1; +wire [5:0] trunc_ln203_16_fu_78118_p1; +wire [5:0] trunc_ln203_15_fu_78178_p1; +wire [5:0] trunc_ln203_24_fu_78472_p1; +wire [5:0] trunc_ln203_23_fu_78650_p1; +wire [5:0] trunc_ln203_32_fu_78841_p1; +wire [5:0] trunc_ln203_31_fu_78901_p1; +wire [5:0] trunc_ln203_12_fu_79341_p1; +wire [5:0] trunc_ln203_11_fu_79618_p1; +wire [5:0] trunc_ln203_22_fu_79809_p1; +wire [5:0] trunc_ln203_21_fu_79869_p1; +wire [5:0] trunc_ln203_28_fu_80153_p1; +wire [5:0] trunc_ln203_27_fu_80331_p1; +wire [5:0] trunc_ln203_36_fu_80522_p1; +wire [5:0] trunc_ln203_35_fu_80582_p1; +wire [5:0] or_ln2_fu_80834_p3; +wire [5:0] add_ln203_3_fu_80968_p2; +wire [5:0] or_ln203_1_fu_81206_p3; +wire [5:0] add_ln203_7_fu_81344_p2; +wire [7:0] add_ln703_3_fu_82193_p2; +wire [7:0] add_ln703_14_fu_82538_p2; +wire [7:0] add_ln703_6_fu_84152_p2; +wire [7:0] add_ln703_19_fu_84629_p2; +wire [7:0] add_ln703_5_fu_86408_p2; +wire [7:0] add_ln703_18_fu_86885_p2; +wire [7:0] add_ln703_9_fu_88499_p2; +wire [7:0] add_ln703_23_fu_88976_p2; +wire [7:0] add_ln703_16_fu_83045_p2; +wire [7:0] add_ln703_27_fu_83490_p2; +wire [7:0] add_ln703_21_fu_85135_p2; +wire [7:0] add_ln703_30_fu_85578_p2; +wire [7:0] add_ln703_20_fu_87392_p2; +wire [7:0] add_ln703_29_fu_87837_p2; +wire [7:0] add_ln703_24_fu_89482_p2; +wire [7:0] add_ln703_31_fu_89925_p2; +wire [5:0] or_ln203_2_fu_80935_p3; +wire [5:0] or_ln203_4_fu_81049_p3; +wire [5:0] or_ln203_3_fu_81311_p3; +wire [5:0] or_ln203_5_fu_81425_p3; +wire [31:0] grp_fu_73372_p0; +wire [5:0] grp_fu_73372_p1; +wire [31:0] grp_fu_73378_p0; +wire [5:0] grp_fu_73378_p1; +wire [31:0] grp_fu_73388_p0; +wire [5:0] grp_fu_73388_p1; +wire [31:0] grp_fu_73394_p0; +wire [5:0] grp_fu_73394_p1; +wire [31:0] grp_fu_73404_p0; +wire [5:0] grp_fu_73404_p1; +wire [31:0] grp_fu_73410_p0; +wire [5:0] grp_fu_73410_p1; +wire [31:0] grp_fu_73420_p0; +wire [5:0] grp_fu_73420_p1; +wire [31:0] grp_fu_73426_p0; +wire [5:0] grp_fu_73426_p1; +wire [31:0] grp_fu_73436_p0; +wire [5:0] grp_fu_73436_p1; +wire [31:0] grp_fu_73442_p0; +wire [5:0] grp_fu_73442_p1; +wire [31:0] grp_fu_73452_p0; +wire [5:0] grp_fu_73452_p1; +wire [31:0] grp_fu_73458_p0; +wire [5:0] grp_fu_73458_p1; +wire [31:0] grp_fu_73468_p0; +wire [5:0] grp_fu_73468_p1; +wire [31:0] grp_fu_73474_p0; +wire [5:0] grp_fu_73474_p1; +wire [31:0] grp_fu_73484_p0; +wire [5:0] grp_fu_73484_p1; +wire [31:0] grp_fu_73490_p0; +wire [5:0] grp_fu_73490_p1; +wire [4:0] mul_ln231_fu_73704_p1; +wire [6:0] add_ln231_fu_73714_p2; +wire [4:0] or_ln199_fu_73734_p2; +wire [11:0] zext_ln216_fu_73770_p1; +wire [11:0] add_ln216_fu_73774_p2; +wire [16:0] zext_ln216_1_fu_73779_p1; + wire [16:0] add_ln216_1_fu_73783_p2; +wire [4:0] or_ln201_fu_73792_p2; +wire [4:0] mul_ln231_2_fu_73806_p0; +wire [6:0] add_ln231_2_fu_73812_p2; +wire [31:0] add_ln223_fu_73826_p2; +wire [30:0] tmp_1_fu_73831_p4; +wire [0:0] icmp_ln223_fu_73841_p2; +wire [0:0] icmp_ln223_1_fu_73847_p2; +wire [31:0] shl_ln231_fu_73859_p2; +wire [31:0] shl_ln231_1_fu_73865_p2; +wire [31:0] sub_ln231_fu_73871_p2; +wire [31:0] shl_ln221_fu_73887_p2; +wire [31:0] shl_ln216_fu_73881_p2; +wire [31:0] add_ln216_2_fu_73899_p2; +wire [31:0] add_ln221_fu_73893_p2; +wire [28:0] tmp_20_fu_73910_p4; +wire [31:0] shl_ln221_1_fu_73932_p2; +wire [31:0] add_ln223_3_fu_73943_p2; +wire [30:0] tmp_4_fu_73948_p4; +wire [0:0] icmp_ln223_6_fu_73958_p2; +wire [0:0] icmp_ln223_7_fu_73964_p2; +wire [31:0] add_ln221_3_fu_73938_p2; +wire [33:0] grp_fu_73985_p0; +wire [31:0] grp_fu_73985_p1; +wire [64:0] grp_fu_73985_p2; +wire [10:0] trunc_ln231_5_fu_74001_p1; +wire [10:0] add_ln1116_4_fu_74005_p2; +wire [7:0] lshr_ln_fu_74010_p4; +wire [2:0] empty_83_fu_74025_p1; +wire [2:0] tmp34_fu_74029_p2; +wire [2:0] trunc_ln1116_326113291_fu_74035_p2; +wire [1:0] tmp_41_fu_74040_p4; +wire [5:0] tmp_42_fu_74050_p3; +wire [5:0] empty_84_fu_74058_p2; +wire [6:0] zext_ln1116_16_fu_74070_p1; +wire [6:0] zext_ln1116_17_fu_74074_p1; +wire [0:0] icmp_ln1116_fu_74064_p2; +wire [6:0] sub_ln1116_fu_74088_p2; +wire [6:0] sub_ln1116_1_fu_74100_p2; +reg [63:0] tmp_6_fu_74078_p4; +wire [6:0] xor_ln1116_fu_74094_p2; +wire [6:0] select_ln1116_fu_74106_p3; +wire [6:0] select_ln1116_2_fu_74122_p3; +wire [63:0] select_ln1116_1_fu_74114_p3; +wire [63:0] zext_ln1116_18_fu_74136_p1; +wire [63:0] zext_ln1116_19_fu_74146_p1; +wire [63:0] lshr_ln1116_15_fu_74149_p2; +wire [63:0] and_ln1116_fu_74155_p2; +wire [7:0] trunc_ln1116_1_fu_74160_p1; +wire [4:0] mul_ln1118_fu_74172_p0; +wire [7:0] mul_ln1118_fu_74172_p1; +wire [11:0] mul_ln1118_fu_74172_p2; +wire [5:0] grp_fu_73372_p2; +wire [31:0] or_ln208_fu_74227_p2; +wire [31:0] shl_ln221_8_fu_74245_p2; +wire [31:0] add_ln223_9_fu_74256_p2; +wire [30:0] tmp_84_fu_74261_p4; +wire [0:0] icmp_ln223_18_fu_74271_p2; +wire [0:0] icmp_ln223_19_fu_74277_p2; +wire [10:0] trunc_ln208_fu_74223_p1; +wire [31:0] add_ln221_10_fu_74251_p2; +wire [10:0] or_ln231_fu_74289_p2; +wire [10:0] add_ln1116_8_fu_74300_p2; +wire [7:0] lshr_ln1116_3_fu_74305_p4; +wire [31:0] or_ln206_fu_74320_p2; +wire [31:0] add_ln223_8_fu_74344_p2; +wire [30:0] tmp_83_fu_74349_p4; +wire [0:0] icmp_ln223_16_fu_74359_p2; +wire [0:0] icmp_ln223_17_fu_74365_p2; +wire [31:0] shl_ln231_8_fu_74377_p2; +wire [31:0] shl_ln231_9_fu_74383_p2; +wire [31:0] add_ln216_21_fu_74395_p2; +wire [31:0] shl_ln216_4_fu_74332_p2; +wire [31:0] add_ln221_11_fu_74406_p2; +wire [31:0] shl_ln221_9_fu_74338_p2; +wire [31:0] sub_ln231_4_fu_74389_p2; +wire [33:0] grp_fu_74429_p0; +wire [31:0] grp_fu_74429_p1; +wire [64:0] grp_fu_74429_p2; +wire [2:0] trunc_ln1116_7_fu_74480_p1; +wire [2:0] empty_85_fu_74484_p2; +wire [2:0] tmp35_fu_74490_p2; +wire [2:0] trunc_ln1116_406113313_fu_74496_p2; +wire [5:0] tmp_92_fu_74501_p3; +wire [5:0] empty_86_fu_74509_p2; +wire [6:0] zext_ln1116_32_fu_74521_p1; +wire [6:0] zext_ln1116_33_fu_74525_p1; +wire [0:0] icmp_ln1116_4_fu_74515_p2; +wire [6:0] sub_ln1116_12_fu_74539_p2; +wire [6:0] sub_ln1116_13_fu_74551_p2; +reg [63:0] tmp_93_fu_74529_p4; +wire [6:0] xor_ln1116_4_fu_74545_p2; +wire [6:0] select_ln1116_12_fu_74557_p3; +wire [6:0] select_ln1116_14_fu_74573_p3; +wire [63:0] select_ln1116_13_fu_74565_p3; +wire [63:0] zext_ln1116_34_fu_74587_p1; +wire [63:0] zext_ln1116_35_fu_74597_p1; +wire [63:0] lshr_ln1116_23_fu_74600_p2; +wire [63:0] and_ln1116_4_fu_74606_p2; +wire [7:0] trunc_ln1116_8_fu_74611_p1; +wire [4:0] mul_ln1118_13_fu_74623_p0; +wire [7:0] mul_ln1118_13_fu_74623_p1; +wire [11:0] mul_ln1118_13_fu_74623_p2; +wire [33:0] grp_fu_74642_p0; +wire [31:0] grp_fu_74642_p1; +wire [64:0] grp_fu_74642_p2; +wire [5:0] grp_fu_73378_p2; +wire [33:0] grp_fu_74702_p0; +wire [31:0] grp_fu_74702_p1; +wire [64:0] grp_fu_74702_p2; +wire [31:0] shl_ln221_12_fu_74757_p2; +wire [31:0] add_ln223_14_fu_74768_p2; +wire [30:0] tmp_109_fu_74773_p4; +wire [0:0] icmp_ln223_28_fu_74783_p2; +wire [0:0] icmp_ln223_29_fu_74789_p2; +wire [31:0] add_ln221_15_fu_74763_p2; +wire [33:0] grp_fu_74810_p0; +wire [31:0] grp_fu_74810_p1; +wire [64:0] grp_fu_74810_p2; +wire [10:0] trunc_ln231_13_fu_74826_p1; +wire [10:0] add_ln1116_11_fu_74830_p2; +wire [7:0] lshr_ln1116_6_fu_74835_p4; +wire [2:0] empty_89_fu_74850_p1; +wire [2:0] tmp36_fu_74854_p2; +wire [2:0] trunc_ln1116_466113335_fu_74859_p2; +wire [1:0] tmp_128_fu_74864_p4; +wire [5:0] tmp_129_fu_74874_p3; +wire [5:0] empty_90_fu_74882_p2; +wire [6:0] zext_ln1116_44_fu_74894_p1; +wire [6:0] zext_ln1116_45_fu_74898_p1; +wire [0:0] icmp_ln1116_7_fu_74888_p2; +wire [6:0] sub_ln1116_21_fu_74912_p2; +wire [6:0] sub_ln1116_22_fu_74924_p2; +reg [63:0] tmp_130_fu_74902_p4; +wire [6:0] xor_ln1116_7_fu_74918_p2; +wire [6:0] select_ln1116_21_fu_74930_p3; +wire [6:0] select_ln1116_23_fu_74946_p3; +wire [63:0] select_ln1116_22_fu_74938_p3; +wire [63:0] zext_ln1116_46_fu_74960_p1; +wire [63:0] zext_ln1116_47_fu_74970_p1; +wire [63:0] lshr_ln1116_29_fu_74973_p2; +wire [63:0] and_ln1116_7_fu_74979_p2; +wire [7:0] trunc_ln1116_15_fu_74984_p1; +wire [4:0] mul_ln1118_16_fu_74996_p0; +wire [7:0] mul_ln1118_16_fu_74996_p1; +wire [11:0] mul_ln1118_16_fu_74996_p2; +wire [5:0] grp_fu_73388_p2; +wire [31:0] or_ln208_4_fu_75051_p2; +wire [31:0] shl_ln221_20_fu_75069_p2; +wire [31:0] add_ln223_20_fu_75080_p2; +wire [30:0] tmp_197_fu_75085_p4; +wire [0:0] icmp_ln223_40_fu_75095_p2; +wire [0:0] icmp_ln223_41_fu_75101_p2; +wire [10:0] trunc_ln208_4_fu_75047_p1; +wire [31:0] add_ln221_26_fu_75075_p2; +wire [10:0] or_ln231_4_fu_75113_p2; +wire [10:0] add_ln1116_16_fu_75124_p2; +wire [7:0] lshr_ln1116_11_fu_75129_p4; +wire [2:0] trunc_ln1116_22_fu_75139_p1; +wire [2:0] empty_91_fu_75148_p2; +wire [2:0] tmp37_fu_75154_p2; +wire [33:0] grp_fu_75174_p0; +wire [31:0] grp_fu_75174_p1; +wire [64:0] grp_fu_75174_p2; +wire [5:0] tmp_203_fu_75225_p3; +wire [5:0] empty_92_fu_75232_p2; +wire [6:0] zext_ln1116_64_fu_75244_p1; +wire [6:0] zext_ln1116_65_fu_75248_p1; +wire [0:0] icmp_ln1116_12_fu_75238_p2; +wire [6:0] sub_ln1116_36_fu_75262_p2; +wire [6:0] sub_ln1116_37_fu_75274_p2; +reg [63:0] tmp_204_fu_75252_p4; +wire [6:0] xor_ln1116_12_fu_75268_p2; +wire [6:0] select_ln1116_36_fu_75280_p3; +wire [6:0] select_ln1116_38_fu_75296_p3; +wire [63:0] select_ln1116_37_fu_75288_p3; +wire [63:0] zext_ln1116_66_fu_75310_p1; +wire [63:0] zext_ln1116_67_fu_75320_p1; +wire [63:0] lshr_ln1116_39_fu_75323_p2; +wire [63:0] and_ln1116_12_fu_75329_p2; +wire [7:0] trunc_ln1116_23_fu_75334_p1; +wire [4:0] mul_ln1118_21_fu_75346_p0; +wire [7:0] mul_ln1118_21_fu_75346_p1; +wire [11:0] mul_ln1118_21_fu_75346_p2; +wire [33:0] grp_fu_75365_p0; +wire [31:0] grp_fu_75365_p1; +wire [64:0] grp_fu_75365_p2; +wire [5:0] grp_fu_73394_p2; +wire [33:0] grp_fu_75425_p0; +wire [31:0] grp_fu_75425_p1; +wire [64:0] grp_fu_75425_p2; +wire [11:0] zext_ln216_6_fu_75498_p1; +wire [11:0] add_ln216_6_fu_75502_p2; +wire [16:0] zext_ln216_7_fu_75507_p1; + wire [16:0] add_ln216_7_fu_75511_p2; +wire [31:0] add_ln223_2_fu_75526_p2; +wire [30:0] tmp_3_fu_75531_p4; +wire [0:0] icmp_ln223_4_fu_75541_p2; +wire [0:0] icmp_ln223_5_fu_75547_p2; +wire [31:0] shl_ln231_4_fu_75559_p2; +wire [31:0] shl_ln231_5_fu_75565_p2; +wire [31:0] sub_ln231_2_fu_75571_p2; +wire [31:0] shl_ln221_3_fu_75587_p2; +wire [31:0] shl_ln216_2_fu_75581_p2; +wire [31:0] add_ln216_10_fu_75599_p2; +wire [31:0] add_ln221_5_fu_75593_p2; +wire [28:0] tmp_32_fu_75610_p4; +wire [31:0] shl_ln221_5_fu_75632_p2; +wire [31:0] add_ln223_6_fu_75643_p2; +wire [30:0] tmp_10_fu_75648_p4; +wire [0:0] icmp_ln223_12_fu_75658_p2; +wire [0:0] icmp_ln223_13_fu_75664_p2; +wire [31:0] add_ln221_7_fu_75638_p2; +wire [33:0] grp_fu_75685_p0; +wire [31:0] grp_fu_75685_p1; +wire [64:0] grp_fu_75685_p2; +wire [10:0] trunc_ln231_8_fu_75701_p1; +wire [10:0] add_ln1116_6_fu_75705_p2; +wire [7:0] lshr_ln1116_1_fu_75710_p4; +wire [2:0] empty_99_fu_75725_p1; +wire [2:0] tmp42_fu_75729_p2; +wire [2:0] trunc_ln1116_366113379_fu_75735_p2; +wire [5:0] tmp_61_fu_75740_p3; +wire [5:0] empty_100_fu_75748_p2; +wire [6:0] zext_ln1116_24_fu_75760_p1; +wire [6:0] zext_ln1116_25_fu_75764_p1; +wire [0:0] icmp_ln1116_2_fu_75754_p2; +wire [6:0] sub_ln1116_6_fu_75778_p2; +wire [6:0] sub_ln1116_7_fu_75790_p2; +reg [63:0] tmp_62_fu_75768_p4; +wire [6:0] xor_ln1116_2_fu_75784_p2; +wire [6:0] select_ln1116_6_fu_75796_p3; +wire [6:0] select_ln1116_8_fu_75812_p3; +wire [63:0] select_ln1116_7_fu_75804_p3; +wire [63:0] zext_ln1116_26_fu_75826_p1; +wire [63:0] zext_ln1116_27_fu_75836_p1; +wire [63:0] lshr_ln1116_19_fu_75839_p2; +wire [63:0] and_ln1116_2_fu_75845_p2; +wire [7:0] trunc_ln1116_4_fu_75850_p1; +wire [4:0] mul_ln1118_11_fu_75862_p0; +wire [7:0] mul_ln1118_11_fu_75862_p1; +wire [11:0] mul_ln1118_11_fu_75862_p2; +wire [5:0] grp_fu_73404_p2; +wire [31:0] or_ln208_2_fu_75917_p2; +wire [31:0] shl_ln221_11_fu_75935_p2; +wire [31:0] add_ln223_13_fu_75946_p2; +wire [30:0] tmp_108_fu_75951_p4; +wire [0:0] icmp_ln223_26_fu_75961_p2; +wire [0:0] icmp_ln223_27_fu_75967_p2; +wire [10:0] trunc_ln208_2_fu_75913_p1; +wire [31:0] add_ln221_14_fu_75941_p2; +wire [10:0] or_ln231_2_fu_75979_p2; +wire [10:0] add_ln1116_10_fu_75990_p2; +wire [7:0] lshr_ln1116_5_fu_75995_p4; +wire [31:0] or_ln206_2_fu_76010_p2; +wire [31:0] add_ln223_12_fu_76034_p2; +wire [30:0] tmp_107_fu_76039_p4; +wire [0:0] icmp_ln223_24_fu_76049_p2; +wire [0:0] icmp_ln223_25_fu_76055_p2; +wire [31:0] shl_ln231_12_fu_76067_p2; +wire [31:0] shl_ln231_13_fu_76073_p2; +wire [31:0] add_ln216_28_fu_76085_p2; +wire [31:0] shl_ln216_6_fu_76022_p2; +wire [31:0] add_ln221_18_fu_76096_p2; +wire [31:0] shl_ln221_14_fu_76028_p2; +wire [31:0] sub_ln231_6_fu_76079_p2; +wire [33:0] grp_fu_76119_p0; +wire [31:0] grp_fu_76119_p1; +wire [64:0] grp_fu_76119_p2; +wire [2:0] trunc_ln1116_13_fu_76170_p1; +wire [2:0] empty_101_fu_76174_p2; +wire [2:0] tmp43_fu_76180_p2; +wire [2:0] trunc_ln1116_4461133911_fu_76186_p2; +wire [5:0] tmp_124_fu_76191_p3; +wire [5:0] empty_102_fu_76199_p2; +wire [6:0] zext_ln1116_40_fu_76211_p1; +wire [6:0] zext_ln1116_41_fu_76215_p1; +wire [0:0] icmp_ln1116_6_fu_76205_p2; +wire [6:0] sub_ln1116_18_fu_76229_p2; +wire [6:0] sub_ln1116_19_fu_76241_p2; +reg [63:0] tmp_125_fu_76219_p4; +wire [6:0] xor_ln1116_6_fu_76235_p2; +wire [6:0] select_ln1116_18_fu_76247_p3; +wire [6:0] select_ln1116_20_fu_76263_p3; +wire [63:0] select_ln1116_19_fu_76255_p3; +wire [63:0] zext_ln1116_42_fu_76277_p1; +wire [63:0] zext_ln1116_43_fu_76287_p1; +wire [63:0] lshr_ln1116_27_fu_76290_p2; +wire [63:0] and_ln1116_6_fu_76296_p2; +wire [7:0] trunc_ln1116_14_fu_76301_p1; +wire [4:0] mul_ln1118_15_fu_76313_p0; +wire [7:0] mul_ln1118_15_fu_76313_p1; +wire [11:0] mul_ln1118_15_fu_76313_p2; +wire [33:0] grp_fu_76332_p0; +wire [31:0] grp_fu_76332_p1; +wire [64:0] grp_fu_76332_p2; +wire [5:0] grp_fu_73410_p2; +wire [33:0] grp_fu_76392_p0; +wire [31:0] grp_fu_76392_p1; +wire [64:0] grp_fu_76392_p2; +wire [31:0] shl_ln221_17_fu_76447_p2; +wire [31:0] add_ln223_18_fu_76458_p2; +wire [30:0] tmp_146_fu_76463_p4; +wire [0:0] icmp_ln223_36_fu_76473_p2; +wire [0:0] icmp_ln223_37_fu_76479_p2; +wire [31:0] add_ln221_22_fu_76453_p2; +wire [33:0] grp_fu_76500_p0; +wire [31:0] grp_fu_76500_p1; +wire [64:0] grp_fu_76500_p2; +wire [10:0] trunc_ln231_16_fu_76516_p1; +wire [10:0] add_ln1116_14_fu_76520_p2; +wire [7:0] lshr_ln1116_9_fu_76525_p4; +wire [2:0] empty_105_fu_76540_p1; +wire [2:0] tmp44_fu_76544_p2; +wire [2:0] trunc_ln1116_5261134113_fu_76549_p2; +wire [5:0] tmp_168_fu_76554_p3; +wire [5:0] empty_106_fu_76562_p2; +wire [6:0] zext_ln1116_56_fu_76574_p1; +wire [6:0] zext_ln1116_57_fu_76578_p1; +wire [0:0] icmp_ln1116_10_fu_76568_p2; +wire [6:0] sub_ln1116_30_fu_76592_p2; +wire [6:0] sub_ln1116_31_fu_76604_p2; +reg [63:0] tmp_169_fu_76582_p4; +wire [6:0] xor_ln1116_10_fu_76598_p2; +wire [6:0] select_ln1116_30_fu_76610_p3; +wire [6:0] select_ln1116_32_fu_76626_p3; +wire [63:0] select_ln1116_31_fu_76618_p3; +wire [63:0] zext_ln1116_58_fu_76640_p1; +wire [63:0] zext_ln1116_59_fu_76650_p1; +wire [63:0] lshr_ln1116_35_fu_76653_p2; +wire [63:0] and_ln1116_10_fu_76659_p2; +wire [7:0] trunc_ln1116_20_fu_76664_p1; +wire [4:0] mul_ln1118_19_fu_76676_p0; +wire [7:0] mul_ln1118_19_fu_76676_p1; +wire [11:0] mul_ln1118_19_fu_76676_p2; +wire [5:0] grp_fu_73420_p2; +wire [31:0] or_ln208_6_fu_76731_p2; +wire [31:0] shl_ln221_22_fu_76749_p2; +wire [31:0] add_ln223_22_fu_76760_p2; +wire [30:0] tmp_215_fu_76765_p4; +wire [0:0] icmp_ln223_44_fu_76775_p2; +wire [0:0] icmp_ln223_45_fu_76781_p2; +wire [10:0] trunc_ln208_6_fu_76727_p1; +wire [31:0] add_ln221_28_fu_76755_p2; +wire [10:0] or_ln231_6_fu_76793_p2; +wire [10:0] add_ln1116_18_fu_76804_p2; +wire [7:0] lshr_ln1116_13_fu_76809_p4; +wire [2:0] trunc_ln1116_26_fu_76819_p1; +wire [2:0] empty_107_fu_76828_p2; +wire [2:0] tmp45_fu_76834_p2; +wire [33:0] grp_fu_76854_p0; +wire [31:0] grp_fu_76854_p1; +wire [64:0] grp_fu_76854_p2; +wire [5:0] tmp_224_fu_76905_p3; +wire [5:0] empty_108_fu_76912_p2; +wire [6:0] zext_ln1116_72_fu_76924_p1; +wire [6:0] zext_ln1116_73_fu_76928_p1; +wire [0:0] icmp_ln1116_14_fu_76918_p2; +wire [6:0] sub_ln1116_42_fu_76942_p2; +wire [6:0] sub_ln1116_43_fu_76954_p2; +reg [63:0] tmp_225_fu_76932_p4; +wire [6:0] xor_ln1116_14_fu_76948_p2; +wire [6:0] select_ln1116_42_fu_76960_p3; +wire [6:0] select_ln1116_44_fu_76976_p3; +wire [63:0] select_ln1116_43_fu_76968_p3; +wire [63:0] zext_ln1116_74_fu_76990_p1; +wire [63:0] zext_ln1116_75_fu_77000_p1; +wire [63:0] lshr_ln1116_43_fu_77003_p2; +wire [63:0] and_ln1116_14_fu_77009_p2; +wire [7:0] trunc_ln1116_27_fu_77014_p1; +wire [4:0] mul_ln1118_23_fu_77026_p0; +wire [7:0] mul_ln1118_23_fu_77026_p1; +wire [11:0] mul_ln1118_23_fu_77026_p2; +wire [33:0] grp_fu_77045_p0; +wire [31:0] grp_fu_77045_p1; +wire [64:0] grp_fu_77045_p2; +wire [5:0] grp_fu_73426_p2; +wire [33:0] grp_fu_77105_p0; +wire [31:0] grp_fu_77105_p1; +wire [64:0] grp_fu_77105_p2; +wire [4:0] mul_ln231_1_fu_77170_p1; +wire [6:0] add_ln231_1_fu_77180_p2; +wire [11:0] zext_ln216_3_fu_77228_p1; +wire [11:0] add_ln216_4_fu_77232_p2; +wire [16:0] zext_ln216_4_fu_77237_p1; + wire [16:0] add_ln216_5_fu_77241_p2; +wire [4:0] or_ln201_1_fu_77250_p2; +wire [4:0] mul_ln231_3_fu_77264_p0; +wire [6:0] add_ln231_4_fu_77270_p2; +wire [31:0] add_ln223_1_fu_77284_p2; +wire [30:0] tmp_2_fu_77289_p4; +wire [0:0] icmp_ln223_2_fu_77299_p2; +wire [0:0] icmp_ln223_3_fu_77305_p2; +wire [31:0] shl_ln231_2_fu_77317_p2; +wire [31:0] shl_ln231_3_fu_77323_p2; +wire [31:0] sub_ln231_1_fu_77329_p2; +wire [31:0] shl_ln221_2_fu_77349_p2; +wire [31:0] shl_ln216_1_fu_77343_p2; +wire [31:0] add_ln216_8_fu_77361_p2; +wire [31:0] add_ln221_4_fu_77355_p2; +wire [28:0] tmp_30_fu_77372_p4; +wire [31:0] shl_ln221_4_fu_77394_p2; +wire [31:0] add_ln223_5_fu_77405_p2; +wire [30:0] tmp_9_fu_77410_p4; +wire [0:0] icmp_ln223_10_fu_77420_p2; +wire [0:0] icmp_ln223_11_fu_77426_p2; +wire [31:0] add_ln221_6_fu_77400_p2; +wire [33:0] grp_fu_77447_p0; +wire [31:0] grp_fu_77447_p1; +wire [64:0] grp_fu_77447_p2; +wire [10:0] trunc_ln231_7_fu_77463_p1; +wire [10:0] add_ln1116_5_fu_77467_p2; +wire [7:0] lshr_ln1116_s_fu_77472_p4; +wire [2:0] empty_117_fu_77487_p1; +wire [2:0] tmp50_fu_77491_p2; +wire [2:0] trunc_ln1116_3461134517_fu_77496_p2; +wire [1:0] tmp_56_fu_77501_p4; +wire [5:0] tmp_57_fu_77511_p3; +wire [5:0] empty_118_fu_77519_p2; +wire [6:0] zext_ln1116_20_fu_77531_p1; +wire [6:0] zext_ln1116_21_fu_77535_p1; +wire [0:0] icmp_ln1116_1_fu_77525_p2; +wire [6:0] sub_ln1116_3_fu_77549_p2; +wire [6:0] sub_ln1116_4_fu_77561_p2; +reg [63:0] tmp_58_fu_77539_p4; +wire [6:0] xor_ln1116_1_fu_77555_p2; +wire [6:0] select_ln1116_3_fu_77567_p3; +wire [6:0] select_ln1116_5_fu_77583_p3; +wire [63:0] select_ln1116_4_fu_77575_p3; +wire [63:0] zext_ln1116_22_fu_77597_p1; +wire [63:0] zext_ln1116_23_fu_77607_p1; +wire [63:0] lshr_ln1116_17_fu_77610_p2; +wire [63:0] and_ln1116_1_fu_77616_p2; +wire [7:0] trunc_ln1116_3_fu_77621_p1; +wire [4:0] mul_ln1118_10_fu_77633_p0; +wire [7:0] mul_ln1118_10_fu_77633_p1; +wire [11:0] mul_ln1118_10_fu_77633_p2; +wire [5:0] grp_fu_73436_p2; +wire [31:0] or_ln208_1_fu_77688_p2; +wire [31:0] shl_ln221_10_fu_77706_p2; +wire [31:0] add_ln223_11_fu_77717_p2; +wire [30:0] tmp_105_fu_77722_p4; +wire [0:0] icmp_ln223_22_fu_77732_p2; +wire [0:0] icmp_ln223_23_fu_77738_p2; +wire [10:0] trunc_ln208_1_fu_77684_p1; +wire [31:0] add_ln221_13_fu_77712_p2; +wire [10:0] or_ln231_1_fu_77750_p2; +wire [10:0] add_ln1116_9_fu_77761_p2; +wire [7:0] lshr_ln1116_4_fu_77766_p4; +wire [31:0] or_ln206_1_fu_77781_p2; +wire [31:0] add_ln223_10_fu_77805_p2; +wire [30:0] tmp_104_fu_77810_p4; +wire [0:0] icmp_ln223_20_fu_77820_p2; +wire [0:0] icmp_ln223_21_fu_77826_p2; +wire [31:0] shl_ln231_10_fu_77838_p2; +wire [31:0] shl_ln231_11_fu_77844_p2; +wire [31:0] add_ln216_26_fu_77856_p2; +wire [31:0] shl_ln216_5_fu_77793_p2; +wire [31:0] add_ln221_16_fu_77867_p2; +wire [31:0] shl_ln221_13_fu_77799_p2; +wire [31:0] sub_ln231_5_fu_77850_p2; +wire [33:0] grp_fu_77890_p0; +wire [31:0] grp_fu_77890_p1; +wire [64:0] grp_fu_77890_p2; +wire [2:0] trunc_ln1116_11_fu_77941_p1; +wire [2:0] empty_119_fu_77945_p2; +wire [2:0] tmp51_fu_77951_p2; +wire [2:0] trunc_ln1116_4261134719_fu_77956_p2; +wire [5:0] tmp_120_fu_77961_p3; +wire [5:0] empty_120_fu_77969_p2; +wire [6:0] zext_ln1116_36_fu_77981_p1; +wire [6:0] zext_ln1116_37_fu_77985_p1; +wire [0:0] icmp_ln1116_5_fu_77975_p2; +wire [6:0] sub_ln1116_15_fu_77999_p2; +wire [6:0] sub_ln1116_16_fu_78011_p2; +reg [63:0] tmp_121_fu_77989_p4; +wire [6:0] xor_ln1116_5_fu_78005_p2; +wire [6:0] select_ln1116_15_fu_78017_p3; +wire [6:0] select_ln1116_17_fu_78033_p3; +wire [63:0] select_ln1116_16_fu_78025_p3; +wire [63:0] zext_ln1116_38_fu_78047_p1; +wire [63:0] zext_ln1116_39_fu_78057_p1; +wire [63:0] lshr_ln1116_25_fu_78060_p2; +wire [63:0] and_ln1116_5_fu_78066_p2; +wire [7:0] trunc_ln1116_12_fu_78071_p1; +wire [4:0] mul_ln1118_14_fu_78083_p0; +wire [7:0] mul_ln1118_14_fu_78083_p1; +wire [11:0] mul_ln1118_14_fu_78083_p2; +wire [33:0] grp_fu_78102_p0; +wire [31:0] grp_fu_78102_p1; +wire [64:0] grp_fu_78102_p2; +wire [5:0] grp_fu_73442_p2; +wire [33:0] grp_fu_78162_p0; +wire [31:0] grp_fu_78162_p1; +wire [64:0] grp_fu_78162_p2; +wire [31:0] shl_ln221_16_fu_78217_p2; +wire [31:0] add_ln223_17_fu_78228_p2; +wire [30:0] tmp_145_fu_78233_p4; +wire [0:0] icmp_ln223_34_fu_78243_p2; +wire [0:0] icmp_ln223_35_fu_78249_p2; +wire [31:0] add_ln221_21_fu_78223_p2; +wire [33:0] grp_fu_78270_p0; +wire [31:0] grp_fu_78270_p1; +wire [64:0] grp_fu_78270_p2; +wire [10:0] trunc_ln231_15_fu_78286_p1; +wire [10:0] add_ln1116_13_fu_78290_p2; +wire [7:0] lshr_ln1116_8_fu_78295_p4; +wire [2:0] empty_123_fu_78310_p1; +wire [2:0] tmp52_fu_78314_p2; +wire [2:0] trunc_ln1116_5061134921_fu_78319_p2; +wire [1:0] tmp_163_fu_78324_p4; +wire [5:0] tmp_164_fu_78334_p3; +wire [5:0] empty_124_fu_78342_p2; +wire [6:0] zext_ln1116_52_fu_78354_p1; +wire [6:0] zext_ln1116_53_fu_78358_p1; +wire [0:0] icmp_ln1116_9_fu_78348_p2; +wire [6:0] sub_ln1116_27_fu_78372_p2; +wire [6:0] sub_ln1116_28_fu_78384_p2; +reg [63:0] tmp_165_fu_78362_p4; +wire [6:0] xor_ln1116_9_fu_78378_p2; +wire [6:0] select_ln1116_27_fu_78390_p3; +wire [6:0] select_ln1116_29_fu_78406_p3; +wire [63:0] select_ln1116_28_fu_78398_p3; +wire [63:0] zext_ln1116_54_fu_78420_p1; +wire [63:0] zext_ln1116_55_fu_78430_p1; +wire [63:0] lshr_ln1116_33_fu_78433_p2; +wire [63:0] and_ln1116_9_fu_78439_p2; +wire [7:0] trunc_ln1116_19_fu_78444_p1; +wire [4:0] mul_ln1118_18_fu_78456_p0; +wire [7:0] mul_ln1118_18_fu_78456_p1; +wire [11:0] mul_ln1118_18_fu_78456_p2; +wire [5:0] grp_fu_73452_p2; +wire [31:0] or_ln208_5_fu_78511_p2; +wire [31:0] shl_ln221_21_fu_78529_p2; +wire [31:0] add_ln223_21_fu_78540_p2; +wire [30:0] tmp_214_fu_78545_p4; +wire [0:0] icmp_ln223_42_fu_78555_p2; +wire [0:0] icmp_ln223_43_fu_78561_p2; +wire [10:0] trunc_ln208_5_fu_78507_p1; +wire [31:0] add_ln221_27_fu_78535_p2; +wire [10:0] or_ln231_5_fu_78573_p2; +wire [10:0] add_ln1116_17_fu_78584_p2; +wire [7:0] lshr_ln1116_12_fu_78589_p4; +wire [2:0] trunc_ln1116_24_fu_78599_p1; +wire [2:0] empty_125_fu_78608_p2; +wire [2:0] tmp53_fu_78614_p2; +wire [33:0] grp_fu_78634_p0; +wire [31:0] grp_fu_78634_p1; +wire [64:0] grp_fu_78634_p2; +wire [5:0] tmp_220_fu_78685_p3; +wire [5:0] empty_126_fu_78692_p2; +wire [6:0] zext_ln1116_68_fu_78704_p1; +wire [6:0] zext_ln1116_69_fu_78708_p1; +wire [0:0] icmp_ln1116_13_fu_78698_p2; +wire [6:0] sub_ln1116_39_fu_78722_p2; +wire [6:0] sub_ln1116_40_fu_78734_p2; +reg [63:0] tmp_221_fu_78712_p4; +wire [6:0] xor_ln1116_13_fu_78728_p2; +wire [6:0] select_ln1116_39_fu_78740_p3; +wire [6:0] select_ln1116_41_fu_78756_p3; +wire [63:0] select_ln1116_40_fu_78748_p3; +wire [63:0] zext_ln1116_70_fu_78770_p1; +wire [63:0] zext_ln1116_71_fu_78780_p1; +wire [63:0] lshr_ln1116_41_fu_78783_p2; +wire [63:0] and_ln1116_13_fu_78789_p2; +wire [7:0] trunc_ln1116_25_fu_78794_p1; +wire [4:0] mul_ln1118_22_fu_78806_p0; +wire [7:0] mul_ln1118_22_fu_78806_p1; +wire [11:0] mul_ln1118_22_fu_78806_p2; +wire [33:0] grp_fu_78825_p0; +wire [31:0] grp_fu_78825_p1; +wire [64:0] grp_fu_78825_p2; +wire [5:0] grp_fu_73458_p2; +wire [33:0] grp_fu_78885_p0; +wire [31:0] grp_fu_78885_p1; +wire [64:0] grp_fu_78885_p2; +wire [11:0] zext_ln216_9_fu_78958_p1; +wire [11:0] add_ln216_12_fu_78962_p2; +wire [16:0] zext_ln216_10_fu_78967_p1; + wire [16:0] add_ln216_13_fu_78971_p2; +wire [31:0] add_ln223_4_fu_78986_p2; +wire [30:0] tmp_8_fu_78991_p4; +wire [0:0] icmp_ln223_8_fu_79001_p2; +wire [0:0] icmp_ln223_9_fu_79007_p2; +wire [31:0] shl_ln231_6_fu_79019_p2; +wire [31:0] shl_ln231_7_fu_79025_p2; +wire [31:0] sub_ln231_3_fu_79031_p2; +wire [31:0] shl_ln221_6_fu_79051_p2; +wire [31:0] shl_ln216_3_fu_79045_p2; +wire [31:0] add_ln216_16_fu_79063_p2; +wire [31:0] add_ln221_8_fu_79057_p2; +wire [28:0] tmp_45_fu_79074_p4; +wire [31:0] shl_ln221_7_fu_79096_p2; +wire [31:0] add_ln223_7_fu_79107_p2; +wire [30:0] tmp_66_fu_79112_p4; +wire [0:0] icmp_ln223_14_fu_79122_p2; +wire [0:0] icmp_ln223_15_fu_79128_p2; +wire [31:0] add_ln221_9_fu_79102_p2; +wire [33:0] grp_fu_79149_p0; +wire [31:0] grp_fu_79149_p1; +wire [64:0] grp_fu_79149_p2; +wire [10:0] trunc_ln231_9_fu_79165_p1; +wire [10:0] add_ln1116_7_fu_79169_p2; +wire [7:0] lshr_ln1116_2_fu_79174_p4; +wire [2:0] empty_133_fu_79189_p1; +wire [2:0] tmp58_fu_79193_p2; +wire [2:0] trunc_ln1116_3861135325_fu_79198_p2; +wire [5:0] tmp_76_fu_79203_p3; +wire [5:0] empty_134_fu_79211_p2; +wire [6:0] zext_ln1116_28_fu_79223_p1; +wire [6:0] zext_ln1116_29_fu_79227_p1; +wire [0:0] icmp_ln1116_3_fu_79217_p2; +wire [6:0] sub_ln1116_9_fu_79241_p2; +wire [6:0] sub_ln1116_10_fu_79253_p2; +reg [63:0] tmp_77_fu_79231_p4; +wire [6:0] xor_ln1116_3_fu_79247_p2; +wire [6:0] select_ln1116_9_fu_79259_p3; +wire [6:0] select_ln1116_11_fu_79275_p3; +wire [63:0] select_ln1116_10_fu_79267_p3; +wire [63:0] zext_ln1116_30_fu_79289_p1; +wire [63:0] zext_ln1116_31_fu_79299_p1; +wire [63:0] lshr_ln1116_21_fu_79302_p2; +wire [63:0] and_ln1116_3_fu_79308_p2; +wire [7:0] trunc_ln1116_5_fu_79313_p1; +wire [4:0] mul_ln1118_12_fu_79325_p0; +wire [7:0] mul_ln1118_12_fu_79325_p1; +wire [11:0] mul_ln1118_12_fu_79325_p2; +wire [5:0] grp_fu_73468_p2; +wire [31:0] or_ln208_3_fu_79380_p2; +wire [31:0] shl_ln221_15_fu_79398_p2; +wire [31:0] add_ln223_16_fu_79409_p2; +wire [30:0] tmp_144_fu_79414_p4; +wire [0:0] icmp_ln223_32_fu_79424_p2; +wire [0:0] icmp_ln223_33_fu_79430_p2; +wire [10:0] trunc_ln208_3_fu_79376_p1; +wire [31:0] add_ln221_20_fu_79404_p2; +wire [10:0] or_ln231_3_fu_79442_p2; +wire [10:0] add_ln1116_12_fu_79453_p2; +wire [7:0] lshr_ln1116_7_fu_79458_p4; +wire [2:0] trunc_ln1116_17_fu_79468_p1; +wire [2:0] empty_135_fu_79477_p2; +wire [2:0] tmp59_fu_79483_p2; +wire [31:0] or_ln206_3_fu_79493_p2; +wire [31:0] add_ln223_15_fu_79517_p2; +wire [30:0] tmp_143_fu_79522_p4; +wire [0:0] icmp_ln223_30_fu_79532_p2; +wire [0:0] icmp_ln223_31_fu_79538_p2; +wire [31:0] shl_ln231_14_fu_79550_p2; +wire [31:0] shl_ln231_15_fu_79556_p2; +wire [31:0] add_ln216_33_fu_79568_p2; +wire [31:0] shl_ln216_7_fu_79505_p2; +wire [31:0] add_ln221_23_fu_79579_p2; +wire [31:0] shl_ln221_18_fu_79511_p2; +wire [31:0] sub_ln231_7_fu_79562_p2; +wire [33:0] grp_fu_79602_p0; +wire [31:0] grp_fu_79602_p1; +wire [64:0] grp_fu_79602_p2; +wire [5:0] tmp_159_fu_79653_p3; +wire [5:0] empty_136_fu_79660_p2; +wire [6:0] zext_ln1116_48_fu_79672_p1; +wire [6:0] zext_ln1116_49_fu_79676_p1; +wire [0:0] icmp_ln1116_8_fu_79666_p2; +wire [6:0] sub_ln1116_24_fu_79690_p2; +wire [6:0] sub_ln1116_25_fu_79702_p2; +reg [63:0] tmp_160_fu_79680_p4; +wire [6:0] xor_ln1116_8_fu_79696_p2; +wire [6:0] select_ln1116_24_fu_79708_p3; +wire [6:0] select_ln1116_26_fu_79724_p3; +wire [63:0] select_ln1116_25_fu_79716_p3; +wire [63:0] zext_ln1116_50_fu_79738_p1; +wire [63:0] zext_ln1116_51_fu_79748_p1; +wire [63:0] lshr_ln1116_31_fu_79751_p2; +wire [63:0] and_ln1116_8_fu_79757_p2; +wire [7:0] trunc_ln1116_18_fu_79762_p1; +wire [4:0] mul_ln1118_17_fu_79774_p0; +wire [7:0] mul_ln1118_17_fu_79774_p1; +wire [11:0] mul_ln1118_17_fu_79774_p2; +wire [33:0] grp_fu_79793_p0; +wire [31:0] grp_fu_79793_p1; +wire [64:0] grp_fu_79793_p2; +wire [5:0] grp_fu_73474_p2; +wire [33:0] grp_fu_79853_p0; +wire [31:0] grp_fu_79853_p1; +wire [64:0] grp_fu_79853_p2; +wire [31:0] shl_ln221_19_fu_79908_p2; +wire [31:0] add_ln223_19_fu_79919_p2; +wire [30:0] tmp_177_fu_79924_p4; +wire [0:0] icmp_ln223_38_fu_79934_p2; +wire [0:0] icmp_ln223_39_fu_79940_p2; +wire [31:0] add_ln221_25_fu_79914_p2; +wire [33:0] grp_fu_79961_p0; +wire [31:0] grp_fu_79961_p1; +wire [64:0] grp_fu_79961_p2; +wire [10:0] trunc_ln231_17_fu_79977_p1; +wire [10:0] add_ln1116_15_fu_79981_p2; +wire [7:0] lshr_ln1116_10_fu_79986_p4; +wire [2:0] empty_139_fu_80001_p1; +wire [2:0] tmp60_fu_80005_p2; +wire [2:0] trunc_ln1116_5461135729_fu_80010_p2; +wire [5:0] tmp_187_fu_80015_p3; +wire [5:0] empty_140_fu_80023_p2; +wire [6:0] zext_ln1116_60_fu_80035_p1; +wire [6:0] zext_ln1116_61_fu_80039_p1; +wire [0:0] icmp_ln1116_11_fu_80029_p2; +wire [6:0] sub_ln1116_33_fu_80053_p2; +wire [6:0] sub_ln1116_34_fu_80065_p2; +reg [63:0] tmp_188_fu_80043_p4; +wire [6:0] xor_ln1116_11_fu_80059_p2; +wire [6:0] select_ln1116_33_fu_80071_p3; +wire [6:0] select_ln1116_35_fu_80087_p3; +wire [63:0] select_ln1116_34_fu_80079_p3; +wire [63:0] zext_ln1116_62_fu_80101_p1; +wire [63:0] zext_ln1116_63_fu_80111_p1; +wire [63:0] lshr_ln1116_37_fu_80114_p2; +wire [63:0] and_ln1116_11_fu_80120_p2; +wire [7:0] trunc_ln1116_21_fu_80125_p1; +wire [4:0] mul_ln1118_20_fu_80137_p0; +wire [7:0] mul_ln1118_20_fu_80137_p1; +wire [11:0] mul_ln1118_20_fu_80137_p2; +wire [5:0] grp_fu_73484_p2; +wire [31:0] or_ln208_7_fu_80192_p2; +wire [31:0] shl_ln221_23_fu_80210_p2; +wire [31:0] add_ln223_23_fu_80221_p2; +wire [30:0] tmp_233_fu_80226_p4; +wire [0:0] icmp_ln223_46_fu_80236_p2; +wire [0:0] icmp_ln223_47_fu_80242_p2; +wire [10:0] trunc_ln208_7_fu_80188_p1; +wire [31:0] add_ln221_29_fu_80216_p2; +wire [10:0] or_ln231_7_fu_80254_p2; +wire [10:0] add_ln1116_19_fu_80265_p2; +wire [7:0] lshr_ln1116_14_fu_80270_p4; +wire [2:0] trunc_ln1116_28_fu_80280_p1; +wire [2:0] empty_141_fu_80289_p2; +wire [2:0] tmp61_fu_80295_p2; +wire [33:0] grp_fu_80315_p0; +wire [31:0] grp_fu_80315_p1; +wire [64:0] grp_fu_80315_p2; +wire [5:0] tmp_232_fu_80366_p3; +wire [5:0] empty_142_fu_80373_p2; +wire [6:0] zext_ln1116_76_fu_80385_p1; +wire [6:0] zext_ln1116_77_fu_80389_p1; +wire [0:0] icmp_ln1116_15_fu_80379_p2; +wire [6:0] sub_ln1116_45_fu_80403_p2; +wire [6:0] sub_ln1116_46_fu_80415_p2; +reg [63:0] tmp_238_fu_80393_p4; +wire [6:0] xor_ln1116_15_fu_80409_p2; +wire [6:0] select_ln1116_45_fu_80421_p3; +wire [6:0] select_ln1116_47_fu_80437_p3; +wire [63:0] select_ln1116_46_fu_80429_p3; +wire [63:0] zext_ln1116_78_fu_80451_p1; +wire [63:0] zext_ln1116_79_fu_80461_p1; +wire [63:0] lshr_ln1116_45_fu_80464_p2; +wire [63:0] and_ln1116_15_fu_80470_p2; +wire [7:0] trunc_ln1116_29_fu_80475_p1; +wire [4:0] mul_ln1118_24_fu_80487_p0; +wire [7:0] mul_ln1118_24_fu_80487_p1; +wire [11:0] mul_ln1118_24_fu_80487_p2; +wire [33:0] grp_fu_80506_p0; +wire [31:0] grp_fu_80506_p1; +wire [64:0] grp_fu_80506_p2; +wire [5:0] grp_fu_73490_p2; +wire [33:0] grp_fu_80566_p0; +wire [31:0] grp_fu_80566_p1; +wire [64:0] grp_fu_80566_p2; +wire [11:0] shl_ln_fu_80623_p3; +wire [8:0] shl_ln250_8_fu_80635_p3; +wire [12:0] zext_ln250_fu_80631_p1; +wire [12:0] zext_ln250_1_fu_80643_p1; +wire [3:0] trunc_ln250_2_fu_80675_p1; +wire [12:0] zext_ln250_4_fu_80671_p1; +wire [12:0] add_ln250_fu_80687_p2; +wire [6:0] trunc_ln203_s_fu_80697_p4; +wire [25:0] sext_ln203_fu_80707_p1; +wire [4:0] or_ln244_fu_80779_p2; +wire [11:0] shl_ln250_9_fu_80785_p3; +wire [8:0] shl_ln250_s_fu_80797_p3; +wire [12:0] zext_ln250_2_fu_80793_p1; +wire [12:0] zext_ln250_3_fu_80805_p1; +wire [2:0] tmp_25_fu_80825_p4; +wire [6:0] or_ln250_fu_80842_p2; +wire [12:0] zext_ln250_6_fu_80847_p1; +wire [5:0] or_ln250_2_fu_80851_p2; +wire [6:0] trunc_ln203_2_fu_80866_p4; +wire [25:0] sext_ln203_4_fu_80876_p1; +wire [1:0] empty_149_fu_80916_p1; +wire [3:0] tmp_39_fu_80926_p4; +wire [1:0] or_ln203_fu_80920_p2; +wire [12:0] ff4_0_0_1_0_cast41_fu_80949_p1; +wire [5:0] zext_ln250_8_fu_80959_p1; +wire [12:0] add_ln250_8_fu_80963_p2; +wire [6:0] trunc_ln203_4_fu_80973_p4; +wire [25:0] sext_ln203_6_fu_80983_p1; +wire [1:0] empty_152_fu_81030_p1; +wire [3:0] tmp_54_fu_81040_p4; +wire [1:0] or_ln203_7_fu_81034_p2; +wire [3:0] trunc_ln250_3_fu_81081_p1; +wire [12:0] zext_ln250_5_fu_81077_p1; +wire [12:0] add_ln250_2_fu_81093_p2; +wire [6:0] trunc_ln203_1_fu_81103_p4; +wire [25:0] sext_ln203_3_fu_81113_p1; +wire [2:0] tmp_38_fu_81197_p4; +wire [6:0] or_ln250_1_fu_81214_p2; +wire [12:0] zext_ln250_7_fu_81219_p1; +wire [12:0] add_ln250_6_fu_81228_p2; +wire [5:0] or_ln250_3_fu_81223_p2; +wire [6:0] trunc_ln203_3_fu_81242_p4; +wire [25:0] sext_ln203_5_fu_81252_p1; +wire [1:0] empty_157_fu_81292_p1; +wire [3:0] tmp_53_fu_81302_p4; +wire [1:0] or_ln203_6_fu_81296_p2; +wire [13:0] ff4_0_1_1_0_cast34_fu_81325_p1; +wire [5:0] zext_ln250_9_fu_81335_p1; +wire [13:0] add_ln250_9_fu_81339_p2; +wire [7:0] trunc_ln203_6_fu_81349_p4; +wire [25:0] sext_ln203_7_fu_81359_p1; +wire [1:0] empty_160_fu_81406_p1; +wire [3:0] tmp_74_fu_81416_p4; +wire [1:0] or_ln203_8_fu_81410_p2; +wire [11:0] shl_ln5_fu_81449_p3; +wire [8:0] shl_ln279_8_fu_81461_p3; +wire [12:0] zext_ln279_1_fu_81457_p1; +wire [12:0] zext_ln279_2_fu_81469_p1; +wire [6:0] shl_ln279_1_fu_81493_p3; +wire [3:0] trunc_ln279_2_fu_81505_p1; +wire [12:0] zext_ln279_7_fu_81501_p1; +wire [5:0] trunc_ln279_5_fu_81509_p3; +wire [12:0] add_ln279_fu_81517_p2; +wire [6:0] trunc_ln7_fu_81527_p4; +wire [25:0] sext_ln1265_fu_81537_p1; +wire [4:0] or_ln257_fu_81609_p2; +wire [11:0] shl_ln279_9_fu_81619_p3; +wire [8:0] shl_ln279_s_fu_81631_p3; +wire [12:0] zext_ln279_4_fu_81627_p1; +wire [12:0] zext_ln279_5_fu_81639_p1; +wire [2:0] tmp_36_fu_81663_p4; +wire [16:0] grp_fu_89982_p3; +wire [4:0] or_ln259_fu_81687_p2; +wire [6:0] shl_ln279_3_fu_81697_p3; +wire [3:0] trunc_ln279_4_fu_81709_p1; +wire [12:0] zext_ln279_11_fu_81705_p1; +wire [5:0] trunc_ln279_7_fu_81713_p3; +wire [6:0] trunc_ln1265_9_fu_81731_p4; +wire [25:0] sext_ln1265_2_fu_81741_p1; +wire [31:0] add_ln276_4_fu_81819_p2; +wire [31:0] shl_ln276_fu_81813_p2; +wire [31:0] grp_fu_81835_p0; +wire [5:0] grp_fu_81835_p1; +wire [31:0] grp_fu_81844_p0; +wire [33:0] grp_fu_81844_p1; +wire [64:0] grp_fu_81844_p2; +wire [31:0] grp_fu_81835_p2; +wire [31:0] or_ln268_fu_81991_p2; +wire [31:0] grp_fu_82008_p0; +wire [5:0] grp_fu_82008_p1; +wire [31:0] or_ln266_fu_82014_p2; +wire [31:0] add_ln276_22_fu_82032_p2; +wire [31:0] shl_ln276_4_fu_82026_p2; +wire [1:0] empty_172_fu_82043_p1; +wire [1:0] or_ln261_fu_82047_p2; +wire [3:0] tmp_89_fu_82057_p4; +wire [16:0] grp_fu_89997_p3; +wire [31:0] grp_fu_82084_p0; +wire [33:0] grp_fu_82084_p1; +wire [64:0] grp_fu_82084_p2; +wire [31:0] grp_fu_82008_p2; +wire [31:0] grp_fu_82241_p0; +wire [5:0] grp_fu_82241_p1; +wire [31:0] grp_fu_82250_p0; +wire [33:0] grp_fu_82250_p1; +wire [64:0] grp_fu_82250_p2; +wire [31:0] grp_fu_82241_p2; +wire [31:0] or_ln268_4_fu_82397_p2; +wire [31:0] grp_fu_82414_p0; +wire [5:0] grp_fu_82414_p1; +wire [31:0] grp_fu_82429_p0; +wire [33:0] grp_fu_82429_p1; +wire [64:0] grp_fu_82429_p2; +wire [31:0] grp_fu_82414_p2; +wire [31:0] add_ln276_26_fu_82587_p2; +wire [31:0] shl_ln276_5_fu_82581_p2; +wire [31:0] grp_fu_82603_p0; +wire [5:0] grp_fu_82603_p1; +wire [31:0] grp_fu_82612_p0; +wire [33:0] grp_fu_82612_p1; +wire [64:0] grp_fu_82612_p2; +wire [31:0] grp_fu_82603_p2; +wire [31:0] or_ln268_5_fu_82875_p2; +wire [31:0] grp_fu_82892_p0; +wire [5:0] grp_fu_82892_p1; +wire [31:0] or_ln266_4_fu_82898_p2; +wire [31:0] add_ln276_56_fu_82916_p2; +wire [31:0] shl_ln276_12_fu_82910_p2; +wire [31:0] grp_fu_82936_p0; +wire [33:0] grp_fu_82936_p1; +wire [64:0] grp_fu_82936_p2; +wire [31:0] grp_fu_82892_p2; +wire [31:0] grp_fu_83077_p0; +wire [5:0] grp_fu_83077_p1; +wire [31:0] grp_fu_83219_p0; +wire [33:0] grp_fu_83219_p1; +wire [64:0] grp_fu_83219_p2; +wire [31:0] grp_fu_83077_p2; +wire [31:0] or_ln268_12_fu_83349_p2; +wire [31:0] grp_fu_83366_p0; +wire [5:0] grp_fu_83366_p1; +wire [31:0] grp_fu_83381_p0; +wire [33:0] grp_fu_83381_p1; +wire [64:0] grp_fu_83381_p2; +wire [31:0] grp_fu_83366_p2; +wire [12:0] ff7_0_0_1_0_cast20_fu_83517_p1; +wire [5:0] zext_ln279_17_fu_83531_p1; +wire [12:0] add_ln279_8_fu_83535_p2; +wire [6:0] trunc_ln1265_1_fu_83549_p4; +wire [25:0] sext_ln1265_4_fu_83559_p1; +wire [16:0] grp_fu_90005_p3; +wire [31:0] add_ln276_12_fu_83646_p2; +wire [31:0] shl_ln276_2_fu_83640_p2; +wire [31:0] grp_fu_83662_p0; +wire [5:0] grp_fu_83662_p1; +wire [31:0] grp_fu_83671_p0; +wire [33:0] grp_fu_83671_p1; +wire [64:0] grp_fu_83671_p2; +wire [31:0] grp_fu_83662_p2; +wire [31:0] or_ln268_2_fu_83950_p2; +wire [31:0] grp_fu_83967_p0; +wire [5:0] grp_fu_83967_p1; +wire [31:0] or_ln266_2_fu_83973_p2; +wire [31:0] add_ln276_33_fu_83991_p2; +wire [31:0] shl_ln276_7_fu_83985_p2; +wire [1:0] empty_187_fu_84002_p1; +wire [1:0] or_ln261_2_fu_84006_p2; +wire [3:0] tmp_114_fu_84016_p4; +wire [16:0] grp_fu_90013_p3; +wire [31:0] grp_fu_84043_p0; +wire [33:0] grp_fu_84043_p1; +wire [64:0] grp_fu_84043_p2; +wire [31:0] grp_fu_83967_p2; +wire [31:0] grp_fu_84200_p0; +wire [5:0] grp_fu_84200_p1; +wire [31:0] grp_fu_84342_p0; +wire [33:0] grp_fu_84342_p1; +wire [64:0] grp_fu_84342_p2; +wire [31:0] grp_fu_84200_p2; +wire [31:0] or_ln268_7_fu_84488_p2; +wire [31:0] grp_fu_84505_p0; +wire [5:0] grp_fu_84505_p1; +wire [31:0] grp_fu_84520_p0; +wire [33:0] grp_fu_84520_p1; +wire [64:0] grp_fu_84520_p2; +wire [31:0] grp_fu_84505_p2; +wire [31:0] add_ln276_40_fu_84678_p2; +wire [31:0] shl_ln276_9_fu_84672_p2; +wire [31:0] grp_fu_84694_p0; +wire [5:0] grp_fu_84694_p1; +wire [31:0] grp_fu_84703_p0; +wire [33:0] grp_fu_84703_p1; +wire [64:0] grp_fu_84703_p2; +wire [31:0] grp_fu_84694_p2; +wire [31:0] or_ln268_9_fu_84965_p2; +wire [31:0] grp_fu_84982_p0; +wire [5:0] grp_fu_84982_p1; +wire [31:0] or_ln266_6_fu_84988_p2; +wire [31:0] add_ln276_64_fu_85006_p2; +wire [31:0] shl_ln276_14_fu_85000_p2; +wire [31:0] grp_fu_85026_p0; +wire [33:0] grp_fu_85026_p1; +wire [64:0] grp_fu_85026_p2; +wire [31:0] grp_fu_84982_p2; +wire [31:0] grp_fu_85166_p0; +wire [5:0] grp_fu_85166_p1; +wire [31:0] grp_fu_85308_p0; +wire [33:0] grp_fu_85308_p1; +wire [64:0] grp_fu_85308_p2; +wire [31:0] grp_fu_85166_p2; +wire [31:0] or_ln268_14_fu_85437_p2; +wire [31:0] grp_fu_85454_p0; +wire [5:0] grp_fu_85454_p1; +wire [31:0] grp_fu_85469_p0; +wire [33:0] grp_fu_85469_p1; +wire [64:0] grp_fu_85469_p2; +wire [31:0] grp_fu_85454_p2; +wire [6:0] shl_ln279_2_fu_85614_p3; +wire [3:0] trunc_ln279_3_fu_85626_p1; +wire [12:0] zext_ln279_9_fu_85622_p1; +wire [5:0] trunc_ln279_6_fu_85630_p3; +wire [12:0] add_ln279_2_fu_85638_p2; +wire [6:0] trunc_ln1265_8_fu_85648_p4; +wire [25:0] sext_ln1265_1_fu_85658_p1; +wire [2:0] tmp_48_fu_85746_p4; +wire [16:0] grp_fu_90028_p3; +wire [4:0] or_ln259_1_fu_85770_p2; +wire [6:0] shl_ln279_4_fu_85780_p3; +wire [3:0] trunc_ln279_9_fu_85792_p1; +wire [12:0] zext_ln279_14_fu_85788_p1; +wire [5:0] trunc_ln279_8_fu_85796_p3; +wire [6:0] trunc_ln1265_s_fu_85814_p4; +wire [25:0] sext_ln1265_3_fu_85824_p1; +wire [31:0] add_ln276_10_fu_85902_p2; +wire [31:0] shl_ln276_1_fu_85896_p2; +wire [31:0] grp_fu_85918_p0; +wire [5:0] grp_fu_85918_p1; +wire [31:0] grp_fu_85927_p0; +wire [33:0] grp_fu_85927_p1; +wire [64:0] grp_fu_85927_p2; +wire [31:0] grp_fu_85918_p2; +wire [31:0] or_ln268_1_fu_86206_p2; +wire [31:0] grp_fu_86223_p0; +wire [5:0] grp_fu_86223_p1; +wire [31:0] or_ln266_1_fu_86229_p2; +wire [31:0] add_ln276_30_fu_86247_p2; +wire [31:0] shl_ln276_6_fu_86241_p2; +wire [1:0] empty_204_fu_86258_p1; +wire [1:0] or_ln261_1_fu_86262_p2; +wire [3:0] tmp_111_fu_86272_p4; +wire [16:0] grp_fu_90043_p3; +wire [31:0] grp_fu_86299_p0; +wire [33:0] grp_fu_86299_p1; +wire [64:0] grp_fu_86299_p2; +wire [31:0] grp_fu_86223_p2; +wire [31:0] grp_fu_86456_p0; +wire [5:0] grp_fu_86456_p1; +wire [31:0] grp_fu_86598_p0; +wire [33:0] grp_fu_86598_p1; +wire [64:0] grp_fu_86598_p2; +wire [31:0] grp_fu_86456_p2; +wire [31:0] or_ln268_6_fu_86744_p2; +wire [31:0] grp_fu_86761_p0; +wire [5:0] grp_fu_86761_p1; +wire [31:0] grp_fu_86776_p0; +wire [33:0] grp_fu_86776_p1; +wire [64:0] grp_fu_86776_p2; +wire [31:0] grp_fu_86761_p2; +wire [31:0] add_ln276_37_fu_86934_p2; +wire [31:0] shl_ln276_8_fu_86928_p2; +wire [31:0] grp_fu_86950_p0; +wire [5:0] grp_fu_86950_p1; +wire [31:0] grp_fu_86959_p0; +wire [33:0] grp_fu_86959_p1; +wire [64:0] grp_fu_86959_p2; +wire [31:0] grp_fu_86950_p2; +wire [31:0] or_ln268_8_fu_87222_p2; +wire [31:0] grp_fu_87239_p0; +wire [5:0] grp_fu_87239_p1; +wire [31:0] or_ln266_5_fu_87245_p2; +wire [31:0] add_ln276_62_fu_87263_p2; +wire [31:0] shl_ln276_13_fu_87257_p2; +wire [31:0] grp_fu_87283_p0; +wire [33:0] grp_fu_87283_p1; +wire [64:0] grp_fu_87283_p2; +wire [31:0] grp_fu_87239_p2; +wire [31:0] grp_fu_87424_p0; +wire [5:0] grp_fu_87424_p1; +wire [31:0] grp_fu_87566_p0; +wire [33:0] grp_fu_87566_p1; +wire [64:0] grp_fu_87566_p2; +wire [31:0] grp_fu_87424_p2; +wire [31:0] or_ln268_13_fu_87696_p2; +wire [31:0] grp_fu_87713_p0; +wire [5:0] grp_fu_87713_p1; +wire [31:0] grp_fu_87728_p0; +wire [33:0] grp_fu_87728_p1; +wire [64:0] grp_fu_87728_p2; +wire [31:0] grp_fu_87713_p2; +wire [12:0] ff7_0_1_1_0_cast4_fu_87864_p1; +wire [5:0] zext_ln279_19_fu_87878_p1; +wire [12:0] add_ln279_9_fu_87882_p2; +wire [6:0] trunc_ln1265_2_fu_87896_p4; +wire [25:0] sext_ln1265_5_fu_87906_p1; +wire [16:0] grp_fu_90051_p3; +wire [31:0] add_ln276_17_fu_87993_p2; +wire [31:0] shl_ln276_3_fu_87987_p2; +wire [31:0] grp_fu_88009_p0; +wire [5:0] grp_fu_88009_p1; +wire [31:0] grp_fu_88018_p0; +wire [33:0] grp_fu_88018_p1; +wire [64:0] grp_fu_88018_p2; +wire [31:0] grp_fu_88009_p2; +wire [31:0] or_ln268_3_fu_88297_p2; +wire [31:0] grp_fu_88314_p0; +wire [5:0] grp_fu_88314_p1; +wire [31:0] or_ln266_3_fu_88320_p2; +wire [31:0] add_ln276_44_fu_88338_p2; +wire [31:0] shl_ln276_10_fu_88332_p2; +wire [1:0] empty_219_fu_88349_p1; +wire [1:0] or_ln261_3_fu_88353_p2; +wire [3:0] tmp_148_fu_88363_p4; +wire [16:0] grp_fu_90059_p3; +wire [31:0] grp_fu_88390_p0; +wire [33:0] grp_fu_88390_p1; +wire [64:0] grp_fu_88390_p2; +wire [31:0] grp_fu_88314_p2; +wire [31:0] grp_fu_88547_p0; +wire [5:0] grp_fu_88547_p1; +wire [31:0] grp_fu_88689_p0; +wire [33:0] grp_fu_88689_p1; +wire [64:0] grp_fu_88689_p2; +wire [31:0] grp_fu_88547_p2; +wire [31:0] or_ln268_10_fu_88835_p2; +wire [31:0] grp_fu_88852_p0; +wire [5:0] grp_fu_88852_p1; +wire [31:0] grp_fu_88867_p0; +wire [33:0] grp_fu_88867_p1; +wire [64:0] grp_fu_88867_p2; +wire [31:0] grp_fu_88852_p2; +wire [31:0] add_ln276_49_fu_89025_p2; +wire [31:0] shl_ln276_11_fu_89019_p2; +wire [31:0] grp_fu_89041_p0; +wire [5:0] grp_fu_89041_p1; +wire [31:0] grp_fu_89050_p0; +wire [33:0] grp_fu_89050_p1; +wire [64:0] grp_fu_89050_p2; +wire [31:0] grp_fu_89041_p2; +wire [31:0] or_ln268_11_fu_89312_p2; +wire [31:0] grp_fu_89329_p0; +wire [5:0] grp_fu_89329_p1; +wire [31:0] or_ln266_7_fu_89335_p2; +wire [31:0] add_ln276_69_fu_89353_p2; +wire [31:0] shl_ln276_15_fu_89347_p2; +wire [31:0] grp_fu_89373_p0; +wire [33:0] grp_fu_89373_p1; +wire [64:0] grp_fu_89373_p2; +wire [31:0] grp_fu_89329_p2; +wire [31:0] grp_fu_89513_p0; +wire [5:0] grp_fu_89513_p1; +wire [31:0] grp_fu_89655_p0; +wire [33:0] grp_fu_89655_p1; +wire [64:0] grp_fu_89655_p2; +wire [31:0] grp_fu_89513_p2; +wire [31:0] or_ln268_15_fu_89784_p2; +wire [31:0] grp_fu_89801_p0; +wire [5:0] grp_fu_89801_p1; +wire [31:0] grp_fu_89816_p0; +wire [33:0] grp_fu_89816_p1; +wire [64:0] grp_fu_89816_p2; +wire [31:0] grp_fu_89801_p2; +wire [4:0] mul_ln201_fu_89951_p0; +wire [12:0] mul_ln201_fu_89951_p1; +wire [4:0] mul_ln201_1_fu_89957_p0; +wire [12:0] mul_ln201_1_fu_89957_p1; +wire [12:0] mul_ln279_fu_89963_p0; +wire [4:0] mul_ln279_fu_89963_p1; +wire [7:0] grp_fu_89969_p0; +wire [4:0] grp_fu_89969_p1; +wire [12:0] mul_ln279_1_fu_89976_p0; +wire [4:0] mul_ln279_1_fu_89976_p1; +wire [2:0] grp_fu_89982_p0; +wire [5:0] grp_fu_89982_p1; +wire [7:0] grp_fu_89990_p0; +wire [4:0] grp_fu_89990_p1; +wire [5:0] grp_fu_89997_p0; +wire [1:0] grp_fu_89997_p1; +wire [2:0] grp_fu_90005_p0; +wire [5:0] grp_fu_90005_p1; +wire [5:0] grp_fu_90013_p0; +wire [1:0] grp_fu_90013_p1; +wire [7:0] grp_fu_90021_p0; +wire [4:0] grp_fu_90021_p1; +wire [2:0] grp_fu_90028_p0; +wire [5:0] grp_fu_90028_p1; +wire [7:0] grp_fu_90036_p0; +wire [4:0] grp_fu_90036_p1; +wire [5:0] grp_fu_90043_p0; +wire [1:0] grp_fu_90043_p1; +wire [2:0] grp_fu_90051_p0; +wire [5:0] grp_fu_90051_p1; +wire [5:0] grp_fu_90059_p0; +wire [1:0] grp_fu_90059_p1; +reg grp_fu_73372_ap_start; +wire grp_fu_73372_ap_done; +reg grp_fu_73378_ap_start; +wire grp_fu_73378_ap_done; +reg grp_fu_73388_ap_start; +wire grp_fu_73388_ap_done; +reg grp_fu_73394_ap_start; +wire grp_fu_73394_ap_done; +reg grp_fu_73404_ap_start; +wire grp_fu_73404_ap_done; +reg grp_fu_73410_ap_start; +wire grp_fu_73410_ap_done; +reg grp_fu_73420_ap_start; +wire grp_fu_73420_ap_done; +reg grp_fu_73426_ap_start; +wire grp_fu_73426_ap_done; +reg grp_fu_73436_ap_start; +wire grp_fu_73436_ap_done; +reg grp_fu_73442_ap_start; +wire grp_fu_73442_ap_done; +reg grp_fu_73452_ap_start; +wire grp_fu_73452_ap_done; +reg grp_fu_73458_ap_start; +wire grp_fu_73458_ap_done; +reg grp_fu_73468_ap_start; +wire grp_fu_73468_ap_done; +reg grp_fu_73474_ap_start; +wire grp_fu_73474_ap_done; +reg grp_fu_73484_ap_start; +wire grp_fu_73484_ap_done; +reg grp_fu_73490_ap_start; +wire grp_fu_73490_ap_done; +reg grp_fu_81835_ap_start; +wire grp_fu_81835_ap_done; +reg grp_fu_82008_ap_start; +wire grp_fu_82008_ap_done; +reg grp_fu_82241_ap_start; +wire grp_fu_82241_ap_done; +reg grp_fu_82414_ap_start; +wire grp_fu_82414_ap_done; +reg grp_fu_82603_ap_start; +wire grp_fu_82603_ap_done; +reg grp_fu_82892_ap_start; +wire grp_fu_82892_ap_done; +reg grp_fu_83077_ap_start; +wire grp_fu_83077_ap_done; +reg grp_fu_83366_ap_start; +wire grp_fu_83366_ap_done; +reg grp_fu_83662_ap_start; +wire grp_fu_83662_ap_done; +reg grp_fu_83967_ap_start; +wire grp_fu_83967_ap_done; +reg grp_fu_84200_ap_start; +wire grp_fu_84200_ap_done; +reg grp_fu_84505_ap_start; +wire grp_fu_84505_ap_done; +reg grp_fu_84694_ap_start; +wire grp_fu_84694_ap_done; +reg grp_fu_84982_ap_start; +wire grp_fu_84982_ap_done; +reg grp_fu_85166_ap_start; +wire grp_fu_85166_ap_done; +reg grp_fu_85454_ap_start; +wire grp_fu_85454_ap_done; +reg grp_fu_85918_ap_start; +wire grp_fu_85918_ap_done; +reg grp_fu_86223_ap_start; +wire grp_fu_86223_ap_done; +reg grp_fu_86456_ap_start; +wire grp_fu_86456_ap_done; +reg grp_fu_86761_ap_start; +wire grp_fu_86761_ap_done; +reg grp_fu_86950_ap_start; +wire grp_fu_86950_ap_done; +reg grp_fu_87239_ap_start; +wire grp_fu_87239_ap_done; +reg grp_fu_87424_ap_start; +wire grp_fu_87424_ap_done; +reg grp_fu_87713_ap_start; +wire grp_fu_87713_ap_done; +reg grp_fu_88009_ap_start; +wire grp_fu_88009_ap_done; +reg grp_fu_88314_ap_start; +wire grp_fu_88314_ap_done; +reg grp_fu_88547_ap_start; +wire grp_fu_88547_ap_done; +reg grp_fu_88852_ap_start; +wire grp_fu_88852_ap_done; +reg grp_fu_89041_ap_start; +wire grp_fu_89041_ap_done; +reg grp_fu_89329_ap_start; +wire grp_fu_89329_ap_done; +reg grp_fu_89513_ap_start; +wire grp_fu_89513_ap_done; +reg grp_fu_89801_ap_start; +wire grp_fu_89801_ap_done; +reg [11:0] ap_NS_fsm; +wire [64:0] grp_fu_73985_p10; +wire [64:0] grp_fu_74429_p10; +wire [64:0] grp_fu_74642_p10; +wire [64:0] grp_fu_74702_p10; +wire [64:0] grp_fu_74810_p10; +wire [64:0] grp_fu_75174_p10; +wire [64:0] grp_fu_75365_p10; +wire [64:0] grp_fu_75425_p10; +wire [64:0] grp_fu_75685_p10; +wire [64:0] grp_fu_76119_p10; +wire [64:0] grp_fu_76332_p10; +wire [64:0] grp_fu_76392_p10; +wire [64:0] grp_fu_76500_p10; +wire [64:0] grp_fu_76854_p10; +wire [64:0] grp_fu_77045_p10; +wire [64:0] grp_fu_77105_p10; +wire [64:0] grp_fu_77447_p10; +wire [64:0] grp_fu_77890_p10; +wire [64:0] grp_fu_78102_p10; +wire [64:0] grp_fu_78162_p10; +wire [64:0] grp_fu_78270_p10; +wire [64:0] grp_fu_78634_p10; +wire [64:0] grp_fu_78825_p10; +wire [64:0] grp_fu_78885_p10; +wire [64:0] grp_fu_79149_p10; +wire [64:0] grp_fu_79602_p10; +wire [64:0] grp_fu_79793_p10; +wire [64:0] grp_fu_79853_p10; +wire [64:0] grp_fu_79961_p10; +wire [64:0] grp_fu_80315_p10; +wire [64:0] grp_fu_80506_p10; +wire [64:0] grp_fu_80566_p10; +wire [64:0] grp_fu_81844_p00; +wire [64:0] grp_fu_82084_p00; +wire [64:0] grp_fu_82250_p00; +wire [64:0] grp_fu_82429_p00; +wire [64:0] grp_fu_82612_p00; +wire [64:0] grp_fu_82936_p00; +wire [64:0] grp_fu_83219_p00; +wire [64:0] grp_fu_83381_p00; +wire [64:0] grp_fu_83671_p00; +wire [64:0] grp_fu_84043_p00; +wire [64:0] grp_fu_84342_p00; +wire [64:0] grp_fu_84520_p00; +wire [64:0] grp_fu_84703_p00; +wire [64:0] grp_fu_85026_p00; +wire [64:0] grp_fu_85308_p00; +wire [64:0] grp_fu_85469_p00; +wire [64:0] grp_fu_85927_p00; +wire [64:0] grp_fu_86299_p00; +wire [64:0] grp_fu_86598_p00; +wire [64:0] grp_fu_86776_p00; +wire [64:0] grp_fu_86959_p00; +wire [64:0] grp_fu_87283_p00; +wire [64:0] grp_fu_87566_p00; +wire [64:0] grp_fu_87728_p00; +wire [64:0] grp_fu_88018_p00; +wire [64:0] grp_fu_88390_p00; +wire [64:0] grp_fu_88689_p00; +wire [64:0] grp_fu_88867_p00; +wire [64:0] grp_fu_89050_p00; +wire [64:0] grp_fu_89373_p00; +wire [64:0] grp_fu_89655_p00; +wire [64:0] grp_fu_89816_p00; +wire [12:0] grp_fu_89969_p10; +wire [8:0] grp_fu_89982_p00; +wire [12:0] grp_fu_89990_p10; +wire [7:0] grp_fu_89997_p10; +wire [8:0] grp_fu_90005_p00; +wire [7:0] grp_fu_90013_p10; +wire [12:0] grp_fu_90021_p10; +wire [8:0] grp_fu_90028_p00; +wire [12:0] grp_fu_90036_p10; +wire [7:0] grp_fu_90043_p10; +wire [8:0] grp_fu_90051_p00; +wire [7:0] grp_fu_90059_p10; +wire [16:0] mul_ln201_1_fu_89957_p00; +wire [16:0] mul_ln201_fu_89951_p00; +wire [11:0] mul_ln231_1_fu_77170_p10; +wire [11:0] mul_ln231_2_fu_73806_p00; +wire [11:0] mul_ln231_3_fu_77264_p00; +wire [11:0] mul_ln231_fu_73704_p10; +wire [16:0] mul_ln279_1_fu_89976_p10; +wire [16:0] mul_ln279_fu_89963_p10; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 12'd0; +end + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_w2_V #( + .DataWidth( 5 ), + .AddressRange( 100 ), + .AddressWidth( 7 )) +w2_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(w2_V_address0), + .ce0(w2_V_ce0), + .q0(w2_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_0_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_0_V_address0), + .ce0(mult_0_V_ce0), + .we0(mult_0_V_we0), + .d0(mult_0_V_d0), + .q0(mult_0_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_1_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_1_V_address0), + .ce0(mult_1_V_ce0), + .we0(mult_1_V_we0), + .d0(mult_1_V_d0), + .q0(mult_1_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_2_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_2_V_address0), + .ce0(mult_2_V_ce0), + .we0(mult_2_V_we0), + .d0(mult_2_V_d0), + .q0(mult_2_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_3_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_3_V_address0), + .ce0(mult_3_V_ce0), + .we0(mult_3_V_we0), + .d0(mult_3_V_d0), + .q0(mult_3_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_4_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_4_V_address0), + .ce0(mult_4_V_ce0), + .we0(mult_4_V_we0), + .d0(mult_4_V_d0), + .q0(mult_4_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_5_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_5_V_address0), + .ce0(mult_5_V_ce0), + .we0(mult_5_V_we0), + .d0(mult_5_V_d0), + .q0(mult_5_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_6_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_6_V_address0), + .ce0(mult_6_V_ce0), + .we0(mult_6_V_we0), + .d0(mult_6_V_d0), + .q0(mult_6_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_7_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_7_V_address0), + .ce0(mult_7_V_ce0), + .we0(mult_7_V_we0), + .d0(mult_7_V_d0), + .q0(mult_7_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_8_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_8_V_address0), + .ce0(mult_8_V_ce0), + .we0(mult_8_V_we0), + .d0(mult_8_V_d0), + .q0(mult_8_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_9_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_9_V_address0), + .ce0(mult_9_V_ce0), + .we0(mult_9_V_we0), + .d0(mult_9_V_d0), + .q0(mult_9_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_10_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_10_V_address0), + .ce0(mult_10_V_ce0), + .we0(mult_10_V_we0), + .d0(mult_10_V_d0), + .q0(mult_10_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_11_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_11_V_address0), + .ce0(mult_11_V_ce0), + .we0(mult_11_V_we0), + .d0(mult_11_V_d0), + .q0(mult_11_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_12_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_12_V_address0), + .ce0(mult_12_V_ce0), + .we0(mult_12_V_we0), + .d0(mult_12_V_d0), + .q0(mult_12_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_13_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_13_V_address0), + .ce0(mult_13_V_ce0), + .we0(mult_13_V_we0), + .d0(mult_13_V_d0), + .q0(mult_13_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_14_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_14_V_address0), + .ce0(mult_14_V_ce0), + .we0(mult_14_V_we0), + .d0(mult_14_V_d0), + .q0(mult_14_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_15_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_15_V_address0), + .ce0(mult_15_V_ce0), + .we0(mult_15_V_we0), + .d0(mult_15_V_d0), + .q0(mult_15_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_16_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_16_V_address0), + .ce0(mult_16_V_ce0), + .we0(mult_16_V_we0), + .d0(mult_16_V_d0), + .q0(mult_16_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_17_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_17_V_address0), + .ce0(mult_17_V_ce0), + .we0(mult_17_V_we0), + .d0(mult_17_V_d0), + .q0(mult_17_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_18_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_18_V_address0), + .ce0(mult_18_V_ce0), + .we0(mult_18_V_we0), + .d0(mult_18_V_d0), + .q0(mult_18_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_19_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_19_V_address0), + .ce0(mult_19_V_ce0), + .we0(mult_19_V_we0), + .d0(mult_19_V_d0), + .q0(mult_19_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_20_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_20_V_address0), + .ce0(mult_20_V_ce0), + .we0(mult_20_V_we0), + .d0(mult_20_V_d0), + .q0(mult_20_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_21_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_21_V_address0), + .ce0(mult_21_V_ce0), + .we0(mult_21_V_we0), + .d0(mult_21_V_d0), + .q0(mult_21_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_22_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_22_V_address0), + .ce0(mult_22_V_ce0), + .we0(mult_22_V_we0), + .d0(mult_22_V_d0), + .q0(mult_22_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_23_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_23_V_address0), + .ce0(mult_23_V_ce0), + .we0(mult_23_V_we0), + .d0(mult_23_V_d0), + .q0(mult_23_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_24_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_24_V_address0), + .ce0(mult_24_V_ce0), + .we0(mult_24_V_we0), + .d0(mult_24_V_d0), + .q0(mult_24_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_25_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_25_V_address0), + .ce0(mult_25_V_ce0), + .we0(mult_25_V_we0), + .d0(mult_25_V_d0), + .q0(mult_25_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_26_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_26_V_address0), + .ce0(mult_26_V_ce0), + .we0(mult_26_V_we0), + .d0(mult_26_V_d0), + .q0(mult_26_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_mubkb #( + .DataWidth( 8 ), + .AddressRange( 2800 ), + .AddressWidth( 12 )) +mult_27_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(mult_27_V_address0), + .ce0(mult_27_V_ce0), + .we0(mult_27_V_we0), + .d0(mult_27_V_d0), + .q0(mult_27_V_q0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_0_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_0_V_address0), + .ce0(acc_0_V_ce0), + .we0(acc_0_V_we0), + .d0(acc_0_V_d0), + .q0(acc_0_V_q0), + .address1(acc_0_V_address1), + .ce1(acc_0_V_ce1), + .we1(acc_0_V_we1), + .d1(acc_0_V_d1), + .q1(acc_0_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_1_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_1_V_address0), + .ce0(acc_1_V_ce0), + .we0(acc_1_V_we0), + .d0(acc_1_V_d0), + .q0(acc_1_V_q0), + .address1(acc_1_V_address1), + .ce1(acc_1_V_ce1), + .we1(acc_1_V_we1), + .d1(acc_1_V_d1), + .q1(acc_1_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_2_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_2_V_address0), + .ce0(acc_2_V_ce0), + .we0(acc_2_V_we0), + .d0(acc_2_V_d0), + .q0(acc_2_V_q0), + .address1(acc_2_V_address1), + .ce1(acc_2_V_ce1), + .we1(acc_2_V_we1), + .d1(acc_2_V_d1), + .q1(acc_2_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_3_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_3_V_address0), + .ce0(acc_3_V_ce0), + .we0(acc_3_V_we0), + .d0(acc_3_V_d0), + .q0(acc_3_V_q0), + .address1(acc_3_V_address1), + .ce1(acc_3_V_ce1), + .we1(acc_3_V_we1), + .d1(acc_3_V_d1), + .q1(acc_3_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_4_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_4_V_address0), + .ce0(acc_4_V_ce0), + .we0(acc_4_V_we0), + .d0(acc_4_V_d0), + .q0(acc_4_V_q0), + .address1(acc_4_V_address1), + .ce1(acc_4_V_ce1), + .we1(acc_4_V_we1), + .d1(acc_4_V_d1), + .q1(acc_4_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_5_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_5_V_address0), + .ce0(acc_5_V_ce0), + .we0(acc_5_V_we0), + .d0(acc_5_V_d0), + .q0(acc_5_V_q0), + .address1(acc_5_V_address1), + .ce1(acc_5_V_ce1), + .we1(acc_5_V_we1), + .d1(acc_5_V_d1), + .q1(acc_5_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_6_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_6_V_address0), + .ce0(acc_6_V_ce0), + .we0(acc_6_V_we0), + .d0(acc_6_V_d0), + .q0(acc_6_V_q0), + .address1(acc_6_V_address1), + .ce1(acc_6_V_ce1), + .we1(acc_6_V_we1), + .d1(acc_6_V_d1), + .q1(acc_6_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_7_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_7_V_address0), + .ce0(acc_7_V_ce0), + .we0(acc_7_V_we0), + .d0(acc_7_V_d0), + .q0(acc_7_V_q0), + .address1(acc_7_V_address1), + .ce1(acc_7_V_ce1), + .we1(acc_7_V_we1), + .d1(acc_7_V_d1), + .q1(acc_7_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_8_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_8_V_address0), + .ce0(acc_8_V_ce0), + .we0(acc_8_V_we0), + .d0(acc_8_V_d0), + .q0(acc_8_V_q0), + .address1(acc_8_V_address1), + .ce1(acc_8_V_ce1), + .we1(acc_8_V_we1), + .d1(acc_8_V_d1), + .q1(acc_8_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_9_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_9_V_address0), + .ce0(acc_9_V_ce0), + .we0(acc_9_V_we0), + .d0(acc_9_V_d0), + .q0(acc_9_V_q0), + .address1(acc_9_V_address1), + .ce1(acc_9_V_ce1), + .we1(acc_9_V_we1), + .d1(acc_9_V_d1), + .q1(acc_9_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_10_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_10_V_address0), + .ce0(acc_10_V_ce0), + .we0(acc_10_V_we0), + .d0(acc_10_V_d0), + .q0(acc_10_V_q0), + .address1(acc_10_V_address1), + .ce1(acc_10_V_ce1), + .we1(acc_10_V_we1), + .d1(acc_10_V_d1), + .q1(acc_10_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_11_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_11_V_address0), + .ce0(acc_11_V_ce0), + .we0(acc_11_V_we0), + .d0(acc_11_V_d0), + .q0(acc_11_V_q0), + .address1(acc_11_V_address1), + .ce1(acc_11_V_ce1), + .we1(acc_11_V_we1), + .d1(acc_11_V_d1), + .q1(acc_11_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_12_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_12_V_address0), + .ce0(acc_12_V_ce0), + .we0(acc_12_V_we0), + .d0(acc_12_V_d0), + .q0(acc_12_V_q0), + .address1(acc_12_V_address1), + .ce1(acc_12_V_ce1), + .we1(acc_12_V_we1), + .d1(acc_12_V_d1), + .q1(acc_12_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_13_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_13_V_address0), + .ce0(acc_13_V_ce0), + .we0(acc_13_V_we0), + .d0(acc_13_V_d0), + .q0(acc_13_V_q0), + .address1(acc_13_V_address1), + .ce1(acc_13_V_ce1), + .we1(acc_13_V_we1), + .d1(acc_13_V_d1), + .q1(acc_13_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_14_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_14_V_address0), + .ce0(acc_14_V_ce0), + .we0(acc_14_V_we0), + .d0(acc_14_V_d0), + .q0(acc_14_V_q0), + .address1(acc_14_V_address1), + .ce1(acc_14_V_ce1), + .we1(acc_14_V_we1), + .d1(acc_14_V_d1), + .q1(acc_14_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_15_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_15_V_address0), + .ce0(acc_15_V_ce0), + .we0(acc_15_V_we0), + .d0(acc_15_V_d0), + .q0(acc_15_V_q0), + .address1(acc_15_V_address1), + .ce1(acc_15_V_ce1), + .we1(acc_15_V_we1), + .d1(acc_15_V_d1), + .q1(acc_15_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_16_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_16_V_address0), + .ce0(acc_16_V_ce0), + .we0(acc_16_V_we0), + .d0(acc_16_V_d0), + .q0(acc_16_V_q0), + .address1(acc_16_V_address1), + .ce1(acc_16_V_ce1), + .we1(acc_16_V_we1), + .d1(acc_16_V_d1), + .q1(acc_16_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_17_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_17_V_address0), + .ce0(acc_17_V_ce0), + .we0(acc_17_V_we0), + .d0(acc_17_V_d0), + .q0(acc_17_V_q0), + .address1(acc_17_V_address1), + .ce1(acc_17_V_ce1), + .we1(acc_17_V_we1), + .d1(acc_17_V_d1), + .q1(acc_17_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_18_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_18_V_address0), + .ce0(acc_18_V_ce0), + .we0(acc_18_V_we0), + .d0(acc_18_V_d0), + .q0(acc_18_V_q0), + .address1(acc_18_V_address1), + .ce1(acc_18_V_ce1), + .we1(acc_18_V_we1), + .d1(acc_18_V_d1), + .q1(acc_18_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_19_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_19_V_address0), + .ce0(acc_19_V_ce0), + .we0(acc_19_V_we0), + .d0(acc_19_V_d0), + .q0(acc_19_V_q0), + .address1(acc_19_V_address1), + .ce1(acc_19_V_ce1), + .we1(acc_19_V_we1), + .d1(acc_19_V_d1), + .q1(acc_19_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_20_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_20_V_address0), + .ce0(acc_20_V_ce0), + .we0(acc_20_V_we0), + .d0(acc_20_V_d0), + .q0(acc_20_V_q0), + .address1(acc_20_V_address1), + .ce1(acc_20_V_ce1), + .we1(acc_20_V_we1), + .d1(acc_20_V_d1), + .q1(acc_20_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_21_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_21_V_address0), + .ce0(acc_21_V_ce0), + .we0(acc_21_V_we0), + .d0(acc_21_V_d0), + .q0(acc_21_V_q0), + .address1(acc_21_V_address1), + .ce1(acc_21_V_ce1), + .we1(acc_21_V_we1), + .d1(acc_21_V_d1), + .q1(acc_21_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_22_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_22_V_address0), + .ce0(acc_22_V_ce0), + .we0(acc_22_V_we0), + .d0(acc_22_V_d0), + .q0(acc_22_V_q0), + .address1(acc_22_V_address1), + .ce1(acc_22_V_ce1), + .we1(acc_22_V_we1), + .d1(acc_22_V_d1), + .q1(acc_22_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_23_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_23_V_address0), + .ce0(acc_23_V_ce0), + .we0(acc_23_V_we0), + .d0(acc_23_V_d0), + .q0(acc_23_V_q0), + .address1(acc_23_V_address1), + .ce1(acc_23_V_ce1), + .we1(acc_23_V_we1), + .d1(acc_23_V_d1), + .q1(acc_23_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_24_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_24_V_address0), + .ce0(acc_24_V_ce0), + .we0(acc_24_V_we0), + .d0(acc_24_V_d0), + .q0(acc_24_V_q0), + .address1(acc_24_V_address1), + .ce1(acc_24_V_ce1), + .we1(acc_24_V_we1), + .d1(acc_24_V_d1), + .q1(acc_24_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_25_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_25_V_address0), + .ce0(acc_25_V_ce0), + .we0(acc_25_V_we0), + .d0(acc_25_V_d0), + .q0(acc_25_V_q0), + .address1(acc_25_V_address1), + .ce1(acc_25_V_ce1), + .we1(acc_25_V_we1), + .d1(acc_25_V_d1), + .q1(acc_25_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_26_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_26_V_address0), + .ce0(acc_26_V_ce0), + .we0(acc_26_V_we0), + .d0(acc_26_V_d0), + .q0(acc_26_V_q0), + .address1(acc_26_V_address1), + .ce1(acc_26_V_ce1), + .we1(acc_26_V_we1), + .d1(acc_26_V_d1), + .q1(acc_26_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_27_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_27_V_address0), + .ce0(acc_27_V_ce0), + .we0(acc_27_V_we0), + .d0(acc_27_V_d0), + .q0(acc_27_V_q0), + .address1(acc_27_V_address1), + .ce1(acc_27_V_ce1), + .we1(acc_27_V_we1), + .d1(acc_27_V_d1), + .q1(acc_27_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_28_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_28_V_address0), + .ce0(acc_28_V_ce0), + .we0(acc_28_V_we0), + .d0(acc_28_V_d0), + .q0(acc_28_V_q0), + .address1(acc_28_V_address1), + .ce1(acc_28_V_ce1), + .we1(acc_28_V_we1), + .d1(acc_28_V_d1), + .q1(acc_28_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_29_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_29_V_address0), + .ce0(acc_29_V_ce0), + .we0(acc_29_V_we0), + .d0(acc_29_V_d0), + .q0(acc_29_V_q0), + .address1(acc_29_V_address1), + .ce1(acc_29_V_ce1), + .we1(acc_29_V_we1), + .d1(acc_29_V_d1), + .q1(acc_29_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_30_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_30_V_address0), + .ce0(acc_30_V_ce0), + .we0(acc_30_V_we0), + .d0(acc_30_V_d0), + .q0(acc_30_V_q0), + .address1(acc_30_V_address1), + .ce1(acc_30_V_ce1), + .we1(acc_30_V_we1), + .d1(acc_30_V_d1), + .q1(acc_30_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_31_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_31_V_address0), + .ce0(acc_31_V_ce0), + .we0(acc_31_V_we0), + .d0(acc_31_V_d0), + .q0(acc_31_V_q0), + .address1(acc_31_V_address1), + .ce1(acc_31_V_ce1), + .we1(acc_31_V_we1), + .d1(acc_31_V_d1), + .q1(acc_31_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_32_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_32_V_address0), + .ce0(acc_32_V_ce0), + .we0(acc_32_V_we0), + .d0(acc_32_V_d0), + .q0(acc_32_V_q0), + .address1(acc_32_V_address1), + .ce1(acc_32_V_ce1), + .we1(acc_32_V_we1), + .d1(acc_32_V_d1), + .q1(acc_32_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_33_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_33_V_address0), + .ce0(acc_33_V_ce0), + .we0(acc_33_V_we0), + .d0(acc_33_V_d0), + .q0(acc_33_V_q0), + .address1(acc_33_V_address1), + .ce1(acc_33_V_ce1), + .we1(acc_33_V_we1), + .d1(acc_33_V_d1), + .q1(acc_33_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_34_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_34_V_address0), + .ce0(acc_34_V_ce0), + .we0(acc_34_V_we0), + .d0(acc_34_V_d0), + .q0(acc_34_V_q0), + .address1(acc_34_V_address1), + .ce1(acc_34_V_ce1), + .we1(acc_34_V_we1), + .d1(acc_34_V_d1), + .q1(acc_34_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_35_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_35_V_address0), + .ce0(acc_35_V_ce0), + .we0(acc_35_V_we0), + .d0(acc_35_V_d0), + .q0(acc_35_V_q0), + .address1(acc_35_V_address1), + .ce1(acc_35_V_ce1), + .we1(acc_35_V_we1), + .d1(acc_35_V_d1), + .q1(acc_35_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_36_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_36_V_address0), + .ce0(acc_36_V_ce0), + .we0(acc_36_V_we0), + .d0(acc_36_V_d0), + .q0(acc_36_V_q0), + .address1(acc_36_V_address1), + .ce1(acc_36_V_ce1), + .we1(acc_36_V_we1), + .d1(acc_36_V_d1), + .q1(acc_36_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_37_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_37_V_address0), + .ce0(acc_37_V_ce0), + .we0(acc_37_V_we0), + .d0(acc_37_V_d0), + .q0(acc_37_V_q0), + .address1(acc_37_V_address1), + .ce1(acc_37_V_ce1), + .we1(acc_37_V_we1), + .d1(acc_37_V_d1), + .q1(acc_37_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_38_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_38_V_address0), + .ce0(acc_38_V_ce0), + .we0(acc_38_V_we0), + .d0(acc_38_V_d0), + .q0(acc_38_V_q0), + .address1(acc_38_V_address1), + .ce1(acc_38_V_ce1), + .we1(acc_38_V_we1), + .d1(acc_38_V_d1), + .q1(acc_38_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_39_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_39_V_address0), + .ce0(acc_39_V_ce0), + .we0(acc_39_V_we0), + .d0(acc_39_V_d0), + .q0(acc_39_V_q0), + .address1(acc_39_V_address1), + .ce1(acc_39_V_ce1), + .we1(acc_39_V_we1), + .d1(acc_39_V_d1), + .q1(acc_39_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_40_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_40_V_address0), + .ce0(acc_40_V_ce0), + .we0(acc_40_V_we0), + .d0(acc_40_V_d0), + .q0(acc_40_V_q0), + .address1(acc_40_V_address1), + .ce1(acc_40_V_ce1), + .we1(acc_40_V_we1), + .d1(acc_40_V_d1), + .q1(acc_40_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_41_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_41_V_address0), + .ce0(acc_41_V_ce0), + .we0(acc_41_V_we0), + .d0(acc_41_V_d0), + .q0(acc_41_V_q0), + .address1(acc_41_V_address1), + .ce1(acc_41_V_ce1), + .we1(acc_41_V_we1), + .d1(acc_41_V_d1), + .q1(acc_41_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_42_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_42_V_address0), + .ce0(acc_42_V_ce0), + .we0(acc_42_V_we0), + .d0(acc_42_V_d0), + .q0(acc_42_V_q0), + .address1(acc_42_V_address1), + .ce1(acc_42_V_ce1), + .we1(acc_42_V_we1), + .d1(acc_42_V_d1), + .q1(acc_42_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_43_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_43_V_address0), + .ce0(acc_43_V_ce0), + .we0(acc_43_V_we0), + .d0(acc_43_V_d0), + .q0(acc_43_V_q0), + .address1(acc_43_V_address1), + .ce1(acc_43_V_ce1), + .we1(acc_43_V_we1), + .d1(acc_43_V_d1), + .q1(acc_43_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_44_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_44_V_address0), + .ce0(acc_44_V_ce0), + .we0(acc_44_V_we0), + .d0(acc_44_V_d0), + .q0(acc_44_V_q0), + .address1(acc_44_V_address1), + .ce1(acc_44_V_ce1), + .we1(acc_44_V_we1), + .d1(acc_44_V_d1), + .q1(acc_44_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_45_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_45_V_address0), + .ce0(acc_45_V_ce0), + .we0(acc_45_V_we0), + .d0(acc_45_V_d0), + .q0(acc_45_V_q0), + .address1(acc_45_V_address1), + .ce1(acc_45_V_ce1), + .we1(acc_45_V_we1), + .d1(acc_45_V_d1), + .q1(acc_45_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_46_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_46_V_address0), + .ce0(acc_46_V_ce0), + .we0(acc_46_V_we0), + .d0(acc_46_V_d0), + .q0(acc_46_V_q0), + .address1(acc_46_V_address1), + .ce1(acc_46_V_ce1), + .we1(acc_46_V_we1), + .d1(acc_46_V_d1), + .q1(acc_46_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_47_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_47_V_address0), + .ce0(acc_47_V_ce0), + .we0(acc_47_V_we0), + .d0(acc_47_V_d0), + .q0(acc_47_V_q0), + .address1(acc_47_V_address1), + .ce1(acc_47_V_ce1), + .we1(acc_47_V_we1), + .d1(acc_47_V_d1), + .q1(acc_47_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_48_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_48_V_address0), + .ce0(acc_48_V_ce0), + .we0(acc_48_V_we0), + .d0(acc_48_V_d0), + .q0(acc_48_V_q0), + .address1(acc_48_V_address1), + .ce1(acc_48_V_ce1), + .we1(acc_48_V_we1), + .d1(acc_48_V_d1), + .q1(acc_48_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_49_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_49_V_address0), + .ce0(acc_49_V_ce0), + .we0(acc_49_V_we0), + .d0(acc_49_V_d0), + .q0(acc_49_V_q0), + .address1(acc_49_V_address1), + .ce1(acc_49_V_ce1), + .we1(acc_49_V_we1), + .d1(acc_49_V_d1), + .q1(acc_49_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_50_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_50_V_address0), + .ce0(acc_50_V_ce0), + .we0(acc_50_V_we0), + .d0(acc_50_V_d0), + .q0(acc_50_V_q0), + .address1(acc_50_V_address1), + .ce1(acc_50_V_ce1), + .we1(acc_50_V_we1), + .d1(acc_50_V_d1), + .q1(acc_50_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_51_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_51_V_address0), + .ce0(acc_51_V_ce0), + .we0(acc_51_V_we0), + .d0(acc_51_V_d0), + .q0(acc_51_V_q0), + .address1(acc_51_V_address1), + .ce1(acc_51_V_ce1), + .we1(acc_51_V_we1), + .d1(acc_51_V_d1), + .q1(acc_51_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_52_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_52_V_address0), + .ce0(acc_52_V_ce0), + .we0(acc_52_V_we0), + .d0(acc_52_V_d0), + .q0(acc_52_V_q0), + .address1(acc_52_V_address1), + .ce1(acc_52_V_ce1), + .we1(acc_52_V_we1), + .d1(acc_52_V_d1), + .q1(acc_52_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_53_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_53_V_address0), + .ce0(acc_53_V_ce0), + .we0(acc_53_V_we0), + .d0(acc_53_V_d0), + .q0(acc_53_V_q0), + .address1(acc_53_V_address1), + .ce1(acc_53_V_ce1), + .we1(acc_53_V_we1), + .d1(acc_53_V_d1), + .q1(acc_53_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_54_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_54_V_address0), + .ce0(acc_54_V_ce0), + .we0(acc_54_V_we0), + .d0(acc_54_V_d0), + .q0(acc_54_V_q0), + .address1(acc_54_V_address1), + .ce1(acc_54_V_ce1), + .we1(acc_54_V_we1), + .d1(acc_54_V_d1), + .q1(acc_54_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_55_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_55_V_address0), + .ce0(acc_55_V_ce0), + .we0(acc_55_V_we0), + .d0(acc_55_V_d0), + .q0(acc_55_V_q0), + .address1(acc_55_V_address1), + .ce1(acc_55_V_ce1), + .we1(acc_55_V_we1), + .d1(acc_55_V_d1), + .q1(acc_55_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_56_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_56_V_address0), + .ce0(acc_56_V_ce0), + .we0(acc_56_V_we0), + .d0(acc_56_V_d0), + .q0(acc_56_V_q0), + .address1(acc_56_V_address1), + .ce1(acc_56_V_ce1), + .we1(acc_56_V_we1), + .d1(acc_56_V_d1), + .q1(acc_56_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_57_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_57_V_address0), + .ce0(acc_57_V_ce0), + .we0(acc_57_V_we0), + .d0(acc_57_V_d0), + .q0(acc_57_V_q0), + .address1(acc_57_V_address1), + .ce1(acc_57_V_ce1), + .we1(acc_57_V_we1), + .d1(acc_57_V_d1), + .q1(acc_57_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_58_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_58_V_address0), + .ce0(acc_58_V_ce0), + .we0(acc_58_V_we0), + .d0(acc_58_V_d0), + .q0(acc_58_V_q0), + .address1(acc_58_V_address1), + .ce1(acc_58_V_ce1), + .we1(acc_58_V_we1), + .d1(acc_58_V_d1), + .q1(acc_58_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_59_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_59_V_address0), + .ce0(acc_59_V_ce0), + .we0(acc_59_V_we0), + .d0(acc_59_V_d0), + .q0(acc_59_V_q0), + .address1(acc_59_V_address1), + .ce1(acc_59_V_ce1), + .we1(acc_59_V_we1), + .d1(acc_59_V_d1), + .q1(acc_59_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_60_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_60_V_address0), + .ce0(acc_60_V_ce0), + .we0(acc_60_V_we0), + .d0(acc_60_V_d0), + .q0(acc_60_V_q0), + .address1(acc_60_V_address1), + .ce1(acc_60_V_ce1), + .we1(acc_60_V_we1), + .d1(acc_60_V_d1), + .q1(acc_60_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_61_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_61_V_address0), + .ce0(acc_61_V_ce0), + .we0(acc_61_V_we0), + .d0(acc_61_V_d0), + .q0(acc_61_V_q0), + .address1(acc_61_V_address1), + .ce1(acc_61_V_ce1), + .we1(acc_61_V_we1), + .d1(acc_61_V_d1), + .q1(acc_61_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_62_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_62_V_address0), + .ce0(acc_62_V_ce0), + .we0(acc_62_V_we0), + .d0(acc_62_V_d0), + .q0(acc_62_V_q0), + .address1(acc_62_V_address1), + .ce1(acc_62_V_ce1), + .we1(acc_62_V_we1), + .d1(acc_62_V_d1), + .q1(acc_62_V_q1) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_acDeQ #( + .DataWidth( 8 ), + .AddressRange( 49 ), + .AddressWidth( 6 )) +acc_63_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(acc_63_V_address0), + .ce0(acc_63_V_ce0), + .we0(acc_63_V_we0), + .d0(acc_63_V_d0), + .q0(acc_63_V_q0), + .address1(acc_63_V_address1), + .ce1(acc_63_V_ce1), + .we1(acc_63_V_we1), + .d1(acc_63_V_d1), + .q1(acc_63_V_q1) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U1( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73372_ap_start), + .done(grp_fu_73372_ap_done), + .din0(grp_fu_73372_p0), + .din1(grp_fu_73372_p1), + .ce(1'b1), + .dout(grp_fu_73372_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U2( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73378_ap_start), + .done(grp_fu_73378_ap_done), + .din0(grp_fu_73378_p0), + .din1(grp_fu_73378_p1), + .ce(1'b1), + .dout(grp_fu_73378_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U3( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73388_ap_start), + .done(grp_fu_73388_ap_done), + .din0(grp_fu_73388_p0), + .din1(grp_fu_73388_p1), + .ce(1'b1), + .dout(grp_fu_73388_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U4( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73394_ap_start), + .done(grp_fu_73394_ap_done), + .din0(grp_fu_73394_p0), + .din1(grp_fu_73394_p1), + .ce(1'b1), + .dout(grp_fu_73394_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U5( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73404_ap_start), + .done(grp_fu_73404_ap_done), + .din0(grp_fu_73404_p0), + .din1(grp_fu_73404_p1), + .ce(1'b1), + .dout(grp_fu_73404_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U6( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73410_ap_start), + .done(grp_fu_73410_ap_done), + .din0(grp_fu_73410_p0), + .din1(grp_fu_73410_p1), + .ce(1'b1), + .dout(grp_fu_73410_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U7( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73420_ap_start), + .done(grp_fu_73420_ap_done), + .din0(grp_fu_73420_p0), + .din1(grp_fu_73420_p1), + .ce(1'b1), + .dout(grp_fu_73420_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U8( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73426_ap_start), + .done(grp_fu_73426_ap_done), + .din0(grp_fu_73426_p0), + .din1(grp_fu_73426_p1), + .ce(1'b1), + .dout(grp_fu_73426_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U9( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73436_ap_start), + .done(grp_fu_73436_ap_done), + .din0(grp_fu_73436_p0), + .din1(grp_fu_73436_p1), + .ce(1'b1), + .dout(grp_fu_73436_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U10( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73442_ap_start), + .done(grp_fu_73442_ap_done), + .din0(grp_fu_73442_p0), + .din1(grp_fu_73442_p1), + .ce(1'b1), + .dout(grp_fu_73442_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U11( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73452_ap_start), + .done(grp_fu_73452_ap_done), + .din0(grp_fu_73452_p0), + .din1(grp_fu_73452_p1), + .ce(1'b1), + .dout(grp_fu_73452_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U12( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73458_ap_start), + .done(grp_fu_73458_ap_done), + .din0(grp_fu_73458_p0), + .din1(grp_fu_73458_p1), + .ce(1'b1), + .dout(grp_fu_73458_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U13( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73468_ap_start), + .done(grp_fu_73468_ap_done), + .din0(grp_fu_73468_p0), + .din1(grp_fu_73468_p1), + .ce(1'b1), + .dout(grp_fu_73468_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U14( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73474_ap_start), + .done(grp_fu_73474_ap_done), + .din0(grp_fu_73474_p0), + .din1(grp_fu_73474_p1), + .ce(1'b1), + .dout(grp_fu_73474_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U15( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73484_ap_start), + .done(grp_fu_73484_ap_done), + .din0(grp_fu_73484_p0), + .din1(grp_fu_73484_p1), + .ce(1'b1), + .dout(grp_fu_73484_p2) +); + +myproject_urem_32ns_6ns_6_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 6 )) +myproject_urem_32ns_6ns_6_36_seq_1_U16( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_73490_ap_start), + .done(grp_fu_73490_ap_done), + .din0(grp_fu_73490_p0), + .din1(grp_fu_73490_p1), + .ce(1'b1), + .dout(grp_fu_73490_p2) +); + +myproject_mux_6432_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 8 ), + .din29_WIDTH( 8 ), + .din30_WIDTH( 8 ), + .din31_WIDTH( 8 ), + .din32_WIDTH( 8 ), + .din33_WIDTH( 8 ), + .din34_WIDTH( 8 ), + .din35_WIDTH( 8 ), + .din36_WIDTH( 8 ), + .din37_WIDTH( 8 ), + .din38_WIDTH( 8 ), + .din39_WIDTH( 8 ), + .din40_WIDTH( 8 ), + .din41_WIDTH( 8 ), + .din42_WIDTH( 8 ), + .din43_WIDTH( 8 ), + .din44_WIDTH( 8 ), + .din45_WIDTH( 8 ), + .din46_WIDTH( 8 ), + .din47_WIDTH( 8 ), + .din48_WIDTH( 8 ), + .din49_WIDTH( 8 ), + .din50_WIDTH( 8 ), + .din51_WIDTH( 8 ), + .din52_WIDTH( 8 ), + .din53_WIDTH( 8 ), + .din54_WIDTH( 8 ), + .din55_WIDTH( 8 ), + .din56_WIDTH( 8 ), + .din57_WIDTH( 8 ), + .din58_WIDTH( 8 ), + .din59_WIDTH( 8 ), + .din60_WIDTH( 8 ), + .din61_WIDTH( 8 ), + .din62_WIDTH( 8 ), + .din63_WIDTH( 8 ), + .din64_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_6432_8_1_1_U17( + .din0(acc_0_V_q1), + .din1(acc_1_V_q1), + .din2(acc_2_V_q1), + .din3(acc_3_V_q1), + .din4(acc_4_V_q1), + .din5(acc_5_V_q1), + .din6(acc_6_V_q1), + .din7(acc_7_V_q1), + .din8(acc_8_V_q1), + .din9(acc_9_V_q1), + .din10(acc_10_V_q1), + .din11(acc_11_V_q1), + .din12(acc_12_V_q1), + .din13(acc_13_V_q1), + .din14(acc_14_V_q1), + .din15(acc_15_V_q1), + .din16(acc_16_V_q1), + .din17(acc_17_V_q1), + .din18(acc_18_V_q1), + .din19(acc_19_V_q1), + .din20(acc_20_V_q1), + .din21(acc_21_V_q1), + .din22(acc_22_V_q1), + .din23(acc_23_V_q1), + .din24(acc_24_V_q1), + .din25(acc_25_V_q1), + .din26(acc_26_V_q1), + .din27(acc_27_V_q1), + .din28(acc_28_V_q1), + .din29(acc_29_V_q1), + .din30(acc_30_V_q1), + .din31(acc_31_V_q1), + .din32(acc_32_V_q1), + .din33(acc_33_V_q1), + .din34(acc_34_V_q1), + .din35(acc_35_V_q1), + .din36(acc_36_V_q1), + .din37(acc_37_V_q1), + .din38(acc_38_V_q1), + .din39(acc_39_V_q1), + .din40(acc_40_V_q1), + .din41(acc_41_V_q1), + .din42(acc_42_V_q1), + .din43(acc_43_V_q1), + .din44(acc_44_V_q1), + .din45(acc_45_V_q1), + .din46(acc_46_V_q1), + .din47(acc_47_V_q1), + .din48(acc_48_V_q1), + .din49(acc_49_V_q1), + .din50(acc_50_V_q1), + .din51(acc_51_V_q1), + .din52(acc_52_V_q1), + .din53(acc_53_V_q1), + .din54(acc_54_V_q1), + .din55(acc_55_V_q1), + .din56(acc_56_V_q1), + .din57(acc_57_V_q1), + .din58(acc_58_V_q1), + .din59(acc_59_V_q1), + .din60(acc_60_V_q1), + .din61(acc_61_V_q1), + .din62(acc_62_V_q1), + .din63(acc_63_V_q1), + .din64(zext_ln1265_reg_94272), + .dout(grp_fu_73495_p66) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U18( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_73985_p0), + .din1(grp_fu_73985_p1), + .ce(1'b1), + .dout(grp_fu_73985_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U19( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_74429_p0), + .din1(grp_fu_74429_p1), + .ce(1'b1), + .dout(grp_fu_74429_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U20( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_74642_p0), + .din1(grp_fu_74642_p1), + .ce(1'b1), + .dout(grp_fu_74642_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U21( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_74702_p0), + .din1(grp_fu_74702_p1), + .ce(1'b1), + .dout(grp_fu_74702_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U22( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_74810_p0), + .din1(grp_fu_74810_p1), + .ce(1'b1), + .dout(grp_fu_74810_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U23( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_75174_p0), + .din1(grp_fu_75174_p1), + .ce(1'b1), + .dout(grp_fu_75174_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U24( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_75365_p0), + .din1(grp_fu_75365_p1), + .ce(1'b1), + .dout(grp_fu_75365_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U25( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_75425_p0), + .din1(grp_fu_75425_p1), + .ce(1'b1), + .dout(grp_fu_75425_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U26( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_75685_p0), + .din1(grp_fu_75685_p1), + .ce(1'b1), + .dout(grp_fu_75685_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U27( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_76119_p0), + .din1(grp_fu_76119_p1), + .ce(1'b1), + .dout(grp_fu_76119_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U28( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_76332_p0), + .din1(grp_fu_76332_p1), + .ce(1'b1), + .dout(grp_fu_76332_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U29( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_76392_p0), + .din1(grp_fu_76392_p1), + .ce(1'b1), + .dout(grp_fu_76392_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U30( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_76500_p0), + .din1(grp_fu_76500_p1), + .ce(1'b1), + .dout(grp_fu_76500_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U31( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_76854_p0), + .din1(grp_fu_76854_p1), + .ce(1'b1), + .dout(grp_fu_76854_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U32( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_77045_p0), + .din1(grp_fu_77045_p1), + .ce(1'b1), + .dout(grp_fu_77045_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U33( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_77105_p0), + .din1(grp_fu_77105_p1), + .ce(1'b1), + .dout(grp_fu_77105_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U34( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_77447_p0), + .din1(grp_fu_77447_p1), + .ce(1'b1), + .dout(grp_fu_77447_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U35( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_77890_p0), + .din1(grp_fu_77890_p1), + .ce(1'b1), + .dout(grp_fu_77890_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U36( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_78102_p0), + .din1(grp_fu_78102_p1), + .ce(1'b1), + .dout(grp_fu_78102_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U37( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_78162_p0), + .din1(grp_fu_78162_p1), + .ce(1'b1), + .dout(grp_fu_78162_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U38( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_78270_p0), + .din1(grp_fu_78270_p1), + .ce(1'b1), + .dout(grp_fu_78270_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U39( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_78634_p0), + .din1(grp_fu_78634_p1), + .ce(1'b1), + .dout(grp_fu_78634_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U40( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_78825_p0), + .din1(grp_fu_78825_p1), + .ce(1'b1), + .dout(grp_fu_78825_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U41( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_78885_p0), + .din1(grp_fu_78885_p1), + .ce(1'b1), + .dout(grp_fu_78885_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U42( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_79149_p0), + .din1(grp_fu_79149_p1), + .ce(1'b1), + .dout(grp_fu_79149_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U43( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_79602_p0), + .din1(grp_fu_79602_p1), + .ce(1'b1), + .dout(grp_fu_79602_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U44( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_79793_p0), + .din1(grp_fu_79793_p1), + .ce(1'b1), + .dout(grp_fu_79793_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U45( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_79853_p0), + .din1(grp_fu_79853_p1), + .ce(1'b1), + .dout(grp_fu_79853_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U46( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_79961_p0), + .din1(grp_fu_79961_p1), + .ce(1'b1), + .dout(grp_fu_79961_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U47( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_80315_p0), + .din1(grp_fu_80315_p1), + .ce(1'b1), + .dout(grp_fu_80315_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U48( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_80506_p0), + .din1(grp_fu_80506_p1), + .ce(1'b1), + .dout(grp_fu_80506_p2) +); + +myproject_mul_34ns_32ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 34 ), + .din1_WIDTH( 32 ), + .dout_WIDTH( 65 )) +myproject_mul_34ns_32ns_65_2_1_U49( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_80566_p0), + .din1(grp_fu_80566_p1), + .ce(1'b1), + .dout(grp_fu_80566_p2) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U50( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_81835_ap_start), + .done(grp_fu_81835_ap_done), + .din0(grp_fu_81835_p0), + .din1(grp_fu_81835_p1), + .ce(1'b1), + .dout(grp_fu_81835_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U51( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_81844_p0), + .din1(grp_fu_81844_p1), + .ce(1'b1), + .dout(grp_fu_81844_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U52( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_81835_p2), + .dout(tmp_52_fu_81891_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U53( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_82008_ap_start), + .done(grp_fu_82008_ap_done), + .din0(grp_fu_82008_p0), + .din1(grp_fu_82008_p1), + .ce(1'b1), + .dout(grp_fu_82008_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U54( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_82084_p0), + .din1(grp_fu_82084_p1), + .ce(1'b1), + .dout(grp_fu_82084_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U55( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_82008_p2), + .dout(tmp_81_fu_82131_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U56( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_82241_ap_start), + .done(grp_fu_82241_ap_done), + .din0(grp_fu_82241_p0), + .din1(grp_fu_82241_p1), + .ce(1'b1), + .dout(grp_fu_82241_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U57( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_82250_p0), + .din1(grp_fu_82250_p1), + .ce(1'b1), + .dout(grp_fu_82250_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U58( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_82241_p2), + .dout(tmp_102_fu_82297_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U59( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_82414_ap_start), + .done(grp_fu_82414_ap_done), + .din0(grp_fu_82414_p0), + .din1(grp_fu_82414_p1), + .ce(1'b1), + .dout(grp_fu_82414_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U60( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_82429_p0), + .din1(grp_fu_82429_p1), + .ce(1'b1), + .dout(grp_fu_82429_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U61( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_82414_p2), + .dout(tmp_157_fu_82476_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U62( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_82603_ap_start), + .done(grp_fu_82603_ap_done), + .din0(grp_fu_82603_p0), + .din1(grp_fu_82603_p1), + .ce(1'b1), + .dout(grp_fu_82603_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U63( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_82612_p0), + .din1(grp_fu_82612_p1), + .ce(1'b1), + .dout(grp_fu_82612_p2) +); + +myproject_mux_6432_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 8 ), + .din29_WIDTH( 8 ), + .din30_WIDTH( 8 ), + .din31_WIDTH( 8 ), + .din32_WIDTH( 8 ), + .din33_WIDTH( 8 ), + .din34_WIDTH( 8 ), + .din35_WIDTH( 8 ), + .din36_WIDTH( 8 ), + .din37_WIDTH( 8 ), + .din38_WIDTH( 8 ), + .din39_WIDTH( 8 ), + .din40_WIDTH( 8 ), + .din41_WIDTH( 8 ), + .din42_WIDTH( 8 ), + .din43_WIDTH( 8 ), + .din44_WIDTH( 8 ), + .din45_WIDTH( 8 ), + .din46_WIDTH( 8 ), + .din47_WIDTH( 8 ), + .din48_WIDTH( 8 ), + .din49_WIDTH( 8 ), + .din50_WIDTH( 8 ), + .din51_WIDTH( 8 ), + .din52_WIDTH( 8 ), + .din53_WIDTH( 8 ), + .din54_WIDTH( 8 ), + .din55_WIDTH( 8 ), + .din56_WIDTH( 8 ), + .din57_WIDTH( 8 ), + .din58_WIDTH( 8 ), + .din59_WIDTH( 8 ), + .din60_WIDTH( 8 ), + .din61_WIDTH( 8 ), + .din62_WIDTH( 8 ), + .din63_WIDTH( 8 ), + .din64_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_6432_8_1_1_U64( + .din0(acc_0_V_q0), + .din1(acc_1_V_q1), + .din2(acc_2_V_q0), + .din3(acc_3_V_q1), + .din4(acc_4_V_q0), + .din5(acc_5_V_q1), + .din6(acc_6_V_q0), + .din7(acc_7_V_q1), + .din8(acc_8_V_q0), + .din9(acc_9_V_q1), + .din10(acc_10_V_q0), + .din11(acc_11_V_q1), + .din12(acc_12_V_q0), + .din13(acc_13_V_q1), + .din14(acc_14_V_q0), + .din15(acc_15_V_q1), + .din16(acc_16_V_q0), + .din17(acc_17_V_q1), + .din18(acc_18_V_q0), + .din19(acc_19_V_q1), + .din20(acc_20_V_q0), + .din21(acc_21_V_q1), + .din22(acc_22_V_q0), + .din23(acc_23_V_q1), + .din24(acc_24_V_q0), + .din25(acc_25_V_q1), + .din26(acc_26_V_q0), + .din27(acc_27_V_q1), + .din28(acc_28_V_q0), + .din29(acc_29_V_q1), + .din30(acc_30_V_q0), + .din31(acc_31_V_q1), + .din32(acc_32_V_q0), + .din33(acc_33_V_q1), + .din34(acc_34_V_q0), + .din35(acc_35_V_q1), + .din36(acc_36_V_q0), + .din37(acc_37_V_q1), + .din38(acc_38_V_q0), + .din39(acc_39_V_q1), + .din40(acc_40_V_q0), + .din41(acc_41_V_q1), + .din42(acc_42_V_q0), + .din43(acc_43_V_q1), + .din44(acc_44_V_q0), + .din45(acc_45_V_q1), + .din46(acc_46_V_q0), + .din47(acc_47_V_q1), + .din48(acc_48_V_q0), + .din49(acc_49_V_q1), + .din50(acc_50_V_q0), + .din51(acc_51_V_q1), + .din52(acc_52_V_q0), + .din53(acc_53_V_q1), + .din54(acc_54_V_q0), + .din55(acc_55_V_q1), + .din56(acc_56_V_q0), + .din57(acc_57_V_q1), + .din58(acc_58_V_q0), + .din59(acc_59_V_q1), + .din60(acc_60_V_q0), + .din61(acc_61_V_q1), + .din62(acc_62_V_q0), + .din63(acc_63_V_q1), + .din64(zext_ln1265_20_reg_94878), + .dout(tmp_116_fu_82659_p66) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U65( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_82603_p2), + .dout(tmp_118_fu_82792_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U66( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_82892_ap_start), + .done(grp_fu_82892_ap_done), + .din0(grp_fu_82892_p0), + .din1(grp_fu_82892_p1), + .ce(1'b1), + .dout(grp_fu_82892_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U67( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_82936_p0), + .din1(grp_fu_82936_p1), + .ce(1'b1), + .dout(grp_fu_82936_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U68( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_82892_p2), + .dout(tmp_176_fu_82983_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U69( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_83077_ap_start), + .done(grp_fu_83077_ap_done), + .din0(grp_fu_83077_p0), + .din1(grp_fu_83077_p1), + .ce(1'b1), + .dout(grp_fu_83077_p2) +); + +myproject_mux_6432_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 8 ), + .din29_WIDTH( 8 ), + .din30_WIDTH( 8 ), + .din31_WIDTH( 8 ), + .din32_WIDTH( 8 ), + .din33_WIDTH( 8 ), + .din34_WIDTH( 8 ), + .din35_WIDTH( 8 ), + .din36_WIDTH( 8 ), + .din37_WIDTH( 8 ), + .din38_WIDTH( 8 ), + .din39_WIDTH( 8 ), + .din40_WIDTH( 8 ), + .din41_WIDTH( 8 ), + .din42_WIDTH( 8 ), + .din43_WIDTH( 8 ), + .din44_WIDTH( 8 ), + .din45_WIDTH( 8 ), + .din46_WIDTH( 8 ), + .din47_WIDTH( 8 ), + .din48_WIDTH( 8 ), + .din49_WIDTH( 8 ), + .din50_WIDTH( 8 ), + .din51_WIDTH( 8 ), + .din52_WIDTH( 8 ), + .din53_WIDTH( 8 ), + .din54_WIDTH( 8 ), + .din55_WIDTH( 8 ), + .din56_WIDTH( 8 ), + .din57_WIDTH( 8 ), + .din58_WIDTH( 8 ), + .din59_WIDTH( 8 ), + .din60_WIDTH( 8 ), + .din61_WIDTH( 8 ), + .din62_WIDTH( 8 ), + .din63_WIDTH( 8 ), + .din64_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_6432_8_1_1_U70( + .din0(acc_0_V_q1), + .din1(acc_1_V_q1), + .din2(acc_2_V_q1), + .din3(acc_3_V_q1), + .din4(acc_4_V_q1), + .din5(acc_5_V_q1), + .din6(acc_6_V_q1), + .din7(acc_7_V_q1), + .din8(acc_8_V_q1), + .din9(acc_9_V_q1), + .din10(acc_10_V_q1), + .din11(acc_11_V_q1), + .din12(acc_12_V_q1), + .din13(acc_13_V_q1), + .din14(acc_14_V_q1), + .din15(acc_15_V_q1), + .din16(acc_16_V_q1), + .din17(acc_17_V_q1), + .din18(acc_18_V_q1), + .din19(acc_19_V_q1), + .din20(acc_20_V_q1), + .din21(acc_21_V_q1), + .din22(acc_22_V_q1), + .din23(acc_23_V_q1), + .din24(acc_24_V_q1), + .din25(acc_25_V_q1), + .din26(acc_26_V_q1), + .din27(acc_27_V_q1), + .din28(acc_28_V_q1), + .din29(acc_29_V_q1), + .din30(acc_30_V_q1), + .din31(acc_31_V_q1), + .din32(acc_32_V_q1), + .din33(acc_33_V_q1), + .din34(acc_34_V_q1), + .din35(acc_35_V_q1), + .din36(acc_36_V_q1), + .din37(acc_37_V_q1), + .din38(acc_38_V_q1), + .din39(acc_39_V_q1), + .din40(acc_40_V_q1), + .din41(acc_41_V_q1), + .din42(acc_42_V_q1), + .din43(acc_43_V_q1), + .din44(acc_44_V_q1), + .din45(acc_45_V_q1), + .din46(acc_46_V_q1), + .din47(acc_47_V_q1), + .din48(acc_48_V_q1), + .din49(acc_49_V_q1), + .din50(acc_50_V_q1), + .din51(acc_51_V_q1), + .din52(acc_52_V_q1), + .din53(acc_53_V_q1), + .din54(acc_54_V_q1), + .din55(acc_55_V_q1), + .din56(acc_56_V_q1), + .din57(acc_57_V_q1), + .din58(acc_58_V_q1), + .din59(acc_59_V_q1), + .din60(acc_60_V_q1), + .din61(acc_61_V_q1), + .din62(acc_62_V_q1), + .din63(acc_63_V_q1), + .din64(zext_ln1265_20_reg_94878), + .dout(tmp_194_fu_83083_p66) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U71( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_83219_p0), + .din1(grp_fu_83219_p1), + .ce(1'b1), + .dout(grp_fu_83219_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U72( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_83077_p2), + .dout(tmp_196_fu_83266_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U73( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_83366_ap_start), + .done(grp_fu_83366_ap_done), + .din0(grp_fu_83366_p0), + .din1(grp_fu_83366_p1), + .ce(1'b1), + .dout(grp_fu_83366_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U74( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_83381_p0), + .din1(grp_fu_83381_p1), + .ce(1'b1), + .dout(grp_fu_83381_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U75( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_83366_p2), + .dout(tmp_218_fu_83428_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U76( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_83662_ap_start), + .done(grp_fu_83662_ap_done), + .din0(grp_fu_83662_p0), + .din1(grp_fu_83662_p1), + .ce(1'b1), + .dout(grp_fu_83662_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U77( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_83671_p0), + .din1(grp_fu_83671_p1), + .ce(1'b1), + .dout(grp_fu_83671_p2) +); + +myproject_mux_6432_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 8 ), + .din29_WIDTH( 8 ), + .din30_WIDTH( 8 ), + .din31_WIDTH( 8 ), + .din32_WIDTH( 8 ), + .din33_WIDTH( 8 ), + .din34_WIDTH( 8 ), + .din35_WIDTH( 8 ), + .din36_WIDTH( 8 ), + .din37_WIDTH( 8 ), + .din38_WIDTH( 8 ), + .din39_WIDTH( 8 ), + .din40_WIDTH( 8 ), + .din41_WIDTH( 8 ), + .din42_WIDTH( 8 ), + .din43_WIDTH( 8 ), + .din44_WIDTH( 8 ), + .din45_WIDTH( 8 ), + .din46_WIDTH( 8 ), + .din47_WIDTH( 8 ), + .din48_WIDTH( 8 ), + .din49_WIDTH( 8 ), + .din50_WIDTH( 8 ), + .din51_WIDTH( 8 ), + .din52_WIDTH( 8 ), + .din53_WIDTH( 8 ), + .din54_WIDTH( 8 ), + .din55_WIDTH( 8 ), + .din56_WIDTH( 8 ), + .din57_WIDTH( 8 ), + .din58_WIDTH( 8 ), + .din59_WIDTH( 8 ), + .din60_WIDTH( 8 ), + .din61_WIDTH( 8 ), + .din62_WIDTH( 8 ), + .din63_WIDTH( 8 ), + .din64_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_6432_8_1_1_U78( + .din0(acc_0_V_q0), + .din1(acc_1_V_q0), + .din2(acc_2_V_q0), + .din3(acc_3_V_q0), + .din4(acc_4_V_q0), + .din5(acc_5_V_q0), + .din6(acc_6_V_q0), + .din7(acc_7_V_q0), + .din8(acc_8_V_q0), + .din9(acc_9_V_q0), + .din10(acc_10_V_q0), + .din11(acc_11_V_q0), + .din12(acc_12_V_q0), + .din13(acc_13_V_q0), + .din14(acc_14_V_q0), + .din15(acc_15_V_q0), + .din16(acc_16_V_q0), + .din17(acc_17_V_q0), + .din18(acc_18_V_q0), + .din19(acc_19_V_q0), + .din20(acc_20_V_q0), + .din21(acc_21_V_q0), + .din22(acc_22_V_q0), + .din23(acc_23_V_q0), + .din24(acc_24_V_q0), + .din25(acc_25_V_q0), + .din26(acc_26_V_q0), + .din27(acc_27_V_q0), + .din28(acc_28_V_q0), + .din29(acc_29_V_q0), + .din30(acc_30_V_q0), + .din31(acc_31_V_q0), + .din32(acc_32_V_q0), + .din33(acc_33_V_q0), + .din34(acc_34_V_q0), + .din35(acc_35_V_q0), + .din36(acc_36_V_q0), + .din37(acc_37_V_q0), + .din38(acc_38_V_q0), + .din39(acc_39_V_q0), + .din40(acc_40_V_q0), + .din41(acc_41_V_q0), + .din42(acc_42_V_q0), + .din43(acc_43_V_q0), + .din44(acc_44_V_q0), + .din45(acc_45_V_q0), + .din46(acc_46_V_q0), + .din47(acc_47_V_q0), + .din48(acc_48_V_q0), + .din49(acc_49_V_q0), + .din50(acc_50_V_q0), + .din51(acc_51_V_q0), + .din52(acc_52_V_q0), + .din53(acc_53_V_q0), + .din54(acc_54_V_q0), + .din55(acc_55_V_q0), + .din56(acc_56_V_q0), + .din57(acc_57_V_q0), + .din58(acc_58_V_q0), + .din59(acc_59_V_q0), + .din60(acc_60_V_q0), + .din61(acc_61_V_q0), + .din62(acc_62_V_q0), + .din63(acc_63_V_q0), + .din64(zext_ln1265_6_reg_96102), + .dout(tmp_71_fu_83718_p66) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U79( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_83662_p2), + .dout(tmp_73_fu_83851_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U80( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_83967_ap_start), + .done(grp_fu_83967_ap_done), + .din0(grp_fu_83967_p0), + .din1(grp_fu_83967_p1), + .ce(1'b1), + .dout(grp_fu_83967_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U81( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_84043_p0), + .din1(grp_fu_84043_p1), + .ce(1'b1), + .dout(grp_fu_84043_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U82( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_83967_p2), + .dout(tmp_98_fu_84090_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U83( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_84200_ap_start), + .done(grp_fu_84200_ap_done), + .din0(grp_fu_84200_p0), + .din1(grp_fu_84200_p1), + .ce(1'b1), + .dout(grp_fu_84200_p2) +); + +myproject_mux_6432_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 8 ), + .din29_WIDTH( 8 ), + .din30_WIDTH( 8 ), + .din31_WIDTH( 8 ), + .din32_WIDTH( 8 ), + .din33_WIDTH( 8 ), + .din34_WIDTH( 8 ), + .din35_WIDTH( 8 ), + .din36_WIDTH( 8 ), + .din37_WIDTH( 8 ), + .din38_WIDTH( 8 ), + .din39_WIDTH( 8 ), + .din40_WIDTH( 8 ), + .din41_WIDTH( 8 ), + .din42_WIDTH( 8 ), + .din43_WIDTH( 8 ), + .din44_WIDTH( 8 ), + .din45_WIDTH( 8 ), + .din46_WIDTH( 8 ), + .din47_WIDTH( 8 ), + .din48_WIDTH( 8 ), + .din49_WIDTH( 8 ), + .din50_WIDTH( 8 ), + .din51_WIDTH( 8 ), + .din52_WIDTH( 8 ), + .din53_WIDTH( 8 ), + .din54_WIDTH( 8 ), + .din55_WIDTH( 8 ), + .din56_WIDTH( 8 ), + .din57_WIDTH( 8 ), + .din58_WIDTH( 8 ), + .din59_WIDTH( 8 ), + .din60_WIDTH( 8 ), + .din61_WIDTH( 8 ), + .din62_WIDTH( 8 ), + .din63_WIDTH( 8 ), + .din64_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_6432_8_1_1_U84( + .din0(acc_0_V_q1), + .din1(acc_1_V_q1), + .din2(acc_2_V_q1), + .din3(acc_3_V_q1), + .din4(acc_4_V_q1), + .din5(acc_5_V_q1), + .din6(acc_6_V_q1), + .din7(acc_7_V_q1), + .din8(acc_8_V_q1), + .din9(acc_9_V_q1), + .din10(acc_10_V_q1), + .din11(acc_11_V_q1), + .din12(acc_12_V_q1), + .din13(acc_13_V_q1), + .din14(acc_14_V_q1), + .din15(acc_15_V_q1), + .din16(acc_16_V_q1), + .din17(acc_17_V_q1), + .din18(acc_18_V_q1), + .din19(acc_19_V_q1), + .din20(acc_20_V_q1), + .din21(acc_21_V_q1), + .din22(acc_22_V_q1), + .din23(acc_23_V_q1), + .din24(acc_24_V_q1), + .din25(acc_25_V_q1), + .din26(acc_26_V_q1), + .din27(acc_27_V_q1), + .din28(acc_28_V_q1), + .din29(acc_29_V_q1), + .din30(acc_30_V_q1), + .din31(acc_31_V_q1), + .din32(acc_32_V_q1), + .din33(acc_33_V_q1), + .din34(acc_34_V_q1), + .din35(acc_35_V_q1), + .din36(acc_36_V_q1), + .din37(acc_37_V_q1), + .din38(acc_38_V_q1), + .din39(acc_39_V_q1), + .din40(acc_40_V_q1), + .din41(acc_41_V_q1), + .din42(acc_42_V_q1), + .din43(acc_43_V_q1), + .din44(acc_44_V_q1), + .din45(acc_45_V_q1), + .din46(acc_46_V_q1), + .din47(acc_47_V_q1), + .din48(acc_48_V_q1), + .din49(acc_49_V_q1), + .din50(acc_50_V_q1), + .din51(acc_51_V_q1), + .din52(acc_52_V_q1), + .din53(acc_53_V_q1), + .din54(acc_54_V_q1), + .din55(acc_55_V_q1), + .din56(acc_56_V_q1), + .din57(acc_57_V_q1), + .din58(acc_58_V_q1), + .din59(acc_59_V_q1), + .din60(acc_60_V_q1), + .din61(acc_61_V_q1), + .din62(acc_62_V_q1), + .din63(acc_63_V_q1), + .din64(zext_ln1265_6_reg_96102), + .dout(tmp_139_fu_84206_p66) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U85( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_84342_p0), + .din1(grp_fu_84342_p1), + .ce(1'b1), + .dout(grp_fu_84342_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U86( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_84200_p2), + .dout(tmp_141_fu_84389_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U87( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_84505_ap_start), + .done(grp_fu_84505_ap_done), + .din0(grp_fu_84505_p0), + .din1(grp_fu_84505_p1), + .ce(1'b1), + .dout(grp_fu_84505_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U88( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_84520_p0), + .din1(grp_fu_84520_p1), + .ce(1'b1), + .dout(grp_fu_84520_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U89( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_84505_p2), + .dout(tmp_184_fu_84567_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U90( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_84694_ap_start), + .done(grp_fu_84694_ap_done), + .din0(grp_fu_84694_p0), + .din1(grp_fu_84694_p1), + .ce(1'b1), + .dout(grp_fu_84694_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U91( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_84703_p0), + .din1(grp_fu_84703_p1), + .ce(1'b1), + .dout(grp_fu_84703_p2) +); + +myproject_mux_6432_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 8 ), + .din29_WIDTH( 8 ), + .din30_WIDTH( 8 ), + .din31_WIDTH( 8 ), + .din32_WIDTH( 8 ), + .din33_WIDTH( 8 ), + .din34_WIDTH( 8 ), + .din35_WIDTH( 8 ), + .din36_WIDTH( 8 ), + .din37_WIDTH( 8 ), + .din38_WIDTH( 8 ), + .din39_WIDTH( 8 ), + .din40_WIDTH( 8 ), + .din41_WIDTH( 8 ), + .din42_WIDTH( 8 ), + .din43_WIDTH( 8 ), + .din44_WIDTH( 8 ), + .din45_WIDTH( 8 ), + .din46_WIDTH( 8 ), + .din47_WIDTH( 8 ), + .din48_WIDTH( 8 ), + .din49_WIDTH( 8 ), + .din50_WIDTH( 8 ), + .din51_WIDTH( 8 ), + .din52_WIDTH( 8 ), + .din53_WIDTH( 8 ), + .din54_WIDTH( 8 ), + .din55_WIDTH( 8 ), + .din56_WIDTH( 8 ), + .din57_WIDTH( 8 ), + .din58_WIDTH( 8 ), + .din59_WIDTH( 8 ), + .din60_WIDTH( 8 ), + .din61_WIDTH( 8 ), + .din62_WIDTH( 8 ), + .din63_WIDTH( 8 ), + .din64_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_6432_8_1_1_U92( + .din0(acc_0_V_q0), + .din1(acc_1_V_q0), + .din2(acc_2_V_q0), + .din3(acc_3_V_q0), + .din4(acc_4_V_q0), + .din5(acc_5_V_q0), + .din6(acc_6_V_q0), + .din7(acc_7_V_q0), + .din8(acc_8_V_q0), + .din9(acc_9_V_q0), + .din10(acc_10_V_q0), + .din11(acc_11_V_q0), + .din12(acc_12_V_q0), + .din13(acc_13_V_q0), + .din14(acc_14_V_q0), + .din15(acc_15_V_q0), + .din16(acc_16_V_q0), + .din17(acc_17_V_q0), + .din18(acc_18_V_q0), + .din19(acc_19_V_q0), + .din20(acc_20_V_q0), + .din21(acc_21_V_q0), + .din22(acc_22_V_q0), + .din23(acc_23_V_q0), + .din24(acc_24_V_q0), + .din25(acc_25_V_q0), + .din26(acc_26_V_q0), + .din27(acc_27_V_q0), + .din28(acc_28_V_q0), + .din29(acc_29_V_q0), + .din30(acc_30_V_q0), + .din31(acc_31_V_q0), + .din32(acc_32_V_q0), + .din33(acc_33_V_q0), + .din34(acc_34_V_q0), + .din35(acc_35_V_q0), + .din36(acc_36_V_q0), + .din37(acc_37_V_q0), + .din38(acc_38_V_q0), + .din39(acc_39_V_q0), + .din40(acc_40_V_q0), + .din41(acc_41_V_q0), + .din42(acc_42_V_q0), + .din43(acc_43_V_q0), + .din44(acc_44_V_q0), + .din45(acc_45_V_q0), + .din46(acc_46_V_q0), + .din47(acc_47_V_q0), + .din48(acc_48_V_q0), + .din49(acc_49_V_q0), + .din50(acc_50_V_q0), + .din51(acc_51_V_q0), + .din52(acc_52_V_q0), + .din53(acc_53_V_q0), + .din54(acc_54_V_q0), + .din55(acc_55_V_q0), + .din56(acc_56_V_q0), + .din57(acc_57_V_q0), + .din58(acc_58_V_q0), + .din59(acc_59_V_q0), + .din60(acc_60_V_q0), + .din61(acc_61_V_q0), + .din62(acc_62_V_q0), + .din63(acc_63_V_q0), + .din64(zext_ln1265_28_reg_96702), + .dout(tmp_153_fu_84750_p66) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U93( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_84694_p2), + .dout(tmp_155_fu_84883_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U94( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_84982_ap_start), + .done(grp_fu_84982_ap_done), + .din0(grp_fu_84982_p0), + .din1(grp_fu_84982_p1), + .ce(1'b1), + .dout(grp_fu_84982_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U95( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_85026_p0), + .din1(grp_fu_85026_p1), + .ce(1'b1), + .dout(grp_fu_85026_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U96( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_84982_p2), + .dout(tmp_193_fu_85073_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U97( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_85166_ap_start), + .done(grp_fu_85166_ap_done), + .din0(grp_fu_85166_p0), + .din1(grp_fu_85166_p1), + .ce(1'b1), + .dout(grp_fu_85166_p2) +); + +myproject_mux_6432_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 8 ), + .din29_WIDTH( 8 ), + .din30_WIDTH( 8 ), + .din31_WIDTH( 8 ), + .din32_WIDTH( 8 ), + .din33_WIDTH( 8 ), + .din34_WIDTH( 8 ), + .din35_WIDTH( 8 ), + .din36_WIDTH( 8 ), + .din37_WIDTH( 8 ), + .din38_WIDTH( 8 ), + .din39_WIDTH( 8 ), + .din40_WIDTH( 8 ), + .din41_WIDTH( 8 ), + .din42_WIDTH( 8 ), + .din43_WIDTH( 8 ), + .din44_WIDTH( 8 ), + .din45_WIDTH( 8 ), + .din46_WIDTH( 8 ), + .din47_WIDTH( 8 ), + .din48_WIDTH( 8 ), + .din49_WIDTH( 8 ), + .din50_WIDTH( 8 ), + .din51_WIDTH( 8 ), + .din52_WIDTH( 8 ), + .din53_WIDTH( 8 ), + .din54_WIDTH( 8 ), + .din55_WIDTH( 8 ), + .din56_WIDTH( 8 ), + .din57_WIDTH( 8 ), + .din58_WIDTH( 8 ), + .din59_WIDTH( 8 ), + .din60_WIDTH( 8 ), + .din61_WIDTH( 8 ), + .din62_WIDTH( 8 ), + .din63_WIDTH( 8 ), + .din64_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_6432_8_1_1_U98( + .din0(acc_0_V_q1), + .din1(acc_1_V_q1), + .din2(acc_2_V_q1), + .din3(acc_3_V_q1), + .din4(acc_4_V_q1), + .din5(acc_5_V_q1), + .din6(acc_6_V_q1), + .din7(acc_7_V_q1), + .din8(acc_8_V_q1), + .din9(acc_9_V_q1), + .din10(acc_10_V_q1), + .din11(acc_11_V_q1), + .din12(acc_12_V_q1), + .din13(acc_13_V_q1), + .din14(acc_14_V_q1), + .din15(acc_15_V_q1), + .din16(acc_16_V_q1), + .din17(acc_17_V_q1), + .din18(acc_18_V_q1), + .din19(acc_19_V_q1), + .din20(acc_20_V_q1), + .din21(acc_21_V_q1), + .din22(acc_22_V_q1), + .din23(acc_23_V_q1), + .din24(acc_24_V_q1), + .din25(acc_25_V_q1), + .din26(acc_26_V_q1), + .din27(acc_27_V_q1), + .din28(acc_28_V_q1), + .din29(acc_29_V_q1), + .din30(acc_30_V_q1), + .din31(acc_31_V_q1), + .din32(acc_32_V_q1), + .din33(acc_33_V_q1), + .din34(acc_34_V_q1), + .din35(acc_35_V_q1), + .din36(acc_36_V_q1), + .din37(acc_37_V_q1), + .din38(acc_38_V_q1), + .din39(acc_39_V_q1), + .din40(acc_40_V_q1), + .din41(acc_41_V_q1), + .din42(acc_42_V_q1), + .din43(acc_43_V_q1), + .din44(acc_44_V_q1), + .din45(acc_45_V_q1), + .din46(acc_46_V_q1), + .din47(acc_47_V_q1), + .din48(acc_48_V_q1), + .din49(acc_49_V_q1), + .din50(acc_50_V_q1), + .din51(acc_51_V_q1), + .din52(acc_52_V_q1), + .din53(acc_53_V_q1), + .din54(acc_54_V_q1), + .din55(acc_55_V_q1), + .din56(acc_56_V_q1), + .din57(acc_57_V_q1), + .din58(acc_58_V_q1), + .din59(acc_59_V_q1), + .din60(acc_60_V_q1), + .din61(acc_61_V_q1), + .din62(acc_62_V_q1), + .din63(acc_63_V_q1), + .din64(zext_ln1265_28_reg_96702), + .dout(tmp_211_fu_85172_p66) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U99( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_85308_p0), + .din1(grp_fu_85308_p1), + .ce(1'b1), + .dout(grp_fu_85308_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U100( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_85166_p2), + .dout(tmp_213_fu_85355_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U101( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_85454_ap_start), + .done(grp_fu_85454_ap_done), + .din0(grp_fu_85454_p0), + .din1(grp_fu_85454_p1), + .ce(1'b1), + .dout(grp_fu_85454_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U102( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_85469_p0), + .din1(grp_fu_85469_p1), + .ce(1'b1), + .dout(grp_fu_85469_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U103( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_85454_p2), + .dout(tmp_231_fu_85516_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U104( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_85918_ap_start), + .done(grp_fu_85918_ap_done), + .din0(grp_fu_85918_p0), + .din1(grp_fu_85918_p1), + .ce(1'b1), + .dout(grp_fu_85918_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U105( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_85927_p0), + .din1(grp_fu_85927_p1), + .ce(1'b1), + .dout(grp_fu_85927_p2) +); + +myproject_mux_6432_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 8 ), + .din29_WIDTH( 8 ), + .din30_WIDTH( 8 ), + .din31_WIDTH( 8 ), + .din32_WIDTH( 8 ), + .din33_WIDTH( 8 ), + .din34_WIDTH( 8 ), + .din35_WIDTH( 8 ), + .din36_WIDTH( 8 ), + .din37_WIDTH( 8 ), + .din38_WIDTH( 8 ), + .din39_WIDTH( 8 ), + .din40_WIDTH( 8 ), + .din41_WIDTH( 8 ), + .din42_WIDTH( 8 ), + .din43_WIDTH( 8 ), + .din44_WIDTH( 8 ), + .din45_WIDTH( 8 ), + .din46_WIDTH( 8 ), + .din47_WIDTH( 8 ), + .din48_WIDTH( 8 ), + .din49_WIDTH( 8 ), + .din50_WIDTH( 8 ), + .din51_WIDTH( 8 ), + .din52_WIDTH( 8 ), + .din53_WIDTH( 8 ), + .din54_WIDTH( 8 ), + .din55_WIDTH( 8 ), + .din56_WIDTH( 8 ), + .din57_WIDTH( 8 ), + .din58_WIDTH( 8 ), + .din59_WIDTH( 8 ), + .din60_WIDTH( 8 ), + .din61_WIDTH( 8 ), + .din62_WIDTH( 8 ), + .din63_WIDTH( 8 ), + .din64_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_6432_8_1_1_U106( + .din0(acc_0_V_q0), + .din1(acc_1_V_q0), + .din2(acc_2_V_q0), + .din3(acc_3_V_q0), + .din4(acc_4_V_q0), + .din5(acc_5_V_q0), + .din6(acc_6_V_q0), + .din7(acc_7_V_q0), + .din8(acc_8_V_q0), + .din9(acc_9_V_q0), + .din10(acc_10_V_q0), + .din11(acc_11_V_q0), + .din12(acc_12_V_q0), + .din13(acc_13_V_q0), + .din14(acc_14_V_q0), + .din15(acc_15_V_q0), + .din16(acc_16_V_q0), + .din17(acc_17_V_q0), + .din18(acc_18_V_q0), + .din19(acc_19_V_q0), + .din20(acc_20_V_q0), + .din21(acc_21_V_q0), + .din22(acc_22_V_q0), + .din23(acc_23_V_q0), + .din24(acc_24_V_q0), + .din25(acc_25_V_q0), + .din26(acc_26_V_q0), + .din27(acc_27_V_q0), + .din28(acc_28_V_q0), + .din29(acc_29_V_q0), + .din30(acc_30_V_q0), + .din31(acc_31_V_q0), + .din32(acc_32_V_q0), + .din33(acc_33_V_q0), + .din34(acc_34_V_q0), + .din35(acc_35_V_q0), + .din36(acc_36_V_q0), + .din37(acc_37_V_q0), + .din38(acc_38_V_q0), + .din39(acc_39_V_q0), + .din40(acc_40_V_q0), + .din41(acc_41_V_q0), + .din42(acc_42_V_q0), + .din43(acc_43_V_q0), + .din44(acc_44_V_q0), + .din45(acc_45_V_q0), + .din46(acc_46_V_q0), + .din47(acc_47_V_q0), + .din48(acc_48_V_q0), + .din49(acc_49_V_q0), + .din50(acc_50_V_q0), + .din51(acc_51_V_q0), + .din52(acc_52_V_q0), + .din53(acc_53_V_q0), + .din54(acc_54_V_q0), + .din55(acc_55_V_q0), + .din56(acc_56_V_q0), + .din57(acc_57_V_q0), + .din58(acc_58_V_q0), + .din59(acc_59_V_q0), + .din60(acc_60_V_q0), + .din61(acc_61_V_q0), + .din62(acc_62_V_q0), + .din63(acc_63_V_q0), + .din64(zext_ln1265_5_reg_98335), + .dout(tmp_68_fu_85974_p66) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U107( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_85918_p2), + .dout(tmp_70_fu_86107_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U108( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_86223_ap_start), + .done(grp_fu_86223_ap_done), + .din0(grp_fu_86223_p0), + .din1(grp_fu_86223_p1), + .ce(1'b1), + .dout(grp_fu_86223_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U109( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_86299_p0), + .din1(grp_fu_86299_p1), + .ce(1'b1), + .dout(grp_fu_86299_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U110( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_86223_p2), + .dout(tmp_96_fu_86346_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U111( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_86456_ap_start), + .done(grp_fu_86456_ap_done), + .din0(grp_fu_86456_p0), + .din1(grp_fu_86456_p1), + .ce(1'b1), + .dout(grp_fu_86456_p2) +); + +myproject_mux_6432_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 8 ), + .din29_WIDTH( 8 ), + .din30_WIDTH( 8 ), + .din31_WIDTH( 8 ), + .din32_WIDTH( 8 ), + .din33_WIDTH( 8 ), + .din34_WIDTH( 8 ), + .din35_WIDTH( 8 ), + .din36_WIDTH( 8 ), + .din37_WIDTH( 8 ), + .din38_WIDTH( 8 ), + .din39_WIDTH( 8 ), + .din40_WIDTH( 8 ), + .din41_WIDTH( 8 ), + .din42_WIDTH( 8 ), + .din43_WIDTH( 8 ), + .din44_WIDTH( 8 ), + .din45_WIDTH( 8 ), + .din46_WIDTH( 8 ), + .din47_WIDTH( 8 ), + .din48_WIDTH( 8 ), + .din49_WIDTH( 8 ), + .din50_WIDTH( 8 ), + .din51_WIDTH( 8 ), + .din52_WIDTH( 8 ), + .din53_WIDTH( 8 ), + .din54_WIDTH( 8 ), + .din55_WIDTH( 8 ), + .din56_WIDTH( 8 ), + .din57_WIDTH( 8 ), + .din58_WIDTH( 8 ), + .din59_WIDTH( 8 ), + .din60_WIDTH( 8 ), + .din61_WIDTH( 8 ), + .din62_WIDTH( 8 ), + .din63_WIDTH( 8 ), + .din64_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_6432_8_1_1_U112( + .din0(acc_0_V_q1), + .din1(acc_1_V_q1), + .din2(acc_2_V_q1), + .din3(acc_3_V_q1), + .din4(acc_4_V_q1), + .din5(acc_5_V_q1), + .din6(acc_6_V_q1), + .din7(acc_7_V_q1), + .din8(acc_8_V_q1), + .din9(acc_9_V_q1), + .din10(acc_10_V_q1), + .din11(acc_11_V_q1), + .din12(acc_12_V_q1), + .din13(acc_13_V_q1), + .din14(acc_14_V_q1), + .din15(acc_15_V_q1), + .din16(acc_16_V_q1), + .din17(acc_17_V_q1), + .din18(acc_18_V_q1), + .din19(acc_19_V_q1), + .din20(acc_20_V_q1), + .din21(acc_21_V_q1), + .din22(acc_22_V_q1), + .din23(acc_23_V_q1), + .din24(acc_24_V_q1), + .din25(acc_25_V_q1), + .din26(acc_26_V_q1), + .din27(acc_27_V_q1), + .din28(acc_28_V_q1), + .din29(acc_29_V_q1), + .din30(acc_30_V_q1), + .din31(acc_31_V_q1), + .din32(acc_32_V_q1), + .din33(acc_33_V_q1), + .din34(acc_34_V_q1), + .din35(acc_35_V_q1), + .din36(acc_36_V_q1), + .din37(acc_37_V_q1), + .din38(acc_38_V_q1), + .din39(acc_39_V_q1), + .din40(acc_40_V_q1), + .din41(acc_41_V_q1), + .din42(acc_42_V_q1), + .din43(acc_43_V_q1), + .din44(acc_44_V_q1), + .din45(acc_45_V_q1), + .din46(acc_46_V_q1), + .din47(acc_47_V_q1), + .din48(acc_48_V_q1), + .din49(acc_49_V_q1), + .din50(acc_50_V_q1), + .din51(acc_51_V_q1), + .din52(acc_52_V_q1), + .din53(acc_53_V_q1), + .din54(acc_54_V_q1), + .din55(acc_55_V_q1), + .din56(acc_56_V_q1), + .din57(acc_57_V_q1), + .din58(acc_58_V_q1), + .din59(acc_59_V_q1), + .din60(acc_60_V_q1), + .din61(acc_61_V_q1), + .din62(acc_62_V_q1), + .din63(acc_63_V_q1), + .din64(zext_ln1265_5_reg_98335), + .dout(tmp_135_fu_86462_p66) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U113( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_86598_p0), + .din1(grp_fu_86598_p1), + .ce(1'b1), + .dout(grp_fu_86598_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U114( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_86456_p2), + .dout(tmp_137_fu_86645_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U115( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_86761_ap_start), + .done(grp_fu_86761_ap_done), + .din0(grp_fu_86761_p0), + .din1(grp_fu_86761_p1), + .ce(1'b1), + .dout(grp_fu_86761_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U116( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_86776_p0), + .din1(grp_fu_86776_p1), + .ce(1'b1), + .dout(grp_fu_86776_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U117( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_86761_p2), + .dout(tmp_182_fu_86823_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U118( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_86950_ap_start), + .done(grp_fu_86950_ap_done), + .din0(grp_fu_86950_p0), + .din1(grp_fu_86950_p1), + .ce(1'b1), + .dout(grp_fu_86950_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U119( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_86959_p0), + .din1(grp_fu_86959_p1), + .ce(1'b1), + .dout(grp_fu_86959_p2) +); + +myproject_mux_6432_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 8 ), + .din29_WIDTH( 8 ), + .din30_WIDTH( 8 ), + .din31_WIDTH( 8 ), + .din32_WIDTH( 8 ), + .din33_WIDTH( 8 ), + .din34_WIDTH( 8 ), + .din35_WIDTH( 8 ), + .din36_WIDTH( 8 ), + .din37_WIDTH( 8 ), + .din38_WIDTH( 8 ), + .din39_WIDTH( 8 ), + .din40_WIDTH( 8 ), + .din41_WIDTH( 8 ), + .din42_WIDTH( 8 ), + .din43_WIDTH( 8 ), + .din44_WIDTH( 8 ), + .din45_WIDTH( 8 ), + .din46_WIDTH( 8 ), + .din47_WIDTH( 8 ), + .din48_WIDTH( 8 ), + .din49_WIDTH( 8 ), + .din50_WIDTH( 8 ), + .din51_WIDTH( 8 ), + .din52_WIDTH( 8 ), + .din53_WIDTH( 8 ), + .din54_WIDTH( 8 ), + .din55_WIDTH( 8 ), + .din56_WIDTH( 8 ), + .din57_WIDTH( 8 ), + .din58_WIDTH( 8 ), + .din59_WIDTH( 8 ), + .din60_WIDTH( 8 ), + .din61_WIDTH( 8 ), + .din62_WIDTH( 8 ), + .din63_WIDTH( 8 ), + .din64_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_6432_8_1_1_U120( + .din0(acc_0_V_q0), + .din1(acc_1_V_q0), + .din2(acc_2_V_q0), + .din3(acc_3_V_q0), + .din4(acc_4_V_q0), + .din5(acc_5_V_q0), + .din6(acc_6_V_q0), + .din7(acc_7_V_q0), + .din8(acc_8_V_q0), + .din9(acc_9_V_q0), + .din10(acc_10_V_q0), + .din11(acc_11_V_q0), + .din12(acc_12_V_q0), + .din13(acc_13_V_q0), + .din14(acc_14_V_q0), + .din15(acc_15_V_q0), + .din16(acc_16_V_q0), + .din17(acc_17_V_q0), + .din18(acc_18_V_q0), + .din19(acc_19_V_q0), + .din20(acc_20_V_q0), + .din21(acc_21_V_q0), + .din22(acc_22_V_q0), + .din23(acc_23_V_q0), + .din24(acc_24_V_q0), + .din25(acc_25_V_q0), + .din26(acc_26_V_q0), + .din27(acc_27_V_q0), + .din28(acc_28_V_q0), + .din29(acc_29_V_q0), + .din30(acc_30_V_q0), + .din31(acc_31_V_q0), + .din32(acc_32_V_q0), + .din33(acc_33_V_q0), + .din34(acc_34_V_q0), + .din35(acc_35_V_q0), + .din36(acc_36_V_q0), + .din37(acc_37_V_q0), + .din38(acc_38_V_q0), + .din39(acc_39_V_q0), + .din40(acc_40_V_q0), + .din41(acc_41_V_q0), + .din42(acc_42_V_q0), + .din43(acc_43_V_q0), + .din44(acc_44_V_q0), + .din45(acc_45_V_q0), + .din46(acc_46_V_q0), + .din47(acc_47_V_q0), + .din48(acc_48_V_q0), + .din49(acc_49_V_q0), + .din50(acc_50_V_q0), + .din51(acc_51_V_q0), + .din52(acc_52_V_q0), + .din53(acc_53_V_q0), + .din54(acc_54_V_q0), + .din55(acc_55_V_q0), + .din56(acc_56_V_q0), + .din57(acc_57_V_q0), + .din58(acc_58_V_q0), + .din59(acc_59_V_q0), + .din60(acc_60_V_q0), + .din61(acc_61_V_q0), + .din62(acc_62_V_q0), + .din63(acc_63_V_q0), + .din64(zext_ln1265_27_reg_98947), + .dout(tmp_150_fu_87006_p66) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U121( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_86950_p2), + .dout(tmp_152_fu_87139_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U122( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_87239_ap_start), + .done(grp_fu_87239_ap_done), + .din0(grp_fu_87239_p0), + .din1(grp_fu_87239_p1), + .ce(1'b1), + .dout(grp_fu_87239_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U123( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_87283_p0), + .din1(grp_fu_87283_p1), + .ce(1'b1), + .dout(grp_fu_87283_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U124( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_87239_p2), + .dout(tmp_191_fu_87330_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U125( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_87424_ap_start), + .done(grp_fu_87424_ap_done), + .din0(grp_fu_87424_p0), + .din1(grp_fu_87424_p1), + .ce(1'b1), + .dout(grp_fu_87424_p2) +); + +myproject_mux_6432_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 8 ), + .din29_WIDTH( 8 ), + .din30_WIDTH( 8 ), + .din31_WIDTH( 8 ), + .din32_WIDTH( 8 ), + .din33_WIDTH( 8 ), + .din34_WIDTH( 8 ), + .din35_WIDTH( 8 ), + .din36_WIDTH( 8 ), + .din37_WIDTH( 8 ), + .din38_WIDTH( 8 ), + .din39_WIDTH( 8 ), + .din40_WIDTH( 8 ), + .din41_WIDTH( 8 ), + .din42_WIDTH( 8 ), + .din43_WIDTH( 8 ), + .din44_WIDTH( 8 ), + .din45_WIDTH( 8 ), + .din46_WIDTH( 8 ), + .din47_WIDTH( 8 ), + .din48_WIDTH( 8 ), + .din49_WIDTH( 8 ), + .din50_WIDTH( 8 ), + .din51_WIDTH( 8 ), + .din52_WIDTH( 8 ), + .din53_WIDTH( 8 ), + .din54_WIDTH( 8 ), + .din55_WIDTH( 8 ), + .din56_WIDTH( 8 ), + .din57_WIDTH( 8 ), + .din58_WIDTH( 8 ), + .din59_WIDTH( 8 ), + .din60_WIDTH( 8 ), + .din61_WIDTH( 8 ), + .din62_WIDTH( 8 ), + .din63_WIDTH( 8 ), + .din64_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_6432_8_1_1_U126( + .din0(acc_0_V_q1), + .din1(acc_1_V_q1), + .din2(acc_2_V_q1), + .din3(acc_3_V_q1), + .din4(acc_4_V_q1), + .din5(acc_5_V_q1), + .din6(acc_6_V_q1), + .din7(acc_7_V_q1), + .din8(acc_8_V_q1), + .din9(acc_9_V_q1), + .din10(acc_10_V_q1), + .din11(acc_11_V_q1), + .din12(acc_12_V_q1), + .din13(acc_13_V_q1), + .din14(acc_14_V_q1), + .din15(acc_15_V_q1), + .din16(acc_16_V_q1), + .din17(acc_17_V_q1), + .din18(acc_18_V_q1), + .din19(acc_19_V_q1), + .din20(acc_20_V_q1), + .din21(acc_21_V_q1), + .din22(acc_22_V_q1), + .din23(acc_23_V_q1), + .din24(acc_24_V_q1), + .din25(acc_25_V_q1), + .din26(acc_26_V_q1), + .din27(acc_27_V_q1), + .din28(acc_28_V_q1), + .din29(acc_29_V_q1), + .din30(acc_30_V_q1), + .din31(acc_31_V_q1), + .din32(acc_32_V_q1), + .din33(acc_33_V_q1), + .din34(acc_34_V_q1), + .din35(acc_35_V_q1), + .din36(acc_36_V_q1), + .din37(acc_37_V_q1), + .din38(acc_38_V_q1), + .din39(acc_39_V_q1), + .din40(acc_40_V_q1), + .din41(acc_41_V_q1), + .din42(acc_42_V_q1), + .din43(acc_43_V_q1), + .din44(acc_44_V_q1), + .din45(acc_45_V_q1), + .din46(acc_46_V_q1), + .din47(acc_47_V_q1), + .din48(acc_48_V_q1), + .din49(acc_49_V_q1), + .din50(acc_50_V_q1), + .din51(acc_51_V_q1), + .din52(acc_52_V_q1), + .din53(acc_53_V_q1), + .din54(acc_54_V_q1), + .din55(acc_55_V_q1), + .din56(acc_56_V_q1), + .din57(acc_57_V_q1), + .din58(acc_58_V_q1), + .din59(acc_59_V_q1), + .din60(acc_60_V_q1), + .din61(acc_61_V_q1), + .din62(acc_62_V_q1), + .din63(acc_63_V_q1), + .din64(zext_ln1265_27_reg_98947), + .dout(tmp_208_fu_87430_p66) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U127( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_87566_p0), + .din1(grp_fu_87566_p1), + .ce(1'b1), + .dout(grp_fu_87566_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U128( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_87424_p2), + .dout(tmp_210_fu_87613_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U129( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_87713_ap_start), + .done(grp_fu_87713_ap_done), + .din0(grp_fu_87713_p0), + .din1(grp_fu_87713_p1), + .ce(1'b1), + .dout(grp_fu_87713_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U130( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_87728_p0), + .din1(grp_fu_87728_p1), + .ce(1'b1), + .dout(grp_fu_87728_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U131( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_87713_p2), + .dout(tmp_230_fu_87775_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U132( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_88009_ap_start), + .done(grp_fu_88009_ap_done), + .din0(grp_fu_88009_p0), + .din1(grp_fu_88009_p1), + .ce(1'b1), + .dout(grp_fu_88009_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U133( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_88018_p0), + .din1(grp_fu_88018_p1), + .ce(1'b1), + .dout(grp_fu_88018_p2) +); + +myproject_mux_6432_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 8 ), + .din29_WIDTH( 8 ), + .din30_WIDTH( 8 ), + .din31_WIDTH( 8 ), + .din32_WIDTH( 8 ), + .din33_WIDTH( 8 ), + .din34_WIDTH( 8 ), + .din35_WIDTH( 8 ), + .din36_WIDTH( 8 ), + .din37_WIDTH( 8 ), + .din38_WIDTH( 8 ), + .din39_WIDTH( 8 ), + .din40_WIDTH( 8 ), + .din41_WIDTH( 8 ), + .din42_WIDTH( 8 ), + .din43_WIDTH( 8 ), + .din44_WIDTH( 8 ), + .din45_WIDTH( 8 ), + .din46_WIDTH( 8 ), + .din47_WIDTH( 8 ), + .din48_WIDTH( 8 ), + .din49_WIDTH( 8 ), + .din50_WIDTH( 8 ), + .din51_WIDTH( 8 ), + .din52_WIDTH( 8 ), + .din53_WIDTH( 8 ), + .din54_WIDTH( 8 ), + .din55_WIDTH( 8 ), + .din56_WIDTH( 8 ), + .din57_WIDTH( 8 ), + .din58_WIDTH( 8 ), + .din59_WIDTH( 8 ), + .din60_WIDTH( 8 ), + .din61_WIDTH( 8 ), + .din62_WIDTH( 8 ), + .din63_WIDTH( 8 ), + .din64_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_6432_8_1_1_U134( + .din0(acc_0_V_q0), + .din1(acc_1_V_q0), + .din2(acc_2_V_q0), + .din3(acc_3_V_q0), + .din4(acc_4_V_q0), + .din5(acc_5_V_q0), + .din6(acc_6_V_q0), + .din7(acc_7_V_q0), + .din8(acc_8_V_q0), + .din9(acc_9_V_q0), + .din10(acc_10_V_q0), + .din11(acc_11_V_q0), + .din12(acc_12_V_q0), + .din13(acc_13_V_q0), + .din14(acc_14_V_q0), + .din15(acc_15_V_q0), + .din16(acc_16_V_q0), + .din17(acc_17_V_q0), + .din18(acc_18_V_q0), + .din19(acc_19_V_q0), + .din20(acc_20_V_q0), + .din21(acc_21_V_q0), + .din22(acc_22_V_q0), + .din23(acc_23_V_q0), + .din24(acc_24_V_q0), + .din25(acc_25_V_q0), + .din26(acc_26_V_q0), + .din27(acc_27_V_q0), + .din28(acc_28_V_q0), + .din29(acc_29_V_q0), + .din30(acc_30_V_q0), + .din31(acc_31_V_q0), + .din32(acc_32_V_q0), + .din33(acc_33_V_q0), + .din34(acc_34_V_q0), + .din35(acc_35_V_q0), + .din36(acc_36_V_q0), + .din37(acc_37_V_q0), + .din38(acc_38_V_q0), + .din39(acc_39_V_q0), + .din40(acc_40_V_q0), + .din41(acc_41_V_q0), + .din42(acc_42_V_q0), + .din43(acc_43_V_q0), + .din44(acc_44_V_q0), + .din45(acc_45_V_q0), + .din46(acc_46_V_q0), + .din47(acc_47_V_q0), + .din48(acc_48_V_q0), + .din49(acc_49_V_q0), + .din50(acc_50_V_q0), + .din51(acc_51_V_q0), + .din52(acc_52_V_q0), + .din53(acc_53_V_q0), + .din54(acc_54_V_q0), + .din55(acc_55_V_q0), + .din56(acc_56_V_q0), + .din57(acc_57_V_q0), + .din58(acc_58_V_q0), + .din59(acc_59_V_q0), + .din60(acc_60_V_q0), + .din61(acc_61_V_q0), + .din62(acc_62_V_q0), + .din63(acc_63_V_q0), + .din64(zext_ln1265_10_reg_100176), + .dout(tmp_85_fu_88065_p66) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U135( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_88009_p2), + .dout(tmp_87_fu_88198_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U136( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_88314_ap_start), + .done(grp_fu_88314_ap_done), + .din0(grp_fu_88314_p0), + .din1(grp_fu_88314_p1), + .ce(1'b1), + .dout(grp_fu_88314_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U137( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_88390_p0), + .din1(grp_fu_88390_p1), + .ce(1'b1), + .dout(grp_fu_88390_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U138( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_88314_p2), + .dout(tmp_133_fu_88437_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U139( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_88547_ap_start), + .done(grp_fu_88547_ap_done), + .din0(grp_fu_88547_p0), + .din1(grp_fu_88547_p1), + .ce(1'b1), + .dout(grp_fu_88547_p2) +); + +myproject_mux_6432_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 8 ), + .din29_WIDTH( 8 ), + .din30_WIDTH( 8 ), + .din31_WIDTH( 8 ), + .din32_WIDTH( 8 ), + .din33_WIDTH( 8 ), + .din34_WIDTH( 8 ), + .din35_WIDTH( 8 ), + .din36_WIDTH( 8 ), + .din37_WIDTH( 8 ), + .din38_WIDTH( 8 ), + .din39_WIDTH( 8 ), + .din40_WIDTH( 8 ), + .din41_WIDTH( 8 ), + .din42_WIDTH( 8 ), + .din43_WIDTH( 8 ), + .din44_WIDTH( 8 ), + .din45_WIDTH( 8 ), + .din46_WIDTH( 8 ), + .din47_WIDTH( 8 ), + .din48_WIDTH( 8 ), + .din49_WIDTH( 8 ), + .din50_WIDTH( 8 ), + .din51_WIDTH( 8 ), + .din52_WIDTH( 8 ), + .din53_WIDTH( 8 ), + .din54_WIDTH( 8 ), + .din55_WIDTH( 8 ), + .din56_WIDTH( 8 ), + .din57_WIDTH( 8 ), + .din58_WIDTH( 8 ), + .din59_WIDTH( 8 ), + .din60_WIDTH( 8 ), + .din61_WIDTH( 8 ), + .din62_WIDTH( 8 ), + .din63_WIDTH( 8 ), + .din64_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_6432_8_1_1_U140( + .din0(acc_0_V_q1), + .din1(acc_1_V_q1), + .din2(acc_2_V_q1), + .din3(acc_3_V_q1), + .din4(acc_4_V_q1), + .din5(acc_5_V_q1), + .din6(acc_6_V_q1), + .din7(acc_7_V_q1), + .din8(acc_8_V_q1), + .din9(acc_9_V_q1), + .din10(acc_10_V_q1), + .din11(acc_11_V_q1), + .din12(acc_12_V_q1), + .din13(acc_13_V_q1), + .din14(acc_14_V_q1), + .din15(acc_15_V_q1), + .din16(acc_16_V_q1), + .din17(acc_17_V_q1), + .din18(acc_18_V_q1), + .din19(acc_19_V_q1), + .din20(acc_20_V_q1), + .din21(acc_21_V_q1), + .din22(acc_22_V_q1), + .din23(acc_23_V_q1), + .din24(acc_24_V_q1), + .din25(acc_25_V_q1), + .din26(acc_26_V_q1), + .din27(acc_27_V_q1), + .din28(acc_28_V_q1), + .din29(acc_29_V_q1), + .din30(acc_30_V_q1), + .din31(acc_31_V_q1), + .din32(acc_32_V_q1), + .din33(acc_33_V_q1), + .din34(acc_34_V_q1), + .din35(acc_35_V_q1), + .din36(acc_36_V_q1), + .din37(acc_37_V_q1), + .din38(acc_38_V_q1), + .din39(acc_39_V_q1), + .din40(acc_40_V_q1), + .din41(acc_41_V_q1), + .din42(acc_42_V_q1), + .din43(acc_43_V_q1), + .din44(acc_44_V_q1), + .din45(acc_45_V_q1), + .din46(acc_46_V_q1), + .din47(acc_47_V_q1), + .din48(acc_48_V_q1), + .din49(acc_49_V_q1), + .din50(acc_50_V_q1), + .din51(acc_51_V_q1), + .din52(acc_52_V_q1), + .din53(acc_53_V_q1), + .din54(acc_54_V_q1), + .din55(acc_55_V_q1), + .din56(acc_56_V_q1), + .din57(acc_57_V_q1), + .din58(acc_58_V_q1), + .din59(acc_59_V_q1), + .din60(acc_60_V_q1), + .din61(acc_61_V_q1), + .din62(acc_62_V_q1), + .din63(acc_63_V_q1), + .din64(zext_ln1265_10_reg_100176), + .dout(tmp_172_fu_88553_p66) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U141( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_88689_p0), + .din1(grp_fu_88689_p1), + .ce(1'b1), + .dout(grp_fu_88689_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U142( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_88547_p2), + .dout(tmp_174_fu_88736_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U143( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_88852_ap_start), + .done(grp_fu_88852_ap_done), + .din0(grp_fu_88852_p0), + .din1(grp_fu_88852_p1), + .ce(1'b1), + .dout(grp_fu_88852_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U144( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_88867_p0), + .din1(grp_fu_88867_p1), + .ce(1'b1), + .dout(grp_fu_88867_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U145( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_88852_p2), + .dout(tmp_199_fu_88914_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U146( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_89041_ap_start), + .done(grp_fu_89041_ap_done), + .din0(grp_fu_89041_p0), + .din1(grp_fu_89041_p1), + .ce(1'b1), + .dout(grp_fu_89041_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U147( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_89050_p0), + .din1(grp_fu_89050_p1), + .ce(1'b1), + .dout(grp_fu_89050_p2) +); + +myproject_mux_6432_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 8 ), + .din29_WIDTH( 8 ), + .din30_WIDTH( 8 ), + .din31_WIDTH( 8 ), + .din32_WIDTH( 8 ), + .din33_WIDTH( 8 ), + .din34_WIDTH( 8 ), + .din35_WIDTH( 8 ), + .din36_WIDTH( 8 ), + .din37_WIDTH( 8 ), + .din38_WIDTH( 8 ), + .din39_WIDTH( 8 ), + .din40_WIDTH( 8 ), + .din41_WIDTH( 8 ), + .din42_WIDTH( 8 ), + .din43_WIDTH( 8 ), + .din44_WIDTH( 8 ), + .din45_WIDTH( 8 ), + .din46_WIDTH( 8 ), + .din47_WIDTH( 8 ), + .din48_WIDTH( 8 ), + .din49_WIDTH( 8 ), + .din50_WIDTH( 8 ), + .din51_WIDTH( 8 ), + .din52_WIDTH( 8 ), + .din53_WIDTH( 8 ), + .din54_WIDTH( 8 ), + .din55_WIDTH( 8 ), + .din56_WIDTH( 8 ), + .din57_WIDTH( 8 ), + .din58_WIDTH( 8 ), + .din59_WIDTH( 8 ), + .din60_WIDTH( 8 ), + .din61_WIDTH( 8 ), + .din62_WIDTH( 8 ), + .din63_WIDTH( 8 ), + .din64_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_6432_8_1_1_U148( + .din0(acc_0_V_q0), + .din1(acc_1_V_q0), + .din2(acc_2_V_q0), + .din3(acc_3_V_q0), + .din4(acc_4_V_q0), + .din5(acc_5_V_q0), + .din6(acc_6_V_q0), + .din7(acc_7_V_q0), + .din8(acc_8_V_q0), + .din9(acc_9_V_q0), + .din10(acc_10_V_q0), + .din11(acc_11_V_q0), + .din12(acc_12_V_q0), + .din13(acc_13_V_q0), + .din14(acc_14_V_q0), + .din15(acc_15_V_q0), + .din16(acc_16_V_q0), + .din17(acc_17_V_q0), + .din18(acc_18_V_q0), + .din19(acc_19_V_q0), + .din20(acc_20_V_q0), + .din21(acc_21_V_q0), + .din22(acc_22_V_q0), + .din23(acc_23_V_q0), + .din24(acc_24_V_q0), + .din25(acc_25_V_q0), + .din26(acc_26_V_q0), + .din27(acc_27_V_q0), + .din28(acc_28_V_q0), + .din29(acc_29_V_q0), + .din30(acc_30_V_q0), + .din31(acc_31_V_q0), + .din32(acc_32_V_q0), + .din33(acc_33_V_q0), + .din34(acc_34_V_q0), + .din35(acc_35_V_q0), + .din36(acc_36_V_q0), + .din37(acc_37_V_q0), + .din38(acc_38_V_q0), + .din39(acc_39_V_q0), + .din40(acc_40_V_q0), + .din41(acc_41_V_q0), + .din42(acc_42_V_q0), + .din43(acc_43_V_q0), + .din44(acc_44_V_q0), + .din45(acc_45_V_q0), + .din46(acc_46_V_q0), + .din47(acc_47_V_q0), + .din48(acc_48_V_q0), + .din49(acc_49_V_q0), + .din50(acc_50_V_q0), + .din51(acc_51_V_q0), + .din52(acc_52_V_q0), + .din53(acc_53_V_q0), + .din54(acc_54_V_q0), + .din55(acc_55_V_q0), + .din56(acc_56_V_q0), + .din57(acc_57_V_q0), + .din58(acc_58_V_q0), + .din59(acc_59_V_q0), + .din60(acc_60_V_q0), + .din61(acc_61_V_q0), + .din62(acc_62_V_q0), + .din63(acc_63_V_q0), + .din64(zext_ln1265_37_reg_100776), + .dout(tmp_178_fu_89097_p66) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U149( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_89041_p2), + .dout(tmp_180_fu_89230_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U150( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_89329_ap_start), + .done(grp_fu_89329_ap_done), + .din0(grp_fu_89329_p0), + .din1(grp_fu_89329_p1), + .ce(1'b1), + .dout(grp_fu_89329_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U151( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_89373_p0), + .din1(grp_fu_89373_p1), + .ce(1'b1), + .dout(grp_fu_89373_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U152( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_89329_p2), + .dout(tmp_207_fu_89420_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U153( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_89513_ap_start), + .done(grp_fu_89513_ap_done), + .din0(grp_fu_89513_p0), + .din1(grp_fu_89513_p1), + .ce(1'b1), + .dout(grp_fu_89513_p2) +); + +myproject_mux_6432_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 8 ), + .din29_WIDTH( 8 ), + .din30_WIDTH( 8 ), + .din31_WIDTH( 8 ), + .din32_WIDTH( 8 ), + .din33_WIDTH( 8 ), + .din34_WIDTH( 8 ), + .din35_WIDTH( 8 ), + .din36_WIDTH( 8 ), + .din37_WIDTH( 8 ), + .din38_WIDTH( 8 ), + .din39_WIDTH( 8 ), + .din40_WIDTH( 8 ), + .din41_WIDTH( 8 ), + .din42_WIDTH( 8 ), + .din43_WIDTH( 8 ), + .din44_WIDTH( 8 ), + .din45_WIDTH( 8 ), + .din46_WIDTH( 8 ), + .din47_WIDTH( 8 ), + .din48_WIDTH( 8 ), + .din49_WIDTH( 8 ), + .din50_WIDTH( 8 ), + .din51_WIDTH( 8 ), + .din52_WIDTH( 8 ), + .din53_WIDTH( 8 ), + .din54_WIDTH( 8 ), + .din55_WIDTH( 8 ), + .din56_WIDTH( 8 ), + .din57_WIDTH( 8 ), + .din58_WIDTH( 8 ), + .din59_WIDTH( 8 ), + .din60_WIDTH( 8 ), + .din61_WIDTH( 8 ), + .din62_WIDTH( 8 ), + .din63_WIDTH( 8 ), + .din64_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_6432_8_1_1_U154( + .din0(acc_0_V_q1), + .din1(acc_1_V_q1), + .din2(acc_2_V_q1), + .din3(acc_3_V_q1), + .din4(acc_4_V_q1), + .din5(acc_5_V_q1), + .din6(acc_6_V_q1), + .din7(acc_7_V_q1), + .din8(acc_8_V_q1), + .din9(acc_9_V_q1), + .din10(acc_10_V_q1), + .din11(acc_11_V_q1), + .din12(acc_12_V_q1), + .din13(acc_13_V_q1), + .din14(acc_14_V_q1), + .din15(acc_15_V_q1), + .din16(acc_16_V_q1), + .din17(acc_17_V_q1), + .din18(acc_18_V_q1), + .din19(acc_19_V_q1), + .din20(acc_20_V_q1), + .din21(acc_21_V_q1), + .din22(acc_22_V_q1), + .din23(acc_23_V_q1), + .din24(acc_24_V_q1), + .din25(acc_25_V_q1), + .din26(acc_26_V_q1), + .din27(acc_27_V_q1), + .din28(acc_28_V_q1), + .din29(acc_29_V_q1), + .din30(acc_30_V_q1), + .din31(acc_31_V_q1), + .din32(acc_32_V_q1), + .din33(acc_33_V_q1), + .din34(acc_34_V_q1), + .din35(acc_35_V_q1), + .din36(acc_36_V_q1), + .din37(acc_37_V_q1), + .din38(acc_38_V_q1), + .din39(acc_39_V_q1), + .din40(acc_40_V_q1), + .din41(acc_41_V_q1), + .din42(acc_42_V_q1), + .din43(acc_43_V_q1), + .din44(acc_44_V_q1), + .din45(acc_45_V_q1), + .din46(acc_46_V_q1), + .din47(acc_47_V_q1), + .din48(acc_48_V_q1), + .din49(acc_49_V_q1), + .din50(acc_50_V_q1), + .din51(acc_51_V_q1), + .din52(acc_52_V_q1), + .din53(acc_53_V_q1), + .din54(acc_54_V_q1), + .din55(acc_55_V_q1), + .din56(acc_56_V_q1), + .din57(acc_57_V_q1), + .din58(acc_58_V_q1), + .din59(acc_59_V_q1), + .din60(acc_60_V_q1), + .din61(acc_61_V_q1), + .din62(acc_62_V_q1), + .din63(acc_63_V_q1), + .din64(zext_ln1265_37_reg_100776), + .dout(tmp_227_fu_89519_p66) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U155( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_89655_p0), + .din1(grp_fu_89655_p1), + .ce(1'b1), + .dout(grp_fu_89655_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U156( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_89513_p2), + .dout(tmp_229_fu_89702_p30) +); + +myproject_urem_32ns_6ns_32_36_seq_1 #( + .ID( 1 ), + .NUM_STAGE( 36 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 6 ), + .dout_WIDTH( 32 )) +myproject_urem_32ns_6ns_32_36_seq_1_U157( + .clk(ap_clk), + .reset(ap_rst), + .start(grp_fu_89801_ap_start), + .done(grp_fu_89801_ap_done), + .din0(grp_fu_89801_p0), + .din1(grp_fu_89801_p1), + .ce(1'b1), + .dout(grp_fu_89801_p2) +); + +myproject_mul_32ns_34ns_65_2_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 34 ), + .dout_WIDTH( 65 )) +myproject_mul_32ns_34ns_65_2_1_U158( + .clk(ap_clk), + .reset(ap_rst), + .din0(grp_fu_89816_p0), + .din1(grp_fu_89816_p1), + .ce(1'b1), + .dout(grp_fu_89816_p2) +); + +myproject_mux_2832_8_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 8 ), + .din2_WIDTH( 8 ), + .din3_WIDTH( 8 ), + .din4_WIDTH( 8 ), + .din5_WIDTH( 8 ), + .din6_WIDTH( 8 ), + .din7_WIDTH( 8 ), + .din8_WIDTH( 8 ), + .din9_WIDTH( 8 ), + .din10_WIDTH( 8 ), + .din11_WIDTH( 8 ), + .din12_WIDTH( 8 ), + .din13_WIDTH( 8 ), + .din14_WIDTH( 8 ), + .din15_WIDTH( 8 ), + .din16_WIDTH( 8 ), + .din17_WIDTH( 8 ), + .din18_WIDTH( 8 ), + .din19_WIDTH( 8 ), + .din20_WIDTH( 8 ), + .din21_WIDTH( 8 ), + .din22_WIDTH( 8 ), + .din23_WIDTH( 8 ), + .din24_WIDTH( 8 ), + .din25_WIDTH( 8 ), + .din26_WIDTH( 8 ), + .din27_WIDTH( 8 ), + .din28_WIDTH( 32 ), + .dout_WIDTH( 8 )) +myproject_mux_2832_8_1_1_U159( + .din0(mult_0_V_q0), + .din1(mult_1_V_q0), + .din2(mult_2_V_q0), + .din3(mult_3_V_q0), + .din4(mult_4_V_q0), + .din5(mult_5_V_q0), + .din6(mult_6_V_q0), + .din7(mult_7_V_q0), + .din8(mult_8_V_q0), + .din9(mult_9_V_q0), + .din10(mult_10_V_q0), + .din11(mult_11_V_q0), + .din12(mult_12_V_q0), + .din13(mult_13_V_q0), + .din14(mult_14_V_q0), + .din15(mult_15_V_q0), + .din16(mult_16_V_q0), + .din17(mult_17_V_q0), + .din18(mult_18_V_q0), + .din19(mult_19_V_q0), + .din20(mult_20_V_q0), + .din21(mult_21_V_q0), + .din22(mult_22_V_q0), + .din23(mult_23_V_q0), + .din24(mult_24_V_q0), + .din25(mult_25_V_q0), + .din26(mult_26_V_q0), + .din27(mult_27_V_q0), + .din28(grp_fu_89801_p2), + .dout(tmp_234_fu_89863_p30) +); + +myproject_mul_mul_5ns_13ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 5 ), + .din1_WIDTH( 13 ), + .dout_WIDTH( 17 )) +myproject_mul_mul_5ns_13ns_17_1_1_U160( + .din0(mul_ln201_fu_89951_p0), + .din1(mul_ln201_fu_89951_p1), + .dout(mul_ln201_fu_89951_p2) +); + +myproject_mul_mul_5ns_13ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 5 ), + .din1_WIDTH( 13 ), + .dout_WIDTH( 17 )) +myproject_mul_mul_5ns_13ns_17_1_1_U161( + .din0(mul_ln201_1_fu_89957_p0), + .din1(mul_ln201_1_fu_89957_p1), + .dout(mul_ln201_1_fu_89957_p2) +); + +myproject_mul_mul_13ns_5ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 13 ), + .din1_WIDTH( 5 ), + .dout_WIDTH( 17 )) +myproject_mul_mul_13ns_5ns_17_1_1_U162( + .din0(mul_ln279_fu_89963_p0), + .din1(mul_ln279_fu_89963_p1), + .dout(mul_ln279_fu_89963_p2) +); + +myproject_mac_muladd_8ns_5ns_17ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 5 ), + .din2_WIDTH( 17 ), + .dout_WIDTH( 17 )) +myproject_mac_muladd_8ns_5ns_17ns_17_1_1_U163( + .din0(grp_fu_89969_p0), + .din1(grp_fu_89969_p1), + .din2(mul_ln279_reg_93205), + .dout(grp_fu_89969_p3) +); + +myproject_mul_mul_13ns_5ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 13 ), + .din1_WIDTH( 5 ), + .dout_WIDTH( 17 )) +myproject_mul_mul_13ns_5ns_17_1_1_U164( + .din0(mul_ln279_1_fu_89976_p0), + .din1(mul_ln279_1_fu_89976_p1), + .dout(mul_ln279_1_fu_89976_p2) +); + +myproject_mac_muladd_3ns_6ns_17ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 3 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 17 ), + .dout_WIDTH( 17 )) +myproject_mac_muladd_3ns_6ns_17ns_17_1_1_U165( + .din0(grp_fu_89982_p0), + .din1(grp_fu_89982_p1), + .din2(add_ln276_reg_94070), + .dout(grp_fu_89982_p3) +); + +myproject_mac_muladd_8ns_5ns_17ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 5 ), + .din2_WIDTH( 17 ), + .dout_WIDTH( 17 )) +myproject_mac_muladd_8ns_5ns_17ns_17_1_1_U166( + .din0(grp_fu_89990_p0), + .din1(grp_fu_89990_p1), + .din2(mul_ln279_reg_93205), + .dout(grp_fu_89990_p3) +); + +myproject_mac_muladd_6ns_2ns_17ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 2 ), + .din2_WIDTH( 17 ), + .dout_WIDTH( 17 )) +myproject_mac_muladd_6ns_2ns_17ns_17_1_1_U167( + .din0(grp_fu_89997_p0), + .din1(grp_fu_89997_p1), + .din2(add_ln276_reg_94070), + .dout(grp_fu_89997_p3) +); + +myproject_mac_muladd_3ns_6ns_17ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 3 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 17 ), + .dout_WIDTH( 17 )) +myproject_mac_muladd_3ns_6ns_17ns_17_1_1_U168( + .din0(grp_fu_90005_p0), + .din1(grp_fu_90005_p1), + .din2(add_ln276_2_reg_94294), + .dout(grp_fu_90005_p3) +); + +myproject_mac_muladd_6ns_2ns_17ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 2 ), + .din2_WIDTH( 17 ), + .dout_WIDTH( 17 )) +myproject_mac_muladd_6ns_2ns_17ns_17_1_1_U169( + .din0(grp_fu_90013_p0), + .din1(grp_fu_90013_p1), + .din2(add_ln276_2_reg_94294), + .dout(grp_fu_90013_p3) +); + +myproject_mac_muladd_8ns_5ns_17ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 5 ), + .din2_WIDTH( 17 ), + .dout_WIDTH( 17 )) +myproject_mac_muladd_8ns_5ns_17ns_17_1_1_U170( + .din0(grp_fu_90021_p0), + .din1(grp_fu_90021_p1), + .din2(mul_ln279_1_reg_94247), + .dout(grp_fu_90021_p3) +); + +myproject_mac_muladd_3ns_6ns_17ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 3 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 17 ), + .dout_WIDTH( 17 )) +myproject_mac_muladd_3ns_6ns_17ns_17_1_1_U171( + .din0(grp_fu_90028_p0), + .din1(grp_fu_90028_p1), + .din2(add_ln276_1_reg_98131), + .dout(grp_fu_90028_p3) +); + +myproject_mac_muladd_8ns_5ns_17ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 5 ), + .din2_WIDTH( 17 ), + .dout_WIDTH( 17 )) +myproject_mac_muladd_8ns_5ns_17ns_17_1_1_U172( + .din0(grp_fu_90036_p0), + .din1(grp_fu_90036_p1), + .din2(mul_ln279_1_reg_94247), + .dout(grp_fu_90036_p3) +); + +myproject_mac_muladd_6ns_2ns_17ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 2 ), + .din2_WIDTH( 17 ), + .dout_WIDTH( 17 )) +myproject_mac_muladd_6ns_2ns_17ns_17_1_1_U173( + .din0(grp_fu_90043_p0), + .din1(grp_fu_90043_p1), + .din2(add_ln276_1_reg_98131), + .dout(grp_fu_90043_p3) +); + +myproject_mac_muladd_3ns_6ns_17ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 3 ), + .din1_WIDTH( 6 ), + .din2_WIDTH( 17 ), + .dout_WIDTH( 17 )) +myproject_mac_muladd_3ns_6ns_17ns_17_1_1_U174( + .din0(grp_fu_90051_p0), + .din1(grp_fu_90051_p1), + .din2(add_ln276_6_reg_98358), + .dout(grp_fu_90051_p3) +); + +myproject_mac_muladd_6ns_2ns_17ns_17_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 6 ), + .din1_WIDTH( 2 ), + .din2_WIDTH( 17 ), + .dout_WIDTH( 17 )) +myproject_mac_muladd_6ns_2ns_17ns_17_1_1_U175( + .din0(grp_fu_90059_p0), + .din1(grp_fu_90059_p1), + .din2(add_ln276_6_reg_98358), + .dout(grp_fu_90059_p3) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1170 == ap_CS_fsm)) begin + ff4_0_0_0_0_reg_72935 <= add_ln248_fu_80943_p2; + end else if (((icmp_ln246_fu_80657_p2 == 1'd0) & (ap_ST_fsm_state1166 == ap_CS_fsm))) begin + ff4_0_0_0_0_reg_72935 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1174 == ap_CS_fsm)) begin + ff4_0_0_1_0_reg_72947 <= add_ln248_2_fu_81057_p2; + end else if (((icmp_ln248_fu_80819_p2 == 1'd1) & (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + ff4_0_0_1_0_reg_72947 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1179 == ap_CS_fsm)) begin + ff4_0_1_0_0_reg_72971 <= add_ln248_1_fu_81319_p2; + end else if (((icmp_ln246_1_fu_81063_p2 == 1'd0) & (ap_ST_fsm_state1175 == ap_CS_fsm))) begin + ff4_0_1_0_0_reg_72971 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1183 == ap_CS_fsm)) begin + ff4_0_1_1_0_reg_72983 <= add_ln248_3_fu_81433_p2; + end else if (((icmp_ln248_1_fu_81191_p2 == 1'd1) & (ap_ST_fsm_state1176 == ap_CS_fsm))) begin + ff4_0_1_1_0_reg_72983 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_4_fu_82904_p2 == 1'd1) & (icmp_ln268_5_fu_82881_p2 == 1'd1) & (ap_ST_fsm_state1376 == ap_CS_fsm))) begin + ff7_0_0_0_0_reg_73019 <= add_ln261_fu_82927_p2; + end else if (((icmp_ln259_fu_81487_p2 == 1'd0) & (ap_ST_fsm_state1185 == ap_CS_fsm))) begin + ff7_0_0_0_0_reg_73019 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_6_fu_84994_p2 == 1'd1) & (icmp_ln268_9_fu_84971_p2 == 1'd1) & (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + ff7_0_0_1_0_reg_73103 <= add_ln261_2_fu_85017_p2; + end else if (((icmp_ln261_fu_81657_p2 == 1'd1) & (ap_ST_fsm_state1186 == ap_CS_fsm))) begin + ff7_0_0_1_0_reg_73103 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_5_fu_87251_p2 == 1'd1) & (icmp_ln268_8_fu_87228_p2 == 1'd1) & (ap_ST_fsm_state1977 == ap_CS_fsm))) begin + ff7_0_1_0_0_reg_73199 <= add_ln261_1_fu_87274_p2; + end else if (((icmp_ln259_1_fu_85608_p2 == 1'd0) & (ap_ST_fsm_state1787 == ap_CS_fsm))) begin + ff7_0_1_0_0_reg_73199 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_7_fu_89341_p2 == 1'd1) & (icmp_ln268_11_fu_89318_p2 == 1'd1) & (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + ff7_0_1_1_0_reg_73283 <= add_ln261_3_fu_89364_p2; + end else if (((icmp_ln261_1_fu_85740_p2 == 1'd1) & (ap_ST_fsm_state1788 == ap_CS_fsm))) begin + ff7_0_1_1_0_reg_73283 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state43 == ap_CS_fsm) & (icmp_ln206_fu_74326_p2 == 1'd1) & (icmp_ln208_fu_74233_p2 == 1'd1))) begin + ff_0_0_0_reg_72663 <= add_ln203_reg_90153; + end else if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln201_fu_73698_p2 == 1'd0))) begin + ff_0_0_0_reg_72663 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state333 == ap_CS_fsm) & (icmp_ln206_2_fu_76016_p2 == 1'd1) & (icmp_ln208_2_fu_75923_p2 == 1'd1))) begin + ff_0_0_1_reg_72722 <= add_ln203_5_reg_90633; + end else if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln203_fu_73758_p2 == 1'd1))) begin + ff_0_0_1_reg_72722 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state624 == ap_CS_fsm) & (icmp_ln206_1_fu_77787_p2 == 1'd1) & (icmp_ln208_1_fu_77694_p2 == 1'd1))) begin + ff_0_1_0_reg_72793 <= add_ln203_4_reg_91138; + end else if (((ap_ST_fsm_state584 == ap_CS_fsm) & (icmp_ln201_1_fu_77164_p2 == 1'd0))) begin + ff_0_1_0_reg_72793 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state914 == ap_CS_fsm) & (icmp_ln206_3_fu_79499_p2 == 1'd1) & (icmp_ln208_3_fu_79386_p2 == 1'd1))) begin + ff_0_1_1_reg_72852 <= add_ln203_6_reg_91626; + end else if (((ap_ST_fsm_state585 == ap_CS_fsm) & (icmp_ln203_1_fu_77216_p2 == 1'd1))) begin + ff_0_1_1_reg_72852 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_4_fu_82403_p2 == 1'd1) & (ap_ST_fsm_state1300 == ap_CS_fsm))) begin + fh9_0_0_0_0_0_0_reg_73031 <= add_ln266_fu_82420_p2; + end else if (((icmp_ln261_fu_81657_p2 == 1'd0) & (ap_ST_fsm_state1186 == ap_CS_fsm))) begin + fh9_0_0_0_0_0_0_reg_73031 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_12_fu_83355_p2 == 1'd1) & (ap_ST_fsm_state1450 == ap_CS_fsm))) begin + fh9_0_0_0_0_1_0_reg_73067 <= add_ln266_4_fu_83372_p2; + end else if (((icmp_ln266_fu_82020_p2 == 1'd1) & (icmp_ln268_fu_81997_p2 == 1'd1) & (ap_ST_fsm_state1225 == ap_CS_fsm))) begin + fh9_0_0_0_0_1_0_reg_73067 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_7_fu_84494_p2 == 1'd1) & (ap_ST_fsm_state1601 == ap_CS_fsm))) begin + fh9_0_0_0_1_0_0_reg_73115 <= add_ln266_2_fu_84511_p2; + end else if (((icmp_ln261_2_fu_83525_p2 == 1'd0) & (ap_ST_fsm_state1487 == ap_CS_fsm))) begin + fh9_0_0_0_1_0_0_reg_73115 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_14_fu_85443_p2 == 1'd1) & (ap_ST_fsm_state1750 == ap_CS_fsm))) begin + fh9_0_0_0_1_1_0_reg_73151 <= add_ln266_6_fu_85460_p2; + end else if (((icmp_ln266_2_fu_83979_p2 == 1'd1) & (icmp_ln268_2_fu_83956_p2 == 1'd1) & (ap_ST_fsm_state1526 == ap_CS_fsm))) begin + fh9_0_0_0_1_1_0_reg_73151 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_6_fu_86750_p2 == 1'd1) & (ap_ST_fsm_state1902 == ap_CS_fsm))) begin + fh9_0_0_1_0_0_0_reg_73211 <= add_ln266_1_fu_86767_p2; + end else if (((icmp_ln261_1_fu_85740_p2 == 1'd0) & (ap_ST_fsm_state1788 == ap_CS_fsm))) begin + fh9_0_0_1_0_0_0_reg_73211 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_13_fu_87702_p2 == 1'd1) & (ap_ST_fsm_state2051 == ap_CS_fsm))) begin + fh9_0_0_1_0_1_0_reg_73247 <= add_ln266_5_fu_87719_p2; + end else if (((icmp_ln266_1_fu_86235_p2 == 1'd1) & (icmp_ln268_1_fu_86212_p2 == 1'd1) & (ap_ST_fsm_state1827 == ap_CS_fsm))) begin + fh9_0_0_1_0_1_0_reg_73247 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_10_fu_88841_p2 == 1'd1) & (ap_ST_fsm_state2201 == ap_CS_fsm))) begin + fh9_0_0_1_1_0_0_reg_73295 <= add_ln266_3_fu_88858_p2; + end else if (((icmp_ln261_3_fu_87872_p2 == 1'd0) & (ap_ST_fsm_state2088 == ap_CS_fsm))) begin + fh9_0_0_1_1_0_0_reg_73295 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_15_fu_89790_p2 == 1'd1) & (ap_ST_fsm_state2350 == ap_CS_fsm))) begin + fh9_0_0_1_1_1_0_reg_73331 <= add_ln266_7_fu_89807_p2; + end else if (((icmp_ln266_3_fu_88326_p2 == 1'd1) & (icmp_ln268_3_fu_88303_p2 == 1'd1) & (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + fh9_0_0_1_1_1_0_reg_73331 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_4_fu_75057_p2 == 1'd1) & (ap_ST_fsm_state187 == ap_CS_fsm))) begin + fh_0_0_0_0_0_reg_72686 <= add_ln206_fu_75164_p2; + end else if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln203_fu_73758_p2 == 1'd0))) begin + fh_0_0_0_0_0_reg_72686 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state477 == ap_CS_fsm) & (icmp_ln208_6_fu_76737_p2 == 1'd1))) begin + fh_0_0_0_1_0_reg_72745 <= add_ln206_2_fu_76844_p2; + end else if (((icmp_ln203_2_fu_75486_p2 == 1'd0) & (ap_ST_fsm_state294 == ap_CS_fsm))) begin + fh_0_0_0_1_0_reg_72745 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state768 == ap_CS_fsm) & (icmp_ln208_5_fu_78517_p2 == 1'd1))) begin + fh_0_0_1_0_0_reg_72816 <= add_ln206_1_fu_78624_p2; + end else if (((ap_ST_fsm_state585 == ap_CS_fsm) & (icmp_ln203_1_fu_77216_p2 == 1'd0))) begin + fh_0_0_1_0_0_reg_72816 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_7_fu_80198_p2 == 1'd1) & (ap_ST_fsm_state1058 == ap_CS_fsm))) begin + fh_0_0_1_1_0_reg_72875 <= add_ln206_3_fu_80305_p2; + end else if (((ap_ST_fsm_state875 == ap_CS_fsm) & (icmp_ln203_3_fu_78946_p2 == 1'd0))) begin + fh_0_0_1_1_0_reg_72875 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1262 == ap_CS_fsm)) begin + fw10_0_0_0_0_0_0_0_reg_73043 <= add_ln268_fu_82230_p2; + end else if ((ap_ST_fsm_state1187 == ap_CS_fsm)) begin + fw10_0_0_0_0_0_0_0_reg_73043 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1337 == ap_CS_fsm)) begin + fw10_0_0_0_0_0_1_0_reg_73055 <= add_ln268_4_fu_82575_p2; + end else if (((icmp_ln268_fu_81997_p2 == 1'd1) & (icmp_ln266_fu_82020_p2 == 1'd0) & (ap_ST_fsm_state1225 == ap_CS_fsm))) begin + fw10_0_0_0_0_0_1_0_reg_73055 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1413 == ap_CS_fsm)) begin + fw10_0_0_0_0_1_0_0_reg_73079 <= add_ln268_5_fu_83066_p2; + end else if ((ap_ST_fsm_state1338 == ap_CS_fsm)) begin + fw10_0_0_0_0_1_0_0_reg_73079 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + fw10_0_0_0_0_1_1_0_reg_73091 <= add_ln268_12_fu_83511_p2; + end else if (((icmp_ln268_5_fu_82881_p2 == 1'd1) & (icmp_ln266_4_fu_82904_p2 == 1'd0) & (ap_ST_fsm_state1376 == ap_CS_fsm))) begin + fw10_0_0_0_0_1_1_0_reg_73091 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1563 == ap_CS_fsm)) begin + fw10_0_0_0_1_0_0_0_reg_73127 <= add_ln268_2_fu_84189_p2; + end else if ((ap_ST_fsm_state1488 == ap_CS_fsm)) begin + fw10_0_0_0_1_0_0_0_reg_73127 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1638 == ap_CS_fsm)) begin + fw10_0_0_0_1_0_1_0_reg_73139 <= add_ln268_7_fu_84666_p2; + end else if (((icmp_ln268_2_fu_83956_p2 == 1'd1) & (icmp_ln266_2_fu_83979_p2 == 1'd0) & (ap_ST_fsm_state1526 == ap_CS_fsm))) begin + fw10_0_0_0_1_0_1_0_reg_73139 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1713 == ap_CS_fsm)) begin + fw10_0_0_0_1_1_0_0_reg_73163 <= add_ln268_9_fu_85155_p2; + end else if ((ap_ST_fsm_state1639 == ap_CS_fsm)) begin + fw10_0_0_0_1_1_0_0_reg_73163 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + fw10_0_0_0_1_1_1_0_reg_73175 <= add_ln268_14_fu_85598_p2; + end else if (((icmp_ln268_9_fu_84971_p2 == 1'd1) & (icmp_ln266_6_fu_84994_p2 == 1'd0) & (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + fw10_0_0_0_1_1_1_0_reg_73175 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1864 == ap_CS_fsm)) begin + fw10_0_0_1_0_0_0_0_reg_73223 <= add_ln268_1_fu_86445_p2; + end else if ((ap_ST_fsm_state1789 == ap_CS_fsm)) begin + fw10_0_0_1_0_0_0_0_reg_73223 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1939 == ap_CS_fsm)) begin + fw10_0_0_1_0_0_1_0_reg_73235 <= add_ln268_6_fu_86922_p2; + end else if (((icmp_ln268_1_fu_86212_p2 == 1'd1) & (icmp_ln266_1_fu_86235_p2 == 1'd0) & (ap_ST_fsm_state1827 == ap_CS_fsm))) begin + fw10_0_0_1_0_0_1_0_reg_73235 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2014 == ap_CS_fsm)) begin + fw10_0_0_1_0_1_0_0_reg_73259 <= add_ln268_8_fu_87413_p2; + end else if ((ap_ST_fsm_state1940 == ap_CS_fsm)) begin + fw10_0_0_1_0_1_0_0_reg_73259 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + fw10_0_0_1_0_1_1_0_reg_73271 <= add_ln268_13_fu_87858_p2; + end else if (((icmp_ln268_8_fu_87228_p2 == 1'd1) & (icmp_ln266_5_fu_87251_p2 == 1'd0) & (ap_ST_fsm_state1977 == ap_CS_fsm))) begin + fw10_0_0_1_0_1_1_0_reg_73271 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2163 == ap_CS_fsm)) begin + fw10_0_0_1_1_0_0_0_reg_73307 <= add_ln268_3_fu_88536_p2; + end else if ((ap_ST_fsm_state2089 == ap_CS_fsm)) begin + fw10_0_0_1_1_0_0_0_reg_73307 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2238 == ap_CS_fsm)) begin + fw10_0_0_1_1_0_1_0_reg_73319 <= add_ln268_10_fu_89013_p2; + end else if (((icmp_ln268_3_fu_88303_p2 == 1'd1) & (icmp_ln266_3_fu_88326_p2 == 1'd0) & (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + fw10_0_0_1_1_0_1_0_reg_73319 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2313 == ap_CS_fsm)) begin + fw10_0_0_1_1_1_0_0_reg_73343 <= add_ln268_11_fu_89502_p2; + end else if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + fw10_0_0_1_1_1_0_0_reg_73343 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + fw10_0_0_1_1_1_1_0_reg_73355 <= add_ln268_15_fu_89945_p2; + end else if (((icmp_ln268_11_fu_89318_p2 == 1'd1) & (icmp_ln266_7_fu_89341_p2 == 1'd0) & (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + fw10_0_0_1_1_1_1_0_reg_73355 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state114 == ap_CS_fsm)) begin + fw_0_0_0_0_0_0_reg_72698 <= add_ln208_fu_74693_p2; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + fw_0_0_0_0_0_0_reg_72698 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state258 == ap_CS_fsm)) begin + fw_0_0_0_0_1_0_reg_72710 <= add_ln208_4_fu_75416_p2; + end else if ((ap_ST_fsm_state150 == ap_CS_fsm)) begin + fw_0_0_0_0_1_0_reg_72710 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state404 == ap_CS_fsm)) begin + fw_0_0_0_1_0_0_reg_72757 <= add_ln208_2_fu_76383_p2; + end else if ((ap_ST_fsm_state296 == ap_CS_fsm)) begin + fw_0_0_0_1_0_0_reg_72757 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state548 == ap_CS_fsm)) begin + fw_0_0_0_1_1_0_reg_72769 <= add_ln208_6_fu_77096_p2; + end else if ((ap_ST_fsm_state440 == ap_CS_fsm)) begin + fw_0_0_0_1_1_0_reg_72769 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state695 == ap_CS_fsm)) begin + fw_0_0_1_0_0_0_reg_72828 <= add_ln208_1_fu_78153_p2; + end else if ((ap_ST_fsm_state587 == ap_CS_fsm)) begin + fw_0_0_1_0_0_0_reg_72828 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state839 == ap_CS_fsm)) begin + fw_0_0_1_0_1_0_reg_72840 <= add_ln208_5_fu_78876_p2; + end else if ((ap_ST_fsm_state731 == ap_CS_fsm)) begin + fw_0_0_1_0_1_0_reg_72840 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state985 == ap_CS_fsm)) begin + fw_0_0_1_1_0_0_reg_72887 <= add_ln208_3_fu_79844_p2; + end else if ((ap_ST_fsm_state877 == ap_CS_fsm)) begin + fw_0_0_1_1_0_0_reg_72887 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1129 == ap_CS_fsm)) begin + fw_0_0_1_1_1_0_reg_72899 <= add_ln208_7_fu_80557_p2; + end else if ((ap_ST_fsm_state1021 == ap_CS_fsm)) begin + fw_0_0_1_1_1_0_reg_72899 <= 32'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2 == ap_CS_fsm) & (icmp_ln199_fu_73684_p2 == 1'd1))) begin + oh2_0_0_reg_72911 <= 5'd0; + end else if (((icmp_ln246_1_fu_81063_p2 == 1'd1) & (ap_ST_fsm_state1175 == ap_CS_fsm))) begin + oh2_0_0_reg_72911 <= add_ln244_fu_81185_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln244_fu_80617_p2 == 1'd1) & (ap_ST_fsm_state1165 == ap_CS_fsm))) begin + oh5_0_0_reg_72995 <= 5'd0; + end else if (((icmp_ln259_1_fu_85608_p2 == 1'd1) & (ap_ST_fsm_state1787 == ap_CS_fsm))) begin + oh5_0_0_reg_72995 <= add_ln257_fu_85730_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state584 == ap_CS_fsm) & (icmp_ln201_1_fu_77164_p2 == 1'd1))) begin + oh_0_0_reg_72639 <= add_ln199_fu_77200_p2; + end else if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b1))) begin + oh_0_0_reg_72639 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln248_2_fu_80953_p2 == 1'd1) & (ap_ST_fsm_state1171 == ap_CS_fsm))) begin + ow3_0_0_0_reg_72923 <= add_ln246_fu_81024_p2; + end else if (((icmp_ln244_fu_80617_p2 == 1'd0) & (ap_ST_fsm_state1165 == ap_CS_fsm))) begin + ow3_0_0_0_reg_72923 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln248_3_fu_81329_p2 == 1'd1) & (ap_ST_fsm_state1180 == ap_CS_fsm))) begin + ow3_0_1_0_reg_72959 <= add_ln246_1_fu_81400_p2; + end else if (((icmp_ln246_fu_80657_p2 == 1'd1) & (ap_ST_fsm_state1166 == ap_CS_fsm))) begin + ow3_0_1_0_reg_72959 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln261_2_fu_83525_p2 == 1'd1) & (ap_ST_fsm_state1487 == ap_CS_fsm))) begin + ow6_0_0_0_reg_73007 <= add_ln259_fu_83634_p2; + end else if (((icmp_ln257_fu_81443_p2 == 1'd0) & (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + ow6_0_0_0_reg_73007 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln261_3_fu_87872_p2 == 1'd1) & (ap_ST_fsm_state2088 == ap_CS_fsm))) begin + ow6_0_1_0_reg_73187 <= add_ln259_1_fu_87981_p2; + end else if (((icmp_ln259_fu_81487_p2 == 1'd1) & (ap_ST_fsm_state1185 == ap_CS_fsm))) begin + ow6_0_1_0_reg_73187 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln203_2_fu_75486_p2 == 1'd1) & (ap_ST_fsm_state294 == ap_CS_fsm))) begin + ow_0_0_0_reg_72651 <= add_ln201_fu_75520_p2; + end else if (((ap_ST_fsm_state2 == ap_CS_fsm) & (icmp_ln199_fu_73684_p2 == 1'd0))) begin + ow_0_0_0_reg_72651 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state875 == ap_CS_fsm) & (icmp_ln203_3_fu_78946_p2 == 1'd1))) begin + ow_0_1_0_reg_72781 <= add_ln201_1_fu_78980_p2; + end else if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln201_fu_73698_p2 == 1'd1))) begin + ow_0_1_0_reg_72781 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state333 == ap_CS_fsm) & (icmp_ln206_2_fu_76016_p2 == 1'd1) & (icmp_ln208_2_fu_75923_p2 == 1'd1))) begin + phi_mul104991_reg_72734 <= add_ln203_10_reg_90620; + end else if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln203_fu_73758_p2 == 1'd1))) begin + phi_mul104991_reg_72734 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state624 == ap_CS_fsm) & (icmp_ln206_1_fu_77787_p2 == 1'd1) & (icmp_ln208_1_fu_77694_p2 == 1'd1))) begin + phi_mul105001_reg_72805 <= add_ln203_9_reg_91125; + end else if (((ap_ST_fsm_state584 == ap_CS_fsm) & (icmp_ln201_1_fu_77164_p2 == 1'd0))) begin + phi_mul105001_reg_72805 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state914 == ap_CS_fsm) & (icmp_ln206_3_fu_79499_p2 == 1'd1) & (icmp_ln208_3_fu_79386_p2 == 1'd1))) begin + phi_mul105011_reg_72864 <= add_ln203_11_reg_91613; + end else if (((ap_ST_fsm_state585 == ap_CS_fsm) & (icmp_ln203_1_fu_77216_p2 == 1'd1))) begin + phi_mul105011_reg_72864 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state43 == ap_CS_fsm) & (icmp_ln206_fu_74326_p2 == 1'd1) & (icmp_ln208_fu_74233_p2 == 1'd1))) begin + phi_mul_reg_72675 <= add_ln203_8_reg_90140; + end else if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln201_fu_73698_p2 == 1'd0))) begin + phi_mul_reg_72675 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln246_fu_80657_p2 == 1'd0) & (ap_ST_fsm_state1166 == ap_CS_fsm))) begin + acc_0_V_addr_49_reg_92118 <= zext_ln203_3_fu_80711_p1; + acc_10_V_addr_49_reg_92143 <= zext_ln203_3_fu_80711_p1; + acc_11_V_addr_49_reg_92308 <= zext_ln203_3_fu_80711_p1; + acc_12_V_addr_49_reg_92148 <= zext_ln203_3_fu_80711_p1; + acc_13_V_addr_49_reg_92313 <= zext_ln203_3_fu_80711_p1; + acc_14_V_addr_49_reg_92153 <= zext_ln203_3_fu_80711_p1; + acc_15_V_addr_49_reg_92318 <= zext_ln203_3_fu_80711_p1; + acc_16_V_addr_49_reg_92158 <= zext_ln203_3_fu_80711_p1; + acc_17_V_addr_49_reg_92323 <= zext_ln203_3_fu_80711_p1; + acc_18_V_addr_49_reg_92163 <= zext_ln203_3_fu_80711_p1; + acc_19_V_addr_49_reg_92328 <= zext_ln203_3_fu_80711_p1; + acc_1_V_addr_49_reg_92283 <= zext_ln203_3_fu_80711_p1; + acc_20_V_addr_49_reg_92168 <= zext_ln203_3_fu_80711_p1; + acc_21_V_addr_49_reg_92333 <= zext_ln203_3_fu_80711_p1; + acc_22_V_addr_49_reg_92173 <= zext_ln203_3_fu_80711_p1; + acc_23_V_addr_49_reg_92338 <= zext_ln203_3_fu_80711_p1; + acc_24_V_addr_49_reg_92178 <= zext_ln203_3_fu_80711_p1; + acc_25_V_addr_49_reg_92343 <= zext_ln203_3_fu_80711_p1; + acc_26_V_addr_49_reg_92183 <= zext_ln203_3_fu_80711_p1; + acc_27_V_addr_49_reg_92348 <= zext_ln203_3_fu_80711_p1; + acc_28_V_addr_49_reg_92188 <= zext_ln203_3_fu_80711_p1; + acc_29_V_addr_49_reg_92353 <= zext_ln203_3_fu_80711_p1; + acc_2_V_addr_49_reg_92123 <= zext_ln203_3_fu_80711_p1; + acc_30_V_addr_49_reg_92193 <= zext_ln203_3_fu_80711_p1; + acc_31_V_addr_49_reg_92358 <= zext_ln203_3_fu_80711_p1; + acc_32_V_addr_49_reg_92198 <= zext_ln203_3_fu_80711_p1; + acc_33_V_addr_49_reg_92363 <= zext_ln203_3_fu_80711_p1; + acc_34_V_addr_49_reg_92203 <= zext_ln203_3_fu_80711_p1; + acc_35_V_addr_49_reg_92368 <= zext_ln203_3_fu_80711_p1; + acc_36_V_addr_49_reg_92208 <= zext_ln203_3_fu_80711_p1; + acc_37_V_addr_49_reg_92373 <= zext_ln203_3_fu_80711_p1; + acc_38_V_addr_49_reg_92213 <= zext_ln203_3_fu_80711_p1; + acc_39_V_addr_49_reg_92378 <= zext_ln203_3_fu_80711_p1; + acc_3_V_addr_49_reg_92288 <= zext_ln203_3_fu_80711_p1; + acc_40_V_addr_49_reg_92218 <= zext_ln203_3_fu_80711_p1; + acc_41_V_addr_49_reg_92383 <= zext_ln203_3_fu_80711_p1; + acc_42_V_addr_49_reg_92223 <= zext_ln203_3_fu_80711_p1; + acc_43_V_addr_49_reg_92388 <= zext_ln203_3_fu_80711_p1; + acc_44_V_addr_49_reg_92228 <= zext_ln203_3_fu_80711_p1; + acc_45_V_addr_49_reg_92393 <= zext_ln203_3_fu_80711_p1; + acc_46_V_addr_49_reg_92233 <= zext_ln203_3_fu_80711_p1; + acc_47_V_addr_49_reg_92398 <= zext_ln203_3_fu_80711_p1; + acc_48_V_addr_49_reg_92238 <= zext_ln203_3_fu_80711_p1; + acc_49_V_addr_49_reg_92403 <= zext_ln203_3_fu_80711_p1; + acc_4_V_addr_49_reg_92128 <= zext_ln203_3_fu_80711_p1; + acc_50_V_addr_49_reg_92243 <= zext_ln203_3_fu_80711_p1; + acc_51_V_addr_49_reg_92408 <= zext_ln203_3_fu_80711_p1; + acc_52_V_addr_49_reg_92248 <= zext_ln203_3_fu_80711_p1; + acc_53_V_addr_49_reg_92413 <= zext_ln203_3_fu_80711_p1; + acc_54_V_addr_49_reg_92253 <= zext_ln203_3_fu_80711_p1; + acc_55_V_addr_49_reg_92418 <= zext_ln203_3_fu_80711_p1; + acc_56_V_addr_49_reg_92258 <= zext_ln203_3_fu_80711_p1; + acc_57_V_addr_49_reg_92423 <= zext_ln203_3_fu_80711_p1; + acc_58_V_addr_49_reg_92263 <= zext_ln203_3_fu_80711_p1; + acc_59_V_addr_49_reg_92428 <= zext_ln203_3_fu_80711_p1; + acc_5_V_addr_49_reg_92293 <= zext_ln203_3_fu_80711_p1; + acc_60_V_addr_49_reg_92268 <= zext_ln203_3_fu_80711_p1; + acc_61_V_addr_49_reg_92433 <= zext_ln203_3_fu_80711_p1; + acc_62_V_addr_49_reg_92273 <= zext_ln203_3_fu_80711_p1; + acc_63_V_addr_49_reg_92278 <= zext_ln203_3_fu_80711_p1; + acc_6_V_addr_49_reg_92133 <= zext_ln203_3_fu_80711_p1; + acc_7_V_addr_49_reg_92298 <= zext_ln203_3_fu_80711_p1; + acc_8_V_addr_49_reg_92138 <= zext_ln203_3_fu_80711_p1; + acc_9_V_addr_49_reg_92303 <= zext_ln203_3_fu_80711_p1; + add_ln250_1_reg_92112[5 : 2] <= add_ln250_1_fu_80692_p2[5 : 2]; + shl_ln250_1_reg_92102[6 : 2] <= shl_ln250_1_fu_80663_p3[6 : 2]; + trunc_ln250_8_reg_92107[5 : 2] <= trunc_ln250_8_fu_80679_p3[5 : 2]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln259_fu_81487_p2 == 1'd0) & (ap_ST_fsm_state1185 == ap_CS_fsm))) begin + acc_0_V_addr_50_reg_93872 <= zext_ln1265_1_fu_81541_p1; + acc_10_V_addr_50_reg_93902 <= zext_ln1265_1_fu_81541_p1; + acc_11_V_addr_50_reg_94094 <= zext_ln1265_1_fu_81541_p1; + acc_12_V_addr_50_reg_93908 <= zext_ln1265_1_fu_81541_p1; + acc_13_V_addr_50_reg_94232 <= zext_ln1265_1_fu_81541_p1; + acc_14_V_addr_50_reg_93914 <= zext_ln1265_1_fu_81541_p1; + acc_15_V_addr_50_reg_94227 <= zext_ln1265_1_fu_81541_p1; + acc_16_V_addr_50_reg_93920 <= zext_ln1265_1_fu_81541_p1; + acc_17_V_addr_50_reg_94100 <= zext_ln1265_1_fu_81541_p1; + acc_18_V_addr_50_reg_93926 <= zext_ln1265_1_fu_81541_p1; + acc_19_V_addr_50_reg_94106 <= zext_ln1265_1_fu_81541_p1; + acc_1_V_addr_50_reg_94076 <= zext_ln1265_1_fu_81541_p1; + acc_20_V_addr_50_reg_93932 <= zext_ln1265_1_fu_81541_p1; + acc_21_V_addr_50_reg_94222 <= zext_ln1265_1_fu_81541_p1; + acc_22_V_addr_50_reg_93938 <= zext_ln1265_1_fu_81541_p1; + acc_23_V_addr_50_reg_94217 <= zext_ln1265_1_fu_81541_p1; + acc_24_V_addr_50_reg_93944 <= zext_ln1265_1_fu_81541_p1; + acc_25_V_addr_50_reg_94112 <= zext_ln1265_1_fu_81541_p1; + acc_26_V_addr_50_reg_93950 <= zext_ln1265_1_fu_81541_p1; + acc_27_V_addr_50_reg_94118 <= zext_ln1265_1_fu_81541_p1; + acc_28_V_addr_50_reg_93956 <= zext_ln1265_1_fu_81541_p1; + acc_29_V_addr_50_reg_94212 <= zext_ln1265_1_fu_81541_p1; + acc_2_V_addr_50_reg_93878 <= zext_ln1265_1_fu_81541_p1; + acc_30_V_addr_50_reg_93962 <= zext_ln1265_1_fu_81541_p1; + acc_31_V_addr_50_reg_94207 <= zext_ln1265_1_fu_81541_p1; + acc_32_V_addr_50_reg_93968 <= zext_ln1265_1_fu_81541_p1; + acc_33_V_addr_50_reg_94124 <= zext_ln1265_1_fu_81541_p1; + acc_34_V_addr_50_reg_93974 <= zext_ln1265_1_fu_81541_p1; + acc_35_V_addr_50_reg_94130 <= zext_ln1265_1_fu_81541_p1; + acc_36_V_addr_50_reg_93980 <= zext_ln1265_1_fu_81541_p1; + acc_37_V_addr_50_reg_94202 <= zext_ln1265_1_fu_81541_p1; + acc_38_V_addr_50_reg_93986 <= zext_ln1265_1_fu_81541_p1; + acc_39_V_addr_50_reg_94197 <= zext_ln1265_1_fu_81541_p1; + acc_3_V_addr_50_reg_94082 <= zext_ln1265_1_fu_81541_p1; + acc_40_V_addr_50_reg_93992 <= zext_ln1265_1_fu_81541_p1; + acc_41_V_addr_50_reg_94136 <= zext_ln1265_1_fu_81541_p1; + acc_42_V_addr_50_reg_93998 <= zext_ln1265_1_fu_81541_p1; + acc_43_V_addr_50_reg_94142 <= zext_ln1265_1_fu_81541_p1; + acc_44_V_addr_50_reg_94004 <= zext_ln1265_1_fu_81541_p1; + acc_45_V_addr_50_reg_94192 <= zext_ln1265_1_fu_81541_p1; + acc_46_V_addr_50_reg_94010 <= zext_ln1265_1_fu_81541_p1; + acc_47_V_addr_50_reg_94187 <= zext_ln1265_1_fu_81541_p1; + acc_48_V_addr_50_reg_94016 <= zext_ln1265_1_fu_81541_p1; + acc_49_V_addr_50_reg_94148 <= zext_ln1265_1_fu_81541_p1; + acc_4_V_addr_50_reg_93884 <= zext_ln1265_1_fu_81541_p1; + acc_50_V_addr_50_reg_94022 <= zext_ln1265_1_fu_81541_p1; + acc_51_V_addr_50_reg_94154 <= zext_ln1265_1_fu_81541_p1; + acc_52_V_addr_50_reg_94028 <= zext_ln1265_1_fu_81541_p1; + acc_53_V_addr_50_reg_94182 <= zext_ln1265_1_fu_81541_p1; + acc_54_V_addr_50_reg_94034 <= zext_ln1265_1_fu_81541_p1; + acc_55_V_addr_50_reg_94177 <= zext_ln1265_1_fu_81541_p1; + acc_56_V_addr_50_reg_94040 <= zext_ln1265_1_fu_81541_p1; + acc_57_V_addr_50_reg_94160 <= zext_ln1265_1_fu_81541_p1; + acc_58_V_addr_50_reg_94046 <= zext_ln1265_1_fu_81541_p1; + acc_59_V_addr_50_reg_94166 <= zext_ln1265_1_fu_81541_p1; + acc_5_V_addr_50_reg_94242 <= zext_ln1265_1_fu_81541_p1; + acc_60_V_addr_50_reg_94052 <= zext_ln1265_1_fu_81541_p1; + acc_61_V_addr_50_reg_94172 <= zext_ln1265_1_fu_81541_p1; + acc_62_V_addr_50_reg_94058 <= zext_ln1265_1_fu_81541_p1; + acc_63_V_addr_50_reg_94064 <= zext_ln1265_1_fu_81541_p1; + acc_6_V_addr_50_reg_93890 <= zext_ln1265_1_fu_81541_p1; + acc_7_V_addr_50_reg_94237 <= zext_ln1265_1_fu_81541_p1; + acc_8_V_addr_50_reg_93896 <= zext_ln1265_1_fu_81541_p1; + acc_9_V_addr_50_reg_94088 <= zext_ln1265_1_fu_81541_p1; + add_ln276_reg_94070 <= grp_fu_89969_p3; + add_ln279_1_reg_93866[5 : 2] <= add_ln279_1_fu_81522_p2[5 : 2]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln246_1_fu_81063_p2 == 1'd0) & (ap_ST_fsm_state1175 == ap_CS_fsm))) begin + acc_0_V_addr_51_reg_92673 <= zext_ln203_6_fu_81117_p1; + acc_10_V_addr_51_reg_92698 <= zext_ln203_6_fu_81117_p1; + acc_11_V_addr_51_reg_92863 <= zext_ln203_6_fu_81117_p1; + acc_12_V_addr_51_reg_92703 <= zext_ln203_6_fu_81117_p1; + acc_13_V_addr_51_reg_92868 <= zext_ln203_6_fu_81117_p1; + acc_14_V_addr_51_reg_92708 <= zext_ln203_6_fu_81117_p1; + acc_15_V_addr_51_reg_92873 <= zext_ln203_6_fu_81117_p1; + acc_16_V_addr_51_reg_92713 <= zext_ln203_6_fu_81117_p1; + acc_17_V_addr_51_reg_92878 <= zext_ln203_6_fu_81117_p1; + acc_18_V_addr_51_reg_92718 <= zext_ln203_6_fu_81117_p1; + acc_19_V_addr_51_reg_92883 <= zext_ln203_6_fu_81117_p1; + acc_1_V_addr_51_reg_92838 <= zext_ln203_6_fu_81117_p1; + acc_20_V_addr_51_reg_92723 <= zext_ln203_6_fu_81117_p1; + acc_21_V_addr_51_reg_92888 <= zext_ln203_6_fu_81117_p1; + acc_22_V_addr_51_reg_92728 <= zext_ln203_6_fu_81117_p1; + acc_23_V_addr_51_reg_92893 <= zext_ln203_6_fu_81117_p1; + acc_24_V_addr_51_reg_92733 <= zext_ln203_6_fu_81117_p1; + acc_25_V_addr_51_reg_92898 <= zext_ln203_6_fu_81117_p1; + acc_26_V_addr_51_reg_92738 <= zext_ln203_6_fu_81117_p1; + acc_27_V_addr_51_reg_92903 <= zext_ln203_6_fu_81117_p1; + acc_28_V_addr_51_reg_92743 <= zext_ln203_6_fu_81117_p1; + acc_29_V_addr_51_reg_92908 <= zext_ln203_6_fu_81117_p1; + acc_2_V_addr_51_reg_92678 <= zext_ln203_6_fu_81117_p1; + acc_30_V_addr_51_reg_92748 <= zext_ln203_6_fu_81117_p1; + acc_31_V_addr_51_reg_92913 <= zext_ln203_6_fu_81117_p1; + acc_32_V_addr_51_reg_92753 <= zext_ln203_6_fu_81117_p1; + acc_33_V_addr_51_reg_92918 <= zext_ln203_6_fu_81117_p1; + acc_34_V_addr_51_reg_92758 <= zext_ln203_6_fu_81117_p1; + acc_35_V_addr_51_reg_92923 <= zext_ln203_6_fu_81117_p1; + acc_36_V_addr_51_reg_92763 <= zext_ln203_6_fu_81117_p1; + acc_37_V_addr_51_reg_92928 <= zext_ln203_6_fu_81117_p1; + acc_38_V_addr_51_reg_92768 <= zext_ln203_6_fu_81117_p1; + acc_39_V_addr_51_reg_92933 <= zext_ln203_6_fu_81117_p1; + acc_3_V_addr_51_reg_92843 <= zext_ln203_6_fu_81117_p1; + acc_40_V_addr_51_reg_92773 <= zext_ln203_6_fu_81117_p1; + acc_41_V_addr_51_reg_92938 <= zext_ln203_6_fu_81117_p1; + acc_42_V_addr_51_reg_92778 <= zext_ln203_6_fu_81117_p1; + acc_43_V_addr_51_reg_92943 <= zext_ln203_6_fu_81117_p1; + acc_44_V_addr_51_reg_92783 <= zext_ln203_6_fu_81117_p1; + acc_45_V_addr_51_reg_92948 <= zext_ln203_6_fu_81117_p1; + acc_46_V_addr_51_reg_92788 <= zext_ln203_6_fu_81117_p1; + acc_47_V_addr_51_reg_92953 <= zext_ln203_6_fu_81117_p1; + acc_48_V_addr_51_reg_92793 <= zext_ln203_6_fu_81117_p1; + acc_49_V_addr_51_reg_92958 <= zext_ln203_6_fu_81117_p1; + acc_4_V_addr_51_reg_92683 <= zext_ln203_6_fu_81117_p1; + acc_50_V_addr_51_reg_92798 <= zext_ln203_6_fu_81117_p1; + acc_51_V_addr_51_reg_92963 <= zext_ln203_6_fu_81117_p1; + acc_52_V_addr_51_reg_92803 <= zext_ln203_6_fu_81117_p1; + acc_53_V_addr_51_reg_92968 <= zext_ln203_6_fu_81117_p1; + acc_54_V_addr_51_reg_92808 <= zext_ln203_6_fu_81117_p1; + acc_55_V_addr_51_reg_92973 <= zext_ln203_6_fu_81117_p1; + acc_56_V_addr_51_reg_92813 <= zext_ln203_6_fu_81117_p1; + acc_57_V_addr_51_reg_92978 <= zext_ln203_6_fu_81117_p1; + acc_58_V_addr_51_reg_92818 <= zext_ln203_6_fu_81117_p1; + acc_59_V_addr_51_reg_92983 <= zext_ln203_6_fu_81117_p1; + acc_5_V_addr_51_reg_92848 <= zext_ln203_6_fu_81117_p1; + acc_60_V_addr_51_reg_92823 <= zext_ln203_6_fu_81117_p1; + acc_61_V_addr_51_reg_92988 <= zext_ln203_6_fu_81117_p1; + acc_62_V_addr_51_reg_92828 <= zext_ln203_6_fu_81117_p1; + acc_63_V_addr_51_reg_92833 <= zext_ln203_6_fu_81117_p1; + acc_6_V_addr_51_reg_92688 <= zext_ln203_6_fu_81117_p1; + acc_7_V_addr_51_reg_92853 <= zext_ln203_6_fu_81117_p1; + acc_8_V_addr_51_reg_92693 <= zext_ln203_6_fu_81117_p1; + acc_9_V_addr_51_reg_92858 <= zext_ln203_6_fu_81117_p1; + add_ln250_3_reg_92667[5 : 2] <= add_ln250_3_fu_81098_p2[5 : 2]; + shl_ln250_2_reg_92657[6 : 2] <= shl_ln250_2_fu_81069_p3[6 : 2]; + trunc_ln250_9_reg_92662[5 : 2] <= trunc_ln250_9_fu_81085_p3[5 : 2]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln259_1_fu_85608_p2 == 1'd0) & (ap_ST_fsm_state1787 == ap_CS_fsm))) begin + acc_0_V_addr_52_reg_97933 <= zext_ln1265_2_fu_85662_p1; + acc_10_V_addr_52_reg_97963 <= zext_ln1265_2_fu_85662_p1; + acc_11_V_addr_53_reg_98155 <= zext_ln1265_2_fu_85662_p1; + acc_12_V_addr_52_reg_97969 <= zext_ln1265_2_fu_85662_p1; + acc_13_V_addr_53_reg_98305 <= zext_ln1265_2_fu_85662_p1; + acc_14_V_addr_52_reg_97975 <= zext_ln1265_2_fu_85662_p1; + acc_15_V_addr_53_reg_98299 <= zext_ln1265_2_fu_85662_p1; + acc_16_V_addr_52_reg_97981 <= zext_ln1265_2_fu_85662_p1; + acc_17_V_addr_53_reg_98161 <= zext_ln1265_2_fu_85662_p1; + acc_18_V_addr_52_reg_97987 <= zext_ln1265_2_fu_85662_p1; + acc_19_V_addr_53_reg_98167 <= zext_ln1265_2_fu_85662_p1; + acc_1_V_addr_53_reg_98137 <= zext_ln1265_2_fu_85662_p1; + acc_20_V_addr_52_reg_97993 <= zext_ln1265_2_fu_85662_p1; + acc_21_V_addr_53_reg_98293 <= zext_ln1265_2_fu_85662_p1; + acc_22_V_addr_52_reg_97999 <= zext_ln1265_2_fu_85662_p1; + acc_23_V_addr_53_reg_98287 <= zext_ln1265_2_fu_85662_p1; + acc_24_V_addr_52_reg_98005 <= zext_ln1265_2_fu_85662_p1; + acc_25_V_addr_53_reg_98173 <= zext_ln1265_2_fu_85662_p1; + acc_26_V_addr_52_reg_98011 <= zext_ln1265_2_fu_85662_p1; + acc_27_V_addr_53_reg_98179 <= zext_ln1265_2_fu_85662_p1; + acc_28_V_addr_52_reg_98017 <= zext_ln1265_2_fu_85662_p1; + acc_29_V_addr_53_reg_98281 <= zext_ln1265_2_fu_85662_p1; + acc_2_V_addr_52_reg_97939 <= zext_ln1265_2_fu_85662_p1; + acc_30_V_addr_52_reg_98023 <= zext_ln1265_2_fu_85662_p1; + acc_31_V_addr_53_reg_98275 <= zext_ln1265_2_fu_85662_p1; + acc_32_V_addr_52_reg_98029 <= zext_ln1265_2_fu_85662_p1; + acc_33_V_addr_53_reg_98185 <= zext_ln1265_2_fu_85662_p1; + acc_34_V_addr_52_reg_98035 <= zext_ln1265_2_fu_85662_p1; + acc_35_V_addr_53_reg_98191 <= zext_ln1265_2_fu_85662_p1; + acc_36_V_addr_52_reg_98041 <= zext_ln1265_2_fu_85662_p1; + acc_37_V_addr_53_reg_98269 <= zext_ln1265_2_fu_85662_p1; + acc_38_V_addr_52_reg_98047 <= zext_ln1265_2_fu_85662_p1; + acc_39_V_addr_53_reg_98263 <= zext_ln1265_2_fu_85662_p1; + acc_3_V_addr_53_reg_98143 <= zext_ln1265_2_fu_85662_p1; + acc_40_V_addr_52_reg_98053 <= zext_ln1265_2_fu_85662_p1; + acc_41_V_addr_53_reg_98197 <= zext_ln1265_2_fu_85662_p1; + acc_42_V_addr_52_reg_98059 <= zext_ln1265_2_fu_85662_p1; + acc_43_V_addr_53_reg_98203 <= zext_ln1265_2_fu_85662_p1; + acc_44_V_addr_52_reg_98065 <= zext_ln1265_2_fu_85662_p1; + acc_45_V_addr_53_reg_98257 <= zext_ln1265_2_fu_85662_p1; + acc_46_V_addr_52_reg_98071 <= zext_ln1265_2_fu_85662_p1; + acc_47_V_addr_53_reg_98251 <= zext_ln1265_2_fu_85662_p1; + acc_48_V_addr_52_reg_98077 <= zext_ln1265_2_fu_85662_p1; + acc_49_V_addr_53_reg_98209 <= zext_ln1265_2_fu_85662_p1; + acc_4_V_addr_52_reg_97945 <= zext_ln1265_2_fu_85662_p1; + acc_50_V_addr_52_reg_98083 <= zext_ln1265_2_fu_85662_p1; + acc_51_V_addr_53_reg_98215 <= zext_ln1265_2_fu_85662_p1; + acc_52_V_addr_52_reg_98089 <= zext_ln1265_2_fu_85662_p1; + acc_53_V_addr_53_reg_98245 <= zext_ln1265_2_fu_85662_p1; + acc_54_V_addr_52_reg_98095 <= zext_ln1265_2_fu_85662_p1; + acc_55_V_addr_53_reg_98239 <= zext_ln1265_2_fu_85662_p1; + acc_56_V_addr_52_reg_98101 <= zext_ln1265_2_fu_85662_p1; + acc_57_V_addr_53_reg_98221 <= zext_ln1265_2_fu_85662_p1; + acc_58_V_addr_52_reg_98107 <= zext_ln1265_2_fu_85662_p1; + acc_59_V_addr_53_reg_98227 <= zext_ln1265_2_fu_85662_p1; + acc_5_V_addr_53_reg_98317 <= zext_ln1265_2_fu_85662_p1; + acc_60_V_addr_52_reg_98113 <= zext_ln1265_2_fu_85662_p1; + acc_61_V_addr_53_reg_98233 <= zext_ln1265_2_fu_85662_p1; + acc_62_V_addr_52_reg_98119 <= zext_ln1265_2_fu_85662_p1; + acc_63_V_addr_53_reg_98125 <= zext_ln1265_2_fu_85662_p1; + acc_6_V_addr_52_reg_97951 <= zext_ln1265_2_fu_85662_p1; + acc_7_V_addr_53_reg_98311 <= zext_ln1265_2_fu_85662_p1; + acc_8_V_addr_52_reg_97957 <= zext_ln1265_2_fu_85662_p1; + acc_9_V_addr_53_reg_98149 <= zext_ln1265_2_fu_85662_p1; + add_ln276_1_reg_98131 <= grp_fu_90021_p3; + add_ln279_3_reg_97927[5 : 2] <= add_ln279_3_fu_85643_p2[5 : 2]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln261_fu_81657_p2 == 1'd1) & (ap_ST_fsm_state1186 == ap_CS_fsm))) begin + acc_0_V_addr_53_reg_94678 <= zext_ln1265_3_fu_81745_p1; + acc_10_V_addr_53_reg_94630 <= zext_ln1265_3_fu_81745_p1; + acc_11_V_addr_54_reg_94624 <= zext_ln1265_3_fu_81745_p1; + acc_12_V_addr_53_reg_94618 <= zext_ln1265_3_fu_81745_p1; + acc_13_V_addr_54_reg_94312 <= zext_ln1265_3_fu_81745_p1; + acc_14_V_addr_53_reg_94612 <= zext_ln1265_3_fu_81745_p1; + acc_15_V_addr_54_reg_94318 <= zext_ln1265_3_fu_81745_p1; + acc_16_V_addr_53_reg_94606 <= zext_ln1265_3_fu_81745_p1; + acc_17_V_addr_54_reg_94600 <= zext_ln1265_3_fu_81745_p1; + acc_18_V_addr_53_reg_94594 <= zext_ln1265_3_fu_81745_p1; + acc_19_V_addr_54_reg_94588 <= zext_ln1265_3_fu_81745_p1; + acc_1_V_addr_54_reg_94672 <= zext_ln1265_3_fu_81745_p1; + acc_20_V_addr_53_reg_94582 <= zext_ln1265_3_fu_81745_p1; + acc_21_V_addr_54_reg_94324 <= zext_ln1265_3_fu_81745_p1; + acc_22_V_addr_53_reg_94576 <= zext_ln1265_3_fu_81745_p1; + acc_23_V_addr_54_reg_94330 <= zext_ln1265_3_fu_81745_p1; + acc_24_V_addr_53_reg_94570 <= zext_ln1265_3_fu_81745_p1; + acc_25_V_addr_54_reg_94564 <= zext_ln1265_3_fu_81745_p1; + acc_26_V_addr_53_reg_94558 <= zext_ln1265_3_fu_81745_p1; + acc_27_V_addr_54_reg_94552 <= zext_ln1265_3_fu_81745_p1; + acc_28_V_addr_53_reg_94546 <= zext_ln1265_3_fu_81745_p1; + acc_29_V_addr_54_reg_94336 <= zext_ln1265_3_fu_81745_p1; + acc_2_V_addr_53_reg_94666 <= zext_ln1265_3_fu_81745_p1; + acc_30_V_addr_53_reg_94540 <= zext_ln1265_3_fu_81745_p1; + acc_31_V_addr_54_reg_94342 <= zext_ln1265_3_fu_81745_p1; + acc_32_V_addr_53_reg_94534 <= zext_ln1265_3_fu_81745_p1; + acc_33_V_addr_54_reg_94528 <= zext_ln1265_3_fu_81745_p1; + acc_34_V_addr_53_reg_94522 <= zext_ln1265_3_fu_81745_p1; + acc_35_V_addr_54_reg_94516 <= zext_ln1265_3_fu_81745_p1; + acc_36_V_addr_53_reg_94510 <= zext_ln1265_3_fu_81745_p1; + acc_37_V_addr_54_reg_94348 <= zext_ln1265_3_fu_81745_p1; + acc_38_V_addr_53_reg_94504 <= zext_ln1265_3_fu_81745_p1; + acc_39_V_addr_54_reg_94354 <= zext_ln1265_3_fu_81745_p1; + acc_3_V_addr_54_reg_94660 <= zext_ln1265_3_fu_81745_p1; + acc_40_V_addr_53_reg_94498 <= zext_ln1265_3_fu_81745_p1; + acc_41_V_addr_54_reg_94492 <= zext_ln1265_3_fu_81745_p1; + acc_42_V_addr_53_reg_94486 <= zext_ln1265_3_fu_81745_p1; + acc_43_V_addr_54_reg_94480 <= zext_ln1265_3_fu_81745_p1; + acc_44_V_addr_53_reg_94474 <= zext_ln1265_3_fu_81745_p1; + acc_45_V_addr_54_reg_94360 <= zext_ln1265_3_fu_81745_p1; + acc_46_V_addr_53_reg_94468 <= zext_ln1265_3_fu_81745_p1; + acc_47_V_addr_54_reg_94366 <= zext_ln1265_3_fu_81745_p1; + acc_48_V_addr_53_reg_94462 <= zext_ln1265_3_fu_81745_p1; + acc_49_V_addr_54_reg_94456 <= zext_ln1265_3_fu_81745_p1; + acc_4_V_addr_53_reg_94654 <= zext_ln1265_3_fu_81745_p1; + acc_50_V_addr_53_reg_94450 <= zext_ln1265_3_fu_81745_p1; + acc_51_V_addr_54_reg_94444 <= zext_ln1265_3_fu_81745_p1; + acc_52_V_addr_53_reg_94438 <= zext_ln1265_3_fu_81745_p1; + acc_53_V_addr_54_reg_94372 <= zext_ln1265_3_fu_81745_p1; + acc_54_V_addr_53_reg_94432 <= zext_ln1265_3_fu_81745_p1; + acc_55_V_addr_54_reg_94378 <= zext_ln1265_3_fu_81745_p1; + acc_56_V_addr_53_reg_94426 <= zext_ln1265_3_fu_81745_p1; + acc_57_V_addr_54_reg_94420 <= zext_ln1265_3_fu_81745_p1; + acc_58_V_addr_53_reg_94414 <= zext_ln1265_3_fu_81745_p1; + acc_59_V_addr_54_reg_94408 <= zext_ln1265_3_fu_81745_p1; + acc_5_V_addr_54_reg_94300 <= zext_ln1265_3_fu_81745_p1; + acc_60_V_addr_53_reg_94402 <= zext_ln1265_3_fu_81745_p1; + acc_61_V_addr_54_reg_94384 <= zext_ln1265_3_fu_81745_p1; + acc_62_V_addr_53_reg_94396 <= zext_ln1265_3_fu_81745_p1; + acc_63_V_addr_54_reg_94390 <= zext_ln1265_3_fu_81745_p1; + acc_6_V_addr_53_reg_94648 <= zext_ln1265_3_fu_81745_p1; + acc_7_V_addr_54_reg_94306 <= zext_ln1265_3_fu_81745_p1; + acc_8_V_addr_53_reg_94642 <= zext_ln1265_3_fu_81745_p1; + acc_9_V_addr_54_reg_94636 <= zext_ln1265_3_fu_81745_p1; + add_ln276_2_reg_94294 <= grp_fu_89990_p3; + add_ln279_4_reg_94283[12 : 3] <= add_ln279_4_fu_81721_p2[12 : 3]; + add_ln279_5_reg_94288[5 : 3] <= add_ln279_5_fu_81726_p2[5 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln261_1_fu_85740_p2 == 1'd1) & (ap_ST_fsm_state1788 == ap_CS_fsm))) begin + acc_0_V_addr_55_reg_98742 <= zext_ln1265_4_fu_85828_p1; + acc_10_V_addr_55_reg_98694 <= zext_ln1265_4_fu_85828_p1; + acc_11_V_addr_56_reg_98688 <= zext_ln1265_4_fu_85828_p1; + acc_12_V_addr_55_reg_98682 <= zext_ln1265_4_fu_85828_p1; + acc_13_V_addr_56_reg_98376 <= zext_ln1265_4_fu_85828_p1; + acc_14_V_addr_55_reg_98676 <= zext_ln1265_4_fu_85828_p1; + acc_15_V_addr_56_reg_98382 <= zext_ln1265_4_fu_85828_p1; + acc_16_V_addr_55_reg_98670 <= zext_ln1265_4_fu_85828_p1; + acc_17_V_addr_56_reg_98664 <= zext_ln1265_4_fu_85828_p1; + acc_18_V_addr_55_reg_98658 <= zext_ln1265_4_fu_85828_p1; + acc_19_V_addr_56_reg_98652 <= zext_ln1265_4_fu_85828_p1; + acc_1_V_addr_56_reg_98736 <= zext_ln1265_4_fu_85828_p1; + acc_20_V_addr_55_reg_98646 <= zext_ln1265_4_fu_85828_p1; + acc_21_V_addr_56_reg_98388 <= zext_ln1265_4_fu_85828_p1; + acc_22_V_addr_55_reg_98640 <= zext_ln1265_4_fu_85828_p1; + acc_23_V_addr_56_reg_98394 <= zext_ln1265_4_fu_85828_p1; + acc_24_V_addr_55_reg_98634 <= zext_ln1265_4_fu_85828_p1; + acc_25_V_addr_56_reg_98628 <= zext_ln1265_4_fu_85828_p1; + acc_26_V_addr_55_reg_98622 <= zext_ln1265_4_fu_85828_p1; + acc_27_V_addr_56_reg_98616 <= zext_ln1265_4_fu_85828_p1; + acc_28_V_addr_55_reg_98610 <= zext_ln1265_4_fu_85828_p1; + acc_29_V_addr_56_reg_98400 <= zext_ln1265_4_fu_85828_p1; + acc_2_V_addr_55_reg_98730 <= zext_ln1265_4_fu_85828_p1; + acc_30_V_addr_55_reg_98604 <= zext_ln1265_4_fu_85828_p1; + acc_31_V_addr_56_reg_98406 <= zext_ln1265_4_fu_85828_p1; + acc_32_V_addr_55_reg_98598 <= zext_ln1265_4_fu_85828_p1; + acc_33_V_addr_56_reg_98592 <= zext_ln1265_4_fu_85828_p1; + acc_34_V_addr_55_reg_98586 <= zext_ln1265_4_fu_85828_p1; + acc_35_V_addr_56_reg_98580 <= zext_ln1265_4_fu_85828_p1; + acc_36_V_addr_55_reg_98574 <= zext_ln1265_4_fu_85828_p1; + acc_37_V_addr_56_reg_98412 <= zext_ln1265_4_fu_85828_p1; + acc_38_V_addr_55_reg_98568 <= zext_ln1265_4_fu_85828_p1; + acc_39_V_addr_56_reg_98418 <= zext_ln1265_4_fu_85828_p1; + acc_3_V_addr_56_reg_98724 <= zext_ln1265_4_fu_85828_p1; + acc_40_V_addr_55_reg_98562 <= zext_ln1265_4_fu_85828_p1; + acc_41_V_addr_56_reg_98556 <= zext_ln1265_4_fu_85828_p1; + acc_42_V_addr_55_reg_98550 <= zext_ln1265_4_fu_85828_p1; + acc_43_V_addr_56_reg_98544 <= zext_ln1265_4_fu_85828_p1; + acc_44_V_addr_55_reg_98538 <= zext_ln1265_4_fu_85828_p1; + acc_45_V_addr_56_reg_98424 <= zext_ln1265_4_fu_85828_p1; + acc_46_V_addr_55_reg_98532 <= zext_ln1265_4_fu_85828_p1; + acc_47_V_addr_56_reg_98430 <= zext_ln1265_4_fu_85828_p1; + acc_48_V_addr_55_reg_98526 <= zext_ln1265_4_fu_85828_p1; + acc_49_V_addr_56_reg_98520 <= zext_ln1265_4_fu_85828_p1; + acc_4_V_addr_55_reg_98718 <= zext_ln1265_4_fu_85828_p1; + acc_50_V_addr_55_reg_98514 <= zext_ln1265_4_fu_85828_p1; + acc_51_V_addr_56_reg_98508 <= zext_ln1265_4_fu_85828_p1; + acc_52_V_addr_55_reg_98502 <= zext_ln1265_4_fu_85828_p1; + acc_53_V_addr_56_reg_98436 <= zext_ln1265_4_fu_85828_p1; + acc_54_V_addr_55_reg_98496 <= zext_ln1265_4_fu_85828_p1; + acc_55_V_addr_56_reg_98442 <= zext_ln1265_4_fu_85828_p1; + acc_56_V_addr_55_reg_98490 <= zext_ln1265_4_fu_85828_p1; + acc_57_V_addr_56_reg_98484 <= zext_ln1265_4_fu_85828_p1; + acc_58_V_addr_55_reg_98478 <= zext_ln1265_4_fu_85828_p1; + acc_59_V_addr_56_reg_98472 <= zext_ln1265_4_fu_85828_p1; + acc_5_V_addr_56_reg_98364 <= zext_ln1265_4_fu_85828_p1; + acc_60_V_addr_55_reg_98466 <= zext_ln1265_4_fu_85828_p1; + acc_61_V_addr_56_reg_98448 <= zext_ln1265_4_fu_85828_p1; + acc_62_V_addr_55_reg_98460 <= zext_ln1265_4_fu_85828_p1; + acc_63_V_addr_57_reg_98454 <= zext_ln1265_4_fu_85828_p1; + acc_6_V_addr_55_reg_98712 <= zext_ln1265_4_fu_85828_p1; + acc_7_V_addr_56_reg_98370 <= zext_ln1265_4_fu_85828_p1; + acc_8_V_addr_55_reg_98706 <= zext_ln1265_4_fu_85828_p1; + acc_9_V_addr_56_reg_98700 <= zext_ln1265_4_fu_85828_p1; + add_ln276_6_reg_98358 <= grp_fu_90036_p3; + add_ln279_6_reg_98347[12 : 3] <= add_ln279_6_fu_85804_p2[12 : 3]; + add_ln279_7_reg_98352[5 : 3] <= add_ln279_7_fu_85809_p2[5 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln261_2_fu_83525_p2 == 1'd0) & (ap_ST_fsm_state1487 == ap_CS_fsm))) begin + acc_0_V_addr_56_reg_96108 <= zext_ln1265_7_fu_83563_p1; + acc_10_V_addr_56_reg_96138 <= zext_ln1265_7_fu_83563_p1; + acc_11_V_addr_57_reg_96462 <= zext_ln1265_7_fu_83563_p1; + acc_12_V_addr_56_reg_96144 <= zext_ln1265_7_fu_83563_p1; + acc_13_V_addr_57_reg_96456 <= zext_ln1265_7_fu_83563_p1; + acc_14_V_addr_56_reg_96150 <= zext_ln1265_7_fu_83563_p1; + acc_15_V_addr_57_reg_96450 <= zext_ln1265_7_fu_83563_p1; + acc_16_V_addr_56_reg_96156 <= zext_ln1265_7_fu_83563_p1; + acc_17_V_addr_57_reg_96444 <= zext_ln1265_7_fu_83563_p1; + acc_18_V_addr_56_reg_96162 <= zext_ln1265_7_fu_83563_p1; + acc_19_V_addr_57_reg_96438 <= zext_ln1265_7_fu_83563_p1; + acc_1_V_addr_57_reg_96492 <= zext_ln1265_7_fu_83563_p1; + acc_20_V_addr_56_reg_96168 <= zext_ln1265_7_fu_83563_p1; + acc_21_V_addr_57_reg_96432 <= zext_ln1265_7_fu_83563_p1; + acc_22_V_addr_56_reg_96174 <= zext_ln1265_7_fu_83563_p1; + acc_23_V_addr_57_reg_96426 <= zext_ln1265_7_fu_83563_p1; + acc_24_V_addr_56_reg_96180 <= zext_ln1265_7_fu_83563_p1; + acc_25_V_addr_57_reg_96420 <= zext_ln1265_7_fu_83563_p1; + acc_26_V_addr_56_reg_96186 <= zext_ln1265_7_fu_83563_p1; + acc_27_V_addr_57_reg_96414 <= zext_ln1265_7_fu_83563_p1; + acc_28_V_addr_56_reg_96192 <= zext_ln1265_7_fu_83563_p1; + acc_29_V_addr_57_reg_96408 <= zext_ln1265_7_fu_83563_p1; + acc_2_V_addr_56_reg_96114 <= zext_ln1265_7_fu_83563_p1; + acc_30_V_addr_56_reg_96198 <= zext_ln1265_7_fu_83563_p1; + acc_31_V_addr_57_reg_96402 <= zext_ln1265_7_fu_83563_p1; + acc_32_V_addr_56_reg_96204 <= zext_ln1265_7_fu_83563_p1; + acc_33_V_addr_57_reg_96396 <= zext_ln1265_7_fu_83563_p1; + acc_34_V_addr_56_reg_96210 <= zext_ln1265_7_fu_83563_p1; + acc_35_V_addr_57_reg_96390 <= zext_ln1265_7_fu_83563_p1; + acc_36_V_addr_56_reg_96216 <= zext_ln1265_7_fu_83563_p1; + acc_37_V_addr_57_reg_96384 <= zext_ln1265_7_fu_83563_p1; + acc_38_V_addr_56_reg_96222 <= zext_ln1265_7_fu_83563_p1; + acc_39_V_addr_57_reg_96378 <= zext_ln1265_7_fu_83563_p1; + acc_3_V_addr_57_reg_96486 <= zext_ln1265_7_fu_83563_p1; + acc_40_V_addr_56_reg_96228 <= zext_ln1265_7_fu_83563_p1; + acc_41_V_addr_57_reg_96372 <= zext_ln1265_7_fu_83563_p1; + acc_42_V_addr_56_reg_96234 <= zext_ln1265_7_fu_83563_p1; + acc_43_V_addr_57_reg_96366 <= zext_ln1265_7_fu_83563_p1; + acc_44_V_addr_56_reg_96240 <= zext_ln1265_7_fu_83563_p1; + acc_45_V_addr_57_reg_96360 <= zext_ln1265_7_fu_83563_p1; + acc_46_V_addr_56_reg_96246 <= zext_ln1265_7_fu_83563_p1; + acc_47_V_addr_57_reg_96354 <= zext_ln1265_7_fu_83563_p1; + acc_48_V_addr_56_reg_96252 <= zext_ln1265_7_fu_83563_p1; + acc_49_V_addr_57_reg_96348 <= zext_ln1265_7_fu_83563_p1; + acc_4_V_addr_56_reg_96120 <= zext_ln1265_7_fu_83563_p1; + acc_50_V_addr_56_reg_96258 <= zext_ln1265_7_fu_83563_p1; + acc_51_V_addr_57_reg_96342 <= zext_ln1265_7_fu_83563_p1; + acc_52_V_addr_56_reg_96264 <= zext_ln1265_7_fu_83563_p1; + acc_53_V_addr_57_reg_96336 <= zext_ln1265_7_fu_83563_p1; + acc_54_V_addr_56_reg_96270 <= zext_ln1265_7_fu_83563_p1; + acc_55_V_addr_57_reg_96330 <= zext_ln1265_7_fu_83563_p1; + acc_56_V_addr_56_reg_96276 <= zext_ln1265_7_fu_83563_p1; + acc_57_V_addr_57_reg_96324 <= zext_ln1265_7_fu_83563_p1; + acc_58_V_addr_56_reg_96282 <= zext_ln1265_7_fu_83563_p1; + acc_59_V_addr_57_reg_96318 <= zext_ln1265_7_fu_83563_p1; + acc_5_V_addr_57_reg_96480 <= zext_ln1265_7_fu_83563_p1; + acc_60_V_addr_56_reg_96288 <= zext_ln1265_7_fu_83563_p1; + acc_61_V_addr_57_reg_96312 <= zext_ln1265_7_fu_83563_p1; + acc_62_V_addr_56_reg_96294 <= zext_ln1265_7_fu_83563_p1; + acc_63_V_addr_58_reg_96300 <= zext_ln1265_7_fu_83563_p1; + acc_6_V_addr_56_reg_96126 <= zext_ln1265_7_fu_83563_p1; + acc_7_V_addr_57_reg_96474 <= zext_ln1265_7_fu_83563_p1; + acc_8_V_addr_56_reg_96132 <= zext_ln1265_7_fu_83563_p1; + acc_9_V_addr_57_reg_96468 <= zext_ln1265_7_fu_83563_p1; + add_ln1265_reg_96098 <= add_ln1265_fu_83540_p2; + zext_ln1265_6_reg_96102[5 : 0] <= zext_ln1265_6_fu_83545_p1[5 : 0]; + zext_ln276_2_reg_96306[16 : 0] <= zext_ln276_2_fu_83631_p1[16 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln261_3_fu_87872_p2 == 1'd0) & (ap_ST_fsm_state2088 == ap_CS_fsm))) begin + acc_0_V_addr_58_reg_100182 <= zext_ln1265_11_fu_87910_p1; + acc_10_V_addr_58_reg_100212 <= zext_ln1265_11_fu_87910_p1; + acc_11_V_addr_58_reg_100536 <= zext_ln1265_11_fu_87910_p1; + acc_12_V_addr_58_reg_100218 <= zext_ln1265_11_fu_87910_p1; + acc_13_V_addr_58_reg_100530 <= zext_ln1265_11_fu_87910_p1; + acc_14_V_addr_58_reg_100224 <= zext_ln1265_11_fu_87910_p1; + acc_15_V_addr_58_reg_100524 <= zext_ln1265_11_fu_87910_p1; + acc_16_V_addr_58_reg_100230 <= zext_ln1265_11_fu_87910_p1; + acc_17_V_addr_58_reg_100518 <= zext_ln1265_11_fu_87910_p1; + acc_18_V_addr_58_reg_100236 <= zext_ln1265_11_fu_87910_p1; + acc_19_V_addr_58_reg_100512 <= zext_ln1265_11_fu_87910_p1; + acc_1_V_addr_58_reg_100566 <= zext_ln1265_11_fu_87910_p1; + acc_20_V_addr_58_reg_100242 <= zext_ln1265_11_fu_87910_p1; + acc_21_V_addr_58_reg_100506 <= zext_ln1265_11_fu_87910_p1; + acc_22_V_addr_58_reg_100248 <= zext_ln1265_11_fu_87910_p1; + acc_23_V_addr_58_reg_100500 <= zext_ln1265_11_fu_87910_p1; + acc_24_V_addr_58_reg_100254 <= zext_ln1265_11_fu_87910_p1; + acc_25_V_addr_58_reg_100494 <= zext_ln1265_11_fu_87910_p1; + acc_26_V_addr_58_reg_100260 <= zext_ln1265_11_fu_87910_p1; + acc_27_V_addr_58_reg_100488 <= zext_ln1265_11_fu_87910_p1; + acc_28_V_addr_58_reg_100266 <= zext_ln1265_11_fu_87910_p1; + acc_29_V_addr_58_reg_100482 <= zext_ln1265_11_fu_87910_p1; + acc_2_V_addr_58_reg_100188 <= zext_ln1265_11_fu_87910_p1; + acc_30_V_addr_58_reg_100272 <= zext_ln1265_11_fu_87910_p1; + acc_31_V_addr_58_reg_100476 <= zext_ln1265_11_fu_87910_p1; + acc_32_V_addr_58_reg_100278 <= zext_ln1265_11_fu_87910_p1; + acc_33_V_addr_58_reg_100470 <= zext_ln1265_11_fu_87910_p1; + acc_34_V_addr_58_reg_100284 <= zext_ln1265_11_fu_87910_p1; + acc_35_V_addr_58_reg_100464 <= zext_ln1265_11_fu_87910_p1; + acc_36_V_addr_58_reg_100290 <= zext_ln1265_11_fu_87910_p1; + acc_37_V_addr_58_reg_100458 <= zext_ln1265_11_fu_87910_p1; + acc_38_V_addr_58_reg_100296 <= zext_ln1265_11_fu_87910_p1; + acc_39_V_addr_58_reg_100452 <= zext_ln1265_11_fu_87910_p1; + acc_3_V_addr_58_reg_100560 <= zext_ln1265_11_fu_87910_p1; + acc_40_V_addr_58_reg_100302 <= zext_ln1265_11_fu_87910_p1; + acc_41_V_addr_58_reg_100446 <= zext_ln1265_11_fu_87910_p1; + acc_42_V_addr_58_reg_100308 <= zext_ln1265_11_fu_87910_p1; + acc_43_V_addr_58_reg_100440 <= zext_ln1265_11_fu_87910_p1; + acc_44_V_addr_58_reg_100314 <= zext_ln1265_11_fu_87910_p1; + acc_45_V_addr_58_reg_100434 <= zext_ln1265_11_fu_87910_p1; + acc_46_V_addr_58_reg_100320 <= zext_ln1265_11_fu_87910_p1; + acc_47_V_addr_58_reg_100428 <= zext_ln1265_11_fu_87910_p1; + acc_48_V_addr_58_reg_100326 <= zext_ln1265_11_fu_87910_p1; + acc_49_V_addr_58_reg_100422 <= zext_ln1265_11_fu_87910_p1; + acc_4_V_addr_58_reg_100194 <= zext_ln1265_11_fu_87910_p1; + acc_50_V_addr_58_reg_100332 <= zext_ln1265_11_fu_87910_p1; + acc_51_V_addr_58_reg_100416 <= zext_ln1265_11_fu_87910_p1; + acc_52_V_addr_58_reg_100338 <= zext_ln1265_11_fu_87910_p1; + acc_53_V_addr_58_reg_100410 <= zext_ln1265_11_fu_87910_p1; + acc_54_V_addr_58_reg_100344 <= zext_ln1265_11_fu_87910_p1; + acc_55_V_addr_58_reg_100404 <= zext_ln1265_11_fu_87910_p1; + acc_56_V_addr_58_reg_100350 <= zext_ln1265_11_fu_87910_p1; + acc_57_V_addr_58_reg_100398 <= zext_ln1265_11_fu_87910_p1; + acc_58_V_addr_58_reg_100356 <= zext_ln1265_11_fu_87910_p1; + acc_59_V_addr_58_reg_100392 <= zext_ln1265_11_fu_87910_p1; + acc_5_V_addr_58_reg_100554 <= zext_ln1265_11_fu_87910_p1; + acc_60_V_addr_58_reg_100362 <= zext_ln1265_11_fu_87910_p1; + acc_61_V_addr_58_reg_100386 <= zext_ln1265_11_fu_87910_p1; + acc_62_V_addr_58_reg_100368 <= zext_ln1265_11_fu_87910_p1; + acc_63_V_addr_60_reg_100374 <= zext_ln1265_11_fu_87910_p1; + acc_6_V_addr_58_reg_100200 <= zext_ln1265_11_fu_87910_p1; + acc_7_V_addr_58_reg_100548 <= zext_ln1265_11_fu_87910_p1; + acc_8_V_addr_58_reg_100206 <= zext_ln1265_11_fu_87910_p1; + acc_9_V_addr_58_reg_100542 <= zext_ln1265_11_fu_87910_p1; + add_ln1265_1_reg_100172 <= add_ln1265_1_fu_87887_p2; + zext_ln1265_10_reg_100176[5 : 0] <= zext_ln1265_10_fu_87892_p1[5 : 0]; + zext_ln276_3_reg_100380[16 : 0] <= zext_ln276_3_fu_87978_p1[16 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln248_fu_80819_p2 == 1'd1) & (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_11_V_addr_52_reg_92492 <= zext_ln203_7_fu_80880_p1; + acc_13_V_addr_52_reg_92497 <= zext_ln203_7_fu_80880_p1; + acc_15_V_addr_52_reg_92502 <= zext_ln203_7_fu_80880_p1; + acc_17_V_addr_52_reg_92507 <= zext_ln203_7_fu_80880_p1; + acc_19_V_addr_52_reg_92512 <= zext_ln203_7_fu_80880_p1; + acc_1_V_addr_52_reg_92467 <= zext_ln203_7_fu_80880_p1; + acc_21_V_addr_52_reg_92517 <= zext_ln203_7_fu_80880_p1; + acc_23_V_addr_52_reg_92522 <= zext_ln203_7_fu_80880_p1; + acc_25_V_addr_52_reg_92527 <= zext_ln203_7_fu_80880_p1; + acc_27_V_addr_52_reg_92532 <= zext_ln203_7_fu_80880_p1; + acc_29_V_addr_52_reg_92537 <= zext_ln203_7_fu_80880_p1; + acc_31_V_addr_52_reg_92542 <= zext_ln203_7_fu_80880_p1; + acc_33_V_addr_52_reg_92547 <= zext_ln203_7_fu_80880_p1; + acc_35_V_addr_52_reg_92552 <= zext_ln203_7_fu_80880_p1; + acc_37_V_addr_52_reg_92557 <= zext_ln203_7_fu_80880_p1; + acc_39_V_addr_52_reg_92562 <= zext_ln203_7_fu_80880_p1; + acc_3_V_addr_52_reg_92472 <= zext_ln203_7_fu_80880_p1; + acc_41_V_addr_52_reg_92567 <= zext_ln203_7_fu_80880_p1; + acc_43_V_addr_52_reg_92572 <= zext_ln203_7_fu_80880_p1; + acc_45_V_addr_52_reg_92577 <= zext_ln203_7_fu_80880_p1; + acc_47_V_addr_52_reg_92582 <= zext_ln203_7_fu_80880_p1; + acc_49_V_addr_52_reg_92587 <= zext_ln203_7_fu_80880_p1; + acc_51_V_addr_52_reg_92592 <= zext_ln203_7_fu_80880_p1; + acc_53_V_addr_52_reg_92597 <= zext_ln203_7_fu_80880_p1; + acc_55_V_addr_52_reg_92602 <= zext_ln203_7_fu_80880_p1; + acc_57_V_addr_52_reg_92607 <= zext_ln203_7_fu_80880_p1; + acc_59_V_addr_52_reg_92612 <= zext_ln203_7_fu_80880_p1; + acc_5_V_addr_52_reg_92477 <= zext_ln203_7_fu_80880_p1; + acc_61_V_addr_52_reg_92617 <= zext_ln203_7_fu_80880_p1; + acc_63_V_addr_52_reg_92622 <= zext_ln203_7_fu_80880_p1; + acc_7_V_addr_52_reg_92482 <= zext_ln203_7_fu_80880_p1; + acc_9_V_addr_52_reg_92487 <= zext_ln203_7_fu_80880_p1; + add_ln250_4_reg_92456[12 : 3] <= add_ln250_4_fu_80856_p2[12 : 3]; + add_ln250_5_reg_92461[5 : 3] <= add_ln250_5_fu_80861_p2[5 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln248_1_fu_81191_p2 == 1'd1) & (ap_ST_fsm_state1176 == ap_CS_fsm))) begin + acc_11_V_addr_55_reg_93040 <= zext_ln203_9_fu_81256_p1; + acc_13_V_addr_55_reg_93045 <= zext_ln203_9_fu_81256_p1; + acc_15_V_addr_55_reg_93050 <= zext_ln203_9_fu_81256_p1; + acc_17_V_addr_55_reg_93055 <= zext_ln203_9_fu_81256_p1; + acc_19_V_addr_55_reg_93060 <= zext_ln203_9_fu_81256_p1; + acc_1_V_addr_55_reg_93015 <= zext_ln203_9_fu_81256_p1; + acc_21_V_addr_55_reg_93065 <= zext_ln203_9_fu_81256_p1; + acc_23_V_addr_55_reg_93070 <= zext_ln203_9_fu_81256_p1; + acc_25_V_addr_55_reg_93075 <= zext_ln203_9_fu_81256_p1; + acc_27_V_addr_55_reg_93080 <= zext_ln203_9_fu_81256_p1; + acc_29_V_addr_55_reg_93085 <= zext_ln203_9_fu_81256_p1; + acc_31_V_addr_55_reg_93090 <= zext_ln203_9_fu_81256_p1; + acc_33_V_addr_55_reg_93095 <= zext_ln203_9_fu_81256_p1; + acc_35_V_addr_55_reg_93100 <= zext_ln203_9_fu_81256_p1; + acc_37_V_addr_55_reg_93105 <= zext_ln203_9_fu_81256_p1; + acc_39_V_addr_55_reg_93110 <= zext_ln203_9_fu_81256_p1; + acc_3_V_addr_55_reg_93020 <= zext_ln203_9_fu_81256_p1; + acc_41_V_addr_55_reg_93115 <= zext_ln203_9_fu_81256_p1; + acc_43_V_addr_55_reg_93120 <= zext_ln203_9_fu_81256_p1; + acc_45_V_addr_55_reg_93125 <= zext_ln203_9_fu_81256_p1; + acc_47_V_addr_55_reg_93130 <= zext_ln203_9_fu_81256_p1; + acc_49_V_addr_55_reg_93135 <= zext_ln203_9_fu_81256_p1; + acc_51_V_addr_55_reg_93140 <= zext_ln203_9_fu_81256_p1; + acc_53_V_addr_55_reg_93145 <= zext_ln203_9_fu_81256_p1; + acc_55_V_addr_55_reg_93150 <= zext_ln203_9_fu_81256_p1; + acc_57_V_addr_55_reg_93155 <= zext_ln203_9_fu_81256_p1; + acc_59_V_addr_55_reg_93160 <= zext_ln203_9_fu_81256_p1; + acc_5_V_addr_55_reg_93025 <= zext_ln203_9_fu_81256_p1; + acc_61_V_addr_55_reg_93165 <= zext_ln203_9_fu_81256_p1; + acc_63_V_addr_55_reg_93170 <= zext_ln203_9_fu_81256_p1; + acc_7_V_addr_55_reg_93030 <= zext_ln203_9_fu_81256_p1; + acc_9_V_addr_55_reg_93035 <= zext_ln203_9_fu_81256_p1; + add_ln250_7_reg_93009[5 : 3] <= add_ln250_7_fu_81237_p2[5 : 3]; + sext_ln250_reg_93004[13 : 3] <= sext_ln250_fu_81233_p1[13 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln201_fu_73698_p2 == 1'd0))) begin + add_ln1116_1_reg_90120 <= add_ln1116_1_fu_73728_p2; + mul_ln231_reg_90095 <= mul_ln231_fu_73704_p2; + sext_ln231_reg_90105 <= sext_ln231_fu_73720_p1; + trunc_ln231_reg_90111 <= trunc_ln231_fu_73724_p1; + zext_ln231_reg_90100[4 : 0] <= zext_ln231_fu_73710_p1[4 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln203_fu_73758_p2 == 1'd1))) begin + add_ln1116_2_reg_90183 <= add_ln1116_2_fu_73821_p2; + mul_ln231_2_reg_90172[11 : 2] <= mul_ln231_2_fu_73806_p2[11 : 2]; + sext_ln231_2_reg_90177 <= sext_ln231_2_fu_73817_p1; + zext_ln201_2_reg_90164[4 : 1] <= zext_ln201_2_fu_73798_p1[4 : 1]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state585 == ap_CS_fsm) & (icmp_ln203_1_fu_77216_p2 == 1'd1))) begin + add_ln1116_3_reg_91168 <= add_ln1116_3_fu_77279_p2; + mul_ln231_3_reg_91157[11 : 2] <= mul_ln231_3_fu_77264_p2[11 : 2]; + sext_ln231_3_reg_91162 <= sext_ln231_3_fu_77275_p1; + zext_ln201_3_reg_91149[4 : 1] <= zext_ln201_3_fu_77256_p1[4 : 1]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state584 == ap_CS_fsm) & (icmp_ln201_1_fu_77164_p2 == 1'd0))) begin + add_ln1116_reg_91112 <= add_ln1116_fu_77194_p2; + mul_ln231_1_reg_91091 <= mul_ln231_1_fu_77170_p2; + sext_ln231_1_reg_91101 <= sext_ln231_1_fu_77186_p1; + trunc_ln231_1_reg_91107 <= trunc_ln231_1_fu_77190_p1; + zext_ln231_3_reg_91096[4 : 0] <= zext_ln231_3_fu_77176_p1[4 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state294 == ap_CS_fsm)) begin + add_ln203_10_reg_90620 <= add_ln203_10_fu_75476_p2; + add_ln203_5_reg_90633 <= add_ln203_5_fu_75492_p2; + zext_ln203_5_reg_90625[2 : 0] <= zext_ln203_5_fu_75482_p1[2 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state875 == ap_CS_fsm)) begin + add_ln203_11_reg_91613 <= add_ln203_11_fu_78936_p2; + add_ln203_6_reg_91626 <= add_ln203_6_fu_78952_p2; + zext_ln203_8_reg_91618[2 : 0] <= zext_ln203_8_fu_78942_p1[2 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state585 == ap_CS_fsm)) begin + add_ln203_4_reg_91138 <= add_ln203_4_fu_77222_p2; + add_ln203_9_reg_91125 <= add_ln203_9_fu_77206_p2; + zext_ln203_4_reg_91130[2 : 0] <= zext_ln203_4_fu_77212_p1[2 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + add_ln203_8_reg_90140 <= add_ln203_8_fu_73748_p2; + add_ln203_reg_90153 <= add_ln203_fu_73764_p2; + zext_ln203_reg_90145[2 : 0] <= zext_ln203_fu_73754_p1[2 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state296 == ap_CS_fsm)) begin + add_ln216_11_reg_90658 <= add_ln216_11_fu_75604_p2; + add_ln231_6_reg_90670 <= add_ln231_6_fu_75628_p2; + or_ln221_2_reg_90664 <= or_ln221_2_fu_75620_p3; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state877 == ap_CS_fsm)) begin + add_ln216_17_reg_91657 <= add_ln216_17_fu_79068_p2; + add_ln231_7_reg_91669 <= add_ln231_7_fu_79092_p2; + or_ln221_3_reg_91663 <= or_ln221_3_fu_79084_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state43 == ap_CS_fsm) & (icmp_ln208_fu_74233_p2 == 1'd0))) begin + add_ln216_20_reg_90288 <= add_ln216_20_fu_74239_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state43 == ap_CS_fsm) & (icmp_ln208_fu_74233_p2 == 1'd1) & (icmp_ln206_fu_74326_p2 == 1'd0))) begin + add_ln216_22_reg_90316 <= add_ln216_22_fu_74400_p2; + add_ln221_12_reg_90322 <= add_ln221_12_fu_74411_p2; + or_ln223_8_reg_90312 <= or_ln223_8_fu_74371_p2; + trunc_ln1116_6_reg_90333[2] <= trunc_ln1116_6_fu_74421_p1[2]; + trunc_ln231_10_reg_90328[10 : 2] <= trunc_ln231_10_fu_74417_p1[10 : 2]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state624 == ap_CS_fsm) & (icmp_ln208_1_fu_77694_p2 == 1'd0))) begin + add_ln216_23_reg_91281 <= add_ln216_23_fu_77700_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state333 == ap_CS_fsm) & (icmp_ln208_2_fu_75923_p2 == 1'd0))) begin + add_ln216_24_reg_90748 <= add_ln216_24_fu_75929_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state624 == ap_CS_fsm) & (icmp_ln208_1_fu_77694_p2 == 1'd1) & (icmp_ln206_1_fu_77787_p2 == 1'd0))) begin + add_ln216_27_reg_91309 <= add_ln216_27_fu_77861_p2; + add_ln221_17_reg_91315 <= add_ln221_17_fu_77872_p2; + or_ln223_10_reg_91305 <= or_ln223_10_fu_77832_p2; + trunc_ln231_11_reg_91321[10 : 3] <= trunc_ln231_11_fu_77878_p1[10 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state333 == ap_CS_fsm) & (icmp_ln208_2_fu_75923_p2 == 1'd1) & (icmp_ln206_2_fu_76016_p2 == 1'd0))) begin + add_ln216_29_reg_90776 <= add_ln216_29_fu_76090_p2; + add_ln221_19_reg_90782 <= add_ln221_19_fu_76101_p2; + or_ln223_12_reg_90772 <= or_ln223_12_fu_76061_p2; + trunc_ln1116_10_reg_90793[2] <= trunc_ln1116_10_fu_76111_p1[2]; + trunc_ln231_12_reg_90788[10 : 2] <= trunc_ln231_12_fu_76107_p1[10 : 2]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state914 == ap_CS_fsm) & (icmp_ln208_3_fu_79386_p2 == 1'd0))) begin + add_ln216_30_reg_91747 <= add_ln216_30_fu_79392_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state914 == ap_CS_fsm) & (icmp_ln208_3_fu_79386_p2 == 1'd1) & (icmp_ln206_3_fu_79499_p2 == 1'd0))) begin + add_ln216_34_reg_91780 <= add_ln216_34_fu_79573_p2; + add_ln221_24_reg_91786 <= add_ln221_24_fu_79584_p2; + or_ln223_15_reg_91776 <= or_ln223_15_fu_79544_p2; + trunc_ln231_14_reg_91792[10 : 3] <= trunc_ln231_14_fu_79590_p1[10 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_4_fu_75057_p2 == 1'd0) & (ap_ST_fsm_state187 == ap_CS_fsm))) begin + add_ln216_36_reg_90503 <= add_ln216_36_fu_75063_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state768 == ap_CS_fsm) & (icmp_ln208_5_fu_78517_p2 == 1'd0))) begin + add_ln216_37_reg_91496 <= add_ln216_37_fu_78523_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state477 == ap_CS_fsm) & (icmp_ln208_6_fu_76737_p2 == 1'd0))) begin + add_ln216_38_reg_90963 <= add_ln216_38_fu_76743_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln208_7_fu_80198_p2 == 1'd0) & (ap_ST_fsm_state1058 == ap_CS_fsm))) begin + add_ln216_39_reg_91967 <= add_ln216_39_fu_80204_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + add_ln216_3_reg_90198 <= add_ln216_3_fu_73904_p2; + add_ln231_3_reg_90210 <= add_ln231_3_fu_73928_p2; + or_ln_reg_90204 <= or_ln_fu_73920_p3; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state587 == ap_CS_fsm)) begin + add_ln216_9_reg_91191 <= add_ln216_9_fu_77366_p2; + add_ln231_5_reg_91203 <= add_ln231_5_fu_77390_p2; + or_ln221_1_reg_91197 <= or_ln221_1_fu_77382_p3; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state440 == ap_CS_fsm)) begin + add_ln231_10_reg_90885 <= add_ln231_10_fu_76443_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1021 == ap_CS_fsm)) begin + add_ln231_11_reg_91889 <= add_ln231_11_fu_79904_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state150 == ap_CS_fsm)) begin + add_ln231_8_reg_90425 <= add_ln231_8_fu_74753_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state731 == ap_CS_fsm)) begin + add_ln231_9_reg_91418 <= add_ln231_9_fu_78213_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1789 == ap_CS_fsm)) begin + add_ln276_11_reg_98748 <= add_ln276_11_fu_85907_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1488 == ap_CS_fsm)) begin + add_ln276_13_reg_96503 <= add_ln276_13_fu_83651_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1790 == ap_CS_fsm)) begin + add_ln276_15_reg_98754 <= add_ln276_15_fu_85913_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1489 == ap_CS_fsm)) begin + add_ln276_16_reg_96509 <= add_ln276_16_fu_83657_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2089 == ap_CS_fsm)) begin + add_ln276_18_reg_100577 <= add_ln276_18_fu_87998_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_fu_81997_p2 == 1'd0) & (ap_ST_fsm_state1225 == ap_CS_fsm))) begin + add_ln276_19_reg_94859 <= add_ln276_19_fu_82003_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2090 == ap_CS_fsm)) begin + add_ln276_20_reg_100583 <= add_ln276_20_fu_88004_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_fu_81997_p2 == 1'd1) & (icmp_ln266_fu_82020_p2 == 1'd0) & (ap_ST_fsm_state1225 == ap_CS_fsm))) begin + add_ln276_23_reg_94868 <= add_ln276_23_fu_82037_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_1_fu_86212_p2 == 1'd0) & (ap_ST_fsm_state1827 == ap_CS_fsm))) begin + add_ln276_24_reg_98928 <= add_ln276_24_fu_86218_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_2_fu_83956_p2 == 1'd0) & (ap_ST_fsm_state1526 == ap_CS_fsm))) begin + add_ln276_25_reg_96683 <= add_ln276_25_fu_83962_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1338 == ap_CS_fsm)) begin + add_ln276_27_reg_95390 <= add_ln276_27_fu_82592_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1263 == ap_CS_fsm)) begin + add_ln276_28_reg_95050 <= add_ln276_28_fu_82236_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_1_fu_86212_p2 == 1'd1) & (icmp_ln266_1_fu_86235_p2 == 1'd0) & (ap_ST_fsm_state1827 == ap_CS_fsm))) begin + add_ln276_31_reg_98937 <= add_ln276_31_fu_86252_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_2_fu_83956_p2 == 1'd1) & (icmp_ln266_2_fu_83979_p2 == 1'd0) & (ap_ST_fsm_state1526 == ap_CS_fsm))) begin + add_ln276_34_reg_96692 <= add_ln276_34_fu_83996_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1339 == ap_CS_fsm)) begin + add_ln276_35_reg_95396 <= add_ln276_35_fu_82598_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_3_fu_88303_p2 == 1'd0) & (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + add_ln276_36_reg_100757 <= add_ln276_36_fu_88309_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1940 == ap_CS_fsm)) begin + add_ln276_38_reg_99464 <= add_ln276_38_fu_86939_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1865 == ap_CS_fsm)) begin + add_ln276_39_reg_99119 <= add_ln276_39_fu_86451_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1639 == ap_CS_fsm)) begin + add_ln276_41_reg_97219 <= add_ln276_41_fu_84683_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + add_ln276_42_reg_96874 <= add_ln276_42_fu_84195_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_3_fu_88303_p2 == 1'd1) & (icmp_ln266_3_fu_88326_p2 == 1'd0) & (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + add_ln276_45_reg_100766 <= add_ln276_45_fu_88343_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1941 == ap_CS_fsm)) begin + add_ln276_46_reg_99470 <= add_ln276_46_fu_86945_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1640 == ap_CS_fsm)) begin + add_ln276_47_reg_97225 <= add_ln276_47_fu_84689_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_4_fu_82403_p2 == 1'd0) & (ap_ST_fsm_state1300 == ap_CS_fsm))) begin + add_ln276_48_reg_95219 <= add_ln276_48_fu_82409_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2239 == ap_CS_fsm)) begin + add_ln276_50_reg_101293 <= add_ln276_50_fu_89030_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + add_ln276_51_reg_100948 <= add_ln276_51_fu_88542_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_5_fu_82881_p2 == 1'd0) & (ap_ST_fsm_state1376 == ap_CS_fsm))) begin + add_ln276_52_reg_95570 <= add_ln276_52_fu_82887_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2240 == ap_CS_fsm)) begin + add_ln276_53_reg_101299 <= add_ln276_53_fu_89036_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_6_fu_86750_p2 == 1'd0) & (ap_ST_fsm_state1902 == ap_CS_fsm))) begin + add_ln276_54_reg_99293 <= add_ln276_54_fu_86756_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_7_fu_84494_p2 == 1'd0) & (ap_ST_fsm_state1601 == ap_CS_fsm))) begin + add_ln276_55_reg_97048 <= add_ln276_55_fu_84500_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_5_fu_82881_p2 == 1'd1) & (icmp_ln266_4_fu_82904_p2 == 1'd0) & (ap_ST_fsm_state1376 == ap_CS_fsm))) begin + add_ln276_57_reg_95579 <= add_ln276_57_fu_82921_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_8_fu_87228_p2 == 1'd0) & (ap_ST_fsm_state1977 == ap_CS_fsm))) begin + add_ln276_58_reg_99644 <= add_ln276_58_fu_87234_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_9_fu_84971_p2 == 1'd0) & (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + add_ln276_59_reg_97399 <= add_ln276_59_fu_84977_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1187 == ap_CS_fsm)) begin + add_ln276_5_reg_94684 <= add_ln276_5_fu_81824_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1414 == ap_CS_fsm)) begin + add_ln276_60_reg_95750 <= add_ln276_60_fu_83072_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_10_fu_88841_p2 == 1'd0) & (ap_ST_fsm_state2201 == ap_CS_fsm))) begin + add_ln276_61_reg_101122 <= add_ln276_61_fu_88847_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_8_fu_87228_p2 == 1'd1) & (icmp_ln266_5_fu_87251_p2 == 1'd0) & (ap_ST_fsm_state1977 == ap_CS_fsm))) begin + add_ln276_63_reg_99653 <= add_ln276_63_fu_87268_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_9_fu_84971_p2 == 1'd1) & (icmp_ln266_6_fu_84994_p2 == 1'd0) & (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + add_ln276_65_reg_97408 <= add_ln276_65_fu_85011_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_11_fu_89318_p2 == 1'd0) & (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + add_ln276_66_reg_101473 <= add_ln276_66_fu_89324_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2015 == ap_CS_fsm)) begin + add_ln276_67_reg_99824 <= add_ln276_67_fu_87419_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + add_ln276_68_reg_97579 <= add_ln276_68_fu_85161_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_11_fu_89318_p2 == 1'd1) & (icmp_ln266_7_fu_89341_p2 == 1'd0) & (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + add_ln276_70_reg_101482 <= add_ln276_70_fu_89358_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_12_fu_83355_p2 == 1'd0) & (ap_ST_fsm_state1450 == ap_CS_fsm))) begin + add_ln276_71_reg_95924 <= add_ln276_71_fu_83361_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + add_ln276_72_reg_101653 <= add_ln276_72_fu_89508_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_13_fu_87702_p2 == 1'd0) & (ap_ST_fsm_state2051 == ap_CS_fsm))) begin + add_ln276_73_reg_99998 <= add_ln276_73_fu_87708_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_14_fu_85443_p2 == 1'd0) & (ap_ST_fsm_state1750 == ap_CS_fsm))) begin + add_ln276_74_reg_97753 <= add_ln276_74_fu_85449_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln268_15_fu_89790_p2 == 1'd0) & (ap_ST_fsm_state2350 == ap_CS_fsm))) begin + add_ln276_75_reg_101827 <= add_ln276_75_fu_89796_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1188 == ap_CS_fsm)) begin + add_ln276_9_reg_94690 <= add_ln276_9_fu_81830_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + add_ln703_10_reg_99285 <= add_ln703_10_fu_86707_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + add_ln703_11_reg_97040 <= add_ln703_11_fu_84451_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + add_ln703_12_reg_99636 <= add_ln703_12_fu_87201_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + add_ln703_13_reg_97391 <= add_ln703_13_fu_84945_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + add_ln703_15_reg_101114 <= add_ln703_15_fu_88798_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + add_ln703_17_reg_101465 <= add_ln703_17_fu_89292_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + add_ln703_1_reg_98920 <= add_ln703_1_fu_86169_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + add_ln703_22_reg_95916 <= add_ln703_22_fu_83328_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + add_ln703_25_reg_99990 <= add_ln703_25_fu_87675_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + add_ln703_26_reg_97745 <= add_ln703_26_fu_85417_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + add_ln703_28_reg_101819 <= add_ln703_28_fu_89764_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + add_ln703_2_reg_96675 <= add_ln703_2_fu_83913_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + add_ln703_4_reg_100749 <= add_ln703_4_fu_88260_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + add_ln703_7_reg_95211 <= add_ln703_7_fu_82359_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + add_ln703_8_reg_95562 <= add_ln703_8_fu_82854_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + add_ln703_reg_94851 <= add_ln703_fu_81953_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state621 == ap_CS_fsm)) begin + lshr_ln1116_16_reg_91238 <= lshr_ln1116_16_fu_77601_p2; + sub_ln1116_5_reg_91233[6 : 1] <= sub_ln1116_5_fu_77591_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state330 == ap_CS_fsm)) begin + lshr_ln1116_18_reg_90705 <= lshr_ln1116_18_fu_75830_p2; + sub_ln1116_8_reg_90700[6 : 1] <= sub_ln1116_8_fu_75820_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state911 == ap_CS_fsm)) begin + lshr_ln1116_20_reg_91704 <= lshr_ln1116_20_fu_79293_p2; + sub_ln1116_11_reg_91699[6 : 1] <= sub_ln1116_11_fu_79283_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state79 == ap_CS_fsm)) begin + lshr_ln1116_22_reg_90357 <= lshr_ln1116_22_fu_74591_p2; + sub_ln1116_14_reg_90352[6 : 1] <= sub_ln1116_14_fu_74581_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state660 == ap_CS_fsm)) begin + lshr_ln1116_24_reg_91350 <= lshr_ln1116_24_fu_78051_p2; + sub_ln1116_17_reg_91345[6 : 1] <= sub_ln1116_17_fu_78041_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state369 == ap_CS_fsm)) begin + lshr_ln1116_26_reg_90817 <= lshr_ln1116_26_fu_76281_p2; + sub_ln1116_20_reg_90812[6 : 1] <= sub_ln1116_20_fu_76271_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state184 == ap_CS_fsm)) begin + lshr_ln1116_28_reg_90460 <= lshr_ln1116_28_fu_74964_p2; + sub_ln1116_23_reg_90455[6 : 1] <= sub_ln1116_23_fu_74954_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state950 == ap_CS_fsm)) begin + lshr_ln1116_30_reg_91821 <= lshr_ln1116_30_fu_79742_p2; + sub_ln1116_26_reg_91816[6 : 1] <= sub_ln1116_26_fu_79732_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state765 == ap_CS_fsm)) begin + lshr_ln1116_32_reg_91453 <= lshr_ln1116_32_fu_78424_p2; + sub_ln1116_29_reg_91448[6 : 1] <= sub_ln1116_29_fu_78414_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state474 == ap_CS_fsm)) begin + lshr_ln1116_34_reg_90920 <= lshr_ln1116_34_fu_76644_p2; + sub_ln1116_32_reg_90915[6 : 1] <= sub_ln1116_32_fu_76634_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1055 == ap_CS_fsm)) begin + lshr_ln1116_36_reg_91924 <= lshr_ln1116_36_fu_80105_p2; + sub_ln1116_35_reg_91919[6 : 1] <= sub_ln1116_35_fu_80095_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state223 == ap_CS_fsm)) begin + lshr_ln1116_38_reg_90552 <= lshr_ln1116_38_fu_75314_p2; + sub_ln1116_38_reg_90547[6 : 1] <= sub_ln1116_38_fu_75304_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state804 == ap_CS_fsm)) begin + lshr_ln1116_40_reg_91545 <= lshr_ln1116_40_fu_78774_p2; + sub_ln1116_41_reg_91540[6 : 1] <= sub_ln1116_41_fu_78764_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state513 == ap_CS_fsm)) begin + lshr_ln1116_42_reg_91012 <= lshr_ln1116_42_fu_76994_p2; + sub_ln1116_44_reg_91007[6 : 1] <= sub_ln1116_44_fu_76984_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1094 == ap_CS_fsm)) begin + lshr_ln1116_44_reg_92016 <= lshr_ln1116_44_fu_80455_p2; + sub_ln1116_47_reg_92011[6 : 1] <= sub_ln1116_47_fu_80445_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state40 == ap_CS_fsm)) begin + lshr_ln1116_reg_90245 <= lshr_ln1116_fu_74140_p2; + sub_ln1116_2_reg_90240[6 : 1] <= sub_ln1116_2_fu_74130_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln201_fu_73698_p2 == 1'd1))) begin + mul_ln201_1_reg_90134 <= mul_ln201_1_fu_89957_p2; + zext_ln199_reg_90126[4 : 1] <= zext_ln199_fu_73740_p1[4 : 1]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2 == ap_CS_fsm) & (icmp_ln199_fu_73684_p2 == 1'd0))) begin + mul_ln201_reg_90078 <= mul_ln201_fu_89951_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln259_fu_81487_p2 == 1'd1) & (ap_ST_fsm_state1185 == ap_CS_fsm))) begin + mul_ln279_1_reg_94247 <= mul_ln279_1_fu_89976_p2; + sub_ln279_1_reg_94253[12 : 5] <= sub_ln279_1_fu_81643_p2[12 : 5]; + trunc_ln279_1_reg_94259[5] <= trunc_ln279_1_fu_81649_p1[5]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln257_fu_81443_p2 == 1'd0) & (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + mul_ln279_reg_93205 <= mul_ln279_fu_89963_p2; + sub_ln279_reg_93211[12 : 4] <= sub_ln279_fu_81473_p2[12 : 4]; + trunc_ln279_reg_93217[5 : 4] <= trunc_ln279_fu_81479_p1[5 : 4]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + oh_0_0_cast_reg_90067[4 : 0] <= oh_0_0_cast_fu_73676_p1[4 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln261_1_fu_85740_p2 == 1'd0) & (ap_ST_fsm_state1788 == ap_CS_fsm))) begin + or_ln1265_1_reg_98331 <= or_ln1265_1_fu_85755_p3; + zext_ln1265_5_reg_98335[5 : 0] <= zext_ln1265_5_fu_85763_p1[5 : 0]; + zext_ln276_1_reg_98341[16 : 0] <= zext_ln276_1_fu_85767_p1[16 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_fu_82020_p2 == 1'd1) & (icmp_ln268_fu_81997_p2 == 1'd1) & (ap_ST_fsm_state1225 == ap_CS_fsm))) begin + or_ln1265_2_reg_94874[5 : 1] <= or_ln1265_2_fu_82066_p3[5 : 1]; + zext_ln1265_20_reg_94878[5 : 1] <= zext_ln1265_20_fu_82074_p1[5 : 1]; + zext_ln276_4_reg_94884[16 : 0] <= zext_ln276_4_fu_82078_p1[16 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_1_fu_86235_p2 == 1'd1) & (icmp_ln268_1_fu_86212_p2 == 1'd1) & (ap_ST_fsm_state1827 == ap_CS_fsm))) begin + or_ln1265_3_reg_98943[5 : 1] <= or_ln1265_3_fu_86281_p3[5 : 1]; + zext_ln1265_27_reg_98947[5 : 1] <= zext_ln1265_27_fu_86289_p1[5 : 1]; + zext_ln276_5_reg_98953[16 : 0] <= zext_ln276_5_fu_86293_p1[16 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_2_fu_83979_p2 == 1'd1) & (icmp_ln268_2_fu_83956_p2 == 1'd1) & (ap_ST_fsm_state1526 == ap_CS_fsm))) begin + or_ln1265_4_reg_96698[1] <= or_ln1265_4_fu_84025_p3[1]; +or_ln1265_4_reg_96698[5 : 3] <= or_ln1265_4_fu_84025_p3[5 : 3]; + zext_ln1265_28_reg_96702[1] <= zext_ln1265_28_fu_84033_p1[1]; +zext_ln1265_28_reg_96702[5 : 3] <= zext_ln1265_28_fu_84033_p1[5 : 3]; + zext_ln276_6_reg_96708[16 : 0] <= zext_ln276_6_fu_84037_p1[16 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln266_3_fu_88326_p2 == 1'd1) & (icmp_ln268_3_fu_88303_p2 == 1'd1) & (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + or_ln1265_5_reg_100772[1] <= or_ln1265_5_fu_88372_p3[1]; +or_ln1265_5_reg_100772[5 : 3] <= or_ln1265_5_fu_88372_p3[5 : 3]; + zext_ln1265_37_reg_100776[1] <= zext_ln1265_37_fu_88380_p1[1]; +zext_ln1265_37_reg_100776[5 : 3] <= zext_ln1265_37_fu_88380_p1[5 : 3]; + zext_ln276_7_reg_100782[16 : 0] <= zext_ln276_7_fu_88384_p1[16 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state586 == ap_CS_fsm)) begin + or_ln223_1_reg_91176 <= or_ln223_1_fu_77311_p2; + trunc_ln1116_reg_91185[2] <= trunc_ln1116_fu_77339_p1[2]; + trunc_ln231_3_reg_91180[10 : 2] <= trunc_ln231_3_fu_77335_p1[10 : 2]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state295 == ap_CS_fsm)) begin + or_ln223_2_reg_90649 <= or_ln223_2_fu_75553_p2; + trunc_ln231_4_reg_90653[10 : 2] <= trunc_ln231_4_fu_75577_p1[10 : 2]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state876 == ap_CS_fsm)) begin + or_ln223_4_reg_91642 <= or_ln223_4_fu_79013_p2; + trunc_ln1116_2_reg_91651[2] <= trunc_ln1116_2_fu_79041_p1[2]; + trunc_ln231_6_reg_91646[10 : 2] <= trunc_ln231_6_fu_79037_p1[10 : 2]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state5 == ap_CS_fsm)) begin + or_ln223_reg_90189 <= or_ln223_fu_73853_p2; + trunc_ln231_2_reg_90193[10 : 2] <= trunc_ln231_2_fu_73877_p1[10 : 2]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln261_fu_81657_p2 == 1'd0) & (ap_ST_fsm_state1186 == ap_CS_fsm))) begin + or_ln3_reg_94268 <= or_ln3_fu_81672_p3; + zext_ln1265_reg_94272[5 : 0] <= zext_ln1265_fu_81680_p1[5 : 0]; + zext_ln276_reg_94277[16 : 0] <= zext_ln276_fu_81684_p1[16 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state3 == ap_CS_fsm)) begin + ow_0_0_0_cast_reg_90084[4 : 0] <= ow_0_0_0_cast_fu_73690_p1[4 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state584 == ap_CS_fsm)) begin + ow_0_1_0_cast_reg_91080[4 : 0] <= ow_0_1_0_cast_fu_77156_p1[4 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state7 == ap_CS_fsm) & ((or_ln223_3_fu_73970_p2 == 1'd1) | (or_ln223_reg_90189 == 1'd1))) | ((ap_ST_fsm_state7 == ap_CS_fsm) & (or_ln223_3_fu_73970_p2 == 1'd0) & (or_ln223_reg_90189 == 1'd0)))) begin + reg_73628 <= grp_fu_73367_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state950 == ap_CS_fsm) | (ap_ST_fsm_state879 == ap_CS_fsm) | (ap_ST_fsm_state79 == ap_CS_fsm) | (ap_ST_fsm_state804 == ap_CS_fsm) | (ap_ST_fsm_state733 == ap_CS_fsm) | (ap_ST_fsm_state660 == ap_CS_fsm) | (ap_ST_fsm_state589 == ap_CS_fsm) | (ap_ST_fsm_state513 == ap_CS_fsm) | (ap_ST_fsm_state442 == ap_CS_fsm) | (ap_ST_fsm_state369 == ap_CS_fsm) | (ap_ST_fsm_state298 == ap_CS_fsm) | (ap_ST_fsm_state223 == ap_CS_fsm) | (ap_ST_fsm_state152 == ap_CS_fsm) | (ap_ST_fsm_state8 == ap_CS_fsm) | (ap_ST_fsm_state1094 == ap_CS_fsm) | (ap_ST_fsm_state1023 == ap_CS_fsm))) begin + reg_73633 <= w2_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state151 == ap_CS_fsm) & ((or_ln223_14_fu_74795_p2 == 1'd1) | (or_ln223_8_reg_90312 == 1'd1))) | ((or_ln223_14_fu_74795_p2 == 1'd0) & (or_ln223_8_reg_90312 == 1'd0) & (ap_ST_fsm_state151 == ap_CS_fsm)))) begin + reg_73637 <= grp_fu_73383_p2; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state297 == ap_CS_fsm) & ((or_ln223_6_fu_75670_p2 == 1'd1) | (or_ln223_2_reg_90649 == 1'd1))) | ((or_ln223_6_fu_75670_p2 == 1'd0) & (or_ln223_2_reg_90649 == 1'd0) & (ap_ST_fsm_state297 == ap_CS_fsm)))) begin + reg_73642 <= grp_fu_73399_p2; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state441 == ap_CS_fsm) & ((or_ln223_18_fu_76485_p2 == 1'd1) | (or_ln223_12_reg_90772 == 1'd1))) | ((ap_ST_fsm_state441 == ap_CS_fsm) & (or_ln223_18_fu_76485_p2 == 1'd0) & (or_ln223_12_reg_90772 == 1'd0)))) begin + reg_73647 <= grp_fu_73415_p2; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state588 == ap_CS_fsm) & ((or_ln223_5_fu_77432_p2 == 1'd1) | (or_ln223_1_reg_91176 == 1'd1))) | ((ap_ST_fsm_state588 == ap_CS_fsm) & (or_ln223_5_fu_77432_p2 == 1'd0) & (or_ln223_1_reg_91176 == 1'd0)))) begin + reg_73652 <= grp_fu_73431_p2; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state732 == ap_CS_fsm) & ((or_ln223_17_fu_78255_p2 == 1'd1) | (or_ln223_10_reg_91305 == 1'd1))) | ((ap_ST_fsm_state732 == ap_CS_fsm) & (or_ln223_17_fu_78255_p2 == 1'd0) & (or_ln223_10_reg_91305 == 1'd0)))) begin + reg_73657 <= grp_fu_73447_p2; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state878 == ap_CS_fsm) & ((or_ln223_7_fu_79134_p2 == 1'd1) | (or_ln223_4_reg_91642 == 1'd1))) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (or_ln223_7_fu_79134_p2 == 1'd0) & (or_ln223_4_reg_91642 == 1'd0)))) begin + reg_73662 <= grp_fu_73463_p2; + end +end + +always @ (posedge ap_clk) begin + if ((((ap_ST_fsm_state1022 == ap_CS_fsm) & ((or_ln223_19_fu_79946_p2 == 1'd1) | (or_ln223_15_reg_91776 == 1'd1))) | ((or_ln223_19_fu_79946_p2 == 1'd0) & (or_ln223_15_reg_91776 == 1'd0) & (ap_ST_fsm_state1022 == ap_CS_fsm)))) begin + reg_73667 <= grp_fu_73479_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state1264 == ap_CS_fsm) | (ap_ST_fsm_state1223 == ap_CS_fsm))) begin + reg_73672 <= grp_fu_73495_p66; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln246_fu_80657_p2 == 1'd1) & (ap_ST_fsm_state1166 == ap_CS_fsm))) begin + sub_ln250_1_reg_92438[12 : 5] <= sub_ln250_1_fu_80809_p2[12 : 5]; + trunc_ln250_1_reg_92444[5] <= trunc_ln250_1_fu_80815_p1[5]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln244_fu_80617_p2 == 1'd0) & (ap_ST_fsm_state1165 == ap_CS_fsm))) begin + sub_ln250_reg_92087[12 : 4] <= sub_ln250_fu_80647_p2[12 : 4]; + trunc_ln250_reg_92093[5 : 4] <= trunc_ln250_fu_80653_p1[5 : 4]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1265 == ap_CS_fsm)) begin + tmp_101_reg_95061 <= {{grp_fu_82250_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1298 == ap_CS_fsm)) begin + tmp_102_reg_95206 <= tmp_102_fu_82297_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1374 == ap_CS_fsm)) begin + tmp_116_reg_95552 <= tmp_116_fu_82659_p66; + tmp_118_reg_95557 <= tmp_118_fu_82792_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1341 == ap_CS_fsm)) begin + tmp_117_reg_95407 <= {{grp_fu_82612_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state729 == ap_CS_fsm)) begin + tmp_119_reg_91410 <= {{grp_fu_78162_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state693 == ap_CS_fsm)) begin + tmp_122_reg_91392 <= {{grp_fu_78102_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state438 == ap_CS_fsm)) begin + tmp_123_reg_90877 <= {{grp_fu_76392_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state402 == ap_CS_fsm)) begin + tmp_126_reg_90859 <= {{grp_fu_76332_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state189 == ap_CS_fsm)) begin + tmp_127_reg_90539 <= {{grp_fu_75174_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state153 == ap_CS_fsm)) begin + tmp_131_reg_90445 <= {{grp_fu_74810_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2128 == ap_CS_fsm)) begin + tmp_132_reg_100793 <= {{grp_fu_88390_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2161 == ap_CS_fsm)) begin + tmp_133_reg_100938 <= tmp_133_fu_88437_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1866 == ap_CS_fsm)) begin + tmp_135_reg_99125 <= tmp_135_fu_86462_p66; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1867 == ap_CS_fsm)) begin + tmp_136_reg_99135 <= {{grp_fu_86598_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1900 == ap_CS_fsm)) begin + tmp_137_reg_99280 <= tmp_137_fu_86645_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1565 == ap_CS_fsm)) begin + tmp_139_reg_96880 <= tmp_139_fu_84206_p66; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1566 == ap_CS_fsm)) begin + tmp_140_reg_96890 <= {{grp_fu_84342_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1599 == ap_CS_fsm)) begin + tmp_141_reg_97035 <= tmp_141_fu_84389_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1976 == ap_CS_fsm)) begin + tmp_150_reg_99626 <= tmp_150_fu_87006_p66; + tmp_152_reg_99631 <= tmp_152_fu_87139_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1943 == ap_CS_fsm)) begin + tmp_151_reg_99481 <= {{grp_fu_86959_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1675 == ap_CS_fsm)) begin + tmp_153_reg_97381 <= tmp_153_fu_84750_p66; + tmp_155_reg_97386 <= tmp_155_fu_84883_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1642 == ap_CS_fsm)) begin + tmp_154_reg_97236 <= {{grp_fu_84703_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1302 == ap_CS_fsm)) begin + tmp_156_reg_95235 <= {{grp_fu_82429_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1335 == ap_CS_fsm)) begin + tmp_157_reg_95380 <= tmp_157_fu_82476_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1019 == ap_CS_fsm)) begin + tmp_158_reg_91881 <= {{grp_fu_79853_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state983 == ap_CS_fsm)) begin + tmp_161_reg_91863 <= {{grp_fu_79793_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state770 == ap_CS_fsm)) begin + tmp_162_reg_91532 <= {{grp_fu_78634_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state734 == ap_CS_fsm)) begin + tmp_166_reg_91438 <= {{grp_fu_78270_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state479 == ap_CS_fsm)) begin + tmp_167_reg_90999 <= {{grp_fu_76854_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state443 == ap_CS_fsm)) begin + tmp_170_reg_90905 <= {{grp_fu_76500_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2165 == ap_CS_fsm)) begin + tmp_172_reg_100954 <= tmp_172_fu_88553_p66; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2166 == ap_CS_fsm)) begin + tmp_173_reg_100964 <= {{grp_fu_88689_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2199 == ap_CS_fsm)) begin + tmp_174_reg_101109 <= tmp_174_fu_88736_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1378 == ap_CS_fsm)) begin + tmp_175_reg_95595 <= {{grp_fu_82936_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1411 == ap_CS_fsm)) begin + tmp_176_reg_95740 <= tmp_176_fu_82983_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2275 == ap_CS_fsm)) begin + tmp_178_reg_101455 <= tmp_178_fu_89097_p66; + tmp_180_reg_101460 <= tmp_180_fu_89230_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2242 == ap_CS_fsm)) begin + tmp_179_reg_101310 <= {{grp_fu_89050_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1904 == ap_CS_fsm)) begin + tmp_181_reg_99309 <= {{grp_fu_86776_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1937 == ap_CS_fsm)) begin + tmp_182_reg_99454 <= tmp_182_fu_86823_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1603 == ap_CS_fsm)) begin + tmp_183_reg_97064 <= {{grp_fu_84520_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1636 == ap_CS_fsm)) begin + tmp_184_reg_97209 <= tmp_184_fu_84567_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1060 == ap_CS_fsm)) begin + tmp_186_reg_92003 <= {{grp_fu_80315_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1024 == ap_CS_fsm)) begin + tmp_189_reg_91909 <= {{grp_fu_79961_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1979 == ap_CS_fsm)) begin + tmp_190_reg_99669 <= {{grp_fu_87283_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2012 == ap_CS_fsm)) begin + tmp_191_reg_99814 <= tmp_191_fu_87330_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1678 == ap_CS_fsm)) begin + tmp_192_reg_97424 <= {{grp_fu_85026_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1711 == ap_CS_fsm)) begin + tmp_193_reg_97569 <= tmp_193_fu_85073_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1415 == ap_CS_fsm)) begin + tmp_194_reg_95756 <= tmp_194_fu_83083_p66; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1416 == ap_CS_fsm)) begin + tmp_195_reg_95766 <= {{grp_fu_83219_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1449 == ap_CS_fsm)) begin + tmp_196_reg_95911 <= tmp_196_fu_83266_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2203 == ap_CS_fsm)) begin + tmp_198_reg_101138 <= {{grp_fu_88867_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2236 == ap_CS_fsm)) begin + tmp_199_reg_101283 <= tmp_199_fu_88914_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state292 == ap_CS_fsm)) begin + tmp_202_reg_90612 <= {{grp_fu_75425_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state256 == ap_CS_fsm)) begin + tmp_205_reg_90594 <= {{grp_fu_75365_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2278 == ap_CS_fsm)) begin + tmp_206_reg_101498 <= {{grp_fu_89373_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2311 == ap_CS_fsm)) begin + tmp_207_reg_101643 <= tmp_207_fu_89420_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2016 == ap_CS_fsm)) begin + tmp_208_reg_99830 <= tmp_208_fu_87430_p66; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2017 == ap_CS_fsm)) begin + tmp_209_reg_99840 <= {{grp_fu_87566_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2050 == ap_CS_fsm)) begin + tmp_210_reg_99985 <= tmp_210_fu_87613_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1715 == ap_CS_fsm)) begin + tmp_211_reg_97585 <= tmp_211_fu_85172_p66; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1716 == ap_CS_fsm)) begin + tmp_212_reg_97595 <= {{grp_fu_85308_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1749 == ap_CS_fsm)) begin + tmp_213_reg_97740 <= tmp_213_fu_85355_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1452 == ap_CS_fsm)) begin + tmp_217_reg_95940 <= {{grp_fu_83381_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1485 == ap_CS_fsm)) begin + tmp_218_reg_96085 <= tmp_218_fu_83428_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state873 == ap_CS_fsm)) begin + tmp_219_reg_91605 <= {{grp_fu_78885_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state837 == ap_CS_fsm)) begin + tmp_222_reg_91587 <= {{grp_fu_78825_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state582 == ap_CS_fsm)) begin + tmp_223_reg_91072 <= {{grp_fu_77105_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state546 == ap_CS_fsm)) begin + tmp_226_reg_91054 <= {{grp_fu_77045_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2315 == ap_CS_fsm)) begin + tmp_227_reg_101659 <= tmp_227_fu_89519_p66; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2316 == ap_CS_fsm)) begin + tmp_228_reg_101669 <= {{grp_fu_89655_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2349 == ap_CS_fsm)) begin + tmp_229_reg_101814 <= tmp_229_fu_89702_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2086 == ap_CS_fsm)) begin + tmp_230_reg_100159 <= tmp_230_fu_87775_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1785 == ap_CS_fsm)) begin + tmp_231_reg_97914 <= tmp_231_fu_85516_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2385 == ap_CS_fsm)) begin + tmp_234_reg_101988 <= tmp_234_fu_89863_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2053 == ap_CS_fsm)) begin + tmp_235_reg_100014 <= {{grp_fu_87728_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1752 == ap_CS_fsm)) begin + tmp_236_reg_97769 <= {{grp_fu_85469_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1163 == ap_CS_fsm)) begin + tmp_237_reg_92076 <= {{grp_fu_80566_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1127 == ap_CS_fsm)) begin + tmp_239_reg_92058 <= {{grp_fu_80506_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2352 == ap_CS_fsm)) begin + tmp_240_reg_101843 <= {{grp_fu_89816_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1190 == ap_CS_fsm)) begin + tmp_51_reg_94701 <= {{grp_fu_81844_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1223 == ap_CS_fsm)) begin + tmp_52_reg_94846 <= tmp_52_fu_81891_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state626 == ap_CS_fsm)) begin + tmp_55_reg_91337 <= {{grp_fu_77890_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state590 == ap_CS_fsm)) begin + tmp_59_reg_91223 <= {{grp_fu_77447_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state45 == ap_CS_fsm)) begin + tmp_5_reg_90344 <= {{grp_fu_74429_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state335 == ap_CS_fsm)) begin + tmp_60_reg_90804 <= {{grp_fu_76119_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state299 == ap_CS_fsm)) begin + tmp_63_reg_90690 <= {{grp_fu_75685_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1825 == ap_CS_fsm)) begin + tmp_68_reg_98910 <= tmp_68_fu_85974_p66; + tmp_70_reg_98915 <= tmp_70_fu_86107_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1792 == ap_CS_fsm)) begin + tmp_69_reg_98765 <= {{grp_fu_85927_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1524 == ap_CS_fsm)) begin + tmp_71_reg_96665 <= tmp_71_fu_83718_p66; + tmp_73_reg_96670 <= tmp_73_fu_83851_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1491 == ap_CS_fsm)) begin + tmp_72_reg_96520 <= {{grp_fu_83671_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state916 == ap_CS_fsm)) begin + tmp_75_reg_91808 <= {{grp_fu_79602_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state880 == ap_CS_fsm)) begin + tmp_78_reg_91689 <= {{grp_fu_79149_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state9 == ap_CS_fsm)) begin + tmp_7_reg_90230 <= {{grp_fu_73985_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1227 == ap_CS_fsm)) begin + tmp_80_reg_94895 <= {{grp_fu_82084_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1260 == ap_CS_fsm)) begin + tmp_81_reg_95040 <= tmp_81_fu_82131_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2125 == ap_CS_fsm)) begin + tmp_85_reg_100739 <= tmp_85_fu_88065_p66; + tmp_87_reg_100744 <= tmp_87_fu_88198_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2092 == ap_CS_fsm)) begin + tmp_86_reg_100594 <= {{grp_fu_88018_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state148 == ap_CS_fsm)) begin + tmp_91_reg_90417 <= {{grp_fu_74702_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state112 == ap_CS_fsm)) begin + tmp_94_reg_90399 <= {{grp_fu_74642_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1829 == ap_CS_fsm)) begin + tmp_95_reg_98964 <= {{grp_fu_86299_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1862 == ap_CS_fsm)) begin + tmp_96_reg_99109 <= tmp_96_fu_86346_p30; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1528 == ap_CS_fsm)) begin + tmp_97_reg_96719 <= {{grp_fu_84043_p2[64:37]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1561 == ap_CS_fsm)) begin + tmp_98_reg_96864 <= tmp_98_fu_84090_p30; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state914 == ap_CS_fsm) & (or_ln223_16_fu_79436_p2 == 1'd0) & (icmp_ln208_3_fu_79386_p2 == 1'd0) & (or_ln223_4_reg_91642 == 1'd0))) begin + trunc_ln1116_4861135527_reg_91763 <= trunc_ln1116_4861135527_fu_79488_p2; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_20_fu_75107_p2 == 1'd0) & (icmp_ln208_4_fu_75057_p2 == 1'd0) & (or_ln223_8_reg_90312 == 1'd0) & (ap_ST_fsm_state187 == ap_CS_fsm))) begin + trunc_ln1116_566113357_reg_90519 <= trunc_ln1116_566113357_fu_75159_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state768 == ap_CS_fsm) & (or_ln223_21_fu_78567_p2 == 1'd0) & (icmp_ln208_5_fu_78517_p2 == 1'd0) & (or_ln223_10_reg_91305 == 1'd0))) begin + trunc_ln1116_5861135123_reg_91512 <= trunc_ln1116_5861135123_fu_78619_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state477 == ap_CS_fsm) & (or_ln223_22_fu_76787_p2 == 1'd0) & (icmp_ln208_6_fu_76737_p2 == 1'd0) & (or_ln223_12_reg_90772 == 1'd0))) begin + trunc_ln1116_6061134315_reg_90979 <= trunc_ln1116_6061134315_fu_76839_p2; + end +end + +always @ (posedge ap_clk) begin + if (((or_ln223_23_fu_80248_p2 == 1'd0) & (icmp_ln208_7_fu_80198_p2 == 1'd0) & (or_ln223_15_reg_91776 == 1'd0) & (ap_ST_fsm_state1058 == ap_CS_fsm))) begin + trunc_ln1116_6261135931_reg_91983 <= trunc_ln1116_6261135931_fu_80300_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1056 == ap_CS_fsm)) begin + trunc_ln708_10_reg_91929 <= {{mul_ln1118_20_fu_80137_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state224 == ap_CS_fsm)) begin + trunc_ln708_11_reg_90557 <= {{mul_ln1118_21_fu_75346_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state805 == ap_CS_fsm)) begin + trunc_ln708_12_reg_91550 <= {{mul_ln1118_22_fu_78806_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state514 == ap_CS_fsm)) begin + trunc_ln708_13_reg_91017 <= {{mul_ln1118_23_fu_77026_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state1095 == ap_CS_fsm)) begin + trunc_ln708_14_reg_92021 <= {{mul_ln1118_24_fu_80487_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state331 == ap_CS_fsm)) begin + trunc_ln708_1_reg_90710 <= {{mul_ln1118_11_fu_75862_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state912 == ap_CS_fsm)) begin + trunc_ln708_2_reg_91709 <= {{mul_ln1118_12_fu_79325_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state80 == ap_CS_fsm)) begin + trunc_ln708_3_reg_90362 <= {{mul_ln1118_13_fu_74623_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state661 == ap_CS_fsm)) begin + trunc_ln708_4_reg_91355 <= {{mul_ln1118_14_fu_78083_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state370 == ap_CS_fsm)) begin + trunc_ln708_5_reg_90822 <= {{mul_ln1118_15_fu_76313_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state185 == ap_CS_fsm)) begin + trunc_ln708_6_reg_90465 <= {{mul_ln1118_16_fu_74996_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state951 == ap_CS_fsm)) begin + trunc_ln708_7_reg_91826 <= {{mul_ln1118_17_fu_79774_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state766 == ap_CS_fsm)) begin + trunc_ln708_8_reg_91458 <= {{mul_ln1118_18_fu_78456_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state475 == ap_CS_fsm)) begin + trunc_ln708_9_reg_90925 <= {{mul_ln1118_19_fu_76676_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state622 == ap_CS_fsm)) begin + trunc_ln708_s_reg_91243 <= {{mul_ln1118_10_fu_77633_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state41 == ap_CS_fsm)) begin + trunc_ln_reg_90250 <= {{mul_ln1118_fu_74172_p2[11:4]}}; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state875 == ap_CS_fsm) & (icmp_ln203_3_fu_78946_p2 == 1'd0))) begin + zext_ln216_11_reg_91631[16 : 0] <= zext_ln216_11_fu_78976_p1[16 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln203_fu_73758_p2 == 1'd0))) begin + zext_ln216_2_reg_90158[16 : 0] <= zext_ln216_2_fu_73788_p1[16 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state585 == ap_CS_fsm) & (icmp_ln203_1_fu_77216_p2 == 1'd0))) begin + zext_ln216_5_reg_91143[16 : 0] <= zext_ln216_5_fu_77246_p1[16 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln203_2_fu_75486_p2 == 1'd0) & (ap_ST_fsm_state294 == ap_CS_fsm))) begin + zext_ln216_8_reg_90638[16 : 0] <= zext_ln216_8_fu_75516_p1[16 : 0]; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_0_V_address0 = acc_0_V_addr_55_reg_98742; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_0_V_address0 = acc_0_V_addr_58_reg_100182; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_0_V_address0 = acc_0_V_addr_52_reg_97933; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_0_V_address0 = acc_0_V_addr_53_reg_94678; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_0_V_address0 = acc_0_V_addr_56_reg_96108; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_0_V_address0 = acc_0_V_addr_50_reg_93872; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_0_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_0_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_0_V_address0 = acc_0_V_addr_51_reg_92673; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_0_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_0_V_address0 = acc_0_V_addr_49_reg_92118; + end else begin + acc_0_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_0_V_address1 = acc_0_V_addr_55_reg_98742; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_0_V_address1 = acc_0_V_addr_58_reg_100182; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_0_V_address1 = acc_0_V_addr_52_reg_97933; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_0_V_address1 = acc_0_V_addr_53_reg_94678; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_0_V_address1 = acc_0_V_addr_56_reg_96108; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_0_V_address1 = acc_0_V_addr_50_reg_93872; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_0_V_address1 = 64'd1; + end else begin + acc_0_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_0_V_ce0 = 1'b1; + end else begin + acc_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_0_V_ce1 = 1'b1; + end else begin + acc_0_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_0_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_0_V_d0 = 8'd0; + end else begin + acc_0_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_0_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_0_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd0 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd0) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd0 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd0) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd0 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd0) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd0 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd0) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd0 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd0) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd0 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_0_V_we0 = 1'b1; + end else begin + acc_0_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd0 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd0) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd0 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd0) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd0 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd0) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd0 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd0) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd0) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_0_V_we1 = 1'b1; + end else begin + acc_0_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_10_V_address0 = acc_10_V_addr_55_reg_98694; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_10_V_address0 = acc_10_V_addr_58_reg_100212; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_10_V_address0 = acc_10_V_addr_52_reg_97963; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_10_V_address0 = acc_10_V_addr_53_reg_94630; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_10_V_address0 = acc_10_V_addr_56_reg_96138; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_10_V_address0 = acc_10_V_addr_50_reg_93902; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_10_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_10_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_10_V_address0 = acc_10_V_addr_51_reg_92698; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_10_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_10_V_address0 = acc_10_V_addr_49_reg_92143; + end else begin + acc_10_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_10_V_address1 = acc_10_V_addr_55_reg_98694; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_10_V_address1 = acc_10_V_addr_58_reg_100212; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_10_V_address1 = acc_10_V_addr_52_reg_97963; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_10_V_address1 = acc_10_V_addr_53_reg_94630; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_10_V_address1 = acc_10_V_addr_56_reg_96138; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_10_V_address1 = acc_10_V_addr_50_reg_93902; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_10_V_address1 = 64'd1; + end else begin + acc_10_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_10_V_ce0 = 1'b1; + end else begin + acc_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_10_V_ce1 = 1'b1; + end else begin + acc_10_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_10_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_10_V_d0 = 8'd0; + end else begin + acc_10_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_10_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_10_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd10 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd10) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd10 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd10) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd10 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd10) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd10 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd10) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd10 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd10) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd10 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_10_V_we0 = 1'b1; + end else begin + acc_10_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd10 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd10) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd10 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd10) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd10 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd10) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd10 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd10) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd10) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_10_V_we1 = 1'b1; + end else begin + acc_10_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_11_V_address0 = acc_11_V_addr_56_reg_98688; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_11_V_address0 = acc_11_V_addr_58_reg_100536; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_11_V_address0 = acc_11_V_addr_53_reg_98155; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_11_V_address0 = acc_11_V_addr_54_reg_94624; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_11_V_address0 = acc_11_V_addr_57_reg_96462; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_11_V_address0 = acc_11_V_addr_50_reg_94094; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_11_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_11_V_address0 = acc_11_V_addr_55_reg_93040; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_11_V_address0 = acc_11_V_addr_51_reg_92863; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_11_V_address0 = acc_11_V_addr_52_reg_92492; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_11_V_address0 = acc_11_V_addr_49_reg_92308; + end else begin + acc_11_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_11_V_address1 = acc_11_V_addr_56_reg_98688; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_11_V_address1 = acc_11_V_addr_58_reg_100536; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_11_V_address1 = acc_11_V_addr_53_reg_98155; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_11_V_address1 = acc_11_V_addr_54_reg_94624; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_11_V_address1 = acc_11_V_addr_57_reg_96462; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_11_V_address1 = acc_11_V_addr_50_reg_94094; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_11_V_address1 = 64'd1; + end else begin + acc_11_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_11_V_ce0 = 1'b1; + end else begin + acc_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_11_V_ce1 = 1'b1; + end else begin + acc_11_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_11_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_11_V_d0 = 8'd254; + end else begin + acc_11_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_11_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_11_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd11) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd11) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd11) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd11) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd11) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd11) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd11) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd11) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_11_V_we0 = 1'b1; + end else begin + acc_11_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd11) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd11) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd11) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd11) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_11_V_we1 = 1'b1; + end else begin + acc_11_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_12_V_address0 = acc_12_V_addr_55_reg_98682; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_12_V_address0 = acc_12_V_addr_58_reg_100218; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_12_V_address0 = acc_12_V_addr_52_reg_97969; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_12_V_address0 = acc_12_V_addr_53_reg_94618; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_12_V_address0 = acc_12_V_addr_56_reg_96144; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_12_V_address0 = acc_12_V_addr_50_reg_93908; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_12_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_12_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_12_V_address0 = acc_12_V_addr_51_reg_92703; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_12_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_12_V_address0 = acc_12_V_addr_49_reg_92148; + end else begin + acc_12_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_12_V_address1 = acc_12_V_addr_55_reg_98682; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_12_V_address1 = acc_12_V_addr_58_reg_100218; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_12_V_address1 = acc_12_V_addr_52_reg_97969; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_12_V_address1 = acc_12_V_addr_53_reg_94618; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_12_V_address1 = acc_12_V_addr_56_reg_96144; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_12_V_address1 = acc_12_V_addr_50_reg_93908; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_12_V_address1 = 64'd1; + end else begin + acc_12_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_12_V_ce0 = 1'b1; + end else begin + acc_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_12_V_ce1 = 1'b1; + end else begin + acc_12_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_12_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_12_V_d0 = 8'd0; + end else begin + acc_12_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_12_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_12_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd12 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd12) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd12 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd12) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd12 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd12) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd12 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd12) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd12 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd12) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd12 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_12_V_we0 = 1'b1; + end else begin + acc_12_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd12 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd12) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd12 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd12) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd12 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd12) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd12 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd12) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd12) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_12_V_we1 = 1'b1; + end else begin + acc_12_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_13_V_address0 = acc_13_V_addr_56_reg_98376; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_13_V_address0 = acc_13_V_addr_58_reg_100530; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_13_V_address0 = acc_13_V_addr_53_reg_98305; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_13_V_address0 = acc_13_V_addr_54_reg_94312; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_13_V_address0 = acc_13_V_addr_57_reg_96456; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_13_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_13_V_address0 = acc_13_V_addr_55_reg_93045; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_13_V_address0 = acc_13_V_addr_51_reg_92868; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_13_V_address0 = acc_13_V_addr_52_reg_92497; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_13_V_address0 = acc_13_V_addr_49_reg_92313; + end else begin + acc_13_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_13_V_address1 = acc_13_V_addr_56_reg_98376; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_13_V_address1 = acc_13_V_addr_58_reg_100530; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_13_V_address1 = acc_13_V_addr_53_reg_98305; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_13_V_address1 = acc_13_V_addr_54_reg_94312; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_13_V_address1 = acc_13_V_addr_57_reg_96456; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_13_V_address1 = acc_13_V_addr_50_reg_94232; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_13_V_address1 = 64'd1; + end else begin + acc_13_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_13_V_ce0 = 1'b1; + end else begin + acc_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_13_V_ce1 = 1'b1; + end else begin + acc_13_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_13_V_d0 = add_ln703_21_fu_85135_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_13_V_d0 = 8'd254; + end else begin + acc_13_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_13_V_d1 = add_ln703_13_fu_84945_p2; + end else begin + acc_13_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd13) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd13) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd13) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd13) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd13) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd13) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd13) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd13) & (ap_ST_fsm_state1712 == ap_CS_fsm)))) begin + acc_13_V_we0 = 1'b1; + end else begin + acc_13_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd13) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd13) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd13) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd13) & (ap_ST_fsm_state1676 == ap_CS_fsm)))) begin + acc_13_V_we1 = 1'b1; + end else begin + acc_13_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_14_V_address0 = acc_14_V_addr_55_reg_98676; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_14_V_address0 = acc_14_V_addr_58_reg_100224; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_14_V_address0 = acc_14_V_addr_52_reg_97975; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_14_V_address0 = acc_14_V_addr_53_reg_94612; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_14_V_address0 = acc_14_V_addr_56_reg_96150; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_14_V_address0 = acc_14_V_addr_50_reg_93914; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_14_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_14_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_14_V_address0 = acc_14_V_addr_51_reg_92708; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_14_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_14_V_address0 = acc_14_V_addr_49_reg_92153; + end else begin + acc_14_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_14_V_address1 = acc_14_V_addr_55_reg_98676; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_14_V_address1 = acc_14_V_addr_58_reg_100224; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_14_V_address1 = acc_14_V_addr_52_reg_97975; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_14_V_address1 = acc_14_V_addr_53_reg_94612; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_14_V_address1 = acc_14_V_addr_56_reg_96150; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_14_V_address1 = acc_14_V_addr_50_reg_93914; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_14_V_address1 = 64'd1; + end else begin + acc_14_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_14_V_ce0 = 1'b1; + end else begin + acc_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_14_V_ce1 = 1'b1; + end else begin + acc_14_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_14_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_14_V_d0 = 8'd0; + end else begin + acc_14_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_14_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_14_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd14 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd14) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd14 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd14) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd14 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd14) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd14 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd14) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd14 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd14) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd14 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_14_V_we0 = 1'b1; + end else begin + acc_14_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd14 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd14) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd14 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd14) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd14 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd14) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd14 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd14) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd14) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_14_V_we1 = 1'b1; + end else begin + acc_14_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_15_V_address0 = acc_15_V_addr_56_reg_98382; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_15_V_address0 = acc_15_V_addr_58_reg_100524; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_15_V_address0 = acc_15_V_addr_53_reg_98299; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_15_V_address0 = acc_15_V_addr_54_reg_94318; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_15_V_address0 = acc_15_V_addr_57_reg_96450; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_15_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_15_V_address0 = acc_15_V_addr_55_reg_93050; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_15_V_address0 = acc_15_V_addr_51_reg_92873; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_15_V_address0 = acc_15_V_addr_52_reg_92502; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_15_V_address0 = acc_15_V_addr_49_reg_92318; + end else begin + acc_15_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_15_V_address1 = acc_15_V_addr_56_reg_98382; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_15_V_address1 = acc_15_V_addr_58_reg_100524; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_15_V_address1 = acc_15_V_addr_53_reg_98299; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_15_V_address1 = acc_15_V_addr_54_reg_94318; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_15_V_address1 = acc_15_V_addr_57_reg_96450; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_15_V_address1 = acc_15_V_addr_50_reg_94227; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_15_V_address1 = 64'd1; + end else begin + acc_15_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_15_V_ce0 = 1'b1; + end else begin + acc_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_15_V_ce1 = 1'b1; + end else begin + acc_15_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_15_V_d0 = add_ln703_21_fu_85135_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_15_V_d0 = 8'd254; + end else begin + acc_15_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_15_V_d1 = add_ln703_13_fu_84945_p2; + end else begin + acc_15_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd15) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd15) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd15) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd15) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd15) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd15) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd15) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd15) & (ap_ST_fsm_state1712 == ap_CS_fsm)))) begin + acc_15_V_we0 = 1'b1; + end else begin + acc_15_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd15) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd15) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd15) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd15) & (ap_ST_fsm_state1676 == ap_CS_fsm)))) begin + acc_15_V_we1 = 1'b1; + end else begin + acc_15_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_16_V_address0 = acc_16_V_addr_55_reg_98670; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_16_V_address0 = acc_16_V_addr_58_reg_100230; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_16_V_address0 = acc_16_V_addr_52_reg_97981; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_16_V_address0 = acc_16_V_addr_53_reg_94606; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_16_V_address0 = acc_16_V_addr_56_reg_96156; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_16_V_address0 = acc_16_V_addr_50_reg_93920; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_16_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_16_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_16_V_address0 = acc_16_V_addr_51_reg_92713; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_16_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_16_V_address0 = acc_16_V_addr_49_reg_92158; + end else begin + acc_16_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_16_V_address1 = acc_16_V_addr_55_reg_98670; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_16_V_address1 = acc_16_V_addr_58_reg_100230; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_16_V_address1 = acc_16_V_addr_52_reg_97981; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_16_V_address1 = acc_16_V_addr_53_reg_94606; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_16_V_address1 = acc_16_V_addr_56_reg_96156; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_16_V_address1 = acc_16_V_addr_50_reg_93920; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_16_V_address1 = 64'd1; + end else begin + acc_16_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_16_V_ce0 = 1'b1; + end else begin + acc_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_16_V_ce1 = 1'b1; + end else begin + acc_16_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_16_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_16_V_d0 = 8'd0; + end else begin + acc_16_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_16_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_16_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd16 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd16) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd16 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd16) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd16 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd16) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd16 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd16) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd16 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd16) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd16 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_16_V_we0 = 1'b1; + end else begin + acc_16_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd16 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd16) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd16 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd16) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd16 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd16) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd16 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd16) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd16) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_16_V_we1 = 1'b1; + end else begin + acc_16_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_17_V_address0 = acc_17_V_addr_56_reg_98664; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_17_V_address0 = acc_17_V_addr_58_reg_100518; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_17_V_address0 = acc_17_V_addr_53_reg_98161; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_17_V_address0 = acc_17_V_addr_54_reg_94600; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_17_V_address0 = acc_17_V_addr_57_reg_96444; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_17_V_address0 = acc_17_V_addr_50_reg_94100; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_17_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_17_V_address0 = acc_17_V_addr_55_reg_93055; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_17_V_address0 = acc_17_V_addr_51_reg_92878; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_17_V_address0 = acc_17_V_addr_52_reg_92507; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_17_V_address0 = acc_17_V_addr_49_reg_92323; + end else begin + acc_17_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_17_V_address1 = acc_17_V_addr_56_reg_98664; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_17_V_address1 = acc_17_V_addr_58_reg_100518; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_17_V_address1 = acc_17_V_addr_53_reg_98161; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_17_V_address1 = acc_17_V_addr_54_reg_94600; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_17_V_address1 = acc_17_V_addr_57_reg_96444; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_17_V_address1 = acc_17_V_addr_50_reg_94100; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_17_V_address1 = 64'd1; + end else begin + acc_17_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_17_V_ce0 = 1'b1; + end else begin + acc_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_17_V_ce1 = 1'b1; + end else begin + acc_17_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_17_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_17_V_d0 = 8'd254; + end else begin + acc_17_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_17_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_17_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd17) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd17) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd17) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd17) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd17) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd17) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd17) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd17) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_17_V_we0 = 1'b1; + end else begin + acc_17_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd17) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd17) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd17) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd17) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_17_V_we1 = 1'b1; + end else begin + acc_17_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_18_V_address0 = acc_18_V_addr_55_reg_98658; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_18_V_address0 = acc_18_V_addr_58_reg_100236; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_18_V_address0 = acc_18_V_addr_52_reg_97987; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_18_V_address0 = acc_18_V_addr_53_reg_94594; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_18_V_address0 = acc_18_V_addr_56_reg_96162; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_18_V_address0 = acc_18_V_addr_50_reg_93926; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_18_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_18_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_18_V_address0 = acc_18_V_addr_51_reg_92718; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_18_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_18_V_address0 = acc_18_V_addr_49_reg_92163; + end else begin + acc_18_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_18_V_address1 = acc_18_V_addr_55_reg_98658; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_18_V_address1 = acc_18_V_addr_58_reg_100236; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_18_V_address1 = acc_18_V_addr_52_reg_97987; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_18_V_address1 = acc_18_V_addr_53_reg_94594; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_18_V_address1 = acc_18_V_addr_56_reg_96162; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_18_V_address1 = acc_18_V_addr_50_reg_93926; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_18_V_address1 = 64'd1; + end else begin + acc_18_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_18_V_ce0 = 1'b1; + end else begin + acc_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_18_V_ce1 = 1'b1; + end else begin + acc_18_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_18_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_18_V_d0 = 8'd0; + end else begin + acc_18_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_18_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_18_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd18 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd18) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd18 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd18) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd18 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd18) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd18 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd18) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd18 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd18) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd18 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_18_V_we0 = 1'b1; + end else begin + acc_18_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd18 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd18) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd18 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd18) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd18 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd18) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd18 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd18) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd18) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_18_V_we1 = 1'b1; + end else begin + acc_18_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_19_V_address0 = acc_19_V_addr_56_reg_98652; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_19_V_address0 = acc_19_V_addr_58_reg_100512; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_19_V_address0 = acc_19_V_addr_53_reg_98167; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_19_V_address0 = acc_19_V_addr_54_reg_94588; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_19_V_address0 = acc_19_V_addr_57_reg_96438; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_19_V_address0 = acc_19_V_addr_50_reg_94106; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_19_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_19_V_address0 = acc_19_V_addr_55_reg_93060; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_19_V_address0 = acc_19_V_addr_51_reg_92883; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_19_V_address0 = acc_19_V_addr_52_reg_92512; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_19_V_address0 = acc_19_V_addr_49_reg_92328; + end else begin + acc_19_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_19_V_address1 = acc_19_V_addr_56_reg_98652; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_19_V_address1 = acc_19_V_addr_58_reg_100512; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_19_V_address1 = acc_19_V_addr_53_reg_98167; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_19_V_address1 = acc_19_V_addr_54_reg_94588; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_19_V_address1 = acc_19_V_addr_57_reg_96438; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_19_V_address1 = acc_19_V_addr_50_reg_94106; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_19_V_address1 = 64'd1; + end else begin + acc_19_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_19_V_ce0 = 1'b1; + end else begin + acc_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_19_V_ce1 = 1'b1; + end else begin + acc_19_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_19_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_19_V_d0 = 8'd254; + end else begin + acc_19_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_19_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_19_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd19) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd19) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd19) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd19) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd19) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd19) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd19) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd19) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_19_V_we0 = 1'b1; + end else begin + acc_19_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd19) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd19) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd19) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd19) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_19_V_we1 = 1'b1; + end else begin + acc_19_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_1_V_address0 = acc_1_V_addr_56_reg_98736; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_1_V_address0 = acc_1_V_addr_58_reg_100566; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_1_V_address0 = acc_1_V_addr_53_reg_98137; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_1_V_address0 = acc_1_V_addr_54_reg_94672; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_1_V_address0 = acc_1_V_addr_57_reg_96492; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_1_V_address0 = acc_1_V_addr_50_reg_94076; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_1_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_1_V_address0 = acc_1_V_addr_55_reg_93015; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_1_V_address0 = acc_1_V_addr_51_reg_92838; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_1_V_address0 = acc_1_V_addr_52_reg_92467; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_1_V_address0 = acc_1_V_addr_49_reg_92283; + end else begin + acc_1_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_1_V_address1 = acc_1_V_addr_56_reg_98736; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_1_V_address1 = acc_1_V_addr_58_reg_100566; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_1_V_address1 = acc_1_V_addr_53_reg_98137; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_1_V_address1 = acc_1_V_addr_54_reg_94672; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_1_V_address1 = acc_1_V_addr_57_reg_96492; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_1_V_address1 = acc_1_V_addr_50_reg_94076; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_1_V_address1 = 64'd1; + end else begin + acc_1_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_1_V_ce0 = 1'b1; + end else begin + acc_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_1_V_ce1 = 1'b1; + end else begin + acc_1_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_1_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_1_V_d0 = 8'd254; + end else begin + acc_1_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_1_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_1_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd1) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd1) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd1) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd1) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd1) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd1) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd1) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd1) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_1_V_we0 = 1'b1; + end else begin + acc_1_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd1) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd1) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd1) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd1) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_1_V_we1 = 1'b1; + end else begin + acc_1_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_20_V_address0 = acc_20_V_addr_55_reg_98646; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_20_V_address0 = acc_20_V_addr_58_reg_100242; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_20_V_address0 = acc_20_V_addr_52_reg_97993; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_20_V_address0 = acc_20_V_addr_53_reg_94582; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_20_V_address0 = acc_20_V_addr_56_reg_96168; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_20_V_address0 = acc_20_V_addr_50_reg_93932; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_20_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_20_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_20_V_address0 = acc_20_V_addr_51_reg_92723; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_20_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_20_V_address0 = acc_20_V_addr_49_reg_92168; + end else begin + acc_20_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_20_V_address1 = acc_20_V_addr_55_reg_98646; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_20_V_address1 = acc_20_V_addr_58_reg_100242; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_20_V_address1 = acc_20_V_addr_52_reg_97993; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_20_V_address1 = acc_20_V_addr_53_reg_94582; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_20_V_address1 = acc_20_V_addr_56_reg_96168; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_20_V_address1 = acc_20_V_addr_50_reg_93932; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_20_V_address1 = 64'd1; + end else begin + acc_20_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_20_V_ce0 = 1'b1; + end else begin + acc_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_20_V_ce1 = 1'b1; + end else begin + acc_20_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_20_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_20_V_d0 = 8'd0; + end else begin + acc_20_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_20_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_20_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd20 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd20) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd20 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd20) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd20 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd20) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd20 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd20) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd20 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd20) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd20 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_20_V_we0 = 1'b1; + end else begin + acc_20_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd20 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd20) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd20 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd20) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd20 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd20) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd20 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd20) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd20) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_20_V_we1 = 1'b1; + end else begin + acc_20_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_21_V_address0 = acc_21_V_addr_56_reg_98388; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_21_V_address0 = acc_21_V_addr_58_reg_100506; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_21_V_address0 = acc_21_V_addr_53_reg_98293; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_21_V_address0 = acc_21_V_addr_54_reg_94324; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_21_V_address0 = acc_21_V_addr_57_reg_96432; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_21_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_21_V_address0 = acc_21_V_addr_55_reg_93065; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_21_V_address0 = acc_21_V_addr_51_reg_92888; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_21_V_address0 = acc_21_V_addr_52_reg_92517; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_21_V_address0 = acc_21_V_addr_49_reg_92333; + end else begin + acc_21_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_21_V_address1 = acc_21_V_addr_56_reg_98388; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_21_V_address1 = acc_21_V_addr_58_reg_100506; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_21_V_address1 = acc_21_V_addr_53_reg_98293; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_21_V_address1 = acc_21_V_addr_54_reg_94324; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_21_V_address1 = acc_21_V_addr_57_reg_96432; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_21_V_address1 = acc_21_V_addr_50_reg_94222; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_21_V_address1 = 64'd1; + end else begin + acc_21_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_21_V_ce0 = 1'b1; + end else begin + acc_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_21_V_ce1 = 1'b1; + end else begin + acc_21_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_21_V_d0 = add_ln703_21_fu_85135_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_21_V_d0 = 8'd254; + end else begin + acc_21_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_21_V_d1 = add_ln703_13_fu_84945_p2; + end else begin + acc_21_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd21) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd21) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd21) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd21) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd21) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd21) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd21) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd21) & (ap_ST_fsm_state1712 == ap_CS_fsm)))) begin + acc_21_V_we0 = 1'b1; + end else begin + acc_21_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd21) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd21) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd21) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd21) & (ap_ST_fsm_state1676 == ap_CS_fsm)))) begin + acc_21_V_we1 = 1'b1; + end else begin + acc_21_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_22_V_address0 = acc_22_V_addr_55_reg_98640; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_22_V_address0 = acc_22_V_addr_58_reg_100248; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_22_V_address0 = acc_22_V_addr_52_reg_97999; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_22_V_address0 = acc_22_V_addr_53_reg_94576; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_22_V_address0 = acc_22_V_addr_56_reg_96174; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_22_V_address0 = acc_22_V_addr_50_reg_93938; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_22_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_22_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_22_V_address0 = acc_22_V_addr_51_reg_92728; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_22_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_22_V_address0 = acc_22_V_addr_49_reg_92173; + end else begin + acc_22_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_22_V_address1 = acc_22_V_addr_55_reg_98640; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_22_V_address1 = acc_22_V_addr_58_reg_100248; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_22_V_address1 = acc_22_V_addr_52_reg_97999; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_22_V_address1 = acc_22_V_addr_53_reg_94576; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_22_V_address1 = acc_22_V_addr_56_reg_96174; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_22_V_address1 = acc_22_V_addr_50_reg_93938; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_22_V_address1 = 64'd1; + end else begin + acc_22_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_22_V_ce0 = 1'b1; + end else begin + acc_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_22_V_ce1 = 1'b1; + end else begin + acc_22_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_22_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_22_V_d0 = 8'd0; + end else begin + acc_22_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_22_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_22_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd22 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd22) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd22 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd22) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd22 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd22) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd22 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd22) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd22 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd22) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd22 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_22_V_we0 = 1'b1; + end else begin + acc_22_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd22 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd22) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd22 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd22) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd22 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd22) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd22 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd22) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd22) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_22_V_we1 = 1'b1; + end else begin + acc_22_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_23_V_address0 = acc_23_V_addr_56_reg_98394; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_23_V_address0 = acc_23_V_addr_58_reg_100500; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_23_V_address0 = acc_23_V_addr_53_reg_98287; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_23_V_address0 = acc_23_V_addr_54_reg_94330; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_23_V_address0 = acc_23_V_addr_57_reg_96426; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_23_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_23_V_address0 = acc_23_V_addr_55_reg_93070; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_23_V_address0 = acc_23_V_addr_51_reg_92893; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_23_V_address0 = acc_23_V_addr_52_reg_92522; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_23_V_address0 = acc_23_V_addr_49_reg_92338; + end else begin + acc_23_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_23_V_address1 = acc_23_V_addr_56_reg_98394; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_23_V_address1 = acc_23_V_addr_58_reg_100500; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_23_V_address1 = acc_23_V_addr_53_reg_98287; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_23_V_address1 = acc_23_V_addr_54_reg_94330; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_23_V_address1 = acc_23_V_addr_57_reg_96426; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_23_V_address1 = acc_23_V_addr_50_reg_94217; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_23_V_address1 = 64'd1; + end else begin + acc_23_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_23_V_ce0 = 1'b1; + end else begin + acc_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_23_V_ce1 = 1'b1; + end else begin + acc_23_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_23_V_d0 = add_ln703_21_fu_85135_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_23_V_d0 = 8'd254; + end else begin + acc_23_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_23_V_d1 = add_ln703_13_fu_84945_p2; + end else begin + acc_23_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd23) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd23) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd23) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd23) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd23) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd23) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd23) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd23) & (ap_ST_fsm_state1712 == ap_CS_fsm)))) begin + acc_23_V_we0 = 1'b1; + end else begin + acc_23_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd23) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd23) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd23) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd23) & (ap_ST_fsm_state1676 == ap_CS_fsm)))) begin + acc_23_V_we1 = 1'b1; + end else begin + acc_23_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_24_V_address0 = acc_24_V_addr_55_reg_98634; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_24_V_address0 = acc_24_V_addr_58_reg_100254; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_24_V_address0 = acc_24_V_addr_52_reg_98005; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_24_V_address0 = acc_24_V_addr_53_reg_94570; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_24_V_address0 = acc_24_V_addr_56_reg_96180; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_24_V_address0 = acc_24_V_addr_50_reg_93944; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_24_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_24_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_24_V_address0 = acc_24_V_addr_51_reg_92733; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_24_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_24_V_address0 = acc_24_V_addr_49_reg_92178; + end else begin + acc_24_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_24_V_address1 = acc_24_V_addr_55_reg_98634; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_24_V_address1 = acc_24_V_addr_58_reg_100254; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_24_V_address1 = acc_24_V_addr_52_reg_98005; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_24_V_address1 = acc_24_V_addr_53_reg_94570; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_24_V_address1 = acc_24_V_addr_56_reg_96180; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_24_V_address1 = acc_24_V_addr_50_reg_93944; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_24_V_address1 = 64'd1; + end else begin + acc_24_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_24_V_ce0 = 1'b1; + end else begin + acc_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_24_V_ce1 = 1'b1; + end else begin + acc_24_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_24_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_24_V_d0 = 8'd0; + end else begin + acc_24_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_24_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_24_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd24 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd24) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd24 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd24) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd24 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd24) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd24 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd24) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd24 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd24) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd24 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_24_V_we0 = 1'b1; + end else begin + acc_24_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd24 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd24) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd24 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd24) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd24 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd24) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd24 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd24) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd24) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_24_V_we1 = 1'b1; + end else begin + acc_24_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_25_V_address0 = acc_25_V_addr_56_reg_98628; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_25_V_address0 = acc_25_V_addr_58_reg_100494; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_25_V_address0 = acc_25_V_addr_53_reg_98173; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_25_V_address0 = acc_25_V_addr_54_reg_94564; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_25_V_address0 = acc_25_V_addr_57_reg_96420; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_25_V_address0 = acc_25_V_addr_50_reg_94112; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_25_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_25_V_address0 = acc_25_V_addr_55_reg_93075; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_25_V_address0 = acc_25_V_addr_51_reg_92898; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_25_V_address0 = acc_25_V_addr_52_reg_92527; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_25_V_address0 = acc_25_V_addr_49_reg_92343; + end else begin + acc_25_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_25_V_address1 = acc_25_V_addr_56_reg_98628; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_25_V_address1 = acc_25_V_addr_58_reg_100494; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_25_V_address1 = acc_25_V_addr_53_reg_98173; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_25_V_address1 = acc_25_V_addr_54_reg_94564; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_25_V_address1 = acc_25_V_addr_57_reg_96420; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_25_V_address1 = acc_25_V_addr_50_reg_94112; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_25_V_address1 = 64'd1; + end else begin + acc_25_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_25_V_ce0 = 1'b1; + end else begin + acc_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_25_V_ce1 = 1'b1; + end else begin + acc_25_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_25_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_25_V_d0 = 8'd254; + end else begin + acc_25_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_25_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_25_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd25) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd25) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd25) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd25) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd25) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd25) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd25) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd25) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_25_V_we0 = 1'b1; + end else begin + acc_25_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd25) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd25) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd25) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd25) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_25_V_we1 = 1'b1; + end else begin + acc_25_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_26_V_address0 = acc_26_V_addr_55_reg_98622; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_26_V_address0 = acc_26_V_addr_58_reg_100260; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_26_V_address0 = acc_26_V_addr_52_reg_98011; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_26_V_address0 = acc_26_V_addr_53_reg_94558; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_26_V_address0 = acc_26_V_addr_56_reg_96186; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_26_V_address0 = acc_26_V_addr_50_reg_93950; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_26_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_26_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_26_V_address0 = acc_26_V_addr_51_reg_92738; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_26_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_26_V_address0 = acc_26_V_addr_49_reg_92183; + end else begin + acc_26_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_26_V_address1 = acc_26_V_addr_55_reg_98622; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_26_V_address1 = acc_26_V_addr_58_reg_100260; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_26_V_address1 = acc_26_V_addr_52_reg_98011; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_26_V_address1 = acc_26_V_addr_53_reg_94558; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_26_V_address1 = acc_26_V_addr_56_reg_96186; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_26_V_address1 = acc_26_V_addr_50_reg_93950; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_26_V_address1 = 64'd1; + end else begin + acc_26_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_26_V_ce0 = 1'b1; + end else begin + acc_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_26_V_ce1 = 1'b1; + end else begin + acc_26_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_26_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_26_V_d0 = 8'd0; + end else begin + acc_26_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_26_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_26_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd26 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd26) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd26 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd26) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd26 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd26) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd26 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd26) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd26 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd26) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd26 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_26_V_we0 = 1'b1; + end else begin + acc_26_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd26 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd26) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd26 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd26) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd26 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd26) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd26 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd26) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd26) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_26_V_we1 = 1'b1; + end else begin + acc_26_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_27_V_address0 = acc_27_V_addr_56_reg_98616; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_27_V_address0 = acc_27_V_addr_58_reg_100488; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_27_V_address0 = acc_27_V_addr_53_reg_98179; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_27_V_address0 = acc_27_V_addr_54_reg_94552; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_27_V_address0 = acc_27_V_addr_57_reg_96414; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_27_V_address0 = acc_27_V_addr_50_reg_94118; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_27_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_27_V_address0 = acc_27_V_addr_55_reg_93080; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_27_V_address0 = acc_27_V_addr_51_reg_92903; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_27_V_address0 = acc_27_V_addr_52_reg_92532; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_27_V_address0 = acc_27_V_addr_49_reg_92348; + end else begin + acc_27_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_27_V_address1 = acc_27_V_addr_56_reg_98616; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_27_V_address1 = acc_27_V_addr_58_reg_100488; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_27_V_address1 = acc_27_V_addr_53_reg_98179; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_27_V_address1 = acc_27_V_addr_54_reg_94552; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_27_V_address1 = acc_27_V_addr_57_reg_96414; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_27_V_address1 = acc_27_V_addr_50_reg_94118; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_27_V_address1 = 64'd1; + end else begin + acc_27_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_27_V_ce0 = 1'b1; + end else begin + acc_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_27_V_ce1 = 1'b1; + end else begin + acc_27_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_27_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_27_V_d0 = 8'd254; + end else begin + acc_27_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_27_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_27_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd27) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd27) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd27) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd27) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd27) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd27) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd27) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd27) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_27_V_we0 = 1'b1; + end else begin + acc_27_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd27) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd27) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd27) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd27) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_27_V_we1 = 1'b1; + end else begin + acc_27_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_28_V_address0 = acc_28_V_addr_55_reg_98610; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_28_V_address0 = acc_28_V_addr_58_reg_100266; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_28_V_address0 = acc_28_V_addr_52_reg_98017; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_28_V_address0 = acc_28_V_addr_53_reg_94546; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_28_V_address0 = acc_28_V_addr_56_reg_96192; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_28_V_address0 = acc_28_V_addr_50_reg_93956; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_28_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_28_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_28_V_address0 = acc_28_V_addr_51_reg_92743; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_28_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_28_V_address0 = acc_28_V_addr_49_reg_92188; + end else begin + acc_28_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_28_V_address1 = acc_28_V_addr_55_reg_98610; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_28_V_address1 = acc_28_V_addr_58_reg_100266; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_28_V_address1 = acc_28_V_addr_52_reg_98017; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_28_V_address1 = acc_28_V_addr_53_reg_94546; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_28_V_address1 = acc_28_V_addr_56_reg_96192; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_28_V_address1 = acc_28_V_addr_50_reg_93956; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_28_V_address1 = 64'd1; + end else begin + acc_28_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_28_V_ce0 = 1'b1; + end else begin + acc_28_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_28_V_ce1 = 1'b1; + end else begin + acc_28_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_28_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_28_V_d0 = 8'd0; + end else begin + acc_28_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_28_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_28_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd28 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd28) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd28 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd28) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd28 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd28) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd28 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd28) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd28 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd28) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd28 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_28_V_we0 = 1'b1; + end else begin + acc_28_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd28 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd28) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd28 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd28) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd28 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd28) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd28 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd28) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd28) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_28_V_we1 = 1'b1; + end else begin + acc_28_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_29_V_address0 = acc_29_V_addr_56_reg_98400; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_29_V_address0 = acc_29_V_addr_58_reg_100482; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_29_V_address0 = acc_29_V_addr_53_reg_98281; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_29_V_address0 = acc_29_V_addr_54_reg_94336; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_29_V_address0 = acc_29_V_addr_57_reg_96408; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_29_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_29_V_address0 = acc_29_V_addr_55_reg_93085; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_29_V_address0 = acc_29_V_addr_51_reg_92908; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_29_V_address0 = acc_29_V_addr_52_reg_92537; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_29_V_address0 = acc_29_V_addr_49_reg_92353; + end else begin + acc_29_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_29_V_address1 = acc_29_V_addr_56_reg_98400; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_29_V_address1 = acc_29_V_addr_58_reg_100482; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_29_V_address1 = acc_29_V_addr_53_reg_98281; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_29_V_address1 = acc_29_V_addr_54_reg_94336; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_29_V_address1 = acc_29_V_addr_57_reg_96408; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_29_V_address1 = acc_29_V_addr_50_reg_94212; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_29_V_address1 = 64'd1; + end else begin + acc_29_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_29_V_ce0 = 1'b1; + end else begin + acc_29_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_29_V_ce1 = 1'b1; + end else begin + acc_29_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_29_V_d0 = add_ln703_21_fu_85135_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_29_V_d0 = 8'd254; + end else begin + acc_29_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_29_V_d1 = add_ln703_13_fu_84945_p2; + end else begin + acc_29_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd29) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd29) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd29) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd29) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd29) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd29) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd29) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd29) & (ap_ST_fsm_state1712 == ap_CS_fsm)))) begin + acc_29_V_we0 = 1'b1; + end else begin + acc_29_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd29) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd29) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd29) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd29) & (ap_ST_fsm_state1676 == ap_CS_fsm)))) begin + acc_29_V_we1 = 1'b1; + end else begin + acc_29_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_2_V_address0 = acc_2_V_addr_55_reg_98730; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_2_V_address0 = acc_2_V_addr_58_reg_100188; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_2_V_address0 = acc_2_V_addr_52_reg_97939; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_2_V_address0 = acc_2_V_addr_53_reg_94666; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_2_V_address0 = acc_2_V_addr_56_reg_96114; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_2_V_address0 = acc_2_V_addr_50_reg_93878; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_2_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_2_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_2_V_address0 = acc_2_V_addr_51_reg_92678; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_2_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_2_V_address0 = acc_2_V_addr_49_reg_92123; + end else begin + acc_2_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_2_V_address1 = acc_2_V_addr_55_reg_98730; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_2_V_address1 = acc_2_V_addr_58_reg_100188; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_2_V_address1 = acc_2_V_addr_52_reg_97939; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_2_V_address1 = acc_2_V_addr_53_reg_94666; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_2_V_address1 = acc_2_V_addr_56_reg_96114; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_2_V_address1 = acc_2_V_addr_50_reg_93878; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_2_V_address1 = 64'd1; + end else begin + acc_2_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_2_V_ce0 = 1'b1; + end else begin + acc_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_2_V_ce1 = 1'b1; + end else begin + acc_2_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_2_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_2_V_d0 = 8'd0; + end else begin + acc_2_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_2_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_2_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd2 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd2) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd2 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd2) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd2 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd2) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd2 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd2) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd2 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd2) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd2 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_2_V_we0 = 1'b1; + end else begin + acc_2_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd2 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd2) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd2 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd2) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd2 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd2) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd2 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd2) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd2) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_2_V_we1 = 1'b1; + end else begin + acc_2_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_30_V_address0 = acc_30_V_addr_55_reg_98604; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_30_V_address0 = acc_30_V_addr_58_reg_100272; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_30_V_address0 = acc_30_V_addr_52_reg_98023; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_30_V_address0 = acc_30_V_addr_53_reg_94540; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_30_V_address0 = acc_30_V_addr_56_reg_96198; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_30_V_address0 = acc_30_V_addr_50_reg_93962; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_30_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_30_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_30_V_address0 = acc_30_V_addr_51_reg_92748; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_30_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_30_V_address0 = acc_30_V_addr_49_reg_92193; + end else begin + acc_30_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_30_V_address1 = acc_30_V_addr_55_reg_98604; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_30_V_address1 = acc_30_V_addr_58_reg_100272; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_30_V_address1 = acc_30_V_addr_52_reg_98023; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_30_V_address1 = acc_30_V_addr_53_reg_94540; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_30_V_address1 = acc_30_V_addr_56_reg_96198; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_30_V_address1 = acc_30_V_addr_50_reg_93962; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_30_V_address1 = 64'd1; + end else begin + acc_30_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_30_V_ce0 = 1'b1; + end else begin + acc_30_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_30_V_ce1 = 1'b1; + end else begin + acc_30_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_30_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_30_V_d0 = 8'd0; + end else begin + acc_30_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_30_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_30_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd30 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd30) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd30 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd30) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd30 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd30) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd30 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd30) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd30 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd30) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd30 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_30_V_we0 = 1'b1; + end else begin + acc_30_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd30 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd30) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd30 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd30) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd30 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd30) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd30 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd30) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd30) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_30_V_we1 = 1'b1; + end else begin + acc_30_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_31_V_address0 = acc_31_V_addr_56_reg_98406; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_31_V_address0 = acc_31_V_addr_58_reg_100476; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_31_V_address0 = acc_31_V_addr_53_reg_98275; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_31_V_address0 = acc_31_V_addr_54_reg_94342; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_31_V_address0 = acc_31_V_addr_57_reg_96402; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_31_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_31_V_address0 = acc_31_V_addr_55_reg_93090; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_31_V_address0 = acc_31_V_addr_51_reg_92913; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_31_V_address0 = acc_31_V_addr_52_reg_92542; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_31_V_address0 = acc_31_V_addr_49_reg_92358; + end else begin + acc_31_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_31_V_address1 = acc_31_V_addr_56_reg_98406; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_31_V_address1 = acc_31_V_addr_58_reg_100476; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_31_V_address1 = acc_31_V_addr_53_reg_98275; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_31_V_address1 = acc_31_V_addr_54_reg_94342; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_31_V_address1 = acc_31_V_addr_57_reg_96402; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_31_V_address1 = acc_31_V_addr_50_reg_94207; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_31_V_address1 = 64'd1; + end else begin + acc_31_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_31_V_ce0 = 1'b1; + end else begin + acc_31_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_31_V_ce1 = 1'b1; + end else begin + acc_31_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_31_V_d0 = add_ln703_21_fu_85135_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_31_V_d0 = 8'd254; + end else begin + acc_31_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_31_V_d1 = add_ln703_13_fu_84945_p2; + end else begin + acc_31_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd31) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd31) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd31) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd31) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd31) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd31) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd31) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd31) & (ap_ST_fsm_state1712 == ap_CS_fsm)))) begin + acc_31_V_we0 = 1'b1; + end else begin + acc_31_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd31) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd31) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd31) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd31) & (ap_ST_fsm_state1676 == ap_CS_fsm)))) begin + acc_31_V_we1 = 1'b1; + end else begin + acc_31_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_32_V_address0 = acc_32_V_addr_55_reg_98598; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_32_V_address0 = acc_32_V_addr_58_reg_100278; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_32_V_address0 = acc_32_V_addr_52_reg_98029; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_32_V_address0 = acc_32_V_addr_53_reg_94534; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_32_V_address0 = acc_32_V_addr_56_reg_96204; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_32_V_address0 = acc_32_V_addr_50_reg_93968; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_32_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_32_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_32_V_address0 = acc_32_V_addr_51_reg_92753; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_32_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_32_V_address0 = acc_32_V_addr_49_reg_92198; + end else begin + acc_32_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_32_V_address1 = acc_32_V_addr_55_reg_98598; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_32_V_address1 = acc_32_V_addr_58_reg_100278; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_32_V_address1 = acc_32_V_addr_52_reg_98029; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_32_V_address1 = acc_32_V_addr_53_reg_94534; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_32_V_address1 = acc_32_V_addr_56_reg_96204; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_32_V_address1 = acc_32_V_addr_50_reg_93968; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_32_V_address1 = 64'd1; + end else begin + acc_32_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_32_V_ce0 = 1'b1; + end else begin + acc_32_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_32_V_ce1 = 1'b1; + end else begin + acc_32_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_32_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_32_V_d0 = 8'd0; + end else begin + acc_32_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_32_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_32_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd32 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd32) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd32 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd32) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd32 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd32) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd32 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd32) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd32 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd32) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd32 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_32_V_we0 = 1'b1; + end else begin + acc_32_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd32 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd32) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd32 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd32) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd32 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd32) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd32 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd32) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd32) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_32_V_we1 = 1'b1; + end else begin + acc_32_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_33_V_address0 = acc_33_V_addr_56_reg_98592; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_33_V_address0 = acc_33_V_addr_58_reg_100470; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_33_V_address0 = acc_33_V_addr_53_reg_98185; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_33_V_address0 = acc_33_V_addr_54_reg_94528; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_33_V_address0 = acc_33_V_addr_57_reg_96396; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_33_V_address0 = acc_33_V_addr_50_reg_94124; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_33_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_33_V_address0 = acc_33_V_addr_55_reg_93095; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_33_V_address0 = acc_33_V_addr_51_reg_92918; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_33_V_address0 = acc_33_V_addr_52_reg_92547; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_33_V_address0 = acc_33_V_addr_49_reg_92363; + end else begin + acc_33_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_33_V_address1 = acc_33_V_addr_56_reg_98592; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_33_V_address1 = acc_33_V_addr_58_reg_100470; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_33_V_address1 = acc_33_V_addr_53_reg_98185; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_33_V_address1 = acc_33_V_addr_54_reg_94528; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_33_V_address1 = acc_33_V_addr_57_reg_96396; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_33_V_address1 = acc_33_V_addr_50_reg_94124; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_33_V_address1 = 64'd1; + end else begin + acc_33_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_33_V_ce0 = 1'b1; + end else begin + acc_33_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_33_V_ce1 = 1'b1; + end else begin + acc_33_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_33_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_33_V_d0 = 8'd254; + end else begin + acc_33_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_33_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_33_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd33) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd33) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd33) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd33) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd33) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd33) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd33) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd33) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_33_V_we0 = 1'b1; + end else begin + acc_33_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd33) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd33) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd33) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd33) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_33_V_we1 = 1'b1; + end else begin + acc_33_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_34_V_address0 = acc_34_V_addr_55_reg_98586; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_34_V_address0 = acc_34_V_addr_58_reg_100284; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_34_V_address0 = acc_34_V_addr_52_reg_98035; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_34_V_address0 = acc_34_V_addr_53_reg_94522; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_34_V_address0 = acc_34_V_addr_56_reg_96210; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_34_V_address0 = acc_34_V_addr_50_reg_93974; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_34_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_34_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_34_V_address0 = acc_34_V_addr_51_reg_92758; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_34_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_34_V_address0 = acc_34_V_addr_49_reg_92203; + end else begin + acc_34_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_34_V_address1 = acc_34_V_addr_55_reg_98586; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_34_V_address1 = acc_34_V_addr_58_reg_100284; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_34_V_address1 = acc_34_V_addr_52_reg_98035; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_34_V_address1 = acc_34_V_addr_53_reg_94522; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_34_V_address1 = acc_34_V_addr_56_reg_96210; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_34_V_address1 = acc_34_V_addr_50_reg_93974; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_34_V_address1 = 64'd1; + end else begin + acc_34_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_34_V_ce0 = 1'b1; + end else begin + acc_34_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_34_V_ce1 = 1'b1; + end else begin + acc_34_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_34_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_34_V_d0 = 8'd0; + end else begin + acc_34_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_34_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_34_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd34 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd34) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd34 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd34) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd34 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd34) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd34 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd34) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd34 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd34) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd34 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_34_V_we0 = 1'b1; + end else begin + acc_34_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd34 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd34) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd34 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd34) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd34 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd34) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd34 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd34) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd34) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_34_V_we1 = 1'b1; + end else begin + acc_34_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_35_V_address0 = acc_35_V_addr_56_reg_98580; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_35_V_address0 = acc_35_V_addr_58_reg_100464; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_35_V_address0 = acc_35_V_addr_53_reg_98191; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_35_V_address0 = acc_35_V_addr_54_reg_94516; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_35_V_address0 = acc_35_V_addr_57_reg_96390; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_35_V_address0 = acc_35_V_addr_50_reg_94130; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_35_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_35_V_address0 = acc_35_V_addr_55_reg_93100; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_35_V_address0 = acc_35_V_addr_51_reg_92923; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_35_V_address0 = acc_35_V_addr_52_reg_92552; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_35_V_address0 = acc_35_V_addr_49_reg_92368; + end else begin + acc_35_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_35_V_address1 = acc_35_V_addr_56_reg_98580; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_35_V_address1 = acc_35_V_addr_58_reg_100464; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_35_V_address1 = acc_35_V_addr_53_reg_98191; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_35_V_address1 = acc_35_V_addr_54_reg_94516; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_35_V_address1 = acc_35_V_addr_57_reg_96390; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_35_V_address1 = acc_35_V_addr_50_reg_94130; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_35_V_address1 = 64'd1; + end else begin + acc_35_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_35_V_ce0 = 1'b1; + end else begin + acc_35_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_35_V_ce1 = 1'b1; + end else begin + acc_35_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_35_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_35_V_d0 = 8'd254; + end else begin + acc_35_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_35_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_35_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd35) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd35) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd35) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd35) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd35) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd35) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd35) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd35) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_35_V_we0 = 1'b1; + end else begin + acc_35_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd35) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd35) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd35) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd35) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_35_V_we1 = 1'b1; + end else begin + acc_35_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_36_V_address0 = acc_36_V_addr_55_reg_98574; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_36_V_address0 = acc_36_V_addr_58_reg_100290; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_36_V_address0 = acc_36_V_addr_52_reg_98041; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_36_V_address0 = acc_36_V_addr_53_reg_94510; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_36_V_address0 = acc_36_V_addr_56_reg_96216; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_36_V_address0 = acc_36_V_addr_50_reg_93980; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_36_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_36_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_36_V_address0 = acc_36_V_addr_51_reg_92763; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_36_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_36_V_address0 = acc_36_V_addr_49_reg_92208; + end else begin + acc_36_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_36_V_address1 = acc_36_V_addr_55_reg_98574; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_36_V_address1 = acc_36_V_addr_58_reg_100290; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_36_V_address1 = acc_36_V_addr_52_reg_98041; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_36_V_address1 = acc_36_V_addr_53_reg_94510; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_36_V_address1 = acc_36_V_addr_56_reg_96216; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_36_V_address1 = acc_36_V_addr_50_reg_93980; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_36_V_address1 = 64'd1; + end else begin + acc_36_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_36_V_ce0 = 1'b1; + end else begin + acc_36_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_36_V_ce1 = 1'b1; + end else begin + acc_36_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_36_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_36_V_d0 = 8'd0; + end else begin + acc_36_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_36_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_36_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd36 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd36) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd36 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd36) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd36 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd36) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd36 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd36) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd36 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd36) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd36 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_36_V_we0 = 1'b1; + end else begin + acc_36_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd36 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd36) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd36 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd36) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd36 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd36) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd36 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd36) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd36) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_36_V_we1 = 1'b1; + end else begin + acc_36_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_37_V_address0 = acc_37_V_addr_56_reg_98412; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_37_V_address0 = acc_37_V_addr_58_reg_100458; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_37_V_address0 = acc_37_V_addr_53_reg_98269; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_37_V_address0 = acc_37_V_addr_54_reg_94348; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_37_V_address0 = acc_37_V_addr_57_reg_96384; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_37_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_37_V_address0 = acc_37_V_addr_55_reg_93105; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_37_V_address0 = acc_37_V_addr_51_reg_92928; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_37_V_address0 = acc_37_V_addr_52_reg_92557; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_37_V_address0 = acc_37_V_addr_49_reg_92373; + end else begin + acc_37_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_37_V_address1 = acc_37_V_addr_56_reg_98412; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_37_V_address1 = acc_37_V_addr_58_reg_100458; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_37_V_address1 = acc_37_V_addr_53_reg_98269; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_37_V_address1 = acc_37_V_addr_54_reg_94348; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_37_V_address1 = acc_37_V_addr_57_reg_96384; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_37_V_address1 = acc_37_V_addr_50_reg_94202; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_37_V_address1 = 64'd1; + end else begin + acc_37_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_37_V_ce0 = 1'b1; + end else begin + acc_37_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_37_V_ce1 = 1'b1; + end else begin + acc_37_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_37_V_d0 = add_ln703_21_fu_85135_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_37_V_d0 = 8'd254; + end else begin + acc_37_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_37_V_d1 = add_ln703_13_fu_84945_p2; + end else begin + acc_37_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd37) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd37) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd37) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd37) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd37) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd37) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd37) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd37) & (ap_ST_fsm_state1712 == ap_CS_fsm)))) begin + acc_37_V_we0 = 1'b1; + end else begin + acc_37_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd37) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd37) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd37) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd37) & (ap_ST_fsm_state1676 == ap_CS_fsm)))) begin + acc_37_V_we1 = 1'b1; + end else begin + acc_37_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_38_V_address0 = acc_38_V_addr_55_reg_98568; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_38_V_address0 = acc_38_V_addr_58_reg_100296; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_38_V_address0 = acc_38_V_addr_52_reg_98047; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_38_V_address0 = acc_38_V_addr_53_reg_94504; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_38_V_address0 = acc_38_V_addr_56_reg_96222; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_38_V_address0 = acc_38_V_addr_50_reg_93986; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_38_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_38_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_38_V_address0 = acc_38_V_addr_51_reg_92768; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_38_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_38_V_address0 = acc_38_V_addr_49_reg_92213; + end else begin + acc_38_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_38_V_address1 = acc_38_V_addr_55_reg_98568; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_38_V_address1 = acc_38_V_addr_58_reg_100296; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_38_V_address1 = acc_38_V_addr_52_reg_98047; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_38_V_address1 = acc_38_V_addr_53_reg_94504; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_38_V_address1 = acc_38_V_addr_56_reg_96222; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_38_V_address1 = acc_38_V_addr_50_reg_93986; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_38_V_address1 = 64'd1; + end else begin + acc_38_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_38_V_ce0 = 1'b1; + end else begin + acc_38_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_38_V_ce1 = 1'b1; + end else begin + acc_38_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_38_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_38_V_d0 = 8'd0; + end else begin + acc_38_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_38_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_38_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd38 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd38) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd38 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd38) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd38 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd38) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd38 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd38) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd38 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd38) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd38 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_38_V_we0 = 1'b1; + end else begin + acc_38_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd38 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd38) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd38 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd38) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd38 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd38) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd38 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd38) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd38) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_38_V_we1 = 1'b1; + end else begin + acc_38_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_39_V_address0 = acc_39_V_addr_56_reg_98418; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_39_V_address0 = acc_39_V_addr_58_reg_100452; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_39_V_address0 = acc_39_V_addr_53_reg_98263; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_39_V_address0 = acc_39_V_addr_54_reg_94354; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_39_V_address0 = acc_39_V_addr_57_reg_96378; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_39_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_39_V_address0 = acc_39_V_addr_55_reg_93110; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_39_V_address0 = acc_39_V_addr_51_reg_92933; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_39_V_address0 = acc_39_V_addr_52_reg_92562; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_39_V_address0 = acc_39_V_addr_49_reg_92378; + end else begin + acc_39_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_39_V_address1 = acc_39_V_addr_56_reg_98418; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_39_V_address1 = acc_39_V_addr_58_reg_100452; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_39_V_address1 = acc_39_V_addr_53_reg_98263; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_39_V_address1 = acc_39_V_addr_54_reg_94354; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_39_V_address1 = acc_39_V_addr_57_reg_96378; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_39_V_address1 = acc_39_V_addr_50_reg_94197; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_39_V_address1 = 64'd1; + end else begin + acc_39_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_39_V_ce0 = 1'b1; + end else begin + acc_39_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_39_V_ce1 = 1'b1; + end else begin + acc_39_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_39_V_d0 = add_ln703_21_fu_85135_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_39_V_d0 = 8'd254; + end else begin + acc_39_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_39_V_d1 = add_ln703_13_fu_84945_p2; + end else begin + acc_39_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd39) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd39) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd39) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd39) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd39) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd39) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd39) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd39) & (ap_ST_fsm_state1712 == ap_CS_fsm)))) begin + acc_39_V_we0 = 1'b1; + end else begin + acc_39_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd39) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd39) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd39) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd39) & (ap_ST_fsm_state1676 == ap_CS_fsm)))) begin + acc_39_V_we1 = 1'b1; + end else begin + acc_39_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_3_V_address0 = acc_3_V_addr_56_reg_98724; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_3_V_address0 = acc_3_V_addr_58_reg_100560; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_3_V_address0 = acc_3_V_addr_53_reg_98143; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_3_V_address0 = acc_3_V_addr_54_reg_94660; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_3_V_address0 = acc_3_V_addr_57_reg_96486; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_3_V_address0 = acc_3_V_addr_50_reg_94082; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_3_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_3_V_address0 = acc_3_V_addr_55_reg_93020; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_3_V_address0 = acc_3_V_addr_51_reg_92843; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_3_V_address0 = acc_3_V_addr_52_reg_92472; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_3_V_address0 = acc_3_V_addr_49_reg_92288; + end else begin + acc_3_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_3_V_address1 = acc_3_V_addr_56_reg_98724; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_3_V_address1 = acc_3_V_addr_58_reg_100560; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_3_V_address1 = acc_3_V_addr_53_reg_98143; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_3_V_address1 = acc_3_V_addr_54_reg_94660; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_3_V_address1 = acc_3_V_addr_57_reg_96486; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_3_V_address1 = acc_3_V_addr_50_reg_94082; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_3_V_address1 = 64'd1; + end else begin + acc_3_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_3_V_ce0 = 1'b1; + end else begin + acc_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_3_V_ce1 = 1'b1; + end else begin + acc_3_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_3_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_3_V_d0 = 8'd254; + end else begin + acc_3_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_3_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_3_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd3) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd3) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd3) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd3) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd3) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd3) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd3) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd3) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_3_V_we0 = 1'b1; + end else begin + acc_3_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd3) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd3) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd3) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd3) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_3_V_we1 = 1'b1; + end else begin + acc_3_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_40_V_address0 = acc_40_V_addr_55_reg_98562; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_40_V_address0 = acc_40_V_addr_58_reg_100302; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_40_V_address0 = acc_40_V_addr_52_reg_98053; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_40_V_address0 = acc_40_V_addr_53_reg_94498; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_40_V_address0 = acc_40_V_addr_56_reg_96228; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_40_V_address0 = acc_40_V_addr_50_reg_93992; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_40_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_40_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_40_V_address0 = acc_40_V_addr_51_reg_92773; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_40_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_40_V_address0 = acc_40_V_addr_49_reg_92218; + end else begin + acc_40_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_40_V_address1 = acc_40_V_addr_55_reg_98562; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_40_V_address1 = acc_40_V_addr_58_reg_100302; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_40_V_address1 = acc_40_V_addr_52_reg_98053; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_40_V_address1 = acc_40_V_addr_53_reg_94498; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_40_V_address1 = acc_40_V_addr_56_reg_96228; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_40_V_address1 = acc_40_V_addr_50_reg_93992; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_40_V_address1 = 64'd1; + end else begin + acc_40_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_40_V_ce0 = 1'b1; + end else begin + acc_40_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_40_V_ce1 = 1'b1; + end else begin + acc_40_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_40_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_40_V_d0 = 8'd0; + end else begin + acc_40_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_40_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_40_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd40 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd40) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd40 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd40) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd40 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd40) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd40 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd40) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd40 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd40) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd40 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_40_V_we0 = 1'b1; + end else begin + acc_40_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd40 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd40) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd40 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd40) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd40 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd40) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd40 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd40) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd40) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_40_V_we1 = 1'b1; + end else begin + acc_40_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_41_V_address0 = acc_41_V_addr_56_reg_98556; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_41_V_address0 = acc_41_V_addr_58_reg_100446; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_41_V_address0 = acc_41_V_addr_53_reg_98197; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_41_V_address0 = acc_41_V_addr_54_reg_94492; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_41_V_address0 = acc_41_V_addr_57_reg_96372; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_41_V_address0 = acc_41_V_addr_50_reg_94136; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_41_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_41_V_address0 = acc_41_V_addr_55_reg_93115; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_41_V_address0 = acc_41_V_addr_51_reg_92938; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_41_V_address0 = acc_41_V_addr_52_reg_92567; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_41_V_address0 = acc_41_V_addr_49_reg_92383; + end else begin + acc_41_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_41_V_address1 = acc_41_V_addr_56_reg_98556; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_41_V_address1 = acc_41_V_addr_58_reg_100446; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_41_V_address1 = acc_41_V_addr_53_reg_98197; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_41_V_address1 = acc_41_V_addr_54_reg_94492; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_41_V_address1 = acc_41_V_addr_57_reg_96372; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_41_V_address1 = acc_41_V_addr_50_reg_94136; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_41_V_address1 = 64'd1; + end else begin + acc_41_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_41_V_ce0 = 1'b1; + end else begin + acc_41_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_41_V_ce1 = 1'b1; + end else begin + acc_41_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_41_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_41_V_d0 = 8'd254; + end else begin + acc_41_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_41_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_41_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd41) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd41) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd41) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd41) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd41) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd41) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd41) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd41) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_41_V_we0 = 1'b1; + end else begin + acc_41_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd41) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd41) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd41) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd41) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_41_V_we1 = 1'b1; + end else begin + acc_41_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_42_V_address0 = acc_42_V_addr_55_reg_98550; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_42_V_address0 = acc_42_V_addr_58_reg_100308; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_42_V_address0 = acc_42_V_addr_52_reg_98059; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_42_V_address0 = acc_42_V_addr_53_reg_94486; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_42_V_address0 = acc_42_V_addr_56_reg_96234; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_42_V_address0 = acc_42_V_addr_50_reg_93998; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_42_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_42_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_42_V_address0 = acc_42_V_addr_51_reg_92778; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_42_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_42_V_address0 = acc_42_V_addr_49_reg_92223; + end else begin + acc_42_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_42_V_address1 = acc_42_V_addr_55_reg_98550; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_42_V_address1 = acc_42_V_addr_58_reg_100308; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_42_V_address1 = acc_42_V_addr_52_reg_98059; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_42_V_address1 = acc_42_V_addr_53_reg_94486; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_42_V_address1 = acc_42_V_addr_56_reg_96234; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_42_V_address1 = acc_42_V_addr_50_reg_93998; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_42_V_address1 = 64'd1; + end else begin + acc_42_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_42_V_ce0 = 1'b1; + end else begin + acc_42_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_42_V_ce1 = 1'b1; + end else begin + acc_42_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_42_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_42_V_d0 = 8'd0; + end else begin + acc_42_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_42_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_42_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd42 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd42) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd42 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd42) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd42 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd42) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd42 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd42) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd42 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd42) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd42 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_42_V_we0 = 1'b1; + end else begin + acc_42_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd42 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd42) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd42 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd42) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd42 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd42) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd42 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd42) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd42) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_42_V_we1 = 1'b1; + end else begin + acc_42_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_43_V_address0 = acc_43_V_addr_56_reg_98544; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_43_V_address0 = acc_43_V_addr_58_reg_100440; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_43_V_address0 = acc_43_V_addr_53_reg_98203; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_43_V_address0 = acc_43_V_addr_54_reg_94480; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_43_V_address0 = acc_43_V_addr_57_reg_96366; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_43_V_address0 = acc_43_V_addr_50_reg_94142; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_43_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_43_V_address0 = acc_43_V_addr_55_reg_93120; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_43_V_address0 = acc_43_V_addr_51_reg_92943; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_43_V_address0 = acc_43_V_addr_52_reg_92572; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_43_V_address0 = acc_43_V_addr_49_reg_92388; + end else begin + acc_43_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_43_V_address1 = acc_43_V_addr_56_reg_98544; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_43_V_address1 = acc_43_V_addr_58_reg_100440; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_43_V_address1 = acc_43_V_addr_53_reg_98203; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_43_V_address1 = acc_43_V_addr_54_reg_94480; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_43_V_address1 = acc_43_V_addr_57_reg_96366; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_43_V_address1 = acc_43_V_addr_50_reg_94142; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_43_V_address1 = 64'd1; + end else begin + acc_43_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_43_V_ce0 = 1'b1; + end else begin + acc_43_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_43_V_ce1 = 1'b1; + end else begin + acc_43_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_43_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_43_V_d0 = 8'd254; + end else begin + acc_43_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_43_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_43_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd43) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd43) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd43) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd43) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd43) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd43) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd43) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd43) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_43_V_we0 = 1'b1; + end else begin + acc_43_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd43) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd43) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd43) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd43) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_43_V_we1 = 1'b1; + end else begin + acc_43_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_44_V_address0 = acc_44_V_addr_55_reg_98538; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_44_V_address0 = acc_44_V_addr_58_reg_100314; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_44_V_address0 = acc_44_V_addr_52_reg_98065; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_44_V_address0 = acc_44_V_addr_53_reg_94474; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_44_V_address0 = acc_44_V_addr_56_reg_96240; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_44_V_address0 = acc_44_V_addr_50_reg_94004; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_44_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_44_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_44_V_address0 = acc_44_V_addr_51_reg_92783; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_44_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_44_V_address0 = acc_44_V_addr_49_reg_92228; + end else begin + acc_44_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_44_V_address1 = acc_44_V_addr_55_reg_98538; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_44_V_address1 = acc_44_V_addr_58_reg_100314; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_44_V_address1 = acc_44_V_addr_52_reg_98065; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_44_V_address1 = acc_44_V_addr_53_reg_94474; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_44_V_address1 = acc_44_V_addr_56_reg_96240; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_44_V_address1 = acc_44_V_addr_50_reg_94004; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_44_V_address1 = 64'd1; + end else begin + acc_44_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_44_V_ce0 = 1'b1; + end else begin + acc_44_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_44_V_ce1 = 1'b1; + end else begin + acc_44_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_44_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_44_V_d0 = 8'd0; + end else begin + acc_44_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_44_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_44_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd44 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd44) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd44 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd44) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd44 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd44) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd44 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd44) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd44 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd44) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd44 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_44_V_we0 = 1'b1; + end else begin + acc_44_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd44 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd44) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd44 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd44) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd44 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd44) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd44 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd44) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd44) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_44_V_we1 = 1'b1; + end else begin + acc_44_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_45_V_address0 = acc_45_V_addr_56_reg_98424; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_45_V_address0 = acc_45_V_addr_58_reg_100434; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_45_V_address0 = acc_45_V_addr_53_reg_98257; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_45_V_address0 = acc_45_V_addr_54_reg_94360; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_45_V_address0 = acc_45_V_addr_57_reg_96360; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_45_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_45_V_address0 = acc_45_V_addr_55_reg_93125; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_45_V_address0 = acc_45_V_addr_51_reg_92948; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_45_V_address0 = acc_45_V_addr_52_reg_92577; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_45_V_address0 = acc_45_V_addr_49_reg_92393; + end else begin + acc_45_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_45_V_address1 = acc_45_V_addr_56_reg_98424; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_45_V_address1 = acc_45_V_addr_58_reg_100434; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_45_V_address1 = acc_45_V_addr_53_reg_98257; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_45_V_address1 = acc_45_V_addr_54_reg_94360; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_45_V_address1 = acc_45_V_addr_57_reg_96360; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_45_V_address1 = acc_45_V_addr_50_reg_94192; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_45_V_address1 = 64'd1; + end else begin + acc_45_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_45_V_ce0 = 1'b1; + end else begin + acc_45_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_45_V_ce1 = 1'b1; + end else begin + acc_45_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_45_V_d0 = add_ln703_21_fu_85135_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_45_V_d0 = 8'd254; + end else begin + acc_45_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_45_V_d1 = add_ln703_13_fu_84945_p2; + end else begin + acc_45_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd45) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd45) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd45) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd45) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd45) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd45) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd45) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd45) & (ap_ST_fsm_state1712 == ap_CS_fsm)))) begin + acc_45_V_we0 = 1'b1; + end else begin + acc_45_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd45) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd45) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd45) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd45) & (ap_ST_fsm_state1676 == ap_CS_fsm)))) begin + acc_45_V_we1 = 1'b1; + end else begin + acc_45_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_46_V_address0 = acc_46_V_addr_55_reg_98532; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_46_V_address0 = acc_46_V_addr_58_reg_100320; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_46_V_address0 = acc_46_V_addr_52_reg_98071; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_46_V_address0 = acc_46_V_addr_53_reg_94468; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_46_V_address0 = acc_46_V_addr_56_reg_96246; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_46_V_address0 = acc_46_V_addr_50_reg_94010; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_46_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_46_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_46_V_address0 = acc_46_V_addr_51_reg_92788; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_46_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_46_V_address0 = acc_46_V_addr_49_reg_92233; + end else begin + acc_46_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_46_V_address1 = acc_46_V_addr_55_reg_98532; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_46_V_address1 = acc_46_V_addr_58_reg_100320; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_46_V_address1 = acc_46_V_addr_52_reg_98071; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_46_V_address1 = acc_46_V_addr_53_reg_94468; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_46_V_address1 = acc_46_V_addr_56_reg_96246; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_46_V_address1 = acc_46_V_addr_50_reg_94010; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_46_V_address1 = 64'd1; + end else begin + acc_46_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_46_V_ce0 = 1'b1; + end else begin + acc_46_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_46_V_ce1 = 1'b1; + end else begin + acc_46_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_46_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_46_V_d0 = 8'd0; + end else begin + acc_46_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_46_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_46_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd46 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd46) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd46 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd46) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd46 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd46) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd46 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd46) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd46 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd46) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd46 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_46_V_we0 = 1'b1; + end else begin + acc_46_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd46 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd46) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd46 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd46) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd46 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd46) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd46 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd46) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd46) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_46_V_we1 = 1'b1; + end else begin + acc_46_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_47_V_address0 = acc_47_V_addr_56_reg_98430; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_47_V_address0 = acc_47_V_addr_58_reg_100428; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_47_V_address0 = acc_47_V_addr_53_reg_98251; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_47_V_address0 = acc_47_V_addr_54_reg_94366; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_47_V_address0 = acc_47_V_addr_57_reg_96354; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_47_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_47_V_address0 = acc_47_V_addr_55_reg_93130; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_47_V_address0 = acc_47_V_addr_51_reg_92953; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_47_V_address0 = acc_47_V_addr_52_reg_92582; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_47_V_address0 = acc_47_V_addr_49_reg_92398; + end else begin + acc_47_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_47_V_address1 = acc_47_V_addr_56_reg_98430; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_47_V_address1 = acc_47_V_addr_58_reg_100428; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_47_V_address1 = acc_47_V_addr_53_reg_98251; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_47_V_address1 = acc_47_V_addr_54_reg_94366; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_47_V_address1 = acc_47_V_addr_57_reg_96354; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_47_V_address1 = acc_47_V_addr_50_reg_94187; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_47_V_address1 = 64'd1; + end else begin + acc_47_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_47_V_ce0 = 1'b1; + end else begin + acc_47_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_47_V_ce1 = 1'b1; + end else begin + acc_47_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_47_V_d0 = add_ln703_21_fu_85135_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_47_V_d0 = 8'd254; + end else begin + acc_47_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_47_V_d1 = add_ln703_13_fu_84945_p2; + end else begin + acc_47_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd47) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd47) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd47) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd47) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd47) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd47) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd47) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd47) & (ap_ST_fsm_state1712 == ap_CS_fsm)))) begin + acc_47_V_we0 = 1'b1; + end else begin + acc_47_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd47) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd47) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd47) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd47) & (ap_ST_fsm_state1676 == ap_CS_fsm)))) begin + acc_47_V_we1 = 1'b1; + end else begin + acc_47_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_48_V_address0 = acc_48_V_addr_55_reg_98526; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_48_V_address0 = acc_48_V_addr_58_reg_100326; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_48_V_address0 = acc_48_V_addr_52_reg_98077; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_48_V_address0 = acc_48_V_addr_53_reg_94462; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_48_V_address0 = acc_48_V_addr_56_reg_96252; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_48_V_address0 = acc_48_V_addr_50_reg_94016; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_48_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_48_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_48_V_address0 = acc_48_V_addr_51_reg_92793; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_48_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_48_V_address0 = acc_48_V_addr_49_reg_92238; + end else begin + acc_48_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_48_V_address1 = acc_48_V_addr_55_reg_98526; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_48_V_address1 = acc_48_V_addr_58_reg_100326; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_48_V_address1 = acc_48_V_addr_52_reg_98077; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_48_V_address1 = acc_48_V_addr_53_reg_94462; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_48_V_address1 = acc_48_V_addr_56_reg_96252; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_48_V_address1 = acc_48_V_addr_50_reg_94016; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_48_V_address1 = 64'd1; + end else begin + acc_48_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_48_V_ce0 = 1'b1; + end else begin + acc_48_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_48_V_ce1 = 1'b1; + end else begin + acc_48_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_48_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_48_V_d0 = 8'd0; + end else begin + acc_48_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_48_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_48_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd48 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd48) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd48 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd48) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd48 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd48) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd48 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd48) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd48 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd48) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd48 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_48_V_we0 = 1'b1; + end else begin + acc_48_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd48 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd48) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd48 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd48) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd48 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd48) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd48 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd48) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd48) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_48_V_we1 = 1'b1; + end else begin + acc_48_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_49_V_address0 = acc_49_V_addr_56_reg_98520; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_49_V_address0 = acc_49_V_addr_58_reg_100422; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_49_V_address0 = acc_49_V_addr_53_reg_98209; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_49_V_address0 = acc_49_V_addr_54_reg_94456; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_49_V_address0 = acc_49_V_addr_57_reg_96348; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_49_V_address0 = acc_49_V_addr_50_reg_94148; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_49_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_49_V_address0 = acc_49_V_addr_55_reg_93135; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_49_V_address0 = acc_49_V_addr_51_reg_92958; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_49_V_address0 = acc_49_V_addr_52_reg_92587; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_49_V_address0 = acc_49_V_addr_49_reg_92403; + end else begin + acc_49_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_49_V_address1 = acc_49_V_addr_56_reg_98520; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_49_V_address1 = acc_49_V_addr_58_reg_100422; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_49_V_address1 = acc_49_V_addr_53_reg_98209; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_49_V_address1 = acc_49_V_addr_54_reg_94456; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_49_V_address1 = acc_49_V_addr_57_reg_96348; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_49_V_address1 = acc_49_V_addr_50_reg_94148; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_49_V_address1 = 64'd1; + end else begin + acc_49_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_49_V_ce0 = 1'b1; + end else begin + acc_49_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_49_V_ce1 = 1'b1; + end else begin + acc_49_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_49_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_49_V_d0 = 8'd254; + end else begin + acc_49_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_49_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_49_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd49) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd49) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd49) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd49) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd49) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd49) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd49) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd49) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_49_V_we0 = 1'b1; + end else begin + acc_49_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd49) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd49) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd49) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd49) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_49_V_we1 = 1'b1; + end else begin + acc_49_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_4_V_address0 = acc_4_V_addr_55_reg_98718; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_4_V_address0 = acc_4_V_addr_58_reg_100194; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_4_V_address0 = acc_4_V_addr_52_reg_97945; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_4_V_address0 = acc_4_V_addr_53_reg_94654; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_4_V_address0 = acc_4_V_addr_56_reg_96120; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_4_V_address0 = acc_4_V_addr_50_reg_93884; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_4_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_4_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_4_V_address0 = acc_4_V_addr_51_reg_92683; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_4_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_4_V_address0 = acc_4_V_addr_49_reg_92128; + end else begin + acc_4_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_4_V_address1 = acc_4_V_addr_55_reg_98718; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_4_V_address1 = acc_4_V_addr_58_reg_100194; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_4_V_address1 = acc_4_V_addr_52_reg_97945; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_4_V_address1 = acc_4_V_addr_53_reg_94654; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_4_V_address1 = acc_4_V_addr_56_reg_96120; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_4_V_address1 = acc_4_V_addr_50_reg_93884; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_4_V_address1 = 64'd1; + end else begin + acc_4_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_4_V_ce0 = 1'b1; + end else begin + acc_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_4_V_ce1 = 1'b1; + end else begin + acc_4_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_4_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_4_V_d0 = 8'd0; + end else begin + acc_4_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_4_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_4_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd4 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd4) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd4 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd4) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd4 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd4) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd4 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd4) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd4 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd4) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd4 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_4_V_we0 = 1'b1; + end else begin + acc_4_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd4 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd4) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd4 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd4) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd4 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd4) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd4 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd4) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd4) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_4_V_we1 = 1'b1; + end else begin + acc_4_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_50_V_address0 = acc_50_V_addr_55_reg_98514; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_50_V_address0 = acc_50_V_addr_58_reg_100332; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_50_V_address0 = acc_50_V_addr_52_reg_98083; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_50_V_address0 = acc_50_V_addr_53_reg_94450; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_50_V_address0 = acc_50_V_addr_56_reg_96258; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_50_V_address0 = acc_50_V_addr_50_reg_94022; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_50_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_50_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_50_V_address0 = acc_50_V_addr_51_reg_92798; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_50_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_50_V_address0 = acc_50_V_addr_49_reg_92243; + end else begin + acc_50_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_50_V_address1 = acc_50_V_addr_55_reg_98514; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_50_V_address1 = acc_50_V_addr_58_reg_100332; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_50_V_address1 = acc_50_V_addr_52_reg_98083; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_50_V_address1 = acc_50_V_addr_53_reg_94450; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_50_V_address1 = acc_50_V_addr_56_reg_96258; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_50_V_address1 = acc_50_V_addr_50_reg_94022; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_50_V_address1 = 64'd1; + end else begin + acc_50_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_50_V_ce0 = 1'b1; + end else begin + acc_50_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_50_V_ce1 = 1'b1; + end else begin + acc_50_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_50_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_50_V_d0 = 8'd0; + end else begin + acc_50_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_50_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_50_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd50 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd50) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd50 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd50) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd50 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd50) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd50 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd50) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd50 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd50) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd50 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_50_V_we0 = 1'b1; + end else begin + acc_50_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd50 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd50) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd50 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd50) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd50 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd50) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd50 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd50) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd50) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_50_V_we1 = 1'b1; + end else begin + acc_50_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_51_V_address0 = acc_51_V_addr_56_reg_98508; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_51_V_address0 = acc_51_V_addr_58_reg_100416; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_51_V_address0 = acc_51_V_addr_53_reg_98215; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_51_V_address0 = acc_51_V_addr_54_reg_94444; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_51_V_address0 = acc_51_V_addr_57_reg_96342; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_51_V_address0 = acc_51_V_addr_50_reg_94154; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_51_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_51_V_address0 = acc_51_V_addr_55_reg_93140; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_51_V_address0 = acc_51_V_addr_51_reg_92963; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_51_V_address0 = acc_51_V_addr_52_reg_92592; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_51_V_address0 = acc_51_V_addr_49_reg_92408; + end else begin + acc_51_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_51_V_address1 = acc_51_V_addr_56_reg_98508; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_51_V_address1 = acc_51_V_addr_58_reg_100416; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_51_V_address1 = acc_51_V_addr_53_reg_98215; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_51_V_address1 = acc_51_V_addr_54_reg_94444; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_51_V_address1 = acc_51_V_addr_57_reg_96342; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_51_V_address1 = acc_51_V_addr_50_reg_94154; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_51_V_address1 = 64'd1; + end else begin + acc_51_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_51_V_ce0 = 1'b1; + end else begin + acc_51_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_51_V_ce1 = 1'b1; + end else begin + acc_51_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_51_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_51_V_d0 = 8'd254; + end else begin + acc_51_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_51_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_51_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd51) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd51) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd51) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd51) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd51) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd51) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd51) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd51) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_51_V_we0 = 1'b1; + end else begin + acc_51_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd51) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd51) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd51) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd51) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_51_V_we1 = 1'b1; + end else begin + acc_51_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_52_V_address0 = acc_52_V_addr_55_reg_98502; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_52_V_address0 = acc_52_V_addr_58_reg_100338; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_52_V_address0 = acc_52_V_addr_52_reg_98089; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_52_V_address0 = acc_52_V_addr_53_reg_94438; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_52_V_address0 = acc_52_V_addr_56_reg_96264; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_52_V_address0 = acc_52_V_addr_50_reg_94028; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_52_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_52_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_52_V_address0 = acc_52_V_addr_51_reg_92803; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_52_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_52_V_address0 = acc_52_V_addr_49_reg_92248; + end else begin + acc_52_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_52_V_address1 = acc_52_V_addr_55_reg_98502; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_52_V_address1 = acc_52_V_addr_58_reg_100338; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_52_V_address1 = acc_52_V_addr_52_reg_98089; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_52_V_address1 = acc_52_V_addr_53_reg_94438; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_52_V_address1 = acc_52_V_addr_56_reg_96264; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_52_V_address1 = acc_52_V_addr_50_reg_94028; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_52_V_address1 = 64'd1; + end else begin + acc_52_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_52_V_ce0 = 1'b1; + end else begin + acc_52_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_52_V_ce1 = 1'b1; + end else begin + acc_52_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_52_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_52_V_d0 = 8'd0; + end else begin + acc_52_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_52_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_52_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd52 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd52) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd52 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd52) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd52 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd52) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd52 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd52) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd52 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd52) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd52 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_52_V_we0 = 1'b1; + end else begin + acc_52_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd52 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd52) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd52 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd52) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd52 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd52) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd52 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd52) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd52) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_52_V_we1 = 1'b1; + end else begin + acc_52_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_53_V_address0 = acc_53_V_addr_56_reg_98436; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_53_V_address0 = acc_53_V_addr_58_reg_100410; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_53_V_address0 = acc_53_V_addr_53_reg_98245; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_53_V_address0 = acc_53_V_addr_54_reg_94372; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_53_V_address0 = acc_53_V_addr_57_reg_96336; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_53_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_53_V_address0 = acc_53_V_addr_55_reg_93145; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_53_V_address0 = acc_53_V_addr_51_reg_92968; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_53_V_address0 = acc_53_V_addr_52_reg_92597; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_53_V_address0 = acc_53_V_addr_49_reg_92413; + end else begin + acc_53_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_53_V_address1 = acc_53_V_addr_56_reg_98436; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_53_V_address1 = acc_53_V_addr_58_reg_100410; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_53_V_address1 = acc_53_V_addr_53_reg_98245; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_53_V_address1 = acc_53_V_addr_54_reg_94372; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_53_V_address1 = acc_53_V_addr_57_reg_96336; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_53_V_address1 = acc_53_V_addr_50_reg_94182; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_53_V_address1 = 64'd1; + end else begin + acc_53_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_53_V_ce0 = 1'b1; + end else begin + acc_53_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_53_V_ce1 = 1'b1; + end else begin + acc_53_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_53_V_d0 = add_ln703_21_fu_85135_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_53_V_d0 = 8'd254; + end else begin + acc_53_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_53_V_d1 = add_ln703_13_fu_84945_p2; + end else begin + acc_53_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd53) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd53) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd53) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd53) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd53) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd53) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd53) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd53) & (ap_ST_fsm_state1712 == ap_CS_fsm)))) begin + acc_53_V_we0 = 1'b1; + end else begin + acc_53_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd53) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd53) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd53) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd53) & (ap_ST_fsm_state1676 == ap_CS_fsm)))) begin + acc_53_V_we1 = 1'b1; + end else begin + acc_53_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_54_V_address0 = acc_54_V_addr_55_reg_98496; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_54_V_address0 = acc_54_V_addr_58_reg_100344; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_54_V_address0 = acc_54_V_addr_52_reg_98095; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_54_V_address0 = acc_54_V_addr_53_reg_94432; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_54_V_address0 = acc_54_V_addr_56_reg_96270; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_54_V_address0 = acc_54_V_addr_50_reg_94034; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_54_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_54_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_54_V_address0 = acc_54_V_addr_51_reg_92808; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_54_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_54_V_address0 = acc_54_V_addr_49_reg_92253; + end else begin + acc_54_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_54_V_address1 = acc_54_V_addr_55_reg_98496; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_54_V_address1 = acc_54_V_addr_58_reg_100344; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_54_V_address1 = acc_54_V_addr_52_reg_98095; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_54_V_address1 = acc_54_V_addr_53_reg_94432; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_54_V_address1 = acc_54_V_addr_56_reg_96270; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_54_V_address1 = acc_54_V_addr_50_reg_94034; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_54_V_address1 = 64'd1; + end else begin + acc_54_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_54_V_ce0 = 1'b1; + end else begin + acc_54_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_54_V_ce1 = 1'b1; + end else begin + acc_54_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_54_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_54_V_d0 = 8'd0; + end else begin + acc_54_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_54_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_54_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd54 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd54) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd54 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd54) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd54 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd54) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd54 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd54) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd54 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd54) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd54 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_54_V_we0 = 1'b1; + end else begin + acc_54_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd54 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd54) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd54 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd54) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd54 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd54) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd54 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd54) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd54) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_54_V_we1 = 1'b1; + end else begin + acc_54_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_55_V_address0 = acc_55_V_addr_56_reg_98442; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_55_V_address0 = acc_55_V_addr_58_reg_100404; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_55_V_address0 = acc_55_V_addr_53_reg_98239; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_55_V_address0 = acc_55_V_addr_54_reg_94378; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_55_V_address0 = acc_55_V_addr_57_reg_96330; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_55_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_55_V_address0 = acc_55_V_addr_55_reg_93150; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_55_V_address0 = acc_55_V_addr_51_reg_92973; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_55_V_address0 = acc_55_V_addr_52_reg_92602; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_55_V_address0 = acc_55_V_addr_49_reg_92418; + end else begin + acc_55_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_55_V_address1 = acc_55_V_addr_56_reg_98442; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_55_V_address1 = acc_55_V_addr_58_reg_100404; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_55_V_address1 = acc_55_V_addr_53_reg_98239; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_55_V_address1 = acc_55_V_addr_54_reg_94378; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_55_V_address1 = acc_55_V_addr_57_reg_96330; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_55_V_address1 = acc_55_V_addr_50_reg_94177; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_55_V_address1 = 64'd1; + end else begin + acc_55_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_55_V_ce0 = 1'b1; + end else begin + acc_55_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_55_V_ce1 = 1'b1; + end else begin + acc_55_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_55_V_d0 = add_ln703_21_fu_85135_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_55_V_d0 = 8'd254; + end else begin + acc_55_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_55_V_d1 = add_ln703_13_fu_84945_p2; + end else begin + acc_55_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd55) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd55) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd55) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd55) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd55) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd55) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd55) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd55) & (ap_ST_fsm_state1712 == ap_CS_fsm)))) begin + acc_55_V_we0 = 1'b1; + end else begin + acc_55_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd55) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd55) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd55) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd55) & (ap_ST_fsm_state1676 == ap_CS_fsm)))) begin + acc_55_V_we1 = 1'b1; + end else begin + acc_55_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_56_V_address0 = acc_56_V_addr_55_reg_98490; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_56_V_address0 = acc_56_V_addr_58_reg_100350; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_56_V_address0 = acc_56_V_addr_52_reg_98101; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_56_V_address0 = acc_56_V_addr_53_reg_94426; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_56_V_address0 = acc_56_V_addr_56_reg_96276; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_56_V_address0 = acc_56_V_addr_50_reg_94040; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_56_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_56_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_56_V_address0 = acc_56_V_addr_51_reg_92813; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_56_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_56_V_address0 = acc_56_V_addr_49_reg_92258; + end else begin + acc_56_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_56_V_address1 = acc_56_V_addr_55_reg_98490; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_56_V_address1 = acc_56_V_addr_58_reg_100350; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_56_V_address1 = acc_56_V_addr_52_reg_98101; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_56_V_address1 = acc_56_V_addr_53_reg_94426; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_56_V_address1 = acc_56_V_addr_56_reg_96276; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_56_V_address1 = acc_56_V_addr_50_reg_94040; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_56_V_address1 = 64'd1; + end else begin + acc_56_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_56_V_ce0 = 1'b1; + end else begin + acc_56_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_56_V_ce1 = 1'b1; + end else begin + acc_56_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_56_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_56_V_d0 = 8'd0; + end else begin + acc_56_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_56_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_56_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd56 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd56) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd56 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd56) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd56 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd56) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd56 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd56) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd56 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd56) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd56 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_56_V_we0 = 1'b1; + end else begin + acc_56_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd56 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd56) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd56 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd56) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd56 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd56) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd56 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd56) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd56) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_56_V_we1 = 1'b1; + end else begin + acc_56_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_57_V_address0 = acc_57_V_addr_56_reg_98484; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_57_V_address0 = acc_57_V_addr_58_reg_100398; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_57_V_address0 = acc_57_V_addr_53_reg_98221; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_57_V_address0 = acc_57_V_addr_54_reg_94420; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_57_V_address0 = acc_57_V_addr_57_reg_96324; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_57_V_address0 = acc_57_V_addr_50_reg_94160; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_57_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_57_V_address0 = acc_57_V_addr_55_reg_93155; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_57_V_address0 = acc_57_V_addr_51_reg_92978; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_57_V_address0 = acc_57_V_addr_52_reg_92607; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_57_V_address0 = acc_57_V_addr_49_reg_92423; + end else begin + acc_57_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_57_V_address1 = acc_57_V_addr_56_reg_98484; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_57_V_address1 = acc_57_V_addr_58_reg_100398; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_57_V_address1 = acc_57_V_addr_53_reg_98221; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_57_V_address1 = acc_57_V_addr_54_reg_94420; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_57_V_address1 = acc_57_V_addr_57_reg_96324; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_57_V_address1 = acc_57_V_addr_50_reg_94160; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_57_V_address1 = 64'd1; + end else begin + acc_57_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_57_V_ce0 = 1'b1; + end else begin + acc_57_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_57_V_ce1 = 1'b1; + end else begin + acc_57_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_57_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_57_V_d0 = 8'd254; + end else begin + acc_57_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_57_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_57_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd57) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd57) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd57) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd57) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd57) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd57) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd57) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd57) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_57_V_we0 = 1'b1; + end else begin + acc_57_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd57) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd57) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd57) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd57) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_57_V_we1 = 1'b1; + end else begin + acc_57_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_58_V_address0 = acc_58_V_addr_55_reg_98478; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_58_V_address0 = acc_58_V_addr_58_reg_100356; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_58_V_address0 = acc_58_V_addr_52_reg_98107; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_58_V_address0 = acc_58_V_addr_53_reg_94414; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_58_V_address0 = acc_58_V_addr_56_reg_96282; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_58_V_address0 = acc_58_V_addr_50_reg_94046; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_58_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_58_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_58_V_address0 = acc_58_V_addr_51_reg_92818; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_58_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_58_V_address0 = acc_58_V_addr_49_reg_92263; + end else begin + acc_58_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_58_V_address1 = acc_58_V_addr_55_reg_98478; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_58_V_address1 = acc_58_V_addr_58_reg_100356; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_58_V_address1 = acc_58_V_addr_52_reg_98107; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_58_V_address1 = acc_58_V_addr_53_reg_94414; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_58_V_address1 = acc_58_V_addr_56_reg_96282; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_58_V_address1 = acc_58_V_addr_50_reg_94046; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_58_V_address1 = 64'd1; + end else begin + acc_58_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_58_V_ce0 = 1'b1; + end else begin + acc_58_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_58_V_ce1 = 1'b1; + end else begin + acc_58_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_58_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_58_V_d0 = 8'd0; + end else begin + acc_58_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_58_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_58_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd58 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd58) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd58 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd58) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd58 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd58) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd58 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd58) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd58 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd58) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd58 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_58_V_we0 = 1'b1; + end else begin + acc_58_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd58 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd58) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd58 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd58) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd58 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd58) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd58 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd58) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd58) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_58_V_we1 = 1'b1; + end else begin + acc_58_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_59_V_address0 = acc_59_V_addr_56_reg_98472; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_59_V_address0 = acc_59_V_addr_58_reg_100392; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_59_V_address0 = acc_59_V_addr_53_reg_98227; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_59_V_address0 = acc_59_V_addr_54_reg_94408; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_59_V_address0 = acc_59_V_addr_57_reg_96318; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_59_V_address0 = acc_59_V_addr_50_reg_94166; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_59_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_59_V_address0 = acc_59_V_addr_55_reg_93160; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_59_V_address0 = acc_59_V_addr_51_reg_92983; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_59_V_address0 = acc_59_V_addr_52_reg_92612; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_59_V_address0 = acc_59_V_addr_49_reg_92428; + end else begin + acc_59_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_59_V_address1 = acc_59_V_addr_56_reg_98472; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_59_V_address1 = acc_59_V_addr_58_reg_100392; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_59_V_address1 = acc_59_V_addr_53_reg_98227; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_59_V_address1 = acc_59_V_addr_54_reg_94408; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_59_V_address1 = acc_59_V_addr_57_reg_96318; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_59_V_address1 = acc_59_V_addr_50_reg_94166; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_59_V_address1 = 64'd1; + end else begin + acc_59_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_59_V_ce0 = 1'b1; + end else begin + acc_59_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_59_V_ce1 = 1'b1; + end else begin + acc_59_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_59_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_59_V_d0 = 8'd254; + end else begin + acc_59_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_59_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_59_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd59) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd59) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd59) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd59) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd59) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd59) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd59) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd59) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_59_V_we0 = 1'b1; + end else begin + acc_59_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd59) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd59) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd59) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd59) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_59_V_we1 = 1'b1; + end else begin + acc_59_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_5_V_address0 = acc_5_V_addr_56_reg_98364; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_5_V_address0 = acc_5_V_addr_58_reg_100554; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_5_V_address0 = acc_5_V_addr_53_reg_98317; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_5_V_address0 = acc_5_V_addr_54_reg_94300; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_5_V_address0 = acc_5_V_addr_57_reg_96480; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_5_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_5_V_address0 = acc_5_V_addr_55_reg_93025; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_5_V_address0 = acc_5_V_addr_51_reg_92848; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_5_V_address0 = acc_5_V_addr_52_reg_92477; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_5_V_address0 = acc_5_V_addr_49_reg_92293; + end else begin + acc_5_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_5_V_address1 = acc_5_V_addr_56_reg_98364; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_5_V_address1 = acc_5_V_addr_58_reg_100554; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_5_V_address1 = acc_5_V_addr_53_reg_98317; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_5_V_address1 = acc_5_V_addr_54_reg_94300; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_5_V_address1 = acc_5_V_addr_57_reg_96480; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_5_V_address1 = acc_5_V_addr_50_reg_94242; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_5_V_address1 = 64'd1; + end else begin + acc_5_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_5_V_ce0 = 1'b1; + end else begin + acc_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_5_V_ce1 = 1'b1; + end else begin + acc_5_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_5_V_d0 = add_ln703_21_fu_85135_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_5_V_d0 = 8'd254; + end else begin + acc_5_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_5_V_d1 = add_ln703_13_fu_84945_p2; + end else begin + acc_5_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd5) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd5) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd5) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd5) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd5) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd5) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd5) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd5) & (ap_ST_fsm_state1712 == ap_CS_fsm)))) begin + acc_5_V_we0 = 1'b1; + end else begin + acc_5_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd5) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd5) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd5) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd5) & (ap_ST_fsm_state1676 == ap_CS_fsm)))) begin + acc_5_V_we1 = 1'b1; + end else begin + acc_5_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_60_V_address0 = acc_60_V_addr_55_reg_98466; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_60_V_address0 = acc_60_V_addr_58_reg_100362; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_60_V_address0 = acc_60_V_addr_52_reg_98113; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_60_V_address0 = acc_60_V_addr_53_reg_94402; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_60_V_address0 = acc_60_V_addr_56_reg_96288; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_60_V_address0 = acc_60_V_addr_50_reg_94052; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_60_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_60_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_60_V_address0 = acc_60_V_addr_51_reg_92823; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_60_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_60_V_address0 = acc_60_V_addr_49_reg_92268; + end else begin + acc_60_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_60_V_address1 = acc_60_V_addr_55_reg_98466; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_60_V_address1 = acc_60_V_addr_58_reg_100362; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_60_V_address1 = acc_60_V_addr_52_reg_98113; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_60_V_address1 = acc_60_V_addr_53_reg_94402; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_60_V_address1 = acc_60_V_addr_56_reg_96288; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_60_V_address1 = acc_60_V_addr_50_reg_94052; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_60_V_address1 = 64'd1; + end else begin + acc_60_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_60_V_ce0 = 1'b1; + end else begin + acc_60_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_60_V_ce1 = 1'b1; + end else begin + acc_60_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_60_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_60_V_d0 = 8'd0; + end else begin + acc_60_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_60_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_60_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd60 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd60) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd60 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd60) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd60 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd60) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd60 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd60) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd60 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd60) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd60 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_60_V_we0 = 1'b1; + end else begin + acc_60_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd60 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd60) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd60 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd60) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd60 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd60) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd60 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd60) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd60) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_60_V_we1 = 1'b1; + end else begin + acc_60_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_61_V_address0 = acc_61_V_addr_56_reg_98448; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_61_V_address0 = acc_61_V_addr_58_reg_100386; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_61_V_address0 = acc_61_V_addr_53_reg_98233; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_61_V_address0 = acc_61_V_addr_54_reg_94384; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_61_V_address0 = acc_61_V_addr_57_reg_96312; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_61_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_61_V_address0 = acc_61_V_addr_55_reg_93165; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_61_V_address0 = acc_61_V_addr_51_reg_92988; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_61_V_address0 = acc_61_V_addr_52_reg_92617; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_61_V_address0 = acc_61_V_addr_49_reg_92433; + end else begin + acc_61_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_61_V_address1 = acc_61_V_addr_56_reg_98448; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_61_V_address1 = acc_61_V_addr_58_reg_100386; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_61_V_address1 = acc_61_V_addr_53_reg_98233; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_61_V_address1 = acc_61_V_addr_54_reg_94384; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_61_V_address1 = acc_61_V_addr_57_reg_96312; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_61_V_address1 = acc_61_V_addr_50_reg_94172; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_61_V_address1 = 64'd1; + end else begin + acc_61_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_61_V_ce0 = 1'b1; + end else begin + acc_61_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_61_V_ce1 = 1'b1; + end else begin + acc_61_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_61_V_d0 = add_ln703_21_fu_85135_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_61_V_d0 = 8'd254; + end else begin + acc_61_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_61_V_d1 = add_ln703_13_fu_84945_p2; + end else begin + acc_61_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd61) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd61) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd61) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd61) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd61) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd61) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd61) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd61) & (ap_ST_fsm_state1712 == ap_CS_fsm)))) begin + acc_61_V_we0 = 1'b1; + end else begin + acc_61_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd61) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd61) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd61) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd61) & (ap_ST_fsm_state1676 == ap_CS_fsm)))) begin + acc_61_V_we1 = 1'b1; + end else begin + acc_61_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_62_V_address0 = acc_62_V_addr_55_reg_98460; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_62_V_address0 = acc_62_V_addr_58_reg_100368; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_62_V_address0 = acc_62_V_addr_52_reg_98119; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_62_V_address0 = acc_62_V_addr_53_reg_94396; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_62_V_address0 = acc_62_V_addr_56_reg_96294; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_62_V_address0 = acc_62_V_addr_50_reg_94058; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_62_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_62_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_62_V_address0 = acc_62_V_addr_51_reg_92828; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_62_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_62_V_address0 = acc_62_V_addr_49_reg_92273; + end else begin + acc_62_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_62_V_address1 = acc_62_V_addr_55_reg_98460; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_62_V_address1 = acc_62_V_addr_58_reg_100368; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_62_V_address1 = acc_62_V_addr_52_reg_98119; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_62_V_address1 = acc_62_V_addr_53_reg_94396; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_62_V_address1 = acc_62_V_addr_56_reg_96294; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_62_V_address1 = acc_62_V_addr_50_reg_94058; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_62_V_address1 = 64'd1; + end else begin + acc_62_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_62_V_ce0 = 1'b1; + end else begin + acc_62_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_62_V_ce1 = 1'b1; + end else begin + acc_62_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_62_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_62_V_d0 = 8'd0; + end else begin + acc_62_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_62_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_62_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd62 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd62) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd62 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd62) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd62 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd62) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd62 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd62) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd62 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd62) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd62 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_62_V_we0 = 1'b1; + end else begin + acc_62_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd62 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd62) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd62 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd62) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd62 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd62) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd62 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd62) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd62) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_62_V_we1 = 1'b1; + end else begin + acc_62_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_57_reg_98454; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_60_reg_100374; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_53_reg_98125; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_54_reg_94390; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_58_reg_96300; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_50_reg_94064; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_63_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1182 == ap_CS_fsm)) begin + acc_63_V_address0 = acc_63_V_addr_55_reg_93170; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_63_V_address0 = zext_ln203_15_fu_81363_p1; + end else if (((ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_51_reg_92833; + end else if ((ap_ST_fsm_state1173 == ap_CS_fsm)) begin + acc_63_V_address0 = acc_63_V_addr_52_reg_92622; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_63_V_address0 = zext_ln203_10_fu_80987_p1; + end else if (((ap_ST_fsm_state1169 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_63_V_address0 = acc_63_V_addr_49_reg_92278; + end else begin + acc_63_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_63_V_address1 = acc_63_V_addr_57_reg_98454; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_63_V_address1 = acc_63_V_addr_60_reg_100374; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_63_V_address1 = acc_63_V_addr_53_reg_98125; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_63_V_address1 = acc_63_V_addr_54_reg_94390; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_63_V_address1 = acc_63_V_addr_58_reg_96300; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_63_V_address1 = acc_63_V_addr_50_reg_94064; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_63_V_address1 = 64'd1; + end else begin + acc_63_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1182 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1173 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1169 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_63_V_ce0 = 1'b1; + end else begin + acc_63_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_63_V_ce1 = 1'b1; + end else begin + acc_63_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_21_fu_85135_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_63_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1182 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1173 == ap_CS_fsm) | (ap_ST_fsm_state1169 == ap_CS_fsm))) begin + acc_63_V_d0 = 8'd254; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_63_V_d0 = 8'd0; + end else begin + acc_63_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_13_fu_84945_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_8_fu_82854_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_7_fu_82359_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_63_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_63_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1182 == ap_CS_fsm) | (ap_ST_fsm_state1178 == ap_CS_fsm) | (ap_ST_fsm_state1173 == ap_CS_fsm) | (ap_ST_fsm_state1169 == ap_CS_fsm) | (~(or_ln1265_5_reg_100772 == 6'd55) & ~(or_ln1265_5_reg_100772 == 6'd13) & ~(or_ln1265_5_reg_100772 == 6'd45) & ~(or_ln1265_5_reg_100772 == 6'd37) & ~(or_ln1265_5_reg_100772 == 6'd53) & ~(or_ln1265_5_reg_100772 == 6'd21) & ~(or_ln1265_5_reg_100772 == 6'd23) & ~(or_ln1265_5_reg_100772 == 6'd7) & ~(or_ln1265_5_reg_100772 == 6'd15) & ~(or_ln1265_5_reg_100772 == 6'd5) & ~(or_ln1265_5_reg_100772 == 6'd39) & ~(or_ln1265_5_reg_100772 == 6'd29) & ~(or_ln1265_5_reg_100772 == 6'd61) & ~(or_ln1265_5_reg_100772 == 6'd47) & ~(or_ln1265_5_reg_100772 == 6'd31) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_1_reg_100172) & ~(6'd62 == add_ln1265_1_reg_100172) & ~(6'd2 == add_ln1265_1_reg_100172) & ~(6'd32 == add_ln1265_1_reg_100172) & ~(6'd4 == add_ln1265_1_reg_100172) & ~(6'd60 == add_ln1265_1_reg_100172) & ~(6'd6 == add_ln1265_1_reg_100172) & ~(6'd46 == add_ln1265_1_reg_100172) & ~(6'd8 == add_ln1265_1_reg_100172) & ~(6'd58 == add_ln1265_1_reg_100172) & ~(6'd10 == add_ln1265_1_reg_100172) & ~(6'd34 == add_ln1265_1_reg_100172) & ~(6'd12 == add_ln1265_1_reg_100172) & ~(6'd56 == add_ln1265_1_reg_100172) & ~(6'd14 == add_ln1265_1_reg_100172) & ~(6'd40 == add_ln1265_1_reg_100172) & ~(6'd16 == add_ln1265_1_reg_100172) & ~(6'd54 == add_ln1265_1_reg_100172) & ~(6'd18 == add_ln1265_1_reg_100172) & ~(6'd36 == add_ln1265_1_reg_100172) & ~(6'd20 == add_ln1265_1_reg_100172) & ~(6'd52 == add_ln1265_1_reg_100172) & ~(6'd22 == add_ln1265_1_reg_100172) & ~(6'd44 == add_ln1265_1_reg_100172) & ~(6'd24 == add_ln1265_1_reg_100172) & ~(6'd50 == add_ln1265_1_reg_100172) & ~(6'd26 == add_ln1265_1_reg_100172) & ~(6'd38 == add_ln1265_1_reg_100172) & ~(6'd28 == add_ln1265_1_reg_100172) & ~(6'd48 == add_ln1265_1_reg_100172) & ~(6'd30 == add_ln1265_1_reg_100172) & ~(6'd42 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | (~(or_ln1265_3_reg_98943 == 6'd51) & ~(or_ln1265_3_reg_98943 == 6'd19) & ~(or_ln1265_3_reg_98943 == 6'd41) & ~(or_ln1265_3_reg_98943 == 6'd25) & ~(or_ln1265_3_reg_98943 == 6'd11) & ~(or_ln1265_3_reg_98943 == 6'd57) & ~(or_ln1265_3_reg_98943 == 6'd9) & ~(or_ln1265_3_reg_98943 == 6'd33) & ~(or_ln1265_3_reg_98943 == 6'd49) & ~(or_ln1265_3_reg_98943 == 6'd59) & ~(or_ln1265_3_reg_98943 == 6'd27) & ~(or_ln1265_3_reg_98943 == 6'd43) & ~(or_ln1265_3_reg_98943 == 6'd3) & ~(or_ln1265_3_reg_98943 == 6'd17) & ~(or_ln1265_3_reg_98943 == 6'd1) & ~(or_ln1265_3_reg_98943 == 6'd35) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | (~(or_ln1265_1_reg_98331 == 6'd0) & ~(or_ln1265_1_reg_98331 == 6'd62) & ~(or_ln1265_1_reg_98331 == 6'd2) & ~(or_ln1265_1_reg_98331 == 6'd32) & ~(or_ln1265_1_reg_98331 == 6'd4) & ~(or_ln1265_1_reg_98331 == 6'd60) & ~(or_ln1265_1_reg_98331 == 6'd6) & ~(or_ln1265_1_reg_98331 == 6'd46) & ~(or_ln1265_1_reg_98331 == 6'd8) & ~(or_ln1265_1_reg_98331 == 6'd58) & ~(or_ln1265_1_reg_98331 == 6'd10) & ~(or_ln1265_1_reg_98331 == 6'd34) & ~(or_ln1265_1_reg_98331 == 6'd12) & ~(or_ln1265_1_reg_98331 == 6'd56) & ~(or_ln1265_1_reg_98331 == 6'd14) & ~(or_ln1265_1_reg_98331 == 6'd40) & ~(or_ln1265_1_reg_98331 == 6'd16) & ~(or_ln1265_1_reg_98331 == 6'd54) & ~(or_ln1265_1_reg_98331 == 6'd18) & ~(or_ln1265_1_reg_98331 == 6'd36) & ~(or_ln1265_1_reg_98331 == 6'd20) & ~(or_ln1265_1_reg_98331 == 6'd52) & ~(or_ln1265_1_reg_98331 == 6'd22) & ~(or_ln1265_1_reg_98331 == 6'd44) & ~(or_ln1265_1_reg_98331 == 6'd24) & ~(or_ln1265_1_reg_98331 == 6'd50) & ~(or_ln1265_1_reg_98331 == 6'd26) & ~(or_ln1265_1_reg_98331 == 6'd38) & ~(or_ln1265_1_reg_98331 == 6'd28) & ~(or_ln1265_1_reg_98331 == 6'd48) & ~(or_ln1265_1_reg_98331 == 6'd30) & ~(or_ln1265_1_reg_98331 == 6'd42) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | (~(or_ln1265_4_reg_96698 == 6'd55) & ~(or_ln1265_4_reg_96698 == 6'd13) & ~(or_ln1265_4_reg_96698 == 6'd45) & ~(or_ln1265_4_reg_96698 == 6'd37) & ~(or_ln1265_4_reg_96698 == 6'd53) & ~(or_ln1265_4_reg_96698 == 6'd21) & ~(or_ln1265_4_reg_96698 == 6'd23) & ~(or_ln1265_4_reg_96698 == 6'd7) & ~(or_ln1265_4_reg_96698 == 6'd15) & ~(or_ln1265_4_reg_96698 == 6'd5) & ~(or_ln1265_4_reg_96698 == 6'd39) & ~(or_ln1265_4_reg_96698 == 6'd29) & ~(or_ln1265_4_reg_96698 == 6'd61) & ~(or_ln1265_4_reg_96698 == 6'd47) & ~(or_ln1265_4_reg_96698 == 6'd31) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_reg_96098) & ~(6'd62 == add_ln1265_reg_96098) & ~(6'd2 == add_ln1265_reg_96098) & ~(6'd32 == add_ln1265_reg_96098) & ~(6'd4 == add_ln1265_reg_96098) & ~(6'd60 == add_ln1265_reg_96098) & ~(6'd6 == add_ln1265_reg_96098) & ~(6'd46 == add_ln1265_reg_96098) & ~(6'd8 == add_ln1265_reg_96098) & ~(6'd58 == add_ln1265_reg_96098) & ~(6'd10 == add_ln1265_reg_96098) & ~(6'd34 == add_ln1265_reg_96098) & ~(6'd12 == add_ln1265_reg_96098) & ~(6'd56 == add_ln1265_reg_96098) & ~(6'd14 == add_ln1265_reg_96098) & ~(6'd40 == add_ln1265_reg_96098) & ~(6'd16 == add_ln1265_reg_96098) & ~(6'd54 == add_ln1265_reg_96098) & ~(6'd18 == add_ln1265_reg_96098) & ~(6'd36 == add_ln1265_reg_96098) & ~(6'd20 == add_ln1265_reg_96098) & ~(6'd52 == add_ln1265_reg_96098) & ~(6'd22 == add_ln1265_reg_96098) & ~(6'd44 == add_ln1265_reg_96098) & ~(6'd24 == add_ln1265_reg_96098) & ~(6'd50 == add_ln1265_reg_96098) & ~(6'd26 == add_ln1265_reg_96098) & ~(6'd38 == add_ln1265_reg_96098) & ~(6'd28 == add_ln1265_reg_96098) & ~(6'd48 == add_ln1265_reg_96098) & ~(6'd30 == add_ln1265_reg_96098) & ~(6'd42 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | (~(or_ln1265_2_reg_94874 == 6'd51) & ~(or_ln1265_2_reg_94874 == 6'd19) & ~(or_ln1265_2_reg_94874 == 6'd41) & ~(or_ln1265_2_reg_94874 == 6'd25) & ~(or_ln1265_2_reg_94874 == 6'd11) & ~(or_ln1265_2_reg_94874 == 6'd57) & ~(or_ln1265_2_reg_94874 == 6'd9) & ~(or_ln1265_2_reg_94874 == 6'd33) & ~(or_ln1265_2_reg_94874 == 6'd49) & ~(or_ln1265_2_reg_94874 == 6'd59) & ~(or_ln1265_2_reg_94874 == 6'd27) & ~(or_ln1265_2_reg_94874 == 6'd43) & ~(or_ln1265_2_reg_94874 == 6'd3) & ~(or_ln1265_2_reg_94874 == 6'd17) & ~(or_ln1265_2_reg_94874 == 6'd1) & ~(or_ln1265_2_reg_94874 == 6'd35) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | (~(6'd0 == add_ln203_7_fu_81344_p2) & ~(6'd62 == add_ln203_7_fu_81344_p2) & ~(6'd2 == add_ln203_7_fu_81344_p2) & ~(6'd32 == add_ln203_7_fu_81344_p2) & ~(6'd4 == add_ln203_7_fu_81344_p2) & ~(6'd60 == add_ln203_7_fu_81344_p2) & ~(6'd6 == add_ln203_7_fu_81344_p2) & ~(6'd46 == add_ln203_7_fu_81344_p2) & ~(6'd8 == add_ln203_7_fu_81344_p2) & ~(6'd58 == add_ln203_7_fu_81344_p2) & ~(6'd10 == add_ln203_7_fu_81344_p2) & ~(6'd34 == add_ln203_7_fu_81344_p2) & ~(6'd12 == add_ln203_7_fu_81344_p2) & ~(6'd56 == add_ln203_7_fu_81344_p2) & ~(6'd14 == add_ln203_7_fu_81344_p2) & ~(6'd40 == add_ln203_7_fu_81344_p2) & ~(6'd16 == add_ln203_7_fu_81344_p2) & ~(6'd54 == add_ln203_7_fu_81344_p2) & ~(6'd18 == add_ln203_7_fu_81344_p2) & ~(6'd36 == add_ln203_7_fu_81344_p2) & ~(6'd20 == add_ln203_7_fu_81344_p2) & ~(6'd52 == add_ln203_7_fu_81344_p2) & ~(6'd22 == add_ln203_7_fu_81344_p2) & ~(6'd44 == add_ln203_7_fu_81344_p2) & ~(6'd24 == add_ln203_7_fu_81344_p2) & ~(6'd50 == add_ln203_7_fu_81344_p2) & ~(6'd26 == add_ln203_7_fu_81344_p2) & ~(6'd38 == add_ln203_7_fu_81344_p2) & ~(6'd28 == add_ln203_7_fu_81344_p2) & ~(6'd48 == add_ln203_7_fu_81344_p2) & ~(6'd30 == add_ln203_7_fu_81344_p2) & ~(6'd42 == add_ln203_7_fu_81344_p2) & (icmp_ln248_3_fu_81329_p2 == 1'd0) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | (~(or_ln203_1_fu_81206_p3 == 6'd0) & ~(or_ln203_1_fu_81206_p3 == 6'd62) & ~(or_ln203_1_fu_81206_p3 == 6'd2) & ~(or_ln203_1_fu_81206_p3 == 6'd32) & ~(or_ln203_1_fu_81206_p3 == 6'd4) & ~(or_ln203_1_fu_81206_p3 == 6'd60) & ~(or_ln203_1_fu_81206_p3 == 6'd6) & ~(or_ln203_1_fu_81206_p3 == 6'd46) & ~(or_ln203_1_fu_81206_p3 == 6'd8) & ~(or_ln203_1_fu_81206_p3 == 6'd58) & ~(or_ln203_1_fu_81206_p3 == 6'd10) & ~(or_ln203_1_fu_81206_p3 == 6'd34) & ~(or_ln203_1_fu_81206_p3 == 6'd12) & ~(or_ln203_1_fu_81206_p3 == 6'd56) & ~(or_ln203_1_fu_81206_p3 == 6'd14) & ~(or_ln203_1_fu_81206_p3 == 6'd40) & ~(or_ln203_1_fu_81206_p3 == 6'd16) & ~(or_ln203_1_fu_81206_p3 == 6'd54) & ~(or_ln203_1_fu_81206_p3 == 6'd18) & ~(or_ln203_1_fu_81206_p3 == 6'd36) & ~(or_ln203_1_fu_81206_p3 == 6'd20) & ~(or_ln203_1_fu_81206_p3 == 6'd52) & ~(or_ln203_1_fu_81206_p3 == 6'd22) & ~(or_ln203_1_fu_81206_p3 == 6'd44) & ~(or_ln203_1_fu_81206_p3 == 6'd24) & ~(or_ln203_1_fu_81206_p3 == 6'd50) & ~(or_ln203_1_fu_81206_p3 == 6'd26) & ~(or_ln203_1_fu_81206_p3 == 6'd38) & ~(or_ln203_1_fu_81206_p3 == 6'd28) & ~(or_ln203_1_fu_81206_p3 == 6'd48) & ~(or_ln203_1_fu_81206_p3 == 6'd30) & ~(or_ln203_1_fu_81206_p3 == 6'd42) & (icmp_ln248_1_fu_81191_p2 == 1'd0) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | (~(6'd0 == add_ln203_3_fu_80968_p2) & ~(6'd62 == add_ln203_3_fu_80968_p2) & ~(6'd2 == add_ln203_3_fu_80968_p2) & ~(6'd32 == add_ln203_3_fu_80968_p2) & ~(6'd4 == add_ln203_3_fu_80968_p2) & ~(6'd60 == add_ln203_3_fu_80968_p2) & ~(6'd6 == add_ln203_3_fu_80968_p2) & ~(6'd46 == add_ln203_3_fu_80968_p2) & ~(6'd8 == add_ln203_3_fu_80968_p2) & ~(6'd58 == add_ln203_3_fu_80968_p2) & ~(6'd10 == add_ln203_3_fu_80968_p2) & ~(6'd34 == add_ln203_3_fu_80968_p2) & ~(6'd12 == add_ln203_3_fu_80968_p2) & ~(6'd56 == add_ln203_3_fu_80968_p2) & ~(6'd14 == add_ln203_3_fu_80968_p2) & ~(6'd40 == add_ln203_3_fu_80968_p2) & ~(6'd16 == add_ln203_3_fu_80968_p2) & ~(6'd54 == add_ln203_3_fu_80968_p2) & ~(6'd18 == add_ln203_3_fu_80968_p2) & ~(6'd36 == add_ln203_3_fu_80968_p2) & ~(6'd20 == add_ln203_3_fu_80968_p2) & ~(6'd52 == add_ln203_3_fu_80968_p2) & ~(6'd22 == add_ln203_3_fu_80968_p2) & ~(6'd44 == add_ln203_3_fu_80968_p2) & ~(6'd24 == add_ln203_3_fu_80968_p2) & ~(6'd50 == add_ln203_3_fu_80968_p2) & ~(6'd26 == add_ln203_3_fu_80968_p2) & ~(6'd38 == add_ln203_3_fu_80968_p2) & ~(6'd28 == add_ln203_3_fu_80968_p2) & ~(6'd48 == add_ln203_3_fu_80968_p2) & ~(6'd30 == add_ln203_3_fu_80968_p2) & ~(6'd42 == add_ln203_3_fu_80968_p2) & (icmp_ln248_2_fu_80953_p2 == 1'd0) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | (~(or_ln2_fu_80834_p3 == 6'd0) & ~(or_ln2_fu_80834_p3 == 6'd62) & ~(or_ln2_fu_80834_p3 == 6'd2) & ~(or_ln2_fu_80834_p3 == 6'd32) & ~(or_ln2_fu_80834_p3 == 6'd4) & ~(or_ln2_fu_80834_p3 == 6'd60) & ~(or_ln2_fu_80834_p3 == 6'd6) & ~(or_ln2_fu_80834_p3 == 6'd46) & ~(or_ln2_fu_80834_p3 == 6'd8) & ~(or_ln2_fu_80834_p3 == 6'd58) & ~(or_ln2_fu_80834_p3 == 6'd10) & ~(or_ln2_fu_80834_p3 == 6'd34) & ~(or_ln2_fu_80834_p3 == 6'd12) & ~(or_ln2_fu_80834_p3 == 6'd56) & ~(or_ln2_fu_80834_p3 == 6'd14) & ~(or_ln2_fu_80834_p3 == 6'd40) & ~(or_ln2_fu_80834_p3 == 6'd16) & ~(or_ln2_fu_80834_p3 == 6'd54) & ~(or_ln2_fu_80834_p3 == 6'd18) & ~(or_ln2_fu_80834_p3 == 6'd36) & ~(or_ln2_fu_80834_p3 == 6'd20) & ~(or_ln2_fu_80834_p3 == 6'd52) & ~(or_ln2_fu_80834_p3 == 6'd22) & ~(or_ln2_fu_80834_p3 == 6'd44) & ~(or_ln2_fu_80834_p3 == 6'd24) & ~(or_ln2_fu_80834_p3 == 6'd50) & ~(or_ln2_fu_80834_p3 == 6'd26) & ~(or_ln2_fu_80834_p3 == 6'd38) & ~(or_ln2_fu_80834_p3 == 6'd28) & ~(or_ln2_fu_80834_p3 == 6'd48) & ~(or_ln2_fu_80834_p3 == 6'd30) & ~(or_ln2_fu_80834_p3 == 6'd42) & (icmp_ln248_fu_80819_p2 == 1'd0) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | (~(or_ln1265_5_reg_100772 == 6'd55) & ~(or_ln1265_5_reg_100772 == 6'd13) & ~(or_ln1265_5_reg_100772 == 6'd45) & ~(or_ln1265_5_reg_100772 == 6'd37) & ~(or_ln1265_5_reg_100772 == 6'd53) & ~(or_ln1265_5_reg_100772 == 6'd21) & ~(or_ln1265_5_reg_100772 == 6'd23) & ~(or_ln1265_5_reg_100772 == 6'd7) & ~(or_ln1265_5_reg_100772 == 6'd15) & ~(or_ln1265_5_reg_100772 == 6'd5) & ~(or_ln1265_5_reg_100772 == 6'd39) & ~(or_ln1265_5_reg_100772 == 6'd29) & ~(or_ln1265_5_reg_100772 == 6'd61) & ~(or_ln1265_5_reg_100772 == 6'd47) & ~(or_ln1265_5_reg_100772 == 6'd31) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | (~(or_ln1265_3_reg_98943 == 6'd51) & ~(or_ln1265_3_reg_98943 == 6'd19) & ~(or_ln1265_3_reg_98943 == 6'd41) & ~(or_ln1265_3_reg_98943 == 6'd25) & ~(or_ln1265_3_reg_98943 == 6'd11) & ~(or_ln1265_3_reg_98943 == 6'd57) & ~(or_ln1265_3_reg_98943 == 6'd9) & ~(or_ln1265_3_reg_98943 == 6'd33) & ~(or_ln1265_3_reg_98943 == 6'd49) & ~(or_ln1265_3_reg_98943 == 6'd59) & ~(or_ln1265_3_reg_98943 == 6'd27) & ~(or_ln1265_3_reg_98943 == 6'd43) & ~(or_ln1265_3_reg_98943 == 6'd3) & ~(or_ln1265_3_reg_98943 == 6'd17) & ~(or_ln1265_3_reg_98943 == 6'd1) & ~(or_ln1265_3_reg_98943 == 6'd35) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | (~(or_ln1265_4_reg_96698 == 6'd55) & ~(or_ln1265_4_reg_96698 == 6'd13) & ~(or_ln1265_4_reg_96698 == 6'd45) & ~(or_ln1265_4_reg_96698 == 6'd37) & ~(or_ln1265_4_reg_96698 == 6'd53) & ~(or_ln1265_4_reg_96698 == 6'd21) & ~(or_ln1265_4_reg_96698 == 6'd23) & ~(or_ln1265_4_reg_96698 == 6'd7) & ~(or_ln1265_4_reg_96698 == 6'd15) & ~(or_ln1265_4_reg_96698 == 6'd5) & ~(or_ln1265_4_reg_96698 == 6'd39) & ~(or_ln1265_4_reg_96698 == 6'd29) & ~(or_ln1265_4_reg_96698 == 6'd61) & ~(or_ln1265_4_reg_96698 == 6'd47) & ~(or_ln1265_4_reg_96698 == 6'd31) & (ap_ST_fsm_state1712 == ap_CS_fsm)) | (~(or_ln1265_2_reg_94874 == 6'd51) & ~(or_ln1265_2_reg_94874 == 6'd19) & ~(or_ln1265_2_reg_94874 == 6'd41) & ~(or_ln1265_2_reg_94874 == 6'd25) & ~(or_ln1265_2_reg_94874 == 6'd11) & ~(or_ln1265_2_reg_94874 == 6'd57) & ~(or_ln1265_2_reg_94874 == 6'd9) & ~(or_ln1265_2_reg_94874 == 6'd33) & ~(or_ln1265_2_reg_94874 == 6'd49) & ~(or_ln1265_2_reg_94874 == 6'd59) & ~(or_ln1265_2_reg_94874 == 6'd27) & ~(or_ln1265_2_reg_94874 == 6'd43) & ~(or_ln1265_2_reg_94874 == 6'd3) & ~(or_ln1265_2_reg_94874 == 6'd17) & ~(or_ln1265_2_reg_94874 == 6'd1) & ~(or_ln1265_2_reg_94874 == 6'd35) & (ap_ST_fsm_state1412 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_1_reg_100172) & ~(6'd62 == add_ln1265_1_reg_100172) & ~(6'd2 == add_ln1265_1_reg_100172) & ~(6'd32 == add_ln1265_1_reg_100172) & ~(6'd4 == add_ln1265_1_reg_100172) & ~(6'd60 == add_ln1265_1_reg_100172) & ~(6'd6 == add_ln1265_1_reg_100172) & ~(6'd46 == add_ln1265_1_reg_100172) & ~(6'd8 == add_ln1265_1_reg_100172) & ~(6'd58 == add_ln1265_1_reg_100172) & ~(6'd10 == add_ln1265_1_reg_100172) & ~(6'd34 == add_ln1265_1_reg_100172) & ~(6'd12 == add_ln1265_1_reg_100172) & ~(6'd56 == add_ln1265_1_reg_100172) & ~(6'd14 == add_ln1265_1_reg_100172) & ~(6'd40 == add_ln1265_1_reg_100172) & ~(6'd16 == add_ln1265_1_reg_100172) & ~(6'd54 == add_ln1265_1_reg_100172) & ~(6'd18 == add_ln1265_1_reg_100172) & ~(6'd36 == add_ln1265_1_reg_100172) & ~(6'd20 == add_ln1265_1_reg_100172) & ~(6'd52 == add_ln1265_1_reg_100172) & ~(6'd22 == add_ln1265_1_reg_100172) & ~(6'd44 == add_ln1265_1_reg_100172) & ~(6'd24 == add_ln1265_1_reg_100172) & ~(6'd50 == add_ln1265_1_reg_100172) & ~(6'd26 == add_ln1265_1_reg_100172) & ~(6'd38 == add_ln1265_1_reg_100172) & ~(6'd28 == add_ln1265_1_reg_100172) & ~(6'd48 == add_ln1265_1_reg_100172) & ~(6'd30 == add_ln1265_1_reg_100172) & ~(6'd42 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | (~(or_ln1265_1_reg_98331 == 6'd0) & ~(or_ln1265_1_reg_98331 == 6'd62) & ~(or_ln1265_1_reg_98331 == 6'd2) & ~(or_ln1265_1_reg_98331 == 6'd32) & ~(or_ln1265_1_reg_98331 == 6'd4) & ~(or_ln1265_1_reg_98331 == 6'd60) & ~(or_ln1265_1_reg_98331 == 6'd6) & ~(or_ln1265_1_reg_98331 == 6'd46) & ~(or_ln1265_1_reg_98331 == 6'd8) & ~(or_ln1265_1_reg_98331 == 6'd58) & ~(or_ln1265_1_reg_98331 == 6'd10) & ~(or_ln1265_1_reg_98331 == 6'd34) & ~(or_ln1265_1_reg_98331 == 6'd12) & ~(or_ln1265_1_reg_98331 == 6'd56) & ~(or_ln1265_1_reg_98331 == 6'd14) & ~(or_ln1265_1_reg_98331 == 6'd40) & ~(or_ln1265_1_reg_98331 == 6'd16) & ~(or_ln1265_1_reg_98331 == 6'd54) & ~(or_ln1265_1_reg_98331 == 6'd18) & ~(or_ln1265_1_reg_98331 == 6'd36) & ~(or_ln1265_1_reg_98331 == 6'd20) & ~(or_ln1265_1_reg_98331 == 6'd52) & ~(or_ln1265_1_reg_98331 == 6'd22) & ~(or_ln1265_1_reg_98331 == 6'd44) & ~(or_ln1265_1_reg_98331 == 6'd24) & ~(or_ln1265_1_reg_98331 == 6'd50) & ~(or_ln1265_1_reg_98331 == 6'd26) & ~(or_ln1265_1_reg_98331 == 6'd38) & ~(or_ln1265_1_reg_98331 == 6'd28) & ~(or_ln1265_1_reg_98331 == 6'd48) & ~(or_ln1265_1_reg_98331 == 6'd30) & ~(or_ln1265_1_reg_98331 == 6'd42) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_reg_96098) & ~(6'd62 == add_ln1265_reg_96098) & ~(6'd2 == add_ln1265_reg_96098) & ~(6'd32 == add_ln1265_reg_96098) & ~(6'd4 == add_ln1265_reg_96098) & ~(6'd60 == add_ln1265_reg_96098) & ~(6'd6 == add_ln1265_reg_96098) & ~(6'd46 == add_ln1265_reg_96098) & ~(6'd8 == add_ln1265_reg_96098) & ~(6'd58 == add_ln1265_reg_96098) & ~(6'd10 == add_ln1265_reg_96098) & ~(6'd34 == add_ln1265_reg_96098) & ~(6'd12 == add_ln1265_reg_96098) & ~(6'd56 == add_ln1265_reg_96098) & ~(6'd14 == add_ln1265_reg_96098) & ~(6'd40 == add_ln1265_reg_96098) & ~(6'd16 == add_ln1265_reg_96098) & ~(6'd54 == add_ln1265_reg_96098) & ~(6'd18 == add_ln1265_reg_96098) & ~(6'd36 == add_ln1265_reg_96098) & ~(6'd20 == add_ln1265_reg_96098) & ~(6'd52 == add_ln1265_reg_96098) & ~(6'd22 == add_ln1265_reg_96098) & ~(6'd44 == add_ln1265_reg_96098) & ~(6'd24 == add_ln1265_reg_96098) & ~(6'd50 == add_ln1265_reg_96098) & ~(6'd26 == add_ln1265_reg_96098) & ~(6'd38 == add_ln1265_reg_96098) & ~(6'd28 == add_ln1265_reg_96098) & ~(6'd48 == add_ln1265_reg_96098) & ~(6'd30 == add_ln1265_reg_96098) & ~(6'd42 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_63_V_we0 = 1'b1; + end else begin + acc_63_V_we0 = 1'b0; + end +end + +always @ (*) begin + if (((~(or_ln1265_5_reg_100772 == 6'd55) & ~(or_ln1265_5_reg_100772 == 6'd13) & ~(or_ln1265_5_reg_100772 == 6'd45) & ~(or_ln1265_5_reg_100772 == 6'd37) & ~(or_ln1265_5_reg_100772 == 6'd53) & ~(or_ln1265_5_reg_100772 == 6'd21) & ~(or_ln1265_5_reg_100772 == 6'd23) & ~(or_ln1265_5_reg_100772 == 6'd7) & ~(or_ln1265_5_reg_100772 == 6'd15) & ~(or_ln1265_5_reg_100772 == 6'd5) & ~(or_ln1265_5_reg_100772 == 6'd39) & ~(or_ln1265_5_reg_100772 == 6'd29) & ~(or_ln1265_5_reg_100772 == 6'd61) & ~(or_ln1265_5_reg_100772 == 6'd47) & ~(or_ln1265_5_reg_100772 == 6'd31) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | (~(or_ln1265_5_reg_100772 == 6'd55) & ~(or_ln1265_5_reg_100772 == 6'd13) & ~(or_ln1265_5_reg_100772 == 6'd45) & ~(or_ln1265_5_reg_100772 == 6'd37) & ~(or_ln1265_5_reg_100772 == 6'd53) & ~(or_ln1265_5_reg_100772 == 6'd21) & ~(or_ln1265_5_reg_100772 == 6'd23) & ~(or_ln1265_5_reg_100772 == 6'd7) & ~(or_ln1265_5_reg_100772 == 6'd15) & ~(or_ln1265_5_reg_100772 == 6'd5) & ~(or_ln1265_5_reg_100772 == 6'd39) & ~(or_ln1265_5_reg_100772 == 6'd29) & ~(or_ln1265_5_reg_100772 == 6'd61) & ~(or_ln1265_5_reg_100772 == 6'd47) & ~(or_ln1265_5_reg_100772 == 6'd31) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_1_reg_100172) & ~(6'd62 == add_ln1265_1_reg_100172) & ~(6'd2 == add_ln1265_1_reg_100172) & ~(6'd32 == add_ln1265_1_reg_100172) & ~(6'd4 == add_ln1265_1_reg_100172) & ~(6'd60 == add_ln1265_1_reg_100172) & ~(6'd6 == add_ln1265_1_reg_100172) & ~(6'd46 == add_ln1265_1_reg_100172) & ~(6'd8 == add_ln1265_1_reg_100172) & ~(6'd58 == add_ln1265_1_reg_100172) & ~(6'd10 == add_ln1265_1_reg_100172) & ~(6'd34 == add_ln1265_1_reg_100172) & ~(6'd12 == add_ln1265_1_reg_100172) & ~(6'd56 == add_ln1265_1_reg_100172) & ~(6'd14 == add_ln1265_1_reg_100172) & ~(6'd40 == add_ln1265_1_reg_100172) & ~(6'd16 == add_ln1265_1_reg_100172) & ~(6'd54 == add_ln1265_1_reg_100172) & ~(6'd18 == add_ln1265_1_reg_100172) & ~(6'd36 == add_ln1265_1_reg_100172) & ~(6'd20 == add_ln1265_1_reg_100172) & ~(6'd52 == add_ln1265_1_reg_100172) & ~(6'd22 == add_ln1265_1_reg_100172) & ~(6'd44 == add_ln1265_1_reg_100172) & ~(6'd24 == add_ln1265_1_reg_100172) & ~(6'd50 == add_ln1265_1_reg_100172) & ~(6'd26 == add_ln1265_1_reg_100172) & ~(6'd38 == add_ln1265_1_reg_100172) & ~(6'd28 == add_ln1265_1_reg_100172) & ~(6'd48 == add_ln1265_1_reg_100172) & ~(6'd30 == add_ln1265_1_reg_100172) & ~(6'd42 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | (~(or_ln1265_3_reg_98943 == 6'd51) & ~(or_ln1265_3_reg_98943 == 6'd19) & ~(or_ln1265_3_reg_98943 == 6'd41) & ~(or_ln1265_3_reg_98943 == 6'd25) & ~(or_ln1265_3_reg_98943 == 6'd11) & ~(or_ln1265_3_reg_98943 == 6'd57) & ~(or_ln1265_3_reg_98943 == 6'd9) & ~(or_ln1265_3_reg_98943 == 6'd33) & ~(or_ln1265_3_reg_98943 == 6'd49) & ~(or_ln1265_3_reg_98943 == 6'd59) & ~(or_ln1265_3_reg_98943 == 6'd27) & ~(or_ln1265_3_reg_98943 == 6'd43) & ~(or_ln1265_3_reg_98943 == 6'd3) & ~(or_ln1265_3_reg_98943 == 6'd17) & ~(or_ln1265_3_reg_98943 == 6'd1) & ~(or_ln1265_3_reg_98943 == 6'd35) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | (~(or_ln1265_3_reg_98943 == 6'd51) & ~(or_ln1265_3_reg_98943 == 6'd19) & ~(or_ln1265_3_reg_98943 == 6'd41) & ~(or_ln1265_3_reg_98943 == 6'd25) & ~(or_ln1265_3_reg_98943 == 6'd11) & ~(or_ln1265_3_reg_98943 == 6'd57) & ~(or_ln1265_3_reg_98943 == 6'd9) & ~(or_ln1265_3_reg_98943 == 6'd33) & ~(or_ln1265_3_reg_98943 == 6'd49) & ~(or_ln1265_3_reg_98943 == 6'd59) & ~(or_ln1265_3_reg_98943 == 6'd27) & ~(or_ln1265_3_reg_98943 == 6'd43) & ~(or_ln1265_3_reg_98943 == 6'd3) & ~(or_ln1265_3_reg_98943 == 6'd17) & ~(or_ln1265_3_reg_98943 == 6'd1) & ~(or_ln1265_3_reg_98943 == 6'd35) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | (~(or_ln1265_1_reg_98331 == 6'd0) & ~(or_ln1265_1_reg_98331 == 6'd62) & ~(or_ln1265_1_reg_98331 == 6'd2) & ~(or_ln1265_1_reg_98331 == 6'd32) & ~(or_ln1265_1_reg_98331 == 6'd4) & ~(or_ln1265_1_reg_98331 == 6'd60) & ~(or_ln1265_1_reg_98331 == 6'd6) & ~(or_ln1265_1_reg_98331 == 6'd46) & ~(or_ln1265_1_reg_98331 == 6'd8) & ~(or_ln1265_1_reg_98331 == 6'd58) & ~(or_ln1265_1_reg_98331 == 6'd10) & ~(or_ln1265_1_reg_98331 == 6'd34) & ~(or_ln1265_1_reg_98331 == 6'd12) & ~(or_ln1265_1_reg_98331 == 6'd56) & ~(or_ln1265_1_reg_98331 == 6'd14) & ~(or_ln1265_1_reg_98331 == 6'd40) & ~(or_ln1265_1_reg_98331 == 6'd16) & ~(or_ln1265_1_reg_98331 == 6'd54) & ~(or_ln1265_1_reg_98331 == 6'd18) & ~(or_ln1265_1_reg_98331 == 6'd36) & ~(or_ln1265_1_reg_98331 == 6'd20) & ~(or_ln1265_1_reg_98331 == 6'd52) & ~(or_ln1265_1_reg_98331 == 6'd22) & ~(or_ln1265_1_reg_98331 == 6'd44) & ~(or_ln1265_1_reg_98331 == 6'd24) & ~(or_ln1265_1_reg_98331 == 6'd50) & ~(or_ln1265_1_reg_98331 == 6'd26) & ~(or_ln1265_1_reg_98331 == 6'd38) & ~(or_ln1265_1_reg_98331 == 6'd28) & ~(or_ln1265_1_reg_98331 == 6'd48) & ~(or_ln1265_1_reg_98331 == 6'd30) & ~(or_ln1265_1_reg_98331 == 6'd42) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | (~(or_ln1265_4_reg_96698 == 6'd55) & ~(or_ln1265_4_reg_96698 == 6'd13) & ~(or_ln1265_4_reg_96698 == 6'd45) & ~(or_ln1265_4_reg_96698 == 6'd37) & ~(or_ln1265_4_reg_96698 == 6'd53) & ~(or_ln1265_4_reg_96698 == 6'd21) & ~(or_ln1265_4_reg_96698 == 6'd23) & ~(or_ln1265_4_reg_96698 == 6'd7) & ~(or_ln1265_4_reg_96698 == 6'd15) & ~(or_ln1265_4_reg_96698 == 6'd5) & ~(or_ln1265_4_reg_96698 == 6'd39) & ~(or_ln1265_4_reg_96698 == 6'd29) & ~(or_ln1265_4_reg_96698 == 6'd61) & ~(or_ln1265_4_reg_96698 == 6'd47) & ~(or_ln1265_4_reg_96698 == 6'd31) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | (~(or_ln1265_4_reg_96698 == 6'd55) & ~(or_ln1265_4_reg_96698 == 6'd13) & ~(or_ln1265_4_reg_96698 == 6'd45) & ~(or_ln1265_4_reg_96698 == 6'd37) & ~(or_ln1265_4_reg_96698 == 6'd53) & ~(or_ln1265_4_reg_96698 == 6'd21) & ~(or_ln1265_4_reg_96698 == 6'd23) & ~(or_ln1265_4_reg_96698 == 6'd7) & ~(or_ln1265_4_reg_96698 == 6'd15) & ~(or_ln1265_4_reg_96698 == 6'd5) & ~(or_ln1265_4_reg_96698 == 6'd39) & ~(or_ln1265_4_reg_96698 == 6'd29) & ~(or_ln1265_4_reg_96698 == 6'd61) & ~(or_ln1265_4_reg_96698 == 6'd47) & ~(or_ln1265_4_reg_96698 == 6'd31) & (ap_ST_fsm_state1676 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_reg_96098) & ~(6'd62 == add_ln1265_reg_96098) & ~(6'd2 == add_ln1265_reg_96098) & ~(6'd32 == add_ln1265_reg_96098) & ~(6'd4 == add_ln1265_reg_96098) & ~(6'd60 == add_ln1265_reg_96098) & ~(6'd6 == add_ln1265_reg_96098) & ~(6'd46 == add_ln1265_reg_96098) & ~(6'd8 == add_ln1265_reg_96098) & ~(6'd58 == add_ln1265_reg_96098) & ~(6'd10 == add_ln1265_reg_96098) & ~(6'd34 == add_ln1265_reg_96098) & ~(6'd12 == add_ln1265_reg_96098) & ~(6'd56 == add_ln1265_reg_96098) & ~(6'd14 == add_ln1265_reg_96098) & ~(6'd40 == add_ln1265_reg_96098) & ~(6'd16 == add_ln1265_reg_96098) & ~(6'd54 == add_ln1265_reg_96098) & ~(6'd18 == add_ln1265_reg_96098) & ~(6'd36 == add_ln1265_reg_96098) & ~(6'd20 == add_ln1265_reg_96098) & ~(6'd52 == add_ln1265_reg_96098) & ~(6'd22 == add_ln1265_reg_96098) & ~(6'd44 == add_ln1265_reg_96098) & ~(6'd24 == add_ln1265_reg_96098) & ~(6'd50 == add_ln1265_reg_96098) & ~(6'd26 == add_ln1265_reg_96098) & ~(6'd38 == add_ln1265_reg_96098) & ~(6'd28 == add_ln1265_reg_96098) & ~(6'd48 == add_ln1265_reg_96098) & ~(6'd30 == add_ln1265_reg_96098) & ~(6'd42 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | (~(or_ln1265_2_reg_94874 == 6'd51) & ~(or_ln1265_2_reg_94874 == 6'd19) & ~(or_ln1265_2_reg_94874 == 6'd41) & ~(or_ln1265_2_reg_94874 == 6'd25) & ~(or_ln1265_2_reg_94874 == 6'd11) & ~(or_ln1265_2_reg_94874 == 6'd57) & ~(or_ln1265_2_reg_94874 == 6'd9) & ~(or_ln1265_2_reg_94874 == 6'd33) & ~(or_ln1265_2_reg_94874 == 6'd49) & ~(or_ln1265_2_reg_94874 == 6'd59) & ~(or_ln1265_2_reg_94874 == 6'd27) & ~(or_ln1265_2_reg_94874 == 6'd43) & ~(or_ln1265_2_reg_94874 == 6'd3) & ~(or_ln1265_2_reg_94874 == 6'd17) & ~(or_ln1265_2_reg_94874 == 6'd1) & ~(or_ln1265_2_reg_94874 == 6'd35) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | (~(or_ln1265_2_reg_94874 == 6'd51) & ~(or_ln1265_2_reg_94874 == 6'd19) & ~(or_ln1265_2_reg_94874 == 6'd41) & ~(or_ln1265_2_reg_94874 == 6'd25) & ~(or_ln1265_2_reg_94874 == 6'd11) & ~(or_ln1265_2_reg_94874 == 6'd57) & ~(or_ln1265_2_reg_94874 == 6'd9) & ~(or_ln1265_2_reg_94874 == 6'd33) & ~(or_ln1265_2_reg_94874 == 6'd49) & ~(or_ln1265_2_reg_94874 == 6'd59) & ~(or_ln1265_2_reg_94874 == 6'd27) & ~(or_ln1265_2_reg_94874 == 6'd43) & ~(or_ln1265_2_reg_94874 == 6'd3) & ~(or_ln1265_2_reg_94874 == 6'd17) & ~(or_ln1265_2_reg_94874 == 6'd1) & ~(or_ln1265_2_reg_94874 == 6'd35) & (ap_ST_fsm_state1375 == ap_CS_fsm)) | (~(or_ln3_reg_94268 == 6'd0) & ~(or_ln3_reg_94268 == 6'd62) & ~(or_ln3_reg_94268 == 6'd2) & ~(or_ln3_reg_94268 == 6'd32) & ~(or_ln3_reg_94268 == 6'd4) & ~(or_ln3_reg_94268 == 6'd60) & ~(or_ln3_reg_94268 == 6'd6) & ~(or_ln3_reg_94268 == 6'd46) & ~(or_ln3_reg_94268 == 6'd8) & ~(or_ln3_reg_94268 == 6'd58) & ~(or_ln3_reg_94268 == 6'd10) & ~(or_ln3_reg_94268 == 6'd34) & ~(or_ln3_reg_94268 == 6'd12) & ~(or_ln3_reg_94268 == 6'd56) & ~(or_ln3_reg_94268 == 6'd14) & ~(or_ln3_reg_94268 == 6'd40) & ~(or_ln3_reg_94268 == 6'd16) & ~(or_ln3_reg_94268 == 6'd54) & ~(or_ln3_reg_94268 == 6'd18) & ~(or_ln3_reg_94268 == 6'd36) & ~(or_ln3_reg_94268 == 6'd20) & ~(or_ln3_reg_94268 == 6'd52) & ~(or_ln3_reg_94268 == 6'd22) & ~(or_ln3_reg_94268 == 6'd44) & ~(or_ln3_reg_94268 == 6'd24) & ~(or_ln3_reg_94268 == 6'd50) & ~(or_ln3_reg_94268 == 6'd26) & ~(or_ln3_reg_94268 == 6'd38) & ~(or_ln3_reg_94268 == 6'd28) & ~(or_ln3_reg_94268 == 6'd48) & ~(or_ln3_reg_94268 == 6'd30) & ~(or_ln3_reg_94268 == 6'd42) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | (~(or_ln3_reg_94268 == 6'd0) & ~(or_ln3_reg_94268 == 6'd62) & ~(or_ln3_reg_94268 == 6'd2) & ~(or_ln3_reg_94268 == 6'd32) & ~(or_ln3_reg_94268 == 6'd4) & ~(or_ln3_reg_94268 == 6'd60) & ~(or_ln3_reg_94268 == 6'd6) & ~(or_ln3_reg_94268 == 6'd46) & ~(or_ln3_reg_94268 == 6'd8) & ~(or_ln3_reg_94268 == 6'd58) & ~(or_ln3_reg_94268 == 6'd10) & ~(or_ln3_reg_94268 == 6'd34) & ~(or_ln3_reg_94268 == 6'd12) & ~(or_ln3_reg_94268 == 6'd56) & ~(or_ln3_reg_94268 == 6'd14) & ~(or_ln3_reg_94268 == 6'd40) & ~(or_ln3_reg_94268 == 6'd16) & ~(or_ln3_reg_94268 == 6'd54) & ~(or_ln3_reg_94268 == 6'd18) & ~(or_ln3_reg_94268 == 6'd36) & ~(or_ln3_reg_94268 == 6'd20) & ~(or_ln3_reg_94268 == 6'd52) & ~(or_ln3_reg_94268 == 6'd22) & ~(or_ln3_reg_94268 == 6'd44) & ~(or_ln3_reg_94268 == 6'd24) & ~(or_ln3_reg_94268 == 6'd50) & ~(or_ln3_reg_94268 == 6'd26) & ~(or_ln3_reg_94268 == 6'd38) & ~(or_ln3_reg_94268 == 6'd28) & ~(or_ln3_reg_94268 == 6'd48) & ~(or_ln3_reg_94268 == 6'd30) & ~(or_ln3_reg_94268 == 6'd42) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_1_reg_100172) & ~(6'd62 == add_ln1265_1_reg_100172) & ~(6'd2 == add_ln1265_1_reg_100172) & ~(6'd32 == add_ln1265_1_reg_100172) & ~(6'd4 == add_ln1265_1_reg_100172) & ~(6'd60 == add_ln1265_1_reg_100172) & ~(6'd6 == add_ln1265_1_reg_100172) & ~(6'd46 == add_ln1265_1_reg_100172) & ~(6'd8 == add_ln1265_1_reg_100172) & ~(6'd58 == add_ln1265_1_reg_100172) & ~(6'd10 == add_ln1265_1_reg_100172) & ~(6'd34 == add_ln1265_1_reg_100172) & ~(6'd12 == add_ln1265_1_reg_100172) & ~(6'd56 == add_ln1265_1_reg_100172) & ~(6'd14 == add_ln1265_1_reg_100172) & ~(6'd40 == add_ln1265_1_reg_100172) & ~(6'd16 == add_ln1265_1_reg_100172) & ~(6'd54 == add_ln1265_1_reg_100172) & ~(6'd18 == add_ln1265_1_reg_100172) & ~(6'd36 == add_ln1265_1_reg_100172) & ~(6'd20 == add_ln1265_1_reg_100172) & ~(6'd52 == add_ln1265_1_reg_100172) & ~(6'd22 == add_ln1265_1_reg_100172) & ~(6'd44 == add_ln1265_1_reg_100172) & ~(6'd24 == add_ln1265_1_reg_100172) & ~(6'd50 == add_ln1265_1_reg_100172) & ~(6'd26 == add_ln1265_1_reg_100172) & ~(6'd38 == add_ln1265_1_reg_100172) & ~(6'd28 == add_ln1265_1_reg_100172) & ~(6'd48 == add_ln1265_1_reg_100172) & ~(6'd30 == add_ln1265_1_reg_100172) & ~(6'd42 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | (~(or_ln1265_1_reg_98331 == 6'd0) & ~(or_ln1265_1_reg_98331 == 6'd62) & ~(or_ln1265_1_reg_98331 == 6'd2) & ~(or_ln1265_1_reg_98331 == 6'd32) & ~(or_ln1265_1_reg_98331 == 6'd4) & ~(or_ln1265_1_reg_98331 == 6'd60) & ~(or_ln1265_1_reg_98331 == 6'd6) & ~(or_ln1265_1_reg_98331 == 6'd46) & ~(or_ln1265_1_reg_98331 == 6'd8) & ~(or_ln1265_1_reg_98331 == 6'd58) & ~(or_ln1265_1_reg_98331 == 6'd10) & ~(or_ln1265_1_reg_98331 == 6'd34) & ~(or_ln1265_1_reg_98331 == 6'd12) & ~(or_ln1265_1_reg_98331 == 6'd56) & ~(or_ln1265_1_reg_98331 == 6'd14) & ~(or_ln1265_1_reg_98331 == 6'd40) & ~(or_ln1265_1_reg_98331 == 6'd16) & ~(or_ln1265_1_reg_98331 == 6'd54) & ~(or_ln1265_1_reg_98331 == 6'd18) & ~(or_ln1265_1_reg_98331 == 6'd36) & ~(or_ln1265_1_reg_98331 == 6'd20) & ~(or_ln1265_1_reg_98331 == 6'd52) & ~(or_ln1265_1_reg_98331 == 6'd22) & ~(or_ln1265_1_reg_98331 == 6'd44) & ~(or_ln1265_1_reg_98331 == 6'd24) & ~(or_ln1265_1_reg_98331 == 6'd50) & ~(or_ln1265_1_reg_98331 == 6'd26) & ~(or_ln1265_1_reg_98331 == 6'd38) & ~(or_ln1265_1_reg_98331 == 6'd28) & ~(or_ln1265_1_reg_98331 == 6'd48) & ~(or_ln1265_1_reg_98331 == 6'd30) & ~(or_ln1265_1_reg_98331 == 6'd42) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | (~(6'd0 == add_ln1265_reg_96098) & ~(6'd62 == add_ln1265_reg_96098) & ~(6'd2 == add_ln1265_reg_96098) & ~(6'd32 == add_ln1265_reg_96098) & ~(6'd4 == add_ln1265_reg_96098) & ~(6'd60 == add_ln1265_reg_96098) & ~(6'd6 == add_ln1265_reg_96098) & ~(6'd46 == add_ln1265_reg_96098) & ~(6'd8 == add_ln1265_reg_96098) & ~(6'd58 == add_ln1265_reg_96098) & ~(6'd10 == add_ln1265_reg_96098) & ~(6'd34 == add_ln1265_reg_96098) & ~(6'd12 == add_ln1265_reg_96098) & ~(6'd56 == add_ln1265_reg_96098) & ~(6'd14 == add_ln1265_reg_96098) & ~(6'd40 == add_ln1265_reg_96098) & ~(6'd16 == add_ln1265_reg_96098) & ~(6'd54 == add_ln1265_reg_96098) & ~(6'd18 == add_ln1265_reg_96098) & ~(6'd36 == add_ln1265_reg_96098) & ~(6'd20 == add_ln1265_reg_96098) & ~(6'd52 == add_ln1265_reg_96098) & ~(6'd22 == add_ln1265_reg_96098) & ~(6'd44 == add_ln1265_reg_96098) & ~(6'd24 == add_ln1265_reg_96098) & ~(6'd50 == add_ln1265_reg_96098) & ~(6'd26 == add_ln1265_reg_96098) & ~(6'd38 == add_ln1265_reg_96098) & ~(6'd28 == add_ln1265_reg_96098) & ~(6'd48 == add_ln1265_reg_96098) & ~(6'd30 == add_ln1265_reg_96098) & ~(6'd42 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | (~(or_ln3_reg_94268 == 6'd0) & ~(or_ln3_reg_94268 == 6'd62) & ~(or_ln3_reg_94268 == 6'd2) & ~(or_ln3_reg_94268 == 6'd32) & ~(or_ln3_reg_94268 == 6'd4) & ~(or_ln3_reg_94268 == 6'd60) & ~(or_ln3_reg_94268 == 6'd6) & ~(or_ln3_reg_94268 == 6'd46) & ~(or_ln3_reg_94268 == 6'd8) & ~(or_ln3_reg_94268 == 6'd58) & ~(or_ln3_reg_94268 == 6'd10) & ~(or_ln3_reg_94268 == 6'd34) & ~(or_ln3_reg_94268 == 6'd12) & ~(or_ln3_reg_94268 == 6'd56) & ~(or_ln3_reg_94268 == 6'd14) & ~(or_ln3_reg_94268 == 6'd40) & ~(or_ln3_reg_94268 == 6'd16) & ~(or_ln3_reg_94268 == 6'd54) & ~(or_ln3_reg_94268 == 6'd18) & ~(or_ln3_reg_94268 == 6'd36) & ~(or_ln3_reg_94268 == 6'd20) & ~(or_ln3_reg_94268 == 6'd52) & ~(or_ln3_reg_94268 == 6'd22) & ~(or_ln3_reg_94268 == 6'd44) & ~(or_ln3_reg_94268 == 6'd24) & ~(or_ln3_reg_94268 == 6'd50) & ~(or_ln3_reg_94268 == 6'd26) & ~(or_ln3_reg_94268 == 6'd38) & ~(or_ln3_reg_94268 == 6'd28) & ~(or_ln3_reg_94268 == 6'd48) & ~(or_ln3_reg_94268 == 6'd30) & ~(or_ln3_reg_94268 == 6'd42) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | (~(or_ln3_reg_94268 == 6'd0) & ~(or_ln3_reg_94268 == 6'd62) & ~(or_ln3_reg_94268 == 6'd2) & ~(or_ln3_reg_94268 == 6'd32) & ~(or_ln3_reg_94268 == 6'd4) & ~(or_ln3_reg_94268 == 6'd60) & ~(or_ln3_reg_94268 == 6'd6) & ~(or_ln3_reg_94268 == 6'd46) & ~(or_ln3_reg_94268 == 6'd8) & ~(or_ln3_reg_94268 == 6'd58) & ~(or_ln3_reg_94268 == 6'd10) & ~(or_ln3_reg_94268 == 6'd34) & ~(or_ln3_reg_94268 == 6'd12) & ~(or_ln3_reg_94268 == 6'd56) & ~(or_ln3_reg_94268 == 6'd14) & ~(or_ln3_reg_94268 == 6'd40) & ~(or_ln3_reg_94268 == 6'd16) & ~(or_ln3_reg_94268 == 6'd54) & ~(or_ln3_reg_94268 == 6'd18) & ~(or_ln3_reg_94268 == 6'd36) & ~(or_ln3_reg_94268 == 6'd20) & ~(or_ln3_reg_94268 == 6'd52) & ~(or_ln3_reg_94268 == 6'd22) & ~(or_ln3_reg_94268 == 6'd44) & ~(or_ln3_reg_94268 == 6'd24) & ~(or_ln3_reg_94268 == 6'd50) & ~(or_ln3_reg_94268 == 6'd26) & ~(or_ln3_reg_94268 == 6'd38) & ~(or_ln3_reg_94268 == 6'd28) & ~(or_ln3_reg_94268 == 6'd48) & ~(or_ln3_reg_94268 == 6'd30) & ~(or_ln3_reg_94268 == 6'd42) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_63_V_we1 = 1'b1; + end else begin + acc_63_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_6_V_address0 = acc_6_V_addr_55_reg_98712; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_6_V_address0 = acc_6_V_addr_58_reg_100200; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_6_V_address0 = acc_6_V_addr_52_reg_97951; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_6_V_address0 = acc_6_V_addr_53_reg_94648; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_6_V_address0 = acc_6_V_addr_56_reg_96126; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_6_V_address0 = acc_6_V_addr_50_reg_93890; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_6_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_6_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_6_V_address0 = acc_6_V_addr_51_reg_92688; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_6_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_6_V_address0 = acc_6_V_addr_49_reg_92133; + end else begin + acc_6_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_6_V_address1 = acc_6_V_addr_55_reg_98712; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_6_V_address1 = acc_6_V_addr_58_reg_100200; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_6_V_address1 = acc_6_V_addr_52_reg_97951; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_6_V_address1 = acc_6_V_addr_53_reg_94648; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_6_V_address1 = acc_6_V_addr_56_reg_96126; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_6_V_address1 = acc_6_V_addr_50_reg_93890; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_6_V_address1 = 64'd1; + end else begin + acc_6_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_6_V_ce0 = 1'b1; + end else begin + acc_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_6_V_ce1 = 1'b1; + end else begin + acc_6_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_6_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_6_V_d0 = 8'd0; + end else begin + acc_6_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_6_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_6_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd6 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd6) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd6 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd6) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd6 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd6) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd6 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd6) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd6 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd6) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd6 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_6_V_we0 = 1'b1; + end else begin + acc_6_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd6 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd6) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd6 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd6) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd6 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd6) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd6 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd6) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd6) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_6_V_we1 = 1'b1; + end else begin + acc_6_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd2; + end else if (((ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm))) begin + acc_7_V_address0 = acc_7_V_addr_56_reg_98370; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_7_V_address0 = acc_7_V_addr_58_reg_100548; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_7_V_address0 = acc_7_V_addr_53_reg_98311; + end else if (((ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm))) begin + acc_7_V_address0 = acc_7_V_addr_54_reg_94306; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_7_V_address0 = acc_7_V_addr_57_reg_96474; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_7_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_7_V_address0 = acc_7_V_addr_55_reg_93030; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_7_V_address0 = acc_7_V_addr_51_reg_92853; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_7_V_address0 = acc_7_V_addr_52_reg_92482; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_7_V_address0 = acc_7_V_addr_49_reg_92298; + end else begin + acc_7_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd3; + end else if (((ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + acc_7_V_address1 = acc_7_V_addr_56_reg_98370; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_7_V_address1 = acc_7_V_addr_58_reg_100548; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_7_V_address1 = acc_7_V_addr_53_reg_98311; + end else if (((ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + acc_7_V_address1 = acc_7_V_addr_54_reg_94306; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_7_V_address1 = acc_7_V_addr_57_reg_96474; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_7_V_address1 = acc_7_V_addr_50_reg_94237; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_7_V_address1 = 64'd1; + end else begin + acc_7_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2350 == ap_CS_fsm) | (ap_ST_fsm_state2312 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1750 == ap_CS_fsm) | (ap_ST_fsm_state1712 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_7_V_ce0 = 1'b1; + end else begin + acc_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2386 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2276 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1786 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1676 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_7_V_ce1 = 1'b1; + end else begin + acc_7_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2350 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_28_fu_89764_p2; + end else if ((ap_ST_fsm_state2312 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_24_fu_89482_p2; + end else if ((ap_ST_fsm_state1750 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_26_fu_85417_p2; + end else if ((ap_ST_fsm_state1712 == ap_CS_fsm)) begin + acc_7_V_d0 = add_ln703_21_fu_85135_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_7_V_d0 = 8'd254; + end else begin + acc_7_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2386 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_31_fu_89925_p2; + end else if ((ap_ST_fsm_state2276 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_17_fu_89292_p2; + end else if ((ap_ST_fsm_state1786 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_30_fu_85578_p2; + end else if ((ap_ST_fsm_state1676 == ap_CS_fsm)) begin + acc_7_V_d1 = add_ln703_13_fu_84945_p2; + end else begin + acc_7_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd7) & (ap_ST_fsm_state2350 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd7) & (ap_ST_fsm_state1750 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd7) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd7) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd7) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd7) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd7) & (ap_ST_fsm_state2312 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd7) & (ap_ST_fsm_state1712 == ap_CS_fsm)))) begin + acc_7_V_we0 = 1'b1; + end else begin + acc_7_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_5_reg_100772 == 6'd7) & (ap_ST_fsm_state2386 == ap_CS_fsm)) | ((or_ln1265_5_reg_100772 == 6'd7) & (ap_ST_fsm_state2276 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd7) & (ap_ST_fsm_state1786 == ap_CS_fsm)) | ((or_ln1265_4_reg_96698 == 6'd7) & (ap_ST_fsm_state1676 == ap_CS_fsm)))) begin + acc_7_V_we1 = 1'b1; + end else begin + acc_7_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_8_V_address0 = acc_8_V_addr_55_reg_98706; + end else if (((ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm))) begin + acc_8_V_address0 = acc_8_V_addr_58_reg_100206; + end else if (((ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_8_V_address0 = acc_8_V_addr_52_reg_97957; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_8_V_address0 = acc_8_V_addr_53_reg_94642; + end else if (((ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm))) begin + acc_8_V_address0 = acc_8_V_addr_56_reg_96132; + end else if (((ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm))) begin + acc_8_V_address0 = acc_8_V_addr_50_reg_93896; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_8_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1180 == ap_CS_fsm)) begin + acc_8_V_address0 = zext_ln203_15_fu_81363_p1; + end else if ((ap_ST_fsm_state1176 == ap_CS_fsm)) begin + acc_8_V_address0 = acc_8_V_addr_51_reg_92693; + end else if ((ap_ST_fsm_state1171 == ap_CS_fsm)) begin + acc_8_V_address0 = zext_ln203_10_fu_80987_p1; + end else if ((ap_ST_fsm_state1167 == ap_CS_fsm)) begin + acc_8_V_address0 = acc_8_V_addr_49_reg_92138; + end else begin + acc_8_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_8_V_address1 = acc_8_V_addr_55_reg_98706; + end else if (((ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + acc_8_V_address1 = acc_8_V_addr_58_reg_100206; + end else if (((ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm))) begin + acc_8_V_address1 = acc_8_V_addr_52_reg_97957; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_8_V_address1 = acc_8_V_addr_53_reg_94642; + end else if (((ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm))) begin + acc_8_V_address1 = acc_8_V_addr_56_reg_96132; + end else if (((ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_8_V_address1 = acc_8_V_addr_50_reg_93896; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_8_V_address1 = 64'd1; + end else begin + acc_8_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2200 == ap_CS_fsm) | (ap_ST_fsm_state2162 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1901 == ap_CS_fsm) | (ap_ST_fsm_state1863 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1600 == ap_CS_fsm) | (ap_ST_fsm_state1562 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1299 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_8_V_ce0 = 1'b1; + end else begin + acc_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2237 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2126 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1938 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1826 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1637 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1525 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1336 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1261 == ap_CS_fsm) | (ap_ST_fsm_state1224 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_8_V_ce1 = 1'b1; + end else begin + acc_8_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2200 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_15_fu_88798_p2; + end else if ((ap_ST_fsm_state2162 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_9_fu_88499_p2; + end else if ((ap_ST_fsm_state1901 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_10_fu_86707_p2; + end else if ((ap_ST_fsm_state1863 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_5_fu_86408_p2; + end else if ((ap_ST_fsm_state1600 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_11_fu_84451_p2; + end else if ((ap_ST_fsm_state1562 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_6_fu_84152_p2; + end else if ((ap_ST_fsm_state1299 == ap_CS_fsm)) begin + acc_8_V_d0 = add_ln703_7_fu_82359_p2; + end else if (((ap_ST_fsm_state1180 == ap_CS_fsm) | (ap_ST_fsm_state1176 == ap_CS_fsm) | (ap_ST_fsm_state1171 == ap_CS_fsm) | (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + acc_8_V_d0 = 8'd0; + end else begin + acc_8_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2237 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_23_fu_88976_p2; + end else if ((ap_ST_fsm_state2126 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_4_fu_88260_p2; + end else if ((ap_ST_fsm_state1938 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_18_fu_86885_p2; + end else if ((ap_ST_fsm_state1826 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_1_fu_86169_p2; + end else if ((ap_ST_fsm_state1637 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_19_fu_84629_p2; + end else if ((ap_ST_fsm_state1525 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_2_fu_83913_p2; + end else if ((ap_ST_fsm_state1336 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_14_fu_82538_p2; + end else if ((ap_ST_fsm_state1261 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_3_fu_82193_p2; + end else if ((ap_ST_fsm_state1224 == ap_CS_fsm)) begin + acc_8_V_d1 = add_ln703_fu_81953_p2; + end else begin + acc_8_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((6'd8 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2200 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd8) & (ap_ST_fsm_state1901 == ap_CS_fsm)) | ((6'd8 == add_ln1265_reg_96098) & (ap_ST_fsm_state1600 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd8) & (ap_ST_fsm_state1299 == ap_CS_fsm)) | ((icmp_ln248_3_fu_81329_p2 == 1'd0) & (6'd8 == add_ln203_7_fu_81344_p2) & (ap_ST_fsm_state1180 == ap_CS_fsm)) | ((icmp_ln248_1_fu_81191_p2 == 1'd0) & (or_ln203_1_fu_81206_p3 == 6'd8) & (ap_ST_fsm_state1176 == ap_CS_fsm)) | ((icmp_ln248_2_fu_80953_p2 == 1'd0) & (6'd8 == add_ln203_3_fu_80968_p2) & (ap_ST_fsm_state1171 == ap_CS_fsm)) | ((icmp_ln248_fu_80819_p2 == 1'd0) & (or_ln2_fu_80834_p3 == 6'd8) & (ap_ST_fsm_state1167 == ap_CS_fsm)) | ((6'd8 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2162 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd8) & (ap_ST_fsm_state1863 == ap_CS_fsm)) | ((6'd8 == add_ln1265_reg_96098) & (ap_ST_fsm_state1562 == ap_CS_fsm)))) begin + acc_8_V_we0 = 1'b1; + end else begin + acc_8_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((6'd8 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2126 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd8) & (ap_ST_fsm_state1826 == ap_CS_fsm)) | ((6'd8 == add_ln1265_reg_96098) & (ap_ST_fsm_state1525 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd8) & (ap_ST_fsm_state1224 == ap_CS_fsm)) | ((6'd8 == add_ln1265_1_reg_100172) & (ap_ST_fsm_state2237 == ap_CS_fsm)) | ((or_ln1265_1_reg_98331 == 6'd8) & (ap_ST_fsm_state1938 == ap_CS_fsm)) | ((6'd8 == add_ln1265_reg_96098) & (ap_ST_fsm_state1637 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd8) & (ap_ST_fsm_state1336 == ap_CS_fsm)) | ((or_ln3_reg_94268 == 6'd8) & (ap_ST_fsm_state1261 == ap_CS_fsm)))) begin + acc_8_V_we1 = 1'b1; + end else begin + acc_8_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd48; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd46; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd44; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd42; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd40; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd38; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd36; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd34; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd32; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd30; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd28; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd26; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + acc_9_V_address0 = acc_9_V_addr_56_reg_98700; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + acc_9_V_address0 = acc_9_V_addr_58_reg_100542; + end else if (((ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm))) begin + acc_9_V_address0 = acc_9_V_addr_53_reg_98149; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + acc_9_V_address0 = acc_9_V_addr_54_reg_94636; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + acc_9_V_address0 = acc_9_V_addr_57_reg_96468; + end else if (((ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm))) begin + acc_9_V_address0 = acc_9_V_addr_50_reg_94088; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_9_V_address0 = 64'd0; + end else if ((ap_ST_fsm_state1181 == ap_CS_fsm)) begin + acc_9_V_address0 = acc_9_V_addr_55_reg_93035; + end else if ((ap_ST_fsm_state1177 == ap_CS_fsm)) begin + acc_9_V_address0 = acc_9_V_addr_51_reg_92858; + end else if ((ap_ST_fsm_state1172 == ap_CS_fsm)) begin + acc_9_V_address0 = acc_9_V_addr_52_reg_92487; + end else if ((ap_ST_fsm_state1168 == ap_CS_fsm)) begin + acc_9_V_address0 = acc_9_V_addr_49_reg_92303; + end else begin + acc_9_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd47; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd45; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd43; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd41; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd39; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd37; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd35; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd33; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd31; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd29; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd27; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd25; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd23; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd21; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd19; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd17; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd15; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd13; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd11; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + acc_9_V_address1 = acc_9_V_addr_56_reg_98700; + end else if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + acc_9_V_address1 = acc_9_V_addr_58_reg_100542; + end else if (((ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm))) begin + acc_9_V_address1 = acc_9_V_addr_53_reg_98149; + end else if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + acc_9_V_address1 = acc_9_V_addr_54_reg_94636; + end else if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + acc_9_V_address1 = acc_9_V_addr_57_reg_96468; + end else if (((ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm))) begin + acc_9_V_address1 = acc_9_V_addr_50_reg_94088; + end else if ((ap_ST_fsm_state1184 == ap_CS_fsm)) begin + acc_9_V_address1 = 64'd1; + end else begin + acc_9_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2051 == ap_CS_fsm) | (ap_ST_fsm_state2013 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state1450 == ap_CS_fsm) | (ap_ST_fsm_state1412 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm) | (ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_9_V_ce0 = 1'b1; + end else begin + acc_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm) | (ap_ST_fsm_state2314 == ap_CS_fsm) | (ap_ST_fsm_state2164 == ap_CS_fsm) | (ap_ST_fsm_state2087 == ap_CS_fsm) | (ap_ST_fsm_state2015 == ap_CS_fsm) | (ap_ST_fsm_state1977 == ap_CS_fsm) | (ap_ST_fsm_state1865 == ap_CS_fsm) | (ap_ST_fsm_state1714 == ap_CS_fsm) | (ap_ST_fsm_state1564 == ap_CS_fsm) | (ap_ST_fsm_state1486 == ap_CS_fsm) | (ap_ST_fsm_state1414 == ap_CS_fsm) | (ap_ST_fsm_state1375 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1263 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + acc_9_V_ce1 = 1'b1; + end else begin + acc_9_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2051 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_25_fu_87675_p2; + end else if ((ap_ST_fsm_state2013 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_20_fu_87392_p2; + end else if ((ap_ST_fsm_state1450 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_22_fu_83328_p2; + end else if ((ap_ST_fsm_state1412 == ap_CS_fsm)) begin + acc_9_V_d0 = add_ln703_16_fu_83045_p2; + end else if (((ap_ST_fsm_state1181 == ap_CS_fsm) | (ap_ST_fsm_state1177 == ap_CS_fsm) | (ap_ST_fsm_state1172 == ap_CS_fsm) | (ap_ST_fsm_state1168 == ap_CS_fsm))) begin + acc_9_V_d0 = 8'd254; + end else begin + acc_9_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2087 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_29_fu_87837_p2; + end else if ((ap_ST_fsm_state1977 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_12_fu_87201_p2; + end else if ((ap_ST_fsm_state1486 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_27_fu_83490_p2; + end else if ((ap_ST_fsm_state1375 == ap_CS_fsm)) begin + acc_9_V_d1 = add_ln703_8_fu_82854_p2; + end else begin + acc_9_V_d1 = 'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd9) & (ap_ST_fsm_state2051 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd9) & (ap_ST_fsm_state1450 == ap_CS_fsm)) | ((or_ln203_5_fu_81425_p3 == 6'd9) & (ap_ST_fsm_state1181 == ap_CS_fsm)) | ((or_ln203_3_fu_81311_p3 == 6'd9) & (ap_ST_fsm_state1177 == ap_CS_fsm)) | ((or_ln203_4_fu_81049_p3 == 6'd9) & (ap_ST_fsm_state1172 == ap_CS_fsm)) | ((or_ln203_2_fu_80935_p3 == 6'd9) & (ap_ST_fsm_state1168 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd9) & (ap_ST_fsm_state2013 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd9) & (ap_ST_fsm_state1412 == ap_CS_fsm)))) begin + acc_9_V_we0 = 1'b1; + end else begin + acc_9_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((or_ln1265_3_reg_98943 == 6'd9) & (ap_ST_fsm_state2087 == ap_CS_fsm)) | ((or_ln1265_3_reg_98943 == 6'd9) & (ap_ST_fsm_state1977 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd9) & (ap_ST_fsm_state1486 == ap_CS_fsm)) | ((or_ln1265_2_reg_94874 == 6'd9) & (ap_ST_fsm_state1375 == ap_CS_fsm)))) begin + acc_9_V_we1 = 1'b1; + end else begin + acc_9_V_we1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | ((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0)))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1058 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_15_fu_80284_p1; + end else if ((ap_ST_fsm_state1054 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_11_fu_79996_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_8_fu_79472_p1; + end else if ((ap_ST_fsm_state910 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_3_fu_79184_p1; + end else if ((ap_ST_fsm_state768 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_13_fu_78603_p1; + end else if ((ap_ST_fsm_state764 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_9_fu_78305_p1; + end else if ((ap_ST_fsm_state624 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_5_fu_77776_p1; + end else if ((ap_ST_fsm_state620 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_1_fu_77482_p1; + end else if ((ap_ST_fsm_state477 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_14_fu_76823_p1; + end else if ((ap_ST_fsm_state473 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_10_fu_76535_p1; + end else if ((ap_ST_fsm_state333 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_6_fu_76005_p1; + end else if ((ap_ST_fsm_state329 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_2_fu_75720_p1; + end else if ((ap_ST_fsm_state187 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_12_fu_75143_p1; + end else if ((ap_ST_fsm_state183 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_7_fu_74845_p1; + end else if ((ap_ST_fsm_state43 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_4_fu_74315_p1; + end else if ((ap_ST_fsm_state39 == ap_CS_fsm)) begin + data_V_address0 = zext_ln1116_fu_74020_p1; + end else begin + data_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state910 == ap_CS_fsm) | (ap_ST_fsm_state768 == ap_CS_fsm) | (ap_ST_fsm_state764 == ap_CS_fsm) | (ap_ST_fsm_state624 == ap_CS_fsm) | (ap_ST_fsm_state620 == ap_CS_fsm) | (ap_ST_fsm_state477 == ap_CS_fsm) | (ap_ST_fsm_state473 == ap_CS_fsm) | (ap_ST_fsm_state43 == ap_CS_fsm) | (ap_ST_fsm_state39 == ap_CS_fsm) | (ap_ST_fsm_state333 == ap_CS_fsm) | (ap_ST_fsm_state329 == ap_CS_fsm) | (ap_ST_fsm_state187 == ap_CS_fsm) | (ap_ST_fsm_state183 == ap_CS_fsm) | (ap_ST_fsm_state1058 == ap_CS_fsm) | (ap_ST_fsm_state1054 == ap_CS_fsm))) begin + data_V_ce0 = 1'b1; + end else begin + data_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state7 == ap_CS_fsm) & ((or_ln223_3_fu_73970_p2 == 1'd1) | (or_ln223_reg_90189 == 1'd1))) | ((ap_ST_fsm_state7 == ap_CS_fsm) & (or_ln223_3_fu_73970_p2 == 1'd0) & (or_ln223_reg_90189 == 1'd0)))) begin + grp_fu_73372_ap_start = 1'b1; + end else begin + grp_fu_73372_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state43 == ap_CS_fsm) & (((or_ln223_9_fu_74283_p2 == 1'd1) & (icmp_ln208_fu_74233_p2 == 1'd0)) | ((icmp_ln208_fu_74233_p2 == 1'd0) & (or_ln223_reg_90189 == 1'd1)))) | ((ap_ST_fsm_state43 == ap_CS_fsm) & (or_ln223_9_fu_74283_p2 == 1'd0) & (icmp_ln208_fu_74233_p2 == 1'd0) & (or_ln223_reg_90189 == 1'd0)))) begin + grp_fu_73378_ap_start = 1'b1; + end else begin + grp_fu_73378_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state151 == ap_CS_fsm) & ((or_ln223_14_fu_74795_p2 == 1'd1) | (or_ln223_8_reg_90312 == 1'd1))) | ((or_ln223_14_fu_74795_p2 == 1'd0) & (or_ln223_8_reg_90312 == 1'd0) & (ap_ST_fsm_state151 == ap_CS_fsm)))) begin + grp_fu_73388_ap_start = 1'b1; + end else begin + grp_fu_73388_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state187 == ap_CS_fsm) & (((or_ln223_20_fu_75107_p2 == 1'd1) & (icmp_ln208_4_fu_75057_p2 == 1'd0)) | ((or_ln223_8_reg_90312 == 1'd1) & (icmp_ln208_4_fu_75057_p2 == 1'd0)))) | ((or_ln223_20_fu_75107_p2 == 1'd0) & (icmp_ln208_4_fu_75057_p2 == 1'd0) & (or_ln223_8_reg_90312 == 1'd0) & (ap_ST_fsm_state187 == ap_CS_fsm)))) begin + grp_fu_73394_ap_start = 1'b1; + end else begin + grp_fu_73394_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state297 == ap_CS_fsm) & ((or_ln223_6_fu_75670_p2 == 1'd1) | (or_ln223_2_reg_90649 == 1'd1))) | ((or_ln223_6_fu_75670_p2 == 1'd0) & (or_ln223_2_reg_90649 == 1'd0) & (ap_ST_fsm_state297 == ap_CS_fsm)))) begin + grp_fu_73404_ap_start = 1'b1; + end else begin + grp_fu_73404_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state333 == ap_CS_fsm) & (((or_ln223_13_fu_75973_p2 == 1'd1) & (icmp_ln208_2_fu_75923_p2 == 1'd0)) | ((or_ln223_2_reg_90649 == 1'd1) & (icmp_ln208_2_fu_75923_p2 == 1'd0)))) | ((ap_ST_fsm_state333 == ap_CS_fsm) & (or_ln223_13_fu_75973_p2 == 1'd0) & (icmp_ln208_2_fu_75923_p2 == 1'd0) & (or_ln223_2_reg_90649 == 1'd0)))) begin + grp_fu_73410_ap_start = 1'b1; + end else begin + grp_fu_73410_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state441 == ap_CS_fsm) & ((or_ln223_18_fu_76485_p2 == 1'd1) | (or_ln223_12_reg_90772 == 1'd1))) | ((ap_ST_fsm_state441 == ap_CS_fsm) & (or_ln223_18_fu_76485_p2 == 1'd0) & (or_ln223_12_reg_90772 == 1'd0)))) begin + grp_fu_73420_ap_start = 1'b1; + end else begin + grp_fu_73420_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state477 == ap_CS_fsm) & (((or_ln223_22_fu_76787_p2 == 1'd1) & (icmp_ln208_6_fu_76737_p2 == 1'd0)) | ((or_ln223_12_reg_90772 == 1'd1) & (icmp_ln208_6_fu_76737_p2 == 1'd0)))) | ((ap_ST_fsm_state477 == ap_CS_fsm) & (or_ln223_22_fu_76787_p2 == 1'd0) & (icmp_ln208_6_fu_76737_p2 == 1'd0) & (or_ln223_12_reg_90772 == 1'd0)))) begin + grp_fu_73426_ap_start = 1'b1; + end else begin + grp_fu_73426_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state588 == ap_CS_fsm) & ((or_ln223_5_fu_77432_p2 == 1'd1) | (or_ln223_1_reg_91176 == 1'd1))) | ((ap_ST_fsm_state588 == ap_CS_fsm) & (or_ln223_5_fu_77432_p2 == 1'd0) & (or_ln223_1_reg_91176 == 1'd0)))) begin + grp_fu_73436_ap_start = 1'b1; + end else begin + grp_fu_73436_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state624 == ap_CS_fsm) & (((or_ln223_11_fu_77744_p2 == 1'd1) & (icmp_ln208_1_fu_77694_p2 == 1'd0)) | ((or_ln223_1_reg_91176 == 1'd1) & (icmp_ln208_1_fu_77694_p2 == 1'd0)))) | ((ap_ST_fsm_state624 == ap_CS_fsm) & (or_ln223_11_fu_77744_p2 == 1'd0) & (icmp_ln208_1_fu_77694_p2 == 1'd0) & (or_ln223_1_reg_91176 == 1'd0)))) begin + grp_fu_73442_ap_start = 1'b1; + end else begin + grp_fu_73442_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state732 == ap_CS_fsm) & ((or_ln223_17_fu_78255_p2 == 1'd1) | (or_ln223_10_reg_91305 == 1'd1))) | ((ap_ST_fsm_state732 == ap_CS_fsm) & (or_ln223_17_fu_78255_p2 == 1'd0) & (or_ln223_10_reg_91305 == 1'd0)))) begin + grp_fu_73452_ap_start = 1'b1; + end else begin + grp_fu_73452_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state768 == ap_CS_fsm) & (((or_ln223_21_fu_78567_p2 == 1'd1) & (icmp_ln208_5_fu_78517_p2 == 1'd0)) | ((or_ln223_10_reg_91305 == 1'd1) & (icmp_ln208_5_fu_78517_p2 == 1'd0)))) | ((ap_ST_fsm_state768 == ap_CS_fsm) & (or_ln223_21_fu_78567_p2 == 1'd0) & (icmp_ln208_5_fu_78517_p2 == 1'd0) & (or_ln223_10_reg_91305 == 1'd0)))) begin + grp_fu_73458_ap_start = 1'b1; + end else begin + grp_fu_73458_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state878 == ap_CS_fsm) & ((or_ln223_7_fu_79134_p2 == 1'd1) | (or_ln223_4_reg_91642 == 1'd1))) | ((ap_ST_fsm_state878 == ap_CS_fsm) & (or_ln223_7_fu_79134_p2 == 1'd0) & (or_ln223_4_reg_91642 == 1'd0)))) begin + grp_fu_73468_ap_start = 1'b1; + end else begin + grp_fu_73468_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state914 == ap_CS_fsm) & (((or_ln223_16_fu_79436_p2 == 1'd1) & (icmp_ln208_3_fu_79386_p2 == 1'd0)) | ((or_ln223_4_reg_91642 == 1'd1) & (icmp_ln208_3_fu_79386_p2 == 1'd0)))) | ((ap_ST_fsm_state914 == ap_CS_fsm) & (or_ln223_16_fu_79436_p2 == 1'd0) & (icmp_ln208_3_fu_79386_p2 == 1'd0) & (or_ln223_4_reg_91642 == 1'd0)))) begin + grp_fu_73474_ap_start = 1'b1; + end else begin + grp_fu_73474_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state1022 == ap_CS_fsm) & ((or_ln223_19_fu_79946_p2 == 1'd1) | (or_ln223_15_reg_91776 == 1'd1))) | ((or_ln223_19_fu_79946_p2 == 1'd0) & (or_ln223_15_reg_91776 == 1'd0) & (ap_ST_fsm_state1022 == ap_CS_fsm)))) begin + grp_fu_73484_ap_start = 1'b1; + end else begin + grp_fu_73484_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state1058 == ap_CS_fsm) & (((or_ln223_23_fu_80248_p2 == 1'd1) & (icmp_ln208_7_fu_80198_p2 == 1'd0)) | ((or_ln223_15_reg_91776 == 1'd1) & (icmp_ln208_7_fu_80198_p2 == 1'd0)))) | ((or_ln223_23_fu_80248_p2 == 1'd0) & (icmp_ln208_7_fu_80198_p2 == 1'd0) & (or_ln223_15_reg_91776 == 1'd0) & (ap_ST_fsm_state1058 == ap_CS_fsm)))) begin + grp_fu_73490_ap_start = 1'b1; + end else begin + grp_fu_73490_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1188 == ap_CS_fsm)) begin + grp_fu_81835_ap_start = 1'b1; + end else begin + grp_fu_81835_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_fu_81997_p2 == 1'd0) & (ap_ST_fsm_state1225 == ap_CS_fsm))) begin + grp_fu_82008_ap_start = 1'b1; + end else begin + grp_fu_82008_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1263 == ap_CS_fsm)) begin + grp_fu_82241_ap_start = 1'b1; + end else begin + grp_fu_82241_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_4_fu_82403_p2 == 1'd0) & (ap_ST_fsm_state1300 == ap_CS_fsm))) begin + grp_fu_82414_ap_start = 1'b1; + end else begin + grp_fu_82414_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1339 == ap_CS_fsm)) begin + grp_fu_82603_ap_start = 1'b1; + end else begin + grp_fu_82603_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_5_fu_82881_p2 == 1'd0) & (ap_ST_fsm_state1376 == ap_CS_fsm))) begin + grp_fu_82892_ap_start = 1'b1; + end else begin + grp_fu_82892_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1414 == ap_CS_fsm)) begin + grp_fu_83077_ap_start = 1'b1; + end else begin + grp_fu_83077_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_12_fu_83355_p2 == 1'd0) & (ap_ST_fsm_state1450 == ap_CS_fsm))) begin + grp_fu_83366_ap_start = 1'b1; + end else begin + grp_fu_83366_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1489 == ap_CS_fsm)) begin + grp_fu_83662_ap_start = 1'b1; + end else begin + grp_fu_83662_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_2_fu_83956_p2 == 1'd0) & (ap_ST_fsm_state1526 == ap_CS_fsm))) begin + grp_fu_83967_ap_start = 1'b1; + end else begin + grp_fu_83967_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1564 == ap_CS_fsm)) begin + grp_fu_84200_ap_start = 1'b1; + end else begin + grp_fu_84200_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_7_fu_84494_p2 == 1'd0) & (ap_ST_fsm_state1601 == ap_CS_fsm))) begin + grp_fu_84505_ap_start = 1'b1; + end else begin + grp_fu_84505_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1640 == ap_CS_fsm)) begin + grp_fu_84694_ap_start = 1'b1; + end else begin + grp_fu_84694_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_9_fu_84971_p2 == 1'd0) & (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + grp_fu_84982_ap_start = 1'b1; + end else begin + grp_fu_84982_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1714 == ap_CS_fsm)) begin + grp_fu_85166_ap_start = 1'b1; + end else begin + grp_fu_85166_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_14_fu_85443_p2 == 1'd0) & (ap_ST_fsm_state1750 == ap_CS_fsm))) begin + grp_fu_85454_ap_start = 1'b1; + end else begin + grp_fu_85454_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1790 == ap_CS_fsm)) begin + grp_fu_85918_ap_start = 1'b1; + end else begin + grp_fu_85918_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_1_fu_86212_p2 == 1'd0) & (ap_ST_fsm_state1827 == ap_CS_fsm))) begin + grp_fu_86223_ap_start = 1'b1; + end else begin + grp_fu_86223_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1865 == ap_CS_fsm)) begin + grp_fu_86456_ap_start = 1'b1; + end else begin + grp_fu_86456_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_6_fu_86750_p2 == 1'd0) & (ap_ST_fsm_state1902 == ap_CS_fsm))) begin + grp_fu_86761_ap_start = 1'b1; + end else begin + grp_fu_86761_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1941 == ap_CS_fsm)) begin + grp_fu_86950_ap_start = 1'b1; + end else begin + grp_fu_86950_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_8_fu_87228_p2 == 1'd0) & (ap_ST_fsm_state1977 == ap_CS_fsm))) begin + grp_fu_87239_ap_start = 1'b1; + end else begin + grp_fu_87239_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2015 == ap_CS_fsm)) begin + grp_fu_87424_ap_start = 1'b1; + end else begin + grp_fu_87424_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_13_fu_87702_p2 == 1'd0) & (ap_ST_fsm_state2051 == ap_CS_fsm))) begin + grp_fu_87713_ap_start = 1'b1; + end else begin + grp_fu_87713_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2090 == ap_CS_fsm)) begin + grp_fu_88009_ap_start = 1'b1; + end else begin + grp_fu_88009_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_3_fu_88303_p2 == 1'd0) & (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + grp_fu_88314_ap_start = 1'b1; + end else begin + grp_fu_88314_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2164 == ap_CS_fsm)) begin + grp_fu_88547_ap_start = 1'b1; + end else begin + grp_fu_88547_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_10_fu_88841_p2 == 1'd0) & (ap_ST_fsm_state2201 == ap_CS_fsm))) begin + grp_fu_88852_ap_start = 1'b1; + end else begin + grp_fu_88852_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2240 == ap_CS_fsm)) begin + grp_fu_89041_ap_start = 1'b1; + end else begin + grp_fu_89041_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_11_fu_89318_p2 == 1'd0) & (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + grp_fu_89329_ap_start = 1'b1; + end else begin + grp_fu_89329_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2314 == ap_CS_fsm)) begin + grp_fu_89513_ap_start = 1'b1; + end else begin + grp_fu_89513_ap_start = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln268_15_fu_89790_p2 == 1'd0) & (ap_ST_fsm_state2350 == ap_CS_fsm))) begin + grp_fu_89801_ap_start = 1'b1; + end else begin + grp_fu_89801_ap_start = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_0_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_0_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_0_V_ce0 = 1'b1; + end else begin + mult_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_0_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_0_V_d0 = trunc_ln_reg_90250; + end else begin + mult_0_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd0) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd0) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd0) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd0) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd0) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd0)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd0)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd0)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd0)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd0)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd0)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd0)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd0)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd0)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd0)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd0)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd0)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd0)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd0)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd0)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd0)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd0)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd0)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd0)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd0)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd0)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd0)) | ((trunc_ln203_20_fu_75012_p1 == 6'd0) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd0) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd0) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd0)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd0)))) begin + mult_0_V_we0 = 1'b1; + end else begin + mult_0_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_10_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_10_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_10_V_ce0 = 1'b1; + end else begin + mult_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_10_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_10_V_d0 = trunc_ln_reg_90250; + end else begin + mult_10_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd10) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd10) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd10) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd10) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd10) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd10)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd10)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd10)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd10)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd10)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd10)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd10)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd10)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd10)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd10)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd10)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd10)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd10)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd10)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd10)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd10)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd10)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd10)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd10)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd10)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd10)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd10)) | ((trunc_ln203_20_fu_75012_p1 == 6'd10) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd10) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd10) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd10)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd10)))) begin + mult_10_V_we0 = 1'b1; + end else begin + mult_10_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_11_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_11_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_11_V_ce0 = 1'b1; + end else begin + mult_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_11_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_11_V_d0 = trunc_ln_reg_90250; + end else begin + mult_11_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd11) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd11) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd11) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd11) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd11) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd11)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd11)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd11)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd11)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd11)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd11)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd11)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd11)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd11)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd11)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd11)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd11)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd11)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd11)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd11)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd11)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd11)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd11)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd11)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd11)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd11)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd11)) | ((trunc_ln203_20_fu_75012_p1 == 6'd11) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd11) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd11) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd11)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd11)))) begin + mult_11_V_we0 = 1'b1; + end else begin + mult_11_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_12_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_12_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_12_V_ce0 = 1'b1; + end else begin + mult_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_12_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_12_V_d0 = trunc_ln_reg_90250; + end else begin + mult_12_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd12) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd12) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd12) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd12) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd12) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd12)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd12)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd12)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd12)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd12)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd12)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd12)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd12)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd12)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd12)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd12)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd12)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd12)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd12)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd12)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd12)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd12)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd12)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd12)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd12)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd12)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd12)) | ((trunc_ln203_20_fu_75012_p1 == 6'd12) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd12) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd12) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd12)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd12)))) begin + mult_12_V_we0 = 1'b1; + end else begin + mult_12_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_13_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_13_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_13_V_ce0 = 1'b1; + end else begin + mult_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_13_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_13_V_d0 = trunc_ln_reg_90250; + end else begin + mult_13_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd13) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd13) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd13) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd13) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd13) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd13)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd13)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd13)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd13)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd13)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd13)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd13)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd13)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd13)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd13)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd13)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd13)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd13)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd13)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd13)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd13)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd13)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd13)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd13)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd13)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd13)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd13)) | ((trunc_ln203_20_fu_75012_p1 == 6'd13) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd13) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd13) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd13)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd13)))) begin + mult_13_V_we0 = 1'b1; + end else begin + mult_13_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_14_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_14_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_14_V_ce0 = 1'b1; + end else begin + mult_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_14_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_14_V_d0 = trunc_ln_reg_90250; + end else begin + mult_14_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd14) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd14) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd14) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd14) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd14) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd14)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd14)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd14)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd14)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd14)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd14)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd14)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd14)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd14)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd14)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd14)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd14)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd14)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd14)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd14)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd14)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd14)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd14)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd14)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd14)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd14)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd14)) | ((trunc_ln203_20_fu_75012_p1 == 6'd14) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd14) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd14) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd14)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd14)))) begin + mult_14_V_we0 = 1'b1; + end else begin + mult_14_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_15_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_15_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_15_V_ce0 = 1'b1; + end else begin + mult_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_15_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_15_V_d0 = trunc_ln_reg_90250; + end else begin + mult_15_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd15) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd15) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd15) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd15) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd15) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd15)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd15)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd15)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd15)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd15)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd15)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd15)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd15)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd15)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd15)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd15)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd15)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd15)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd15)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd15)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd15)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd15)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd15)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd15)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd15)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd15)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd15)) | ((trunc_ln203_20_fu_75012_p1 == 6'd15) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd15) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd15) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd15)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd15)))) begin + mult_15_V_we0 = 1'b1; + end else begin + mult_15_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_16_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_16_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_16_V_ce0 = 1'b1; + end else begin + mult_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_16_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_16_V_d0 = trunc_ln_reg_90250; + end else begin + mult_16_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd16) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd16) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd16) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd16) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd16) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd16)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd16)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd16)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd16)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd16)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd16)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd16)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd16)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd16)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd16)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd16)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd16)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd16)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd16)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd16)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd16)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd16)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd16)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd16)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd16)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd16)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd16)) | ((trunc_ln203_20_fu_75012_p1 == 6'd16) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd16) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd16) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd16)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd16)))) begin + mult_16_V_we0 = 1'b1; + end else begin + mult_16_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_17_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_17_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_17_V_ce0 = 1'b1; + end else begin + mult_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_17_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_17_V_d0 = trunc_ln_reg_90250; + end else begin + mult_17_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd17) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd17) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd17) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd17) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd17) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd17)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd17)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd17)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd17)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd17)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd17)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd17)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd17)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd17)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd17)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd17)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd17)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd17)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd17)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd17)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd17)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd17)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd17)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd17)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd17)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd17)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd17)) | ((trunc_ln203_20_fu_75012_p1 == 6'd17) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd17) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd17) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd17)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd17)))) begin + mult_17_V_we0 = 1'b1; + end else begin + mult_17_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_18_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_18_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_18_V_ce0 = 1'b1; + end else begin + mult_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_18_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_18_V_d0 = trunc_ln_reg_90250; + end else begin + mult_18_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd18) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd18) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd18) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd18) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd18) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd18)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd18)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd18)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd18)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd18)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd18)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd18)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd18)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd18)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd18)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd18)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd18)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd18)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd18)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd18)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd18)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd18)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd18)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd18)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd18)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd18)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd18)) | ((trunc_ln203_20_fu_75012_p1 == 6'd18) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd18) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd18) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd18)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd18)))) begin + mult_18_V_we0 = 1'b1; + end else begin + mult_18_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_19_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_19_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_19_V_ce0 = 1'b1; + end else begin + mult_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_19_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_19_V_d0 = trunc_ln_reg_90250; + end else begin + mult_19_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd19) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd19) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd19) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd19) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd19) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd19)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd19)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd19)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd19)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd19)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd19)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd19)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd19)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd19)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd19)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd19)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd19)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd19)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd19)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd19)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd19)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd19)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd19)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd19)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd19)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd19)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd19)) | ((trunc_ln203_20_fu_75012_p1 == 6'd19) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd19) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd19) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd19)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd19)))) begin + mult_19_V_we0 = 1'b1; + end else begin + mult_19_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_1_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_1_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_1_V_ce0 = 1'b1; + end else begin + mult_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_1_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_1_V_d0 = trunc_ln_reg_90250; + end else begin + mult_1_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd1) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd1) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd1) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd1) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd1) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd1)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd1)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd1)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd1)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd1)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd1)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd1)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd1)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd1)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd1)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd1)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd1)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd1)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd1)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd1)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd1)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd1)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd1)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd1)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd1)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd1)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd1)) | ((trunc_ln203_20_fu_75012_p1 == 6'd1) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd1) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd1) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd1)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd1)))) begin + mult_1_V_we0 = 1'b1; + end else begin + mult_1_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_20_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_20_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_20_V_ce0 = 1'b1; + end else begin + mult_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_20_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_20_V_d0 = trunc_ln_reg_90250; + end else begin + mult_20_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd20) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd20) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd20) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd20) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd20) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd20)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd20)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd20)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd20)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd20)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd20)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd20)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd20)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd20)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd20)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd20)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd20)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd20)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd20)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd20)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd20)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd20)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd20)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd20)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd20)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd20)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd20)) | ((trunc_ln203_20_fu_75012_p1 == 6'd20) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd20) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd20) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd20)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd20)))) begin + mult_20_V_we0 = 1'b1; + end else begin + mult_20_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_21_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_21_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_21_V_ce0 = 1'b1; + end else begin + mult_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_21_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_21_V_d0 = trunc_ln_reg_90250; + end else begin + mult_21_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd21) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd21) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd21) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd21) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd21) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd21)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd21)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd21)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd21)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd21)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd21)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd21)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd21)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd21)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd21)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd21)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd21)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd21)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd21)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd21)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd21)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd21)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd21)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd21)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd21)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd21)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd21)) | ((trunc_ln203_20_fu_75012_p1 == 6'd21) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd21) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd21) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd21)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd21)))) begin + mult_21_V_we0 = 1'b1; + end else begin + mult_21_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_22_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_22_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_22_V_ce0 = 1'b1; + end else begin + mult_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_22_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_22_V_d0 = trunc_ln_reg_90250; + end else begin + mult_22_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd22) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd22) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd22) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd22) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd22) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd22)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd22)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd22)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd22)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd22)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd22)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd22)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd22)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd22)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd22)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd22)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd22)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd22)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd22)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd22)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd22)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd22)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd22)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd22)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd22)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd22)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd22)) | ((trunc_ln203_20_fu_75012_p1 == 6'd22) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd22) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd22) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd22)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd22)))) begin + mult_22_V_we0 = 1'b1; + end else begin + mult_22_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_23_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_23_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_23_V_ce0 = 1'b1; + end else begin + mult_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_23_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_23_V_d0 = trunc_ln_reg_90250; + end else begin + mult_23_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd23) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd23) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd23) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd23) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd23) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd23)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd23)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd23)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd23)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd23)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd23)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd23)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd23)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd23)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd23)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd23)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd23)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd23)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd23)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd23)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd23)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd23)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd23)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd23)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd23)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd23)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd23)) | ((trunc_ln203_20_fu_75012_p1 == 6'd23) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd23) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd23) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd23)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd23)))) begin + mult_23_V_we0 = 1'b1; + end else begin + mult_23_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_24_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_24_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_24_V_ce0 = 1'b1; + end else begin + mult_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_24_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_24_V_d0 = trunc_ln_reg_90250; + end else begin + mult_24_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd24) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd24) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd24) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd24) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd24) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd24)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd24)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd24)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd24)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd24)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd24)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd24)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd24)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd24)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd24)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd24)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd24)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd24)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd24)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd24)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd24)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd24)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd24)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd24)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd24)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd24)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd24)) | ((trunc_ln203_20_fu_75012_p1 == 6'd24) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd24) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd24) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd24)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd24)))) begin + mult_24_V_we0 = 1'b1; + end else begin + mult_24_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_25_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_25_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_25_V_ce0 = 1'b1; + end else begin + mult_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_25_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_25_V_d0 = trunc_ln_reg_90250; + end else begin + mult_25_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd25) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd25) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd25) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd25) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd25) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd25)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd25)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd25)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd25)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd25)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd25)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd25)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd25)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd25)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd25)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd25)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd25)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd25)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd25)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd25)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd25)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd25)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd25)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd25)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd25)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd25)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd25)) | ((trunc_ln203_20_fu_75012_p1 == 6'd25) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd25) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd25) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd25)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd25)))) begin + mult_25_V_we0 = 1'b1; + end else begin + mult_25_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_26_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_26_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_26_V_ce0 = 1'b1; + end else begin + mult_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_26_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_26_V_d0 = trunc_ln_reg_90250; + end else begin + mult_26_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd26) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd26) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd26) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd26) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd26) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd26)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd26)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd26)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd26)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd26)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd26)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd26)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd26)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd26)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd26)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd26)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd26)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd26)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd26)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd26)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd26)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd26)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd26)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd26)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd26)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd26)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd26)) | ((trunc_ln203_20_fu_75012_p1 == 6'd26) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd26) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd26) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd26)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd26)))) begin + mult_26_V_we0 = 1'b1; + end else begin + mult_26_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_27_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_27_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_27_V_ce0 = 1'b1; + end else begin + mult_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_27_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_27_V_d0 = trunc_ln_reg_90250; + end else begin + mult_27_V_d0 = 'b0; + end +end + +always @ (*) begin + if (((~(trunc_ln203_35_fu_80582_p1 == 6'd0) & ~(trunc_ln203_35_fu_80582_p1 == 6'd1) & ~(trunc_ln203_35_fu_80582_p1 == 6'd2) & ~(trunc_ln203_35_fu_80582_p1 == 6'd3) & ~(trunc_ln203_35_fu_80582_p1 == 6'd4) & ~(trunc_ln203_35_fu_80582_p1 == 6'd5) & ~(trunc_ln203_35_fu_80582_p1 == 6'd6) & ~(trunc_ln203_35_fu_80582_p1 == 6'd7) & ~(trunc_ln203_35_fu_80582_p1 == 6'd8) & ~(trunc_ln203_35_fu_80582_p1 == 6'd9) & ~(trunc_ln203_35_fu_80582_p1 == 6'd10) & ~(trunc_ln203_35_fu_80582_p1 == 6'd11) & ~(trunc_ln203_35_fu_80582_p1 == 6'd12) & ~(trunc_ln203_35_fu_80582_p1 == 6'd13) & ~(trunc_ln203_35_fu_80582_p1 == 6'd14) & ~(trunc_ln203_35_fu_80582_p1 == 6'd15) & ~(trunc_ln203_35_fu_80582_p1 == 6'd16) & ~(trunc_ln203_35_fu_80582_p1 == 6'd17) & ~(trunc_ln203_35_fu_80582_p1 == 6'd18) & ~(trunc_ln203_35_fu_80582_p1 == 6'd19) & ~(trunc_ln203_35_fu_80582_p1 == 6'd20) & ~(trunc_ln203_35_fu_80582_p1 == 6'd21) & ~(trunc_ln203_35_fu_80582_p1 == 6'd22) & ~(trunc_ln203_35_fu_80582_p1 == 6'd23) & ~(trunc_ln203_35_fu_80582_p1 == 6'd24) & ~(trunc_ln203_35_fu_80582_p1 == 6'd25) & ~(trunc_ln203_35_fu_80582_p1 == 6'd26) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | (~(trunc_ln203_36_fu_80522_p1 == 6'd0) & ~(trunc_ln203_36_fu_80522_p1 == 6'd1) & ~(trunc_ln203_36_fu_80522_p1 == 6'd2) & ~(trunc_ln203_36_fu_80522_p1 == 6'd3) & ~(trunc_ln203_36_fu_80522_p1 == 6'd4) & ~(trunc_ln203_36_fu_80522_p1 == 6'd5) & ~(trunc_ln203_36_fu_80522_p1 == 6'd6) & ~(trunc_ln203_36_fu_80522_p1 == 6'd7) & ~(trunc_ln203_36_fu_80522_p1 == 6'd8) & ~(trunc_ln203_36_fu_80522_p1 == 6'd9) & ~(trunc_ln203_36_fu_80522_p1 == 6'd10) & ~(trunc_ln203_36_fu_80522_p1 == 6'd11) & ~(trunc_ln203_36_fu_80522_p1 == 6'd12) & ~(trunc_ln203_36_fu_80522_p1 == 6'd13) & ~(trunc_ln203_36_fu_80522_p1 == 6'd14) & ~(trunc_ln203_36_fu_80522_p1 == 6'd15) & ~(trunc_ln203_36_fu_80522_p1 == 6'd16) & ~(trunc_ln203_36_fu_80522_p1 == 6'd17) & ~(trunc_ln203_36_fu_80522_p1 == 6'd18) & ~(trunc_ln203_36_fu_80522_p1 == 6'd19) & ~(trunc_ln203_36_fu_80522_p1 == 6'd20) & ~(trunc_ln203_36_fu_80522_p1 == 6'd21) & ~(trunc_ln203_36_fu_80522_p1 == 6'd22) & ~(trunc_ln203_36_fu_80522_p1 == 6'd23) & ~(trunc_ln203_36_fu_80522_p1 == 6'd24) & ~(trunc_ln203_36_fu_80522_p1 == 6'd25) & ~(trunc_ln203_36_fu_80522_p1 == 6'd26) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | (~(trunc_ln203_27_fu_80331_p1 == 6'd0) & ~(trunc_ln203_27_fu_80331_p1 == 6'd1) & ~(trunc_ln203_27_fu_80331_p1 == 6'd2) & ~(trunc_ln203_27_fu_80331_p1 == 6'd3) & ~(trunc_ln203_27_fu_80331_p1 == 6'd4) & ~(trunc_ln203_27_fu_80331_p1 == 6'd5) & ~(trunc_ln203_27_fu_80331_p1 == 6'd6) & ~(trunc_ln203_27_fu_80331_p1 == 6'd7) & ~(trunc_ln203_27_fu_80331_p1 == 6'd8) & ~(trunc_ln203_27_fu_80331_p1 == 6'd9) & ~(trunc_ln203_27_fu_80331_p1 == 6'd10) & ~(trunc_ln203_27_fu_80331_p1 == 6'd11) & ~(trunc_ln203_27_fu_80331_p1 == 6'd12) & ~(trunc_ln203_27_fu_80331_p1 == 6'd13) & ~(trunc_ln203_27_fu_80331_p1 == 6'd14) & ~(trunc_ln203_27_fu_80331_p1 == 6'd15) & ~(trunc_ln203_27_fu_80331_p1 == 6'd16) & ~(trunc_ln203_27_fu_80331_p1 == 6'd17) & ~(trunc_ln203_27_fu_80331_p1 == 6'd18) & ~(trunc_ln203_27_fu_80331_p1 == 6'd19) & ~(trunc_ln203_27_fu_80331_p1 == 6'd20) & ~(trunc_ln203_27_fu_80331_p1 == 6'd21) & ~(trunc_ln203_27_fu_80331_p1 == 6'd22) & ~(trunc_ln203_27_fu_80331_p1 == 6'd23) & ~(trunc_ln203_27_fu_80331_p1 == 6'd24) & ~(trunc_ln203_27_fu_80331_p1 == 6'd25) & ~(trunc_ln203_27_fu_80331_p1 == 6'd26) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | (~(trunc_ln203_28_fu_80153_p1 == 6'd0) & ~(trunc_ln203_28_fu_80153_p1 == 6'd1) & ~(trunc_ln203_28_fu_80153_p1 == 6'd2) & ~(trunc_ln203_28_fu_80153_p1 == 6'd3) & ~(trunc_ln203_28_fu_80153_p1 == 6'd4) & ~(trunc_ln203_28_fu_80153_p1 == 6'd5) & ~(trunc_ln203_28_fu_80153_p1 == 6'd6) & ~(trunc_ln203_28_fu_80153_p1 == 6'd7) & ~(trunc_ln203_28_fu_80153_p1 == 6'd8) & ~(trunc_ln203_28_fu_80153_p1 == 6'd9) & ~(trunc_ln203_28_fu_80153_p1 == 6'd10) & ~(trunc_ln203_28_fu_80153_p1 == 6'd11) & ~(trunc_ln203_28_fu_80153_p1 == 6'd12) & ~(trunc_ln203_28_fu_80153_p1 == 6'd13) & ~(trunc_ln203_28_fu_80153_p1 == 6'd14) & ~(trunc_ln203_28_fu_80153_p1 == 6'd15) & ~(trunc_ln203_28_fu_80153_p1 == 6'd16) & ~(trunc_ln203_28_fu_80153_p1 == 6'd17) & ~(trunc_ln203_28_fu_80153_p1 == 6'd18) & ~(trunc_ln203_28_fu_80153_p1 == 6'd19) & ~(trunc_ln203_28_fu_80153_p1 == 6'd20) & ~(trunc_ln203_28_fu_80153_p1 == 6'd21) & ~(trunc_ln203_28_fu_80153_p1 == 6'd22) & ~(trunc_ln203_28_fu_80153_p1 == 6'd23) & ~(trunc_ln203_28_fu_80153_p1 == 6'd24) & ~(trunc_ln203_28_fu_80153_p1 == 6'd25) & ~(trunc_ln203_28_fu_80153_p1 == 6'd26) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | (~(trunc_ln203_21_fu_79869_p1 == 6'd0) & ~(trunc_ln203_21_fu_79869_p1 == 6'd1) & ~(trunc_ln203_21_fu_79869_p1 == 6'd2) & ~(trunc_ln203_21_fu_79869_p1 == 6'd3) & ~(trunc_ln203_21_fu_79869_p1 == 6'd4) & ~(trunc_ln203_21_fu_79869_p1 == 6'd5) & ~(trunc_ln203_21_fu_79869_p1 == 6'd6) & ~(trunc_ln203_21_fu_79869_p1 == 6'd7) & ~(trunc_ln203_21_fu_79869_p1 == 6'd8) & ~(trunc_ln203_21_fu_79869_p1 == 6'd9) & ~(trunc_ln203_21_fu_79869_p1 == 6'd10) & ~(trunc_ln203_21_fu_79869_p1 == 6'd11) & ~(trunc_ln203_21_fu_79869_p1 == 6'd12) & ~(trunc_ln203_21_fu_79869_p1 == 6'd13) & ~(trunc_ln203_21_fu_79869_p1 == 6'd14) & ~(trunc_ln203_21_fu_79869_p1 == 6'd15) & ~(trunc_ln203_21_fu_79869_p1 == 6'd16) & ~(trunc_ln203_21_fu_79869_p1 == 6'd17) & ~(trunc_ln203_21_fu_79869_p1 == 6'd18) & ~(trunc_ln203_21_fu_79869_p1 == 6'd19) & ~(trunc_ln203_21_fu_79869_p1 == 6'd20) & ~(trunc_ln203_21_fu_79869_p1 == 6'd21) & ~(trunc_ln203_21_fu_79869_p1 == 6'd22) & ~(trunc_ln203_21_fu_79869_p1 == 6'd23) & ~(trunc_ln203_21_fu_79869_p1 == 6'd24) & ~(trunc_ln203_21_fu_79869_p1 == 6'd25) & ~(trunc_ln203_21_fu_79869_p1 == 6'd26) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | (~(trunc_ln203_22_fu_79809_p1 == 6'd0) & ~(trunc_ln203_22_fu_79809_p1 == 6'd1) & ~(trunc_ln203_22_fu_79809_p1 == 6'd2) & ~(trunc_ln203_22_fu_79809_p1 == 6'd3) & ~(trunc_ln203_22_fu_79809_p1 == 6'd4) & ~(trunc_ln203_22_fu_79809_p1 == 6'd5) & ~(trunc_ln203_22_fu_79809_p1 == 6'd6) & ~(trunc_ln203_22_fu_79809_p1 == 6'd7) & ~(trunc_ln203_22_fu_79809_p1 == 6'd8) & ~(trunc_ln203_22_fu_79809_p1 == 6'd9) & ~(trunc_ln203_22_fu_79809_p1 == 6'd10) & ~(trunc_ln203_22_fu_79809_p1 == 6'd11) & ~(trunc_ln203_22_fu_79809_p1 == 6'd12) & ~(trunc_ln203_22_fu_79809_p1 == 6'd13) & ~(trunc_ln203_22_fu_79809_p1 == 6'd14) & ~(trunc_ln203_22_fu_79809_p1 == 6'd15) & ~(trunc_ln203_22_fu_79809_p1 == 6'd16) & ~(trunc_ln203_22_fu_79809_p1 == 6'd17) & ~(trunc_ln203_22_fu_79809_p1 == 6'd18) & ~(trunc_ln203_22_fu_79809_p1 == 6'd19) & ~(trunc_ln203_22_fu_79809_p1 == 6'd20) & ~(trunc_ln203_22_fu_79809_p1 == 6'd21) & ~(trunc_ln203_22_fu_79809_p1 == 6'd22) & ~(trunc_ln203_22_fu_79809_p1 == 6'd23) & ~(trunc_ln203_22_fu_79809_p1 == 6'd24) & ~(trunc_ln203_22_fu_79809_p1 == 6'd25) & ~(trunc_ln203_22_fu_79809_p1 == 6'd26) & (ap_ST_fsm_state984 == ap_CS_fsm)) | (~(trunc_ln203_11_fu_79618_p1 == 6'd0) & ~(trunc_ln203_11_fu_79618_p1 == 6'd1) & ~(trunc_ln203_11_fu_79618_p1 == 6'd2) & ~(trunc_ln203_11_fu_79618_p1 == 6'd3) & ~(trunc_ln203_11_fu_79618_p1 == 6'd4) & ~(trunc_ln203_11_fu_79618_p1 == 6'd5) & ~(trunc_ln203_11_fu_79618_p1 == 6'd6) & ~(trunc_ln203_11_fu_79618_p1 == 6'd7) & ~(trunc_ln203_11_fu_79618_p1 == 6'd8) & ~(trunc_ln203_11_fu_79618_p1 == 6'd9) & ~(trunc_ln203_11_fu_79618_p1 == 6'd10) & ~(trunc_ln203_11_fu_79618_p1 == 6'd11) & ~(trunc_ln203_11_fu_79618_p1 == 6'd12) & ~(trunc_ln203_11_fu_79618_p1 == 6'd13) & ~(trunc_ln203_11_fu_79618_p1 == 6'd14) & ~(trunc_ln203_11_fu_79618_p1 == 6'd15) & ~(trunc_ln203_11_fu_79618_p1 == 6'd16) & ~(trunc_ln203_11_fu_79618_p1 == 6'd17) & ~(trunc_ln203_11_fu_79618_p1 == 6'd18) & ~(trunc_ln203_11_fu_79618_p1 == 6'd19) & ~(trunc_ln203_11_fu_79618_p1 == 6'd20) & ~(trunc_ln203_11_fu_79618_p1 == 6'd21) & ~(trunc_ln203_11_fu_79618_p1 == 6'd22) & ~(trunc_ln203_11_fu_79618_p1 == 6'd23) & ~(trunc_ln203_11_fu_79618_p1 == 6'd24) & ~(trunc_ln203_11_fu_79618_p1 == 6'd25) & ~(trunc_ln203_11_fu_79618_p1 == 6'd26) & (ap_ST_fsm_state949 == ap_CS_fsm)) | (~(trunc_ln203_12_fu_79341_p1 == 6'd0) & ~(trunc_ln203_12_fu_79341_p1 == 6'd1) & ~(trunc_ln203_12_fu_79341_p1 == 6'd2) & ~(trunc_ln203_12_fu_79341_p1 == 6'd3) & ~(trunc_ln203_12_fu_79341_p1 == 6'd4) & ~(trunc_ln203_12_fu_79341_p1 == 6'd5) & ~(trunc_ln203_12_fu_79341_p1 == 6'd6) & ~(trunc_ln203_12_fu_79341_p1 == 6'd7) & ~(trunc_ln203_12_fu_79341_p1 == 6'd8) & ~(trunc_ln203_12_fu_79341_p1 == 6'd9) & ~(trunc_ln203_12_fu_79341_p1 == 6'd10) & ~(trunc_ln203_12_fu_79341_p1 == 6'd11) & ~(trunc_ln203_12_fu_79341_p1 == 6'd12) & ~(trunc_ln203_12_fu_79341_p1 == 6'd13) & ~(trunc_ln203_12_fu_79341_p1 == 6'd14) & ~(trunc_ln203_12_fu_79341_p1 == 6'd15) & ~(trunc_ln203_12_fu_79341_p1 == 6'd16) & ~(trunc_ln203_12_fu_79341_p1 == 6'd17) & ~(trunc_ln203_12_fu_79341_p1 == 6'd18) & ~(trunc_ln203_12_fu_79341_p1 == 6'd19) & ~(trunc_ln203_12_fu_79341_p1 == 6'd20) & ~(trunc_ln203_12_fu_79341_p1 == 6'd21) & ~(trunc_ln203_12_fu_79341_p1 == 6'd22) & ~(trunc_ln203_12_fu_79341_p1 == 6'd23) & ~(trunc_ln203_12_fu_79341_p1 == 6'd24) & ~(trunc_ln203_12_fu_79341_p1 == 6'd25) & ~(trunc_ln203_12_fu_79341_p1 == 6'd26) & (ap_ST_fsm_state913 == ap_CS_fsm)) | (~(trunc_ln203_31_fu_78901_p1 == 6'd0) & ~(trunc_ln203_31_fu_78901_p1 == 6'd1) & ~(trunc_ln203_31_fu_78901_p1 == 6'd2) & ~(trunc_ln203_31_fu_78901_p1 == 6'd3) & ~(trunc_ln203_31_fu_78901_p1 == 6'd4) & ~(trunc_ln203_31_fu_78901_p1 == 6'd5) & ~(trunc_ln203_31_fu_78901_p1 == 6'd6) & ~(trunc_ln203_31_fu_78901_p1 == 6'd7) & ~(trunc_ln203_31_fu_78901_p1 == 6'd8) & ~(trunc_ln203_31_fu_78901_p1 == 6'd9) & ~(trunc_ln203_31_fu_78901_p1 == 6'd10) & ~(trunc_ln203_31_fu_78901_p1 == 6'd11) & ~(trunc_ln203_31_fu_78901_p1 == 6'd12) & ~(trunc_ln203_31_fu_78901_p1 == 6'd13) & ~(trunc_ln203_31_fu_78901_p1 == 6'd14) & ~(trunc_ln203_31_fu_78901_p1 == 6'd15) & ~(trunc_ln203_31_fu_78901_p1 == 6'd16) & ~(trunc_ln203_31_fu_78901_p1 == 6'd17) & ~(trunc_ln203_31_fu_78901_p1 == 6'd18) & ~(trunc_ln203_31_fu_78901_p1 == 6'd19) & ~(trunc_ln203_31_fu_78901_p1 == 6'd20) & ~(trunc_ln203_31_fu_78901_p1 == 6'd21) & ~(trunc_ln203_31_fu_78901_p1 == 6'd22) & ~(trunc_ln203_31_fu_78901_p1 == 6'd23) & ~(trunc_ln203_31_fu_78901_p1 == 6'd24) & ~(trunc_ln203_31_fu_78901_p1 == 6'd25) & ~(trunc_ln203_31_fu_78901_p1 == 6'd26) & (ap_ST_fsm_state874 == ap_CS_fsm)) | (~(trunc_ln203_32_fu_78841_p1 == 6'd0) & ~(trunc_ln203_32_fu_78841_p1 == 6'd1) & ~(trunc_ln203_32_fu_78841_p1 == 6'd2) & ~(trunc_ln203_32_fu_78841_p1 == 6'd3) & ~(trunc_ln203_32_fu_78841_p1 == 6'd4) & ~(trunc_ln203_32_fu_78841_p1 == 6'd5) & ~(trunc_ln203_32_fu_78841_p1 == 6'd6) & ~(trunc_ln203_32_fu_78841_p1 == 6'd7) & ~(trunc_ln203_32_fu_78841_p1 == 6'd8) & ~(trunc_ln203_32_fu_78841_p1 == 6'd9) & ~(trunc_ln203_32_fu_78841_p1 == 6'd10) & ~(trunc_ln203_32_fu_78841_p1 == 6'd11) & ~(trunc_ln203_32_fu_78841_p1 == 6'd12) & ~(trunc_ln203_32_fu_78841_p1 == 6'd13) & ~(trunc_ln203_32_fu_78841_p1 == 6'd14) & ~(trunc_ln203_32_fu_78841_p1 == 6'd15) & ~(trunc_ln203_32_fu_78841_p1 == 6'd16) & ~(trunc_ln203_32_fu_78841_p1 == 6'd17) & ~(trunc_ln203_32_fu_78841_p1 == 6'd18) & ~(trunc_ln203_32_fu_78841_p1 == 6'd19) & ~(trunc_ln203_32_fu_78841_p1 == 6'd20) & ~(trunc_ln203_32_fu_78841_p1 == 6'd21) & ~(trunc_ln203_32_fu_78841_p1 == 6'd22) & ~(trunc_ln203_32_fu_78841_p1 == 6'd23) & ~(trunc_ln203_32_fu_78841_p1 == 6'd24) & ~(trunc_ln203_32_fu_78841_p1 == 6'd25) & ~(trunc_ln203_32_fu_78841_p1 == 6'd26) & (ap_ST_fsm_state838 == ap_CS_fsm)) | (~(trunc_ln203_23_fu_78650_p1 == 6'd0) & ~(trunc_ln203_23_fu_78650_p1 == 6'd1) & ~(trunc_ln203_23_fu_78650_p1 == 6'd2) & ~(trunc_ln203_23_fu_78650_p1 == 6'd3) & ~(trunc_ln203_23_fu_78650_p1 == 6'd4) & ~(trunc_ln203_23_fu_78650_p1 == 6'd5) & ~(trunc_ln203_23_fu_78650_p1 == 6'd6) & ~(trunc_ln203_23_fu_78650_p1 == 6'd7) & ~(trunc_ln203_23_fu_78650_p1 == 6'd8) & ~(trunc_ln203_23_fu_78650_p1 == 6'd9) & ~(trunc_ln203_23_fu_78650_p1 == 6'd10) & ~(trunc_ln203_23_fu_78650_p1 == 6'd11) & ~(trunc_ln203_23_fu_78650_p1 == 6'd12) & ~(trunc_ln203_23_fu_78650_p1 == 6'd13) & ~(trunc_ln203_23_fu_78650_p1 == 6'd14) & ~(trunc_ln203_23_fu_78650_p1 == 6'd15) & ~(trunc_ln203_23_fu_78650_p1 == 6'd16) & ~(trunc_ln203_23_fu_78650_p1 == 6'd17) & ~(trunc_ln203_23_fu_78650_p1 == 6'd18) & ~(trunc_ln203_23_fu_78650_p1 == 6'd19) & ~(trunc_ln203_23_fu_78650_p1 == 6'd20) & ~(trunc_ln203_23_fu_78650_p1 == 6'd21) & ~(trunc_ln203_23_fu_78650_p1 == 6'd22) & ~(trunc_ln203_23_fu_78650_p1 == 6'd23) & ~(trunc_ln203_23_fu_78650_p1 == 6'd24) & ~(trunc_ln203_23_fu_78650_p1 == 6'd25) & ~(trunc_ln203_23_fu_78650_p1 == 6'd26) & (ap_ST_fsm_state803 == ap_CS_fsm)) | (~(trunc_ln203_24_fu_78472_p1 == 6'd0) & ~(trunc_ln203_24_fu_78472_p1 == 6'd1) & ~(trunc_ln203_24_fu_78472_p1 == 6'd2) & ~(trunc_ln203_24_fu_78472_p1 == 6'd3) & ~(trunc_ln203_24_fu_78472_p1 == 6'd4) & ~(trunc_ln203_24_fu_78472_p1 == 6'd5) & ~(trunc_ln203_24_fu_78472_p1 == 6'd6) & ~(trunc_ln203_24_fu_78472_p1 == 6'd7) & ~(trunc_ln203_24_fu_78472_p1 == 6'd8) & ~(trunc_ln203_24_fu_78472_p1 == 6'd9) & ~(trunc_ln203_24_fu_78472_p1 == 6'd10) & ~(trunc_ln203_24_fu_78472_p1 == 6'd11) & ~(trunc_ln203_24_fu_78472_p1 == 6'd12) & ~(trunc_ln203_24_fu_78472_p1 == 6'd13) & ~(trunc_ln203_24_fu_78472_p1 == 6'd14) & ~(trunc_ln203_24_fu_78472_p1 == 6'd15) & ~(trunc_ln203_24_fu_78472_p1 == 6'd16) & ~(trunc_ln203_24_fu_78472_p1 == 6'd17) & ~(trunc_ln203_24_fu_78472_p1 == 6'd18) & ~(trunc_ln203_24_fu_78472_p1 == 6'd19) & ~(trunc_ln203_24_fu_78472_p1 == 6'd20) & ~(trunc_ln203_24_fu_78472_p1 == 6'd21) & ~(trunc_ln203_24_fu_78472_p1 == 6'd22) & ~(trunc_ln203_24_fu_78472_p1 == 6'd23) & ~(trunc_ln203_24_fu_78472_p1 == 6'd24) & ~(trunc_ln203_24_fu_78472_p1 == 6'd25) & ~(trunc_ln203_24_fu_78472_p1 == 6'd26) & (ap_ST_fsm_state767 == ap_CS_fsm)) | (~(trunc_ln203_15_fu_78178_p1 == 6'd0) & ~(trunc_ln203_15_fu_78178_p1 == 6'd1) & ~(trunc_ln203_15_fu_78178_p1 == 6'd2) & ~(trunc_ln203_15_fu_78178_p1 == 6'd3) & ~(trunc_ln203_15_fu_78178_p1 == 6'd4) & ~(trunc_ln203_15_fu_78178_p1 == 6'd5) & ~(trunc_ln203_15_fu_78178_p1 == 6'd6) & ~(trunc_ln203_15_fu_78178_p1 == 6'd7) & ~(trunc_ln203_15_fu_78178_p1 == 6'd8) & ~(trunc_ln203_15_fu_78178_p1 == 6'd9) & ~(trunc_ln203_15_fu_78178_p1 == 6'd10) & ~(trunc_ln203_15_fu_78178_p1 == 6'd11) & ~(trunc_ln203_15_fu_78178_p1 == 6'd12) & ~(trunc_ln203_15_fu_78178_p1 == 6'd13) & ~(trunc_ln203_15_fu_78178_p1 == 6'd14) & ~(trunc_ln203_15_fu_78178_p1 == 6'd15) & ~(trunc_ln203_15_fu_78178_p1 == 6'd16) & ~(trunc_ln203_15_fu_78178_p1 == 6'd17) & ~(trunc_ln203_15_fu_78178_p1 == 6'd18) & ~(trunc_ln203_15_fu_78178_p1 == 6'd19) & ~(trunc_ln203_15_fu_78178_p1 == 6'd20) & ~(trunc_ln203_15_fu_78178_p1 == 6'd21) & ~(trunc_ln203_15_fu_78178_p1 == 6'd22) & ~(trunc_ln203_15_fu_78178_p1 == 6'd23) & ~(trunc_ln203_15_fu_78178_p1 == 6'd24) & ~(trunc_ln203_15_fu_78178_p1 == 6'd25) & ~(trunc_ln203_15_fu_78178_p1 == 6'd26) & (ap_ST_fsm_state730 == ap_CS_fsm)) | (~(trunc_ln203_16_fu_78118_p1 == 6'd0) & ~(trunc_ln203_16_fu_78118_p1 == 6'd1) & ~(trunc_ln203_16_fu_78118_p1 == 6'd2) & ~(trunc_ln203_16_fu_78118_p1 == 6'd3) & ~(trunc_ln203_16_fu_78118_p1 == 6'd4) & ~(trunc_ln203_16_fu_78118_p1 == 6'd5) & ~(trunc_ln203_16_fu_78118_p1 == 6'd6) & ~(trunc_ln203_16_fu_78118_p1 == 6'd7) & ~(trunc_ln203_16_fu_78118_p1 == 6'd8) & ~(trunc_ln203_16_fu_78118_p1 == 6'd9) & ~(trunc_ln203_16_fu_78118_p1 == 6'd10) & ~(trunc_ln203_16_fu_78118_p1 == 6'd11) & ~(trunc_ln203_16_fu_78118_p1 == 6'd12) & ~(trunc_ln203_16_fu_78118_p1 == 6'd13) & ~(trunc_ln203_16_fu_78118_p1 == 6'd14) & ~(trunc_ln203_16_fu_78118_p1 == 6'd15) & ~(trunc_ln203_16_fu_78118_p1 == 6'd16) & ~(trunc_ln203_16_fu_78118_p1 == 6'd17) & ~(trunc_ln203_16_fu_78118_p1 == 6'd18) & ~(trunc_ln203_16_fu_78118_p1 == 6'd19) & ~(trunc_ln203_16_fu_78118_p1 == 6'd20) & ~(trunc_ln203_16_fu_78118_p1 == 6'd21) & ~(trunc_ln203_16_fu_78118_p1 == 6'd22) & ~(trunc_ln203_16_fu_78118_p1 == 6'd23) & ~(trunc_ln203_16_fu_78118_p1 == 6'd24) & ~(trunc_ln203_16_fu_78118_p1 == 6'd25) & ~(trunc_ln203_16_fu_78118_p1 == 6'd26) & (ap_ST_fsm_state694 == ap_CS_fsm)) | (~(trunc_ln203_7_fu_77906_p1 == 6'd0) & ~(trunc_ln203_7_fu_77906_p1 == 6'd1) & ~(trunc_ln203_7_fu_77906_p1 == 6'd2) & ~(trunc_ln203_7_fu_77906_p1 == 6'd3) & ~(trunc_ln203_7_fu_77906_p1 == 6'd4) & ~(trunc_ln203_7_fu_77906_p1 == 6'd5) & ~(trunc_ln203_7_fu_77906_p1 == 6'd6) & ~(trunc_ln203_7_fu_77906_p1 == 6'd7) & ~(trunc_ln203_7_fu_77906_p1 == 6'd8) & ~(trunc_ln203_7_fu_77906_p1 == 6'd9) & ~(trunc_ln203_7_fu_77906_p1 == 6'd10) & ~(trunc_ln203_7_fu_77906_p1 == 6'd11) & ~(trunc_ln203_7_fu_77906_p1 == 6'd12) & ~(trunc_ln203_7_fu_77906_p1 == 6'd13) & ~(trunc_ln203_7_fu_77906_p1 == 6'd14) & ~(trunc_ln203_7_fu_77906_p1 == 6'd15) & ~(trunc_ln203_7_fu_77906_p1 == 6'd16) & ~(trunc_ln203_7_fu_77906_p1 == 6'd17) & ~(trunc_ln203_7_fu_77906_p1 == 6'd18) & ~(trunc_ln203_7_fu_77906_p1 == 6'd19) & ~(trunc_ln203_7_fu_77906_p1 == 6'd20) & ~(trunc_ln203_7_fu_77906_p1 == 6'd21) & ~(trunc_ln203_7_fu_77906_p1 == 6'd22) & ~(trunc_ln203_7_fu_77906_p1 == 6'd23) & ~(trunc_ln203_7_fu_77906_p1 == 6'd24) & ~(trunc_ln203_7_fu_77906_p1 == 6'd25) & ~(trunc_ln203_7_fu_77906_p1 == 6'd26) & (ap_ST_fsm_state659 == ap_CS_fsm)) | (~(trunc_ln203_8_fu_77649_p1 == 6'd0) & ~(trunc_ln203_8_fu_77649_p1 == 6'd1) & ~(trunc_ln203_8_fu_77649_p1 == 6'd2) & ~(trunc_ln203_8_fu_77649_p1 == 6'd3) & ~(trunc_ln203_8_fu_77649_p1 == 6'd4) & ~(trunc_ln203_8_fu_77649_p1 == 6'd5) & ~(trunc_ln203_8_fu_77649_p1 == 6'd6) & ~(trunc_ln203_8_fu_77649_p1 == 6'd7) & ~(trunc_ln203_8_fu_77649_p1 == 6'd8) & ~(trunc_ln203_8_fu_77649_p1 == 6'd9) & ~(trunc_ln203_8_fu_77649_p1 == 6'd10) & ~(trunc_ln203_8_fu_77649_p1 == 6'd11) & ~(trunc_ln203_8_fu_77649_p1 == 6'd12) & ~(trunc_ln203_8_fu_77649_p1 == 6'd13) & ~(trunc_ln203_8_fu_77649_p1 == 6'd14) & ~(trunc_ln203_8_fu_77649_p1 == 6'd15) & ~(trunc_ln203_8_fu_77649_p1 == 6'd16) & ~(trunc_ln203_8_fu_77649_p1 == 6'd17) & ~(trunc_ln203_8_fu_77649_p1 == 6'd18) & ~(trunc_ln203_8_fu_77649_p1 == 6'd19) & ~(trunc_ln203_8_fu_77649_p1 == 6'd20) & ~(trunc_ln203_8_fu_77649_p1 == 6'd21) & ~(trunc_ln203_8_fu_77649_p1 == 6'd22) & ~(trunc_ln203_8_fu_77649_p1 == 6'd23) & ~(trunc_ln203_8_fu_77649_p1 == 6'd24) & ~(trunc_ln203_8_fu_77649_p1 == 6'd25) & ~(trunc_ln203_8_fu_77649_p1 == 6'd26) & (ap_ST_fsm_state623 == ap_CS_fsm)) | (~(trunc_ln203_33_fu_77121_p1 == 6'd0) & ~(trunc_ln203_33_fu_77121_p1 == 6'd1) & ~(trunc_ln203_33_fu_77121_p1 == 6'd2) & ~(trunc_ln203_33_fu_77121_p1 == 6'd3) & ~(trunc_ln203_33_fu_77121_p1 == 6'd4) & ~(trunc_ln203_33_fu_77121_p1 == 6'd5) & ~(trunc_ln203_33_fu_77121_p1 == 6'd6) & ~(trunc_ln203_33_fu_77121_p1 == 6'd7) & ~(trunc_ln203_33_fu_77121_p1 == 6'd8) & ~(trunc_ln203_33_fu_77121_p1 == 6'd9) & ~(trunc_ln203_33_fu_77121_p1 == 6'd10) & ~(trunc_ln203_33_fu_77121_p1 == 6'd11) & ~(trunc_ln203_33_fu_77121_p1 == 6'd12) & ~(trunc_ln203_33_fu_77121_p1 == 6'd13) & ~(trunc_ln203_33_fu_77121_p1 == 6'd14) & ~(trunc_ln203_33_fu_77121_p1 == 6'd15) & ~(trunc_ln203_33_fu_77121_p1 == 6'd16) & ~(trunc_ln203_33_fu_77121_p1 == 6'd17) & ~(trunc_ln203_33_fu_77121_p1 == 6'd18) & ~(trunc_ln203_33_fu_77121_p1 == 6'd19) & ~(trunc_ln203_33_fu_77121_p1 == 6'd20) & ~(trunc_ln203_33_fu_77121_p1 == 6'd21) & ~(trunc_ln203_33_fu_77121_p1 == 6'd22) & ~(trunc_ln203_33_fu_77121_p1 == 6'd23) & ~(trunc_ln203_33_fu_77121_p1 == 6'd24) & ~(trunc_ln203_33_fu_77121_p1 == 6'd25) & ~(trunc_ln203_33_fu_77121_p1 == 6'd26) & (ap_ST_fsm_state583 == ap_CS_fsm)) | (~(trunc_ln203_34_fu_77061_p1 == 6'd0) & ~(trunc_ln203_34_fu_77061_p1 == 6'd1) & ~(trunc_ln203_34_fu_77061_p1 == 6'd2) & ~(trunc_ln203_34_fu_77061_p1 == 6'd3) & ~(trunc_ln203_34_fu_77061_p1 == 6'd4) & ~(trunc_ln203_34_fu_77061_p1 == 6'd5) & ~(trunc_ln203_34_fu_77061_p1 == 6'd6) & ~(trunc_ln203_34_fu_77061_p1 == 6'd7) & ~(trunc_ln203_34_fu_77061_p1 == 6'd8) & ~(trunc_ln203_34_fu_77061_p1 == 6'd9) & ~(trunc_ln203_34_fu_77061_p1 == 6'd10) & ~(trunc_ln203_34_fu_77061_p1 == 6'd11) & ~(trunc_ln203_34_fu_77061_p1 == 6'd12) & ~(trunc_ln203_34_fu_77061_p1 == 6'd13) & ~(trunc_ln203_34_fu_77061_p1 == 6'd14) & ~(trunc_ln203_34_fu_77061_p1 == 6'd15) & ~(trunc_ln203_34_fu_77061_p1 == 6'd16) & ~(trunc_ln203_34_fu_77061_p1 == 6'd17) & ~(trunc_ln203_34_fu_77061_p1 == 6'd18) & ~(trunc_ln203_34_fu_77061_p1 == 6'd19) & ~(trunc_ln203_34_fu_77061_p1 == 6'd20) & ~(trunc_ln203_34_fu_77061_p1 == 6'd21) & ~(trunc_ln203_34_fu_77061_p1 == 6'd22) & ~(trunc_ln203_34_fu_77061_p1 == 6'd23) & ~(trunc_ln203_34_fu_77061_p1 == 6'd24) & ~(trunc_ln203_34_fu_77061_p1 == 6'd25) & ~(trunc_ln203_34_fu_77061_p1 == 6'd26) & (ap_ST_fsm_state547 == ap_CS_fsm)) | (~(trunc_ln203_25_fu_76870_p1 == 6'd0) & ~(trunc_ln203_25_fu_76870_p1 == 6'd1) & ~(trunc_ln203_25_fu_76870_p1 == 6'd2) & ~(trunc_ln203_25_fu_76870_p1 == 6'd3) & ~(trunc_ln203_25_fu_76870_p1 == 6'd4) & ~(trunc_ln203_25_fu_76870_p1 == 6'd5) & ~(trunc_ln203_25_fu_76870_p1 == 6'd6) & ~(trunc_ln203_25_fu_76870_p1 == 6'd7) & ~(trunc_ln203_25_fu_76870_p1 == 6'd8) & ~(trunc_ln203_25_fu_76870_p1 == 6'd9) & ~(trunc_ln203_25_fu_76870_p1 == 6'd10) & ~(trunc_ln203_25_fu_76870_p1 == 6'd11) & ~(trunc_ln203_25_fu_76870_p1 == 6'd12) & ~(trunc_ln203_25_fu_76870_p1 == 6'd13) & ~(trunc_ln203_25_fu_76870_p1 == 6'd14) & ~(trunc_ln203_25_fu_76870_p1 == 6'd15) & ~(trunc_ln203_25_fu_76870_p1 == 6'd16) & ~(trunc_ln203_25_fu_76870_p1 == 6'd17) & ~(trunc_ln203_25_fu_76870_p1 == 6'd18) & ~(trunc_ln203_25_fu_76870_p1 == 6'd19) & ~(trunc_ln203_25_fu_76870_p1 == 6'd20) & ~(trunc_ln203_25_fu_76870_p1 == 6'd21) & ~(trunc_ln203_25_fu_76870_p1 == 6'd22) & ~(trunc_ln203_25_fu_76870_p1 == 6'd23) & ~(trunc_ln203_25_fu_76870_p1 == 6'd24) & ~(trunc_ln203_25_fu_76870_p1 == 6'd25) & ~(trunc_ln203_25_fu_76870_p1 == 6'd26) & (ap_ST_fsm_state512 == ap_CS_fsm)) | (~(trunc_ln203_26_fu_76692_p1 == 6'd0) & ~(trunc_ln203_26_fu_76692_p1 == 6'd1) & ~(trunc_ln203_26_fu_76692_p1 == 6'd2) & ~(trunc_ln203_26_fu_76692_p1 == 6'd3) & ~(trunc_ln203_26_fu_76692_p1 == 6'd4) & ~(trunc_ln203_26_fu_76692_p1 == 6'd5) & ~(trunc_ln203_26_fu_76692_p1 == 6'd6) & ~(trunc_ln203_26_fu_76692_p1 == 6'd7) & ~(trunc_ln203_26_fu_76692_p1 == 6'd8) & ~(trunc_ln203_26_fu_76692_p1 == 6'd9) & ~(trunc_ln203_26_fu_76692_p1 == 6'd10) & ~(trunc_ln203_26_fu_76692_p1 == 6'd11) & ~(trunc_ln203_26_fu_76692_p1 == 6'd12) & ~(trunc_ln203_26_fu_76692_p1 == 6'd13) & ~(trunc_ln203_26_fu_76692_p1 == 6'd14) & ~(trunc_ln203_26_fu_76692_p1 == 6'd15) & ~(trunc_ln203_26_fu_76692_p1 == 6'd16) & ~(trunc_ln203_26_fu_76692_p1 == 6'd17) & ~(trunc_ln203_26_fu_76692_p1 == 6'd18) & ~(trunc_ln203_26_fu_76692_p1 == 6'd19) & ~(trunc_ln203_26_fu_76692_p1 == 6'd20) & ~(trunc_ln203_26_fu_76692_p1 == 6'd21) & ~(trunc_ln203_26_fu_76692_p1 == 6'd22) & ~(trunc_ln203_26_fu_76692_p1 == 6'd23) & ~(trunc_ln203_26_fu_76692_p1 == 6'd24) & ~(trunc_ln203_26_fu_76692_p1 == 6'd25) & ~(trunc_ln203_26_fu_76692_p1 == 6'd26) & (ap_ST_fsm_state476 == ap_CS_fsm)) | (~(trunc_ln203_17_fu_76408_p1 == 6'd0) & ~(trunc_ln203_17_fu_76408_p1 == 6'd1) & ~(trunc_ln203_17_fu_76408_p1 == 6'd2) & ~(trunc_ln203_17_fu_76408_p1 == 6'd3) & ~(trunc_ln203_17_fu_76408_p1 == 6'd4) & ~(trunc_ln203_17_fu_76408_p1 == 6'd5) & ~(trunc_ln203_17_fu_76408_p1 == 6'd6) & ~(trunc_ln203_17_fu_76408_p1 == 6'd7) & ~(trunc_ln203_17_fu_76408_p1 == 6'd8) & ~(trunc_ln203_17_fu_76408_p1 == 6'd9) & ~(trunc_ln203_17_fu_76408_p1 == 6'd10) & ~(trunc_ln203_17_fu_76408_p1 == 6'd11) & ~(trunc_ln203_17_fu_76408_p1 == 6'd12) & ~(trunc_ln203_17_fu_76408_p1 == 6'd13) & ~(trunc_ln203_17_fu_76408_p1 == 6'd14) & ~(trunc_ln203_17_fu_76408_p1 == 6'd15) & ~(trunc_ln203_17_fu_76408_p1 == 6'd16) & ~(trunc_ln203_17_fu_76408_p1 == 6'd17) & ~(trunc_ln203_17_fu_76408_p1 == 6'd18) & ~(trunc_ln203_17_fu_76408_p1 == 6'd19) & ~(trunc_ln203_17_fu_76408_p1 == 6'd20) & ~(trunc_ln203_17_fu_76408_p1 == 6'd21) & ~(trunc_ln203_17_fu_76408_p1 == 6'd22) & ~(trunc_ln203_17_fu_76408_p1 == 6'd23) & ~(trunc_ln203_17_fu_76408_p1 == 6'd24) & ~(trunc_ln203_17_fu_76408_p1 == 6'd25) & ~(trunc_ln203_17_fu_76408_p1 == 6'd26) & (ap_ST_fsm_state439 == ap_CS_fsm)) | (~(trunc_ln203_18_fu_76348_p1 == 6'd0) & ~(trunc_ln203_18_fu_76348_p1 == 6'd1) & ~(trunc_ln203_18_fu_76348_p1 == 6'd2) & ~(trunc_ln203_18_fu_76348_p1 == 6'd3) & ~(trunc_ln203_18_fu_76348_p1 == 6'd4) & ~(trunc_ln203_18_fu_76348_p1 == 6'd5) & ~(trunc_ln203_18_fu_76348_p1 == 6'd6) & ~(trunc_ln203_18_fu_76348_p1 == 6'd7) & ~(trunc_ln203_18_fu_76348_p1 == 6'd8) & ~(trunc_ln203_18_fu_76348_p1 == 6'd9) & ~(trunc_ln203_18_fu_76348_p1 == 6'd10) & ~(trunc_ln203_18_fu_76348_p1 == 6'd11) & ~(trunc_ln203_18_fu_76348_p1 == 6'd12) & ~(trunc_ln203_18_fu_76348_p1 == 6'd13) & ~(trunc_ln203_18_fu_76348_p1 == 6'd14) & ~(trunc_ln203_18_fu_76348_p1 == 6'd15) & ~(trunc_ln203_18_fu_76348_p1 == 6'd16) & ~(trunc_ln203_18_fu_76348_p1 == 6'd17) & ~(trunc_ln203_18_fu_76348_p1 == 6'd18) & ~(trunc_ln203_18_fu_76348_p1 == 6'd19) & ~(trunc_ln203_18_fu_76348_p1 == 6'd20) & ~(trunc_ln203_18_fu_76348_p1 == 6'd21) & ~(trunc_ln203_18_fu_76348_p1 == 6'd22) & ~(trunc_ln203_18_fu_76348_p1 == 6'd23) & ~(trunc_ln203_18_fu_76348_p1 == 6'd24) & ~(trunc_ln203_18_fu_76348_p1 == 6'd25) & ~(trunc_ln203_18_fu_76348_p1 == 6'd26) & (ap_ST_fsm_state403 == ap_CS_fsm)) | (~(trunc_ln203_9_fu_76135_p1 == 6'd0) & ~(trunc_ln203_9_fu_76135_p1 == 6'd1) & ~(trunc_ln203_9_fu_76135_p1 == 6'd2) & ~(trunc_ln203_9_fu_76135_p1 == 6'd3) & ~(trunc_ln203_9_fu_76135_p1 == 6'd4) & ~(trunc_ln203_9_fu_76135_p1 == 6'd5) & ~(trunc_ln203_9_fu_76135_p1 == 6'd6) & ~(trunc_ln203_9_fu_76135_p1 == 6'd7) & ~(trunc_ln203_9_fu_76135_p1 == 6'd8) & ~(trunc_ln203_9_fu_76135_p1 == 6'd9) & ~(trunc_ln203_9_fu_76135_p1 == 6'd10) & ~(trunc_ln203_9_fu_76135_p1 == 6'd11) & ~(trunc_ln203_9_fu_76135_p1 == 6'd12) & ~(trunc_ln203_9_fu_76135_p1 == 6'd13) & ~(trunc_ln203_9_fu_76135_p1 == 6'd14) & ~(trunc_ln203_9_fu_76135_p1 == 6'd15) & ~(trunc_ln203_9_fu_76135_p1 == 6'd16) & ~(trunc_ln203_9_fu_76135_p1 == 6'd17) & ~(trunc_ln203_9_fu_76135_p1 == 6'd18) & ~(trunc_ln203_9_fu_76135_p1 == 6'd19) & ~(trunc_ln203_9_fu_76135_p1 == 6'd20) & ~(trunc_ln203_9_fu_76135_p1 == 6'd21) & ~(trunc_ln203_9_fu_76135_p1 == 6'd22) & ~(trunc_ln203_9_fu_76135_p1 == 6'd23) & ~(trunc_ln203_9_fu_76135_p1 == 6'd24) & ~(trunc_ln203_9_fu_76135_p1 == 6'd25) & ~(trunc_ln203_9_fu_76135_p1 == 6'd26) & (ap_ST_fsm_state368 == ap_CS_fsm)) | (~(trunc_ln203_10_fu_75878_p1 == 6'd0) & ~(trunc_ln203_10_fu_75878_p1 == 6'd1) & ~(trunc_ln203_10_fu_75878_p1 == 6'd2) & ~(trunc_ln203_10_fu_75878_p1 == 6'd3) & ~(trunc_ln203_10_fu_75878_p1 == 6'd4) & ~(trunc_ln203_10_fu_75878_p1 == 6'd5) & ~(trunc_ln203_10_fu_75878_p1 == 6'd6) & ~(trunc_ln203_10_fu_75878_p1 == 6'd7) & ~(trunc_ln203_10_fu_75878_p1 == 6'd8) & ~(trunc_ln203_10_fu_75878_p1 == 6'd9) & ~(trunc_ln203_10_fu_75878_p1 == 6'd10) & ~(trunc_ln203_10_fu_75878_p1 == 6'd11) & ~(trunc_ln203_10_fu_75878_p1 == 6'd12) & ~(trunc_ln203_10_fu_75878_p1 == 6'd13) & ~(trunc_ln203_10_fu_75878_p1 == 6'd14) & ~(trunc_ln203_10_fu_75878_p1 == 6'd15) & ~(trunc_ln203_10_fu_75878_p1 == 6'd16) & ~(trunc_ln203_10_fu_75878_p1 == 6'd17) & ~(trunc_ln203_10_fu_75878_p1 == 6'd18) & ~(trunc_ln203_10_fu_75878_p1 == 6'd19) & ~(trunc_ln203_10_fu_75878_p1 == 6'd20) & ~(trunc_ln203_10_fu_75878_p1 == 6'd21) & ~(trunc_ln203_10_fu_75878_p1 == 6'd22) & ~(trunc_ln203_10_fu_75878_p1 == 6'd23) & ~(trunc_ln203_10_fu_75878_p1 == 6'd24) & ~(trunc_ln203_10_fu_75878_p1 == 6'd25) & ~(trunc_ln203_10_fu_75878_p1 == 6'd26) & (ap_ST_fsm_state332 == ap_CS_fsm)) | (~(trunc_ln203_29_fu_75441_p1 == 6'd0) & ~(trunc_ln203_29_fu_75441_p1 == 6'd1) & ~(trunc_ln203_29_fu_75441_p1 == 6'd2) & ~(trunc_ln203_29_fu_75441_p1 == 6'd3) & ~(trunc_ln203_29_fu_75441_p1 == 6'd4) & ~(trunc_ln203_29_fu_75441_p1 == 6'd5) & ~(trunc_ln203_29_fu_75441_p1 == 6'd6) & ~(trunc_ln203_29_fu_75441_p1 == 6'd7) & ~(trunc_ln203_29_fu_75441_p1 == 6'd8) & ~(trunc_ln203_29_fu_75441_p1 == 6'd9) & ~(trunc_ln203_29_fu_75441_p1 == 6'd10) & ~(trunc_ln203_29_fu_75441_p1 == 6'd11) & ~(trunc_ln203_29_fu_75441_p1 == 6'd12) & ~(trunc_ln203_29_fu_75441_p1 == 6'd13) & ~(trunc_ln203_29_fu_75441_p1 == 6'd14) & ~(trunc_ln203_29_fu_75441_p1 == 6'd15) & ~(trunc_ln203_29_fu_75441_p1 == 6'd16) & ~(trunc_ln203_29_fu_75441_p1 == 6'd17) & ~(trunc_ln203_29_fu_75441_p1 == 6'd18) & ~(trunc_ln203_29_fu_75441_p1 == 6'd19) & ~(trunc_ln203_29_fu_75441_p1 == 6'd20) & ~(trunc_ln203_29_fu_75441_p1 == 6'd21) & ~(trunc_ln203_29_fu_75441_p1 == 6'd22) & ~(trunc_ln203_29_fu_75441_p1 == 6'd23) & ~(trunc_ln203_29_fu_75441_p1 == 6'd24) & ~(trunc_ln203_29_fu_75441_p1 == 6'd25) & ~(trunc_ln203_29_fu_75441_p1 == 6'd26) & (ap_ST_fsm_state293 == ap_CS_fsm)) | (~(trunc_ln203_30_fu_75381_p1 == 6'd0) & ~(trunc_ln203_30_fu_75381_p1 == 6'd1) & ~(trunc_ln203_30_fu_75381_p1 == 6'd2) & ~(trunc_ln203_30_fu_75381_p1 == 6'd3) & ~(trunc_ln203_30_fu_75381_p1 == 6'd4) & ~(trunc_ln203_30_fu_75381_p1 == 6'd5) & ~(trunc_ln203_30_fu_75381_p1 == 6'd6) & ~(trunc_ln203_30_fu_75381_p1 == 6'd7) & ~(trunc_ln203_30_fu_75381_p1 == 6'd8) & ~(trunc_ln203_30_fu_75381_p1 == 6'd9) & ~(trunc_ln203_30_fu_75381_p1 == 6'd10) & ~(trunc_ln203_30_fu_75381_p1 == 6'd11) & ~(trunc_ln203_30_fu_75381_p1 == 6'd12) & ~(trunc_ln203_30_fu_75381_p1 == 6'd13) & ~(trunc_ln203_30_fu_75381_p1 == 6'd14) & ~(trunc_ln203_30_fu_75381_p1 == 6'd15) & ~(trunc_ln203_30_fu_75381_p1 == 6'd16) & ~(trunc_ln203_30_fu_75381_p1 == 6'd17) & ~(trunc_ln203_30_fu_75381_p1 == 6'd18) & ~(trunc_ln203_30_fu_75381_p1 == 6'd19) & ~(trunc_ln203_30_fu_75381_p1 == 6'd20) & ~(trunc_ln203_30_fu_75381_p1 == 6'd21) & ~(trunc_ln203_30_fu_75381_p1 == 6'd22) & ~(trunc_ln203_30_fu_75381_p1 == 6'd23) & ~(trunc_ln203_30_fu_75381_p1 == 6'd24) & ~(trunc_ln203_30_fu_75381_p1 == 6'd25) & ~(trunc_ln203_30_fu_75381_p1 == 6'd26) & (ap_ST_fsm_state257 == ap_CS_fsm)) | (~(trunc_ln203_19_fu_75190_p1 == 6'd0) & ~(trunc_ln203_19_fu_75190_p1 == 6'd1) & ~(trunc_ln203_19_fu_75190_p1 == 6'd2) & ~(trunc_ln203_19_fu_75190_p1 == 6'd3) & ~(trunc_ln203_19_fu_75190_p1 == 6'd4) & ~(trunc_ln203_19_fu_75190_p1 == 6'd5) & ~(trunc_ln203_19_fu_75190_p1 == 6'd6) & ~(trunc_ln203_19_fu_75190_p1 == 6'd7) & ~(trunc_ln203_19_fu_75190_p1 == 6'd8) & ~(trunc_ln203_19_fu_75190_p1 == 6'd9) & ~(trunc_ln203_19_fu_75190_p1 == 6'd10) & ~(trunc_ln203_19_fu_75190_p1 == 6'd11) & ~(trunc_ln203_19_fu_75190_p1 == 6'd12) & ~(trunc_ln203_19_fu_75190_p1 == 6'd13) & ~(trunc_ln203_19_fu_75190_p1 == 6'd14) & ~(trunc_ln203_19_fu_75190_p1 == 6'd15) & ~(trunc_ln203_19_fu_75190_p1 == 6'd16) & ~(trunc_ln203_19_fu_75190_p1 == 6'd17) & ~(trunc_ln203_19_fu_75190_p1 == 6'd18) & ~(trunc_ln203_19_fu_75190_p1 == 6'd19) & ~(trunc_ln203_19_fu_75190_p1 == 6'd20) & ~(trunc_ln203_19_fu_75190_p1 == 6'd21) & ~(trunc_ln203_19_fu_75190_p1 == 6'd22) & ~(trunc_ln203_19_fu_75190_p1 == 6'd23) & ~(trunc_ln203_19_fu_75190_p1 == 6'd24) & ~(trunc_ln203_19_fu_75190_p1 == 6'd25) & ~(trunc_ln203_19_fu_75190_p1 == 6'd26) & (ap_ST_fsm_state222 == ap_CS_fsm)) | (~(trunc_ln203_20_fu_75012_p1 == 6'd0) & ~(trunc_ln203_20_fu_75012_p1 == 6'd1) & ~(trunc_ln203_20_fu_75012_p1 == 6'd2) & ~(trunc_ln203_20_fu_75012_p1 == 6'd3) & ~(trunc_ln203_20_fu_75012_p1 == 6'd4) & ~(trunc_ln203_20_fu_75012_p1 == 6'd5) & ~(trunc_ln203_20_fu_75012_p1 == 6'd6) & ~(trunc_ln203_20_fu_75012_p1 == 6'd7) & ~(trunc_ln203_20_fu_75012_p1 == 6'd8) & ~(trunc_ln203_20_fu_75012_p1 == 6'd9) & ~(trunc_ln203_20_fu_75012_p1 == 6'd10) & ~(trunc_ln203_20_fu_75012_p1 == 6'd11) & ~(trunc_ln203_20_fu_75012_p1 == 6'd12) & ~(trunc_ln203_20_fu_75012_p1 == 6'd13) & ~(trunc_ln203_20_fu_75012_p1 == 6'd14) & ~(trunc_ln203_20_fu_75012_p1 == 6'd15) & ~(trunc_ln203_20_fu_75012_p1 == 6'd16) & ~(trunc_ln203_20_fu_75012_p1 == 6'd17) & ~(trunc_ln203_20_fu_75012_p1 == 6'd18) & ~(trunc_ln203_20_fu_75012_p1 == 6'd19) & ~(trunc_ln203_20_fu_75012_p1 == 6'd20) & ~(trunc_ln203_20_fu_75012_p1 == 6'd21) & ~(trunc_ln203_20_fu_75012_p1 == 6'd22) & ~(trunc_ln203_20_fu_75012_p1 == 6'd23) & ~(trunc_ln203_20_fu_75012_p1 == 6'd24) & ~(trunc_ln203_20_fu_75012_p1 == 6'd25) & ~(trunc_ln203_20_fu_75012_p1 == 6'd26) & (ap_ST_fsm_state186 == ap_CS_fsm)) | (~(trunc_ln203_13_fu_74718_p1 == 6'd0) & ~(trunc_ln203_13_fu_74718_p1 == 6'd1) & ~(trunc_ln203_13_fu_74718_p1 == 6'd2) & ~(trunc_ln203_13_fu_74718_p1 == 6'd3) & ~(trunc_ln203_13_fu_74718_p1 == 6'd4) & ~(trunc_ln203_13_fu_74718_p1 == 6'd5) & ~(trunc_ln203_13_fu_74718_p1 == 6'd6) & ~(trunc_ln203_13_fu_74718_p1 == 6'd7) & ~(trunc_ln203_13_fu_74718_p1 == 6'd8) & ~(trunc_ln203_13_fu_74718_p1 == 6'd9) & ~(trunc_ln203_13_fu_74718_p1 == 6'd10) & ~(trunc_ln203_13_fu_74718_p1 == 6'd11) & ~(trunc_ln203_13_fu_74718_p1 == 6'd12) & ~(trunc_ln203_13_fu_74718_p1 == 6'd13) & ~(trunc_ln203_13_fu_74718_p1 == 6'd14) & ~(trunc_ln203_13_fu_74718_p1 == 6'd15) & ~(trunc_ln203_13_fu_74718_p1 == 6'd16) & ~(trunc_ln203_13_fu_74718_p1 == 6'd17) & ~(trunc_ln203_13_fu_74718_p1 == 6'd18) & ~(trunc_ln203_13_fu_74718_p1 == 6'd19) & ~(trunc_ln203_13_fu_74718_p1 == 6'd20) & ~(trunc_ln203_13_fu_74718_p1 == 6'd21) & ~(trunc_ln203_13_fu_74718_p1 == 6'd22) & ~(trunc_ln203_13_fu_74718_p1 == 6'd23) & ~(trunc_ln203_13_fu_74718_p1 == 6'd24) & ~(trunc_ln203_13_fu_74718_p1 == 6'd25) & ~(trunc_ln203_13_fu_74718_p1 == 6'd26) & (ap_ST_fsm_state149 == ap_CS_fsm)) | (~(trunc_ln203_14_fu_74658_p1 == 6'd0) & ~(trunc_ln203_14_fu_74658_p1 == 6'd1) & ~(trunc_ln203_14_fu_74658_p1 == 6'd2) & ~(trunc_ln203_14_fu_74658_p1 == 6'd3) & ~(trunc_ln203_14_fu_74658_p1 == 6'd4) & ~(trunc_ln203_14_fu_74658_p1 == 6'd5) & ~(trunc_ln203_14_fu_74658_p1 == 6'd6) & ~(trunc_ln203_14_fu_74658_p1 == 6'd7) & ~(trunc_ln203_14_fu_74658_p1 == 6'd8) & ~(trunc_ln203_14_fu_74658_p1 == 6'd9) & ~(trunc_ln203_14_fu_74658_p1 == 6'd10) & ~(trunc_ln203_14_fu_74658_p1 == 6'd11) & ~(trunc_ln203_14_fu_74658_p1 == 6'd12) & ~(trunc_ln203_14_fu_74658_p1 == 6'd13) & ~(trunc_ln203_14_fu_74658_p1 == 6'd14) & ~(trunc_ln203_14_fu_74658_p1 == 6'd15) & ~(trunc_ln203_14_fu_74658_p1 == 6'd16) & ~(trunc_ln203_14_fu_74658_p1 == 6'd17) & ~(trunc_ln203_14_fu_74658_p1 == 6'd18) & ~(trunc_ln203_14_fu_74658_p1 == 6'd19) & ~(trunc_ln203_14_fu_74658_p1 == 6'd20) & ~(trunc_ln203_14_fu_74658_p1 == 6'd21) & ~(trunc_ln203_14_fu_74658_p1 == 6'd22) & ~(trunc_ln203_14_fu_74658_p1 == 6'd23) & ~(trunc_ln203_14_fu_74658_p1 == 6'd24) & ~(trunc_ln203_14_fu_74658_p1 == 6'd25) & ~(trunc_ln203_14_fu_74658_p1 == 6'd26) & (ap_ST_fsm_state113 == ap_CS_fsm)) | (~(trunc_ln203_fu_74445_p1 == 6'd0) & ~(trunc_ln203_fu_74445_p1 == 6'd1) & ~(trunc_ln203_fu_74445_p1 == 6'd2) & ~(trunc_ln203_fu_74445_p1 == 6'd3) & ~(trunc_ln203_fu_74445_p1 == 6'd4) & ~(trunc_ln203_fu_74445_p1 == 6'd5) & ~(trunc_ln203_fu_74445_p1 == 6'd6) & ~(trunc_ln203_fu_74445_p1 == 6'd7) & ~(trunc_ln203_fu_74445_p1 == 6'd8) & ~(trunc_ln203_fu_74445_p1 == 6'd9) & ~(trunc_ln203_fu_74445_p1 == 6'd10) & ~(trunc_ln203_fu_74445_p1 == 6'd11) & ~(trunc_ln203_fu_74445_p1 == 6'd12) & ~(trunc_ln203_fu_74445_p1 == 6'd13) & ~(trunc_ln203_fu_74445_p1 == 6'd14) & ~(trunc_ln203_fu_74445_p1 == 6'd15) & ~(trunc_ln203_fu_74445_p1 == 6'd16) & ~(trunc_ln203_fu_74445_p1 == 6'd17) & ~(trunc_ln203_fu_74445_p1 == 6'd18) & ~(trunc_ln203_fu_74445_p1 == 6'd19) & ~(trunc_ln203_fu_74445_p1 == 6'd20) & ~(trunc_ln203_fu_74445_p1 == 6'd21) & ~(trunc_ln203_fu_74445_p1 == 6'd22) & ~(trunc_ln203_fu_74445_p1 == 6'd23) & ~(trunc_ln203_fu_74445_p1 == 6'd24) & ~(trunc_ln203_fu_74445_p1 == 6'd25) & ~(trunc_ln203_fu_74445_p1 == 6'd26) & (ap_ST_fsm_state78 == ap_CS_fsm)) | (~(trunc_ln203_5_fu_74188_p1 == 6'd0) & ~(trunc_ln203_5_fu_74188_p1 == 6'd1) & ~(trunc_ln203_5_fu_74188_p1 == 6'd2) & ~(trunc_ln203_5_fu_74188_p1 == 6'd3) & ~(trunc_ln203_5_fu_74188_p1 == 6'd4) & ~(trunc_ln203_5_fu_74188_p1 == 6'd5) & ~(trunc_ln203_5_fu_74188_p1 == 6'd6) & ~(trunc_ln203_5_fu_74188_p1 == 6'd7) & ~(trunc_ln203_5_fu_74188_p1 == 6'd8) & ~(trunc_ln203_5_fu_74188_p1 == 6'd9) & ~(trunc_ln203_5_fu_74188_p1 == 6'd10) & ~(trunc_ln203_5_fu_74188_p1 == 6'd11) & ~(trunc_ln203_5_fu_74188_p1 == 6'd12) & ~(trunc_ln203_5_fu_74188_p1 == 6'd13) & ~(trunc_ln203_5_fu_74188_p1 == 6'd14) & ~(trunc_ln203_5_fu_74188_p1 == 6'd15) & ~(trunc_ln203_5_fu_74188_p1 == 6'd16) & ~(trunc_ln203_5_fu_74188_p1 == 6'd17) & ~(trunc_ln203_5_fu_74188_p1 == 6'd18) & ~(trunc_ln203_5_fu_74188_p1 == 6'd19) & ~(trunc_ln203_5_fu_74188_p1 == 6'd20) & ~(trunc_ln203_5_fu_74188_p1 == 6'd21) & ~(trunc_ln203_5_fu_74188_p1 == 6'd22) & ~(trunc_ln203_5_fu_74188_p1 == 6'd23) & ~(trunc_ln203_5_fu_74188_p1 == 6'd24) & ~(trunc_ln203_5_fu_74188_p1 == 6'd25) & ~(trunc_ln203_5_fu_74188_p1 == 6'd26) & (ap_ST_fsm_state42 == ap_CS_fsm)))) begin + mult_27_V_we0 = 1'b1; + end else begin + mult_27_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_2_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_2_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_2_V_ce0 = 1'b1; + end else begin + mult_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_2_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_2_V_d0 = trunc_ln_reg_90250; + end else begin + mult_2_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd2) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd2) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd2) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd2) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd2) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd2)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd2)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd2)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd2)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd2)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd2)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd2)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd2)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd2)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd2)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd2)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd2)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd2)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd2)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd2)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd2)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd2)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd2)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd2)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd2)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd2)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd2)) | ((trunc_ln203_20_fu_75012_p1 == 6'd2) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd2) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd2) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd2)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd2)))) begin + mult_2_V_we0 = 1'b1; + end else begin + mult_2_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_3_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_3_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_3_V_ce0 = 1'b1; + end else begin + mult_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_3_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_3_V_d0 = trunc_ln_reg_90250; + end else begin + mult_3_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd3) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd3) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd3) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd3) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd3) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd3)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd3)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd3)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd3)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd3)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd3)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd3)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd3)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd3)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd3)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd3)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd3)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd3)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd3)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd3)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd3)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd3)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd3)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd3)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd3)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd3)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd3)) | ((trunc_ln203_20_fu_75012_p1 == 6'd3) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd3) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd3) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd3)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd3)))) begin + mult_3_V_we0 = 1'b1; + end else begin + mult_3_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_4_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_4_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_4_V_ce0 = 1'b1; + end else begin + mult_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_4_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_4_V_d0 = trunc_ln_reg_90250; + end else begin + mult_4_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd4) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd4) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd4) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd4) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd4) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd4)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd4)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd4)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd4)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd4)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd4)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd4)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd4)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd4)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd4)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd4)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd4)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd4)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd4)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd4)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd4)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd4)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd4)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd4)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd4)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd4)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd4)) | ((trunc_ln203_20_fu_75012_p1 == 6'd4) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd4) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd4) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd4)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd4)))) begin + mult_4_V_we0 = 1'b1; + end else begin + mult_4_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_5_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_5_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_5_V_ce0 = 1'b1; + end else begin + mult_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_5_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_5_V_d0 = trunc_ln_reg_90250; + end else begin + mult_5_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd5) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd5) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd5) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd5) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd5) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd5)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd5)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd5)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd5)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd5)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd5)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd5)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd5)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd5)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd5)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd5)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd5)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd5)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd5)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd5)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd5)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd5)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd5)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd5)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd5)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd5)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd5)) | ((trunc_ln203_20_fu_75012_p1 == 6'd5) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd5) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd5) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd5)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd5)))) begin + mult_5_V_we0 = 1'b1; + end else begin + mult_5_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_6_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_6_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_6_V_ce0 = 1'b1; + end else begin + mult_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_6_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_6_V_d0 = trunc_ln_reg_90250; + end else begin + mult_6_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd6) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd6) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd6) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd6) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd6) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd6)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd6)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd6)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd6)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd6)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd6)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd6)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd6)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd6)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd6)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd6)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd6)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd6)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd6)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd6)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd6)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd6)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd6)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd6)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd6)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd6)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd6)) | ((trunc_ln203_20_fu_75012_p1 == 6'd6) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd6) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd6) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd6)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd6)))) begin + mult_6_V_we0 = 1'b1; + end else begin + mult_6_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_7_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_7_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_7_V_ce0 = 1'b1; + end else begin + mult_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_7_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_7_V_d0 = trunc_ln_reg_90250; + end else begin + mult_7_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd7) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd7) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd7) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd7) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd7) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd7)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd7)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd7)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd7)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd7)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd7)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd7)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd7)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd7)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd7)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd7)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd7)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd7)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd7)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd7)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd7)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd7)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd7)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd7)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd7)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd7)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd7)) | ((trunc_ln203_20_fu_75012_p1 == 6'd7) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd7) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd7) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd7)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd7)))) begin + mult_7_V_we0 = 1'b1; + end else begin + mult_7_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_8_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_8_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_8_V_ce0 = 1'b1; + end else begin + mult_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_8_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_8_V_d0 = trunc_ln_reg_90250; + end else begin + mult_8_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd8) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd8) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd8) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd8) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd8) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd8)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd8)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd8)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd8)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd8)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd8)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd8)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd8)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd8)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd8)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd8)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd8)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd8)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd8)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd8)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd8)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd8)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd8)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd8)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd8)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd8)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd8)) | ((trunc_ln203_20_fu_75012_p1 == 6'd8) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd8) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd8) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd8)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd8)))) begin + mult_8_V_we0 = 1'b1; + end else begin + mult_8_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2384 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_77_fu_89832_p1; + end else if ((ap_ST_fsm_state2348 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_71_fu_89671_p1; + end else if ((ap_ST_fsm_state2310 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_63_fu_89389_p1; + end else if ((ap_ST_fsm_state2274 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_49_fu_89066_p1; + end else if ((ap_ST_fsm_state2235 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_61_fu_88883_p1; + end else if ((ap_ST_fsm_state2198 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_45_fu_88705_p1; + end else if ((ap_ST_fsm_state2160 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_32_fu_88406_p1; + end else if ((ap_ST_fsm_state2124 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_19_fu_88034_p1; + end else if ((ap_ST_fsm_state2085 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_73_fu_87744_p1; + end else if ((ap_ST_fsm_state2049 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_65_fu_87582_p1; + end else if ((ap_ST_fsm_state2011 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_55_fu_87299_p1; + end else if ((ap_ST_fsm_state1975 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_39_fu_86975_p1; + end else if ((ap_ST_fsm_state1936 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_51_fu_86792_p1; + end else if ((ap_ST_fsm_state1899 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_34_fu_86614_p1; + end else if ((ap_ST_fsm_state1861 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_22_fu_86315_p1; + end else if ((ap_ST_fsm_state1824 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_13_fu_85943_p1; + end else if ((ap_ST_fsm_state1784 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_75_fu_85485_p1; + end else if ((ap_ST_fsm_state1748 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_67_fu_85324_p1; + end else if ((ap_ST_fsm_state1710 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_57_fu_85042_p1; + end else if ((ap_ST_fsm_state1674 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_41_fu_84719_p1; + end else if ((ap_ST_fsm_state1635 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_53_fu_84536_p1; + end else if ((ap_ST_fsm_state1598 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_36_fu_84358_p1; + end else if ((ap_ST_fsm_state1560 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_24_fu_84059_p1; + end else if ((ap_ST_fsm_state1523 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_15_fu_83687_p1; + end else if ((ap_ST_fsm_state1484 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_69_fu_83397_p1; + end else if ((ap_ST_fsm_state1448 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_59_fu_83235_p1; + end else if ((ap_ST_fsm_state1410 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_47_fu_82952_p1; + end else if ((ap_ST_fsm_state1373 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_30_fu_82628_p1; + end else if ((ap_ST_fsm_state1334 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_43_fu_82445_p1; + end else if ((ap_ST_fsm_state1297 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_26_fu_82266_p1; + end else if ((ap_ST_fsm_state1259 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_17_fu_82100_p1; + end else if ((ap_ST_fsm_state1222 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln1265_9_fu_81860_p1; + end else if ((ap_ST_fsm_state1164 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_73_fu_80586_p1; + end else if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_75_fu_80526_p1; + end else if ((ap_ST_fsm_state1093 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_57_fu_80335_p1; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_59_fu_80157_p1; + end else if ((ap_ST_fsm_state1020 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_45_fu_79873_p1; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_47_fu_79813_p1; + end else if ((ap_ST_fsm_state949 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_25_fu_79622_p1; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_27_fu_79345_p1; + end else if ((ap_ST_fsm_state874 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_65_fu_78905_p1; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_67_fu_78845_p1; + end else if ((ap_ST_fsm_state803 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_49_fu_78654_p1; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_51_fu_78476_p1; + end else if ((ap_ST_fsm_state730 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_33_fu_78182_p1; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_35_fu_78122_p1; + end else if ((ap_ST_fsm_state659 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_17_fu_77910_p1; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_19_fu_77653_p1; + end else if ((ap_ST_fsm_state583 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_69_fu_77125_p1; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_71_fu_77065_p1; + end else if ((ap_ST_fsm_state512 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_53_fu_76874_p1; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_55_fu_76696_p1; + end else if ((ap_ST_fsm_state439 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_37_fu_76412_p1; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_39_fu_76352_p1; + end else if ((ap_ST_fsm_state368 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_21_fu_76139_p1; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_23_fu_75882_p1; + end else if ((ap_ST_fsm_state293 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_61_fu_75445_p1; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_63_fu_75385_p1; + end else if ((ap_ST_fsm_state222 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_41_fu_75194_p1; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_43_fu_75016_p1; + end else if ((ap_ST_fsm_state149 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_29_fu_74722_p1; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_31_fu_74662_p1; + end else if ((ap_ST_fsm_state78 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_12_fu_74449_p1; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_9_V_address0 = zext_ln203_14_fu_74192_p1; + end else begin + mult_9_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state984 == ap_CS_fsm) | (ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state913 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state838 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state767 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state694 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state623 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state547 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state476 == ap_CS_fsm) | (ap_ST_fsm_state42 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state403 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state332 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state257 == ap_CS_fsm) | (ap_ST_fsm_state2384 == ap_CS_fsm) | (ap_ST_fsm_state2348 == ap_CS_fsm) | (ap_ST_fsm_state2310 == ap_CS_fsm) | (ap_ST_fsm_state2274 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state2235 == ap_CS_fsm) | (ap_ST_fsm_state2198 == ap_CS_fsm) | (ap_ST_fsm_state2160 == ap_CS_fsm) | (ap_ST_fsm_state2124 == ap_CS_fsm) | (ap_ST_fsm_state2085 == ap_CS_fsm) | (ap_ST_fsm_state2049 == ap_CS_fsm) | (ap_ST_fsm_state2011 == ap_CS_fsm) | (ap_ST_fsm_state1975 == ap_CS_fsm) | (ap_ST_fsm_state1936 == ap_CS_fsm) | (ap_ST_fsm_state1899 == ap_CS_fsm) | (ap_ST_fsm_state186 == ap_CS_fsm) | (ap_ST_fsm_state1861 == ap_CS_fsm) | (ap_ST_fsm_state1824 == ap_CS_fsm) | (ap_ST_fsm_state1784 == ap_CS_fsm) | (ap_ST_fsm_state1748 == ap_CS_fsm) | (ap_ST_fsm_state1710 == ap_CS_fsm) | (ap_ST_fsm_state1674 == ap_CS_fsm) | (ap_ST_fsm_state1635 == ap_CS_fsm) | (ap_ST_fsm_state1598 == ap_CS_fsm) | (ap_ST_fsm_state1560 == ap_CS_fsm) | (ap_ST_fsm_state1523 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1484 == ap_CS_fsm) | (ap_ST_fsm_state1448 == ap_CS_fsm) | (ap_ST_fsm_state1410 == ap_CS_fsm) | (ap_ST_fsm_state1373 == ap_CS_fsm) | (ap_ST_fsm_state1334 == ap_CS_fsm) | (ap_ST_fsm_state1297 == ap_CS_fsm) | (ap_ST_fsm_state1259 == ap_CS_fsm) | (ap_ST_fsm_state1222 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state113 == ap_CS_fsm) | (ap_ST_fsm_state1128 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1057 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_9_V_ce0 = 1'b1; + end else begin + mult_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1128 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_14_reg_92021; + end else if ((ap_ST_fsm_state1057 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_10_reg_91929; + end else if ((ap_ST_fsm_state984 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_7_reg_91826; + end else if ((ap_ST_fsm_state913 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_2_reg_91709; + end else if ((ap_ST_fsm_state838 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_12_reg_91550; + end else if ((ap_ST_fsm_state767 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_8_reg_91458; + end else if ((ap_ST_fsm_state694 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_4_reg_91355; + end else if ((ap_ST_fsm_state623 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_s_reg_91243; + end else if ((ap_ST_fsm_state547 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_13_reg_91017; + end else if ((ap_ST_fsm_state476 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_9_reg_90925; + end else if ((ap_ST_fsm_state403 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_5_reg_90822; + end else if ((ap_ST_fsm_state332 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_1_reg_90710; + end else if ((ap_ST_fsm_state257 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_11_reg_90557; + end else if ((ap_ST_fsm_state186 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_6_reg_90465; + end else if ((ap_ST_fsm_state113 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln708_3_reg_90362; + end else if (((ap_ST_fsm_state949 == ap_CS_fsm) | (ap_ST_fsm_state874 == ap_CS_fsm) | (ap_ST_fsm_state78 == ap_CS_fsm) | (ap_ST_fsm_state803 == ap_CS_fsm) | (ap_ST_fsm_state730 == ap_CS_fsm) | (ap_ST_fsm_state659 == ap_CS_fsm) | (ap_ST_fsm_state583 == ap_CS_fsm) | (ap_ST_fsm_state512 == ap_CS_fsm) | (ap_ST_fsm_state439 == ap_CS_fsm) | (ap_ST_fsm_state368 == ap_CS_fsm) | (ap_ST_fsm_state293 == ap_CS_fsm) | (ap_ST_fsm_state222 == ap_CS_fsm) | (ap_ST_fsm_state149 == ap_CS_fsm) | (ap_ST_fsm_state1164 == ap_CS_fsm) | (ap_ST_fsm_state1093 == ap_CS_fsm) | (ap_ST_fsm_state1020 == ap_CS_fsm))) begin + mult_9_V_d0 = 8'd0; + end else if ((ap_ST_fsm_state42 == ap_CS_fsm)) begin + mult_9_V_d0 = trunc_ln_reg_90250; + end else begin + mult_9_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((trunc_ln203_35_fu_80582_p1 == 6'd9) & (ap_ST_fsm_state1164 == ap_CS_fsm)) | ((trunc_ln203_36_fu_80522_p1 == 6'd9) & (ap_ST_fsm_state1128 == ap_CS_fsm)) | ((trunc_ln203_27_fu_80331_p1 == 6'd9) & (ap_ST_fsm_state1093 == ap_CS_fsm)) | ((trunc_ln203_28_fu_80153_p1 == 6'd9) & (ap_ST_fsm_state1057 == ap_CS_fsm)) | ((trunc_ln203_21_fu_79869_p1 == 6'd9) & (ap_ST_fsm_state1020 == ap_CS_fsm)) | ((ap_ST_fsm_state984 == ap_CS_fsm) & (trunc_ln203_22_fu_79809_p1 == 6'd9)) | ((ap_ST_fsm_state949 == ap_CS_fsm) & (trunc_ln203_11_fu_79618_p1 == 6'd9)) | ((ap_ST_fsm_state913 == ap_CS_fsm) & (trunc_ln203_12_fu_79341_p1 == 6'd9)) | ((ap_ST_fsm_state874 == ap_CS_fsm) & (trunc_ln203_31_fu_78901_p1 == 6'd9)) | ((ap_ST_fsm_state838 == ap_CS_fsm) & (trunc_ln203_32_fu_78841_p1 == 6'd9)) | ((ap_ST_fsm_state803 == ap_CS_fsm) & (trunc_ln203_23_fu_78650_p1 == 6'd9)) | ((ap_ST_fsm_state767 == ap_CS_fsm) & (trunc_ln203_24_fu_78472_p1 == 6'd9)) | ((ap_ST_fsm_state730 == ap_CS_fsm) & (trunc_ln203_15_fu_78178_p1 == 6'd9)) | ((ap_ST_fsm_state694 == ap_CS_fsm) & (trunc_ln203_16_fu_78118_p1 == 6'd9)) | ((ap_ST_fsm_state659 == ap_CS_fsm) & (trunc_ln203_7_fu_77906_p1 == 6'd9)) | ((ap_ST_fsm_state623 == ap_CS_fsm) & (trunc_ln203_8_fu_77649_p1 == 6'd9)) | ((ap_ST_fsm_state583 == ap_CS_fsm) & (trunc_ln203_33_fu_77121_p1 == 6'd9)) | ((ap_ST_fsm_state547 == ap_CS_fsm) & (trunc_ln203_34_fu_77061_p1 == 6'd9)) | ((ap_ST_fsm_state512 == ap_CS_fsm) & (trunc_ln203_25_fu_76870_p1 == 6'd9)) | ((ap_ST_fsm_state476 == ap_CS_fsm) & (trunc_ln203_26_fu_76692_p1 == 6'd9)) | ((ap_ST_fsm_state439 == ap_CS_fsm) & (trunc_ln203_17_fu_76408_p1 == 6'd9)) | ((ap_ST_fsm_state403 == ap_CS_fsm) & (trunc_ln203_18_fu_76348_p1 == 6'd9)) | ((ap_ST_fsm_state368 == ap_CS_fsm) & (trunc_ln203_9_fu_76135_p1 == 6'd9)) | ((ap_ST_fsm_state332 == ap_CS_fsm) & (trunc_ln203_10_fu_75878_p1 == 6'd9)) | ((ap_ST_fsm_state293 == ap_CS_fsm) & (trunc_ln203_29_fu_75441_p1 == 6'd9)) | ((ap_ST_fsm_state257 == ap_CS_fsm) & (trunc_ln203_30_fu_75381_p1 == 6'd9)) | ((ap_ST_fsm_state222 == ap_CS_fsm) & (trunc_ln203_19_fu_75190_p1 == 6'd9)) | ((trunc_ln203_20_fu_75012_p1 == 6'd9) & (ap_ST_fsm_state186 == ap_CS_fsm)) | ((trunc_ln203_13_fu_74718_p1 == 6'd9) & (ap_ST_fsm_state149 == ap_CS_fsm)) | ((trunc_ln203_14_fu_74658_p1 == 6'd9) & (ap_ST_fsm_state113 == ap_CS_fsm)) | ((ap_ST_fsm_state78 == ap_CS_fsm) & (trunc_ln203_fu_74445_p1 == 6'd9)) | ((ap_ST_fsm_state42 == ap_CS_fsm) & (trunc_ln203_5_fu_74188_p1 == 6'd9)))) begin + mult_9_V_we0 = 1'b1; + end else begin + mult_9_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_0_V_address0 = 64'd0; + end else begin + res_0_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_0_V_ce0 = 1'b1; + end else begin + res_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_0_V_we0 = 1'b1; + end else begin + res_0_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_100_V_address0 = 64'd0; + end else begin + res_100_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_100_V_ce0 = 1'b1; + end else begin + res_100_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_100_V_we0 = 1'b1; + end else begin + res_100_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_101_V_address0 = 64'd0; + end else begin + res_101_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_101_V_ce0 = 1'b1; + end else begin + res_101_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_101_V_we0 = 1'b1; + end else begin + res_101_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_102_V_address0 = 64'd0; + end else begin + res_102_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_102_V_ce0 = 1'b1; + end else begin + res_102_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_102_V_we0 = 1'b1; + end else begin + res_102_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_103_V_address0 = 64'd0; + end else begin + res_103_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_103_V_ce0 = 1'b1; + end else begin + res_103_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_103_V_we0 = 1'b1; + end else begin + res_103_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_104_V_address0 = 64'd0; + end else begin + res_104_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_104_V_ce0 = 1'b1; + end else begin + res_104_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_104_V_we0 = 1'b1; + end else begin + res_104_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_105_V_address0 = 64'd0; + end else begin + res_105_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_105_V_ce0 = 1'b1; + end else begin + res_105_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_105_V_we0 = 1'b1; + end else begin + res_105_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_106_V_address0 = 64'd0; + end else begin + res_106_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_106_V_ce0 = 1'b1; + end else begin + res_106_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_106_V_we0 = 1'b1; + end else begin + res_106_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_107_V_address0 = 64'd0; + end else begin + res_107_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_107_V_ce0 = 1'b1; + end else begin + res_107_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_107_V_we0 = 1'b1; + end else begin + res_107_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_108_V_address0 = 64'd0; + end else begin + res_108_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_108_V_ce0 = 1'b1; + end else begin + res_108_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_108_V_we0 = 1'b1; + end else begin + res_108_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_109_V_address0 = 64'd0; + end else begin + res_109_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_109_V_ce0 = 1'b1; + end else begin + res_109_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_109_V_we0 = 1'b1; + end else begin + res_109_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_10_V_address0 = 64'd0; + end else begin + res_10_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_10_V_ce0 = 1'b1; + end else begin + res_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_10_V_we0 = 1'b1; + end else begin + res_10_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_110_V_address0 = 64'd0; + end else begin + res_110_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_110_V_ce0 = 1'b1; + end else begin + res_110_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_110_V_we0 = 1'b1; + end else begin + res_110_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_111_V_address0 = 64'd0; + end else begin + res_111_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_111_V_ce0 = 1'b1; + end else begin + res_111_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_111_V_we0 = 1'b1; + end else begin + res_111_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_112_V_address0 = 64'd0; + end else begin + res_112_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_112_V_ce0 = 1'b1; + end else begin + res_112_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_112_V_we0 = 1'b1; + end else begin + res_112_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_113_V_address0 = 64'd0; + end else begin + res_113_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_113_V_ce0 = 1'b1; + end else begin + res_113_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_113_V_we0 = 1'b1; + end else begin + res_113_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_114_V_address0 = 64'd0; + end else begin + res_114_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_114_V_ce0 = 1'b1; + end else begin + res_114_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_114_V_we0 = 1'b1; + end else begin + res_114_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_115_V_address0 = 64'd0; + end else begin + res_115_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_115_V_ce0 = 1'b1; + end else begin + res_115_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_115_V_we0 = 1'b1; + end else begin + res_115_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_116_V_address0 = 64'd0; + end else begin + res_116_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_116_V_ce0 = 1'b1; + end else begin + res_116_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_116_V_we0 = 1'b1; + end else begin + res_116_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_117_V_address0 = 64'd0; + end else begin + res_117_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_117_V_ce0 = 1'b1; + end else begin + res_117_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_117_V_we0 = 1'b1; + end else begin + res_117_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_118_V_address0 = 64'd0; + end else begin + res_118_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_118_V_ce0 = 1'b1; + end else begin + res_118_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_118_V_we0 = 1'b1; + end else begin + res_118_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_119_V_address0 = 64'd0; + end else begin + res_119_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_119_V_ce0 = 1'b1; + end else begin + res_119_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_119_V_we0 = 1'b1; + end else begin + res_119_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_11_V_address0 = 64'd0; + end else begin + res_11_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_11_V_ce0 = 1'b1; + end else begin + res_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_11_V_we0 = 1'b1; + end else begin + res_11_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_120_V_address0 = 64'd0; + end else begin + res_120_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_120_V_ce0 = 1'b1; + end else begin + res_120_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_120_V_we0 = 1'b1; + end else begin + res_120_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_121_V_address0 = 64'd0; + end else begin + res_121_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_121_V_ce0 = 1'b1; + end else begin + res_121_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_121_V_we0 = 1'b1; + end else begin + res_121_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_122_V_address0 = 64'd0; + end else begin + res_122_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_122_V_ce0 = 1'b1; + end else begin + res_122_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_122_V_we0 = 1'b1; + end else begin + res_122_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_123_V_address0 = 64'd0; + end else begin + res_123_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_123_V_ce0 = 1'b1; + end else begin + res_123_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_123_V_we0 = 1'b1; + end else begin + res_123_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_124_V_address0 = 64'd0; + end else begin + res_124_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_124_V_ce0 = 1'b1; + end else begin + res_124_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_124_V_we0 = 1'b1; + end else begin + res_124_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_125_V_address0 = 64'd0; + end else begin + res_125_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_125_V_ce0 = 1'b1; + end else begin + res_125_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_125_V_we0 = 1'b1; + end else begin + res_125_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_126_V_address0 = 64'd0; + end else begin + res_126_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_126_V_ce0 = 1'b1; + end else begin + res_126_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_126_V_we0 = 1'b1; + end else begin + res_126_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_127_V_address0 = 64'd0; + end else begin + res_127_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_127_V_ce0 = 1'b1; + end else begin + res_127_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_127_V_we0 = 1'b1; + end else begin + res_127_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_12_V_address0 = 64'd0; + end else begin + res_12_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_12_V_ce0 = 1'b1; + end else begin + res_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_12_V_we0 = 1'b1; + end else begin + res_12_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_13_V_address0 = 64'd0; + end else begin + res_13_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_13_V_ce0 = 1'b1; + end else begin + res_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_13_V_we0 = 1'b1; + end else begin + res_13_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_14_V_address0 = 64'd0; + end else begin + res_14_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_14_V_ce0 = 1'b1; + end else begin + res_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_14_V_we0 = 1'b1; + end else begin + res_14_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_15_V_address0 = 64'd0; + end else begin + res_15_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_15_V_ce0 = 1'b1; + end else begin + res_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_15_V_we0 = 1'b1; + end else begin + res_15_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_16_V_address0 = 64'd0; + end else begin + res_16_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_16_V_ce0 = 1'b1; + end else begin + res_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_16_V_we0 = 1'b1; + end else begin + res_16_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_17_V_address0 = 64'd0; + end else begin + res_17_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_17_V_ce0 = 1'b1; + end else begin + res_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_17_V_we0 = 1'b1; + end else begin + res_17_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_18_V_address0 = 64'd0; + end else begin + res_18_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_18_V_ce0 = 1'b1; + end else begin + res_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_18_V_we0 = 1'b1; + end else begin + res_18_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_19_V_address0 = 64'd0; + end else begin + res_19_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_19_V_ce0 = 1'b1; + end else begin + res_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_19_V_we0 = 1'b1; + end else begin + res_19_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_1_V_address0 = 64'd0; + end else begin + res_1_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_1_V_ce0 = 1'b1; + end else begin + res_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_1_V_we0 = 1'b1; + end else begin + res_1_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_20_V_address0 = 64'd0; + end else begin + res_20_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_20_V_ce0 = 1'b1; + end else begin + res_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_20_V_we0 = 1'b1; + end else begin + res_20_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_21_V_address0 = 64'd0; + end else begin + res_21_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_21_V_ce0 = 1'b1; + end else begin + res_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_21_V_we0 = 1'b1; + end else begin + res_21_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_22_V_address0 = 64'd0; + end else begin + res_22_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_22_V_ce0 = 1'b1; + end else begin + res_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_22_V_we0 = 1'b1; + end else begin + res_22_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_23_V_address0 = 64'd0; + end else begin + res_23_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_23_V_ce0 = 1'b1; + end else begin + res_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_23_V_we0 = 1'b1; + end else begin + res_23_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_24_V_address0 = 64'd0; + end else begin + res_24_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_24_V_ce0 = 1'b1; + end else begin + res_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_24_V_we0 = 1'b1; + end else begin + res_24_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_25_V_address0 = 64'd0; + end else begin + res_25_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_25_V_ce0 = 1'b1; + end else begin + res_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_25_V_we0 = 1'b1; + end else begin + res_25_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_26_V_address0 = 64'd0; + end else begin + res_26_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_26_V_ce0 = 1'b1; + end else begin + res_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_26_V_we0 = 1'b1; + end else begin + res_26_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_27_V_address0 = 64'd0; + end else begin + res_27_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_27_V_ce0 = 1'b1; + end else begin + res_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_27_V_we0 = 1'b1; + end else begin + res_27_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_28_V_address0 = 64'd0; + end else begin + res_28_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_28_V_ce0 = 1'b1; + end else begin + res_28_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_28_V_we0 = 1'b1; + end else begin + res_28_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_29_V_address0 = 64'd0; + end else begin + res_29_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_29_V_ce0 = 1'b1; + end else begin + res_29_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_29_V_we0 = 1'b1; + end else begin + res_29_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_2_V_address0 = 64'd0; + end else begin + res_2_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_2_V_ce0 = 1'b1; + end else begin + res_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_2_V_we0 = 1'b1; + end else begin + res_2_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_30_V_address0 = 64'd0; + end else begin + res_30_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_30_V_ce0 = 1'b1; + end else begin + res_30_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_30_V_we0 = 1'b1; + end else begin + res_30_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_31_V_address0 = 64'd0; + end else begin + res_31_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_31_V_ce0 = 1'b1; + end else begin + res_31_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_31_V_we0 = 1'b1; + end else begin + res_31_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_32_V_address0 = 64'd0; + end else begin + res_32_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_32_V_ce0 = 1'b1; + end else begin + res_32_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_32_V_we0 = 1'b1; + end else begin + res_32_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_33_V_address0 = 64'd0; + end else begin + res_33_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_33_V_ce0 = 1'b1; + end else begin + res_33_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_33_V_we0 = 1'b1; + end else begin + res_33_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_34_V_address0 = 64'd0; + end else begin + res_34_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_34_V_ce0 = 1'b1; + end else begin + res_34_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_34_V_we0 = 1'b1; + end else begin + res_34_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_35_V_address0 = 64'd0; + end else begin + res_35_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_35_V_ce0 = 1'b1; + end else begin + res_35_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_35_V_we0 = 1'b1; + end else begin + res_35_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_36_V_address0 = 64'd0; + end else begin + res_36_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_36_V_ce0 = 1'b1; + end else begin + res_36_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_36_V_we0 = 1'b1; + end else begin + res_36_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_37_V_address0 = 64'd0; + end else begin + res_37_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_37_V_ce0 = 1'b1; + end else begin + res_37_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_37_V_we0 = 1'b1; + end else begin + res_37_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_38_V_address0 = 64'd0; + end else begin + res_38_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_38_V_ce0 = 1'b1; + end else begin + res_38_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_38_V_we0 = 1'b1; + end else begin + res_38_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_39_V_address0 = 64'd0; + end else begin + res_39_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_39_V_ce0 = 1'b1; + end else begin + res_39_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_39_V_we0 = 1'b1; + end else begin + res_39_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_3_V_address0 = 64'd0; + end else begin + res_3_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_3_V_ce0 = 1'b1; + end else begin + res_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_3_V_we0 = 1'b1; + end else begin + res_3_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_40_V_address0 = 64'd0; + end else begin + res_40_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_40_V_ce0 = 1'b1; + end else begin + res_40_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_40_V_we0 = 1'b1; + end else begin + res_40_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_41_V_address0 = 64'd0; + end else begin + res_41_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_41_V_ce0 = 1'b1; + end else begin + res_41_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_41_V_we0 = 1'b1; + end else begin + res_41_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_42_V_address0 = 64'd0; + end else begin + res_42_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_42_V_ce0 = 1'b1; + end else begin + res_42_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_42_V_we0 = 1'b1; + end else begin + res_42_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_43_V_address0 = 64'd0; + end else begin + res_43_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_43_V_ce0 = 1'b1; + end else begin + res_43_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_43_V_we0 = 1'b1; + end else begin + res_43_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_44_V_address0 = 64'd0; + end else begin + res_44_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_44_V_ce0 = 1'b1; + end else begin + res_44_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_44_V_we0 = 1'b1; + end else begin + res_44_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_45_V_address0 = 64'd0; + end else begin + res_45_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_45_V_ce0 = 1'b1; + end else begin + res_45_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_45_V_we0 = 1'b1; + end else begin + res_45_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_46_V_address0 = 64'd0; + end else begin + res_46_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_46_V_ce0 = 1'b1; + end else begin + res_46_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_46_V_we0 = 1'b1; + end else begin + res_46_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_47_V_address0 = 64'd0; + end else begin + res_47_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_47_V_ce0 = 1'b1; + end else begin + res_47_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_47_V_we0 = 1'b1; + end else begin + res_47_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_48_V_address0 = 64'd0; + end else begin + res_48_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_48_V_ce0 = 1'b1; + end else begin + res_48_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_48_V_we0 = 1'b1; + end else begin + res_48_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_49_V_address0 = 64'd0; + end else begin + res_49_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_49_V_ce0 = 1'b1; + end else begin + res_49_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_49_V_we0 = 1'b1; + end else begin + res_49_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_4_V_address0 = 64'd0; + end else begin + res_4_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_4_V_ce0 = 1'b1; + end else begin + res_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_4_V_we0 = 1'b1; + end else begin + res_4_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_50_V_address0 = 64'd0; + end else begin + res_50_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_50_V_ce0 = 1'b1; + end else begin + res_50_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_50_V_we0 = 1'b1; + end else begin + res_50_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_51_V_address0 = 64'd0; + end else begin + res_51_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_51_V_ce0 = 1'b1; + end else begin + res_51_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_51_V_we0 = 1'b1; + end else begin + res_51_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_52_V_address0 = 64'd0; + end else begin + res_52_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_52_V_ce0 = 1'b1; + end else begin + res_52_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_52_V_we0 = 1'b1; + end else begin + res_52_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_53_V_address0 = 64'd0; + end else begin + res_53_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_53_V_ce0 = 1'b1; + end else begin + res_53_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_53_V_we0 = 1'b1; + end else begin + res_53_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_54_V_address0 = 64'd0; + end else begin + res_54_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_54_V_ce0 = 1'b1; + end else begin + res_54_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_54_V_we0 = 1'b1; + end else begin + res_54_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_55_V_address0 = 64'd0; + end else begin + res_55_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_55_V_ce0 = 1'b1; + end else begin + res_55_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_55_V_we0 = 1'b1; + end else begin + res_55_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_56_V_address0 = 64'd0; + end else begin + res_56_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_56_V_ce0 = 1'b1; + end else begin + res_56_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_56_V_we0 = 1'b1; + end else begin + res_56_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_57_V_address0 = 64'd0; + end else begin + res_57_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_57_V_ce0 = 1'b1; + end else begin + res_57_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_57_V_we0 = 1'b1; + end else begin + res_57_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_58_V_address0 = 64'd0; + end else begin + res_58_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_58_V_ce0 = 1'b1; + end else begin + res_58_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_58_V_we0 = 1'b1; + end else begin + res_58_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_59_V_address0 = 64'd0; + end else begin + res_59_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_59_V_ce0 = 1'b1; + end else begin + res_59_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_59_V_we0 = 1'b1; + end else begin + res_59_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_5_V_address0 = 64'd0; + end else begin + res_5_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_5_V_ce0 = 1'b1; + end else begin + res_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_5_V_we0 = 1'b1; + end else begin + res_5_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_60_V_address0 = 64'd0; + end else begin + res_60_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_60_V_ce0 = 1'b1; + end else begin + res_60_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_60_V_we0 = 1'b1; + end else begin + res_60_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_61_V_address0 = 64'd0; + end else begin + res_61_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_61_V_ce0 = 1'b1; + end else begin + res_61_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_61_V_we0 = 1'b1; + end else begin + res_61_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_62_V_address0 = 64'd0; + end else begin + res_62_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_62_V_ce0 = 1'b1; + end else begin + res_62_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_62_V_we0 = 1'b1; + end else begin + res_62_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_63_V_address0 = 64'd0; + end else begin + res_63_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_63_V_ce0 = 1'b1; + end else begin + res_63_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_63_V_we0 = 1'b1; + end else begin + res_63_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_64_V_address0 = 64'd0; + end else begin + res_64_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_64_V_ce0 = 1'b1; + end else begin + res_64_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_64_V_we0 = 1'b1; + end else begin + res_64_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_65_V_address0 = 64'd0; + end else begin + res_65_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_65_V_ce0 = 1'b1; + end else begin + res_65_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_65_V_we0 = 1'b1; + end else begin + res_65_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_66_V_address0 = 64'd0; + end else begin + res_66_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_66_V_ce0 = 1'b1; + end else begin + res_66_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_66_V_we0 = 1'b1; + end else begin + res_66_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_67_V_address0 = 64'd0; + end else begin + res_67_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_67_V_ce0 = 1'b1; + end else begin + res_67_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_67_V_we0 = 1'b1; + end else begin + res_67_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_68_V_address0 = 64'd0; + end else begin + res_68_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_68_V_ce0 = 1'b1; + end else begin + res_68_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_68_V_we0 = 1'b1; + end else begin + res_68_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_69_V_address0 = 64'd0; + end else begin + res_69_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_69_V_ce0 = 1'b1; + end else begin + res_69_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_69_V_we0 = 1'b1; + end else begin + res_69_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_6_V_address0 = 64'd0; + end else begin + res_6_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_6_V_ce0 = 1'b1; + end else begin + res_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_6_V_we0 = 1'b1; + end else begin + res_6_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_70_V_address0 = 64'd0; + end else begin + res_70_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_70_V_ce0 = 1'b1; + end else begin + res_70_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_70_V_we0 = 1'b1; + end else begin + res_70_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_71_V_address0 = 64'd0; + end else begin + res_71_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_71_V_ce0 = 1'b1; + end else begin + res_71_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_71_V_we0 = 1'b1; + end else begin + res_71_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_72_V_address0 = 64'd0; + end else begin + res_72_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_72_V_ce0 = 1'b1; + end else begin + res_72_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_72_V_we0 = 1'b1; + end else begin + res_72_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_73_V_address0 = 64'd0; + end else begin + res_73_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_73_V_ce0 = 1'b1; + end else begin + res_73_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_73_V_we0 = 1'b1; + end else begin + res_73_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_74_V_address0 = 64'd0; + end else begin + res_74_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_74_V_ce0 = 1'b1; + end else begin + res_74_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_74_V_we0 = 1'b1; + end else begin + res_74_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_75_V_address0 = 64'd0; + end else begin + res_75_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_75_V_ce0 = 1'b1; + end else begin + res_75_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_75_V_we0 = 1'b1; + end else begin + res_75_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_76_V_address0 = 64'd0; + end else begin + res_76_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_76_V_ce0 = 1'b1; + end else begin + res_76_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_76_V_we0 = 1'b1; + end else begin + res_76_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_77_V_address0 = 64'd0; + end else begin + res_77_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_77_V_ce0 = 1'b1; + end else begin + res_77_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_77_V_we0 = 1'b1; + end else begin + res_77_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_78_V_address0 = 64'd0; + end else begin + res_78_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_78_V_ce0 = 1'b1; + end else begin + res_78_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_78_V_we0 = 1'b1; + end else begin + res_78_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_79_V_address0 = 64'd0; + end else begin + res_79_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_79_V_ce0 = 1'b1; + end else begin + res_79_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_79_V_we0 = 1'b1; + end else begin + res_79_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_7_V_address0 = 64'd0; + end else begin + res_7_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_7_V_ce0 = 1'b1; + end else begin + res_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_7_V_we0 = 1'b1; + end else begin + res_7_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_80_V_address0 = 64'd0; + end else begin + res_80_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_80_V_ce0 = 1'b1; + end else begin + res_80_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_80_V_we0 = 1'b1; + end else begin + res_80_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_81_V_address0 = 64'd0; + end else begin + res_81_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_81_V_ce0 = 1'b1; + end else begin + res_81_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_81_V_we0 = 1'b1; + end else begin + res_81_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_82_V_address0 = 64'd0; + end else begin + res_82_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_82_V_ce0 = 1'b1; + end else begin + res_82_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_82_V_we0 = 1'b1; + end else begin + res_82_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_83_V_address0 = 64'd0; + end else begin + res_83_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_83_V_ce0 = 1'b1; + end else begin + res_83_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_83_V_we0 = 1'b1; + end else begin + res_83_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_84_V_address0 = 64'd0; + end else begin + res_84_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_84_V_ce0 = 1'b1; + end else begin + res_84_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_84_V_we0 = 1'b1; + end else begin + res_84_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_85_V_address0 = 64'd0; + end else begin + res_85_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_85_V_ce0 = 1'b1; + end else begin + res_85_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_85_V_we0 = 1'b1; + end else begin + res_85_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_86_V_address0 = 64'd0; + end else begin + res_86_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_86_V_ce0 = 1'b1; + end else begin + res_86_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_86_V_we0 = 1'b1; + end else begin + res_86_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_87_V_address0 = 64'd0; + end else begin + res_87_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_87_V_ce0 = 1'b1; + end else begin + res_87_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_87_V_we0 = 1'b1; + end else begin + res_87_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_88_V_address0 = 64'd0; + end else begin + res_88_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_88_V_ce0 = 1'b1; + end else begin + res_88_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_88_V_we0 = 1'b1; + end else begin + res_88_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_89_V_address0 = 64'd0; + end else begin + res_89_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_89_V_ce0 = 1'b1; + end else begin + res_89_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_89_V_we0 = 1'b1; + end else begin + res_89_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_8_V_address0 = 64'd0; + end else begin + res_8_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_8_V_ce0 = 1'b1; + end else begin + res_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_8_V_we0 = 1'b1; + end else begin + res_8_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_90_V_address0 = 64'd0; + end else begin + res_90_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_90_V_ce0 = 1'b1; + end else begin + res_90_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_90_V_we0 = 1'b1; + end else begin + res_90_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_91_V_address0 = 64'd0; + end else begin + res_91_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_91_V_ce0 = 1'b1; + end else begin + res_91_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_91_V_we0 = 1'b1; + end else begin + res_91_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_92_V_address0 = 64'd0; + end else begin + res_92_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_92_V_ce0 = 1'b1; + end else begin + res_92_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_92_V_we0 = 1'b1; + end else begin + res_92_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_93_V_address0 = 64'd0; + end else begin + res_93_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_93_V_ce0 = 1'b1; + end else begin + res_93_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_93_V_we0 = 1'b1; + end else begin + res_93_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_94_V_address0 = 64'd0; + end else begin + res_94_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_94_V_ce0 = 1'b1; + end else begin + res_94_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_94_V_we0 = 1'b1; + end else begin + res_94_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_95_V_address0 = 64'd0; + end else begin + res_95_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_95_V_ce0 = 1'b1; + end else begin + res_95_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_95_V_we0 = 1'b1; + end else begin + res_95_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_96_V_address0 = 64'd0; + end else begin + res_96_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_96_V_ce0 = 1'b1; + end else begin + res_96_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_96_V_we0 = 1'b1; + end else begin + res_96_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_97_V_address0 = 64'd0; + end else begin + res_97_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_97_V_ce0 = 1'b1; + end else begin + res_97_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_97_V_we0 = 1'b1; + end else begin + res_97_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_98_V_address0 = 64'd0; + end else begin + res_98_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_98_V_ce0 = 1'b1; + end else begin + res_98_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_98_V_we0 = 1'b1; + end else begin + res_98_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_99_V_address0 = 64'd0; + end else begin + res_99_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_99_V_ce0 = 1'b1; + end else begin + res_99_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_99_V_we0 = 1'b1; + end else begin + res_99_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2411 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd24; + end else if ((ap_ST_fsm_state2410 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd23; + end else if ((ap_ST_fsm_state2409 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd22; + end else if ((ap_ST_fsm_state2408 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd21; + end else if ((ap_ST_fsm_state2407 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd20; + end else if ((ap_ST_fsm_state2406 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd19; + end else if ((ap_ST_fsm_state2405 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd18; + end else if ((ap_ST_fsm_state2404 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd17; + end else if ((ap_ST_fsm_state2403 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd16; + end else if ((ap_ST_fsm_state2402 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd15; + end else if ((ap_ST_fsm_state2401 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd14; + end else if ((ap_ST_fsm_state2400 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd13; + end else if ((ap_ST_fsm_state2399 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd12; + end else if ((ap_ST_fsm_state2398 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd11; + end else if ((ap_ST_fsm_state2397 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd10; + end else if ((ap_ST_fsm_state2396 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd9; + end else if ((ap_ST_fsm_state2395 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state2394 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd7; + end else if ((ap_ST_fsm_state2393 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state2392 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd5; + end else if ((ap_ST_fsm_state2391 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state2390 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd3; + end else if ((ap_ST_fsm_state2389 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state2388 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd1; + end else if ((ap_ST_fsm_state2387 == ap_CS_fsm)) begin + res_9_V_address0 = 64'd0; + end else begin + res_9_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_9_V_ce0 = 1'b1; + end else begin + res_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2411 == ap_CS_fsm) | (ap_ST_fsm_state2410 == ap_CS_fsm) | (ap_ST_fsm_state2409 == ap_CS_fsm) | (ap_ST_fsm_state2408 == ap_CS_fsm) | (ap_ST_fsm_state2407 == ap_CS_fsm) | (ap_ST_fsm_state2406 == ap_CS_fsm) | (ap_ST_fsm_state2405 == ap_CS_fsm) | (ap_ST_fsm_state2404 == ap_CS_fsm) | (ap_ST_fsm_state2403 == ap_CS_fsm) | (ap_ST_fsm_state2402 == ap_CS_fsm) | (ap_ST_fsm_state2401 == ap_CS_fsm) | (ap_ST_fsm_state2400 == ap_CS_fsm) | (ap_ST_fsm_state2399 == ap_CS_fsm) | (ap_ST_fsm_state2398 == ap_CS_fsm) | (ap_ST_fsm_state2397 == ap_CS_fsm) | (ap_ST_fsm_state2396 == ap_CS_fsm) | (ap_ST_fsm_state2395 == ap_CS_fsm) | (ap_ST_fsm_state2394 == ap_CS_fsm) | (ap_ST_fsm_state2393 == ap_CS_fsm) | (ap_ST_fsm_state2392 == ap_CS_fsm) | (ap_ST_fsm_state2391 == ap_CS_fsm) | (ap_ST_fsm_state2390 == ap_CS_fsm) | (ap_ST_fsm_state2389 == ap_CS_fsm) | (ap_ST_fsm_state2388 == ap_CS_fsm) | (ap_ST_fsm_state2387 == ap_CS_fsm))) begin + res_9_V_we0 = 1'b1; + end else begin + res_9_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state1058 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_15_fu_80260_p1; + end else if ((ap_ST_fsm_state1022 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_11_fu_79952_p1; + end else if ((ap_ST_fsm_state914 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_8_fu_79448_p1; + end else if ((ap_ST_fsm_state878 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_3_fu_79140_p1; + end else if ((ap_ST_fsm_state768 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_13_fu_78579_p1; + end else if ((ap_ST_fsm_state732 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_9_fu_78261_p1; + end else if ((ap_ST_fsm_state624 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_5_fu_77756_p1; + end else if ((ap_ST_fsm_state588 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_1_fu_77438_p1; + end else if ((ap_ST_fsm_state477 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_14_fu_76799_p1; + end else if ((ap_ST_fsm_state441 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_10_fu_76491_p1; + end else if ((ap_ST_fsm_state333 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_6_fu_75985_p1; + end else if ((ap_ST_fsm_state297 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_2_fu_75676_p1; + end else if ((ap_ST_fsm_state187 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_12_fu_75119_p1; + end else if ((ap_ST_fsm_state151 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_7_fu_74801_p1; + end else if ((ap_ST_fsm_state43 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_4_fu_74295_p1; + end else if ((ap_ST_fsm_state7 == ap_CS_fsm)) begin + w2_V_address0 = zext_ln232_fu_73976_p1; + end else begin + w2_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) | (ap_ST_fsm_state914 == ap_CS_fsm) | (ap_ST_fsm_state878 == ap_CS_fsm) | (ap_ST_fsm_state768 == ap_CS_fsm) | (ap_ST_fsm_state732 == ap_CS_fsm) | (ap_ST_fsm_state624 == ap_CS_fsm) | (ap_ST_fsm_state588 == ap_CS_fsm) | (ap_ST_fsm_state477 == ap_CS_fsm) | (ap_ST_fsm_state43 == ap_CS_fsm) | (ap_ST_fsm_state441 == ap_CS_fsm) | (ap_ST_fsm_state333 == ap_CS_fsm) | (ap_ST_fsm_state297 == ap_CS_fsm) | (ap_ST_fsm_state187 == ap_CS_fsm) | (ap_ST_fsm_state151 == ap_CS_fsm) | (ap_ST_fsm_state1058 == ap_CS_fsm) | (ap_ST_fsm_state1022 == ap_CS_fsm))) begin + w2_V_ce0 = 1'b1; + end else begin + w2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((ap_ST_fsm_state2 == ap_CS_fsm) & (icmp_ln199_fu_73684_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state1165; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln201_fu_73698_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state584; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + ap_ST_fsm_state4 : begin + if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln203_fu_73758_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state294; + end else begin + ap_NS_fsm = ap_ST_fsm_state5; + end + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (or_ln223_3_fu_73970_p2 == 1'd0) & (or_ln223_reg_90189 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state8; + end else begin + ap_NS_fsm = ap_ST_fsm_state44; + end + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state18; + end + ap_ST_fsm_state18 : begin + ap_NS_fsm = ap_ST_fsm_state19; + end + ap_ST_fsm_state19 : begin + ap_NS_fsm = ap_ST_fsm_state20; + end + ap_ST_fsm_state20 : begin + ap_NS_fsm = ap_ST_fsm_state21; + end + ap_ST_fsm_state21 : begin + ap_NS_fsm = ap_ST_fsm_state22; + end + ap_ST_fsm_state22 : begin + ap_NS_fsm = ap_ST_fsm_state23; + end + ap_ST_fsm_state23 : begin + ap_NS_fsm = ap_ST_fsm_state24; + end + ap_ST_fsm_state24 : begin + ap_NS_fsm = ap_ST_fsm_state25; + end + ap_ST_fsm_state25 : begin + ap_NS_fsm = ap_ST_fsm_state26; + end + ap_ST_fsm_state26 : begin + ap_NS_fsm = ap_ST_fsm_state27; + end + ap_ST_fsm_state27 : begin + ap_NS_fsm = ap_ST_fsm_state28; + end + ap_ST_fsm_state28 : begin + ap_NS_fsm = ap_ST_fsm_state29; + end + ap_ST_fsm_state29 : begin + ap_NS_fsm = ap_ST_fsm_state30; + end + ap_ST_fsm_state30 : begin + ap_NS_fsm = ap_ST_fsm_state31; + end + ap_ST_fsm_state31 : begin + ap_NS_fsm = ap_ST_fsm_state32; + end + ap_ST_fsm_state32 : begin + ap_NS_fsm = ap_ST_fsm_state33; + end + ap_ST_fsm_state33 : begin + ap_NS_fsm = ap_ST_fsm_state34; + end + ap_ST_fsm_state34 : begin + ap_NS_fsm = ap_ST_fsm_state35; + end + ap_ST_fsm_state35 : begin + ap_NS_fsm = ap_ST_fsm_state36; + end + ap_ST_fsm_state36 : begin + ap_NS_fsm = ap_ST_fsm_state37; + end + ap_ST_fsm_state37 : begin + ap_NS_fsm = ap_ST_fsm_state38; + end + ap_ST_fsm_state38 : begin + ap_NS_fsm = ap_ST_fsm_state39; + end + ap_ST_fsm_state39 : begin + ap_NS_fsm = ap_ST_fsm_state40; + end + ap_ST_fsm_state40 : begin + ap_NS_fsm = ap_ST_fsm_state41; + end + ap_ST_fsm_state41 : begin + ap_NS_fsm = ap_ST_fsm_state42; + end + ap_ST_fsm_state42 : begin + ap_NS_fsm = ap_ST_fsm_state43; + end + ap_ST_fsm_state43 : begin + if (((ap_ST_fsm_state43 == ap_CS_fsm) & (icmp_ln206_fu_74326_p2 == 1'd1) & (icmp_ln208_fu_74233_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else if (((ap_ST_fsm_state43 == ap_CS_fsm) & (icmp_ln208_fu_74233_p2 == 1'd1) & (icmp_ln206_fu_74326_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state150; + end else if (((ap_ST_fsm_state43 == ap_CS_fsm) & (or_ln223_9_fu_74283_p2 == 1'd0) & (icmp_ln208_fu_74233_p2 == 1'd0) & (or_ln223_reg_90189 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state79; + end else begin + ap_NS_fsm = ap_ST_fsm_state115; + end + end + ap_ST_fsm_state44 : begin + ap_NS_fsm = ap_ST_fsm_state45; + end + ap_ST_fsm_state45 : begin + ap_NS_fsm = ap_ST_fsm_state46; + end + ap_ST_fsm_state46 : begin + ap_NS_fsm = ap_ST_fsm_state47; + end + ap_ST_fsm_state47 : begin + ap_NS_fsm = ap_ST_fsm_state48; + end + ap_ST_fsm_state48 : begin + ap_NS_fsm = ap_ST_fsm_state49; + end + ap_ST_fsm_state49 : begin + ap_NS_fsm = ap_ST_fsm_state50; + end + ap_ST_fsm_state50 : begin + ap_NS_fsm = ap_ST_fsm_state51; + end + ap_ST_fsm_state51 : begin + ap_NS_fsm = ap_ST_fsm_state52; + end + ap_ST_fsm_state52 : begin + ap_NS_fsm = ap_ST_fsm_state53; + end + ap_ST_fsm_state53 : begin + ap_NS_fsm = ap_ST_fsm_state54; + end + ap_ST_fsm_state54 : begin + ap_NS_fsm = ap_ST_fsm_state55; + end + ap_ST_fsm_state55 : begin + ap_NS_fsm = ap_ST_fsm_state56; + end + ap_ST_fsm_state56 : begin + ap_NS_fsm = ap_ST_fsm_state57; + end + ap_ST_fsm_state57 : begin + ap_NS_fsm = ap_ST_fsm_state58; + end + ap_ST_fsm_state58 : begin + ap_NS_fsm = ap_ST_fsm_state59; + end + ap_ST_fsm_state59 : begin + ap_NS_fsm = ap_ST_fsm_state60; + end + ap_ST_fsm_state60 : begin + ap_NS_fsm = ap_ST_fsm_state61; + end + ap_ST_fsm_state61 : begin + ap_NS_fsm = ap_ST_fsm_state62; + end + ap_ST_fsm_state62 : begin + ap_NS_fsm = ap_ST_fsm_state63; + end + ap_ST_fsm_state63 : begin + ap_NS_fsm = ap_ST_fsm_state64; + end + ap_ST_fsm_state64 : begin + ap_NS_fsm = ap_ST_fsm_state65; + end + ap_ST_fsm_state65 : begin + ap_NS_fsm = ap_ST_fsm_state66; + end + ap_ST_fsm_state66 : begin + ap_NS_fsm = ap_ST_fsm_state67; + end + ap_ST_fsm_state67 : begin + ap_NS_fsm = ap_ST_fsm_state68; + end + ap_ST_fsm_state68 : begin + ap_NS_fsm = ap_ST_fsm_state69; + end + ap_ST_fsm_state69 : begin + ap_NS_fsm = ap_ST_fsm_state70; + end + ap_ST_fsm_state70 : begin + ap_NS_fsm = ap_ST_fsm_state71; + end + ap_ST_fsm_state71 : begin + ap_NS_fsm = ap_ST_fsm_state72; + end + ap_ST_fsm_state72 : begin + ap_NS_fsm = ap_ST_fsm_state73; + end + ap_ST_fsm_state73 : begin + ap_NS_fsm = ap_ST_fsm_state74; + end + ap_ST_fsm_state74 : begin + ap_NS_fsm = ap_ST_fsm_state75; + end + ap_ST_fsm_state75 : begin + ap_NS_fsm = ap_ST_fsm_state76; + end + ap_ST_fsm_state76 : begin + ap_NS_fsm = ap_ST_fsm_state77; + end + ap_ST_fsm_state77 : begin + ap_NS_fsm = ap_ST_fsm_state78; + end + ap_ST_fsm_state78 : begin + ap_NS_fsm = ap_ST_fsm_state43; + end + ap_ST_fsm_state79 : begin + ap_NS_fsm = ap_ST_fsm_state80; + end + ap_ST_fsm_state80 : begin + ap_NS_fsm = ap_ST_fsm_state81; + end + ap_ST_fsm_state81 : begin + ap_NS_fsm = ap_ST_fsm_state82; + end + ap_ST_fsm_state82 : begin + ap_NS_fsm = ap_ST_fsm_state83; + end + ap_ST_fsm_state83 : begin + ap_NS_fsm = ap_ST_fsm_state84; + end + ap_ST_fsm_state84 : begin + ap_NS_fsm = ap_ST_fsm_state85; + end + ap_ST_fsm_state85 : begin + ap_NS_fsm = ap_ST_fsm_state86; + end + ap_ST_fsm_state86 : begin + ap_NS_fsm = ap_ST_fsm_state87; + end + ap_ST_fsm_state87 : begin + ap_NS_fsm = ap_ST_fsm_state88; + end + ap_ST_fsm_state88 : begin + ap_NS_fsm = ap_ST_fsm_state89; + end + ap_ST_fsm_state89 : begin + ap_NS_fsm = ap_ST_fsm_state90; + end + ap_ST_fsm_state90 : begin + ap_NS_fsm = ap_ST_fsm_state91; + end + ap_ST_fsm_state91 : begin + ap_NS_fsm = ap_ST_fsm_state92; + end + ap_ST_fsm_state92 : begin + ap_NS_fsm = ap_ST_fsm_state93; + end + ap_ST_fsm_state93 : begin + ap_NS_fsm = ap_ST_fsm_state94; + end + ap_ST_fsm_state94 : begin + ap_NS_fsm = ap_ST_fsm_state95; + end + ap_ST_fsm_state95 : begin + ap_NS_fsm = ap_ST_fsm_state96; + end + ap_ST_fsm_state96 : begin + ap_NS_fsm = ap_ST_fsm_state97; + end + ap_ST_fsm_state97 : begin + ap_NS_fsm = ap_ST_fsm_state98; + end + ap_ST_fsm_state98 : begin + ap_NS_fsm = ap_ST_fsm_state99; + end + ap_ST_fsm_state99 : begin + ap_NS_fsm = ap_ST_fsm_state100; + end + ap_ST_fsm_state100 : begin + ap_NS_fsm = ap_ST_fsm_state101; + end + ap_ST_fsm_state101 : begin + ap_NS_fsm = ap_ST_fsm_state102; + end + ap_ST_fsm_state102 : begin + ap_NS_fsm = ap_ST_fsm_state103; + end + ap_ST_fsm_state103 : begin + ap_NS_fsm = ap_ST_fsm_state104; + end + ap_ST_fsm_state104 : begin + ap_NS_fsm = ap_ST_fsm_state105; + end + ap_ST_fsm_state105 : begin + ap_NS_fsm = ap_ST_fsm_state106; + end + ap_ST_fsm_state106 : begin + ap_NS_fsm = ap_ST_fsm_state107; + end + ap_ST_fsm_state107 : begin + ap_NS_fsm = ap_ST_fsm_state108; + end + ap_ST_fsm_state108 : begin + ap_NS_fsm = ap_ST_fsm_state109; + end + ap_ST_fsm_state109 : begin + ap_NS_fsm = ap_ST_fsm_state110; + end + ap_ST_fsm_state110 : begin + ap_NS_fsm = ap_ST_fsm_state111; + end + ap_ST_fsm_state111 : begin + ap_NS_fsm = ap_ST_fsm_state112; + end + ap_ST_fsm_state112 : begin + ap_NS_fsm = ap_ST_fsm_state113; + end + ap_ST_fsm_state113 : begin + ap_NS_fsm = ap_ST_fsm_state114; + end + ap_ST_fsm_state114 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state115 : begin + ap_NS_fsm = ap_ST_fsm_state116; + end + ap_ST_fsm_state116 : begin + ap_NS_fsm = ap_ST_fsm_state117; + end + ap_ST_fsm_state117 : begin + ap_NS_fsm = ap_ST_fsm_state118; + end + ap_ST_fsm_state118 : begin + ap_NS_fsm = ap_ST_fsm_state119; + end + ap_ST_fsm_state119 : begin + ap_NS_fsm = ap_ST_fsm_state120; + end + ap_ST_fsm_state120 : begin + ap_NS_fsm = ap_ST_fsm_state121; + end + ap_ST_fsm_state121 : begin + ap_NS_fsm = ap_ST_fsm_state122; + end + ap_ST_fsm_state122 : begin + ap_NS_fsm = ap_ST_fsm_state123; + end + ap_ST_fsm_state123 : begin + ap_NS_fsm = ap_ST_fsm_state124; + end + ap_ST_fsm_state124 : begin + ap_NS_fsm = ap_ST_fsm_state125; + end + ap_ST_fsm_state125 : begin + ap_NS_fsm = ap_ST_fsm_state126; + end + ap_ST_fsm_state126 : begin + ap_NS_fsm = ap_ST_fsm_state127; + end + ap_ST_fsm_state127 : begin + ap_NS_fsm = ap_ST_fsm_state128; + end + ap_ST_fsm_state128 : begin + ap_NS_fsm = ap_ST_fsm_state129; + end + ap_ST_fsm_state129 : begin + ap_NS_fsm = ap_ST_fsm_state130; + end + ap_ST_fsm_state130 : begin + ap_NS_fsm = ap_ST_fsm_state131; + end + ap_ST_fsm_state131 : begin + ap_NS_fsm = ap_ST_fsm_state132; + end + ap_ST_fsm_state132 : begin + ap_NS_fsm = ap_ST_fsm_state133; + end + ap_ST_fsm_state133 : begin + ap_NS_fsm = ap_ST_fsm_state134; + end + ap_ST_fsm_state134 : begin + ap_NS_fsm = ap_ST_fsm_state135; + end + ap_ST_fsm_state135 : begin + ap_NS_fsm = ap_ST_fsm_state136; + end + ap_ST_fsm_state136 : begin + ap_NS_fsm = ap_ST_fsm_state137; + end + ap_ST_fsm_state137 : begin + ap_NS_fsm = ap_ST_fsm_state138; + end + ap_ST_fsm_state138 : begin + ap_NS_fsm = ap_ST_fsm_state139; + end + ap_ST_fsm_state139 : begin + ap_NS_fsm = ap_ST_fsm_state140; + end + ap_ST_fsm_state140 : begin + ap_NS_fsm = ap_ST_fsm_state141; + end + ap_ST_fsm_state141 : begin + ap_NS_fsm = ap_ST_fsm_state142; + end + ap_ST_fsm_state142 : begin + ap_NS_fsm = ap_ST_fsm_state143; + end + ap_ST_fsm_state143 : begin + ap_NS_fsm = ap_ST_fsm_state144; + end + ap_ST_fsm_state144 : begin + ap_NS_fsm = ap_ST_fsm_state145; + end + ap_ST_fsm_state145 : begin + ap_NS_fsm = ap_ST_fsm_state146; + end + ap_ST_fsm_state146 : begin + ap_NS_fsm = ap_ST_fsm_state147; + end + ap_ST_fsm_state147 : begin + ap_NS_fsm = ap_ST_fsm_state148; + end + ap_ST_fsm_state148 : begin + ap_NS_fsm = ap_ST_fsm_state149; + end + ap_ST_fsm_state149 : begin + ap_NS_fsm = ap_ST_fsm_state114; + end + ap_ST_fsm_state150 : begin + ap_NS_fsm = ap_ST_fsm_state151; + end + ap_ST_fsm_state151 : begin + if (((or_ln223_14_fu_74795_p2 == 1'd0) & (or_ln223_8_reg_90312 == 1'd0) & (ap_ST_fsm_state151 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state152; + end else begin + ap_NS_fsm = ap_ST_fsm_state188; + end + end + ap_ST_fsm_state152 : begin + ap_NS_fsm = ap_ST_fsm_state153; + end + ap_ST_fsm_state153 : begin + ap_NS_fsm = ap_ST_fsm_state154; + end + ap_ST_fsm_state154 : begin + ap_NS_fsm = ap_ST_fsm_state155; + end + ap_ST_fsm_state155 : begin + ap_NS_fsm = ap_ST_fsm_state156; + end + ap_ST_fsm_state156 : begin + ap_NS_fsm = ap_ST_fsm_state157; + end + ap_ST_fsm_state157 : begin + ap_NS_fsm = ap_ST_fsm_state158; + end + ap_ST_fsm_state158 : begin + ap_NS_fsm = ap_ST_fsm_state159; + end + ap_ST_fsm_state159 : begin + ap_NS_fsm = ap_ST_fsm_state160; + end + ap_ST_fsm_state160 : begin + ap_NS_fsm = ap_ST_fsm_state161; + end + ap_ST_fsm_state161 : begin + ap_NS_fsm = ap_ST_fsm_state162; + end + ap_ST_fsm_state162 : begin + ap_NS_fsm = ap_ST_fsm_state163; + end + ap_ST_fsm_state163 : begin + ap_NS_fsm = ap_ST_fsm_state164; + end + ap_ST_fsm_state164 : begin + ap_NS_fsm = ap_ST_fsm_state165; + end + ap_ST_fsm_state165 : begin + ap_NS_fsm = ap_ST_fsm_state166; + end + ap_ST_fsm_state166 : begin + ap_NS_fsm = ap_ST_fsm_state167; + end + ap_ST_fsm_state167 : begin + ap_NS_fsm = ap_ST_fsm_state168; + end + ap_ST_fsm_state168 : begin + ap_NS_fsm = ap_ST_fsm_state169; + end + ap_ST_fsm_state169 : begin + ap_NS_fsm = ap_ST_fsm_state170; + end + ap_ST_fsm_state170 : begin + ap_NS_fsm = ap_ST_fsm_state171; + end + ap_ST_fsm_state171 : begin + ap_NS_fsm = ap_ST_fsm_state172; + end + ap_ST_fsm_state172 : begin + ap_NS_fsm = ap_ST_fsm_state173; + end + ap_ST_fsm_state173 : begin + ap_NS_fsm = ap_ST_fsm_state174; + end + ap_ST_fsm_state174 : begin + ap_NS_fsm = ap_ST_fsm_state175; + end + ap_ST_fsm_state175 : begin + ap_NS_fsm = ap_ST_fsm_state176; + end + ap_ST_fsm_state176 : begin + ap_NS_fsm = ap_ST_fsm_state177; + end + ap_ST_fsm_state177 : begin + ap_NS_fsm = ap_ST_fsm_state178; + end + ap_ST_fsm_state178 : begin + ap_NS_fsm = ap_ST_fsm_state179; + end + ap_ST_fsm_state179 : begin + ap_NS_fsm = ap_ST_fsm_state180; + end + ap_ST_fsm_state180 : begin + ap_NS_fsm = ap_ST_fsm_state181; + end + ap_ST_fsm_state181 : begin + ap_NS_fsm = ap_ST_fsm_state182; + end + ap_ST_fsm_state182 : begin + ap_NS_fsm = ap_ST_fsm_state183; + end + ap_ST_fsm_state183 : begin + ap_NS_fsm = ap_ST_fsm_state184; + end + ap_ST_fsm_state184 : begin + ap_NS_fsm = ap_ST_fsm_state185; + end + ap_ST_fsm_state185 : begin + ap_NS_fsm = ap_ST_fsm_state186; + end + ap_ST_fsm_state186 : begin + ap_NS_fsm = ap_ST_fsm_state187; + end + ap_ST_fsm_state187 : begin + if (((icmp_ln208_4_fu_75057_p2 == 1'd1) & (ap_ST_fsm_state187 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state5; + end else if (((or_ln223_20_fu_75107_p2 == 1'd0) & (icmp_ln208_4_fu_75057_p2 == 1'd0) & (or_ln223_8_reg_90312 == 1'd0) & (ap_ST_fsm_state187 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state223; + end else begin + ap_NS_fsm = ap_ST_fsm_state259; + end + end + ap_ST_fsm_state188 : begin + ap_NS_fsm = ap_ST_fsm_state189; + end + ap_ST_fsm_state189 : begin + ap_NS_fsm = ap_ST_fsm_state190; + end + ap_ST_fsm_state190 : begin + ap_NS_fsm = ap_ST_fsm_state191; + end + ap_ST_fsm_state191 : begin + ap_NS_fsm = ap_ST_fsm_state192; + end + ap_ST_fsm_state192 : begin + ap_NS_fsm = ap_ST_fsm_state193; + end + ap_ST_fsm_state193 : begin + ap_NS_fsm = ap_ST_fsm_state194; + end + ap_ST_fsm_state194 : begin + ap_NS_fsm = ap_ST_fsm_state195; + end + ap_ST_fsm_state195 : begin + ap_NS_fsm = ap_ST_fsm_state196; + end + ap_ST_fsm_state196 : begin + ap_NS_fsm = ap_ST_fsm_state197; + end + ap_ST_fsm_state197 : begin + ap_NS_fsm = ap_ST_fsm_state198; + end + ap_ST_fsm_state198 : begin + ap_NS_fsm = ap_ST_fsm_state199; + end + ap_ST_fsm_state199 : begin + ap_NS_fsm = ap_ST_fsm_state200; + end + ap_ST_fsm_state200 : begin + ap_NS_fsm = ap_ST_fsm_state201; + end + ap_ST_fsm_state201 : begin + ap_NS_fsm = ap_ST_fsm_state202; + end + ap_ST_fsm_state202 : begin + ap_NS_fsm = ap_ST_fsm_state203; + end + ap_ST_fsm_state203 : begin + ap_NS_fsm = ap_ST_fsm_state204; + end + ap_ST_fsm_state204 : begin + ap_NS_fsm = ap_ST_fsm_state205; + end + ap_ST_fsm_state205 : begin + ap_NS_fsm = ap_ST_fsm_state206; + end + ap_ST_fsm_state206 : begin + ap_NS_fsm = ap_ST_fsm_state207; + end + ap_ST_fsm_state207 : begin + ap_NS_fsm = ap_ST_fsm_state208; + end + ap_ST_fsm_state208 : begin + ap_NS_fsm = ap_ST_fsm_state209; + end + ap_ST_fsm_state209 : begin + ap_NS_fsm = ap_ST_fsm_state210; + end + ap_ST_fsm_state210 : begin + ap_NS_fsm = ap_ST_fsm_state211; + end + ap_ST_fsm_state211 : begin + ap_NS_fsm = ap_ST_fsm_state212; + end + ap_ST_fsm_state212 : begin + ap_NS_fsm = ap_ST_fsm_state213; + end + ap_ST_fsm_state213 : begin + ap_NS_fsm = ap_ST_fsm_state214; + end + ap_ST_fsm_state214 : begin + ap_NS_fsm = ap_ST_fsm_state215; + end + ap_ST_fsm_state215 : begin + ap_NS_fsm = ap_ST_fsm_state216; + end + ap_ST_fsm_state216 : begin + ap_NS_fsm = ap_ST_fsm_state217; + end + ap_ST_fsm_state217 : begin + ap_NS_fsm = ap_ST_fsm_state218; + end + ap_ST_fsm_state218 : begin + ap_NS_fsm = ap_ST_fsm_state219; + end + ap_ST_fsm_state219 : begin + ap_NS_fsm = ap_ST_fsm_state220; + end + ap_ST_fsm_state220 : begin + ap_NS_fsm = ap_ST_fsm_state221; + end + ap_ST_fsm_state221 : begin + ap_NS_fsm = ap_ST_fsm_state222; + end + ap_ST_fsm_state222 : begin + ap_NS_fsm = ap_ST_fsm_state187; + end + ap_ST_fsm_state223 : begin + ap_NS_fsm = ap_ST_fsm_state224; + end + ap_ST_fsm_state224 : begin + ap_NS_fsm = ap_ST_fsm_state225; + end + ap_ST_fsm_state225 : begin + ap_NS_fsm = ap_ST_fsm_state226; + end + ap_ST_fsm_state226 : begin + ap_NS_fsm = ap_ST_fsm_state227; + end + ap_ST_fsm_state227 : begin + ap_NS_fsm = ap_ST_fsm_state228; + end + ap_ST_fsm_state228 : begin + ap_NS_fsm = ap_ST_fsm_state229; + end + ap_ST_fsm_state229 : begin + ap_NS_fsm = ap_ST_fsm_state230; + end + ap_ST_fsm_state230 : begin + ap_NS_fsm = ap_ST_fsm_state231; + end + ap_ST_fsm_state231 : begin + ap_NS_fsm = ap_ST_fsm_state232; + end + ap_ST_fsm_state232 : begin + ap_NS_fsm = ap_ST_fsm_state233; + end + ap_ST_fsm_state233 : begin + ap_NS_fsm = ap_ST_fsm_state234; + end + ap_ST_fsm_state234 : begin + ap_NS_fsm = ap_ST_fsm_state235; + end + ap_ST_fsm_state235 : begin + ap_NS_fsm = ap_ST_fsm_state236; + end + ap_ST_fsm_state236 : begin + ap_NS_fsm = ap_ST_fsm_state237; + end + ap_ST_fsm_state237 : begin + ap_NS_fsm = ap_ST_fsm_state238; + end + ap_ST_fsm_state238 : begin + ap_NS_fsm = ap_ST_fsm_state239; + end + ap_ST_fsm_state239 : begin + ap_NS_fsm = ap_ST_fsm_state240; + end + ap_ST_fsm_state240 : begin + ap_NS_fsm = ap_ST_fsm_state241; + end + ap_ST_fsm_state241 : begin + ap_NS_fsm = ap_ST_fsm_state242; + end + ap_ST_fsm_state242 : begin + ap_NS_fsm = ap_ST_fsm_state243; + end + ap_ST_fsm_state243 : begin + ap_NS_fsm = ap_ST_fsm_state244; + end + ap_ST_fsm_state244 : begin + ap_NS_fsm = ap_ST_fsm_state245; + end + ap_ST_fsm_state245 : begin + ap_NS_fsm = ap_ST_fsm_state246; + end + ap_ST_fsm_state246 : begin + ap_NS_fsm = ap_ST_fsm_state247; + end + ap_ST_fsm_state247 : begin + ap_NS_fsm = ap_ST_fsm_state248; + end + ap_ST_fsm_state248 : begin + ap_NS_fsm = ap_ST_fsm_state249; + end + ap_ST_fsm_state249 : begin + ap_NS_fsm = ap_ST_fsm_state250; + end + ap_ST_fsm_state250 : begin + ap_NS_fsm = ap_ST_fsm_state251; + end + ap_ST_fsm_state251 : begin + ap_NS_fsm = ap_ST_fsm_state252; + end + ap_ST_fsm_state252 : begin + ap_NS_fsm = ap_ST_fsm_state253; + end + ap_ST_fsm_state253 : begin + ap_NS_fsm = ap_ST_fsm_state254; + end + ap_ST_fsm_state254 : begin + ap_NS_fsm = ap_ST_fsm_state255; + end + ap_ST_fsm_state255 : begin + ap_NS_fsm = ap_ST_fsm_state256; + end + ap_ST_fsm_state256 : begin + ap_NS_fsm = ap_ST_fsm_state257; + end + ap_ST_fsm_state257 : begin + ap_NS_fsm = ap_ST_fsm_state258; + end + ap_ST_fsm_state258 : begin + ap_NS_fsm = ap_ST_fsm_state151; + end + ap_ST_fsm_state259 : begin + ap_NS_fsm = ap_ST_fsm_state260; + end + ap_ST_fsm_state260 : begin + ap_NS_fsm = ap_ST_fsm_state261; + end + ap_ST_fsm_state261 : begin + ap_NS_fsm = ap_ST_fsm_state262; + end + ap_ST_fsm_state262 : begin + ap_NS_fsm = ap_ST_fsm_state263; + end + ap_ST_fsm_state263 : begin + ap_NS_fsm = ap_ST_fsm_state264; + end + ap_ST_fsm_state264 : begin + ap_NS_fsm = ap_ST_fsm_state265; + end + ap_ST_fsm_state265 : begin + ap_NS_fsm = ap_ST_fsm_state266; + end + ap_ST_fsm_state266 : begin + ap_NS_fsm = ap_ST_fsm_state267; + end + ap_ST_fsm_state267 : begin + ap_NS_fsm = ap_ST_fsm_state268; + end + ap_ST_fsm_state268 : begin + ap_NS_fsm = ap_ST_fsm_state269; + end + ap_ST_fsm_state269 : begin + ap_NS_fsm = ap_ST_fsm_state270; + end + ap_ST_fsm_state270 : begin + ap_NS_fsm = ap_ST_fsm_state271; + end + ap_ST_fsm_state271 : begin + ap_NS_fsm = ap_ST_fsm_state272; + end + ap_ST_fsm_state272 : begin + ap_NS_fsm = ap_ST_fsm_state273; + end + ap_ST_fsm_state273 : begin + ap_NS_fsm = ap_ST_fsm_state274; + end + ap_ST_fsm_state274 : begin + ap_NS_fsm = ap_ST_fsm_state275; + end + ap_ST_fsm_state275 : begin + ap_NS_fsm = ap_ST_fsm_state276; + end + ap_ST_fsm_state276 : begin + ap_NS_fsm = ap_ST_fsm_state277; + end + ap_ST_fsm_state277 : begin + ap_NS_fsm = ap_ST_fsm_state278; + end + ap_ST_fsm_state278 : begin + ap_NS_fsm = ap_ST_fsm_state279; + end + ap_ST_fsm_state279 : begin + ap_NS_fsm = ap_ST_fsm_state280; + end + ap_ST_fsm_state280 : begin + ap_NS_fsm = ap_ST_fsm_state281; + end + ap_ST_fsm_state281 : begin + ap_NS_fsm = ap_ST_fsm_state282; + end + ap_ST_fsm_state282 : begin + ap_NS_fsm = ap_ST_fsm_state283; + end + ap_ST_fsm_state283 : begin + ap_NS_fsm = ap_ST_fsm_state284; + end + ap_ST_fsm_state284 : begin + ap_NS_fsm = ap_ST_fsm_state285; + end + ap_ST_fsm_state285 : begin + ap_NS_fsm = ap_ST_fsm_state286; + end + ap_ST_fsm_state286 : begin + ap_NS_fsm = ap_ST_fsm_state287; + end + ap_ST_fsm_state287 : begin + ap_NS_fsm = ap_ST_fsm_state288; + end + ap_ST_fsm_state288 : begin + ap_NS_fsm = ap_ST_fsm_state289; + end + ap_ST_fsm_state289 : begin + ap_NS_fsm = ap_ST_fsm_state290; + end + ap_ST_fsm_state290 : begin + ap_NS_fsm = ap_ST_fsm_state291; + end + ap_ST_fsm_state291 : begin + ap_NS_fsm = ap_ST_fsm_state292; + end + ap_ST_fsm_state292 : begin + ap_NS_fsm = ap_ST_fsm_state293; + end + ap_ST_fsm_state293 : begin + ap_NS_fsm = ap_ST_fsm_state258; + end + ap_ST_fsm_state294 : begin + if (((icmp_ln203_2_fu_75486_p2 == 1'd1) & (ap_ST_fsm_state294 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3; + end else begin + ap_NS_fsm = ap_ST_fsm_state295; + end + end + ap_ST_fsm_state295 : begin + ap_NS_fsm = ap_ST_fsm_state296; + end + ap_ST_fsm_state296 : begin + ap_NS_fsm = ap_ST_fsm_state297; + end + ap_ST_fsm_state297 : begin + if (((or_ln223_6_fu_75670_p2 == 1'd0) & (or_ln223_2_reg_90649 == 1'd0) & (ap_ST_fsm_state297 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state298; + end else begin + ap_NS_fsm = ap_ST_fsm_state334; + end + end + ap_ST_fsm_state298 : begin + ap_NS_fsm = ap_ST_fsm_state299; + end + ap_ST_fsm_state299 : begin + ap_NS_fsm = ap_ST_fsm_state300; + end + ap_ST_fsm_state300 : begin + ap_NS_fsm = ap_ST_fsm_state301; + end + ap_ST_fsm_state301 : begin + ap_NS_fsm = ap_ST_fsm_state302; + end + ap_ST_fsm_state302 : begin + ap_NS_fsm = ap_ST_fsm_state303; + end + ap_ST_fsm_state303 : begin + ap_NS_fsm = ap_ST_fsm_state304; + end + ap_ST_fsm_state304 : begin + ap_NS_fsm = ap_ST_fsm_state305; + end + ap_ST_fsm_state305 : begin + ap_NS_fsm = ap_ST_fsm_state306; + end + ap_ST_fsm_state306 : begin + ap_NS_fsm = ap_ST_fsm_state307; + end + ap_ST_fsm_state307 : begin + ap_NS_fsm = ap_ST_fsm_state308; + end + ap_ST_fsm_state308 : begin + ap_NS_fsm = ap_ST_fsm_state309; + end + ap_ST_fsm_state309 : begin + ap_NS_fsm = ap_ST_fsm_state310; + end + ap_ST_fsm_state310 : begin + ap_NS_fsm = ap_ST_fsm_state311; + end + ap_ST_fsm_state311 : begin + ap_NS_fsm = ap_ST_fsm_state312; + end + ap_ST_fsm_state312 : begin + ap_NS_fsm = ap_ST_fsm_state313; + end + ap_ST_fsm_state313 : begin + ap_NS_fsm = ap_ST_fsm_state314; + end + ap_ST_fsm_state314 : begin + ap_NS_fsm = ap_ST_fsm_state315; + end + ap_ST_fsm_state315 : begin + ap_NS_fsm = ap_ST_fsm_state316; + end + ap_ST_fsm_state316 : begin + ap_NS_fsm = ap_ST_fsm_state317; + end + ap_ST_fsm_state317 : begin + ap_NS_fsm = ap_ST_fsm_state318; + end + ap_ST_fsm_state318 : begin + ap_NS_fsm = ap_ST_fsm_state319; + end + ap_ST_fsm_state319 : begin + ap_NS_fsm = ap_ST_fsm_state320; + end + ap_ST_fsm_state320 : begin + ap_NS_fsm = ap_ST_fsm_state321; + end + ap_ST_fsm_state321 : begin + ap_NS_fsm = ap_ST_fsm_state322; + end + ap_ST_fsm_state322 : begin + ap_NS_fsm = ap_ST_fsm_state323; + end + ap_ST_fsm_state323 : begin + ap_NS_fsm = ap_ST_fsm_state324; + end + ap_ST_fsm_state324 : begin + ap_NS_fsm = ap_ST_fsm_state325; + end + ap_ST_fsm_state325 : begin + ap_NS_fsm = ap_ST_fsm_state326; + end + ap_ST_fsm_state326 : begin + ap_NS_fsm = ap_ST_fsm_state327; + end + ap_ST_fsm_state327 : begin + ap_NS_fsm = ap_ST_fsm_state328; + end + ap_ST_fsm_state328 : begin + ap_NS_fsm = ap_ST_fsm_state329; + end + ap_ST_fsm_state329 : begin + ap_NS_fsm = ap_ST_fsm_state330; + end + ap_ST_fsm_state330 : begin + ap_NS_fsm = ap_ST_fsm_state331; + end + ap_ST_fsm_state331 : begin + ap_NS_fsm = ap_ST_fsm_state332; + end + ap_ST_fsm_state332 : begin + ap_NS_fsm = ap_ST_fsm_state333; + end + ap_ST_fsm_state333 : begin + if (((ap_ST_fsm_state333 == ap_CS_fsm) & (icmp_ln206_2_fu_76016_p2 == 1'd1) & (icmp_ln208_2_fu_75923_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state294; + end else if (((ap_ST_fsm_state333 == ap_CS_fsm) & (icmp_ln208_2_fu_75923_p2 == 1'd1) & (icmp_ln206_2_fu_76016_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state440; + end else if (((ap_ST_fsm_state333 == ap_CS_fsm) & (or_ln223_13_fu_75973_p2 == 1'd0) & (icmp_ln208_2_fu_75923_p2 == 1'd0) & (or_ln223_2_reg_90649 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state369; + end else begin + ap_NS_fsm = ap_ST_fsm_state405; + end + end + ap_ST_fsm_state334 : begin + ap_NS_fsm = ap_ST_fsm_state335; + end + ap_ST_fsm_state335 : begin + ap_NS_fsm = ap_ST_fsm_state336; + end + ap_ST_fsm_state336 : begin + ap_NS_fsm = ap_ST_fsm_state337; + end + ap_ST_fsm_state337 : begin + ap_NS_fsm = ap_ST_fsm_state338; + end + ap_ST_fsm_state338 : begin + ap_NS_fsm = ap_ST_fsm_state339; + end + ap_ST_fsm_state339 : begin + ap_NS_fsm = ap_ST_fsm_state340; + end + ap_ST_fsm_state340 : begin + ap_NS_fsm = ap_ST_fsm_state341; + end + ap_ST_fsm_state341 : begin + ap_NS_fsm = ap_ST_fsm_state342; + end + ap_ST_fsm_state342 : begin + ap_NS_fsm = ap_ST_fsm_state343; + end + ap_ST_fsm_state343 : begin + ap_NS_fsm = ap_ST_fsm_state344; + end + ap_ST_fsm_state344 : begin + ap_NS_fsm = ap_ST_fsm_state345; + end + ap_ST_fsm_state345 : begin + ap_NS_fsm = ap_ST_fsm_state346; + end + ap_ST_fsm_state346 : begin + ap_NS_fsm = ap_ST_fsm_state347; + end + ap_ST_fsm_state347 : begin + ap_NS_fsm = ap_ST_fsm_state348; + end + ap_ST_fsm_state348 : begin + ap_NS_fsm = ap_ST_fsm_state349; + end + ap_ST_fsm_state349 : begin + ap_NS_fsm = ap_ST_fsm_state350; + end + ap_ST_fsm_state350 : begin + ap_NS_fsm = ap_ST_fsm_state351; + end + ap_ST_fsm_state351 : begin + ap_NS_fsm = ap_ST_fsm_state352; + end + ap_ST_fsm_state352 : begin + ap_NS_fsm = ap_ST_fsm_state353; + end + ap_ST_fsm_state353 : begin + ap_NS_fsm = ap_ST_fsm_state354; + end + ap_ST_fsm_state354 : begin + ap_NS_fsm = ap_ST_fsm_state355; + end + ap_ST_fsm_state355 : begin + ap_NS_fsm = ap_ST_fsm_state356; + end + ap_ST_fsm_state356 : begin + ap_NS_fsm = ap_ST_fsm_state357; + end + ap_ST_fsm_state357 : begin + ap_NS_fsm = ap_ST_fsm_state358; + end + ap_ST_fsm_state358 : begin + ap_NS_fsm = ap_ST_fsm_state359; + end + ap_ST_fsm_state359 : begin + ap_NS_fsm = ap_ST_fsm_state360; + end + ap_ST_fsm_state360 : begin + ap_NS_fsm = ap_ST_fsm_state361; + end + ap_ST_fsm_state361 : begin + ap_NS_fsm = ap_ST_fsm_state362; + end + ap_ST_fsm_state362 : begin + ap_NS_fsm = ap_ST_fsm_state363; + end + ap_ST_fsm_state363 : begin + ap_NS_fsm = ap_ST_fsm_state364; + end + ap_ST_fsm_state364 : begin + ap_NS_fsm = ap_ST_fsm_state365; + end + ap_ST_fsm_state365 : begin + ap_NS_fsm = ap_ST_fsm_state366; + end + ap_ST_fsm_state366 : begin + ap_NS_fsm = ap_ST_fsm_state367; + end + ap_ST_fsm_state367 : begin + ap_NS_fsm = ap_ST_fsm_state368; + end + ap_ST_fsm_state368 : begin + ap_NS_fsm = ap_ST_fsm_state333; + end + ap_ST_fsm_state369 : begin + ap_NS_fsm = ap_ST_fsm_state370; + end + ap_ST_fsm_state370 : begin + ap_NS_fsm = ap_ST_fsm_state371; + end + ap_ST_fsm_state371 : begin + ap_NS_fsm = ap_ST_fsm_state372; + end + ap_ST_fsm_state372 : begin + ap_NS_fsm = ap_ST_fsm_state373; + end + ap_ST_fsm_state373 : begin + ap_NS_fsm = ap_ST_fsm_state374; + end + ap_ST_fsm_state374 : begin + ap_NS_fsm = ap_ST_fsm_state375; + end + ap_ST_fsm_state375 : begin + ap_NS_fsm = ap_ST_fsm_state376; + end + ap_ST_fsm_state376 : begin + ap_NS_fsm = ap_ST_fsm_state377; + end + ap_ST_fsm_state377 : begin + ap_NS_fsm = ap_ST_fsm_state378; + end + ap_ST_fsm_state378 : begin + ap_NS_fsm = ap_ST_fsm_state379; + end + ap_ST_fsm_state379 : begin + ap_NS_fsm = ap_ST_fsm_state380; + end + ap_ST_fsm_state380 : begin + ap_NS_fsm = ap_ST_fsm_state381; + end + ap_ST_fsm_state381 : begin + ap_NS_fsm = ap_ST_fsm_state382; + end + ap_ST_fsm_state382 : begin + ap_NS_fsm = ap_ST_fsm_state383; + end + ap_ST_fsm_state383 : begin + ap_NS_fsm = ap_ST_fsm_state384; + end + ap_ST_fsm_state384 : begin + ap_NS_fsm = ap_ST_fsm_state385; + end + ap_ST_fsm_state385 : begin + ap_NS_fsm = ap_ST_fsm_state386; + end + ap_ST_fsm_state386 : begin + ap_NS_fsm = ap_ST_fsm_state387; + end + ap_ST_fsm_state387 : begin + ap_NS_fsm = ap_ST_fsm_state388; + end + ap_ST_fsm_state388 : begin + ap_NS_fsm = ap_ST_fsm_state389; + end + ap_ST_fsm_state389 : begin + ap_NS_fsm = ap_ST_fsm_state390; + end + ap_ST_fsm_state390 : begin + ap_NS_fsm = ap_ST_fsm_state391; + end + ap_ST_fsm_state391 : begin + ap_NS_fsm = ap_ST_fsm_state392; + end + ap_ST_fsm_state392 : begin + ap_NS_fsm = ap_ST_fsm_state393; + end + ap_ST_fsm_state393 : begin + ap_NS_fsm = ap_ST_fsm_state394; + end + ap_ST_fsm_state394 : begin + ap_NS_fsm = ap_ST_fsm_state395; + end + ap_ST_fsm_state395 : begin + ap_NS_fsm = ap_ST_fsm_state396; + end + ap_ST_fsm_state396 : begin + ap_NS_fsm = ap_ST_fsm_state397; + end + ap_ST_fsm_state397 : begin + ap_NS_fsm = ap_ST_fsm_state398; + end + ap_ST_fsm_state398 : begin + ap_NS_fsm = ap_ST_fsm_state399; + end + ap_ST_fsm_state399 : begin + ap_NS_fsm = ap_ST_fsm_state400; + end + ap_ST_fsm_state400 : begin + ap_NS_fsm = ap_ST_fsm_state401; + end + ap_ST_fsm_state401 : begin + ap_NS_fsm = ap_ST_fsm_state402; + end + ap_ST_fsm_state402 : begin + ap_NS_fsm = ap_ST_fsm_state403; + end + ap_ST_fsm_state403 : begin + ap_NS_fsm = ap_ST_fsm_state404; + end + ap_ST_fsm_state404 : begin + ap_NS_fsm = ap_ST_fsm_state297; + end + ap_ST_fsm_state405 : begin + ap_NS_fsm = ap_ST_fsm_state406; + end + ap_ST_fsm_state406 : begin + ap_NS_fsm = ap_ST_fsm_state407; + end + ap_ST_fsm_state407 : begin + ap_NS_fsm = ap_ST_fsm_state408; + end + ap_ST_fsm_state408 : begin + ap_NS_fsm = ap_ST_fsm_state409; + end + ap_ST_fsm_state409 : begin + ap_NS_fsm = ap_ST_fsm_state410; + end + ap_ST_fsm_state410 : begin + ap_NS_fsm = ap_ST_fsm_state411; + end + ap_ST_fsm_state411 : begin + ap_NS_fsm = ap_ST_fsm_state412; + end + ap_ST_fsm_state412 : begin + ap_NS_fsm = ap_ST_fsm_state413; + end + ap_ST_fsm_state413 : begin + ap_NS_fsm = ap_ST_fsm_state414; + end + ap_ST_fsm_state414 : begin + ap_NS_fsm = ap_ST_fsm_state415; + end + ap_ST_fsm_state415 : begin + ap_NS_fsm = ap_ST_fsm_state416; + end + ap_ST_fsm_state416 : begin + ap_NS_fsm = ap_ST_fsm_state417; + end + ap_ST_fsm_state417 : begin + ap_NS_fsm = ap_ST_fsm_state418; + end + ap_ST_fsm_state418 : begin + ap_NS_fsm = ap_ST_fsm_state419; + end + ap_ST_fsm_state419 : begin + ap_NS_fsm = ap_ST_fsm_state420; + end + ap_ST_fsm_state420 : begin + ap_NS_fsm = ap_ST_fsm_state421; + end + ap_ST_fsm_state421 : begin + ap_NS_fsm = ap_ST_fsm_state422; + end + ap_ST_fsm_state422 : begin + ap_NS_fsm = ap_ST_fsm_state423; + end + ap_ST_fsm_state423 : begin + ap_NS_fsm = ap_ST_fsm_state424; + end + ap_ST_fsm_state424 : begin + ap_NS_fsm = ap_ST_fsm_state425; + end + ap_ST_fsm_state425 : begin + ap_NS_fsm = ap_ST_fsm_state426; + end + ap_ST_fsm_state426 : begin + ap_NS_fsm = ap_ST_fsm_state427; + end + ap_ST_fsm_state427 : begin + ap_NS_fsm = ap_ST_fsm_state428; + end + ap_ST_fsm_state428 : begin + ap_NS_fsm = ap_ST_fsm_state429; + end + ap_ST_fsm_state429 : begin + ap_NS_fsm = ap_ST_fsm_state430; + end + ap_ST_fsm_state430 : begin + ap_NS_fsm = ap_ST_fsm_state431; + end + ap_ST_fsm_state431 : begin + ap_NS_fsm = ap_ST_fsm_state432; + end + ap_ST_fsm_state432 : begin + ap_NS_fsm = ap_ST_fsm_state433; + end + ap_ST_fsm_state433 : begin + ap_NS_fsm = ap_ST_fsm_state434; + end + ap_ST_fsm_state434 : begin + ap_NS_fsm = ap_ST_fsm_state435; + end + ap_ST_fsm_state435 : begin + ap_NS_fsm = ap_ST_fsm_state436; + end + ap_ST_fsm_state436 : begin + ap_NS_fsm = ap_ST_fsm_state437; + end + ap_ST_fsm_state437 : begin + ap_NS_fsm = ap_ST_fsm_state438; + end + ap_ST_fsm_state438 : begin + ap_NS_fsm = ap_ST_fsm_state439; + end + ap_ST_fsm_state439 : begin + ap_NS_fsm = ap_ST_fsm_state404; + end + ap_ST_fsm_state440 : begin + ap_NS_fsm = ap_ST_fsm_state441; + end + ap_ST_fsm_state441 : begin + if (((ap_ST_fsm_state441 == ap_CS_fsm) & (or_ln223_18_fu_76485_p2 == 1'd0) & (or_ln223_12_reg_90772 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state442; + end else begin + ap_NS_fsm = ap_ST_fsm_state478; + end + end + ap_ST_fsm_state442 : begin + ap_NS_fsm = ap_ST_fsm_state443; + end + ap_ST_fsm_state443 : begin + ap_NS_fsm = ap_ST_fsm_state444; + end + ap_ST_fsm_state444 : begin + ap_NS_fsm = ap_ST_fsm_state445; + end + ap_ST_fsm_state445 : begin + ap_NS_fsm = ap_ST_fsm_state446; + end + ap_ST_fsm_state446 : begin + ap_NS_fsm = ap_ST_fsm_state447; + end + ap_ST_fsm_state447 : begin + ap_NS_fsm = ap_ST_fsm_state448; + end + ap_ST_fsm_state448 : begin + ap_NS_fsm = ap_ST_fsm_state449; + end + ap_ST_fsm_state449 : begin + ap_NS_fsm = ap_ST_fsm_state450; + end + ap_ST_fsm_state450 : begin + ap_NS_fsm = ap_ST_fsm_state451; + end + ap_ST_fsm_state451 : begin + ap_NS_fsm = ap_ST_fsm_state452; + end + ap_ST_fsm_state452 : begin + ap_NS_fsm = ap_ST_fsm_state453; + end + ap_ST_fsm_state453 : begin + ap_NS_fsm = ap_ST_fsm_state454; + end + ap_ST_fsm_state454 : begin + ap_NS_fsm = ap_ST_fsm_state455; + end + ap_ST_fsm_state455 : begin + ap_NS_fsm = ap_ST_fsm_state456; + end + ap_ST_fsm_state456 : begin + ap_NS_fsm = ap_ST_fsm_state457; + end + ap_ST_fsm_state457 : begin + ap_NS_fsm = ap_ST_fsm_state458; + end + ap_ST_fsm_state458 : begin + ap_NS_fsm = ap_ST_fsm_state459; + end + ap_ST_fsm_state459 : begin + ap_NS_fsm = ap_ST_fsm_state460; + end + ap_ST_fsm_state460 : begin + ap_NS_fsm = ap_ST_fsm_state461; + end + ap_ST_fsm_state461 : begin + ap_NS_fsm = ap_ST_fsm_state462; + end + ap_ST_fsm_state462 : begin + ap_NS_fsm = ap_ST_fsm_state463; + end + ap_ST_fsm_state463 : begin + ap_NS_fsm = ap_ST_fsm_state464; + end + ap_ST_fsm_state464 : begin + ap_NS_fsm = ap_ST_fsm_state465; + end + ap_ST_fsm_state465 : begin + ap_NS_fsm = ap_ST_fsm_state466; + end + ap_ST_fsm_state466 : begin + ap_NS_fsm = ap_ST_fsm_state467; + end + ap_ST_fsm_state467 : begin + ap_NS_fsm = ap_ST_fsm_state468; + end + ap_ST_fsm_state468 : begin + ap_NS_fsm = ap_ST_fsm_state469; + end + ap_ST_fsm_state469 : begin + ap_NS_fsm = ap_ST_fsm_state470; + end + ap_ST_fsm_state470 : begin + ap_NS_fsm = ap_ST_fsm_state471; + end + ap_ST_fsm_state471 : begin + ap_NS_fsm = ap_ST_fsm_state472; + end + ap_ST_fsm_state472 : begin + ap_NS_fsm = ap_ST_fsm_state473; + end + ap_ST_fsm_state473 : begin + ap_NS_fsm = ap_ST_fsm_state474; + end + ap_ST_fsm_state474 : begin + ap_NS_fsm = ap_ST_fsm_state475; + end + ap_ST_fsm_state475 : begin + ap_NS_fsm = ap_ST_fsm_state476; + end + ap_ST_fsm_state476 : begin + ap_NS_fsm = ap_ST_fsm_state477; + end + ap_ST_fsm_state477 : begin + if (((ap_ST_fsm_state477 == ap_CS_fsm) & (icmp_ln208_6_fu_76737_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state295; + end else if (((ap_ST_fsm_state477 == ap_CS_fsm) & (or_ln223_22_fu_76787_p2 == 1'd0) & (icmp_ln208_6_fu_76737_p2 == 1'd0) & (or_ln223_12_reg_90772 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state513; + end else begin + ap_NS_fsm = ap_ST_fsm_state549; + end + end + ap_ST_fsm_state478 : begin + ap_NS_fsm = ap_ST_fsm_state479; + end + ap_ST_fsm_state479 : begin + ap_NS_fsm = ap_ST_fsm_state480; + end + ap_ST_fsm_state480 : begin + ap_NS_fsm = ap_ST_fsm_state481; + end + ap_ST_fsm_state481 : begin + ap_NS_fsm = ap_ST_fsm_state482; + end + ap_ST_fsm_state482 : begin + ap_NS_fsm = ap_ST_fsm_state483; + end + ap_ST_fsm_state483 : begin + ap_NS_fsm = ap_ST_fsm_state484; + end + ap_ST_fsm_state484 : begin + ap_NS_fsm = ap_ST_fsm_state485; + end + ap_ST_fsm_state485 : begin + ap_NS_fsm = ap_ST_fsm_state486; + end + ap_ST_fsm_state486 : begin + ap_NS_fsm = ap_ST_fsm_state487; + end + ap_ST_fsm_state487 : begin + ap_NS_fsm = ap_ST_fsm_state488; + end + ap_ST_fsm_state488 : begin + ap_NS_fsm = ap_ST_fsm_state489; + end + ap_ST_fsm_state489 : begin + ap_NS_fsm = ap_ST_fsm_state490; + end + ap_ST_fsm_state490 : begin + ap_NS_fsm = ap_ST_fsm_state491; + end + ap_ST_fsm_state491 : begin + ap_NS_fsm = ap_ST_fsm_state492; + end + ap_ST_fsm_state492 : begin + ap_NS_fsm = ap_ST_fsm_state493; + end + ap_ST_fsm_state493 : begin + ap_NS_fsm = ap_ST_fsm_state494; + end + ap_ST_fsm_state494 : begin + ap_NS_fsm = ap_ST_fsm_state495; + end + ap_ST_fsm_state495 : begin + ap_NS_fsm = ap_ST_fsm_state496; + end + ap_ST_fsm_state496 : begin + ap_NS_fsm = ap_ST_fsm_state497; + end + ap_ST_fsm_state497 : begin + ap_NS_fsm = ap_ST_fsm_state498; + end + ap_ST_fsm_state498 : begin + ap_NS_fsm = ap_ST_fsm_state499; + end + ap_ST_fsm_state499 : begin + ap_NS_fsm = ap_ST_fsm_state500; + end + ap_ST_fsm_state500 : begin + ap_NS_fsm = ap_ST_fsm_state501; + end + ap_ST_fsm_state501 : begin + ap_NS_fsm = ap_ST_fsm_state502; + end + ap_ST_fsm_state502 : begin + ap_NS_fsm = ap_ST_fsm_state503; + end + ap_ST_fsm_state503 : begin + ap_NS_fsm = ap_ST_fsm_state504; + end + ap_ST_fsm_state504 : begin + ap_NS_fsm = ap_ST_fsm_state505; + end + ap_ST_fsm_state505 : begin + ap_NS_fsm = ap_ST_fsm_state506; + end + ap_ST_fsm_state506 : begin + ap_NS_fsm = ap_ST_fsm_state507; + end + ap_ST_fsm_state507 : begin + ap_NS_fsm = ap_ST_fsm_state508; + end + ap_ST_fsm_state508 : begin + ap_NS_fsm = ap_ST_fsm_state509; + end + ap_ST_fsm_state509 : begin + ap_NS_fsm = ap_ST_fsm_state510; + end + ap_ST_fsm_state510 : begin + ap_NS_fsm = ap_ST_fsm_state511; + end + ap_ST_fsm_state511 : begin + ap_NS_fsm = ap_ST_fsm_state512; + end + ap_ST_fsm_state512 : begin + ap_NS_fsm = ap_ST_fsm_state477; + end + ap_ST_fsm_state513 : begin + ap_NS_fsm = ap_ST_fsm_state514; + end + ap_ST_fsm_state514 : begin + ap_NS_fsm = ap_ST_fsm_state515; + end + ap_ST_fsm_state515 : begin + ap_NS_fsm = ap_ST_fsm_state516; + end + ap_ST_fsm_state516 : begin + ap_NS_fsm = ap_ST_fsm_state517; + end + ap_ST_fsm_state517 : begin + ap_NS_fsm = ap_ST_fsm_state518; + end + ap_ST_fsm_state518 : begin + ap_NS_fsm = ap_ST_fsm_state519; + end + ap_ST_fsm_state519 : begin + ap_NS_fsm = ap_ST_fsm_state520; + end + ap_ST_fsm_state520 : begin + ap_NS_fsm = ap_ST_fsm_state521; + end + ap_ST_fsm_state521 : begin + ap_NS_fsm = ap_ST_fsm_state522; + end + ap_ST_fsm_state522 : begin + ap_NS_fsm = ap_ST_fsm_state523; + end + ap_ST_fsm_state523 : begin + ap_NS_fsm = ap_ST_fsm_state524; + end + ap_ST_fsm_state524 : begin + ap_NS_fsm = ap_ST_fsm_state525; + end + ap_ST_fsm_state525 : begin + ap_NS_fsm = ap_ST_fsm_state526; + end + ap_ST_fsm_state526 : begin + ap_NS_fsm = ap_ST_fsm_state527; + end + ap_ST_fsm_state527 : begin + ap_NS_fsm = ap_ST_fsm_state528; + end + ap_ST_fsm_state528 : begin + ap_NS_fsm = ap_ST_fsm_state529; + end + ap_ST_fsm_state529 : begin + ap_NS_fsm = ap_ST_fsm_state530; + end + ap_ST_fsm_state530 : begin + ap_NS_fsm = ap_ST_fsm_state531; + end + ap_ST_fsm_state531 : begin + ap_NS_fsm = ap_ST_fsm_state532; + end + ap_ST_fsm_state532 : begin + ap_NS_fsm = ap_ST_fsm_state533; + end + ap_ST_fsm_state533 : begin + ap_NS_fsm = ap_ST_fsm_state534; + end + ap_ST_fsm_state534 : begin + ap_NS_fsm = ap_ST_fsm_state535; + end + ap_ST_fsm_state535 : begin + ap_NS_fsm = ap_ST_fsm_state536; + end + ap_ST_fsm_state536 : begin + ap_NS_fsm = ap_ST_fsm_state537; + end + ap_ST_fsm_state537 : begin + ap_NS_fsm = ap_ST_fsm_state538; + end + ap_ST_fsm_state538 : begin + ap_NS_fsm = ap_ST_fsm_state539; + end + ap_ST_fsm_state539 : begin + ap_NS_fsm = ap_ST_fsm_state540; + end + ap_ST_fsm_state540 : begin + ap_NS_fsm = ap_ST_fsm_state541; + end + ap_ST_fsm_state541 : begin + ap_NS_fsm = ap_ST_fsm_state542; + end + ap_ST_fsm_state542 : begin + ap_NS_fsm = ap_ST_fsm_state543; + end + ap_ST_fsm_state543 : begin + ap_NS_fsm = ap_ST_fsm_state544; + end + ap_ST_fsm_state544 : begin + ap_NS_fsm = ap_ST_fsm_state545; + end + ap_ST_fsm_state545 : begin + ap_NS_fsm = ap_ST_fsm_state546; + end + ap_ST_fsm_state546 : begin + ap_NS_fsm = ap_ST_fsm_state547; + end + ap_ST_fsm_state547 : begin + ap_NS_fsm = ap_ST_fsm_state548; + end + ap_ST_fsm_state548 : begin + ap_NS_fsm = ap_ST_fsm_state441; + end + ap_ST_fsm_state549 : begin + ap_NS_fsm = ap_ST_fsm_state550; + end + ap_ST_fsm_state550 : begin + ap_NS_fsm = ap_ST_fsm_state551; + end + ap_ST_fsm_state551 : begin + ap_NS_fsm = ap_ST_fsm_state552; + end + ap_ST_fsm_state552 : begin + ap_NS_fsm = ap_ST_fsm_state553; + end + ap_ST_fsm_state553 : begin + ap_NS_fsm = ap_ST_fsm_state554; + end + ap_ST_fsm_state554 : begin + ap_NS_fsm = ap_ST_fsm_state555; + end + ap_ST_fsm_state555 : begin + ap_NS_fsm = ap_ST_fsm_state556; + end + ap_ST_fsm_state556 : begin + ap_NS_fsm = ap_ST_fsm_state557; + end + ap_ST_fsm_state557 : begin + ap_NS_fsm = ap_ST_fsm_state558; + end + ap_ST_fsm_state558 : begin + ap_NS_fsm = ap_ST_fsm_state559; + end + ap_ST_fsm_state559 : begin + ap_NS_fsm = ap_ST_fsm_state560; + end + ap_ST_fsm_state560 : begin + ap_NS_fsm = ap_ST_fsm_state561; + end + ap_ST_fsm_state561 : begin + ap_NS_fsm = ap_ST_fsm_state562; + end + ap_ST_fsm_state562 : begin + ap_NS_fsm = ap_ST_fsm_state563; + end + ap_ST_fsm_state563 : begin + ap_NS_fsm = ap_ST_fsm_state564; + end + ap_ST_fsm_state564 : begin + ap_NS_fsm = ap_ST_fsm_state565; + end + ap_ST_fsm_state565 : begin + ap_NS_fsm = ap_ST_fsm_state566; + end + ap_ST_fsm_state566 : begin + ap_NS_fsm = ap_ST_fsm_state567; + end + ap_ST_fsm_state567 : begin + ap_NS_fsm = ap_ST_fsm_state568; + end + ap_ST_fsm_state568 : begin + ap_NS_fsm = ap_ST_fsm_state569; + end + ap_ST_fsm_state569 : begin + ap_NS_fsm = ap_ST_fsm_state570; + end + ap_ST_fsm_state570 : begin + ap_NS_fsm = ap_ST_fsm_state571; + end + ap_ST_fsm_state571 : begin + ap_NS_fsm = ap_ST_fsm_state572; + end + ap_ST_fsm_state572 : begin + ap_NS_fsm = ap_ST_fsm_state573; + end + ap_ST_fsm_state573 : begin + ap_NS_fsm = ap_ST_fsm_state574; + end + ap_ST_fsm_state574 : begin + ap_NS_fsm = ap_ST_fsm_state575; + end + ap_ST_fsm_state575 : begin + ap_NS_fsm = ap_ST_fsm_state576; + end + ap_ST_fsm_state576 : begin + ap_NS_fsm = ap_ST_fsm_state577; + end + ap_ST_fsm_state577 : begin + ap_NS_fsm = ap_ST_fsm_state578; + end + ap_ST_fsm_state578 : begin + ap_NS_fsm = ap_ST_fsm_state579; + end + ap_ST_fsm_state579 : begin + ap_NS_fsm = ap_ST_fsm_state580; + end + ap_ST_fsm_state580 : begin + ap_NS_fsm = ap_ST_fsm_state581; + end + ap_ST_fsm_state581 : begin + ap_NS_fsm = ap_ST_fsm_state582; + end + ap_ST_fsm_state582 : begin + ap_NS_fsm = ap_ST_fsm_state583; + end + ap_ST_fsm_state583 : begin + ap_NS_fsm = ap_ST_fsm_state548; + end + ap_ST_fsm_state584 : begin + if (((ap_ST_fsm_state584 == ap_CS_fsm) & (icmp_ln201_1_fu_77164_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state585; + end + end + ap_ST_fsm_state585 : begin + if (((ap_ST_fsm_state585 == ap_CS_fsm) & (icmp_ln203_1_fu_77216_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state875; + end else begin + ap_NS_fsm = ap_ST_fsm_state586; + end + end + ap_ST_fsm_state586 : begin + ap_NS_fsm = ap_ST_fsm_state587; + end + ap_ST_fsm_state587 : begin + ap_NS_fsm = ap_ST_fsm_state588; + end + ap_ST_fsm_state588 : begin + if (((ap_ST_fsm_state588 == ap_CS_fsm) & (or_ln223_5_fu_77432_p2 == 1'd0) & (or_ln223_1_reg_91176 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state589; + end else begin + ap_NS_fsm = ap_ST_fsm_state625; + end + end + ap_ST_fsm_state589 : begin + ap_NS_fsm = ap_ST_fsm_state590; + end + ap_ST_fsm_state590 : begin + ap_NS_fsm = ap_ST_fsm_state591; + end + ap_ST_fsm_state591 : begin + ap_NS_fsm = ap_ST_fsm_state592; + end + ap_ST_fsm_state592 : begin + ap_NS_fsm = ap_ST_fsm_state593; + end + ap_ST_fsm_state593 : begin + ap_NS_fsm = ap_ST_fsm_state594; + end + ap_ST_fsm_state594 : begin + ap_NS_fsm = ap_ST_fsm_state595; + end + ap_ST_fsm_state595 : begin + ap_NS_fsm = ap_ST_fsm_state596; + end + ap_ST_fsm_state596 : begin + ap_NS_fsm = ap_ST_fsm_state597; + end + ap_ST_fsm_state597 : begin + ap_NS_fsm = ap_ST_fsm_state598; + end + ap_ST_fsm_state598 : begin + ap_NS_fsm = ap_ST_fsm_state599; + end + ap_ST_fsm_state599 : begin + ap_NS_fsm = ap_ST_fsm_state600; + end + ap_ST_fsm_state600 : begin + ap_NS_fsm = ap_ST_fsm_state601; + end + ap_ST_fsm_state601 : begin + ap_NS_fsm = ap_ST_fsm_state602; + end + ap_ST_fsm_state602 : begin + ap_NS_fsm = ap_ST_fsm_state603; + end + ap_ST_fsm_state603 : begin + ap_NS_fsm = ap_ST_fsm_state604; + end + ap_ST_fsm_state604 : begin + ap_NS_fsm = ap_ST_fsm_state605; + end + ap_ST_fsm_state605 : begin + ap_NS_fsm = ap_ST_fsm_state606; + end + ap_ST_fsm_state606 : begin + ap_NS_fsm = ap_ST_fsm_state607; + end + ap_ST_fsm_state607 : begin + ap_NS_fsm = ap_ST_fsm_state608; + end + ap_ST_fsm_state608 : begin + ap_NS_fsm = ap_ST_fsm_state609; + end + ap_ST_fsm_state609 : begin + ap_NS_fsm = ap_ST_fsm_state610; + end + ap_ST_fsm_state610 : begin + ap_NS_fsm = ap_ST_fsm_state611; + end + ap_ST_fsm_state611 : begin + ap_NS_fsm = ap_ST_fsm_state612; + end + ap_ST_fsm_state612 : begin + ap_NS_fsm = ap_ST_fsm_state613; + end + ap_ST_fsm_state613 : begin + ap_NS_fsm = ap_ST_fsm_state614; + end + ap_ST_fsm_state614 : begin + ap_NS_fsm = ap_ST_fsm_state615; + end + ap_ST_fsm_state615 : begin + ap_NS_fsm = ap_ST_fsm_state616; + end + ap_ST_fsm_state616 : begin + ap_NS_fsm = ap_ST_fsm_state617; + end + ap_ST_fsm_state617 : begin + ap_NS_fsm = ap_ST_fsm_state618; + end + ap_ST_fsm_state618 : begin + ap_NS_fsm = ap_ST_fsm_state619; + end + ap_ST_fsm_state619 : begin + ap_NS_fsm = ap_ST_fsm_state620; + end + ap_ST_fsm_state620 : begin + ap_NS_fsm = ap_ST_fsm_state621; + end + ap_ST_fsm_state621 : begin + ap_NS_fsm = ap_ST_fsm_state622; + end + ap_ST_fsm_state622 : begin + ap_NS_fsm = ap_ST_fsm_state623; + end + ap_ST_fsm_state623 : begin + ap_NS_fsm = ap_ST_fsm_state624; + end + ap_ST_fsm_state624 : begin + if (((ap_ST_fsm_state624 == ap_CS_fsm) & (icmp_ln206_1_fu_77787_p2 == 1'd1) & (icmp_ln208_1_fu_77694_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state585; + end else if (((ap_ST_fsm_state624 == ap_CS_fsm) & (icmp_ln208_1_fu_77694_p2 == 1'd1) & (icmp_ln206_1_fu_77787_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state731; + end else if (((ap_ST_fsm_state624 == ap_CS_fsm) & (or_ln223_11_fu_77744_p2 == 1'd0) & (icmp_ln208_1_fu_77694_p2 == 1'd0) & (or_ln223_1_reg_91176 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state660; + end else begin + ap_NS_fsm = ap_ST_fsm_state696; + end + end + ap_ST_fsm_state625 : begin + ap_NS_fsm = ap_ST_fsm_state626; + end + ap_ST_fsm_state626 : begin + ap_NS_fsm = ap_ST_fsm_state627; + end + ap_ST_fsm_state627 : begin + ap_NS_fsm = ap_ST_fsm_state628; + end + ap_ST_fsm_state628 : begin + ap_NS_fsm = ap_ST_fsm_state629; + end + ap_ST_fsm_state629 : begin + ap_NS_fsm = ap_ST_fsm_state630; + end + ap_ST_fsm_state630 : begin + ap_NS_fsm = ap_ST_fsm_state631; + end + ap_ST_fsm_state631 : begin + ap_NS_fsm = ap_ST_fsm_state632; + end + ap_ST_fsm_state632 : begin + ap_NS_fsm = ap_ST_fsm_state633; + end + ap_ST_fsm_state633 : begin + ap_NS_fsm = ap_ST_fsm_state634; + end + ap_ST_fsm_state634 : begin + ap_NS_fsm = ap_ST_fsm_state635; + end + ap_ST_fsm_state635 : begin + ap_NS_fsm = ap_ST_fsm_state636; + end + ap_ST_fsm_state636 : begin + ap_NS_fsm = ap_ST_fsm_state637; + end + ap_ST_fsm_state637 : begin + ap_NS_fsm = ap_ST_fsm_state638; + end + ap_ST_fsm_state638 : begin + ap_NS_fsm = ap_ST_fsm_state639; + end + ap_ST_fsm_state639 : begin + ap_NS_fsm = ap_ST_fsm_state640; + end + ap_ST_fsm_state640 : begin + ap_NS_fsm = ap_ST_fsm_state641; + end + ap_ST_fsm_state641 : begin + ap_NS_fsm = ap_ST_fsm_state642; + end + ap_ST_fsm_state642 : begin + ap_NS_fsm = ap_ST_fsm_state643; + end + ap_ST_fsm_state643 : begin + ap_NS_fsm = ap_ST_fsm_state644; + end + ap_ST_fsm_state644 : begin + ap_NS_fsm = ap_ST_fsm_state645; + end + ap_ST_fsm_state645 : begin + ap_NS_fsm = ap_ST_fsm_state646; + end + ap_ST_fsm_state646 : begin + ap_NS_fsm = ap_ST_fsm_state647; + end + ap_ST_fsm_state647 : begin + ap_NS_fsm = ap_ST_fsm_state648; + end + ap_ST_fsm_state648 : begin + ap_NS_fsm = ap_ST_fsm_state649; + end + ap_ST_fsm_state649 : begin + ap_NS_fsm = ap_ST_fsm_state650; + end + ap_ST_fsm_state650 : begin + ap_NS_fsm = ap_ST_fsm_state651; + end + ap_ST_fsm_state651 : begin + ap_NS_fsm = ap_ST_fsm_state652; + end + ap_ST_fsm_state652 : begin + ap_NS_fsm = ap_ST_fsm_state653; + end + ap_ST_fsm_state653 : begin + ap_NS_fsm = ap_ST_fsm_state654; + end + ap_ST_fsm_state654 : begin + ap_NS_fsm = ap_ST_fsm_state655; + end + ap_ST_fsm_state655 : begin + ap_NS_fsm = ap_ST_fsm_state656; + end + ap_ST_fsm_state656 : begin + ap_NS_fsm = ap_ST_fsm_state657; + end + ap_ST_fsm_state657 : begin + ap_NS_fsm = ap_ST_fsm_state658; + end + ap_ST_fsm_state658 : begin + ap_NS_fsm = ap_ST_fsm_state659; + end + ap_ST_fsm_state659 : begin + ap_NS_fsm = ap_ST_fsm_state624; + end + ap_ST_fsm_state660 : begin + ap_NS_fsm = ap_ST_fsm_state661; + end + ap_ST_fsm_state661 : begin + ap_NS_fsm = ap_ST_fsm_state662; + end + ap_ST_fsm_state662 : begin + ap_NS_fsm = ap_ST_fsm_state663; + end + ap_ST_fsm_state663 : begin + ap_NS_fsm = ap_ST_fsm_state664; + end + ap_ST_fsm_state664 : begin + ap_NS_fsm = ap_ST_fsm_state665; + end + ap_ST_fsm_state665 : begin + ap_NS_fsm = ap_ST_fsm_state666; + end + ap_ST_fsm_state666 : begin + ap_NS_fsm = ap_ST_fsm_state667; + end + ap_ST_fsm_state667 : begin + ap_NS_fsm = ap_ST_fsm_state668; + end + ap_ST_fsm_state668 : begin + ap_NS_fsm = ap_ST_fsm_state669; + end + ap_ST_fsm_state669 : begin + ap_NS_fsm = ap_ST_fsm_state670; + end + ap_ST_fsm_state670 : begin + ap_NS_fsm = ap_ST_fsm_state671; + end + ap_ST_fsm_state671 : begin + ap_NS_fsm = ap_ST_fsm_state672; + end + ap_ST_fsm_state672 : begin + ap_NS_fsm = ap_ST_fsm_state673; + end + ap_ST_fsm_state673 : begin + ap_NS_fsm = ap_ST_fsm_state674; + end + ap_ST_fsm_state674 : begin + ap_NS_fsm = ap_ST_fsm_state675; + end + ap_ST_fsm_state675 : begin + ap_NS_fsm = ap_ST_fsm_state676; + end + ap_ST_fsm_state676 : begin + ap_NS_fsm = ap_ST_fsm_state677; + end + ap_ST_fsm_state677 : begin + ap_NS_fsm = ap_ST_fsm_state678; + end + ap_ST_fsm_state678 : begin + ap_NS_fsm = ap_ST_fsm_state679; + end + ap_ST_fsm_state679 : begin + ap_NS_fsm = ap_ST_fsm_state680; + end + ap_ST_fsm_state680 : begin + ap_NS_fsm = ap_ST_fsm_state681; + end + ap_ST_fsm_state681 : begin + ap_NS_fsm = ap_ST_fsm_state682; + end + ap_ST_fsm_state682 : begin + ap_NS_fsm = ap_ST_fsm_state683; + end + ap_ST_fsm_state683 : begin + ap_NS_fsm = ap_ST_fsm_state684; + end + ap_ST_fsm_state684 : begin + ap_NS_fsm = ap_ST_fsm_state685; + end + ap_ST_fsm_state685 : begin + ap_NS_fsm = ap_ST_fsm_state686; + end + ap_ST_fsm_state686 : begin + ap_NS_fsm = ap_ST_fsm_state687; + end + ap_ST_fsm_state687 : begin + ap_NS_fsm = ap_ST_fsm_state688; + end + ap_ST_fsm_state688 : begin + ap_NS_fsm = ap_ST_fsm_state689; + end + ap_ST_fsm_state689 : begin + ap_NS_fsm = ap_ST_fsm_state690; + end + ap_ST_fsm_state690 : begin + ap_NS_fsm = ap_ST_fsm_state691; + end + ap_ST_fsm_state691 : begin + ap_NS_fsm = ap_ST_fsm_state692; + end + ap_ST_fsm_state692 : begin + ap_NS_fsm = ap_ST_fsm_state693; + end + ap_ST_fsm_state693 : begin + ap_NS_fsm = ap_ST_fsm_state694; + end + ap_ST_fsm_state694 : begin + ap_NS_fsm = ap_ST_fsm_state695; + end + ap_ST_fsm_state695 : begin + ap_NS_fsm = ap_ST_fsm_state588; + end + ap_ST_fsm_state696 : begin + ap_NS_fsm = ap_ST_fsm_state697; + end + ap_ST_fsm_state697 : begin + ap_NS_fsm = ap_ST_fsm_state698; + end + ap_ST_fsm_state698 : begin + ap_NS_fsm = ap_ST_fsm_state699; + end + ap_ST_fsm_state699 : begin + ap_NS_fsm = ap_ST_fsm_state700; + end + ap_ST_fsm_state700 : begin + ap_NS_fsm = ap_ST_fsm_state701; + end + ap_ST_fsm_state701 : begin + ap_NS_fsm = ap_ST_fsm_state702; + end + ap_ST_fsm_state702 : begin + ap_NS_fsm = ap_ST_fsm_state703; + end + ap_ST_fsm_state703 : begin + ap_NS_fsm = ap_ST_fsm_state704; + end + ap_ST_fsm_state704 : begin + ap_NS_fsm = ap_ST_fsm_state705; + end + ap_ST_fsm_state705 : begin + ap_NS_fsm = ap_ST_fsm_state706; + end + ap_ST_fsm_state706 : begin + ap_NS_fsm = ap_ST_fsm_state707; + end + ap_ST_fsm_state707 : begin + ap_NS_fsm = ap_ST_fsm_state708; + end + ap_ST_fsm_state708 : begin + ap_NS_fsm = ap_ST_fsm_state709; + end + ap_ST_fsm_state709 : begin + ap_NS_fsm = ap_ST_fsm_state710; + end + ap_ST_fsm_state710 : begin + ap_NS_fsm = ap_ST_fsm_state711; + end + ap_ST_fsm_state711 : begin + ap_NS_fsm = ap_ST_fsm_state712; + end + ap_ST_fsm_state712 : begin + ap_NS_fsm = ap_ST_fsm_state713; + end + ap_ST_fsm_state713 : begin + ap_NS_fsm = ap_ST_fsm_state714; + end + ap_ST_fsm_state714 : begin + ap_NS_fsm = ap_ST_fsm_state715; + end + ap_ST_fsm_state715 : begin + ap_NS_fsm = ap_ST_fsm_state716; + end + ap_ST_fsm_state716 : begin + ap_NS_fsm = ap_ST_fsm_state717; + end + ap_ST_fsm_state717 : begin + ap_NS_fsm = ap_ST_fsm_state718; + end + ap_ST_fsm_state718 : begin + ap_NS_fsm = ap_ST_fsm_state719; + end + ap_ST_fsm_state719 : begin + ap_NS_fsm = ap_ST_fsm_state720; + end + ap_ST_fsm_state720 : begin + ap_NS_fsm = ap_ST_fsm_state721; + end + ap_ST_fsm_state721 : begin + ap_NS_fsm = ap_ST_fsm_state722; + end + ap_ST_fsm_state722 : begin + ap_NS_fsm = ap_ST_fsm_state723; + end + ap_ST_fsm_state723 : begin + ap_NS_fsm = ap_ST_fsm_state724; + end + ap_ST_fsm_state724 : begin + ap_NS_fsm = ap_ST_fsm_state725; + end + ap_ST_fsm_state725 : begin + ap_NS_fsm = ap_ST_fsm_state726; + end + ap_ST_fsm_state726 : begin + ap_NS_fsm = ap_ST_fsm_state727; + end + ap_ST_fsm_state727 : begin + ap_NS_fsm = ap_ST_fsm_state728; + end + ap_ST_fsm_state728 : begin + ap_NS_fsm = ap_ST_fsm_state729; + end + ap_ST_fsm_state729 : begin + ap_NS_fsm = ap_ST_fsm_state730; + end + ap_ST_fsm_state730 : begin + ap_NS_fsm = ap_ST_fsm_state695; + end + ap_ST_fsm_state731 : begin + ap_NS_fsm = ap_ST_fsm_state732; + end + ap_ST_fsm_state732 : begin + if (((ap_ST_fsm_state732 == ap_CS_fsm) & (or_ln223_17_fu_78255_p2 == 1'd0) & (or_ln223_10_reg_91305 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state733; + end else begin + ap_NS_fsm = ap_ST_fsm_state769; + end + end + ap_ST_fsm_state733 : begin + ap_NS_fsm = ap_ST_fsm_state734; + end + ap_ST_fsm_state734 : begin + ap_NS_fsm = ap_ST_fsm_state735; + end + ap_ST_fsm_state735 : begin + ap_NS_fsm = ap_ST_fsm_state736; + end + ap_ST_fsm_state736 : begin + ap_NS_fsm = ap_ST_fsm_state737; + end + ap_ST_fsm_state737 : begin + ap_NS_fsm = ap_ST_fsm_state738; + end + ap_ST_fsm_state738 : begin + ap_NS_fsm = ap_ST_fsm_state739; + end + ap_ST_fsm_state739 : begin + ap_NS_fsm = ap_ST_fsm_state740; + end + ap_ST_fsm_state740 : begin + ap_NS_fsm = ap_ST_fsm_state741; + end + ap_ST_fsm_state741 : begin + ap_NS_fsm = ap_ST_fsm_state742; + end + ap_ST_fsm_state742 : begin + ap_NS_fsm = ap_ST_fsm_state743; + end + ap_ST_fsm_state743 : begin + ap_NS_fsm = ap_ST_fsm_state744; + end + ap_ST_fsm_state744 : begin + ap_NS_fsm = ap_ST_fsm_state745; + end + ap_ST_fsm_state745 : begin + ap_NS_fsm = ap_ST_fsm_state746; + end + ap_ST_fsm_state746 : begin + ap_NS_fsm = ap_ST_fsm_state747; + end + ap_ST_fsm_state747 : begin + ap_NS_fsm = ap_ST_fsm_state748; + end + ap_ST_fsm_state748 : begin + ap_NS_fsm = ap_ST_fsm_state749; + end + ap_ST_fsm_state749 : begin + ap_NS_fsm = ap_ST_fsm_state750; + end + ap_ST_fsm_state750 : begin + ap_NS_fsm = ap_ST_fsm_state751; + end + ap_ST_fsm_state751 : begin + ap_NS_fsm = ap_ST_fsm_state752; + end + ap_ST_fsm_state752 : begin + ap_NS_fsm = ap_ST_fsm_state753; + end + ap_ST_fsm_state753 : begin + ap_NS_fsm = ap_ST_fsm_state754; + end + ap_ST_fsm_state754 : begin + ap_NS_fsm = ap_ST_fsm_state755; + end + ap_ST_fsm_state755 : begin + ap_NS_fsm = ap_ST_fsm_state756; + end + ap_ST_fsm_state756 : begin + ap_NS_fsm = ap_ST_fsm_state757; + end + ap_ST_fsm_state757 : begin + ap_NS_fsm = ap_ST_fsm_state758; + end + ap_ST_fsm_state758 : begin + ap_NS_fsm = ap_ST_fsm_state759; + end + ap_ST_fsm_state759 : begin + ap_NS_fsm = ap_ST_fsm_state760; + end + ap_ST_fsm_state760 : begin + ap_NS_fsm = ap_ST_fsm_state761; + end + ap_ST_fsm_state761 : begin + ap_NS_fsm = ap_ST_fsm_state762; + end + ap_ST_fsm_state762 : begin + ap_NS_fsm = ap_ST_fsm_state763; + end + ap_ST_fsm_state763 : begin + ap_NS_fsm = ap_ST_fsm_state764; + end + ap_ST_fsm_state764 : begin + ap_NS_fsm = ap_ST_fsm_state765; + end + ap_ST_fsm_state765 : begin + ap_NS_fsm = ap_ST_fsm_state766; + end + ap_ST_fsm_state766 : begin + ap_NS_fsm = ap_ST_fsm_state767; + end + ap_ST_fsm_state767 : begin + ap_NS_fsm = ap_ST_fsm_state768; + end + ap_ST_fsm_state768 : begin + if (((ap_ST_fsm_state768 == ap_CS_fsm) & (icmp_ln208_5_fu_78517_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state586; + end else if (((ap_ST_fsm_state768 == ap_CS_fsm) & (or_ln223_21_fu_78567_p2 == 1'd0) & (icmp_ln208_5_fu_78517_p2 == 1'd0) & (or_ln223_10_reg_91305 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state804; + end else begin + ap_NS_fsm = ap_ST_fsm_state840; + end + end + ap_ST_fsm_state769 : begin + ap_NS_fsm = ap_ST_fsm_state770; + end + ap_ST_fsm_state770 : begin + ap_NS_fsm = ap_ST_fsm_state771; + end + ap_ST_fsm_state771 : begin + ap_NS_fsm = ap_ST_fsm_state772; + end + ap_ST_fsm_state772 : begin + ap_NS_fsm = ap_ST_fsm_state773; + end + ap_ST_fsm_state773 : begin + ap_NS_fsm = ap_ST_fsm_state774; + end + ap_ST_fsm_state774 : begin + ap_NS_fsm = ap_ST_fsm_state775; + end + ap_ST_fsm_state775 : begin + ap_NS_fsm = ap_ST_fsm_state776; + end + ap_ST_fsm_state776 : begin + ap_NS_fsm = ap_ST_fsm_state777; + end + ap_ST_fsm_state777 : begin + ap_NS_fsm = ap_ST_fsm_state778; + end + ap_ST_fsm_state778 : begin + ap_NS_fsm = ap_ST_fsm_state779; + end + ap_ST_fsm_state779 : begin + ap_NS_fsm = ap_ST_fsm_state780; + end + ap_ST_fsm_state780 : begin + ap_NS_fsm = ap_ST_fsm_state781; + end + ap_ST_fsm_state781 : begin + ap_NS_fsm = ap_ST_fsm_state782; + end + ap_ST_fsm_state782 : begin + ap_NS_fsm = ap_ST_fsm_state783; + end + ap_ST_fsm_state783 : begin + ap_NS_fsm = ap_ST_fsm_state784; + end + ap_ST_fsm_state784 : begin + ap_NS_fsm = ap_ST_fsm_state785; + end + ap_ST_fsm_state785 : begin + ap_NS_fsm = ap_ST_fsm_state786; + end + ap_ST_fsm_state786 : begin + ap_NS_fsm = ap_ST_fsm_state787; + end + ap_ST_fsm_state787 : begin + ap_NS_fsm = ap_ST_fsm_state788; + end + ap_ST_fsm_state788 : begin + ap_NS_fsm = ap_ST_fsm_state789; + end + ap_ST_fsm_state789 : begin + ap_NS_fsm = ap_ST_fsm_state790; + end + ap_ST_fsm_state790 : begin + ap_NS_fsm = ap_ST_fsm_state791; + end + ap_ST_fsm_state791 : begin + ap_NS_fsm = ap_ST_fsm_state792; + end + ap_ST_fsm_state792 : begin + ap_NS_fsm = ap_ST_fsm_state793; + end + ap_ST_fsm_state793 : begin + ap_NS_fsm = ap_ST_fsm_state794; + end + ap_ST_fsm_state794 : begin + ap_NS_fsm = ap_ST_fsm_state795; + end + ap_ST_fsm_state795 : begin + ap_NS_fsm = ap_ST_fsm_state796; + end + ap_ST_fsm_state796 : begin + ap_NS_fsm = ap_ST_fsm_state797; + end + ap_ST_fsm_state797 : begin + ap_NS_fsm = ap_ST_fsm_state798; + end + ap_ST_fsm_state798 : begin + ap_NS_fsm = ap_ST_fsm_state799; + end + ap_ST_fsm_state799 : begin + ap_NS_fsm = ap_ST_fsm_state800; + end + ap_ST_fsm_state800 : begin + ap_NS_fsm = ap_ST_fsm_state801; + end + ap_ST_fsm_state801 : begin + ap_NS_fsm = ap_ST_fsm_state802; + end + ap_ST_fsm_state802 : begin + ap_NS_fsm = ap_ST_fsm_state803; + end + ap_ST_fsm_state803 : begin + ap_NS_fsm = ap_ST_fsm_state768; + end + ap_ST_fsm_state804 : begin + ap_NS_fsm = ap_ST_fsm_state805; + end + ap_ST_fsm_state805 : begin + ap_NS_fsm = ap_ST_fsm_state806; + end + ap_ST_fsm_state806 : begin + ap_NS_fsm = ap_ST_fsm_state807; + end + ap_ST_fsm_state807 : begin + ap_NS_fsm = ap_ST_fsm_state808; + end + ap_ST_fsm_state808 : begin + ap_NS_fsm = ap_ST_fsm_state809; + end + ap_ST_fsm_state809 : begin + ap_NS_fsm = ap_ST_fsm_state810; + end + ap_ST_fsm_state810 : begin + ap_NS_fsm = ap_ST_fsm_state811; + end + ap_ST_fsm_state811 : begin + ap_NS_fsm = ap_ST_fsm_state812; + end + ap_ST_fsm_state812 : begin + ap_NS_fsm = ap_ST_fsm_state813; + end + ap_ST_fsm_state813 : begin + ap_NS_fsm = ap_ST_fsm_state814; + end + ap_ST_fsm_state814 : begin + ap_NS_fsm = ap_ST_fsm_state815; + end + ap_ST_fsm_state815 : begin + ap_NS_fsm = ap_ST_fsm_state816; + end + ap_ST_fsm_state816 : begin + ap_NS_fsm = ap_ST_fsm_state817; + end + ap_ST_fsm_state817 : begin + ap_NS_fsm = ap_ST_fsm_state818; + end + ap_ST_fsm_state818 : begin + ap_NS_fsm = ap_ST_fsm_state819; + end + ap_ST_fsm_state819 : begin + ap_NS_fsm = ap_ST_fsm_state820; + end + ap_ST_fsm_state820 : begin + ap_NS_fsm = ap_ST_fsm_state821; + end + ap_ST_fsm_state821 : begin + ap_NS_fsm = ap_ST_fsm_state822; + end + ap_ST_fsm_state822 : begin + ap_NS_fsm = ap_ST_fsm_state823; + end + ap_ST_fsm_state823 : begin + ap_NS_fsm = ap_ST_fsm_state824; + end + ap_ST_fsm_state824 : begin + ap_NS_fsm = ap_ST_fsm_state825; + end + ap_ST_fsm_state825 : begin + ap_NS_fsm = ap_ST_fsm_state826; + end + ap_ST_fsm_state826 : begin + ap_NS_fsm = ap_ST_fsm_state827; + end + ap_ST_fsm_state827 : begin + ap_NS_fsm = ap_ST_fsm_state828; + end + ap_ST_fsm_state828 : begin + ap_NS_fsm = ap_ST_fsm_state829; + end + ap_ST_fsm_state829 : begin + ap_NS_fsm = ap_ST_fsm_state830; + end + ap_ST_fsm_state830 : begin + ap_NS_fsm = ap_ST_fsm_state831; + end + ap_ST_fsm_state831 : begin + ap_NS_fsm = ap_ST_fsm_state832; + end + ap_ST_fsm_state832 : begin + ap_NS_fsm = ap_ST_fsm_state833; + end + ap_ST_fsm_state833 : begin + ap_NS_fsm = ap_ST_fsm_state834; + end + ap_ST_fsm_state834 : begin + ap_NS_fsm = ap_ST_fsm_state835; + end + ap_ST_fsm_state835 : begin + ap_NS_fsm = ap_ST_fsm_state836; + end + ap_ST_fsm_state836 : begin + ap_NS_fsm = ap_ST_fsm_state837; + end + ap_ST_fsm_state837 : begin + ap_NS_fsm = ap_ST_fsm_state838; + end + ap_ST_fsm_state838 : begin + ap_NS_fsm = ap_ST_fsm_state839; + end + ap_ST_fsm_state839 : begin + ap_NS_fsm = ap_ST_fsm_state732; + end + ap_ST_fsm_state840 : begin + ap_NS_fsm = ap_ST_fsm_state841; + end + ap_ST_fsm_state841 : begin + ap_NS_fsm = ap_ST_fsm_state842; + end + ap_ST_fsm_state842 : begin + ap_NS_fsm = ap_ST_fsm_state843; + end + ap_ST_fsm_state843 : begin + ap_NS_fsm = ap_ST_fsm_state844; + end + ap_ST_fsm_state844 : begin + ap_NS_fsm = ap_ST_fsm_state845; + end + ap_ST_fsm_state845 : begin + ap_NS_fsm = ap_ST_fsm_state846; + end + ap_ST_fsm_state846 : begin + ap_NS_fsm = ap_ST_fsm_state847; + end + ap_ST_fsm_state847 : begin + ap_NS_fsm = ap_ST_fsm_state848; + end + ap_ST_fsm_state848 : begin + ap_NS_fsm = ap_ST_fsm_state849; + end + ap_ST_fsm_state849 : begin + ap_NS_fsm = ap_ST_fsm_state850; + end + ap_ST_fsm_state850 : begin + ap_NS_fsm = ap_ST_fsm_state851; + end + ap_ST_fsm_state851 : begin + ap_NS_fsm = ap_ST_fsm_state852; + end + ap_ST_fsm_state852 : begin + ap_NS_fsm = ap_ST_fsm_state853; + end + ap_ST_fsm_state853 : begin + ap_NS_fsm = ap_ST_fsm_state854; + end + ap_ST_fsm_state854 : begin + ap_NS_fsm = ap_ST_fsm_state855; + end + ap_ST_fsm_state855 : begin + ap_NS_fsm = ap_ST_fsm_state856; + end + ap_ST_fsm_state856 : begin + ap_NS_fsm = ap_ST_fsm_state857; + end + ap_ST_fsm_state857 : begin + ap_NS_fsm = ap_ST_fsm_state858; + end + ap_ST_fsm_state858 : begin + ap_NS_fsm = ap_ST_fsm_state859; + end + ap_ST_fsm_state859 : begin + ap_NS_fsm = ap_ST_fsm_state860; + end + ap_ST_fsm_state860 : begin + ap_NS_fsm = ap_ST_fsm_state861; + end + ap_ST_fsm_state861 : begin + ap_NS_fsm = ap_ST_fsm_state862; + end + ap_ST_fsm_state862 : begin + ap_NS_fsm = ap_ST_fsm_state863; + end + ap_ST_fsm_state863 : begin + ap_NS_fsm = ap_ST_fsm_state864; + end + ap_ST_fsm_state864 : begin + ap_NS_fsm = ap_ST_fsm_state865; + end + ap_ST_fsm_state865 : begin + ap_NS_fsm = ap_ST_fsm_state866; + end + ap_ST_fsm_state866 : begin + ap_NS_fsm = ap_ST_fsm_state867; + end + ap_ST_fsm_state867 : begin + ap_NS_fsm = ap_ST_fsm_state868; + end + ap_ST_fsm_state868 : begin + ap_NS_fsm = ap_ST_fsm_state869; + end + ap_ST_fsm_state869 : begin + ap_NS_fsm = ap_ST_fsm_state870; + end + ap_ST_fsm_state870 : begin + ap_NS_fsm = ap_ST_fsm_state871; + end + ap_ST_fsm_state871 : begin + ap_NS_fsm = ap_ST_fsm_state872; + end + ap_ST_fsm_state872 : begin + ap_NS_fsm = ap_ST_fsm_state873; + end + ap_ST_fsm_state873 : begin + ap_NS_fsm = ap_ST_fsm_state874; + end + ap_ST_fsm_state874 : begin + ap_NS_fsm = ap_ST_fsm_state839; + end + ap_ST_fsm_state875 : begin + if (((ap_ST_fsm_state875 == ap_CS_fsm) & (icmp_ln203_3_fu_78946_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state584; + end else begin + ap_NS_fsm = ap_ST_fsm_state876; + end + end + ap_ST_fsm_state876 : begin + ap_NS_fsm = ap_ST_fsm_state877; + end + ap_ST_fsm_state877 : begin + ap_NS_fsm = ap_ST_fsm_state878; + end + ap_ST_fsm_state878 : begin + if (((ap_ST_fsm_state878 == ap_CS_fsm) & (or_ln223_7_fu_79134_p2 == 1'd0) & (or_ln223_4_reg_91642 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state879; + end else begin + ap_NS_fsm = ap_ST_fsm_state915; + end + end + ap_ST_fsm_state879 : begin + ap_NS_fsm = ap_ST_fsm_state880; + end + ap_ST_fsm_state880 : begin + ap_NS_fsm = ap_ST_fsm_state881; + end + ap_ST_fsm_state881 : begin + ap_NS_fsm = ap_ST_fsm_state882; + end + ap_ST_fsm_state882 : begin + ap_NS_fsm = ap_ST_fsm_state883; + end + ap_ST_fsm_state883 : begin + ap_NS_fsm = ap_ST_fsm_state884; + end + ap_ST_fsm_state884 : begin + ap_NS_fsm = ap_ST_fsm_state885; + end + ap_ST_fsm_state885 : begin + ap_NS_fsm = ap_ST_fsm_state886; + end + ap_ST_fsm_state886 : begin + ap_NS_fsm = ap_ST_fsm_state887; + end + ap_ST_fsm_state887 : begin + ap_NS_fsm = ap_ST_fsm_state888; + end + ap_ST_fsm_state888 : begin + ap_NS_fsm = ap_ST_fsm_state889; + end + ap_ST_fsm_state889 : begin + ap_NS_fsm = ap_ST_fsm_state890; + end + ap_ST_fsm_state890 : begin + ap_NS_fsm = ap_ST_fsm_state891; + end + ap_ST_fsm_state891 : begin + ap_NS_fsm = ap_ST_fsm_state892; + end + ap_ST_fsm_state892 : begin + ap_NS_fsm = ap_ST_fsm_state893; + end + ap_ST_fsm_state893 : begin + ap_NS_fsm = ap_ST_fsm_state894; + end + ap_ST_fsm_state894 : begin + ap_NS_fsm = ap_ST_fsm_state895; + end + ap_ST_fsm_state895 : begin + ap_NS_fsm = ap_ST_fsm_state896; + end + ap_ST_fsm_state896 : begin + ap_NS_fsm = ap_ST_fsm_state897; + end + ap_ST_fsm_state897 : begin + ap_NS_fsm = ap_ST_fsm_state898; + end + ap_ST_fsm_state898 : begin + ap_NS_fsm = ap_ST_fsm_state899; + end + ap_ST_fsm_state899 : begin + ap_NS_fsm = ap_ST_fsm_state900; + end + ap_ST_fsm_state900 : begin + ap_NS_fsm = ap_ST_fsm_state901; + end + ap_ST_fsm_state901 : begin + ap_NS_fsm = ap_ST_fsm_state902; + end + ap_ST_fsm_state902 : begin + ap_NS_fsm = ap_ST_fsm_state903; + end + ap_ST_fsm_state903 : begin + ap_NS_fsm = ap_ST_fsm_state904; + end + ap_ST_fsm_state904 : begin + ap_NS_fsm = ap_ST_fsm_state905; + end + ap_ST_fsm_state905 : begin + ap_NS_fsm = ap_ST_fsm_state906; + end + ap_ST_fsm_state906 : begin + ap_NS_fsm = ap_ST_fsm_state907; + end + ap_ST_fsm_state907 : begin + ap_NS_fsm = ap_ST_fsm_state908; + end + ap_ST_fsm_state908 : begin + ap_NS_fsm = ap_ST_fsm_state909; + end + ap_ST_fsm_state909 : begin + ap_NS_fsm = ap_ST_fsm_state910; + end + ap_ST_fsm_state910 : begin + ap_NS_fsm = ap_ST_fsm_state911; + end + ap_ST_fsm_state911 : begin + ap_NS_fsm = ap_ST_fsm_state912; + end + ap_ST_fsm_state912 : begin + ap_NS_fsm = ap_ST_fsm_state913; + end + ap_ST_fsm_state913 : begin + ap_NS_fsm = ap_ST_fsm_state914; + end + ap_ST_fsm_state914 : begin + if (((ap_ST_fsm_state914 == ap_CS_fsm) & (icmp_ln206_3_fu_79499_p2 == 1'd1) & (icmp_ln208_3_fu_79386_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state875; + end else if (((ap_ST_fsm_state914 == ap_CS_fsm) & (icmp_ln208_3_fu_79386_p2 == 1'd1) & (icmp_ln206_3_fu_79499_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state1021; + end else if (((ap_ST_fsm_state914 == ap_CS_fsm) & (or_ln223_16_fu_79436_p2 == 1'd0) & (icmp_ln208_3_fu_79386_p2 == 1'd0) & (or_ln223_4_reg_91642 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state950; + end else begin + ap_NS_fsm = ap_ST_fsm_state986; + end + end + ap_ST_fsm_state915 : begin + ap_NS_fsm = ap_ST_fsm_state916; + end + ap_ST_fsm_state916 : begin + ap_NS_fsm = ap_ST_fsm_state917; + end + ap_ST_fsm_state917 : begin + ap_NS_fsm = ap_ST_fsm_state918; + end + ap_ST_fsm_state918 : begin + ap_NS_fsm = ap_ST_fsm_state919; + end + ap_ST_fsm_state919 : begin + ap_NS_fsm = ap_ST_fsm_state920; + end + ap_ST_fsm_state920 : begin + ap_NS_fsm = ap_ST_fsm_state921; + end + ap_ST_fsm_state921 : begin + ap_NS_fsm = ap_ST_fsm_state922; + end + ap_ST_fsm_state922 : begin + ap_NS_fsm = ap_ST_fsm_state923; + end + ap_ST_fsm_state923 : begin + ap_NS_fsm = ap_ST_fsm_state924; + end + ap_ST_fsm_state924 : begin + ap_NS_fsm = ap_ST_fsm_state925; + end + ap_ST_fsm_state925 : begin + ap_NS_fsm = ap_ST_fsm_state926; + end + ap_ST_fsm_state926 : begin + ap_NS_fsm = ap_ST_fsm_state927; + end + ap_ST_fsm_state927 : begin + ap_NS_fsm = ap_ST_fsm_state928; + end + ap_ST_fsm_state928 : begin + ap_NS_fsm = ap_ST_fsm_state929; + end + ap_ST_fsm_state929 : begin + ap_NS_fsm = ap_ST_fsm_state930; + end + ap_ST_fsm_state930 : begin + ap_NS_fsm = ap_ST_fsm_state931; + end + ap_ST_fsm_state931 : begin + ap_NS_fsm = ap_ST_fsm_state932; + end + ap_ST_fsm_state932 : begin + ap_NS_fsm = ap_ST_fsm_state933; + end + ap_ST_fsm_state933 : begin + ap_NS_fsm = ap_ST_fsm_state934; + end + ap_ST_fsm_state934 : begin + ap_NS_fsm = ap_ST_fsm_state935; + end + ap_ST_fsm_state935 : begin + ap_NS_fsm = ap_ST_fsm_state936; + end + ap_ST_fsm_state936 : begin + ap_NS_fsm = ap_ST_fsm_state937; + end + ap_ST_fsm_state937 : begin + ap_NS_fsm = ap_ST_fsm_state938; + end + ap_ST_fsm_state938 : begin + ap_NS_fsm = ap_ST_fsm_state939; + end + ap_ST_fsm_state939 : begin + ap_NS_fsm = ap_ST_fsm_state940; + end + ap_ST_fsm_state940 : begin + ap_NS_fsm = ap_ST_fsm_state941; + end + ap_ST_fsm_state941 : begin + ap_NS_fsm = ap_ST_fsm_state942; + end + ap_ST_fsm_state942 : begin + ap_NS_fsm = ap_ST_fsm_state943; + end + ap_ST_fsm_state943 : begin + ap_NS_fsm = ap_ST_fsm_state944; + end + ap_ST_fsm_state944 : begin + ap_NS_fsm = ap_ST_fsm_state945; + end + ap_ST_fsm_state945 : begin + ap_NS_fsm = ap_ST_fsm_state946; + end + ap_ST_fsm_state946 : begin + ap_NS_fsm = ap_ST_fsm_state947; + end + ap_ST_fsm_state947 : begin + ap_NS_fsm = ap_ST_fsm_state948; + end + ap_ST_fsm_state948 : begin + ap_NS_fsm = ap_ST_fsm_state949; + end + ap_ST_fsm_state949 : begin + ap_NS_fsm = ap_ST_fsm_state914; + end + ap_ST_fsm_state950 : begin + ap_NS_fsm = ap_ST_fsm_state951; + end + ap_ST_fsm_state951 : begin + ap_NS_fsm = ap_ST_fsm_state952; + end + ap_ST_fsm_state952 : begin + ap_NS_fsm = ap_ST_fsm_state953; + end + ap_ST_fsm_state953 : begin + ap_NS_fsm = ap_ST_fsm_state954; + end + ap_ST_fsm_state954 : begin + ap_NS_fsm = ap_ST_fsm_state955; + end + ap_ST_fsm_state955 : begin + ap_NS_fsm = ap_ST_fsm_state956; + end + ap_ST_fsm_state956 : begin + ap_NS_fsm = ap_ST_fsm_state957; + end + ap_ST_fsm_state957 : begin + ap_NS_fsm = ap_ST_fsm_state958; + end + ap_ST_fsm_state958 : begin + ap_NS_fsm = ap_ST_fsm_state959; + end + ap_ST_fsm_state959 : begin + ap_NS_fsm = ap_ST_fsm_state960; + end + ap_ST_fsm_state960 : begin + ap_NS_fsm = ap_ST_fsm_state961; + end + ap_ST_fsm_state961 : begin + ap_NS_fsm = ap_ST_fsm_state962; + end + ap_ST_fsm_state962 : begin + ap_NS_fsm = ap_ST_fsm_state963; + end + ap_ST_fsm_state963 : begin + ap_NS_fsm = ap_ST_fsm_state964; + end + ap_ST_fsm_state964 : begin + ap_NS_fsm = ap_ST_fsm_state965; + end + ap_ST_fsm_state965 : begin + ap_NS_fsm = ap_ST_fsm_state966; + end + ap_ST_fsm_state966 : begin + ap_NS_fsm = ap_ST_fsm_state967; + end + ap_ST_fsm_state967 : begin + ap_NS_fsm = ap_ST_fsm_state968; + end + ap_ST_fsm_state968 : begin + ap_NS_fsm = ap_ST_fsm_state969; + end + ap_ST_fsm_state969 : begin + ap_NS_fsm = ap_ST_fsm_state970; + end + ap_ST_fsm_state970 : begin + ap_NS_fsm = ap_ST_fsm_state971; + end + ap_ST_fsm_state971 : begin + ap_NS_fsm = ap_ST_fsm_state972; + end + ap_ST_fsm_state972 : begin + ap_NS_fsm = ap_ST_fsm_state973; + end + ap_ST_fsm_state973 : begin + ap_NS_fsm = ap_ST_fsm_state974; + end + ap_ST_fsm_state974 : begin + ap_NS_fsm = ap_ST_fsm_state975; + end + ap_ST_fsm_state975 : begin + ap_NS_fsm = ap_ST_fsm_state976; + end + ap_ST_fsm_state976 : begin + ap_NS_fsm = ap_ST_fsm_state977; + end + ap_ST_fsm_state977 : begin + ap_NS_fsm = ap_ST_fsm_state978; + end + ap_ST_fsm_state978 : begin + ap_NS_fsm = ap_ST_fsm_state979; + end + ap_ST_fsm_state979 : begin + ap_NS_fsm = ap_ST_fsm_state980; + end + ap_ST_fsm_state980 : begin + ap_NS_fsm = ap_ST_fsm_state981; + end + ap_ST_fsm_state981 : begin + ap_NS_fsm = ap_ST_fsm_state982; + end + ap_ST_fsm_state982 : begin + ap_NS_fsm = ap_ST_fsm_state983; + end + ap_ST_fsm_state983 : begin + ap_NS_fsm = ap_ST_fsm_state984; + end + ap_ST_fsm_state984 : begin + ap_NS_fsm = ap_ST_fsm_state985; + end + ap_ST_fsm_state985 : begin + ap_NS_fsm = ap_ST_fsm_state878; + end + ap_ST_fsm_state986 : begin + ap_NS_fsm = ap_ST_fsm_state987; + end + ap_ST_fsm_state987 : begin + ap_NS_fsm = ap_ST_fsm_state988; + end + ap_ST_fsm_state988 : begin + ap_NS_fsm = ap_ST_fsm_state989; + end + ap_ST_fsm_state989 : begin + ap_NS_fsm = ap_ST_fsm_state990; + end + ap_ST_fsm_state990 : begin + ap_NS_fsm = ap_ST_fsm_state991; + end + ap_ST_fsm_state991 : begin + ap_NS_fsm = ap_ST_fsm_state992; + end + ap_ST_fsm_state992 : begin + ap_NS_fsm = ap_ST_fsm_state993; + end + ap_ST_fsm_state993 : begin + ap_NS_fsm = ap_ST_fsm_state994; + end + ap_ST_fsm_state994 : begin + ap_NS_fsm = ap_ST_fsm_state995; + end + ap_ST_fsm_state995 : begin + ap_NS_fsm = ap_ST_fsm_state996; + end + ap_ST_fsm_state996 : begin + ap_NS_fsm = ap_ST_fsm_state997; + end + ap_ST_fsm_state997 : begin + ap_NS_fsm = ap_ST_fsm_state998; + end + ap_ST_fsm_state998 : begin + ap_NS_fsm = ap_ST_fsm_state999; + end + ap_ST_fsm_state999 : begin + ap_NS_fsm = ap_ST_fsm_state1000; + end + ap_ST_fsm_state1000 : begin + ap_NS_fsm = ap_ST_fsm_state1001; + end + ap_ST_fsm_state1001 : begin + ap_NS_fsm = ap_ST_fsm_state1002; + end + ap_ST_fsm_state1002 : begin + ap_NS_fsm = ap_ST_fsm_state1003; + end + ap_ST_fsm_state1003 : begin + ap_NS_fsm = ap_ST_fsm_state1004; + end + ap_ST_fsm_state1004 : begin + ap_NS_fsm = ap_ST_fsm_state1005; + end + ap_ST_fsm_state1005 : begin + ap_NS_fsm = ap_ST_fsm_state1006; + end + ap_ST_fsm_state1006 : begin + ap_NS_fsm = ap_ST_fsm_state1007; + end + ap_ST_fsm_state1007 : begin + ap_NS_fsm = ap_ST_fsm_state1008; + end + ap_ST_fsm_state1008 : begin + ap_NS_fsm = ap_ST_fsm_state1009; + end + ap_ST_fsm_state1009 : begin + ap_NS_fsm = ap_ST_fsm_state1010; + end + ap_ST_fsm_state1010 : begin + ap_NS_fsm = ap_ST_fsm_state1011; + end + ap_ST_fsm_state1011 : begin + ap_NS_fsm = ap_ST_fsm_state1012; + end + ap_ST_fsm_state1012 : begin + ap_NS_fsm = ap_ST_fsm_state1013; + end + ap_ST_fsm_state1013 : begin + ap_NS_fsm = ap_ST_fsm_state1014; + end + ap_ST_fsm_state1014 : begin + ap_NS_fsm = ap_ST_fsm_state1015; + end + ap_ST_fsm_state1015 : begin + ap_NS_fsm = ap_ST_fsm_state1016; + end + ap_ST_fsm_state1016 : begin + ap_NS_fsm = ap_ST_fsm_state1017; + end + ap_ST_fsm_state1017 : begin + ap_NS_fsm = ap_ST_fsm_state1018; + end + ap_ST_fsm_state1018 : begin + ap_NS_fsm = ap_ST_fsm_state1019; + end + ap_ST_fsm_state1019 : begin + ap_NS_fsm = ap_ST_fsm_state1020; + end + ap_ST_fsm_state1020 : begin + ap_NS_fsm = ap_ST_fsm_state985; + end + ap_ST_fsm_state1021 : begin + ap_NS_fsm = ap_ST_fsm_state1022; + end + ap_ST_fsm_state1022 : begin + if (((or_ln223_19_fu_79946_p2 == 1'd0) & (or_ln223_15_reg_91776 == 1'd0) & (ap_ST_fsm_state1022 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1023; + end else begin + ap_NS_fsm = ap_ST_fsm_state1059; + end + end + ap_ST_fsm_state1023 : begin + ap_NS_fsm = ap_ST_fsm_state1024; + end + ap_ST_fsm_state1024 : begin + ap_NS_fsm = ap_ST_fsm_state1025; + end + ap_ST_fsm_state1025 : begin + ap_NS_fsm = ap_ST_fsm_state1026; + end + ap_ST_fsm_state1026 : begin + ap_NS_fsm = ap_ST_fsm_state1027; + end + ap_ST_fsm_state1027 : begin + ap_NS_fsm = ap_ST_fsm_state1028; + end + ap_ST_fsm_state1028 : begin + ap_NS_fsm = ap_ST_fsm_state1029; + end + ap_ST_fsm_state1029 : begin + ap_NS_fsm = ap_ST_fsm_state1030; + end + ap_ST_fsm_state1030 : begin + ap_NS_fsm = ap_ST_fsm_state1031; + end + ap_ST_fsm_state1031 : begin + ap_NS_fsm = ap_ST_fsm_state1032; + end + ap_ST_fsm_state1032 : begin + ap_NS_fsm = ap_ST_fsm_state1033; + end + ap_ST_fsm_state1033 : begin + ap_NS_fsm = ap_ST_fsm_state1034; + end + ap_ST_fsm_state1034 : begin + ap_NS_fsm = ap_ST_fsm_state1035; + end + ap_ST_fsm_state1035 : begin + ap_NS_fsm = ap_ST_fsm_state1036; + end + ap_ST_fsm_state1036 : begin + ap_NS_fsm = ap_ST_fsm_state1037; + end + ap_ST_fsm_state1037 : begin + ap_NS_fsm = ap_ST_fsm_state1038; + end + ap_ST_fsm_state1038 : begin + ap_NS_fsm = ap_ST_fsm_state1039; + end + ap_ST_fsm_state1039 : begin + ap_NS_fsm = ap_ST_fsm_state1040; + end + ap_ST_fsm_state1040 : begin + ap_NS_fsm = ap_ST_fsm_state1041; + end + ap_ST_fsm_state1041 : begin + ap_NS_fsm = ap_ST_fsm_state1042; + end + ap_ST_fsm_state1042 : begin + ap_NS_fsm = ap_ST_fsm_state1043; + end + ap_ST_fsm_state1043 : begin + ap_NS_fsm = ap_ST_fsm_state1044; + end + ap_ST_fsm_state1044 : begin + ap_NS_fsm = ap_ST_fsm_state1045; + end + ap_ST_fsm_state1045 : begin + ap_NS_fsm = ap_ST_fsm_state1046; + end + ap_ST_fsm_state1046 : begin + ap_NS_fsm = ap_ST_fsm_state1047; + end + ap_ST_fsm_state1047 : begin + ap_NS_fsm = ap_ST_fsm_state1048; + end + ap_ST_fsm_state1048 : begin + ap_NS_fsm = ap_ST_fsm_state1049; + end + ap_ST_fsm_state1049 : begin + ap_NS_fsm = ap_ST_fsm_state1050; + end + ap_ST_fsm_state1050 : begin + ap_NS_fsm = ap_ST_fsm_state1051; + end + ap_ST_fsm_state1051 : begin + ap_NS_fsm = ap_ST_fsm_state1052; + end + ap_ST_fsm_state1052 : begin + ap_NS_fsm = ap_ST_fsm_state1053; + end + ap_ST_fsm_state1053 : begin + ap_NS_fsm = ap_ST_fsm_state1054; + end + ap_ST_fsm_state1054 : begin + ap_NS_fsm = ap_ST_fsm_state1055; + end + ap_ST_fsm_state1055 : begin + ap_NS_fsm = ap_ST_fsm_state1056; + end + ap_ST_fsm_state1056 : begin + ap_NS_fsm = ap_ST_fsm_state1057; + end + ap_ST_fsm_state1057 : begin + ap_NS_fsm = ap_ST_fsm_state1058; + end + ap_ST_fsm_state1058 : begin + if (((icmp_ln208_7_fu_80198_p2 == 1'd1) & (ap_ST_fsm_state1058 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state876; + end else if (((or_ln223_23_fu_80248_p2 == 1'd0) & (icmp_ln208_7_fu_80198_p2 == 1'd0) & (or_ln223_15_reg_91776 == 1'd0) & (ap_ST_fsm_state1058 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1094; + end else begin + ap_NS_fsm = ap_ST_fsm_state1130; + end + end + ap_ST_fsm_state1059 : begin + ap_NS_fsm = ap_ST_fsm_state1060; + end + ap_ST_fsm_state1060 : begin + ap_NS_fsm = ap_ST_fsm_state1061; + end + ap_ST_fsm_state1061 : begin + ap_NS_fsm = ap_ST_fsm_state1062; + end + ap_ST_fsm_state1062 : begin + ap_NS_fsm = ap_ST_fsm_state1063; + end + ap_ST_fsm_state1063 : begin + ap_NS_fsm = ap_ST_fsm_state1064; + end + ap_ST_fsm_state1064 : begin + ap_NS_fsm = ap_ST_fsm_state1065; + end + ap_ST_fsm_state1065 : begin + ap_NS_fsm = ap_ST_fsm_state1066; + end + ap_ST_fsm_state1066 : begin + ap_NS_fsm = ap_ST_fsm_state1067; + end + ap_ST_fsm_state1067 : begin + ap_NS_fsm = ap_ST_fsm_state1068; + end + ap_ST_fsm_state1068 : begin + ap_NS_fsm = ap_ST_fsm_state1069; + end + ap_ST_fsm_state1069 : begin + ap_NS_fsm = ap_ST_fsm_state1070; + end + ap_ST_fsm_state1070 : begin + ap_NS_fsm = ap_ST_fsm_state1071; + end + ap_ST_fsm_state1071 : begin + ap_NS_fsm = ap_ST_fsm_state1072; + end + ap_ST_fsm_state1072 : begin + ap_NS_fsm = ap_ST_fsm_state1073; + end + ap_ST_fsm_state1073 : begin + ap_NS_fsm = ap_ST_fsm_state1074; + end + ap_ST_fsm_state1074 : begin + ap_NS_fsm = ap_ST_fsm_state1075; + end + ap_ST_fsm_state1075 : begin + ap_NS_fsm = ap_ST_fsm_state1076; + end + ap_ST_fsm_state1076 : begin + ap_NS_fsm = ap_ST_fsm_state1077; + end + ap_ST_fsm_state1077 : begin + ap_NS_fsm = ap_ST_fsm_state1078; + end + ap_ST_fsm_state1078 : begin + ap_NS_fsm = ap_ST_fsm_state1079; + end + ap_ST_fsm_state1079 : begin + ap_NS_fsm = ap_ST_fsm_state1080; + end + ap_ST_fsm_state1080 : begin + ap_NS_fsm = ap_ST_fsm_state1081; + end + ap_ST_fsm_state1081 : begin + ap_NS_fsm = ap_ST_fsm_state1082; + end + ap_ST_fsm_state1082 : begin + ap_NS_fsm = ap_ST_fsm_state1083; + end + ap_ST_fsm_state1083 : begin + ap_NS_fsm = ap_ST_fsm_state1084; + end + ap_ST_fsm_state1084 : begin + ap_NS_fsm = ap_ST_fsm_state1085; + end + ap_ST_fsm_state1085 : begin + ap_NS_fsm = ap_ST_fsm_state1086; + end + ap_ST_fsm_state1086 : begin + ap_NS_fsm = ap_ST_fsm_state1087; + end + ap_ST_fsm_state1087 : begin + ap_NS_fsm = ap_ST_fsm_state1088; + end + ap_ST_fsm_state1088 : begin + ap_NS_fsm = ap_ST_fsm_state1089; + end + ap_ST_fsm_state1089 : begin + ap_NS_fsm = ap_ST_fsm_state1090; + end + ap_ST_fsm_state1090 : begin + ap_NS_fsm = ap_ST_fsm_state1091; + end + ap_ST_fsm_state1091 : begin + ap_NS_fsm = ap_ST_fsm_state1092; + end + ap_ST_fsm_state1092 : begin + ap_NS_fsm = ap_ST_fsm_state1093; + end + ap_ST_fsm_state1093 : begin + ap_NS_fsm = ap_ST_fsm_state1058; + end + ap_ST_fsm_state1094 : begin + ap_NS_fsm = ap_ST_fsm_state1095; + end + ap_ST_fsm_state1095 : begin + ap_NS_fsm = ap_ST_fsm_state1096; + end + ap_ST_fsm_state1096 : begin + ap_NS_fsm = ap_ST_fsm_state1097; + end + ap_ST_fsm_state1097 : begin + ap_NS_fsm = ap_ST_fsm_state1098; + end + ap_ST_fsm_state1098 : begin + ap_NS_fsm = ap_ST_fsm_state1099; + end + ap_ST_fsm_state1099 : begin + ap_NS_fsm = ap_ST_fsm_state1100; + end + ap_ST_fsm_state1100 : begin + ap_NS_fsm = ap_ST_fsm_state1101; + end + ap_ST_fsm_state1101 : begin + ap_NS_fsm = ap_ST_fsm_state1102; + end + ap_ST_fsm_state1102 : begin + ap_NS_fsm = ap_ST_fsm_state1103; + end + ap_ST_fsm_state1103 : begin + ap_NS_fsm = ap_ST_fsm_state1104; + end + ap_ST_fsm_state1104 : begin + ap_NS_fsm = ap_ST_fsm_state1105; + end + ap_ST_fsm_state1105 : begin + ap_NS_fsm = ap_ST_fsm_state1106; + end + ap_ST_fsm_state1106 : begin + ap_NS_fsm = ap_ST_fsm_state1107; + end + ap_ST_fsm_state1107 : begin + ap_NS_fsm = ap_ST_fsm_state1108; + end + ap_ST_fsm_state1108 : begin + ap_NS_fsm = ap_ST_fsm_state1109; + end + ap_ST_fsm_state1109 : begin + ap_NS_fsm = ap_ST_fsm_state1110; + end + ap_ST_fsm_state1110 : begin + ap_NS_fsm = ap_ST_fsm_state1111; + end + ap_ST_fsm_state1111 : begin + ap_NS_fsm = ap_ST_fsm_state1112; + end + ap_ST_fsm_state1112 : begin + ap_NS_fsm = ap_ST_fsm_state1113; + end + ap_ST_fsm_state1113 : begin + ap_NS_fsm = ap_ST_fsm_state1114; + end + ap_ST_fsm_state1114 : begin + ap_NS_fsm = ap_ST_fsm_state1115; + end + ap_ST_fsm_state1115 : begin + ap_NS_fsm = ap_ST_fsm_state1116; + end + ap_ST_fsm_state1116 : begin + ap_NS_fsm = ap_ST_fsm_state1117; + end + ap_ST_fsm_state1117 : begin + ap_NS_fsm = ap_ST_fsm_state1118; + end + ap_ST_fsm_state1118 : begin + ap_NS_fsm = ap_ST_fsm_state1119; + end + ap_ST_fsm_state1119 : begin + ap_NS_fsm = ap_ST_fsm_state1120; + end + ap_ST_fsm_state1120 : begin + ap_NS_fsm = ap_ST_fsm_state1121; + end + ap_ST_fsm_state1121 : begin + ap_NS_fsm = ap_ST_fsm_state1122; + end + ap_ST_fsm_state1122 : begin + ap_NS_fsm = ap_ST_fsm_state1123; + end + ap_ST_fsm_state1123 : begin + ap_NS_fsm = ap_ST_fsm_state1124; + end + ap_ST_fsm_state1124 : begin + ap_NS_fsm = ap_ST_fsm_state1125; + end + ap_ST_fsm_state1125 : begin + ap_NS_fsm = ap_ST_fsm_state1126; + end + ap_ST_fsm_state1126 : begin + ap_NS_fsm = ap_ST_fsm_state1127; + end + ap_ST_fsm_state1127 : begin + ap_NS_fsm = ap_ST_fsm_state1128; + end + ap_ST_fsm_state1128 : begin + ap_NS_fsm = ap_ST_fsm_state1129; + end + ap_ST_fsm_state1129 : begin + ap_NS_fsm = ap_ST_fsm_state1022; + end + ap_ST_fsm_state1130 : begin + ap_NS_fsm = ap_ST_fsm_state1131; + end + ap_ST_fsm_state1131 : begin + ap_NS_fsm = ap_ST_fsm_state1132; + end + ap_ST_fsm_state1132 : begin + ap_NS_fsm = ap_ST_fsm_state1133; + end + ap_ST_fsm_state1133 : begin + ap_NS_fsm = ap_ST_fsm_state1134; + end + ap_ST_fsm_state1134 : begin + ap_NS_fsm = ap_ST_fsm_state1135; + end + ap_ST_fsm_state1135 : begin + ap_NS_fsm = ap_ST_fsm_state1136; + end + ap_ST_fsm_state1136 : begin + ap_NS_fsm = ap_ST_fsm_state1137; + end + ap_ST_fsm_state1137 : begin + ap_NS_fsm = ap_ST_fsm_state1138; + end + ap_ST_fsm_state1138 : begin + ap_NS_fsm = ap_ST_fsm_state1139; + end + ap_ST_fsm_state1139 : begin + ap_NS_fsm = ap_ST_fsm_state1140; + end + ap_ST_fsm_state1140 : begin + ap_NS_fsm = ap_ST_fsm_state1141; + end + ap_ST_fsm_state1141 : begin + ap_NS_fsm = ap_ST_fsm_state1142; + end + ap_ST_fsm_state1142 : begin + ap_NS_fsm = ap_ST_fsm_state1143; + end + ap_ST_fsm_state1143 : begin + ap_NS_fsm = ap_ST_fsm_state1144; + end + ap_ST_fsm_state1144 : begin + ap_NS_fsm = ap_ST_fsm_state1145; + end + ap_ST_fsm_state1145 : begin + ap_NS_fsm = ap_ST_fsm_state1146; + end + ap_ST_fsm_state1146 : begin + ap_NS_fsm = ap_ST_fsm_state1147; + end + ap_ST_fsm_state1147 : begin + ap_NS_fsm = ap_ST_fsm_state1148; + end + ap_ST_fsm_state1148 : begin + ap_NS_fsm = ap_ST_fsm_state1149; + end + ap_ST_fsm_state1149 : begin + ap_NS_fsm = ap_ST_fsm_state1150; + end + ap_ST_fsm_state1150 : begin + ap_NS_fsm = ap_ST_fsm_state1151; + end + ap_ST_fsm_state1151 : begin + ap_NS_fsm = ap_ST_fsm_state1152; + end + ap_ST_fsm_state1152 : begin + ap_NS_fsm = ap_ST_fsm_state1153; + end + ap_ST_fsm_state1153 : begin + ap_NS_fsm = ap_ST_fsm_state1154; + end + ap_ST_fsm_state1154 : begin + ap_NS_fsm = ap_ST_fsm_state1155; + end + ap_ST_fsm_state1155 : begin + ap_NS_fsm = ap_ST_fsm_state1156; + end + ap_ST_fsm_state1156 : begin + ap_NS_fsm = ap_ST_fsm_state1157; + end + ap_ST_fsm_state1157 : begin + ap_NS_fsm = ap_ST_fsm_state1158; + end + ap_ST_fsm_state1158 : begin + ap_NS_fsm = ap_ST_fsm_state1159; + end + ap_ST_fsm_state1159 : begin + ap_NS_fsm = ap_ST_fsm_state1160; + end + ap_ST_fsm_state1160 : begin + ap_NS_fsm = ap_ST_fsm_state1161; + end + ap_ST_fsm_state1161 : begin + ap_NS_fsm = ap_ST_fsm_state1162; + end + ap_ST_fsm_state1162 : begin + ap_NS_fsm = ap_ST_fsm_state1163; + end + ap_ST_fsm_state1163 : begin + ap_NS_fsm = ap_ST_fsm_state1164; + end + ap_ST_fsm_state1164 : begin + ap_NS_fsm = ap_ST_fsm_state1129; + end + ap_ST_fsm_state1165 : begin + if (((icmp_ln244_fu_80617_p2 == 1'd1) & (ap_ST_fsm_state1165 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1184; + end else begin + ap_NS_fsm = ap_ST_fsm_state1166; + end + end + ap_ST_fsm_state1166 : begin + if (((icmp_ln246_fu_80657_p2 == 1'd1) & (ap_ST_fsm_state1166 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1175; + end else begin + ap_NS_fsm = ap_ST_fsm_state1167; + end + end + ap_ST_fsm_state1167 : begin + if (((icmp_ln248_fu_80819_p2 == 1'd1) & (ap_ST_fsm_state1167 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1171; + end else begin + ap_NS_fsm = ap_ST_fsm_state1168; + end + end + ap_ST_fsm_state1168 : begin + if (((ap_ST_fsm_state1168 == ap_CS_fsm) & ((or_ln203_2_fu_80935_p3 == 6'd31) | ((or_ln203_2_fu_80935_p3 == 6'd1) | ((or_ln203_2_fu_80935_p3 == 6'd61) | ((or_ln203_2_fu_80935_p3 == 6'd3) | ((or_ln203_2_fu_80935_p3 == 6'd39) | ((or_ln203_2_fu_80935_p3 == 6'd5) | ((or_ln203_2_fu_80935_p3 == 6'd59) | ((or_ln203_2_fu_80935_p3 == 6'd7) | ((or_ln203_2_fu_80935_p3 == 6'd33) | ((or_ln203_2_fu_80935_p3 == 6'd9) | ((or_ln203_2_fu_80935_p3 == 6'd57) | ((or_ln203_2_fu_80935_p3 == 6'd11) | ((or_ln203_2_fu_80935_p3 == 6'd45) | ((or_ln203_2_fu_80935_p3 == 6'd13) | ((or_ln203_2_fu_80935_p3 == 6'd55) | ((or_ln203_2_fu_80935_p3 == 6'd15) | ((or_ln203_2_fu_80935_p3 == 6'd35) | ((or_ln203_2_fu_80935_p3 == 6'd17) | ((or_ln203_2_fu_80935_p3 == 6'd53) | ((or_ln203_2_fu_80935_p3 == 6'd19) | ((or_ln203_2_fu_80935_p3 == 6'd41) | ((or_ln203_2_fu_80935_p3 == 6'd21) | ((or_ln203_2_fu_80935_p3 == 6'd51) | ((or_ln203_2_fu_80935_p3 == 6'd23) | ((or_ln203_2_fu_80935_p3 == 6'd37) | ((or_ln203_2_fu_80935_p3 == 6'd25) | ((or_ln203_2_fu_80935_p3 == 6'd49) | ((or_ln203_2_fu_80935_p3 == 6'd27) | ((or_ln203_2_fu_80935_p3 == 6'd43) | ((or_ln203_2_fu_80935_p3 == 6'd29) | (or_ln203_2_fu_80935_p3 == 6'd47))))))))))))))))))))))))))))))))) begin + ap_NS_fsm = ap_ST_fsm_state1170; + end else begin + ap_NS_fsm = ap_ST_fsm_state1169; + end + end + ap_ST_fsm_state1169 : begin + ap_NS_fsm = ap_ST_fsm_state1170; + end + ap_ST_fsm_state1170 : begin + ap_NS_fsm = ap_ST_fsm_state1167; + end + ap_ST_fsm_state1171 : begin + if (((icmp_ln248_2_fu_80953_p2 == 1'd1) & (ap_ST_fsm_state1171 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1166; + end else begin + ap_NS_fsm = ap_ST_fsm_state1172; + end + end + ap_ST_fsm_state1172 : begin + if (((ap_ST_fsm_state1172 == ap_CS_fsm) & ((or_ln203_4_fu_81049_p3 == 6'd31) | ((or_ln203_4_fu_81049_p3 == 6'd1) | ((or_ln203_4_fu_81049_p3 == 6'd61) | ((or_ln203_4_fu_81049_p3 == 6'd3) | ((or_ln203_4_fu_81049_p3 == 6'd39) | ((or_ln203_4_fu_81049_p3 == 6'd5) | ((or_ln203_4_fu_81049_p3 == 6'd59) | ((or_ln203_4_fu_81049_p3 == 6'd7) | ((or_ln203_4_fu_81049_p3 == 6'd33) | ((or_ln203_4_fu_81049_p3 == 6'd9) | ((or_ln203_4_fu_81049_p3 == 6'd57) | ((or_ln203_4_fu_81049_p3 == 6'd11) | ((or_ln203_4_fu_81049_p3 == 6'd45) | ((or_ln203_4_fu_81049_p3 == 6'd13) | ((or_ln203_4_fu_81049_p3 == 6'd55) | ((or_ln203_4_fu_81049_p3 == 6'd15) | ((or_ln203_4_fu_81049_p3 == 6'd35) | ((or_ln203_4_fu_81049_p3 == 6'd17) | ((or_ln203_4_fu_81049_p3 == 6'd53) | ((or_ln203_4_fu_81049_p3 == 6'd19) | ((or_ln203_4_fu_81049_p3 == 6'd41) | ((or_ln203_4_fu_81049_p3 == 6'd21) | ((or_ln203_4_fu_81049_p3 == 6'd51) | ((or_ln203_4_fu_81049_p3 == 6'd23) | ((or_ln203_4_fu_81049_p3 == 6'd37) | ((or_ln203_4_fu_81049_p3 == 6'd25) | ((or_ln203_4_fu_81049_p3 == 6'd49) | ((or_ln203_4_fu_81049_p3 == 6'd27) | ((or_ln203_4_fu_81049_p3 == 6'd43) | ((or_ln203_4_fu_81049_p3 == 6'd29) | (or_ln203_4_fu_81049_p3 == 6'd47))))))))))))))))))))))))))))))))) begin + ap_NS_fsm = ap_ST_fsm_state1174; + end else begin + ap_NS_fsm = ap_ST_fsm_state1173; + end + end + ap_ST_fsm_state1173 : begin + ap_NS_fsm = ap_ST_fsm_state1174; + end + ap_ST_fsm_state1174 : begin + ap_NS_fsm = ap_ST_fsm_state1171; + end + ap_ST_fsm_state1175 : begin + if (((icmp_ln246_1_fu_81063_p2 == 1'd1) & (ap_ST_fsm_state1175 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1165; + end else begin + ap_NS_fsm = ap_ST_fsm_state1176; + end + end + ap_ST_fsm_state1176 : begin + if (((icmp_ln248_1_fu_81191_p2 == 1'd1) & (ap_ST_fsm_state1176 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1180; + end else begin + ap_NS_fsm = ap_ST_fsm_state1177; + end + end + ap_ST_fsm_state1177 : begin + if (((ap_ST_fsm_state1177 == ap_CS_fsm) & ((or_ln203_3_fu_81311_p3 == 6'd31) | ((or_ln203_3_fu_81311_p3 == 6'd1) | ((or_ln203_3_fu_81311_p3 == 6'd61) | ((or_ln203_3_fu_81311_p3 == 6'd3) | ((or_ln203_3_fu_81311_p3 == 6'd39) | ((or_ln203_3_fu_81311_p3 == 6'd5) | ((or_ln203_3_fu_81311_p3 == 6'd59) | ((or_ln203_3_fu_81311_p3 == 6'd7) | ((or_ln203_3_fu_81311_p3 == 6'd33) | ((or_ln203_3_fu_81311_p3 == 6'd9) | ((or_ln203_3_fu_81311_p3 == 6'd57) | ((or_ln203_3_fu_81311_p3 == 6'd11) | ((or_ln203_3_fu_81311_p3 == 6'd45) | ((or_ln203_3_fu_81311_p3 == 6'd13) | ((or_ln203_3_fu_81311_p3 == 6'd55) | ((or_ln203_3_fu_81311_p3 == 6'd15) | ((or_ln203_3_fu_81311_p3 == 6'd35) | ((or_ln203_3_fu_81311_p3 == 6'd17) | ((or_ln203_3_fu_81311_p3 == 6'd53) | ((or_ln203_3_fu_81311_p3 == 6'd19) | ((or_ln203_3_fu_81311_p3 == 6'd41) | ((or_ln203_3_fu_81311_p3 == 6'd21) | ((or_ln203_3_fu_81311_p3 == 6'd51) | ((or_ln203_3_fu_81311_p3 == 6'd23) | ((or_ln203_3_fu_81311_p3 == 6'd37) | ((or_ln203_3_fu_81311_p3 == 6'd25) | ((or_ln203_3_fu_81311_p3 == 6'd49) | ((or_ln203_3_fu_81311_p3 == 6'd27) | ((or_ln203_3_fu_81311_p3 == 6'd43) | ((or_ln203_3_fu_81311_p3 == 6'd29) | (or_ln203_3_fu_81311_p3 == 6'd47))))))))))))))))))))))))))))))))) begin + ap_NS_fsm = ap_ST_fsm_state1179; + end else begin + ap_NS_fsm = ap_ST_fsm_state1178; + end + end + ap_ST_fsm_state1178 : begin + ap_NS_fsm = ap_ST_fsm_state1179; + end + ap_ST_fsm_state1179 : begin + ap_NS_fsm = ap_ST_fsm_state1176; + end + ap_ST_fsm_state1180 : begin + if (((icmp_ln248_3_fu_81329_p2 == 1'd1) & (ap_ST_fsm_state1180 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1175; + end else begin + ap_NS_fsm = ap_ST_fsm_state1181; + end + end + ap_ST_fsm_state1181 : begin + if (((ap_ST_fsm_state1181 == ap_CS_fsm) & ((or_ln203_5_fu_81425_p3 == 6'd31) | ((or_ln203_5_fu_81425_p3 == 6'd1) | ((or_ln203_5_fu_81425_p3 == 6'd61) | ((or_ln203_5_fu_81425_p3 == 6'd3) | ((or_ln203_5_fu_81425_p3 == 6'd39) | ((or_ln203_5_fu_81425_p3 == 6'd5) | ((or_ln203_5_fu_81425_p3 == 6'd59) | ((or_ln203_5_fu_81425_p3 == 6'd7) | ((or_ln203_5_fu_81425_p3 == 6'd33) | ((or_ln203_5_fu_81425_p3 == 6'd9) | ((or_ln203_5_fu_81425_p3 == 6'd57) | ((or_ln203_5_fu_81425_p3 == 6'd11) | ((or_ln203_5_fu_81425_p3 == 6'd45) | ((or_ln203_5_fu_81425_p3 == 6'd13) | ((or_ln203_5_fu_81425_p3 == 6'd55) | ((or_ln203_5_fu_81425_p3 == 6'd15) | ((or_ln203_5_fu_81425_p3 == 6'd35) | ((or_ln203_5_fu_81425_p3 == 6'd17) | ((or_ln203_5_fu_81425_p3 == 6'd53) | ((or_ln203_5_fu_81425_p3 == 6'd19) | ((or_ln203_5_fu_81425_p3 == 6'd41) | ((or_ln203_5_fu_81425_p3 == 6'd21) | ((or_ln203_5_fu_81425_p3 == 6'd51) | ((or_ln203_5_fu_81425_p3 == 6'd23) | ((or_ln203_5_fu_81425_p3 == 6'd37) | ((or_ln203_5_fu_81425_p3 == 6'd25) | ((or_ln203_5_fu_81425_p3 == 6'd49) | ((or_ln203_5_fu_81425_p3 == 6'd27) | ((or_ln203_5_fu_81425_p3 == 6'd43) | ((or_ln203_5_fu_81425_p3 == 6'd29) | (or_ln203_5_fu_81425_p3 == 6'd47))))))))))))))))))))))))))))))))) begin + ap_NS_fsm = ap_ST_fsm_state1183; + end else begin + ap_NS_fsm = ap_ST_fsm_state1182; + end + end + ap_ST_fsm_state1182 : begin + ap_NS_fsm = ap_ST_fsm_state1183; + end + ap_ST_fsm_state1183 : begin + ap_NS_fsm = ap_ST_fsm_state1180; + end + ap_ST_fsm_state1184 : begin + if (((icmp_ln257_fu_81443_p2 == 1'd0) & (ap_ST_fsm_state1184 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1185; + end else begin + ap_NS_fsm = ap_ST_fsm_state2387; + end + end + ap_ST_fsm_state1185 : begin + if (((icmp_ln259_fu_81487_p2 == 1'd1) & (ap_ST_fsm_state1185 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1787; + end else begin + ap_NS_fsm = ap_ST_fsm_state1186; + end + end + ap_ST_fsm_state1186 : begin + if (((icmp_ln261_fu_81657_p2 == 1'd1) & (ap_ST_fsm_state1186 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1487; + end else begin + ap_NS_fsm = ap_ST_fsm_state1187; + end + end + ap_ST_fsm_state1187 : begin + ap_NS_fsm = ap_ST_fsm_state1188; + end + ap_ST_fsm_state1188 : begin + ap_NS_fsm = ap_ST_fsm_state1189; + end + ap_ST_fsm_state1189 : begin + ap_NS_fsm = ap_ST_fsm_state1190; + end + ap_ST_fsm_state1190 : begin + ap_NS_fsm = ap_ST_fsm_state1191; + end + ap_ST_fsm_state1191 : begin + ap_NS_fsm = ap_ST_fsm_state1192; + end + ap_ST_fsm_state1192 : begin + ap_NS_fsm = ap_ST_fsm_state1193; + end + ap_ST_fsm_state1193 : begin + ap_NS_fsm = ap_ST_fsm_state1194; + end + ap_ST_fsm_state1194 : begin + ap_NS_fsm = ap_ST_fsm_state1195; + end + ap_ST_fsm_state1195 : begin + ap_NS_fsm = ap_ST_fsm_state1196; + end + ap_ST_fsm_state1196 : begin + ap_NS_fsm = ap_ST_fsm_state1197; + end + ap_ST_fsm_state1197 : begin + ap_NS_fsm = ap_ST_fsm_state1198; + end + ap_ST_fsm_state1198 : begin + ap_NS_fsm = ap_ST_fsm_state1199; + end + ap_ST_fsm_state1199 : begin + ap_NS_fsm = ap_ST_fsm_state1200; + end + ap_ST_fsm_state1200 : begin + ap_NS_fsm = ap_ST_fsm_state1201; + end + ap_ST_fsm_state1201 : begin + ap_NS_fsm = ap_ST_fsm_state1202; + end + ap_ST_fsm_state1202 : begin + ap_NS_fsm = ap_ST_fsm_state1203; + end + ap_ST_fsm_state1203 : begin + ap_NS_fsm = ap_ST_fsm_state1204; + end + ap_ST_fsm_state1204 : begin + ap_NS_fsm = ap_ST_fsm_state1205; + end + ap_ST_fsm_state1205 : begin + ap_NS_fsm = ap_ST_fsm_state1206; + end + ap_ST_fsm_state1206 : begin + ap_NS_fsm = ap_ST_fsm_state1207; + end + ap_ST_fsm_state1207 : begin + ap_NS_fsm = ap_ST_fsm_state1208; + end + ap_ST_fsm_state1208 : begin + ap_NS_fsm = ap_ST_fsm_state1209; + end + ap_ST_fsm_state1209 : begin + ap_NS_fsm = ap_ST_fsm_state1210; + end + ap_ST_fsm_state1210 : begin + ap_NS_fsm = ap_ST_fsm_state1211; + end + ap_ST_fsm_state1211 : begin + ap_NS_fsm = ap_ST_fsm_state1212; + end + ap_ST_fsm_state1212 : begin + ap_NS_fsm = ap_ST_fsm_state1213; + end + ap_ST_fsm_state1213 : begin + ap_NS_fsm = ap_ST_fsm_state1214; + end + ap_ST_fsm_state1214 : begin + ap_NS_fsm = ap_ST_fsm_state1215; + end + ap_ST_fsm_state1215 : begin + ap_NS_fsm = ap_ST_fsm_state1216; + end + ap_ST_fsm_state1216 : begin + ap_NS_fsm = ap_ST_fsm_state1217; + end + ap_ST_fsm_state1217 : begin + ap_NS_fsm = ap_ST_fsm_state1218; + end + ap_ST_fsm_state1218 : begin + ap_NS_fsm = ap_ST_fsm_state1219; + end + ap_ST_fsm_state1219 : begin + ap_NS_fsm = ap_ST_fsm_state1220; + end + ap_ST_fsm_state1220 : begin + ap_NS_fsm = ap_ST_fsm_state1221; + end + ap_ST_fsm_state1221 : begin + ap_NS_fsm = ap_ST_fsm_state1222; + end + ap_ST_fsm_state1222 : begin + ap_NS_fsm = ap_ST_fsm_state1223; + end + ap_ST_fsm_state1223 : begin + ap_NS_fsm = ap_ST_fsm_state1224; + end + ap_ST_fsm_state1224 : begin + ap_NS_fsm = ap_ST_fsm_state1225; + end + ap_ST_fsm_state1225 : begin + if (((icmp_ln266_fu_82020_p2 == 1'd1) & (icmp_ln268_fu_81997_p2 == 1'd1) & (ap_ST_fsm_state1225 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1338; + end else if (((icmp_ln268_fu_81997_p2 == 1'd1) & (icmp_ln266_fu_82020_p2 == 1'd0) & (ap_ST_fsm_state1225 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1263; + end else begin + ap_NS_fsm = ap_ST_fsm_state1226; + end + end + ap_ST_fsm_state1226 : begin + ap_NS_fsm = ap_ST_fsm_state1227; + end + ap_ST_fsm_state1227 : begin + ap_NS_fsm = ap_ST_fsm_state1228; + end + ap_ST_fsm_state1228 : begin + ap_NS_fsm = ap_ST_fsm_state1229; + end + ap_ST_fsm_state1229 : begin + ap_NS_fsm = ap_ST_fsm_state1230; + end + ap_ST_fsm_state1230 : begin + ap_NS_fsm = ap_ST_fsm_state1231; + end + ap_ST_fsm_state1231 : begin + ap_NS_fsm = ap_ST_fsm_state1232; + end + ap_ST_fsm_state1232 : begin + ap_NS_fsm = ap_ST_fsm_state1233; + end + ap_ST_fsm_state1233 : begin + ap_NS_fsm = ap_ST_fsm_state1234; + end + ap_ST_fsm_state1234 : begin + ap_NS_fsm = ap_ST_fsm_state1235; + end + ap_ST_fsm_state1235 : begin + ap_NS_fsm = ap_ST_fsm_state1236; + end + ap_ST_fsm_state1236 : begin + ap_NS_fsm = ap_ST_fsm_state1237; + end + ap_ST_fsm_state1237 : begin + ap_NS_fsm = ap_ST_fsm_state1238; + end + ap_ST_fsm_state1238 : begin + ap_NS_fsm = ap_ST_fsm_state1239; + end + ap_ST_fsm_state1239 : begin + ap_NS_fsm = ap_ST_fsm_state1240; + end + ap_ST_fsm_state1240 : begin + ap_NS_fsm = ap_ST_fsm_state1241; + end + ap_ST_fsm_state1241 : begin + ap_NS_fsm = ap_ST_fsm_state1242; + end + ap_ST_fsm_state1242 : begin + ap_NS_fsm = ap_ST_fsm_state1243; + end + ap_ST_fsm_state1243 : begin + ap_NS_fsm = ap_ST_fsm_state1244; + end + ap_ST_fsm_state1244 : begin + ap_NS_fsm = ap_ST_fsm_state1245; + end + ap_ST_fsm_state1245 : begin + ap_NS_fsm = ap_ST_fsm_state1246; + end + ap_ST_fsm_state1246 : begin + ap_NS_fsm = ap_ST_fsm_state1247; + end + ap_ST_fsm_state1247 : begin + ap_NS_fsm = ap_ST_fsm_state1248; + end + ap_ST_fsm_state1248 : begin + ap_NS_fsm = ap_ST_fsm_state1249; + end + ap_ST_fsm_state1249 : begin + ap_NS_fsm = ap_ST_fsm_state1250; + end + ap_ST_fsm_state1250 : begin + ap_NS_fsm = ap_ST_fsm_state1251; + end + ap_ST_fsm_state1251 : begin + ap_NS_fsm = ap_ST_fsm_state1252; + end + ap_ST_fsm_state1252 : begin + ap_NS_fsm = ap_ST_fsm_state1253; + end + ap_ST_fsm_state1253 : begin + ap_NS_fsm = ap_ST_fsm_state1254; + end + ap_ST_fsm_state1254 : begin + ap_NS_fsm = ap_ST_fsm_state1255; + end + ap_ST_fsm_state1255 : begin + ap_NS_fsm = ap_ST_fsm_state1256; + end + ap_ST_fsm_state1256 : begin + ap_NS_fsm = ap_ST_fsm_state1257; + end + ap_ST_fsm_state1257 : begin + ap_NS_fsm = ap_ST_fsm_state1258; + end + ap_ST_fsm_state1258 : begin + ap_NS_fsm = ap_ST_fsm_state1259; + end + ap_ST_fsm_state1259 : begin + ap_NS_fsm = ap_ST_fsm_state1260; + end + ap_ST_fsm_state1260 : begin + ap_NS_fsm = ap_ST_fsm_state1261; + end + ap_ST_fsm_state1261 : begin + ap_NS_fsm = ap_ST_fsm_state1262; + end + ap_ST_fsm_state1262 : begin + ap_NS_fsm = ap_ST_fsm_state1188; + end + ap_ST_fsm_state1263 : begin + ap_NS_fsm = ap_ST_fsm_state1264; + end + ap_ST_fsm_state1264 : begin + ap_NS_fsm = ap_ST_fsm_state1265; + end + ap_ST_fsm_state1265 : begin + ap_NS_fsm = ap_ST_fsm_state1266; + end + ap_ST_fsm_state1266 : begin + ap_NS_fsm = ap_ST_fsm_state1267; + end + ap_ST_fsm_state1267 : begin + ap_NS_fsm = ap_ST_fsm_state1268; + end + ap_ST_fsm_state1268 : begin + ap_NS_fsm = ap_ST_fsm_state1269; + end + ap_ST_fsm_state1269 : begin + ap_NS_fsm = ap_ST_fsm_state1270; + end + ap_ST_fsm_state1270 : begin + ap_NS_fsm = ap_ST_fsm_state1271; + end + ap_ST_fsm_state1271 : begin + ap_NS_fsm = ap_ST_fsm_state1272; + end + ap_ST_fsm_state1272 : begin + ap_NS_fsm = ap_ST_fsm_state1273; + end + ap_ST_fsm_state1273 : begin + ap_NS_fsm = ap_ST_fsm_state1274; + end + ap_ST_fsm_state1274 : begin + ap_NS_fsm = ap_ST_fsm_state1275; + end + ap_ST_fsm_state1275 : begin + ap_NS_fsm = ap_ST_fsm_state1276; + end + ap_ST_fsm_state1276 : begin + ap_NS_fsm = ap_ST_fsm_state1277; + end + ap_ST_fsm_state1277 : begin + ap_NS_fsm = ap_ST_fsm_state1278; + end + ap_ST_fsm_state1278 : begin + ap_NS_fsm = ap_ST_fsm_state1279; + end + ap_ST_fsm_state1279 : begin + ap_NS_fsm = ap_ST_fsm_state1280; + end + ap_ST_fsm_state1280 : begin + ap_NS_fsm = ap_ST_fsm_state1281; + end + ap_ST_fsm_state1281 : begin + ap_NS_fsm = ap_ST_fsm_state1282; + end + ap_ST_fsm_state1282 : begin + ap_NS_fsm = ap_ST_fsm_state1283; + end + ap_ST_fsm_state1283 : begin + ap_NS_fsm = ap_ST_fsm_state1284; + end + ap_ST_fsm_state1284 : begin + ap_NS_fsm = ap_ST_fsm_state1285; + end + ap_ST_fsm_state1285 : begin + ap_NS_fsm = ap_ST_fsm_state1286; + end + ap_ST_fsm_state1286 : begin + ap_NS_fsm = ap_ST_fsm_state1287; + end + ap_ST_fsm_state1287 : begin + ap_NS_fsm = ap_ST_fsm_state1288; + end + ap_ST_fsm_state1288 : begin + ap_NS_fsm = ap_ST_fsm_state1289; + end + ap_ST_fsm_state1289 : begin + ap_NS_fsm = ap_ST_fsm_state1290; + end + ap_ST_fsm_state1290 : begin + ap_NS_fsm = ap_ST_fsm_state1291; + end + ap_ST_fsm_state1291 : begin + ap_NS_fsm = ap_ST_fsm_state1292; + end + ap_ST_fsm_state1292 : begin + ap_NS_fsm = ap_ST_fsm_state1293; + end + ap_ST_fsm_state1293 : begin + ap_NS_fsm = ap_ST_fsm_state1294; + end + ap_ST_fsm_state1294 : begin + ap_NS_fsm = ap_ST_fsm_state1295; + end + ap_ST_fsm_state1295 : begin + ap_NS_fsm = ap_ST_fsm_state1296; + end + ap_ST_fsm_state1296 : begin + ap_NS_fsm = ap_ST_fsm_state1297; + end + ap_ST_fsm_state1297 : begin + ap_NS_fsm = ap_ST_fsm_state1298; + end + ap_ST_fsm_state1298 : begin + ap_NS_fsm = ap_ST_fsm_state1299; + end + ap_ST_fsm_state1299 : begin + ap_NS_fsm = ap_ST_fsm_state1300; + end + ap_ST_fsm_state1300 : begin + if (((icmp_ln268_4_fu_82403_p2 == 1'd1) & (ap_ST_fsm_state1300 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1187; + end else begin + ap_NS_fsm = ap_ST_fsm_state1301; + end + end + ap_ST_fsm_state1301 : begin + ap_NS_fsm = ap_ST_fsm_state1302; + end + ap_ST_fsm_state1302 : begin + ap_NS_fsm = ap_ST_fsm_state1303; + end + ap_ST_fsm_state1303 : begin + ap_NS_fsm = ap_ST_fsm_state1304; + end + ap_ST_fsm_state1304 : begin + ap_NS_fsm = ap_ST_fsm_state1305; + end + ap_ST_fsm_state1305 : begin + ap_NS_fsm = ap_ST_fsm_state1306; + end + ap_ST_fsm_state1306 : begin + ap_NS_fsm = ap_ST_fsm_state1307; + end + ap_ST_fsm_state1307 : begin + ap_NS_fsm = ap_ST_fsm_state1308; + end + ap_ST_fsm_state1308 : begin + ap_NS_fsm = ap_ST_fsm_state1309; + end + ap_ST_fsm_state1309 : begin + ap_NS_fsm = ap_ST_fsm_state1310; + end + ap_ST_fsm_state1310 : begin + ap_NS_fsm = ap_ST_fsm_state1311; + end + ap_ST_fsm_state1311 : begin + ap_NS_fsm = ap_ST_fsm_state1312; + end + ap_ST_fsm_state1312 : begin + ap_NS_fsm = ap_ST_fsm_state1313; + end + ap_ST_fsm_state1313 : begin + ap_NS_fsm = ap_ST_fsm_state1314; + end + ap_ST_fsm_state1314 : begin + ap_NS_fsm = ap_ST_fsm_state1315; + end + ap_ST_fsm_state1315 : begin + ap_NS_fsm = ap_ST_fsm_state1316; + end + ap_ST_fsm_state1316 : begin + ap_NS_fsm = ap_ST_fsm_state1317; + end + ap_ST_fsm_state1317 : begin + ap_NS_fsm = ap_ST_fsm_state1318; + end + ap_ST_fsm_state1318 : begin + ap_NS_fsm = ap_ST_fsm_state1319; + end + ap_ST_fsm_state1319 : begin + ap_NS_fsm = ap_ST_fsm_state1320; + end + ap_ST_fsm_state1320 : begin + ap_NS_fsm = ap_ST_fsm_state1321; + end + ap_ST_fsm_state1321 : begin + ap_NS_fsm = ap_ST_fsm_state1322; + end + ap_ST_fsm_state1322 : begin + ap_NS_fsm = ap_ST_fsm_state1323; + end + ap_ST_fsm_state1323 : begin + ap_NS_fsm = ap_ST_fsm_state1324; + end + ap_ST_fsm_state1324 : begin + ap_NS_fsm = ap_ST_fsm_state1325; + end + ap_ST_fsm_state1325 : begin + ap_NS_fsm = ap_ST_fsm_state1326; + end + ap_ST_fsm_state1326 : begin + ap_NS_fsm = ap_ST_fsm_state1327; + end + ap_ST_fsm_state1327 : begin + ap_NS_fsm = ap_ST_fsm_state1328; + end + ap_ST_fsm_state1328 : begin + ap_NS_fsm = ap_ST_fsm_state1329; + end + ap_ST_fsm_state1329 : begin + ap_NS_fsm = ap_ST_fsm_state1330; + end + ap_ST_fsm_state1330 : begin + ap_NS_fsm = ap_ST_fsm_state1331; + end + ap_ST_fsm_state1331 : begin + ap_NS_fsm = ap_ST_fsm_state1332; + end + ap_ST_fsm_state1332 : begin + ap_NS_fsm = ap_ST_fsm_state1333; + end + ap_ST_fsm_state1333 : begin + ap_NS_fsm = ap_ST_fsm_state1334; + end + ap_ST_fsm_state1334 : begin + ap_NS_fsm = ap_ST_fsm_state1335; + end + ap_ST_fsm_state1335 : begin + ap_NS_fsm = ap_ST_fsm_state1336; + end + ap_ST_fsm_state1336 : begin + ap_NS_fsm = ap_ST_fsm_state1337; + end + ap_ST_fsm_state1337 : begin + ap_NS_fsm = ap_ST_fsm_state1263; + end + ap_ST_fsm_state1338 : begin + ap_NS_fsm = ap_ST_fsm_state1339; + end + ap_ST_fsm_state1339 : begin + ap_NS_fsm = ap_ST_fsm_state1340; + end + ap_ST_fsm_state1340 : begin + ap_NS_fsm = ap_ST_fsm_state1341; + end + ap_ST_fsm_state1341 : begin + ap_NS_fsm = ap_ST_fsm_state1342; + end + ap_ST_fsm_state1342 : begin + ap_NS_fsm = ap_ST_fsm_state1343; + end + ap_ST_fsm_state1343 : begin + ap_NS_fsm = ap_ST_fsm_state1344; + end + ap_ST_fsm_state1344 : begin + ap_NS_fsm = ap_ST_fsm_state1345; + end + ap_ST_fsm_state1345 : begin + ap_NS_fsm = ap_ST_fsm_state1346; + end + ap_ST_fsm_state1346 : begin + ap_NS_fsm = ap_ST_fsm_state1347; + end + ap_ST_fsm_state1347 : begin + ap_NS_fsm = ap_ST_fsm_state1348; + end + ap_ST_fsm_state1348 : begin + ap_NS_fsm = ap_ST_fsm_state1349; + end + ap_ST_fsm_state1349 : begin + ap_NS_fsm = ap_ST_fsm_state1350; + end + ap_ST_fsm_state1350 : begin + ap_NS_fsm = ap_ST_fsm_state1351; + end + ap_ST_fsm_state1351 : begin + ap_NS_fsm = ap_ST_fsm_state1352; + end + ap_ST_fsm_state1352 : begin + ap_NS_fsm = ap_ST_fsm_state1353; + end + ap_ST_fsm_state1353 : begin + ap_NS_fsm = ap_ST_fsm_state1354; + end + ap_ST_fsm_state1354 : begin + ap_NS_fsm = ap_ST_fsm_state1355; + end + ap_ST_fsm_state1355 : begin + ap_NS_fsm = ap_ST_fsm_state1356; + end + ap_ST_fsm_state1356 : begin + ap_NS_fsm = ap_ST_fsm_state1357; + end + ap_ST_fsm_state1357 : begin + ap_NS_fsm = ap_ST_fsm_state1358; + end + ap_ST_fsm_state1358 : begin + ap_NS_fsm = ap_ST_fsm_state1359; + end + ap_ST_fsm_state1359 : begin + ap_NS_fsm = ap_ST_fsm_state1360; + end + ap_ST_fsm_state1360 : begin + ap_NS_fsm = ap_ST_fsm_state1361; + end + ap_ST_fsm_state1361 : begin + ap_NS_fsm = ap_ST_fsm_state1362; + end + ap_ST_fsm_state1362 : begin + ap_NS_fsm = ap_ST_fsm_state1363; + end + ap_ST_fsm_state1363 : begin + ap_NS_fsm = ap_ST_fsm_state1364; + end + ap_ST_fsm_state1364 : begin + ap_NS_fsm = ap_ST_fsm_state1365; + end + ap_ST_fsm_state1365 : begin + ap_NS_fsm = ap_ST_fsm_state1366; + end + ap_ST_fsm_state1366 : begin + ap_NS_fsm = ap_ST_fsm_state1367; + end + ap_ST_fsm_state1367 : begin + ap_NS_fsm = ap_ST_fsm_state1368; + end + ap_ST_fsm_state1368 : begin + ap_NS_fsm = ap_ST_fsm_state1369; + end + ap_ST_fsm_state1369 : begin + ap_NS_fsm = ap_ST_fsm_state1370; + end + ap_ST_fsm_state1370 : begin + ap_NS_fsm = ap_ST_fsm_state1371; + end + ap_ST_fsm_state1371 : begin + ap_NS_fsm = ap_ST_fsm_state1372; + end + ap_ST_fsm_state1372 : begin + ap_NS_fsm = ap_ST_fsm_state1373; + end + ap_ST_fsm_state1373 : begin + ap_NS_fsm = ap_ST_fsm_state1374; + end + ap_ST_fsm_state1374 : begin + ap_NS_fsm = ap_ST_fsm_state1375; + end + ap_ST_fsm_state1375 : begin + ap_NS_fsm = ap_ST_fsm_state1376; + end + ap_ST_fsm_state1376 : begin + if (((icmp_ln266_4_fu_82904_p2 == 1'd1) & (icmp_ln268_5_fu_82881_p2 == 1'd1) & (ap_ST_fsm_state1376 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1186; + end else if (((icmp_ln268_5_fu_82881_p2 == 1'd1) & (icmp_ln266_4_fu_82904_p2 == 1'd0) & (ap_ST_fsm_state1376 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1414; + end else begin + ap_NS_fsm = ap_ST_fsm_state1377; + end + end + ap_ST_fsm_state1377 : begin + ap_NS_fsm = ap_ST_fsm_state1378; + end + ap_ST_fsm_state1378 : begin + ap_NS_fsm = ap_ST_fsm_state1379; + end + ap_ST_fsm_state1379 : begin + ap_NS_fsm = ap_ST_fsm_state1380; + end + ap_ST_fsm_state1380 : begin + ap_NS_fsm = ap_ST_fsm_state1381; + end + ap_ST_fsm_state1381 : begin + ap_NS_fsm = ap_ST_fsm_state1382; + end + ap_ST_fsm_state1382 : begin + ap_NS_fsm = ap_ST_fsm_state1383; + end + ap_ST_fsm_state1383 : begin + ap_NS_fsm = ap_ST_fsm_state1384; + end + ap_ST_fsm_state1384 : begin + ap_NS_fsm = ap_ST_fsm_state1385; + end + ap_ST_fsm_state1385 : begin + ap_NS_fsm = ap_ST_fsm_state1386; + end + ap_ST_fsm_state1386 : begin + ap_NS_fsm = ap_ST_fsm_state1387; + end + ap_ST_fsm_state1387 : begin + ap_NS_fsm = ap_ST_fsm_state1388; + end + ap_ST_fsm_state1388 : begin + ap_NS_fsm = ap_ST_fsm_state1389; + end + ap_ST_fsm_state1389 : begin + ap_NS_fsm = ap_ST_fsm_state1390; + end + ap_ST_fsm_state1390 : begin + ap_NS_fsm = ap_ST_fsm_state1391; + end + ap_ST_fsm_state1391 : begin + ap_NS_fsm = ap_ST_fsm_state1392; + end + ap_ST_fsm_state1392 : begin + ap_NS_fsm = ap_ST_fsm_state1393; + end + ap_ST_fsm_state1393 : begin + ap_NS_fsm = ap_ST_fsm_state1394; + end + ap_ST_fsm_state1394 : begin + ap_NS_fsm = ap_ST_fsm_state1395; + end + ap_ST_fsm_state1395 : begin + ap_NS_fsm = ap_ST_fsm_state1396; + end + ap_ST_fsm_state1396 : begin + ap_NS_fsm = ap_ST_fsm_state1397; + end + ap_ST_fsm_state1397 : begin + ap_NS_fsm = ap_ST_fsm_state1398; + end + ap_ST_fsm_state1398 : begin + ap_NS_fsm = ap_ST_fsm_state1399; + end + ap_ST_fsm_state1399 : begin + ap_NS_fsm = ap_ST_fsm_state1400; + end + ap_ST_fsm_state1400 : begin + ap_NS_fsm = ap_ST_fsm_state1401; + end + ap_ST_fsm_state1401 : begin + ap_NS_fsm = ap_ST_fsm_state1402; + end + ap_ST_fsm_state1402 : begin + ap_NS_fsm = ap_ST_fsm_state1403; + end + ap_ST_fsm_state1403 : begin + ap_NS_fsm = ap_ST_fsm_state1404; + end + ap_ST_fsm_state1404 : begin + ap_NS_fsm = ap_ST_fsm_state1405; + end + ap_ST_fsm_state1405 : begin + ap_NS_fsm = ap_ST_fsm_state1406; + end + ap_ST_fsm_state1406 : begin + ap_NS_fsm = ap_ST_fsm_state1407; + end + ap_ST_fsm_state1407 : begin + ap_NS_fsm = ap_ST_fsm_state1408; + end + ap_ST_fsm_state1408 : begin + ap_NS_fsm = ap_ST_fsm_state1409; + end + ap_ST_fsm_state1409 : begin + ap_NS_fsm = ap_ST_fsm_state1410; + end + ap_ST_fsm_state1410 : begin + ap_NS_fsm = ap_ST_fsm_state1411; + end + ap_ST_fsm_state1411 : begin + ap_NS_fsm = ap_ST_fsm_state1412; + end + ap_ST_fsm_state1412 : begin + ap_NS_fsm = ap_ST_fsm_state1413; + end + ap_ST_fsm_state1413 : begin + ap_NS_fsm = ap_ST_fsm_state1339; + end + ap_ST_fsm_state1414 : begin + ap_NS_fsm = ap_ST_fsm_state1415; + end + ap_ST_fsm_state1415 : begin + ap_NS_fsm = ap_ST_fsm_state1416; + end + ap_ST_fsm_state1416 : begin + ap_NS_fsm = ap_ST_fsm_state1417; + end + ap_ST_fsm_state1417 : begin + ap_NS_fsm = ap_ST_fsm_state1418; + end + ap_ST_fsm_state1418 : begin + ap_NS_fsm = ap_ST_fsm_state1419; + end + ap_ST_fsm_state1419 : begin + ap_NS_fsm = ap_ST_fsm_state1420; + end + ap_ST_fsm_state1420 : begin + ap_NS_fsm = ap_ST_fsm_state1421; + end + ap_ST_fsm_state1421 : begin + ap_NS_fsm = ap_ST_fsm_state1422; + end + ap_ST_fsm_state1422 : begin + ap_NS_fsm = ap_ST_fsm_state1423; + end + ap_ST_fsm_state1423 : begin + ap_NS_fsm = ap_ST_fsm_state1424; + end + ap_ST_fsm_state1424 : begin + ap_NS_fsm = ap_ST_fsm_state1425; + end + ap_ST_fsm_state1425 : begin + ap_NS_fsm = ap_ST_fsm_state1426; + end + ap_ST_fsm_state1426 : begin + ap_NS_fsm = ap_ST_fsm_state1427; + end + ap_ST_fsm_state1427 : begin + ap_NS_fsm = ap_ST_fsm_state1428; + end + ap_ST_fsm_state1428 : begin + ap_NS_fsm = ap_ST_fsm_state1429; + end + ap_ST_fsm_state1429 : begin + ap_NS_fsm = ap_ST_fsm_state1430; + end + ap_ST_fsm_state1430 : begin + ap_NS_fsm = ap_ST_fsm_state1431; + end + ap_ST_fsm_state1431 : begin + ap_NS_fsm = ap_ST_fsm_state1432; + end + ap_ST_fsm_state1432 : begin + ap_NS_fsm = ap_ST_fsm_state1433; + end + ap_ST_fsm_state1433 : begin + ap_NS_fsm = ap_ST_fsm_state1434; + end + ap_ST_fsm_state1434 : begin + ap_NS_fsm = ap_ST_fsm_state1435; + end + ap_ST_fsm_state1435 : begin + ap_NS_fsm = ap_ST_fsm_state1436; + end + ap_ST_fsm_state1436 : begin + ap_NS_fsm = ap_ST_fsm_state1437; + end + ap_ST_fsm_state1437 : begin + ap_NS_fsm = ap_ST_fsm_state1438; + end + ap_ST_fsm_state1438 : begin + ap_NS_fsm = ap_ST_fsm_state1439; + end + ap_ST_fsm_state1439 : begin + ap_NS_fsm = ap_ST_fsm_state1440; + end + ap_ST_fsm_state1440 : begin + ap_NS_fsm = ap_ST_fsm_state1441; + end + ap_ST_fsm_state1441 : begin + ap_NS_fsm = ap_ST_fsm_state1442; + end + ap_ST_fsm_state1442 : begin + ap_NS_fsm = ap_ST_fsm_state1443; + end + ap_ST_fsm_state1443 : begin + ap_NS_fsm = ap_ST_fsm_state1444; + end + ap_ST_fsm_state1444 : begin + ap_NS_fsm = ap_ST_fsm_state1445; + end + ap_ST_fsm_state1445 : begin + ap_NS_fsm = ap_ST_fsm_state1446; + end + ap_ST_fsm_state1446 : begin + ap_NS_fsm = ap_ST_fsm_state1447; + end + ap_ST_fsm_state1447 : begin + ap_NS_fsm = ap_ST_fsm_state1448; + end + ap_ST_fsm_state1448 : begin + ap_NS_fsm = ap_ST_fsm_state1449; + end + ap_ST_fsm_state1449 : begin + ap_NS_fsm = ap_ST_fsm_state1450; + end + ap_ST_fsm_state1450 : begin + if (((icmp_ln268_12_fu_83355_p2 == 1'd1) & (ap_ST_fsm_state1450 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1338; + end else begin + ap_NS_fsm = ap_ST_fsm_state1451; + end + end + ap_ST_fsm_state1451 : begin + ap_NS_fsm = ap_ST_fsm_state1452; + end + ap_ST_fsm_state1452 : begin + ap_NS_fsm = ap_ST_fsm_state1453; + end + ap_ST_fsm_state1453 : begin + ap_NS_fsm = ap_ST_fsm_state1454; + end + ap_ST_fsm_state1454 : begin + ap_NS_fsm = ap_ST_fsm_state1455; + end + ap_ST_fsm_state1455 : begin + ap_NS_fsm = ap_ST_fsm_state1456; + end + ap_ST_fsm_state1456 : begin + ap_NS_fsm = ap_ST_fsm_state1457; + end + ap_ST_fsm_state1457 : begin + ap_NS_fsm = ap_ST_fsm_state1458; + end + ap_ST_fsm_state1458 : begin + ap_NS_fsm = ap_ST_fsm_state1459; + end + ap_ST_fsm_state1459 : begin + ap_NS_fsm = ap_ST_fsm_state1460; + end + ap_ST_fsm_state1460 : begin + ap_NS_fsm = ap_ST_fsm_state1461; + end + ap_ST_fsm_state1461 : begin + ap_NS_fsm = ap_ST_fsm_state1462; + end + ap_ST_fsm_state1462 : begin + ap_NS_fsm = ap_ST_fsm_state1463; + end + ap_ST_fsm_state1463 : begin + ap_NS_fsm = ap_ST_fsm_state1464; + end + ap_ST_fsm_state1464 : begin + ap_NS_fsm = ap_ST_fsm_state1465; + end + ap_ST_fsm_state1465 : begin + ap_NS_fsm = ap_ST_fsm_state1466; + end + ap_ST_fsm_state1466 : begin + ap_NS_fsm = ap_ST_fsm_state1467; + end + ap_ST_fsm_state1467 : begin + ap_NS_fsm = ap_ST_fsm_state1468; + end + ap_ST_fsm_state1468 : begin + ap_NS_fsm = ap_ST_fsm_state1469; + end + ap_ST_fsm_state1469 : begin + ap_NS_fsm = ap_ST_fsm_state1470; + end + ap_ST_fsm_state1470 : begin + ap_NS_fsm = ap_ST_fsm_state1471; + end + ap_ST_fsm_state1471 : begin + ap_NS_fsm = ap_ST_fsm_state1472; + end + ap_ST_fsm_state1472 : begin + ap_NS_fsm = ap_ST_fsm_state1473; + end + ap_ST_fsm_state1473 : begin + ap_NS_fsm = ap_ST_fsm_state1474; + end + ap_ST_fsm_state1474 : begin + ap_NS_fsm = ap_ST_fsm_state1475; + end + ap_ST_fsm_state1475 : begin + ap_NS_fsm = ap_ST_fsm_state1476; + end + ap_ST_fsm_state1476 : begin + ap_NS_fsm = ap_ST_fsm_state1477; + end + ap_ST_fsm_state1477 : begin + ap_NS_fsm = ap_ST_fsm_state1478; + end + ap_ST_fsm_state1478 : begin + ap_NS_fsm = ap_ST_fsm_state1479; + end + ap_ST_fsm_state1479 : begin + ap_NS_fsm = ap_ST_fsm_state1480; + end + ap_ST_fsm_state1480 : begin + ap_NS_fsm = ap_ST_fsm_state1481; + end + ap_ST_fsm_state1481 : begin + ap_NS_fsm = ap_ST_fsm_state1482; + end + ap_ST_fsm_state1482 : begin + ap_NS_fsm = ap_ST_fsm_state1483; + end + ap_ST_fsm_state1483 : begin + ap_NS_fsm = ap_ST_fsm_state1484; + end + ap_ST_fsm_state1484 : begin + ap_NS_fsm = ap_ST_fsm_state1485; + end + ap_ST_fsm_state1485 : begin + ap_NS_fsm = ap_ST_fsm_state1486; + end + ap_ST_fsm_state1486 : begin + ap_NS_fsm = ap_ST_fsm_state1414; + end + ap_ST_fsm_state1487 : begin + if (((icmp_ln261_2_fu_83525_p2 == 1'd1) & (ap_ST_fsm_state1487 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1185; + end else begin + ap_NS_fsm = ap_ST_fsm_state1488; + end + end + ap_ST_fsm_state1488 : begin + ap_NS_fsm = ap_ST_fsm_state1489; + end + ap_ST_fsm_state1489 : begin + ap_NS_fsm = ap_ST_fsm_state1490; + end + ap_ST_fsm_state1490 : begin + ap_NS_fsm = ap_ST_fsm_state1491; + end + ap_ST_fsm_state1491 : begin + ap_NS_fsm = ap_ST_fsm_state1492; + end + ap_ST_fsm_state1492 : begin + ap_NS_fsm = ap_ST_fsm_state1493; + end + ap_ST_fsm_state1493 : begin + ap_NS_fsm = ap_ST_fsm_state1494; + end + ap_ST_fsm_state1494 : begin + ap_NS_fsm = ap_ST_fsm_state1495; + end + ap_ST_fsm_state1495 : begin + ap_NS_fsm = ap_ST_fsm_state1496; + end + ap_ST_fsm_state1496 : begin + ap_NS_fsm = ap_ST_fsm_state1497; + end + ap_ST_fsm_state1497 : begin + ap_NS_fsm = ap_ST_fsm_state1498; + end + ap_ST_fsm_state1498 : begin + ap_NS_fsm = ap_ST_fsm_state1499; + end + ap_ST_fsm_state1499 : begin + ap_NS_fsm = ap_ST_fsm_state1500; + end + ap_ST_fsm_state1500 : begin + ap_NS_fsm = ap_ST_fsm_state1501; + end + ap_ST_fsm_state1501 : begin + ap_NS_fsm = ap_ST_fsm_state1502; + end + ap_ST_fsm_state1502 : begin + ap_NS_fsm = ap_ST_fsm_state1503; + end + ap_ST_fsm_state1503 : begin + ap_NS_fsm = ap_ST_fsm_state1504; + end + ap_ST_fsm_state1504 : begin + ap_NS_fsm = ap_ST_fsm_state1505; + end + ap_ST_fsm_state1505 : begin + ap_NS_fsm = ap_ST_fsm_state1506; + end + ap_ST_fsm_state1506 : begin + ap_NS_fsm = ap_ST_fsm_state1507; + end + ap_ST_fsm_state1507 : begin + ap_NS_fsm = ap_ST_fsm_state1508; + end + ap_ST_fsm_state1508 : begin + ap_NS_fsm = ap_ST_fsm_state1509; + end + ap_ST_fsm_state1509 : begin + ap_NS_fsm = ap_ST_fsm_state1510; + end + ap_ST_fsm_state1510 : begin + ap_NS_fsm = ap_ST_fsm_state1511; + end + ap_ST_fsm_state1511 : begin + ap_NS_fsm = ap_ST_fsm_state1512; + end + ap_ST_fsm_state1512 : begin + ap_NS_fsm = ap_ST_fsm_state1513; + end + ap_ST_fsm_state1513 : begin + ap_NS_fsm = ap_ST_fsm_state1514; + end + ap_ST_fsm_state1514 : begin + ap_NS_fsm = ap_ST_fsm_state1515; + end + ap_ST_fsm_state1515 : begin + ap_NS_fsm = ap_ST_fsm_state1516; + end + ap_ST_fsm_state1516 : begin + ap_NS_fsm = ap_ST_fsm_state1517; + end + ap_ST_fsm_state1517 : begin + ap_NS_fsm = ap_ST_fsm_state1518; + end + ap_ST_fsm_state1518 : begin + ap_NS_fsm = ap_ST_fsm_state1519; + end + ap_ST_fsm_state1519 : begin + ap_NS_fsm = ap_ST_fsm_state1520; + end + ap_ST_fsm_state1520 : begin + ap_NS_fsm = ap_ST_fsm_state1521; + end + ap_ST_fsm_state1521 : begin + ap_NS_fsm = ap_ST_fsm_state1522; + end + ap_ST_fsm_state1522 : begin + ap_NS_fsm = ap_ST_fsm_state1523; + end + ap_ST_fsm_state1523 : begin + ap_NS_fsm = ap_ST_fsm_state1524; + end + ap_ST_fsm_state1524 : begin + ap_NS_fsm = ap_ST_fsm_state1525; + end + ap_ST_fsm_state1525 : begin + ap_NS_fsm = ap_ST_fsm_state1526; + end + ap_ST_fsm_state1526 : begin + if (((icmp_ln266_2_fu_83979_p2 == 1'd1) & (icmp_ln268_2_fu_83956_p2 == 1'd1) & (ap_ST_fsm_state1526 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1639; + end else if (((icmp_ln268_2_fu_83956_p2 == 1'd1) & (icmp_ln266_2_fu_83979_p2 == 1'd0) & (ap_ST_fsm_state1526 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1564; + end else begin + ap_NS_fsm = ap_ST_fsm_state1527; + end + end + ap_ST_fsm_state1527 : begin + ap_NS_fsm = ap_ST_fsm_state1528; + end + ap_ST_fsm_state1528 : begin + ap_NS_fsm = ap_ST_fsm_state1529; + end + ap_ST_fsm_state1529 : begin + ap_NS_fsm = ap_ST_fsm_state1530; + end + ap_ST_fsm_state1530 : begin + ap_NS_fsm = ap_ST_fsm_state1531; + end + ap_ST_fsm_state1531 : begin + ap_NS_fsm = ap_ST_fsm_state1532; + end + ap_ST_fsm_state1532 : begin + ap_NS_fsm = ap_ST_fsm_state1533; + end + ap_ST_fsm_state1533 : begin + ap_NS_fsm = ap_ST_fsm_state1534; + end + ap_ST_fsm_state1534 : begin + ap_NS_fsm = ap_ST_fsm_state1535; + end + ap_ST_fsm_state1535 : begin + ap_NS_fsm = ap_ST_fsm_state1536; + end + ap_ST_fsm_state1536 : begin + ap_NS_fsm = ap_ST_fsm_state1537; + end + ap_ST_fsm_state1537 : begin + ap_NS_fsm = ap_ST_fsm_state1538; + end + ap_ST_fsm_state1538 : begin + ap_NS_fsm = ap_ST_fsm_state1539; + end + ap_ST_fsm_state1539 : begin + ap_NS_fsm = ap_ST_fsm_state1540; + end + ap_ST_fsm_state1540 : begin + ap_NS_fsm = ap_ST_fsm_state1541; + end + ap_ST_fsm_state1541 : begin + ap_NS_fsm = ap_ST_fsm_state1542; + end + ap_ST_fsm_state1542 : begin + ap_NS_fsm = ap_ST_fsm_state1543; + end + ap_ST_fsm_state1543 : begin + ap_NS_fsm = ap_ST_fsm_state1544; + end + ap_ST_fsm_state1544 : begin + ap_NS_fsm = ap_ST_fsm_state1545; + end + ap_ST_fsm_state1545 : begin + ap_NS_fsm = ap_ST_fsm_state1546; + end + ap_ST_fsm_state1546 : begin + ap_NS_fsm = ap_ST_fsm_state1547; + end + ap_ST_fsm_state1547 : begin + ap_NS_fsm = ap_ST_fsm_state1548; + end + ap_ST_fsm_state1548 : begin + ap_NS_fsm = ap_ST_fsm_state1549; + end + ap_ST_fsm_state1549 : begin + ap_NS_fsm = ap_ST_fsm_state1550; + end + ap_ST_fsm_state1550 : begin + ap_NS_fsm = ap_ST_fsm_state1551; + end + ap_ST_fsm_state1551 : begin + ap_NS_fsm = ap_ST_fsm_state1552; + end + ap_ST_fsm_state1552 : begin + ap_NS_fsm = ap_ST_fsm_state1553; + end + ap_ST_fsm_state1553 : begin + ap_NS_fsm = ap_ST_fsm_state1554; + end + ap_ST_fsm_state1554 : begin + ap_NS_fsm = ap_ST_fsm_state1555; + end + ap_ST_fsm_state1555 : begin + ap_NS_fsm = ap_ST_fsm_state1556; + end + ap_ST_fsm_state1556 : begin + ap_NS_fsm = ap_ST_fsm_state1557; + end + ap_ST_fsm_state1557 : begin + ap_NS_fsm = ap_ST_fsm_state1558; + end + ap_ST_fsm_state1558 : begin + ap_NS_fsm = ap_ST_fsm_state1559; + end + ap_ST_fsm_state1559 : begin + ap_NS_fsm = ap_ST_fsm_state1560; + end + ap_ST_fsm_state1560 : begin + ap_NS_fsm = ap_ST_fsm_state1561; + end + ap_ST_fsm_state1561 : begin + ap_NS_fsm = ap_ST_fsm_state1562; + end + ap_ST_fsm_state1562 : begin + ap_NS_fsm = ap_ST_fsm_state1563; + end + ap_ST_fsm_state1563 : begin + ap_NS_fsm = ap_ST_fsm_state1489; + end + ap_ST_fsm_state1564 : begin + ap_NS_fsm = ap_ST_fsm_state1565; + end + ap_ST_fsm_state1565 : begin + ap_NS_fsm = ap_ST_fsm_state1566; + end + ap_ST_fsm_state1566 : begin + ap_NS_fsm = ap_ST_fsm_state1567; + end + ap_ST_fsm_state1567 : begin + ap_NS_fsm = ap_ST_fsm_state1568; + end + ap_ST_fsm_state1568 : begin + ap_NS_fsm = ap_ST_fsm_state1569; + end + ap_ST_fsm_state1569 : begin + ap_NS_fsm = ap_ST_fsm_state1570; + end + ap_ST_fsm_state1570 : begin + ap_NS_fsm = ap_ST_fsm_state1571; + end + ap_ST_fsm_state1571 : begin + ap_NS_fsm = ap_ST_fsm_state1572; + end + ap_ST_fsm_state1572 : begin + ap_NS_fsm = ap_ST_fsm_state1573; + end + ap_ST_fsm_state1573 : begin + ap_NS_fsm = ap_ST_fsm_state1574; + end + ap_ST_fsm_state1574 : begin + ap_NS_fsm = ap_ST_fsm_state1575; + end + ap_ST_fsm_state1575 : begin + ap_NS_fsm = ap_ST_fsm_state1576; + end + ap_ST_fsm_state1576 : begin + ap_NS_fsm = ap_ST_fsm_state1577; + end + ap_ST_fsm_state1577 : begin + ap_NS_fsm = ap_ST_fsm_state1578; + end + ap_ST_fsm_state1578 : begin + ap_NS_fsm = ap_ST_fsm_state1579; + end + ap_ST_fsm_state1579 : begin + ap_NS_fsm = ap_ST_fsm_state1580; + end + ap_ST_fsm_state1580 : begin + ap_NS_fsm = ap_ST_fsm_state1581; + end + ap_ST_fsm_state1581 : begin + ap_NS_fsm = ap_ST_fsm_state1582; + end + ap_ST_fsm_state1582 : begin + ap_NS_fsm = ap_ST_fsm_state1583; + end + ap_ST_fsm_state1583 : begin + ap_NS_fsm = ap_ST_fsm_state1584; + end + ap_ST_fsm_state1584 : begin + ap_NS_fsm = ap_ST_fsm_state1585; + end + ap_ST_fsm_state1585 : begin + ap_NS_fsm = ap_ST_fsm_state1586; + end + ap_ST_fsm_state1586 : begin + ap_NS_fsm = ap_ST_fsm_state1587; + end + ap_ST_fsm_state1587 : begin + ap_NS_fsm = ap_ST_fsm_state1588; + end + ap_ST_fsm_state1588 : begin + ap_NS_fsm = ap_ST_fsm_state1589; + end + ap_ST_fsm_state1589 : begin + ap_NS_fsm = ap_ST_fsm_state1590; + end + ap_ST_fsm_state1590 : begin + ap_NS_fsm = ap_ST_fsm_state1591; + end + ap_ST_fsm_state1591 : begin + ap_NS_fsm = ap_ST_fsm_state1592; + end + ap_ST_fsm_state1592 : begin + ap_NS_fsm = ap_ST_fsm_state1593; + end + ap_ST_fsm_state1593 : begin + ap_NS_fsm = ap_ST_fsm_state1594; + end + ap_ST_fsm_state1594 : begin + ap_NS_fsm = ap_ST_fsm_state1595; + end + ap_ST_fsm_state1595 : begin + ap_NS_fsm = ap_ST_fsm_state1596; + end + ap_ST_fsm_state1596 : begin + ap_NS_fsm = ap_ST_fsm_state1597; + end + ap_ST_fsm_state1597 : begin + ap_NS_fsm = ap_ST_fsm_state1598; + end + ap_ST_fsm_state1598 : begin + ap_NS_fsm = ap_ST_fsm_state1599; + end + ap_ST_fsm_state1599 : begin + ap_NS_fsm = ap_ST_fsm_state1600; + end + ap_ST_fsm_state1600 : begin + ap_NS_fsm = ap_ST_fsm_state1601; + end + ap_ST_fsm_state1601 : begin + if (((icmp_ln268_7_fu_84494_p2 == 1'd1) & (ap_ST_fsm_state1601 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1488; + end else begin + ap_NS_fsm = ap_ST_fsm_state1602; + end + end + ap_ST_fsm_state1602 : begin + ap_NS_fsm = ap_ST_fsm_state1603; + end + ap_ST_fsm_state1603 : begin + ap_NS_fsm = ap_ST_fsm_state1604; + end + ap_ST_fsm_state1604 : begin + ap_NS_fsm = ap_ST_fsm_state1605; + end + ap_ST_fsm_state1605 : begin + ap_NS_fsm = ap_ST_fsm_state1606; + end + ap_ST_fsm_state1606 : begin + ap_NS_fsm = ap_ST_fsm_state1607; + end + ap_ST_fsm_state1607 : begin + ap_NS_fsm = ap_ST_fsm_state1608; + end + ap_ST_fsm_state1608 : begin + ap_NS_fsm = ap_ST_fsm_state1609; + end + ap_ST_fsm_state1609 : begin + ap_NS_fsm = ap_ST_fsm_state1610; + end + ap_ST_fsm_state1610 : begin + ap_NS_fsm = ap_ST_fsm_state1611; + end + ap_ST_fsm_state1611 : begin + ap_NS_fsm = ap_ST_fsm_state1612; + end + ap_ST_fsm_state1612 : begin + ap_NS_fsm = ap_ST_fsm_state1613; + end + ap_ST_fsm_state1613 : begin + ap_NS_fsm = ap_ST_fsm_state1614; + end + ap_ST_fsm_state1614 : begin + ap_NS_fsm = ap_ST_fsm_state1615; + end + ap_ST_fsm_state1615 : begin + ap_NS_fsm = ap_ST_fsm_state1616; + end + ap_ST_fsm_state1616 : begin + ap_NS_fsm = ap_ST_fsm_state1617; + end + ap_ST_fsm_state1617 : begin + ap_NS_fsm = ap_ST_fsm_state1618; + end + ap_ST_fsm_state1618 : begin + ap_NS_fsm = ap_ST_fsm_state1619; + end + ap_ST_fsm_state1619 : begin + ap_NS_fsm = ap_ST_fsm_state1620; + end + ap_ST_fsm_state1620 : begin + ap_NS_fsm = ap_ST_fsm_state1621; + end + ap_ST_fsm_state1621 : begin + ap_NS_fsm = ap_ST_fsm_state1622; + end + ap_ST_fsm_state1622 : begin + ap_NS_fsm = ap_ST_fsm_state1623; + end + ap_ST_fsm_state1623 : begin + ap_NS_fsm = ap_ST_fsm_state1624; + end + ap_ST_fsm_state1624 : begin + ap_NS_fsm = ap_ST_fsm_state1625; + end + ap_ST_fsm_state1625 : begin + ap_NS_fsm = ap_ST_fsm_state1626; + end + ap_ST_fsm_state1626 : begin + ap_NS_fsm = ap_ST_fsm_state1627; + end + ap_ST_fsm_state1627 : begin + ap_NS_fsm = ap_ST_fsm_state1628; + end + ap_ST_fsm_state1628 : begin + ap_NS_fsm = ap_ST_fsm_state1629; + end + ap_ST_fsm_state1629 : begin + ap_NS_fsm = ap_ST_fsm_state1630; + end + ap_ST_fsm_state1630 : begin + ap_NS_fsm = ap_ST_fsm_state1631; + end + ap_ST_fsm_state1631 : begin + ap_NS_fsm = ap_ST_fsm_state1632; + end + ap_ST_fsm_state1632 : begin + ap_NS_fsm = ap_ST_fsm_state1633; + end + ap_ST_fsm_state1633 : begin + ap_NS_fsm = ap_ST_fsm_state1634; + end + ap_ST_fsm_state1634 : begin + ap_NS_fsm = ap_ST_fsm_state1635; + end + ap_ST_fsm_state1635 : begin + ap_NS_fsm = ap_ST_fsm_state1636; + end + ap_ST_fsm_state1636 : begin + ap_NS_fsm = ap_ST_fsm_state1637; + end + ap_ST_fsm_state1637 : begin + ap_NS_fsm = ap_ST_fsm_state1638; + end + ap_ST_fsm_state1638 : begin + ap_NS_fsm = ap_ST_fsm_state1564; + end + ap_ST_fsm_state1639 : begin + ap_NS_fsm = ap_ST_fsm_state1640; + end + ap_ST_fsm_state1640 : begin + ap_NS_fsm = ap_ST_fsm_state1641; + end + ap_ST_fsm_state1641 : begin + ap_NS_fsm = ap_ST_fsm_state1642; + end + ap_ST_fsm_state1642 : begin + ap_NS_fsm = ap_ST_fsm_state1643; + end + ap_ST_fsm_state1643 : begin + ap_NS_fsm = ap_ST_fsm_state1644; + end + ap_ST_fsm_state1644 : begin + ap_NS_fsm = ap_ST_fsm_state1645; + end + ap_ST_fsm_state1645 : begin + ap_NS_fsm = ap_ST_fsm_state1646; + end + ap_ST_fsm_state1646 : begin + ap_NS_fsm = ap_ST_fsm_state1647; + end + ap_ST_fsm_state1647 : begin + ap_NS_fsm = ap_ST_fsm_state1648; + end + ap_ST_fsm_state1648 : begin + ap_NS_fsm = ap_ST_fsm_state1649; + end + ap_ST_fsm_state1649 : begin + ap_NS_fsm = ap_ST_fsm_state1650; + end + ap_ST_fsm_state1650 : begin + ap_NS_fsm = ap_ST_fsm_state1651; + end + ap_ST_fsm_state1651 : begin + ap_NS_fsm = ap_ST_fsm_state1652; + end + ap_ST_fsm_state1652 : begin + ap_NS_fsm = ap_ST_fsm_state1653; + end + ap_ST_fsm_state1653 : begin + ap_NS_fsm = ap_ST_fsm_state1654; + end + ap_ST_fsm_state1654 : begin + ap_NS_fsm = ap_ST_fsm_state1655; + end + ap_ST_fsm_state1655 : begin + ap_NS_fsm = ap_ST_fsm_state1656; + end + ap_ST_fsm_state1656 : begin + ap_NS_fsm = ap_ST_fsm_state1657; + end + ap_ST_fsm_state1657 : begin + ap_NS_fsm = ap_ST_fsm_state1658; + end + ap_ST_fsm_state1658 : begin + ap_NS_fsm = ap_ST_fsm_state1659; + end + ap_ST_fsm_state1659 : begin + ap_NS_fsm = ap_ST_fsm_state1660; + end + ap_ST_fsm_state1660 : begin + ap_NS_fsm = ap_ST_fsm_state1661; + end + ap_ST_fsm_state1661 : begin + ap_NS_fsm = ap_ST_fsm_state1662; + end + ap_ST_fsm_state1662 : begin + ap_NS_fsm = ap_ST_fsm_state1663; + end + ap_ST_fsm_state1663 : begin + ap_NS_fsm = ap_ST_fsm_state1664; + end + ap_ST_fsm_state1664 : begin + ap_NS_fsm = ap_ST_fsm_state1665; + end + ap_ST_fsm_state1665 : begin + ap_NS_fsm = ap_ST_fsm_state1666; + end + ap_ST_fsm_state1666 : begin + ap_NS_fsm = ap_ST_fsm_state1667; + end + ap_ST_fsm_state1667 : begin + ap_NS_fsm = ap_ST_fsm_state1668; + end + ap_ST_fsm_state1668 : begin + ap_NS_fsm = ap_ST_fsm_state1669; + end + ap_ST_fsm_state1669 : begin + ap_NS_fsm = ap_ST_fsm_state1670; + end + ap_ST_fsm_state1670 : begin + ap_NS_fsm = ap_ST_fsm_state1671; + end + ap_ST_fsm_state1671 : begin + ap_NS_fsm = ap_ST_fsm_state1672; + end + ap_ST_fsm_state1672 : begin + ap_NS_fsm = ap_ST_fsm_state1673; + end + ap_ST_fsm_state1673 : begin + ap_NS_fsm = ap_ST_fsm_state1674; + end + ap_ST_fsm_state1674 : begin + ap_NS_fsm = ap_ST_fsm_state1675; + end + ap_ST_fsm_state1675 : begin + ap_NS_fsm = ap_ST_fsm_state1676; + end + ap_ST_fsm_state1676 : begin + if (((icmp_ln266_6_fu_84994_p2 == 1'd1) & (icmp_ln268_9_fu_84971_p2 == 1'd1) & (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1487; + end else if (((icmp_ln268_9_fu_84971_p2 == 1'd1) & (icmp_ln266_6_fu_84994_p2 == 1'd0) & (ap_ST_fsm_state1676 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1714; + end else begin + ap_NS_fsm = ap_ST_fsm_state1677; + end + end + ap_ST_fsm_state1677 : begin + ap_NS_fsm = ap_ST_fsm_state1678; + end + ap_ST_fsm_state1678 : begin + ap_NS_fsm = ap_ST_fsm_state1679; + end + ap_ST_fsm_state1679 : begin + ap_NS_fsm = ap_ST_fsm_state1680; + end + ap_ST_fsm_state1680 : begin + ap_NS_fsm = ap_ST_fsm_state1681; + end + ap_ST_fsm_state1681 : begin + ap_NS_fsm = ap_ST_fsm_state1682; + end + ap_ST_fsm_state1682 : begin + ap_NS_fsm = ap_ST_fsm_state1683; + end + ap_ST_fsm_state1683 : begin + ap_NS_fsm = ap_ST_fsm_state1684; + end + ap_ST_fsm_state1684 : begin + ap_NS_fsm = ap_ST_fsm_state1685; + end + ap_ST_fsm_state1685 : begin + ap_NS_fsm = ap_ST_fsm_state1686; + end + ap_ST_fsm_state1686 : begin + ap_NS_fsm = ap_ST_fsm_state1687; + end + ap_ST_fsm_state1687 : begin + ap_NS_fsm = ap_ST_fsm_state1688; + end + ap_ST_fsm_state1688 : begin + ap_NS_fsm = ap_ST_fsm_state1689; + end + ap_ST_fsm_state1689 : begin + ap_NS_fsm = ap_ST_fsm_state1690; + end + ap_ST_fsm_state1690 : begin + ap_NS_fsm = ap_ST_fsm_state1691; + end + ap_ST_fsm_state1691 : begin + ap_NS_fsm = ap_ST_fsm_state1692; + end + ap_ST_fsm_state1692 : begin + ap_NS_fsm = ap_ST_fsm_state1693; + end + ap_ST_fsm_state1693 : begin + ap_NS_fsm = ap_ST_fsm_state1694; + end + ap_ST_fsm_state1694 : begin + ap_NS_fsm = ap_ST_fsm_state1695; + end + ap_ST_fsm_state1695 : begin + ap_NS_fsm = ap_ST_fsm_state1696; + end + ap_ST_fsm_state1696 : begin + ap_NS_fsm = ap_ST_fsm_state1697; + end + ap_ST_fsm_state1697 : begin + ap_NS_fsm = ap_ST_fsm_state1698; + end + ap_ST_fsm_state1698 : begin + ap_NS_fsm = ap_ST_fsm_state1699; + end + ap_ST_fsm_state1699 : begin + ap_NS_fsm = ap_ST_fsm_state1700; + end + ap_ST_fsm_state1700 : begin + ap_NS_fsm = ap_ST_fsm_state1701; + end + ap_ST_fsm_state1701 : begin + ap_NS_fsm = ap_ST_fsm_state1702; + end + ap_ST_fsm_state1702 : begin + ap_NS_fsm = ap_ST_fsm_state1703; + end + ap_ST_fsm_state1703 : begin + ap_NS_fsm = ap_ST_fsm_state1704; + end + ap_ST_fsm_state1704 : begin + ap_NS_fsm = ap_ST_fsm_state1705; + end + ap_ST_fsm_state1705 : begin + ap_NS_fsm = ap_ST_fsm_state1706; + end + ap_ST_fsm_state1706 : begin + ap_NS_fsm = ap_ST_fsm_state1707; + end + ap_ST_fsm_state1707 : begin + ap_NS_fsm = ap_ST_fsm_state1708; + end + ap_ST_fsm_state1708 : begin + ap_NS_fsm = ap_ST_fsm_state1709; + end + ap_ST_fsm_state1709 : begin + ap_NS_fsm = ap_ST_fsm_state1710; + end + ap_ST_fsm_state1710 : begin + ap_NS_fsm = ap_ST_fsm_state1711; + end + ap_ST_fsm_state1711 : begin + ap_NS_fsm = ap_ST_fsm_state1712; + end + ap_ST_fsm_state1712 : begin + ap_NS_fsm = ap_ST_fsm_state1713; + end + ap_ST_fsm_state1713 : begin + ap_NS_fsm = ap_ST_fsm_state1640; + end + ap_ST_fsm_state1714 : begin + ap_NS_fsm = ap_ST_fsm_state1715; + end + ap_ST_fsm_state1715 : begin + ap_NS_fsm = ap_ST_fsm_state1716; + end + ap_ST_fsm_state1716 : begin + ap_NS_fsm = ap_ST_fsm_state1717; + end + ap_ST_fsm_state1717 : begin + ap_NS_fsm = ap_ST_fsm_state1718; + end + ap_ST_fsm_state1718 : begin + ap_NS_fsm = ap_ST_fsm_state1719; + end + ap_ST_fsm_state1719 : begin + ap_NS_fsm = ap_ST_fsm_state1720; + end + ap_ST_fsm_state1720 : begin + ap_NS_fsm = ap_ST_fsm_state1721; + end + ap_ST_fsm_state1721 : begin + ap_NS_fsm = ap_ST_fsm_state1722; + end + ap_ST_fsm_state1722 : begin + ap_NS_fsm = ap_ST_fsm_state1723; + end + ap_ST_fsm_state1723 : begin + ap_NS_fsm = ap_ST_fsm_state1724; + end + ap_ST_fsm_state1724 : begin + ap_NS_fsm = ap_ST_fsm_state1725; + end + ap_ST_fsm_state1725 : begin + ap_NS_fsm = ap_ST_fsm_state1726; + end + ap_ST_fsm_state1726 : begin + ap_NS_fsm = ap_ST_fsm_state1727; + end + ap_ST_fsm_state1727 : begin + ap_NS_fsm = ap_ST_fsm_state1728; + end + ap_ST_fsm_state1728 : begin + ap_NS_fsm = ap_ST_fsm_state1729; + end + ap_ST_fsm_state1729 : begin + ap_NS_fsm = ap_ST_fsm_state1730; + end + ap_ST_fsm_state1730 : begin + ap_NS_fsm = ap_ST_fsm_state1731; + end + ap_ST_fsm_state1731 : begin + ap_NS_fsm = ap_ST_fsm_state1732; + end + ap_ST_fsm_state1732 : begin + ap_NS_fsm = ap_ST_fsm_state1733; + end + ap_ST_fsm_state1733 : begin + ap_NS_fsm = ap_ST_fsm_state1734; + end + ap_ST_fsm_state1734 : begin + ap_NS_fsm = ap_ST_fsm_state1735; + end + ap_ST_fsm_state1735 : begin + ap_NS_fsm = ap_ST_fsm_state1736; + end + ap_ST_fsm_state1736 : begin + ap_NS_fsm = ap_ST_fsm_state1737; + end + ap_ST_fsm_state1737 : begin + ap_NS_fsm = ap_ST_fsm_state1738; + end + ap_ST_fsm_state1738 : begin + ap_NS_fsm = ap_ST_fsm_state1739; + end + ap_ST_fsm_state1739 : begin + ap_NS_fsm = ap_ST_fsm_state1740; + end + ap_ST_fsm_state1740 : begin + ap_NS_fsm = ap_ST_fsm_state1741; + end + ap_ST_fsm_state1741 : begin + ap_NS_fsm = ap_ST_fsm_state1742; + end + ap_ST_fsm_state1742 : begin + ap_NS_fsm = ap_ST_fsm_state1743; + end + ap_ST_fsm_state1743 : begin + ap_NS_fsm = ap_ST_fsm_state1744; + end + ap_ST_fsm_state1744 : begin + ap_NS_fsm = ap_ST_fsm_state1745; + end + ap_ST_fsm_state1745 : begin + ap_NS_fsm = ap_ST_fsm_state1746; + end + ap_ST_fsm_state1746 : begin + ap_NS_fsm = ap_ST_fsm_state1747; + end + ap_ST_fsm_state1747 : begin + ap_NS_fsm = ap_ST_fsm_state1748; + end + ap_ST_fsm_state1748 : begin + ap_NS_fsm = ap_ST_fsm_state1749; + end + ap_ST_fsm_state1749 : begin + ap_NS_fsm = ap_ST_fsm_state1750; + end + ap_ST_fsm_state1750 : begin + if (((icmp_ln268_14_fu_85443_p2 == 1'd1) & (ap_ST_fsm_state1750 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1639; + end else begin + ap_NS_fsm = ap_ST_fsm_state1751; + end + end + ap_ST_fsm_state1751 : begin + ap_NS_fsm = ap_ST_fsm_state1752; + end + ap_ST_fsm_state1752 : begin + ap_NS_fsm = ap_ST_fsm_state1753; + end + ap_ST_fsm_state1753 : begin + ap_NS_fsm = ap_ST_fsm_state1754; + end + ap_ST_fsm_state1754 : begin + ap_NS_fsm = ap_ST_fsm_state1755; + end + ap_ST_fsm_state1755 : begin + ap_NS_fsm = ap_ST_fsm_state1756; + end + ap_ST_fsm_state1756 : begin + ap_NS_fsm = ap_ST_fsm_state1757; + end + ap_ST_fsm_state1757 : begin + ap_NS_fsm = ap_ST_fsm_state1758; + end + ap_ST_fsm_state1758 : begin + ap_NS_fsm = ap_ST_fsm_state1759; + end + ap_ST_fsm_state1759 : begin + ap_NS_fsm = ap_ST_fsm_state1760; + end + ap_ST_fsm_state1760 : begin + ap_NS_fsm = ap_ST_fsm_state1761; + end + ap_ST_fsm_state1761 : begin + ap_NS_fsm = ap_ST_fsm_state1762; + end + ap_ST_fsm_state1762 : begin + ap_NS_fsm = ap_ST_fsm_state1763; + end + ap_ST_fsm_state1763 : begin + ap_NS_fsm = ap_ST_fsm_state1764; + end + ap_ST_fsm_state1764 : begin + ap_NS_fsm = ap_ST_fsm_state1765; + end + ap_ST_fsm_state1765 : begin + ap_NS_fsm = ap_ST_fsm_state1766; + end + ap_ST_fsm_state1766 : begin + ap_NS_fsm = ap_ST_fsm_state1767; + end + ap_ST_fsm_state1767 : begin + ap_NS_fsm = ap_ST_fsm_state1768; + end + ap_ST_fsm_state1768 : begin + ap_NS_fsm = ap_ST_fsm_state1769; + end + ap_ST_fsm_state1769 : begin + ap_NS_fsm = ap_ST_fsm_state1770; + end + ap_ST_fsm_state1770 : begin + ap_NS_fsm = ap_ST_fsm_state1771; + end + ap_ST_fsm_state1771 : begin + ap_NS_fsm = ap_ST_fsm_state1772; + end + ap_ST_fsm_state1772 : begin + ap_NS_fsm = ap_ST_fsm_state1773; + end + ap_ST_fsm_state1773 : begin + ap_NS_fsm = ap_ST_fsm_state1774; + end + ap_ST_fsm_state1774 : begin + ap_NS_fsm = ap_ST_fsm_state1775; + end + ap_ST_fsm_state1775 : begin + ap_NS_fsm = ap_ST_fsm_state1776; + end + ap_ST_fsm_state1776 : begin + ap_NS_fsm = ap_ST_fsm_state1777; + end + ap_ST_fsm_state1777 : begin + ap_NS_fsm = ap_ST_fsm_state1778; + end + ap_ST_fsm_state1778 : begin + ap_NS_fsm = ap_ST_fsm_state1779; + end + ap_ST_fsm_state1779 : begin + ap_NS_fsm = ap_ST_fsm_state1780; + end + ap_ST_fsm_state1780 : begin + ap_NS_fsm = ap_ST_fsm_state1781; + end + ap_ST_fsm_state1781 : begin + ap_NS_fsm = ap_ST_fsm_state1782; + end + ap_ST_fsm_state1782 : begin + ap_NS_fsm = ap_ST_fsm_state1783; + end + ap_ST_fsm_state1783 : begin + ap_NS_fsm = ap_ST_fsm_state1784; + end + ap_ST_fsm_state1784 : begin + ap_NS_fsm = ap_ST_fsm_state1785; + end + ap_ST_fsm_state1785 : begin + ap_NS_fsm = ap_ST_fsm_state1786; + end + ap_ST_fsm_state1786 : begin + ap_NS_fsm = ap_ST_fsm_state1714; + end + ap_ST_fsm_state1787 : begin + if (((icmp_ln259_1_fu_85608_p2 == 1'd1) & (ap_ST_fsm_state1787 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1184; + end else begin + ap_NS_fsm = ap_ST_fsm_state1788; + end + end + ap_ST_fsm_state1788 : begin + if (((icmp_ln261_1_fu_85740_p2 == 1'd1) & (ap_ST_fsm_state1788 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2088; + end else begin + ap_NS_fsm = ap_ST_fsm_state1789; + end + end + ap_ST_fsm_state1789 : begin + ap_NS_fsm = ap_ST_fsm_state1790; + end + ap_ST_fsm_state1790 : begin + ap_NS_fsm = ap_ST_fsm_state1791; + end + ap_ST_fsm_state1791 : begin + ap_NS_fsm = ap_ST_fsm_state1792; + end + ap_ST_fsm_state1792 : begin + ap_NS_fsm = ap_ST_fsm_state1793; + end + ap_ST_fsm_state1793 : begin + ap_NS_fsm = ap_ST_fsm_state1794; + end + ap_ST_fsm_state1794 : begin + ap_NS_fsm = ap_ST_fsm_state1795; + end + ap_ST_fsm_state1795 : begin + ap_NS_fsm = ap_ST_fsm_state1796; + end + ap_ST_fsm_state1796 : begin + ap_NS_fsm = ap_ST_fsm_state1797; + end + ap_ST_fsm_state1797 : begin + ap_NS_fsm = ap_ST_fsm_state1798; + end + ap_ST_fsm_state1798 : begin + ap_NS_fsm = ap_ST_fsm_state1799; + end + ap_ST_fsm_state1799 : begin + ap_NS_fsm = ap_ST_fsm_state1800; + end + ap_ST_fsm_state1800 : begin + ap_NS_fsm = ap_ST_fsm_state1801; + end + ap_ST_fsm_state1801 : begin + ap_NS_fsm = ap_ST_fsm_state1802; + end + ap_ST_fsm_state1802 : begin + ap_NS_fsm = ap_ST_fsm_state1803; + end + ap_ST_fsm_state1803 : begin + ap_NS_fsm = ap_ST_fsm_state1804; + end + ap_ST_fsm_state1804 : begin + ap_NS_fsm = ap_ST_fsm_state1805; + end + ap_ST_fsm_state1805 : begin + ap_NS_fsm = ap_ST_fsm_state1806; + end + ap_ST_fsm_state1806 : begin + ap_NS_fsm = ap_ST_fsm_state1807; + end + ap_ST_fsm_state1807 : begin + ap_NS_fsm = ap_ST_fsm_state1808; + end + ap_ST_fsm_state1808 : begin + ap_NS_fsm = ap_ST_fsm_state1809; + end + ap_ST_fsm_state1809 : begin + ap_NS_fsm = ap_ST_fsm_state1810; + end + ap_ST_fsm_state1810 : begin + ap_NS_fsm = ap_ST_fsm_state1811; + end + ap_ST_fsm_state1811 : begin + ap_NS_fsm = ap_ST_fsm_state1812; + end + ap_ST_fsm_state1812 : begin + ap_NS_fsm = ap_ST_fsm_state1813; + end + ap_ST_fsm_state1813 : begin + ap_NS_fsm = ap_ST_fsm_state1814; + end + ap_ST_fsm_state1814 : begin + ap_NS_fsm = ap_ST_fsm_state1815; + end + ap_ST_fsm_state1815 : begin + ap_NS_fsm = ap_ST_fsm_state1816; + end + ap_ST_fsm_state1816 : begin + ap_NS_fsm = ap_ST_fsm_state1817; + end + ap_ST_fsm_state1817 : begin + ap_NS_fsm = ap_ST_fsm_state1818; + end + ap_ST_fsm_state1818 : begin + ap_NS_fsm = ap_ST_fsm_state1819; + end + ap_ST_fsm_state1819 : begin + ap_NS_fsm = ap_ST_fsm_state1820; + end + ap_ST_fsm_state1820 : begin + ap_NS_fsm = ap_ST_fsm_state1821; + end + ap_ST_fsm_state1821 : begin + ap_NS_fsm = ap_ST_fsm_state1822; + end + ap_ST_fsm_state1822 : begin + ap_NS_fsm = ap_ST_fsm_state1823; + end + ap_ST_fsm_state1823 : begin + ap_NS_fsm = ap_ST_fsm_state1824; + end + ap_ST_fsm_state1824 : begin + ap_NS_fsm = ap_ST_fsm_state1825; + end + ap_ST_fsm_state1825 : begin + ap_NS_fsm = ap_ST_fsm_state1826; + end + ap_ST_fsm_state1826 : begin + ap_NS_fsm = ap_ST_fsm_state1827; + end + ap_ST_fsm_state1827 : begin + if (((icmp_ln266_1_fu_86235_p2 == 1'd1) & (icmp_ln268_1_fu_86212_p2 == 1'd1) & (ap_ST_fsm_state1827 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1940; + end else if (((icmp_ln268_1_fu_86212_p2 == 1'd1) & (icmp_ln266_1_fu_86235_p2 == 1'd0) & (ap_ST_fsm_state1827 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1865; + end else begin + ap_NS_fsm = ap_ST_fsm_state1828; + end + end + ap_ST_fsm_state1828 : begin + ap_NS_fsm = ap_ST_fsm_state1829; + end + ap_ST_fsm_state1829 : begin + ap_NS_fsm = ap_ST_fsm_state1830; + end + ap_ST_fsm_state1830 : begin + ap_NS_fsm = ap_ST_fsm_state1831; + end + ap_ST_fsm_state1831 : begin + ap_NS_fsm = ap_ST_fsm_state1832; + end + ap_ST_fsm_state1832 : begin + ap_NS_fsm = ap_ST_fsm_state1833; + end + ap_ST_fsm_state1833 : begin + ap_NS_fsm = ap_ST_fsm_state1834; + end + ap_ST_fsm_state1834 : begin + ap_NS_fsm = ap_ST_fsm_state1835; + end + ap_ST_fsm_state1835 : begin + ap_NS_fsm = ap_ST_fsm_state1836; + end + ap_ST_fsm_state1836 : begin + ap_NS_fsm = ap_ST_fsm_state1837; + end + ap_ST_fsm_state1837 : begin + ap_NS_fsm = ap_ST_fsm_state1838; + end + ap_ST_fsm_state1838 : begin + ap_NS_fsm = ap_ST_fsm_state1839; + end + ap_ST_fsm_state1839 : begin + ap_NS_fsm = ap_ST_fsm_state1840; + end + ap_ST_fsm_state1840 : begin + ap_NS_fsm = ap_ST_fsm_state1841; + end + ap_ST_fsm_state1841 : begin + ap_NS_fsm = ap_ST_fsm_state1842; + end + ap_ST_fsm_state1842 : begin + ap_NS_fsm = ap_ST_fsm_state1843; + end + ap_ST_fsm_state1843 : begin + ap_NS_fsm = ap_ST_fsm_state1844; + end + ap_ST_fsm_state1844 : begin + ap_NS_fsm = ap_ST_fsm_state1845; + end + ap_ST_fsm_state1845 : begin + ap_NS_fsm = ap_ST_fsm_state1846; + end + ap_ST_fsm_state1846 : begin + ap_NS_fsm = ap_ST_fsm_state1847; + end + ap_ST_fsm_state1847 : begin + ap_NS_fsm = ap_ST_fsm_state1848; + end + ap_ST_fsm_state1848 : begin + ap_NS_fsm = ap_ST_fsm_state1849; + end + ap_ST_fsm_state1849 : begin + ap_NS_fsm = ap_ST_fsm_state1850; + end + ap_ST_fsm_state1850 : begin + ap_NS_fsm = ap_ST_fsm_state1851; + end + ap_ST_fsm_state1851 : begin + ap_NS_fsm = ap_ST_fsm_state1852; + end + ap_ST_fsm_state1852 : begin + ap_NS_fsm = ap_ST_fsm_state1853; + end + ap_ST_fsm_state1853 : begin + ap_NS_fsm = ap_ST_fsm_state1854; + end + ap_ST_fsm_state1854 : begin + ap_NS_fsm = ap_ST_fsm_state1855; + end + ap_ST_fsm_state1855 : begin + ap_NS_fsm = ap_ST_fsm_state1856; + end + ap_ST_fsm_state1856 : begin + ap_NS_fsm = ap_ST_fsm_state1857; + end + ap_ST_fsm_state1857 : begin + ap_NS_fsm = ap_ST_fsm_state1858; + end + ap_ST_fsm_state1858 : begin + ap_NS_fsm = ap_ST_fsm_state1859; + end + ap_ST_fsm_state1859 : begin + ap_NS_fsm = ap_ST_fsm_state1860; + end + ap_ST_fsm_state1860 : begin + ap_NS_fsm = ap_ST_fsm_state1861; + end + ap_ST_fsm_state1861 : begin + ap_NS_fsm = ap_ST_fsm_state1862; + end + ap_ST_fsm_state1862 : begin + ap_NS_fsm = ap_ST_fsm_state1863; + end + ap_ST_fsm_state1863 : begin + ap_NS_fsm = ap_ST_fsm_state1864; + end + ap_ST_fsm_state1864 : begin + ap_NS_fsm = ap_ST_fsm_state1790; + end + ap_ST_fsm_state1865 : begin + ap_NS_fsm = ap_ST_fsm_state1866; + end + ap_ST_fsm_state1866 : begin + ap_NS_fsm = ap_ST_fsm_state1867; + end + ap_ST_fsm_state1867 : begin + ap_NS_fsm = ap_ST_fsm_state1868; + end + ap_ST_fsm_state1868 : begin + ap_NS_fsm = ap_ST_fsm_state1869; + end + ap_ST_fsm_state1869 : begin + ap_NS_fsm = ap_ST_fsm_state1870; + end + ap_ST_fsm_state1870 : begin + ap_NS_fsm = ap_ST_fsm_state1871; + end + ap_ST_fsm_state1871 : begin + ap_NS_fsm = ap_ST_fsm_state1872; + end + ap_ST_fsm_state1872 : begin + ap_NS_fsm = ap_ST_fsm_state1873; + end + ap_ST_fsm_state1873 : begin + ap_NS_fsm = ap_ST_fsm_state1874; + end + ap_ST_fsm_state1874 : begin + ap_NS_fsm = ap_ST_fsm_state1875; + end + ap_ST_fsm_state1875 : begin + ap_NS_fsm = ap_ST_fsm_state1876; + end + ap_ST_fsm_state1876 : begin + ap_NS_fsm = ap_ST_fsm_state1877; + end + ap_ST_fsm_state1877 : begin + ap_NS_fsm = ap_ST_fsm_state1878; + end + ap_ST_fsm_state1878 : begin + ap_NS_fsm = ap_ST_fsm_state1879; + end + ap_ST_fsm_state1879 : begin + ap_NS_fsm = ap_ST_fsm_state1880; + end + ap_ST_fsm_state1880 : begin + ap_NS_fsm = ap_ST_fsm_state1881; + end + ap_ST_fsm_state1881 : begin + ap_NS_fsm = ap_ST_fsm_state1882; + end + ap_ST_fsm_state1882 : begin + ap_NS_fsm = ap_ST_fsm_state1883; + end + ap_ST_fsm_state1883 : begin + ap_NS_fsm = ap_ST_fsm_state1884; + end + ap_ST_fsm_state1884 : begin + ap_NS_fsm = ap_ST_fsm_state1885; + end + ap_ST_fsm_state1885 : begin + ap_NS_fsm = ap_ST_fsm_state1886; + end + ap_ST_fsm_state1886 : begin + ap_NS_fsm = ap_ST_fsm_state1887; + end + ap_ST_fsm_state1887 : begin + ap_NS_fsm = ap_ST_fsm_state1888; + end + ap_ST_fsm_state1888 : begin + ap_NS_fsm = ap_ST_fsm_state1889; + end + ap_ST_fsm_state1889 : begin + ap_NS_fsm = ap_ST_fsm_state1890; + end + ap_ST_fsm_state1890 : begin + ap_NS_fsm = ap_ST_fsm_state1891; + end + ap_ST_fsm_state1891 : begin + ap_NS_fsm = ap_ST_fsm_state1892; + end + ap_ST_fsm_state1892 : begin + ap_NS_fsm = ap_ST_fsm_state1893; + end + ap_ST_fsm_state1893 : begin + ap_NS_fsm = ap_ST_fsm_state1894; + end + ap_ST_fsm_state1894 : begin + ap_NS_fsm = ap_ST_fsm_state1895; + end + ap_ST_fsm_state1895 : begin + ap_NS_fsm = ap_ST_fsm_state1896; + end + ap_ST_fsm_state1896 : begin + ap_NS_fsm = ap_ST_fsm_state1897; + end + ap_ST_fsm_state1897 : begin + ap_NS_fsm = ap_ST_fsm_state1898; + end + ap_ST_fsm_state1898 : begin + ap_NS_fsm = ap_ST_fsm_state1899; + end + ap_ST_fsm_state1899 : begin + ap_NS_fsm = ap_ST_fsm_state1900; + end + ap_ST_fsm_state1900 : begin + ap_NS_fsm = ap_ST_fsm_state1901; + end + ap_ST_fsm_state1901 : begin + ap_NS_fsm = ap_ST_fsm_state1902; + end + ap_ST_fsm_state1902 : begin + if (((icmp_ln268_6_fu_86750_p2 == 1'd1) & (ap_ST_fsm_state1902 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1789; + end else begin + ap_NS_fsm = ap_ST_fsm_state1903; + end + end + ap_ST_fsm_state1903 : begin + ap_NS_fsm = ap_ST_fsm_state1904; + end + ap_ST_fsm_state1904 : begin + ap_NS_fsm = ap_ST_fsm_state1905; + end + ap_ST_fsm_state1905 : begin + ap_NS_fsm = ap_ST_fsm_state1906; + end + ap_ST_fsm_state1906 : begin + ap_NS_fsm = ap_ST_fsm_state1907; + end + ap_ST_fsm_state1907 : begin + ap_NS_fsm = ap_ST_fsm_state1908; + end + ap_ST_fsm_state1908 : begin + ap_NS_fsm = ap_ST_fsm_state1909; + end + ap_ST_fsm_state1909 : begin + ap_NS_fsm = ap_ST_fsm_state1910; + end + ap_ST_fsm_state1910 : begin + ap_NS_fsm = ap_ST_fsm_state1911; + end + ap_ST_fsm_state1911 : begin + ap_NS_fsm = ap_ST_fsm_state1912; + end + ap_ST_fsm_state1912 : begin + ap_NS_fsm = ap_ST_fsm_state1913; + end + ap_ST_fsm_state1913 : begin + ap_NS_fsm = ap_ST_fsm_state1914; + end + ap_ST_fsm_state1914 : begin + ap_NS_fsm = ap_ST_fsm_state1915; + end + ap_ST_fsm_state1915 : begin + ap_NS_fsm = ap_ST_fsm_state1916; + end + ap_ST_fsm_state1916 : begin + ap_NS_fsm = ap_ST_fsm_state1917; + end + ap_ST_fsm_state1917 : begin + ap_NS_fsm = ap_ST_fsm_state1918; + end + ap_ST_fsm_state1918 : begin + ap_NS_fsm = ap_ST_fsm_state1919; + end + ap_ST_fsm_state1919 : begin + ap_NS_fsm = ap_ST_fsm_state1920; + end + ap_ST_fsm_state1920 : begin + ap_NS_fsm = ap_ST_fsm_state1921; + end + ap_ST_fsm_state1921 : begin + ap_NS_fsm = ap_ST_fsm_state1922; + end + ap_ST_fsm_state1922 : begin + ap_NS_fsm = ap_ST_fsm_state1923; + end + ap_ST_fsm_state1923 : begin + ap_NS_fsm = ap_ST_fsm_state1924; + end + ap_ST_fsm_state1924 : begin + ap_NS_fsm = ap_ST_fsm_state1925; + end + ap_ST_fsm_state1925 : begin + ap_NS_fsm = ap_ST_fsm_state1926; + end + ap_ST_fsm_state1926 : begin + ap_NS_fsm = ap_ST_fsm_state1927; + end + ap_ST_fsm_state1927 : begin + ap_NS_fsm = ap_ST_fsm_state1928; + end + ap_ST_fsm_state1928 : begin + ap_NS_fsm = ap_ST_fsm_state1929; + end + ap_ST_fsm_state1929 : begin + ap_NS_fsm = ap_ST_fsm_state1930; + end + ap_ST_fsm_state1930 : begin + ap_NS_fsm = ap_ST_fsm_state1931; + end + ap_ST_fsm_state1931 : begin + ap_NS_fsm = ap_ST_fsm_state1932; + end + ap_ST_fsm_state1932 : begin + ap_NS_fsm = ap_ST_fsm_state1933; + end + ap_ST_fsm_state1933 : begin + ap_NS_fsm = ap_ST_fsm_state1934; + end + ap_ST_fsm_state1934 : begin + ap_NS_fsm = ap_ST_fsm_state1935; + end + ap_ST_fsm_state1935 : begin + ap_NS_fsm = ap_ST_fsm_state1936; + end + ap_ST_fsm_state1936 : begin + ap_NS_fsm = ap_ST_fsm_state1937; + end + ap_ST_fsm_state1937 : begin + ap_NS_fsm = ap_ST_fsm_state1938; + end + ap_ST_fsm_state1938 : begin + ap_NS_fsm = ap_ST_fsm_state1939; + end + ap_ST_fsm_state1939 : begin + ap_NS_fsm = ap_ST_fsm_state1865; + end + ap_ST_fsm_state1940 : begin + ap_NS_fsm = ap_ST_fsm_state1941; + end + ap_ST_fsm_state1941 : begin + ap_NS_fsm = ap_ST_fsm_state1942; + end + ap_ST_fsm_state1942 : begin + ap_NS_fsm = ap_ST_fsm_state1943; + end + ap_ST_fsm_state1943 : begin + ap_NS_fsm = ap_ST_fsm_state1944; + end + ap_ST_fsm_state1944 : begin + ap_NS_fsm = ap_ST_fsm_state1945; + end + ap_ST_fsm_state1945 : begin + ap_NS_fsm = ap_ST_fsm_state1946; + end + ap_ST_fsm_state1946 : begin + ap_NS_fsm = ap_ST_fsm_state1947; + end + ap_ST_fsm_state1947 : begin + ap_NS_fsm = ap_ST_fsm_state1948; + end + ap_ST_fsm_state1948 : begin + ap_NS_fsm = ap_ST_fsm_state1949; + end + ap_ST_fsm_state1949 : begin + ap_NS_fsm = ap_ST_fsm_state1950; + end + ap_ST_fsm_state1950 : begin + ap_NS_fsm = ap_ST_fsm_state1951; + end + ap_ST_fsm_state1951 : begin + ap_NS_fsm = ap_ST_fsm_state1952; + end + ap_ST_fsm_state1952 : begin + ap_NS_fsm = ap_ST_fsm_state1953; + end + ap_ST_fsm_state1953 : begin + ap_NS_fsm = ap_ST_fsm_state1954; + end + ap_ST_fsm_state1954 : begin + ap_NS_fsm = ap_ST_fsm_state1955; + end + ap_ST_fsm_state1955 : begin + ap_NS_fsm = ap_ST_fsm_state1956; + end + ap_ST_fsm_state1956 : begin + ap_NS_fsm = ap_ST_fsm_state1957; + end + ap_ST_fsm_state1957 : begin + ap_NS_fsm = ap_ST_fsm_state1958; + end + ap_ST_fsm_state1958 : begin + ap_NS_fsm = ap_ST_fsm_state1959; + end + ap_ST_fsm_state1959 : begin + ap_NS_fsm = ap_ST_fsm_state1960; + end + ap_ST_fsm_state1960 : begin + ap_NS_fsm = ap_ST_fsm_state1961; + end + ap_ST_fsm_state1961 : begin + ap_NS_fsm = ap_ST_fsm_state1962; + end + ap_ST_fsm_state1962 : begin + ap_NS_fsm = ap_ST_fsm_state1963; + end + ap_ST_fsm_state1963 : begin + ap_NS_fsm = ap_ST_fsm_state1964; + end + ap_ST_fsm_state1964 : begin + ap_NS_fsm = ap_ST_fsm_state1965; + end + ap_ST_fsm_state1965 : begin + ap_NS_fsm = ap_ST_fsm_state1966; + end + ap_ST_fsm_state1966 : begin + ap_NS_fsm = ap_ST_fsm_state1967; + end + ap_ST_fsm_state1967 : begin + ap_NS_fsm = ap_ST_fsm_state1968; + end + ap_ST_fsm_state1968 : begin + ap_NS_fsm = ap_ST_fsm_state1969; + end + ap_ST_fsm_state1969 : begin + ap_NS_fsm = ap_ST_fsm_state1970; + end + ap_ST_fsm_state1970 : begin + ap_NS_fsm = ap_ST_fsm_state1971; + end + ap_ST_fsm_state1971 : begin + ap_NS_fsm = ap_ST_fsm_state1972; + end + ap_ST_fsm_state1972 : begin + ap_NS_fsm = ap_ST_fsm_state1973; + end + ap_ST_fsm_state1973 : begin + ap_NS_fsm = ap_ST_fsm_state1974; + end + ap_ST_fsm_state1974 : begin + ap_NS_fsm = ap_ST_fsm_state1975; + end + ap_ST_fsm_state1975 : begin + ap_NS_fsm = ap_ST_fsm_state1976; + end + ap_ST_fsm_state1976 : begin + ap_NS_fsm = ap_ST_fsm_state1977; + end + ap_ST_fsm_state1977 : begin + if (((icmp_ln266_5_fu_87251_p2 == 1'd1) & (icmp_ln268_8_fu_87228_p2 == 1'd1) & (ap_ST_fsm_state1977 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1788; + end else if (((icmp_ln268_8_fu_87228_p2 == 1'd1) & (icmp_ln266_5_fu_87251_p2 == 1'd0) & (ap_ST_fsm_state1977 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2015; + end else begin + ap_NS_fsm = ap_ST_fsm_state1978; + end + end + ap_ST_fsm_state1978 : begin + ap_NS_fsm = ap_ST_fsm_state1979; + end + ap_ST_fsm_state1979 : begin + ap_NS_fsm = ap_ST_fsm_state1980; + end + ap_ST_fsm_state1980 : begin + ap_NS_fsm = ap_ST_fsm_state1981; + end + ap_ST_fsm_state1981 : begin + ap_NS_fsm = ap_ST_fsm_state1982; + end + ap_ST_fsm_state1982 : begin + ap_NS_fsm = ap_ST_fsm_state1983; + end + ap_ST_fsm_state1983 : begin + ap_NS_fsm = ap_ST_fsm_state1984; + end + ap_ST_fsm_state1984 : begin + ap_NS_fsm = ap_ST_fsm_state1985; + end + ap_ST_fsm_state1985 : begin + ap_NS_fsm = ap_ST_fsm_state1986; + end + ap_ST_fsm_state1986 : begin + ap_NS_fsm = ap_ST_fsm_state1987; + end + ap_ST_fsm_state1987 : begin + ap_NS_fsm = ap_ST_fsm_state1988; + end + ap_ST_fsm_state1988 : begin + ap_NS_fsm = ap_ST_fsm_state1989; + end + ap_ST_fsm_state1989 : begin + ap_NS_fsm = ap_ST_fsm_state1990; + end + ap_ST_fsm_state1990 : begin + ap_NS_fsm = ap_ST_fsm_state1991; + end + ap_ST_fsm_state1991 : begin + ap_NS_fsm = ap_ST_fsm_state1992; + end + ap_ST_fsm_state1992 : begin + ap_NS_fsm = ap_ST_fsm_state1993; + end + ap_ST_fsm_state1993 : begin + ap_NS_fsm = ap_ST_fsm_state1994; + end + ap_ST_fsm_state1994 : begin + ap_NS_fsm = ap_ST_fsm_state1995; + end + ap_ST_fsm_state1995 : begin + ap_NS_fsm = ap_ST_fsm_state1996; + end + ap_ST_fsm_state1996 : begin + ap_NS_fsm = ap_ST_fsm_state1997; + end + ap_ST_fsm_state1997 : begin + ap_NS_fsm = ap_ST_fsm_state1998; + end + ap_ST_fsm_state1998 : begin + ap_NS_fsm = ap_ST_fsm_state1999; + end + ap_ST_fsm_state1999 : begin + ap_NS_fsm = ap_ST_fsm_state2000; + end + ap_ST_fsm_state2000 : begin + ap_NS_fsm = ap_ST_fsm_state2001; + end + ap_ST_fsm_state2001 : begin + ap_NS_fsm = ap_ST_fsm_state2002; + end + ap_ST_fsm_state2002 : begin + ap_NS_fsm = ap_ST_fsm_state2003; + end + ap_ST_fsm_state2003 : begin + ap_NS_fsm = ap_ST_fsm_state2004; + end + ap_ST_fsm_state2004 : begin + ap_NS_fsm = ap_ST_fsm_state2005; + end + ap_ST_fsm_state2005 : begin + ap_NS_fsm = ap_ST_fsm_state2006; + end + ap_ST_fsm_state2006 : begin + ap_NS_fsm = ap_ST_fsm_state2007; + end + ap_ST_fsm_state2007 : begin + ap_NS_fsm = ap_ST_fsm_state2008; + end + ap_ST_fsm_state2008 : begin + ap_NS_fsm = ap_ST_fsm_state2009; + end + ap_ST_fsm_state2009 : begin + ap_NS_fsm = ap_ST_fsm_state2010; + end + ap_ST_fsm_state2010 : begin + ap_NS_fsm = ap_ST_fsm_state2011; + end + ap_ST_fsm_state2011 : begin + ap_NS_fsm = ap_ST_fsm_state2012; + end + ap_ST_fsm_state2012 : begin + ap_NS_fsm = ap_ST_fsm_state2013; + end + ap_ST_fsm_state2013 : begin + ap_NS_fsm = ap_ST_fsm_state2014; + end + ap_ST_fsm_state2014 : begin + ap_NS_fsm = ap_ST_fsm_state1941; + end + ap_ST_fsm_state2015 : begin + ap_NS_fsm = ap_ST_fsm_state2016; + end + ap_ST_fsm_state2016 : begin + ap_NS_fsm = ap_ST_fsm_state2017; + end + ap_ST_fsm_state2017 : begin + ap_NS_fsm = ap_ST_fsm_state2018; + end + ap_ST_fsm_state2018 : begin + ap_NS_fsm = ap_ST_fsm_state2019; + end + ap_ST_fsm_state2019 : begin + ap_NS_fsm = ap_ST_fsm_state2020; + end + ap_ST_fsm_state2020 : begin + ap_NS_fsm = ap_ST_fsm_state2021; + end + ap_ST_fsm_state2021 : begin + ap_NS_fsm = ap_ST_fsm_state2022; + end + ap_ST_fsm_state2022 : begin + ap_NS_fsm = ap_ST_fsm_state2023; + end + ap_ST_fsm_state2023 : begin + ap_NS_fsm = ap_ST_fsm_state2024; + end + ap_ST_fsm_state2024 : begin + ap_NS_fsm = ap_ST_fsm_state2025; + end + ap_ST_fsm_state2025 : begin + ap_NS_fsm = ap_ST_fsm_state2026; + end + ap_ST_fsm_state2026 : begin + ap_NS_fsm = ap_ST_fsm_state2027; + end + ap_ST_fsm_state2027 : begin + ap_NS_fsm = ap_ST_fsm_state2028; + end + ap_ST_fsm_state2028 : begin + ap_NS_fsm = ap_ST_fsm_state2029; + end + ap_ST_fsm_state2029 : begin + ap_NS_fsm = ap_ST_fsm_state2030; + end + ap_ST_fsm_state2030 : begin + ap_NS_fsm = ap_ST_fsm_state2031; + end + ap_ST_fsm_state2031 : begin + ap_NS_fsm = ap_ST_fsm_state2032; + end + ap_ST_fsm_state2032 : begin + ap_NS_fsm = ap_ST_fsm_state2033; + end + ap_ST_fsm_state2033 : begin + ap_NS_fsm = ap_ST_fsm_state2034; + end + ap_ST_fsm_state2034 : begin + ap_NS_fsm = ap_ST_fsm_state2035; + end + ap_ST_fsm_state2035 : begin + ap_NS_fsm = ap_ST_fsm_state2036; + end + ap_ST_fsm_state2036 : begin + ap_NS_fsm = ap_ST_fsm_state2037; + end + ap_ST_fsm_state2037 : begin + ap_NS_fsm = ap_ST_fsm_state2038; + end + ap_ST_fsm_state2038 : begin + ap_NS_fsm = ap_ST_fsm_state2039; + end + ap_ST_fsm_state2039 : begin + ap_NS_fsm = ap_ST_fsm_state2040; + end + ap_ST_fsm_state2040 : begin + ap_NS_fsm = ap_ST_fsm_state2041; + end + ap_ST_fsm_state2041 : begin + ap_NS_fsm = ap_ST_fsm_state2042; + end + ap_ST_fsm_state2042 : begin + ap_NS_fsm = ap_ST_fsm_state2043; + end + ap_ST_fsm_state2043 : begin + ap_NS_fsm = ap_ST_fsm_state2044; + end + ap_ST_fsm_state2044 : begin + ap_NS_fsm = ap_ST_fsm_state2045; + end + ap_ST_fsm_state2045 : begin + ap_NS_fsm = ap_ST_fsm_state2046; + end + ap_ST_fsm_state2046 : begin + ap_NS_fsm = ap_ST_fsm_state2047; + end + ap_ST_fsm_state2047 : begin + ap_NS_fsm = ap_ST_fsm_state2048; + end + ap_ST_fsm_state2048 : begin + ap_NS_fsm = ap_ST_fsm_state2049; + end + ap_ST_fsm_state2049 : begin + ap_NS_fsm = ap_ST_fsm_state2050; + end + ap_ST_fsm_state2050 : begin + ap_NS_fsm = ap_ST_fsm_state2051; + end + ap_ST_fsm_state2051 : begin + if (((icmp_ln268_13_fu_87702_p2 == 1'd1) & (ap_ST_fsm_state2051 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1940; + end else begin + ap_NS_fsm = ap_ST_fsm_state2052; + end + end + ap_ST_fsm_state2052 : begin + ap_NS_fsm = ap_ST_fsm_state2053; + end + ap_ST_fsm_state2053 : begin + ap_NS_fsm = ap_ST_fsm_state2054; + end + ap_ST_fsm_state2054 : begin + ap_NS_fsm = ap_ST_fsm_state2055; + end + ap_ST_fsm_state2055 : begin + ap_NS_fsm = ap_ST_fsm_state2056; + end + ap_ST_fsm_state2056 : begin + ap_NS_fsm = ap_ST_fsm_state2057; + end + ap_ST_fsm_state2057 : begin + ap_NS_fsm = ap_ST_fsm_state2058; + end + ap_ST_fsm_state2058 : begin + ap_NS_fsm = ap_ST_fsm_state2059; + end + ap_ST_fsm_state2059 : begin + ap_NS_fsm = ap_ST_fsm_state2060; + end + ap_ST_fsm_state2060 : begin + ap_NS_fsm = ap_ST_fsm_state2061; + end + ap_ST_fsm_state2061 : begin + ap_NS_fsm = ap_ST_fsm_state2062; + end + ap_ST_fsm_state2062 : begin + ap_NS_fsm = ap_ST_fsm_state2063; + end + ap_ST_fsm_state2063 : begin + ap_NS_fsm = ap_ST_fsm_state2064; + end + ap_ST_fsm_state2064 : begin + ap_NS_fsm = ap_ST_fsm_state2065; + end + ap_ST_fsm_state2065 : begin + ap_NS_fsm = ap_ST_fsm_state2066; + end + ap_ST_fsm_state2066 : begin + ap_NS_fsm = ap_ST_fsm_state2067; + end + ap_ST_fsm_state2067 : begin + ap_NS_fsm = ap_ST_fsm_state2068; + end + ap_ST_fsm_state2068 : begin + ap_NS_fsm = ap_ST_fsm_state2069; + end + ap_ST_fsm_state2069 : begin + ap_NS_fsm = ap_ST_fsm_state2070; + end + ap_ST_fsm_state2070 : begin + ap_NS_fsm = ap_ST_fsm_state2071; + end + ap_ST_fsm_state2071 : begin + ap_NS_fsm = ap_ST_fsm_state2072; + end + ap_ST_fsm_state2072 : begin + ap_NS_fsm = ap_ST_fsm_state2073; + end + ap_ST_fsm_state2073 : begin + ap_NS_fsm = ap_ST_fsm_state2074; + end + ap_ST_fsm_state2074 : begin + ap_NS_fsm = ap_ST_fsm_state2075; + end + ap_ST_fsm_state2075 : begin + ap_NS_fsm = ap_ST_fsm_state2076; + end + ap_ST_fsm_state2076 : begin + ap_NS_fsm = ap_ST_fsm_state2077; + end + ap_ST_fsm_state2077 : begin + ap_NS_fsm = ap_ST_fsm_state2078; + end + ap_ST_fsm_state2078 : begin + ap_NS_fsm = ap_ST_fsm_state2079; + end + ap_ST_fsm_state2079 : begin + ap_NS_fsm = ap_ST_fsm_state2080; + end + ap_ST_fsm_state2080 : begin + ap_NS_fsm = ap_ST_fsm_state2081; + end + ap_ST_fsm_state2081 : begin + ap_NS_fsm = ap_ST_fsm_state2082; + end + ap_ST_fsm_state2082 : begin + ap_NS_fsm = ap_ST_fsm_state2083; + end + ap_ST_fsm_state2083 : begin + ap_NS_fsm = ap_ST_fsm_state2084; + end + ap_ST_fsm_state2084 : begin + ap_NS_fsm = ap_ST_fsm_state2085; + end + ap_ST_fsm_state2085 : begin + ap_NS_fsm = ap_ST_fsm_state2086; + end + ap_ST_fsm_state2086 : begin + ap_NS_fsm = ap_ST_fsm_state2087; + end + ap_ST_fsm_state2087 : begin + ap_NS_fsm = ap_ST_fsm_state2015; + end + ap_ST_fsm_state2088 : begin + if (((icmp_ln261_3_fu_87872_p2 == 1'd1) & (ap_ST_fsm_state2088 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state1787; + end else begin + ap_NS_fsm = ap_ST_fsm_state2089; + end + end + ap_ST_fsm_state2089 : begin + ap_NS_fsm = ap_ST_fsm_state2090; + end + ap_ST_fsm_state2090 : begin + ap_NS_fsm = ap_ST_fsm_state2091; + end + ap_ST_fsm_state2091 : begin + ap_NS_fsm = ap_ST_fsm_state2092; + end + ap_ST_fsm_state2092 : begin + ap_NS_fsm = ap_ST_fsm_state2093; + end + ap_ST_fsm_state2093 : begin + ap_NS_fsm = ap_ST_fsm_state2094; + end + ap_ST_fsm_state2094 : begin + ap_NS_fsm = ap_ST_fsm_state2095; + end + ap_ST_fsm_state2095 : begin + ap_NS_fsm = ap_ST_fsm_state2096; + end + ap_ST_fsm_state2096 : begin + ap_NS_fsm = ap_ST_fsm_state2097; + end + ap_ST_fsm_state2097 : begin + ap_NS_fsm = ap_ST_fsm_state2098; + end + ap_ST_fsm_state2098 : begin + ap_NS_fsm = ap_ST_fsm_state2099; + end + ap_ST_fsm_state2099 : begin + ap_NS_fsm = ap_ST_fsm_state2100; + end + ap_ST_fsm_state2100 : begin + ap_NS_fsm = ap_ST_fsm_state2101; + end + ap_ST_fsm_state2101 : begin + ap_NS_fsm = ap_ST_fsm_state2102; + end + ap_ST_fsm_state2102 : begin + ap_NS_fsm = ap_ST_fsm_state2103; + end + ap_ST_fsm_state2103 : begin + ap_NS_fsm = ap_ST_fsm_state2104; + end + ap_ST_fsm_state2104 : begin + ap_NS_fsm = ap_ST_fsm_state2105; + end + ap_ST_fsm_state2105 : begin + ap_NS_fsm = ap_ST_fsm_state2106; + end + ap_ST_fsm_state2106 : begin + ap_NS_fsm = ap_ST_fsm_state2107; + end + ap_ST_fsm_state2107 : begin + ap_NS_fsm = ap_ST_fsm_state2108; + end + ap_ST_fsm_state2108 : begin + ap_NS_fsm = ap_ST_fsm_state2109; + end + ap_ST_fsm_state2109 : begin + ap_NS_fsm = ap_ST_fsm_state2110; + end + ap_ST_fsm_state2110 : begin + ap_NS_fsm = ap_ST_fsm_state2111; + end + ap_ST_fsm_state2111 : begin + ap_NS_fsm = ap_ST_fsm_state2112; + end + ap_ST_fsm_state2112 : begin + ap_NS_fsm = ap_ST_fsm_state2113; + end + ap_ST_fsm_state2113 : begin + ap_NS_fsm = ap_ST_fsm_state2114; + end + ap_ST_fsm_state2114 : begin + ap_NS_fsm = ap_ST_fsm_state2115; + end + ap_ST_fsm_state2115 : begin + ap_NS_fsm = ap_ST_fsm_state2116; + end + ap_ST_fsm_state2116 : begin + ap_NS_fsm = ap_ST_fsm_state2117; + end + ap_ST_fsm_state2117 : begin + ap_NS_fsm = ap_ST_fsm_state2118; + end + ap_ST_fsm_state2118 : begin + ap_NS_fsm = ap_ST_fsm_state2119; + end + ap_ST_fsm_state2119 : begin + ap_NS_fsm = ap_ST_fsm_state2120; + end + ap_ST_fsm_state2120 : begin + ap_NS_fsm = ap_ST_fsm_state2121; + end + ap_ST_fsm_state2121 : begin + ap_NS_fsm = ap_ST_fsm_state2122; + end + ap_ST_fsm_state2122 : begin + ap_NS_fsm = ap_ST_fsm_state2123; + end + ap_ST_fsm_state2123 : begin + ap_NS_fsm = ap_ST_fsm_state2124; + end + ap_ST_fsm_state2124 : begin + ap_NS_fsm = ap_ST_fsm_state2125; + end + ap_ST_fsm_state2125 : begin + ap_NS_fsm = ap_ST_fsm_state2126; + end + ap_ST_fsm_state2126 : begin + if (((icmp_ln266_3_fu_88326_p2 == 1'd1) & (icmp_ln268_3_fu_88303_p2 == 1'd1) & (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2239; + end else if (((icmp_ln268_3_fu_88303_p2 == 1'd1) & (icmp_ln266_3_fu_88326_p2 == 1'd0) & (ap_ST_fsm_state2126 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2164; + end else begin + ap_NS_fsm = ap_ST_fsm_state2127; + end + end + ap_ST_fsm_state2127 : begin + ap_NS_fsm = ap_ST_fsm_state2128; + end + ap_ST_fsm_state2128 : begin + ap_NS_fsm = ap_ST_fsm_state2129; + end + ap_ST_fsm_state2129 : begin + ap_NS_fsm = ap_ST_fsm_state2130; + end + ap_ST_fsm_state2130 : begin + ap_NS_fsm = ap_ST_fsm_state2131; + end + ap_ST_fsm_state2131 : begin + ap_NS_fsm = ap_ST_fsm_state2132; + end + ap_ST_fsm_state2132 : begin + ap_NS_fsm = ap_ST_fsm_state2133; + end + ap_ST_fsm_state2133 : begin + ap_NS_fsm = ap_ST_fsm_state2134; + end + ap_ST_fsm_state2134 : begin + ap_NS_fsm = ap_ST_fsm_state2135; + end + ap_ST_fsm_state2135 : begin + ap_NS_fsm = ap_ST_fsm_state2136; + end + ap_ST_fsm_state2136 : begin + ap_NS_fsm = ap_ST_fsm_state2137; + end + ap_ST_fsm_state2137 : begin + ap_NS_fsm = ap_ST_fsm_state2138; + end + ap_ST_fsm_state2138 : begin + ap_NS_fsm = ap_ST_fsm_state2139; + end + ap_ST_fsm_state2139 : begin + ap_NS_fsm = ap_ST_fsm_state2140; + end + ap_ST_fsm_state2140 : begin + ap_NS_fsm = ap_ST_fsm_state2141; + end + ap_ST_fsm_state2141 : begin + ap_NS_fsm = ap_ST_fsm_state2142; + end + ap_ST_fsm_state2142 : begin + ap_NS_fsm = ap_ST_fsm_state2143; + end + ap_ST_fsm_state2143 : begin + ap_NS_fsm = ap_ST_fsm_state2144; + end + ap_ST_fsm_state2144 : begin + ap_NS_fsm = ap_ST_fsm_state2145; + end + ap_ST_fsm_state2145 : begin + ap_NS_fsm = ap_ST_fsm_state2146; + end + ap_ST_fsm_state2146 : begin + ap_NS_fsm = ap_ST_fsm_state2147; + end + ap_ST_fsm_state2147 : begin + ap_NS_fsm = ap_ST_fsm_state2148; + end + ap_ST_fsm_state2148 : begin + ap_NS_fsm = ap_ST_fsm_state2149; + end + ap_ST_fsm_state2149 : begin + ap_NS_fsm = ap_ST_fsm_state2150; + end + ap_ST_fsm_state2150 : begin + ap_NS_fsm = ap_ST_fsm_state2151; + end + ap_ST_fsm_state2151 : begin + ap_NS_fsm = ap_ST_fsm_state2152; + end + ap_ST_fsm_state2152 : begin + ap_NS_fsm = ap_ST_fsm_state2153; + end + ap_ST_fsm_state2153 : begin + ap_NS_fsm = ap_ST_fsm_state2154; + end + ap_ST_fsm_state2154 : begin + ap_NS_fsm = ap_ST_fsm_state2155; + end + ap_ST_fsm_state2155 : begin + ap_NS_fsm = ap_ST_fsm_state2156; + end + ap_ST_fsm_state2156 : begin + ap_NS_fsm = ap_ST_fsm_state2157; + end + ap_ST_fsm_state2157 : begin + ap_NS_fsm = ap_ST_fsm_state2158; + end + ap_ST_fsm_state2158 : begin + ap_NS_fsm = ap_ST_fsm_state2159; + end + ap_ST_fsm_state2159 : begin + ap_NS_fsm = ap_ST_fsm_state2160; + end + ap_ST_fsm_state2160 : begin + ap_NS_fsm = ap_ST_fsm_state2161; + end + ap_ST_fsm_state2161 : begin + ap_NS_fsm = ap_ST_fsm_state2162; + end + ap_ST_fsm_state2162 : begin + ap_NS_fsm = ap_ST_fsm_state2163; + end + ap_ST_fsm_state2163 : begin + ap_NS_fsm = ap_ST_fsm_state2090; + end + ap_ST_fsm_state2164 : begin + ap_NS_fsm = ap_ST_fsm_state2165; + end + ap_ST_fsm_state2165 : begin + ap_NS_fsm = ap_ST_fsm_state2166; + end + ap_ST_fsm_state2166 : begin + ap_NS_fsm = ap_ST_fsm_state2167; + end + ap_ST_fsm_state2167 : begin + ap_NS_fsm = ap_ST_fsm_state2168; + end + ap_ST_fsm_state2168 : begin + ap_NS_fsm = ap_ST_fsm_state2169; + end + ap_ST_fsm_state2169 : begin + ap_NS_fsm = ap_ST_fsm_state2170; + end + ap_ST_fsm_state2170 : begin + ap_NS_fsm = ap_ST_fsm_state2171; + end + ap_ST_fsm_state2171 : begin + ap_NS_fsm = ap_ST_fsm_state2172; + end + ap_ST_fsm_state2172 : begin + ap_NS_fsm = ap_ST_fsm_state2173; + end + ap_ST_fsm_state2173 : begin + ap_NS_fsm = ap_ST_fsm_state2174; + end + ap_ST_fsm_state2174 : begin + ap_NS_fsm = ap_ST_fsm_state2175; + end + ap_ST_fsm_state2175 : begin + ap_NS_fsm = ap_ST_fsm_state2176; + end + ap_ST_fsm_state2176 : begin + ap_NS_fsm = ap_ST_fsm_state2177; + end + ap_ST_fsm_state2177 : begin + ap_NS_fsm = ap_ST_fsm_state2178; + end + ap_ST_fsm_state2178 : begin + ap_NS_fsm = ap_ST_fsm_state2179; + end + ap_ST_fsm_state2179 : begin + ap_NS_fsm = ap_ST_fsm_state2180; + end + ap_ST_fsm_state2180 : begin + ap_NS_fsm = ap_ST_fsm_state2181; + end + ap_ST_fsm_state2181 : begin + ap_NS_fsm = ap_ST_fsm_state2182; + end + ap_ST_fsm_state2182 : begin + ap_NS_fsm = ap_ST_fsm_state2183; + end + ap_ST_fsm_state2183 : begin + ap_NS_fsm = ap_ST_fsm_state2184; + end + ap_ST_fsm_state2184 : begin + ap_NS_fsm = ap_ST_fsm_state2185; + end + ap_ST_fsm_state2185 : begin + ap_NS_fsm = ap_ST_fsm_state2186; + end + ap_ST_fsm_state2186 : begin + ap_NS_fsm = ap_ST_fsm_state2187; + end + ap_ST_fsm_state2187 : begin + ap_NS_fsm = ap_ST_fsm_state2188; + end + ap_ST_fsm_state2188 : begin + ap_NS_fsm = ap_ST_fsm_state2189; + end + ap_ST_fsm_state2189 : begin + ap_NS_fsm = ap_ST_fsm_state2190; + end + ap_ST_fsm_state2190 : begin + ap_NS_fsm = ap_ST_fsm_state2191; + end + ap_ST_fsm_state2191 : begin + ap_NS_fsm = ap_ST_fsm_state2192; + end + ap_ST_fsm_state2192 : begin + ap_NS_fsm = ap_ST_fsm_state2193; + end + ap_ST_fsm_state2193 : begin + ap_NS_fsm = ap_ST_fsm_state2194; + end + ap_ST_fsm_state2194 : begin + ap_NS_fsm = ap_ST_fsm_state2195; + end + ap_ST_fsm_state2195 : begin + ap_NS_fsm = ap_ST_fsm_state2196; + end + ap_ST_fsm_state2196 : begin + ap_NS_fsm = ap_ST_fsm_state2197; + end + ap_ST_fsm_state2197 : begin + ap_NS_fsm = ap_ST_fsm_state2198; + end + ap_ST_fsm_state2198 : begin + ap_NS_fsm = ap_ST_fsm_state2199; + end + ap_ST_fsm_state2199 : begin + ap_NS_fsm = ap_ST_fsm_state2200; + end + ap_ST_fsm_state2200 : begin + ap_NS_fsm = ap_ST_fsm_state2201; + end + ap_ST_fsm_state2201 : begin + if (((icmp_ln268_10_fu_88841_p2 == 1'd1) & (ap_ST_fsm_state2201 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2089; + end else begin + ap_NS_fsm = ap_ST_fsm_state2202; + end + end + ap_ST_fsm_state2202 : begin + ap_NS_fsm = ap_ST_fsm_state2203; + end + ap_ST_fsm_state2203 : begin + ap_NS_fsm = ap_ST_fsm_state2204; + end + ap_ST_fsm_state2204 : begin + ap_NS_fsm = ap_ST_fsm_state2205; + end + ap_ST_fsm_state2205 : begin + ap_NS_fsm = ap_ST_fsm_state2206; + end + ap_ST_fsm_state2206 : begin + ap_NS_fsm = ap_ST_fsm_state2207; + end + ap_ST_fsm_state2207 : begin + ap_NS_fsm = ap_ST_fsm_state2208; + end + ap_ST_fsm_state2208 : begin + ap_NS_fsm = ap_ST_fsm_state2209; + end + ap_ST_fsm_state2209 : begin + ap_NS_fsm = ap_ST_fsm_state2210; + end + ap_ST_fsm_state2210 : begin + ap_NS_fsm = ap_ST_fsm_state2211; + end + ap_ST_fsm_state2211 : begin + ap_NS_fsm = ap_ST_fsm_state2212; + end + ap_ST_fsm_state2212 : begin + ap_NS_fsm = ap_ST_fsm_state2213; + end + ap_ST_fsm_state2213 : begin + ap_NS_fsm = ap_ST_fsm_state2214; + end + ap_ST_fsm_state2214 : begin + ap_NS_fsm = ap_ST_fsm_state2215; + end + ap_ST_fsm_state2215 : begin + ap_NS_fsm = ap_ST_fsm_state2216; + end + ap_ST_fsm_state2216 : begin + ap_NS_fsm = ap_ST_fsm_state2217; + end + ap_ST_fsm_state2217 : begin + ap_NS_fsm = ap_ST_fsm_state2218; + end + ap_ST_fsm_state2218 : begin + ap_NS_fsm = ap_ST_fsm_state2219; + end + ap_ST_fsm_state2219 : begin + ap_NS_fsm = ap_ST_fsm_state2220; + end + ap_ST_fsm_state2220 : begin + ap_NS_fsm = ap_ST_fsm_state2221; + end + ap_ST_fsm_state2221 : begin + ap_NS_fsm = ap_ST_fsm_state2222; + end + ap_ST_fsm_state2222 : begin + ap_NS_fsm = ap_ST_fsm_state2223; + end + ap_ST_fsm_state2223 : begin + ap_NS_fsm = ap_ST_fsm_state2224; + end + ap_ST_fsm_state2224 : begin + ap_NS_fsm = ap_ST_fsm_state2225; + end + ap_ST_fsm_state2225 : begin + ap_NS_fsm = ap_ST_fsm_state2226; + end + ap_ST_fsm_state2226 : begin + ap_NS_fsm = ap_ST_fsm_state2227; + end + ap_ST_fsm_state2227 : begin + ap_NS_fsm = ap_ST_fsm_state2228; + end + ap_ST_fsm_state2228 : begin + ap_NS_fsm = ap_ST_fsm_state2229; + end + ap_ST_fsm_state2229 : begin + ap_NS_fsm = ap_ST_fsm_state2230; + end + ap_ST_fsm_state2230 : begin + ap_NS_fsm = ap_ST_fsm_state2231; + end + ap_ST_fsm_state2231 : begin + ap_NS_fsm = ap_ST_fsm_state2232; + end + ap_ST_fsm_state2232 : begin + ap_NS_fsm = ap_ST_fsm_state2233; + end + ap_ST_fsm_state2233 : begin + ap_NS_fsm = ap_ST_fsm_state2234; + end + ap_ST_fsm_state2234 : begin + ap_NS_fsm = ap_ST_fsm_state2235; + end + ap_ST_fsm_state2235 : begin + ap_NS_fsm = ap_ST_fsm_state2236; + end + ap_ST_fsm_state2236 : begin + ap_NS_fsm = ap_ST_fsm_state2237; + end + ap_ST_fsm_state2237 : begin + ap_NS_fsm = ap_ST_fsm_state2238; + end + ap_ST_fsm_state2238 : begin + ap_NS_fsm = ap_ST_fsm_state2164; + end + ap_ST_fsm_state2239 : begin + ap_NS_fsm = ap_ST_fsm_state2240; + end + ap_ST_fsm_state2240 : begin + ap_NS_fsm = ap_ST_fsm_state2241; + end + ap_ST_fsm_state2241 : begin + ap_NS_fsm = ap_ST_fsm_state2242; + end + ap_ST_fsm_state2242 : begin + ap_NS_fsm = ap_ST_fsm_state2243; + end + ap_ST_fsm_state2243 : begin + ap_NS_fsm = ap_ST_fsm_state2244; + end + ap_ST_fsm_state2244 : begin + ap_NS_fsm = ap_ST_fsm_state2245; + end + ap_ST_fsm_state2245 : begin + ap_NS_fsm = ap_ST_fsm_state2246; + end + ap_ST_fsm_state2246 : begin + ap_NS_fsm = ap_ST_fsm_state2247; + end + ap_ST_fsm_state2247 : begin + ap_NS_fsm = ap_ST_fsm_state2248; + end + ap_ST_fsm_state2248 : begin + ap_NS_fsm = ap_ST_fsm_state2249; + end + ap_ST_fsm_state2249 : begin + ap_NS_fsm = ap_ST_fsm_state2250; + end + ap_ST_fsm_state2250 : begin + ap_NS_fsm = ap_ST_fsm_state2251; + end + ap_ST_fsm_state2251 : begin + ap_NS_fsm = ap_ST_fsm_state2252; + end + ap_ST_fsm_state2252 : begin + ap_NS_fsm = ap_ST_fsm_state2253; + end + ap_ST_fsm_state2253 : begin + ap_NS_fsm = ap_ST_fsm_state2254; + end + ap_ST_fsm_state2254 : begin + ap_NS_fsm = ap_ST_fsm_state2255; + end + ap_ST_fsm_state2255 : begin + ap_NS_fsm = ap_ST_fsm_state2256; + end + ap_ST_fsm_state2256 : begin + ap_NS_fsm = ap_ST_fsm_state2257; + end + ap_ST_fsm_state2257 : begin + ap_NS_fsm = ap_ST_fsm_state2258; + end + ap_ST_fsm_state2258 : begin + ap_NS_fsm = ap_ST_fsm_state2259; + end + ap_ST_fsm_state2259 : begin + ap_NS_fsm = ap_ST_fsm_state2260; + end + ap_ST_fsm_state2260 : begin + ap_NS_fsm = ap_ST_fsm_state2261; + end + ap_ST_fsm_state2261 : begin + ap_NS_fsm = ap_ST_fsm_state2262; + end + ap_ST_fsm_state2262 : begin + ap_NS_fsm = ap_ST_fsm_state2263; + end + ap_ST_fsm_state2263 : begin + ap_NS_fsm = ap_ST_fsm_state2264; + end + ap_ST_fsm_state2264 : begin + ap_NS_fsm = ap_ST_fsm_state2265; + end + ap_ST_fsm_state2265 : begin + ap_NS_fsm = ap_ST_fsm_state2266; + end + ap_ST_fsm_state2266 : begin + ap_NS_fsm = ap_ST_fsm_state2267; + end + ap_ST_fsm_state2267 : begin + ap_NS_fsm = ap_ST_fsm_state2268; + end + ap_ST_fsm_state2268 : begin + ap_NS_fsm = ap_ST_fsm_state2269; + end + ap_ST_fsm_state2269 : begin + ap_NS_fsm = ap_ST_fsm_state2270; + end + ap_ST_fsm_state2270 : begin + ap_NS_fsm = ap_ST_fsm_state2271; + end + ap_ST_fsm_state2271 : begin + ap_NS_fsm = ap_ST_fsm_state2272; + end + ap_ST_fsm_state2272 : begin + ap_NS_fsm = ap_ST_fsm_state2273; + end + ap_ST_fsm_state2273 : begin + ap_NS_fsm = ap_ST_fsm_state2274; + end + ap_ST_fsm_state2274 : begin + ap_NS_fsm = ap_ST_fsm_state2275; + end + ap_ST_fsm_state2275 : begin + ap_NS_fsm = ap_ST_fsm_state2276; + end + ap_ST_fsm_state2276 : begin + if (((icmp_ln266_7_fu_89341_p2 == 1'd1) & (icmp_ln268_11_fu_89318_p2 == 1'd1) & (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2088; + end else if (((icmp_ln268_11_fu_89318_p2 == 1'd1) & (icmp_ln266_7_fu_89341_p2 == 1'd0) & (ap_ST_fsm_state2276 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2314; + end else begin + ap_NS_fsm = ap_ST_fsm_state2277; + end + end + ap_ST_fsm_state2277 : begin + ap_NS_fsm = ap_ST_fsm_state2278; + end + ap_ST_fsm_state2278 : begin + ap_NS_fsm = ap_ST_fsm_state2279; + end + ap_ST_fsm_state2279 : begin + ap_NS_fsm = ap_ST_fsm_state2280; + end + ap_ST_fsm_state2280 : begin + ap_NS_fsm = ap_ST_fsm_state2281; + end + ap_ST_fsm_state2281 : begin + ap_NS_fsm = ap_ST_fsm_state2282; + end + ap_ST_fsm_state2282 : begin + ap_NS_fsm = ap_ST_fsm_state2283; + end + ap_ST_fsm_state2283 : begin + ap_NS_fsm = ap_ST_fsm_state2284; + end + ap_ST_fsm_state2284 : begin + ap_NS_fsm = ap_ST_fsm_state2285; + end + ap_ST_fsm_state2285 : begin + ap_NS_fsm = ap_ST_fsm_state2286; + end + ap_ST_fsm_state2286 : begin + ap_NS_fsm = ap_ST_fsm_state2287; + end + ap_ST_fsm_state2287 : begin + ap_NS_fsm = ap_ST_fsm_state2288; + end + ap_ST_fsm_state2288 : begin + ap_NS_fsm = ap_ST_fsm_state2289; + end + ap_ST_fsm_state2289 : begin + ap_NS_fsm = ap_ST_fsm_state2290; + end + ap_ST_fsm_state2290 : begin + ap_NS_fsm = ap_ST_fsm_state2291; + end + ap_ST_fsm_state2291 : begin + ap_NS_fsm = ap_ST_fsm_state2292; + end + ap_ST_fsm_state2292 : begin + ap_NS_fsm = ap_ST_fsm_state2293; + end + ap_ST_fsm_state2293 : begin + ap_NS_fsm = ap_ST_fsm_state2294; + end + ap_ST_fsm_state2294 : begin + ap_NS_fsm = ap_ST_fsm_state2295; + end + ap_ST_fsm_state2295 : begin + ap_NS_fsm = ap_ST_fsm_state2296; + end + ap_ST_fsm_state2296 : begin + ap_NS_fsm = ap_ST_fsm_state2297; + end + ap_ST_fsm_state2297 : begin + ap_NS_fsm = ap_ST_fsm_state2298; + end + ap_ST_fsm_state2298 : begin + ap_NS_fsm = ap_ST_fsm_state2299; + end + ap_ST_fsm_state2299 : begin + ap_NS_fsm = ap_ST_fsm_state2300; + end + ap_ST_fsm_state2300 : begin + ap_NS_fsm = ap_ST_fsm_state2301; + end + ap_ST_fsm_state2301 : begin + ap_NS_fsm = ap_ST_fsm_state2302; + end + ap_ST_fsm_state2302 : begin + ap_NS_fsm = ap_ST_fsm_state2303; + end + ap_ST_fsm_state2303 : begin + ap_NS_fsm = ap_ST_fsm_state2304; + end + ap_ST_fsm_state2304 : begin + ap_NS_fsm = ap_ST_fsm_state2305; + end + ap_ST_fsm_state2305 : begin + ap_NS_fsm = ap_ST_fsm_state2306; + end + ap_ST_fsm_state2306 : begin + ap_NS_fsm = ap_ST_fsm_state2307; + end + ap_ST_fsm_state2307 : begin + ap_NS_fsm = ap_ST_fsm_state2308; + end + ap_ST_fsm_state2308 : begin + ap_NS_fsm = ap_ST_fsm_state2309; + end + ap_ST_fsm_state2309 : begin + ap_NS_fsm = ap_ST_fsm_state2310; + end + ap_ST_fsm_state2310 : begin + ap_NS_fsm = ap_ST_fsm_state2311; + end + ap_ST_fsm_state2311 : begin + ap_NS_fsm = ap_ST_fsm_state2312; + end + ap_ST_fsm_state2312 : begin + ap_NS_fsm = ap_ST_fsm_state2313; + end + ap_ST_fsm_state2313 : begin + ap_NS_fsm = ap_ST_fsm_state2240; + end + ap_ST_fsm_state2314 : begin + ap_NS_fsm = ap_ST_fsm_state2315; + end + ap_ST_fsm_state2315 : begin + ap_NS_fsm = ap_ST_fsm_state2316; + end + ap_ST_fsm_state2316 : begin + ap_NS_fsm = ap_ST_fsm_state2317; + end + ap_ST_fsm_state2317 : begin + ap_NS_fsm = ap_ST_fsm_state2318; + end + ap_ST_fsm_state2318 : begin + ap_NS_fsm = ap_ST_fsm_state2319; + end + ap_ST_fsm_state2319 : begin + ap_NS_fsm = ap_ST_fsm_state2320; + end + ap_ST_fsm_state2320 : begin + ap_NS_fsm = ap_ST_fsm_state2321; + end + ap_ST_fsm_state2321 : begin + ap_NS_fsm = ap_ST_fsm_state2322; + end + ap_ST_fsm_state2322 : begin + ap_NS_fsm = ap_ST_fsm_state2323; + end + ap_ST_fsm_state2323 : begin + ap_NS_fsm = ap_ST_fsm_state2324; + end + ap_ST_fsm_state2324 : begin + ap_NS_fsm = ap_ST_fsm_state2325; + end + ap_ST_fsm_state2325 : begin + ap_NS_fsm = ap_ST_fsm_state2326; + end + ap_ST_fsm_state2326 : begin + ap_NS_fsm = ap_ST_fsm_state2327; + end + ap_ST_fsm_state2327 : begin + ap_NS_fsm = ap_ST_fsm_state2328; + end + ap_ST_fsm_state2328 : begin + ap_NS_fsm = ap_ST_fsm_state2329; + end + ap_ST_fsm_state2329 : begin + ap_NS_fsm = ap_ST_fsm_state2330; + end + ap_ST_fsm_state2330 : begin + ap_NS_fsm = ap_ST_fsm_state2331; + end + ap_ST_fsm_state2331 : begin + ap_NS_fsm = ap_ST_fsm_state2332; + end + ap_ST_fsm_state2332 : begin + ap_NS_fsm = ap_ST_fsm_state2333; + end + ap_ST_fsm_state2333 : begin + ap_NS_fsm = ap_ST_fsm_state2334; + end + ap_ST_fsm_state2334 : begin + ap_NS_fsm = ap_ST_fsm_state2335; + end + ap_ST_fsm_state2335 : begin + ap_NS_fsm = ap_ST_fsm_state2336; + end + ap_ST_fsm_state2336 : begin + ap_NS_fsm = ap_ST_fsm_state2337; + end + ap_ST_fsm_state2337 : begin + ap_NS_fsm = ap_ST_fsm_state2338; + end + ap_ST_fsm_state2338 : begin + ap_NS_fsm = ap_ST_fsm_state2339; + end + ap_ST_fsm_state2339 : begin + ap_NS_fsm = ap_ST_fsm_state2340; + end + ap_ST_fsm_state2340 : begin + ap_NS_fsm = ap_ST_fsm_state2341; + end + ap_ST_fsm_state2341 : begin + ap_NS_fsm = ap_ST_fsm_state2342; + end + ap_ST_fsm_state2342 : begin + ap_NS_fsm = ap_ST_fsm_state2343; + end + ap_ST_fsm_state2343 : begin + ap_NS_fsm = ap_ST_fsm_state2344; + end + ap_ST_fsm_state2344 : begin + ap_NS_fsm = ap_ST_fsm_state2345; + end + ap_ST_fsm_state2345 : begin + ap_NS_fsm = ap_ST_fsm_state2346; + end + ap_ST_fsm_state2346 : begin + ap_NS_fsm = ap_ST_fsm_state2347; + end + ap_ST_fsm_state2347 : begin + ap_NS_fsm = ap_ST_fsm_state2348; + end + ap_ST_fsm_state2348 : begin + ap_NS_fsm = ap_ST_fsm_state2349; + end + ap_ST_fsm_state2349 : begin + ap_NS_fsm = ap_ST_fsm_state2350; + end + ap_ST_fsm_state2350 : begin + if (((icmp_ln268_15_fu_89790_p2 == 1'd1) & (ap_ST_fsm_state2350 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state2239; + end else begin + ap_NS_fsm = ap_ST_fsm_state2351; + end + end + ap_ST_fsm_state2351 : begin + ap_NS_fsm = ap_ST_fsm_state2352; + end + ap_ST_fsm_state2352 : begin + ap_NS_fsm = ap_ST_fsm_state2353; + end + ap_ST_fsm_state2353 : begin + ap_NS_fsm = ap_ST_fsm_state2354; + end + ap_ST_fsm_state2354 : begin + ap_NS_fsm = ap_ST_fsm_state2355; + end + ap_ST_fsm_state2355 : begin + ap_NS_fsm = ap_ST_fsm_state2356; + end + ap_ST_fsm_state2356 : begin + ap_NS_fsm = ap_ST_fsm_state2357; + end + ap_ST_fsm_state2357 : begin + ap_NS_fsm = ap_ST_fsm_state2358; + end + ap_ST_fsm_state2358 : begin + ap_NS_fsm = ap_ST_fsm_state2359; + end + ap_ST_fsm_state2359 : begin + ap_NS_fsm = ap_ST_fsm_state2360; + end + ap_ST_fsm_state2360 : begin + ap_NS_fsm = ap_ST_fsm_state2361; + end + ap_ST_fsm_state2361 : begin + ap_NS_fsm = ap_ST_fsm_state2362; + end + ap_ST_fsm_state2362 : begin + ap_NS_fsm = ap_ST_fsm_state2363; + end + ap_ST_fsm_state2363 : begin + ap_NS_fsm = ap_ST_fsm_state2364; + end + ap_ST_fsm_state2364 : begin + ap_NS_fsm = ap_ST_fsm_state2365; + end + ap_ST_fsm_state2365 : begin + ap_NS_fsm = ap_ST_fsm_state2366; + end + ap_ST_fsm_state2366 : begin + ap_NS_fsm = ap_ST_fsm_state2367; + end + ap_ST_fsm_state2367 : begin + ap_NS_fsm = ap_ST_fsm_state2368; + end + ap_ST_fsm_state2368 : begin + ap_NS_fsm = ap_ST_fsm_state2369; + end + ap_ST_fsm_state2369 : begin + ap_NS_fsm = ap_ST_fsm_state2370; + end + ap_ST_fsm_state2370 : begin + ap_NS_fsm = ap_ST_fsm_state2371; + end + ap_ST_fsm_state2371 : begin + ap_NS_fsm = ap_ST_fsm_state2372; + end + ap_ST_fsm_state2372 : begin + ap_NS_fsm = ap_ST_fsm_state2373; + end + ap_ST_fsm_state2373 : begin + ap_NS_fsm = ap_ST_fsm_state2374; + end + ap_ST_fsm_state2374 : begin + ap_NS_fsm = ap_ST_fsm_state2375; + end + ap_ST_fsm_state2375 : begin + ap_NS_fsm = ap_ST_fsm_state2376; + end + ap_ST_fsm_state2376 : begin + ap_NS_fsm = ap_ST_fsm_state2377; + end + ap_ST_fsm_state2377 : begin + ap_NS_fsm = ap_ST_fsm_state2378; + end + ap_ST_fsm_state2378 : begin + ap_NS_fsm = ap_ST_fsm_state2379; + end + ap_ST_fsm_state2379 : begin + ap_NS_fsm = ap_ST_fsm_state2380; + end + ap_ST_fsm_state2380 : begin + ap_NS_fsm = ap_ST_fsm_state2381; + end + ap_ST_fsm_state2381 : begin + ap_NS_fsm = ap_ST_fsm_state2382; + end + ap_ST_fsm_state2382 : begin + ap_NS_fsm = ap_ST_fsm_state2383; + end + ap_ST_fsm_state2383 : begin + ap_NS_fsm = ap_ST_fsm_state2384; + end + ap_ST_fsm_state2384 : begin + ap_NS_fsm = ap_ST_fsm_state2385; + end + ap_ST_fsm_state2385 : begin + ap_NS_fsm = ap_ST_fsm_state2386; + end + ap_ST_fsm_state2386 : begin + ap_NS_fsm = ap_ST_fsm_state2314; + end + ap_ST_fsm_state2387 : begin + ap_NS_fsm = ap_ST_fsm_state2388; + end + ap_ST_fsm_state2388 : begin + ap_NS_fsm = ap_ST_fsm_state2389; + end + ap_ST_fsm_state2389 : begin + ap_NS_fsm = ap_ST_fsm_state2390; + end + ap_ST_fsm_state2390 : begin + ap_NS_fsm = ap_ST_fsm_state2391; + end + ap_ST_fsm_state2391 : begin + ap_NS_fsm = ap_ST_fsm_state2392; + end + ap_ST_fsm_state2392 : begin + ap_NS_fsm = ap_ST_fsm_state2393; + end + ap_ST_fsm_state2393 : begin + ap_NS_fsm = ap_ST_fsm_state2394; + end + ap_ST_fsm_state2394 : begin + ap_NS_fsm = ap_ST_fsm_state2395; + end + ap_ST_fsm_state2395 : begin + ap_NS_fsm = ap_ST_fsm_state2396; + end + ap_ST_fsm_state2396 : begin + ap_NS_fsm = ap_ST_fsm_state2397; + end + ap_ST_fsm_state2397 : begin + ap_NS_fsm = ap_ST_fsm_state2398; + end + ap_ST_fsm_state2398 : begin + ap_NS_fsm = ap_ST_fsm_state2399; + end + ap_ST_fsm_state2399 : begin + ap_NS_fsm = ap_ST_fsm_state2400; + end + ap_ST_fsm_state2400 : begin + ap_NS_fsm = ap_ST_fsm_state2401; + end + ap_ST_fsm_state2401 : begin + ap_NS_fsm = ap_ST_fsm_state2402; + end + ap_ST_fsm_state2402 : begin + ap_NS_fsm = ap_ST_fsm_state2403; + end + ap_ST_fsm_state2403 : begin + ap_NS_fsm = ap_ST_fsm_state2404; + end + ap_ST_fsm_state2404 : begin + ap_NS_fsm = ap_ST_fsm_state2405; + end + ap_ST_fsm_state2405 : begin + ap_NS_fsm = ap_ST_fsm_state2406; + end + ap_ST_fsm_state2406 : begin + ap_NS_fsm = ap_ST_fsm_state2407; + end + ap_ST_fsm_state2407 : begin + ap_NS_fsm = ap_ST_fsm_state2408; + end + ap_ST_fsm_state2408 : begin + ap_NS_fsm = ap_ST_fsm_state2409; + end + ap_ST_fsm_state2409 : begin + ap_NS_fsm = ap_ST_fsm_state2410; + end + ap_ST_fsm_state2410 : begin + ap_NS_fsm = ap_ST_fsm_state2411; + end + ap_ST_fsm_state2411 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +assign add_ln1116_10_fu_75990_p2 = (or_ln231_2_fu_75979_p2 + add_ln231_6_reg_90670); + +assign add_ln1116_11_fu_74830_p2 = (add_ln231_8_reg_90425 + trunc_ln231_13_fu_74826_p1); + +assign add_ln1116_12_fu_79453_p2 = (or_ln231_3_fu_79442_p2 + add_ln231_7_reg_91669); + +assign add_ln1116_13_fu_78290_p2 = (add_ln231_9_reg_91418 + trunc_ln231_15_fu_78286_p1); + +assign add_ln1116_14_fu_76520_p2 = (add_ln231_10_reg_90885 + trunc_ln231_16_fu_76516_p1); + +assign add_ln1116_15_fu_79981_p2 = (add_ln231_11_reg_91889 + trunc_ln231_17_fu_79977_p1); + +assign add_ln1116_16_fu_75124_p2 = (or_ln231_4_fu_75113_p2 + add_ln231_8_reg_90425); + +assign add_ln1116_17_fu_78584_p2 = (or_ln231_5_fu_78573_p2 + add_ln231_9_reg_91418); + +assign add_ln1116_18_fu_76804_p2 = (or_ln231_6_fu_76793_p2 + add_ln231_10_reg_90885); + +assign add_ln1116_19_fu_80265_p2 = (or_ln231_7_fu_80254_p2 + add_ln231_11_reg_91889); + +assign add_ln1116_1_fu_73728_p2 = ((3'd6) + (trunc_ln231_fu_73724_p1)); + +assign add_ln1116_2_fu_73821_p2 = ((trunc_ln231_reg_90111) + (3'd7)); + +assign add_ln1116_3_fu_77279_p2 = ((trunc_ln231_1_reg_91107) + (3'd7)); + +assign add_ln1116_4_fu_74005_p2 = (add_ln231_3_reg_90210 + trunc_ln231_5_fu_74001_p1); + +assign add_ln1116_5_fu_77467_p2 = (add_ln231_5_reg_91203 + trunc_ln231_7_fu_77463_p1); + +assign add_ln1116_6_fu_75705_p2 = (add_ln231_6_reg_90670 + trunc_ln231_8_fu_75701_p1); + +assign add_ln1116_7_fu_79169_p2 = (add_ln231_7_reg_91669 + trunc_ln231_9_fu_79165_p1); + +assign add_ln1116_8_fu_74300_p2 = (or_ln231_fu_74289_p2 + add_ln231_3_reg_90210); + +assign add_ln1116_9_fu_77761_p2 = (or_ln231_1_fu_77750_p2 + add_ln231_5_reg_91203); + +assign add_ln1116_fu_77194_p2 = ((3'd6) + (trunc_ln231_1_fu_77190_p1)); + +assign add_ln1265_1_fu_87887_p2 = (add_ln279_7_reg_98352 + zext_ln279_19_fu_87878_p1); + +assign add_ln1265_fu_83540_p2 = (add_ln279_5_reg_94288 + zext_ln279_17_fu_83531_p1); + +assign add_ln199_fu_77200_p2 = (oh_0_0_reg_72639 + 5'd2); + +assign add_ln201_1_fu_78980_p2 = (ow_0_1_0_reg_72781 + 5'd2); + +assign add_ln201_fu_75520_p2 = (ow_0_0_0_reg_72651 + 5'd2); + +assign add_ln203_10_fu_75476_p2 = (phi_mul104991_reg_72734 + 7'd25); + +assign add_ln203_11_fu_78936_p2 = (phi_mul105011_reg_72864 + 7'd25); + +assign add_ln203_3_fu_80968_p2 = (add_ln250_5_reg_92461 + zext_ln250_8_fu_80959_p1); + +assign add_ln203_4_fu_77222_p2 = (ff_0_1_0_reg_72793 + 3'd1); + +assign add_ln203_5_fu_75492_p2 = (ff_0_0_1_reg_72722 + 3'd1); + +assign add_ln203_6_fu_78952_p2 = (ff_0_1_1_reg_72852 + 3'd1); + +assign add_ln203_7_fu_81344_p2 = (add_ln250_7_reg_93009 + zext_ln250_9_fu_81335_p1); + +assign add_ln203_8_fu_73748_p2 = (phi_mul_reg_72675 + 7'd25); + +assign add_ln203_9_fu_77206_p2 = (phi_mul105001_reg_72805 + 7'd25); + +assign add_ln203_fu_73764_p2 = (ff_0_0_0_reg_72663 + 3'd1); + +assign add_ln206_1_fu_78624_p2 = (fh_0_0_1_0_0_reg_72816 + 32'd2); + +assign add_ln206_2_fu_76844_p2 = (fh_0_0_0_1_0_reg_72745 + 32'd2); + +assign add_ln206_3_fu_80305_p2 = (fh_0_0_1_1_0_reg_72875 + 32'd2); + +assign add_ln206_fu_75164_p2 = (fh_0_0_0_0_0_reg_72686 + 32'd2); + +assign add_ln208_1_fu_78153_p2 = (fw_0_0_1_0_0_0_reg_72828 + 32'd2); + +assign add_ln208_2_fu_76383_p2 = (fw_0_0_0_1_0_0_reg_72757 + 32'd2); + +assign add_ln208_3_fu_79844_p2 = (fw_0_0_1_1_0_0_reg_72887 + 32'd2); + +assign add_ln208_4_fu_75416_p2 = (fw_0_0_0_0_1_0_reg_72710 + 32'd2); + +assign add_ln208_5_fu_78876_p2 = (fw_0_0_1_0_1_0_reg_72840 + 32'd2); + +assign add_ln208_6_fu_77096_p2 = (fw_0_0_0_1_1_0_reg_72769 + 32'd2); + +assign add_ln208_7_fu_80557_p2 = (fw_0_0_1_1_1_0_reg_72899 + 32'd2); + +assign add_ln208_fu_74693_p2 = (fw_0_0_0_0_0_0_reg_72698 + 32'd2); + +assign add_ln216_10_fu_75599_p2 = (fh_0_0_0_1_0_reg_72745 + zext_ln216_8_reg_90638); + +assign add_ln216_11_fu_75604_p2 = (add_ln216_10_fu_75599_p2 + shl_ln216_2_fu_75581_p2); + +assign add_ln216_12_fu_78962_p2 = (zext_ln216_9_fu_78958_p1 + mul_ln231_3_reg_91157); + +assign add_ln216_13_fu_78971_p2 = (mul_ln201_1_reg_90134 + zext_ln216_10_fu_78967_p1); + +assign add_ln216_16_fu_79063_p2 = (fh_0_0_1_1_0_reg_72875 + zext_ln216_11_reg_91631); + +assign add_ln216_17_fu_79068_p2 = (add_ln216_16_fu_79063_p2 + shl_ln216_3_fu_79045_p2); + +assign add_ln216_1_fu_73783_p2 = (mul_ln201_reg_90078 + zext_ln216_1_fu_73779_p1); + +assign add_ln216_20_fu_74239_p2 = (add_ln216_3_reg_90198 + or_ln208_fu_74227_p2); + +assign add_ln216_21_fu_74395_p2 = (or_ln206_fu_74320_p2 + zext_ln216_2_reg_90158); + +assign add_ln216_22_fu_74400_p2 = (add_ln216_21_fu_74395_p2 + shl_ln216_4_fu_74332_p2); + +assign add_ln216_23_fu_77700_p2 = (add_ln216_9_reg_91191 + or_ln208_1_fu_77688_p2); + +assign add_ln216_24_fu_75929_p2 = (add_ln216_11_reg_90658 + or_ln208_2_fu_75917_p2); + +assign add_ln216_26_fu_77856_p2 = (or_ln206_1_fu_77781_p2 + zext_ln216_5_reg_91143); + +assign add_ln216_27_fu_77861_p2 = (add_ln216_26_fu_77856_p2 + shl_ln216_5_fu_77793_p2); + +assign add_ln216_28_fu_76085_p2 = (or_ln206_2_fu_76010_p2 + zext_ln216_8_reg_90638); + +assign add_ln216_29_fu_76090_p2 = (add_ln216_28_fu_76085_p2 + shl_ln216_6_fu_76022_p2); + +assign add_ln216_2_fu_73899_p2 = (fh_0_0_0_0_0_reg_72686 + zext_ln216_2_reg_90158); + +assign add_ln216_30_fu_79392_p2 = (add_ln216_17_reg_91657 + or_ln208_3_fu_79380_p2); + +assign add_ln216_33_fu_79568_p2 = (or_ln206_3_fu_79493_p2 + zext_ln216_11_reg_91631); + +assign add_ln216_34_fu_79573_p2 = (add_ln216_33_fu_79568_p2 + shl_ln216_7_fu_79505_p2); + +assign add_ln216_36_fu_75063_p2 = (add_ln216_22_reg_90316 + or_ln208_4_fu_75051_p2); + +assign add_ln216_37_fu_78523_p2 = (add_ln216_27_reg_91309 + or_ln208_5_fu_78511_p2); + +assign add_ln216_38_fu_76743_p2 = (add_ln216_29_reg_90776 + or_ln208_6_fu_76731_p2); + +assign add_ln216_39_fu_80204_p2 = (add_ln216_34_reg_91780 + or_ln208_7_fu_80192_p2); + +assign add_ln216_3_fu_73904_p2 = (add_ln216_2_fu_73899_p2 + shl_ln216_fu_73881_p2); + +assign add_ln216_4_fu_77232_p2 = (zext_ln216_3_fu_77228_p1 + mul_ln231_1_reg_91091); + +assign add_ln216_5_fu_77241_p2 = (mul_ln201_1_reg_90134 + zext_ln216_4_fu_77237_p1); + +assign add_ln216_6_fu_75502_p2 = (zext_ln216_6_fu_75498_p1 + mul_ln231_2_reg_90172); + +assign add_ln216_7_fu_75511_p2 = (mul_ln201_reg_90078 + zext_ln216_7_fu_75507_p1); + +assign add_ln216_8_fu_77361_p2 = (fh_0_0_1_0_0_reg_72816 + zext_ln216_5_reg_91143); + +assign add_ln216_9_fu_77366_p2 = (add_ln216_8_fu_77361_p2 + shl_ln216_1_fu_77343_p2); + +assign add_ln216_fu_73774_p2 = (zext_ln216_fu_73770_p1 + mul_ln231_reg_90095); + +assign add_ln221_10_fu_74251_p2 = (or_ln_reg_90204 + shl_ln221_8_fu_74245_p2); + +assign add_ln221_11_fu_74406_p2 = (shl_ln216_4_fu_74332_p2 + zext_ln203_reg_90145); + +assign add_ln221_12_fu_74411_p2 = (add_ln221_11_fu_74406_p2 + shl_ln221_9_fu_74338_p2); + +assign add_ln221_13_fu_77712_p2 = (or_ln221_1_reg_91197 + shl_ln221_10_fu_77706_p2); + +assign add_ln221_14_fu_75941_p2 = (or_ln221_2_reg_90664 + shl_ln221_11_fu_75935_p2); + +assign add_ln221_15_fu_74763_p2 = (add_ln221_12_reg_90322 + shl_ln221_12_fu_74757_p2); + +assign add_ln221_16_fu_77867_p2 = (shl_ln216_5_fu_77793_p2 + zext_ln203_4_reg_91130); + +assign add_ln221_17_fu_77872_p2 = (add_ln221_16_fu_77867_p2 + shl_ln221_13_fu_77799_p2); + +assign add_ln221_18_fu_76096_p2 = (shl_ln216_6_fu_76022_p2 + zext_ln203_5_reg_90625); + +assign add_ln221_19_fu_76101_p2 = (add_ln221_18_fu_76096_p2 + shl_ln221_14_fu_76028_p2); + +assign add_ln221_20_fu_79404_p2 = (or_ln221_3_reg_91663 + shl_ln221_15_fu_79398_p2); + +assign add_ln221_21_fu_78223_p2 = (add_ln221_17_reg_91315 + shl_ln221_16_fu_78217_p2); + +assign add_ln221_22_fu_76453_p2 = (add_ln221_19_reg_90782 + shl_ln221_17_fu_76447_p2); + +assign add_ln221_23_fu_79579_p2 = (shl_ln216_7_fu_79505_p2 + zext_ln203_8_reg_91618); + +assign add_ln221_24_fu_79584_p2 = (add_ln221_23_fu_79579_p2 + shl_ln221_18_fu_79511_p2); + +assign add_ln221_25_fu_79914_p2 = (add_ln221_24_reg_91786 + shl_ln221_19_fu_79908_p2); + +assign add_ln221_26_fu_75075_p2 = (add_ln221_12_reg_90322 + shl_ln221_20_fu_75069_p2); + +assign add_ln221_27_fu_78535_p2 = (add_ln221_17_reg_91315 + shl_ln221_21_fu_78529_p2); + +assign add_ln221_28_fu_76755_p2 = (add_ln221_19_reg_90782 + shl_ln221_22_fu_76749_p2); + +assign add_ln221_29_fu_80216_p2 = (add_ln221_24_reg_91786 + shl_ln221_23_fu_80210_p2); + +assign add_ln221_3_fu_73938_p2 = (or_ln_reg_90204 + shl_ln221_1_fu_73932_p2); + +assign add_ln221_4_fu_77355_p2 = (shl_ln221_2_fu_77349_p2 + shl_ln216_1_fu_77343_p2); + +assign add_ln221_5_fu_75593_p2 = (shl_ln221_3_fu_75587_p2 + shl_ln216_2_fu_75581_p2); + +assign add_ln221_6_fu_77400_p2 = (or_ln221_1_reg_91197 + shl_ln221_4_fu_77394_p2); + +assign add_ln221_7_fu_75638_p2 = (or_ln221_2_reg_90664 + shl_ln221_5_fu_75632_p2); + +assign add_ln221_8_fu_79057_p2 = (shl_ln221_6_fu_79051_p2 + shl_ln216_3_fu_79045_p2); + +assign add_ln221_9_fu_79102_p2 = (or_ln221_3_reg_91663 + shl_ln221_7_fu_79096_p2); + +assign add_ln221_fu_73893_p2 = (shl_ln221_fu_73887_p2 + shl_ln216_fu_73881_p2); + +assign add_ln223_10_fu_77805_p2 = (or_ln206_1_fu_77781_p2 + zext_ln199_reg_90126); + +assign add_ln223_11_fu_77717_p2 = (or_ln208_1_fu_77688_p2 + ow_0_1_0_cast_reg_91080); + +assign add_ln223_12_fu_76034_p2 = (or_ln206_2_fu_76010_p2 + oh_0_0_cast_reg_90067); + +assign add_ln223_13_fu_75946_p2 = (or_ln208_2_fu_75917_p2 + zext_ln201_2_reg_90164); + +assign add_ln223_14_fu_74768_p2 = (fw_0_0_0_0_1_0_reg_72710 + ow_0_0_0_cast_reg_90084); + +assign add_ln223_15_fu_79517_p2 = (or_ln206_3_fu_79493_p2 + zext_ln199_reg_90126); + +assign add_ln223_16_fu_79409_p2 = (or_ln208_3_fu_79380_p2 + zext_ln201_3_reg_91149); + +assign add_ln223_17_fu_78228_p2 = (fw_0_0_1_0_1_0_reg_72840 + ow_0_1_0_cast_reg_91080); + +assign add_ln223_18_fu_76458_p2 = (fw_0_0_0_1_1_0_reg_72769 + zext_ln201_2_reg_90164); + +assign add_ln223_19_fu_79919_p2 = (fw_0_0_1_1_1_0_reg_72899 + zext_ln201_3_reg_91149); + +assign add_ln223_1_fu_77284_p2 = (fh_0_0_1_0_0_reg_72816 + zext_ln199_reg_90126); + +assign add_ln223_20_fu_75080_p2 = (or_ln208_4_fu_75051_p2 + ow_0_0_0_cast_reg_90084); + +assign add_ln223_21_fu_78540_p2 = (or_ln208_5_fu_78511_p2 + ow_0_1_0_cast_reg_91080); + +assign add_ln223_22_fu_76760_p2 = (or_ln208_6_fu_76731_p2 + zext_ln201_2_reg_90164); + +assign add_ln223_23_fu_80221_p2 = (or_ln208_7_fu_80192_p2 + zext_ln201_3_reg_91149); + +assign add_ln223_2_fu_75526_p2 = (fh_0_0_0_1_0_reg_72745 + oh_0_0_cast_reg_90067); + +assign add_ln223_3_fu_73943_p2 = (fw_0_0_0_0_0_0_reg_72698 + ow_0_0_0_cast_reg_90084); + +assign add_ln223_4_fu_78986_p2 = (fh_0_0_1_1_0_reg_72875 + zext_ln199_reg_90126); + +assign add_ln223_5_fu_77405_p2 = (fw_0_0_1_0_0_0_reg_72828 + ow_0_1_0_cast_reg_91080); + +assign add_ln223_6_fu_75643_p2 = (fw_0_0_0_1_0_0_reg_72757 + zext_ln201_2_reg_90164); + +assign add_ln223_7_fu_79107_p2 = (fw_0_0_1_1_0_0_reg_72887 + zext_ln201_3_reg_91149); + +assign add_ln223_8_fu_74344_p2 = (or_ln206_fu_74320_p2 + oh_0_0_cast_reg_90067); + +assign add_ln223_9_fu_74256_p2 = (or_ln208_fu_74227_p2 + ow_0_0_0_cast_reg_90084); + +assign add_ln223_fu_73826_p2 = (fh_0_0_0_0_0_reg_72686 + oh_0_0_cast_reg_90067); + +assign add_ln231_10_fu_76443_p2 = ((trunc_ln231_12_reg_90788) + (sext_ln231_2_reg_90177)); + +assign add_ln231_11_fu_79904_p2 = ((trunc_ln231_14_reg_91792) + (sext_ln231_3_reg_91162)); + +assign add_ln231_1_fu_77180_p2 = ((7'd70) + (zext_ln231_3_fu_77176_p1)); + +assign add_ln231_2_fu_73812_p2 = ((zext_ln231_reg_90100) + (7'd71)); + +assign add_ln231_3_fu_73928_p2 = ((trunc_ln231_2_reg_90193) + (sext_ln231_reg_90105)); + +assign add_ln231_4_fu_77270_p2 = ((zext_ln231_3_reg_91096) + (7'd71)); + +assign add_ln231_5_fu_77390_p2 = ((trunc_ln231_3_reg_91180) + (sext_ln231_1_reg_91101)); + +assign add_ln231_6_fu_75628_p2 = ((trunc_ln231_4_reg_90653) + (sext_ln231_2_reg_90177)); + +assign add_ln231_7_fu_79092_p2 = ((trunc_ln231_6_reg_91646) + (sext_ln231_3_reg_91162)); + +assign add_ln231_8_fu_74753_p2 = ((trunc_ln231_10_reg_90328) + (sext_ln231_reg_90105)); + +assign add_ln231_9_fu_78213_p2 = ((trunc_ln231_11_reg_91321) + (sext_ln231_1_reg_91101)); + +assign add_ln231_fu_73714_p2 = ((7'd70) + (zext_ln231_fu_73710_p1)); + +assign add_ln244_fu_81185_p2 = (oh2_0_0_reg_72911 + 5'd2); + +assign add_ln246_1_fu_81400_p2 = (ow3_0_1_0_reg_72959 + 5'd2); + +assign add_ln246_fu_81024_p2 = (ow3_0_0_0_reg_72923 + 5'd2); + +assign add_ln248_1_fu_81319_p2 = (ff4_0_1_0_0_reg_72971 + 3'd2); + +assign add_ln248_2_fu_81057_p2 = (ff4_0_0_1_0_reg_72947 + 3'd2); + +assign add_ln248_3_fu_81433_p2 = (ff4_0_1_1_0_reg_72983 + 3'd2); + +assign add_ln248_fu_80943_p2 = (ff4_0_0_0_0_reg_72935 + 3'd2); + +assign add_ln250_1_fu_80692_p2 = (trunc_ln250_8_fu_80679_p3 + trunc_ln250_reg_92093); + +assign add_ln250_2_fu_81093_p2 = (sub_ln250_1_reg_92438 + zext_ln250_5_fu_81077_p1); + +assign add_ln250_3_fu_81098_p2 = (trunc_ln250_9_fu_81085_p3 + trunc_ln250_1_reg_92444); + +assign add_ln250_4_fu_80856_p2 = (zext_ln250_6_fu_80847_p1 + sub_ln250_reg_92087); + +assign add_ln250_5_fu_80861_p2 = (trunc_ln250_reg_92093 + or_ln250_2_fu_80851_p2); + +assign add_ln250_6_fu_81228_p2 = (zext_ln250_7_fu_81219_p1 + sub_ln250_1_reg_92438); + +assign add_ln250_7_fu_81237_p2 = (trunc_ln250_1_reg_92444 + or_ln250_3_fu_81223_p2); + +assign add_ln250_8_fu_80963_p2 = (add_ln250_4_reg_92456 + ff4_0_0_1_0_cast41_fu_80949_p1); + +assign add_ln250_9_fu_81339_p2 = ((sext_ln250_reg_93004) + (ff4_0_1_1_0_cast34_fu_81325_p1)); + +assign add_ln250_fu_80687_p2 = (sub_ln250_reg_92087 + zext_ln250_4_fu_80671_p1); + +assign add_ln257_fu_85730_p2 = (oh5_0_0_reg_72995 + 5'd2); + +assign add_ln259_1_fu_87981_p2 = (ow6_0_1_0_reg_73187 + 5'd2); + +assign add_ln259_fu_83634_p2 = (ow6_0_0_0_reg_73007 + 5'd2); + +assign add_ln261_1_fu_87274_p2 = (ff7_0_1_0_0_reg_73199 + 3'd2); + +assign add_ln261_2_fu_85017_p2 = (ff7_0_0_1_0_reg_73103 + 3'd2); + +assign add_ln261_3_fu_89364_p2 = (ff7_0_1_1_0_reg_73283 + 3'd2); + +assign add_ln261_fu_82927_p2 = (ff7_0_0_0_0_reg_73019 + 3'd2); + +assign add_ln266_1_fu_86767_p2 = (fh9_0_0_1_0_0_0_reg_73211 + 32'd2); + +assign add_ln266_2_fu_84511_p2 = (fh9_0_0_0_1_0_0_reg_73115 + 32'd2); + +assign add_ln266_3_fu_88858_p2 = (fh9_0_0_1_1_0_0_reg_73295 + 32'd2); + +assign add_ln266_4_fu_83372_p2 = (fh9_0_0_0_0_1_0_reg_73067 + 32'd2); + +assign add_ln266_5_fu_87719_p2 = (fh9_0_0_1_0_1_0_reg_73247 + 32'd2); + +assign add_ln266_6_fu_85460_p2 = (fh9_0_0_0_1_1_0_reg_73151 + 32'd2); + +assign add_ln266_7_fu_89807_p2 = (fh9_0_0_1_1_1_0_reg_73331 + 32'd2); + +assign add_ln266_fu_82420_p2 = (fh9_0_0_0_0_0_0_reg_73031 + 32'd2); + +assign add_ln268_10_fu_89013_p2 = (fw10_0_0_1_1_0_1_0_reg_73319 + 32'd2); + +assign add_ln268_11_fu_89502_p2 = (fw10_0_0_1_1_1_0_0_reg_73343 + 32'd2); + +assign add_ln268_12_fu_83511_p2 = (fw10_0_0_0_0_1_1_0_reg_73091 + 32'd2); + +assign add_ln268_13_fu_87858_p2 = (fw10_0_0_1_0_1_1_0_reg_73271 + 32'd2); + +assign add_ln268_14_fu_85598_p2 = (fw10_0_0_0_1_1_1_0_reg_73175 + 32'd2); + +assign add_ln268_15_fu_89945_p2 = (fw10_0_0_1_1_1_1_0_reg_73355 + 32'd2); + +assign add_ln268_1_fu_86445_p2 = (fw10_0_0_1_0_0_0_0_reg_73223 + 32'd2); + +assign add_ln268_2_fu_84189_p2 = (fw10_0_0_0_1_0_0_0_reg_73127 + 32'd2); + +assign add_ln268_3_fu_88536_p2 = (fw10_0_0_1_1_0_0_0_reg_73307 + 32'd2); + +assign add_ln268_4_fu_82575_p2 = (fw10_0_0_0_0_0_1_0_reg_73055 + 32'd2); + +assign add_ln268_5_fu_83066_p2 = (fw10_0_0_0_0_1_0_0_reg_73079 + 32'd2); + +assign add_ln268_6_fu_86922_p2 = (fw10_0_0_1_0_0_1_0_reg_73235 + 32'd2); + +assign add_ln268_7_fu_84666_p2 = (fw10_0_0_0_1_0_1_0_reg_73139 + 32'd2); + +assign add_ln268_8_fu_87413_p2 = (fw10_0_0_1_0_1_0_0_reg_73259 + 32'd2); + +assign add_ln268_9_fu_85155_p2 = (fw10_0_0_0_1_1_0_0_reg_73163 + 32'd2); + +assign add_ln268_fu_82230_p2 = (fw10_0_0_0_0_0_0_0_reg_73043 + 32'd2); + +assign add_ln276_10_fu_85902_p2 = (fh9_0_0_1_0_0_0_reg_73211 + zext_ln276_1_reg_98341); + +assign add_ln276_11_fu_85907_p2 = (add_ln276_10_fu_85902_p2 + shl_ln276_1_fu_85896_p2); + +assign add_ln276_12_fu_83646_p2 = (fh9_0_0_0_1_0_0_reg_73115 + zext_ln276_2_reg_96306); + +assign add_ln276_13_fu_83651_p2 = (add_ln276_12_fu_83646_p2 + shl_ln276_2_fu_83640_p2); + +assign add_ln276_15_fu_85913_p2 = (add_ln276_11_reg_98748 + fw10_0_0_1_0_0_0_0_reg_73223); + +assign add_ln276_16_fu_83657_p2 = (add_ln276_13_reg_96503 + fw10_0_0_0_1_0_0_0_reg_73127); + +assign add_ln276_17_fu_87993_p2 = (fh9_0_0_1_1_0_0_reg_73295 + zext_ln276_3_reg_100380); + +assign add_ln276_18_fu_87998_p2 = (add_ln276_17_fu_87993_p2 + shl_ln276_3_fu_87987_p2); + +assign add_ln276_19_fu_82003_p2 = (add_ln276_5_reg_94684 + or_ln268_fu_81991_p2); + +assign add_ln276_20_fu_88004_p2 = (add_ln276_18_reg_100577 + fw10_0_0_1_1_0_0_0_reg_73307); + +assign add_ln276_22_fu_82032_p2 = (or_ln266_fu_82014_p2 + zext_ln276_reg_94277); + +assign add_ln276_23_fu_82037_p2 = (add_ln276_22_fu_82032_p2 + shl_ln276_4_fu_82026_p2); + +assign add_ln276_24_fu_86218_p2 = (add_ln276_11_reg_98748 + or_ln268_1_fu_86206_p2); + +assign add_ln276_25_fu_83962_p2 = (add_ln276_13_reg_96503 + or_ln268_2_fu_83950_p2); + +assign add_ln276_26_fu_82587_p2 = (fh9_0_0_0_0_1_0_reg_73067 + zext_ln276_4_reg_94884); + +assign add_ln276_27_fu_82592_p2 = (add_ln276_26_fu_82587_p2 + shl_ln276_5_fu_82581_p2); + +assign add_ln276_28_fu_82236_p2 = (add_ln276_23_reg_94868 + fw10_0_0_0_0_0_1_0_reg_73055); + +assign add_ln276_30_fu_86247_p2 = (or_ln266_1_fu_86229_p2 + zext_ln276_1_reg_98341); + +assign add_ln276_31_fu_86252_p2 = (add_ln276_30_fu_86247_p2 + shl_ln276_6_fu_86241_p2); + +assign add_ln276_33_fu_83991_p2 = (or_ln266_2_fu_83973_p2 + zext_ln276_2_reg_96306); + +assign add_ln276_34_fu_83996_p2 = (add_ln276_33_fu_83991_p2 + shl_ln276_7_fu_83985_p2); + +assign add_ln276_35_fu_82598_p2 = (add_ln276_27_reg_95390 + fw10_0_0_0_0_1_0_0_reg_73079); + +assign add_ln276_36_fu_88309_p2 = (add_ln276_18_reg_100577 + or_ln268_3_fu_88297_p2); + +assign add_ln276_37_fu_86934_p2 = (fh9_0_0_1_0_1_0_reg_73247 + zext_ln276_5_reg_98953); + +assign add_ln276_38_fu_86939_p2 = (add_ln276_37_fu_86934_p2 + shl_ln276_8_fu_86928_p2); + +assign add_ln276_39_fu_86451_p2 = (add_ln276_31_reg_98937 + fw10_0_0_1_0_0_1_0_reg_73235); + +assign add_ln276_40_fu_84678_p2 = (fh9_0_0_0_1_1_0_reg_73151 + zext_ln276_6_reg_96708); + +assign add_ln276_41_fu_84683_p2 = (add_ln276_40_fu_84678_p2 + shl_ln276_9_fu_84672_p2); + +assign add_ln276_42_fu_84195_p2 = (add_ln276_34_reg_96692 + fw10_0_0_0_1_0_1_0_reg_73139); + +assign add_ln276_44_fu_88338_p2 = (or_ln266_3_fu_88320_p2 + zext_ln276_3_reg_100380); + +assign add_ln276_45_fu_88343_p2 = (add_ln276_44_fu_88338_p2 + shl_ln276_10_fu_88332_p2); + +assign add_ln276_46_fu_86945_p2 = (add_ln276_38_reg_99464 + fw10_0_0_1_0_1_0_0_reg_73259); + +assign add_ln276_47_fu_84689_p2 = (add_ln276_41_reg_97219 + fw10_0_0_0_1_1_0_0_reg_73163); + +assign add_ln276_48_fu_82409_p2 = (add_ln276_23_reg_94868 + or_ln268_4_fu_82397_p2); + +assign add_ln276_49_fu_89025_p2 = (fh9_0_0_1_1_1_0_reg_73331 + zext_ln276_7_reg_100782); + +assign add_ln276_4_fu_81819_p2 = (fh9_0_0_0_0_0_0_reg_73031 + zext_ln276_reg_94277); + +assign add_ln276_50_fu_89030_p2 = (add_ln276_49_fu_89025_p2 + shl_ln276_11_fu_89019_p2); + +assign add_ln276_51_fu_88542_p2 = (add_ln276_45_reg_100766 + fw10_0_0_1_1_0_1_0_reg_73319); + +assign add_ln276_52_fu_82887_p2 = (add_ln276_27_reg_95390 + or_ln268_5_fu_82875_p2); + +assign add_ln276_53_fu_89036_p2 = (add_ln276_50_reg_101293 + fw10_0_0_1_1_1_0_0_reg_73343); + +assign add_ln276_54_fu_86756_p2 = (add_ln276_31_reg_98937 + or_ln268_6_fu_86744_p2); + +assign add_ln276_55_fu_84500_p2 = (add_ln276_34_reg_96692 + or_ln268_7_fu_84488_p2); + +assign add_ln276_56_fu_82916_p2 = (or_ln266_4_fu_82898_p2 + zext_ln276_4_reg_94884); + +assign add_ln276_57_fu_82921_p2 = (add_ln276_56_fu_82916_p2 + shl_ln276_12_fu_82910_p2); + +assign add_ln276_58_fu_87234_p2 = (add_ln276_38_reg_99464 + or_ln268_8_fu_87222_p2); + +assign add_ln276_59_fu_84977_p2 = (add_ln276_41_reg_97219 + or_ln268_9_fu_84965_p2); + +assign add_ln276_5_fu_81824_p2 = (add_ln276_4_fu_81819_p2 + shl_ln276_fu_81813_p2); + +assign add_ln276_60_fu_83072_p2 = (add_ln276_57_reg_95579 + fw10_0_0_0_0_1_1_0_reg_73091); + +assign add_ln276_61_fu_88847_p2 = (add_ln276_45_reg_100766 + or_ln268_10_fu_88835_p2); + +assign add_ln276_62_fu_87263_p2 = (or_ln266_5_fu_87245_p2 + zext_ln276_5_reg_98953); + +assign add_ln276_63_fu_87268_p2 = (add_ln276_62_fu_87263_p2 + shl_ln276_13_fu_87257_p2); + +assign add_ln276_64_fu_85006_p2 = (or_ln266_6_fu_84988_p2 + zext_ln276_6_reg_96708); + +assign add_ln276_65_fu_85011_p2 = (add_ln276_64_fu_85006_p2 + shl_ln276_14_fu_85000_p2); + +assign add_ln276_66_fu_89324_p2 = (add_ln276_50_reg_101293 + or_ln268_11_fu_89312_p2); + +assign add_ln276_67_fu_87419_p2 = (add_ln276_63_reg_99653 + fw10_0_0_1_0_1_1_0_reg_73271); + +assign add_ln276_68_fu_85161_p2 = (add_ln276_65_reg_97408 + fw10_0_0_0_1_1_1_0_reg_73175); + +assign add_ln276_69_fu_89353_p2 = (or_ln266_7_fu_89335_p2 + zext_ln276_7_reg_100782); + +assign add_ln276_70_fu_89358_p2 = (add_ln276_69_fu_89353_p2 + shl_ln276_15_fu_89347_p2); + +assign add_ln276_71_fu_83361_p2 = (add_ln276_57_reg_95579 + or_ln268_12_fu_83349_p2); + +assign add_ln276_72_fu_89508_p2 = (add_ln276_70_reg_101482 + fw10_0_0_1_1_1_1_0_reg_73355); + +assign add_ln276_73_fu_87708_p2 = (add_ln276_63_reg_99653 + or_ln268_13_fu_87696_p2); + +assign add_ln276_74_fu_85449_p2 = (add_ln276_65_reg_97408 + or_ln268_14_fu_85437_p2); + +assign add_ln276_75_fu_89796_p2 = (add_ln276_70_reg_101482 + or_ln268_15_fu_89784_p2); + +assign add_ln276_9_fu_81830_p2 = (add_ln276_5_reg_94684 + fw10_0_0_0_0_0_0_0_reg_73043); + +assign add_ln279_1_fu_81522_p2 = (trunc_ln279_5_fu_81509_p3 + trunc_ln279_reg_93217); + +assign add_ln279_2_fu_85638_p2 = (sub_ln279_1_reg_94253 + zext_ln279_9_fu_85622_p1); + +assign add_ln279_3_fu_85643_p2 = (trunc_ln279_6_fu_85630_p3 + trunc_ln279_1_reg_94259); + +assign add_ln279_4_fu_81721_p2 = (sub_ln279_reg_93211 + zext_ln279_11_fu_81705_p1); + +assign add_ln279_5_fu_81726_p2 = (trunc_ln279_7_fu_81713_p3 + trunc_ln279_reg_93217); + +assign add_ln279_6_fu_85804_p2 = (sub_ln279_1_reg_94253 + zext_ln279_14_fu_85788_p1); + +assign add_ln279_7_fu_85809_p2 = (trunc_ln279_8_fu_85796_p3 + trunc_ln279_1_reg_94259); + +assign add_ln279_8_fu_83535_p2 = (add_ln279_4_reg_94283 + ff7_0_0_1_0_cast20_fu_83517_p1); + +assign add_ln279_9_fu_87882_p2 = (add_ln279_6_reg_98347 + ff7_0_1_1_0_cast4_fu_87864_p1); + +assign add_ln279_fu_81517_p2 = (sub_ln279_reg_93211 + zext_ln279_7_fu_81501_p1); + +assign add_ln703_10_fu_86707_p2 = (tmp_137_reg_99280 + tmp_135_reg_99125); + +assign add_ln703_11_fu_84451_p2 = (tmp_141_reg_97035 + tmp_139_reg_96880); + +assign add_ln703_12_fu_87201_p2 = (tmp_152_reg_99631 + tmp_150_reg_99626); + +assign add_ln703_13_fu_84945_p2 = (tmp_155_reg_97386 + tmp_153_reg_97381); + +assign add_ln703_14_fu_82538_p2 = (tmp_157_reg_95380 + add_ln703_7_reg_95211); + +assign add_ln703_15_fu_88798_p2 = (tmp_174_reg_101109 + tmp_172_reg_100954); + +assign add_ln703_16_fu_83045_p2 = (tmp_176_reg_95740 + add_ln703_8_reg_95562); + +assign add_ln703_17_fu_89292_p2 = (tmp_180_reg_101460 + tmp_178_reg_101455); + +assign add_ln703_18_fu_86885_p2 = (tmp_182_reg_99454 + add_ln703_10_reg_99285); + +assign add_ln703_19_fu_84629_p2 = (tmp_184_reg_97209 + add_ln703_11_reg_97040); + +assign add_ln703_1_fu_86169_p2 = (tmp_70_reg_98915 + tmp_68_reg_98910); + +assign add_ln703_20_fu_87392_p2 = (tmp_191_reg_99814 + add_ln703_12_reg_99636); + +assign add_ln703_21_fu_85135_p2 = (tmp_193_reg_97569 + add_ln703_13_reg_97391); + +assign add_ln703_22_fu_83328_p2 = (tmp_196_reg_95911 + tmp_194_reg_95756); + +assign add_ln703_23_fu_88976_p2 = (tmp_199_reg_101283 + add_ln703_15_reg_101114); + +assign add_ln703_24_fu_89482_p2 = (tmp_207_reg_101643 + add_ln703_17_reg_101465); + +assign add_ln703_25_fu_87675_p2 = (tmp_210_reg_99985 + tmp_208_reg_99830); + +assign add_ln703_26_fu_85417_p2 = (tmp_213_reg_97740 + tmp_211_reg_97585); + +assign add_ln703_27_fu_83490_p2 = (tmp_218_reg_96085 + add_ln703_22_reg_95916); + +assign add_ln703_28_fu_89764_p2 = (tmp_229_reg_101814 + tmp_227_reg_101659); + +assign add_ln703_29_fu_87837_p2 = (tmp_230_reg_100159 + add_ln703_25_reg_99990); + +assign add_ln703_2_fu_83913_p2 = (tmp_73_reg_96670 + tmp_71_reg_96665); + +assign add_ln703_30_fu_85578_p2 = (tmp_231_reg_97914 + add_ln703_26_reg_97745); + +assign add_ln703_31_fu_89925_p2 = (tmp_234_reg_101988 + add_ln703_28_reg_101819); + +assign add_ln703_3_fu_82193_p2 = (tmp_81_reg_95040 + add_ln703_reg_94851); + +assign add_ln703_4_fu_88260_p2 = (tmp_87_reg_100744 + tmp_85_reg_100739); + +assign add_ln703_5_fu_86408_p2 = (tmp_96_reg_99109 + add_ln703_1_reg_98920); + +assign add_ln703_6_fu_84152_p2 = (tmp_98_reg_96864 + add_ln703_2_reg_96675); + +assign add_ln703_7_fu_82359_p2 = (tmp_102_reg_95206 + reg_73672); + +assign add_ln703_8_fu_82854_p2 = (tmp_118_reg_95557 + tmp_116_reg_95552); + +assign add_ln703_9_fu_88499_p2 = (tmp_133_reg_100938 + add_ln703_4_reg_100749); + +assign add_ln703_fu_81953_p2 = (tmp_52_reg_94846 + reg_73672); + +assign and_ln1116_10_fu_76659_p2 = (lshr_ln1116_35_fu_76653_p2 & lshr_ln1116_34_reg_90920); + +assign and_ln1116_11_fu_80120_p2 = (lshr_ln1116_37_fu_80114_p2 & lshr_ln1116_36_reg_91924); + +assign and_ln1116_12_fu_75329_p2 = (lshr_ln1116_39_fu_75323_p2 & lshr_ln1116_38_reg_90552); + +assign and_ln1116_13_fu_78789_p2 = (lshr_ln1116_41_fu_78783_p2 & lshr_ln1116_40_reg_91545); + +assign and_ln1116_14_fu_77009_p2 = (lshr_ln1116_43_fu_77003_p2 & lshr_ln1116_42_reg_91012); + +assign and_ln1116_15_fu_80470_p2 = (lshr_ln1116_45_fu_80464_p2 & lshr_ln1116_44_reg_92016); + +assign and_ln1116_1_fu_77616_p2 = (lshr_ln1116_17_fu_77610_p2 & lshr_ln1116_16_reg_91238); + +assign and_ln1116_2_fu_75845_p2 = (lshr_ln1116_19_fu_75839_p2 & lshr_ln1116_18_reg_90705); + +assign and_ln1116_3_fu_79308_p2 = (lshr_ln1116_21_fu_79302_p2 & lshr_ln1116_20_reg_91704); + +assign and_ln1116_4_fu_74606_p2 = (lshr_ln1116_23_fu_74600_p2 & lshr_ln1116_22_reg_90357); + +assign and_ln1116_5_fu_78066_p2 = (lshr_ln1116_25_fu_78060_p2 & lshr_ln1116_24_reg_91350); + +assign and_ln1116_6_fu_76296_p2 = (lshr_ln1116_27_fu_76290_p2 & lshr_ln1116_26_reg_90817); + +assign and_ln1116_7_fu_74979_p2 = (lshr_ln1116_29_fu_74973_p2 & lshr_ln1116_28_reg_90460); + +assign and_ln1116_8_fu_79757_p2 = (lshr_ln1116_31_fu_79751_p2 & lshr_ln1116_30_reg_91821); + +assign and_ln1116_9_fu_78439_p2 = (lshr_ln1116_33_fu_78433_p2 & lshr_ln1116_32_reg_91453); + +assign and_ln1116_fu_74155_p2 = (lshr_ln1116_reg_90245 & lshr_ln1116_15_fu_74149_p2); + +assign empty_100_fu_75748_p2 = (tmp_61_fu_75740_p3 | 6'd7); + +assign empty_101_fu_76174_p2 = (trunc_ln1116_13_fu_76170_p1 | 3'd1); + +assign empty_102_fu_76199_p2 = (tmp_124_fu_76191_p3 | 6'd7); + +assign empty_105_fu_76540_p1 = fw_0_0_0_1_1_0_reg_72769[2:0]; + +assign empty_106_fu_76562_p2 = (tmp_168_fu_76554_p3 | 6'd7); + +assign empty_107_fu_76828_p2 = (trunc_ln1116_26_fu_76819_p1 | 3'd1); + +assign empty_108_fu_76912_p2 = (tmp_224_fu_76905_p3 | 6'd7); + +assign empty_117_fu_77487_p1 = fw_0_0_1_0_0_0_reg_72828[2:0]; + +assign empty_118_fu_77519_p2 = (tmp_57_fu_77511_p3 | 6'd7); + +assign empty_119_fu_77945_p2 = (trunc_ln1116_11_fu_77941_p1 | 3'd1); + +assign empty_120_fu_77969_p2 = (tmp_120_fu_77961_p3 | 6'd7); + +assign empty_123_fu_78310_p1 = fw_0_0_1_0_1_0_reg_72840[2:0]; + +assign empty_124_fu_78342_p2 = (tmp_164_fu_78334_p3 | 6'd7); + +assign empty_125_fu_78608_p2 = (trunc_ln1116_24_fu_78599_p1 | 3'd1); + +assign empty_126_fu_78692_p2 = (tmp_220_fu_78685_p3 | 6'd7); + +assign empty_133_fu_79189_p1 = fw_0_0_1_1_0_0_reg_72887[2:0]; + +assign empty_134_fu_79211_p2 = (tmp_76_fu_79203_p3 | 6'd7); + +assign empty_135_fu_79477_p2 = (trunc_ln1116_17_fu_79468_p1 | 3'd1); + +assign empty_136_fu_79660_p2 = (tmp_159_fu_79653_p3 | 6'd7); + +assign empty_139_fu_80001_p1 = fw_0_0_1_1_1_0_reg_72899[2:0]; + +assign empty_140_fu_80023_p2 = (tmp_187_fu_80015_p3 | 6'd7); + +assign empty_141_fu_80289_p2 = (trunc_ln1116_28_fu_80280_p1 | 3'd1); + +assign empty_142_fu_80373_p2 = (tmp_232_fu_80366_p3 | 6'd7); + +assign empty_149_fu_80916_p1 = ff4_0_0_0_0_reg_72935[1:0]; + +assign empty_152_fu_81030_p1 = ff4_0_0_1_0_reg_72947[1:0]; + +assign empty_157_fu_81292_p1 = ff4_0_1_0_0_reg_72971[1:0]; + +assign empty_160_fu_81406_p1 = ff4_0_1_1_0_reg_72983[1:0]; + +assign empty_172_fu_82043_p1 = ff7_0_0_0_0_reg_73019[1:0]; + +assign empty_187_fu_84002_p1 = ff7_0_0_1_0_reg_73103[1:0]; + +assign empty_204_fu_86258_p1 = ff7_0_1_0_0_reg_73199[1:0]; + +assign empty_219_fu_88349_p1 = ff7_0_1_1_0_reg_73283[1:0]; + +assign empty_83_fu_74025_p1 = fw_0_0_0_0_0_0_reg_72698[2:0]; + +assign empty_84_fu_74058_p2 = (tmp_42_fu_74050_p3 | 6'd7); + +assign empty_85_fu_74484_p2 = (trunc_ln1116_7_fu_74480_p1 | 3'd1); + +assign empty_86_fu_74509_p2 = (tmp_92_fu_74501_p3 | 6'd7); + +assign empty_89_fu_74850_p1 = fw_0_0_0_0_1_0_reg_72710[2:0]; + +assign empty_90_fu_74882_p2 = (tmp_129_fu_74874_p3 | 6'd7); + +assign empty_91_fu_75148_p2 = (trunc_ln1116_22_fu_75139_p1 | 3'd1); + +assign empty_92_fu_75232_p2 = (tmp_203_fu_75225_p3 | 6'd7); + +assign empty_99_fu_75725_p1 = fw_0_0_0_1_0_0_reg_72757[2:0]; + +assign ff4_0_0_1_0_cast41_fu_80949_p1 = ff4_0_0_1_0_reg_72947; + +assign ff4_0_1_1_0_cast34_fu_81325_p1 = ff4_0_1_1_0_reg_72983; + +assign ff7_0_0_1_0_cast20_fu_83517_p1 = ff7_0_0_1_0_reg_73103; + +assign ff7_0_1_1_0_cast4_fu_87864_p1 = ff7_0_1_1_0_reg_73283; + +assign grp_fu_73367_p2 = (fw_0_0_0_0_0_0_reg_72698 + add_ln216_3_reg_90198); + +assign grp_fu_73372_p0 = (fw_0_0_0_0_0_0_reg_72698 + add_ln216_3_reg_90198); + +assign grp_fu_73372_p1 = 32'd28; + +assign grp_fu_73378_p0 = (add_ln216_3_reg_90198 + or_ln208_fu_74227_p2); + +assign grp_fu_73378_p1 = 32'd28; + +assign grp_fu_73383_p2 = (fw_0_0_0_0_1_0_reg_72710 + add_ln216_22_reg_90316); + +assign grp_fu_73388_p0 = (fw_0_0_0_0_1_0_reg_72710 + add_ln216_22_reg_90316); + +assign grp_fu_73388_p1 = 32'd28; + +assign grp_fu_73394_p0 = (add_ln216_22_reg_90316 + or_ln208_4_fu_75051_p2); + +assign grp_fu_73394_p1 = 32'd28; + +assign grp_fu_73399_p2 = (fw_0_0_0_1_0_0_reg_72757 + add_ln216_11_reg_90658); + +assign grp_fu_73404_p0 = (fw_0_0_0_1_0_0_reg_72757 + add_ln216_11_reg_90658); + +assign grp_fu_73404_p1 = 32'd28; + +assign grp_fu_73410_p0 = (add_ln216_11_reg_90658 + or_ln208_2_fu_75917_p2); + +assign grp_fu_73410_p1 = 32'd28; + +assign grp_fu_73415_p2 = (fw_0_0_0_1_1_0_reg_72769 + add_ln216_29_reg_90776); + +assign grp_fu_73420_p0 = (fw_0_0_0_1_1_0_reg_72769 + add_ln216_29_reg_90776); + +assign grp_fu_73420_p1 = 32'd28; + +assign grp_fu_73426_p0 = (add_ln216_29_reg_90776 + or_ln208_6_fu_76731_p2); + +assign grp_fu_73426_p1 = 32'd28; + +assign grp_fu_73431_p2 = (fw_0_0_1_0_0_0_reg_72828 + add_ln216_9_reg_91191); + +assign grp_fu_73436_p0 = (fw_0_0_1_0_0_0_reg_72828 + add_ln216_9_reg_91191); + +assign grp_fu_73436_p1 = 32'd28; + +assign grp_fu_73442_p0 = (add_ln216_9_reg_91191 + or_ln208_1_fu_77688_p2); + +assign grp_fu_73442_p1 = 32'd28; + +assign grp_fu_73447_p2 = (fw_0_0_1_0_1_0_reg_72840 + add_ln216_27_reg_91309); + +assign grp_fu_73452_p0 = (fw_0_0_1_0_1_0_reg_72840 + add_ln216_27_reg_91309); + +assign grp_fu_73452_p1 = 32'd28; + +assign grp_fu_73458_p0 = (add_ln216_27_reg_91309 + or_ln208_5_fu_78511_p2); + +assign grp_fu_73458_p1 = 32'd28; + +assign grp_fu_73463_p2 = (fw_0_0_1_1_0_0_reg_72887 + add_ln216_17_reg_91657); + +assign grp_fu_73468_p0 = (fw_0_0_1_1_0_0_reg_72887 + add_ln216_17_reg_91657); + +assign grp_fu_73468_p1 = 32'd28; + +assign grp_fu_73474_p0 = (add_ln216_17_reg_91657 + or_ln208_3_fu_79380_p2); + +assign grp_fu_73474_p1 = 32'd28; + +assign grp_fu_73479_p2 = (fw_0_0_1_1_1_0_reg_72899 + add_ln216_34_reg_91780); + +assign grp_fu_73484_p0 = (fw_0_0_1_1_1_0_reg_72899 + add_ln216_34_reg_91780); + +assign grp_fu_73484_p1 = 32'd28; + +assign grp_fu_73490_p0 = (add_ln216_34_reg_91780 + or_ln208_7_fu_80192_p2); + +assign grp_fu_73490_p1 = 32'd28; + +assign grp_fu_73985_p0 = 65'd4908534053; + +assign grp_fu_73985_p1 = grp_fu_73985_p10; + +assign grp_fu_73985_p10 = reg_73628; + +assign grp_fu_74429_p0 = 65'd4908534053; + +assign grp_fu_74429_p1 = grp_fu_74429_p10; + +assign grp_fu_74429_p10 = reg_73628; + +assign grp_fu_74642_p0 = 65'd4908534053; + +assign grp_fu_74642_p1 = grp_fu_74642_p10; + +assign grp_fu_74642_p10 = add_ln216_20_reg_90288; + +assign grp_fu_74702_p0 = 65'd4908534053; + +assign grp_fu_74702_p1 = grp_fu_74702_p10; + +assign grp_fu_74702_p10 = add_ln216_20_reg_90288; + +assign grp_fu_74810_p0 = 65'd4908534053; + +assign grp_fu_74810_p1 = grp_fu_74810_p10; + +assign grp_fu_74810_p10 = reg_73637; + +assign grp_fu_75174_p0 = 65'd4908534053; + +assign grp_fu_75174_p1 = grp_fu_75174_p10; + +assign grp_fu_75174_p10 = reg_73637; + +assign grp_fu_75365_p0 = 65'd4908534053; + +assign grp_fu_75365_p1 = grp_fu_75365_p10; + +assign grp_fu_75365_p10 = add_ln216_36_reg_90503; + +assign grp_fu_75425_p0 = 65'd4908534053; + +assign grp_fu_75425_p1 = grp_fu_75425_p10; + +assign grp_fu_75425_p10 = add_ln216_36_reg_90503; + +assign grp_fu_75685_p0 = 65'd4908534053; + +assign grp_fu_75685_p1 = grp_fu_75685_p10; + +assign grp_fu_75685_p10 = reg_73642; + +assign grp_fu_76119_p0 = 65'd4908534053; + +assign grp_fu_76119_p1 = grp_fu_76119_p10; + +assign grp_fu_76119_p10 = reg_73642; + +assign grp_fu_76332_p0 = 65'd4908534053; + +assign grp_fu_76332_p1 = grp_fu_76332_p10; + +assign grp_fu_76332_p10 = add_ln216_24_reg_90748; + +assign grp_fu_76392_p0 = 65'd4908534053; + +assign grp_fu_76392_p1 = grp_fu_76392_p10; + +assign grp_fu_76392_p10 = add_ln216_24_reg_90748; + +assign grp_fu_76500_p0 = 65'd4908534053; + +assign grp_fu_76500_p1 = grp_fu_76500_p10; + +assign grp_fu_76500_p10 = reg_73647; + +assign grp_fu_76854_p0 = 65'd4908534053; + +assign grp_fu_76854_p1 = grp_fu_76854_p10; + +assign grp_fu_76854_p10 = reg_73647; + +assign grp_fu_77045_p0 = 65'd4908534053; + +assign grp_fu_77045_p1 = grp_fu_77045_p10; + +assign grp_fu_77045_p10 = add_ln216_38_reg_90963; + +assign grp_fu_77105_p0 = 65'd4908534053; + +assign grp_fu_77105_p1 = grp_fu_77105_p10; + +assign grp_fu_77105_p10 = add_ln216_38_reg_90963; + +assign grp_fu_77447_p0 = 65'd4908534053; + +assign grp_fu_77447_p1 = grp_fu_77447_p10; + +assign grp_fu_77447_p10 = reg_73652; + +assign grp_fu_77890_p0 = 65'd4908534053; + +assign grp_fu_77890_p1 = grp_fu_77890_p10; + +assign grp_fu_77890_p10 = reg_73652; + +assign grp_fu_78102_p0 = 65'd4908534053; + +assign grp_fu_78102_p1 = grp_fu_78102_p10; + +assign grp_fu_78102_p10 = add_ln216_23_reg_91281; + +assign grp_fu_78162_p0 = 65'd4908534053; + +assign grp_fu_78162_p1 = grp_fu_78162_p10; + +assign grp_fu_78162_p10 = add_ln216_23_reg_91281; + +assign grp_fu_78270_p0 = 65'd4908534053; + +assign grp_fu_78270_p1 = grp_fu_78270_p10; + +assign grp_fu_78270_p10 = reg_73657; + +assign grp_fu_78634_p0 = 65'd4908534053; + +assign grp_fu_78634_p1 = grp_fu_78634_p10; + +assign grp_fu_78634_p10 = reg_73657; + +assign grp_fu_78825_p0 = 65'd4908534053; + +assign grp_fu_78825_p1 = grp_fu_78825_p10; + +assign grp_fu_78825_p10 = add_ln216_37_reg_91496; + +assign grp_fu_78885_p0 = 65'd4908534053; + +assign grp_fu_78885_p1 = grp_fu_78885_p10; + +assign grp_fu_78885_p10 = add_ln216_37_reg_91496; + +assign grp_fu_79149_p0 = 65'd4908534053; + +assign grp_fu_79149_p1 = grp_fu_79149_p10; + +assign grp_fu_79149_p10 = reg_73662; + +assign grp_fu_79602_p0 = 65'd4908534053; + +assign grp_fu_79602_p1 = grp_fu_79602_p10; + +assign grp_fu_79602_p10 = reg_73662; + +assign grp_fu_79793_p0 = 65'd4908534053; + +assign grp_fu_79793_p1 = grp_fu_79793_p10; + +assign grp_fu_79793_p10 = add_ln216_30_reg_91747; + +assign grp_fu_79853_p0 = 65'd4908534053; + +assign grp_fu_79853_p1 = grp_fu_79853_p10; + +assign grp_fu_79853_p10 = add_ln216_30_reg_91747; + +assign grp_fu_79961_p0 = 65'd4908534053; + +assign grp_fu_79961_p1 = grp_fu_79961_p10; + +assign grp_fu_79961_p10 = reg_73667; + +assign grp_fu_80315_p0 = 65'd4908534053; + +assign grp_fu_80315_p1 = grp_fu_80315_p10; + +assign grp_fu_80315_p10 = reg_73667; + +assign grp_fu_80506_p0 = 65'd4908534053; + +assign grp_fu_80506_p1 = grp_fu_80506_p10; + +assign grp_fu_80506_p10 = add_ln216_39_reg_91967; + +assign grp_fu_80566_p0 = 65'd4908534053; + +assign grp_fu_80566_p1 = grp_fu_80566_p10; + +assign grp_fu_80566_p10 = add_ln216_39_reg_91967; + +assign grp_fu_81835_p0 = (add_ln276_5_reg_94684 + fw10_0_0_0_0_0_0_0_reg_73043); + +assign grp_fu_81835_p1 = 32'd28; + +assign grp_fu_81844_p0 = grp_fu_81844_p00; + +assign grp_fu_81844_p00 = add_ln276_9_reg_94690; + +assign grp_fu_81844_p1 = 65'd4908534053; + +assign grp_fu_82008_p0 = (add_ln276_5_reg_94684 + or_ln268_fu_81991_p2); + +assign grp_fu_82008_p1 = 32'd28; + +assign grp_fu_82084_p0 = grp_fu_82084_p00; + +assign grp_fu_82084_p00 = add_ln276_19_reg_94859; + +assign grp_fu_82084_p1 = 65'd4908534053; + +assign grp_fu_82241_p0 = (add_ln276_23_reg_94868 + fw10_0_0_0_0_0_1_0_reg_73055); + +assign grp_fu_82241_p1 = 32'd28; + +assign grp_fu_82250_p0 = grp_fu_82250_p00; + +assign grp_fu_82250_p00 = add_ln276_28_reg_95050; + +assign grp_fu_82250_p1 = 65'd4908534053; + +assign grp_fu_82414_p0 = (add_ln276_23_reg_94868 + or_ln268_4_fu_82397_p2); + +assign grp_fu_82414_p1 = 32'd28; + +assign grp_fu_82429_p0 = grp_fu_82429_p00; + +assign grp_fu_82429_p00 = add_ln276_48_reg_95219; + +assign grp_fu_82429_p1 = 65'd4908534053; + +assign grp_fu_82603_p0 = (add_ln276_27_reg_95390 + fw10_0_0_0_0_1_0_0_reg_73079); + +assign grp_fu_82603_p1 = 32'd28; + +assign grp_fu_82612_p0 = grp_fu_82612_p00; + +assign grp_fu_82612_p00 = add_ln276_35_reg_95396; + +assign grp_fu_82612_p1 = 65'd4908534053; + +assign grp_fu_82892_p0 = (add_ln276_27_reg_95390 + or_ln268_5_fu_82875_p2); + +assign grp_fu_82892_p1 = 32'd28; + +assign grp_fu_82936_p0 = grp_fu_82936_p00; + +assign grp_fu_82936_p00 = add_ln276_52_reg_95570; + +assign grp_fu_82936_p1 = 65'd4908534053; + +assign grp_fu_83077_p0 = (add_ln276_57_reg_95579 + fw10_0_0_0_0_1_1_0_reg_73091); + +assign grp_fu_83077_p1 = 32'd28; + +assign grp_fu_83219_p0 = grp_fu_83219_p00; + +assign grp_fu_83219_p00 = add_ln276_60_reg_95750; + +assign grp_fu_83219_p1 = 65'd4908534053; + +assign grp_fu_83366_p0 = (add_ln276_57_reg_95579 + or_ln268_12_fu_83349_p2); + +assign grp_fu_83366_p1 = 32'd28; + +assign grp_fu_83381_p0 = grp_fu_83381_p00; + +assign grp_fu_83381_p00 = add_ln276_71_reg_95924; + +assign grp_fu_83381_p1 = 65'd4908534053; + +assign grp_fu_83662_p0 = (add_ln276_13_reg_96503 + fw10_0_0_0_1_0_0_0_reg_73127); + +assign grp_fu_83662_p1 = 32'd28; + +assign grp_fu_83671_p0 = grp_fu_83671_p00; + +assign grp_fu_83671_p00 = add_ln276_16_reg_96509; + +assign grp_fu_83671_p1 = 65'd4908534053; + +assign grp_fu_83967_p0 = (add_ln276_13_reg_96503 + or_ln268_2_fu_83950_p2); + +assign grp_fu_83967_p1 = 32'd28; + +assign grp_fu_84043_p0 = grp_fu_84043_p00; + +assign grp_fu_84043_p00 = add_ln276_25_reg_96683; + +assign grp_fu_84043_p1 = 65'd4908534053; + +assign grp_fu_84200_p0 = (add_ln276_34_reg_96692 + fw10_0_0_0_1_0_1_0_reg_73139); + +assign grp_fu_84200_p1 = 32'd28; + +assign grp_fu_84342_p0 = grp_fu_84342_p00; + +assign grp_fu_84342_p00 = add_ln276_42_reg_96874; + +assign grp_fu_84342_p1 = 65'd4908534053; + +assign grp_fu_84505_p0 = (add_ln276_34_reg_96692 + or_ln268_7_fu_84488_p2); + +assign grp_fu_84505_p1 = 32'd28; + +assign grp_fu_84520_p0 = grp_fu_84520_p00; + +assign grp_fu_84520_p00 = add_ln276_55_reg_97048; + +assign grp_fu_84520_p1 = 65'd4908534053; + +assign grp_fu_84694_p0 = (add_ln276_41_reg_97219 + fw10_0_0_0_1_1_0_0_reg_73163); + +assign grp_fu_84694_p1 = 32'd28; + +assign grp_fu_84703_p0 = grp_fu_84703_p00; + +assign grp_fu_84703_p00 = add_ln276_47_reg_97225; + +assign grp_fu_84703_p1 = 65'd4908534053; + +assign grp_fu_84982_p0 = (add_ln276_41_reg_97219 + or_ln268_9_fu_84965_p2); + +assign grp_fu_84982_p1 = 32'd28; + +assign grp_fu_85026_p0 = grp_fu_85026_p00; + +assign grp_fu_85026_p00 = add_ln276_59_reg_97399; + +assign grp_fu_85026_p1 = 65'd4908534053; + +assign grp_fu_85166_p0 = (add_ln276_65_reg_97408 + fw10_0_0_0_1_1_1_0_reg_73175); + +assign grp_fu_85166_p1 = 32'd28; + +assign grp_fu_85308_p0 = grp_fu_85308_p00; + +assign grp_fu_85308_p00 = add_ln276_68_reg_97579; + +assign grp_fu_85308_p1 = 65'd4908534053; + +assign grp_fu_85454_p0 = (add_ln276_65_reg_97408 + or_ln268_14_fu_85437_p2); + +assign grp_fu_85454_p1 = 32'd28; + +assign grp_fu_85469_p0 = grp_fu_85469_p00; + +assign grp_fu_85469_p00 = add_ln276_74_reg_97753; + +assign grp_fu_85469_p1 = 65'd4908534053; + +assign grp_fu_85918_p0 = (add_ln276_11_reg_98748 + fw10_0_0_1_0_0_0_0_reg_73223); + +assign grp_fu_85918_p1 = 32'd28; + +assign grp_fu_85927_p0 = grp_fu_85927_p00; + +assign grp_fu_85927_p00 = add_ln276_15_reg_98754; + +assign grp_fu_85927_p1 = 65'd4908534053; + +assign grp_fu_86223_p0 = (add_ln276_11_reg_98748 + or_ln268_1_fu_86206_p2); + +assign grp_fu_86223_p1 = 32'd28; + +assign grp_fu_86299_p0 = grp_fu_86299_p00; + +assign grp_fu_86299_p00 = add_ln276_24_reg_98928; + +assign grp_fu_86299_p1 = 65'd4908534053; + +assign grp_fu_86456_p0 = (add_ln276_31_reg_98937 + fw10_0_0_1_0_0_1_0_reg_73235); + +assign grp_fu_86456_p1 = 32'd28; + +assign grp_fu_86598_p0 = grp_fu_86598_p00; + +assign grp_fu_86598_p00 = add_ln276_39_reg_99119; + +assign grp_fu_86598_p1 = 65'd4908534053; + +assign grp_fu_86761_p0 = (add_ln276_31_reg_98937 + or_ln268_6_fu_86744_p2); + +assign grp_fu_86761_p1 = 32'd28; + +assign grp_fu_86776_p0 = grp_fu_86776_p00; + +assign grp_fu_86776_p00 = add_ln276_54_reg_99293; + +assign grp_fu_86776_p1 = 65'd4908534053; + +assign grp_fu_86950_p0 = (add_ln276_38_reg_99464 + fw10_0_0_1_0_1_0_0_reg_73259); + +assign grp_fu_86950_p1 = 32'd28; + +assign grp_fu_86959_p0 = grp_fu_86959_p00; + +assign grp_fu_86959_p00 = add_ln276_46_reg_99470; + +assign grp_fu_86959_p1 = 65'd4908534053; + +assign grp_fu_87239_p0 = (add_ln276_38_reg_99464 + or_ln268_8_fu_87222_p2); + +assign grp_fu_87239_p1 = 32'd28; + +assign grp_fu_87283_p0 = grp_fu_87283_p00; + +assign grp_fu_87283_p00 = add_ln276_58_reg_99644; + +assign grp_fu_87283_p1 = 65'd4908534053; + +assign grp_fu_87424_p0 = (add_ln276_63_reg_99653 + fw10_0_0_1_0_1_1_0_reg_73271); + +assign grp_fu_87424_p1 = 32'd28; + +assign grp_fu_87566_p0 = grp_fu_87566_p00; + +assign grp_fu_87566_p00 = add_ln276_67_reg_99824; + +assign grp_fu_87566_p1 = 65'd4908534053; + +assign grp_fu_87713_p0 = (add_ln276_63_reg_99653 + or_ln268_13_fu_87696_p2); + +assign grp_fu_87713_p1 = 32'd28; + +assign grp_fu_87728_p0 = grp_fu_87728_p00; + +assign grp_fu_87728_p00 = add_ln276_73_reg_99998; + +assign grp_fu_87728_p1 = 65'd4908534053; + +assign grp_fu_88009_p0 = (add_ln276_18_reg_100577 + fw10_0_0_1_1_0_0_0_reg_73307); + +assign grp_fu_88009_p1 = 32'd28; + +assign grp_fu_88018_p0 = grp_fu_88018_p00; + +assign grp_fu_88018_p00 = add_ln276_20_reg_100583; + +assign grp_fu_88018_p1 = 65'd4908534053; + +assign grp_fu_88314_p0 = (add_ln276_18_reg_100577 + or_ln268_3_fu_88297_p2); + +assign grp_fu_88314_p1 = 32'd28; + +assign grp_fu_88390_p0 = grp_fu_88390_p00; + +assign grp_fu_88390_p00 = add_ln276_36_reg_100757; + +assign grp_fu_88390_p1 = 65'd4908534053; + +assign grp_fu_88547_p0 = (add_ln276_45_reg_100766 + fw10_0_0_1_1_0_1_0_reg_73319); + +assign grp_fu_88547_p1 = 32'd28; + +assign grp_fu_88689_p0 = grp_fu_88689_p00; + +assign grp_fu_88689_p00 = add_ln276_51_reg_100948; + +assign grp_fu_88689_p1 = 65'd4908534053; + +assign grp_fu_88852_p0 = (add_ln276_45_reg_100766 + or_ln268_10_fu_88835_p2); + +assign grp_fu_88852_p1 = 32'd28; + +assign grp_fu_88867_p0 = grp_fu_88867_p00; + +assign grp_fu_88867_p00 = add_ln276_61_reg_101122; + +assign grp_fu_88867_p1 = 65'd4908534053; + +assign grp_fu_89041_p0 = (add_ln276_50_reg_101293 + fw10_0_0_1_1_1_0_0_reg_73343); + +assign grp_fu_89041_p1 = 32'd28; + +assign grp_fu_89050_p0 = grp_fu_89050_p00; + +assign grp_fu_89050_p00 = add_ln276_53_reg_101299; + +assign grp_fu_89050_p1 = 65'd4908534053; + +assign grp_fu_89329_p0 = (add_ln276_50_reg_101293 + or_ln268_11_fu_89312_p2); + +assign grp_fu_89329_p1 = 32'd28; + +assign grp_fu_89373_p0 = grp_fu_89373_p00; + +assign grp_fu_89373_p00 = add_ln276_66_reg_101473; + +assign grp_fu_89373_p1 = 65'd4908534053; + +assign grp_fu_89513_p0 = (add_ln276_70_reg_101482 + fw10_0_0_1_1_1_1_0_reg_73355); + +assign grp_fu_89513_p1 = 32'd28; + +assign grp_fu_89655_p0 = grp_fu_89655_p00; + +assign grp_fu_89655_p00 = add_ln276_72_reg_101653; + +assign grp_fu_89655_p1 = 65'd4908534053; + +assign grp_fu_89801_p0 = (add_ln276_70_reg_101482 + or_ln268_15_fu_89784_p2); + +assign grp_fu_89801_p1 = 32'd28; + +assign grp_fu_89816_p0 = grp_fu_89816_p00; + +assign grp_fu_89816_p00 = add_ln276_75_reg_101827; + +assign grp_fu_89816_p1 = 65'd4908534053; + +assign grp_fu_89969_p0 = 13'd100; + +assign grp_fu_89969_p1 = grp_fu_89969_p10; + +assign grp_fu_89969_p10 = ow6_0_0_0_reg_73007; + +assign grp_fu_89982_p0 = grp_fu_89982_p00; + +assign grp_fu_89982_p00 = ff7_0_0_0_0_reg_73019; + +assign grp_fu_89982_p1 = 9'd25; + +assign grp_fu_89990_p0 = 13'd100; + +assign grp_fu_89990_p1 = grp_fu_89990_p10; + +assign grp_fu_89990_p10 = or_ln259_fu_81687_p2; + +assign grp_fu_89997_p0 = 8'd25; + +assign grp_fu_89997_p1 = grp_fu_89997_p10; + +assign grp_fu_89997_p10 = or_ln261_fu_82047_p2; + +assign grp_fu_90005_p0 = grp_fu_90005_p00; + +assign grp_fu_90005_p00 = ff7_0_0_1_0_reg_73103; + +assign grp_fu_90005_p1 = 9'd25; + +assign grp_fu_90013_p0 = 8'd25; + +assign grp_fu_90013_p1 = grp_fu_90013_p10; + +assign grp_fu_90013_p10 = or_ln261_2_fu_84006_p2; + +assign grp_fu_90021_p0 = 13'd100; + +assign grp_fu_90021_p1 = grp_fu_90021_p10; + +assign grp_fu_90021_p10 = ow6_0_1_0_reg_73187; + +assign grp_fu_90028_p0 = grp_fu_90028_p00; + +assign grp_fu_90028_p00 = ff7_0_1_0_0_reg_73199; + +assign grp_fu_90028_p1 = 9'd25; + +assign grp_fu_90036_p0 = 13'd100; + +assign grp_fu_90036_p1 = grp_fu_90036_p10; + +assign grp_fu_90036_p10 = or_ln259_1_fu_85770_p2; + +assign grp_fu_90043_p0 = 8'd25; + +assign grp_fu_90043_p1 = grp_fu_90043_p10; + +assign grp_fu_90043_p10 = or_ln261_1_fu_86262_p2; + +assign grp_fu_90051_p0 = grp_fu_90051_p00; + +assign grp_fu_90051_p00 = ff7_0_1_1_0_reg_73283; + +assign grp_fu_90051_p1 = 9'd25; + +assign grp_fu_90059_p0 = 8'd25; + +assign grp_fu_90059_p1 = grp_fu_90059_p10; + +assign grp_fu_90059_p10 = or_ln261_3_fu_88353_p2; + +assign icmp_ln1116_10_fu_76568_p2 = ((tmp_168_fu_76554_p3 > empty_106_fu_76562_p2) ? 1'b1 : 1'b0); + +assign icmp_ln1116_11_fu_80029_p2 = ((tmp_187_fu_80015_p3 > empty_140_fu_80023_p2) ? 1'b1 : 1'b0); + +assign icmp_ln1116_12_fu_75238_p2 = ((tmp_203_fu_75225_p3 > empty_92_fu_75232_p2) ? 1'b1 : 1'b0); + +assign icmp_ln1116_13_fu_78698_p2 = ((tmp_220_fu_78685_p3 > empty_126_fu_78692_p2) ? 1'b1 : 1'b0); + +assign icmp_ln1116_14_fu_76918_p2 = ((tmp_224_fu_76905_p3 > empty_108_fu_76912_p2) ? 1'b1 : 1'b0); + +assign icmp_ln1116_15_fu_80379_p2 = ((tmp_232_fu_80366_p3 > empty_142_fu_80373_p2) ? 1'b1 : 1'b0); + +assign icmp_ln1116_1_fu_77525_p2 = ((tmp_57_fu_77511_p3 > empty_118_fu_77519_p2) ? 1'b1 : 1'b0); + +assign icmp_ln1116_2_fu_75754_p2 = ((tmp_61_fu_75740_p3 > empty_100_fu_75748_p2) ? 1'b1 : 1'b0); + +assign icmp_ln1116_3_fu_79217_p2 = ((tmp_76_fu_79203_p3 > empty_134_fu_79211_p2) ? 1'b1 : 1'b0); + +assign icmp_ln1116_4_fu_74515_p2 = ((tmp_92_fu_74501_p3 > empty_86_fu_74509_p2) ? 1'b1 : 1'b0); + +assign icmp_ln1116_5_fu_77975_p2 = ((tmp_120_fu_77961_p3 > empty_120_fu_77969_p2) ? 1'b1 : 1'b0); + +assign icmp_ln1116_6_fu_76205_p2 = ((tmp_124_fu_76191_p3 > empty_102_fu_76199_p2) ? 1'b1 : 1'b0); + +assign icmp_ln1116_7_fu_74888_p2 = ((tmp_129_fu_74874_p3 > empty_90_fu_74882_p2) ? 1'b1 : 1'b0); + +assign icmp_ln1116_8_fu_79666_p2 = ((tmp_159_fu_79653_p3 > empty_136_fu_79660_p2) ? 1'b1 : 1'b0); + +assign icmp_ln1116_9_fu_78348_p2 = ((tmp_164_fu_78334_p3 > empty_124_fu_78342_p2) ? 1'b1 : 1'b0); + +assign icmp_ln1116_fu_74064_p2 = ((tmp_42_fu_74050_p3 > empty_84_fu_74058_p2) ? 1'b1 : 1'b0); + +assign icmp_ln199_fu_73684_p2 = ((oh_0_0_reg_72639 == 5'd28) ? 1'b1 : 1'b0); + +assign icmp_ln201_1_fu_77164_p2 = ((ow_0_1_0_reg_72781 == 5'd28) ? 1'b1 : 1'b0); + +assign icmp_ln201_fu_73698_p2 = ((ow_0_0_0_reg_72651 == 5'd28) ? 1'b1 : 1'b0); + +assign icmp_ln203_1_fu_77216_p2 = ((ff_0_1_0_reg_72793 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln203_2_fu_75486_p2 = ((ff_0_0_1_reg_72722 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln203_3_fu_78946_p2 = ((ff_0_1_1_reg_72852 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln203_fu_73758_p2 = ((ff_0_0_0_reg_72663 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln206_1_fu_77787_p2 = ((or_ln206_1_fu_77781_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln206_2_fu_76016_p2 = ((or_ln206_2_fu_76010_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln206_3_fu_79499_p2 = ((or_ln206_3_fu_79493_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln206_fu_74326_p2 = ((or_ln206_fu_74320_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_1_fu_77694_p2 = ((or_ln208_1_fu_77688_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_2_fu_75923_p2 = ((or_ln208_2_fu_75917_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_3_fu_79386_p2 = ((or_ln208_3_fu_79380_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_4_fu_75057_p2 = ((or_ln208_4_fu_75051_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_5_fu_78517_p2 = ((or_ln208_5_fu_78511_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_6_fu_76737_p2 = ((or_ln208_6_fu_76731_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_7_fu_80198_p2 = ((or_ln208_7_fu_80192_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln208_fu_74233_p2 = ((or_ln208_fu_74227_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln223_10_fu_77420_p2 = ((tmp_9_fu_77410_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_11_fu_77426_p2 = ((add_ln223_5_fu_77405_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_12_fu_75658_p2 = ((tmp_10_fu_75648_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_13_fu_75664_p2 = ((add_ln223_6_fu_75643_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_14_fu_79122_p2 = ((tmp_66_fu_79112_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_15_fu_79128_p2 = ((add_ln223_7_fu_79107_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_16_fu_74359_p2 = ((tmp_83_fu_74349_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_17_fu_74365_p2 = ((add_ln223_8_fu_74344_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_18_fu_74271_p2 = ((tmp_84_fu_74261_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_19_fu_74277_p2 = ((add_ln223_9_fu_74256_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_1_fu_73847_p2 = ((add_ln223_fu_73826_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_20_fu_77820_p2 = ((tmp_104_fu_77810_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_21_fu_77826_p2 = ((add_ln223_10_fu_77805_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_22_fu_77732_p2 = ((tmp_105_fu_77722_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_23_fu_77738_p2 = ((add_ln223_11_fu_77717_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_24_fu_76049_p2 = ((tmp_107_fu_76039_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_25_fu_76055_p2 = ((add_ln223_12_fu_76034_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_26_fu_75961_p2 = ((tmp_108_fu_75951_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_27_fu_75967_p2 = ((add_ln223_13_fu_75946_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_28_fu_74783_p2 = ((tmp_109_fu_74773_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_29_fu_74789_p2 = ((add_ln223_14_fu_74768_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_2_fu_77299_p2 = ((tmp_2_fu_77289_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_30_fu_79532_p2 = ((tmp_143_fu_79522_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_31_fu_79538_p2 = ((add_ln223_15_fu_79517_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_32_fu_79424_p2 = ((tmp_144_fu_79414_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_33_fu_79430_p2 = ((add_ln223_16_fu_79409_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_34_fu_78243_p2 = ((tmp_145_fu_78233_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_35_fu_78249_p2 = ((add_ln223_17_fu_78228_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_36_fu_76473_p2 = ((tmp_146_fu_76463_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_37_fu_76479_p2 = ((add_ln223_18_fu_76458_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_38_fu_79934_p2 = ((tmp_177_fu_79924_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_39_fu_79940_p2 = ((add_ln223_19_fu_79919_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_3_fu_77305_p2 = ((add_ln223_1_fu_77284_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_40_fu_75095_p2 = ((tmp_197_fu_75085_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_41_fu_75101_p2 = ((add_ln223_20_fu_75080_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_42_fu_78555_p2 = ((tmp_214_fu_78545_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_43_fu_78561_p2 = ((add_ln223_21_fu_78540_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_44_fu_76775_p2 = ((tmp_215_fu_76765_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_45_fu_76781_p2 = ((add_ln223_22_fu_76760_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_46_fu_80236_p2 = ((tmp_233_fu_80226_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_47_fu_80242_p2 = ((add_ln223_23_fu_80221_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_4_fu_75541_p2 = ((tmp_3_fu_75531_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_5_fu_75547_p2 = ((add_ln223_2_fu_75526_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_6_fu_73958_p2 = ((tmp_4_fu_73948_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_7_fu_73964_p2 = ((add_ln223_3_fu_73943_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_8_fu_79001_p2 = ((tmp_8_fu_78991_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln223_9_fu_79007_p2 = ((add_ln223_4_fu_78986_p2 > 32'd29) ? 1'b1 : 1'b0); + +assign icmp_ln223_fu_73841_p2 = ((tmp_1_fu_73831_p4 == 31'd0) ? 1'b1 : 1'b0); + +assign icmp_ln244_fu_80617_p2 = ((oh2_0_0_reg_72911 == 5'd28) ? 1'b1 : 1'b0); + +assign icmp_ln246_1_fu_81063_p2 = ((ow3_0_1_0_reg_72959 == 5'd28) ? 1'b1 : 1'b0); + +assign icmp_ln246_fu_80657_p2 = ((ow3_0_0_0_reg_72923 == 5'd28) ? 1'b1 : 1'b0); + +assign icmp_ln248_1_fu_81191_p2 = ((ff4_0_1_0_0_reg_72971 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln248_2_fu_80953_p2 = ((ff4_0_0_1_0_reg_72947 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln248_3_fu_81329_p2 = ((ff4_0_1_1_0_reg_72983 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln248_fu_80819_p2 = ((ff4_0_0_0_0_reg_72935 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln257_fu_81443_p2 = ((oh5_0_0_reg_72995 == 5'd28) ? 1'b1 : 1'b0); + +assign icmp_ln259_1_fu_85608_p2 = ((ow6_0_1_0_reg_73187 == 5'd28) ? 1'b1 : 1'b0); + +assign icmp_ln259_fu_81487_p2 = ((ow6_0_0_0_reg_73007 == 5'd28) ? 1'b1 : 1'b0); + +assign icmp_ln261_1_fu_85740_p2 = ((ff7_0_1_0_0_reg_73199 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln261_2_fu_83525_p2 = ((ff7_0_0_1_0_reg_73103 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln261_3_fu_87872_p2 = ((ff7_0_1_1_0_reg_73283 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln261_fu_81657_p2 = ((ff7_0_0_0_0_reg_73019 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln266_1_fu_86235_p2 = ((or_ln266_1_fu_86229_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_2_fu_83979_p2 = ((or_ln266_2_fu_83973_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_3_fu_88326_p2 = ((or_ln266_3_fu_88320_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_4_fu_82904_p2 = ((or_ln266_4_fu_82898_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_5_fu_87251_p2 = ((or_ln266_5_fu_87245_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_6_fu_84994_p2 = ((or_ln266_6_fu_84988_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_7_fu_89341_p2 = ((or_ln266_7_fu_89335_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln266_fu_82020_p2 = ((or_ln266_fu_82014_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_10_fu_88841_p2 = ((or_ln268_10_fu_88835_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_11_fu_89318_p2 = ((or_ln268_11_fu_89312_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_12_fu_83355_p2 = ((or_ln268_12_fu_83349_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_13_fu_87702_p2 = ((or_ln268_13_fu_87696_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_14_fu_85443_p2 = ((or_ln268_14_fu_85437_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_15_fu_89790_p2 = ((or_ln268_15_fu_89784_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_1_fu_86212_p2 = ((or_ln268_1_fu_86206_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_2_fu_83956_p2 = ((or_ln268_2_fu_83950_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_3_fu_88303_p2 = ((or_ln268_3_fu_88297_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_4_fu_82403_p2 = ((or_ln268_4_fu_82397_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_5_fu_82881_p2 = ((or_ln268_5_fu_82875_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_6_fu_86750_p2 = ((or_ln268_6_fu_86744_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_7_fu_84494_p2 = ((or_ln268_7_fu_84488_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_8_fu_87228_p2 = ((or_ln268_8_fu_87222_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_9_fu_84971_p2 = ((or_ln268_9_fu_84965_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign icmp_ln268_fu_81997_p2 = ((or_ln268_fu_81991_p2 == 32'd5) ? 1'b1 : 1'b0); + +assign lshr_ln1116_10_fu_79986_p4 = {{add_ln1116_15_fu_79981_p2[10:3]}}; + +assign lshr_ln1116_11_fu_75129_p4 = {{add_ln1116_16_fu_75124_p2[10:3]}}; + +assign lshr_ln1116_12_fu_78589_p4 = {{add_ln1116_17_fu_78584_p2[10:3]}}; + +assign lshr_ln1116_13_fu_76809_p4 = {{add_ln1116_18_fu_76804_p2[10:3]}}; + +assign lshr_ln1116_14_fu_80270_p4 = {{add_ln1116_19_fu_80265_p2[10:3]}}; + +assign lshr_ln1116_15_fu_74149_p2 = 64'd18446744073709551615 >> zext_ln1116_19_fu_74146_p1; + +assign lshr_ln1116_16_fu_77601_p2 = select_ln1116_4_fu_77575_p3 >> zext_ln1116_22_fu_77597_p1; + +assign lshr_ln1116_17_fu_77610_p2 = 64'd18446744073709551615 >> zext_ln1116_23_fu_77607_p1; + +assign lshr_ln1116_18_fu_75830_p2 = select_ln1116_7_fu_75804_p3 >> zext_ln1116_26_fu_75826_p1; + +assign lshr_ln1116_19_fu_75839_p2 = 64'd18446744073709551615 >> zext_ln1116_27_fu_75836_p1; + +assign lshr_ln1116_1_fu_75710_p4 = {{add_ln1116_6_fu_75705_p2[10:3]}}; + +assign lshr_ln1116_20_fu_79293_p2 = select_ln1116_10_fu_79267_p3 >> zext_ln1116_30_fu_79289_p1; + +assign lshr_ln1116_21_fu_79302_p2 = 64'd18446744073709551615 >> zext_ln1116_31_fu_79299_p1; + +assign lshr_ln1116_22_fu_74591_p2 = select_ln1116_13_fu_74565_p3 >> zext_ln1116_34_fu_74587_p1; + +assign lshr_ln1116_23_fu_74600_p2 = 64'd18446744073709551615 >> zext_ln1116_35_fu_74597_p1; + +assign lshr_ln1116_24_fu_78051_p2 = select_ln1116_16_fu_78025_p3 >> zext_ln1116_38_fu_78047_p1; + +assign lshr_ln1116_25_fu_78060_p2 = 64'd18446744073709551615 >> zext_ln1116_39_fu_78057_p1; + +assign lshr_ln1116_26_fu_76281_p2 = select_ln1116_19_fu_76255_p3 >> zext_ln1116_42_fu_76277_p1; + +assign lshr_ln1116_27_fu_76290_p2 = 64'd18446744073709551615 >> zext_ln1116_43_fu_76287_p1; + +assign lshr_ln1116_28_fu_74964_p2 = select_ln1116_22_fu_74938_p3 >> zext_ln1116_46_fu_74960_p1; + +assign lshr_ln1116_29_fu_74973_p2 = 64'd18446744073709551615 >> zext_ln1116_47_fu_74970_p1; + +assign lshr_ln1116_2_fu_79174_p4 = {{add_ln1116_7_fu_79169_p2[10:3]}}; + +assign lshr_ln1116_30_fu_79742_p2 = select_ln1116_25_fu_79716_p3 >> zext_ln1116_50_fu_79738_p1; + +assign lshr_ln1116_31_fu_79751_p2 = 64'd18446744073709551615 >> zext_ln1116_51_fu_79748_p1; + +assign lshr_ln1116_32_fu_78424_p2 = select_ln1116_28_fu_78398_p3 >> zext_ln1116_54_fu_78420_p1; + +assign lshr_ln1116_33_fu_78433_p2 = 64'd18446744073709551615 >> zext_ln1116_55_fu_78430_p1; + +assign lshr_ln1116_34_fu_76644_p2 = select_ln1116_31_fu_76618_p3 >> zext_ln1116_58_fu_76640_p1; + +assign lshr_ln1116_35_fu_76653_p2 = 64'd18446744073709551615 >> zext_ln1116_59_fu_76650_p1; + +assign lshr_ln1116_36_fu_80105_p2 = select_ln1116_34_fu_80079_p3 >> zext_ln1116_62_fu_80101_p1; + +assign lshr_ln1116_37_fu_80114_p2 = 64'd18446744073709551615 >> zext_ln1116_63_fu_80111_p1; + +assign lshr_ln1116_38_fu_75314_p2 = select_ln1116_37_fu_75288_p3 >> zext_ln1116_66_fu_75310_p1; + +assign lshr_ln1116_39_fu_75323_p2 = 64'd18446744073709551615 >> zext_ln1116_67_fu_75320_p1; + +assign lshr_ln1116_3_fu_74305_p4 = {{add_ln1116_8_fu_74300_p2[10:3]}}; + +assign lshr_ln1116_40_fu_78774_p2 = select_ln1116_40_fu_78748_p3 >> zext_ln1116_70_fu_78770_p1; + +assign lshr_ln1116_41_fu_78783_p2 = 64'd18446744073709551615 >> zext_ln1116_71_fu_78780_p1; + +assign lshr_ln1116_42_fu_76994_p2 = select_ln1116_43_fu_76968_p3 >> zext_ln1116_74_fu_76990_p1; + +assign lshr_ln1116_43_fu_77003_p2 = 64'd18446744073709551615 >> zext_ln1116_75_fu_77000_p1; + +assign lshr_ln1116_44_fu_80455_p2 = select_ln1116_46_fu_80429_p3 >> zext_ln1116_78_fu_80451_p1; + +assign lshr_ln1116_45_fu_80464_p2 = 64'd18446744073709551615 >> zext_ln1116_79_fu_80461_p1; + +assign lshr_ln1116_4_fu_77766_p4 = {{add_ln1116_9_fu_77761_p2[10:3]}}; + +assign lshr_ln1116_5_fu_75995_p4 = {{add_ln1116_10_fu_75990_p2[10:3]}}; + +assign lshr_ln1116_6_fu_74835_p4 = {{add_ln1116_11_fu_74830_p2[10:3]}}; + +assign lshr_ln1116_7_fu_79458_p4 = {{add_ln1116_12_fu_79453_p2[10:3]}}; + +assign lshr_ln1116_8_fu_78295_p4 = {{add_ln1116_13_fu_78290_p2[10:3]}}; + +assign lshr_ln1116_9_fu_76525_p4 = {{add_ln1116_14_fu_76520_p2[10:3]}}; + +assign lshr_ln1116_fu_74140_p2 = select_ln1116_1_fu_74114_p3 >> zext_ln1116_18_fu_74136_p1; + +assign lshr_ln1116_s_fu_77472_p4 = {{add_ln1116_5_fu_77467_p2[10:3]}}; + +assign lshr_ln_fu_74010_p4 = {{add_ln1116_4_fu_74005_p2[10:3]}}; + +assign mul_ln1118_10_fu_77633_p0 = reg_73633; + +assign mul_ln1118_10_fu_77633_p1 = trunc_ln1116_3_fu_77621_p1; + +assign mul_ln1118_10_fu_77633_p2 = ((mul_ln1118_10_fu_77633_p0) * (mul_ln1118_10_fu_77633_p1)); + +assign mul_ln1118_11_fu_75862_p0 = reg_73633; + +assign mul_ln1118_11_fu_75862_p1 = trunc_ln1116_4_fu_75850_p1; + +assign mul_ln1118_11_fu_75862_p2 = ((mul_ln1118_11_fu_75862_p0) * (mul_ln1118_11_fu_75862_p1)); + +assign mul_ln1118_12_fu_79325_p0 = reg_73633; + +assign mul_ln1118_12_fu_79325_p1 = trunc_ln1116_5_fu_79313_p1; + +assign mul_ln1118_12_fu_79325_p2 = ((mul_ln1118_12_fu_79325_p0) * (mul_ln1118_12_fu_79325_p1)); + +assign mul_ln1118_13_fu_74623_p0 = reg_73633; + +assign mul_ln1118_13_fu_74623_p1 = trunc_ln1116_8_fu_74611_p1; + +assign mul_ln1118_13_fu_74623_p2 = ((mul_ln1118_13_fu_74623_p0) * (mul_ln1118_13_fu_74623_p1)); + +assign mul_ln1118_14_fu_78083_p0 = reg_73633; + +assign mul_ln1118_14_fu_78083_p1 = trunc_ln1116_12_fu_78071_p1; + +assign mul_ln1118_14_fu_78083_p2 = ((mul_ln1118_14_fu_78083_p0) * (mul_ln1118_14_fu_78083_p1)); + +assign mul_ln1118_15_fu_76313_p0 = reg_73633; + +assign mul_ln1118_15_fu_76313_p1 = trunc_ln1116_14_fu_76301_p1; + +assign mul_ln1118_15_fu_76313_p2 = ((mul_ln1118_15_fu_76313_p0) * (mul_ln1118_15_fu_76313_p1)); + +assign mul_ln1118_16_fu_74996_p0 = reg_73633; + +assign mul_ln1118_16_fu_74996_p1 = trunc_ln1116_15_fu_74984_p1; + +assign mul_ln1118_16_fu_74996_p2 = ((mul_ln1118_16_fu_74996_p0) * (mul_ln1118_16_fu_74996_p1)); + +assign mul_ln1118_17_fu_79774_p0 = reg_73633; + +assign mul_ln1118_17_fu_79774_p1 = trunc_ln1116_18_fu_79762_p1; + +assign mul_ln1118_17_fu_79774_p2 = ((mul_ln1118_17_fu_79774_p0) * (mul_ln1118_17_fu_79774_p1)); + +assign mul_ln1118_18_fu_78456_p0 = reg_73633; + +assign mul_ln1118_18_fu_78456_p1 = trunc_ln1116_19_fu_78444_p1; + +assign mul_ln1118_18_fu_78456_p2 = ((mul_ln1118_18_fu_78456_p0) * (mul_ln1118_18_fu_78456_p1)); + +assign mul_ln1118_19_fu_76676_p0 = reg_73633; + +assign mul_ln1118_19_fu_76676_p1 = trunc_ln1116_20_fu_76664_p1; + +assign mul_ln1118_19_fu_76676_p2 = ((mul_ln1118_19_fu_76676_p0) * (mul_ln1118_19_fu_76676_p1)); + +assign mul_ln1118_20_fu_80137_p0 = reg_73633; + +assign mul_ln1118_20_fu_80137_p1 = trunc_ln1116_21_fu_80125_p1; + +assign mul_ln1118_20_fu_80137_p2 = ((mul_ln1118_20_fu_80137_p0) * (mul_ln1118_20_fu_80137_p1)); + +assign mul_ln1118_21_fu_75346_p0 = reg_73633; + +assign mul_ln1118_21_fu_75346_p1 = trunc_ln1116_23_fu_75334_p1; + +assign mul_ln1118_21_fu_75346_p2 = ((mul_ln1118_21_fu_75346_p0) * (mul_ln1118_21_fu_75346_p1)); + +assign mul_ln1118_22_fu_78806_p0 = reg_73633; + +assign mul_ln1118_22_fu_78806_p1 = trunc_ln1116_25_fu_78794_p1; + +assign mul_ln1118_22_fu_78806_p2 = ((mul_ln1118_22_fu_78806_p0) * (mul_ln1118_22_fu_78806_p1)); + +assign mul_ln1118_23_fu_77026_p0 = reg_73633; + +assign mul_ln1118_23_fu_77026_p1 = trunc_ln1116_27_fu_77014_p1; + +assign mul_ln1118_23_fu_77026_p2 = ((mul_ln1118_23_fu_77026_p0) * (mul_ln1118_23_fu_77026_p1)); + +assign mul_ln1118_24_fu_80487_p0 = reg_73633; + +assign mul_ln1118_24_fu_80487_p1 = trunc_ln1116_29_fu_80475_p1; + +assign mul_ln1118_24_fu_80487_p2 = ((mul_ln1118_24_fu_80487_p0) * (mul_ln1118_24_fu_80487_p1)); + +assign mul_ln1118_fu_74172_p0 = reg_73633; + +assign mul_ln1118_fu_74172_p1 = trunc_ln1116_1_fu_74160_p1; + +assign mul_ln1118_fu_74172_p2 = ((mul_ln1118_fu_74172_p0) * (mul_ln1118_fu_74172_p1)); + +assign mul_ln201_1_fu_89957_p0 = mul_ln201_1_fu_89957_p00; + +assign mul_ln201_1_fu_89957_p00 = or_ln199_fu_73734_p2; + +assign mul_ln201_1_fu_89957_p1 = 17'd2800; + +assign mul_ln201_fu_89951_p0 = mul_ln201_fu_89951_p00; + +assign mul_ln201_fu_89951_p00 = oh_0_0_reg_72639; + +assign mul_ln201_fu_89951_p1 = 17'd2800; + +assign mul_ln231_1_fu_77170_p1 = mul_ln231_1_fu_77170_p10; + +assign mul_ln231_1_fu_77170_p10 = ow_0_1_0_reg_72781; + +assign mul_ln231_1_fu_77170_p2 = (12'd100 * mul_ln231_1_fu_77170_p1); + +assign mul_ln231_2_fu_73806_p0 = mul_ln231_2_fu_73806_p00; + +assign mul_ln231_2_fu_73806_p00 = or_ln201_fu_73792_p2; + +assign mul_ln231_2_fu_73806_p2 = (mul_ln231_2_fu_73806_p0 * ('h64)); + +assign mul_ln231_3_fu_77264_p0 = mul_ln231_3_fu_77264_p00; + +assign mul_ln231_3_fu_77264_p00 = or_ln201_1_fu_77250_p2; + +assign mul_ln231_3_fu_77264_p2 = (mul_ln231_3_fu_77264_p0 * ('h64)); + +assign mul_ln231_fu_73704_p1 = mul_ln231_fu_73704_p10; + +assign mul_ln231_fu_73704_p10 = ow_0_0_0_reg_72651; + +assign mul_ln231_fu_73704_p2 = (12'd100 * mul_ln231_fu_73704_p1); + +assign mul_ln279_1_fu_89976_p0 = 17'd2800; + +assign mul_ln279_1_fu_89976_p1 = mul_ln279_1_fu_89976_p10; + +assign mul_ln279_1_fu_89976_p10 = or_ln257_fu_81609_p2; + +assign mul_ln279_fu_89963_p0 = 17'd2800; + +assign mul_ln279_fu_89963_p1 = mul_ln279_fu_89963_p10; + +assign mul_ln279_fu_89963_p10 = oh5_0_0_reg_72995; + +assign oh_0_0_cast_fu_73676_p1 = oh_0_0_reg_72639; + +assign or_ln1265_1_fu_85755_p3 = {{tmp_48_fu_85746_p4}, {ff7_0_1_0_0_reg_73199}}; + +assign or_ln1265_2_fu_82066_p3 = {{tmp_89_fu_82057_p4}, {or_ln261_fu_82047_p2}}; + +assign or_ln1265_3_fu_86281_p3 = {{tmp_111_fu_86272_p4}, {or_ln261_1_fu_86262_p2}}; + +assign or_ln1265_4_fu_84025_p3 = {{tmp_114_fu_84016_p4}, {or_ln261_2_fu_84006_p2}}; + +assign or_ln1265_5_fu_88372_p3 = {{tmp_148_fu_88363_p4}, {or_ln261_3_fu_88353_p2}}; + +assign or_ln199_fu_73734_p2 = (oh_0_0_reg_72639 | 5'd1); + +assign or_ln201_1_fu_77250_p2 = (ow_0_1_0_reg_72781 | 5'd1); + +assign or_ln201_fu_73792_p2 = (ow_0_0_0_reg_72651 | 5'd1); + +assign or_ln203_1_fu_81206_p3 = {{tmp_38_fu_81197_p4}, {ff4_0_1_0_0_reg_72971}}; + +assign or_ln203_2_fu_80935_p3 = {{tmp_39_fu_80926_p4}, {or_ln203_fu_80920_p2}}; + +assign or_ln203_3_fu_81311_p3 = {{tmp_53_fu_81302_p4}, {or_ln203_6_fu_81296_p2}}; + +assign or_ln203_4_fu_81049_p3 = {{tmp_54_fu_81040_p4}, {or_ln203_7_fu_81034_p2}}; + +assign or_ln203_5_fu_81425_p3 = {{tmp_74_fu_81416_p4}, {or_ln203_8_fu_81410_p2}}; + +assign or_ln203_6_fu_81296_p2 = (empty_157_fu_81292_p1 | 2'd1); + +assign or_ln203_7_fu_81034_p2 = (empty_152_fu_81030_p1 | 2'd1); + +assign or_ln203_8_fu_81410_p2 = (empty_160_fu_81406_p1 | 2'd1); + +assign or_ln203_fu_80920_p2 = (empty_149_fu_80916_p1 | 2'd1); + +assign or_ln206_1_fu_77781_p2 = (fh_0_0_1_0_0_reg_72816 | 32'd1); + +assign or_ln206_2_fu_76010_p2 = (fh_0_0_0_1_0_reg_72745 | 32'd1); + +assign or_ln206_3_fu_79493_p2 = (fh_0_0_1_1_0_reg_72875 | 32'd1); + +assign or_ln206_fu_74320_p2 = (fh_0_0_0_0_0_reg_72686 | 32'd1); + +assign or_ln208_1_fu_77688_p2 = (fw_0_0_1_0_0_0_reg_72828 | 32'd1); + +assign or_ln208_2_fu_75917_p2 = (fw_0_0_0_1_0_0_reg_72757 | 32'd1); + +assign or_ln208_3_fu_79380_p2 = (fw_0_0_1_1_0_0_reg_72887 | 32'd1); + +assign or_ln208_4_fu_75051_p2 = (fw_0_0_0_0_1_0_reg_72710 | 32'd1); + +assign or_ln208_5_fu_78511_p2 = (fw_0_0_1_0_1_0_reg_72840 | 32'd1); + +assign or_ln208_6_fu_76731_p2 = (fw_0_0_0_1_1_0_reg_72769 | 32'd1); + +assign or_ln208_7_fu_80192_p2 = (fw_0_0_1_1_1_0_reg_72899 | 32'd1); + +assign or_ln208_fu_74227_p2 = (fw_0_0_0_0_0_0_reg_72698 | 32'd1); + +assign or_ln221_1_fu_77382_p3 = {{tmp_30_fu_77372_p4}, {ff_0_1_0_reg_72793}}; + +assign or_ln221_2_fu_75620_p3 = {{tmp_32_fu_75610_p4}, {ff_0_0_1_reg_72722}}; + +assign or_ln221_3_fu_79084_p3 = {{tmp_45_fu_79074_p4}, {ff_0_1_1_reg_72852}}; + +assign or_ln223_10_fu_77832_p2 = (icmp_ln223_21_fu_77826_p2 | icmp_ln223_20_fu_77820_p2); + +assign or_ln223_11_fu_77744_p2 = (icmp_ln223_23_fu_77738_p2 | icmp_ln223_22_fu_77732_p2); + +assign or_ln223_12_fu_76061_p2 = (icmp_ln223_25_fu_76055_p2 | icmp_ln223_24_fu_76049_p2); + +assign or_ln223_13_fu_75973_p2 = (icmp_ln223_27_fu_75967_p2 | icmp_ln223_26_fu_75961_p2); + +assign or_ln223_14_fu_74795_p2 = (icmp_ln223_29_fu_74789_p2 | icmp_ln223_28_fu_74783_p2); + +assign or_ln223_15_fu_79544_p2 = (icmp_ln223_31_fu_79538_p2 | icmp_ln223_30_fu_79532_p2); + +assign or_ln223_16_fu_79436_p2 = (icmp_ln223_33_fu_79430_p2 | icmp_ln223_32_fu_79424_p2); + +assign or_ln223_17_fu_78255_p2 = (icmp_ln223_35_fu_78249_p2 | icmp_ln223_34_fu_78243_p2); + +assign or_ln223_18_fu_76485_p2 = (icmp_ln223_37_fu_76479_p2 | icmp_ln223_36_fu_76473_p2); + +assign or_ln223_19_fu_79946_p2 = (icmp_ln223_39_fu_79940_p2 | icmp_ln223_38_fu_79934_p2); + +assign or_ln223_1_fu_77311_p2 = (icmp_ln223_3_fu_77305_p2 | icmp_ln223_2_fu_77299_p2); + +assign or_ln223_20_fu_75107_p2 = (icmp_ln223_41_fu_75101_p2 | icmp_ln223_40_fu_75095_p2); + +assign or_ln223_21_fu_78567_p2 = (icmp_ln223_43_fu_78561_p2 | icmp_ln223_42_fu_78555_p2); + +assign or_ln223_22_fu_76787_p2 = (icmp_ln223_45_fu_76781_p2 | icmp_ln223_44_fu_76775_p2); + +assign or_ln223_23_fu_80248_p2 = (icmp_ln223_47_fu_80242_p2 | icmp_ln223_46_fu_80236_p2); + +assign or_ln223_2_fu_75553_p2 = (icmp_ln223_5_fu_75547_p2 | icmp_ln223_4_fu_75541_p2); + +assign or_ln223_3_fu_73970_p2 = (icmp_ln223_7_fu_73964_p2 | icmp_ln223_6_fu_73958_p2); + +assign or_ln223_4_fu_79013_p2 = (icmp_ln223_9_fu_79007_p2 | icmp_ln223_8_fu_79001_p2); + +assign or_ln223_5_fu_77432_p2 = (icmp_ln223_11_fu_77426_p2 | icmp_ln223_10_fu_77420_p2); + +assign or_ln223_6_fu_75670_p2 = (icmp_ln223_13_fu_75664_p2 | icmp_ln223_12_fu_75658_p2); + +assign or_ln223_7_fu_79134_p2 = (icmp_ln223_15_fu_79128_p2 | icmp_ln223_14_fu_79122_p2); + +assign or_ln223_8_fu_74371_p2 = (icmp_ln223_17_fu_74365_p2 | icmp_ln223_16_fu_74359_p2); + +assign or_ln223_9_fu_74283_p2 = (icmp_ln223_19_fu_74277_p2 | icmp_ln223_18_fu_74271_p2); + +assign or_ln223_fu_73853_p2 = (icmp_ln223_fu_73841_p2 | icmp_ln223_1_fu_73847_p2); + +assign or_ln231_1_fu_77750_p2 = (trunc_ln208_1_fu_77684_p1 | 11'd1); + +assign or_ln231_2_fu_75979_p2 = (trunc_ln208_2_fu_75913_p1 | 11'd1); + +assign or_ln231_3_fu_79442_p2 = (trunc_ln208_3_fu_79376_p1 | 11'd1); + +assign or_ln231_4_fu_75113_p2 = (trunc_ln208_4_fu_75047_p1 | 11'd1); + +assign or_ln231_5_fu_78573_p2 = (trunc_ln208_5_fu_78507_p1 | 11'd1); + +assign or_ln231_6_fu_76793_p2 = (trunc_ln208_6_fu_76727_p1 | 11'd1); + +assign or_ln231_7_fu_80254_p2 = (trunc_ln208_7_fu_80188_p1 | 11'd1); + +assign or_ln231_fu_74289_p2 = (trunc_ln208_fu_74223_p1 | 11'd1); + +assign or_ln244_fu_80779_p2 = (oh2_0_0_reg_72911 | 5'd1); + +assign or_ln250_1_fu_81214_p2 = (shl_ln250_2_reg_92657 | 7'd4); + +assign or_ln250_2_fu_80851_p2 = (trunc_ln250_8_reg_92107 | 6'd4); + +assign or_ln250_3_fu_81223_p2 = (trunc_ln250_9_reg_92662 | 6'd4); + +assign or_ln250_fu_80842_p2 = (shl_ln250_1_reg_92102 | 7'd4); + +assign or_ln257_fu_81609_p2 = (oh5_0_0_reg_72995 | 5'd1); + +assign or_ln259_1_fu_85770_p2 = (ow6_0_1_0_reg_73187 | 5'd1); + +assign or_ln259_fu_81687_p2 = (ow6_0_0_0_reg_73007 | 5'd1); + +assign or_ln261_1_fu_86262_p2 = (empty_204_fu_86258_p1 | 2'd1); + +assign or_ln261_2_fu_84006_p2 = (empty_187_fu_84002_p1 | 2'd1); + +assign or_ln261_3_fu_88353_p2 = (empty_219_fu_88349_p1 | 2'd1); + +assign or_ln261_fu_82047_p2 = (empty_172_fu_82043_p1 | 2'd1); + +assign or_ln266_1_fu_86229_p2 = (fh9_0_0_1_0_0_0_reg_73211 | 32'd1); + +assign or_ln266_2_fu_83973_p2 = (fh9_0_0_0_1_0_0_reg_73115 | 32'd1); + +assign or_ln266_3_fu_88320_p2 = (fh9_0_0_1_1_0_0_reg_73295 | 32'd1); + +assign or_ln266_4_fu_82898_p2 = (fh9_0_0_0_0_1_0_reg_73067 | 32'd1); + +assign or_ln266_5_fu_87245_p2 = (fh9_0_0_1_0_1_0_reg_73247 | 32'd1); + +assign or_ln266_6_fu_84988_p2 = (fh9_0_0_0_1_1_0_reg_73151 | 32'd1); + +assign or_ln266_7_fu_89335_p2 = (fh9_0_0_1_1_1_0_reg_73331 | 32'd1); + +assign or_ln266_fu_82014_p2 = (fh9_0_0_0_0_0_0_reg_73031 | 32'd1); + +assign or_ln268_10_fu_88835_p2 = (fw10_0_0_1_1_0_1_0_reg_73319 | 32'd1); + +assign or_ln268_11_fu_89312_p2 = (fw10_0_0_1_1_1_0_0_reg_73343 | 32'd1); + +assign or_ln268_12_fu_83349_p2 = (fw10_0_0_0_0_1_1_0_reg_73091 | 32'd1); + +assign or_ln268_13_fu_87696_p2 = (fw10_0_0_1_0_1_1_0_reg_73271 | 32'd1); + +assign or_ln268_14_fu_85437_p2 = (fw10_0_0_0_1_1_1_0_reg_73175 | 32'd1); + +assign or_ln268_15_fu_89784_p2 = (fw10_0_0_1_1_1_1_0_reg_73355 | 32'd1); + +assign or_ln268_1_fu_86206_p2 = (fw10_0_0_1_0_0_0_0_reg_73223 | 32'd1); + +assign or_ln268_2_fu_83950_p2 = (fw10_0_0_0_1_0_0_0_reg_73127 | 32'd1); + +assign or_ln268_3_fu_88297_p2 = (fw10_0_0_1_1_0_0_0_reg_73307 | 32'd1); + +assign or_ln268_4_fu_82397_p2 = (fw10_0_0_0_0_0_1_0_reg_73055 | 32'd1); + +assign or_ln268_5_fu_82875_p2 = (fw10_0_0_0_0_1_0_0_reg_73079 | 32'd1); + +assign or_ln268_6_fu_86744_p2 = (fw10_0_0_1_0_0_1_0_reg_73235 | 32'd1); + +assign or_ln268_7_fu_84488_p2 = (fw10_0_0_0_1_0_1_0_reg_73139 | 32'd1); + +assign or_ln268_8_fu_87222_p2 = (fw10_0_0_1_0_1_0_0_reg_73259 | 32'd1); + +assign or_ln268_9_fu_84965_p2 = (fw10_0_0_0_1_1_0_0_reg_73163 | 32'd1); + +assign or_ln268_fu_81991_p2 = (fw10_0_0_0_0_0_0_0_reg_73043 | 32'd1); + +assign or_ln2_fu_80834_p3 = {{tmp_25_fu_80825_p4}, {ff4_0_0_0_0_reg_72935}}; + +assign or_ln3_fu_81672_p3 = {{tmp_36_fu_81663_p4}, {ff7_0_0_0_0_reg_73019}}; + +assign or_ln_fu_73920_p3 = {{tmp_20_fu_73910_p4}, {ff_0_0_0_reg_72663}}; + +assign ow_0_0_0_cast_fu_73690_p1 = ow_0_0_0_reg_72651; + +assign ow_0_1_0_cast_fu_77156_p1 = ow_0_1_0_reg_72781; + +assign res_0_V_d0 = acc_0_V_q0; + +assign res_100_V_d0 = acc_36_V_q1; + +assign res_101_V_d0 = acc_37_V_q1; + +assign res_102_V_d0 = acc_38_V_q1; + +assign res_103_V_d0 = acc_39_V_q1; + +assign res_104_V_d0 = acc_40_V_q1; + +assign res_105_V_d0 = acc_41_V_q1; + +assign res_106_V_d0 = acc_42_V_q1; + +assign res_107_V_d0 = acc_43_V_q1; + +assign res_108_V_d0 = acc_44_V_q1; + +assign res_109_V_d0 = acc_45_V_q1; + +assign res_10_V_d0 = acc_10_V_q0; + +assign res_110_V_d0 = acc_46_V_q1; + +assign res_111_V_d0 = acc_47_V_q1; + +assign res_112_V_d0 = acc_48_V_q1; + +assign res_113_V_d0 = acc_49_V_q1; + +assign res_114_V_d0 = acc_50_V_q1; + +assign res_115_V_d0 = acc_51_V_q1; + +assign res_116_V_d0 = acc_52_V_q1; + +assign res_117_V_d0 = acc_53_V_q1; + +assign res_118_V_d0 = acc_54_V_q1; + +assign res_119_V_d0 = acc_55_V_q1; + +assign res_11_V_d0 = acc_11_V_q0; + +assign res_120_V_d0 = acc_56_V_q1; + +assign res_121_V_d0 = acc_57_V_q1; + +assign res_122_V_d0 = acc_58_V_q1; + +assign res_123_V_d0 = acc_59_V_q1; + +assign res_124_V_d0 = acc_60_V_q1; + +assign res_125_V_d0 = acc_61_V_q1; + +assign res_126_V_d0 = acc_62_V_q1; + +assign res_127_V_d0 = acc_63_V_q1; + +assign res_12_V_d0 = acc_12_V_q0; + +assign res_13_V_d0 = acc_13_V_q0; + +assign res_14_V_d0 = acc_14_V_q0; + +assign res_15_V_d0 = acc_15_V_q0; + +assign res_16_V_d0 = acc_16_V_q0; + +assign res_17_V_d0 = acc_17_V_q0; + +assign res_18_V_d0 = acc_18_V_q0; + +assign res_19_V_d0 = acc_19_V_q0; + +assign res_1_V_d0 = acc_1_V_q0; + +assign res_20_V_d0 = acc_20_V_q0; + +assign res_21_V_d0 = acc_21_V_q0; + +assign res_22_V_d0 = acc_22_V_q0; + +assign res_23_V_d0 = acc_23_V_q0; + +assign res_24_V_d0 = acc_24_V_q0; + +assign res_25_V_d0 = acc_25_V_q0; + +assign res_26_V_d0 = acc_26_V_q0; + +assign res_27_V_d0 = acc_27_V_q0; + +assign res_28_V_d0 = acc_28_V_q0; + +assign res_29_V_d0 = acc_29_V_q0; + +assign res_2_V_d0 = acc_2_V_q0; + +assign res_30_V_d0 = acc_30_V_q0; + +assign res_31_V_d0 = acc_31_V_q0; + +assign res_32_V_d0 = acc_32_V_q0; + +assign res_33_V_d0 = acc_33_V_q0; + +assign res_34_V_d0 = acc_34_V_q0; + +assign res_35_V_d0 = acc_35_V_q0; + +assign res_36_V_d0 = acc_36_V_q0; + +assign res_37_V_d0 = acc_37_V_q0; + +assign res_38_V_d0 = acc_38_V_q0; + +assign res_39_V_d0 = acc_39_V_q0; + +assign res_3_V_d0 = acc_3_V_q0; + +assign res_40_V_d0 = acc_40_V_q0; + +assign res_41_V_d0 = acc_41_V_q0; + +assign res_42_V_d0 = acc_42_V_q0; + +assign res_43_V_d0 = acc_43_V_q0; + +assign res_44_V_d0 = acc_44_V_q0; + +assign res_45_V_d0 = acc_45_V_q0; + +assign res_46_V_d0 = acc_46_V_q0; + +assign res_47_V_d0 = acc_47_V_q0; + +assign res_48_V_d0 = acc_48_V_q0; + +assign res_49_V_d0 = acc_49_V_q0; + +assign res_4_V_d0 = acc_4_V_q0; + +assign res_50_V_d0 = acc_50_V_q0; + +assign res_51_V_d0 = acc_51_V_q0; + +assign res_52_V_d0 = acc_52_V_q0; + +assign res_53_V_d0 = acc_53_V_q0; + +assign res_54_V_d0 = acc_54_V_q0; + +assign res_55_V_d0 = acc_55_V_q0; + +assign res_56_V_d0 = acc_56_V_q0; + +assign res_57_V_d0 = acc_57_V_q0; + +assign res_58_V_d0 = acc_58_V_q0; + +assign res_59_V_d0 = acc_59_V_q0; + +assign res_5_V_d0 = acc_5_V_q0; + +assign res_60_V_d0 = acc_60_V_q0; + +assign res_61_V_d0 = acc_61_V_q0; + +assign res_62_V_d0 = acc_62_V_q0; + +assign res_63_V_d0 = acc_63_V_q0; + +assign res_64_V_d0 = acc_0_V_q1; + +assign res_65_V_d0 = acc_1_V_q1; + +assign res_66_V_d0 = acc_2_V_q1; + +assign res_67_V_d0 = acc_3_V_q1; + +assign res_68_V_d0 = acc_4_V_q1; + +assign res_69_V_d0 = acc_5_V_q1; + +assign res_6_V_d0 = acc_6_V_q0; + +assign res_70_V_d0 = acc_6_V_q1; + +assign res_71_V_d0 = acc_7_V_q1; + +assign res_72_V_d0 = acc_8_V_q1; + +assign res_73_V_d0 = acc_9_V_q1; + +assign res_74_V_d0 = acc_10_V_q1; + +assign res_75_V_d0 = acc_11_V_q1; + +assign res_76_V_d0 = acc_12_V_q1; + +assign res_77_V_d0 = acc_13_V_q1; + +assign res_78_V_d0 = acc_14_V_q1; + +assign res_79_V_d0 = acc_15_V_q1; + +assign res_7_V_d0 = acc_7_V_q0; + +assign res_80_V_d0 = acc_16_V_q1; + +assign res_81_V_d0 = acc_17_V_q1; + +assign res_82_V_d0 = acc_18_V_q1; + +assign res_83_V_d0 = acc_19_V_q1; + +assign res_84_V_d0 = acc_20_V_q1; + +assign res_85_V_d0 = acc_21_V_q1; + +assign res_86_V_d0 = acc_22_V_q1; + +assign res_87_V_d0 = acc_23_V_q1; + +assign res_88_V_d0 = acc_24_V_q1; + +assign res_89_V_d0 = acc_25_V_q1; + +assign res_8_V_d0 = acc_8_V_q0; + +assign res_90_V_d0 = acc_26_V_q1; + +assign res_91_V_d0 = acc_27_V_q1; + +assign res_92_V_d0 = acc_28_V_q1; + +assign res_93_V_d0 = acc_29_V_q1; + +assign res_94_V_d0 = acc_30_V_q1; + +assign res_95_V_d0 = acc_31_V_q1; + +assign res_96_V_d0 = acc_32_V_q1; + +assign res_97_V_d0 = acc_33_V_q1; + +assign res_98_V_d0 = acc_34_V_q1; + +assign res_99_V_d0 = acc_35_V_q1; + +assign res_9_V_d0 = acc_9_V_q0; + +assign select_ln1116_10_fu_79267_p3 = ((icmp_ln1116_3_fu_79217_p2[0:0] == 1'b1) ? tmp_77_fu_79231_p4 : data_V_q0); + +assign select_ln1116_11_fu_79275_p3 = ((icmp_ln1116_3_fu_79217_p2[0:0] == 1'b1) ? xor_ln1116_3_fu_79247_p2 : zext_ln1116_28_fu_79223_p1); + +assign select_ln1116_12_fu_74557_p3 = ((icmp_ln1116_4_fu_74515_p2[0:0] == 1'b1) ? sub_ln1116_12_fu_74539_p2 : sub_ln1116_13_fu_74551_p2); + +assign select_ln1116_13_fu_74565_p3 = ((icmp_ln1116_4_fu_74515_p2[0:0] == 1'b1) ? tmp_93_fu_74529_p4 : data_V_q0); + +assign select_ln1116_14_fu_74573_p3 = ((icmp_ln1116_4_fu_74515_p2[0:0] == 1'b1) ? xor_ln1116_4_fu_74545_p2 : zext_ln1116_32_fu_74521_p1); + +assign select_ln1116_15_fu_78017_p3 = ((icmp_ln1116_5_fu_77975_p2[0:0] == 1'b1) ? sub_ln1116_15_fu_77999_p2 : sub_ln1116_16_fu_78011_p2); + +assign select_ln1116_16_fu_78025_p3 = ((icmp_ln1116_5_fu_77975_p2[0:0] == 1'b1) ? tmp_121_fu_77989_p4 : data_V_q0); + +assign select_ln1116_17_fu_78033_p3 = ((icmp_ln1116_5_fu_77975_p2[0:0] == 1'b1) ? xor_ln1116_5_fu_78005_p2 : zext_ln1116_36_fu_77981_p1); + +assign select_ln1116_18_fu_76247_p3 = ((icmp_ln1116_6_fu_76205_p2[0:0] == 1'b1) ? sub_ln1116_18_fu_76229_p2 : sub_ln1116_19_fu_76241_p2); + +assign select_ln1116_19_fu_76255_p3 = ((icmp_ln1116_6_fu_76205_p2[0:0] == 1'b1) ? tmp_125_fu_76219_p4 : data_V_q0); + +assign select_ln1116_1_fu_74114_p3 = ((icmp_ln1116_fu_74064_p2[0:0] == 1'b1) ? tmp_6_fu_74078_p4 : data_V_q0); + +assign select_ln1116_20_fu_76263_p3 = ((icmp_ln1116_6_fu_76205_p2[0:0] == 1'b1) ? xor_ln1116_6_fu_76235_p2 : zext_ln1116_40_fu_76211_p1); + +assign select_ln1116_21_fu_74930_p3 = ((icmp_ln1116_7_fu_74888_p2[0:0] == 1'b1) ? sub_ln1116_21_fu_74912_p2 : sub_ln1116_22_fu_74924_p2); + +assign select_ln1116_22_fu_74938_p3 = ((icmp_ln1116_7_fu_74888_p2[0:0] == 1'b1) ? tmp_130_fu_74902_p4 : data_V_q0); + +assign select_ln1116_23_fu_74946_p3 = ((icmp_ln1116_7_fu_74888_p2[0:0] == 1'b1) ? xor_ln1116_7_fu_74918_p2 : zext_ln1116_44_fu_74894_p1); + +assign select_ln1116_24_fu_79708_p3 = ((icmp_ln1116_8_fu_79666_p2[0:0] == 1'b1) ? sub_ln1116_24_fu_79690_p2 : sub_ln1116_25_fu_79702_p2); + +assign select_ln1116_25_fu_79716_p3 = ((icmp_ln1116_8_fu_79666_p2[0:0] == 1'b1) ? tmp_160_fu_79680_p4 : data_V_q0); + +assign select_ln1116_26_fu_79724_p3 = ((icmp_ln1116_8_fu_79666_p2[0:0] == 1'b1) ? xor_ln1116_8_fu_79696_p2 : zext_ln1116_48_fu_79672_p1); + +assign select_ln1116_27_fu_78390_p3 = ((icmp_ln1116_9_fu_78348_p2[0:0] == 1'b1) ? sub_ln1116_27_fu_78372_p2 : sub_ln1116_28_fu_78384_p2); + +assign select_ln1116_28_fu_78398_p3 = ((icmp_ln1116_9_fu_78348_p2[0:0] == 1'b1) ? tmp_165_fu_78362_p4 : data_V_q0); + +assign select_ln1116_29_fu_78406_p3 = ((icmp_ln1116_9_fu_78348_p2[0:0] == 1'b1) ? xor_ln1116_9_fu_78378_p2 : zext_ln1116_52_fu_78354_p1); + +assign select_ln1116_2_fu_74122_p3 = ((icmp_ln1116_fu_74064_p2[0:0] == 1'b1) ? xor_ln1116_fu_74094_p2 : zext_ln1116_16_fu_74070_p1); + +assign select_ln1116_30_fu_76610_p3 = ((icmp_ln1116_10_fu_76568_p2[0:0] == 1'b1) ? sub_ln1116_30_fu_76592_p2 : sub_ln1116_31_fu_76604_p2); + +assign select_ln1116_31_fu_76618_p3 = ((icmp_ln1116_10_fu_76568_p2[0:0] == 1'b1) ? tmp_169_fu_76582_p4 : data_V_q0); + +assign select_ln1116_32_fu_76626_p3 = ((icmp_ln1116_10_fu_76568_p2[0:0] == 1'b1) ? xor_ln1116_10_fu_76598_p2 : zext_ln1116_56_fu_76574_p1); + +assign select_ln1116_33_fu_80071_p3 = ((icmp_ln1116_11_fu_80029_p2[0:0] == 1'b1) ? sub_ln1116_33_fu_80053_p2 : sub_ln1116_34_fu_80065_p2); + +assign select_ln1116_34_fu_80079_p3 = ((icmp_ln1116_11_fu_80029_p2[0:0] == 1'b1) ? tmp_188_fu_80043_p4 : data_V_q0); + +assign select_ln1116_35_fu_80087_p3 = ((icmp_ln1116_11_fu_80029_p2[0:0] == 1'b1) ? xor_ln1116_11_fu_80059_p2 : zext_ln1116_60_fu_80035_p1); + +assign select_ln1116_36_fu_75280_p3 = ((icmp_ln1116_12_fu_75238_p2[0:0] == 1'b1) ? sub_ln1116_36_fu_75262_p2 : sub_ln1116_37_fu_75274_p2); + +assign select_ln1116_37_fu_75288_p3 = ((icmp_ln1116_12_fu_75238_p2[0:0] == 1'b1) ? tmp_204_fu_75252_p4 : data_V_q0); + +assign select_ln1116_38_fu_75296_p3 = ((icmp_ln1116_12_fu_75238_p2[0:0] == 1'b1) ? xor_ln1116_12_fu_75268_p2 : zext_ln1116_64_fu_75244_p1); + +assign select_ln1116_39_fu_78740_p3 = ((icmp_ln1116_13_fu_78698_p2[0:0] == 1'b1) ? sub_ln1116_39_fu_78722_p2 : sub_ln1116_40_fu_78734_p2); + +assign select_ln1116_3_fu_77567_p3 = ((icmp_ln1116_1_fu_77525_p2[0:0] == 1'b1) ? sub_ln1116_3_fu_77549_p2 : sub_ln1116_4_fu_77561_p2); + +assign select_ln1116_40_fu_78748_p3 = ((icmp_ln1116_13_fu_78698_p2[0:0] == 1'b1) ? tmp_221_fu_78712_p4 : data_V_q0); + +assign select_ln1116_41_fu_78756_p3 = ((icmp_ln1116_13_fu_78698_p2[0:0] == 1'b1) ? xor_ln1116_13_fu_78728_p2 : zext_ln1116_68_fu_78704_p1); + +assign select_ln1116_42_fu_76960_p3 = ((icmp_ln1116_14_fu_76918_p2[0:0] == 1'b1) ? sub_ln1116_42_fu_76942_p2 : sub_ln1116_43_fu_76954_p2); + +assign select_ln1116_43_fu_76968_p3 = ((icmp_ln1116_14_fu_76918_p2[0:0] == 1'b1) ? tmp_225_fu_76932_p4 : data_V_q0); + +assign select_ln1116_44_fu_76976_p3 = ((icmp_ln1116_14_fu_76918_p2[0:0] == 1'b1) ? xor_ln1116_14_fu_76948_p2 : zext_ln1116_72_fu_76924_p1); + +assign select_ln1116_45_fu_80421_p3 = ((icmp_ln1116_15_fu_80379_p2[0:0] == 1'b1) ? sub_ln1116_45_fu_80403_p2 : sub_ln1116_46_fu_80415_p2); + +assign select_ln1116_46_fu_80429_p3 = ((icmp_ln1116_15_fu_80379_p2[0:0] == 1'b1) ? tmp_238_fu_80393_p4 : data_V_q0); + +assign select_ln1116_47_fu_80437_p3 = ((icmp_ln1116_15_fu_80379_p2[0:0] == 1'b1) ? xor_ln1116_15_fu_80409_p2 : zext_ln1116_76_fu_80385_p1); + +assign select_ln1116_4_fu_77575_p3 = ((icmp_ln1116_1_fu_77525_p2[0:0] == 1'b1) ? tmp_58_fu_77539_p4 : data_V_q0); + +assign select_ln1116_5_fu_77583_p3 = ((icmp_ln1116_1_fu_77525_p2[0:0] == 1'b1) ? xor_ln1116_1_fu_77555_p2 : zext_ln1116_20_fu_77531_p1); + +assign select_ln1116_6_fu_75796_p3 = ((icmp_ln1116_2_fu_75754_p2[0:0] == 1'b1) ? sub_ln1116_6_fu_75778_p2 : sub_ln1116_7_fu_75790_p2); + +assign select_ln1116_7_fu_75804_p3 = ((icmp_ln1116_2_fu_75754_p2[0:0] == 1'b1) ? tmp_62_fu_75768_p4 : data_V_q0); + +assign select_ln1116_8_fu_75812_p3 = ((icmp_ln1116_2_fu_75754_p2[0:0] == 1'b1) ? xor_ln1116_2_fu_75784_p2 : zext_ln1116_24_fu_75760_p1); + +assign select_ln1116_9_fu_79259_p3 = ((icmp_ln1116_3_fu_79217_p2[0:0] == 1'b1) ? sub_ln1116_9_fu_79241_p2 : sub_ln1116_10_fu_79253_p2); + +assign select_ln1116_fu_74106_p3 = ((icmp_ln1116_fu_74064_p2[0:0] == 1'b1) ? sub_ln1116_fu_74088_p2 : sub_ln1116_1_fu_74100_p2); + +assign sext_ln1265_1_fu_85658_p1 = (trunc_ln1265_8_fu_85648_p4); + +assign sext_ln1265_2_fu_81741_p1 = (trunc_ln1265_9_fu_81731_p4); + +assign sext_ln1265_3_fu_85824_p1 = (trunc_ln1265_s_fu_85814_p4); + +assign sext_ln1265_4_fu_83559_p1 = (trunc_ln1265_1_fu_83549_p4); + +assign sext_ln1265_5_fu_87906_p1 = (trunc_ln1265_2_fu_87896_p4); + +assign sext_ln1265_fu_81537_p1 = (trunc_ln7_fu_81527_p4); + +assign sext_ln203_3_fu_81113_p1 = (trunc_ln203_1_fu_81103_p4); + +assign sext_ln203_4_fu_80876_p1 = (trunc_ln203_2_fu_80866_p4); + +assign sext_ln203_5_fu_81252_p1 = (trunc_ln203_3_fu_81242_p4); + +assign sext_ln203_6_fu_80983_p1 = (trunc_ln203_4_fu_80973_p4); + +assign sext_ln203_7_fu_81359_p1 = (trunc_ln203_6_fu_81349_p4); + +assign sext_ln203_fu_80707_p1 = (trunc_ln203_s_fu_80697_p4); + +assign sext_ln231_1_fu_77186_p1 = (add_ln231_1_fu_77180_p2); + +assign sext_ln231_2_fu_73817_p1 = (add_ln231_2_fu_73812_p2); + +assign sext_ln231_3_fu_77275_p1 = (add_ln231_4_fu_77270_p2); + +assign sext_ln231_fu_73720_p1 = (add_ln231_fu_73714_p2); + +assign sext_ln250_fu_81233_p1 = add_ln250_6_fu_81228_p2; + +assign shl_ln216_1_fu_77343_p2 = fh_0_0_1_0_0_reg_72816 << 32'd2; + +assign shl_ln216_2_fu_75581_p2 = fh_0_0_0_1_0_reg_72745 << 32'd2; + +assign shl_ln216_3_fu_79045_p2 = fh_0_0_1_1_0_reg_72875 << 32'd2; + +assign shl_ln216_4_fu_74332_p2 = or_ln206_fu_74320_p2 << 32'd2; + +assign shl_ln216_5_fu_77793_p2 = or_ln206_1_fu_77781_p2 << 32'd2; + +assign shl_ln216_6_fu_76022_p2 = or_ln206_2_fu_76010_p2 << 32'd2; + +assign shl_ln216_7_fu_79505_p2 = or_ln206_3_fu_79493_p2 << 32'd2; + +assign shl_ln216_fu_73881_p2 = fh_0_0_0_0_0_reg_72686 << 32'd2; + +assign shl_ln221_10_fu_77706_p2 = or_ln208_1_fu_77688_p2 << 32'd2; + +assign shl_ln221_11_fu_75935_p2 = or_ln208_2_fu_75917_p2 << 32'd2; + +assign shl_ln221_12_fu_74757_p2 = fw_0_0_0_0_1_0_reg_72710 << 32'd2; + +assign shl_ln221_13_fu_77799_p2 = or_ln206_1_fu_77781_p2 << 32'd4; + +assign shl_ln221_14_fu_76028_p2 = or_ln206_2_fu_76010_p2 << 32'd4; + +assign shl_ln221_15_fu_79398_p2 = or_ln208_3_fu_79380_p2 << 32'd2; + +assign shl_ln221_16_fu_78217_p2 = fw_0_0_1_0_1_0_reg_72840 << 32'd2; + +assign shl_ln221_17_fu_76447_p2 = fw_0_0_0_1_1_0_reg_72769 << 32'd2; + +assign shl_ln221_18_fu_79511_p2 = or_ln206_3_fu_79493_p2 << 32'd4; + +assign shl_ln221_19_fu_79908_p2 = fw_0_0_1_1_1_0_reg_72899 << 32'd2; + +assign shl_ln221_1_fu_73932_p2 = fw_0_0_0_0_0_0_reg_72698 << 32'd2; + +assign shl_ln221_20_fu_75069_p2 = or_ln208_4_fu_75051_p2 << 32'd2; + +assign shl_ln221_21_fu_78529_p2 = or_ln208_5_fu_78511_p2 << 32'd2; + +assign shl_ln221_22_fu_76749_p2 = or_ln208_6_fu_76731_p2 << 32'd2; + +assign shl_ln221_23_fu_80210_p2 = or_ln208_7_fu_80192_p2 << 32'd2; + +assign shl_ln221_2_fu_77349_p2 = fh_0_0_1_0_0_reg_72816 << 32'd4; + +assign shl_ln221_3_fu_75587_p2 = fh_0_0_0_1_0_reg_72745 << 32'd4; + +assign shl_ln221_4_fu_77394_p2 = fw_0_0_1_0_0_0_reg_72828 << 32'd2; + +assign shl_ln221_5_fu_75632_p2 = fw_0_0_0_1_0_0_reg_72757 << 32'd2; + +assign shl_ln221_6_fu_79051_p2 = fh_0_0_1_1_0_reg_72875 << 32'd4; + +assign shl_ln221_7_fu_79096_p2 = fw_0_0_1_1_0_0_reg_72887 << 32'd2; + +assign shl_ln221_8_fu_74245_p2 = or_ln208_fu_74227_p2 << 32'd2; + +assign shl_ln221_9_fu_74338_p2 = or_ln206_fu_74320_p2 << 32'd4; + +assign shl_ln221_fu_73887_p2 = fh_0_0_0_0_0_reg_72686 << 32'd4; + +assign shl_ln231_10_fu_77838_p2 = add_ln223_10_fu_77805_p2 << 32'd5; + +assign shl_ln231_11_fu_77844_p2 = add_ln223_10_fu_77805_p2 << 32'd2; + +assign shl_ln231_12_fu_76067_p2 = add_ln223_12_fu_76034_p2 << 32'd5; + +assign shl_ln231_13_fu_76073_p2 = add_ln223_12_fu_76034_p2 << 32'd2; + +assign shl_ln231_14_fu_79550_p2 = add_ln223_15_fu_79517_p2 << 32'd5; + +assign shl_ln231_15_fu_79556_p2 = add_ln223_15_fu_79517_p2 << 32'd2; + +assign shl_ln231_1_fu_73865_p2 = add_ln223_fu_73826_p2 << 32'd2; + +assign shl_ln231_2_fu_77317_p2 = add_ln223_1_fu_77284_p2 << 32'd5; + +assign shl_ln231_3_fu_77323_p2 = add_ln223_1_fu_77284_p2 << 32'd2; + +assign shl_ln231_4_fu_75559_p2 = add_ln223_2_fu_75526_p2 << 32'd5; + +assign shl_ln231_5_fu_75565_p2 = add_ln223_2_fu_75526_p2 << 32'd2; + +assign shl_ln231_6_fu_79019_p2 = add_ln223_4_fu_78986_p2 << 32'd5; + +assign shl_ln231_7_fu_79025_p2 = add_ln223_4_fu_78986_p2 << 32'd2; + +assign shl_ln231_8_fu_74377_p2 = add_ln223_8_fu_74344_p2 << 32'd5; + +assign shl_ln231_9_fu_74383_p2 = add_ln223_8_fu_74344_p2 << 32'd2; + +assign shl_ln231_fu_73859_p2 = add_ln223_fu_73826_p2 << 32'd5; + +assign shl_ln250_1_fu_80663_p3 = {{ow3_0_0_0_reg_72923}, {2'd0}}; + +assign shl_ln250_2_fu_81069_p3 = {{ow3_0_1_0_reg_72959}, {2'd0}}; + +assign shl_ln250_8_fu_80635_p3 = {{oh2_0_0_reg_72911}, {4'd0}}; + +assign shl_ln250_9_fu_80785_p3 = {{or_ln244_fu_80779_p2}, {7'd0}}; + +assign shl_ln250_s_fu_80797_p3 = {{or_ln244_fu_80779_p2}, {4'd0}}; + +assign shl_ln276_10_fu_88332_p2 = or_ln266_3_fu_88320_p2 << 32'd2; + +assign shl_ln276_11_fu_89019_p2 = fh9_0_0_1_1_1_0_reg_73331 << 32'd2; + +assign shl_ln276_12_fu_82910_p2 = or_ln266_4_fu_82898_p2 << 32'd2; + +assign shl_ln276_13_fu_87257_p2 = or_ln266_5_fu_87245_p2 << 32'd2; + +assign shl_ln276_14_fu_85000_p2 = or_ln266_6_fu_84988_p2 << 32'd2; + +assign shl_ln276_15_fu_89347_p2 = or_ln266_7_fu_89335_p2 << 32'd2; + +assign shl_ln276_1_fu_85896_p2 = fh9_0_0_1_0_0_0_reg_73211 << 32'd2; + +assign shl_ln276_2_fu_83640_p2 = fh9_0_0_0_1_0_0_reg_73115 << 32'd2; + +assign shl_ln276_3_fu_87987_p2 = fh9_0_0_1_1_0_0_reg_73295 << 32'd2; + +assign shl_ln276_4_fu_82026_p2 = or_ln266_fu_82014_p2 << 32'd2; + +assign shl_ln276_5_fu_82581_p2 = fh9_0_0_0_0_1_0_reg_73067 << 32'd2; + +assign shl_ln276_6_fu_86241_p2 = or_ln266_1_fu_86229_p2 << 32'd2; + +assign shl_ln276_7_fu_83985_p2 = or_ln266_2_fu_83973_p2 << 32'd2; + +assign shl_ln276_8_fu_86928_p2 = fh9_0_0_1_0_1_0_reg_73247 << 32'd2; + +assign shl_ln276_9_fu_84672_p2 = fh9_0_0_0_1_1_0_reg_73151 << 32'd2; + +assign shl_ln276_fu_81813_p2 = fh9_0_0_0_0_0_0_reg_73031 << 32'd2; + +assign shl_ln279_1_fu_81493_p3 = {{ow6_0_0_0_reg_73007}, {2'd0}}; + +assign shl_ln279_2_fu_85614_p3 = {{ow6_0_1_0_reg_73187}, {2'd0}}; + +assign shl_ln279_3_fu_81697_p3 = {{or_ln259_fu_81687_p2}, {2'd0}}; + +assign shl_ln279_4_fu_85780_p3 = {{or_ln259_1_fu_85770_p2}, {2'd0}}; + +assign shl_ln279_8_fu_81461_p3 = {{oh5_0_0_reg_72995}, {4'd0}}; + +assign shl_ln279_9_fu_81619_p3 = {{or_ln257_fu_81609_p2}, {7'd0}}; + +assign shl_ln279_s_fu_81631_p3 = {{or_ln257_fu_81609_p2}, {4'd0}}; + +assign shl_ln5_fu_81449_p3 = {{oh5_0_0_reg_72995}, {7'd0}}; + +assign shl_ln_fu_80623_p3 = {{oh2_0_0_reg_72911}, {7'd0}}; + +assign sub_ln1116_10_fu_79253_p2 = (zext_ln1116_29_fu_79227_p1 - zext_ln1116_28_fu_79223_p1); + +assign sub_ln1116_11_fu_79283_p2 = (7'd63 - select_ln1116_9_fu_79259_p3); + +assign sub_ln1116_12_fu_74539_p2 = (zext_ln1116_32_fu_74521_p1 - zext_ln1116_33_fu_74525_p1); + +assign sub_ln1116_13_fu_74551_p2 = (zext_ln1116_33_fu_74525_p1 - zext_ln1116_32_fu_74521_p1); + +assign sub_ln1116_14_fu_74581_p2 = (7'd63 - select_ln1116_12_fu_74557_p3); + +assign sub_ln1116_15_fu_77999_p2 = (zext_ln1116_36_fu_77981_p1 - zext_ln1116_37_fu_77985_p1); + +assign sub_ln1116_16_fu_78011_p2 = (zext_ln1116_37_fu_77985_p1 - zext_ln1116_36_fu_77981_p1); + +assign sub_ln1116_17_fu_78041_p2 = (7'd63 - select_ln1116_15_fu_78017_p3); + +assign sub_ln1116_18_fu_76229_p2 = (zext_ln1116_40_fu_76211_p1 - zext_ln1116_41_fu_76215_p1); + +assign sub_ln1116_19_fu_76241_p2 = (zext_ln1116_41_fu_76215_p1 - zext_ln1116_40_fu_76211_p1); + +assign sub_ln1116_1_fu_74100_p2 = (zext_ln1116_17_fu_74074_p1 - zext_ln1116_16_fu_74070_p1); + +assign sub_ln1116_20_fu_76271_p2 = (7'd63 - select_ln1116_18_fu_76247_p3); + +assign sub_ln1116_21_fu_74912_p2 = (zext_ln1116_44_fu_74894_p1 - zext_ln1116_45_fu_74898_p1); + +assign sub_ln1116_22_fu_74924_p2 = (zext_ln1116_45_fu_74898_p1 - zext_ln1116_44_fu_74894_p1); + +assign sub_ln1116_23_fu_74954_p2 = (7'd63 - select_ln1116_21_fu_74930_p3); + +assign sub_ln1116_24_fu_79690_p2 = (zext_ln1116_48_fu_79672_p1 - zext_ln1116_49_fu_79676_p1); + +assign sub_ln1116_25_fu_79702_p2 = (zext_ln1116_49_fu_79676_p1 - zext_ln1116_48_fu_79672_p1); + +assign sub_ln1116_26_fu_79732_p2 = (7'd63 - select_ln1116_24_fu_79708_p3); + +assign sub_ln1116_27_fu_78372_p2 = (zext_ln1116_52_fu_78354_p1 - zext_ln1116_53_fu_78358_p1); + +assign sub_ln1116_28_fu_78384_p2 = (zext_ln1116_53_fu_78358_p1 - zext_ln1116_52_fu_78354_p1); + +assign sub_ln1116_29_fu_78414_p2 = (7'd63 - select_ln1116_27_fu_78390_p3); + +assign sub_ln1116_2_fu_74130_p2 = (7'd63 - select_ln1116_fu_74106_p3); + +assign sub_ln1116_30_fu_76592_p2 = (zext_ln1116_56_fu_76574_p1 - zext_ln1116_57_fu_76578_p1); + +assign sub_ln1116_31_fu_76604_p2 = (zext_ln1116_57_fu_76578_p1 - zext_ln1116_56_fu_76574_p1); + +assign sub_ln1116_32_fu_76634_p2 = (7'd63 - select_ln1116_30_fu_76610_p3); + +assign sub_ln1116_33_fu_80053_p2 = (zext_ln1116_60_fu_80035_p1 - zext_ln1116_61_fu_80039_p1); + +assign sub_ln1116_34_fu_80065_p2 = (zext_ln1116_61_fu_80039_p1 - zext_ln1116_60_fu_80035_p1); + +assign sub_ln1116_35_fu_80095_p2 = (7'd63 - select_ln1116_33_fu_80071_p3); + +assign sub_ln1116_36_fu_75262_p2 = (zext_ln1116_64_fu_75244_p1 - zext_ln1116_65_fu_75248_p1); + +assign sub_ln1116_37_fu_75274_p2 = (zext_ln1116_65_fu_75248_p1 - zext_ln1116_64_fu_75244_p1); + +assign sub_ln1116_38_fu_75304_p2 = (7'd63 - select_ln1116_36_fu_75280_p3); + +assign sub_ln1116_39_fu_78722_p2 = (zext_ln1116_68_fu_78704_p1 - zext_ln1116_69_fu_78708_p1); + +assign sub_ln1116_3_fu_77549_p2 = (zext_ln1116_20_fu_77531_p1 - zext_ln1116_21_fu_77535_p1); + +assign sub_ln1116_40_fu_78734_p2 = (zext_ln1116_69_fu_78708_p1 - zext_ln1116_68_fu_78704_p1); + +assign sub_ln1116_41_fu_78764_p2 = (7'd63 - select_ln1116_39_fu_78740_p3); + +assign sub_ln1116_42_fu_76942_p2 = (zext_ln1116_72_fu_76924_p1 - zext_ln1116_73_fu_76928_p1); + +assign sub_ln1116_43_fu_76954_p2 = (zext_ln1116_73_fu_76928_p1 - zext_ln1116_72_fu_76924_p1); + +assign sub_ln1116_44_fu_76984_p2 = (7'd63 - select_ln1116_42_fu_76960_p3); + +assign sub_ln1116_45_fu_80403_p2 = (zext_ln1116_76_fu_80385_p1 - zext_ln1116_77_fu_80389_p1); + +assign sub_ln1116_46_fu_80415_p2 = (zext_ln1116_77_fu_80389_p1 - zext_ln1116_76_fu_80385_p1); + +assign sub_ln1116_47_fu_80445_p2 = (7'd63 - select_ln1116_45_fu_80421_p3); + +assign sub_ln1116_4_fu_77561_p2 = (zext_ln1116_21_fu_77535_p1 - zext_ln1116_20_fu_77531_p1); + +assign sub_ln1116_5_fu_77591_p2 = (7'd63 - select_ln1116_3_fu_77567_p3); + +assign sub_ln1116_6_fu_75778_p2 = (zext_ln1116_24_fu_75760_p1 - zext_ln1116_25_fu_75764_p1); + +assign sub_ln1116_7_fu_75790_p2 = (zext_ln1116_25_fu_75764_p1 - zext_ln1116_24_fu_75760_p1); + +assign sub_ln1116_8_fu_75820_p2 = (7'd63 - select_ln1116_6_fu_75796_p3); + +assign sub_ln1116_9_fu_79241_p2 = (zext_ln1116_28_fu_79223_p1 - zext_ln1116_29_fu_79227_p1); + +assign sub_ln1116_fu_74088_p2 = (zext_ln1116_16_fu_74070_p1 - zext_ln1116_17_fu_74074_p1); + +assign sub_ln231_1_fu_77329_p2 = (shl_ln231_2_fu_77317_p2 - shl_ln231_3_fu_77323_p2); + +assign sub_ln231_2_fu_75571_p2 = (shl_ln231_4_fu_75559_p2 - shl_ln231_5_fu_75565_p2); + +assign sub_ln231_3_fu_79031_p2 = (shl_ln231_6_fu_79019_p2 - shl_ln231_7_fu_79025_p2); + +assign sub_ln231_4_fu_74389_p2 = (shl_ln231_8_fu_74377_p2 - shl_ln231_9_fu_74383_p2); + +assign sub_ln231_5_fu_77850_p2 = (shl_ln231_10_fu_77838_p2 - shl_ln231_11_fu_77844_p2); + +assign sub_ln231_6_fu_76079_p2 = (shl_ln231_12_fu_76067_p2 - shl_ln231_13_fu_76073_p2); + +assign sub_ln231_7_fu_79562_p2 = (shl_ln231_14_fu_79550_p2 - shl_ln231_15_fu_79556_p2); + +assign sub_ln231_fu_73871_p2 = (shl_ln231_fu_73859_p2 - shl_ln231_1_fu_73865_p2); + +assign sub_ln250_1_fu_80809_p2 = (zext_ln250_2_fu_80793_p1 - zext_ln250_3_fu_80805_p1); + +assign sub_ln250_fu_80647_p2 = (zext_ln250_fu_80631_p1 - zext_ln250_1_fu_80643_p1); + +assign sub_ln279_1_fu_81643_p2 = (zext_ln279_4_fu_81627_p1 - zext_ln279_5_fu_81639_p1); + +assign sub_ln279_fu_81473_p2 = (zext_ln279_1_fu_81457_p1 - zext_ln279_2_fu_81469_p1); + +assign tmp34_fu_74029_p2 = ((3'd6) + (empty_83_fu_74025_p1)); + +assign tmp35_fu_74490_p2 = ((3'd6) + (empty_85_fu_74484_p2)); + +assign tmp36_fu_74854_p2 = (empty_89_fu_74850_p1 + trunc_ln1116_6_reg_90333); + +assign tmp37_fu_75154_p2 = (empty_91_fu_75148_p2 + add_ln1116_1_reg_90120); + +assign tmp42_fu_75729_p2 = ((3'd7) + (empty_99_fu_75725_p1)); + +assign tmp43_fu_76180_p2 = ((3'd7) + (empty_101_fu_76174_p2)); + +assign tmp44_fu_76544_p2 = (empty_105_fu_76540_p1 + trunc_ln1116_10_reg_90793); + +assign tmp45_fu_76834_p2 = (empty_107_fu_76828_p2 + add_ln1116_2_reg_90183); + +assign tmp50_fu_77491_p2 = (empty_117_fu_77487_p1 + trunc_ln1116_reg_91185); + +assign tmp51_fu_77951_p2 = (empty_119_fu_77945_p2 + add_ln1116_reg_91112); + +assign tmp52_fu_78314_p2 = (empty_123_fu_78310_p1 + trunc_ln1116_9_reg_91326); + +assign tmp53_fu_78614_p2 = (empty_125_fu_78608_p2 + add_ln1116_reg_91112); + +assign tmp58_fu_79193_p2 = (empty_133_fu_79189_p1 + trunc_ln1116_2_reg_91651); + +assign tmp59_fu_79483_p2 = (empty_135_fu_79477_p2 + add_ln1116_3_reg_91168); + +assign tmp60_fu_80005_p2 = (empty_139_fu_80001_p1 + trunc_ln1116_16_reg_91797); + +assign tmp61_fu_80295_p2 = (empty_141_fu_80289_p2 + add_ln1116_3_reg_91168); + +assign tmp_104_fu_77810_p4 = {{add_ln223_10_fu_77805_p2[31:1]}}; + +assign tmp_105_fu_77722_p4 = {{add_ln223_11_fu_77717_p2[31:1]}}; + +assign tmp_107_fu_76039_p4 = {{add_ln223_12_fu_76034_p2[31:1]}}; + +assign tmp_108_fu_75951_p4 = {{add_ln223_13_fu_75946_p2[31:1]}}; + +assign tmp_109_fu_74773_p4 = {{add_ln223_14_fu_74768_p2[31:1]}}; + +assign tmp_10_fu_75648_p4 = {{add_ln223_6_fu_75643_p2[31:1]}}; + +assign tmp_111_fu_86272_p4 = {{add_ln279_3_reg_97927[5:2]}}; + +assign tmp_114_fu_84016_p4 = {{add_ln279_5_reg_94288[5:2]}}; + +assign tmp_120_fu_77961_p3 = {{trunc_ln1116_4261134719_fu_77956_p2}, {3'd0}}; + +integer ap_tvar_int_0; + +always @ (data_V_q0) begin + for (ap_tvar_int_0 = 0; ap_tvar_int_0 < 64; ap_tvar_int_0 = ap_tvar_int_0 + 1) begin + if (ap_tvar_int_0 > 63 - 0) begin + tmp_121_fu_77989_p4[ap_tvar_int_0] = 1'b0; + end else begin + tmp_121_fu_77989_p4[ap_tvar_int_0] = data_V_q0[63 - ap_tvar_int_0]; + end + end +end + +assign tmp_124_fu_76191_p3 = {{trunc_ln1116_4461133911_fu_76186_p2}, {3'd0}}; + +integer ap_tvar_int_1; + +always @ (data_V_q0) begin + for (ap_tvar_int_1 = 0; ap_tvar_int_1 < 64; ap_tvar_int_1 = ap_tvar_int_1 + 1) begin + if (ap_tvar_int_1 > 63 - 0) begin + tmp_125_fu_76219_p4[ap_tvar_int_1] = 1'b0; + end else begin + tmp_125_fu_76219_p4[ap_tvar_int_1] = data_V_q0[63 - ap_tvar_int_1]; + end + end +end + +assign tmp_128_fu_74864_p4 = {{trunc_ln1116_466113335_fu_74859_p2[2:1]}}; + +assign tmp_129_fu_74874_p3 = {{tmp_128_fu_74864_p4}, {4'd0}}; + +integer ap_tvar_int_2; + +always @ (data_V_q0) begin + for (ap_tvar_int_2 = 0; ap_tvar_int_2 < 64; ap_tvar_int_2 = ap_tvar_int_2 + 1) begin + if (ap_tvar_int_2 > 63 - 0) begin + tmp_130_fu_74902_p4[ap_tvar_int_2] = 1'b0; + end else begin + tmp_130_fu_74902_p4[ap_tvar_int_2] = data_V_q0[63 - ap_tvar_int_2]; + end + end +end + +assign tmp_143_fu_79522_p4 = {{add_ln223_15_fu_79517_p2[31:1]}}; + +assign tmp_144_fu_79414_p4 = {{add_ln223_16_fu_79409_p2[31:1]}}; + +assign tmp_145_fu_78233_p4 = {{add_ln223_17_fu_78228_p2[31:1]}}; + +assign tmp_146_fu_76463_p4 = {{add_ln223_18_fu_76458_p2[31:1]}}; + +assign tmp_148_fu_88363_p4 = {{add_ln279_7_reg_98352[5:2]}}; + +assign tmp_159_fu_79653_p3 = {{trunc_ln1116_4861135527_reg_91763}, {3'd0}}; + +integer ap_tvar_int_3; + +always @ (data_V_q0) begin + for (ap_tvar_int_3 = 0; ap_tvar_int_3 < 64; ap_tvar_int_3 = ap_tvar_int_3 + 1) begin + if (ap_tvar_int_3 > 63 - 0) begin + tmp_160_fu_79680_p4[ap_tvar_int_3] = 1'b0; + end else begin + tmp_160_fu_79680_p4[ap_tvar_int_3] = data_V_q0[63 - ap_tvar_int_3]; + end + end +end + +assign tmp_163_fu_78324_p4 = {{trunc_ln1116_5061134921_fu_78319_p2[2:1]}}; + +assign tmp_164_fu_78334_p3 = {{tmp_163_fu_78324_p4}, {4'd0}}; + +integer ap_tvar_int_4; + +always @ (data_V_q0) begin + for (ap_tvar_int_4 = 0; ap_tvar_int_4 < 64; ap_tvar_int_4 = ap_tvar_int_4 + 1) begin + if (ap_tvar_int_4 > 63 - 0) begin + tmp_165_fu_78362_p4[ap_tvar_int_4] = 1'b0; + end else begin + tmp_165_fu_78362_p4[ap_tvar_int_4] = data_V_q0[63 - ap_tvar_int_4]; + end + end +end + +assign tmp_168_fu_76554_p3 = {{trunc_ln1116_5261134113_fu_76549_p2}, {3'd0}}; + +integer ap_tvar_int_5; + +always @ (data_V_q0) begin + for (ap_tvar_int_5 = 0; ap_tvar_int_5 < 64; ap_tvar_int_5 = ap_tvar_int_5 + 1) begin + if (ap_tvar_int_5 > 63 - 0) begin + tmp_169_fu_76582_p4[ap_tvar_int_5] = 1'b0; + end else begin + tmp_169_fu_76582_p4[ap_tvar_int_5] = data_V_q0[63 - ap_tvar_int_5]; + end + end +end + +assign tmp_177_fu_79924_p4 = {{add_ln223_19_fu_79919_p2[31:1]}}; + +assign tmp_187_fu_80015_p3 = {{trunc_ln1116_5461135729_fu_80010_p2}, {3'd0}}; + +integer ap_tvar_int_6; + +always @ (data_V_q0) begin + for (ap_tvar_int_6 = 0; ap_tvar_int_6 < 64; ap_tvar_int_6 = ap_tvar_int_6 + 1) begin + if (ap_tvar_int_6 > 63 - 0) begin + tmp_188_fu_80043_p4[ap_tvar_int_6] = 1'b0; + end else begin + tmp_188_fu_80043_p4[ap_tvar_int_6] = data_V_q0[63 - ap_tvar_int_6]; + end + end +end + +assign tmp_197_fu_75085_p4 = {{add_ln223_20_fu_75080_p2[31:1]}}; + +assign tmp_1_fu_73831_p4 = {{add_ln223_fu_73826_p2[31:1]}}; + +assign tmp_203_fu_75225_p3 = {{trunc_ln1116_566113357_reg_90519}, {3'd0}}; + +integer ap_tvar_int_7; + +always @ (data_V_q0) begin + for (ap_tvar_int_7 = 0; ap_tvar_int_7 < 64; ap_tvar_int_7 = ap_tvar_int_7 + 1) begin + if (ap_tvar_int_7 > 63 - 0) begin + tmp_204_fu_75252_p4[ap_tvar_int_7] = 1'b0; + end else begin + tmp_204_fu_75252_p4[ap_tvar_int_7] = data_V_q0[63 - ap_tvar_int_7]; + end + end +end + +assign tmp_20_fu_73910_p4 = {{add_ln221_fu_73893_p2[31:3]}}; + +assign tmp_214_fu_78545_p4 = {{add_ln223_21_fu_78540_p2[31:1]}}; + +assign tmp_215_fu_76765_p4 = {{add_ln223_22_fu_76760_p2[31:1]}}; + +assign tmp_220_fu_78685_p3 = {{trunc_ln1116_5861135123_reg_91512}, {3'd0}}; + +integer ap_tvar_int_8; + +always @ (data_V_q0) begin + for (ap_tvar_int_8 = 0; ap_tvar_int_8 < 64; ap_tvar_int_8 = ap_tvar_int_8 + 1) begin + if (ap_tvar_int_8 > 63 - 0) begin + tmp_221_fu_78712_p4[ap_tvar_int_8] = 1'b0; + end else begin + tmp_221_fu_78712_p4[ap_tvar_int_8] = data_V_q0[63 - ap_tvar_int_8]; + end + end +end + +assign tmp_224_fu_76905_p3 = {{trunc_ln1116_6061134315_reg_90979}, {3'd0}}; + +integer ap_tvar_int_9; + +always @ (data_V_q0) begin + for (ap_tvar_int_9 = 0; ap_tvar_int_9 < 64; ap_tvar_int_9 = ap_tvar_int_9 + 1) begin + if (ap_tvar_int_9 > 63 - 0) begin + tmp_225_fu_76932_p4[ap_tvar_int_9] = 1'b0; + end else begin + tmp_225_fu_76932_p4[ap_tvar_int_9] = data_V_q0[63 - ap_tvar_int_9]; + end + end +end + +assign tmp_232_fu_80366_p3 = {{trunc_ln1116_6261135931_reg_91983}, {3'd0}}; + +assign tmp_233_fu_80226_p4 = {{add_ln223_23_fu_80221_p2[31:1]}}; + +integer ap_tvar_int_10; + +always @ (data_V_q0) begin + for (ap_tvar_int_10 = 0; ap_tvar_int_10 < 64; ap_tvar_int_10 = ap_tvar_int_10 + 1) begin + if (ap_tvar_int_10 > 63 - 0) begin + tmp_238_fu_80393_p4[ap_tvar_int_10] = 1'b0; + end else begin + tmp_238_fu_80393_p4[ap_tvar_int_10] = data_V_q0[63 - ap_tvar_int_10]; + end + end +end + +assign tmp_25_fu_80825_p4 = {{add_ln250_1_reg_92112[5:3]}}; + +assign tmp_2_fu_77289_p4 = {{add_ln223_1_fu_77284_p2[31:1]}}; + +assign tmp_30_fu_77372_p4 = {{add_ln221_4_fu_77355_p2[31:3]}}; + +assign tmp_32_fu_75610_p4 = {{add_ln221_5_fu_75593_p2[31:3]}}; + +assign tmp_36_fu_81663_p4 = {{add_ln279_1_reg_93866[5:3]}}; + +assign tmp_38_fu_81197_p4 = {{add_ln250_3_reg_92667[5:3]}}; + +assign tmp_39_fu_80926_p4 = {{add_ln250_1_reg_92112[5:2]}}; + +assign tmp_3_fu_75531_p4 = {{add_ln223_2_fu_75526_p2[31:1]}}; + +assign tmp_41_fu_74040_p4 = {{trunc_ln1116_326113291_fu_74035_p2[2:1]}}; + +assign tmp_42_fu_74050_p3 = {{tmp_41_fu_74040_p4}, {4'd0}}; + +assign tmp_45_fu_79074_p4 = {{add_ln221_8_fu_79057_p2[31:3]}}; + +assign tmp_48_fu_85746_p4 = {{add_ln279_3_reg_97927[5:3]}}; + +assign tmp_4_fu_73948_p4 = {{add_ln223_3_fu_73943_p2[31:1]}}; + +assign tmp_53_fu_81302_p4 = {{add_ln250_3_reg_92667[5:2]}}; + +assign tmp_54_fu_81040_p4 = {{add_ln250_5_reg_92461[5:2]}}; + +assign tmp_56_fu_77501_p4 = {{trunc_ln1116_3461134517_fu_77496_p2[2:1]}}; + +assign tmp_57_fu_77511_p3 = {{tmp_56_fu_77501_p4}, {4'd0}}; + +integer ap_tvar_int_11; + +always @ (data_V_q0) begin + for (ap_tvar_int_11 = 0; ap_tvar_int_11 < 64; ap_tvar_int_11 = ap_tvar_int_11 + 1) begin + if (ap_tvar_int_11 > 63 - 0) begin + tmp_58_fu_77539_p4[ap_tvar_int_11] = 1'b0; + end else begin + tmp_58_fu_77539_p4[ap_tvar_int_11] = data_V_q0[63 - ap_tvar_int_11]; + end + end +end + +assign tmp_61_fu_75740_p3 = {{trunc_ln1116_366113379_fu_75735_p2}, {3'd0}}; + +integer ap_tvar_int_12; + +always @ (data_V_q0) begin + for (ap_tvar_int_12 = 0; ap_tvar_int_12 < 64; ap_tvar_int_12 = ap_tvar_int_12 + 1) begin + if (ap_tvar_int_12 > 63 - 0) begin + tmp_62_fu_75768_p4[ap_tvar_int_12] = 1'b0; + end else begin + tmp_62_fu_75768_p4[ap_tvar_int_12] = data_V_q0[63 - ap_tvar_int_12]; + end + end +end + +assign tmp_66_fu_79112_p4 = {{add_ln223_7_fu_79107_p2[31:1]}}; + +integer ap_tvar_int_13; + +always @ (data_V_q0) begin + for (ap_tvar_int_13 = 0; ap_tvar_int_13 < 64; ap_tvar_int_13 = ap_tvar_int_13 + 1) begin + if (ap_tvar_int_13 > 63 - 0) begin + tmp_6_fu_74078_p4[ap_tvar_int_13] = 1'b0; + end else begin + tmp_6_fu_74078_p4[ap_tvar_int_13] = data_V_q0[63 - ap_tvar_int_13]; + end + end +end + +assign tmp_74_fu_81416_p4 = {{add_ln250_7_reg_93009[5:2]}}; + +assign tmp_76_fu_79203_p3 = {{trunc_ln1116_3861135325_fu_79198_p2}, {3'd0}}; + +integer ap_tvar_int_14; + +always @ (data_V_q0) begin + for (ap_tvar_int_14 = 0; ap_tvar_int_14 < 64; ap_tvar_int_14 = ap_tvar_int_14 + 1) begin + if (ap_tvar_int_14 > 63 - 0) begin + tmp_77_fu_79231_p4[ap_tvar_int_14] = 1'b0; + end else begin + tmp_77_fu_79231_p4[ap_tvar_int_14] = data_V_q0[63 - ap_tvar_int_14]; + end + end +end + +assign tmp_83_fu_74349_p4 = {{add_ln223_8_fu_74344_p2[31:1]}}; + +assign tmp_84_fu_74261_p4 = {{add_ln223_9_fu_74256_p2[31:1]}}; + +assign tmp_89_fu_82057_p4 = {{add_ln279_1_reg_93866[5:2]}}; + +assign tmp_8_fu_78991_p4 = {{add_ln223_4_fu_78986_p2[31:1]}}; + +assign tmp_92_fu_74501_p3 = {{trunc_ln1116_406113313_fu_74496_p2}, {3'd0}}; + +integer ap_tvar_int_15; + +always @ (data_V_q0) begin + for (ap_tvar_int_15 = 0; ap_tvar_int_15 < 64; ap_tvar_int_15 = ap_tvar_int_15 + 1) begin + if (ap_tvar_int_15 > 63 - 0) begin + tmp_93_fu_74529_p4[ap_tvar_int_15] = 1'b0; + end else begin + tmp_93_fu_74529_p4[ap_tvar_int_15] = data_V_q0[63 - ap_tvar_int_15]; + end + end +end + +assign tmp_9_fu_77410_p4 = {{add_ln223_5_fu_77405_p2[31:1]}}; + +assign trunc_ln1116_10_fu_76111_p1 = sub_ln231_6_fu_76079_p2[2:0]; + +assign trunc_ln1116_11_fu_77941_p1 = fw_0_0_1_0_0_0_reg_72828[2:0]; + +assign trunc_ln1116_12_fu_78071_p1 = and_ln1116_5_fu_78066_p2[7:0]; + +assign trunc_ln1116_13_fu_76170_p1 = fw_0_0_0_1_0_0_reg_72757[2:0]; + +assign trunc_ln1116_14_fu_76301_p1 = and_ln1116_6_fu_76296_p2[7:0]; + +assign trunc_ln1116_15_fu_74984_p1 = and_ln1116_7_fu_74979_p2[7:0]; + +assign trunc_ln1116_16_fu_79594_p1 = sub_ln231_7_fu_79562_p2[2:0]; + +assign trunc_ln1116_17_fu_79468_p1 = fw_0_0_1_1_0_0_reg_72887[2:0]; + +assign trunc_ln1116_18_fu_79762_p1 = and_ln1116_8_fu_79757_p2[7:0]; + +assign trunc_ln1116_19_fu_78444_p1 = and_ln1116_9_fu_78439_p2[7:0]; + +assign trunc_ln1116_1_fu_74160_p1 = and_ln1116_fu_74155_p2[7:0]; + +assign trunc_ln1116_20_fu_76664_p1 = and_ln1116_10_fu_76659_p2[7:0]; + +assign trunc_ln1116_21_fu_80125_p1 = and_ln1116_11_fu_80120_p2[7:0]; + +assign trunc_ln1116_22_fu_75139_p1 = fw_0_0_0_0_1_0_reg_72710[2:0]; + +assign trunc_ln1116_23_fu_75334_p1 = and_ln1116_12_fu_75329_p2[7:0]; + +assign trunc_ln1116_24_fu_78599_p1 = fw_0_0_1_0_1_0_reg_72840[2:0]; + +assign trunc_ln1116_25_fu_78794_p1 = and_ln1116_13_fu_78789_p2[7:0]; + +assign trunc_ln1116_26_fu_76819_p1 = fw_0_0_0_1_1_0_reg_72769[2:0]; + +assign trunc_ln1116_27_fu_77014_p1 = and_ln1116_14_fu_77009_p2[7:0]; + +assign trunc_ln1116_28_fu_80280_p1 = fw_0_0_1_1_1_0_reg_72899[2:0]; + +assign trunc_ln1116_29_fu_80475_p1 = and_ln1116_15_fu_80470_p2[7:0]; + +assign trunc_ln1116_2_fu_79041_p1 = sub_ln231_3_fu_79031_p2[2:0]; + +assign trunc_ln1116_326113291_fu_74035_p2 = (trunc_ln231_reg_90111 + tmp34_fu_74029_p2); + +assign trunc_ln1116_3461134517_fu_77496_p2 = (add_ln1116_reg_91112 + tmp50_fu_77491_p2); + +assign trunc_ln1116_366113379_fu_75735_p2 = (trunc_ln231_reg_90111 + tmp42_fu_75729_p2); + +assign trunc_ln1116_3861135325_fu_79198_p2 = (add_ln1116_3_reg_91168 + tmp58_fu_79193_p2); + +assign trunc_ln1116_3_fu_77621_p1 = and_ln1116_1_fu_77616_p2[7:0]; + +assign trunc_ln1116_406113313_fu_74496_p2 = (trunc_ln231_reg_90111 + tmp35_fu_74490_p2); + +assign trunc_ln1116_4261134719_fu_77956_p2 = (trunc_ln1116_reg_91185 + tmp51_fu_77951_p2); + +assign trunc_ln1116_4461133911_fu_76186_p2 = (trunc_ln231_reg_90111 + tmp43_fu_76180_p2); + +assign trunc_ln1116_466113335_fu_74859_p2 = (add_ln1116_1_reg_90120 + tmp36_fu_74854_p2); + +assign trunc_ln1116_4861135527_fu_79488_p2 = (trunc_ln1116_2_reg_91651 + tmp59_fu_79483_p2); + +assign trunc_ln1116_4_fu_75850_p1 = and_ln1116_2_fu_75845_p2[7:0]; + +assign trunc_ln1116_5061134921_fu_78319_p2 = (add_ln1116_reg_91112 + tmp52_fu_78314_p2); + +assign trunc_ln1116_5261134113_fu_76549_p2 = (add_ln1116_2_reg_90183 + tmp44_fu_76544_p2); + +assign trunc_ln1116_5461135729_fu_80010_p2 = (add_ln1116_3_reg_91168 + tmp60_fu_80005_p2); + +assign trunc_ln1116_566113357_fu_75159_p2 = (trunc_ln1116_6_reg_90333 + tmp37_fu_75154_p2); + +assign trunc_ln1116_5861135123_fu_78619_p2 = (trunc_ln1116_9_reg_91326 + tmp53_fu_78614_p2); + +assign trunc_ln1116_5_fu_79313_p1 = and_ln1116_3_fu_79308_p2[7:0]; + +assign trunc_ln1116_6061134315_fu_76839_p2 = (trunc_ln1116_10_reg_90793 + tmp45_fu_76834_p2); + +assign trunc_ln1116_6261135931_fu_80300_p2 = (trunc_ln1116_16_reg_91797 + tmp61_fu_80295_p2); + +assign trunc_ln1116_6_fu_74421_p1 = sub_ln231_4_fu_74389_p2[2:0]; + +assign trunc_ln1116_7_fu_74480_p1 = fw_0_0_0_0_0_0_reg_72698[2:0]; + +assign trunc_ln1116_8_fu_74611_p1 = and_ln1116_4_fu_74606_p2[7:0]; + +assign trunc_ln1116_9_fu_77882_p1 = sub_ln231_5_fu_77850_p2[2:0]; + +assign trunc_ln1116_fu_77339_p1 = sub_ln231_1_fu_77329_p2[2:0]; + +assign trunc_ln1265_1_fu_83549_p4 = {{add_ln279_8_fu_83535_p2[12:6]}}; + +assign trunc_ln1265_2_fu_87896_p4 = {{add_ln279_9_fu_87882_p2[12:6]}}; + +assign trunc_ln1265_8_fu_85648_p4 = {{add_ln279_2_fu_85638_p2[12:6]}}; + +assign trunc_ln1265_9_fu_81731_p4 = {{add_ln279_4_fu_81721_p2[12:6]}}; + +assign trunc_ln1265_s_fu_85814_p4 = {{add_ln279_6_fu_85804_p2[12:6]}}; + +assign trunc_ln203_10_fu_75878_p1 = grp_fu_73404_p2[5:0]; + +assign trunc_ln203_11_fu_79618_p1 = grp_fu_73468_p2[5:0]; + +assign trunc_ln203_12_fu_79341_p1 = grp_fu_73468_p2[5:0]; + +assign trunc_ln203_13_fu_74718_p1 = grp_fu_73378_p2[5:0]; + +assign trunc_ln203_14_fu_74658_p1 = grp_fu_73378_p2[5:0]; + +assign trunc_ln203_15_fu_78178_p1 = grp_fu_73442_p2[5:0]; + +assign trunc_ln203_16_fu_78118_p1 = grp_fu_73442_p2[5:0]; + +assign trunc_ln203_17_fu_76408_p1 = grp_fu_73410_p2[5:0]; + +assign trunc_ln203_18_fu_76348_p1 = grp_fu_73410_p2[5:0]; + +assign trunc_ln203_19_fu_75190_p1 = grp_fu_73388_p2[5:0]; + +assign trunc_ln203_1_fu_81103_p4 = {{add_ln250_2_fu_81093_p2[12:6]}}; + +assign trunc_ln203_20_fu_75012_p1 = grp_fu_73388_p2[5:0]; + +assign trunc_ln203_21_fu_79869_p1 = grp_fu_73474_p2[5:0]; + +assign trunc_ln203_22_fu_79809_p1 = grp_fu_73474_p2[5:0]; + +assign trunc_ln203_23_fu_78650_p1 = grp_fu_73452_p2[5:0]; + +assign trunc_ln203_24_fu_78472_p1 = grp_fu_73452_p2[5:0]; + +assign trunc_ln203_25_fu_76870_p1 = grp_fu_73420_p2[5:0]; + +assign trunc_ln203_26_fu_76692_p1 = grp_fu_73420_p2[5:0]; + +assign trunc_ln203_27_fu_80331_p1 = grp_fu_73484_p2[5:0]; + +assign trunc_ln203_28_fu_80153_p1 = grp_fu_73484_p2[5:0]; + +assign trunc_ln203_29_fu_75441_p1 = grp_fu_73394_p2[5:0]; + +assign trunc_ln203_2_fu_80866_p4 = {{add_ln250_4_fu_80856_p2[12:6]}}; + +assign trunc_ln203_30_fu_75381_p1 = grp_fu_73394_p2[5:0]; + +assign trunc_ln203_31_fu_78901_p1 = grp_fu_73458_p2[5:0]; + +assign trunc_ln203_32_fu_78841_p1 = grp_fu_73458_p2[5:0]; + +assign trunc_ln203_33_fu_77121_p1 = grp_fu_73426_p2[5:0]; + +assign trunc_ln203_34_fu_77061_p1 = grp_fu_73426_p2[5:0]; + +assign trunc_ln203_35_fu_80582_p1 = grp_fu_73490_p2[5:0]; + +assign trunc_ln203_36_fu_80522_p1 = grp_fu_73490_p2[5:0]; + +assign trunc_ln203_3_fu_81242_p4 = {{add_ln250_6_fu_81228_p2[12:6]}}; + +assign trunc_ln203_4_fu_80973_p4 = {{add_ln250_8_fu_80963_p2[12:6]}}; + +assign trunc_ln203_5_fu_74188_p1 = grp_fu_73372_p2[5:0]; + +assign trunc_ln203_6_fu_81349_p4 = {{add_ln250_9_fu_81339_p2[13:6]}}; + +assign trunc_ln203_7_fu_77906_p1 = grp_fu_73436_p2[5:0]; + +assign trunc_ln203_8_fu_77649_p1 = grp_fu_73436_p2[5:0]; + +assign trunc_ln203_9_fu_76135_p1 = grp_fu_73404_p2[5:0]; + +assign trunc_ln203_fu_74445_p1 = grp_fu_73372_p2[5:0]; + +assign trunc_ln203_s_fu_80697_p4 = {{add_ln250_fu_80687_p2[12:6]}}; + +assign trunc_ln208_1_fu_77684_p1 = fw_0_0_1_0_0_0_reg_72828[10:0]; + +assign trunc_ln208_2_fu_75913_p1 = fw_0_0_0_1_0_0_reg_72757[10:0]; + +assign trunc_ln208_3_fu_79376_p1 = fw_0_0_1_1_0_0_reg_72887[10:0]; + +assign trunc_ln208_4_fu_75047_p1 = fw_0_0_0_0_1_0_reg_72710[10:0]; + +assign trunc_ln208_5_fu_78507_p1 = fw_0_0_1_0_1_0_reg_72840[10:0]; + +assign trunc_ln208_6_fu_76727_p1 = fw_0_0_0_1_1_0_reg_72769[10:0]; + +assign trunc_ln208_7_fu_80188_p1 = fw_0_0_1_1_1_0_reg_72899[10:0]; + +assign trunc_ln208_fu_74223_p1 = fw_0_0_0_0_0_0_reg_72698[10:0]; + +assign trunc_ln231_10_fu_74417_p1 = sub_ln231_4_fu_74389_p2[10:0]; + +assign trunc_ln231_11_fu_77878_p1 = sub_ln231_5_fu_77850_p2[10:0]; + +assign trunc_ln231_12_fu_76107_p1 = sub_ln231_6_fu_76079_p2[10:0]; + +assign trunc_ln231_13_fu_74826_p1 = fw_0_0_0_0_1_0_reg_72710[10:0]; + +assign trunc_ln231_14_fu_79590_p1 = sub_ln231_7_fu_79562_p2[10:0]; + +assign trunc_ln231_15_fu_78286_p1 = fw_0_0_1_0_1_0_reg_72840[10:0]; + +assign trunc_ln231_16_fu_76516_p1 = fw_0_0_0_1_1_0_reg_72769[10:0]; + +assign trunc_ln231_17_fu_79977_p1 = fw_0_0_1_1_1_0_reg_72899[10:0]; + +assign trunc_ln231_1_fu_77190_p1 = ow_0_1_0_reg_72781[2:0]; + +assign trunc_ln231_2_fu_73877_p1 = sub_ln231_fu_73871_p2[10:0]; + +assign trunc_ln231_3_fu_77335_p1 = sub_ln231_1_fu_77329_p2[10:0]; + +assign trunc_ln231_4_fu_75577_p1 = sub_ln231_2_fu_75571_p2[10:0]; + +assign trunc_ln231_5_fu_74001_p1 = fw_0_0_0_0_0_0_reg_72698[10:0]; + +assign trunc_ln231_6_fu_79037_p1 = sub_ln231_3_fu_79031_p2[10:0]; + +assign trunc_ln231_7_fu_77463_p1 = fw_0_0_1_0_0_0_reg_72828[10:0]; + +assign trunc_ln231_8_fu_75701_p1 = fw_0_0_0_1_0_0_reg_72757[10:0]; + +assign trunc_ln231_9_fu_79165_p1 = fw_0_0_1_1_0_0_reg_72887[10:0]; + +assign trunc_ln231_fu_73724_p1 = ow_0_0_0_reg_72651[2:0]; + +assign trunc_ln250_1_fu_80815_p1 = sub_ln250_1_fu_80809_p2[5:0]; + +assign trunc_ln250_2_fu_80675_p1 = ow3_0_0_0_reg_72923[3:0]; + +assign trunc_ln250_3_fu_81081_p1 = ow3_0_1_0_reg_72959[3:0]; + +assign trunc_ln250_8_fu_80679_p3 = {{trunc_ln250_2_fu_80675_p1}, {2'd0}}; + +assign trunc_ln250_9_fu_81085_p3 = {{trunc_ln250_3_fu_81081_p1}, {2'd0}}; + +assign trunc_ln250_fu_80653_p1 = sub_ln250_fu_80647_p2[5:0]; + +assign trunc_ln279_1_fu_81649_p1 = sub_ln279_1_fu_81643_p2[5:0]; + +assign trunc_ln279_2_fu_81505_p1 = ow6_0_0_0_reg_73007[3:0]; + +assign trunc_ln279_3_fu_85626_p1 = ow6_0_1_0_reg_73187[3:0]; + +assign trunc_ln279_4_fu_81709_p1 = or_ln259_fu_81687_p2[3:0]; + +assign trunc_ln279_5_fu_81509_p3 = {{trunc_ln279_2_fu_81505_p1}, {2'd0}}; + +assign trunc_ln279_6_fu_85630_p3 = {{trunc_ln279_3_fu_85626_p1}, {2'd0}}; + +assign trunc_ln279_7_fu_81713_p3 = {{trunc_ln279_4_fu_81709_p1}, {2'd0}}; + +assign trunc_ln279_8_fu_85796_p3 = {{trunc_ln279_9_fu_85792_p1}, {2'd0}}; + +assign trunc_ln279_9_fu_85792_p1 = or_ln259_1_fu_85770_p2[3:0]; + +assign trunc_ln279_fu_81479_p1 = sub_ln279_fu_81473_p2[5:0]; + +assign trunc_ln7_fu_81527_p4 = {{add_ln279_fu_81517_p2[12:6]}}; + +assign xor_ln1116_10_fu_76598_p2 = (zext_ln1116_56_fu_76574_p1 ^ 7'd63); + +assign xor_ln1116_11_fu_80059_p2 = (zext_ln1116_60_fu_80035_p1 ^ 7'd63); + +assign xor_ln1116_12_fu_75268_p2 = (zext_ln1116_64_fu_75244_p1 ^ 7'd63); + +assign xor_ln1116_13_fu_78728_p2 = (zext_ln1116_68_fu_78704_p1 ^ 7'd63); + +assign xor_ln1116_14_fu_76948_p2 = (zext_ln1116_72_fu_76924_p1 ^ 7'd63); + +assign xor_ln1116_15_fu_80409_p2 = (zext_ln1116_76_fu_80385_p1 ^ 7'd63); + +assign xor_ln1116_1_fu_77555_p2 = (zext_ln1116_20_fu_77531_p1 ^ 7'd63); + +assign xor_ln1116_2_fu_75784_p2 = (zext_ln1116_24_fu_75760_p1 ^ 7'd63); + +assign xor_ln1116_3_fu_79247_p2 = (zext_ln1116_28_fu_79223_p1 ^ 7'd63); + +assign xor_ln1116_4_fu_74545_p2 = (zext_ln1116_32_fu_74521_p1 ^ 7'd63); + +assign xor_ln1116_5_fu_78005_p2 = (zext_ln1116_36_fu_77981_p1 ^ 7'd63); + +assign xor_ln1116_6_fu_76235_p2 = (zext_ln1116_40_fu_76211_p1 ^ 7'd63); + +assign xor_ln1116_7_fu_74918_p2 = (zext_ln1116_44_fu_74894_p1 ^ 7'd63); + +assign xor_ln1116_8_fu_79696_p2 = (zext_ln1116_48_fu_79672_p1 ^ 7'd63); + +assign xor_ln1116_9_fu_78378_p2 = (zext_ln1116_52_fu_78354_p1 ^ 7'd63); + +assign xor_ln1116_fu_74094_p2 = (zext_ln1116_16_fu_74070_p1 ^ 7'd63); + +assign zext_ln1116_10_fu_76535_p1 = lshr_ln1116_9_fu_76525_p4; + +assign zext_ln1116_11_fu_79996_p1 = lshr_ln1116_10_fu_79986_p4; + +assign zext_ln1116_12_fu_75143_p1 = lshr_ln1116_11_fu_75129_p4; + +assign zext_ln1116_13_fu_78603_p1 = lshr_ln1116_12_fu_78589_p4; + +assign zext_ln1116_14_fu_76823_p1 = lshr_ln1116_13_fu_76809_p4; + +assign zext_ln1116_15_fu_80284_p1 = lshr_ln1116_14_fu_80270_p4; + +assign zext_ln1116_16_fu_74070_p1 = tmp_42_fu_74050_p3; + +assign zext_ln1116_17_fu_74074_p1 = empty_84_fu_74058_p2; + +assign zext_ln1116_18_fu_74136_p1 = select_ln1116_2_fu_74122_p3; + +assign zext_ln1116_19_fu_74146_p1 = sub_ln1116_2_reg_90240; + +assign zext_ln1116_1_fu_77482_p1 = lshr_ln1116_s_fu_77472_p4; + +assign zext_ln1116_20_fu_77531_p1 = tmp_57_fu_77511_p3; + +assign zext_ln1116_21_fu_77535_p1 = empty_118_fu_77519_p2; + +assign zext_ln1116_22_fu_77597_p1 = select_ln1116_5_fu_77583_p3; + +assign zext_ln1116_23_fu_77607_p1 = sub_ln1116_5_reg_91233; + +assign zext_ln1116_24_fu_75760_p1 = tmp_61_fu_75740_p3; + +assign zext_ln1116_25_fu_75764_p1 = empty_100_fu_75748_p2; + +assign zext_ln1116_26_fu_75826_p1 = select_ln1116_8_fu_75812_p3; + +assign zext_ln1116_27_fu_75836_p1 = sub_ln1116_8_reg_90700; + +assign zext_ln1116_28_fu_79223_p1 = tmp_76_fu_79203_p3; + +assign zext_ln1116_29_fu_79227_p1 = empty_134_fu_79211_p2; + +assign zext_ln1116_2_fu_75720_p1 = lshr_ln1116_1_fu_75710_p4; + +assign zext_ln1116_30_fu_79289_p1 = select_ln1116_11_fu_79275_p3; + +assign zext_ln1116_31_fu_79299_p1 = sub_ln1116_11_reg_91699; + +assign zext_ln1116_32_fu_74521_p1 = tmp_92_fu_74501_p3; + +assign zext_ln1116_33_fu_74525_p1 = empty_86_fu_74509_p2; + +assign zext_ln1116_34_fu_74587_p1 = select_ln1116_14_fu_74573_p3; + +assign zext_ln1116_35_fu_74597_p1 = sub_ln1116_14_reg_90352; + +assign zext_ln1116_36_fu_77981_p1 = tmp_120_fu_77961_p3; + +assign zext_ln1116_37_fu_77985_p1 = empty_120_fu_77969_p2; + +assign zext_ln1116_38_fu_78047_p1 = select_ln1116_17_fu_78033_p3; + +assign zext_ln1116_39_fu_78057_p1 = sub_ln1116_17_reg_91345; + +assign zext_ln1116_3_fu_79184_p1 = lshr_ln1116_2_fu_79174_p4; + +assign zext_ln1116_40_fu_76211_p1 = tmp_124_fu_76191_p3; + +assign zext_ln1116_41_fu_76215_p1 = empty_102_fu_76199_p2; + +assign zext_ln1116_42_fu_76277_p1 = select_ln1116_20_fu_76263_p3; + +assign zext_ln1116_43_fu_76287_p1 = sub_ln1116_20_reg_90812; + +assign zext_ln1116_44_fu_74894_p1 = tmp_129_fu_74874_p3; + +assign zext_ln1116_45_fu_74898_p1 = empty_90_fu_74882_p2; + +assign zext_ln1116_46_fu_74960_p1 = select_ln1116_23_fu_74946_p3; + +assign zext_ln1116_47_fu_74970_p1 = sub_ln1116_23_reg_90455; + +assign zext_ln1116_48_fu_79672_p1 = tmp_159_fu_79653_p3; + +assign zext_ln1116_49_fu_79676_p1 = empty_136_fu_79660_p2; + +assign zext_ln1116_4_fu_74315_p1 = lshr_ln1116_3_fu_74305_p4; + +assign zext_ln1116_50_fu_79738_p1 = select_ln1116_26_fu_79724_p3; + +assign zext_ln1116_51_fu_79748_p1 = sub_ln1116_26_reg_91816; + +assign zext_ln1116_52_fu_78354_p1 = tmp_164_fu_78334_p3; + +assign zext_ln1116_53_fu_78358_p1 = empty_124_fu_78342_p2; + +assign zext_ln1116_54_fu_78420_p1 = select_ln1116_29_fu_78406_p3; + +assign zext_ln1116_55_fu_78430_p1 = sub_ln1116_29_reg_91448; + +assign zext_ln1116_56_fu_76574_p1 = tmp_168_fu_76554_p3; + +assign zext_ln1116_57_fu_76578_p1 = empty_106_fu_76562_p2; + +assign zext_ln1116_58_fu_76640_p1 = select_ln1116_32_fu_76626_p3; + +assign zext_ln1116_59_fu_76650_p1 = sub_ln1116_32_reg_90915; + +assign zext_ln1116_5_fu_77776_p1 = lshr_ln1116_4_fu_77766_p4; + +assign zext_ln1116_60_fu_80035_p1 = tmp_187_fu_80015_p3; + +assign zext_ln1116_61_fu_80039_p1 = empty_140_fu_80023_p2; + +assign zext_ln1116_62_fu_80101_p1 = select_ln1116_35_fu_80087_p3; + +assign zext_ln1116_63_fu_80111_p1 = sub_ln1116_35_reg_91919; + +assign zext_ln1116_64_fu_75244_p1 = tmp_203_fu_75225_p3; + +assign zext_ln1116_65_fu_75248_p1 = empty_92_fu_75232_p2; + +assign zext_ln1116_66_fu_75310_p1 = select_ln1116_38_fu_75296_p3; + +assign zext_ln1116_67_fu_75320_p1 = sub_ln1116_38_reg_90547; + +assign zext_ln1116_68_fu_78704_p1 = tmp_220_fu_78685_p3; + +assign zext_ln1116_69_fu_78708_p1 = empty_126_fu_78692_p2; + +assign zext_ln1116_6_fu_76005_p1 = lshr_ln1116_5_fu_75995_p4; + +assign zext_ln1116_70_fu_78770_p1 = select_ln1116_41_fu_78756_p3; + +assign zext_ln1116_71_fu_78780_p1 = sub_ln1116_41_reg_91540; + +assign zext_ln1116_72_fu_76924_p1 = tmp_224_fu_76905_p3; + +assign zext_ln1116_73_fu_76928_p1 = empty_108_fu_76912_p2; + +assign zext_ln1116_74_fu_76990_p1 = select_ln1116_44_fu_76976_p3; + +assign zext_ln1116_75_fu_77000_p1 = sub_ln1116_44_reg_91007; + +assign zext_ln1116_76_fu_80385_p1 = tmp_232_fu_80366_p3; + +assign zext_ln1116_77_fu_80389_p1 = empty_142_fu_80373_p2; + +assign zext_ln1116_78_fu_80451_p1 = select_ln1116_47_fu_80437_p3; + +assign zext_ln1116_79_fu_80461_p1 = sub_ln1116_47_reg_92011; + +assign zext_ln1116_7_fu_74845_p1 = lshr_ln1116_6_fu_74835_p4; + +assign zext_ln1116_8_fu_79472_p1 = lshr_ln1116_7_fu_79458_p4; + +assign zext_ln1116_9_fu_78305_p1 = lshr_ln1116_8_fu_78295_p4; + +assign zext_ln1116_fu_74020_p1 = lshr_ln_fu_74010_p4; + +assign zext_ln1265_10_fu_87892_p1 = add_ln1265_1_fu_87887_p2; + +assign zext_ln1265_11_fu_87910_p1 = (sext_ln1265_5_fu_87906_p1); + +assign zext_ln1265_13_fu_85943_p1 = tmp_69_reg_98765; + +assign zext_ln1265_15_fu_83687_p1 = tmp_72_reg_96520; + +assign zext_ln1265_17_fu_82100_p1 = tmp_80_reg_94895; + +assign zext_ln1265_19_fu_88034_p1 = tmp_86_reg_100594; + +assign zext_ln1265_1_fu_81541_p1 = (sext_ln1265_fu_81537_p1); + +assign zext_ln1265_20_fu_82074_p1 = or_ln1265_2_fu_82066_p3; + +assign zext_ln1265_22_fu_86315_p1 = tmp_95_reg_98964; + +assign zext_ln1265_24_fu_84059_p1 = tmp_97_reg_96719; + +assign zext_ln1265_26_fu_82266_p1 = tmp_101_reg_95061; + +assign zext_ln1265_27_fu_86289_p1 = or_ln1265_3_fu_86281_p3; + +assign zext_ln1265_28_fu_84033_p1 = or_ln1265_4_fu_84025_p3; + +assign zext_ln1265_2_fu_85662_p1 = (sext_ln1265_1_fu_85658_p1); + +assign zext_ln1265_30_fu_82628_p1 = tmp_117_reg_95407; + +assign zext_ln1265_32_fu_88406_p1 = tmp_132_reg_100793; + +assign zext_ln1265_34_fu_86614_p1 = tmp_136_reg_99135; + +assign zext_ln1265_36_fu_84358_p1 = tmp_140_reg_96890; + +assign zext_ln1265_37_fu_88380_p1 = or_ln1265_5_fu_88372_p3; + +assign zext_ln1265_39_fu_86975_p1 = tmp_151_reg_99481; + +assign zext_ln1265_3_fu_81745_p1 = (sext_ln1265_2_fu_81741_p1); + +assign zext_ln1265_41_fu_84719_p1 = tmp_154_reg_97236; + +assign zext_ln1265_43_fu_82445_p1 = tmp_156_reg_95235; + +assign zext_ln1265_45_fu_88705_p1 = tmp_173_reg_100964; + +assign zext_ln1265_47_fu_82952_p1 = tmp_175_reg_95595; + +assign zext_ln1265_49_fu_89066_p1 = tmp_179_reg_101310; + +assign zext_ln1265_4_fu_85828_p1 = (sext_ln1265_3_fu_85824_p1); + +assign zext_ln1265_51_fu_86792_p1 = tmp_181_reg_99309; + +assign zext_ln1265_53_fu_84536_p1 = tmp_183_reg_97064; + +assign zext_ln1265_55_fu_87299_p1 = tmp_190_reg_99669; + +assign zext_ln1265_57_fu_85042_p1 = tmp_192_reg_97424; + +assign zext_ln1265_59_fu_83235_p1 = tmp_195_reg_95766; + +assign zext_ln1265_5_fu_85763_p1 = or_ln1265_1_fu_85755_p3; + +assign zext_ln1265_61_fu_88883_p1 = tmp_198_reg_101138; + +assign zext_ln1265_63_fu_89389_p1 = tmp_206_reg_101498; + +assign zext_ln1265_65_fu_87582_p1 = tmp_209_reg_99840; + +assign zext_ln1265_67_fu_85324_p1 = tmp_212_reg_97595; + +assign zext_ln1265_69_fu_83397_p1 = tmp_217_reg_95940; + +assign zext_ln1265_6_fu_83545_p1 = add_ln1265_fu_83540_p2; + +assign zext_ln1265_71_fu_89671_p1 = tmp_228_reg_101669; + +assign zext_ln1265_73_fu_87744_p1 = tmp_235_reg_100014; + +assign zext_ln1265_75_fu_85485_p1 = tmp_236_reg_97769; + +assign zext_ln1265_77_fu_89832_p1 = tmp_240_reg_101843; + +assign zext_ln1265_7_fu_83563_p1 = (sext_ln1265_4_fu_83559_p1); + +assign zext_ln1265_9_fu_81860_p1 = tmp_51_reg_94701; + +assign zext_ln1265_fu_81680_p1 = or_ln3_fu_81672_p3; + +assign zext_ln199_fu_73740_p1 = or_ln199_fu_73734_p2; + +assign zext_ln201_2_fu_73798_p1 = or_ln201_fu_73792_p2; + +assign zext_ln201_3_fu_77256_p1 = or_ln201_1_fu_77250_p2; + +assign zext_ln203_10_fu_80987_p1 = (sext_ln203_6_fu_80983_p1); + +assign zext_ln203_12_fu_74449_p1 = tmp_5_reg_90344; + +assign zext_ln203_14_fu_74192_p1 = tmp_7_reg_90230; + +assign zext_ln203_15_fu_81363_p1 = (sext_ln203_7_fu_81359_p1); + +assign zext_ln203_17_fu_77910_p1 = tmp_55_reg_91337; + +assign zext_ln203_19_fu_77653_p1 = tmp_59_reg_91223; + +assign zext_ln203_21_fu_76139_p1 = tmp_60_reg_90804; + +assign zext_ln203_23_fu_75882_p1 = tmp_63_reg_90690; + +assign zext_ln203_25_fu_79622_p1 = tmp_75_reg_91808; + +assign zext_ln203_27_fu_79345_p1 = tmp_78_reg_91689; + +assign zext_ln203_29_fu_74722_p1 = tmp_91_reg_90417; + +assign zext_ln203_31_fu_74662_p1 = tmp_94_reg_90399; + +assign zext_ln203_33_fu_78182_p1 = tmp_119_reg_91410; + +assign zext_ln203_35_fu_78122_p1 = tmp_122_reg_91392; + +assign zext_ln203_37_fu_76412_p1 = tmp_123_reg_90877; + +assign zext_ln203_39_fu_76352_p1 = tmp_126_reg_90859; + +assign zext_ln203_3_fu_80711_p1 = (sext_ln203_fu_80707_p1); + +assign zext_ln203_41_fu_75194_p1 = tmp_127_reg_90539; + +assign zext_ln203_43_fu_75016_p1 = tmp_131_reg_90445; + +assign zext_ln203_45_fu_79873_p1 = tmp_158_reg_91881; + +assign zext_ln203_47_fu_79813_p1 = tmp_161_reg_91863; + +assign zext_ln203_49_fu_78654_p1 = tmp_162_reg_91532; + +assign zext_ln203_4_fu_77212_p1 = ff_0_1_0_reg_72793; + +assign zext_ln203_51_fu_78476_p1 = tmp_166_reg_91438; + +assign zext_ln203_53_fu_76874_p1 = tmp_167_reg_90999; + +assign zext_ln203_55_fu_76696_p1 = tmp_170_reg_90905; + +assign zext_ln203_57_fu_80335_p1 = tmp_186_reg_92003; + +assign zext_ln203_59_fu_80157_p1 = tmp_189_reg_91909; + +assign zext_ln203_5_fu_75482_p1 = ff_0_0_1_reg_72722; + +assign zext_ln203_61_fu_75445_p1 = tmp_202_reg_90612; + +assign zext_ln203_63_fu_75385_p1 = tmp_205_reg_90594; + +assign zext_ln203_65_fu_78905_p1 = tmp_219_reg_91605; + +assign zext_ln203_67_fu_78845_p1 = tmp_222_reg_91587; + +assign zext_ln203_69_fu_77125_p1 = tmp_223_reg_91072; + +assign zext_ln203_6_fu_81117_p1 = (sext_ln203_3_fu_81113_p1); + +assign zext_ln203_71_fu_77065_p1 = tmp_226_reg_91054; + +assign zext_ln203_73_fu_80586_p1 = tmp_237_reg_92076; + +assign zext_ln203_75_fu_80526_p1 = tmp_239_reg_92058; + +assign zext_ln203_7_fu_80880_p1 = (sext_ln203_4_fu_80876_p1); + +assign zext_ln203_8_fu_78942_p1 = ff_0_1_1_reg_72852; + +assign zext_ln203_9_fu_81256_p1 = (sext_ln203_5_fu_81252_p1); + +assign zext_ln203_fu_73754_p1 = ff_0_0_0_reg_72663; + +assign zext_ln216_10_fu_78967_p1 = add_ln216_12_fu_78962_p2; + +assign zext_ln216_11_fu_78976_p1 = add_ln216_13_fu_78971_p2; + +assign zext_ln216_1_fu_73779_p1 = add_ln216_fu_73774_p2; + +assign zext_ln216_2_fu_73788_p1 = add_ln216_1_fu_73783_p2; + +assign zext_ln216_3_fu_77228_p1 = phi_mul105001_reg_72805; + +assign zext_ln216_4_fu_77237_p1 = add_ln216_4_fu_77232_p2; + +assign zext_ln216_5_fu_77246_p1 = add_ln216_5_fu_77241_p2; + +assign zext_ln216_6_fu_75498_p1 = phi_mul104991_reg_72734; + +assign zext_ln216_7_fu_75507_p1 = add_ln216_6_fu_75502_p2; + +assign zext_ln216_8_fu_75516_p1 = add_ln216_7_fu_75511_p2; + +assign zext_ln216_9_fu_78958_p1 = phi_mul105011_reg_72864; + +assign zext_ln216_fu_73770_p1 = phi_mul_reg_72675; + +assign zext_ln231_3_fu_77176_p1 = ow_0_1_0_reg_72781; + +assign zext_ln231_fu_73710_p1 = ow_0_0_0_reg_72651; + +assign zext_ln232_10_fu_76491_p1 = add_ln221_22_fu_76453_p2; + +assign zext_ln232_11_fu_79952_p1 = add_ln221_25_fu_79914_p2; + +assign zext_ln232_12_fu_75119_p1 = add_ln221_26_fu_75075_p2; + +assign zext_ln232_13_fu_78579_p1 = add_ln221_27_fu_78535_p2; + +assign zext_ln232_14_fu_76799_p1 = add_ln221_28_fu_76755_p2; + +assign zext_ln232_15_fu_80260_p1 = add_ln221_29_fu_80216_p2; + +assign zext_ln232_1_fu_77438_p1 = add_ln221_6_fu_77400_p2; + +assign zext_ln232_2_fu_75676_p1 = add_ln221_7_fu_75638_p2; + +assign zext_ln232_3_fu_79140_p1 = add_ln221_9_fu_79102_p2; + +assign zext_ln232_4_fu_74295_p1 = add_ln221_10_fu_74251_p2; + +assign zext_ln232_5_fu_77756_p1 = add_ln221_13_fu_77712_p2; + +assign zext_ln232_6_fu_75985_p1 = add_ln221_14_fu_75941_p2; + +assign zext_ln232_7_fu_74801_p1 = add_ln221_15_fu_74763_p2; + +assign zext_ln232_8_fu_79448_p1 = add_ln221_20_fu_79404_p2; + +assign zext_ln232_9_fu_78261_p1 = add_ln221_21_fu_78223_p2; + +assign zext_ln232_fu_73976_p1 = add_ln221_3_fu_73938_p2; + +assign zext_ln250_1_fu_80643_p1 = shl_ln250_8_fu_80635_p3; + +assign zext_ln250_2_fu_80793_p1 = shl_ln250_9_fu_80785_p3; + +assign zext_ln250_3_fu_80805_p1 = shl_ln250_s_fu_80797_p3; + +assign zext_ln250_4_fu_80671_p1 = shl_ln250_1_fu_80663_p3; + +assign zext_ln250_5_fu_81077_p1 = shl_ln250_2_fu_81069_p3; + +assign zext_ln250_6_fu_80847_p1 = or_ln250_fu_80842_p2; + +assign zext_ln250_7_fu_81219_p1 = or_ln250_1_fu_81214_p2; + +assign zext_ln250_8_fu_80959_p1 = ff4_0_0_1_0_reg_72947; + +assign zext_ln250_9_fu_81335_p1 = ff4_0_1_1_0_reg_72983; + +assign zext_ln250_fu_80631_p1 = shl_ln_fu_80623_p3; + +assign zext_ln276_1_fu_85767_p1 = grp_fu_90028_p3; + +assign zext_ln276_2_fu_83631_p1 = grp_fu_90005_p3; + +assign zext_ln276_3_fu_87978_p1 = grp_fu_90051_p3; + +assign zext_ln276_4_fu_82078_p1 = grp_fu_89997_p3; + +assign zext_ln276_5_fu_86293_p1 = grp_fu_90043_p3; + +assign zext_ln276_6_fu_84037_p1 = grp_fu_90013_p3; + +assign zext_ln276_7_fu_88384_p1 = grp_fu_90059_p3; + +assign zext_ln276_fu_81684_p1 = grp_fu_89982_p3; + +assign zext_ln279_11_fu_81705_p1 = shl_ln279_3_fu_81697_p3; + +assign zext_ln279_14_fu_85788_p1 = shl_ln279_4_fu_85780_p3; + +assign zext_ln279_17_fu_83531_p1 = ff7_0_0_1_0_reg_73103; + +assign zext_ln279_19_fu_87878_p1 = ff7_0_1_1_0_reg_73283; + +assign zext_ln279_1_fu_81457_p1 = shl_ln5_fu_81449_p3; + +assign zext_ln279_2_fu_81469_p1 = shl_ln279_8_fu_81461_p3; + +assign zext_ln279_4_fu_81627_p1 = shl_ln279_9_fu_81619_p3; + +assign zext_ln279_5_fu_81639_p1 = shl_ln279_s_fu_81631_p3; + +assign zext_ln279_7_fu_81501_p1 = shl_ln279_1_fu_81493_p3; + +assign zext_ln279_9_fu_85622_p1 = shl_ln279_2_fu_85614_p3; + +always @ (posedge ap_clk) begin + oh_0_0_cast_reg_90067[31:5] <= 27'b000000000000000000000000000; + ow_0_0_0_cast_reg_90084[31:5] <= 27'b000000000000000000000000000; + zext_ln231_reg_90100[6:5] <= 2'b00; + zext_ln199_reg_90126[0] <= 1'b1; + zext_ln199_reg_90126[31:5] <= 27'b000000000000000000000000000; + zext_ln203_reg_90145[31:3] <= 29'b00000000000000000000000000000; + zext_ln216_2_reg_90158[31:17] <= 15'b000000000000000; + zext_ln201_2_reg_90164[0] <= 1'b1; + zext_ln201_2_reg_90164[31:5] <= 27'b000000000000000000000000000; + mul_ln231_2_reg_90172[1:0] <= 2'b00; + trunc_ln231_2_reg_90193[1:0] <= 2'b00; + sub_ln1116_2_reg_90240[0] <= 1'b0; + trunc_ln231_10_reg_90328[1:0] <= 2'b00; + trunc_ln1116_6_reg_90333[1:0] <= 2'b00; + sub_ln1116_14_reg_90352[0] <= 1'b0; + sub_ln1116_23_reg_90455[0] <= 1'b0; + sub_ln1116_38_reg_90547[0] <= 1'b0; + zext_ln203_5_reg_90625[31:3] <= 29'b00000000000000000000000000000; + zext_ln216_8_reg_90638[31:17] <= 15'b000000000000000; + trunc_ln231_4_reg_90653[1:0] <= 2'b00; + sub_ln1116_8_reg_90700[0] <= 1'b0; + trunc_ln231_12_reg_90788[1:0] <= 2'b00; + trunc_ln1116_10_reg_90793[1:0] <= 2'b00; + sub_ln1116_20_reg_90812[0] <= 1'b0; + sub_ln1116_32_reg_90915[0] <= 1'b0; + sub_ln1116_44_reg_91007[0] <= 1'b0; + ow_0_1_0_cast_reg_91080[31:5] <= 27'b000000000000000000000000000; + zext_ln231_3_reg_91096[6:5] <= 2'b00; + zext_ln203_4_reg_91130[31:3] <= 29'b00000000000000000000000000000; + zext_ln216_5_reg_91143[31:17] <= 15'b000000000000000; + zext_ln201_3_reg_91149[0] <= 1'b1; + zext_ln201_3_reg_91149[31:5] <= 27'b000000000000000000000000000; + mul_ln231_3_reg_91157[1:0] <= 2'b00; + trunc_ln231_3_reg_91180[1:0] <= 2'b00; + trunc_ln1116_reg_91185[1:0] <= 2'b00; + sub_ln1116_5_reg_91233[0] <= 1'b0; + trunc_ln231_11_reg_91321[2:0] <= 3'b000; + trunc_ln1116_9_reg_91326[2:0] <= 3'b000; + sub_ln1116_17_reg_91345[0] <= 1'b0; + sub_ln1116_29_reg_91448[0] <= 1'b0; + sub_ln1116_41_reg_91540[0] <= 1'b0; + zext_ln203_8_reg_91618[31:3] <= 29'b00000000000000000000000000000; + zext_ln216_11_reg_91631[31:17] <= 15'b000000000000000; + trunc_ln231_6_reg_91646[1:0] <= 2'b00; + trunc_ln1116_2_reg_91651[1:0] <= 2'b00; + sub_ln1116_11_reg_91699[0] <= 1'b0; + trunc_ln231_14_reg_91792[2:0] <= 3'b000; + trunc_ln1116_16_reg_91797[2:0] <= 3'b000; + sub_ln1116_26_reg_91816[0] <= 1'b0; + sub_ln1116_35_reg_91919[0] <= 1'b0; + sub_ln1116_47_reg_92011[0] <= 1'b0; + sub_ln250_reg_92087[3:0] <= 4'b0000; + trunc_ln250_reg_92093[3:0] <= 4'b0000; + shl_ln250_1_reg_92102[1:0] <= 2'b00; + trunc_ln250_8_reg_92107[1:0] <= 2'b00; + add_ln250_1_reg_92112[1:0] <= 2'b00; + sub_ln250_1_reg_92438[4:0] <= 5'b10000; + trunc_ln250_1_reg_92444[4:0] <= 5'b10000; + add_ln250_4_reg_92456[2:0] <= 3'b100; + add_ln250_5_reg_92461[2:0] <= 3'b100; + shl_ln250_2_reg_92657[1:0] <= 2'b00; + trunc_ln250_9_reg_92662[1:0] <= 2'b00; + add_ln250_3_reg_92667[1:0] <= 2'b00; + sext_ln250_reg_93004[2:0] <= 3'b100; + add_ln250_7_reg_93009[2:0] <= 3'b100; + sub_ln279_reg_93211[3:0] <= 4'b0000; + trunc_ln279_reg_93217[3:0] <= 4'b0000; + add_ln279_1_reg_93866[1:0] <= 2'b00; + sub_ln279_1_reg_94253[4:0] <= 5'b10000; + trunc_ln279_1_reg_94259[4:0] <= 5'b10000; + zext_ln1265_reg_94272[31:6] <= 26'b00000000000000000000000000; + zext_ln276_reg_94277[31:17] <= 15'b000000000000000; + add_ln279_4_reg_94283[2:0] <= 3'b100; + add_ln279_5_reg_94288[2:0] <= 3'b100; + or_ln1265_2_reg_94874[0] <= 1'b1; + zext_ln1265_20_reg_94878[0] <= 1'b1; + zext_ln1265_20_reg_94878[31:6] <= 26'b00000000000000000000000000; + zext_ln276_4_reg_94884[31:17] <= 15'b000000000000000; + zext_ln1265_6_reg_96102[31:6] <= 26'b00000000000000000000000000; + zext_ln276_2_reg_96306[31:17] <= 15'b000000000000000; + or_ln1265_4_reg_96698[0] <= 1'b1; + or_ln1265_4_reg_96698[2] <= 1'b1; + zext_ln1265_28_reg_96702[0] <= 1'b1; + zext_ln1265_28_reg_96702[2:2] <= 1'b1; + zext_ln1265_28_reg_96702[31:6] <= 26'b00000000000000000000000000; + zext_ln276_6_reg_96708[31:17] <= 15'b000000000000000; + add_ln279_3_reg_97927[1:0] <= 2'b00; + zext_ln1265_5_reg_98335[31:6] <= 26'b00000000000000000000000000; + zext_ln276_1_reg_98341[31:17] <= 15'b000000000000000; + add_ln279_6_reg_98347[2:0] <= 3'b100; + add_ln279_7_reg_98352[2:0] <= 3'b100; + or_ln1265_3_reg_98943[0] <= 1'b1; + zext_ln1265_27_reg_98947[0] <= 1'b1; + zext_ln1265_27_reg_98947[31:6] <= 26'b00000000000000000000000000; + zext_ln276_5_reg_98953[31:17] <= 15'b000000000000000; + zext_ln1265_10_reg_100176[31:6] <= 26'b00000000000000000000000000; + zext_ln276_3_reg_100380[31:17] <= 15'b000000000000000; + or_ln1265_5_reg_100772[0] <= 1'b1; + or_ln1265_5_reg_100772[2] <= 1'b1; + zext_ln1265_37_reg_100776[0] <= 1'b1; + zext_ln1265_37_reg_100776[2:2] <= 1'b1; + zext_ln1265_37_reg_100776[31:6] <= 26'b00000000000000000000000000; + zext_ln276_7_reg_100782[31:17] <= 15'b000000000000000; +end + +endmodule //conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0 +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + module conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_w2_V_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 5; +parameter AWIDTH = 7; +parameter MEM_SIZE = 100; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +`ifdef QUARTUS +initial begin + $readmemh("/home/boutros6/koios++/quartus_runs/rtl/lenet_rom/conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_w2_V_rom.dat", ram); +end +`endif + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_w2_V( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd5; +parameter AddressRange = 32'd100; +parameter AddressWidth = 32'd7; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_w2_V_rom conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_w2_V_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + op_V_assign_dout, + op_V_assign_empty_n, + op_V_assign_read, + res_8_V, + res_8_V_ap_vld, + p_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] op_V_assign_dout; +input op_V_assign_empty_n; +output op_V_assign_read; +output [7:0] res_8_V; +output res_8_V_ap_vld; +input [7:0] p_read; +output [7:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_read; +reg[7:0] res_8_V; +reg res_8_V_ap_vld; +reg[7:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_blk_n; +reg ap_block_state1; +reg [7:0] res_8_V_preg; +reg [7:0] ap_return_preg; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +#0 res_8_V_preg = 8'd0; +#0 ap_return_preg = 8'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return_preg <= p_read; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + res_8_V_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_8_V_preg <= op_V_assign_dout; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return = p_read; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_blk_n = op_V_assign_empty_n; + end else begin + op_V_assign_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_read = 1'b1; + end else begin + op_V_assign_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_8_V = op_V_assign_dout; + end else begin + res_8_V = res_8_V_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_8_V_ap_vld = 1'b1; + end else begin + res_8_V_ap_vld = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + op_V_assign_dout, + op_V_assign_empty_n, + op_V_assign_read, + res_9_V, + res_9_V_ap_vld +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] op_V_assign_dout; +input op_V_assign_empty_n; +output op_V_assign_read; +output [7:0] res_9_V; +output res_9_V_ap_vld; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_read; +reg[7:0] res_9_V; +reg res_9_V_ap_vld; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_blk_n; +reg ap_block_state1; +reg [7:0] res_9_V_preg; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +#0 res_9_V_preg = 8'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + res_9_V_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_9_V_preg <= op_V_assign_dout; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_blk_n = op_V_assign_empty_n; + end else begin + op_V_assign_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_read = 1'b1; + end else begin + op_V_assign_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_9_V = op_V_assign_dout; + end else begin + res_9_V = res_9_V_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_9_V_ap_vld = 1'b1; + end else begin + res_9_V_ap_vld = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + op_V_assign_dout, + op_V_assign_empty_n, + op_V_assign_read, + res_0_V, + res_0_V_ap_vld, + p_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] op_V_assign_dout; +input op_V_assign_empty_n; +output op_V_assign_read; +output [7:0] res_0_V; +output res_0_V_ap_vld; +input [7:0] p_read; +output [7:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_read; +reg[7:0] res_0_V; +reg res_0_V_ap_vld; +reg[7:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_blk_n; +reg ap_block_state1; +reg [7:0] res_0_V_preg; +reg [7:0] ap_return_preg; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +#0 res_0_V_preg = 8'd0; +#0 ap_return_preg = 8'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return_preg <= p_read; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + res_0_V_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_0_V_preg <= op_V_assign_dout; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return = p_read; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_blk_n = op_V_assign_empty_n; + end else begin + op_V_assign_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_read = 1'b1; + end else begin + op_V_assign_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_0_V = op_V_assign_dout; + end else begin + res_0_V = res_0_V_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_0_V_ap_vld = 1'b1; + end else begin + res_0_V_ap_vld = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + op_V_assign_dout, + op_V_assign_empty_n, + op_V_assign_read, + res_1_V, + res_1_V_ap_vld, + p_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] op_V_assign_dout; +input op_V_assign_empty_n; +output op_V_assign_read; +output [7:0] res_1_V; +output res_1_V_ap_vld; +input [7:0] p_read; +output [7:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_read; +reg[7:0] res_1_V; +reg res_1_V_ap_vld; +reg[7:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_blk_n; +reg ap_block_state1; +reg [7:0] res_1_V_preg; +reg [7:0] ap_return_preg; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +#0 res_1_V_preg = 8'd0; +#0 ap_return_preg = 8'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return_preg <= p_read; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + res_1_V_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_1_V_preg <= op_V_assign_dout; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return = p_read; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_blk_n = op_V_assign_empty_n; + end else begin + op_V_assign_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_read = 1'b1; + end else begin + op_V_assign_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_1_V = op_V_assign_dout; + end else begin + res_1_V = res_1_V_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_1_V_ap_vld = 1'b1; + end else begin + res_1_V_ap_vld = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + op_V_assign_dout, + op_V_assign_empty_n, + op_V_assign_read, + res_2_V, + res_2_V_ap_vld, + p_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] op_V_assign_dout; +input op_V_assign_empty_n; +output op_V_assign_read; +output [7:0] res_2_V; +output res_2_V_ap_vld; +input [7:0] p_read; +output [7:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_read; +reg[7:0] res_2_V; +reg res_2_V_ap_vld; +reg[7:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_blk_n; +reg ap_block_state1; +reg [7:0] res_2_V_preg; +reg [7:0] ap_return_preg; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +#0 res_2_V_preg = 8'd0; +#0 ap_return_preg = 8'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return_preg <= p_read; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + res_2_V_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_2_V_preg <= op_V_assign_dout; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return = p_read; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_blk_n = op_V_assign_empty_n; + end else begin + op_V_assign_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_read = 1'b1; + end else begin + op_V_assign_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_2_V = op_V_assign_dout; + end else begin + res_2_V = res_2_V_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_2_V_ap_vld = 1'b1; + end else begin + res_2_V_ap_vld = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + op_V_assign_dout, + op_V_assign_empty_n, + op_V_assign_read, + res_3_V, + res_3_V_ap_vld, + p_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] op_V_assign_dout; +input op_V_assign_empty_n; +output op_V_assign_read; +output [7:0] res_3_V; +output res_3_V_ap_vld; +input [7:0] p_read; +output [7:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_read; +reg[7:0] res_3_V; +reg res_3_V_ap_vld; +reg[7:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_blk_n; +reg ap_block_state1; +reg [7:0] res_3_V_preg; +reg [7:0] ap_return_preg; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +#0 res_3_V_preg = 8'd0; +#0 ap_return_preg = 8'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return_preg <= p_read; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + res_3_V_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_3_V_preg <= op_V_assign_dout; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return = p_read; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_blk_n = op_V_assign_empty_n; + end else begin + op_V_assign_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_read = 1'b1; + end else begin + op_V_assign_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_3_V = op_V_assign_dout; + end else begin + res_3_V = res_3_V_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_3_V_ap_vld = 1'b1; + end else begin + res_3_V_ap_vld = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + op_V_assign_dout, + op_V_assign_empty_n, + op_V_assign_read, + res_4_V, + res_4_V_ap_vld, + p_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] op_V_assign_dout; +input op_V_assign_empty_n; +output op_V_assign_read; +output [7:0] res_4_V; +output res_4_V_ap_vld; +input [7:0] p_read; +output [7:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_read; +reg[7:0] res_4_V; +reg res_4_V_ap_vld; +reg[7:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_blk_n; +reg ap_block_state1; +reg [7:0] res_4_V_preg; +reg [7:0] ap_return_preg; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +#0 res_4_V_preg = 8'd0; +#0 ap_return_preg = 8'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return_preg <= p_read; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + res_4_V_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_4_V_preg <= op_V_assign_dout; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return = p_read; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_blk_n = op_V_assign_empty_n; + end else begin + op_V_assign_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_read = 1'b1; + end else begin + op_V_assign_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_4_V = op_V_assign_dout; + end else begin + res_4_V = res_4_V_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_4_V_ap_vld = 1'b1; + end else begin + res_4_V_ap_vld = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + op_V_assign_dout, + op_V_assign_empty_n, + op_V_assign_read, + res_5_V, + res_5_V_ap_vld, + p_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] op_V_assign_dout; +input op_V_assign_empty_n; +output op_V_assign_read; +output [7:0] res_5_V; +output res_5_V_ap_vld; +input [7:0] p_read; +output [7:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_read; +reg[7:0] res_5_V; +reg res_5_V_ap_vld; +reg[7:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_blk_n; +reg ap_block_state1; +reg [7:0] res_5_V_preg; +reg [7:0] ap_return_preg; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +#0 res_5_V_preg = 8'd0; +#0 ap_return_preg = 8'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return_preg <= p_read; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + res_5_V_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_5_V_preg <= op_V_assign_dout; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return = p_read; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_blk_n = op_V_assign_empty_n; + end else begin + op_V_assign_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_read = 1'b1; + end else begin + op_V_assign_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_5_V = op_V_assign_dout; + end else begin + res_5_V = res_5_V_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_5_V_ap_vld = 1'b1; + end else begin + res_5_V_ap_vld = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + op_V_assign_dout, + op_V_assign_empty_n, + op_V_assign_read, + res_6_V, + res_6_V_ap_vld, + p_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] op_V_assign_dout; +input op_V_assign_empty_n; +output op_V_assign_read; +output [7:0] res_6_V; +output res_6_V_ap_vld; +input [7:0] p_read; +output [7:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_read; +reg[7:0] res_6_V; +reg res_6_V_ap_vld; +reg[7:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_blk_n; +reg ap_block_state1; +reg [7:0] res_6_V_preg; +reg [7:0] ap_return_preg; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +#0 res_6_V_preg = 8'd0; +#0 ap_return_preg = 8'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return_preg <= p_read; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + res_6_V_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_6_V_preg <= op_V_assign_dout; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return = p_read; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_blk_n = op_V_assign_empty_n; + end else begin + op_V_assign_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_read = 1'b1; + end else begin + op_V_assign_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_6_V = op_V_assign_dout; + end else begin + res_6_V = res_6_V_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_6_V_ap_vld = 1'b1; + end else begin + res_6_V_ap_vld = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + op_V_assign_dout, + op_V_assign_empty_n, + op_V_assign_read, + res_7_V, + res_7_V_ap_vld, + p_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd0; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [7:0] op_V_assign_dout; +input op_V_assign_empty_n; +output op_V_assign_read; +output [7:0] res_7_V; +output res_7_V_ap_vld; +input [7:0] p_read; +output [7:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg op_V_assign_read; +reg[7:0] res_7_V; +reg res_7_V_ap_vld; +reg[7:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +reg op_V_assign_blk_n; +reg ap_block_state1; +reg [7:0] res_7_V_preg; +reg [7:0] ap_return_preg; +reg [0:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd0; +#0 res_7_V_preg = 8'd0; +#0 ap_return_preg = 8'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return_preg <= p_read; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + res_7_V_preg <= 8'd0; + end else begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_7_V_preg <= op_V_assign_dout; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_return = p_read; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_blk_n = op_V_assign_empty_n; + end else begin + op_V_assign_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + op_V_assign_read = 1'b1; + end else begin + op_V_assign_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_7_V = op_V_assign_dout; + end else begin + res_7_V = res_7_V_preg; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + res_7_V_ap_vld = 1'b1; + end else begin + res_7_V_ap_vld = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (op_V_assign_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + mult_0_dout, + mult_0_empty_n, + mult_0_read, + mult_1_dout, + mult_1_empty_n, + mult_1_read, + mult_2_dout, + mult_2_empty_n, + mult_2_read, + mult_3_dout, + mult_3_empty_n, + mult_3_read, + mult_4_dout, + mult_4_empty_n, + mult_4_read, + mult_5_dout, + mult_5_empty_n, + mult_5_read, + mult_6_dout, + mult_6_empty_n, + mult_6_read, + mult_7_dout, + mult_7_empty_n, + mult_7_read, + mult_8_dout, + mult_8_empty_n, + mult_8_read, + mult_9_dout, + mult_9_empty_n, + mult_9_read, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3, + ap_return_4, + ap_return_5, + ap_return_6, + ap_return_7, + ap_return_8, + ap_return_9 +); + +parameter ap_ST_fsm_state1 = 2'd0; +parameter ap_ST_fsm_pp0_stage0 = 2'd1; +parameter ap_ST_fsm_state4 = 2'd2; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [6:0] mult_0_dout; +input mult_0_empty_n; +output mult_0_read; +input [6:0] mult_1_dout; +input mult_1_empty_n; +output mult_1_read; +input [6:0] mult_2_dout; +input mult_2_empty_n; +output mult_2_read; +input [6:0] mult_3_dout; +input mult_3_empty_n; +output mult_3_read; +input [6:0] mult_4_dout; +input mult_4_empty_n; +output mult_4_read; +input [6:0] mult_5_dout; +input mult_5_empty_n; +output mult_5_read; +input [6:0] mult_6_dout; +input mult_6_empty_n; +output mult_6_read; +input [6:0] mult_7_dout; +input mult_7_empty_n; +output mult_7_read; +input [6:0] mult_8_dout; +input mult_8_empty_n; +output mult_8_read; +input [6:0] mult_9_dout; +input mult_9_empty_n; +output mult_9_read; +output [7:0] ap_return_0; +output [7:0] ap_return_1; +output [7:0] ap_return_2; +output [7:0] ap_return_3; +output [7:0] ap_return_4; +output [7:0] ap_return_5; +output [7:0] ap_return_6; +output [7:0] ap_return_7; +output [7:0] ap_return_8; +output [7:0] ap_return_9; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg mult_0_read; +reg mult_1_read; +reg mult_2_read; +reg mult_3_read; +reg mult_4_read; +reg mult_5_read; +reg mult_6_read; +reg mult_7_read; +reg mult_8_read; +reg mult_9_read; + +reg ap_done_reg; + reg [1:0] ap_CS_fsm; +reg mult_0_blk_n; +reg ap_enable_reg_pp0_iter1; +wire ap_block_pp0_stage0; +reg [0:0] icmp_ln109_reg_433; +reg mult_1_blk_n; +reg mult_2_blk_n; +reg mult_3_blk_n; +reg mult_4_blk_n; +reg mult_5_blk_n; +reg mult_6_blk_n; +reg mult_7_blk_n; +reg mult_8_blk_n; +reg mult_9_blk_n; +reg [7:0] acc_4_V_write_assign_reg_130; +reg [7:0] acc_5_V_write_assign_reg_142; +reg [7:0] acc_3_V_write_assign_reg_154; +reg [7:0] acc_6_V_write_assign_reg_166; +reg [7:0] acc_7_V_write_assign_reg_178; +reg [7:0] acc_2_V_write_assign_reg_190; +reg [7:0] acc_8_V_write_assign_reg_202; +reg [7:0] acc_9_V_write_assign_reg_214; +reg [7:0] acc_1_V_write_assign_reg_226; +reg [7:0] p_0_0_out_0_reg_238; +reg [9:0] ii2_0_reg_250; +wire [0:0] icmp_ln109_fu_261_p2; +wire ap_block_state2_pp0_stage0_iter0; +reg ap_block_state3_pp0_stage0_iter1; +reg ap_block_pp0_stage0_11001; +wire [9:0] ii_fu_267_p2; +reg ap_enable_reg_pp0_iter0; +wire [7:0] acc_0_V_fu_277_p2; +wire [7:0] acc_1_V_fu_287_p2; +wire [7:0] acc_2_V_fu_297_p2; +wire [7:0] acc_3_V_fu_307_p2; +wire [7:0] acc_4_V_fu_317_p2; +wire [7:0] acc_5_V_fu_327_p2; +wire [7:0] acc_6_V_fu_337_p2; +wire [7:0] acc_7_V_fu_347_p2; +wire [7:0] acc_8_V_fu_357_p2; +wire [7:0] acc_9_V_fu_367_p2; +reg ap_block_state1; +reg ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +wire [7:0] sext_ln1265_fu_273_p1; +wire [7:0] sext_ln1265_1_fu_283_p1; +wire [7:0] sext_ln1265_2_fu_293_p1; +wire [7:0] sext_ln1265_3_fu_303_p1; +wire [7:0] sext_ln1265_4_fu_313_p1; +wire [7:0] sext_ln1265_5_fu_323_p1; +wire [7:0] sext_ln1265_6_fu_333_p1; +wire [7:0] sext_ln1265_7_fu_343_p1; +wire [7:0] sext_ln1265_8_fu_353_p1; +wire [7:0] sext_ln1265_9_fu_363_p1; +reg [1:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 2'd0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + acc_1_V_write_assign_reg_226 <= acc_1_V_fu_287_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + acc_1_V_write_assign_reg_226 <= 8'd1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + acc_2_V_write_assign_reg_190 <= acc_2_V_fu_297_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + acc_2_V_write_assign_reg_190 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + acc_3_V_write_assign_reg_154 <= acc_3_V_fu_307_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + acc_3_V_write_assign_reg_154 <= 8'd255; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + acc_4_V_write_assign_reg_130 <= acc_4_V_fu_317_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + acc_4_V_write_assign_reg_130 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + acc_5_V_write_assign_reg_142 <= acc_5_V_fu_327_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + acc_5_V_write_assign_reg_142 <= 8'd255; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + acc_6_V_write_assign_reg_166 <= acc_6_V_fu_337_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + acc_6_V_write_assign_reg_166 <= 8'd255; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + acc_7_V_write_assign_reg_178 <= acc_7_V_fu_347_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + acc_7_V_write_assign_reg_178 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + acc_8_V_write_assign_reg_202 <= acc_8_V_fu_357_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + acc_8_V_write_assign_reg_202 <= 8'd255; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + acc_9_V_write_assign_reg_214 <= acc_9_V_fu_367_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + acc_9_V_write_assign_reg_214 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln109_fu_261_p2 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii2_0_reg_250 <= ii_fu_267_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ii2_0_reg_250 <= 10'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + p_0_0_out_0_reg_238 <= acc_0_V_fu_277_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + p_0_0_out_0_reg_238 <= 8'd255; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln109_reg_433 <= icmp_ln109_fu_261_p2; + end +end + +always @ (*) begin + if ((icmp_ln109_fu_261_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_0_blk_n = mult_0_empty_n; + end else begin + mult_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mult_0_read = 1'b1; + end else begin + mult_0_read = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_1_blk_n = mult_1_empty_n; + end else begin + mult_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mult_1_read = 1'b1; + end else begin + mult_1_read = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_2_blk_n = mult_2_empty_n; + end else begin + mult_2_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mult_2_read = 1'b1; + end else begin + mult_2_read = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_3_blk_n = mult_3_empty_n; + end else begin + mult_3_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mult_3_read = 1'b1; + end else begin + mult_3_read = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_4_blk_n = mult_4_empty_n; + end else begin + mult_4_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mult_4_read = 1'b1; + end else begin + mult_4_read = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_5_blk_n = mult_5_empty_n; + end else begin + mult_5_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mult_5_read = 1'b1; + end else begin + mult_5_read = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_6_blk_n = mult_6_empty_n; + end else begin + mult_6_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mult_6_read = 1'b1; + end else begin + mult_6_read = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_7_blk_n = mult_7_empty_n; + end else begin + mult_7_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mult_7_read = 1'b1; + end else begin + mult_7_read = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_8_blk_n = mult_8_empty_n; + end else begin + mult_8_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mult_8_read = 1'b1; + end else begin + mult_8_read = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_9_blk_n = mult_9_empty_n; + end else begin + mult_9_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln109_reg_433 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mult_9_read = 1'b1; + end else begin + mult_9_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln109_fu_261_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln109_fu_261_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +assign acc_0_V_fu_277_p2 = ((sext_ln1265_fu_273_p1) + (p_0_0_out_0_reg_238)); + +assign acc_1_V_fu_287_p2 = ((sext_ln1265_1_fu_283_p1) + (acc_1_V_write_assign_reg_226)); + +assign acc_2_V_fu_297_p2 = ((sext_ln1265_2_fu_293_p1) + (acc_2_V_write_assign_reg_190)); + +assign acc_3_V_fu_307_p2 = ((sext_ln1265_3_fu_303_p1) + (acc_3_V_write_assign_reg_154)); + +assign acc_4_V_fu_317_p2 = ((sext_ln1265_4_fu_313_p1) + (acc_4_V_write_assign_reg_130)); + +assign acc_5_V_fu_327_p2 = ((sext_ln1265_5_fu_323_p1) + (acc_5_V_write_assign_reg_142)); + +assign acc_6_V_fu_337_p2 = ((sext_ln1265_6_fu_333_p1) + (acc_6_V_write_assign_reg_166)); + +assign acc_7_V_fu_347_p2 = ((sext_ln1265_7_fu_343_p1) + (acc_7_V_write_assign_reg_178)); + +assign acc_8_V_fu_357_p2 = ((sext_ln1265_8_fu_353_p1) + (acc_8_V_write_assign_reg_202)); + +assign acc_9_V_fu_367_p2 = ((sext_ln1265_9_fu_363_p1) + (acc_9_V_write_assign_reg_214)); + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_pp0_stage0_11001 = ((ap_enable_reg_pp0_iter1 == 1'b1) & (((icmp_ln109_reg_433 == 1'd0) & (mult_9_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_8_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_7_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_6_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_5_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_4_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_3_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_2_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_1_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_0_empty_n == 1'b0)))); +end + +always @ (*) begin + ap_block_pp0_stage0_subdone = ((ap_enable_reg_pp0_iter1 == 1'b1) & (((icmp_ln109_reg_433 == 1'd0) & (mult_9_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_8_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_7_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_6_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_5_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_4_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_3_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_2_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_1_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_0_empty_n == 1'b0)))); +end + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state3_pp0_stage0_iter1 = (((icmp_ln109_reg_433 == 1'd0) & (mult_9_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_8_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_7_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_6_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_5_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_4_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_3_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_2_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_1_empty_n == 1'b0)) | ((icmp_ln109_reg_433 == 1'd0) & (mult_0_empty_n == 1'b0))); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = acc_1_V_write_assign_reg_226; + +assign ap_return_1 = acc_2_V_write_assign_reg_190; + +assign ap_return_2 = acc_3_V_write_assign_reg_154; + +assign ap_return_3 = acc_4_V_write_assign_reg_130; + +assign ap_return_4 = acc_5_V_write_assign_reg_142; + +assign ap_return_5 = acc_6_V_write_assign_reg_166; + +assign ap_return_6 = acc_7_V_write_assign_reg_178; + +assign ap_return_7 = acc_8_V_write_assign_reg_202; + +assign ap_return_8 = acc_9_V_write_assign_reg_214; + +assign ap_return_9 = p_0_0_out_0_reg_238; + +assign icmp_ln109_fu_261_p2 = ((ii2_0_reg_250 == 10'd588) ? 1'b1 : 1'b0); + +assign ii_fu_267_p2 = (ii2_0_reg_250 + 10'd1); + +assign sext_ln1265_1_fu_283_p1 = (mult_1_dout); + +assign sext_ln1265_2_fu_293_p1 = (mult_2_dout); + +assign sext_ln1265_3_fu_303_p1 = (mult_3_dout); + +assign sext_ln1265_4_fu_313_p1 = (mult_4_dout); + +assign sext_ln1265_5_fu_323_p1 = (mult_5_dout); + +assign sext_ln1265_6_fu_333_p1 = (mult_6_dout); + +assign sext_ln1265_7_fu_343_p1 = (mult_7_dout); + +assign sext_ln1265_8_fu_353_p1 = (mult_8_dout); + +assign sext_ln1265_9_fu_363_p1 = (mult_9_dout); + +assign sext_ln1265_fu_273_p1 = (mult_0_dout); + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + data_0_V_address0, + data_0_V_ce0, + data_0_V_q0, + data_1_V_address0, + data_1_V_ce0, + data_1_V_q0, + data_2_V_address0, + data_2_V_ce0, + data_2_V_q0, + data_3_V_address0, + data_3_V_ce0, + data_3_V_q0, + data_4_V_address0, + data_4_V_ce0, + data_4_V_q0, + data_5_V_address0, + data_5_V_ce0, + data_5_V_q0, + data_6_V_address0, + data_6_V_ce0, + data_6_V_q0, + data_7_V_address0, + data_7_V_ce0, + data_7_V_q0, + data_8_V_address0, + data_8_V_ce0, + data_8_V_q0, + data_9_V_address0, + data_9_V_ce0, + data_9_V_q0, + data_10_V_address0, + data_10_V_ce0, + data_10_V_q0, + data_11_V_address0, + data_11_V_ce0, + data_11_V_q0, + data_12_V_address0, + data_12_V_ce0, + data_12_V_q0, + data_13_V_address0, + data_13_V_ce0, + data_13_V_q0, + data_14_V_address0, + data_14_V_ce0, + data_14_V_q0, + data_15_V_address0, + data_15_V_ce0, + data_15_V_q0, + data_16_V_address0, + data_16_V_ce0, + data_16_V_q0, + data_17_V_address0, + data_17_V_ce0, + data_17_V_q0, + data_18_V_address0, + data_18_V_ce0, + data_18_V_q0, + data_19_V_address0, + data_19_V_ce0, + data_19_V_q0, + data_20_V_address0, + data_20_V_ce0, + data_20_V_q0, + data_21_V_address0, + data_21_V_ce0, + data_21_V_q0, + data_22_V_address0, + data_22_V_ce0, + data_22_V_q0, + data_23_V_address0, + data_23_V_ce0, + data_23_V_q0, + data_24_V_address0, + data_24_V_ce0, + data_24_V_q0, + data_25_V_address0, + data_25_V_ce0, + data_25_V_q0, + data_26_V_address0, + data_26_V_ce0, + data_26_V_q0, + data_27_V_address0, + data_27_V_ce0, + data_27_V_q0, + data_28_V_address0, + data_28_V_ce0, + data_28_V_q0, + data_29_V_address0, + data_29_V_ce0, + data_29_V_q0, + data_30_V_address0, + data_30_V_ce0, + data_30_V_q0, + data_31_V_address0, + data_31_V_ce0, + data_31_V_q0, + data_32_V_address0, + data_32_V_ce0, + data_32_V_q0, + data_33_V_address0, + data_33_V_ce0, + data_33_V_q0, + data_34_V_address0, + data_34_V_ce0, + data_34_V_q0, + data_35_V_address0, + data_35_V_ce0, + data_35_V_q0, + data_36_V_address0, + data_36_V_ce0, + data_36_V_q0, + data_37_V_address0, + data_37_V_ce0, + data_37_V_q0, + data_38_V_address0, + data_38_V_ce0, + data_38_V_q0, + data_39_V_address0, + data_39_V_ce0, + data_39_V_q0, + data_40_V_address0, + data_40_V_ce0, + data_40_V_q0, + data_41_V_address0, + data_41_V_ce0, + data_41_V_q0, + data_42_V_address0, + data_42_V_ce0, + data_42_V_q0, + data_43_V_address0, + data_43_V_ce0, + data_43_V_q0, + data_44_V_address0, + data_44_V_ce0, + data_44_V_q0, + data_45_V_address0, + data_45_V_ce0, + data_45_V_q0, + data_46_V_address0, + data_46_V_ce0, + data_46_V_q0, + data_47_V_address0, + data_47_V_ce0, + data_47_V_q0, + data_48_V_address0, + data_48_V_ce0, + data_48_V_q0, + data_49_V_address0, + data_49_V_ce0, + data_49_V_q0, + data_50_V_address0, + data_50_V_ce0, + data_50_V_q0, + data_51_V_address0, + data_51_V_ce0, + data_51_V_q0, + data_52_V_address0, + data_52_V_ce0, + data_52_V_q0, + data_53_V_address0, + data_53_V_ce0, + data_53_V_q0, + data_54_V_address0, + data_54_V_ce0, + data_54_V_q0, + data_55_V_address0, + data_55_V_ce0, + data_55_V_q0, + data_56_V_address0, + data_56_V_ce0, + data_56_V_q0, + data_57_V_address0, + data_57_V_ce0, + data_57_V_q0, + data_58_V_address0, + data_58_V_ce0, + data_58_V_q0, + data_59_V_address0, + data_59_V_ce0, + data_59_V_q0, + data_60_V_address0, + data_60_V_ce0, + data_60_V_q0, + data_61_V_address0, + data_61_V_ce0, + data_61_V_q0, + data_62_V_address0, + data_62_V_ce0, + data_62_V_q0, + data_63_V_address0, + data_63_V_ce0, + data_63_V_q0, + data_64_V_address0, + data_64_V_ce0, + data_64_V_q0, + data_65_V_address0, + data_65_V_ce0, + data_65_V_q0, + data_66_V_address0, + data_66_V_ce0, + data_66_V_q0, + data_67_V_address0, + data_67_V_ce0, + data_67_V_q0, + data_68_V_address0, + data_68_V_ce0, + data_68_V_q0, + data_69_V_address0, + data_69_V_ce0, + data_69_V_q0, + data_70_V_address0, + data_70_V_ce0, + data_70_V_q0, + data_71_V_address0, + data_71_V_ce0, + data_71_V_q0, + data_72_V_address0, + data_72_V_ce0, + data_72_V_q0, + data_73_V_address0, + data_73_V_ce0, + data_73_V_q0, + data_74_V_address0, + data_74_V_ce0, + data_74_V_q0, + data_75_V_address0, + data_75_V_ce0, + data_75_V_q0, + data_76_V_address0, + data_76_V_ce0, + data_76_V_q0, + data_77_V_address0, + data_77_V_ce0, + data_77_V_q0, + data_78_V_address0, + data_78_V_ce0, + data_78_V_q0, + data_79_V_address0, + data_79_V_ce0, + data_79_V_q0, + data_80_V_address0, + data_80_V_ce0, + data_80_V_q0, + data_81_V_address0, + data_81_V_ce0, + data_81_V_q0, + data_82_V_address0, + data_82_V_ce0, + data_82_V_q0, + data_83_V_address0, + data_83_V_ce0, + data_83_V_q0, + data_84_V_address0, + data_84_V_ce0, + data_84_V_q0, + data_85_V_address0, + data_85_V_ce0, + data_85_V_q0, + data_86_V_address0, + data_86_V_ce0, + data_86_V_q0, + data_87_V_address0, + data_87_V_ce0, + data_87_V_q0, + data_88_V_address0, + data_88_V_ce0, + data_88_V_q0, + data_89_V_address0, + data_89_V_ce0, + data_89_V_q0, + data_90_V_address0, + data_90_V_ce0, + data_90_V_q0, + data_91_V_address0, + data_91_V_ce0, + data_91_V_q0, + data_92_V_address0, + data_92_V_ce0, + data_92_V_q0, + data_93_V_address0, + data_93_V_ce0, + data_93_V_q0, + data_94_V_address0, + data_94_V_ce0, + data_94_V_q0, + data_95_V_address0, + data_95_V_ce0, + data_95_V_q0, + data_96_V_address0, + data_96_V_ce0, + data_96_V_q0, + data_97_V_address0, + data_97_V_ce0, + data_97_V_q0, + data_98_V_address0, + data_98_V_ce0, + data_98_V_q0, + data_99_V_address0, + data_99_V_ce0, + data_99_V_q0, + data_100_V_address0, + data_100_V_ce0, + data_100_V_q0, + data_101_V_address0, + data_101_V_ce0, + data_101_V_q0, + data_102_V_address0, + data_102_V_ce0, + data_102_V_q0, + data_103_V_address0, + data_103_V_ce0, + data_103_V_q0, + data_104_V_address0, + data_104_V_ce0, + data_104_V_q0, + data_105_V_address0, + data_105_V_ce0, + data_105_V_q0, + data_106_V_address0, + data_106_V_ce0, + data_106_V_q0, + data_107_V_address0, + data_107_V_ce0, + data_107_V_q0, + data_108_V_address0, + data_108_V_ce0, + data_108_V_q0, + data_109_V_address0, + data_109_V_ce0, + data_109_V_q0, + data_110_V_address0, + data_110_V_ce0, + data_110_V_q0, + data_111_V_address0, + data_111_V_ce0, + data_111_V_q0, + data_112_V_address0, + data_112_V_ce0, + data_112_V_q0, + data_113_V_address0, + data_113_V_ce0, + data_113_V_q0, + data_114_V_address0, + data_114_V_ce0, + data_114_V_q0, + data_115_V_address0, + data_115_V_ce0, + data_115_V_q0, + data_116_V_address0, + data_116_V_ce0, + data_116_V_q0, + data_117_V_address0, + data_117_V_ce0, + data_117_V_q0, + data_118_V_address0, + data_118_V_ce0, + data_118_V_q0, + data_119_V_address0, + data_119_V_ce0, + data_119_V_q0, + data_120_V_address0, + data_120_V_ce0, + data_120_V_q0, + data_121_V_address0, + data_121_V_ce0, + data_121_V_q0, + data_122_V_address0, + data_122_V_ce0, + data_122_V_q0, + data_123_V_address0, + data_123_V_ce0, + data_123_V_q0, + data_124_V_address0, + data_124_V_ce0, + data_124_V_q0, + data_125_V_address0, + data_125_V_ce0, + data_125_V_q0, + data_126_V_address0, + data_126_V_ce0, + data_126_V_q0, + data_127_V_address0, + data_127_V_ce0, + data_127_V_q0, + mult_0_din, + mult_0_full_n, + mult_0_write, + mult_1_din, + mult_1_full_n, + mult_1_write, + mult_2_din, + mult_2_full_n, + mult_2_write, + mult_3_din, + mult_3_full_n, + mult_3_write, + mult_4_din, + mult_4_full_n, + mult_4_write, + mult_5_din, + mult_5_full_n, + mult_5_write, + mult_6_din, + mult_6_full_n, + mult_6_write, + mult_7_din, + mult_7_full_n, + mult_7_write, + mult_8_din, + mult_8_full_n, + mult_8_write, + mult_9_din, + mult_9_full_n, + mult_9_write +); + +parameter ap_ST_fsm_state1 = 3'd0; +parameter ap_ST_fsm_pp0_stage0 = 3'd1; +parameter ap_ST_fsm_pp0_stage1 = 3'd2; +parameter ap_ST_fsm_pp0_stage2 = 3'd3; +parameter ap_ST_fsm_pp0_stage3 = 3'd4; +parameter ap_ST_fsm_pp0_stage4 = 3'd5; +parameter ap_ST_fsm_state11 = 3'd6; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [2:0] data_0_V_address0; +output data_0_V_ce0; +input [7:0] data_0_V_q0; +output [2:0] data_1_V_address0; +output data_1_V_ce0; +input [7:0] data_1_V_q0; +output [2:0] data_2_V_address0; +output data_2_V_ce0; +input [7:0] data_2_V_q0; +output [2:0] data_3_V_address0; +output data_3_V_ce0; +input [7:0] data_3_V_q0; +output [2:0] data_4_V_address0; +output data_4_V_ce0; +input [7:0] data_4_V_q0; +output [2:0] data_5_V_address0; +output data_5_V_ce0; +input [7:0] data_5_V_q0; +output [2:0] data_6_V_address0; +output data_6_V_ce0; +input [7:0] data_6_V_q0; +output [2:0] data_7_V_address0; +output data_7_V_ce0; +input [7:0] data_7_V_q0; +output [2:0] data_8_V_address0; +output data_8_V_ce0; +input [7:0] data_8_V_q0; +output [2:0] data_9_V_address0; +output data_9_V_ce0; +input [7:0] data_9_V_q0; +output [2:0] data_10_V_address0; +output data_10_V_ce0; +input [7:0] data_10_V_q0; +output [2:0] data_11_V_address0; +output data_11_V_ce0; +input [7:0] data_11_V_q0; +output [2:0] data_12_V_address0; +output data_12_V_ce0; +input [7:0] data_12_V_q0; +output [2:0] data_13_V_address0; +output data_13_V_ce0; +input [7:0] data_13_V_q0; +output [2:0] data_14_V_address0; +output data_14_V_ce0; +input [7:0] data_14_V_q0; +output [2:0] data_15_V_address0; +output data_15_V_ce0; +input [7:0] data_15_V_q0; +output [2:0] data_16_V_address0; +output data_16_V_ce0; +input [7:0] data_16_V_q0; +output [2:0] data_17_V_address0; +output data_17_V_ce0; +input [7:0] data_17_V_q0; +output [2:0] data_18_V_address0; +output data_18_V_ce0; +input [7:0] data_18_V_q0; +output [2:0] data_19_V_address0; +output data_19_V_ce0; +input [7:0] data_19_V_q0; +output [2:0] data_20_V_address0; +output data_20_V_ce0; +input [7:0] data_20_V_q0; +output [2:0] data_21_V_address0; +output data_21_V_ce0; +input [7:0] data_21_V_q0; +output [2:0] data_22_V_address0; +output data_22_V_ce0; +input [7:0] data_22_V_q0; +output [2:0] data_23_V_address0; +output data_23_V_ce0; +input [7:0] data_23_V_q0; +output [2:0] data_24_V_address0; +output data_24_V_ce0; +input [7:0] data_24_V_q0; +output [2:0] data_25_V_address0; +output data_25_V_ce0; +input [7:0] data_25_V_q0; +output [2:0] data_26_V_address0; +output data_26_V_ce0; +input [7:0] data_26_V_q0; +output [2:0] data_27_V_address0; +output data_27_V_ce0; +input [7:0] data_27_V_q0; +output [2:0] data_28_V_address0; +output data_28_V_ce0; +input [7:0] data_28_V_q0; +output [2:0] data_29_V_address0; +output data_29_V_ce0; +input [7:0] data_29_V_q0; +output [2:0] data_30_V_address0; +output data_30_V_ce0; +input [7:0] data_30_V_q0; +output [2:0] data_31_V_address0; +output data_31_V_ce0; +input [7:0] data_31_V_q0; +output [2:0] data_32_V_address0; +output data_32_V_ce0; +input [7:0] data_32_V_q0; +output [2:0] data_33_V_address0; +output data_33_V_ce0; +input [7:0] data_33_V_q0; +output [2:0] data_34_V_address0; +output data_34_V_ce0; +input [7:0] data_34_V_q0; +output [2:0] data_35_V_address0; +output data_35_V_ce0; +input [7:0] data_35_V_q0; +output [2:0] data_36_V_address0; +output data_36_V_ce0; +input [7:0] data_36_V_q0; +output [2:0] data_37_V_address0; +output data_37_V_ce0; +input [7:0] data_37_V_q0; +output [2:0] data_38_V_address0; +output data_38_V_ce0; +input [7:0] data_38_V_q0; +output [2:0] data_39_V_address0; +output data_39_V_ce0; +input [7:0] data_39_V_q0; +output [2:0] data_40_V_address0; +output data_40_V_ce0; +input [7:0] data_40_V_q0; +output [2:0] data_41_V_address0; +output data_41_V_ce0; +input [7:0] data_41_V_q0; +output [2:0] data_42_V_address0; +output data_42_V_ce0; +input [7:0] data_42_V_q0; +output [2:0] data_43_V_address0; +output data_43_V_ce0; +input [7:0] data_43_V_q0; +output [2:0] data_44_V_address0; +output data_44_V_ce0; +input [7:0] data_44_V_q0; +output [2:0] data_45_V_address0; +output data_45_V_ce0; +input [7:0] data_45_V_q0; +output [2:0] data_46_V_address0; +output data_46_V_ce0; +input [7:0] data_46_V_q0; +output [2:0] data_47_V_address0; +output data_47_V_ce0; +input [7:0] data_47_V_q0; +output [2:0] data_48_V_address0; +output data_48_V_ce0; +input [7:0] data_48_V_q0; +output [2:0] data_49_V_address0; +output data_49_V_ce0; +input [7:0] data_49_V_q0; +output [2:0] data_50_V_address0; +output data_50_V_ce0; +input [7:0] data_50_V_q0; +output [2:0] data_51_V_address0; +output data_51_V_ce0; +input [7:0] data_51_V_q0; +output [2:0] data_52_V_address0; +output data_52_V_ce0; +input [7:0] data_52_V_q0; +output [2:0] data_53_V_address0; +output data_53_V_ce0; +input [7:0] data_53_V_q0; +output [2:0] data_54_V_address0; +output data_54_V_ce0; +input [7:0] data_54_V_q0; +output [2:0] data_55_V_address0; +output data_55_V_ce0; +input [7:0] data_55_V_q0; +output [2:0] data_56_V_address0; +output data_56_V_ce0; +input [7:0] data_56_V_q0; +output [2:0] data_57_V_address0; +output data_57_V_ce0; +input [7:0] data_57_V_q0; +output [2:0] data_58_V_address0; +output data_58_V_ce0; +input [7:0] data_58_V_q0; +output [2:0] data_59_V_address0; +output data_59_V_ce0; +input [7:0] data_59_V_q0; +output [2:0] data_60_V_address0; +output data_60_V_ce0; +input [7:0] data_60_V_q0; +output [2:0] data_61_V_address0; +output data_61_V_ce0; +input [7:0] data_61_V_q0; +output [2:0] data_62_V_address0; +output data_62_V_ce0; +input [7:0] data_62_V_q0; +output [2:0] data_63_V_address0; +output data_63_V_ce0; +input [7:0] data_63_V_q0; +output [2:0] data_64_V_address0; +output data_64_V_ce0; +input [7:0] data_64_V_q0; +output [2:0] data_65_V_address0; +output data_65_V_ce0; +input [7:0] data_65_V_q0; +output [2:0] data_66_V_address0; +output data_66_V_ce0; +input [7:0] data_66_V_q0; +output [2:0] data_67_V_address0; +output data_67_V_ce0; +input [7:0] data_67_V_q0; +output [2:0] data_68_V_address0; +output data_68_V_ce0; +input [7:0] data_68_V_q0; +output [2:0] data_69_V_address0; +output data_69_V_ce0; +input [7:0] data_69_V_q0; +output [2:0] data_70_V_address0; +output data_70_V_ce0; +input [7:0] data_70_V_q0; +output [2:0] data_71_V_address0; +output data_71_V_ce0; +input [7:0] data_71_V_q0; +output [2:0] data_72_V_address0; +output data_72_V_ce0; +input [7:0] data_72_V_q0; +output [2:0] data_73_V_address0; +output data_73_V_ce0; +input [7:0] data_73_V_q0; +output [2:0] data_74_V_address0; +output data_74_V_ce0; +input [7:0] data_74_V_q0; +output [2:0] data_75_V_address0; +output data_75_V_ce0; +input [7:0] data_75_V_q0; +output [1:0] data_76_V_address0; +output data_76_V_ce0; +input [7:0] data_76_V_q0; +output [1:0] data_77_V_address0; +output data_77_V_ce0; +input [7:0] data_77_V_q0; +output [1:0] data_78_V_address0; +output data_78_V_ce0; +input [7:0] data_78_V_q0; +output [1:0] data_79_V_address0; +output data_79_V_ce0; +input [7:0] data_79_V_q0; +output [1:0] data_80_V_address0; +output data_80_V_ce0; +input [7:0] data_80_V_q0; +output [1:0] data_81_V_address0; +output data_81_V_ce0; +input [7:0] data_81_V_q0; +output [1:0] data_82_V_address0; +output data_82_V_ce0; +input [7:0] data_82_V_q0; +output [1:0] data_83_V_address0; +output data_83_V_ce0; +input [7:0] data_83_V_q0; +output [1:0] data_84_V_address0; +output data_84_V_ce0; +input [7:0] data_84_V_q0; +output [1:0] data_85_V_address0; +output data_85_V_ce0; +input [7:0] data_85_V_q0; +output [1:0] data_86_V_address0; +output data_86_V_ce0; +input [7:0] data_86_V_q0; +output [1:0] data_87_V_address0; +output data_87_V_ce0; +input [7:0] data_87_V_q0; +output [1:0] data_88_V_address0; +output data_88_V_ce0; +input [7:0] data_88_V_q0; +output [1:0] data_89_V_address0; +output data_89_V_ce0; +input [7:0] data_89_V_q0; +output [1:0] data_90_V_address0; +output data_90_V_ce0; +input [7:0] data_90_V_q0; +output [1:0] data_91_V_address0; +output data_91_V_ce0; +input [7:0] data_91_V_q0; +output [1:0] data_92_V_address0; +output data_92_V_ce0; +input [7:0] data_92_V_q0; +output [1:0] data_93_V_address0; +output data_93_V_ce0; +input [7:0] data_93_V_q0; +output [1:0] data_94_V_address0; +output data_94_V_ce0; +input [7:0] data_94_V_q0; +output [1:0] data_95_V_address0; +output data_95_V_ce0; +input [7:0] data_95_V_q0; +output [1:0] data_96_V_address0; +output data_96_V_ce0; +input [7:0] data_96_V_q0; +output [1:0] data_97_V_address0; +output data_97_V_ce0; +input [7:0] data_97_V_q0; +output [1:0] data_98_V_address0; +output data_98_V_ce0; +input [7:0] data_98_V_q0; +output [1:0] data_99_V_address0; +output data_99_V_ce0; +input [7:0] data_99_V_q0; +output [1:0] data_100_V_address0; +output data_100_V_ce0; +input [7:0] data_100_V_q0; +output [1:0] data_101_V_address0; +output data_101_V_ce0; +input [7:0] data_101_V_q0; +output [1:0] data_102_V_address0; +output data_102_V_ce0; +input [7:0] data_102_V_q0; +output [1:0] data_103_V_address0; +output data_103_V_ce0; +input [7:0] data_103_V_q0; +output [1:0] data_104_V_address0; +output data_104_V_ce0; +input [7:0] data_104_V_q0; +output [1:0] data_105_V_address0; +output data_105_V_ce0; +input [7:0] data_105_V_q0; +output [1:0] data_106_V_address0; +output data_106_V_ce0; +input [7:0] data_106_V_q0; +output [1:0] data_107_V_address0; +output data_107_V_ce0; +input [7:0] data_107_V_q0; +output [1:0] data_108_V_address0; +output data_108_V_ce0; +input [7:0] data_108_V_q0; +output [1:0] data_109_V_address0; +output data_109_V_ce0; +input [7:0] data_109_V_q0; +output [1:0] data_110_V_address0; +output data_110_V_ce0; +input [7:0] data_110_V_q0; +output [1:0] data_111_V_address0; +output data_111_V_ce0; +input [7:0] data_111_V_q0; +output [1:0] data_112_V_address0; +output data_112_V_ce0; +input [7:0] data_112_V_q0; +output [1:0] data_113_V_address0; +output data_113_V_ce0; +input [7:0] data_113_V_q0; +output [1:0] data_114_V_address0; +output data_114_V_ce0; +input [7:0] data_114_V_q0; +output [1:0] data_115_V_address0; +output data_115_V_ce0; +input [7:0] data_115_V_q0; +output [1:0] data_116_V_address0; +output data_116_V_ce0; +input [7:0] data_116_V_q0; +output [1:0] data_117_V_address0; +output data_117_V_ce0; +input [7:0] data_117_V_q0; +output [1:0] data_118_V_address0; +output data_118_V_ce0; +input [7:0] data_118_V_q0; +output [1:0] data_119_V_address0; +output data_119_V_ce0; +input [7:0] data_119_V_q0; +output [1:0] data_120_V_address0; +output data_120_V_ce0; +input [7:0] data_120_V_q0; +output [1:0] data_121_V_address0; +output data_121_V_ce0; +input [7:0] data_121_V_q0; +output [1:0] data_122_V_address0; +output data_122_V_ce0; +input [7:0] data_122_V_q0; +output [1:0] data_123_V_address0; +output data_123_V_ce0; +input [7:0] data_123_V_q0; +output [1:0] data_124_V_address0; +output data_124_V_ce0; +input [7:0] data_124_V_q0; +output [1:0] data_125_V_address0; +output data_125_V_ce0; +input [7:0] data_125_V_q0; +output [1:0] data_126_V_address0; +output data_126_V_ce0; +input [7:0] data_126_V_q0; +output [1:0] data_127_V_address0; +output data_127_V_ce0; +input [7:0] data_127_V_q0; +output [6:0] mult_0_din; +input mult_0_full_n; +output mult_0_write; +output [6:0] mult_1_din; +input mult_1_full_n; +output mult_1_write; +output [6:0] mult_2_din; +input mult_2_full_n; +output mult_2_write; +output [6:0] mult_3_din; +input mult_3_full_n; +output mult_3_write; +output [6:0] mult_4_din; +input mult_4_full_n; +output mult_4_write; +output [6:0] mult_5_din; +input mult_5_full_n; +output mult_5_write; +output [6:0] mult_6_din; +input mult_6_full_n; +output mult_6_write; +output [6:0] mult_7_din; +input mult_7_full_n; +output mult_7_write; +output [6:0] mult_8_din; +input mult_8_full_n; +output mult_8_write; +output [6:0] mult_9_din; +input mult_9_full_n; +output mult_9_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg data_0_V_ce0; +reg data_1_V_ce0; +reg data_2_V_ce0; +reg data_3_V_ce0; +reg data_4_V_ce0; +reg data_5_V_ce0; +reg data_6_V_ce0; +reg data_7_V_ce0; +reg data_8_V_ce0; +reg data_9_V_ce0; +reg data_10_V_ce0; +reg data_11_V_ce0; +reg data_12_V_ce0; +reg data_13_V_ce0; +reg data_14_V_ce0; +reg data_15_V_ce0; +reg data_16_V_ce0; +reg data_17_V_ce0; +reg data_18_V_ce0; +reg data_19_V_ce0; +reg data_20_V_ce0; +reg data_21_V_ce0; +reg data_22_V_ce0; +reg data_23_V_ce0; +reg data_24_V_ce0; +reg data_25_V_ce0; +reg data_26_V_ce0; +reg data_27_V_ce0; +reg data_28_V_ce0; +reg data_29_V_ce0; +reg data_30_V_ce0; +reg data_31_V_ce0; +reg data_32_V_ce0; +reg data_33_V_ce0; +reg data_34_V_ce0; +reg data_35_V_ce0; +reg data_36_V_ce0; +reg data_37_V_ce0; +reg data_38_V_ce0; +reg data_39_V_ce0; +reg data_40_V_ce0; +reg data_41_V_ce0; +reg data_42_V_ce0; +reg data_43_V_ce0; +reg data_44_V_ce0; +reg data_45_V_ce0; +reg data_46_V_ce0; +reg data_47_V_ce0; +reg data_48_V_ce0; +reg data_49_V_ce0; +reg data_50_V_ce0; +reg data_51_V_ce0; +reg data_52_V_ce0; +reg data_53_V_ce0; +reg data_54_V_ce0; +reg data_55_V_ce0; +reg data_56_V_ce0; +reg data_57_V_ce0; +reg data_58_V_ce0; +reg data_59_V_ce0; +reg data_60_V_ce0; +reg data_61_V_ce0; +reg data_62_V_ce0; +reg data_63_V_ce0; +reg data_64_V_ce0; +reg data_65_V_ce0; +reg data_66_V_ce0; +reg data_67_V_ce0; +reg data_68_V_ce0; +reg data_69_V_ce0; +reg data_70_V_ce0; +reg data_71_V_ce0; +reg data_72_V_ce0; +reg data_73_V_ce0; +reg data_74_V_ce0; +reg data_75_V_ce0; +reg data_76_V_ce0; +reg data_77_V_ce0; +reg data_78_V_ce0; +reg data_79_V_ce0; +reg data_80_V_ce0; +reg data_81_V_ce0; +reg data_82_V_ce0; +reg data_83_V_ce0; +reg data_84_V_ce0; +reg data_85_V_ce0; +reg data_86_V_ce0; +reg data_87_V_ce0; +reg data_88_V_ce0; +reg data_89_V_ce0; +reg data_90_V_ce0; +reg data_91_V_ce0; +reg data_92_V_ce0; +reg data_93_V_ce0; +reg data_94_V_ce0; +reg data_95_V_ce0; +reg data_96_V_ce0; +reg data_97_V_ce0; +reg data_98_V_ce0; +reg data_99_V_ce0; +reg data_100_V_ce0; +reg data_101_V_ce0; +reg data_102_V_ce0; +reg data_103_V_ce0; +reg data_104_V_ce0; +reg data_105_V_ce0; +reg data_106_V_ce0; +reg data_107_V_ce0; +reg data_108_V_ce0; +reg data_109_V_ce0; +reg data_110_V_ce0; +reg data_111_V_ce0; +reg data_112_V_ce0; +reg data_113_V_ce0; +reg data_114_V_ce0; +reg data_115_V_ce0; +reg data_116_V_ce0; +reg data_117_V_ce0; +reg data_118_V_ce0; +reg data_119_V_ce0; +reg data_120_V_ce0; +reg data_121_V_ce0; +reg data_122_V_ce0; +reg data_123_V_ce0; +reg data_124_V_ce0; +reg data_125_V_ce0; +reg data_126_V_ce0; +reg data_127_V_ce0; +reg mult_0_write; +reg mult_1_write; +reg mult_2_write; +reg mult_3_write; +reg mult_4_write; +reg mult_5_write; +reg mult_6_write; +reg mult_7_write; +reg mult_8_write; +reg mult_9_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +reg internal_ap_ready; +wire [9:0] w9_V_0_address0; +reg w9_V_0_ce0; +wire [2:0] w9_V_0_q0; +wire [9:0] w9_V_1_address0; +reg w9_V_1_ce0; +wire [2:0] w9_V_1_q0; +wire [9:0] w9_V_2_address0; +reg w9_V_2_ce0; +wire [2:0] w9_V_2_q0; +wire [9:0] w9_V_3_address0; +reg w9_V_3_ce0; +wire [2:0] w9_V_3_q0; +wire [9:0] w9_V_4_address0; +reg w9_V_4_ce0; +wire [2:0] w9_V_4_q0; +wire [9:0] w9_V_5_address0; +reg w9_V_5_ce0; +wire [2:0] w9_V_5_q0; +wire [9:0] w9_V_6_address0; +reg w9_V_6_ce0; +wire [2:0] w9_V_6_q0; +wire [9:0] w9_V_7_address0; +reg w9_V_7_ce0; +wire [2:0] w9_V_7_q0; +wire [9:0] w9_V_8_address0; +reg w9_V_8_ce0; +wire [2:0] w9_V_8_q0; +wire [9:0] w9_V_9_address0; +reg w9_V_9_ce0; +wire [2:0] w9_V_9_q0; +reg mult_0_blk_n; +reg ap_enable_reg_pp0_iter1; +wire ap_block_pp0_stage3; +reg [0:0] icmp_ln85_reg_3035; +reg [0:0] icmp_ln85_reg_3035_pp0_iter1_reg; +reg mult_1_blk_n; +reg mult_2_blk_n; +reg mult_3_blk_n; +reg mult_4_blk_n; +reg mult_5_blk_n; +reg mult_6_blk_n; +reg mult_7_blk_n; +reg mult_8_blk_n; +reg mult_9_blk_n; +reg [9:0] ii_0_i_reg_2476; +wire [0:0] icmp_ln85_fu_2819_p2; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state7_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +wire [9:0] ii_fu_2825_p2; +reg [9:0] ii_reg_3039; +reg ap_enable_reg_pp0_iter0; +wire [6:0] trunc_ln203_fu_2973_p1; +reg [6:0] trunc_ln203_reg_3684; +wire [63:0] zext_ln96_fu_2977_p1; +reg [63:0] zext_ln96_reg_3688; +reg [7:0] data_126_V_load_reg_3734; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state8_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +reg [7:0] data_125_V_load_reg_3739; +reg [7:0] data_124_V_load_reg_3744; +reg [7:0] data_123_V_load_reg_3749; +reg [7:0] data_122_V_load_reg_3754; +reg [7:0] data_121_V_load_reg_3759; +reg [7:0] data_120_V_load_reg_3764; +reg [7:0] data_119_V_load_reg_3769; +reg [7:0] data_118_V_load_reg_3774; +reg [7:0] data_117_V_load_reg_3779; +reg [7:0] data_116_V_load_reg_3784; +reg [7:0] data_115_V_load_reg_3789; +reg [7:0] data_114_V_load_reg_3794; +reg [7:0] data_113_V_load_reg_3799; +reg [7:0] data_112_V_load_reg_3804; +reg [7:0] data_111_V_load_reg_3809; +reg [7:0] data_110_V_load_reg_3814; +reg [7:0] data_109_V_load_reg_3819; +reg [7:0] data_108_V_load_reg_3824; +reg [7:0] data_107_V_load_reg_3829; +reg [7:0] data_106_V_load_reg_3834; +reg [7:0] data_105_V_load_reg_3839; +reg [7:0] data_104_V_load_reg_3844; +reg [7:0] data_103_V_load_reg_3849; +reg [7:0] data_102_V_load_reg_3854; +reg [7:0] data_101_V_load_reg_3859; +reg [7:0] data_100_V_load_reg_3864; +reg [7:0] data_99_V_load_reg_3869; +reg [7:0] data_98_V_load_reg_3874; +reg [7:0] data_97_V_load_reg_3879; +reg [7:0] data_96_V_load_reg_3884; +reg [7:0] data_95_V_load_reg_3889; +reg [7:0] data_94_V_load_reg_3894; +reg [7:0] data_93_V_load_reg_3899; +reg [7:0] data_92_V_load_reg_3904; +reg [7:0] data_91_V_load_reg_3909; +reg [7:0] data_90_V_load_reg_3914; +reg [7:0] data_89_V_load_reg_3919; +reg [7:0] data_88_V_load_reg_3924; +reg [7:0] data_87_V_load_reg_3929; +reg [7:0] data_86_V_load_reg_3934; +reg [7:0] data_85_V_load_reg_3939; +reg [7:0] data_84_V_load_reg_3944; +reg [7:0] data_83_V_load_reg_3949; +reg [7:0] data_82_V_load_reg_3954; +reg [7:0] data_81_V_load_reg_3959; +reg [7:0] data_80_V_load_reg_3964; +reg [7:0] data_79_V_load_reg_3969; +reg [7:0] data_78_V_load_reg_3974; +reg [7:0] data_77_V_load_reg_3979; +reg [7:0] data_76_V_load_reg_3984; +reg [7:0] data_75_V_load_reg_3989; +reg [7:0] data_74_V_load_reg_3994; +reg [7:0] data_73_V_load_reg_3999; +reg [7:0] data_72_V_load_reg_4004; +reg [7:0] data_71_V_load_reg_4009; +reg [7:0] data_70_V_load_reg_4014; +reg [7:0] data_69_V_load_reg_4019; +reg [7:0] data_68_V_load_reg_4024; +reg [7:0] data_67_V_load_reg_4029; +reg [7:0] data_66_V_load_reg_4034; +reg [7:0] data_65_V_load_reg_4039; +reg [7:0] data_64_V_load_reg_4044; +reg [7:0] data_63_V_load_reg_4049; +reg [7:0] data_62_V_load_reg_4054; +reg [7:0] data_61_V_load_reg_4059; +reg [7:0] data_60_V_load_reg_4064; +reg [7:0] data_59_V_load_reg_4069; +reg [7:0] data_58_V_load_reg_4074; +reg [7:0] data_57_V_load_reg_4079; +reg [7:0] data_56_V_load_reg_4084; +reg [7:0] data_55_V_load_reg_4089; +reg [7:0] data_54_V_load_reg_4094; +reg [7:0] data_53_V_load_reg_4099; +reg [7:0] data_52_V_load_reg_4104; +reg [7:0] data_51_V_load_reg_4109; +reg [7:0] data_50_V_load_reg_4114; +reg [7:0] data_49_V_load_reg_4119; +reg [7:0] data_48_V_load_reg_4124; +reg [7:0] data_47_V_load_reg_4129; +reg [7:0] data_46_V_load_reg_4134; +reg [7:0] data_45_V_load_reg_4139; +reg [7:0] data_44_V_load_reg_4144; +reg [7:0] data_43_V_load_reg_4149; +reg [7:0] data_42_V_load_reg_4154; +reg [7:0] data_41_V_load_reg_4159; +reg [7:0] data_40_V_load_reg_4164; +reg [7:0] data_39_V_load_reg_4169; +reg [7:0] data_38_V_load_reg_4174; +reg [7:0] data_37_V_load_reg_4179; +reg [7:0] data_36_V_load_reg_4184; +reg [7:0] data_35_V_load_reg_4189; +reg [7:0] data_34_V_load_reg_4194; +reg [7:0] data_33_V_load_reg_4199; +reg [7:0] data_32_V_load_reg_4204; +reg [7:0] data_31_V_load_reg_4209; +reg [7:0] data_30_V_load_reg_4214; +reg [7:0] data_29_V_load_reg_4219; +reg [7:0] data_28_V_load_reg_4224; +reg [7:0] data_27_V_load_reg_4229; +reg [7:0] data_26_V_load_reg_4234; +reg [7:0] data_25_V_load_reg_4239; +reg [7:0] data_24_V_load_reg_4244; +reg [7:0] data_23_V_load_reg_4249; +reg [7:0] data_22_V_load_reg_4254; +reg [7:0] data_21_V_load_reg_4259; +reg [7:0] data_20_V_load_reg_4264; +reg [7:0] data_19_V_load_reg_4269; +reg [7:0] data_18_V_load_reg_4274; +reg [7:0] data_17_V_load_reg_4279; +reg [7:0] data_16_V_load_reg_4284; +reg [7:0] data_15_V_load_reg_4289; +reg [7:0] data_14_V_load_reg_4294; +reg [7:0] data_13_V_load_reg_4299; +reg [7:0] data_12_V_load_reg_4304; +reg [7:0] data_11_V_load_reg_4309; +reg [7:0] data_10_V_load_reg_4314; +reg [7:0] data_9_V_load_reg_4319; +reg [7:0] data_8_V_load_reg_4324; +reg [7:0] data_7_V_load_reg_4329; +reg [7:0] data_6_V_load_reg_4334; +reg [7:0] data_5_V_load_reg_4339; +reg [7:0] data_4_V_load_reg_4344; +reg [7:0] data_3_V_load_reg_4349; +reg [7:0] data_2_V_load_reg_4354; +reg [7:0] data_1_V_load_reg_4359; +reg [7:0] data_0_V_load_reg_4364; +reg [7:0] data_127_V_load_reg_4369; +reg [2:0] w9_V_0_load_reg_4374; +reg [2:0] w9_V_1_load_reg_4379; +reg [2:0] w9_V_2_load_reg_4384; +reg [2:0] w9_V_3_load_reg_4389; +reg [2:0] w9_V_4_load_reg_4394; +reg [2:0] w9_V_5_load_reg_4399; +reg [2:0] w9_V_6_load_reg_4404; +reg [2:0] w9_V_7_load_reg_4409; +wire [10:0] sext_ln203_fu_2989_p1; +reg [10:0] sext_ln203_reg_4414; +wire ap_block_state5_pp0_stage3_iter0; +reg ap_block_state10_pp0_stage3_iter1; +reg ap_block_pp0_stage3_11001; +reg [6:0] trunc_ln4_reg_4420; +reg [6:0] trunc_ln708_1_reg_4425; +reg [6:0] trunc_ln708_2_reg_4430; +wire ap_block_state6_pp0_stage4_iter0; +wire ap_block_pp0_stage4_11001; +reg [6:0] trunc_ln708_3_reg_4435; +reg [6:0] trunc_ln708_4_reg_4440; +reg [6:0] trunc_ln708_5_reg_4445; +reg [6:0] trunc_ln708_6_reg_4460; +reg [6:0] trunc_ln708_7_reg_4465; +reg [2:0] w9_V_8_load_reg_4470; +reg [2:0] w9_V_9_load_reg_4475; +reg [6:0] trunc_ln708_8_reg_4480; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state9_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [6:0] trunc_ln708_9_reg_4485; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +wire ap_block_pp0_stage4_subdone; +reg ap_block_pp0_stage3_subdone; +reg [9:0] ap_phi_mux_ii_0_i_phi_fu_2480_p4; +wire ap_block_pp0_stage0; +reg [7:0] ap_phi_reg_pp0_iter0_cache_V_reg_2487; +wire [63:0] zext_ln203_fu_2841_p1; +reg ap_block_pp0_stage3_01001; +reg [2:0] grp_fu_2748_p0; +wire [10:0] sext_ln1118_fu_2995_p1; +wire [10:0] sext_ln1118_2_fu_3003_p1; +wire [10:0] sext_ln1118_4_fu_3011_p1; +wire [10:0] sext_ln1118_6_fu_3019_p1; +wire [10:0] sext_ln1118_8_fu_3027_p1; +reg [7:0] grp_fu_2748_p1; +wire ap_block_pp0_stage4; +wire ap_block_pp0_stage1; +wire ap_block_pp0_stage2; +reg [2:0] grp_fu_2749_p0; +wire [10:0] sext_ln1118_1_fu_2999_p1; +wire [10:0] sext_ln1118_3_fu_3007_p1; +wire [10:0] sext_ln1118_5_fu_3015_p1; +wire [10:0] sext_ln1118_7_fu_3023_p1; +wire [10:0] sext_ln1118_9_fu_3031_p1; +reg [7:0] grp_fu_2749_p1; +wire [10:0] grp_fu_2748_p2; +wire [10:0] grp_fu_2749_p2; +wire [2:0] lshr_ln_fu_2831_p4; +reg [2:0] ap_NS_fsm; +wire ap_block_pp0_stage1_subdone; +wire ap_block_pp0_stage2_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_2286; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +end + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bFp #( + .DataWidth( 3 ), + .AddressRange( 588 ), + .AddressWidth( 10 )) +w9_V_0_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(w9_V_0_address0), + .ce0(w9_V_0_ce0), + .q0(w9_V_0_q0) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bGp #( + .DataWidth( 3 ), + .AddressRange( 588 ), + .AddressWidth( 10 )) +w9_V_1_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(w9_V_1_address0), + .ce0(w9_V_1_ce0), + .q0(w9_V_1_q0) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bHp #( + .DataWidth( 3 ), + .AddressRange( 588 ), + .AddressWidth( 10 )) +w9_V_2_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(w9_V_2_address0), + .ce0(w9_V_2_ce0), + .q0(w9_V_2_q0) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bIp #( + .DataWidth( 3 ), + .AddressRange( 588 ), + .AddressWidth( 10 )) +w9_V_3_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(w9_V_3_address0), + .ce0(w9_V_3_ce0), + .q0(w9_V_3_q0) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bJp #( + .DataWidth( 3 ), + .AddressRange( 588 ), + .AddressWidth( 10 )) +w9_V_4_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(w9_V_4_address0), + .ce0(w9_V_4_ce0), + .q0(w9_V_4_q0) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bKp #( + .DataWidth( 3 ), + .AddressRange( 588 ), + .AddressWidth( 10 )) +w9_V_5_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(w9_V_5_address0), + .ce0(w9_V_5_ce0), + .q0(w9_V_5_q0) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bLp #( + .DataWidth( 3 ), + .AddressRange( 588 ), + .AddressWidth( 10 )) +w9_V_6_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(w9_V_6_address0), + .ce0(w9_V_6_ce0), + .q0(w9_V_6_q0) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bMq #( + .DataWidth( 3 ), + .AddressRange( 588 ), + .AddressWidth( 10 )) +w9_V_7_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(w9_V_7_address0), + .ce0(w9_V_7_ce0), + .q0(w9_V_7_q0) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bNq #( + .DataWidth( 3 ), + .AddressRange( 588 ), + .AddressWidth( 10 )) +w9_V_8_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(w9_V_8_address0), + .ce0(w9_V_8_ce0), + .q0(w9_V_8_q0) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bOq #( + .DataWidth( 3 ), + .AddressRange( 588 ), + .AddressWidth( 10 )) +w9_V_9_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(w9_V_9_address0), + .ce0(w9_V_9_ce0), + .q0(w9_V_9_q0) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((((ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage3_subdone)) | ((ap_ST_fsm_pp0_stage4 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage4_subdone)))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((internal_ap_ready == 1'b0) & (real_start == 1'b1))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_condition_2286)) begin + if ((trunc_ln203_reg_3684 == 7'd127)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_127_V_load_reg_4369; + end else if ((trunc_ln203_reg_3684 == 7'd126)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_126_V_load_reg_3734; + end else if ((trunc_ln203_reg_3684 == 7'd125)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_125_V_load_reg_3739; + end else if ((trunc_ln203_reg_3684 == 7'd124)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_124_V_load_reg_3744; + end else if ((trunc_ln203_reg_3684 == 7'd123)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_123_V_load_reg_3749; + end else if ((trunc_ln203_reg_3684 == 7'd122)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_122_V_load_reg_3754; + end else if ((trunc_ln203_reg_3684 == 7'd121)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_121_V_load_reg_3759; + end else if ((trunc_ln203_reg_3684 == 7'd120)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_120_V_load_reg_3764; + end else if ((trunc_ln203_reg_3684 == 7'd119)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_119_V_load_reg_3769; + end else if ((trunc_ln203_reg_3684 == 7'd118)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_118_V_load_reg_3774; + end else if ((trunc_ln203_reg_3684 == 7'd117)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_117_V_load_reg_3779; + end else if ((trunc_ln203_reg_3684 == 7'd116)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_116_V_load_reg_3784; + end else if ((trunc_ln203_reg_3684 == 7'd115)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_115_V_load_reg_3789; + end else if ((trunc_ln203_reg_3684 == 7'd114)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_114_V_load_reg_3794; + end else if ((trunc_ln203_reg_3684 == 7'd113)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_113_V_load_reg_3799; + end else if ((trunc_ln203_reg_3684 == 7'd112)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_112_V_load_reg_3804; + end else if ((trunc_ln203_reg_3684 == 7'd111)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_111_V_load_reg_3809; + end else if ((trunc_ln203_reg_3684 == 7'd110)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_110_V_load_reg_3814; + end else if ((trunc_ln203_reg_3684 == 7'd109)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_109_V_load_reg_3819; + end else if ((trunc_ln203_reg_3684 == 7'd108)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_108_V_load_reg_3824; + end else if ((trunc_ln203_reg_3684 == 7'd107)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_107_V_load_reg_3829; + end else if ((trunc_ln203_reg_3684 == 7'd106)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_106_V_load_reg_3834; + end else if ((trunc_ln203_reg_3684 == 7'd105)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_105_V_load_reg_3839; + end else if ((trunc_ln203_reg_3684 == 7'd104)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_104_V_load_reg_3844; + end else if ((trunc_ln203_reg_3684 == 7'd103)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_103_V_load_reg_3849; + end else if ((trunc_ln203_reg_3684 == 7'd102)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_102_V_load_reg_3854; + end else if ((trunc_ln203_reg_3684 == 7'd101)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_101_V_load_reg_3859; + end else if ((trunc_ln203_reg_3684 == 7'd100)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_100_V_load_reg_3864; + end else if ((trunc_ln203_reg_3684 == 7'd99)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_99_V_load_reg_3869; + end else if ((trunc_ln203_reg_3684 == 7'd98)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_98_V_load_reg_3874; + end else if ((trunc_ln203_reg_3684 == 7'd97)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_97_V_load_reg_3879; + end else if ((trunc_ln203_reg_3684 == 7'd96)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_96_V_load_reg_3884; + end else if ((trunc_ln203_reg_3684 == 7'd95)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_95_V_load_reg_3889; + end else if ((trunc_ln203_reg_3684 == 7'd94)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_94_V_load_reg_3894; + end else if ((trunc_ln203_reg_3684 == 7'd93)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_93_V_load_reg_3899; + end else if ((trunc_ln203_reg_3684 == 7'd92)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_92_V_load_reg_3904; + end else if ((trunc_ln203_reg_3684 == 7'd91)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_91_V_load_reg_3909; + end else if ((trunc_ln203_reg_3684 == 7'd90)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_90_V_load_reg_3914; + end else if ((trunc_ln203_reg_3684 == 7'd89)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_89_V_load_reg_3919; + end else if ((trunc_ln203_reg_3684 == 7'd88)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_88_V_load_reg_3924; + end else if ((trunc_ln203_reg_3684 == 7'd87)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_87_V_load_reg_3929; + end else if ((trunc_ln203_reg_3684 == 7'd86)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_86_V_load_reg_3934; + end else if ((trunc_ln203_reg_3684 == 7'd85)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_85_V_load_reg_3939; + end else if ((trunc_ln203_reg_3684 == 7'd84)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_84_V_load_reg_3944; + end else if ((trunc_ln203_reg_3684 == 7'd83)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_83_V_load_reg_3949; + end else if ((trunc_ln203_reg_3684 == 7'd82)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_82_V_load_reg_3954; + end else if ((trunc_ln203_reg_3684 == 7'd81)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_81_V_load_reg_3959; + end else if ((trunc_ln203_reg_3684 == 7'd80)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_80_V_load_reg_3964; + end else if ((trunc_ln203_reg_3684 == 7'd79)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_79_V_load_reg_3969; + end else if ((trunc_ln203_reg_3684 == 7'd78)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_78_V_load_reg_3974; + end else if ((trunc_ln203_reg_3684 == 7'd77)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_77_V_load_reg_3979; + end else if ((trunc_ln203_reg_3684 == 7'd76)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_76_V_load_reg_3984; + end else if ((trunc_ln203_reg_3684 == 7'd75)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_75_V_load_reg_3989; + end else if ((trunc_ln203_reg_3684 == 7'd74)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_74_V_load_reg_3994; + end else if ((trunc_ln203_reg_3684 == 7'd73)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_73_V_load_reg_3999; + end else if ((trunc_ln203_reg_3684 == 7'd72)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_72_V_load_reg_4004; + end else if ((trunc_ln203_reg_3684 == 7'd71)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_71_V_load_reg_4009; + end else if ((trunc_ln203_reg_3684 == 7'd70)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_70_V_load_reg_4014; + end else if ((trunc_ln203_reg_3684 == 7'd69)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_69_V_load_reg_4019; + end else if ((trunc_ln203_reg_3684 == 7'd68)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_68_V_load_reg_4024; + end else if ((trunc_ln203_reg_3684 == 7'd67)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_67_V_load_reg_4029; + end else if ((trunc_ln203_reg_3684 == 7'd66)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_66_V_load_reg_4034; + end else if ((trunc_ln203_reg_3684 == 7'd65)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_65_V_load_reg_4039; + end else if ((trunc_ln203_reg_3684 == 7'd64)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_64_V_load_reg_4044; + end else if ((trunc_ln203_reg_3684 == 7'd63)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_63_V_load_reg_4049; + end else if ((trunc_ln203_reg_3684 == 7'd62)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_62_V_load_reg_4054; + end else if ((trunc_ln203_reg_3684 == 7'd61)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_61_V_load_reg_4059; + end else if ((trunc_ln203_reg_3684 == 7'd60)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_60_V_load_reg_4064; + end else if ((trunc_ln203_reg_3684 == 7'd59)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_59_V_load_reg_4069; + end else if ((trunc_ln203_reg_3684 == 7'd58)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_58_V_load_reg_4074; + end else if ((trunc_ln203_reg_3684 == 7'd57)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_57_V_load_reg_4079; + end else if ((trunc_ln203_reg_3684 == 7'd56)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_56_V_load_reg_4084; + end else if ((trunc_ln203_reg_3684 == 7'd55)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_55_V_load_reg_4089; + end else if ((trunc_ln203_reg_3684 == 7'd54)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_54_V_load_reg_4094; + end else if ((trunc_ln203_reg_3684 == 7'd53)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_53_V_load_reg_4099; + end else if ((trunc_ln203_reg_3684 == 7'd52)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_52_V_load_reg_4104; + end else if ((trunc_ln203_reg_3684 == 7'd51)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_51_V_load_reg_4109; + end else if ((trunc_ln203_reg_3684 == 7'd50)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_50_V_load_reg_4114; + end else if ((trunc_ln203_reg_3684 == 7'd49)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_49_V_load_reg_4119; + end else if ((trunc_ln203_reg_3684 == 7'd48)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_48_V_load_reg_4124; + end else if ((trunc_ln203_reg_3684 == 7'd47)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_47_V_load_reg_4129; + end else if ((trunc_ln203_reg_3684 == 7'd46)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_46_V_load_reg_4134; + end else if ((trunc_ln203_reg_3684 == 7'd45)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_45_V_load_reg_4139; + end else if ((trunc_ln203_reg_3684 == 7'd44)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_44_V_load_reg_4144; + end else if ((trunc_ln203_reg_3684 == 7'd43)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_43_V_load_reg_4149; + end else if ((trunc_ln203_reg_3684 == 7'd42)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_42_V_load_reg_4154; + end else if ((trunc_ln203_reg_3684 == 7'd41)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_41_V_load_reg_4159; + end else if ((trunc_ln203_reg_3684 == 7'd40)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_40_V_load_reg_4164; + end else if ((trunc_ln203_reg_3684 == 7'd39)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_39_V_load_reg_4169; + end else if ((trunc_ln203_reg_3684 == 7'd38)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_38_V_load_reg_4174; + end else if ((trunc_ln203_reg_3684 == 7'd37)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_37_V_load_reg_4179; + end else if ((trunc_ln203_reg_3684 == 7'd36)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_36_V_load_reg_4184; + end else if ((trunc_ln203_reg_3684 == 7'd35)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_35_V_load_reg_4189; + end else if ((trunc_ln203_reg_3684 == 7'd34)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_34_V_load_reg_4194; + end else if ((trunc_ln203_reg_3684 == 7'd33)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_33_V_load_reg_4199; + end else if ((trunc_ln203_reg_3684 == 7'd32)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_32_V_load_reg_4204; + end else if ((trunc_ln203_reg_3684 == 7'd31)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_31_V_load_reg_4209; + end else if ((trunc_ln203_reg_3684 == 7'd30)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_30_V_load_reg_4214; + end else if ((trunc_ln203_reg_3684 == 7'd29)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_29_V_load_reg_4219; + end else if ((trunc_ln203_reg_3684 == 7'd28)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_28_V_load_reg_4224; + end else if ((trunc_ln203_reg_3684 == 7'd27)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_27_V_load_reg_4229; + end else if ((trunc_ln203_reg_3684 == 7'd26)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_26_V_load_reg_4234; + end else if ((trunc_ln203_reg_3684 == 7'd25)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_25_V_load_reg_4239; + end else if ((trunc_ln203_reg_3684 == 7'd24)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_24_V_load_reg_4244; + end else if ((trunc_ln203_reg_3684 == 7'd23)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_23_V_load_reg_4249; + end else if ((trunc_ln203_reg_3684 == 7'd22)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_22_V_load_reg_4254; + end else if ((trunc_ln203_reg_3684 == 7'd21)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_21_V_load_reg_4259; + end else if ((trunc_ln203_reg_3684 == 7'd20)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_20_V_load_reg_4264; + end else if ((trunc_ln203_reg_3684 == 7'd19)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_19_V_load_reg_4269; + end else if ((trunc_ln203_reg_3684 == 7'd18)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_18_V_load_reg_4274; + end else if ((trunc_ln203_reg_3684 == 7'd17)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_17_V_load_reg_4279; + end else if ((trunc_ln203_reg_3684 == 7'd16)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_16_V_load_reg_4284; + end else if ((trunc_ln203_reg_3684 == 7'd15)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_15_V_load_reg_4289; + end else if ((trunc_ln203_reg_3684 == 7'd14)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_14_V_load_reg_4294; + end else if ((trunc_ln203_reg_3684 == 7'd13)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_13_V_load_reg_4299; + end else if ((trunc_ln203_reg_3684 == 7'd12)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_12_V_load_reg_4304; + end else if ((trunc_ln203_reg_3684 == 7'd11)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_11_V_load_reg_4309; + end else if ((trunc_ln203_reg_3684 == 7'd10)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_10_V_load_reg_4314; + end else if ((trunc_ln203_reg_3684 == 7'd9)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_9_V_load_reg_4319; + end else if ((trunc_ln203_reg_3684 == 7'd8)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_8_V_load_reg_4324; + end else if ((trunc_ln203_reg_3684 == 7'd7)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_7_V_load_reg_4329; + end else if ((trunc_ln203_reg_3684 == 7'd6)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_6_V_load_reg_4334; + end else if ((trunc_ln203_reg_3684 == 7'd5)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_5_V_load_reg_4339; + end else if ((trunc_ln203_reg_3684 == 7'd4)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_4_V_load_reg_4344; + end else if ((trunc_ln203_reg_3684 == 7'd3)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_3_V_load_reg_4349; + end else if ((trunc_ln203_reg_3684 == 7'd2)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_2_V_load_reg_4354; + end else if ((trunc_ln203_reg_3684 == 7'd1)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_1_V_load_reg_4359; + end else if ((trunc_ln203_reg_3684 == 7'd0)) begin + ap_phi_reg_pp0_iter0_cache_V_reg_2487 <= data_0_V_load_reg_4364; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ii_0_i_reg_2476 <= ii_reg_3039; + end else if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ii_0_i_reg_2476 <= 10'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd0))) begin + data_0_V_load_reg_4364 <= data_0_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd100))) begin + data_100_V_load_reg_3864 <= data_100_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd101))) begin + data_101_V_load_reg_3859 <= data_101_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd102))) begin + data_102_V_load_reg_3854 <= data_102_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd103))) begin + data_103_V_load_reg_3849 <= data_103_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd104))) begin + data_104_V_load_reg_3844 <= data_104_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd105))) begin + data_105_V_load_reg_3839 <= data_105_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd106))) begin + data_106_V_load_reg_3834 <= data_106_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd107))) begin + data_107_V_load_reg_3829 <= data_107_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd108))) begin + data_108_V_load_reg_3824 <= data_108_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd109))) begin + data_109_V_load_reg_3819 <= data_109_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd10))) begin + data_10_V_load_reg_4314 <= data_10_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd110))) begin + data_110_V_load_reg_3814 <= data_110_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd111))) begin + data_111_V_load_reg_3809 <= data_111_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd112))) begin + data_112_V_load_reg_3804 <= data_112_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd113))) begin + data_113_V_load_reg_3799 <= data_113_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd114))) begin + data_114_V_load_reg_3794 <= data_114_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd115))) begin + data_115_V_load_reg_3789 <= data_115_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd116))) begin + data_116_V_load_reg_3784 <= data_116_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd117))) begin + data_117_V_load_reg_3779 <= data_117_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd118))) begin + data_118_V_load_reg_3774 <= data_118_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd119))) begin + data_119_V_load_reg_3769 <= data_119_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd11))) begin + data_11_V_load_reg_4309 <= data_11_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd120))) begin + data_120_V_load_reg_3764 <= data_120_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd121))) begin + data_121_V_load_reg_3759 <= data_121_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd122))) begin + data_122_V_load_reg_3754 <= data_122_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd123))) begin + data_123_V_load_reg_3749 <= data_123_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd124))) begin + data_124_V_load_reg_3744 <= data_124_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd125))) begin + data_125_V_load_reg_3739 <= data_125_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd126))) begin + data_126_V_load_reg_3734 <= data_126_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd127))) begin + data_127_V_load_reg_4369 <= data_127_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd12))) begin + data_12_V_load_reg_4304 <= data_12_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd13))) begin + data_13_V_load_reg_4299 <= data_13_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd14))) begin + data_14_V_load_reg_4294 <= data_14_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd15))) begin + data_15_V_load_reg_4289 <= data_15_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd16))) begin + data_16_V_load_reg_4284 <= data_16_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd17))) begin + data_17_V_load_reg_4279 <= data_17_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd18))) begin + data_18_V_load_reg_4274 <= data_18_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd19))) begin + data_19_V_load_reg_4269 <= data_19_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd1))) begin + data_1_V_load_reg_4359 <= data_1_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd20))) begin + data_20_V_load_reg_4264 <= data_20_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd21))) begin + data_21_V_load_reg_4259 <= data_21_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd22))) begin + data_22_V_load_reg_4254 <= data_22_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd23))) begin + data_23_V_load_reg_4249 <= data_23_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd24))) begin + data_24_V_load_reg_4244 <= data_24_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd25))) begin + data_25_V_load_reg_4239 <= data_25_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd26))) begin + data_26_V_load_reg_4234 <= data_26_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd27))) begin + data_27_V_load_reg_4229 <= data_27_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd28))) begin + data_28_V_load_reg_4224 <= data_28_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd29))) begin + data_29_V_load_reg_4219 <= data_29_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd2))) begin + data_2_V_load_reg_4354 <= data_2_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd30))) begin + data_30_V_load_reg_4214 <= data_30_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd31))) begin + data_31_V_load_reg_4209 <= data_31_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd32))) begin + data_32_V_load_reg_4204 <= data_32_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd33))) begin + data_33_V_load_reg_4199 <= data_33_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd34))) begin + data_34_V_load_reg_4194 <= data_34_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd35))) begin + data_35_V_load_reg_4189 <= data_35_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd36))) begin + data_36_V_load_reg_4184 <= data_36_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd37))) begin + data_37_V_load_reg_4179 <= data_37_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd38))) begin + data_38_V_load_reg_4174 <= data_38_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd39))) begin + data_39_V_load_reg_4169 <= data_39_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd3))) begin + data_3_V_load_reg_4349 <= data_3_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd40))) begin + data_40_V_load_reg_4164 <= data_40_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd41))) begin + data_41_V_load_reg_4159 <= data_41_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd42))) begin + data_42_V_load_reg_4154 <= data_42_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd43))) begin + data_43_V_load_reg_4149 <= data_43_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd44))) begin + data_44_V_load_reg_4144 <= data_44_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd45))) begin + data_45_V_load_reg_4139 <= data_45_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd46))) begin + data_46_V_load_reg_4134 <= data_46_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd47))) begin + data_47_V_load_reg_4129 <= data_47_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd48))) begin + data_48_V_load_reg_4124 <= data_48_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd49))) begin + data_49_V_load_reg_4119 <= data_49_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd4))) begin + data_4_V_load_reg_4344 <= data_4_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd50))) begin + data_50_V_load_reg_4114 <= data_50_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd51))) begin + data_51_V_load_reg_4109 <= data_51_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd52))) begin + data_52_V_load_reg_4104 <= data_52_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd53))) begin + data_53_V_load_reg_4099 <= data_53_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd54))) begin + data_54_V_load_reg_4094 <= data_54_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd55))) begin + data_55_V_load_reg_4089 <= data_55_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd56))) begin + data_56_V_load_reg_4084 <= data_56_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd57))) begin + data_57_V_load_reg_4079 <= data_57_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd58))) begin + data_58_V_load_reg_4074 <= data_58_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd59))) begin + data_59_V_load_reg_4069 <= data_59_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd5))) begin + data_5_V_load_reg_4339 <= data_5_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd60))) begin + data_60_V_load_reg_4064 <= data_60_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd61))) begin + data_61_V_load_reg_4059 <= data_61_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd62))) begin + data_62_V_load_reg_4054 <= data_62_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd63))) begin + data_63_V_load_reg_4049 <= data_63_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd64))) begin + data_64_V_load_reg_4044 <= data_64_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd65))) begin + data_65_V_load_reg_4039 <= data_65_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd66))) begin + data_66_V_load_reg_4034 <= data_66_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd67))) begin + data_67_V_load_reg_4029 <= data_67_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd68))) begin + data_68_V_load_reg_4024 <= data_68_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd69))) begin + data_69_V_load_reg_4019 <= data_69_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd6))) begin + data_6_V_load_reg_4334 <= data_6_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd70))) begin + data_70_V_load_reg_4014 <= data_70_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd71))) begin + data_71_V_load_reg_4009 <= data_71_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd72))) begin + data_72_V_load_reg_4004 <= data_72_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd73))) begin + data_73_V_load_reg_3999 <= data_73_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd74))) begin + data_74_V_load_reg_3994 <= data_74_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd75))) begin + data_75_V_load_reg_3989 <= data_75_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd76))) begin + data_76_V_load_reg_3984 <= data_76_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd77))) begin + data_77_V_load_reg_3979 <= data_77_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd78))) begin + data_78_V_load_reg_3974 <= data_78_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd79))) begin + data_79_V_load_reg_3969 <= data_79_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd7))) begin + data_7_V_load_reg_4329 <= data_7_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd80))) begin + data_80_V_load_reg_3964 <= data_80_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd81))) begin + data_81_V_load_reg_3959 <= data_81_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd82))) begin + data_82_V_load_reg_3954 <= data_82_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd83))) begin + data_83_V_load_reg_3949 <= data_83_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd84))) begin + data_84_V_load_reg_3944 <= data_84_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd85))) begin + data_85_V_load_reg_3939 <= data_85_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd86))) begin + data_86_V_load_reg_3934 <= data_86_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd87))) begin + data_87_V_load_reg_3929 <= data_87_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd88))) begin + data_88_V_load_reg_3924 <= data_88_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd89))) begin + data_89_V_load_reg_3919 <= data_89_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd8))) begin + data_8_V_load_reg_4324 <= data_8_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd90))) begin + data_90_V_load_reg_3914 <= data_90_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd91))) begin + data_91_V_load_reg_3909 <= data_91_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd92))) begin + data_92_V_load_reg_3904 <= data_92_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd93))) begin + data_93_V_load_reg_3899 <= data_93_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd94))) begin + data_94_V_load_reg_3894 <= data_94_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd95))) begin + data_95_V_load_reg_3889 <= data_95_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd96))) begin + data_96_V_load_reg_3884 <= data_96_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd97))) begin + data_97_V_load_reg_3879 <= data_97_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd98))) begin + data_98_V_load_reg_3874 <= data_98_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd99))) begin + data_99_V_load_reg_3869 <= data_99_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001) & (trunc_ln203_reg_3684 == 7'd9))) begin + data_9_V_load_reg_4319 <= data_9_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm))) begin + icmp_ln85_reg_3035 <= icmp_ln85_fu_2819_p2; + icmp_ln85_reg_3035_pp0_iter1_reg <= icmp_ln85_reg_3035; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ii_reg_3039 <= ii_fu_2825_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage3_11001))) begin + sext_ln203_reg_4414 <= sext_ln203_fu_2989_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln85_fu_2819_p2 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm))) begin + trunc_ln203_reg_3684 <= trunc_ln203_fu_2973_p1; + zext_ln96_reg_3688[9 : 0] <= zext_ln96_fu_2977_p1[9 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + trunc_ln4_reg_4420 <= {{grp_fu_2748_p2[10:4]}}; + trunc_ln708_1_reg_4425 <= {{grp_fu_2749_p2[10:4]}}; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage4 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4_11001))) begin + trunc_ln708_2_reg_4430 <= {{grp_fu_2748_p2[10:4]}}; + trunc_ln708_3_reg_4435 <= {{grp_fu_2749_p2[10:4]}}; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + trunc_ln708_4_reg_4440 <= {{grp_fu_2748_p2[10:4]}}; + trunc_ln708_5_reg_4445 <= {{grp_fu_2749_p2[10:4]}}; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + trunc_ln708_6_reg_4460 <= {{grp_fu_2748_p2[10:4]}}; + trunc_ln708_7_reg_4465 <= {{grp_fu_2749_p2[10:4]}}; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (ap_ST_fsm_pp0_stage2 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001))) begin + trunc_ln708_8_reg_4480 <= {{grp_fu_2748_p2[10:4]}}; + trunc_ln708_9_reg_4485 <= {{grp_fu_2749_p2[10:4]}}; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001))) begin + w9_V_0_load_reg_4374 <= w9_V_0_q0; + w9_V_1_load_reg_4379 <= w9_V_1_q0; + w9_V_2_load_reg_4384 <= w9_V_2_q0; + w9_V_3_load_reg_4389 <= w9_V_3_q0; + w9_V_4_load_reg_4394 <= w9_V_4_q0; + w9_V_5_load_reg_4399 <= w9_V_5_q0; + w9_V_6_load_reg_4404 <= w9_V_6_q0; + w9_V_7_load_reg_4409 <= w9_V_7_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1_11001))) begin + w9_V_8_load_reg_4470 <= w9_V_8_q0; + w9_V_9_load_reg_4475 <= w9_V_9_q0; + end +end + +always @ (*) begin + if ((icmp_ln85_fu_2819_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (real_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_ii_0_i_phi_fu_2480_p4 = ii_reg_3039; + end else begin + ap_phi_mux_ii_0_i_phi_fu_2480_p4 = ii_0_i_reg_2476; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_0_V_ce0 = 1'b1; + end else begin + data_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_100_V_ce0 = 1'b1; + end else begin + data_100_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_101_V_ce0 = 1'b1; + end else begin + data_101_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_102_V_ce0 = 1'b1; + end else begin + data_102_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_103_V_ce0 = 1'b1; + end else begin + data_103_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_104_V_ce0 = 1'b1; + end else begin + data_104_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_105_V_ce0 = 1'b1; + end else begin + data_105_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_106_V_ce0 = 1'b1; + end else begin + data_106_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_107_V_ce0 = 1'b1; + end else begin + data_107_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_108_V_ce0 = 1'b1; + end else begin + data_108_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_109_V_ce0 = 1'b1; + end else begin + data_109_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_10_V_ce0 = 1'b1; + end else begin + data_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_110_V_ce0 = 1'b1; + end else begin + data_110_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_111_V_ce0 = 1'b1; + end else begin + data_111_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_112_V_ce0 = 1'b1; + end else begin + data_112_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_113_V_ce0 = 1'b1; + end else begin + data_113_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_114_V_ce0 = 1'b1; + end else begin + data_114_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_115_V_ce0 = 1'b1; + end else begin + data_115_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_116_V_ce0 = 1'b1; + end else begin + data_116_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_117_V_ce0 = 1'b1; + end else begin + data_117_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_118_V_ce0 = 1'b1; + end else begin + data_118_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_119_V_ce0 = 1'b1; + end else begin + data_119_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_11_V_ce0 = 1'b1; + end else begin + data_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_120_V_ce0 = 1'b1; + end else begin + data_120_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_121_V_ce0 = 1'b1; + end else begin + data_121_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_122_V_ce0 = 1'b1; + end else begin + data_122_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_123_V_ce0 = 1'b1; + end else begin + data_123_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_124_V_ce0 = 1'b1; + end else begin + data_124_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_125_V_ce0 = 1'b1; + end else begin + data_125_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_126_V_ce0 = 1'b1; + end else begin + data_126_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_127_V_ce0 = 1'b1; + end else begin + data_127_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_12_V_ce0 = 1'b1; + end else begin + data_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_13_V_ce0 = 1'b1; + end else begin + data_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_14_V_ce0 = 1'b1; + end else begin + data_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_15_V_ce0 = 1'b1; + end else begin + data_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_16_V_ce0 = 1'b1; + end else begin + data_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_17_V_ce0 = 1'b1; + end else begin + data_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_18_V_ce0 = 1'b1; + end else begin + data_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_19_V_ce0 = 1'b1; + end else begin + data_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_1_V_ce0 = 1'b1; + end else begin + data_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_20_V_ce0 = 1'b1; + end else begin + data_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_21_V_ce0 = 1'b1; + end else begin + data_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_22_V_ce0 = 1'b1; + end else begin + data_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_23_V_ce0 = 1'b1; + end else begin + data_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_24_V_ce0 = 1'b1; + end else begin + data_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_25_V_ce0 = 1'b1; + end else begin + data_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_26_V_ce0 = 1'b1; + end else begin + data_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_27_V_ce0 = 1'b1; + end else begin + data_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_28_V_ce0 = 1'b1; + end else begin + data_28_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_29_V_ce0 = 1'b1; + end else begin + data_29_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_2_V_ce0 = 1'b1; + end else begin + data_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_30_V_ce0 = 1'b1; + end else begin + data_30_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_31_V_ce0 = 1'b1; + end else begin + data_31_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_32_V_ce0 = 1'b1; + end else begin + data_32_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_33_V_ce0 = 1'b1; + end else begin + data_33_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_34_V_ce0 = 1'b1; + end else begin + data_34_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_35_V_ce0 = 1'b1; + end else begin + data_35_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_36_V_ce0 = 1'b1; + end else begin + data_36_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_37_V_ce0 = 1'b1; + end else begin + data_37_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_38_V_ce0 = 1'b1; + end else begin + data_38_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_39_V_ce0 = 1'b1; + end else begin + data_39_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_3_V_ce0 = 1'b1; + end else begin + data_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_40_V_ce0 = 1'b1; + end else begin + data_40_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_41_V_ce0 = 1'b1; + end else begin + data_41_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_42_V_ce0 = 1'b1; + end else begin + data_42_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_43_V_ce0 = 1'b1; + end else begin + data_43_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_44_V_ce0 = 1'b1; + end else begin + data_44_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_45_V_ce0 = 1'b1; + end else begin + data_45_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_46_V_ce0 = 1'b1; + end else begin + data_46_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_47_V_ce0 = 1'b1; + end else begin + data_47_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_48_V_ce0 = 1'b1; + end else begin + data_48_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_49_V_ce0 = 1'b1; + end else begin + data_49_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_4_V_ce0 = 1'b1; + end else begin + data_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_50_V_ce0 = 1'b1; + end else begin + data_50_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_51_V_ce0 = 1'b1; + end else begin + data_51_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_52_V_ce0 = 1'b1; + end else begin + data_52_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_53_V_ce0 = 1'b1; + end else begin + data_53_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_54_V_ce0 = 1'b1; + end else begin + data_54_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_55_V_ce0 = 1'b1; + end else begin + data_55_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_56_V_ce0 = 1'b1; + end else begin + data_56_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_57_V_ce0 = 1'b1; + end else begin + data_57_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_58_V_ce0 = 1'b1; + end else begin + data_58_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_59_V_ce0 = 1'b1; + end else begin + data_59_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_5_V_ce0 = 1'b1; + end else begin + data_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_60_V_ce0 = 1'b1; + end else begin + data_60_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_61_V_ce0 = 1'b1; + end else begin + data_61_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_62_V_ce0 = 1'b1; + end else begin + data_62_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_63_V_ce0 = 1'b1; + end else begin + data_63_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_64_V_ce0 = 1'b1; + end else begin + data_64_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_65_V_ce0 = 1'b1; + end else begin + data_65_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_66_V_ce0 = 1'b1; + end else begin + data_66_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_67_V_ce0 = 1'b1; + end else begin + data_67_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_68_V_ce0 = 1'b1; + end else begin + data_68_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_69_V_ce0 = 1'b1; + end else begin + data_69_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_6_V_ce0 = 1'b1; + end else begin + data_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_70_V_ce0 = 1'b1; + end else begin + data_70_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_71_V_ce0 = 1'b1; + end else begin + data_71_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_72_V_ce0 = 1'b1; + end else begin + data_72_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_73_V_ce0 = 1'b1; + end else begin + data_73_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_74_V_ce0 = 1'b1; + end else begin + data_74_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_75_V_ce0 = 1'b1; + end else begin + data_75_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_76_V_ce0 = 1'b1; + end else begin + data_76_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_77_V_ce0 = 1'b1; + end else begin + data_77_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_78_V_ce0 = 1'b1; + end else begin + data_78_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_79_V_ce0 = 1'b1; + end else begin + data_79_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_7_V_ce0 = 1'b1; + end else begin + data_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_80_V_ce0 = 1'b1; + end else begin + data_80_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_81_V_ce0 = 1'b1; + end else begin + data_81_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_82_V_ce0 = 1'b1; + end else begin + data_82_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_83_V_ce0 = 1'b1; + end else begin + data_83_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_84_V_ce0 = 1'b1; + end else begin + data_84_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_85_V_ce0 = 1'b1; + end else begin + data_85_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_86_V_ce0 = 1'b1; + end else begin + data_86_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_87_V_ce0 = 1'b1; + end else begin + data_87_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_88_V_ce0 = 1'b1; + end else begin + data_88_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_89_V_ce0 = 1'b1; + end else begin + data_89_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_8_V_ce0 = 1'b1; + end else begin + data_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_90_V_ce0 = 1'b1; + end else begin + data_90_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_91_V_ce0 = 1'b1; + end else begin + data_91_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_92_V_ce0 = 1'b1; + end else begin + data_92_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_93_V_ce0 = 1'b1; + end else begin + data_93_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_94_V_ce0 = 1'b1; + end else begin + data_94_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_95_V_ce0 = 1'b1; + end else begin + data_95_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_96_V_ce0 = 1'b1; + end else begin + data_96_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_97_V_ce0 = 1'b1; + end else begin + data_97_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_98_V_ce0 = 1'b1; + end else begin + data_98_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_99_V_ce0 = 1'b1; + end else begin + data_99_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + data_9_V_ce0 = 1'b1; + end else begin + data_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_pp0_stage2 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_2748_p0 = sext_ln1118_8_fu_3027_p1; + end else if (((ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_2748_p0 = sext_ln1118_6_fu_3019_p1; + end else if (((ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_2748_p0 = sext_ln1118_4_fu_3011_p1; + end else if (((ap_ST_fsm_pp0_stage4 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_2748_p0 = sext_ln1118_2_fu_3003_p1; + end else if (((1'b0 == ap_block_pp0_stage3) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_2748_p0 = sext_ln1118_fu_2995_p1; + end else begin + grp_fu_2748_p0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_pp0_stage4 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((ap_ST_fsm_pp0_stage2 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + grp_fu_2748_p1 = sext_ln203_reg_4414; + end else if (((1'b0 == ap_block_pp0_stage3) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_2748_p1 = sext_ln203_fu_2989_p1; + end else begin + grp_fu_2748_p1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_pp0_stage2 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_2749_p0 = sext_ln1118_9_fu_3031_p1; + end else if (((ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_2749_p0 = sext_ln1118_7_fu_3023_p1; + end else if (((ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_2749_p0 = sext_ln1118_5_fu_3015_p1; + end else if (((ap_ST_fsm_pp0_stage4 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_2749_p0 = sext_ln1118_3_fu_3007_p1; + end else if (((1'b0 == ap_block_pp0_stage3) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_2749_p0 = sext_ln1118_1_fu_2999_p1; + end else begin + grp_fu_2749_p0 = 'b0; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_pp0_stage4 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((ap_ST_fsm_pp0_stage2 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((ap_ST_fsm_pp0_stage1 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + grp_fu_2749_p1 = sext_ln203_reg_4414; + end else if (((1'b0 == ap_block_pp0_stage3) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_2749_p1 = sext_ln203_fu_2989_p1; + end else begin + grp_fu_2749_p1 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_0_blk_n = mult_0_full_n; + end else begin + mult_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + mult_0_write = 1'b1; + end else begin + mult_0_write = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_1_blk_n = mult_1_full_n; + end else begin + mult_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + mult_1_write = 1'b1; + end else begin + mult_1_write = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_2_blk_n = mult_2_full_n; + end else begin + mult_2_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + mult_2_write = 1'b1; + end else begin + mult_2_write = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_3_blk_n = mult_3_full_n; + end else begin + mult_3_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + mult_3_write = 1'b1; + end else begin + mult_3_write = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_4_blk_n = mult_4_full_n; + end else begin + mult_4_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + mult_4_write = 1'b1; + end else begin + mult_4_write = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_5_blk_n = mult_5_full_n; + end else begin + mult_5_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + mult_5_write = 1'b1; + end else begin + mult_5_write = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_6_blk_n = mult_6_full_n; + end else begin + mult_6_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + mult_6_write = 1'b1; + end else begin + mult_6_write = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_7_blk_n = mult_7_full_n; + end else begin + mult_7_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + mult_7_write = 1'b1; + end else begin + mult_7_write = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_8_blk_n = mult_8_full_n; + end else begin + mult_8_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + mult_8_write = 1'b1; + end else begin + mult_8_write = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + mult_9_blk_n = mult_9_full_n; + end else begin + mult_9_blk_n = 1'b1; + end +end + +always @ (*) begin + if (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + mult_9_write = 1'b1; + end else begin + mult_9_write = 1'b0; + end +end + +always @ (*) begin + if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((start_once_reg == 1'b0) & (real_start == 1'b1))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + w9_V_0_ce0 = 1'b1; + end else begin + w9_V_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + w9_V_1_ce0 = 1'b1; + end else begin + w9_V_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + w9_V_2_ce0 = 1'b1; + end else begin + w9_V_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + w9_V_3_ce0 = 1'b1; + end else begin + w9_V_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + w9_V_4_ce0 = 1'b1; + end else begin + w9_V_4_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + w9_V_5_ce0 = 1'b1; + end else begin + w9_V_5_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + w9_V_6_ce0 = 1'b1; + end else begin + w9_V_6_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + w9_V_7_ce0 = 1'b1; + end else begin + w9_V_7_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + w9_V_8_ce0 = 1'b1; + end else begin + w9_V_8_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_ST_fsm_pp0_stage0 == ap_CS_fsm) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + w9_V_9_ce0 = 1'b1; + end else begin + w9_V_9_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (ap_ST_fsm_state1 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln85_fu_2819_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if (((icmp_ln85_fu_2819_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state11; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((1'b0 == ap_block_pp0_stage2_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((~((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage3_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1)) & (1'b0 == ap_block_pp0_stage3_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_ST_fsm_pp0_stage3 == ap_CS_fsm) & (1'b0 == ap_block_pp0_stage3_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state11; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_pp0_stage4 : begin + if ((1'b0 == ap_block_pp0_stage4_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_pp0_stage3_01001 = ((ap_enable_reg_pp0_iter1 == 1'b1) & (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_9_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_8_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_7_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_6_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_5_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_4_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_3_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_2_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_1_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_0_full_n == 1'b0)))); +end + +always @ (*) begin + ap_block_pp0_stage3_11001 = ((ap_enable_reg_pp0_iter1 == 1'b1) & (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_9_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_8_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_7_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_6_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_5_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_4_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_3_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_2_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_1_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_0_full_n == 1'b0)))); +end + +always @ (*) begin + ap_block_pp0_stage3_subdone = ((ap_enable_reg_pp0_iter1 == 1'b1) & (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_9_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_8_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_7_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_6_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_5_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_4_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_3_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_2_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_1_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_0_full_n == 1'b0)))); +end + +assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +always @ (*) begin + ap_block_state10_pp0_stage3_iter1 = (((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_9_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_8_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_7_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_6_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_5_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_4_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_3_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_2_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_1_full_n == 1'b0)) | ((icmp_ln85_reg_3035_pp0_iter1_reg == 1'd0) & (mult_0_full_n == 1'b0))); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_2286 = ((icmp_ln85_reg_3035 == 1'd0) & (ap_ST_fsm_pp0_stage2 == ap_CS_fsm) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_ready = internal_ap_ready; + +assign data_0_V_address0 = zext_ln203_fu_2841_p1; + +assign data_100_V_address0 = zext_ln203_fu_2841_p1; + +assign data_101_V_address0 = zext_ln203_fu_2841_p1; + +assign data_102_V_address0 = zext_ln203_fu_2841_p1; + +assign data_103_V_address0 = zext_ln203_fu_2841_p1; + +assign data_104_V_address0 = zext_ln203_fu_2841_p1; + +assign data_105_V_address0 = zext_ln203_fu_2841_p1; + +assign data_106_V_address0 = zext_ln203_fu_2841_p1; + +assign data_107_V_address0 = zext_ln203_fu_2841_p1; + +assign data_108_V_address0 = zext_ln203_fu_2841_p1; + +assign data_109_V_address0 = zext_ln203_fu_2841_p1; + +assign data_10_V_address0 = zext_ln203_fu_2841_p1; + +assign data_110_V_address0 = zext_ln203_fu_2841_p1; + +assign data_111_V_address0 = zext_ln203_fu_2841_p1; + +assign data_112_V_address0 = zext_ln203_fu_2841_p1; + +assign data_113_V_address0 = zext_ln203_fu_2841_p1; + +assign data_114_V_address0 = zext_ln203_fu_2841_p1; + +assign data_115_V_address0 = zext_ln203_fu_2841_p1; + +assign data_116_V_address0 = zext_ln203_fu_2841_p1; + +assign data_117_V_address0 = zext_ln203_fu_2841_p1; + +assign data_118_V_address0 = zext_ln203_fu_2841_p1; + +assign data_119_V_address0 = zext_ln203_fu_2841_p1; + +assign data_11_V_address0 = zext_ln203_fu_2841_p1; + +assign data_120_V_address0 = zext_ln203_fu_2841_p1; + +assign data_121_V_address0 = zext_ln203_fu_2841_p1; + +assign data_122_V_address0 = zext_ln203_fu_2841_p1; + +assign data_123_V_address0 = zext_ln203_fu_2841_p1; + +assign data_124_V_address0 = zext_ln203_fu_2841_p1; + +assign data_125_V_address0 = zext_ln203_fu_2841_p1; + +assign data_126_V_address0 = zext_ln203_fu_2841_p1; + +assign data_127_V_address0 = zext_ln203_fu_2841_p1; + +assign data_12_V_address0 = zext_ln203_fu_2841_p1; + +assign data_13_V_address0 = zext_ln203_fu_2841_p1; + +assign data_14_V_address0 = zext_ln203_fu_2841_p1; + +assign data_15_V_address0 = zext_ln203_fu_2841_p1; + +assign data_16_V_address0 = zext_ln203_fu_2841_p1; + +assign data_17_V_address0 = zext_ln203_fu_2841_p1; + +assign data_18_V_address0 = zext_ln203_fu_2841_p1; + +assign data_19_V_address0 = zext_ln203_fu_2841_p1; + +assign data_1_V_address0 = zext_ln203_fu_2841_p1; + +assign data_20_V_address0 = zext_ln203_fu_2841_p1; + +assign data_21_V_address0 = zext_ln203_fu_2841_p1; + +assign data_22_V_address0 = zext_ln203_fu_2841_p1; + +assign data_23_V_address0 = zext_ln203_fu_2841_p1; + +assign data_24_V_address0 = zext_ln203_fu_2841_p1; + +assign data_25_V_address0 = zext_ln203_fu_2841_p1; + +assign data_26_V_address0 = zext_ln203_fu_2841_p1; + +assign data_27_V_address0 = zext_ln203_fu_2841_p1; + +assign data_28_V_address0 = zext_ln203_fu_2841_p1; + +assign data_29_V_address0 = zext_ln203_fu_2841_p1; + +assign data_2_V_address0 = zext_ln203_fu_2841_p1; + +assign data_30_V_address0 = zext_ln203_fu_2841_p1; + +assign data_31_V_address0 = zext_ln203_fu_2841_p1; + +assign data_32_V_address0 = zext_ln203_fu_2841_p1; + +assign data_33_V_address0 = zext_ln203_fu_2841_p1; + +assign data_34_V_address0 = zext_ln203_fu_2841_p1; + +assign data_35_V_address0 = zext_ln203_fu_2841_p1; + +assign data_36_V_address0 = zext_ln203_fu_2841_p1; + +assign data_37_V_address0 = zext_ln203_fu_2841_p1; + +assign data_38_V_address0 = zext_ln203_fu_2841_p1; + +assign data_39_V_address0 = zext_ln203_fu_2841_p1; + +assign data_3_V_address0 = zext_ln203_fu_2841_p1; + +assign data_40_V_address0 = zext_ln203_fu_2841_p1; + +assign data_41_V_address0 = zext_ln203_fu_2841_p1; + +assign data_42_V_address0 = zext_ln203_fu_2841_p1; + +assign data_43_V_address0 = zext_ln203_fu_2841_p1; + +assign data_44_V_address0 = zext_ln203_fu_2841_p1; + +assign data_45_V_address0 = zext_ln203_fu_2841_p1; + +assign data_46_V_address0 = zext_ln203_fu_2841_p1; + +assign data_47_V_address0 = zext_ln203_fu_2841_p1; + +assign data_48_V_address0 = zext_ln203_fu_2841_p1; + +assign data_49_V_address0 = zext_ln203_fu_2841_p1; + +assign data_4_V_address0 = zext_ln203_fu_2841_p1; + +assign data_50_V_address0 = zext_ln203_fu_2841_p1; + +assign data_51_V_address0 = zext_ln203_fu_2841_p1; + +assign data_52_V_address0 = zext_ln203_fu_2841_p1; + +assign data_53_V_address0 = zext_ln203_fu_2841_p1; + +assign data_54_V_address0 = zext_ln203_fu_2841_p1; + +assign data_55_V_address0 = zext_ln203_fu_2841_p1; + +assign data_56_V_address0 = zext_ln203_fu_2841_p1; + +assign data_57_V_address0 = zext_ln203_fu_2841_p1; + +assign data_58_V_address0 = zext_ln203_fu_2841_p1; + +assign data_59_V_address0 = zext_ln203_fu_2841_p1; + +assign data_5_V_address0 = zext_ln203_fu_2841_p1; + +assign data_60_V_address0 = zext_ln203_fu_2841_p1; + +assign data_61_V_address0 = zext_ln203_fu_2841_p1; + +assign data_62_V_address0 = zext_ln203_fu_2841_p1; + +assign data_63_V_address0 = zext_ln203_fu_2841_p1; + +assign data_64_V_address0 = zext_ln203_fu_2841_p1; + +assign data_65_V_address0 = zext_ln203_fu_2841_p1; + +assign data_66_V_address0 = zext_ln203_fu_2841_p1; + +assign data_67_V_address0 = zext_ln203_fu_2841_p1; + +assign data_68_V_address0 = zext_ln203_fu_2841_p1; + +assign data_69_V_address0 = zext_ln203_fu_2841_p1; + +assign data_6_V_address0 = zext_ln203_fu_2841_p1; + +assign data_70_V_address0 = zext_ln203_fu_2841_p1; + +assign data_71_V_address0 = zext_ln203_fu_2841_p1; + +assign data_72_V_address0 = zext_ln203_fu_2841_p1; + +assign data_73_V_address0 = zext_ln203_fu_2841_p1; + +assign data_74_V_address0 = zext_ln203_fu_2841_p1; + +assign data_75_V_address0 = zext_ln203_fu_2841_p1; + +assign data_76_V_address0 = zext_ln203_fu_2841_p1; + +assign data_77_V_address0 = zext_ln203_fu_2841_p1; + +assign data_78_V_address0 = zext_ln203_fu_2841_p1; + +assign data_79_V_address0 = zext_ln203_fu_2841_p1; + +assign data_7_V_address0 = zext_ln203_fu_2841_p1; + +assign data_80_V_address0 = zext_ln203_fu_2841_p1; + +assign data_81_V_address0 = zext_ln203_fu_2841_p1; + +assign data_82_V_address0 = zext_ln203_fu_2841_p1; + +assign data_83_V_address0 = zext_ln203_fu_2841_p1; + +assign data_84_V_address0 = zext_ln203_fu_2841_p1; + +assign data_85_V_address0 = zext_ln203_fu_2841_p1; + +assign data_86_V_address0 = zext_ln203_fu_2841_p1; + +assign data_87_V_address0 = zext_ln203_fu_2841_p1; + +assign data_88_V_address0 = zext_ln203_fu_2841_p1; + +assign data_89_V_address0 = zext_ln203_fu_2841_p1; + +assign data_8_V_address0 = zext_ln203_fu_2841_p1; + +assign data_90_V_address0 = zext_ln203_fu_2841_p1; + +assign data_91_V_address0 = zext_ln203_fu_2841_p1; + +assign data_92_V_address0 = zext_ln203_fu_2841_p1; + +assign data_93_V_address0 = zext_ln203_fu_2841_p1; + +assign data_94_V_address0 = zext_ln203_fu_2841_p1; + +assign data_95_V_address0 = zext_ln203_fu_2841_p1; + +assign data_96_V_address0 = zext_ln203_fu_2841_p1; + +assign data_97_V_address0 = zext_ln203_fu_2841_p1; + +assign data_98_V_address0 = zext_ln203_fu_2841_p1; + +assign data_99_V_address0 = zext_ln203_fu_2841_p1; + +assign data_9_V_address0 = zext_ln203_fu_2841_p1; + +assign grp_fu_2748_p2 = ((grp_fu_2748_p0) * (grp_fu_2748_p1)); + +assign grp_fu_2749_p2 = ((grp_fu_2749_p0) * (grp_fu_2749_p1)); + +assign icmp_ln85_fu_2819_p2 = ((ap_phi_mux_ii_0_i_phi_fu_2480_p4 == 10'd588) ? 1'b1 : 1'b0); + +assign ii_fu_2825_p2 = (ap_phi_mux_ii_0_i_phi_fu_2480_p4 + 10'd1); + +assign lshr_ln_fu_2831_p4 = {{ap_phi_mux_ii_0_i_phi_fu_2480_p4[9:7]}}; + +assign mult_0_din = trunc_ln4_reg_4420; + +assign mult_1_din = trunc_ln708_1_reg_4425; + +assign mult_2_din = trunc_ln708_2_reg_4430; + +assign mult_3_din = trunc_ln708_3_reg_4435; + +assign mult_4_din = trunc_ln708_4_reg_4440; + +assign mult_5_din = trunc_ln708_5_reg_4445; + +assign mult_6_din = trunc_ln708_6_reg_4460; + +assign mult_7_din = trunc_ln708_7_reg_4465; + +assign mult_8_din = trunc_ln708_8_reg_4480; + +assign mult_9_din = trunc_ln708_9_reg_4485; + +assign sext_ln1118_1_fu_2999_p1 = (w9_V_1_load_reg_4379); + +assign sext_ln1118_2_fu_3003_p1 = (w9_V_2_load_reg_4384); + +assign sext_ln1118_3_fu_3007_p1 = (w9_V_3_load_reg_4389); + +assign sext_ln1118_4_fu_3011_p1 = (w9_V_4_load_reg_4394); + +assign sext_ln1118_5_fu_3015_p1 = (w9_V_5_load_reg_4399); + +assign sext_ln1118_6_fu_3019_p1 = (w9_V_6_load_reg_4404); + +assign sext_ln1118_7_fu_3023_p1 = (w9_V_7_load_reg_4409); + +assign sext_ln1118_8_fu_3027_p1 = (w9_V_8_load_reg_4470); + +assign sext_ln1118_9_fu_3031_p1 = (w9_V_9_load_reg_4475); + +assign sext_ln1118_fu_2995_p1 = (w9_V_0_load_reg_4374); + +assign sext_ln203_fu_2989_p1 = (ap_phi_reg_pp0_iter0_cache_V_reg_2487); + +assign start_out = real_start; + +assign trunc_ln203_fu_2973_p1 = ap_phi_mux_ii_0_i_phi_fu_2480_p4[6:0]; + +assign w9_V_0_address0 = zext_ln96_fu_2977_p1; + +assign w9_V_1_address0 = zext_ln96_fu_2977_p1; + +assign w9_V_2_address0 = zext_ln96_fu_2977_p1; + +assign w9_V_3_address0 = zext_ln96_fu_2977_p1; + +assign w9_V_4_address0 = zext_ln96_fu_2977_p1; + +assign w9_V_5_address0 = zext_ln96_fu_2977_p1; + +assign w9_V_6_address0 = zext_ln96_fu_2977_p1; + +assign w9_V_7_address0 = zext_ln96_fu_2977_p1; + +assign w9_V_8_address0 = zext_ln96_reg_3688; + +assign w9_V_9_address0 = zext_ln96_reg_3688; + +assign zext_ln203_fu_2841_p1 = lshr_ln_fu_2831_p4; + +assign zext_ln96_fu_2977_p1 = ap_phi_mux_ii_0_i_phi_fu_2480_p4; + +always @ (posedge ap_clk) begin + zext_ln96_reg_3688[63:10] <= 54'b000000000000000000000000000000000000000000000000000000; +end + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bFp_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 3; +parameter AWIDTH = 10; +parameter MEM_SIZE = 588; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +`ifdef QUARTUS +initial begin + $readmemh("/home/boutros6/koios++/quartus_runs/rtl/lenet_rom/dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bFp_rom.dat", ram); +end +`endif + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bFp( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd3; +parameter AddressRange = 32'd588; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bFp_rom dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bFp_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bGp_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 3; +parameter AWIDTH = 10; +parameter MEM_SIZE = 588; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +`ifdef QUARTUS +initial begin + $readmemh("/home/boutros6/koios++/quartus_runs/rtl/lenet_rom/dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bGp_rom.dat", ram); +end +`endif + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bGp( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd3; +parameter AddressRange = 32'd588; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bGp_rom dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bGp_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bHp_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 3; +parameter AWIDTH = 10; +parameter MEM_SIZE = 588; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +`ifdef QUARTUS +initial begin + $readmemh("/home/boutros6/koios++/quartus_runs/rtl/lenet_rom/dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bHp_rom.dat", ram); +end +`endif + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bHp( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd3; +parameter AddressRange = 32'd588; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bHp_rom dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bHp_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bIp_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 3; +parameter AWIDTH = 10; +parameter MEM_SIZE = 588; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +`ifdef QUARTUS +initial begin + $readmemh("/home/boutros6/koios++/quartus_runs/rtl/lenet_rom/dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bIp_rom.dat", ram); +end +`endif + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bIp( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd3; +parameter AddressRange = 32'd588; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bIp_rom dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bIp_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bJp_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 3; +parameter AWIDTH = 10; +parameter MEM_SIZE = 588; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +`ifdef QUARTUS +initial begin + $readmemh("/home/boutros6/koios++/quartus_runs/rtl/lenet_rom/dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bJp_rom.dat", ram); +end +`endif + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bJp( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd3; +parameter AddressRange = 32'd588; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bJp_rom dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bJp_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bKp_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 3; +parameter AWIDTH = 10; +parameter MEM_SIZE = 588; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +`ifdef QUARTUS +initial begin + $readmemh("/home/boutros6/koios++/quartus_runs/rtl/lenet_rom/dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bKp_rom.dat", ram); +end +`endif + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bKp( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd3; +parameter AddressRange = 32'd588; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bKp_rom dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bKp_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bLp_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 3; +parameter AWIDTH = 10; +parameter MEM_SIZE = 588; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +`ifdef QUARTUS +initial begin + $readmemh("/home/boutros6/koios++/quartus_runs/rtl/lenet_rom/dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bLp_rom.dat", ram); +end +`endif + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bLp( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd3; +parameter AddressRange = 32'd588; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bLp_rom dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bLp_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bMq_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 3; +parameter AWIDTH = 10; +parameter MEM_SIZE = 588; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +`ifdef QUARTUS +initial begin + $readmemh("/home/boutros6/koios++/quartus_runs/rtl/lenet_rom/dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bMq_rom.dat", ram); +end +`endif + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bMq( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd3; +parameter AddressRange = 32'd588; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bMq_rom dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bMq_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bNq_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 3; +parameter AWIDTH = 10; +parameter MEM_SIZE = 588; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +`ifdef QUARTUS +initial begin + $readmemh("/home/boutros6/koios++/quartus_runs/rtl/lenet_rom/dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bNq_rom.dat", ram); +end +`endif + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bNq( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd3; +parameter AddressRange = 32'd588; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bNq_rom dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bNq_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bOq_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 3; +parameter AWIDTH = 10; +parameter MEM_SIZE = 588; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +`ifdef QUARTUS +initial begin + $readmemh("/home/boutros6/koios++/quartus_runs/rtl/lenet_rom/dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bOq_rom.dat", ram); +end +`endif + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bOq( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd3; +parameter AddressRange = 32'd588; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bOq_rom dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_w9bOq_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module dense_latency_0_0_0_0_0_0_0_0_0_0_0 ( + data_0_V_address0, + data_0_V_ce0, + data_0_V_d0, + data_0_V_q0, + data_0_V_we0, + data_0_V_address1, + data_0_V_ce1, + data_0_V_d1, + data_0_V_q1, + data_0_V_we1, + data_1_V_address0, + data_1_V_ce0, + data_1_V_d0, + data_1_V_q0, + data_1_V_we0, + data_1_V_address1, + data_1_V_ce1, + data_1_V_d1, + data_1_V_q1, + data_1_V_we1, + data_2_V_address0, + data_2_V_ce0, + data_2_V_d0, + data_2_V_q0, + data_2_V_we0, + data_2_V_address1, + data_2_V_ce1, + data_2_V_d1, + data_2_V_q1, + data_2_V_we1, + data_3_V_address0, + data_3_V_ce0, + data_3_V_d0, + data_3_V_q0, + data_3_V_we0, + data_3_V_address1, + data_3_V_ce1, + data_3_V_d1, + data_3_V_q1, + data_3_V_we1, + data_4_V_address0, + data_4_V_ce0, + data_4_V_d0, + data_4_V_q0, + data_4_V_we0, + data_4_V_address1, + data_4_V_ce1, + data_4_V_d1, + data_4_V_q1, + data_4_V_we1, + data_5_V_address0, + data_5_V_ce0, + data_5_V_d0, + data_5_V_q0, + data_5_V_we0, + data_5_V_address1, + data_5_V_ce1, + data_5_V_d1, + data_5_V_q1, + data_5_V_we1, + data_6_V_address0, + data_6_V_ce0, + data_6_V_d0, + data_6_V_q0, + data_6_V_we0, + data_6_V_address1, + data_6_V_ce1, + data_6_V_d1, + data_6_V_q1, + data_6_V_we1, + data_7_V_address0, + data_7_V_ce0, + data_7_V_d0, + data_7_V_q0, + data_7_V_we0, + data_7_V_address1, + data_7_V_ce1, + data_7_V_d1, + data_7_V_q1, + data_7_V_we1, + data_8_V_address0, + data_8_V_ce0, + data_8_V_d0, + data_8_V_q0, + data_8_V_we0, + data_8_V_address1, + data_8_V_ce1, + data_8_V_d1, + data_8_V_q1, + data_8_V_we1, + data_9_V_address0, + data_9_V_ce0, + data_9_V_d0, + data_9_V_q0, + data_9_V_we0, + data_9_V_address1, + data_9_V_ce1, + data_9_V_d1, + data_9_V_q1, + data_9_V_we1, + data_10_V_address0, + data_10_V_ce0, + data_10_V_d0, + data_10_V_q0, + data_10_V_we0, + data_10_V_address1, + data_10_V_ce1, + data_10_V_d1, + data_10_V_q1, + data_10_V_we1, + data_11_V_address0, + data_11_V_ce0, + data_11_V_d0, + data_11_V_q0, + data_11_V_we0, + data_11_V_address1, + data_11_V_ce1, + data_11_V_d1, + data_11_V_q1, + data_11_V_we1, + data_12_V_address0, + data_12_V_ce0, + data_12_V_d0, + data_12_V_q0, + data_12_V_we0, + data_12_V_address1, + data_12_V_ce1, + data_12_V_d1, + data_12_V_q1, + data_12_V_we1, + data_13_V_address0, + data_13_V_ce0, + data_13_V_d0, + data_13_V_q0, + data_13_V_we0, + data_13_V_address1, + data_13_V_ce1, + data_13_V_d1, + data_13_V_q1, + data_13_V_we1, + data_14_V_address0, + data_14_V_ce0, + data_14_V_d0, + data_14_V_q0, + data_14_V_we0, + data_14_V_address1, + data_14_V_ce1, + data_14_V_d1, + data_14_V_q1, + data_14_V_we1, + data_15_V_address0, + data_15_V_ce0, + data_15_V_d0, + data_15_V_q0, + data_15_V_we0, + data_15_V_address1, + data_15_V_ce1, + data_15_V_d1, + data_15_V_q1, + data_15_V_we1, + data_16_V_address0, + data_16_V_ce0, + data_16_V_d0, + data_16_V_q0, + data_16_V_we0, + data_16_V_address1, + data_16_V_ce1, + data_16_V_d1, + data_16_V_q1, + data_16_V_we1, + data_17_V_address0, + data_17_V_ce0, + data_17_V_d0, + data_17_V_q0, + data_17_V_we0, + data_17_V_address1, + data_17_V_ce1, + data_17_V_d1, + data_17_V_q1, + data_17_V_we1, + data_18_V_address0, + data_18_V_ce0, + data_18_V_d0, + data_18_V_q0, + data_18_V_we0, + data_18_V_address1, + data_18_V_ce1, + data_18_V_d1, + data_18_V_q1, + data_18_V_we1, + data_19_V_address0, + data_19_V_ce0, + data_19_V_d0, + data_19_V_q0, + data_19_V_we0, + data_19_V_address1, + data_19_V_ce1, + data_19_V_d1, + data_19_V_q1, + data_19_V_we1, + data_20_V_address0, + data_20_V_ce0, + data_20_V_d0, + data_20_V_q0, + data_20_V_we0, + data_20_V_address1, + data_20_V_ce1, + data_20_V_d1, + data_20_V_q1, + data_20_V_we1, + data_21_V_address0, + data_21_V_ce0, + data_21_V_d0, + data_21_V_q0, + data_21_V_we0, + data_21_V_address1, + data_21_V_ce1, + data_21_V_d1, + data_21_V_q1, + data_21_V_we1, + data_22_V_address0, + data_22_V_ce0, + data_22_V_d0, + data_22_V_q0, + data_22_V_we0, + data_22_V_address1, + data_22_V_ce1, + data_22_V_d1, + data_22_V_q1, + data_22_V_we1, + data_23_V_address0, + data_23_V_ce0, + data_23_V_d0, + data_23_V_q0, + data_23_V_we0, + data_23_V_address1, + data_23_V_ce1, + data_23_V_d1, + data_23_V_q1, + data_23_V_we1, + data_24_V_address0, + data_24_V_ce0, + data_24_V_d0, + data_24_V_q0, + data_24_V_we0, + data_24_V_address1, + data_24_V_ce1, + data_24_V_d1, + data_24_V_q1, + data_24_V_we1, + data_25_V_address0, + data_25_V_ce0, + data_25_V_d0, + data_25_V_q0, + data_25_V_we0, + data_25_V_address1, + data_25_V_ce1, + data_25_V_d1, + data_25_V_q1, + data_25_V_we1, + data_26_V_address0, + data_26_V_ce0, + data_26_V_d0, + data_26_V_q0, + data_26_V_we0, + data_26_V_address1, + data_26_V_ce1, + data_26_V_d1, + data_26_V_q1, + data_26_V_we1, + data_27_V_address0, + data_27_V_ce0, + data_27_V_d0, + data_27_V_q0, + data_27_V_we0, + data_27_V_address1, + data_27_V_ce1, + data_27_V_d1, + data_27_V_q1, + data_27_V_we1, + data_28_V_address0, + data_28_V_ce0, + data_28_V_d0, + data_28_V_q0, + data_28_V_we0, + data_28_V_address1, + data_28_V_ce1, + data_28_V_d1, + data_28_V_q1, + data_28_V_we1, + data_29_V_address0, + data_29_V_ce0, + data_29_V_d0, + data_29_V_q0, + data_29_V_we0, + data_29_V_address1, + data_29_V_ce1, + data_29_V_d1, + data_29_V_q1, + data_29_V_we1, + data_30_V_address0, + data_30_V_ce0, + data_30_V_d0, + data_30_V_q0, + data_30_V_we0, + data_30_V_address1, + data_30_V_ce1, + data_30_V_d1, + data_30_V_q1, + data_30_V_we1, + data_31_V_address0, + data_31_V_ce0, + data_31_V_d0, + data_31_V_q0, + data_31_V_we0, + data_31_V_address1, + data_31_V_ce1, + data_31_V_d1, + data_31_V_q1, + data_31_V_we1, + data_32_V_address0, + data_32_V_ce0, + data_32_V_d0, + data_32_V_q0, + data_32_V_we0, + data_32_V_address1, + data_32_V_ce1, + data_32_V_d1, + data_32_V_q1, + data_32_V_we1, + data_33_V_address0, + data_33_V_ce0, + data_33_V_d0, + data_33_V_q0, + data_33_V_we0, + data_33_V_address1, + data_33_V_ce1, + data_33_V_d1, + data_33_V_q1, + data_33_V_we1, + data_34_V_address0, + data_34_V_ce0, + data_34_V_d0, + data_34_V_q0, + data_34_V_we0, + data_34_V_address1, + data_34_V_ce1, + data_34_V_d1, + data_34_V_q1, + data_34_V_we1, + data_35_V_address0, + data_35_V_ce0, + data_35_V_d0, + data_35_V_q0, + data_35_V_we0, + data_35_V_address1, + data_35_V_ce1, + data_35_V_d1, + data_35_V_q1, + data_35_V_we1, + data_36_V_address0, + data_36_V_ce0, + data_36_V_d0, + data_36_V_q0, + data_36_V_we0, + data_36_V_address1, + data_36_V_ce1, + data_36_V_d1, + data_36_V_q1, + data_36_V_we1, + data_37_V_address0, + data_37_V_ce0, + data_37_V_d0, + data_37_V_q0, + data_37_V_we0, + data_37_V_address1, + data_37_V_ce1, + data_37_V_d1, + data_37_V_q1, + data_37_V_we1, + data_38_V_address0, + data_38_V_ce0, + data_38_V_d0, + data_38_V_q0, + data_38_V_we0, + data_38_V_address1, + data_38_V_ce1, + data_38_V_d1, + data_38_V_q1, + data_38_V_we1, + data_39_V_address0, + data_39_V_ce0, + data_39_V_d0, + data_39_V_q0, + data_39_V_we0, + data_39_V_address1, + data_39_V_ce1, + data_39_V_d1, + data_39_V_q1, + data_39_V_we1, + data_40_V_address0, + data_40_V_ce0, + data_40_V_d0, + data_40_V_q0, + data_40_V_we0, + data_40_V_address1, + data_40_V_ce1, + data_40_V_d1, + data_40_V_q1, + data_40_V_we1, + data_41_V_address0, + data_41_V_ce0, + data_41_V_d0, + data_41_V_q0, + data_41_V_we0, + data_41_V_address1, + data_41_V_ce1, + data_41_V_d1, + data_41_V_q1, + data_41_V_we1, + data_42_V_address0, + data_42_V_ce0, + data_42_V_d0, + data_42_V_q0, + data_42_V_we0, + data_42_V_address1, + data_42_V_ce1, + data_42_V_d1, + data_42_V_q1, + data_42_V_we1, + data_43_V_address0, + data_43_V_ce0, + data_43_V_d0, + data_43_V_q0, + data_43_V_we0, + data_43_V_address1, + data_43_V_ce1, + data_43_V_d1, + data_43_V_q1, + data_43_V_we1, + data_44_V_address0, + data_44_V_ce0, + data_44_V_d0, + data_44_V_q0, + data_44_V_we0, + data_44_V_address1, + data_44_V_ce1, + data_44_V_d1, + data_44_V_q1, + data_44_V_we1, + data_45_V_address0, + data_45_V_ce0, + data_45_V_d0, + data_45_V_q0, + data_45_V_we0, + data_45_V_address1, + data_45_V_ce1, + data_45_V_d1, + data_45_V_q1, + data_45_V_we1, + data_46_V_address0, + data_46_V_ce0, + data_46_V_d0, + data_46_V_q0, + data_46_V_we0, + data_46_V_address1, + data_46_V_ce1, + data_46_V_d1, + data_46_V_q1, + data_46_V_we1, + data_47_V_address0, + data_47_V_ce0, + data_47_V_d0, + data_47_V_q0, + data_47_V_we0, + data_47_V_address1, + data_47_V_ce1, + data_47_V_d1, + data_47_V_q1, + data_47_V_we1, + data_48_V_address0, + data_48_V_ce0, + data_48_V_d0, + data_48_V_q0, + data_48_V_we0, + data_48_V_address1, + data_48_V_ce1, + data_48_V_d1, + data_48_V_q1, + data_48_V_we1, + data_49_V_address0, + data_49_V_ce0, + data_49_V_d0, + data_49_V_q0, + data_49_V_we0, + data_49_V_address1, + data_49_V_ce1, + data_49_V_d1, + data_49_V_q1, + data_49_V_we1, + data_50_V_address0, + data_50_V_ce0, + data_50_V_d0, + data_50_V_q0, + data_50_V_we0, + data_50_V_address1, + data_50_V_ce1, + data_50_V_d1, + data_50_V_q1, + data_50_V_we1, + data_51_V_address0, + data_51_V_ce0, + data_51_V_d0, + data_51_V_q0, + data_51_V_we0, + data_51_V_address1, + data_51_V_ce1, + data_51_V_d1, + data_51_V_q1, + data_51_V_we1, + data_52_V_address0, + data_52_V_ce0, + data_52_V_d0, + data_52_V_q0, + data_52_V_we0, + data_52_V_address1, + data_52_V_ce1, + data_52_V_d1, + data_52_V_q1, + data_52_V_we1, + data_53_V_address0, + data_53_V_ce0, + data_53_V_d0, + data_53_V_q0, + data_53_V_we0, + data_53_V_address1, + data_53_V_ce1, + data_53_V_d1, + data_53_V_q1, + data_53_V_we1, + data_54_V_address0, + data_54_V_ce0, + data_54_V_d0, + data_54_V_q0, + data_54_V_we0, + data_54_V_address1, + data_54_V_ce1, + data_54_V_d1, + data_54_V_q1, + data_54_V_we1, + data_55_V_address0, + data_55_V_ce0, + data_55_V_d0, + data_55_V_q0, + data_55_V_we0, + data_55_V_address1, + data_55_V_ce1, + data_55_V_d1, + data_55_V_q1, + data_55_V_we1, + data_56_V_address0, + data_56_V_ce0, + data_56_V_d0, + data_56_V_q0, + data_56_V_we0, + data_56_V_address1, + data_56_V_ce1, + data_56_V_d1, + data_56_V_q1, + data_56_V_we1, + data_57_V_address0, + data_57_V_ce0, + data_57_V_d0, + data_57_V_q0, + data_57_V_we0, + data_57_V_address1, + data_57_V_ce1, + data_57_V_d1, + data_57_V_q1, + data_57_V_we1, + data_58_V_address0, + data_58_V_ce0, + data_58_V_d0, + data_58_V_q0, + data_58_V_we0, + data_58_V_address1, + data_58_V_ce1, + data_58_V_d1, + data_58_V_q1, + data_58_V_we1, + data_59_V_address0, + data_59_V_ce0, + data_59_V_d0, + data_59_V_q0, + data_59_V_we0, + data_59_V_address1, + data_59_V_ce1, + data_59_V_d1, + data_59_V_q1, + data_59_V_we1, + data_60_V_address0, + data_60_V_ce0, + data_60_V_d0, + data_60_V_q0, + data_60_V_we0, + data_60_V_address1, + data_60_V_ce1, + data_60_V_d1, + data_60_V_q1, + data_60_V_we1, + data_61_V_address0, + data_61_V_ce0, + data_61_V_d0, + data_61_V_q0, + data_61_V_we0, + data_61_V_address1, + data_61_V_ce1, + data_61_V_d1, + data_61_V_q1, + data_61_V_we1, + data_62_V_address0, + data_62_V_ce0, + data_62_V_d0, + data_62_V_q0, + data_62_V_we0, + data_62_V_address1, + data_62_V_ce1, + data_62_V_d1, + data_62_V_q1, + data_62_V_we1, + data_63_V_address0, + data_63_V_ce0, + data_63_V_d0, + data_63_V_q0, + data_63_V_we0, + data_63_V_address1, + data_63_V_ce1, + data_63_V_d1, + data_63_V_q1, + data_63_V_we1, + data_64_V_address0, + data_64_V_ce0, + data_64_V_d0, + data_64_V_q0, + data_64_V_we0, + data_64_V_address1, + data_64_V_ce1, + data_64_V_d1, + data_64_V_q1, + data_64_V_we1, + data_65_V_address0, + data_65_V_ce0, + data_65_V_d0, + data_65_V_q0, + data_65_V_we0, + data_65_V_address1, + data_65_V_ce1, + data_65_V_d1, + data_65_V_q1, + data_65_V_we1, + data_66_V_address0, + data_66_V_ce0, + data_66_V_d0, + data_66_V_q0, + data_66_V_we0, + data_66_V_address1, + data_66_V_ce1, + data_66_V_d1, + data_66_V_q1, + data_66_V_we1, + data_67_V_address0, + data_67_V_ce0, + data_67_V_d0, + data_67_V_q0, + data_67_V_we0, + data_67_V_address1, + data_67_V_ce1, + data_67_V_d1, + data_67_V_q1, + data_67_V_we1, + data_68_V_address0, + data_68_V_ce0, + data_68_V_d0, + data_68_V_q0, + data_68_V_we0, + data_68_V_address1, + data_68_V_ce1, + data_68_V_d1, + data_68_V_q1, + data_68_V_we1, + data_69_V_address0, + data_69_V_ce0, + data_69_V_d0, + data_69_V_q0, + data_69_V_we0, + data_69_V_address1, + data_69_V_ce1, + data_69_V_d1, + data_69_V_q1, + data_69_V_we1, + data_70_V_address0, + data_70_V_ce0, + data_70_V_d0, + data_70_V_q0, + data_70_V_we0, + data_70_V_address1, + data_70_V_ce1, + data_70_V_d1, + data_70_V_q1, + data_70_V_we1, + data_71_V_address0, + data_71_V_ce0, + data_71_V_d0, + data_71_V_q0, + data_71_V_we0, + data_71_V_address1, + data_71_V_ce1, + data_71_V_d1, + data_71_V_q1, + data_71_V_we1, + data_72_V_address0, + data_72_V_ce0, + data_72_V_d0, + data_72_V_q0, + data_72_V_we0, + data_72_V_address1, + data_72_V_ce1, + data_72_V_d1, + data_72_V_q1, + data_72_V_we1, + data_73_V_address0, + data_73_V_ce0, + data_73_V_d0, + data_73_V_q0, + data_73_V_we0, + data_73_V_address1, + data_73_V_ce1, + data_73_V_d1, + data_73_V_q1, + data_73_V_we1, + data_74_V_address0, + data_74_V_ce0, + data_74_V_d0, + data_74_V_q0, + data_74_V_we0, + data_74_V_address1, + data_74_V_ce1, + data_74_V_d1, + data_74_V_q1, + data_74_V_we1, + data_75_V_address0, + data_75_V_ce0, + data_75_V_d0, + data_75_V_q0, + data_75_V_we0, + data_75_V_address1, + data_75_V_ce1, + data_75_V_d1, + data_75_V_q1, + data_75_V_we1, + data_76_V_address0, + data_76_V_ce0, + data_76_V_d0, + data_76_V_q0, + data_76_V_we0, + data_76_V_address1, + data_76_V_ce1, + data_76_V_d1, + data_76_V_q1, + data_76_V_we1, + data_77_V_address0, + data_77_V_ce0, + data_77_V_d0, + data_77_V_q0, + data_77_V_we0, + data_77_V_address1, + data_77_V_ce1, + data_77_V_d1, + data_77_V_q1, + data_77_V_we1, + data_78_V_address0, + data_78_V_ce0, + data_78_V_d0, + data_78_V_q0, + data_78_V_we0, + data_78_V_address1, + data_78_V_ce1, + data_78_V_d1, + data_78_V_q1, + data_78_V_we1, + data_79_V_address0, + data_79_V_ce0, + data_79_V_d0, + data_79_V_q0, + data_79_V_we0, + data_79_V_address1, + data_79_V_ce1, + data_79_V_d1, + data_79_V_q1, + data_79_V_we1, + data_80_V_address0, + data_80_V_ce0, + data_80_V_d0, + data_80_V_q0, + data_80_V_we0, + data_80_V_address1, + data_80_V_ce1, + data_80_V_d1, + data_80_V_q1, + data_80_V_we1, + data_81_V_address0, + data_81_V_ce0, + data_81_V_d0, + data_81_V_q0, + data_81_V_we0, + data_81_V_address1, + data_81_V_ce1, + data_81_V_d1, + data_81_V_q1, + data_81_V_we1, + data_82_V_address0, + data_82_V_ce0, + data_82_V_d0, + data_82_V_q0, + data_82_V_we0, + data_82_V_address1, + data_82_V_ce1, + data_82_V_d1, + data_82_V_q1, + data_82_V_we1, + data_83_V_address0, + data_83_V_ce0, + data_83_V_d0, + data_83_V_q0, + data_83_V_we0, + data_83_V_address1, + data_83_V_ce1, + data_83_V_d1, + data_83_V_q1, + data_83_V_we1, + data_84_V_address0, + data_84_V_ce0, + data_84_V_d0, + data_84_V_q0, + data_84_V_we0, + data_84_V_address1, + data_84_V_ce1, + data_84_V_d1, + data_84_V_q1, + data_84_V_we1, + data_85_V_address0, + data_85_V_ce0, + data_85_V_d0, + data_85_V_q0, + data_85_V_we0, + data_85_V_address1, + data_85_V_ce1, + data_85_V_d1, + data_85_V_q1, + data_85_V_we1, + data_86_V_address0, + data_86_V_ce0, + data_86_V_d0, + data_86_V_q0, + data_86_V_we0, + data_86_V_address1, + data_86_V_ce1, + data_86_V_d1, + data_86_V_q1, + data_86_V_we1, + data_87_V_address0, + data_87_V_ce0, + data_87_V_d0, + data_87_V_q0, + data_87_V_we0, + data_87_V_address1, + data_87_V_ce1, + data_87_V_d1, + data_87_V_q1, + data_87_V_we1, + data_88_V_address0, + data_88_V_ce0, + data_88_V_d0, + data_88_V_q0, + data_88_V_we0, + data_88_V_address1, + data_88_V_ce1, + data_88_V_d1, + data_88_V_q1, + data_88_V_we1, + data_89_V_address0, + data_89_V_ce0, + data_89_V_d0, + data_89_V_q0, + data_89_V_we0, + data_89_V_address1, + data_89_V_ce1, + data_89_V_d1, + data_89_V_q1, + data_89_V_we1, + data_90_V_address0, + data_90_V_ce0, + data_90_V_d0, + data_90_V_q0, + data_90_V_we0, + data_90_V_address1, + data_90_V_ce1, + data_90_V_d1, + data_90_V_q1, + data_90_V_we1, + data_91_V_address0, + data_91_V_ce0, + data_91_V_d0, + data_91_V_q0, + data_91_V_we0, + data_91_V_address1, + data_91_V_ce1, + data_91_V_d1, + data_91_V_q1, + data_91_V_we1, + data_92_V_address0, + data_92_V_ce0, + data_92_V_d0, + data_92_V_q0, + data_92_V_we0, + data_92_V_address1, + data_92_V_ce1, + data_92_V_d1, + data_92_V_q1, + data_92_V_we1, + data_93_V_address0, + data_93_V_ce0, + data_93_V_d0, + data_93_V_q0, + data_93_V_we0, + data_93_V_address1, + data_93_V_ce1, + data_93_V_d1, + data_93_V_q1, + data_93_V_we1, + data_94_V_address0, + data_94_V_ce0, + data_94_V_d0, + data_94_V_q0, + data_94_V_we0, + data_94_V_address1, + data_94_V_ce1, + data_94_V_d1, + data_94_V_q1, + data_94_V_we1, + data_95_V_address0, + data_95_V_ce0, + data_95_V_d0, + data_95_V_q0, + data_95_V_we0, + data_95_V_address1, + data_95_V_ce1, + data_95_V_d1, + data_95_V_q1, + data_95_V_we1, + data_96_V_address0, + data_96_V_ce0, + data_96_V_d0, + data_96_V_q0, + data_96_V_we0, + data_96_V_address1, + data_96_V_ce1, + data_96_V_d1, + data_96_V_q1, + data_96_V_we1, + data_97_V_address0, + data_97_V_ce0, + data_97_V_d0, + data_97_V_q0, + data_97_V_we0, + data_97_V_address1, + data_97_V_ce1, + data_97_V_d1, + data_97_V_q1, + data_97_V_we1, + data_98_V_address0, + data_98_V_ce0, + data_98_V_d0, + data_98_V_q0, + data_98_V_we0, + data_98_V_address1, + data_98_V_ce1, + data_98_V_d1, + data_98_V_q1, + data_98_V_we1, + data_99_V_address0, + data_99_V_ce0, + data_99_V_d0, + data_99_V_q0, + data_99_V_we0, + data_99_V_address1, + data_99_V_ce1, + data_99_V_d1, + data_99_V_q1, + data_99_V_we1, + data_100_V_address0, + data_100_V_ce0, + data_100_V_d0, + data_100_V_q0, + data_100_V_we0, + data_100_V_address1, + data_100_V_ce1, + data_100_V_d1, + data_100_V_q1, + data_100_V_we1, + data_101_V_address0, + data_101_V_ce0, + data_101_V_d0, + data_101_V_q0, + data_101_V_we0, + data_101_V_address1, + data_101_V_ce1, + data_101_V_d1, + data_101_V_q1, + data_101_V_we1, + data_102_V_address0, + data_102_V_ce0, + data_102_V_d0, + data_102_V_q0, + data_102_V_we0, + data_102_V_address1, + data_102_V_ce1, + data_102_V_d1, + data_102_V_q1, + data_102_V_we1, + data_103_V_address0, + data_103_V_ce0, + data_103_V_d0, + data_103_V_q0, + data_103_V_we0, + data_103_V_address1, + data_103_V_ce1, + data_103_V_d1, + data_103_V_q1, + data_103_V_we1, + data_104_V_address0, + data_104_V_ce0, + data_104_V_d0, + data_104_V_q0, + data_104_V_we0, + data_104_V_address1, + data_104_V_ce1, + data_104_V_d1, + data_104_V_q1, + data_104_V_we1, + data_105_V_address0, + data_105_V_ce0, + data_105_V_d0, + data_105_V_q0, + data_105_V_we0, + data_105_V_address1, + data_105_V_ce1, + data_105_V_d1, + data_105_V_q1, + data_105_V_we1, + data_106_V_address0, + data_106_V_ce0, + data_106_V_d0, + data_106_V_q0, + data_106_V_we0, + data_106_V_address1, + data_106_V_ce1, + data_106_V_d1, + data_106_V_q1, + data_106_V_we1, + data_107_V_address0, + data_107_V_ce0, + data_107_V_d0, + data_107_V_q0, + data_107_V_we0, + data_107_V_address1, + data_107_V_ce1, + data_107_V_d1, + data_107_V_q1, + data_107_V_we1, + data_108_V_address0, + data_108_V_ce0, + data_108_V_d0, + data_108_V_q0, + data_108_V_we0, + data_108_V_address1, + data_108_V_ce1, + data_108_V_d1, + data_108_V_q1, + data_108_V_we1, + data_109_V_address0, + data_109_V_ce0, + data_109_V_d0, + data_109_V_q0, + data_109_V_we0, + data_109_V_address1, + data_109_V_ce1, + data_109_V_d1, + data_109_V_q1, + data_109_V_we1, + data_110_V_address0, + data_110_V_ce0, + data_110_V_d0, + data_110_V_q0, + data_110_V_we0, + data_110_V_address1, + data_110_V_ce1, + data_110_V_d1, + data_110_V_q1, + data_110_V_we1, + data_111_V_address0, + data_111_V_ce0, + data_111_V_d0, + data_111_V_q0, + data_111_V_we0, + data_111_V_address1, + data_111_V_ce1, + data_111_V_d1, + data_111_V_q1, + data_111_V_we1, + data_112_V_address0, + data_112_V_ce0, + data_112_V_d0, + data_112_V_q0, + data_112_V_we0, + data_112_V_address1, + data_112_V_ce1, + data_112_V_d1, + data_112_V_q1, + data_112_V_we1, + data_113_V_address0, + data_113_V_ce0, + data_113_V_d0, + data_113_V_q0, + data_113_V_we0, + data_113_V_address1, + data_113_V_ce1, + data_113_V_d1, + data_113_V_q1, + data_113_V_we1, + data_114_V_address0, + data_114_V_ce0, + data_114_V_d0, + data_114_V_q0, + data_114_V_we0, + data_114_V_address1, + data_114_V_ce1, + data_114_V_d1, + data_114_V_q1, + data_114_V_we1, + data_115_V_address0, + data_115_V_ce0, + data_115_V_d0, + data_115_V_q0, + data_115_V_we0, + data_115_V_address1, + data_115_V_ce1, + data_115_V_d1, + data_115_V_q1, + data_115_V_we1, + data_116_V_address0, + data_116_V_ce0, + data_116_V_d0, + data_116_V_q0, + data_116_V_we0, + data_116_V_address1, + data_116_V_ce1, + data_116_V_d1, + data_116_V_q1, + data_116_V_we1, + data_117_V_address0, + data_117_V_ce0, + data_117_V_d0, + data_117_V_q0, + data_117_V_we0, + data_117_V_address1, + data_117_V_ce1, + data_117_V_d1, + data_117_V_q1, + data_117_V_we1, + data_118_V_address0, + data_118_V_ce0, + data_118_V_d0, + data_118_V_q0, + data_118_V_we0, + data_118_V_address1, + data_118_V_ce1, + data_118_V_d1, + data_118_V_q1, + data_118_V_we1, + data_119_V_address0, + data_119_V_ce0, + data_119_V_d0, + data_119_V_q0, + data_119_V_we0, + data_119_V_address1, + data_119_V_ce1, + data_119_V_d1, + data_119_V_q1, + data_119_V_we1, + data_120_V_address0, + data_120_V_ce0, + data_120_V_d0, + data_120_V_q0, + data_120_V_we0, + data_120_V_address1, + data_120_V_ce1, + data_120_V_d1, + data_120_V_q1, + data_120_V_we1, + data_121_V_address0, + data_121_V_ce0, + data_121_V_d0, + data_121_V_q0, + data_121_V_we0, + data_121_V_address1, + data_121_V_ce1, + data_121_V_d1, + data_121_V_q1, + data_121_V_we1, + data_122_V_address0, + data_122_V_ce0, + data_122_V_d0, + data_122_V_q0, + data_122_V_we0, + data_122_V_address1, + data_122_V_ce1, + data_122_V_d1, + data_122_V_q1, + data_122_V_we1, + data_123_V_address0, + data_123_V_ce0, + data_123_V_d0, + data_123_V_q0, + data_123_V_we0, + data_123_V_address1, + data_123_V_ce1, + data_123_V_d1, + data_123_V_q1, + data_123_V_we1, + data_124_V_address0, + data_124_V_ce0, + data_124_V_d0, + data_124_V_q0, + data_124_V_we0, + data_124_V_address1, + data_124_V_ce1, + data_124_V_d1, + data_124_V_q1, + data_124_V_we1, + data_125_V_address0, + data_125_V_ce0, + data_125_V_d0, + data_125_V_q0, + data_125_V_we0, + data_125_V_address1, + data_125_V_ce1, + data_125_V_d1, + data_125_V_q1, + data_125_V_we1, + data_126_V_address0, + data_126_V_ce0, + data_126_V_d0, + data_126_V_q0, + data_126_V_we0, + data_126_V_address1, + data_126_V_ce1, + data_126_V_d1, + data_126_V_q1, + data_126_V_we1, + data_127_V_address0, + data_127_V_ce0, + data_127_V_d0, + data_127_V_q0, + data_127_V_we0, + data_127_V_address1, + data_127_V_ce1, + data_127_V_d1, + data_127_V_q1, + data_127_V_we1, + res_0_V, + res_1_V, + res_2_V, + res_3_V, + res_4_V, + res_5_V, + res_6_V, + res_7_V, + res_8_V, + res_9_V, + ap_clk, + ap_rst, + ap_start, + res_0_V_ap_vld, + ap_done, + res_1_V_ap_vld, + res_2_V_ap_vld, + res_3_V_ap_vld, + res_4_V_ap_vld, + res_5_V_ap_vld, + res_6_V_ap_vld, + res_7_V_ap_vld, + res_8_V_ap_vld, + res_9_V_ap_vld, + ap_ready, + ap_idle, + ap_continue +); + + +output [2:0] data_0_V_address0; +output data_0_V_ce0; +output [7:0] data_0_V_d0; +input [7:0] data_0_V_q0; +output data_0_V_we0; +output [2:0] data_0_V_address1; +output data_0_V_ce1; +output [7:0] data_0_V_d1; +input [7:0] data_0_V_q1; +output data_0_V_we1; +output [2:0] data_1_V_address0; +output data_1_V_ce0; +output [7:0] data_1_V_d0; +input [7:0] data_1_V_q0; +output data_1_V_we0; +output [2:0] data_1_V_address1; +output data_1_V_ce1; +output [7:0] data_1_V_d1; +input [7:0] data_1_V_q1; +output data_1_V_we1; +output [2:0] data_2_V_address0; +output data_2_V_ce0; +output [7:0] data_2_V_d0; +input [7:0] data_2_V_q0; +output data_2_V_we0; +output [2:0] data_2_V_address1; +output data_2_V_ce1; +output [7:0] data_2_V_d1; +input [7:0] data_2_V_q1; +output data_2_V_we1; +output [2:0] data_3_V_address0; +output data_3_V_ce0; +output [7:0] data_3_V_d0; +input [7:0] data_3_V_q0; +output data_3_V_we0; +output [2:0] data_3_V_address1; +output data_3_V_ce1; +output [7:0] data_3_V_d1; +input [7:0] data_3_V_q1; +output data_3_V_we1; +output [2:0] data_4_V_address0; +output data_4_V_ce0; +output [7:0] data_4_V_d0; +input [7:0] data_4_V_q0; +output data_4_V_we0; +output [2:0] data_4_V_address1; +output data_4_V_ce1; +output [7:0] data_4_V_d1; +input [7:0] data_4_V_q1; +output data_4_V_we1; +output [2:0] data_5_V_address0; +output data_5_V_ce0; +output [7:0] data_5_V_d0; +input [7:0] data_5_V_q0; +output data_5_V_we0; +output [2:0] data_5_V_address1; +output data_5_V_ce1; +output [7:0] data_5_V_d1; +input [7:0] data_5_V_q1; +output data_5_V_we1; +output [2:0] data_6_V_address0; +output data_6_V_ce0; +output [7:0] data_6_V_d0; +input [7:0] data_6_V_q0; +output data_6_V_we0; +output [2:0] data_6_V_address1; +output data_6_V_ce1; +output [7:0] data_6_V_d1; +input [7:0] data_6_V_q1; +output data_6_V_we1; +output [2:0] data_7_V_address0; +output data_7_V_ce0; +output [7:0] data_7_V_d0; +input [7:0] data_7_V_q0; +output data_7_V_we0; +output [2:0] data_7_V_address1; +output data_7_V_ce1; +output [7:0] data_7_V_d1; +input [7:0] data_7_V_q1; +output data_7_V_we1; +output [2:0] data_8_V_address0; +output data_8_V_ce0; +output [7:0] data_8_V_d0; +input [7:0] data_8_V_q0; +output data_8_V_we0; +output [2:0] data_8_V_address1; +output data_8_V_ce1; +output [7:0] data_8_V_d1; +input [7:0] data_8_V_q1; +output data_8_V_we1; +output [2:0] data_9_V_address0; +output data_9_V_ce0; +output [7:0] data_9_V_d0; +input [7:0] data_9_V_q0; +output data_9_V_we0; +output [2:0] data_9_V_address1; +output data_9_V_ce1; +output [7:0] data_9_V_d1; +input [7:0] data_9_V_q1; +output data_9_V_we1; +output [2:0] data_10_V_address0; +output data_10_V_ce0; +output [7:0] data_10_V_d0; +input [7:0] data_10_V_q0; +output data_10_V_we0; +output [2:0] data_10_V_address1; +output data_10_V_ce1; +output [7:0] data_10_V_d1; +input [7:0] data_10_V_q1; +output data_10_V_we1; +output [2:0] data_11_V_address0; +output data_11_V_ce0; +output [7:0] data_11_V_d0; +input [7:0] data_11_V_q0; +output data_11_V_we0; +output [2:0] data_11_V_address1; +output data_11_V_ce1; +output [7:0] data_11_V_d1; +input [7:0] data_11_V_q1; +output data_11_V_we1; +output [2:0] data_12_V_address0; +output data_12_V_ce0; +output [7:0] data_12_V_d0; +input [7:0] data_12_V_q0; +output data_12_V_we0; +output [2:0] data_12_V_address1; +output data_12_V_ce1; +output [7:0] data_12_V_d1; +input [7:0] data_12_V_q1; +output data_12_V_we1; +output [2:0] data_13_V_address0; +output data_13_V_ce0; +output [7:0] data_13_V_d0; +input [7:0] data_13_V_q0; +output data_13_V_we0; +output [2:0] data_13_V_address1; +output data_13_V_ce1; +output [7:0] data_13_V_d1; +input [7:0] data_13_V_q1; +output data_13_V_we1; +output [2:0] data_14_V_address0; +output data_14_V_ce0; +output [7:0] data_14_V_d0; +input [7:0] data_14_V_q0; +output data_14_V_we0; +output [2:0] data_14_V_address1; +output data_14_V_ce1; +output [7:0] data_14_V_d1; +input [7:0] data_14_V_q1; +output data_14_V_we1; +output [2:0] data_15_V_address0; +output data_15_V_ce0; +output [7:0] data_15_V_d0; +input [7:0] data_15_V_q0; +output data_15_V_we0; +output [2:0] data_15_V_address1; +output data_15_V_ce1; +output [7:0] data_15_V_d1; +input [7:0] data_15_V_q1; +output data_15_V_we1; +output [2:0] data_16_V_address0; +output data_16_V_ce0; +output [7:0] data_16_V_d0; +input [7:0] data_16_V_q0; +output data_16_V_we0; +output [2:0] data_16_V_address1; +output data_16_V_ce1; +output [7:0] data_16_V_d1; +input [7:0] data_16_V_q1; +output data_16_V_we1; +output [2:0] data_17_V_address0; +output data_17_V_ce0; +output [7:0] data_17_V_d0; +input [7:0] data_17_V_q0; +output data_17_V_we0; +output [2:0] data_17_V_address1; +output data_17_V_ce1; +output [7:0] data_17_V_d1; +input [7:0] data_17_V_q1; +output data_17_V_we1; +output [2:0] data_18_V_address0; +output data_18_V_ce0; +output [7:0] data_18_V_d0; +input [7:0] data_18_V_q0; +output data_18_V_we0; +output [2:0] data_18_V_address1; +output data_18_V_ce1; +output [7:0] data_18_V_d1; +input [7:0] data_18_V_q1; +output data_18_V_we1; +output [2:0] data_19_V_address0; +output data_19_V_ce0; +output [7:0] data_19_V_d0; +input [7:0] data_19_V_q0; +output data_19_V_we0; +output [2:0] data_19_V_address1; +output data_19_V_ce1; +output [7:0] data_19_V_d1; +input [7:0] data_19_V_q1; +output data_19_V_we1; +output [2:0] data_20_V_address0; +output data_20_V_ce0; +output [7:0] data_20_V_d0; +input [7:0] data_20_V_q0; +output data_20_V_we0; +output [2:0] data_20_V_address1; +output data_20_V_ce1; +output [7:0] data_20_V_d1; +input [7:0] data_20_V_q1; +output data_20_V_we1; +output [2:0] data_21_V_address0; +output data_21_V_ce0; +output [7:0] data_21_V_d0; +input [7:0] data_21_V_q0; +output data_21_V_we0; +output [2:0] data_21_V_address1; +output data_21_V_ce1; +output [7:0] data_21_V_d1; +input [7:0] data_21_V_q1; +output data_21_V_we1; +output [2:0] data_22_V_address0; +output data_22_V_ce0; +output [7:0] data_22_V_d0; +input [7:0] data_22_V_q0; +output data_22_V_we0; +output [2:0] data_22_V_address1; +output data_22_V_ce1; +output [7:0] data_22_V_d1; +input [7:0] data_22_V_q1; +output data_22_V_we1; +output [2:0] data_23_V_address0; +output data_23_V_ce0; +output [7:0] data_23_V_d0; +input [7:0] data_23_V_q0; +output data_23_V_we0; +output [2:0] data_23_V_address1; +output data_23_V_ce1; +output [7:0] data_23_V_d1; +input [7:0] data_23_V_q1; +output data_23_V_we1; +output [2:0] data_24_V_address0; +output data_24_V_ce0; +output [7:0] data_24_V_d0; +input [7:0] data_24_V_q0; +output data_24_V_we0; +output [2:0] data_24_V_address1; +output data_24_V_ce1; +output [7:0] data_24_V_d1; +input [7:0] data_24_V_q1; +output data_24_V_we1; +output [2:0] data_25_V_address0; +output data_25_V_ce0; +output [7:0] data_25_V_d0; +input [7:0] data_25_V_q0; +output data_25_V_we0; +output [2:0] data_25_V_address1; +output data_25_V_ce1; +output [7:0] data_25_V_d1; +input [7:0] data_25_V_q1; +output data_25_V_we1; +output [2:0] data_26_V_address0; +output data_26_V_ce0; +output [7:0] data_26_V_d0; +input [7:0] data_26_V_q0; +output data_26_V_we0; +output [2:0] data_26_V_address1; +output data_26_V_ce1; +output [7:0] data_26_V_d1; +input [7:0] data_26_V_q1; +output data_26_V_we1; +output [2:0] data_27_V_address0; +output data_27_V_ce0; +output [7:0] data_27_V_d0; +input [7:0] data_27_V_q0; +output data_27_V_we0; +output [2:0] data_27_V_address1; +output data_27_V_ce1; +output [7:0] data_27_V_d1; +input [7:0] data_27_V_q1; +output data_27_V_we1; +output [2:0] data_28_V_address0; +output data_28_V_ce0; +output [7:0] data_28_V_d0; +input [7:0] data_28_V_q0; +output data_28_V_we0; +output [2:0] data_28_V_address1; +output data_28_V_ce1; +output [7:0] data_28_V_d1; +input [7:0] data_28_V_q1; +output data_28_V_we1; +output [2:0] data_29_V_address0; +output data_29_V_ce0; +output [7:0] data_29_V_d0; +input [7:0] data_29_V_q0; +output data_29_V_we0; +output [2:0] data_29_V_address1; +output data_29_V_ce1; +output [7:0] data_29_V_d1; +input [7:0] data_29_V_q1; +output data_29_V_we1; +output [2:0] data_30_V_address0; +output data_30_V_ce0; +output [7:0] data_30_V_d0; +input [7:0] data_30_V_q0; +output data_30_V_we0; +output [2:0] data_30_V_address1; +output data_30_V_ce1; +output [7:0] data_30_V_d1; +input [7:0] data_30_V_q1; +output data_30_V_we1; +output [2:0] data_31_V_address0; +output data_31_V_ce0; +output [7:0] data_31_V_d0; +input [7:0] data_31_V_q0; +output data_31_V_we0; +output [2:0] data_31_V_address1; +output data_31_V_ce1; +output [7:0] data_31_V_d1; +input [7:0] data_31_V_q1; +output data_31_V_we1; +output [2:0] data_32_V_address0; +output data_32_V_ce0; +output [7:0] data_32_V_d0; +input [7:0] data_32_V_q0; +output data_32_V_we0; +output [2:0] data_32_V_address1; +output data_32_V_ce1; +output [7:0] data_32_V_d1; +input [7:0] data_32_V_q1; +output data_32_V_we1; +output [2:0] data_33_V_address0; +output data_33_V_ce0; +output [7:0] data_33_V_d0; +input [7:0] data_33_V_q0; +output data_33_V_we0; +output [2:0] data_33_V_address1; +output data_33_V_ce1; +output [7:0] data_33_V_d1; +input [7:0] data_33_V_q1; +output data_33_V_we1; +output [2:0] data_34_V_address0; +output data_34_V_ce0; +output [7:0] data_34_V_d0; +input [7:0] data_34_V_q0; +output data_34_V_we0; +output [2:0] data_34_V_address1; +output data_34_V_ce1; +output [7:0] data_34_V_d1; +input [7:0] data_34_V_q1; +output data_34_V_we1; +output [2:0] data_35_V_address0; +output data_35_V_ce0; +output [7:0] data_35_V_d0; +input [7:0] data_35_V_q0; +output data_35_V_we0; +output [2:0] data_35_V_address1; +output data_35_V_ce1; +output [7:0] data_35_V_d1; +input [7:0] data_35_V_q1; +output data_35_V_we1; +output [2:0] data_36_V_address0; +output data_36_V_ce0; +output [7:0] data_36_V_d0; +input [7:0] data_36_V_q0; +output data_36_V_we0; +output [2:0] data_36_V_address1; +output data_36_V_ce1; +output [7:0] data_36_V_d1; +input [7:0] data_36_V_q1; +output data_36_V_we1; +output [2:0] data_37_V_address0; +output data_37_V_ce0; +output [7:0] data_37_V_d0; +input [7:0] data_37_V_q0; +output data_37_V_we0; +output [2:0] data_37_V_address1; +output data_37_V_ce1; +output [7:0] data_37_V_d1; +input [7:0] data_37_V_q1; +output data_37_V_we1; +output [2:0] data_38_V_address0; +output data_38_V_ce0; +output [7:0] data_38_V_d0; +input [7:0] data_38_V_q0; +output data_38_V_we0; +output [2:0] data_38_V_address1; +output data_38_V_ce1; +output [7:0] data_38_V_d1; +input [7:0] data_38_V_q1; +output data_38_V_we1; +output [2:0] data_39_V_address0; +output data_39_V_ce0; +output [7:0] data_39_V_d0; +input [7:0] data_39_V_q0; +output data_39_V_we0; +output [2:0] data_39_V_address1; +output data_39_V_ce1; +output [7:0] data_39_V_d1; +input [7:0] data_39_V_q1; +output data_39_V_we1; +output [2:0] data_40_V_address0; +output data_40_V_ce0; +output [7:0] data_40_V_d0; +input [7:0] data_40_V_q0; +output data_40_V_we0; +output [2:0] data_40_V_address1; +output data_40_V_ce1; +output [7:0] data_40_V_d1; +input [7:0] data_40_V_q1; +output data_40_V_we1; +output [2:0] data_41_V_address0; +output data_41_V_ce0; +output [7:0] data_41_V_d0; +input [7:0] data_41_V_q0; +output data_41_V_we0; +output [2:0] data_41_V_address1; +output data_41_V_ce1; +output [7:0] data_41_V_d1; +input [7:0] data_41_V_q1; +output data_41_V_we1; +output [2:0] data_42_V_address0; +output data_42_V_ce0; +output [7:0] data_42_V_d0; +input [7:0] data_42_V_q0; +output data_42_V_we0; +output [2:0] data_42_V_address1; +output data_42_V_ce1; +output [7:0] data_42_V_d1; +input [7:0] data_42_V_q1; +output data_42_V_we1; +output [2:0] data_43_V_address0; +output data_43_V_ce0; +output [7:0] data_43_V_d0; +input [7:0] data_43_V_q0; +output data_43_V_we0; +output [2:0] data_43_V_address1; +output data_43_V_ce1; +output [7:0] data_43_V_d1; +input [7:0] data_43_V_q1; +output data_43_V_we1; +output [2:0] data_44_V_address0; +output data_44_V_ce0; +output [7:0] data_44_V_d0; +input [7:0] data_44_V_q0; +output data_44_V_we0; +output [2:0] data_44_V_address1; +output data_44_V_ce1; +output [7:0] data_44_V_d1; +input [7:0] data_44_V_q1; +output data_44_V_we1; +output [2:0] data_45_V_address0; +output data_45_V_ce0; +output [7:0] data_45_V_d0; +input [7:0] data_45_V_q0; +output data_45_V_we0; +output [2:0] data_45_V_address1; +output data_45_V_ce1; +output [7:0] data_45_V_d1; +input [7:0] data_45_V_q1; +output data_45_V_we1; +output [2:0] data_46_V_address0; +output data_46_V_ce0; +output [7:0] data_46_V_d0; +input [7:0] data_46_V_q0; +output data_46_V_we0; +output [2:0] data_46_V_address1; +output data_46_V_ce1; +output [7:0] data_46_V_d1; +input [7:0] data_46_V_q1; +output data_46_V_we1; +output [2:0] data_47_V_address0; +output data_47_V_ce0; +output [7:0] data_47_V_d0; +input [7:0] data_47_V_q0; +output data_47_V_we0; +output [2:0] data_47_V_address1; +output data_47_V_ce1; +output [7:0] data_47_V_d1; +input [7:0] data_47_V_q1; +output data_47_V_we1; +output [2:0] data_48_V_address0; +output data_48_V_ce0; +output [7:0] data_48_V_d0; +input [7:0] data_48_V_q0; +output data_48_V_we0; +output [2:0] data_48_V_address1; +output data_48_V_ce1; +output [7:0] data_48_V_d1; +input [7:0] data_48_V_q1; +output data_48_V_we1; +output [2:0] data_49_V_address0; +output data_49_V_ce0; +output [7:0] data_49_V_d0; +input [7:0] data_49_V_q0; +output data_49_V_we0; +output [2:0] data_49_V_address1; +output data_49_V_ce1; +output [7:0] data_49_V_d1; +input [7:0] data_49_V_q1; +output data_49_V_we1; +output [2:0] data_50_V_address0; +output data_50_V_ce0; +output [7:0] data_50_V_d0; +input [7:0] data_50_V_q0; +output data_50_V_we0; +output [2:0] data_50_V_address1; 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data_61_V_ce1; +output [7:0] data_61_V_d1; +input [7:0] data_61_V_q1; +output data_61_V_we1; +output [2:0] data_62_V_address0; +output data_62_V_ce0; +output [7:0] data_62_V_d0; +input [7:0] data_62_V_q0; +output data_62_V_we0; +output [2:0] data_62_V_address1; +output data_62_V_ce1; +output [7:0] data_62_V_d1; +input [7:0] data_62_V_q1; +output data_62_V_we1; +output [2:0] data_63_V_address0; +output data_63_V_ce0; +output [7:0] data_63_V_d0; +input [7:0] data_63_V_q0; +output data_63_V_we0; +output [2:0] data_63_V_address1; +output data_63_V_ce1; +output [7:0] data_63_V_d1; +input [7:0] data_63_V_q1; +output data_63_V_we1; +output [2:0] data_64_V_address0; +output data_64_V_ce0; +output [7:0] data_64_V_d0; +input [7:0] data_64_V_q0; +output data_64_V_we0; +output [2:0] data_64_V_address1; +output data_64_V_ce1; +output [7:0] data_64_V_d1; +input [7:0] data_64_V_q1; +output data_64_V_we1; +output [2:0] data_65_V_address0; +output data_65_V_ce0; +output [7:0] data_65_V_d0; +input [7:0] data_65_V_q0; +output data_65_V_we0; +output [2:0] data_65_V_address1; +output data_65_V_ce1; +output [7:0] data_65_V_d1; +input [7:0] data_65_V_q1; +output data_65_V_we1; +output [2:0] data_66_V_address0; +output data_66_V_ce0; +output [7:0] data_66_V_d0; +input [7:0] data_66_V_q0; +output data_66_V_we0; +output [2:0] data_66_V_address1; +output data_66_V_ce1; +output [7:0] data_66_V_d1; +input [7:0] data_66_V_q1; +output data_66_V_we1; +output [2:0] data_67_V_address0; +output data_67_V_ce0; +output [7:0] data_67_V_d0; +input [7:0] data_67_V_q0; +output data_67_V_we0; +output [2:0] data_67_V_address1; +output data_67_V_ce1; +output [7:0] data_67_V_d1; +input [7:0] data_67_V_q1; +output data_67_V_we1; +output [2:0] data_68_V_address0; +output data_68_V_ce0; +output [7:0] data_68_V_d0; +input [7:0] data_68_V_q0; +output data_68_V_we0; +output [2:0] data_68_V_address1; +output data_68_V_ce1; +output [7:0] data_68_V_d1; +input [7:0] data_68_V_q1; +output data_68_V_we1; +output [2:0] data_69_V_address0; +output data_69_V_ce0; +output [7:0] data_69_V_d0; +input [7:0] data_69_V_q0; +output data_69_V_we0; +output [2:0] data_69_V_address1; +output data_69_V_ce1; +output [7:0] data_69_V_d1; +input [7:0] data_69_V_q1; +output data_69_V_we1; +output [2:0] data_70_V_address0; +output data_70_V_ce0; +output [7:0] data_70_V_d0; +input [7:0] data_70_V_q0; +output data_70_V_we0; +output [2:0] data_70_V_address1; +output data_70_V_ce1; +output [7:0] data_70_V_d1; +input [7:0] data_70_V_q1; +output data_70_V_we1; +output [2:0] data_71_V_address0; +output data_71_V_ce0; +output [7:0] data_71_V_d0; +input [7:0] data_71_V_q0; +output data_71_V_we0; +output [2:0] data_71_V_address1; +output data_71_V_ce1; +output [7:0] data_71_V_d1; +input [7:0] data_71_V_q1; +output data_71_V_we1; +output [2:0] data_72_V_address0; +output data_72_V_ce0; +output [7:0] data_72_V_d0; +input [7:0] data_72_V_q0; +output data_72_V_we0; +output [2:0] data_72_V_address1; +output data_72_V_ce1; +output [7:0] data_72_V_d1; +input [7:0] data_72_V_q1; +output data_72_V_we1; +output [2:0] data_73_V_address0; +output data_73_V_ce0; +output [7:0] data_73_V_d0; +input [7:0] data_73_V_q0; +output data_73_V_we0; +output [2:0] data_73_V_address1; +output data_73_V_ce1; +output [7:0] data_73_V_d1; +input [7:0] data_73_V_q1; +output data_73_V_we1; +output [2:0] data_74_V_address0; +output data_74_V_ce0; +output [7:0] data_74_V_d0; +input [7:0] data_74_V_q0; +output data_74_V_we0; +output [2:0] data_74_V_address1; +output data_74_V_ce1; +output [7:0] data_74_V_d1; +input [7:0] data_74_V_q1; +output data_74_V_we1; +output [2:0] data_75_V_address0; +output data_75_V_ce0; +output [7:0] data_75_V_d0; +input [7:0] data_75_V_q0; +output data_75_V_we0; +output [2:0] data_75_V_address1; +output data_75_V_ce1; +output [7:0] data_75_V_d1; +input [7:0] data_75_V_q1; +output data_75_V_we1; +output [1:0] data_76_V_address0; +output data_76_V_ce0; +output [7:0] data_76_V_d0; +input [7:0] data_76_V_q0; +output data_76_V_we0; +output [1:0] data_76_V_address1; +output data_76_V_ce1; +output [7:0] data_76_V_d1; +input [7:0] data_76_V_q1; +output data_76_V_we1; +output [1:0] data_77_V_address0; +output data_77_V_ce0; +output [7:0] data_77_V_d0; +input [7:0] data_77_V_q0; +output data_77_V_we0; +output [1:0] data_77_V_address1; +output data_77_V_ce1; +output [7:0] data_77_V_d1; +input [7:0] data_77_V_q1; +output data_77_V_we1; +output [1:0] data_78_V_address0; +output data_78_V_ce0; +output [7:0] data_78_V_d0; +input [7:0] data_78_V_q0; +output data_78_V_we0; +output [1:0] data_78_V_address1; +output data_78_V_ce1; +output [7:0] data_78_V_d1; +input [7:0] data_78_V_q1; +output data_78_V_we1; +output [1:0] data_79_V_address0; +output data_79_V_ce0; +output [7:0] data_79_V_d0; +input [7:0] data_79_V_q0; +output data_79_V_we0; +output [1:0] data_79_V_address1; +output data_79_V_ce1; +output [7:0] data_79_V_d1; +input [7:0] data_79_V_q1; +output data_79_V_we1; +output [1:0] data_80_V_address0; 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data_91_V_ce0; +output [7:0] data_91_V_d0; +input [7:0] data_91_V_q0; +output data_91_V_we0; +output [1:0] data_91_V_address1; +output data_91_V_ce1; +output [7:0] data_91_V_d1; +input [7:0] data_91_V_q1; +output data_91_V_we1; +output [1:0] data_92_V_address0; +output data_92_V_ce0; +output [7:0] data_92_V_d0; +input [7:0] data_92_V_q0; +output data_92_V_we0; +output [1:0] data_92_V_address1; +output data_92_V_ce1; +output [7:0] data_92_V_d1; +input [7:0] data_92_V_q1; +output data_92_V_we1; +output [1:0] data_93_V_address0; +output data_93_V_ce0; +output [7:0] data_93_V_d0; +input [7:0] data_93_V_q0; +output data_93_V_we0; +output [1:0] data_93_V_address1; +output data_93_V_ce1; +output [7:0] data_93_V_d1; +input [7:0] data_93_V_q1; +output data_93_V_we1; +output [1:0] data_94_V_address0; +output data_94_V_ce0; +output [7:0] data_94_V_d0; +input [7:0] data_94_V_q0; +output data_94_V_we0; +output [1:0] data_94_V_address1; +output data_94_V_ce1; +output [7:0] data_94_V_d1; +input [7:0] data_94_V_q1; +output data_94_V_we1; +output [1:0] data_95_V_address0; +output data_95_V_ce0; +output [7:0] data_95_V_d0; +input [7:0] data_95_V_q0; +output data_95_V_we0; +output [1:0] data_95_V_address1; +output data_95_V_ce1; +output [7:0] data_95_V_d1; +input [7:0] data_95_V_q1; +output data_95_V_we1; +output [1:0] data_96_V_address0; +output data_96_V_ce0; +output [7:0] data_96_V_d0; +input [7:0] data_96_V_q0; +output data_96_V_we0; +output [1:0] data_96_V_address1; +output data_96_V_ce1; +output [7:0] data_96_V_d1; +input [7:0] data_96_V_q1; +output data_96_V_we1; +output [1:0] data_97_V_address0; +output data_97_V_ce0; +output [7:0] data_97_V_d0; +input [7:0] data_97_V_q0; +output data_97_V_we0; +output [1:0] data_97_V_address1; +output data_97_V_ce1; +output [7:0] data_97_V_d1; +input [7:0] data_97_V_q1; +output data_97_V_we1; +output [1:0] data_98_V_address0; +output data_98_V_ce0; +output [7:0] data_98_V_d0; +input [7:0] data_98_V_q0; +output data_98_V_we0; +output [1:0] data_98_V_address1; +output data_98_V_ce1; +output [7:0] data_98_V_d1; +input [7:0] data_98_V_q1; +output data_98_V_we1; +output [1:0] data_99_V_address0; +output data_99_V_ce0; +output [7:0] data_99_V_d0; +input [7:0] data_99_V_q0; +output data_99_V_we0; +output [1:0] data_99_V_address1; +output data_99_V_ce1; +output [7:0] data_99_V_d1; +input [7:0] data_99_V_q1; +output data_99_V_we1; +output [1:0] data_100_V_address0; +output data_100_V_ce0; +output [7:0] data_100_V_d0; +input [7:0] data_100_V_q0; +output data_100_V_we0; +output [1:0] data_100_V_address1; +output data_100_V_ce1; +output [7:0] data_100_V_d1; +input [7:0] data_100_V_q1; +output data_100_V_we1; +output [1:0] data_101_V_address0; +output data_101_V_ce0; +output [7:0] data_101_V_d0; +input [7:0] data_101_V_q0; +output data_101_V_we0; +output [1:0] data_101_V_address1; +output data_101_V_ce1; +output [7:0] data_101_V_d1; +input [7:0] data_101_V_q1; +output data_101_V_we1; +output [1:0] data_102_V_address0; +output data_102_V_ce0; +output [7:0] data_102_V_d0; +input [7:0] data_102_V_q0; +output data_102_V_we0; +output [1:0] data_102_V_address1; +output data_102_V_ce1; +output [7:0] data_102_V_d1; +input [7:0] data_102_V_q1; +output data_102_V_we1; +output [1:0] data_103_V_address0; +output data_103_V_ce0; +output [7:0] data_103_V_d0; +input [7:0] data_103_V_q0; +output data_103_V_we0; +output [1:0] data_103_V_address1; +output data_103_V_ce1; +output [7:0] data_103_V_d1; +input [7:0] data_103_V_q1; +output data_103_V_we1; +output [1:0] data_104_V_address0; +output data_104_V_ce0; +output [7:0] data_104_V_d0; +input [7:0] data_104_V_q0; +output data_104_V_we0; +output [1:0] data_104_V_address1; +output data_104_V_ce1; +output [7:0] data_104_V_d1; +input [7:0] data_104_V_q1; +output data_104_V_we1; +output [1:0] data_105_V_address0; +output data_105_V_ce0; +output [7:0] data_105_V_d0; +input [7:0] data_105_V_q0; +output data_105_V_we0; +output [1:0] data_105_V_address1; +output data_105_V_ce1; +output [7:0] data_105_V_d1; +input [7:0] data_105_V_q1; +output data_105_V_we1; +output [1:0] data_106_V_address0; +output data_106_V_ce0; +output [7:0] data_106_V_d0; +input [7:0] data_106_V_q0; +output data_106_V_we0; +output [1:0] data_106_V_address1; +output data_106_V_ce1; +output [7:0] data_106_V_d1; +input [7:0] data_106_V_q1; +output data_106_V_we1; +output [1:0] data_107_V_address0; +output data_107_V_ce0; +output [7:0] data_107_V_d0; +input [7:0] data_107_V_q0; +output data_107_V_we0; +output [1:0] data_107_V_address1; +output data_107_V_ce1; +output [7:0] data_107_V_d1; +input [7:0] data_107_V_q1; +output data_107_V_we1; +output [1:0] data_108_V_address0; +output data_108_V_ce0; +output [7:0] data_108_V_d0; +input [7:0] data_108_V_q0; +output data_108_V_we0; +output [1:0] data_108_V_address1; +output data_108_V_ce1; +output [7:0] data_108_V_d1; +input [7:0] data_108_V_q1; +output data_108_V_we1; +output [1:0] data_109_V_address0; +output data_109_V_ce0; +output [7:0] data_109_V_d0; +input [7:0] data_109_V_q0; +output data_109_V_we0; +output [1:0] data_109_V_address1; +output data_109_V_ce1; +output [7:0] data_109_V_d1; +input [7:0] data_109_V_q1; +output data_109_V_we1; +output [1:0] data_110_V_address0; +output data_110_V_ce0; +output [7:0] data_110_V_d0; +input [7:0] data_110_V_q0; +output data_110_V_we0; +output [1:0] data_110_V_address1; +output data_110_V_ce1; +output [7:0] data_110_V_d1; +input [7:0] data_110_V_q1; +output data_110_V_we1; +output [1:0] data_111_V_address0; +output data_111_V_ce0; +output [7:0] data_111_V_d0; +input [7:0] data_111_V_q0; +output data_111_V_we0; +output [1:0] data_111_V_address1; +output data_111_V_ce1; +output [7:0] data_111_V_d1; +input [7:0] data_111_V_q1; +output data_111_V_we1; +output [1:0] data_112_V_address0; +output data_112_V_ce0; +output [7:0] data_112_V_d0; +input [7:0] data_112_V_q0; +output data_112_V_we0; +output [1:0] data_112_V_address1; +output data_112_V_ce1; +output [7:0] data_112_V_d1; +input [7:0] data_112_V_q1; +output data_112_V_we1; +output [1:0] data_113_V_address0; +output data_113_V_ce0; +output [7:0] data_113_V_d0; +input [7:0] data_113_V_q0; +output data_113_V_we0; +output [1:0] data_113_V_address1; +output data_113_V_ce1; +output [7:0] data_113_V_d1; +input [7:0] data_113_V_q1; +output data_113_V_we1; +output [1:0] data_114_V_address0; +output data_114_V_ce0; +output [7:0] data_114_V_d0; +input [7:0] data_114_V_q0; +output data_114_V_we0; +output [1:0] data_114_V_address1; +output data_114_V_ce1; +output [7:0] data_114_V_d1; +input [7:0] data_114_V_q1; +output data_114_V_we1; +output [1:0] data_115_V_address0; +output data_115_V_ce0; +output [7:0] data_115_V_d0; +input [7:0] data_115_V_q0; +output data_115_V_we0; +output [1:0] data_115_V_address1; +output data_115_V_ce1; +output [7:0] data_115_V_d1; +input [7:0] data_115_V_q1; +output data_115_V_we1; +output [1:0] data_116_V_address0; +output data_116_V_ce0; +output [7:0] data_116_V_d0; +input [7:0] data_116_V_q0; +output data_116_V_we0; +output [1:0] data_116_V_address1; +output data_116_V_ce1; +output [7:0] data_116_V_d1; +input [7:0] data_116_V_q1; +output data_116_V_we1; +output [1:0] data_117_V_address0; +output data_117_V_ce0; +output [7:0] data_117_V_d0; +input [7:0] data_117_V_q0; +output data_117_V_we0; +output [1:0] data_117_V_address1; +output data_117_V_ce1; +output [7:0] data_117_V_d1; +input [7:0] data_117_V_q1; +output data_117_V_we1; +output [1:0] data_118_V_address0; +output data_118_V_ce0; +output [7:0] data_118_V_d0; +input [7:0] data_118_V_q0; +output data_118_V_we0; +output [1:0] data_118_V_address1; +output data_118_V_ce1; +output [7:0] data_118_V_d1; +input [7:0] data_118_V_q1; +output data_118_V_we1; +output [1:0] data_119_V_address0; +output data_119_V_ce0; +output [7:0] data_119_V_d0; +input [7:0] data_119_V_q0; +output data_119_V_we0; +output [1:0] data_119_V_address1; +output data_119_V_ce1; +output [7:0] data_119_V_d1; +input [7:0] data_119_V_q1; +output data_119_V_we1; +output [1:0] data_120_V_address0; +output data_120_V_ce0; +output [7:0] data_120_V_d0; +input [7:0] data_120_V_q0; +output data_120_V_we0; +output [1:0] data_120_V_address1; +output data_120_V_ce1; +output [7:0] data_120_V_d1; +input [7:0] data_120_V_q1; +output data_120_V_we1; +output [1:0] data_121_V_address0; +output data_121_V_ce0; +output [7:0] data_121_V_d0; +input [7:0] data_121_V_q0; +output data_121_V_we0; +output [1:0] data_121_V_address1; +output data_121_V_ce1; +output [7:0] data_121_V_d1; +input [7:0] data_121_V_q1; +output data_121_V_we1; +output [1:0] data_122_V_address0; +output data_122_V_ce0; +output [7:0] data_122_V_d0; +input [7:0] data_122_V_q0; +output data_122_V_we0; +output [1:0] data_122_V_address1; +output data_122_V_ce1; +output [7:0] data_122_V_d1; +input [7:0] data_122_V_q1; +output data_122_V_we1; +output [1:0] data_123_V_address0; +output data_123_V_ce0; +output [7:0] data_123_V_d0; +input [7:0] data_123_V_q0; +output data_123_V_we0; +output [1:0] data_123_V_address1; +output data_123_V_ce1; +output [7:0] data_123_V_d1; +input [7:0] data_123_V_q1; +output data_123_V_we1; +output [1:0] data_124_V_address0; +output data_124_V_ce0; +output [7:0] data_124_V_d0; +input [7:0] data_124_V_q0; +output data_124_V_we0; +output [1:0] data_124_V_address1; +output data_124_V_ce1; +output [7:0] data_124_V_d1; +input [7:0] data_124_V_q1; +output data_124_V_we1; +output [1:0] data_125_V_address0; +output data_125_V_ce0; +output [7:0] data_125_V_d0; +input [7:0] data_125_V_q0; +output data_125_V_we0; +output [1:0] data_125_V_address1; +output data_125_V_ce1; +output [7:0] data_125_V_d1; +input [7:0] data_125_V_q1; +output data_125_V_we1; +output [1:0] data_126_V_address0; +output data_126_V_ce0; +output [7:0] data_126_V_d0; +input [7:0] data_126_V_q0; +output data_126_V_we0; +output [1:0] data_126_V_address1; +output data_126_V_ce1; +output [7:0] data_126_V_d1; +input [7:0] data_126_V_q1; +output data_126_V_we1; +output [1:0] data_127_V_address0; +output data_127_V_ce0; +output [7:0] data_127_V_d0; +input [7:0] data_127_V_q0; +output data_127_V_we0; +output [1:0] data_127_V_address1; +output data_127_V_ce1; +output [7:0] data_127_V_d1; +input [7:0] data_127_V_q1; +output data_127_V_we1; +output [7:0] res_0_V; +output [7:0] res_1_V; +output [7:0] res_2_V; +output [7:0] res_3_V; +output [7:0] res_4_V; +output [7:0] res_5_V; +output [7:0] res_6_V; +output [7:0] res_7_V; +output [7:0] res_8_V; +output [7:0] res_9_V; +input ap_clk; +input ap_rst; +input ap_start; +output res_0_V_ap_vld; +output ap_done; +output res_1_V_ap_vld; +output res_2_V_ap_vld; +output res_3_V_ap_vld; +output res_4_V_ap_vld; +output res_5_V_ap_vld; +output res_6_V_ap_vld; +output res_7_V_ap_vld; +output res_8_V_ap_vld; +output res_9_V_ap_vld; +output ap_ready; +output ap_idle; +input ap_continue; + +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_ap_start; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_ap_done; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_ap_continue; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_ap_idle; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_ap_ready; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_start_out; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_start_write; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_0_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_0_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_1_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_1_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_2_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_2_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_3_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_3_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_4_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_4_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_5_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_5_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_6_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_6_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_7_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_7_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_8_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_8_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_9_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_9_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_10_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_10_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_11_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_11_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_12_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_12_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_13_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_13_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_14_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_14_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_15_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_15_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_16_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_16_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_17_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_17_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_18_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_18_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_19_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_19_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_20_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_20_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_21_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_21_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_22_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_22_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_23_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_23_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_24_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_24_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_25_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_25_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_26_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_26_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_27_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_27_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_28_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_28_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_29_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_29_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_30_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_30_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_31_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_31_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_32_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_32_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_33_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_33_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_34_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_34_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_35_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_35_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_36_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_36_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_37_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_37_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_38_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_38_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_39_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_39_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_40_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_40_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_41_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_41_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_42_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_42_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_43_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_43_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_44_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_44_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_45_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_45_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_46_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_46_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_47_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_47_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_48_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_48_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_49_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_49_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_50_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_50_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_51_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_51_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_52_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_52_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_53_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_53_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_54_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_54_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_55_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_55_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_56_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_56_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_57_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_57_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_58_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_58_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_59_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_59_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_60_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_60_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_61_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_61_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_62_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_62_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_63_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_63_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_64_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_64_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_65_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_65_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_66_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_66_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_67_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_67_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_68_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_68_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_69_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_69_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_70_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_70_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_71_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_71_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_72_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_72_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_73_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_73_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_74_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_74_V_ce0; +wire [2:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_75_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_75_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_76_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_76_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_77_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_77_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_78_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_78_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_79_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_79_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_80_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_80_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_81_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_81_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_82_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_82_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_83_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_83_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_84_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_84_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_85_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_85_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_86_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_86_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_87_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_87_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_88_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_88_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_89_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_89_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_90_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_90_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_91_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_91_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_92_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_92_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_93_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_93_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_94_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_94_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_95_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_95_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_96_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_96_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_97_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_97_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_98_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_98_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_99_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_99_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_100_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_100_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_101_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_101_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_102_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_102_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_103_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_103_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_104_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_104_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_105_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_105_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_106_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_106_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_107_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_107_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_108_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_108_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_109_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_109_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_110_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_110_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_111_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_111_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_112_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_112_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_113_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_113_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_114_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_114_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_115_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_115_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_116_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_116_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_117_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_117_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_118_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_118_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_119_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_119_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_120_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_120_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_121_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_121_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_122_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_122_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_123_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_123_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_124_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_124_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_125_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_125_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_126_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_126_V_ce0; +wire [1:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_127_V_address0; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_127_V_ce0; +wire [6:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_0_din; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_0_write; +wire [6:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_1_din; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_1_write; +wire [6:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_2_din; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_2_write; +wire [6:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_3_din; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_3_write; +wire [6:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_4_din; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_4_write; +wire [6:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_5_din; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_5_write; +wire [6:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_6_din; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_6_write; +wire [6:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_7_din; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_7_write; +wire [6:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_8_din; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_8_write; +wire [6:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_9_din; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_9_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_start; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_continue; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_idle; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_ready; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_0_read; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_1_read; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_2_read; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_3_read; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_4_read; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_5_read; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_6_read; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_7_read; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_8_read; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_9_read; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_0; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_1; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_2; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_3; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_4; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_5; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_6; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_7; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_8; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_9; +wire ap_channel_done_p_0_0_loc_channel; +wire p_0_0_loc_channel_full_n; +reg ap_sync_reg_channel_write_p_0_0_loc_channel; +wire ap_sync_channel_write_p_0_0_loc_channel; +wire ap_channel_done_acc_9_V; +wire acc_9_V_full_n; +reg ap_sync_reg_channel_write_acc_9_V; +wire ap_sync_channel_write_acc_9_V; +wire ap_channel_done_acc_8_V; +wire acc_8_V_full_n; +reg ap_sync_reg_channel_write_acc_8_V; +wire ap_sync_channel_write_acc_8_V; +wire ap_channel_done_acc_7_V; +wire acc_7_V_full_n; +reg ap_sync_reg_channel_write_acc_7_V; +wire ap_sync_channel_write_acc_7_V; +wire ap_channel_done_acc_6_V; +wire acc_6_V_full_n; +reg ap_sync_reg_channel_write_acc_6_V; +wire ap_sync_channel_write_acc_6_V; +wire ap_channel_done_acc_5_V; +wire acc_5_V_full_n; +reg ap_sync_reg_channel_write_acc_5_V; +wire ap_sync_channel_write_acc_5_V; +wire ap_channel_done_acc_4_V; +wire acc_4_V_full_n; +reg ap_sync_reg_channel_write_acc_4_V; +wire ap_sync_channel_write_acc_4_V; +wire ap_channel_done_acc_3_V; +wire acc_3_V_full_n; +reg ap_sync_reg_channel_write_acc_3_V; +wire ap_sync_channel_write_acc_3_V; +wire ap_channel_done_acc_2_V; +wire acc_2_V_full_n; +reg ap_sync_reg_channel_write_acc_2_V; +wire ap_sync_channel_write_acc_2_V; +wire ap_channel_done_acc_1_V; +wire acc_1_V_full_n; +reg ap_sync_reg_channel_write_acc_1_V; +wire ap_sync_channel_write_acc_1_V; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_ap_start; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_ap_done; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_ap_continue; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_ap_idle; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_ap_ready; +wire [7:0] cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_op_V_assign_out_din; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_op_V_assign_out_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_start; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_done; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_continue; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_idle; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_ready; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_op_V_assign_read; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_res_0_V; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_res_0_V_ap_vld; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_return; +wire ap_channel_done_acc_1_V_load_loc_channel; +wire acc_1_V_load_loc_channel_full_n; +reg ap_sync_reg_channel_write_acc_1_V_load_loc_channel; +wire ap_sync_channel_write_acc_1_V_load_loc_channel; +wire ap_sync_continue; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_ap_start; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_ap_done; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_ap_continue; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_ap_idle; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_ap_ready; +wire [7:0] cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_op_V_assign_out_din; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_op_V_assign_out_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_start; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_done; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_continue; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_idle; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_ready; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_op_V_assign_read; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_res_1_V; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_res_1_V_ap_vld; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_return; +wire ap_channel_done_acc_2_V_load_loc_channel; +wire acc_2_V_load_loc_channel_full_n; +reg ap_sync_reg_channel_write_acc_2_V_load_loc_channel; +wire ap_sync_channel_write_acc_2_V_load_loc_channel; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_ap_start; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_ap_done; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_ap_continue; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_ap_idle; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_ap_ready; +wire [7:0] cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_op_V_assign_out_din; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_op_V_assign_out_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_start; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_done; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_continue; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_idle; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_ready; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_op_V_assign_read; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_res_2_V; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_res_2_V_ap_vld; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_return; +wire ap_channel_done_acc_3_V_load_loc_channel; +wire acc_3_V_load_loc_channel_full_n; +reg ap_sync_reg_channel_write_acc_3_V_load_loc_channel; +wire ap_sync_channel_write_acc_3_V_load_loc_channel; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_ap_start; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_ap_done; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_ap_continue; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_ap_idle; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_ap_ready; +wire [7:0] cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_op_V_assign_out_din; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_op_V_assign_out_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_start; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_done; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_continue; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_idle; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_ready; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_op_V_assign_read; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_res_3_V; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_res_3_V_ap_vld; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_return; +wire ap_channel_done_acc_4_V_load_loc_channel; +wire acc_4_V_load_loc_channel_full_n; +reg ap_sync_reg_channel_write_acc_4_V_load_loc_channel; +wire ap_sync_channel_write_acc_4_V_load_loc_channel; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_ap_start; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_ap_done; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_ap_continue; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_ap_idle; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_ap_ready; +wire [7:0] cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_op_V_assign_out_din; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_op_V_assign_out_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_start; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_done; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_continue; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_idle; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_ready; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_op_V_assign_read; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_res_4_V; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_res_4_V_ap_vld; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_return; +wire ap_channel_done_acc_5_V_load_loc_channel; +wire acc_5_V_load_loc_channel_full_n; +reg ap_sync_reg_channel_write_acc_5_V_load_loc_channel; +wire ap_sync_channel_write_acc_5_V_load_loc_channel; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_ap_start; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_ap_done; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_ap_continue; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_ap_idle; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_ap_ready; +wire [7:0] cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_op_V_assign_out_din; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_op_V_assign_out_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_start; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_done; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_continue; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_idle; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_ready; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_op_V_assign_read; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_res_5_V; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_res_5_V_ap_vld; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_return; +wire ap_channel_done_acc_6_V_load_loc_channel; +wire acc_6_V_load_loc_channel_full_n; +reg ap_sync_reg_channel_write_acc_6_V_load_loc_channel; +wire ap_sync_channel_write_acc_6_V_load_loc_channel; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_ap_start; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_ap_done; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_ap_continue; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_ap_idle; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_ap_ready; +wire [7:0] cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_op_V_assign_out_din; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_op_V_assign_out_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_start; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_done; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_continue; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_idle; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_ready; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_op_V_assign_read; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_res_6_V; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_res_6_V_ap_vld; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_return; +wire ap_channel_done_acc_7_V_load_loc_channel; +wire acc_7_V_load_loc_channel_full_n; +reg ap_sync_reg_channel_write_acc_7_V_load_loc_channel; +wire ap_sync_channel_write_acc_7_V_load_loc_channel; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_ap_start; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_ap_done; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_ap_continue; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_ap_idle; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_ap_ready; +wire [7:0] cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_op_V_assign_out_din; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_op_V_assign_out_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_start; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_done; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_continue; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_idle; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_ready; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_op_V_assign_read; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_res_7_V; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_res_7_V_ap_vld; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_return; +wire ap_channel_done_acc_8_V_load_loc_channel; +wire acc_8_V_load_loc_channel_full_n; +reg ap_sync_reg_channel_write_acc_8_V_load_loc_channel; +wire ap_sync_channel_write_acc_8_V_load_loc_channel; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_ap_start; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_ap_done; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_ap_continue; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_ap_idle; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_ap_ready; +wire [7:0] cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_op_V_assign_out_din; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_op_V_assign_out_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_start; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_done; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_continue; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_idle; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_ready; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_op_V_assign_read; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_res_8_V; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_res_8_V_ap_vld; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_return; +wire ap_channel_done_acc_9_V_load_loc_channel; +wire acc_9_V_load_loc_channel_full_n; +reg ap_sync_reg_channel_write_acc_9_V_load_loc_channel; +wire ap_sync_channel_write_acc_9_V_load_loc_channel; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_ap_start; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_ap_done; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_ap_continue; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_ap_idle; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_ap_ready; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_start_out; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_start_write; +wire [7:0] cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_agg_result_V_din; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_agg_result_V_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_ap_start; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_ap_done; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_ap_continue; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_ap_idle; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_ap_ready; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_op_V_assign_read; +wire [7:0] dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_res_9_V; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_res_9_V_ap_vld; +wire mult_0_channel_full_n; +wire [6:0] mult_0_channel_dout; +wire mult_0_channel_empty_n; +wire mult_1_channel_full_n; +wire [6:0] mult_1_channel_dout; +wire mult_1_channel_empty_n; +wire mult_2_channel_full_n; +wire [6:0] mult_2_channel_dout; +wire mult_2_channel_empty_n; +wire mult_3_channel_full_n; +wire [6:0] mult_3_channel_dout; +wire mult_3_channel_empty_n; +wire mult_4_channel_full_n; +wire [6:0] mult_4_channel_dout; +wire mult_4_channel_empty_n; +wire mult_5_channel_full_n; +wire [6:0] mult_5_channel_dout; +wire mult_5_channel_empty_n; +wire mult_6_channel_full_n; +wire [6:0] mult_6_channel_dout; +wire mult_6_channel_empty_n; +wire mult_7_channel_full_n; +wire [6:0] mult_7_channel_dout; +wire mult_7_channel_empty_n; +wire mult_8_channel_full_n; +wire [6:0] mult_8_channel_dout; +wire mult_8_channel_empty_n; +wire mult_9_channel_full_n; +wire [6:0] mult_9_channel_dout; +wire mult_9_channel_empty_n; +wire [7:0] acc_1_V_dout; +wire acc_1_V_empty_n; +wire [7:0] acc_2_V_dout; +wire acc_2_V_empty_n; +wire [7:0] acc_3_V_dout; +wire acc_3_V_empty_n; +wire [7:0] acc_4_V_dout; +wire acc_4_V_empty_n; +wire [7:0] acc_5_V_dout; +wire acc_5_V_empty_n; +wire [7:0] acc_6_V_dout; +wire acc_6_V_empty_n; +wire [7:0] acc_7_V_dout; +wire acc_7_V_empty_n; +wire [7:0] acc_8_V_dout; +wire acc_8_V_empty_n; +wire [7:0] acc_9_V_dout; +wire acc_9_V_empty_n; +wire [7:0] p_0_0_loc_channel_dout; +wire p_0_0_loc_channel_empty_n; +wire op_V_assign_c_full_n; +wire [7:0] op_V_assign_c_dout; +wire op_V_assign_c_empty_n; +wire [7:0] acc_1_V_load_loc_channel_dout; +wire acc_1_V_load_loc_channel_empty_n; +wire op_V_assign_c143_full_n; +wire [7:0] op_V_assign_c143_dout; +wire op_V_assign_c143_empty_n; +wire [7:0] acc_2_V_load_loc_channel_dout; +wire acc_2_V_load_loc_channel_empty_n; +wire op_V_assign_c144_full_n; +wire [7:0] op_V_assign_c144_dout; +wire op_V_assign_c144_empty_n; +wire [7:0] acc_3_V_load_loc_channel_dout; +wire acc_3_V_load_loc_channel_empty_n; +wire op_V_assign_c145_full_n; +wire [7:0] op_V_assign_c145_dout; +wire op_V_assign_c145_empty_n; +wire [7:0] acc_4_V_load_loc_channel_dout; +wire acc_4_V_load_loc_channel_empty_n; +wire op_V_assign_c146_full_n; +wire [7:0] op_V_assign_c146_dout; +wire op_V_assign_c146_empty_n; +wire [7:0] acc_5_V_load_loc_channel_dout; +wire acc_5_V_load_loc_channel_empty_n; +wire op_V_assign_c147_full_n; +wire [7:0] op_V_assign_c147_dout; +wire op_V_assign_c147_empty_n; +wire [7:0] acc_6_V_load_loc_channel_dout; +wire acc_6_V_load_loc_channel_empty_n; +wire op_V_assign_c148_full_n; +wire [7:0] op_V_assign_c148_dout; +wire op_V_assign_c148_empty_n; +wire [7:0] acc_7_V_load_loc_channel_dout; +wire acc_7_V_load_loc_channel_empty_n; +wire op_V_assign_c149_full_n; +wire [7:0] op_V_assign_c149_dout; +wire op_V_assign_c149_empty_n; +wire [7:0] acc_8_V_load_loc_channel_dout; +wire acc_8_V_load_loc_channel_empty_n; +wire op_V_assign_c150_full_n; +wire [7:0] op_V_assign_c150_dout; +wire op_V_assign_c150_empty_n; +wire [7:0] acc_9_V_load_loc_channel_dout; +wire acc_9_V_load_loc_channel_empty_n; +wire op_V_assign_c151_full_n; +wire [7:0] op_V_assign_c151_dout; +wire op_V_assign_c151_empty_n; +wire ap_sync_done; +wire ap_sync_ready; +wire [0:0] start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_din; +wire start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_full_n; +wire [0:0] start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_dout; +wire start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_empty_n; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_start_full_n; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_start_write; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_start_full_n; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_start_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_start_full_n; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_start_write; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_start_full_n; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_start_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_start_full_n; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_start_write; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_start_full_n; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_start_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_start_full_n; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_start_write; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_start_full_n; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_start_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_start_full_n; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_start_write; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_start_full_n; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_start_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_start_full_n; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_start_write; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_start_full_n; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_start_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_start_full_n; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_start_write; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_start_full_n; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_start_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_start_full_n; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_start_write; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_start_full_n; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_start_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_start_full_n; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_start_write; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_start_full_n; +wire cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_start_write; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_start_full_n; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_start_write; +wire [0:0] start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_din; +wire start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_full_n; +wire [0:0] start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_dout; +wire start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_empty_n; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_start_full_n; +wire dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_start_write; + +// power-on initialization +initial begin +#0 ap_sync_reg_channel_write_p_0_0_loc_channel = 1'b0; +#0 ap_sync_reg_channel_write_acc_9_V = 1'b0; +#0 ap_sync_reg_channel_write_acc_8_V = 1'b0; +#0 ap_sync_reg_channel_write_acc_7_V = 1'b0; +#0 ap_sync_reg_channel_write_acc_6_V = 1'b0; +#0 ap_sync_reg_channel_write_acc_5_V = 1'b0; +#0 ap_sync_reg_channel_write_acc_4_V = 1'b0; +#0 ap_sync_reg_channel_write_acc_3_V = 1'b0; +#0 ap_sync_reg_channel_write_acc_2_V = 1'b0; +#0 ap_sync_reg_channel_write_acc_1_V = 1'b0; +#0 ap_sync_reg_channel_write_acc_1_V_load_loc_channel = 1'b0; +#0 ap_sync_reg_channel_write_acc_2_V_load_loc_channel = 1'b0; +#0 ap_sync_reg_channel_write_acc_3_V_load_loc_channel = 1'b0; +#0 ap_sync_reg_channel_write_acc_4_V_load_loc_channel = 1'b0; +#0 ap_sync_reg_channel_write_acc_5_V_load_loc_channel = 1'b0; +#0 ap_sync_reg_channel_write_acc_6_V_load_loc_channel = 1'b0; +#0 ap_sync_reg_channel_write_acc_7_V_load_loc_channel = 1'b0; +#0 ap_sync_reg_channel_write_acc_8_V_load_loc_channel = 1'b0; +#0 ap_sync_reg_channel_write_acc_9_V_load_loc_channel = 1'b0; +end + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_ap_start), + .start_full_n(start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_full_n), + .ap_done(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_ap_done), + .ap_continue(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_ap_continue), + .ap_idle(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_ap_idle), + .ap_ready(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_ap_ready), + .start_out(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_start_out), + .start_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_start_write), + .data_0_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_0_V_address0), + .data_0_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_0_V_ce0), + .data_0_V_q0(data_0_V_q0), + .data_1_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_1_V_address0), + .data_1_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_1_V_ce0), + .data_1_V_q0(data_1_V_q0), + .data_2_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_2_V_address0), + .data_2_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_2_V_ce0), + .data_2_V_q0(data_2_V_q0), + .data_3_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_3_V_address0), + .data_3_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_3_V_ce0), + .data_3_V_q0(data_3_V_q0), + .data_4_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_4_V_address0), + .data_4_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_4_V_ce0), + .data_4_V_q0(data_4_V_q0), + .data_5_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_5_V_address0), + .data_5_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_5_V_ce0), + .data_5_V_q0(data_5_V_q0), + .data_6_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_6_V_address0), + .data_6_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_6_V_ce0), + .data_6_V_q0(data_6_V_q0), + .data_7_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_7_V_address0), + .data_7_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_7_V_ce0), + .data_7_V_q0(data_7_V_q0), + .data_8_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_8_V_address0), + .data_8_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_8_V_ce0), + .data_8_V_q0(data_8_V_q0), + .data_9_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_9_V_address0), + .data_9_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_9_V_ce0), + .data_9_V_q0(data_9_V_q0), + .data_10_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_10_V_address0), + .data_10_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_10_V_ce0), + .data_10_V_q0(data_10_V_q0), + .data_11_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_11_V_address0), + .data_11_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_11_V_ce0), + .data_11_V_q0(data_11_V_q0), + .data_12_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_12_V_address0), + .data_12_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_12_V_ce0), + .data_12_V_q0(data_12_V_q0), + .data_13_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_13_V_address0), + .data_13_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_13_V_ce0), + .data_13_V_q0(data_13_V_q0), + .data_14_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_14_V_address0), + .data_14_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_14_V_ce0), + .data_14_V_q0(data_14_V_q0), + .data_15_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_15_V_address0), + .data_15_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_15_V_ce0), + .data_15_V_q0(data_15_V_q0), + .data_16_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_16_V_address0), + .data_16_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_16_V_ce0), + .data_16_V_q0(data_16_V_q0), + .data_17_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_17_V_address0), + .data_17_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_17_V_ce0), + .data_17_V_q0(data_17_V_q0), + .data_18_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_18_V_address0), + .data_18_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_18_V_ce0), + .data_18_V_q0(data_18_V_q0), + .data_19_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_19_V_address0), + .data_19_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_19_V_ce0), + .data_19_V_q0(data_19_V_q0), + .data_20_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_20_V_address0), + .data_20_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_20_V_ce0), + .data_20_V_q0(data_20_V_q0), + .data_21_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_21_V_address0), + .data_21_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_21_V_ce0), + .data_21_V_q0(data_21_V_q0), + .data_22_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_22_V_address0), + .data_22_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_22_V_ce0), + .data_22_V_q0(data_22_V_q0), + .data_23_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_23_V_address0), + .data_23_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_23_V_ce0), + .data_23_V_q0(data_23_V_q0), + .data_24_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_24_V_address0), + .data_24_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_24_V_ce0), + .data_24_V_q0(data_24_V_q0), + .data_25_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_25_V_address0), + .data_25_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_25_V_ce0), + .data_25_V_q0(data_25_V_q0), + .data_26_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_26_V_address0), + .data_26_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_26_V_ce0), + .data_26_V_q0(data_26_V_q0), + .data_27_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_27_V_address0), + .data_27_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_27_V_ce0), + .data_27_V_q0(data_27_V_q0), + .data_28_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_28_V_address0), + .data_28_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_28_V_ce0), + .data_28_V_q0(data_28_V_q0), + .data_29_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_29_V_address0), + .data_29_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_29_V_ce0), + .data_29_V_q0(data_29_V_q0), + .data_30_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_30_V_address0), + .data_30_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_30_V_ce0), + .data_30_V_q0(data_30_V_q0), + .data_31_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_31_V_address0), + .data_31_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_31_V_ce0), + .data_31_V_q0(data_31_V_q0), + .data_32_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_32_V_address0), + .data_32_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_32_V_ce0), + .data_32_V_q0(data_32_V_q0), + .data_33_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_33_V_address0), + .data_33_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_33_V_ce0), + .data_33_V_q0(data_33_V_q0), + .data_34_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_34_V_address0), + .data_34_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_34_V_ce0), + .data_34_V_q0(data_34_V_q0), + .data_35_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_35_V_address0), + .data_35_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_35_V_ce0), + .data_35_V_q0(data_35_V_q0), + .data_36_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_36_V_address0), + .data_36_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_36_V_ce0), + .data_36_V_q0(data_36_V_q0), + .data_37_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_37_V_address0), + .data_37_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_37_V_ce0), + .data_37_V_q0(data_37_V_q0), + .data_38_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_38_V_address0), + .data_38_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_38_V_ce0), + .data_38_V_q0(data_38_V_q0), + .data_39_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_39_V_address0), + .data_39_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_39_V_ce0), + .data_39_V_q0(data_39_V_q0), + .data_40_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_40_V_address0), + .data_40_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_40_V_ce0), + .data_40_V_q0(data_40_V_q0), + .data_41_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_41_V_address0), + .data_41_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_41_V_ce0), + .data_41_V_q0(data_41_V_q0), + .data_42_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_42_V_address0), + .data_42_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_42_V_ce0), + .data_42_V_q0(data_42_V_q0), + .data_43_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_43_V_address0), + .data_43_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_43_V_ce0), + .data_43_V_q0(data_43_V_q0), + .data_44_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_44_V_address0), + .data_44_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_44_V_ce0), + .data_44_V_q0(data_44_V_q0), + .data_45_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_45_V_address0), + .data_45_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_45_V_ce0), + .data_45_V_q0(data_45_V_q0), + .data_46_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_46_V_address0), + .data_46_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_46_V_ce0), + .data_46_V_q0(data_46_V_q0), + .data_47_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_47_V_address0), + .data_47_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_47_V_ce0), + .data_47_V_q0(data_47_V_q0), + .data_48_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_48_V_address0), + .data_48_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_48_V_ce0), + .data_48_V_q0(data_48_V_q0), + .data_49_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_49_V_address0), + .data_49_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_49_V_ce0), + .data_49_V_q0(data_49_V_q0), + .data_50_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_50_V_address0), + .data_50_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_50_V_ce0), + .data_50_V_q0(data_50_V_q0), + .data_51_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_51_V_address0), + .data_51_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_51_V_ce0), + .data_51_V_q0(data_51_V_q0), + .data_52_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_52_V_address0), + .data_52_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_52_V_ce0), + .data_52_V_q0(data_52_V_q0), + .data_53_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_53_V_address0), + .data_53_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_53_V_ce0), + .data_53_V_q0(data_53_V_q0), + .data_54_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_54_V_address0), + .data_54_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_54_V_ce0), + .data_54_V_q0(data_54_V_q0), + .data_55_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_55_V_address0), + .data_55_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_55_V_ce0), + .data_55_V_q0(data_55_V_q0), + .data_56_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_56_V_address0), + .data_56_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_56_V_ce0), + .data_56_V_q0(data_56_V_q0), + .data_57_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_57_V_address0), + .data_57_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_57_V_ce0), + .data_57_V_q0(data_57_V_q0), + .data_58_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_58_V_address0), + .data_58_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_58_V_ce0), + .data_58_V_q0(data_58_V_q0), + .data_59_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_59_V_address0), + .data_59_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_59_V_ce0), + .data_59_V_q0(data_59_V_q0), + .data_60_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_60_V_address0), + .data_60_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_60_V_ce0), + .data_60_V_q0(data_60_V_q0), + .data_61_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_61_V_address0), + .data_61_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_61_V_ce0), + .data_61_V_q0(data_61_V_q0), + .data_62_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_62_V_address0), + .data_62_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_62_V_ce0), + .data_62_V_q0(data_62_V_q0), + .data_63_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_63_V_address0), + .data_63_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_63_V_ce0), + .data_63_V_q0(data_63_V_q0), + .data_64_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_64_V_address0), + .data_64_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_64_V_ce0), + .data_64_V_q0(data_64_V_q0), + .data_65_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_65_V_address0), + .data_65_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_65_V_ce0), + .data_65_V_q0(data_65_V_q0), + .data_66_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_66_V_address0), + .data_66_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_66_V_ce0), + .data_66_V_q0(data_66_V_q0), + .data_67_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_67_V_address0), + .data_67_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_67_V_ce0), + .data_67_V_q0(data_67_V_q0), + .data_68_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_68_V_address0), + .data_68_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_68_V_ce0), + .data_68_V_q0(data_68_V_q0), + .data_69_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_69_V_address0), + .data_69_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_69_V_ce0), + .data_69_V_q0(data_69_V_q0), + .data_70_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_70_V_address0), + .data_70_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_70_V_ce0), + .data_70_V_q0(data_70_V_q0), + .data_71_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_71_V_address0), + .data_71_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_71_V_ce0), + .data_71_V_q0(data_71_V_q0), + .data_72_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_72_V_address0), + .data_72_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_72_V_ce0), + .data_72_V_q0(data_72_V_q0), + .data_73_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_73_V_address0), + .data_73_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_73_V_ce0), + .data_73_V_q0(data_73_V_q0), + .data_74_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_74_V_address0), + .data_74_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_74_V_ce0), + .data_74_V_q0(data_74_V_q0), + .data_75_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_75_V_address0), + .data_75_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_75_V_ce0), + .data_75_V_q0(data_75_V_q0), + .data_76_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_76_V_address0), + .data_76_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_76_V_ce0), + .data_76_V_q0(data_76_V_q0), + .data_77_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_77_V_address0), + .data_77_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_77_V_ce0), + .data_77_V_q0(data_77_V_q0), + .data_78_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_78_V_address0), + .data_78_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_78_V_ce0), + .data_78_V_q0(data_78_V_q0), + .data_79_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_79_V_address0), + .data_79_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_79_V_ce0), + .data_79_V_q0(data_79_V_q0), + .data_80_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_80_V_address0), + .data_80_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_80_V_ce0), + .data_80_V_q0(data_80_V_q0), + .data_81_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_81_V_address0), + .data_81_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_81_V_ce0), + .data_81_V_q0(data_81_V_q0), + .data_82_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_82_V_address0), + .data_82_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_82_V_ce0), + .data_82_V_q0(data_82_V_q0), + .data_83_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_83_V_address0), + .data_83_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_83_V_ce0), + .data_83_V_q0(data_83_V_q0), + .data_84_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_84_V_address0), + .data_84_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_84_V_ce0), + .data_84_V_q0(data_84_V_q0), + .data_85_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_85_V_address0), + .data_85_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_85_V_ce0), + .data_85_V_q0(data_85_V_q0), + .data_86_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_86_V_address0), + .data_86_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_86_V_ce0), + .data_86_V_q0(data_86_V_q0), + .data_87_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_87_V_address0), + .data_87_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_87_V_ce0), + .data_87_V_q0(data_87_V_q0), + .data_88_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_88_V_address0), + .data_88_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_88_V_ce0), + .data_88_V_q0(data_88_V_q0), + .data_89_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_89_V_address0), + .data_89_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_89_V_ce0), + .data_89_V_q0(data_89_V_q0), + .data_90_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_90_V_address0), + .data_90_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_90_V_ce0), + .data_90_V_q0(data_90_V_q0), + .data_91_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_91_V_address0), + .data_91_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_91_V_ce0), + .data_91_V_q0(data_91_V_q0), + .data_92_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_92_V_address0), + .data_92_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_92_V_ce0), + .data_92_V_q0(data_92_V_q0), + .data_93_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_93_V_address0), + .data_93_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_93_V_ce0), + .data_93_V_q0(data_93_V_q0), + .data_94_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_94_V_address0), + .data_94_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_94_V_ce0), + .data_94_V_q0(data_94_V_q0), + .data_95_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_95_V_address0), + .data_95_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_95_V_ce0), + .data_95_V_q0(data_95_V_q0), + .data_96_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_96_V_address0), + .data_96_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_96_V_ce0), + .data_96_V_q0(data_96_V_q0), + .data_97_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_97_V_address0), + .data_97_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_97_V_ce0), + .data_97_V_q0(data_97_V_q0), + .data_98_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_98_V_address0), + .data_98_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_98_V_ce0), + .data_98_V_q0(data_98_V_q0), + .data_99_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_99_V_address0), + .data_99_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_99_V_ce0), + .data_99_V_q0(data_99_V_q0), + .data_100_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_100_V_address0), + .data_100_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_100_V_ce0), + .data_100_V_q0(data_100_V_q0), + .data_101_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_101_V_address0), + .data_101_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_101_V_ce0), + .data_101_V_q0(data_101_V_q0), + .data_102_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_102_V_address0), + .data_102_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_102_V_ce0), + .data_102_V_q0(data_102_V_q0), + .data_103_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_103_V_address0), + .data_103_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_103_V_ce0), + .data_103_V_q0(data_103_V_q0), + .data_104_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_104_V_address0), + .data_104_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_104_V_ce0), + .data_104_V_q0(data_104_V_q0), + .data_105_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_105_V_address0), + .data_105_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_105_V_ce0), + .data_105_V_q0(data_105_V_q0), + .data_106_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_106_V_address0), + .data_106_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_106_V_ce0), + .data_106_V_q0(data_106_V_q0), + .data_107_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_107_V_address0), + .data_107_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_107_V_ce0), + .data_107_V_q0(data_107_V_q0), + .data_108_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_108_V_address0), + .data_108_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_108_V_ce0), + .data_108_V_q0(data_108_V_q0), + .data_109_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_109_V_address0), + .data_109_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_109_V_ce0), + .data_109_V_q0(data_109_V_q0), + .data_110_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_110_V_address0), + .data_110_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_110_V_ce0), + .data_110_V_q0(data_110_V_q0), + .data_111_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_111_V_address0), + .data_111_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_111_V_ce0), + .data_111_V_q0(data_111_V_q0), + .data_112_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_112_V_address0), + .data_112_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_112_V_ce0), + .data_112_V_q0(data_112_V_q0), + .data_113_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_113_V_address0), + .data_113_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_113_V_ce0), + .data_113_V_q0(data_113_V_q0), + .data_114_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_114_V_address0), + .data_114_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_114_V_ce0), + .data_114_V_q0(data_114_V_q0), + .data_115_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_115_V_address0), + .data_115_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_115_V_ce0), + .data_115_V_q0(data_115_V_q0), + .data_116_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_116_V_address0), + .data_116_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_116_V_ce0), + .data_116_V_q0(data_116_V_q0), + .data_117_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_117_V_address0), + .data_117_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_117_V_ce0), + .data_117_V_q0(data_117_V_q0), + .data_118_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_118_V_address0), + .data_118_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_118_V_ce0), + .data_118_V_q0(data_118_V_q0), + .data_119_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_119_V_address0), + .data_119_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_119_V_ce0), + .data_119_V_q0(data_119_V_q0), + .data_120_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_120_V_address0), + .data_120_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_120_V_ce0), + .data_120_V_q0(data_120_V_q0), + .data_121_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_121_V_address0), + .data_121_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_121_V_ce0), + .data_121_V_q0(data_121_V_q0), + .data_122_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_122_V_address0), + .data_122_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_122_V_ce0), + .data_122_V_q0(data_122_V_q0), + .data_123_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_123_V_address0), + .data_123_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_123_V_ce0), + .data_123_V_q0(data_123_V_q0), + .data_124_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_124_V_address0), + .data_124_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_124_V_ce0), + .data_124_V_q0(data_124_V_q0), + .data_125_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_125_V_address0), + .data_125_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_125_V_ce0), + .data_125_V_q0(data_125_V_q0), + .data_126_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_126_V_address0), + .data_126_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_126_V_ce0), + .data_126_V_q0(data_126_V_q0), + .data_127_V_address0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_127_V_address0), + .data_127_V_ce0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_127_V_ce0), + .data_127_V_q0(data_127_V_q0), + .mult_0_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_0_din), + .mult_0_full_n(mult_0_channel_full_n), + .mult_0_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_0_write), + .mult_1_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_1_din), + .mult_1_full_n(mult_1_channel_full_n), + .mult_1_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_1_write), + .mult_2_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_2_din), + .mult_2_full_n(mult_2_channel_full_n), + .mult_2_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_2_write), + .mult_3_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_3_din), + .mult_3_full_n(mult_3_channel_full_n), + .mult_3_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_3_write), + .mult_4_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_4_din), + .mult_4_full_n(mult_4_channel_full_n), + .mult_4_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_4_write), + .mult_5_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_5_din), + .mult_5_full_n(mult_5_channel_full_n), + .mult_5_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_5_write), + .mult_6_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_6_din), + .mult_6_full_n(mult_6_channel_full_n), + .mult_6_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_6_write), + .mult_7_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_7_din), + .mult_7_full_n(mult_7_channel_full_n), + .mult_7_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_7_write), + .mult_8_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_8_din), + .mult_8_full_n(mult_8_channel_full_n), + .mult_8_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_8_write), + .mult_9_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_9_din), + .mult_9_full_n(mult_9_channel_full_n), + .mult_9_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_9_write) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_start), + .ap_done(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done), + .ap_continue(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_continue), + .ap_idle(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_idle), + .ap_ready(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_ready), + .mult_0_dout(mult_0_channel_dout), + .mult_0_empty_n(mult_0_channel_empty_n), + .mult_0_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_0_read), + .mult_1_dout(mult_1_channel_dout), + .mult_1_empty_n(mult_1_channel_empty_n), + .mult_1_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_1_read), + .mult_2_dout(mult_2_channel_dout), + .mult_2_empty_n(mult_2_channel_empty_n), + .mult_2_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_2_read), + .mult_3_dout(mult_3_channel_dout), + .mult_3_empty_n(mult_3_channel_empty_n), + .mult_3_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_3_read), + .mult_4_dout(mult_4_channel_dout), + .mult_4_empty_n(mult_4_channel_empty_n), + .mult_4_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_4_read), + .mult_5_dout(mult_5_channel_dout), + .mult_5_empty_n(mult_5_channel_empty_n), + .mult_5_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_5_read), + .mult_6_dout(mult_6_channel_dout), + .mult_6_empty_n(mult_6_channel_empty_n), + .mult_6_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_6_read), + .mult_7_dout(mult_7_channel_dout), + .mult_7_empty_n(mult_7_channel_empty_n), + .mult_7_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_7_read), + .mult_8_dout(mult_8_channel_dout), + .mult_8_empty_n(mult_8_channel_empty_n), + .mult_8_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_8_read), + .mult_9_dout(mult_9_channel_dout), + .mult_9_empty_n(mult_9_channel_empty_n), + .mult_9_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_9_read), + .ap_return_0(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_0), + .ap_return_1(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_1), + .ap_return_2(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_2), + .ap_return_3(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_3), + .ap_return_4(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_4), + .ap_return_5(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_5), + .ap_return_6(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_6), + .ap_return_7(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_7), + .ap_return_8(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_8), + .ap_return_9(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_9) +); + +cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110 cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_ap_start), + .ap_done(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_ap_done), + .ap_continue(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_ap_continue), + .ap_idle(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_ap_idle), + .ap_ready(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_ap_ready), + .p_read(p_0_0_loc_channel_dout), + .op_V_assign_out_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_op_V_assign_out_din), + .op_V_assign_out_full_n(op_V_assign_c_full_n), + .op_V_assign_out_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_op_V_assign_out_write) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_start), + .ap_done(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_done), + .ap_continue(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_continue), + .ap_idle(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_idle), + .ap_ready(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_ready), + .op_V_assign_dout(op_V_assign_c_dout), + .op_V_assign_empty_n(op_V_assign_c_empty_n), + .op_V_assign_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_op_V_assign_read), + .res_0_V(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_res_0_V), + .res_0_V_ap_vld(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_res_0_V_ap_vld), + .p_read(acc_1_V_dout), + .ap_return(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_return) +); + +cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111 cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_ap_start), + .ap_done(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_ap_done), + .ap_continue(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_ap_continue), + .ap_idle(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_ap_idle), + .ap_ready(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_ap_ready), + .p_read(acc_1_V_load_loc_channel_dout), + .op_V_assign_out_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_op_V_assign_out_din), + .op_V_assign_out_full_n(op_V_assign_c143_full_n), + .op_V_assign_out_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_op_V_assign_out_write) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_start), + .ap_done(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_done), + .ap_continue(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_continue), + .ap_idle(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_idle), + .ap_ready(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_ready), + .op_V_assign_dout(op_V_assign_c143_dout), + .op_V_assign_empty_n(op_V_assign_c143_empty_n), + .op_V_assign_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_op_V_assign_read), + .res_1_V(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_res_1_V), + .res_1_V_ap_vld(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_res_1_V_ap_vld), + .p_read(acc_2_V_dout), + .ap_return(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_return) +); + +cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112 cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_ap_start), + .ap_done(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_ap_done), + .ap_continue(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_ap_continue), + .ap_idle(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_ap_idle), + .ap_ready(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_ap_ready), + .p_read(acc_2_V_load_loc_channel_dout), + .op_V_assign_out_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_op_V_assign_out_din), + .op_V_assign_out_full_n(op_V_assign_c144_full_n), + .op_V_assign_out_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_op_V_assign_out_write) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_start), + .ap_done(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_done), + .ap_continue(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_continue), + .ap_idle(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_idle), + .ap_ready(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_ready), + .op_V_assign_dout(op_V_assign_c144_dout), + .op_V_assign_empty_n(op_V_assign_c144_empty_n), + .op_V_assign_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_op_V_assign_read), + .res_2_V(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_res_2_V), + .res_2_V_ap_vld(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_res_2_V_ap_vld), + .p_read(acc_3_V_dout), + .ap_return(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_return) +); + +cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113 cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_ap_start), + .ap_done(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_ap_done), + .ap_continue(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_ap_continue), + .ap_idle(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_ap_idle), + .ap_ready(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_ap_ready), + .p_read(acc_3_V_load_loc_channel_dout), + .op_V_assign_out_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_op_V_assign_out_din), + .op_V_assign_out_full_n(op_V_assign_c145_full_n), + .op_V_assign_out_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_op_V_assign_out_write) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_start), + .ap_done(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_done), + .ap_continue(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_continue), + .ap_idle(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_idle), + .ap_ready(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_ready), + .op_V_assign_dout(op_V_assign_c145_dout), + .op_V_assign_empty_n(op_V_assign_c145_empty_n), + .op_V_assign_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_op_V_assign_read), + .res_3_V(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_res_3_V), + .res_3_V_ap_vld(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_res_3_V_ap_vld), + .p_read(acc_4_V_dout), + .ap_return(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_return) +); + +cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114 cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_ap_start), + .ap_done(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_ap_done), + .ap_continue(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_ap_continue), + .ap_idle(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_ap_idle), + .ap_ready(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_ap_ready), + .p_read(acc_4_V_load_loc_channel_dout), + .op_V_assign_out_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_op_V_assign_out_din), + .op_V_assign_out_full_n(op_V_assign_c146_full_n), + .op_V_assign_out_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_op_V_assign_out_write) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_start), + .ap_done(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_done), + .ap_continue(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_continue), + .ap_idle(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_idle), + .ap_ready(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_ready), + .op_V_assign_dout(op_V_assign_c146_dout), + .op_V_assign_empty_n(op_V_assign_c146_empty_n), + .op_V_assign_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_op_V_assign_read), + .res_4_V(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_res_4_V), + .res_4_V_ap_vld(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_res_4_V_ap_vld), + .p_read(acc_5_V_dout), + .ap_return(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_return) +); + +cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115 cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_ap_start), + .ap_done(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_ap_done), + .ap_continue(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_ap_continue), + .ap_idle(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_ap_idle), + .ap_ready(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_ap_ready), + .p_read(acc_5_V_load_loc_channel_dout), + .op_V_assign_out_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_op_V_assign_out_din), + .op_V_assign_out_full_n(op_V_assign_c147_full_n), + .op_V_assign_out_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_op_V_assign_out_write) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_start), + .ap_done(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_done), + .ap_continue(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_continue), + .ap_idle(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_idle), + .ap_ready(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_ready), + .op_V_assign_dout(op_V_assign_c147_dout), + .op_V_assign_empty_n(op_V_assign_c147_empty_n), + .op_V_assign_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_op_V_assign_read), + .res_5_V(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_res_5_V), + .res_5_V_ap_vld(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_res_5_V_ap_vld), + .p_read(acc_6_V_dout), + .ap_return(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_return) +); + +cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116 cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_ap_start), + .ap_done(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_ap_done), + .ap_continue(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_ap_continue), + .ap_idle(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_ap_idle), + .ap_ready(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_ap_ready), + .p_read(acc_6_V_load_loc_channel_dout), + .op_V_assign_out_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_op_V_assign_out_din), + .op_V_assign_out_full_n(op_V_assign_c148_full_n), + .op_V_assign_out_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_op_V_assign_out_write) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_start), + .ap_done(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_done), + .ap_continue(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_continue), + .ap_idle(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_idle), + .ap_ready(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_ready), + .op_V_assign_dout(op_V_assign_c148_dout), + .op_V_assign_empty_n(op_V_assign_c148_empty_n), + .op_V_assign_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_op_V_assign_read), + .res_6_V(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_res_6_V), + .res_6_V_ap_vld(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_res_6_V_ap_vld), + .p_read(acc_7_V_dout), + .ap_return(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_return) +); + +cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117 cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_ap_start), + .ap_done(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_ap_done), + .ap_continue(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_ap_continue), + .ap_idle(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_ap_idle), + .ap_ready(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_ap_ready), + .p_read(acc_7_V_load_loc_channel_dout), + .op_V_assign_out_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_op_V_assign_out_din), + .op_V_assign_out_full_n(op_V_assign_c149_full_n), + .op_V_assign_out_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_op_V_assign_out_write) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_start), + .ap_done(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_done), + .ap_continue(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_continue), + .ap_idle(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_idle), + .ap_ready(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_ready), + .op_V_assign_dout(op_V_assign_c149_dout), + .op_V_assign_empty_n(op_V_assign_c149_empty_n), + .op_V_assign_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_op_V_assign_read), + .res_7_V(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_res_7_V), + .res_7_V_ap_vld(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_res_7_V_ap_vld), + .p_read(acc_8_V_dout), + .ap_return(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_return) +); + +cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118 cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_ap_start), + .ap_done(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_ap_done), + .ap_continue(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_ap_continue), + .ap_idle(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_ap_idle), + .ap_ready(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_ap_ready), + .p_read(acc_8_V_load_loc_channel_dout), + .op_V_assign_out_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_op_V_assign_out_din), + .op_V_assign_out_full_n(op_V_assign_c150_full_n), + .op_V_assign_out_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_op_V_assign_out_write) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_start), + .ap_done(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_done), + .ap_continue(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_continue), + .ap_idle(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_idle), + .ap_ready(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_ready), + .op_V_assign_dout(op_V_assign_c150_dout), + .op_V_assign_empty_n(op_V_assign_c150_empty_n), + .op_V_assign_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_op_V_assign_read), + .res_8_V(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_res_8_V), + .res_8_V_ap_vld(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_res_8_V_ap_vld), + .p_read(acc_9_V_dout), + .ap_return(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_return) +); + +cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_s cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_ap_start), + .start_full_n(start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_full_n), + .ap_done(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_ap_done), + .ap_continue(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_ap_continue), + .ap_idle(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_ap_idle), + .ap_ready(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_ap_ready), + .start_out(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_start_out), + .start_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_start_write), + .p_read(acc_9_V_load_loc_channel_dout), + .agg_result_V_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_agg_result_V_din), + .agg_result_V_full_n(op_V_assign_c151_full_n), + .agg_result_V_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_agg_result_V_write) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_ap_start), + .ap_done(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_ap_done), + .ap_continue(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_ap_continue), + .ap_idle(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_ap_idle), + .ap_ready(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_ap_ready), + .op_V_assign_dout(op_V_assign_c151_dout), + .op_V_assign_empty_n(op_V_assign_c151_empty_n), + .op_V_assign_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_op_V_assign_read), + .res_9_V(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_res_9_V), + .res_9_V_ap_vld(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_res_9_V_ap_vld) +); + +fifo_w7_d1_A mult_0_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_0_din), + .if_full_n(mult_0_channel_full_n), + .if_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_0_write), + .if_dout(mult_0_channel_dout), + .if_empty_n(mult_0_channel_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_0_read) +); + +fifo_w7_d1_A mult_1_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_1_din), + .if_full_n(mult_1_channel_full_n), + .if_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_1_write), + .if_dout(mult_1_channel_dout), + .if_empty_n(mult_1_channel_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_1_read) +); + +fifo_w7_d1_A mult_2_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_2_din), + .if_full_n(mult_2_channel_full_n), + .if_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_2_write), + .if_dout(mult_2_channel_dout), + .if_empty_n(mult_2_channel_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_2_read) +); + +fifo_w7_d1_A mult_3_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_3_din), + .if_full_n(mult_3_channel_full_n), + .if_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_3_write), + .if_dout(mult_3_channel_dout), + .if_empty_n(mult_3_channel_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_3_read) +); + +fifo_w7_d1_A mult_4_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_4_din), + .if_full_n(mult_4_channel_full_n), + .if_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_4_write), + .if_dout(mult_4_channel_dout), + .if_empty_n(mult_4_channel_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_4_read) +); + +fifo_w7_d1_A mult_5_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_5_din), + .if_full_n(mult_5_channel_full_n), + .if_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_5_write), + .if_dout(mult_5_channel_dout), + .if_empty_n(mult_5_channel_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_5_read) +); + +fifo_w7_d1_A mult_6_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_6_din), + .if_full_n(mult_6_channel_full_n), + .if_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_6_write), + .if_dout(mult_6_channel_dout), + .if_empty_n(mult_6_channel_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_6_read) +); + +fifo_w7_d1_A mult_7_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_7_din), + .if_full_n(mult_7_channel_full_n), + .if_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_7_write), + .if_dout(mult_7_channel_dout), + .if_empty_n(mult_7_channel_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_7_read) +); + +fifo_w7_d1_A mult_8_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_8_din), + .if_full_n(mult_8_channel_full_n), + .if_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_8_write), + .if_dout(mult_8_channel_dout), + .if_empty_n(mult_8_channel_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_8_read) +); + +fifo_w7_d1_A mult_9_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_9_din), + .if_full_n(mult_9_channel_full_n), + .if_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_mult_9_write), + .if_dout(mult_9_channel_dout), + .if_empty_n(mult_9_channel_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_mult_9_read) +); + +fifo_w8_d2_A acc_1_V_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_0), + .if_full_n(acc_1_V_full_n), + .if_write(ap_channel_done_acc_1_V), + .if_dout(acc_1_V_dout), + .if_empty_n(acc_1_V_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_ready) +); + +fifo_w8_d2_A acc_2_V_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_1), + .if_full_n(acc_2_V_full_n), + .if_write(ap_channel_done_acc_2_V), + .if_dout(acc_2_V_dout), + .if_empty_n(acc_2_V_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_ready) +); + +fifo_w8_d2_A acc_3_V_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_2), + .if_full_n(acc_3_V_full_n), + .if_write(ap_channel_done_acc_3_V), + .if_dout(acc_3_V_dout), + .if_empty_n(acc_3_V_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_ready) +); + +fifo_w8_d2_A acc_4_V_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_3), + .if_full_n(acc_4_V_full_n), + .if_write(ap_channel_done_acc_4_V), + .if_dout(acc_4_V_dout), + .if_empty_n(acc_4_V_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_ready) +); + +fifo_w8_d2_A acc_5_V_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_4), + .if_full_n(acc_5_V_full_n), + .if_write(ap_channel_done_acc_5_V), + .if_dout(acc_5_V_dout), + .if_empty_n(acc_5_V_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_ready) +); + +fifo_w8_d2_A acc_6_V_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_5), + .if_full_n(acc_6_V_full_n), + .if_write(ap_channel_done_acc_6_V), + .if_dout(acc_6_V_dout), + .if_empty_n(acc_6_V_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_ready) +); + +fifo_w8_d2_A acc_7_V_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_6), + .if_full_n(acc_7_V_full_n), + .if_write(ap_channel_done_acc_7_V), + .if_dout(acc_7_V_dout), + .if_empty_n(acc_7_V_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_ready) +); + +fifo_w8_d2_A acc_8_V_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_7), + .if_full_n(acc_8_V_full_n), + .if_write(ap_channel_done_acc_8_V), + .if_dout(acc_8_V_dout), + .if_empty_n(acc_8_V_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_ready) +); + +fifo_w8_d2_A acc_9_V_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_8), + .if_full_n(acc_9_V_full_n), + .if_write(ap_channel_done_acc_9_V), + .if_dout(acc_9_V_dout), + .if_empty_n(acc_9_V_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_ready) +); + +fifo_w8_d2_A p_0_0_loc_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_return_9), + .if_full_n(p_0_0_loc_channel_full_n), + .if_write(ap_channel_done_p_0_0_loc_channel), + .if_dout(p_0_0_loc_channel_dout), + .if_empty_n(p_0_0_loc_channel_empty_n), + .if_read(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_ap_ready) +); + +fifo_w8_d2_A op_V_assign_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_op_V_assign_out_din), + .if_full_n(op_V_assign_c_full_n), + .if_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_op_V_assign_out_write), + .if_dout(op_V_assign_c_dout), + .if_empty_n(op_V_assign_c_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_op_V_assign_read) +); + +fifo_w8_d2_A acc_1_V_load_loc_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_return), + .if_full_n(acc_1_V_load_loc_channel_full_n), + .if_write(ap_channel_done_acc_1_V_load_loc_channel), + .if_dout(acc_1_V_load_loc_channel_dout), + .if_empty_n(acc_1_V_load_loc_channel_empty_n), + .if_read(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_ap_ready) +); + +fifo_w8_d2_A op_V_assign_c143_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_op_V_assign_out_din), + .if_full_n(op_V_assign_c143_full_n), + .if_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_op_V_assign_out_write), + .if_dout(op_V_assign_c143_dout), + .if_empty_n(op_V_assign_c143_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_op_V_assign_read) +); + +fifo_w8_d2_A acc_2_V_load_loc_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_return), + .if_full_n(acc_2_V_load_loc_channel_full_n), + .if_write(ap_channel_done_acc_2_V_load_loc_channel), + .if_dout(acc_2_V_load_loc_channel_dout), + .if_empty_n(acc_2_V_load_loc_channel_empty_n), + .if_read(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_ap_ready) +); + +fifo_w8_d2_A op_V_assign_c144_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_op_V_assign_out_din), + .if_full_n(op_V_assign_c144_full_n), + .if_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_op_V_assign_out_write), + .if_dout(op_V_assign_c144_dout), + .if_empty_n(op_V_assign_c144_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_op_V_assign_read) +); + +fifo_w8_d2_A acc_3_V_load_loc_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_return), + .if_full_n(acc_3_V_load_loc_channel_full_n), + .if_write(ap_channel_done_acc_3_V_load_loc_channel), + .if_dout(acc_3_V_load_loc_channel_dout), + .if_empty_n(acc_3_V_load_loc_channel_empty_n), + .if_read(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_ap_ready) +); + +fifo_w8_d2_A op_V_assign_c145_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_op_V_assign_out_din), + .if_full_n(op_V_assign_c145_full_n), + .if_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_op_V_assign_out_write), + .if_dout(op_V_assign_c145_dout), + .if_empty_n(op_V_assign_c145_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_op_V_assign_read) +); + +fifo_w8_d2_A acc_4_V_load_loc_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_return), + .if_full_n(acc_4_V_load_loc_channel_full_n), + .if_write(ap_channel_done_acc_4_V_load_loc_channel), + .if_dout(acc_4_V_load_loc_channel_dout), + .if_empty_n(acc_4_V_load_loc_channel_empty_n), + .if_read(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_ap_ready) +); + +fifo_w8_d2_A op_V_assign_c146_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_op_V_assign_out_din), + .if_full_n(op_V_assign_c146_full_n), + .if_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_op_V_assign_out_write), + .if_dout(op_V_assign_c146_dout), + .if_empty_n(op_V_assign_c146_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_op_V_assign_read) +); + +fifo_w8_d2_A acc_5_V_load_loc_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_return), + .if_full_n(acc_5_V_load_loc_channel_full_n), + .if_write(ap_channel_done_acc_5_V_load_loc_channel), + .if_dout(acc_5_V_load_loc_channel_dout), + .if_empty_n(acc_5_V_load_loc_channel_empty_n), + .if_read(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_ap_ready) +); + +fifo_w8_d2_A op_V_assign_c147_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_op_V_assign_out_din), + .if_full_n(op_V_assign_c147_full_n), + .if_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_op_V_assign_out_write), + .if_dout(op_V_assign_c147_dout), + .if_empty_n(op_V_assign_c147_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_op_V_assign_read) +); + +fifo_w8_d2_A acc_6_V_load_loc_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_return), + .if_full_n(acc_6_V_load_loc_channel_full_n), + .if_write(ap_channel_done_acc_6_V_load_loc_channel), + .if_dout(acc_6_V_load_loc_channel_dout), + .if_empty_n(acc_6_V_load_loc_channel_empty_n), + .if_read(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_ap_ready) +); + +fifo_w8_d2_A op_V_assign_c148_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_op_V_assign_out_din), + .if_full_n(op_V_assign_c148_full_n), + .if_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_op_V_assign_out_write), + .if_dout(op_V_assign_c148_dout), + .if_empty_n(op_V_assign_c148_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_op_V_assign_read) +); + +fifo_w8_d2_A acc_7_V_load_loc_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_return), + .if_full_n(acc_7_V_load_loc_channel_full_n), + .if_write(ap_channel_done_acc_7_V_load_loc_channel), + .if_dout(acc_7_V_load_loc_channel_dout), + .if_empty_n(acc_7_V_load_loc_channel_empty_n), + .if_read(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_ap_ready) +); + +fifo_w8_d2_A op_V_assign_c149_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_op_V_assign_out_din), + .if_full_n(op_V_assign_c149_full_n), + .if_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_op_V_assign_out_write), + .if_dout(op_V_assign_c149_dout), + .if_empty_n(op_V_assign_c149_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_op_V_assign_read) +); + +fifo_w8_d2_A acc_8_V_load_loc_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_return), + .if_full_n(acc_8_V_load_loc_channel_full_n), + .if_write(ap_channel_done_acc_8_V_load_loc_channel), + .if_dout(acc_8_V_load_loc_channel_dout), + .if_empty_n(acc_8_V_load_loc_channel_empty_n), + .if_read(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_ap_ready) +); + +fifo_w8_d2_A op_V_assign_c150_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_op_V_assign_out_din), + .if_full_n(op_V_assign_c150_full_n), + .if_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_op_V_assign_out_write), + .if_dout(op_V_assign_c150_dout), + .if_empty_n(op_V_assign_c150_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_op_V_assign_read) +); + +fifo_w8_d2_A acc_9_V_load_loc_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_return), + .if_full_n(acc_9_V_load_loc_channel_full_n), + .if_write(ap_channel_done_acc_9_V_load_loc_channel), + .if_dout(acc_9_V_load_loc_channel_dout), + .if_empty_n(acc_9_V_load_loc_channel_empty_n), + .if_read(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_ap_ready) +); + +fifo_w8_d2_A op_V_assign_c151_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_agg_result_V_din), + .if_full_n(op_V_assign_c151_full_n), + .if_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_agg_result_V_write), + .if_dout(op_V_assign_c151_dout), + .if_empty_n(op_V_assign_c151_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_op_V_assign_read) +); + +start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_prehebPq start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_prehebPq_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_din), + .if_full_n(start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_full_n), + .if_write(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_start_write), + .if_dout(start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_dout), + .if_empty_n(start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_ready) +); + +start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_prehebQq start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_prehebQq_U( + .clk(ap_clk), + .reset(ap_rst), + .if_read_ce(1'b1), + .if_write_ce(1'b1), + .if_din(start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_din), + .if_full_n(start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_full_n), + .if_write(cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_start_write), + .if_dout(start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_dout), + .if_empty_n(start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_empty_n), + .if_read(dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_ap_ready) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_1_V <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_1_V <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_1_V <= ap_sync_channel_write_acc_1_V; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_1_V_load_loc_channel <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_1_V_load_loc_channel <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_1_V_load_loc_channel <= ap_sync_channel_write_acc_1_V_load_loc_channel; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_2_V <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_2_V <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_2_V <= ap_sync_channel_write_acc_2_V; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_2_V_load_loc_channel <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_2_V_load_loc_channel <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_2_V_load_loc_channel <= ap_sync_channel_write_acc_2_V_load_loc_channel; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_3_V <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_3_V <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_3_V <= ap_sync_channel_write_acc_3_V; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_3_V_load_loc_channel <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_3_V_load_loc_channel <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_3_V_load_loc_channel <= ap_sync_channel_write_acc_3_V_load_loc_channel; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_4_V <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_4_V <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_4_V <= ap_sync_channel_write_acc_4_V; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_4_V_load_loc_channel <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_4_V_load_loc_channel <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_4_V_load_loc_channel <= ap_sync_channel_write_acc_4_V_load_loc_channel; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_5_V <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_5_V <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_5_V <= ap_sync_channel_write_acc_5_V; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_5_V_load_loc_channel <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_5_V_load_loc_channel <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_5_V_load_loc_channel <= ap_sync_channel_write_acc_5_V_load_loc_channel; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_6_V <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_6_V <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_6_V <= ap_sync_channel_write_acc_6_V; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_6_V_load_loc_channel <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_6_V_load_loc_channel <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_6_V_load_loc_channel <= ap_sync_channel_write_acc_6_V_load_loc_channel; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_7_V <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_7_V <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_7_V <= ap_sync_channel_write_acc_7_V; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_7_V_load_loc_channel <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_7_V_load_loc_channel <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_7_V_load_loc_channel <= ap_sync_channel_write_acc_7_V_load_loc_channel; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_8_V <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_8_V <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_8_V <= ap_sync_channel_write_acc_8_V; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_8_V_load_loc_channel <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_8_V_load_loc_channel <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_8_V_load_loc_channel <= ap_sync_channel_write_acc_8_V_load_loc_channel; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_9_V <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_9_V <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_9_V <= ap_sync_channel_write_acc_9_V; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_acc_9_V_load_loc_channel <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_acc_9_V_load_loc_channel <= 1'b0; + end else begin + ap_sync_reg_channel_write_acc_9_V_load_loc_channel <= ap_sync_channel_write_acc_9_V_load_loc_channel; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_p_0_0_loc_channel <= 1'b0; + end else begin + if (((dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_p_0_0_loc_channel <= 1'b0; + end else begin + ap_sync_reg_channel_write_p_0_0_loc_channel <= ap_sync_channel_write_p_0_0_loc_channel; + end + end +end + +assign ap_channel_done_acc_1_V = ((ap_sync_reg_channel_write_acc_1_V ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done); + +assign ap_channel_done_acc_1_V_load_loc_channel = ((ap_sync_reg_channel_write_acc_1_V_load_loc_channel ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_done); + +assign ap_channel_done_acc_2_V = ((ap_sync_reg_channel_write_acc_2_V ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done); + +assign ap_channel_done_acc_2_V_load_loc_channel = ((ap_sync_reg_channel_write_acc_2_V_load_loc_channel ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_done); + +assign ap_channel_done_acc_3_V = ((ap_sync_reg_channel_write_acc_3_V ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done); + +assign ap_channel_done_acc_3_V_load_loc_channel = ((ap_sync_reg_channel_write_acc_3_V_load_loc_channel ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_done); + +assign ap_channel_done_acc_4_V = ((ap_sync_reg_channel_write_acc_4_V ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done); + +assign ap_channel_done_acc_4_V_load_loc_channel = ((ap_sync_reg_channel_write_acc_4_V_load_loc_channel ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_done); + +assign ap_channel_done_acc_5_V = ((ap_sync_reg_channel_write_acc_5_V ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done); + +assign ap_channel_done_acc_5_V_load_loc_channel = ((ap_sync_reg_channel_write_acc_5_V_load_loc_channel ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_done); + +assign ap_channel_done_acc_6_V = ((ap_sync_reg_channel_write_acc_6_V ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done); + +assign ap_channel_done_acc_6_V_load_loc_channel = ((ap_sync_reg_channel_write_acc_6_V_load_loc_channel ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_done); + +assign ap_channel_done_acc_7_V = ((ap_sync_reg_channel_write_acc_7_V ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done); + +assign ap_channel_done_acc_7_V_load_loc_channel = ((ap_sync_reg_channel_write_acc_7_V_load_loc_channel ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_done); + +assign ap_channel_done_acc_8_V = ((ap_sync_reg_channel_write_acc_8_V ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done); + +assign ap_channel_done_acc_8_V_load_loc_channel = ((ap_sync_reg_channel_write_acc_8_V_load_loc_channel ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_done); + +assign ap_channel_done_acc_9_V = ((ap_sync_reg_channel_write_acc_9_V ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done); + +assign ap_channel_done_acc_9_V_load_loc_channel = ((ap_sync_reg_channel_write_acc_9_V_load_loc_channel ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_done); + +assign ap_channel_done_p_0_0_loc_channel = ((ap_sync_reg_channel_write_p_0_0_loc_channel ^ 1'b1) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_done); + +assign ap_done = ap_sync_done; + +assign ap_idle = ((1'b1 ^ acc_9_V_load_loc_channel_empty_n) & (1'b1 ^ acc_8_V_load_loc_channel_empty_n) & (1'b1 ^ acc_7_V_load_loc_channel_empty_n) & (1'b1 ^ acc_6_V_load_loc_channel_empty_n) & (1'b1 ^ acc_5_V_load_loc_channel_empty_n) & (1'b1 ^ acc_4_V_load_loc_channel_empty_n) & (1'b1 ^ acc_3_V_load_loc_channel_empty_n) & (1'b1 ^ acc_2_V_load_loc_channel_empty_n) & (1'b1 ^ acc_1_V_load_loc_channel_empty_n) & (p_0_0_loc_channel_empty_n ^ 1'b1) & (1'b1 ^ acc_9_V_empty_n) & (1'b1 ^ acc_8_V_empty_n) & (1'b1 ^ acc_7_V_empty_n) & (1'b1 ^ acc_6_V_empty_n) & (1'b1 ^ acc_5_V_empty_n) & (1'b1 ^ acc_4_V_empty_n) & (1'b1 ^ acc_3_V_empty_n) & (1'b1 ^ acc_2_V_empty_n) & (1'b1 ^ acc_1_V_empty_n) & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_ap_idle & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_idle & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_idle & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_idle & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_idle & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_idle & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_idle & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_idle & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_idle & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_ap_idle & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_idle & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_idle & cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_ap_idle & cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_ap_idle & cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_ap_idle & cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_ap_idle & cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_ap_idle & cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_ap_idle & cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_ap_idle & cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_ap_idle & cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_ap_idle & cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_ap_idle); + +assign ap_ready = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_ap_ready; + +assign ap_sync_channel_write_acc_1_V = ((ap_channel_done_acc_1_V & acc_1_V_full_n) | ap_sync_reg_channel_write_acc_1_V); + +assign ap_sync_channel_write_acc_1_V_load_loc_channel = ((ap_channel_done_acc_1_V_load_loc_channel & acc_1_V_load_loc_channel_full_n) | ap_sync_reg_channel_write_acc_1_V_load_loc_channel); + +assign ap_sync_channel_write_acc_2_V = ((ap_channel_done_acc_2_V & acc_2_V_full_n) | ap_sync_reg_channel_write_acc_2_V); + +assign ap_sync_channel_write_acc_2_V_load_loc_channel = ((ap_channel_done_acc_2_V_load_loc_channel & acc_2_V_load_loc_channel_full_n) | ap_sync_reg_channel_write_acc_2_V_load_loc_channel); + +assign ap_sync_channel_write_acc_3_V = ((ap_channel_done_acc_3_V & acc_3_V_full_n) | ap_sync_reg_channel_write_acc_3_V); + +assign ap_sync_channel_write_acc_3_V_load_loc_channel = ((ap_channel_done_acc_3_V_load_loc_channel & acc_3_V_load_loc_channel_full_n) | ap_sync_reg_channel_write_acc_3_V_load_loc_channel); + +assign ap_sync_channel_write_acc_4_V = ((ap_channel_done_acc_4_V & acc_4_V_full_n) | ap_sync_reg_channel_write_acc_4_V); + +assign ap_sync_channel_write_acc_4_V_load_loc_channel = ((ap_channel_done_acc_4_V_load_loc_channel & acc_4_V_load_loc_channel_full_n) | ap_sync_reg_channel_write_acc_4_V_load_loc_channel); + +assign ap_sync_channel_write_acc_5_V = ((ap_channel_done_acc_5_V & acc_5_V_full_n) | ap_sync_reg_channel_write_acc_5_V); + +assign ap_sync_channel_write_acc_5_V_load_loc_channel = ((ap_channel_done_acc_5_V_load_loc_channel & acc_5_V_load_loc_channel_full_n) | ap_sync_reg_channel_write_acc_5_V_load_loc_channel); + +assign ap_sync_channel_write_acc_6_V = ((ap_channel_done_acc_6_V & acc_6_V_full_n) | ap_sync_reg_channel_write_acc_6_V); + +assign ap_sync_channel_write_acc_6_V_load_loc_channel = ((ap_channel_done_acc_6_V_load_loc_channel & acc_6_V_load_loc_channel_full_n) | ap_sync_reg_channel_write_acc_6_V_load_loc_channel); + +assign ap_sync_channel_write_acc_7_V = ((ap_channel_done_acc_7_V & acc_7_V_full_n) | ap_sync_reg_channel_write_acc_7_V); + +assign ap_sync_channel_write_acc_7_V_load_loc_channel = ((ap_channel_done_acc_7_V_load_loc_channel & acc_7_V_load_loc_channel_full_n) | ap_sync_reg_channel_write_acc_7_V_load_loc_channel); + +assign ap_sync_channel_write_acc_8_V = ((ap_channel_done_acc_8_V & acc_8_V_full_n) | ap_sync_reg_channel_write_acc_8_V); + +assign ap_sync_channel_write_acc_8_V_load_loc_channel = ((ap_channel_done_acc_8_V_load_loc_channel & acc_8_V_load_loc_channel_full_n) | ap_sync_reg_channel_write_acc_8_V_load_loc_channel); + +assign ap_sync_channel_write_acc_9_V = ((ap_channel_done_acc_9_V & acc_9_V_full_n) | ap_sync_reg_channel_write_acc_9_V); + +assign ap_sync_channel_write_acc_9_V_load_loc_channel = ((ap_channel_done_acc_9_V_load_loc_channel & acc_9_V_load_loc_channel_full_n) | ap_sync_reg_channel_write_acc_9_V_load_loc_channel); + +assign ap_sync_channel_write_p_0_0_loc_channel = ((p_0_0_loc_channel_full_n & ap_channel_done_p_0_0_loc_channel) | ap_sync_reg_channel_write_p_0_0_loc_channel); + +assign ap_sync_continue = (ap_sync_done & ap_continue); + +assign ap_sync_done = (dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_ap_done & dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_done); + +assign ap_sync_ready = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_ap_ready; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_ap_continue = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_ap_start = p_0_0_loc_channel_empty_n; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_start_full_n = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_110_U0_start_write = 1'b0; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_ap_continue = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_ap_start = acc_1_V_load_loc_channel_empty_n; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_start_full_n = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_111_U0_start_write = 1'b0; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_ap_continue = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_ap_start = acc_2_V_load_loc_channel_empty_n; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_start_full_n = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_112_U0_start_write = 1'b0; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_ap_continue = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_ap_start = acc_3_V_load_loc_channel_empty_n; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_start_full_n = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_113_U0_start_write = 1'b0; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_ap_continue = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_ap_start = acc_4_V_load_loc_channel_empty_n; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_start_full_n = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_114_U0_start_write = 1'b0; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_ap_continue = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_ap_start = acc_5_V_load_loc_channel_empty_n; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_start_full_n = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_115_U0_start_write = 1'b0; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_ap_continue = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_ap_start = acc_6_V_load_loc_channel_empty_n; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_start_full_n = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_116_U0_start_write = 1'b0; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_ap_continue = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_ap_start = acc_7_V_load_loc_channel_empty_n; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_start_full_n = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_117_U0_start_write = 1'b0; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_ap_continue = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_ap_start = acc_8_V_load_loc_channel_empty_n; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_start_full_n = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_118_U0_start_write = 1'b0; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_ap_continue = 1'b1; + +assign cast_ap_fixed_ap_fixed_8_4_5_3_0_config9_U0_ap_start = acc_9_V_load_loc_channel_empty_n; + +assign data_0_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_0_V_address0; + +assign data_0_V_address1 = 3'd0; + +assign data_0_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_0_V_ce0; + +assign data_0_V_ce1 = 1'b0; + +assign data_0_V_d0 = 8'd0; + +assign data_0_V_d1 = 8'd0; + +assign data_0_V_we0 = 1'b0; + +assign data_0_V_we1 = 1'b0; + +assign data_100_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_100_V_address0; + +assign data_100_V_address1 = 2'd0; + +assign data_100_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_100_V_ce0; + +assign data_100_V_ce1 = 1'b0; + +assign data_100_V_d0 = 8'd0; + +assign data_100_V_d1 = 8'd0; + +assign data_100_V_we0 = 1'b0; + +assign data_100_V_we1 = 1'b0; + +assign data_101_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_101_V_address0; + +assign data_101_V_address1 = 2'd0; + +assign data_101_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_101_V_ce0; + +assign data_101_V_ce1 = 1'b0; + +assign data_101_V_d0 = 8'd0; + +assign data_101_V_d1 = 8'd0; + +assign data_101_V_we0 = 1'b0; + +assign data_101_V_we1 = 1'b0; + +assign data_102_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_102_V_address0; + +assign data_102_V_address1 = 2'd0; + +assign data_102_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_102_V_ce0; + +assign data_102_V_ce1 = 1'b0; + +assign data_102_V_d0 = 8'd0; + +assign data_102_V_d1 = 8'd0; + +assign data_102_V_we0 = 1'b0; + +assign data_102_V_we1 = 1'b0; + +assign data_103_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_103_V_address0; + +assign data_103_V_address1 = 2'd0; + +assign data_103_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_103_V_ce0; + +assign data_103_V_ce1 = 1'b0; + +assign data_103_V_d0 = 8'd0; + +assign data_103_V_d1 = 8'd0; + +assign data_103_V_we0 = 1'b0; + +assign data_103_V_we1 = 1'b0; + +assign data_104_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_104_V_address0; + +assign data_104_V_address1 = 2'd0; + +assign data_104_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_104_V_ce0; + +assign data_104_V_ce1 = 1'b0; + +assign data_104_V_d0 = 8'd0; + +assign data_104_V_d1 = 8'd0; + +assign data_104_V_we0 = 1'b0; + +assign data_104_V_we1 = 1'b0; + +assign data_105_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_105_V_address0; + +assign data_105_V_address1 = 2'd0; + +assign data_105_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_105_V_ce0; + +assign data_105_V_ce1 = 1'b0; + +assign data_105_V_d0 = 8'd0; + +assign data_105_V_d1 = 8'd0; + +assign data_105_V_we0 = 1'b0; + +assign data_105_V_we1 = 1'b0; + +assign data_106_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_106_V_address0; + +assign data_106_V_address1 = 2'd0; + +assign data_106_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_106_V_ce0; + +assign data_106_V_ce1 = 1'b0; + +assign data_106_V_d0 = 8'd0; + +assign data_106_V_d1 = 8'd0; + +assign data_106_V_we0 = 1'b0; + +assign data_106_V_we1 = 1'b0; + +assign data_107_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_107_V_address0; + +assign data_107_V_address1 = 2'd0; + +assign data_107_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_107_V_ce0; + +assign data_107_V_ce1 = 1'b0; + +assign data_107_V_d0 = 8'd0; + +assign data_107_V_d1 = 8'd0; + +assign data_107_V_we0 = 1'b0; + +assign data_107_V_we1 = 1'b0; + +assign data_108_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_108_V_address0; + +assign data_108_V_address1 = 2'd0; + +assign data_108_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_108_V_ce0; + +assign data_108_V_ce1 = 1'b0; + +assign data_108_V_d0 = 8'd0; + +assign data_108_V_d1 = 8'd0; + +assign data_108_V_we0 = 1'b0; + +assign data_108_V_we1 = 1'b0; + +assign data_109_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_109_V_address0; + +assign data_109_V_address1 = 2'd0; + +assign data_109_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_109_V_ce0; + +assign data_109_V_ce1 = 1'b0; + +assign data_109_V_d0 = 8'd0; + +assign data_109_V_d1 = 8'd0; + +assign data_109_V_we0 = 1'b0; + +assign data_109_V_we1 = 1'b0; + +assign data_10_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_10_V_address0; + +assign data_10_V_address1 = 3'd0; + +assign data_10_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_10_V_ce0; + +assign data_10_V_ce1 = 1'b0; + +assign data_10_V_d0 = 8'd0; + +assign data_10_V_d1 = 8'd0; + +assign data_10_V_we0 = 1'b0; + +assign data_10_V_we1 = 1'b0; + +assign data_110_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_110_V_address0; + +assign data_110_V_address1 = 2'd0; + +assign data_110_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_110_V_ce0; + +assign data_110_V_ce1 = 1'b0; + +assign data_110_V_d0 = 8'd0; + +assign data_110_V_d1 = 8'd0; + +assign data_110_V_we0 = 1'b0; + +assign data_110_V_we1 = 1'b0; + +assign data_111_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_111_V_address0; + +assign data_111_V_address1 = 2'd0; + +assign data_111_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_111_V_ce0; + +assign data_111_V_ce1 = 1'b0; + +assign data_111_V_d0 = 8'd0; + +assign data_111_V_d1 = 8'd0; + +assign data_111_V_we0 = 1'b0; + +assign data_111_V_we1 = 1'b0; + +assign data_112_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_112_V_address0; + +assign data_112_V_address1 = 2'd0; + +assign data_112_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_112_V_ce0; + +assign data_112_V_ce1 = 1'b0; + +assign data_112_V_d0 = 8'd0; + +assign data_112_V_d1 = 8'd0; + +assign data_112_V_we0 = 1'b0; + +assign data_112_V_we1 = 1'b0; + +assign data_113_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_113_V_address0; + +assign data_113_V_address1 = 2'd0; + +assign data_113_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_113_V_ce0; + +assign data_113_V_ce1 = 1'b0; + +assign data_113_V_d0 = 8'd0; + +assign data_113_V_d1 = 8'd0; + +assign data_113_V_we0 = 1'b0; + +assign data_113_V_we1 = 1'b0; + +assign data_114_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_114_V_address0; + +assign data_114_V_address1 = 2'd0; + +assign data_114_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_114_V_ce0; + +assign data_114_V_ce1 = 1'b0; + +assign data_114_V_d0 = 8'd0; + +assign data_114_V_d1 = 8'd0; + +assign data_114_V_we0 = 1'b0; + +assign data_114_V_we1 = 1'b0; + +assign data_115_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_115_V_address0; + +assign data_115_V_address1 = 2'd0; + +assign data_115_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_115_V_ce0; + +assign data_115_V_ce1 = 1'b0; + +assign data_115_V_d0 = 8'd0; + +assign data_115_V_d1 = 8'd0; + +assign data_115_V_we0 = 1'b0; + +assign data_115_V_we1 = 1'b0; + +assign data_116_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_116_V_address0; + +assign data_116_V_address1 = 2'd0; + +assign data_116_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_116_V_ce0; + +assign data_116_V_ce1 = 1'b0; + +assign data_116_V_d0 = 8'd0; + +assign data_116_V_d1 = 8'd0; + +assign data_116_V_we0 = 1'b0; + +assign data_116_V_we1 = 1'b0; + +assign data_117_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_117_V_address0; + +assign data_117_V_address1 = 2'd0; + +assign data_117_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_117_V_ce0; + +assign data_117_V_ce1 = 1'b0; + +assign data_117_V_d0 = 8'd0; + +assign data_117_V_d1 = 8'd0; + +assign data_117_V_we0 = 1'b0; + +assign data_117_V_we1 = 1'b0; + +assign data_118_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_118_V_address0; + +assign data_118_V_address1 = 2'd0; + +assign data_118_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_118_V_ce0; + +assign data_118_V_ce1 = 1'b0; + +assign data_118_V_d0 = 8'd0; + +assign data_118_V_d1 = 8'd0; + +assign data_118_V_we0 = 1'b0; + +assign data_118_V_we1 = 1'b0; + +assign data_119_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_119_V_address0; + +assign data_119_V_address1 = 2'd0; + +assign data_119_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_119_V_ce0; + +assign data_119_V_ce1 = 1'b0; + +assign data_119_V_d0 = 8'd0; + +assign data_119_V_d1 = 8'd0; + +assign data_119_V_we0 = 1'b0; + +assign data_119_V_we1 = 1'b0; + +assign data_11_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_11_V_address0; + +assign data_11_V_address1 = 3'd0; + +assign data_11_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_11_V_ce0; + +assign data_11_V_ce1 = 1'b0; + +assign data_11_V_d0 = 8'd0; + +assign data_11_V_d1 = 8'd0; + +assign data_11_V_we0 = 1'b0; + +assign data_11_V_we1 = 1'b0; + +assign data_120_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_120_V_address0; + +assign data_120_V_address1 = 2'd0; + +assign data_120_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_120_V_ce0; + +assign data_120_V_ce1 = 1'b0; + +assign data_120_V_d0 = 8'd0; + +assign data_120_V_d1 = 8'd0; + +assign data_120_V_we0 = 1'b0; + +assign data_120_V_we1 = 1'b0; + +assign data_121_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_121_V_address0; + +assign data_121_V_address1 = 2'd0; + +assign data_121_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_121_V_ce0; + +assign data_121_V_ce1 = 1'b0; + +assign data_121_V_d0 = 8'd0; + +assign data_121_V_d1 = 8'd0; + +assign data_121_V_we0 = 1'b0; + +assign data_121_V_we1 = 1'b0; + +assign data_122_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_122_V_address0; + +assign data_122_V_address1 = 2'd0; + +assign data_122_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_122_V_ce0; + +assign data_122_V_ce1 = 1'b0; + +assign data_122_V_d0 = 8'd0; + +assign data_122_V_d1 = 8'd0; + +assign data_122_V_we0 = 1'b0; + +assign data_122_V_we1 = 1'b0; + +assign data_123_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_123_V_address0; + +assign data_123_V_address1 = 2'd0; + +assign data_123_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_123_V_ce0; + +assign data_123_V_ce1 = 1'b0; + +assign data_123_V_d0 = 8'd0; + +assign data_123_V_d1 = 8'd0; + +assign data_123_V_we0 = 1'b0; + +assign data_123_V_we1 = 1'b0; + +assign data_124_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_124_V_address0; + +assign data_124_V_address1 = 2'd0; + +assign data_124_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_124_V_ce0; + +assign data_124_V_ce1 = 1'b0; + +assign data_124_V_d0 = 8'd0; + +assign data_124_V_d1 = 8'd0; + +assign data_124_V_we0 = 1'b0; + +assign data_124_V_we1 = 1'b0; + +assign data_125_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_125_V_address0; + +assign data_125_V_address1 = 2'd0; + +assign data_125_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_125_V_ce0; + +assign data_125_V_ce1 = 1'b0; + +assign data_125_V_d0 = 8'd0; + +assign data_125_V_d1 = 8'd0; + +assign data_125_V_we0 = 1'b0; + +assign data_125_V_we1 = 1'b0; + +assign data_126_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_126_V_address0; + +assign data_126_V_address1 = 2'd0; + +assign data_126_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_126_V_ce0; + +assign data_126_V_ce1 = 1'b0; + +assign data_126_V_d0 = 8'd0; + +assign data_126_V_d1 = 8'd0; + +assign data_126_V_we0 = 1'b0; + +assign data_126_V_we1 = 1'b0; + +assign data_127_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_127_V_address0; + +assign data_127_V_address1 = 2'd0; + +assign data_127_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_127_V_ce0; + +assign data_127_V_ce1 = 1'b0; + +assign data_127_V_d0 = 8'd0; + +assign data_127_V_d1 = 8'd0; + +assign data_127_V_we0 = 1'b0; + +assign data_127_V_we1 = 1'b0; + +assign data_12_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_12_V_address0; + +assign data_12_V_address1 = 3'd0; + +assign data_12_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_12_V_ce0; + +assign data_12_V_ce1 = 1'b0; + +assign data_12_V_d0 = 8'd0; + +assign data_12_V_d1 = 8'd0; + +assign data_12_V_we0 = 1'b0; + +assign data_12_V_we1 = 1'b0; + +assign data_13_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_13_V_address0; + +assign data_13_V_address1 = 3'd0; + +assign data_13_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_13_V_ce0; + +assign data_13_V_ce1 = 1'b0; + +assign data_13_V_d0 = 8'd0; + +assign data_13_V_d1 = 8'd0; + +assign data_13_V_we0 = 1'b0; + +assign data_13_V_we1 = 1'b0; + +assign data_14_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_14_V_address0; + +assign data_14_V_address1 = 3'd0; + +assign data_14_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_14_V_ce0; + +assign data_14_V_ce1 = 1'b0; + +assign data_14_V_d0 = 8'd0; + +assign data_14_V_d1 = 8'd0; + +assign data_14_V_we0 = 1'b0; + +assign data_14_V_we1 = 1'b0; + +assign data_15_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_15_V_address0; + +assign data_15_V_address1 = 3'd0; + +assign data_15_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_15_V_ce0; + +assign data_15_V_ce1 = 1'b0; + +assign data_15_V_d0 = 8'd0; + +assign data_15_V_d1 = 8'd0; + +assign data_15_V_we0 = 1'b0; + +assign data_15_V_we1 = 1'b0; + +assign data_16_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_16_V_address0; + +assign data_16_V_address1 = 3'd0; + +assign data_16_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_16_V_ce0; + +assign data_16_V_ce1 = 1'b0; + +assign data_16_V_d0 = 8'd0; + +assign data_16_V_d1 = 8'd0; + +assign data_16_V_we0 = 1'b0; + +assign data_16_V_we1 = 1'b0; + +assign data_17_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_17_V_address0; + +assign data_17_V_address1 = 3'd0; + +assign data_17_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_17_V_ce0; + +assign data_17_V_ce1 = 1'b0; + +assign data_17_V_d0 = 8'd0; + +assign data_17_V_d1 = 8'd0; + +assign data_17_V_we0 = 1'b0; + +assign data_17_V_we1 = 1'b0; + +assign data_18_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_18_V_address0; + +assign data_18_V_address1 = 3'd0; + +assign data_18_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_18_V_ce0; + +assign data_18_V_ce1 = 1'b0; + +assign data_18_V_d0 = 8'd0; + +assign data_18_V_d1 = 8'd0; + +assign data_18_V_we0 = 1'b0; + +assign data_18_V_we1 = 1'b0; + +assign data_19_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_19_V_address0; + +assign data_19_V_address1 = 3'd0; + +assign data_19_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_19_V_ce0; + +assign data_19_V_ce1 = 1'b0; + +assign data_19_V_d0 = 8'd0; + +assign data_19_V_d1 = 8'd0; + +assign data_19_V_we0 = 1'b0; + +assign data_19_V_we1 = 1'b0; + +assign data_1_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_1_V_address0; + +assign data_1_V_address1 = 3'd0; + +assign data_1_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_1_V_ce0; + +assign data_1_V_ce1 = 1'b0; + +assign data_1_V_d0 = 8'd0; + +assign data_1_V_d1 = 8'd0; + +assign data_1_V_we0 = 1'b0; + +assign data_1_V_we1 = 1'b0; + +assign data_20_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_20_V_address0; + +assign data_20_V_address1 = 3'd0; + +assign data_20_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_20_V_ce0; + +assign data_20_V_ce1 = 1'b0; + +assign data_20_V_d0 = 8'd0; + +assign data_20_V_d1 = 8'd0; + +assign data_20_V_we0 = 1'b0; + +assign data_20_V_we1 = 1'b0; + +assign data_21_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_21_V_address0; + +assign data_21_V_address1 = 3'd0; + +assign data_21_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_21_V_ce0; + +assign data_21_V_ce1 = 1'b0; + +assign data_21_V_d0 = 8'd0; + +assign data_21_V_d1 = 8'd0; + +assign data_21_V_we0 = 1'b0; + +assign data_21_V_we1 = 1'b0; + +assign data_22_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_22_V_address0; + +assign data_22_V_address1 = 3'd0; + +assign data_22_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_22_V_ce0; + +assign data_22_V_ce1 = 1'b0; + +assign data_22_V_d0 = 8'd0; + +assign data_22_V_d1 = 8'd0; + +assign data_22_V_we0 = 1'b0; + +assign data_22_V_we1 = 1'b0; + +assign data_23_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_23_V_address0; + +assign data_23_V_address1 = 3'd0; + +assign data_23_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_23_V_ce0; + +assign data_23_V_ce1 = 1'b0; + +assign data_23_V_d0 = 8'd0; + +assign data_23_V_d1 = 8'd0; + +assign data_23_V_we0 = 1'b0; + +assign data_23_V_we1 = 1'b0; + +assign data_24_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_24_V_address0; + +assign data_24_V_address1 = 3'd0; + +assign data_24_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_24_V_ce0; + +assign data_24_V_ce1 = 1'b0; + +assign data_24_V_d0 = 8'd0; + +assign data_24_V_d1 = 8'd0; + +assign data_24_V_we0 = 1'b0; + +assign data_24_V_we1 = 1'b0; + +assign data_25_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_25_V_address0; + +assign data_25_V_address1 = 3'd0; + +assign data_25_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_25_V_ce0; + +assign data_25_V_ce1 = 1'b0; + +assign data_25_V_d0 = 8'd0; + +assign data_25_V_d1 = 8'd0; + +assign data_25_V_we0 = 1'b0; + +assign data_25_V_we1 = 1'b0; + +assign data_26_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_26_V_address0; + +assign data_26_V_address1 = 3'd0; + +assign data_26_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_26_V_ce0; + +assign data_26_V_ce1 = 1'b0; + +assign data_26_V_d0 = 8'd0; + +assign data_26_V_d1 = 8'd0; + +assign data_26_V_we0 = 1'b0; + +assign data_26_V_we1 = 1'b0; + +assign data_27_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_27_V_address0; + +assign data_27_V_address1 = 3'd0; + +assign data_27_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_27_V_ce0; + +assign data_27_V_ce1 = 1'b0; + +assign data_27_V_d0 = 8'd0; + +assign data_27_V_d1 = 8'd0; + +assign data_27_V_we0 = 1'b0; + +assign data_27_V_we1 = 1'b0; + +assign data_28_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_28_V_address0; + +assign data_28_V_address1 = 3'd0; + +assign data_28_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_28_V_ce0; + +assign data_28_V_ce1 = 1'b0; + +assign data_28_V_d0 = 8'd0; + +assign data_28_V_d1 = 8'd0; + +assign data_28_V_we0 = 1'b0; + +assign data_28_V_we1 = 1'b0; + +assign data_29_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_29_V_address0; + +assign data_29_V_address1 = 3'd0; + +assign data_29_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_29_V_ce0; + +assign data_29_V_ce1 = 1'b0; + +assign data_29_V_d0 = 8'd0; + +assign data_29_V_d1 = 8'd0; + +assign data_29_V_we0 = 1'b0; + +assign data_29_V_we1 = 1'b0; + +assign data_2_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_2_V_address0; + +assign data_2_V_address1 = 3'd0; + +assign data_2_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_2_V_ce0; + +assign data_2_V_ce1 = 1'b0; + +assign data_2_V_d0 = 8'd0; + +assign data_2_V_d1 = 8'd0; + +assign data_2_V_we0 = 1'b0; + +assign data_2_V_we1 = 1'b0; + +assign data_30_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_30_V_address0; + +assign data_30_V_address1 = 3'd0; + +assign data_30_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_30_V_ce0; + +assign data_30_V_ce1 = 1'b0; + +assign data_30_V_d0 = 8'd0; + +assign data_30_V_d1 = 8'd0; + +assign data_30_V_we0 = 1'b0; + +assign data_30_V_we1 = 1'b0; + +assign data_31_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_31_V_address0; + +assign data_31_V_address1 = 3'd0; + +assign data_31_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_31_V_ce0; + +assign data_31_V_ce1 = 1'b0; + +assign data_31_V_d0 = 8'd0; + +assign data_31_V_d1 = 8'd0; + +assign data_31_V_we0 = 1'b0; + +assign data_31_V_we1 = 1'b0; + +assign data_32_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_32_V_address0; + +assign data_32_V_address1 = 3'd0; + +assign data_32_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_32_V_ce0; + +assign data_32_V_ce1 = 1'b0; + +assign data_32_V_d0 = 8'd0; + +assign data_32_V_d1 = 8'd0; + +assign data_32_V_we0 = 1'b0; + +assign data_32_V_we1 = 1'b0; + +assign data_33_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_33_V_address0; + +assign data_33_V_address1 = 3'd0; + +assign data_33_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_33_V_ce0; + +assign data_33_V_ce1 = 1'b0; + +assign data_33_V_d0 = 8'd0; + +assign data_33_V_d1 = 8'd0; + +assign data_33_V_we0 = 1'b0; + +assign data_33_V_we1 = 1'b0; + +assign data_34_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_34_V_address0; + +assign data_34_V_address1 = 3'd0; + +assign data_34_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_34_V_ce0; + +assign data_34_V_ce1 = 1'b0; + +assign data_34_V_d0 = 8'd0; + +assign data_34_V_d1 = 8'd0; + +assign data_34_V_we0 = 1'b0; + +assign data_34_V_we1 = 1'b0; + +assign data_35_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_35_V_address0; + +assign data_35_V_address1 = 3'd0; + +assign data_35_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_35_V_ce0; + +assign data_35_V_ce1 = 1'b0; + +assign data_35_V_d0 = 8'd0; + +assign data_35_V_d1 = 8'd0; + +assign data_35_V_we0 = 1'b0; + +assign data_35_V_we1 = 1'b0; + +assign data_36_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_36_V_address0; + +assign data_36_V_address1 = 3'd0; + +assign data_36_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_36_V_ce0; + +assign data_36_V_ce1 = 1'b0; + +assign data_36_V_d0 = 8'd0; + +assign data_36_V_d1 = 8'd0; + +assign data_36_V_we0 = 1'b0; + +assign data_36_V_we1 = 1'b0; + +assign data_37_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_37_V_address0; + +assign data_37_V_address1 = 3'd0; + +assign data_37_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_37_V_ce0; + +assign data_37_V_ce1 = 1'b0; + +assign data_37_V_d0 = 8'd0; + +assign data_37_V_d1 = 8'd0; + +assign data_37_V_we0 = 1'b0; + +assign data_37_V_we1 = 1'b0; + +assign data_38_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_38_V_address0; + +assign data_38_V_address1 = 3'd0; + +assign data_38_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_38_V_ce0; + +assign data_38_V_ce1 = 1'b0; + +assign data_38_V_d0 = 8'd0; + +assign data_38_V_d1 = 8'd0; + +assign data_38_V_we0 = 1'b0; + +assign data_38_V_we1 = 1'b0; + +assign data_39_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_39_V_address0; + +assign data_39_V_address1 = 3'd0; + +assign data_39_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_39_V_ce0; + +assign data_39_V_ce1 = 1'b0; + +assign data_39_V_d0 = 8'd0; + +assign data_39_V_d1 = 8'd0; + +assign data_39_V_we0 = 1'b0; + +assign data_39_V_we1 = 1'b0; + +assign data_3_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_3_V_address0; + +assign data_3_V_address1 = 3'd0; + +assign data_3_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_3_V_ce0; + +assign data_3_V_ce1 = 1'b0; + +assign data_3_V_d0 = 8'd0; + +assign data_3_V_d1 = 8'd0; + +assign data_3_V_we0 = 1'b0; + +assign data_3_V_we1 = 1'b0; + +assign data_40_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_40_V_address0; + +assign data_40_V_address1 = 3'd0; + +assign data_40_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_40_V_ce0; + +assign data_40_V_ce1 = 1'b0; + +assign data_40_V_d0 = 8'd0; + +assign data_40_V_d1 = 8'd0; + +assign data_40_V_we0 = 1'b0; + +assign data_40_V_we1 = 1'b0; + +assign data_41_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_41_V_address0; + +assign data_41_V_address1 = 3'd0; + +assign data_41_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_41_V_ce0; + +assign data_41_V_ce1 = 1'b0; + +assign data_41_V_d0 = 8'd0; + +assign data_41_V_d1 = 8'd0; + +assign data_41_V_we0 = 1'b0; + +assign data_41_V_we1 = 1'b0; + +assign data_42_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_42_V_address0; + +assign data_42_V_address1 = 3'd0; + +assign data_42_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_42_V_ce0; + +assign data_42_V_ce1 = 1'b0; + +assign data_42_V_d0 = 8'd0; + +assign data_42_V_d1 = 8'd0; + +assign data_42_V_we0 = 1'b0; + +assign data_42_V_we1 = 1'b0; + +assign data_43_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_43_V_address0; + +assign data_43_V_address1 = 3'd0; + +assign data_43_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_43_V_ce0; + +assign data_43_V_ce1 = 1'b0; + +assign data_43_V_d0 = 8'd0; + +assign data_43_V_d1 = 8'd0; + +assign data_43_V_we0 = 1'b0; + +assign data_43_V_we1 = 1'b0; + +assign data_44_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_44_V_address0; + +assign data_44_V_address1 = 3'd0; + +assign data_44_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_44_V_ce0; + +assign data_44_V_ce1 = 1'b0; + +assign data_44_V_d0 = 8'd0; + +assign data_44_V_d1 = 8'd0; + +assign data_44_V_we0 = 1'b0; + +assign data_44_V_we1 = 1'b0; + +assign data_45_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_45_V_address0; + +assign data_45_V_address1 = 3'd0; + +assign data_45_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_45_V_ce0; + +assign data_45_V_ce1 = 1'b0; + +assign data_45_V_d0 = 8'd0; + +assign data_45_V_d1 = 8'd0; + +assign data_45_V_we0 = 1'b0; + +assign data_45_V_we1 = 1'b0; + +assign data_46_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_46_V_address0; + +assign data_46_V_address1 = 3'd0; + +assign data_46_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_46_V_ce0; + +assign data_46_V_ce1 = 1'b0; + +assign data_46_V_d0 = 8'd0; + +assign data_46_V_d1 = 8'd0; + +assign data_46_V_we0 = 1'b0; + +assign data_46_V_we1 = 1'b0; + +assign data_47_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_47_V_address0; + +assign data_47_V_address1 = 3'd0; + +assign data_47_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_47_V_ce0; + +assign data_47_V_ce1 = 1'b0; + +assign data_47_V_d0 = 8'd0; + +assign data_47_V_d1 = 8'd0; + +assign data_47_V_we0 = 1'b0; + +assign data_47_V_we1 = 1'b0; + +assign data_48_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_48_V_address0; + +assign data_48_V_address1 = 3'd0; + +assign data_48_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_48_V_ce0; + +assign data_48_V_ce1 = 1'b0; + +assign data_48_V_d0 = 8'd0; + +assign data_48_V_d1 = 8'd0; + +assign data_48_V_we0 = 1'b0; + +assign data_48_V_we1 = 1'b0; + +assign data_49_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_49_V_address0; + +assign data_49_V_address1 = 3'd0; + +assign data_49_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_49_V_ce0; + +assign data_49_V_ce1 = 1'b0; + +assign data_49_V_d0 = 8'd0; + +assign data_49_V_d1 = 8'd0; + +assign data_49_V_we0 = 1'b0; + +assign data_49_V_we1 = 1'b0; + +assign data_4_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_4_V_address0; + +assign data_4_V_address1 = 3'd0; + +assign data_4_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_4_V_ce0; + +assign data_4_V_ce1 = 1'b0; + +assign data_4_V_d0 = 8'd0; + +assign data_4_V_d1 = 8'd0; + +assign data_4_V_we0 = 1'b0; + +assign data_4_V_we1 = 1'b0; + +assign data_50_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_50_V_address0; + +assign data_50_V_address1 = 3'd0; + +assign data_50_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_50_V_ce0; + +assign data_50_V_ce1 = 1'b0; + +assign data_50_V_d0 = 8'd0; + +assign data_50_V_d1 = 8'd0; + +assign data_50_V_we0 = 1'b0; + +assign data_50_V_we1 = 1'b0; + +assign data_51_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_51_V_address0; + +assign data_51_V_address1 = 3'd0; + +assign data_51_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_51_V_ce0; + +assign data_51_V_ce1 = 1'b0; + +assign data_51_V_d0 = 8'd0; + +assign data_51_V_d1 = 8'd0; + +assign data_51_V_we0 = 1'b0; + +assign data_51_V_we1 = 1'b0; + +assign data_52_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_52_V_address0; + +assign data_52_V_address1 = 3'd0; + +assign data_52_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_52_V_ce0; + +assign data_52_V_ce1 = 1'b0; + +assign data_52_V_d0 = 8'd0; + +assign data_52_V_d1 = 8'd0; + +assign data_52_V_we0 = 1'b0; + +assign data_52_V_we1 = 1'b0; + +assign data_53_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_53_V_address0; + +assign data_53_V_address1 = 3'd0; + +assign data_53_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_53_V_ce0; + +assign data_53_V_ce1 = 1'b0; + +assign data_53_V_d0 = 8'd0; + +assign data_53_V_d1 = 8'd0; + +assign data_53_V_we0 = 1'b0; + +assign data_53_V_we1 = 1'b0; + +assign data_54_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_54_V_address0; + +assign data_54_V_address1 = 3'd0; + +assign data_54_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_54_V_ce0; + +assign data_54_V_ce1 = 1'b0; + +assign data_54_V_d0 = 8'd0; + +assign data_54_V_d1 = 8'd0; + +assign data_54_V_we0 = 1'b0; + +assign data_54_V_we1 = 1'b0; + +assign data_55_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_55_V_address0; + +assign data_55_V_address1 = 3'd0; + +assign data_55_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_55_V_ce0; + +assign data_55_V_ce1 = 1'b0; + +assign data_55_V_d0 = 8'd0; + +assign data_55_V_d1 = 8'd0; + +assign data_55_V_we0 = 1'b0; + +assign data_55_V_we1 = 1'b0; + +assign data_56_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_56_V_address0; + +assign data_56_V_address1 = 3'd0; + +assign data_56_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_56_V_ce0; + +assign data_56_V_ce1 = 1'b0; + +assign data_56_V_d0 = 8'd0; + +assign data_56_V_d1 = 8'd0; + +assign data_56_V_we0 = 1'b0; + +assign data_56_V_we1 = 1'b0; + +assign data_57_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_57_V_address0; + +assign data_57_V_address1 = 3'd0; + +assign data_57_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_57_V_ce0; + +assign data_57_V_ce1 = 1'b0; + +assign data_57_V_d0 = 8'd0; + +assign data_57_V_d1 = 8'd0; + +assign data_57_V_we0 = 1'b0; + +assign data_57_V_we1 = 1'b0; + +assign data_58_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_58_V_address0; + +assign data_58_V_address1 = 3'd0; + +assign data_58_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_58_V_ce0; + +assign data_58_V_ce1 = 1'b0; + +assign data_58_V_d0 = 8'd0; + +assign data_58_V_d1 = 8'd0; + +assign data_58_V_we0 = 1'b0; + +assign data_58_V_we1 = 1'b0; + +assign data_59_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_59_V_address0; + +assign data_59_V_address1 = 3'd0; + +assign data_59_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_59_V_ce0; + +assign data_59_V_ce1 = 1'b0; + +assign data_59_V_d0 = 8'd0; + +assign data_59_V_d1 = 8'd0; + +assign data_59_V_we0 = 1'b0; + +assign data_59_V_we1 = 1'b0; + +assign data_5_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_5_V_address0; + +assign data_5_V_address1 = 3'd0; + +assign data_5_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_5_V_ce0; + +assign data_5_V_ce1 = 1'b0; + +assign data_5_V_d0 = 8'd0; + +assign data_5_V_d1 = 8'd0; + +assign data_5_V_we0 = 1'b0; + +assign data_5_V_we1 = 1'b0; + +assign data_60_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_60_V_address0; + +assign data_60_V_address1 = 3'd0; + +assign data_60_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_60_V_ce0; + +assign data_60_V_ce1 = 1'b0; + +assign data_60_V_d0 = 8'd0; + +assign data_60_V_d1 = 8'd0; + +assign data_60_V_we0 = 1'b0; + +assign data_60_V_we1 = 1'b0; + +assign data_61_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_61_V_address0; + +assign data_61_V_address1 = 3'd0; + +assign data_61_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_61_V_ce0; + +assign data_61_V_ce1 = 1'b0; + +assign data_61_V_d0 = 8'd0; + +assign data_61_V_d1 = 8'd0; + +assign data_61_V_we0 = 1'b0; + +assign data_61_V_we1 = 1'b0; + +assign data_62_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_62_V_address0; + +assign data_62_V_address1 = 3'd0; + +assign data_62_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_62_V_ce0; + +assign data_62_V_ce1 = 1'b0; + +assign data_62_V_d0 = 8'd0; + +assign data_62_V_d1 = 8'd0; + +assign data_62_V_we0 = 1'b0; + +assign data_62_V_we1 = 1'b0; + +assign data_63_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_63_V_address0; + +assign data_63_V_address1 = 3'd0; + +assign data_63_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_63_V_ce0; + +assign data_63_V_ce1 = 1'b0; + +assign data_63_V_d0 = 8'd0; + +assign data_63_V_d1 = 8'd0; + +assign data_63_V_we0 = 1'b0; + +assign data_63_V_we1 = 1'b0; + +assign data_64_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_64_V_address0; + +assign data_64_V_address1 = 3'd0; + +assign data_64_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_64_V_ce0; + +assign data_64_V_ce1 = 1'b0; + +assign data_64_V_d0 = 8'd0; + +assign data_64_V_d1 = 8'd0; + +assign data_64_V_we0 = 1'b0; + +assign data_64_V_we1 = 1'b0; + +assign data_65_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_65_V_address0; + +assign data_65_V_address1 = 3'd0; + +assign data_65_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_65_V_ce0; + +assign data_65_V_ce1 = 1'b0; + +assign data_65_V_d0 = 8'd0; + +assign data_65_V_d1 = 8'd0; + +assign data_65_V_we0 = 1'b0; + +assign data_65_V_we1 = 1'b0; + +assign data_66_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_66_V_address0; + +assign data_66_V_address1 = 3'd0; + +assign data_66_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_66_V_ce0; + +assign data_66_V_ce1 = 1'b0; + +assign data_66_V_d0 = 8'd0; + +assign data_66_V_d1 = 8'd0; + +assign data_66_V_we0 = 1'b0; + +assign data_66_V_we1 = 1'b0; + +assign data_67_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_67_V_address0; + +assign data_67_V_address1 = 3'd0; + +assign data_67_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_67_V_ce0; + +assign data_67_V_ce1 = 1'b0; + +assign data_67_V_d0 = 8'd0; + +assign data_67_V_d1 = 8'd0; + +assign data_67_V_we0 = 1'b0; + +assign data_67_V_we1 = 1'b0; + +assign data_68_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_68_V_address0; + +assign data_68_V_address1 = 3'd0; + +assign data_68_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_68_V_ce0; + +assign data_68_V_ce1 = 1'b0; + +assign data_68_V_d0 = 8'd0; + +assign data_68_V_d1 = 8'd0; + +assign data_68_V_we0 = 1'b0; + +assign data_68_V_we1 = 1'b0; + +assign data_69_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_69_V_address0; + +assign data_69_V_address1 = 3'd0; + +assign data_69_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_69_V_ce0; + +assign data_69_V_ce1 = 1'b0; + +assign data_69_V_d0 = 8'd0; + +assign data_69_V_d1 = 8'd0; + +assign data_69_V_we0 = 1'b0; + +assign data_69_V_we1 = 1'b0; + +assign data_6_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_6_V_address0; + +assign data_6_V_address1 = 3'd0; + +assign data_6_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_6_V_ce0; + +assign data_6_V_ce1 = 1'b0; + +assign data_6_V_d0 = 8'd0; + +assign data_6_V_d1 = 8'd0; + +assign data_6_V_we0 = 1'b0; + +assign data_6_V_we1 = 1'b0; + +assign data_70_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_70_V_address0; + +assign data_70_V_address1 = 3'd0; + +assign data_70_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_70_V_ce0; + +assign data_70_V_ce1 = 1'b0; + +assign data_70_V_d0 = 8'd0; + +assign data_70_V_d1 = 8'd0; + +assign data_70_V_we0 = 1'b0; + +assign data_70_V_we1 = 1'b0; + +assign data_71_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_71_V_address0; + +assign data_71_V_address1 = 3'd0; + +assign data_71_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_71_V_ce0; + +assign data_71_V_ce1 = 1'b0; + +assign data_71_V_d0 = 8'd0; + +assign data_71_V_d1 = 8'd0; + +assign data_71_V_we0 = 1'b0; + +assign data_71_V_we1 = 1'b0; + +assign data_72_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_72_V_address0; + +assign data_72_V_address1 = 3'd0; + +assign data_72_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_72_V_ce0; + +assign data_72_V_ce1 = 1'b0; + +assign data_72_V_d0 = 8'd0; + +assign data_72_V_d1 = 8'd0; + +assign data_72_V_we0 = 1'b0; + +assign data_72_V_we1 = 1'b0; + +assign data_73_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_73_V_address0; + +assign data_73_V_address1 = 3'd0; + +assign data_73_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_73_V_ce0; + +assign data_73_V_ce1 = 1'b0; + +assign data_73_V_d0 = 8'd0; + +assign data_73_V_d1 = 8'd0; + +assign data_73_V_we0 = 1'b0; + +assign data_73_V_we1 = 1'b0; + +assign data_74_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_74_V_address0; + +assign data_74_V_address1 = 3'd0; + +assign data_74_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_74_V_ce0; + +assign data_74_V_ce1 = 1'b0; + +assign data_74_V_d0 = 8'd0; + +assign data_74_V_d1 = 8'd0; + +assign data_74_V_we0 = 1'b0; + +assign data_74_V_we1 = 1'b0; + +assign data_75_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_75_V_address0; + +assign data_75_V_address1 = 3'd0; + +assign data_75_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_75_V_ce0; + +assign data_75_V_ce1 = 1'b0; + +assign data_75_V_d0 = 8'd0; + +assign data_75_V_d1 = 8'd0; + +assign data_75_V_we0 = 1'b0; + +assign data_75_V_we1 = 1'b0; + +assign data_76_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_76_V_address0; + +assign data_76_V_address1 = 2'd0; + +assign data_76_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_76_V_ce0; + +assign data_76_V_ce1 = 1'b0; + +assign data_76_V_d0 = 8'd0; + +assign data_76_V_d1 = 8'd0; + +assign data_76_V_we0 = 1'b0; + +assign data_76_V_we1 = 1'b0; + +assign data_77_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_77_V_address0; + +assign data_77_V_address1 = 2'd0; + +assign data_77_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_77_V_ce0; + +assign data_77_V_ce1 = 1'b0; + +assign data_77_V_d0 = 8'd0; + +assign data_77_V_d1 = 8'd0; + +assign data_77_V_we0 = 1'b0; + +assign data_77_V_we1 = 1'b0; + +assign data_78_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_78_V_address0; + +assign data_78_V_address1 = 2'd0; + +assign data_78_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_78_V_ce0; + +assign data_78_V_ce1 = 1'b0; + +assign data_78_V_d0 = 8'd0; + +assign data_78_V_d1 = 8'd0; + +assign data_78_V_we0 = 1'b0; + +assign data_78_V_we1 = 1'b0; + +assign data_79_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_79_V_address0; + +assign data_79_V_address1 = 2'd0; + +assign data_79_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_79_V_ce0; + +assign data_79_V_ce1 = 1'b0; + +assign data_79_V_d0 = 8'd0; + +assign data_79_V_d1 = 8'd0; + +assign data_79_V_we0 = 1'b0; + +assign data_79_V_we1 = 1'b0; + +assign data_7_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_7_V_address0; + +assign data_7_V_address1 = 3'd0; + +assign data_7_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_7_V_ce0; + +assign data_7_V_ce1 = 1'b0; + +assign data_7_V_d0 = 8'd0; + +assign data_7_V_d1 = 8'd0; + +assign data_7_V_we0 = 1'b0; + +assign data_7_V_we1 = 1'b0; + +assign data_80_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_80_V_address0; + +assign data_80_V_address1 = 2'd0; + +assign data_80_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_80_V_ce0; + +assign data_80_V_ce1 = 1'b0; + +assign data_80_V_d0 = 8'd0; + +assign data_80_V_d1 = 8'd0; + +assign data_80_V_we0 = 1'b0; + +assign data_80_V_we1 = 1'b0; + +assign data_81_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_81_V_address0; + +assign data_81_V_address1 = 2'd0; + +assign data_81_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_81_V_ce0; + +assign data_81_V_ce1 = 1'b0; + +assign data_81_V_d0 = 8'd0; + +assign data_81_V_d1 = 8'd0; + +assign data_81_V_we0 = 1'b0; + +assign data_81_V_we1 = 1'b0; + +assign data_82_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_82_V_address0; + +assign data_82_V_address1 = 2'd0; + +assign data_82_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_82_V_ce0; + +assign data_82_V_ce1 = 1'b0; + +assign data_82_V_d0 = 8'd0; + +assign data_82_V_d1 = 8'd0; + +assign data_82_V_we0 = 1'b0; + +assign data_82_V_we1 = 1'b0; + +assign data_83_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_83_V_address0; + +assign data_83_V_address1 = 2'd0; + +assign data_83_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_83_V_ce0; + +assign data_83_V_ce1 = 1'b0; + +assign data_83_V_d0 = 8'd0; + +assign data_83_V_d1 = 8'd0; + +assign data_83_V_we0 = 1'b0; + +assign data_83_V_we1 = 1'b0; + +assign data_84_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_84_V_address0; + +assign data_84_V_address1 = 2'd0; + +assign data_84_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_84_V_ce0; + +assign data_84_V_ce1 = 1'b0; + +assign data_84_V_d0 = 8'd0; + +assign data_84_V_d1 = 8'd0; + +assign data_84_V_we0 = 1'b0; + +assign data_84_V_we1 = 1'b0; + +assign data_85_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_85_V_address0; + +assign data_85_V_address1 = 2'd0; + +assign data_85_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_85_V_ce0; + +assign data_85_V_ce1 = 1'b0; + +assign data_85_V_d0 = 8'd0; + +assign data_85_V_d1 = 8'd0; + +assign data_85_V_we0 = 1'b0; + +assign data_85_V_we1 = 1'b0; + +assign data_86_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_86_V_address0; + +assign data_86_V_address1 = 2'd0; + +assign data_86_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_86_V_ce0; + +assign data_86_V_ce1 = 1'b0; + +assign data_86_V_d0 = 8'd0; + +assign data_86_V_d1 = 8'd0; + +assign data_86_V_we0 = 1'b0; + +assign data_86_V_we1 = 1'b0; + +assign data_87_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_87_V_address0; + +assign data_87_V_address1 = 2'd0; + +assign data_87_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_87_V_ce0; + +assign data_87_V_ce1 = 1'b0; + +assign data_87_V_d0 = 8'd0; + +assign data_87_V_d1 = 8'd0; + +assign data_87_V_we0 = 1'b0; + +assign data_87_V_we1 = 1'b0; + +assign data_88_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_88_V_address0; + +assign data_88_V_address1 = 2'd0; + +assign data_88_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_88_V_ce0; + +assign data_88_V_ce1 = 1'b0; + +assign data_88_V_d0 = 8'd0; + +assign data_88_V_d1 = 8'd0; + +assign data_88_V_we0 = 1'b0; + +assign data_88_V_we1 = 1'b0; + +assign data_89_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_89_V_address0; + +assign data_89_V_address1 = 2'd0; + +assign data_89_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_89_V_ce0; + +assign data_89_V_ce1 = 1'b0; + +assign data_89_V_d0 = 8'd0; + +assign data_89_V_d1 = 8'd0; + +assign data_89_V_we0 = 1'b0; + +assign data_89_V_we1 = 1'b0; + +assign data_8_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_8_V_address0; + +assign data_8_V_address1 = 3'd0; + +assign data_8_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_8_V_ce0; + +assign data_8_V_ce1 = 1'b0; + +assign data_8_V_d0 = 8'd0; + +assign data_8_V_d1 = 8'd0; + +assign data_8_V_we0 = 1'b0; + +assign data_8_V_we1 = 1'b0; + +assign data_90_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_90_V_address0; + +assign data_90_V_address1 = 2'd0; + +assign data_90_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_90_V_ce0; + +assign data_90_V_ce1 = 1'b0; + +assign data_90_V_d0 = 8'd0; + +assign data_90_V_d1 = 8'd0; + +assign data_90_V_we0 = 1'b0; + +assign data_90_V_we1 = 1'b0; + +assign data_91_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_91_V_address0; + +assign data_91_V_address1 = 2'd0; + +assign data_91_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_91_V_ce0; + +assign data_91_V_ce1 = 1'b0; + +assign data_91_V_d0 = 8'd0; + +assign data_91_V_d1 = 8'd0; + +assign data_91_V_we0 = 1'b0; + +assign data_91_V_we1 = 1'b0; + +assign data_92_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_92_V_address0; + +assign data_92_V_address1 = 2'd0; + +assign data_92_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_92_V_ce0; + +assign data_92_V_ce1 = 1'b0; + +assign data_92_V_d0 = 8'd0; + +assign data_92_V_d1 = 8'd0; + +assign data_92_V_we0 = 1'b0; + +assign data_92_V_we1 = 1'b0; + +assign data_93_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_93_V_address0; + +assign data_93_V_address1 = 2'd0; + +assign data_93_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_93_V_ce0; + +assign data_93_V_ce1 = 1'b0; + +assign data_93_V_d0 = 8'd0; + +assign data_93_V_d1 = 8'd0; + +assign data_93_V_we0 = 1'b0; + +assign data_93_V_we1 = 1'b0; + +assign data_94_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_94_V_address0; + +assign data_94_V_address1 = 2'd0; + +assign data_94_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_94_V_ce0; + +assign data_94_V_ce1 = 1'b0; + +assign data_94_V_d0 = 8'd0; + +assign data_94_V_d1 = 8'd0; + +assign data_94_V_we0 = 1'b0; + +assign data_94_V_we1 = 1'b0; + +assign data_95_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_95_V_address0; + +assign data_95_V_address1 = 2'd0; + +assign data_95_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_95_V_ce0; + +assign data_95_V_ce1 = 1'b0; + +assign data_95_V_d0 = 8'd0; + +assign data_95_V_d1 = 8'd0; + +assign data_95_V_we0 = 1'b0; + +assign data_95_V_we1 = 1'b0; + +assign data_96_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_96_V_address0; + +assign data_96_V_address1 = 2'd0; + +assign data_96_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_96_V_ce0; + +assign data_96_V_ce1 = 1'b0; + +assign data_96_V_d0 = 8'd0; + +assign data_96_V_d1 = 8'd0; + +assign data_96_V_we0 = 1'b0; + +assign data_96_V_we1 = 1'b0; + +assign data_97_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_97_V_address0; + +assign data_97_V_address1 = 2'd0; + +assign data_97_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_97_V_ce0; + +assign data_97_V_ce1 = 1'b0; + +assign data_97_V_d0 = 8'd0; + +assign data_97_V_d1 = 8'd0; + +assign data_97_V_we0 = 1'b0; + +assign data_97_V_we1 = 1'b0; + +assign data_98_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_98_V_address0; + +assign data_98_V_address1 = 2'd0; + +assign data_98_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_98_V_ce0; + +assign data_98_V_ce1 = 1'b0; + +assign data_98_V_d0 = 8'd0; + +assign data_98_V_d1 = 8'd0; + +assign data_98_V_we0 = 1'b0; + +assign data_98_V_we1 = 1'b0; + +assign data_99_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_99_V_address0; + +assign data_99_V_address1 = 2'd0; + +assign data_99_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_99_V_ce0; + +assign data_99_V_ce1 = 1'b0; + +assign data_99_V_d0 = 8'd0; + +assign data_99_V_d1 = 8'd0; + +assign data_99_V_we0 = 1'b0; + +assign data_99_V_we1 = 1'b0; + +assign data_9_V_address0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_9_V_address0; + +assign data_9_V_address1 = 3'd0; + +assign data_9_V_ce0 = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_data_9_V_ce0; + +assign data_9_V_ce1 = 1'b0; + +assign data_9_V_d0 = 8'd0; + +assign data_9_V_d1 = 8'd0; + +assign data_9_V_we0 = 1'b0; + +assign data_9_V_we1 = 1'b0; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_continue = (ap_sync_channel_write_p_0_0_loc_channel & ap_sync_channel_write_acc_9_V & ap_sync_channel_write_acc_8_V & ap_sync_channel_write_acc_7_V & ap_sync_channel_write_acc_6_V & ap_sync_channel_write_acc_5_V & ap_sync_channel_write_acc_4_V & ap_sync_channel_write_acc_3_V & ap_sync_channel_write_acc_2_V & ap_sync_channel_write_acc_1_V); + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_ap_start = start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_empty_n; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_start_full_n = 1'b1; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_start_write = 1'b0; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_continue = (ap_sync_continue & ap_sync_channel_write_acc_9_V_load_loc_channel); + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_ap_start = acc_9_V_empty_n; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_start_full_n = 1'b1; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_start_write = 1'b0; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_ap_continue = ap_sync_continue; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_ap_start = start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_empty_n; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_start_full_n = 1'b1; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_start_write = 1'b0; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_continue = (ap_sync_continue & ap_sync_channel_write_acc_1_V_load_loc_channel); + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_ap_start = acc_1_V_empty_n; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_start_full_n = 1'b1; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_start_write = 1'b0; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_continue = (ap_sync_continue & ap_sync_channel_write_acc_2_V_load_loc_channel); + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_ap_start = acc_2_V_empty_n; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_start_full_n = 1'b1; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_start_write = 1'b0; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_continue = (ap_sync_continue & ap_sync_channel_write_acc_3_V_load_loc_channel); + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_ap_start = acc_3_V_empty_n; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_start_full_n = 1'b1; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_start_write = 1'b0; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_continue = (ap_sync_continue & ap_sync_channel_write_acc_4_V_load_loc_channel); + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_ap_start = acc_4_V_empty_n; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_start_full_n = 1'b1; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_start_write = 1'b0; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_continue = (ap_sync_continue & ap_sync_channel_write_acc_5_V_load_loc_channel); + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_ap_start = acc_5_V_empty_n; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_start_full_n = 1'b1; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_start_write = 1'b0; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_continue = (ap_sync_continue & ap_sync_channel_write_acc_6_V_load_loc_channel); + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_ap_start = acc_6_V_empty_n; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_start_full_n = 1'b1; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_start_write = 1'b0; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_continue = (ap_sync_continue & ap_sync_channel_write_acc_7_V_load_loc_channel); + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_ap_start = acc_7_V_empty_n; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_start_full_n = 1'b1; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_start_write = 1'b0; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_continue = (ap_sync_continue & ap_sync_channel_write_acc_8_V_load_loc_channel); + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_ap_start = acc_8_V_empty_n; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_start_full_n = 1'b1; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_start_write = 1'b0; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_ap_continue = 1'b1; + +assign dense_latency_0_0_0_0_0_0_0_0_0_0_0_Loop_Product1_proc_U0_ap_start = ap_start; + +assign res_0_V = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_res_0_V; + +assign res_0_V_ap_vld = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_022_pro_U0_res_0_V_ap_vld; + +assign res_1_V = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_res_1_V; + +assign res_1_V_ap_vld = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_033_pro_U0_res_1_V_ap_vld; + +assign res_2_V = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_res_2_V; + +assign res_2_V_ap_vld = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_044_pro_U0_res_2_V_ap_vld; + +assign res_3_V = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_res_3_V; + +assign res_3_V_ap_vld = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_055_pro_U0_res_3_V_ap_vld; + +assign res_4_V = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_res_4_V; + +assign res_4_V_ap_vld = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_066_pro_U0_res_4_V_ap_vld; + +assign res_5_V = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_res_5_V; + +assign res_5_V_ap_vld = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_077_pro_U0_res_5_V_ap_vld; + +assign res_6_V = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_res_6_V; + +assign res_6_V_ap_vld = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_088_pro_U0_res_6_V_ap_vld; + +assign res_7_V = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_res_7_V; + +assign res_7_V_ap_vld = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_099_pro_U0_res_7_V_ap_vld; + +assign res_8_V = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_res_8_V; + +assign res_8_V_ap_vld = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0110_pr_U0_res_8_V_ap_vld; + +assign res_9_V = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_res_9_V; + +assign res_9_V_ap_vld = dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_res_9_V_ap_vld; + +assign start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader70_0_pro_U0_din = 1'b1; + +assign start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_preheader_0121_pr_U0_din = 1'b1; + +endmodule //dense_latency_0_0_0_0_0_0_0_0_0_0_0 +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module fifo_w7_d1_A_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd7; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd1; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0; +reg [DATA_WIDTH-1:0] q_tmp; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + + + end + end + +always @( sr_0, a) begin + case (a) + 0: q_tmp = sr_0; + default: q_tmp = sr_0; + endcase +end + +assign q = q_tmp; + +endmodule + +module fifo_w7_d1_A ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "auto"; +parameter DATA_WIDTH = 32'd7; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd1; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +fifo_w7_d1_A_shiftReg +#( + .DATA_WIDTH(DATA_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DEPTH(DEPTH)) +U_fifo_w7_d1_A_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module fifo_w8_d2_A_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +reg [DATA_WIDTH-1:0] q_tmp; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q_tmp = sr_0; + 1'd1: q_tmp = sr_1; + default: q_tmp = sr_1; + endcase +end + +assign q = q_tmp; + +endmodule + +module fifo_w8_d2_A ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +fifo_w8_d2_A_shiftReg +#( + .DATA_WIDTH(DATA_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DEPTH(DEPTH)) +U_fifo_w8_d2_A_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module myproject_layer2_out_0_V_ram (addr0, ce0, d0, we0, q0, clk); + +parameter DWIDTH = 8; +parameter AWIDTH = 5; +parameter MEM_SIZE = 25; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module myproject_layer2_out_0_V( + reset, + clk, + address0, + ce0, + we0, + d0, + q0); + +parameter DataWidth = 32'd8; +parameter AddressRange = 32'd25; +parameter AddressWidth = 32'd5; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; + + + +myproject_layer2_out_0_V_ram myproject_layer2_out_0_V_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module myproject_layer2_out_64_V_ram (addr0, ce0, d0, we0, q0, clk); + +parameter DWIDTH = 8; +parameter AWIDTH = 5; +parameter MEM_SIZE = 24; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module myproject_layer2_out_64_V( + reset, + clk, + address0, + ce0, + we0, + d0, + q0); + +parameter DataWidth = 32'd8; +parameter AddressRange = 32'd24; +parameter AddressWidth = 32'd5; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; + + + +myproject_layer2_out_64_V_ram myproject_layer2_out_64_V_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module myproject_layer4_out_0_V_ram (addr0, ce0, d0, we0, q0, clk); + +parameter DWIDTH = 8; +parameter AWIDTH = 3; +parameter MEM_SIZE = 7; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module myproject_layer4_out_0_V( + reset, + clk, + address0, + ce0, + we0, + d0, + q0); + +parameter DataWidth = 32'd8; +parameter AddressRange = 32'd7; +parameter AddressWidth = 32'd3; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; + + + +myproject_layer4_out_0_V_ram myproject_layer4_out_0_V_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module myproject_layer4_out_16_V_ram (addr0, ce0, d0, we0, q0, clk); + +parameter DWIDTH = 8; +parameter AWIDTH = 3; +parameter MEM_SIZE = 6; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module myproject_layer4_out_16_V( + reset, + clk, + address0, + ce0, + we0, + d0, + q0); + +parameter DataWidth = 32'd8; +parameter AddressRange = 32'd6; +parameter AddressWidth = 32'd3; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; + + + +myproject_layer4_out_16_V_ram myproject_layer4_out_16_V_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module myproject_layer5_out_0_V_ram (addr0, ce0, d0, we0, q0, clk); + +parameter DWIDTH = 8; +parameter AWIDTH = 5; +parameter MEM_SIZE = 19; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module myproject_layer5_out_0_V( + reset, + clk, + address0, + ce0, + we0, + d0, + q0); + +parameter DataWidth = 32'd8; +parameter AddressRange = 32'd19; +parameter AddressWidth = 32'd5; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; + + + +myproject_layer5_out_0_V_ram myproject_layer5_out_0_V_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module myproject_layer5_out_48_V_ram (addr0, ce0, d0, we0, q0, clk); + +parameter DWIDTH = 8; +parameter AWIDTH = 5; +parameter MEM_SIZE = 18; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module myproject_layer5_out_48_V( + reset, + clk, + address0, + ce0, + we0, + d0, + q0); + +parameter DataWidth = 32'd8; +parameter AddressRange = 32'd18; +parameter AddressWidth = 32'd5; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; + + + +myproject_layer5_out_48_V_ram myproject_layer5_out_48_V_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module myproject_layer7_out_0_V_ram (addr0, ce0, d0, we0, q0, clk); + +parameter DWIDTH = 8; +parameter AWIDTH = 3; +parameter MEM_SIZE = 5; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module myproject_layer7_out_0_V( + reset, + clk, + address0, + ce0, + we0, + d0, + q0); + +parameter DataWidth = 32'd8; +parameter AddressRange = 32'd5; +parameter AddressWidth = 32'd3; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; + + + +myproject_layer7_out_0_V_ram myproject_layer7_out_0_V_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_12ns_4ns_18ns_18_1_1_DSP48_9( + input [12 - 1:0] in0, + input [4 - 1:0] in1, + input [18 - 1:0] in2, + output [18 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_12ns_4ns_18ns_18_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_12ns_4ns_18ns_18_1_1_DSP48_9 myproject_mac_muladd_12ns_4ns_18ns_18_1_1_DSP48_9_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_12ns_4ns_19ns_19_1_1_DSP48_13( + input [12 - 1:0] in0, + input [4 - 1:0] in1, + input [19 - 1:0] in2, + output [19 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_12ns_4ns_19ns_19_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_12ns_4ns_19ns_19_1_1_DSP48_13 myproject_mac_muladd_12ns_4ns_19ns_19_1_1_DSP48_13_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_2ns_6ns_18ns_18_1_1_DSP48_6( + input [2 - 1:0] in0, + input [6 - 1:0] in1, + input [18 - 1:0] in2, + output [18 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_2ns_6ns_18ns_18_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_2ns_6ns_18ns_18_1_1_DSP48_6 myproject_mac_muladd_2ns_6ns_18ns_18_1_1_DSP48_6_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_2ns_6ns_19ns_19_1_1_DSP48_8( + input [2 - 1:0] in0, + input [6 - 1:0] in1, + input [19 - 1:0] in2, + output [19 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_2ns_6ns_19ns_19_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_2ns_6ns_19ns_19_1_1_DSP48_8 myproject_mac_muladd_2ns_6ns_19ns_19_1_1_DSP48_8_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_3ns_6ns_17ns_17_1_1_DSP48_3( + input [3 - 1:0] in0, + input [6 - 1:0] in1, + input [17 - 1:0] in2, + output [17 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_3ns_6ns_17ns_17_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_3ns_6ns_17ns_17_1_1_DSP48_3 myproject_mac_muladd_3ns_6ns_17ns_17_1_1_DSP48_3_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_3ns_6ns_18ns_18_1_1_DSP48_11( + input [3 - 1:0] in0, + input [6 - 1:0] in1, + input [18 - 1:0] in2, + output [18 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_3ns_6ns_18ns_18_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_3ns_6ns_18ns_18_1_1_DSP48_11 myproject_mac_muladd_3ns_6ns_18ns_18_1_1_DSP48_11_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_3ns_6ns_19ns_19_1_1_DSP48_15( + input [3 - 1:0] in0, + input [6 - 1:0] in1, + input [19 - 1:0] in2, + output [19 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_3ns_6ns_19ns_19_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_3ns_6ns_19ns_19_1_1_DSP48_15 myproject_mac_muladd_3ns_6ns_19ns_19_1_1_DSP48_15_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_4ns_8ns_18ns_18_1_1_DSP48_10( + input [4 - 1:0] in0, + input [8 - 1:0] in1, + input [18 - 1:0] in2, + output [18 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_4ns_8ns_18ns_18_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_4ns_8ns_18ns_18_1_1_DSP48_10 myproject_mac_muladd_4ns_8ns_18ns_18_1_1_DSP48_10_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_4ns_8ns_19ns_19_1_1_DSP48_14( + input [4 - 1:0] in0, + input [8 - 1:0] in1, + input [19 - 1:0] in2, + output [19 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_4ns_8ns_19ns_19_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_4ns_8ns_19ns_19_1_1_DSP48_14 myproject_mac_muladd_4ns_8ns_19ns_19_1_1_DSP48_14_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_6ns_2ns_17ns_17_1_1_DSP48_4( + input [6 - 1:0] in0, + input [2 - 1:0] in1, + input [17 - 1:0] in2, + output [17 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_6ns_2ns_17ns_17_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_6ns_2ns_17ns_17_1_1_DSP48_4 myproject_mac_muladd_6ns_2ns_17ns_17_1_1_DSP48_4_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_6ns_2ns_18ns_18_1_1_DSP48_12( + input [6 - 1:0] in0, + input [2 - 1:0] in1, + input [18 - 1:0] in2, + output [18 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_6ns_2ns_18ns_18_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_6ns_2ns_18ns_18_1_1_DSP48_12 myproject_mac_muladd_6ns_2ns_18ns_18_1_1_DSP48_12_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_6ns_2ns_19ns_19_1_1_DSP48_16( + input [6 - 1:0] in0, + input [2 - 1:0] in1, + input [19 - 1:0] in2, + output [19 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_6ns_2ns_19ns_19_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_6ns_2ns_19ns_19_1_1_DSP48_16 myproject_mac_muladd_6ns_2ns_19ns_19_1_1_DSP48_16_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_6ns_3ns_18ns_18_1_1_DSP48_5( + input [6 - 1:0] in0, + input [3 - 1:0] in1, + input [18 - 1:0] in2, + output [18 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_6ns_3ns_18ns_18_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_6ns_3ns_18ns_18_1_1_DSP48_5 myproject_mac_muladd_6ns_3ns_18ns_18_1_1_DSP48_5_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_6ns_3ns_19ns_19_1_1_DSP48_7( + input [6 - 1:0] in0, + input [3 - 1:0] in1, + input [19 - 1:0] in2, + output [19 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_6ns_3ns_19ns_19_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_6ns_3ns_19ns_19_1_1_DSP48_7 myproject_mac_muladd_6ns_3ns_19ns_19_1_1_DSP48_7_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_8ns_3ns_4ns_10_1_1_DSP48_17( + input [8 - 1:0] in0, + input [3 - 1:0] in1, + input [4 - 1:0] in2, + output [10 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_8ns_3ns_4ns_10_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_8ns_3ns_4ns_10_1_1_DSP48_17 myproject_mac_muladd_8ns_3ns_4ns_10_1_1_DSP48_17_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_8ns_5ns_17ns_17_1_1_DSP48_2( + input [8 - 1:0] in0, + input [5 - 1:0] in1, + input [17 - 1:0] in2, + output [17 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_8ns_5ns_17ns_17_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_8ns_5ns_17ns_17_1_1_DSP48_2 myproject_mac_muladd_8ns_5ns_17ns_17_1_1_DSP48_2_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module myproject_mac_muladd_9ns_4ns_4ns_12_1_1_DSP48_18( + input [9 - 1:0] in0, + input [4 - 1:0] in1, + input [4 - 1:0] in2, + output [12 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a * b; +assign p = m + c; + +assign dout = p; + +endmodule +`timescale 1 ns / 1 ps +module myproject_mac_muladd_9ns_4ns_4ns_12_1_1( + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mac_muladd_9ns_4ns_4ns_12_1_1_DSP48_18 myproject_mac_muladd_9ns_4ns_4ns_12_1_1_DSP48_18_U( + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module myproject_mul_32ns_34ns_65_2_1_MulnS_1(clk, ce, a, b, p); +input clk; +input ce; +input [32 - 1 : 0] a; +input [34 - 1 : 0] b; +output[65 - 1 : 0] p; +reg [65 - 1 : 0] p; +wire [65 - 1 : 0] tmp_product; + +assign tmp_product = a * b; +always @ (posedge clk) begin + if (ce) begin + p <= tmp_product; + end +end +endmodule +`timescale 1 ns / 1 ps +module myproject_mul_32ns_34ns_65_2_1( + clk, + reset, + ce, + din0, + din1, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input clk; +input reset; +input ce; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mul_32ns_34ns_65_2_1_MulnS_1 myproject_mul_32ns_34ns_65_2_1_MulnS_1_U( + .clk( clk ), + .ce( ce ), + .a( din0 ), + .b( din1 ), + .p( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module myproject_mul_34ns_32ns_65_2_1_MulnS_0(clk, ce, a, b, p); +input clk; +input ce; +input [34 - 1 : 0] a; +input [32 - 1 : 0] b; +output[65 - 1 : 0] p; +reg [65 - 1 : 0] p; +wire [65 - 1 : 0] tmp_product; + +assign tmp_product = a * b; +always @ (posedge clk) begin + if (ce) begin + p <= tmp_product; + end +end +endmodule +`timescale 1 ns / 1 ps +module myproject_mul_34ns_32ns_65_2_1( + clk, + reset, + ce, + din0, + din1, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input clk; +input reset; +input ce; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mul_34ns_32ns_65_2_1_MulnS_0 myproject_mul_34ns_32ns_65_2_1_MulnS_0_U( + .clk( clk ), + .ce( ce ), + .a( din0 ), + .b( din1 ), + .p( dout ) +); + +endmodule + + +`timescale 1 ns / 1 ps + + module myproject_mul_mul_13ns_5ns_17_1_1_DSP48_1(a, b, p); +input [13 - 1 : 0] a; +input [5 - 1 : 0] b; +output [17 - 1 : 0] p; + +assign p = (a) * (b); + +endmodule +`timescale 1 ns / 1 ps +module myproject_mul_mul_13ns_5ns_17_1_1( + din0, + din1, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mul_mul_13ns_5ns_17_1_1_DSP48_1 myproject_mul_mul_13ns_5ns_17_1_1_DSP48_1_U( + .a( din0 ), + .b( din1 ), + .p( dout ) +); + +endmodule + + +`timescale 1 ns / 1 ps + + module myproject_mul_mul_5ns_13ns_17_1_1_DSP48_0(a, b, p); +input [5 - 1 : 0] a; +input [13 - 1 : 0] b; +output [17 - 1 : 0] p; + +assign p = (a) * (b); + +endmodule +`timescale 1 ns / 1 ps +module myproject_mul_mul_5ns_13ns_17_1_1( + din0, + din1, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +output[dout_WIDTH - 1:0] dout; + + + +myproject_mul_mul_5ns_13ns_17_1_1_DSP48_0 myproject_mul_mul_5ns_13ns_17_1_1_DSP48_0_U( + .a( din0 ), + .b( din1 ), + .p( dout ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module myproject_mux_164_8_1_1 #( +parameter + ID = 0, + NUM_STAGE = 1, + din0_WIDTH = 32, + din1_WIDTH = 32, + din2_WIDTH = 32, + din3_WIDTH = 32, + din4_WIDTH = 32, + din5_WIDTH = 32, + din6_WIDTH = 32, + din7_WIDTH = 32, + din8_WIDTH = 32, + din9_WIDTH = 32, + din10_WIDTH = 32, + din11_WIDTH = 32, + din12_WIDTH = 32, + din13_WIDTH = 32, + din14_WIDTH = 32, + din15_WIDTH = 32, + din16_WIDTH = 32, + dout_WIDTH = 32 +)( + input [7 : 0] din0, + input [7 : 0] din1, + input [7 : 0] din2, + input [7 : 0] din3, + input [7 : 0] din4, + input [7 : 0] din5, + input [7 : 0] din6, + input [7 : 0] din7, + input [7 : 0] din8, + input [7 : 0] din9, + input [7 : 0] din10, + input [7 : 0] din11, + input [7 : 0] din12, + input [7 : 0] din13, + input [7 : 0] din14, + input [7 : 0] din15, + input [3 : 0] din16, + output [7 : 0] dout); + +// puts internal signals +wire [3 : 0] sel; +// level 1 signals +wire [7 : 0] mux_1_0; +wire [7 : 0] mux_1_1; +wire [7 : 0] mux_1_2; +wire [7 : 0] mux_1_3; +wire [7 : 0] mux_1_4; +wire [7 : 0] mux_1_5; +wire [7 : 0] mux_1_6; +wire [7 : 0] mux_1_7; +// level 2 signals +wire [7 : 0] mux_2_0; +wire [7 : 0] mux_2_1; +wire [7 : 0] mux_2_2; +wire [7 : 0] mux_2_3; +// level 3 signals +wire [7 : 0] mux_3_0; +wire [7 : 0] mux_3_1; +// level 4 signals +wire [7 : 0] mux_4_0; + +assign sel = din16; + +// Generate level 1 logic +assign mux_1_0 = (sel[0] == 0)? din0 : din1; +assign mux_1_1 = (sel[0] == 0)? din2 : din3; +assign mux_1_2 = (sel[0] == 0)? din4 : din5; +assign mux_1_3 = (sel[0] == 0)? din6 : din7; +assign mux_1_4 = (sel[0] == 0)? din8 : din9; +assign mux_1_5 = (sel[0] == 0)? din10 : din11; +assign mux_1_6 = (sel[0] == 0)? din12 : din13; +assign mux_1_7 = (sel[0] == 0)? din14 : din15; + +// Generate level 2 logic +assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1; +assign mux_2_1 = (sel[1] == 0)? mux_1_2 : mux_1_3; +assign mux_2_2 = (sel[1] == 0)? mux_1_4 : mux_1_5; +assign mux_2_3 = (sel[1] == 0)? mux_1_6 : mux_1_7; + +// Generate level 3 logic +assign mux_3_0 = (sel[2] == 0)? mux_2_0 : mux_2_1; +assign mux_3_1 = (sel[2] == 0)? mux_2_2 : mux_2_3; + +// Generate level 4 logic +assign mux_4_0 = (sel[3] == 0)? mux_3_0 : mux_3_1; + +// output logic +assign dout = mux_4_0; + +endmodule +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module myproject_mux_2832_8_1_1 #( +parameter + ID = 0, + NUM_STAGE = 1, + din0_WIDTH = 32, + din1_WIDTH = 32, + din2_WIDTH = 32, + din3_WIDTH = 32, + din4_WIDTH = 32, + din5_WIDTH = 32, + din6_WIDTH = 32, + din7_WIDTH = 32, + din8_WIDTH = 32, + din9_WIDTH = 32, + din10_WIDTH = 32, + din11_WIDTH = 32, + din12_WIDTH = 32, + din13_WIDTH = 32, + din14_WIDTH = 32, + din15_WIDTH = 32, + din16_WIDTH = 32, + din17_WIDTH = 32, + din18_WIDTH = 32, + din19_WIDTH = 32, + din20_WIDTH = 32, + din21_WIDTH = 32, + din22_WIDTH = 32, + din23_WIDTH = 32, + din24_WIDTH = 32, + din25_WIDTH = 32, + din26_WIDTH = 32, + din27_WIDTH = 32, + din28_WIDTH = 32, + dout_WIDTH = 32 +)( + input [7 : 0] din0, + input [7 : 0] din1, + input [7 : 0] din2, + input [7 : 0] din3, + input [7 : 0] din4, + input [7 : 0] din5, + input [7 : 0] din6, + input [7 : 0] din7, + input [7 : 0] din8, + input [7 : 0] din9, + input [7 : 0] din10, + input [7 : 0] din11, + input [7 : 0] din12, + input [7 : 0] din13, + input [7 : 0] din14, + input [7 : 0] din15, + input [7 : 0] din16, + input [7 : 0] din17, + input [7 : 0] din18, + input [7 : 0] din19, + input [7 : 0] din20, + input [7 : 0] din21, + input [7 : 0] din22, + input [7 : 0] din23, + input [7 : 0] din24, + input [7 : 0] din25, + input [7 : 0] din26, + input [7 : 0] din27, + input [31 : 0] din28, + output [7 : 0] dout); + +// puts internal signals +wire [31 : 0] sel; +// level 1 signals +wire [7 : 0] mux_1_0; +wire [7 : 0] mux_1_1; +wire [7 : 0] mux_1_2; +wire [7 : 0] mux_1_3; +wire [7 : 0] mux_1_4; +wire [7 : 0] mux_1_5; +wire [7 : 0] mux_1_6; +wire [7 : 0] mux_1_7; +wire [7 : 0] mux_1_8; +wire [7 : 0] mux_1_9; +wire [7 : 0] mux_1_10; +wire [7 : 0] mux_1_11; +wire [7 : 0] mux_1_12; +wire [7 : 0] mux_1_13; +// level 2 signals +wire [7 : 0] mux_2_0; +wire [7 : 0] mux_2_1; +wire [7 : 0] mux_2_2; +wire [7 : 0] mux_2_3; +wire [7 : 0] mux_2_4; +wire [7 : 0] mux_2_5; +wire [7 : 0] mux_2_6; +// level 3 signals +wire [7 : 0] mux_3_0; +wire [7 : 0] mux_3_1; +wire [7 : 0] mux_3_2; +wire [7 : 0] mux_3_3; +// level 4 signals +wire [7 : 0] mux_4_0; +wire [7 : 0] mux_4_1; +// level 5 signals +wire [7 : 0] mux_5_0; +// level 6 signals +wire [7 : 0] mux_6_0; +// level 7 signals +wire [7 : 0] mux_7_0; +// level 8 signals +wire [7 : 0] mux_8_0; +// level 9 signals +wire [7 : 0] mux_9_0; +// level 10 signals +wire [7 : 0] mux_10_0; +// level 11 signals +wire [7 : 0] mux_11_0; +// level 12 signals +wire [7 : 0] mux_12_0; +// level 13 signals +wire [7 : 0] mux_13_0; +// level 14 signals +wire [7 : 0] mux_14_0; +// level 15 signals +wire [7 : 0] mux_15_0; +// level 16 signals +wire [7 : 0] mux_16_0; +// level 17 signals +wire [7 : 0] mux_17_0; +// level 18 signals +wire [7 : 0] mux_18_0; +// level 19 signals +wire [7 : 0] mux_19_0; +// level 20 signals +wire [7 : 0] mux_20_0; +// level 21 signals +wire [7 : 0] mux_21_0; +// level 22 signals +wire [7 : 0] mux_22_0; +// level 23 signals +wire [7 : 0] mux_23_0; +// level 24 signals +wire [7 : 0] mux_24_0; +// level 25 signals +wire [7 : 0] mux_25_0; +// level 26 signals +wire [7 : 0] mux_26_0; +// level 27 signals +wire [7 : 0] mux_27_0; +// level 28 signals +wire [7 : 0] mux_28_0; +// level 29 signals +wire [7 : 0] mux_29_0; +// level 30 signals +wire [7 : 0] mux_30_0; +// level 31 signals +wire [7 : 0] mux_31_0; +// level 32 signals +wire [7 : 0] mux_32_0; + +assign sel = din28; + +// Generate level 1 logic +assign mux_1_0 = (sel[0] == 0)? din0 : din1; +assign mux_1_1 = (sel[0] == 0)? din2 : din3; +assign mux_1_2 = (sel[0] == 0)? din4 : din5; +assign mux_1_3 = (sel[0] == 0)? din6 : din7; +assign mux_1_4 = (sel[0] == 0)? din8 : din9; +assign mux_1_5 = (sel[0] == 0)? din10 : din11; +assign mux_1_6 = (sel[0] == 0)? din12 : din13; +assign mux_1_7 = (sel[0] == 0)? din14 : din15; +assign mux_1_8 = (sel[0] == 0)? din16 : din17; +assign mux_1_9 = (sel[0] == 0)? din18 : din19; +assign mux_1_10 = (sel[0] == 0)? din20 : din21; +assign mux_1_11 = (sel[0] == 0)? din22 : din23; +assign mux_1_12 = (sel[0] == 0)? din24 : din25; +assign mux_1_13 = (sel[0] == 0)? din26 : din27; + +// Generate level 2 logic +assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1; +assign mux_2_1 = (sel[1] == 0)? mux_1_2 : mux_1_3; +assign mux_2_2 = (sel[1] == 0)? mux_1_4 : mux_1_5; +assign mux_2_3 = (sel[1] == 0)? mux_1_6 : mux_1_7; +assign mux_2_4 = (sel[1] == 0)? mux_1_8 : mux_1_9; +assign mux_2_5 = (sel[1] == 0)? mux_1_10 : mux_1_11; +assign mux_2_6 = (sel[1] == 0)? mux_1_12 : mux_1_13; + +// Generate level 3 logic +assign mux_3_0 = (sel[2] == 0)? mux_2_0 : mux_2_1; +assign mux_3_1 = (sel[2] == 0)? mux_2_2 : mux_2_3; +assign mux_3_2 = (sel[2] == 0)? mux_2_4 : mux_2_5; +assign mux_3_3 = mux_2_6; + +// Generate level 4 logic +assign mux_4_0 = (sel[3] == 0)? mux_3_0 : mux_3_1; +assign mux_4_1 = (sel[3] == 0)? mux_3_2 : mux_3_3; + +// Generate level 5 logic +assign mux_5_0 = (sel[4] == 0)? mux_4_0 : mux_4_1; + +// Generate level 6 logic +assign mux_6_0 = mux_5_0; + +// Generate level 7 logic +assign mux_7_0 = mux_6_0; + +// Generate level 8 logic +assign mux_8_0 = mux_7_0; + +// Generate level 9 logic +assign mux_9_0 = mux_8_0; + +// Generate level 10 logic +assign mux_10_0 = mux_9_0; + +// Generate level 11 logic +assign mux_11_0 = mux_10_0; + +// Generate level 12 logic +assign mux_12_0 = mux_11_0; + +// Generate level 13 logic +assign mux_13_0 = mux_12_0; + +// Generate level 14 logic +assign mux_14_0 = mux_13_0; + +// Generate level 15 logic +assign mux_15_0 = mux_14_0; + +// Generate level 16 logic +assign mux_16_0 = mux_15_0; + +// Generate level 17 logic +assign mux_17_0 = mux_16_0; + +// Generate level 18 logic +assign mux_18_0 = mux_17_0; + +// Generate level 19 logic +assign mux_19_0 = mux_18_0; + +// Generate level 20 logic +assign mux_20_0 = mux_19_0; + +// Generate level 21 logic +assign mux_21_0 = mux_20_0; + +// Generate level 22 logic +assign mux_22_0 = mux_21_0; + +// Generate level 23 logic +assign mux_23_0 = mux_22_0; + +// Generate level 24 logic +assign mux_24_0 = mux_23_0; + +// Generate level 25 logic +assign mux_25_0 = mux_24_0; + +// Generate level 26 logic +assign mux_26_0 = mux_25_0; + +// Generate level 27 logic +assign mux_27_0 = mux_26_0; + +// Generate level 28 logic +assign mux_28_0 = mux_27_0; + +// Generate level 29 logic +assign mux_29_0 = mux_28_0; + +// Generate level 30 logic +assign mux_30_0 = mux_29_0; + +// Generate level 31 logic +assign mux_31_0 = mux_30_0; + +// Generate level 32 logic +assign mux_32_0 = mux_31_0; + +// output logic +assign dout = mux_32_0; + +endmodule +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module myproject_mux_6432_8_1_1 #( +parameter + ID = 0, + NUM_STAGE = 1, + din0_WIDTH = 32, + din1_WIDTH = 32, + din2_WIDTH = 32, + din3_WIDTH = 32, + din4_WIDTH = 32, + din5_WIDTH = 32, + din6_WIDTH = 32, + din7_WIDTH = 32, + din8_WIDTH = 32, + din9_WIDTH = 32, + din10_WIDTH = 32, + din11_WIDTH = 32, + din12_WIDTH = 32, + din13_WIDTH = 32, + din14_WIDTH = 32, + din15_WIDTH = 32, + din16_WIDTH = 32, + din17_WIDTH = 32, + din18_WIDTH = 32, + din19_WIDTH = 32, + din20_WIDTH = 32, + din21_WIDTH = 32, + din22_WIDTH = 32, + din23_WIDTH = 32, + din24_WIDTH = 32, + din25_WIDTH = 32, + din26_WIDTH = 32, + din27_WIDTH = 32, + din28_WIDTH = 32, + din29_WIDTH = 32, + din30_WIDTH = 32, + din31_WIDTH = 32, + din32_WIDTH = 32, + din33_WIDTH = 32, + din34_WIDTH = 32, + din35_WIDTH = 32, + din36_WIDTH = 32, + din37_WIDTH = 32, + din38_WIDTH = 32, + din39_WIDTH = 32, + din40_WIDTH = 32, + din41_WIDTH = 32, + din42_WIDTH = 32, + din43_WIDTH = 32, + din44_WIDTH = 32, + din45_WIDTH = 32, + din46_WIDTH = 32, + din47_WIDTH = 32, + din48_WIDTH = 32, + din49_WIDTH = 32, + din50_WIDTH = 32, + din51_WIDTH = 32, + din52_WIDTH = 32, + din53_WIDTH = 32, + din54_WIDTH = 32, + din55_WIDTH = 32, + din56_WIDTH = 32, + din57_WIDTH = 32, + din58_WIDTH = 32, + din59_WIDTH = 32, + din60_WIDTH = 32, + din61_WIDTH = 32, + din62_WIDTH = 32, + din63_WIDTH = 32, + din64_WIDTH = 32, + dout_WIDTH = 32 +)( + input [7 : 0] din0, + input [7 : 0] din1, + input [7 : 0] din2, + input [7 : 0] din3, + input [7 : 0] din4, + input [7 : 0] din5, + input [7 : 0] din6, + input [7 : 0] din7, + input [7 : 0] din8, + input [7 : 0] din9, + input [7 : 0] din10, + input [7 : 0] din11, + input [7 : 0] din12, + input [7 : 0] din13, + input [7 : 0] din14, + input [7 : 0] din15, + input [7 : 0] din16, + input [7 : 0] din17, + input [7 : 0] din18, + input [7 : 0] din19, + input [7 : 0] din20, + input [7 : 0] din21, + input [7 : 0] din22, + input [7 : 0] din23, + input [7 : 0] din24, + input [7 : 0] din25, + input [7 : 0] din26, + input [7 : 0] din27, + input [7 : 0] din28, + input [7 : 0] din29, + input [7 : 0] din30, + input [7 : 0] din31, + input [7 : 0] din32, + input [7 : 0] din33, + input [7 : 0] din34, + input [7 : 0] din35, + input [7 : 0] din36, + input [7 : 0] din37, + input [7 : 0] din38, + input [7 : 0] din39, + input [7 : 0] din40, + input [7 : 0] din41, + input [7 : 0] din42, + input [7 : 0] din43, + input [7 : 0] din44, + input [7 : 0] din45, + input [7 : 0] din46, + input [7 : 0] din47, + input [7 : 0] din48, + input [7 : 0] din49, + input [7 : 0] din50, + input [7 : 0] din51, + input [7 : 0] din52, + input [7 : 0] din53, + input [7 : 0] din54, + input [7 : 0] din55, + input [7 : 0] din56, + input [7 : 0] din57, + input [7 : 0] din58, + input [7 : 0] din59, + input [7 : 0] din60, + input [7 : 0] din61, + input [7 : 0] din62, + input [7 : 0] din63, + input [31 : 0] din64, + output [7 : 0] dout); + +// puts internal signals +wire [31 : 0] sel; +// level 1 signals +wire [7 : 0] mux_1_0; +wire [7 : 0] mux_1_1; +wire [7 : 0] mux_1_2; +wire [7 : 0] mux_1_3; +wire [7 : 0] mux_1_4; +wire [7 : 0] mux_1_5; +wire [7 : 0] mux_1_6; +wire [7 : 0] mux_1_7; +wire [7 : 0] mux_1_8; +wire [7 : 0] mux_1_9; +wire [7 : 0] mux_1_10; +wire [7 : 0] mux_1_11; +wire [7 : 0] mux_1_12; +wire [7 : 0] mux_1_13; +wire [7 : 0] mux_1_14; +wire [7 : 0] mux_1_15; +wire [7 : 0] mux_1_16; +wire [7 : 0] mux_1_17; +wire [7 : 0] mux_1_18; +wire [7 : 0] mux_1_19; +wire [7 : 0] mux_1_20; +wire [7 : 0] mux_1_21; +wire [7 : 0] mux_1_22; +wire [7 : 0] mux_1_23; +wire [7 : 0] mux_1_24; +wire [7 : 0] mux_1_25; +wire [7 : 0] mux_1_26; +wire [7 : 0] mux_1_27; +wire [7 : 0] mux_1_28; +wire [7 : 0] mux_1_29; +wire [7 : 0] mux_1_30; +wire [7 : 0] mux_1_31; +// level 2 signals +wire [7 : 0] mux_2_0; +wire [7 : 0] mux_2_1; +wire [7 : 0] mux_2_2; +wire [7 : 0] mux_2_3; +wire [7 : 0] mux_2_4; +wire [7 : 0] mux_2_5; +wire [7 : 0] mux_2_6; +wire [7 : 0] mux_2_7; +wire [7 : 0] mux_2_8; +wire [7 : 0] mux_2_9; +wire [7 : 0] mux_2_10; +wire [7 : 0] mux_2_11; +wire [7 : 0] mux_2_12; +wire [7 : 0] mux_2_13; +wire [7 : 0] mux_2_14; +wire [7 : 0] mux_2_15; +// level 3 signals +wire [7 : 0] mux_3_0; +wire [7 : 0] mux_3_1; +wire [7 : 0] mux_3_2; +wire [7 : 0] mux_3_3; +wire [7 : 0] mux_3_4; +wire [7 : 0] mux_3_5; +wire [7 : 0] mux_3_6; +wire [7 : 0] mux_3_7; +// level 4 signals +wire [7 : 0] mux_4_0; +wire [7 : 0] mux_4_1; +wire [7 : 0] mux_4_2; +wire [7 : 0] mux_4_3; +// level 5 signals +wire [7 : 0] mux_5_0; +wire [7 : 0] mux_5_1; +// level 6 signals +wire [7 : 0] mux_6_0; +// level 7 signals +wire [7 : 0] mux_7_0; +// level 8 signals +wire [7 : 0] mux_8_0; +// level 9 signals +wire [7 : 0] mux_9_0; +// level 10 signals +wire [7 : 0] mux_10_0; +// level 11 signals +wire [7 : 0] mux_11_0; +// level 12 signals +wire [7 : 0] mux_12_0; +// level 13 signals +wire [7 : 0] mux_13_0; +// level 14 signals +wire [7 : 0] mux_14_0; +// level 15 signals +wire [7 : 0] mux_15_0; +// level 16 signals +wire [7 : 0] mux_16_0; +// level 17 signals +wire [7 : 0] mux_17_0; +// level 18 signals +wire [7 : 0] mux_18_0; +// level 19 signals +wire [7 : 0] mux_19_0; +// level 20 signals +wire [7 : 0] mux_20_0; +// level 21 signals +wire [7 : 0] mux_21_0; +// level 22 signals +wire [7 : 0] mux_22_0; +// level 23 signals +wire [7 : 0] mux_23_0; +// level 24 signals +wire [7 : 0] mux_24_0; +// level 25 signals +wire [7 : 0] mux_25_0; +// level 26 signals +wire [7 : 0] mux_26_0; +// level 27 signals +wire [7 : 0] mux_27_0; +// level 28 signals +wire [7 : 0] mux_28_0; +// level 29 signals +wire [7 : 0] mux_29_0; +// level 30 signals +wire [7 : 0] mux_30_0; +// level 31 signals +wire [7 : 0] mux_31_0; +// level 32 signals +wire [7 : 0] mux_32_0; + +assign sel = din64; + +// Generate level 1 logic +assign mux_1_0 = (sel[0] == 0)? din0 : din1; +assign mux_1_1 = (sel[0] == 0)? din2 : din3; +assign mux_1_2 = (sel[0] == 0)? din4 : din5; +assign mux_1_3 = (sel[0] == 0)? din6 : din7; +assign mux_1_4 = (sel[0] == 0)? din8 : din9; +assign mux_1_5 = (sel[0] == 0)? din10 : din11; +assign mux_1_6 = (sel[0] == 0)? din12 : din13; +assign mux_1_7 = (sel[0] == 0)? din14 : din15; +assign mux_1_8 = (sel[0] == 0)? din16 : din17; +assign mux_1_9 = (sel[0] == 0)? din18 : din19; +assign mux_1_10 = (sel[0] == 0)? din20 : din21; +assign mux_1_11 = (sel[0] == 0)? din22 : din23; +assign mux_1_12 = (sel[0] == 0)? din24 : din25; +assign mux_1_13 = (sel[0] == 0)? din26 : din27; +assign mux_1_14 = (sel[0] == 0)? din28 : din29; +assign mux_1_15 = (sel[0] == 0)? din30 : din31; +assign mux_1_16 = (sel[0] == 0)? din32 : din33; +assign mux_1_17 = (sel[0] == 0)? din34 : din35; +assign mux_1_18 = (sel[0] == 0)? din36 : din37; +assign mux_1_19 = (sel[0] == 0)? din38 : din39; +assign mux_1_20 = (sel[0] == 0)? din40 : din41; +assign mux_1_21 = (sel[0] == 0)? din42 : din43; +assign mux_1_22 = (sel[0] == 0)? din44 : din45; +assign mux_1_23 = (sel[0] == 0)? din46 : din47; +assign mux_1_24 = (sel[0] == 0)? din48 : din49; +assign mux_1_25 = (sel[0] == 0)? din50 : din51; +assign mux_1_26 = (sel[0] == 0)? din52 : din53; +assign mux_1_27 = (sel[0] == 0)? din54 : din55; +assign mux_1_28 = (sel[0] == 0)? din56 : din57; +assign mux_1_29 = (sel[0] == 0)? din58 : din59; +assign mux_1_30 = (sel[0] == 0)? din60 : din61; +assign mux_1_31 = (sel[0] == 0)? din62 : din63; + +// Generate level 2 logic +assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1; +assign mux_2_1 = (sel[1] == 0)? mux_1_2 : mux_1_3; +assign mux_2_2 = (sel[1] == 0)? mux_1_4 : mux_1_5; +assign mux_2_3 = (sel[1] == 0)? mux_1_6 : mux_1_7; +assign mux_2_4 = (sel[1] == 0)? mux_1_8 : mux_1_9; +assign mux_2_5 = (sel[1] == 0)? mux_1_10 : mux_1_11; +assign mux_2_6 = (sel[1] == 0)? mux_1_12 : mux_1_13; +assign mux_2_7 = (sel[1] == 0)? mux_1_14 : mux_1_15; +assign mux_2_8 = (sel[1] == 0)? mux_1_16 : mux_1_17; +assign mux_2_9 = (sel[1] == 0)? mux_1_18 : mux_1_19; +assign mux_2_10 = (sel[1] == 0)? mux_1_20 : mux_1_21; +assign mux_2_11 = (sel[1] == 0)? mux_1_22 : mux_1_23; +assign mux_2_12 = (sel[1] == 0)? mux_1_24 : mux_1_25; +assign mux_2_13 = (sel[1] == 0)? mux_1_26 : mux_1_27; +assign mux_2_14 = (sel[1] == 0)? mux_1_28 : mux_1_29; +assign mux_2_15 = (sel[1] == 0)? mux_1_30 : mux_1_31; + +// Generate level 3 logic +assign mux_3_0 = (sel[2] == 0)? mux_2_0 : mux_2_1; +assign mux_3_1 = (sel[2] == 0)? mux_2_2 : mux_2_3; +assign mux_3_2 = (sel[2] == 0)? mux_2_4 : mux_2_5; +assign mux_3_3 = (sel[2] == 0)? mux_2_6 : mux_2_7; +assign mux_3_4 = (sel[2] == 0)? mux_2_8 : mux_2_9; +assign mux_3_5 = (sel[2] == 0)? mux_2_10 : mux_2_11; +assign mux_3_6 = (sel[2] == 0)? mux_2_12 : mux_2_13; +assign mux_3_7 = (sel[2] == 0)? mux_2_14 : mux_2_15; + +// Generate level 4 logic +assign mux_4_0 = (sel[3] == 0)? mux_3_0 : mux_3_1; +assign mux_4_1 = (sel[3] == 0)? mux_3_2 : mux_3_3; +assign mux_4_2 = (sel[3] == 0)? mux_3_4 : mux_3_5; +assign mux_4_3 = (sel[3] == 0)? mux_3_6 : mux_3_7; + +// Generate level 5 logic +assign mux_5_0 = (sel[4] == 0)? mux_4_0 : mux_4_1; +assign mux_5_1 = (sel[4] == 0)? mux_4_2 : mux_4_3; + +// Generate level 6 logic +assign mux_6_0 = (sel[5] == 0)? mux_5_0 : mux_5_1; + +// Generate level 7 logic +assign mux_7_0 = mux_6_0; + +// Generate level 8 logic +assign mux_8_0 = mux_7_0; + +// Generate level 9 logic +assign mux_9_0 = mux_8_0; + +// Generate level 10 logic +assign mux_10_0 = mux_9_0; + +// Generate level 11 logic +assign mux_11_0 = mux_10_0; + +// Generate level 12 logic +assign mux_12_0 = mux_11_0; + +// Generate level 13 logic +assign mux_13_0 = mux_12_0; + +// Generate level 14 logic +assign mux_14_0 = mux_13_0; + +// Generate level 15 logic +assign mux_15_0 = mux_14_0; + +// Generate level 16 logic +assign mux_16_0 = mux_15_0; + +// Generate level 17 logic +assign mux_17_0 = mux_16_0; + +// Generate level 18 logic +assign mux_18_0 = mux_17_0; + +// Generate level 19 logic +assign mux_19_0 = mux_18_0; + +// Generate level 20 logic +assign mux_20_0 = mux_19_0; + +// Generate level 21 logic +assign mux_21_0 = mux_20_0; + +// Generate level 22 logic +assign mux_22_0 = mux_21_0; + +// Generate level 23 logic +assign mux_23_0 = mux_22_0; + +// Generate level 24 logic +assign mux_24_0 = mux_23_0; + +// Generate level 25 logic +assign mux_25_0 = mux_24_0; + +// Generate level 26 logic +assign mux_26_0 = mux_25_0; + +// Generate level 27 logic +assign mux_27_0 = mux_26_0; + +// Generate level 28 logic +assign mux_28_0 = mux_27_0; + +// Generate level 29 logic +assign mux_29_0 = mux_28_0; + +// Generate level 30 logic +assign mux_30_0 = mux_29_0; + +// Generate level 31 logic +assign mux_31_0 = mux_30_0; + +// Generate level 32 logic +assign mux_32_0 = mux_31_0; + +// output logic +assign dout = mux_32_0; + +endmodule +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + +module myproject_urem_32ns_6ns_32_36_seq_1_div_u +#(parameter + in0_WIDTH = 32, + in1_WIDTH = 32, + out_WIDTH = 32 +) +( + input clk, + input reset, + input ce, + input start, + input [in0_WIDTH-1:0] dividend, + input [in1_WIDTH-1:0] divisor, + output wire done, + output wire [out_WIDTH-1:0] quot, + output wire [out_WIDTH-1:0] remd +); + +localparam cal_WIDTH = (in0_WIDTH > in1_WIDTH)? in0_WIDTH : in1_WIDTH; + +//------------------------Local signal------------------- +reg [in0_WIDTH-1:0] dividend0; +reg [in1_WIDTH-1:0] divisor0; +reg [in0_WIDTH-1:0] dividend_tmp; +reg [in0_WIDTH-1:0] remd_tmp; +wire [in0_WIDTH-1:0] dividend_tmp_mux; +wire [in0_WIDTH-1:0] remd_tmp_mux; +wire [in0_WIDTH-1:0] comb_tmp; +wire [cal_WIDTH:0] cal_tmp; + +//------------------------Body--------------------------- +assign quot = dividend_tmp; +assign remd = remd_tmp; + +// dividend0, divisor0 +always @(posedge clk) +begin + if (start) begin + dividend0 <= dividend; + divisor0 <= divisor; + end +end + +// One-Hot Register +// r_stage[0]=1:accept input; r_stage[in0_WIDTH]=1:done +reg [in0_WIDTH:0] r_stage; +assign done = r_stage[in0_WIDTH]; +always @(posedge clk) +begin + if (reset == 1'b1) + r_stage[in0_WIDTH:0] <= {in0_WIDTH{1'b0}}; + else if (ce) + r_stage[in0_WIDTH:0] <= {r_stage[in0_WIDTH-1:0], start}; +end + +// MUXs +assign dividend_tmp_mux = r_stage[0]? dividend0 : dividend_tmp; +assign remd_tmp_mux = r_stage[0]? {in0_WIDTH{1'b0}} : remd_tmp; + +generate +if (in0_WIDTH == 1) assign comb_tmp = dividend_tmp_mux[0]; +else assign comb_tmp = {remd_tmp_mux[in0_WIDTH-2:0], dividend_tmp_mux[in0_WIDTH-1]}; +endgenerate + +assign cal_tmp = {1'b0, comb_tmp} - {1'b0, divisor0}; + +always @(posedge clk) +begin + if (ce) begin + if (in0_WIDTH == 1) dividend_tmp <= ~cal_tmp[cal_WIDTH]; + else dividend_tmp <= {dividend_tmp_mux[in0_WIDTH-2:0], ~cal_tmp[cal_WIDTH]}; + remd_tmp <= cal_tmp[cal_WIDTH]? comb_tmp : cal_tmp[in0_WIDTH-1:0]; + end +end + +endmodule + +module myproject_urem_32ns_6ns_32_36_seq_1_div +#(parameter + in0_WIDTH = 32, + in1_WIDTH = 32, + out_WIDTH = 32 +) +( + input clk, + input reset, + input ce, + input start, + output reg done, + input [in0_WIDTH-1:0] dividend, + input [in1_WIDTH-1:0] divisor, + output reg [out_WIDTH-1:0] quot, + output reg [out_WIDTH-1:0] remd +); +//------------------------Local signal------------------- +reg start0 = 'b0; +wire done0; +reg [in0_WIDTH-1:0] dividend0; +reg [in1_WIDTH-1:0] divisor0; +wire [in0_WIDTH-1:0] dividend_u; +wire [in1_WIDTH-1:0] divisor_u; +wire [out_WIDTH-1:0] quot_u; +wire [out_WIDTH-1:0] remd_u; +//------------------------Instantiation------------------ +myproject_urem_32ns_6ns_32_36_seq_1_div_u #( + .in0_WIDTH ( in0_WIDTH ), + .in1_WIDTH ( in1_WIDTH ), + .out_WIDTH ( out_WIDTH ) +) myproject_urem_32ns_6ns_32_36_seq_1_div_u_0 ( + .clk ( clk ), + .reset ( reset ), + .ce ( ce ), + .start ( start0 ), + .done ( done0 ), + .dividend ( dividend_u ), + .divisor ( divisor_u ), + .quot ( quot_u ), + .remd ( remd_u ) +); +//------------------------Body--------------------------- +assign dividend_u = dividend0; +assign divisor_u = divisor0; + +always @(posedge clk) +begin + if (ce) begin + dividend0 <= dividend; + divisor0 <= divisor; + start0 <= start; + end +end + +always @(posedge clk) +begin + done <= done0; +end + +always @(posedge clk) +begin + if (done0) begin + quot <= quot_u; + remd <= remd_u; + end +end + +endmodule + + +`timescale 1 ns / 1 ps +module myproject_urem_32ns_6ns_32_36_seq_1( + clk, + reset, + ce, + start, + done, + din0, + din1, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input clk; +input reset; +input ce; +input start; +output done; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +output[dout_WIDTH - 1:0] dout; + +wire[dout_WIDTH - 1:0] sig_quot; + + +myproject_urem_32ns_6ns_32_36_seq_1_div #( +.in0_WIDTH( din0_WIDTH ), +.in1_WIDTH( din1_WIDTH ), +.out_WIDTH( dout_WIDTH )) +myproject_urem_32ns_6ns_32_36_seq_1_div_U( + .dividend( din0 ), + .divisor( din1 ), + .remd( dout ), + .quot( sig_quot ), + .clk( clk ), + .ce( ce ), + .reset( reset ), + .start( start ), + .done( done ) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + +module myproject_urem_32ns_6ns_6_36_seq_1_div_u +#(parameter + in0_WIDTH = 32, + in1_WIDTH = 32, + out_WIDTH = 32 +) +( + input clk, + input reset, + input ce, + input start, + input [in0_WIDTH-1:0] dividend, + input [in1_WIDTH-1:0] divisor, + output wire done, + output wire [out_WIDTH-1:0] quot, + output wire [out_WIDTH-1:0] remd +); + +localparam cal_WIDTH = (in0_WIDTH > in1_WIDTH)? in0_WIDTH : in1_WIDTH; + +//------------------------Local signal------------------- +reg [in0_WIDTH-1:0] dividend0; +reg [in1_WIDTH-1:0] divisor0; +reg [in0_WIDTH-1:0] dividend_tmp; +reg [in0_WIDTH-1:0] remd_tmp; +wire [in0_WIDTH-1:0] dividend_tmp_mux; +wire [in0_WIDTH-1:0] remd_tmp_mux; +wire [in0_WIDTH-1:0] comb_tmp; +wire [cal_WIDTH:0] cal_tmp; + +//------------------------Body--------------------------- +assign quot = dividend_tmp; +assign remd = remd_tmp; + +// dividend0, divisor0 +always @(posedge clk) +begin + if (start) begin + dividend0 <= dividend; + divisor0 <= divisor; + end +end + +// One-Hot Register +// r_stage[0]=1:accept input; r_stage[in0_WIDTH]=1:done +reg [in0_WIDTH:0] r_stage; +assign done = r_stage[in0_WIDTH]; +always @(posedge clk) +begin + if (reset == 1'b1) + r_stage[in0_WIDTH:0] <= {in0_WIDTH{1'b0}}; + else if (ce) + r_stage[in0_WIDTH:0] <= {r_stage[in0_WIDTH-1:0], start}; +end + +// MUXs +assign dividend_tmp_mux = r_stage[0]? dividend0 : dividend_tmp; +assign remd_tmp_mux = r_stage[0]? {in0_WIDTH{1'b0}} : remd_tmp; + +generate +if (in0_WIDTH == 1) assign comb_tmp = dividend_tmp_mux[0]; +else assign comb_tmp = {remd_tmp_mux[in0_WIDTH-2:0], dividend_tmp_mux[in0_WIDTH-1]}; +endgenerate + +assign cal_tmp = {1'b0, comb_tmp} - {1'b0, divisor0}; + +always @(posedge clk) +begin + if (ce) begin + if (in0_WIDTH == 1) dividend_tmp <= ~cal_tmp[cal_WIDTH]; + else dividend_tmp <= {dividend_tmp_mux[in0_WIDTH-2:0], ~cal_tmp[cal_WIDTH]}; + remd_tmp <= cal_tmp[cal_WIDTH]? comb_tmp : cal_tmp[in0_WIDTH-1:0]; + end +end + +endmodule + +module myproject_urem_32ns_6ns_6_36_seq_1_div +#(parameter + in0_WIDTH = 32, + in1_WIDTH = 32, + out_WIDTH = 32 +) +( + input clk, + input reset, + input ce, + input start, + output reg done, + input [in0_WIDTH-1:0] dividend, + input [in1_WIDTH-1:0] divisor, + output reg [out_WIDTH-1:0] quot, + output reg [out_WIDTH-1:0] remd +); +//------------------------Local signal------------------- +reg start0 = 'b0; +wire done0; +reg [in0_WIDTH-1:0] dividend0; +reg [in1_WIDTH-1:0] divisor0; +wire [in0_WIDTH-1:0] dividend_u; +wire [in1_WIDTH-1:0] divisor_u; +wire [out_WIDTH-1:0] quot_u; +wire [out_WIDTH-1:0] remd_u; +//------------------------Instantiation------------------ +myproject_urem_32ns_6ns_6_36_seq_1_div_u #( + .in0_WIDTH ( in0_WIDTH ), + .in1_WIDTH ( in1_WIDTH ), + .out_WIDTH ( out_WIDTH ) +) myproject_urem_32ns_6ns_6_36_seq_1_div_u_0 ( + .clk ( clk ), + .reset ( reset ), + .ce ( ce ), + .start ( start0 ), + .done ( done0 ), + .dividend ( dividend_u ), + .divisor ( divisor_u ), + .quot ( quot_u ), + .remd ( remd_u ) +); +//------------------------Body--------------------------- +assign dividend_u = dividend0; +assign divisor_u = divisor0; + +always @(posedge clk) +begin + if (ce) begin + dividend0 <= dividend; + divisor0 <= divisor; + start0 <= start; + end +end + +always @(posedge clk) +begin + done <= done0; +end + +always @(posedge clk) +begin + if (done0) begin + quot <= quot_u; + remd <= remd_u; + end +end + +endmodule + + +`timescale 1 ns / 1 ps +module myproject_urem_32ns_6ns_6_36_seq_1( + clk, + reset, + ce, + start, + done, + din0, + din1, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input clk; +input reset; +input ce; +input start; +output done; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +output[dout_WIDTH - 1:0] dout; + +wire[dout_WIDTH - 1:0] sig_quot; + + +myproject_urem_32ns_6ns_6_36_seq_1_div #( +.in0_WIDTH( din0_WIDTH ), +.in1_WIDTH( din1_WIDTH ), +.out_WIDTH( dout_WIDTH )) +myproject_urem_32ns_6ns_6_36_seq_1_div_U( + .dividend( din0 ), + .divisor( din1 ), + .remd( dout ), + .quot( sig_quot ), + .clk( clk ), + .ce( ce ), + .reset( reset ), + .start( start ), + .done( done ) +); + +endmodule + +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + + + +module myproject ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_idle, + ap_ready, + conv2d_input_V_address0, + conv2d_input_V_ce0, + conv2d_input_V_q0, + layer11_out_V_address0, + layer11_out_V_ce0, + layer11_out_V_we0, + layer11_out_V_d0, + layer11_out_V_address1, + layer11_out_V_ce1, + layer11_out_V_we1, + layer11_out_V_d1, + const_size_in_1, + const_size_in_1_ap_vld, + const_size_out_1, + const_size_out_1_ap_vld +); + +parameter ap_ST_fsm_state1 = 4'd0; +parameter ap_ST_fsm_state2 = 4'd1; +parameter ap_ST_fsm_state3 = 4'd2; +parameter ap_ST_fsm_state4 = 4'd3; +parameter ap_ST_fsm_state5 = 4'd4; +parameter ap_ST_fsm_state6 = 4'd5; +parameter ap_ST_fsm_state7 = 4'd6; +parameter ap_ST_fsm_state8 = 4'd7; +parameter ap_ST_fsm_state9 = 4'd8; +parameter ap_ST_fsm_state10 = 4'd9; +parameter ap_ST_fsm_state11 = 4'd10; +parameter ap_ST_fsm_state12 = 4'd11; +parameter ap_ST_fsm_state13 = 4'd12; +parameter ap_ST_fsm_state14 = 4'd13; +parameter ap_ST_fsm_state15 = 4'd14; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +output [6:0] conv2d_input_V_address0; +output conv2d_input_V_ce0; +input [63:0] conv2d_input_V_q0; +output [3:0] layer11_out_V_address0; +output layer11_out_V_ce0; +output layer11_out_V_we0; +output [7:0] layer11_out_V_d0; +output [3:0] layer11_out_V_address1; +output layer11_out_V_ce1; +output layer11_out_V_we1; +output [7:0] layer11_out_V_d1; +output [15:0] const_size_in_1; +output const_size_in_1_ap_vld; +output [15:0] const_size_out_1; +output const_size_out_1_ap_vld; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[3:0] layer11_out_V_address0; +reg layer11_out_V_ce0; +reg layer11_out_V_we0; +reg[7:0] layer11_out_V_d0; +reg[3:0] layer11_out_V_address1; +reg layer11_out_V_ce1; +reg layer11_out_V_we1; +reg[7:0] layer11_out_V_d1; +reg const_size_in_1_ap_vld; +reg const_size_out_1_ap_vld; + + reg [3:0] ap_CS_fsm; +reg [4:0] layer2_out_0_V_address0; +reg layer2_out_0_V_ce0; +reg layer2_out_0_V_we0; +wire [7:0] layer2_out_0_V_q0; +reg [4:0] layer2_out_1_V_address0; +reg layer2_out_1_V_ce0; +reg layer2_out_1_V_we0; +wire [7:0] layer2_out_1_V_q0; +reg [4:0] layer2_out_2_V_address0; +reg layer2_out_2_V_ce0; +reg layer2_out_2_V_we0; +wire [7:0] layer2_out_2_V_q0; +reg [4:0] layer2_out_3_V_address0; +reg layer2_out_3_V_ce0; +reg layer2_out_3_V_we0; +wire [7:0] layer2_out_3_V_q0; +reg [4:0] layer2_out_4_V_address0; +reg layer2_out_4_V_ce0; +reg layer2_out_4_V_we0; +wire [7:0] layer2_out_4_V_q0; +reg [4:0] layer2_out_5_V_address0; +reg layer2_out_5_V_ce0; +reg layer2_out_5_V_we0; +wire [7:0] layer2_out_5_V_q0; +reg [4:0] layer2_out_6_V_address0; +reg layer2_out_6_V_ce0; +reg layer2_out_6_V_we0; +wire [7:0] layer2_out_6_V_q0; +reg [4:0] layer2_out_7_V_address0; +reg layer2_out_7_V_ce0; +reg layer2_out_7_V_we0; +wire [7:0] layer2_out_7_V_q0; +reg [4:0] layer2_out_8_V_address0; +reg layer2_out_8_V_ce0; +reg layer2_out_8_V_we0; +wire [7:0] layer2_out_8_V_q0; +reg [4:0] layer2_out_9_V_address0; +reg layer2_out_9_V_ce0; +reg layer2_out_9_V_we0; +wire [7:0] layer2_out_9_V_q0; +reg [4:0] layer2_out_10_V_address0; +reg layer2_out_10_V_ce0; +reg layer2_out_10_V_we0; +wire [7:0] layer2_out_10_V_q0; +reg [4:0] layer2_out_11_V_address0; +reg layer2_out_11_V_ce0; +reg layer2_out_11_V_we0; +wire [7:0] layer2_out_11_V_q0; +reg [4:0] layer2_out_12_V_address0; +reg layer2_out_12_V_ce0; +reg layer2_out_12_V_we0; +wire [7:0] layer2_out_12_V_q0; +reg [4:0] layer2_out_13_V_address0; +reg layer2_out_13_V_ce0; +reg layer2_out_13_V_we0; +wire [7:0] layer2_out_13_V_q0; +reg [4:0] layer2_out_14_V_address0; +reg layer2_out_14_V_ce0; +reg layer2_out_14_V_we0; +wire [7:0] layer2_out_14_V_q0; +reg [4:0] layer2_out_15_V_address0; +reg layer2_out_15_V_ce0; +reg layer2_out_15_V_we0; +wire [7:0] layer2_out_15_V_q0; +reg [4:0] layer2_out_16_V_address0; +reg layer2_out_16_V_ce0; +reg layer2_out_16_V_we0; +wire [7:0] layer2_out_16_V_q0; +reg [4:0] layer2_out_17_V_address0; +reg layer2_out_17_V_ce0; +reg layer2_out_17_V_we0; +wire [7:0] layer2_out_17_V_q0; +reg [4:0] layer2_out_18_V_address0; +reg layer2_out_18_V_ce0; +reg layer2_out_18_V_we0; +wire [7:0] layer2_out_18_V_q0; +reg [4:0] layer2_out_19_V_address0; +reg layer2_out_19_V_ce0; +reg layer2_out_19_V_we0; +wire [7:0] layer2_out_19_V_q0; +reg [4:0] layer2_out_20_V_address0; +reg layer2_out_20_V_ce0; +reg layer2_out_20_V_we0; +wire [7:0] layer2_out_20_V_q0; +reg [4:0] layer2_out_21_V_address0; +reg layer2_out_21_V_ce0; +reg layer2_out_21_V_we0; +wire [7:0] layer2_out_21_V_q0; +reg [4:0] layer2_out_22_V_address0; +reg layer2_out_22_V_ce0; +reg layer2_out_22_V_we0; +wire [7:0] layer2_out_22_V_q0; +reg [4:0] layer2_out_23_V_address0; +reg layer2_out_23_V_ce0; +reg layer2_out_23_V_we0; +wire [7:0] layer2_out_23_V_q0; +reg [4:0] layer2_out_24_V_address0; +reg layer2_out_24_V_ce0; +reg layer2_out_24_V_we0; +wire [7:0] layer2_out_24_V_q0; +reg [4:0] layer2_out_25_V_address0; +reg layer2_out_25_V_ce0; +reg layer2_out_25_V_we0; +wire [7:0] layer2_out_25_V_q0; +reg [4:0] layer2_out_26_V_address0; +reg layer2_out_26_V_ce0; +reg layer2_out_26_V_we0; +wire [7:0] layer2_out_26_V_q0; +reg [4:0] layer2_out_27_V_address0; +reg layer2_out_27_V_ce0; +reg layer2_out_27_V_we0; +wire [7:0] layer2_out_27_V_q0; +reg [4:0] layer2_out_28_V_address0; +reg layer2_out_28_V_ce0; +reg layer2_out_28_V_we0; +wire [7:0] layer2_out_28_V_q0; +reg [4:0] layer2_out_29_V_address0; +reg layer2_out_29_V_ce0; +reg layer2_out_29_V_we0; +wire [7:0] layer2_out_29_V_q0; +reg [4:0] layer2_out_30_V_address0; +reg layer2_out_30_V_ce0; +reg layer2_out_30_V_we0; +wire [7:0] layer2_out_30_V_q0; +reg [4:0] layer2_out_31_V_address0; +reg layer2_out_31_V_ce0; +reg layer2_out_31_V_we0; +wire [7:0] layer2_out_31_V_q0; +reg [4:0] layer2_out_32_V_address0; +reg layer2_out_32_V_ce0; +reg layer2_out_32_V_we0; +wire [7:0] layer2_out_32_V_q0; +reg [4:0] layer2_out_33_V_address0; +reg layer2_out_33_V_ce0; +reg layer2_out_33_V_we0; +wire [7:0] layer2_out_33_V_q0; +reg [4:0] layer2_out_34_V_address0; +reg layer2_out_34_V_ce0; +reg layer2_out_34_V_we0; +wire [7:0] layer2_out_34_V_q0; +reg [4:0] layer2_out_35_V_address0; +reg layer2_out_35_V_ce0; +reg layer2_out_35_V_we0; +wire [7:0] layer2_out_35_V_q0; +reg [4:0] layer2_out_36_V_address0; +reg layer2_out_36_V_ce0; +reg layer2_out_36_V_we0; +wire [7:0] layer2_out_36_V_q0; +reg [4:0] layer2_out_37_V_address0; +reg layer2_out_37_V_ce0; +reg layer2_out_37_V_we0; +wire [7:0] layer2_out_37_V_q0; +reg [4:0] layer2_out_38_V_address0; +reg layer2_out_38_V_ce0; +reg layer2_out_38_V_we0; +wire [7:0] layer2_out_38_V_q0; +reg [4:0] layer2_out_39_V_address0; +reg layer2_out_39_V_ce0; +reg layer2_out_39_V_we0; +wire [7:0] layer2_out_39_V_q0; +reg [4:0] layer2_out_40_V_address0; +reg layer2_out_40_V_ce0; +reg layer2_out_40_V_we0; +wire [7:0] layer2_out_40_V_q0; +reg [4:0] layer2_out_41_V_address0; +reg layer2_out_41_V_ce0; +reg layer2_out_41_V_we0; +wire [7:0] layer2_out_41_V_q0; +reg [4:0] layer2_out_42_V_address0; +reg layer2_out_42_V_ce0; +reg layer2_out_42_V_we0; +wire [7:0] layer2_out_42_V_q0; +reg [4:0] layer2_out_43_V_address0; +reg layer2_out_43_V_ce0; +reg layer2_out_43_V_we0; +wire [7:0] layer2_out_43_V_q0; +reg [4:0] layer2_out_44_V_address0; +reg layer2_out_44_V_ce0; +reg layer2_out_44_V_we0; +wire [7:0] layer2_out_44_V_q0; +reg [4:0] layer2_out_45_V_address0; +reg layer2_out_45_V_ce0; +reg layer2_out_45_V_we0; +wire [7:0] layer2_out_45_V_q0; +reg [4:0] layer2_out_46_V_address0; +reg layer2_out_46_V_ce0; +reg layer2_out_46_V_we0; +wire [7:0] layer2_out_46_V_q0; +reg [4:0] layer2_out_47_V_address0; +reg layer2_out_47_V_ce0; +reg layer2_out_47_V_we0; +wire [7:0] layer2_out_47_V_q0; +reg [4:0] layer2_out_48_V_address0; +reg layer2_out_48_V_ce0; +reg layer2_out_48_V_we0; +wire [7:0] layer2_out_48_V_q0; +reg [4:0] layer2_out_49_V_address0; +reg layer2_out_49_V_ce0; +reg layer2_out_49_V_we0; +wire [7:0] layer2_out_49_V_q0; +reg [4:0] layer2_out_50_V_address0; +reg layer2_out_50_V_ce0; +reg layer2_out_50_V_we0; +wire [7:0] layer2_out_50_V_q0; +reg [4:0] layer2_out_51_V_address0; +reg layer2_out_51_V_ce0; +reg layer2_out_51_V_we0; +wire [7:0] layer2_out_51_V_q0; +reg [4:0] layer2_out_52_V_address0; +reg layer2_out_52_V_ce0; +reg layer2_out_52_V_we0; +wire [7:0] layer2_out_52_V_q0; +reg [4:0] layer2_out_53_V_address0; +reg layer2_out_53_V_ce0; +reg layer2_out_53_V_we0; +wire [7:0] layer2_out_53_V_q0; +reg [4:0] layer2_out_54_V_address0; +reg layer2_out_54_V_ce0; +reg layer2_out_54_V_we0; +wire [7:0] layer2_out_54_V_q0; +reg [4:0] layer2_out_55_V_address0; +reg layer2_out_55_V_ce0; +reg layer2_out_55_V_we0; +wire [7:0] layer2_out_55_V_q0; +reg [4:0] layer2_out_56_V_address0; +reg layer2_out_56_V_ce0; +reg layer2_out_56_V_we0; +wire [7:0] layer2_out_56_V_q0; +reg [4:0] layer2_out_57_V_address0; +reg layer2_out_57_V_ce0; +reg layer2_out_57_V_we0; +wire [7:0] layer2_out_57_V_q0; +reg [4:0] layer2_out_58_V_address0; +reg layer2_out_58_V_ce0; +reg layer2_out_58_V_we0; +wire [7:0] layer2_out_58_V_q0; +reg [4:0] layer2_out_59_V_address0; +reg layer2_out_59_V_ce0; +reg layer2_out_59_V_we0; +wire [7:0] layer2_out_59_V_q0; +reg [4:0] layer2_out_60_V_address0; +reg layer2_out_60_V_ce0; +reg layer2_out_60_V_we0; +wire [7:0] layer2_out_60_V_q0; +reg [4:0] layer2_out_61_V_address0; +reg layer2_out_61_V_ce0; +reg layer2_out_61_V_we0; +wire [7:0] layer2_out_61_V_q0; +reg [4:0] layer2_out_62_V_address0; +reg layer2_out_62_V_ce0; +reg layer2_out_62_V_we0; +wire [7:0] layer2_out_62_V_q0; +reg [4:0] layer2_out_63_V_address0; +reg layer2_out_63_V_ce0; +reg layer2_out_63_V_we0; +wire [7:0] layer2_out_63_V_q0; +reg [4:0] layer2_out_64_V_address0; +reg layer2_out_64_V_ce0; +reg layer2_out_64_V_we0; +wire [7:0] layer2_out_64_V_q0; +reg [4:0] layer2_out_65_V_address0; +reg layer2_out_65_V_ce0; +reg layer2_out_65_V_we0; +wire [7:0] layer2_out_65_V_q0; +reg [4:0] layer2_out_66_V_address0; +reg layer2_out_66_V_ce0; +reg layer2_out_66_V_we0; +wire [7:0] layer2_out_66_V_q0; +reg [4:0] layer2_out_67_V_address0; +reg layer2_out_67_V_ce0; +reg layer2_out_67_V_we0; +wire [7:0] layer2_out_67_V_q0; +reg [4:0] layer2_out_68_V_address0; +reg layer2_out_68_V_ce0; +reg layer2_out_68_V_we0; +wire [7:0] layer2_out_68_V_q0; +reg [4:0] layer2_out_69_V_address0; +reg layer2_out_69_V_ce0; +reg layer2_out_69_V_we0; +wire [7:0] layer2_out_69_V_q0; +reg [4:0] layer2_out_70_V_address0; +reg layer2_out_70_V_ce0; +reg layer2_out_70_V_we0; +wire [7:0] layer2_out_70_V_q0; +reg [4:0] layer2_out_71_V_address0; +reg layer2_out_71_V_ce0; +reg layer2_out_71_V_we0; +wire [7:0] layer2_out_71_V_q0; +reg [4:0] layer2_out_72_V_address0; +reg layer2_out_72_V_ce0; +reg layer2_out_72_V_we0; +wire [7:0] layer2_out_72_V_q0; +reg [4:0] layer2_out_73_V_address0; +reg layer2_out_73_V_ce0; +reg layer2_out_73_V_we0; +wire [7:0] layer2_out_73_V_q0; +reg [4:0] layer2_out_74_V_address0; +reg layer2_out_74_V_ce0; +reg layer2_out_74_V_we0; +wire [7:0] layer2_out_74_V_q0; +reg [4:0] layer2_out_75_V_address0; +reg layer2_out_75_V_ce0; +reg layer2_out_75_V_we0; +wire [7:0] layer2_out_75_V_q0; +reg [4:0] layer2_out_76_V_address0; +reg layer2_out_76_V_ce0; +reg layer2_out_76_V_we0; +wire [7:0] layer2_out_76_V_q0; +reg [4:0] layer2_out_77_V_address0; +reg layer2_out_77_V_ce0; +reg layer2_out_77_V_we0; +wire [7:0] layer2_out_77_V_q0; +reg [4:0] layer2_out_78_V_address0; +reg layer2_out_78_V_ce0; +reg layer2_out_78_V_we0; +wire [7:0] layer2_out_78_V_q0; +reg [4:0] layer2_out_79_V_address0; +reg layer2_out_79_V_ce0; +reg layer2_out_79_V_we0; +wire [7:0] layer2_out_79_V_q0; +reg [4:0] layer2_out_80_V_address0; +reg layer2_out_80_V_ce0; +reg layer2_out_80_V_we0; +wire [7:0] layer2_out_80_V_q0; +reg [4:0] layer2_out_81_V_address0; +reg layer2_out_81_V_ce0; +reg layer2_out_81_V_we0; +wire [7:0] layer2_out_81_V_q0; +reg [4:0] layer2_out_82_V_address0; +reg layer2_out_82_V_ce0; +reg layer2_out_82_V_we0; +wire [7:0] layer2_out_82_V_q0; +reg [4:0] layer2_out_83_V_address0; +reg layer2_out_83_V_ce0; +reg layer2_out_83_V_we0; +wire [7:0] layer2_out_83_V_q0; +reg [4:0] layer2_out_84_V_address0; +reg layer2_out_84_V_ce0; +reg layer2_out_84_V_we0; +wire [7:0] layer2_out_84_V_q0; +reg [4:0] layer2_out_85_V_address0; +reg layer2_out_85_V_ce0; +reg layer2_out_85_V_we0; +wire [7:0] layer2_out_85_V_q0; +reg [4:0] layer2_out_86_V_address0; +reg layer2_out_86_V_ce0; +reg layer2_out_86_V_we0; +wire [7:0] layer2_out_86_V_q0; +reg [4:0] layer2_out_87_V_address0; +reg layer2_out_87_V_ce0; +reg layer2_out_87_V_we0; +wire [7:0] layer2_out_87_V_q0; +reg [4:0] layer2_out_88_V_address0; +reg layer2_out_88_V_ce0; +reg layer2_out_88_V_we0; +wire [7:0] layer2_out_88_V_q0; +reg [4:0] layer2_out_89_V_address0; +reg layer2_out_89_V_ce0; +reg layer2_out_89_V_we0; +wire [7:0] layer2_out_89_V_q0; +reg [4:0] layer2_out_90_V_address0; +reg layer2_out_90_V_ce0; +reg layer2_out_90_V_we0; +wire [7:0] layer2_out_90_V_q0; +reg [4:0] layer2_out_91_V_address0; +reg layer2_out_91_V_ce0; +reg layer2_out_91_V_we0; +wire [7:0] layer2_out_91_V_q0; +reg [4:0] layer2_out_92_V_address0; +reg layer2_out_92_V_ce0; +reg layer2_out_92_V_we0; +wire [7:0] layer2_out_92_V_q0; +reg [4:0] layer2_out_93_V_address0; +reg layer2_out_93_V_ce0; +reg layer2_out_93_V_we0; +wire [7:0] layer2_out_93_V_q0; +reg [4:0] layer2_out_94_V_address0; +reg layer2_out_94_V_ce0; +reg layer2_out_94_V_we0; +wire [7:0] layer2_out_94_V_q0; +reg [4:0] layer2_out_95_V_address0; +reg layer2_out_95_V_ce0; +reg layer2_out_95_V_we0; +wire [7:0] layer2_out_95_V_q0; +reg [4:0] layer2_out_96_V_address0; +reg layer2_out_96_V_ce0; +reg layer2_out_96_V_we0; +wire [7:0] layer2_out_96_V_q0; +reg [4:0] layer2_out_97_V_address0; +reg layer2_out_97_V_ce0; +reg layer2_out_97_V_we0; +wire [7:0] layer2_out_97_V_q0; +reg [4:0] layer2_out_98_V_address0; +reg layer2_out_98_V_ce0; +reg layer2_out_98_V_we0; +wire [7:0] layer2_out_98_V_q0; +reg [4:0] layer2_out_99_V_address0; +reg layer2_out_99_V_ce0; +reg layer2_out_99_V_we0; +wire [7:0] layer2_out_99_V_q0; +reg [4:0] layer2_out_100_V_address0; +reg layer2_out_100_V_ce0; +reg layer2_out_100_V_we0; +wire [7:0] layer2_out_100_V_q0; +reg [4:0] layer2_out_101_V_address0; +reg layer2_out_101_V_ce0; +reg layer2_out_101_V_we0; +wire [7:0] layer2_out_101_V_q0; +reg [4:0] layer2_out_102_V_address0; +reg layer2_out_102_V_ce0; +reg layer2_out_102_V_we0; +wire [7:0] layer2_out_102_V_q0; +reg [4:0] layer2_out_103_V_address0; +reg layer2_out_103_V_ce0; +reg layer2_out_103_V_we0; +wire [7:0] layer2_out_103_V_q0; +reg [4:0] layer2_out_104_V_address0; +reg layer2_out_104_V_ce0; +reg layer2_out_104_V_we0; +wire [7:0] layer2_out_104_V_q0; +reg [4:0] layer2_out_105_V_address0; +reg layer2_out_105_V_ce0; +reg layer2_out_105_V_we0; +wire [7:0] layer2_out_105_V_q0; +reg [4:0] layer2_out_106_V_address0; +reg layer2_out_106_V_ce0; +reg layer2_out_106_V_we0; +wire [7:0] layer2_out_106_V_q0; +reg [4:0] layer2_out_107_V_address0; +reg layer2_out_107_V_ce0; +reg layer2_out_107_V_we0; +wire [7:0] layer2_out_107_V_q0; +reg [4:0] layer2_out_108_V_address0; +reg layer2_out_108_V_ce0; +reg layer2_out_108_V_we0; +wire [7:0] layer2_out_108_V_q0; +reg [4:0] layer2_out_109_V_address0; +reg layer2_out_109_V_ce0; +reg layer2_out_109_V_we0; +wire [7:0] layer2_out_109_V_q0; +reg [4:0] layer2_out_110_V_address0; +reg layer2_out_110_V_ce0; +reg layer2_out_110_V_we0; +wire [7:0] layer2_out_110_V_q0; +reg [4:0] layer2_out_111_V_address0; +reg layer2_out_111_V_ce0; +reg layer2_out_111_V_we0; +wire [7:0] layer2_out_111_V_q0; +reg [4:0] layer2_out_112_V_address0; +reg layer2_out_112_V_ce0; +reg layer2_out_112_V_we0; +wire [7:0] layer2_out_112_V_q0; +reg [4:0] layer2_out_113_V_address0; +reg layer2_out_113_V_ce0; +reg layer2_out_113_V_we0; +wire [7:0] layer2_out_113_V_q0; +reg [4:0] layer2_out_114_V_address0; +reg layer2_out_114_V_ce0; +reg layer2_out_114_V_we0; +wire [7:0] layer2_out_114_V_q0; +reg [4:0] layer2_out_115_V_address0; +reg layer2_out_115_V_ce0; +reg layer2_out_115_V_we0; +wire [7:0] layer2_out_115_V_q0; +reg [4:0] layer2_out_116_V_address0; +reg layer2_out_116_V_ce0; +reg layer2_out_116_V_we0; +wire [7:0] layer2_out_116_V_q0; +reg [4:0] layer2_out_117_V_address0; +reg layer2_out_117_V_ce0; +reg layer2_out_117_V_we0; +wire [7:0] layer2_out_117_V_q0; +reg [4:0] layer2_out_118_V_address0; +reg layer2_out_118_V_ce0; +reg layer2_out_118_V_we0; +wire [7:0] layer2_out_118_V_q0; +reg [4:0] layer2_out_119_V_address0; +reg layer2_out_119_V_ce0; +reg layer2_out_119_V_we0; +wire [7:0] layer2_out_119_V_q0; +reg [4:0] layer2_out_120_V_address0; +reg layer2_out_120_V_ce0; +reg layer2_out_120_V_we0; +wire [7:0] layer2_out_120_V_q0; +reg [4:0] layer2_out_121_V_address0; +reg layer2_out_121_V_ce0; +reg layer2_out_121_V_we0; +wire [7:0] layer2_out_121_V_q0; +reg [4:0] layer2_out_122_V_address0; +reg layer2_out_122_V_ce0; +reg layer2_out_122_V_we0; +wire [7:0] layer2_out_122_V_q0; +reg [4:0] layer2_out_123_V_address0; +reg layer2_out_123_V_ce0; +reg layer2_out_123_V_we0; +wire [7:0] layer2_out_123_V_q0; +reg [4:0] layer2_out_124_V_address0; +reg layer2_out_124_V_ce0; +reg layer2_out_124_V_we0; +wire [7:0] layer2_out_124_V_q0; +reg [4:0] layer2_out_125_V_address0; +reg layer2_out_125_V_ce0; +reg layer2_out_125_V_we0; +wire [7:0] layer2_out_125_V_q0; +reg [4:0] layer2_out_126_V_address0; +reg layer2_out_126_V_ce0; +reg layer2_out_126_V_we0; +wire [7:0] layer2_out_126_V_q0; +reg [4:0] layer2_out_127_V_address0; +reg layer2_out_127_V_ce0; +reg layer2_out_127_V_we0; +wire [7:0] layer2_out_127_V_q0; +reg [2:0] layer4_out_0_V_address0; +reg layer4_out_0_V_ce0; +reg layer4_out_0_V_we0; +wire [7:0] layer4_out_0_V_q0; +reg [2:0] layer4_out_1_V_address0; +reg layer4_out_1_V_ce0; +reg layer4_out_1_V_we0; +wire [7:0] layer4_out_1_V_q0; +reg [2:0] layer4_out_2_V_address0; +reg layer4_out_2_V_ce0; +reg layer4_out_2_V_we0; +wire [7:0] layer4_out_2_V_q0; +reg [2:0] layer4_out_3_V_address0; +reg layer4_out_3_V_ce0; +reg layer4_out_3_V_we0; +wire [7:0] layer4_out_3_V_q0; +reg [2:0] layer4_out_4_V_address0; +reg layer4_out_4_V_ce0; +reg layer4_out_4_V_we0; +wire [7:0] layer4_out_4_V_q0; +reg [2:0] layer4_out_5_V_address0; +reg layer4_out_5_V_ce0; +reg layer4_out_5_V_we0; +wire [7:0] layer4_out_5_V_q0; +reg [2:0] layer4_out_6_V_address0; +reg layer4_out_6_V_ce0; +reg layer4_out_6_V_we0; +wire [7:0] layer4_out_6_V_q0; +reg [2:0] layer4_out_7_V_address0; +reg layer4_out_7_V_ce0; +reg layer4_out_7_V_we0; +wire [7:0] layer4_out_7_V_q0; +reg [2:0] layer4_out_8_V_address0; +reg layer4_out_8_V_ce0; +reg layer4_out_8_V_we0; +wire [7:0] layer4_out_8_V_q0; +reg [2:0] layer4_out_9_V_address0; +reg layer4_out_9_V_ce0; +reg layer4_out_9_V_we0; +wire [7:0] layer4_out_9_V_q0; +reg [2:0] layer4_out_10_V_address0; +reg layer4_out_10_V_ce0; +reg layer4_out_10_V_we0; +wire [7:0] layer4_out_10_V_q0; +reg [2:0] layer4_out_11_V_address0; +reg layer4_out_11_V_ce0; +reg layer4_out_11_V_we0; +wire [7:0] layer4_out_11_V_q0; +reg [2:0] layer4_out_12_V_address0; +reg layer4_out_12_V_ce0; +reg layer4_out_12_V_we0; +wire [7:0] layer4_out_12_V_q0; +reg [2:0] layer4_out_13_V_address0; +reg layer4_out_13_V_ce0; +reg layer4_out_13_V_we0; +wire [7:0] layer4_out_13_V_q0; +reg [2:0] layer4_out_14_V_address0; +reg layer4_out_14_V_ce0; +reg layer4_out_14_V_we0; +wire [7:0] layer4_out_14_V_q0; +reg [2:0] layer4_out_15_V_address0; +reg layer4_out_15_V_ce0; +reg layer4_out_15_V_we0; +wire [7:0] layer4_out_15_V_q0; +reg [2:0] layer4_out_16_V_address0; +reg layer4_out_16_V_ce0; +reg layer4_out_16_V_we0; +wire [7:0] layer4_out_16_V_q0; +reg [2:0] layer4_out_17_V_address0; +reg layer4_out_17_V_ce0; +reg layer4_out_17_V_we0; +wire [7:0] layer4_out_17_V_q0; +reg [2:0] layer4_out_18_V_address0; +reg layer4_out_18_V_ce0; +reg layer4_out_18_V_we0; +wire [7:0] layer4_out_18_V_q0; +reg [2:0] layer4_out_19_V_address0; +reg layer4_out_19_V_ce0; +reg layer4_out_19_V_we0; +wire [7:0] layer4_out_19_V_q0; +reg [2:0] layer4_out_20_V_address0; +reg layer4_out_20_V_ce0; +reg layer4_out_20_V_we0; +wire [7:0] layer4_out_20_V_q0; +reg [2:0] layer4_out_21_V_address0; +reg layer4_out_21_V_ce0; +reg layer4_out_21_V_we0; +wire [7:0] layer4_out_21_V_q0; +reg [2:0] layer4_out_22_V_address0; +reg layer4_out_22_V_ce0; +reg layer4_out_22_V_we0; +wire [7:0] layer4_out_22_V_q0; +reg [2:0] layer4_out_23_V_address0; +reg layer4_out_23_V_ce0; +reg layer4_out_23_V_we0; +wire [7:0] layer4_out_23_V_q0; +reg [2:0] layer4_out_24_V_address0; +reg layer4_out_24_V_ce0; +reg layer4_out_24_V_we0; +wire [7:0] layer4_out_24_V_q0; +reg [2:0] layer4_out_25_V_address0; +reg layer4_out_25_V_ce0; +reg layer4_out_25_V_we0; +wire [7:0] layer4_out_25_V_q0; +reg [2:0] layer4_out_26_V_address0; +reg layer4_out_26_V_ce0; +reg layer4_out_26_V_we0; +wire [7:0] layer4_out_26_V_q0; +reg [2:0] layer4_out_27_V_address0; +reg layer4_out_27_V_ce0; +reg layer4_out_27_V_we0; +wire [7:0] layer4_out_27_V_q0; +reg [2:0] layer4_out_28_V_address0; +reg layer4_out_28_V_ce0; +reg layer4_out_28_V_we0; +wire [7:0] layer4_out_28_V_q0; +reg [2:0] layer4_out_29_V_address0; +reg layer4_out_29_V_ce0; +reg layer4_out_29_V_we0; +wire [7:0] layer4_out_29_V_q0; +reg [2:0] layer4_out_30_V_address0; +reg layer4_out_30_V_ce0; +reg layer4_out_30_V_we0; +wire [7:0] layer4_out_30_V_q0; +reg [2:0] layer4_out_31_V_address0; +reg layer4_out_31_V_ce0; +reg layer4_out_31_V_we0; +wire [7:0] layer4_out_31_V_q0; +reg [2:0] layer4_out_32_V_address0; +reg layer4_out_32_V_ce0; +reg layer4_out_32_V_we0; +wire [7:0] layer4_out_32_V_q0; +reg [2:0] layer4_out_33_V_address0; +reg layer4_out_33_V_ce0; +reg layer4_out_33_V_we0; +wire [7:0] layer4_out_33_V_q0; +reg [2:0] layer4_out_34_V_address0; +reg layer4_out_34_V_ce0; +reg layer4_out_34_V_we0; +wire [7:0] layer4_out_34_V_q0; +reg [2:0] layer4_out_35_V_address0; +reg layer4_out_35_V_ce0; +reg layer4_out_35_V_we0; +wire [7:0] layer4_out_35_V_q0; +reg [2:0] layer4_out_36_V_address0; +reg layer4_out_36_V_ce0; +reg layer4_out_36_V_we0; +wire [7:0] layer4_out_36_V_q0; +reg [2:0] layer4_out_37_V_address0; +reg layer4_out_37_V_ce0; +reg layer4_out_37_V_we0; +wire [7:0] layer4_out_37_V_q0; +reg [2:0] layer4_out_38_V_address0; +reg layer4_out_38_V_ce0; +reg layer4_out_38_V_we0; +wire [7:0] layer4_out_38_V_q0; +reg [2:0] layer4_out_39_V_address0; +reg layer4_out_39_V_ce0; +reg layer4_out_39_V_we0; +wire [7:0] layer4_out_39_V_q0; +reg [2:0] layer4_out_40_V_address0; +reg layer4_out_40_V_ce0; +reg layer4_out_40_V_we0; +wire [7:0] layer4_out_40_V_q0; +reg [2:0] layer4_out_41_V_address0; +reg layer4_out_41_V_ce0; +reg layer4_out_41_V_we0; +wire [7:0] layer4_out_41_V_q0; +reg [2:0] layer4_out_42_V_address0; +reg layer4_out_42_V_ce0; +reg layer4_out_42_V_we0; +wire [7:0] layer4_out_42_V_q0; +reg [2:0] layer4_out_43_V_address0; +reg layer4_out_43_V_ce0; +reg layer4_out_43_V_we0; +wire [7:0] layer4_out_43_V_q0; +reg [2:0] layer4_out_44_V_address0; +reg layer4_out_44_V_ce0; +reg layer4_out_44_V_we0; +wire [7:0] layer4_out_44_V_q0; +reg [2:0] layer4_out_45_V_address0; +reg layer4_out_45_V_ce0; +reg layer4_out_45_V_we0; +wire [7:0] layer4_out_45_V_q0; +reg [2:0] layer4_out_46_V_address0; +reg layer4_out_46_V_ce0; +reg layer4_out_46_V_we0; +wire [7:0] layer4_out_46_V_q0; +reg [2:0] layer4_out_47_V_address0; +reg layer4_out_47_V_ce0; +reg layer4_out_47_V_we0; +wire [7:0] layer4_out_47_V_q0; +reg [2:0] layer4_out_48_V_address0; +reg layer4_out_48_V_ce0; +reg layer4_out_48_V_we0; +wire [7:0] layer4_out_48_V_q0; +reg [2:0] layer4_out_49_V_address0; +reg layer4_out_49_V_ce0; +reg layer4_out_49_V_we0; +wire [7:0] layer4_out_49_V_q0; +reg [2:0] layer4_out_50_V_address0; +reg layer4_out_50_V_ce0; +reg layer4_out_50_V_we0; +wire [7:0] layer4_out_50_V_q0; +reg [2:0] layer4_out_51_V_address0; +reg layer4_out_51_V_ce0; +reg layer4_out_51_V_we0; +wire [7:0] layer4_out_51_V_q0; +reg [2:0] layer4_out_52_V_address0; +reg layer4_out_52_V_ce0; +reg layer4_out_52_V_we0; +wire [7:0] layer4_out_52_V_q0; +reg [2:0] layer4_out_53_V_address0; +reg layer4_out_53_V_ce0; +reg layer4_out_53_V_we0; +wire [7:0] layer4_out_53_V_q0; +reg [2:0] layer4_out_54_V_address0; +reg layer4_out_54_V_ce0; +reg layer4_out_54_V_we0; +wire [7:0] layer4_out_54_V_q0; +reg [2:0] layer4_out_55_V_address0; +reg layer4_out_55_V_ce0; +reg layer4_out_55_V_we0; +wire [7:0] layer4_out_55_V_q0; +reg [2:0] layer4_out_56_V_address0; +reg layer4_out_56_V_ce0; +reg layer4_out_56_V_we0; +wire [7:0] layer4_out_56_V_q0; +reg [2:0] layer4_out_57_V_address0; +reg layer4_out_57_V_ce0; +reg layer4_out_57_V_we0; +wire [7:0] layer4_out_57_V_q0; +reg [2:0] layer4_out_58_V_address0; +reg layer4_out_58_V_ce0; +reg layer4_out_58_V_we0; +wire [7:0] layer4_out_58_V_q0; +reg [2:0] layer4_out_59_V_address0; +reg layer4_out_59_V_ce0; +reg layer4_out_59_V_we0; +wire [7:0] layer4_out_59_V_q0; +reg [2:0] layer4_out_60_V_address0; +reg layer4_out_60_V_ce0; +reg layer4_out_60_V_we0; +wire [7:0] layer4_out_60_V_q0; +reg [2:0] layer4_out_61_V_address0; +reg layer4_out_61_V_ce0; +reg layer4_out_61_V_we0; +wire [7:0] layer4_out_61_V_q0; +reg [2:0] layer4_out_62_V_address0; +reg layer4_out_62_V_ce0; +reg layer4_out_62_V_we0; +wire [7:0] layer4_out_62_V_q0; +reg [2:0] layer4_out_63_V_address0; +reg layer4_out_63_V_ce0; +reg layer4_out_63_V_we0; +wire [7:0] layer4_out_63_V_q0; +reg [2:0] layer4_out_64_V_address0; +reg layer4_out_64_V_ce0; +reg layer4_out_64_V_we0; +wire [7:0] layer4_out_64_V_q0; +reg [2:0] layer4_out_65_V_address0; +reg layer4_out_65_V_ce0; +reg layer4_out_65_V_we0; +wire [7:0] layer4_out_65_V_q0; +reg [2:0] layer4_out_66_V_address0; +reg layer4_out_66_V_ce0; +reg layer4_out_66_V_we0; +wire [7:0] layer4_out_66_V_q0; +reg [2:0] layer4_out_67_V_address0; +reg layer4_out_67_V_ce0; +reg layer4_out_67_V_we0; +wire [7:0] layer4_out_67_V_q0; +reg [2:0] layer4_out_68_V_address0; +reg layer4_out_68_V_ce0; +reg layer4_out_68_V_we0; +wire [7:0] layer4_out_68_V_q0; +reg [2:0] layer4_out_69_V_address0; +reg layer4_out_69_V_ce0; +reg layer4_out_69_V_we0; +wire [7:0] layer4_out_69_V_q0; +reg [2:0] layer4_out_70_V_address0; +reg layer4_out_70_V_ce0; +reg layer4_out_70_V_we0; +wire [7:0] layer4_out_70_V_q0; +reg [2:0] layer4_out_71_V_address0; +reg layer4_out_71_V_ce0; +reg layer4_out_71_V_we0; +wire [7:0] layer4_out_71_V_q0; +reg [2:0] layer4_out_72_V_address0; +reg layer4_out_72_V_ce0; +reg layer4_out_72_V_we0; +wire [7:0] layer4_out_72_V_q0; +reg [2:0] layer4_out_73_V_address0; +reg layer4_out_73_V_ce0; +reg layer4_out_73_V_we0; +wire [7:0] layer4_out_73_V_q0; +reg [2:0] layer4_out_74_V_address0; +reg layer4_out_74_V_ce0; +reg layer4_out_74_V_we0; +wire [7:0] layer4_out_74_V_q0; +reg [2:0] layer4_out_75_V_address0; +reg layer4_out_75_V_ce0; +reg layer4_out_75_V_we0; +wire [7:0] layer4_out_75_V_q0; +reg [2:0] layer4_out_76_V_address0; +reg layer4_out_76_V_ce0; +reg layer4_out_76_V_we0; +wire [7:0] layer4_out_76_V_q0; +reg [2:0] layer4_out_77_V_address0; +reg layer4_out_77_V_ce0; +reg layer4_out_77_V_we0; +wire [7:0] layer4_out_77_V_q0; +reg [2:0] layer4_out_78_V_address0; +reg layer4_out_78_V_ce0; +reg layer4_out_78_V_we0; +wire [7:0] layer4_out_78_V_q0; +reg [2:0] layer4_out_79_V_address0; +reg layer4_out_79_V_ce0; +reg layer4_out_79_V_we0; +wire [7:0] layer4_out_79_V_q0; +reg [2:0] layer4_out_80_V_address0; +reg layer4_out_80_V_ce0; +reg layer4_out_80_V_we0; +wire [7:0] layer4_out_80_V_q0; +reg [2:0] layer4_out_81_V_address0; +reg layer4_out_81_V_ce0; +reg layer4_out_81_V_we0; +wire [7:0] layer4_out_81_V_q0; +reg [2:0] layer4_out_82_V_address0; +reg layer4_out_82_V_ce0; +reg layer4_out_82_V_we0; +wire [7:0] layer4_out_82_V_q0; +reg [2:0] layer4_out_83_V_address0; +reg layer4_out_83_V_ce0; +reg layer4_out_83_V_we0; +wire [7:0] layer4_out_83_V_q0; +reg [2:0] layer4_out_84_V_address0; +reg layer4_out_84_V_ce0; +reg layer4_out_84_V_we0; +wire [7:0] layer4_out_84_V_q0; +reg [2:0] layer4_out_85_V_address0; +reg layer4_out_85_V_ce0; +reg layer4_out_85_V_we0; +wire [7:0] layer4_out_85_V_q0; +reg [2:0] layer4_out_86_V_address0; +reg layer4_out_86_V_ce0; +reg layer4_out_86_V_we0; +wire [7:0] layer4_out_86_V_q0; +reg [2:0] layer4_out_87_V_address0; +reg layer4_out_87_V_ce0; +reg layer4_out_87_V_we0; +wire [7:0] layer4_out_87_V_q0; +reg [2:0] layer4_out_88_V_address0; +reg layer4_out_88_V_ce0; +reg layer4_out_88_V_we0; +wire [7:0] layer4_out_88_V_q0; +reg [2:0] layer4_out_89_V_address0; +reg layer4_out_89_V_ce0; +reg layer4_out_89_V_we0; +wire [7:0] layer4_out_89_V_q0; +reg [2:0] layer4_out_90_V_address0; +reg layer4_out_90_V_ce0; +reg layer4_out_90_V_we0; +wire [7:0] layer4_out_90_V_q0; +reg [2:0] layer4_out_91_V_address0; +reg layer4_out_91_V_ce0; +reg layer4_out_91_V_we0; +wire [7:0] layer4_out_91_V_q0; +reg [2:0] layer4_out_92_V_address0; +reg layer4_out_92_V_ce0; +reg layer4_out_92_V_we0; +wire [7:0] layer4_out_92_V_q0; +reg [2:0] layer4_out_93_V_address0; +reg layer4_out_93_V_ce0; +reg layer4_out_93_V_we0; +wire [7:0] layer4_out_93_V_q0; +reg [2:0] layer4_out_94_V_address0; +reg layer4_out_94_V_ce0; +reg layer4_out_94_V_we0; +wire [7:0] layer4_out_94_V_q0; +reg [2:0] layer4_out_95_V_address0; +reg layer4_out_95_V_ce0; +reg layer4_out_95_V_we0; +wire [7:0] layer4_out_95_V_q0; +reg [2:0] layer4_out_96_V_address0; +reg layer4_out_96_V_ce0; +reg layer4_out_96_V_we0; +wire [7:0] layer4_out_96_V_q0; +reg [2:0] layer4_out_97_V_address0; +reg layer4_out_97_V_ce0; +reg layer4_out_97_V_we0; +wire [7:0] layer4_out_97_V_q0; +reg [2:0] layer4_out_98_V_address0; +reg layer4_out_98_V_ce0; +reg layer4_out_98_V_we0; +wire [7:0] layer4_out_98_V_q0; +reg [2:0] layer4_out_99_V_address0; +reg layer4_out_99_V_ce0; +reg layer4_out_99_V_we0; +wire [7:0] layer4_out_99_V_q0; +reg [2:0] layer4_out_100_V_address0; +reg layer4_out_100_V_ce0; +reg layer4_out_100_V_we0; +wire [7:0] layer4_out_100_V_q0; +reg [2:0] layer4_out_101_V_address0; +reg layer4_out_101_V_ce0; +reg layer4_out_101_V_we0; +wire [7:0] layer4_out_101_V_q0; +reg [2:0] layer4_out_102_V_address0; +reg layer4_out_102_V_ce0; +reg layer4_out_102_V_we0; +wire [7:0] layer4_out_102_V_q0; +reg [2:0] layer4_out_103_V_address0; +reg layer4_out_103_V_ce0; +reg layer4_out_103_V_we0; +wire [7:0] layer4_out_103_V_q0; +reg [2:0] layer4_out_104_V_address0; +reg layer4_out_104_V_ce0; +reg layer4_out_104_V_we0; +wire [7:0] layer4_out_104_V_q0; +reg [2:0] layer4_out_105_V_address0; +reg layer4_out_105_V_ce0; +reg layer4_out_105_V_we0; +wire [7:0] layer4_out_105_V_q0; +reg [2:0] layer4_out_106_V_address0; +reg layer4_out_106_V_ce0; +reg layer4_out_106_V_we0; +wire [7:0] layer4_out_106_V_q0; +reg [2:0] layer4_out_107_V_address0; +reg layer4_out_107_V_ce0; +reg layer4_out_107_V_we0; +wire [7:0] layer4_out_107_V_q0; +reg [2:0] layer4_out_108_V_address0; +reg layer4_out_108_V_ce0; +reg layer4_out_108_V_we0; +wire [7:0] layer4_out_108_V_q0; +reg [2:0] layer4_out_109_V_address0; +reg layer4_out_109_V_ce0; +reg layer4_out_109_V_we0; +wire [7:0] layer4_out_109_V_q0; +reg [2:0] layer4_out_110_V_address0; +reg layer4_out_110_V_ce0; +reg layer4_out_110_V_we0; +wire [7:0] layer4_out_110_V_q0; +reg [2:0] layer4_out_111_V_address0; +reg layer4_out_111_V_ce0; +reg layer4_out_111_V_we0; +wire [7:0] layer4_out_111_V_q0; +reg [2:0] layer4_out_112_V_address0; +reg layer4_out_112_V_ce0; +reg layer4_out_112_V_we0; +wire [7:0] layer4_out_112_V_q0; +reg [2:0] layer4_out_113_V_address0; +reg layer4_out_113_V_ce0; +reg layer4_out_113_V_we0; +wire [7:0] layer4_out_113_V_q0; +reg [2:0] layer4_out_114_V_address0; +reg layer4_out_114_V_ce0; +reg layer4_out_114_V_we0; +wire [7:0] layer4_out_114_V_q0; +reg [2:0] layer4_out_115_V_address0; +reg layer4_out_115_V_ce0; +reg layer4_out_115_V_we0; +wire [7:0] layer4_out_115_V_q0; +reg [2:0] layer4_out_116_V_address0; +reg layer4_out_116_V_ce0; +reg layer4_out_116_V_we0; +wire [7:0] layer4_out_116_V_q0; +reg [2:0] layer4_out_117_V_address0; +reg layer4_out_117_V_ce0; +reg layer4_out_117_V_we0; +wire [7:0] layer4_out_117_V_q0; +reg [2:0] layer4_out_118_V_address0; +reg layer4_out_118_V_ce0; +reg layer4_out_118_V_we0; +wire [7:0] layer4_out_118_V_q0; +reg [2:0] layer4_out_119_V_address0; +reg layer4_out_119_V_ce0; +reg layer4_out_119_V_we0; +wire [7:0] layer4_out_119_V_q0; +reg [2:0] layer4_out_120_V_address0; +reg layer4_out_120_V_ce0; +reg layer4_out_120_V_we0; +wire [7:0] layer4_out_120_V_q0; +reg [2:0] layer4_out_121_V_address0; +reg layer4_out_121_V_ce0; +reg layer4_out_121_V_we0; +wire [7:0] layer4_out_121_V_q0; +reg [2:0] layer4_out_122_V_address0; +reg layer4_out_122_V_ce0; +reg layer4_out_122_V_we0; +wire [7:0] layer4_out_122_V_q0; +reg [2:0] layer4_out_123_V_address0; +reg layer4_out_123_V_ce0; +reg layer4_out_123_V_we0; +wire [7:0] layer4_out_123_V_q0; +reg [2:0] layer4_out_124_V_address0; +reg layer4_out_124_V_ce0; +reg layer4_out_124_V_we0; +wire [7:0] layer4_out_124_V_q0; +reg [2:0] layer4_out_125_V_address0; +reg layer4_out_125_V_ce0; +reg layer4_out_125_V_we0; +wire [7:0] layer4_out_125_V_q0; +reg [2:0] layer4_out_126_V_address0; +reg layer4_out_126_V_ce0; +reg layer4_out_126_V_we0; +wire [7:0] layer4_out_126_V_q0; +reg [2:0] layer4_out_127_V_address0; +reg layer4_out_127_V_ce0; +reg layer4_out_127_V_we0; +wire [7:0] layer4_out_127_V_q0; +reg [4:0] layer5_out_0_V_address0; +reg layer5_out_0_V_ce0; +reg layer5_out_0_V_we0; +wire [7:0] layer5_out_0_V_q0; +reg [4:0] layer5_out_1_V_address0; +reg layer5_out_1_V_ce0; +reg layer5_out_1_V_we0; +wire [7:0] layer5_out_1_V_q0; +reg [4:0] layer5_out_2_V_address0; +reg layer5_out_2_V_ce0; +reg layer5_out_2_V_we0; +wire [7:0] layer5_out_2_V_q0; +reg [4:0] layer5_out_3_V_address0; +reg layer5_out_3_V_ce0; +reg layer5_out_3_V_we0; +wire [7:0] layer5_out_3_V_q0; +reg [4:0] layer5_out_4_V_address0; +reg layer5_out_4_V_ce0; +reg layer5_out_4_V_we0; +wire [7:0] layer5_out_4_V_q0; +reg [4:0] layer5_out_5_V_address0; +reg layer5_out_5_V_ce0; +reg layer5_out_5_V_we0; +wire [7:0] layer5_out_5_V_q0; +reg [4:0] layer5_out_6_V_address0; +reg layer5_out_6_V_ce0; +reg layer5_out_6_V_we0; +wire [7:0] layer5_out_6_V_q0; +reg [4:0] layer5_out_7_V_address0; +reg layer5_out_7_V_ce0; +reg layer5_out_7_V_we0; +wire [7:0] layer5_out_7_V_q0; +reg [4:0] layer5_out_8_V_address0; +reg layer5_out_8_V_ce0; +reg layer5_out_8_V_we0; +wire [7:0] layer5_out_8_V_q0; +reg [4:0] layer5_out_9_V_address0; +reg layer5_out_9_V_ce0; +reg layer5_out_9_V_we0; +wire [7:0] layer5_out_9_V_q0; +reg [4:0] layer5_out_10_V_address0; +reg layer5_out_10_V_ce0; +reg layer5_out_10_V_we0; +wire [7:0] layer5_out_10_V_q0; +reg [4:0] layer5_out_11_V_address0; +reg layer5_out_11_V_ce0; +reg layer5_out_11_V_we0; +wire [7:0] layer5_out_11_V_q0; +reg [4:0] layer5_out_12_V_address0; +reg layer5_out_12_V_ce0; +reg layer5_out_12_V_we0; +wire [7:0] layer5_out_12_V_q0; +reg [4:0] layer5_out_13_V_address0; +reg layer5_out_13_V_ce0; +reg layer5_out_13_V_we0; +wire [7:0] layer5_out_13_V_q0; +reg [4:0] layer5_out_14_V_address0; +reg layer5_out_14_V_ce0; +reg layer5_out_14_V_we0; +wire [7:0] layer5_out_14_V_q0; +reg [4:0] layer5_out_15_V_address0; +reg layer5_out_15_V_ce0; +reg layer5_out_15_V_we0; +wire [7:0] layer5_out_15_V_q0; +reg [4:0] layer5_out_16_V_address0; +reg layer5_out_16_V_ce0; +reg layer5_out_16_V_we0; +wire [7:0] layer5_out_16_V_q0; +reg [4:0] layer5_out_17_V_address0; +reg layer5_out_17_V_ce0; +reg layer5_out_17_V_we0; +wire [7:0] layer5_out_17_V_q0; +reg [4:0] layer5_out_18_V_address0; +reg layer5_out_18_V_ce0; +reg layer5_out_18_V_we0; +wire [7:0] layer5_out_18_V_q0; +reg [4:0] layer5_out_19_V_address0; +reg layer5_out_19_V_ce0; +reg layer5_out_19_V_we0; +wire [7:0] layer5_out_19_V_q0; +reg [4:0] layer5_out_20_V_address0; +reg layer5_out_20_V_ce0; +reg layer5_out_20_V_we0; +wire [7:0] layer5_out_20_V_q0; +reg [4:0] layer5_out_21_V_address0; +reg layer5_out_21_V_ce0; +reg layer5_out_21_V_we0; +wire [7:0] layer5_out_21_V_q0; +reg [4:0] layer5_out_22_V_address0; +reg layer5_out_22_V_ce0; +reg layer5_out_22_V_we0; +wire [7:0] layer5_out_22_V_q0; +reg [4:0] layer5_out_23_V_address0; +reg layer5_out_23_V_ce0; +reg layer5_out_23_V_we0; +wire [7:0] layer5_out_23_V_q0; +reg [4:0] layer5_out_24_V_address0; +reg layer5_out_24_V_ce0; +reg layer5_out_24_V_we0; +wire [7:0] layer5_out_24_V_q0; +reg [4:0] layer5_out_25_V_address0; +reg layer5_out_25_V_ce0; +reg layer5_out_25_V_we0; +wire [7:0] layer5_out_25_V_q0; +reg [4:0] layer5_out_26_V_address0; +reg layer5_out_26_V_ce0; +reg layer5_out_26_V_we0; +wire [7:0] layer5_out_26_V_q0; +reg [4:0] layer5_out_27_V_address0; +reg layer5_out_27_V_ce0; +reg layer5_out_27_V_we0; +wire [7:0] layer5_out_27_V_q0; +reg [4:0] layer5_out_28_V_address0; +reg layer5_out_28_V_ce0; +reg layer5_out_28_V_we0; +wire [7:0] layer5_out_28_V_q0; +reg [4:0] layer5_out_29_V_address0; +reg layer5_out_29_V_ce0; +reg layer5_out_29_V_we0; +wire [7:0] layer5_out_29_V_q0; +reg [4:0] layer5_out_30_V_address0; +reg layer5_out_30_V_ce0; +reg layer5_out_30_V_we0; +wire [7:0] layer5_out_30_V_q0; +reg [4:0] layer5_out_31_V_address0; +reg layer5_out_31_V_ce0; +reg layer5_out_31_V_we0; +wire [7:0] layer5_out_31_V_q0; +reg [4:0] layer5_out_32_V_address0; +reg layer5_out_32_V_ce0; +reg layer5_out_32_V_we0; +wire [7:0] layer5_out_32_V_q0; +reg [4:0] layer5_out_33_V_address0; +reg layer5_out_33_V_ce0; +reg layer5_out_33_V_we0; +wire [7:0] layer5_out_33_V_q0; +reg [4:0] layer5_out_34_V_address0; +reg layer5_out_34_V_ce0; +reg layer5_out_34_V_we0; +wire [7:0] layer5_out_34_V_q0; +reg [4:0] layer5_out_35_V_address0; +reg layer5_out_35_V_ce0; +reg layer5_out_35_V_we0; +wire [7:0] layer5_out_35_V_q0; +reg [4:0] layer5_out_36_V_address0; +reg layer5_out_36_V_ce0; +reg layer5_out_36_V_we0; +wire [7:0] layer5_out_36_V_q0; +reg [4:0] layer5_out_37_V_address0; +reg layer5_out_37_V_ce0; +reg layer5_out_37_V_we0; +wire [7:0] layer5_out_37_V_q0; +reg [4:0] layer5_out_38_V_address0; +reg layer5_out_38_V_ce0; +reg layer5_out_38_V_we0; +wire [7:0] layer5_out_38_V_q0; +reg [4:0] layer5_out_39_V_address0; +reg layer5_out_39_V_ce0; +reg layer5_out_39_V_we0; +wire [7:0] layer5_out_39_V_q0; +reg [4:0] layer5_out_40_V_address0; +reg layer5_out_40_V_ce0; +reg layer5_out_40_V_we0; +wire [7:0] layer5_out_40_V_q0; +reg [4:0] layer5_out_41_V_address0; +reg layer5_out_41_V_ce0; +reg layer5_out_41_V_we0; +wire [7:0] layer5_out_41_V_q0; +reg [4:0] layer5_out_42_V_address0; +reg layer5_out_42_V_ce0; +reg layer5_out_42_V_we0; +wire [7:0] layer5_out_42_V_q0; +reg [4:0] layer5_out_43_V_address0; +reg layer5_out_43_V_ce0; +reg layer5_out_43_V_we0; +wire [7:0] layer5_out_43_V_q0; +reg [4:0] layer5_out_44_V_address0; +reg layer5_out_44_V_ce0; +reg layer5_out_44_V_we0; +wire [7:0] layer5_out_44_V_q0; +reg [4:0] layer5_out_45_V_address0; +reg layer5_out_45_V_ce0; +reg layer5_out_45_V_we0; +wire [7:0] layer5_out_45_V_q0; +reg [4:0] layer5_out_46_V_address0; +reg layer5_out_46_V_ce0; +reg layer5_out_46_V_we0; +wire [7:0] layer5_out_46_V_q0; +reg [4:0] layer5_out_47_V_address0; +reg layer5_out_47_V_ce0; +reg layer5_out_47_V_we0; +wire [7:0] layer5_out_47_V_q0; +reg [4:0] layer5_out_48_V_address0; +reg layer5_out_48_V_ce0; +reg layer5_out_48_V_we0; +wire [7:0] layer5_out_48_V_q0; +reg [4:0] layer5_out_49_V_address0; +reg layer5_out_49_V_ce0; +reg layer5_out_49_V_we0; +wire [7:0] layer5_out_49_V_q0; +reg [4:0] layer5_out_50_V_address0; +reg layer5_out_50_V_ce0; +reg layer5_out_50_V_we0; +wire [7:0] layer5_out_50_V_q0; +reg [4:0] layer5_out_51_V_address0; +reg layer5_out_51_V_ce0; +reg layer5_out_51_V_we0; +wire [7:0] layer5_out_51_V_q0; +reg [4:0] layer5_out_52_V_address0; +reg layer5_out_52_V_ce0; +reg layer5_out_52_V_we0; +wire [7:0] layer5_out_52_V_q0; +reg [4:0] layer5_out_53_V_address0; +reg layer5_out_53_V_ce0; +reg layer5_out_53_V_we0; +wire [7:0] layer5_out_53_V_q0; +reg [4:0] layer5_out_54_V_address0; +reg layer5_out_54_V_ce0; +reg layer5_out_54_V_we0; +wire [7:0] layer5_out_54_V_q0; +reg [4:0] layer5_out_55_V_address0; +reg layer5_out_55_V_ce0; +reg layer5_out_55_V_we0; +wire [7:0] layer5_out_55_V_q0; +reg [4:0] layer5_out_56_V_address0; +reg layer5_out_56_V_ce0; +reg layer5_out_56_V_we0; +wire [7:0] layer5_out_56_V_q0; +reg [4:0] layer5_out_57_V_address0; +reg layer5_out_57_V_ce0; +reg layer5_out_57_V_we0; +wire [7:0] layer5_out_57_V_q0; +reg [4:0] layer5_out_58_V_address0; +reg layer5_out_58_V_ce0; +reg layer5_out_58_V_we0; +wire [7:0] layer5_out_58_V_q0; +reg [4:0] layer5_out_59_V_address0; +reg layer5_out_59_V_ce0; +reg layer5_out_59_V_we0; +wire [7:0] layer5_out_59_V_q0; +reg [4:0] layer5_out_60_V_address0; +reg layer5_out_60_V_ce0; +reg layer5_out_60_V_we0; +wire [7:0] layer5_out_60_V_q0; +reg [4:0] layer5_out_61_V_address0; +reg layer5_out_61_V_ce0; +reg layer5_out_61_V_we0; +wire [7:0] layer5_out_61_V_q0; +reg [4:0] layer5_out_62_V_address0; +reg layer5_out_62_V_ce0; +reg layer5_out_62_V_we0; +wire [7:0] layer5_out_62_V_q0; +reg [4:0] layer5_out_63_V_address0; +reg layer5_out_63_V_ce0; +reg layer5_out_63_V_we0; +wire [7:0] layer5_out_63_V_q0; +reg [4:0] layer5_out_64_V_address0; +reg layer5_out_64_V_ce0; +reg layer5_out_64_V_we0; +wire [7:0] layer5_out_64_V_q0; +reg [4:0] layer5_out_65_V_address0; +reg layer5_out_65_V_ce0; +reg layer5_out_65_V_we0; +wire [7:0] layer5_out_65_V_q0; +reg [4:0] layer5_out_66_V_address0; +reg layer5_out_66_V_ce0; +reg layer5_out_66_V_we0; +wire [7:0] layer5_out_66_V_q0; +reg [4:0] layer5_out_67_V_address0; +reg layer5_out_67_V_ce0; +reg layer5_out_67_V_we0; +wire [7:0] layer5_out_67_V_q0; +reg [4:0] layer5_out_68_V_address0; +reg layer5_out_68_V_ce0; +reg layer5_out_68_V_we0; +wire [7:0] layer5_out_68_V_q0; +reg [4:0] layer5_out_69_V_address0; +reg layer5_out_69_V_ce0; +reg layer5_out_69_V_we0; +wire [7:0] layer5_out_69_V_q0; +reg [4:0] layer5_out_70_V_address0; +reg layer5_out_70_V_ce0; +reg layer5_out_70_V_we0; +wire [7:0] layer5_out_70_V_q0; +reg [4:0] layer5_out_71_V_address0; +reg layer5_out_71_V_ce0; +reg layer5_out_71_V_we0; +wire [7:0] layer5_out_71_V_q0; +reg [4:0] layer5_out_72_V_address0; +reg layer5_out_72_V_ce0; +reg layer5_out_72_V_we0; +wire [7:0] layer5_out_72_V_q0; +reg [4:0] layer5_out_73_V_address0; +reg layer5_out_73_V_ce0; +reg layer5_out_73_V_we0; +wire [7:0] layer5_out_73_V_q0; +reg [4:0] layer5_out_74_V_address0; +reg layer5_out_74_V_ce0; +reg layer5_out_74_V_we0; +wire [7:0] layer5_out_74_V_q0; +reg [4:0] layer5_out_75_V_address0; +reg layer5_out_75_V_ce0; +reg layer5_out_75_V_we0; +wire [7:0] layer5_out_75_V_q0; +reg [4:0] layer5_out_76_V_address0; +reg layer5_out_76_V_ce0; +reg layer5_out_76_V_we0; +wire [7:0] layer5_out_76_V_q0; +reg [4:0] layer5_out_77_V_address0; +reg layer5_out_77_V_ce0; +reg layer5_out_77_V_we0; +wire [7:0] layer5_out_77_V_q0; +reg [4:0] layer5_out_78_V_address0; +reg layer5_out_78_V_ce0; +reg layer5_out_78_V_we0; +wire [7:0] layer5_out_78_V_q0; +reg [4:0] layer5_out_79_V_address0; +reg layer5_out_79_V_ce0; +reg layer5_out_79_V_we0; +wire [7:0] layer5_out_79_V_q0; +reg [4:0] layer5_out_80_V_address0; +reg layer5_out_80_V_ce0; +reg layer5_out_80_V_we0; +wire [7:0] layer5_out_80_V_q0; +reg [4:0] layer5_out_81_V_address0; +reg layer5_out_81_V_ce0; +reg layer5_out_81_V_we0; +wire [7:0] layer5_out_81_V_q0; +reg [4:0] layer5_out_82_V_address0; +reg layer5_out_82_V_ce0; +reg layer5_out_82_V_we0; +wire [7:0] layer5_out_82_V_q0; +reg [4:0] layer5_out_83_V_address0; +reg layer5_out_83_V_ce0; +reg layer5_out_83_V_we0; +wire [7:0] layer5_out_83_V_q0; +reg [4:0] layer5_out_84_V_address0; +reg layer5_out_84_V_ce0; +reg layer5_out_84_V_we0; +wire [7:0] layer5_out_84_V_q0; +reg [4:0] layer5_out_85_V_address0; +reg layer5_out_85_V_ce0; +reg layer5_out_85_V_we0; +wire [7:0] layer5_out_85_V_q0; +reg [4:0] layer5_out_86_V_address0; +reg layer5_out_86_V_ce0; +reg layer5_out_86_V_we0; +wire [7:0] layer5_out_86_V_q0; +reg [4:0] layer5_out_87_V_address0; +reg layer5_out_87_V_ce0; +reg layer5_out_87_V_we0; +wire [7:0] layer5_out_87_V_q0; +reg [4:0] layer5_out_88_V_address0; +reg layer5_out_88_V_ce0; +reg layer5_out_88_V_we0; +wire [7:0] layer5_out_88_V_q0; +reg [4:0] layer5_out_89_V_address0; +reg layer5_out_89_V_ce0; +reg layer5_out_89_V_we0; +wire [7:0] layer5_out_89_V_q0; +reg [4:0] layer5_out_90_V_address0; +reg layer5_out_90_V_ce0; +reg layer5_out_90_V_we0; +wire [7:0] layer5_out_90_V_q0; +reg [4:0] layer5_out_91_V_address0; +reg layer5_out_91_V_ce0; +reg layer5_out_91_V_we0; +wire [7:0] layer5_out_91_V_q0; +reg [4:0] layer5_out_92_V_address0; +reg layer5_out_92_V_ce0; +reg layer5_out_92_V_we0; +wire [7:0] layer5_out_92_V_q0; +reg [4:0] layer5_out_93_V_address0; +reg layer5_out_93_V_ce0; +reg layer5_out_93_V_we0; +wire [7:0] layer5_out_93_V_q0; +reg [4:0] layer5_out_94_V_address0; +reg layer5_out_94_V_ce0; +reg layer5_out_94_V_we0; +wire [7:0] layer5_out_94_V_q0; +reg [4:0] layer5_out_95_V_address0; +reg layer5_out_95_V_ce0; +reg layer5_out_95_V_we0; +wire [7:0] layer5_out_95_V_q0; +reg [4:0] layer5_out_96_V_address0; +reg layer5_out_96_V_ce0; +reg layer5_out_96_V_we0; +wire [7:0] layer5_out_96_V_q0; +reg [4:0] layer5_out_97_V_address0; +reg layer5_out_97_V_ce0; +reg layer5_out_97_V_we0; +wire [7:0] layer5_out_97_V_q0; +reg [4:0] layer5_out_98_V_address0; +reg layer5_out_98_V_ce0; +reg layer5_out_98_V_we0; +wire [7:0] layer5_out_98_V_q0; +reg [4:0] layer5_out_99_V_address0; +reg layer5_out_99_V_ce0; +reg layer5_out_99_V_we0; +wire [7:0] layer5_out_99_V_q0; +reg [4:0] layer5_out_100_V_address0; +reg layer5_out_100_V_ce0; +reg layer5_out_100_V_we0; +wire [7:0] layer5_out_100_V_q0; +reg [4:0] layer5_out_101_V_address0; +reg layer5_out_101_V_ce0; +reg layer5_out_101_V_we0; +wire [7:0] layer5_out_101_V_q0; +reg [4:0] layer5_out_102_V_address0; +reg layer5_out_102_V_ce0; +reg layer5_out_102_V_we0; +wire [7:0] layer5_out_102_V_q0; +reg [4:0] layer5_out_103_V_address0; +reg layer5_out_103_V_ce0; +reg layer5_out_103_V_we0; +wire [7:0] layer5_out_103_V_q0; +reg [4:0] layer5_out_104_V_address0; +reg layer5_out_104_V_ce0; +reg layer5_out_104_V_we0; +wire [7:0] layer5_out_104_V_q0; +reg [4:0] layer5_out_105_V_address0; +reg layer5_out_105_V_ce0; +reg layer5_out_105_V_we0; +wire [7:0] layer5_out_105_V_q0; +reg [4:0] layer5_out_106_V_address0; +reg layer5_out_106_V_ce0; +reg layer5_out_106_V_we0; +wire [7:0] layer5_out_106_V_q0; +reg [4:0] layer5_out_107_V_address0; +reg layer5_out_107_V_ce0; +reg layer5_out_107_V_we0; +wire [7:0] layer5_out_107_V_q0; +reg [4:0] layer5_out_108_V_address0; +reg layer5_out_108_V_ce0; +reg layer5_out_108_V_we0; +wire [7:0] layer5_out_108_V_q0; +reg [4:0] layer5_out_109_V_address0; +reg layer5_out_109_V_ce0; +reg layer5_out_109_V_we0; +wire [7:0] layer5_out_109_V_q0; +reg [4:0] layer5_out_110_V_address0; +reg layer5_out_110_V_ce0; +reg layer5_out_110_V_we0; +wire [7:0] layer5_out_110_V_q0; +reg [4:0] layer5_out_111_V_address0; +reg layer5_out_111_V_ce0; +reg layer5_out_111_V_we0; +wire [7:0] layer5_out_111_V_q0; +reg [4:0] layer5_out_112_V_address0; +reg layer5_out_112_V_ce0; +reg layer5_out_112_V_we0; +wire [7:0] layer5_out_112_V_q0; +reg [4:0] layer5_out_113_V_address0; +reg layer5_out_113_V_ce0; +reg layer5_out_113_V_we0; +wire [7:0] layer5_out_113_V_q0; +reg [4:0] layer5_out_114_V_address0; +reg layer5_out_114_V_ce0; +reg layer5_out_114_V_we0; +wire [7:0] layer5_out_114_V_q0; +reg [4:0] layer5_out_115_V_address0; +reg layer5_out_115_V_ce0; +reg layer5_out_115_V_we0; +wire [7:0] layer5_out_115_V_q0; +reg [4:0] layer5_out_116_V_address0; +reg layer5_out_116_V_ce0; +reg layer5_out_116_V_we0; +wire [7:0] layer5_out_116_V_q0; +reg [4:0] layer5_out_117_V_address0; +reg layer5_out_117_V_ce0; +reg layer5_out_117_V_we0; +wire [7:0] layer5_out_117_V_q0; +reg [4:0] layer5_out_118_V_address0; +reg layer5_out_118_V_ce0; +reg layer5_out_118_V_we0; +wire [7:0] layer5_out_118_V_q0; +reg [4:0] layer5_out_119_V_address0; +reg layer5_out_119_V_ce0; +reg layer5_out_119_V_we0; +wire [7:0] layer5_out_119_V_q0; +reg [4:0] layer5_out_120_V_address0; +reg layer5_out_120_V_ce0; +reg layer5_out_120_V_we0; +wire [7:0] layer5_out_120_V_q0; +reg [4:0] layer5_out_121_V_address0; +reg layer5_out_121_V_ce0; +reg layer5_out_121_V_we0; +wire [7:0] layer5_out_121_V_q0; +reg [4:0] layer5_out_122_V_address0; +reg layer5_out_122_V_ce0; +reg layer5_out_122_V_we0; +wire [7:0] layer5_out_122_V_q0; +reg [4:0] layer5_out_123_V_address0; +reg layer5_out_123_V_ce0; +reg layer5_out_123_V_we0; +wire [7:0] layer5_out_123_V_q0; +reg [4:0] layer5_out_124_V_address0; +reg layer5_out_124_V_ce0; +reg layer5_out_124_V_we0; +wire [7:0] layer5_out_124_V_q0; +reg [4:0] layer5_out_125_V_address0; +reg layer5_out_125_V_ce0; +reg layer5_out_125_V_we0; +wire [7:0] layer5_out_125_V_q0; +reg [4:0] layer5_out_126_V_address0; +reg layer5_out_126_V_ce0; +reg layer5_out_126_V_we0; +wire [7:0] layer5_out_126_V_q0; +reg [4:0] layer5_out_127_V_address0; +reg layer5_out_127_V_ce0; +reg layer5_out_127_V_we0; +wire [7:0] layer5_out_127_V_q0; +reg [2:0] layer7_out_0_V_address0; +reg layer7_out_0_V_ce0; +reg layer7_out_0_V_we0; +wire [7:0] layer7_out_0_V_q0; +reg [2:0] layer7_out_1_V_address0; +reg layer7_out_1_V_ce0; +reg layer7_out_1_V_we0; +wire [7:0] layer7_out_1_V_q0; +reg [2:0] layer7_out_2_V_address0; +reg layer7_out_2_V_ce0; +reg layer7_out_2_V_we0; +wire [7:0] layer7_out_2_V_q0; +reg [2:0] layer7_out_3_V_address0; +reg layer7_out_3_V_ce0; +reg layer7_out_3_V_we0; +wire [7:0] layer7_out_3_V_q0; +reg [2:0] layer7_out_4_V_address0; +reg layer7_out_4_V_ce0; +reg layer7_out_4_V_we0; +wire [7:0] layer7_out_4_V_q0; +reg [2:0] layer7_out_5_V_address0; +reg layer7_out_5_V_ce0; +reg layer7_out_5_V_we0; +wire [7:0] layer7_out_5_V_q0; +reg [2:0] layer7_out_6_V_address0; +reg layer7_out_6_V_ce0; +reg layer7_out_6_V_we0; +wire [7:0] layer7_out_6_V_q0; +reg [2:0] layer7_out_7_V_address0; +reg layer7_out_7_V_ce0; +reg layer7_out_7_V_we0; +wire [7:0] layer7_out_7_V_q0; +reg [2:0] layer7_out_8_V_address0; +reg layer7_out_8_V_ce0; +reg layer7_out_8_V_we0; +wire [7:0] layer7_out_8_V_q0; +reg [2:0] layer7_out_9_V_address0; +reg layer7_out_9_V_ce0; +reg layer7_out_9_V_we0; +wire [7:0] layer7_out_9_V_q0; +reg [2:0] layer7_out_10_V_address0; +reg layer7_out_10_V_ce0; +reg layer7_out_10_V_we0; +wire [7:0] layer7_out_10_V_q0; +reg [2:0] layer7_out_11_V_address0; +reg layer7_out_11_V_ce0; +reg layer7_out_11_V_we0; +wire [7:0] layer7_out_11_V_q0; +reg [2:0] layer7_out_12_V_address0; +reg layer7_out_12_V_ce0; +reg layer7_out_12_V_we0; +wire [7:0] layer7_out_12_V_q0; +reg [2:0] layer7_out_13_V_address0; +reg layer7_out_13_V_ce0; +reg layer7_out_13_V_we0; +wire [7:0] layer7_out_13_V_q0; +reg [2:0] layer7_out_14_V_address0; +reg layer7_out_14_V_ce0; +reg layer7_out_14_V_we0; +wire [7:0] layer7_out_14_V_q0; +reg [2:0] layer7_out_15_V_address0; +reg layer7_out_15_V_ce0; +reg layer7_out_15_V_we0; +wire [7:0] layer7_out_15_V_q0; +reg [2:0] layer7_out_16_V_address0; +reg layer7_out_16_V_ce0; +reg layer7_out_16_V_we0; +wire [7:0] layer7_out_16_V_q0; +reg [2:0] layer7_out_17_V_address0; +reg layer7_out_17_V_ce0; +reg layer7_out_17_V_we0; +wire [7:0] layer7_out_17_V_q0; +reg [2:0] layer7_out_18_V_address0; +reg layer7_out_18_V_ce0; +reg layer7_out_18_V_we0; +wire [7:0] layer7_out_18_V_q0; +reg [2:0] layer7_out_19_V_address0; +reg layer7_out_19_V_ce0; +reg layer7_out_19_V_we0; +wire [7:0] layer7_out_19_V_q0; +reg [2:0] layer7_out_20_V_address0; +reg layer7_out_20_V_ce0; +reg layer7_out_20_V_we0; +wire [7:0] layer7_out_20_V_q0; +reg [2:0] layer7_out_21_V_address0; +reg layer7_out_21_V_ce0; +reg layer7_out_21_V_we0; +wire [7:0] layer7_out_21_V_q0; +reg [2:0] layer7_out_22_V_address0; +reg layer7_out_22_V_ce0; +reg layer7_out_22_V_we0; +wire [7:0] layer7_out_22_V_q0; +reg [2:0] layer7_out_23_V_address0; +reg layer7_out_23_V_ce0; +reg layer7_out_23_V_we0; +wire [7:0] layer7_out_23_V_q0; +reg [2:0] layer7_out_24_V_address0; +reg layer7_out_24_V_ce0; +reg layer7_out_24_V_we0; +wire [7:0] layer7_out_24_V_q0; +reg [2:0] layer7_out_25_V_address0; +reg layer7_out_25_V_ce0; +reg layer7_out_25_V_we0; +wire [7:0] layer7_out_25_V_q0; +reg [2:0] layer7_out_26_V_address0; +reg layer7_out_26_V_ce0; +reg layer7_out_26_V_we0; +wire [7:0] layer7_out_26_V_q0; +reg [2:0] layer7_out_27_V_address0; +reg layer7_out_27_V_ce0; +reg layer7_out_27_V_we0; +wire [7:0] layer7_out_27_V_q0; +reg [2:0] layer7_out_28_V_address0; +reg layer7_out_28_V_ce0; +reg layer7_out_28_V_we0; +wire [7:0] layer7_out_28_V_q0; +reg [2:0] layer7_out_29_V_address0; +reg layer7_out_29_V_ce0; +reg layer7_out_29_V_we0; +wire [7:0] layer7_out_29_V_q0; +reg [2:0] layer7_out_30_V_address0; +reg layer7_out_30_V_ce0; +reg layer7_out_30_V_we0; +wire [7:0] layer7_out_30_V_q0; +reg [2:0] layer7_out_31_V_address0; +reg layer7_out_31_V_ce0; +reg layer7_out_31_V_we0; +wire [7:0] layer7_out_31_V_q0; +reg [2:0] layer7_out_32_V_address0; +reg layer7_out_32_V_ce0; +reg layer7_out_32_V_we0; +wire [7:0] layer7_out_32_V_q0; +reg [2:0] layer7_out_33_V_address0; +reg layer7_out_33_V_ce0; +reg layer7_out_33_V_we0; +wire [7:0] layer7_out_33_V_q0; +reg [2:0] layer7_out_34_V_address0; +reg layer7_out_34_V_ce0; +reg layer7_out_34_V_we0; +wire [7:0] layer7_out_34_V_q0; +reg [2:0] layer7_out_35_V_address0; +reg layer7_out_35_V_ce0; +reg layer7_out_35_V_we0; +wire [7:0] layer7_out_35_V_q0; +reg [2:0] layer7_out_36_V_address0; +reg layer7_out_36_V_ce0; +reg layer7_out_36_V_we0; +wire [7:0] layer7_out_36_V_q0; +reg [2:0] layer7_out_37_V_address0; +reg layer7_out_37_V_ce0; +reg layer7_out_37_V_we0; +wire [7:0] layer7_out_37_V_q0; +reg [2:0] layer7_out_38_V_address0; +reg layer7_out_38_V_ce0; +reg layer7_out_38_V_we0; +wire [7:0] layer7_out_38_V_q0; +reg [2:0] layer7_out_39_V_address0; +reg layer7_out_39_V_ce0; +reg layer7_out_39_V_we0; +wire [7:0] layer7_out_39_V_q0; +reg [2:0] layer7_out_40_V_address0; +reg layer7_out_40_V_ce0; +reg layer7_out_40_V_we0; +wire [7:0] layer7_out_40_V_q0; +reg [2:0] layer7_out_41_V_address0; +reg layer7_out_41_V_ce0; +reg layer7_out_41_V_we0; +wire [7:0] layer7_out_41_V_q0; +reg [2:0] layer7_out_42_V_address0; +reg layer7_out_42_V_ce0; +reg layer7_out_42_V_we0; +wire [7:0] layer7_out_42_V_q0; +reg [2:0] layer7_out_43_V_address0; +reg layer7_out_43_V_ce0; +reg layer7_out_43_V_we0; +wire [7:0] layer7_out_43_V_q0; +reg [2:0] layer7_out_44_V_address0; +reg layer7_out_44_V_ce0; +reg layer7_out_44_V_we0; +wire [7:0] layer7_out_44_V_q0; +reg [2:0] layer7_out_45_V_address0; +reg layer7_out_45_V_ce0; +reg layer7_out_45_V_we0; +wire [7:0] layer7_out_45_V_q0; +reg [2:0] layer7_out_46_V_address0; +reg layer7_out_46_V_ce0; +reg layer7_out_46_V_we0; +wire [7:0] layer7_out_46_V_q0; +reg [2:0] layer7_out_47_V_address0; +reg layer7_out_47_V_ce0; +reg layer7_out_47_V_we0; +wire [7:0] layer7_out_47_V_q0; +reg [2:0] layer7_out_48_V_address0; +reg layer7_out_48_V_ce0; +reg layer7_out_48_V_we0; +wire [7:0] layer7_out_48_V_q0; +reg [2:0] layer7_out_49_V_address0; +reg layer7_out_49_V_ce0; +reg layer7_out_49_V_we0; +wire [7:0] layer7_out_49_V_q0; +reg [2:0] layer7_out_50_V_address0; +reg layer7_out_50_V_ce0; +reg layer7_out_50_V_we0; +wire [7:0] layer7_out_50_V_q0; +reg [2:0] layer7_out_51_V_address0; +reg layer7_out_51_V_ce0; +reg layer7_out_51_V_we0; +wire [7:0] layer7_out_51_V_q0; +reg [2:0] layer7_out_52_V_address0; +reg layer7_out_52_V_ce0; +reg layer7_out_52_V_we0; +wire [7:0] layer7_out_52_V_q0; +reg [2:0] layer7_out_53_V_address0; +reg layer7_out_53_V_ce0; +reg layer7_out_53_V_we0; +wire [7:0] layer7_out_53_V_q0; +reg [2:0] layer7_out_54_V_address0; +reg layer7_out_54_V_ce0; +reg layer7_out_54_V_we0; +wire [7:0] layer7_out_54_V_q0; +reg [2:0] layer7_out_55_V_address0; +reg layer7_out_55_V_ce0; +reg layer7_out_55_V_we0; +wire [7:0] layer7_out_55_V_q0; +reg [2:0] layer7_out_56_V_address0; +reg layer7_out_56_V_ce0; +reg layer7_out_56_V_we0; +wire [7:0] layer7_out_56_V_q0; +reg [2:0] layer7_out_57_V_address0; +reg layer7_out_57_V_ce0; +reg layer7_out_57_V_we0; +wire [7:0] layer7_out_57_V_q0; +reg [2:0] layer7_out_58_V_address0; +reg layer7_out_58_V_ce0; +reg layer7_out_58_V_we0; +wire [7:0] layer7_out_58_V_q0; +reg [2:0] layer7_out_59_V_address0; +reg layer7_out_59_V_ce0; +reg layer7_out_59_V_we0; +wire [7:0] layer7_out_59_V_q0; +reg [2:0] layer7_out_60_V_address0; +reg layer7_out_60_V_ce0; +reg layer7_out_60_V_we0; +wire [7:0] layer7_out_60_V_q0; +reg [2:0] layer7_out_61_V_address0; +reg layer7_out_61_V_ce0; +reg layer7_out_61_V_we0; +wire [7:0] layer7_out_61_V_q0; +reg [2:0] layer7_out_62_V_address0; +reg layer7_out_62_V_ce0; +reg layer7_out_62_V_we0; +wire [7:0] layer7_out_62_V_q0; +reg [2:0] layer7_out_63_V_address0; +reg layer7_out_63_V_ce0; +reg layer7_out_63_V_we0; +wire [7:0] layer7_out_63_V_q0; +reg [2:0] layer7_out_64_V_address0; +reg layer7_out_64_V_ce0; +reg layer7_out_64_V_we0; +wire [7:0] layer7_out_64_V_q0; +reg [2:0] layer7_out_65_V_address0; +reg layer7_out_65_V_ce0; +reg layer7_out_65_V_we0; +wire [7:0] layer7_out_65_V_q0; +reg [2:0] layer7_out_66_V_address0; +reg layer7_out_66_V_ce0; +reg layer7_out_66_V_we0; +wire [7:0] layer7_out_66_V_q0; +reg [2:0] layer7_out_67_V_address0; +reg layer7_out_67_V_ce0; +reg layer7_out_67_V_we0; +wire [7:0] layer7_out_67_V_q0; +reg [2:0] layer7_out_68_V_address0; +reg layer7_out_68_V_ce0; +reg layer7_out_68_V_we0; +wire [7:0] layer7_out_68_V_q0; +reg [2:0] layer7_out_69_V_address0; +reg layer7_out_69_V_ce0; +reg layer7_out_69_V_we0; +wire [7:0] layer7_out_69_V_q0; +reg [2:0] layer7_out_70_V_address0; +reg layer7_out_70_V_ce0; +reg layer7_out_70_V_we0; +wire [7:0] layer7_out_70_V_q0; +reg [2:0] layer7_out_71_V_address0; +reg layer7_out_71_V_ce0; +reg layer7_out_71_V_we0; +wire [7:0] layer7_out_71_V_q0; +reg [2:0] layer7_out_72_V_address0; +reg layer7_out_72_V_ce0; +reg layer7_out_72_V_we0; +wire [7:0] layer7_out_72_V_q0; +reg [2:0] layer7_out_73_V_address0; +reg layer7_out_73_V_ce0; +reg layer7_out_73_V_we0; +wire [7:0] layer7_out_73_V_q0; +reg [2:0] layer7_out_74_V_address0; +reg layer7_out_74_V_ce0; +reg layer7_out_74_V_we0; +wire [7:0] layer7_out_74_V_q0; +reg [2:0] layer7_out_75_V_address0; +reg layer7_out_75_V_ce0; +reg layer7_out_75_V_we0; +wire [7:0] layer7_out_75_V_q0; +reg [1:0] layer7_out_76_V_address0; +reg layer7_out_76_V_ce0; +reg layer7_out_76_V_we0; +wire [7:0] layer7_out_76_V_q0; +reg [1:0] layer7_out_77_V_address0; +reg layer7_out_77_V_ce0; +reg layer7_out_77_V_we0; +wire [7:0] layer7_out_77_V_q0; +reg [1:0] layer7_out_78_V_address0; +reg layer7_out_78_V_ce0; +reg layer7_out_78_V_we0; +wire [7:0] layer7_out_78_V_q0; +reg [1:0] layer7_out_79_V_address0; +reg layer7_out_79_V_ce0; +reg layer7_out_79_V_we0; +wire [7:0] layer7_out_79_V_q0; +reg [1:0] layer7_out_80_V_address0; +reg layer7_out_80_V_ce0; +reg layer7_out_80_V_we0; +wire [7:0] layer7_out_80_V_q0; +reg [1:0] layer7_out_81_V_address0; +reg layer7_out_81_V_ce0; +reg layer7_out_81_V_we0; +wire [7:0] layer7_out_81_V_q0; +reg [1:0] layer7_out_82_V_address0; +reg layer7_out_82_V_ce0; +reg layer7_out_82_V_we0; +wire [7:0] layer7_out_82_V_q0; +reg [1:0] layer7_out_83_V_address0; +reg layer7_out_83_V_ce0; +reg layer7_out_83_V_we0; +wire [7:0] layer7_out_83_V_q0; +reg [1:0] layer7_out_84_V_address0; +reg layer7_out_84_V_ce0; +reg layer7_out_84_V_we0; +wire [7:0] layer7_out_84_V_q0; +reg [1:0] layer7_out_85_V_address0; +reg layer7_out_85_V_ce0; +reg layer7_out_85_V_we0; +wire [7:0] layer7_out_85_V_q0; +reg [1:0] layer7_out_86_V_address0; +reg layer7_out_86_V_ce0; +reg layer7_out_86_V_we0; +wire [7:0] layer7_out_86_V_q0; +reg [1:0] layer7_out_87_V_address0; +reg layer7_out_87_V_ce0; +reg layer7_out_87_V_we0; +wire [7:0] layer7_out_87_V_q0; +reg [1:0] layer7_out_88_V_address0; +reg layer7_out_88_V_ce0; +reg layer7_out_88_V_we0; +wire [7:0] layer7_out_88_V_q0; +reg [1:0] layer7_out_89_V_address0; +reg layer7_out_89_V_ce0; +reg layer7_out_89_V_we0; +wire [7:0] layer7_out_89_V_q0; +reg [1:0] layer7_out_90_V_address0; +reg layer7_out_90_V_ce0; +reg layer7_out_90_V_we0; +wire [7:0] layer7_out_90_V_q0; +reg [1:0] layer7_out_91_V_address0; +reg layer7_out_91_V_ce0; +reg layer7_out_91_V_we0; +wire [7:0] layer7_out_91_V_q0; +reg [1:0] layer7_out_92_V_address0; +reg layer7_out_92_V_ce0; +reg layer7_out_92_V_we0; +wire [7:0] layer7_out_92_V_q0; +reg [1:0] layer7_out_93_V_address0; +reg layer7_out_93_V_ce0; +reg layer7_out_93_V_we0; +wire [7:0] layer7_out_93_V_q0; +reg [1:0] layer7_out_94_V_address0; +reg layer7_out_94_V_ce0; +reg layer7_out_94_V_we0; +wire [7:0] layer7_out_94_V_q0; +reg [1:0] layer7_out_95_V_address0; +reg layer7_out_95_V_ce0; +reg layer7_out_95_V_we0; +wire [7:0] layer7_out_95_V_q0; +reg [1:0] layer7_out_96_V_address0; +reg layer7_out_96_V_ce0; +reg layer7_out_96_V_we0; +wire [7:0] layer7_out_96_V_q0; +reg [1:0] layer7_out_97_V_address0; +reg layer7_out_97_V_ce0; +reg layer7_out_97_V_we0; +wire [7:0] layer7_out_97_V_q0; +reg [1:0] layer7_out_98_V_address0; +reg layer7_out_98_V_ce0; +reg layer7_out_98_V_we0; +wire [7:0] layer7_out_98_V_q0; +reg [1:0] layer7_out_99_V_address0; +reg layer7_out_99_V_ce0; +reg layer7_out_99_V_we0; +wire [7:0] layer7_out_99_V_q0; +reg [1:0] layer7_out_100_V_address0; +reg layer7_out_100_V_ce0; +reg layer7_out_100_V_we0; +wire [7:0] layer7_out_100_V_q0; +reg [1:0] layer7_out_101_V_address0; +reg layer7_out_101_V_ce0; +reg layer7_out_101_V_we0; +wire [7:0] layer7_out_101_V_q0; +reg [1:0] layer7_out_102_V_address0; +reg layer7_out_102_V_ce0; +reg layer7_out_102_V_we0; +wire [7:0] layer7_out_102_V_q0; +reg [1:0] layer7_out_103_V_address0; +reg layer7_out_103_V_ce0; +reg layer7_out_103_V_we0; +wire [7:0] layer7_out_103_V_q0; +reg [1:0] layer7_out_104_V_address0; +reg layer7_out_104_V_ce0; +reg layer7_out_104_V_we0; +wire [7:0] layer7_out_104_V_q0; +reg [1:0] layer7_out_105_V_address0; +reg layer7_out_105_V_ce0; +reg layer7_out_105_V_we0; +wire [7:0] layer7_out_105_V_q0; +reg [1:0] layer7_out_106_V_address0; +reg layer7_out_106_V_ce0; +reg layer7_out_106_V_we0; +wire [7:0] layer7_out_106_V_q0; +reg [1:0] layer7_out_107_V_address0; +reg layer7_out_107_V_ce0; +reg layer7_out_107_V_we0; +wire [7:0] layer7_out_107_V_q0; +reg [1:0] layer7_out_108_V_address0; +reg layer7_out_108_V_ce0; +reg layer7_out_108_V_we0; +wire [7:0] layer7_out_108_V_q0; +reg [1:0] layer7_out_109_V_address0; +reg layer7_out_109_V_ce0; +reg layer7_out_109_V_we0; +wire [7:0] layer7_out_109_V_q0; +reg [1:0] layer7_out_110_V_address0; +reg layer7_out_110_V_ce0; +reg layer7_out_110_V_we0; +wire [7:0] layer7_out_110_V_q0; +reg [1:0] layer7_out_111_V_address0; +reg layer7_out_111_V_ce0; +reg layer7_out_111_V_we0; +wire [7:0] layer7_out_111_V_q0; +reg [1:0] layer7_out_112_V_address0; +reg layer7_out_112_V_ce0; +reg layer7_out_112_V_we0; +wire [7:0] layer7_out_112_V_q0; +reg [1:0] layer7_out_113_V_address0; +reg layer7_out_113_V_ce0; +reg layer7_out_113_V_we0; +wire [7:0] layer7_out_113_V_q0; +reg [1:0] layer7_out_114_V_address0; +reg layer7_out_114_V_ce0; +reg layer7_out_114_V_we0; +wire [7:0] layer7_out_114_V_q0; +reg [1:0] layer7_out_115_V_address0; +reg layer7_out_115_V_ce0; +reg layer7_out_115_V_we0; +wire [7:0] layer7_out_115_V_q0; +reg [1:0] layer7_out_116_V_address0; +reg layer7_out_116_V_ce0; +reg layer7_out_116_V_we0; +wire [7:0] layer7_out_116_V_q0; +reg [1:0] layer7_out_117_V_address0; +reg layer7_out_117_V_ce0; +reg layer7_out_117_V_we0; +wire [7:0] layer7_out_117_V_q0; +reg [1:0] layer7_out_118_V_address0; +reg layer7_out_118_V_ce0; +reg layer7_out_118_V_we0; +wire [7:0] layer7_out_118_V_q0; +reg [1:0] layer7_out_119_V_address0; +reg layer7_out_119_V_ce0; +reg layer7_out_119_V_we0; +wire [7:0] layer7_out_119_V_q0; +reg [1:0] layer7_out_120_V_address0; +reg layer7_out_120_V_ce0; +reg layer7_out_120_V_we0; +wire [7:0] layer7_out_120_V_q0; +reg [1:0] layer7_out_121_V_address0; +reg layer7_out_121_V_ce0; +reg layer7_out_121_V_we0; +wire [7:0] layer7_out_121_V_q0; +reg [1:0] layer7_out_122_V_address0; +reg layer7_out_122_V_ce0; +reg layer7_out_122_V_we0; +wire [7:0] layer7_out_122_V_q0; +reg [1:0] layer7_out_123_V_address0; +reg layer7_out_123_V_ce0; +reg layer7_out_123_V_we0; +wire [7:0] layer7_out_123_V_q0; +reg [1:0] layer7_out_124_V_address0; +reg layer7_out_124_V_ce0; +reg layer7_out_124_V_we0; +wire [7:0] layer7_out_124_V_q0; +reg [1:0] layer7_out_125_V_address0; +reg layer7_out_125_V_ce0; +reg layer7_out_125_V_we0; +wire [7:0] layer7_out_125_V_q0; +reg [1:0] layer7_out_126_V_address0; +reg layer7_out_126_V_ce0; +reg layer7_out_126_V_we0; +wire [7:0] layer7_out_126_V_q0; +reg [1:0] layer7_out_127_V_address0; +reg layer7_out_127_V_ce0; +reg layer7_out_127_V_we0; +wire [7:0] layer7_out_127_V_q0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_start; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_done; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_idle; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_ready; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_0_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_0_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_1_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_1_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_2_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_2_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_3_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_3_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_4_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_4_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_5_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_5_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_6_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_6_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_7_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_7_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_8_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_8_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_9_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_9_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_10_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_10_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_11_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_11_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_12_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_12_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_13_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_13_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_14_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_14_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_15_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_15_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_16_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_16_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_17_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_17_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_18_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_18_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_19_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_19_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_20_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_20_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_21_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_21_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_22_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_22_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_23_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_23_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_24_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_24_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_25_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_25_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_26_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_26_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_27_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_27_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_28_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_28_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_29_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_29_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_30_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_30_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_31_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_31_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_32_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_32_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_33_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_33_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_34_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_34_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_35_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_35_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_36_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_36_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_37_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_37_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_38_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_38_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_39_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_39_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_40_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_40_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_41_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_41_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_42_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_42_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_43_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_43_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_44_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_44_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_45_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_45_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_46_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_46_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_47_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_47_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_48_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_48_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_49_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_49_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_50_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_50_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_51_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_51_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_52_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_52_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_53_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_53_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_54_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_54_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_55_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_55_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_56_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_56_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_57_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_57_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_58_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_58_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_59_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_59_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_60_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_60_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_61_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_61_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_62_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_62_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_63_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_63_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_64_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_64_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_65_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_65_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_66_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_66_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_67_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_67_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_68_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_68_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_69_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_69_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_70_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_70_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_71_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_71_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_72_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_72_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_73_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_73_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_74_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_74_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_75_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_75_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_76_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_76_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_77_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_77_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_78_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_78_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_79_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_79_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_80_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_80_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_81_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_81_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_82_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_82_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_83_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_83_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_84_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_84_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_85_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_85_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_86_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_86_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_87_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_87_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_88_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_88_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_89_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_89_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_90_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_90_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_91_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_91_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_92_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_92_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_93_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_93_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_94_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_94_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_95_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_95_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_96_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_96_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_97_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_97_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_98_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_98_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_99_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_99_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_100_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_100_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_101_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_101_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_102_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_102_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_103_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_103_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_104_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_104_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_105_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_105_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_106_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_106_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_107_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_107_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_108_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_108_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_109_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_109_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_110_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_110_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_111_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_111_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_112_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_112_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_113_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_113_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_114_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_114_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_115_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_115_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_116_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_116_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_117_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_117_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_118_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_118_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_119_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_119_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_120_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_120_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_121_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_121_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_122_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_122_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_123_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_123_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_124_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_124_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_125_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_125_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_126_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_126_V_ce0; +wire [2:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_127_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_127_V_ce0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_0_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_0_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_0_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_0_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_1_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_1_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_1_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_1_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_2_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_2_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_2_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_2_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_3_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_3_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_3_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_3_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_4_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_4_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_4_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_4_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_5_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_5_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_5_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_5_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_6_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_6_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_6_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_6_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_7_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_7_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_7_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_7_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_8_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_8_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_8_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_8_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_9_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_9_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_9_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_9_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_10_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_10_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_10_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_10_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_11_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_11_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_11_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_11_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_12_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_12_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_12_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_12_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_13_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_13_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_13_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_13_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_14_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_14_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_14_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_14_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_15_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_15_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_15_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_15_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_16_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_16_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_16_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_16_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_17_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_17_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_17_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_17_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_18_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_18_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_18_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_18_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_19_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_19_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_19_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_19_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_20_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_20_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_20_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_20_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_21_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_21_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_21_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_21_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_22_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_22_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_22_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_22_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_23_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_23_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_23_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_23_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_24_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_24_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_24_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_24_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_25_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_25_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_25_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_25_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_26_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_26_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_26_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_26_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_27_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_27_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_27_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_27_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_28_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_28_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_28_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_28_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_29_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_29_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_29_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_29_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_30_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_30_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_30_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_30_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_31_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_31_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_31_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_31_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_32_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_32_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_32_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_32_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_33_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_33_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_33_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_33_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_34_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_34_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_34_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_34_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_35_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_35_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_35_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_35_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_36_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_36_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_36_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_36_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_37_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_37_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_37_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_37_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_38_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_38_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_38_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_38_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_39_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_39_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_39_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_39_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_40_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_40_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_40_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_40_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_41_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_41_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_41_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_41_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_42_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_42_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_42_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_42_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_43_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_43_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_43_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_43_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_44_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_44_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_44_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_44_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_45_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_45_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_45_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_45_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_46_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_46_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_46_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_46_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_47_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_47_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_47_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_47_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_48_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_48_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_48_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_48_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_49_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_49_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_49_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_49_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_50_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_50_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_50_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_50_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_51_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_51_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_51_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_51_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_52_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_52_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_52_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_52_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_53_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_53_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_53_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_53_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_54_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_54_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_54_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_54_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_55_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_55_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_55_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_55_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_56_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_56_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_56_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_56_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_57_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_57_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_57_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_57_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_58_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_58_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_58_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_58_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_59_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_59_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_59_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_59_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_60_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_60_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_60_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_60_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_61_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_61_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_61_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_61_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_62_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_62_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_62_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_62_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_63_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_63_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_63_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_63_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_64_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_64_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_64_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_64_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_65_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_65_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_65_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_65_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_66_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_66_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_66_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_66_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_67_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_67_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_67_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_67_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_68_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_68_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_68_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_68_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_69_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_69_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_69_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_69_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_70_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_70_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_70_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_70_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_71_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_71_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_71_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_71_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_72_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_72_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_72_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_72_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_73_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_73_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_73_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_73_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_74_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_74_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_74_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_74_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_75_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_75_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_75_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_75_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_76_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_76_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_76_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_76_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_77_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_77_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_77_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_77_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_78_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_78_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_78_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_78_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_79_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_79_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_79_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_79_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_80_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_80_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_80_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_80_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_81_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_81_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_81_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_81_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_82_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_82_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_82_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_82_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_83_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_83_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_83_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_83_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_84_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_84_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_84_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_84_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_85_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_85_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_85_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_85_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_86_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_86_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_86_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_86_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_87_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_87_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_87_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_87_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_88_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_88_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_88_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_88_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_89_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_89_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_89_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_89_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_90_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_90_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_90_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_90_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_91_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_91_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_91_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_91_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_92_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_92_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_92_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_92_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_93_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_93_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_93_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_93_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_94_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_94_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_94_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_94_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_95_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_95_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_95_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_95_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_96_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_96_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_96_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_96_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_97_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_97_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_97_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_97_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_98_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_98_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_98_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_98_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_99_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_99_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_99_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_99_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_100_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_100_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_100_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_100_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_101_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_101_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_101_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_101_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_102_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_102_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_102_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_102_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_103_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_103_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_103_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_103_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_104_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_104_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_104_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_104_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_105_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_105_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_105_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_105_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_106_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_106_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_106_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_106_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_107_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_107_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_107_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_107_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_108_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_108_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_108_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_108_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_109_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_109_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_109_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_109_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_110_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_110_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_110_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_110_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_111_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_111_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_111_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_111_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_112_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_112_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_112_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_112_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_113_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_113_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_113_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_113_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_114_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_114_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_114_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_114_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_115_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_115_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_115_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_115_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_116_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_116_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_116_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_116_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_117_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_117_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_117_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_117_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_118_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_118_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_118_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_118_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_119_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_119_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_119_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_119_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_120_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_120_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_120_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_120_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_121_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_121_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_121_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_121_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_122_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_122_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_122_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_122_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_123_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_123_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_123_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_123_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_124_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_124_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_124_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_124_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_125_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_125_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_125_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_125_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_126_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_126_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_126_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_126_V_d0; +wire [4:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_127_V_address0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_127_V_ce0; +wire grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_127_V_we0; +wire [7:0] grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_127_V_d0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_start; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_done; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_idle; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_ready; +wire [6:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_data_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_data_V_ce0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_0_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_0_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_0_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_0_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_1_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_1_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_1_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_1_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_2_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_2_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_2_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_2_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_3_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_3_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_3_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_3_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_4_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_4_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_4_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_4_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_5_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_5_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_5_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_5_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_6_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_6_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_6_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_6_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_7_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_7_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_7_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_7_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_8_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_8_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_8_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_8_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_9_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_9_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_9_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_9_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_10_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_10_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_10_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_10_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_11_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_11_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_11_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_11_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_12_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_12_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_12_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_12_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_13_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_13_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_13_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_13_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_14_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_14_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_14_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_14_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_15_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_15_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_15_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_15_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_16_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_16_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_16_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_16_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_17_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_17_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_17_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_17_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_18_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_18_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_18_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_18_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_19_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_19_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_19_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_19_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_20_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_20_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_20_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_20_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_21_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_21_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_21_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_21_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_22_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_22_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_22_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_22_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_23_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_23_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_23_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_23_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_24_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_24_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_24_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_24_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_25_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_25_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_25_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_25_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_26_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_26_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_26_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_26_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_27_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_27_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_27_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_27_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_28_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_28_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_28_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_28_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_29_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_29_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_29_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_29_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_30_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_30_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_30_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_30_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_31_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_31_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_31_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_31_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_32_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_32_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_32_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_32_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_33_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_33_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_33_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_33_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_34_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_34_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_34_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_34_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_35_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_35_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_35_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_35_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_36_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_36_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_36_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_36_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_37_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_37_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_37_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_37_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_38_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_38_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_38_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_38_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_39_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_39_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_39_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_39_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_40_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_40_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_40_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_40_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_41_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_41_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_41_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_41_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_42_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_42_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_42_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_42_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_43_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_43_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_43_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_43_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_44_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_44_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_44_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_44_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_45_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_45_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_45_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_45_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_46_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_46_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_46_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_46_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_47_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_47_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_47_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_47_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_48_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_48_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_48_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_48_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_49_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_49_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_49_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_49_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_50_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_50_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_50_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_50_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_51_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_51_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_51_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_51_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_52_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_52_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_52_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_52_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_53_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_53_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_53_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_53_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_54_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_54_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_54_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_54_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_55_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_55_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_55_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_55_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_56_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_56_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_56_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_56_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_57_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_57_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_57_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_57_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_58_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_58_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_58_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_58_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_59_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_59_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_59_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_59_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_60_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_60_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_60_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_60_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_61_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_61_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_61_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_61_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_62_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_62_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_62_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_62_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_63_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_63_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_63_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_63_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_64_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_64_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_64_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_64_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_65_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_65_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_65_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_65_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_66_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_66_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_66_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_66_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_67_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_67_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_67_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_67_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_68_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_68_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_68_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_68_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_69_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_69_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_69_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_69_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_70_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_70_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_70_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_70_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_71_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_71_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_71_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_71_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_72_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_72_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_72_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_72_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_73_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_73_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_73_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_73_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_74_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_74_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_74_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_74_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_75_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_75_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_75_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_75_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_76_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_76_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_76_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_76_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_77_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_77_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_77_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_77_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_78_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_78_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_78_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_78_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_79_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_79_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_79_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_79_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_80_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_80_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_80_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_80_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_81_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_81_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_81_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_81_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_82_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_82_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_82_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_82_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_83_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_83_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_83_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_83_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_84_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_84_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_84_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_84_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_85_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_85_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_85_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_85_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_86_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_86_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_86_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_86_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_87_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_87_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_87_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_87_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_88_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_88_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_88_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_88_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_89_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_89_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_89_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_89_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_90_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_90_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_90_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_90_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_91_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_91_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_91_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_91_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_92_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_92_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_92_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_92_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_93_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_93_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_93_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_93_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_94_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_94_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_94_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_94_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_95_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_95_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_95_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_95_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_96_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_96_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_96_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_96_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_97_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_97_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_97_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_97_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_98_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_98_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_98_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_98_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_99_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_99_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_99_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_99_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_100_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_100_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_100_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_100_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_101_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_101_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_101_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_101_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_102_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_102_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_102_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_102_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_103_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_103_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_103_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_103_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_104_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_104_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_104_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_104_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_105_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_105_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_105_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_105_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_106_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_106_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_106_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_106_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_107_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_107_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_107_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_107_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_108_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_108_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_108_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_108_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_109_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_109_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_109_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_109_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_110_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_110_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_110_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_110_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_111_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_111_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_111_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_111_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_112_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_112_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_112_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_112_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_113_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_113_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_113_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_113_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_114_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_114_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_114_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_114_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_115_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_115_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_115_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_115_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_116_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_116_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_116_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_116_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_117_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_117_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_117_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_117_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_118_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_118_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_118_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_118_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_119_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_119_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_119_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_119_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_120_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_120_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_120_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_120_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_121_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_121_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_121_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_121_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_122_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_122_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_122_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_122_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_123_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_123_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_123_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_123_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_124_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_124_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_124_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_124_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_125_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_125_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_125_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_125_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_126_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_126_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_126_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_126_V_d0; +wire [4:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_127_V_address0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_127_V_ce0; +wire grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_127_V_we0; +wire [7:0] grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_127_V_d0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_we1; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_we0; +wire [2:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_we1; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_address0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_ce0; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_d0; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_we0; +wire [1:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_address1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_ce1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_d1; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_we1; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_0_V; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_1_V; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_2_V; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_3_V; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_4_V; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_5_V; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_6_V; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_7_V; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_8_V; +wire [7:0] grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_9_V; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_start; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_0_V_ap_vld; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_done; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_1_V_ap_vld; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_2_V_ap_vld; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_3_V_ap_vld; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_4_V_ap_vld; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_5_V_ap_vld; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_6_V_ap_vld; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_7_V_ap_vld; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_8_V_ap_vld; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_9_V_ap_vld; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_ready; +wire grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_idle; +reg grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_continue; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_start; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_done; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_idle; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_ready; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_0_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_0_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_1_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_1_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_2_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_2_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_3_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_3_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_4_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_4_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_5_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_5_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_6_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_6_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_7_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_7_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_8_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_8_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_9_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_9_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_10_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_10_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_11_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_11_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_12_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_12_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_13_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_13_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_14_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_14_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_15_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_15_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_16_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_16_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_17_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_17_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_18_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_18_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_19_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_19_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_20_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_20_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_21_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_21_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_22_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_22_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_23_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_23_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_24_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_24_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_25_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_25_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_26_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_26_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_27_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_27_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_28_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_28_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_29_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_29_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_30_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_30_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_31_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_31_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_32_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_32_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_33_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_33_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_34_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_34_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_35_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_35_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_36_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_36_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_37_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_37_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_38_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_38_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_39_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_39_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_40_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_40_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_41_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_41_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_42_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_42_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_43_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_43_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_44_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_44_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_45_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_45_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_46_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_46_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_47_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_47_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_48_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_48_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_49_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_49_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_50_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_50_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_51_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_51_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_52_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_52_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_53_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_53_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_54_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_54_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_55_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_55_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_56_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_56_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_57_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_57_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_58_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_58_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_59_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_59_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_60_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_60_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_61_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_61_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_62_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_62_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_63_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_63_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_64_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_64_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_65_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_65_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_66_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_66_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_67_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_67_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_68_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_68_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_69_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_69_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_70_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_70_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_71_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_71_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_72_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_72_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_73_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_73_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_74_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_74_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_75_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_75_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_76_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_76_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_77_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_77_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_78_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_78_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_79_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_79_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_80_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_80_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_81_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_81_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_82_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_82_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_83_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_83_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_84_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_84_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_85_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_85_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_86_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_86_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_87_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_87_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_88_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_88_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_89_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_89_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_90_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_90_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_91_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_91_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_92_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_92_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_93_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_93_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_94_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_94_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_95_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_95_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_96_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_96_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_97_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_97_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_98_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_98_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_99_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_99_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_100_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_100_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_101_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_101_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_102_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_102_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_103_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_103_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_104_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_104_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_105_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_105_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_106_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_106_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_107_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_107_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_108_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_108_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_109_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_109_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_110_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_110_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_111_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_111_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_112_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_112_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_113_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_113_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_114_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_114_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_115_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_115_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_116_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_116_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_117_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_117_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_118_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_118_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_119_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_119_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_120_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_120_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_121_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_121_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_122_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_122_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_123_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_123_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_124_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_124_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_125_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_125_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_126_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_126_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_127_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_127_V_ce0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_0_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_0_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_0_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_0_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_1_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_1_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_1_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_1_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_2_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_2_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_2_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_2_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_3_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_3_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_3_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_3_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_4_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_4_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_4_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_4_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_5_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_5_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_5_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_5_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_6_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_6_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_6_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_6_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_7_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_7_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_7_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_7_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_8_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_8_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_8_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_8_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_9_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_9_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_9_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_9_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_10_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_10_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_10_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_10_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_11_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_11_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_11_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_11_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_12_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_12_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_12_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_12_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_13_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_13_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_13_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_13_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_14_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_14_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_14_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_14_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_15_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_15_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_15_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_15_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_16_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_16_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_16_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_16_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_17_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_17_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_17_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_17_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_18_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_18_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_18_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_18_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_19_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_19_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_19_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_19_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_20_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_20_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_20_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_20_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_21_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_21_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_21_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_21_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_22_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_22_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_22_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_22_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_23_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_23_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_23_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_23_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_24_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_24_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_24_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_24_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_25_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_25_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_25_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_25_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_26_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_26_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_26_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_26_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_27_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_27_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_27_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_27_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_28_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_28_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_28_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_28_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_29_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_29_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_29_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_29_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_30_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_30_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_30_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_30_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_31_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_31_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_31_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_31_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_32_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_32_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_32_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_32_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_33_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_33_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_33_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_33_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_34_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_34_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_34_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_34_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_35_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_35_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_35_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_35_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_36_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_36_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_36_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_36_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_37_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_37_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_37_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_37_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_38_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_38_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_38_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_38_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_39_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_39_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_39_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_39_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_40_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_40_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_40_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_40_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_41_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_41_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_41_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_41_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_42_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_42_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_42_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_42_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_43_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_43_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_43_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_43_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_44_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_44_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_44_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_44_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_45_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_45_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_45_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_45_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_46_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_46_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_46_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_46_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_47_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_47_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_47_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_47_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_48_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_48_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_48_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_48_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_49_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_49_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_49_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_49_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_50_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_50_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_50_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_50_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_51_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_51_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_51_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_51_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_52_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_52_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_52_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_52_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_53_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_53_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_53_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_53_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_54_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_54_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_54_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_54_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_55_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_55_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_55_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_55_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_56_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_56_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_56_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_56_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_57_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_57_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_57_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_57_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_58_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_58_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_58_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_58_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_59_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_59_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_59_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_59_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_60_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_60_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_60_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_60_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_61_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_61_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_61_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_61_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_62_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_62_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_62_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_62_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_63_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_63_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_63_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_63_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_64_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_64_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_64_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_64_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_65_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_65_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_65_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_65_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_66_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_66_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_66_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_66_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_67_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_67_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_67_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_67_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_68_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_68_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_68_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_68_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_69_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_69_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_69_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_69_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_70_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_70_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_70_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_70_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_71_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_71_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_71_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_71_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_72_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_72_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_72_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_72_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_73_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_73_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_73_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_73_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_74_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_74_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_74_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_74_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_75_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_75_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_75_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_75_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_76_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_76_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_76_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_76_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_77_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_77_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_77_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_77_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_78_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_78_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_78_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_78_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_79_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_79_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_79_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_79_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_80_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_80_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_80_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_80_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_81_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_81_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_81_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_81_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_82_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_82_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_82_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_82_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_83_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_83_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_83_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_83_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_84_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_84_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_84_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_84_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_85_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_85_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_85_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_85_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_86_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_86_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_86_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_86_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_87_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_87_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_87_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_87_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_88_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_88_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_88_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_88_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_89_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_89_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_89_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_89_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_90_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_90_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_90_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_90_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_91_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_91_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_91_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_91_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_92_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_92_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_92_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_92_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_93_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_93_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_93_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_93_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_94_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_94_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_94_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_94_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_95_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_95_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_95_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_95_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_96_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_96_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_96_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_96_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_97_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_97_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_97_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_97_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_98_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_98_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_98_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_98_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_99_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_99_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_99_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_99_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_100_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_100_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_100_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_100_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_101_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_101_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_101_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_101_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_102_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_102_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_102_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_102_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_103_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_103_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_103_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_103_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_104_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_104_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_104_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_104_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_105_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_105_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_105_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_105_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_106_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_106_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_106_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_106_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_107_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_107_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_107_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_107_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_108_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_108_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_108_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_108_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_109_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_109_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_109_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_109_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_110_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_110_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_110_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_110_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_111_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_111_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_111_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_111_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_112_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_112_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_112_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_112_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_113_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_113_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_113_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_113_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_114_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_114_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_114_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_114_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_115_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_115_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_115_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_115_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_116_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_116_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_116_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_116_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_117_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_117_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_117_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_117_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_118_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_118_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_118_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_118_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_119_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_119_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_119_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_119_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_120_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_120_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_120_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_120_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_121_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_121_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_121_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_121_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_122_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_122_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_122_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_122_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_123_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_123_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_123_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_123_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_124_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_124_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_124_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_124_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_125_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_125_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_125_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_125_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_126_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_126_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_126_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_126_V_d0; +wire [1:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_127_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_127_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_127_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_127_V_d0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_start; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_done; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_idle; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_ready; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_0_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_0_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_1_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_1_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_2_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_2_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_3_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_3_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_4_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_4_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_5_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_5_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_6_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_6_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_7_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_7_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_8_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_8_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_9_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_9_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_10_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_10_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_11_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_11_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_12_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_12_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_13_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_13_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_14_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_14_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_15_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_15_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_16_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_16_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_17_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_17_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_18_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_18_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_19_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_19_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_20_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_20_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_21_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_21_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_22_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_22_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_23_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_23_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_24_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_24_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_25_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_25_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_26_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_26_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_27_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_27_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_28_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_28_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_29_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_29_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_30_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_30_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_31_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_31_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_32_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_32_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_33_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_33_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_34_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_34_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_35_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_35_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_36_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_36_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_37_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_37_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_38_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_38_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_39_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_39_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_40_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_40_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_41_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_41_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_42_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_42_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_43_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_43_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_44_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_44_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_45_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_45_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_46_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_46_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_47_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_47_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_48_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_48_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_49_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_49_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_50_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_50_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_51_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_51_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_52_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_52_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_53_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_53_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_54_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_54_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_55_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_55_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_56_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_56_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_57_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_57_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_58_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_58_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_59_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_59_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_60_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_60_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_61_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_61_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_62_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_62_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_63_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_63_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_64_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_64_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_65_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_65_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_66_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_66_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_67_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_67_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_68_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_68_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_69_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_69_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_70_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_70_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_71_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_71_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_72_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_72_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_73_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_73_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_74_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_74_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_75_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_75_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_76_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_76_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_77_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_77_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_78_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_78_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_79_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_79_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_80_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_80_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_81_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_81_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_82_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_82_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_83_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_83_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_84_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_84_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_85_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_85_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_86_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_86_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_87_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_87_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_88_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_88_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_89_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_89_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_90_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_90_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_91_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_91_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_92_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_92_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_93_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_93_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_94_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_94_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_95_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_95_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_96_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_96_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_97_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_97_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_98_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_98_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_99_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_99_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_100_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_100_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_101_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_101_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_102_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_102_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_103_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_103_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_104_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_104_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_105_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_105_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_106_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_106_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_107_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_107_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_108_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_108_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_109_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_109_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_110_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_110_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_111_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_111_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_112_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_112_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_113_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_113_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_114_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_114_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_115_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_115_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_116_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_116_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_117_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_117_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_118_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_118_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_119_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_119_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_120_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_120_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_121_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_121_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_122_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_122_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_123_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_123_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_124_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_124_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_125_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_125_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_126_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_126_V_ce0; +wire [4:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_127_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_127_V_ce0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_0_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_0_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_0_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_0_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_1_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_1_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_1_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_1_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_2_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_2_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_2_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_2_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_3_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_3_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_3_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_3_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_4_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_4_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_4_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_4_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_5_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_5_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_5_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_5_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_6_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_6_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_6_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_6_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_7_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_7_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_7_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_7_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_8_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_8_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_8_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_8_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_9_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_9_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_9_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_9_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_10_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_10_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_10_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_10_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_11_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_11_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_11_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_11_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_12_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_12_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_12_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_12_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_13_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_13_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_13_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_13_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_14_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_14_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_14_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_14_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_15_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_15_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_15_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_15_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_16_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_16_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_16_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_16_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_17_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_17_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_17_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_17_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_18_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_18_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_18_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_18_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_19_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_19_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_19_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_19_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_20_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_20_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_20_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_20_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_21_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_21_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_21_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_21_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_22_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_22_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_22_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_22_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_23_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_23_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_23_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_23_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_24_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_24_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_24_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_24_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_25_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_25_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_25_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_25_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_26_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_26_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_26_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_26_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_27_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_27_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_27_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_27_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_28_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_28_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_28_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_28_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_29_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_29_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_29_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_29_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_30_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_30_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_30_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_30_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_31_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_31_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_31_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_31_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_32_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_32_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_32_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_32_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_33_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_33_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_33_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_33_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_34_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_34_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_34_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_34_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_35_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_35_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_35_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_35_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_36_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_36_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_36_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_36_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_37_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_37_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_37_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_37_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_38_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_38_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_38_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_38_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_39_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_39_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_39_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_39_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_40_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_40_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_40_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_40_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_41_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_41_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_41_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_41_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_42_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_42_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_42_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_42_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_43_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_43_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_43_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_43_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_44_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_44_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_44_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_44_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_45_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_45_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_45_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_45_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_46_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_46_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_46_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_46_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_47_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_47_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_47_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_47_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_48_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_48_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_48_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_48_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_49_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_49_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_49_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_49_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_50_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_50_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_50_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_50_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_51_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_51_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_51_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_51_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_52_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_52_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_52_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_52_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_53_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_53_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_53_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_53_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_54_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_54_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_54_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_54_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_55_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_55_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_55_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_55_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_56_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_56_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_56_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_56_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_57_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_57_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_57_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_57_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_58_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_58_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_58_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_58_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_59_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_59_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_59_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_59_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_60_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_60_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_60_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_60_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_61_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_61_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_61_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_61_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_62_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_62_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_62_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_62_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_63_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_63_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_63_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_63_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_64_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_64_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_64_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_64_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_65_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_65_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_65_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_65_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_66_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_66_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_66_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_66_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_67_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_67_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_67_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_67_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_68_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_68_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_68_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_68_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_69_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_69_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_69_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_69_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_70_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_70_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_70_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_70_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_71_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_71_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_71_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_71_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_72_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_72_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_72_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_72_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_73_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_73_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_73_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_73_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_74_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_74_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_74_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_74_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_75_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_75_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_75_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_75_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_76_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_76_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_76_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_76_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_77_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_77_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_77_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_77_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_78_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_78_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_78_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_78_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_79_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_79_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_79_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_79_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_80_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_80_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_80_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_80_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_81_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_81_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_81_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_81_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_82_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_82_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_82_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_82_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_83_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_83_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_83_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_83_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_84_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_84_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_84_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_84_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_85_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_85_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_85_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_85_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_86_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_86_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_86_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_86_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_87_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_87_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_87_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_87_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_88_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_88_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_88_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_88_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_89_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_89_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_89_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_89_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_90_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_90_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_90_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_90_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_91_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_91_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_91_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_91_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_92_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_92_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_92_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_92_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_93_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_93_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_93_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_93_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_94_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_94_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_94_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_94_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_95_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_95_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_95_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_95_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_96_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_96_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_96_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_96_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_97_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_97_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_97_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_97_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_98_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_98_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_98_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_98_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_99_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_99_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_99_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_99_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_100_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_100_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_100_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_100_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_101_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_101_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_101_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_101_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_102_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_102_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_102_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_102_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_103_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_103_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_103_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_103_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_104_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_104_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_104_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_104_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_105_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_105_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_105_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_105_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_106_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_106_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_106_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_106_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_107_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_107_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_107_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_107_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_108_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_108_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_108_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_108_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_109_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_109_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_109_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_109_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_110_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_110_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_110_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_110_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_111_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_111_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_111_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_111_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_112_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_112_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_112_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_112_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_113_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_113_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_113_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_113_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_114_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_114_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_114_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_114_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_115_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_115_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_115_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_115_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_116_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_116_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_116_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_116_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_117_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_117_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_117_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_117_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_118_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_118_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_118_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_118_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_119_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_119_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_119_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_119_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_120_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_120_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_120_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_120_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_121_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_121_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_121_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_121_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_122_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_122_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_122_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_122_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_123_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_123_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_123_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_123_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_124_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_124_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_124_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_124_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_125_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_125_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_125_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_125_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_126_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_126_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_126_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_126_V_d0; +wire [2:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_127_V_address0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_127_V_ce0; +wire grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_127_V_we0; +wire [7:0] grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_127_V_d0; +reg grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_start_reg; +reg grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_start_reg; +reg grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_start_reg; +wire ap_sync_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_ready; +wire ap_sync_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_done; +reg ap_block_state10_on_subcall_done; +reg ap_sync_reg_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_ready; +reg ap_sync_reg_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_done; +reg [7:0] layer9_out_0_V_fu_2130; +reg [7:0] layer9_out_1_V_fu_2134; +reg [7:0] layer9_out_2_V_fu_2138; +reg [7:0] layer9_out_3_V_fu_2142; +reg [7:0] layer9_out_4_V_fu_2146; +reg [7:0] layer9_out_5_V_fu_2150; +reg [7:0] layer9_out_6_V_fu_2154; +reg [7:0] layer9_out_7_V_fu_2158; +reg [7:0] layer9_out_8_V_fu_2162; +reg [7:0] layer9_out_9_V_fu_2166; +reg grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_start_reg; +reg grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_start_reg; +reg [3:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 4'd0; +#0 grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_start_reg = 1'b0; +#0 grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_start_reg = 1'b0; +#0 grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_start_reg = 1'b0; +#0 ap_sync_reg_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_ready = 1'b0; +#0 ap_sync_reg_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_done = 1'b0; +#0 grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_start_reg = 1'b0; +#0 grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_start_reg = 1'b0; +end + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_0_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_0_V_address0), + .ce0(layer2_out_0_V_ce0), + .we0(layer2_out_0_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_0_V_d0), + .q0(layer2_out_0_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_1_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_1_V_address0), + .ce0(layer2_out_1_V_ce0), + .we0(layer2_out_1_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_1_V_d0), + .q0(layer2_out_1_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_2_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_2_V_address0), + .ce0(layer2_out_2_V_ce0), + .we0(layer2_out_2_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_2_V_d0), + .q0(layer2_out_2_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_3_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_3_V_address0), + .ce0(layer2_out_3_V_ce0), + .we0(layer2_out_3_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_3_V_d0), + .q0(layer2_out_3_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_4_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_4_V_address0), + .ce0(layer2_out_4_V_ce0), + .we0(layer2_out_4_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_4_V_d0), + .q0(layer2_out_4_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_5_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_5_V_address0), + .ce0(layer2_out_5_V_ce0), + .we0(layer2_out_5_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_5_V_d0), + .q0(layer2_out_5_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_6_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_6_V_address0), + .ce0(layer2_out_6_V_ce0), + .we0(layer2_out_6_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_6_V_d0), + .q0(layer2_out_6_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_7_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_7_V_address0), + .ce0(layer2_out_7_V_ce0), + .we0(layer2_out_7_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_7_V_d0), + .q0(layer2_out_7_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_8_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_8_V_address0), + .ce0(layer2_out_8_V_ce0), + .we0(layer2_out_8_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_8_V_d0), + .q0(layer2_out_8_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_9_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_9_V_address0), + .ce0(layer2_out_9_V_ce0), + .we0(layer2_out_9_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_9_V_d0), + .q0(layer2_out_9_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_10_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_10_V_address0), + .ce0(layer2_out_10_V_ce0), + .we0(layer2_out_10_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_10_V_d0), + .q0(layer2_out_10_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_11_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_11_V_address0), + .ce0(layer2_out_11_V_ce0), + .we0(layer2_out_11_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_11_V_d0), + .q0(layer2_out_11_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_12_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_12_V_address0), + .ce0(layer2_out_12_V_ce0), + .we0(layer2_out_12_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_12_V_d0), + .q0(layer2_out_12_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_13_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_13_V_address0), + .ce0(layer2_out_13_V_ce0), + .we0(layer2_out_13_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_13_V_d0), + .q0(layer2_out_13_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_14_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_14_V_address0), + .ce0(layer2_out_14_V_ce0), + .we0(layer2_out_14_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_14_V_d0), + .q0(layer2_out_14_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_15_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_15_V_address0), + .ce0(layer2_out_15_V_ce0), + .we0(layer2_out_15_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_15_V_d0), + .q0(layer2_out_15_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_16_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_16_V_address0), + .ce0(layer2_out_16_V_ce0), + .we0(layer2_out_16_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_16_V_d0), + .q0(layer2_out_16_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_17_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_17_V_address0), + .ce0(layer2_out_17_V_ce0), + .we0(layer2_out_17_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_17_V_d0), + .q0(layer2_out_17_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_18_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_18_V_address0), + .ce0(layer2_out_18_V_ce0), + .we0(layer2_out_18_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_18_V_d0), + .q0(layer2_out_18_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_19_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_19_V_address0), + .ce0(layer2_out_19_V_ce0), + .we0(layer2_out_19_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_19_V_d0), + .q0(layer2_out_19_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_20_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_20_V_address0), + .ce0(layer2_out_20_V_ce0), + .we0(layer2_out_20_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_20_V_d0), + .q0(layer2_out_20_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_21_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_21_V_address0), + .ce0(layer2_out_21_V_ce0), + .we0(layer2_out_21_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_21_V_d0), + .q0(layer2_out_21_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_22_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_22_V_address0), + .ce0(layer2_out_22_V_ce0), + .we0(layer2_out_22_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_22_V_d0), + .q0(layer2_out_22_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_23_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_23_V_address0), + .ce0(layer2_out_23_V_ce0), + .we0(layer2_out_23_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_23_V_d0), + .q0(layer2_out_23_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_24_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_24_V_address0), + .ce0(layer2_out_24_V_ce0), + .we0(layer2_out_24_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_24_V_d0), + .q0(layer2_out_24_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_25_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_25_V_address0), + .ce0(layer2_out_25_V_ce0), + .we0(layer2_out_25_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_25_V_d0), + .q0(layer2_out_25_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_26_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_26_V_address0), + .ce0(layer2_out_26_V_ce0), + .we0(layer2_out_26_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_26_V_d0), + .q0(layer2_out_26_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_27_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_27_V_address0), + .ce0(layer2_out_27_V_ce0), + .we0(layer2_out_27_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_27_V_d0), + .q0(layer2_out_27_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_28_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_28_V_address0), + .ce0(layer2_out_28_V_ce0), + .we0(layer2_out_28_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_28_V_d0), + .q0(layer2_out_28_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_29_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_29_V_address0), + .ce0(layer2_out_29_V_ce0), + .we0(layer2_out_29_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_29_V_d0), + .q0(layer2_out_29_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_30_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_30_V_address0), + .ce0(layer2_out_30_V_ce0), + .we0(layer2_out_30_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_30_V_d0), + .q0(layer2_out_30_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_31_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_31_V_address0), + .ce0(layer2_out_31_V_ce0), + .we0(layer2_out_31_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_31_V_d0), + .q0(layer2_out_31_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_32_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_32_V_address0), + .ce0(layer2_out_32_V_ce0), + .we0(layer2_out_32_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_32_V_d0), + .q0(layer2_out_32_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_33_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_33_V_address0), + .ce0(layer2_out_33_V_ce0), + .we0(layer2_out_33_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_33_V_d0), + .q0(layer2_out_33_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_34_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_34_V_address0), + .ce0(layer2_out_34_V_ce0), + .we0(layer2_out_34_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_34_V_d0), + .q0(layer2_out_34_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_35_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_35_V_address0), + .ce0(layer2_out_35_V_ce0), + .we0(layer2_out_35_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_35_V_d0), + .q0(layer2_out_35_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_36_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_36_V_address0), + .ce0(layer2_out_36_V_ce0), + .we0(layer2_out_36_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_36_V_d0), + .q0(layer2_out_36_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_37_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_37_V_address0), + .ce0(layer2_out_37_V_ce0), + .we0(layer2_out_37_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_37_V_d0), + .q0(layer2_out_37_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_38_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_38_V_address0), + .ce0(layer2_out_38_V_ce0), + .we0(layer2_out_38_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_38_V_d0), + .q0(layer2_out_38_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_39_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_39_V_address0), + .ce0(layer2_out_39_V_ce0), + .we0(layer2_out_39_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_39_V_d0), + .q0(layer2_out_39_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_40_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_40_V_address0), + .ce0(layer2_out_40_V_ce0), + .we0(layer2_out_40_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_40_V_d0), + .q0(layer2_out_40_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_41_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_41_V_address0), + .ce0(layer2_out_41_V_ce0), + .we0(layer2_out_41_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_41_V_d0), + .q0(layer2_out_41_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_42_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_42_V_address0), + .ce0(layer2_out_42_V_ce0), + .we0(layer2_out_42_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_42_V_d0), + .q0(layer2_out_42_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_43_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_43_V_address0), + .ce0(layer2_out_43_V_ce0), + .we0(layer2_out_43_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_43_V_d0), + .q0(layer2_out_43_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_44_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_44_V_address0), + .ce0(layer2_out_44_V_ce0), + .we0(layer2_out_44_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_44_V_d0), + .q0(layer2_out_44_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_45_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_45_V_address0), + .ce0(layer2_out_45_V_ce0), + .we0(layer2_out_45_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_45_V_d0), + .q0(layer2_out_45_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_46_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_46_V_address0), + .ce0(layer2_out_46_V_ce0), + .we0(layer2_out_46_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_46_V_d0), + .q0(layer2_out_46_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_47_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_47_V_address0), + .ce0(layer2_out_47_V_ce0), + .we0(layer2_out_47_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_47_V_d0), + .q0(layer2_out_47_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_48_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_48_V_address0), + .ce0(layer2_out_48_V_ce0), + .we0(layer2_out_48_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_48_V_d0), + .q0(layer2_out_48_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_49_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_49_V_address0), + .ce0(layer2_out_49_V_ce0), + .we0(layer2_out_49_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_49_V_d0), + .q0(layer2_out_49_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_50_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_50_V_address0), + .ce0(layer2_out_50_V_ce0), + .we0(layer2_out_50_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_50_V_d0), + .q0(layer2_out_50_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_51_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_51_V_address0), + .ce0(layer2_out_51_V_ce0), + .we0(layer2_out_51_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_51_V_d0), + .q0(layer2_out_51_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_52_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_52_V_address0), + .ce0(layer2_out_52_V_ce0), + .we0(layer2_out_52_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_52_V_d0), + .q0(layer2_out_52_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_53_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_53_V_address0), + .ce0(layer2_out_53_V_ce0), + .we0(layer2_out_53_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_53_V_d0), + .q0(layer2_out_53_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_54_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_54_V_address0), + .ce0(layer2_out_54_V_ce0), + .we0(layer2_out_54_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_54_V_d0), + .q0(layer2_out_54_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_55_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_55_V_address0), + .ce0(layer2_out_55_V_ce0), + .we0(layer2_out_55_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_55_V_d0), + .q0(layer2_out_55_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_56_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_56_V_address0), + .ce0(layer2_out_56_V_ce0), + .we0(layer2_out_56_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_56_V_d0), + .q0(layer2_out_56_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_57_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_57_V_address0), + .ce0(layer2_out_57_V_ce0), + .we0(layer2_out_57_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_57_V_d0), + .q0(layer2_out_57_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_58_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_58_V_address0), + .ce0(layer2_out_58_V_ce0), + .we0(layer2_out_58_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_58_V_d0), + .q0(layer2_out_58_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_59_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_59_V_address0), + .ce0(layer2_out_59_V_ce0), + .we0(layer2_out_59_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_59_V_d0), + .q0(layer2_out_59_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_60_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_60_V_address0), + .ce0(layer2_out_60_V_ce0), + .we0(layer2_out_60_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_60_V_d0), + .q0(layer2_out_60_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_61_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_61_V_address0), + .ce0(layer2_out_61_V_ce0), + .we0(layer2_out_61_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_61_V_d0), + .q0(layer2_out_61_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_62_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_62_V_address0), + .ce0(layer2_out_62_V_ce0), + .we0(layer2_out_62_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_62_V_d0), + .q0(layer2_out_62_V_q0) +); + +myproject_layer2_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 25 ), + .AddressWidth( 5 )) +layer2_out_63_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_63_V_address0), + .ce0(layer2_out_63_V_ce0), + .we0(layer2_out_63_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_63_V_d0), + .q0(layer2_out_63_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_64_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_64_V_address0), + .ce0(layer2_out_64_V_ce0), + .we0(layer2_out_64_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_64_V_d0), + .q0(layer2_out_64_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_65_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_65_V_address0), + .ce0(layer2_out_65_V_ce0), + .we0(layer2_out_65_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_65_V_d0), + .q0(layer2_out_65_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_66_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_66_V_address0), + .ce0(layer2_out_66_V_ce0), + .we0(layer2_out_66_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_66_V_d0), + .q0(layer2_out_66_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_67_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_67_V_address0), + .ce0(layer2_out_67_V_ce0), + .we0(layer2_out_67_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_67_V_d0), + .q0(layer2_out_67_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_68_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_68_V_address0), + .ce0(layer2_out_68_V_ce0), + .we0(layer2_out_68_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_68_V_d0), + .q0(layer2_out_68_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_69_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_69_V_address0), + .ce0(layer2_out_69_V_ce0), + .we0(layer2_out_69_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_69_V_d0), + .q0(layer2_out_69_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_70_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_70_V_address0), + .ce0(layer2_out_70_V_ce0), + .we0(layer2_out_70_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_70_V_d0), + .q0(layer2_out_70_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_71_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_71_V_address0), + .ce0(layer2_out_71_V_ce0), + .we0(layer2_out_71_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_71_V_d0), + .q0(layer2_out_71_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_72_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_72_V_address0), + .ce0(layer2_out_72_V_ce0), + .we0(layer2_out_72_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_72_V_d0), + .q0(layer2_out_72_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_73_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_73_V_address0), + .ce0(layer2_out_73_V_ce0), + .we0(layer2_out_73_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_73_V_d0), + .q0(layer2_out_73_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_74_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_74_V_address0), + .ce0(layer2_out_74_V_ce0), + .we0(layer2_out_74_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_74_V_d0), + .q0(layer2_out_74_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_75_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_75_V_address0), + .ce0(layer2_out_75_V_ce0), + .we0(layer2_out_75_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_75_V_d0), + .q0(layer2_out_75_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_76_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_76_V_address0), + .ce0(layer2_out_76_V_ce0), + .we0(layer2_out_76_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_76_V_d0), + .q0(layer2_out_76_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_77_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_77_V_address0), + .ce0(layer2_out_77_V_ce0), + .we0(layer2_out_77_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_77_V_d0), + .q0(layer2_out_77_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_78_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_78_V_address0), + .ce0(layer2_out_78_V_ce0), + .we0(layer2_out_78_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_78_V_d0), + .q0(layer2_out_78_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_79_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_79_V_address0), + .ce0(layer2_out_79_V_ce0), + .we0(layer2_out_79_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_79_V_d0), + .q0(layer2_out_79_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_80_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_80_V_address0), + .ce0(layer2_out_80_V_ce0), + .we0(layer2_out_80_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_80_V_d0), + .q0(layer2_out_80_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_81_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_81_V_address0), + .ce0(layer2_out_81_V_ce0), + .we0(layer2_out_81_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_81_V_d0), + .q0(layer2_out_81_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_82_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_82_V_address0), + .ce0(layer2_out_82_V_ce0), + .we0(layer2_out_82_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_82_V_d0), + .q0(layer2_out_82_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_83_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_83_V_address0), + .ce0(layer2_out_83_V_ce0), + .we0(layer2_out_83_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_83_V_d0), + .q0(layer2_out_83_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_84_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_84_V_address0), + .ce0(layer2_out_84_V_ce0), + .we0(layer2_out_84_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_84_V_d0), + .q0(layer2_out_84_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_85_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_85_V_address0), + .ce0(layer2_out_85_V_ce0), + .we0(layer2_out_85_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_85_V_d0), + .q0(layer2_out_85_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_86_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_86_V_address0), + .ce0(layer2_out_86_V_ce0), + .we0(layer2_out_86_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_86_V_d0), + .q0(layer2_out_86_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_87_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_87_V_address0), + .ce0(layer2_out_87_V_ce0), + .we0(layer2_out_87_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_87_V_d0), + .q0(layer2_out_87_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_88_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_88_V_address0), + .ce0(layer2_out_88_V_ce0), + .we0(layer2_out_88_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_88_V_d0), + .q0(layer2_out_88_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_89_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_89_V_address0), + .ce0(layer2_out_89_V_ce0), + .we0(layer2_out_89_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_89_V_d0), + .q0(layer2_out_89_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_90_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_90_V_address0), + .ce0(layer2_out_90_V_ce0), + .we0(layer2_out_90_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_90_V_d0), + .q0(layer2_out_90_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_91_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_91_V_address0), + .ce0(layer2_out_91_V_ce0), + .we0(layer2_out_91_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_91_V_d0), + .q0(layer2_out_91_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_92_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_92_V_address0), + .ce0(layer2_out_92_V_ce0), + .we0(layer2_out_92_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_92_V_d0), + .q0(layer2_out_92_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_93_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_93_V_address0), + .ce0(layer2_out_93_V_ce0), + .we0(layer2_out_93_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_93_V_d0), + .q0(layer2_out_93_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_94_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_94_V_address0), + .ce0(layer2_out_94_V_ce0), + .we0(layer2_out_94_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_94_V_d0), + .q0(layer2_out_94_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_95_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_95_V_address0), + .ce0(layer2_out_95_V_ce0), + .we0(layer2_out_95_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_95_V_d0), + .q0(layer2_out_95_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_96_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_96_V_address0), + .ce0(layer2_out_96_V_ce0), + .we0(layer2_out_96_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_96_V_d0), + .q0(layer2_out_96_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_97_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_97_V_address0), + .ce0(layer2_out_97_V_ce0), + .we0(layer2_out_97_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_97_V_d0), + .q0(layer2_out_97_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_98_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_98_V_address0), + .ce0(layer2_out_98_V_ce0), + .we0(layer2_out_98_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_98_V_d0), + .q0(layer2_out_98_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_99_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_99_V_address0), + .ce0(layer2_out_99_V_ce0), + .we0(layer2_out_99_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_99_V_d0), + .q0(layer2_out_99_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_100_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_100_V_address0), + .ce0(layer2_out_100_V_ce0), + .we0(layer2_out_100_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_100_V_d0), + .q0(layer2_out_100_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_101_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_101_V_address0), + .ce0(layer2_out_101_V_ce0), + .we0(layer2_out_101_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_101_V_d0), + .q0(layer2_out_101_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_102_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_102_V_address0), + .ce0(layer2_out_102_V_ce0), + .we0(layer2_out_102_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_102_V_d0), + .q0(layer2_out_102_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_103_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_103_V_address0), + .ce0(layer2_out_103_V_ce0), + .we0(layer2_out_103_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_103_V_d0), + .q0(layer2_out_103_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_104_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_104_V_address0), + .ce0(layer2_out_104_V_ce0), + .we0(layer2_out_104_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_104_V_d0), + .q0(layer2_out_104_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_105_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_105_V_address0), + .ce0(layer2_out_105_V_ce0), + .we0(layer2_out_105_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_105_V_d0), + .q0(layer2_out_105_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_106_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_106_V_address0), + .ce0(layer2_out_106_V_ce0), + .we0(layer2_out_106_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_106_V_d0), + .q0(layer2_out_106_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_107_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_107_V_address0), + .ce0(layer2_out_107_V_ce0), + .we0(layer2_out_107_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_107_V_d0), + .q0(layer2_out_107_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_108_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_108_V_address0), + .ce0(layer2_out_108_V_ce0), + .we0(layer2_out_108_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_108_V_d0), + .q0(layer2_out_108_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_109_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_109_V_address0), + .ce0(layer2_out_109_V_ce0), + .we0(layer2_out_109_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_109_V_d0), + .q0(layer2_out_109_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_110_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_110_V_address0), + .ce0(layer2_out_110_V_ce0), + .we0(layer2_out_110_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_110_V_d0), + .q0(layer2_out_110_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_111_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_111_V_address0), + .ce0(layer2_out_111_V_ce0), + .we0(layer2_out_111_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_111_V_d0), + .q0(layer2_out_111_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_112_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_112_V_address0), + .ce0(layer2_out_112_V_ce0), + .we0(layer2_out_112_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_112_V_d0), + .q0(layer2_out_112_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_113_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_113_V_address0), + .ce0(layer2_out_113_V_ce0), + .we0(layer2_out_113_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_113_V_d0), + .q0(layer2_out_113_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_114_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_114_V_address0), + .ce0(layer2_out_114_V_ce0), + .we0(layer2_out_114_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_114_V_d0), + .q0(layer2_out_114_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_115_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_115_V_address0), + .ce0(layer2_out_115_V_ce0), + .we0(layer2_out_115_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_115_V_d0), + .q0(layer2_out_115_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_116_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_116_V_address0), + .ce0(layer2_out_116_V_ce0), + .we0(layer2_out_116_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_116_V_d0), + .q0(layer2_out_116_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_117_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_117_V_address0), + .ce0(layer2_out_117_V_ce0), + .we0(layer2_out_117_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_117_V_d0), + .q0(layer2_out_117_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_118_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_118_V_address0), + .ce0(layer2_out_118_V_ce0), + .we0(layer2_out_118_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_118_V_d0), + .q0(layer2_out_118_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_119_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_119_V_address0), + .ce0(layer2_out_119_V_ce0), + .we0(layer2_out_119_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_119_V_d0), + .q0(layer2_out_119_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_120_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_120_V_address0), + .ce0(layer2_out_120_V_ce0), + .we0(layer2_out_120_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_120_V_d0), + .q0(layer2_out_120_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_121_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_121_V_address0), + .ce0(layer2_out_121_V_ce0), + .we0(layer2_out_121_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_121_V_d0), + .q0(layer2_out_121_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_122_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_122_V_address0), + .ce0(layer2_out_122_V_ce0), + .we0(layer2_out_122_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_122_V_d0), + .q0(layer2_out_122_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_123_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_123_V_address0), + .ce0(layer2_out_123_V_ce0), + .we0(layer2_out_123_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_123_V_d0), + .q0(layer2_out_123_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_124_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_124_V_address0), + .ce0(layer2_out_124_V_ce0), + .we0(layer2_out_124_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_124_V_d0), + .q0(layer2_out_124_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_125_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_125_V_address0), + .ce0(layer2_out_125_V_ce0), + .we0(layer2_out_125_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_125_V_d0), + .q0(layer2_out_125_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_126_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_126_V_address0), + .ce0(layer2_out_126_V_ce0), + .we0(layer2_out_126_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_126_V_d0), + .q0(layer2_out_126_V_q0) +); + +myproject_layer2_out_64_V #( + .DataWidth( 8 ), + .AddressRange( 24 ), + .AddressWidth( 5 )) +layer2_out_127_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer2_out_127_V_address0), + .ce0(layer2_out_127_V_ce0), + .we0(layer2_out_127_V_we0), + .d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_127_V_d0), + .q0(layer2_out_127_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_0_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_0_V_address0), + .ce0(layer4_out_0_V_ce0), + .we0(layer4_out_0_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_0_V_d0), + .q0(layer4_out_0_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_1_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_1_V_address0), + .ce0(layer4_out_1_V_ce0), + .we0(layer4_out_1_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_1_V_d0), + .q0(layer4_out_1_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_2_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_2_V_address0), + .ce0(layer4_out_2_V_ce0), + .we0(layer4_out_2_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_2_V_d0), + .q0(layer4_out_2_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_3_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_3_V_address0), + .ce0(layer4_out_3_V_ce0), + .we0(layer4_out_3_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_3_V_d0), + .q0(layer4_out_3_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_4_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_4_V_address0), + .ce0(layer4_out_4_V_ce0), + .we0(layer4_out_4_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_4_V_d0), + .q0(layer4_out_4_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_5_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_5_V_address0), + .ce0(layer4_out_5_V_ce0), + .we0(layer4_out_5_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_5_V_d0), + .q0(layer4_out_5_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_6_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_6_V_address0), + .ce0(layer4_out_6_V_ce0), + .we0(layer4_out_6_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_6_V_d0), + .q0(layer4_out_6_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_7_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_7_V_address0), + .ce0(layer4_out_7_V_ce0), + .we0(layer4_out_7_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_7_V_d0), + .q0(layer4_out_7_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_8_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_8_V_address0), + .ce0(layer4_out_8_V_ce0), + .we0(layer4_out_8_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_8_V_d0), + .q0(layer4_out_8_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_9_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_9_V_address0), + .ce0(layer4_out_9_V_ce0), + .we0(layer4_out_9_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_9_V_d0), + .q0(layer4_out_9_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_10_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_10_V_address0), + .ce0(layer4_out_10_V_ce0), + .we0(layer4_out_10_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_10_V_d0), + .q0(layer4_out_10_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_11_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_11_V_address0), + .ce0(layer4_out_11_V_ce0), + .we0(layer4_out_11_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_11_V_d0), + .q0(layer4_out_11_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_12_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_12_V_address0), + .ce0(layer4_out_12_V_ce0), + .we0(layer4_out_12_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_12_V_d0), + .q0(layer4_out_12_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_13_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_13_V_address0), + .ce0(layer4_out_13_V_ce0), + .we0(layer4_out_13_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_13_V_d0), + .q0(layer4_out_13_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_14_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_14_V_address0), + .ce0(layer4_out_14_V_ce0), + .we0(layer4_out_14_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_14_V_d0), + .q0(layer4_out_14_V_q0) +); + +myproject_layer4_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +layer4_out_15_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_15_V_address0), + .ce0(layer4_out_15_V_ce0), + .we0(layer4_out_15_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_15_V_d0), + .q0(layer4_out_15_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_16_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_16_V_address0), + .ce0(layer4_out_16_V_ce0), + .we0(layer4_out_16_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_16_V_d0), + .q0(layer4_out_16_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_17_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_17_V_address0), + .ce0(layer4_out_17_V_ce0), + .we0(layer4_out_17_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_17_V_d0), + .q0(layer4_out_17_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_18_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_18_V_address0), + .ce0(layer4_out_18_V_ce0), + .we0(layer4_out_18_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_18_V_d0), + .q0(layer4_out_18_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_19_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_19_V_address0), + .ce0(layer4_out_19_V_ce0), + .we0(layer4_out_19_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_19_V_d0), + .q0(layer4_out_19_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_20_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_20_V_address0), + .ce0(layer4_out_20_V_ce0), + .we0(layer4_out_20_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_20_V_d0), + .q0(layer4_out_20_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_21_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_21_V_address0), + .ce0(layer4_out_21_V_ce0), + .we0(layer4_out_21_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_21_V_d0), + .q0(layer4_out_21_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_22_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_22_V_address0), + .ce0(layer4_out_22_V_ce0), + .we0(layer4_out_22_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_22_V_d0), + .q0(layer4_out_22_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_23_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_23_V_address0), + .ce0(layer4_out_23_V_ce0), + .we0(layer4_out_23_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_23_V_d0), + .q0(layer4_out_23_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_24_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_24_V_address0), + .ce0(layer4_out_24_V_ce0), + .we0(layer4_out_24_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_24_V_d0), + .q0(layer4_out_24_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_25_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_25_V_address0), + .ce0(layer4_out_25_V_ce0), + .we0(layer4_out_25_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_25_V_d0), + .q0(layer4_out_25_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_26_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_26_V_address0), + .ce0(layer4_out_26_V_ce0), + .we0(layer4_out_26_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_26_V_d0), + .q0(layer4_out_26_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_27_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_27_V_address0), + .ce0(layer4_out_27_V_ce0), + .we0(layer4_out_27_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_27_V_d0), + .q0(layer4_out_27_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_28_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_28_V_address0), + .ce0(layer4_out_28_V_ce0), + .we0(layer4_out_28_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_28_V_d0), + .q0(layer4_out_28_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_29_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_29_V_address0), + .ce0(layer4_out_29_V_ce0), + .we0(layer4_out_29_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_29_V_d0), + .q0(layer4_out_29_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_30_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_30_V_address0), + .ce0(layer4_out_30_V_ce0), + .we0(layer4_out_30_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_30_V_d0), + .q0(layer4_out_30_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_31_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_31_V_address0), + .ce0(layer4_out_31_V_ce0), + .we0(layer4_out_31_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_31_V_d0), + .q0(layer4_out_31_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_32_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_32_V_address0), + .ce0(layer4_out_32_V_ce0), + .we0(layer4_out_32_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_32_V_d0), + .q0(layer4_out_32_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_33_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_33_V_address0), + .ce0(layer4_out_33_V_ce0), + .we0(layer4_out_33_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_33_V_d0), + .q0(layer4_out_33_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_34_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_34_V_address0), + .ce0(layer4_out_34_V_ce0), + .we0(layer4_out_34_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_34_V_d0), + .q0(layer4_out_34_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_35_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_35_V_address0), + .ce0(layer4_out_35_V_ce0), + .we0(layer4_out_35_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_35_V_d0), + .q0(layer4_out_35_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_36_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_36_V_address0), + .ce0(layer4_out_36_V_ce0), + .we0(layer4_out_36_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_36_V_d0), + .q0(layer4_out_36_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_37_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_37_V_address0), + .ce0(layer4_out_37_V_ce0), + .we0(layer4_out_37_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_37_V_d0), + .q0(layer4_out_37_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_38_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_38_V_address0), + .ce0(layer4_out_38_V_ce0), + .we0(layer4_out_38_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_38_V_d0), + .q0(layer4_out_38_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_39_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_39_V_address0), + .ce0(layer4_out_39_V_ce0), + .we0(layer4_out_39_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_39_V_d0), + .q0(layer4_out_39_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_40_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_40_V_address0), + .ce0(layer4_out_40_V_ce0), + .we0(layer4_out_40_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_40_V_d0), + .q0(layer4_out_40_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_41_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_41_V_address0), + .ce0(layer4_out_41_V_ce0), + .we0(layer4_out_41_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_41_V_d0), + .q0(layer4_out_41_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_42_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_42_V_address0), + .ce0(layer4_out_42_V_ce0), + .we0(layer4_out_42_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_42_V_d0), + .q0(layer4_out_42_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_43_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_43_V_address0), + .ce0(layer4_out_43_V_ce0), + .we0(layer4_out_43_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_43_V_d0), + .q0(layer4_out_43_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_44_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_44_V_address0), + .ce0(layer4_out_44_V_ce0), + .we0(layer4_out_44_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_44_V_d0), + .q0(layer4_out_44_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_45_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_45_V_address0), + .ce0(layer4_out_45_V_ce0), + .we0(layer4_out_45_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_45_V_d0), + .q0(layer4_out_45_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_46_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_46_V_address0), + .ce0(layer4_out_46_V_ce0), + .we0(layer4_out_46_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_46_V_d0), + .q0(layer4_out_46_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_47_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_47_V_address0), + .ce0(layer4_out_47_V_ce0), + .we0(layer4_out_47_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_47_V_d0), + .q0(layer4_out_47_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_48_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_48_V_address0), + .ce0(layer4_out_48_V_ce0), + .we0(layer4_out_48_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_48_V_d0), + .q0(layer4_out_48_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_49_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_49_V_address0), + .ce0(layer4_out_49_V_ce0), + .we0(layer4_out_49_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_49_V_d0), + .q0(layer4_out_49_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_50_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_50_V_address0), + .ce0(layer4_out_50_V_ce0), + .we0(layer4_out_50_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_50_V_d0), + .q0(layer4_out_50_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_51_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_51_V_address0), + .ce0(layer4_out_51_V_ce0), + .we0(layer4_out_51_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_51_V_d0), + .q0(layer4_out_51_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_52_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_52_V_address0), + .ce0(layer4_out_52_V_ce0), + .we0(layer4_out_52_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_52_V_d0), + .q0(layer4_out_52_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_53_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_53_V_address0), + .ce0(layer4_out_53_V_ce0), + .we0(layer4_out_53_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_53_V_d0), + .q0(layer4_out_53_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_54_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_54_V_address0), + .ce0(layer4_out_54_V_ce0), + .we0(layer4_out_54_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_54_V_d0), + .q0(layer4_out_54_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_55_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_55_V_address0), + .ce0(layer4_out_55_V_ce0), + .we0(layer4_out_55_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_55_V_d0), + .q0(layer4_out_55_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_56_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_56_V_address0), + .ce0(layer4_out_56_V_ce0), + .we0(layer4_out_56_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_56_V_d0), + .q0(layer4_out_56_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_57_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_57_V_address0), + .ce0(layer4_out_57_V_ce0), + .we0(layer4_out_57_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_57_V_d0), + .q0(layer4_out_57_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_58_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_58_V_address0), + .ce0(layer4_out_58_V_ce0), + .we0(layer4_out_58_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_58_V_d0), + .q0(layer4_out_58_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_59_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_59_V_address0), + .ce0(layer4_out_59_V_ce0), + .we0(layer4_out_59_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_59_V_d0), + .q0(layer4_out_59_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_60_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_60_V_address0), + .ce0(layer4_out_60_V_ce0), + .we0(layer4_out_60_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_60_V_d0), + .q0(layer4_out_60_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_61_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_61_V_address0), + .ce0(layer4_out_61_V_ce0), + .we0(layer4_out_61_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_61_V_d0), + .q0(layer4_out_61_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_62_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_62_V_address0), + .ce0(layer4_out_62_V_ce0), + .we0(layer4_out_62_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_62_V_d0), + .q0(layer4_out_62_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_63_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_63_V_address0), + .ce0(layer4_out_63_V_ce0), + .we0(layer4_out_63_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_63_V_d0), + .q0(layer4_out_63_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_64_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_64_V_address0), + .ce0(layer4_out_64_V_ce0), + .we0(layer4_out_64_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_64_V_d0), + .q0(layer4_out_64_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_65_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_65_V_address0), + .ce0(layer4_out_65_V_ce0), + .we0(layer4_out_65_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_65_V_d0), + .q0(layer4_out_65_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_66_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_66_V_address0), + .ce0(layer4_out_66_V_ce0), + .we0(layer4_out_66_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_66_V_d0), + .q0(layer4_out_66_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_67_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_67_V_address0), + .ce0(layer4_out_67_V_ce0), + .we0(layer4_out_67_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_67_V_d0), + .q0(layer4_out_67_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_68_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_68_V_address0), + .ce0(layer4_out_68_V_ce0), + .we0(layer4_out_68_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_68_V_d0), + .q0(layer4_out_68_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_69_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_69_V_address0), + .ce0(layer4_out_69_V_ce0), + .we0(layer4_out_69_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_69_V_d0), + .q0(layer4_out_69_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_70_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_70_V_address0), + .ce0(layer4_out_70_V_ce0), + .we0(layer4_out_70_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_70_V_d0), + .q0(layer4_out_70_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_71_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_71_V_address0), + .ce0(layer4_out_71_V_ce0), + .we0(layer4_out_71_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_71_V_d0), + .q0(layer4_out_71_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_72_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_72_V_address0), + .ce0(layer4_out_72_V_ce0), + .we0(layer4_out_72_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_72_V_d0), + .q0(layer4_out_72_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_73_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_73_V_address0), + .ce0(layer4_out_73_V_ce0), + .we0(layer4_out_73_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_73_V_d0), + .q0(layer4_out_73_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_74_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_74_V_address0), + .ce0(layer4_out_74_V_ce0), + .we0(layer4_out_74_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_74_V_d0), + .q0(layer4_out_74_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_75_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_75_V_address0), + .ce0(layer4_out_75_V_ce0), + .we0(layer4_out_75_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_75_V_d0), + .q0(layer4_out_75_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_76_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_76_V_address0), + .ce0(layer4_out_76_V_ce0), + .we0(layer4_out_76_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_76_V_d0), + .q0(layer4_out_76_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_77_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_77_V_address0), + .ce0(layer4_out_77_V_ce0), + .we0(layer4_out_77_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_77_V_d0), + .q0(layer4_out_77_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_78_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_78_V_address0), + .ce0(layer4_out_78_V_ce0), + .we0(layer4_out_78_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_78_V_d0), + .q0(layer4_out_78_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_79_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_79_V_address0), + .ce0(layer4_out_79_V_ce0), + .we0(layer4_out_79_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_79_V_d0), + .q0(layer4_out_79_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_80_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_80_V_address0), + .ce0(layer4_out_80_V_ce0), + .we0(layer4_out_80_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_80_V_d0), + .q0(layer4_out_80_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_81_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_81_V_address0), + .ce0(layer4_out_81_V_ce0), + .we0(layer4_out_81_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_81_V_d0), + .q0(layer4_out_81_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_82_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_82_V_address0), + .ce0(layer4_out_82_V_ce0), + .we0(layer4_out_82_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_82_V_d0), + .q0(layer4_out_82_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_83_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_83_V_address0), + .ce0(layer4_out_83_V_ce0), + .we0(layer4_out_83_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_83_V_d0), + .q0(layer4_out_83_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_84_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_84_V_address0), + .ce0(layer4_out_84_V_ce0), + .we0(layer4_out_84_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_84_V_d0), + .q0(layer4_out_84_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_85_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_85_V_address0), + .ce0(layer4_out_85_V_ce0), + .we0(layer4_out_85_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_85_V_d0), + .q0(layer4_out_85_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_86_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_86_V_address0), + .ce0(layer4_out_86_V_ce0), + .we0(layer4_out_86_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_86_V_d0), + .q0(layer4_out_86_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_87_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_87_V_address0), + .ce0(layer4_out_87_V_ce0), + .we0(layer4_out_87_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_87_V_d0), + .q0(layer4_out_87_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_88_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_88_V_address0), + .ce0(layer4_out_88_V_ce0), + .we0(layer4_out_88_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_88_V_d0), + .q0(layer4_out_88_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_89_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_89_V_address0), + .ce0(layer4_out_89_V_ce0), + .we0(layer4_out_89_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_89_V_d0), + .q0(layer4_out_89_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_90_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_90_V_address0), + .ce0(layer4_out_90_V_ce0), + .we0(layer4_out_90_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_90_V_d0), + .q0(layer4_out_90_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_91_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_91_V_address0), + .ce0(layer4_out_91_V_ce0), + .we0(layer4_out_91_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_91_V_d0), + .q0(layer4_out_91_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_92_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_92_V_address0), + .ce0(layer4_out_92_V_ce0), + .we0(layer4_out_92_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_92_V_d0), + .q0(layer4_out_92_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_93_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_93_V_address0), + .ce0(layer4_out_93_V_ce0), + .we0(layer4_out_93_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_93_V_d0), + .q0(layer4_out_93_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_94_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_94_V_address0), + .ce0(layer4_out_94_V_ce0), + .we0(layer4_out_94_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_94_V_d0), + .q0(layer4_out_94_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_95_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_95_V_address0), + .ce0(layer4_out_95_V_ce0), + .we0(layer4_out_95_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_95_V_d0), + .q0(layer4_out_95_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_96_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_96_V_address0), + .ce0(layer4_out_96_V_ce0), + .we0(layer4_out_96_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_96_V_d0), + .q0(layer4_out_96_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_97_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_97_V_address0), + .ce0(layer4_out_97_V_ce0), + .we0(layer4_out_97_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_97_V_d0), + .q0(layer4_out_97_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_98_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_98_V_address0), + .ce0(layer4_out_98_V_ce0), + .we0(layer4_out_98_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_98_V_d0), + .q0(layer4_out_98_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_99_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_99_V_address0), + .ce0(layer4_out_99_V_ce0), + .we0(layer4_out_99_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_99_V_d0), + .q0(layer4_out_99_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_100_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_100_V_address0), + .ce0(layer4_out_100_V_ce0), + .we0(layer4_out_100_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_100_V_d0), + .q0(layer4_out_100_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_101_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_101_V_address0), + .ce0(layer4_out_101_V_ce0), + .we0(layer4_out_101_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_101_V_d0), + .q0(layer4_out_101_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_102_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_102_V_address0), + .ce0(layer4_out_102_V_ce0), + .we0(layer4_out_102_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_102_V_d0), + .q0(layer4_out_102_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_103_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_103_V_address0), + .ce0(layer4_out_103_V_ce0), + .we0(layer4_out_103_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_103_V_d0), + .q0(layer4_out_103_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_104_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_104_V_address0), + .ce0(layer4_out_104_V_ce0), + .we0(layer4_out_104_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_104_V_d0), + .q0(layer4_out_104_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_105_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_105_V_address0), + .ce0(layer4_out_105_V_ce0), + .we0(layer4_out_105_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_105_V_d0), + .q0(layer4_out_105_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_106_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_106_V_address0), + .ce0(layer4_out_106_V_ce0), + .we0(layer4_out_106_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_106_V_d0), + .q0(layer4_out_106_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_107_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_107_V_address0), + .ce0(layer4_out_107_V_ce0), + .we0(layer4_out_107_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_107_V_d0), + .q0(layer4_out_107_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_108_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_108_V_address0), + .ce0(layer4_out_108_V_ce0), + .we0(layer4_out_108_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_108_V_d0), + .q0(layer4_out_108_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_109_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_109_V_address0), + .ce0(layer4_out_109_V_ce0), + .we0(layer4_out_109_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_109_V_d0), + .q0(layer4_out_109_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_110_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_110_V_address0), + .ce0(layer4_out_110_V_ce0), + .we0(layer4_out_110_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_110_V_d0), + .q0(layer4_out_110_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_111_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_111_V_address0), + .ce0(layer4_out_111_V_ce0), + .we0(layer4_out_111_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_111_V_d0), + .q0(layer4_out_111_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_112_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_112_V_address0), + .ce0(layer4_out_112_V_ce0), + .we0(layer4_out_112_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_112_V_d0), + .q0(layer4_out_112_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_113_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_113_V_address0), + .ce0(layer4_out_113_V_ce0), + .we0(layer4_out_113_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_113_V_d0), + .q0(layer4_out_113_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_114_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_114_V_address0), + .ce0(layer4_out_114_V_ce0), + .we0(layer4_out_114_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_114_V_d0), + .q0(layer4_out_114_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_115_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_115_V_address0), + .ce0(layer4_out_115_V_ce0), + .we0(layer4_out_115_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_115_V_d0), + .q0(layer4_out_115_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_116_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_116_V_address0), + .ce0(layer4_out_116_V_ce0), + .we0(layer4_out_116_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_116_V_d0), + .q0(layer4_out_116_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_117_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_117_V_address0), + .ce0(layer4_out_117_V_ce0), + .we0(layer4_out_117_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_117_V_d0), + .q0(layer4_out_117_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_118_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_118_V_address0), + .ce0(layer4_out_118_V_ce0), + .we0(layer4_out_118_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_118_V_d0), + .q0(layer4_out_118_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_119_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_119_V_address0), + .ce0(layer4_out_119_V_ce0), + .we0(layer4_out_119_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_119_V_d0), + .q0(layer4_out_119_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_120_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_120_V_address0), + .ce0(layer4_out_120_V_ce0), + .we0(layer4_out_120_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_120_V_d0), + .q0(layer4_out_120_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_121_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_121_V_address0), + .ce0(layer4_out_121_V_ce0), + .we0(layer4_out_121_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_121_V_d0), + .q0(layer4_out_121_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_122_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_122_V_address0), + .ce0(layer4_out_122_V_ce0), + .we0(layer4_out_122_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_122_V_d0), + .q0(layer4_out_122_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_123_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_123_V_address0), + .ce0(layer4_out_123_V_ce0), + .we0(layer4_out_123_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_123_V_d0), + .q0(layer4_out_123_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_124_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_124_V_address0), + .ce0(layer4_out_124_V_ce0), + .we0(layer4_out_124_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_124_V_d0), + .q0(layer4_out_124_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_125_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_125_V_address0), + .ce0(layer4_out_125_V_ce0), + .we0(layer4_out_125_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_125_V_d0), + .q0(layer4_out_125_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_126_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_126_V_address0), + .ce0(layer4_out_126_V_ce0), + .we0(layer4_out_126_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_126_V_d0), + .q0(layer4_out_126_V_q0) +); + +myproject_layer4_out_16_V #( + .DataWidth( 8 ), + .AddressRange( 6 ), + .AddressWidth( 3 )) +layer4_out_127_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer4_out_127_V_address0), + .ce0(layer4_out_127_V_ce0), + .we0(layer4_out_127_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_127_V_d0), + .q0(layer4_out_127_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_0_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_0_V_address0), + .ce0(layer5_out_0_V_ce0), + .we0(layer5_out_0_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_0_V_d0), + .q0(layer5_out_0_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_1_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_1_V_address0), + .ce0(layer5_out_1_V_ce0), + .we0(layer5_out_1_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_1_V_d0), + .q0(layer5_out_1_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_2_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_2_V_address0), + .ce0(layer5_out_2_V_ce0), + .we0(layer5_out_2_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_2_V_d0), + .q0(layer5_out_2_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_3_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_3_V_address0), + .ce0(layer5_out_3_V_ce0), + .we0(layer5_out_3_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_3_V_d0), + .q0(layer5_out_3_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_4_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_4_V_address0), + .ce0(layer5_out_4_V_ce0), + .we0(layer5_out_4_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_4_V_d0), + .q0(layer5_out_4_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_5_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_5_V_address0), + .ce0(layer5_out_5_V_ce0), + .we0(layer5_out_5_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_5_V_d0), + .q0(layer5_out_5_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_6_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_6_V_address0), + .ce0(layer5_out_6_V_ce0), + .we0(layer5_out_6_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_6_V_d0), + .q0(layer5_out_6_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_7_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_7_V_address0), + .ce0(layer5_out_7_V_ce0), + .we0(layer5_out_7_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_7_V_d0), + .q0(layer5_out_7_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_8_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_8_V_address0), + .ce0(layer5_out_8_V_ce0), + .we0(layer5_out_8_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_8_V_d0), + .q0(layer5_out_8_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_9_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_9_V_address0), + .ce0(layer5_out_9_V_ce0), + .we0(layer5_out_9_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_9_V_d0), + .q0(layer5_out_9_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_10_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_10_V_address0), + .ce0(layer5_out_10_V_ce0), + .we0(layer5_out_10_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_10_V_d0), + .q0(layer5_out_10_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_11_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_11_V_address0), + .ce0(layer5_out_11_V_ce0), + .we0(layer5_out_11_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_11_V_d0), + .q0(layer5_out_11_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_12_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_12_V_address0), + .ce0(layer5_out_12_V_ce0), + .we0(layer5_out_12_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_12_V_d0), + .q0(layer5_out_12_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_13_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_13_V_address0), + .ce0(layer5_out_13_V_ce0), + .we0(layer5_out_13_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_13_V_d0), + .q0(layer5_out_13_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_14_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_14_V_address0), + .ce0(layer5_out_14_V_ce0), + .we0(layer5_out_14_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_14_V_d0), + .q0(layer5_out_14_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_15_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_15_V_address0), + .ce0(layer5_out_15_V_ce0), + .we0(layer5_out_15_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_15_V_d0), + .q0(layer5_out_15_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_16_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_16_V_address0), + .ce0(layer5_out_16_V_ce0), + .we0(layer5_out_16_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_16_V_d0), + .q0(layer5_out_16_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_17_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_17_V_address0), + .ce0(layer5_out_17_V_ce0), + .we0(layer5_out_17_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_17_V_d0), + .q0(layer5_out_17_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_18_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_18_V_address0), + .ce0(layer5_out_18_V_ce0), + .we0(layer5_out_18_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_18_V_d0), + .q0(layer5_out_18_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_19_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_19_V_address0), + .ce0(layer5_out_19_V_ce0), + .we0(layer5_out_19_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_19_V_d0), + .q0(layer5_out_19_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_20_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_20_V_address0), + .ce0(layer5_out_20_V_ce0), + .we0(layer5_out_20_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_20_V_d0), + .q0(layer5_out_20_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_21_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_21_V_address0), + .ce0(layer5_out_21_V_ce0), + .we0(layer5_out_21_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_21_V_d0), + .q0(layer5_out_21_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_22_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_22_V_address0), + .ce0(layer5_out_22_V_ce0), + .we0(layer5_out_22_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_22_V_d0), + .q0(layer5_out_22_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_23_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_23_V_address0), + .ce0(layer5_out_23_V_ce0), + .we0(layer5_out_23_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_23_V_d0), + .q0(layer5_out_23_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_24_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_24_V_address0), + .ce0(layer5_out_24_V_ce0), + .we0(layer5_out_24_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_24_V_d0), + .q0(layer5_out_24_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_25_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_25_V_address0), + .ce0(layer5_out_25_V_ce0), + .we0(layer5_out_25_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_25_V_d0), + .q0(layer5_out_25_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_26_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_26_V_address0), + .ce0(layer5_out_26_V_ce0), + .we0(layer5_out_26_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_26_V_d0), + .q0(layer5_out_26_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_27_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_27_V_address0), + .ce0(layer5_out_27_V_ce0), + .we0(layer5_out_27_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_27_V_d0), + .q0(layer5_out_27_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_28_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_28_V_address0), + .ce0(layer5_out_28_V_ce0), + .we0(layer5_out_28_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_28_V_d0), + .q0(layer5_out_28_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_29_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_29_V_address0), + .ce0(layer5_out_29_V_ce0), + .we0(layer5_out_29_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_29_V_d0), + .q0(layer5_out_29_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_30_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_30_V_address0), + .ce0(layer5_out_30_V_ce0), + .we0(layer5_out_30_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_30_V_d0), + .q0(layer5_out_30_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_31_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_31_V_address0), + .ce0(layer5_out_31_V_ce0), + .we0(layer5_out_31_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_31_V_d0), + .q0(layer5_out_31_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_32_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_32_V_address0), + .ce0(layer5_out_32_V_ce0), + .we0(layer5_out_32_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_32_V_d0), + .q0(layer5_out_32_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_33_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_33_V_address0), + .ce0(layer5_out_33_V_ce0), + .we0(layer5_out_33_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_33_V_d0), + .q0(layer5_out_33_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_34_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_34_V_address0), + .ce0(layer5_out_34_V_ce0), + .we0(layer5_out_34_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_34_V_d0), + .q0(layer5_out_34_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_35_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_35_V_address0), + .ce0(layer5_out_35_V_ce0), + .we0(layer5_out_35_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_35_V_d0), + .q0(layer5_out_35_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_36_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_36_V_address0), + .ce0(layer5_out_36_V_ce0), + .we0(layer5_out_36_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_36_V_d0), + .q0(layer5_out_36_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_37_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_37_V_address0), + .ce0(layer5_out_37_V_ce0), + .we0(layer5_out_37_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_37_V_d0), + .q0(layer5_out_37_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_38_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_38_V_address0), + .ce0(layer5_out_38_V_ce0), + .we0(layer5_out_38_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_38_V_d0), + .q0(layer5_out_38_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_39_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_39_V_address0), + .ce0(layer5_out_39_V_ce0), + .we0(layer5_out_39_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_39_V_d0), + .q0(layer5_out_39_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_40_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_40_V_address0), + .ce0(layer5_out_40_V_ce0), + .we0(layer5_out_40_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_40_V_d0), + .q0(layer5_out_40_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_41_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_41_V_address0), + .ce0(layer5_out_41_V_ce0), + .we0(layer5_out_41_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_41_V_d0), + .q0(layer5_out_41_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_42_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_42_V_address0), + .ce0(layer5_out_42_V_ce0), + .we0(layer5_out_42_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_42_V_d0), + .q0(layer5_out_42_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_43_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_43_V_address0), + .ce0(layer5_out_43_V_ce0), + .we0(layer5_out_43_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_43_V_d0), + .q0(layer5_out_43_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_44_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_44_V_address0), + .ce0(layer5_out_44_V_ce0), + .we0(layer5_out_44_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_44_V_d0), + .q0(layer5_out_44_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_45_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_45_V_address0), + .ce0(layer5_out_45_V_ce0), + .we0(layer5_out_45_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_45_V_d0), + .q0(layer5_out_45_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_46_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_46_V_address0), + .ce0(layer5_out_46_V_ce0), + .we0(layer5_out_46_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_46_V_d0), + .q0(layer5_out_46_V_q0) +); + +myproject_layer5_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 19 ), + .AddressWidth( 5 )) +layer5_out_47_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_47_V_address0), + .ce0(layer5_out_47_V_ce0), + .we0(layer5_out_47_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_47_V_d0), + .q0(layer5_out_47_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_48_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_48_V_address0), + .ce0(layer5_out_48_V_ce0), + .we0(layer5_out_48_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_48_V_d0), + .q0(layer5_out_48_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_49_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_49_V_address0), + .ce0(layer5_out_49_V_ce0), + .we0(layer5_out_49_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_49_V_d0), + .q0(layer5_out_49_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_50_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_50_V_address0), + .ce0(layer5_out_50_V_ce0), + .we0(layer5_out_50_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_50_V_d0), + .q0(layer5_out_50_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_51_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_51_V_address0), + .ce0(layer5_out_51_V_ce0), + .we0(layer5_out_51_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_51_V_d0), + .q0(layer5_out_51_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_52_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_52_V_address0), + .ce0(layer5_out_52_V_ce0), + .we0(layer5_out_52_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_52_V_d0), + .q0(layer5_out_52_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_53_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_53_V_address0), + .ce0(layer5_out_53_V_ce0), + .we0(layer5_out_53_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_53_V_d0), + .q0(layer5_out_53_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_54_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_54_V_address0), + .ce0(layer5_out_54_V_ce0), + .we0(layer5_out_54_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_54_V_d0), + .q0(layer5_out_54_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_55_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_55_V_address0), + .ce0(layer5_out_55_V_ce0), + .we0(layer5_out_55_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_55_V_d0), + .q0(layer5_out_55_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_56_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_56_V_address0), + .ce0(layer5_out_56_V_ce0), + .we0(layer5_out_56_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_56_V_d0), + .q0(layer5_out_56_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_57_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_57_V_address0), + .ce0(layer5_out_57_V_ce0), + .we0(layer5_out_57_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_57_V_d0), + .q0(layer5_out_57_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_58_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_58_V_address0), + .ce0(layer5_out_58_V_ce0), + .we0(layer5_out_58_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_58_V_d0), + .q0(layer5_out_58_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_59_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_59_V_address0), + .ce0(layer5_out_59_V_ce0), + .we0(layer5_out_59_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_59_V_d0), + .q0(layer5_out_59_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_60_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_60_V_address0), + .ce0(layer5_out_60_V_ce0), + .we0(layer5_out_60_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_60_V_d0), + .q0(layer5_out_60_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_61_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_61_V_address0), + .ce0(layer5_out_61_V_ce0), + .we0(layer5_out_61_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_61_V_d0), + .q0(layer5_out_61_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_62_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_62_V_address0), + .ce0(layer5_out_62_V_ce0), + .we0(layer5_out_62_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_62_V_d0), + .q0(layer5_out_62_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_63_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_63_V_address0), + .ce0(layer5_out_63_V_ce0), + .we0(layer5_out_63_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_63_V_d0), + .q0(layer5_out_63_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_64_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_64_V_address0), + .ce0(layer5_out_64_V_ce0), + .we0(layer5_out_64_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_64_V_d0), + .q0(layer5_out_64_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_65_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_65_V_address0), + .ce0(layer5_out_65_V_ce0), + .we0(layer5_out_65_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_65_V_d0), + .q0(layer5_out_65_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_66_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_66_V_address0), + .ce0(layer5_out_66_V_ce0), + .we0(layer5_out_66_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_66_V_d0), + .q0(layer5_out_66_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_67_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_67_V_address0), + .ce0(layer5_out_67_V_ce0), + .we0(layer5_out_67_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_67_V_d0), + .q0(layer5_out_67_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_68_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_68_V_address0), + .ce0(layer5_out_68_V_ce0), + .we0(layer5_out_68_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_68_V_d0), + .q0(layer5_out_68_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_69_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_69_V_address0), + .ce0(layer5_out_69_V_ce0), + .we0(layer5_out_69_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_69_V_d0), + .q0(layer5_out_69_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_70_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_70_V_address0), + .ce0(layer5_out_70_V_ce0), + .we0(layer5_out_70_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_70_V_d0), + .q0(layer5_out_70_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_71_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_71_V_address0), + .ce0(layer5_out_71_V_ce0), + .we0(layer5_out_71_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_71_V_d0), + .q0(layer5_out_71_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_72_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_72_V_address0), + .ce0(layer5_out_72_V_ce0), + .we0(layer5_out_72_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_72_V_d0), + .q0(layer5_out_72_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_73_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_73_V_address0), + .ce0(layer5_out_73_V_ce0), + .we0(layer5_out_73_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_73_V_d0), + .q0(layer5_out_73_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_74_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_74_V_address0), + .ce0(layer5_out_74_V_ce0), + .we0(layer5_out_74_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_74_V_d0), + .q0(layer5_out_74_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_75_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_75_V_address0), + .ce0(layer5_out_75_V_ce0), + .we0(layer5_out_75_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_75_V_d0), + .q0(layer5_out_75_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_76_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_76_V_address0), + .ce0(layer5_out_76_V_ce0), + .we0(layer5_out_76_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_76_V_d0), + .q0(layer5_out_76_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_77_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_77_V_address0), + .ce0(layer5_out_77_V_ce0), + .we0(layer5_out_77_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_77_V_d0), + .q0(layer5_out_77_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_78_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_78_V_address0), + .ce0(layer5_out_78_V_ce0), + .we0(layer5_out_78_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_78_V_d0), + .q0(layer5_out_78_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_79_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_79_V_address0), + .ce0(layer5_out_79_V_ce0), + .we0(layer5_out_79_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_79_V_d0), + .q0(layer5_out_79_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_80_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_80_V_address0), + .ce0(layer5_out_80_V_ce0), + .we0(layer5_out_80_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_80_V_d0), + .q0(layer5_out_80_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_81_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_81_V_address0), + .ce0(layer5_out_81_V_ce0), + .we0(layer5_out_81_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_81_V_d0), + .q0(layer5_out_81_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_82_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_82_V_address0), + .ce0(layer5_out_82_V_ce0), + .we0(layer5_out_82_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_82_V_d0), + .q0(layer5_out_82_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_83_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_83_V_address0), + .ce0(layer5_out_83_V_ce0), + .we0(layer5_out_83_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_83_V_d0), + .q0(layer5_out_83_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_84_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_84_V_address0), + .ce0(layer5_out_84_V_ce0), + .we0(layer5_out_84_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_84_V_d0), + .q0(layer5_out_84_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_85_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_85_V_address0), + .ce0(layer5_out_85_V_ce0), + .we0(layer5_out_85_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_85_V_d0), + .q0(layer5_out_85_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_86_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_86_V_address0), + .ce0(layer5_out_86_V_ce0), + .we0(layer5_out_86_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_86_V_d0), + .q0(layer5_out_86_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_87_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_87_V_address0), + .ce0(layer5_out_87_V_ce0), + .we0(layer5_out_87_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_87_V_d0), + .q0(layer5_out_87_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_88_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_88_V_address0), + .ce0(layer5_out_88_V_ce0), + .we0(layer5_out_88_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_88_V_d0), + .q0(layer5_out_88_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_89_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_89_V_address0), + .ce0(layer5_out_89_V_ce0), + .we0(layer5_out_89_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_89_V_d0), + .q0(layer5_out_89_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_90_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_90_V_address0), + .ce0(layer5_out_90_V_ce0), + .we0(layer5_out_90_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_90_V_d0), + .q0(layer5_out_90_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_91_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_91_V_address0), + .ce0(layer5_out_91_V_ce0), + .we0(layer5_out_91_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_91_V_d0), + .q0(layer5_out_91_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_92_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_92_V_address0), + .ce0(layer5_out_92_V_ce0), + .we0(layer5_out_92_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_92_V_d0), + .q0(layer5_out_92_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_93_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_93_V_address0), + .ce0(layer5_out_93_V_ce0), + .we0(layer5_out_93_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_93_V_d0), + .q0(layer5_out_93_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_94_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_94_V_address0), + .ce0(layer5_out_94_V_ce0), + .we0(layer5_out_94_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_94_V_d0), + .q0(layer5_out_94_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_95_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_95_V_address0), + .ce0(layer5_out_95_V_ce0), + .we0(layer5_out_95_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_95_V_d0), + .q0(layer5_out_95_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_96_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_96_V_address0), + .ce0(layer5_out_96_V_ce0), + .we0(layer5_out_96_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_96_V_d0), + .q0(layer5_out_96_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_97_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_97_V_address0), + .ce0(layer5_out_97_V_ce0), + .we0(layer5_out_97_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_97_V_d0), + .q0(layer5_out_97_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_98_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_98_V_address0), + .ce0(layer5_out_98_V_ce0), + .we0(layer5_out_98_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_98_V_d0), + .q0(layer5_out_98_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_99_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_99_V_address0), + .ce0(layer5_out_99_V_ce0), + .we0(layer5_out_99_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_99_V_d0), + .q0(layer5_out_99_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_100_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_100_V_address0), + .ce0(layer5_out_100_V_ce0), + .we0(layer5_out_100_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_100_V_d0), + .q0(layer5_out_100_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_101_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_101_V_address0), + .ce0(layer5_out_101_V_ce0), + .we0(layer5_out_101_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_101_V_d0), + .q0(layer5_out_101_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_102_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_102_V_address0), + .ce0(layer5_out_102_V_ce0), + .we0(layer5_out_102_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_102_V_d0), + .q0(layer5_out_102_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_103_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_103_V_address0), + .ce0(layer5_out_103_V_ce0), + .we0(layer5_out_103_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_103_V_d0), + .q0(layer5_out_103_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_104_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_104_V_address0), + .ce0(layer5_out_104_V_ce0), + .we0(layer5_out_104_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_104_V_d0), + .q0(layer5_out_104_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_105_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_105_V_address0), + .ce0(layer5_out_105_V_ce0), + .we0(layer5_out_105_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_105_V_d0), + .q0(layer5_out_105_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_106_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_106_V_address0), + .ce0(layer5_out_106_V_ce0), + .we0(layer5_out_106_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_106_V_d0), + .q0(layer5_out_106_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_107_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_107_V_address0), + .ce0(layer5_out_107_V_ce0), + .we0(layer5_out_107_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_107_V_d0), + .q0(layer5_out_107_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_108_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_108_V_address0), + .ce0(layer5_out_108_V_ce0), + .we0(layer5_out_108_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_108_V_d0), + .q0(layer5_out_108_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_109_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_109_V_address0), + .ce0(layer5_out_109_V_ce0), + .we0(layer5_out_109_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_109_V_d0), + .q0(layer5_out_109_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_110_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_110_V_address0), + .ce0(layer5_out_110_V_ce0), + .we0(layer5_out_110_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_110_V_d0), + .q0(layer5_out_110_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_111_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_111_V_address0), + .ce0(layer5_out_111_V_ce0), + .we0(layer5_out_111_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_111_V_d0), + .q0(layer5_out_111_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_112_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_112_V_address0), + .ce0(layer5_out_112_V_ce0), + .we0(layer5_out_112_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_112_V_d0), + .q0(layer5_out_112_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_113_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_113_V_address0), + .ce0(layer5_out_113_V_ce0), + .we0(layer5_out_113_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_113_V_d0), + .q0(layer5_out_113_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_114_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_114_V_address0), + .ce0(layer5_out_114_V_ce0), + .we0(layer5_out_114_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_114_V_d0), + .q0(layer5_out_114_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_115_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_115_V_address0), + .ce0(layer5_out_115_V_ce0), + .we0(layer5_out_115_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_115_V_d0), + .q0(layer5_out_115_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_116_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_116_V_address0), + .ce0(layer5_out_116_V_ce0), + .we0(layer5_out_116_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_116_V_d0), + .q0(layer5_out_116_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_117_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_117_V_address0), + .ce0(layer5_out_117_V_ce0), + .we0(layer5_out_117_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_117_V_d0), + .q0(layer5_out_117_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_118_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_118_V_address0), + .ce0(layer5_out_118_V_ce0), + .we0(layer5_out_118_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_118_V_d0), + .q0(layer5_out_118_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_119_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_119_V_address0), + .ce0(layer5_out_119_V_ce0), + .we0(layer5_out_119_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_119_V_d0), + .q0(layer5_out_119_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_120_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_120_V_address0), + .ce0(layer5_out_120_V_ce0), + .we0(layer5_out_120_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_120_V_d0), + .q0(layer5_out_120_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_121_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_121_V_address0), + .ce0(layer5_out_121_V_ce0), + .we0(layer5_out_121_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_121_V_d0), + .q0(layer5_out_121_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_122_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_122_V_address0), + .ce0(layer5_out_122_V_ce0), + .we0(layer5_out_122_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_122_V_d0), + .q0(layer5_out_122_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_123_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_123_V_address0), + .ce0(layer5_out_123_V_ce0), + .we0(layer5_out_123_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_123_V_d0), + .q0(layer5_out_123_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_124_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_124_V_address0), + .ce0(layer5_out_124_V_ce0), + .we0(layer5_out_124_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_124_V_d0), + .q0(layer5_out_124_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_125_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_125_V_address0), + .ce0(layer5_out_125_V_ce0), + .we0(layer5_out_125_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_125_V_d0), + .q0(layer5_out_125_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_126_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_126_V_address0), + .ce0(layer5_out_126_V_ce0), + .we0(layer5_out_126_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_126_V_d0), + .q0(layer5_out_126_V_q0) +); + +myproject_layer5_out_48_V #( + .DataWidth( 8 ), + .AddressRange( 18 ), + .AddressWidth( 5 )) +layer5_out_127_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer5_out_127_V_address0), + .ce0(layer5_out_127_V_ce0), + .we0(layer5_out_127_V_we0), + .d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_127_V_d0), + .q0(layer5_out_127_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_0_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_0_V_address0), + .ce0(layer7_out_0_V_ce0), + .we0(layer7_out_0_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_0_V_d0), + .q0(layer7_out_0_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_1_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_1_V_address0), + .ce0(layer7_out_1_V_ce0), + .we0(layer7_out_1_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_1_V_d0), + .q0(layer7_out_1_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_2_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_2_V_address0), + .ce0(layer7_out_2_V_ce0), + .we0(layer7_out_2_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_2_V_d0), + .q0(layer7_out_2_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_3_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_3_V_address0), + .ce0(layer7_out_3_V_ce0), + .we0(layer7_out_3_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_3_V_d0), + .q0(layer7_out_3_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_4_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_4_V_address0), + .ce0(layer7_out_4_V_ce0), + .we0(layer7_out_4_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_4_V_d0), + .q0(layer7_out_4_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_5_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_5_V_address0), + .ce0(layer7_out_5_V_ce0), + .we0(layer7_out_5_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_5_V_d0), + .q0(layer7_out_5_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_6_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_6_V_address0), + .ce0(layer7_out_6_V_ce0), + .we0(layer7_out_6_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_6_V_d0), + .q0(layer7_out_6_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_7_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_7_V_address0), + .ce0(layer7_out_7_V_ce0), + .we0(layer7_out_7_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_7_V_d0), + .q0(layer7_out_7_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_8_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_8_V_address0), + .ce0(layer7_out_8_V_ce0), + .we0(layer7_out_8_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_8_V_d0), + .q0(layer7_out_8_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_9_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_9_V_address0), + .ce0(layer7_out_9_V_ce0), + .we0(layer7_out_9_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_9_V_d0), + .q0(layer7_out_9_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_10_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_10_V_address0), + .ce0(layer7_out_10_V_ce0), + .we0(layer7_out_10_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_10_V_d0), + .q0(layer7_out_10_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_11_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_11_V_address0), + .ce0(layer7_out_11_V_ce0), + .we0(layer7_out_11_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_11_V_d0), + .q0(layer7_out_11_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_12_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_12_V_address0), + .ce0(layer7_out_12_V_ce0), + .we0(layer7_out_12_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_12_V_d0), + .q0(layer7_out_12_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_13_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_13_V_address0), + .ce0(layer7_out_13_V_ce0), + .we0(layer7_out_13_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_13_V_d0), + .q0(layer7_out_13_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_14_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_14_V_address0), + .ce0(layer7_out_14_V_ce0), + .we0(layer7_out_14_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_14_V_d0), + .q0(layer7_out_14_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_15_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_15_V_address0), + .ce0(layer7_out_15_V_ce0), + .we0(layer7_out_15_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_15_V_d0), + .q0(layer7_out_15_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_16_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_16_V_address0), + .ce0(layer7_out_16_V_ce0), + .we0(layer7_out_16_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_16_V_d0), + .q0(layer7_out_16_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_17_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_17_V_address0), + .ce0(layer7_out_17_V_ce0), + .we0(layer7_out_17_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_17_V_d0), + .q0(layer7_out_17_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_18_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_18_V_address0), + .ce0(layer7_out_18_V_ce0), + .we0(layer7_out_18_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_18_V_d0), + .q0(layer7_out_18_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_19_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_19_V_address0), + .ce0(layer7_out_19_V_ce0), + .we0(layer7_out_19_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_19_V_d0), + .q0(layer7_out_19_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_20_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_20_V_address0), + .ce0(layer7_out_20_V_ce0), + .we0(layer7_out_20_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_20_V_d0), + .q0(layer7_out_20_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_21_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_21_V_address0), + .ce0(layer7_out_21_V_ce0), + .we0(layer7_out_21_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_21_V_d0), + .q0(layer7_out_21_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_22_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_22_V_address0), + .ce0(layer7_out_22_V_ce0), + .we0(layer7_out_22_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_22_V_d0), + .q0(layer7_out_22_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_23_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_23_V_address0), + .ce0(layer7_out_23_V_ce0), + .we0(layer7_out_23_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_23_V_d0), + .q0(layer7_out_23_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_24_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_24_V_address0), + .ce0(layer7_out_24_V_ce0), + .we0(layer7_out_24_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_24_V_d0), + .q0(layer7_out_24_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_25_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_25_V_address0), + .ce0(layer7_out_25_V_ce0), + .we0(layer7_out_25_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_25_V_d0), + .q0(layer7_out_25_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_26_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_26_V_address0), + .ce0(layer7_out_26_V_ce0), + .we0(layer7_out_26_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_26_V_d0), + .q0(layer7_out_26_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_27_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_27_V_address0), + .ce0(layer7_out_27_V_ce0), + .we0(layer7_out_27_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_27_V_d0), + .q0(layer7_out_27_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_28_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_28_V_address0), + .ce0(layer7_out_28_V_ce0), + .we0(layer7_out_28_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_28_V_d0), + .q0(layer7_out_28_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_29_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_29_V_address0), + .ce0(layer7_out_29_V_ce0), + .we0(layer7_out_29_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_29_V_d0), + .q0(layer7_out_29_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_30_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_30_V_address0), + .ce0(layer7_out_30_V_ce0), + .we0(layer7_out_30_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_30_V_d0), + .q0(layer7_out_30_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_31_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_31_V_address0), + .ce0(layer7_out_31_V_ce0), + .we0(layer7_out_31_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_31_V_d0), + .q0(layer7_out_31_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_32_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_32_V_address0), + .ce0(layer7_out_32_V_ce0), + .we0(layer7_out_32_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_32_V_d0), + .q0(layer7_out_32_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_33_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_33_V_address0), + .ce0(layer7_out_33_V_ce0), + .we0(layer7_out_33_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_33_V_d0), + .q0(layer7_out_33_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_34_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_34_V_address0), + .ce0(layer7_out_34_V_ce0), + .we0(layer7_out_34_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_34_V_d0), + .q0(layer7_out_34_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_35_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_35_V_address0), + .ce0(layer7_out_35_V_ce0), + .we0(layer7_out_35_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_35_V_d0), + .q0(layer7_out_35_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_36_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_36_V_address0), + .ce0(layer7_out_36_V_ce0), + .we0(layer7_out_36_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_36_V_d0), + .q0(layer7_out_36_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_37_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_37_V_address0), + .ce0(layer7_out_37_V_ce0), + .we0(layer7_out_37_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_37_V_d0), + .q0(layer7_out_37_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_38_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_38_V_address0), + .ce0(layer7_out_38_V_ce0), + .we0(layer7_out_38_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_38_V_d0), + .q0(layer7_out_38_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_39_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_39_V_address0), + .ce0(layer7_out_39_V_ce0), + .we0(layer7_out_39_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_39_V_d0), + .q0(layer7_out_39_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_40_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_40_V_address0), + .ce0(layer7_out_40_V_ce0), + .we0(layer7_out_40_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_40_V_d0), + .q0(layer7_out_40_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_41_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_41_V_address0), + .ce0(layer7_out_41_V_ce0), + .we0(layer7_out_41_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_41_V_d0), + .q0(layer7_out_41_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_42_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_42_V_address0), + .ce0(layer7_out_42_V_ce0), + .we0(layer7_out_42_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_42_V_d0), + .q0(layer7_out_42_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_43_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_43_V_address0), + .ce0(layer7_out_43_V_ce0), + .we0(layer7_out_43_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_43_V_d0), + .q0(layer7_out_43_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_44_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_44_V_address0), + .ce0(layer7_out_44_V_ce0), + .we0(layer7_out_44_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_44_V_d0), + .q0(layer7_out_44_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_45_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_45_V_address0), + .ce0(layer7_out_45_V_ce0), + .we0(layer7_out_45_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_45_V_d0), + .q0(layer7_out_45_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_46_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_46_V_address0), + .ce0(layer7_out_46_V_ce0), + .we0(layer7_out_46_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_46_V_d0), + .q0(layer7_out_46_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_47_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_47_V_address0), + .ce0(layer7_out_47_V_ce0), + .we0(layer7_out_47_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_47_V_d0), + .q0(layer7_out_47_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_48_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_48_V_address0), + .ce0(layer7_out_48_V_ce0), + .we0(layer7_out_48_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_48_V_d0), + .q0(layer7_out_48_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_49_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_49_V_address0), + .ce0(layer7_out_49_V_ce0), + .we0(layer7_out_49_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_49_V_d0), + .q0(layer7_out_49_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_50_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_50_V_address0), + .ce0(layer7_out_50_V_ce0), + .we0(layer7_out_50_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_50_V_d0), + .q0(layer7_out_50_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_51_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_51_V_address0), + .ce0(layer7_out_51_V_ce0), + .we0(layer7_out_51_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_51_V_d0), + .q0(layer7_out_51_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_52_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_52_V_address0), + .ce0(layer7_out_52_V_ce0), + .we0(layer7_out_52_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_52_V_d0), + .q0(layer7_out_52_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_53_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_53_V_address0), + .ce0(layer7_out_53_V_ce0), + .we0(layer7_out_53_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_53_V_d0), + .q0(layer7_out_53_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_54_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_54_V_address0), + .ce0(layer7_out_54_V_ce0), + .we0(layer7_out_54_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_54_V_d0), + .q0(layer7_out_54_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_55_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_55_V_address0), + .ce0(layer7_out_55_V_ce0), + .we0(layer7_out_55_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_55_V_d0), + .q0(layer7_out_55_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_56_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_56_V_address0), + .ce0(layer7_out_56_V_ce0), + .we0(layer7_out_56_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_56_V_d0), + .q0(layer7_out_56_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_57_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_57_V_address0), + .ce0(layer7_out_57_V_ce0), + .we0(layer7_out_57_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_57_V_d0), + .q0(layer7_out_57_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_58_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_58_V_address0), + .ce0(layer7_out_58_V_ce0), + .we0(layer7_out_58_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_58_V_d0), + .q0(layer7_out_58_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_59_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_59_V_address0), + .ce0(layer7_out_59_V_ce0), + .we0(layer7_out_59_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_59_V_d0), + .q0(layer7_out_59_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_60_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_60_V_address0), + .ce0(layer7_out_60_V_ce0), + .we0(layer7_out_60_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_60_V_d0), + .q0(layer7_out_60_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_61_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_61_V_address0), + .ce0(layer7_out_61_V_ce0), + .we0(layer7_out_61_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_61_V_d0), + .q0(layer7_out_61_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_62_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_62_V_address0), + .ce0(layer7_out_62_V_ce0), + .we0(layer7_out_62_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_62_V_d0), + .q0(layer7_out_62_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_63_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_63_V_address0), + .ce0(layer7_out_63_V_ce0), + .we0(layer7_out_63_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_63_V_d0), + .q0(layer7_out_63_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_64_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_64_V_address0), + .ce0(layer7_out_64_V_ce0), + .we0(layer7_out_64_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_64_V_d0), + .q0(layer7_out_64_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_65_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_65_V_address0), + .ce0(layer7_out_65_V_ce0), + .we0(layer7_out_65_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_65_V_d0), + .q0(layer7_out_65_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_66_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_66_V_address0), + .ce0(layer7_out_66_V_ce0), + .we0(layer7_out_66_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_66_V_d0), + .q0(layer7_out_66_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_67_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_67_V_address0), + .ce0(layer7_out_67_V_ce0), + .we0(layer7_out_67_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_67_V_d0), + .q0(layer7_out_67_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_68_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_68_V_address0), + .ce0(layer7_out_68_V_ce0), + .we0(layer7_out_68_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_68_V_d0), + .q0(layer7_out_68_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_69_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_69_V_address0), + .ce0(layer7_out_69_V_ce0), + .we0(layer7_out_69_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_69_V_d0), + .q0(layer7_out_69_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_70_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_70_V_address0), + .ce0(layer7_out_70_V_ce0), + .we0(layer7_out_70_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_70_V_d0), + .q0(layer7_out_70_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_71_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_71_V_address0), + .ce0(layer7_out_71_V_ce0), + .we0(layer7_out_71_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_71_V_d0), + .q0(layer7_out_71_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_72_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_72_V_address0), + .ce0(layer7_out_72_V_ce0), + .we0(layer7_out_72_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_72_V_d0), + .q0(layer7_out_72_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_73_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_73_V_address0), + .ce0(layer7_out_73_V_ce0), + .we0(layer7_out_73_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_73_V_d0), + .q0(layer7_out_73_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_74_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_74_V_address0), + .ce0(layer7_out_74_V_ce0), + .we0(layer7_out_74_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_74_V_d0), + .q0(layer7_out_74_V_q0) +); + +myproject_layer7_out_0_V #( + .DataWidth( 8 ), + .AddressRange( 5 ), + .AddressWidth( 3 )) +layer7_out_75_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_75_V_address0), + .ce0(layer7_out_75_V_ce0), + .we0(layer7_out_75_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_75_V_d0), + .q0(layer7_out_75_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_76_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_76_V_address0), + .ce0(layer7_out_76_V_ce0), + .we0(layer7_out_76_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_76_V_d0), + .q0(layer7_out_76_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_77_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_77_V_address0), + .ce0(layer7_out_77_V_ce0), + .we0(layer7_out_77_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_77_V_d0), + .q0(layer7_out_77_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_78_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_78_V_address0), + .ce0(layer7_out_78_V_ce0), + .we0(layer7_out_78_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_78_V_d0), + .q0(layer7_out_78_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_79_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_79_V_address0), + .ce0(layer7_out_79_V_ce0), + .we0(layer7_out_79_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_79_V_d0), + .q0(layer7_out_79_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_80_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_80_V_address0), + .ce0(layer7_out_80_V_ce0), + .we0(layer7_out_80_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_80_V_d0), + .q0(layer7_out_80_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_81_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_81_V_address0), + .ce0(layer7_out_81_V_ce0), + .we0(layer7_out_81_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_81_V_d0), + .q0(layer7_out_81_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_82_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_82_V_address0), + .ce0(layer7_out_82_V_ce0), + .we0(layer7_out_82_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_82_V_d0), + .q0(layer7_out_82_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_83_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_83_V_address0), + .ce0(layer7_out_83_V_ce0), + .we0(layer7_out_83_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_83_V_d0), + .q0(layer7_out_83_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_84_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_84_V_address0), + .ce0(layer7_out_84_V_ce0), + .we0(layer7_out_84_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_84_V_d0), + .q0(layer7_out_84_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_85_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_85_V_address0), + .ce0(layer7_out_85_V_ce0), + .we0(layer7_out_85_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_85_V_d0), + .q0(layer7_out_85_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_86_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_86_V_address0), + .ce0(layer7_out_86_V_ce0), + .we0(layer7_out_86_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_86_V_d0), + .q0(layer7_out_86_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_87_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_87_V_address0), + .ce0(layer7_out_87_V_ce0), + .we0(layer7_out_87_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_87_V_d0), + .q0(layer7_out_87_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_88_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_88_V_address0), + .ce0(layer7_out_88_V_ce0), + .we0(layer7_out_88_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_88_V_d0), + .q0(layer7_out_88_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_89_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_89_V_address0), + .ce0(layer7_out_89_V_ce0), + .we0(layer7_out_89_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_89_V_d0), + .q0(layer7_out_89_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_90_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_90_V_address0), + .ce0(layer7_out_90_V_ce0), + .we0(layer7_out_90_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_90_V_d0), + .q0(layer7_out_90_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_91_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_91_V_address0), + .ce0(layer7_out_91_V_ce0), + .we0(layer7_out_91_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_91_V_d0), + .q0(layer7_out_91_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_92_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_92_V_address0), + .ce0(layer7_out_92_V_ce0), + .we0(layer7_out_92_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_92_V_d0), + .q0(layer7_out_92_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_93_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_93_V_address0), + .ce0(layer7_out_93_V_ce0), + .we0(layer7_out_93_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_93_V_d0), + .q0(layer7_out_93_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_94_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_94_V_address0), + .ce0(layer7_out_94_V_ce0), + .we0(layer7_out_94_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_94_V_d0), + .q0(layer7_out_94_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_95_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_95_V_address0), + .ce0(layer7_out_95_V_ce0), + .we0(layer7_out_95_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_95_V_d0), + .q0(layer7_out_95_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_96_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_96_V_address0), + .ce0(layer7_out_96_V_ce0), + .we0(layer7_out_96_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_96_V_d0), + .q0(layer7_out_96_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_97_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_97_V_address0), + .ce0(layer7_out_97_V_ce0), + .we0(layer7_out_97_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_97_V_d0), + .q0(layer7_out_97_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_98_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_98_V_address0), + .ce0(layer7_out_98_V_ce0), + .we0(layer7_out_98_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_98_V_d0), + .q0(layer7_out_98_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_99_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_99_V_address0), + .ce0(layer7_out_99_V_ce0), + .we0(layer7_out_99_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_99_V_d0), + .q0(layer7_out_99_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_100_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_100_V_address0), + .ce0(layer7_out_100_V_ce0), + .we0(layer7_out_100_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_100_V_d0), + .q0(layer7_out_100_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_101_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_101_V_address0), + .ce0(layer7_out_101_V_ce0), + .we0(layer7_out_101_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_101_V_d0), + .q0(layer7_out_101_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_102_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_102_V_address0), + .ce0(layer7_out_102_V_ce0), + .we0(layer7_out_102_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_102_V_d0), + .q0(layer7_out_102_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_103_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_103_V_address0), + .ce0(layer7_out_103_V_ce0), + .we0(layer7_out_103_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_103_V_d0), + .q0(layer7_out_103_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_104_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_104_V_address0), + .ce0(layer7_out_104_V_ce0), + .we0(layer7_out_104_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_104_V_d0), + .q0(layer7_out_104_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_105_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_105_V_address0), + .ce0(layer7_out_105_V_ce0), + .we0(layer7_out_105_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_105_V_d0), + .q0(layer7_out_105_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_106_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_106_V_address0), + .ce0(layer7_out_106_V_ce0), + .we0(layer7_out_106_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_106_V_d0), + .q0(layer7_out_106_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_107_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_107_V_address0), + .ce0(layer7_out_107_V_ce0), + .we0(layer7_out_107_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_107_V_d0), + .q0(layer7_out_107_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_108_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_108_V_address0), + .ce0(layer7_out_108_V_ce0), + .we0(layer7_out_108_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_108_V_d0), + .q0(layer7_out_108_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_109_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_109_V_address0), + .ce0(layer7_out_109_V_ce0), + .we0(layer7_out_109_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_109_V_d0), + .q0(layer7_out_109_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_110_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_110_V_address0), + .ce0(layer7_out_110_V_ce0), + .we0(layer7_out_110_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_110_V_d0), + .q0(layer7_out_110_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_111_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_111_V_address0), + .ce0(layer7_out_111_V_ce0), + .we0(layer7_out_111_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_111_V_d0), + .q0(layer7_out_111_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_112_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_112_V_address0), + .ce0(layer7_out_112_V_ce0), + .we0(layer7_out_112_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_112_V_d0), + .q0(layer7_out_112_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_113_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_113_V_address0), + .ce0(layer7_out_113_V_ce0), + .we0(layer7_out_113_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_113_V_d0), + .q0(layer7_out_113_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_114_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_114_V_address0), + .ce0(layer7_out_114_V_ce0), + .we0(layer7_out_114_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_114_V_d0), + .q0(layer7_out_114_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_115_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_115_V_address0), + .ce0(layer7_out_115_V_ce0), + .we0(layer7_out_115_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_115_V_d0), + .q0(layer7_out_115_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_116_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_116_V_address0), + .ce0(layer7_out_116_V_ce0), + .we0(layer7_out_116_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_116_V_d0), + .q0(layer7_out_116_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_117_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_117_V_address0), + .ce0(layer7_out_117_V_ce0), + .we0(layer7_out_117_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_117_V_d0), + .q0(layer7_out_117_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_118_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_118_V_address0), + .ce0(layer7_out_118_V_ce0), + .we0(layer7_out_118_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_118_V_d0), + .q0(layer7_out_118_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_119_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_119_V_address0), + .ce0(layer7_out_119_V_ce0), + .we0(layer7_out_119_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_119_V_d0), + .q0(layer7_out_119_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_120_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_120_V_address0), + .ce0(layer7_out_120_V_ce0), + .we0(layer7_out_120_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_120_V_d0), + .q0(layer7_out_120_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_121_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_121_V_address0), + .ce0(layer7_out_121_V_ce0), + .we0(layer7_out_121_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_121_V_d0), + .q0(layer7_out_121_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_122_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_122_V_address0), + .ce0(layer7_out_122_V_ce0), + .we0(layer7_out_122_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_122_V_d0), + .q0(layer7_out_122_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_123_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_123_V_address0), + .ce0(layer7_out_123_V_ce0), + .we0(layer7_out_123_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_123_V_d0), + .q0(layer7_out_123_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_124_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_124_V_address0), + .ce0(layer7_out_124_V_ce0), + .we0(layer7_out_124_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_124_V_d0), + .q0(layer7_out_124_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_125_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_125_V_address0), + .ce0(layer7_out_125_V_ce0), + .we0(layer7_out_125_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_125_V_d0), + .q0(layer7_out_125_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_126_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_126_V_address0), + .ce0(layer7_out_126_V_ce0), + .we0(layer7_out_126_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_126_V_d0), + .q0(layer7_out_126_V_q0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +layer7_out_127_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(layer7_out_127_V_address0), + .ce0(layer7_out_127_V_ce0), + .we0(layer7_out_127_V_we0), + .d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_127_V_d0), + .q0(layer7_out_127_V_q0) +); + +conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0 grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_start), + .ap_done(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_done), + .ap_idle(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_idle), + .ap_ready(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_ready), + .data_0_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_0_V_address0), + .data_0_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_0_V_ce0), + .data_0_V_q0(layer4_out_0_V_q0), + .data_1_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_1_V_address0), + .data_1_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_1_V_ce0), + .data_1_V_q0(layer4_out_1_V_q0), + .data_2_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_2_V_address0), + .data_2_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_2_V_ce0), + .data_2_V_q0(layer4_out_2_V_q0), + .data_3_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_3_V_address0), + .data_3_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_3_V_ce0), + .data_3_V_q0(layer4_out_3_V_q0), + .data_4_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_4_V_address0), + .data_4_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_4_V_ce0), + .data_4_V_q0(layer4_out_4_V_q0), + .data_5_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_5_V_address0), + .data_5_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_5_V_ce0), + .data_5_V_q0(layer4_out_5_V_q0), + .data_6_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_6_V_address0), + .data_6_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_6_V_ce0), + .data_6_V_q0(layer4_out_6_V_q0), + .data_7_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_7_V_address0), + .data_7_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_7_V_ce0), + .data_7_V_q0(layer4_out_7_V_q0), + .data_8_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_8_V_address0), + .data_8_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_8_V_ce0), + .data_8_V_q0(layer4_out_8_V_q0), + .data_9_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_9_V_address0), + .data_9_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_9_V_ce0), + .data_9_V_q0(layer4_out_9_V_q0), + .data_10_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_10_V_address0), + .data_10_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_10_V_ce0), + .data_10_V_q0(layer4_out_10_V_q0), + .data_11_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_11_V_address0), + .data_11_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_11_V_ce0), + .data_11_V_q0(layer4_out_11_V_q0), + .data_12_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_12_V_address0), + .data_12_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_12_V_ce0), + .data_12_V_q0(layer4_out_12_V_q0), + .data_13_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_13_V_address0), + .data_13_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_13_V_ce0), + .data_13_V_q0(layer4_out_13_V_q0), + .data_14_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_14_V_address0), + .data_14_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_14_V_ce0), + .data_14_V_q0(layer4_out_14_V_q0), + .data_15_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_15_V_address0), + .data_15_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_15_V_ce0), + .data_15_V_q0(layer4_out_15_V_q0), + .data_16_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_16_V_address0), + .data_16_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_16_V_ce0), + .data_16_V_q0(layer4_out_16_V_q0), + .data_17_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_17_V_address0), + .data_17_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_17_V_ce0), + .data_17_V_q0(layer4_out_17_V_q0), + .data_18_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_18_V_address0), + .data_18_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_18_V_ce0), + .data_18_V_q0(layer4_out_18_V_q0), + .data_19_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_19_V_address0), + .data_19_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_19_V_ce0), + .data_19_V_q0(layer4_out_19_V_q0), + .data_20_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_20_V_address0), + .data_20_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_20_V_ce0), + .data_20_V_q0(layer4_out_20_V_q0), + .data_21_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_21_V_address0), + .data_21_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_21_V_ce0), + .data_21_V_q0(layer4_out_21_V_q0), + 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.data_110_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_110_V_address0), + .data_110_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_110_V_ce0), + .data_110_V_q0(layer4_out_110_V_q0), + .data_111_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_111_V_address0), + .data_111_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_111_V_ce0), + .data_111_V_q0(layer4_out_111_V_q0), + .data_112_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_112_V_address0), + .data_112_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_112_V_ce0), + .data_112_V_q0(layer4_out_112_V_q0), + .data_113_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_113_V_address0), + .data_113_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_113_V_ce0), + .data_113_V_q0(layer4_out_113_V_q0), + .data_114_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_114_V_address0), + .data_114_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_114_V_ce0), + .data_114_V_q0(layer4_out_114_V_q0), + .data_115_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_115_V_address0), + .data_115_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_115_V_ce0), + .data_115_V_q0(layer4_out_115_V_q0), + .data_116_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_116_V_address0), + .data_116_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_116_V_ce0), + .data_116_V_q0(layer4_out_116_V_q0), + .data_117_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_117_V_address0), + .data_117_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_117_V_ce0), + .data_117_V_q0(layer4_out_117_V_q0), + .data_118_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_118_V_address0), + .data_118_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_118_V_ce0), + .data_118_V_q0(layer4_out_118_V_q0), + .data_119_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_119_V_address0), + .data_119_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_119_V_ce0), + .data_119_V_q0(layer4_out_119_V_q0), + .data_120_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_120_V_address0), + .data_120_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_120_V_ce0), + .data_120_V_q0(layer4_out_120_V_q0), + .data_121_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_121_V_address0), + .data_121_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_121_V_ce0), + .data_121_V_q0(layer4_out_121_V_q0), + .data_122_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_122_V_address0), + .data_122_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_122_V_ce0), + .data_122_V_q0(layer4_out_122_V_q0), + .data_123_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_123_V_address0), + .data_123_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_123_V_ce0), + .data_123_V_q0(layer4_out_123_V_q0), + .data_124_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_124_V_address0), + .data_124_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_124_V_ce0), + .data_124_V_q0(layer4_out_124_V_q0), + .data_125_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_125_V_address0), + .data_125_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_125_V_ce0), + .data_125_V_q0(layer4_out_125_V_q0), + .data_126_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_126_V_address0), + .data_126_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_126_V_ce0), + .data_126_V_q0(layer4_out_126_V_q0), + .data_127_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_127_V_address0), + .data_127_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_127_V_ce0), + .data_127_V_q0(layer4_out_127_V_q0), + .res_0_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_0_V_address0), + .res_0_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_0_V_ce0), + .res_0_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_0_V_we0), + .res_0_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_0_V_d0), + .res_1_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_1_V_address0), + .res_1_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_1_V_ce0), + .res_1_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_1_V_we0), + .res_1_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_1_V_d0), + .res_2_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_2_V_address0), + .res_2_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_2_V_ce0), + .res_2_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_2_V_we0), + .res_2_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_2_V_d0), + .res_3_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_3_V_address0), + .res_3_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_3_V_ce0), + .res_3_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_3_V_we0), + .res_3_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_3_V_d0), + .res_4_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_4_V_address0), + .res_4_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_4_V_ce0), + .res_4_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_4_V_we0), + .res_4_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_4_V_d0), + .res_5_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_5_V_address0), + .res_5_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_5_V_ce0), + .res_5_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_5_V_we0), + .res_5_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_5_V_d0), + .res_6_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_6_V_address0), + .res_6_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_6_V_ce0), + .res_6_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_6_V_we0), + .res_6_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_6_V_d0), + .res_7_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_7_V_address0), + .res_7_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_7_V_ce0), + .res_7_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_7_V_we0), + .res_7_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_7_V_d0), + .res_8_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_8_V_address0), + .res_8_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_8_V_ce0), + .res_8_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_8_V_we0), + .res_8_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_8_V_d0), + .res_9_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_9_V_address0), + .res_9_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_9_V_ce0), + .res_9_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_9_V_we0), + .res_9_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_9_V_d0), + .res_10_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_10_V_address0), + .res_10_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_10_V_ce0), + .res_10_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_10_V_we0), + .res_10_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_10_V_d0), + .res_11_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_11_V_address0), + .res_11_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_11_V_ce0), + .res_11_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_11_V_we0), + .res_11_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_11_V_d0), + .res_12_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_12_V_address0), + .res_12_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_12_V_ce0), + .res_12_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_12_V_we0), + .res_12_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_12_V_d0), + .res_13_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_13_V_address0), + .res_13_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_13_V_ce0), + .res_13_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_13_V_we0), + .res_13_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_13_V_d0), + .res_14_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_14_V_address0), + .res_14_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_14_V_ce0), + .res_14_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_14_V_we0), + .res_14_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_14_V_d0), + .res_15_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_15_V_address0), + .res_15_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_15_V_ce0), + .res_15_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_15_V_we0), + .res_15_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_15_V_d0), + .res_16_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_16_V_address0), + .res_16_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_16_V_ce0), + .res_16_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_16_V_we0), + .res_16_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_16_V_d0), + .res_17_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_17_V_address0), + .res_17_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_17_V_ce0), + .res_17_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_17_V_we0), + .res_17_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_17_V_d0), + .res_18_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_18_V_address0), + .res_18_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_18_V_ce0), + .res_18_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_18_V_we0), + .res_18_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_18_V_d0), + .res_19_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_19_V_address0), + .res_19_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_19_V_ce0), + .res_19_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_19_V_we0), + .res_19_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_19_V_d0), + .res_20_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_20_V_address0), + .res_20_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_20_V_ce0), + .res_20_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_20_V_we0), + .res_20_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_20_V_d0), + .res_21_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_21_V_address0), + .res_21_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_21_V_ce0), + .res_21_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_21_V_we0), + .res_21_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_21_V_d0), + .res_22_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_22_V_address0), + .res_22_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_22_V_ce0), + .res_22_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_22_V_we0), + .res_22_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_22_V_d0), + .res_23_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_23_V_address0), + .res_23_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_23_V_ce0), + .res_23_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_23_V_we0), + .res_23_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_23_V_d0), + .res_24_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_24_V_address0), + .res_24_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_24_V_ce0), + .res_24_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_24_V_we0), + .res_24_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_24_V_d0), + .res_25_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_25_V_address0), + .res_25_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_25_V_ce0), + .res_25_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_25_V_we0), + .res_25_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_25_V_d0), + .res_26_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_26_V_address0), + .res_26_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_26_V_ce0), + .res_26_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_26_V_we0), + .res_26_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_26_V_d0), + .res_27_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_27_V_address0), + .res_27_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_27_V_ce0), + .res_27_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_27_V_we0), + .res_27_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_27_V_d0), + .res_28_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_28_V_address0), + .res_28_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_28_V_ce0), + .res_28_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_28_V_we0), + .res_28_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_28_V_d0), + .res_29_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_29_V_address0), + .res_29_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_29_V_ce0), + .res_29_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_29_V_we0), + .res_29_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_29_V_d0), + .res_30_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_30_V_address0), + .res_30_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_30_V_ce0), + .res_30_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_30_V_we0), + .res_30_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_30_V_d0), + .res_31_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_31_V_address0), + .res_31_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_31_V_ce0), + .res_31_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_31_V_we0), + .res_31_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_31_V_d0), + .res_32_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_32_V_address0), + .res_32_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_32_V_ce0), + .res_32_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_32_V_we0), + .res_32_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_32_V_d0), + .res_33_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_33_V_address0), + .res_33_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_33_V_ce0), + .res_33_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_33_V_we0), + .res_33_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_33_V_d0), + .res_34_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_34_V_address0), + .res_34_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_34_V_ce0), + .res_34_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_34_V_we0), + .res_34_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_34_V_d0), + .res_35_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_35_V_address0), + .res_35_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_35_V_ce0), + .res_35_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_35_V_we0), + .res_35_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_35_V_d0), + .res_36_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_36_V_address0), + .res_36_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_36_V_ce0), + .res_36_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_36_V_we0), + .res_36_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_36_V_d0), + .res_37_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_37_V_address0), + .res_37_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_37_V_ce0), + .res_37_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_37_V_we0), + .res_37_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_37_V_d0), + .res_38_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_38_V_address0), + .res_38_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_38_V_ce0), + .res_38_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_38_V_we0), + .res_38_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_38_V_d0), + .res_39_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_39_V_address0), + .res_39_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_39_V_ce0), + .res_39_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_39_V_we0), + .res_39_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_39_V_d0), + .res_40_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_40_V_address0), + .res_40_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_40_V_ce0), + .res_40_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_40_V_we0), + .res_40_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_40_V_d0), + .res_41_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_41_V_address0), + .res_41_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_41_V_ce0), + .res_41_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_41_V_we0), + .res_41_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_41_V_d0), + .res_42_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_42_V_address0), + .res_42_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_42_V_ce0), + .res_42_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_42_V_we0), + .res_42_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_42_V_d0), + .res_43_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_43_V_address0), + .res_43_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_43_V_ce0), + .res_43_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_43_V_we0), + .res_43_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_43_V_d0), + .res_44_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_44_V_address0), + .res_44_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_44_V_ce0), + .res_44_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_44_V_we0), + .res_44_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_44_V_d0), + .res_45_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_45_V_address0), + .res_45_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_45_V_ce0), + .res_45_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_45_V_we0), + .res_45_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_45_V_d0), + .res_46_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_46_V_address0), + .res_46_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_46_V_ce0), + .res_46_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_46_V_we0), + .res_46_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_46_V_d0), + .res_47_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_47_V_address0), + .res_47_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_47_V_ce0), + .res_47_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_47_V_we0), + .res_47_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_47_V_d0), + .res_48_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_48_V_address0), + .res_48_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_48_V_ce0), + .res_48_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_48_V_we0), + .res_48_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_48_V_d0), + .res_49_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_49_V_address0), + .res_49_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_49_V_ce0), + .res_49_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_49_V_we0), + .res_49_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_49_V_d0), + .res_50_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_50_V_address0), + .res_50_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_50_V_ce0), + .res_50_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_50_V_we0), + .res_50_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_50_V_d0), + .res_51_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_51_V_address0), + .res_51_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_51_V_ce0), + .res_51_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_51_V_we0), + .res_51_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_51_V_d0), + .res_52_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_52_V_address0), + .res_52_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_52_V_ce0), + .res_52_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_52_V_we0), + .res_52_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_52_V_d0), + .res_53_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_53_V_address0), + .res_53_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_53_V_ce0), + .res_53_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_53_V_we0), + .res_53_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_53_V_d0), + .res_54_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_54_V_address0), + .res_54_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_54_V_ce0), + .res_54_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_54_V_we0), + .res_54_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_54_V_d0), + .res_55_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_55_V_address0), + .res_55_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_55_V_ce0), + .res_55_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_55_V_we0), + .res_55_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_55_V_d0), + .res_56_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_56_V_address0), + .res_56_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_56_V_ce0), + .res_56_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_56_V_we0), + .res_56_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_56_V_d0), + .res_57_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_57_V_address0), + .res_57_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_57_V_ce0), + .res_57_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_57_V_we0), + .res_57_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_57_V_d0), + .res_58_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_58_V_address0), + .res_58_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_58_V_ce0), + .res_58_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_58_V_we0), + .res_58_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_58_V_d0), + .res_59_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_59_V_address0), + .res_59_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_59_V_ce0), + .res_59_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_59_V_we0), + .res_59_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_59_V_d0), + .res_60_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_60_V_address0), + .res_60_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_60_V_ce0), + .res_60_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_60_V_we0), + .res_60_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_60_V_d0), + .res_61_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_61_V_address0), + .res_61_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_61_V_ce0), + .res_61_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_61_V_we0), + .res_61_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_61_V_d0), + .res_62_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_62_V_address0), + .res_62_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_62_V_ce0), + .res_62_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_62_V_we0), + .res_62_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_62_V_d0), + .res_63_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_63_V_address0), + .res_63_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_63_V_ce0), + .res_63_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_63_V_we0), + .res_63_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_63_V_d0), + .res_64_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_64_V_address0), + .res_64_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_64_V_ce0), + .res_64_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_64_V_we0), + .res_64_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_64_V_d0), + .res_65_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_65_V_address0), + .res_65_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_65_V_ce0), + .res_65_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_65_V_we0), + .res_65_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_65_V_d0), + .res_66_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_66_V_address0), + .res_66_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_66_V_ce0), + .res_66_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_66_V_we0), + .res_66_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_66_V_d0), + .res_67_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_67_V_address0), + .res_67_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_67_V_ce0), + .res_67_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_67_V_we0), + .res_67_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_67_V_d0), + .res_68_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_68_V_address0), + .res_68_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_68_V_ce0), + .res_68_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_68_V_we0), + .res_68_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_68_V_d0), + .res_69_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_69_V_address0), + .res_69_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_69_V_ce0), + .res_69_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_69_V_we0), + .res_69_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_69_V_d0), + .res_70_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_70_V_address0), + .res_70_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_70_V_ce0), + .res_70_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_70_V_we0), + .res_70_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_70_V_d0), + .res_71_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_71_V_address0), + .res_71_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_71_V_ce0), + .res_71_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_71_V_we0), + .res_71_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_71_V_d0), + .res_72_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_72_V_address0), + .res_72_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_72_V_ce0), + .res_72_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_72_V_we0), + .res_72_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_72_V_d0), + .res_73_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_73_V_address0), + .res_73_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_73_V_ce0), + .res_73_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_73_V_we0), + .res_73_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_73_V_d0), + .res_74_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_74_V_address0), + .res_74_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_74_V_ce0), + .res_74_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_74_V_we0), + .res_74_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_74_V_d0), + .res_75_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_75_V_address0), + .res_75_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_75_V_ce0), + .res_75_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_75_V_we0), + .res_75_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_75_V_d0), + .res_76_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_76_V_address0), + .res_76_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_76_V_ce0), + .res_76_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_76_V_we0), + .res_76_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_76_V_d0), + .res_77_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_77_V_address0), + .res_77_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_77_V_ce0), + .res_77_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_77_V_we0), + .res_77_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_77_V_d0), + .res_78_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_78_V_address0), + .res_78_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_78_V_ce0), + .res_78_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_78_V_we0), + .res_78_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_78_V_d0), + .res_79_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_79_V_address0), + .res_79_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_79_V_ce0), + .res_79_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_79_V_we0), + .res_79_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_79_V_d0), + .res_80_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_80_V_address0), + .res_80_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_80_V_ce0), + .res_80_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_80_V_we0), + .res_80_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_80_V_d0), + .res_81_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_81_V_address0), + .res_81_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_81_V_ce0), + .res_81_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_81_V_we0), + .res_81_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_81_V_d0), + .res_82_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_82_V_address0), + .res_82_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_82_V_ce0), + .res_82_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_82_V_we0), + .res_82_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_82_V_d0), + .res_83_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_83_V_address0), + .res_83_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_83_V_ce0), + .res_83_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_83_V_we0), + .res_83_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_83_V_d0), + .res_84_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_84_V_address0), + .res_84_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_84_V_ce0), + .res_84_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_84_V_we0), + .res_84_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_84_V_d0), + .res_85_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_85_V_address0), + .res_85_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_85_V_ce0), + .res_85_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_85_V_we0), + .res_85_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_85_V_d0), + .res_86_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_86_V_address0), + .res_86_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_86_V_ce0), + .res_86_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_86_V_we0), + .res_86_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_86_V_d0), + .res_87_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_87_V_address0), + .res_87_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_87_V_ce0), + .res_87_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_87_V_we0), + .res_87_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_87_V_d0), + .res_88_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_88_V_address0), + .res_88_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_88_V_ce0), + .res_88_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_88_V_we0), + .res_88_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_88_V_d0), + .res_89_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_89_V_address0), + .res_89_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_89_V_ce0), + .res_89_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_89_V_we0), + .res_89_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_89_V_d0), + .res_90_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_90_V_address0), + .res_90_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_90_V_ce0), + .res_90_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_90_V_we0), + .res_90_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_90_V_d0), + .res_91_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_91_V_address0), + .res_91_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_91_V_ce0), + .res_91_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_91_V_we0), + .res_91_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_91_V_d0), + .res_92_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_92_V_address0), + .res_92_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_92_V_ce0), + .res_92_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_92_V_we0), + .res_92_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_92_V_d0), + .res_93_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_93_V_address0), + .res_93_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_93_V_ce0), + .res_93_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_93_V_we0), + .res_93_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_93_V_d0), + .res_94_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_94_V_address0), + .res_94_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_94_V_ce0), + .res_94_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_94_V_we0), + .res_94_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_94_V_d0), + .res_95_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_95_V_address0), + .res_95_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_95_V_ce0), + .res_95_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_95_V_we0), + .res_95_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_95_V_d0), + .res_96_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_96_V_address0), + .res_96_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_96_V_ce0), + .res_96_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_96_V_we0), + .res_96_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_96_V_d0), + .res_97_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_97_V_address0), + .res_97_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_97_V_ce0), + .res_97_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_97_V_we0), + .res_97_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_97_V_d0), + .res_98_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_98_V_address0), + .res_98_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_98_V_ce0), + .res_98_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_98_V_we0), + .res_98_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_98_V_d0), + .res_99_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_99_V_address0), + .res_99_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_99_V_ce0), + .res_99_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_99_V_we0), + .res_99_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_99_V_d0), + .res_100_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_100_V_address0), + .res_100_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_100_V_ce0), + .res_100_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_100_V_we0), + .res_100_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_100_V_d0), + .res_101_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_101_V_address0), + .res_101_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_101_V_ce0), + .res_101_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_101_V_we0), + .res_101_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_101_V_d0), + .res_102_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_102_V_address0), + .res_102_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_102_V_ce0), + .res_102_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_102_V_we0), + .res_102_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_102_V_d0), + .res_103_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_103_V_address0), + .res_103_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_103_V_ce0), + .res_103_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_103_V_we0), + .res_103_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_103_V_d0), + .res_104_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_104_V_address0), + .res_104_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_104_V_ce0), + .res_104_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_104_V_we0), + .res_104_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_104_V_d0), + .res_105_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_105_V_address0), + .res_105_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_105_V_ce0), + .res_105_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_105_V_we0), + .res_105_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_105_V_d0), + .res_106_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_106_V_address0), + .res_106_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_106_V_ce0), + .res_106_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_106_V_we0), + .res_106_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_106_V_d0), + .res_107_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_107_V_address0), + .res_107_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_107_V_ce0), + .res_107_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_107_V_we0), + .res_107_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_107_V_d0), + .res_108_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_108_V_address0), + .res_108_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_108_V_ce0), + .res_108_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_108_V_we0), + .res_108_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_108_V_d0), + .res_109_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_109_V_address0), + .res_109_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_109_V_ce0), + .res_109_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_109_V_we0), + .res_109_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_109_V_d0), + .res_110_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_110_V_address0), + .res_110_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_110_V_ce0), + .res_110_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_110_V_we0), + .res_110_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_110_V_d0), + .res_111_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_111_V_address0), + .res_111_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_111_V_ce0), + .res_111_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_111_V_we0), + .res_111_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_111_V_d0), + .res_112_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_112_V_address0), + .res_112_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_112_V_ce0), + .res_112_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_112_V_we0), + .res_112_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_112_V_d0), + .res_113_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_113_V_address0), + .res_113_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_113_V_ce0), + .res_113_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_113_V_we0), + .res_113_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_113_V_d0), + .res_114_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_114_V_address0), + .res_114_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_114_V_ce0), + .res_114_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_114_V_we0), + .res_114_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_114_V_d0), + .res_115_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_115_V_address0), + .res_115_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_115_V_ce0), + .res_115_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_115_V_we0), + .res_115_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_115_V_d0), + .res_116_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_116_V_address0), + .res_116_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_116_V_ce0), + .res_116_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_116_V_we0), + .res_116_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_116_V_d0), + .res_117_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_117_V_address0), + .res_117_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_117_V_ce0), + .res_117_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_117_V_we0), + .res_117_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_117_V_d0), + .res_118_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_118_V_address0), + .res_118_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_118_V_ce0), + .res_118_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_118_V_we0), + .res_118_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_118_V_d0), + .res_119_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_119_V_address0), + .res_119_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_119_V_ce0), + .res_119_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_119_V_we0), + .res_119_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_119_V_d0), + .res_120_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_120_V_address0), + .res_120_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_120_V_ce0), + .res_120_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_120_V_we0), + .res_120_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_120_V_d0), + .res_121_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_121_V_address0), + .res_121_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_121_V_ce0), + .res_121_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_121_V_we0), + .res_121_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_121_V_d0), + .res_122_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_122_V_address0), + .res_122_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_122_V_ce0), + .res_122_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_122_V_we0), + .res_122_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_122_V_d0), + .res_123_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_123_V_address0), + .res_123_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_123_V_ce0), + .res_123_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_123_V_we0), + .res_123_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_123_V_d0), + .res_124_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_124_V_address0), + .res_124_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_124_V_ce0), + .res_124_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_124_V_we0), + .res_124_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_124_V_d0), + .res_125_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_125_V_address0), + .res_125_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_125_V_ce0), + .res_125_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_125_V_we0), + .res_125_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_125_V_d0), + .res_126_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_126_V_address0), + .res_126_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_126_V_ce0), + .res_126_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_126_V_we0), + .res_126_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_126_V_d0), + .res_127_V_address0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_127_V_address0), + .res_127_V_ce0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_127_V_ce0), + .res_127_V_we0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_127_V_we0), + .res_127_V_d0(grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_127_V_d0) +); + +conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0 grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_start), + .ap_done(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_done), + .ap_idle(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_idle), + .ap_ready(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_ready), + .data_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_data_V_address0), + .data_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_data_V_ce0), + .data_V_q0(conv2d_input_V_q0), + .res_0_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_0_V_address0), + .res_0_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_0_V_ce0), + .res_0_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_0_V_we0), + .res_0_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_0_V_d0), + .res_1_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_1_V_address0), + .res_1_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_1_V_ce0), + .res_1_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_1_V_we0), + .res_1_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_1_V_d0), + .res_2_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_2_V_address0), + .res_2_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_2_V_ce0), + .res_2_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_2_V_we0), + .res_2_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_2_V_d0), + .res_3_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_3_V_address0), + .res_3_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_3_V_ce0), + .res_3_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_3_V_we0), + .res_3_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_3_V_d0), + .res_4_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_4_V_address0), + .res_4_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_4_V_ce0), + .res_4_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_4_V_we0), + .res_4_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_4_V_d0), + .res_5_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_5_V_address0), + .res_5_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_5_V_ce0), + .res_5_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_5_V_we0), + .res_5_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_5_V_d0), + .res_6_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_6_V_address0), + .res_6_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_6_V_ce0), + .res_6_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_6_V_we0), + .res_6_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_6_V_d0), + .res_7_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_7_V_address0), + .res_7_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_7_V_ce0), + .res_7_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_7_V_we0), + .res_7_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_7_V_d0), + .res_8_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_8_V_address0), + .res_8_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_8_V_ce0), + .res_8_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_8_V_we0), + .res_8_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_8_V_d0), + .res_9_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_9_V_address0), + .res_9_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_9_V_ce0), + .res_9_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_9_V_we0), + .res_9_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_9_V_d0), + .res_10_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_10_V_address0), + .res_10_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_10_V_ce0), + .res_10_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_10_V_we0), + .res_10_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_10_V_d0), + .res_11_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_11_V_address0), + .res_11_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_11_V_ce0), + .res_11_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_11_V_we0), + .res_11_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_11_V_d0), + .res_12_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_12_V_address0), + .res_12_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_12_V_ce0), + .res_12_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_12_V_we0), + .res_12_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_12_V_d0), + .res_13_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_13_V_address0), + .res_13_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_13_V_ce0), + .res_13_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_13_V_we0), + .res_13_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_13_V_d0), + .res_14_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_14_V_address0), + .res_14_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_14_V_ce0), + .res_14_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_14_V_we0), + .res_14_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_14_V_d0), + .res_15_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_15_V_address0), + .res_15_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_15_V_ce0), + .res_15_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_15_V_we0), + .res_15_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_15_V_d0), + .res_16_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_16_V_address0), + .res_16_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_16_V_ce0), + .res_16_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_16_V_we0), + .res_16_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_16_V_d0), + .res_17_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_17_V_address0), + .res_17_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_17_V_ce0), + .res_17_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_17_V_we0), + .res_17_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_17_V_d0), + .res_18_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_18_V_address0), + .res_18_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_18_V_ce0), + .res_18_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_18_V_we0), + .res_18_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_18_V_d0), + .res_19_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_19_V_address0), + .res_19_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_19_V_ce0), + .res_19_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_19_V_we0), + .res_19_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_19_V_d0), + .res_20_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_20_V_address0), + .res_20_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_20_V_ce0), + .res_20_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_20_V_we0), + .res_20_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_20_V_d0), + .res_21_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_21_V_address0), + .res_21_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_21_V_ce0), + .res_21_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_21_V_we0), + .res_21_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_21_V_d0), + .res_22_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_22_V_address0), + .res_22_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_22_V_ce0), + .res_22_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_22_V_we0), + .res_22_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_22_V_d0), + .res_23_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_23_V_address0), + .res_23_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_23_V_ce0), + .res_23_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_23_V_we0), + .res_23_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_23_V_d0), + .res_24_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_24_V_address0), + .res_24_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_24_V_ce0), + .res_24_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_24_V_we0), + .res_24_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_24_V_d0), + .res_25_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_25_V_address0), + .res_25_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_25_V_ce0), + .res_25_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_25_V_we0), + .res_25_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_25_V_d0), + .res_26_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_26_V_address0), + .res_26_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_26_V_ce0), + .res_26_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_26_V_we0), + .res_26_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_26_V_d0), + .res_27_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_27_V_address0), + .res_27_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_27_V_ce0), + .res_27_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_27_V_we0), + .res_27_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_27_V_d0), + .res_28_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_28_V_address0), + .res_28_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_28_V_ce0), + .res_28_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_28_V_we0), + .res_28_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_28_V_d0), + .res_29_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_29_V_address0), + .res_29_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_29_V_ce0), + .res_29_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_29_V_we0), + .res_29_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_29_V_d0), + .res_30_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_30_V_address0), + .res_30_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_30_V_ce0), + .res_30_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_30_V_we0), + .res_30_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_30_V_d0), + .res_31_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_31_V_address0), + .res_31_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_31_V_ce0), + .res_31_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_31_V_we0), + .res_31_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_31_V_d0), + .res_32_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_32_V_address0), + .res_32_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_32_V_ce0), + .res_32_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_32_V_we0), + .res_32_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_32_V_d0), + .res_33_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_33_V_address0), + .res_33_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_33_V_ce0), + .res_33_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_33_V_we0), + .res_33_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_33_V_d0), + .res_34_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_34_V_address0), + .res_34_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_34_V_ce0), + .res_34_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_34_V_we0), + .res_34_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_34_V_d0), + .res_35_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_35_V_address0), + .res_35_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_35_V_ce0), + .res_35_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_35_V_we0), + .res_35_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_35_V_d0), + .res_36_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_36_V_address0), + .res_36_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_36_V_ce0), + .res_36_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_36_V_we0), + .res_36_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_36_V_d0), + .res_37_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_37_V_address0), + .res_37_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_37_V_ce0), + .res_37_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_37_V_we0), + .res_37_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_37_V_d0), + .res_38_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_38_V_address0), + .res_38_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_38_V_ce0), + .res_38_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_38_V_we0), + .res_38_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_38_V_d0), + .res_39_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_39_V_address0), + .res_39_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_39_V_ce0), + .res_39_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_39_V_we0), + .res_39_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_39_V_d0), + .res_40_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_40_V_address0), + .res_40_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_40_V_ce0), + .res_40_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_40_V_we0), + .res_40_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_40_V_d0), + .res_41_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_41_V_address0), + .res_41_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_41_V_ce0), + .res_41_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_41_V_we0), + .res_41_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_41_V_d0), + .res_42_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_42_V_address0), + .res_42_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_42_V_ce0), + .res_42_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_42_V_we0), + .res_42_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_42_V_d0), + .res_43_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_43_V_address0), + .res_43_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_43_V_ce0), + .res_43_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_43_V_we0), + .res_43_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_43_V_d0), + .res_44_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_44_V_address0), + .res_44_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_44_V_ce0), + .res_44_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_44_V_we0), + .res_44_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_44_V_d0), + .res_45_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_45_V_address0), + .res_45_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_45_V_ce0), + .res_45_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_45_V_we0), + .res_45_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_45_V_d0), + .res_46_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_46_V_address0), + .res_46_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_46_V_ce0), + .res_46_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_46_V_we0), + .res_46_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_46_V_d0), + .res_47_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_47_V_address0), + .res_47_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_47_V_ce0), + .res_47_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_47_V_we0), + .res_47_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_47_V_d0), + .res_48_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_48_V_address0), + .res_48_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_48_V_ce0), + .res_48_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_48_V_we0), + .res_48_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_48_V_d0), + .res_49_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_49_V_address0), + .res_49_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_49_V_ce0), + .res_49_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_49_V_we0), + .res_49_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_49_V_d0), + .res_50_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_50_V_address0), + .res_50_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_50_V_ce0), + .res_50_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_50_V_we0), + .res_50_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_50_V_d0), + .res_51_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_51_V_address0), + .res_51_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_51_V_ce0), + .res_51_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_51_V_we0), + .res_51_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_51_V_d0), + .res_52_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_52_V_address0), + .res_52_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_52_V_ce0), + .res_52_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_52_V_we0), + .res_52_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_52_V_d0), + .res_53_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_53_V_address0), + .res_53_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_53_V_ce0), + .res_53_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_53_V_we0), + .res_53_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_53_V_d0), + .res_54_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_54_V_address0), + .res_54_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_54_V_ce0), + .res_54_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_54_V_we0), + .res_54_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_54_V_d0), + .res_55_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_55_V_address0), + .res_55_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_55_V_ce0), + .res_55_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_55_V_we0), + .res_55_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_55_V_d0), + .res_56_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_56_V_address0), + .res_56_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_56_V_ce0), + .res_56_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_56_V_we0), + .res_56_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_56_V_d0), + .res_57_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_57_V_address0), + .res_57_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_57_V_ce0), + .res_57_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_57_V_we0), + .res_57_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_57_V_d0), + .res_58_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_58_V_address0), + .res_58_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_58_V_ce0), + .res_58_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_58_V_we0), + .res_58_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_58_V_d0), + .res_59_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_59_V_address0), + .res_59_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_59_V_ce0), + .res_59_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_59_V_we0), + .res_59_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_59_V_d0), + .res_60_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_60_V_address0), + .res_60_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_60_V_ce0), + .res_60_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_60_V_we0), + .res_60_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_60_V_d0), + .res_61_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_61_V_address0), + .res_61_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_61_V_ce0), + .res_61_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_61_V_we0), + .res_61_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_61_V_d0), + .res_62_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_62_V_address0), + .res_62_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_62_V_ce0), + .res_62_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_62_V_we0), + .res_62_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_62_V_d0), + .res_63_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_63_V_address0), + .res_63_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_63_V_ce0), + .res_63_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_63_V_we0), + .res_63_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_63_V_d0), + .res_64_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_64_V_address0), + .res_64_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_64_V_ce0), + .res_64_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_64_V_we0), + .res_64_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_64_V_d0), + .res_65_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_65_V_address0), + .res_65_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_65_V_ce0), + .res_65_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_65_V_we0), + .res_65_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_65_V_d0), + .res_66_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_66_V_address0), + .res_66_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_66_V_ce0), + .res_66_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_66_V_we0), + .res_66_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_66_V_d0), + .res_67_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_67_V_address0), + .res_67_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_67_V_ce0), + .res_67_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_67_V_we0), + .res_67_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_67_V_d0), + .res_68_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_68_V_address0), + .res_68_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_68_V_ce0), + .res_68_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_68_V_we0), + .res_68_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_68_V_d0), + .res_69_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_69_V_address0), + .res_69_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_69_V_ce0), + .res_69_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_69_V_we0), + .res_69_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_69_V_d0), + .res_70_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_70_V_address0), + .res_70_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_70_V_ce0), + .res_70_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_70_V_we0), + .res_70_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_70_V_d0), + .res_71_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_71_V_address0), + .res_71_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_71_V_ce0), + .res_71_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_71_V_we0), + .res_71_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_71_V_d0), + .res_72_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_72_V_address0), + .res_72_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_72_V_ce0), + .res_72_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_72_V_we0), + .res_72_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_72_V_d0), + .res_73_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_73_V_address0), + .res_73_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_73_V_ce0), + .res_73_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_73_V_we0), + .res_73_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_73_V_d0), + .res_74_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_74_V_address0), + .res_74_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_74_V_ce0), + .res_74_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_74_V_we0), + .res_74_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_74_V_d0), + .res_75_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_75_V_address0), + .res_75_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_75_V_ce0), + .res_75_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_75_V_we0), + .res_75_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_75_V_d0), + .res_76_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_76_V_address0), + .res_76_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_76_V_ce0), + .res_76_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_76_V_we0), + .res_76_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_76_V_d0), + .res_77_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_77_V_address0), + .res_77_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_77_V_ce0), + .res_77_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_77_V_we0), + .res_77_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_77_V_d0), + .res_78_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_78_V_address0), + .res_78_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_78_V_ce0), + .res_78_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_78_V_we0), + .res_78_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_78_V_d0), + .res_79_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_79_V_address0), + .res_79_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_79_V_ce0), + .res_79_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_79_V_we0), + .res_79_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_79_V_d0), + .res_80_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_80_V_address0), + .res_80_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_80_V_ce0), + .res_80_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_80_V_we0), + .res_80_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_80_V_d0), + .res_81_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_81_V_address0), + .res_81_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_81_V_ce0), + .res_81_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_81_V_we0), + .res_81_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_81_V_d0), + .res_82_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_82_V_address0), + .res_82_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_82_V_ce0), + .res_82_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_82_V_we0), + .res_82_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_82_V_d0), + .res_83_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_83_V_address0), + .res_83_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_83_V_ce0), + .res_83_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_83_V_we0), + .res_83_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_83_V_d0), + .res_84_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_84_V_address0), + .res_84_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_84_V_ce0), + .res_84_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_84_V_we0), + .res_84_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_84_V_d0), + .res_85_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_85_V_address0), + .res_85_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_85_V_ce0), + .res_85_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_85_V_we0), + .res_85_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_85_V_d0), + .res_86_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_86_V_address0), + .res_86_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_86_V_ce0), + .res_86_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_86_V_we0), + .res_86_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_86_V_d0), + .res_87_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_87_V_address0), + .res_87_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_87_V_ce0), + .res_87_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_87_V_we0), + .res_87_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_87_V_d0), + .res_88_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_88_V_address0), + .res_88_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_88_V_ce0), + .res_88_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_88_V_we0), + .res_88_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_88_V_d0), + .res_89_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_89_V_address0), + .res_89_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_89_V_ce0), + .res_89_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_89_V_we0), + .res_89_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_89_V_d0), + .res_90_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_90_V_address0), + .res_90_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_90_V_ce0), + .res_90_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_90_V_we0), + .res_90_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_90_V_d0), + .res_91_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_91_V_address0), + .res_91_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_91_V_ce0), + .res_91_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_91_V_we0), + .res_91_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_91_V_d0), + .res_92_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_92_V_address0), + .res_92_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_92_V_ce0), + .res_92_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_92_V_we0), + .res_92_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_92_V_d0), + .res_93_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_93_V_address0), + .res_93_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_93_V_ce0), + .res_93_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_93_V_we0), + .res_93_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_93_V_d0), + .res_94_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_94_V_address0), + .res_94_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_94_V_ce0), + .res_94_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_94_V_we0), + .res_94_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_94_V_d0), + .res_95_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_95_V_address0), + .res_95_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_95_V_ce0), + .res_95_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_95_V_we0), + .res_95_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_95_V_d0), + .res_96_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_96_V_address0), + .res_96_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_96_V_ce0), + .res_96_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_96_V_we0), + .res_96_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_96_V_d0), + .res_97_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_97_V_address0), + .res_97_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_97_V_ce0), + .res_97_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_97_V_we0), + .res_97_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_97_V_d0), + .res_98_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_98_V_address0), + .res_98_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_98_V_ce0), + .res_98_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_98_V_we0), + .res_98_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_98_V_d0), + .res_99_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_99_V_address0), + .res_99_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_99_V_ce0), + .res_99_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_99_V_we0), + .res_99_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_99_V_d0), + .res_100_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_100_V_address0), + .res_100_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_100_V_ce0), + .res_100_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_100_V_we0), + .res_100_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_100_V_d0), + .res_101_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_101_V_address0), + .res_101_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_101_V_ce0), + .res_101_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_101_V_we0), + .res_101_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_101_V_d0), + .res_102_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_102_V_address0), + .res_102_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_102_V_ce0), + .res_102_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_102_V_we0), + .res_102_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_102_V_d0), + .res_103_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_103_V_address0), + .res_103_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_103_V_ce0), + .res_103_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_103_V_we0), + .res_103_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_103_V_d0), + .res_104_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_104_V_address0), + .res_104_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_104_V_ce0), + .res_104_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_104_V_we0), + .res_104_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_104_V_d0), + .res_105_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_105_V_address0), + .res_105_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_105_V_ce0), + .res_105_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_105_V_we0), + .res_105_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_105_V_d0), + .res_106_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_106_V_address0), + .res_106_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_106_V_ce0), + .res_106_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_106_V_we0), + .res_106_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_106_V_d0), + .res_107_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_107_V_address0), + .res_107_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_107_V_ce0), + .res_107_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_107_V_we0), + .res_107_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_107_V_d0), + .res_108_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_108_V_address0), + .res_108_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_108_V_ce0), + .res_108_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_108_V_we0), + .res_108_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_108_V_d0), + .res_109_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_109_V_address0), + .res_109_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_109_V_ce0), + .res_109_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_109_V_we0), + .res_109_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_109_V_d0), + .res_110_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_110_V_address0), + .res_110_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_110_V_ce0), + .res_110_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_110_V_we0), + .res_110_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_110_V_d0), + .res_111_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_111_V_address0), + .res_111_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_111_V_ce0), + .res_111_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_111_V_we0), + .res_111_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_111_V_d0), + .res_112_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_112_V_address0), + .res_112_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_112_V_ce0), + .res_112_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_112_V_we0), + .res_112_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_112_V_d0), + .res_113_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_113_V_address0), + .res_113_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_113_V_ce0), + .res_113_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_113_V_we0), + .res_113_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_113_V_d0), + .res_114_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_114_V_address0), + .res_114_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_114_V_ce0), + .res_114_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_114_V_we0), + .res_114_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_114_V_d0), + .res_115_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_115_V_address0), + .res_115_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_115_V_ce0), + .res_115_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_115_V_we0), + .res_115_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_115_V_d0), + .res_116_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_116_V_address0), + .res_116_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_116_V_ce0), + .res_116_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_116_V_we0), + .res_116_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_116_V_d0), + .res_117_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_117_V_address0), + .res_117_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_117_V_ce0), + .res_117_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_117_V_we0), + .res_117_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_117_V_d0), + .res_118_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_118_V_address0), + .res_118_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_118_V_ce0), + .res_118_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_118_V_we0), + .res_118_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_118_V_d0), + .res_119_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_119_V_address0), + .res_119_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_119_V_ce0), + .res_119_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_119_V_we0), + .res_119_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_119_V_d0), + .res_120_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_120_V_address0), + .res_120_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_120_V_ce0), + .res_120_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_120_V_we0), + .res_120_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_120_V_d0), + .res_121_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_121_V_address0), + .res_121_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_121_V_ce0), + .res_121_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_121_V_we0), + .res_121_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_121_V_d0), + .res_122_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_122_V_address0), + .res_122_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_122_V_ce0), + .res_122_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_122_V_we0), + .res_122_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_122_V_d0), + .res_123_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_123_V_address0), + .res_123_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_123_V_ce0), + .res_123_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_123_V_we0), + .res_123_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_123_V_d0), + .res_124_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_124_V_address0), + .res_124_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_124_V_ce0), + .res_124_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_124_V_we0), + .res_124_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_124_V_d0), + .res_125_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_125_V_address0), + .res_125_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_125_V_ce0), + .res_125_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_125_V_we0), + .res_125_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_125_V_d0), + .res_126_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_126_V_address0), + .res_126_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_126_V_ce0), + .res_126_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_126_V_we0), + .res_126_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_126_V_d0), + .res_127_V_address0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_127_V_address0), + .res_127_V_ce0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_127_V_ce0), + .res_127_V_we0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_127_V_we0), + .res_127_V_d0(grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_127_V_d0) +); + +dense_latency_0_0_0_0_0_0_0_0_0_0_0 grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811( + .data_0_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_address0), + .data_0_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_ce0), + .data_0_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_d0), + .data_0_V_q0(layer7_out_0_V_q0), + .data_0_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_we0), + .data_0_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_address1), + .data_0_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_ce1), + .data_0_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_d1), + .data_0_V_q1(8'd0), + .data_0_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_we1), + .data_1_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_address0), + .data_1_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_ce0), + .data_1_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_d0), + .data_1_V_q0(layer7_out_1_V_q0), + .data_1_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_we0), + .data_1_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_address1), + .data_1_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_ce1), + .data_1_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_d1), + .data_1_V_q1(8'd0), + .data_1_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_we1), + .data_2_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_address0), + .data_2_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_ce0), + .data_2_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_d0), + .data_2_V_q0(layer7_out_2_V_q0), + .data_2_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_we0), + .data_2_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_address1), + .data_2_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_ce1), + .data_2_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_d1), + .data_2_V_q1(8'd0), + .data_2_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_we1), + .data_3_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_address0), + .data_3_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_ce0), + .data_3_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_d0), + .data_3_V_q0(layer7_out_3_V_q0), + .data_3_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_we0), + .data_3_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_address1), + .data_3_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_ce1), + .data_3_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_d1), + .data_3_V_q1(8'd0), + .data_3_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_we1), + .data_4_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_address0), + .data_4_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_ce0), + .data_4_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_d0), + .data_4_V_q0(layer7_out_4_V_q0), + .data_4_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_we0), + .data_4_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_address1), + .data_4_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_ce1), + .data_4_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_d1), + .data_4_V_q1(8'd0), + .data_4_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_we1), + .data_5_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_address0), + .data_5_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_ce0), + .data_5_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_d0), + .data_5_V_q0(layer7_out_5_V_q0), + .data_5_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_we0), + .data_5_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_address1), + .data_5_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_ce1), + .data_5_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_d1), + .data_5_V_q1(8'd0), + .data_5_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_we1), + .data_6_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_address0), + .data_6_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_ce0), + .data_6_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_d0), + .data_6_V_q0(layer7_out_6_V_q0), + .data_6_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_we0), + .data_6_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_address1), + .data_6_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_ce1), + .data_6_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_d1), + .data_6_V_q1(8'd0), + .data_6_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_we1), + .data_7_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_address0), + .data_7_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_ce0), + .data_7_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_d0), + .data_7_V_q0(layer7_out_7_V_q0), + .data_7_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_we0), + .data_7_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_address1), + .data_7_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_ce1), + .data_7_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_d1), + .data_7_V_q1(8'd0), + .data_7_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_we1), + .data_8_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_address0), + .data_8_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_ce0), + .data_8_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_d0), + .data_8_V_q0(layer7_out_8_V_q0), + .data_8_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_we0), + .data_8_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_address1), + .data_8_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_ce1), + .data_8_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_d1), + .data_8_V_q1(8'd0), + .data_8_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_we1), + .data_9_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_address0), + .data_9_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_ce0), + .data_9_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_d0), + .data_9_V_q0(layer7_out_9_V_q0), + .data_9_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_we0), + .data_9_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_address1), + .data_9_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_ce1), + .data_9_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_d1), + .data_9_V_q1(8'd0), + .data_9_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_we1), + .data_10_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_address0), + .data_10_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_ce0), + .data_10_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_d0), + .data_10_V_q0(layer7_out_10_V_q0), + .data_10_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_we0), + .data_10_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_address1), + .data_10_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_ce1), + .data_10_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_d1), + .data_10_V_q1(8'd0), + .data_10_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_we1), + .data_11_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_address0), + .data_11_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_ce0), + .data_11_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_d0), + .data_11_V_q0(layer7_out_11_V_q0), + .data_11_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_we0), + .data_11_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_address1), + .data_11_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_ce1), + .data_11_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_d1), + .data_11_V_q1(8'd0), + .data_11_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_we1), + .data_12_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_address0), + .data_12_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_ce0), + .data_12_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_d0), + .data_12_V_q0(layer7_out_12_V_q0), + .data_12_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_we0), + .data_12_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_address1), + .data_12_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_ce1), + .data_12_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_d1), + .data_12_V_q1(8'd0), + .data_12_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_we1), + .data_13_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_address0), + .data_13_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_ce0), + .data_13_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_d0), + .data_13_V_q0(layer7_out_13_V_q0), + .data_13_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_we0), + .data_13_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_address1), + .data_13_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_ce1), + .data_13_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_d1), + .data_13_V_q1(8'd0), + .data_13_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_we1), + .data_14_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_address0), + .data_14_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_ce0), + .data_14_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_d0), + .data_14_V_q0(layer7_out_14_V_q0), + .data_14_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_we0), + .data_14_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_address1), + .data_14_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_ce1), + .data_14_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_d1), + .data_14_V_q1(8'd0), + .data_14_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_we1), + .data_15_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_address0), + .data_15_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_ce0), + .data_15_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_d0), + .data_15_V_q0(layer7_out_15_V_q0), + .data_15_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_we0), + .data_15_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_address1), + .data_15_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_ce1), + .data_15_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_d1), + .data_15_V_q1(8'd0), + .data_15_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_we1), + .data_16_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_address0), + .data_16_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_ce0), + .data_16_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_d0), + .data_16_V_q0(layer7_out_16_V_q0), + .data_16_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_we0), + .data_16_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_address1), + .data_16_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_ce1), + .data_16_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_d1), + .data_16_V_q1(8'd0), + .data_16_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_we1), + .data_17_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_address0), + .data_17_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_ce0), + .data_17_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_d0), + .data_17_V_q0(layer7_out_17_V_q0), + .data_17_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_we0), + .data_17_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_address1), + .data_17_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_ce1), + .data_17_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_d1), + .data_17_V_q1(8'd0), + .data_17_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_we1), + .data_18_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_address0), + .data_18_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_ce0), + .data_18_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_d0), + .data_18_V_q0(layer7_out_18_V_q0), + .data_18_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_we0), + .data_18_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_address1), + .data_18_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_ce1), + .data_18_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_d1), + .data_18_V_q1(8'd0), + .data_18_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_we1), + .data_19_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_address0), + .data_19_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_ce0), + .data_19_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_d0), + .data_19_V_q0(layer7_out_19_V_q0), + .data_19_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_we0), + .data_19_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_address1), + .data_19_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_ce1), + .data_19_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_d1), + .data_19_V_q1(8'd0), + .data_19_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_we1), + .data_20_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_address0), + .data_20_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_ce0), + .data_20_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_d0), + .data_20_V_q0(layer7_out_20_V_q0), + .data_20_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_we0), + .data_20_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_address1), + .data_20_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_ce1), + .data_20_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_d1), + .data_20_V_q1(8'd0), + .data_20_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_we1), + .data_21_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_address0), + .data_21_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_ce0), + .data_21_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_d0), + .data_21_V_q0(layer7_out_21_V_q0), + .data_21_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_we0), + .data_21_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_address1), + .data_21_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_ce1), + .data_21_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_d1), + .data_21_V_q1(8'd0), + .data_21_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_we1), + .data_22_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_address0), + .data_22_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_ce0), + .data_22_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_d0), + .data_22_V_q0(layer7_out_22_V_q0), + .data_22_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_we0), + .data_22_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_address1), + .data_22_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_ce1), + .data_22_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_d1), + .data_22_V_q1(8'd0), + .data_22_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_we1), + .data_23_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_address0), + .data_23_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_ce0), + .data_23_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_d0), + .data_23_V_q0(layer7_out_23_V_q0), + .data_23_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_we0), + .data_23_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_address1), + .data_23_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_ce1), + .data_23_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_d1), + .data_23_V_q1(8'd0), + .data_23_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_we1), + .data_24_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_address0), + .data_24_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_ce0), + .data_24_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_d0), + .data_24_V_q0(layer7_out_24_V_q0), + .data_24_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_we0), + .data_24_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_address1), + .data_24_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_ce1), + .data_24_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_d1), + .data_24_V_q1(8'd0), + .data_24_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_we1), + .data_25_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_address0), + .data_25_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_ce0), + .data_25_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_d0), + .data_25_V_q0(layer7_out_25_V_q0), + .data_25_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_we0), + .data_25_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_address1), + .data_25_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_ce1), + .data_25_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_d1), + .data_25_V_q1(8'd0), + .data_25_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_we1), + .data_26_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_address0), + .data_26_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_ce0), + .data_26_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_d0), + .data_26_V_q0(layer7_out_26_V_q0), + .data_26_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_we0), + .data_26_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_address1), + .data_26_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_ce1), + .data_26_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_d1), + .data_26_V_q1(8'd0), + .data_26_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_we1), + .data_27_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_address0), + .data_27_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_ce0), + .data_27_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_d0), + .data_27_V_q0(layer7_out_27_V_q0), + .data_27_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_we0), + .data_27_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_address1), + .data_27_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_ce1), + .data_27_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_d1), + .data_27_V_q1(8'd0), + .data_27_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_we1), + .data_28_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_address0), + .data_28_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_ce0), + .data_28_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_d0), + .data_28_V_q0(layer7_out_28_V_q0), + .data_28_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_we0), + .data_28_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_address1), + .data_28_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_ce1), + .data_28_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_d1), + .data_28_V_q1(8'd0), + .data_28_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_we1), + .data_29_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_address0), + .data_29_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_ce0), + .data_29_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_d0), + .data_29_V_q0(layer7_out_29_V_q0), + .data_29_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_we0), + .data_29_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_address1), + .data_29_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_ce1), + .data_29_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_d1), + .data_29_V_q1(8'd0), + .data_29_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_we1), + .data_30_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_address0), + .data_30_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_ce0), + .data_30_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_d0), + .data_30_V_q0(layer7_out_30_V_q0), + .data_30_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_we0), + .data_30_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_address1), + .data_30_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_ce1), + .data_30_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_d1), + .data_30_V_q1(8'd0), + .data_30_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_we1), + .data_31_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_address0), + .data_31_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_ce0), + .data_31_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_d0), + .data_31_V_q0(layer7_out_31_V_q0), + .data_31_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_we0), + .data_31_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_address1), + .data_31_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_ce1), + .data_31_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_d1), + .data_31_V_q1(8'd0), + .data_31_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_we1), + .data_32_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_address0), + .data_32_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_ce0), + .data_32_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_d0), + .data_32_V_q0(layer7_out_32_V_q0), + .data_32_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_we0), + .data_32_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_address1), + .data_32_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_ce1), + .data_32_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_d1), + .data_32_V_q1(8'd0), + .data_32_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_we1), + .data_33_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_address0), + .data_33_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_ce0), + .data_33_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_d0), + .data_33_V_q0(layer7_out_33_V_q0), + .data_33_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_we0), + .data_33_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_address1), + .data_33_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_ce1), + .data_33_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_d1), + .data_33_V_q1(8'd0), + .data_33_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_we1), + .data_34_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_address0), + .data_34_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_ce0), + .data_34_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_d0), + .data_34_V_q0(layer7_out_34_V_q0), + .data_34_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_we0), + .data_34_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_address1), + .data_34_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_ce1), + .data_34_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_d1), + .data_34_V_q1(8'd0), + .data_34_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_we1), + .data_35_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_address0), + .data_35_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_ce0), + .data_35_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_d0), + .data_35_V_q0(layer7_out_35_V_q0), + .data_35_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_we0), + .data_35_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_address1), + .data_35_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_ce1), + .data_35_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_d1), + .data_35_V_q1(8'd0), + .data_35_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_we1), + .data_36_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_address0), + .data_36_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_ce0), + .data_36_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_d0), + .data_36_V_q0(layer7_out_36_V_q0), + .data_36_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_we0), + .data_36_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_address1), + .data_36_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_ce1), + .data_36_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_d1), + .data_36_V_q1(8'd0), + .data_36_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_we1), + .data_37_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_address0), + .data_37_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_ce0), + .data_37_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_d0), + .data_37_V_q0(layer7_out_37_V_q0), + .data_37_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_we0), + .data_37_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_address1), + .data_37_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_ce1), + .data_37_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_d1), + .data_37_V_q1(8'd0), + .data_37_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_we1), + .data_38_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_address0), + .data_38_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_ce0), + .data_38_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_d0), + .data_38_V_q0(layer7_out_38_V_q0), + .data_38_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_we0), + .data_38_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_address1), + .data_38_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_ce1), + .data_38_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_d1), + .data_38_V_q1(8'd0), + .data_38_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_we1), + .data_39_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_address0), + .data_39_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_ce0), + .data_39_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_d0), + .data_39_V_q0(layer7_out_39_V_q0), + .data_39_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_we0), + .data_39_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_address1), + .data_39_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_ce1), + .data_39_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_d1), + .data_39_V_q1(8'd0), + .data_39_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_we1), + .data_40_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_address0), + .data_40_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_ce0), + .data_40_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_d0), + .data_40_V_q0(layer7_out_40_V_q0), + .data_40_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_we0), + .data_40_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_address1), + .data_40_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_ce1), + .data_40_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_d1), + .data_40_V_q1(8'd0), + .data_40_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_we1), + .data_41_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_address0), + .data_41_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_ce0), + .data_41_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_d0), + .data_41_V_q0(layer7_out_41_V_q0), + .data_41_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_we0), + .data_41_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_address1), + .data_41_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_ce1), + .data_41_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_d1), + .data_41_V_q1(8'd0), + .data_41_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_we1), + .data_42_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_address0), + .data_42_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_ce0), + .data_42_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_d0), + .data_42_V_q0(layer7_out_42_V_q0), + .data_42_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_we0), + .data_42_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_address1), + .data_42_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_ce1), + .data_42_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_d1), + .data_42_V_q1(8'd0), + .data_42_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_we1), + .data_43_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_address0), + .data_43_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_ce0), + .data_43_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_d0), + .data_43_V_q0(layer7_out_43_V_q0), + .data_43_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_we0), + .data_43_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_address1), + .data_43_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_ce1), + .data_43_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_d1), + .data_43_V_q1(8'd0), + .data_43_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_we1), + .data_44_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_address0), + .data_44_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_ce0), + .data_44_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_d0), + .data_44_V_q0(layer7_out_44_V_q0), + .data_44_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_we0), + .data_44_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_address1), + .data_44_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_ce1), + .data_44_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_d1), + .data_44_V_q1(8'd0), + .data_44_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_we1), + .data_45_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_address0), + .data_45_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_ce0), + .data_45_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_d0), + .data_45_V_q0(layer7_out_45_V_q0), + .data_45_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_we0), + .data_45_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_address1), + .data_45_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_ce1), + .data_45_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_d1), + .data_45_V_q1(8'd0), + .data_45_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_we1), + .data_46_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_address0), + .data_46_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_ce0), + .data_46_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_d0), + .data_46_V_q0(layer7_out_46_V_q0), + .data_46_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_we0), + .data_46_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_address1), + .data_46_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_ce1), + .data_46_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_d1), + .data_46_V_q1(8'd0), + .data_46_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_we1), + .data_47_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_address0), + .data_47_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_ce0), + .data_47_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_d0), + .data_47_V_q0(layer7_out_47_V_q0), + .data_47_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_we0), + .data_47_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_address1), + .data_47_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_ce1), + .data_47_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_d1), + .data_47_V_q1(8'd0), + .data_47_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_we1), + .data_48_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_address0), + .data_48_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_ce0), + .data_48_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_d0), + .data_48_V_q0(layer7_out_48_V_q0), + .data_48_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_we0), + .data_48_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_address1), + .data_48_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_ce1), + .data_48_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_d1), + .data_48_V_q1(8'd0), + .data_48_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_we1), + .data_49_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_address0), + .data_49_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_ce0), + .data_49_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_d0), + .data_49_V_q0(layer7_out_49_V_q0), + .data_49_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_we0), + .data_49_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_address1), + .data_49_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_ce1), + .data_49_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_d1), + .data_49_V_q1(8'd0), + .data_49_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_we1), + .data_50_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_address0), + .data_50_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_ce0), + .data_50_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_d0), + .data_50_V_q0(layer7_out_50_V_q0), + .data_50_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_we0), + .data_50_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_address1), + .data_50_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_ce1), + .data_50_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_d1), + .data_50_V_q1(8'd0), + .data_50_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_we1), + .data_51_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_address0), + .data_51_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_ce0), + .data_51_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_d0), + .data_51_V_q0(layer7_out_51_V_q0), + .data_51_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_we0), + .data_51_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_address1), + .data_51_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_ce1), + .data_51_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_d1), + .data_51_V_q1(8'd0), + .data_51_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_we1), + .data_52_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_address0), + .data_52_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_ce0), + .data_52_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_d0), + .data_52_V_q0(layer7_out_52_V_q0), + .data_52_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_we0), + .data_52_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_address1), + .data_52_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_ce1), + .data_52_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_d1), + .data_52_V_q1(8'd0), + .data_52_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_we1), + .data_53_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_address0), + .data_53_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_ce0), + .data_53_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_d0), + .data_53_V_q0(layer7_out_53_V_q0), + .data_53_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_we0), + .data_53_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_address1), + .data_53_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_ce1), + .data_53_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_d1), + .data_53_V_q1(8'd0), + .data_53_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_we1), + .data_54_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_address0), + .data_54_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_ce0), + .data_54_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_d0), + .data_54_V_q0(layer7_out_54_V_q0), + .data_54_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_we0), + .data_54_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_address1), + .data_54_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_ce1), + .data_54_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_d1), + .data_54_V_q1(8'd0), + .data_54_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_we1), + .data_55_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_address0), + .data_55_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_ce0), + .data_55_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_d0), + .data_55_V_q0(layer7_out_55_V_q0), + .data_55_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_we0), + .data_55_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_address1), + .data_55_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_ce1), + .data_55_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_d1), + .data_55_V_q1(8'd0), + .data_55_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_we1), + .data_56_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_address0), + .data_56_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_ce0), + .data_56_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_d0), + .data_56_V_q0(layer7_out_56_V_q0), + .data_56_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_we0), + .data_56_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_address1), + .data_56_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_ce1), + .data_56_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_d1), + .data_56_V_q1(8'd0), + .data_56_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_we1), + .data_57_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_address0), + .data_57_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_ce0), + .data_57_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_d0), + .data_57_V_q0(layer7_out_57_V_q0), + .data_57_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_we0), + .data_57_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_address1), + .data_57_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_ce1), + .data_57_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_d1), + .data_57_V_q1(8'd0), + .data_57_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_we1), + .data_58_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_address0), + .data_58_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_ce0), + .data_58_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_d0), + .data_58_V_q0(layer7_out_58_V_q0), + .data_58_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_we0), + .data_58_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_address1), + .data_58_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_ce1), + .data_58_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_d1), + .data_58_V_q1(8'd0), + .data_58_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_we1), + .data_59_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_address0), + .data_59_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_ce0), + .data_59_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_d0), + .data_59_V_q0(layer7_out_59_V_q0), + .data_59_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_we0), + .data_59_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_address1), + .data_59_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_ce1), + .data_59_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_d1), + .data_59_V_q1(8'd0), + .data_59_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_we1), + .data_60_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_address0), + .data_60_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_ce0), + .data_60_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_d0), + .data_60_V_q0(layer7_out_60_V_q0), + .data_60_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_we0), + .data_60_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_address1), + .data_60_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_ce1), + .data_60_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_d1), + .data_60_V_q1(8'd0), + .data_60_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_we1), + .data_61_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_address0), + .data_61_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_ce0), + .data_61_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_d0), + .data_61_V_q0(layer7_out_61_V_q0), + .data_61_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_we0), + .data_61_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_address1), + .data_61_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_ce1), + .data_61_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_d1), + .data_61_V_q1(8'd0), + .data_61_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_we1), + .data_62_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_address0), + .data_62_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_ce0), + .data_62_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_d0), + .data_62_V_q0(layer7_out_62_V_q0), + .data_62_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_we0), + .data_62_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_address1), + .data_62_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_ce1), + .data_62_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_d1), + .data_62_V_q1(8'd0), + .data_62_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_we1), + .data_63_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_address0), + .data_63_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_ce0), + .data_63_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_d0), + .data_63_V_q0(layer7_out_63_V_q0), + .data_63_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_we0), + .data_63_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_address1), + .data_63_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_ce1), + .data_63_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_d1), + .data_63_V_q1(8'd0), + .data_63_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_we1), + .data_64_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_address0), + .data_64_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_ce0), + .data_64_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_d0), + .data_64_V_q0(layer7_out_64_V_q0), + .data_64_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_we0), + .data_64_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_address1), + .data_64_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_ce1), + .data_64_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_d1), + .data_64_V_q1(8'd0), + .data_64_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_we1), + .data_65_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_address0), + .data_65_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_ce0), + .data_65_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_d0), + .data_65_V_q0(layer7_out_65_V_q0), + .data_65_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_we0), + .data_65_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_address1), + .data_65_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_ce1), + .data_65_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_d1), + .data_65_V_q1(8'd0), + .data_65_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_we1), + .data_66_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_address0), + .data_66_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_ce0), + .data_66_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_d0), + .data_66_V_q0(layer7_out_66_V_q0), + .data_66_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_we0), + .data_66_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_address1), + .data_66_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_ce1), + .data_66_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_d1), + .data_66_V_q1(8'd0), + .data_66_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_we1), + .data_67_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_address0), + .data_67_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_ce0), + .data_67_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_d0), + .data_67_V_q0(layer7_out_67_V_q0), + .data_67_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_we0), + .data_67_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_address1), + .data_67_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_ce1), + .data_67_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_d1), + .data_67_V_q1(8'd0), + .data_67_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_we1), + .data_68_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_address0), + .data_68_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_ce0), + .data_68_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_d0), + .data_68_V_q0(layer7_out_68_V_q0), + .data_68_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_we0), + .data_68_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_address1), + .data_68_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_ce1), + .data_68_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_d1), + .data_68_V_q1(8'd0), + .data_68_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_we1), + .data_69_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_address0), + .data_69_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_ce0), + .data_69_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_d0), + .data_69_V_q0(layer7_out_69_V_q0), + .data_69_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_we0), + .data_69_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_address1), + .data_69_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_ce1), + .data_69_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_d1), + .data_69_V_q1(8'd0), + .data_69_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_we1), + .data_70_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_address0), + .data_70_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_ce0), + .data_70_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_d0), + .data_70_V_q0(layer7_out_70_V_q0), + .data_70_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_we0), + .data_70_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_address1), + .data_70_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_ce1), + .data_70_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_d1), + .data_70_V_q1(8'd0), + .data_70_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_we1), + .data_71_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_address0), + .data_71_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_ce0), + .data_71_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_d0), + .data_71_V_q0(layer7_out_71_V_q0), + .data_71_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_we0), + .data_71_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_address1), + .data_71_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_ce1), + .data_71_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_d1), + .data_71_V_q1(8'd0), + .data_71_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_we1), + .data_72_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_address0), + .data_72_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_ce0), + .data_72_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_d0), + .data_72_V_q0(layer7_out_72_V_q0), + .data_72_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_we0), + .data_72_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_address1), + .data_72_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_ce1), + .data_72_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_d1), + .data_72_V_q1(8'd0), + .data_72_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_we1), + .data_73_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_address0), + .data_73_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_ce0), + .data_73_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_d0), + .data_73_V_q0(layer7_out_73_V_q0), + .data_73_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_we0), + .data_73_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_address1), + .data_73_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_ce1), + .data_73_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_d1), + .data_73_V_q1(8'd0), + .data_73_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_we1), + .data_74_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_address0), + .data_74_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_ce0), + .data_74_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_d0), + .data_74_V_q0(layer7_out_74_V_q0), + .data_74_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_we0), + .data_74_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_address1), + .data_74_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_ce1), + .data_74_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_d1), + .data_74_V_q1(8'd0), + .data_74_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_we1), + .data_75_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_address0), + .data_75_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_ce0), + .data_75_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_d0), + .data_75_V_q0(layer7_out_75_V_q0), + .data_75_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_we0), + .data_75_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_address1), + .data_75_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_ce1), + .data_75_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_d1), + .data_75_V_q1(8'd0), + .data_75_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_we1), + .data_76_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_address0), + .data_76_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_ce0), + .data_76_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_d0), + .data_76_V_q0(layer7_out_76_V_q0), + .data_76_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_we0), + .data_76_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_address1), + .data_76_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_ce1), + .data_76_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_d1), + .data_76_V_q1(8'd0), + .data_76_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_we1), + .data_77_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_address0), + .data_77_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_ce0), + .data_77_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_d0), + .data_77_V_q0(layer7_out_77_V_q0), + .data_77_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_we0), + .data_77_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_address1), + .data_77_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_ce1), + .data_77_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_d1), + .data_77_V_q1(8'd0), + .data_77_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_we1), + .data_78_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_address0), + .data_78_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_ce0), + .data_78_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_d0), + .data_78_V_q0(layer7_out_78_V_q0), + .data_78_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_we0), + .data_78_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_address1), + .data_78_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_ce1), + .data_78_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_d1), + .data_78_V_q1(8'd0), + .data_78_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_we1), + .data_79_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_address0), + .data_79_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_ce0), + .data_79_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_d0), + .data_79_V_q0(layer7_out_79_V_q0), + .data_79_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_we0), + .data_79_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_address1), + .data_79_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_ce1), + .data_79_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_d1), + .data_79_V_q1(8'd0), + .data_79_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_we1), + .data_80_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_address0), + .data_80_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_ce0), + .data_80_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_d0), + .data_80_V_q0(layer7_out_80_V_q0), + .data_80_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_we0), + .data_80_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_address1), + .data_80_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_ce1), + .data_80_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_d1), + .data_80_V_q1(8'd0), + .data_80_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_we1), + .data_81_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_address0), + .data_81_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_ce0), + .data_81_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_d0), + .data_81_V_q0(layer7_out_81_V_q0), + .data_81_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_we0), + .data_81_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_address1), + .data_81_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_ce1), + .data_81_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_d1), + .data_81_V_q1(8'd0), + .data_81_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_we1), + .data_82_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_address0), + .data_82_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_ce0), + .data_82_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_d0), + .data_82_V_q0(layer7_out_82_V_q0), + .data_82_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_we0), + .data_82_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_address1), + .data_82_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_ce1), + .data_82_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_d1), + .data_82_V_q1(8'd0), + .data_82_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_we1), + .data_83_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_address0), + .data_83_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_ce0), + .data_83_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_d0), + .data_83_V_q0(layer7_out_83_V_q0), + .data_83_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_we0), + .data_83_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_address1), + .data_83_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_ce1), + .data_83_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_d1), + .data_83_V_q1(8'd0), + .data_83_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_we1), + .data_84_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_address0), + .data_84_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_ce0), + .data_84_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_d0), + .data_84_V_q0(layer7_out_84_V_q0), + .data_84_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_we0), + .data_84_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_address1), + .data_84_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_ce1), + .data_84_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_d1), + .data_84_V_q1(8'd0), + .data_84_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_we1), + .data_85_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_address0), + .data_85_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_ce0), + .data_85_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_d0), + .data_85_V_q0(layer7_out_85_V_q0), + .data_85_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_we0), + .data_85_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_address1), + .data_85_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_ce1), + .data_85_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_d1), + .data_85_V_q1(8'd0), + .data_85_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_we1), + .data_86_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_address0), + .data_86_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_ce0), + .data_86_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_d0), + .data_86_V_q0(layer7_out_86_V_q0), + .data_86_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_we0), + .data_86_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_address1), + .data_86_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_ce1), + .data_86_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_d1), + .data_86_V_q1(8'd0), + .data_86_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_we1), + .data_87_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_address0), + .data_87_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_ce0), + .data_87_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_d0), + .data_87_V_q0(layer7_out_87_V_q0), + .data_87_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_we0), + .data_87_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_address1), + .data_87_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_ce1), + .data_87_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_d1), + .data_87_V_q1(8'd0), + .data_87_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_we1), + .data_88_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_address0), + .data_88_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_ce0), + .data_88_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_d0), + .data_88_V_q0(layer7_out_88_V_q0), + .data_88_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_we0), + .data_88_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_address1), + .data_88_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_ce1), + .data_88_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_d1), + .data_88_V_q1(8'd0), + .data_88_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_we1), + .data_89_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_address0), + .data_89_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_ce0), + .data_89_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_d0), + .data_89_V_q0(layer7_out_89_V_q0), + .data_89_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_we0), + .data_89_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_address1), + .data_89_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_ce1), + .data_89_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_d1), + .data_89_V_q1(8'd0), + .data_89_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_we1), + .data_90_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_address0), + .data_90_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_ce0), + .data_90_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_d0), + .data_90_V_q0(layer7_out_90_V_q0), + .data_90_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_we0), + .data_90_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_address1), + .data_90_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_ce1), + .data_90_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_d1), + .data_90_V_q1(8'd0), + .data_90_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_we1), + .data_91_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_address0), + .data_91_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_ce0), + .data_91_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_d0), + .data_91_V_q0(layer7_out_91_V_q0), + .data_91_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_we0), + .data_91_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_address1), + .data_91_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_ce1), + .data_91_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_d1), + .data_91_V_q1(8'd0), + .data_91_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_we1), + .data_92_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_address0), + .data_92_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_ce0), + .data_92_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_d0), + .data_92_V_q0(layer7_out_92_V_q0), + .data_92_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_we0), + .data_92_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_address1), + .data_92_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_ce1), + .data_92_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_d1), + .data_92_V_q1(8'd0), + .data_92_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_we1), + .data_93_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_address0), + .data_93_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_ce0), + .data_93_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_d0), + .data_93_V_q0(layer7_out_93_V_q0), + .data_93_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_we0), + .data_93_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_address1), + .data_93_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_ce1), + .data_93_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_d1), + .data_93_V_q1(8'd0), + .data_93_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_we1), + .data_94_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_address0), + .data_94_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_ce0), + .data_94_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_d0), + .data_94_V_q0(layer7_out_94_V_q0), + .data_94_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_we0), + .data_94_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_address1), + .data_94_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_ce1), + .data_94_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_d1), + .data_94_V_q1(8'd0), + .data_94_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_we1), + .data_95_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_address0), + .data_95_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_ce0), + .data_95_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_d0), + .data_95_V_q0(layer7_out_95_V_q0), + .data_95_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_we0), + .data_95_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_address1), + .data_95_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_ce1), + .data_95_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_d1), + .data_95_V_q1(8'd0), + .data_95_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_we1), + .data_96_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_address0), + .data_96_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_ce0), + .data_96_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_d0), + .data_96_V_q0(layer7_out_96_V_q0), + .data_96_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_we0), + .data_96_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_address1), + .data_96_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_ce1), + .data_96_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_d1), + .data_96_V_q1(8'd0), + .data_96_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_we1), + .data_97_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_address0), + .data_97_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_ce0), + .data_97_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_d0), + .data_97_V_q0(layer7_out_97_V_q0), + .data_97_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_we0), + .data_97_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_address1), + .data_97_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_ce1), + .data_97_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_d1), + .data_97_V_q1(8'd0), + .data_97_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_we1), + .data_98_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_address0), + .data_98_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_ce0), + .data_98_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_d0), + .data_98_V_q0(layer7_out_98_V_q0), + .data_98_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_we0), + .data_98_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_address1), + .data_98_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_ce1), + .data_98_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_d1), + .data_98_V_q1(8'd0), + .data_98_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_we1), + .data_99_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_address0), + .data_99_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_ce0), + .data_99_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_d0), + .data_99_V_q0(layer7_out_99_V_q0), + .data_99_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_we0), + .data_99_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_address1), + .data_99_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_ce1), + .data_99_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_d1), + .data_99_V_q1(8'd0), + .data_99_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_we1), + .data_100_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_address0), + .data_100_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_ce0), + .data_100_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_d0), + .data_100_V_q0(layer7_out_100_V_q0), + .data_100_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_we0), + .data_100_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_address1), + .data_100_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_ce1), + .data_100_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_d1), + .data_100_V_q1(8'd0), + .data_100_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_we1), + .data_101_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_address0), + .data_101_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_ce0), + .data_101_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_d0), + .data_101_V_q0(layer7_out_101_V_q0), + .data_101_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_we0), + .data_101_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_address1), + .data_101_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_ce1), + .data_101_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_d1), + .data_101_V_q1(8'd0), + .data_101_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_we1), + .data_102_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_address0), + .data_102_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_ce0), + .data_102_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_d0), + .data_102_V_q0(layer7_out_102_V_q0), + .data_102_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_we0), + .data_102_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_address1), + .data_102_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_ce1), + .data_102_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_d1), + .data_102_V_q1(8'd0), + .data_102_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_we1), + .data_103_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_address0), + .data_103_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_ce0), + .data_103_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_d0), + .data_103_V_q0(layer7_out_103_V_q0), + .data_103_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_we0), + .data_103_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_address1), + .data_103_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_ce1), + .data_103_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_d1), + .data_103_V_q1(8'd0), + .data_103_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_we1), + .data_104_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_address0), + .data_104_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_ce0), + .data_104_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_d0), + .data_104_V_q0(layer7_out_104_V_q0), + .data_104_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_we0), + .data_104_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_address1), + .data_104_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_ce1), + .data_104_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_d1), + .data_104_V_q1(8'd0), + .data_104_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_we1), + .data_105_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_address0), + .data_105_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_ce0), + .data_105_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_d0), + .data_105_V_q0(layer7_out_105_V_q0), + .data_105_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_we0), + .data_105_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_address1), + .data_105_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_ce1), + .data_105_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_d1), + .data_105_V_q1(8'd0), + .data_105_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_we1), + .data_106_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_address0), + .data_106_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_ce0), + .data_106_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_d0), + .data_106_V_q0(layer7_out_106_V_q0), + .data_106_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_we0), + .data_106_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_address1), + .data_106_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_ce1), + .data_106_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_d1), + .data_106_V_q1(8'd0), + .data_106_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_we1), + .data_107_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_address0), + .data_107_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_ce0), + .data_107_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_d0), + .data_107_V_q0(layer7_out_107_V_q0), + .data_107_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_we0), + .data_107_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_address1), + .data_107_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_ce1), + .data_107_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_d1), + .data_107_V_q1(8'd0), + .data_107_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_we1), + .data_108_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_address0), + .data_108_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_ce0), + .data_108_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_d0), + .data_108_V_q0(layer7_out_108_V_q0), + .data_108_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_we0), + .data_108_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_address1), + .data_108_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_ce1), + .data_108_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_d1), + .data_108_V_q1(8'd0), + .data_108_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_we1), + .data_109_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_address0), + .data_109_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_ce0), + .data_109_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_d0), + .data_109_V_q0(layer7_out_109_V_q0), + .data_109_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_we0), + .data_109_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_address1), + .data_109_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_ce1), + .data_109_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_d1), + .data_109_V_q1(8'd0), + .data_109_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_we1), + .data_110_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_address0), + .data_110_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_ce0), + .data_110_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_d0), + .data_110_V_q0(layer7_out_110_V_q0), + .data_110_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_we0), + .data_110_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_address1), + .data_110_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_ce1), + .data_110_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_d1), + .data_110_V_q1(8'd0), + .data_110_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_we1), + .data_111_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_address0), + .data_111_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_ce0), + .data_111_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_d0), + .data_111_V_q0(layer7_out_111_V_q0), + .data_111_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_we0), + .data_111_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_address1), + .data_111_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_ce1), + .data_111_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_d1), + .data_111_V_q1(8'd0), + .data_111_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_we1), + .data_112_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_address0), + .data_112_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_ce0), + .data_112_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_d0), + .data_112_V_q0(layer7_out_112_V_q0), + .data_112_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_we0), + .data_112_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_address1), + .data_112_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_ce1), + .data_112_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_d1), + .data_112_V_q1(8'd0), + .data_112_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_we1), + .data_113_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_address0), + .data_113_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_ce0), + .data_113_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_d0), + .data_113_V_q0(layer7_out_113_V_q0), + .data_113_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_we0), + .data_113_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_address1), + .data_113_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_ce1), + .data_113_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_d1), + .data_113_V_q1(8'd0), + .data_113_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_we1), + .data_114_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_address0), + .data_114_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_ce0), + .data_114_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_d0), + .data_114_V_q0(layer7_out_114_V_q0), + .data_114_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_we0), + .data_114_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_address1), + .data_114_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_ce1), + .data_114_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_d1), + .data_114_V_q1(8'd0), + .data_114_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_we1), + .data_115_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_address0), + .data_115_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_ce0), + .data_115_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_d0), + .data_115_V_q0(layer7_out_115_V_q0), + .data_115_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_we0), + .data_115_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_address1), + .data_115_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_ce1), + .data_115_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_d1), + .data_115_V_q1(8'd0), + .data_115_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_we1), + .data_116_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_address0), + .data_116_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_ce0), + .data_116_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_d0), + .data_116_V_q0(layer7_out_116_V_q0), + .data_116_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_we0), + .data_116_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_address1), + .data_116_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_ce1), + .data_116_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_d1), + .data_116_V_q1(8'd0), + .data_116_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_we1), + .data_117_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_address0), + .data_117_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_ce0), + .data_117_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_d0), + .data_117_V_q0(layer7_out_117_V_q0), + .data_117_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_we0), + .data_117_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_address1), + .data_117_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_ce1), + .data_117_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_d1), + .data_117_V_q1(8'd0), + .data_117_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_we1), + .data_118_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_address0), + .data_118_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_ce0), + .data_118_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_d0), + .data_118_V_q0(layer7_out_118_V_q0), + .data_118_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_we0), + .data_118_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_address1), + .data_118_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_ce1), + .data_118_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_d1), + .data_118_V_q1(8'd0), + .data_118_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_we1), + .data_119_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_address0), + .data_119_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_ce0), + .data_119_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_d0), + .data_119_V_q0(layer7_out_119_V_q0), + .data_119_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_we0), + .data_119_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_address1), + .data_119_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_ce1), + .data_119_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_d1), + .data_119_V_q1(8'd0), + .data_119_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_we1), + .data_120_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_address0), + .data_120_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_ce0), + .data_120_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_d0), + .data_120_V_q0(layer7_out_120_V_q0), + .data_120_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_we0), + .data_120_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_address1), + .data_120_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_ce1), + .data_120_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_d1), + .data_120_V_q1(8'd0), + .data_120_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_we1), + .data_121_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_address0), + .data_121_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_ce0), + .data_121_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_d0), + .data_121_V_q0(layer7_out_121_V_q0), + .data_121_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_we0), + .data_121_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_address1), + .data_121_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_ce1), + .data_121_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_d1), + .data_121_V_q1(8'd0), + .data_121_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_we1), + .data_122_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_address0), + .data_122_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_ce0), + .data_122_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_d0), + .data_122_V_q0(layer7_out_122_V_q0), + .data_122_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_we0), + .data_122_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_address1), + .data_122_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_ce1), + .data_122_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_d1), + .data_122_V_q1(8'd0), + .data_122_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_we1), + .data_123_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_address0), + .data_123_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_ce0), + .data_123_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_d0), + .data_123_V_q0(layer7_out_123_V_q0), + .data_123_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_we0), + .data_123_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_address1), + .data_123_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_ce1), + .data_123_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_d1), + .data_123_V_q1(8'd0), + .data_123_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_we1), + .data_124_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_address0), + .data_124_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_ce0), + .data_124_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_d0), + .data_124_V_q0(layer7_out_124_V_q0), + .data_124_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_we0), + .data_124_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_address1), + .data_124_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_ce1), + .data_124_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_d1), + .data_124_V_q1(8'd0), + .data_124_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_we1), + .data_125_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_address0), + .data_125_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_ce0), + .data_125_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_d0), + .data_125_V_q0(layer7_out_125_V_q0), + .data_125_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_we0), + .data_125_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_address1), + .data_125_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_ce1), + .data_125_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_d1), + .data_125_V_q1(8'd0), + .data_125_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_we1), + .data_126_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_address0), + .data_126_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_ce0), + .data_126_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_d0), + .data_126_V_q0(layer7_out_126_V_q0), + .data_126_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_we0), + .data_126_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_address1), + .data_126_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_ce1), + .data_126_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_d1), + .data_126_V_q1(8'd0), + .data_126_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_we1), + .data_127_V_address0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_address0), + .data_127_V_ce0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_ce0), + .data_127_V_d0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_d0), + .data_127_V_q0(layer7_out_127_V_q0), + .data_127_V_we0(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_we0), + .data_127_V_address1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_address1), + .data_127_V_ce1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_ce1), + .data_127_V_d1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_d1), + .data_127_V_q1(8'd0), + .data_127_V_we1(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_we1), + .res_0_V(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_0_V), + .res_1_V(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_1_V), + .res_2_V(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_2_V), + .res_3_V(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_3_V), + .res_4_V(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_4_V), + .res_5_V(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_5_V), + .res_6_V(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_6_V), + .res_7_V(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_7_V), + .res_8_V(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_8_V), + .res_9_V(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_9_V), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_start), + .res_0_V_ap_vld(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_0_V_ap_vld), + .ap_done(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_done), + .res_1_V_ap_vld(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_1_V_ap_vld), + .res_2_V_ap_vld(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_2_V_ap_vld), + .res_3_V_ap_vld(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_3_V_ap_vld), + .res_4_V_ap_vld(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_4_V_ap_vld), + .res_5_V_ap_vld(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_5_V_ap_vld), + .res_6_V_ap_vld(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_6_V_ap_vld), + .res_7_V_ap_vld(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_7_V_ap_vld), + .res_8_V_ap_vld(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_8_V_ap_vld), + .res_9_V_ap_vld(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_9_V_ap_vld), + .ap_ready(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_ready), + .ap_idle(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_idle), + .ap_continue(grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_continue) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_start), + .ap_done(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_done), + .ap_idle(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_idle), + .ap_ready(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_ready), + .data_0_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_0_V_address0), + .data_0_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_0_V_ce0), + .data_0_V_q0(layer5_out_0_V_q0), + .data_1_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_1_V_address0), + .data_1_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_1_V_ce0), + .data_1_V_q0(layer5_out_1_V_q0), + .data_2_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_2_V_address0), + .data_2_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_2_V_ce0), + .data_2_V_q0(layer5_out_2_V_q0), + .data_3_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_3_V_address0), + .data_3_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_3_V_ce0), + .data_3_V_q0(layer5_out_3_V_q0), + .data_4_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_4_V_address0), + .data_4_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_4_V_ce0), + .data_4_V_q0(layer5_out_4_V_q0), + .data_5_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_5_V_address0), + .data_5_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_5_V_ce0), + .data_5_V_q0(layer5_out_5_V_q0), + .data_6_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_6_V_address0), + .data_6_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_6_V_ce0), + .data_6_V_q0(layer5_out_6_V_q0), + .data_7_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_7_V_address0), + .data_7_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_7_V_ce0), + .data_7_V_q0(layer5_out_7_V_q0), + .data_8_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_8_V_address0), + .data_8_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_8_V_ce0), + .data_8_V_q0(layer5_out_8_V_q0), + .data_9_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_9_V_address0), + .data_9_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_9_V_ce0), + .data_9_V_q0(layer5_out_9_V_q0), + .data_10_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_10_V_address0), + .data_10_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_10_V_ce0), + .data_10_V_q0(layer5_out_10_V_q0), + .data_11_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_11_V_address0), + .data_11_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_11_V_ce0), + .data_11_V_q0(layer5_out_11_V_q0), + .data_12_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_12_V_address0), + .data_12_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_12_V_ce0), + .data_12_V_q0(layer5_out_12_V_q0), + .data_13_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_13_V_address0), + .data_13_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_13_V_ce0), + .data_13_V_q0(layer5_out_13_V_q0), + .data_14_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_14_V_address0), + .data_14_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_14_V_ce0), + .data_14_V_q0(layer5_out_14_V_q0), + .data_15_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_15_V_address0), + .data_15_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_15_V_ce0), + .data_15_V_q0(layer5_out_15_V_q0), + .data_16_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_16_V_address0), + .data_16_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_16_V_ce0), + .data_16_V_q0(layer5_out_16_V_q0), + .data_17_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_17_V_address0), + .data_17_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_17_V_ce0), + .data_17_V_q0(layer5_out_17_V_q0), + .data_18_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_18_V_address0), + .data_18_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_18_V_ce0), + .data_18_V_q0(layer5_out_18_V_q0), + .data_19_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_19_V_address0), + .data_19_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_19_V_ce0), + .data_19_V_q0(layer5_out_19_V_q0), + .data_20_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_20_V_address0), + .data_20_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_20_V_ce0), + .data_20_V_q0(layer5_out_20_V_q0), + .data_21_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_21_V_address0), + .data_21_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_21_V_ce0), + .data_21_V_q0(layer5_out_21_V_q0), + .data_22_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_22_V_address0), + .data_22_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_22_V_ce0), + .data_22_V_q0(layer5_out_22_V_q0), + .data_23_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_23_V_address0), + .data_23_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_23_V_ce0), + .data_23_V_q0(layer5_out_23_V_q0), + .data_24_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_24_V_address0), + .data_24_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_24_V_ce0), + .data_24_V_q0(layer5_out_24_V_q0), + .data_25_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_25_V_address0), + .data_25_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_25_V_ce0), + .data_25_V_q0(layer5_out_25_V_q0), + .data_26_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_26_V_address0), + .data_26_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_26_V_ce0), + .data_26_V_q0(layer5_out_26_V_q0), + .data_27_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_27_V_address0), + .data_27_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_27_V_ce0), + .data_27_V_q0(layer5_out_27_V_q0), + .data_28_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_28_V_address0), + .data_28_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_28_V_ce0), + .data_28_V_q0(layer5_out_28_V_q0), + .data_29_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_29_V_address0), + .data_29_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_29_V_ce0), + .data_29_V_q0(layer5_out_29_V_q0), + .data_30_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_30_V_address0), + .data_30_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_30_V_ce0), + .data_30_V_q0(layer5_out_30_V_q0), + .data_31_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_31_V_address0), + .data_31_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_31_V_ce0), + .data_31_V_q0(layer5_out_31_V_q0), + .data_32_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_32_V_address0), + .data_32_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_32_V_ce0), + .data_32_V_q0(layer5_out_32_V_q0), + .data_33_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_33_V_address0), + .data_33_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_33_V_ce0), + .data_33_V_q0(layer5_out_33_V_q0), + .data_34_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_34_V_address0), + .data_34_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_34_V_ce0), + .data_34_V_q0(layer5_out_34_V_q0), + .data_35_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_35_V_address0), + .data_35_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_35_V_ce0), + .data_35_V_q0(layer5_out_35_V_q0), + .data_36_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_36_V_address0), + .data_36_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_36_V_ce0), + .data_36_V_q0(layer5_out_36_V_q0), + .data_37_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_37_V_address0), + .data_37_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_37_V_ce0), + .data_37_V_q0(layer5_out_37_V_q0), + .data_38_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_38_V_address0), + .data_38_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_38_V_ce0), + .data_38_V_q0(layer5_out_38_V_q0), + .data_39_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_39_V_address0), + .data_39_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_39_V_ce0), + .data_39_V_q0(layer5_out_39_V_q0), + .data_40_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_40_V_address0), + .data_40_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_40_V_ce0), + .data_40_V_q0(layer5_out_40_V_q0), + .data_41_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_41_V_address0), + .data_41_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_41_V_ce0), + .data_41_V_q0(layer5_out_41_V_q0), + .data_42_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_42_V_address0), + .data_42_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_42_V_ce0), + .data_42_V_q0(layer5_out_42_V_q0), + .data_43_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_43_V_address0), + .data_43_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_43_V_ce0), + .data_43_V_q0(layer5_out_43_V_q0), + .data_44_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_44_V_address0), + .data_44_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_44_V_ce0), + .data_44_V_q0(layer5_out_44_V_q0), + .data_45_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_45_V_address0), + .data_45_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_45_V_ce0), + .data_45_V_q0(layer5_out_45_V_q0), + .data_46_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_46_V_address0), + .data_46_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_46_V_ce0), + .data_46_V_q0(layer5_out_46_V_q0), + .data_47_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_47_V_address0), + .data_47_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_47_V_ce0), + .data_47_V_q0(layer5_out_47_V_q0), + .data_48_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_48_V_address0), + .data_48_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_48_V_ce0), + .data_48_V_q0(layer5_out_48_V_q0), + .data_49_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_49_V_address0), + .data_49_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_49_V_ce0), + .data_49_V_q0(layer5_out_49_V_q0), + .data_50_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_50_V_address0), + .data_50_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_50_V_ce0), + .data_50_V_q0(layer5_out_50_V_q0), + .data_51_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_51_V_address0), + .data_51_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_51_V_ce0), + .data_51_V_q0(layer5_out_51_V_q0), + .data_52_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_52_V_address0), + .data_52_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_52_V_ce0), + .data_52_V_q0(layer5_out_52_V_q0), + .data_53_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_53_V_address0), + .data_53_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_53_V_ce0), + .data_53_V_q0(layer5_out_53_V_q0), + .data_54_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_54_V_address0), + .data_54_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_54_V_ce0), + .data_54_V_q0(layer5_out_54_V_q0), + .data_55_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_55_V_address0), + .data_55_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_55_V_ce0), + .data_55_V_q0(layer5_out_55_V_q0), + .data_56_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_56_V_address0), + .data_56_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_56_V_ce0), + .data_56_V_q0(layer5_out_56_V_q0), + .data_57_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_57_V_address0), + .data_57_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_57_V_ce0), + .data_57_V_q0(layer5_out_57_V_q0), + .data_58_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_58_V_address0), + .data_58_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_58_V_ce0), + .data_58_V_q0(layer5_out_58_V_q0), + .data_59_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_59_V_address0), + .data_59_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_59_V_ce0), + .data_59_V_q0(layer5_out_59_V_q0), + .data_60_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_60_V_address0), + .data_60_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_60_V_ce0), + .data_60_V_q0(layer5_out_60_V_q0), + .data_61_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_61_V_address0), + .data_61_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_61_V_ce0), + .data_61_V_q0(layer5_out_61_V_q0), + .data_62_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_62_V_address0), + .data_62_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_62_V_ce0), + .data_62_V_q0(layer5_out_62_V_q0), + .data_63_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_63_V_address0), + .data_63_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_63_V_ce0), + .data_63_V_q0(layer5_out_63_V_q0), + .data_64_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_64_V_address0), + .data_64_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_64_V_ce0), + .data_64_V_q0(layer5_out_64_V_q0), + .data_65_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_65_V_address0), + .data_65_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_65_V_ce0), + .data_65_V_q0(layer5_out_65_V_q0), + .data_66_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_66_V_address0), + .data_66_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_66_V_ce0), + .data_66_V_q0(layer5_out_66_V_q0), + .data_67_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_67_V_address0), + .data_67_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_67_V_ce0), + .data_67_V_q0(layer5_out_67_V_q0), + .data_68_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_68_V_address0), + .data_68_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_68_V_ce0), + .data_68_V_q0(layer5_out_68_V_q0), + .data_69_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_69_V_address0), + .data_69_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_69_V_ce0), + .data_69_V_q0(layer5_out_69_V_q0), + .data_70_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_70_V_address0), + .data_70_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_70_V_ce0), + .data_70_V_q0(layer5_out_70_V_q0), + .data_71_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_71_V_address0), + .data_71_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_71_V_ce0), + .data_71_V_q0(layer5_out_71_V_q0), + .data_72_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_72_V_address0), + .data_72_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_72_V_ce0), + .data_72_V_q0(layer5_out_72_V_q0), + .data_73_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_73_V_address0), + .data_73_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_73_V_ce0), + .data_73_V_q0(layer5_out_73_V_q0), + .data_74_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_74_V_address0), + .data_74_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_74_V_ce0), + .data_74_V_q0(layer5_out_74_V_q0), + .data_75_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_75_V_address0), + .data_75_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_75_V_ce0), + .data_75_V_q0(layer5_out_75_V_q0), + .data_76_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_76_V_address0), + .data_76_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_76_V_ce0), + .data_76_V_q0(layer5_out_76_V_q0), + .data_77_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_77_V_address0), + .data_77_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_77_V_ce0), + .data_77_V_q0(layer5_out_77_V_q0), + .data_78_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_78_V_address0), + .data_78_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_78_V_ce0), + .data_78_V_q0(layer5_out_78_V_q0), + .data_79_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_79_V_address0), + .data_79_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_79_V_ce0), + .data_79_V_q0(layer5_out_79_V_q0), + .data_80_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_80_V_address0), + .data_80_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_80_V_ce0), + .data_80_V_q0(layer5_out_80_V_q0), + .data_81_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_81_V_address0), + .data_81_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_81_V_ce0), + .data_81_V_q0(layer5_out_81_V_q0), + .data_82_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_82_V_address0), + .data_82_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_82_V_ce0), + .data_82_V_q0(layer5_out_82_V_q0), + .data_83_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_83_V_address0), + .data_83_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_83_V_ce0), + .data_83_V_q0(layer5_out_83_V_q0), + .data_84_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_84_V_address0), + .data_84_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_84_V_ce0), + .data_84_V_q0(layer5_out_84_V_q0), + .data_85_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_85_V_address0), + .data_85_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_85_V_ce0), + .data_85_V_q0(layer5_out_85_V_q0), + .data_86_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_86_V_address0), + .data_86_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_86_V_ce0), + .data_86_V_q0(layer5_out_86_V_q0), + .data_87_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_87_V_address0), + .data_87_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_87_V_ce0), + .data_87_V_q0(layer5_out_87_V_q0), + .data_88_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_88_V_address0), + .data_88_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_88_V_ce0), + .data_88_V_q0(layer5_out_88_V_q0), + .data_89_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_89_V_address0), + .data_89_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_89_V_ce0), + .data_89_V_q0(layer5_out_89_V_q0), + .data_90_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_90_V_address0), + .data_90_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_90_V_ce0), + .data_90_V_q0(layer5_out_90_V_q0), + .data_91_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_91_V_address0), + .data_91_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_91_V_ce0), + .data_91_V_q0(layer5_out_91_V_q0), + .data_92_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_92_V_address0), + .data_92_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_92_V_ce0), + .data_92_V_q0(layer5_out_92_V_q0), + .data_93_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_93_V_address0), + .data_93_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_93_V_ce0), + .data_93_V_q0(layer5_out_93_V_q0), + .data_94_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_94_V_address0), + .data_94_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_94_V_ce0), + .data_94_V_q0(layer5_out_94_V_q0), + .data_95_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_95_V_address0), + .data_95_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_95_V_ce0), + .data_95_V_q0(layer5_out_95_V_q0), + .data_96_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_96_V_address0), + .data_96_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_96_V_ce0), + .data_96_V_q0(layer5_out_96_V_q0), + .data_97_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_97_V_address0), + .data_97_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_97_V_ce0), + .data_97_V_q0(layer5_out_97_V_q0), + .data_98_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_98_V_address0), + .data_98_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_98_V_ce0), + .data_98_V_q0(layer5_out_98_V_q0), + .data_99_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_99_V_address0), + .data_99_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_99_V_ce0), + .data_99_V_q0(layer5_out_99_V_q0), + .data_100_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_100_V_address0), + .data_100_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_100_V_ce0), + .data_100_V_q0(layer5_out_100_V_q0), + .data_101_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_101_V_address0), + .data_101_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_101_V_ce0), + .data_101_V_q0(layer5_out_101_V_q0), + .data_102_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_102_V_address0), + .data_102_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_102_V_ce0), + .data_102_V_q0(layer5_out_102_V_q0), + .data_103_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_103_V_address0), + .data_103_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_103_V_ce0), + .data_103_V_q0(layer5_out_103_V_q0), + .data_104_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_104_V_address0), + .data_104_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_104_V_ce0), + .data_104_V_q0(layer5_out_104_V_q0), + .data_105_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_105_V_address0), + .data_105_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_105_V_ce0), + .data_105_V_q0(layer5_out_105_V_q0), + .data_106_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_106_V_address0), + .data_106_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_106_V_ce0), + .data_106_V_q0(layer5_out_106_V_q0), + .data_107_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_107_V_address0), + .data_107_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_107_V_ce0), + .data_107_V_q0(layer5_out_107_V_q0), + .data_108_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_108_V_address0), + .data_108_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_108_V_ce0), + .data_108_V_q0(layer5_out_108_V_q0), + .data_109_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_109_V_address0), + .data_109_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_109_V_ce0), + .data_109_V_q0(layer5_out_109_V_q0), + .data_110_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_110_V_address0), + .data_110_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_110_V_ce0), + .data_110_V_q0(layer5_out_110_V_q0), + .data_111_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_111_V_address0), + .data_111_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_111_V_ce0), + .data_111_V_q0(layer5_out_111_V_q0), + .data_112_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_112_V_address0), + .data_112_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_112_V_ce0), + .data_112_V_q0(layer5_out_112_V_q0), + .data_113_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_113_V_address0), + .data_113_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_113_V_ce0), + .data_113_V_q0(layer5_out_113_V_q0), + .data_114_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_114_V_address0), + .data_114_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_114_V_ce0), + .data_114_V_q0(layer5_out_114_V_q0), + .data_115_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_115_V_address0), + .data_115_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_115_V_ce0), + .data_115_V_q0(layer5_out_115_V_q0), + .data_116_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_116_V_address0), + .data_116_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_116_V_ce0), + .data_116_V_q0(layer5_out_116_V_q0), + .data_117_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_117_V_address0), + .data_117_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_117_V_ce0), + .data_117_V_q0(layer5_out_117_V_q0), + .data_118_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_118_V_address0), + .data_118_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_118_V_ce0), + .data_118_V_q0(layer5_out_118_V_q0), + .data_119_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_119_V_address0), + .data_119_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_119_V_ce0), + .data_119_V_q0(layer5_out_119_V_q0), + .data_120_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_120_V_address0), + .data_120_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_120_V_ce0), + .data_120_V_q0(layer5_out_120_V_q0), + .data_121_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_121_V_address0), + .data_121_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_121_V_ce0), + .data_121_V_q0(layer5_out_121_V_q0), + .data_122_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_122_V_address0), + .data_122_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_122_V_ce0), + .data_122_V_q0(layer5_out_122_V_q0), + .data_123_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_123_V_address0), + .data_123_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_123_V_ce0), + .data_123_V_q0(layer5_out_123_V_q0), + .data_124_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_124_V_address0), + .data_124_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_124_V_ce0), + .data_124_V_q0(layer5_out_124_V_q0), + .data_125_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_125_V_address0), + .data_125_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_125_V_ce0), + .data_125_V_q0(layer5_out_125_V_q0), + .data_126_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_126_V_address0), + .data_126_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_126_V_ce0), + .data_126_V_q0(layer5_out_126_V_q0), + .data_127_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_127_V_address0), + .data_127_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_127_V_ce0), + .data_127_V_q0(layer5_out_127_V_q0), + .res_0_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_0_V_address0), + .res_0_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_0_V_ce0), + .res_0_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_0_V_we0), + .res_0_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_0_V_d0), + .res_1_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_1_V_address0), + .res_1_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_1_V_ce0), + .res_1_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_1_V_we0), + .res_1_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_1_V_d0), + .res_2_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_2_V_address0), + .res_2_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_2_V_ce0), + .res_2_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_2_V_we0), + .res_2_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_2_V_d0), + .res_3_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_3_V_address0), + .res_3_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_3_V_ce0), + .res_3_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_3_V_we0), + .res_3_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_3_V_d0), + .res_4_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_4_V_address0), + .res_4_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_4_V_ce0), + .res_4_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_4_V_we0), + .res_4_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_4_V_d0), + .res_5_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_5_V_address0), + .res_5_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_5_V_ce0), + .res_5_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_5_V_we0), + .res_5_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_5_V_d0), + .res_6_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_6_V_address0), + .res_6_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_6_V_ce0), + .res_6_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_6_V_we0), + .res_6_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_6_V_d0), + .res_7_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_7_V_address0), + .res_7_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_7_V_ce0), + .res_7_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_7_V_we0), + .res_7_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_7_V_d0), + .res_8_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_8_V_address0), + .res_8_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_8_V_ce0), + .res_8_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_8_V_we0), + .res_8_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_8_V_d0), + .res_9_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_9_V_address0), + .res_9_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_9_V_ce0), + .res_9_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_9_V_we0), + .res_9_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_9_V_d0), + .res_10_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_10_V_address0), + .res_10_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_10_V_ce0), + .res_10_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_10_V_we0), + .res_10_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_10_V_d0), + .res_11_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_11_V_address0), + .res_11_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_11_V_ce0), + .res_11_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_11_V_we0), + .res_11_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_11_V_d0), + .res_12_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_12_V_address0), + .res_12_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_12_V_ce0), + .res_12_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_12_V_we0), + .res_12_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_12_V_d0), + .res_13_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_13_V_address0), + .res_13_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_13_V_ce0), + .res_13_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_13_V_we0), + .res_13_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_13_V_d0), + .res_14_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_14_V_address0), + .res_14_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_14_V_ce0), + .res_14_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_14_V_we0), + .res_14_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_14_V_d0), + .res_15_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_15_V_address0), + .res_15_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_15_V_ce0), + .res_15_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_15_V_we0), + .res_15_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_15_V_d0), + .res_16_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_16_V_address0), + .res_16_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_16_V_ce0), + .res_16_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_16_V_we0), + .res_16_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_16_V_d0), + .res_17_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_17_V_address0), + .res_17_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_17_V_ce0), + .res_17_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_17_V_we0), + .res_17_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_17_V_d0), + .res_18_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_18_V_address0), + .res_18_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_18_V_ce0), + .res_18_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_18_V_we0), + .res_18_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_18_V_d0), + .res_19_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_19_V_address0), + .res_19_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_19_V_ce0), + .res_19_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_19_V_we0), + .res_19_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_19_V_d0), + .res_20_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_20_V_address0), + .res_20_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_20_V_ce0), + .res_20_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_20_V_we0), + .res_20_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_20_V_d0), + .res_21_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_21_V_address0), + .res_21_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_21_V_ce0), + .res_21_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_21_V_we0), + .res_21_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_21_V_d0), + .res_22_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_22_V_address0), + .res_22_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_22_V_ce0), + .res_22_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_22_V_we0), + .res_22_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_22_V_d0), + .res_23_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_23_V_address0), + .res_23_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_23_V_ce0), + .res_23_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_23_V_we0), + .res_23_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_23_V_d0), + .res_24_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_24_V_address0), + .res_24_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_24_V_ce0), + .res_24_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_24_V_we0), + .res_24_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_24_V_d0), + .res_25_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_25_V_address0), + .res_25_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_25_V_ce0), + .res_25_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_25_V_we0), + .res_25_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_25_V_d0), + .res_26_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_26_V_address0), + .res_26_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_26_V_ce0), + .res_26_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_26_V_we0), + .res_26_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_26_V_d0), + .res_27_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_27_V_address0), + .res_27_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_27_V_ce0), + .res_27_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_27_V_we0), + .res_27_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_27_V_d0), + .res_28_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_28_V_address0), + .res_28_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_28_V_ce0), + .res_28_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_28_V_we0), + .res_28_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_28_V_d0), + .res_29_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_29_V_address0), + .res_29_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_29_V_ce0), + .res_29_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_29_V_we0), + .res_29_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_29_V_d0), + .res_30_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_30_V_address0), + .res_30_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_30_V_ce0), + .res_30_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_30_V_we0), + .res_30_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_30_V_d0), + .res_31_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_31_V_address0), + .res_31_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_31_V_ce0), + .res_31_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_31_V_we0), + .res_31_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_31_V_d0), + .res_32_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_32_V_address0), + .res_32_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_32_V_ce0), + .res_32_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_32_V_we0), + .res_32_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_32_V_d0), + .res_33_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_33_V_address0), + .res_33_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_33_V_ce0), + .res_33_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_33_V_we0), + .res_33_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_33_V_d0), + .res_34_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_34_V_address0), + .res_34_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_34_V_ce0), + .res_34_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_34_V_we0), + .res_34_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_34_V_d0), + .res_35_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_35_V_address0), + .res_35_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_35_V_ce0), + .res_35_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_35_V_we0), + .res_35_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_35_V_d0), + .res_36_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_36_V_address0), + .res_36_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_36_V_ce0), + .res_36_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_36_V_we0), + .res_36_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_36_V_d0), + .res_37_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_37_V_address0), + .res_37_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_37_V_ce0), + .res_37_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_37_V_we0), + .res_37_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_37_V_d0), + .res_38_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_38_V_address0), + .res_38_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_38_V_ce0), + .res_38_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_38_V_we0), + .res_38_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_38_V_d0), + .res_39_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_39_V_address0), + .res_39_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_39_V_ce0), + .res_39_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_39_V_we0), + .res_39_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_39_V_d0), + .res_40_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_40_V_address0), + .res_40_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_40_V_ce0), + .res_40_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_40_V_we0), + .res_40_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_40_V_d0), + .res_41_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_41_V_address0), + .res_41_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_41_V_ce0), + .res_41_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_41_V_we0), + .res_41_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_41_V_d0), + .res_42_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_42_V_address0), + .res_42_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_42_V_ce0), + .res_42_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_42_V_we0), + .res_42_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_42_V_d0), + .res_43_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_43_V_address0), + .res_43_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_43_V_ce0), + .res_43_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_43_V_we0), + .res_43_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_43_V_d0), + .res_44_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_44_V_address0), + .res_44_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_44_V_ce0), + .res_44_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_44_V_we0), + .res_44_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_44_V_d0), + .res_45_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_45_V_address0), + .res_45_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_45_V_ce0), + .res_45_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_45_V_we0), + .res_45_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_45_V_d0), + .res_46_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_46_V_address0), + .res_46_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_46_V_ce0), + .res_46_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_46_V_we0), + .res_46_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_46_V_d0), + .res_47_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_47_V_address0), + .res_47_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_47_V_ce0), + .res_47_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_47_V_we0), + .res_47_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_47_V_d0), + .res_48_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_48_V_address0), + .res_48_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_48_V_ce0), + .res_48_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_48_V_we0), + .res_48_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_48_V_d0), + .res_49_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_49_V_address0), + .res_49_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_49_V_ce0), + .res_49_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_49_V_we0), + .res_49_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_49_V_d0), + .res_50_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_50_V_address0), + .res_50_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_50_V_ce0), + .res_50_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_50_V_we0), + .res_50_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_50_V_d0), + .res_51_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_51_V_address0), + .res_51_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_51_V_ce0), + .res_51_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_51_V_we0), + .res_51_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_51_V_d0), + .res_52_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_52_V_address0), + .res_52_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_52_V_ce0), + .res_52_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_52_V_we0), + .res_52_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_52_V_d0), + .res_53_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_53_V_address0), + .res_53_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_53_V_ce0), + .res_53_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_53_V_we0), + .res_53_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_53_V_d0), + .res_54_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_54_V_address0), + .res_54_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_54_V_ce0), + .res_54_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_54_V_we0), + .res_54_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_54_V_d0), + .res_55_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_55_V_address0), + .res_55_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_55_V_ce0), + .res_55_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_55_V_we0), + .res_55_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_55_V_d0), + .res_56_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_56_V_address0), + .res_56_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_56_V_ce0), + .res_56_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_56_V_we0), + .res_56_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_56_V_d0), + .res_57_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_57_V_address0), + .res_57_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_57_V_ce0), + .res_57_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_57_V_we0), + .res_57_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_57_V_d0), + .res_58_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_58_V_address0), + .res_58_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_58_V_ce0), + .res_58_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_58_V_we0), + .res_58_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_58_V_d0), + .res_59_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_59_V_address0), + .res_59_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_59_V_ce0), + .res_59_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_59_V_we0), + .res_59_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_59_V_d0), + .res_60_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_60_V_address0), + .res_60_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_60_V_ce0), + .res_60_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_60_V_we0), + .res_60_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_60_V_d0), + .res_61_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_61_V_address0), + .res_61_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_61_V_ce0), + .res_61_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_61_V_we0), + .res_61_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_61_V_d0), + .res_62_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_62_V_address0), + .res_62_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_62_V_ce0), + .res_62_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_62_V_we0), + .res_62_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_62_V_d0), + .res_63_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_63_V_address0), + .res_63_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_63_V_ce0), + .res_63_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_63_V_we0), + .res_63_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_63_V_d0), + .res_64_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_64_V_address0), + .res_64_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_64_V_ce0), + .res_64_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_64_V_we0), + .res_64_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_64_V_d0), + .res_65_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_65_V_address0), + .res_65_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_65_V_ce0), + .res_65_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_65_V_we0), + .res_65_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_65_V_d0), + .res_66_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_66_V_address0), + .res_66_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_66_V_ce0), + .res_66_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_66_V_we0), + .res_66_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_66_V_d0), + .res_67_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_67_V_address0), + .res_67_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_67_V_ce0), + .res_67_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_67_V_we0), + .res_67_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_67_V_d0), + .res_68_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_68_V_address0), + .res_68_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_68_V_ce0), + .res_68_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_68_V_we0), + .res_68_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_68_V_d0), + .res_69_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_69_V_address0), + .res_69_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_69_V_ce0), + .res_69_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_69_V_we0), + .res_69_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_69_V_d0), + .res_70_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_70_V_address0), + .res_70_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_70_V_ce0), + .res_70_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_70_V_we0), + .res_70_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_70_V_d0), + .res_71_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_71_V_address0), + .res_71_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_71_V_ce0), + .res_71_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_71_V_we0), + .res_71_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_71_V_d0), + .res_72_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_72_V_address0), + .res_72_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_72_V_ce0), + .res_72_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_72_V_we0), + .res_72_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_72_V_d0), + .res_73_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_73_V_address0), + .res_73_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_73_V_ce0), + .res_73_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_73_V_we0), + .res_73_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_73_V_d0), + .res_74_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_74_V_address0), + .res_74_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_74_V_ce0), + .res_74_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_74_V_we0), + .res_74_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_74_V_d0), + .res_75_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_75_V_address0), + .res_75_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_75_V_ce0), + .res_75_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_75_V_we0), + .res_75_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_75_V_d0), + .res_76_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_76_V_address0), + .res_76_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_76_V_ce0), + .res_76_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_76_V_we0), + .res_76_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_76_V_d0), + .res_77_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_77_V_address0), + .res_77_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_77_V_ce0), + .res_77_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_77_V_we0), + .res_77_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_77_V_d0), + .res_78_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_78_V_address0), + .res_78_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_78_V_ce0), + .res_78_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_78_V_we0), + .res_78_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_78_V_d0), + .res_79_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_79_V_address0), + .res_79_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_79_V_ce0), + .res_79_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_79_V_we0), + .res_79_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_79_V_d0), + .res_80_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_80_V_address0), + .res_80_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_80_V_ce0), + .res_80_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_80_V_we0), + .res_80_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_80_V_d0), + .res_81_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_81_V_address0), + .res_81_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_81_V_ce0), + .res_81_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_81_V_we0), + .res_81_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_81_V_d0), + .res_82_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_82_V_address0), + .res_82_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_82_V_ce0), + .res_82_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_82_V_we0), + .res_82_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_82_V_d0), + .res_83_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_83_V_address0), + .res_83_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_83_V_ce0), + .res_83_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_83_V_we0), + .res_83_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_83_V_d0), + .res_84_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_84_V_address0), + .res_84_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_84_V_ce0), + .res_84_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_84_V_we0), + .res_84_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_84_V_d0), + .res_85_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_85_V_address0), + .res_85_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_85_V_ce0), + .res_85_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_85_V_we0), + .res_85_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_85_V_d0), + .res_86_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_86_V_address0), + .res_86_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_86_V_ce0), + .res_86_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_86_V_we0), + .res_86_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_86_V_d0), + .res_87_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_87_V_address0), + .res_87_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_87_V_ce0), + .res_87_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_87_V_we0), + .res_87_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_87_V_d0), + .res_88_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_88_V_address0), + .res_88_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_88_V_ce0), + .res_88_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_88_V_we0), + .res_88_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_88_V_d0), + .res_89_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_89_V_address0), + .res_89_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_89_V_ce0), + .res_89_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_89_V_we0), + .res_89_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_89_V_d0), + .res_90_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_90_V_address0), + .res_90_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_90_V_ce0), + .res_90_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_90_V_we0), + .res_90_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_90_V_d0), + .res_91_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_91_V_address0), + .res_91_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_91_V_ce0), + .res_91_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_91_V_we0), + .res_91_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_91_V_d0), + .res_92_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_92_V_address0), + .res_92_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_92_V_ce0), + .res_92_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_92_V_we0), + .res_92_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_92_V_d0), + .res_93_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_93_V_address0), + .res_93_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_93_V_ce0), + .res_93_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_93_V_we0), + .res_93_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_93_V_d0), + .res_94_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_94_V_address0), + .res_94_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_94_V_ce0), + .res_94_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_94_V_we0), + .res_94_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_94_V_d0), + .res_95_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_95_V_address0), + .res_95_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_95_V_ce0), + .res_95_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_95_V_we0), + .res_95_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_95_V_d0), + .res_96_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_96_V_address0), + .res_96_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_96_V_ce0), + .res_96_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_96_V_we0), + .res_96_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_96_V_d0), + .res_97_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_97_V_address0), + .res_97_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_97_V_ce0), + .res_97_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_97_V_we0), + .res_97_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_97_V_d0), + .res_98_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_98_V_address0), + .res_98_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_98_V_ce0), + .res_98_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_98_V_we0), + .res_98_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_98_V_d0), + .res_99_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_99_V_address0), + .res_99_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_99_V_ce0), + .res_99_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_99_V_we0), + .res_99_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_99_V_d0), + .res_100_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_100_V_address0), + .res_100_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_100_V_ce0), + .res_100_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_100_V_we0), + .res_100_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_100_V_d0), + .res_101_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_101_V_address0), + .res_101_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_101_V_ce0), + .res_101_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_101_V_we0), + .res_101_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_101_V_d0), + .res_102_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_102_V_address0), + .res_102_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_102_V_ce0), + .res_102_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_102_V_we0), + .res_102_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_102_V_d0), + .res_103_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_103_V_address0), + .res_103_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_103_V_ce0), + .res_103_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_103_V_we0), + .res_103_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_103_V_d0), + .res_104_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_104_V_address0), + .res_104_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_104_V_ce0), + .res_104_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_104_V_we0), + .res_104_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_104_V_d0), + .res_105_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_105_V_address0), + .res_105_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_105_V_ce0), + .res_105_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_105_V_we0), + .res_105_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_105_V_d0), + .res_106_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_106_V_address0), + .res_106_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_106_V_ce0), + .res_106_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_106_V_we0), + .res_106_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_106_V_d0), + .res_107_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_107_V_address0), + .res_107_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_107_V_ce0), + .res_107_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_107_V_we0), + .res_107_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_107_V_d0), + .res_108_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_108_V_address0), + .res_108_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_108_V_ce0), + .res_108_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_108_V_we0), + .res_108_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_108_V_d0), + .res_109_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_109_V_address0), + .res_109_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_109_V_ce0), + .res_109_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_109_V_we0), + .res_109_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_109_V_d0), + .res_110_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_110_V_address0), + .res_110_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_110_V_ce0), + .res_110_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_110_V_we0), + .res_110_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_110_V_d0), + .res_111_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_111_V_address0), + .res_111_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_111_V_ce0), + .res_111_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_111_V_we0), + .res_111_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_111_V_d0), + .res_112_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_112_V_address0), + .res_112_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_112_V_ce0), + .res_112_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_112_V_we0), + .res_112_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_112_V_d0), + .res_113_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_113_V_address0), + .res_113_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_113_V_ce0), + .res_113_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_113_V_we0), + .res_113_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_113_V_d0), + .res_114_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_114_V_address0), + .res_114_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_114_V_ce0), + .res_114_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_114_V_we0), + .res_114_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_114_V_d0), + .res_115_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_115_V_address0), + .res_115_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_115_V_ce0), + .res_115_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_115_V_we0), + .res_115_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_115_V_d0), + .res_116_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_116_V_address0), + .res_116_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_116_V_ce0), + .res_116_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_116_V_we0), + .res_116_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_116_V_d0), + .res_117_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_117_V_address0), + .res_117_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_117_V_ce0), + .res_117_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_117_V_we0), + .res_117_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_117_V_d0), + .res_118_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_118_V_address0), + .res_118_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_118_V_ce0), + .res_118_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_118_V_we0), + .res_118_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_118_V_d0), + .res_119_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_119_V_address0), + .res_119_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_119_V_ce0), + .res_119_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_119_V_we0), + .res_119_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_119_V_d0), + .res_120_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_120_V_address0), + .res_120_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_120_V_ce0), + .res_120_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_120_V_we0), + .res_120_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_120_V_d0), + .res_121_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_121_V_address0), + .res_121_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_121_V_ce0), + .res_121_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_121_V_we0), + .res_121_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_121_V_d0), + .res_122_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_122_V_address0), + .res_122_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_122_V_ce0), + .res_122_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_122_V_we0), + .res_122_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_122_V_d0), + .res_123_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_123_V_address0), + .res_123_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_123_V_ce0), + .res_123_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_123_V_we0), + .res_123_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_123_V_d0), + .res_124_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_124_V_address0), + .res_124_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_124_V_ce0), + .res_124_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_124_V_we0), + .res_124_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_124_V_d0), + .res_125_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_125_V_address0), + .res_125_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_125_V_ce0), + .res_125_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_125_V_we0), + .res_125_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_125_V_d0), + .res_126_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_126_V_address0), + .res_126_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_126_V_ce0), + .res_126_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_126_V_we0), + .res_126_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_126_V_d0), + .res_127_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_127_V_address0), + .res_127_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_127_V_ce0), + .res_127_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_127_V_we0), + .res_127_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_127_V_d0) +); + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_start), + .ap_done(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_done), + .ap_idle(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_idle), + .ap_ready(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_ready), + .data_0_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_0_V_address0), + .data_0_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_0_V_ce0), + .data_0_V_q0(layer2_out_0_V_q0), + .data_1_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_1_V_address0), + .data_1_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_1_V_ce0), + .data_1_V_q0(layer2_out_1_V_q0), + .data_2_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_2_V_address0), + .data_2_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_2_V_ce0), + .data_2_V_q0(layer2_out_2_V_q0), + .data_3_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_3_V_address0), + .data_3_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_3_V_ce0), + .data_3_V_q0(layer2_out_3_V_q0), + .data_4_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_4_V_address0), + .data_4_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_4_V_ce0), + .data_4_V_q0(layer2_out_4_V_q0), + .data_5_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_5_V_address0), + .data_5_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_5_V_ce0), + .data_5_V_q0(layer2_out_5_V_q0), + .data_6_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_6_V_address0), + .data_6_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_6_V_ce0), + .data_6_V_q0(layer2_out_6_V_q0), + .data_7_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_7_V_address0), + .data_7_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_7_V_ce0), + .data_7_V_q0(layer2_out_7_V_q0), + .data_8_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_8_V_address0), + .data_8_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_8_V_ce0), + .data_8_V_q0(layer2_out_8_V_q0), + .data_9_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_9_V_address0), + .data_9_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_9_V_ce0), + .data_9_V_q0(layer2_out_9_V_q0), + .data_10_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_10_V_address0), + .data_10_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_10_V_ce0), + .data_10_V_q0(layer2_out_10_V_q0), + .data_11_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_11_V_address0), + .data_11_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_11_V_ce0), + .data_11_V_q0(layer2_out_11_V_q0), + .data_12_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_12_V_address0), + .data_12_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_12_V_ce0), + .data_12_V_q0(layer2_out_12_V_q0), + .data_13_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_13_V_address0), + .data_13_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_13_V_ce0), + .data_13_V_q0(layer2_out_13_V_q0), + .data_14_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_14_V_address0), + .data_14_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_14_V_ce0), + .data_14_V_q0(layer2_out_14_V_q0), + .data_15_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_15_V_address0), + .data_15_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_15_V_ce0), + .data_15_V_q0(layer2_out_15_V_q0), + .data_16_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_16_V_address0), + .data_16_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_16_V_ce0), + .data_16_V_q0(layer2_out_16_V_q0), + .data_17_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_17_V_address0), + .data_17_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_17_V_ce0), + .data_17_V_q0(layer2_out_17_V_q0), + .data_18_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_18_V_address0), + .data_18_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_18_V_ce0), + .data_18_V_q0(layer2_out_18_V_q0), + .data_19_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_19_V_address0), + .data_19_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_19_V_ce0), + .data_19_V_q0(layer2_out_19_V_q0), + .data_20_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_20_V_address0), + .data_20_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_20_V_ce0), + .data_20_V_q0(layer2_out_20_V_q0), + .data_21_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_21_V_address0), + .data_21_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_21_V_ce0), + .data_21_V_q0(layer2_out_21_V_q0), + .data_22_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_22_V_address0), + .data_22_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_22_V_ce0), + .data_22_V_q0(layer2_out_22_V_q0), + .data_23_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_23_V_address0), + .data_23_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_23_V_ce0), + .data_23_V_q0(layer2_out_23_V_q0), + .data_24_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_24_V_address0), + .data_24_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_24_V_ce0), + .data_24_V_q0(layer2_out_24_V_q0), + .data_25_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_25_V_address0), + .data_25_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_25_V_ce0), + .data_25_V_q0(layer2_out_25_V_q0), + .data_26_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_26_V_address0), + .data_26_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_26_V_ce0), + .data_26_V_q0(layer2_out_26_V_q0), + .data_27_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_27_V_address0), + .data_27_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_27_V_ce0), + .data_27_V_q0(layer2_out_27_V_q0), + .data_28_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_28_V_address0), + .data_28_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_28_V_ce0), + .data_28_V_q0(layer2_out_28_V_q0), + .data_29_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_29_V_address0), + .data_29_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_29_V_ce0), + .data_29_V_q0(layer2_out_29_V_q0), + .data_30_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_30_V_address0), + .data_30_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_30_V_ce0), + .data_30_V_q0(layer2_out_30_V_q0), + .data_31_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_31_V_address0), + .data_31_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_31_V_ce0), + .data_31_V_q0(layer2_out_31_V_q0), + .data_32_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_32_V_address0), + .data_32_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_32_V_ce0), + .data_32_V_q0(layer2_out_32_V_q0), + .data_33_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_33_V_address0), + .data_33_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_33_V_ce0), + .data_33_V_q0(layer2_out_33_V_q0), + .data_34_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_34_V_address0), + .data_34_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_34_V_ce0), + .data_34_V_q0(layer2_out_34_V_q0), + .data_35_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_35_V_address0), + .data_35_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_35_V_ce0), + .data_35_V_q0(layer2_out_35_V_q0), + .data_36_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_36_V_address0), + .data_36_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_36_V_ce0), + .data_36_V_q0(layer2_out_36_V_q0), + .data_37_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_37_V_address0), + .data_37_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_37_V_ce0), + .data_37_V_q0(layer2_out_37_V_q0), + .data_38_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_38_V_address0), + .data_38_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_38_V_ce0), + .data_38_V_q0(layer2_out_38_V_q0), + .data_39_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_39_V_address0), + .data_39_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_39_V_ce0), + .data_39_V_q0(layer2_out_39_V_q0), + .data_40_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_40_V_address0), + .data_40_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_40_V_ce0), + .data_40_V_q0(layer2_out_40_V_q0), + .data_41_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_41_V_address0), + .data_41_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_41_V_ce0), + .data_41_V_q0(layer2_out_41_V_q0), + .data_42_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_42_V_address0), + .data_42_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_42_V_ce0), + .data_42_V_q0(layer2_out_42_V_q0), + .data_43_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_43_V_address0), + .data_43_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_43_V_ce0), + .data_43_V_q0(layer2_out_43_V_q0), + .data_44_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_44_V_address0), + .data_44_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_44_V_ce0), + .data_44_V_q0(layer2_out_44_V_q0), + .data_45_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_45_V_address0), + .data_45_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_45_V_ce0), + .data_45_V_q0(layer2_out_45_V_q0), + .data_46_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_46_V_address0), + .data_46_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_46_V_ce0), + .data_46_V_q0(layer2_out_46_V_q0), + .data_47_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_47_V_address0), + .data_47_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_47_V_ce0), + .data_47_V_q0(layer2_out_47_V_q0), + .data_48_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_48_V_address0), + .data_48_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_48_V_ce0), + .data_48_V_q0(layer2_out_48_V_q0), + .data_49_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_49_V_address0), + .data_49_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_49_V_ce0), + .data_49_V_q0(layer2_out_49_V_q0), + .data_50_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_50_V_address0), + .data_50_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_50_V_ce0), + .data_50_V_q0(layer2_out_50_V_q0), + .data_51_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_51_V_address0), + .data_51_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_51_V_ce0), + .data_51_V_q0(layer2_out_51_V_q0), + .data_52_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_52_V_address0), + .data_52_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_52_V_ce0), + .data_52_V_q0(layer2_out_52_V_q0), + .data_53_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_53_V_address0), + .data_53_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_53_V_ce0), + .data_53_V_q0(layer2_out_53_V_q0), + .data_54_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_54_V_address0), + .data_54_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_54_V_ce0), + .data_54_V_q0(layer2_out_54_V_q0), + .data_55_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_55_V_address0), + .data_55_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_55_V_ce0), + .data_55_V_q0(layer2_out_55_V_q0), + .data_56_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_56_V_address0), + .data_56_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_56_V_ce0), + .data_56_V_q0(layer2_out_56_V_q0), + .data_57_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_57_V_address0), + .data_57_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_57_V_ce0), + .data_57_V_q0(layer2_out_57_V_q0), + .data_58_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_58_V_address0), + .data_58_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_58_V_ce0), + .data_58_V_q0(layer2_out_58_V_q0), + .data_59_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_59_V_address0), + .data_59_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_59_V_ce0), + .data_59_V_q0(layer2_out_59_V_q0), + .data_60_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_60_V_address0), + .data_60_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_60_V_ce0), + .data_60_V_q0(layer2_out_60_V_q0), + .data_61_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_61_V_address0), + .data_61_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_61_V_ce0), + .data_61_V_q0(layer2_out_61_V_q0), + .data_62_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_62_V_address0), + .data_62_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_62_V_ce0), + .data_62_V_q0(layer2_out_62_V_q0), + .data_63_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_63_V_address0), + .data_63_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_63_V_ce0), + .data_63_V_q0(layer2_out_63_V_q0), + .data_64_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_64_V_address0), + .data_64_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_64_V_ce0), + .data_64_V_q0(layer2_out_64_V_q0), + .data_65_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_65_V_address0), + .data_65_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_65_V_ce0), + .data_65_V_q0(layer2_out_65_V_q0), + .data_66_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_66_V_address0), + .data_66_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_66_V_ce0), + .data_66_V_q0(layer2_out_66_V_q0), + .data_67_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_67_V_address0), + .data_67_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_67_V_ce0), + .data_67_V_q0(layer2_out_67_V_q0), + .data_68_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_68_V_address0), + .data_68_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_68_V_ce0), + .data_68_V_q0(layer2_out_68_V_q0), + .data_69_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_69_V_address0), + .data_69_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_69_V_ce0), + .data_69_V_q0(layer2_out_69_V_q0), + .data_70_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_70_V_address0), + .data_70_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_70_V_ce0), + .data_70_V_q0(layer2_out_70_V_q0), + .data_71_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_71_V_address0), + .data_71_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_71_V_ce0), + .data_71_V_q0(layer2_out_71_V_q0), + .data_72_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_72_V_address0), + .data_72_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_72_V_ce0), + .data_72_V_q0(layer2_out_72_V_q0), + .data_73_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_73_V_address0), + .data_73_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_73_V_ce0), + .data_73_V_q0(layer2_out_73_V_q0), + .data_74_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_74_V_address0), + .data_74_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_74_V_ce0), + .data_74_V_q0(layer2_out_74_V_q0), + .data_75_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_75_V_address0), + .data_75_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_75_V_ce0), + .data_75_V_q0(layer2_out_75_V_q0), + .data_76_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_76_V_address0), + .data_76_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_76_V_ce0), + .data_76_V_q0(layer2_out_76_V_q0), + .data_77_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_77_V_address0), + .data_77_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_77_V_ce0), + .data_77_V_q0(layer2_out_77_V_q0), + .data_78_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_78_V_address0), + .data_78_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_78_V_ce0), + .data_78_V_q0(layer2_out_78_V_q0), + .data_79_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_79_V_address0), + .data_79_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_79_V_ce0), + .data_79_V_q0(layer2_out_79_V_q0), + .data_80_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_80_V_address0), + .data_80_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_80_V_ce0), + .data_80_V_q0(layer2_out_80_V_q0), + .data_81_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_81_V_address0), + .data_81_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_81_V_ce0), + .data_81_V_q0(layer2_out_81_V_q0), + .data_82_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_82_V_address0), + .data_82_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_82_V_ce0), + .data_82_V_q0(layer2_out_82_V_q0), + .data_83_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_83_V_address0), + .data_83_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_83_V_ce0), + .data_83_V_q0(layer2_out_83_V_q0), + .data_84_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_84_V_address0), + .data_84_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_84_V_ce0), + .data_84_V_q0(layer2_out_84_V_q0), + .data_85_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_85_V_address0), + .data_85_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_85_V_ce0), + .data_85_V_q0(layer2_out_85_V_q0), + .data_86_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_86_V_address0), + .data_86_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_86_V_ce0), + .data_86_V_q0(layer2_out_86_V_q0), + .data_87_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_87_V_address0), + .data_87_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_87_V_ce0), + .data_87_V_q0(layer2_out_87_V_q0), + .data_88_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_88_V_address0), + .data_88_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_88_V_ce0), + .data_88_V_q0(layer2_out_88_V_q0), + .data_89_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_89_V_address0), + .data_89_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_89_V_ce0), + .data_89_V_q0(layer2_out_89_V_q0), + .data_90_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_90_V_address0), + .data_90_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_90_V_ce0), + .data_90_V_q0(layer2_out_90_V_q0), + .data_91_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_91_V_address0), + .data_91_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_91_V_ce0), + .data_91_V_q0(layer2_out_91_V_q0), + .data_92_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_92_V_address0), + .data_92_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_92_V_ce0), + .data_92_V_q0(layer2_out_92_V_q0), + .data_93_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_93_V_address0), + .data_93_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_93_V_ce0), + .data_93_V_q0(layer2_out_93_V_q0), + .data_94_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_94_V_address0), + .data_94_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_94_V_ce0), + .data_94_V_q0(layer2_out_94_V_q0), + .data_95_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_95_V_address0), + .data_95_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_95_V_ce0), + .data_95_V_q0(layer2_out_95_V_q0), + .data_96_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_96_V_address0), + .data_96_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_96_V_ce0), + .data_96_V_q0(layer2_out_96_V_q0), + .data_97_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_97_V_address0), + .data_97_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_97_V_ce0), + .data_97_V_q0(layer2_out_97_V_q0), + .data_98_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_98_V_address0), + .data_98_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_98_V_ce0), + .data_98_V_q0(layer2_out_98_V_q0), + .data_99_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_99_V_address0), + .data_99_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_99_V_ce0), + .data_99_V_q0(layer2_out_99_V_q0), + .data_100_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_100_V_address0), + .data_100_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_100_V_ce0), + .data_100_V_q0(layer2_out_100_V_q0), + .data_101_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_101_V_address0), + .data_101_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_101_V_ce0), + .data_101_V_q0(layer2_out_101_V_q0), + .data_102_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_102_V_address0), + .data_102_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_102_V_ce0), + .data_102_V_q0(layer2_out_102_V_q0), + .data_103_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_103_V_address0), + .data_103_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_103_V_ce0), + .data_103_V_q0(layer2_out_103_V_q0), + .data_104_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_104_V_address0), + .data_104_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_104_V_ce0), + .data_104_V_q0(layer2_out_104_V_q0), + .data_105_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_105_V_address0), + .data_105_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_105_V_ce0), + .data_105_V_q0(layer2_out_105_V_q0), + .data_106_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_106_V_address0), + .data_106_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_106_V_ce0), + .data_106_V_q0(layer2_out_106_V_q0), + .data_107_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_107_V_address0), + .data_107_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_107_V_ce0), + .data_107_V_q0(layer2_out_107_V_q0), + .data_108_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_108_V_address0), + .data_108_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_108_V_ce0), + .data_108_V_q0(layer2_out_108_V_q0), + .data_109_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_109_V_address0), + .data_109_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_109_V_ce0), + .data_109_V_q0(layer2_out_109_V_q0), + .data_110_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_110_V_address0), + .data_110_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_110_V_ce0), + .data_110_V_q0(layer2_out_110_V_q0), + .data_111_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_111_V_address0), + .data_111_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_111_V_ce0), + .data_111_V_q0(layer2_out_111_V_q0), + .data_112_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_112_V_address0), + .data_112_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_112_V_ce0), + .data_112_V_q0(layer2_out_112_V_q0), + .data_113_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_113_V_address0), + .data_113_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_113_V_ce0), + .data_113_V_q0(layer2_out_113_V_q0), + .data_114_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_114_V_address0), + .data_114_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_114_V_ce0), + .data_114_V_q0(layer2_out_114_V_q0), + .data_115_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_115_V_address0), + .data_115_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_115_V_ce0), + .data_115_V_q0(layer2_out_115_V_q0), + .data_116_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_116_V_address0), + .data_116_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_116_V_ce0), + .data_116_V_q0(layer2_out_116_V_q0), + .data_117_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_117_V_address0), + .data_117_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_117_V_ce0), + .data_117_V_q0(layer2_out_117_V_q0), + .data_118_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_118_V_address0), + .data_118_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_118_V_ce0), + .data_118_V_q0(layer2_out_118_V_q0), + .data_119_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_119_V_address0), + .data_119_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_119_V_ce0), + .data_119_V_q0(layer2_out_119_V_q0), + .data_120_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_120_V_address0), + .data_120_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_120_V_ce0), + .data_120_V_q0(layer2_out_120_V_q0), + .data_121_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_121_V_address0), + .data_121_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_121_V_ce0), + .data_121_V_q0(layer2_out_121_V_q0), + .data_122_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_122_V_address0), + .data_122_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_122_V_ce0), + .data_122_V_q0(layer2_out_122_V_q0), + .data_123_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_123_V_address0), + .data_123_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_123_V_ce0), + .data_123_V_q0(layer2_out_123_V_q0), + .data_124_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_124_V_address0), + .data_124_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_124_V_ce0), + .data_124_V_q0(layer2_out_124_V_q0), + .data_125_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_125_V_address0), + .data_125_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_125_V_ce0), + .data_125_V_q0(layer2_out_125_V_q0), + .data_126_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_126_V_address0), + .data_126_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_126_V_ce0), + .data_126_V_q0(layer2_out_126_V_q0), + .data_127_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_127_V_address0), + .data_127_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_127_V_ce0), + .data_127_V_q0(layer2_out_127_V_q0), + .res_0_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_0_V_address0), + .res_0_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_0_V_ce0), + .res_0_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_0_V_we0), + .res_0_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_0_V_d0), + .res_1_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_1_V_address0), + .res_1_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_1_V_ce0), + .res_1_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_1_V_we0), + .res_1_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_1_V_d0), + .res_2_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_2_V_address0), + .res_2_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_2_V_ce0), + .res_2_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_2_V_we0), + .res_2_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_2_V_d0), + .res_3_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_3_V_address0), + .res_3_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_3_V_ce0), + .res_3_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_3_V_we0), + .res_3_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_3_V_d0), + .res_4_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_4_V_address0), + .res_4_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_4_V_ce0), + .res_4_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_4_V_we0), + .res_4_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_4_V_d0), + .res_5_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_5_V_address0), + .res_5_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_5_V_ce0), + .res_5_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_5_V_we0), + .res_5_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_5_V_d0), + .res_6_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_6_V_address0), + .res_6_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_6_V_ce0), + .res_6_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_6_V_we0), + .res_6_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_6_V_d0), + .res_7_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_7_V_address0), + .res_7_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_7_V_ce0), + .res_7_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_7_V_we0), + .res_7_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_7_V_d0), + .res_8_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_8_V_address0), + .res_8_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_8_V_ce0), + .res_8_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_8_V_we0), + .res_8_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_8_V_d0), + .res_9_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_9_V_address0), + .res_9_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_9_V_ce0), + .res_9_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_9_V_we0), + .res_9_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_9_V_d0), + .res_10_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_10_V_address0), + .res_10_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_10_V_ce0), + .res_10_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_10_V_we0), + .res_10_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_10_V_d0), + .res_11_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_11_V_address0), + .res_11_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_11_V_ce0), + .res_11_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_11_V_we0), + .res_11_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_11_V_d0), + .res_12_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_12_V_address0), + .res_12_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_12_V_ce0), + .res_12_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_12_V_we0), + .res_12_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_12_V_d0), + .res_13_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_13_V_address0), + .res_13_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_13_V_ce0), + .res_13_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_13_V_we0), + .res_13_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_13_V_d0), + .res_14_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_14_V_address0), + .res_14_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_14_V_ce0), + .res_14_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_14_V_we0), + .res_14_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_14_V_d0), + .res_15_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_15_V_address0), + .res_15_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_15_V_ce0), + .res_15_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_15_V_we0), + .res_15_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_15_V_d0), + .res_16_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_16_V_address0), + .res_16_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_16_V_ce0), + .res_16_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_16_V_we0), + .res_16_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_16_V_d0), + .res_17_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_17_V_address0), + .res_17_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_17_V_ce0), + .res_17_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_17_V_we0), + .res_17_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_17_V_d0), + .res_18_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_18_V_address0), + .res_18_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_18_V_ce0), + .res_18_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_18_V_we0), + .res_18_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_18_V_d0), + .res_19_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_19_V_address0), + .res_19_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_19_V_ce0), + .res_19_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_19_V_we0), + .res_19_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_19_V_d0), + .res_20_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_20_V_address0), + .res_20_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_20_V_ce0), + .res_20_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_20_V_we0), + .res_20_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_20_V_d0), + .res_21_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_21_V_address0), + .res_21_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_21_V_ce0), + .res_21_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_21_V_we0), + .res_21_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_21_V_d0), + .res_22_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_22_V_address0), + .res_22_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_22_V_ce0), + .res_22_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_22_V_we0), + .res_22_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_22_V_d0), + .res_23_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_23_V_address0), + .res_23_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_23_V_ce0), + .res_23_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_23_V_we0), + .res_23_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_23_V_d0), + .res_24_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_24_V_address0), + .res_24_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_24_V_ce0), + .res_24_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_24_V_we0), + .res_24_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_24_V_d0), + .res_25_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_25_V_address0), + .res_25_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_25_V_ce0), + .res_25_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_25_V_we0), + .res_25_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_25_V_d0), + .res_26_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_26_V_address0), + .res_26_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_26_V_ce0), + .res_26_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_26_V_we0), + .res_26_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_26_V_d0), + .res_27_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_27_V_address0), + .res_27_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_27_V_ce0), + .res_27_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_27_V_we0), + .res_27_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_27_V_d0), + .res_28_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_28_V_address0), + .res_28_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_28_V_ce0), + .res_28_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_28_V_we0), + .res_28_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_28_V_d0), + .res_29_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_29_V_address0), + .res_29_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_29_V_ce0), + .res_29_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_29_V_we0), + .res_29_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_29_V_d0), + .res_30_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_30_V_address0), + .res_30_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_30_V_ce0), + .res_30_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_30_V_we0), + .res_30_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_30_V_d0), + .res_31_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_31_V_address0), + .res_31_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_31_V_ce0), + .res_31_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_31_V_we0), + .res_31_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_31_V_d0), + .res_32_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_32_V_address0), + .res_32_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_32_V_ce0), + .res_32_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_32_V_we0), + .res_32_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_32_V_d0), + .res_33_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_33_V_address0), + .res_33_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_33_V_ce0), + .res_33_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_33_V_we0), + .res_33_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_33_V_d0), + .res_34_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_34_V_address0), + .res_34_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_34_V_ce0), + .res_34_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_34_V_we0), + .res_34_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_34_V_d0), + .res_35_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_35_V_address0), + .res_35_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_35_V_ce0), + .res_35_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_35_V_we0), + .res_35_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_35_V_d0), + .res_36_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_36_V_address0), + .res_36_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_36_V_ce0), + .res_36_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_36_V_we0), + .res_36_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_36_V_d0), + .res_37_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_37_V_address0), + .res_37_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_37_V_ce0), + .res_37_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_37_V_we0), + .res_37_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_37_V_d0), + .res_38_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_38_V_address0), + .res_38_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_38_V_ce0), + .res_38_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_38_V_we0), + .res_38_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_38_V_d0), + .res_39_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_39_V_address0), + .res_39_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_39_V_ce0), + .res_39_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_39_V_we0), + .res_39_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_39_V_d0), + .res_40_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_40_V_address0), + .res_40_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_40_V_ce0), + .res_40_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_40_V_we0), + .res_40_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_40_V_d0), + .res_41_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_41_V_address0), + .res_41_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_41_V_ce0), + .res_41_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_41_V_we0), + .res_41_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_41_V_d0), + .res_42_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_42_V_address0), + .res_42_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_42_V_ce0), + .res_42_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_42_V_we0), + .res_42_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_42_V_d0), + .res_43_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_43_V_address0), + .res_43_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_43_V_ce0), + .res_43_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_43_V_we0), + .res_43_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_43_V_d0), + .res_44_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_44_V_address0), + .res_44_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_44_V_ce0), + .res_44_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_44_V_we0), + .res_44_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_44_V_d0), + .res_45_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_45_V_address0), + .res_45_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_45_V_ce0), + .res_45_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_45_V_we0), + .res_45_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_45_V_d0), + .res_46_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_46_V_address0), + .res_46_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_46_V_ce0), + .res_46_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_46_V_we0), + .res_46_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_46_V_d0), + .res_47_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_47_V_address0), + .res_47_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_47_V_ce0), + .res_47_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_47_V_we0), + .res_47_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_47_V_d0), + .res_48_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_48_V_address0), + .res_48_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_48_V_ce0), + .res_48_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_48_V_we0), + .res_48_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_48_V_d0), + .res_49_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_49_V_address0), + .res_49_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_49_V_ce0), + .res_49_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_49_V_we0), + .res_49_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_49_V_d0), + .res_50_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_50_V_address0), + .res_50_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_50_V_ce0), + .res_50_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_50_V_we0), + .res_50_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_50_V_d0), + .res_51_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_51_V_address0), + .res_51_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_51_V_ce0), + .res_51_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_51_V_we0), + .res_51_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_51_V_d0), + .res_52_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_52_V_address0), + .res_52_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_52_V_ce0), + .res_52_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_52_V_we0), + .res_52_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_52_V_d0), + .res_53_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_53_V_address0), + .res_53_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_53_V_ce0), + .res_53_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_53_V_we0), + .res_53_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_53_V_d0), + .res_54_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_54_V_address0), + .res_54_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_54_V_ce0), + .res_54_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_54_V_we0), + .res_54_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_54_V_d0), + .res_55_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_55_V_address0), + .res_55_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_55_V_ce0), + .res_55_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_55_V_we0), + .res_55_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_55_V_d0), + .res_56_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_56_V_address0), + .res_56_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_56_V_ce0), + .res_56_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_56_V_we0), + .res_56_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_56_V_d0), + .res_57_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_57_V_address0), + .res_57_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_57_V_ce0), + .res_57_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_57_V_we0), + .res_57_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_57_V_d0), + .res_58_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_58_V_address0), + .res_58_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_58_V_ce0), + .res_58_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_58_V_we0), + .res_58_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_58_V_d0), + .res_59_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_59_V_address0), + .res_59_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_59_V_ce0), + .res_59_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_59_V_we0), + .res_59_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_59_V_d0), + .res_60_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_60_V_address0), + .res_60_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_60_V_ce0), + .res_60_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_60_V_we0), + .res_60_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_60_V_d0), + .res_61_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_61_V_address0), + .res_61_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_61_V_ce0), + .res_61_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_61_V_we0), + .res_61_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_61_V_d0), + .res_62_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_62_V_address0), + .res_62_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_62_V_ce0), + .res_62_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_62_V_we0), + .res_62_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_62_V_d0), + .res_63_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_63_V_address0), + .res_63_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_63_V_ce0), + .res_63_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_63_V_we0), + .res_63_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_63_V_d0), + .res_64_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_64_V_address0), + .res_64_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_64_V_ce0), + .res_64_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_64_V_we0), + .res_64_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_64_V_d0), + .res_65_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_65_V_address0), + .res_65_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_65_V_ce0), + .res_65_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_65_V_we0), + .res_65_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_65_V_d0), + .res_66_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_66_V_address0), + .res_66_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_66_V_ce0), + .res_66_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_66_V_we0), + .res_66_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_66_V_d0), + .res_67_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_67_V_address0), + .res_67_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_67_V_ce0), + .res_67_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_67_V_we0), + .res_67_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_67_V_d0), + .res_68_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_68_V_address0), + .res_68_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_68_V_ce0), + .res_68_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_68_V_we0), + .res_68_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_68_V_d0), + .res_69_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_69_V_address0), + .res_69_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_69_V_ce0), + .res_69_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_69_V_we0), + .res_69_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_69_V_d0), + .res_70_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_70_V_address0), + .res_70_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_70_V_ce0), + .res_70_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_70_V_we0), + .res_70_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_70_V_d0), + .res_71_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_71_V_address0), + .res_71_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_71_V_ce0), + .res_71_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_71_V_we0), + .res_71_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_71_V_d0), + .res_72_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_72_V_address0), + .res_72_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_72_V_ce0), + .res_72_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_72_V_we0), + .res_72_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_72_V_d0), + .res_73_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_73_V_address0), + .res_73_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_73_V_ce0), + .res_73_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_73_V_we0), + .res_73_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_73_V_d0), + .res_74_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_74_V_address0), + .res_74_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_74_V_ce0), + .res_74_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_74_V_we0), + .res_74_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_74_V_d0), + .res_75_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_75_V_address0), + .res_75_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_75_V_ce0), + .res_75_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_75_V_we0), + .res_75_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_75_V_d0), + .res_76_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_76_V_address0), + .res_76_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_76_V_ce0), + .res_76_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_76_V_we0), + .res_76_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_76_V_d0), + .res_77_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_77_V_address0), + .res_77_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_77_V_ce0), + .res_77_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_77_V_we0), + .res_77_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_77_V_d0), + .res_78_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_78_V_address0), + .res_78_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_78_V_ce0), + .res_78_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_78_V_we0), + .res_78_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_78_V_d0), + .res_79_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_79_V_address0), + .res_79_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_79_V_ce0), + .res_79_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_79_V_we0), + .res_79_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_79_V_d0), + .res_80_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_80_V_address0), + .res_80_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_80_V_ce0), + .res_80_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_80_V_we0), + .res_80_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_80_V_d0), + .res_81_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_81_V_address0), + .res_81_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_81_V_ce0), + .res_81_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_81_V_we0), + .res_81_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_81_V_d0), + .res_82_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_82_V_address0), + .res_82_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_82_V_ce0), + .res_82_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_82_V_we0), + .res_82_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_82_V_d0), + .res_83_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_83_V_address0), + .res_83_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_83_V_ce0), + .res_83_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_83_V_we0), + .res_83_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_83_V_d0), + .res_84_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_84_V_address0), + .res_84_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_84_V_ce0), + .res_84_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_84_V_we0), + .res_84_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_84_V_d0), + .res_85_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_85_V_address0), + .res_85_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_85_V_ce0), + .res_85_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_85_V_we0), + .res_85_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_85_V_d0), + .res_86_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_86_V_address0), + .res_86_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_86_V_ce0), + .res_86_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_86_V_we0), + .res_86_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_86_V_d0), + .res_87_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_87_V_address0), + .res_87_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_87_V_ce0), + .res_87_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_87_V_we0), + .res_87_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_87_V_d0), + .res_88_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_88_V_address0), + .res_88_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_88_V_ce0), + .res_88_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_88_V_we0), + .res_88_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_88_V_d0), + .res_89_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_89_V_address0), + .res_89_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_89_V_ce0), + .res_89_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_89_V_we0), + .res_89_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_89_V_d0), + .res_90_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_90_V_address0), + .res_90_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_90_V_ce0), + .res_90_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_90_V_we0), + .res_90_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_90_V_d0), + .res_91_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_91_V_address0), + .res_91_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_91_V_ce0), + .res_91_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_91_V_we0), + .res_91_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_91_V_d0), + .res_92_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_92_V_address0), + .res_92_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_92_V_ce0), + .res_92_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_92_V_we0), + .res_92_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_92_V_d0), + .res_93_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_93_V_address0), + .res_93_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_93_V_ce0), + .res_93_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_93_V_we0), + .res_93_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_93_V_d0), + .res_94_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_94_V_address0), + .res_94_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_94_V_ce0), + .res_94_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_94_V_we0), + .res_94_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_94_V_d0), + .res_95_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_95_V_address0), + .res_95_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_95_V_ce0), + .res_95_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_95_V_we0), + .res_95_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_95_V_d0), + .res_96_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_96_V_address0), + .res_96_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_96_V_ce0), + .res_96_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_96_V_we0), + .res_96_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_96_V_d0), + .res_97_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_97_V_address0), + .res_97_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_97_V_ce0), + .res_97_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_97_V_we0), + .res_97_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_97_V_d0), + .res_98_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_98_V_address0), + .res_98_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_98_V_ce0), + .res_98_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_98_V_we0), + .res_98_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_98_V_d0), + .res_99_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_99_V_address0), + .res_99_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_99_V_ce0), + .res_99_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_99_V_we0), + .res_99_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_99_V_d0), + .res_100_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_100_V_address0), + .res_100_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_100_V_ce0), + .res_100_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_100_V_we0), + .res_100_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_100_V_d0), + .res_101_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_101_V_address0), + .res_101_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_101_V_ce0), + .res_101_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_101_V_we0), + .res_101_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_101_V_d0), + .res_102_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_102_V_address0), + .res_102_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_102_V_ce0), + .res_102_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_102_V_we0), + .res_102_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_102_V_d0), + .res_103_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_103_V_address0), + .res_103_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_103_V_ce0), + .res_103_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_103_V_we0), + .res_103_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_103_V_d0), + .res_104_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_104_V_address0), + .res_104_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_104_V_ce0), + .res_104_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_104_V_we0), + .res_104_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_104_V_d0), + .res_105_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_105_V_address0), + .res_105_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_105_V_ce0), + .res_105_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_105_V_we0), + .res_105_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_105_V_d0), + .res_106_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_106_V_address0), + .res_106_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_106_V_ce0), + .res_106_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_106_V_we0), + .res_106_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_106_V_d0), + .res_107_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_107_V_address0), + .res_107_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_107_V_ce0), + .res_107_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_107_V_we0), + .res_107_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_107_V_d0), + .res_108_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_108_V_address0), + .res_108_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_108_V_ce0), + .res_108_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_108_V_we0), + .res_108_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_108_V_d0), + .res_109_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_109_V_address0), + .res_109_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_109_V_ce0), + .res_109_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_109_V_we0), + .res_109_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_109_V_d0), + .res_110_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_110_V_address0), + .res_110_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_110_V_ce0), + .res_110_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_110_V_we0), + .res_110_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_110_V_d0), + .res_111_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_111_V_address0), + .res_111_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_111_V_ce0), + .res_111_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_111_V_we0), + .res_111_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_111_V_d0), + .res_112_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_112_V_address0), + .res_112_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_112_V_ce0), + .res_112_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_112_V_we0), + .res_112_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_112_V_d0), + .res_113_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_113_V_address0), + .res_113_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_113_V_ce0), + .res_113_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_113_V_we0), + .res_113_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_113_V_d0), + .res_114_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_114_V_address0), + .res_114_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_114_V_ce0), + .res_114_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_114_V_we0), + .res_114_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_114_V_d0), + .res_115_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_115_V_address0), + .res_115_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_115_V_ce0), + .res_115_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_115_V_we0), + .res_115_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_115_V_d0), + .res_116_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_116_V_address0), + .res_116_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_116_V_ce0), + .res_116_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_116_V_we0), + .res_116_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_116_V_d0), + .res_117_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_117_V_address0), + .res_117_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_117_V_ce0), + .res_117_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_117_V_we0), + .res_117_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_117_V_d0), + .res_118_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_118_V_address0), + .res_118_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_118_V_ce0), + .res_118_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_118_V_we0), + .res_118_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_118_V_d0), + .res_119_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_119_V_address0), + .res_119_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_119_V_ce0), + .res_119_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_119_V_we0), + .res_119_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_119_V_d0), + .res_120_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_120_V_address0), + .res_120_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_120_V_ce0), + .res_120_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_120_V_we0), + .res_120_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_120_V_d0), + .res_121_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_121_V_address0), + .res_121_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_121_V_ce0), + .res_121_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_121_V_we0), + .res_121_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_121_V_d0), + .res_122_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_122_V_address0), + .res_122_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_122_V_ce0), + .res_122_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_122_V_we0), + .res_122_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_122_V_d0), + .res_123_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_123_V_address0), + .res_123_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_123_V_ce0), + .res_123_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_123_V_we0), + .res_123_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_123_V_d0), + .res_124_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_124_V_address0), + .res_124_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_124_V_ce0), + .res_124_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_124_V_we0), + .res_124_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_124_V_d0), + .res_125_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_125_V_address0), + .res_125_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_125_V_ce0), + .res_125_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_125_V_we0), + .res_125_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_125_V_d0), + .res_126_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_126_V_address0), + .res_126_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_126_V_ce0), + .res_126_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_126_V_we0), + .res_126_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_126_V_d0), + .res_127_V_address0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_127_V_address0), + .res_127_V_ce0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_127_V_ce0), + .res_127_V_we0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_127_V_we0), + .res_127_V_d0(grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_127_V_d0) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_done <= 1'b0; + end else begin + if (((1'b0 == ap_block_state10_on_subcall_done) & (ap_ST_fsm_state10 == ap_CS_fsm))) begin + ap_sync_reg_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_done <= 1'b0; + end else if ((grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_done == 1'b1)) begin + ap_sync_reg_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_done <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_ready <= 1'b0; + end else begin + if (((1'b0 == ap_block_state10_on_subcall_done) & (ap_ST_fsm_state10 == ap_CS_fsm))) begin + ap_sync_reg_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_ready <= 1'b0; + end else if ((grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_ready == 1'b1)) begin + ap_sync_reg_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_ready <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_start_reg <= 1'b0; + end else begin + if ((ap_ST_fsm_state5 == ap_CS_fsm)) begin + grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_start_reg <= 1'b1; + end else if ((grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_ready == 1'b1)) begin + grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_start_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_start_reg <= 1'b0; + end else begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b1))) begin + grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_start_reg <= 1'b1; + end else if ((grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_ready == 1'b1)) begin + grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_start_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_start_reg <= 1'b0; + end else begin + if (((ap_ST_fsm_state9 == ap_CS_fsm) | ((ap_sync_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_ready == 1'b0) & (ap_ST_fsm_state10 == ap_CS_fsm)))) begin + grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_start_reg <= 1'b1; + end else if ((grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_ready == 1'b1)) begin + grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_start_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_start_reg <= 1'b0; + end else begin + if ((ap_ST_fsm_state3 == ap_CS_fsm)) begin + grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_start_reg <= 1'b1; + end else if ((grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_ready == 1'b1)) begin + grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_start_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_start_reg <= 1'b0; + end else begin + if ((ap_ST_fsm_state7 == ap_CS_fsm)) begin + grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_start_reg <= 1'b1; + end else if ((grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_ready == 1'b1)) begin + grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_start_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_0_V_ap_vld == 1'b1) & (ap_ST_fsm_state10 == ap_CS_fsm))) begin + layer9_out_0_V_fu_2130 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_0_V; + end +end + +always @ (posedge ap_clk) begin + if (((grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_1_V_ap_vld == 1'b1) & (ap_ST_fsm_state10 == ap_CS_fsm))) begin + layer9_out_1_V_fu_2134 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_1_V; + end +end + +always @ (posedge ap_clk) begin + if (((grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_2_V_ap_vld == 1'b1) & (ap_ST_fsm_state10 == ap_CS_fsm))) begin + layer9_out_2_V_fu_2138 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_2_V; + end +end + +always @ (posedge ap_clk) begin + if (((grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_3_V_ap_vld == 1'b1) & (ap_ST_fsm_state10 == ap_CS_fsm))) begin + layer9_out_3_V_fu_2142 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_3_V; + end +end + +always @ (posedge ap_clk) begin + if (((grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_4_V_ap_vld == 1'b1) & (ap_ST_fsm_state10 == ap_CS_fsm))) begin + layer9_out_4_V_fu_2146 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_4_V; + end +end + +always @ (posedge ap_clk) begin + if (((grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_5_V_ap_vld == 1'b1) & (ap_ST_fsm_state10 == ap_CS_fsm))) begin + layer9_out_5_V_fu_2150 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_5_V; + end +end + +always @ (posedge ap_clk) begin + if (((grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_6_V_ap_vld == 1'b1) & (ap_ST_fsm_state10 == ap_CS_fsm))) begin + layer9_out_6_V_fu_2154 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_6_V; + end +end + +always @ (posedge ap_clk) begin + if (((grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_7_V_ap_vld == 1'b1) & (ap_ST_fsm_state10 == ap_CS_fsm))) begin + layer9_out_7_V_fu_2158 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_7_V; + end +end + +always @ (posedge ap_clk) begin + if (((grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_8_V_ap_vld == 1'b1) & (ap_ST_fsm_state10 == ap_CS_fsm))) begin + layer9_out_8_V_fu_2162 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_8_V; + end +end + +always @ (posedge ap_clk) begin + if (((grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_9_V_ap_vld == 1'b1) & (ap_ST_fsm_state10 == ap_CS_fsm))) begin + layer9_out_9_V_fu_2166 <= grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_res_9_V; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state15 == ap_CS_fsm)) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state15 == ap_CS_fsm)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state15 == ap_CS_fsm)) begin + const_size_in_1_ap_vld = 1'b1; + end else begin + const_size_in_1_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state15 == ap_CS_fsm)) begin + const_size_out_1_ap_vld = 1'b1; + end else begin + const_size_out_1_ap_vld = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_state10_on_subcall_done) & (ap_ST_fsm_state10 == ap_CS_fsm))) begin + grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_continue = 1'b1; + end else begin + grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_continue = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state15 == ap_CS_fsm)) begin + layer11_out_V_address0 = 64'd8; + end else if ((ap_ST_fsm_state14 == ap_CS_fsm)) begin + layer11_out_V_address0 = 64'd6; + end else if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + layer11_out_V_address0 = 64'd4; + end else if ((ap_ST_fsm_state12 == ap_CS_fsm)) begin + layer11_out_V_address0 = 64'd2; + end else if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + layer11_out_V_address0 = 64'd0; + end else begin + layer11_out_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state15 == ap_CS_fsm)) begin + layer11_out_V_address1 = 64'd9; + end else if ((ap_ST_fsm_state14 == ap_CS_fsm)) begin + layer11_out_V_address1 = 64'd7; + end else if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + layer11_out_V_address1 = 64'd5; + end else if ((ap_ST_fsm_state12 == ap_CS_fsm)) begin + layer11_out_V_address1 = 64'd3; + end else if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + layer11_out_V_address1 = 64'd1; + end else begin + layer11_out_V_address1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state15 == ap_CS_fsm) | (ap_ST_fsm_state14 == ap_CS_fsm) | (ap_ST_fsm_state13 == ap_CS_fsm) | (ap_ST_fsm_state12 == ap_CS_fsm) | (ap_ST_fsm_state11 == ap_CS_fsm))) begin + layer11_out_V_ce0 = 1'b1; + end else begin + layer11_out_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state15 == ap_CS_fsm) | (ap_ST_fsm_state14 == ap_CS_fsm) | (ap_ST_fsm_state13 == ap_CS_fsm) | (ap_ST_fsm_state12 == ap_CS_fsm) | (ap_ST_fsm_state11 == ap_CS_fsm))) begin + layer11_out_V_ce1 = 1'b1; + end else begin + layer11_out_V_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state15 == ap_CS_fsm)) begin + layer11_out_V_d0 = layer9_out_8_V_fu_2162; + end else if ((ap_ST_fsm_state14 == ap_CS_fsm)) begin + layer11_out_V_d0 = layer9_out_6_V_fu_2154; + end else if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + layer11_out_V_d0 = layer9_out_4_V_fu_2146; + end else if ((ap_ST_fsm_state12 == ap_CS_fsm)) begin + layer11_out_V_d0 = layer9_out_2_V_fu_2138; + end else if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + layer11_out_V_d0 = layer9_out_0_V_fu_2130; + end else begin + layer11_out_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state15 == ap_CS_fsm)) begin + layer11_out_V_d1 = layer9_out_9_V_fu_2166; + end else if ((ap_ST_fsm_state14 == ap_CS_fsm)) begin + layer11_out_V_d1 = layer9_out_7_V_fu_2158; + end else if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + layer11_out_V_d1 = layer9_out_5_V_fu_2150; + end else if ((ap_ST_fsm_state12 == ap_CS_fsm)) begin + layer11_out_V_d1 = layer9_out_3_V_fu_2142; + end else if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + layer11_out_V_d1 = layer9_out_1_V_fu_2134; + end else begin + layer11_out_V_d1 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state15 == ap_CS_fsm) | (ap_ST_fsm_state14 == ap_CS_fsm) | (ap_ST_fsm_state13 == ap_CS_fsm) | (ap_ST_fsm_state12 == ap_CS_fsm) | (ap_ST_fsm_state11 == ap_CS_fsm))) begin + layer11_out_V_we0 = 1'b1; + end else begin + layer11_out_V_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state15 == ap_CS_fsm) | (ap_ST_fsm_state14 == ap_CS_fsm) | (ap_ST_fsm_state13 == ap_CS_fsm) | (ap_ST_fsm_state12 == ap_CS_fsm) | (ap_ST_fsm_state11 == ap_CS_fsm))) begin + layer11_out_V_we1 = 1'b1; + end else begin + layer11_out_V_we1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_0_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_0_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_0_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_0_V_address0; + end else begin + layer2_out_0_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_0_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_0_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_0_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_0_V_ce0; + end else begin + layer2_out_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_0_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_0_V_we0; + end else begin + layer2_out_0_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_100_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_100_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_100_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_100_V_address0; + end else begin + layer2_out_100_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_100_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_100_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_100_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_100_V_ce0; + end else begin + layer2_out_100_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_100_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_100_V_we0; + end else begin + layer2_out_100_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_101_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_101_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_101_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_101_V_address0; + end else begin + layer2_out_101_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_101_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_101_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_101_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_101_V_ce0; + end else begin + layer2_out_101_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_101_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_101_V_we0; + end else begin + layer2_out_101_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_102_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_102_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_102_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_102_V_address0; + end else begin + layer2_out_102_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_102_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_102_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_102_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_102_V_ce0; + end else begin + layer2_out_102_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_102_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_102_V_we0; + end else begin + layer2_out_102_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_103_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_103_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_103_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_103_V_address0; + end else begin + layer2_out_103_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_103_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_103_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_103_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_103_V_ce0; + end else begin + layer2_out_103_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_103_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_103_V_we0; + end else begin + layer2_out_103_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_104_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_104_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_104_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_104_V_address0; + end else begin + layer2_out_104_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_104_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_104_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_104_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_104_V_ce0; + end else begin + layer2_out_104_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_104_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_104_V_we0; + end else begin + layer2_out_104_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_105_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_105_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_105_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_105_V_address0; + end else begin + layer2_out_105_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_105_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_105_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_105_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_105_V_ce0; + end else begin + layer2_out_105_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_105_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_105_V_we0; + end else begin + layer2_out_105_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_106_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_106_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_106_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_106_V_address0; + end else begin + layer2_out_106_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_106_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_106_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_106_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_106_V_ce0; + end else begin + layer2_out_106_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_106_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_106_V_we0; + end else begin + layer2_out_106_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_107_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_107_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_107_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_107_V_address0; + end else begin + layer2_out_107_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_107_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_107_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_107_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_107_V_ce0; + end else begin + layer2_out_107_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_107_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_107_V_we0; + end else begin + layer2_out_107_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_108_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_108_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_108_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_108_V_address0; + end else begin + layer2_out_108_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_108_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_108_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_108_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_108_V_ce0; + end else begin + layer2_out_108_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_108_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_108_V_we0; + end else begin + layer2_out_108_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_109_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_109_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_109_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_109_V_address0; + end else begin + layer2_out_109_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_109_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_109_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_109_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_109_V_ce0; + end else begin + layer2_out_109_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_109_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_109_V_we0; + end else begin + layer2_out_109_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_10_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_10_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_10_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_10_V_address0; + end else begin + layer2_out_10_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_10_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_10_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_10_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_10_V_ce0; + end else begin + layer2_out_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_10_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_10_V_we0; + end else begin + layer2_out_10_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_110_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_110_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_110_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_110_V_address0; + end else begin + layer2_out_110_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_110_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_110_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_110_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_110_V_ce0; + end else begin + layer2_out_110_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_110_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_110_V_we0; + end else begin + layer2_out_110_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_111_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_111_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_111_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_111_V_address0; + end else begin + layer2_out_111_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_111_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_111_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_111_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_111_V_ce0; + end else begin + layer2_out_111_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_111_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_111_V_we0; + end else begin + layer2_out_111_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_112_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_112_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_112_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_112_V_address0; + end else begin + layer2_out_112_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_112_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_112_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_112_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_112_V_ce0; + end else begin + layer2_out_112_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_112_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_112_V_we0; + end else begin + layer2_out_112_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_113_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_113_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_113_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_113_V_address0; + end else begin + layer2_out_113_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_113_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_113_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_113_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_113_V_ce0; + end else begin + layer2_out_113_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_113_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_113_V_we0; + end else begin + layer2_out_113_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_114_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_114_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_114_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_114_V_address0; + end else begin + layer2_out_114_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_114_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_114_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_114_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_114_V_ce0; + end else begin + layer2_out_114_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_114_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_114_V_we0; + end else begin + layer2_out_114_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_115_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_115_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_115_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_115_V_address0; + end else begin + layer2_out_115_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_115_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_115_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_115_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_115_V_ce0; + end else begin + layer2_out_115_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_115_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_115_V_we0; + end else begin + layer2_out_115_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_116_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_116_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_116_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_116_V_address0; + end else begin + layer2_out_116_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_116_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_116_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_116_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_116_V_ce0; + end else begin + layer2_out_116_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_116_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_116_V_we0; + end else begin + layer2_out_116_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_117_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_117_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_117_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_117_V_address0; + end else begin + layer2_out_117_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_117_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_117_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_117_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_117_V_ce0; + end else begin + layer2_out_117_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_117_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_117_V_we0; + end else begin + layer2_out_117_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_118_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_118_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_118_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_118_V_address0; + end else begin + layer2_out_118_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_118_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_118_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_118_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_118_V_ce0; + end else begin + layer2_out_118_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_118_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_118_V_we0; + end else begin + layer2_out_118_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_119_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_119_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_119_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_119_V_address0; + end else begin + layer2_out_119_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_119_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_119_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_119_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_119_V_ce0; + end else begin + layer2_out_119_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_119_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_119_V_we0; + end else begin + layer2_out_119_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_11_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_11_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_11_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_11_V_address0; + end else begin + layer2_out_11_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_11_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_11_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_11_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_11_V_ce0; + end else begin + layer2_out_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_11_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_11_V_we0; + end else begin + layer2_out_11_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_120_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_120_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_120_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_120_V_address0; + end else begin + layer2_out_120_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_120_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_120_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_120_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_120_V_ce0; + end else begin + layer2_out_120_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_120_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_120_V_we0; + end else begin + layer2_out_120_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_121_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_121_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_121_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_121_V_address0; + end else begin + layer2_out_121_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_121_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_121_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_121_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_121_V_ce0; + end else begin + layer2_out_121_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_121_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_121_V_we0; + end else begin + layer2_out_121_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_122_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_122_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_122_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_122_V_address0; + end else begin + layer2_out_122_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_122_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_122_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_122_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_122_V_ce0; + end else begin + layer2_out_122_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_122_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_122_V_we0; + end else begin + layer2_out_122_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_123_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_123_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_123_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_123_V_address0; + end else begin + layer2_out_123_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_123_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_123_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_123_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_123_V_ce0; + end else begin + layer2_out_123_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_123_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_123_V_we0; + end else begin + layer2_out_123_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_124_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_124_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_124_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_124_V_address0; + end else begin + layer2_out_124_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_124_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_124_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_124_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_124_V_ce0; + end else begin + layer2_out_124_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_124_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_124_V_we0; + end else begin + layer2_out_124_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_125_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_125_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_125_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_125_V_address0; + end else begin + layer2_out_125_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_125_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_125_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_125_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_125_V_ce0; + end else begin + layer2_out_125_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_125_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_125_V_we0; + end else begin + layer2_out_125_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_126_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_126_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_126_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_126_V_address0; + end else begin + layer2_out_126_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_126_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_126_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_126_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_126_V_ce0; + end else begin + layer2_out_126_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_126_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_126_V_we0; + end else begin + layer2_out_126_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_127_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_127_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_127_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_127_V_address0; + end else begin + layer2_out_127_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_127_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_127_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_127_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_127_V_ce0; + end else begin + layer2_out_127_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_127_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_127_V_we0; + end else begin + layer2_out_127_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_12_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_12_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_12_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_12_V_address0; + end else begin + layer2_out_12_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_12_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_12_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_12_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_12_V_ce0; + end else begin + layer2_out_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_12_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_12_V_we0; + end else begin + layer2_out_12_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_13_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_13_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_13_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_13_V_address0; + end else begin + layer2_out_13_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_13_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_13_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_13_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_13_V_ce0; + end else begin + layer2_out_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_13_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_13_V_we0; + end else begin + layer2_out_13_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_14_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_14_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_14_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_14_V_address0; + end else begin + layer2_out_14_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_14_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_14_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_14_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_14_V_ce0; + end else begin + layer2_out_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_14_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_14_V_we0; + end else begin + layer2_out_14_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_15_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_15_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_15_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_15_V_address0; + end else begin + layer2_out_15_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_15_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_15_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_15_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_15_V_ce0; + end else begin + layer2_out_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_15_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_15_V_we0; + end else begin + layer2_out_15_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_16_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_16_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_16_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_16_V_address0; + end else begin + layer2_out_16_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_16_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_16_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_16_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_16_V_ce0; + end else begin + layer2_out_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_16_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_16_V_we0; + end else begin + layer2_out_16_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_17_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_17_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_17_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_17_V_address0; + end else begin + layer2_out_17_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_17_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_17_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_17_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_17_V_ce0; + end else begin + layer2_out_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_17_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_17_V_we0; + end else begin + layer2_out_17_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_18_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_18_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_18_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_18_V_address0; + end else begin + layer2_out_18_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_18_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_18_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_18_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_18_V_ce0; + end else begin + layer2_out_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_18_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_18_V_we0; + end else begin + layer2_out_18_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_19_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_19_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_19_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_19_V_address0; + end else begin + layer2_out_19_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_19_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_19_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_19_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_19_V_ce0; + end else begin + layer2_out_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_19_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_19_V_we0; + end else begin + layer2_out_19_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_1_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_1_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_1_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_1_V_address0; + end else begin + layer2_out_1_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_1_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_1_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_1_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_1_V_ce0; + end else begin + layer2_out_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_1_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_1_V_we0; + end else begin + layer2_out_1_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_20_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_20_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_20_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_20_V_address0; + end else begin + layer2_out_20_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_20_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_20_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_20_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_20_V_ce0; + end else begin + layer2_out_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_20_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_20_V_we0; + end else begin + layer2_out_20_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_21_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_21_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_21_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_21_V_address0; + end else begin + layer2_out_21_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_21_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_21_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_21_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_21_V_ce0; + end else begin + layer2_out_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_21_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_21_V_we0; + end else begin + layer2_out_21_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_22_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_22_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_22_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_22_V_address0; + end else begin + layer2_out_22_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_22_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_22_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_22_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_22_V_ce0; + end else begin + layer2_out_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_22_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_22_V_we0; + end else begin + layer2_out_22_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_23_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_23_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_23_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_23_V_address0; + end else begin + layer2_out_23_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_23_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_23_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_23_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_23_V_ce0; + end else begin + layer2_out_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_23_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_23_V_we0; + end else begin + layer2_out_23_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_24_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_24_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_24_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_24_V_address0; + end else begin + layer2_out_24_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_24_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_24_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_24_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_24_V_ce0; + end else begin + layer2_out_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_24_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_24_V_we0; + end else begin + layer2_out_24_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_25_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_25_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_25_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_25_V_address0; + end else begin + layer2_out_25_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_25_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_25_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_25_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_25_V_ce0; + end else begin + layer2_out_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_25_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_25_V_we0; + end else begin + layer2_out_25_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_26_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_26_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_26_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_26_V_address0; + end else begin + layer2_out_26_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_26_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_26_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_26_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_26_V_ce0; + end else begin + layer2_out_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_26_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_26_V_we0; + end else begin + layer2_out_26_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_27_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_27_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_27_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_27_V_address0; + end else begin + layer2_out_27_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_27_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_27_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_27_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_27_V_ce0; + end else begin + layer2_out_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_27_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_27_V_we0; + end else begin + layer2_out_27_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_28_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_28_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_28_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_28_V_address0; + end else begin + layer2_out_28_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_28_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_28_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_28_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_28_V_ce0; + end else begin + layer2_out_28_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_28_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_28_V_we0; + end else begin + layer2_out_28_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_29_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_29_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_29_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_29_V_address0; + end else begin + layer2_out_29_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_29_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_29_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_29_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_29_V_ce0; + end else begin + layer2_out_29_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_29_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_29_V_we0; + end else begin + layer2_out_29_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_2_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_2_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_2_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_2_V_address0; + end else begin + layer2_out_2_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_2_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_2_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_2_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_2_V_ce0; + end else begin + layer2_out_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_2_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_2_V_we0; + end else begin + layer2_out_2_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_30_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_30_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_30_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_30_V_address0; + end else begin + layer2_out_30_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_30_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_30_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_30_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_30_V_ce0; + end else begin + layer2_out_30_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_30_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_30_V_we0; + end else begin + layer2_out_30_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_31_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_31_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_31_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_31_V_address0; + end else begin + layer2_out_31_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_31_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_31_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_31_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_31_V_ce0; + end else begin + layer2_out_31_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_31_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_31_V_we0; + end else begin + layer2_out_31_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_32_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_32_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_32_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_32_V_address0; + end else begin + layer2_out_32_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_32_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_32_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_32_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_32_V_ce0; + end else begin + layer2_out_32_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_32_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_32_V_we0; + end else begin + layer2_out_32_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_33_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_33_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_33_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_33_V_address0; + end else begin + layer2_out_33_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_33_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_33_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_33_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_33_V_ce0; + end else begin + layer2_out_33_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_33_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_33_V_we0; + end else begin + layer2_out_33_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_34_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_34_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_34_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_34_V_address0; + end else begin + layer2_out_34_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_34_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_34_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_34_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_34_V_ce0; + end else begin + layer2_out_34_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_34_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_34_V_we0; + end else begin + layer2_out_34_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_35_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_35_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_35_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_35_V_address0; + end else begin + layer2_out_35_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_35_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_35_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_35_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_35_V_ce0; + end else begin + layer2_out_35_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_35_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_35_V_we0; + end else begin + layer2_out_35_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_36_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_36_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_36_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_36_V_address0; + end else begin + layer2_out_36_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_36_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_36_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_36_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_36_V_ce0; + end else begin + layer2_out_36_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_36_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_36_V_we0; + end else begin + layer2_out_36_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_37_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_37_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_37_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_37_V_address0; + end else begin + layer2_out_37_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_37_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_37_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_37_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_37_V_ce0; + end else begin + layer2_out_37_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_37_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_37_V_we0; + end else begin + layer2_out_37_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_38_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_38_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_38_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_38_V_address0; + end else begin + layer2_out_38_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_38_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_38_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_38_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_38_V_ce0; + end else begin + layer2_out_38_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_38_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_38_V_we0; + end else begin + layer2_out_38_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_39_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_39_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_39_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_39_V_address0; + end else begin + layer2_out_39_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_39_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_39_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_39_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_39_V_ce0; + end else begin + layer2_out_39_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_39_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_39_V_we0; + end else begin + layer2_out_39_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_3_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_3_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_3_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_3_V_address0; + end else begin + layer2_out_3_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_3_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_3_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_3_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_3_V_ce0; + end else begin + layer2_out_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_3_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_3_V_we0; + end else begin + layer2_out_3_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_40_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_40_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_40_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_40_V_address0; + end else begin + layer2_out_40_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_40_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_40_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_40_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_40_V_ce0; + end else begin + layer2_out_40_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_40_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_40_V_we0; + end else begin + layer2_out_40_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_41_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_41_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_41_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_41_V_address0; + end else begin + layer2_out_41_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_41_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_41_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_41_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_41_V_ce0; + end else begin + layer2_out_41_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_41_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_41_V_we0; + end else begin + layer2_out_41_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_42_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_42_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_42_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_42_V_address0; + end else begin + layer2_out_42_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_42_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_42_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_42_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_42_V_ce0; + end else begin + layer2_out_42_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_42_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_42_V_we0; + end else begin + layer2_out_42_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_43_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_43_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_43_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_43_V_address0; + end else begin + layer2_out_43_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_43_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_43_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_43_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_43_V_ce0; + end else begin + layer2_out_43_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_43_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_43_V_we0; + end else begin + layer2_out_43_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_44_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_44_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_44_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_44_V_address0; + end else begin + layer2_out_44_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_44_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_44_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_44_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_44_V_ce0; + end else begin + layer2_out_44_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_44_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_44_V_we0; + end else begin + layer2_out_44_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_45_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_45_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_45_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_45_V_address0; + end else begin + layer2_out_45_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_45_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_45_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_45_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_45_V_ce0; + end else begin + layer2_out_45_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_45_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_45_V_we0; + end else begin + layer2_out_45_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_46_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_46_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_46_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_46_V_address0; + end else begin + layer2_out_46_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_46_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_46_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_46_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_46_V_ce0; + end else begin + layer2_out_46_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_46_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_46_V_we0; + end else begin + layer2_out_46_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_47_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_47_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_47_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_47_V_address0; + end else begin + layer2_out_47_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_47_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_47_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_47_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_47_V_ce0; + end else begin + layer2_out_47_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_47_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_47_V_we0; + end else begin + layer2_out_47_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_48_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_48_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_48_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_48_V_address0; + end else begin + layer2_out_48_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_48_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_48_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_48_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_48_V_ce0; + end else begin + layer2_out_48_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_48_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_48_V_we0; + end else begin + layer2_out_48_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_49_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_49_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_49_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_49_V_address0; + end else begin + layer2_out_49_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_49_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_49_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_49_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_49_V_ce0; + end else begin + layer2_out_49_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_49_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_49_V_we0; + end else begin + layer2_out_49_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_4_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_4_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_4_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_4_V_address0; + end else begin + layer2_out_4_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_4_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_4_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_4_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_4_V_ce0; + end else begin + layer2_out_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_4_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_4_V_we0; + end else begin + layer2_out_4_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_50_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_50_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_50_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_50_V_address0; + end else begin + layer2_out_50_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_50_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_50_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_50_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_50_V_ce0; + end else begin + layer2_out_50_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_50_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_50_V_we0; + end else begin + layer2_out_50_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_51_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_51_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_51_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_51_V_address0; + end else begin + layer2_out_51_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_51_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_51_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_51_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_51_V_ce0; + end else begin + layer2_out_51_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_51_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_51_V_we0; + end else begin + layer2_out_51_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_52_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_52_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_52_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_52_V_address0; + end else begin + layer2_out_52_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_52_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_52_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_52_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_52_V_ce0; + end else begin + layer2_out_52_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_52_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_52_V_we0; + end else begin + layer2_out_52_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_53_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_53_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_53_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_53_V_address0; + end else begin + layer2_out_53_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_53_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_53_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_53_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_53_V_ce0; + end else begin + layer2_out_53_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_53_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_53_V_we0; + end else begin + layer2_out_53_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_54_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_54_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_54_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_54_V_address0; + end else begin + layer2_out_54_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_54_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_54_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_54_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_54_V_ce0; + end else begin + layer2_out_54_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_54_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_54_V_we0; + end else begin + layer2_out_54_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_55_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_55_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_55_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_55_V_address0; + end else begin + layer2_out_55_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_55_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_55_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_55_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_55_V_ce0; + end else begin + layer2_out_55_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_55_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_55_V_we0; + end else begin + layer2_out_55_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_56_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_56_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_56_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_56_V_address0; + end else begin + layer2_out_56_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_56_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_56_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_56_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_56_V_ce0; + end else begin + layer2_out_56_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_56_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_56_V_we0; + end else begin + layer2_out_56_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_57_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_57_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_57_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_57_V_address0; + end else begin + layer2_out_57_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_57_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_57_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_57_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_57_V_ce0; + end else begin + layer2_out_57_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_57_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_57_V_we0; + end else begin + layer2_out_57_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_58_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_58_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_58_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_58_V_address0; + end else begin + layer2_out_58_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_58_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_58_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_58_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_58_V_ce0; + end else begin + layer2_out_58_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_58_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_58_V_we0; + end else begin + layer2_out_58_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_59_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_59_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_59_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_59_V_address0; + end else begin + layer2_out_59_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_59_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_59_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_59_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_59_V_ce0; + end else begin + layer2_out_59_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_59_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_59_V_we0; + end else begin + layer2_out_59_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_5_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_5_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_5_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_5_V_address0; + end else begin + layer2_out_5_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_5_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_5_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_5_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_5_V_ce0; + end else begin + layer2_out_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_5_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_5_V_we0; + end else begin + layer2_out_5_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_60_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_60_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_60_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_60_V_address0; + end else begin + layer2_out_60_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_60_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_60_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_60_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_60_V_ce0; + end else begin + layer2_out_60_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_60_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_60_V_we0; + end else begin + layer2_out_60_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_61_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_61_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_61_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_61_V_address0; + end else begin + layer2_out_61_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_61_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_61_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_61_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_61_V_ce0; + end else begin + layer2_out_61_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_61_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_61_V_we0; + end else begin + layer2_out_61_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_62_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_62_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_62_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_62_V_address0; + end else begin + layer2_out_62_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_62_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_62_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_62_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_62_V_ce0; + end else begin + layer2_out_62_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_62_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_62_V_we0; + end else begin + layer2_out_62_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_63_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_63_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_63_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_63_V_address0; + end else begin + layer2_out_63_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_63_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_63_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_63_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_63_V_ce0; + end else begin + layer2_out_63_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_63_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_63_V_we0; + end else begin + layer2_out_63_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_64_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_64_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_64_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_64_V_address0; + end else begin + layer2_out_64_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_64_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_64_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_64_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_64_V_ce0; + end else begin + layer2_out_64_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_64_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_64_V_we0; + end else begin + layer2_out_64_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_65_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_65_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_65_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_65_V_address0; + end else begin + layer2_out_65_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_65_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_65_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_65_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_65_V_ce0; + end else begin + layer2_out_65_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_65_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_65_V_we0; + end else begin + layer2_out_65_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_66_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_66_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_66_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_66_V_address0; + end else begin + layer2_out_66_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_66_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_66_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_66_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_66_V_ce0; + end else begin + layer2_out_66_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_66_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_66_V_we0; + end else begin + layer2_out_66_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_67_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_67_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_67_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_67_V_address0; + end else begin + layer2_out_67_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_67_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_67_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_67_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_67_V_ce0; + end else begin + layer2_out_67_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_67_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_67_V_we0; + end else begin + layer2_out_67_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_68_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_68_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_68_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_68_V_address0; + end else begin + layer2_out_68_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_68_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_68_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_68_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_68_V_ce0; + end else begin + layer2_out_68_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_68_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_68_V_we0; + end else begin + layer2_out_68_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_69_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_69_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_69_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_69_V_address0; + end else begin + layer2_out_69_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_69_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_69_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_69_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_69_V_ce0; + end else begin + layer2_out_69_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_69_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_69_V_we0; + end else begin + layer2_out_69_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_6_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_6_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_6_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_6_V_address0; + end else begin + layer2_out_6_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_6_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_6_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_6_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_6_V_ce0; + end else begin + layer2_out_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_6_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_6_V_we0; + end else begin + layer2_out_6_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_70_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_70_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_70_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_70_V_address0; + end else begin + layer2_out_70_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_70_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_70_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_70_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_70_V_ce0; + end else begin + layer2_out_70_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_70_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_70_V_we0; + end else begin + layer2_out_70_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_71_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_71_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_71_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_71_V_address0; + end else begin + layer2_out_71_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_71_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_71_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_71_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_71_V_ce0; + end else begin + layer2_out_71_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_71_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_71_V_we0; + end else begin + layer2_out_71_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_72_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_72_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_72_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_72_V_address0; + end else begin + layer2_out_72_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_72_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_72_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_72_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_72_V_ce0; + end else begin + layer2_out_72_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_72_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_72_V_we0; + end else begin + layer2_out_72_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_73_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_73_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_73_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_73_V_address0; + end else begin + layer2_out_73_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_73_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_73_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_73_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_73_V_ce0; + end else begin + layer2_out_73_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_73_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_73_V_we0; + end else begin + layer2_out_73_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_74_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_74_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_74_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_74_V_address0; + end else begin + layer2_out_74_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_74_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_74_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_74_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_74_V_ce0; + end else begin + layer2_out_74_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_74_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_74_V_we0; + end else begin + layer2_out_74_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_75_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_75_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_75_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_75_V_address0; + end else begin + layer2_out_75_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_75_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_75_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_75_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_75_V_ce0; + end else begin + layer2_out_75_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_75_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_75_V_we0; + end else begin + layer2_out_75_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_76_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_76_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_76_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_76_V_address0; + end else begin + layer2_out_76_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_76_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_76_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_76_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_76_V_ce0; + end else begin + layer2_out_76_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_76_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_76_V_we0; + end else begin + layer2_out_76_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_77_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_77_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_77_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_77_V_address0; + end else begin + layer2_out_77_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_77_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_77_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_77_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_77_V_ce0; + end else begin + layer2_out_77_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_77_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_77_V_we0; + end else begin + layer2_out_77_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_78_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_78_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_78_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_78_V_address0; + end else begin + layer2_out_78_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_78_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_78_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_78_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_78_V_ce0; + end else begin + layer2_out_78_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_78_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_78_V_we0; + end else begin + layer2_out_78_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_79_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_79_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_79_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_79_V_address0; + end else begin + layer2_out_79_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_79_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_79_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_79_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_79_V_ce0; + end else begin + layer2_out_79_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_79_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_79_V_we0; + end else begin + layer2_out_79_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_7_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_7_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_7_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_7_V_address0; + end else begin + layer2_out_7_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_7_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_7_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_7_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_7_V_ce0; + end else begin + layer2_out_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_7_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_7_V_we0; + end else begin + layer2_out_7_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_80_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_80_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_80_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_80_V_address0; + end else begin + layer2_out_80_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_80_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_80_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_80_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_80_V_ce0; + end else begin + layer2_out_80_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_80_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_80_V_we0; + end else begin + layer2_out_80_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_81_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_81_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_81_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_81_V_address0; + end else begin + layer2_out_81_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_81_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_81_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_81_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_81_V_ce0; + end else begin + layer2_out_81_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_81_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_81_V_we0; + end else begin + layer2_out_81_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_82_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_82_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_82_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_82_V_address0; + end else begin + layer2_out_82_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_82_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_82_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_82_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_82_V_ce0; + end else begin + layer2_out_82_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_82_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_82_V_we0; + end else begin + layer2_out_82_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_83_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_83_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_83_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_83_V_address0; + end else begin + layer2_out_83_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_83_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_83_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_83_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_83_V_ce0; + end else begin + layer2_out_83_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_83_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_83_V_we0; + end else begin + layer2_out_83_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_84_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_84_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_84_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_84_V_address0; + end else begin + layer2_out_84_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_84_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_84_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_84_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_84_V_ce0; + end else begin + layer2_out_84_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_84_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_84_V_we0; + end else begin + layer2_out_84_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_85_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_85_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_85_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_85_V_address0; + end else begin + layer2_out_85_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_85_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_85_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_85_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_85_V_ce0; + end else begin + layer2_out_85_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_85_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_85_V_we0; + end else begin + layer2_out_85_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_86_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_86_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_86_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_86_V_address0; + end else begin + layer2_out_86_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_86_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_86_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_86_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_86_V_ce0; + end else begin + layer2_out_86_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_86_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_86_V_we0; + end else begin + layer2_out_86_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_87_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_87_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_87_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_87_V_address0; + end else begin + layer2_out_87_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_87_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_87_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_87_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_87_V_ce0; + end else begin + layer2_out_87_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_87_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_87_V_we0; + end else begin + layer2_out_87_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_88_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_88_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_88_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_88_V_address0; + end else begin + layer2_out_88_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_88_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_88_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_88_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_88_V_ce0; + end else begin + layer2_out_88_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_88_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_88_V_we0; + end else begin + layer2_out_88_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_89_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_89_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_89_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_89_V_address0; + end else begin + layer2_out_89_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_89_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_89_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_89_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_89_V_ce0; + end else begin + layer2_out_89_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_89_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_89_V_we0; + end else begin + layer2_out_89_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_8_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_8_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_8_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_8_V_address0; + end else begin + layer2_out_8_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_8_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_8_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_8_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_8_V_ce0; + end else begin + layer2_out_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_8_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_8_V_we0; + end else begin + layer2_out_8_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_90_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_90_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_90_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_90_V_address0; + end else begin + layer2_out_90_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_90_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_90_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_90_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_90_V_ce0; + end else begin + layer2_out_90_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_90_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_90_V_we0; + end else begin + layer2_out_90_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_91_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_91_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_91_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_91_V_address0; + end else begin + layer2_out_91_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_91_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_91_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_91_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_91_V_ce0; + end else begin + layer2_out_91_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_91_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_91_V_we0; + end else begin + layer2_out_91_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_92_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_92_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_92_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_92_V_address0; + end else begin + layer2_out_92_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_92_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_92_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_92_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_92_V_ce0; + end else begin + layer2_out_92_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_92_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_92_V_we0; + end else begin + layer2_out_92_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_93_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_93_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_93_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_93_V_address0; + end else begin + layer2_out_93_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_93_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_93_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_93_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_93_V_ce0; + end else begin + layer2_out_93_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_93_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_93_V_we0; + end else begin + layer2_out_93_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_94_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_94_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_94_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_94_V_address0; + end else begin + layer2_out_94_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_94_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_94_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_94_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_94_V_ce0; + end else begin + layer2_out_94_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_94_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_94_V_we0; + end else begin + layer2_out_94_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_95_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_95_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_95_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_95_V_address0; + end else begin + layer2_out_95_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_95_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_95_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_95_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_95_V_ce0; + end else begin + layer2_out_95_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_95_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_95_V_we0; + end else begin + layer2_out_95_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_96_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_96_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_96_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_96_V_address0; + end else begin + layer2_out_96_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_96_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_96_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_96_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_96_V_ce0; + end else begin + layer2_out_96_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_96_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_96_V_we0; + end else begin + layer2_out_96_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_97_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_97_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_97_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_97_V_address0; + end else begin + layer2_out_97_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_97_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_97_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_97_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_97_V_ce0; + end else begin + layer2_out_97_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_97_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_97_V_we0; + end else begin + layer2_out_97_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_98_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_98_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_98_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_98_V_address0; + end else begin + layer2_out_98_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_98_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_98_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_98_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_98_V_ce0; + end else begin + layer2_out_98_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_98_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_98_V_we0; + end else begin + layer2_out_98_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_99_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_99_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_99_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_99_V_address0; + end else begin + layer2_out_99_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_99_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_99_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_99_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_99_V_ce0; + end else begin + layer2_out_99_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_99_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_99_V_we0; + end else begin + layer2_out_99_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_9_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_9_V_address0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_9_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_9_V_address0; + end else begin + layer2_out_9_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer2_out_9_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_data_9_V_ce0; + end else if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_9_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_9_V_ce0; + end else begin + layer2_out_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + layer2_out_9_V_we0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_res_9_V_we0; + end else begin + layer2_out_9_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_0_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_0_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_0_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_0_V_address0; + end else begin + layer4_out_0_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_0_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_0_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_0_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_0_V_ce0; + end else begin + layer4_out_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_0_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_0_V_we0; + end else begin + layer4_out_0_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_100_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_100_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_100_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_100_V_address0; + end else begin + layer4_out_100_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_100_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_100_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_100_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_100_V_ce0; + end else begin + layer4_out_100_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_100_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_100_V_we0; + end else begin + layer4_out_100_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_101_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_101_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_101_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_101_V_address0; + end else begin + layer4_out_101_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_101_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_101_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_101_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_101_V_ce0; + end else begin + layer4_out_101_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_101_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_101_V_we0; + end else begin + layer4_out_101_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_102_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_102_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_102_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_102_V_address0; + end else begin + layer4_out_102_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_102_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_102_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_102_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_102_V_ce0; + end else begin + layer4_out_102_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_102_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_102_V_we0; + end else begin + layer4_out_102_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_103_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_103_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_103_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_103_V_address0; + end else begin + layer4_out_103_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_103_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_103_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_103_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_103_V_ce0; + end else begin + layer4_out_103_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_103_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_103_V_we0; + end else begin + layer4_out_103_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_104_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_104_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_104_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_104_V_address0; + end else begin + layer4_out_104_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_104_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_104_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_104_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_104_V_ce0; + end else begin + layer4_out_104_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_104_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_104_V_we0; + end else begin + layer4_out_104_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_105_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_105_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_105_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_105_V_address0; + end else begin + layer4_out_105_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_105_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_105_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_105_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_105_V_ce0; + end else begin + layer4_out_105_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_105_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_105_V_we0; + end else begin + layer4_out_105_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_106_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_106_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_106_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_106_V_address0; + end else begin + layer4_out_106_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_106_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_106_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_106_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_106_V_ce0; + end else begin + layer4_out_106_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_106_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_106_V_we0; + end else begin + layer4_out_106_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_107_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_107_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_107_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_107_V_address0; + end else begin + layer4_out_107_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_107_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_107_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_107_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_107_V_ce0; + end else begin + layer4_out_107_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_107_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_107_V_we0; + end else begin + layer4_out_107_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_108_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_108_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_108_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_108_V_address0; + end else begin + layer4_out_108_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_108_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_108_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_108_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_108_V_ce0; + end else begin + layer4_out_108_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_108_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_108_V_we0; + end else begin + layer4_out_108_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_109_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_109_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_109_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_109_V_address0; + end else begin + layer4_out_109_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_109_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_109_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_109_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_109_V_ce0; + end else begin + layer4_out_109_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_109_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_109_V_we0; + end else begin + layer4_out_109_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_10_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_10_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_10_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_10_V_address0; + end else begin + layer4_out_10_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_10_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_10_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_10_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_10_V_ce0; + end else begin + layer4_out_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_10_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_10_V_we0; + end else begin + layer4_out_10_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_110_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_110_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_110_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_110_V_address0; + end else begin + layer4_out_110_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_110_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_110_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_110_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_110_V_ce0; + end else begin + layer4_out_110_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_110_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_110_V_we0; + end else begin + layer4_out_110_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_111_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_111_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_111_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_111_V_address0; + end else begin + layer4_out_111_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_111_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_111_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_111_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_111_V_ce0; + end else begin + layer4_out_111_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_111_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_111_V_we0; + end else begin + layer4_out_111_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_112_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_112_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_112_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_112_V_address0; + end else begin + layer4_out_112_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_112_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_112_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_112_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_112_V_ce0; + end else begin + layer4_out_112_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_112_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_112_V_we0; + end else begin + layer4_out_112_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_113_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_113_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_113_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_113_V_address0; + end else begin + layer4_out_113_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_113_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_113_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_113_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_113_V_ce0; + end else begin + layer4_out_113_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_113_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_113_V_we0; + end else begin + layer4_out_113_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_114_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_114_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_114_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_114_V_address0; + end else begin + layer4_out_114_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_114_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_114_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_114_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_114_V_ce0; + end else begin + layer4_out_114_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_114_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_114_V_we0; + end else begin + layer4_out_114_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_115_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_115_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_115_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_115_V_address0; + end else begin + layer4_out_115_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_115_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_115_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_115_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_115_V_ce0; + end else begin + layer4_out_115_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_115_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_115_V_we0; + end else begin + layer4_out_115_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_116_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_116_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_116_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_116_V_address0; + end else begin + layer4_out_116_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_116_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_116_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_116_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_116_V_ce0; + end else begin + layer4_out_116_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_116_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_116_V_we0; + end else begin + layer4_out_116_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_117_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_117_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_117_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_117_V_address0; + end else begin + layer4_out_117_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_117_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_117_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_117_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_117_V_ce0; + end else begin + layer4_out_117_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_117_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_117_V_we0; + end else begin + layer4_out_117_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_118_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_118_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_118_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_118_V_address0; + end else begin + layer4_out_118_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_118_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_118_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_118_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_118_V_ce0; + end else begin + layer4_out_118_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_118_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_118_V_we0; + end else begin + layer4_out_118_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_119_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_119_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_119_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_119_V_address0; + end else begin + layer4_out_119_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_119_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_119_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_119_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_119_V_ce0; + end else begin + layer4_out_119_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_119_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_119_V_we0; + end else begin + layer4_out_119_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_11_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_11_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_11_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_11_V_address0; + end else begin + layer4_out_11_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_11_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_11_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_11_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_11_V_ce0; + end else begin + layer4_out_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_11_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_11_V_we0; + end else begin + layer4_out_11_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_120_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_120_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_120_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_120_V_address0; + end else begin + layer4_out_120_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_120_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_120_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_120_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_120_V_ce0; + end else begin + layer4_out_120_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_120_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_120_V_we0; + end else begin + layer4_out_120_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_121_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_121_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_121_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_121_V_address0; + end else begin + layer4_out_121_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_121_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_121_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_121_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_121_V_ce0; + end else begin + layer4_out_121_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_121_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_121_V_we0; + end else begin + layer4_out_121_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_122_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_122_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_122_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_122_V_address0; + end else begin + layer4_out_122_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_122_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_122_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_122_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_122_V_ce0; + end else begin + layer4_out_122_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_122_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_122_V_we0; + end else begin + layer4_out_122_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_123_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_123_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_123_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_123_V_address0; + end else begin + layer4_out_123_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_123_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_123_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_123_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_123_V_ce0; + end else begin + layer4_out_123_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_123_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_123_V_we0; + end else begin + layer4_out_123_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_124_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_124_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_124_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_124_V_address0; + end else begin + layer4_out_124_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_124_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_124_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_124_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_124_V_ce0; + end else begin + layer4_out_124_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_124_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_124_V_we0; + end else begin + layer4_out_124_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_125_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_125_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_125_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_125_V_address0; + end else begin + layer4_out_125_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_125_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_125_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_125_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_125_V_ce0; + end else begin + layer4_out_125_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_125_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_125_V_we0; + end else begin + layer4_out_125_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_126_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_126_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_126_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_126_V_address0; + end else begin + layer4_out_126_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_126_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_126_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_126_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_126_V_ce0; + end else begin + layer4_out_126_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_126_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_126_V_we0; + end else begin + layer4_out_126_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_127_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_127_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_127_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_127_V_address0; + end else begin + layer4_out_127_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_127_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_127_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_127_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_127_V_ce0; + end else begin + layer4_out_127_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_127_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_127_V_we0; + end else begin + layer4_out_127_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_12_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_12_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_12_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_12_V_address0; + end else begin + layer4_out_12_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_12_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_12_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_12_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_12_V_ce0; + end else begin + layer4_out_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_12_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_12_V_we0; + end else begin + layer4_out_12_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_13_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_13_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_13_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_13_V_address0; + end else begin + layer4_out_13_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_13_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_13_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_13_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_13_V_ce0; + end else begin + layer4_out_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_13_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_13_V_we0; + end else begin + layer4_out_13_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_14_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_14_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_14_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_14_V_address0; + end else begin + layer4_out_14_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_14_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_14_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_14_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_14_V_ce0; + end else begin + layer4_out_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_14_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_14_V_we0; + end else begin + layer4_out_14_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_15_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_15_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_15_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_15_V_address0; + end else begin + layer4_out_15_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_15_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_15_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_15_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_15_V_ce0; + end else begin + layer4_out_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_15_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_15_V_we0; + end else begin + layer4_out_15_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_16_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_16_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_16_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_16_V_address0; + end else begin + layer4_out_16_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_16_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_16_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_16_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_16_V_ce0; + end else begin + layer4_out_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_16_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_16_V_we0; + end else begin + layer4_out_16_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_17_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_17_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_17_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_17_V_address0; + end else begin + layer4_out_17_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_17_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_17_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_17_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_17_V_ce0; + end else begin + layer4_out_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_17_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_17_V_we0; + end else begin + layer4_out_17_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_18_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_18_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_18_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_18_V_address0; + end else begin + layer4_out_18_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_18_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_18_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_18_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_18_V_ce0; + end else begin + layer4_out_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_18_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_18_V_we0; + end else begin + layer4_out_18_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_19_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_19_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_19_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_19_V_address0; + end else begin + layer4_out_19_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_19_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_19_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_19_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_19_V_ce0; + end else begin + layer4_out_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_19_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_19_V_we0; + end else begin + layer4_out_19_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_1_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_1_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_1_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_1_V_address0; + end else begin + layer4_out_1_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_1_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_1_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_1_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_1_V_ce0; + end else begin + layer4_out_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_1_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_1_V_we0; + end else begin + layer4_out_1_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_20_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_20_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_20_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_20_V_address0; + end else begin + layer4_out_20_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_20_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_20_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_20_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_20_V_ce0; + end else begin + layer4_out_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_20_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_20_V_we0; + end else begin + layer4_out_20_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_21_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_21_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_21_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_21_V_address0; + end else begin + layer4_out_21_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_21_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_21_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_21_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_21_V_ce0; + end else begin + layer4_out_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_21_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_21_V_we0; + end else begin + layer4_out_21_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_22_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_22_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_22_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_22_V_address0; + end else begin + layer4_out_22_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_22_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_22_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_22_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_22_V_ce0; + end else begin + layer4_out_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_22_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_22_V_we0; + end else begin + layer4_out_22_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_23_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_23_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_23_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_23_V_address0; + end else begin + layer4_out_23_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_23_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_23_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_23_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_23_V_ce0; + end else begin + layer4_out_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_23_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_23_V_we0; + end else begin + layer4_out_23_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_24_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_24_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_24_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_24_V_address0; + end else begin + layer4_out_24_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_24_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_24_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_24_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_24_V_ce0; + end else begin + layer4_out_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_24_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_24_V_we0; + end else begin + layer4_out_24_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_25_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_25_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_25_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_25_V_address0; + end else begin + layer4_out_25_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_25_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_25_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_25_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_25_V_ce0; + end else begin + layer4_out_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_25_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_25_V_we0; + end else begin + layer4_out_25_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_26_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_26_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_26_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_26_V_address0; + end else begin + layer4_out_26_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_26_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_26_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_26_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_26_V_ce0; + end else begin + layer4_out_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_26_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_26_V_we0; + end else begin + layer4_out_26_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_27_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_27_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_27_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_27_V_address0; + end else begin + layer4_out_27_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_27_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_27_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_27_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_27_V_ce0; + end else begin + layer4_out_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_27_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_27_V_we0; + end else begin + layer4_out_27_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_28_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_28_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_28_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_28_V_address0; + end else begin + layer4_out_28_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_28_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_28_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_28_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_28_V_ce0; + end else begin + layer4_out_28_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_28_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_28_V_we0; + end else begin + layer4_out_28_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_29_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_29_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_29_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_29_V_address0; + end else begin + layer4_out_29_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_29_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_29_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_29_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_29_V_ce0; + end else begin + layer4_out_29_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_29_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_29_V_we0; + end else begin + layer4_out_29_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_2_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_2_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_2_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_2_V_address0; + end else begin + layer4_out_2_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_2_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_2_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_2_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_2_V_ce0; + end else begin + layer4_out_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_2_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_2_V_we0; + end else begin + layer4_out_2_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_30_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_30_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_30_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_30_V_address0; + end else begin + layer4_out_30_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_30_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_30_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_30_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_30_V_ce0; + end else begin + layer4_out_30_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_30_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_30_V_we0; + end else begin + layer4_out_30_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_31_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_31_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_31_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_31_V_address0; + end else begin + layer4_out_31_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_31_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_31_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_31_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_31_V_ce0; + end else begin + layer4_out_31_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_31_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_31_V_we0; + end else begin + layer4_out_31_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_32_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_32_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_32_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_32_V_address0; + end else begin + layer4_out_32_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_32_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_32_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_32_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_32_V_ce0; + end else begin + layer4_out_32_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_32_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_32_V_we0; + end else begin + layer4_out_32_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_33_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_33_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_33_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_33_V_address0; + end else begin + layer4_out_33_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_33_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_33_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_33_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_33_V_ce0; + end else begin + layer4_out_33_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_33_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_33_V_we0; + end else begin + layer4_out_33_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_34_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_34_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_34_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_34_V_address0; + end else begin + layer4_out_34_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_34_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_34_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_34_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_34_V_ce0; + end else begin + layer4_out_34_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_34_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_34_V_we0; + end else begin + layer4_out_34_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_35_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_35_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_35_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_35_V_address0; + end else begin + layer4_out_35_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_35_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_35_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_35_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_35_V_ce0; + end else begin + layer4_out_35_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_35_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_35_V_we0; + end else begin + layer4_out_35_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_36_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_36_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_36_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_36_V_address0; + end else begin + layer4_out_36_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_36_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_36_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_36_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_36_V_ce0; + end else begin + layer4_out_36_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_36_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_36_V_we0; + end else begin + layer4_out_36_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_37_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_37_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_37_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_37_V_address0; + end else begin + layer4_out_37_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_37_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_37_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_37_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_37_V_ce0; + end else begin + layer4_out_37_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_37_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_37_V_we0; + end else begin + layer4_out_37_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_38_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_38_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_38_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_38_V_address0; + end else begin + layer4_out_38_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_38_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_38_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_38_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_38_V_ce0; + end else begin + layer4_out_38_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_38_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_38_V_we0; + end else begin + layer4_out_38_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_39_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_39_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_39_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_39_V_address0; + end else begin + layer4_out_39_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_39_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_39_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_39_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_39_V_ce0; + end else begin + layer4_out_39_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_39_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_39_V_we0; + end else begin + layer4_out_39_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_3_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_3_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_3_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_3_V_address0; + end else begin + layer4_out_3_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_3_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_3_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_3_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_3_V_ce0; + end else begin + layer4_out_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_3_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_3_V_we0; + end else begin + layer4_out_3_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_40_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_40_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_40_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_40_V_address0; + end else begin + layer4_out_40_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_40_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_40_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_40_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_40_V_ce0; + end else begin + layer4_out_40_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_40_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_40_V_we0; + end else begin + layer4_out_40_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_41_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_41_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_41_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_41_V_address0; + end else begin + layer4_out_41_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_41_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_41_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_41_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_41_V_ce0; + end else begin + layer4_out_41_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_41_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_41_V_we0; + end else begin + layer4_out_41_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_42_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_42_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_42_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_42_V_address0; + end else begin + layer4_out_42_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_42_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_42_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_42_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_42_V_ce0; + end else begin + layer4_out_42_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_42_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_42_V_we0; + end else begin + layer4_out_42_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_43_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_43_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_43_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_43_V_address0; + end else begin + layer4_out_43_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_43_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_43_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_43_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_43_V_ce0; + end else begin + layer4_out_43_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_43_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_43_V_we0; + end else begin + layer4_out_43_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_44_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_44_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_44_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_44_V_address0; + end else begin + layer4_out_44_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_44_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_44_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_44_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_44_V_ce0; + end else begin + layer4_out_44_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_44_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_44_V_we0; + end else begin + layer4_out_44_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_45_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_45_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_45_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_45_V_address0; + end else begin + layer4_out_45_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_45_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_45_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_45_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_45_V_ce0; + end else begin + layer4_out_45_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_45_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_45_V_we0; + end else begin + layer4_out_45_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_46_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_46_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_46_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_46_V_address0; + end else begin + layer4_out_46_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_46_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_46_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_46_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_46_V_ce0; + end else begin + layer4_out_46_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_46_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_46_V_we0; + end else begin + layer4_out_46_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_47_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_47_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_47_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_47_V_address0; + end else begin + layer4_out_47_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_47_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_47_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_47_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_47_V_ce0; + end else begin + layer4_out_47_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_47_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_47_V_we0; + end else begin + layer4_out_47_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_48_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_48_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_48_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_48_V_address0; + end else begin + layer4_out_48_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_48_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_48_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_48_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_48_V_ce0; + end else begin + layer4_out_48_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_48_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_48_V_we0; + end else begin + layer4_out_48_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_49_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_49_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_49_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_49_V_address0; + end else begin + layer4_out_49_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_49_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_49_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_49_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_49_V_ce0; + end else begin + layer4_out_49_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_49_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_49_V_we0; + end else begin + layer4_out_49_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_4_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_4_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_4_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_4_V_address0; + end else begin + layer4_out_4_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_4_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_4_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_4_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_4_V_ce0; + end else begin + layer4_out_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_4_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_4_V_we0; + end else begin + layer4_out_4_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_50_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_50_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_50_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_50_V_address0; + end else begin + layer4_out_50_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_50_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_50_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_50_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_50_V_ce0; + end else begin + layer4_out_50_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_50_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_50_V_we0; + end else begin + layer4_out_50_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_51_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_51_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_51_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_51_V_address0; + end else begin + layer4_out_51_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_51_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_51_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_51_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_51_V_ce0; + end else begin + layer4_out_51_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_51_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_51_V_we0; + end else begin + layer4_out_51_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_52_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_52_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_52_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_52_V_address0; + end else begin + layer4_out_52_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_52_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_52_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_52_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_52_V_ce0; + end else begin + layer4_out_52_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_52_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_52_V_we0; + end else begin + layer4_out_52_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_53_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_53_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_53_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_53_V_address0; + end else begin + layer4_out_53_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_53_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_53_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_53_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_53_V_ce0; + end else begin + layer4_out_53_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_53_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_53_V_we0; + end else begin + layer4_out_53_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_54_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_54_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_54_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_54_V_address0; + end else begin + layer4_out_54_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_54_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_54_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_54_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_54_V_ce0; + end else begin + layer4_out_54_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_54_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_54_V_we0; + end else begin + layer4_out_54_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_55_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_55_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_55_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_55_V_address0; + end else begin + layer4_out_55_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_55_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_55_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_55_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_55_V_ce0; + end else begin + layer4_out_55_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_55_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_55_V_we0; + end else begin + layer4_out_55_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_56_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_56_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_56_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_56_V_address0; + end else begin + layer4_out_56_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_56_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_56_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_56_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_56_V_ce0; + end else begin + layer4_out_56_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_56_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_56_V_we0; + end else begin + layer4_out_56_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_57_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_57_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_57_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_57_V_address0; + end else begin + layer4_out_57_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_57_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_57_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_57_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_57_V_ce0; + end else begin + layer4_out_57_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_57_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_57_V_we0; + end else begin + layer4_out_57_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_58_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_58_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_58_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_58_V_address0; + end else begin + layer4_out_58_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_58_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_58_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_58_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_58_V_ce0; + end else begin + layer4_out_58_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_58_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_58_V_we0; + end else begin + layer4_out_58_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_59_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_59_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_59_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_59_V_address0; + end else begin + layer4_out_59_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_59_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_59_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_59_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_59_V_ce0; + end else begin + layer4_out_59_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_59_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_59_V_we0; + end else begin + layer4_out_59_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_5_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_5_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_5_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_5_V_address0; + end else begin + layer4_out_5_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_5_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_5_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_5_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_5_V_ce0; + end else begin + layer4_out_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_5_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_5_V_we0; + end else begin + layer4_out_5_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_60_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_60_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_60_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_60_V_address0; + end else begin + layer4_out_60_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_60_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_60_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_60_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_60_V_ce0; + end else begin + layer4_out_60_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_60_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_60_V_we0; + end else begin + layer4_out_60_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_61_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_61_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_61_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_61_V_address0; + end else begin + layer4_out_61_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_61_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_61_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_61_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_61_V_ce0; + end else begin + layer4_out_61_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_61_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_61_V_we0; + end else begin + layer4_out_61_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_62_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_62_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_62_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_62_V_address0; + end else begin + layer4_out_62_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_62_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_62_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_62_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_62_V_ce0; + end else begin + layer4_out_62_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_62_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_62_V_we0; + end else begin + layer4_out_62_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_63_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_63_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_63_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_63_V_address0; + end else begin + layer4_out_63_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_63_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_63_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_63_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_63_V_ce0; + end else begin + layer4_out_63_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_63_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_63_V_we0; + end else begin + layer4_out_63_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_64_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_64_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_64_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_64_V_address0; + end else begin + layer4_out_64_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_64_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_64_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_64_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_64_V_ce0; + end else begin + layer4_out_64_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_64_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_64_V_we0; + end else begin + layer4_out_64_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_65_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_65_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_65_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_65_V_address0; + end else begin + layer4_out_65_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_65_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_65_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_65_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_65_V_ce0; + end else begin + layer4_out_65_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_65_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_65_V_we0; + end else begin + layer4_out_65_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_66_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_66_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_66_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_66_V_address0; + end else begin + layer4_out_66_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_66_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_66_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_66_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_66_V_ce0; + end else begin + layer4_out_66_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_66_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_66_V_we0; + end else begin + layer4_out_66_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_67_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_67_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_67_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_67_V_address0; + end else begin + layer4_out_67_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_67_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_67_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_67_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_67_V_ce0; + end else begin + layer4_out_67_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_67_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_67_V_we0; + end else begin + layer4_out_67_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_68_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_68_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_68_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_68_V_address0; + end else begin + layer4_out_68_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_68_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_68_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_68_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_68_V_ce0; + end else begin + layer4_out_68_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_68_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_68_V_we0; + end else begin + layer4_out_68_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_69_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_69_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_69_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_69_V_address0; + end else begin + layer4_out_69_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_69_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_69_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_69_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_69_V_ce0; + end else begin + layer4_out_69_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_69_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_69_V_we0; + end else begin + layer4_out_69_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_6_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_6_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_6_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_6_V_address0; + end else begin + layer4_out_6_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_6_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_6_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_6_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_6_V_ce0; + end else begin + layer4_out_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_6_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_6_V_we0; + end else begin + layer4_out_6_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_70_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_70_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_70_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_70_V_address0; + end else begin + layer4_out_70_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_70_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_70_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_70_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_70_V_ce0; + end else begin + layer4_out_70_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_70_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_70_V_we0; + end else begin + layer4_out_70_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_71_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_71_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_71_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_71_V_address0; + end else begin + layer4_out_71_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_71_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_71_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_71_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_71_V_ce0; + end else begin + layer4_out_71_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_71_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_71_V_we0; + end else begin + layer4_out_71_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_72_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_72_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_72_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_72_V_address0; + end else begin + layer4_out_72_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_72_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_72_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_72_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_72_V_ce0; + end else begin + layer4_out_72_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_72_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_72_V_we0; + end else begin + layer4_out_72_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_73_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_73_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_73_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_73_V_address0; + end else begin + layer4_out_73_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_73_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_73_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_73_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_73_V_ce0; + end else begin + layer4_out_73_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_73_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_73_V_we0; + end else begin + layer4_out_73_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_74_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_74_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_74_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_74_V_address0; + end else begin + layer4_out_74_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_74_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_74_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_74_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_74_V_ce0; + end else begin + layer4_out_74_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_74_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_74_V_we0; + end else begin + layer4_out_74_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_75_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_75_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_75_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_75_V_address0; + end else begin + layer4_out_75_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_75_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_75_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_75_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_75_V_ce0; + end else begin + layer4_out_75_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_75_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_75_V_we0; + end else begin + layer4_out_75_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_76_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_76_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_76_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_76_V_address0; + end else begin + layer4_out_76_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_76_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_76_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_76_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_76_V_ce0; + end else begin + layer4_out_76_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_76_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_76_V_we0; + end else begin + layer4_out_76_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_77_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_77_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_77_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_77_V_address0; + end else begin + layer4_out_77_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_77_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_77_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_77_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_77_V_ce0; + end else begin + layer4_out_77_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_77_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_77_V_we0; + end else begin + layer4_out_77_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_78_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_78_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_78_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_78_V_address0; + end else begin + layer4_out_78_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_78_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_78_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_78_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_78_V_ce0; + end else begin + layer4_out_78_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_78_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_78_V_we0; + end else begin + layer4_out_78_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_79_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_79_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_79_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_79_V_address0; + end else begin + layer4_out_79_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_79_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_79_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_79_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_79_V_ce0; + end else begin + layer4_out_79_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_79_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_79_V_we0; + end else begin + layer4_out_79_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_7_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_7_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_7_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_7_V_address0; + end else begin + layer4_out_7_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_7_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_7_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_7_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_7_V_ce0; + end else begin + layer4_out_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_7_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_7_V_we0; + end else begin + layer4_out_7_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_80_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_80_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_80_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_80_V_address0; + end else begin + layer4_out_80_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_80_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_80_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_80_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_80_V_ce0; + end else begin + layer4_out_80_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_80_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_80_V_we0; + end else begin + layer4_out_80_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_81_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_81_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_81_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_81_V_address0; + end else begin + layer4_out_81_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_81_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_81_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_81_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_81_V_ce0; + end else begin + layer4_out_81_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_81_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_81_V_we0; + end else begin + layer4_out_81_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_82_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_82_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_82_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_82_V_address0; + end else begin + layer4_out_82_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_82_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_82_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_82_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_82_V_ce0; + end else begin + layer4_out_82_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_82_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_82_V_we0; + end else begin + layer4_out_82_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_83_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_83_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_83_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_83_V_address0; + end else begin + layer4_out_83_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_83_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_83_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_83_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_83_V_ce0; + end else begin + layer4_out_83_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_83_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_83_V_we0; + end else begin + layer4_out_83_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_84_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_84_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_84_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_84_V_address0; + end else begin + layer4_out_84_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_84_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_84_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_84_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_84_V_ce0; + end else begin + layer4_out_84_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_84_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_84_V_we0; + end else begin + layer4_out_84_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_85_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_85_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_85_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_85_V_address0; + end else begin + layer4_out_85_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_85_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_85_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_85_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_85_V_ce0; + end else begin + layer4_out_85_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_85_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_85_V_we0; + end else begin + layer4_out_85_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_86_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_86_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_86_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_86_V_address0; + end else begin + layer4_out_86_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_86_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_86_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_86_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_86_V_ce0; + end else begin + layer4_out_86_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_86_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_86_V_we0; + end else begin + layer4_out_86_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_87_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_87_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_87_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_87_V_address0; + end else begin + layer4_out_87_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_87_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_87_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_87_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_87_V_ce0; + end else begin + layer4_out_87_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_87_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_87_V_we0; + end else begin + layer4_out_87_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_88_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_88_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_88_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_88_V_address0; + end else begin + layer4_out_88_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_88_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_88_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_88_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_88_V_ce0; + end else begin + layer4_out_88_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_88_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_88_V_we0; + end else begin + layer4_out_88_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_89_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_89_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_89_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_89_V_address0; + end else begin + layer4_out_89_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_89_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_89_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_89_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_89_V_ce0; + end else begin + layer4_out_89_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_89_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_89_V_we0; + end else begin + layer4_out_89_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_8_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_8_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_8_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_8_V_address0; + end else begin + layer4_out_8_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_8_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_8_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_8_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_8_V_ce0; + end else begin + layer4_out_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_8_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_8_V_we0; + end else begin + layer4_out_8_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_90_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_90_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_90_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_90_V_address0; + end else begin + layer4_out_90_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_90_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_90_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_90_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_90_V_ce0; + end else begin + layer4_out_90_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_90_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_90_V_we0; + end else begin + layer4_out_90_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_91_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_91_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_91_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_91_V_address0; + end else begin + layer4_out_91_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_91_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_91_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_91_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_91_V_ce0; + end else begin + layer4_out_91_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_91_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_91_V_we0; + end else begin + layer4_out_91_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_92_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_92_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_92_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_92_V_address0; + end else begin + layer4_out_92_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_92_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_92_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_92_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_92_V_ce0; + end else begin + layer4_out_92_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_92_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_92_V_we0; + end else begin + layer4_out_92_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_93_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_93_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_93_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_93_V_address0; + end else begin + layer4_out_93_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_93_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_93_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_93_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_93_V_ce0; + end else begin + layer4_out_93_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_93_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_93_V_we0; + end else begin + layer4_out_93_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_94_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_94_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_94_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_94_V_address0; + end else begin + layer4_out_94_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_94_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_94_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_94_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_94_V_ce0; + end else begin + layer4_out_94_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_94_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_94_V_we0; + end else begin + layer4_out_94_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_95_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_95_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_95_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_95_V_address0; + end else begin + layer4_out_95_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_95_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_95_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_95_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_95_V_ce0; + end else begin + layer4_out_95_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_95_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_95_V_we0; + end else begin + layer4_out_95_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_96_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_96_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_96_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_96_V_address0; + end else begin + layer4_out_96_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_96_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_96_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_96_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_96_V_ce0; + end else begin + layer4_out_96_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_96_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_96_V_we0; + end else begin + layer4_out_96_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_97_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_97_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_97_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_97_V_address0; + end else begin + layer4_out_97_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_97_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_97_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_97_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_97_V_ce0; + end else begin + layer4_out_97_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_97_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_97_V_we0; + end else begin + layer4_out_97_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_98_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_98_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_98_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_98_V_address0; + end else begin + layer4_out_98_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_98_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_98_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_98_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_98_V_ce0; + end else begin + layer4_out_98_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_98_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_98_V_we0; + end else begin + layer4_out_98_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_99_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_99_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_99_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_99_V_address0; + end else begin + layer4_out_99_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_99_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_99_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_99_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_99_V_ce0; + end else begin + layer4_out_99_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_99_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_99_V_we0; + end else begin + layer4_out_99_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_9_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_9_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_9_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_9_V_address0; + end else begin + layer4_out_9_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_9_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_9_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer4_out_9_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_data_9_V_ce0; + end else begin + layer4_out_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state4 == ap_CS_fsm)) begin + layer4_out_9_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_res_9_V_we0; + end else begin + layer4_out_9_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_0_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_0_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_0_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_0_V_address0; + end else begin + layer5_out_0_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_0_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_0_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_0_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_0_V_ce0; + end else begin + layer5_out_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_0_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_0_V_we0; + end else begin + layer5_out_0_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_100_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_100_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_100_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_100_V_address0; + end else begin + layer5_out_100_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_100_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_100_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_100_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_100_V_ce0; + end else begin + layer5_out_100_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_100_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_100_V_we0; + end else begin + layer5_out_100_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_101_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_101_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_101_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_101_V_address0; + end else begin + layer5_out_101_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_101_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_101_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_101_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_101_V_ce0; + end else begin + layer5_out_101_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_101_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_101_V_we0; + end else begin + layer5_out_101_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_102_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_102_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_102_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_102_V_address0; + end else begin + layer5_out_102_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_102_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_102_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_102_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_102_V_ce0; + end else begin + layer5_out_102_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_102_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_102_V_we0; + end else begin + layer5_out_102_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_103_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_103_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_103_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_103_V_address0; + end else begin + layer5_out_103_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_103_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_103_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_103_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_103_V_ce0; + end else begin + layer5_out_103_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_103_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_103_V_we0; + end else begin + layer5_out_103_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_104_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_104_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_104_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_104_V_address0; + end else begin + layer5_out_104_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_104_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_104_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_104_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_104_V_ce0; + end else begin + layer5_out_104_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_104_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_104_V_we0; + end else begin + layer5_out_104_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_105_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_105_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_105_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_105_V_address0; + end else begin + layer5_out_105_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_105_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_105_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_105_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_105_V_ce0; + end else begin + layer5_out_105_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_105_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_105_V_we0; + end else begin + layer5_out_105_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_106_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_106_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_106_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_106_V_address0; + end else begin + layer5_out_106_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_106_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_106_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_106_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_106_V_ce0; + end else begin + layer5_out_106_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_106_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_106_V_we0; + end else begin + layer5_out_106_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_107_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_107_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_107_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_107_V_address0; + end else begin + layer5_out_107_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_107_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_107_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_107_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_107_V_ce0; + end else begin + layer5_out_107_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_107_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_107_V_we0; + end else begin + layer5_out_107_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_108_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_108_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_108_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_108_V_address0; + end else begin + layer5_out_108_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_108_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_108_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_108_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_108_V_ce0; + end else begin + layer5_out_108_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_108_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_108_V_we0; + end else begin + layer5_out_108_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_109_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_109_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_109_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_109_V_address0; + end else begin + layer5_out_109_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_109_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_109_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_109_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_109_V_ce0; + end else begin + layer5_out_109_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_109_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_109_V_we0; + end else begin + layer5_out_109_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_10_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_10_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_10_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_10_V_address0; + end else begin + layer5_out_10_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_10_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_10_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_10_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_10_V_ce0; + end else begin + layer5_out_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_10_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_10_V_we0; + end else begin + layer5_out_10_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_110_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_110_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_110_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_110_V_address0; + end else begin + layer5_out_110_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_110_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_110_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_110_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_110_V_ce0; + end else begin + layer5_out_110_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_110_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_110_V_we0; + end else begin + layer5_out_110_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_111_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_111_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_111_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_111_V_address0; + end else begin + layer5_out_111_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_111_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_111_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_111_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_111_V_ce0; + end else begin + layer5_out_111_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_111_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_111_V_we0; + end else begin + layer5_out_111_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_112_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_112_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_112_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_112_V_address0; + end else begin + layer5_out_112_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_112_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_112_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_112_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_112_V_ce0; + end else begin + layer5_out_112_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_112_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_112_V_we0; + end else begin + layer5_out_112_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_113_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_113_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_113_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_113_V_address0; + end else begin + layer5_out_113_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_113_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_113_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_113_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_113_V_ce0; + end else begin + layer5_out_113_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_113_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_113_V_we0; + end else begin + layer5_out_113_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_114_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_114_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_114_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_114_V_address0; + end else begin + layer5_out_114_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_114_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_114_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_114_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_114_V_ce0; + end else begin + layer5_out_114_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_114_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_114_V_we0; + end else begin + layer5_out_114_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_115_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_115_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_115_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_115_V_address0; + end else begin + layer5_out_115_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_115_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_115_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_115_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_115_V_ce0; + end else begin + layer5_out_115_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_115_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_115_V_we0; + end else begin + layer5_out_115_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_116_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_116_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_116_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_116_V_address0; + end else begin + layer5_out_116_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_116_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_116_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_116_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_116_V_ce0; + end else begin + layer5_out_116_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_116_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_116_V_we0; + end else begin + layer5_out_116_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_117_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_117_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_117_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_117_V_address0; + end else begin + layer5_out_117_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_117_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_117_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_117_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_117_V_ce0; + end else begin + layer5_out_117_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_117_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_117_V_we0; + end else begin + layer5_out_117_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_118_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_118_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_118_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_118_V_address0; + end else begin + layer5_out_118_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_118_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_118_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_118_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_118_V_ce0; + end else begin + layer5_out_118_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_118_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_118_V_we0; + end else begin + layer5_out_118_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_119_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_119_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_119_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_119_V_address0; + end else begin + layer5_out_119_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_119_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_119_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_119_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_119_V_ce0; + end else begin + layer5_out_119_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_119_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_119_V_we0; + end else begin + layer5_out_119_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_11_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_11_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_11_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_11_V_address0; + end else begin + layer5_out_11_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_11_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_11_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_11_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_11_V_ce0; + end else begin + layer5_out_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_11_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_11_V_we0; + end else begin + layer5_out_11_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_120_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_120_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_120_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_120_V_address0; + end else begin + layer5_out_120_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_120_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_120_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_120_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_120_V_ce0; + end else begin + layer5_out_120_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_120_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_120_V_we0; + end else begin + layer5_out_120_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_121_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_121_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_121_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_121_V_address0; + end else begin + layer5_out_121_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_121_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_121_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_121_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_121_V_ce0; + end else begin + layer5_out_121_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_121_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_121_V_we0; + end else begin + layer5_out_121_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_122_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_122_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_122_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_122_V_address0; + end else begin + layer5_out_122_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_122_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_122_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_122_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_122_V_ce0; + end else begin + layer5_out_122_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_122_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_122_V_we0; + end else begin + layer5_out_122_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_123_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_123_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_123_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_123_V_address0; + end else begin + layer5_out_123_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_123_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_123_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_123_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_123_V_ce0; + end else begin + layer5_out_123_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_123_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_123_V_we0; + end else begin + layer5_out_123_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_124_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_124_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_124_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_124_V_address0; + end else begin + layer5_out_124_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_124_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_124_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_124_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_124_V_ce0; + end else begin + layer5_out_124_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_124_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_124_V_we0; + end else begin + layer5_out_124_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_125_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_125_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_125_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_125_V_address0; + end else begin + layer5_out_125_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_125_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_125_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_125_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_125_V_ce0; + end else begin + layer5_out_125_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_125_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_125_V_we0; + end else begin + layer5_out_125_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_126_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_126_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_126_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_126_V_address0; + end else begin + layer5_out_126_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_126_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_126_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_126_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_126_V_ce0; + end else begin + layer5_out_126_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_126_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_126_V_we0; + end else begin + layer5_out_126_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_127_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_127_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_127_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_127_V_address0; + end else begin + layer5_out_127_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_127_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_127_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_127_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_127_V_ce0; + end else begin + layer5_out_127_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_127_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_127_V_we0; + end else begin + layer5_out_127_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_12_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_12_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_12_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_12_V_address0; + end else begin + layer5_out_12_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_12_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_12_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_12_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_12_V_ce0; + end else begin + layer5_out_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_12_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_12_V_we0; + end else begin + layer5_out_12_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_13_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_13_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_13_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_13_V_address0; + end else begin + layer5_out_13_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_13_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_13_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_13_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_13_V_ce0; + end else begin + layer5_out_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_13_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_13_V_we0; + end else begin + layer5_out_13_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_14_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_14_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_14_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_14_V_address0; + end else begin + layer5_out_14_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_14_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_14_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_14_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_14_V_ce0; + end else begin + layer5_out_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_14_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_14_V_we0; + end else begin + layer5_out_14_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_15_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_15_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_15_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_15_V_address0; + end else begin + layer5_out_15_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_15_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_15_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_15_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_15_V_ce0; + end else begin + layer5_out_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_15_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_15_V_we0; + end else begin + layer5_out_15_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_16_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_16_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_16_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_16_V_address0; + end else begin + layer5_out_16_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_16_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_16_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_16_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_16_V_ce0; + end else begin + layer5_out_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_16_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_16_V_we0; + end else begin + layer5_out_16_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_17_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_17_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_17_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_17_V_address0; + end else begin + layer5_out_17_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_17_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_17_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_17_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_17_V_ce0; + end else begin + layer5_out_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_17_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_17_V_we0; + end else begin + layer5_out_17_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_18_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_18_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_18_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_18_V_address0; + end else begin + layer5_out_18_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_18_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_18_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_18_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_18_V_ce0; + end else begin + layer5_out_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_18_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_18_V_we0; + end else begin + layer5_out_18_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_19_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_19_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_19_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_19_V_address0; + end else begin + layer5_out_19_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_19_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_19_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_19_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_19_V_ce0; + end else begin + layer5_out_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_19_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_19_V_we0; + end else begin + layer5_out_19_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_1_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_1_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_1_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_1_V_address0; + end else begin + layer5_out_1_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_1_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_1_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_1_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_1_V_ce0; + end else begin + layer5_out_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_1_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_1_V_we0; + end else begin + layer5_out_1_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_20_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_20_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_20_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_20_V_address0; + end else begin + layer5_out_20_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_20_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_20_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_20_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_20_V_ce0; + end else begin + layer5_out_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_20_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_20_V_we0; + end else begin + layer5_out_20_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_21_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_21_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_21_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_21_V_address0; + end else begin + layer5_out_21_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_21_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_21_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_21_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_21_V_ce0; + end else begin + layer5_out_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_21_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_21_V_we0; + end else begin + layer5_out_21_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_22_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_22_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_22_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_22_V_address0; + end else begin + layer5_out_22_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_22_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_22_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_22_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_22_V_ce0; + end else begin + layer5_out_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_22_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_22_V_we0; + end else begin + layer5_out_22_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_23_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_23_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_23_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_23_V_address0; + end else begin + layer5_out_23_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_23_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_23_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_23_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_23_V_ce0; + end else begin + layer5_out_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_23_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_23_V_we0; + end else begin + layer5_out_23_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_24_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_24_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_24_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_24_V_address0; + end else begin + layer5_out_24_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_24_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_24_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_24_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_24_V_ce0; + end else begin + layer5_out_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_24_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_24_V_we0; + end else begin + layer5_out_24_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_25_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_25_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_25_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_25_V_address0; + end else begin + layer5_out_25_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_25_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_25_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_25_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_25_V_ce0; + end else begin + layer5_out_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_25_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_25_V_we0; + end else begin + layer5_out_25_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_26_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_26_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_26_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_26_V_address0; + end else begin + layer5_out_26_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_26_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_26_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_26_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_26_V_ce0; + end else begin + layer5_out_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_26_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_26_V_we0; + end else begin + layer5_out_26_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_27_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_27_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_27_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_27_V_address0; + end else begin + layer5_out_27_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_27_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_27_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_27_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_27_V_ce0; + end else begin + layer5_out_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_27_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_27_V_we0; + end else begin + layer5_out_27_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_28_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_28_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_28_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_28_V_address0; + end else begin + layer5_out_28_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_28_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_28_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_28_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_28_V_ce0; + end else begin + layer5_out_28_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_28_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_28_V_we0; + end else begin + layer5_out_28_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_29_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_29_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_29_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_29_V_address0; + end else begin + layer5_out_29_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_29_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_29_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_29_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_29_V_ce0; + end else begin + layer5_out_29_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_29_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_29_V_we0; + end else begin + layer5_out_29_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_2_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_2_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_2_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_2_V_address0; + end else begin + layer5_out_2_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_2_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_2_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_2_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_2_V_ce0; + end else begin + layer5_out_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_2_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_2_V_we0; + end else begin + layer5_out_2_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_30_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_30_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_30_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_30_V_address0; + end else begin + layer5_out_30_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_30_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_30_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_30_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_30_V_ce0; + end else begin + layer5_out_30_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_30_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_30_V_we0; + end else begin + layer5_out_30_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_31_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_31_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_31_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_31_V_address0; + end else begin + layer5_out_31_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_31_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_31_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_31_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_31_V_ce0; + end else begin + layer5_out_31_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_31_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_31_V_we0; + end else begin + layer5_out_31_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_32_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_32_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_32_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_32_V_address0; + end else begin + layer5_out_32_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_32_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_32_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_32_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_32_V_ce0; + end else begin + layer5_out_32_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_32_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_32_V_we0; + end else begin + layer5_out_32_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_33_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_33_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_33_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_33_V_address0; + end else begin + layer5_out_33_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_33_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_33_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_33_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_33_V_ce0; + end else begin + layer5_out_33_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_33_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_33_V_we0; + end else begin + layer5_out_33_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_34_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_34_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_34_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_34_V_address0; + end else begin + layer5_out_34_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_34_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_34_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_34_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_34_V_ce0; + end else begin + layer5_out_34_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_34_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_34_V_we0; + end else begin + layer5_out_34_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_35_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_35_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_35_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_35_V_address0; + end else begin + layer5_out_35_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_35_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_35_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_35_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_35_V_ce0; + end else begin + layer5_out_35_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_35_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_35_V_we0; + end else begin + layer5_out_35_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_36_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_36_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_36_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_36_V_address0; + end else begin + layer5_out_36_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_36_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_36_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_36_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_36_V_ce0; + end else begin + layer5_out_36_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_36_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_36_V_we0; + end else begin + layer5_out_36_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_37_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_37_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_37_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_37_V_address0; + end else begin + layer5_out_37_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_37_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_37_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_37_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_37_V_ce0; + end else begin + layer5_out_37_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_37_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_37_V_we0; + end else begin + layer5_out_37_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_38_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_38_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_38_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_38_V_address0; + end else begin + layer5_out_38_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_38_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_38_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_38_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_38_V_ce0; + end else begin + layer5_out_38_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_38_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_38_V_we0; + end else begin + layer5_out_38_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_39_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_39_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_39_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_39_V_address0; + end else begin + layer5_out_39_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_39_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_39_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_39_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_39_V_ce0; + end else begin + layer5_out_39_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_39_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_39_V_we0; + end else begin + layer5_out_39_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_3_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_3_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_3_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_3_V_address0; + end else begin + layer5_out_3_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_3_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_3_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_3_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_3_V_ce0; + end else begin + layer5_out_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_3_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_3_V_we0; + end else begin + layer5_out_3_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_40_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_40_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_40_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_40_V_address0; + end else begin + layer5_out_40_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_40_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_40_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_40_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_40_V_ce0; + end else begin + layer5_out_40_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_40_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_40_V_we0; + end else begin + layer5_out_40_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_41_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_41_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_41_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_41_V_address0; + end else begin + layer5_out_41_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_41_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_41_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_41_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_41_V_ce0; + end else begin + layer5_out_41_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_41_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_41_V_we0; + end else begin + layer5_out_41_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_42_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_42_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_42_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_42_V_address0; + end else begin + layer5_out_42_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_42_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_42_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_42_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_42_V_ce0; + end else begin + layer5_out_42_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_42_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_42_V_we0; + end else begin + layer5_out_42_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_43_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_43_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_43_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_43_V_address0; + end else begin + layer5_out_43_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_43_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_43_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_43_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_43_V_ce0; + end else begin + layer5_out_43_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_43_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_43_V_we0; + end else begin + layer5_out_43_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_44_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_44_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_44_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_44_V_address0; + end else begin + layer5_out_44_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_44_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_44_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_44_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_44_V_ce0; + end else begin + layer5_out_44_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_44_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_44_V_we0; + end else begin + layer5_out_44_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_45_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_45_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_45_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_45_V_address0; + end else begin + layer5_out_45_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_45_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_45_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_45_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_45_V_ce0; + end else begin + layer5_out_45_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_45_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_45_V_we0; + end else begin + layer5_out_45_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_46_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_46_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_46_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_46_V_address0; + end else begin + layer5_out_46_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_46_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_46_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_46_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_46_V_ce0; + end else begin + layer5_out_46_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_46_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_46_V_we0; + end else begin + layer5_out_46_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_47_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_47_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_47_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_47_V_address0; + end else begin + layer5_out_47_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_47_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_47_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_47_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_47_V_ce0; + end else begin + layer5_out_47_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_47_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_47_V_we0; + end else begin + layer5_out_47_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_48_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_48_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_48_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_48_V_address0; + end else begin + layer5_out_48_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_48_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_48_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_48_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_48_V_ce0; + end else begin + layer5_out_48_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_48_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_48_V_we0; + end else begin + layer5_out_48_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_49_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_49_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_49_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_49_V_address0; + end else begin + layer5_out_49_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_49_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_49_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_49_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_49_V_ce0; + end else begin + layer5_out_49_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_49_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_49_V_we0; + end else begin + layer5_out_49_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_4_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_4_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_4_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_4_V_address0; + end else begin + layer5_out_4_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_4_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_4_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_4_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_4_V_ce0; + end else begin + layer5_out_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_4_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_4_V_we0; + end else begin + layer5_out_4_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_50_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_50_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_50_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_50_V_address0; + end else begin + layer5_out_50_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_50_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_50_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_50_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_50_V_ce0; + end else begin + layer5_out_50_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_50_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_50_V_we0; + end else begin + layer5_out_50_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_51_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_51_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_51_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_51_V_address0; + end else begin + layer5_out_51_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_51_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_51_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_51_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_51_V_ce0; + end else begin + layer5_out_51_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_51_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_51_V_we0; + end else begin + layer5_out_51_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_52_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_52_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_52_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_52_V_address0; + end else begin + layer5_out_52_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_52_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_52_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_52_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_52_V_ce0; + end else begin + layer5_out_52_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_52_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_52_V_we0; + end else begin + layer5_out_52_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_53_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_53_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_53_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_53_V_address0; + end else begin + layer5_out_53_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_53_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_53_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_53_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_53_V_ce0; + end else begin + layer5_out_53_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_53_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_53_V_we0; + end else begin + layer5_out_53_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_54_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_54_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_54_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_54_V_address0; + end else begin + layer5_out_54_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_54_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_54_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_54_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_54_V_ce0; + end else begin + layer5_out_54_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_54_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_54_V_we0; + end else begin + layer5_out_54_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_55_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_55_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_55_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_55_V_address0; + end else begin + layer5_out_55_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_55_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_55_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_55_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_55_V_ce0; + end else begin + layer5_out_55_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_55_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_55_V_we0; + end else begin + layer5_out_55_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_56_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_56_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_56_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_56_V_address0; + end else begin + layer5_out_56_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_56_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_56_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_56_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_56_V_ce0; + end else begin + layer5_out_56_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_56_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_56_V_we0; + end else begin + layer5_out_56_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_57_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_57_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_57_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_57_V_address0; + end else begin + layer5_out_57_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_57_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_57_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_57_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_57_V_ce0; + end else begin + layer5_out_57_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_57_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_57_V_we0; + end else begin + layer5_out_57_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_58_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_58_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_58_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_58_V_address0; + end else begin + layer5_out_58_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_58_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_58_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_58_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_58_V_ce0; + end else begin + layer5_out_58_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_58_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_58_V_we0; + end else begin + layer5_out_58_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_59_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_59_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_59_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_59_V_address0; + end else begin + layer5_out_59_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_59_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_59_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_59_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_59_V_ce0; + end else begin + layer5_out_59_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_59_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_59_V_we0; + end else begin + layer5_out_59_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_5_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_5_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_5_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_5_V_address0; + end else begin + layer5_out_5_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_5_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_5_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_5_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_5_V_ce0; + end else begin + layer5_out_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_5_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_5_V_we0; + end else begin + layer5_out_5_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_60_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_60_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_60_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_60_V_address0; + end else begin + layer5_out_60_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_60_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_60_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_60_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_60_V_ce0; + end else begin + layer5_out_60_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_60_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_60_V_we0; + end else begin + layer5_out_60_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_61_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_61_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_61_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_61_V_address0; + end else begin + layer5_out_61_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_61_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_61_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_61_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_61_V_ce0; + end else begin + layer5_out_61_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_61_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_61_V_we0; + end else begin + layer5_out_61_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_62_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_62_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_62_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_62_V_address0; + end else begin + layer5_out_62_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_62_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_62_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_62_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_62_V_ce0; + end else begin + layer5_out_62_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_62_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_62_V_we0; + end else begin + layer5_out_62_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_63_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_63_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_63_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_63_V_address0; + end else begin + layer5_out_63_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_63_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_63_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_63_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_63_V_ce0; + end else begin + layer5_out_63_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_63_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_63_V_we0; + end else begin + layer5_out_63_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_64_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_64_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_64_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_64_V_address0; + end else begin + layer5_out_64_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_64_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_64_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_64_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_64_V_ce0; + end else begin + layer5_out_64_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_64_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_64_V_we0; + end else begin + layer5_out_64_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_65_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_65_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_65_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_65_V_address0; + end else begin + layer5_out_65_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_65_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_65_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_65_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_65_V_ce0; + end else begin + layer5_out_65_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_65_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_65_V_we0; + end else begin + layer5_out_65_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_66_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_66_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_66_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_66_V_address0; + end else begin + layer5_out_66_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_66_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_66_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_66_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_66_V_ce0; + end else begin + layer5_out_66_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_66_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_66_V_we0; + end else begin + layer5_out_66_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_67_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_67_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_67_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_67_V_address0; + end else begin + layer5_out_67_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_67_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_67_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_67_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_67_V_ce0; + end else begin + layer5_out_67_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_67_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_67_V_we0; + end else begin + layer5_out_67_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_68_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_68_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_68_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_68_V_address0; + end else begin + layer5_out_68_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_68_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_68_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_68_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_68_V_ce0; + end else begin + layer5_out_68_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_68_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_68_V_we0; + end else begin + layer5_out_68_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_69_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_69_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_69_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_69_V_address0; + end else begin + layer5_out_69_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_69_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_69_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_69_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_69_V_ce0; + end else begin + layer5_out_69_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_69_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_69_V_we0; + end else begin + layer5_out_69_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_6_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_6_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_6_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_6_V_address0; + end else begin + layer5_out_6_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_6_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_6_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_6_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_6_V_ce0; + end else begin + layer5_out_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_6_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_6_V_we0; + end else begin + layer5_out_6_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_70_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_70_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_70_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_70_V_address0; + end else begin + layer5_out_70_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_70_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_70_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_70_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_70_V_ce0; + end else begin + layer5_out_70_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_70_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_70_V_we0; + end else begin + layer5_out_70_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_71_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_71_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_71_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_71_V_address0; + end else begin + layer5_out_71_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_71_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_71_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_71_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_71_V_ce0; + end else begin + layer5_out_71_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_71_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_71_V_we0; + end else begin + layer5_out_71_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_72_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_72_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_72_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_72_V_address0; + end else begin + layer5_out_72_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_72_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_72_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_72_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_72_V_ce0; + end else begin + layer5_out_72_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_72_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_72_V_we0; + end else begin + layer5_out_72_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_73_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_73_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_73_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_73_V_address0; + end else begin + layer5_out_73_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_73_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_73_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_73_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_73_V_ce0; + end else begin + layer5_out_73_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_73_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_73_V_we0; + end else begin + layer5_out_73_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_74_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_74_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_74_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_74_V_address0; + end else begin + layer5_out_74_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_74_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_74_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_74_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_74_V_ce0; + end else begin + layer5_out_74_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_74_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_74_V_we0; + end else begin + layer5_out_74_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_75_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_75_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_75_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_75_V_address0; + end else begin + layer5_out_75_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_75_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_75_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_75_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_75_V_ce0; + end else begin + layer5_out_75_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_75_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_75_V_we0; + end else begin + layer5_out_75_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_76_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_76_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_76_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_76_V_address0; + end else begin + layer5_out_76_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_76_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_76_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_76_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_76_V_ce0; + end else begin + layer5_out_76_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_76_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_76_V_we0; + end else begin + layer5_out_76_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_77_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_77_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_77_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_77_V_address0; + end else begin + layer5_out_77_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_77_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_77_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_77_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_77_V_ce0; + end else begin + layer5_out_77_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_77_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_77_V_we0; + end else begin + layer5_out_77_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_78_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_78_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_78_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_78_V_address0; + end else begin + layer5_out_78_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_78_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_78_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_78_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_78_V_ce0; + end else begin + layer5_out_78_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_78_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_78_V_we0; + end else begin + layer5_out_78_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_79_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_79_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_79_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_79_V_address0; + end else begin + layer5_out_79_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_79_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_79_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_79_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_79_V_ce0; + end else begin + layer5_out_79_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_79_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_79_V_we0; + end else begin + layer5_out_79_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_7_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_7_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_7_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_7_V_address0; + end else begin + layer5_out_7_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_7_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_7_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_7_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_7_V_ce0; + end else begin + layer5_out_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_7_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_7_V_we0; + end else begin + layer5_out_7_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_80_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_80_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_80_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_80_V_address0; + end else begin + layer5_out_80_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_80_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_80_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_80_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_80_V_ce0; + end else begin + layer5_out_80_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_80_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_80_V_we0; + end else begin + layer5_out_80_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_81_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_81_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_81_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_81_V_address0; + end else begin + layer5_out_81_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_81_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_81_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_81_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_81_V_ce0; + end else begin + layer5_out_81_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_81_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_81_V_we0; + end else begin + layer5_out_81_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_82_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_82_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_82_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_82_V_address0; + end else begin + layer5_out_82_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_82_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_82_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_82_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_82_V_ce0; + end else begin + layer5_out_82_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_82_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_82_V_we0; + end else begin + layer5_out_82_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_83_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_83_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_83_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_83_V_address0; + end else begin + layer5_out_83_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_83_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_83_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_83_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_83_V_ce0; + end else begin + layer5_out_83_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_83_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_83_V_we0; + end else begin + layer5_out_83_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_84_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_84_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_84_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_84_V_address0; + end else begin + layer5_out_84_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_84_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_84_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_84_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_84_V_ce0; + end else begin + layer5_out_84_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_84_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_84_V_we0; + end else begin + layer5_out_84_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_85_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_85_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_85_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_85_V_address0; + end else begin + layer5_out_85_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_85_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_85_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_85_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_85_V_ce0; + end else begin + layer5_out_85_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_85_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_85_V_we0; + end else begin + layer5_out_85_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_86_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_86_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_86_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_86_V_address0; + end else begin + layer5_out_86_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_86_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_86_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_86_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_86_V_ce0; + end else begin + layer5_out_86_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_86_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_86_V_we0; + end else begin + layer5_out_86_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_87_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_87_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_87_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_87_V_address0; + end else begin + layer5_out_87_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_87_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_87_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_87_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_87_V_ce0; + end else begin + layer5_out_87_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_87_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_87_V_we0; + end else begin + layer5_out_87_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_88_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_88_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_88_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_88_V_address0; + end else begin + layer5_out_88_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_88_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_88_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_88_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_88_V_ce0; + end else begin + layer5_out_88_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_88_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_88_V_we0; + end else begin + layer5_out_88_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_89_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_89_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_89_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_89_V_address0; + end else begin + layer5_out_89_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_89_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_89_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_89_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_89_V_ce0; + end else begin + layer5_out_89_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_89_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_89_V_we0; + end else begin + layer5_out_89_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_8_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_8_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_8_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_8_V_address0; + end else begin + layer5_out_8_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_8_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_8_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_8_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_8_V_ce0; + end else begin + layer5_out_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_8_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_8_V_we0; + end else begin + layer5_out_8_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_90_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_90_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_90_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_90_V_address0; + end else begin + layer5_out_90_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_90_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_90_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_90_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_90_V_ce0; + end else begin + layer5_out_90_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_90_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_90_V_we0; + end else begin + layer5_out_90_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_91_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_91_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_91_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_91_V_address0; + end else begin + layer5_out_91_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_91_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_91_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_91_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_91_V_ce0; + end else begin + layer5_out_91_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_91_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_91_V_we0; + end else begin + layer5_out_91_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_92_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_92_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_92_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_92_V_address0; + end else begin + layer5_out_92_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_92_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_92_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_92_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_92_V_ce0; + end else begin + layer5_out_92_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_92_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_92_V_we0; + end else begin + layer5_out_92_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_93_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_93_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_93_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_93_V_address0; + end else begin + layer5_out_93_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_93_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_93_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_93_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_93_V_ce0; + end else begin + layer5_out_93_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_93_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_93_V_we0; + end else begin + layer5_out_93_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_94_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_94_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_94_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_94_V_address0; + end else begin + layer5_out_94_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_94_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_94_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_94_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_94_V_ce0; + end else begin + layer5_out_94_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_94_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_94_V_we0; + end else begin + layer5_out_94_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_95_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_95_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_95_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_95_V_address0; + end else begin + layer5_out_95_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_95_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_95_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_95_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_95_V_ce0; + end else begin + layer5_out_95_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_95_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_95_V_we0; + end else begin + layer5_out_95_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_96_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_96_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_96_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_96_V_address0; + end else begin + layer5_out_96_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_96_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_96_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_96_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_96_V_ce0; + end else begin + layer5_out_96_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_96_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_96_V_we0; + end else begin + layer5_out_96_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_97_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_97_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_97_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_97_V_address0; + end else begin + layer5_out_97_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_97_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_97_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_97_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_97_V_ce0; + end else begin + layer5_out_97_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_97_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_97_V_we0; + end else begin + layer5_out_97_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_98_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_98_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_98_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_98_V_address0; + end else begin + layer5_out_98_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_98_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_98_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_98_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_98_V_ce0; + end else begin + layer5_out_98_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_98_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_98_V_we0; + end else begin + layer5_out_98_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_99_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_99_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_99_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_99_V_address0; + end else begin + layer5_out_99_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_99_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_99_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_99_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_99_V_ce0; + end else begin + layer5_out_99_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_99_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_99_V_we0; + end else begin + layer5_out_99_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_9_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_9_V_address0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_9_V_address0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_9_V_address0; + end else begin + layer5_out_9_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer5_out_9_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_data_9_V_ce0; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_9_V_ce0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_9_V_ce0; + end else begin + layer5_out_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + layer5_out_9_V_we0 = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_res_9_V_we0; + end else begin + layer5_out_9_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_0_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_0_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_0_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_address0; + end else begin + layer7_out_0_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_0_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_0_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_0_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_0_V_ce0; + end else begin + layer7_out_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_0_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_0_V_we0; + end else begin + layer7_out_0_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_100_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_100_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_100_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_address0; + end else begin + layer7_out_100_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_100_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_100_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_100_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_100_V_ce0; + end else begin + layer7_out_100_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_100_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_100_V_we0; + end else begin + layer7_out_100_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_101_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_101_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_101_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_address0; + end else begin + layer7_out_101_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_101_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_101_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_101_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_101_V_ce0; + end else begin + layer7_out_101_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_101_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_101_V_we0; + end else begin + layer7_out_101_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_102_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_102_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_102_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_address0; + end else begin + layer7_out_102_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_102_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_102_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_102_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_102_V_ce0; + end else begin + layer7_out_102_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_102_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_102_V_we0; + end else begin + layer7_out_102_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_103_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_103_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_103_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_address0; + end else begin + layer7_out_103_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_103_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_103_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_103_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_103_V_ce0; + end else begin + layer7_out_103_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_103_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_103_V_we0; + end else begin + layer7_out_103_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_104_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_104_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_104_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_address0; + end else begin + layer7_out_104_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_104_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_104_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_104_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_104_V_ce0; + end else begin + layer7_out_104_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_104_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_104_V_we0; + end else begin + layer7_out_104_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_105_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_105_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_105_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_address0; + end else begin + layer7_out_105_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_105_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_105_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_105_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_105_V_ce0; + end else begin + layer7_out_105_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_105_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_105_V_we0; + end else begin + layer7_out_105_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_106_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_106_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_106_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_address0; + end else begin + layer7_out_106_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_106_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_106_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_106_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_106_V_ce0; + end else begin + layer7_out_106_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_106_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_106_V_we0; + end else begin + layer7_out_106_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_107_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_107_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_107_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_address0; + end else begin + layer7_out_107_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_107_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_107_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_107_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_107_V_ce0; + end else begin + layer7_out_107_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_107_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_107_V_we0; + end else begin + layer7_out_107_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_108_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_108_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_108_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_address0; + end else begin + layer7_out_108_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_108_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_108_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_108_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_108_V_ce0; + end else begin + layer7_out_108_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_108_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_108_V_we0; + end else begin + layer7_out_108_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_109_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_109_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_109_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_address0; + end else begin + layer7_out_109_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_109_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_109_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_109_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_109_V_ce0; + end else begin + layer7_out_109_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_109_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_109_V_we0; + end else begin + layer7_out_109_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_10_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_10_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_10_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_address0; + end else begin + layer7_out_10_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_10_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_10_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_10_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_10_V_ce0; + end else begin + layer7_out_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_10_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_10_V_we0; + end else begin + layer7_out_10_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_110_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_110_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_110_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_address0; + end else begin + layer7_out_110_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_110_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_110_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_110_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_110_V_ce0; + end else begin + layer7_out_110_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_110_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_110_V_we0; + end else begin + layer7_out_110_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_111_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_111_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_111_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_address0; + end else begin + layer7_out_111_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_111_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_111_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_111_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_111_V_ce0; + end else begin + layer7_out_111_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_111_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_111_V_we0; + end else begin + layer7_out_111_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_112_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_112_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_112_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_address0; + end else begin + layer7_out_112_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_112_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_112_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_112_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_112_V_ce0; + end else begin + layer7_out_112_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_112_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_112_V_we0; + end else begin + layer7_out_112_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_113_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_113_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_113_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_address0; + end else begin + layer7_out_113_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_113_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_113_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_113_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_113_V_ce0; + end else begin + layer7_out_113_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_113_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_113_V_we0; + end else begin + layer7_out_113_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_114_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_114_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_114_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_address0; + end else begin + layer7_out_114_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_114_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_114_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_114_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_114_V_ce0; + end else begin + layer7_out_114_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_114_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_114_V_we0; + end else begin + layer7_out_114_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_115_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_115_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_115_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_address0; + end else begin + layer7_out_115_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_115_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_115_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_115_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_115_V_ce0; + end else begin + layer7_out_115_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_115_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_115_V_we0; + end else begin + layer7_out_115_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_116_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_116_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_116_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_address0; + end else begin + layer7_out_116_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_116_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_116_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_116_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_116_V_ce0; + end else begin + layer7_out_116_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_116_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_116_V_we0; + end else begin + layer7_out_116_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_117_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_117_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_117_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_address0; + end else begin + layer7_out_117_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_117_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_117_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_117_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_117_V_ce0; + end else begin + layer7_out_117_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_117_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_117_V_we0; + end else begin + layer7_out_117_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_118_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_118_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_118_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_address0; + end else begin + layer7_out_118_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_118_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_118_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_118_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_118_V_ce0; + end else begin + layer7_out_118_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_118_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_118_V_we0; + end else begin + layer7_out_118_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_119_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_119_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_119_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_address0; + end else begin + layer7_out_119_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_119_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_119_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_119_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_119_V_ce0; + end else begin + layer7_out_119_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_119_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_119_V_we0; + end else begin + layer7_out_119_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_11_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_11_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_11_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_address0; + end else begin + layer7_out_11_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_11_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_11_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_11_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_11_V_ce0; + end else begin + layer7_out_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_11_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_11_V_we0; + end else begin + layer7_out_11_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_120_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_120_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_120_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_address0; + end else begin + layer7_out_120_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_120_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_120_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_120_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_120_V_ce0; + end else begin + layer7_out_120_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_120_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_120_V_we0; + end else begin + layer7_out_120_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_121_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_121_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_121_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_address0; + end else begin + layer7_out_121_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_121_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_121_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_121_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_121_V_ce0; + end else begin + layer7_out_121_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_121_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_121_V_we0; + end else begin + layer7_out_121_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_122_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_122_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_122_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_address0; + end else begin + layer7_out_122_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_122_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_122_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_122_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_122_V_ce0; + end else begin + layer7_out_122_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_122_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_122_V_we0; + end else begin + layer7_out_122_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_123_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_123_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_123_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_address0; + end else begin + layer7_out_123_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_123_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_123_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_123_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_123_V_ce0; + end else begin + layer7_out_123_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_123_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_123_V_we0; + end else begin + layer7_out_123_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_124_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_124_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_124_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_address0; + end else begin + layer7_out_124_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_124_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_124_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_124_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_124_V_ce0; + end else begin + layer7_out_124_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_124_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_124_V_we0; + end else begin + layer7_out_124_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_125_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_125_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_125_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_address0; + end else begin + layer7_out_125_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_125_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_125_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_125_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_125_V_ce0; + end else begin + layer7_out_125_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_125_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_125_V_we0; + end else begin + layer7_out_125_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_126_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_126_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_126_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_address0; + end else begin + layer7_out_126_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_126_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_126_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_126_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_126_V_ce0; + end else begin + layer7_out_126_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_126_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_126_V_we0; + end else begin + layer7_out_126_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_127_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_127_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_127_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_address0; + end else begin + layer7_out_127_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_127_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_127_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_127_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_127_V_ce0; + end else begin + layer7_out_127_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_127_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_127_V_we0; + end else begin + layer7_out_127_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_12_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_12_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_12_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_address0; + end else begin + layer7_out_12_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_12_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_12_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_12_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_12_V_ce0; + end else begin + layer7_out_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_12_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_12_V_we0; + end else begin + layer7_out_12_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_13_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_13_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_13_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_address0; + end else begin + layer7_out_13_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_13_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_13_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_13_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_13_V_ce0; + end else begin + layer7_out_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_13_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_13_V_we0; + end else begin + layer7_out_13_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_14_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_14_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_14_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_address0; + end else begin + layer7_out_14_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_14_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_14_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_14_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_14_V_ce0; + end else begin + layer7_out_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_14_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_14_V_we0; + end else begin + layer7_out_14_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_15_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_15_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_15_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_address0; + end else begin + layer7_out_15_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_15_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_15_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_15_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_15_V_ce0; + end else begin + layer7_out_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_15_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_15_V_we0; + end else begin + layer7_out_15_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_16_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_16_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_16_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_address0; + end else begin + layer7_out_16_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_16_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_16_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_16_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_16_V_ce0; + end else begin + layer7_out_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_16_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_16_V_we0; + end else begin + layer7_out_16_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_17_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_17_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_17_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_address0; + end else begin + layer7_out_17_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_17_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_17_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_17_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_17_V_ce0; + end else begin + layer7_out_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_17_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_17_V_we0; + end else begin + layer7_out_17_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_18_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_18_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_18_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_address0; + end else begin + layer7_out_18_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_18_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_18_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_18_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_18_V_ce0; + end else begin + layer7_out_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_18_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_18_V_we0; + end else begin + layer7_out_18_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_19_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_19_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_19_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_address0; + end else begin + layer7_out_19_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_19_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_19_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_19_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_19_V_ce0; + end else begin + layer7_out_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_19_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_19_V_we0; + end else begin + layer7_out_19_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_1_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_1_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_1_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_address0; + end else begin + layer7_out_1_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_1_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_1_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_1_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_1_V_ce0; + end else begin + layer7_out_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_1_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_1_V_we0; + end else begin + layer7_out_1_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_20_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_20_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_20_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_address0; + end else begin + layer7_out_20_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_20_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_20_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_20_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_20_V_ce0; + end else begin + layer7_out_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_20_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_20_V_we0; + end else begin + layer7_out_20_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_21_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_21_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_21_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_address0; + end else begin + layer7_out_21_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_21_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_21_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_21_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_21_V_ce0; + end else begin + layer7_out_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_21_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_21_V_we0; + end else begin + layer7_out_21_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_22_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_22_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_22_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_address0; + end else begin + layer7_out_22_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_22_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_22_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_22_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_22_V_ce0; + end else begin + layer7_out_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_22_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_22_V_we0; + end else begin + layer7_out_22_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_23_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_23_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_23_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_address0; + end else begin + layer7_out_23_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_23_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_23_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_23_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_23_V_ce0; + end else begin + layer7_out_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_23_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_23_V_we0; + end else begin + layer7_out_23_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_24_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_24_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_24_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_address0; + end else begin + layer7_out_24_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_24_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_24_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_24_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_24_V_ce0; + end else begin + layer7_out_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_24_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_24_V_we0; + end else begin + layer7_out_24_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_25_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_25_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_25_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_address0; + end else begin + layer7_out_25_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_25_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_25_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_25_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_25_V_ce0; + end else begin + layer7_out_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_25_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_25_V_we0; + end else begin + layer7_out_25_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_26_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_26_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_26_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_address0; + end else begin + layer7_out_26_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_26_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_26_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_26_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_26_V_ce0; + end else begin + layer7_out_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_26_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_26_V_we0; + end else begin + layer7_out_26_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_27_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_27_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_27_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_address0; + end else begin + layer7_out_27_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_27_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_27_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_27_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_27_V_ce0; + end else begin + layer7_out_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_27_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_27_V_we0; + end else begin + layer7_out_27_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_28_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_28_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_28_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_address0; + end else begin + layer7_out_28_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_28_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_28_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_28_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_28_V_ce0; + end else begin + layer7_out_28_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_28_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_28_V_we0; + end else begin + layer7_out_28_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_29_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_29_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_29_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_address0; + end else begin + layer7_out_29_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_29_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_29_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_29_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_29_V_ce0; + end else begin + layer7_out_29_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_29_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_29_V_we0; + end else begin + layer7_out_29_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_2_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_2_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_2_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_address0; + end else begin + layer7_out_2_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_2_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_2_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_2_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_2_V_ce0; + end else begin + layer7_out_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_2_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_2_V_we0; + end else begin + layer7_out_2_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_30_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_30_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_30_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_address0; + end else begin + layer7_out_30_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_30_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_30_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_30_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_30_V_ce0; + end else begin + layer7_out_30_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_30_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_30_V_we0; + end else begin + layer7_out_30_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_31_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_31_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_31_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_address0; + end else begin + layer7_out_31_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_31_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_31_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_31_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_31_V_ce0; + end else begin + layer7_out_31_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_31_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_31_V_we0; + end else begin + layer7_out_31_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_32_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_32_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_32_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_address0; + end else begin + layer7_out_32_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_32_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_32_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_32_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_32_V_ce0; + end else begin + layer7_out_32_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_32_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_32_V_we0; + end else begin + layer7_out_32_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_33_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_33_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_33_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_address0; + end else begin + layer7_out_33_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_33_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_33_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_33_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_33_V_ce0; + end else begin + layer7_out_33_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_33_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_33_V_we0; + end else begin + layer7_out_33_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_34_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_34_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_34_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_address0; + end else begin + layer7_out_34_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_34_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_34_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_34_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_34_V_ce0; + end else begin + layer7_out_34_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_34_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_34_V_we0; + end else begin + layer7_out_34_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_35_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_35_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_35_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_address0; + end else begin + layer7_out_35_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_35_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_35_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_35_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_35_V_ce0; + end else begin + layer7_out_35_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_35_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_35_V_we0; + end else begin + layer7_out_35_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_36_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_36_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_36_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_address0; + end else begin + layer7_out_36_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_36_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_36_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_36_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_36_V_ce0; + end else begin + layer7_out_36_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_36_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_36_V_we0; + end else begin + layer7_out_36_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_37_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_37_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_37_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_address0; + end else begin + layer7_out_37_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_37_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_37_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_37_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_37_V_ce0; + end else begin + layer7_out_37_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_37_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_37_V_we0; + end else begin + layer7_out_37_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_38_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_38_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_38_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_address0; + end else begin + layer7_out_38_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_38_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_38_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_38_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_38_V_ce0; + end else begin + layer7_out_38_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_38_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_38_V_we0; + end else begin + layer7_out_38_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_39_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_39_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_39_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_address0; + end else begin + layer7_out_39_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_39_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_39_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_39_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_39_V_ce0; + end else begin + layer7_out_39_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_39_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_39_V_we0; + end else begin + layer7_out_39_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_3_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_3_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_3_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_address0; + end else begin + layer7_out_3_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_3_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_3_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_3_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_3_V_ce0; + end else begin + layer7_out_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_3_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_3_V_we0; + end else begin + layer7_out_3_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_40_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_40_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_40_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_address0; + end else begin + layer7_out_40_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_40_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_40_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_40_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_40_V_ce0; + end else begin + layer7_out_40_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_40_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_40_V_we0; + end else begin + layer7_out_40_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_41_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_41_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_41_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_address0; + end else begin + layer7_out_41_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_41_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_41_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_41_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_41_V_ce0; + end else begin + layer7_out_41_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_41_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_41_V_we0; + end else begin + layer7_out_41_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_42_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_42_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_42_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_address0; + end else begin + layer7_out_42_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_42_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_42_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_42_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_42_V_ce0; + end else begin + layer7_out_42_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_42_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_42_V_we0; + end else begin + layer7_out_42_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_43_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_43_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_43_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_address0; + end else begin + layer7_out_43_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_43_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_43_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_43_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_43_V_ce0; + end else begin + layer7_out_43_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_43_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_43_V_we0; + end else begin + layer7_out_43_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_44_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_44_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_44_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_address0; + end else begin + layer7_out_44_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_44_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_44_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_44_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_44_V_ce0; + end else begin + layer7_out_44_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_44_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_44_V_we0; + end else begin + layer7_out_44_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_45_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_45_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_45_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_address0; + end else begin + layer7_out_45_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_45_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_45_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_45_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_45_V_ce0; + end else begin + layer7_out_45_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_45_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_45_V_we0; + end else begin + layer7_out_45_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_46_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_46_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_46_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_address0; + end else begin + layer7_out_46_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_46_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_46_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_46_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_46_V_ce0; + end else begin + layer7_out_46_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_46_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_46_V_we0; + end else begin + layer7_out_46_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_47_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_47_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_47_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_address0; + end else begin + layer7_out_47_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_47_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_47_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_47_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_47_V_ce0; + end else begin + layer7_out_47_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_47_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_47_V_we0; + end else begin + layer7_out_47_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_48_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_48_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_48_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_address0; + end else begin + layer7_out_48_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_48_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_48_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_48_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_48_V_ce0; + end else begin + layer7_out_48_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_48_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_48_V_we0; + end else begin + layer7_out_48_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_49_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_49_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_49_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_address0; + end else begin + layer7_out_49_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_49_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_49_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_49_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_49_V_ce0; + end else begin + layer7_out_49_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_49_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_49_V_we0; + end else begin + layer7_out_49_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_4_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_4_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_4_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_address0; + end else begin + layer7_out_4_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_4_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_4_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_4_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_4_V_ce0; + end else begin + layer7_out_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_4_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_4_V_we0; + end else begin + layer7_out_4_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_50_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_50_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_50_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_address0; + end else begin + layer7_out_50_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_50_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_50_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_50_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_50_V_ce0; + end else begin + layer7_out_50_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_50_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_50_V_we0; + end else begin + layer7_out_50_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_51_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_51_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_51_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_address0; + end else begin + layer7_out_51_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_51_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_51_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_51_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_51_V_ce0; + end else begin + layer7_out_51_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_51_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_51_V_we0; + end else begin + layer7_out_51_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_52_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_52_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_52_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_address0; + end else begin + layer7_out_52_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_52_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_52_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_52_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_52_V_ce0; + end else begin + layer7_out_52_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_52_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_52_V_we0; + end else begin + layer7_out_52_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_53_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_53_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_53_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_address0; + end else begin + layer7_out_53_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_53_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_53_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_53_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_53_V_ce0; + end else begin + layer7_out_53_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_53_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_53_V_we0; + end else begin + layer7_out_53_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_54_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_54_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_54_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_address0; + end else begin + layer7_out_54_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_54_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_54_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_54_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_54_V_ce0; + end else begin + layer7_out_54_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_54_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_54_V_we0; + end else begin + layer7_out_54_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_55_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_55_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_55_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_address0; + end else begin + layer7_out_55_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_55_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_55_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_55_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_55_V_ce0; + end else begin + layer7_out_55_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_55_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_55_V_we0; + end else begin + layer7_out_55_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_56_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_56_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_56_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_address0; + end else begin + layer7_out_56_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_56_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_56_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_56_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_56_V_ce0; + end else begin + layer7_out_56_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_56_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_56_V_we0; + end else begin + layer7_out_56_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_57_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_57_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_57_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_address0; + end else begin + layer7_out_57_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_57_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_57_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_57_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_57_V_ce0; + end else begin + layer7_out_57_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_57_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_57_V_we0; + end else begin + layer7_out_57_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_58_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_58_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_58_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_address0; + end else begin + layer7_out_58_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_58_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_58_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_58_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_58_V_ce0; + end else begin + layer7_out_58_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_58_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_58_V_we0; + end else begin + layer7_out_58_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_59_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_59_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_59_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_address0; + end else begin + layer7_out_59_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_59_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_59_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_59_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_59_V_ce0; + end else begin + layer7_out_59_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_59_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_59_V_we0; + end else begin + layer7_out_59_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_5_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_5_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_5_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_address0; + end else begin + layer7_out_5_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_5_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_5_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_5_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_5_V_ce0; + end else begin + layer7_out_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_5_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_5_V_we0; + end else begin + layer7_out_5_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_60_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_60_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_60_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_address0; + end else begin + layer7_out_60_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_60_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_60_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_60_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_60_V_ce0; + end else begin + layer7_out_60_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_60_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_60_V_we0; + end else begin + layer7_out_60_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_61_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_61_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_61_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_address0; + end else begin + layer7_out_61_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_61_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_61_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_61_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_61_V_ce0; + end else begin + layer7_out_61_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_61_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_61_V_we0; + end else begin + layer7_out_61_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_62_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_62_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_62_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_address0; + end else begin + layer7_out_62_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_62_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_62_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_62_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_62_V_ce0; + end else begin + layer7_out_62_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_62_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_62_V_we0; + end else begin + layer7_out_62_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_63_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_63_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_63_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_address0; + end else begin + layer7_out_63_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_63_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_63_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_63_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_63_V_ce0; + end else begin + layer7_out_63_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_63_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_63_V_we0; + end else begin + layer7_out_63_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_64_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_64_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_64_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_address0; + end else begin + layer7_out_64_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_64_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_64_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_64_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_64_V_ce0; + end else begin + layer7_out_64_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_64_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_64_V_we0; + end else begin + layer7_out_64_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_65_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_65_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_65_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_address0; + end else begin + layer7_out_65_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_65_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_65_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_65_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_65_V_ce0; + end else begin + layer7_out_65_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_65_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_65_V_we0; + end else begin + layer7_out_65_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_66_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_66_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_66_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_address0; + end else begin + layer7_out_66_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_66_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_66_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_66_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_66_V_ce0; + end else begin + layer7_out_66_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_66_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_66_V_we0; + end else begin + layer7_out_66_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_67_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_67_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_67_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_address0; + end else begin + layer7_out_67_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_67_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_67_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_67_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_67_V_ce0; + end else begin + layer7_out_67_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_67_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_67_V_we0; + end else begin + layer7_out_67_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_68_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_68_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_68_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_address0; + end else begin + layer7_out_68_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_68_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_68_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_68_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_68_V_ce0; + end else begin + layer7_out_68_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_68_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_68_V_we0; + end else begin + layer7_out_68_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_69_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_69_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_69_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_address0; + end else begin + layer7_out_69_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_69_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_69_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_69_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_69_V_ce0; + end else begin + layer7_out_69_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_69_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_69_V_we0; + end else begin + layer7_out_69_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_6_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_6_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_6_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_address0; + end else begin + layer7_out_6_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_6_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_6_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_6_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_6_V_ce0; + end else begin + layer7_out_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_6_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_6_V_we0; + end else begin + layer7_out_6_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_70_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_70_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_70_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_address0; + end else begin + layer7_out_70_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_70_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_70_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_70_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_70_V_ce0; + end else begin + layer7_out_70_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_70_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_70_V_we0; + end else begin + layer7_out_70_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_71_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_71_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_71_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_address0; + end else begin + layer7_out_71_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_71_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_71_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_71_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_71_V_ce0; + end else begin + layer7_out_71_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_71_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_71_V_we0; + end else begin + layer7_out_71_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_72_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_72_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_72_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_address0; + end else begin + layer7_out_72_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_72_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_72_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_72_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_72_V_ce0; + end else begin + layer7_out_72_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_72_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_72_V_we0; + end else begin + layer7_out_72_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_73_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_73_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_73_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_address0; + end else begin + layer7_out_73_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_73_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_73_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_73_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_73_V_ce0; + end else begin + layer7_out_73_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_73_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_73_V_we0; + end else begin + layer7_out_73_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_74_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_74_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_74_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_address0; + end else begin + layer7_out_74_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_74_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_74_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_74_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_74_V_ce0; + end else begin + layer7_out_74_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_74_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_74_V_we0; + end else begin + layer7_out_74_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_75_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_75_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_75_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_address0; + end else begin + layer7_out_75_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_75_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_75_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_75_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_75_V_ce0; + end else begin + layer7_out_75_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_75_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_75_V_we0; + end else begin + layer7_out_75_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_76_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_76_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_76_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_address0; + end else begin + layer7_out_76_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_76_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_76_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_76_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_76_V_ce0; + end else begin + layer7_out_76_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_76_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_76_V_we0; + end else begin + layer7_out_76_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_77_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_77_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_77_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_address0; + end else begin + layer7_out_77_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_77_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_77_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_77_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_77_V_ce0; + end else begin + layer7_out_77_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_77_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_77_V_we0; + end else begin + layer7_out_77_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_78_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_78_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_78_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_address0; + end else begin + layer7_out_78_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_78_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_78_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_78_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_78_V_ce0; + end else begin + layer7_out_78_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_78_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_78_V_we0; + end else begin + layer7_out_78_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_79_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_79_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_79_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_address0; + end else begin + layer7_out_79_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_79_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_79_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_79_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_79_V_ce0; + end else begin + layer7_out_79_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_79_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_79_V_we0; + end else begin + layer7_out_79_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_7_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_7_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_7_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_address0; + end else begin + layer7_out_7_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_7_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_7_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_7_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_7_V_ce0; + end else begin + layer7_out_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_7_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_7_V_we0; + end else begin + layer7_out_7_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_80_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_80_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_80_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_address0; + end else begin + layer7_out_80_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_80_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_80_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_80_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_80_V_ce0; + end else begin + layer7_out_80_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_80_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_80_V_we0; + end else begin + layer7_out_80_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_81_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_81_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_81_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_address0; + end else begin + layer7_out_81_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_81_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_81_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_81_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_81_V_ce0; + end else begin + layer7_out_81_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_81_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_81_V_we0; + end else begin + layer7_out_81_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_82_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_82_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_82_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_address0; + end else begin + layer7_out_82_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_82_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_82_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_82_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_82_V_ce0; + end else begin + layer7_out_82_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_82_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_82_V_we0; + end else begin + layer7_out_82_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_83_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_83_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_83_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_address0; + end else begin + layer7_out_83_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_83_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_83_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_83_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_83_V_ce0; + end else begin + layer7_out_83_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_83_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_83_V_we0; + end else begin + layer7_out_83_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_84_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_84_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_84_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_address0; + end else begin + layer7_out_84_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_84_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_84_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_84_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_84_V_ce0; + end else begin + layer7_out_84_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_84_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_84_V_we0; + end else begin + layer7_out_84_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_85_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_85_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_85_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_address0; + end else begin + layer7_out_85_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_85_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_85_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_85_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_85_V_ce0; + end else begin + layer7_out_85_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_85_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_85_V_we0; + end else begin + layer7_out_85_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_86_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_86_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_86_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_address0; + end else begin + layer7_out_86_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_86_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_86_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_86_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_86_V_ce0; + end else begin + layer7_out_86_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_86_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_86_V_we0; + end else begin + layer7_out_86_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_87_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_87_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_87_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_address0; + end else begin + layer7_out_87_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_87_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_87_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_87_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_87_V_ce0; + end else begin + layer7_out_87_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_87_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_87_V_we0; + end else begin + layer7_out_87_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_88_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_88_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_88_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_address0; + end else begin + layer7_out_88_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_88_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_88_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_88_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_88_V_ce0; + end else begin + layer7_out_88_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_88_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_88_V_we0; + end else begin + layer7_out_88_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_89_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_89_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_89_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_address0; + end else begin + layer7_out_89_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_89_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_89_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_89_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_89_V_ce0; + end else begin + layer7_out_89_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_89_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_89_V_we0; + end else begin + layer7_out_89_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_8_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_8_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_8_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_address0; + end else begin + layer7_out_8_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_8_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_8_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_8_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_8_V_ce0; + end else begin + layer7_out_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_8_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_8_V_we0; + end else begin + layer7_out_8_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_90_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_90_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_90_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_address0; + end else begin + layer7_out_90_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_90_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_90_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_90_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_90_V_ce0; + end else begin + layer7_out_90_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_90_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_90_V_we0; + end else begin + layer7_out_90_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_91_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_91_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_91_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_address0; + end else begin + layer7_out_91_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_91_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_91_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_91_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_91_V_ce0; + end else begin + layer7_out_91_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_91_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_91_V_we0; + end else begin + layer7_out_91_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_92_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_92_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_92_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_address0; + end else begin + layer7_out_92_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_92_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_92_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_92_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_92_V_ce0; + end else begin + layer7_out_92_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_92_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_92_V_we0; + end else begin + layer7_out_92_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_93_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_93_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_93_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_address0; + end else begin + layer7_out_93_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_93_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_93_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_93_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_93_V_ce0; + end else begin + layer7_out_93_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_93_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_93_V_we0; + end else begin + layer7_out_93_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_94_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_94_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_94_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_address0; + end else begin + layer7_out_94_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_94_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_94_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_94_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_94_V_ce0; + end else begin + layer7_out_94_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_94_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_94_V_we0; + end else begin + layer7_out_94_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_95_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_95_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_95_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_address0; + end else begin + layer7_out_95_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_95_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_95_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_95_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_95_V_ce0; + end else begin + layer7_out_95_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_95_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_95_V_we0; + end else begin + layer7_out_95_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_96_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_96_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_96_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_address0; + end else begin + layer7_out_96_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_96_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_96_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_96_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_96_V_ce0; + end else begin + layer7_out_96_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_96_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_96_V_we0; + end else begin + layer7_out_96_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_97_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_97_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_97_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_address0; + end else begin + layer7_out_97_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_97_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_97_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_97_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_97_V_ce0; + end else begin + layer7_out_97_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_97_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_97_V_we0; + end else begin + layer7_out_97_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_98_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_98_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_98_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_address0; + end else begin + layer7_out_98_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_98_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_98_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_98_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_98_V_ce0; + end else begin + layer7_out_98_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_98_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_98_V_we0; + end else begin + layer7_out_98_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_99_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_99_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_99_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_address0; + end else begin + layer7_out_99_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_99_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_99_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_99_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_99_V_ce0; + end else begin + layer7_out_99_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_99_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_99_V_we0; + end else begin + layer7_out_99_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_9_V_address0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_9_V_address0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_9_V_address0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_address0; + end else begin + layer7_out_9_V_address0 = 'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_9_V_ce0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_9_V_ce0; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + layer7_out_9_V_ce0 = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_data_9_V_ce0; + end else begin + layer7_out_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + layer7_out_9_V_we0 = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_res_9_V_we0; + end else begin + layer7_out_9_V_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_done == 1'b1) & (ap_ST_fsm_state2 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state3; + end else begin + ap_NS_fsm = ap_ST_fsm_state2; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + if (((grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_done == 1'b1) & (ap_ST_fsm_state4 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state5; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + if (((ap_ST_fsm_state6 == ap_CS_fsm) & (grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_done == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_state6; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + if (((grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_done == 1'b1) & (ap_ST_fsm_state8 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state9; + end else begin + ap_NS_fsm = ap_ST_fsm_state8; + end + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + if (((1'b0 == ap_block_state10_on_subcall_done) & (ap_ST_fsm_state10 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state11; + end else begin + ap_NS_fsm = ap_ST_fsm_state10; + end + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +always @ (*) begin + ap_block_state10_on_subcall_done = ((ap_sync_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_ready & ap_sync_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_done) == 1'b0); +end + +assign ap_sync_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_done = (grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_done | ap_sync_reg_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_done); + +assign ap_sync_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_ready = (grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_ready | ap_sync_reg_grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_ready); + +assign const_size_in_1 = 16'd784; + +assign const_size_out_1 = 16'd10; + +assign conv2d_input_V_address0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_data_V_address0; + +assign conv2d_input_V_ce0 = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_data_V_ce0; + +assign grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_start = grp_conv_2d_latency_cl_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_2285_ap_start_reg; + +assign grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_start = grp_conv_2d_latency_cl_ap_fixed_ap_fixed_config2_0_0_0_0_0_fu_2547_ap_start_reg; + +assign grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_start = grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_fu_2811_ap_start_reg; + +assign grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_start = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_fu_3233_ap_start_reg; + +assign grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_start = grp_pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s_fu_2973_ap_start_reg; + +endmodule //myproject +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V_ram (addr0, ce0, d0, we0, q0, clk); + +parameter DWIDTH = 8; +parameter AWIDTH = 2; +parameter MEM_SIZE = 4; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V( + reset, + clk, + address0, + ce0, + we0, + d0, + q0); + +parameter DataWidth = 32'd8; +parameter AddressRange = 32'd4; +parameter AddressWidth = 32'd2; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; + + + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V_ram pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_idle, + ap_ready, + data_0_V_address0, + data_0_V_ce0, + data_0_V_q0, + data_1_V_address0, + data_1_V_ce0, + data_1_V_q0, + data_2_V_address0, + data_2_V_ce0, + data_2_V_q0, + data_3_V_address0, + data_3_V_ce0, + data_3_V_q0, + data_4_V_address0, + data_4_V_ce0, + data_4_V_q0, + data_5_V_address0, + data_5_V_ce0, + data_5_V_q0, + data_6_V_address0, + data_6_V_ce0, + data_6_V_q0, + data_7_V_address0, + data_7_V_ce0, + data_7_V_q0, + data_8_V_address0, + data_8_V_ce0, + data_8_V_q0, + data_9_V_address0, + data_9_V_ce0, + data_9_V_q0, + data_10_V_address0, + data_10_V_ce0, + data_10_V_q0, + data_11_V_address0, + data_11_V_ce0, + data_11_V_q0, + data_12_V_address0, + data_12_V_ce0, + data_12_V_q0, + data_13_V_address0, + data_13_V_ce0, + data_13_V_q0, + data_14_V_address0, + data_14_V_ce0, + data_14_V_q0, + data_15_V_address0, + data_15_V_ce0, + data_15_V_q0, + data_16_V_address0, + data_16_V_ce0, + data_16_V_q0, + data_17_V_address0, + data_17_V_ce0, + data_17_V_q0, + data_18_V_address0, + data_18_V_ce0, + data_18_V_q0, + data_19_V_address0, + data_19_V_ce0, + data_19_V_q0, + data_20_V_address0, + data_20_V_ce0, + data_20_V_q0, + data_21_V_address0, + data_21_V_ce0, + data_21_V_q0, + data_22_V_address0, + data_22_V_ce0, + data_22_V_q0, + data_23_V_address0, + data_23_V_ce0, + data_23_V_q0, + data_24_V_address0, + data_24_V_ce0, + data_24_V_q0, + data_25_V_address0, + data_25_V_ce0, + data_25_V_q0, + data_26_V_address0, + data_26_V_ce0, + data_26_V_q0, + data_27_V_address0, + data_27_V_ce0, + data_27_V_q0, + data_28_V_address0, + data_28_V_ce0, + data_28_V_q0, + data_29_V_address0, + data_29_V_ce0, + data_29_V_q0, + data_30_V_address0, + data_30_V_ce0, + data_30_V_q0, + data_31_V_address0, + data_31_V_ce0, + data_31_V_q0, + data_32_V_address0, + data_32_V_ce0, + data_32_V_q0, + data_33_V_address0, + data_33_V_ce0, + data_33_V_q0, + data_34_V_address0, + data_34_V_ce0, + data_34_V_q0, + data_35_V_address0, + data_35_V_ce0, + data_35_V_q0, + data_36_V_address0, + data_36_V_ce0, + data_36_V_q0, + data_37_V_address0, + data_37_V_ce0, + data_37_V_q0, + data_38_V_address0, + data_38_V_ce0, + data_38_V_q0, + data_39_V_address0, + data_39_V_ce0, + data_39_V_q0, + data_40_V_address0, + data_40_V_ce0, + data_40_V_q0, + data_41_V_address0, + data_41_V_ce0, + data_41_V_q0, + data_42_V_address0, + data_42_V_ce0, + data_42_V_q0, + data_43_V_address0, + data_43_V_ce0, + data_43_V_q0, + data_44_V_address0, + data_44_V_ce0, + data_44_V_q0, + data_45_V_address0, + data_45_V_ce0, + data_45_V_q0, + data_46_V_address0, + data_46_V_ce0, + data_46_V_q0, + data_47_V_address0, + data_47_V_ce0, + data_47_V_q0, + data_48_V_address0, + data_48_V_ce0, + data_48_V_q0, + data_49_V_address0, + data_49_V_ce0, + data_49_V_q0, + data_50_V_address0, + data_50_V_ce0, + data_50_V_q0, + data_51_V_address0, + data_51_V_ce0, + data_51_V_q0, + data_52_V_address0, + data_52_V_ce0, + data_52_V_q0, + data_53_V_address0, + data_53_V_ce0, + data_53_V_q0, + data_54_V_address0, + data_54_V_ce0, + data_54_V_q0, + data_55_V_address0, + data_55_V_ce0, + data_55_V_q0, + data_56_V_address0, + data_56_V_ce0, + data_56_V_q0, + data_57_V_address0, + data_57_V_ce0, + data_57_V_q0, + data_58_V_address0, + data_58_V_ce0, + data_58_V_q0, + data_59_V_address0, + data_59_V_ce0, + data_59_V_q0, + data_60_V_address0, + data_60_V_ce0, + data_60_V_q0, + data_61_V_address0, + data_61_V_ce0, + data_61_V_q0, + data_62_V_address0, + data_62_V_ce0, + data_62_V_q0, + data_63_V_address0, + data_63_V_ce0, + data_63_V_q0, + data_64_V_address0, + data_64_V_ce0, + data_64_V_q0, + data_65_V_address0, + data_65_V_ce0, + data_65_V_q0, + data_66_V_address0, + data_66_V_ce0, + data_66_V_q0, + data_67_V_address0, + data_67_V_ce0, + data_67_V_q0, + data_68_V_address0, + data_68_V_ce0, + data_68_V_q0, + data_69_V_address0, + data_69_V_ce0, + data_69_V_q0, + data_70_V_address0, + data_70_V_ce0, + data_70_V_q0, + data_71_V_address0, + data_71_V_ce0, + data_71_V_q0, + data_72_V_address0, + data_72_V_ce0, + data_72_V_q0, + data_73_V_address0, + data_73_V_ce0, + data_73_V_q0, + data_74_V_address0, + data_74_V_ce0, + data_74_V_q0, + data_75_V_address0, + data_75_V_ce0, + data_75_V_q0, + data_76_V_address0, + data_76_V_ce0, + data_76_V_q0, + data_77_V_address0, + data_77_V_ce0, + data_77_V_q0, + data_78_V_address0, + data_78_V_ce0, + data_78_V_q0, + data_79_V_address0, + data_79_V_ce0, + data_79_V_q0, + data_80_V_address0, + data_80_V_ce0, + data_80_V_q0, + data_81_V_address0, + data_81_V_ce0, + data_81_V_q0, + data_82_V_address0, + data_82_V_ce0, + data_82_V_q0, + data_83_V_address0, + data_83_V_ce0, + data_83_V_q0, + data_84_V_address0, + data_84_V_ce0, + data_84_V_q0, + data_85_V_address0, + data_85_V_ce0, + data_85_V_q0, + data_86_V_address0, + data_86_V_ce0, + data_86_V_q0, + data_87_V_address0, + data_87_V_ce0, + data_87_V_q0, + data_88_V_address0, + data_88_V_ce0, + data_88_V_q0, + data_89_V_address0, + data_89_V_ce0, + data_89_V_q0, + data_90_V_address0, + data_90_V_ce0, + data_90_V_q0, + data_91_V_address0, + data_91_V_ce0, + data_91_V_q0, + data_92_V_address0, + data_92_V_ce0, + data_92_V_q0, + data_93_V_address0, + data_93_V_ce0, + data_93_V_q0, + data_94_V_address0, + data_94_V_ce0, + data_94_V_q0, + data_95_V_address0, + data_95_V_ce0, + data_95_V_q0, + data_96_V_address0, + data_96_V_ce0, + data_96_V_q0, + data_97_V_address0, + data_97_V_ce0, + data_97_V_q0, + data_98_V_address0, + data_98_V_ce0, + data_98_V_q0, + data_99_V_address0, + data_99_V_ce0, + data_99_V_q0, + data_100_V_address0, + data_100_V_ce0, + data_100_V_q0, + data_101_V_address0, + data_101_V_ce0, + data_101_V_q0, + data_102_V_address0, + data_102_V_ce0, + data_102_V_q0, + data_103_V_address0, + data_103_V_ce0, + data_103_V_q0, + data_104_V_address0, + data_104_V_ce0, + data_104_V_q0, + data_105_V_address0, + data_105_V_ce0, + data_105_V_q0, + data_106_V_address0, + data_106_V_ce0, + data_106_V_q0, + data_107_V_address0, + data_107_V_ce0, + data_107_V_q0, + data_108_V_address0, + data_108_V_ce0, + data_108_V_q0, + data_109_V_address0, + data_109_V_ce0, + data_109_V_q0, + data_110_V_address0, + data_110_V_ce0, + data_110_V_q0, + data_111_V_address0, + data_111_V_ce0, + data_111_V_q0, + data_112_V_address0, + data_112_V_ce0, + data_112_V_q0, + data_113_V_address0, + data_113_V_ce0, + data_113_V_q0, + data_114_V_address0, + data_114_V_ce0, + data_114_V_q0, + data_115_V_address0, + data_115_V_ce0, + data_115_V_q0, + data_116_V_address0, + data_116_V_ce0, + data_116_V_q0, + data_117_V_address0, + data_117_V_ce0, + data_117_V_q0, + data_118_V_address0, + data_118_V_ce0, + data_118_V_q0, + data_119_V_address0, + data_119_V_ce0, + data_119_V_q0, + data_120_V_address0, + data_120_V_ce0, + data_120_V_q0, + data_121_V_address0, + data_121_V_ce0, + data_121_V_q0, + data_122_V_address0, + data_122_V_ce0, + data_122_V_q0, + data_123_V_address0, + data_123_V_ce0, + data_123_V_q0, + data_124_V_address0, + data_124_V_ce0, + data_124_V_q0, + data_125_V_address0, + data_125_V_ce0, + data_125_V_q0, + data_126_V_address0, + data_126_V_ce0, + data_126_V_q0, + data_127_V_address0, + data_127_V_ce0, + data_127_V_q0, + res_0_V_address0, + res_0_V_ce0, + res_0_V_we0, + res_0_V_d0, + res_1_V_address0, + res_1_V_ce0, + res_1_V_we0, + res_1_V_d0, + res_2_V_address0, + res_2_V_ce0, + res_2_V_we0, + res_2_V_d0, + res_3_V_address0, + res_3_V_ce0, + res_3_V_we0, + res_3_V_d0, + res_4_V_address0, + res_4_V_ce0, + res_4_V_we0, + res_4_V_d0, + res_5_V_address0, + res_5_V_ce0, + res_5_V_we0, + res_5_V_d0, + res_6_V_address0, + res_6_V_ce0, + res_6_V_we0, + res_6_V_d0, + res_7_V_address0, + res_7_V_ce0, + res_7_V_we0, + res_7_V_d0, + res_8_V_address0, + res_8_V_ce0, + res_8_V_we0, + res_8_V_d0, + res_9_V_address0, + res_9_V_ce0, + res_9_V_we0, + res_9_V_d0, + res_10_V_address0, + res_10_V_ce0, + res_10_V_we0, + res_10_V_d0, + res_11_V_address0, + res_11_V_ce0, + res_11_V_we0, + res_11_V_d0, + res_12_V_address0, + res_12_V_ce0, + res_12_V_we0, + res_12_V_d0, + res_13_V_address0, + res_13_V_ce0, + res_13_V_we0, + res_13_V_d0, + res_14_V_address0, + res_14_V_ce0, + res_14_V_we0, + res_14_V_d0, + res_15_V_address0, + res_15_V_ce0, + res_15_V_we0, + res_15_V_d0, + res_16_V_address0, + res_16_V_ce0, + res_16_V_we0, + res_16_V_d0, + res_17_V_address0, + res_17_V_ce0, + res_17_V_we0, + res_17_V_d0, + res_18_V_address0, + res_18_V_ce0, + res_18_V_we0, + res_18_V_d0, + res_19_V_address0, + res_19_V_ce0, + res_19_V_we0, + res_19_V_d0, + res_20_V_address0, + res_20_V_ce0, + res_20_V_we0, + res_20_V_d0, + res_21_V_address0, + res_21_V_ce0, + res_21_V_we0, + res_21_V_d0, + res_22_V_address0, + res_22_V_ce0, + res_22_V_we0, + res_22_V_d0, + res_23_V_address0, + res_23_V_ce0, + res_23_V_we0, + res_23_V_d0, + res_24_V_address0, + res_24_V_ce0, + res_24_V_we0, + res_24_V_d0, + res_25_V_address0, + res_25_V_ce0, + res_25_V_we0, + res_25_V_d0, + res_26_V_address0, + res_26_V_ce0, + res_26_V_we0, + res_26_V_d0, + res_27_V_address0, + res_27_V_ce0, + res_27_V_we0, + res_27_V_d0, + res_28_V_address0, + res_28_V_ce0, + res_28_V_we0, + res_28_V_d0, + res_29_V_address0, + res_29_V_ce0, + res_29_V_we0, + res_29_V_d0, + res_30_V_address0, + res_30_V_ce0, + res_30_V_we0, + res_30_V_d0, + res_31_V_address0, + res_31_V_ce0, + res_31_V_we0, + res_31_V_d0, + res_32_V_address0, + res_32_V_ce0, + res_32_V_we0, + res_32_V_d0, + res_33_V_address0, + res_33_V_ce0, + res_33_V_we0, + res_33_V_d0, + res_34_V_address0, + res_34_V_ce0, + res_34_V_we0, + res_34_V_d0, + res_35_V_address0, + res_35_V_ce0, + res_35_V_we0, + res_35_V_d0, + res_36_V_address0, + res_36_V_ce0, + res_36_V_we0, + res_36_V_d0, + res_37_V_address0, + res_37_V_ce0, + res_37_V_we0, + res_37_V_d0, + res_38_V_address0, + res_38_V_ce0, + res_38_V_we0, + res_38_V_d0, + res_39_V_address0, + res_39_V_ce0, + res_39_V_we0, + res_39_V_d0, + res_40_V_address0, + res_40_V_ce0, + res_40_V_we0, + res_40_V_d0, + res_41_V_address0, + res_41_V_ce0, + res_41_V_we0, + res_41_V_d0, + res_42_V_address0, + res_42_V_ce0, + res_42_V_we0, + res_42_V_d0, + res_43_V_address0, + res_43_V_ce0, + res_43_V_we0, + res_43_V_d0, + res_44_V_address0, + res_44_V_ce0, + res_44_V_we0, + res_44_V_d0, + res_45_V_address0, + res_45_V_ce0, + res_45_V_we0, + res_45_V_d0, + res_46_V_address0, + res_46_V_ce0, + res_46_V_we0, + res_46_V_d0, + res_47_V_address0, + res_47_V_ce0, + res_47_V_we0, + res_47_V_d0, + res_48_V_address0, + res_48_V_ce0, + res_48_V_we0, + res_48_V_d0, + res_49_V_address0, + res_49_V_ce0, + res_49_V_we0, + res_49_V_d0, + res_50_V_address0, + res_50_V_ce0, + res_50_V_we0, + res_50_V_d0, + res_51_V_address0, + res_51_V_ce0, + res_51_V_we0, + res_51_V_d0, + res_52_V_address0, + res_52_V_ce0, + res_52_V_we0, + res_52_V_d0, + res_53_V_address0, + res_53_V_ce0, + res_53_V_we0, + res_53_V_d0, + res_54_V_address0, + res_54_V_ce0, + res_54_V_we0, + res_54_V_d0, + res_55_V_address0, + res_55_V_ce0, + res_55_V_we0, + res_55_V_d0, + res_56_V_address0, + res_56_V_ce0, + res_56_V_we0, + res_56_V_d0, + res_57_V_address0, + res_57_V_ce0, + res_57_V_we0, + res_57_V_d0, + res_58_V_address0, + res_58_V_ce0, + res_58_V_we0, + res_58_V_d0, + res_59_V_address0, + res_59_V_ce0, + res_59_V_we0, + res_59_V_d0, + res_60_V_address0, + res_60_V_ce0, + res_60_V_we0, + res_60_V_d0, + res_61_V_address0, + res_61_V_ce0, + res_61_V_we0, + res_61_V_d0, + res_62_V_address0, + res_62_V_ce0, + res_62_V_we0, + res_62_V_d0, + res_63_V_address0, + res_63_V_ce0, + res_63_V_we0, + res_63_V_d0, + res_64_V_address0, + res_64_V_ce0, + res_64_V_we0, + res_64_V_d0, + res_65_V_address0, + res_65_V_ce0, + res_65_V_we0, + res_65_V_d0, + res_66_V_address0, + res_66_V_ce0, + res_66_V_we0, + res_66_V_d0, + res_67_V_address0, + res_67_V_ce0, + res_67_V_we0, + res_67_V_d0, + res_68_V_address0, + res_68_V_ce0, + res_68_V_we0, + res_68_V_d0, + res_69_V_address0, + res_69_V_ce0, + res_69_V_we0, + res_69_V_d0, + res_70_V_address0, + res_70_V_ce0, + res_70_V_we0, + res_70_V_d0, + res_71_V_address0, + res_71_V_ce0, + res_71_V_we0, + res_71_V_d0, + res_72_V_address0, + res_72_V_ce0, + res_72_V_we0, + res_72_V_d0, + res_73_V_address0, + res_73_V_ce0, + res_73_V_we0, + res_73_V_d0, + res_74_V_address0, + res_74_V_ce0, + res_74_V_we0, + res_74_V_d0, + res_75_V_address0, + res_75_V_ce0, + res_75_V_we0, + res_75_V_d0, + res_76_V_address0, + res_76_V_ce0, + res_76_V_we0, + res_76_V_d0, + res_77_V_address0, + res_77_V_ce0, + res_77_V_we0, + res_77_V_d0, + res_78_V_address0, + res_78_V_ce0, + res_78_V_we0, + res_78_V_d0, + res_79_V_address0, + res_79_V_ce0, + res_79_V_we0, + res_79_V_d0, + res_80_V_address0, + res_80_V_ce0, + res_80_V_we0, + res_80_V_d0, + res_81_V_address0, + res_81_V_ce0, + res_81_V_we0, + res_81_V_d0, + res_82_V_address0, + res_82_V_ce0, + res_82_V_we0, + res_82_V_d0, + res_83_V_address0, + res_83_V_ce0, + res_83_V_we0, + res_83_V_d0, + res_84_V_address0, + res_84_V_ce0, + res_84_V_we0, + res_84_V_d0, + res_85_V_address0, + res_85_V_ce0, + res_85_V_we0, + res_85_V_d0, + res_86_V_address0, + res_86_V_ce0, + res_86_V_we0, + res_86_V_d0, + res_87_V_address0, + res_87_V_ce0, + res_87_V_we0, + res_87_V_d0, + res_88_V_address0, + res_88_V_ce0, + res_88_V_we0, + res_88_V_d0, + res_89_V_address0, + res_89_V_ce0, + res_89_V_we0, + res_89_V_d0, + res_90_V_address0, + res_90_V_ce0, + res_90_V_we0, + res_90_V_d0, + res_91_V_address0, + res_91_V_ce0, + res_91_V_we0, + res_91_V_d0, + res_92_V_address0, + res_92_V_ce0, + res_92_V_we0, + res_92_V_d0, + res_93_V_address0, + res_93_V_ce0, + res_93_V_we0, + res_93_V_d0, + res_94_V_address0, + res_94_V_ce0, + res_94_V_we0, + res_94_V_d0, + res_95_V_address0, + res_95_V_ce0, + res_95_V_we0, + res_95_V_d0, + res_96_V_address0, + res_96_V_ce0, + res_96_V_we0, + res_96_V_d0, + res_97_V_address0, + res_97_V_ce0, + res_97_V_we0, + res_97_V_d0, + res_98_V_address0, + res_98_V_ce0, + res_98_V_we0, + res_98_V_d0, + res_99_V_address0, + res_99_V_ce0, + res_99_V_we0, + res_99_V_d0, + res_100_V_address0, + res_100_V_ce0, + res_100_V_we0, + res_100_V_d0, + res_101_V_address0, + res_101_V_ce0, + res_101_V_we0, + res_101_V_d0, + res_102_V_address0, + res_102_V_ce0, + res_102_V_we0, + res_102_V_d0, + res_103_V_address0, + res_103_V_ce0, + res_103_V_we0, + res_103_V_d0, + res_104_V_address0, + res_104_V_ce0, + res_104_V_we0, + res_104_V_d0, + res_105_V_address0, + res_105_V_ce0, + res_105_V_we0, + res_105_V_d0, + res_106_V_address0, + res_106_V_ce0, + res_106_V_we0, + res_106_V_d0, + res_107_V_address0, + res_107_V_ce0, + res_107_V_we0, + res_107_V_d0, + res_108_V_address0, + res_108_V_ce0, + res_108_V_we0, + res_108_V_d0, + res_109_V_address0, + res_109_V_ce0, + res_109_V_we0, + res_109_V_d0, + res_110_V_address0, + res_110_V_ce0, + res_110_V_we0, + res_110_V_d0, + res_111_V_address0, + res_111_V_ce0, + res_111_V_we0, + res_111_V_d0, + res_112_V_address0, + res_112_V_ce0, + res_112_V_we0, + res_112_V_d0, + res_113_V_address0, + res_113_V_ce0, + res_113_V_we0, + res_113_V_d0, + res_114_V_address0, + res_114_V_ce0, + res_114_V_we0, + res_114_V_d0, + res_115_V_address0, + res_115_V_ce0, + res_115_V_we0, + res_115_V_d0, + res_116_V_address0, + res_116_V_ce0, + res_116_V_we0, + res_116_V_d0, + res_117_V_address0, + res_117_V_ce0, + res_117_V_we0, + res_117_V_d0, + res_118_V_address0, + res_118_V_ce0, + res_118_V_we0, + res_118_V_d0, + res_119_V_address0, + res_119_V_ce0, + res_119_V_we0, + res_119_V_d0, + res_120_V_address0, + res_120_V_ce0, + res_120_V_we0, + res_120_V_d0, + res_121_V_address0, + res_121_V_ce0, + res_121_V_we0, + res_121_V_d0, + res_122_V_address0, + res_122_V_ce0, + res_122_V_we0, + res_122_V_d0, + res_123_V_address0, + res_123_V_ce0, + res_123_V_we0, + res_123_V_d0, + res_124_V_address0, + res_124_V_ce0, + res_124_V_we0, + res_124_V_d0, + res_125_V_address0, + res_125_V_ce0, + res_125_V_we0, + res_125_V_d0, + res_126_V_address0, + res_126_V_ce0, + res_126_V_we0, + res_126_V_d0, + res_127_V_address0, + res_127_V_ce0, + res_127_V_we0, + res_127_V_d0 +); + +parameter ap_ST_fsm_state1 = 4'd0; +parameter ap_ST_fsm_state2 = 4'd1; +parameter ap_ST_fsm_state3 = 4'd2; +parameter ap_ST_fsm_state4 = 4'd3; +parameter ap_ST_fsm_state5 = 4'd4; +parameter ap_ST_fsm_state6 = 4'd5; +parameter ap_ST_fsm_state7 = 4'd6; +parameter ap_ST_fsm_state8 = 4'd7; +parameter ap_ST_fsm_state9 = 4'd8; +parameter ap_ST_fsm_state10 = 4'd9; +parameter ap_ST_fsm_state11 = 4'd10; +parameter ap_ST_fsm_state12 = 4'd11; +parameter ap_ST_fsm_state13 = 4'd12; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +output [4:0] data_0_V_address0; +output data_0_V_ce0; +input [7:0] data_0_V_q0; +output [4:0] data_1_V_address0; +output data_1_V_ce0; +input [7:0] data_1_V_q0; +output [4:0] data_2_V_address0; +output data_2_V_ce0; +input [7:0] data_2_V_q0; +output [4:0] data_3_V_address0; +output data_3_V_ce0; +input [7:0] data_3_V_q0; +output [4:0] data_4_V_address0; +output data_4_V_ce0; +input [7:0] data_4_V_q0; +output [4:0] data_5_V_address0; +output data_5_V_ce0; +input [7:0] data_5_V_q0; +output [4:0] data_6_V_address0; +output data_6_V_ce0; +input [7:0] data_6_V_q0; +output [4:0] data_7_V_address0; +output data_7_V_ce0; +input [7:0] data_7_V_q0; +output [4:0] data_8_V_address0; +output data_8_V_ce0; +input [7:0] data_8_V_q0; +output [4:0] data_9_V_address0; +output data_9_V_ce0; +input [7:0] data_9_V_q0; +output [4:0] data_10_V_address0; +output data_10_V_ce0; +input [7:0] data_10_V_q0; +output [4:0] data_11_V_address0; +output data_11_V_ce0; +input [7:0] data_11_V_q0; +output [4:0] data_12_V_address0; +output data_12_V_ce0; +input [7:0] data_12_V_q0; +output [4:0] data_13_V_address0; +output data_13_V_ce0; +input [7:0] data_13_V_q0; +output [4:0] data_14_V_address0; +output data_14_V_ce0; +input [7:0] data_14_V_q0; +output [4:0] data_15_V_address0; +output data_15_V_ce0; +input [7:0] data_15_V_q0; +output [4:0] data_16_V_address0; +output data_16_V_ce0; +input [7:0] data_16_V_q0; +output [4:0] data_17_V_address0; +output data_17_V_ce0; +input [7:0] data_17_V_q0; +output [4:0] data_18_V_address0; +output data_18_V_ce0; +input [7:0] data_18_V_q0; +output [4:0] data_19_V_address0; +output data_19_V_ce0; +input [7:0] data_19_V_q0; +output [4:0] data_20_V_address0; +output data_20_V_ce0; +input [7:0] data_20_V_q0; +output [4:0] data_21_V_address0; +output data_21_V_ce0; +input [7:0] data_21_V_q0; +output [4:0] data_22_V_address0; +output data_22_V_ce0; +input [7:0] data_22_V_q0; +output [4:0] data_23_V_address0; +output data_23_V_ce0; +input [7:0] data_23_V_q0; +output [4:0] data_24_V_address0; +output data_24_V_ce0; +input [7:0] data_24_V_q0; +output [4:0] data_25_V_address0; +output data_25_V_ce0; +input [7:0] data_25_V_q0; +output [4:0] data_26_V_address0; +output data_26_V_ce0; +input [7:0] data_26_V_q0; +output [4:0] data_27_V_address0; +output data_27_V_ce0; +input [7:0] data_27_V_q0; +output [4:0] data_28_V_address0; +output data_28_V_ce0; +input [7:0] data_28_V_q0; +output [4:0] data_29_V_address0; +output data_29_V_ce0; +input [7:0] data_29_V_q0; +output [4:0] data_30_V_address0; +output data_30_V_ce0; +input [7:0] data_30_V_q0; +output [4:0] data_31_V_address0; +output data_31_V_ce0; +input [7:0] data_31_V_q0; +output [4:0] data_32_V_address0; +output data_32_V_ce0; +input [7:0] data_32_V_q0; +output [4:0] data_33_V_address0; +output data_33_V_ce0; +input [7:0] data_33_V_q0; +output [4:0] data_34_V_address0; +output data_34_V_ce0; +input [7:0] data_34_V_q0; +output [4:0] data_35_V_address0; +output data_35_V_ce0; +input [7:0] data_35_V_q0; +output [4:0] data_36_V_address0; +output data_36_V_ce0; +input [7:0] data_36_V_q0; +output [4:0] data_37_V_address0; +output data_37_V_ce0; +input [7:0] data_37_V_q0; +output [4:0] data_38_V_address0; +output data_38_V_ce0; +input [7:0] data_38_V_q0; +output [4:0] data_39_V_address0; +output data_39_V_ce0; +input [7:0] data_39_V_q0; +output [4:0] data_40_V_address0; +output data_40_V_ce0; +input [7:0] data_40_V_q0; +output [4:0] data_41_V_address0; +output data_41_V_ce0; +input [7:0] data_41_V_q0; +output [4:0] data_42_V_address0; +output data_42_V_ce0; +input [7:0] data_42_V_q0; +output [4:0] data_43_V_address0; +output data_43_V_ce0; +input [7:0] data_43_V_q0; +output [4:0] data_44_V_address0; +output data_44_V_ce0; +input [7:0] data_44_V_q0; +output [4:0] data_45_V_address0; +output data_45_V_ce0; +input [7:0] data_45_V_q0; +output [4:0] data_46_V_address0; +output data_46_V_ce0; +input [7:0] data_46_V_q0; +output [4:0] data_47_V_address0; +output data_47_V_ce0; +input [7:0] data_47_V_q0; +output [4:0] data_48_V_address0; +output data_48_V_ce0; +input [7:0] data_48_V_q0; +output [4:0] data_49_V_address0; +output data_49_V_ce0; +input [7:0] data_49_V_q0; +output [4:0] data_50_V_address0; +output data_50_V_ce0; +input [7:0] data_50_V_q0; +output [4:0] data_51_V_address0; +output data_51_V_ce0; +input [7:0] data_51_V_q0; +output [4:0] data_52_V_address0; +output data_52_V_ce0; +input [7:0] data_52_V_q0; +output [4:0] data_53_V_address0; +output data_53_V_ce0; +input [7:0] data_53_V_q0; +output [4:0] data_54_V_address0; +output data_54_V_ce0; +input [7:0] data_54_V_q0; +output [4:0] data_55_V_address0; +output data_55_V_ce0; +input [7:0] data_55_V_q0; +output [4:0] data_56_V_address0; +output data_56_V_ce0; +input [7:0] data_56_V_q0; +output [4:0] data_57_V_address0; +output data_57_V_ce0; +input [7:0] data_57_V_q0; +output [4:0] data_58_V_address0; +output data_58_V_ce0; +input [7:0] data_58_V_q0; +output [4:0] data_59_V_address0; +output data_59_V_ce0; +input [7:0] data_59_V_q0; +output [4:0] data_60_V_address0; +output data_60_V_ce0; +input [7:0] data_60_V_q0; +output [4:0] data_61_V_address0; +output data_61_V_ce0; +input [7:0] data_61_V_q0; +output [4:0] data_62_V_address0; +output data_62_V_ce0; +input [7:0] data_62_V_q0; +output [4:0] data_63_V_address0; +output data_63_V_ce0; +input [7:0] data_63_V_q0; +output [4:0] data_64_V_address0; +output data_64_V_ce0; +input [7:0] data_64_V_q0; +output [4:0] data_65_V_address0; +output data_65_V_ce0; +input [7:0] data_65_V_q0; +output [4:0] data_66_V_address0; +output data_66_V_ce0; +input [7:0] data_66_V_q0; +output [4:0] data_67_V_address0; +output data_67_V_ce0; +input [7:0] data_67_V_q0; +output [4:0] data_68_V_address0; +output data_68_V_ce0; +input [7:0] data_68_V_q0; +output [4:0] data_69_V_address0; +output data_69_V_ce0; +input [7:0] data_69_V_q0; +output [4:0] data_70_V_address0; +output data_70_V_ce0; +input [7:0] data_70_V_q0; +output [4:0] data_71_V_address0; +output data_71_V_ce0; +input [7:0] data_71_V_q0; +output [4:0] data_72_V_address0; +output data_72_V_ce0; +input [7:0] data_72_V_q0; +output [4:0] data_73_V_address0; +output data_73_V_ce0; +input [7:0] data_73_V_q0; +output [4:0] data_74_V_address0; +output data_74_V_ce0; +input [7:0] data_74_V_q0; +output [4:0] data_75_V_address0; +output data_75_V_ce0; +input [7:0] data_75_V_q0; +output [4:0] data_76_V_address0; +output data_76_V_ce0; +input [7:0] data_76_V_q0; +output [4:0] data_77_V_address0; +output data_77_V_ce0; +input [7:0] data_77_V_q0; +output [4:0] data_78_V_address0; +output data_78_V_ce0; +input [7:0] data_78_V_q0; +output [4:0] data_79_V_address0; +output data_79_V_ce0; +input [7:0] data_79_V_q0; +output [4:0] data_80_V_address0; +output data_80_V_ce0; +input [7:0] data_80_V_q0; +output [4:0] data_81_V_address0; +output data_81_V_ce0; +input [7:0] data_81_V_q0; +output [4:0] data_82_V_address0; +output data_82_V_ce0; +input [7:0] data_82_V_q0; +output [4:0] data_83_V_address0; +output data_83_V_ce0; +input [7:0] data_83_V_q0; +output [4:0] data_84_V_address0; +output data_84_V_ce0; +input [7:0] data_84_V_q0; +output [4:0] data_85_V_address0; +output data_85_V_ce0; +input [7:0] data_85_V_q0; +output [4:0] data_86_V_address0; +output data_86_V_ce0; +input [7:0] data_86_V_q0; +output [4:0] data_87_V_address0; +output data_87_V_ce0; +input [7:0] data_87_V_q0; +output [4:0] data_88_V_address0; +output data_88_V_ce0; +input [7:0] data_88_V_q0; +output [4:0] data_89_V_address0; +output data_89_V_ce0; +input [7:0] data_89_V_q0; +output [4:0] data_90_V_address0; +output data_90_V_ce0; +input [7:0] data_90_V_q0; +output [4:0] data_91_V_address0; +output data_91_V_ce0; +input [7:0] data_91_V_q0; +output [4:0] data_92_V_address0; +output data_92_V_ce0; +input [7:0] data_92_V_q0; +output [4:0] data_93_V_address0; +output data_93_V_ce0; +input [7:0] data_93_V_q0; +output [4:0] data_94_V_address0; +output data_94_V_ce0; +input [7:0] data_94_V_q0; +output [4:0] data_95_V_address0; +output data_95_V_ce0; +input [7:0] data_95_V_q0; +output [4:0] data_96_V_address0; +output data_96_V_ce0; +input [7:0] data_96_V_q0; +output [4:0] data_97_V_address0; +output data_97_V_ce0; +input [7:0] data_97_V_q0; +output [4:0] data_98_V_address0; +output data_98_V_ce0; +input [7:0] data_98_V_q0; +output [4:0] data_99_V_address0; +output data_99_V_ce0; +input [7:0] data_99_V_q0; +output [4:0] data_100_V_address0; +output data_100_V_ce0; +input [7:0] data_100_V_q0; +output [4:0] data_101_V_address0; +output data_101_V_ce0; +input [7:0] data_101_V_q0; +output [4:0] data_102_V_address0; +output data_102_V_ce0; +input [7:0] data_102_V_q0; +output [4:0] data_103_V_address0; +output data_103_V_ce0; +input [7:0] data_103_V_q0; +output [4:0] data_104_V_address0; +output data_104_V_ce0; +input [7:0] data_104_V_q0; +output [4:0] data_105_V_address0; +output data_105_V_ce0; +input [7:0] data_105_V_q0; +output [4:0] data_106_V_address0; +output data_106_V_ce0; +input [7:0] data_106_V_q0; +output [4:0] data_107_V_address0; +output data_107_V_ce0; +input [7:0] data_107_V_q0; +output [4:0] data_108_V_address0; +output data_108_V_ce0; +input [7:0] data_108_V_q0; +output [4:0] data_109_V_address0; +output data_109_V_ce0; +input [7:0] data_109_V_q0; +output [4:0] data_110_V_address0; +output data_110_V_ce0; +input [7:0] data_110_V_q0; +output [4:0] data_111_V_address0; +output data_111_V_ce0; +input [7:0] data_111_V_q0; +output [4:0] data_112_V_address0; +output data_112_V_ce0; +input [7:0] data_112_V_q0; +output [4:0] data_113_V_address0; +output data_113_V_ce0; +input [7:0] data_113_V_q0; +output [4:0] data_114_V_address0; +output data_114_V_ce0; +input [7:0] data_114_V_q0; +output [4:0] data_115_V_address0; +output data_115_V_ce0; +input [7:0] data_115_V_q0; +output [4:0] data_116_V_address0; +output data_116_V_ce0; +input [7:0] data_116_V_q0; +output [4:0] data_117_V_address0; +output data_117_V_ce0; +input [7:0] data_117_V_q0; +output [4:0] data_118_V_address0; +output data_118_V_ce0; +input [7:0] data_118_V_q0; +output [4:0] data_119_V_address0; +output data_119_V_ce0; +input [7:0] data_119_V_q0; +output [4:0] data_120_V_address0; +output data_120_V_ce0; +input [7:0] data_120_V_q0; +output [4:0] data_121_V_address0; +output data_121_V_ce0; +input [7:0] data_121_V_q0; +output [4:0] data_122_V_address0; +output data_122_V_ce0; +input [7:0] data_122_V_q0; +output [4:0] data_123_V_address0; +output data_123_V_ce0; +input [7:0] data_123_V_q0; +output [4:0] data_124_V_address0; +output data_124_V_ce0; +input [7:0] data_124_V_q0; +output [4:0] data_125_V_address0; +output data_125_V_ce0; +input [7:0] data_125_V_q0; +output [4:0] data_126_V_address0; +output data_126_V_ce0; +input [7:0] data_126_V_q0; +output [4:0] data_127_V_address0; +output data_127_V_ce0; +input [7:0] data_127_V_q0; +output [2:0] res_0_V_address0; +output res_0_V_ce0; +output res_0_V_we0; +output [7:0] res_0_V_d0; +output [2:0] res_1_V_address0; +output res_1_V_ce0; +output res_1_V_we0; +output [7:0] res_1_V_d0; +output [2:0] res_2_V_address0; +output res_2_V_ce0; +output res_2_V_we0; +output [7:0] res_2_V_d0; +output [2:0] res_3_V_address0; +output res_3_V_ce0; +output res_3_V_we0; +output [7:0] res_3_V_d0; +output [2:0] res_4_V_address0; +output res_4_V_ce0; +output res_4_V_we0; +output [7:0] res_4_V_d0; +output [2:0] res_5_V_address0; +output res_5_V_ce0; +output res_5_V_we0; +output [7:0] res_5_V_d0; +output [2:0] res_6_V_address0; +output res_6_V_ce0; +output res_6_V_we0; +output [7:0] res_6_V_d0; +output [2:0] res_7_V_address0; +output res_7_V_ce0; +output res_7_V_we0; +output [7:0] res_7_V_d0; +output [2:0] res_8_V_address0; +output res_8_V_ce0; +output res_8_V_we0; +output [7:0] res_8_V_d0; +output [2:0] res_9_V_address0; +output res_9_V_ce0; +output res_9_V_we0; +output [7:0] res_9_V_d0; +output [2:0] res_10_V_address0; +output res_10_V_ce0; +output res_10_V_we0; +output [7:0] res_10_V_d0; +output [2:0] res_11_V_address0; +output res_11_V_ce0; +output res_11_V_we0; +output [7:0] res_11_V_d0; +output [2:0] res_12_V_address0; +output res_12_V_ce0; +output res_12_V_we0; +output [7:0] res_12_V_d0; +output [2:0] res_13_V_address0; +output res_13_V_ce0; +output res_13_V_we0; +output [7:0] res_13_V_d0; +output [2:0] res_14_V_address0; +output res_14_V_ce0; +output res_14_V_we0; +output [7:0] res_14_V_d0; +output [2:0] res_15_V_address0; +output res_15_V_ce0; +output res_15_V_we0; +output [7:0] res_15_V_d0; +output [2:0] res_16_V_address0; +output res_16_V_ce0; +output res_16_V_we0; +output [7:0] res_16_V_d0; +output [2:0] res_17_V_address0; +output res_17_V_ce0; +output res_17_V_we0; +output [7:0] res_17_V_d0; +output [2:0] res_18_V_address0; +output res_18_V_ce0; +output res_18_V_we0; +output [7:0] res_18_V_d0; +output [2:0] res_19_V_address0; +output res_19_V_ce0; +output res_19_V_we0; +output [7:0] res_19_V_d0; +output [2:0] res_20_V_address0; +output res_20_V_ce0; +output res_20_V_we0; +output [7:0] res_20_V_d0; +output [2:0] res_21_V_address0; +output res_21_V_ce0; +output res_21_V_we0; +output [7:0] res_21_V_d0; +output [2:0] res_22_V_address0; +output res_22_V_ce0; +output res_22_V_we0; +output [7:0] res_22_V_d0; +output [2:0] res_23_V_address0; +output res_23_V_ce0; +output res_23_V_we0; +output [7:0] res_23_V_d0; +output [2:0] res_24_V_address0; +output res_24_V_ce0; +output res_24_V_we0; +output [7:0] res_24_V_d0; +output [2:0] res_25_V_address0; +output res_25_V_ce0; +output res_25_V_we0; +output [7:0] res_25_V_d0; +output [2:0] res_26_V_address0; +output res_26_V_ce0; +output res_26_V_we0; +output [7:0] res_26_V_d0; +output [2:0] res_27_V_address0; +output res_27_V_ce0; +output res_27_V_we0; +output [7:0] res_27_V_d0; +output [2:0] res_28_V_address0; +output res_28_V_ce0; +output res_28_V_we0; +output [7:0] res_28_V_d0; +output [2:0] res_29_V_address0; +output res_29_V_ce0; +output res_29_V_we0; +output [7:0] res_29_V_d0; +output [2:0] res_30_V_address0; +output res_30_V_ce0; +output res_30_V_we0; +output [7:0] res_30_V_d0; +output [2:0] res_31_V_address0; +output res_31_V_ce0; +output res_31_V_we0; +output [7:0] res_31_V_d0; +output [2:0] res_32_V_address0; +output res_32_V_ce0; +output res_32_V_we0; +output [7:0] res_32_V_d0; +output [2:0] res_33_V_address0; +output res_33_V_ce0; +output res_33_V_we0; +output [7:0] res_33_V_d0; +output [2:0] res_34_V_address0; +output res_34_V_ce0; +output res_34_V_we0; +output [7:0] res_34_V_d0; +output [2:0] res_35_V_address0; +output res_35_V_ce0; +output res_35_V_we0; +output [7:0] res_35_V_d0; +output [2:0] res_36_V_address0; +output res_36_V_ce0; +output res_36_V_we0; +output [7:0] res_36_V_d0; +output [2:0] res_37_V_address0; +output res_37_V_ce0; +output res_37_V_we0; +output [7:0] res_37_V_d0; +output [2:0] res_38_V_address0; +output res_38_V_ce0; +output res_38_V_we0; +output [7:0] res_38_V_d0; +output [2:0] res_39_V_address0; +output res_39_V_ce0; +output res_39_V_we0; +output [7:0] res_39_V_d0; +output [2:0] res_40_V_address0; +output res_40_V_ce0; +output res_40_V_we0; +output [7:0] res_40_V_d0; +output [2:0] res_41_V_address0; +output res_41_V_ce0; +output res_41_V_we0; +output [7:0] res_41_V_d0; +output [2:0] res_42_V_address0; +output res_42_V_ce0; +output res_42_V_we0; +output [7:0] res_42_V_d0; +output [2:0] res_43_V_address0; +output res_43_V_ce0; +output res_43_V_we0; +output [7:0] res_43_V_d0; +output [2:0] res_44_V_address0; +output res_44_V_ce0; +output res_44_V_we0; +output [7:0] res_44_V_d0; +output [2:0] res_45_V_address0; +output res_45_V_ce0; +output res_45_V_we0; +output [7:0] res_45_V_d0; +output [2:0] res_46_V_address0; +output res_46_V_ce0; +output res_46_V_we0; +output [7:0] res_46_V_d0; +output [2:0] res_47_V_address0; +output res_47_V_ce0; +output res_47_V_we0; +output [7:0] res_47_V_d0; +output [2:0] res_48_V_address0; +output res_48_V_ce0; +output res_48_V_we0; +output [7:0] res_48_V_d0; +output [2:0] res_49_V_address0; +output res_49_V_ce0; +output res_49_V_we0; +output [7:0] res_49_V_d0; +output [2:0] res_50_V_address0; +output res_50_V_ce0; +output res_50_V_we0; +output [7:0] res_50_V_d0; +output [2:0] res_51_V_address0; +output res_51_V_ce0; +output res_51_V_we0; +output [7:0] res_51_V_d0; +output [2:0] res_52_V_address0; +output res_52_V_ce0; +output res_52_V_we0; +output [7:0] res_52_V_d0; +output [2:0] res_53_V_address0; +output res_53_V_ce0; +output res_53_V_we0; +output [7:0] res_53_V_d0; +output [2:0] res_54_V_address0; +output res_54_V_ce0; +output res_54_V_we0; +output [7:0] res_54_V_d0; +output [2:0] res_55_V_address0; +output res_55_V_ce0; +output res_55_V_we0; +output [7:0] res_55_V_d0; +output [2:0] res_56_V_address0; +output res_56_V_ce0; +output res_56_V_we0; +output [7:0] res_56_V_d0; +output [2:0] res_57_V_address0; +output res_57_V_ce0; +output res_57_V_we0; +output [7:0] res_57_V_d0; +output [2:0] res_58_V_address0; +output res_58_V_ce0; +output res_58_V_we0; +output [7:0] res_58_V_d0; +output [2:0] res_59_V_address0; +output res_59_V_ce0; +output res_59_V_we0; +output [7:0] res_59_V_d0; +output [2:0] res_60_V_address0; +output res_60_V_ce0; +output res_60_V_we0; +output [7:0] res_60_V_d0; +output [2:0] res_61_V_address0; +output res_61_V_ce0; +output res_61_V_we0; +output [7:0] res_61_V_d0; +output [2:0] res_62_V_address0; +output res_62_V_ce0; +output res_62_V_we0; +output [7:0] res_62_V_d0; +output [2:0] res_63_V_address0; +output res_63_V_ce0; +output res_63_V_we0; +output [7:0] res_63_V_d0; +output [2:0] res_64_V_address0; +output res_64_V_ce0; +output res_64_V_we0; +output [7:0] res_64_V_d0; +output [2:0] res_65_V_address0; +output res_65_V_ce0; +output res_65_V_we0; +output [7:0] res_65_V_d0; +output [2:0] res_66_V_address0; +output res_66_V_ce0; +output res_66_V_we0; +output [7:0] res_66_V_d0; +output [2:0] res_67_V_address0; +output res_67_V_ce0; +output res_67_V_we0; +output [7:0] res_67_V_d0; +output [2:0] res_68_V_address0; +output res_68_V_ce0; +output res_68_V_we0; +output [7:0] res_68_V_d0; +output [2:0] res_69_V_address0; +output res_69_V_ce0; +output res_69_V_we0; +output [7:0] res_69_V_d0; +output [2:0] res_70_V_address0; +output res_70_V_ce0; +output res_70_V_we0; +output [7:0] res_70_V_d0; +output [2:0] res_71_V_address0; +output res_71_V_ce0; +output res_71_V_we0; +output [7:0] res_71_V_d0; +output [2:0] res_72_V_address0; +output res_72_V_ce0; +output res_72_V_we0; +output [7:0] res_72_V_d0; +output [2:0] res_73_V_address0; +output res_73_V_ce0; +output res_73_V_we0; +output [7:0] res_73_V_d0; +output [2:0] res_74_V_address0; +output res_74_V_ce0; +output res_74_V_we0; +output [7:0] res_74_V_d0; +output [2:0] res_75_V_address0; +output res_75_V_ce0; +output res_75_V_we0; +output [7:0] res_75_V_d0; +output [2:0] res_76_V_address0; +output res_76_V_ce0; +output res_76_V_we0; +output [7:0] res_76_V_d0; +output [2:0] res_77_V_address0; +output res_77_V_ce0; +output res_77_V_we0; +output [7:0] res_77_V_d0; +output [2:0] res_78_V_address0; +output res_78_V_ce0; +output res_78_V_we0; +output [7:0] res_78_V_d0; +output [2:0] res_79_V_address0; +output res_79_V_ce0; +output res_79_V_we0; +output [7:0] res_79_V_d0; +output [2:0] res_80_V_address0; +output res_80_V_ce0; +output res_80_V_we0; +output [7:0] res_80_V_d0; +output [2:0] res_81_V_address0; +output res_81_V_ce0; +output res_81_V_we0; +output [7:0] res_81_V_d0; +output [2:0] res_82_V_address0; +output res_82_V_ce0; +output res_82_V_we0; +output [7:0] res_82_V_d0; +output [2:0] res_83_V_address0; +output res_83_V_ce0; +output res_83_V_we0; +output [7:0] res_83_V_d0; +output [2:0] res_84_V_address0; +output res_84_V_ce0; +output res_84_V_we0; +output [7:0] res_84_V_d0; +output [2:0] res_85_V_address0; +output res_85_V_ce0; +output res_85_V_we0; +output [7:0] res_85_V_d0; +output [2:0] res_86_V_address0; +output res_86_V_ce0; +output res_86_V_we0; +output [7:0] res_86_V_d0; +output [2:0] res_87_V_address0; +output res_87_V_ce0; +output res_87_V_we0; +output [7:0] res_87_V_d0; +output [2:0] res_88_V_address0; +output res_88_V_ce0; +output res_88_V_we0; +output [7:0] res_88_V_d0; +output [2:0] res_89_V_address0; +output res_89_V_ce0; +output res_89_V_we0; +output [7:0] res_89_V_d0; +output [2:0] res_90_V_address0; +output res_90_V_ce0; +output res_90_V_we0; +output [7:0] res_90_V_d0; +output [2:0] res_91_V_address0; +output res_91_V_ce0; +output res_91_V_we0; +output [7:0] res_91_V_d0; +output [2:0] res_92_V_address0; +output res_92_V_ce0; +output res_92_V_we0; +output [7:0] res_92_V_d0; +output [2:0] res_93_V_address0; +output res_93_V_ce0; +output res_93_V_we0; +output [7:0] res_93_V_d0; +output [2:0] res_94_V_address0; +output res_94_V_ce0; +output res_94_V_we0; +output [7:0] res_94_V_d0; +output [2:0] res_95_V_address0; +output res_95_V_ce0; +output res_95_V_we0; +output [7:0] res_95_V_d0; +output [2:0] res_96_V_address0; +output res_96_V_ce0; +output res_96_V_we0; +output [7:0] res_96_V_d0; +output [2:0] res_97_V_address0; +output res_97_V_ce0; +output res_97_V_we0; +output [7:0] res_97_V_d0; +output [2:0] res_98_V_address0; +output res_98_V_ce0; +output res_98_V_we0; +output [7:0] res_98_V_d0; +output [2:0] res_99_V_address0; +output res_99_V_ce0; +output res_99_V_we0; +output [7:0] res_99_V_d0; +output [2:0] res_100_V_address0; +output res_100_V_ce0; +output res_100_V_we0; +output [7:0] res_100_V_d0; +output [2:0] res_101_V_address0; +output res_101_V_ce0; +output res_101_V_we0; +output [7:0] res_101_V_d0; +output [2:0] res_102_V_address0; +output res_102_V_ce0; +output res_102_V_we0; +output [7:0] res_102_V_d0; +output [2:0] res_103_V_address0; +output res_103_V_ce0; +output res_103_V_we0; +output [7:0] res_103_V_d0; +output [2:0] res_104_V_address0; +output res_104_V_ce0; +output res_104_V_we0; +output [7:0] res_104_V_d0; +output [2:0] res_105_V_address0; +output res_105_V_ce0; +output res_105_V_we0; +output [7:0] res_105_V_d0; +output [2:0] res_106_V_address0; +output res_106_V_ce0; +output res_106_V_we0; +output [7:0] res_106_V_d0; +output [2:0] res_107_V_address0; +output res_107_V_ce0; +output res_107_V_we0; +output [7:0] res_107_V_d0; +output [2:0] res_108_V_address0; +output res_108_V_ce0; +output res_108_V_we0; +output [7:0] res_108_V_d0; +output [2:0] res_109_V_address0; +output res_109_V_ce0; +output res_109_V_we0; +output [7:0] res_109_V_d0; +output [2:0] res_110_V_address0; +output res_110_V_ce0; +output res_110_V_we0; +output [7:0] res_110_V_d0; +output [2:0] res_111_V_address0; +output res_111_V_ce0; +output res_111_V_we0; +output [7:0] res_111_V_d0; +output [2:0] res_112_V_address0; +output res_112_V_ce0; +output res_112_V_we0; +output [7:0] res_112_V_d0; +output [2:0] res_113_V_address0; +output res_113_V_ce0; +output res_113_V_we0; +output [7:0] res_113_V_d0; +output [2:0] res_114_V_address0; +output res_114_V_ce0; +output res_114_V_we0; +output [7:0] res_114_V_d0; +output [2:0] res_115_V_address0; +output res_115_V_ce0; +output res_115_V_we0; +output [7:0] res_115_V_d0; +output [2:0] res_116_V_address0; +output res_116_V_ce0; +output res_116_V_we0; +output [7:0] res_116_V_d0; +output [2:0] res_117_V_address0; +output res_117_V_ce0; +output res_117_V_we0; +output [7:0] res_117_V_d0; +output [2:0] res_118_V_address0; +output res_118_V_ce0; +output res_118_V_we0; +output [7:0] res_118_V_d0; +output [2:0] res_119_V_address0; +output res_119_V_ce0; +output res_119_V_we0; +output [7:0] res_119_V_d0; +output [2:0] res_120_V_address0; +output res_120_V_ce0; +output res_120_V_we0; +output [7:0] res_120_V_d0; +output [2:0] res_121_V_address0; +output res_121_V_ce0; +output res_121_V_we0; +output [7:0] res_121_V_d0; +output [2:0] res_122_V_address0; +output res_122_V_ce0; +output res_122_V_we0; +output [7:0] res_122_V_d0; +output [2:0] res_123_V_address0; +output res_123_V_ce0; +output res_123_V_we0; +output [7:0] res_123_V_d0; +output [2:0] res_124_V_address0; +output res_124_V_ce0; +output res_124_V_we0; +output [7:0] res_124_V_d0; +output [2:0] res_125_V_address0; +output res_125_V_ce0; +output res_125_V_we0; +output [7:0] res_125_V_d0; +output [2:0] res_126_V_address0; +output res_126_V_ce0; +output res_126_V_we0; +output [7:0] res_126_V_d0; +output [2:0] res_127_V_address0; +output res_127_V_ce0; +output res_127_V_we0; +output [7:0] res_127_V_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg data_0_V_ce0; +reg data_1_V_ce0; +reg data_2_V_ce0; +reg data_3_V_ce0; +reg data_4_V_ce0; +reg data_5_V_ce0; +reg data_6_V_ce0; +reg data_7_V_ce0; +reg data_8_V_ce0; +reg data_9_V_ce0; +reg data_10_V_ce0; +reg data_11_V_ce0; +reg data_12_V_ce0; +reg data_13_V_ce0; +reg data_14_V_ce0; +reg data_15_V_ce0; +reg data_16_V_ce0; +reg data_17_V_ce0; +reg data_18_V_ce0; +reg data_19_V_ce0; +reg data_20_V_ce0; +reg data_21_V_ce0; +reg data_22_V_ce0; +reg data_23_V_ce0; +reg data_24_V_ce0; +reg data_25_V_ce0; +reg data_26_V_ce0; +reg data_27_V_ce0; +reg data_28_V_ce0; +reg data_29_V_ce0; +reg data_30_V_ce0; +reg data_31_V_ce0; +reg data_32_V_ce0; +reg data_33_V_ce0; +reg data_34_V_ce0; +reg data_35_V_ce0; +reg data_36_V_ce0; +reg data_37_V_ce0; +reg data_38_V_ce0; +reg data_39_V_ce0; +reg data_40_V_ce0; +reg data_41_V_ce0; +reg data_42_V_ce0; +reg data_43_V_ce0; +reg data_44_V_ce0; +reg data_45_V_ce0; +reg data_46_V_ce0; +reg data_47_V_ce0; +reg data_48_V_ce0; +reg data_49_V_ce0; +reg data_50_V_ce0; +reg data_51_V_ce0; +reg data_52_V_ce0; +reg data_53_V_ce0; +reg data_54_V_ce0; +reg data_55_V_ce0; +reg data_56_V_ce0; +reg data_57_V_ce0; +reg data_58_V_ce0; +reg data_59_V_ce0; +reg data_60_V_ce0; +reg data_61_V_ce0; +reg data_62_V_ce0; +reg data_63_V_ce0; +reg data_64_V_ce0; +reg data_65_V_ce0; +reg data_66_V_ce0; +reg data_67_V_ce0; +reg data_68_V_ce0; +reg data_69_V_ce0; +reg data_70_V_ce0; +reg data_71_V_ce0; +reg data_72_V_ce0; +reg data_73_V_ce0; +reg data_74_V_ce0; +reg data_75_V_ce0; +reg data_76_V_ce0; +reg data_77_V_ce0; +reg data_78_V_ce0; +reg data_79_V_ce0; +reg data_80_V_ce0; +reg data_81_V_ce0; +reg data_82_V_ce0; +reg data_83_V_ce0; +reg data_84_V_ce0; +reg data_85_V_ce0; +reg data_86_V_ce0; +reg data_87_V_ce0; +reg data_88_V_ce0; +reg data_89_V_ce0; +reg data_90_V_ce0; +reg data_91_V_ce0; +reg data_92_V_ce0; +reg data_93_V_ce0; +reg data_94_V_ce0; +reg data_95_V_ce0; +reg data_96_V_ce0; +reg data_97_V_ce0; +reg data_98_V_ce0; +reg data_99_V_ce0; +reg data_100_V_ce0; +reg data_101_V_ce0; +reg data_102_V_ce0; +reg data_103_V_ce0; +reg data_104_V_ce0; +reg data_105_V_ce0; +reg data_106_V_ce0; +reg data_107_V_ce0; +reg data_108_V_ce0; +reg data_109_V_ce0; +reg data_110_V_ce0; +reg data_111_V_ce0; +reg data_112_V_ce0; +reg data_113_V_ce0; +reg data_114_V_ce0; +reg data_115_V_ce0; +reg data_116_V_ce0; +reg data_117_V_ce0; +reg data_118_V_ce0; +reg data_119_V_ce0; +reg data_120_V_ce0; +reg data_121_V_ce0; +reg data_122_V_ce0; +reg data_123_V_ce0; +reg data_124_V_ce0; +reg data_125_V_ce0; +reg data_126_V_ce0; +reg data_127_V_ce0; +reg res_0_V_ce0; +reg res_0_V_we0; +reg res_1_V_ce0; +reg res_1_V_we0; +reg res_2_V_ce0; +reg res_2_V_we0; +reg res_3_V_ce0; +reg res_3_V_we0; +reg res_4_V_ce0; +reg res_4_V_we0; +reg res_5_V_ce0; +reg res_5_V_we0; +reg res_6_V_ce0; +reg res_6_V_we0; +reg res_7_V_ce0; +reg res_7_V_we0; +reg res_8_V_ce0; +reg res_8_V_we0; +reg res_9_V_ce0; +reg res_9_V_we0; +reg res_10_V_ce0; +reg res_10_V_we0; +reg res_11_V_ce0; +reg res_11_V_we0; +reg res_12_V_ce0; +reg res_12_V_we0; +reg res_13_V_ce0; +reg res_13_V_we0; +reg res_14_V_ce0; +reg res_14_V_we0; +reg res_15_V_ce0; +reg res_15_V_we0; +reg res_16_V_ce0; +reg res_16_V_we0; +reg res_17_V_ce0; +reg res_17_V_we0; +reg res_18_V_ce0; +reg res_18_V_we0; +reg res_19_V_ce0; +reg res_19_V_we0; +reg res_20_V_ce0; +reg res_20_V_we0; +reg res_21_V_ce0; +reg res_21_V_we0; +reg res_22_V_ce0; +reg res_22_V_we0; +reg res_23_V_ce0; +reg res_23_V_we0; +reg res_24_V_ce0; +reg res_24_V_we0; +reg res_25_V_ce0; +reg res_25_V_we0; +reg res_26_V_ce0; +reg res_26_V_we0; +reg res_27_V_ce0; +reg res_27_V_we0; +reg res_28_V_ce0; +reg res_28_V_we0; +reg res_29_V_ce0; +reg res_29_V_we0; +reg res_30_V_ce0; +reg res_30_V_we0; +reg res_31_V_ce0; +reg res_31_V_we0; +reg res_32_V_ce0; +reg res_32_V_we0; +reg res_33_V_ce0; +reg res_33_V_we0; +reg res_34_V_ce0; +reg res_34_V_we0; +reg res_35_V_ce0; +reg res_35_V_we0; +reg res_36_V_ce0; +reg res_36_V_we0; +reg res_37_V_ce0; +reg res_37_V_we0; +reg res_38_V_ce0; +reg res_38_V_we0; +reg res_39_V_ce0; +reg res_39_V_we0; +reg res_40_V_ce0; +reg res_40_V_we0; +reg res_41_V_ce0; +reg res_41_V_we0; +reg res_42_V_ce0; +reg res_42_V_we0; +reg res_43_V_ce0; +reg res_43_V_we0; +reg res_44_V_ce0; +reg res_44_V_we0; +reg res_45_V_ce0; +reg res_45_V_we0; +reg res_46_V_ce0; +reg res_46_V_we0; +reg res_47_V_ce0; +reg res_47_V_we0; +reg res_48_V_ce0; +reg res_48_V_we0; +reg res_49_V_ce0; +reg res_49_V_we0; +reg res_50_V_ce0; +reg res_50_V_we0; +reg res_51_V_ce0; +reg res_51_V_we0; +reg res_52_V_ce0; +reg res_52_V_we0; +reg res_53_V_ce0; +reg res_53_V_we0; +reg res_54_V_ce0; +reg res_54_V_we0; +reg res_55_V_ce0; +reg res_55_V_we0; +reg res_56_V_ce0; +reg res_56_V_we0; +reg res_57_V_ce0; +reg res_57_V_we0; +reg res_58_V_ce0; +reg res_58_V_we0; +reg res_59_V_ce0; +reg res_59_V_we0; +reg res_60_V_ce0; +reg res_60_V_we0; +reg res_61_V_ce0; +reg res_61_V_we0; +reg res_62_V_ce0; +reg res_62_V_we0; +reg res_63_V_ce0; +reg res_63_V_we0; +reg res_64_V_ce0; +reg res_64_V_we0; +reg res_65_V_ce0; +reg res_65_V_we0; +reg res_66_V_ce0; +reg res_66_V_we0; +reg res_67_V_ce0; +reg res_67_V_we0; +reg res_68_V_ce0; +reg res_68_V_we0; +reg res_69_V_ce0; +reg res_69_V_we0; +reg res_70_V_ce0; +reg res_70_V_we0; +reg res_71_V_ce0; +reg res_71_V_we0; +reg res_72_V_ce0; +reg res_72_V_we0; +reg res_73_V_ce0; +reg res_73_V_we0; +reg res_74_V_ce0; +reg res_74_V_we0; +reg res_75_V_ce0; +reg res_75_V_we0; +reg res_76_V_ce0; +reg res_76_V_we0; +reg res_77_V_ce0; +reg res_77_V_we0; +reg res_78_V_ce0; +reg res_78_V_we0; +reg res_79_V_ce0; +reg res_79_V_we0; +reg res_80_V_ce0; +reg res_80_V_we0; +reg res_81_V_ce0; +reg res_81_V_we0; +reg res_82_V_ce0; +reg res_82_V_we0; +reg res_83_V_ce0; +reg res_83_V_we0; +reg res_84_V_ce0; +reg res_84_V_we0; +reg res_85_V_ce0; +reg res_85_V_we0; +reg res_86_V_ce0; +reg res_86_V_we0; +reg res_87_V_ce0; +reg res_87_V_we0; +reg res_88_V_ce0; +reg res_88_V_we0; +reg res_89_V_ce0; +reg res_89_V_we0; +reg res_90_V_ce0; +reg res_90_V_we0; +reg res_91_V_ce0; +reg res_91_V_we0; +reg res_92_V_ce0; +reg res_92_V_we0; +reg res_93_V_ce0; +reg res_93_V_we0; +reg res_94_V_ce0; +reg res_94_V_we0; +reg res_95_V_ce0; +reg res_95_V_we0; +reg res_96_V_ce0; +reg res_96_V_we0; +reg res_97_V_ce0; +reg res_97_V_we0; +reg res_98_V_ce0; +reg res_98_V_we0; +reg res_99_V_ce0; +reg res_99_V_we0; +reg res_100_V_ce0; +reg res_100_V_we0; +reg res_101_V_ce0; +reg res_101_V_we0; +reg res_102_V_ce0; +reg res_102_V_we0; +reg res_103_V_ce0; +reg res_103_V_we0; +reg res_104_V_ce0; +reg res_104_V_we0; +reg res_105_V_ce0; +reg res_105_V_we0; +reg res_106_V_ce0; +reg res_106_V_we0; +reg res_107_V_ce0; +reg res_107_V_we0; +reg res_108_V_ce0; +reg res_108_V_we0; +reg res_109_V_ce0; +reg res_109_V_we0; +reg res_110_V_ce0; +reg res_110_V_we0; +reg res_111_V_ce0; +reg res_111_V_we0; +reg res_112_V_ce0; +reg res_112_V_we0; +reg res_113_V_ce0; +reg res_113_V_we0; +reg res_114_V_ce0; +reg res_114_V_we0; +reg res_115_V_ce0; +reg res_115_V_we0; +reg res_116_V_ce0; +reg res_116_V_we0; +reg res_117_V_ce0; +reg res_117_V_we0; +reg res_118_V_ce0; +reg res_118_V_we0; +reg res_119_V_ce0; +reg res_119_V_we0; +reg res_120_V_ce0; +reg res_120_V_we0; +reg res_121_V_ce0; +reg res_121_V_we0; +reg res_122_V_ce0; +reg res_122_V_we0; +reg res_123_V_ce0; +reg res_123_V_we0; +reg res_124_V_ce0; +reg res_124_V_we0; +reg res_125_V_ce0; +reg res_125_V_we0; +reg res_126_V_ce0; +reg res_126_V_we0; +reg res_127_V_ce0; +reg res_127_V_we0; + + reg [3:0] ap_CS_fsm; +wire [2:0] ff_fu_4684_p2; +reg [2:0] ff_reg_5304; +wire [10:0] or_ln_fu_4736_p3; +reg [10:0] or_ln_reg_5312; +wire [0:0] icmp_ln211_fu_4690_p2; +wire [6:0] trunc_ln_fu_4754_p3; +reg [6:0] trunc_ln_reg_5317; +wire [4:0] ii_fu_4768_p2; +wire [0:0] icmp_ln213_fu_4762_p2; +wire [1:0] kk_fu_4784_p2; +reg [1:0] kk_reg_5333; +wire [0:0] icmp_ln221_fu_4796_p2; +reg [0:0] icmp_ln221_reg_5338; +wire [0:0] icmp_ln218_fu_4778_p2; +wire [1:0] shl_ln223_fu_4802_p2; +reg [1:0] shl_ln223_reg_5342; +wire [12:0] or_ln1_fu_4848_p3; +reg [12:0] or_ln1_reg_5348; +wire [6:0] or_ln225_1_fu_4866_p3; +reg [6:0] or_ln225_1_reg_5353; +wire [1:0] ll_fu_4884_p2; +reg [1:0] ll_reg_5361; +wire [0:0] icmp_ln221_2_fu_4896_p2; +reg [0:0] icmp_ln221_2_reg_5366; +wire [0:0] icmp_ln220_fu_4878_p2; +wire [63:0] zext_ln225_fu_4907_p1; +reg [63:0] zext_ln225_reg_5370; +wire [6:0] add_ln203_2_fu_4928_p2; +reg [6:0] add_ln203_2_reg_5375; +reg [7:0] data_126_V_load_reg_6019; +reg [7:0] data_125_V_load_reg_6024; +reg [7:0] data_124_V_load_reg_6029; +reg [7:0] data_123_V_load_reg_6034; +reg [7:0] data_122_V_load_reg_6039; +reg [7:0] data_121_V_load_reg_6044; +reg [7:0] data_120_V_load_reg_6049; +reg [7:0] data_119_V_load_reg_6054; +reg [7:0] data_118_V_load_reg_6059; +reg [7:0] data_117_V_load_reg_6064; +reg [7:0] data_116_V_load_reg_6069; +reg [7:0] data_115_V_load_reg_6074; +reg [7:0] data_114_V_load_reg_6079; +reg [7:0] data_113_V_load_reg_6084; +reg [7:0] data_112_V_load_reg_6089; +reg [7:0] data_111_V_load_reg_6094; +reg [7:0] data_110_V_load_reg_6099; +reg [7:0] data_109_V_load_reg_6104; +reg [7:0] data_108_V_load_reg_6109; +reg [7:0] data_107_V_load_reg_6114; +reg [7:0] data_106_V_load_reg_6119; +reg [7:0] data_105_V_load_reg_6124; +reg [7:0] data_104_V_load_reg_6129; +reg [7:0] data_103_V_load_reg_6134; +reg [7:0] data_102_V_load_reg_6139; +reg [7:0] data_101_V_load_reg_6144; +reg [7:0] data_100_V_load_reg_6149; +reg [7:0] data_99_V_load_reg_6154; +reg [7:0] data_98_V_load_reg_6159; +reg [7:0] data_97_V_load_reg_6164; +reg [7:0] data_96_V_load_reg_6169; +reg [7:0] data_95_V_load_reg_6174; +reg [7:0] data_94_V_load_reg_6179; +reg [7:0] data_93_V_load_reg_6184; +reg [7:0] data_92_V_load_reg_6189; +reg [7:0] data_91_V_load_reg_6194; +reg [7:0] data_90_V_load_reg_6199; +reg [7:0] data_89_V_load_reg_6204; +reg [7:0] data_88_V_load_reg_6209; +reg [7:0] data_87_V_load_reg_6214; +reg [7:0] data_86_V_load_reg_6219; +reg [7:0] data_85_V_load_reg_6224; +reg [7:0] data_84_V_load_reg_6229; +reg [7:0] data_83_V_load_reg_6234; +reg [7:0] data_82_V_load_reg_6239; +reg [7:0] data_81_V_load_reg_6244; +reg [7:0] data_80_V_load_reg_6249; +reg [7:0] data_79_V_load_reg_6254; +reg [7:0] data_78_V_load_reg_6259; +reg [7:0] data_77_V_load_reg_6264; +reg [7:0] data_76_V_load_reg_6269; +reg [7:0] data_75_V_load_reg_6274; +reg [7:0] data_74_V_load_reg_6279; +reg [7:0] data_73_V_load_reg_6284; +reg [7:0] data_72_V_load_reg_6289; +reg [7:0] data_71_V_load_reg_6294; +reg [7:0] data_70_V_load_reg_6299; +reg [7:0] data_69_V_load_reg_6304; +reg [7:0] data_68_V_load_reg_6309; +reg [7:0] data_67_V_load_reg_6314; +reg [7:0] data_66_V_load_reg_6319; +reg [7:0] data_65_V_load_reg_6324; +reg [7:0] data_64_V_load_reg_6329; +reg [7:0] data_63_V_load_reg_6334; +reg [7:0] data_62_V_load_reg_6339; +reg [7:0] data_61_V_load_reg_6344; +reg [7:0] data_60_V_load_reg_6349; +reg [7:0] data_59_V_load_reg_6354; +reg [7:0] data_58_V_load_reg_6359; +reg [7:0] data_57_V_load_reg_6364; +reg [7:0] data_56_V_load_reg_6369; +reg [7:0] data_55_V_load_reg_6374; +reg [7:0] data_54_V_load_reg_6379; +reg [7:0] data_53_V_load_reg_6384; +reg [7:0] data_52_V_load_reg_6389; +reg [7:0] data_51_V_load_reg_6394; +reg [7:0] data_50_V_load_reg_6399; +reg [7:0] data_49_V_load_reg_6404; +reg [7:0] data_48_V_load_reg_6409; +reg [7:0] data_47_V_load_reg_6414; +reg [7:0] data_46_V_load_reg_6419; +reg [7:0] data_45_V_load_reg_6424; +reg [7:0] data_44_V_load_reg_6429; +reg [7:0] data_43_V_load_reg_6434; +reg [7:0] data_42_V_load_reg_6439; +reg [7:0] data_41_V_load_reg_6444; +reg [7:0] data_40_V_load_reg_6449; +reg [7:0] data_39_V_load_reg_6454; +reg [7:0] data_38_V_load_reg_6459; +reg [7:0] data_37_V_load_reg_6464; +reg [7:0] data_36_V_load_reg_6469; +reg [7:0] data_35_V_load_reg_6474; +reg [7:0] data_34_V_load_reg_6479; +reg [7:0] data_33_V_load_reg_6484; +reg [7:0] data_32_V_load_reg_6489; +reg [7:0] data_31_V_load_reg_6494; +reg [7:0] data_30_V_load_reg_6499; +reg [7:0] data_29_V_load_reg_6504; +reg [7:0] data_28_V_load_reg_6509; +reg [7:0] data_27_V_load_reg_6514; +reg [7:0] data_26_V_load_reg_6519; +reg [7:0] data_25_V_load_reg_6524; +reg [7:0] data_24_V_load_reg_6529; +reg [7:0] data_23_V_load_reg_6534; +reg [7:0] data_22_V_load_reg_6539; +reg [7:0] data_21_V_load_reg_6544; +reg [7:0] data_20_V_load_reg_6549; +reg [7:0] data_19_V_load_reg_6554; +reg [7:0] data_18_V_load_reg_6559; +reg [7:0] data_17_V_load_reg_6564; +reg [7:0] data_16_V_load_reg_6569; +reg [7:0] data_15_V_load_reg_6574; +reg [7:0] data_14_V_load_reg_6579; +reg [7:0] data_13_V_load_reg_6584; +reg [7:0] data_12_V_load_reg_6589; +reg [7:0] data_11_V_load_reg_6594; +reg [7:0] data_10_V_load_reg_6599; +reg [7:0] data_9_V_load_reg_6604; +reg [7:0] data_8_V_load_reg_6609; +reg [7:0] data_7_V_load_reg_6614; +reg [7:0] data_6_V_load_reg_6619; +reg [7:0] data_5_V_load_reg_6624; +reg [7:0] data_4_V_load_reg_6629; +reg [7:0] data_3_V_load_reg_6634; +reg [7:0] data_2_V_load_reg_6639; +reg [7:0] data_1_V_load_reg_6644; +reg [7:0] data_0_V_load_reg_6649; +reg [7:0] data_127_V_load_reg_6654; +wire [6:0] zext_ln233_5_fu_5101_p1; +reg [6:0] zext_ln233_5_reg_6659; +wire [10:0] add_ln233_fu_5105_p2; +reg [10:0] add_ln233_reg_6664; +wire [7:0] pool_V_q0; +wire [0:0] icmp_ln13_fu_5110_p2; +wire [2:0] i_fu_5121_p2; +reg [2:0] i_reg_6682; +wire [7:0] y_V_2_fu_5282_p3; +wire [4:0] jj_fu_5290_p2; +reg [1:0] pool_V_address0; +reg pool_V_ce0; +reg pool_V_we0; +reg [7:0] pool_V_d0; +reg [2:0] ff_0_reg_4209; +reg [4:0] ii_0_reg_4221; +wire [0:0] icmp_ln209_fu_4678_p2; +reg [4:0] jj_0_reg_4233; +reg [1:0] kk_0_reg_4245; +reg [1:0] ll_0_reg_4256; +reg [7:0] phi_ln203_reg_4267; +reg [7:0] agg_result_V_0_i_i_reg_4529; +reg [2:0] i_0_i_i_reg_4667; +wire [63:0] zext_ln203_2_fu_4947_p1; +wire [63:0] zext_ln223_fu_5084_p1; +wire [63:0] zext_ln14_fu_5116_p1; +wire [63:0] zext_ln203_fu_5144_p1; +wire [6:0] add_ln203_fu_5127_p2; +wire [9:0] shl_ln_fu_4696_p3; +wire [6:0] shl_ln233_2_fu_4708_p3; +wire [10:0] zext_ln233_fu_4704_p1; +wire [10:0] zext_ln233_3_fu_4716_p1; +wire [10:0] sub_ln233_fu_4720_p2; +wire [7:0] tmp_fu_4726_p4; +wire [3:0] tmp_1_fu_4744_p4; +wire [4:0] zext_ln218_fu_4774_p1; +wire [4:0] add_ln221_fu_4790_p2; +wire [11:0] shl_ln4_fu_4808_p3; +wire [8:0] shl_ln225_2_fu_4820_p3; +wire [12:0] zext_ln225_4_fu_4816_p1; +wire [12:0] zext_ln225_5_fu_4828_p1; +wire [12:0] sub_ln225_fu_4832_p2; +wire [9:0] tmp_2_fu_4838_p4; +wire [3:0] tmp_3_fu_4856_p4; +wire [4:0] zext_ln220_fu_4874_p1; +wire [4:0] add_ln221_2_fu_4890_p2; +wire [1:0] add_ln225_fu_4902_p2; +wire [6:0] shl_ln225_3_fu_4911_p3; +wire [12:0] zext_ln225_6_fu_4919_p1; +wire [12:0] add_ln225_3_fu_4923_p2; +wire [5:0] trunc_ln203_2_fu_4933_p4; +wire [24:0] sext_ln203_2_fu_4943_p1; +wire [1:0] add_ln223_fu_5079_p2; +wire [5:0] shl_ln233_3_fu_5089_p3; +wire [10:0] zext_ln233_4_fu_5097_p1; +wire [3:0] trunc_ln3_fu_5131_p4; +wire [24:0] sext_ln203_fu_5140_p1; +wire [0:0] icmp_ln1494_fu_5276_p2; +reg [3:0] ap_NS_fsm; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 4'd0; +end + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +pool_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(pool_V_address0), + .ce0(pool_V_ce0), + .we0(pool_V_we0), + .d0(pool_V_d0), + .q0(pool_V_q0) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state12 == ap_CS_fsm)) begin + agg_result_V_0_i_i_reg_4529 <= y_V_2_fu_5282_p3; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + agg_result_V_0_i_i_reg_4529 <= pool_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln211_fu_4690_p2 == 1'd0))) begin + ff_0_reg_4209 <= ff_reg_5304; + end else if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b1))) begin + ff_0_reg_4209 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state12 == ap_CS_fsm)) begin + i_0_i_i_reg_4667 <= i_reg_6682; + end else if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + i_0_i_i_reg_4667 <= 3'd1; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2 == ap_CS_fsm) & (icmp_ln209_fu_4678_p2 == 1'd0))) begin + ii_0_reg_4221 <= 5'd0; + end else if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln213_fu_4762_p2 == 1'd0))) begin + ii_0_reg_4221 <= ii_fu_4768_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln211_fu_4690_p2 == 1'd1))) begin + jj_0_reg_4233 <= 5'd0; + end else if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + jj_0_reg_4233 <= jj_fu_5290_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln213_fu_4762_p2 == 1'd1))) begin + kk_0_reg_4245 <= 2'd0; + end else if (((ap_ST_fsm_state6 == ap_CS_fsm) & (icmp_ln220_fu_4878_p2 == 1'd1))) begin + kk_0_reg_4245 <= kk_reg_5333; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state5 == ap_CS_fsm) & (icmp_ln218_fu_4778_p2 == 1'd0))) begin + ll_0_reg_4256 <= 2'd0; + end else if ((ap_ST_fsm_state9 == ap_CS_fsm)) begin + ll_0_reg_4256 <= ll_reg_5361; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + if ((7'd127 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_127_V_load_reg_6654; + end else if ((7'd126 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_126_V_load_reg_6019; + end else if ((7'd125 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_125_V_load_reg_6024; + end else if ((7'd124 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_124_V_load_reg_6029; + end else if ((7'd123 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_123_V_load_reg_6034; + end else if ((7'd122 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_122_V_load_reg_6039; + end else if ((7'd121 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_121_V_load_reg_6044; + end else if ((7'd120 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_120_V_load_reg_6049; + end else if ((7'd119 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_119_V_load_reg_6054; + end else if ((7'd118 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_118_V_load_reg_6059; + end else if ((7'd117 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_117_V_load_reg_6064; + end else if ((7'd116 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_116_V_load_reg_6069; + end else if ((7'd115 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_115_V_load_reg_6074; + end else if ((7'd114 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_114_V_load_reg_6079; + end else if ((7'd113 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_113_V_load_reg_6084; + end else if ((7'd112 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_112_V_load_reg_6089; + end else if ((7'd111 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_111_V_load_reg_6094; + end else if ((7'd110 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_110_V_load_reg_6099; + end else if ((7'd109 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_109_V_load_reg_6104; + end else if ((7'd108 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_108_V_load_reg_6109; + end else if ((7'd107 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_107_V_load_reg_6114; + end else if ((7'd106 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_106_V_load_reg_6119; + end else if ((7'd105 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_105_V_load_reg_6124; + end else if ((7'd104 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_104_V_load_reg_6129; + end else if ((7'd103 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_103_V_load_reg_6134; + end else if ((7'd102 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_102_V_load_reg_6139; + end else if ((7'd101 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_101_V_load_reg_6144; + end else if ((7'd100 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_100_V_load_reg_6149; + end else if ((7'd99 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_99_V_load_reg_6154; + end else if ((7'd98 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_98_V_load_reg_6159; + end else if ((7'd97 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_97_V_load_reg_6164; + end else if ((7'd96 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_96_V_load_reg_6169; + end else if ((7'd95 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_95_V_load_reg_6174; + end else if ((7'd94 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_94_V_load_reg_6179; + end else if ((7'd93 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_93_V_load_reg_6184; + end else if ((7'd92 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_92_V_load_reg_6189; + end else if ((7'd91 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_91_V_load_reg_6194; + end else if ((7'd90 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_90_V_load_reg_6199; + end else if ((7'd89 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_89_V_load_reg_6204; + end else if ((7'd88 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_88_V_load_reg_6209; + end else if ((7'd87 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_87_V_load_reg_6214; + end else if ((7'd86 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_86_V_load_reg_6219; + end else if ((7'd85 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_85_V_load_reg_6224; + end else if ((7'd84 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_84_V_load_reg_6229; + end else if ((7'd83 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_83_V_load_reg_6234; + end else if ((7'd82 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_82_V_load_reg_6239; + end else if ((7'd81 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_81_V_load_reg_6244; + end else if ((7'd80 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_80_V_load_reg_6249; + end else if ((7'd79 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_79_V_load_reg_6254; + end else if ((7'd78 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_78_V_load_reg_6259; + end else if ((7'd77 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_77_V_load_reg_6264; + end else if ((7'd76 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_76_V_load_reg_6269; + end else if ((7'd75 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_75_V_load_reg_6274; + end else if ((7'd74 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_74_V_load_reg_6279; + end else if ((7'd73 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_73_V_load_reg_6284; + end else if ((7'd72 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_72_V_load_reg_6289; + end else if ((7'd71 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_71_V_load_reg_6294; + end else if ((7'd70 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_70_V_load_reg_6299; + end else if ((7'd69 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_69_V_load_reg_6304; + end else if ((7'd68 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_68_V_load_reg_6309; + end else if ((7'd67 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_67_V_load_reg_6314; + end else if ((7'd66 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_66_V_load_reg_6319; + end else if ((7'd65 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_65_V_load_reg_6324; + end else if ((7'd64 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_64_V_load_reg_6329; + end else if ((7'd63 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_63_V_load_reg_6334; + end else if ((7'd62 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_62_V_load_reg_6339; + end else if ((7'd61 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_61_V_load_reg_6344; + end else if ((7'd60 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_60_V_load_reg_6349; + end else if ((7'd59 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_59_V_load_reg_6354; + end else if ((7'd58 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_58_V_load_reg_6359; + end else if ((7'd57 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_57_V_load_reg_6364; + end else if ((7'd56 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_56_V_load_reg_6369; + end else if ((7'd55 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_55_V_load_reg_6374; + end else if ((7'd54 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_54_V_load_reg_6379; + end else if ((7'd53 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_53_V_load_reg_6384; + end else if ((7'd52 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_52_V_load_reg_6389; + end else if ((7'd51 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_51_V_load_reg_6394; + end else if ((7'd50 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_50_V_load_reg_6399; + end else if ((7'd49 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_49_V_load_reg_6404; + end else if ((7'd48 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_48_V_load_reg_6409; + end else if ((7'd47 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_47_V_load_reg_6414; + end else if ((7'd46 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_46_V_load_reg_6419; + end else if ((7'd45 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_45_V_load_reg_6424; + end else if ((7'd44 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_44_V_load_reg_6429; + end else if ((7'd43 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_43_V_load_reg_6434; + end else if ((7'd42 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_42_V_load_reg_6439; + end else if ((7'd41 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_41_V_load_reg_6444; + end else if ((7'd40 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_40_V_load_reg_6449; + end else if ((7'd39 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_39_V_load_reg_6454; + end else if ((7'd38 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_38_V_load_reg_6459; + end else if ((7'd37 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_37_V_load_reg_6464; + end else if ((7'd36 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_36_V_load_reg_6469; + end else if ((7'd35 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_35_V_load_reg_6474; + end else if ((7'd34 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_34_V_load_reg_6479; + end else if ((7'd33 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_33_V_load_reg_6484; + end else if ((7'd32 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_32_V_load_reg_6489; + end else if ((7'd31 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_31_V_load_reg_6494; + end else if ((7'd30 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_30_V_load_reg_6499; + end else if ((7'd29 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_29_V_load_reg_6504; + end else if ((7'd28 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_28_V_load_reg_6509; + end else if ((7'd27 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_27_V_load_reg_6514; + end else if ((7'd26 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_26_V_load_reg_6519; + end else if ((7'd25 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_25_V_load_reg_6524; + end else if ((7'd24 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_24_V_load_reg_6529; + end else if ((7'd23 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_23_V_load_reg_6534; + end else if ((7'd22 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_22_V_load_reg_6539; + end else if ((7'd21 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_21_V_load_reg_6544; + end else if ((7'd20 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_20_V_load_reg_6549; + end else if ((7'd19 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_19_V_load_reg_6554; + end else if ((7'd18 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_18_V_load_reg_6559; + end else if ((7'd17 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_17_V_load_reg_6564; + end else if ((7'd16 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_16_V_load_reg_6569; + end else if ((7'd15 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_15_V_load_reg_6574; + end else if ((7'd14 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_14_V_load_reg_6579; + end else if ((7'd13 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_13_V_load_reg_6584; + end else if ((7'd12 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_12_V_load_reg_6589; + end else if ((7'd11 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_11_V_load_reg_6594; + end else if ((7'd10 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_10_V_load_reg_6599; + end else if ((7'd9 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_9_V_load_reg_6604; + end else if ((7'd8 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_8_V_load_reg_6609; + end else if ((7'd7 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_7_V_load_reg_6614; + end else if ((7'd6 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_6_V_load_reg_6619; + end else if ((7'd5 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_5_V_load_reg_6624; + end else if ((7'd4 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_4_V_load_reg_6629; + end else if ((7'd3 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_3_V_load_reg_6634; + end else if ((7'd2 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_2_V_load_reg_6639; + end else if ((7'd1 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_1_V_load_reg_6644; + end else if ((7'd0 == add_ln203_2_reg_5375)) begin + phi_ln203_reg_4267 <= data_0_V_load_reg_6649; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state6 == ap_CS_fsm) & (icmp_ln220_fu_4878_p2 == 1'd0) & (icmp_ln221_2_fu_4896_p2 == 1'd0) & (icmp_ln221_reg_5338 == 1'd0))) begin + add_ln203_2_reg_5375 <= add_ln203_2_fu_4928_p2; + zext_ln225_reg_5370[1 : 0] <= zext_ln225_fu_4907_p1[1 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + add_ln233_reg_6664 <= add_ln233_fu_5105_p2; + zext_ln233_5_reg_6659[5 : 1] <= zext_ln233_5_fu_5101_p1[5 : 1]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd0 == add_ln203_2_reg_5375))) begin + data_0_V_load_reg_6649 <= data_0_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd100 == add_ln203_2_reg_5375))) begin + data_100_V_load_reg_6149 <= data_100_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd101 == add_ln203_2_reg_5375))) begin + data_101_V_load_reg_6144 <= data_101_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd102 == add_ln203_2_reg_5375))) begin + data_102_V_load_reg_6139 <= data_102_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd103 == add_ln203_2_reg_5375))) begin + data_103_V_load_reg_6134 <= data_103_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd104 == add_ln203_2_reg_5375))) begin + data_104_V_load_reg_6129 <= data_104_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd105 == add_ln203_2_reg_5375))) begin + data_105_V_load_reg_6124 <= data_105_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd106 == add_ln203_2_reg_5375))) begin + data_106_V_load_reg_6119 <= data_106_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd107 == add_ln203_2_reg_5375))) begin + data_107_V_load_reg_6114 <= data_107_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd108 == add_ln203_2_reg_5375))) begin + data_108_V_load_reg_6109 <= data_108_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd109 == add_ln203_2_reg_5375))) begin + data_109_V_load_reg_6104 <= data_109_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd10 == add_ln203_2_reg_5375))) begin + data_10_V_load_reg_6599 <= data_10_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd110 == add_ln203_2_reg_5375))) begin + data_110_V_load_reg_6099 <= data_110_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd111 == add_ln203_2_reg_5375))) begin + data_111_V_load_reg_6094 <= data_111_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd112 == add_ln203_2_reg_5375))) begin + data_112_V_load_reg_6089 <= data_112_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd113 == add_ln203_2_reg_5375))) begin + data_113_V_load_reg_6084 <= data_113_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd114 == add_ln203_2_reg_5375))) begin + data_114_V_load_reg_6079 <= data_114_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd115 == add_ln203_2_reg_5375))) begin + data_115_V_load_reg_6074 <= data_115_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd116 == add_ln203_2_reg_5375))) begin + data_116_V_load_reg_6069 <= data_116_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd117 == add_ln203_2_reg_5375))) begin + data_117_V_load_reg_6064 <= data_117_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd118 == add_ln203_2_reg_5375))) begin + data_118_V_load_reg_6059 <= data_118_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd119 == add_ln203_2_reg_5375))) begin + data_119_V_load_reg_6054 <= data_119_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd11 == add_ln203_2_reg_5375))) begin + data_11_V_load_reg_6594 <= data_11_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd120 == add_ln203_2_reg_5375))) begin + data_120_V_load_reg_6049 <= data_120_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd121 == add_ln203_2_reg_5375))) begin + data_121_V_load_reg_6044 <= data_121_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd122 == add_ln203_2_reg_5375))) begin + data_122_V_load_reg_6039 <= data_122_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd123 == add_ln203_2_reg_5375))) begin + data_123_V_load_reg_6034 <= data_123_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd124 == add_ln203_2_reg_5375))) begin + data_124_V_load_reg_6029 <= data_124_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd125 == add_ln203_2_reg_5375))) begin + data_125_V_load_reg_6024 <= data_125_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd126 == add_ln203_2_reg_5375))) begin + data_126_V_load_reg_6019 <= data_126_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd127 == add_ln203_2_reg_5375))) begin + data_127_V_load_reg_6654 <= data_127_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd12 == add_ln203_2_reg_5375))) begin + data_12_V_load_reg_6589 <= data_12_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd13 == add_ln203_2_reg_5375))) begin + data_13_V_load_reg_6584 <= data_13_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd14 == add_ln203_2_reg_5375))) begin + data_14_V_load_reg_6579 <= data_14_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd15 == add_ln203_2_reg_5375))) begin + data_15_V_load_reg_6574 <= data_15_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd16 == add_ln203_2_reg_5375))) begin + data_16_V_load_reg_6569 <= data_16_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd17 == add_ln203_2_reg_5375))) begin + data_17_V_load_reg_6564 <= data_17_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd18 == add_ln203_2_reg_5375))) begin + data_18_V_load_reg_6559 <= data_18_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd19 == add_ln203_2_reg_5375))) begin + data_19_V_load_reg_6554 <= data_19_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd1 == add_ln203_2_reg_5375))) begin + data_1_V_load_reg_6644 <= data_1_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd20 == add_ln203_2_reg_5375))) begin + data_20_V_load_reg_6549 <= data_20_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd21 == add_ln203_2_reg_5375))) begin + data_21_V_load_reg_6544 <= data_21_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd22 == add_ln203_2_reg_5375))) begin + data_22_V_load_reg_6539 <= data_22_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd23 == add_ln203_2_reg_5375))) begin + data_23_V_load_reg_6534 <= data_23_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd24 == add_ln203_2_reg_5375))) begin + data_24_V_load_reg_6529 <= data_24_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd25 == add_ln203_2_reg_5375))) begin + data_25_V_load_reg_6524 <= data_25_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd26 == add_ln203_2_reg_5375))) begin + data_26_V_load_reg_6519 <= data_26_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd27 == add_ln203_2_reg_5375))) begin + data_27_V_load_reg_6514 <= data_27_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd28 == add_ln203_2_reg_5375))) begin + data_28_V_load_reg_6509 <= data_28_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd29 == add_ln203_2_reg_5375))) begin + data_29_V_load_reg_6504 <= data_29_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd2 == add_ln203_2_reg_5375))) begin + data_2_V_load_reg_6639 <= data_2_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd30 == add_ln203_2_reg_5375))) begin + data_30_V_load_reg_6499 <= data_30_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd31 == add_ln203_2_reg_5375))) begin + data_31_V_load_reg_6494 <= data_31_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd32 == add_ln203_2_reg_5375))) begin + data_32_V_load_reg_6489 <= data_32_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd33 == add_ln203_2_reg_5375))) begin + data_33_V_load_reg_6484 <= data_33_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd34 == add_ln203_2_reg_5375))) begin + data_34_V_load_reg_6479 <= data_34_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd35 == add_ln203_2_reg_5375))) begin + data_35_V_load_reg_6474 <= data_35_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd36 == add_ln203_2_reg_5375))) begin + data_36_V_load_reg_6469 <= data_36_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd37 == add_ln203_2_reg_5375))) begin + data_37_V_load_reg_6464 <= data_37_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd38 == add_ln203_2_reg_5375))) begin + data_38_V_load_reg_6459 <= data_38_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd39 == add_ln203_2_reg_5375))) begin + data_39_V_load_reg_6454 <= data_39_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd3 == add_ln203_2_reg_5375))) begin + data_3_V_load_reg_6634 <= data_3_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd40 == add_ln203_2_reg_5375))) begin + data_40_V_load_reg_6449 <= data_40_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd41 == add_ln203_2_reg_5375))) begin + data_41_V_load_reg_6444 <= data_41_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd42 == add_ln203_2_reg_5375))) begin + data_42_V_load_reg_6439 <= data_42_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd43 == add_ln203_2_reg_5375))) begin + data_43_V_load_reg_6434 <= data_43_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd44 == add_ln203_2_reg_5375))) begin + data_44_V_load_reg_6429 <= data_44_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd45 == add_ln203_2_reg_5375))) begin + data_45_V_load_reg_6424 <= data_45_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd46 == add_ln203_2_reg_5375))) begin + data_46_V_load_reg_6419 <= data_46_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd47 == add_ln203_2_reg_5375))) begin + data_47_V_load_reg_6414 <= data_47_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd48 == add_ln203_2_reg_5375))) begin + data_48_V_load_reg_6409 <= data_48_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd49 == add_ln203_2_reg_5375))) begin + data_49_V_load_reg_6404 <= data_49_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd4 == add_ln203_2_reg_5375))) begin + data_4_V_load_reg_6629 <= data_4_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd50 == add_ln203_2_reg_5375))) begin + data_50_V_load_reg_6399 <= data_50_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd51 == add_ln203_2_reg_5375))) begin + data_51_V_load_reg_6394 <= data_51_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd52 == add_ln203_2_reg_5375))) begin + data_52_V_load_reg_6389 <= data_52_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd53 == add_ln203_2_reg_5375))) begin + data_53_V_load_reg_6384 <= data_53_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd54 == add_ln203_2_reg_5375))) begin + data_54_V_load_reg_6379 <= data_54_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd55 == add_ln203_2_reg_5375))) begin + data_55_V_load_reg_6374 <= data_55_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd56 == add_ln203_2_reg_5375))) begin + data_56_V_load_reg_6369 <= data_56_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd57 == add_ln203_2_reg_5375))) begin + data_57_V_load_reg_6364 <= data_57_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd58 == add_ln203_2_reg_5375))) begin + data_58_V_load_reg_6359 <= data_58_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd59 == add_ln203_2_reg_5375))) begin + data_59_V_load_reg_6354 <= data_59_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd5 == add_ln203_2_reg_5375))) begin + data_5_V_load_reg_6624 <= data_5_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd60 == add_ln203_2_reg_5375))) begin + data_60_V_load_reg_6349 <= data_60_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd61 == add_ln203_2_reg_5375))) begin + data_61_V_load_reg_6344 <= data_61_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd62 == add_ln203_2_reg_5375))) begin + data_62_V_load_reg_6339 <= data_62_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd63 == add_ln203_2_reg_5375))) begin + data_63_V_load_reg_6334 <= data_63_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd64 == add_ln203_2_reg_5375))) begin + data_64_V_load_reg_6329 <= data_64_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd65 == add_ln203_2_reg_5375))) begin + data_65_V_load_reg_6324 <= data_65_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd66 == add_ln203_2_reg_5375))) begin + data_66_V_load_reg_6319 <= data_66_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd67 == add_ln203_2_reg_5375))) begin + data_67_V_load_reg_6314 <= data_67_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd68 == add_ln203_2_reg_5375))) begin + data_68_V_load_reg_6309 <= data_68_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd69 == add_ln203_2_reg_5375))) begin + data_69_V_load_reg_6304 <= data_69_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd6 == add_ln203_2_reg_5375))) begin + data_6_V_load_reg_6619 <= data_6_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd70 == add_ln203_2_reg_5375))) begin + data_70_V_load_reg_6299 <= data_70_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd71 == add_ln203_2_reg_5375))) begin + data_71_V_load_reg_6294 <= data_71_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd72 == add_ln203_2_reg_5375))) begin + data_72_V_load_reg_6289 <= data_72_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd73 == add_ln203_2_reg_5375))) begin + data_73_V_load_reg_6284 <= data_73_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd74 == add_ln203_2_reg_5375))) begin + data_74_V_load_reg_6279 <= data_74_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd75 == add_ln203_2_reg_5375))) begin + data_75_V_load_reg_6274 <= data_75_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd76 == add_ln203_2_reg_5375))) begin + data_76_V_load_reg_6269 <= data_76_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd77 == add_ln203_2_reg_5375))) begin + data_77_V_load_reg_6264 <= data_77_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd78 == add_ln203_2_reg_5375))) begin + data_78_V_load_reg_6259 <= data_78_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd79 == add_ln203_2_reg_5375))) begin + data_79_V_load_reg_6254 <= data_79_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd7 == add_ln203_2_reg_5375))) begin + data_7_V_load_reg_6614 <= data_7_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd80 == add_ln203_2_reg_5375))) begin + data_80_V_load_reg_6249 <= data_80_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd81 == add_ln203_2_reg_5375))) begin + data_81_V_load_reg_6244 <= data_81_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd82 == add_ln203_2_reg_5375))) begin + data_82_V_load_reg_6239 <= data_82_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd83 == add_ln203_2_reg_5375))) begin + data_83_V_load_reg_6234 <= data_83_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd84 == add_ln203_2_reg_5375))) begin + data_84_V_load_reg_6229 <= data_84_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd85 == add_ln203_2_reg_5375))) begin + data_85_V_load_reg_6224 <= data_85_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd86 == add_ln203_2_reg_5375))) begin + data_86_V_load_reg_6219 <= data_86_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd87 == add_ln203_2_reg_5375))) begin + data_87_V_load_reg_6214 <= data_87_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd88 == add_ln203_2_reg_5375))) begin + data_88_V_load_reg_6209 <= data_88_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd89 == add_ln203_2_reg_5375))) begin + data_89_V_load_reg_6204 <= data_89_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd8 == add_ln203_2_reg_5375))) begin + data_8_V_load_reg_6609 <= data_8_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd90 == add_ln203_2_reg_5375))) begin + data_90_V_load_reg_6199 <= data_90_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd91 == add_ln203_2_reg_5375))) begin + data_91_V_load_reg_6194 <= data_91_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd92 == add_ln203_2_reg_5375))) begin + data_92_V_load_reg_6189 <= data_92_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd93 == add_ln203_2_reg_5375))) begin + data_93_V_load_reg_6184 <= data_93_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd94 == add_ln203_2_reg_5375))) begin + data_94_V_load_reg_6179 <= data_94_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd95 == add_ln203_2_reg_5375))) begin + data_95_V_load_reg_6174 <= data_95_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd96 == add_ln203_2_reg_5375))) begin + data_96_V_load_reg_6169 <= data_96_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd97 == add_ln203_2_reg_5375))) begin + data_97_V_load_reg_6164 <= data_97_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd98 == add_ln203_2_reg_5375))) begin + data_98_V_load_reg_6159 <= data_98_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd99 == add_ln203_2_reg_5375))) begin + data_99_V_load_reg_6154 <= data_99_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (7'd9 == add_ln203_2_reg_5375))) begin + data_9_V_load_reg_6604 <= data_9_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + ff_reg_5304 <= ff_fu_4684_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln13_fu_5110_p2 == 1'd0) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + i_reg_6682 <= i_fu_5121_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state6 == ap_CS_fsm) & (icmp_ln220_fu_4878_p2 == 1'd0) & (icmp_ln221_reg_5338 == 1'd0))) begin + icmp_ln221_2_reg_5366 <= icmp_ln221_2_fu_4896_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state5 == ap_CS_fsm) & (icmp_ln218_fu_4778_p2 == 1'd0))) begin + icmp_ln221_reg_5338 <= icmp_ln221_fu_4796_p2; + or_ln1_reg_5348[2 : 0] <= or_ln1_fu_4848_p3[2 : 0]; +or_ln1_reg_5348[12 : 4] <= or_ln1_fu_4848_p3[12 : 4]; + or_ln225_1_reg_5353[2 : 0] <= or_ln225_1_fu_4866_p3[2 : 0]; +or_ln225_1_reg_5353[6 : 4] <= or_ln225_1_fu_4866_p3[6 : 4]; + shl_ln223_reg_5342[1] <= shl_ln223_fu_4802_p2[1]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state5 == ap_CS_fsm)) begin + kk_reg_5333 <= kk_fu_4784_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + ll_reg_5361 <= ll_fu_4884_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln211_fu_4690_p2 == 1'd1))) begin + or_ln_reg_5312 <= or_ln_fu_4736_p3; + trunc_ln_reg_5317 <= trunc_ln_fu_4754_p3; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0)) | ((ap_ST_fsm_state2 == ap_CS_fsm) & (icmp_ln209_fu_4678_p2 == 1'd1)))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2 == ap_CS_fsm) & (icmp_ln209_fu_4678_p2 == 1'd1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_0_V_ce0 = 1'b1; + end else begin + data_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_100_V_ce0 = 1'b1; + end else begin + data_100_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_101_V_ce0 = 1'b1; + end else begin + data_101_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_102_V_ce0 = 1'b1; + end else begin + data_102_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_103_V_ce0 = 1'b1; + end else begin + data_103_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_104_V_ce0 = 1'b1; + end else begin + data_104_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_105_V_ce0 = 1'b1; + end else begin + data_105_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_106_V_ce0 = 1'b1; + end else begin + data_106_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_107_V_ce0 = 1'b1; + end else begin + data_107_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_108_V_ce0 = 1'b1; + end else begin + data_108_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_109_V_ce0 = 1'b1; + end else begin + data_109_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_10_V_ce0 = 1'b1; + end else begin + data_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_110_V_ce0 = 1'b1; + end else begin + data_110_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_111_V_ce0 = 1'b1; + end else begin + data_111_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_112_V_ce0 = 1'b1; + end else begin + data_112_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_113_V_ce0 = 1'b1; + end else begin + data_113_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_114_V_ce0 = 1'b1; + end else begin + data_114_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_115_V_ce0 = 1'b1; + end else begin + data_115_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_116_V_ce0 = 1'b1; + end else begin + data_116_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_117_V_ce0 = 1'b1; + end else begin + data_117_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_118_V_ce0 = 1'b1; + end else begin + data_118_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_119_V_ce0 = 1'b1; + end else begin + data_119_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_11_V_ce0 = 1'b1; + end else begin + data_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_120_V_ce0 = 1'b1; + end else begin + data_120_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_121_V_ce0 = 1'b1; + end else begin + data_121_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_122_V_ce0 = 1'b1; + end else begin + data_122_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_123_V_ce0 = 1'b1; + end else begin + data_123_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_124_V_ce0 = 1'b1; + end else begin + data_124_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_125_V_ce0 = 1'b1; + end else begin + data_125_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_126_V_ce0 = 1'b1; + end else begin + data_126_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_127_V_ce0 = 1'b1; + end else begin + data_127_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_12_V_ce0 = 1'b1; + end else begin + data_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_13_V_ce0 = 1'b1; + end else begin + data_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_14_V_ce0 = 1'b1; + end else begin + data_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_15_V_ce0 = 1'b1; + end else begin + data_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_16_V_ce0 = 1'b1; + end else begin + data_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_17_V_ce0 = 1'b1; + end else begin + data_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_18_V_ce0 = 1'b1; + end else begin + data_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_19_V_ce0 = 1'b1; + end else begin + data_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_1_V_ce0 = 1'b1; + end else begin + data_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_20_V_ce0 = 1'b1; + end else begin + data_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_21_V_ce0 = 1'b1; + end else begin + data_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_22_V_ce0 = 1'b1; + end else begin + data_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_23_V_ce0 = 1'b1; + end else begin + data_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_24_V_ce0 = 1'b1; + end else begin + data_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_25_V_ce0 = 1'b1; + end else begin + data_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_26_V_ce0 = 1'b1; + end else begin + data_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_27_V_ce0 = 1'b1; + end else begin + data_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_28_V_ce0 = 1'b1; + end else begin + data_28_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_29_V_ce0 = 1'b1; + end else begin + data_29_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_2_V_ce0 = 1'b1; + end else begin + data_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_30_V_ce0 = 1'b1; + end else begin + data_30_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_31_V_ce0 = 1'b1; + end else begin + data_31_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_32_V_ce0 = 1'b1; + end else begin + data_32_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_33_V_ce0 = 1'b1; + end else begin + data_33_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_34_V_ce0 = 1'b1; + end else begin + data_34_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_35_V_ce0 = 1'b1; + end else begin + data_35_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_36_V_ce0 = 1'b1; + end else begin + data_36_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_37_V_ce0 = 1'b1; + end else begin + data_37_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_38_V_ce0 = 1'b1; + end else begin + data_38_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_39_V_ce0 = 1'b1; + end else begin + data_39_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_3_V_ce0 = 1'b1; + end else begin + data_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_40_V_ce0 = 1'b1; + end else begin + data_40_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_41_V_ce0 = 1'b1; + end else begin + data_41_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_42_V_ce0 = 1'b1; + end else begin + data_42_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_43_V_ce0 = 1'b1; + end else begin + data_43_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_44_V_ce0 = 1'b1; + end else begin + data_44_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_45_V_ce0 = 1'b1; + end else begin + data_45_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_46_V_ce0 = 1'b1; + end else begin + data_46_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_47_V_ce0 = 1'b1; + end else begin + data_47_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_48_V_ce0 = 1'b1; + end else begin + data_48_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_49_V_ce0 = 1'b1; + end else begin + data_49_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_4_V_ce0 = 1'b1; + end else begin + data_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_50_V_ce0 = 1'b1; + end else begin + data_50_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_51_V_ce0 = 1'b1; + end else begin + data_51_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_52_V_ce0 = 1'b1; + end else begin + data_52_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_53_V_ce0 = 1'b1; + end else begin + data_53_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_54_V_ce0 = 1'b1; + end else begin + data_54_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_55_V_ce0 = 1'b1; + end else begin + data_55_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_56_V_ce0 = 1'b1; + end else begin + data_56_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_57_V_ce0 = 1'b1; + end else begin + data_57_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_58_V_ce0 = 1'b1; + end else begin + data_58_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_59_V_ce0 = 1'b1; + end else begin + data_59_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_5_V_ce0 = 1'b1; + end else begin + data_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_60_V_ce0 = 1'b1; + end else begin + data_60_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_61_V_ce0 = 1'b1; + end else begin + data_61_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_62_V_ce0 = 1'b1; + end else begin + data_62_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_63_V_ce0 = 1'b1; + end else begin + data_63_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_64_V_ce0 = 1'b1; + end else begin + data_64_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_65_V_ce0 = 1'b1; + end else begin + data_65_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_66_V_ce0 = 1'b1; + end else begin + data_66_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_67_V_ce0 = 1'b1; + end else begin + data_67_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_68_V_ce0 = 1'b1; + end else begin + data_68_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_69_V_ce0 = 1'b1; + end else begin + data_69_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_6_V_ce0 = 1'b1; + end else begin + data_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_70_V_ce0 = 1'b1; + end else begin + data_70_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_71_V_ce0 = 1'b1; + end else begin + data_71_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_72_V_ce0 = 1'b1; + end else begin + data_72_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_73_V_ce0 = 1'b1; + end else begin + data_73_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_74_V_ce0 = 1'b1; + end else begin + data_74_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_75_V_ce0 = 1'b1; + end else begin + data_75_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_76_V_ce0 = 1'b1; + end else begin + data_76_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_77_V_ce0 = 1'b1; + end else begin + data_77_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_78_V_ce0 = 1'b1; + end else begin + data_78_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_79_V_ce0 = 1'b1; + end else begin + data_79_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_7_V_ce0 = 1'b1; + end else begin + data_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_80_V_ce0 = 1'b1; + end else begin + data_80_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_81_V_ce0 = 1'b1; + end else begin + data_81_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_82_V_ce0 = 1'b1; + end else begin + data_82_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_83_V_ce0 = 1'b1; + end else begin + data_83_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_84_V_ce0 = 1'b1; + end else begin + data_84_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_85_V_ce0 = 1'b1; + end else begin + data_85_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_86_V_ce0 = 1'b1; + end else begin + data_86_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_87_V_ce0 = 1'b1; + end else begin + data_87_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_88_V_ce0 = 1'b1; + end else begin + data_88_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_89_V_ce0 = 1'b1; + end else begin + data_89_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_8_V_ce0 = 1'b1; + end else begin + data_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_90_V_ce0 = 1'b1; + end else begin + data_90_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_91_V_ce0 = 1'b1; + end else begin + data_91_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_92_V_ce0 = 1'b1; + end else begin + data_92_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_93_V_ce0 = 1'b1; + end else begin + data_93_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_94_V_ce0 = 1'b1; + end else begin + data_94_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_95_V_ce0 = 1'b1; + end else begin + data_95_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_96_V_ce0 = 1'b1; + end else begin + data_96_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_97_V_ce0 = 1'b1; + end else begin + data_97_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_98_V_ce0 = 1'b1; + end else begin + data_98_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_99_V_ce0 = 1'b1; + end else begin + data_99_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + data_9_V_ce0 = 1'b1; + end else begin + data_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + pool_V_address0 = zext_ln14_fu_5116_p1; + end else if ((ap_ST_fsm_state9 == ap_CS_fsm)) begin + pool_V_address0 = zext_ln225_reg_5370; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + pool_V_address0 = zext_ln223_fu_5084_p1; + end else if ((ap_ST_fsm_state5 == ap_CS_fsm)) begin + pool_V_address0 = 64'd0; + end else begin + pool_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state6 == ap_CS_fsm) | (ap_ST_fsm_state5 == ap_CS_fsm) | (ap_ST_fsm_state11 == ap_CS_fsm) | (ap_ST_fsm_state9 == ap_CS_fsm))) begin + pool_V_ce0 = 1'b1; + end else begin + pool_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state9 == ap_CS_fsm)) begin + pool_V_d0 = phi_ln203_reg_4267; + end else if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + pool_V_d0 = 8'd128; + end else begin + pool_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((icmp_ln221_2_reg_5366 == 1'd0) & (icmp_ln221_reg_5338 == 1'd0) & (ap_ST_fsm_state9 == ap_CS_fsm)) | ((ap_ST_fsm_state6 == ap_CS_fsm) & (((icmp_ln220_fu_4878_p2 == 1'd0) & (icmp_ln221_reg_5338 == 1'd1)) | ((icmp_ln220_fu_4878_p2 == 1'd0) & (icmp_ln221_2_fu_4896_p2 == 1'd1)))))) begin + pool_V_we0 = 1'b1; + end else begin + pool_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_0_V_ce0 = 1'b1; + end else begin + res_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd0 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_0_V_we0 = 1'b1; + end else begin + res_0_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_100_V_ce0 = 1'b1; + end else begin + res_100_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd100 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_100_V_we0 = 1'b1; + end else begin + res_100_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_101_V_ce0 = 1'b1; + end else begin + res_101_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd101 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_101_V_we0 = 1'b1; + end else begin + res_101_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_102_V_ce0 = 1'b1; + end else begin + res_102_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd102 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_102_V_we0 = 1'b1; + end else begin + res_102_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_103_V_ce0 = 1'b1; + end else begin + res_103_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd103 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_103_V_we0 = 1'b1; + end else begin + res_103_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_104_V_ce0 = 1'b1; + end else begin + res_104_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd104 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_104_V_we0 = 1'b1; + end else begin + res_104_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_105_V_ce0 = 1'b1; + end else begin + res_105_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd105 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_105_V_we0 = 1'b1; + end else begin + res_105_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_106_V_ce0 = 1'b1; + end else begin + res_106_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd106 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_106_V_we0 = 1'b1; + end else begin + res_106_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_107_V_ce0 = 1'b1; + end else begin + res_107_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd107 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_107_V_we0 = 1'b1; + end else begin + res_107_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_108_V_ce0 = 1'b1; + end else begin + res_108_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd108 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_108_V_we0 = 1'b1; + end else begin + res_108_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_109_V_ce0 = 1'b1; + end else begin + res_109_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd109 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_109_V_we0 = 1'b1; + end else begin + res_109_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_10_V_ce0 = 1'b1; + end else begin + res_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd10 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_10_V_we0 = 1'b1; + end else begin + res_10_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_110_V_ce0 = 1'b1; + end else begin + res_110_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd110 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_110_V_we0 = 1'b1; + end else begin + res_110_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_111_V_ce0 = 1'b1; + end else begin + res_111_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd111 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_111_V_we0 = 1'b1; + end else begin + res_111_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_112_V_ce0 = 1'b1; + end else begin + res_112_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd112 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_112_V_we0 = 1'b1; + end else begin + res_112_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_113_V_ce0 = 1'b1; + end else begin + res_113_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd113 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_113_V_we0 = 1'b1; + end else begin + res_113_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_114_V_ce0 = 1'b1; + end else begin + res_114_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd114 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_114_V_we0 = 1'b1; + end else begin + res_114_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_115_V_ce0 = 1'b1; + end else begin + res_115_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd115 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_115_V_we0 = 1'b1; + end else begin + res_115_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_116_V_ce0 = 1'b1; + end else begin + res_116_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd116 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_116_V_we0 = 1'b1; + end else begin + res_116_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_117_V_ce0 = 1'b1; + end else begin + res_117_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd117 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_117_V_we0 = 1'b1; + end else begin + res_117_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_118_V_ce0 = 1'b1; + end else begin + res_118_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd118 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_118_V_we0 = 1'b1; + end else begin + res_118_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_119_V_ce0 = 1'b1; + end else begin + res_119_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd119 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_119_V_we0 = 1'b1; + end else begin + res_119_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_11_V_ce0 = 1'b1; + end else begin + res_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd11 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_11_V_we0 = 1'b1; + end else begin + res_11_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_120_V_ce0 = 1'b1; + end else begin + res_120_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd120 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_120_V_we0 = 1'b1; + end else begin + res_120_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_121_V_ce0 = 1'b1; + end else begin + res_121_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd121 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_121_V_we0 = 1'b1; + end else begin + res_121_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_122_V_ce0 = 1'b1; + end else begin + res_122_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd122 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_122_V_we0 = 1'b1; + end else begin + res_122_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_123_V_ce0 = 1'b1; + end else begin + res_123_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd123 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_123_V_we0 = 1'b1; + end else begin + res_123_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_124_V_ce0 = 1'b1; + end else begin + res_124_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd124 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_124_V_we0 = 1'b1; + end else begin + res_124_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_125_V_ce0 = 1'b1; + end else begin + res_125_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd125 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_125_V_we0 = 1'b1; + end else begin + res_125_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_126_V_ce0 = 1'b1; + end else begin + res_126_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd126 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_126_V_we0 = 1'b1; + end else begin + res_126_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_127_V_ce0 = 1'b1; + end else begin + res_127_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd127 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_127_V_we0 = 1'b1; + end else begin + res_127_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_12_V_ce0 = 1'b1; + end else begin + res_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd12 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_12_V_we0 = 1'b1; + end else begin + res_12_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_13_V_ce0 = 1'b1; + end else begin + res_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd13 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_13_V_we0 = 1'b1; + end else begin + res_13_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_14_V_ce0 = 1'b1; + end else begin + res_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd14 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_14_V_we0 = 1'b1; + end else begin + res_14_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_15_V_ce0 = 1'b1; + end else begin + res_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd15 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_15_V_we0 = 1'b1; + end else begin + res_15_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_16_V_ce0 = 1'b1; + end else begin + res_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd16 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_16_V_we0 = 1'b1; + end else begin + res_16_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_17_V_ce0 = 1'b1; + end else begin + res_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd17 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_17_V_we0 = 1'b1; + end else begin + res_17_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_18_V_ce0 = 1'b1; + end else begin + res_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd18 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_18_V_we0 = 1'b1; + end else begin + res_18_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_19_V_ce0 = 1'b1; + end else begin + res_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd19 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_19_V_we0 = 1'b1; + end else begin + res_19_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_1_V_ce0 = 1'b1; + end else begin + res_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd1 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_1_V_we0 = 1'b1; + end else begin + res_1_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_20_V_ce0 = 1'b1; + end else begin + res_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd20 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_20_V_we0 = 1'b1; + end else begin + res_20_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_21_V_ce0 = 1'b1; + end else begin + res_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd21 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_21_V_we0 = 1'b1; + end else begin + res_21_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_22_V_ce0 = 1'b1; + end else begin + res_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd22 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_22_V_we0 = 1'b1; + end else begin + res_22_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_23_V_ce0 = 1'b1; + end else begin + res_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd23 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_23_V_we0 = 1'b1; + end else begin + res_23_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_24_V_ce0 = 1'b1; + end else begin + res_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd24 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_24_V_we0 = 1'b1; + end else begin + res_24_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_25_V_ce0 = 1'b1; + end else begin + res_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd25 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_25_V_we0 = 1'b1; + end else begin + res_25_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_26_V_ce0 = 1'b1; + end else begin + res_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd26 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_26_V_we0 = 1'b1; + end else begin + res_26_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_27_V_ce0 = 1'b1; + end else begin + res_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd27 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_27_V_we0 = 1'b1; + end else begin + res_27_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_28_V_ce0 = 1'b1; + end else begin + res_28_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd28 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_28_V_we0 = 1'b1; + end else begin + res_28_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_29_V_ce0 = 1'b1; + end else begin + res_29_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd29 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_29_V_we0 = 1'b1; + end else begin + res_29_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_2_V_ce0 = 1'b1; + end else begin + res_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd2 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_2_V_we0 = 1'b1; + end else begin + res_2_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_30_V_ce0 = 1'b1; + end else begin + res_30_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd30 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_30_V_we0 = 1'b1; + end else begin + res_30_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_31_V_ce0 = 1'b1; + end else begin + res_31_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd31 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_31_V_we0 = 1'b1; + end else begin + res_31_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_32_V_ce0 = 1'b1; + end else begin + res_32_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd32 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_32_V_we0 = 1'b1; + end else begin + res_32_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_33_V_ce0 = 1'b1; + end else begin + res_33_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd33 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_33_V_we0 = 1'b1; + end else begin + res_33_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_34_V_ce0 = 1'b1; + end else begin + res_34_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd34 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_34_V_we0 = 1'b1; + end else begin + res_34_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_35_V_ce0 = 1'b1; + end else begin + res_35_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd35 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_35_V_we0 = 1'b1; + end else begin + res_35_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_36_V_ce0 = 1'b1; + end else begin + res_36_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd36 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_36_V_we0 = 1'b1; + end else begin + res_36_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_37_V_ce0 = 1'b1; + end else begin + res_37_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd37 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_37_V_we0 = 1'b1; + end else begin + res_37_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_38_V_ce0 = 1'b1; + end else begin + res_38_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd38 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_38_V_we0 = 1'b1; + end else begin + res_38_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_39_V_ce0 = 1'b1; + end else begin + res_39_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd39 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_39_V_we0 = 1'b1; + end else begin + res_39_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_3_V_ce0 = 1'b1; + end else begin + res_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd3 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_3_V_we0 = 1'b1; + end else begin + res_3_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_40_V_ce0 = 1'b1; + end else begin + res_40_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd40 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_40_V_we0 = 1'b1; + end else begin + res_40_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_41_V_ce0 = 1'b1; + end else begin + res_41_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd41 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_41_V_we0 = 1'b1; + end else begin + res_41_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_42_V_ce0 = 1'b1; + end else begin + res_42_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd42 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_42_V_we0 = 1'b1; + end else begin + res_42_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_43_V_ce0 = 1'b1; + end else begin + res_43_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd43 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_43_V_we0 = 1'b1; + end else begin + res_43_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_44_V_ce0 = 1'b1; + end else begin + res_44_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd44 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_44_V_we0 = 1'b1; + end else begin + res_44_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_45_V_ce0 = 1'b1; + end else begin + res_45_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd45 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_45_V_we0 = 1'b1; + end else begin + res_45_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_46_V_ce0 = 1'b1; + end else begin + res_46_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd46 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_46_V_we0 = 1'b1; + end else begin + res_46_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_47_V_ce0 = 1'b1; + end else begin + res_47_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd47 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_47_V_we0 = 1'b1; + end else begin + res_47_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_48_V_ce0 = 1'b1; + end else begin + res_48_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd48 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_48_V_we0 = 1'b1; + end else begin + res_48_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_49_V_ce0 = 1'b1; + end else begin + res_49_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd49 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_49_V_we0 = 1'b1; + end else begin + res_49_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_4_V_ce0 = 1'b1; + end else begin + res_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd4 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_4_V_we0 = 1'b1; + end else begin + res_4_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_50_V_ce0 = 1'b1; + end else begin + res_50_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd50 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_50_V_we0 = 1'b1; + end else begin + res_50_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_51_V_ce0 = 1'b1; + end else begin + res_51_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd51 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_51_V_we0 = 1'b1; + end else begin + res_51_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_52_V_ce0 = 1'b1; + end else begin + res_52_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd52 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_52_V_we0 = 1'b1; + end else begin + res_52_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_53_V_ce0 = 1'b1; + end else begin + res_53_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd53 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_53_V_we0 = 1'b1; + end else begin + res_53_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_54_V_ce0 = 1'b1; + end else begin + res_54_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd54 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_54_V_we0 = 1'b1; + end else begin + res_54_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_55_V_ce0 = 1'b1; + end else begin + res_55_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd55 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_55_V_we0 = 1'b1; + end else begin + res_55_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_56_V_ce0 = 1'b1; + end else begin + res_56_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd56 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_56_V_we0 = 1'b1; + end else begin + res_56_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_57_V_ce0 = 1'b1; + end else begin + res_57_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd57 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_57_V_we0 = 1'b1; + end else begin + res_57_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_58_V_ce0 = 1'b1; + end else begin + res_58_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd58 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_58_V_we0 = 1'b1; + end else begin + res_58_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_59_V_ce0 = 1'b1; + end else begin + res_59_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd59 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_59_V_we0 = 1'b1; + end else begin + res_59_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_5_V_ce0 = 1'b1; + end else begin + res_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd5 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_5_V_we0 = 1'b1; + end else begin + res_5_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_60_V_ce0 = 1'b1; + end else begin + res_60_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd60 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_60_V_we0 = 1'b1; + end else begin + res_60_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_61_V_ce0 = 1'b1; + end else begin + res_61_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd61 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_61_V_we0 = 1'b1; + end else begin + res_61_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_62_V_ce0 = 1'b1; + end else begin + res_62_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd62 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_62_V_we0 = 1'b1; + end else begin + res_62_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_63_V_ce0 = 1'b1; + end else begin + res_63_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd63 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_63_V_we0 = 1'b1; + end else begin + res_63_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_64_V_ce0 = 1'b1; + end else begin + res_64_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd64 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_64_V_we0 = 1'b1; + end else begin + res_64_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_65_V_ce0 = 1'b1; + end else begin + res_65_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd65 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_65_V_we0 = 1'b1; + end else begin + res_65_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_66_V_ce0 = 1'b1; + end else begin + res_66_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd66 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_66_V_we0 = 1'b1; + end else begin + res_66_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_67_V_ce0 = 1'b1; + end else begin + res_67_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd67 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_67_V_we0 = 1'b1; + end else begin + res_67_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_68_V_ce0 = 1'b1; + end else begin + res_68_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd68 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_68_V_we0 = 1'b1; + end else begin + res_68_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_69_V_ce0 = 1'b1; + end else begin + res_69_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd69 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_69_V_we0 = 1'b1; + end else begin + res_69_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_6_V_ce0 = 1'b1; + end else begin + res_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd6 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_6_V_we0 = 1'b1; + end else begin + res_6_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_70_V_ce0 = 1'b1; + end else begin + res_70_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd70 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_70_V_we0 = 1'b1; + end else begin + res_70_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_71_V_ce0 = 1'b1; + end else begin + res_71_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd71 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_71_V_we0 = 1'b1; + end else begin + res_71_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_72_V_ce0 = 1'b1; + end else begin + res_72_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd72 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_72_V_we0 = 1'b1; + end else begin + res_72_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_73_V_ce0 = 1'b1; + end else begin + res_73_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd73 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_73_V_we0 = 1'b1; + end else begin + res_73_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_74_V_ce0 = 1'b1; + end else begin + res_74_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd74 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_74_V_we0 = 1'b1; + end else begin + res_74_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_75_V_ce0 = 1'b1; + end else begin + res_75_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd75 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_75_V_we0 = 1'b1; + end else begin + res_75_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_76_V_ce0 = 1'b1; + end else begin + res_76_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd76 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_76_V_we0 = 1'b1; + end else begin + res_76_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_77_V_ce0 = 1'b1; + end else begin + res_77_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd77 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_77_V_we0 = 1'b1; + end else begin + res_77_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_78_V_ce0 = 1'b1; + end else begin + res_78_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd78 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_78_V_we0 = 1'b1; + end else begin + res_78_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_79_V_ce0 = 1'b1; + end else begin + res_79_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd79 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_79_V_we0 = 1'b1; + end else begin + res_79_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_7_V_ce0 = 1'b1; + end else begin + res_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd7 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_7_V_we0 = 1'b1; + end else begin + res_7_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_80_V_ce0 = 1'b1; + end else begin + res_80_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd80 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_80_V_we0 = 1'b1; + end else begin + res_80_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_81_V_ce0 = 1'b1; + end else begin + res_81_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd81 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_81_V_we0 = 1'b1; + end else begin + res_81_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_82_V_ce0 = 1'b1; + end else begin + res_82_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd82 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_82_V_we0 = 1'b1; + end else begin + res_82_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_83_V_ce0 = 1'b1; + end else begin + res_83_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd83 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_83_V_we0 = 1'b1; + end else begin + res_83_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_84_V_ce0 = 1'b1; + end else begin + res_84_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd84 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_84_V_we0 = 1'b1; + end else begin + res_84_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_85_V_ce0 = 1'b1; + end else begin + res_85_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd85 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_85_V_we0 = 1'b1; + end else begin + res_85_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_86_V_ce0 = 1'b1; + end else begin + res_86_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd86 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_86_V_we0 = 1'b1; + end else begin + res_86_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_87_V_ce0 = 1'b1; + end else begin + res_87_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd87 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_87_V_we0 = 1'b1; + end else begin + res_87_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_88_V_ce0 = 1'b1; + end else begin + res_88_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd88 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_88_V_we0 = 1'b1; + end else begin + res_88_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_89_V_ce0 = 1'b1; + end else begin + res_89_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd89 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_89_V_we0 = 1'b1; + end else begin + res_89_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_8_V_ce0 = 1'b1; + end else begin + res_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd8 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_8_V_we0 = 1'b1; + end else begin + res_8_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_90_V_ce0 = 1'b1; + end else begin + res_90_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd90 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_90_V_we0 = 1'b1; + end else begin + res_90_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_91_V_ce0 = 1'b1; + end else begin + res_91_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd91 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_91_V_we0 = 1'b1; + end else begin + res_91_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_92_V_ce0 = 1'b1; + end else begin + res_92_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd92 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_92_V_we0 = 1'b1; + end else begin + res_92_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_93_V_ce0 = 1'b1; + end else begin + res_93_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd93 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_93_V_we0 = 1'b1; + end else begin + res_93_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_94_V_ce0 = 1'b1; + end else begin + res_94_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd94 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_94_V_we0 = 1'b1; + end else begin + res_94_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_95_V_ce0 = 1'b1; + end else begin + res_95_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd95 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_95_V_we0 = 1'b1; + end else begin + res_95_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_96_V_ce0 = 1'b1; + end else begin + res_96_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd96 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_96_V_we0 = 1'b1; + end else begin + res_96_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_97_V_ce0 = 1'b1; + end else begin + res_97_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd97 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_97_V_we0 = 1'b1; + end else begin + res_97_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_98_V_ce0 = 1'b1; + end else begin + res_98_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd98 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_98_V_we0 = 1'b1; + end else begin + res_98_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_99_V_ce0 = 1'b1; + end else begin + res_99_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd99 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_99_V_we0 = 1'b1; + end else begin + res_99_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + res_9_V_ce0 = 1'b1; + end else begin + res_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd9 == add_ln203_fu_5127_p2) & (icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + res_9_V_we0 = 1'b1; + end else begin + res_9_V_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((ap_ST_fsm_state2 == ap_CS_fsm) & (icmp_ln209_fu_4678_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln211_fu_4690_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + ap_ST_fsm_state4 : begin + if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln213_fu_4762_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state3; + end else begin + ap_NS_fsm = ap_ST_fsm_state5; + end + end + ap_ST_fsm_state5 : begin + if (((ap_ST_fsm_state5 == ap_CS_fsm) & (icmp_ln218_fu_4778_p2 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state6; + end else begin + ap_NS_fsm = ap_ST_fsm_state10; + end + end + ap_ST_fsm_state6 : begin + if (((ap_ST_fsm_state6 == ap_CS_fsm) & (icmp_ln220_fu_4878_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state5; + end else if (((ap_ST_fsm_state6 == ap_CS_fsm) & (((icmp_ln220_fu_4878_p2 == 1'd0) & (icmp_ln221_reg_5338 == 1'd1)) | ((icmp_ln220_fu_4878_p2 == 1'd0) & (icmp_ln221_2_fu_4896_p2 == 1'd1))))) begin + ap_NS_fsm = ap_ST_fsm_state9; + end else begin + ap_NS_fsm = ap_ST_fsm_state7; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + if (((icmp_ln13_fu_5110_p2 == 1'd1) & (ap_ST_fsm_state11 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_state12; + end + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +assign add_ln203_2_fu_4928_p2 = (or_ln225_1_reg_5353 + shl_ln225_3_fu_4911_p3); + +assign add_ln203_fu_5127_p2 = (trunc_ln_reg_5317 + zext_ln233_5_reg_6659); + +assign add_ln221_2_fu_4890_p2 = (jj_0_reg_4233 + zext_ln220_fu_4874_p1); + +assign add_ln221_fu_4790_p2 = (ii_0_reg_4221 + zext_ln218_fu_4774_p1); + +assign add_ln223_fu_5079_p2 = (ll_0_reg_4256 + shl_ln223_reg_5342); + +assign add_ln225_3_fu_4923_p2 = (zext_ln225_6_fu_4919_p1 + or_ln1_reg_5348); + +assign add_ln225_fu_4902_p2 = (shl_ln223_reg_5342 + ll_0_reg_4256); + +assign add_ln233_fu_5105_p2 = (zext_ln233_4_fu_5097_p1 + or_ln_reg_5312); + +assign data_0_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_100_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_101_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_102_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_103_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_104_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_105_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_106_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_107_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_108_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_109_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_10_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_110_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_111_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_112_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_113_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_114_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_115_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_116_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_117_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_118_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_119_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_11_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_120_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_121_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_122_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_123_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_124_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_125_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_126_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_127_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_12_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_13_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_14_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_15_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_16_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_17_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_18_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_19_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_1_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_20_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_21_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_22_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_23_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_24_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_25_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_26_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_27_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_28_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_29_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_2_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_30_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_31_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_32_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_33_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_34_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_35_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_36_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_37_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_38_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_39_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_3_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_40_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_41_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_42_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_43_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_44_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_45_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_46_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_47_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_48_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_49_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_4_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_50_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_51_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_52_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_53_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_54_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_55_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_56_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_57_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_58_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_59_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_5_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_60_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_61_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_62_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_63_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_64_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_65_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_66_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_67_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_68_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_69_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_6_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_70_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_71_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_72_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_73_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_74_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_75_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_76_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_77_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_78_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_79_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_7_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_80_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_81_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_82_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_83_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_84_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_85_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_86_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_87_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_88_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_89_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_8_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_90_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_91_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_92_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_93_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_94_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_95_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_96_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_97_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_98_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_99_V_address0 = zext_ln203_2_fu_4947_p1; + +assign data_9_V_address0 = zext_ln203_2_fu_4947_p1; + +assign ff_fu_4684_p2 = (ff_0_reg_4209 + 3'd1); + +assign i_fu_5121_p2 = (i_0_i_i_reg_4667 + 3'd1); + +assign icmp_ln13_fu_5110_p2 = ((i_0_i_i_reg_4667 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln1494_fu_5276_p2 = (((pool_V_q0) > (agg_result_V_0_i_i_reg_4529)) ? 1'b1 : 1'b0); + +assign icmp_ln209_fu_4678_p2 = ((ff_0_reg_4209 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln211_fu_4690_p2 = ((ii_0_reg_4221 < 5'd28) ? 1'b1 : 1'b0); + +assign icmp_ln213_fu_4762_p2 = ((jj_0_reg_4233 < 5'd28) ? 1'b1 : 1'b0); + +assign icmp_ln218_fu_4778_p2 = ((kk_0_reg_4245 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln220_fu_4878_p2 = ((ll_0_reg_4256 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln221_2_fu_4896_p2 = ((add_ln221_2_fu_4890_p2 > 5'd27) ? 1'b1 : 1'b0); + +assign icmp_ln221_fu_4796_p2 = ((add_ln221_fu_4790_p2 > 5'd27) ? 1'b1 : 1'b0); + +assign ii_fu_4768_p2 = (ii_0_reg_4221 + 5'd2); + +assign jj_fu_5290_p2 = (jj_0_reg_4233 + 5'd2); + +assign kk_fu_4784_p2 = (kk_0_reg_4245 + 2'd1); + +assign ll_fu_4884_p2 = (ll_0_reg_4256 + 2'd1); + +assign or_ln1_fu_4848_p3 = {{tmp_2_fu_4838_p4}, {ff_0_reg_4209}}; + +assign or_ln225_1_fu_4866_p3 = {{tmp_3_fu_4856_p4}, {ff_0_reg_4209}}; + +assign or_ln_fu_4736_p3 = {{tmp_fu_4726_p4}, {ff_0_reg_4209}}; + +assign res_0_V_address0 = zext_ln203_fu_5144_p1; + +assign res_0_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_100_V_address0 = zext_ln203_fu_5144_p1; + +assign res_100_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_101_V_address0 = zext_ln203_fu_5144_p1; + +assign res_101_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_102_V_address0 = zext_ln203_fu_5144_p1; + +assign res_102_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_103_V_address0 = zext_ln203_fu_5144_p1; + +assign res_103_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_104_V_address0 = zext_ln203_fu_5144_p1; + +assign res_104_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_105_V_address0 = zext_ln203_fu_5144_p1; + +assign res_105_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_106_V_address0 = zext_ln203_fu_5144_p1; + +assign res_106_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_107_V_address0 = zext_ln203_fu_5144_p1; + +assign res_107_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_108_V_address0 = zext_ln203_fu_5144_p1; + +assign res_108_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_109_V_address0 = zext_ln203_fu_5144_p1; + +assign res_109_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_10_V_address0 = zext_ln203_fu_5144_p1; + +assign res_10_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_110_V_address0 = zext_ln203_fu_5144_p1; + +assign res_110_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_111_V_address0 = zext_ln203_fu_5144_p1; + +assign res_111_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_112_V_address0 = zext_ln203_fu_5144_p1; + +assign res_112_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_113_V_address0 = zext_ln203_fu_5144_p1; + +assign res_113_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_114_V_address0 = zext_ln203_fu_5144_p1; + +assign res_114_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_115_V_address0 = zext_ln203_fu_5144_p1; + +assign res_115_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_116_V_address0 = zext_ln203_fu_5144_p1; + +assign res_116_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_117_V_address0 = zext_ln203_fu_5144_p1; + +assign res_117_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_118_V_address0 = zext_ln203_fu_5144_p1; + +assign res_118_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_119_V_address0 = zext_ln203_fu_5144_p1; + +assign res_119_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_11_V_address0 = zext_ln203_fu_5144_p1; + +assign res_11_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_120_V_address0 = zext_ln203_fu_5144_p1; + +assign res_120_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_121_V_address0 = zext_ln203_fu_5144_p1; + +assign res_121_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_122_V_address0 = zext_ln203_fu_5144_p1; + +assign res_122_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_123_V_address0 = zext_ln203_fu_5144_p1; + +assign res_123_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_124_V_address0 = zext_ln203_fu_5144_p1; + +assign res_124_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_125_V_address0 = zext_ln203_fu_5144_p1; + +assign res_125_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_126_V_address0 = zext_ln203_fu_5144_p1; + +assign res_126_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_127_V_address0 = zext_ln203_fu_5144_p1; + +assign res_127_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_12_V_address0 = zext_ln203_fu_5144_p1; + +assign res_12_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_13_V_address0 = zext_ln203_fu_5144_p1; + +assign res_13_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_14_V_address0 = zext_ln203_fu_5144_p1; + +assign res_14_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_15_V_address0 = zext_ln203_fu_5144_p1; + +assign res_15_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_16_V_address0 = zext_ln203_fu_5144_p1; + +assign res_16_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_17_V_address0 = zext_ln203_fu_5144_p1; + +assign res_17_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_18_V_address0 = zext_ln203_fu_5144_p1; + +assign res_18_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_19_V_address0 = zext_ln203_fu_5144_p1; + +assign res_19_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_1_V_address0 = zext_ln203_fu_5144_p1; + +assign res_1_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_20_V_address0 = zext_ln203_fu_5144_p1; + +assign res_20_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_21_V_address0 = zext_ln203_fu_5144_p1; + +assign res_21_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_22_V_address0 = zext_ln203_fu_5144_p1; + +assign res_22_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_23_V_address0 = zext_ln203_fu_5144_p1; + +assign res_23_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_24_V_address0 = zext_ln203_fu_5144_p1; + +assign res_24_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_25_V_address0 = zext_ln203_fu_5144_p1; + +assign res_25_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_26_V_address0 = zext_ln203_fu_5144_p1; + +assign res_26_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_27_V_address0 = zext_ln203_fu_5144_p1; + +assign res_27_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_28_V_address0 = zext_ln203_fu_5144_p1; + +assign res_28_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_29_V_address0 = zext_ln203_fu_5144_p1; + +assign res_29_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_2_V_address0 = zext_ln203_fu_5144_p1; + +assign res_2_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_30_V_address0 = zext_ln203_fu_5144_p1; + +assign res_30_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_31_V_address0 = zext_ln203_fu_5144_p1; + +assign res_31_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_32_V_address0 = zext_ln203_fu_5144_p1; + +assign res_32_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_33_V_address0 = zext_ln203_fu_5144_p1; + +assign res_33_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_34_V_address0 = zext_ln203_fu_5144_p1; + +assign res_34_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_35_V_address0 = zext_ln203_fu_5144_p1; + +assign res_35_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_36_V_address0 = zext_ln203_fu_5144_p1; + +assign res_36_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_37_V_address0 = zext_ln203_fu_5144_p1; + +assign res_37_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_38_V_address0 = zext_ln203_fu_5144_p1; + +assign res_38_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_39_V_address0 = zext_ln203_fu_5144_p1; + +assign res_39_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_3_V_address0 = zext_ln203_fu_5144_p1; + +assign res_3_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_40_V_address0 = zext_ln203_fu_5144_p1; + +assign res_40_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_41_V_address0 = zext_ln203_fu_5144_p1; + +assign res_41_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_42_V_address0 = zext_ln203_fu_5144_p1; + +assign res_42_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_43_V_address0 = zext_ln203_fu_5144_p1; + +assign res_43_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_44_V_address0 = zext_ln203_fu_5144_p1; + +assign res_44_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_45_V_address0 = zext_ln203_fu_5144_p1; + +assign res_45_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_46_V_address0 = zext_ln203_fu_5144_p1; + +assign res_46_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_47_V_address0 = zext_ln203_fu_5144_p1; + +assign res_47_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_48_V_address0 = zext_ln203_fu_5144_p1; + +assign res_48_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_49_V_address0 = zext_ln203_fu_5144_p1; + +assign res_49_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_4_V_address0 = zext_ln203_fu_5144_p1; + +assign res_4_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_50_V_address0 = zext_ln203_fu_5144_p1; + +assign res_50_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_51_V_address0 = zext_ln203_fu_5144_p1; + +assign res_51_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_52_V_address0 = zext_ln203_fu_5144_p1; + +assign res_52_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_53_V_address0 = zext_ln203_fu_5144_p1; + +assign res_53_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_54_V_address0 = zext_ln203_fu_5144_p1; + +assign res_54_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_55_V_address0 = zext_ln203_fu_5144_p1; + +assign res_55_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_56_V_address0 = zext_ln203_fu_5144_p1; + +assign res_56_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_57_V_address0 = zext_ln203_fu_5144_p1; + +assign res_57_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_58_V_address0 = zext_ln203_fu_5144_p1; + +assign res_58_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_59_V_address0 = zext_ln203_fu_5144_p1; + +assign res_59_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_5_V_address0 = zext_ln203_fu_5144_p1; + +assign res_5_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_60_V_address0 = zext_ln203_fu_5144_p1; + +assign res_60_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_61_V_address0 = zext_ln203_fu_5144_p1; + +assign res_61_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_62_V_address0 = zext_ln203_fu_5144_p1; + +assign res_62_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_63_V_address0 = zext_ln203_fu_5144_p1; + +assign res_63_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_64_V_address0 = zext_ln203_fu_5144_p1; + +assign res_64_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_65_V_address0 = zext_ln203_fu_5144_p1; + +assign res_65_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_66_V_address0 = zext_ln203_fu_5144_p1; + +assign res_66_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_67_V_address0 = zext_ln203_fu_5144_p1; + +assign res_67_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_68_V_address0 = zext_ln203_fu_5144_p1; + +assign res_68_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_69_V_address0 = zext_ln203_fu_5144_p1; + +assign res_69_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_6_V_address0 = zext_ln203_fu_5144_p1; + +assign res_6_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_70_V_address0 = zext_ln203_fu_5144_p1; + +assign res_70_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_71_V_address0 = zext_ln203_fu_5144_p1; + +assign res_71_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_72_V_address0 = zext_ln203_fu_5144_p1; + +assign res_72_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_73_V_address0 = zext_ln203_fu_5144_p1; + +assign res_73_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_74_V_address0 = zext_ln203_fu_5144_p1; + +assign res_74_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_75_V_address0 = zext_ln203_fu_5144_p1; + +assign res_75_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_76_V_address0 = zext_ln203_fu_5144_p1; + +assign res_76_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_77_V_address0 = zext_ln203_fu_5144_p1; + +assign res_77_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_78_V_address0 = zext_ln203_fu_5144_p1; + +assign res_78_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_79_V_address0 = zext_ln203_fu_5144_p1; + +assign res_79_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_7_V_address0 = zext_ln203_fu_5144_p1; + +assign res_7_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_80_V_address0 = zext_ln203_fu_5144_p1; + +assign res_80_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_81_V_address0 = zext_ln203_fu_5144_p1; + +assign res_81_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_82_V_address0 = zext_ln203_fu_5144_p1; + +assign res_82_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_83_V_address0 = zext_ln203_fu_5144_p1; + +assign res_83_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_84_V_address0 = zext_ln203_fu_5144_p1; + +assign res_84_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_85_V_address0 = zext_ln203_fu_5144_p1; + +assign res_85_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_86_V_address0 = zext_ln203_fu_5144_p1; + +assign res_86_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_87_V_address0 = zext_ln203_fu_5144_p1; + +assign res_87_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_88_V_address0 = zext_ln203_fu_5144_p1; + +assign res_88_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_89_V_address0 = zext_ln203_fu_5144_p1; + +assign res_89_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_8_V_address0 = zext_ln203_fu_5144_p1; + +assign res_8_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_90_V_address0 = zext_ln203_fu_5144_p1; + +assign res_90_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_91_V_address0 = zext_ln203_fu_5144_p1; + +assign res_91_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_92_V_address0 = zext_ln203_fu_5144_p1; + +assign res_92_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_93_V_address0 = zext_ln203_fu_5144_p1; + +assign res_93_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_94_V_address0 = zext_ln203_fu_5144_p1; + +assign res_94_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_95_V_address0 = zext_ln203_fu_5144_p1; + +assign res_95_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_96_V_address0 = zext_ln203_fu_5144_p1; + +assign res_96_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_97_V_address0 = zext_ln203_fu_5144_p1; + +assign res_97_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_98_V_address0 = zext_ln203_fu_5144_p1; + +assign res_98_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_99_V_address0 = zext_ln203_fu_5144_p1; + +assign res_99_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign res_9_V_address0 = zext_ln203_fu_5144_p1; + +assign res_9_V_d0 = agg_result_V_0_i_i_reg_4529; + +assign sext_ln203_2_fu_4943_p1 = (trunc_ln203_2_fu_4933_p4); + +assign sext_ln203_fu_5140_p1 = (trunc_ln3_fu_5131_p4); + +assign shl_ln223_fu_4802_p2 = kk_0_reg_4245 << 2'd1; + +assign shl_ln225_2_fu_4820_p3 = {{add_ln221_fu_4790_p2}, {4'd0}}; + +assign shl_ln225_3_fu_4911_p3 = {{add_ln221_2_fu_4890_p2}, {2'd0}}; + +assign shl_ln233_2_fu_4708_p3 = {{ii_0_reg_4221}, {2'd0}}; + +assign shl_ln233_3_fu_5089_p3 = {{jj_0_reg_4233}, {1'd0}}; + +assign shl_ln4_fu_4808_p3 = {{add_ln221_fu_4790_p2}, {7'd0}}; + +assign shl_ln_fu_4696_p3 = {{ii_0_reg_4221}, {5'd0}}; + +assign sub_ln225_fu_4832_p2 = (zext_ln225_4_fu_4816_p1 - zext_ln225_5_fu_4828_p1); + +assign sub_ln233_fu_4720_p2 = (zext_ln233_fu_4704_p1 - zext_ln233_3_fu_4716_p1); + +assign tmp_1_fu_4744_p4 = {{sub_ln233_fu_4720_p2[6:3]}}; + +assign tmp_2_fu_4838_p4 = {{sub_ln225_fu_4832_p2[12:3]}}; + +assign tmp_3_fu_4856_p4 = {{sub_ln225_fu_4832_p2[6:3]}}; + +assign tmp_fu_4726_p4 = {{sub_ln233_fu_4720_p2[10:3]}}; + +assign trunc_ln203_2_fu_4933_p4 = {{add_ln225_3_fu_4923_p2[12:7]}}; + +assign trunc_ln3_fu_5131_p4 = {{add_ln233_reg_6664[10:7]}}; + +assign trunc_ln_fu_4754_p3 = {{tmp_1_fu_4744_p4}, {ff_0_reg_4209}}; + +assign y_V_2_fu_5282_p3 = ((icmp_ln1494_fu_5276_p2[0:0] == 1'b1) ? pool_V_q0 : agg_result_V_0_i_i_reg_4529); + +assign zext_ln14_fu_5116_p1 = i_0_i_i_reg_4667; + +assign zext_ln203_2_fu_4947_p1 = (sext_ln203_2_fu_4943_p1); + +assign zext_ln203_fu_5144_p1 = (sext_ln203_fu_5140_p1); + +assign zext_ln218_fu_4774_p1 = kk_0_reg_4245; + +assign zext_ln220_fu_4874_p1 = ll_0_reg_4256; + +assign zext_ln223_fu_5084_p1 = add_ln223_fu_5079_p2; + +assign zext_ln225_4_fu_4816_p1 = shl_ln4_fu_4808_p3; + +assign zext_ln225_5_fu_4828_p1 = shl_ln225_2_fu_4820_p3; + +assign zext_ln225_6_fu_4919_p1 = shl_ln225_3_fu_4911_p3; + +assign zext_ln225_fu_4907_p1 = add_ln225_fu_4902_p2; + +assign zext_ln233_3_fu_4716_p1 = shl_ln233_2_fu_4708_p3; + +assign zext_ln233_4_fu_5097_p1 = shl_ln233_3_fu_5089_p3; + +assign zext_ln233_5_fu_5101_p1 = shl_ln233_3_fu_5089_p3; + +assign zext_ln233_fu_4704_p1 = shl_ln_fu_4696_p3; + +always @ (posedge ap_clk) begin + shl_ln223_reg_5342[0] <= 1'b0; + or_ln1_reg_5348[3] <= 1'b0; + or_ln225_1_reg_5353[3] <= 1'b0; + zext_ln225_reg_5370[63:2] <= 62'b00000000000000000000000000000000000000000000000000000000000000; + zext_ln233_5_reg_6659[0] <= 1'b0; + zext_ln233_5_reg_6659[6] <= 1'b0; +end + +endmodule //pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s +// ============================================================== +// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL +// Version: 2019.2 +// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_idle, + ap_ready, + data_0_V_address0, + data_0_V_ce0, + data_0_V_q0, + data_1_V_address0, + data_1_V_ce0, + data_1_V_q0, + data_2_V_address0, + data_2_V_ce0, + data_2_V_q0, + data_3_V_address0, + data_3_V_ce0, + data_3_V_q0, + data_4_V_address0, + data_4_V_ce0, + data_4_V_q0, + data_5_V_address0, + data_5_V_ce0, + data_5_V_q0, + data_6_V_address0, + data_6_V_ce0, + data_6_V_q0, + data_7_V_address0, + data_7_V_ce0, + data_7_V_q0, + data_8_V_address0, + data_8_V_ce0, + data_8_V_q0, + data_9_V_address0, + data_9_V_ce0, + data_9_V_q0, + data_10_V_address0, + data_10_V_ce0, + data_10_V_q0, + data_11_V_address0, + data_11_V_ce0, + data_11_V_q0, + data_12_V_address0, + data_12_V_ce0, + data_12_V_q0, + data_13_V_address0, + data_13_V_ce0, + data_13_V_q0, + data_14_V_address0, + data_14_V_ce0, + data_14_V_q0, + data_15_V_address0, + data_15_V_ce0, + data_15_V_q0, + data_16_V_address0, + data_16_V_ce0, + data_16_V_q0, + data_17_V_address0, + data_17_V_ce0, + data_17_V_q0, + data_18_V_address0, + data_18_V_ce0, + data_18_V_q0, + data_19_V_address0, + data_19_V_ce0, + data_19_V_q0, + data_20_V_address0, + data_20_V_ce0, + data_20_V_q0, + data_21_V_address0, + data_21_V_ce0, + data_21_V_q0, + data_22_V_address0, + data_22_V_ce0, + data_22_V_q0, + data_23_V_address0, + data_23_V_ce0, + data_23_V_q0, + data_24_V_address0, + data_24_V_ce0, + data_24_V_q0, + data_25_V_address0, + data_25_V_ce0, + data_25_V_q0, + data_26_V_address0, + data_26_V_ce0, + data_26_V_q0, + data_27_V_address0, + data_27_V_ce0, + data_27_V_q0, + data_28_V_address0, + data_28_V_ce0, + data_28_V_q0, + data_29_V_address0, + data_29_V_ce0, + data_29_V_q0, + data_30_V_address0, + data_30_V_ce0, + data_30_V_q0, + data_31_V_address0, + data_31_V_ce0, + data_31_V_q0, + data_32_V_address0, + data_32_V_ce0, + data_32_V_q0, + data_33_V_address0, + data_33_V_ce0, + data_33_V_q0, + data_34_V_address0, + data_34_V_ce0, + data_34_V_q0, + data_35_V_address0, + data_35_V_ce0, + data_35_V_q0, + data_36_V_address0, + data_36_V_ce0, + data_36_V_q0, + data_37_V_address0, + data_37_V_ce0, + data_37_V_q0, + data_38_V_address0, + data_38_V_ce0, + data_38_V_q0, + data_39_V_address0, + data_39_V_ce0, + data_39_V_q0, + data_40_V_address0, + data_40_V_ce0, + data_40_V_q0, + data_41_V_address0, + data_41_V_ce0, + data_41_V_q0, + data_42_V_address0, + data_42_V_ce0, + data_42_V_q0, + data_43_V_address0, + data_43_V_ce0, + data_43_V_q0, + data_44_V_address0, + data_44_V_ce0, + data_44_V_q0, + data_45_V_address0, + data_45_V_ce0, + data_45_V_q0, + data_46_V_address0, + data_46_V_ce0, + data_46_V_q0, + data_47_V_address0, + data_47_V_ce0, + data_47_V_q0, + data_48_V_address0, + data_48_V_ce0, + data_48_V_q0, + data_49_V_address0, + data_49_V_ce0, + data_49_V_q0, + data_50_V_address0, + data_50_V_ce0, + data_50_V_q0, + data_51_V_address0, + data_51_V_ce0, + data_51_V_q0, + data_52_V_address0, + data_52_V_ce0, + data_52_V_q0, + data_53_V_address0, + data_53_V_ce0, + data_53_V_q0, + data_54_V_address0, + data_54_V_ce0, + data_54_V_q0, + data_55_V_address0, + data_55_V_ce0, + data_55_V_q0, + data_56_V_address0, + data_56_V_ce0, + data_56_V_q0, + data_57_V_address0, + data_57_V_ce0, + data_57_V_q0, + data_58_V_address0, + data_58_V_ce0, + data_58_V_q0, + data_59_V_address0, + data_59_V_ce0, + data_59_V_q0, + data_60_V_address0, + data_60_V_ce0, + data_60_V_q0, + data_61_V_address0, + data_61_V_ce0, + data_61_V_q0, + data_62_V_address0, + data_62_V_ce0, + data_62_V_q0, + data_63_V_address0, + data_63_V_ce0, + data_63_V_q0, + data_64_V_address0, + data_64_V_ce0, + data_64_V_q0, + data_65_V_address0, + data_65_V_ce0, + data_65_V_q0, + data_66_V_address0, + data_66_V_ce0, + data_66_V_q0, + data_67_V_address0, + data_67_V_ce0, + data_67_V_q0, + data_68_V_address0, + data_68_V_ce0, + data_68_V_q0, + data_69_V_address0, + data_69_V_ce0, + data_69_V_q0, + data_70_V_address0, + data_70_V_ce0, + data_70_V_q0, + data_71_V_address0, + data_71_V_ce0, + data_71_V_q0, + data_72_V_address0, + data_72_V_ce0, + data_72_V_q0, + data_73_V_address0, + data_73_V_ce0, + data_73_V_q0, + data_74_V_address0, + data_74_V_ce0, + data_74_V_q0, + data_75_V_address0, + data_75_V_ce0, + data_75_V_q0, + data_76_V_address0, + data_76_V_ce0, + data_76_V_q0, + data_77_V_address0, + data_77_V_ce0, + data_77_V_q0, + data_78_V_address0, + data_78_V_ce0, + data_78_V_q0, + data_79_V_address0, + data_79_V_ce0, + data_79_V_q0, + data_80_V_address0, + data_80_V_ce0, + data_80_V_q0, + data_81_V_address0, + data_81_V_ce0, + data_81_V_q0, + data_82_V_address0, + data_82_V_ce0, + data_82_V_q0, + data_83_V_address0, + data_83_V_ce0, + data_83_V_q0, + data_84_V_address0, + data_84_V_ce0, + data_84_V_q0, + data_85_V_address0, + data_85_V_ce0, + data_85_V_q0, + data_86_V_address0, + data_86_V_ce0, + data_86_V_q0, + data_87_V_address0, + data_87_V_ce0, + data_87_V_q0, + data_88_V_address0, + data_88_V_ce0, + data_88_V_q0, + data_89_V_address0, + data_89_V_ce0, + data_89_V_q0, + data_90_V_address0, + data_90_V_ce0, + data_90_V_q0, + data_91_V_address0, + data_91_V_ce0, + data_91_V_q0, + data_92_V_address0, + data_92_V_ce0, + data_92_V_q0, + data_93_V_address0, + data_93_V_ce0, + data_93_V_q0, + data_94_V_address0, + data_94_V_ce0, + data_94_V_q0, + data_95_V_address0, + data_95_V_ce0, + data_95_V_q0, + data_96_V_address0, + data_96_V_ce0, + data_96_V_q0, + data_97_V_address0, + data_97_V_ce0, + data_97_V_q0, + data_98_V_address0, + data_98_V_ce0, + data_98_V_q0, + data_99_V_address0, + data_99_V_ce0, + data_99_V_q0, + data_100_V_address0, + data_100_V_ce0, + data_100_V_q0, + data_101_V_address0, + data_101_V_ce0, + data_101_V_q0, + data_102_V_address0, + data_102_V_ce0, + data_102_V_q0, + data_103_V_address0, + data_103_V_ce0, + data_103_V_q0, + data_104_V_address0, + data_104_V_ce0, + data_104_V_q0, + data_105_V_address0, + data_105_V_ce0, + data_105_V_q0, + data_106_V_address0, + data_106_V_ce0, + data_106_V_q0, + data_107_V_address0, + data_107_V_ce0, + data_107_V_q0, + data_108_V_address0, + data_108_V_ce0, + data_108_V_q0, + data_109_V_address0, + data_109_V_ce0, + data_109_V_q0, + data_110_V_address0, + data_110_V_ce0, + data_110_V_q0, + data_111_V_address0, + data_111_V_ce0, + data_111_V_q0, + data_112_V_address0, + data_112_V_ce0, + data_112_V_q0, + data_113_V_address0, + data_113_V_ce0, + data_113_V_q0, + data_114_V_address0, + data_114_V_ce0, + data_114_V_q0, + data_115_V_address0, + data_115_V_ce0, + data_115_V_q0, + data_116_V_address0, + data_116_V_ce0, + data_116_V_q0, + data_117_V_address0, + data_117_V_ce0, + data_117_V_q0, + data_118_V_address0, + data_118_V_ce0, + data_118_V_q0, + data_119_V_address0, + data_119_V_ce0, + data_119_V_q0, + data_120_V_address0, + data_120_V_ce0, + data_120_V_q0, + data_121_V_address0, + data_121_V_ce0, + data_121_V_q0, + data_122_V_address0, + data_122_V_ce0, + data_122_V_q0, + data_123_V_address0, + data_123_V_ce0, + data_123_V_q0, + data_124_V_address0, + data_124_V_ce0, + data_124_V_q0, + data_125_V_address0, + data_125_V_ce0, + data_125_V_q0, + data_126_V_address0, + data_126_V_ce0, + data_126_V_q0, + data_127_V_address0, + data_127_V_ce0, + data_127_V_q0, + res_0_V_address0, + res_0_V_ce0, + res_0_V_we0, + res_0_V_d0, + res_1_V_address0, + res_1_V_ce0, + res_1_V_we0, + res_1_V_d0, + res_2_V_address0, + res_2_V_ce0, + res_2_V_we0, + res_2_V_d0, + res_3_V_address0, + res_3_V_ce0, + res_3_V_we0, + res_3_V_d0, + res_4_V_address0, + res_4_V_ce0, + res_4_V_we0, + res_4_V_d0, + res_5_V_address0, + res_5_V_ce0, + res_5_V_we0, + res_5_V_d0, + res_6_V_address0, + res_6_V_ce0, + res_6_V_we0, + res_6_V_d0, + res_7_V_address0, + res_7_V_ce0, + res_7_V_we0, + res_7_V_d0, + res_8_V_address0, + res_8_V_ce0, + res_8_V_we0, + res_8_V_d0, + res_9_V_address0, + res_9_V_ce0, + res_9_V_we0, + res_9_V_d0, + res_10_V_address0, + res_10_V_ce0, + res_10_V_we0, + res_10_V_d0, + res_11_V_address0, + res_11_V_ce0, + res_11_V_we0, + res_11_V_d0, + res_12_V_address0, + res_12_V_ce0, + res_12_V_we0, + res_12_V_d0, + res_13_V_address0, + res_13_V_ce0, + res_13_V_we0, + res_13_V_d0, + res_14_V_address0, + res_14_V_ce0, + res_14_V_we0, + res_14_V_d0, + res_15_V_address0, + res_15_V_ce0, + res_15_V_we0, + res_15_V_d0, + res_16_V_address0, + res_16_V_ce0, + res_16_V_we0, + res_16_V_d0, + res_17_V_address0, + res_17_V_ce0, + res_17_V_we0, + res_17_V_d0, + res_18_V_address0, + res_18_V_ce0, + res_18_V_we0, + res_18_V_d0, + res_19_V_address0, + res_19_V_ce0, + res_19_V_we0, + res_19_V_d0, + res_20_V_address0, + res_20_V_ce0, + res_20_V_we0, + res_20_V_d0, + res_21_V_address0, + res_21_V_ce0, + res_21_V_we0, + res_21_V_d0, + res_22_V_address0, + res_22_V_ce0, + res_22_V_we0, + res_22_V_d0, + res_23_V_address0, + res_23_V_ce0, + res_23_V_we0, + res_23_V_d0, + res_24_V_address0, + res_24_V_ce0, + res_24_V_we0, + res_24_V_d0, + res_25_V_address0, + res_25_V_ce0, + res_25_V_we0, + res_25_V_d0, + res_26_V_address0, + res_26_V_ce0, + res_26_V_we0, + res_26_V_d0, + res_27_V_address0, + res_27_V_ce0, + res_27_V_we0, + res_27_V_d0, + res_28_V_address0, + res_28_V_ce0, + res_28_V_we0, + res_28_V_d0, + res_29_V_address0, + res_29_V_ce0, + res_29_V_we0, + res_29_V_d0, + res_30_V_address0, + res_30_V_ce0, + res_30_V_we0, + res_30_V_d0, + res_31_V_address0, + res_31_V_ce0, + res_31_V_we0, + res_31_V_d0, + res_32_V_address0, + res_32_V_ce0, + res_32_V_we0, + res_32_V_d0, + res_33_V_address0, + res_33_V_ce0, + res_33_V_we0, + res_33_V_d0, + res_34_V_address0, + res_34_V_ce0, + res_34_V_we0, + res_34_V_d0, + res_35_V_address0, + res_35_V_ce0, + res_35_V_we0, + res_35_V_d0, + res_36_V_address0, + res_36_V_ce0, + res_36_V_we0, + res_36_V_d0, + res_37_V_address0, + res_37_V_ce0, + res_37_V_we0, + res_37_V_d0, + res_38_V_address0, + res_38_V_ce0, + res_38_V_we0, + res_38_V_d0, + res_39_V_address0, + res_39_V_ce0, + res_39_V_we0, + res_39_V_d0, + res_40_V_address0, + res_40_V_ce0, + res_40_V_we0, + res_40_V_d0, + res_41_V_address0, + res_41_V_ce0, + res_41_V_we0, + res_41_V_d0, + res_42_V_address0, + res_42_V_ce0, + res_42_V_we0, + res_42_V_d0, + res_43_V_address0, + res_43_V_ce0, + res_43_V_we0, + res_43_V_d0, + res_44_V_address0, + res_44_V_ce0, + res_44_V_we0, + res_44_V_d0, + res_45_V_address0, + res_45_V_ce0, + res_45_V_we0, + res_45_V_d0, + res_46_V_address0, + res_46_V_ce0, + res_46_V_we0, + res_46_V_d0, + res_47_V_address0, + res_47_V_ce0, + res_47_V_we0, + res_47_V_d0, + res_48_V_address0, + res_48_V_ce0, + res_48_V_we0, + res_48_V_d0, + res_49_V_address0, + res_49_V_ce0, + res_49_V_we0, + res_49_V_d0, + res_50_V_address0, + res_50_V_ce0, + res_50_V_we0, + res_50_V_d0, + res_51_V_address0, + res_51_V_ce0, + res_51_V_we0, + res_51_V_d0, + res_52_V_address0, + res_52_V_ce0, + res_52_V_we0, + res_52_V_d0, + res_53_V_address0, + res_53_V_ce0, + res_53_V_we0, + res_53_V_d0, + res_54_V_address0, + res_54_V_ce0, + res_54_V_we0, + res_54_V_d0, + res_55_V_address0, + res_55_V_ce0, + res_55_V_we0, + res_55_V_d0, + res_56_V_address0, + res_56_V_ce0, + res_56_V_we0, + res_56_V_d0, + res_57_V_address0, + res_57_V_ce0, + res_57_V_we0, + res_57_V_d0, + res_58_V_address0, + res_58_V_ce0, + res_58_V_we0, + res_58_V_d0, + res_59_V_address0, + res_59_V_ce0, + res_59_V_we0, + res_59_V_d0, + res_60_V_address0, + res_60_V_ce0, + res_60_V_we0, + res_60_V_d0, + res_61_V_address0, + res_61_V_ce0, + res_61_V_we0, + res_61_V_d0, + res_62_V_address0, + res_62_V_ce0, + res_62_V_we0, + res_62_V_d0, + res_63_V_address0, + res_63_V_ce0, + res_63_V_we0, + res_63_V_d0, + res_64_V_address0, + res_64_V_ce0, + res_64_V_we0, + res_64_V_d0, + res_65_V_address0, + res_65_V_ce0, + res_65_V_we0, + res_65_V_d0, + res_66_V_address0, + res_66_V_ce0, + res_66_V_we0, + res_66_V_d0, + res_67_V_address0, + res_67_V_ce0, + res_67_V_we0, + res_67_V_d0, + res_68_V_address0, + res_68_V_ce0, + res_68_V_we0, + res_68_V_d0, + res_69_V_address0, + res_69_V_ce0, + res_69_V_we0, + res_69_V_d0, + res_70_V_address0, + res_70_V_ce0, + res_70_V_we0, + res_70_V_d0, + res_71_V_address0, + res_71_V_ce0, + res_71_V_we0, + res_71_V_d0, + res_72_V_address0, + res_72_V_ce0, + res_72_V_we0, + res_72_V_d0, + res_73_V_address0, + res_73_V_ce0, + res_73_V_we0, + res_73_V_d0, + res_74_V_address0, + res_74_V_ce0, + res_74_V_we0, + res_74_V_d0, + res_75_V_address0, + res_75_V_ce0, + res_75_V_we0, + res_75_V_d0, + res_76_V_address0, + res_76_V_ce0, + res_76_V_we0, + res_76_V_d0, + res_77_V_address0, + res_77_V_ce0, + res_77_V_we0, + res_77_V_d0, + res_78_V_address0, + res_78_V_ce0, + res_78_V_we0, + res_78_V_d0, + res_79_V_address0, + res_79_V_ce0, + res_79_V_we0, + res_79_V_d0, + res_80_V_address0, + res_80_V_ce0, + res_80_V_we0, + res_80_V_d0, + res_81_V_address0, + res_81_V_ce0, + res_81_V_we0, + res_81_V_d0, + res_82_V_address0, + res_82_V_ce0, + res_82_V_we0, + res_82_V_d0, + res_83_V_address0, + res_83_V_ce0, + res_83_V_we0, + res_83_V_d0, + res_84_V_address0, + res_84_V_ce0, + res_84_V_we0, + res_84_V_d0, + res_85_V_address0, + res_85_V_ce0, + res_85_V_we0, + res_85_V_d0, + res_86_V_address0, + res_86_V_ce0, + res_86_V_we0, + res_86_V_d0, + res_87_V_address0, + res_87_V_ce0, + res_87_V_we0, + res_87_V_d0, + res_88_V_address0, + res_88_V_ce0, + res_88_V_we0, + res_88_V_d0, + res_89_V_address0, + res_89_V_ce0, + res_89_V_we0, + res_89_V_d0, + res_90_V_address0, + res_90_V_ce0, + res_90_V_we0, + res_90_V_d0, + res_91_V_address0, + res_91_V_ce0, + res_91_V_we0, + res_91_V_d0, + res_92_V_address0, + res_92_V_ce0, + res_92_V_we0, + res_92_V_d0, + res_93_V_address0, + res_93_V_ce0, + res_93_V_we0, + res_93_V_d0, + res_94_V_address0, + res_94_V_ce0, + res_94_V_we0, + res_94_V_d0, + res_95_V_address0, + res_95_V_ce0, + res_95_V_we0, + res_95_V_d0, + res_96_V_address0, + res_96_V_ce0, + res_96_V_we0, + res_96_V_d0, + res_97_V_address0, + res_97_V_ce0, + res_97_V_we0, + res_97_V_d0, + res_98_V_address0, + res_98_V_ce0, + res_98_V_we0, + res_98_V_d0, + res_99_V_address0, + res_99_V_ce0, + res_99_V_we0, + res_99_V_d0, + res_100_V_address0, + res_100_V_ce0, + res_100_V_we0, + res_100_V_d0, + res_101_V_address0, + res_101_V_ce0, + res_101_V_we0, + res_101_V_d0, + res_102_V_address0, + res_102_V_ce0, + res_102_V_we0, + res_102_V_d0, + res_103_V_address0, + res_103_V_ce0, + res_103_V_we0, + res_103_V_d0, + res_104_V_address0, + res_104_V_ce0, + res_104_V_we0, + res_104_V_d0, + res_105_V_address0, + res_105_V_ce0, + res_105_V_we0, + res_105_V_d0, + res_106_V_address0, + res_106_V_ce0, + res_106_V_we0, + res_106_V_d0, + res_107_V_address0, + res_107_V_ce0, + res_107_V_we0, + res_107_V_d0, + res_108_V_address0, + res_108_V_ce0, + res_108_V_we0, + res_108_V_d0, + res_109_V_address0, + res_109_V_ce0, + res_109_V_we0, + res_109_V_d0, + res_110_V_address0, + res_110_V_ce0, + res_110_V_we0, + res_110_V_d0, + res_111_V_address0, + res_111_V_ce0, + res_111_V_we0, + res_111_V_d0, + res_112_V_address0, + res_112_V_ce0, + res_112_V_we0, + res_112_V_d0, + res_113_V_address0, + res_113_V_ce0, + res_113_V_we0, + res_113_V_d0, + res_114_V_address0, + res_114_V_ce0, + res_114_V_we0, + res_114_V_d0, + res_115_V_address0, + res_115_V_ce0, + res_115_V_we0, + res_115_V_d0, + res_116_V_address0, + res_116_V_ce0, + res_116_V_we0, + res_116_V_d0, + res_117_V_address0, + res_117_V_ce0, + res_117_V_we0, + res_117_V_d0, + res_118_V_address0, + res_118_V_ce0, + res_118_V_we0, + res_118_V_d0, + res_119_V_address0, + res_119_V_ce0, + res_119_V_we0, + res_119_V_d0, + res_120_V_address0, + res_120_V_ce0, + res_120_V_we0, + res_120_V_d0, + res_121_V_address0, + res_121_V_ce0, + res_121_V_we0, + res_121_V_d0, + res_122_V_address0, + res_122_V_ce0, + res_122_V_we0, + res_122_V_d0, + res_123_V_address0, + res_123_V_ce0, + res_123_V_we0, + res_123_V_d0, + res_124_V_address0, + res_124_V_ce0, + res_124_V_we0, + res_124_V_d0, + res_125_V_address0, + res_125_V_ce0, + res_125_V_we0, + res_125_V_d0, + res_126_V_address0, + res_126_V_ce0, + res_126_V_we0, + res_126_V_d0, + res_127_V_address0, + res_127_V_ce0, + res_127_V_we0, + res_127_V_d0 +); + +parameter ap_ST_fsm_state1 = 4'd0; +parameter ap_ST_fsm_state2 = 4'd1; +parameter ap_ST_fsm_state3 = 4'd2; +parameter ap_ST_fsm_state4 = 4'd3; +parameter ap_ST_fsm_state5 = 4'd4; +parameter ap_ST_fsm_state6 = 4'd5; +parameter ap_ST_fsm_state7 = 4'd6; +parameter ap_ST_fsm_state8 = 4'd7; +parameter ap_ST_fsm_state9 = 4'd8; +parameter ap_ST_fsm_state10 = 4'd9; +parameter ap_ST_fsm_state11 = 4'd10; +parameter ap_ST_fsm_state12 = 4'd11; +parameter ap_ST_fsm_state13 = 4'd12; +parameter ap_ST_fsm_state14 = 4'd13; +parameter ap_ST_fsm_state15 = 4'd14; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +output [4:0] data_0_V_address0; +output data_0_V_ce0; +input [7:0] data_0_V_q0; +output [4:0] data_1_V_address0; +output data_1_V_ce0; +input [7:0] data_1_V_q0; +output [4:0] data_2_V_address0; +output data_2_V_ce0; +input [7:0] data_2_V_q0; +output [4:0] data_3_V_address0; +output data_3_V_ce0; +input [7:0] data_3_V_q0; +output [4:0] data_4_V_address0; +output data_4_V_ce0; +input [7:0] data_4_V_q0; +output [4:0] data_5_V_address0; +output data_5_V_ce0; +input [7:0] data_5_V_q0; +output [4:0] data_6_V_address0; +output data_6_V_ce0; +input [7:0] data_6_V_q0; +output [4:0] data_7_V_address0; +output data_7_V_ce0; +input [7:0] data_7_V_q0; +output [4:0] data_8_V_address0; +output data_8_V_ce0; +input [7:0] data_8_V_q0; +output [4:0] data_9_V_address0; +output data_9_V_ce0; +input [7:0] data_9_V_q0; +output [4:0] data_10_V_address0; +output data_10_V_ce0; +input [7:0] data_10_V_q0; +output [4:0] data_11_V_address0; +output data_11_V_ce0; +input [7:0] data_11_V_q0; +output [4:0] data_12_V_address0; +output data_12_V_ce0; +input [7:0] data_12_V_q0; +output [4:0] data_13_V_address0; +output data_13_V_ce0; +input [7:0] data_13_V_q0; +output [4:0] data_14_V_address0; +output data_14_V_ce0; +input [7:0] data_14_V_q0; +output [4:0] data_15_V_address0; +output data_15_V_ce0; +input [7:0] data_15_V_q0; +output [4:0] data_16_V_address0; +output data_16_V_ce0; +input [7:0] data_16_V_q0; +output [4:0] data_17_V_address0; +output data_17_V_ce0; +input [7:0] data_17_V_q0; +output [4:0] data_18_V_address0; +output data_18_V_ce0; +input [7:0] data_18_V_q0; +output [4:0] data_19_V_address0; +output data_19_V_ce0; +input [7:0] data_19_V_q0; +output [4:0] data_20_V_address0; +output data_20_V_ce0; +input [7:0] data_20_V_q0; +output [4:0] data_21_V_address0; +output data_21_V_ce0; +input [7:0] data_21_V_q0; +output [4:0] data_22_V_address0; +output data_22_V_ce0; +input [7:0] data_22_V_q0; +output [4:0] data_23_V_address0; +output data_23_V_ce0; +input [7:0] data_23_V_q0; +output [4:0] data_24_V_address0; +output data_24_V_ce0; +input [7:0] data_24_V_q0; +output [4:0] data_25_V_address0; +output data_25_V_ce0; +input [7:0] data_25_V_q0; +output [4:0] data_26_V_address0; +output data_26_V_ce0; +input [7:0] data_26_V_q0; +output [4:0] data_27_V_address0; +output data_27_V_ce0; +input [7:0] data_27_V_q0; +output [4:0] data_28_V_address0; +output data_28_V_ce0; +input [7:0] data_28_V_q0; +output [4:0] data_29_V_address0; +output data_29_V_ce0; +input [7:0] data_29_V_q0; +output [4:0] data_30_V_address0; +output data_30_V_ce0; +input [7:0] data_30_V_q0; +output [4:0] data_31_V_address0; +output data_31_V_ce0; +input [7:0] data_31_V_q0; +output [4:0] data_32_V_address0; +output data_32_V_ce0; +input [7:0] data_32_V_q0; +output [4:0] data_33_V_address0; +output data_33_V_ce0; +input [7:0] data_33_V_q0; +output [4:0] data_34_V_address0; +output data_34_V_ce0; +input [7:0] data_34_V_q0; +output [4:0] data_35_V_address0; +output data_35_V_ce0; +input [7:0] data_35_V_q0; +output [4:0] data_36_V_address0; +output data_36_V_ce0; +input [7:0] data_36_V_q0; +output [4:0] data_37_V_address0; +output data_37_V_ce0; +input [7:0] data_37_V_q0; +output [4:0] data_38_V_address0; +output data_38_V_ce0; +input [7:0] data_38_V_q0; +output [4:0] data_39_V_address0; +output data_39_V_ce0; +input [7:0] data_39_V_q0; +output [4:0] data_40_V_address0; +output data_40_V_ce0; +input [7:0] data_40_V_q0; +output [4:0] data_41_V_address0; +output data_41_V_ce0; +input [7:0] data_41_V_q0; +output [4:0] data_42_V_address0; +output data_42_V_ce0; +input [7:0] data_42_V_q0; +output [4:0] data_43_V_address0; +output data_43_V_ce0; +input [7:0] data_43_V_q0; +output [4:0] data_44_V_address0; +output data_44_V_ce0; +input [7:0] data_44_V_q0; +output [4:0] data_45_V_address0; +output data_45_V_ce0; +input [7:0] data_45_V_q0; +output [4:0] data_46_V_address0; +output data_46_V_ce0; +input [7:0] data_46_V_q0; +output [4:0] data_47_V_address0; +output data_47_V_ce0; +input [7:0] data_47_V_q0; +output [4:0] data_48_V_address0; +output data_48_V_ce0; +input [7:0] data_48_V_q0; +output [4:0] data_49_V_address0; +output data_49_V_ce0; +input [7:0] data_49_V_q0; +output [4:0] data_50_V_address0; +output data_50_V_ce0; +input [7:0] data_50_V_q0; +output [4:0] data_51_V_address0; +output data_51_V_ce0; +input [7:0] data_51_V_q0; +output [4:0] data_52_V_address0; +output data_52_V_ce0; +input [7:0] data_52_V_q0; +output [4:0] data_53_V_address0; +output data_53_V_ce0; +input [7:0] data_53_V_q0; +output [4:0] data_54_V_address0; +output data_54_V_ce0; +input [7:0] data_54_V_q0; +output [4:0] data_55_V_address0; +output data_55_V_ce0; +input [7:0] data_55_V_q0; +output [4:0] data_56_V_address0; +output data_56_V_ce0; +input [7:0] data_56_V_q0; +output [4:0] data_57_V_address0; +output data_57_V_ce0; +input [7:0] data_57_V_q0; +output [4:0] data_58_V_address0; +output data_58_V_ce0; +input [7:0] data_58_V_q0; +output [4:0] data_59_V_address0; +output data_59_V_ce0; +input [7:0] data_59_V_q0; +output [4:0] data_60_V_address0; +output data_60_V_ce0; +input [7:0] data_60_V_q0; +output [4:0] data_61_V_address0; +output data_61_V_ce0; +input [7:0] data_61_V_q0; +output [4:0] data_62_V_address0; +output data_62_V_ce0; +input [7:0] data_62_V_q0; +output [4:0] data_63_V_address0; +output data_63_V_ce0; +input [7:0] data_63_V_q0; +output [4:0] data_64_V_address0; +output data_64_V_ce0; +input [7:0] data_64_V_q0; +output [4:0] data_65_V_address0; +output data_65_V_ce0; +input [7:0] data_65_V_q0; +output [4:0] data_66_V_address0; +output data_66_V_ce0; +input [7:0] data_66_V_q0; +output [4:0] data_67_V_address0; +output data_67_V_ce0; +input [7:0] data_67_V_q0; +output [4:0] data_68_V_address0; +output data_68_V_ce0; +input [7:0] data_68_V_q0; +output [4:0] data_69_V_address0; +output data_69_V_ce0; +input [7:0] data_69_V_q0; +output [4:0] data_70_V_address0; +output data_70_V_ce0; +input [7:0] data_70_V_q0; +output [4:0] data_71_V_address0; +output data_71_V_ce0; +input [7:0] data_71_V_q0; +output [4:0] data_72_V_address0; +output data_72_V_ce0; +input [7:0] data_72_V_q0; +output [4:0] data_73_V_address0; +output data_73_V_ce0; +input [7:0] data_73_V_q0; +output [4:0] data_74_V_address0; +output data_74_V_ce0; +input [7:0] data_74_V_q0; +output [4:0] data_75_V_address0; +output data_75_V_ce0; +input [7:0] data_75_V_q0; +output [4:0] data_76_V_address0; +output data_76_V_ce0; +input [7:0] data_76_V_q0; +output [4:0] data_77_V_address0; +output data_77_V_ce0; +input [7:0] data_77_V_q0; +output [4:0] data_78_V_address0; +output data_78_V_ce0; +input [7:0] data_78_V_q0; +output [4:0] data_79_V_address0; +output data_79_V_ce0; +input [7:0] data_79_V_q0; +output [4:0] data_80_V_address0; +output data_80_V_ce0; +input [7:0] data_80_V_q0; +output [4:0] data_81_V_address0; +output data_81_V_ce0; +input [7:0] data_81_V_q0; +output [4:0] data_82_V_address0; +output data_82_V_ce0; +input [7:0] data_82_V_q0; +output [4:0] data_83_V_address0; +output data_83_V_ce0; +input [7:0] data_83_V_q0; +output [4:0] data_84_V_address0; +output data_84_V_ce0; +input [7:0] data_84_V_q0; +output [4:0] data_85_V_address0; +output data_85_V_ce0; +input [7:0] data_85_V_q0; +output [4:0] data_86_V_address0; +output data_86_V_ce0; +input [7:0] data_86_V_q0; +output [4:0] data_87_V_address0; +output data_87_V_ce0; +input [7:0] data_87_V_q0; +output [4:0] data_88_V_address0; +output data_88_V_ce0; +input [7:0] data_88_V_q0; +output [4:0] data_89_V_address0; +output data_89_V_ce0; +input [7:0] data_89_V_q0; +output [4:0] data_90_V_address0; +output data_90_V_ce0; +input [7:0] data_90_V_q0; +output [4:0] data_91_V_address0; +output data_91_V_ce0; +input [7:0] data_91_V_q0; +output [4:0] data_92_V_address0; +output data_92_V_ce0; +input [7:0] data_92_V_q0; +output [4:0] data_93_V_address0; +output data_93_V_ce0; +input [7:0] data_93_V_q0; +output [4:0] data_94_V_address0; +output data_94_V_ce0; +input [7:0] data_94_V_q0; +output [4:0] data_95_V_address0; +output data_95_V_ce0; +input [7:0] data_95_V_q0; +output [4:0] data_96_V_address0; +output data_96_V_ce0; +input [7:0] data_96_V_q0; +output [4:0] data_97_V_address0; +output data_97_V_ce0; +input [7:0] data_97_V_q0; +output [4:0] data_98_V_address0; +output data_98_V_ce0; +input [7:0] data_98_V_q0; +output [4:0] data_99_V_address0; +output data_99_V_ce0; +input [7:0] data_99_V_q0; +output [4:0] data_100_V_address0; +output data_100_V_ce0; +input [7:0] data_100_V_q0; +output [4:0] data_101_V_address0; +output data_101_V_ce0; +input [7:0] data_101_V_q0; +output [4:0] data_102_V_address0; +output data_102_V_ce0; +input [7:0] data_102_V_q0; +output [4:0] data_103_V_address0; +output data_103_V_ce0; +input [7:0] data_103_V_q0; +output [4:0] data_104_V_address0; +output data_104_V_ce0; +input [7:0] data_104_V_q0; +output [4:0] data_105_V_address0; +output data_105_V_ce0; +input [7:0] data_105_V_q0; +output [4:0] data_106_V_address0; +output data_106_V_ce0; +input [7:0] data_106_V_q0; +output [4:0] data_107_V_address0; +output data_107_V_ce0; +input [7:0] data_107_V_q0; +output [4:0] data_108_V_address0; +output data_108_V_ce0; +input [7:0] data_108_V_q0; +output [4:0] data_109_V_address0; +output data_109_V_ce0; +input [7:0] data_109_V_q0; +output [4:0] data_110_V_address0; +output data_110_V_ce0; +input [7:0] data_110_V_q0; +output [4:0] data_111_V_address0; +output data_111_V_ce0; +input [7:0] data_111_V_q0; +output [4:0] data_112_V_address0; +output data_112_V_ce0; +input [7:0] data_112_V_q0; +output [4:0] data_113_V_address0; +output data_113_V_ce0; +input [7:0] data_113_V_q0; +output [4:0] data_114_V_address0; +output data_114_V_ce0; +input [7:0] data_114_V_q0; +output [4:0] data_115_V_address0; +output data_115_V_ce0; +input [7:0] data_115_V_q0; +output [4:0] data_116_V_address0; +output data_116_V_ce0; +input [7:0] data_116_V_q0; +output [4:0] data_117_V_address0; +output data_117_V_ce0; +input [7:0] data_117_V_q0; +output [4:0] data_118_V_address0; +output data_118_V_ce0; +input [7:0] data_118_V_q0; +output [4:0] data_119_V_address0; +output data_119_V_ce0; +input [7:0] data_119_V_q0; +output [4:0] data_120_V_address0; +output data_120_V_ce0; +input [7:0] data_120_V_q0; +output [4:0] data_121_V_address0; +output data_121_V_ce0; +input [7:0] data_121_V_q0; +output [4:0] data_122_V_address0; +output data_122_V_ce0; +input [7:0] data_122_V_q0; +output [4:0] data_123_V_address0; +output data_123_V_ce0; +input [7:0] data_123_V_q0; +output [4:0] data_124_V_address0; +output data_124_V_ce0; +input [7:0] data_124_V_q0; +output [4:0] data_125_V_address0; +output data_125_V_ce0; +input [7:0] data_125_V_q0; +output [4:0] data_126_V_address0; +output data_126_V_ce0; +input [7:0] data_126_V_q0; +output [4:0] data_127_V_address0; +output data_127_V_ce0; +input [7:0] data_127_V_q0; +output [2:0] res_0_V_address0; +output res_0_V_ce0; +output res_0_V_we0; +output [7:0] res_0_V_d0; +output [2:0] res_1_V_address0; +output res_1_V_ce0; +output res_1_V_we0; +output [7:0] res_1_V_d0; +output [2:0] res_2_V_address0; +output res_2_V_ce0; +output res_2_V_we0; +output [7:0] res_2_V_d0; +output [2:0] res_3_V_address0; +output res_3_V_ce0; +output res_3_V_we0; +output [7:0] res_3_V_d0; +output [2:0] res_4_V_address0; +output res_4_V_ce0; +output res_4_V_we0; +output [7:0] res_4_V_d0; +output [2:0] res_5_V_address0; +output res_5_V_ce0; +output res_5_V_we0; +output [7:0] res_5_V_d0; +output [2:0] res_6_V_address0; +output res_6_V_ce0; +output res_6_V_we0; +output [7:0] res_6_V_d0; +output [2:0] res_7_V_address0; +output res_7_V_ce0; +output res_7_V_we0; +output [7:0] res_7_V_d0; +output [2:0] res_8_V_address0; +output res_8_V_ce0; +output res_8_V_we0; +output [7:0] res_8_V_d0; +output [2:0] res_9_V_address0; +output res_9_V_ce0; +output res_9_V_we0; +output [7:0] res_9_V_d0; +output [2:0] res_10_V_address0; +output res_10_V_ce0; +output res_10_V_we0; +output [7:0] res_10_V_d0; +output [2:0] res_11_V_address0; +output res_11_V_ce0; +output res_11_V_we0; +output [7:0] res_11_V_d0; +output [2:0] res_12_V_address0; +output res_12_V_ce0; +output res_12_V_we0; +output [7:0] res_12_V_d0; +output [2:0] res_13_V_address0; +output res_13_V_ce0; +output res_13_V_we0; +output [7:0] res_13_V_d0; +output [2:0] res_14_V_address0; +output res_14_V_ce0; +output res_14_V_we0; +output [7:0] res_14_V_d0; +output [2:0] res_15_V_address0; +output res_15_V_ce0; +output res_15_V_we0; +output [7:0] res_15_V_d0; +output [2:0] res_16_V_address0; +output res_16_V_ce0; +output res_16_V_we0; +output [7:0] res_16_V_d0; +output [2:0] res_17_V_address0; +output res_17_V_ce0; +output res_17_V_we0; +output [7:0] res_17_V_d0; +output [2:0] res_18_V_address0; +output res_18_V_ce0; +output res_18_V_we0; +output [7:0] res_18_V_d0; +output [2:0] res_19_V_address0; +output res_19_V_ce0; +output res_19_V_we0; +output [7:0] res_19_V_d0; +output [2:0] res_20_V_address0; +output res_20_V_ce0; +output res_20_V_we0; +output [7:0] res_20_V_d0; +output [2:0] res_21_V_address0; +output res_21_V_ce0; +output res_21_V_we0; +output [7:0] res_21_V_d0; +output [2:0] res_22_V_address0; +output res_22_V_ce0; +output res_22_V_we0; +output [7:0] res_22_V_d0; +output [2:0] res_23_V_address0; +output res_23_V_ce0; +output res_23_V_we0; +output [7:0] res_23_V_d0; +output [2:0] res_24_V_address0; +output res_24_V_ce0; +output res_24_V_we0; +output [7:0] res_24_V_d0; +output [2:0] res_25_V_address0; +output res_25_V_ce0; +output res_25_V_we0; +output [7:0] res_25_V_d0; +output [2:0] res_26_V_address0; +output res_26_V_ce0; +output res_26_V_we0; +output [7:0] res_26_V_d0; +output [2:0] res_27_V_address0; +output res_27_V_ce0; +output res_27_V_we0; +output [7:0] res_27_V_d0; +output [2:0] res_28_V_address0; +output res_28_V_ce0; +output res_28_V_we0; +output [7:0] res_28_V_d0; +output [2:0] res_29_V_address0; +output res_29_V_ce0; +output res_29_V_we0; +output [7:0] res_29_V_d0; +output [2:0] res_30_V_address0; +output res_30_V_ce0; +output res_30_V_we0; +output [7:0] res_30_V_d0; +output [2:0] res_31_V_address0; +output res_31_V_ce0; +output res_31_V_we0; +output [7:0] res_31_V_d0; +output [2:0] res_32_V_address0; +output res_32_V_ce0; +output res_32_V_we0; +output [7:0] res_32_V_d0; +output [2:0] res_33_V_address0; +output res_33_V_ce0; +output res_33_V_we0; +output [7:0] res_33_V_d0; +output [2:0] res_34_V_address0; +output res_34_V_ce0; +output res_34_V_we0; +output [7:0] res_34_V_d0; +output [2:0] res_35_V_address0; +output res_35_V_ce0; +output res_35_V_we0; +output [7:0] res_35_V_d0; +output [2:0] res_36_V_address0; +output res_36_V_ce0; +output res_36_V_we0; +output [7:0] res_36_V_d0; +output [2:0] res_37_V_address0; +output res_37_V_ce0; +output res_37_V_we0; +output [7:0] res_37_V_d0; +output [2:0] res_38_V_address0; +output res_38_V_ce0; +output res_38_V_we0; +output [7:0] res_38_V_d0; +output [2:0] res_39_V_address0; +output res_39_V_ce0; +output res_39_V_we0; +output [7:0] res_39_V_d0; +output [2:0] res_40_V_address0; +output res_40_V_ce0; +output res_40_V_we0; +output [7:0] res_40_V_d0; +output [2:0] res_41_V_address0; +output res_41_V_ce0; +output res_41_V_we0; +output [7:0] res_41_V_d0; +output [2:0] res_42_V_address0; +output res_42_V_ce0; +output res_42_V_we0; +output [7:0] res_42_V_d0; +output [2:0] res_43_V_address0; +output res_43_V_ce0; +output res_43_V_we0; +output [7:0] res_43_V_d0; +output [2:0] res_44_V_address0; +output res_44_V_ce0; +output res_44_V_we0; +output [7:0] res_44_V_d0; +output [2:0] res_45_V_address0; +output res_45_V_ce0; +output res_45_V_we0; +output [7:0] res_45_V_d0; +output [2:0] res_46_V_address0; +output res_46_V_ce0; +output res_46_V_we0; +output [7:0] res_46_V_d0; +output [2:0] res_47_V_address0; +output res_47_V_ce0; +output res_47_V_we0; +output [7:0] res_47_V_d0; +output [2:0] res_48_V_address0; +output res_48_V_ce0; +output res_48_V_we0; +output [7:0] res_48_V_d0; +output [2:0] res_49_V_address0; +output res_49_V_ce0; +output res_49_V_we0; +output [7:0] res_49_V_d0; +output [2:0] res_50_V_address0; +output res_50_V_ce0; +output res_50_V_we0; +output [7:0] res_50_V_d0; +output [2:0] res_51_V_address0; +output res_51_V_ce0; +output res_51_V_we0; +output [7:0] res_51_V_d0; +output [2:0] res_52_V_address0; +output res_52_V_ce0; +output res_52_V_we0; +output [7:0] res_52_V_d0; +output [2:0] res_53_V_address0; +output res_53_V_ce0; +output res_53_V_we0; +output [7:0] res_53_V_d0; +output [2:0] res_54_V_address0; +output res_54_V_ce0; +output res_54_V_we0; +output [7:0] res_54_V_d0; +output [2:0] res_55_V_address0; +output res_55_V_ce0; +output res_55_V_we0; +output [7:0] res_55_V_d0; +output [2:0] res_56_V_address0; +output res_56_V_ce0; +output res_56_V_we0; +output [7:0] res_56_V_d0; +output [2:0] res_57_V_address0; +output res_57_V_ce0; +output res_57_V_we0; +output [7:0] res_57_V_d0; +output [2:0] res_58_V_address0; +output res_58_V_ce0; +output res_58_V_we0; +output [7:0] res_58_V_d0; +output [2:0] res_59_V_address0; +output res_59_V_ce0; +output res_59_V_we0; +output [7:0] res_59_V_d0; +output [2:0] res_60_V_address0; +output res_60_V_ce0; +output res_60_V_we0; +output [7:0] res_60_V_d0; +output [2:0] res_61_V_address0; +output res_61_V_ce0; +output res_61_V_we0; +output [7:0] res_61_V_d0; +output [2:0] res_62_V_address0; +output res_62_V_ce0; +output res_62_V_we0; +output [7:0] res_62_V_d0; +output [2:0] res_63_V_address0; +output res_63_V_ce0; +output res_63_V_we0; +output [7:0] res_63_V_d0; +output [2:0] res_64_V_address0; +output res_64_V_ce0; +output res_64_V_we0; +output [7:0] res_64_V_d0; +output [2:0] res_65_V_address0; +output res_65_V_ce0; +output res_65_V_we0; +output [7:0] res_65_V_d0; +output [2:0] res_66_V_address0; +output res_66_V_ce0; +output res_66_V_we0; +output [7:0] res_66_V_d0; +output [2:0] res_67_V_address0; +output res_67_V_ce0; +output res_67_V_we0; +output [7:0] res_67_V_d0; +output [2:0] res_68_V_address0; +output res_68_V_ce0; +output res_68_V_we0; +output [7:0] res_68_V_d0; +output [2:0] res_69_V_address0; +output res_69_V_ce0; +output res_69_V_we0; +output [7:0] res_69_V_d0; +output [2:0] res_70_V_address0; +output res_70_V_ce0; +output res_70_V_we0; +output [7:0] res_70_V_d0; +output [2:0] res_71_V_address0; +output res_71_V_ce0; +output res_71_V_we0; +output [7:0] res_71_V_d0; +output [2:0] res_72_V_address0; +output res_72_V_ce0; +output res_72_V_we0; +output [7:0] res_72_V_d0; +output [2:0] res_73_V_address0; +output res_73_V_ce0; +output res_73_V_we0; +output [7:0] res_73_V_d0; +output [2:0] res_74_V_address0; +output res_74_V_ce0; +output res_74_V_we0; +output [7:0] res_74_V_d0; +output [2:0] res_75_V_address0; +output res_75_V_ce0; +output res_75_V_we0; +output [7:0] res_75_V_d0; +output [1:0] res_76_V_address0; +output res_76_V_ce0; +output res_76_V_we0; +output [7:0] res_76_V_d0; +output [1:0] res_77_V_address0; +output res_77_V_ce0; +output res_77_V_we0; +output [7:0] res_77_V_d0; +output [1:0] res_78_V_address0; +output res_78_V_ce0; +output res_78_V_we0; +output [7:0] res_78_V_d0; +output [1:0] res_79_V_address0; +output res_79_V_ce0; +output res_79_V_we0; +output [7:0] res_79_V_d0; +output [1:0] res_80_V_address0; +output res_80_V_ce0; +output res_80_V_we0; +output [7:0] res_80_V_d0; +output [1:0] res_81_V_address0; +output res_81_V_ce0; +output res_81_V_we0; +output [7:0] res_81_V_d0; +output [1:0] res_82_V_address0; +output res_82_V_ce0; +output res_82_V_we0; +output [7:0] res_82_V_d0; +output [1:0] res_83_V_address0; +output res_83_V_ce0; +output res_83_V_we0; +output [7:0] res_83_V_d0; +output [1:0] res_84_V_address0; +output res_84_V_ce0; +output res_84_V_we0; +output [7:0] res_84_V_d0; +output [1:0] res_85_V_address0; +output res_85_V_ce0; +output res_85_V_we0; +output [7:0] res_85_V_d0; +output [1:0] res_86_V_address0; +output res_86_V_ce0; +output res_86_V_we0; +output [7:0] res_86_V_d0; +output [1:0] res_87_V_address0; +output res_87_V_ce0; +output res_87_V_we0; +output [7:0] res_87_V_d0; +output [1:0] res_88_V_address0; +output res_88_V_ce0; +output res_88_V_we0; +output [7:0] res_88_V_d0; +output [1:0] res_89_V_address0; +output res_89_V_ce0; +output res_89_V_we0; +output [7:0] res_89_V_d0; +output [1:0] res_90_V_address0; +output res_90_V_ce0; +output res_90_V_we0; +output [7:0] res_90_V_d0; +output [1:0] res_91_V_address0; +output res_91_V_ce0; +output res_91_V_we0; +output [7:0] res_91_V_d0; +output [1:0] res_92_V_address0; +output res_92_V_ce0; +output res_92_V_we0; +output [7:0] res_92_V_d0; +output [1:0] res_93_V_address0; +output res_93_V_ce0; +output res_93_V_we0; +output [7:0] res_93_V_d0; +output [1:0] res_94_V_address0; +output res_94_V_ce0; +output res_94_V_we0; +output [7:0] res_94_V_d0; +output [1:0] res_95_V_address0; +output res_95_V_ce0; +output res_95_V_we0; +output [7:0] res_95_V_d0; +output [1:0] res_96_V_address0; +output res_96_V_ce0; +output res_96_V_we0; +output [7:0] res_96_V_d0; +output [1:0] res_97_V_address0; +output res_97_V_ce0; +output res_97_V_we0; +output [7:0] res_97_V_d0; +output [1:0] res_98_V_address0; +output res_98_V_ce0; +output res_98_V_we0; +output [7:0] res_98_V_d0; +output [1:0] res_99_V_address0; +output res_99_V_ce0; +output res_99_V_we0; +output [7:0] res_99_V_d0; +output [1:0] res_100_V_address0; +output res_100_V_ce0; +output res_100_V_we0; +output [7:0] res_100_V_d0; +output [1:0] res_101_V_address0; +output res_101_V_ce0; +output res_101_V_we0; +output [7:0] res_101_V_d0; +output [1:0] res_102_V_address0; +output res_102_V_ce0; +output res_102_V_we0; +output [7:0] res_102_V_d0; +output [1:0] res_103_V_address0; +output res_103_V_ce0; +output res_103_V_we0; +output [7:0] res_103_V_d0; +output [1:0] res_104_V_address0; +output res_104_V_ce0; +output res_104_V_we0; +output [7:0] res_104_V_d0; +output [1:0] res_105_V_address0; +output res_105_V_ce0; +output res_105_V_we0; +output [7:0] res_105_V_d0; +output [1:0] res_106_V_address0; +output res_106_V_ce0; +output res_106_V_we0; +output [7:0] res_106_V_d0; +output [1:0] res_107_V_address0; +output res_107_V_ce0; +output res_107_V_we0; +output [7:0] res_107_V_d0; +output [1:0] res_108_V_address0; +output res_108_V_ce0; +output res_108_V_we0; +output [7:0] res_108_V_d0; +output [1:0] res_109_V_address0; +output res_109_V_ce0; +output res_109_V_we0; +output [7:0] res_109_V_d0; +output [1:0] res_110_V_address0; +output res_110_V_ce0; +output res_110_V_we0; +output [7:0] res_110_V_d0; +output [1:0] res_111_V_address0; +output res_111_V_ce0; +output res_111_V_we0; +output [7:0] res_111_V_d0; +output [1:0] res_112_V_address0; +output res_112_V_ce0; +output res_112_V_we0; +output [7:0] res_112_V_d0; +output [1:0] res_113_V_address0; +output res_113_V_ce0; +output res_113_V_we0; +output [7:0] res_113_V_d0; +output [1:0] res_114_V_address0; +output res_114_V_ce0; +output res_114_V_we0; +output [7:0] res_114_V_d0; +output [1:0] res_115_V_address0; +output res_115_V_ce0; +output res_115_V_we0; +output [7:0] res_115_V_d0; +output [1:0] res_116_V_address0; +output res_116_V_ce0; +output res_116_V_we0; +output [7:0] res_116_V_d0; +output [1:0] res_117_V_address0; +output res_117_V_ce0; +output res_117_V_we0; +output [7:0] res_117_V_d0; +output [1:0] res_118_V_address0; +output res_118_V_ce0; +output res_118_V_we0; +output [7:0] res_118_V_d0; +output [1:0] res_119_V_address0; +output res_119_V_ce0; +output res_119_V_we0; +output [7:0] res_119_V_d0; +output [1:0] res_120_V_address0; +output res_120_V_ce0; +output res_120_V_we0; +output [7:0] res_120_V_d0; +output [1:0] res_121_V_address0; +output res_121_V_ce0; +output res_121_V_we0; +output [7:0] res_121_V_d0; +output [1:0] res_122_V_address0; +output res_122_V_ce0; +output res_122_V_we0; +output [7:0] res_122_V_d0; +output [1:0] res_123_V_address0; +output res_123_V_ce0; +output res_123_V_we0; +output [7:0] res_123_V_d0; +output [1:0] res_124_V_address0; +output res_124_V_ce0; +output res_124_V_we0; +output [7:0] res_124_V_d0; +output [1:0] res_125_V_address0; +output res_125_V_ce0; +output res_125_V_we0; +output [7:0] res_125_V_d0; +output [1:0] res_126_V_address0; +output res_126_V_ce0; +output res_126_V_we0; +output [7:0] res_126_V_d0; +output [1:0] res_127_V_address0; +output res_127_V_ce0; +output res_127_V_we0; +output [7:0] res_127_V_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg data_0_V_ce0; +reg data_1_V_ce0; +reg data_2_V_ce0; +reg data_3_V_ce0; +reg data_4_V_ce0; +reg data_5_V_ce0; +reg data_6_V_ce0; +reg data_7_V_ce0; +reg data_8_V_ce0; +reg data_9_V_ce0; +reg data_10_V_ce0; +reg data_11_V_ce0; +reg data_12_V_ce0; +reg data_13_V_ce0; +reg data_14_V_ce0; +reg data_15_V_ce0; +reg data_16_V_ce0; +reg data_17_V_ce0; +reg data_18_V_ce0; +reg data_19_V_ce0; +reg data_20_V_ce0; +reg data_21_V_ce0; +reg data_22_V_ce0; +reg data_23_V_ce0; +reg data_24_V_ce0; +reg data_25_V_ce0; +reg data_26_V_ce0; +reg data_27_V_ce0; +reg data_28_V_ce0; +reg data_29_V_ce0; +reg data_30_V_ce0; +reg data_31_V_ce0; +reg data_32_V_ce0; +reg data_33_V_ce0; +reg data_34_V_ce0; +reg data_35_V_ce0; +reg data_36_V_ce0; +reg data_37_V_ce0; +reg data_38_V_ce0; +reg data_39_V_ce0; +reg data_40_V_ce0; +reg data_41_V_ce0; +reg data_42_V_ce0; +reg data_43_V_ce0; +reg data_44_V_ce0; +reg data_45_V_ce0; +reg data_46_V_ce0; +reg data_47_V_ce0; +reg data_48_V_ce0; +reg data_49_V_ce0; +reg data_50_V_ce0; +reg data_51_V_ce0; +reg data_52_V_ce0; +reg data_53_V_ce0; +reg data_54_V_ce0; +reg data_55_V_ce0; +reg data_56_V_ce0; +reg data_57_V_ce0; +reg data_58_V_ce0; +reg data_59_V_ce0; +reg data_60_V_ce0; +reg data_61_V_ce0; +reg data_62_V_ce0; +reg data_63_V_ce0; +reg data_64_V_ce0; +reg data_65_V_ce0; +reg data_66_V_ce0; +reg data_67_V_ce0; +reg data_68_V_ce0; +reg data_69_V_ce0; +reg data_70_V_ce0; +reg data_71_V_ce0; +reg data_72_V_ce0; +reg data_73_V_ce0; +reg data_74_V_ce0; +reg data_75_V_ce0; +reg data_76_V_ce0; +reg data_77_V_ce0; +reg data_78_V_ce0; +reg data_79_V_ce0; +reg data_80_V_ce0; +reg data_81_V_ce0; +reg data_82_V_ce0; +reg data_83_V_ce0; +reg data_84_V_ce0; +reg data_85_V_ce0; +reg data_86_V_ce0; +reg data_87_V_ce0; +reg data_88_V_ce0; +reg data_89_V_ce0; +reg data_90_V_ce0; +reg data_91_V_ce0; +reg data_92_V_ce0; +reg data_93_V_ce0; +reg data_94_V_ce0; +reg data_95_V_ce0; +reg data_96_V_ce0; +reg data_97_V_ce0; +reg data_98_V_ce0; +reg data_99_V_ce0; +reg data_100_V_ce0; +reg data_101_V_ce0; +reg data_102_V_ce0; +reg data_103_V_ce0; +reg data_104_V_ce0; +reg data_105_V_ce0; +reg data_106_V_ce0; +reg data_107_V_ce0; +reg data_108_V_ce0; +reg data_109_V_ce0; +reg data_110_V_ce0; +reg data_111_V_ce0; +reg data_112_V_ce0; +reg data_113_V_ce0; +reg data_114_V_ce0; +reg data_115_V_ce0; +reg data_116_V_ce0; +reg data_117_V_ce0; +reg data_118_V_ce0; +reg data_119_V_ce0; +reg data_120_V_ce0; +reg data_121_V_ce0; +reg data_122_V_ce0; +reg data_123_V_ce0; +reg data_124_V_ce0; +reg data_125_V_ce0; +reg data_126_V_ce0; +reg data_127_V_ce0; +reg res_0_V_ce0; +reg res_0_V_we0; +reg res_1_V_ce0; +reg res_1_V_we0; +reg res_2_V_ce0; +reg res_2_V_we0; +reg res_3_V_ce0; +reg res_3_V_we0; +reg res_4_V_ce0; +reg res_4_V_we0; +reg res_5_V_ce0; +reg res_5_V_we0; +reg res_6_V_ce0; +reg res_6_V_we0; +reg res_7_V_ce0; +reg res_7_V_we0; +reg res_8_V_ce0; +reg res_8_V_we0; +reg res_9_V_ce0; +reg res_9_V_we0; +reg res_10_V_ce0; +reg res_10_V_we0; +reg res_11_V_ce0; +reg res_11_V_we0; +reg res_12_V_ce0; +reg res_12_V_we0; +reg res_13_V_ce0; +reg res_13_V_we0; +reg res_14_V_ce0; +reg res_14_V_we0; +reg res_15_V_ce0; +reg res_15_V_we0; +reg res_16_V_ce0; +reg res_16_V_we0; +reg res_17_V_ce0; +reg res_17_V_we0; +reg res_18_V_ce0; +reg res_18_V_we0; +reg res_19_V_ce0; +reg res_19_V_we0; +reg res_20_V_ce0; +reg res_20_V_we0; +reg res_21_V_ce0; +reg res_21_V_we0; +reg res_22_V_ce0; +reg res_22_V_we0; +reg res_23_V_ce0; +reg res_23_V_we0; +reg res_24_V_ce0; +reg res_24_V_we0; +reg res_25_V_ce0; +reg res_25_V_we0; +reg res_26_V_ce0; +reg res_26_V_we0; +reg res_27_V_ce0; +reg res_27_V_we0; +reg res_28_V_ce0; +reg res_28_V_we0; +reg res_29_V_ce0; +reg res_29_V_we0; +reg res_30_V_ce0; +reg res_30_V_we0; +reg res_31_V_ce0; +reg res_31_V_we0; +reg res_32_V_ce0; +reg res_32_V_we0; +reg res_33_V_ce0; +reg res_33_V_we0; +reg res_34_V_ce0; +reg res_34_V_we0; +reg res_35_V_ce0; +reg res_35_V_we0; +reg res_36_V_ce0; +reg res_36_V_we0; +reg res_37_V_ce0; +reg res_37_V_we0; +reg res_38_V_ce0; +reg res_38_V_we0; +reg res_39_V_ce0; +reg res_39_V_we0; +reg res_40_V_ce0; +reg res_40_V_we0; +reg res_41_V_ce0; +reg res_41_V_we0; +reg res_42_V_ce0; +reg res_42_V_we0; +reg res_43_V_ce0; +reg res_43_V_we0; +reg res_44_V_ce0; +reg res_44_V_we0; +reg res_45_V_ce0; +reg res_45_V_we0; +reg res_46_V_ce0; +reg res_46_V_we0; +reg res_47_V_ce0; +reg res_47_V_we0; +reg res_48_V_ce0; +reg res_48_V_we0; +reg res_49_V_ce0; +reg res_49_V_we0; +reg res_50_V_ce0; +reg res_50_V_we0; +reg res_51_V_ce0; +reg res_51_V_we0; +reg res_52_V_ce0; +reg res_52_V_we0; +reg res_53_V_ce0; +reg res_53_V_we0; +reg res_54_V_ce0; +reg res_54_V_we0; +reg res_55_V_ce0; +reg res_55_V_we0; +reg res_56_V_ce0; +reg res_56_V_we0; +reg res_57_V_ce0; +reg res_57_V_we0; +reg res_58_V_ce0; +reg res_58_V_we0; +reg res_59_V_ce0; +reg res_59_V_we0; +reg res_60_V_ce0; +reg res_60_V_we0; +reg res_61_V_ce0; +reg res_61_V_we0; +reg res_62_V_ce0; +reg res_62_V_we0; +reg res_63_V_ce0; +reg res_63_V_we0; +reg res_64_V_ce0; +reg res_64_V_we0; +reg res_65_V_ce0; +reg res_65_V_we0; +reg res_66_V_ce0; +reg res_66_V_we0; +reg res_67_V_ce0; +reg res_67_V_we0; +reg res_68_V_ce0; +reg res_68_V_we0; +reg res_69_V_ce0; +reg res_69_V_we0; +reg res_70_V_ce0; +reg res_70_V_we0; +reg res_71_V_ce0; +reg res_71_V_we0; +reg res_72_V_ce0; +reg res_72_V_we0; +reg res_73_V_ce0; +reg res_73_V_we0; +reg res_74_V_ce0; +reg res_74_V_we0; +reg res_75_V_ce0; +reg res_75_V_we0; +reg res_76_V_ce0; +reg res_76_V_we0; +reg res_77_V_ce0; +reg res_77_V_we0; +reg res_78_V_ce0; +reg res_78_V_we0; +reg res_79_V_ce0; +reg res_79_V_we0; +reg res_80_V_ce0; +reg res_80_V_we0; +reg res_81_V_ce0; +reg res_81_V_we0; +reg res_82_V_ce0; +reg res_82_V_we0; +reg res_83_V_ce0; +reg res_83_V_we0; +reg res_84_V_ce0; +reg res_84_V_we0; +reg res_85_V_ce0; +reg res_85_V_we0; +reg res_86_V_ce0; +reg res_86_V_we0; +reg res_87_V_ce0; +reg res_87_V_we0; +reg res_88_V_ce0; +reg res_88_V_we0; +reg res_89_V_ce0; +reg res_89_V_we0; +reg res_90_V_ce0; +reg res_90_V_we0; +reg res_91_V_ce0; +reg res_91_V_we0; +reg res_92_V_ce0; +reg res_92_V_we0; +reg res_93_V_ce0; +reg res_93_V_we0; +reg res_94_V_ce0; +reg res_94_V_we0; +reg res_95_V_ce0; +reg res_95_V_we0; +reg res_96_V_ce0; +reg res_96_V_we0; +reg res_97_V_ce0; +reg res_97_V_we0; +reg res_98_V_ce0; +reg res_98_V_we0; +reg res_99_V_ce0; +reg res_99_V_we0; +reg res_100_V_ce0; +reg res_100_V_we0; +reg res_101_V_ce0; +reg res_101_V_we0; +reg res_102_V_ce0; +reg res_102_V_we0; +reg res_103_V_ce0; +reg res_103_V_we0; +reg res_104_V_ce0; +reg res_104_V_we0; +reg res_105_V_ce0; +reg res_105_V_we0; +reg res_106_V_ce0; +reg res_106_V_we0; +reg res_107_V_ce0; +reg res_107_V_we0; +reg res_108_V_ce0; +reg res_108_V_we0; +reg res_109_V_ce0; +reg res_109_V_we0; +reg res_110_V_ce0; +reg res_110_V_we0; +reg res_111_V_ce0; +reg res_111_V_we0; +reg res_112_V_ce0; +reg res_112_V_we0; +reg res_113_V_ce0; +reg res_113_V_we0; +reg res_114_V_ce0; +reg res_114_V_we0; +reg res_115_V_ce0; +reg res_115_V_we0; +reg res_116_V_ce0; +reg res_116_V_we0; +reg res_117_V_ce0; +reg res_117_V_we0; +reg res_118_V_ce0; +reg res_118_V_we0; +reg res_119_V_ce0; +reg res_119_V_we0; +reg res_120_V_ce0; +reg res_120_V_we0; +reg res_121_V_ce0; +reg res_121_V_we0; +reg res_122_V_ce0; +reg res_122_V_we0; +reg res_123_V_ce0; +reg res_123_V_we0; +reg res_124_V_ce0; +reg res_124_V_we0; +reg res_125_V_ce0; +reg res_125_V_we0; +reg res_126_V_ce0; +reg res_126_V_we0; +reg res_127_V_ce0; +reg res_127_V_we0; + + reg [3:0] ap_CS_fsm; +wire [9:0] zext_ln209_fu_4677_p1; +reg [9:0] zext_ln209_reg_5258; +wire [11:0] zext_ln209_1_fu_4681_p1; +reg [11:0] zext_ln209_1_reg_5263; +wire [3:0] ff_fu_4691_p2; +reg [3:0] ff_reg_5271; +wire [10:0] zext_ln233_fu_4717_p1; +reg [10:0] zext_ln233_reg_5279; +wire [0:0] icmp_ln211_fu_4697_p2; +wire [6:0] trunc_ln233_fu_4720_p1; +reg [6:0] trunc_ln233_reg_5284; +wire [3:0] ii_fu_4729_p2; +wire [0:0] icmp_ln213_fu_4723_p2; +wire [1:0] kk_fu_4745_p2; +reg [1:0] kk_reg_5300; +wire [3:0] add_ln221_fu_4751_p2; +reg [3:0] add_ln221_reg_5305; +wire [0:0] icmp_ln218_fu_4739_p2; +wire [0:0] icmp_ln221_fu_4760_p2; +reg [0:0] icmp_ln221_reg_5311; +wire [1:0] shl_ln223_fu_4765_p2; +reg [1:0] shl_ln223_reg_5315; +wire [12:0] zext_ln225_1_fu_4771_p1; +reg [12:0] zext_ln225_1_reg_5320; +wire [6:0] trunc_ln225_fu_4774_p1; +reg [6:0] trunc_ln225_reg_5325; +wire [1:0] ll_fu_4787_p2; +reg [1:0] ll_reg_5333; +wire [0:0] icmp_ln221_1_fu_4799_p2; +reg [0:0] icmp_ln221_1_reg_5338; +wire [0:0] icmp_ln220_fu_4781_p2; +wire [1:0] grp_fu_4672_p2; +reg [1:0] add_ln225_reg_5342; +wire [6:0] add_ln203_1_fu_4848_p2; +reg [6:0] add_ln203_1_reg_5347; +reg [5:0] trunc_ln203_1_reg_5351; +wire [63:0] zext_ln225_fu_4868_p1; +reg [63:0] zext_ln225_reg_5356; +reg [7:0] data_126_V_load_reg_6001; +reg [7:0] data_125_V_load_reg_6006; +reg [7:0] data_124_V_load_reg_6011; +reg [7:0] data_123_V_load_reg_6016; +reg [7:0] data_122_V_load_reg_6021; +reg [7:0] data_121_V_load_reg_6026; +reg [7:0] data_120_V_load_reg_6031; +reg [7:0] data_119_V_load_reg_6036; +reg [7:0] data_118_V_load_reg_6041; +reg [7:0] data_117_V_load_reg_6046; +reg [7:0] data_116_V_load_reg_6051; +reg [7:0] data_115_V_load_reg_6056; +reg [7:0] data_114_V_load_reg_6061; +reg [7:0] data_113_V_load_reg_6066; +reg [7:0] data_112_V_load_reg_6071; +reg [7:0] data_111_V_load_reg_6076; +reg [7:0] data_110_V_load_reg_6081; +reg [7:0] data_109_V_load_reg_6086; +reg [7:0] data_108_V_load_reg_6091; +reg [7:0] data_107_V_load_reg_6096; +reg [7:0] data_106_V_load_reg_6101; +reg [7:0] data_105_V_load_reg_6106; +reg [7:0] data_104_V_load_reg_6111; +reg [7:0] data_103_V_load_reg_6116; +reg [7:0] data_102_V_load_reg_6121; +reg [7:0] data_101_V_load_reg_6126; +reg [7:0] data_100_V_load_reg_6131; +reg [7:0] data_99_V_load_reg_6136; +reg [7:0] data_98_V_load_reg_6141; +reg [7:0] data_97_V_load_reg_6146; +reg [7:0] data_96_V_load_reg_6151; +reg [7:0] data_95_V_load_reg_6156; +reg [7:0] data_94_V_load_reg_6161; +reg [7:0] data_93_V_load_reg_6166; +reg [7:0] data_92_V_load_reg_6171; +reg [7:0] data_91_V_load_reg_6176; +reg [7:0] data_90_V_load_reg_6181; +reg [7:0] data_89_V_load_reg_6186; +reg [7:0] data_88_V_load_reg_6191; +reg [7:0] data_87_V_load_reg_6196; +reg [7:0] data_86_V_load_reg_6201; +reg [7:0] data_85_V_load_reg_6206; +reg [7:0] data_84_V_load_reg_6211; +reg [7:0] data_83_V_load_reg_6216; +reg [7:0] data_82_V_load_reg_6221; +reg [7:0] data_81_V_load_reg_6226; +reg [7:0] data_80_V_load_reg_6231; +reg [7:0] data_79_V_load_reg_6236; +reg [7:0] data_78_V_load_reg_6241; +reg [7:0] data_77_V_load_reg_6246; +reg [7:0] data_76_V_load_reg_6251; +reg [7:0] data_75_V_load_reg_6256; +reg [7:0] data_74_V_load_reg_6261; +reg [7:0] data_73_V_load_reg_6266; +reg [7:0] data_72_V_load_reg_6271; +reg [7:0] data_71_V_load_reg_6276; +reg [7:0] data_70_V_load_reg_6281; +reg [7:0] data_69_V_load_reg_6286; +reg [7:0] data_68_V_load_reg_6291; +reg [7:0] data_67_V_load_reg_6296; +reg [7:0] data_66_V_load_reg_6301; +reg [7:0] data_65_V_load_reg_6306; +reg [7:0] data_64_V_load_reg_6311; +reg [7:0] data_63_V_load_reg_6316; +reg [7:0] data_62_V_load_reg_6321; +reg [7:0] data_61_V_load_reg_6326; +reg [7:0] data_60_V_load_reg_6331; +reg [7:0] data_59_V_load_reg_6336; +reg [7:0] data_58_V_load_reg_6341; +reg [7:0] data_57_V_load_reg_6346; +reg [7:0] data_56_V_load_reg_6351; +reg [7:0] data_55_V_load_reg_6356; +reg [7:0] data_54_V_load_reg_6361; +reg [7:0] data_53_V_load_reg_6366; +reg [7:0] data_52_V_load_reg_6371; +reg [7:0] data_51_V_load_reg_6376; +reg [7:0] data_50_V_load_reg_6381; +reg [7:0] data_49_V_load_reg_6386; +reg [7:0] data_48_V_load_reg_6391; +reg [7:0] data_47_V_load_reg_6396; +reg [7:0] data_46_V_load_reg_6401; +reg [7:0] data_45_V_load_reg_6406; +reg [7:0] data_44_V_load_reg_6411; +reg [7:0] data_43_V_load_reg_6416; +reg [7:0] data_42_V_load_reg_6421; +reg [7:0] data_41_V_load_reg_6426; +reg [7:0] data_40_V_load_reg_6431; +reg [7:0] data_39_V_load_reg_6436; +reg [7:0] data_38_V_load_reg_6441; +reg [7:0] data_37_V_load_reg_6446; +reg [7:0] data_36_V_load_reg_6451; +reg [7:0] data_35_V_load_reg_6456; +reg [7:0] data_34_V_load_reg_6461; +reg [7:0] data_33_V_load_reg_6466; +reg [7:0] data_32_V_load_reg_6471; +reg [7:0] data_31_V_load_reg_6476; +reg [7:0] data_30_V_load_reg_6481; +reg [7:0] data_29_V_load_reg_6486; +reg [7:0] data_28_V_load_reg_6491; +reg [7:0] data_27_V_load_reg_6496; +reg [7:0] data_26_V_load_reg_6501; +reg [7:0] data_25_V_load_reg_6506; +reg [7:0] data_24_V_load_reg_6511; +reg [7:0] data_23_V_load_reg_6516; +reg [7:0] data_22_V_load_reg_6521; +reg [7:0] data_21_V_load_reg_6526; +reg [7:0] data_20_V_load_reg_6531; +reg [7:0] data_19_V_load_reg_6536; +reg [7:0] data_18_V_load_reg_6541; +reg [7:0] data_17_V_load_reg_6546; +reg [7:0] data_16_V_load_reg_6551; +reg [7:0] data_15_V_load_reg_6556; +reg [7:0] data_14_V_load_reg_6561; +reg [7:0] data_13_V_load_reg_6566; +reg [7:0] data_12_V_load_reg_6571; +reg [7:0] data_11_V_load_reg_6576; +reg [7:0] data_10_V_load_reg_6581; +reg [7:0] data_9_V_load_reg_6586; +reg [7:0] data_8_V_load_reg_6591; +reg [7:0] data_7_V_load_reg_6596; +reg [7:0] data_6_V_load_reg_6601; +reg [7:0] data_5_V_load_reg_6606; +reg [7:0] data_4_V_load_reg_6611; +reg [7:0] data_3_V_load_reg_6616; +reg [7:0] data_2_V_load_reg_6621; +reg [7:0] data_1_V_load_reg_6626; +reg [7:0] data_0_V_load_reg_6631; +reg [7:0] data_127_V_load_reg_6636; +wire [6:0] trunc_ln233_1_fu_5040_p1; +reg [6:0] trunc_ln233_1_reg_6641; +wire [10:0] add_ln233_1_fu_5044_p2; +reg [10:0] add_ln233_1_reg_6646; +wire [7:0] pool_V_q0; +wire [0:0] icmp_ln13_fu_5049_p2; +wire [2:0] i_fu_5060_p2; +reg [2:0] i_reg_6664; +wire [7:0] y_V_1_fu_5221_p3; +wire [3:0] jj_fu_5229_p2; +reg [1:0] pool_V_address0; +reg pool_V_ce0; +reg pool_V_we0; +reg [7:0] pool_V_d0; +reg [3:0] ff_0_reg_4203; +reg [3:0] ii_0_reg_4214; +wire [0:0] icmp_ln209_fu_4685_p2; +reg [3:0] jj_0_reg_4226; +reg [1:0] kk_0_reg_4238; +reg [1:0] ll_0_reg_4250; +reg [7:0] phi_ln203_reg_4261; +reg [7:0] agg_result_V_0_i_i_reg_4523; +reg [2:0] i_0_i_i_reg_4661; +wire [63:0] zext_ln223_fu_4863_p1; +wire [63:0] zext_ln203_1_fu_4874_p1; +wire [63:0] zext_ln14_fu_5055_p1; +wire [63:0] zext_ln203_fu_5083_p1; +wire [6:0] add_ln203_fu_5066_p2; +wire [2:0] lshr_ln_fu_4703_p4; +wire [9:0] grp_fu_5235_p3; +wire [3:0] zext_ln218_fu_4735_p1; +wire [11:0] grp_fu_5244_p3; +wire [3:0] zext_ln220_1_fu_4777_p1; +wire [3:0] add_ln221_1_fu_4793_p2; +wire [7:0] shl_ln2_fu_4805_p3; +wire [5:0] shl_ln225_1_fu_4817_p3; +wire [8:0] zext_ln225_2_fu_4813_p1; +wire [8:0] zext_ln225_3_fu_4825_p1; +wire [8:0] sub_ln225_fu_4829_p2; +wire [12:0] sext_ln225_fu_4835_p1; +wire [6:0] trunc_ln225_1_fu_4839_p1; +wire [12:0] add_ln225_2_fu_4843_p2; +wire [24:0] sext_ln203_1_fu_4871_p1; +wire [6:0] shl_ln_fu_5006_p3; +wire [4:0] shl_ln233_1_fu_5018_p3; +wire [7:0] zext_ln233_1_fu_5014_p1; +wire [7:0] zext_ln233_2_fu_5026_p1; +wire [7:0] sub_ln233_fu_5030_p2; +wire [10:0] sext_ln233_fu_5036_p1; +wire [3:0] trunc_ln2_fu_5070_p4; +wire [24:0] sext_ln203_fu_5079_p1; +wire [0:0] icmp_ln1494_fu_5215_p2; +wire [7:0] grp_fu_5235_p0; +wire [2:0] grp_fu_5235_p1; +wire [3:0] grp_fu_5235_p2; +wire [8:0] grp_fu_5244_p0; +wire [3:0] grp_fu_5244_p1; +wire [3:0] grp_fu_5244_p2; +reg [3:0] ap_NS_fsm; +wire [9:0] grp_fu_5235_p10; +wire [11:0] grp_fu_5244_p10; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 4'd0; +end + +pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config4_s_pool_V #( + .DataWidth( 8 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +pool_V_U( + .clk(ap_clk), + .reset(ap_rst), + .address0(pool_V_address0), + .ce0(pool_V_ce0), + .we0(pool_V_we0), + .d0(pool_V_d0), + .q0(pool_V_q0) +); + +myproject_mac_muladd_8ns_3ns_4ns_10_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 8 ), + .din1_WIDTH( 3 ), + .din2_WIDTH( 4 ), + .dout_WIDTH( 10 )) +myproject_mac_muladd_8ns_3ns_4ns_10_1_1_U1182( + .din0(grp_fu_5235_p0), + .din1(grp_fu_5235_p1), + .din2(grp_fu_5235_p2), + .dout(grp_fu_5235_p3) +); + +myproject_mac_muladd_9ns_4ns_4ns_12_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 9 ), + .din1_WIDTH( 4 ), + .din2_WIDTH( 4 ), + .dout_WIDTH( 12 )) +myproject_mac_muladd_9ns_4ns_4ns_12_1_1_U1183( + .din0(grp_fu_5244_p0), + .din1(grp_fu_5244_p1), + .din2(grp_fu_5244_p2), + .dout(grp_fu_5244_p3) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state14 == ap_CS_fsm)) begin + agg_result_V_0_i_i_reg_4523 <= y_V_1_fu_5221_p3; + end else if ((ap_ST_fsm_state12 == ap_CS_fsm)) begin + agg_result_V_0_i_i_reg_4523 <= pool_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln211_fu_4697_p2 == 1'd1))) begin + ff_0_reg_4203 <= ff_reg_5271; + end else if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b1))) begin + ff_0_reg_4203 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state14 == ap_CS_fsm)) begin + i_0_i_i_reg_4661 <= i_reg_6664; + end else if ((ap_ST_fsm_state12 == ap_CS_fsm)) begin + i_0_i_i_reg_4661 <= 3'd1; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state2 == ap_CS_fsm) & (icmp_ln209_fu_4685_p2 == 1'd0))) begin + ii_0_reg_4214 <= 4'd0; + end else if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln213_fu_4723_p2 == 1'd1))) begin + ii_0_reg_4214 <= ii_fu_4729_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln211_fu_4697_p2 == 1'd0))) begin + jj_0_reg_4226 <= 4'd0; + end else if ((ap_ST_fsm_state15 == ap_CS_fsm)) begin + jj_0_reg_4226 <= jj_fu_5229_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln213_fu_4723_p2 == 1'd0))) begin + kk_0_reg_4238 <= 2'd0; + end else if (((ap_ST_fsm_state7 == ap_CS_fsm) & (icmp_ln220_fu_4781_p2 == 1'd1))) begin + kk_0_reg_4238 <= kk_reg_5300; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + ll_0_reg_4250 <= 2'd0; + end else if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + ll_0_reg_4250 <= ll_reg_5333; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state10 == ap_CS_fsm)) begin + if ((7'd127 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_127_V_load_reg_6636; + end else if ((7'd126 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_126_V_load_reg_6001; + end else if ((7'd125 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_125_V_load_reg_6006; + end else if ((7'd124 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_124_V_load_reg_6011; + end else if ((7'd123 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_123_V_load_reg_6016; + end else if ((7'd122 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_122_V_load_reg_6021; + end else if ((7'd121 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_121_V_load_reg_6026; + end else if ((7'd120 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_120_V_load_reg_6031; + end else if ((7'd119 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_119_V_load_reg_6036; + end else if ((7'd118 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_118_V_load_reg_6041; + end else if ((7'd117 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_117_V_load_reg_6046; + end else if ((7'd116 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_116_V_load_reg_6051; + end else if ((7'd115 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_115_V_load_reg_6056; + end else if ((7'd114 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_114_V_load_reg_6061; + end else if ((7'd113 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_113_V_load_reg_6066; + end else if ((7'd112 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_112_V_load_reg_6071; + end else if ((7'd111 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_111_V_load_reg_6076; + end else if ((7'd110 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_110_V_load_reg_6081; + end else if ((7'd109 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_109_V_load_reg_6086; + end else if ((7'd108 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_108_V_load_reg_6091; + end else if ((7'd107 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_107_V_load_reg_6096; + end else if ((7'd106 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_106_V_load_reg_6101; + end else if ((7'd105 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_105_V_load_reg_6106; + end else if ((7'd104 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_104_V_load_reg_6111; + end else if ((7'd103 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_103_V_load_reg_6116; + end else if ((7'd102 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_102_V_load_reg_6121; + end else if ((7'd101 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_101_V_load_reg_6126; + end else if ((7'd100 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_100_V_load_reg_6131; + end else if ((7'd99 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_99_V_load_reg_6136; + end else if ((7'd98 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_98_V_load_reg_6141; + end else if ((7'd97 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_97_V_load_reg_6146; + end else if ((7'd96 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_96_V_load_reg_6151; + end else if ((7'd95 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_95_V_load_reg_6156; + end else if ((7'd94 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_94_V_load_reg_6161; + end else if ((7'd93 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_93_V_load_reg_6166; + end else if ((7'd92 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_92_V_load_reg_6171; + end else if ((7'd91 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_91_V_load_reg_6176; + end else if ((7'd90 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_90_V_load_reg_6181; + end else if ((7'd89 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_89_V_load_reg_6186; + end else if ((7'd88 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_88_V_load_reg_6191; + end else if ((7'd87 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_87_V_load_reg_6196; + end else if ((7'd86 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_86_V_load_reg_6201; + end else if ((7'd85 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_85_V_load_reg_6206; + end else if ((7'd84 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_84_V_load_reg_6211; + end else if ((7'd83 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_83_V_load_reg_6216; + end else if ((7'd82 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_82_V_load_reg_6221; + end else if ((7'd81 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_81_V_load_reg_6226; + end else if ((7'd80 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_80_V_load_reg_6231; + end else if ((7'd79 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_79_V_load_reg_6236; + end else if ((7'd78 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_78_V_load_reg_6241; + end else if ((7'd77 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_77_V_load_reg_6246; + end else if ((7'd76 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_76_V_load_reg_6251; + end else if ((7'd75 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_75_V_load_reg_6256; + end else if ((7'd74 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_74_V_load_reg_6261; + end else if ((7'd73 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_73_V_load_reg_6266; + end else if ((7'd72 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_72_V_load_reg_6271; + end else if ((7'd71 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_71_V_load_reg_6276; + end else if ((7'd70 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_70_V_load_reg_6281; + end else if ((7'd69 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_69_V_load_reg_6286; + end else if ((7'd68 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_68_V_load_reg_6291; + end else if ((7'd67 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_67_V_load_reg_6296; + end else if ((7'd66 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_66_V_load_reg_6301; + end else if ((7'd65 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_65_V_load_reg_6306; + end else if ((7'd64 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_64_V_load_reg_6311; + end else if ((7'd63 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_63_V_load_reg_6316; + end else if ((7'd62 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_62_V_load_reg_6321; + end else if ((7'd61 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_61_V_load_reg_6326; + end else if ((7'd60 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_60_V_load_reg_6331; + end else if ((7'd59 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_59_V_load_reg_6336; + end else if ((7'd58 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_58_V_load_reg_6341; + end else if ((7'd57 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_57_V_load_reg_6346; + end else if ((7'd56 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_56_V_load_reg_6351; + end else if ((7'd55 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_55_V_load_reg_6356; + end else if ((7'd54 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_54_V_load_reg_6361; + end else if ((7'd53 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_53_V_load_reg_6366; + end else if ((7'd52 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_52_V_load_reg_6371; + end else if ((7'd51 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_51_V_load_reg_6376; + end else if ((7'd50 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_50_V_load_reg_6381; + end else if ((7'd49 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_49_V_load_reg_6386; + end else if ((7'd48 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_48_V_load_reg_6391; + end else if ((7'd47 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_47_V_load_reg_6396; + end else if ((7'd46 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_46_V_load_reg_6401; + end else if ((7'd45 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_45_V_load_reg_6406; + end else if ((7'd44 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_44_V_load_reg_6411; + end else if ((7'd43 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_43_V_load_reg_6416; + end else if ((7'd42 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_42_V_load_reg_6421; + end else if ((7'd41 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_41_V_load_reg_6426; + end else if ((7'd40 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_40_V_load_reg_6431; + end else if ((7'd39 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_39_V_load_reg_6436; + end else if ((7'd38 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_38_V_load_reg_6441; + end else if ((7'd37 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_37_V_load_reg_6446; + end else if ((7'd36 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_36_V_load_reg_6451; + end else if ((7'd35 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_35_V_load_reg_6456; + end else if ((7'd34 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_34_V_load_reg_6461; + end else if ((7'd33 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_33_V_load_reg_6466; + end else if ((7'd32 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_32_V_load_reg_6471; + end else if ((7'd31 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_31_V_load_reg_6476; + end else if ((7'd30 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_30_V_load_reg_6481; + end else if ((7'd29 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_29_V_load_reg_6486; + end else if ((7'd28 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_28_V_load_reg_6491; + end else if ((7'd27 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_27_V_load_reg_6496; + end else if ((7'd26 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_26_V_load_reg_6501; + end else if ((7'd25 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_25_V_load_reg_6506; + end else if ((7'd24 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_24_V_load_reg_6511; + end else if ((7'd23 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_23_V_load_reg_6516; + end else if ((7'd22 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_22_V_load_reg_6521; + end else if ((7'd21 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_21_V_load_reg_6526; + end else if ((7'd20 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_20_V_load_reg_6531; + end else if ((7'd19 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_19_V_load_reg_6536; + end else if ((7'd18 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_18_V_load_reg_6541; + end else if ((7'd17 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_17_V_load_reg_6546; + end else if ((7'd16 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_16_V_load_reg_6551; + end else if ((7'd15 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_15_V_load_reg_6556; + end else if ((7'd14 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_14_V_load_reg_6561; + end else if ((7'd13 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_13_V_load_reg_6566; + end else if ((7'd12 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_12_V_load_reg_6571; + end else if ((7'd11 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_11_V_load_reg_6576; + end else if ((7'd10 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_10_V_load_reg_6581; + end else if ((7'd9 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_9_V_load_reg_6586; + end else if ((7'd8 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_8_V_load_reg_6591; + end else if ((7'd7 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_7_V_load_reg_6596; + end else if ((7'd6 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_6_V_load_reg_6601; + end else if ((7'd5 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_5_V_load_reg_6606; + end else if ((7'd4 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_4_V_load_reg_6611; + end else if ((7'd3 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_3_V_load_reg_6616; + end else if ((7'd2 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_2_V_load_reg_6621; + end else if ((7'd1 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_1_V_load_reg_6626; + end else if ((7'd0 == add_ln203_1_reg_5347)) begin + phi_ln203_reg_4261 <= data_0_V_load_reg_6631; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (icmp_ln220_fu_4781_p2 == 1'd0) & (icmp_ln221_1_fu_4799_p2 == 1'd0) & (icmp_ln221_reg_5311 == 1'd0))) begin + add_ln203_1_reg_5347 <= add_ln203_1_fu_4848_p2; + add_ln225_reg_5342 <= grp_fu_4672_p2; + trunc_ln203_1_reg_5351 <= {{add_ln225_2_fu_4843_p2[12:7]}}; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state5 == ap_CS_fsm) & (icmp_ln218_fu_4739_p2 == 1'd0))) begin + add_ln221_reg_5305 <= add_ln221_fu_4751_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state12 == ap_CS_fsm)) begin + add_ln233_1_reg_6646 <= add_ln233_1_fu_5044_p2; + trunc_ln233_1_reg_6641[6 : 1] <= trunc_ln233_1_fu_5040_p1[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if (((7'd0 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_0_V_load_reg_6631 <= data_0_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd100 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_100_V_load_reg_6131 <= data_100_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd101 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_101_V_load_reg_6126 <= data_101_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd102 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_102_V_load_reg_6121 <= data_102_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd103 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_103_V_load_reg_6116 <= data_103_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd104 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_104_V_load_reg_6111 <= data_104_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd105 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_105_V_load_reg_6106 <= data_105_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd106 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_106_V_load_reg_6101 <= data_106_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd107 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_107_V_load_reg_6096 <= data_107_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd108 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_108_V_load_reg_6091 <= data_108_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd109 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_109_V_load_reg_6086 <= data_109_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd10 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_10_V_load_reg_6581 <= data_10_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd110 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_110_V_load_reg_6081 <= data_110_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd111 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_111_V_load_reg_6076 <= data_111_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd112 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_112_V_load_reg_6071 <= data_112_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd113 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_113_V_load_reg_6066 <= data_113_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd114 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_114_V_load_reg_6061 <= data_114_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd115 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_115_V_load_reg_6056 <= data_115_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd116 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_116_V_load_reg_6051 <= data_116_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd117 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_117_V_load_reg_6046 <= data_117_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd118 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_118_V_load_reg_6041 <= data_118_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd119 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_119_V_load_reg_6036 <= data_119_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd11 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_11_V_load_reg_6576 <= data_11_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd120 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_120_V_load_reg_6031 <= data_120_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd121 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_121_V_load_reg_6026 <= data_121_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd122 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_122_V_load_reg_6021 <= data_122_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd123 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_123_V_load_reg_6016 <= data_123_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd124 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_124_V_load_reg_6011 <= data_124_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd125 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_125_V_load_reg_6006 <= data_125_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd126 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_126_V_load_reg_6001 <= data_126_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd127 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_127_V_load_reg_6636 <= data_127_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd12 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_12_V_load_reg_6571 <= data_12_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd13 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_13_V_load_reg_6566 <= data_13_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd14 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_14_V_load_reg_6561 <= data_14_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd15 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_15_V_load_reg_6556 <= data_15_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd16 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_16_V_load_reg_6551 <= data_16_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd17 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_17_V_load_reg_6546 <= data_17_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd18 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_18_V_load_reg_6541 <= data_18_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd19 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_19_V_load_reg_6536 <= data_19_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd1 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_1_V_load_reg_6626 <= data_1_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd20 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_20_V_load_reg_6531 <= data_20_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd21 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_21_V_load_reg_6526 <= data_21_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd22 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_22_V_load_reg_6521 <= data_22_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd23 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_23_V_load_reg_6516 <= data_23_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd24 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_24_V_load_reg_6511 <= data_24_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd25 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_25_V_load_reg_6506 <= data_25_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd26 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_26_V_load_reg_6501 <= data_26_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd27 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_27_V_load_reg_6496 <= data_27_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd28 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_28_V_load_reg_6491 <= data_28_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd29 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_29_V_load_reg_6486 <= data_29_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd2 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_2_V_load_reg_6621 <= data_2_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd30 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_30_V_load_reg_6481 <= data_30_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd31 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_31_V_load_reg_6476 <= data_31_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd32 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_32_V_load_reg_6471 <= data_32_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd33 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_33_V_load_reg_6466 <= data_33_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd34 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_34_V_load_reg_6461 <= data_34_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd35 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_35_V_load_reg_6456 <= data_35_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd36 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_36_V_load_reg_6451 <= data_36_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd37 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_37_V_load_reg_6446 <= data_37_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd38 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_38_V_load_reg_6441 <= data_38_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd39 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_39_V_load_reg_6436 <= data_39_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd3 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_3_V_load_reg_6616 <= data_3_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd40 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_40_V_load_reg_6431 <= data_40_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd41 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_41_V_load_reg_6426 <= data_41_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd42 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_42_V_load_reg_6421 <= data_42_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd43 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_43_V_load_reg_6416 <= data_43_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd44 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_44_V_load_reg_6411 <= data_44_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd45 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_45_V_load_reg_6406 <= data_45_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd46 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_46_V_load_reg_6401 <= data_46_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd47 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_47_V_load_reg_6396 <= data_47_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd48 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_48_V_load_reg_6391 <= data_48_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd49 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_49_V_load_reg_6386 <= data_49_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd4 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_4_V_load_reg_6611 <= data_4_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd50 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_50_V_load_reg_6381 <= data_50_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd51 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_51_V_load_reg_6376 <= data_51_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd52 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_52_V_load_reg_6371 <= data_52_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd53 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_53_V_load_reg_6366 <= data_53_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd54 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_54_V_load_reg_6361 <= data_54_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd55 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_55_V_load_reg_6356 <= data_55_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd56 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_56_V_load_reg_6351 <= data_56_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd57 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_57_V_load_reg_6346 <= data_57_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd58 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_58_V_load_reg_6341 <= data_58_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd59 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_59_V_load_reg_6336 <= data_59_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd5 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_5_V_load_reg_6606 <= data_5_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd60 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_60_V_load_reg_6331 <= data_60_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd61 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_61_V_load_reg_6326 <= data_61_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd62 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_62_V_load_reg_6321 <= data_62_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd63 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_63_V_load_reg_6316 <= data_63_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd64 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_64_V_load_reg_6311 <= data_64_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd65 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_65_V_load_reg_6306 <= data_65_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd66 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_66_V_load_reg_6301 <= data_66_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd67 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_67_V_load_reg_6296 <= data_67_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd68 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_68_V_load_reg_6291 <= data_68_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd69 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_69_V_load_reg_6286 <= data_69_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd6 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_6_V_load_reg_6601 <= data_6_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd70 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_70_V_load_reg_6281 <= data_70_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd71 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_71_V_load_reg_6276 <= data_71_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd72 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_72_V_load_reg_6271 <= data_72_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd73 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_73_V_load_reg_6266 <= data_73_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd74 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_74_V_load_reg_6261 <= data_74_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd75 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_75_V_load_reg_6256 <= data_75_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd76 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_76_V_load_reg_6251 <= data_76_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd77 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_77_V_load_reg_6246 <= data_77_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd78 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_78_V_load_reg_6241 <= data_78_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd79 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_79_V_load_reg_6236 <= data_79_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd7 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_7_V_load_reg_6596 <= data_7_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd80 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_80_V_load_reg_6231 <= data_80_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd81 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_81_V_load_reg_6226 <= data_81_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd82 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_82_V_load_reg_6221 <= data_82_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd83 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_83_V_load_reg_6216 <= data_83_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd84 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_84_V_load_reg_6211 <= data_84_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd85 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_85_V_load_reg_6206 <= data_85_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd86 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_86_V_load_reg_6201 <= data_86_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd87 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_87_V_load_reg_6196 <= data_87_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd88 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_88_V_load_reg_6191 <= data_88_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd89 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_89_V_load_reg_6186 <= data_89_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd8 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_8_V_load_reg_6591 <= data_8_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd90 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_90_V_load_reg_6181 <= data_90_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd91 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_91_V_load_reg_6176 <= data_91_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd92 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_92_V_load_reg_6171 <= data_92_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd93 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_93_V_load_reg_6166 <= data_93_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd94 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_94_V_load_reg_6161 <= data_94_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd95 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_95_V_load_reg_6156 <= data_95_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd96 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_96_V_load_reg_6151 <= data_96_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd97 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_97_V_load_reg_6146 <= data_97_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd98 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_98_V_load_reg_6141 <= data_98_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd99 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_99_V_load_reg_6136 <= data_99_V_q0; + end +end + +always @ (posedge ap_clk) begin + if (((7'd9 == add_ln203_1_reg_5347) & (ap_ST_fsm_state9 == ap_CS_fsm))) begin + data_9_V_load_reg_6586 <= data_9_V_q0; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state2 == ap_CS_fsm)) begin + ff_reg_5271 <= ff_fu_4691_p2; + zext_ln209_1_reg_5263[3 : 0] <= zext_ln209_1_fu_4681_p1[3 : 0]; + zext_ln209_reg_5258[3 : 0] <= zext_ln209_fu_4677_p1[3 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln13_fu_5049_p2 == 1'd0) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + i_reg_6664 <= i_fu_5060_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (icmp_ln220_fu_4781_p2 == 1'd0) & (icmp_ln221_reg_5311 == 1'd0))) begin + icmp_ln221_1_reg_5338 <= icmp_ln221_1_fu_4799_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state6 == ap_CS_fsm)) begin + icmp_ln221_reg_5311 <= icmp_ln221_fu_4760_p2; + shl_ln223_reg_5315[1] <= shl_ln223_fu_4765_p2[1]; + trunc_ln225_reg_5325 <= trunc_ln225_fu_4774_p1; + zext_ln225_1_reg_5320[11 : 0] <= zext_ln225_1_fu_4771_p1[11 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state5 == ap_CS_fsm)) begin + kk_reg_5300 <= kk_fu_4745_p2; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state7 == ap_CS_fsm)) begin + ll_reg_5333 <= ll_fu_4787_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln211_fu_4697_p2 == 1'd0))) begin + trunc_ln233_reg_5284 <= trunc_ln233_fu_4720_p1; + zext_ln233_reg_5279[9 : 0] <= zext_ln233_fu_4717_p1[9 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + zext_ln225_reg_5356[1 : 0] <= zext_ln225_fu_4868_p1[1 : 0]; + end +end + +always @ (*) begin + if ((((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0)) | ((ap_ST_fsm_state2 == ap_CS_fsm) & (icmp_ln209_fu_4685_p2 == 1'd1)))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state2 == ap_CS_fsm) & (icmp_ln209_fu_4685_p2 == 1'd1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_0_V_ce0 = 1'b1; + end else begin + data_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_100_V_ce0 = 1'b1; + end else begin + data_100_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_101_V_ce0 = 1'b1; + end else begin + data_101_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_102_V_ce0 = 1'b1; + end else begin + data_102_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_103_V_ce0 = 1'b1; + end else begin + data_103_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_104_V_ce0 = 1'b1; + end else begin + data_104_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_105_V_ce0 = 1'b1; + end else begin + data_105_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_106_V_ce0 = 1'b1; + end else begin + data_106_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_107_V_ce0 = 1'b1; + end else begin + data_107_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_108_V_ce0 = 1'b1; + end else begin + data_108_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_109_V_ce0 = 1'b1; + end else begin + data_109_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_10_V_ce0 = 1'b1; + end else begin + data_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_110_V_ce0 = 1'b1; + end else begin + data_110_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_111_V_ce0 = 1'b1; + end else begin + data_111_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_112_V_ce0 = 1'b1; + end else begin + data_112_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_113_V_ce0 = 1'b1; + end else begin + data_113_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_114_V_ce0 = 1'b1; + end else begin + data_114_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_115_V_ce0 = 1'b1; + end else begin + data_115_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_116_V_ce0 = 1'b1; + end else begin + data_116_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_117_V_ce0 = 1'b1; + end else begin + data_117_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_118_V_ce0 = 1'b1; + end else begin + data_118_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_119_V_ce0 = 1'b1; + end else begin + data_119_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_11_V_ce0 = 1'b1; + end else begin + data_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_120_V_ce0 = 1'b1; + end else begin + data_120_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_121_V_ce0 = 1'b1; + end else begin + data_121_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_122_V_ce0 = 1'b1; + end else begin + data_122_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_123_V_ce0 = 1'b1; + end else begin + data_123_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_124_V_ce0 = 1'b1; + end else begin + data_124_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_125_V_ce0 = 1'b1; + end else begin + data_125_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_126_V_ce0 = 1'b1; + end else begin + data_126_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_127_V_ce0 = 1'b1; + end else begin + data_127_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_12_V_ce0 = 1'b1; + end else begin + data_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_13_V_ce0 = 1'b1; + end else begin + data_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_14_V_ce0 = 1'b1; + end else begin + data_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_15_V_ce0 = 1'b1; + end else begin + data_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_16_V_ce0 = 1'b1; + end else begin + data_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_17_V_ce0 = 1'b1; + end else begin + data_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_18_V_ce0 = 1'b1; + end else begin + data_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_19_V_ce0 = 1'b1; + end else begin + data_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_1_V_ce0 = 1'b1; + end else begin + data_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_20_V_ce0 = 1'b1; + end else begin + data_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_21_V_ce0 = 1'b1; + end else begin + data_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_22_V_ce0 = 1'b1; + end else begin + data_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_23_V_ce0 = 1'b1; + end else begin + data_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_24_V_ce0 = 1'b1; + end else begin + data_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_25_V_ce0 = 1'b1; + end else begin + data_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_26_V_ce0 = 1'b1; + end else begin + data_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_27_V_ce0 = 1'b1; + end else begin + data_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_28_V_ce0 = 1'b1; + end else begin + data_28_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_29_V_ce0 = 1'b1; + end else begin + data_29_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_2_V_ce0 = 1'b1; + end else begin + data_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_30_V_ce0 = 1'b1; + end else begin + data_30_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_31_V_ce0 = 1'b1; + end else begin + data_31_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_32_V_ce0 = 1'b1; + end else begin + data_32_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_33_V_ce0 = 1'b1; + end else begin + data_33_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_34_V_ce0 = 1'b1; + end else begin + data_34_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_35_V_ce0 = 1'b1; + end else begin + data_35_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_36_V_ce0 = 1'b1; + end else begin + data_36_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_37_V_ce0 = 1'b1; + end else begin + data_37_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_38_V_ce0 = 1'b1; + end else begin + data_38_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_39_V_ce0 = 1'b1; + end else begin + data_39_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_3_V_ce0 = 1'b1; + end else begin + data_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_40_V_ce0 = 1'b1; + end else begin + data_40_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_41_V_ce0 = 1'b1; + end else begin + data_41_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_42_V_ce0 = 1'b1; + end else begin + data_42_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_43_V_ce0 = 1'b1; + end else begin + data_43_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_44_V_ce0 = 1'b1; + end else begin + data_44_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_45_V_ce0 = 1'b1; + end else begin + data_45_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_46_V_ce0 = 1'b1; + end else begin + data_46_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_47_V_ce0 = 1'b1; + end else begin + data_47_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_48_V_ce0 = 1'b1; + end else begin + data_48_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_49_V_ce0 = 1'b1; + end else begin + data_49_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_4_V_ce0 = 1'b1; + end else begin + data_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_50_V_ce0 = 1'b1; + end else begin + data_50_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_51_V_ce0 = 1'b1; + end else begin + data_51_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_52_V_ce0 = 1'b1; + end else begin + data_52_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_53_V_ce0 = 1'b1; + end else begin + data_53_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_54_V_ce0 = 1'b1; + end else begin + data_54_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_55_V_ce0 = 1'b1; + end else begin + data_55_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_56_V_ce0 = 1'b1; + end else begin + data_56_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_57_V_ce0 = 1'b1; + end else begin + data_57_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_58_V_ce0 = 1'b1; + end else begin + data_58_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_59_V_ce0 = 1'b1; + end else begin + data_59_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_5_V_ce0 = 1'b1; + end else begin + data_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_60_V_ce0 = 1'b1; + end else begin + data_60_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_61_V_ce0 = 1'b1; + end else begin + data_61_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_62_V_ce0 = 1'b1; + end else begin + data_62_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_63_V_ce0 = 1'b1; + end else begin + data_63_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_64_V_ce0 = 1'b1; + end else begin + data_64_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_65_V_ce0 = 1'b1; + end else begin + data_65_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_66_V_ce0 = 1'b1; + end else begin + data_66_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_67_V_ce0 = 1'b1; + end else begin + data_67_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_68_V_ce0 = 1'b1; + end else begin + data_68_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_69_V_ce0 = 1'b1; + end else begin + data_69_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_6_V_ce0 = 1'b1; + end else begin + data_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_70_V_ce0 = 1'b1; + end else begin + data_70_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_71_V_ce0 = 1'b1; + end else begin + data_71_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_72_V_ce0 = 1'b1; + end else begin + data_72_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_73_V_ce0 = 1'b1; + end else begin + data_73_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_74_V_ce0 = 1'b1; + end else begin + data_74_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_75_V_ce0 = 1'b1; + end else begin + data_75_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_76_V_ce0 = 1'b1; + end else begin + data_76_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_77_V_ce0 = 1'b1; + end else begin + data_77_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_78_V_ce0 = 1'b1; + end else begin + data_78_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_79_V_ce0 = 1'b1; + end else begin + data_79_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_7_V_ce0 = 1'b1; + end else begin + data_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_80_V_ce0 = 1'b1; + end else begin + data_80_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_81_V_ce0 = 1'b1; + end else begin + data_81_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_82_V_ce0 = 1'b1; + end else begin + data_82_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_83_V_ce0 = 1'b1; + end else begin + data_83_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_84_V_ce0 = 1'b1; + end else begin + data_84_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_85_V_ce0 = 1'b1; + end else begin + data_85_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_86_V_ce0 = 1'b1; + end else begin + data_86_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_87_V_ce0 = 1'b1; + end else begin + data_87_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_88_V_ce0 = 1'b1; + end else begin + data_88_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_89_V_ce0 = 1'b1; + end else begin + data_89_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_8_V_ce0 = 1'b1; + end else begin + data_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_90_V_ce0 = 1'b1; + end else begin + data_90_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_91_V_ce0 = 1'b1; + end else begin + data_91_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_92_V_ce0 = 1'b1; + end else begin + data_92_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_93_V_ce0 = 1'b1; + end else begin + data_93_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_94_V_ce0 = 1'b1; + end else begin + data_94_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_95_V_ce0 = 1'b1; + end else begin + data_95_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_96_V_ce0 = 1'b1; + end else begin + data_96_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_97_V_ce0 = 1'b1; + end else begin + data_97_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_98_V_ce0 = 1'b1; + end else begin + data_98_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_99_V_ce0 = 1'b1; + end else begin + data_99_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state8 == ap_CS_fsm)) begin + data_9_V_ce0 = 1'b1; + end else begin + data_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + pool_V_address0 = zext_ln14_fu_5055_p1; + end else if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + pool_V_address0 = zext_ln225_reg_5356; + end else if ((ap_ST_fsm_state7 == ap_CS_fsm)) begin + pool_V_address0 = zext_ln223_fu_4863_p1; + end else if ((ap_ST_fsm_state5 == ap_CS_fsm)) begin + pool_V_address0 = 64'd0; + end else begin + pool_V_address0 = 'b0; + end +end + +always @ (*) begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) | (ap_ST_fsm_state5 == ap_CS_fsm) | (ap_ST_fsm_state13 == ap_CS_fsm) | (ap_ST_fsm_state11 == ap_CS_fsm))) begin + pool_V_ce0 = 1'b1; + end else begin + pool_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state11 == ap_CS_fsm)) begin + pool_V_d0 = phi_ln203_reg_4261; + end else if ((ap_ST_fsm_state7 == ap_CS_fsm)) begin + pool_V_d0 = 8'd128; + end else begin + pool_V_d0 = 'b0; + end +end + +always @ (*) begin + if ((((icmp_ln221_1_reg_5338 == 1'd0) & (icmp_ln221_reg_5311 == 1'd0) & (ap_ST_fsm_state11 == ap_CS_fsm)) | ((ap_ST_fsm_state7 == ap_CS_fsm) & (((icmp_ln221_reg_5311 == 1'd1) & (icmp_ln220_fu_4781_p2 == 1'd0)) | ((icmp_ln221_1_fu_4799_p2 == 1'd1) & (icmp_ln220_fu_4781_p2 == 1'd0)))))) begin + pool_V_we0 = 1'b1; + end else begin + pool_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_0_V_ce0 = 1'b1; + end else begin + res_0_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd0 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_0_V_we0 = 1'b1; + end else begin + res_0_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_100_V_ce0 = 1'b1; + end else begin + res_100_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd100 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_100_V_we0 = 1'b1; + end else begin + res_100_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_101_V_ce0 = 1'b1; + end else begin + res_101_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd101 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_101_V_we0 = 1'b1; + end else begin + res_101_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_102_V_ce0 = 1'b1; + end else begin + res_102_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd102 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_102_V_we0 = 1'b1; + end else begin + res_102_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_103_V_ce0 = 1'b1; + end else begin + res_103_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd103 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_103_V_we0 = 1'b1; + end else begin + res_103_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_104_V_ce0 = 1'b1; + end else begin + res_104_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd104 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_104_V_we0 = 1'b1; + end else begin + res_104_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_105_V_ce0 = 1'b1; + end else begin + res_105_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd105 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_105_V_we0 = 1'b1; + end else begin + res_105_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_106_V_ce0 = 1'b1; + end else begin + res_106_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd106 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_106_V_we0 = 1'b1; + end else begin + res_106_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_107_V_ce0 = 1'b1; + end else begin + res_107_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd107 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_107_V_we0 = 1'b1; + end else begin + res_107_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_108_V_ce0 = 1'b1; + end else begin + res_108_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd108 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_108_V_we0 = 1'b1; + end else begin + res_108_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_109_V_ce0 = 1'b1; + end else begin + res_109_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd109 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_109_V_we0 = 1'b1; + end else begin + res_109_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_10_V_ce0 = 1'b1; + end else begin + res_10_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd10 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_10_V_we0 = 1'b1; + end else begin + res_10_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_110_V_ce0 = 1'b1; + end else begin + res_110_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd110 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_110_V_we0 = 1'b1; + end else begin + res_110_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_111_V_ce0 = 1'b1; + end else begin + res_111_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd111 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_111_V_we0 = 1'b1; + end else begin + res_111_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_112_V_ce0 = 1'b1; + end else begin + res_112_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd112 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_112_V_we0 = 1'b1; + end else begin + res_112_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_113_V_ce0 = 1'b1; + end else begin + res_113_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd113 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_113_V_we0 = 1'b1; + end else begin + res_113_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_114_V_ce0 = 1'b1; + end else begin + res_114_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd114 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_114_V_we0 = 1'b1; + end else begin + res_114_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_115_V_ce0 = 1'b1; + end else begin + res_115_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd115 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_115_V_we0 = 1'b1; + end else begin + res_115_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_116_V_ce0 = 1'b1; + end else begin + res_116_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd116 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_116_V_we0 = 1'b1; + end else begin + res_116_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_117_V_ce0 = 1'b1; + end else begin + res_117_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd117 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_117_V_we0 = 1'b1; + end else begin + res_117_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_118_V_ce0 = 1'b1; + end else begin + res_118_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd118 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_118_V_we0 = 1'b1; + end else begin + res_118_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_119_V_ce0 = 1'b1; + end else begin + res_119_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd119 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_119_V_we0 = 1'b1; + end else begin + res_119_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_11_V_ce0 = 1'b1; + end else begin + res_11_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd11 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_11_V_we0 = 1'b1; + end else begin + res_11_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_120_V_ce0 = 1'b1; + end else begin + res_120_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd120 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_120_V_we0 = 1'b1; + end else begin + res_120_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_121_V_ce0 = 1'b1; + end else begin + res_121_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd121 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_121_V_we0 = 1'b1; + end else begin + res_121_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_122_V_ce0 = 1'b1; + end else begin + res_122_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd122 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_122_V_we0 = 1'b1; + end else begin + res_122_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_123_V_ce0 = 1'b1; + end else begin + res_123_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd123 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_123_V_we0 = 1'b1; + end else begin + res_123_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_124_V_ce0 = 1'b1; + end else begin + res_124_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd124 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_124_V_we0 = 1'b1; + end else begin + res_124_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_125_V_ce0 = 1'b1; + end else begin + res_125_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd125 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_125_V_we0 = 1'b1; + end else begin + res_125_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_126_V_ce0 = 1'b1; + end else begin + res_126_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd126 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_126_V_we0 = 1'b1; + end else begin + res_126_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_127_V_ce0 = 1'b1; + end else begin + res_127_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd127 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_127_V_we0 = 1'b1; + end else begin + res_127_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_12_V_ce0 = 1'b1; + end else begin + res_12_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd12 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_12_V_we0 = 1'b1; + end else begin + res_12_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_13_V_ce0 = 1'b1; + end else begin + res_13_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd13 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_13_V_we0 = 1'b1; + end else begin + res_13_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_14_V_ce0 = 1'b1; + end else begin + res_14_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd14 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_14_V_we0 = 1'b1; + end else begin + res_14_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_15_V_ce0 = 1'b1; + end else begin + res_15_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd15 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_15_V_we0 = 1'b1; + end else begin + res_15_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_16_V_ce0 = 1'b1; + end else begin + res_16_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd16 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_16_V_we0 = 1'b1; + end else begin + res_16_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_17_V_ce0 = 1'b1; + end else begin + res_17_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd17 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_17_V_we0 = 1'b1; + end else begin + res_17_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_18_V_ce0 = 1'b1; + end else begin + res_18_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd18 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_18_V_we0 = 1'b1; + end else begin + res_18_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_19_V_ce0 = 1'b1; + end else begin + res_19_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd19 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_19_V_we0 = 1'b1; + end else begin + res_19_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_1_V_ce0 = 1'b1; + end else begin + res_1_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd1 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_1_V_we0 = 1'b1; + end else begin + res_1_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_20_V_ce0 = 1'b1; + end else begin + res_20_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd20 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_20_V_we0 = 1'b1; + end else begin + res_20_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_21_V_ce0 = 1'b1; + end else begin + res_21_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd21 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_21_V_we0 = 1'b1; + end else begin + res_21_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_22_V_ce0 = 1'b1; + end else begin + res_22_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd22 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_22_V_we0 = 1'b1; + end else begin + res_22_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_23_V_ce0 = 1'b1; + end else begin + res_23_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd23 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_23_V_we0 = 1'b1; + end else begin + res_23_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_24_V_ce0 = 1'b1; + end else begin + res_24_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd24 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_24_V_we0 = 1'b1; + end else begin + res_24_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_25_V_ce0 = 1'b1; + end else begin + res_25_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd25 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_25_V_we0 = 1'b1; + end else begin + res_25_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_26_V_ce0 = 1'b1; + end else begin + res_26_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd26 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_26_V_we0 = 1'b1; + end else begin + res_26_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_27_V_ce0 = 1'b1; + end else begin + res_27_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd27 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_27_V_we0 = 1'b1; + end else begin + res_27_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_28_V_ce0 = 1'b1; + end else begin + res_28_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd28 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_28_V_we0 = 1'b1; + end else begin + res_28_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_29_V_ce0 = 1'b1; + end else begin + res_29_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd29 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_29_V_we0 = 1'b1; + end else begin + res_29_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_2_V_ce0 = 1'b1; + end else begin + res_2_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd2 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_2_V_we0 = 1'b1; + end else begin + res_2_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_30_V_ce0 = 1'b1; + end else begin + res_30_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd30 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_30_V_we0 = 1'b1; + end else begin + res_30_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_31_V_ce0 = 1'b1; + end else begin + res_31_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd31 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_31_V_we0 = 1'b1; + end else begin + res_31_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_32_V_ce0 = 1'b1; + end else begin + res_32_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd32 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_32_V_we0 = 1'b1; + end else begin + res_32_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_33_V_ce0 = 1'b1; + end else begin + res_33_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd33 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_33_V_we0 = 1'b1; + end else begin + res_33_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_34_V_ce0 = 1'b1; + end else begin + res_34_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd34 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_34_V_we0 = 1'b1; + end else begin + res_34_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_35_V_ce0 = 1'b1; + end else begin + res_35_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd35 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_35_V_we0 = 1'b1; + end else begin + res_35_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_36_V_ce0 = 1'b1; + end else begin + res_36_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd36 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_36_V_we0 = 1'b1; + end else begin + res_36_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_37_V_ce0 = 1'b1; + end else begin + res_37_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd37 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_37_V_we0 = 1'b1; + end else begin + res_37_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_38_V_ce0 = 1'b1; + end else begin + res_38_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd38 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_38_V_we0 = 1'b1; + end else begin + res_38_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_39_V_ce0 = 1'b1; + end else begin + res_39_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd39 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_39_V_we0 = 1'b1; + end else begin + res_39_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_3_V_ce0 = 1'b1; + end else begin + res_3_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd3 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_3_V_we0 = 1'b1; + end else begin + res_3_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_40_V_ce0 = 1'b1; + end else begin + res_40_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd40 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_40_V_we0 = 1'b1; + end else begin + res_40_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_41_V_ce0 = 1'b1; + end else begin + res_41_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd41 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_41_V_we0 = 1'b1; + end else begin + res_41_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_42_V_ce0 = 1'b1; + end else begin + res_42_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd42 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_42_V_we0 = 1'b1; + end else begin + res_42_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_43_V_ce0 = 1'b1; + end else begin + res_43_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd43 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_43_V_we0 = 1'b1; + end else begin + res_43_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_44_V_ce0 = 1'b1; + end else begin + res_44_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd44 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_44_V_we0 = 1'b1; + end else begin + res_44_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_45_V_ce0 = 1'b1; + end else begin + res_45_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd45 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_45_V_we0 = 1'b1; + end else begin + res_45_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_46_V_ce0 = 1'b1; + end else begin + res_46_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd46 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_46_V_we0 = 1'b1; + end else begin + res_46_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_47_V_ce0 = 1'b1; + end else begin + res_47_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd47 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_47_V_we0 = 1'b1; + end else begin + res_47_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_48_V_ce0 = 1'b1; + end else begin + res_48_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd48 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_48_V_we0 = 1'b1; + end else begin + res_48_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_49_V_ce0 = 1'b1; + end else begin + res_49_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd49 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_49_V_we0 = 1'b1; + end else begin + res_49_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_4_V_ce0 = 1'b1; + end else begin + res_4_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd4 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_4_V_we0 = 1'b1; + end else begin + res_4_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_50_V_ce0 = 1'b1; + end else begin + res_50_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd50 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_50_V_we0 = 1'b1; + end else begin + res_50_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_51_V_ce0 = 1'b1; + end else begin + res_51_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd51 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_51_V_we0 = 1'b1; + end else begin + res_51_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_52_V_ce0 = 1'b1; + end else begin + res_52_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd52 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_52_V_we0 = 1'b1; + end else begin + res_52_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_53_V_ce0 = 1'b1; + end else begin + res_53_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd53 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_53_V_we0 = 1'b1; + end else begin + res_53_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_54_V_ce0 = 1'b1; + end else begin + res_54_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd54 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_54_V_we0 = 1'b1; + end else begin + res_54_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_55_V_ce0 = 1'b1; + end else begin + res_55_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd55 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_55_V_we0 = 1'b1; + end else begin + res_55_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_56_V_ce0 = 1'b1; + end else begin + res_56_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd56 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_56_V_we0 = 1'b1; + end else begin + res_56_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_57_V_ce0 = 1'b1; + end else begin + res_57_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd57 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_57_V_we0 = 1'b1; + end else begin + res_57_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_58_V_ce0 = 1'b1; + end else begin + res_58_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd58 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_58_V_we0 = 1'b1; + end else begin + res_58_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_59_V_ce0 = 1'b1; + end else begin + res_59_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd59 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_59_V_we0 = 1'b1; + end else begin + res_59_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_5_V_ce0 = 1'b1; + end else begin + res_5_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd5 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_5_V_we0 = 1'b1; + end else begin + res_5_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_60_V_ce0 = 1'b1; + end else begin + res_60_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd60 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_60_V_we0 = 1'b1; + end else begin + res_60_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_61_V_ce0 = 1'b1; + end else begin + res_61_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd61 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_61_V_we0 = 1'b1; + end else begin + res_61_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_62_V_ce0 = 1'b1; + end else begin + res_62_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd62 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_62_V_we0 = 1'b1; + end else begin + res_62_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_63_V_ce0 = 1'b1; + end else begin + res_63_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd63 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_63_V_we0 = 1'b1; + end else begin + res_63_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_64_V_ce0 = 1'b1; + end else begin + res_64_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd64 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_64_V_we0 = 1'b1; + end else begin + res_64_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_65_V_ce0 = 1'b1; + end else begin + res_65_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd65 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_65_V_we0 = 1'b1; + end else begin + res_65_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_66_V_ce0 = 1'b1; + end else begin + res_66_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd66 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_66_V_we0 = 1'b1; + end else begin + res_66_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_67_V_ce0 = 1'b1; + end else begin + res_67_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd67 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_67_V_we0 = 1'b1; + end else begin + res_67_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_68_V_ce0 = 1'b1; + end else begin + res_68_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd68 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_68_V_we0 = 1'b1; + end else begin + res_68_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_69_V_ce0 = 1'b1; + end else begin + res_69_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd69 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_69_V_we0 = 1'b1; + end else begin + res_69_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_6_V_ce0 = 1'b1; + end else begin + res_6_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd6 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_6_V_we0 = 1'b1; + end else begin + res_6_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_70_V_ce0 = 1'b1; + end else begin + res_70_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd70 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_70_V_we0 = 1'b1; + end else begin + res_70_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_71_V_ce0 = 1'b1; + end else begin + res_71_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd71 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_71_V_we0 = 1'b1; + end else begin + res_71_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_72_V_ce0 = 1'b1; + end else begin + res_72_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd72 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_72_V_we0 = 1'b1; + end else begin + res_72_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_73_V_ce0 = 1'b1; + end else begin + res_73_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd73 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_73_V_we0 = 1'b1; + end else begin + res_73_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_74_V_ce0 = 1'b1; + end else begin + res_74_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd74 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_74_V_we0 = 1'b1; + end else begin + res_74_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_75_V_ce0 = 1'b1; + end else begin + res_75_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd75 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_75_V_we0 = 1'b1; + end else begin + res_75_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_76_V_ce0 = 1'b1; + end else begin + res_76_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd76 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_76_V_we0 = 1'b1; + end else begin + res_76_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_77_V_ce0 = 1'b1; + end else begin + res_77_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd77 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_77_V_we0 = 1'b1; + end else begin + res_77_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_78_V_ce0 = 1'b1; + end else begin + res_78_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd78 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_78_V_we0 = 1'b1; + end else begin + res_78_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_79_V_ce0 = 1'b1; + end else begin + res_79_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd79 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_79_V_we0 = 1'b1; + end else begin + res_79_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_7_V_ce0 = 1'b1; + end else begin + res_7_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd7 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_7_V_we0 = 1'b1; + end else begin + res_7_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_80_V_ce0 = 1'b1; + end else begin + res_80_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd80 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_80_V_we0 = 1'b1; + end else begin + res_80_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_81_V_ce0 = 1'b1; + end else begin + res_81_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd81 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_81_V_we0 = 1'b1; + end else begin + res_81_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_82_V_ce0 = 1'b1; + end else begin + res_82_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd82 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_82_V_we0 = 1'b1; + end else begin + res_82_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_83_V_ce0 = 1'b1; + end else begin + res_83_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd83 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_83_V_we0 = 1'b1; + end else begin + res_83_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_84_V_ce0 = 1'b1; + end else begin + res_84_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd84 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_84_V_we0 = 1'b1; + end else begin + res_84_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_85_V_ce0 = 1'b1; + end else begin + res_85_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd85 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_85_V_we0 = 1'b1; + end else begin + res_85_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_86_V_ce0 = 1'b1; + end else begin + res_86_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd86 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_86_V_we0 = 1'b1; + end else begin + res_86_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_87_V_ce0 = 1'b1; + end else begin + res_87_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd87 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_87_V_we0 = 1'b1; + end else begin + res_87_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_88_V_ce0 = 1'b1; + end else begin + res_88_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd88 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_88_V_we0 = 1'b1; + end else begin + res_88_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_89_V_ce0 = 1'b1; + end else begin + res_89_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd89 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_89_V_we0 = 1'b1; + end else begin + res_89_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_8_V_ce0 = 1'b1; + end else begin + res_8_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd8 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_8_V_we0 = 1'b1; + end else begin + res_8_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_90_V_ce0 = 1'b1; + end else begin + res_90_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd90 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_90_V_we0 = 1'b1; + end else begin + res_90_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_91_V_ce0 = 1'b1; + end else begin + res_91_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd91 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_91_V_we0 = 1'b1; + end else begin + res_91_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_92_V_ce0 = 1'b1; + end else begin + res_92_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd92 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_92_V_we0 = 1'b1; + end else begin + res_92_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_93_V_ce0 = 1'b1; + end else begin + res_93_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd93 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_93_V_we0 = 1'b1; + end else begin + res_93_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_94_V_ce0 = 1'b1; + end else begin + res_94_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd94 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_94_V_we0 = 1'b1; + end else begin + res_94_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_95_V_ce0 = 1'b1; + end else begin + res_95_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd95 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_95_V_we0 = 1'b1; + end else begin + res_95_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_96_V_ce0 = 1'b1; + end else begin + res_96_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd96 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_96_V_we0 = 1'b1; + end else begin + res_96_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_97_V_ce0 = 1'b1; + end else begin + res_97_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd97 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_97_V_we0 = 1'b1; + end else begin + res_97_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_98_V_ce0 = 1'b1; + end else begin + res_98_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd98 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_98_V_we0 = 1'b1; + end else begin + res_98_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_99_V_ce0 = 1'b1; + end else begin + res_99_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd99 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_99_V_we0 = 1'b1; + end else begin + res_99_V_we0 = 1'b0; + end +end + +always @ (*) begin + if ((ap_ST_fsm_state13 == ap_CS_fsm)) begin + res_9_V_ce0 = 1'b1; + end else begin + res_9_V_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((7'd9 == add_ln203_fu_5066_p2) & (icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + res_9_V_we0 = 1'b1; + end else begin + res_9_V_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if (((ap_ST_fsm_state1 == ap_CS_fsm) & (ap_start == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((ap_ST_fsm_state2 == ap_CS_fsm) & (icmp_ln209_fu_4685_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + if (((ap_ST_fsm_state3 == ap_CS_fsm) & (icmp_ln211_fu_4697_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + ap_ST_fsm_state4 : begin + if (((ap_ST_fsm_state4 == ap_CS_fsm) & (icmp_ln213_fu_4723_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state3; + end else begin + ap_NS_fsm = ap_ST_fsm_state5; + end + end + ap_ST_fsm_state5 : begin + if (((ap_ST_fsm_state5 == ap_CS_fsm) & (icmp_ln218_fu_4739_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_state6; + end + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + if (((ap_ST_fsm_state7 == ap_CS_fsm) & (icmp_ln220_fu_4781_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state5; + end else if (((ap_ST_fsm_state7 == ap_CS_fsm) & (((icmp_ln221_reg_5311 == 1'd1) & (icmp_ln220_fu_4781_p2 == 1'd0)) | ((icmp_ln221_1_fu_4799_p2 == 1'd1) & (icmp_ln220_fu_4781_p2 == 1'd0))))) begin + ap_NS_fsm = ap_ST_fsm_state11; + end else begin + ap_NS_fsm = ap_ST_fsm_state8; + end + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + if (((icmp_ln13_fu_5049_p2 == 1'd1) & (ap_ST_fsm_state13 == ap_CS_fsm))) begin + ap_NS_fsm = ap_ST_fsm_state15; + end else begin + ap_NS_fsm = ap_ST_fsm_state14; + end + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + default : begin + ap_NS_fsm = 'b0; + end + endcase +end + +assign add_ln203_1_fu_4848_p2 = (trunc_ln225_1_fu_4839_p1 + trunc_ln225_reg_5325); + +assign add_ln203_fu_5066_p2 = (trunc_ln233_reg_5284 + trunc_ln233_1_reg_6641); + +assign add_ln221_1_fu_4793_p2 = (jj_0_reg_4226 + zext_ln220_1_fu_4777_p1); + +assign add_ln221_fu_4751_p2 = (ii_0_reg_4214 + zext_ln218_fu_4735_p1); + +assign add_ln225_2_fu_4843_p2 = ((zext_ln225_1_reg_5320) + (sext_ln225_fu_4835_p1)); + +assign add_ln233_1_fu_5044_p2 = ((zext_ln233_reg_5279) + (sext_ln233_fu_5036_p1)); + +assign data_0_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_100_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_101_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_102_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_103_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_104_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_105_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_106_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_107_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_108_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_109_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_10_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_110_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_111_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_112_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_113_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_114_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_115_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_116_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_117_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_118_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_119_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_11_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_120_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_121_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_122_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_123_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_124_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_125_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_126_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_127_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_12_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_13_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_14_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_15_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_16_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_17_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_18_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_19_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_1_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_20_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_21_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_22_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_23_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_24_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_25_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_26_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_27_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_28_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_29_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_2_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_30_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_31_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_32_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_33_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_34_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_35_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_36_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_37_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_38_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_39_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_3_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_40_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_41_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_42_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_43_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_44_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_45_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_46_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_47_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_48_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_49_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_4_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_50_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_51_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_52_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_53_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_54_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_55_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_56_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_57_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_58_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_59_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_5_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_60_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_61_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_62_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_63_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_64_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_65_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_66_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_67_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_68_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_69_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_6_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_70_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_71_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_72_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_73_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_74_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_75_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_76_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_77_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_78_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_79_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_7_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_80_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_81_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_82_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_83_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_84_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_85_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_86_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_87_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_88_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_89_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_8_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_90_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_91_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_92_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_93_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_94_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_95_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_96_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_97_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_98_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_99_V_address0 = zext_ln203_1_fu_4874_p1; + +assign data_9_V_address0 = zext_ln203_1_fu_4874_p1; + +assign ff_fu_4691_p2 = (ff_0_reg_4203 + 4'd1); + +assign grp_fu_4672_p2 = (ll_0_reg_4250 + shl_ln223_reg_5315); + +assign grp_fu_5235_p0 = 10'd84; + +assign grp_fu_5235_p1 = grp_fu_5235_p10; + +assign grp_fu_5235_p10 = lshr_ln_fu_4703_p4; + +assign grp_fu_5235_p2 = zext_ln209_reg_5258; + +assign grp_fu_5244_p0 = 12'd168; + +assign grp_fu_5244_p1 = grp_fu_5244_p10; + +assign grp_fu_5244_p10 = add_ln221_reg_5305; + +assign grp_fu_5244_p2 = zext_ln209_1_reg_5263; + +assign i_fu_5060_p2 = (i_0_i_i_reg_4661 + 3'd1); + +assign icmp_ln13_fu_5049_p2 = ((i_0_i_i_reg_4661 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln1494_fu_5215_p2 = (((pool_V_q0) > (agg_result_V_0_i_i_reg_4523)) ? 1'b1 : 1'b0); + +assign icmp_ln209_fu_4685_p2 = ((ff_0_reg_4203 == 4'd12) ? 1'b1 : 1'b0); + +assign icmp_ln211_fu_4697_p2 = ((ii_0_reg_4214 == 4'd14) ? 1'b1 : 1'b0); + +assign icmp_ln213_fu_4723_p2 = ((jj_0_reg_4226 == 4'd14) ? 1'b1 : 1'b0); + +assign icmp_ln218_fu_4739_p2 = ((kk_0_reg_4238 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln220_fu_4781_p2 = ((ll_0_reg_4250 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln221_1_fu_4799_p2 = ((add_ln221_1_fu_4793_p2 > 4'd13) ? 1'b1 : 1'b0); + +assign icmp_ln221_fu_4760_p2 = ((add_ln221_reg_5305 > 4'd13) ? 1'b1 : 1'b0); + +assign ii_fu_4729_p2 = (ii_0_reg_4214 + 4'd2); + +assign jj_fu_5229_p2 = (jj_0_reg_4226 + 4'd2); + +assign kk_fu_4745_p2 = (kk_0_reg_4238 + 2'd1); + +assign ll_fu_4787_p2 = (ll_0_reg_4250 + 2'd1); + +assign lshr_ln_fu_4703_p4 = {{ii_0_reg_4214[3:1]}}; + +assign res_0_V_address0 = zext_ln203_fu_5083_p1; + +assign res_0_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_100_V_address0 = zext_ln203_fu_5083_p1; + +assign res_100_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_101_V_address0 = zext_ln203_fu_5083_p1; + +assign res_101_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_102_V_address0 = zext_ln203_fu_5083_p1; + +assign res_102_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_103_V_address0 = zext_ln203_fu_5083_p1; + +assign res_103_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_104_V_address0 = zext_ln203_fu_5083_p1; + +assign res_104_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_105_V_address0 = zext_ln203_fu_5083_p1; + +assign res_105_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_106_V_address0 = zext_ln203_fu_5083_p1; + +assign res_106_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_107_V_address0 = zext_ln203_fu_5083_p1; + +assign res_107_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_108_V_address0 = zext_ln203_fu_5083_p1; + +assign res_108_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_109_V_address0 = zext_ln203_fu_5083_p1; + +assign res_109_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_10_V_address0 = zext_ln203_fu_5083_p1; + +assign res_10_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_110_V_address0 = zext_ln203_fu_5083_p1; + +assign res_110_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_111_V_address0 = zext_ln203_fu_5083_p1; + +assign res_111_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_112_V_address0 = zext_ln203_fu_5083_p1; + +assign res_112_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_113_V_address0 = zext_ln203_fu_5083_p1; + +assign res_113_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_114_V_address0 = zext_ln203_fu_5083_p1; + +assign res_114_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_115_V_address0 = zext_ln203_fu_5083_p1; + +assign res_115_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_116_V_address0 = zext_ln203_fu_5083_p1; + +assign res_116_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_117_V_address0 = zext_ln203_fu_5083_p1; + +assign res_117_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_118_V_address0 = zext_ln203_fu_5083_p1; + +assign res_118_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_119_V_address0 = zext_ln203_fu_5083_p1; + +assign res_119_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_11_V_address0 = zext_ln203_fu_5083_p1; + +assign res_11_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_120_V_address0 = zext_ln203_fu_5083_p1; + +assign res_120_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_121_V_address0 = zext_ln203_fu_5083_p1; + +assign res_121_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_122_V_address0 = zext_ln203_fu_5083_p1; + +assign res_122_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_123_V_address0 = zext_ln203_fu_5083_p1; + +assign res_123_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_124_V_address0 = zext_ln203_fu_5083_p1; + +assign res_124_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_125_V_address0 = zext_ln203_fu_5083_p1; + +assign res_125_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_126_V_address0 = zext_ln203_fu_5083_p1; + +assign res_126_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_127_V_address0 = zext_ln203_fu_5083_p1; + +assign res_127_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_12_V_address0 = zext_ln203_fu_5083_p1; + +assign res_12_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_13_V_address0 = zext_ln203_fu_5083_p1; + +assign res_13_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_14_V_address0 = zext_ln203_fu_5083_p1; + +assign res_14_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_15_V_address0 = zext_ln203_fu_5083_p1; + +assign res_15_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_16_V_address0 = zext_ln203_fu_5083_p1; + +assign res_16_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_17_V_address0 = zext_ln203_fu_5083_p1; + +assign res_17_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_18_V_address0 = zext_ln203_fu_5083_p1; + +assign res_18_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_19_V_address0 = zext_ln203_fu_5083_p1; + +assign res_19_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_1_V_address0 = zext_ln203_fu_5083_p1; + +assign res_1_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_20_V_address0 = zext_ln203_fu_5083_p1; + +assign res_20_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_21_V_address0 = zext_ln203_fu_5083_p1; + +assign res_21_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_22_V_address0 = zext_ln203_fu_5083_p1; + +assign res_22_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_23_V_address0 = zext_ln203_fu_5083_p1; + +assign res_23_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_24_V_address0 = zext_ln203_fu_5083_p1; + +assign res_24_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_25_V_address0 = zext_ln203_fu_5083_p1; + +assign res_25_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_26_V_address0 = zext_ln203_fu_5083_p1; + +assign res_26_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_27_V_address0 = zext_ln203_fu_5083_p1; + +assign res_27_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_28_V_address0 = zext_ln203_fu_5083_p1; + +assign res_28_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_29_V_address0 = zext_ln203_fu_5083_p1; + +assign res_29_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_2_V_address0 = zext_ln203_fu_5083_p1; + +assign res_2_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_30_V_address0 = zext_ln203_fu_5083_p1; + +assign res_30_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_31_V_address0 = zext_ln203_fu_5083_p1; + +assign res_31_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_32_V_address0 = zext_ln203_fu_5083_p1; + +assign res_32_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_33_V_address0 = zext_ln203_fu_5083_p1; + +assign res_33_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_34_V_address0 = zext_ln203_fu_5083_p1; + +assign res_34_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_35_V_address0 = zext_ln203_fu_5083_p1; + +assign res_35_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_36_V_address0 = zext_ln203_fu_5083_p1; + +assign res_36_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_37_V_address0 = zext_ln203_fu_5083_p1; + +assign res_37_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_38_V_address0 = zext_ln203_fu_5083_p1; + +assign res_38_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_39_V_address0 = zext_ln203_fu_5083_p1; + +assign res_39_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_3_V_address0 = zext_ln203_fu_5083_p1; + +assign res_3_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_40_V_address0 = zext_ln203_fu_5083_p1; + +assign res_40_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_41_V_address0 = zext_ln203_fu_5083_p1; + +assign res_41_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_42_V_address0 = zext_ln203_fu_5083_p1; + +assign res_42_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_43_V_address0 = zext_ln203_fu_5083_p1; + +assign res_43_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_44_V_address0 = zext_ln203_fu_5083_p1; + +assign res_44_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_45_V_address0 = zext_ln203_fu_5083_p1; + +assign res_45_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_46_V_address0 = zext_ln203_fu_5083_p1; + +assign res_46_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_47_V_address0 = zext_ln203_fu_5083_p1; + +assign res_47_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_48_V_address0 = zext_ln203_fu_5083_p1; + +assign res_48_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_49_V_address0 = zext_ln203_fu_5083_p1; + +assign res_49_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_4_V_address0 = zext_ln203_fu_5083_p1; + +assign res_4_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_50_V_address0 = zext_ln203_fu_5083_p1; + +assign res_50_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_51_V_address0 = zext_ln203_fu_5083_p1; + +assign res_51_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_52_V_address0 = zext_ln203_fu_5083_p1; + +assign res_52_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_53_V_address0 = zext_ln203_fu_5083_p1; + +assign res_53_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_54_V_address0 = zext_ln203_fu_5083_p1; + +assign res_54_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_55_V_address0 = zext_ln203_fu_5083_p1; + +assign res_55_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_56_V_address0 = zext_ln203_fu_5083_p1; + +assign res_56_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_57_V_address0 = zext_ln203_fu_5083_p1; + +assign res_57_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_58_V_address0 = zext_ln203_fu_5083_p1; + +assign res_58_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_59_V_address0 = zext_ln203_fu_5083_p1; + +assign res_59_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_5_V_address0 = zext_ln203_fu_5083_p1; + +assign res_5_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_60_V_address0 = zext_ln203_fu_5083_p1; + +assign res_60_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_61_V_address0 = zext_ln203_fu_5083_p1; + +assign res_61_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_62_V_address0 = zext_ln203_fu_5083_p1; + +assign res_62_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_63_V_address0 = zext_ln203_fu_5083_p1; + +assign res_63_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_64_V_address0 = zext_ln203_fu_5083_p1; + +assign res_64_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_65_V_address0 = zext_ln203_fu_5083_p1; + +assign res_65_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_66_V_address0 = zext_ln203_fu_5083_p1; + +assign res_66_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_67_V_address0 = zext_ln203_fu_5083_p1; + +assign res_67_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_68_V_address0 = zext_ln203_fu_5083_p1; + +assign res_68_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_69_V_address0 = zext_ln203_fu_5083_p1; + +assign res_69_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_6_V_address0 = zext_ln203_fu_5083_p1; + +assign res_6_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_70_V_address0 = zext_ln203_fu_5083_p1; + +assign res_70_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_71_V_address0 = zext_ln203_fu_5083_p1; + +assign res_71_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_72_V_address0 = zext_ln203_fu_5083_p1; + +assign res_72_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_73_V_address0 = zext_ln203_fu_5083_p1; + +assign res_73_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_74_V_address0 = zext_ln203_fu_5083_p1; + +assign res_74_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_75_V_address0 = zext_ln203_fu_5083_p1; + +assign res_75_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_76_V_address0 = zext_ln203_fu_5083_p1; + +assign res_76_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_77_V_address0 = zext_ln203_fu_5083_p1; + +assign res_77_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_78_V_address0 = zext_ln203_fu_5083_p1; + +assign res_78_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_79_V_address0 = zext_ln203_fu_5083_p1; + +assign res_79_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_7_V_address0 = zext_ln203_fu_5083_p1; + +assign res_7_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_80_V_address0 = zext_ln203_fu_5083_p1; + +assign res_80_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_81_V_address0 = zext_ln203_fu_5083_p1; + +assign res_81_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_82_V_address0 = zext_ln203_fu_5083_p1; + +assign res_82_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_83_V_address0 = zext_ln203_fu_5083_p1; + +assign res_83_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_84_V_address0 = zext_ln203_fu_5083_p1; + +assign res_84_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_85_V_address0 = zext_ln203_fu_5083_p1; + +assign res_85_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_86_V_address0 = zext_ln203_fu_5083_p1; + +assign res_86_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_87_V_address0 = zext_ln203_fu_5083_p1; + +assign res_87_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_88_V_address0 = zext_ln203_fu_5083_p1; + +assign res_88_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_89_V_address0 = zext_ln203_fu_5083_p1; + +assign res_89_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_8_V_address0 = zext_ln203_fu_5083_p1; + +assign res_8_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_90_V_address0 = zext_ln203_fu_5083_p1; + +assign res_90_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_91_V_address0 = zext_ln203_fu_5083_p1; + +assign res_91_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_92_V_address0 = zext_ln203_fu_5083_p1; + +assign res_92_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_93_V_address0 = zext_ln203_fu_5083_p1; + +assign res_93_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_94_V_address0 = zext_ln203_fu_5083_p1; + +assign res_94_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_95_V_address0 = zext_ln203_fu_5083_p1; + +assign res_95_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_96_V_address0 = zext_ln203_fu_5083_p1; + +assign res_96_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_97_V_address0 = zext_ln203_fu_5083_p1; + +assign res_97_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_98_V_address0 = zext_ln203_fu_5083_p1; + +assign res_98_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_99_V_address0 = zext_ln203_fu_5083_p1; + +assign res_99_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign res_9_V_address0 = zext_ln203_fu_5083_p1; + +assign res_9_V_d0 = agg_result_V_0_i_i_reg_4523; + +assign sext_ln203_1_fu_4871_p1 = (trunc_ln203_1_reg_5351); + +assign sext_ln203_fu_5079_p1 = (trunc_ln2_fu_5070_p4); + +assign sext_ln225_fu_4835_p1 = sub_ln225_fu_4829_p2; + +assign sext_ln233_fu_5036_p1 = sub_ln233_fu_5030_p2; + +assign shl_ln223_fu_4765_p2 = kk_0_reg_4238 << 2'd1; + +assign shl_ln225_1_fu_4817_p3 = {{add_ln221_1_fu_4793_p2}, {2'd0}}; + +assign shl_ln233_1_fu_5018_p3 = {{jj_0_reg_4226}, {1'd0}}; + +assign shl_ln2_fu_4805_p3 = {{add_ln221_1_fu_4793_p2}, {4'd0}}; + +assign shl_ln_fu_5006_p3 = {{jj_0_reg_4226}, {3'd0}}; + +assign sub_ln225_fu_4829_p2 = (zext_ln225_2_fu_4813_p1 - zext_ln225_3_fu_4825_p1); + +assign sub_ln233_fu_5030_p2 = (zext_ln233_1_fu_5014_p1 - zext_ln233_2_fu_5026_p1); + +assign trunc_ln225_1_fu_4839_p1 = sub_ln225_fu_4829_p2[6:0]; + +assign trunc_ln225_fu_4774_p1 = grp_fu_5244_p3[6:0]; + +assign trunc_ln233_1_fu_5040_p1 = sub_ln233_fu_5030_p2[6:0]; + +assign trunc_ln233_fu_4720_p1 = grp_fu_5235_p3[6:0]; + +assign trunc_ln2_fu_5070_p4 = {{add_ln233_1_reg_6646[10:7]}}; + +assign y_V_1_fu_5221_p3 = ((icmp_ln1494_fu_5215_p2[0:0] == 1'b1) ? pool_V_q0 : agg_result_V_0_i_i_reg_4523); + +assign zext_ln14_fu_5055_p1 = i_0_i_i_reg_4661; + +assign zext_ln203_1_fu_4874_p1 = (sext_ln203_1_fu_4871_p1); + +assign zext_ln203_fu_5083_p1 = (sext_ln203_fu_5079_p1); + +assign zext_ln209_1_fu_4681_p1 = ff_0_reg_4203; + +assign zext_ln209_fu_4677_p1 = ff_0_reg_4203; + +assign zext_ln218_fu_4735_p1 = kk_0_reg_4238; + +assign zext_ln220_1_fu_4777_p1 = ll_0_reg_4250; + +assign zext_ln223_fu_4863_p1 = grp_fu_4672_p2; + +assign zext_ln225_1_fu_4771_p1 = grp_fu_5244_p3; + +assign zext_ln225_2_fu_4813_p1 = shl_ln2_fu_4805_p3; + +assign zext_ln225_3_fu_4825_p1 = shl_ln225_1_fu_4817_p3; + +assign zext_ln225_fu_4868_p1 = add_ln225_reg_5342; + +assign zext_ln233_1_fu_5014_p1 = shl_ln_fu_5006_p3; + +assign zext_ln233_2_fu_5026_p1 = shl_ln233_1_fu_5018_p3; + +assign zext_ln233_fu_4717_p1 = grp_fu_5235_p3; + +always @ (posedge ap_clk) begin + zext_ln209_reg_5258[9:4] <= 6'b000000; + zext_ln209_1_reg_5263[11:4] <= 8'b00000000; + zext_ln233_reg_5279[10] <= 1'b0; + shl_ln223_reg_5315[0] <= 1'b0; + zext_ln225_1_reg_5320[12] <= 1'b0; + zext_ln225_reg_5356[63:2] <= 62'b00000000000000000000000000000000000000000000000000000000000000; + trunc_ln233_1_reg_6641[0] <= 1'b0; +end + +endmodule //pooling2d_cl_ap_fixed_ap_fixed_8_4_5_3_0_config7_s +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_prehebPq_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +reg [DATA_WIDTH-1:0] q_tmp; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q_tmp = sr_0; + 1'd1: q_tmp = sr_1; + default: q_tmp = sr_1; + endcase +end + +assign q = q_tmp; + +endmodule + +module start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_prehebPq ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_prehebPq_shiftReg +#( + .DATA_WIDTH(DATA_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DEPTH(DEPTH)) +U_start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_prehebPq_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit) +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_prehebQq_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +reg [DATA_WIDTH-1:0] q_tmp; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q_tmp = sr_0; + 1'd1: q_tmp = sr_1; + default: q_tmp = sr_1; + endcase +end + +assign q = q_tmp; + +endmodule + +module start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_prehebQq ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_prehebQq_shiftReg +#( + .DATA_WIDTH(DATA_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DEPTH(DEPTH)) +U_start_for_dense_latency_0_0_0_0_0_0_0_0_0_0_0_Block_prehebQq_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + + diff --git a/designs/koios/lstm/design.yaml b/designs/koios/lstm/design.yaml new file mode 100644 index 000000000..ca3e1970c --- /dev/null +++ b/designs/koios/lstm/design.yaml @@ -0,0 +1 @@ +top: lstm_random diff --git a/designs/koios/lstm/lstm.v b/designs/koios/lstm/lstm.v new file mode 100644 index 000000000..fbd2f201c --- /dev/null +++ b/designs/koios/lstm/lstm.v @@ -0,0 +1,1652 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Aishwarya Rajen +////////////////////////////////////////////////////////////////////////////// + +//`define SIMULATION_MEMORY +`define ARRAY_DEPTH 64 //Number of Hidden neurons +`define INPUT_DEPTH 100 //LSTM input vector dimensions +`define DATA_WIDTH 16 //16 bit representation +`define INWEIGHT_DEPTH 6400 //100x64 +`define HWEIGHT_DEPTH 4096 //64x64 +`define varraysize 1600 //100x16 +`define uarraysize 1024 //64x16 + +///////////////////////////////////////////////////////////////////////////////// +//LSTM layer design +///////////////////////////////////////////////////////////////////////////////// +// +//This verilog implementation can be used for LSTM inference applications. +//LSTM contains four gates :Input,Output,Forget and Cell State. +//The architecture is such that the four gates can be parallelized for the +//most part except for the ending few stages were previous cycle output is +//required. The weights of the gates (obtained from training using Python or +//other sources) is stored and accessed through BRAMs on the FPGA. +//Fixed Point 16 (4.12) format is used +//This is a pipelined LSTM network design with the following blocks: +//1.MVM - Matrix vector multiplication Block +// Every cycle one row of the matrix gets multiplied with the vector producing +// one 16 bit output which can get processed by further stages. +//2.ELEMENT WISE ADD +// 16 bit addition +//3.SIGMOID +// LUT based Sigmoid approximation +//4.ELEMENT WISE MULTIPLICATION +// 2s complement based signed multiplication +//5.TANH +// LUT based tanH approximation +// +////////////////////////////////////////////////////////////////////////////////// + + + +module top( +input clk, +input reset, +input start, //start the computation +input [6:0] start_addr, //start address of the Xin bram (input words to LSTM) +input [6:0] end_addr, //end address of the Xin bram +input wren_a, +input [`uarraysize-1:0] wdata_u, +input [`varraysize-1:0] wdata_v, +input [`DATA_WIDTH-1:0] wdata_b, +output ht_valid, //indicates the output ht_out is valid in those cycles +output [`DATA_WIDTH-1:0] ht_out, //output ht from the lstm +output reg cycle_complete, //generates a pulse when a cycle fo 64 ht outputs are complete +output reg Done //Stays high indicating the end of lstm output computation for all the Xin words provided. +); + +wire [`uarraysize-1:0] Ui_in; +wire [`varraysize-1:0] Wi_in; +wire [`uarraysize-1:0] Uf_in; +wire [`varraysize-1:0] Wf_in; +wire [`uarraysize-1:0] Uo_in; +wire [`varraysize-1:0] Wo_in; +wire [`uarraysize-1:0] Uc_in; +wire [`varraysize-1:0] Wc_in; +wire [`varraysize-1:0] x_in; +reg [`uarraysize-1:0] h_in; + + +//reg [`uarraysize-1:0] dummyin_u; +//reg [`varraysize-1:0] dummyin_v; +//reg [`DATA_WIDTH-1:0] dummyin_b; + +wire [`DATA_WIDTH-1:0] bi_in; +wire [`DATA_WIDTH-1:0] bf_in; +wire [`DATA_WIDTH-1:0] bo_in; +wire [`DATA_WIDTH-1:0] bc_in; +reg [`DATA_WIDTH-1:0] C_in; +//wire [`varraysize-1:0] xdata_b_ext; +//wire [`uarraysize-1:0] hdata_b_ext; + +//keeping an additional bit so that the counters don't get reset to 0 automatically after 63 +//and start repeating access to elements prematurely +reg [6:0] inaddr; +reg [6:0] waddr; +//reg wren_a; +reg [6:0] c_count; +reg [6:0] b_count; +reg [6:0] ct_count; +reg [6:0] count; +reg [6:0] i,j; +reg [5:0] h_count; + +wire [`DATA_WIDTH-1:0] ht; +reg [`uarraysize-1:0] ht_prev; +reg [`uarraysize-1:0] Ct; +wire [`DATA_WIDTH-1:0] add_cf; +//reg wren_a_ct, wren_b_cin; + +assign ht_out = ht; + + +//indicates that the ht_out output is valid +assign ht_valid = (count>16)? 1'b1: 1'b0; + + +//BRAMs storing the input and hidden weights of each of the gates +//Hidden weights are represented by U and Input weights by W +spram_u Ui_mem(.clk(clk),.address_a(waddr),.wren_a(wren_a),.data_a(wdata_u),.out_a(Ui_in)); +spram_u Uf_mem(.clk(clk),.address_a(waddr),.wren_a(wren_a),.data_a(wdata_u),.out_a(Uf_in)); +spram_u Uo_mem(.clk(clk),.address_a(waddr),.wren_a(wren_a),.data_a(wdata_u),.out_a(Uo_in)); +spram_u Uc_mem(.clk(clk),.address_a(waddr),.wren_a(wren_a),.data_a(wdata_u),.out_a(Uc_in)); +spram_v Wi_mem(.clk(clk),.address_a(waddr),.wren_a(wren_a),.data_a(wdata_v),.out_a(Wi_in)); +spram_v Wf_mem(.clk(clk),.address_a(waddr),.wren_a(wren_a),.data_a(wdata_v),.out_a(Wf_in)); +spram_v Wo_mem(.clk(clk),.address_a(waddr),.wren_a(wren_a),.data_a(wdata_v),.out_a(Wo_in)); +spram_v Wc_mem(.clk(clk),.address_a(waddr),.wren_a(wren_a),.data_a(wdata_v),.out_a(Wc_in)); + +//BRAM of the input vectors to LSTM +spram_v Xi_mem(.clk(clk),.address_a(inaddr),.wren_a(wren_a),.data_a(wdata_v),.out_a(x_in)); + +//BRAM storing Bias of each gate +spram_b bi_mem(.clk(clk),.address_a(b_count),.wren_a(wren_a),.data_a(wdata_b),.out_a(bi_in)); +spram_b bf_mem(.clk(clk),.address_a(b_count),.wren_a(wren_a),.data_a(wdata_b),.out_a(bf_in)); +spram_b bo_mem(.clk(clk),.address_a(b_count),.wren_a(wren_a),.data_a(wdata_b),.out_a(bo_in)); +spram_b bc_mem(.clk(clk),.address_a(b_count),.wren_a(wren_a),.data_a(wdata_b),.out_a(bc_in)); + + + +lstm_top lstm(.clk(clk),.rst(reset),.ht_out(ht),.Ui_in(Ui_in),.Wi_in(Wi_in),.Uf_in(Uf_in),.Wf_in(Wf_in),.Uo_in(Uo_in),.Wo_in(Wo_in), +.Uc_in(Uc_in),.Wc_in(Wc_in),.x_in(x_in),.h_in(h_in),.C_in(C_in),.bi_in(bi_in),.bf_in(bf_in),.bo_in(bo_in),.bc_in(bc_in),.add_cf(add_cf)); + +always @(posedge clk) begin + if(reset == 1'b1 || start==1'b0) + begin + count <= 0; + b_count <=0; + h_count <= 0; + c_count <= 0; + ct_count <=0; + Ct <= 0; + C_in <=0; + h_in <= 0; + ht_prev <= 0; + //wren_a <= 0; + //wren_a_ct <= 1; + //wren_b_cin <= 0; + cycle_complete <=0; + Done <= 0; + waddr <=0; + inaddr <= start_addr; + + //dummy ports initialize + //dummyin_u <= 0; + //dummyin_v <=0; + //dummyin_b <= 0; + + end + else begin + + if(h_count == `ARRAY_DEPTH-1) begin + cycle_complete <= 1; + waddr <= 0; + count <=0; + b_count <= 0; + ct_count <=0; + c_count <= 0; + + if(inaddr == end_addr) + Done <= 1; + else begin + inaddr <= inaddr+1'b1; + h_count <= 0; + + end + end + else begin + cycle_complete <= 0; + waddr <= waddr+1'b1; + count <= count+1'b1; + + if(count>7) //delay before bias add + b_count <= b_count+1'b1; + + if(count >8) begin //delay before Cin elmul + c_count <=c_count+1'b1; + case(c_count) + 0: C_in<=Ct[16*0+:16] ; + 1: C_in<=Ct[16*1+:16] ; + 2: C_in<=Ct[16*2+:16] ; + 3: C_in<=Ct[16*3+:16] ; + 4: C_in<=Ct[16*4+:16] ; + 5: C_in<=Ct[16*5+:16] ; + 6: C_in<=Ct[16*6+:16] ; + 7: C_in<=Ct[16*7+:16] ; + 8: C_in<=Ct[16*8+:16] ; + 9: C_in<=Ct[16*9+:16] ; + 10: C_in <=Ct[16*10+:16]; + 11: C_in <=Ct[16*11+:16]; + 12: C_in <=Ct[16*12+:16]; + 13: C_in <=Ct[16*13+:16]; + 14: C_in <=Ct[16*14+:16]; + 15: C_in <=Ct[16*15+:16]; + 16: C_in <=Ct[16*16+:16]; + 17: C_in <=Ct[16*17+:16]; + 18: C_in <=Ct[16*18+:16]; + 19: C_in <=Ct[16*19+:16]; + 20: C_in <=Ct[16*20+:16]; + 21: C_in <=Ct[16*21+:16]; + 22: C_in <=Ct[16*22+:16]; + 23: C_in <=Ct[16*23+:16]; + 24: C_in <=Ct[16*24+:16]; + 25: C_in <=Ct[16*25+:16]; + 26: C_in <=Ct[16*26+:16]; + 27: C_in <=Ct[16*27+:16]; + 28: C_in <=Ct[16*28+:16]; + 29: C_in <=Ct[16*29+:16]; + 30: C_in <=Ct[16*30+:16]; + 31: C_in <=Ct[16*31+:16]; + 32: C_in <=Ct[16*32+:16]; + 33: C_in <=Ct[16*33+:16]; + 34: C_in <=Ct[16*34+:16]; + 35: C_in <=Ct[16*35+:16]; + 36: C_in <=Ct[16*36+:16]; + 37: C_in <=Ct[16*37+:16]; + 38: C_in <=Ct[16*38+:16]; + 39: C_in <=Ct[16*39+:16]; + 40: C_in <=Ct[16*40+:16]; + 41: C_in <=Ct[16*41+:16]; + 42: C_in <=Ct[16*42+:16]; + 43: C_in <=Ct[16*43+:16]; + 44: C_in <=Ct[16*44+:16]; + 45: C_in <=Ct[16*45+:16]; + 46: C_in <=Ct[16*46+:16]; + 47: C_in <=Ct[16*47+:16]; + 48: C_in <=Ct[16*48+:16]; + 49: C_in <=Ct[16*49+:16]; + 50: C_in <=Ct[16*50+:16]; + 51: C_in <=Ct[16*51+:16]; + 52: C_in <=Ct[16*52+:16]; + 53: C_in <=Ct[16*53+:16]; + 54: C_in <=Ct[16*54+:16]; + 55: C_in <=Ct[16*55+:16]; + 56: C_in <=Ct[16*56+:16]; + 57: C_in <=Ct[16*57+:16]; + 58: C_in <=Ct[16*58+:16]; + 59: C_in <=Ct[16*59+:16]; + 60: C_in <=Ct[16*60+:16]; + 61: C_in <=Ct[16*61+:16]; + 62: C_in <=Ct[16*62+:16]; + 63: C_in <=Ct[16*63+:16]; + default : C_in <= 0; + endcase + end + + if(count >11) begin //for storing output of Ct + ct_count <= ct_count+1'b1; + //storing cell state + case(ct_count) + 0: Ct[16*0+:16] <= add_cf; + 1: Ct[16*1+:16] <= add_cf; + 2: Ct[16*2+:16] <= add_cf; + 3: Ct[16*3+:16] <= add_cf; + 4: Ct[16*4+:16] <= add_cf; + 5: Ct[16*5+:16] <= add_cf; + 6: Ct[16*6+:16] <= add_cf; + 7: Ct[16*7+:16] <= add_cf; + 8: Ct[16*8+:16] <= add_cf; + 9: Ct[16*9+:16] <= add_cf; + 10: Ct[16*10+:16] <=add_cf; + 11: Ct[16*11+:16] <=add_cf; + 12: Ct[16*12+:16] <=add_cf; + 13: Ct[16*13+:16] <=add_cf; + 14: Ct[16*14+:16] <=add_cf; + 15: Ct[16*15+:16] <=add_cf; + 16: Ct[16*16+:16] <=add_cf; + 17: Ct[16*17+:16] <=add_cf; + 18: Ct[16*18+:16] <=add_cf; + 19: Ct[16*19+:16] <=add_cf; + 20: Ct[16*20+:16] <=add_cf; + 21: Ct[16*21+:16] <=add_cf; + 22: Ct[16*22+:16] <=add_cf; + 23: Ct[16*23+:16] <=add_cf; + 24: Ct[16*24+:16] <=add_cf; + 25: Ct[16*25+:16] <=add_cf; + 26: Ct[16*26+:16] <=add_cf; + 27: Ct[16*27+:16] <=add_cf; + 28: Ct[16*28+:16] <=add_cf; + 29: Ct[16*29+:16] <=add_cf; + 30: Ct[16*30+:16] <=add_cf; + 31: Ct[16*31+:16] <=add_cf; + 32: Ct[16*32+:16] <=add_cf; + 33: Ct[16*33+:16] <=add_cf; + 34: Ct[16*34+:16] <=add_cf; + 35: Ct[16*35+:16] <=add_cf; + 36: Ct[16*36+:16] <=add_cf; + 37: Ct[16*37+:16] <=add_cf; + 38: Ct[16*38+:16] <=add_cf; + 39: Ct[16*39+:16] <=add_cf; + 40: Ct[16*40+:16] <=add_cf; + 41: Ct[16*41+:16] <=add_cf; + 42: Ct[16*42+:16] <=add_cf; + 43: Ct[16*43+:16] <=add_cf; + 44: Ct[16*44+:16] <=add_cf; + 45: Ct[16*45+:16] <=add_cf; + 46: Ct[16*46+:16] <=add_cf; + 47: Ct[16*47+:16] <=add_cf; + 48: Ct[16*48+:16] <=add_cf; + 49: Ct[16*49+:16] <=add_cf; + 50: Ct[16*50+:16] <=add_cf; + 51: Ct[16*51+:16] <=add_cf; + 52: Ct[16*52+:16] <=add_cf; + 53: Ct[16*53+:16] <=add_cf; + 54: Ct[16*54+:16] <=add_cf; + 55: Ct[16*55+:16] <=add_cf; + 56: Ct[16*56+:16] <=add_cf; + 57: Ct[16*57+:16] <=add_cf; + 58: Ct[16*58+:16] <=add_cf; + 59: Ct[16*59+:16] <=add_cf; + 60: Ct[16*60+:16] <=add_cf; + 61: Ct[16*61+:16] <=add_cf; + 62: Ct[16*62+:16] <=add_cf; + 63: Ct[16*63+:16] <=add_cf; + default : Ct <= 0; + endcase + end + if(count >16) begin + h_count <= h_count + 1'b1; + case(h_count) + 0: ht_prev[16*0+:16] <= ht; + 1: ht_prev[16*1+:16] <= ht; + 2: ht_prev[16*2+:16] <= ht; + 3: ht_prev[16*3+:16] <= ht; + 4: ht_prev[16*4+:16] <= ht; + 5: ht_prev[16*5+:16] <= ht; + 6: ht_prev[16*6+:16] <= ht; + 7: ht_prev[16*7+:16] <= ht; + 8: ht_prev[16*8+:16] <= ht; + 9: ht_prev[16*9+:16] <= ht; + 10: ht_prev[16*10+:16] <= ht; + 11: ht_prev[16*11+:16] <= ht; + 12: ht_prev[16*12+:16] <= ht; + 13: ht_prev[16*13+:16] <= ht; + 14: ht_prev[16*14+:16] <= ht; + 15: ht_prev[16*15+:16] <= ht; + 16: ht_prev[16*16+:16] <= ht; + 17: ht_prev[16*17+:16] <= ht; + 18: ht_prev[16*18+:16] <= ht; + 19: ht_prev[16*19+:16] <= ht; + 20: ht_prev[16*20+:16] <= ht; + 21: ht_prev[16*21+:16] <= ht; + 22: ht_prev[16*22+:16] <= ht; + 23: ht_prev[16*23+:16] <= ht; + 24: ht_prev[16*24+:16] <= ht; + 25: ht_prev[16*25+:16] <= ht; + 26: ht_prev[16*26+:16] <= ht; + 27: ht_prev[16*27+:16] <= ht; + 28: ht_prev[16*28+:16] <= ht; + 29: ht_prev[16*29+:16] <= ht; + 30: ht_prev[16*30+:16] <= ht; + 31: ht_prev[16*31+:16] <= ht; + 32: ht_prev[16*32+:16] <= ht; + 33: ht_prev[16*33+:16] <= ht; + 34: ht_prev[16*34+:16] <= ht; + 35: ht_prev[16*35+:16] <= ht; + 36: ht_prev[16*36+:16] <= ht; + 37: ht_prev[16*37+:16] <= ht; + 38: ht_prev[16*38+:16] <= ht; + 39: ht_prev[16*39+:16] <= ht; + 40: ht_prev[16*40+:16] <= ht; + 41: ht_prev[16*41+:16] <= ht; + 42: ht_prev[16*42+:16] <= ht; + 43: ht_prev[16*43+:16] <= ht; + 44: ht_prev[16*44+:16] <= ht; + 45: ht_prev[16*45+:16] <= ht; + 46: ht_prev[16*46+:16] <= ht; + 47: ht_prev[16*47+:16] <= ht; + 48: ht_prev[16*48+:16] <= ht; + 49: ht_prev[16*49+:16] <= ht; + 50: ht_prev[16*50+:16] <= ht; + 51: ht_prev[16*51+:16] <= ht; + 52: ht_prev[16*52+:16] <= ht; + 53: ht_prev[16*53+:16] <= ht; + 54: ht_prev[16*54+:16] <= ht; + 55: ht_prev[16*55+:16] <= ht; + 56: ht_prev[16*56+:16] <= ht; + 57: ht_prev[16*57+:16] <= ht; + 58: ht_prev[16*58+:16] <= ht; + 59: ht_prev[16*59+:16] <= ht; + 60: ht_prev[16*60+:16] <= ht; + 61: ht_prev[16*61+:16] <= ht; + 62: ht_prev[16*62+:16] <= ht; + 63: ht_prev[16*63+:16] <= ht; + default: ht_prev <= 0; + endcase + end + + end + + + + if(cycle_complete==1) begin + h_in <= ht_prev; + end + + end + end + + + +endmodule + + + + + +module spram_v( +input clk, +input [(7-1):0] address_a, +input wren_a, +input [(`varraysize-1):0] data_a, +output reg [(`varraysize-1):0] out_a +); + + +`ifndef hard_mem + +reg [`varraysize-1:0] ram[`ARRAY_DEPTH-1:0]; + +always @ (posedge clk) begin + if (wren_a) begin + ram[address_a] <= data_a; + end + else begin + out_a <= ram[address_a]; + end +end + + +`else + +defparam u_single_port_ram.ADDR_WIDTH = 7; +defparam u_single_port_ram.DATA_WIDTH = `varraysize; + +single_port_ram u_single_port_ram( +.addr(address_a), +.we(wren_a), +.data(data_a), +.out(out_a), +.clk(clk) +); + +`endif + +endmodule + +module spram_u ( +input clk, +input [(7-1):0] address_a, +input wren_a, +input [(`uarraysize-1):0] data_a, +output reg [(`uarraysize-1):0] out_a +); + + +`ifndef hard_mem + +reg [`uarraysize-1:0] ram[`ARRAY_DEPTH-1:0]; + +always @ (posedge clk) begin + if (wren_a) begin + ram[address_a] <= data_a; + end + else begin + out_a <= ram[address_a]; + end +end + + +`else + +defparam u_single_port_ram.ADDR_WIDTH = 7; +defparam u_single_port_ram.DATA_WIDTH = `uarraysize; + +single_port_ram u_single_port_ram( +.addr(address_a), +.we(wren_a), +.data(data_a), +.out(out_a), +.clk(clk) +); + +`endif + +endmodule + +module spram_b ( +input clk, +input [(7-1):0] address_a, +input wren_a, +input [(`DATA_WIDTH-1):0] data_a, +output reg [(`DATA_WIDTH-1):0] out_a +); + + +`ifndef hard_mem + +reg [`DATA_WIDTH-1:0] ram[`ARRAY_DEPTH-1:0]; + +always @ (posedge clk) begin + if (wren_a) begin + ram[address_a] <= data_a; + end + else begin + out_a <= ram[address_a]; + end +end + + +`else + +defparam u_single_port_ram.ADDR_WIDTH = 7; +defparam u_single_port_ram.DATA_WIDTH = `DATA_WIDTH; + +single_port_ram u_single_port_ram( +.addr(address_a), +.we(wren_a), +.data(data_a), +.out(out_a), +.clk(clk) +); + +`endif + +endmodule + + +module lstm_top( +input clk, +input rst, +output [15:0] ht_out, +input [`uarraysize-1:0] Ui_in, +input [`varraysize-1:0] Wi_in, +input [`uarraysize-1:0] Uf_in, +input [`varraysize-1:0] Wf_in, +input [`uarraysize-1:0] Uo_in, +input [`varraysize-1:0] Wo_in, +input [`uarraysize-1:0] Uc_in, +input [`varraysize-1:0] Wc_in, +input [`varraysize-1:0] x_in, +input [`uarraysize-1:0] h_in, +input [`DATA_WIDTH-1:0] bi_in, +input [`DATA_WIDTH-1:0] bf_in, +input [`DATA_WIDTH-1:0] bo_in, +input [`DATA_WIDTH-1:0] bc_in, +input [`DATA_WIDTH-1:0] C_in, +output [`DATA_WIDTH-1:0] add_cf); + + +wire [`uarraysize-1:0] mulout_ih; +wire [`uarraysize-1:0] mulout_fh; +wire [`uarraysize-1:0] mulout_ch; +wire [`uarraysize-1:0] mulout_oh; + +wire [`varraysize-1:0] mulout_ix; +wire [`varraysize-1:0] mulout_fx; +wire [`varraysize-1:0] mulout_cx; +wire [`varraysize-1:0] mulout_ox; + +wire [`DATA_WIDTH-1:0] macout_ix; +wire [`DATA_WIDTH-1:0] macout_ih; +wire [`DATA_WIDTH-1:0] add_i; +wire [`DATA_WIDTH-1:0] macout_fx; +wire [`DATA_WIDTH-1:0] macout_fh; +wire [`DATA_WIDTH-1:0] add_f; +wire [`DATA_WIDTH-1:0] macout_cx; +wire [`DATA_WIDTH-1:0] macout_ch; +wire [`DATA_WIDTH-1:0] add_c; +wire [`DATA_WIDTH-1:0] macout_ox; +wire [`DATA_WIDTH-1:0] macout_oh; +wire [`DATA_WIDTH-1:0] add_o; +//wire [`DATA_WIDTH-1:0] add_cf; + + +wire [`DATA_WIDTH-1:0] addbias_i; +wire [`DATA_WIDTH-1:0] addbias_f; +wire [`DATA_WIDTH-1:0] addbias_o; +wire [`DATA_WIDTH-1:0] addbias_c; + +wire [`DATA_WIDTH-1:0] sig_io; +wire [`DATA_WIDTH-1:0] sig_fo; +wire [`DATA_WIDTH-1:0] sig_oo; + + +wire [`DATA_WIDTH-1:0] elmul_fo; +wire [`DATA_WIDTH-1:0] elmul_co; +wire [`DATA_WIDTH-1:0] tan_c; +wire [`DATA_WIDTH-1:0] tan_h; + + +wire [15:0] ht; + + +assign ht_out = ht; + +reg [15:0] mac_fx_reg,mac_fh_reg,add_f_reg,addb_f_reg,sig_fo_reg; +reg [15:0] mac_ix_reg,mac_ih_reg,add_i_reg,addb_i_reg,sig_io_reg; +reg [15:0] mac_ox_reg,mac_oh_reg, add_o_reg,addb_o_reg,sig_oo_reg; +reg [15:0] mac_cx_reg,mac_ch_reg, add_c_reg,addb_c_reg,sig_co_reg; +reg [15:0] tan_c_reg,elmul_co_reg,add_cf_reg,tan_h_reg,elmul_fo_reg; + +reg [`uarraysize-1:0] mulout_ih_reg,mulout_fh_reg,mulout_oh_reg,mulout_ch_reg; +reg [`varraysize-1:0] mulout_ix_reg,mulout_fx_reg,mulout_ox_reg,mulout_cx_reg; + +reg [15:0] sig_oo_d1,sig_oo_d2,sig_oo_d3,sig_oo_d4,sig_oo_d5; + +always @(posedge clk) begin + +//Pipeline Registers + mulout_fx_reg <= mulout_fx; + mulout_fh_reg <= mulout_fh; + mac_fx_reg <= macout_fx; + mac_fh_reg <= macout_fh; + add_f_reg <= add_f; + addb_f_reg <= addbias_f; + sig_fo_reg <= sig_fo; + elmul_fo_reg <= elmul_fo; //check if need to delay to wait for elmul_co + + mulout_ix_reg <= mulout_ix; + mulout_ih_reg <= mulout_ih; + mac_ix_reg <= macout_ix; + mac_ih_reg <= macout_ih; + add_i_reg <= add_i; + addb_i_reg <= addbias_i; + sig_io_reg <= sig_io; + + mulout_ox_reg <= mulout_ox; + mulout_oh_reg <= mulout_oh; + mac_ox_reg <= macout_ox; + mac_oh_reg <= macout_oh; + add_o_reg <= add_o; + addb_o_reg <= addbias_o; + sig_oo_reg <= sig_oo; + + + sig_oo_d1 <= sig_oo_reg; //delaying sig_oo by 5 cycles to feed to c gate + sig_oo_d2 <= sig_oo_d1; + sig_oo_d3 <= sig_oo_d2; + sig_oo_d4 <= sig_oo_d3; + sig_oo_d5 <= sig_oo_d4; + + mulout_cx_reg <= mulout_cx; + mulout_ch_reg <= mulout_ch; + mac_cx_reg <= macout_cx; + mac_ch_reg <= macout_ch; + add_c_reg <= add_c; + addb_c_reg <= addbias_c; + tan_c_reg <= tan_c; + elmul_co_reg <= elmul_co; + add_cf_reg <= add_cf; + tan_h_reg <= tan_h; + +end + + +//FORGET GATE + vecmat_mul_x #(`varraysize,`INPUT_DEPTH) f_gatex(.clk(clk),.reset(rst),.data(x_in),.W(Wf_in),.tmp(mulout_fx)); + vecmat_mul_h #(`uarraysize,`ARRAY_DEPTH) f_gateh(.clk(clk),.reset(rst),.data(h_in),.W(Uf_in),.tmp(mulout_fh)); + vecmat_add_x #(`varraysize,`INPUT_DEPTH) f_gateaddx(.clk(clk),.reset(rst),.mulout(mulout_fx_reg),.data_out(macout_fx)); + vecmat_add_h #(`uarraysize,`ARRAY_DEPTH) f_gateaddh(.clk(clk),.reset(rst),.mulout(mulout_fh_reg),.data_out(macout_fh)); + qadd2 f_gate_add(.a(mac_fx_reg),.b(mac_fh_reg),.c(add_f)); + qadd2 f_gate_biasadd(.a(bf_in),.b(add_f),.c(addbias_f)); + sigmoid sigf(addb_f_reg,sig_fo); + //qmult #(12,16) f_elmul(.i_multiplicand(sig_fo_reg),.i_multiplier(C_in),.o_result(elmul_fo),.ovr(overflow0)); + signedmul f_elmul(.clk(clk),.a(sig_fo_reg),.b(C_in),.c(elmul_fo)); + +//INPUT GATE + vecmat_mul_x #(`varraysize,`INPUT_DEPTH) i_gatex(.clk(clk),.reset(rst),.data(x_in),.W(Wi_in),.tmp(mulout_ix)); + vecmat_mul_h #(`uarraysize,`ARRAY_DEPTH) i_gateh(.clk(clk),.reset(rst),.data(h_in),.W(Ui_in),.tmp(mulout_ih)); + vecmat_add_x #(`varraysize,`INPUT_DEPTH) i_gateaddx(.clk(clk),.reset(rst),.mulout(mulout_ix_reg),.data_out(macout_ix)); + vecmat_add_h #(`uarraysize,`ARRAY_DEPTH) i_gateaddh(.clk(clk),.reset(rst),.mulout(mulout_ih_reg),.data_out(macout_ih)); + qadd2 i_gate_add(.a(mac_ix_reg),.b(mac_ih_reg),.c(add_i)); + qadd2 i_gate_biasadd(.a(bi_in),.b(add_i),.c(addbias_i)); + sigmoid sigi(addb_i_reg,sig_io); + +//OUTPUT GATE + vecmat_mul_x #(`varraysize,`INPUT_DEPTH) o_gatex(.clk(clk),.reset(rst),.data(x_in),.W(Wo_in),.tmp(mulout_ox)); + vecmat_mul_h #(`uarraysize,`ARRAY_DEPTH) o_gateh(.clk(clk),.reset(rst),.data(h_in),.W(Uo_in),.tmp(mulout_oh)); + vecmat_add_x #(`varraysize,`INPUT_DEPTH) o_gateaddx(.clk(clk),.reset(rst),.mulout(mulout_ox_reg),.data_out(macout_ox)); + vecmat_add_h #(`uarraysize,`ARRAY_DEPTH) o_gateaddh(.clk(clk),.reset(rst),.mulout(mulout_oh_reg),.data_out(macout_oh)); + qadd2 o_gate_add(.a(mac_ox_reg),.b(mac_oh_reg),.c(add_o)); + qadd2 o_gate_biasadd(.a(bo_in),.b(add_o),.c(addbias_o)); + sigmoid sigo(addb_o_reg,sig_oo); + +//CELL STATE GATE + vecmat_mul_x #(`varraysize,`INPUT_DEPTH) c_gatex(.clk(clk),.reset(rst),.data(x_in),.W(Wc_in),.tmp(mulout_cx)); + vecmat_mul_h #(`uarraysize,`ARRAY_DEPTH) c_gateh(.clk(clk),.reset(rst),.data(h_in),.W(Uc_in),.tmp(mulout_ch)); + vecmat_add_x #(`varraysize,`INPUT_DEPTH) c_gateaddx(.clk(clk),.reset(rst),.mulout(mulout_cx_reg),.data_out(macout_cx)); + vecmat_add_h #(`uarraysize,`ARRAY_DEPTH) c_gateaddh(.clk(clk),.reset(rst),.mulout(mulout_ch_reg),.data_out(macout_ch)); + qadd2 c_gate_add(.a(mac_cx_reg),.b(mac_ch_reg),.c(add_c)); + qadd2 c_gate_biasadd(.a(bc_in),.b(add_c),.c(addbias_c)); + tanh tan_c1(addb_c_reg,tan_c); + //qmult #(12,16) c_elmul(.i_multiplicand(tan_c_reg),.i_multiplier(sig_io_reg),.o_result(elmul_co),.ovr(overflow0)); + signedmul c_elmul(.clk(clk),.a(tan_c_reg),.b(sig_io_reg),.c(elmul_co)); + qadd2 cf_gate_add(.a(elmul_co_reg),.b(elmul_fo_reg),.c(add_cf)); + tanh tan_c2(add_cf_reg,tan_h); + //qmult #(12,16) h_elmul(.i_multiplicand(tan_h_reg),.i_multiplier(sig_oo_d3),.o_result(ht),.ovr(overflow0)); + signedmul h_elmul(.clk(clk),.a(tan_h_reg),.b(sig_oo_d5),.c(ht)); + + + +endmodule + + +module vecmat_mul_h #( parameter uarraysize=1024,parameter vectwidth=64) //,matsize=64) // varraysize=1024 vectwidth=64,matsize=4096 +( + input clk, + input reset, + input [uarraysize-1:0] data, + input [uarraysize-1:0] W, + //output reg [15:0] data_out + output [uarraysize-1:0] tmp + ); + + //wire [uarraysize-1:0] tmp; + + reg [uarraysize-1:0] matrix; + reg [uarraysize-1:0] vector; + + + always @(posedge clk) begin + if(~reset) begin + + vector <= data; + matrix <= W; + + end + end + + /*genvar j; + generate + for (j=0;j= 12'h000) && (x[11:0] <= 12'h333)) // -3 + begin + address = 6'd8; + end + else if((x[11:0] > 12'h333) && (x[11:0] <= 12'h666)) + begin + address = 6'd9; + end + else if((x[11:0] > 12'h666) && (x[11:0] <= 12'h99a)) + begin + address = 6'd10; + end + else if((x[11:0] > 12'h99a) && (x[11:0] <= 12'hccd)) + begin + address = 6'd11; + end + else + begin + address = 6'd12; + end + 4'b1110:if((x[11:0] >= 12'h000) && (x[11:0] <= 12'h333)) // -2 + begin + address = 6'd13; + end + else if((x[11:0] > 12'h333) && (x[11:0] <= 12'h666)) + begin + address = 6'd14; + end + else if((x[11:0] > 12'h666) && (x[11:0] <= 12'h99a)) + begin + address = 6'd15; + end + else if((x[11:0] > 12'h99a) && (x[11:0] <= 12'hccd)) + begin + address = 6'd16; + end + else + begin + address = 6'd17; + end + 4'b1111:if((x[11:0] >= 12'h000) && (x[11:0] <= 12'h333)) // -1 + begin + address = 6'd18; + end + else if((x[11:0] > 12'h333) && (x[11:0] <= 12'h666)) + begin + address = 6'd19; + end + else if((x[11:0] > 12'h666) && (x[11:0] <= 12'h99a)) + begin + address = 6'd20; + end + else if((x[11:0] > 12'h99a) && (x[11:0] <= 12'hccd)) + begin + address = 6'd21; + end + else + begin + address = 6'd22; + end + 4'b0000:if((x[11:0] >= 12'h000) && (x[11:0] <= 12'h333)) // 0 + begin + address = 6'd23; + end + else if((x[11:0] > 12'h333) && (x[11:0] <= 12'h666)) + begin + address = 6'd24; + end + else if((x[11:0] > 12'h666) && (x[11:0] <= 12'h99a)) + begin + address = 6'd25; + end + else if((x[11:0] > 12'h99a) && (x[11:0] <= 12'hccd)) + begin + address = 6'd26; + end + else + begin + address = 6'd27; + end + 4'b0001:if((x[11:0] >= 12'h000) && (x[11:0] <= 12'h333)) // 1 + begin + address = 6'd28; + end + else if((x[11:0] > 12'h333) && (x[11:0] <= 12'h666)) + begin + address = 6'd29; + end + else if((x[11:0] > 12'h666) && (x[11:0] <= 12'h99a)) + begin + address = 6'd30; + end + else if((x[11:0] > 12'h99a) && (x[11:0] <= 12'hccd)) + begin + address = 6'd31; + end + else + begin + address = 6'd32; + end + 4'b0010:if((x[11:0] >= 12'h000) && (x[11:0] <= 12'h333)) // 2 + begin + address = 6'd33; + end + else if((x[11:0] > 12'h333) && (x[11:0] <= 12'h666)) + begin + address = 6'd34; + end + else if((x[11:0] > 12'h666) && (x[11:0] <= 12'h99a)) + begin + address = 6'd35; + end + else if((x[11:0] > 12'h99a) && (x[11:0] <= 12'hccd)) + begin + address = 6'd36; + end + else + begin + address = 6'd37; + end + 4'b0011:if((x[11:0] >= 12'h000) && (x[11:0] <= 12'h333)) // 3 + begin + address = 6'd38; + end + else if((x[11:0] > 12'h333) && (x[11:0] <= 12'h666)) + begin + address = 6'd39; + end + else if((x[11:0] > 12'h666) && (x[11:0] <= 12'h99a)) + begin + address = 6'd40; + end + else if((x[11:0] > 12'h99a) && (x[11:0] <= 12'hccd)) + begin + address = 6'd41; + end + else + begin + address = 6'd42; + end + 4'b0100:address = 6'd49; + 4'b0101:address = 6'd49; + 4'b0110:address = 6'd49; + 4'b0111:address = 6'd49; + /* 4'b0100:if((x[11:0] >= 12'h000) && (x[11:0] <= 12'h333)) //4 + begin + address = lut[43]; + end + else if((x[11:0] > 12'h333) && (x[11:0] <= 12'h666)) + begin + address = lut[44]; + end + else if((x[11:0] > 12'h666) && (x[11:0] <= 12'h99a)) + begin + address = lut[45]; + end + else if(x[11:0] > 12'h99a) + begin + address = lut[46]; + end + 4'b0101: address = lut[46]; + 4'b0110: address = lut[46]; + 4'b0111: address = lut[46]; */ + /*default:begin + address = 16'h1000; + end*/ + endcase + +end + +endmodule + +module tanh( +input [15:0] x, +output [15:0] tanh_out); + +reg [15:0] lut; +wire [15:0] x_comp; +reg [15:0] tanh_comp; +//reg [15:0] tanh; +reg [4:0] address; + + +assign x_comp = x[15]? {1'b0,~(x[14:0])}+1'b1:x; // first take 2's complement if x is negative +assign tanh_out = x[15]?(~lut+1'b1):lut; // take 2's complement of tanh if x was negative + +always @(address, x_comp) +begin + case(address) + 5'd0: lut =16'b0000100000000010; //address(0.55) + 5'd1: lut=16'b0000100100100101; //address(0.65) + 5'd2: lut=16'b0000101000101001; //address(0.75) + 5'd3: lut=16'b0000101100001110; //address(0.85) + 5'd4: lut=16'b0000101111010110; //address(0.95) + 5'd5: lut=16'b0000110010000010; //address(1.05) + 5'd6: lut=16'b0000110100010101; //address(1.15) + 5'd7: lut=16'b0000110110010010; //address(1.25) + 5'd8: lut=16'b0000110111111100; //address(1.35) + 5'd9: lut=16'b0000111001010100; //address(1.45) + 5'd10: lut=16'b0000111010011110; //address(1.55) + 5'd11: lut=16'b0000111011011100; //address(1.65) + 5'd12: lut=16'b0000111100001111; //address(1.75) + 5'd13: lut=16'b0000111100111010; //address(1.85) + 5'd14: lut=16'b0000111101011101; //address(1.95) + 5'd15: lut=16'b0000111101111010; //address(2.05) + 5'd16: lut=16'b0000111110010010; //address(2.15) + 5'd17: lut=16'b0000111110100110; //address(2.25) + 5'd18: lut=16'b0000111110110110; //address(2.35) + 5'd19: lut=16'b0000111111000011; //address(2.45) + 5'd20: lut=16'b0000111111001110; //address(2.55) + 5'd21: lut=16'b0000111111101011; //address(3.0) + 5'd22: lut=16'b0001000000000000; //1 + 5'd23: lut=x_comp; + default: lut=0; + endcase +end + +always@(x_comp) +begin + /*if(rst == 0) + tanh_out = 0; + else + begin*/ + // first take 2's complement if x is negative + /*if(x[15] == 1'b1) + begin + x_comp = {1'b0,~(x[14:0])}+1'b1; + end + else + begin + x_comp = x; + end*/ + + // next find the address + + if((x_comp >= 16'h0800) && (x_comp < 16'h3000)) + begin + case(x_comp[15:12]) + 4'b0000:begin + if((x_comp[11:0] >= 16'h800) && (x_comp[11:0] < 16'h99a)) + address = 5'd0; + else if((x_comp[11:0] >= 16'h99a) && (x_comp[11:0] < 16'hb33)) + address = 5'd1; + else if((x_comp[11:0] >= 16'hb33) && (x_comp[11:0] < 16'hccd)) + address = 5'd2; + else if((x_comp[11:0] >= 16'hccd) && (x_comp[11:0] < 16'he66)) + address = 5'd3; + else + address = 5'd4; + end + 4'b0001:begin + if((x_comp[11:0] >= 16'h000) && (x_comp[11:0] < 16'h19a)) + address = 5'd5; + else if((x_comp[11:0] >= 16'h19a) && (x_comp[11:0] < 16'h333)) + address = 5'd6; + else if((x_comp[11:0] >= 16'h333) && (x_comp[11:0] < 16'h4cd)) + address = 5'd7; + else if((x_comp[11:0] >= 16'h4cd) && (x_comp[11:0] < 16'h666)) + address = 5'd8; + else if((x_comp[11:0] >= 16'h666) && (x_comp[11:0] < 16'h800)) + address = 5'd9; + else if((x_comp[11:0] >= 16'h800) && (x_comp[11:0] < 16'h99a)) + address = 5'd10; + else if((x_comp[11:0] >= 16'h99a) && (x_comp[11:0] < 16'hb33)) + address = 5'd11; + else if((x_comp[11:0] >= 16'hb33) && (x_comp[11:0] < 16'hccd)) + address = 5'd12; + else if((x_comp[11:0] >= 16'hccd) && (x_comp[11:0] < 16'he66)) + address = 5'd13; + else + address = 5'd14; + end + 4'b0010:begin + if((x_comp[11:0] >= 16'h000) && (x_comp[11:0] < 16'h19a)) + address = 5'd15; + else if((x_comp[11:0] >= 16'h19a) && (x_comp[11:0] < 16'h333)) + address = 5'd16; + else if((x_comp[11:0] >= 16'h333) && (x_comp[11:0] < 16'h4cd)) + address = 5'd17; + else if((x_comp[11:0] >= 16'h4cd) && (x_comp[11:0] < 16'h666)) + address = 5'd18; + else if((x_comp[11:0] >= 16'h666) && (x_comp[11:0] < 16'h800)) + address = 5'd19; + else if((x_comp[11:0] >= 16'h800) && (x_comp[11:0] < 16'h99a)) + address = 5'd20; + else + address = 5'd21; + end + default: address = 0; + endcase + end + + else if((x_comp >= 16'h0000) && (x_comp < 16'h0800)) + begin + address = 5'd23; + end + else begin + address = 5'd22; + end + //end + +end + + +endmodule + + diff --git a/designs/koios/lstm/lstm_random.sv b/designs/koios/lstm/lstm_random.sv new file mode 100644 index 000000000..e1141238a --- /dev/null +++ b/designs/koios/lstm/lstm_random.sv @@ -0,0 +1,67 @@ +/* +Random I/Os for LSTM +*/ + +`include "../../random_number_generator.sv" + +`define ARRAY_DEPTH 64 //Number of Hidden neurons +`define input wire logic_DEPTH 100 //LSTM input wire logic vector dimensions +`define DATA_WIDTH 16 //16 bit representation +`define INWEIGHT_DEPTH 6400 //100x64 +`define HWEIGHT_DEPTH 4096 //64x64 +`define varraysize 1600 //100x16 +`define uarraysize 1024 //64x16 + +module lstm_random ( +input wire logic clk, +input wire logic reset, +input wire logic start, //start the computation +input wire logic [6:0] start_addr, //start address of the Xin bram (input wire logic words to LSTM) +input wire logic [6:0] end_addr, //end address of the Xin bram +input wire logic wren_a, +input wire logic [`DATA_WIDTH-1:0] wdata_b, +output logic ht_valid, //indicates the output logic ht_out is valid in those cycles +output logic [`DATA_WIDTH-1:0] ht_out, //output logic ht from the lstm +output logic cycle_complete, //generates a pulse when a cycle fo 64 ht output logics are complete +output logic Done //Stays high indicating the end of lstm output logic computation for all the Xin words provided. +); + +logic [`uarraysize-1:0] wdata_u; +RandomNumberGenerator #( + .RANDOM_WIDTH(`uarraysize), + .SEED(0) +) rng0 ( + .clk(clk), + .reset(reset), + .random_number(wdata_u) +); + +logic [`varraysize-1:0] wdata_v; +RandomNumberGenerator #( + .RANDOM_WIDTH(`varraysize), + .SEED(0) +) rng1 ( + .clk(clk), + .reset(reset), + .random_number(wdata_v) +); + + + +top lstm0( + clk, + reset, + start, //start the computation + start_addr, //start address of the Xin bram (input words to LSTM) + end_addr, //end address of the Xin bram + wren_a, + wdata_u, + wdata_v, + wdata_b, + ht_valid, //indicates the output ht_out is valid in those cycles + ht_out, //output ht from the lstm + cycle_complete, //generates a pulse when a cycle fo 64 ht outputs are complete + Done //Stays high indicating the end of lstm output computation for all the Xin words provided. +); + +endmodule \ No newline at end of file diff --git a/designs/koios/reduction_layer/design.yaml b/designs/koios/reduction_layer/design.yaml new file mode 100644 index 000000000..31f6e1cd6 --- /dev/null +++ b/designs/koios/reduction_layer/design.yaml @@ -0,0 +1 @@ +top: reduction_layer diff --git a/designs/koios/reduction_layer/reduction_layer.v b/designs/koios/reduction_layer/reduction_layer.v new file mode 100644 index 000000000..af462bb60 --- /dev/null +++ b/designs/koios/reduction_layer/reduction_layer.v @@ -0,0 +1,1368 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Aman Arora +////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////// +//Module to reduce multiple values (add, max, min) into one final result. +////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////// +// Numerics. We use fixed point format: +// Most significant 8 bits represent integer part and Least significant 8 bits +// represent fraction part +// i.e. IIIIIIIIFFFFFFFF = IIIIIIII.FFFFFFFF +////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////// +// There are 128 inputs to the reduction unit. We use a tree structure to reduce the 128 values. +// It is assumed that the number of addressses supplied (end_addr - start_addr + 1) is a multiple +// of 128. If the real application needs to reduce a number of values that are not a multiple of +// 128, then the application must pad the values in the input BRAM appropriately +////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////// +// A user is expected to use the resetn signal everytime before starting a new reduction operation. +////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////// +// Accumulation is done in 20 bits (16 + log(16)) +////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////// +// Each entry of the RAM contains `NUM_INPUTS (which is 128) values. So, +// 1 read of the RAM provides all the inputs required for going through +// the reduction unit once. +////////////////////////////////////////////////////////////////// + +`timescale 1ns/1ns +`define DWIDTH 16 +`define LOGDWIDTH 4 +`define AWIDTH 5 +`define MEM_SIZE 2048 +`define NUM_INPUTS 128 + +//////////////////////////////////////////// +// Top module +//////////////////////////////////////////// +module reduction_layer( + input clk, + input resetn, //resets the control logic and the processing elements + input start, //indicates start of the reduction operation + input [`AWIDTH-1:0] start_addr, //the starting address where the inputs are located (inclusive) + input [`AWIDTH-1:0] end_addr, //the end address where the inputs are located (inclusive) + input [1:0] reduction_type, //can have 3 values: 0 (Add), 1 (Max), 2 (Min) + input bram_in_we, //flag used to load the RAM with inputs from outside + input [`DWIDTH-1:0] bram_in_wdata_ext, //port to load RAM with inputs from outside (ideally we'd have AXI or some similar interface to load the RAM through a DMA module) + input [`AWIDTH-1:0] bram_in_addr_ext, //port to load RAM with inputs from outside (ideally we'd have AXI or some similar interface to load the RAM through a DMA module) + output [`DWIDTH-1:0] reduced_out, //output + output reg done //output is valid when done is 1 +); + +reg [`AWIDTH-1:0] bram_in_addr; +wire [`AWIDTH-1:0] bram_in_addr_muxed; +wire [`NUM_INPUTS*`DWIDTH-1:0] bram_in_wdata; +wire [`NUM_INPUTS*`DWIDTH-1:0] bram_in_rdata; +wire [`DWIDTH+`LOGDWIDTH-1:0] reduced_out_unrounded; +wire [`DWIDTH-1:0] reduced_out_add; + +//////////////////////////////////////////////////////////////// +//Ideally the RAM would be loaded using an AXI interface or something similar through a DMA engine. +//Here we've just exposed the write data and address bus to the top-level. +//Each data entry in the RAM is very wide (`NUM_INPUTS*`DWIDTH). That leads to lot of +//ports on the top-level, causing very long wires from RAM to/from IOs. To avoid this, +//we are just going to reduce the width of the port (to `DWIDTH) and just replicate +//that over tha actual data port of the BRAM `NUM_INPUTS times. This doesn't impact +//hardware/functionality of the core design. +assign bram_in_addr_muxed = bram_in_we ? bram_in_addr_ext : bram_in_addr; +assign bram_in_wdata = {`NUM_INPUTS{bram_in_wdata_ext}}; + +//////////////////////////////////////////////////////////////// +//Input matrix data is stored in this RAM +//The design reads 16 elements in one clock +//////////////////////////////////////////////////////////////// + +spram in_data( + .addr(bram_in_addr_muxed), + .d(bram_in_wdata), + .we(bram_in_we), + .q(bram_in_rdata), + .clk(clk)); + + +reg [3:0] state; +reg [3:0] count; +reg reset_reduction_unit; + +//////////////////////////////////////////////////////////////// +// Control logic +//////////////////////////////////////////////////////////////// + always @( posedge clk) begin + if (resetn == 1'b0) begin + state <= 4'b0000; + count <= 0; + done <= 0; + reset_reduction_unit <= 1; + end + else begin + case (state) + 4'b0000: begin + //Stay here until start becomes 1. Keep the processing + //elements in reset because we don't need them yet. + if (start == 1'b1) begin + state <= 4'b0001; + end + done <= 0; + reset_reduction_unit <= 1; + end + + 4'b0001: begin + state <= 4'b0010; + //Set correct read address for the BRAM containing input values + //so that the values are available in the next cycle + bram_in_addr <= start_addr; + reset_reduction_unit <= 1; + end + + 4'b0010: begin + //During this state, the values for the address set in previous state + //are available at the read-output of the BRAM. + //Now let's lift the reset from the processing elements. + reset_reduction_unit <= 0; + //If we have reached the end condition (that is, we have + //read all the entries from start_addr to end_addr), let's + //move to the next state (that state doesn't read the RAM any more) + if (bram_in_addr == end_addr) begin + //end the loop + state <= 4'b1110; + end + else begin + //Increment BRAM addr, so we can fetch the next data in the next cycle + bram_in_addr <= bram_in_addr + 1'b1; + end + end + + 4'b1110: begin + //The full operation ends after all the locations have been read + //(and data fed to the reduction unit) and initiation interval + //(latency) has passed. So, let's count for the initiation interval + //and then assert done and go back to the initial state. + if (count==5) begin + state <= 4'b0000; + count <= 0; + done <= 1; + reset_reduction_unit <= 1; + end + else begin + count <= count + 1'b1; + end + end + endcase + end + end + + +//////////////////////////////////////////////////////////////// +// Let's instantiate the unit that actually performs the reduction +//////////////////////////////////////////////////////////////// + +reduction_unit ucu( + .clk(clk), + .reset(reset_reduction_unit), + .inp0(bram_in_rdata[1*`DWIDTH-1:0*`DWIDTH]), + .inp1(bram_in_rdata[2*`DWIDTH-1:1*`DWIDTH]), + .inp2(bram_in_rdata[3*`DWIDTH-1:2*`DWIDTH]), + .inp3(bram_in_rdata[4*`DWIDTH-1:3*`DWIDTH]), + .inp4(bram_in_rdata[5*`DWIDTH-1:4*`DWIDTH]), + .inp5(bram_in_rdata[6*`DWIDTH-1:5*`DWIDTH]), + .inp6(bram_in_rdata[7*`DWIDTH-1:6*`DWIDTH]), + .inp7(bram_in_rdata[8*`DWIDTH-1:7*`DWIDTH]), + .inp8(bram_in_rdata[9*`DWIDTH-1:8*`DWIDTH]), + .inp9(bram_in_rdata[10*`DWIDTH-1:9*`DWIDTH]), + .inp10(bram_in_rdata[11*`DWIDTH-1:10*`DWIDTH]), + .inp11(bram_in_rdata[12*`DWIDTH-1:11*`DWIDTH]), + .inp12(bram_in_rdata[13*`DWIDTH-1:12*`DWIDTH]), + .inp13(bram_in_rdata[14*`DWIDTH-1:13*`DWIDTH]), + .inp14(bram_in_rdata[15*`DWIDTH-1:14*`DWIDTH]), + .inp15(bram_in_rdata[16*`DWIDTH-1:15*`DWIDTH]), + .inp16(bram_in_rdata[17*`DWIDTH-1:16*`DWIDTH]), + .inp17(bram_in_rdata[18*`DWIDTH-1:17*`DWIDTH]), + .inp18(bram_in_rdata[19*`DWIDTH-1:18*`DWIDTH]), + .inp19(bram_in_rdata[20*`DWIDTH-1:19*`DWIDTH]), + .inp20(bram_in_rdata[21*`DWIDTH-1:20*`DWIDTH]), + .inp21(bram_in_rdata[22*`DWIDTH-1:21*`DWIDTH]), + .inp22(bram_in_rdata[23*`DWIDTH-1:22*`DWIDTH]), + .inp23(bram_in_rdata[24*`DWIDTH-1:23*`DWIDTH]), + .inp24(bram_in_rdata[25*`DWIDTH-1:24*`DWIDTH]), + .inp25(bram_in_rdata[26*`DWIDTH-1:25*`DWIDTH]), + .inp26(bram_in_rdata[27*`DWIDTH-1:26*`DWIDTH]), + .inp27(bram_in_rdata[28*`DWIDTH-1:27*`DWIDTH]), + .inp28(bram_in_rdata[29*`DWIDTH-1:28*`DWIDTH]), + .inp29(bram_in_rdata[30*`DWIDTH-1:29*`DWIDTH]), + .inp30(bram_in_rdata[31*`DWIDTH-1:30*`DWIDTH]), + .inp31(bram_in_rdata[32*`DWIDTH-1:31*`DWIDTH]), + .inp32(bram_in_rdata[33*`DWIDTH-1:32*`DWIDTH]), + .inp33(bram_in_rdata[34*`DWIDTH-1:33*`DWIDTH]), + .inp34(bram_in_rdata[35*`DWIDTH-1:34*`DWIDTH]), + .inp35(bram_in_rdata[36*`DWIDTH-1:35*`DWIDTH]), + .inp36(bram_in_rdata[37*`DWIDTH-1:36*`DWIDTH]), + .inp37(bram_in_rdata[38*`DWIDTH-1:37*`DWIDTH]), + .inp38(bram_in_rdata[39*`DWIDTH-1:38*`DWIDTH]), + .inp39(bram_in_rdata[40*`DWIDTH-1:39*`DWIDTH]), + .inp40(bram_in_rdata[41*`DWIDTH-1:40*`DWIDTH]), + .inp41(bram_in_rdata[42*`DWIDTH-1:41*`DWIDTH]), + .inp42(bram_in_rdata[43*`DWIDTH-1:42*`DWIDTH]), + .inp43(bram_in_rdata[44*`DWIDTH-1:43*`DWIDTH]), + .inp44(bram_in_rdata[45*`DWIDTH-1:44*`DWIDTH]), + .inp45(bram_in_rdata[46*`DWIDTH-1:45*`DWIDTH]), + .inp46(bram_in_rdata[47*`DWIDTH-1:46*`DWIDTH]), + .inp47(bram_in_rdata[48*`DWIDTH-1:47*`DWIDTH]), + .inp48(bram_in_rdata[49*`DWIDTH-1:48*`DWIDTH]), + .inp49(bram_in_rdata[50*`DWIDTH-1:49*`DWIDTH]), + .inp50(bram_in_rdata[51*`DWIDTH-1:50*`DWIDTH]), + .inp51(bram_in_rdata[52*`DWIDTH-1:51*`DWIDTH]), + .inp52(bram_in_rdata[53*`DWIDTH-1:52*`DWIDTH]), + .inp53(bram_in_rdata[54*`DWIDTH-1:53*`DWIDTH]), + .inp54(bram_in_rdata[55*`DWIDTH-1:54*`DWIDTH]), + .inp55(bram_in_rdata[56*`DWIDTH-1:55*`DWIDTH]), + .inp56(bram_in_rdata[57*`DWIDTH-1:56*`DWIDTH]), + .inp57(bram_in_rdata[58*`DWIDTH-1:57*`DWIDTH]), + .inp58(bram_in_rdata[59*`DWIDTH-1:58*`DWIDTH]), + .inp59(bram_in_rdata[60*`DWIDTH-1:59*`DWIDTH]), + .inp60(bram_in_rdata[61*`DWIDTH-1:60*`DWIDTH]), + .inp61(bram_in_rdata[62*`DWIDTH-1:61*`DWIDTH]), + .inp62(bram_in_rdata[63*`DWIDTH-1:62*`DWIDTH]), + .inp63(bram_in_rdata[64*`DWIDTH-1:63*`DWIDTH]), + .inp64(bram_in_rdata[65*`DWIDTH-1:64*`DWIDTH]), + .inp65(bram_in_rdata[66*`DWIDTH-1:65*`DWIDTH]), + .inp66(bram_in_rdata[67*`DWIDTH-1:66*`DWIDTH]), + .inp67(bram_in_rdata[68*`DWIDTH-1:67*`DWIDTH]), + .inp68(bram_in_rdata[69*`DWIDTH-1:68*`DWIDTH]), + .inp69(bram_in_rdata[70*`DWIDTH-1:69*`DWIDTH]), + .inp70(bram_in_rdata[71*`DWIDTH-1:70*`DWIDTH]), + .inp71(bram_in_rdata[72*`DWIDTH-1:71*`DWIDTH]), + .inp72(bram_in_rdata[73*`DWIDTH-1:72*`DWIDTH]), + .inp73(bram_in_rdata[74*`DWIDTH-1:73*`DWIDTH]), + .inp74(bram_in_rdata[75*`DWIDTH-1:74*`DWIDTH]), + .inp75(bram_in_rdata[76*`DWIDTH-1:75*`DWIDTH]), + .inp76(bram_in_rdata[77*`DWIDTH-1:76*`DWIDTH]), + .inp77(bram_in_rdata[78*`DWIDTH-1:77*`DWIDTH]), + .inp78(bram_in_rdata[79*`DWIDTH-1:78*`DWIDTH]), + .inp79(bram_in_rdata[80*`DWIDTH-1:79*`DWIDTH]), + .inp80(bram_in_rdata[81*`DWIDTH-1:80*`DWIDTH]), + .inp81(bram_in_rdata[82*`DWIDTH-1:81*`DWIDTH]), + .inp82(bram_in_rdata[83*`DWIDTH-1:82*`DWIDTH]), + .inp83(bram_in_rdata[84*`DWIDTH-1:83*`DWIDTH]), + .inp84(bram_in_rdata[85*`DWIDTH-1:84*`DWIDTH]), + .inp85(bram_in_rdata[86*`DWIDTH-1:85*`DWIDTH]), + .inp86(bram_in_rdata[87*`DWIDTH-1:86*`DWIDTH]), + .inp87(bram_in_rdata[88*`DWIDTH-1:87*`DWIDTH]), + .inp88(bram_in_rdata[89*`DWIDTH-1:88*`DWIDTH]), + .inp89(bram_in_rdata[90*`DWIDTH-1:89*`DWIDTH]), + .inp90(bram_in_rdata[91*`DWIDTH-1:90*`DWIDTH]), + .inp91(bram_in_rdata[92*`DWIDTH-1:91*`DWIDTH]), + .inp92(bram_in_rdata[93*`DWIDTH-1:92*`DWIDTH]), + .inp93(bram_in_rdata[94*`DWIDTH-1:93*`DWIDTH]), + .inp94(bram_in_rdata[95*`DWIDTH-1:94*`DWIDTH]), + .inp95(bram_in_rdata[96*`DWIDTH-1:95*`DWIDTH]), + .inp96(bram_in_rdata[97*`DWIDTH-1:96*`DWIDTH]), + .inp97(bram_in_rdata[98*`DWIDTH-1:97*`DWIDTH]), + .inp98(bram_in_rdata[99*`DWIDTH-1:98*`DWIDTH]), + .inp99(bram_in_rdata[100*`DWIDTH-1:99*`DWIDTH]), + .inp100(bram_in_rdata[101*`DWIDTH-1:100*`DWIDTH]), + .inp101(bram_in_rdata[102*`DWIDTH-1:101*`DWIDTH]), + .inp102(bram_in_rdata[103*`DWIDTH-1:102*`DWIDTH]), + .inp103(bram_in_rdata[104*`DWIDTH-1:103*`DWIDTH]), + .inp104(bram_in_rdata[105*`DWIDTH-1:104*`DWIDTH]), + .inp105(bram_in_rdata[106*`DWIDTH-1:105*`DWIDTH]), + .inp106(bram_in_rdata[107*`DWIDTH-1:106*`DWIDTH]), + .inp107(bram_in_rdata[108*`DWIDTH-1:107*`DWIDTH]), + .inp108(bram_in_rdata[109*`DWIDTH-1:108*`DWIDTH]), + .inp109(bram_in_rdata[110*`DWIDTH-1:109*`DWIDTH]), + .inp110(bram_in_rdata[111*`DWIDTH-1:110*`DWIDTH]), + .inp111(bram_in_rdata[112*`DWIDTH-1:111*`DWIDTH]), + .inp112(bram_in_rdata[113*`DWIDTH-1:112*`DWIDTH]), + .inp113(bram_in_rdata[114*`DWIDTH-1:113*`DWIDTH]), + .inp114(bram_in_rdata[115*`DWIDTH-1:114*`DWIDTH]), + .inp115(bram_in_rdata[116*`DWIDTH-1:115*`DWIDTH]), + .inp116(bram_in_rdata[117*`DWIDTH-1:116*`DWIDTH]), + .inp117(bram_in_rdata[118*`DWIDTH-1:117*`DWIDTH]), + .inp118(bram_in_rdata[119*`DWIDTH-1:118*`DWIDTH]), + .inp119(bram_in_rdata[120*`DWIDTH-1:119*`DWIDTH]), + .inp120(bram_in_rdata[121*`DWIDTH-1:120*`DWIDTH]), + .inp121(bram_in_rdata[122*`DWIDTH-1:121*`DWIDTH]), + .inp122(bram_in_rdata[123*`DWIDTH-1:122*`DWIDTH]), + .inp123(bram_in_rdata[124*`DWIDTH-1:123*`DWIDTH]), + .inp124(bram_in_rdata[125*`DWIDTH-1:124*`DWIDTH]), + .inp125(bram_in_rdata[126*`DWIDTH-1:125*`DWIDTH]), + .inp126(bram_in_rdata[127*`DWIDTH-1:126*`DWIDTH]), + .inp127(bram_in_rdata[128*`DWIDTH-1:127*`DWIDTH]), + .mode(reduction_type), + .outp(reduced_out_unrounded) +); + +//////////////////////////////////////////////////////////////// +// Rounding of the output of reduction unit (from 20 bits to 16 bits). +// This is required only when reduction type is "sum" +//////////////////////////////////////////////////////////////// +rounding #(`DWIDTH+`LOGDWIDTH, `DWIDTH) u_round(.i_data(reduced_out_unrounded), .o_data(reduced_out_add)); + +assign reduced_out = (reduction_type==2'b0) ? reduced_out_add : reduced_out_unrounded[`DWIDTH-1:0]; + +endmodule + + +////////////////////////////////// +//Single port RAM. Stores the inputs. +////////////////////////////////// +module spram ( + addr, + d, + we, + q, + clk); + +input [`AWIDTH-1:0] addr; +input [`NUM_INPUTS*`DWIDTH-1:0] d; +input we; +output reg [`NUM_INPUTS*`DWIDTH-1:0] q; +input clk; + +`ifndef hard_mem + +reg [`NUM_INPUTS*`DWIDTH-1:0] ram[((1<<`AWIDTH)-1):0]; + +always @(posedge clk) +begin + if (we) + ram[addr] <= d; + else + q <= ram[addr]; +end + +`else + +defparam u_single_port_ram.ADDR_WIDTH = `AWIDTH; +defparam u_single_port_ram.DATA_WIDTH = `NUM_INPUTS*`DWIDTH; + +single_port_ram u_single_port_ram( +.addr(addr), +.we(we), +.data(d), +.out(q), +.clk(clk) +); + +`endif + +endmodule + + +/////////////////////////////////////////////////////// +// Reduction unit. It's a tree of processing elements. +// There are 128 inputs and one output and 8 stages. +// +// The output is +// wider (more bits) than the inputs. It has logN more +// bits (if N is the number of bits in the inputs). This +// is based on https://zipcpu.com/dsp/2017/07/22/rounding.html. +// +// The last stage is special. It adds the previous +// result. This is useful when we have more than 128 inputs +// to reduce. We send the next set of 128 inputs in the next +// clock after the first set. +// +// Each stage of the tree is pipelined. +/////////////////////////////////////////////////////// +module reduction_unit( + clk, + reset, + inp0, + inp1, + inp2, + inp3, + inp4, + inp5, + inp6, + inp7, + inp8, + inp9, + inp10, + inp11, + inp12, + inp13, + inp14, + inp15, + inp16, + inp17, + inp18, + inp19, + inp20, + inp21, + inp22, + inp23, + inp24, + inp25, + inp26, + inp27, + inp28, + inp29, + inp30, + inp31, + inp32, + inp33, + inp34, + inp35, + inp36, + inp37, + inp38, + inp39, + inp40, + inp41, + inp42, + inp43, + inp44, + inp45, + inp46, + inp47, + inp48, + inp49, + inp50, + inp51, + inp52, + inp53, + inp54, + inp55, + inp56, + inp57, + inp58, + inp59, + inp60, + inp61, + inp62, + inp63, + inp64, + inp65, + inp66, + inp67, + inp68, + inp69, + inp70, + inp71, + inp72, + inp73, + inp74, + inp75, + inp76, + inp77, + inp78, + inp79, + inp80, + inp81, + inp82, + inp83, + inp84, + inp85, + inp86, + inp87, + inp88, + inp89, + inp90, + inp91, + inp92, + inp93, + inp94, + inp95, + inp96, + inp97, + inp98, + inp99, + inp100, + inp101, + inp102, + inp103, + inp104, + inp105, + inp106, + inp107, + inp108, + inp109, + inp110, + inp111, + inp112, + inp113, + inp114, + inp115, + inp116, + inp117, + inp118, + inp119, + inp120, + inp121, + inp122, + inp123, + inp124, + inp125, + inp126, + inp127, + + mode, + outp +); + + input clk; + input reset; + input [`DWIDTH-1 : 0] inp0; + input [`DWIDTH-1 : 0] inp1; + input [`DWIDTH-1 : 0] inp2; + input [`DWIDTH-1 : 0] inp3; + input [`DWIDTH-1 : 0] inp4; + input [`DWIDTH-1 : 0] inp5; + input [`DWIDTH-1 : 0] inp6; + input [`DWIDTH-1 : 0] inp7; + input [`DWIDTH-1 : 0] inp8; + input [`DWIDTH-1 : 0] inp9; + input [`DWIDTH-1 : 0] inp10; + input [`DWIDTH-1 : 0] inp11; + input [`DWIDTH-1 : 0] inp12; + input [`DWIDTH-1 : 0] inp13; + input [`DWIDTH-1 : 0] inp14; + input [`DWIDTH-1 : 0] inp15; + input [`DWIDTH-1 : 0] inp16; + input [`DWIDTH-1 : 0] inp17; + input [`DWIDTH-1 : 0] inp18; + input [`DWIDTH-1 : 0] inp19; + input [`DWIDTH-1 : 0] inp20; + input [`DWIDTH-1 : 0] inp21; + input [`DWIDTH-1 : 0] inp22; + input [`DWIDTH-1 : 0] inp23; + input [`DWIDTH-1 : 0] inp24; + input [`DWIDTH-1 : 0] inp25; + input [`DWIDTH-1 : 0] inp26; + input [`DWIDTH-1 : 0] inp27; + input [`DWIDTH-1 : 0] inp28; + input [`DWIDTH-1 : 0] inp29; + input [`DWIDTH-1 : 0] inp30; + input [`DWIDTH-1 : 0] inp31; + input [`DWIDTH-1 : 0] inp32; + input [`DWIDTH-1 : 0] inp33; + input [`DWIDTH-1 : 0] inp34; + input [`DWIDTH-1 : 0] inp35; + input [`DWIDTH-1 : 0] inp36; + input [`DWIDTH-1 : 0] inp37; + input [`DWIDTH-1 : 0] inp38; + input [`DWIDTH-1 : 0] inp39; + input [`DWIDTH-1 : 0] inp40; + input [`DWIDTH-1 : 0] inp41; + input [`DWIDTH-1 : 0] inp42; + input [`DWIDTH-1 : 0] inp43; + input [`DWIDTH-1 : 0] inp44; + input [`DWIDTH-1 : 0] inp45; + input [`DWIDTH-1 : 0] inp46; + input [`DWIDTH-1 : 0] inp47; + input [`DWIDTH-1 : 0] inp48; + input [`DWIDTH-1 : 0] inp49; + input [`DWIDTH-1 : 0] inp50; + input [`DWIDTH-1 : 0] inp51; + input [`DWIDTH-1 : 0] inp52; + input [`DWIDTH-1 : 0] inp53; + input [`DWIDTH-1 : 0] inp54; + input [`DWIDTH-1 : 0] inp55; + input [`DWIDTH-1 : 0] inp56; + input [`DWIDTH-1 : 0] inp57; + input [`DWIDTH-1 : 0] inp58; + input [`DWIDTH-1 : 0] inp59; + input [`DWIDTH-1 : 0] inp60; + input [`DWIDTH-1 : 0] inp61; + input [`DWIDTH-1 : 0] inp62; + input [`DWIDTH-1 : 0] inp63; + input [`DWIDTH-1 : 0] inp64; + input [`DWIDTH-1 : 0] inp65; + input [`DWIDTH-1 : 0] inp66; + input [`DWIDTH-1 : 0] inp67; + input [`DWIDTH-1 : 0] inp68; + input [`DWIDTH-1 : 0] inp69; + input [`DWIDTH-1 : 0] inp70; + input [`DWIDTH-1 : 0] inp71; + input [`DWIDTH-1 : 0] inp72; + input [`DWIDTH-1 : 0] inp73; + input [`DWIDTH-1 : 0] inp74; + input [`DWIDTH-1 : 0] inp75; + input [`DWIDTH-1 : 0] inp76; + input [`DWIDTH-1 : 0] inp77; + input [`DWIDTH-1 : 0] inp78; + input [`DWIDTH-1 : 0] inp79; + input [`DWIDTH-1 : 0] inp80; + input [`DWIDTH-1 : 0] inp81; + input [`DWIDTH-1 : 0] inp82; + input [`DWIDTH-1 : 0] inp83; + input [`DWIDTH-1 : 0] inp84; + input [`DWIDTH-1 : 0] inp85; + input [`DWIDTH-1 : 0] inp86; + input [`DWIDTH-1 : 0] inp87; + input [`DWIDTH-1 : 0] inp88; + input [`DWIDTH-1 : 0] inp89; + input [`DWIDTH-1 : 0] inp90; + input [`DWIDTH-1 : 0] inp91; + input [`DWIDTH-1 : 0] inp92; + input [`DWIDTH-1 : 0] inp93; + input [`DWIDTH-1 : 0] inp94; + input [`DWIDTH-1 : 0] inp95; + input [`DWIDTH-1 : 0] inp96; + input [`DWIDTH-1 : 0] inp97; + input [`DWIDTH-1 : 0] inp98; + input [`DWIDTH-1 : 0] inp99; + input [`DWIDTH-1 : 0] inp100; + input [`DWIDTH-1 : 0] inp101; + input [`DWIDTH-1 : 0] inp102; + input [`DWIDTH-1 : 0] inp103; + input [`DWIDTH-1 : 0] inp104; + input [`DWIDTH-1 : 0] inp105; + input [`DWIDTH-1 : 0] inp106; + input [`DWIDTH-1 : 0] inp107; + input [`DWIDTH-1 : 0] inp108; + input [`DWIDTH-1 : 0] inp109; + input [`DWIDTH-1 : 0] inp110; + input [`DWIDTH-1 : 0] inp111; + input [`DWIDTH-1 : 0] inp112; + input [`DWIDTH-1 : 0] inp113; + input [`DWIDTH-1 : 0] inp114; + input [`DWIDTH-1 : 0] inp115; + input [`DWIDTH-1 : 0] inp116; + input [`DWIDTH-1 : 0] inp117; + input [`DWIDTH-1 : 0] inp118; + input [`DWIDTH-1 : 0] inp119; + input [`DWIDTH-1 : 0] inp120; + input [`DWIDTH-1 : 0] inp121; + input [`DWIDTH-1 : 0] inp122; + input [`DWIDTH-1 : 0] inp123; + input [`DWIDTH-1 : 0] inp124; + input [`DWIDTH-1 : 0] inp125; + input [`DWIDTH-1 : 0] inp126; + input [`DWIDTH-1 : 0] inp127; + input [1:0] mode; + output [`DWIDTH+`LOGDWIDTH-1 : 0] outp; + + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute0_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute0_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute1_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute1_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute2_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute2_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute3_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute3_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute4_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute4_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute5_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute5_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute6_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute6_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute7_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute7_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute8_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute8_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute9_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute9_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute10_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute10_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute11_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute11_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute12_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute12_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute13_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute13_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute14_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute14_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute15_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute15_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute16_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute16_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute17_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute17_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute18_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute18_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute19_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute19_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute20_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute20_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute21_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute21_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute22_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute22_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute23_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute23_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute24_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute24_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute25_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute25_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute26_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute26_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute27_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute27_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute28_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute28_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute29_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute29_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute30_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute30_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute31_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute31_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute32_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute32_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute33_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute33_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute34_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute34_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute35_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute35_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute36_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute36_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute37_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute37_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute38_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute38_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute39_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute39_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute40_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute40_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute41_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute41_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute42_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute42_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute43_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute43_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute44_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute44_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute45_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute45_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute46_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute46_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute47_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute47_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute48_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute48_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute49_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute49_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute50_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute50_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute51_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute51_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute52_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute52_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute53_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute53_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute54_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute54_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute55_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute55_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute56_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute56_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute57_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute57_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute58_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute58_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute59_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute59_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute60_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute60_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute61_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute61_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute62_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute62_out_stage7_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute63_out_stage7; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute63_out_stage7_reg; + + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute0_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute0_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute1_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute1_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute2_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute2_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute3_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute3_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute4_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute4_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute5_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute5_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute6_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute6_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute7_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute7_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute8_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute8_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute9_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute9_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute10_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute10_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute11_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute11_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute12_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute12_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute13_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute13_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute14_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute14_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute15_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute15_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute16_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute16_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute17_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute17_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute18_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute18_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute19_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute19_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute20_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute20_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute21_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute21_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute22_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute22_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute23_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute23_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute24_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute24_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute25_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute25_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute26_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute26_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute27_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute27_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute28_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute28_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute29_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute29_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute30_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute30_out_stage6_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute31_out_stage6; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute31_out_stage6_reg; + + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute0_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute0_out_stage5_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute1_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute1_out_stage5_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute2_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute2_out_stage5_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute3_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute3_out_stage5_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute4_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute4_out_stage5_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute5_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute5_out_stage5_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute6_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute6_out_stage5_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute7_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute7_out_stage5_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute8_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute8_out_stage5_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute9_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute9_out_stage5_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute10_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute10_out_stage5_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute11_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute11_out_stage5_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute12_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute12_out_stage5_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute13_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute13_out_stage5_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute14_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute14_out_stage5_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute15_out_stage5; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute15_out_stage5_reg; + + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute0_out_stage4; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute0_out_stage4_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute1_out_stage4; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute1_out_stage4_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute2_out_stage4; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute2_out_stage4_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute3_out_stage4; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute3_out_stage4_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute4_out_stage4; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute4_out_stage4_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute5_out_stage4; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute5_out_stage4_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute6_out_stage4; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute6_out_stage4_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute7_out_stage4; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute7_out_stage4_reg; + + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute0_out_stage3; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute0_out_stage3_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute1_out_stage3; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute1_out_stage3_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute2_out_stage3; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute2_out_stage3_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute3_out_stage3; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute3_out_stage3_reg; + + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute0_out_stage2; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute0_out_stage2_reg; + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute1_out_stage2; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute1_out_stage2_reg; + + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute0_out_stage1; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] compute0_out_stage1_reg; + + wire [`DWIDTH+`LOGDWIDTH-1 : 0] compute0_out_stage0; + reg [`DWIDTH+`LOGDWIDTH-1 : 0] outp; + + always @(posedge clk) begin + if (reset) begin + outp <= 0; + compute0_out_stage7_reg <= 0; + compute1_out_stage7_reg <= 0; + compute2_out_stage7_reg <= 0; + compute3_out_stage7_reg <= 0; + compute4_out_stage7_reg <= 0; + compute5_out_stage7_reg <= 0; + compute6_out_stage7_reg <= 0; + compute7_out_stage7_reg <= 0; + compute8_out_stage7_reg <= 0; + compute9_out_stage7_reg <= 0; + compute10_out_stage7_reg <= 0; + compute11_out_stage7_reg <= 0; + compute12_out_stage7_reg <= 0; + compute13_out_stage7_reg <= 0; + compute14_out_stage7_reg <= 0; + compute15_out_stage7_reg <= 0; + compute16_out_stage7_reg <= 0; + compute17_out_stage7_reg <= 0; + compute18_out_stage7_reg <= 0; + compute19_out_stage7_reg <= 0; + compute20_out_stage7_reg <= 0; + compute21_out_stage7_reg <= 0; + compute22_out_stage7_reg <= 0; + compute23_out_stage7_reg <= 0; + compute24_out_stage7_reg <= 0; + compute25_out_stage7_reg <= 0; + compute26_out_stage7_reg <= 0; + compute27_out_stage7_reg <= 0; + compute28_out_stage7_reg <= 0; + compute29_out_stage7_reg <= 0; + compute30_out_stage7_reg <= 0; + compute31_out_stage7_reg <= 0; + compute32_out_stage7_reg <= 0; + compute33_out_stage7_reg <= 0; + compute34_out_stage7_reg <= 0; + compute35_out_stage7_reg <= 0; + compute36_out_stage7_reg <= 0; + compute37_out_stage7_reg <= 0; + compute38_out_stage7_reg <= 0; + compute39_out_stage7_reg <= 0; + compute40_out_stage7_reg <= 0; + compute41_out_stage7_reg <= 0; + compute42_out_stage7_reg <= 0; + compute43_out_stage7_reg <= 0; + compute44_out_stage7_reg <= 0; + compute45_out_stage7_reg <= 0; + compute46_out_stage7_reg <= 0; + compute47_out_stage7_reg <= 0; + compute48_out_stage7_reg <= 0; + compute49_out_stage7_reg <= 0; + compute50_out_stage7_reg <= 0; + compute51_out_stage7_reg <= 0; + compute52_out_stage7_reg <= 0; + compute53_out_stage7_reg <= 0; + compute54_out_stage7_reg <= 0; + compute55_out_stage7_reg <= 0; + compute56_out_stage7_reg <= 0; + compute57_out_stage7_reg <= 0; + compute58_out_stage7_reg <= 0; + compute59_out_stage7_reg <= 0; + compute60_out_stage7_reg <= 0; + compute61_out_stage7_reg <= 0; + compute62_out_stage7_reg <= 0; + compute63_out_stage7_reg <= 0; + compute0_out_stage6_reg <= 0; + compute1_out_stage6_reg <= 0; + compute2_out_stage6_reg <= 0; + compute3_out_stage6_reg <= 0; + compute4_out_stage6_reg <= 0; + compute5_out_stage6_reg <= 0; + compute6_out_stage6_reg <= 0; + compute7_out_stage6_reg <= 0; + compute8_out_stage6_reg <= 0; + compute9_out_stage6_reg <= 0; + compute10_out_stage6_reg <= 0; + compute11_out_stage6_reg <= 0; + compute12_out_stage6_reg <= 0; + compute13_out_stage6_reg <= 0; + compute14_out_stage6_reg <= 0; + compute15_out_stage6_reg <= 0; + compute16_out_stage6_reg <= 0; + compute17_out_stage6_reg <= 0; + compute18_out_stage6_reg <= 0; + compute19_out_stage6_reg <= 0; + compute20_out_stage6_reg <= 0; + compute21_out_stage6_reg <= 0; + compute22_out_stage6_reg <= 0; + compute23_out_stage6_reg <= 0; + compute24_out_stage6_reg <= 0; + compute25_out_stage6_reg <= 0; + compute26_out_stage6_reg <= 0; + compute27_out_stage6_reg <= 0; + compute28_out_stage6_reg <= 0; + compute29_out_stage6_reg <= 0; + compute30_out_stage6_reg <= 0; + compute31_out_stage6_reg <= 0; + compute0_out_stage5_reg <= 0; + compute1_out_stage5_reg <= 0; + compute2_out_stage5_reg <= 0; + compute3_out_stage5_reg <= 0; + compute4_out_stage5_reg <= 0; + compute5_out_stage5_reg <= 0; + compute6_out_stage5_reg <= 0; + compute7_out_stage5_reg <= 0; + compute8_out_stage5_reg <= 0; + compute9_out_stage5_reg <= 0; + compute10_out_stage5_reg <= 0; + compute11_out_stage5_reg <= 0; + compute12_out_stage5_reg <= 0; + compute13_out_stage5_reg <= 0; + compute14_out_stage5_reg <= 0; + compute15_out_stage5_reg <= 0; + compute0_out_stage4_reg <= 0; + compute1_out_stage4_reg <= 0; + compute2_out_stage4_reg <= 0; + compute3_out_stage4_reg <= 0; + compute4_out_stage4_reg <= 0; + compute5_out_stage4_reg <= 0; + compute6_out_stage4_reg <= 0; + compute7_out_stage4_reg <= 0; + compute0_out_stage3_reg <= 0; + compute1_out_stage3_reg <= 0; + compute2_out_stage3_reg <= 0; + compute3_out_stage3_reg <= 0; + compute0_out_stage2_reg <= 0; + compute1_out_stage2_reg <= 0; + compute0_out_stage1_reg <= 0; + end + + else begin + compute0_out_stage7_reg <= compute0_out_stage7; + compute1_out_stage7_reg <= compute1_out_stage7; + compute2_out_stage7_reg <= compute2_out_stage7; + compute3_out_stage7_reg <= compute3_out_stage7; + compute4_out_stage7_reg <= compute4_out_stage7; + compute5_out_stage7_reg <= compute5_out_stage7; + compute6_out_stage7_reg <= compute6_out_stage7; + compute7_out_stage7_reg <= compute7_out_stage7; + compute8_out_stage7_reg <= compute8_out_stage7; + compute9_out_stage7_reg <= compute9_out_stage7; + compute10_out_stage7_reg <= compute10_out_stage7; + compute11_out_stage7_reg <= compute11_out_stage7; + compute12_out_stage7_reg <= compute12_out_stage7; + compute13_out_stage7_reg <= compute13_out_stage7; + compute14_out_stage7_reg <= compute14_out_stage7; + compute15_out_stage7_reg <= compute15_out_stage7; + compute16_out_stage7_reg <= compute16_out_stage7; + compute17_out_stage7_reg <= compute17_out_stage7; + compute18_out_stage7_reg <= compute18_out_stage7; + compute19_out_stage7_reg <= compute19_out_stage7; + compute20_out_stage7_reg <= compute20_out_stage7; + compute21_out_stage7_reg <= compute21_out_stage7; + compute22_out_stage7_reg <= compute22_out_stage7; + compute23_out_stage7_reg <= compute23_out_stage7; + compute24_out_stage7_reg <= compute24_out_stage7; + compute25_out_stage7_reg <= compute25_out_stage7; + compute26_out_stage7_reg <= compute26_out_stage7; + compute27_out_stage7_reg <= compute27_out_stage7; + compute28_out_stage7_reg <= compute28_out_stage7; + compute29_out_stage7_reg <= compute29_out_stage7; + compute30_out_stage7_reg <= compute30_out_stage7; + compute31_out_stage7_reg <= compute31_out_stage7; + compute32_out_stage7_reg <= compute32_out_stage7; + compute33_out_stage7_reg <= compute33_out_stage7; + compute34_out_stage7_reg <= compute34_out_stage7; + compute35_out_stage7_reg <= compute35_out_stage7; + compute36_out_stage7_reg <= compute36_out_stage7; + compute37_out_stage7_reg <= compute37_out_stage7; + compute38_out_stage7_reg <= compute38_out_stage7; + compute39_out_stage7_reg <= compute39_out_stage7; + compute40_out_stage7_reg <= compute40_out_stage7; + compute41_out_stage7_reg <= compute41_out_stage7; + compute42_out_stage7_reg <= compute42_out_stage7; + compute43_out_stage7_reg <= compute43_out_stage7; + compute44_out_stage7_reg <= compute44_out_stage7; + compute45_out_stage7_reg <= compute45_out_stage7; + compute46_out_stage7_reg <= compute46_out_stage7; + compute47_out_stage7_reg <= compute47_out_stage7; + compute48_out_stage7_reg <= compute48_out_stage7; + compute49_out_stage7_reg <= compute49_out_stage7; + compute50_out_stage7_reg <= compute50_out_stage7; + compute51_out_stage7_reg <= compute51_out_stage7; + compute52_out_stage7_reg <= compute52_out_stage7; + compute53_out_stage7_reg <= compute53_out_stage7; + compute54_out_stage7_reg <= compute54_out_stage7; + compute55_out_stage7_reg <= compute55_out_stage7; + compute56_out_stage7_reg <= compute56_out_stage7; + compute57_out_stage7_reg <= compute57_out_stage7; + compute58_out_stage7_reg <= compute58_out_stage7; + compute59_out_stage7_reg <= compute59_out_stage7; + compute60_out_stage7_reg <= compute60_out_stage7; + compute61_out_stage7_reg <= compute61_out_stage7; + compute62_out_stage7_reg <= compute62_out_stage7; + compute63_out_stage7_reg <= compute63_out_stage7; + + compute0_out_stage6_reg <= compute0_out_stage6; + compute1_out_stage6_reg <= compute1_out_stage6; + compute2_out_stage6_reg <= compute2_out_stage6; + compute3_out_stage6_reg <= compute3_out_stage6; + compute4_out_stage6_reg <= compute4_out_stage6; + compute5_out_stage6_reg <= compute5_out_stage6; + compute6_out_stage6_reg <= compute6_out_stage6; + compute7_out_stage6_reg <= compute7_out_stage6; + compute8_out_stage6_reg <= compute8_out_stage6; + compute9_out_stage6_reg <= compute9_out_stage6; + compute10_out_stage6_reg <= compute10_out_stage6; + compute11_out_stage6_reg <= compute11_out_stage6; + compute12_out_stage6_reg <= compute12_out_stage6; + compute13_out_stage6_reg <= compute13_out_stage6; + compute14_out_stage6_reg <= compute14_out_stage6; + compute15_out_stage6_reg <= compute15_out_stage6; + compute16_out_stage6_reg <= compute16_out_stage6; + compute17_out_stage6_reg <= compute17_out_stage6; + compute18_out_stage6_reg <= compute18_out_stage6; + compute19_out_stage6_reg <= compute19_out_stage6; + compute20_out_stage6_reg <= compute20_out_stage6; + compute21_out_stage6_reg <= compute21_out_stage6; + compute22_out_stage6_reg <= compute22_out_stage6; + compute23_out_stage6_reg <= compute23_out_stage6; + compute24_out_stage6_reg <= compute24_out_stage6; + compute25_out_stage6_reg <= compute25_out_stage6; + compute26_out_stage6_reg <= compute26_out_stage6; + compute27_out_stage6_reg <= compute27_out_stage6; + compute28_out_stage6_reg <= compute28_out_stage6; + compute29_out_stage6_reg <= compute29_out_stage6; + compute30_out_stage6_reg <= compute30_out_stage6; + compute31_out_stage6_reg <= compute31_out_stage6; + + compute0_out_stage5_reg <= compute0_out_stage5; + compute1_out_stage5_reg <= compute1_out_stage5; + compute2_out_stage5_reg <= compute2_out_stage5; + compute3_out_stage5_reg <= compute3_out_stage5; + compute4_out_stage5_reg <= compute4_out_stage5; + compute5_out_stage5_reg <= compute5_out_stage5; + compute6_out_stage5_reg <= compute6_out_stage5; + compute7_out_stage5_reg <= compute7_out_stage5; + compute8_out_stage5_reg <= compute8_out_stage5; + compute9_out_stage5_reg <= compute9_out_stage5; + compute10_out_stage5_reg <= compute10_out_stage5; + compute11_out_stage5_reg <= compute11_out_stage5; + compute12_out_stage5_reg <= compute12_out_stage5; + compute13_out_stage5_reg <= compute13_out_stage5; + compute14_out_stage5_reg <= compute14_out_stage5; + compute15_out_stage5_reg <= compute15_out_stage5; + + compute0_out_stage4_reg <= compute0_out_stage4; + compute1_out_stage4_reg <= compute1_out_stage4; + compute2_out_stage4_reg <= compute2_out_stage4; + compute3_out_stage4_reg <= compute3_out_stage4; + compute4_out_stage4_reg <= compute4_out_stage4; + compute5_out_stage4_reg <= compute5_out_stage4; + compute6_out_stage4_reg <= compute6_out_stage4; + compute7_out_stage4_reg <= compute7_out_stage4; + + compute0_out_stage3_reg <= compute0_out_stage3; + compute1_out_stage3_reg <= compute1_out_stage3; + compute2_out_stage3_reg <= compute2_out_stage3; + compute3_out_stage3_reg <= compute3_out_stage3; + + compute0_out_stage2_reg <= compute0_out_stage2; + compute1_out_stage2_reg <= compute1_out_stage2; + + compute0_out_stage1_reg <= compute0_out_stage1; + + outp <= compute0_out_stage0; + + end + end + + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute0_stage7(.A(inp0), .B(inp1), .OUT(compute0_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute1_stage7(.A(inp2), .B(inp3), .OUT(compute1_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute2_stage7(.A(inp4), .B(inp5), .OUT(compute2_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute3_stage7(.A(inp6), .B(inp7), .OUT(compute3_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute4_stage7(.A(inp8), .B(inp9), .OUT(compute4_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute5_stage7(.A(inp10), .B(inp11), .OUT(compute5_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute6_stage7(.A(inp12), .B(inp13), .OUT(compute6_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute7_stage7(.A(inp14), .B(inp15), .OUT(compute7_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute8_stage7(.A(inp16), .B(inp17), .OUT(compute8_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute9_stage7(.A(inp18), .B(inp19), .OUT(compute9_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute10_stage7(.A(inp20), .B(inp21), .OUT(compute10_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute11_stage7(.A(inp22), .B(inp23), .OUT(compute11_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute12_stage7(.A(inp24), .B(inp25), .OUT(compute12_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute13_stage7(.A(inp26), .B(inp27), .OUT(compute13_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute14_stage7(.A(inp28), .B(inp29), .OUT(compute14_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute15_stage7(.A(inp30), .B(inp31), .OUT(compute15_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute16_stage7(.A(inp32), .B(inp33), .OUT(compute16_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute17_stage7(.A(inp34), .B(inp35), .OUT(compute17_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute18_stage7(.A(inp36), .B(inp37), .OUT(compute18_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute19_stage7(.A(inp38), .B(inp39), .OUT(compute19_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute20_stage7(.A(inp40), .B(inp41), .OUT(compute20_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute21_stage7(.A(inp42), .B(inp43), .OUT(compute21_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute22_stage7(.A(inp44), .B(inp45), .OUT(compute22_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute23_stage7(.A(inp46), .B(inp47), .OUT(compute23_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute24_stage7(.A(inp48), .B(inp49), .OUT(compute24_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute25_stage7(.A(inp50), .B(inp51), .OUT(compute25_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute26_stage7(.A(inp52), .B(inp53), .OUT(compute26_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute27_stage7(.A(inp54), .B(inp55), .OUT(compute27_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute28_stage7(.A(inp56), .B(inp57), .OUT(compute28_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute29_stage7(.A(inp58), .B(inp59), .OUT(compute29_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute30_stage7(.A(inp60), .B(inp61), .OUT(compute30_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute31_stage7(.A(inp62), .B(inp63), .OUT(compute31_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute32_stage7(.A(inp64), .B(inp65), .OUT(compute32_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute33_stage7(.A(inp66), .B(inp67), .OUT(compute33_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute34_stage7(.A(inp68), .B(inp69), .OUT(compute34_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute35_stage7(.A(inp70), .B(inp71), .OUT(compute35_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute36_stage7(.A(inp72), .B(inp73), .OUT(compute36_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute37_stage7(.A(inp74), .B(inp75), .OUT(compute37_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute38_stage7(.A(inp76), .B(inp77), .OUT(compute38_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute39_stage7(.A(inp78), .B(inp79), .OUT(compute39_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute40_stage7(.A(inp80), .B(inp81), .OUT(compute40_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute41_stage7(.A(inp82), .B(inp83), .OUT(compute41_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute42_stage7(.A(inp84), .B(inp85), .OUT(compute42_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute43_stage7(.A(inp86), .B(inp87), .OUT(compute43_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute44_stage7(.A(inp88), .B(inp89), .OUT(compute44_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute45_stage7(.A(inp90), .B(inp91), .OUT(compute45_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute46_stage7(.A(inp92), .B(inp93), .OUT(compute46_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute47_stage7(.A(inp94), .B(inp95), .OUT(compute47_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute48_stage7(.A(inp96), .B(inp97), .OUT(compute48_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute49_stage7(.A(inp98), .B(inp99), .OUT(compute49_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute50_stage7(.A(inp100), .B(inp101), .OUT(compute50_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute51_stage7(.A(inp102), .B(inp103), .OUT(compute51_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute52_stage7(.A(inp104), .B(inp105), .OUT(compute52_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute53_stage7(.A(inp106), .B(inp107), .OUT(compute53_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute54_stage7(.A(inp108), .B(inp109), .OUT(compute54_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute55_stage7(.A(inp110), .B(inp111), .OUT(compute55_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute56_stage7(.A(inp112), .B(inp113), .OUT(compute56_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute57_stage7(.A(inp114), .B(inp115), .OUT(compute57_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute58_stage7(.A(inp116), .B(inp117), .OUT(compute58_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute59_stage7(.A(inp118), .B(inp119), .OUT(compute59_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute60_stage7(.A(inp120), .B(inp121), .OUT(compute60_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute61_stage7(.A(inp122), .B(inp123), .OUT(compute61_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute62_stage7(.A(inp124), .B(inp125), .OUT(compute62_out_stage7), .MODE(mode)); + processing_element #(`DWIDTH,`DWIDTH+`LOGDWIDTH) compute63_stage7(.A(inp126), .B(inp127), .OUT(compute63_out_stage7), .MODE(mode)); + + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute0_stage6(.A(compute0_out_stage7_reg), .B(compute1_out_stage7_reg), .OUT(compute0_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute1_stage6(.A(compute2_out_stage7_reg), .B(compute3_out_stage7_reg), .OUT(compute1_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute2_stage6(.A(compute4_out_stage7_reg), .B(compute5_out_stage7_reg), .OUT(compute2_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute3_stage6(.A(compute6_out_stage7_reg), .B(compute7_out_stage7_reg), .OUT(compute3_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute4_stage6(.A(compute8_out_stage7_reg), .B(compute9_out_stage7_reg), .OUT(compute4_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute5_stage6(.A(compute10_out_stage7_reg), .B(compute11_out_stage7_reg), .OUT(compute5_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute6_stage6(.A(compute12_out_stage7_reg), .B(compute13_out_stage7_reg), .OUT(compute6_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute7_stage6(.A(compute14_out_stage7_reg), .B(compute15_out_stage7_reg), .OUT(compute7_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute8_stage6(.A(compute16_out_stage7_reg), .B(compute17_out_stage7_reg), .OUT(compute8_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute9_stage6(.A(compute18_out_stage7_reg), .B(compute19_out_stage7_reg), .OUT(compute9_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute10_stage6(.A(compute20_out_stage7_reg), .B(compute21_out_stage7_reg), .OUT(compute10_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute11_stage6(.A(compute22_out_stage7_reg), .B(compute23_out_stage7_reg), .OUT(compute11_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute12_stage6(.A(compute24_out_stage7_reg), .B(compute25_out_stage7_reg), .OUT(compute12_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute13_stage6(.A(compute26_out_stage7_reg), .B(compute27_out_stage7_reg), .OUT(compute13_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute14_stage6(.A(compute28_out_stage7_reg), .B(compute29_out_stage7_reg), .OUT(compute14_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute15_stage6(.A(compute30_out_stage7_reg), .B(compute31_out_stage7_reg), .OUT(compute15_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute16_stage6(.A(compute32_out_stage7_reg), .B(compute33_out_stage7_reg), .OUT(compute16_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute17_stage6(.A(compute34_out_stage7_reg), .B(compute35_out_stage7_reg), .OUT(compute17_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute18_stage6(.A(compute36_out_stage7_reg), .B(compute37_out_stage7_reg), .OUT(compute18_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute19_stage6(.A(compute38_out_stage7_reg), .B(compute39_out_stage7_reg), .OUT(compute19_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute20_stage6(.A(compute40_out_stage7_reg), .B(compute41_out_stage7_reg), .OUT(compute20_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute21_stage6(.A(compute42_out_stage7_reg), .B(compute43_out_stage7_reg), .OUT(compute21_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute22_stage6(.A(compute44_out_stage7_reg), .B(compute45_out_stage7_reg), .OUT(compute22_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute23_stage6(.A(compute46_out_stage7_reg), .B(compute47_out_stage7_reg), .OUT(compute23_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute24_stage6(.A(compute48_out_stage7_reg), .B(compute49_out_stage7_reg), .OUT(compute24_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute25_stage6(.A(compute50_out_stage7_reg), .B(compute51_out_stage7_reg), .OUT(compute25_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute26_stage6(.A(compute52_out_stage7_reg), .B(compute53_out_stage7_reg), .OUT(compute26_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute27_stage6(.A(compute54_out_stage7_reg), .B(compute55_out_stage7_reg), .OUT(compute27_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute28_stage6(.A(compute56_out_stage7_reg), .B(compute57_out_stage7_reg), .OUT(compute28_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute29_stage6(.A(compute58_out_stage7_reg), .B(compute59_out_stage7_reg), .OUT(compute29_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute30_stage6(.A(compute60_out_stage7_reg), .B(compute61_out_stage7_reg), .OUT(compute30_out_stage6), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute31_stage6(.A(compute62_out_stage7_reg), .B(compute63_out_stage7_reg), .OUT(compute31_out_stage6), .MODE(mode)); + + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute0_stage5(.A(compute0_out_stage6_reg), .B(compute1_out_stage6_reg), .OUT(compute0_out_stage5), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute1_stage5(.A(compute2_out_stage6_reg), .B(compute3_out_stage6_reg), .OUT(compute1_out_stage5), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute2_stage5(.A(compute4_out_stage6_reg), .B(compute5_out_stage6_reg), .OUT(compute2_out_stage5), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute3_stage5(.A(compute6_out_stage6_reg), .B(compute7_out_stage6_reg), .OUT(compute3_out_stage5), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute4_stage5(.A(compute8_out_stage6_reg), .B(compute9_out_stage6_reg), .OUT(compute4_out_stage5), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute5_stage5(.A(compute10_out_stage6_reg), .B(compute11_out_stage6_reg), .OUT(compute5_out_stage5), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute6_stage5(.A(compute12_out_stage6_reg), .B(compute13_out_stage6_reg), .OUT(compute6_out_stage5), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute7_stage5(.A(compute14_out_stage6_reg), .B(compute15_out_stage6_reg), .OUT(compute7_out_stage5), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute8_stage5(.A(compute16_out_stage6_reg), .B(compute17_out_stage6_reg), .OUT(compute8_out_stage5), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute9_stage5(.A(compute18_out_stage6_reg), .B(compute19_out_stage6_reg), .OUT(compute9_out_stage5), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute10_stage5(.A(compute20_out_stage6_reg), .B(compute21_out_stage6_reg), .OUT(compute10_out_stage5), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute11_stage5(.A(compute22_out_stage6_reg), .B(compute23_out_stage6_reg), .OUT(compute11_out_stage5), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute12_stage5(.A(compute24_out_stage6_reg), .B(compute25_out_stage6_reg), .OUT(compute12_out_stage5), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute13_stage5(.A(compute26_out_stage6_reg), .B(compute27_out_stage6_reg), .OUT(compute13_out_stage5), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute14_stage5(.A(compute28_out_stage6_reg), .B(compute29_out_stage6_reg), .OUT(compute14_out_stage5), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute15_stage5(.A(compute30_out_stage6_reg), .B(compute31_out_stage6_reg), .OUT(compute15_out_stage5), .MODE(mode)); + + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute0_stage4(.A(compute0_out_stage5_reg), .B(compute1_out_stage5_reg), .OUT(compute0_out_stage4), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute1_stage4(.A(compute2_out_stage5_reg), .B(compute3_out_stage5_reg), .OUT(compute1_out_stage4), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute2_stage4(.A(compute4_out_stage5_reg), .B(compute5_out_stage5_reg), .OUT(compute2_out_stage4), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute3_stage4(.A(compute6_out_stage5_reg), .B(compute7_out_stage5_reg), .OUT(compute3_out_stage4), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute4_stage4(.A(compute8_out_stage5_reg), .B(compute9_out_stage5_reg), .OUT(compute4_out_stage4), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute5_stage4(.A(compute10_out_stage5_reg), .B(compute11_out_stage5_reg), .OUT(compute5_out_stage4), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute6_stage4(.A(compute12_out_stage5_reg), .B(compute13_out_stage5_reg), .OUT(compute6_out_stage4), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute7_stage4(.A(compute14_out_stage5_reg), .B(compute15_out_stage5_reg), .OUT(compute7_out_stage4), .MODE(mode)); + + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute0_stage3(.A(compute0_out_stage4_reg), .B(compute1_out_stage4_reg), .OUT(compute0_out_stage3), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute1_stage3(.A(compute2_out_stage4_reg), .B(compute3_out_stage4_reg), .OUT(compute1_out_stage3), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute2_stage3(.A(compute4_out_stage4_reg), .B(compute5_out_stage4_reg), .OUT(compute2_out_stage3), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute3_stage3(.A(compute6_out_stage4_reg), .B(compute7_out_stage4_reg), .OUT(compute3_out_stage3), .MODE(mode)); + + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute0_stage2(.A(compute0_out_stage3_reg), .B(compute1_out_stage3_reg), .OUT(compute0_out_stage2), .MODE(mode)); + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute1_stage2(.A(compute2_out_stage3_reg), .B(compute3_out_stage3_reg), .OUT(compute1_out_stage2), .MODE(mode)); + + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute0_stage1(.A(compute0_out_stage2_reg), .B(compute1_out_stage2_reg), .OUT(compute0_out_stage1), .MODE(mode)); + + processing_element #(`DWIDTH+`LOGDWIDTH,`DWIDTH+`LOGDWIDTH) compute0_stage0(.A(outp), .B(compute0_out_stage1_reg), .OUT(compute0_out_stage0), .MODE(mode)); + +endmodule + + +/////////////////////////////////////////////////////// +// Processing element. Finds sum, min or max depending on mode +/////////////////////////////////////////////////////// +module processing_element( + A, B, OUT, MODE +); +parameter IN_DWIDTH = 16; +parameter OUT_DWIDTH = 4; +input [IN_DWIDTH-1:0] A; +input [IN_DWIDTH-1:0] B; +output [OUT_DWIDTH-1:0] OUT; +input [1:0] MODE; + +wire [OUT_DWIDTH-1:0] greater; +wire [OUT_DWIDTH-1:0] smaller; +wire [OUT_DWIDTH-1:0] sum; + +assign greater = (A>B) ? A : B; +assign smaller = (A 2 bits for integer, 4 bits for the fractional part. +alpha = gamma = 0.5 + +*/ +//////////////////////////////////////////////////////////////////////////////////////// + +// Sum_Calc: Calculates the value of the Q expression after accomodating for the different radix forms of the numbers. +module Sum_Calc + ( clk, + reset, + Q, + alpha, + r, + gamma, + max, + Output_rsvd); + + input clk; + input reset; + input [31:0] Q; // int32 + input [7:0] alpha; // ufix8_En7 + input [31:0] r; // sfix32_En4 + input [7:0] gamma; // ufix8_En7 + input [15:0] max; // int16 + output [31:0] Output_rsvd; // int32 + + + wire [37:0] Sum1_stage2_sub_cast; // sfix38_En4 + wire [37:0] Sum1_stage2_sub_cast_1; // sfix38_En4 + wire [37:0] Sum1_op_stage2; // sfix38_En4 + wire [8:0] Product_cast; // sfix9_En7 + wire [24:0] Product_mul_temp; // sfix25_En7 + wire [23:0] Product_cast_1; // sfix24_En7 + wire [31:0] Product_out1; // int32 + wire [37:0] Sum1_stage3_add_cast; // sfix38_En4 + wire [37:0] Sum1_stage3_add_temp; // sfix38_En4 + wire [31:0] Sum1_out1; // int32 + wire [8:0] Product1_cast; // sfix9_En7 + wire [40:0] Product1_mul_temp; // sfix41_En7 + wire [39:0] Product1_cast_1; // sfix40_En7 + wire [31:0] Product1_out1; // int32 + wire [15:0] Sum_add_cast; // sfix16 + wire [15:0] Sum_add_cast_1; // sfix16 + wire [15:0] Sum_add_temp; // sfix16 + wire [31:0] Sum_out1; // int32 + + + assign Sum1_stage2_sub_cast = {{6{r[31]}}, r}; + assign Sum1_stage2_sub_cast_1 = {{2{Q[31]}}, {Q, 4'b0000}}; + assign Sum1_op_stage2 = Sum1_stage2_sub_cast - Sum1_stage2_sub_cast_1; + + + + assign Product_cast = {1'b0, gamma}; + assign Product_mul_temp = max * Product_cast; + assign Product_cast_1 = Product_mul_temp[23:0]; + assign Product_out1 = {{15{Product_cast_1[23]}}, Product_cast_1[23:7]}; + + + + assign Sum1_stage3_add_cast = {{2{Product_out1[31]}}, {Product_out1, 4'b0000}}; + assign Sum1_stage3_add_temp = Sum1_op_stage2 + Sum1_stage3_add_cast; + assign Sum1_out1 = Sum1_stage3_add_temp[35:4]; +//// + + reg [31:0] Sum1_out1_flopped; + reg [7:0] alpha_flopped; + reg [31:0] Q_flopped; + +always @(posedge clk) + begin + if (reset == 1'b1) begin + Sum1_out1_flopped <= 0; + alpha_flopped <= 0; + Q_flopped <= 0; + end + else begin + Sum1_out1_flopped <= Sum1_out1; + alpha_flopped <= alpha; + Q_flopped <= Q; + end + end + +//// + assign Product1_cast = {1'b0, alpha_flopped}; + assign Product1_mul_temp = Sum1_out1_flopped * Product1_cast; + assign Product1_cast_1 = Product1_mul_temp[39:0]; + assign Product1_out1 = Product1_cast_1[38:7]; + +//pipelining + reg [31:0] Product1_out1_flopped; // int32 + reg [31:0] Q_flopped2; + always @(posedge clk) begin + Q_flopped2 <= Q_flopped; + Product1_out1_flopped <= Product1_out1; + end + + + assign Sum_add_cast = Q_flopped2[15:0]; + assign Sum_add_cast_1 = Product1_out1_flopped[15:0]; + assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1; + assign Sum_out1 = {{16{Sum_add_temp[15]}}, Sum_add_temp}; + + assign Output_rsvd = Sum_out1; + +endmodule // Sum_Calc + +////////////////////////////SAME/////////////////// +//Max: Gives an output of the maximum number from 4 possible numbers (= no. of actions) truncated to fit within 16 bits. +// A tree approach is used, where 3 comparators are used. +module Max + (in0_0, + in0_1, + in0_2, + in0_3, + out0, + clk); + + + + input [31:0] in0_0; // int32 + input [31:0] in0_1; // int32 + input [31:0] in0_2; // int32 + input [31:0] in0_3; // int32 + output [15:0] out0; // int16 + input clk; +/* + wire [31:0] in0 [0:3]; // int32 [4] + wire [31:0] Max_stage1_val [0:1]; // int32 [2] + wire [31:0] Max_stage2_val; // int32 + + + assign in0[0] = in0_0; + assign in0[1] = in0_1; + assign in0[2] = in0_2; + assign in0[3] = in0_3; + + // ---- Tree max implementation ---- + // ---- Tree max stage 1 ---- + assign Max_stage1_val[0] = (in0[0] >= in0[1] ? in0[0] : + in0[1]); + assign Max_stage1_val[1] = (in0[2] >= in0[3] ? in0[2] : + in0[3]); + + + + // ---- Tree max stage 2 ---- + assign Max_stage2_val = (Max_stage1_val[0] >= Max_stage1_val[1] ? Max_stage1_val[0] : + Max_stage1_val[1]); + +*/ + +//wire [31:0] in0[0:3]; // int32 [4] + wire [31:0] Max_stage1_val_0; // int32 [2] + wire [31:0] Max_stage1_val_1; // int32 [2] + wire [31:0] Max_stage2_val; // int32 + + + // assign in0[0] = in0_0; + //assign in0[1] = in0_1; + //assign in0[2] = in0_2; + //assign in0[3] = in0_3; + + // ---- Tree max implementation ---- + // ---- Tree max stage 1 ---- + assign Max_stage1_val_0 = (in0_0 >= in0_1 ? in0_0 : in0_1); + assign Max_stage1_val_1 = (in0_2 >= in0_3 ? in0_2 : in0_3); + + reg [31:0] Max_stage1_val_0_flopped; // int32 [2] + reg [31:0] Max_stage1_val_1_flopped; // int32 [2] + //pipelining the tree + always @(posedge clk) begin + Max_stage1_val_0_flopped <= Max_stage1_val_0; + Max_stage1_val_1_flopped <= Max_stage1_val_1; + end + + // ---- Tree max stage 2 ---- + assign Max_stage2_val = (Max_stage1_val_0_flopped >= Max_stage1_val_1_flopped ? Max_stage1_val_0_flopped : Max_stage1_val_1_flopped); + + + assign out0 = Max_stage2_val[15:0]; + + + +endmodule // Max + + + + + +// SimpleDualPortRAM_generic : 4 RAM banks ( = no. of actions) with a depth of 12 ( = no. of states). Writes during training. Reads during inferfence. +module SimpleDualPortRAM_generic + (clk, + enb, + wr_din, + wr_addr, + wr_en, + rd_addr, + rd_dout); + + parameter AddrWidth = 1; + parameter DataWidth = 1; + + input clk; + input enb; + input [DataWidth - 1:0] wr_din; // parameterized width + input [AddrWidth - 1:0] wr_addr; // parameterized width + input wr_en; // ufix1 + input [AddrWidth - 1:0] rd_addr; // parameterized width + output [DataWidth - 1:0] rd_dout; // parameterized width + + wire temp_wr_en; + assign temp_wr_en = enb && wr_en; + + `ifndef hard_mem //vtr_edit + + reg [DataWidth - 1:0] data_int; + reg [DataWidth - 1:0] ram [2**AddrWidth - 1:0]; + +/* + initial begin + ram[7] = 32'h00000000; + ram[6] = 32'h00000000; + ram[5] = 32'h00000000; + ram[4] = 32'h00000000; + ram[3] = 32'h00000000; + ram[2] = 32'h00000000; + ram[1] = 32'h00000000; + ram[0] = 32'h00000000; + + data_int = 32'h00000000; + end +*/ + + always @(posedge clk) + begin + //if (enb == 1'b1) begin + // if (wr_en == 1'b1) begin + if (temp_wr_en) + ram[wr_addr] <= wr_din; + // end + data_int <= ram[rd_addr]; + //end + end + + assign rd_dout = data_int; + + //vtr_edit +`else + +wire [DataWidth - 1:0] data_int; +wire [DataWidth - 1:0] fake_op_1; +wire [DataWidth - 1:0] fake_op_2; + +defparam u_dual_port_ram.ADDR_WIDTH = AddrWidth; +defparam u_dual_port_ram.DATA_WIDTH = DataWidth; + +dual_port_ram u_dual_port_ram( +.addr1(wr_addr), +.we1(temp_wr_en), +.data1(wr_din), +.out1(fake_op_1), +.addr2(rd_addr), +.we2(1'b0), +.data2(fake_op_2), +.out2(data_int), +.clk(clk) +); + +assign rd_dout = data_int; + +`endif + +endmodule // SimpleDualPortRAM_generic + +// Q_Hw: connects all the blocks and incorporates pipelining for appropriate syncing. +module Q_HW + (mode, clk, + reset, + clk_enable, + State, + Action, + Reward, + alpha, + gamma, + ce_out, + Q, + Data_Type_Conversion_out1_0, + Data_Type_Conversion_out1_1, + Data_Type_Conversion_out1_2, + Data_Type_Conversion_out1_3 + ); + + input mode; + input clk; + input reset; + input clk_enable; + input [3:0] State; // ufix3 + input [1:0] Action; // ufix2 + input [31:0] Reward; // sfix32_En4 + input [7:0] alpha; // ufix8_En7 + input [7:0] gamma; // ufix8_En7 + output ce_out; + output [31:0] Q; // int32 + output [31:0] Data_Type_Conversion_out1_0; +output [31:0] Data_Type_Conversion_out1_1; +output [31:0] Data_Type_Conversion_out1_2; +output [31:0] Data_Type_Conversion_out1_3; + + + + wire enb; + reg [1:0] Delay2_out1; // ufix2 + reg [1:0] Delay5_out1; // ufix2 + wire [7:0] Data_Type_Conversion1_out1; // uint8 + reg [3:0] Delay1_out1; // ufix3 + reg [3:0] Delay4_out1; // ufix3 + wire Constant3_out1; + reg [7:0] Delay11_out1; // ufix8_En7 + reg [7:0] Delay13_out1; // ufix8_En7 + reg [31:0] Delay3_out1; // sfix32_En4 + reg [31:0] Delay6_out1; // sfix32_En4 + reg [7:0] Delay12_out1; // ufix8_En7 + reg [7:0] Delay7_out1; // ufix8_En7 + + //wire [31:0] Data_Type_Conversion_out1 [0:3]; // int32 [4] + wire [31:0] Data_Type_Conversion_out1_0; + wire [31:0] Data_Type_Conversion_out1_1; + wire [31:0] Data_Type_Conversion_out1_2; + wire [31:0] Data_Type_Conversion_out1_3; + + + wire [15:0] Max_out1; // int16 + + //wire [31:0] Assignment_out1 [0:3]; // int32 [4] + wire [31:0] Assignment_out1_0; + wire [31:0] Assignment_out1_1; + wire [31:0] Assignment_out1_2; + wire [31:0] Assignment_out1_3; + + wire [31:0] pre_rd_out; // int32 + wire [31:0] pre_rd_out_1; // int32 + wire [31:0] pre_rd_out_2; // int32 + + //wire [31:0] Delay_out1 [0:3]; // int32 [4] + wire [31:0] Delay_out1_0; + wire [31:0] Delay_out1_1; + wire [31:0] Delay_out1_2; + wire [31:0] Delay_out1_3; + + //wire [31:0] From8_out1 [0:3]; // int32 [4] + wire [31:0] From8_out1_0; + wire [31:0] From8_out1_1; + wire [31:0] From8_out1_2; + wire [31:0] From8_out1_3; + + wire [31:0] Sum_Calc_out1; // int32 + wire [31:0] pre_rd_out_3; // int32 + + //wire [31:0] Simple_Dual_Port_RAM_System_out1 [0:3]; // int32 [4] + wire [31:0] Simple_Dual_Port_RAM_System_out1_0; + wire [31:0] Simple_Dual_Port_RAM_System_out1_1; + wire [31:0] Simple_Dual_Port_RAM_System_out1_2; + wire [31:0] Simple_Dual_Port_RAM_System_out1_3; + + //reg [31:0] Delay_reg [0:3]; // sfix32 [4] + reg [31:0] Delay_reg_0; + reg [31:0] Delay_reg_1; + reg [31:0] Delay_reg_2; + reg [31:0] Delay_reg_3; + + //wire [31:0] Delay_reg_next [0:3]; // sfix32 [4] + wire [31:0] Delay_reg_next_0; + wire [31:0] Delay_reg_next_1; + wire [31:0] Delay_reg_next_2; + wire [31:0] Delay_reg_next_3; + + + wire [31:0] Multiport_Switch_out1; // int32 + reg [31:0] Delay9_out1; // int32 + +/* +assign Data_Type_Conversion_out1_0 = Data_Type_Conversion_out1_0; +assign Data_Type_Conversion_out1_1 = Data_Type_Conversion_out1_1; +assign Data_Type_Conversion_out1_2 = Data_Type_Conversion_out1_2; +assign Data_Type_Conversion_out1_3 = Data_Type_Conversion_out1_3; +*/ + assign enb = clk_enable; + + always @(posedge clk) + begin + if (reset == 1'b1) begin + Delay2_out1 <= 2'b00; + end + else begin + if (enb) begin + Delay2_out1 <= Action; + end + end + end + + + + always @(posedge clk) + begin + if (reset == 1'b1) begin + Delay5_out1 <= 2'b00; + end + else begin + if (enb) begin + Delay5_out1 <= Delay2_out1; + end + end + end + + + + assign Data_Type_Conversion1_out1 = {6'b0, Delay5_out1}; + + + + always @(posedge clk) + begin : Delay1_process + if (reset == 1'b1) begin + Delay1_out1 <= 3'b000; + end + else begin + if (enb) begin + Delay1_out1 <= State; + end + end + end + + + + always @(posedge clk) + begin + if (reset == 1'b1) begin + Delay4_out1 <= 3'b000; + end + else begin + if (enb) begin + Delay4_out1 <= Delay1_out1; + end + end + end + + + + assign Constant3_out1 = !mode; + + + always @(posedge clk) + begin + if (reset == 1'b1) begin + Delay11_out1 <= 8'b00000000; + end + else begin + if (enb) begin + Delay11_out1 <= alpha; + end + end + end + + + + always @(posedge clk) + begin + if (reset == 1'b1) begin + Delay13_out1 <= 8'b00000000; + end + else begin + if (enb) begin + Delay13_out1 <= Delay11_out1; + end + end + end + + + + always @(posedge clk) + begin + if (reset == 1'b1) begin + Delay3_out1 <= 32'sb00000000000000000000000000000000; + end + else begin + if (enb) begin + Delay3_out1 <= Reward; + end + end + end + + + + always @(posedge clk) + begin + if (reset == 1'b1) begin + Delay6_out1 <= 32'sb00000000000000000000000000000000; + end + else begin + if (enb) begin + Delay6_out1 <= Delay3_out1; + end + end + end + + + + always @(posedge clk) + begin + if (reset == 1'b1) begin + Delay12_out1 <= 8'b00000000; + end + else begin + if (enb) begin + Delay12_out1 <= gamma; + end + end + end + + + + always @(posedge clk) + begin + if (reset == 1'b1) begin + Delay7_out1 <= 8'b00000000; + end + else begin + if (enb) begin + Delay7_out1 <= Delay12_out1; + end + end + end + + + + Max u_Max (.in0_0(Data_Type_Conversion_out1_0), // int32 + .in0_1(Data_Type_Conversion_out1_1), // int32 + .in0_2(Data_Type_Conversion_out1_2), // int32 + .in0_3(Data_Type_Conversion_out1_3), // int32 + .out0(Max_out1), // int16 + .clk(clk)); + + SimpleDualPortRAM_generic #(.AddrWidth(4), + .DataWidth(32) + ) + u_Simple_Dual_Port_RAM_System_bank3 (.clk(clk), + .enb(clk_enable), + .wr_din(Assignment_out1_3), + .wr_addr(Delay4_out1), + .wr_en(Constant3_out1), + .rd_addr(Delay1_out1), + .rd_dout(pre_rd_out) + ); + + SimpleDualPortRAM_generic #(.AddrWidth(4), + .DataWidth(32) + ) + u_Simple_Dual_Port_RAM_System_bank2 (.clk(clk), + .enb(clk_enable), + .wr_din(Assignment_out1_2), + .wr_addr(Delay4_out1), + .wr_en(Constant3_out1), + .rd_addr(Delay1_out1), + .rd_dout(pre_rd_out_1) + ); + + SimpleDualPortRAM_generic #(.AddrWidth(4), + .DataWidth(32) + ) + u_Simple_Dual_Port_RAM_System_bank1 (.clk(clk), + .enb(clk_enable), + .wr_din(Assignment_out1_1), + .wr_addr(Delay4_out1), + .wr_en(Constant3_out1), + .rd_addr(Delay1_out1), + .rd_dout(pre_rd_out_2) + ); + + + + + SimpleDualPortRAM_generic #(.AddrWidth(4), + .DataWidth(32) + ) + u_Simple_Dual_Port_RAM_System_bank0 (.clk(clk), + .enb(clk_enable), + .wr_din(Assignment_out1_0), + .wr_addr(Delay4_out1), + .wr_en(Constant3_out1), + .rd_addr(Delay1_out1), + .rd_dout(pre_rd_out_3) + ); + + assign From8_out1_0 = Delay_out1_0; + assign From8_out1_1 = Delay_out1_1; + assign From8_out1_2 = Delay_out1_2; + assign From8_out1_3 = Delay_out1_3; + + assign Assignment_out1_0 = (Data_Type_Conversion1_out1 == 8'b00000000 ? Sum_Calc_out1 : + From8_out1_0); + assign Assignment_out1_1 = (Data_Type_Conversion1_out1 == 8'b00000001 ? Sum_Calc_out1 : + From8_out1_1); + assign Assignment_out1_2 = (Data_Type_Conversion1_out1 == 8'b00000010 ? Sum_Calc_out1 : + From8_out1_2); + assign Assignment_out1_3 = (Data_Type_Conversion1_out1 == 8'b00000011 ? Sum_Calc_out1 : + From8_out1_3); + + + assign Simple_Dual_Port_RAM_System_out1_0 = pre_rd_out_3; + assign Simple_Dual_Port_RAM_System_out1_1 = pre_rd_out_2; + assign Simple_Dual_Port_RAM_System_out1_2 = pre_rd_out_1; + assign Simple_Dual_Port_RAM_System_out1_3 = pre_rd_out; + + assign Data_Type_Conversion_out1_0 = Simple_Dual_Port_RAM_System_out1_0; + assign Data_Type_Conversion_out1_1 = Simple_Dual_Port_RAM_System_out1_1; + assign Data_Type_Conversion_out1_2 = Simple_Dual_Port_RAM_System_out1_2; + assign Data_Type_Conversion_out1_3 = Simple_Dual_Port_RAM_System_out1_3; + + + + always @(posedge clk) + begin : Delay_process + if (reset == 1'b1) begin + Delay_reg_0 <= 32'sb00000000000000000000000000000000; + Delay_reg_1 <= 32'sb00000000000000000000000000000000; + Delay_reg_2 <= 32'sb00000000000000000000000000000000; + Delay_reg_3 <= 32'sb00000000000000000000000000000000; + end + else begin + if (enb) begin + Delay_reg_0 <= Delay_reg_next_0; + Delay_reg_1 <= Delay_reg_next_1; + Delay_reg_2 <= Delay_reg_next_2; + Delay_reg_3 <= Delay_reg_next_3; + end + end + end + + assign Delay_out1_0= Delay_reg_0; + assign Delay_out1_1 = Delay_reg_1; + assign Delay_out1_2 = Delay_reg_2; + assign Delay_out1_3 = Delay_reg_3; + assign Delay_reg_next_0 = Data_Type_Conversion_out1_0; + assign Delay_reg_next_1 = Data_Type_Conversion_out1_1; + assign Delay_reg_next_2 = Data_Type_Conversion_out1_2; + assign Delay_reg_next_3 = Data_Type_Conversion_out1_3; + + + + assign Multiport_Switch_out1 = (Delay5_out1 == 2'b00 ? Delay_out1_0 : + (Delay5_out1 == 2'b01 ? Delay_out1_1 : + (Delay5_out1 == 2'b10 ? Delay_out1_2 : + Delay_out1_3))); + +reg [31:0] Multiport_Switch_out1_flopped; +reg [7:0] Delay13_out1_flopped; +reg [31:0] Delay6_out1_flopped; +reg [7:0] Delay7_out1_flopped; +reg [15:0] Max_out1_flopped; + +always @(posedge clk) + begin + if (reset == 1'b1) begin + Multiport_Switch_out1_flopped <= 0; + Delay13_out1_flopped <= 0; + Delay6_out1_flopped <= 0; + Delay7_out1_flopped <= 0; + Max_out1_flopped <= 0; + end + else begin + Multiport_Switch_out1_flopped <= Multiport_Switch_out1; + Delay13_out1_flopped <= Delay13_out1; + Delay6_out1_flopped <= Delay6_out1; + Delay7_out1_flopped <= Delay7_out1; + Max_out1_flopped <= Max_out1; + end + end + + Sum_Calc u_Sum_Calc (.clk (clk), .reset(reset), .Q(Multiport_Switch_out1_flopped), // int32 + .alpha(Delay13_out1_flopped), // ufix8_En7 + .r(Delay6_out1_flopped), // sfix32_En4 + .gamma(Delay7_out1_flopped), // ufix8_En7 + .max(Max_out1_flopped), // int16 + .Output_rsvd(Sum_Calc_out1) // int32 + ); +/* + Sum_Calc u_Sum_Calc (.Q(Multiport_Switch_out1), // int32 + .alpha(Delay13_out1), // ufix8_En7 + .r(Delay6_out1), // sfix32_En4 + .gamma(Delay7_out1), // ufix8_En7 + .max(Max_out1), // int16 + .Output_rsvd(Sum_Calc_out1) // int32 + ); +*/ + + always @(posedge clk) + begin : Delay9_process + if (reset == 1'b1) begin + Delay9_out1 <= 32'sb00000000000000000000000000000000; + end + else begin + if (enb) begin + Delay9_out1 <= Sum_Calc_out1; + end + end + end + + + assign Q = Delay9_out1; + + assign ce_out = clk_enable; + +endmodule // Q_HW + + +// FSM: Mealy state machine for the action-state relation. Reward values have been adjusted to suit the problem statement. +module FSM ( input [3:0]final_state, input clk, input reset, input [1:0] action, output reg [31:0] reward, output reg [3:0] state, output [1:0] next_action); + +parameter region1 = 4'd0, + region2 = 4'd1, + region3 = 4'd2, + region4 = 4'd3, + region5 = 4'd4, + region6 = 4'd5, + region7 = 4'd6, + region8 = 4'd7, + region9 = 4'd8, + region10 = 4'd9, + region11 = 4'd10, + region12 = 4'd11; + +parameter action1 = 2'd0, + action2 = 2'd1, + action3 = 2'd2, + action4 = 2'd3; + +assign next_action = action; +always @ (posedge clk) begin + +if (reset) begin +state<= region1; +reward <= 32'b0; +end + +else begin + case(final_state) + + region1: + begin + case (state) + + region1: + begin + case(action) + + action1: + begin + state <= region1; + reward <= reward + (32'd1000<<4); + end + action2: + begin + state <= region7; + reward <= reward - (32'd1000<<4); + end + action3: + begin + state <= region1; + reward <= reward + (32'd1000<<4); + end + action4: + begin + state <= region2; + reward <= reward - (32'd1000<<4); + end + endcase + + end + + region2: + begin + case(action) + + action1: + begin + state <= region2; + reward <= reward; + end + action2: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region1; + reward <= reward + (32'd1000<<4); + end + action4: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region3: + begin + case(action) + + action1: + begin + state <= region3; + reward <= reward; + end + action2: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region4: + begin + case(action) + + action1: + begin + state <= region4; + reward <= reward; + end + action2: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region5: + begin + case(action) + + action1: + begin + state <= region5; + reward <= reward; + end + action2: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region6; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region6: + begin + case(action) + + action1: + begin + state <= region6; + reward <= reward; + end + action2: + begin + state <= region12; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region6; + reward <= reward; + end + endcase + + end + //////////////////////////////// + region7: + begin + case(action) + + action1: + begin + state <= region1; + reward <= reward + (32'd1000<<4); + end + action2: + begin + state <= region7; + reward <= reward; + end + action3: + begin + state <= region7; + reward <= reward; + end + action4: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region8: + begin + case(action) + + action1: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region8; + reward <= reward ; + end + action3: + begin + state <= region7; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region9: + begin + case(action) + + action1: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region9; + reward <= reward; + end + action3: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region10: + begin + case(action) + + action1: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region10; + reward <= reward; + end + action3: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region11: + begin + case(action) + + action1: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region11; + reward <= reward; + end + action3: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region12; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region12: + begin + case(action) + + action1: + begin + state <= region6; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region12; + reward <= reward; + end + action3: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region12; + reward <= reward; + end + endcase + + end + + + endcase + end + + + region2: + begin + case (state) + + region1: + begin + case(action) + + action1: + begin + state <= region1; + reward <= reward ; + end + action2: + begin + state <= region7; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region1; + reward <= reward; + end + action4: + begin + state <= region2; + reward <= reward + (32'd1000<<4); + end + endcase + + end + + region2: + begin + case(action) + + action1: + begin + state <= region2; + reward <= reward + (32'd1000<<4); + end + action2: + begin + state <= region8; + reward <= reward - (32'd1000<<4); + end + action3: + begin + state <= region1; + reward <= reward - (32'd1000<<4); + end + action4: + begin + state <= region3; + reward <= reward - (32'd1000<<4); + end + endcase + + end + + region3: + begin + case(action) + + action1: + begin + state <= region3; + reward <= reward; + end + action2: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region2; + reward <= reward + (32'd1000<<4); + end + action4: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region4: + begin + case(action) + + action1: + begin + state <= region4; + reward <= reward; + end + action2: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region5: + begin + case(action) + + action1: + begin + state <= region5; + reward <= reward; + end + action2: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region6; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region6: + begin + case(action) + + action1: + begin + state <= region6; + reward <= reward; + end + action2: + begin + state <= region12; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region6; + reward <= reward; + end + endcase + + end + //////////////////////////////// + region7: + begin + case(action) + + action1: + begin + state <= region1; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region7; + reward <= reward; + end + action3: + begin + state <= region7; + reward <= reward; + end + action4: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region8: + begin + case(action) + + action1: + begin + state <= region2; + reward <= reward + (32'd1000<<4); + end + action2: + begin + state <= region8; + reward <= reward ; + end + action3: + begin + state <= region7; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region9: + begin + case(action) + + action1: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region9; + reward <= reward; + end + action3: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region10: + begin + case(action) + + action1: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region10; + reward <= reward; + end + action3: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region11: + begin + case(action) + + action1: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region11; + reward <= reward; + end + action3: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region12; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region12: + begin + case(action) + + action1: + begin + state <= region6; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region12; + reward <= reward; + end + action3: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region12; + reward <= reward; + end + endcase + + end + + + endcase + end + + + + region3: + begin + case (state) + + region1: + begin + case(action) + + action1: + begin + state <= region1; + reward <= reward ; + end + action2: + begin + state <= region7; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region1; + reward <= reward; + end + action4: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region2: + begin + case(action) + + action1: + begin + state <= region2; + reward <= reward; + end + action2: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region1; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region3; + reward <= reward + (32'd1000<<4); + end + endcase + + end + + region3: + begin + case(action) + + action1: + begin + state <= region3; + reward <= reward + (32'd1000<<4); + end + action2: + begin + state <= region9; + reward <= reward - (32'd1000<<4); + end + action3: + begin + state <= region2; + reward <= reward - (32'd1000<<4); + end + action4: + begin + state <= region4; + reward <= reward - (32'd1000<<4); + end + endcase + + end + + region4: + begin + case(action) + + action1: + begin + state <= region4; + reward <= reward; + end + action2: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region3; + reward <= reward + (32'd1000<<4); + end + action4: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region5: + begin + case(action) + + action1: + begin + state <= region5; + reward <= reward; + end + action2: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region6; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region6: + begin + case(action) + + action1: + begin + state <= region6; + reward <= reward; + end + action2: + begin + state <= region12; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region6; + reward <= reward; + end + endcase + + end + //////////////////////////////// + region7: + begin + case(action) + + action1: + begin + state <= region1; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region7; + reward <= reward; + end + action3: + begin + state <= region7; + reward <= reward; + end + action4: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region8: + begin + case(action) + + action1: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region8; + reward <= reward ; + end + action3: + begin + state <= region7; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region9: + begin + case(action) + + action1: + begin + state <= region3; + reward <= reward + (32'd1000<<4); + end + action2: + begin + state <= region9; + reward <= reward; + end + action3: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region10: + begin + case(action) + + action1: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region10; + reward <= reward; + end + action3: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region11: + begin + case(action) + + action1: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region11; + reward <= reward; + end + action3: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region12; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region12: + begin + case(action) + + action1: + begin + state <= region6; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region12; + reward <= reward; + end + action3: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region12; + reward <= reward; + end + endcase + + end + + + endcase + end + + + region4: + begin + case (state) + + region1: + begin + case(action) + + action1: + begin + state <= region1; + reward <= reward ; + end + action2: + begin + state <= region7; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region1; + reward <= reward; + end + action4: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region2: + begin + case(action) + + action1: + begin + state <= region2; + reward <= reward; + end + action2: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region1; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region3: + begin + case(action) + + action1: + begin + state <= region3; + reward <= reward; + end + action2: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region4; + reward <= reward + (32'd1000<<4); + end + endcase + + end + + region4: + begin + case(action) + + action1: + begin + state <= region4; + reward <= reward + (32'd1000<<4); + end + action2: + begin + state <= region10; + reward <= reward - (32'd1000<<4); + end + action3: + begin + state <= region3; + reward <= reward - (32'd1000<<4); + end + action4: + begin + state <= region5; + reward <= reward - (32'd1000<<4); + end + endcase + + end + + region5: + begin + case(action) + + action1: + begin + state <= region5; + reward <= reward; + end + action2: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region4; + reward <= reward + (32'd1000<<4); + end + action4: + begin + state <= region6; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region6: + begin + case(action) + + action1: + begin + state <= region6; + reward <= reward; + end + action2: + begin + state <= region12; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region6; + reward <= reward; + end + endcase + + end + //////////////////////////////// + region7: + begin + case(action) + + action1: + begin + state <= region1; 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+ end + action3: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region5: + begin + case(action) + + action1: + begin + state <= region5; + reward <= reward; + end + action2: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region6; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region6: + begin + case(action) + + action1: + begin + state <= region6; + reward <= reward; + end + action2: + begin + state <= region12; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region6; + reward <= reward; + end + endcase + + end + //////////////////////////////// + region7: + begin + case(action) + + action1: + begin + state <= region1; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region7; + reward <= reward; + end + action3: + begin + state <= region7; + reward <= reward; + end + action4: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region8: + begin + case(action) + + action1: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region8; + reward <= reward ; + end + action3: + begin + state <= region7; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region9; + reward <= reward + (32'd1000<<4); + end + endcase + + end + + region9: + begin + case(action) + + action1: + begin + state <= region3; + reward <= reward - (32'd1000<<4); + end + action2: + begin + state <= region9; + reward <= reward + (32'd1000<<4); + end + action3: + begin + state <= region8; + reward <= reward - (32'd1000<<4); + end + action4: + begin + state <= region10; + reward <= reward - (32'd1000<<4); + end + endcase + + end + + region10: + begin + case(action) + + action1: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region10; + reward <= reward; + end + action3: + begin + state <= region9; + reward <= reward + (32'd1000<<4); + end + action4: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region11: + begin + case(action) + + action1: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region11; + reward <= reward; + end + action3: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region12; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region12: + begin + case(action) + + action1: + begin + state <= region6; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region12; + reward <= reward; + end + action3: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region12; + reward <= reward; + end + endcase + + end + + + endcase + end + + + region10: + begin + case (state) + + region1: + begin + case(action) + + action1: + begin + state <= region1; + reward <= reward ; + end + action2: + begin + state <= region7; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region1; + reward <= reward; + end + action4: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region2: + begin + case(action) + + action1: + begin + state <= region2; + reward <= reward; + end + action2: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region1; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region3: + begin + case(action) + + action1: + begin + state <= region3; + reward <= reward; + end + action2: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region4: + begin + case(action) + + action1: + begin + state <= region4; + reward <= reward; + end + action2: + begin + state <= region10; + reward <= reward + (32'd1000<<4); + end + action3: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region5: + begin + case(action) + + action1: + begin + state <= region5; + reward <= reward; + end + action2: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region6; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region6: + begin + case(action) + + action1: + begin + state <= region6; + reward <= reward; + end + action2: + begin + state <= region12; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region6; + reward <= reward; + end + endcase + + end + //////////////////////////////// + region7: + begin + case(action) + + action1: + begin + state <= region1; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region7; + reward <= reward; + end + action3: + begin + state <= region7; + reward <= reward; + end + action4: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region8: + begin + case(action) + + action1: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region8; + reward <= reward ; + end + action3: + begin + state <= region7; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region9: + begin + case(action) + + action1: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region9; + reward <= reward; + end + action3: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region10; + reward <= reward + (32'd1000<<4); + end + endcase + + end + + region10: + begin + case(action) + + action1: + begin + state <= region4; + reward <= reward - (32'd1000<<4); + end + action2: + begin + state <= region10; + reward <= reward + (32'd1000<<4); + end + action3: + begin + state <= region9; + reward <= reward - (32'd1000<<4); + end + action4: + begin + state <= region11; + reward <= reward - (32'd1000<<4); + end + endcase + + end + + region11: + begin + case(action) + + action1: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region11; + reward <= reward; + end + action3: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region12; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region12: + begin + case(action) + + action1: + begin + state <= region6; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region12; + reward <= reward; + end + action3: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region12; + reward <= reward; + end + endcase + + end + + + endcase + end + + + region11: + begin + case (state) + + region1: + begin + case(action) + + action1: + begin + state <= region1; + reward <= reward ; + end + action2: + begin + state <= region7; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region1; + reward <= reward; + end + action4: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region2: + begin + case(action) + + action1: + begin + state <= region2; + reward <= reward; + end + action2: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region1; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region3: + begin + case(action) + + action1: + begin + state <= region3; + reward <= reward; + end + action2: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region4: + begin + case(action) + + action1: + begin + state <= region4; + reward <= reward; + end + action2: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region5: + begin + case(action) + + action1: + begin + state <= region5; + reward <= reward; + end + action2: + begin + state <= region11; + reward <= reward + (32'd1000<<4); + end + action3: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region6; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region6: + begin + case(action) + + action1: + begin + state <= region6; + reward <= reward; + end + action2: + begin + state <= region12; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region6; + reward <= reward; + end + endcase + + end + //////////////////////////////// + region7: + begin + case(action) + + action1: + begin + state <= region1; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region7; + reward <= reward; + end + action3: + begin + state <= region7; + reward <= reward; + end + action4: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region8: + begin + case(action) + + action1: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region8; + reward <= reward ; + end + action3: + begin + state <= region7; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region9: + begin + case(action) + + action1: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region9; + reward <= reward; + end + action3: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region10: + begin + case(action) + + action1: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region10; + reward <= reward; + end + action3: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region11; + reward <= reward + (32'd1000<<4); + end + endcase + + end + + region11: + begin + case(action) + + action1: + begin + state <= region5; + reward <= reward - (32'd1000<<4); + end + action2: + begin + state <= region11; + reward <= reward + (32'd1000<<4); + end + action3: + begin + state <= region10; + reward <= reward - (32'd1000<<4); + end + action4: + begin + state <= region12; + reward <= reward - (32'd1000<<4); + end + endcase + + end + + region12: + begin + case(action) + + action1: + begin + state <= region6; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region12; + reward <= reward; + end + action3: + begin + state <= region11; + reward <= reward + (32'd1000<<4); + end + action4: + begin + state <= region12; + reward <= reward; + end + endcase + + end + + + endcase + end + + + + + + + region12: + begin + case (state) + + region1: + begin + case(action) + + action1: + begin + state <= region1; + reward <= reward ; + end + action2: + begin + state <= region7; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region1; + reward <= reward; + end + action4: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region2: + begin + case(action) + + action1: + begin + state <= region2; + reward <= reward; + end + action2: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region1; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region3: + begin + case(action) + + action1: + begin + state <= region3; + reward <= reward; + end + action2: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region4: + begin + case(action) + + action1: + begin + state <= region4; + reward <= reward; + end + action2: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region5: + begin + case(action) + + action1: + begin + state <= region5; + reward <= reward; + end + action2: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + action3: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region6; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region6: + begin + case(action) + + action1: + begin + state <= region6; + reward <= reward; + end + action2: + begin + state <= region12; + reward <= reward + (32'd1000<<4); + end + action3: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region6; + reward <= reward; + end + endcase + + end + //////////////////////////////// + region7: + begin + case(action) + + action1: + begin + state <= region1; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region7; + reward <= reward; + end + action3: + begin + state <= region7; + reward <= reward; + end + action4: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region8: + begin + case(action) + + action1: + begin + state <= region2; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region8; + reward <= reward ; + end + action3: + begin + state <= region7; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region9: + begin + case(action) + + action1: + begin + state <= region3; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region9; + reward <= reward; + end + action3: + begin + state <= region8; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region10: + begin + case(action) + + action1: + begin + state <= region4; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region10; + reward <= reward; + end + action3: + begin + state <= region9; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region11; + reward <= reward + (32'd100<<4); + end + endcase + + end + + region11: + begin + case(action) + + action1: + begin + state <= region5; + reward <= reward + (32'd100<<4); + end + action2: + begin + state <= region11; + reward <= reward; + end + action3: + begin + state <= region10; + reward <= reward + (32'd100<<4); + end + action4: + begin + state <= region12; + reward <= reward + (32'd1000<<4); + end + endcase + + end + + region12: + begin + case(action) + + action1: + begin + state <= region6; + reward <= reward - (32'd1000<<4); + end + action2: + begin + state <= region12; + reward <= reward + (32'd1000<<4); + end + action3: + begin + state <= region11; + reward <= reward - (32'd1000<<4); + end + action4: + begin + state <= region12; + reward <= reward + (32'd1000<<4); + end + endcase + + end + + + endcase + end +endcase +end +end + +endmodule //robot_fsm + + +// LFSR_2bit: This is used as Policy Generator 1. 2 bit random number generator. LFSR: Linear Feedback Shift Register. +// A 2 bit random number generator designed with a LFSR forms a cyclic sequence, hindering the 'random' nature of the module. +// Thus, we use a 8 bit random number generator and pick 2 bits from that to decide our state. +module LFSR_2bit ( input clk, input reset, output reg [1:0] action); + +wire [7:0] random; +LFSR_8bit module_4 ( clk, reset, random) ; +always @ (posedge clk) begin + +if (reset) action <= 2'b0; + +else begin + +action<= random[5:4] ; // 2 bits selected +end + +end +endmodule + +// LFSR_8bit: used to supplement the 2 bit random number generator +module LFSR_8bit ( input clk, input reset, output reg [7:0]random); +reg bit_; + +always @ (posedge clk) begin + +if (reset) random <= 8'd85; + +else begin + bit_ <= random[7] ^ random[6] ^ random[5] ^ random[4]; + random[7:1] <= random[6:0]; + random[0] <= bit_; +end +end + +endmodule + +//policy_generator_2: the second policy generator which bases the next action on the max value of Q. used during inference. +module policy_generator_2 (input clk, input reset, input [31:0]in0_0, input [31:0]in0_1, input [31:0]in0_2, input [31:0]in0_3, output reg [1:0] action ); + + //wire [31:0] in0[0:3]; // int32 [4] + wire [31:0] Max_stage1_val_0; // int32 [2] + wire [31:0] Max_stage1_val_1; // int32 [2] + wire [31:0] Max_stage2_val; // int32 + + + // assign in0[0] = in0_0; + //assign in0[1] = in0_1; + //assign in0[2] = in0_2; + //assign in0[3] = in0_3; + + // ---- Tree max implementation ---- + // ---- Tree max stage 1 ---- + assign Max_stage1_val_0 = (in0_0 >= in0_1 ? in0_0 : in0_1); + assign Max_stage1_val_1 = (in0_2 >= in0_3? in0_2 : in0_3); + + reg [31:0] Max_stage1_val_0_flopped; // int32 [2] + reg [31:0] Max_stage1_val_1_flopped; // int32 [2] + //pipelining the tree + always @(posedge clk) begin + Max_stage1_val_0_flopped <= Max_stage1_val_0; + Max_stage1_val_1_flopped <= Max_stage1_val_1; + end + + + // ---- Tree max stage 2 ---- + assign Max_stage2_val = (Max_stage1_val_0_flopped >= Max_stage1_val_1_flopped ? Max_stage1_val_0_flopped : + Max_stage1_val_1_flopped); + + reg [31:0] Max_stage2_val_flopped; // int32 + //pipelining the tree + always @(posedge clk) begin + Max_stage2_val_flopped <= Max_stage2_val; + end + +always @ (posedge clk) begin + +if (reset== 1'b1) action<= 2'b0; +else begin + + if (Max_stage2_val_flopped == in0_0) action <= 2'd0; + else if (Max_stage2_val_flopped == in0_1) action <= 2'd1; + else if (Max_stage2_val_flopped == in0_2) action <= 2'd2; + else action <= 2'd3; + + end +end + + + + +endmodule + + +//robot_high_level: connects all the modules together +module robot_high_level ( input [3:0] final_state, input clk, input reset, input mode, output [31:0]Q); + +//final_state; //0 to 11 corresponds to region 1 to 12 + +wire [1:0] action; +wire [31:0]reward; +wire [3:0] state; +wire [1:0] next_action; +wire [7:0] alpha; +wire [7:0] gamma; +// wire mode; //mode =0 training; mode = 1 inference +wire [1:0] action_1; +wire [1:0] action_2; + +wire [31:0] Data_Type_Conversion_out1_0; +wire [31:0] Data_Type_Conversion_out1_1; +wire [31:0] Data_Type_Conversion_out1_2; +wire [31:0] Data_Type_Conversion_out1_3; + + +assign alpha = 8'b01000000; +assign gamma = 8'b01000000; + + +reg [31:0] reward_flopped_1; +reg [3:0] state_flopped_1; +reg [1:0] next_action_flopped_1; + +reg [31:0] Data_Type_Conversion_out1_0_flopped; +reg [31:0] Data_Type_Conversion_out1_1_flopped; +reg [31:0] Data_Type_Conversion_out1_2_flopped; +reg [31:0] Data_Type_Conversion_out1_3_flopped; + +FSM module_1 ( final_state, clk, reset, action, reward, state, next_action); + +always @ (posedge clk) begin + if (reset) begin + reward_flopped_1<=0; + state_flopped_1<=0; + next_action_flopped_1<=0; + end + + else begin + reward_flopped_1<=reward; + state_flopped_1<=state; + next_action_flopped_1<=next_action; + end +end +//Q_HW module_2(mode, clk, reset, 1'b1, state, next_action, reward, alpha, gamma, , Q, Data_Type_Conversion_out1_0, Data_Type_Conversion_out1_1, Data_Type_Conversion_out1_2, Data_Type_Conversion_out1_3 ); +Q_HW module_2(mode, clk, reset, 1'b1, state_flopped_1, next_action_flopped_1, reward_flopped_1, alpha, gamma, , Q, Data_Type_Conversion_out1_0, Data_Type_Conversion_out1_1, Data_Type_Conversion_out1_2, Data_Type_Conversion_out1_3 ); + +always @ (posedge clk) begin + if (reset) begin + Data_Type_Conversion_out1_0_flopped<=0; + Data_Type_Conversion_out1_1_flopped<=0; + Data_Type_Conversion_out1_2_flopped<=0; + Data_Type_Conversion_out1_3_flopped<=0; + end + + else begin + Data_Type_Conversion_out1_0_flopped<=Data_Type_Conversion_out1_0; + Data_Type_Conversion_out1_1_flopped<=Data_Type_Conversion_out1_1; + Data_Type_Conversion_out1_2_flopped<=Data_Type_Conversion_out1_2; + Data_Type_Conversion_out1_3_flopped<=Data_Type_Conversion_out1_3; + end +end + +LFSR_2bit module_3 (clk, reset, action_1); + +policy_generator_2 module_6(clk, reset, Data_Type_Conversion_out1_0_flopped, Data_Type_Conversion_out1_1_flopped, Data_Type_Conversion_out1_2_flopped, Data_Type_Conversion_out1_3_flopped , action_2); + +assign action = mode ? action_2 : action_1; + +endmodule + + + + +module robot_maze ( input clk, input reset, input mode, +output [31:0] Q_1, +output [31:0] Q_2, +output [31:0] Q_3, +output [31:0] Q_4, +output [31:0] Q_5, +output [31:0] Q_6, +output [31:0] Q_7, +output [31:0] Q_8, +output [31:0] Q_9, +output [31:0] Q_10, +output [31:0] Q_11, +output [31:0] Q_12 +); + + +robot_high_level robot_1 ( 4'd00, clk, reset, mode, Q_1); +robot_high_level robot_2 ( 4'd01, clk, reset, mode, Q_2); +robot_high_level robot_3 ( 4'd02, clk, reset, mode, Q_3); +robot_high_level robot_4 ( 4'd03, clk, reset, mode, Q_4); +robot_high_level robot_5 ( 4'd04, clk, reset, mode, Q_5); +robot_high_level robot_6 ( 4'd05, clk, reset, mode, Q_6); +robot_high_level robot_7 ( 4'd06, clk, reset, mode, Q_7); +robot_high_level robot_8 ( 4'd07, clk, reset, mode, Q_8); +robot_high_level robot_9 ( 4'd08, clk, reset, mode, Q_9); +robot_high_level robot_10 ( 4'd09, clk, reset, mode, Q_10); +robot_high_level robot_11 ( 4'd10, clk, reset, mode, Q_11); +robot_high_level robot_12 ( 4'd11, clk, reset, mode, Q_12); + +endmodule + + diff --git a/designs/koios/softmax/design.yaml b/designs/koios/softmax/design.yaml new file mode 100644 index 000000000..3a8e305bc --- /dev/null +++ b/designs/koios/softmax/design.yaml @@ -0,0 +1 @@ +top: softmax_random diff --git a/designs/koios/softmax/softmax.v b/designs/koios/softmax/softmax.v new file mode 100644 index 000000000..0dacf14e7 --- /dev/null +++ b/designs/koios/softmax/softmax.v @@ -0,0 +1,3424 @@ +////////////////////////////////////////////////////////////////////////////// +// Accelerator for Softmax classification layer. Based on implementation in: +// Z. Wei et al., “Design Space Exploration for Softmax Implementations,” in +// International Conference on Application-specific Systems, Architectures +// and Processors (ASAP), 2020. +// IEEE FP16 precision is used. +// LUT based log and exp units, Adder tree (reduction), Comparators, Subtractors. +// RAM outside of the design. +////////////////////////////////////////////////////////////////////////////// + + +////////////////////////////////////////////////////////////////////////////// +// Authors: Pragnesh Patel and Aman Arora +////////////////////////////////////////////////////////////////////////////// + +//softmax_p8_smem_rfloat16_alut_v512_b2_-0.1_0.1.v + +`ifndef DEFINES_DONE +`define DEFINES_DONE +`define EXPONENT 5 +`define MANTISSA 10 +`define SIGN 1 +`define DATAWIDTH (`SIGN+`EXPONENT+`MANTISSA) +`define IEEE_COMPLIANCE 1 +`define NUM 8 +`define ADDRSIZE 7 +`define ADDRSIZE_FOR_TB 10 +`endif + + +`timescale 1ns / 1ps + +//fixed adder adds unsigned fixed numbers. Overflow flag is high in case of overflow +module softmax( + inp, //data in from memory to max block + sub0_inp, //data inputs from memory to first-stage subtractors + sub1_inp, //data inputs from memory to second-stage subtractors + + start_addr, //the first address that contains input data in the on-chip memory + end_addr, //max address containing required data + + addr, //address corresponding to data inp + sub0_inp_addr, //address corresponding to sub0_inp + sub1_inp_addr, //address corresponding to sub1_inp + + outp0, + outp1, + outp2, + outp3, + outp4, + outp5, + outp6, + outp7, + + clk, + reset, + init, //the signal indicating to latch the new start address + done, //done signal asserts when the softmax calculation is over + start); //start signal for the overall softmax operation + + input clk; + input reset; + input start; + input init; + + input [`DATAWIDTH*`NUM-1:0] inp; + input [`DATAWIDTH*`NUM-1:0] sub0_inp; + input [`DATAWIDTH*`NUM-1:0] sub1_inp; + input [`ADDRSIZE-1:0] end_addr; + input [`ADDRSIZE-1:0] start_addr; + + output [`ADDRSIZE-1 :0] addr; + output [`ADDRSIZE-1:0] sub0_inp_addr; + output [`ADDRSIZE-1:0] sub1_inp_addr; + + output [`DATAWIDTH-1:0] outp0; + output [`DATAWIDTH-1:0] outp1; + output [`DATAWIDTH-1:0] outp2; + output [`DATAWIDTH-1:0] outp3; + output [`DATAWIDTH-1:0] outp4; + output [`DATAWIDTH-1:0] outp5; + output [`DATAWIDTH-1:0] outp6; + output [`DATAWIDTH-1:0] outp7; + output done; + + reg [`DATAWIDTH*`NUM-1:0] inp_reg; + reg [`ADDRSIZE-1:0] addr; + reg [`DATAWIDTH*`NUM-1:0] sub0_inp_reg; + reg [`DATAWIDTH*`NUM-1:0] sub1_inp_reg; + reg [`ADDRSIZE-1:0] sub0_inp_addr; + reg [`ADDRSIZE-1:0] sub1_inp_addr; + + + ////-----------control signals--------------//// + reg mode1_start; + reg mode1_run; + reg mode2_start; + reg mode2_run; + + reg mode3_stage_run2; + reg mode3_stage_run; + reg mode7_stage_run2; + reg mode7_stage_run; + + reg mode3_run; + + reg mode1_stage0_run; + reg mode1_stage1_run; + reg mode1_stage2_run; + wire mode1_stage3_run; + assign mode1_stage3_run = mode1_run; + + reg mode4_stage1_run_a; + reg mode4_stage2_run_a; + reg mode4_stage0_run; + reg mode4_stage1_run; + reg mode4_stage2_run; + reg mode4_stage3_run; + + reg mode5_run; + reg mode6_run; + reg mode7_run; + reg presub_start; + reg presub_run; + reg done; + + always @(posedge clk)begin + mode4_stage1_run_a <= mode4_stage1_run; + mode4_stage2_run_a <= mode4_stage2_run; + end + + always @(posedge clk) begin + if(reset) begin + inp_reg <= 0; + addr <= 0; + mode1_start <= 0; + mode1_run <= 0; + end + //init latch the input address + else if(init) begin + addr <= start_addr; + end + //start the mode1 max calculation + else if(start)begin + mode1_start <= 1; + end + //logic when to finish mode1 and trigger mode2 to latch the mode2 address + else if(mode1_start && addr < end_addr) begin + addr <= addr + 1; + inp_reg <= inp; + mode1_run <= 1; + end else if(addr == end_addr)begin + addr <= 0; + mode1_run <= 0; + mode1_start <= 0; + end else begin + mode1_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode1_stage2_run <= 0; + end + else if (mode1_stage3_run == 1) begin + mode1_stage2_run <= 1; + end + else begin + mode1_stage2_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode1_stage1_run <= 0; + end + else if (mode1_stage2_run == 1) begin + mode1_stage1_run <= 1; + end + else begin + mode1_stage1_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + mode1_stage0_run <= 0; + end + else if (mode1_stage1_run == 1) begin + mode1_stage0_run <= 1; + end + else begin + mode1_stage0_run <= 0; + end + end + + always @(posedge clk) begin + if(reset) begin + sub0_inp_addr <= 0; + sub0_inp_reg <= 0; + mode2_start <= 0; + mode2_run <= 0; + end + else if ((addr == end_addr) && ~(mode1_start && (addr>(expWidth - 1) == 'b11); + + + assign isNaN = isSpecial && exp[expWidth - 2]; + assign isInf = isSpecial && !exp[expWidth - 2]; + assign isZero = (exp>>(expWidth - 2) == 'b000); + assign sExp = exp; + assign sig = {1'b0, !isZero, fract}; + +endmodule + + + +module isSigNaNRecFN(in, isSigNaN); + + parameter expWidth = 3; + parameter sigWidth = 3; + + input [(expWidth + sigWidth):0] in; + output isSigNaN; + + wire isNaN = + (in[(expWidth + sigWidth - 1):(expWidth + sigWidth - 3)] == 'b111); + assign isSigNaN = isNaN && !in[sigWidth - 2]; + +endmodule + +module countLeadingZerosfp16 #(parameter inWidth = 10, parameter countWidth = 4) ( + input [(inWidth - 1):0] in, output reg [(countWidth - 1):0] count + ); + + wire [(inWidth - 1):0] reverseIn; + reverseFp16 reverse_in(in, reverseIn); + wire [inWidth:0] oneLeastReverseIn = + {1'b1, reverseIn} & ({1'b0, ~reverseIn} + 1); + + always@(*) + begin + if (oneLeastReverseIn[10] == 1) + begin + count = 4'd10; + end + else if (oneLeastReverseIn[9] == 1) + begin + count = 4'd9; + end + else if (oneLeastReverseIn[8] == 1) + begin + count= 4'd8; + end + else if (oneLeastReverseIn[7] == 1) + begin + count = 4'd7; + end + else if (oneLeastReverseIn[6] == 1) + begin + count = 4'd6; + end + else if (oneLeastReverseIn[5] == 1) + begin + count = 4'd5; + end + else if (oneLeastReverseIn[4] == 1) + begin + count = 4'd4; + end + else if (oneLeastReverseIn[3] == 1) + begin + count = 4'd3; + end + else if (oneLeastReverseIn[2] == 1) + begin + count = 4'd2; + end + else if (oneLeastReverseIn[1] == 1) + begin + count = 4'd1; + end + else + begin + count = 4'd0; + end + end + +endmodule + + +////////////////////////////////////////////////////// +// Log unit +////////////////////////////////////////////////////// + +module logunit (clk, rst, a, z, status); + + input clk; + input rst; + input [15:0] a; + output [15:0] z; + output [4:0] status; + + wire [15: 0] fxout1; + wire [15: 0] fxout2; + + + LUT1 lut1 (.addr(a[14:10]),.log(fxout1)); + LUT2 lut2 (.addr(a[9:4]),.log(fxout2)); + + wire clk_NC; + wire rst_NC; + + //DW_fp_addsub #(`MANTISSA, `EXPONENT, `IEEE_COMPLIANCE) add(.a(fxout1), .b(fxout2), .rnd(3'b0), .op(1'b0), .z(z), .status(status[7:0])); + FPAddSub add (.clk(clk), .rst(rst), .a(fxout1), .b(fxout2), .operation(1'b1), .result(z), .flags()); +endmodule + +module LUT1(addr, log); + input [4:0] addr; + output reg [15:0] log; + + always @(addr) begin + case (addr) + 5'b0 : log = 16'b1111110000000000; + 5'b1 : log = 16'b1100100011011010; + 5'b10 : log = 16'b1100100010000001; + 5'b11 : log = 16'b1100100000101001; + 5'b100 : log = 16'b1100011110100000; + 5'b101 : log = 16'b1100011011101110; + 5'b110 : log = 16'b1100011000111101; + 5'b111 : log = 16'b1100010110001100; + 5'b1000 : log = 16'b1100010011011010; + 5'b1001 : log = 16'b1100010000101001; + 5'b1010 : log = 16'b1100001011101110; + 5'b1011 : log = 16'b1100000110001100; + 5'b1100 : log = 16'b1100000000101001; + 5'b1101 : log = 16'b1011110110001100; + 5'b1110 : log = 16'b1011100110001100; + 5'b1111 : log = 16'b0000000000000000; + 5'b10000 : log = 16'b0011100110001100; + 5'b10001 : log = 16'b0011110110001100; + 5'b10010 : log = 16'b0100000000101001; + 5'b10011 : log = 16'b0100000110001100; + 5'b10100 : log = 16'b0100001011101110; + 5'b10101 : log = 16'b0100010000101001; + 5'b10110 : log = 16'b0100010011011010; + 5'b10111 : log = 16'b0100010110001100; + 5'b11000 : log = 16'b0100011000111101; + 5'b11001 : log = 16'b0100011011101110; + 5'b11010 : log = 16'b0100011110100000; + 5'b11011 : log = 16'b0100100000101001; + 5'b11100 : log = 16'b0100100010000001; + 5'b11101 : log = 16'b0100100011011010; + 5'b11110 : log = 16'b0100100100110011; + 5'b11111 : log = 16'b0111110000000000; + endcase + end +endmodule + +module LUT2(addr, log); + input [5:0] addr; + output reg [15:0] log; + + always @(addr) begin + case (addr) + 6'b0 : log = 16'b0000000000000000; + 6'b1 : log = 16'b0010001111110000; + 6'b10 : log = 16'b0010011111100001; + 6'b11 : log = 16'b0010100111011101; + 6'b100 : log = 16'b0010101111000011; + 6'b101 : log = 16'b0010110011010000; + 6'b110 : log = 16'b0010110110111100; + 6'b111 : log = 16'b0010111010100101; + 6'b1000 : log = 16'b0010111110001010; + 6'b1001 : log = 16'b0011000000110110; + 6'b1010 : log = 16'b0011000010100101; + 6'b1011 : log = 16'b0011000100010011; + 6'b1100 : log = 16'b0011000110000000; + 6'b1101 : log = 16'b0011000111101011; + 6'b1110 : log = 16'b0011001001010101; + 6'b1111 : log = 16'b0011001010111101; + 6'b10000 : log = 16'b0011001100100100; + 6'b10001 : log = 16'b0011001110001010; + 6'b10010 : log = 16'b0011001111101110; + 6'b10011 : log = 16'b0011010000101001; + 6'b10100 : log = 16'b0011010001011010; + 6'b10101 : log = 16'b0011010010001010; + 6'b10110 : log = 16'b0011010010111010; + 6'b10111 : log = 16'b0011010011101010; + 6'b11000 : log = 16'b0011010100011000; + 6'b11001 : log = 16'b0011010101000111; + 6'b11010 : log = 16'b0011010101110100; + 6'b11011 : log = 16'b0011010110100010; + 6'b11100 : log = 16'b0011010111001110; + 6'b11101 : log = 16'b0011010111111011; + 6'b11110 : log = 16'b0011011000100111; + 6'b11111 : log = 16'b0011011001010010; + 6'b100000 : log = 16'b0011011001111101; + 6'b100001 : log = 16'b0011011010100111; + 6'b100010 : log = 16'b0011011011010001; + 6'b100011 : log = 16'b0011011011111011; + 6'b100100 : log = 16'b0011011100100100; + 6'b100101 : log = 16'b0011011101001101; + 6'b100110 : log = 16'b0011011101110101; + 6'b100111 : log = 16'b0011011110011101; + 6'b101000 : log = 16'b0011011111000101; + 6'b101001 : log = 16'b0011011111101100; + 6'b101010 : log = 16'b0011100000001001; + 6'b101011 : log = 16'b0011100000011101; + 6'b101100 : log = 16'b0011100000110000; + 6'b101101 : log = 16'b0011100001000010; + 6'b101110 : log = 16'b0011100001010101; + 6'b101111 : log = 16'b0011100001101000; + 6'b110000 : log = 16'b0011100001111010; + 6'b110001 : log = 16'b0011100010001100; + 6'b110010 : log = 16'b0011100010011110; + 6'b110011 : log = 16'b0011100010110000; + 6'b110100 : log = 16'b0011100011000010; + 6'b110101 : log = 16'b0011100011010100; + 6'b110110 : log = 16'b0011100011100101; + 6'b110111 : log = 16'b0011100011110110; + 6'b111000 : log = 16'b0011100100000111; + 6'b111001 : log = 16'b0011100100011000; + 6'b111010 : log = 16'b0011100100101001; + 6'b111011 : log = 16'b0011100100111010; + 6'b111100 : log = 16'b0011100101001011; + 6'b111101 : log = 16'b0011100101011011; + 6'b111110 : log = 16'b0011100101101011; + 6'b111111 : log = 16'b0011100101111100; + endcase + end +endmodule + + +////////////////////////////////////////////////////// +// Exponential unit +// Author: Pragnesh Patel +////////////////////////////////////////////////////// + +module expunit (a, z, status, stage_run, stage_run2, clk, reset); + + parameter int_width = 3; // fixed point integer length + parameter frac_width = 3; // fixed point fraction length + + input [15:0] a; + input stage_run2; + input stage_run; + input clk; + input reset; + output [15:0] z; + output [7:0] status; + + wire [int_width + frac_width - 1: 0] fxout; + wire [31:0] LUTout; + reg [31:0] LUTout_reg; + reg [31:0] LUTout_reg2; + wire [15:0] Mult_out; + reg [15:0] Mult_out_reg; + reg [15:0] a_reg; + + + always @(posedge clk) begin + if(reset) begin + Mult_out_reg <= 0; + LUTout_reg <= 0; + LUTout_reg2 <= 0; + a_reg <= 0; + end + else if(stage_run2) begin + LUTout_reg2 <= LUTout; + a_reg <= a; + end + else if(stage_run) begin + Mult_out_reg <= Mult_out; + LUTout_reg <= LUTout_reg2; + end + end + + wire clk_NC, rst_NC; + + fptofixed_para fpfx (.fp(a), .fx(fxout)); + LUT lut(.addr(fxout[int_width + frac_width - 1 : 0]), .exp(LUTout)); + //DW_fp_mult #(`MANTISSA, `EXPONENT, `IEEE_COMPLIANCE) fpmult (.a(a), .b(LUTout[31:16]), .rnd(3'b000), .z(Mult_out), .status()); + FPMult fpmult (.clk(clk), .rst(reset), .a(a_reg), .b(LUTout_reg2[31:16]), .result(Mult_out), .flags()); + //DW_fp_add #(`MANTISSA, `EXPONENT, `IEEE_COMPLIANCE) fpsub (.a(Mult_out_reg), .b(LUTout_reg[15:0]), .rnd(3'b000), .z(z), .status(status[7:0])); + FPAddSub fpsub (.clk(clk), .rst(reset), .a(Mult_out_reg), .b(LUTout_reg[15:0]), .operation(1'b0), .result(z), .flags()); +endmodule + +module fptofixed_para ( + fp, + fx + ); + + parameter int_width = 3; // fixed point integer length + parameter frac_width = 3; // fixed point fraction length + + input [15:0] fp; // Half Precision fp + output [int_width + frac_width - 1:0] fx; + + wire [15:0] Mant; // mantissa of fp + wire [4:0] Ea; // non biased exponent + wire [4:0] Exp; // biased exponent + reg [15:0] sftfx; // output of shifter block + reg [15:0] temp; + + assign Mant = {6'b000001, fp[9:0]}; + assign Exp = fp[14:10]; + assign Ea = Exp - 15; + + assign fx = temp[9+int_width:10-frac_width]; + + +always @(sftfx, Ea, fp) +begin +// only negetive numbers as inputs after sorting and subtraction from max + if (Ea > int_width - 1) + begin + temp <= 16'hFFFF; // if there is an overflow + + end + else if ( fp[14:0] == 15'b0) + begin + temp <= 16'b0; + + end + else // underflow automatically becomes zero + begin + temp <= sftfx; + end +end + +//DW01_ash #(`DATAWIDTH, 5) ash( .A(Mant[15:0]), .DATA_TC(1'b0), .SH(Ea[4:0]), .SH_TC(1'b1), .B(sftfx)); +reg shift_direction; +reg [3:0] shift_magnitude; +always @(*) begin + shift_direction = Ea[4]; //if this bit is 1, that means Ea was a negative number, which means right shift. if this bit is 0, that means left shift. + shift_magnitude = (Ea[4] ? ((~Ea[3:0]) + 1) : Ea[3:0]); //take 2's complement to find the magnitude if negative + sftfx = (shift_direction ? (Mant[15:0] >> shift_magnitude) : (Mant[15:0] << shift_magnitude)); //perform the actual shift + //Mant[15:0] is unsigned, so no need to handle sign bit explicitly. zero padding is good on both direction shifts for unsigned numbers. +end + +endmodule + +module LUT(addr, exp); + input [5:0] addr; + output reg [31:0] exp; + + always @(addr) begin + case (addr) + 6'b0 : exp = 32'b00111011110000010011110000000000; + 6'b1 : exp = 32'b00111010110110000011101111101010; + 6'b10 : exp = 32'b00111010000010100011101110111110; + 6'b11 : exp = 32'b00111001010101000011101101111111; + 6'b100 : exp = 32'b00111000101101000011101100110100; + 6'b101 : exp = 32'b00111000001001110011101011100000; + 6'b110 : exp = 32'b00110111010101000011101010000111; + 6'b111 : exp = 32'b00110110011101110011101000101010; + 6'b1000 : exp = 32'b00110101101101010011100111001100; + 6'b1001 : exp = 32'b00110101000010010011100101101110; + 6'b1010 : exp = 32'b00110100011100100011100100010010; + 6'b1011 : exp = 32'b00110011110110000011100010111000; + 6'b1100 : exp = 32'b00110010111011000011100001100001; + 6'b1101 : exp = 32'b00110010000111000011100000001111; + 6'b1110 : exp = 32'b00110001011001000011011101111111; + 6'b1111 : exp = 32'b00110000110000100011011011101010; + 6'b10000 : exp = 32'b00110000001100110011011001011101; + 6'b10001 : exp = 32'b00101111011010010011010111011001; + 6'b10010 : exp = 32'b00101110100010100011010101011101; + 6'b10011 : exp = 32'b00101101110001010011010011101010; + 6'b10100 : exp = 32'b00101101000110000011010001111111; + 6'b10101 : exp = 32'b00101100011111110011010000011100; + 6'b10110 : exp = 32'b00101011111011110011001110000000; + 6'b10111 : exp = 32'b00101011000000000011001011010110; + 6'b11000 : exp = 32'b00101010001011010011001000111010; + 6'b11001 : exp = 32'b00101001011101000011000110101010; + 6'b11010 : exp = 32'b00101000110100000011000100100110; + 6'b11011 : exp = 32'b00101000001111110011000010101101; + 6'b11100 : exp = 32'b00100111011111100011000000111111; + 6'b11101 : exp = 32'b00100110100111010010111110110011; + 6'b11110 : exp = 32'b00100101110101100010111011111010; + 6'b11111 : exp = 32'b00100101001001110010111001010001; + 6'b100000 : exp = 32'b00100100100011000010110110111000; + 6'b100001 : exp = 32'b00100100000000110010110100101100; + 6'b100010 : exp = 32'b00100011000101000010110010101101; + 6'b100011 : exp = 32'b00100010001111110010110000111001; + 6'b100100 : exp = 32'b00100001100001000010101110100000; + 6'b100101 : exp = 32'b00100000110111100010101011100010; + 6'b100110 : exp = 32'b00100000010010110010101000110101; + 6'b100111 : exp = 32'b00011111100101000010100110011001; + 6'b101000 : exp = 32'b00011110101100000010100100001011; + 6'b101001 : exp = 32'b00011101111001110010100010001011; + 6'b101010 : exp = 32'b00011101001101010010100000010111; + 6'b101011 : exp = 32'b00011100100110010010011101011101; + 6'b101100 : exp = 32'b00011100000011110010011010100000; + 6'b101101 : exp = 32'b00011011001010010010010111110101; + 6'b101110 : exp = 32'b00011010010100100010010101011011; + 6'b101111 : exp = 32'b00011001100101000010010011010000; + 6'b110000 : exp = 32'b00011000111011000010010001010011; + 6'b110001 : exp = 32'b00011000010110000010001111000101; + 6'b110010 : exp = 32'b00010111101010100010001011111010; + 6'b110011 : exp = 32'b00010110110001000010001001000011; + 6'b110100 : exp = 32'b00010101111110000010000110011111; + 6'b110101 : exp = 32'b00010101010001010010000100001011; + 6'b110110 : exp = 32'b00010100101001100010000010000110; + 6'b110111 : exp = 32'b00010100000110100010000000001110; + 6'b111000 : exp = 32'b00010011001111100001111101000101; + 6'b111001 : exp = 32'b00010010011001000001111010000100; + 6'b111010 : exp = 32'b00010001101001000001110111010111; + 6'b111011 : exp = 32'b00010000111110100001110100111011; + 6'b111100 : exp = 32'b00010000011001000001110010101111; + 6'b111101 : exp = 32'b00001111110000010001110000110010; + 6'b111110 : exp = 32'b00001110110101110001101110000010; + 6'b111111 : exp = 32'b00001110000010100001101010111001; + endcase + end +endmodule + + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Floating point 16-bit multiplier +// This is a heavily modified version of: +// https://github.com/fbrosser/DSP48E1-FP/tree/master/src/FPMult +// Original author: Fredrik Brosser +// Abridged by: Samidh Mehta +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// + +`define EXPONENT 5 +`define MANTISSA 10 +`define ACTUAL_MANTISSA 11 +`define EXPONENT_LSB 10 +`define EXPONENT_MSB 14 +`define MANTISSA_LSB 0 +`define MANTISSA_MSB 9 +`define MANTISSA_MUL_SPLIT_LSB 3 +`define MANTISSA_MUL_SPLIT_MSB 9 +`define SIGN 1 +`define SIGN_LOC 15 +`define DWIDTH (`SIGN+`EXPONENT+`MANTISSA) +`define IEEE_COMPLIANCE 1 + +module FPMult( + clk, + rst, + a, + b, + result, + flags + ); + + // Input Ports + input clk ; // Clock + input rst ; // Reset signal + input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number + + // Output ports + output [`DWIDTH-1:0] result ; // Product, result of the operation, 32-bit FP number + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + assign flags = 5'b0; +`ifdef complex_dsp + mult_fp_clk_16 u_mult_fp(.clk(clk), .a(a), .b(b), .out(result)); +`else +FPMult_16 u_FPMult (.clk(clk), .rst(1'b0), .a(a), .b(b), .result(result), .flags()); +`endif + + +endmodule +`ifndef complex_dsp + +`define EXPONENT 5 +`define MANTISSA 10 +`define ACTUAL_MANTISSA 11 +`define EXPONENT_LSB 10 +`define EXPONENT_MSB 14 +`define MANTISSA_LSB 0 +`define MANTISSA_MSB 9 +`define MANTISSA_MUL_SPLIT_LSB 3 +`define MANTISSA_MUL_SPLIT_MSB 9 +`define SIGN 1 +`define SIGN_LOC 15 +`define DWIDTH (`SIGN+`EXPONENT+`MANTISSA) +`define IEEE_COMPLIANCE 1 + +module FPMult_16( + clk, + rst, + a, + b, + result, + flags + ); + + // Input Ports + input clk ; // Clock + input rst ; // Reset signal + input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number + + // Output ports + output [`DWIDTH-1:0] result ; // Product, result of the operation, 32-bit FP number + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Internal signals + wire [`DWIDTH-1:0] Z_int ; // Product, result of the operation, 32-bit FP number + wire [4:0] Flags_int ; // Flags indicating exceptions according to IEEE754 + + wire Sa ; // A's sign + wire Sb ; // B's sign + wire Sp ; // Product sign + wire [`EXPONENT-1:0] Ea ; // A's exponent + wire [`EXPONENT-1:0] Eb ; // B's exponent + wire [2*`MANTISSA+1:0] Mp ; // Product mantissa + wire [4:0] InputExc ; // Exceptions in inputs + wire [`MANTISSA-1:0] NormM ; // Normalized mantissa + wire [`EXPONENT:0] NormE ; // Normalized exponent + wire [`MANTISSA:0] RoundM ; // Normalized mantissa + wire [`EXPONENT:0] RoundE ; // Normalized exponent + wire [`MANTISSA:0] RoundMP ; // Normalized mantissa + wire [`EXPONENT:0] RoundEP ; // Normalized exponent + wire GRS ; + + //reg [63:0] pipe_0; // Pipeline register Input->Prep + reg [2*`DWIDTH-1:0] pipe_0; // Pipeline register Input->Prep + + //reg [92:0] pipe_1; // Pipeline register Prep->Execute + //reg [3*`MANTISSA+2*`EXPONENT+7:0] pipe_1; // Pipeline register Prep->Execute + reg [3*`MANTISSA+2*`EXPONENT+18:0] pipe_1; + + //reg [38:0] pipe_2; // Pipeline register Execute->Normalize + reg [`MANTISSA+`EXPONENT+7:0] pipe_2; // Pipeline register Execute->Normalize + + //reg [72:0] pipe_3; // Pipeline register Normalize->Round + reg [2*`MANTISSA+2*`EXPONENT+10:0] pipe_3; // Pipeline register Normalize->Round + + //reg [36:0] pipe_4; // Pipeline register Round->Output + reg [`DWIDTH+4:0] pipe_4; // Pipeline register Round->Output + + assign result = pipe_4[`DWIDTH+4:5] ; + assign flags = pipe_4[4:0] ; + + // Prepare the operands for alignment and check for exceptions + FPMult_PrepModule PrepModule(clk, rst, pipe_0[2*`DWIDTH-1:`DWIDTH], pipe_0[`DWIDTH-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]) ; + + // Perform (unsigned) mantissa multiplication + FPMult_ExecuteModule ExecuteModule(pipe_1[3*`MANTISSA+`EXPONENT*2+7:2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7:2*`MANTISSA+7], pipe_1[2*`MANTISSA+6:5], pipe_1[2*`MANTISSA+2*`EXPONENT+6:2*`MANTISSA+`EXPONENT+7], pipe_1[2*`MANTISSA+`EXPONENT+6:2*`MANTISSA+7], pipe_1[2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7], Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0], GRS) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + FPMult_NormalizeModule NormalizeModule(pipe_2[`MANTISSA-1:0], pipe_2[`MANTISSA+`EXPONENT:`MANTISSA], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + //FPMult_RoundModule RoundModule(pipe_3[47:24], pipe_3[23:0], pipe_3[65:57], pipe_3[56:48], pipe_3[66], pipe_3[67], pipe_3[72:68], Z_int[31:0], Flags_int[4:0]) ; + FPMult_RoundModule RoundModule(pipe_3[2*`MANTISSA+1:`MANTISSA+1], pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+2*`EXPONENT+3:2*`MANTISSA+`EXPONENT+3], pipe_3[2*`MANTISSA+`EXPONENT+2:2*`MANTISSA+2], pipe_3[2*`MANTISSA+2*`EXPONENT+4], pipe_3[2*`MANTISSA+2*`EXPONENT+5], pipe_3[2*`MANTISSA+2*`EXPONENT+10:2*`MANTISSA+2*`EXPONENT+6], Z_int[`DWIDTH-1:0], Flags_int[4:0]) ; + +//adding always@ (*) instead of posedge clock to make design combinational + always @ (posedge clk) begin + if(rst) begin + pipe_0 <= 0; + pipe_1 <= 0; + pipe_2 <= 0; + pipe_3 <= 0; + pipe_4 <= 0; + end + else begin + /* PIPE 0 + [2*`DWIDTH-1:`DWIDTH] A + [`DWIDTH-1:0] B + */ + pipe_0 <= {a, b} ; + + + /* PIPE 1 + [2*`EXPONENT+3*`MANTISSA + 18: 2*`EXPONENT+2*`MANTISSA + 18] //pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH] , mantissa of A + [2*`EXPONENT+2*`MANTISSA + 17 :2*`EXPONENT+2*`MANTISSA + 9] // pipe_0[8:0] + [2*`EXPONENT+2*`MANTISSA + 8] Sa + [2*`EXPONENT+2*`MANTISSA + 7] Sb + [2*`EXPONENT+2*`MANTISSA + 6:`EXPONENT+2*`MANTISSA+7] Ea + [`EXPONENT +2*`MANTISSA+6:2*`MANTISSA+7] Eb + [2*`MANTISSA+1+5:5] Mp + [4:0] InputExc + */ + //pipe_1 <= {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[`MANTISSA_MUL_SPLIT_LSB-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA-1:0], InputExc[4:0]} ; + pipe_1 <= {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[8:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]} ; + + /* PIPE 2 + [`EXPONENT + `MANTISSA + 7:`EXPONENT + `MANTISSA + 3] InputExc + [`EXPONENT + `MANTISSA + 2] GRS + [`EXPONENT + `MANTISSA + 1] Sp + [`EXPONENT + `MANTISSA:`MANTISSA] NormE + [`MANTISSA-1:0] NormM + */ + pipe_2 <= {pipe_1[4:0], GRS, Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0]} ; + /* PIPE 3 + [2*`EXPONENT+2*`MANTISSA+10:2*`EXPONENT+2*`MANTISSA+6] InputExc + [2*`EXPONENT+2*`MANTISSA+5] GRS + [2*`EXPONENT+2*`MANTISSA+4] Sp + [2*`EXPONENT+2*`MANTISSA+3:`EXPONENT+2*`MANTISSA+3] RoundE + [`EXPONENT+2*`MANTISSA+2:2*`MANTISSA+2] RoundEP + [2*`MANTISSA+1:`MANTISSA+1] RoundM + [`MANTISSA:0] RoundMP + */ + pipe_3 <= {pipe_2[`EXPONENT+`MANTISSA+7:`EXPONENT+`MANTISSA+1], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]} ; + /* PIPE 4 + [`DWIDTH+4:5] Z + [4:0] Flags + */ + pipe_4 <= {Z_int[`DWIDTH-1:0], Flags_int[4:0]} ; + end + end + +endmodule + + + +module FPMult_PrepModule ( + clk, + rst, + a, + b, + Sa, + Sb, + Ea, + Eb, + Mp, + InputExc + ); + + // Input ports + input clk ; + input rst ; + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [`EXPONENT-1:0] Ea ; // A's exponent + output [`EXPONENT-1:0] Eb ; // B's exponent + output [2*`MANTISSA+1:0] Mp ; // Mantissa product + output [4:0] InputExc ; // Input numbers are exceptions + + // Internal signals // If signal is high... + wire ANaN ; // A is a signalling NaN + wire BNaN ; // B is a signalling NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`MANTISSA-1:0] Ma; + wire [`MANTISSA-1:0] Mb; + + assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + + // Check for any exceptions and put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + //assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ; + + // Take input numbers apart + assign Sa = a[`DWIDTH-1] ; // A's sign + assign Sb = b[`DWIDTH-1] ; // B's sign + assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception + assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception +// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB]; + // assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB]; + + + + //assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ; + assign Mp = ({1'b1,a[`MANTISSA-1:0]}*{1'b1, b[`MANTISSA-1:0]}) ; + + + //We multiply part of the mantissa here + //Full mantissa of A + //Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B + // wire [`ACTUAL_MANTISSA-1:0] inp_A; + // wire [`ACTUAL_MANTISSA-1:0] inp_B; + // assign inp_A = {1'b1, Ma}; + // assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp)); +endmodule + + +module FPMult_ExecuteModule( + a, + b, + MpC, + Ea, + Eb, + Sa, + Sb, + Sp, + NormE, + NormM, + GRS + ); + + // Input ports + input [`MANTISSA-1:0] a ; + input [2*`EXPONENT:0] b ; + input [2*`MANTISSA+1:0] MpC ; + input [`EXPONENT-1:0] Ea ; // A's exponent + input [`EXPONENT-1:0] Eb ; // B's exponent + input Sa ; // A's sign + input Sb ; // B's sign + + // Output ports + output Sp ; // Product sign + output [`EXPONENT:0] NormE ; // Normalized exponent + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output GRS ; + + wire [2*`MANTISSA+1:0] Mp ; + + assign Sp = (Sa ^ Sb) ; // Equal signs give a positive product + + // wire [`ACTUAL_MANTISSA-1:0] inp_a; + // wire [`ACTUAL_MANTISSA-1:0] inp_b; + // assign inp_a = {1'b1, a}; + // assign inp_b = {{(`MANTISSA-`MANTISSA_MUL_SPLIT_LSB){1'b0}}, 1'b0, b}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_a), .B(inp_b), .TC(1'b0), .PRODUCT(Mp_temp)); + // DW01_add #(2*`ACTUAL_MANTISSA) u_add(.A(Mp_temp), .B(MpC<<`MANTISSA_MUL_SPLIT_LSB), .CI(1'b0), .SUM(Mp), .CO()); + + //assign Mp = (MpC<<(2*`EXPONENT+1)) + ({4'b0001, a[`MANTISSA-1:0]}*{1'b0, b[2*`EXPONENT:0]}) ; + assign Mp = MpC; + + + assign NormM = (Mp[2*`MANTISSA+1] ? Mp[2*`MANTISSA:`MANTISSA+1] : Mp[2*`MANTISSA-1:`MANTISSA]); // Check for overflow + assign NormE = (Ea + Eb + Mp[2*`MANTISSA+1]); // If so, increment exponent + + assign GRS = ((Mp[`MANTISSA]&(Mp[`MANTISSA+1]))|(|Mp[`MANTISSA-1:0])) ; + +endmodule + +module FPMult_NormalizeModule( + NormM, + NormE, + RoundE, + RoundEP, + RoundM, + RoundMP + ); + + // Input Ports + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input [`EXPONENT:0] NormE ; // Normalized exponent + + // Output Ports + output [`EXPONENT:0] RoundE ; + output [`EXPONENT:0] RoundEP ; + output [`MANTISSA:0] RoundM ; + output [`MANTISSA:0] RoundMP ; + +// EXPONENT = 5 +// EXPONENT -1 = 4 +// NEED to subtract 2^4 -1 = 15 + +wire [`EXPONENT-1 : 0] bias; + +assign bias = ((1<< (`EXPONENT -1)) -1); + + assign RoundE = NormE - bias ; + assign RoundEP = NormE - bias -1 ; + assign RoundM = NormM ; + assign RoundMP = NormM ; + +endmodule + +module FPMult_RoundModule( + RoundM, + RoundMP, + RoundE, + RoundEP, + Sp, + GRS, + InputExc, + Z, + Flags + ); + + // Input Ports + input [`MANTISSA:0] RoundM ; // Normalized mantissa + input [`MANTISSA:0] RoundMP ; // Normalized exponent + input [`EXPONENT:0] RoundE ; // Normalized mantissa + 1 + input [`EXPONENT:0] RoundEP ; // Normalized exponent + 1 + input Sp ; // Product sign + input GRS ; + input [4:0] InputExc ; + + // Output Ports + output [`DWIDTH-1:0] Z ; // Final product + output [4:0] Flags ; + + // Internal Signals + wire [`EXPONENT:0] FinalE ; // Rounded exponent + wire [`MANTISSA:0] FinalM; + wire [`MANTISSA:0] PreShiftM; + + assign PreShiftM = GRS ? RoundMP : RoundM ; // Round up if R and (G or S) + + // Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow) + assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]) ; + + assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done + + assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]} ; // Putting the pieces together + assign Flags = InputExc[4:0]; + +endmodule + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Definition of a 16-bit floating point adder/subtractor +// This is a heavily modified version of: +// https://github.com/fbrosser/DSP48E1-FP/tree/master/src/FP_AddSub +// Original author: Fredrik Brosser +// Abridged by: Samidh Mehta +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// + +module FPAddSub_16( + //bf16, + clk, + rst, + a, + b, + operation, // 0 add, 1 sub + result, + flags + ); + //input bf16; //1 for Bfloat16, 0 for IEEE half precision + + // Clock and reset + input clk ; // Clock signal + input rst ; // Reset (active high, resets pipeline registers) + + // Input ports + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + input operation ; // Operation select signal + + // Output ports + output [`DWIDTH-1:0] result ; // Result of the operation + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Pipeline Registers + //reg [79:0] pipe_1; // Pipeline register PreAlign->Align1 + reg [2*`EXPONENT + 2*`DWIDTH + 5:0] pipe_1; // Pipeline register PreAlign->Align1 + + //reg [67:0] pipe_2; // Pipeline register Align1->Align3 + //reg [2*`EXPONENT+ 2*`MANTISSA + 8:0] pipe_2; // Pipeline register Align1->Align3 + wire [2*`EXPONENT+ 2*`MANTISSA + 8:0] pipe_2; + + //reg [76:0] pipe_3; 68 // Pipeline register Align1->Align3 + reg [2*`EXPONENT+ 2*`MANTISSA + 9:0] pipe_3; // Pipeline register Align1->Align3 + + //reg [69:0] pipe_4; // Pipeline register Align3->Execute + //reg [2*`EXPONENT+ 2*`MANTISSA + 9:0] pipe_4; // Pipeline register Align3->Execute + wire [2*`EXPONENT+ 2*`MANTISSA + 9:0] pipe_4; + + //reg [51:0] pipe_5; // Pipeline register Execute->Normalize + reg [`DWIDTH+`EXPONENT+11:0] pipe_5; // Pipeline register Execute->Normalize + + //reg [56:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + //reg [`DWIDTH+`EXPONENT+16:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + wire [`DWIDTH+`EXPONENT+16:0] pipe_6; + + //reg [56:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + //reg [`DWIDTH+`EXPONENT+16:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + wire [`DWIDTH+`EXPONENT+16:0] pipe_7; + //reg [54:0] pipe_8; // Pipeline register NormalizeShift3->Round + reg [`EXPONENT*2+`MANTISSA+15:0] pipe_8; // Pipeline register NormalizeShift3->Round + + //reg [40:0] pipe_9; // Pipeline register NormalizeShift3->Round + //reg [`DWIDTH+8:0] pipe_9; // Pipeline register NormalizeShift3->Round + wire [`DWIDTH+8:0] pipe_9; + + // Internal wires between modules + wire [`DWIDTH-2:0] Aout_0 ; // A - sign + wire [`DWIDTH-2:0] Bout_0 ; // B - sign + wire Opout_0 ; // A's sign + wire Sa_0 ; // A's sign + wire Sb_0 ; // B's sign + wire MaxAB_1 ; // Indicates the larger of A and B(0/A, 1/B) + wire [`EXPONENT-1:0] CExp_1 ; // Common Exponent + wire [`EXPONENT-1:0] Shift_1 ; // Number of steps to smaller mantissa shift right (align) + wire [`MANTISSA-1:0] Mmax_1 ; // Larger mantissa + wire [4:0] InputExc_0 ; // Input numbers are exceptions + wire [2*`EXPONENT-1:0] ShiftDet_0 ; + wire [`MANTISSA-1:0] MminS_1 ; // Smaller mantissa after 0/16 shift + wire [`MANTISSA:0] MminS_2 ; // Smaller mantissa after 0/4/8/12 shift + wire [`MANTISSA:0] Mmin_3 ; // Smaller mantissa after 0/1/2/3 shift + wire [`DWIDTH:0] Sum_4 ; + wire PSgn_4 ; + wire Opr_4 ; + wire [`EXPONENT-1:0] Shift_5 ; // Number of steps to shift sum left (normalize) + wire [`DWIDTH:0] SumS_5 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_6 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_7 ; // Sum after 0/16 shift + wire [`MANTISSA-1:0] NormM_8 ; // Normalized mantissa + wire [`EXPONENT:0] NormE_8; // Adjusted exponent + wire ZeroSum_8 ; // Zero flag + wire NegE_8 ; // Flag indicating negative exponent + wire R_8 ; // Round bit + wire S_8 ; // Final sticky bit + wire FG_8 ; // Final sticky bit + wire [`DWIDTH-1:0] P_int ; + wire EOF ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_PrealignModule PrealignModule + ( // Inputs + a, b, operation, + // Outputs + Sa_0, Sb_0, ShiftDet_0[2*`EXPONENT-1:0], InputExc_0[4:0], Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Opout_0) ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_AlignModule AlignModule + ( // Inputs + pipe_1[2*`EXPONENT + 2*`DWIDTH + 4: 2*`EXPONENT +`DWIDTH + 6], pipe_1[2*`EXPONENT +`DWIDTH + 5 : 2*`EXPONENT +7], pipe_1[2*`EXPONENT+4:5], + // Outputs + CExp_1[`EXPONENT-1:0], MaxAB_1, Shift_1[`EXPONENT-1:0], MminS_1[`MANTISSA-1:0], Mmax_1[`MANTISSA-1:0]) ; + + // Alignment Shift Stage 1 + FPAddSub_AlignShift1 AlignShift1 + ( // Inputs + //bf16, + pipe_2[`MANTISSA-1:0], pipe_2[`EXPONENT+ 2*`MANTISSA + 4 : 2*`MANTISSA + 7], + // Outputs + MminS_2[`MANTISSA:0]) ; + + // Alignment Shift Stage 3 and compution of guard and sticky bits + FPAddSub_AlignShift2 AlignShift2 + ( // Inputs + pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+7:2*`MANTISSA+6], + // Outputs + Mmin_3[`MANTISSA:0]) ; + + // Perform mantissa addition + FPAddSub_ExecutionModule ExecutionModule + ( // Inputs + pipe_4[`MANTISSA*2+5:`MANTISSA+6], pipe_4[`MANTISSA:0], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 8], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 7], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 6], pipe_4[2*`EXPONENT+ 2*`MANTISSA + 9], + // Outputs + Sum_4[`DWIDTH:0], PSgn_4, Opr_4) ; + + // Prepare normalization of result + FPAddSub_NormalizeModule NormalizeModule + ( // Inputs + pipe_5[`DWIDTH:0], + // Outputs + SumS_5[`DWIDTH:0], Shift_5[4:0]) ; + + // Normalization Shift Stage 1 + FPAddSub_NormalizeShift1 NormalizeShift1 + ( // Inputs + pipe_6[`DWIDTH:0], pipe_6[`DWIDTH+`EXPONENT+14:`DWIDTH+`EXPONENT+11], + // Outputs + SumS_7[`DWIDTH:0]) ; + + // Normalization Shift Stage 3 and final guard, sticky and round bits + FPAddSub_NormalizeShift2 NormalizeShift2 + ( // Inputs + pipe_7[`DWIDTH:0], pipe_7[`DWIDTH+`EXPONENT+5:`DWIDTH+6], pipe_7[`DWIDTH+`EXPONENT+15:`DWIDTH+`EXPONENT+11], + // Outputs + NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8, FG_8) ; + + // Round and put result together + FPAddSub_RoundModule RoundModule + ( // Inputs + pipe_8[3], pipe_8[4+`EXPONENT:4], pipe_8[`EXPONENT+`MANTISSA+4:5+`EXPONENT], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT*2+`MANTISSA+15], pipe_8[`EXPONENT*2+`MANTISSA+12], pipe_8[`EXPONENT*2+`MANTISSA+11], pipe_8[`EXPONENT*2+`MANTISSA+14], pipe_8[`EXPONENT*2+`MANTISSA+10], + // Outputs + P_int[`DWIDTH-1:0], EOF) ; + + // Check for exceptions + FPAddSub_ExceptionModule Exceptionmodule + ( // Inputs + pipe_9[8+`DWIDTH:9], pipe_9[8], pipe_9[7], pipe_9[6], pipe_9[5:1], pipe_9[0], + // Outputs + result[`DWIDTH-1:0], flags[4:0]) ; + + +assign pipe_2 = {pipe_1[2*`EXPONENT + 2*`DWIDTH + 5], pipe_1[2*`EXPONENT +6:2*`EXPONENT +5], MaxAB_1, CExp_1[`EXPONENT-1:0], Shift_1[`EXPONENT-1:0], Mmax_1[`MANTISSA-1:0], pipe_1[4:0], MminS_1[`MANTISSA-1:0]} ; +assign pipe_4 = {pipe_3[2*`EXPONENT+ 2*`MANTISSA + 9:`MANTISSA+1], Mmin_3[`MANTISSA:0]} ; +assign pipe_6 = {pipe_5[`DWIDTH+`EXPONENT+11], Shift_5[4:0], pipe_5[`DWIDTH+`EXPONENT+10:`DWIDTH+1], SumS_5[`DWIDTH:0]} ; +assign pipe_7 = {pipe_6[`DWIDTH+`EXPONENT+16:`DWIDTH+1], SumS_7[`DWIDTH:0]} ; +assign pipe_9 = {P_int[`DWIDTH-1:0], pipe_8[2], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT+`MANTISSA+9:`EXPONENT+`MANTISSA+5], EOF} ; + + always @ (posedge clk) begin + if(rst) begin + pipe_1 <= 0; + //pipe_2 <= 0; + pipe_3 <= 0; + //pipe_4 <= 0; + pipe_5 <= 0; + //pipe_6 <= 0; + //pipe_7 <= 0; + pipe_8 <= 0; + //pipe_9 <= 0; + end + else begin +/* PIPE_1: + [2*`EXPONENT + 2*`DWIDTH + 5] Opout_0 + [2*`EXPONENT + 2*`DWIDTH + 4: 2*`EXPONENT +`DWIDTH + 6] A_out0 + [2*`EXPONENT +`DWIDTH + 5 : 2*`EXPONENT +7] Bout_0 + [2*`EXPONENT +6] Sa_0 + [2*`EXPONENT +5] Sb_0 + [2*`EXPONENT +4 : 5] ShiftDet_0 + [4:0] Input Exc +*/ + pipe_1 <= {Opout_0, Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Sa_0, Sb_0, ShiftDet_0[2*`EXPONENT -1:0], InputExc_0[4:0]} ; +/* PIPE_2 +[2*`EXPONENT+ 2*`MANTISSA + 8] operation +[2*`EXPONENT+ 2*`MANTISSA + 7] Sa_0 +[2*`EXPONENT+ 2*`MANTISSA + 6] Sb_0 +[2*`EXPONENT+ 2*`MANTISSA + 5] MaxAB_0 +[2*`EXPONENT+ 2*`MANTISSA + 4:`EXPONENT+ 2*`MANTISSA + 5] CExp_0 +[`EXPONENT+ 2*`MANTISSA + 4 : 2*`MANTISSA + 5] Shift_0 +[2*`MANTISSA + 4:`MANTISSA + 5] Mmax_0 +[`MANTISSA + 4 : `MANTISSA] InputExc_0 +[`MANTISSA-1:0] MminS_1 +*/ + //pipe_2 <= {pipe_1[2*`EXPONENT + 2*`DWIDTH + 5], pipe_1[2*`EXPONENT +6:2*`EXPONENT +5], MaxAB_1, CExp_1[`EXPONENT-1:0], Shift_1[`EXPONENT-1:0], Mmax_1[`MANTISSA-1:0], pipe_1[4:0], MminS_1[`MANTISSA-1:0]} ; +/* PIPE_3 +[2*`EXPONENT+ 2*`MANTISSA + 9] operation +[2*`EXPONENT+ 2*`MANTISSA + 8] Sa_0 +[2*`EXPONENT+ 2*`MANTISSA + 7] Sb_0 +[2*`EXPONENT+ 2*`MANTISSA + 6] MaxAB_0 +[2*`EXPONENT+ 2*`MANTISSA + 5:`EXPONENT+ 2*`MANTISSA + 6] CExp_0 +[`EXPONENT+ 2*`MANTISSA + 5 : 2*`MANTISSA + 6] Shift_0 +[2*`MANTISSA + 5:`MANTISSA + 6] Mmax_0 +[`MANTISSA + 5 : `MANTISSA + 1] InputExc_0 +[`MANTISSA:0] MminS_2 +*/ + pipe_3 <= {pipe_2[2*`EXPONENT+ 2*`MANTISSA + 8:`MANTISSA], MminS_2[`MANTISSA:0]} ; +/* PIPE_4 +[2*`EXPONENT+ 2*`MANTISSA + 9] operation +[2*`EXPONENT+ 2*`MANTISSA + 8] Sa_0 +[2*`EXPONENT+ 2*`MANTISSA + 7] Sb_0 +[2*`EXPONENT+ 2*`MANTISSA + 6] MaxAB_0 +[2*`EXPONENT+ 2*`MANTISSA + 5:`EXPONENT+ 2*`MANTISSA + 6] CExp_0 +[`EXPONENT+ 2*`MANTISSA + 5 : 2*`MANTISSA + 6] Shift_0 +[2*`MANTISSA + 5:`MANTISSA + 6] Mmax_0 +[`MANTISSA + 5 : `MANTISSA + 1] InputExc_0 +[`MANTISSA:0] MminS_3 +*/ + //pipe_4 <= {pipe_3[2*`EXPONENT+ 2*`MANTISSA + 9:`MANTISSA+1], Mmin_3[`MANTISSA:0]} ; +/* PIPE_5 : +[`DWIDTH+ `EXPONENT + 11] operation +[`DWIDTH+ `EXPONENT + 10] PSgn_4 +[`DWIDTH+ `EXPONENT + 9] Opr_4 +[`DWIDTH+ `EXPONENT + 8] Sa_0 +[`DWIDTH+ `EXPONENT + 7] Sb_0 +[`DWIDTH+ `EXPONENT + 6] MaxAB_0 +[`DWIDTH+ `EXPONENT + 5 :`DWIDTH+6] CExp_0 +[`DWIDTH+5:`DWIDTH+1] InputExc_0 +[`DWIDTH:0] Sum_4 +*/ + pipe_5 <= {pipe_4[2*`EXPONENT+ 2*`MANTISSA + 9], PSgn_4, Opr_4, pipe_4[2*`EXPONENT+ 2*`MANTISSA + 8:`EXPONENT+ 2*`MANTISSA + 6], pipe_4[`MANTISSA+5:`MANTISSA+1], Sum_4[`DWIDTH:0]} ; +/* PIPE_6 : +[`DWIDTH+ `EXPONENT + 16] operation +[`DWIDTH+ `EXPONENT + 15:`DWIDTH+ `EXPONENT + 11] Shift_5 +[`DWIDTH+ `EXPONENT + 10] PSgn_4 +[`DWIDTH+ `EXPONENT + 9] Opr_4 +[`DWIDTH+ `EXPONENT + 8] Sa_0 +[`DWIDTH+ `EXPONENT + 7] Sb_0 +[`DWIDTH+ `EXPONENT + 6] MaxAB_0 +[`DWIDTH+ `EXPONENT + 5 :`DWIDTH+6] CExp_0 +[`DWIDTH+5:`DWIDTH+1] InputExc_0 +[`DWIDTH:0] Sum_4 +*/ + //pipe_6 <= {pipe_5[`DWIDTH+`EXPONENT+11], Shift_5[4:0], pipe_5[`DWIDTH+`EXPONENT+10:`DWIDTH+1], SumS_5[`DWIDTH:0]} ; +/* PIPE_7 : +[`DWIDTH+ `EXPONENT + 16] operation +[`DWIDTH+ `EXPONENT + 15:`DWIDTH+ `EXPONENT + 11] Shift_5 +[`DWIDTH+ `EXPONENT + 10] PSgn_4 +[`DWIDTH+ `EXPONENT + 9] Opr_4 +[`DWIDTH+ `EXPONENT + 8] Sa_0 +[`DWIDTH+ `EXPONENT + 7] Sb_0 +[`DWIDTH+ `EXPONENT + 6] MaxAB_0 +[`DWIDTH+ `EXPONENT + 5 :`DWIDTH+6] CExp_0 +[`DWIDTH+5:`DWIDTH+1] InputExc_0 +[`DWIDTH:0] Sum_4 +*/ + //pipe_7 <= {pipe_6[`DWIDTH+`EXPONENT+16:`DWIDTH+1], SumS_7[`DWIDTH:0]} ; +/* PIPE_8: +[2*`EXPONENT + `MANTISSA + 15] FG_8 +[2*`EXPONENT + `MANTISSA + 14] operation +[2*`EXPONENT + `MANTISSA + 13] PSgn_4 +[2*`EXPONENT + `MANTISSA + 12] Sa_0 +[2*`EXPONENT + `MANTISSA + 11] Sb_0 +[2*`EXPONENT + `MANTISSA + 10] MaxAB_0 +[2*`EXPONENT + `MANTISSA + 9:`EXPONENT + `MANTISSA + 10] CExp_0 +[`EXPONENT + `MANTISSA + 9:`EXPONENT + `MANTISSA + 5] InputExc_8 +[`EXPONENT + `MANTISSA + 4 :`EXPONENT + 5] NormM_8 +[`EXPONENT + 4 :4] NormE_8 +[3] ZeroSum_8 +[2] NegE_8 +[1] R_8 +[0] S_8 +*/ + pipe_8 <= {FG_8, pipe_7[`DWIDTH+`EXPONENT+16], pipe_7[`DWIDTH+`EXPONENT+10], pipe_7[`DWIDTH+`EXPONENT+8:`DWIDTH+1], NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8} ; +/* pipe_9: +[`DWIDTH + 8 :9] P_int +[8] NegE_8 +[7] R_8 +[6] S_8 +[5:1] InputExc_8 +[0] EOF +*/ + //pipe_9 <= {P_int[`DWIDTH-1:0], pipe_8[2], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT+`MANTISSA+9:`EXPONENT+`MANTISSA+5], EOF} ; + end + end + +endmodule + + +// +// Description: The pre-alignment module is responsible for taking the inputs +// apart and checking the parts for exceptions. +// The exponent difference is also calculated in this module. +// + + +module FPAddSub_PrealignModule( + A, + B, + operation, + Sa, + Sb, + ShiftDet, + InputExc, + Aout, + Bout, + Opout + ); + + // Input ports + input [`DWIDTH-1:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] B ; // Input B, a 32-bit floating point number + input operation ; + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [2*`EXPONENT-1:0] ShiftDet ; + output [4:0] InputExc ; // Input numbers are exceptions + output [`DWIDTH-2:0] Aout ; + output [`DWIDTH-2:0] Bout ; + output Opout ; + + // Internal signals // If signal is high... + wire ANaN ; // A is a NaN (Not-a-Number) + wire BNaN ; // B is a NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`EXPONENT-1:0] DAB ; // ExpA - ExpB + wire [`EXPONENT-1:0] DBA ; // ExpB - ExpA + + assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + + // Put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + + //assign DAB = (A[30:23] - B[30:23]) ; + //assign DBA = (B[30:23] - A[30:23]) ; + assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1) ; + assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1) ; + + assign Sa = A[`DWIDTH-1] ; // A's sign bit + assign Sb = B[`DWIDTH-1] ; // B's sign bit + assign ShiftDet = {DBA[`EXPONENT-1:0], DAB[`EXPONENT-1:0]} ; // Shift data + assign Opout = operation ; + assign Aout = A[`DWIDTH-2:0] ; + assign Bout = B[`DWIDTH-2:0] ; + +endmodule + + +// +// Description: The alignment module determines the larger input operand and +// sets the mantissas, shift and common exponent accordingly. +// + + +module FPAddSub_AlignModule ( + A, + B, + ShiftDet, + CExp, + MaxAB, + Shift, + Mmin, + Mmax + ); + + // Input ports + input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-2:0] B ; // Input B, a 32-bit floating point number + input [2*`EXPONENT-1:0] ShiftDet ; + + // Output ports + output [`EXPONENT-1:0] CExp ; // Common Exponent + output MaxAB ; // Incidates larger of A and B (0/A, 1/B) + output [`EXPONENT-1:0] Shift ; // Number of steps to smaller mantissa shift right + output [`MANTISSA-1:0] Mmin ; // Smaller mantissa + output [`MANTISSA-1:0] Mmax ; // Larger mantissa + + // Internal signals + //wire BOF ; // Check for shifting overflow if B is larger + //wire AOF ; // Check for shifting overflow if A is larger + + assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]) ; + //assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits + //assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits + + // Determine final shift value + //assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ; + + assign Shift = MaxAB ? ShiftDet[2*`EXPONENT-1:`EXPONENT] : ShiftDet[`EXPONENT-1:0] ; + + // Take out smaller mantissa and append shift space + assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0] ; + + // Take out larger mantissa + assign Mmax = MaxAB ? B[`MANTISSA-1:0]: A[`MANTISSA-1:0] ; + + // Common exponent + assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]) ; + +endmodule + + +// Description: Alignment shift stage 1, performs 16|12|8|4 shift +// + + +// ONLY THIS MODULE IS HARDCODED for half precision fp16 and bfloat16 +module FPAddSub_AlignShift1( + //bf16, + MminP, + Shift, + Mmin + ); + + // Input ports + //input bf16; + input [`MANTISSA-1:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bits + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + + wire bf16; + assign bf16 = 1'b0; //hardcoding to 1, to avoid ODIN issue. a `ifdef here wasn't working. apparently, nested `ifdefs don't work + + // Internal signals + reg [`MANTISSA:0] Lvl1; + reg [`MANTISSA:0] Lvl2; + wire [2*`MANTISSA+1:0] Stage1; + integer i; // Loop variable + + always @(*) begin + if (bf16 == 1'b1) begin +//hardcoding for bfloat16 + //For bfloat16, we can shift the mantissa by a max of 7 bits since mantissa has a width of 7. + //Hence if either, bit[3]/bit[4]/bit[5]/bit[6]/bit[7] is 1, we can make it 0. This corresponds to bits [5:1] in our updated shift which doesn't contain last 2 bits. + //Lvl1 <= (Shift[1]|Shift[2]|Shift[3]|Shift[4]|Shift[5]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width + Lvl1 <= (|Shift[`EXPONENT-3:1]) ? 'd0 : {1'b1, MminP}; // MANTISSA + 1 width + end + else begin + //for half precision fp16, 10 bits can be shifted. Hence, only shifts till 10 (01010)can be made. + Lvl1 <= Shift[2] ? 'd0 : {1'b1, MminP}; + end + end + + assign Stage1 = {Lvl1, Lvl1}; //2*MANTISSA + 2 width + + always @(*) begin // Rotate {0 | 4 } bits + if(bf16 == 1'b1) begin + case (Shift[0]) + // Rotate by 0 + 1'b0: Lvl2 <= Stage1[`MANTISSA:0]; + // Rotate by 4 + 1'b1: Lvl2 <= Stage1[`MANTISSA+4:4]; + endcase + end + else begin + case (Shift[1:0]) // Rotate {0 | 4 | 8} bits + // Rotate by 0 + 2'b00: Lvl2 <= Stage1[`MANTISSA:0]; + // Rotate by 4 + 2'b01: Lvl2 <= Stage1[`MANTISSA+4:4]; + // Rotate by 8 + 2'b10: Lvl2 <= Stage1[`MANTISSA+8:8]; + // Rotate by 12 + 2'b11: Lvl2[`MANTISSA: 0] <= 0; + //2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end + endcase + end + end + + // Assign output to next shift stage + assign Mmin = Lvl2; + +endmodule + + +// Description: Alignment shift stage 2, performs 3|2|1 shift +// + + +module FPAddSub_AlignShift2( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`MANTISSA:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [1:0] Shift ; // Shift amount. Last 2 bits + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + // Internal Signal + reg [`MANTISSA:0] Lvl3; + wire [2*`MANTISSA+1:0] Stage2; + integer j; // Loop variable + + assign Stage2 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl3 <= Stage2[`MANTISSA:0]; + // Rotate by 1 + 2'b01: Lvl3 <= Stage2[`MANTISSA+1:1]; + // Rotate by 2 + 2'b10: Lvl3 <= Stage2[`MANTISSA+2:2]; + // Rotate by 3 + 2'b11: Lvl3 <= Stage2[`MANTISSA+3:3]; + endcase + end + + // Assign output + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + + +// +// Description: Module that executes the addition or subtraction on mantissas. +// + + +module FPAddSub_ExecutionModule( + Mmax, + Mmin, + Sa, + Sb, + MaxAB, + OpMode, + Sum, + PSgn, + Opr + ); + + // Input ports + input [`MANTISSA-1:0] Mmax ; // The larger mantissa + input [`MANTISSA:0] Mmin ; // The smaller mantissa + input Sa ; // Sign bit of larger number + input Sb ; // Sign bit of smaller number + input MaxAB ; // Indicates the larger number (0/A, 1/B) + input OpMode ; // Operation to be performed (0/Add, 1/Sub) + + // Output ports + output [`DWIDTH:0] Sum ; // The result of the operation + output PSgn ; // The sign for the result + output Opr ; // The effective (performed) operation + + wire [`EXPONENT-1:0]temp_1; + + assign Opr = (OpMode^Sa^Sb); // Resolve sign to determine operation + assign temp_1 = 0; + // Perform effective operation +//SAMIDH_UNSURE 5--> 8 + + assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, temp_1} - {Mmin, temp_1}) : ({1'b1, Mmax, temp_1} + {Mmin, temp_1}) ; + + // Assign result sign + assign PSgn = (MaxAB ? Sb : Sa) ; + +endmodule + + +// +// Description: Determine the normalization shift amount and perform 16-shift +// + + +module FPAddSub_NormalizeModule( + Sum, + Mmin, + Shift + ); + + // Input ports + input [`DWIDTH:0] Sum ; // Mantissa sum including hidden 1 and GRS + + // Output ports + output [`DWIDTH:0] Mmin ; // Mantissa after 16|0 shift + output [4:0] Shift ; // Shift amount + //Changes in this doesn't matter since even Bfloat16 can't go beyond 7 shift to the mantissa (only 3 bits valid here) + // Determine normalization shift amount by finding leading nought + assign Shift = ( + Sum[16] ? 5'b00000 : + Sum[15] ? 5'b00001 : + Sum[14] ? 5'b00010 : + Sum[13] ? 5'b00011 : + Sum[12] ? 5'b00100 : + Sum[11] ? 5'b00101 : + Sum[10] ? 5'b00110 : + Sum[9] ? 5'b00111 : + Sum[8] ? 5'b01000 : + Sum[7] ? 5'b01001 : + Sum[6] ? 5'b01010 : + Sum[5] ? 5'b01011 : + Sum[4] ? 5'b01100 : 5'b01101 + // Sum[19] ? 5'b01101 : + // Sum[18] ? 5'b01110 : + // Sum[17] ? 5'b01111 : + // Sum[16] ? 5'b10000 : + // Sum[15] ? 5'b10001 : + // Sum[14] ? 5'b10010 : + // Sum[13] ? 5'b10011 : + // Sum[12] ? 5'b10100 : + // Sum[11] ? 5'b10101 : + // Sum[10] ? 5'b10110 : + // Sum[9] ? 5'b10111 : + // Sum[8] ? 5'b11000 : + // Sum[7] ? 5'b11001 : 5'b11010 + ); + + reg [`DWIDTH:0] Lvl1; + + always @(*) begin + // Rotate by 16? + Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum; + end + + // Assign outputs + assign Mmin = Lvl1; // Take out smaller mantissa + +endmodule + + +// Description: Normalization shift stage 1, performs 12|8|4|3|2|1|0 shift +// +//Hardcoding loop start and end values of i. To avoid ODIN limitations. i=`DWIDTH*2+1 wasn't working. + +module FPAddSub_NormalizeShift1( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`DWIDTH:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [3:0] Shift ; // Shift amount + + // Output ports + output [`DWIDTH:0] Mmin ; // The smaller mantissa + + reg [`DWIDTH:0] Lvl2; + wire [2*`DWIDTH+1:0] Stage1; + reg [`DWIDTH:0] Lvl3; + wire [2*`DWIDTH+1:0] Stage2; + integer i; // Loop variable + + assign Stage1 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 4 | 8 | 12} bits + case (Shift[3:2]) + // Rotate by 0 + 2'b00: Lvl2 <= Stage1[`DWIDTH:0]; + // Rotate by 4 + 2'b01: Lvl2 <= Stage1[29:13]; + // Rotate by 8 + 2'b10: Lvl2 <= Stage1[25:9]; + // Rotate by 12 + 2'b11: Lvl2 <= Stage1[21:5]; + endcase + end + + assign Stage2 = {Lvl2, Lvl2}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl3 <= Stage2[`DWIDTH:0]; + // Rotate by 1 + 2'b01: Lvl3 <= Stage2[32:16]; + // Rotate by 2 + 2'b10: Lvl3 <= Stage2[31:15]; + // Rotate by 3 + 2'b11: Lvl3 <= Stage2[30:14]; + endcase + end + + // Assign outputs + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + + +// Description: Normalization shift stage 2, calculates post-normalization +// mantissa and exponent, as well as the bits used in rounding +// + + +module FPAddSub_NormalizeShift2( + PSSum, + CExp, + Shift, + NormM, + NormE, + ZeroSum, + NegE, + R, + S, + FG + ); + + // Input ports + input [`DWIDTH:0] PSSum ; // The Pre-Shift-Sum + input [`EXPONENT-1:0] CExp ; + input [4:0] Shift ; // Amount to be shifted + + // Output ports + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output [`EXPONENT:0] NormE ; // Adjusted exponent + output ZeroSum ; // Zero flag + output NegE ; // Flag indicating negative exponent + output R ; // Round bit + output S ; // Final sticky bit + output FG ; + + // Internal signals + wire MSBShift ; // Flag indicating that a second shift is needed + wire [`EXPONENT:0] ExpOF ; // MSB set in sum indicates overflow + wire [`EXPONENT:0] ExpOK ; // MSB not set, no adjustment + + // Calculate normalized exponent and mantissa, check for all-zero sum + assign MSBShift = PSSum[`DWIDTH] ; // Check MSB in unnormalized sum + assign ZeroSum = ~|PSSum ; // Check for all zero sum + assign ExpOK = CExp - Shift ; // Adjust exponent for new normalized mantissa + assign NegE = ExpOK[`EXPONENT] ; // Check for exponent overflow + assign ExpOF = CExp - Shift + 1'b1 ; // If MSB set, add one to exponent(x2) + assign NormE = MSBShift ? ExpOF : ExpOK ; // Check for exponent overflow + assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1] ; // The new, normalized mantissa + + // Also need to compute sticky and round bits for the rounding stage + assign FG = PSSum[`EXPONENT] ; + assign R = PSSum[`EXPONENT-1] ; + assign S = |PSSum[`EXPONENT-2:0] ; + +endmodule + + +// Description: Performs 'Round to nearest, tie to even'-rounding on the +// normalized mantissa according to the G, R, S bits. Calculates +// final result and checks for exponent overflow. +// + + +module FPAddSub_RoundModule( + ZeroSum, + NormE, + NormM, + R, + S, + G, + Sa, + Sb, + Ctrl, + MaxAB, + Z, + EOF + ); + + // Input ports + input ZeroSum ; // Sum is zero + input [`EXPONENT:0] NormE ; // Normalized exponent + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input R ; // Round bit + input S ; // Sticky bit + input G ; + input Sa ; // A's sign bit + input Sb ; // B's sign bit + input Ctrl ; // Control bit (operation) + input MaxAB ; + + // Output ports + output [`DWIDTH-1:0] Z ; // Final result + output EOF ; + + // Internal signals + wire [`MANTISSA:0] RoundUpM ; // Rounded up sum with room for overflow + wire [`MANTISSA-1:0] RoundM ; // The final rounded sum + wire [`EXPONENT:0] RoundE ; // Rounded exponent (note extra bit due to poential overflow ) + wire RoundUp ; // Flag indicating that the sum should be rounded up + wire FSgn; + wire ExpAdd ; // May have to add 1 to compensate for overflow + wire RoundOF ; // Rounding overflow + + wire [`EXPONENT:0]temp_2; + assign temp_2 = 0; + // The cases where we need to round upwards (= adding one) in Round to nearest, tie to even + assign RoundUp = (G & ((R | S) | NormM[0])) ; + + // Note that in the other cases (rounding down), the sum is already 'rounded' + assign RoundUpM = (NormM + 1) ; // The sum, rounded up by 1 + assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM) ; // Compute final mantissa + assign RoundOF = RoundUp & RoundUpM[`MANTISSA] ; // Check for overflow when rounding up + + // Calculate post-rounding exponent + assign ExpAdd = (RoundOF ? 1'b1 : 1'b0) ; // Add 1 to exponent to compensate for overflow + assign RoundE = ZeroSum ? temp_2 : (NormE + ExpAdd) ; // Final exponent + + // If zero, need to determine sign according to rounding + assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ; + + // Assign final result + assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]} ; + + // Indicate exponent overflow + assign EOF = RoundE[`EXPONENT]; + +endmodule + + +// +// Description: Check the final result for exception conditions and set +// flags accordingly. +// + + +module FPAddSub_ExceptionModule( + Z, + NegE, + R, + S, + InputExc, + EOF, + P, + Flags + ); + + // Input ports + input [`DWIDTH-1:0] Z ; // Final product + input NegE ; // Negative exponent? + input R ; // Round bit + input S ; // Sticky bit + input [4:0] InputExc ; // Exceptions in inputs A and B + input EOF ; + + // Output ports + output [`DWIDTH-1:0] P ; // Final result + output [4:0] Flags ; // Exception flags + + // Internal signals + wire Overflow ; // Overflow flag + wire Underflow ; // Underflow flag + wire DivideByZero ; // Divide-by-Zero flag (always 0 in Add/Sub) + wire Invalid ; // Invalid inputs or result + wire Inexact ; // Result is inexact because of rounding + + // Exception flags + + // Result is too big to be represented + assign Overflow = EOF | InputExc[1] | InputExc[0] ; + + // Result is too small to be represented + assign Underflow = NegE & (R | S); + + // Infinite result computed exactly from finite operands + assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0]; + + // Invalid inputs or operation + assign Invalid = |(InputExc[4:2]) ; + + // Inexact answer due to rounding, overflow or underflow + assign Inexact = (R | S) | Overflow | Underflow; + + // Put pieces together to form final result + assign P = Z ; + + // Collect exception flags + assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact} ; + +endmodule +`endif + + diff --git a/designs/koios/softmax/softmax_random.sv b/designs/koios/softmax/softmax_random.sv new file mode 100644 index 000000000..d2aef7df5 --- /dev/null +++ b/designs/koios/softmax/softmax_random.sv @@ -0,0 +1,82 @@ +/* +Random I/Os for softmax module +*/ + +`include "../../random_number_generator.sv" + +`ifndef DEFINES_DONE +`define DEFINES_DONE +`define EXPONENT 5 +`define MANTISSA 10 +`define SIGN 1 +`define DATAWIDTH (`SIGN+`EXPONENT+`MANTISSA) +`define IEEE_COMPLIANCE 1 +`define NUM 8 +`define ADDRSIZE 7 +`define ADDRSIZE_FOR_TB 10 +`endif + +module softmax_random ( + input wire logic clk, + input wire logic reset, + input wire logic start, + input wire logic init, + + input wire logic [`ADDRSIZE-1:0] end_addr, + input wire logic [`ADDRSIZE-1:0] start_addr, + + output logic [`ADDRSIZE-1 :0] addr, + output logic [`ADDRSIZE-1:0] sub0_inp_addr, + output logic [`ADDRSIZE-1:0] sub1_inp_addr, + + output logic [2:0] sel, + output logic [`DATAWIDTH-1:0] max_out, + output logic done +); + +logic [`DATAWIDTH-1:0] outp[3:0]; +assign max_out = outp[sel[2:0]]; + +logic [`DATAWIDTH*`NUM-1:0] inp [2:0]; +generate + genvar i; + for (i=0; i<`NUM; i=i+1) begin + RandomNumberGenerator #( + .RANDOM_WIDTH(`DATAWIDTH*`NUM), + .SEED(i) + ) rng0 ( + .clk(clk), + .reset(reset), + .random_number(inp[i]) + ); + end +endgenerate + +softmax sm0( + inp[0], //data in from memory to max block + inp[1], //data inputs from memory to first-stage subtractors + inp[2], //data inputs from memory to second-stage subtractors + + start_addr, //the first address that contains input wire logic data in the on-chip memory + end_addr, //max address containing required data + + addr, //address corresponding to data inp + sub0_inp_addr, //address corresponding to sub0_inp + sub1_inp_addr, //address corresponding to sub1_inp + + outp[0], + outp[1], + outp[2], + outp[3], + outp[4], + outp[5], + outp[6], + outp[7], + + clk, + reset, + init, //the signal indicating to latch the new start address + done, //done signal asserts when the softmax calculation is over + start); + +endmodule \ No newline at end of file diff --git a/designs/koios/spmv/design.yaml b/designs/koios/spmv/design.yaml new file mode 100644 index 000000000..9b9886fa7 --- /dev/null +++ b/designs/koios/spmv/design.yaml @@ -0,0 +1 @@ +top: spmv diff --git a/designs/koios/spmv/spmv.v b/designs/koios/spmv/spmv.v new file mode 100644 index 000000000..a166b1fb1 --- /dev/null +++ b/designs/koios/spmv/spmv.v @@ -0,0 +1,3791 @@ +////////////////////////////////////////////////////////////////////////////// +// Matrix vector multiplication design with sparsity +// This is a Sparse Matrix-Vector Multiplication accelerator design. +// The mathematical formula is Y = M * X where M is input sparse matrix, +// X is input dense vector and Y is output dense vector. We support 8-bit +// precision. Vector X is loaded in on-chip banked memory before start of +// the operation. The input to the accelerator are 3 values corresponding +// to each matrix element: data, col, number of non zero values in a row. +// There are 32 channels which can run in parallel. Each channel has a MAC +// unit. Computation for each row of the matrix is assigned to a channel +// dynamically based on the number of non zero values in that row. The final +// accumulated value is written in the output memory. The write address is +// based on row number. Hence, write is out of order with respect to rows +// in output vector. +// Multipliers in channels followed by accumulators, Banked Vector Buffer +// (RAM and crossbar) to store vector elements. Arbiter to fetch data from +// RAMs store matrix elements. Uses CISR encoding. Multiple FIFOs. +////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////// +// Author: Aatman Borda +////////////////////////////////////////////////////////////////////////////// + +//`define SIMULATION +`define COL_ID_BITS 8 +`define ROW_ID_BITS 8 +`define MAT_VAL_BITS 8 +`define VEC_VAL_BITS 8 +`define MULT_BITS (`VEC_VAL_BITS + `MAT_VAL_BITS) +`define NUM_CHANNEL 32 +`define NUM_CHANNEL_BITS $clog2(`NUM_CHANNEL) +`define LANE_NUM (3 * `NUM_CHANNEL) +// `define LANE_NUM_BITS $clog2(`LANE_NUM) +//`define NUM_MAT_VALS 8864 +`define NUM_MAT_VALS 4096 +`define NUM_COL_IDS `NUM_MAT_VALS +`define NUM_ROW_IDS `NUM_MAT_VALS +`define NUM_VEC_VALS 128 + +//`define MAT_VAL_ADDR_WIDTH $clog2(`NUM_MAT_VALS) +`define MAT_VAL_ADDR_WIDTH 12 +`define COL_ID_ADDR_WIDTH `MAT_VAL_ADDR_WIDTH +`define ROW_ID_ADDR_WIDTH `MAT_VAL_ADDR_WIDTH + +`define FIFO_DEPTH 8 +`define MAX_COLS (1<<`COL_ID_BITS) + +// MACROS for BVB +`define BYTES_PER_ADDR_PER_BRAM 1 +`define NUM_BRAMS 1 +`define VEC_VAL_BYTES (`VEC_VAL_BITS/8) +`define VEC_VAL_OFFSET $clog2(`VEC_VAL_BITS) +`define NUM_VEC_VALS_PER_ADDR_PER_BRAM (`BYTES_PER_ADDR_PER_BRAM/`VEC_VAL_BYTES) +`define NUM_VEC_VALS_PER_ADDR `NUM_VEC_VALS_PER_ADDR_PER_BRAM*`NUM_BRAMS +`define NUM_VEC_VALS_PER_ADDR_BITS $clog2(`NUM_VEC_VALS_PER_ADDR) +`define NUM_ADDR (`NUM_VEC_VALS/`NUM_VEC_VALS_PER_ADDR)+1 +`define BVB_AWIDTH `COL_ID_BITS +`define COUNTER_BITS $clog2(`NUM_ADDR) +`define LOCAL_ID_BITS `NUM_VEC_VALS_PER_ADDR_BITS + +module spmv( + input clk, + input rst, + + output [`MULT_BITS-1:0] dout, + + output reg done_reg, + + input [`MAT_VAL_BITS-1:0] mat_val_din, + input [`COL_ID_BITS-1:0] col_id_din, + input [`ROW_ID_BITS-1:0] row_id_din, + + input mat_val_wren, + input col_id_wren, + input row_id_wren, + + input [`MAT_VAL_ADDR_WIDTH-1:0] mat_val_addr_ext, + input [`COL_ID_ADDR_WIDTH-1:0] col_id_addr_ext, + input [`ROW_ID_ADDR_WIDTH-1:0] row_id_addr_ext, + + input [`NUM_VEC_VALS_PER_ADDR*`VEC_VAL_BITS-1:0] vector_din, + input vector_wren, + input [`BVB_AWIDTH-1:0] vector_addr_ext +); + + // Row ID fifo signal + wire [(`ROW_ID_BITS*`NUM_CHANNEL)-1:0] row_id; + wire [`NUM_CHANNEL-1:0] row_id_empty; + wire [`NUM_CHANNEL-1:0] row_id_rd_en; + + // column id fifo signals + wire [(`COL_ID_BITS*`NUM_CHANNEL-1):0] col_id; + wire [`NUM_CHANNEL-1:0] col_id_empty; + wire [`NUM_CHANNEL-1:0] col_id_rd_en; + + // matrix elements fifo signals + wire [(`MAT_VAL_BITS*`NUM_CHANNEL)-1:0] mat_val; + wire [`NUM_CHANNEL-1:0] mat_val_empty; + wire [`NUM_CHANNEL-1:0] mat_val_rd_en; + + // The above the FIFOs are called fetcher FIFOs as they are a part of fetcher module and are filled by fetcher. + + // Fetcher module signals. There are just the above three put together. + wire [((`ROW_ID_BITS+`COL_ID_BITS+`MAT_VAL_BITS)*`NUM_CHANNEL)-1:0] fetcher_out; + wire [3*`NUM_CHANNEL-1:0] fetcher_empty; + wire [3*`NUM_CHANNEL-1:0] fetcher_rd_en; + + // Vector values fifo signals + wire [`VEC_VAL_BITS*`NUM_CHANNEL-1:0] vec_val; + wire [`NUM_CHANNEL-1:0] vec_val_empty; + wire [`NUM_CHANNEL-1:0] vec_val_rd_en; + + // 1 if at least 1 of the fetcher FIFOs is empty + reg all_empty; + + // Signal to start the engine + reg start; + + // Output data + wire [(`MULT_BITS*`NUM_CHANNEL)-1:0] data_out; + // output fifo empty signals + wire [`NUM_CHANNEL-1:0] data_out_empty; + // Address to store output data + wire [(`ROW_ID_BITS*`NUM_CHANNEL)-1:0] addr_out; + // output fifo read enable signal + wire [`NUM_CHANNEL-1:0] out_rd_en; + // reg [`NUM_CHANNEL-1:0] out_rd_en_reg; + wire [`NUM_CHANNEL-1:0] out_rd_en_shifted; + // Memory to write the output data + + wire [`MULT_BITS-1:0] data_out_shifted; + wire [`ROW_ID_BITS-1:0] addr_out_shifted; + wire [`MULT_BITS-1:0] wr_data; + wire [`ROW_ID_BITS-1:0] wr_addr; + reg wr_en; + + // Signals to indicate that the computation is complete + wire [`NUM_CHANNEL-1:0] done; + reg done_all, last; + + wire fetcher_done; + + always@(posedge clk) begin + if (rst) begin + all_empty <= 1; + start <= 0; + end + else begin + all_empty <= (|fetcher_empty) & (~start); + if (!all_empty) begin + start <= 1; + end + end + end + + reg [`NUM_CHANNEL_BITS-1:0] counter; + reg [`NUM_CHANNEL_BITS-1:0] counter_delay; + reg [`NUM_CHANNEL_BITS-1:0] counter_store; + + assign out_rd_en = (({`NUM_CHANNEL{1'b0}})|(1<> counter; + + assign data_out_shifted = data_out >> (counter_delay*`MULT_BITS); +`ifdef QUARTUS + genvar loop_idx; + generate + for (loop_idx = 0; loop_idx < `ROW_ID_BITS; loop_idx = loop_idx + 1) begin: gen_addr_out + assign addr_out_shifted[loop_idx] = ^(addr_out[(loop_idx+1)*`NUM_CHANNEL-1:loop_idx*`NUM_CHANNEL]); + end + endgenerate +`else + assign addr_out_shifted = addr_out >> (counter_delay*`ROW_ID_BITS); +`endif + + assign wr_data = data_out_shifted; + assign wr_addr = addr_out_shifted; + + always @ (posedge clk) begin + if(rst) begin + counter <= 0; + counter_delay <= 0; + last <= 0; + end + else if(start) begin + done_all <= &done; + counter <= counter + 1; + counter_delay <= counter; + if(out_rd_en_shifted[0]) begin + wr_en <= 1; + end + else begin + wr_en <= 0; + end + if(done_all & !last) begin + counter_store <= counter_delay; + last <= 1; + end + else if (last) begin + done_reg <= (counter_store==counter_delay); + end + end + end + + spram #( + .AWIDTH(`ROW_ID_BITS), + .NUM_WORDS(`NUM_VEC_VALS), + .DWIDTH(`MULT_BITS) + ) write_mem ( + .clk(clk), + .address(wr_addr), + .wren(wr_en), + .din(wr_data), + .dout(dout) + ); + + // Assign FIFOs' read enables to the respective wires of fetcher read enable. + assign fetcher_rd_en[3*`NUM_CHANNEL-1: 2*`NUM_CHANNEL] = row_id_rd_en; + assign fetcher_rd_en[2*`NUM_CHANNEL-1: 1*`NUM_CHANNEL] = col_id_rd_en; + assign fetcher_rd_en[1*`NUM_CHANNEL-1: 0] = mat_val_rd_en; + + fetcher fetcher ( + .clk(clk), + .rst(rst), + + .mat_val_rd_en(fetcher_rd_en[1*`NUM_CHANNEL-1: 0]), + .col_id_rd_en(fetcher_rd_en[2*`NUM_CHANNEL-1: 1*`NUM_CHANNEL]), + .row_id_rd_en(fetcher_rd_en[3*`NUM_CHANNEL-1: 2*`NUM_CHANNEL]), + + .mat_val_out(fetcher_out[(1*`MAT_VAL_BITS*`NUM_CHANNEL)-1: 0]), + .col_id_out(fetcher_out[(2*`COL_ID_BITS*`NUM_CHANNEL)-1: 1*`COL_ID_BITS*`NUM_CHANNEL]), + .row_id_out(fetcher_out[(3*`ROW_ID_BITS*`NUM_CHANNEL)-1: 2*`ROW_ID_BITS*`NUM_CHANNEL]), + + .mat_val_empty(fetcher_empty[1*`NUM_CHANNEL-1: 0]), + .col_id_empty(fetcher_empty[2*`NUM_CHANNEL-1: 1*`NUM_CHANNEL]), + .row_id_empty(fetcher_empty[3*`NUM_CHANNEL-1: 2*`NUM_CHANNEL]), + + .done(fetcher_done), + .mat_val_din(mat_val_din), + .col_id_din(col_id_din), + .row_id_din(row_id_din), + .mat_val_wren(mat_val_wren), + .col_id_wren(col_id_wren), + .row_id_wren(row_id_wren), + .mat_val_addr_ext(mat_val_addr_ext), + .col_id_addr_ext(col_id_addr_ext), + .row_id_addr_ext(row_id_addr_ext) + ); + + assign row_id = fetcher_out[3*`ROW_ID_BITS*`NUM_CHANNEL-1: 2*`ROW_ID_BITS*`NUM_CHANNEL]; + assign row_id_empty = fetcher_empty[3*`NUM_CHANNEL-1: 2*`NUM_CHANNEL]; + + assign col_id = fetcher_out[2*`COL_ID_BITS*`NUM_CHANNEL-1: 1*`COL_ID_BITS*`NUM_CHANNEL]; + assign col_id_empty = fetcher_empty[2*`NUM_CHANNEL-1: 1*`NUM_CHANNEL]; + + assign mat_val = fetcher_out[1*`MAT_VAL_BITS*`NUM_CHANNEL-1: 0]; + assign mat_val_empty = fetcher_empty[1*`NUM_CHANNEL-1: 0]; + + + bvb bvb ( + .clk(clk), + .rst(rst), + .start(start), + .id(col_id), + .id_empty(col_id_empty), + .id_rd_en(col_id_rd_en), + .val(vec_val), + .val_empty(vec_val_empty), + .val_rd_en(vec_val_rd_en), + .vector_din(vector_din), + .vector_wren(vector_wren), + .vector_addr_ext(vector_addr_ext) + ); + + Big_Channel Big_Channel_ ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val), + .mat_val_empty(mat_val_empty), + .mat_val_rd_en(mat_val_rd_en), + .vec_val(vec_val), + .vec_val_empty(vec_val_empty), + .vec_val_rd_en(vec_val_rd_en), + .row_id(row_id), + .row_id_empty(row_id_empty), + .row_id_rd_en(row_id_rd_en), + .data_out(data_out), + .data_out_empty(data_out_empty), + .addr_out(addr_out), + .out_rd_en(out_rd_en), + .done(done) + ); +endmodule + + + +/* Fetcher Module */ +module fetcher( + input clk, + input rst, + + input [`NUM_CHANNEL-1:0] mat_val_rd_en, + input [`NUM_CHANNEL-1:0] col_id_rd_en, + input [`NUM_CHANNEL-1:0] row_id_rd_en, + + output [(`MAT_VAL_BITS*`NUM_CHANNEL)-1:0] mat_val_out, + output [(`COL_ID_BITS*`NUM_CHANNEL)-1:0] col_id_out, + output [(`ROW_ID_BITS*`NUM_CHANNEL)-1:0] row_id_out, + + output [`NUM_CHANNEL-1:0] mat_val_empty, + output [`NUM_CHANNEL-1:0] col_id_empty, + output [`NUM_CHANNEL-1:0] row_id_empty, + + output done, + + input [`MAT_VAL_BITS-1:0] mat_val_din, + input [`COL_ID_BITS-1:0] col_id_din, + input [`ROW_ID_BITS-1:0] row_id_din, + + input mat_val_wren, + input col_id_wren, + input row_id_wren, + + input [`MAT_VAL_ADDR_WIDTH-1:0] mat_val_addr_ext, + input [`COL_ID_ADDR_WIDTH-1:0] col_id_addr_ext, + input [`ROW_ID_ADDR_WIDTH-1:0] row_id_addr_ext + ); + +`ifdef SIMULATION + parameter MAT_VAL_FILE = "/home/aatman/Desktop/SpMV/src/coe/mat_val.txt"; + parameter COL_ID_FILE = "/home/aatman/Desktop/SpMV/src/coe/col_id.txt"; + parameter ROW_ID_FILE = "/home/aatman/Desktop/SpMV/src/coe/row_id.txt"; +`endif + + // parameter FIFO_DEPTH = 8; + parameter FIFO_DEPTH_BITS = $clog2(`FIFO_DEPTH); + + // parameter ROW_LEN_ROM_DWIDTH = `ROW_LEN_BITS * `NUM_CHANNEL; + // parameter ROW_LEN_ROM_NUM_ADDR = `NUM_ROW_LENS/`NUM_CHANNEL; + parameter ROW_ID_ROM_DWIDTH = `ROW_ID_BITS; + parameter ROW_ID_ROM_NUM_ADDR = `NUM_ROW_IDS; + parameter ROW_ID_AWIDTH = `ROW_ID_ADDR_WIDTH; + + // parameter MAT_VAL_ROM_DWIDTH = `MAT_VAL_BITS * `NUM_CHANNEL; + // parameter MAT_VAL_ROM_NUM_ADDR = `NUM_MAT_VALS/`NUM_CHANNEL; + parameter MAT_VAL_ROM_DWIDTH = `MAT_VAL_BITS; + parameter MAT_VAL_ROM_NUM_ADDR = `NUM_MAT_VALS; + parameter MAT_VAL_AWIDTH = `MAT_VAL_ADDR_WIDTH; + + // parameter COL_ID_ROM_DWIDTH = `COL_ID_BITS * `NUM_CHANNEL; + // parameter COL_ID_ROM_NUM_ADDR = `NUM_COL_IDS/`NUM_CHANNEL; + parameter COL_ID_ROM_DWIDTH = `COL_ID_BITS; + parameter COL_ID_ROM_NUM_ADDR = `NUM_COL_IDS; + parameter COL_ID_AWIDTH = `COL_ID_ADDR_WIDTH; + + parameter NUM_CHANNEL_BITS = $clog2(`NUM_CHANNEL); + + reg [MAT_VAL_AWIDTH-1:0] mat_val_addr; + reg [COL_ID_AWIDTH-1:0] col_id_addr; + reg [ROW_ID_AWIDTH-1:0] row_id_addr; + + wire [MAT_VAL_ROM_DWIDTH-1:0] mat_val_dout; + wire [COL_ID_ROM_DWIDTH-1:0] col_id_dout; + wire [ROW_ID_ROM_DWIDTH-1:0] row_id_dout; + + reg [NUM_CHANNEL_BITS-1:0] mat_val_lane; + reg [NUM_CHANNEL_BITS-1:0] col_id_lane; + reg [NUM_CHANNEL_BITS-1:0] row_id_lane; + + reg [`NUM_CHANNEL-1:0] mat_val_wr_en; + reg [`NUM_CHANNEL-1:0] col_id_wr_en; + reg [`NUM_CHANNEL-1:0] row_id_wr_en; + + wire [`NUM_CHANNEL-1:0] mat_val_full; + wire [`NUM_CHANNEL-1:0] col_id_full; + wire [`NUM_CHANNEL-1:0] row_id_full; + + wire [`NUM_CHANNEL-1:0] mat_val_full_shifted; + wire [`NUM_CHANNEL-1:0] col_id_full_shifted; + wire [`NUM_CHANNEL-1:0] row_id_full_shifted; + + // wire done; + reg [MAT_VAL_AWIDTH:0] counter; + + wire [MAT_VAL_AWIDTH-1:0] mat_val_addr_; + wire [COL_ID_AWIDTH-1:0] col_id_addr_; + wire [ROW_ID_AWIDTH-1:0] row_id_addr_; + + assign mat_val_addr_ = mat_val_wren ? mat_val_addr_ext : mat_val_addr; + assign col_id_addr_ = col_id_wren ? col_id_addr_ext : col_id_addr; + assign row_id_addr_ = row_id_wren ? row_id_addr_ext : row_id_addr; + + spram #( + `ifdef SIMULATION + .INIT(MAT_VAL_FILE), + `endif + .AWIDTH(MAT_VAL_AWIDTH), + .NUM_WORDS(MAT_VAL_ROM_NUM_ADDR), + .DWIDTH(MAT_VAL_ROM_DWIDTH) + ) mat_val_rom ( + .clk(clk), + .address(mat_val_addr_), + .wren(mat_val_wren), + .din(mat_val_din), //{MAT_VAL_ROM_DWIDTH{1'b0}}), + .dout(mat_val_dout) + ); + + spram #( + `ifdef SIMULATION + .INIT(COL_ID_FILE), + `endif + .AWIDTH(COL_ID_AWIDTH), + .NUM_WORDS(COL_ID_ROM_NUM_ADDR), + .DWIDTH(COL_ID_ROM_DWIDTH) + ) col_id_rom ( + .clk(clk), + .address(col_id_addr_), + .wren(col_id_wren), + .din(col_id_din),// {COL_ID_ROM_DWIDTH{1'b0}}), + .dout(col_id_dout) + ); + + spram #( + `ifdef SIMULATION + .INIT(ROW_ID_FILE), + `endif + .AWIDTH(ROW_ID_AWIDTH), + .NUM_WORDS(ROW_ID_ROM_NUM_ADDR), + .DWIDTH(ROW_ID_ROM_DWIDTH) + ) row_id_rom ( + .clk(clk), + .address(row_id_addr_), + .wren(row_id_wren), + .din(row_id_din), //{ROW_ID_ROM_DWIDTH{1'b0}}), + .dout(row_id_dout) + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_0 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[0]), // input wr_en + .re(mat_val_rd_en[0]), // input rd_en + .dout(mat_val_out[((0+1)*`MAT_VAL_BITS)-1:0*`MAT_VAL_BITS]), + .full(mat_val_full[0]), // output full + .empty(mat_val_empty[0]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_0 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[0]), // input wr_en + .re(col_id_rd_en[0]), // input rd_en + .dout(col_id_out[((0+1)*`COL_ID_BITS)-1:0*`COL_ID_BITS]), + .full(col_id_full[0]), // output full + .empty(col_id_empty[0]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_0 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[0]), // input wr_en + .re(row_id_rd_en[0]), // input rd_en + .dout(row_id_out[((0+1)*`ROW_ID_BITS)-1:0*`ROW_ID_BITS]), + .full(row_id_full[0]), // output full + .empty(row_id_empty[0]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_1 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[1]), // input wr_en + .re(mat_val_rd_en[1]), // input rd_en + .dout(mat_val_out[((1+1)*`MAT_VAL_BITS)-1:1*`MAT_VAL_BITS]), + .full(mat_val_full[1]), // output full + .empty(mat_val_empty[1]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_1 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[1]), // input wr_en + .re(col_id_rd_en[1]), // input rd_en + .dout(col_id_out[((1+1)*`COL_ID_BITS)-1:1*`COL_ID_BITS]), + .full(col_id_full[1]), // output full + .empty(col_id_empty[1]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_1 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[1]), // input wr_en + .re(row_id_rd_en[1]), // input rd_en + .dout(row_id_out[((1+1)*`ROW_ID_BITS)-1:1*`ROW_ID_BITS]), + .full(row_id_full[1]), // output full + .empty(row_id_empty[1]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_2 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[2]), // input wr_en + .re(mat_val_rd_en[2]), // input rd_en + .dout(mat_val_out[((2+1)*`MAT_VAL_BITS)-1:2*`MAT_VAL_BITS]), + .full(mat_val_full[2]), // output full + .empty(mat_val_empty[2]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_2 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[2]), // input wr_en + .re(col_id_rd_en[2]), // input rd_en + .dout(col_id_out[((2+1)*`COL_ID_BITS)-1:2*`COL_ID_BITS]), + .full(col_id_full[2]), // output full + .empty(col_id_empty[2]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_2 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[2]), // input wr_en + .re(row_id_rd_en[2]), // input rd_en + .dout(row_id_out[((2+1)*`ROW_ID_BITS)-1:2*`ROW_ID_BITS]), + .full(row_id_full[2]), // output full + .empty(row_id_empty[2]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_3 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[3]), // input wr_en + .re(mat_val_rd_en[3]), // input rd_en + .dout(mat_val_out[((3+1)*`MAT_VAL_BITS)-1:3*`MAT_VAL_BITS]), + .full(mat_val_full[3]), // output full + .empty(mat_val_empty[3]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_3 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[3]), // input wr_en + .re(col_id_rd_en[3]), // input rd_en + .dout(col_id_out[((3+1)*`COL_ID_BITS)-1:3*`COL_ID_BITS]), + .full(col_id_full[3]), // output full + .empty(col_id_empty[3]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_3 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[3]), // input wr_en + .re(row_id_rd_en[3]), // input rd_en + .dout(row_id_out[((3+1)*`ROW_ID_BITS)-1:3*`ROW_ID_BITS]), + .full(row_id_full[3]), // output full + .empty(row_id_empty[3]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_4 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[4]), // input wr_en + .re(mat_val_rd_en[4]), // input rd_en + .dout(mat_val_out[((4+1)*`MAT_VAL_BITS)-1:4*`MAT_VAL_BITS]), + .full(mat_val_full[4]), // output full + .empty(mat_val_empty[4]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_4 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[4]), // input wr_en + .re(col_id_rd_en[4]), // input rd_en + .dout(col_id_out[((4+1)*`COL_ID_BITS)-1:4*`COL_ID_BITS]), + .full(col_id_full[4]), // output full + .empty(col_id_empty[4]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_4 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[4]), // input wr_en + .re(row_id_rd_en[4]), // input rd_en + .dout(row_id_out[((4+1)*`ROW_ID_BITS)-1:4*`ROW_ID_BITS]), + .full(row_id_full[4]), // output full + .empty(row_id_empty[4]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_5 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[5]), // input wr_en + .re(mat_val_rd_en[5]), // input rd_en + .dout(mat_val_out[((5+1)*`MAT_VAL_BITS)-1:5*`MAT_VAL_BITS]), + .full(mat_val_full[5]), // output full + .empty(mat_val_empty[5]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_5 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[5]), // input wr_en + .re(col_id_rd_en[5]), // input rd_en + .dout(col_id_out[((5+1)*`COL_ID_BITS)-1:5*`COL_ID_BITS]), + .full(col_id_full[5]), // output full + .empty(col_id_empty[5]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_5 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[5]), // input wr_en + .re(row_id_rd_en[5]), // input rd_en + .dout(row_id_out[((5+1)*`ROW_ID_BITS)-1:5*`ROW_ID_BITS]), + .full(row_id_full[5]), // output full + .empty(row_id_empty[5]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_6 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[6]), // input wr_en + .re(mat_val_rd_en[6]), // input rd_en + .dout(mat_val_out[((6+1)*`MAT_VAL_BITS)-1:6*`MAT_VAL_BITS]), + .full(mat_val_full[6]), // output full + .empty(mat_val_empty[6]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_6 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[6]), // input wr_en + .re(col_id_rd_en[6]), // input rd_en + .dout(col_id_out[((6+1)*`COL_ID_BITS)-1:6*`COL_ID_BITS]), + .full(col_id_full[6]), // output full + .empty(col_id_empty[6]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_6 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[6]), // input wr_en + .re(row_id_rd_en[6]), // input rd_en + .dout(row_id_out[((6+1)*`ROW_ID_BITS)-1:6*`ROW_ID_BITS]), + .full(row_id_full[6]), // output full + .empty(row_id_empty[6]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_7 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[7]), // input wr_en + .re(mat_val_rd_en[7]), // input rd_en + .dout(mat_val_out[((7+1)*`MAT_VAL_BITS)-1:7*`MAT_VAL_BITS]), + .full(mat_val_full[7]), // output full + .empty(mat_val_empty[7]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_7 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[7]), // input wr_en + .re(col_id_rd_en[7]), // input rd_en + .dout(col_id_out[((7+1)*`COL_ID_BITS)-1:7*`COL_ID_BITS]), + .full(col_id_full[7]), // output full + .empty(col_id_empty[7]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_7 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[7]), // input wr_en + .re(row_id_rd_en[7]), // input rd_en + .dout(row_id_out[((7+1)*`ROW_ID_BITS)-1:7*`ROW_ID_BITS]), + .full(row_id_full[7]), // output full + .empty(row_id_empty[7]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_8 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[8]), // input wr_en + .re(mat_val_rd_en[8]), // input rd_en + .dout(mat_val_out[((8+1)*`MAT_VAL_BITS)-1:8*`MAT_VAL_BITS]), + .full(mat_val_full[8]), // output full + .empty(mat_val_empty[8]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_8 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[8]), // input wr_en + .re(col_id_rd_en[8]), // input rd_en + .dout(col_id_out[((8+1)*`COL_ID_BITS)-1:8*`COL_ID_BITS]), + .full(col_id_full[8]), // output full + .empty(col_id_empty[8]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_8 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[8]), // input wr_en + .re(row_id_rd_en[8]), // input rd_en + .dout(row_id_out[((8+1)*`ROW_ID_BITS)-1:8*`ROW_ID_BITS]), + .full(row_id_full[8]), // output full + .empty(row_id_empty[8]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_9 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[9]), // input wr_en + .re(mat_val_rd_en[9]), // input rd_en + .dout(mat_val_out[((9+1)*`MAT_VAL_BITS)-1:9*`MAT_VAL_BITS]), + .full(mat_val_full[9]), // output full + .empty(mat_val_empty[9]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_9 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[9]), // input wr_en + .re(col_id_rd_en[9]), // input rd_en + .dout(col_id_out[((9+1)*`COL_ID_BITS)-1:9*`COL_ID_BITS]), + .full(col_id_full[9]), // output full + .empty(col_id_empty[9]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_9 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[9]), // input wr_en + .re(row_id_rd_en[9]), // input rd_en + .dout(row_id_out[((9+1)*`ROW_ID_BITS)-1:9*`ROW_ID_BITS]), + .full(row_id_full[9]), // output full + .empty(row_id_empty[9]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_10 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[10]), // input wr_en + .re(mat_val_rd_en[10]), // input rd_en + .dout(mat_val_out[((10+1)*`MAT_VAL_BITS)-1:10*`MAT_VAL_BITS]), + .full(mat_val_full[10]), // output full + .empty(mat_val_empty[10]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_10 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[10]), // input wr_en + .re(col_id_rd_en[10]), // input rd_en + .dout(col_id_out[((10+1)*`COL_ID_BITS)-1:10*`COL_ID_BITS]), + .full(col_id_full[10]), // output full + .empty(col_id_empty[10]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_10 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[10]), // input wr_en + .re(row_id_rd_en[10]), // input rd_en + .dout(row_id_out[((10+1)*`ROW_ID_BITS)-1:10*`ROW_ID_BITS]), + .full(row_id_full[10]), // output full + .empty(row_id_empty[10]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_11 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[11]), // input wr_en + .re(mat_val_rd_en[11]), // input rd_en + .dout(mat_val_out[((11+1)*`MAT_VAL_BITS)-1:11*`MAT_VAL_BITS]), + .full(mat_val_full[11]), // output full + .empty(mat_val_empty[11]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_11 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[11]), // input wr_en + .re(col_id_rd_en[11]), // input rd_en + .dout(col_id_out[((11+1)*`COL_ID_BITS)-1:11*`COL_ID_BITS]), + .full(col_id_full[11]), // output full + .empty(col_id_empty[11]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_11 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[11]), // input wr_en + .re(row_id_rd_en[11]), // input rd_en + .dout(row_id_out[((11+1)*`ROW_ID_BITS)-1:11*`ROW_ID_BITS]), + .full(row_id_full[11]), // output full + .empty(row_id_empty[11]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_12 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[12]), // input wr_en + .re(mat_val_rd_en[12]), // input rd_en + .dout(mat_val_out[((12+1)*`MAT_VAL_BITS)-1:12*`MAT_VAL_BITS]), + .full(mat_val_full[12]), // output full + .empty(mat_val_empty[12]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_12 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[12]), // input wr_en + .re(col_id_rd_en[12]), // input rd_en + .dout(col_id_out[((12+1)*`COL_ID_BITS)-1:12*`COL_ID_BITS]), + .full(col_id_full[12]), // output full + .empty(col_id_empty[12]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_12 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[12]), // input wr_en + .re(row_id_rd_en[12]), // input rd_en + .dout(row_id_out[((12+1)*`ROW_ID_BITS)-1:12*`ROW_ID_BITS]), + .full(row_id_full[12]), // output full + .empty(row_id_empty[12]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_13 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[13]), // input wr_en + .re(mat_val_rd_en[13]), // input rd_en + .dout(mat_val_out[((13+1)*`MAT_VAL_BITS)-1:13*`MAT_VAL_BITS]), + .full(mat_val_full[13]), // output full + .empty(mat_val_empty[13]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_13 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[13]), // input wr_en + .re(col_id_rd_en[13]), // input rd_en + .dout(col_id_out[((13+1)*`COL_ID_BITS)-1:13*`COL_ID_BITS]), + .full(col_id_full[13]), // output full + .empty(col_id_empty[13]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_13 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[13]), // input wr_en + .re(row_id_rd_en[13]), // input rd_en + .dout(row_id_out[((13+1)*`ROW_ID_BITS)-1:13*`ROW_ID_BITS]), + .full(row_id_full[13]), // output full + .empty(row_id_empty[13]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_14 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[14]), // input wr_en + .re(mat_val_rd_en[14]), // input rd_en + .dout(mat_val_out[((14+1)*`MAT_VAL_BITS)-1:14*`MAT_VAL_BITS]), + .full(mat_val_full[14]), // output full + .empty(mat_val_empty[14]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_14 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[14]), // input wr_en + .re(col_id_rd_en[14]), // input rd_en + .dout(col_id_out[((14+1)*`COL_ID_BITS)-1:14*`COL_ID_BITS]), + .full(col_id_full[14]), // output full + .empty(col_id_empty[14]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_14 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[14]), // input wr_en + .re(row_id_rd_en[14]), // input rd_en + .dout(row_id_out[((14+1)*`ROW_ID_BITS)-1:14*`ROW_ID_BITS]), + .full(row_id_full[14]), // output full + .empty(row_id_empty[14]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_15 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[15]), // input wr_en + .re(mat_val_rd_en[15]), // input rd_en + .dout(mat_val_out[((15+1)*`MAT_VAL_BITS)-1:15*`MAT_VAL_BITS]), + .full(mat_val_full[15]), // output full + .empty(mat_val_empty[15]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_15 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[15]), // input wr_en + .re(col_id_rd_en[15]), // input rd_en + .dout(col_id_out[((15+1)*`COL_ID_BITS)-1:15*`COL_ID_BITS]), + .full(col_id_full[15]), // output full + .empty(col_id_empty[15]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_15 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[15]), // input wr_en + .re(row_id_rd_en[15]), // input rd_en + .dout(row_id_out[((15+1)*`ROW_ID_BITS)-1:15*`ROW_ID_BITS]), + .full(row_id_full[15]), // output full + .empty(row_id_empty[15]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_16 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[16]), // input wr_en + .re(mat_val_rd_en[16]), // input rd_en + .dout(mat_val_out[((16+1)*`MAT_VAL_BITS)-1:16*`MAT_VAL_BITS]), + .full(mat_val_full[16]), // output full + .empty(mat_val_empty[16]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_16 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[16]), // input wr_en + .re(col_id_rd_en[16]), // input rd_en + .dout(col_id_out[((16+1)*`COL_ID_BITS)-1:16*`COL_ID_BITS]), + .full(col_id_full[16]), // output full + .empty(col_id_empty[16]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_16 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[16]), // input wr_en + .re(row_id_rd_en[16]), // input rd_en + .dout(row_id_out[((16+1)*`ROW_ID_BITS)-1:16*`ROW_ID_BITS]), + .full(row_id_full[16]), // output full + .empty(row_id_empty[16]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_17 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[17]), // input wr_en + .re(mat_val_rd_en[17]), // input rd_en + .dout(mat_val_out[((17+1)*`MAT_VAL_BITS)-1:17*`MAT_VAL_BITS]), + .full(mat_val_full[17]), // output full + .empty(mat_val_empty[17]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_17 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[17]), // input wr_en + .re(col_id_rd_en[17]), // input rd_en + .dout(col_id_out[((17+1)*`COL_ID_BITS)-1:17*`COL_ID_BITS]), + .full(col_id_full[17]), // output full + .empty(col_id_empty[17]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_17 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[17]), // input wr_en + .re(row_id_rd_en[17]), // input rd_en + .dout(row_id_out[((17+1)*`ROW_ID_BITS)-1:17*`ROW_ID_BITS]), + .full(row_id_full[17]), // output full + .empty(row_id_empty[17]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_18 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[18]), // input wr_en + .re(mat_val_rd_en[18]), // input rd_en + .dout(mat_val_out[((18+1)*`MAT_VAL_BITS)-1:18*`MAT_VAL_BITS]), + .full(mat_val_full[18]), // output full + .empty(mat_val_empty[18]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_18 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[18]), // input wr_en + .re(col_id_rd_en[18]), // input rd_en + .dout(col_id_out[((18+1)*`COL_ID_BITS)-1:18*`COL_ID_BITS]), + .full(col_id_full[18]), // output full + .empty(col_id_empty[18]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_18 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[18]), // input wr_en + .re(row_id_rd_en[18]), // input rd_en + .dout(row_id_out[((18+1)*`ROW_ID_BITS)-1:18*`ROW_ID_BITS]), + .full(row_id_full[18]), // output full + .empty(row_id_empty[18]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_19 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[19]), // input wr_en + .re(mat_val_rd_en[19]), // input rd_en + .dout(mat_val_out[((19+1)*`MAT_VAL_BITS)-1:19*`MAT_VAL_BITS]), + .full(mat_val_full[19]), // output full + .empty(mat_val_empty[19]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_19 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[19]), // input wr_en + .re(col_id_rd_en[19]), // input rd_en + .dout(col_id_out[((19+1)*`COL_ID_BITS)-1:19*`COL_ID_BITS]), + .full(col_id_full[19]), // output full + .empty(col_id_empty[19]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_19 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[19]), // input wr_en + .re(row_id_rd_en[19]), // input rd_en + .dout(row_id_out[((19+1)*`ROW_ID_BITS)-1:19*`ROW_ID_BITS]), + .full(row_id_full[19]), // output full + .empty(row_id_empty[19]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_20 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[20]), // input wr_en + .re(mat_val_rd_en[20]), // input rd_en + .dout(mat_val_out[((20+1)*`MAT_VAL_BITS)-1:20*`MAT_VAL_BITS]), + .full(mat_val_full[20]), // output full + .empty(mat_val_empty[20]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_20 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[20]), // input wr_en + .re(col_id_rd_en[20]), // input rd_en + .dout(col_id_out[((20+1)*`COL_ID_BITS)-1:20*`COL_ID_BITS]), + .full(col_id_full[20]), // output full + .empty(col_id_empty[20]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_20 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[20]), // input wr_en + .re(row_id_rd_en[20]), // input rd_en + .dout(row_id_out[((20+1)*`ROW_ID_BITS)-1:20*`ROW_ID_BITS]), + .full(row_id_full[20]), // output full + .empty(row_id_empty[20]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_21 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[21]), // input wr_en + .re(mat_val_rd_en[21]), // input rd_en + .dout(mat_val_out[((21+1)*`MAT_VAL_BITS)-1:21*`MAT_VAL_BITS]), + .full(mat_val_full[21]), // output full + .empty(mat_val_empty[21]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_21 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[21]), // input wr_en + .re(col_id_rd_en[21]), // input rd_en + .dout(col_id_out[((21+1)*`COL_ID_BITS)-1:21*`COL_ID_BITS]), + .full(col_id_full[21]), // output full + .empty(col_id_empty[21]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_21 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[21]), // input wr_en + .re(row_id_rd_en[21]), // input rd_en + .dout(row_id_out[((21+1)*`ROW_ID_BITS)-1:21*`ROW_ID_BITS]), + .full(row_id_full[21]), // output full + .empty(row_id_empty[21]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_22 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[22]), // input wr_en + .re(mat_val_rd_en[22]), // input rd_en + .dout(mat_val_out[((22+1)*`MAT_VAL_BITS)-1:22*`MAT_VAL_BITS]), + .full(mat_val_full[22]), // output full + .empty(mat_val_empty[22]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_22 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[22]), // input wr_en + .re(col_id_rd_en[22]), // input rd_en + .dout(col_id_out[((22+1)*`COL_ID_BITS)-1:22*`COL_ID_BITS]), + .full(col_id_full[22]), // output full + .empty(col_id_empty[22]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_22 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[22]), // input wr_en + .re(row_id_rd_en[22]), // input rd_en + .dout(row_id_out[((22+1)*`ROW_ID_BITS)-1:22*`ROW_ID_BITS]), + .full(row_id_full[22]), // output full + .empty(row_id_empty[22]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_23 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[23]), // input wr_en + .re(mat_val_rd_en[23]), // input rd_en + .dout(mat_val_out[((23+1)*`MAT_VAL_BITS)-1:23*`MAT_VAL_BITS]), + .full(mat_val_full[23]), // output full + .empty(mat_val_empty[23]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_23 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[23]), // input wr_en + .re(col_id_rd_en[23]), // input rd_en + .dout(col_id_out[((23+1)*`COL_ID_BITS)-1:23*`COL_ID_BITS]), + .full(col_id_full[23]), // output full + .empty(col_id_empty[23]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_23 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[23]), // input wr_en + .re(row_id_rd_en[23]), // input rd_en + .dout(row_id_out[((23+1)*`ROW_ID_BITS)-1:23*`ROW_ID_BITS]), + .full(row_id_full[23]), // output full + .empty(row_id_empty[23]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_24 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[24]), // input wr_en + .re(mat_val_rd_en[24]), // input rd_en + .dout(mat_val_out[((24+1)*`MAT_VAL_BITS)-1:24*`MAT_VAL_BITS]), + .full(mat_val_full[24]), // output full + .empty(mat_val_empty[24]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_24 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[24]), // input wr_en + .re(col_id_rd_en[24]), // input rd_en + .dout(col_id_out[((24+1)*`COL_ID_BITS)-1:24*`COL_ID_BITS]), + .full(col_id_full[24]), // output full + .empty(col_id_empty[24]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_24 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[24]), // input wr_en + .re(row_id_rd_en[24]), // input rd_en + .dout(row_id_out[((24+1)*`ROW_ID_BITS)-1:24*`ROW_ID_BITS]), + .full(row_id_full[24]), // output full + .empty(row_id_empty[24]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_25 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[25]), // input wr_en + .re(mat_val_rd_en[25]), // input rd_en + .dout(mat_val_out[((25+1)*`MAT_VAL_BITS)-1:25*`MAT_VAL_BITS]), + .full(mat_val_full[25]), // output full + .empty(mat_val_empty[25]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_25 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[25]), // input wr_en + .re(col_id_rd_en[25]), // input rd_en + .dout(col_id_out[((25+1)*`COL_ID_BITS)-1:25*`COL_ID_BITS]), + .full(col_id_full[25]), // output full + .empty(col_id_empty[25]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_25 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[25]), // input wr_en + .re(row_id_rd_en[25]), // input rd_en + .dout(row_id_out[((25+1)*`ROW_ID_BITS)-1:25*`ROW_ID_BITS]), + .full(row_id_full[25]), // output full + .empty(row_id_empty[25]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_26 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[26]), // input wr_en + .re(mat_val_rd_en[26]), // input rd_en + .dout(mat_val_out[((26+1)*`MAT_VAL_BITS)-1:26*`MAT_VAL_BITS]), + .full(mat_val_full[26]), // output full + .empty(mat_val_empty[26]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_26 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[26]), // input wr_en + .re(col_id_rd_en[26]), // input rd_en + .dout(col_id_out[((26+1)*`COL_ID_BITS)-1:26*`COL_ID_BITS]), + .full(col_id_full[26]), // output full + .empty(col_id_empty[26]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_26 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[26]), // input wr_en + .re(row_id_rd_en[26]), // input rd_en + .dout(row_id_out[((26+1)*`ROW_ID_BITS)-1:26*`ROW_ID_BITS]), + .full(row_id_full[26]), // output full + .empty(row_id_empty[26]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_27 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[27]), // input wr_en + .re(mat_val_rd_en[27]), // input rd_en + .dout(mat_val_out[((27+1)*`MAT_VAL_BITS)-1:27*`MAT_VAL_BITS]), + .full(mat_val_full[27]), // output full + .empty(mat_val_empty[27]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_27 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[27]), // input wr_en + .re(col_id_rd_en[27]), // input rd_en + .dout(col_id_out[((27+1)*`COL_ID_BITS)-1:27*`COL_ID_BITS]), + .full(col_id_full[27]), // output full + .empty(col_id_empty[27]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_27 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[27]), // input wr_en + .re(row_id_rd_en[27]), // input rd_en + .dout(row_id_out[((27+1)*`ROW_ID_BITS)-1:27*`ROW_ID_BITS]), + .full(row_id_full[27]), // output full + .empty(row_id_empty[27]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_28 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[28]), // input wr_en + .re(mat_val_rd_en[28]), // input rd_en + .dout(mat_val_out[((28+1)*`MAT_VAL_BITS)-1:28*`MAT_VAL_BITS]), + .full(mat_val_full[28]), // output full + .empty(mat_val_empty[28]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_28 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[28]), // input wr_en + .re(col_id_rd_en[28]), // input rd_en + .dout(col_id_out[((28+1)*`COL_ID_BITS)-1:28*`COL_ID_BITS]), + .full(col_id_full[28]), // output full + .empty(col_id_empty[28]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_28 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[28]), // input wr_en + .re(row_id_rd_en[28]), // input rd_en + .dout(row_id_out[((28+1)*`ROW_ID_BITS)-1:28*`ROW_ID_BITS]), + .full(row_id_full[28]), // output full + .empty(row_id_empty[28]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_29 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[29]), // input wr_en + .re(mat_val_rd_en[29]), // input rd_en + .dout(mat_val_out[((29+1)*`MAT_VAL_BITS)-1:29*`MAT_VAL_BITS]), + .full(mat_val_full[29]), // output full + .empty(mat_val_empty[29]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_29 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[29]), // input wr_en + .re(col_id_rd_en[29]), // input rd_en + .dout(col_id_out[((29+1)*`COL_ID_BITS)-1:29*`COL_ID_BITS]), + .full(col_id_full[29]), // output full + .empty(col_id_empty[29]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_29 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[29]), // input wr_en + .re(row_id_rd_en[29]), // input rd_en + .dout(row_id_out[((29+1)*`ROW_ID_BITS)-1:29*`ROW_ID_BITS]), + .full(row_id_full[29]), // output full + .empty(row_id_empty[29]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_30 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[30]), // input wr_en + .re(mat_val_rd_en[30]), // input rd_en + .dout(mat_val_out[((30+1)*`MAT_VAL_BITS)-1:30*`MAT_VAL_BITS]), + .full(mat_val_full[30]), // output full + .empty(mat_val_empty[30]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_30 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[30]), // input wr_en + .re(col_id_rd_en[30]), // input rd_en + .dout(col_id_out[((30+1)*`COL_ID_BITS)-1:30*`COL_ID_BITS]), + .full(col_id_full[30]), // output full + .empty(col_id_empty[30]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_30 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[30]), // input wr_en + .re(row_id_rd_en[30]), // input rd_en + .dout(row_id_out[((30+1)*`ROW_ID_BITS)-1:30*`ROW_ID_BITS]), + .full(row_id_full[30]), // output full + .empty(row_id_empty[30]) // output empty + ); + + generic_fifo_sc_a #( + .dw(MAT_VAL_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_mat_val_31 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(mat_val_dout), + .we(mat_val_wr_en[31]), // input wr_en + .re(mat_val_rd_en[31]), // input rd_en + .dout(mat_val_out[((31+1)*`MAT_VAL_BITS)-1:31*`MAT_VAL_BITS]), + .full(mat_val_full[31]), // output full + .empty(mat_val_empty[31]) // output empty + ); + + generic_fifo_sc_a #( + .dw(COL_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_col_id_31 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(col_id_dout), + .we(col_id_wr_en[31]), // input wr_en + .re(col_id_rd_en[31]), // input rd_en + .dout(col_id_out[((31+1)*`COL_ID_BITS)-1:31*`COL_ID_BITS]), + .full(col_id_full[31]), // output full + .empty(col_id_empty[31]) // output empty + ); + + generic_fifo_sc_a #( + .dw(ROW_ID_ROM_DWIDTH), + .aw(FIFO_DEPTH_BITS) + ) fifo_row_id_31 ( + .clk(clk), // input clk + .rst(rst), // input clk + .clr(1'b0), + .din(row_id_dout), + .we(row_id_wr_en[31]), // input wr_en + .re(row_id_rd_en[31]), // input rd_en + .dout(row_id_out[((31+1)*`ROW_ID_BITS)-1:31*`ROW_ID_BITS]), + .full(row_id_full[31]), // output full + .empty(row_id_empty[31]) // output empty + ); + + //TODO: done signal check for matrix values only. Should check for all three. Use 3 done signals and the final done is the and of all three. + assign done = (counter >=`NUM_MAT_VALS); + + assign mat_val_full_shifted = mat_val_full>>mat_val_lane; + assign col_id_full_shifted = col_id_full>>col_id_lane; + assign row_id_full_shifted = row_id_full>>row_id_lane; + + always @ (posedge clk) begin + if (rst) begin + mat_val_addr <= 0; + col_id_addr <= 0; + row_id_addr <= 0; + + mat_val_wr_en <= 0; + col_id_wr_en <= 0; + row_id_wr_en <= 0; + + mat_val_lane <= 0; + col_id_lane <= 0; + row_id_lane <= 0; + + counter <= 0; + end + else begin + if(!done) begin + // Write matrix value into its FIFO + if (!mat_val_full_shifted[0]) begin + mat_val_wr_en <= (({`NUM_CHANNEL{1'b0}}) | (1<> counter; + assign val_full_shifted = val_full >> counter; + assign id_rd_en_local = (start & (~id_empty_shifted) & (~val_full_shifted)); + assign id_rd_en = id_rd_en_local << counter; + + always @ (posedge clk) begin + if (rst) begin + counter <= 0; + counter_delay <= 0; + end + else if (start) begin + counter <= counter + 1; + counter_delay <= counter; + id_rd_en_local_reg <= id_rd_en_local; + val_wr_en <= id_rd_en_local_reg << counter_delay; + rd_addr <= id >> (counter*`COL_ID_BITS); + end + end +endmodule + +module Big_Channel( + input clk, + input rst, + input start, + input fetcher_done, + + input [`MAT_VAL_BITS * `NUM_CHANNEL -1 :0] mat_val, + input [`NUM_CHANNEL - 1 : 0] mat_val_empty, + output [`NUM_CHANNEL - 1 : 0] mat_val_rd_en, + + input [`VEC_VAL_BITS * `NUM_CHANNEL - 1 : 0] vec_val, + input [`NUM_CHANNEL-1:0] vec_val_empty, + output [`NUM_CHANNEL-1:0] vec_val_rd_en, + + input [`ROW_ID_BITS * `NUM_CHANNEL -1:0] row_id, + input [`NUM_CHANNEL-1:0] row_id_empty, + output [`NUM_CHANNEL-1:0] row_id_rd_en, + + output [`MULT_BITS * `NUM_CHANNEL -1:0] data_out, + output [`NUM_CHANNEL-1:0] data_out_empty, + output [`ROW_ID_BITS * `NUM_CHANNEL -1:0] addr_out, + input [`NUM_CHANNEL-1:0] out_rd_en, + + output [`NUM_CHANNEL-1:0] done +); + + Channel_Accumulator CH_0 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(0+1)*`MAT_VAL_BITS-1:0*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[0]), + .mat_val_rd_en(mat_val_rd_en[0]), + .vec_val(vec_val[(0+1)*`VEC_VAL_BITS-1:0*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[0]), + .vec_val_rd_en(vec_val_rd_en[0]), + .row_id(row_id[(0+1)*`ROW_ID_BITS-1:0*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[0]), + .row_id_rd_en(row_id_rd_en[0]), + .data_out(data_out[(0+1)*`MULT_BITS-1:0*`MULT_BITS]), + .data_out_empty(data_out_empty[0]), + .addr_out(addr_out[(0+1)*`ROW_ID_BITS-1:0*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[0]), + .done(done[0]) + ); + + Channel_Accumulator CH_1 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(1+1)*`MAT_VAL_BITS-1:1*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[1]), + .mat_val_rd_en(mat_val_rd_en[1]), + .vec_val(vec_val[(1+1)*`VEC_VAL_BITS-1:1*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[1]), + .vec_val_rd_en(vec_val_rd_en[1]), + .row_id(row_id[(1+1)*`ROW_ID_BITS-1:1*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[1]), + .row_id_rd_en(row_id_rd_en[1]), + .data_out(data_out[(1+1)*`MULT_BITS-1:1*`MULT_BITS]), + .data_out_empty(data_out_empty[1]), + .addr_out(addr_out[(1+1)*`ROW_ID_BITS-1:1*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[1]), + .done(done[1]) + ); + + Channel_Accumulator CH_2 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(2+1)*`MAT_VAL_BITS-1:2*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[2]), + .mat_val_rd_en(mat_val_rd_en[2]), + .vec_val(vec_val[(2+1)*`VEC_VAL_BITS-1:2*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[2]), + .vec_val_rd_en(vec_val_rd_en[2]), + .row_id(row_id[(2+1)*`ROW_ID_BITS-1:2*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[2]), + .row_id_rd_en(row_id_rd_en[2]), + .data_out(data_out[(2+1)*`MULT_BITS-1:2*`MULT_BITS]), + .data_out_empty(data_out_empty[2]), + .addr_out(addr_out[(2+1)*`ROW_ID_BITS-1:2*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[2]), + .done(done[2]) + ); + + Channel_Accumulator CH_3 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(3+1)*`MAT_VAL_BITS-1:3*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[3]), + .mat_val_rd_en(mat_val_rd_en[3]), + .vec_val(vec_val[(3+1)*`VEC_VAL_BITS-1:3*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[3]), + .vec_val_rd_en(vec_val_rd_en[3]), + .row_id(row_id[(3+1)*`ROW_ID_BITS-1:3*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[3]), + .row_id_rd_en(row_id_rd_en[3]), + .data_out(data_out[(3+1)*`MULT_BITS-1:3*`MULT_BITS]), + .data_out_empty(data_out_empty[3]), + .addr_out(addr_out[(3+1)*`ROW_ID_BITS-1:3*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[3]), + .done(done[3]) + ); + + Channel_Accumulator CH_4 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(4+1)*`MAT_VAL_BITS-1:4*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[4]), + .mat_val_rd_en(mat_val_rd_en[4]), + .vec_val(vec_val[(4+1)*`VEC_VAL_BITS-1:4*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[4]), + .vec_val_rd_en(vec_val_rd_en[4]), + .row_id(row_id[(4+1)*`ROW_ID_BITS-1:4*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[4]), + .row_id_rd_en(row_id_rd_en[4]), + .data_out(data_out[(4+1)*`MULT_BITS-1:4*`MULT_BITS]), + .data_out_empty(data_out_empty[4]), + .addr_out(addr_out[(4+1)*`ROW_ID_BITS-1:4*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[4]), + .done(done[4]) + ); + + Channel_Accumulator CH_5 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(5+1)*`MAT_VAL_BITS-1:5*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[5]), + .mat_val_rd_en(mat_val_rd_en[5]), + .vec_val(vec_val[(5+1)*`VEC_VAL_BITS-1:5*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[5]), + .vec_val_rd_en(vec_val_rd_en[5]), + .row_id(row_id[(5+1)*`ROW_ID_BITS-1:5*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[5]), + .row_id_rd_en(row_id_rd_en[5]), + .data_out(data_out[(5+1)*`MULT_BITS-1:5*`MULT_BITS]), + .data_out_empty(data_out_empty[5]), + .addr_out(addr_out[(5+1)*`ROW_ID_BITS-1:5*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[5]), + .done(done[5]) + ); + + Channel_Accumulator CH_6 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(6+1)*`MAT_VAL_BITS-1:6*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[6]), + .mat_val_rd_en(mat_val_rd_en[6]), + .vec_val(vec_val[(6+1)*`VEC_VAL_BITS-1:6*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[6]), + .vec_val_rd_en(vec_val_rd_en[6]), + .row_id(row_id[(6+1)*`ROW_ID_BITS-1:6*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[6]), + .row_id_rd_en(row_id_rd_en[6]), + .data_out(data_out[(6+1)*`MULT_BITS-1:6*`MULT_BITS]), + .data_out_empty(data_out_empty[6]), + .addr_out(addr_out[(6+1)*`ROW_ID_BITS-1:6*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[6]), + .done(done[6]) + ); + + Channel_Accumulator CH_7 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(7+1)*`MAT_VAL_BITS-1:7*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[7]), + .mat_val_rd_en(mat_val_rd_en[7]), + .vec_val(vec_val[(7+1)*`VEC_VAL_BITS-1:7*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[7]), + .vec_val_rd_en(vec_val_rd_en[7]), + .row_id(row_id[(7+1)*`ROW_ID_BITS-1:7*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[7]), + .row_id_rd_en(row_id_rd_en[7]), + .data_out(data_out[(7+1)*`MULT_BITS-1:7*`MULT_BITS]), + .data_out_empty(data_out_empty[7]), + .addr_out(addr_out[(7+1)*`ROW_ID_BITS-1:7*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[7]), + .done(done[7]) + ); + + Channel_Accumulator CH_8 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(8+1)*`MAT_VAL_BITS-1:8*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[8]), + .mat_val_rd_en(mat_val_rd_en[8]), + .vec_val(vec_val[(8+1)*`VEC_VAL_BITS-1:8*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[8]), + .vec_val_rd_en(vec_val_rd_en[8]), + .row_id(row_id[(8+1)*`ROW_ID_BITS-1:8*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[8]), + .row_id_rd_en(row_id_rd_en[8]), + .data_out(data_out[(8+1)*`MULT_BITS-1:8*`MULT_BITS]), + .data_out_empty(data_out_empty[8]), + .addr_out(addr_out[(8+1)*`ROW_ID_BITS-1:8*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[8]), + .done(done[8]) + ); + + Channel_Accumulator CH_9 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(9+1)*`MAT_VAL_BITS-1:9*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[9]), + .mat_val_rd_en(mat_val_rd_en[9]), + .vec_val(vec_val[(9+1)*`VEC_VAL_BITS-1:9*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[9]), + .vec_val_rd_en(vec_val_rd_en[9]), + .row_id(row_id[(9+1)*`ROW_ID_BITS-1:9*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[9]), + .row_id_rd_en(row_id_rd_en[9]), + .data_out(data_out[(9+1)*`MULT_BITS-1:9*`MULT_BITS]), + .data_out_empty(data_out_empty[9]), + .addr_out(addr_out[(9+1)*`ROW_ID_BITS-1:9*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[9]), + .done(done[9]) + ); + + Channel_Accumulator CH_10 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(10+1)*`MAT_VAL_BITS-1:10*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[10]), + .mat_val_rd_en(mat_val_rd_en[10]), + .vec_val(vec_val[(10+1)*`VEC_VAL_BITS-1:10*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[10]), + .vec_val_rd_en(vec_val_rd_en[10]), + .row_id(row_id[(10+1)*`ROW_ID_BITS-1:10*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[10]), + .row_id_rd_en(row_id_rd_en[10]), + .data_out(data_out[(10+1)*`MULT_BITS-1:10*`MULT_BITS]), + .data_out_empty(data_out_empty[10]), + .addr_out(addr_out[(10+1)*`ROW_ID_BITS-1:10*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[10]), + .done(done[10]) + ); + + Channel_Accumulator CH_11 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(11+1)*`MAT_VAL_BITS-1:11*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[11]), + .mat_val_rd_en(mat_val_rd_en[11]), + .vec_val(vec_val[(11+1)*`VEC_VAL_BITS-1:11*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[11]), + .vec_val_rd_en(vec_val_rd_en[11]), + .row_id(row_id[(11+1)*`ROW_ID_BITS-1:11*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[11]), + .row_id_rd_en(row_id_rd_en[11]), + .data_out(data_out[(11+1)*`MULT_BITS-1:11*`MULT_BITS]), + .data_out_empty(data_out_empty[11]), + .addr_out(addr_out[(11+1)*`ROW_ID_BITS-1:11*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[11]), + .done(done[11]) + ); + + Channel_Accumulator CH_12 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(12+1)*`MAT_VAL_BITS-1:12*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[12]), + .mat_val_rd_en(mat_val_rd_en[12]), + .vec_val(vec_val[(12+1)*`VEC_VAL_BITS-1:12*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[12]), + .vec_val_rd_en(vec_val_rd_en[12]), + .row_id(row_id[(12+1)*`ROW_ID_BITS-1:12*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[12]), + .row_id_rd_en(row_id_rd_en[12]), + .data_out(data_out[(12+1)*`MULT_BITS-1:12*`MULT_BITS]), + .data_out_empty(data_out_empty[12]), + .addr_out(addr_out[(12+1)*`ROW_ID_BITS-1:12*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[12]), + .done(done[12]) + ); + + Channel_Accumulator CH_13 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(13+1)*`MAT_VAL_BITS-1:13*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[13]), + .mat_val_rd_en(mat_val_rd_en[13]), + .vec_val(vec_val[(13+1)*`VEC_VAL_BITS-1:13*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[13]), + .vec_val_rd_en(vec_val_rd_en[13]), + .row_id(row_id[(13+1)*`ROW_ID_BITS-1:13*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[13]), + .row_id_rd_en(row_id_rd_en[13]), + .data_out(data_out[(13+1)*`MULT_BITS-1:13*`MULT_BITS]), + .data_out_empty(data_out_empty[13]), + .addr_out(addr_out[(13+1)*`ROW_ID_BITS-1:13*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[13]), + .done(done[13]) + ); + + Channel_Accumulator CH_14 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(14+1)*`MAT_VAL_BITS-1:14*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[14]), + .mat_val_rd_en(mat_val_rd_en[14]), + .vec_val(vec_val[(14+1)*`VEC_VAL_BITS-1:14*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[14]), + .vec_val_rd_en(vec_val_rd_en[14]), + .row_id(row_id[(14+1)*`ROW_ID_BITS-1:14*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[14]), + .row_id_rd_en(row_id_rd_en[14]), + .data_out(data_out[(14+1)*`MULT_BITS-1:14*`MULT_BITS]), + .data_out_empty(data_out_empty[14]), + .addr_out(addr_out[(14+1)*`ROW_ID_BITS-1:14*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[14]), + .done(done[14]) + ); + + Channel_Accumulator CH_15 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(15+1)*`MAT_VAL_BITS-1:15*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[15]), + .mat_val_rd_en(mat_val_rd_en[15]), + .vec_val(vec_val[(15+1)*`VEC_VAL_BITS-1:15*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[15]), + .vec_val_rd_en(vec_val_rd_en[15]), + .row_id(row_id[(15+1)*`ROW_ID_BITS-1:15*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[15]), + .row_id_rd_en(row_id_rd_en[15]), + .data_out(data_out[(15+1)*`MULT_BITS-1:15*`MULT_BITS]), + .data_out_empty(data_out_empty[15]), + .addr_out(addr_out[(15+1)*`ROW_ID_BITS-1:15*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[15]), + .done(done[15]) + ); + + Channel_Accumulator CH_16 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(16+1)*`MAT_VAL_BITS-1:16*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[16]), + .mat_val_rd_en(mat_val_rd_en[16]), + .vec_val(vec_val[(16+1)*`VEC_VAL_BITS-1:16*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[16]), + .vec_val_rd_en(vec_val_rd_en[16]), + .row_id(row_id[(16+1)*`ROW_ID_BITS-1:16*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[16]), + .row_id_rd_en(row_id_rd_en[16]), + .data_out(data_out[(16+1)*`MULT_BITS-1:16*`MULT_BITS]), + .data_out_empty(data_out_empty[16]), + .addr_out(addr_out[(16+1)*`ROW_ID_BITS-1:16*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[16]), + .done(done[16]) + ); + + Channel_Accumulator CH_17 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(17+1)*`MAT_VAL_BITS-1:17*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[17]), + .mat_val_rd_en(mat_val_rd_en[17]), + .vec_val(vec_val[(17+1)*`VEC_VAL_BITS-1:17*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[17]), + .vec_val_rd_en(vec_val_rd_en[17]), + .row_id(row_id[(17+1)*`ROW_ID_BITS-1:17*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[17]), + .row_id_rd_en(row_id_rd_en[17]), + .data_out(data_out[(17+1)*`MULT_BITS-1:17*`MULT_BITS]), + .data_out_empty(data_out_empty[17]), + .addr_out(addr_out[(17+1)*`ROW_ID_BITS-1:17*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[17]), + .done(done[17]) + ); + + Channel_Accumulator CH_18 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(18+1)*`MAT_VAL_BITS-1:18*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[18]), + .mat_val_rd_en(mat_val_rd_en[18]), + .vec_val(vec_val[(18+1)*`VEC_VAL_BITS-1:18*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[18]), + .vec_val_rd_en(vec_val_rd_en[18]), + .row_id(row_id[(18+1)*`ROW_ID_BITS-1:18*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[18]), + .row_id_rd_en(row_id_rd_en[18]), + .data_out(data_out[(18+1)*`MULT_BITS-1:18*`MULT_BITS]), + .data_out_empty(data_out_empty[18]), + .addr_out(addr_out[(18+1)*`ROW_ID_BITS-1:18*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[18]), + .done(done[18]) + ); + + Channel_Accumulator CH_19 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(19+1)*`MAT_VAL_BITS-1:19*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[19]), + .mat_val_rd_en(mat_val_rd_en[19]), + .vec_val(vec_val[(19+1)*`VEC_VAL_BITS-1:19*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[19]), + .vec_val_rd_en(vec_val_rd_en[19]), + .row_id(row_id[(19+1)*`ROW_ID_BITS-1:19*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[19]), + .row_id_rd_en(row_id_rd_en[19]), + .data_out(data_out[(19+1)*`MULT_BITS-1:19*`MULT_BITS]), + .data_out_empty(data_out_empty[19]), + .addr_out(addr_out[(19+1)*`ROW_ID_BITS-1:19*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[19]), + .done(done[19]) + ); + + Channel_Accumulator CH_20 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(20+1)*`MAT_VAL_BITS-1:20*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[20]), + .mat_val_rd_en(mat_val_rd_en[20]), + .vec_val(vec_val[(20+1)*`VEC_VAL_BITS-1:20*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[20]), + .vec_val_rd_en(vec_val_rd_en[20]), + .row_id(row_id[(20+1)*`ROW_ID_BITS-1:20*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[20]), + .row_id_rd_en(row_id_rd_en[20]), + .data_out(data_out[(20+1)*`MULT_BITS-1:20*`MULT_BITS]), + .data_out_empty(data_out_empty[20]), + .addr_out(addr_out[(20+1)*`ROW_ID_BITS-1:20*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[20]), + .done(done[20]) + ); + + Channel_Accumulator CH_21 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(21+1)*`MAT_VAL_BITS-1:21*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[21]), + .mat_val_rd_en(mat_val_rd_en[21]), + .vec_val(vec_val[(21+1)*`VEC_VAL_BITS-1:21*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[21]), + .vec_val_rd_en(vec_val_rd_en[21]), + .row_id(row_id[(21+1)*`ROW_ID_BITS-1:21*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[21]), + .row_id_rd_en(row_id_rd_en[21]), + .data_out(data_out[(21+1)*`MULT_BITS-1:21*`MULT_BITS]), + .data_out_empty(data_out_empty[21]), + .addr_out(addr_out[(21+1)*`ROW_ID_BITS-1:21*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[21]), + .done(done[21]) + ); + + Channel_Accumulator CH_22 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(22+1)*`MAT_VAL_BITS-1:22*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[22]), + .mat_val_rd_en(mat_val_rd_en[22]), + .vec_val(vec_val[(22+1)*`VEC_VAL_BITS-1:22*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[22]), + .vec_val_rd_en(vec_val_rd_en[22]), + .row_id(row_id[(22+1)*`ROW_ID_BITS-1:22*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[22]), + .row_id_rd_en(row_id_rd_en[22]), + .data_out(data_out[(22+1)*`MULT_BITS-1:22*`MULT_BITS]), + .data_out_empty(data_out_empty[22]), + .addr_out(addr_out[(22+1)*`ROW_ID_BITS-1:22*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[22]), + .done(done[22]) + ); + + Channel_Accumulator CH_23 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(23+1)*`MAT_VAL_BITS-1:23*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[23]), + .mat_val_rd_en(mat_val_rd_en[23]), + .vec_val(vec_val[(23+1)*`VEC_VAL_BITS-1:23*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[23]), + .vec_val_rd_en(vec_val_rd_en[23]), + .row_id(row_id[(23+1)*`ROW_ID_BITS-1:23*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[23]), + .row_id_rd_en(row_id_rd_en[23]), + .data_out(data_out[(23+1)*`MULT_BITS-1:23*`MULT_BITS]), + .data_out_empty(data_out_empty[23]), + .addr_out(addr_out[(23+1)*`ROW_ID_BITS-1:23*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[23]), + .done(done[23]) + ); + + Channel_Accumulator CH_24 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(24+1)*`MAT_VAL_BITS-1:24*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[24]), + .mat_val_rd_en(mat_val_rd_en[24]), + .vec_val(vec_val[(24+1)*`VEC_VAL_BITS-1:24*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[24]), + .vec_val_rd_en(vec_val_rd_en[24]), + .row_id(row_id[(24+1)*`ROW_ID_BITS-1:24*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[24]), + .row_id_rd_en(row_id_rd_en[24]), + .data_out(data_out[(24+1)*`MULT_BITS-1:24*`MULT_BITS]), + .data_out_empty(data_out_empty[24]), + .addr_out(addr_out[(24+1)*`ROW_ID_BITS-1:24*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[24]), + .done(done[24]) + ); + + Channel_Accumulator CH_25 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(25+1)*`MAT_VAL_BITS-1:25*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[25]), + .mat_val_rd_en(mat_val_rd_en[25]), + .vec_val(vec_val[(25+1)*`VEC_VAL_BITS-1:25*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[25]), + .vec_val_rd_en(vec_val_rd_en[25]), + .row_id(row_id[(25+1)*`ROW_ID_BITS-1:25*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[25]), + .row_id_rd_en(row_id_rd_en[25]), + .data_out(data_out[(25+1)*`MULT_BITS-1:25*`MULT_BITS]), + .data_out_empty(data_out_empty[25]), + .addr_out(addr_out[(25+1)*`ROW_ID_BITS-1:25*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[25]), + .done(done[25]) + ); + + Channel_Accumulator CH_26 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(26+1)*`MAT_VAL_BITS-1:26*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[26]), + .mat_val_rd_en(mat_val_rd_en[26]), + .vec_val(vec_val[(26+1)*`VEC_VAL_BITS-1:26*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[26]), + .vec_val_rd_en(vec_val_rd_en[26]), + .row_id(row_id[(26+1)*`ROW_ID_BITS-1:26*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[26]), + .row_id_rd_en(row_id_rd_en[26]), + .data_out(data_out[(26+1)*`MULT_BITS-1:26*`MULT_BITS]), + .data_out_empty(data_out_empty[26]), + .addr_out(addr_out[(26+1)*`ROW_ID_BITS-1:26*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[26]), + .done(done[26]) + ); + + Channel_Accumulator CH_27 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(27+1)*`MAT_VAL_BITS-1:27*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[27]), + .mat_val_rd_en(mat_val_rd_en[27]), + .vec_val(vec_val[(27+1)*`VEC_VAL_BITS-1:27*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[27]), + .vec_val_rd_en(vec_val_rd_en[27]), + .row_id(row_id[(27+1)*`ROW_ID_BITS-1:27*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[27]), + .row_id_rd_en(row_id_rd_en[27]), + .data_out(data_out[(27+1)*`MULT_BITS-1:27*`MULT_BITS]), + .data_out_empty(data_out_empty[27]), + .addr_out(addr_out[(27+1)*`ROW_ID_BITS-1:27*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[27]), + .done(done[27]) + ); + + Channel_Accumulator CH_28 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(28+1)*`MAT_VAL_BITS-1:28*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[28]), + .mat_val_rd_en(mat_val_rd_en[28]), + .vec_val(vec_val[(28+1)*`VEC_VAL_BITS-1:28*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[28]), + .vec_val_rd_en(vec_val_rd_en[28]), + .row_id(row_id[(28+1)*`ROW_ID_BITS-1:28*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[28]), + .row_id_rd_en(row_id_rd_en[28]), + .data_out(data_out[(28+1)*`MULT_BITS-1:28*`MULT_BITS]), + .data_out_empty(data_out_empty[28]), + .addr_out(addr_out[(28+1)*`ROW_ID_BITS-1:28*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[28]), + .done(done[28]) + ); + + Channel_Accumulator CH_29 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(29+1)*`MAT_VAL_BITS-1:29*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[29]), + .mat_val_rd_en(mat_val_rd_en[29]), + .vec_val(vec_val[(29+1)*`VEC_VAL_BITS-1:29*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[29]), + .vec_val_rd_en(vec_val_rd_en[29]), + .row_id(row_id[(29+1)*`ROW_ID_BITS-1:29*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[29]), + .row_id_rd_en(row_id_rd_en[29]), + .data_out(data_out[(29+1)*`MULT_BITS-1:29*`MULT_BITS]), + .data_out_empty(data_out_empty[29]), + .addr_out(addr_out[(29+1)*`ROW_ID_BITS-1:29*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[29]), + .done(done[29]) + ); + + Channel_Accumulator CH_30 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(30+1)*`MAT_VAL_BITS-1:30*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[30]), + .mat_val_rd_en(mat_val_rd_en[30]), + .vec_val(vec_val[(30+1)*`VEC_VAL_BITS-1:30*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[30]), + .vec_val_rd_en(vec_val_rd_en[30]), + .row_id(row_id[(30+1)*`ROW_ID_BITS-1:30*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[30]), + .row_id_rd_en(row_id_rd_en[30]), + .data_out(data_out[(30+1)*`MULT_BITS-1:30*`MULT_BITS]), + .data_out_empty(data_out_empty[30]), + .addr_out(addr_out[(30+1)*`ROW_ID_BITS-1:30*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[30]), + .done(done[30]) + ); + + Channel_Accumulator CH_31 ( + .clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val[(31+1)*`MAT_VAL_BITS-1:31*`MAT_VAL_BITS]), + .mat_val_empty(mat_val_empty[31]), + .mat_val_rd_en(mat_val_rd_en[31]), + .vec_val(vec_val[(31+1)*`VEC_VAL_BITS-1:31*`VEC_VAL_BITS]), + .vec_val_empty(vec_val_empty[31]), + .vec_val_rd_en(vec_val_rd_en[31]), + .row_id(row_id[(31+1)*`ROW_ID_BITS-1:31*`ROW_ID_BITS]), + .row_id_empty(row_id_empty[31]), + .row_id_rd_en(row_id_rd_en[31]), + .data_out(data_out[(31+1)*`MULT_BITS-1:31*`MULT_BITS]), + .data_out_empty(data_out_empty[31]), + .addr_out(addr_out[(31+1)*`ROW_ID_BITS-1:31*`ROW_ID_BITS]), + .out_rd_en(out_rd_en[31]), + .done(done[31]) + ); +endmodule + +module Channel_Accumulator( + input clk, + input rst, + input start, + input fetcher_done, + + input [`MAT_VAL_BITS-1:0] mat_val, + input mat_val_empty, + output mat_val_rd_en, + + input [`VEC_VAL_BITS-1:0] vec_val, + input vec_val_empty, + output vec_val_rd_en, + + input [`ROW_ID_BITS-1:0] row_id, + input row_id_empty, + output row_id_rd_en, + + output [`MULT_BITS-1:0] data_out, + output data_out_empty, + output [`ROW_ID_BITS-1:0] addr_out, + input out_rd_en, + + output done + ); + + wire mult_rd_en; + wire mult_empty; + wire [`MULT_BITS-1:0] mult_out; + wire mult_done; + + Channel CH0(.clk(clk), + .rst(rst), + .start(start), + .fetcher_done(fetcher_done), + .mat_val(mat_val), + .mat_val_empty(mat_val_empty), + .mat_val_rd_en(mat_val_rd_en), + .vec_val(vec_val), + .vec_val_empty(vec_val_empty), + .vec_val_rd_en(vec_val_rd_en), + .mult_out(mult_out), + .mult_empty(mult_empty), + .mult_rd_en(mult_rd_en), + .done(mult_done) + ); + + Accumulator A0( .clk(clk), + .rst(rst), + .start(start), + .mult_done(mult_done), + .row_id(row_id), + .row_id_empty(row_id_empty), + .row_id_rd_en(row_id_rd_en), + .mult_out(mult_out), + .mult_empty(mult_empty), + .mult_rd_en(mult_rd_en), + .data_out(data_out), + .data_out_empty(data_out_empty), + .addr_out(addr_out), + .out_rd_en(out_rd_en), + .done(done) + ); + +endmodule + +module Channel( + input clk, + input rst, + input start, + input fetcher_done, + + input [`MAT_VAL_BITS-1:0] mat_val, + input mat_val_empty, + output mat_val_rd_en, + + input [`VEC_VAL_BITS-1:0] vec_val, + input vec_val_empty, + output vec_val_rd_en, + + output [`MULT_BITS-1:0] mult_out, + output mult_empty, + input mult_rd_en, + + output done + ); + + parameter FIFO_DEPTH = 8; + // parameter FIFO_DEPTH_BITS = `LOG2(FIFO_DEPTH); + parameter FIFO_DEPTH_BITS = $clog2(8); + + reg [`MULT_BITS-1:0] mult; + reg mult_wr_en; + wire mult_full; + + reg vec_val_rd_en_reg; + reg mat_val_rd_en_reg; + + generic_fifo_sc_a #( + .dw(`MULT_BITS), + .aw(FIFO_DEPTH_BITS) + ) fifo_mult ( + .clk(clk), + .rst(rst), + .clr(1'b0), + .din(mult), + .we(mult_wr_en), + .re(mult_rd_en), + .dout(mult_out), + .full(mult_full), + .empty(mult_empty) + ); + + assign done = mat_val_empty & fetcher_done & start; + + assign vec_val_rd_en = start & (~vec_val_empty) & (~mat_val_empty) & (~mult_full); + assign mat_val_rd_en = start & (~vec_val_empty) & (~mat_val_empty) & (~mult_full); + + always@(posedge clk) begin + vec_val_rd_en_reg <= vec_val_rd_en; + mat_val_rd_en_reg <= mat_val_rd_en; + + if(vec_val_rd_en_reg && mat_val_rd_en_reg) begin + mult <= vec_val * mat_val; + mult_wr_en <= 1; + end + else begin + mult_wr_en <= 0; + end + end +endmodule + +module Accumulator( + input clk, + input rst, + input start, + input mult_done, + + input [`ROW_ID_BITS-1:0] row_id, + input row_id_empty, + output row_id_rd_en, + + input [`MULT_BITS-1:0] mult_out, + input mult_empty, + output mult_rd_en, + + output [`MULT_BITS-1:0] data_out, + output data_out_empty, + output [`ROW_ID_BITS-1:0] addr_out, + input out_rd_en, + + output reg done + ); + + reg first_read; + + reg row_id_rd_en_reg; + reg mult_rd_en_reg; + + wire data_out_full; + wire addr_out_full_nc; + + wire addr_out_empty_nc; + + reg [`MULT_BITS-1:0] wr_data; + reg [`ROW_ID_BITS-1:0] wr_addr; + reg wr_en; + + reg [`MULT_BITS-1:0] wr_data_delay; + reg [`ROW_ID_BITS-1:0] wr_addr_delay; + + reg last; + + parameter FIFO_DEPTH_BITS = $clog2(`FIFO_DEPTH); + + generic_fifo_sc_a #( + .aw(FIFO_DEPTH_BITS), + .dw(`MULT_BITS) + ) fifo_data_out ( + .clk(clk), + .rst(rst), + .clr(1'b0), + .din(wr_data_delay), + .we(wr_en), + .re(out_rd_en), + .dout(data_out), + .full(data_out_full), + .empty(data_out_empty) + ); + + generic_fifo_sc_a #( + .aw(FIFO_DEPTH_BITS), + .dw(`ROW_ID_BITS) + ) fifo_addr_out ( + .clk(clk), + .rst(rst), + .clr(1'b0), + .din(wr_addr_delay), + .we(wr_en), + .re(out_rd_en), + .dout(addr_out), + .full(addr_out_full_nc), + .empty(addr_out_empty_nc) + ); + + assign row_id_rd_en = start & (~row_id_empty) & (~mult_empty) & (~data_out_full); + assign mult_rd_en = start & (~row_id_empty) & (~mult_empty) & (~data_out_full); + + always@(posedge clk) begin + if(rst) begin + wr_data<=0; + wr_en<=0; + first_read <= 0; + done <= 0; + end + else if(start) begin + last <= mult_done & row_id_empty; + row_id_rd_en_reg <= row_id_rd_en; + mult_rd_en_reg <= mult_rd_en; + wr_addr_delay <= wr_addr; + wr_data_delay <= wr_data; + + if(~first_read) begin + wr_addr <= row_id; + first_read <= 1; + end + else if(row_id_rd_en_reg & mult_rd_en_reg) begin + if(row_id!=wr_addr) begin + wr_en <= 1; + wr_data <= mult_out; + wr_addr <= row_id; + end + else begin + wr_en <= 0; + wr_data <= wr_data + mult_out; + end + end + else if (last) begin + wr_en <= 1; + done <= 1; + end + else begin + wr_en <= 0; + end + end + end +endmodule + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp $ +// +// $Date: 2002-09-25 05:42:06 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// +// +// +// +// +// +// + +// `include "timescale.v" + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +// `define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +// `define SC_FIFO_ASYNC_RESET or posedge rst // Uncomment for Async. reset + + +module generic_fifo_sc_a + #(parameter dw=8, + parameter aw=8) + (clk, rst, clr, din, we, dout, re, + full, empty); + +localparam max_size = 1< 18'd13) ? 1'b1 : 1'b0); + +assign empty_162_fu_578_p2 = ((tmp1_cast_fu_574_p1) + (empty_reg_920)); + +assign empty_fu_293_p1 = indices_12_dout[7:0]; + +assign icmp_ln19_fu_410_p2 = ((indvar_flatten47_reg_231 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_422_p2 = ((indvar_flatten_reg_254 == 7'd48) ? 1'b1 : 1'b0); + +assign icmp_ln24_8_fu_392_p2 = (((add_ln22_8_fu_379_p2) > (18'd13)) ? 1'b1 : 1'b0); + +assign icmp_ln24_9_fu_692_p2 = (((add_ln22_9_reg_1021) > (18'd13)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_337_p2 = (((add_ln22_fu_314_p2) > (17'd13)) ? 1'b1 : 1'b0); + +assign ifmap_vec_0_address0 = sext_ln33_fu_897_p1; + +assign ifmap_vec_0_d0 = select_ln33_reg_1081; + +assign ifmap_vec_1_address0 = sext_ln33_fu_897_p1; + +assign ifmap_vec_1_d0 = select_ln33_23_reg_1086; + +assign ifmap_vec_2_address0 = sext_ln33_fu_897_p1; + +assign ifmap_vec_2_d0 = select_ln33_24_reg_1091; + +assign ifmap_vec_3_address0 = sext_ln33_fu_897_p1; + +assign ifmap_vec_3_d0 = select_ln33_25_reg_1096; + +assign ii_cast_fu_548_p1 = ii_reg_242; + +assign ii_cast_i_i_fu_360_p1 = ap_phi_mux_ii_phi_fu_246_p4; + +assign ii_cast_i_i_mid1_fu_452_p1 = add_ln19_fu_416_p2; + +assign ii_cast_mid1_fu_614_p1 = add_ln19_reg_976; + +assign in_data_address0 = sext_ln32_fu_808_p1; + +assign in_data_elem_13_fu_838_p1 = tmp_357_i_i_fu_828_p4; + +assign in_data_elem_14_fu_859_p1 = tmp_358_i_i_fu_849_p4; + +assign in_data_elem_15_fu_880_p1 = tmp_359_i_i_fu_870_p4; + +assign in_data_elem_fu_817_p1 = trunc_ln32_fu_813_p1; + +assign indices_01_out_din = indices_01_dout[3:0]; + +assign indices_12_out_din = indices_12_dout[7:0]; + +assign is_padding_fu_404_p2 = (or_ln23_fu_398_p2 | empty_161_fu_369_p2); + +assign j_cast_i_i_fu_298_p1 = indices_12_read_reg_915; + +assign or_ln19_fu_481_p2 = (xor_ln25_fu_475_p2 | icmp_ln20_fu_422_p2); + +assign or_ln23_36_fu_343_p2 = (tmp_96_fu_329_p3 | icmp_ln24_fu_337_p2); + +assign or_ln23_38_fu_634_p2 = (p_mid113_reg_997 | or_ln23_36_reg_945); + +assign or_ln23_39_fu_697_p2 = (tmp_99_fu_685_p3 | icmp_ln24_9_fu_692_p2); + +assign or_ln23_40_fu_703_p2 = (select_ln19_51_fu_629_p3 | or_ln23_39_fu_697_p2); + +assign or_ln23_fu_398_p2 = (tmp_97_fu_384_p3 | icmp_ln24_8_fu_392_p2); + +assign p_cast28_i_i_fu_552_p2 = (p_cast_reg_939 + ii_cast_fu_548_p1); + +assign p_cast28_i_i_mid1_fu_617_p2 = (p_cast_reg_939 + ii_cast_mid1_fu_614_p1); + +assign p_cast_fu_324_p2 = ((trunc_ln289_reg_910) + (4'd15)); + +assign p_cast_i_i_fu_310_p1 = (empty_159_fu_304_p2); + +assign p_mid111_fu_456_p2 = ((p_cast_i_i_reg_927) + (ii_cast_i_i_mid1_fu_452_p1)); + +assign p_mid113_fu_461_p2 = ((p_mid111_fu_456_p2 > 18'd13) ? 1'b1 : 1'b0); + +assign p_mid137_fu_349_p2 = ((empty_reg_920) + (8'd255)); + +assign p_mid1_fu_734_p2 = ((tmp1_cast_mid1_fu_730_p1) + (empty_reg_920)); + +assign row_coord_int_fu_561_p3 = ((is_padding_reg_965[0:0] == 1'b1) ? 4'd0 : p_cast28_i_i_fu_552_p2); + +assign row_coord_int_mid131_fu_644_p3 = ((or_ln23_38_fu_634_p2[0:0] == 1'b1) ? 4'd0 : p_cast28_i_i_mid1_fu_617_p2); + +assign row_coord_int_mid1_fu_716_p3 = ((or_ln23_40_fu_703_p2[0:0] == 1'b1) ? 4'd0 : select_ln19_50_fu_622_p3); + +assign select_ln19_48_fu_436_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? 7'd0 : kk_reg_277); + +assign select_ln19_49_fu_444_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? add_ln19_fu_416_p2 : ap_phi_mux_ii_phi_fu_246_p4); + +assign select_ln19_50_fu_622_p3 = ((icmp_ln20_reg_981[0:0] == 1'b1) ? p_cast28_i_i_mid1_fu_617_p2 : p_cast28_i_i_fu_552_p2); + +assign select_ln19_51_fu_629_p3 = ((icmp_ln20_reg_981[0:0] == 1'b1) ? p_mid113_reg_997 : empty_161_reg_960); + +assign select_ln19_52_fu_638_p3 = ((icmp_ln20_reg_981[0:0] == 1'b1) ? or_ln23_38_fu_634_p2 : is_padding_reg_965); + +assign select_ln19_53_fu_659_p3 = ((icmp_ln20_reg_981[0:0] == 1'b1) ? row_coord_int_mid131_fu_644_p3 : row_coord_int_fu_561_p3); + +assign select_ln19_54_fu_666_p3 = ((icmp_ln20_reg_981[0:0] == 1'b1) ? col_coord_int_mid139_fu_652_p3 : col_coord_int_fu_583_p3); + +assign select_ln19_fu_428_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_269_p4); + +assign select_ln20_35_fu_501_p3 = ((or_ln19_fu_481_p2[0:0] == 1'b1) ? select_ln19_fu_428_p3 : add_ln20_fu_487_p2); + +assign select_ln20_36_fu_709_p3 = ((or_ln19_reg_1003[0:0] == 1'b1) ? select_ln19_52_fu_638_p3 : or_ln23_40_fu_703_p2); + +assign select_ln20_37_fu_739_p3 = ((or_ln19_reg_1003[0:0] == 1'b1) ? select_ln19_53_fu_659_p3 : row_coord_int_mid1_fu_716_p3); + +assign select_ln20_38_fu_785_p3 = ((or_ln19_reg_1003_pp0_iter1_reg[0:0] == 1'b1) ? select_ln19_54_reg_1043 : col_coord_int_mid1_fu_776_p3); + +assign select_ln20_39_fu_540_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? 7'd1 : add_ln20_8_fu_534_p2); + +assign select_ln20_fu_493_p3 = ((or_ln19_fu_481_p2[0:0] == 1'b1) ? select_ln19_48_fu_436_p3 : 7'd0); + +assign select_ln33_23_fu_842_p3 = ((select_ln20_36_reg_1058_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_13_fu_838_p1); + +assign select_ln33_24_fu_863_p3 = ((select_ln20_36_reg_1058_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_14_fu_859_p1); + +assign select_ln33_25_fu_884_p3 = ((select_ln20_36_reg_1058_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_15_fu_880_p1); + +assign select_ln33_fu_821_p3 = ((select_ln20_36_reg_1058_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_fu_817_p1); + +assign sext_ln20_fu_782_p1 = (sub_ln32_reg_1071); + +assign sext_ln22_fu_320_p1 = add_ln22_fu_314_p2; + +assign sext_ln32_fu_808_p1 = (tmp_100_fu_801_p3); + +assign sext_ln33_fu_897_p1 = (tmp_101_fu_891_p3); + +assign sub_ln32_fu_770_p2 = (zext_ln32_fu_754_p1 - zext_ln32_65_fu_766_p1); + +assign sub_ln33_cast_fu_610_p1 = (sub_ln33_fu_604_p2); + +assign sub_ln33_fu_604_p2 = (zext_ln33_18_fu_600_p1 - zext_ln33_fu_590_p1); + +assign tmp1_cast_fu_574_p1 = (tmp1_fu_568_p2); + +assign tmp1_cast_mid1_fu_730_p1 = (tmp1_mid1_fu_724_p2); + +assign tmp1_fu_568_p2 = ((zext_ln22_fu_557_p1) + (3'd7)); + +assign tmp1_mid1_fu_724_p2 = ((zext_ln22_8_fu_682_p1) + (3'd7)); + +assign tmp_100_fu_801_p3 = {{add_ln32_fu_795_p2}, {lshr_ln_reg_1027_pp0_iter1_reg}}; + +assign tmp_101_fu_891_p3 = {{add_ln33_reg_1048_pp0_iter3_reg}, {lshr_ln_reg_1027_pp0_iter3_reg}}; + +assign tmp_357_i_i_fu_828_p4 = {{in_data_q0[31:16]}}; + +assign tmp_358_i_i_fu_849_p4 = {{in_data_q0[47:32]}}; + +assign tmp_359_i_i_fu_870_p4 = {{in_data_q0[63:48]}}; + +assign tmp_65_fu_758_p3 = {{select_ln20_37_fu_739_p3}, {1'd0}}; + +assign tmp_96_fu_329_p3 = add_ln22_fu_314_p2[32'd16]; + +assign tmp_97_fu_384_p3 = add_ln22_8_fu_379_p2[32'd17]; + +assign tmp_98_fu_467_p3 = kk_reg_277[32'd6]; + +assign tmp_99_fu_685_p3 = add_ln22_9_reg_1021[32'd17]; + +assign tmp_fu_593_p3 = {{select_ln19_49_reg_990}, {2'd0}}; + +assign tmp_s_fu_746_p3 = {{select_ln20_37_fu_739_p3}, {4'd0}}; + +assign trunc_ln289_fu_288_p1 = indices_01_dout[3:0]; + +assign trunc_ln32_fu_813_p1 = in_data_q0[15:0]; + +assign xor_ln25_fu_475_p2 = (tmp_98_fu_467_p3 ^ 1'd1); + +assign zext_ln19_fu_301_p1 = indices_01_read_reg_905; + +assign zext_ln20_8_fu_509_p1 = add_ln20_fu_487_p2; + +assign zext_ln20_fu_375_p1 = ap_phi_mux_jj_phi_fu_269_p4; + +assign zext_ln22_8_fu_682_p1 = add_ln20_reg_1010; + +assign zext_ln22_fu_557_p1 = jj_reg_265; + +assign zext_ln32_65_fu_766_p1 = tmp_65_fu_758_p3; + +assign zext_ln32_66_fu_791_p1 = select_ln20_38_fu_785_p3; + +assign zext_ln32_fu_754_p1 = tmp_s_fu_746_p3; + +assign zext_ln33_18_fu_600_p1 = tmp_fu_593_p3; + +assign zext_ln33_19_fu_673_p1 = select_ln20_35_reg_1015; + +assign zext_ln33_fu_590_p1 = select_ln19_49_reg_990; + +always @ (posedge ap_clk) begin + sub_ln32_reg_1071[0] <= 1'b0; +end + +endmodule //td_fused_top_tdf10_readInputs71 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_114 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_0_address0, + filter_data_0_ce0, + filter_data_0_d0, + filter_data_0_q0, + filter_data_0_we0, + filter_data_0_address1, + filter_data_0_ce1, + filter_data_0_d1, + filter_data_0_q1, + filter_data_0_we1, + filter_data_1_address0, + filter_data_1_ce0, + filter_data_1_d0, + filter_data_1_q0, + filter_data_1_we0, + filter_data_1_address1, + filter_data_1_ce1, + filter_data_1_d1, + filter_data_1_q1, + filter_data_1_we1, + filter_data_2_address0, + filter_data_2_ce0, + filter_data_2_d0, + filter_data_2_q0, + filter_data_2_we0, + filter_data_2_address1, + filter_data_2_ce1, + filter_data_2_d1, + filter_data_2_q1, + filter_data_2_we1, + filter_data_3_address0, + filter_data_3_ce0, + filter_data_3_d0, + filter_data_3_q0, + filter_data_3_we0, + filter_data_3_address1, + filter_data_3_ce1, + filter_data_3_d1, + filter_data_3_q1, + filter_data_3_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [15:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [15:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [15:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [15:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [6:0] filter_data_0_address0; +output filter_data_0_ce0; +output [15:0] filter_data_0_d0; +input [15:0] filter_data_0_q0; +output filter_data_0_we0; +output [6:0] filter_data_0_address1; +output filter_data_0_ce1; +output [15:0] filter_data_0_d1; +input [15:0] filter_data_0_q1; +output filter_data_0_we1; +output [6:0] filter_data_1_address0; +output filter_data_1_ce0; +output [15:0] filter_data_1_d0; +input [15:0] filter_data_1_q0; +output filter_data_1_we0; +output [6:0] filter_data_1_address1; +output filter_data_1_ce1; +output [15:0] filter_data_1_d1; +input [15:0] filter_data_1_q1; +output filter_data_1_we1; +output [6:0] filter_data_2_address0; +output filter_data_2_ce0; +output [15:0] filter_data_2_d0; +input [15:0] filter_data_2_q0; +output filter_data_2_we0; +output [6:0] filter_data_2_address1; +output filter_data_2_ce1; +output [15:0] filter_data_2_d1; +input [15:0] filter_data_2_q1; +output filter_data_2_we1; +output [6:0] filter_data_3_address0; +output filter_data_3_ce0; +output [15:0] filter_data_3_d0; +input [15:0] filter_data_3_q0; +output filter_data_3_we0; +output [6:0] filter_data_3_address1; +output filter_data_3_ce1; +output [15:0] filter_data_3_d1; +input [15:0] filter_data_3_q1; +output filter_data_3_we1; +output [3:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [3:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [15:0] dataflow_in_loop_TOP_LOOP16_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP16_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP16_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP16_U0_in_data_we0; +wire [15:0] dataflow_in_loop_TOP_LOOP16_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP16_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP16_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP16_U0_in_data_we1; +wire [6:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_address0; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_d0; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_we0; +wire [6:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_address1; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_d1; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_we1; +wire [6:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_address0; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_d0; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_we0; +wire [6:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_address1; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_d1; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_we1; +wire [6:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_address0; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_d0; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_we0; +wire [6:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_address1; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_d1; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_we1; +wire [6:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_address0; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_d0; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_we0; +wire [6:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_address1; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_d1; +wire dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_we1; +wire [3:0] dataflow_in_loop_TOP_LOOP16_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP16_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP16_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP16_U0_adjustments_we0; +wire [3:0] dataflow_in_loop_TOP_LOOP16_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP16_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP16_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP16_U0_adjustments_we1; +wire [15:0] dataflow_in_loop_TOP_LOOP16_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP16_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP16_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP16_U0_out_data_we0; +wire [15:0] dataflow_in_loop_TOP_LOOP16_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP16_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP16_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP16_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP16_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP16_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP16_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP16_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP16_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP16_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP16_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP16_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP16_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [17:0] loop_dataflow_input_count; +reg [17:0] loop_dataflow_output_count; +wire [17:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP16_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP16_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 18'd0; +#0 loop_dataflow_output_count = 18'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP16 dataflow_in_loop_TOP_LOOP16_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP16_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP16_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP16_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP16_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP16_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP16_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP16_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP16_U0_in_data_we1), + .filter_data_0_address0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_address0), + .filter_data_0_ce0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_ce0), + .filter_data_0_d0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_d0), + .filter_data_0_q0(filter_data_0_q0), + .filter_data_0_we0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_we0), + .filter_data_0_address1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_address1), + .filter_data_0_ce1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_ce1), + .filter_data_0_d1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_d1), + .filter_data_0_q1(16'd0), + .filter_data_0_we1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_we1), + .filter_data_1_address0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_address0), + .filter_data_1_ce0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_ce0), + .filter_data_1_d0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_d0), + .filter_data_1_q0(filter_data_1_q0), + .filter_data_1_we0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_we0), + .filter_data_1_address1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_address1), + .filter_data_1_ce1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_ce1), + .filter_data_1_d1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_d1), + .filter_data_1_q1(16'd0), + .filter_data_1_we1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_we1), + .filter_data_2_address0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_address0), + .filter_data_2_ce0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_ce0), + .filter_data_2_d0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_d0), + .filter_data_2_q0(filter_data_2_q0), + .filter_data_2_we0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_we0), + .filter_data_2_address1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_address1), + .filter_data_2_ce1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_ce1), + .filter_data_2_d1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_d1), + .filter_data_2_q1(16'd0), + .filter_data_2_we1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_we1), + .filter_data_3_address0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_address0), + .filter_data_3_ce0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_ce0), + .filter_data_3_d0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_d0), + .filter_data_3_q0(filter_data_3_q0), + .filter_data_3_we0(dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_we0), + .filter_data_3_address1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_address1), + .filter_data_3_ce1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_ce1), + .filter_data_3_d1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_d1), + .filter_data_3_q1(16'd0), + .filter_data_3_we1(dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP16_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP16_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP16_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP16_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP16_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP16_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP16_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP16_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP16_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP16_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP16_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP16_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP16_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP16_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP16_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP16_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP16_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP16_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP16_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP16_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP16_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP16_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP16_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 18'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP16_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 18'd1); + end else if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP16_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= 18'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 18'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP16_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP16_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 18'd1); + end else if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP16_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP16_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= 18'd0; + end + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP16_U0_ap_done == 1'b1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == 18'd0) & (ap_start == 1'b0) & (dataflow_in_loop_TOP_LOOP16_U0_ap_idle == 1'b1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP16_U0_ap_ready == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP16_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP16_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP16_U0_adjustments_address0; + +assign adjustments_address1 = 4'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP16_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP16_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP16_U0_ap_ready; + +assign bound_minus_1 = (18'd200704 - 18'd1); + +assign dataflow_in_loop_TOP_LOOP16_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP16_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP16_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP16_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP16_U0_start_write = 1'b0; + +assign filter_data_0_address0 = dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_address0; + +assign filter_data_0_address1 = 7'd0; + +assign filter_data_0_ce0 = dataflow_in_loop_TOP_LOOP16_U0_filter_data_0_ce0; + +assign filter_data_0_ce1 = 1'b0; + +assign filter_data_0_d0 = 16'd0; + +assign filter_data_0_d1 = 16'd0; + +assign filter_data_0_we0 = 1'b0; + +assign filter_data_0_we1 = 1'b0; + +assign filter_data_1_address0 = dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_address0; + +assign filter_data_1_address1 = 7'd0; + +assign filter_data_1_ce0 = dataflow_in_loop_TOP_LOOP16_U0_filter_data_1_ce0; + +assign filter_data_1_ce1 = 1'b0; + +assign filter_data_1_d0 = 16'd0; + +assign filter_data_1_d1 = 16'd0; + +assign filter_data_1_we0 = 1'b0; + +assign filter_data_1_we1 = 1'b0; + +assign filter_data_2_address0 = dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_address0; + +assign filter_data_2_address1 = 7'd0; + +assign filter_data_2_ce0 = dataflow_in_loop_TOP_LOOP16_U0_filter_data_2_ce0; + +assign filter_data_2_ce1 = 1'b0; + +assign filter_data_2_d0 = 16'd0; + +assign filter_data_2_d1 = 16'd0; + +assign filter_data_2_we0 = 1'b0; + +assign filter_data_2_we1 = 1'b0; + +assign filter_data_3_address0 = dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_address0; + +assign filter_data_3_address1 = 7'd0; + +assign filter_data_3_ce0 = dataflow_in_loop_TOP_LOOP16_U0_filter_data_3_ce0; + +assign filter_data_3_ce1 = 1'b0; + +assign filter_data_3_d0 = 16'd0; + +assign filter_data_3_d1 = 16'd0; + +assign filter_data_3_we0 = 1'b0; + +assign filter_data_3_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP16_U0_in_data_address0; + +assign in_data_address1 = 16'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP16_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP16_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 16'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP16_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP16_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP16_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP16_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP16_U0_out_data_write; + +endmodule //td_fused_top_tdf1_114 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_14 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + l1_filter_data_0_address0, + l1_filter_data_0_ce0, + l1_filter_data_0_d0, + l1_filter_data_0_q0, + l1_filter_data_0_we0, + l1_filter_data_0_address1, + l1_filter_data_0_ce1, + l1_filter_data_0_d1, + l1_filter_data_0_q1, + l1_filter_data_0_we1, + l1_filter_data_1_address0, + l1_filter_data_1_ce0, + l1_filter_data_1_d0, + l1_filter_data_1_q0, + l1_filter_data_1_we0, + l1_filter_data_1_address1, + l1_filter_data_1_ce1, + l1_filter_data_1_d1, + l1_filter_data_1_q1, + l1_filter_data_1_we1, + l1_filter_data_2_address0, + l1_filter_data_2_ce0, + l1_filter_data_2_d0, + l1_filter_data_2_q0, + l1_filter_data_2_we0, + l1_filter_data_2_address1, + l1_filter_data_2_ce1, + l1_filter_data_2_d1, + l1_filter_data_2_q1, + l1_filter_data_2_we1, + l1_filter_data_3_address0, + l1_filter_data_3_ce0, + l1_filter_data_3_d0, + l1_filter_data_3_q0, + l1_filter_data_3_we0, + l1_filter_data_3_address1, + l1_filter_data_3_ce1, + l1_filter_data_3_d1, + l1_filter_data_3_q1, + l1_filter_data_3_we1, + l2_filter_data_0_address0, + l2_filter_data_0_ce0, + l2_filter_data_0_d0, + l2_filter_data_0_q0, + l2_filter_data_0_we0, + l2_filter_data_0_address1, + l2_filter_data_0_ce1, + l2_filter_data_0_d1, + l2_filter_data_0_q1, + l2_filter_data_0_we1, + l2_filter_data_1_address0, + l2_filter_data_1_ce0, + l2_filter_data_1_d0, + l2_filter_data_1_q0, + l2_filter_data_1_we0, + l2_filter_data_1_address1, + l2_filter_data_1_ce1, + l2_filter_data_1_d1, + l2_filter_data_1_q1, + l2_filter_data_1_we1, + l2_filter_data_2_address0, + l2_filter_data_2_ce0, + l2_filter_data_2_d0, + l2_filter_data_2_q0, + l2_filter_data_2_we0, + l2_filter_data_2_address1, + l2_filter_data_2_ce1, + l2_filter_data_2_d1, + l2_filter_data_2_q1, + l2_filter_data_2_we1, + l2_filter_data_3_address0, + l2_filter_data_3_ce0, + l2_filter_data_3_d0, + l2_filter_data_3_q0, + l2_filter_data_3_we0, + l2_filter_data_3_address1, + l2_filter_data_3_ce1, + l2_filter_data_3_d1, + l2_filter_data_3_q1, + l2_filter_data_3_we1, + l1_adjustments_address0, + l1_adjustments_ce0, + l1_adjustments_d0, + l1_adjustments_q0, + l1_adjustments_we0, + l1_adjustments_address1, + l1_adjustments_ce1, + l1_adjustments_d1, + l1_adjustments_q1, + l1_adjustments_we1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_d0, + l2_adjustments_q0, + l2_adjustments_we0, + l2_adjustments_address1, + l2_adjustments_ce1, + l2_adjustments_d1, + l2_adjustments_q1, + l2_adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [11:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [11:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [12:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [12:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [14:0] l1_filter_data_0_address0; +output l1_filter_data_0_ce0; +output [63:0] l1_filter_data_0_d0; +input [63:0] l1_filter_data_0_q0; +output l1_filter_data_0_we0; +output [14:0] l1_filter_data_0_address1; +output l1_filter_data_0_ce1; +output [63:0] l1_filter_data_0_d1; +input [63:0] l1_filter_data_0_q1; +output l1_filter_data_0_we1; +output [14:0] l1_filter_data_1_address0; +output l1_filter_data_1_ce0; +output [63:0] l1_filter_data_1_d0; +input [63:0] l1_filter_data_1_q0; +output l1_filter_data_1_we0; +output [14:0] l1_filter_data_1_address1; +output l1_filter_data_1_ce1; +output [63:0] l1_filter_data_1_d1; +input [63:0] l1_filter_data_1_q1; +output l1_filter_data_1_we1; +output [14:0] l1_filter_data_2_address0; +output l1_filter_data_2_ce0; +output [63:0] l1_filter_data_2_d0; +input [63:0] l1_filter_data_2_q0; +output l1_filter_data_2_we0; +output [14:0] l1_filter_data_2_address1; +output l1_filter_data_2_ce1; +output [63:0] l1_filter_data_2_d1; +input [63:0] l1_filter_data_2_q1; +output l1_filter_data_2_we1; +output [14:0] l1_filter_data_3_address0; +output l1_filter_data_3_ce0; +output [63:0] l1_filter_data_3_d0; +input [63:0] l1_filter_data_3_q0; +output l1_filter_data_3_we0; +output [14:0] l1_filter_data_3_address1; +output l1_filter_data_3_ce1; +output [63:0] l1_filter_data_3_d1; +input [63:0] l1_filter_data_3_q1; +output l1_filter_data_3_we1; +output [13:0] l2_filter_data_0_address0; +output l2_filter_data_0_ce0; +output [15:0] l2_filter_data_0_d0; +input [15:0] l2_filter_data_0_q0; +output l2_filter_data_0_we0; +output [13:0] l2_filter_data_0_address1; +output l2_filter_data_0_ce1; +output [15:0] l2_filter_data_0_d1; +input [15:0] l2_filter_data_0_q1; +output l2_filter_data_0_we1; +output [13:0] l2_filter_data_1_address0; +output l2_filter_data_1_ce0; +output [15:0] l2_filter_data_1_d0; +input [15:0] l2_filter_data_1_q0; +output l2_filter_data_1_we0; +output [13:0] l2_filter_data_1_address1; +output l2_filter_data_1_ce1; +output [15:0] l2_filter_data_1_d1; +input [15:0] l2_filter_data_1_q1; +output l2_filter_data_1_we1; +output [13:0] l2_filter_data_2_address0; +output l2_filter_data_2_ce0; +output [15:0] l2_filter_data_2_d0; +input [15:0] l2_filter_data_2_q0; +output l2_filter_data_2_we0; +output [13:0] l2_filter_data_2_address1; +output l2_filter_data_2_ce1; +output [15:0] l2_filter_data_2_d1; +input [15:0] l2_filter_data_2_q1; +output l2_filter_data_2_we1; +output [13:0] l2_filter_data_3_address0; +output l2_filter_data_3_ce0; +output [15:0] l2_filter_data_3_d0; +input [15:0] l2_filter_data_3_q0; +output l2_filter_data_3_we0; +output [13:0] l2_filter_data_3_address1; +output l2_filter_data_3_ce1; +output [15:0] l2_filter_data_3_d1; +input [15:0] l2_filter_data_3_q1; +output l2_filter_data_3_we1; +output [8:0] l1_adjustments_address0; +output l1_adjustments_ce0; +output [47:0] l1_adjustments_d0; +input [47:0] l1_adjustments_q0; +output l1_adjustments_we0; +output [8:0] l1_adjustments_address1; +output l1_adjustments_ce1; +output [47:0] l1_adjustments_d1; +input [47:0] l1_adjustments_q1; +output l1_adjustments_we1; +output [6:0] l2_adjustments_address0; +output l2_adjustments_ce0; +output [47:0] l2_adjustments_d0; +input [47:0] l2_adjustments_q0; +output l2_adjustments_we0; +output [6:0] l2_adjustments_address1; +output l2_adjustments_ce1; +output [47:0] l2_adjustments_d1; +input [47:0] l2_adjustments_q1; +output l2_adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [11:0] dataflow_in_loop_TOP_LOOP47773_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP47773_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP47773_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP47773_U0_in_data_we0; +wire [11:0] dataflow_in_loop_TOP_LOOP47773_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP47773_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP47773_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP47773_U0_in_data_we1; +wire [14:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_address0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_d0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_address1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_d1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_we1; +wire [14:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_address0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_d0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_address1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_d1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_we1; +wire [14:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_address0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_d0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_address1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_d1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_we1; +wire [14:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_address0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_d0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_address1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_d1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_we1; +wire [8:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_we0; +wire [8:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_address0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_d0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_address1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_d1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_address0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_d0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_address1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_d1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_address0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_d0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_address1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_d1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_address0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_d0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_address1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_d1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_we1; +wire [12:0] dataflow_in_loop_TOP_LOOP47773_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP47773_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP47773_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP47773_U0_out_data_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP47773_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP47773_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP47773_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP47773_U0_out_data_we1; +wire [6:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_we0; +wire [6:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_we1; +wire dataflow_in_loop_TOP_LOOP47773_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP47773_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP47773_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP47773_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP47773_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP47773_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP47773_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP47773_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP47773_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [14:0] loop_dataflow_input_count; +reg [14:0] loop_dataflow_output_count; +wire [14:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP47773_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP47773_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 15'd0; +#0 loop_dataflow_output_count = 15'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP47773 dataflow_in_loop_TOP_LOOP47773_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP47773_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP47773_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP47773_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP47773_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP47773_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP47773_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP47773_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP47773_U0_in_data_we1), + .l1_filter_data_0_address0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_address0), + .l1_filter_data_0_ce0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_ce0), + .l1_filter_data_0_d0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_d0), + .l1_filter_data_0_q0(l1_filter_data_0_q0), + .l1_filter_data_0_we0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_we0), + .l1_filter_data_0_address1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_address1), + .l1_filter_data_0_ce1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_ce1), + .l1_filter_data_0_d1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_d1), + .l1_filter_data_0_q1(64'd0), + .l1_filter_data_0_we1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_we1), + .l1_filter_data_1_address0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_address0), + .l1_filter_data_1_ce0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_ce0), + .l1_filter_data_1_d0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_d0), + .l1_filter_data_1_q0(l1_filter_data_1_q0), + .l1_filter_data_1_we0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_we0), + .l1_filter_data_1_address1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_address1), + .l1_filter_data_1_ce1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_ce1), + .l1_filter_data_1_d1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_d1), + .l1_filter_data_1_q1(64'd0), + .l1_filter_data_1_we1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_we1), + .l1_filter_data_2_address0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_address0), + .l1_filter_data_2_ce0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_ce0), + .l1_filter_data_2_d0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_d0), + .l1_filter_data_2_q0(l1_filter_data_2_q0), + .l1_filter_data_2_we0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_we0), + .l1_filter_data_2_address1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_address1), + .l1_filter_data_2_ce1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_ce1), + .l1_filter_data_2_d1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_d1), + .l1_filter_data_2_q1(64'd0), + .l1_filter_data_2_we1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_we1), + .l1_filter_data_3_address0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_address0), + .l1_filter_data_3_ce0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_ce0), + .l1_filter_data_3_d0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_d0), + .l1_filter_data_3_q0(l1_filter_data_3_q0), + .l1_filter_data_3_we0(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_we0), + .l1_filter_data_3_address1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_address1), + .l1_filter_data_3_ce1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_ce1), + .l1_filter_data_3_d1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_d1), + .l1_filter_data_3_q1(64'd0), + .l1_filter_data_3_we1(dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_we1), + .l1_adjustments_address0(dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_address0), + .l1_adjustments_ce0(dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_ce0), + .l1_adjustments_d0(dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_d0), + .l1_adjustments_q0(l1_adjustments_q0), + .l1_adjustments_we0(dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_we0), + .l1_adjustments_address1(dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_address1), + .l1_adjustments_ce1(dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_ce1), + .l1_adjustments_d1(dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_d1), + .l1_adjustments_q1(48'd0), + .l1_adjustments_we1(dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_we1), + .l2_filter_data_0_address0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_address0), + .l2_filter_data_0_ce0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_ce0), + .l2_filter_data_0_d0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_d0), + .l2_filter_data_0_q0(l2_filter_data_0_q0), + .l2_filter_data_0_we0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_we0), + .l2_filter_data_0_address1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_address1), + .l2_filter_data_0_ce1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_ce1), + .l2_filter_data_0_d1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_d1), + .l2_filter_data_0_q1(l2_filter_data_0_q1), + .l2_filter_data_0_we1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_we1), + .l2_filter_data_1_address0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_address0), + .l2_filter_data_1_ce0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_ce0), + .l2_filter_data_1_d0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_d0), + .l2_filter_data_1_q0(l2_filter_data_1_q0), + .l2_filter_data_1_we0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_we0), + .l2_filter_data_1_address1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_address1), + .l2_filter_data_1_ce1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_ce1), + .l2_filter_data_1_d1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_d1), + .l2_filter_data_1_q1(l2_filter_data_1_q1), + .l2_filter_data_1_we1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_we1), + .l2_filter_data_2_address0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_address0), + .l2_filter_data_2_ce0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_ce0), + .l2_filter_data_2_d0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_d0), + .l2_filter_data_2_q0(l2_filter_data_2_q0), + .l2_filter_data_2_we0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_we0), + .l2_filter_data_2_address1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_address1), + .l2_filter_data_2_ce1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_ce1), + .l2_filter_data_2_d1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_d1), + .l2_filter_data_2_q1(l2_filter_data_2_q1), + .l2_filter_data_2_we1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_we1), + .l2_filter_data_3_address0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_address0), + .l2_filter_data_3_ce0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_ce0), + .l2_filter_data_3_d0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_d0), + .l2_filter_data_3_q0(l2_filter_data_3_q0), + .l2_filter_data_3_we0(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_we0), + .l2_filter_data_3_address1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_address1), + .l2_filter_data_3_ce1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_ce1), + .l2_filter_data_3_d1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_d1), + .l2_filter_data_3_q1(l2_filter_data_3_q1), + .l2_filter_data_3_we1(dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP47773_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP47773_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP47773_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP47773_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP47773_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP47773_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP47773_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP47773_U0_out_data_we1), + .l2_adjustments_address0(dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_address0), + .l2_adjustments_ce0(dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_ce0), + .l2_adjustments_d0(dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_d0), + .l2_adjustments_q0(l2_adjustments_q0), + .l2_adjustments_we0(dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_we0), + .l2_adjustments_address1(dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_address1), + .l2_adjustments_ce1(dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_ce1), + .l2_adjustments_d1(dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_d1), + .l2_adjustments_q1(48'd0), + .l2_adjustments_we1(dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_we1), + .ap_start(dataflow_in_loop_TOP_LOOP47773_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP47773_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP47773_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP47773_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP47773_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP47773_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP47773_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 15'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP47773_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 15'd1); + end else if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP47773_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= 15'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 15'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP47773_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP47773_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 15'd1); + end else if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP47773_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP47773_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= 15'd0; + end + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP47773_U0_ap_done == 1'b1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == 15'd0) & (ap_start == 1'b0) & (dataflow_in_loop_TOP_LOOP47773_U0_ap_idle == 1'b1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP47773_U0_ap_ready == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP47773_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP47773_U0_ap_continue = 1'b0; + end +end + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP47773_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP47773_U0_ap_ready; + +assign bound_minus_1 = (15'd25088 - 15'd1); + +assign dataflow_in_loop_TOP_LOOP47773_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP47773_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP47773_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP47773_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP47773_U0_start_write = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP47773_U0_in_data_address0; + +assign in_data_address1 = 12'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP47773_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP47773_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign l1_adjustments_address0 = dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_address0; + +assign l1_adjustments_address1 = 9'd0; + +assign l1_adjustments_ce0 = dataflow_in_loop_TOP_LOOP47773_U0_l1_adjustments_ce0; + +assign l1_adjustments_ce1 = 1'b0; + +assign l1_adjustments_d0 = 48'd0; + +assign l1_adjustments_d1 = 48'd0; + +assign l1_adjustments_we0 = 1'b0; + +assign l1_adjustments_we1 = 1'b0; + +assign l1_filter_data_0_address0 = dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_address0; + +assign l1_filter_data_0_address1 = 15'd0; + +assign l1_filter_data_0_ce0 = dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_0_ce0; + +assign l1_filter_data_0_ce1 = 1'b0; + +assign l1_filter_data_0_d0 = 64'd0; + +assign l1_filter_data_0_d1 = 64'd0; + +assign l1_filter_data_0_we0 = 1'b0; + +assign l1_filter_data_0_we1 = 1'b0; + +assign l1_filter_data_1_address0 = dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_address0; + +assign l1_filter_data_1_address1 = 15'd0; + +assign l1_filter_data_1_ce0 = dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_1_ce0; + +assign l1_filter_data_1_ce1 = 1'b0; + +assign l1_filter_data_1_d0 = 64'd0; + +assign l1_filter_data_1_d1 = 64'd0; + +assign l1_filter_data_1_we0 = 1'b0; + +assign l1_filter_data_1_we1 = 1'b0; + +assign l1_filter_data_2_address0 = dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_address0; + +assign l1_filter_data_2_address1 = 15'd0; + +assign l1_filter_data_2_ce0 = dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_2_ce0; + +assign l1_filter_data_2_ce1 = 1'b0; + +assign l1_filter_data_2_d0 = 64'd0; + +assign l1_filter_data_2_d1 = 64'd0; + +assign l1_filter_data_2_we0 = 1'b0; + +assign l1_filter_data_2_we1 = 1'b0; + +assign l1_filter_data_3_address0 = dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_address0; + +assign l1_filter_data_3_address1 = 15'd0; + +assign l1_filter_data_3_ce0 = dataflow_in_loop_TOP_LOOP47773_U0_l1_filter_data_3_ce0; + +assign l1_filter_data_3_ce1 = 1'b0; + +assign l1_filter_data_3_d0 = 64'd0; + +assign l1_filter_data_3_d1 = 64'd0; + +assign l1_filter_data_3_we0 = 1'b0; + +assign l1_filter_data_3_we1 = 1'b0; + +assign l2_adjustments_address0 = dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_address0; + +assign l2_adjustments_address1 = 7'd0; + +assign l2_adjustments_ce0 = dataflow_in_loop_TOP_LOOP47773_U0_l2_adjustments_ce0; + +assign l2_adjustments_ce1 = 1'b0; + +assign l2_adjustments_d0 = 48'd0; + +assign l2_adjustments_d1 = 48'd0; + +assign l2_adjustments_we0 = 1'b0; + +assign l2_adjustments_we1 = 1'b0; + +assign l2_filter_data_0_address0 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_address0; + +assign l2_filter_data_0_address1 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_address1; + +assign l2_filter_data_0_ce0 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_ce0; + +assign l2_filter_data_0_ce1 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_0_ce1; + +assign l2_filter_data_0_d0 = 16'd0; + +assign l2_filter_data_0_d1 = 16'd0; + +assign l2_filter_data_0_we0 = 1'b0; + +assign l2_filter_data_0_we1 = 1'b0; + +assign l2_filter_data_1_address0 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_address0; + +assign l2_filter_data_1_address1 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_address1; + +assign l2_filter_data_1_ce0 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_ce0; + +assign l2_filter_data_1_ce1 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_1_ce1; + +assign l2_filter_data_1_d0 = 16'd0; + +assign l2_filter_data_1_d1 = 16'd0; + +assign l2_filter_data_1_we0 = 1'b0; + +assign l2_filter_data_1_we1 = 1'b0; + +assign l2_filter_data_2_address0 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_address0; + +assign l2_filter_data_2_address1 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_address1; + +assign l2_filter_data_2_ce0 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_ce0; + +assign l2_filter_data_2_ce1 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_2_ce1; + +assign l2_filter_data_2_d0 = 16'd0; + +assign l2_filter_data_2_d1 = 16'd0; + +assign l2_filter_data_2_we0 = 1'b0; + +assign l2_filter_data_2_we1 = 1'b0; + +assign l2_filter_data_3_address0 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_address0; + +assign l2_filter_data_3_address1 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_address1; + +assign l2_filter_data_3_ce0 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_ce0; + +assign l2_filter_data_3_ce1 = dataflow_in_loop_TOP_LOOP47773_U0_l2_filter_data_3_ce1; + +assign l2_filter_data_3_d0 = 16'd0; + +assign l2_filter_data_3_d1 = 16'd0; + +assign l2_filter_data_3_we0 = 1'b0; + +assign l2_filter_data_3_we1 = 1'b0; + +assign out_data_address0 = 13'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP47773_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP47773_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP47773_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP47773_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP47773_U0_out_data_write; + +endmodule //td_fused_top_tdf11_14 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_in1_address0, + accum_in1_ce0, + accum_in1_q0, + accum_in1_address1, + accum_in1_ce1, + accum_in1_q1, + accum_in2_address0, + accum_in2_ce0, + accum_in2_q0, + accum_in2_address1, + accum_in2_ce1, + accum_in2_q1, + accum_in3_address0, + accum_in3_ce0, + accum_in3_q0, + accum_in3_address1, + accum_in3_ce1, + accum_in3_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_pp0_stage0 = 11'd2; +parameter ap_ST_fsm_pp0_stage1 = 11'd4; +parameter ap_ST_fsm_pp0_stage2 = 11'd8; +parameter ap_ST_fsm_pp0_stage3 = 11'd16; +parameter ap_ST_fsm_pp0_stage4 = 11'd32; +parameter ap_ST_fsm_pp0_stage5 = 11'd64; +parameter ap_ST_fsm_pp0_stage6 = 11'd128; +parameter ap_ST_fsm_state18 = 11'd256; +parameter ap_ST_fsm_pp1_stage0 = 11'd512; +parameter ap_ST_fsm_state21 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [7:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [7:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [7:0] accum_in1_address0; +output accum_in1_ce0; +input [15:0] accum_in1_q0; +output [7:0] accum_in1_address1; +output accum_in1_ce1; +input [15:0] accum_in1_q1; +output [7:0] accum_in2_address0; +output accum_in2_ce0; +input [15:0] accum_in2_q0; +output [7:0] accum_in2_address1; +output accum_in2_ce1; +input [15:0] accum_in2_q1; +output [7:0] accum_in3_address0; +output accum_in3_ce0; +input [15:0] accum_in3_q0; +output [7:0] accum_in3_address1; +output accum_in3_ce1; +input [15:0] accum_in3_q1; +output [4:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [4:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[7:0] accum_in_address0; +reg accum_in_ce0; +reg[7:0] accum_in_address1; +reg accum_in_ce1; +reg[7:0] accum_in1_address0; +reg accum_in1_ce0; +reg[7:0] accum_in1_address1; +reg accum_in1_ce1; +reg[7:0] accum_in2_address0; +reg accum_in2_ce0; +reg[7:0] accum_in2_address1; +reg accum_in2_ce1; +reg[7:0] accum_in3_address0; +reg accum_in3_ce0; +reg[7:0] accum_in3_address1; +reg accum_in3_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [9:0] x_reg_447; +reg [15:0] psum_4_05_reg_459; +reg [15:0] psum_3_04_reg_471; +reg [15:0] psum_2_03_reg_483; +reg [15:0] psum_1_02_reg_495; +reg [15:0] psum_0_01_reg_507; +reg [15:0] psum_9_010_reg_519; +reg [15:0] psum_8_09_reg_531; +reg [15:0] psum_7_08_reg_543; +reg [15:0] psum_6_07_reg_555; +reg [15:0] psum_5_06_reg_567; +reg [15:0] psum_31_032_reg_579; +reg [15:0] psum_30_031_reg_591; +reg [15:0] psum_29_030_reg_603; +reg [15:0] psum_28_029_reg_615; +reg [15:0] psum_27_028_reg_627; +reg [15:0] psum_26_027_reg_639; +reg [15:0] psum_25_026_reg_651; +reg [15:0] psum_24_025_reg_663; +reg [15:0] psum_23_024_reg_675; +reg [15:0] psum_22_023_reg_687; +reg [15:0] psum_21_022_reg_699; +reg [15:0] psum_20_021_reg_711; +reg [15:0] psum_19_020_reg_723; +reg [15:0] psum_18_019_reg_735; +reg [15:0] psum_17_018_reg_747; +reg [15:0] psum_16_017_reg_759; +reg [15:0] psum_15_016_reg_771; +reg [15:0] psum_14_015_reg_783; +reg [15:0] psum_13_014_reg_795; +reg [15:0] psum_12_013_reg_807; +reg [15:0] psum_11_012_reg_819; +reg [15:0] psum_10_011_reg_831; +reg [5:0] q_reg_843; +wire [0:0] icmp_ln132_fu_960_p2; +reg [0:0] icmp_ln132_reg_1322; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state9_pp0_stage0_iter1; +wire ap_block_state16_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln132_reg_1322_pp0_iter1_reg; +reg [0:0] icmp_ln132_reg_1322_pp0_iter2_reg; +wire [7:0] lshr_ln_fu_966_p4; +reg [7:0] lshr_ln_reg_1326; +reg [15:0] accum_in_load_reg_1376; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state10_pp0_stage1_iter1; +wire ap_block_state17_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in1_load_reg_1381; +reg [15:0] accum_in2_load_reg_1386; +reg [15:0] accum_in3_load_reg_1391; +reg [15:0] accum_in_load_50_reg_1396; +reg [15:0] accum_in1_load_29_reg_1401; +reg [15:0] accum_in2_load_15_reg_1406; +reg [15:0] accum_in3_load_15_reg_1411; +reg [15:0] accum_in_load_51_reg_1456; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state11_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in1_load_30_reg_1461; +reg [15:0] accum_in2_load_16_reg_1466; +reg [15:0] accum_in3_load_16_reg_1471; +reg [15:0] accum_in_load_52_reg_1476; +reg [15:0] accum_in1_load_31_reg_1481; +reg [15:0] accum_in2_load_17_reg_1486; +reg [15:0] accum_in3_load_17_reg_1491; +reg [15:0] accum_in_load_53_reg_1536; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state12_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in1_load_32_reg_1541; +reg [15:0] accum_in2_load_18_reg_1546; +reg [15:0] accum_in3_load_18_reg_1551; +reg [15:0] accum_in_load_54_reg_1556; +reg [15:0] accum_in1_load_33_reg_1561; +reg [15:0] accum_in2_load_19_reg_1566; +reg [15:0] accum_in3_load_19_reg_1571; +reg [15:0] accum_in_load_55_reg_1616; +wire ap_CS_fsm_pp0_stage4; +wire ap_block_state6_pp0_stage4_iter0; +wire ap_block_state13_pp0_stage4_iter1; +wire ap_block_pp0_stage4_11001; +reg [15:0] accum_in1_load_34_reg_1621; +reg [15:0] accum_in2_load_20_reg_1626; +reg [15:0] accum_in3_load_20_reg_1631; +reg [15:0] accum_in_load_56_reg_1636; +reg [15:0] accum_in1_load_35_reg_1641; +reg [15:0] accum_in2_load_21_reg_1646; +reg [15:0] accum_in3_load_21_reg_1651; +wire [9:0] add_ln132_fu_1076_p2; +reg [9:0] add_ln132_reg_1656; +wire ap_CS_fsm_pp0_stage6; +wire ap_block_state8_pp0_stage6_iter0; +wire ap_block_state15_pp0_stage6_iter1; +wire ap_block_pp0_stage6_11001; +wire [15:0] grp_fu_908_p2; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_913_p2; +wire [15:0] grp_fu_918_p2; +wire [15:0] grp_fu_923_p2; +wire [15:0] grp_fu_928_p2; +wire ap_CS_fsm_pp0_stage5; +wire ap_block_state7_pp0_stage5_iter0; +wire ap_block_state14_pp0_stage5_iter1; +wire ap_block_pp0_stage5_11001; +reg ap_enable_reg_pp0_iter2; +wire [0:0] tmp_fu_1082_p3; +reg [0:0] tmp_reg_1821; +wire ap_CS_fsm_pp1_stage0; +wire ap_block_state19_pp1_stage0_iter0; +wire ap_block_state20_pp1_stage0_iter1; +wire ap_block_pp1_stage0_11001; +wire [4:0] trunc_ln140_fu_1095_p1; +wire [5:0] add_ln140_fu_1099_p2; +reg ap_enable_reg_pp1_iter0; +wire [4:0] or_ln140_fu_1105_p2; +reg [4:0] or_ln140_reg_1834; +wire [15:0] select_ln152_39_fu_1271_p3; +reg [15:0] select_ln152_39_reg_1842; +reg ap_block_state1; +wire ap_block_pp0_stage4_subdone; +reg ap_condition_pp0_exit_iter0_state6; +wire ap_block_pp0_stage6_subdone; +wire ap_block_pp0_stage1_subdone; +wire ap_CS_fsm_state18; +wire ap_block_pp1_stage0_subdone; +reg ap_condition_pp1_exit_iter0_state19; +reg ap_enable_reg_pp1_iter1; +reg [9:0] ap_phi_mux_x_phi_fu_451_p4; +wire ap_block_pp0_stage0; +wire ap_block_pp0_stage2; +wire [15:0] ap_phi_mux_psum_9_010_phi_fu_523_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_8_09_phi_fu_535_p4; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_547_p4; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_559_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_571_p4; +wire [15:0] ap_phi_mux_psum_31_032_phi_fu_583_p4; +wire ap_block_pp0_stage1; +wire [15:0] ap_phi_mux_psum_30_031_phi_fu_595_p4; +wire [15:0] ap_phi_mux_psum_29_030_phi_fu_607_p4; +wire [15:0] ap_phi_mux_psum_28_029_phi_fu_619_p4; +wire [15:0] ap_phi_mux_psum_27_028_phi_fu_631_p4; +wire [15:0] ap_phi_mux_psum_26_027_phi_fu_643_p4; +wire [15:0] ap_phi_mux_psum_25_026_phi_fu_655_p4; +wire [15:0] ap_phi_mux_psum_24_025_phi_fu_667_p4; +wire ap_block_pp0_stage6; +wire [15:0] ap_phi_mux_psum_23_024_phi_fu_679_p4; +wire [15:0] ap_phi_mux_psum_22_023_phi_fu_691_p4; +wire [15:0] ap_phi_mux_psum_21_022_phi_fu_703_p4; +wire [15:0] ap_phi_mux_psum_20_021_phi_fu_715_p4; +wire [15:0] ap_phi_mux_psum_19_020_phi_fu_727_p4; +wire ap_block_pp0_stage5; +wire [15:0] ap_phi_mux_psum_18_019_phi_fu_739_p4; +wire [15:0] ap_phi_mux_psum_17_018_phi_fu_751_p4; +wire [15:0] ap_phi_mux_psum_16_017_phi_fu_763_p4; +wire [15:0] ap_phi_mux_psum_15_016_phi_fu_775_p4; +wire [15:0] ap_phi_mux_psum_14_015_phi_fu_787_p4; +wire ap_block_pp0_stage4; +wire [15:0] ap_phi_mux_psum_13_014_phi_fu_799_p4; +wire [15:0] ap_phi_mux_psum_12_013_phi_fu_811_p4; +wire [15:0] ap_phi_mux_psum_11_012_phi_fu_823_p4; +wire [15:0] ap_phi_mux_psum_10_011_phi_fu_835_p4; +reg [15:0] ap_phi_mux_phi_ln152_phi_fu_857_p32; +wire [15:0] ap_phi_reg_pp1_iter0_phi_ln152_reg_854; +wire [63:0] zext_ln136_fu_976_p1; +wire [63:0] zext_ln136_27_fu_990_p1; +wire [63:0] zext_ln136_28_fu_1003_p1; +wire [63:0] zext_ln136_29_fu_1016_p1; +wire [63:0] zext_ln136_30_fu_1029_p1; +wire [63:0] zext_ln136_31_fu_1042_p1; +wire [63:0] zext_ln136_32_fu_1055_p1; +wire [63:0] zext_ln136_33_fu_1068_p1; +wire [63:0] zext_ln140_fu_1090_p1; +wire ap_block_pp1_stage0; +wire [63:0] zext_ln140_3_fu_1279_p1; +reg [15:0] grp_fu_908_p0; +reg [15:0] grp_fu_908_p1; +reg [15:0] grp_fu_913_p0; +reg [15:0] grp_fu_913_p1; +reg [15:0] grp_fu_918_p0; +reg [15:0] grp_fu_918_p1; +reg [15:0] grp_fu_923_p0; +reg [15:0] grp_fu_923_p1; +reg [15:0] grp_fu_928_p0; +reg [15:0] grp_fu_928_p1; +wire [7:0] or_ln136_fu_984_p2; +wire [7:0] or_ln136_25_fu_998_p2; +wire [7:0] or_ln136_26_fu_1011_p2; +wire [7:0] or_ln136_27_fu_1024_p2; +wire [7:0] or_ln136_28_fu_1037_p2; +wire [7:0] or_ln136_29_fu_1050_p2; +wire [7:0] or_ln136_30_fu_1063_p2; +wire [0:0] icmp_ln152_fu_1111_p2; +wire [0:0] icmp_ln152_29_fu_1125_p2; +wire [15:0] select_ln152_fu_1117_p3; +wire [0:0] icmp_ln152_30_fu_1139_p2; +wire [15:0] select_ln152_29_fu_1131_p3; +wire [0:0] icmp_ln152_31_fu_1153_p2; +wire [15:0] select_ln152_30_fu_1145_p3; +wire [0:0] icmp_ln152_32_fu_1167_p2; +wire [15:0] select_ln152_31_fu_1159_p3; +wire [0:0] icmp_ln152_33_fu_1181_p2; +wire [15:0] select_ln152_32_fu_1173_p3; +wire [0:0] icmp_ln152_34_fu_1195_p2; +wire [15:0] select_ln152_33_fu_1187_p3; +wire [0:0] icmp_ln152_35_fu_1209_p2; +wire [15:0] select_ln152_34_fu_1201_p3; +wire [0:0] icmp_ln152_36_fu_1223_p2; +wire [15:0] select_ln152_35_fu_1215_p3; +wire [0:0] icmp_ln152_37_fu_1237_p2; +wire [15:0] select_ln152_36_fu_1229_p3; +wire [0:0] icmp_ln152_38_fu_1251_p2; +wire [15:0] select_ln152_37_fu_1243_p3; +wire [0:0] icmp_ln152_39_fu_1265_p2; +wire [15:0] select_ln152_38_fu_1257_p3; +wire [0:0] icmp_ln152_40_fu_1283_p2; +wire [0:0] icmp_ln152_41_fu_1295_p2; +wire [15:0] select_ln152_40_fu_1288_p3; +wire [0:0] icmp_ln152_42_fu_1308_p2; +wire [15:0] select_ln152_41_fu_1300_p3; +wire ap_CS_fsm_state21; +reg [10:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +wire ap_block_pp0_stage2_subdone; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage5_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_idle_pp1; +wire ap_enable_pp1; +reg ap_condition_1097; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp1_iter0 = 1'b0; +#0 ap_enable_reg_pp1_iter1 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1697( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_908_p0), + .din1(grp_fu_908_p1), + .dout(grp_fu_908_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1698( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_913_p0), + .din1(grp_fu_913_p1), + .dout(grp_fu_913_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1699( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_918_p0), + .din1(grp_fu_918_p1), + .dout(grp_fu_918_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1700( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_923_p0), + .din1(grp_fu_923_p1), + .dout(grp_fu_923_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1701( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_928_p0), + .din1(grp_fu_928_p1), + .dout(grp_fu_928_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state21)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state6) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6_subdone))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone)) | ((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6_subdone)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp1_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp1_exit_iter0_state19) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_subdone))) begin + ap_enable_reg_pp1_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state18)) begin + ap_enable_reg_pp1_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp1_iter1 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp1_exit_iter0_state19) & (1'b0 == ap_block_pp1_stage0_subdone))) begin + ap_enable_reg_pp1_iter1 <= (1'b1 ^ ap_condition_pp1_exit_iter0_state19); + end else if ((1'b0 == ap_block_pp1_stage0_subdone)) begin + ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0; + end else if ((1'b1 == ap_CS_fsm_state18)) begin + ap_enable_reg_pp1_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state18)) begin + q_reg_843 <= 6'd0; + end else if (((ap_enable_reg_pp1_iter0 == 1'b1) & (tmp_fu_1082_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + q_reg_843 <= add_ln140_fu_1099_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln132_reg_1322 == 1'd1))) begin + x_reg_447 <= add_ln132_reg_1656; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_447 <= 10'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln132_reg_1322 == 1'd1))) begin + accum_in1_load_29_reg_1401 <= accum_in1_q0; + accum_in1_load_reg_1381 <= accum_in1_q1; + accum_in2_load_15_reg_1406 <= accum_in2_q0; + accum_in2_load_reg_1386 <= accum_in2_q1; + accum_in3_load_15_reg_1411 <= accum_in3_q0; + accum_in3_load_reg_1391 <= accum_in3_q1; + accum_in_load_50_reg_1396 <= accum_in_q0; + accum_in_load_reg_1376 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (icmp_ln132_reg_1322 == 1'd1))) begin + accum_in1_load_30_reg_1461 <= accum_in1_q1; + accum_in1_load_31_reg_1481 <= accum_in1_q0; + accum_in2_load_16_reg_1466 <= accum_in2_q1; + accum_in2_load_17_reg_1486 <= accum_in2_q0; + accum_in3_load_16_reg_1471 <= accum_in3_q1; + accum_in3_load_17_reg_1491 <= accum_in3_q0; + accum_in_load_51_reg_1456 <= accum_in_q1; + accum_in_load_52_reg_1476 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (icmp_ln132_reg_1322 == 1'd1))) begin + accum_in1_load_32_reg_1541 <= accum_in1_q1; + accum_in1_load_33_reg_1561 <= accum_in1_q0; + accum_in2_load_18_reg_1546 <= accum_in2_q1; + accum_in2_load_19_reg_1566 <= accum_in2_q0; + accum_in3_load_18_reg_1551 <= accum_in3_q1; + accum_in3_load_19_reg_1571 <= accum_in3_q0; + accum_in_load_53_reg_1536 <= accum_in_q1; + accum_in_load_54_reg_1556 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4_11001) & (icmp_ln132_reg_1322 == 1'd1))) begin + accum_in1_load_34_reg_1621 <= accum_in1_q1; + accum_in1_load_35_reg_1641 <= accum_in1_q0; + accum_in2_load_20_reg_1626 <= accum_in2_q1; + accum_in2_load_21_reg_1646 <= accum_in2_q0; + accum_in3_load_20_reg_1631 <= accum_in3_q1; + accum_in3_load_21_reg_1651 <= accum_in3_q0; + accum_in_load_55_reg_1616 <= accum_in_q1; + accum_in_load_56_reg_1636 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6_11001) & (icmp_ln132_reg_1322 == 1'd1))) begin + add_ln132_reg_1656 <= add_ln132_fu_1076_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln132_reg_1322 <= icmp_ln132_fu_960_p2; + icmp_ln132_reg_1322_pp0_iter1_reg <= icmp_ln132_reg_1322; + icmp_ln132_reg_1322_pp0_iter2_reg <= icmp_ln132_reg_1322_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln132_fu_960_p2 == 1'd1))) begin + lshr_ln_reg_1326 <= {{ap_phi_mux_x_phi_fu_451_p4[9:2]}}; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_fu_1082_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + or_ln140_reg_1834[4 : 1] <= or_ln140_fu_1105_p2[4 : 1]; + select_ln152_39_reg_1842 <= select_ln152_39_fu_1271_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (icmp_ln132_reg_1322_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage2_11001))) begin + psum_0_01_reg_507 <= grp_fu_908_p2; + psum_1_02_reg_495 <= grp_fu_913_p2; + psum_2_03_reg_483 <= grp_fu_918_p2; + psum_3_04_reg_471 <= grp_fu_923_p2; + psum_4_05_reg_459 <= grp_fu_928_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (icmp_ln132_reg_1322_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage4_11001))) begin + psum_10_011_reg_831 <= grp_fu_908_p2; + psum_11_012_reg_819 <= grp_fu_913_p2; + psum_12_013_reg_807 <= grp_fu_918_p2; + psum_13_014_reg_795 <= grp_fu_923_p2; + psum_14_015_reg_783 <= grp_fu_928_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (icmp_ln132_reg_1322_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage5_11001))) begin + psum_15_016_reg_771 <= grp_fu_908_p2; + psum_16_017_reg_759 <= grp_fu_913_p2; + psum_17_018_reg_747 <= grp_fu_918_p2; + psum_18_019_reg_735 <= grp_fu_923_p2; + psum_19_020_reg_723 <= grp_fu_928_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage6) & (icmp_ln132_reg_1322_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage6_11001))) begin + psum_20_021_reg_711 <= grp_fu_908_p2; + psum_21_022_reg_699 <= grp_fu_913_p2; + psum_22_023_reg_687 <= grp_fu_918_p2; + psum_23_024_reg_675 <= grp_fu_923_p2; + psum_24_025_reg_663 <= grp_fu_928_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln132_reg_1322_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + psum_25_026_reg_651 <= grp_fu_908_p2; + psum_26_027_reg_639 <= grp_fu_913_p2; + psum_27_028_reg_627 <= grp_fu_918_p2; + psum_28_029_reg_615 <= grp_fu_923_p2; + psum_29_030_reg_603 <= grp_fu_928_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln132_reg_1322_pp0_iter2_reg == 1'd1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + psum_30_031_reg_591 <= grp_fu_908_p2; + psum_31_032_reg_579 <= grp_fu_913_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (icmp_ln132_reg_1322_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + psum_5_06_reg_567 <= grp_fu_908_p2; + psum_6_07_reg_555 <= grp_fu_913_p2; + psum_7_08_reg_543 <= grp_fu_918_p2; + psum_8_09_reg_531 <= grp_fu_923_p2; + psum_9_010_reg_519 <= grp_fu_928_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + tmp_reg_1821 <= q_reg_843[32'd5]; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in1_address0 = zext_ln136_33_fu_1068_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in1_address0 = zext_ln136_31_fu_1042_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in1_address0 = zext_ln136_29_fu_1016_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in1_address0 = zext_ln136_27_fu_990_p1; + end else begin + accum_in1_address0 = 'bx; + end + end else begin + accum_in1_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in1_address1 = zext_ln136_32_fu_1055_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in1_address1 = zext_ln136_30_fu_1029_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in1_address1 = zext_ln136_28_fu_1003_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in1_address1 = zext_ln136_fu_976_p1; + end else begin + accum_in1_address1 = 'bx; + end + end else begin + accum_in1_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in1_ce0 = 1'b1; + end else begin + accum_in1_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in1_ce1 = 1'b1; + end else begin + accum_in1_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in2_address0 = zext_ln136_33_fu_1068_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in2_address0 = zext_ln136_31_fu_1042_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in2_address0 = zext_ln136_29_fu_1016_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in2_address0 = zext_ln136_27_fu_990_p1; + end else begin + accum_in2_address0 = 'bx; + end + end else begin + accum_in2_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in2_address1 = zext_ln136_32_fu_1055_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in2_address1 = zext_ln136_30_fu_1029_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in2_address1 = zext_ln136_28_fu_1003_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in2_address1 = zext_ln136_fu_976_p1; + end else begin + accum_in2_address1 = 'bx; + end + end else begin + accum_in2_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in2_ce0 = 1'b1; + end else begin + accum_in2_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in2_ce1 = 1'b1; + end else begin + accum_in2_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in3_address0 = zext_ln136_33_fu_1068_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in3_address0 = zext_ln136_31_fu_1042_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in3_address0 = zext_ln136_29_fu_1016_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in3_address0 = zext_ln136_27_fu_990_p1; + end else begin + accum_in3_address0 = 'bx; + end + end else begin + accum_in3_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in3_address1 = zext_ln136_32_fu_1055_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in3_address1 = zext_ln136_30_fu_1029_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in3_address1 = zext_ln136_28_fu_1003_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in3_address1 = zext_ln136_fu_976_p1; + end else begin + accum_in3_address1 = 'bx; + end + end else begin + accum_in3_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in3_ce0 = 1'b1; + end else begin + accum_in3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in3_ce1 = 1'b1; + end else begin + accum_in3_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in_address0 = zext_ln136_33_fu_1068_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in_address0 = zext_ln136_31_fu_1042_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in_address0 = zext_ln136_29_fu_1016_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in_address0 = zext_ln136_27_fu_990_p1; + end else begin + accum_in_address0 = 'bx; + end + end else begin + accum_in_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in_address1 = zext_ln136_32_fu_1055_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in_address1 = zext_ln136_30_fu_1029_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in_address1 = zext_ln136_28_fu_1003_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in_address1 = zext_ln136_fu_976_p1; + end else begin + accum_in_address1 = 'bx; + end + end else begin + accum_in_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp1_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp1_iter1 == 1'b1) & (tmp_reg_1821 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp1_iter0 == 1'b1) & (tmp_fu_1082_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln132_reg_1322 == 1'd0)) begin + ap_condition_pp0_exit_iter0_state6 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state6 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_fu_1082_p3 == 1'd1)) begin + ap_condition_pp1_exit_iter0_state19 = 1'b1; + end else begin + ap_condition_pp1_exit_iter0_state19 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state21)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b0))) begin + ap_idle_pp1 = 1'b1; + end else begin + ap_idle_pp1 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_fu_1082_p3 == 1'd0)) begin + if ((trunc_ln140_fu_1095_p1 == 5'd0)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_0_01_reg_507; + end else if ((1'b1 == ap_condition_1097)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_30_031_reg_591; + end else if ((trunc_ln140_fu_1095_p1 == 5'd28)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_28_029_reg_615; + end else if ((trunc_ln140_fu_1095_p1 == 5'd26)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_26_027_reg_639; + end else if ((trunc_ln140_fu_1095_p1 == 5'd24)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_24_025_reg_663; + end else if ((trunc_ln140_fu_1095_p1 == 5'd22)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_22_023_reg_687; + end else if ((trunc_ln140_fu_1095_p1 == 5'd20)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_20_021_reg_711; + end else if ((trunc_ln140_fu_1095_p1 == 5'd18)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_18_019_reg_735; + end else if ((trunc_ln140_fu_1095_p1 == 5'd16)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_16_017_reg_759; + end else if ((trunc_ln140_fu_1095_p1 == 5'd14)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_14_015_reg_783; + end else if ((trunc_ln140_fu_1095_p1 == 5'd12)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_12_013_reg_807; + end else if ((trunc_ln140_fu_1095_p1 == 5'd10)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_10_011_reg_831; + end else if ((trunc_ln140_fu_1095_p1 == 5'd8)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_8_09_reg_531; + end else if ((trunc_ln140_fu_1095_p1 == 5'd6)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_6_07_reg_555; + end else if ((trunc_ln140_fu_1095_p1 == 5'd4)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_4_05_reg_459; + end else if ((trunc_ln140_fu_1095_p1 == 5'd2)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_2_03_reg_483; + end else begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = ap_phi_reg_pp1_iter0_phi_ln152_reg_854; + end + end else begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = ap_phi_reg_pp1_iter0_phi_ln152_reg_854; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0) & (icmp_ln132_reg_1322 == 1'd1))) begin + ap_phi_mux_x_phi_fu_451_p4 = add_ln132_reg_1656; + end else begin + ap_phi_mux_x_phi_fu_451_p4 = x_reg_447; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state21)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + grp_fu_908_p0 = ap_phi_mux_psum_30_031_phi_fu_595_p4; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_908_p0 = ap_phi_mux_psum_25_026_phi_fu_655_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_908_p0 = ap_phi_mux_psum_20_021_phi_fu_715_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_908_p0 = ap_phi_mux_psum_15_016_phi_fu_775_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_908_p0 = ap_phi_mux_psum_10_011_phi_fu_835_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_908_p0 = ap_phi_mux_psum_5_06_phi_fu_571_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_908_p0 = grp_fu_908_p2; + end else begin + grp_fu_908_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + grp_fu_908_p1 = accum_in2_load_21_reg_1646; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_908_p1 = accum_in1_load_34_reg_1621; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_908_p1 = accum_in_load_54_reg_1556; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_908_p1 = accum_in3_load_17_reg_1491; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_908_p1 = accum_in2_load_16_reg_1466; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_908_p1 = accum_in1_load_29_reg_1401; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_908_p1 = accum_in_load_reg_1376; + end else begin + grp_fu_908_p1 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + grp_fu_913_p0 = ap_phi_mux_psum_31_032_phi_fu_583_p4; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_913_p0 = ap_phi_mux_psum_26_027_phi_fu_643_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_913_p0 = ap_phi_mux_psum_21_022_phi_fu_703_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_913_p0 = ap_phi_mux_psum_16_017_phi_fu_763_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_913_p0 = ap_phi_mux_psum_11_012_phi_fu_823_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_913_p0 = ap_phi_mux_psum_6_07_phi_fu_559_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_913_p0 = grp_fu_913_p2; + end else begin + grp_fu_913_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + grp_fu_913_p1 = accum_in3_load_21_reg_1651; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_913_p1 = accum_in2_load_20_reg_1626; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_913_p1 = accum_in1_load_33_reg_1561; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_913_p1 = accum_in_load_53_reg_1536; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_913_p1 = accum_in3_load_16_reg_1471; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_913_p1 = accum_in2_load_15_reg_1406; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_913_p1 = accum_in1_load_reg_1381; + end else begin + grp_fu_913_p1 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_918_p0 = ap_phi_mux_psum_27_028_phi_fu_631_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_918_p0 = ap_phi_mux_psum_22_023_phi_fu_691_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_918_p0 = ap_phi_mux_psum_17_018_phi_fu_751_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_918_p0 = ap_phi_mux_psum_12_013_phi_fu_811_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_918_p0 = ap_phi_mux_psum_7_08_phi_fu_547_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_918_p0 = grp_fu_918_p2; + end else begin + grp_fu_918_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_918_p1 = accum_in3_load_20_reg_1631; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_918_p1 = accum_in2_load_19_reg_1566; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_918_p1 = accum_in1_load_32_reg_1541; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_918_p1 = accum_in_load_52_reg_1476; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_918_p1 = accum_in3_load_15_reg_1411; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_918_p1 = accum_in2_load_reg_1386; + end else begin + grp_fu_918_p1 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_923_p0 = ap_phi_mux_psum_28_029_phi_fu_619_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_923_p0 = ap_phi_mux_psum_23_024_phi_fu_679_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_923_p0 = ap_phi_mux_psum_18_019_phi_fu_739_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_923_p0 = ap_phi_mux_psum_13_014_phi_fu_799_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_923_p0 = ap_phi_mux_psum_8_09_phi_fu_535_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_923_p0 = grp_fu_923_p2; + end else begin + grp_fu_923_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_923_p1 = accum_in_load_56_reg_1636; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_923_p1 = accum_in3_load_19_reg_1571; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_923_p1 = accum_in2_load_18_reg_1546; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_923_p1 = accum_in1_load_31_reg_1481; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_923_p1 = accum_in_load_51_reg_1456; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_923_p1 = accum_in3_load_reg_1391; + end else begin + grp_fu_923_p1 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_928_p0 = ap_phi_mux_psum_29_030_phi_fu_607_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_928_p0 = ap_phi_mux_psum_24_025_phi_fu_667_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_928_p0 = ap_phi_mux_psum_19_020_phi_fu_727_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_928_p0 = ap_phi_mux_psum_14_015_phi_fu_787_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_928_p0 = ap_phi_mux_psum_9_010_phi_fu_523_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_928_p0 = grp_fu_928_p2; + end else begin + grp_fu_928_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_928_p1 = accum_in1_load_35_reg_1641; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_928_p1 = accum_in_load_55_reg_1616; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_928_p1 = accum_in3_load_18_reg_1551; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_928_p1 = accum_in2_load_17_reg_1486; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_928_p1 = accum_in1_load_30_reg_1461; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_928_p1 = accum_in_load_50_reg_1396; + end else begin + grp_fu_928_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state18; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((1'b0 == ap_block_pp0_stage2_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_pp0_stage4 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4_subdone) & (icmp_ln132_reg_1322 == 1'd0)) & (1'b0 == ap_block_pp0_stage4_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end else if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4_subdone) & (icmp_ln132_reg_1322 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state18; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end + end + ap_ST_fsm_pp0_stage5 : begin + if ((1'b0 == ap_block_pp0_stage5_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end + end + ap_ST_fsm_pp0_stage6 : begin + if ((1'b0 == ap_block_pp0_stage6_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end + end + ap_ST_fsm_state18 : begin + ap_NS_fsm = ap_ST_fsm_pp1_stage0; + end + ap_ST_fsm_pp1_stage0 : begin + if (~((ap_enable_reg_pp1_iter0 == 1'b1) & (tmp_fu_1082_p3 == 1'd1) & (1'b0 == ap_block_pp1_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp1_stage0; + end else if (((ap_enable_reg_pp1_iter0 == 1'b1) & (tmp_fu_1082_p3 == 1'd1) & (1'b0 == ap_block_pp1_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state21; + end else begin + ap_NS_fsm = ap_ST_fsm_pp1_stage0; + end + end + ap_ST_fsm_state21 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln140_3_fu_1279_p1; + +assign accum_out_address1 = zext_ln140_fu_1090_p1; + +assign accum_out_d0 = ((icmp_ln152_42_fu_1308_p2[0:0] == 1'b1) ? psum_29_030_reg_603 : select_ln152_41_fu_1300_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln152_phi_fu_857_p32; + +assign add_ln132_fu_1076_p2 = (x_reg_447 + 10'd32); + +assign add_ln140_fu_1099_p2 = (q_reg_843 + 6'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_pp1_stage0 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state18 = ap_CS_fsm[32'd8]; + +assign ap_CS_fsm_state21 = ap_CS_fsm[32'd10]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp1_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp1_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp1_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage4_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage5_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage6_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp1_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp1_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_1097 = (~(trunc_ln140_fu_1095_p1 == 5'd0) & ~(trunc_ln140_fu_1095_p1 == 5'd28) & ~(trunc_ln140_fu_1095_p1 == 5'd26) & ~(trunc_ln140_fu_1095_p1 == 5'd24) & ~(trunc_ln140_fu_1095_p1 == 5'd22) & ~(trunc_ln140_fu_1095_p1 == 5'd20) & ~(trunc_ln140_fu_1095_p1 == 5'd18) & ~(trunc_ln140_fu_1095_p1 == 5'd16) & ~(trunc_ln140_fu_1095_p1 == 5'd14) & ~(trunc_ln140_fu_1095_p1 == 5'd12) & ~(trunc_ln140_fu_1095_p1 == 5'd10) & ~(trunc_ln140_fu_1095_p1 == 5'd8) & ~(trunc_ln140_fu_1095_p1 == 5'd6) & ~(trunc_ln140_fu_1095_p1 == 5'd4) & ~(trunc_ln140_fu_1095_p1 == 5'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_enable_pp1 = (ap_idle_pp1 ^ 1'b1); + +assign ap_phi_mux_psum_10_011_phi_fu_835_p4 = grp_fu_908_p2; + +assign ap_phi_mux_psum_11_012_phi_fu_823_p4 = grp_fu_913_p2; + +assign ap_phi_mux_psum_12_013_phi_fu_811_p4 = grp_fu_918_p2; + +assign ap_phi_mux_psum_13_014_phi_fu_799_p4 = grp_fu_923_p2; + +assign ap_phi_mux_psum_14_015_phi_fu_787_p4 = grp_fu_928_p2; + +assign ap_phi_mux_psum_15_016_phi_fu_775_p4 = grp_fu_908_p2; + +assign ap_phi_mux_psum_16_017_phi_fu_763_p4 = grp_fu_913_p2; + +assign ap_phi_mux_psum_17_018_phi_fu_751_p4 = grp_fu_918_p2; + +assign ap_phi_mux_psum_18_019_phi_fu_739_p4 = grp_fu_923_p2; + +assign ap_phi_mux_psum_19_020_phi_fu_727_p4 = grp_fu_928_p2; + +assign ap_phi_mux_psum_20_021_phi_fu_715_p4 = grp_fu_908_p2; + +assign ap_phi_mux_psum_21_022_phi_fu_703_p4 = grp_fu_913_p2; + +assign ap_phi_mux_psum_22_023_phi_fu_691_p4 = grp_fu_918_p2; + +assign ap_phi_mux_psum_23_024_phi_fu_679_p4 = grp_fu_923_p2; + +assign ap_phi_mux_psum_24_025_phi_fu_667_p4 = grp_fu_928_p2; + +assign ap_phi_mux_psum_25_026_phi_fu_655_p4 = grp_fu_908_p2; + +assign ap_phi_mux_psum_26_027_phi_fu_643_p4 = grp_fu_913_p2; + +assign ap_phi_mux_psum_27_028_phi_fu_631_p4 = grp_fu_918_p2; + +assign ap_phi_mux_psum_28_029_phi_fu_619_p4 = grp_fu_923_p2; + +assign ap_phi_mux_psum_29_030_phi_fu_607_p4 = grp_fu_928_p2; + +assign ap_phi_mux_psum_30_031_phi_fu_595_p4 = grp_fu_908_p2; + +assign ap_phi_mux_psum_31_032_phi_fu_583_p4 = grp_fu_913_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_571_p4 = grp_fu_908_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_559_p4 = grp_fu_913_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_547_p4 = grp_fu_918_p2; + +assign ap_phi_mux_psum_8_09_phi_fu_535_p4 = grp_fu_923_p2; + +assign ap_phi_mux_psum_9_010_phi_fu_523_p4 = grp_fu_928_p2; + +assign ap_phi_reg_pp1_iter0_phi_ln152_reg_854 = 'bx; + +assign icmp_ln132_fu_960_p2 = ((ap_phi_mux_x_phi_fu_451_p4 < 10'd576) ? 1'b1 : 1'b0); + +assign icmp_ln152_29_fu_1125_p2 = ((or_ln140_fu_1105_p2 == 5'd3) ? 1'b1 : 1'b0); + +assign icmp_ln152_30_fu_1139_p2 = ((or_ln140_fu_1105_p2 == 5'd5) ? 1'b1 : 1'b0); + +assign icmp_ln152_31_fu_1153_p2 = ((or_ln140_fu_1105_p2 == 5'd7) ? 1'b1 : 1'b0); + +assign icmp_ln152_32_fu_1167_p2 = ((or_ln140_fu_1105_p2 == 5'd9) ? 1'b1 : 1'b0); + +assign icmp_ln152_33_fu_1181_p2 = ((or_ln140_fu_1105_p2 == 5'd11) ? 1'b1 : 1'b0); + +assign icmp_ln152_34_fu_1195_p2 = ((or_ln140_fu_1105_p2 == 5'd13) ? 1'b1 : 1'b0); + +assign icmp_ln152_35_fu_1209_p2 = ((or_ln140_fu_1105_p2 == 5'd15) ? 1'b1 : 1'b0); + +assign icmp_ln152_36_fu_1223_p2 = ((or_ln140_fu_1105_p2 == 5'd17) ? 1'b1 : 1'b0); + +assign icmp_ln152_37_fu_1237_p2 = ((or_ln140_fu_1105_p2 == 5'd19) ? 1'b1 : 1'b0); + +assign icmp_ln152_38_fu_1251_p2 = ((or_ln140_fu_1105_p2 == 5'd21) ? 1'b1 : 1'b0); + +assign icmp_ln152_39_fu_1265_p2 = ((or_ln140_fu_1105_p2 == 5'd23) ? 1'b1 : 1'b0); + +assign icmp_ln152_40_fu_1283_p2 = ((or_ln140_reg_1834 == 5'd25) ? 1'b1 : 1'b0); + +assign icmp_ln152_41_fu_1295_p2 = ((or_ln140_reg_1834 == 5'd27) ? 1'b1 : 1'b0); + +assign icmp_ln152_42_fu_1308_p2 = ((or_ln140_reg_1834 == 5'd29) ? 1'b1 : 1'b0); + +assign icmp_ln152_fu_1111_p2 = ((or_ln140_fu_1105_p2 == 5'd1) ? 1'b1 : 1'b0); + +assign lshr_ln_fu_966_p4 = {{ap_phi_mux_x_phi_fu_451_p4[9:2]}}; + +assign or_ln136_25_fu_998_p2 = (lshr_ln_reg_1326 | 8'd2); + +assign or_ln136_26_fu_1011_p2 = (lshr_ln_reg_1326 | 8'd3); + +assign or_ln136_27_fu_1024_p2 = (lshr_ln_reg_1326 | 8'd4); + +assign or_ln136_28_fu_1037_p2 = (lshr_ln_reg_1326 | 8'd5); + +assign or_ln136_29_fu_1050_p2 = (lshr_ln_reg_1326 | 8'd6); + +assign or_ln136_30_fu_1063_p2 = (lshr_ln_reg_1326 | 8'd7); + +assign or_ln136_fu_984_p2 = (lshr_ln_fu_966_p4 | 8'd1); + +assign or_ln140_fu_1105_p2 = (trunc_ln140_fu_1095_p1 | 5'd1); + +assign select_ln152_29_fu_1131_p3 = ((icmp_ln152_29_fu_1125_p2[0:0] == 1'b1) ? psum_3_04_reg_471 : select_ln152_fu_1117_p3); + +assign select_ln152_30_fu_1145_p3 = ((icmp_ln152_30_fu_1139_p2[0:0] == 1'b1) ? psum_5_06_reg_567 : select_ln152_29_fu_1131_p3); + +assign select_ln152_31_fu_1159_p3 = ((icmp_ln152_31_fu_1153_p2[0:0] == 1'b1) ? psum_7_08_reg_543 : select_ln152_30_fu_1145_p3); + +assign select_ln152_32_fu_1173_p3 = ((icmp_ln152_32_fu_1167_p2[0:0] == 1'b1) ? psum_9_010_reg_519 : select_ln152_31_fu_1159_p3); + +assign select_ln152_33_fu_1187_p3 = ((icmp_ln152_33_fu_1181_p2[0:0] == 1'b1) ? psum_11_012_reg_819 : select_ln152_32_fu_1173_p3); + +assign select_ln152_34_fu_1201_p3 = ((icmp_ln152_34_fu_1195_p2[0:0] == 1'b1) ? psum_13_014_reg_795 : select_ln152_33_fu_1187_p3); + +assign select_ln152_35_fu_1215_p3 = ((icmp_ln152_35_fu_1209_p2[0:0] == 1'b1) ? psum_15_016_reg_771 : select_ln152_34_fu_1201_p3); + +assign select_ln152_36_fu_1229_p3 = ((icmp_ln152_36_fu_1223_p2[0:0] == 1'b1) ? psum_17_018_reg_747 : select_ln152_35_fu_1215_p3); + +assign select_ln152_37_fu_1243_p3 = ((icmp_ln152_37_fu_1237_p2[0:0] == 1'b1) ? psum_19_020_reg_723 : select_ln152_36_fu_1229_p3); + +assign select_ln152_38_fu_1257_p3 = ((icmp_ln152_38_fu_1251_p2[0:0] == 1'b1) ? psum_21_022_reg_699 : select_ln152_37_fu_1243_p3); + +assign select_ln152_39_fu_1271_p3 = ((icmp_ln152_39_fu_1265_p2[0:0] == 1'b1) ? psum_23_024_reg_675 : select_ln152_38_fu_1257_p3); + +assign select_ln152_40_fu_1288_p3 = ((icmp_ln152_40_fu_1283_p2[0:0] == 1'b1) ? psum_25_026_reg_651 : select_ln152_39_reg_1842); + +assign select_ln152_41_fu_1300_p3 = ((icmp_ln152_41_fu_1295_p2[0:0] == 1'b1) ? psum_27_028_reg_627 : select_ln152_40_fu_1288_p3); + +assign select_ln152_fu_1117_p3 = ((icmp_ln152_fu_1111_p2[0:0] == 1'b1) ? psum_1_02_reg_495 : psum_31_032_reg_579); + +assign tmp_fu_1082_p3 = q_reg_843[32'd5]; + +assign trunc_ln140_fu_1095_p1 = q_reg_843[4:0]; + +assign zext_ln136_27_fu_990_p1 = or_ln136_fu_984_p2; + +assign zext_ln136_28_fu_1003_p1 = or_ln136_25_fu_998_p2; + +assign zext_ln136_29_fu_1016_p1 = or_ln136_26_fu_1011_p2; + +assign zext_ln136_30_fu_1029_p1 = or_ln136_27_fu_1024_p2; + +assign zext_ln136_31_fu_1042_p1 = or_ln136_28_fu_1037_p2; + +assign zext_ln136_32_fu_1055_p1 = or_ln136_29_fu_1050_p2; + +assign zext_ln136_33_fu_1068_p1 = or_ln136_30_fu_1063_p2; + +assign zext_ln136_fu_976_p1 = lshr_ln_fu_966_p4; + +assign zext_ln140_3_fu_1279_p1 = or_ln140_reg_1834; + +assign zext_ln140_fu_1090_p1 = q_reg_843; + +always @ (posedge ap_clk) begin + or_ln140_reg_1834[0] <= 1'b1; +end + +endmodule //td_fused_top_tdf11_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_pp0_stage0 = 11'd2; +parameter ap_ST_fsm_pp0_stage1 = 11'd4; +parameter ap_ST_fsm_pp0_stage2 = 11'd8; +parameter ap_ST_fsm_pp0_stage3 = 11'd16; +parameter ap_ST_fsm_pp0_stage4 = 11'd32; +parameter ap_ST_fsm_pp0_stage5 = 11'd64; +parameter ap_ST_fsm_pp0_stage6 = 11'd128; +parameter ap_ST_fsm_state15 = 11'd256; +parameter ap_ST_fsm_state16 = 11'd512; +parameter ap_ST_fsm_state17 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [4:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [4:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[4:0] accum_in_address0; +reg accum_in_ce0; +reg[4:0] accum_in_address1; +reg accum_in_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [5:0] x_reg_168; +reg [15:0] psum_7_0134_reg_180; +reg [15:0] psum_6_0133_reg_192; +reg [15:0] psum_5_0132_reg_204; +reg [15:0] psum_4_0131_reg_216; +reg [15:0] psum_3_0130_reg_228; +reg [15:0] psum_2_0129_reg_240; +reg [15:0] psum_1_0128_reg_252; +reg [15:0] psum_0_0127_reg_264; +wire [0:0] tmp_fu_321_p3; +reg [0:0] tmp_reg_492; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state9_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +reg [0:0] tmp_reg_492_pp0_iter1_reg; +wire [4:0] trunc_ln171_fu_334_p1; +reg [4:0] trunc_ln171_reg_496; +reg [15:0] accum_in_load_reg_516; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state10_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_load_43_reg_521; +reg [15:0] accum_in_load_44_reg_536; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state11_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_load_45_reg_541; +reg [15:0] accum_in_load_46_reg_556; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state12_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_load_47_reg_561; +reg [15:0] accum_in_load_48_reg_576; +wire ap_CS_fsm_pp0_stage4; +wire ap_block_state6_pp0_stage4_iter0; +wire ap_block_state13_pp0_stage4_iter1; +wire ap_block_pp0_stage4_11001; +reg [15:0] accum_in_load_49_reg_581; +wire [5:0] add_ln171_fu_409_p2; +reg [5:0] add_ln171_reg_586; +wire ap_CS_fsm_pp0_stage6; +wire ap_block_state8_pp0_stage6_iter0; +wire ap_block_pp0_stage6_11001; +wire [15:0] grp_fu_305_p2; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_310_p2; +wire ap_CS_fsm_pp0_stage5; +wire ap_block_state7_pp0_stage5_iter0; +wire ap_block_state14_pp0_stage5_iter1; +wire ap_block_pp0_stage5_11001; +wire [3:0] add_ln179_fu_432_p2; +wire ap_CS_fsm_state16; +wire [0:0] tmp_95_fu_415_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage6_subdone; +wire ap_block_pp0_stage5_subdone; +reg [5:0] ap_phi_mux_x_phi_fu_172_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_0134_phi_fu_184_p4; +wire ap_block_pp0_stage5; +wire [15:0] ap_phi_mux_psum_6_0133_phi_fu_196_p4; +wire [15:0] ap_phi_mux_psum_5_0132_phi_fu_208_p4; +wire ap_block_pp0_stage4; +wire [15:0] ap_phi_mux_psum_4_0131_phi_fu_220_p4; +wire [15:0] ap_phi_mux_psum_3_0130_phi_fu_232_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_0129_phi_fu_244_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_276; +wire ap_CS_fsm_state15; +reg [15:0] ap_phi_mux_phi_ln191_phi_fu_290_p8; +wire [2:0] trunc_ln179_fu_428_p1; +wire [63:0] zext_ln171_fu_329_p1; +wire [63:0] zext_ln175_fu_344_p1; +wire [63:0] zext_ln175_13_fu_354_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln175_14_fu_364_p1; +wire [63:0] zext_ln175_15_fu_374_p1; +wire [63:0] zext_ln175_16_fu_384_p1; +wire [63:0] zext_ln175_17_fu_394_p1; +wire [63:0] zext_ln175_18_fu_404_p1; +wire [63:0] zext_ln179_fu_423_p1; +wire [63:0] zext_ln179_3_fu_444_p1; +reg [15:0] grp_fu_305_p0; +reg [15:0] grp_fu_305_p1; +reg [15:0] grp_fu_310_p0; +reg [15:0] grp_fu_310_p1; +wire [4:0] or_ln175_fu_338_p2; +wire [4:0] or_ln175_13_fu_349_p2; +wire [4:0] or_ln175_14_fu_359_p2; +wire [4:0] or_ln175_15_fu_369_p2; +wire [4:0] or_ln175_16_fu_379_p2; +wire [4:0] or_ln175_17_fu_389_p2; +wire [4:0] or_ln175_18_fu_399_p2; +wire ap_block_pp0_stage6; +wire [2:0] or_ln179_fu_438_p2; +wire [0:0] icmp_ln191_fu_449_p2; +wire [0:0] icmp_ln191_5_fu_463_p2; +wire [15:0] select_ln191_fu_455_p3; +wire [0:0] icmp_ln191_6_fu_477_p2; +wire [15:0] select_ln191_5_fu_469_p3; +wire ap_CS_fsm_state17; +reg [10:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +wire ap_block_pp0_stage1_subdone; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage4_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_570; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1707( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_305_p0), + .din1(grp_fu_305_p1), + .dout(grp_fu_305_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1708( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_310_p0), + .din1(grp_fu_310_p1), + .dout(grp_fu_310_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage5_subdone) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0)) | ((1'b0 == ap_block_pp0_stage6_subdone) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state15)) begin + q_reg_276 <= 4'd0; + end else if (((tmp_95_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + q_reg_276 <= add_ln179_fu_432_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + x_reg_168 <= add_ln171_reg_586; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_168 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_load_43_reg_521 <= accum_in_q0; + accum_in_load_reg_516 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage2_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_load_44_reg_536 <= accum_in_q1; + accum_in_load_45_reg_541 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage3_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_load_46_reg_556 <= accum_in_q1; + accum_in_load_47_reg_561 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage4_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_load_48_reg_576 <= accum_in_q1; + accum_in_load_49_reg_581 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage6_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln171_reg_586 <= add_ln171_fu_409_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage2_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + psum_0_0127_reg_264 <= grp_fu_305_p2; + psum_1_0128_reg_252 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + psum_2_0129_reg_240 <= grp_fu_305_p2; + psum_3_0130_reg_228 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage4_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + psum_4_0131_reg_216 <= grp_fu_305_p2; + psum_5_0132_reg_204 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage5_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + psum_6_0133_reg_192 <= grp_fu_305_p2; + psum_7_0134_reg_180 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + tmp_reg_492 <= ap_phi_mux_x_phi_fu_172_p4[32'd5]; + tmp_reg_492_pp0_iter1_reg <= tmp_reg_492; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_fu_321_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln171_reg_496 <= trunc_ln171_fu_334_p1; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_address0 = zext_ln175_18_fu_404_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_address0 = zext_ln175_16_fu_384_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_address0 = zext_ln175_14_fu_364_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_address0 = zext_ln175_fu_344_p1; + end else begin + accum_in_address0 = 'bx; + end + end else begin + accum_in_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_address1 = zext_ln175_17_fu_394_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_address1 = zext_ln175_15_fu_374_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_address1 = zext_ln175_13_fu_354_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_address1 = zext_ln171_fu_329_p1; + end else begin + accum_in_address1 = 'bx; + end + end else begin + accum_in_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_95_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_95_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_reg_492 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_95_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + if ((trunc_ln179_fu_428_p1 == 3'd0)) begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = psum_0_0127_reg_264; + end else if ((1'b1 == ap_condition_570)) begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = psum_6_0133_reg_192; + end else if ((trunc_ln179_fu_428_p1 == 3'd4)) begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = psum_4_0131_reg_216; + end else if ((trunc_ln179_fu_428_p1 == 3'd2)) begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = psum_2_0129_reg_240; + end else begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (tmp_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_x_phi_fu_172_p4 = add_ln171_reg_586; + end else begin + ap_phi_mux_x_phi_fu_172_p4 = x_reg_168; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_305_p0 = ap_phi_mux_psum_6_0133_phi_fu_196_p4; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_305_p0 = ap_phi_mux_psum_4_0131_phi_fu_220_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p0 = ap_phi_mux_psum_2_0129_phi_fu_244_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p0 = grp_fu_305_p2; + end else begin + grp_fu_305_p0 = 'bx; + end + end else begin + grp_fu_305_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_305_p1 = accum_in_load_48_reg_576; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_305_p1 = accum_in_load_46_reg_556; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p1 = accum_in_load_44_reg_536; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p1 = accum_in_load_reg_516; + end else begin + grp_fu_305_p1 = 'bx; + end + end else begin + grp_fu_305_p1 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_310_p0 = ap_phi_mux_psum_7_0134_phi_fu_184_p4; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_310_p0 = ap_phi_mux_psum_5_0132_phi_fu_208_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p0 = ap_phi_mux_psum_3_0130_phi_fu_232_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p0 = grp_fu_310_p2; + end else begin + grp_fu_310_p0 = 'bx; + end + end else begin + grp_fu_310_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_310_p1 = accum_in_load_49_reg_581; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_310_p1 = accum_in_load_47_reg_561; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p1 = accum_in_load_45_reg_541; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p1 = accum_in_load_43_reg_521; + end else begin + grp_fu_310_p1 = 'bx; + end + end else begin + grp_fu_310_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_492 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_492 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state15; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_pp0_stage4 : begin + if ((1'b0 == ap_block_pp0_stage4_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end + end + ap_ST_fsm_pp0_stage5 : begin + if ((~((1'b0 == ap_block_pp0_stage5_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0)) & (1'b0 == ap_block_pp0_stage5_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end else if (((1'b0 == ap_block_pp0_stage5_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state15; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end + end + ap_ST_fsm_pp0_stage6 : begin + if ((1'b0 == ap_block_pp0_stage6_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + if (((tmp_95_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + ap_NS_fsm = ap_ST_fsm_state16; + end else begin + ap_NS_fsm = ap_ST_fsm_state17; + end + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln179_3_fu_444_p1; + +assign accum_out_address1 = zext_ln179_fu_423_p1; + +assign accum_out_d0 = ((icmp_ln191_6_fu_477_p2[0:0] == 1'b1) ? psum_5_0132_reg_204 : select_ln191_5_fu_469_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln191_phi_fu_290_p8; + +assign add_ln171_fu_409_p2 = (x_reg_168 + 6'd8); + +assign add_ln179_fu_432_p2 = (q_reg_276 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state15 = ap_CS_fsm[32'd8]; + +assign ap_CS_fsm_state16 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd10]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage4_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage5_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_570 = (~(trunc_ln179_fu_428_p1 == 3'd0) & ~(trunc_ln179_fu_428_p1 == 3'd4) & ~(trunc_ln179_fu_428_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_0129_phi_fu_244_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_3_0130_phi_fu_232_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_4_0131_phi_fu_220_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_5_0132_phi_fu_208_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_6_0133_phi_fu_196_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_7_0134_phi_fu_184_p4 = grp_fu_310_p2; + +assign icmp_ln191_5_fu_463_p2 = ((or_ln179_fu_438_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln191_6_fu_477_p2 = ((or_ln179_fu_438_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln191_fu_449_p2 = ((or_ln179_fu_438_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln175_13_fu_349_p2 = (trunc_ln171_reg_496 | 5'd2); + +assign or_ln175_14_fu_359_p2 = (trunc_ln171_reg_496 | 5'd3); + +assign or_ln175_15_fu_369_p2 = (trunc_ln171_reg_496 | 5'd4); + +assign or_ln175_16_fu_379_p2 = (trunc_ln171_reg_496 | 5'd5); + +assign or_ln175_17_fu_389_p2 = (trunc_ln171_reg_496 | 5'd6); + +assign or_ln175_18_fu_399_p2 = (trunc_ln171_reg_496 | 5'd7); + +assign or_ln175_fu_338_p2 = (trunc_ln171_fu_334_p1 | 5'd1); + +assign or_ln179_fu_438_p2 = (trunc_ln179_fu_428_p1 | 3'd1); + +assign select_ln191_5_fu_469_p3 = ((icmp_ln191_5_fu_463_p2[0:0] == 1'b1) ? psum_3_0130_reg_228 : select_ln191_fu_455_p3); + +assign select_ln191_fu_455_p3 = ((icmp_ln191_fu_449_p2[0:0] == 1'b1) ? psum_1_0128_reg_252 : psum_7_0134_reg_180); + +assign tmp_95_fu_415_p3 = q_reg_276[32'd3]; + +assign tmp_fu_321_p3 = ap_phi_mux_x_phi_fu_172_p4[32'd5]; + +assign trunc_ln171_fu_334_p1 = ap_phi_mux_x_phi_fu_172_p4[4:0]; + +assign trunc_ln179_fu_428_p1 = q_reg_276[2:0]; + +assign zext_ln171_fu_329_p1 = ap_phi_mux_x_phi_fu_172_p4; + +assign zext_ln175_13_fu_354_p1 = or_ln175_13_fu_349_p2; + +assign zext_ln175_14_fu_364_p1 = or_ln175_14_fu_359_p2; + +assign zext_ln175_15_fu_374_p1 = or_ln175_15_fu_369_p2; + +assign zext_ln175_16_fu_384_p1 = or_ln175_16_fu_379_p2; + +assign zext_ln175_17_fu_394_p1 = or_ln175_17_fu_389_p2; + +assign zext_ln175_18_fu_404_p1 = or_ln175_18_fu_399_p2; + +assign zext_ln175_fu_344_p1 = or_ln175_fu_338_p2; + +assign zext_ln179_3_fu_444_p1 = or_ln179_fu_438_p2; + +assign zext_ln179_fu_423_p1 = q_reg_276; + +endmodule //td_fused_top_tdf11_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_accum_3_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_46, + accum_in_46_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_46; +output accum_in_46_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_46; +reg accum_in_46_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln203_fu_73_p2; +reg [3:0] add_ln203_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln203_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln203_fu_79_p1; +reg [15:0] accum_in_46_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_46_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1715( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_46_preg <= 16'd0; + end else begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_46_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln203_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln203_reg_90 <= add_ln203_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_46 = sum_01_reg_55; + end else begin + accum_in_46 = accum_in_46_preg; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_46_ap_vld = 1'b1; + end else begin + accum_in_46_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln203_fu_79_p1; + +assign add_ln203_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln203_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln203_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf11_accum_3_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_accum_3_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_44, + accum_in_44_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_44; +output accum_in_44_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_44; +reg accum_in_44_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln203_fu_73_p2; +reg [3:0] add_ln203_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln203_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln203_fu_79_p1; +reg [15:0] accum_in_44_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_44_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1719( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_44_preg <= 16'd0; + end else begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_44_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln203_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln203_reg_90 <= add_ln203_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_44 = sum_01_reg_55; + end else begin + accum_in_44 = accum_in_44_preg; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_44_ap_vld = 1'b1; + end else begin + accum_in_44_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln203_fu_79_p1; + +assign add_ln203_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln203_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln203_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf11_accum_3_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_accum_3_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_42, + accum_in_42_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_42; +output accum_in_42_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_42; +reg accum_in_42_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln203_fu_73_p2; +reg [3:0] add_ln203_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln203_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln203_fu_79_p1; +reg [15:0] accum_in_42_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_42_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1723( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_42_preg <= 16'd0; + end else begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_42_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln203_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln203_reg_90 <= add_ln203_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_42 = sum_01_reg_55; + end else begin + accum_in_42 = accum_in_42_preg; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_42_ap_vld = 1'b1; + end else begin + accum_in_42_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln203_fu_79_p1; + +assign add_ln203_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln203_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln203_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf11_accum_3_3 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_accum_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_48, + accum_in_48_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_48; +output accum_in_48_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_48; +reg accum_in_48_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln203_fu_73_p2; +reg [3:0] add_ln203_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln203_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln203_fu_79_p1; +reg [15:0] accum_in_48_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_48_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1711( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_48_preg <= 16'd0; + end else begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_48_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln203_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln203_reg_90 <= add_ln203_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_48 = sum_01_reg_55; + end else begin + accum_in_48 = accum_in_48_preg; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_48_ap_vld = 1'b1; + end else begin + accum_in_48_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln203_fu_79_p1; + +assign add_ln203_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln203_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln203_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf11_accum_3 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_0_read, + sums_1_read, + sums_2_read, + sums_3_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + indices_23_out_din, + indices_23_out_full_n, + indices_23_out_write, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state25 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_0_read; +input [15:0] sums_1_read; +input [15:0] sums_2_read; +input [15:0] sums_3_read; +output [8:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [6:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [6:0] indices_23_out_din; +input indices_23_out_full_n; +output indices_23_out_write; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg indices_23_read; +reg indices_23_out_write; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg indices_23_out_blk_n; +reg [0:0] write_flag6_0_reg_153; +reg [0:0] write_flag9_0_reg_164; +reg [0:0] write_flag12_0_reg_175; +reg [0:0] write_flag_0_reg_186; +reg [2:0] o_reg_197; +reg [15:0] outputs_1_011_reg_208; +reg [15:0] outputs_0_010_reg_220; +reg [15:0] outputs_2_09_reg_232; +reg [15:0] outputs_3_08_reg_244; +reg [6:0] indices_23_read_reg_546; +wire [2:0] add_ln213_fu_268_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_state13_pp0_stage0_iter11; +wire ap_block_state14_pp0_stage0_iter12; +wire ap_block_state15_pp0_stage0_iter13; +wire ap_block_state16_pp0_stage0_iter14; +wire ap_block_state17_pp0_stage0_iter15; +wire ap_block_state18_pp0_stage0_iter16; +wire ap_block_state19_pp0_stage0_iter17; +wire ap_block_state20_pp0_stage0_iter18; +wire ap_block_state21_pp0_stage0_iter19; +wire ap_block_state22_pp0_stage0_iter20; +wire ap_block_state23_pp0_stage0_iter21; +wire ap_block_state24_pp0_stage0_iter22; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln213_fu_274_p2; +reg [0:0] icmp_ln213_reg_556; +reg [0:0] icmp_ln213_reg_556_pp0_iter1_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter2_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter3_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter4_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter5_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter6_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter7_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter8_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter9_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter10_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter11_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter12_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter13_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter14_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter15_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter16_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter17_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter18_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter19_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter20_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter21_reg; +wire [1:0] trunc_ln219_fu_280_p1; +reg [1:0] trunc_ln219_reg_560; +reg [1:0] trunc_ln219_reg_560_pp0_iter1_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter2_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter3_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter4_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter5_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter6_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter7_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter8_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter9_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter10_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter11_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter12_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter13_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter14_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter15_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter16_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter17_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter18_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter19_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter20_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter21_reg; +wire [0:0] write_flag_1_fu_296_p6; +wire [0:0] write_flag12_1_fu_310_p6; +wire [0:0] write_flag9_1_fu_324_p6; +wire [0:0] write_flag6_1_fu_338_p6; +wire [15:0] trunc_ln220_fu_352_p1; +reg [15:0] trunc_ln220_reg_593; +reg [15:0] tmp_320_i_i_reg_598; +reg [15:0] tmp_320_i_i_reg_598_pp0_iter2_reg; +reg [15:0] tmp_320_i_i_reg_598_pp0_iter3_reg; +reg [15:0] tmp_320_i_i_reg_598_pp0_iter4_reg; +reg [15:0] tmp_320_i_i_reg_598_pp0_iter5_reg; +reg [15:0] tmp_320_i_i_reg_598_pp0_iter6_reg; +reg [15:0] tmp_320_i_i_reg_598_pp0_iter7_reg; +reg [15:0] tmp_320_i_i_reg_598_pp0_iter8_reg; +reg [15:0] tmp_321_i_i_reg_603; +reg [15:0] tmp_321_i_i_reg_603_pp0_iter2_reg; +reg [15:0] tmp_321_i_i_reg_603_pp0_iter3_reg; +reg [15:0] tmp_321_i_i_reg_603_pp0_iter4_reg; +reg [15:0] tmp_321_i_i_reg_603_pp0_iter5_reg; +reg [15:0] tmp_321_i_i_reg_603_pp0_iter6_reg; +reg [15:0] tmp_321_i_i_reg_603_pp0_iter7_reg; +reg [15:0] tmp_321_i_i_reg_603_pp0_iter8_reg; +reg [15:0] tmp_321_i_i_reg_603_pp0_iter9_reg; +reg [15:0] tmp_321_i_i_reg_603_pp0_iter10_reg; +reg [15:0] tmp_321_i_i_reg_603_pp0_iter11_reg; +reg [15:0] tmp_321_i_i_reg_603_pp0_iter12_reg; +reg [15:0] tmp_321_i_i_reg_603_pp0_iter13_reg; +wire [15:0] val_in_assign_fu_376_p6; +reg [15:0] val_in_assign_reg_608; +wire [15:0] grp_fu_260_p2; +reg [15:0] sub_i_i_i_reg_618; +wire [15:0] grp_fu_264_p2; +reg [15:0] normalized_reg_628; +wire [15:0] grp_fu_256_p2; +reg [15:0] biased_reg_638; +wire [15:0] outputs_3_1_fu_446_p3; +reg ap_enable_reg_pp0_iter22; +wire [15:0] outputs_2_1_fu_454_p3; +wire [15:0] outputs_0_1_fu_478_p3; +wire [15:0] outputs_1_1_fu_494_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_condition_pp0_exit_iter21_state23; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln220_fu_291_p1; +wire [15:0] grp_fu_256_p1; +wire [15:0] grp_fu_260_p1; +wire [15:0] grp_fu_264_p1; +wire [8:0] ochan_fu_284_p3; +wire [15:0] data_V_fu_397_p1; +wire [0:0] p_Result_s_fu_400_p3; +wire [0:0] icmp_ln223_fu_415_p2; +wire [15:0] activated_fu_408_p3; +wire [0:0] icmp_ln223_13_fu_428_p2; +wire [15:0] select_ln223_fu_420_p3; +wire [0:0] icmp_ln223_14_fu_441_p2; +wire [15:0] select_ln223_26_fu_433_p3; +wire [15:0] select_ln223_27_fu_462_p3; +wire [15:0] select_ln223_28_fu_470_p3; +wire [15:0] select_ln223_29_fu_486_p3; +wire ap_CS_fsm_state25; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1727( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(normalized_reg_628), + .din1(grp_fu_256_p1), + .dout(grp_fu_256_p2) +); + +td_fused_top_hsub_16ns_16ns_16_7_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 7 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_7_full_dsp_1_U1728( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(val_in_assign_reg_608), + .din1(grp_fu_260_p1), + .dout(grp_fu_260_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1729( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_618), + .din1(grp_fu_264_p1), + .dout(grp_fu_264_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U1730( + .din0(1'd1), + .din1(write_flag_0_reg_186), + .din2(write_flag_0_reg_186), + .din3(write_flag_0_reg_186), + .din4(trunc_ln219_fu_280_p1), + .dout(write_flag_1_fu_296_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U1731( + .din0(write_flag12_0_reg_175), + .din1(write_flag12_0_reg_175), + .din2(write_flag12_0_reg_175), + .din3(1'd1), + .din4(trunc_ln219_fu_280_p1), + .dout(write_flag12_1_fu_310_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U1732( + .din0(write_flag9_0_reg_164), + .din1(write_flag9_0_reg_164), + .din2(1'd1), + .din3(write_flag9_0_reg_164), + .din4(trunc_ln219_fu_280_p1), + .dout(write_flag9_1_fu_324_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U1733( + .din0(write_flag6_0_reg_153), + .din1(1'd1), + .din2(write_flag6_0_reg_153), + .din3(write_flag6_0_reg_153), + .din4(trunc_ln219_fu_280_p1), + .dout(write_flag6_1_fu_338_p6) +); + +td_fused_top_mux_42_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 16 )) +mux_42_16_1_1_U1734( + .din0(sums_0_read), + .din1(sums_1_read), + .din2(sums_2_read), + .din3(sums_3_read), + .din4(trunc_ln219_reg_560), + .dout(val_in_assign_fu_376_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end else if ((((ap_enable_reg_pp0_iter20 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter21_state23) & (1'b0 == ap_block_pp0_stage0_subdone)) | (~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter21_state23) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter20; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + o_reg_197 <= add_ln213_fu_268_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + o_reg_197 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag12_0_reg_175 <= write_flag12_1_fu_310_p6; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag12_0_reg_175 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag6_0_reg_153 <= write_flag6_1_fu_338_p6; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_153 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag9_0_reg_164 <= write_flag9_1_fu_324_p6; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_164 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag_0_reg_186 <= write_flag_1_fu_296_p6; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_186 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_556_pp0_iter20_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + biased_reg_638 <= grp_fu_256_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln213_reg_556 <= icmp_ln213_fu_274_p2; + icmp_ln213_reg_556_pp0_iter1_reg <= icmp_ln213_reg_556; + trunc_ln219_reg_560_pp0_iter1_reg <= trunc_ln219_reg_560; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln213_reg_556_pp0_iter10_reg <= icmp_ln213_reg_556_pp0_iter9_reg; + icmp_ln213_reg_556_pp0_iter11_reg <= icmp_ln213_reg_556_pp0_iter10_reg; + icmp_ln213_reg_556_pp0_iter12_reg <= icmp_ln213_reg_556_pp0_iter11_reg; + icmp_ln213_reg_556_pp0_iter13_reg <= icmp_ln213_reg_556_pp0_iter12_reg; + icmp_ln213_reg_556_pp0_iter14_reg <= icmp_ln213_reg_556_pp0_iter13_reg; + icmp_ln213_reg_556_pp0_iter15_reg <= icmp_ln213_reg_556_pp0_iter14_reg; + icmp_ln213_reg_556_pp0_iter16_reg <= icmp_ln213_reg_556_pp0_iter15_reg; + icmp_ln213_reg_556_pp0_iter17_reg <= icmp_ln213_reg_556_pp0_iter16_reg; + icmp_ln213_reg_556_pp0_iter18_reg <= icmp_ln213_reg_556_pp0_iter17_reg; + icmp_ln213_reg_556_pp0_iter19_reg <= icmp_ln213_reg_556_pp0_iter18_reg; + icmp_ln213_reg_556_pp0_iter20_reg <= icmp_ln213_reg_556_pp0_iter19_reg; + icmp_ln213_reg_556_pp0_iter21_reg <= icmp_ln213_reg_556_pp0_iter20_reg; + icmp_ln213_reg_556_pp0_iter2_reg <= icmp_ln213_reg_556_pp0_iter1_reg; + icmp_ln213_reg_556_pp0_iter3_reg <= icmp_ln213_reg_556_pp0_iter2_reg; + icmp_ln213_reg_556_pp0_iter4_reg <= icmp_ln213_reg_556_pp0_iter3_reg; + icmp_ln213_reg_556_pp0_iter5_reg <= icmp_ln213_reg_556_pp0_iter4_reg; + icmp_ln213_reg_556_pp0_iter6_reg <= icmp_ln213_reg_556_pp0_iter5_reg; + icmp_ln213_reg_556_pp0_iter7_reg <= icmp_ln213_reg_556_pp0_iter6_reg; + icmp_ln213_reg_556_pp0_iter8_reg <= icmp_ln213_reg_556_pp0_iter7_reg; + icmp_ln213_reg_556_pp0_iter9_reg <= icmp_ln213_reg_556_pp0_iter8_reg; + tmp_320_i_i_reg_598_pp0_iter2_reg <= tmp_320_i_i_reg_598; + tmp_320_i_i_reg_598_pp0_iter3_reg <= tmp_320_i_i_reg_598_pp0_iter2_reg; + tmp_320_i_i_reg_598_pp0_iter4_reg <= tmp_320_i_i_reg_598_pp0_iter3_reg; + tmp_320_i_i_reg_598_pp0_iter5_reg <= tmp_320_i_i_reg_598_pp0_iter4_reg; + tmp_320_i_i_reg_598_pp0_iter6_reg <= tmp_320_i_i_reg_598_pp0_iter5_reg; + tmp_320_i_i_reg_598_pp0_iter7_reg <= tmp_320_i_i_reg_598_pp0_iter6_reg; + tmp_320_i_i_reg_598_pp0_iter8_reg <= tmp_320_i_i_reg_598_pp0_iter7_reg; + tmp_321_i_i_reg_603_pp0_iter10_reg <= tmp_321_i_i_reg_603_pp0_iter9_reg; + tmp_321_i_i_reg_603_pp0_iter11_reg <= tmp_321_i_i_reg_603_pp0_iter10_reg; + tmp_321_i_i_reg_603_pp0_iter12_reg <= tmp_321_i_i_reg_603_pp0_iter11_reg; + tmp_321_i_i_reg_603_pp0_iter13_reg <= tmp_321_i_i_reg_603_pp0_iter12_reg; + tmp_321_i_i_reg_603_pp0_iter2_reg <= tmp_321_i_i_reg_603; + tmp_321_i_i_reg_603_pp0_iter3_reg <= tmp_321_i_i_reg_603_pp0_iter2_reg; + tmp_321_i_i_reg_603_pp0_iter4_reg <= tmp_321_i_i_reg_603_pp0_iter3_reg; + tmp_321_i_i_reg_603_pp0_iter5_reg <= tmp_321_i_i_reg_603_pp0_iter4_reg; + tmp_321_i_i_reg_603_pp0_iter6_reg <= tmp_321_i_i_reg_603_pp0_iter5_reg; + tmp_321_i_i_reg_603_pp0_iter7_reg <= tmp_321_i_i_reg_603_pp0_iter6_reg; + tmp_321_i_i_reg_603_pp0_iter8_reg <= tmp_321_i_i_reg_603_pp0_iter7_reg; + tmp_321_i_i_reg_603_pp0_iter9_reg <= tmp_321_i_i_reg_603_pp0_iter8_reg; + trunc_ln219_reg_560_pp0_iter10_reg <= trunc_ln219_reg_560_pp0_iter9_reg; + trunc_ln219_reg_560_pp0_iter11_reg <= trunc_ln219_reg_560_pp0_iter10_reg; + trunc_ln219_reg_560_pp0_iter12_reg <= trunc_ln219_reg_560_pp0_iter11_reg; + trunc_ln219_reg_560_pp0_iter13_reg <= trunc_ln219_reg_560_pp0_iter12_reg; + trunc_ln219_reg_560_pp0_iter14_reg <= trunc_ln219_reg_560_pp0_iter13_reg; + trunc_ln219_reg_560_pp0_iter15_reg <= trunc_ln219_reg_560_pp0_iter14_reg; + trunc_ln219_reg_560_pp0_iter16_reg <= trunc_ln219_reg_560_pp0_iter15_reg; + trunc_ln219_reg_560_pp0_iter17_reg <= trunc_ln219_reg_560_pp0_iter16_reg; + trunc_ln219_reg_560_pp0_iter18_reg <= trunc_ln219_reg_560_pp0_iter17_reg; + trunc_ln219_reg_560_pp0_iter19_reg <= trunc_ln219_reg_560_pp0_iter18_reg; + trunc_ln219_reg_560_pp0_iter20_reg <= trunc_ln219_reg_560_pp0_iter19_reg; + trunc_ln219_reg_560_pp0_iter21_reg <= trunc_ln219_reg_560_pp0_iter20_reg; + trunc_ln219_reg_560_pp0_iter2_reg <= trunc_ln219_reg_560_pp0_iter1_reg; + trunc_ln219_reg_560_pp0_iter3_reg <= trunc_ln219_reg_560_pp0_iter2_reg; + trunc_ln219_reg_560_pp0_iter4_reg <= trunc_ln219_reg_560_pp0_iter3_reg; + trunc_ln219_reg_560_pp0_iter5_reg <= trunc_ln219_reg_560_pp0_iter4_reg; + trunc_ln219_reg_560_pp0_iter6_reg <= trunc_ln219_reg_560_pp0_iter5_reg; + trunc_ln219_reg_560_pp0_iter7_reg <= trunc_ln219_reg_560_pp0_iter6_reg; + trunc_ln219_reg_560_pp0_iter8_reg <= trunc_ln219_reg_560_pp0_iter7_reg; + trunc_ln219_reg_560_pp0_iter9_reg <= trunc_ln219_reg_560_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + indices_23_read_reg_546 <= indices_23_dout; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_556_pp0_iter12_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + normalized_reg_628 <= grp_fu_264_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter22 == 1'b1) & (icmp_ln213_reg_556_pp0_iter21_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + outputs_0_010_reg_220 <= outputs_0_1_fu_478_p3; + outputs_1_011_reg_208 <= outputs_1_1_fu_494_p3; + outputs_2_09_reg_232 <= outputs_2_1_fu_454_p3; + outputs_3_08_reg_244 <= outputs_3_1_fu_446_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_556_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sub_i_i_i_reg_618 <= grp_fu_260_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_reg_556 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + tmp_320_i_i_reg_598 <= {{adjustments_q0[31:16]}}; + tmp_321_i_i_reg_603 <= {{adjustments_q0[47:32]}}; + trunc_ln220_reg_593 <= trunc_ln220_fu_352_p1; + val_in_assign_reg_608 <= val_in_assign_fu_376_p6; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + trunc_ln219_reg_560 <= trunc_ln219_fu_280_p1; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0))) begin + ap_condition_pp0_exit_iter21_state23 = 1'b1; + end else begin + ap_condition_pp0_exit_iter21_state23 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_out_blk_n = indices_23_out_full_n; + end else begin + indices_23_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_out_write = 1'b1; + end else begin + indices_23_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state25; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state25 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign activated_fu_408_p3 = ((p_Result_s_fu_400_p3[0:0] == 1'b1) ? 16'd0 : biased_reg_638); + +assign add_ln213_fu_268_p2 = (o_reg_197 + 3'd1); + +assign adjustments_address0 = zext_ln220_fu_291_p1; + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state25 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = outputs_0_010_reg_220; + +assign ap_return_1 = outputs_1_011_reg_208; + +assign ap_return_2 = outputs_2_09_reg_232; + +assign ap_return_3 = outputs_3_08_reg_244; + +assign data_V_fu_397_p1 = biased_reg_638; + +assign grp_fu_256_p1 = tmp_321_i_i_reg_603_pp0_iter13_reg; + +assign grp_fu_260_p1 = trunc_ln220_reg_593; + +assign grp_fu_264_p1 = tmp_320_i_i_reg_598_pp0_iter8_reg; + +assign icmp_ln213_fu_274_p2 = ((o_reg_197 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln223_13_fu_428_p2 = ((trunc_ln219_reg_560_pp0_iter21_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln223_14_fu_441_p2 = ((trunc_ln219_reg_560_pp0_iter21_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln223_fu_415_p2 = ((trunc_ln219_reg_560_pp0_iter21_reg == 2'd0) ? 1'b1 : 1'b0); + +assign indices_23_out_din = indices_23_dout; + +assign ochan_fu_284_p3 = {{indices_23_read_reg_546}, {trunc_ln219_fu_280_p1}}; + +assign outputs_0_1_fu_478_p3 = ((icmp_ln223_14_fu_441_p2[0:0] == 1'b1) ? outputs_0_010_reg_220 : select_ln223_28_fu_470_p3); + +assign outputs_1_1_fu_494_p3 = ((icmp_ln223_14_fu_441_p2[0:0] == 1'b1) ? outputs_1_011_reg_208 : select_ln223_29_fu_486_p3); + +assign outputs_2_1_fu_454_p3 = ((icmp_ln223_14_fu_441_p2[0:0] == 1'b1) ? activated_fu_408_p3 : outputs_2_09_reg_232); + +assign outputs_3_1_fu_446_p3 = ((icmp_ln223_14_fu_441_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : select_ln223_26_fu_433_p3); + +assign p_Result_s_fu_400_p3 = data_V_fu_397_p1[32'd15]; + +assign select_ln223_26_fu_433_p3 = ((icmp_ln223_13_fu_428_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : select_ln223_fu_420_p3); + +assign select_ln223_27_fu_462_p3 = ((icmp_ln223_fu_415_p2[0:0] == 1'b1) ? activated_fu_408_p3 : outputs_0_010_reg_220); + +assign select_ln223_28_fu_470_p3 = ((icmp_ln223_13_fu_428_p2[0:0] == 1'b1) ? outputs_0_010_reg_220 : select_ln223_27_fu_462_p3); + +assign select_ln223_29_fu_486_p3 = ((icmp_ln223_13_fu_428_p2[0:0] == 1'b1) ? activated_fu_408_p3 : outputs_1_011_reg_208); + +assign select_ln223_fu_420_p3 = ((icmp_ln223_fu_415_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : activated_fu_408_p3); + +assign trunc_ln219_fu_280_p1 = o_reg_197[1:0]; + +assign trunc_ln220_fu_352_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_291_p1 = ochan_fu_284_p3; + +endmodule //td_fused_top_tdf11_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_0_address0, + ifmap_vec_0_ce0, + ifmap_vec_0_q0, + ifmap_vec_1_address0, + ifmap_vec_1_ce0, + ifmap_vec_1_q0, + ifmap_vec_2_address0, + ifmap_vec_2_ce0, + ifmap_vec_2_q0, + ifmap_vec_3_address0, + ifmap_vec_3_ce0, + ifmap_vec_3_q0, + weight_vecs_0_0_address0, + weight_vecs_0_0_ce0, + weight_vecs_0_0_q0, + weight_vecs_0_1_address0, + weight_vecs_0_1_ce0, + weight_vecs_0_1_q0, + weight_vecs_0_2_address0, + weight_vecs_0_2_ce0, + weight_vecs_0_2_q0, + weight_vecs_0_3_address0, + weight_vecs_0_3_ce0, + weight_vecs_0_3_q0, + weight_vecs_1_0_address0, + weight_vecs_1_0_ce0, + weight_vecs_1_0_q0, + weight_vecs_1_1_address0, + weight_vecs_1_1_ce0, + weight_vecs_1_1_q0, + weight_vecs_1_2_address0, + weight_vecs_1_2_ce0, + weight_vecs_1_2_q0, + weight_vecs_1_3_address0, + weight_vecs_1_3_ce0, + weight_vecs_1_3_q0, + weight_vecs_2_0_address0, + weight_vecs_2_0_ce0, + weight_vecs_2_0_q0, + weight_vecs_2_1_address0, + weight_vecs_2_1_ce0, + weight_vecs_2_1_q0, + weight_vecs_2_2_address0, + weight_vecs_2_2_ce0, + weight_vecs_2_2_q0, + weight_vecs_2_3_address0, + weight_vecs_2_3_ce0, + weight_vecs_2_3_q0, + weight_vecs_3_0_address0, + weight_vecs_3_0_ce0, + weight_vecs_3_0_q0, + weight_vecs_3_1_address0, + weight_vecs_3_1_ce0, + weight_vecs_3_1_q0, + weight_vecs_3_2_address0, + weight_vecs_3_2_ce0, + weight_vecs_3_2_q0, + weight_vecs_3_3_address0, + weight_vecs_3_3_ce0, + weight_vecs_3_3_q0, + products_0_0_address0, + products_0_0_ce0, + products_0_0_we0, + products_0_0_d0, + products_0_1_address0, + products_0_1_ce0, + products_0_1_we0, + products_0_1_d0, + products_0_2_address0, + products_0_2_ce0, + products_0_2_we0, + products_0_2_d0, + products_0_3_address0, + products_0_3_ce0, + products_0_3_we0, + products_0_3_d0, + products_1_0_address0, + products_1_0_ce0, + products_1_0_we0, + products_1_0_d0, + products_1_1_address0, + products_1_1_ce0, + products_1_1_we0, + products_1_1_d0, + products_1_2_address0, + products_1_2_ce0, + products_1_2_we0, + products_1_2_d0, + products_1_3_address0, + products_1_3_ce0, + products_1_3_we0, + products_1_3_d0, + products_2_0_address0, + products_2_0_ce0, + products_2_0_we0, + products_2_0_d0, + products_2_1_address0, + products_2_1_ce0, + products_2_1_we0, + products_2_1_d0, + products_2_2_address0, + products_2_2_ce0, + products_2_2_we0, + products_2_2_d0, + products_2_3_address0, + products_2_3_ce0, + products_2_3_we0, + products_2_3_d0, + products_3_0_address0, + products_3_0_ce0, + products_3_0_we0, + products_3_0_d0, + products_3_1_address0, + products_3_1_ce0, + products_3_1_we0, + products_3_1_d0, + products_3_2_address0, + products_3_2_ce0, + products_3_2_we0, + products_3_2_d0, + products_3_3_address0, + products_3_3_ce0, + products_3_3_we0, + products_3_3_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state11 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [7:0] ifmap_vec_0_address0; +output ifmap_vec_0_ce0; +input [15:0] ifmap_vec_0_q0; +output [7:0] ifmap_vec_1_address0; +output ifmap_vec_1_ce0; +input [15:0] ifmap_vec_1_q0; +output [7:0] ifmap_vec_2_address0; +output ifmap_vec_2_ce0; +input [15:0] ifmap_vec_2_q0; +output [7:0] ifmap_vec_3_address0; +output ifmap_vec_3_ce0; +input [15:0] ifmap_vec_3_q0; +output [7:0] weight_vecs_0_0_address0; +output weight_vecs_0_0_ce0; +input [15:0] weight_vecs_0_0_q0; +output [7:0] weight_vecs_0_1_address0; +output weight_vecs_0_1_ce0; +input [15:0] weight_vecs_0_1_q0; +output [7:0] weight_vecs_0_2_address0; +output weight_vecs_0_2_ce0; +input [15:0] weight_vecs_0_2_q0; +output [7:0] weight_vecs_0_3_address0; +output weight_vecs_0_3_ce0; +input [15:0] weight_vecs_0_3_q0; +output [7:0] weight_vecs_1_0_address0; +output weight_vecs_1_0_ce0; +input [15:0] weight_vecs_1_0_q0; +output [7:0] weight_vecs_1_1_address0; +output weight_vecs_1_1_ce0; +input [15:0] weight_vecs_1_1_q0; +output [7:0] weight_vecs_1_2_address0; +output weight_vecs_1_2_ce0; +input [15:0] weight_vecs_1_2_q0; +output [7:0] weight_vecs_1_3_address0; +output weight_vecs_1_3_ce0; +input [15:0] weight_vecs_1_3_q0; +output [7:0] weight_vecs_2_0_address0; +output weight_vecs_2_0_ce0; +input [15:0] weight_vecs_2_0_q0; +output [7:0] weight_vecs_2_1_address0; +output weight_vecs_2_1_ce0; +input [15:0] weight_vecs_2_1_q0; +output [7:0] weight_vecs_2_2_address0; +output weight_vecs_2_2_ce0; +input [15:0] weight_vecs_2_2_q0; +output [7:0] weight_vecs_2_3_address0; +output weight_vecs_2_3_ce0; +input [15:0] weight_vecs_2_3_q0; +output [7:0] weight_vecs_3_0_address0; +output weight_vecs_3_0_ce0; +input [15:0] weight_vecs_3_0_q0; +output [7:0] weight_vecs_3_1_address0; +output weight_vecs_3_1_ce0; +input [15:0] weight_vecs_3_1_q0; +output [7:0] weight_vecs_3_2_address0; +output weight_vecs_3_2_ce0; +input [15:0] weight_vecs_3_2_q0; +output [7:0] weight_vecs_3_3_address0; +output weight_vecs_3_3_ce0; +input [15:0] weight_vecs_3_3_q0; +output [7:0] products_0_0_address0; +output products_0_0_ce0; +output products_0_0_we0; +output [15:0] products_0_0_d0; +output [7:0] products_0_1_address0; +output products_0_1_ce0; +output products_0_1_we0; +output [15:0] products_0_1_d0; +output [7:0] products_0_2_address0; +output products_0_2_ce0; +output products_0_2_we0; +output [15:0] products_0_2_d0; +output [7:0] products_0_3_address0; +output products_0_3_ce0; +output products_0_3_we0; +output [15:0] products_0_3_d0; +output [7:0] products_1_0_address0; +output products_1_0_ce0; +output products_1_0_we0; +output [15:0] products_1_0_d0; +output [7:0] products_1_1_address0; +output products_1_1_ce0; +output products_1_1_we0; +output [15:0] products_1_1_d0; +output [7:0] products_1_2_address0; +output products_1_2_ce0; +output products_1_2_we0; +output [15:0] products_1_2_d0; +output [7:0] products_1_3_address0; +output products_1_3_ce0; +output products_1_3_we0; +output [15:0] products_1_3_d0; +output [7:0] products_2_0_address0; +output products_2_0_ce0; +output products_2_0_we0; +output [15:0] products_2_0_d0; +output [7:0] products_2_1_address0; +output products_2_1_ce0; +output products_2_1_we0; +output [15:0] products_2_1_d0; +output [7:0] products_2_2_address0; +output products_2_2_ce0; +output products_2_2_we0; +output [15:0] products_2_2_d0; +output [7:0] products_2_3_address0; +output products_2_3_ce0; +output products_2_3_we0; +output [15:0] products_2_3_d0; +output [7:0] products_3_0_address0; +output products_3_0_ce0; +output products_3_0_we0; +output [15:0] products_3_0_d0; +output [7:0] products_3_1_address0; +output products_3_1_ce0; +output products_3_1_we0; +output [15:0] products_3_1_d0; +output [7:0] products_3_2_address0; +output products_3_2_ce0; +output products_3_2_we0; +output [15:0] products_3_2_d0; +output [7:0] products_3_3_address0; +output products_3_3_ce0; +output products_3_3_we0; +output [15:0] products_3_3_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_0_ce0; +reg ifmap_vec_1_ce0; +reg ifmap_vec_2_ce0; +reg ifmap_vec_3_ce0; +reg weight_vecs_0_0_ce0; +reg weight_vecs_0_1_ce0; +reg weight_vecs_0_2_ce0; +reg weight_vecs_0_3_ce0; +reg weight_vecs_1_0_ce0; +reg weight_vecs_1_1_ce0; +reg weight_vecs_1_2_ce0; +reg weight_vecs_1_3_ce0; +reg weight_vecs_2_0_ce0; +reg weight_vecs_2_1_ce0; +reg weight_vecs_2_2_ce0; +reg weight_vecs_2_3_ce0; +reg weight_vecs_3_0_ce0; +reg weight_vecs_3_1_ce0; +reg weight_vecs_3_2_ce0; +reg weight_vecs_3_3_ce0; +reg products_0_0_ce0; +reg products_0_0_we0; +reg products_0_1_ce0; +reg products_0_1_we0; +reg products_0_2_ce0; +reg products_0_2_we0; +reg products_0_3_ce0; +reg products_0_3_we0; +reg products_1_0_ce0; +reg products_1_0_we0; +reg products_1_1_ce0; +reg products_1_1_we0; +reg products_1_2_ce0; +reg products_1_2_we0; +reg products_1_3_ce0; +reg products_1_3_we0; +reg products_2_0_ce0; +reg products_2_0_we0; +reg products_2_1_ce0; +reg products_2_1_we0; +reg products_2_2_ce0; +reg products_2_2_we0; +reg products_2_3_ce0; +reg products_2_3_we0; +reg products_3_0_ce0; +reg products_3_0_we0; +reg products_3_1_ce0; +reg products_3_1_we0; +reg products_3_2_ce0; +reg products_3_2_we0; +reg products_3_3_ce0; +reg products_3_3_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] indvar_flatten17_reg_606; +reg [1:0] ii_reg_617; +reg [6:0] indvar_flatten_reg_628; +reg [1:0] jj_reg_639; +reg [6:0] ic_reg_650; +wire [7:0] add_ln147_7_fu_725_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln147_fu_759_p2; +reg [0:0] icmp_ln147_reg_1104; +reg [0:0] icmp_ln147_reg_1104_pp0_iter1_reg; +reg [0:0] icmp_ln147_reg_1104_pp0_iter2_reg; +reg [0:0] icmp_ln147_reg_1104_pp0_iter3_reg; +reg [0:0] icmp_ln147_reg_1104_pp0_iter4_reg; +reg [0:0] icmp_ln147_reg_1104_pp0_iter5_reg; +reg [0:0] icmp_ln147_reg_1104_pp0_iter6_reg; +reg [0:0] icmp_ln147_reg_1104_pp0_iter7_reg; +wire [1:0] select_ln147_26_fu_793_p3; +reg [1:0] select_ln147_26_reg_1108; +wire [1:0] select_ln148_19_fu_895_p3; +reg [1:0] select_ln148_19_reg_1113; +wire [5:0] empty_156_fu_907_p2; +reg [5:0] empty_156_reg_1118; +wire [3:0] select_ln148_20_fu_923_p3; +reg [3:0] select_ln148_20_reg_1123; +reg [3:0] select_ln148_20_reg_1123_pp0_iter1_reg; +reg [3:0] select_ln148_20_reg_1123_pp0_iter2_reg; +reg [3:0] select_ln148_20_reg_1123_pp0_iter3_reg; +reg [3:0] select_ln148_20_reg_1123_pp0_iter4_reg; +reg [3:0] select_ln148_20_reg_1123_pp0_iter5_reg; +reg [3:0] select_ln148_20_reg_1123_pp0_iter6_reg; +reg [3:0] select_ln148_20_reg_1123_pp0_iter7_reg; +wire [5:0] trunc_ln149_fu_931_p1; +reg [5:0] trunc_ln149_reg_1131; +reg [5:0] trunc_ln149_reg_1131_pp0_iter1_reg; +reg [5:0] trunc_ln149_reg_1131_pp0_iter2_reg; +reg [5:0] trunc_ln149_reg_1131_pp0_iter3_reg; +reg [5:0] trunc_ln149_reg_1131_pp0_iter4_reg; +reg [5:0] trunc_ln149_reg_1131_pp0_iter5_reg; +reg [5:0] trunc_ln149_reg_1131_pp0_iter6_reg; +reg [5:0] trunc_ln149_reg_1131_pp0_iter7_reg; +reg [3:0] newIndex_reg_1138; +reg [3:0] newIndex_reg_1138_pp0_iter1_reg; +reg [3:0] newIndex_reg_1138_pp0_iter2_reg; +reg [3:0] newIndex_reg_1138_pp0_iter3_reg; +reg [3:0] newIndex_reg_1138_pp0_iter4_reg; +reg [3:0] newIndex_reg_1138_pp0_iter5_reg; +reg [3:0] newIndex_reg_1138_pp0_iter6_reg; +reg [3:0] newIndex_reg_1138_pp0_iter7_reg; +wire [6:0] add_ln149_fu_945_p2; +wire [6:0] select_ln148_21_fu_957_p3; +reg [15:0] ifmap_vec_0_load_reg_1254; +reg [15:0] weight_vecs_0_0_load_reg_1262; +reg [15:0] weight_vecs_1_0_load_reg_1267; +reg [15:0] weight_vecs_2_0_load_reg_1272; +reg [15:0] weight_vecs_3_0_load_reg_1277; +reg [15:0] ifmap_vec_1_load_reg_1282; +reg [15:0] weight_vecs_0_1_load_reg_1290; +reg [15:0] weight_vecs_1_1_load_reg_1295; +reg [15:0] weight_vecs_2_1_load_reg_1300; +reg [15:0] weight_vecs_3_1_load_reg_1305; +reg [15:0] ifmap_vec_2_load_reg_1310; +reg [15:0] weight_vecs_0_2_load_reg_1318; +reg [15:0] weight_vecs_1_2_load_reg_1323; +reg [15:0] weight_vecs_2_2_load_reg_1328; +reg [15:0] weight_vecs_3_2_load_reg_1333; +reg [15:0] ifmap_vec_3_load_reg_1338; +reg [15:0] weight_vecs_0_3_load_reg_1346; +reg [15:0] weight_vecs_1_3_load_reg_1351; +reg [15:0] weight_vecs_2_3_load_reg_1356; +reg [15:0] weight_vecs_3_3_load_reg_1361; +wire [15:0] grp_fu_661_p2; +reg [15:0] mul_reg_1366; +wire [15:0] grp_fu_665_p2; +reg [15:0] mul_1_reg_1371; +wire [15:0] grp_fu_669_p2; +reg [15:0] mul_2_reg_1376; +wire [15:0] grp_fu_673_p2; +reg [15:0] mul_3_reg_1381; +wire [15:0] grp_fu_677_p2; +reg [15:0] mul27_1_reg_1386; +wire [15:0] grp_fu_681_p2; +reg [15:0] mul27_1_1_reg_1391; +wire [15:0] grp_fu_685_p2; +reg [15:0] mul27_1_2_reg_1396; +wire [15:0] grp_fu_689_p2; +reg [15:0] mul27_1_3_reg_1401; +wire [15:0] grp_fu_693_p2; +reg [15:0] mul27_2_reg_1406; +wire [15:0] grp_fu_697_p2; +reg [15:0] mul27_2_1_reg_1411; +wire [15:0] grp_fu_701_p2; +reg [15:0] mul27_2_2_reg_1416; +wire [15:0] grp_fu_705_p2; +reg [15:0] mul27_2_3_reg_1421; +wire [15:0] grp_fu_709_p2; +reg [15:0] mul27_3_reg_1426; +wire [15:0] grp_fu_713_p2; +reg [15:0] mul27_3_1_reg_1431; +wire [15:0] grp_fu_717_p2; +reg [15:0] mul27_3_2_reg_1436; +wire [15:0] grp_fu_721_p2; +reg [15:0] mul27_3_3_reg_1441; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg [1:0] ap_phi_mux_ii_phi_fu_621_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_643_p4; +wire [63:0] tmp_204_fu_971_p1; +wire [63:0] zext_ln153_fu_1001_p1; +wire [63:0] zext_ln153_10_fu_1031_p1; +wire [63:0] zext_ln153_11_fu_1061_p1; +wire [63:0] zext_ln153_12_fu_1091_p1; +wire [3:0] shl_ln_fu_735_p3; +wire [3:0] zext_ln150_fu_731_p1; +wire [3:0] sub_ln150_fu_743_p2; +wire [3:0] zext_ln150_10_fu_749_p1; +wire [0:0] icmp_ln148_fu_771_p2; +wire [1:0] add_ln147_fu_765_p2; +wire [3:0] tmp_fu_805_p3; +wire [4:0] tmp_cast_fu_813_p1; +wire [4:0] select_ln147_32_cast_fu_801_p1; +wire [4:0] empty_155_fu_817_p2; +wire [3:0] shl_ln150_mid1_fu_831_p3; +wire [3:0] zext_ln150_15_fu_827_p1; +wire [3:0] sub_ln150_9_fu_839_p2; +wire [3:0] add_ln150_fu_753_p2; +wire [0:0] tmp_93_fu_861_p3; +wire [0:0] xor_ln149_fu_869_p2; +wire [1:0] select_ln147_fu_777_p3; +wire [0:0] or_ln147_fu_875_p2; +wire [6:0] select_ln147_25_fu_785_p3; +wire [1:0] add_ln148_fu_881_p2; +wire [5:0] sext_ln150_fu_823_p1; +wire [5:0] select_ln148_25_cast_fu_903_p1; +wire [3:0] select_ln147_27_fu_845_p3; +wire [3:0] zext_ln150_16_fu_913_p1; +wire [3:0] select_ln147_28_fu_853_p3; +wire [3:0] add_ln150_8_fu_917_p2; +wire [6:0] select_ln148_fu_887_p3; +wire [6:0] add_ln148_7_fu_951_p2; +wire [9:0] tmp_94_fu_965_p3; +wire [7:0] lshr_ln_fu_995_p3; +wire [5:0] or_ln150_fu_1009_p2; +wire [3:0] tmp_s_fu_1014_p4; +wire [7:0] lshr_ln153_s_fu_1024_p3; +wire [5:0] or_ln150_5_fu_1039_p2; +wire [3:0] tmp_63_fu_1044_p4; +wire [7:0] lshr_ln153_1_fu_1054_p3; +wire [5:0] or_ln150_6_fu_1069_p2; +wire [3:0] tmp_64_fu_1074_p4; +wire [7:0] lshr_ln153_2_fu_1084_p3; +wire ap_CS_fsm_state11; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1645( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_1254), + .din1(weight_vecs_0_0_load_reg_1262), + .dout(grp_fu_661_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1646( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_1254), + .din1(weight_vecs_1_0_load_reg_1267), + .dout(grp_fu_665_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1647( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_1254), + .din1(weight_vecs_2_0_load_reg_1272), + .dout(grp_fu_669_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1648( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_1254), + .din1(weight_vecs_3_0_load_reg_1277), + .dout(grp_fu_673_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1649( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_1282), + .din1(weight_vecs_0_1_load_reg_1290), + .dout(grp_fu_677_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1650( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_1282), + .din1(weight_vecs_1_1_load_reg_1295), + .dout(grp_fu_681_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1651( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_1282), + .din1(weight_vecs_2_1_load_reg_1300), + .dout(grp_fu_685_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1652( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_1282), + .din1(weight_vecs_3_1_load_reg_1305), + .dout(grp_fu_689_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1653( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_2_load_reg_1310), + .din1(weight_vecs_0_2_load_reg_1318), + .dout(grp_fu_693_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1654( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_2_load_reg_1310), + .din1(weight_vecs_1_2_load_reg_1323), + .dout(grp_fu_697_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1655( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_2_load_reg_1310), + .din1(weight_vecs_2_2_load_reg_1328), + .dout(grp_fu_701_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1656( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_2_load_reg_1310), + .din1(weight_vecs_3_2_load_reg_1333), + .dout(grp_fu_705_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1657( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_3_load_reg_1338), + .din1(weight_vecs_0_3_load_reg_1346), + .dout(grp_fu_709_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1658( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_3_load_reg_1338), + .din1(weight_vecs_1_3_load_reg_1351), + .dout(grp_fu_713_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1659( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_3_load_reg_1338), + .din1(weight_vecs_2_3_load_reg_1356), + .dout(grp_fu_717_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1660( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_3_load_reg_1338), + .din1(weight_vecs_3_3_load_reg_1361), + .dout(grp_fu_721_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_759_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_reg_650 <= add_ln149_fu_945_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_reg_650 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_1104 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ii_reg_617 <= select_ln147_26_reg_1108; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_617 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_759_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten17_reg_606 <= add_ln147_7_fu_725_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten17_reg_606 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_759_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_628 <= select_ln148_21_fu_957_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_628 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_1104 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + jj_reg_639 <= select_ln148_19_reg_1113; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_639 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_759_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + empty_156_reg_1118 <= empty_156_fu_907_p2; + newIndex_reg_1138 <= {{select_ln148_fu_887_p3[5:2]}}; + select_ln148_20_reg_1123 <= select_ln148_20_fu_923_p3; + trunc_ln149_reg_1131 <= trunc_ln149_fu_931_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln147_reg_1104 <= icmp_ln147_fu_759_p2; + icmp_ln147_reg_1104_pp0_iter1_reg <= icmp_ln147_reg_1104; + newIndex_reg_1138_pp0_iter1_reg <= newIndex_reg_1138; + select_ln148_20_reg_1123_pp0_iter1_reg <= select_ln148_20_reg_1123; + trunc_ln149_reg_1131_pp0_iter1_reg <= trunc_ln149_reg_1131; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln147_reg_1104_pp0_iter2_reg <= icmp_ln147_reg_1104_pp0_iter1_reg; + icmp_ln147_reg_1104_pp0_iter3_reg <= icmp_ln147_reg_1104_pp0_iter2_reg; + icmp_ln147_reg_1104_pp0_iter4_reg <= icmp_ln147_reg_1104_pp0_iter3_reg; + icmp_ln147_reg_1104_pp0_iter5_reg <= icmp_ln147_reg_1104_pp0_iter4_reg; + icmp_ln147_reg_1104_pp0_iter6_reg <= icmp_ln147_reg_1104_pp0_iter5_reg; + icmp_ln147_reg_1104_pp0_iter7_reg <= icmp_ln147_reg_1104_pp0_iter6_reg; + newIndex_reg_1138_pp0_iter2_reg <= newIndex_reg_1138_pp0_iter1_reg; + newIndex_reg_1138_pp0_iter3_reg <= newIndex_reg_1138_pp0_iter2_reg; + newIndex_reg_1138_pp0_iter4_reg <= newIndex_reg_1138_pp0_iter3_reg; + newIndex_reg_1138_pp0_iter5_reg <= newIndex_reg_1138_pp0_iter4_reg; + newIndex_reg_1138_pp0_iter6_reg <= newIndex_reg_1138_pp0_iter5_reg; + newIndex_reg_1138_pp0_iter7_reg <= newIndex_reg_1138_pp0_iter6_reg; + select_ln148_20_reg_1123_pp0_iter2_reg <= select_ln148_20_reg_1123_pp0_iter1_reg; + select_ln148_20_reg_1123_pp0_iter3_reg <= select_ln148_20_reg_1123_pp0_iter2_reg; + select_ln148_20_reg_1123_pp0_iter4_reg <= select_ln148_20_reg_1123_pp0_iter3_reg; + select_ln148_20_reg_1123_pp0_iter5_reg <= select_ln148_20_reg_1123_pp0_iter4_reg; + select_ln148_20_reg_1123_pp0_iter6_reg <= select_ln148_20_reg_1123_pp0_iter5_reg; + select_ln148_20_reg_1123_pp0_iter7_reg <= select_ln148_20_reg_1123_pp0_iter6_reg; + trunc_ln149_reg_1131_pp0_iter2_reg <= trunc_ln149_reg_1131_pp0_iter1_reg; + trunc_ln149_reg_1131_pp0_iter3_reg <= trunc_ln149_reg_1131_pp0_iter2_reg; + trunc_ln149_reg_1131_pp0_iter4_reg <= trunc_ln149_reg_1131_pp0_iter3_reg; + trunc_ln149_reg_1131_pp0_iter5_reg <= trunc_ln149_reg_1131_pp0_iter4_reg; + trunc_ln149_reg_1131_pp0_iter6_reg <= trunc_ln149_reg_1131_pp0_iter5_reg; + trunc_ln149_reg_1131_pp0_iter7_reg <= trunc_ln149_reg_1131_pp0_iter6_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_1104_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_load_reg_1254 <= ifmap_vec_0_q0; + ifmap_vec_1_load_reg_1282 <= ifmap_vec_1_q0; + ifmap_vec_2_load_reg_1310 <= ifmap_vec_2_q0; + ifmap_vec_3_load_reg_1338 <= ifmap_vec_3_q0; + weight_vecs_0_0_load_reg_1262 <= weight_vecs_0_0_q0; + weight_vecs_0_1_load_reg_1290 <= weight_vecs_0_1_q0; + weight_vecs_0_2_load_reg_1318 <= weight_vecs_0_2_q0; + weight_vecs_0_3_load_reg_1346 <= weight_vecs_0_3_q0; + weight_vecs_1_0_load_reg_1267 <= weight_vecs_1_0_q0; + weight_vecs_1_1_load_reg_1295 <= weight_vecs_1_1_q0; + weight_vecs_1_2_load_reg_1323 <= weight_vecs_1_2_q0; + weight_vecs_1_3_load_reg_1351 <= weight_vecs_1_3_q0; + weight_vecs_2_0_load_reg_1272 <= weight_vecs_2_0_q0; + weight_vecs_2_1_load_reg_1300 <= weight_vecs_2_1_q0; + weight_vecs_2_2_load_reg_1328 <= weight_vecs_2_2_q0; + weight_vecs_2_3_load_reg_1356 <= weight_vecs_2_3_q0; + weight_vecs_3_0_load_reg_1277 <= weight_vecs_3_0_q0; + weight_vecs_3_1_load_reg_1305 <= weight_vecs_3_1_q0; + weight_vecs_3_2_load_reg_1333 <= weight_vecs_3_2_q0; + weight_vecs_3_3_load_reg_1361 <= weight_vecs_3_3_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_1104_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul27_1_1_reg_1391 <= grp_fu_681_p2; + mul27_1_2_reg_1396 <= grp_fu_685_p2; + mul27_1_3_reg_1401 <= grp_fu_689_p2; + mul27_1_reg_1386 <= grp_fu_677_p2; + mul27_2_1_reg_1411 <= grp_fu_697_p2; + mul27_2_2_reg_1416 <= grp_fu_701_p2; + mul27_2_3_reg_1421 <= grp_fu_705_p2; + mul27_2_reg_1406 <= grp_fu_693_p2; + mul27_3_1_reg_1431 <= grp_fu_713_p2; + mul27_3_2_reg_1436 <= grp_fu_717_p2; + mul27_3_3_reg_1441 <= grp_fu_721_p2; + mul27_3_reg_1426 <= grp_fu_709_p2; + mul_1_reg_1371 <= grp_fu_665_p2; + mul_2_reg_1376 <= grp_fu_669_p2; + mul_3_reg_1381 <= grp_fu_673_p2; + mul_reg_1366 <= grp_fu_661_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_759_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln147_26_reg_1108 <= select_ln147_26_fu_793_p3; + select_ln148_19_reg_1113 <= select_ln148_19_fu_895_p3; + end +end + +always @ (*) begin + if ((icmp_ln147_fu_759_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_1104 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_621_p4 = select_ln147_26_reg_1108; + end else begin + ap_phi_mux_ii_phi_fu_621_p4 = ii_reg_617; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_1104 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_643_p4 = select_ln148_19_reg_1113; + end else begin + ap_phi_mux_jj_phi_fu_643_p4 = jj_reg_639; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_1_ce0 = 1'b1; + end else begin + ifmap_vec_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_2_ce0 = 1'b1; + end else begin + ifmap_vec_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_3_ce0 = 1'b1; + end else begin + ifmap_vec_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_0_ce0 = 1'b1; + end else begin + products_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_0_we0 = 1'b1; + end else begin + products_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_1_ce0 = 1'b1; + end else begin + products_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_1_we0 = 1'b1; + end else begin + products_0_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_2_ce0 = 1'b1; + end else begin + products_0_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_2_we0 = 1'b1; + end else begin + products_0_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_3_ce0 = 1'b1; + end else begin + products_0_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_3_we0 = 1'b1; + end else begin + products_0_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_0_ce0 = 1'b1; + end else begin + products_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_0_we0 = 1'b1; + end else begin + products_1_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_1_ce0 = 1'b1; + end else begin + products_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_1_we0 = 1'b1; + end else begin + products_1_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_2_ce0 = 1'b1; + end else begin + products_1_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_2_we0 = 1'b1; + end else begin + products_1_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_3_ce0 = 1'b1; + end else begin + products_1_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_3_we0 = 1'b1; + end else begin + products_1_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_0_ce0 = 1'b1; + end else begin + products_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_0_we0 = 1'b1; + end else begin + products_2_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_1_ce0 = 1'b1; + end else begin + products_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_1_we0 = 1'b1; + end else begin + products_2_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_2_ce0 = 1'b1; + end else begin + products_2_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_2_we0 = 1'b1; + end else begin + products_2_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_3_ce0 = 1'b1; + end else begin + products_2_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_3_we0 = 1'b1; + end else begin + products_2_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_0_ce0 = 1'b1; + end else begin + products_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_0_we0 = 1'b1; + end else begin + products_3_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_1_ce0 = 1'b1; + end else begin + products_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_1_we0 = 1'b1; + end else begin + products_3_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_2_ce0 = 1'b1; + end else begin + products_3_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_2_we0 = 1'b1; + end else begin + products_3_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_3_ce0 = 1'b1; + end else begin + products_3_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_3_we0 = 1'b1; + end else begin + products_3_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_1_ce0 = 1'b1; + end else begin + weight_vecs_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_2_ce0 = 1'b1; + end else begin + weight_vecs_0_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_3_ce0 = 1'b1; + end else begin + weight_vecs_0_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_1_0_ce0 = 1'b1; + end else begin + weight_vecs_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_1_1_ce0 = 1'b1; + end else begin + weight_vecs_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_1_2_ce0 = 1'b1; + end else begin + weight_vecs_1_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_1_3_ce0 = 1'b1; + end else begin + weight_vecs_1_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_2_0_ce0 = 1'b1; + end else begin + weight_vecs_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_2_1_ce0 = 1'b1; + end else begin + weight_vecs_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_2_2_ce0 = 1'b1; + end else begin + weight_vecs_2_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_2_3_ce0 = 1'b1; + end else begin + weight_vecs_2_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_3_0_ce0 = 1'b1; + end else begin + weight_vecs_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_3_1_ce0 = 1'b1; + end else begin + weight_vecs_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_3_2_ce0 = 1'b1; + end else begin + weight_vecs_3_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_3_3_ce0 = 1'b1; + end else begin + weight_vecs_3_3_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln147_fu_759_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter8 == 1'b1) & (ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter8 == 1'b1) & (ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln147_fu_759_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state11; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_7_fu_725_p2 = (indvar_flatten17_reg_606 + 8'd1); + +assign add_ln147_fu_765_p2 = (ap_phi_mux_ii_phi_fu_621_p4 + 2'd1); + +assign add_ln148_7_fu_951_p2 = (indvar_flatten_reg_628 + 7'd1); + +assign add_ln148_fu_881_p2 = (select_ln147_fu_777_p3 + 2'd1); + +assign add_ln149_fu_945_p2 = (select_ln148_fu_887_p3 + 7'd4); + +assign add_ln150_8_fu_917_p2 = (select_ln147_27_fu_845_p3 + zext_ln150_16_fu_913_p1); + +assign add_ln150_fu_753_p2 = (sub_ln150_fu_743_p2 + zext_ln150_10_fu_749_p1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign empty_155_fu_817_p2 = (tmp_cast_fu_813_p1 - select_ln147_32_cast_fu_801_p1); + +assign empty_156_fu_907_p2 = ((sext_ln150_fu_823_p1) + (select_ln148_25_cast_fu_903_p1)); + +assign icmp_ln147_fu_759_p2 = ((indvar_flatten17_reg_606 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln148_fu_771_p2 = ((indvar_flatten_reg_628 == 7'd48) ? 1'b1 : 1'b0); + +assign ifmap_vec_0_address0 = tmp_204_fu_971_p1; + +assign ifmap_vec_1_address0 = tmp_204_fu_971_p1; + +assign ifmap_vec_2_address0 = tmp_204_fu_971_p1; + +assign ifmap_vec_3_address0 = tmp_204_fu_971_p1; + +assign lshr_ln153_1_fu_1054_p3 = {{select_ln148_20_reg_1123_pp0_iter7_reg}, {tmp_63_fu_1044_p4}}; + +assign lshr_ln153_2_fu_1084_p3 = {{select_ln148_20_reg_1123_pp0_iter7_reg}, {tmp_64_fu_1074_p4}}; + +assign lshr_ln153_s_fu_1024_p3 = {{select_ln148_20_reg_1123_pp0_iter7_reg}, {tmp_s_fu_1014_p4}}; + +assign lshr_ln_fu_995_p3 = {{select_ln148_20_reg_1123_pp0_iter7_reg}, {newIndex_reg_1138_pp0_iter7_reg}}; + +assign or_ln147_fu_875_p2 = (xor_ln149_fu_869_p2 | icmp_ln148_fu_771_p2); + +assign or_ln150_5_fu_1039_p2 = (trunc_ln149_reg_1131_pp0_iter7_reg | 6'd2); + +assign or_ln150_6_fu_1069_p2 = (trunc_ln149_reg_1131_pp0_iter7_reg | 6'd3); + +assign or_ln150_fu_1009_p2 = (trunc_ln149_reg_1131_pp0_iter7_reg | 6'd1); + +assign products_0_0_address0 = zext_ln153_fu_1001_p1; + +assign products_0_0_d0 = mul_reg_1366; + +assign products_0_1_address0 = zext_ln153_10_fu_1031_p1; + +assign products_0_1_d0 = mul27_1_reg_1386; + +assign products_0_2_address0 = zext_ln153_11_fu_1061_p1; + +assign products_0_2_d0 = mul27_2_reg_1406; + +assign products_0_3_address0 = zext_ln153_12_fu_1091_p1; + +assign products_0_3_d0 = mul27_3_reg_1426; + +assign products_1_0_address0 = zext_ln153_fu_1001_p1; + +assign products_1_0_d0 = mul_1_reg_1371; + +assign products_1_1_address0 = zext_ln153_10_fu_1031_p1; + +assign products_1_1_d0 = mul27_1_1_reg_1391; + +assign products_1_2_address0 = zext_ln153_11_fu_1061_p1; + +assign products_1_2_d0 = mul27_2_1_reg_1411; + +assign products_1_3_address0 = zext_ln153_12_fu_1091_p1; + +assign products_1_3_d0 = mul27_3_1_reg_1431; + +assign products_2_0_address0 = zext_ln153_fu_1001_p1; + +assign products_2_0_d0 = mul_2_reg_1376; + +assign products_2_1_address0 = zext_ln153_10_fu_1031_p1; + +assign products_2_1_d0 = mul27_1_2_reg_1396; + +assign products_2_2_address0 = zext_ln153_11_fu_1061_p1; + +assign products_2_2_d0 = mul27_2_2_reg_1416; + +assign products_2_3_address0 = zext_ln153_12_fu_1091_p1; + +assign products_2_3_d0 = mul27_3_2_reg_1436; + +assign products_3_0_address0 = zext_ln153_fu_1001_p1; + +assign products_3_0_d0 = mul_3_reg_1381; + +assign products_3_1_address0 = zext_ln153_10_fu_1031_p1; + +assign products_3_1_d0 = mul27_1_3_reg_1401; + +assign products_3_2_address0 = zext_ln153_11_fu_1061_p1; + +assign products_3_2_d0 = mul27_2_3_reg_1421; + +assign products_3_3_address0 = zext_ln153_12_fu_1091_p1; + +assign products_3_3_d0 = mul27_3_3_reg_1441; + +assign select_ln147_25_fu_785_p3 = ((icmp_ln148_fu_771_p2[0:0] == 1'b1) ? 7'd0 : ic_reg_650); + +assign select_ln147_26_fu_793_p3 = ((icmp_ln148_fu_771_p2[0:0] == 1'b1) ? add_ln147_fu_765_p2 : ap_phi_mux_ii_phi_fu_621_p4); + +assign select_ln147_27_fu_845_p3 = ((icmp_ln148_fu_771_p2[0:0] == 1'b1) ? sub_ln150_9_fu_839_p2 : sub_ln150_fu_743_p2); + +assign select_ln147_28_fu_853_p3 = ((icmp_ln148_fu_771_p2[0:0] == 1'b1) ? sub_ln150_9_fu_839_p2 : add_ln150_fu_753_p2); + +assign select_ln147_32_cast_fu_801_p1 = select_ln147_26_fu_793_p3; + +assign select_ln147_fu_777_p3 = ((icmp_ln148_fu_771_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_643_p4); + +assign select_ln148_19_fu_895_p3 = ((or_ln147_fu_875_p2[0:0] == 1'b1) ? select_ln147_fu_777_p3 : add_ln148_fu_881_p2); + +assign select_ln148_20_fu_923_p3 = ((or_ln147_fu_875_p2[0:0] == 1'b1) ? select_ln147_28_fu_853_p3 : add_ln150_8_fu_917_p2); + +assign select_ln148_21_fu_957_p3 = ((icmp_ln148_fu_771_p2[0:0] == 1'b1) ? 7'd1 : add_ln148_7_fu_951_p2); + +assign select_ln148_25_cast_fu_903_p1 = select_ln148_19_fu_895_p3; + +assign select_ln148_fu_887_p3 = ((or_ln147_fu_875_p2[0:0] == 1'b1) ? select_ln147_25_fu_785_p3 : 7'd0); + +assign sext_ln150_fu_823_p1 = (empty_155_fu_817_p2); + +assign shl_ln150_mid1_fu_831_p3 = {{add_ln147_fu_765_p2}, {2'd0}}; + +assign shl_ln_fu_735_p3 = {{ap_phi_mux_ii_phi_fu_621_p4}, {2'd0}}; + +assign sub_ln150_9_fu_839_p2 = (shl_ln150_mid1_fu_831_p3 - zext_ln150_15_fu_827_p1); + +assign sub_ln150_fu_743_p2 = (shl_ln_fu_735_p3 - zext_ln150_fu_731_p1); + +assign tmp_204_fu_971_p1 = (tmp_94_fu_965_p3); + +assign tmp_63_fu_1044_p4 = {{or_ln150_5_fu_1039_p2[5:2]}}; + +assign tmp_64_fu_1074_p4 = {{or_ln150_6_fu_1069_p2[5:2]}}; + +assign tmp_93_fu_861_p3 = ic_reg_650[32'd6]; + +assign tmp_94_fu_965_p3 = {{empty_156_reg_1118}, {newIndex_reg_1138}}; + +assign tmp_cast_fu_813_p1 = tmp_fu_805_p3; + +assign tmp_fu_805_p3 = {{select_ln147_26_fu_793_p3}, {2'd0}}; + +assign tmp_s_fu_1014_p4 = {{or_ln150_fu_1009_p2[5:2]}}; + +assign trunc_ln149_fu_931_p1 = select_ln148_fu_887_p3[5:0]; + +assign weight_vecs_0_0_address0 = tmp_204_fu_971_p1; + +assign weight_vecs_0_1_address0 = tmp_204_fu_971_p1; + +assign weight_vecs_0_2_address0 = tmp_204_fu_971_p1; + +assign weight_vecs_0_3_address0 = tmp_204_fu_971_p1; + +assign weight_vecs_1_0_address0 = tmp_204_fu_971_p1; + +assign weight_vecs_1_1_address0 = tmp_204_fu_971_p1; + +assign weight_vecs_1_2_address0 = tmp_204_fu_971_p1; + +assign weight_vecs_1_3_address0 = tmp_204_fu_971_p1; + +assign weight_vecs_2_0_address0 = tmp_204_fu_971_p1; + +assign weight_vecs_2_1_address0 = tmp_204_fu_971_p1; + +assign weight_vecs_2_2_address0 = tmp_204_fu_971_p1; + +assign weight_vecs_2_3_address0 = tmp_204_fu_971_p1; + +assign weight_vecs_3_0_address0 = tmp_204_fu_971_p1; + +assign weight_vecs_3_1_address0 = tmp_204_fu_971_p1; + +assign weight_vecs_3_2_address0 = tmp_204_fu_971_p1; + +assign weight_vecs_3_3_address0 = tmp_204_fu_971_p1; + +assign xor_ln149_fu_869_p2 = (tmp_93_fu_861_p3 ^ 1'd1); + +assign zext_ln150_10_fu_749_p1 = ap_phi_mux_jj_phi_fu_643_p4; + +assign zext_ln150_15_fu_827_p1 = add_ln147_fu_765_p2; + +assign zext_ln150_16_fu_913_p1 = add_ln148_fu_881_p2; + +assign zext_ln150_fu_731_p1 = ap_phi_mux_ii_phi_fu_621_p4; + +assign zext_ln153_10_fu_1031_p1 = lshr_ln153_s_fu_1024_p3; + +assign zext_ln153_11_fu_1061_p1 = lshr_ln153_1_fu_1054_p3; + +assign zext_ln153_12_fu_1091_p1 = lshr_ln153_2_fu_1084_p3; + +assign zext_ln153_fu_1001_p1 = lshr_ln_fu_995_p3; + +endmodule //td_fused_top_tdf11_dot_product +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + indices_2_out_din, + indices_2_out_full_n, + indices_2_out_write, + indices_2_out1_din, + indices_2_out1_full_n, + indices_2_out1_write, + write_r_din, + write_r_full_n, + write_r_write +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [6:0] indices_2_out_din; +input indices_2_out_full_n; +output indices_2_out_write; +output [6:0] indices_2_out1_din; +input indices_2_out1_full_n; +output indices_2_out1_write; +output write_r_din; +input write_r_full_n; +output write_r_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg indices_0_write; +reg indices_1_write; +reg indices_2_out_write; +reg indices_2_out1_write; +reg write_r_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [15:0] i_9; +reg [15:0] j_9; +reg [15:0] k_9; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg indices_2_out_blk_n; +reg indices_2_out1_blk_n; +reg write_r_blk_n; +reg [0:0] ap_phi_mux_j_20_flag_0_i_phi_fu_90_p6; +reg ap_block_state1; +wire [0:0] icmp_ln227_fu_161_p2; +wire [0:0] icmp_ln230_fu_174_p2; +reg [15:0] ap_phi_mux_j_20_new_0_i_phi_fu_104_p6; +wire [15:0] add_ln229_fu_167_p2; +reg [15:0] ap_phi_mux_k_20_new_0_i_phi_fu_117_p6; +wire [15:0] add_ln226_fu_154_p2; +wire [15:0] select_ln233_fu_192_p3; +wire [6:0] trunc_ln224_fu_141_p1; +wire [15:0] add_ln232_fu_180_p2; +wire [0:0] icmp_ln233_fu_186_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_9 = 16'd0; +#0 j_9 = 16'd0; +#0 k_9 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln230_fu_174_p2 == 1'd1) & (icmp_ln227_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_9 <= select_ln233_fu_192_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_20_flag_0_i_phi_fu_90_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j_9 <= ap_phi_mux_j_20_new_0_i_phi_fu_104_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k_9 <= ap_phi_mux_k_20_new_0_i_phi_fu_117_p6; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln227_fu_161_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_20_flag_0_i_phi_fu_90_p6 = 1'd0; + end else if ((((icmp_ln230_fu_174_p2 == 1'd0) & (icmp_ln227_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln230_fu_174_p2 == 1'd1) & (icmp_ln227_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_20_flag_0_i_phi_fu_90_p6 = 1'd1; + end else begin + ap_phi_mux_j_20_flag_0_i_phi_fu_90_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln227_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln230_fu_174_p2 == 1'd0)) begin + ap_phi_mux_j_20_new_0_i_phi_fu_104_p6 = add_ln229_fu_167_p2; + end else if ((icmp_ln230_fu_174_p2 == 1'd1)) begin + ap_phi_mux_j_20_new_0_i_phi_fu_104_p6 = 16'd0; + end else begin + ap_phi_mux_j_20_new_0_i_phi_fu_104_p6 = 'bx; + end + end else begin + ap_phi_mux_j_20_new_0_i_phi_fu_104_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln227_fu_161_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_20_new_0_i_phi_fu_117_p6 = add_ln226_fu_154_p2; + end else if ((((icmp_ln230_fu_174_p2 == 1'd0) & (icmp_ln227_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln230_fu_174_p2 == 1'd1) & (icmp_ln227_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_20_new_0_i_phi_fu_117_p6 = 16'd0; + end else begin + ap_phi_mux_k_20_new_0_i_phi_fu_117_p6 = 'bx; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_blk_n = indices_2_out1_full_n; + end else begin + indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_write = 1'b1; + end else begin + indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_blk_n = indices_2_out_full_n; + end else begin + indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_write = 1'b1; + end else begin + indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_r_blk_n = write_r_full_n; + end else begin + write_r_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_r_write = 1'b1; + end else begin + write_r_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln226_fu_154_p2 = (k_9 + 16'd1); + +assign add_ln229_fu_167_p2 = (j_9 + 16'd1); + +assign add_ln232_fu_180_p2 = (i_9 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign icmp_ln227_fu_161_p2 = ((add_ln226_fu_154_p2 == 16'd128) ? 1'b1 : 1'b0); + +assign icmp_ln230_fu_174_p2 = ((add_ln229_fu_167_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign icmp_ln233_fu_186_p2 = ((add_ln232_fu_180_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign indices_0_din = i_9; + +assign indices_1_din = j_9; + +assign indices_2_out1_din = trunc_ln224_fu_141_p1; + +assign indices_2_out_din = trunc_ln224_fu_141_p1; + +assign select_ln233_fu_192_p3 = ((icmp_ln233_fu_186_p2[0:0] == 1'b1) ? 16'd0 : add_ln232_fu_180_p2); + +assign start_out = real_start; + +assign trunc_ln224_fu_141_p1 = k_9[6:0]; + +assign write_r_din = ((k_9 == 16'd127) ? 1'b1 : 1'b0); + +endmodule //td_fused_top_tdf11_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_l2_accum ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + l2_products_0_address0, + l2_products_0_ce0, + l2_products_0_q0, + l2_products_0_address1, + l2_products_0_ce1, + l2_products_0_q1, + l2_products_1_address0, + l2_products_1_ce0, + l2_products_1_q0, + l2_products_1_address1, + l2_products_1_ce1, + l2_products_1_q1, + l2_products_2_address0, + l2_products_2_ce0, + l2_products_2_q0, + l2_products_2_address1, + l2_products_2_ce1, + l2_products_2_q1, + l2_products_3_address0, + l2_products_3_ce0, + l2_products_3_q0, + l2_products_3_address1, + l2_products_3_ce1, + l2_products_3_q1, + l2_products_4_address0, + l2_products_4_ce0, + l2_products_4_q0, + l2_products_4_address1, + l2_products_4_ce1, + l2_products_4_q1, + l2_products_5_address0, + l2_products_5_ce0, + l2_products_5_q0, + l2_products_5_address1, + l2_products_5_ce1, + l2_products_5_q1, + l2_products_6_address0, + l2_products_6_ce0, + l2_products_6_q0, + l2_products_6_address1, + l2_products_6_ce1, + l2_products_6_q1, + l2_products_7_address0, + l2_products_7_ce0, + l2_products_7_q0, + l2_products_7_address1, + l2_products_7_ce1, + l2_products_7_q1, + l2_partial_sums_0_address0, + l2_partial_sums_0_ce0, + l2_partial_sums_0_we0, + l2_partial_sums_0_d0, + l2_partial_sums_0_address1, + l2_partial_sums_0_ce1, + l2_partial_sums_0_we1, + l2_partial_sums_0_d1, + l2_partial_sums_1_address0, + l2_partial_sums_1_ce0, + l2_partial_sums_1_we0, + l2_partial_sums_1_d0, + l2_partial_sums_1_address1, + l2_partial_sums_1_ce1, + l2_partial_sums_1_we1, + l2_partial_sums_1_d1, + l2_partial_sums_2_address0, + l2_partial_sums_2_ce0, + l2_partial_sums_2_we0, + l2_partial_sums_2_d0, + l2_partial_sums_2_address1, + l2_partial_sums_2_ce1, + l2_partial_sums_2_we1, + l2_partial_sums_2_d1, + l2_partial_sums_3_address0, + l2_partial_sums_3_ce0, + l2_partial_sums_3_we0, + l2_partial_sums_3_d0, + l2_partial_sums_3_address1, + l2_partial_sums_3_ce1, + l2_partial_sums_3_we1, + l2_partial_sums_3_d1, + l2_partial_sums_4_address0, + l2_partial_sums_4_ce0, + l2_partial_sums_4_we0, + l2_partial_sums_4_d0, + l2_partial_sums_4_address1, + l2_partial_sums_4_ce1, + l2_partial_sums_4_we1, + l2_partial_sums_4_d1, + l2_partial_sums_5_address0, + l2_partial_sums_5_ce0, + l2_partial_sums_5_we0, + l2_partial_sums_5_d0, + l2_partial_sums_5_address1, + l2_partial_sums_5_ce1, + l2_partial_sums_5_we1, + l2_partial_sums_5_d1, + l2_partial_sums_6_address0, + l2_partial_sums_6_ce0, + l2_partial_sums_6_we0, + l2_partial_sums_6_d0, + l2_partial_sums_6_address1, + l2_partial_sums_6_ce1, + l2_partial_sums_6_we1, + l2_partial_sums_6_d1, + l2_partial_sums_7_address0, + l2_partial_sums_7_ce0, + l2_partial_sums_7_we0, + l2_partial_sums_7_d0, + l2_partial_sums_7_address1, + l2_partial_sums_7_ce1, + l2_partial_sums_7_we1, + l2_partial_sums_7_d1 +); + +parameter ap_ST_fsm_state1 = 12'd1; +parameter ap_ST_fsm_state2 = 12'd2; +parameter ap_ST_fsm_state3 = 12'd4; +parameter ap_ST_fsm_state4 = 12'd8; +parameter ap_ST_fsm_state5 = 12'd16; +parameter ap_ST_fsm_state6 = 12'd32; +parameter ap_ST_fsm_state7 = 12'd64; +parameter ap_ST_fsm_state8 = 12'd128; +parameter ap_ST_fsm_state9 = 12'd256; +parameter ap_ST_fsm_state10 = 12'd512; +parameter ap_ST_fsm_state11 = 12'd1024; +parameter ap_ST_fsm_state12 = 12'd2048; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [5:0] l2_products_0_address0; +output l2_products_0_ce0; +input [15:0] l2_products_0_q0; +output [5:0] l2_products_0_address1; +output l2_products_0_ce1; +input [15:0] l2_products_0_q1; +output [5:0] l2_products_1_address0; +output l2_products_1_ce0; +input [15:0] l2_products_1_q0; +output [5:0] l2_products_1_address1; +output l2_products_1_ce1; +input [15:0] l2_products_1_q1; +output [5:0] l2_products_2_address0; +output l2_products_2_ce0; +input [15:0] l2_products_2_q0; +output [5:0] l2_products_2_address1; +output l2_products_2_ce1; +input [15:0] l2_products_2_q1; +output [5:0] l2_products_3_address0; +output l2_products_3_ce0; +input [15:0] l2_products_3_q0; +output [5:0] l2_products_3_address1; +output l2_products_3_ce1; +input [15:0] l2_products_3_q1; +output [5:0] l2_products_4_address0; +output l2_products_4_ce0; +input [15:0] l2_products_4_q0; +output [5:0] l2_products_4_address1; +output l2_products_4_ce1; +input [15:0] l2_products_4_q1; +output [5:0] l2_products_5_address0; +output l2_products_5_ce0; +input [15:0] l2_products_5_q0; +output [5:0] l2_products_5_address1; +output l2_products_5_ce1; +input [15:0] l2_products_5_q1; +output [5:0] l2_products_6_address0; +output l2_products_6_ce0; +input [15:0] l2_products_6_q0; +output [5:0] l2_products_6_address1; +output l2_products_6_ce1; +input [15:0] l2_products_6_q1; +output [5:0] l2_products_7_address0; +output l2_products_7_ce0; +input [15:0] l2_products_7_q0; +output [5:0] l2_products_7_address1; +output l2_products_7_ce1; +input [15:0] l2_products_7_q1; +output [3:0] l2_partial_sums_0_address0; +output l2_partial_sums_0_ce0; +output l2_partial_sums_0_we0; +output [15:0] l2_partial_sums_0_d0; +output [3:0] l2_partial_sums_0_address1; +output l2_partial_sums_0_ce1; +output l2_partial_sums_0_we1; +output [15:0] l2_partial_sums_0_d1; +output [3:0] l2_partial_sums_1_address0; +output l2_partial_sums_1_ce0; +output l2_partial_sums_1_we0; +output [15:0] l2_partial_sums_1_d0; +output [3:0] l2_partial_sums_1_address1; +output l2_partial_sums_1_ce1; +output l2_partial_sums_1_we1; +output [15:0] l2_partial_sums_1_d1; +output [3:0] l2_partial_sums_2_address0; +output l2_partial_sums_2_ce0; +output l2_partial_sums_2_we0; +output [15:0] l2_partial_sums_2_d0; +output [3:0] l2_partial_sums_2_address1; +output l2_partial_sums_2_ce1; +output l2_partial_sums_2_we1; +output [15:0] l2_partial_sums_2_d1; +output [3:0] l2_partial_sums_3_address0; +output l2_partial_sums_3_ce0; +output l2_partial_sums_3_we0; +output [15:0] l2_partial_sums_3_d0; +output [3:0] l2_partial_sums_3_address1; +output l2_partial_sums_3_ce1; +output l2_partial_sums_3_we1; +output [15:0] l2_partial_sums_3_d1; +output [3:0] l2_partial_sums_4_address0; +output l2_partial_sums_4_ce0; +output l2_partial_sums_4_we0; +output [15:0] l2_partial_sums_4_d0; +output [3:0] l2_partial_sums_4_address1; +output l2_partial_sums_4_ce1; +output l2_partial_sums_4_we1; +output [15:0] l2_partial_sums_4_d1; +output [3:0] l2_partial_sums_5_address0; +output l2_partial_sums_5_ce0; +output l2_partial_sums_5_we0; +output [15:0] l2_partial_sums_5_d0; +output [3:0] l2_partial_sums_5_address1; +output l2_partial_sums_5_ce1; +output l2_partial_sums_5_we1; +output [15:0] l2_partial_sums_5_d1; +output [3:0] l2_partial_sums_6_address0; +output l2_partial_sums_6_ce0; +output l2_partial_sums_6_we0; +output [15:0] l2_partial_sums_6_d0; +output [3:0] l2_partial_sums_6_address1; +output l2_partial_sums_6_ce1; +output l2_partial_sums_6_we1; +output [15:0] l2_partial_sums_6_d1; +output [3:0] l2_partial_sums_7_address0; +output l2_partial_sums_7_ce0; +output l2_partial_sums_7_we0; +output [15:0] l2_partial_sums_7_d0; +output [3:0] l2_partial_sums_7_address1; +output l2_partial_sums_7_ce1; +output l2_partial_sums_7_we1; +output [15:0] l2_partial_sums_7_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg l2_products_0_ce0; +reg l2_products_0_ce1; +reg l2_products_1_ce0; +reg l2_products_1_ce1; +reg l2_products_2_ce0; +reg l2_products_2_ce1; +reg l2_products_3_ce0; +reg l2_products_3_ce1; +reg l2_products_4_ce0; +reg l2_products_4_ce1; +reg l2_products_5_ce0; +reg l2_products_5_ce1; +reg l2_products_6_ce0; +reg l2_products_6_ce1; +reg l2_products_7_ce0; +reg l2_products_7_ce1; +reg l2_partial_sums_0_ce0; +reg l2_partial_sums_0_we0; +reg l2_partial_sums_0_ce1; +reg l2_partial_sums_0_we1; +reg l2_partial_sums_1_ce0; +reg l2_partial_sums_1_we0; +reg l2_partial_sums_1_ce1; +reg l2_partial_sums_1_we1; +reg l2_partial_sums_2_ce0; +reg l2_partial_sums_2_we0; +reg l2_partial_sums_2_ce1; +reg l2_partial_sums_2_we1; +reg l2_partial_sums_3_ce0; +reg l2_partial_sums_3_we0; +reg l2_partial_sums_3_ce1; +reg l2_partial_sums_3_we1; +reg l2_partial_sums_4_ce0; +reg l2_partial_sums_4_we0; +reg l2_partial_sums_4_ce1; +reg l2_partial_sums_4_we1; +reg l2_partial_sums_5_ce0; +reg l2_partial_sums_5_we0; +reg l2_partial_sums_5_ce1; +reg l2_partial_sums_5_we1; +reg l2_partial_sums_6_ce0; +reg l2_partial_sums_6_we0; +reg l2_partial_sums_6_ce1; +reg l2_partial_sums_6_we1; +reg l2_partial_sums_7_ce0; +reg l2_partial_sums_7_we0; +reg l2_partial_sums_7_ce1; +reg l2_partial_sums_7_we1; + +reg ap_done_reg; + reg [11:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln40_fu_704_p2; +reg [3:0] add_ln40_reg_968; +wire ap_CS_fsm_state2; +wire [2:0] trunc_ln52_fu_716_p1; +reg [2:0] trunc_ln52_reg_976; +wire [0:0] icmp_ln40_fu_710_p2; +wire [3:0] out_idx_3_fu_726_p2; +reg [3:0] out_idx_3_reg_981; +wire [63:0] zext_ln54_fu_732_p1; +reg [63:0] zext_ln54_reg_986; +wire [63:0] zext_ln54_7_fu_736_p1; +reg [63:0] zext_ln54_7_reg_998; +wire [2:0] add_ln45_fu_740_p2; +reg [2:0] add_ln45_reg_1010; +wire ap_CS_fsm_state3; +reg [15:0] l2_products_0_load_reg_1098; +wire ap_CS_fsm_state4; +reg [15:0] l2_products_1_load_reg_1103; +reg [15:0] l2_products_2_load_reg_1108; +reg [15:0] l2_products_3_load_reg_1113; +reg [15:0] l2_products_4_load_reg_1118; +reg [15:0] l2_products_5_load_reg_1123; +reg [15:0] l2_products_6_load_reg_1128; +reg [15:0] l2_products_7_load_reg_1133; +reg [15:0] l2_products_0_load_3_reg_1138; +reg [15:0] l2_products_1_load_3_reg_1143; +reg [15:0] l2_products_2_load_3_reg_1148; +reg [15:0] l2_products_3_load_3_reg_1153; +reg [15:0] l2_products_4_load_1_reg_1158; +reg [15:0] l2_products_5_load_1_reg_1163; +reg [15:0] l2_products_6_load_1_reg_1168; +reg [15:0] l2_products_7_load_1_reg_1173; +wire ap_CS_fsm_state5; +reg [3:0] group_reg_538; +wire [0:0] icmp_ln45_fu_786_p2; +reg ap_block_state1; +reg [2:0] i_1_1_reg_549; +wire ap_CS_fsm_state12; +wire [63:0] zext_ln54_8_fu_755_p1; +wire [63:0] zext_ln54_9_fu_774_p1; +reg [15:0] add14_lcssa23_fu_74; +wire [15:0] grp_fu_560_p2; +reg [15:0] add14_1_lcssa25_fu_78; +wire [15:0] grp_fu_564_p2; +reg [15:0] add14_2_lcssa27_fu_82; +wire [15:0] grp_fu_568_p2; +reg [15:0] add14_3_lcssa29_fu_86; +wire [15:0] grp_fu_572_p2; +reg [15:0] add14_4_lcssa31_fu_90; +wire [15:0] grp_fu_576_p2; +reg [15:0] add14_5_lcssa33_fu_94; +wire [15:0] grp_fu_580_p2; +reg [15:0] add14_6_lcssa35_fu_98; +wire [15:0] grp_fu_584_p2; +reg [15:0] add14_7_lcssa37_fu_102; +wire [15:0] grp_fu_588_p2; +reg [15:0] add14_8_lcssa39_fu_106; +wire [15:0] grp_fu_592_p2; +reg [15:0] add14_9_lcssa41_fu_110; +wire [15:0] grp_fu_596_p2; +reg [15:0] add14_10_lcssa43_fu_114; +wire [15:0] grp_fu_600_p2; +reg [15:0] add14_11_lcssa45_fu_118; +wire [15:0] grp_fu_604_p2; +reg [15:0] add14_12_lcssa47_fu_122; +wire [15:0] grp_fu_608_p2; +reg [15:0] add14_13_lcssa49_fu_126; +wire [15:0] grp_fu_612_p2; +reg [15:0] add14_14_lcssa51_fu_130; +wire [15:0] grp_fu_616_p2; +reg [15:0] add14_15_lcssa53_fu_134; +wire [15:0] grp_fu_620_p2; +wire [3:0] out_idx_fu_720_p2; +wire [6:0] tmp_s_fu_746_p4; +wire [6:0] tmp_62_fu_767_p3; +reg [11:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 12'd1; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1768( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_lcssa23_fu_74), + .din1(l2_products_0_load_reg_1098), + .dout(grp_fu_560_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1769( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_1_lcssa25_fu_78), + .din1(l2_products_1_load_reg_1103), + .dout(grp_fu_564_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1770( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_2_lcssa27_fu_82), + .din1(l2_products_2_load_reg_1108), + .dout(grp_fu_568_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1771( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_3_lcssa29_fu_86), + .din1(l2_products_3_load_reg_1113), + .dout(grp_fu_572_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1772( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_4_lcssa31_fu_90), + .din1(l2_products_4_load_reg_1118), + .dout(grp_fu_576_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1773( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_5_lcssa33_fu_94), + .din1(l2_products_5_load_reg_1123), + .dout(grp_fu_580_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1774( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_6_lcssa35_fu_98), + .din1(l2_products_6_load_reg_1128), + .dout(grp_fu_584_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1775( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_7_lcssa37_fu_102), + .din1(l2_products_7_load_reg_1133), + .dout(grp_fu_588_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1776( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_8_lcssa39_fu_106), + .din1(l2_products_0_load_3_reg_1138), + .dout(grp_fu_592_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1777( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_9_lcssa41_fu_110), + .din1(l2_products_1_load_3_reg_1143), + .dout(grp_fu_596_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1778( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_10_lcssa43_fu_114), + .din1(l2_products_2_load_3_reg_1148), + .dout(grp_fu_600_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1779( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_11_lcssa45_fu_118), + .din1(l2_products_3_load_3_reg_1153), + .dout(grp_fu_604_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1780( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_12_lcssa47_fu_122), + .din1(l2_products_4_load_1_reg_1158), + .dout(grp_fu_608_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1781( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_13_lcssa49_fu_126), + .din1(l2_products_5_load_1_reg_1163), + .dout(grp_fu_612_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1782( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_14_lcssa51_fu_130), + .din1(l2_products_6_load_1_reg_1168), + .dout(grp_fu_616_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1783( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_15_lcssa53_fu_134), + .din1(l2_products_7_load_1_reg_1173), + .dout(grp_fu_620_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln40_fu_710_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + group_reg_538 <= 4'd0; + end else if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + group_reg_538 <= add_ln40_reg_968; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + i_1_1_reg_549 <= add_ln45_reg_1010; + end else if (((icmp_ln40_fu_710_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + i_1_1_reg_549 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + add14_10_lcssa43_fu_114 <= grp_fu_600_p2; + add14_11_lcssa45_fu_118 <= grp_fu_604_p2; + add14_12_lcssa47_fu_122 <= grp_fu_608_p2; + add14_13_lcssa49_fu_126 <= grp_fu_612_p2; + add14_14_lcssa51_fu_130 <= grp_fu_616_p2; + add14_15_lcssa53_fu_134 <= grp_fu_620_p2; + add14_1_lcssa25_fu_78 <= grp_fu_564_p2; + add14_2_lcssa27_fu_82 <= grp_fu_568_p2; + add14_3_lcssa29_fu_86 <= grp_fu_572_p2; + add14_4_lcssa31_fu_90 <= grp_fu_576_p2; + add14_5_lcssa33_fu_94 <= grp_fu_580_p2; + add14_6_lcssa35_fu_98 <= grp_fu_584_p2; + add14_7_lcssa37_fu_102 <= grp_fu_588_p2; + add14_8_lcssa39_fu_106 <= grp_fu_592_p2; + add14_9_lcssa41_fu_110 <= grp_fu_596_p2; + add14_lcssa23_fu_74 <= grp_fu_560_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln40_reg_968 <= add_ln40_fu_704_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + add_ln45_reg_1010 <= add_ln45_fu_740_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + l2_products_0_load_3_reg_1138 <= l2_products_0_q0; + l2_products_0_load_reg_1098 <= l2_products_0_q1; + l2_products_1_load_3_reg_1143 <= l2_products_1_q0; + l2_products_1_load_reg_1103 <= l2_products_1_q1; + l2_products_2_load_3_reg_1148 <= l2_products_2_q0; + l2_products_2_load_reg_1108 <= l2_products_2_q1; + l2_products_3_load_3_reg_1153 <= l2_products_3_q0; + l2_products_3_load_reg_1113 <= l2_products_3_q1; + l2_products_4_load_1_reg_1158 <= l2_products_4_q0; + l2_products_4_load_reg_1118 <= l2_products_4_q1; + l2_products_5_load_1_reg_1163 <= l2_products_5_q0; + l2_products_5_load_reg_1123 <= l2_products_5_q1; + l2_products_6_load_1_reg_1168 <= l2_products_6_q0; + l2_products_6_load_reg_1128 <= l2_products_6_q1; + l2_products_7_load_1_reg_1173 <= l2_products_7_q0; + l2_products_7_load_reg_1133 <= l2_products_7_q1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln40_fu_710_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + out_idx_3_reg_981[3 : 1] <= out_idx_3_fu_726_p2[3 : 1]; + trunc_ln52_reg_976 <= trunc_ln52_fu_716_p1; + zext_ln54_7_reg_998[3 : 1] <= zext_ln54_7_fu_736_p1[3 : 1]; + zext_ln54_reg_986[3 : 1] <= zext_ln54_fu_732_p1[3 : 1]; + end +end + +always @ (*) begin + if (((icmp_ln40_fu_710_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln40_fu_710_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_0_ce0 = 1'b1; + end else begin + l2_partial_sums_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_0_ce1 = 1'b1; + end else begin + l2_partial_sums_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_0_we0 = 1'b1; + end else begin + l2_partial_sums_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_0_we1 = 1'b1; + end else begin + l2_partial_sums_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_1_ce0 = 1'b1; + end else begin + l2_partial_sums_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_1_ce1 = 1'b1; + end else begin + l2_partial_sums_1_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_1_we0 = 1'b1; + end else begin + l2_partial_sums_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_1_we1 = 1'b1; + end else begin + l2_partial_sums_1_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_2_ce0 = 1'b1; + end else begin + l2_partial_sums_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_2_ce1 = 1'b1; + end else begin + l2_partial_sums_2_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_2_we0 = 1'b1; + end else begin + l2_partial_sums_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_2_we1 = 1'b1; + end else begin + l2_partial_sums_2_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_3_ce0 = 1'b1; + end else begin + l2_partial_sums_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_3_ce1 = 1'b1; + end else begin + l2_partial_sums_3_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_3_we0 = 1'b1; + end else begin + l2_partial_sums_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_3_we1 = 1'b1; + end else begin + l2_partial_sums_3_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_4_ce0 = 1'b1; + end else begin + l2_partial_sums_4_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_4_ce1 = 1'b1; + end else begin + l2_partial_sums_4_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_4_we0 = 1'b1; + end else begin + l2_partial_sums_4_we0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_4_we1 = 1'b1; + end else begin + l2_partial_sums_4_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_5_ce0 = 1'b1; + end else begin + l2_partial_sums_5_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_5_ce1 = 1'b1; + end else begin + l2_partial_sums_5_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_5_we0 = 1'b1; + end else begin + l2_partial_sums_5_we0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_5_we1 = 1'b1; + end else begin + l2_partial_sums_5_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_6_ce0 = 1'b1; + end else begin + l2_partial_sums_6_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_6_ce1 = 1'b1; + end else begin + l2_partial_sums_6_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_6_we0 = 1'b1; + end else begin + l2_partial_sums_6_we0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_6_we1 = 1'b1; + end else begin + l2_partial_sums_6_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_7_ce0 = 1'b1; + end else begin + l2_partial_sums_7_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_7_ce1 = 1'b1; + end else begin + l2_partial_sums_7_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_7_we0 = 1'b1; + end else begin + l2_partial_sums_7_we0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + l2_partial_sums_7_we1 = 1'b1; + end else begin + l2_partial_sums_7_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_0_ce0 = 1'b1; + end else begin + l2_products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_0_ce1 = 1'b1; + end else begin + l2_products_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_1_ce0 = 1'b1; + end else begin + l2_products_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_1_ce1 = 1'b1; + end else begin + l2_products_1_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_2_ce0 = 1'b1; + end else begin + l2_products_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_2_ce1 = 1'b1; + end else begin + l2_products_2_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_3_ce0 = 1'b1; + end else begin + l2_products_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_3_ce1 = 1'b1; + end else begin + l2_products_3_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_4_ce0 = 1'b1; + end else begin + l2_products_4_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_4_ce1 = 1'b1; + end else begin + l2_products_4_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_5_ce0 = 1'b1; + end else begin + l2_products_5_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_5_ce1 = 1'b1; + end else begin + l2_products_5_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_6_ce0 = 1'b1; + end else begin + l2_products_6_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_6_ce1 = 1'b1; + end else begin + l2_products_6_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_7_ce0 = 1'b1; + end else begin + l2_products_7_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_7_ce1 = 1'b1; + end else begin + l2_products_7_ce1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln40_fu_710_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + if (((icmp_ln45_fu_786_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln40_fu_704_p2 = (group_reg_538 + 4'd1); + +assign add_ln45_fu_740_p2 = (i_1_1_reg_549 + 3'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln40_fu_710_p2 = ((group_reg_538 == 4'd8) ? 1'b1 : 1'b0); + +assign icmp_ln45_fu_786_p2 = ((i_1_1_reg_549 == 3'd4) ? 1'b1 : 1'b0); + +assign l2_partial_sums_0_address0 = zext_ln54_7_reg_998; + +assign l2_partial_sums_0_address1 = zext_ln54_reg_986; + +assign l2_partial_sums_0_d0 = add14_8_lcssa39_fu_106; + +assign l2_partial_sums_0_d1 = add14_lcssa23_fu_74; + +assign l2_partial_sums_1_address0 = zext_ln54_7_reg_998; + +assign l2_partial_sums_1_address1 = zext_ln54_reg_986; + +assign l2_partial_sums_1_d0 = add14_9_lcssa41_fu_110; + +assign l2_partial_sums_1_d1 = add14_1_lcssa25_fu_78; + +assign l2_partial_sums_2_address0 = zext_ln54_7_reg_998; + +assign l2_partial_sums_2_address1 = zext_ln54_reg_986; + +assign l2_partial_sums_2_d0 = add14_10_lcssa43_fu_114; + +assign l2_partial_sums_2_d1 = add14_2_lcssa27_fu_82; + +assign l2_partial_sums_3_address0 = zext_ln54_7_reg_998; + +assign l2_partial_sums_3_address1 = zext_ln54_reg_986; + +assign l2_partial_sums_3_d0 = add14_11_lcssa45_fu_118; + +assign l2_partial_sums_3_d1 = add14_3_lcssa29_fu_86; + +assign l2_partial_sums_4_address0 = zext_ln54_7_reg_998; + +assign l2_partial_sums_4_address1 = zext_ln54_reg_986; + +assign l2_partial_sums_4_d0 = add14_12_lcssa47_fu_122; + +assign l2_partial_sums_4_d1 = add14_4_lcssa31_fu_90; + +assign l2_partial_sums_5_address0 = zext_ln54_7_reg_998; + +assign l2_partial_sums_5_address1 = zext_ln54_reg_986; + +assign l2_partial_sums_5_d0 = add14_13_lcssa49_fu_126; + +assign l2_partial_sums_5_d1 = add14_5_lcssa33_fu_94; + +assign l2_partial_sums_6_address0 = zext_ln54_7_reg_998; + +assign l2_partial_sums_6_address1 = zext_ln54_reg_986; + +assign l2_partial_sums_6_d0 = add14_14_lcssa51_fu_130; + +assign l2_partial_sums_6_d1 = add14_6_lcssa35_fu_98; + +assign l2_partial_sums_7_address0 = zext_ln54_7_reg_998; + +assign l2_partial_sums_7_address1 = zext_ln54_reg_986; + +assign l2_partial_sums_7_d0 = add14_15_lcssa53_fu_134; + +assign l2_partial_sums_7_d1 = add14_7_lcssa37_fu_102; + +assign l2_products_0_address0 = zext_ln54_9_fu_774_p1; + +assign l2_products_0_address1 = zext_ln54_8_fu_755_p1; + +assign l2_products_1_address0 = zext_ln54_9_fu_774_p1; + +assign l2_products_1_address1 = zext_ln54_8_fu_755_p1; + +assign l2_products_2_address0 = zext_ln54_9_fu_774_p1; + +assign l2_products_2_address1 = zext_ln54_8_fu_755_p1; + +assign l2_products_3_address0 = zext_ln54_9_fu_774_p1; + +assign l2_products_3_address1 = zext_ln54_8_fu_755_p1; + +assign l2_products_4_address0 = zext_ln54_9_fu_774_p1; + +assign l2_products_4_address1 = zext_ln54_8_fu_755_p1; + +assign l2_products_5_address0 = zext_ln54_9_fu_774_p1; + +assign l2_products_5_address1 = zext_ln54_8_fu_755_p1; + +assign l2_products_6_address0 = zext_ln54_9_fu_774_p1; + +assign l2_products_6_address1 = zext_ln54_8_fu_755_p1; + +assign l2_products_7_address0 = zext_ln54_9_fu_774_p1; + +assign l2_products_7_address1 = zext_ln54_8_fu_755_p1; + +assign out_idx_3_fu_726_p2 = (out_idx_fu_720_p2 | 4'd1); + +assign out_idx_fu_720_p2 = group_reg_538 << 4'd1; + +assign tmp_62_fu_767_p3 = {{i_1_1_reg_549}, {out_idx_3_reg_981}}; + +assign tmp_s_fu_746_p4 = {{{i_1_1_reg_549}, {trunc_ln52_reg_976}}, {1'd0}}; + +assign trunc_ln52_fu_716_p1 = group_reg_538[2:0]; + +assign zext_ln54_7_fu_736_p1 = out_idx_3_fu_726_p2; + +assign zext_ln54_8_fu_755_p1 = tmp_s_fu_746_p4; + +assign zext_ln54_9_fu_774_p1 = tmp_62_fu_767_p3; + +assign zext_ln54_fu_732_p1 = out_idx_fu_720_p2; + +always @ (posedge ap_clk) begin + out_idx_3_reg_981[0] <= 1'b1; + zext_ln54_reg_986[0] <= 1'b0; + zext_ln54_reg_986[63:4] <= 60'b000000000000000000000000000000000000000000000000000000000000; + zext_ln54_7_reg_998[0] <= 1'b1; + zext_ln54_7_reg_998[63:4] <= 60'b000000000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf11_l2_accum +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_l2_multiply75 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + intermediate_fmaps_0_read, + intermediate_fmaps_1_read, + intermediate_fmaps_2_read, + intermediate_fmaps_3_read, + l2_filter_data_0_address0, + l2_filter_data_0_ce0, + l2_filter_data_0_q0, + l2_filter_data_0_address1, + l2_filter_data_0_ce1, + l2_filter_data_0_q1, + l2_filter_data_1_address0, + l2_filter_data_1_ce0, + l2_filter_data_1_q0, + l2_filter_data_1_address1, + l2_filter_data_1_ce1, + l2_filter_data_1_q1, + l2_filter_data_2_address0, + l2_filter_data_2_ce0, + l2_filter_data_2_q0, + l2_filter_data_2_address1, + l2_filter_data_2_ce1, + l2_filter_data_2_q1, + l2_filter_data_3_address0, + l2_filter_data_3_ce0, + l2_filter_data_3_q0, + l2_filter_data_3_address1, + l2_filter_data_3_ce1, + l2_filter_data_3_q1, + l2_products_0_address0, + l2_products_0_ce0, + l2_products_0_we0, + l2_products_0_d0, + l2_products_1_address0, + l2_products_1_ce0, + l2_products_1_we0, + l2_products_1_d0, + l2_products_2_address0, + l2_products_2_ce0, + l2_products_2_we0, + l2_products_2_d0, + l2_products_3_address0, + l2_products_3_ce0, + l2_products_3_we0, + l2_products_3_d0, + l2_products_4_address0, + l2_products_4_ce0, + l2_products_4_we0, + l2_products_4_d0, + l2_products_5_address0, + l2_products_5_ce0, + l2_products_5_we0, + l2_products_5_d0, + l2_products_6_address0, + l2_products_6_ce0, + l2_products_6_we0, + l2_products_6_d0, + l2_products_7_address0, + l2_products_7_ce0, + l2_products_7_we0, + l2_products_7_d0, + indices_23_dout, + indices_23_empty_n, + indices_23_read +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] intermediate_fmaps_0_read; +input [15:0] intermediate_fmaps_1_read; +input [15:0] intermediate_fmaps_2_read; +input [15:0] intermediate_fmaps_3_read; +output [13:0] l2_filter_data_0_address0; +output l2_filter_data_0_ce0; +input [15:0] l2_filter_data_0_q0; +output [13:0] l2_filter_data_0_address1; +output l2_filter_data_0_ce1; +input [15:0] l2_filter_data_0_q1; +output [13:0] l2_filter_data_1_address0; +output l2_filter_data_1_ce0; +input [15:0] l2_filter_data_1_q0; +output [13:0] l2_filter_data_1_address1; +output l2_filter_data_1_ce1; +input [15:0] l2_filter_data_1_q1; +output [13:0] l2_filter_data_2_address0; +output l2_filter_data_2_ce0; +input [15:0] l2_filter_data_2_q0; +output [13:0] l2_filter_data_2_address1; +output l2_filter_data_2_ce1; +input [15:0] l2_filter_data_2_q1; +output [13:0] l2_filter_data_3_address0; +output l2_filter_data_3_ce0; +input [15:0] l2_filter_data_3_q0; +output [13:0] l2_filter_data_3_address1; +output l2_filter_data_3_ce1; +input [15:0] l2_filter_data_3_q1; +output [5:0] l2_products_0_address0; +output l2_products_0_ce0; +output l2_products_0_we0; +output [15:0] l2_products_0_d0; +output [5:0] l2_products_1_address0; +output l2_products_1_ce0; +output l2_products_1_we0; +output [15:0] l2_products_1_d0; +output [5:0] l2_products_2_address0; +output l2_products_2_ce0; +output l2_products_2_we0; +output [15:0] l2_products_2_d0; +output [5:0] l2_products_3_address0; +output l2_products_3_ce0; +output l2_products_3_we0; +output [15:0] l2_products_3_d0; +output [5:0] l2_products_4_address0; +output l2_products_4_ce0; +output l2_products_4_we0; +output [15:0] l2_products_4_d0; +output [5:0] l2_products_5_address0; +output l2_products_5_ce0; +output l2_products_5_we0; +output [15:0] l2_products_5_d0; +output [5:0] l2_products_6_address0; +output l2_products_6_ce0; +output l2_products_6_we0; +output [15:0] l2_products_6_d0; +output [5:0] l2_products_7_address0; +output l2_products_7_ce0; +output l2_products_7_we0; +output [15:0] l2_products_7_d0; +input [6:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg l2_filter_data_0_ce0; +reg l2_filter_data_0_ce1; +reg l2_filter_data_1_ce0; +reg l2_filter_data_1_ce1; +reg l2_filter_data_2_ce0; +reg l2_filter_data_2_ce1; +reg l2_filter_data_3_ce0; +reg l2_filter_data_3_ce1; +reg l2_products_0_ce0; +reg l2_products_0_we0; +reg l2_products_1_ce0; +reg l2_products_1_we0; +reg l2_products_2_ce0; +reg l2_products_2_we0; +reg l2_products_3_ce0; +reg l2_products_3_we0; +reg l2_products_4_ce0; +reg l2_products_4_we0; +reg l2_products_5_ce0; +reg l2_products_5_we0; +reg l2_products_6_ce0; +reg l2_products_6_we0; +reg l2_products_7_ce0; +reg l2_products_7_we0; +reg indices_23_read; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [9:0] i_03_0_i_i_reg_354; +wire [8:0] shl_ln_fu_397_p3; +reg [8:0] shl_ln_reg_552; +wire [0:0] icmp_ln20_fu_405_p2; +reg [0:0] icmp_ln20_reg_557; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln20_reg_557_pp0_iter1_reg; +reg [0:0] icmp_ln20_reg_557_pp0_iter2_reg; +reg [0:0] icmp_ln20_reg_557_pp0_iter3_reg; +reg [0:0] icmp_ln20_reg_557_pp0_iter4_reg; +reg [0:0] icmp_ln20_reg_557_pp0_iter5_reg; +reg [0:0] icmp_ln20_reg_557_pp0_iter6_reg; +wire [9:0] add_ln20_fu_411_p2; +reg ap_enable_reg_pp0_iter0; +reg [1:0] trunc_ln_reg_566; +reg [6:0] tmp_59_reg_591; +reg [6:0] tmp_59_reg_591_pp0_iter1_reg; +reg [6:0] tmp_59_reg_591_pp0_iter2_reg; +reg [6:0] tmp_59_reg_591_pp0_iter3_reg; +reg [6:0] tmp_59_reg_591_pp0_iter4_reg; +reg [6:0] tmp_59_reg_591_pp0_iter5_reg; +reg [6:0] tmp_59_reg_591_pp0_iter6_reg; +wire [15:0] tmp_fu_504_p6; +reg [15:0] tmp_reg_616; +reg [15:0] l2_filter_data_0_load_reg_628; +reg ap_enable_reg_pp0_iter1; +reg [15:0] l2_filter_data_1_load_reg_633; +reg [15:0] l2_filter_data_2_load_reg_638; +reg [15:0] l2_filter_data_3_load_reg_643; +reg [15:0] l2_filter_data_0_load_3_reg_648; +reg [15:0] l2_filter_data_1_load_3_reg_653; +reg [15:0] l2_filter_data_2_load_1_reg_658; +reg [15:0] l2_filter_data_3_load_1_reg_663; +wire [15:0] grp_fu_365_p2; +reg [15:0] mul_i_i_reg_668; +wire [15:0] grp_fu_369_p2; +reg [15:0] mul_1_i_i_reg_673; +wire [15:0] grp_fu_373_p2; +reg [15:0] mul_2_i_i_reg_678; +wire [15:0] grp_fu_377_p2; +reg [15:0] mul_3_i_i_reg_683; +wire [15:0] grp_fu_381_p2; +reg [15:0] mul_4_i_i_reg_688; +wire [15:0] grp_fu_385_p2; +reg [15:0] mul_5_i_i_reg_693; +wire [15:0] grp_fu_389_p2; +reg [15:0] mul_6_i_i_reg_698; +wire [15:0] grp_fu_393_p2; +reg [15:0] mul_7_i_i_reg_703; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +wire [63:0] zext_ln29_fu_464_p1; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln29_30_fu_496_p1; +wire [63:0] zext_ln29_29_fu_520_p1; +wire [2:0] trunc_ln1_fu_417_p4; +wire [8:0] zext_ln24_fu_427_p1; +wire [4:0] lshr_ln_fu_446_p4; +wire [8:0] add_ln25_fu_431_p2; +wire [13:0] tmp_s_fu_456_p3; +wire [4:0] or_ln29_fu_482_p2; +wire [13:0] tmp_61_fu_488_p3; +wire [13:0] tmp_60_fu_513_p3; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1742( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_616), + .din1(l2_filter_data_0_load_reg_628), + .dout(grp_fu_365_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1743( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_616), + .din1(l2_filter_data_1_load_reg_633), + .dout(grp_fu_369_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1744( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_616), + .din1(l2_filter_data_2_load_reg_638), + .dout(grp_fu_373_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1745( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_616), + .din1(l2_filter_data_3_load_reg_643), + .dout(grp_fu_377_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1746( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_616), + .din1(l2_filter_data_0_load_3_reg_648), + .dout(grp_fu_381_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1747( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_616), + .din1(l2_filter_data_1_load_3_reg_653), + .dout(grp_fu_385_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1748( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_616), + .din1(l2_filter_data_2_load_1_reg_658), + .dout(grp_fu_389_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1749( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_616), + .din1(l2_filter_data_3_load_1_reg_663), + .dout(grp_fu_393_p2) +); + +td_fused_top_mux_42_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 16 )) +mux_42_16_1_1_U1750( + .din0(intermediate_fmaps_0_read), + .din1(intermediate_fmaps_1_read), + .din2(intermediate_fmaps_2_read), + .din3(intermediate_fmaps_3_read), + .din4(trunc_ln_reg_566), + .dout(tmp_fu_504_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1) | (indices_23_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1) | (indices_23_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln20_fu_405_p2 == 1'd0))) begin + i_03_0_i_i_reg_354 <= add_ln20_fu_411_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1) | (indices_23_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_03_0_i_i_reg_354 <= 10'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln20_reg_557 <= icmp_ln20_fu_405_p2; + icmp_ln20_reg_557_pp0_iter1_reg <= icmp_ln20_reg_557; + tmp_59_reg_591_pp0_iter1_reg <= tmp_59_reg_591; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln20_reg_557_pp0_iter2_reg <= icmp_ln20_reg_557_pp0_iter1_reg; + icmp_ln20_reg_557_pp0_iter3_reg <= icmp_ln20_reg_557_pp0_iter2_reg; + icmp_ln20_reg_557_pp0_iter4_reg <= icmp_ln20_reg_557_pp0_iter3_reg; + icmp_ln20_reg_557_pp0_iter5_reg <= icmp_ln20_reg_557_pp0_iter4_reg; + icmp_ln20_reg_557_pp0_iter6_reg <= icmp_ln20_reg_557_pp0_iter5_reg; + tmp_59_reg_591_pp0_iter2_reg <= tmp_59_reg_591_pp0_iter1_reg; + tmp_59_reg_591_pp0_iter3_reg <= tmp_59_reg_591_pp0_iter2_reg; + tmp_59_reg_591_pp0_iter4_reg <= tmp_59_reg_591_pp0_iter3_reg; + tmp_59_reg_591_pp0_iter5_reg <= tmp_59_reg_591_pp0_iter4_reg; + tmp_59_reg_591_pp0_iter6_reg <= tmp_59_reg_591_pp0_iter5_reg; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln20_reg_557 == 1'd0))) begin + l2_filter_data_0_load_3_reg_648 <= l2_filter_data_0_q0; + l2_filter_data_0_load_reg_628 <= l2_filter_data_0_q1; + l2_filter_data_1_load_3_reg_653 <= l2_filter_data_1_q0; + l2_filter_data_1_load_reg_633 <= l2_filter_data_1_q1; + l2_filter_data_2_load_1_reg_658 <= l2_filter_data_2_q0; + l2_filter_data_2_load_reg_638 <= l2_filter_data_2_q1; + l2_filter_data_3_load_1_reg_663 <= l2_filter_data_3_q0; + l2_filter_data_3_load_reg_643 <= l2_filter_data_3_q1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln20_reg_557_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_1_i_i_reg_673 <= grp_fu_369_p2; + mul_2_i_i_reg_678 <= grp_fu_373_p2; + mul_3_i_i_reg_683 <= grp_fu_377_p2; + mul_4_i_i_reg_688 <= grp_fu_381_p2; + mul_5_i_i_reg_693 <= grp_fu_385_p2; + mul_6_i_i_reg_698 <= grp_fu_389_p2; + mul_7_i_i_reg_703 <= grp_fu_393_p2; + mul_i_i_reg_668 <= grp_fu_365_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + shl_ln_reg_552[8 : 2] <= shl_ln_fu_397_p3[8 : 2]; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln20_fu_405_p2 == 1'd0))) begin + tmp_59_reg_591 <= {{i_03_0_i_i_reg_354[9:3]}}; + trunc_ln_reg_566 <= {{i_03_0_i_i_reg_354[8:7]}}; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln20_reg_557 == 1'd0))) begin + tmp_reg_616 <= tmp_fu_504_p6; + end +end + +always @ (*) begin + if ((icmp_ln20_fu_405_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1) | (indices_23_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_0_ce0 = 1'b1; + end else begin + l2_filter_data_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_0_ce1 = 1'b1; + end else begin + l2_filter_data_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_1_ce0 = 1'b1; + end else begin + l2_filter_data_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_1_ce1 = 1'b1; + end else begin + l2_filter_data_1_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_2_ce0 = 1'b1; + end else begin + l2_filter_data_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_2_ce1 = 1'b1; + end else begin + l2_filter_data_2_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_3_ce0 = 1'b1; + end else begin + l2_filter_data_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_3_ce1 = 1'b1; + end else begin + l2_filter_data_3_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_0_ce0 = 1'b1; + end else begin + l2_products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln20_reg_557_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_0_we0 = 1'b1; + end else begin + l2_products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_1_ce0 = 1'b1; + end else begin + l2_products_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln20_reg_557_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_1_we0 = 1'b1; + end else begin + l2_products_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_2_ce0 = 1'b1; + end else begin + l2_products_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln20_reg_557_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_2_we0 = 1'b1; + end else begin + l2_products_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_3_ce0 = 1'b1; + end else begin + l2_products_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln20_reg_557_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_3_we0 = 1'b1; + end else begin + l2_products_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_4_ce0 = 1'b1; + end else begin + l2_products_4_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln20_reg_557_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_4_we0 = 1'b1; + end else begin + l2_products_4_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_5_ce0 = 1'b1; + end else begin + l2_products_5_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln20_reg_557_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_5_we0 = 1'b1; + end else begin + l2_products_5_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_6_ce0 = 1'b1; + end else begin + l2_products_6_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln20_reg_557_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_6_we0 = 1'b1; + end else begin + l2_products_6_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_7_ce0 = 1'b1; + end else begin + l2_products_7_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln20_reg_557_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_7_we0 = 1'b1; + end else begin + l2_products_7_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1) | (indices_23_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln20_fu_405_p2 == 1'd1)) & ~((ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln20_fu_405_p2 == 1'd1)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln20_fu_411_p2 = (i_03_0_i_i_reg_354 + 10'd8); + +assign add_ln25_fu_431_p2 = (shl_ln_reg_552 + zext_ln24_fu_427_p1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1) | (indices_23_empty_n == 1'b0)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign icmp_ln20_fu_405_p2 = ((i_03_0_i_i_reg_354 == 10'd512) ? 1'b1 : 1'b0); + +assign l2_filter_data_0_address0 = zext_ln29_30_fu_496_p1; + +assign l2_filter_data_0_address1 = zext_ln29_fu_464_p1; + +assign l2_filter_data_1_address0 = zext_ln29_30_fu_496_p1; + +assign l2_filter_data_1_address1 = zext_ln29_fu_464_p1; + +assign l2_filter_data_2_address0 = zext_ln29_30_fu_496_p1; + +assign l2_filter_data_2_address1 = zext_ln29_fu_464_p1; + +assign l2_filter_data_3_address0 = zext_ln29_30_fu_496_p1; + +assign l2_filter_data_3_address1 = zext_ln29_fu_464_p1; + +assign l2_products_0_address0 = zext_ln29_29_fu_520_p1; + +assign l2_products_0_d0 = mul_i_i_reg_668; + +assign l2_products_1_address0 = zext_ln29_29_fu_520_p1; + +assign l2_products_1_d0 = mul_1_i_i_reg_673; + +assign l2_products_2_address0 = zext_ln29_29_fu_520_p1; + +assign l2_products_2_d0 = mul_2_i_i_reg_678; + +assign l2_products_3_address0 = zext_ln29_29_fu_520_p1; + +assign l2_products_3_d0 = mul_3_i_i_reg_683; + +assign l2_products_4_address0 = zext_ln29_29_fu_520_p1; + +assign l2_products_4_d0 = mul_4_i_i_reg_688; + +assign l2_products_5_address0 = zext_ln29_29_fu_520_p1; + +assign l2_products_5_d0 = mul_5_i_i_reg_693; + +assign l2_products_6_address0 = zext_ln29_29_fu_520_p1; + +assign l2_products_6_d0 = mul_6_i_i_reg_698; + +assign l2_products_7_address0 = zext_ln29_29_fu_520_p1; + +assign l2_products_7_d0 = mul_7_i_i_reg_703; + +assign lshr_ln_fu_446_p4 = {{i_03_0_i_i_reg_354[6:2]}}; + +assign or_ln29_fu_482_p2 = (lshr_ln_fu_446_p4 | 5'd1); + +assign shl_ln_fu_397_p3 = {{indices_23_dout}, {2'd0}}; + +assign tmp_60_fu_513_p3 = {{7'd0}, {tmp_59_reg_591_pp0_iter6_reg}}; + +assign tmp_61_fu_488_p3 = {{or_ln29_fu_482_p2}, {add_ln25_fu_431_p2}}; + +assign tmp_s_fu_456_p3 = {{lshr_ln_fu_446_p4}, {add_ln25_fu_431_p2}}; + +assign trunc_ln1_fu_417_p4 = {{i_03_0_i_i_reg_354[9:7]}}; + +assign zext_ln24_fu_427_p1 = trunc_ln1_fu_417_p4; + +assign zext_ln29_29_fu_520_p1 = tmp_60_fu_513_p3; + +assign zext_ln29_30_fu_496_p1 = tmp_61_fu_488_p3; + +assign zext_ln29_fu_464_p1 = tmp_s_fu_456_p3; + +always @ (posedge ap_clk) begin + shl_ln_reg_552[1:0] <= 2'b00; +end + +endmodule //td_fused_top_tdf11_l2_multiply75 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2_ram (addr0, ce0, d0, we0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 7; +parameter MEM_SIZE = 128; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2_ram.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2( + reset, + clk, + address0, + ce0, + we0, + d0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd128; +parameter AddressWidth = 32'd7; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2_ram td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_l2_writeOutputs_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + write4_dout, + write4_empty_n, + write4_read, + l2_partial_sums_0_address0, + l2_partial_sums_0_ce0, + l2_partial_sums_0_q0, + l2_partial_sums_1_address0, + l2_partial_sums_1_ce0, + l2_partial_sums_1_q0, + l2_partial_sums_2_address0, + l2_partial_sums_2_ce0, + l2_partial_sums_2_q0, + l2_partial_sums_3_address0, + l2_partial_sums_3_ce0, + l2_partial_sums_3_q0, + l2_partial_sums_4_address0, + l2_partial_sums_4_ce0, + l2_partial_sums_4_q0, + l2_partial_sums_5_address0, + l2_partial_sums_5_ce0, + l2_partial_sums_5_q0, + l2_partial_sums_6_address0, + l2_partial_sums_6_ce0, + l2_partial_sums_6_q0, + l2_partial_sums_7_address0, + l2_partial_sums_7_ce0, + l2_partial_sums_7_q0, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_q0 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_pp0_stage0 = 4'd4; +parameter ap_ST_fsm_state34 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [3:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [7:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [0:0] write4_dout; +input write4_empty_n; +output write4_read; +output [3:0] l2_partial_sums_0_address0; +output l2_partial_sums_0_ce0; +input [15:0] l2_partial_sums_0_q0; +output [3:0] l2_partial_sums_1_address0; +output l2_partial_sums_1_ce0; +input [15:0] l2_partial_sums_1_q0; +output [3:0] l2_partial_sums_2_address0; +output l2_partial_sums_2_ce0; +input [15:0] l2_partial_sums_2_q0; +output [3:0] l2_partial_sums_3_address0; +output l2_partial_sums_3_ce0; +input [15:0] l2_partial_sums_3_q0; +output [3:0] l2_partial_sums_4_address0; +output l2_partial_sums_4_ce0; +input [15:0] l2_partial_sums_4_q0; +output [3:0] l2_partial_sums_5_address0; +output l2_partial_sums_5_ce0; +input [15:0] l2_partial_sums_5_q0; +output [3:0] l2_partial_sums_6_address0; +output l2_partial_sums_6_ce0; +input [15:0] l2_partial_sums_6_q0; +output [3:0] l2_partial_sums_7_address0; +output l2_partial_sums_7_ce0; +input [15:0] l2_partial_sums_7_q0; +output [12:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; +output [6:0] l2_adjustments_address0; +output l2_adjustments_ce0; +input [47:0] l2_adjustments_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg write4_read; +reg l2_partial_sums_0_ce0; +reg l2_partial_sums_1_ce0; +reg l2_partial_sums_2_ce0; +reg l2_partial_sums_3_ce0; +reg l2_partial_sums_4_ce0; +reg l2_partial_sums_5_ce0; +reg l2_partial_sums_6_ce0; +reg l2_partial_sums_7_ce0; +reg out_data_ce1; +reg out_data_we1; +reg l2_adjustments_ce0; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg running_sums_2_ce0; +reg running_sums_2_we0; +wire [15:0] running_sums_2_d0; +wire [6:0] running_sums_2_address1; +reg running_sums_2_ce1; +wire [15:0] running_sums_2_q1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg write4_blk_n; +reg [7:0] ochan_reg_317; +reg [3:0] indices_01_read_reg_724; +reg [7:0] indices_12_read_reg_730; +reg [0:0] write4_read_reg_735; +wire [9:0] add_ln109_fu_380_p2; +reg [9:0] add_ln109_reg_741; +wire ap_CS_fsm_state2; +wire [7:0] ochan_1_fu_386_p2; +reg [7:0] ochan_1_reg_746; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state4_pp0_stage0_iter1; +wire ap_block_state5_pp0_stage0_iter2; +wire ap_block_state6_pp0_stage0_iter3; +wire ap_block_state7_pp0_stage0_iter4; +wire ap_block_state8_pp0_stage0_iter5; +wire ap_block_state9_pp0_stage0_iter6; +wire ap_block_state10_pp0_stage0_iter7; +wire ap_block_state11_pp0_stage0_iter8; +wire ap_block_state12_pp0_stage0_iter9; +wire ap_block_state13_pp0_stage0_iter10; +wire ap_block_state14_pp0_stage0_iter11; +wire ap_block_state15_pp0_stage0_iter12; +wire ap_block_state16_pp0_stage0_iter13; +wire ap_block_state17_pp0_stage0_iter14; +wire ap_block_state18_pp0_stage0_iter15; +wire ap_block_state19_pp0_stage0_iter16; +wire ap_block_state20_pp0_stage0_iter17; +wire ap_block_state21_pp0_stage0_iter18; +wire ap_block_state22_pp0_stage0_iter19; +wire ap_block_state23_pp0_stage0_iter20; +wire ap_block_state24_pp0_stage0_iter21; +wire ap_block_state25_pp0_stage0_iter22; +wire ap_block_state26_pp0_stage0_iter23; +wire ap_block_state27_pp0_stage0_iter24; +wire ap_block_state28_pp0_stage0_iter25; +wire ap_block_state29_pp0_stage0_iter26; +wire ap_block_state30_pp0_stage0_iter27; +wire ap_block_state31_pp0_stage0_iter28; +wire ap_block_state32_pp0_stage0_iter29; +wire ap_block_state33_pp0_stage0_iter30; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln86_fu_392_p2; +reg [0:0] icmp_ln86_reg_751; +wire [63:0] zext_ln89_fu_398_p1; +reg [63:0] zext_ln89_reg_755; +reg [63:0] zext_ln89_reg_755_pp0_iter1_reg; +reg [63:0] zext_ln89_reg_755_pp0_iter2_reg; +reg [63:0] zext_ln89_reg_755_pp0_iter3_reg; +reg [63:0] zext_ln89_reg_755_pp0_iter4_reg; +reg [63:0] zext_ln89_reg_755_pp0_iter5_reg; +reg [63:0] zext_ln89_reg_755_pp0_iter6_reg; +reg [63:0] zext_ln89_reg_755_pp0_iter7_reg; +reg [6:0] running_sums_2_addr_reg_800; +reg [6:0] running_sums_2_addr_reg_800_pp0_iter1_reg; +reg [6:0] running_sums_2_addr_reg_800_pp0_iter2_reg; +reg [6:0] running_sums_2_addr_reg_800_pp0_iter3_reg; +reg [6:0] running_sums_2_addr_reg_800_pp0_iter4_reg; +reg [6:0] running_sums_2_addr_reg_800_pp0_iter5_reg; +reg [6:0] running_sums_2_addr_reg_800_pp0_iter6_reg; +reg [6:0] running_sums_2_addr_reg_800_pp0_iter7_reg; +reg [6:0] running_sums_2_addr_reg_800_pp0_iter8_reg; +reg [6:0] running_sums_2_addr_reg_800_pp0_iter9_reg; +wire [1:0] trunc_ln86_fu_425_p1; +reg [1:0] trunc_ln86_reg_806; +reg [1:0] trunc_ln86_reg_806_pp0_iter2_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter3_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter4_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter5_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter6_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter7_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter8_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter9_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter10_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter11_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter12_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter13_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter14_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter15_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter16_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter17_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter18_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter19_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter20_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter21_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter22_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter23_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter24_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter25_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter26_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter27_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter28_reg; +reg [1:0] trunc_ln86_reg_806_pp0_iter29_reg; +wire [15:0] val_fu_437_p10; +reg [15:0] val_reg_813; +reg [15:0] running_sums_2_load_reg_818; +reg ap_enable_reg_pp0_iter1; +wire [0:0] and_ln103_fu_465_p2; +reg [0:0] and_ln103_reg_823; +reg [0:0] and_ln103_reg_823_pp0_iter2_reg; +reg [0:0] and_ln103_reg_823_pp0_iter3_reg; +reg [0:0] and_ln103_reg_823_pp0_iter4_reg; +reg [0:0] and_ln103_reg_823_pp0_iter5_reg; +reg [0:0] and_ln103_reg_823_pp0_iter6_reg; +reg [0:0] and_ln103_reg_823_pp0_iter7_reg; +reg [0:0] and_ln103_reg_823_pp0_iter8_reg; +reg [0:0] and_ln103_reg_823_pp0_iter9_reg; +reg [0:0] and_ln103_reg_823_pp0_iter10_reg; +reg [0:0] and_ln103_reg_823_pp0_iter11_reg; +reg [0:0] and_ln103_reg_823_pp0_iter12_reg; +reg [0:0] and_ln103_reg_823_pp0_iter13_reg; +reg [0:0] and_ln103_reg_823_pp0_iter14_reg; +reg [0:0] and_ln103_reg_823_pp0_iter15_reg; +reg [0:0] and_ln103_reg_823_pp0_iter16_reg; +reg [0:0] and_ln103_reg_823_pp0_iter17_reg; +reg [0:0] and_ln103_reg_823_pp0_iter18_reg; +reg [0:0] and_ln103_reg_823_pp0_iter19_reg; +reg [0:0] and_ln103_reg_823_pp0_iter20_reg; +reg [0:0] and_ln103_reg_823_pp0_iter21_reg; +reg [0:0] and_ln103_reg_823_pp0_iter22_reg; +reg [0:0] and_ln103_reg_823_pp0_iter23_reg; +reg [0:0] and_ln103_reg_823_pp0_iter24_reg; +reg [0:0] and_ln103_reg_823_pp0_iter25_reg; +reg [0:0] and_ln103_reg_823_pp0_iter26_reg; +reg [0:0] and_ln103_reg_823_pp0_iter27_reg; +reg [0:0] and_ln103_reg_823_pp0_iter28_reg; +reg [0:0] and_ln103_reg_823_pp0_iter29_reg; +reg [4:0] lshr_ln6_reg_827; +reg [4:0] lshr_ln6_reg_827_pp0_iter2_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter3_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter4_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter5_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter6_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter7_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter8_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter9_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter10_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter11_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter12_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter13_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter14_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter15_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter16_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter17_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter18_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter19_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter20_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter21_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter22_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter23_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter24_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter25_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter26_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter27_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter28_reg; +reg [4:0] lshr_ln6_reg_827_pp0_iter29_reg; +wire [15:0] grp_fu_329_p2; +reg [15:0] sum_reg_837; +wire [15:0] trunc_ln95_fu_480_p1; +reg [15:0] trunc_ln95_reg_843; +reg [15:0] tmp_307_i_i_reg_848; +reg [15:0] tmp_307_i_i_reg_848_pp0_iter10_reg; +reg [15:0] tmp_307_i_i_reg_848_pp0_iter11_reg; +reg [15:0] tmp_307_i_i_reg_848_pp0_iter12_reg; +reg [15:0] tmp_307_i_i_reg_848_pp0_iter13_reg; +reg [15:0] tmp_307_i_i_reg_848_pp0_iter14_reg; +reg [15:0] tmp_307_i_i_reg_848_pp0_iter15_reg; +reg [15:0] tmp_307_i_i_reg_848_pp0_iter16_reg; +reg [15:0] tmp_308_i_i_reg_853; +reg [15:0] tmp_308_i_i_reg_853_pp0_iter10_reg; +reg [15:0] tmp_308_i_i_reg_853_pp0_iter11_reg; +reg [15:0] tmp_308_i_i_reg_853_pp0_iter12_reg; +reg [15:0] tmp_308_i_i_reg_853_pp0_iter13_reg; +reg [15:0] tmp_308_i_i_reg_853_pp0_iter14_reg; +reg [15:0] tmp_308_i_i_reg_853_pp0_iter15_reg; +reg [15:0] tmp_308_i_i_reg_853_pp0_iter16_reg; +reg [15:0] tmp_308_i_i_reg_853_pp0_iter17_reg; +reg [15:0] tmp_308_i_i_reg_853_pp0_iter18_reg; +reg [15:0] tmp_308_i_i_reg_853_pp0_iter19_reg; +reg [15:0] tmp_308_i_i_reg_853_pp0_iter20_reg; +reg [15:0] tmp_308_i_i_reg_853_pp0_iter21_reg; +wire [15:0] grp_fu_337_p2; +reg [15:0] sub_i_i_i_reg_863; +wire [15:0] grp_fu_341_p2; +reg [15:0] normalized_reg_873; +wire [15:0] grp_fu_333_p2; +reg [15:0] biased_reg_883; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state3; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_enable_reg_pp0_iter22; +reg ap_enable_reg_pp0_iter23; +reg ap_enable_reg_pp0_iter24; +reg ap_enable_reg_pp0_iter25; +reg ap_enable_reg_pp0_iter26; +reg ap_enable_reg_pp0_iter27; +reg ap_enable_reg_pp0_iter28; +reg ap_enable_reg_pp0_iter29; +reg ap_enable_reg_pp0_iter30; +reg [7:0] ap_phi_mux_ochan_phi_fu_321_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln89_4_fu_413_p1; +wire [63:0] sext_ln109_fu_666_p1; +reg [15:0] quad_3_27_fu_132; +wire [15:0] quad_3_38_fu_632_p3; +reg [15:0] quad_3_26_fu_136; +wire [15:0] quad_3_37_fu_624_p3; +reg [15:0] quad_3_28_fu_140; +wire [15:0] quad_3_35_fu_608_p3; +reg [15:0] quad_3_29_fu_144; +wire [15:0] quad_3_32_fu_584_p3; +reg ap_block_state1; +wire [15:0] grp_fu_333_p1; +wire [15:0] grp_fu_337_p1; +wire [15:0] grp_fu_341_p1; +wire [7:0] tmp_fu_345_p3; +wire [4:0] tmp_s_fu_356_p3; +wire [8:0] zext_ln109_fu_352_p1; +wire [8:0] zext_ln109_5_fu_363_p1; +wire [8:0] sub_ln109_fu_367_p2; +wire [9:0] sub_ln109_cast_fu_373_p1; +wire [9:0] zext_ln109_6_fu_377_p1; +wire [3:0] lshr_ln_fu_403_p4; +wire [2:0] trunc_ln89_fu_429_p1; +wire [15:0] val_fu_437_p9; +wire [0:0] icmp_ln103_fu_459_p2; +wire [15:0] data_V_fu_535_p1; +wire [0:0] p_Result_s_fu_538_p3; +wire [0:0] icmp_ln99_fu_553_p2; +wire [15:0] quad_0_fu_546_p3; +wire [0:0] icmp_ln99_5_fu_566_p2; +wire [15:0] quad_3_fu_558_p3; +wire [0:0] icmp_ln99_6_fu_579_p2; +wire [15:0] quad_3_31_fu_571_p3; +wire [15:0] quad_3_33_fu_592_p3; +wire [15:0] quad_3_34_fu_600_p3; +wire [15:0] quad_3_36_fu_616_p3; +wire [14:0] tmp_92_fu_660_p3; +wire [15:0] bitcast_ln109_9_fu_683_p1; +wire [15:0] bitcast_ln109_8_fu_679_p1; +wire [15:0] bitcast_ln109_7_fu_675_p1; +wire [15:0] bitcast_ln109_fu_671_p1; +wire ap_CS_fsm_state34; +reg [3:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +#0 ap_enable_reg_pp0_iter23 = 1'b0; +#0 ap_enable_reg_pp0_iter24 = 1'b0; +#0 ap_enable_reg_pp0_iter25 = 1'b0; +#0 ap_enable_reg_pp0_iter26 = 1'b0; +#0 ap_enable_reg_pp0_iter27 = 1'b0; +#0 ap_enable_reg_pp0_iter28 = 1'b0; +#0 ap_enable_reg_pp0_iter29 = 1'b0; +#0 ap_enable_reg_pp0_iter30 = 1'b0; +end + +td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2 #( + .DataWidth( 16 ), + .AddressRange( 128 ), + .AddressWidth( 7 )) +running_sums_2_U( + .reset(ap_rst), + .clk(ap_clk), + .address0(running_sums_2_addr_reg_800_pp0_iter9_reg), + .ce0(running_sums_2_ce0), + .we0(running_sums_2_we0), + .d0(running_sums_2_d0), + .address1(running_sums_2_address1), + .ce1(running_sums_2_ce1), + .q1(running_sums_2_q1) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1800( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(running_sums_2_load_reg_818), + .din1(val_reg_813), + .dout(grp_fu_329_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1801( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(normalized_reg_873), + .din1(grp_fu_333_p1), + .dout(grp_fu_333_p2) +); + +td_fused_top_hsub_16ns_16ns_16_7_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 7 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_7_full_dsp_1_U1802( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_reg_837), + .din1(grp_fu_337_p1), + .dout(grp_fu_337_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1803( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_863), + .din1(grp_fu_341_p1), + .dout(grp_fu_341_p2) +); + +td_fused_top_mux_816_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 16 ), + .din5_WIDTH( 16 ), + .din6_WIDTH( 16 ), + .din7_WIDTH( 16 ), + .din8_WIDTH( 16 ), + .dout_WIDTH( 16 )) +mux_816_16_1_1_U1804( + .din0(l2_partial_sums_0_q0), + .din1(l2_partial_sums_1_q0), + .din2(l2_partial_sums_2_q0), + .din3(l2_partial_sums_3_q0), + .din4(l2_partial_sums_4_q0), + .din5(l2_partial_sums_5_q0), + .din6(l2_partial_sums_6_q0), + .din7(l2_partial_sums_7_q0), + .din8(val_fu_437_p9), + .dout(val_fu_437_p10) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state34)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state3) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state3)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state3); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter23 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter23 <= ap_enable_reg_pp0_iter22; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter24 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter24 <= ap_enable_reg_pp0_iter23; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter25 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter25 <= ap_enable_reg_pp0_iter24; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter26 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter26 <= ap_enable_reg_pp0_iter25; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter27 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter27 <= ap_enable_reg_pp0_iter26; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter28 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter28 <= ap_enable_reg_pp0_iter27; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter29 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter29 <= ap_enable_reg_pp0_iter28; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter30 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter30 <= ap_enable_reg_pp0_iter29; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter30 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_reg_751 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ochan_reg_317 <= ochan_1_reg_746; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ochan_reg_317 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln109_reg_741 <= add_ln109_fu_380_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + and_ln103_reg_823 <= and_ln103_fu_465_p2; + icmp_ln86_reg_751 <= icmp_ln86_fu_392_p2; + running_sums_2_addr_reg_800_pp0_iter1_reg <= running_sums_2_addr_reg_800; + trunc_ln86_reg_806 <= trunc_ln86_fu_425_p1; + val_reg_813 <= val_fu_437_p10; + zext_ln89_reg_755_pp0_iter1_reg[7 : 0] <= zext_ln89_reg_755[7 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + and_ln103_reg_823_pp0_iter10_reg <= and_ln103_reg_823_pp0_iter9_reg; + and_ln103_reg_823_pp0_iter11_reg <= and_ln103_reg_823_pp0_iter10_reg; + and_ln103_reg_823_pp0_iter12_reg <= and_ln103_reg_823_pp0_iter11_reg; + and_ln103_reg_823_pp0_iter13_reg <= and_ln103_reg_823_pp0_iter12_reg; + and_ln103_reg_823_pp0_iter14_reg <= and_ln103_reg_823_pp0_iter13_reg; + and_ln103_reg_823_pp0_iter15_reg <= and_ln103_reg_823_pp0_iter14_reg; + and_ln103_reg_823_pp0_iter16_reg <= and_ln103_reg_823_pp0_iter15_reg; + and_ln103_reg_823_pp0_iter17_reg <= and_ln103_reg_823_pp0_iter16_reg; + and_ln103_reg_823_pp0_iter18_reg <= and_ln103_reg_823_pp0_iter17_reg; + and_ln103_reg_823_pp0_iter19_reg <= and_ln103_reg_823_pp0_iter18_reg; + and_ln103_reg_823_pp0_iter20_reg <= and_ln103_reg_823_pp0_iter19_reg; + and_ln103_reg_823_pp0_iter21_reg <= and_ln103_reg_823_pp0_iter20_reg; + and_ln103_reg_823_pp0_iter22_reg <= and_ln103_reg_823_pp0_iter21_reg; + and_ln103_reg_823_pp0_iter23_reg <= and_ln103_reg_823_pp0_iter22_reg; + and_ln103_reg_823_pp0_iter24_reg <= and_ln103_reg_823_pp0_iter23_reg; + and_ln103_reg_823_pp0_iter25_reg <= and_ln103_reg_823_pp0_iter24_reg; + and_ln103_reg_823_pp0_iter26_reg <= and_ln103_reg_823_pp0_iter25_reg; + and_ln103_reg_823_pp0_iter27_reg <= and_ln103_reg_823_pp0_iter26_reg; + and_ln103_reg_823_pp0_iter28_reg <= and_ln103_reg_823_pp0_iter27_reg; + and_ln103_reg_823_pp0_iter29_reg <= and_ln103_reg_823_pp0_iter28_reg; + and_ln103_reg_823_pp0_iter2_reg <= and_ln103_reg_823; + and_ln103_reg_823_pp0_iter3_reg <= and_ln103_reg_823_pp0_iter2_reg; + and_ln103_reg_823_pp0_iter4_reg <= and_ln103_reg_823_pp0_iter3_reg; + and_ln103_reg_823_pp0_iter5_reg <= and_ln103_reg_823_pp0_iter4_reg; + and_ln103_reg_823_pp0_iter6_reg <= and_ln103_reg_823_pp0_iter5_reg; + and_ln103_reg_823_pp0_iter7_reg <= and_ln103_reg_823_pp0_iter6_reg; + and_ln103_reg_823_pp0_iter8_reg <= and_ln103_reg_823_pp0_iter7_reg; + and_ln103_reg_823_pp0_iter9_reg <= and_ln103_reg_823_pp0_iter8_reg; + biased_reg_883 <= grp_fu_333_p2; + lshr_ln6_reg_827_pp0_iter10_reg <= lshr_ln6_reg_827_pp0_iter9_reg; + lshr_ln6_reg_827_pp0_iter11_reg <= lshr_ln6_reg_827_pp0_iter10_reg; + lshr_ln6_reg_827_pp0_iter12_reg <= lshr_ln6_reg_827_pp0_iter11_reg; + lshr_ln6_reg_827_pp0_iter13_reg <= lshr_ln6_reg_827_pp0_iter12_reg; + lshr_ln6_reg_827_pp0_iter14_reg <= lshr_ln6_reg_827_pp0_iter13_reg; + lshr_ln6_reg_827_pp0_iter15_reg <= lshr_ln6_reg_827_pp0_iter14_reg; + lshr_ln6_reg_827_pp0_iter16_reg <= lshr_ln6_reg_827_pp0_iter15_reg; + lshr_ln6_reg_827_pp0_iter17_reg <= lshr_ln6_reg_827_pp0_iter16_reg; + lshr_ln6_reg_827_pp0_iter18_reg <= lshr_ln6_reg_827_pp0_iter17_reg; + lshr_ln6_reg_827_pp0_iter19_reg <= lshr_ln6_reg_827_pp0_iter18_reg; + lshr_ln6_reg_827_pp0_iter20_reg <= lshr_ln6_reg_827_pp0_iter19_reg; + lshr_ln6_reg_827_pp0_iter21_reg <= lshr_ln6_reg_827_pp0_iter20_reg; + lshr_ln6_reg_827_pp0_iter22_reg <= lshr_ln6_reg_827_pp0_iter21_reg; + lshr_ln6_reg_827_pp0_iter23_reg <= lshr_ln6_reg_827_pp0_iter22_reg; + lshr_ln6_reg_827_pp0_iter24_reg <= lshr_ln6_reg_827_pp0_iter23_reg; + lshr_ln6_reg_827_pp0_iter25_reg <= lshr_ln6_reg_827_pp0_iter24_reg; + lshr_ln6_reg_827_pp0_iter26_reg <= lshr_ln6_reg_827_pp0_iter25_reg; + lshr_ln6_reg_827_pp0_iter27_reg <= lshr_ln6_reg_827_pp0_iter26_reg; + lshr_ln6_reg_827_pp0_iter28_reg <= lshr_ln6_reg_827_pp0_iter27_reg; + lshr_ln6_reg_827_pp0_iter29_reg <= lshr_ln6_reg_827_pp0_iter28_reg; + lshr_ln6_reg_827_pp0_iter2_reg <= lshr_ln6_reg_827; + lshr_ln6_reg_827_pp0_iter3_reg <= lshr_ln6_reg_827_pp0_iter2_reg; + lshr_ln6_reg_827_pp0_iter4_reg <= lshr_ln6_reg_827_pp0_iter3_reg; + lshr_ln6_reg_827_pp0_iter5_reg <= lshr_ln6_reg_827_pp0_iter4_reg; + lshr_ln6_reg_827_pp0_iter6_reg <= lshr_ln6_reg_827_pp0_iter5_reg; + lshr_ln6_reg_827_pp0_iter7_reg <= lshr_ln6_reg_827_pp0_iter6_reg; + lshr_ln6_reg_827_pp0_iter8_reg <= lshr_ln6_reg_827_pp0_iter7_reg; + lshr_ln6_reg_827_pp0_iter9_reg <= lshr_ln6_reg_827_pp0_iter8_reg; + normalized_reg_873 <= grp_fu_341_p2; + running_sums_2_addr_reg_800_pp0_iter2_reg <= running_sums_2_addr_reg_800_pp0_iter1_reg; + running_sums_2_addr_reg_800_pp0_iter3_reg <= running_sums_2_addr_reg_800_pp0_iter2_reg; + running_sums_2_addr_reg_800_pp0_iter4_reg <= running_sums_2_addr_reg_800_pp0_iter3_reg; + running_sums_2_addr_reg_800_pp0_iter5_reg <= running_sums_2_addr_reg_800_pp0_iter4_reg; + running_sums_2_addr_reg_800_pp0_iter6_reg <= running_sums_2_addr_reg_800_pp0_iter5_reg; + running_sums_2_addr_reg_800_pp0_iter7_reg <= running_sums_2_addr_reg_800_pp0_iter6_reg; + running_sums_2_addr_reg_800_pp0_iter8_reg <= running_sums_2_addr_reg_800_pp0_iter7_reg; + running_sums_2_addr_reg_800_pp0_iter9_reg <= running_sums_2_addr_reg_800_pp0_iter8_reg; + sub_i_i_i_reg_863 <= grp_fu_337_p2; + sum_reg_837 <= grp_fu_329_p2; + tmp_307_i_i_reg_848 <= {{l2_adjustments_q0[31:16]}}; + tmp_307_i_i_reg_848_pp0_iter10_reg <= tmp_307_i_i_reg_848; + tmp_307_i_i_reg_848_pp0_iter11_reg <= tmp_307_i_i_reg_848_pp0_iter10_reg; + tmp_307_i_i_reg_848_pp0_iter12_reg <= tmp_307_i_i_reg_848_pp0_iter11_reg; + tmp_307_i_i_reg_848_pp0_iter13_reg <= tmp_307_i_i_reg_848_pp0_iter12_reg; + tmp_307_i_i_reg_848_pp0_iter14_reg <= tmp_307_i_i_reg_848_pp0_iter13_reg; + tmp_307_i_i_reg_848_pp0_iter15_reg <= tmp_307_i_i_reg_848_pp0_iter14_reg; + tmp_307_i_i_reg_848_pp0_iter16_reg <= tmp_307_i_i_reg_848_pp0_iter15_reg; + tmp_308_i_i_reg_853 <= {{l2_adjustments_q0[47:32]}}; + tmp_308_i_i_reg_853_pp0_iter10_reg <= tmp_308_i_i_reg_853; + tmp_308_i_i_reg_853_pp0_iter11_reg <= tmp_308_i_i_reg_853_pp0_iter10_reg; + tmp_308_i_i_reg_853_pp0_iter12_reg <= tmp_308_i_i_reg_853_pp0_iter11_reg; + tmp_308_i_i_reg_853_pp0_iter13_reg <= tmp_308_i_i_reg_853_pp0_iter12_reg; + tmp_308_i_i_reg_853_pp0_iter14_reg <= tmp_308_i_i_reg_853_pp0_iter13_reg; + tmp_308_i_i_reg_853_pp0_iter15_reg <= tmp_308_i_i_reg_853_pp0_iter14_reg; + tmp_308_i_i_reg_853_pp0_iter16_reg <= tmp_308_i_i_reg_853_pp0_iter15_reg; + tmp_308_i_i_reg_853_pp0_iter17_reg <= tmp_308_i_i_reg_853_pp0_iter16_reg; + tmp_308_i_i_reg_853_pp0_iter18_reg <= tmp_308_i_i_reg_853_pp0_iter17_reg; + tmp_308_i_i_reg_853_pp0_iter19_reg <= tmp_308_i_i_reg_853_pp0_iter18_reg; + tmp_308_i_i_reg_853_pp0_iter20_reg <= tmp_308_i_i_reg_853_pp0_iter19_reg; + tmp_308_i_i_reg_853_pp0_iter21_reg <= tmp_308_i_i_reg_853_pp0_iter20_reg; + trunc_ln86_reg_806_pp0_iter10_reg <= trunc_ln86_reg_806_pp0_iter9_reg; + trunc_ln86_reg_806_pp0_iter11_reg <= trunc_ln86_reg_806_pp0_iter10_reg; + trunc_ln86_reg_806_pp0_iter12_reg <= trunc_ln86_reg_806_pp0_iter11_reg; + trunc_ln86_reg_806_pp0_iter13_reg <= trunc_ln86_reg_806_pp0_iter12_reg; + trunc_ln86_reg_806_pp0_iter14_reg <= trunc_ln86_reg_806_pp0_iter13_reg; + trunc_ln86_reg_806_pp0_iter15_reg <= trunc_ln86_reg_806_pp0_iter14_reg; + trunc_ln86_reg_806_pp0_iter16_reg <= trunc_ln86_reg_806_pp0_iter15_reg; + trunc_ln86_reg_806_pp0_iter17_reg <= trunc_ln86_reg_806_pp0_iter16_reg; + trunc_ln86_reg_806_pp0_iter18_reg <= trunc_ln86_reg_806_pp0_iter17_reg; + trunc_ln86_reg_806_pp0_iter19_reg <= trunc_ln86_reg_806_pp0_iter18_reg; + trunc_ln86_reg_806_pp0_iter20_reg <= trunc_ln86_reg_806_pp0_iter19_reg; + trunc_ln86_reg_806_pp0_iter21_reg <= trunc_ln86_reg_806_pp0_iter20_reg; + trunc_ln86_reg_806_pp0_iter22_reg <= trunc_ln86_reg_806_pp0_iter21_reg; + trunc_ln86_reg_806_pp0_iter23_reg <= trunc_ln86_reg_806_pp0_iter22_reg; + trunc_ln86_reg_806_pp0_iter24_reg <= trunc_ln86_reg_806_pp0_iter23_reg; + trunc_ln86_reg_806_pp0_iter25_reg <= trunc_ln86_reg_806_pp0_iter24_reg; + trunc_ln86_reg_806_pp0_iter26_reg <= trunc_ln86_reg_806_pp0_iter25_reg; + trunc_ln86_reg_806_pp0_iter27_reg <= trunc_ln86_reg_806_pp0_iter26_reg; + trunc_ln86_reg_806_pp0_iter28_reg <= trunc_ln86_reg_806_pp0_iter27_reg; + trunc_ln86_reg_806_pp0_iter29_reg <= trunc_ln86_reg_806_pp0_iter28_reg; + trunc_ln86_reg_806_pp0_iter2_reg <= trunc_ln86_reg_806; + trunc_ln86_reg_806_pp0_iter3_reg <= trunc_ln86_reg_806_pp0_iter2_reg; + trunc_ln86_reg_806_pp0_iter4_reg <= trunc_ln86_reg_806_pp0_iter3_reg; + trunc_ln86_reg_806_pp0_iter5_reg <= trunc_ln86_reg_806_pp0_iter4_reg; + trunc_ln86_reg_806_pp0_iter6_reg <= trunc_ln86_reg_806_pp0_iter5_reg; + trunc_ln86_reg_806_pp0_iter7_reg <= trunc_ln86_reg_806_pp0_iter6_reg; + trunc_ln86_reg_806_pp0_iter8_reg <= trunc_ln86_reg_806_pp0_iter7_reg; + trunc_ln86_reg_806_pp0_iter9_reg <= trunc_ln86_reg_806_pp0_iter8_reg; + trunc_ln95_reg_843 <= trunc_ln95_fu_480_p1; + zext_ln89_reg_755_pp0_iter2_reg[7 : 0] <= zext_ln89_reg_755_pp0_iter1_reg[7 : 0]; + zext_ln89_reg_755_pp0_iter3_reg[7 : 0] <= zext_ln89_reg_755_pp0_iter2_reg[7 : 0]; + zext_ln89_reg_755_pp0_iter4_reg[7 : 0] <= zext_ln89_reg_755_pp0_iter3_reg[7 : 0]; + zext_ln89_reg_755_pp0_iter5_reg[7 : 0] <= zext_ln89_reg_755_pp0_iter4_reg[7 : 0]; + zext_ln89_reg_755_pp0_iter6_reg[7 : 0] <= zext_ln89_reg_755_pp0_iter5_reg[7 : 0]; + zext_ln89_reg_755_pp0_iter7_reg[7 : 0] <= zext_ln89_reg_755_pp0_iter6_reg[7 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + indices_01_read_reg_724 <= indices_01_dout; + indices_12_read_reg_730 <= indices_12_dout; + write4_read_reg_735 <= write4_dout; + end +end + +always @ (posedge ap_clk) begin + if (((1'd1 == and_ln103_fu_465_p2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + lshr_ln6_reg_827 <= {{ochan_reg_317[6:2]}}; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ochan_1_reg_746 <= ochan_1_fu_386_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter30 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + quad_3_26_fu_136 <= quad_3_37_fu_624_p3; + quad_3_27_fu_132 <= quad_3_38_fu_632_p3; + quad_3_28_fu_140 <= quad_3_35_fu_608_p3; + quad_3_29_fu_144 <= quad_3_32_fu_584_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_392_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_2_addr_reg_800 <= zext_ln89_fu_398_p1; + zext_ln89_reg_755[7 : 0] <= zext_ln89_fu_398_p1[7 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_2_load_reg_818 <= running_sums_2_q1; + end +end + +always @ (*) begin + if ((icmp_ln86_fu_392_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state34)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter30 == 1'b0) & (ap_enable_reg_pp0_iter29 == 1'b0) & (ap_enable_reg_pp0_iter28 == 1'b0) & (ap_enable_reg_pp0_iter27 == 1'b0) & (ap_enable_reg_pp0_iter26 == 1'b0) & (ap_enable_reg_pp0_iter25 == 1'b0) & (ap_enable_reg_pp0_iter24 == 1'b0) & (ap_enable_reg_pp0_iter23 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_reg_751 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ochan_phi_fu_321_p4 = ochan_1_reg_746; + end else begin + ap_phi_mux_ochan_phi_fu_321_p4 = ochan_reg_317; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state34)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_adjustments_ce0 = 1'b1; + end else begin + l2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_0_ce0 = 1'b1; + end else begin + l2_partial_sums_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_1_ce0 = 1'b1; + end else begin + l2_partial_sums_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_2_ce0 = 1'b1; + end else begin + l2_partial_sums_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_3_ce0 = 1'b1; + end else begin + l2_partial_sums_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_4_ce0 = 1'b1; + end else begin + l2_partial_sums_4_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_5_ce0 = 1'b1; + end else begin + l2_partial_sums_5_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_6_ce0 = 1'b1; + end else begin + l2_partial_sums_6_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_7_ce0 = 1'b1; + end else begin + l2_partial_sums_7_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter30 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter30 == 1'b1) & (1'd1 == and_ln103_reg_823_pp0_iter29_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter10 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_2_ce0 = 1'b1; + end else begin + running_sums_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + running_sums_2_ce1 = 1'b1; + end else begin + running_sums_2_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter10 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_2_we0 = 1'b1; + end else begin + running_sums_2_we0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write4_blk_n = write4_empty_n; + end else begin + write4_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write4_read = 1'b1; + end else begin + write4_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln86_fu_392_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter30 == 1'b1) & (ap_enable_reg_pp0_iter29 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter30 == 1'b1) & (ap_enable_reg_pp0_iter29 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln86_fu_392_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state34; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state34 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln109_fu_380_p2 = ((sub_ln109_cast_fu_373_p1) + (zext_ln109_6_fu_377_p1)); + +assign and_ln103_fu_465_p2 = (write4_read_reg_735 & icmp_ln103_fu_459_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state34 = ap_CS_fsm[32'd3]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state25_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state26_pp0_stage0_iter23 = ~(1'b1 == 1'b1); + +assign ap_block_state27_pp0_stage0_iter24 = ~(1'b1 == 1'b1); + +assign ap_block_state28_pp0_stage0_iter25 = ~(1'b1 == 1'b1); + +assign ap_block_state29_pp0_stage0_iter26 = ~(1'b1 == 1'b1); + +assign ap_block_state30_pp0_stage0_iter27 = ~(1'b1 == 1'b1); + +assign ap_block_state31_pp0_stage0_iter28 = ~(1'b1 == 1'b1); + +assign ap_block_state32_pp0_stage0_iter29 = ~(1'b1 == 1'b1); + +assign ap_block_state33_pp0_stage0_iter30 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln109_7_fu_675_p1 = quad_3_37_fu_624_p3; + +assign bitcast_ln109_8_fu_679_p1 = quad_3_35_fu_608_p3; + +assign bitcast_ln109_9_fu_683_p1 = quad_3_32_fu_584_p3; + +assign bitcast_ln109_fu_671_p1 = quad_3_38_fu_632_p3; + +assign data_V_fu_535_p1 = biased_reg_883; + +assign grp_fu_333_p1 = tmp_308_i_i_reg_853_pp0_iter21_reg; + +assign grp_fu_337_p1 = trunc_ln95_reg_843; + +assign grp_fu_341_p1 = tmp_307_i_i_reg_848_pp0_iter16_reg; + +assign icmp_ln103_fu_459_p2 = ((trunc_ln86_fu_425_p1 == 2'd3) ? 1'b1 : 1'b0); + +assign icmp_ln86_fu_392_p2 = ((ap_phi_mux_ochan_phi_fu_321_p4 == 8'd128) ? 1'b1 : 1'b0); + +assign icmp_ln99_5_fu_566_p2 = ((trunc_ln86_reg_806_pp0_iter29_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln99_6_fu_579_p2 = ((trunc_ln86_reg_806_pp0_iter29_reg == 2'd0) ? 1'b1 : 1'b0); + +assign icmp_ln99_fu_553_p2 = ((trunc_ln86_reg_806_pp0_iter29_reg == 2'd2) ? 1'b1 : 1'b0); + +assign l2_adjustments_address0 = zext_ln89_reg_755_pp0_iter7_reg; + +assign l2_partial_sums_0_address0 = zext_ln89_4_fu_413_p1; + +assign l2_partial_sums_1_address0 = zext_ln89_4_fu_413_p1; + +assign l2_partial_sums_2_address0 = zext_ln89_4_fu_413_p1; + +assign l2_partial_sums_3_address0 = zext_ln89_4_fu_413_p1; + +assign l2_partial_sums_4_address0 = zext_ln89_4_fu_413_p1; + +assign l2_partial_sums_5_address0 = zext_ln89_4_fu_413_p1; + +assign l2_partial_sums_6_address0 = zext_ln89_4_fu_413_p1; + +assign l2_partial_sums_7_address0 = zext_ln89_4_fu_413_p1; + +assign lshr_ln_fu_403_p4 = {{ap_phi_mux_ochan_phi_fu_321_p4[6:3]}}; + +assign ochan_1_fu_386_p2 = (ap_phi_mux_ochan_phi_fu_321_p4 + 8'd1); + +assign out_data_address1 = sext_ln109_fu_666_p1; + +assign out_data_d1 = {{{{bitcast_ln109_9_fu_683_p1}, {bitcast_ln109_8_fu_679_p1}}, {bitcast_ln109_7_fu_675_p1}}, {bitcast_ln109_fu_671_p1}}; + +assign p_Result_s_fu_538_p3 = data_V_fu_535_p1[32'd15]; + +assign quad_0_fu_546_p3 = ((p_Result_s_fu_538_p3[0:0] == 1'b1) ? 16'd0 : biased_reg_883); + +assign quad_3_31_fu_571_p3 = ((icmp_ln99_5_fu_566_p2[0:0] == 1'b1) ? quad_3_29_fu_144 : quad_3_fu_558_p3); + +assign quad_3_32_fu_584_p3 = ((icmp_ln99_6_fu_579_p2[0:0] == 1'b1) ? quad_3_29_fu_144 : quad_3_31_fu_571_p3); + +assign quad_3_33_fu_592_p3 = ((icmp_ln99_fu_553_p2[0:0] == 1'b1) ? quad_0_fu_546_p3 : quad_3_28_fu_140); + +assign quad_3_34_fu_600_p3 = ((icmp_ln99_5_fu_566_p2[0:0] == 1'b1) ? quad_3_28_fu_140 : quad_3_33_fu_592_p3); + +assign quad_3_35_fu_608_p3 = ((icmp_ln99_6_fu_579_p2[0:0] == 1'b1) ? quad_3_28_fu_140 : quad_3_34_fu_600_p3); + +assign quad_3_36_fu_616_p3 = ((icmp_ln99_5_fu_566_p2[0:0] == 1'b1) ? quad_0_fu_546_p3 : quad_3_26_fu_136); + +assign quad_3_37_fu_624_p3 = ((icmp_ln99_6_fu_579_p2[0:0] == 1'b1) ? quad_3_26_fu_136 : quad_3_36_fu_616_p3); + +assign quad_3_38_fu_632_p3 = ((icmp_ln99_6_fu_579_p2[0:0] == 1'b1) ? quad_0_fu_546_p3 : quad_3_27_fu_132); + +assign quad_3_fu_558_p3 = ((icmp_ln99_fu_553_p2[0:0] == 1'b1) ? quad_3_29_fu_144 : quad_0_fu_546_p3); + +assign running_sums_2_address1 = zext_ln89_fu_398_p1; + +assign running_sums_2_d0 = ((write4_read_reg_735[0:0] == 1'b1) ? 16'd0 : sum_reg_837); + +assign sext_ln109_fu_666_p1 = (tmp_92_fu_660_p3); + +assign sub_ln109_cast_fu_373_p1 = (sub_ln109_fu_367_p2); + +assign sub_ln109_fu_367_p2 = (zext_ln109_fu_352_p1 - zext_ln109_5_fu_363_p1); + +assign tmp_92_fu_660_p3 = {{add_ln109_reg_741}, {lshr_ln6_reg_827_pp0_iter29_reg}}; + +assign tmp_fu_345_p3 = {{indices_01_read_reg_724}, {4'd0}}; + +assign tmp_s_fu_356_p3 = {{indices_01_read_reg_724}, {1'd0}}; + +assign trunc_ln86_fu_425_p1 = ochan_reg_317[1:0]; + +assign trunc_ln89_fu_429_p1 = ochan_reg_317[2:0]; + +assign trunc_ln95_fu_480_p1 = l2_adjustments_q0[15:0]; + +assign val_fu_437_p9 = trunc_ln89_fu_429_p1; + +assign zext_ln109_5_fu_363_p1 = tmp_s_fu_356_p3; + +assign zext_ln109_6_fu_377_p1 = indices_12_read_reg_730; + +assign zext_ln109_fu_352_p1 = tmp_fu_345_p3; + +assign zext_ln89_4_fu_413_p1 = lshr_ln_fu_403_p4; + +assign zext_ln89_fu_398_p1 = ap_phi_mux_ochan_phi_fu_321_p4; + +always @ (posedge ap_clk) begin + zext_ln89_reg_755[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + zext_ln89_reg_755_pp0_iter1_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + zext_ln89_reg_755_pp0_iter2_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + zext_ln89_reg_755_pp0_iter3_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + zext_ln89_reg_755_pp0_iter4_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + zext_ln89_reg_755_pp0_iter5_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + zext_ln89_reg_755_pp0_iter6_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + zext_ln89_reg_755_pp0_iter7_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf11_l2_writeOutputs_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_readFilters77 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_0_address0, + filter_data_0_ce0, + filter_data_0_q0, + filter_data_1_address0, + filter_data_1_ce0, + filter_data_1_q0, + filter_data_2_address0, + filter_data_2_ce0, + filter_data_2_q0, + filter_data_3_address0, + filter_data_3_ce0, + filter_data_3_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + weight_vecs_0_0_address0, + weight_vecs_0_0_ce0, + weight_vecs_0_0_we0, + weight_vecs_0_0_d0, + weight_vecs_0_1_address0, + weight_vecs_0_1_ce0, + weight_vecs_0_1_we0, + weight_vecs_0_1_d0, + weight_vecs_0_2_address0, + weight_vecs_0_2_ce0, + weight_vecs_0_2_we0, + weight_vecs_0_2_d0, + weight_vecs_0_3_address0, + weight_vecs_0_3_ce0, + weight_vecs_0_3_we0, + weight_vecs_0_3_d0, + weight_vecs_1_0_address0, + weight_vecs_1_0_ce0, + weight_vecs_1_0_we0, + weight_vecs_1_0_d0, + weight_vecs_1_1_address0, + weight_vecs_1_1_ce0, + weight_vecs_1_1_we0, + weight_vecs_1_1_d0, + weight_vecs_1_2_address0, + weight_vecs_1_2_ce0, + weight_vecs_1_2_we0, + weight_vecs_1_2_d0, + weight_vecs_1_3_address0, + weight_vecs_1_3_ce0, + weight_vecs_1_3_we0, + weight_vecs_1_3_d0, + weight_vecs_2_0_address0, + weight_vecs_2_0_ce0, + weight_vecs_2_0_we0, + weight_vecs_2_0_d0, + weight_vecs_2_1_address0, + weight_vecs_2_1_ce0, + weight_vecs_2_1_we0, + weight_vecs_2_1_d0, + weight_vecs_2_2_address0, + weight_vecs_2_2_ce0, + weight_vecs_2_2_we0, + weight_vecs_2_2_d0, + weight_vecs_2_3_address0, + weight_vecs_2_3_ce0, + weight_vecs_2_3_we0, + weight_vecs_2_3_d0, + weight_vecs_3_0_address0, + weight_vecs_3_0_ce0, + weight_vecs_3_0_we0, + weight_vecs_3_0_d0, + weight_vecs_3_1_address0, + weight_vecs_3_1_ce0, + weight_vecs_3_1_we0, + weight_vecs_3_1_d0, + weight_vecs_3_2_address0, + weight_vecs_3_2_ce0, + weight_vecs_3_2_we0, + weight_vecs_3_2_d0, + weight_vecs_3_3_address0, + weight_vecs_3_3_ce0, + weight_vecs_3_3_we0, + weight_vecs_3_3_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state6 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [14:0] filter_data_0_address0; +output filter_data_0_ce0; +input [63:0] filter_data_0_q0; +output [14:0] filter_data_1_address0; +output filter_data_1_ce0; +input [63:0] filter_data_1_q0; +output [14:0] filter_data_2_address0; +output filter_data_2_ce0; +input [63:0] filter_data_2_q0; +output [14:0] filter_data_3_address0; +output filter_data_3_ce0; +input [63:0] filter_data_3_q0; +input [6:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [7:0] weight_vecs_0_0_address0; +output weight_vecs_0_0_ce0; +output weight_vecs_0_0_we0; +output [15:0] weight_vecs_0_0_d0; +output [7:0] weight_vecs_0_1_address0; +output weight_vecs_0_1_ce0; +output weight_vecs_0_1_we0; +output [15:0] weight_vecs_0_1_d0; +output [7:0] weight_vecs_0_2_address0; +output weight_vecs_0_2_ce0; +output weight_vecs_0_2_we0; +output [15:0] weight_vecs_0_2_d0; +output [7:0] weight_vecs_0_3_address0; +output weight_vecs_0_3_ce0; +output weight_vecs_0_3_we0; +output [15:0] weight_vecs_0_3_d0; +output [7:0] weight_vecs_1_0_address0; +output weight_vecs_1_0_ce0; +output weight_vecs_1_0_we0; +output [15:0] weight_vecs_1_0_d0; +output [7:0] weight_vecs_1_1_address0; +output weight_vecs_1_1_ce0; +output weight_vecs_1_1_we0; +output [15:0] weight_vecs_1_1_d0; +output [7:0] weight_vecs_1_2_address0; +output weight_vecs_1_2_ce0; +output weight_vecs_1_2_we0; +output [15:0] weight_vecs_1_2_d0; +output [7:0] weight_vecs_1_3_address0; +output weight_vecs_1_3_ce0; +output weight_vecs_1_3_we0; +output [15:0] weight_vecs_1_3_d0; +output [7:0] weight_vecs_2_0_address0; +output weight_vecs_2_0_ce0; +output weight_vecs_2_0_we0; +output [15:0] weight_vecs_2_0_d0; +output [7:0] weight_vecs_2_1_address0; +output weight_vecs_2_1_ce0; +output weight_vecs_2_1_we0; +output [15:0] weight_vecs_2_1_d0; +output [7:0] weight_vecs_2_2_address0; +output weight_vecs_2_2_ce0; +output weight_vecs_2_2_we0; +output [15:0] weight_vecs_2_2_d0; +output [7:0] weight_vecs_2_3_address0; +output weight_vecs_2_3_ce0; +output weight_vecs_2_3_we0; +output [15:0] weight_vecs_2_3_d0; +output [7:0] weight_vecs_3_0_address0; +output weight_vecs_3_0_ce0; +output weight_vecs_3_0_we0; +output [15:0] weight_vecs_3_0_d0; +output [7:0] weight_vecs_3_1_address0; +output weight_vecs_3_1_ce0; +output weight_vecs_3_1_we0; +output [15:0] weight_vecs_3_1_d0; +output [7:0] weight_vecs_3_2_address0; +output weight_vecs_3_2_ce0; +output weight_vecs_3_2_we0; +output [15:0] weight_vecs_3_2_d0; +output [7:0] weight_vecs_3_3_address0; +output weight_vecs_3_3_ce0; +output weight_vecs_3_3_we0; +output [15:0] weight_vecs_3_3_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_0_ce0; +reg filter_data_1_ce0; +reg filter_data_2_ce0; +reg filter_data_3_ce0; +reg indices_23_read; +reg weight_vecs_0_0_ce0; +reg weight_vecs_0_0_we0; +reg weight_vecs_0_1_ce0; +reg weight_vecs_0_1_we0; +reg weight_vecs_0_2_ce0; +reg weight_vecs_0_2_we0; +reg weight_vecs_0_3_ce0; +reg weight_vecs_0_3_we0; +reg weight_vecs_1_0_ce0; +reg weight_vecs_1_0_we0; +reg weight_vecs_1_1_ce0; +reg weight_vecs_1_1_we0; +reg weight_vecs_1_2_ce0; +reg weight_vecs_1_2_we0; +reg weight_vecs_1_3_ce0; +reg weight_vecs_1_3_we0; +reg weight_vecs_2_0_ce0; +reg weight_vecs_2_0_we0; +reg weight_vecs_2_1_ce0; +reg weight_vecs_2_1_we0; +reg weight_vecs_2_2_ce0; +reg weight_vecs_2_2_we0; +reg weight_vecs_2_3_ce0; +reg weight_vecs_2_3_we0; +reg weight_vecs_3_0_ce0; +reg weight_vecs_3_0_we0; +reg weight_vecs_3_1_ce0; +reg weight_vecs_3_1_we0; +reg weight_vecs_3_2_ce0; +reg weight_vecs_3_2_we0; +reg weight_vecs_3_3_ce0; +reg weight_vecs_3_3_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [7:0] indvar_flatten13_reg_412; +reg [1:0] ii_reg_423; +reg [6:0] indvar_flatten_reg_434; +reg [1:0] jj_reg_445; +reg [6:0] kk_reg_456; +wire [10:0] sext_ln47_fu_489_p1; +reg [10:0] sext_ln47_reg_989; +wire [7:0] add_ln47_7_fu_493_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln47_fu_499_p2; +reg [0:0] icmp_ln47_reg_999; +reg [0:0] icmp_ln47_reg_999_pp0_iter1_reg; +reg [0:0] icmp_ln47_reg_999_pp0_iter2_reg; +wire [1:0] select_ln47_13_fu_533_p3; +reg [1:0] select_ln47_13_reg_1003; +wire [10:0] add_ln55_fu_545_p2; +reg [10:0] add_ln55_reg_1010; +wire [1:0] select_ln48_13_fu_584_p3; +reg [1:0] select_ln48_13_reg_1016; +reg [3:0] lshr_ln_reg_1023; +reg [3:0] lshr_ln_reg_1023_pp0_iter1_reg; +reg [3:0] lshr_ln_reg_1023_pp0_iter2_reg; +wire [6:0] add_ln49_fu_602_p2; +wire [6:0] select_ln48_14_fu_614_p3; +wire [5:0] add_ln55_16_fu_678_p2; +reg [5:0] add_ln55_16_reg_1039; +reg [5:0] add_ln55_16_reg_1039_pp0_iter2_reg; +reg [63:0] filter_data_0_load_reg_1064; +reg [63:0] filter_data_1_load_reg_1069; +reg [63:0] filter_data_2_load_reg_1074; +reg [63:0] filter_data_3_load_reg_1079; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg [1:0] ap_phi_mux_ii_phi_fu_427_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_449_p4; +wire [63:0] tmp_58_fu_684_p3; +wire [63:0] sext_ln55_13_fu_701_p1; +wire [8:0] tmp_56_fu_471_p3; +wire [9:0] zext_ln55_44_fu_479_p1; +wire [9:0] zext_ln55_fu_467_p1; +wire [9:0] sub_ln55_fu_483_p2; +wire [0:0] icmp_ln48_fu_511_p2; +wire [1:0] add_ln47_fu_505_p2; +wire [10:0] zext_ln55_46_fu_541_p1; +wire [0:0] tmp_89_fu_550_p3; +wire [0:0] xor_ln49_fu_558_p2; +wire [1:0] select_ln47_fu_517_p3; +wire [0:0] or_ln47_fu_564_p2; +wire [6:0] select_ln47_12_fu_525_p3; +wire [1:0] add_ln48_fu_570_p2; +wire [6:0] select_ln48_fu_576_p3; +wire [6:0] add_ln48_7_fu_608_p2; +wire [12:0] tmp_88_fu_628_p3; +wire [59:0] sext_ln55_12_fu_635_p1; +wire [59:0] sext_ln55_fu_625_p1; +wire [3:0] tmp_57_fu_645_p3; +wire [4:0] zext_ln55_47_fu_652_p1; +wire [4:0] zext_ln55_45_fu_622_p1; +wire [4:0] sub_ln55_16_fu_656_p2; +wire [59:0] sub_ln55_15_fu_639_p2; +wire [59:0] zext_ln55_49_fu_669_p1; +wire [5:0] sext_ln48_fu_662_p1; +wire [5:0] zext_ln55_48_fu_666_p1; +wire [59:0] add_ln55_15_fu_672_p2; +wire [9:0] tmp_90_fu_695_p3; +wire [63:0] tmp_fu_721_p6; +wire [15:0] trunc_ln55_fu_734_p1; +wire [63:0] tmp_s_fu_743_p6; +wire [15:0] trunc_ln55_20_fu_756_p1; +wire [63:0] tmp_7_fu_765_p6; +wire [15:0] trunc_ln55_21_fu_778_p1; +wire [63:0] tmp_8_fu_787_p6; +wire [15:0] trunc_ln55_22_fu_800_p1; +wire [15:0] tmp_284_i_i_fu_809_p4; +wire [15:0] tmp_286_i_i_fu_824_p4; +wire [15:0] tmp_288_i_i_fu_839_p4; +wire [15:0] tmp_290_i_i_fu_854_p4; +wire [15:0] tmp_292_i_i_fu_869_p4; +wire [15:0] tmp_294_i_i_fu_884_p4; +wire [15:0] tmp_296_i_i_fu_899_p4; +wire [15:0] tmp_298_i_i_fu_914_p4; +wire [15:0] tmp_300_i_i_fu_929_p4; +wire [15:0] tmp_302_i_i_fu_944_p4; +wire [15:0] tmp_304_i_i_fu_959_p4; +wire [15:0] tmp_306_i_i_fu_974_p4; +wire ap_CS_fsm_state6; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +end + +td_fused_top_mux_416_64_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 64 ), + .din1_WIDTH( 64 ), + .din2_WIDTH( 64 ), + .din3_WIDTH( 64 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 64 )) +mux_416_64_1_1_U1620( + .din0(filter_data_0_load_reg_1064), + .din1(64'd0), + .din2(64'd0), + .din3(64'd0), + .din4(16'd0), + .dout(tmp_fu_721_p6) +); + +td_fused_top_mux_416_64_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 64 ), + .din1_WIDTH( 64 ), + .din2_WIDTH( 64 ), + .din3_WIDTH( 64 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 64 )) +mux_416_64_1_1_U1621( + .din0(filter_data_1_load_reg_1069), + .din1(64'd0), + .din2(64'd0), + .din3(64'd0), + .din4(16'd0), + .dout(tmp_s_fu_743_p6) +); + +td_fused_top_mux_416_64_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 64 ), + .din1_WIDTH( 64 ), + .din2_WIDTH( 64 ), + .din3_WIDTH( 64 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 64 )) +mux_416_64_1_1_U1622( + .din0(filter_data_2_load_reg_1074), + .din1(64'd0), + .din2(64'd0), + .din3(64'd0), + .din4(16'd0), + .dout(tmp_7_fu_765_p6) +); + +td_fused_top_mux_416_64_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 64 ), + .din1_WIDTH( 64 ), + .din2_WIDTH( 64 ), + .din3_WIDTH( 64 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 64 )) +mux_416_64_1_1_U1623( + .din0(filter_data_3_load_reg_1079), + .din1(64'd0), + .din2(64'd0), + .din3(64'd0), + .din4(16'd0), + .dout(tmp_8_fu_787_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_999 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_423 <= select_ln47_13_reg_1003; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_423 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_499_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten13_reg_412 <= add_ln47_7_fu_493_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_412 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_499_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten_reg_434 <= select_ln48_14_fu_614_p3; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_434 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_999 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_445 <= select_ln48_13_reg_1016; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_445 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_499_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + kk_reg_456 <= add_ln49_fu_602_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_456 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_999 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln55_16_reg_1039 <= add_ln55_16_fu_678_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln55_16_reg_1039_pp0_iter2_reg <= add_ln55_16_reg_1039; + icmp_ln47_reg_999_pp0_iter2_reg <= icmp_ln47_reg_999_pp0_iter1_reg; + lshr_ln_reg_1023_pp0_iter2_reg <= lshr_ln_reg_1023_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_499_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln55_reg_1010 <= add_ln55_fu_545_p2; + lshr_ln_reg_1023 <= {{select_ln48_fu_576_p3[5:2]}}; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_999_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_0_load_reg_1064 <= filter_data_0_q0; + filter_data_1_load_reg_1069 <= filter_data_1_q0; + filter_data_2_load_reg_1074 <= filter_data_2_q0; + filter_data_3_load_reg_1079 <= filter_data_3_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln47_reg_999 <= icmp_ln47_fu_499_p2; + icmp_ln47_reg_999_pp0_iter1_reg <= icmp_ln47_reg_999; + lshr_ln_reg_1023_pp0_iter1_reg <= lshr_ln_reg_1023; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_499_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln47_13_reg_1003 <= select_ln47_13_fu_533_p3; + select_ln48_13_reg_1016 <= select_ln48_13_fu_584_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sext_ln47_reg_989 <= sext_ln47_fu_489_p1; + end +end + +always @ (*) begin + if ((icmp_ln47_fu_499_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_999 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_427_p4 = select_ln47_13_reg_1003; + end else begin + ap_phi_mux_ii_phi_fu_427_p4 = ii_reg_423; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_999 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_449_p4 = select_ln48_13_reg_1016; + end else begin + ap_phi_mux_jj_phi_fu_449_p4 = jj_reg_445; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_0_ce0 = 1'b1; + end else begin + filter_data_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_1_ce0 = 1'b1; + end else begin + filter_data_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_2_ce0 = 1'b1; + end else begin + filter_data_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_3_ce0 = 1'b1; + end else begin + filter_data_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_ce0 = 1'b1; + end else begin + weight_vecs_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_we0 = 1'b1; + end else begin + weight_vecs_0_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_2_ce0 = 1'b1; + end else begin + weight_vecs_0_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_2_we0 = 1'b1; + end else begin + weight_vecs_0_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_3_ce0 = 1'b1; + end else begin + weight_vecs_0_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_3_we0 = 1'b1; + end else begin + weight_vecs_0_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_ce0 = 1'b1; + end else begin + weight_vecs_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_we0 = 1'b1; + end else begin + weight_vecs_1_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_ce0 = 1'b1; + end else begin + weight_vecs_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_we0 = 1'b1; + end else begin + weight_vecs_1_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_2_ce0 = 1'b1; + end else begin + weight_vecs_1_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_2_we0 = 1'b1; + end else begin + weight_vecs_1_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_3_ce0 = 1'b1; + end else begin + weight_vecs_1_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_3_we0 = 1'b1; + end else begin + weight_vecs_1_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_0_ce0 = 1'b1; + end else begin + weight_vecs_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_0_we0 = 1'b1; + end else begin + weight_vecs_2_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_1_ce0 = 1'b1; + end else begin + weight_vecs_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_1_we0 = 1'b1; + end else begin + weight_vecs_2_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_2_ce0 = 1'b1; + end else begin + weight_vecs_2_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_2_we0 = 1'b1; + end else begin + weight_vecs_2_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_3_ce0 = 1'b1; + end else begin + weight_vecs_2_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_3_we0 = 1'b1; + end else begin + weight_vecs_2_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_0_ce0 = 1'b1; + end else begin + weight_vecs_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_0_we0 = 1'b1; + end else begin + weight_vecs_3_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_1_ce0 = 1'b1; + end else begin + weight_vecs_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_1_we0 = 1'b1; + end else begin + weight_vecs_3_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_2_ce0 = 1'b1; + end else begin + weight_vecs_3_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_2_we0 = 1'b1; + end else begin + weight_vecs_3_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_3_ce0 = 1'b1; + end else begin + weight_vecs_3_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_3_we0 = 1'b1; + end else begin + weight_vecs_3_3_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln47_fu_499_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln47_fu_499_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln47_7_fu_493_p2 = (indvar_flatten13_reg_412 + 8'd1); + +assign add_ln47_fu_505_p2 = (ap_phi_mux_ii_phi_fu_427_p4 + 2'd1); + +assign add_ln48_7_fu_608_p2 = (indvar_flatten_reg_434 + 7'd1); + +assign add_ln48_fu_570_p2 = (select_ln47_fu_517_p3 + 2'd1); + +assign add_ln49_fu_602_p2 = (select_ln48_fu_576_p3 + 7'd4); + +assign add_ln55_15_fu_672_p2 = (sub_ln55_15_fu_639_p2 + zext_ln55_49_fu_669_p1); + +assign add_ln55_16_fu_678_p2 = ((sext_ln48_fu_662_p1) + (zext_ln55_48_fu_666_p1)); + +assign add_ln55_fu_545_p2 = ((sext_ln47_reg_989) + (zext_ln55_46_fu_541_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_0_address0 = tmp_58_fu_684_p3; + +assign filter_data_1_address0 = tmp_58_fu_684_p3; + +assign filter_data_2_address0 = tmp_58_fu_684_p3; + +assign filter_data_3_address0 = tmp_58_fu_684_p3; + +assign icmp_ln47_fu_499_p2 = ((indvar_flatten13_reg_412 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln48_fu_511_p2 = ((indvar_flatten_reg_434 == 7'd48) ? 1'b1 : 1'b0); + +assign or_ln47_fu_564_p2 = (xor_ln49_fu_558_p2 | icmp_ln48_fu_511_p2); + +assign select_ln47_12_fu_525_p3 = ((icmp_ln48_fu_511_p2[0:0] == 1'b1) ? 7'd0 : kk_reg_456); + +assign select_ln47_13_fu_533_p3 = ((icmp_ln48_fu_511_p2[0:0] == 1'b1) ? add_ln47_fu_505_p2 : ap_phi_mux_ii_phi_fu_427_p4); + +assign select_ln47_fu_517_p3 = ((icmp_ln48_fu_511_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_449_p4); + +assign select_ln48_13_fu_584_p3 = ((or_ln47_fu_564_p2[0:0] == 1'b1) ? select_ln47_fu_517_p3 : add_ln48_fu_570_p2); + +assign select_ln48_14_fu_614_p3 = ((icmp_ln48_fu_511_p2[0:0] == 1'b1) ? 7'd1 : add_ln48_7_fu_608_p2); + +assign select_ln48_fu_576_p3 = ((or_ln47_fu_564_p2[0:0] == 1'b1) ? select_ln47_12_fu_525_p3 : 7'd0); + +assign sext_ln47_fu_489_p1 = (sub_ln55_fu_483_p2); + +assign sext_ln48_fu_662_p1 = (sub_ln55_16_fu_656_p2); + +assign sext_ln55_12_fu_635_p1 = (tmp_88_fu_628_p3); + +assign sext_ln55_13_fu_701_p1 = (tmp_90_fu_695_p3); + +assign sext_ln55_fu_625_p1 = add_ln55_reg_1010; + +assign sub_ln55_15_fu_639_p2 = ((sext_ln55_12_fu_635_p1) - (sext_ln55_fu_625_p1)); + +assign sub_ln55_16_fu_656_p2 = (zext_ln55_47_fu_652_p1 - zext_ln55_45_fu_622_p1); + +assign sub_ln55_fu_483_p2 = (zext_ln55_44_fu_479_p1 - zext_ln55_fu_467_p1); + +assign tmp_284_i_i_fu_809_p4 = {{tmp_fu_721_p6[31:16]}}; + +assign tmp_286_i_i_fu_824_p4 = {{tmp_s_fu_743_p6[31:16]}}; + +assign tmp_288_i_i_fu_839_p4 = {{tmp_7_fu_765_p6[31:16]}}; + +assign tmp_290_i_i_fu_854_p4 = {{tmp_8_fu_787_p6[31:16]}}; + +assign tmp_292_i_i_fu_869_p4 = {{tmp_fu_721_p6[47:32]}}; + +assign tmp_294_i_i_fu_884_p4 = {{tmp_s_fu_743_p6[47:32]}}; + +assign tmp_296_i_i_fu_899_p4 = {{tmp_7_fu_765_p6[47:32]}}; + +assign tmp_298_i_i_fu_914_p4 = {{tmp_8_fu_787_p6[47:32]}}; + +assign tmp_300_i_i_fu_929_p4 = {{tmp_fu_721_p6[63:48]}}; + +assign tmp_302_i_i_fu_944_p4 = {{tmp_s_fu_743_p6[63:48]}}; + +assign tmp_304_i_i_fu_959_p4 = {{tmp_7_fu_765_p6[63:48]}}; + +assign tmp_306_i_i_fu_974_p4 = {{tmp_8_fu_787_p6[63:48]}}; + +assign tmp_56_fu_471_p3 = {{indices_23_dout}, {2'd0}}; + +assign tmp_57_fu_645_p3 = {{select_ln47_13_reg_1003}, {2'd0}}; + +assign tmp_58_fu_684_p3 = {{add_ln55_15_fu_672_p2}, {lshr_ln_reg_1023}}; + +assign tmp_88_fu_628_p3 = {{add_ln55_reg_1010}, {2'd0}}; + +assign tmp_89_fu_550_p3 = kk_reg_456[32'd6]; + +assign tmp_90_fu_695_p3 = {{add_ln55_16_reg_1039_pp0_iter2_reg}, {lshr_ln_reg_1023_pp0_iter2_reg}}; + +assign trunc_ln55_20_fu_756_p1 = tmp_s_fu_743_p6[15:0]; + +assign trunc_ln55_21_fu_778_p1 = tmp_7_fu_765_p6[15:0]; + +assign trunc_ln55_22_fu_800_p1 = tmp_8_fu_787_p6[15:0]; + +assign trunc_ln55_fu_734_p1 = tmp_fu_721_p6[15:0]; + +assign weight_vecs_0_0_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_0_0_d0 = trunc_ln55_fu_734_p1; + +assign weight_vecs_0_1_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_0_1_d0 = tmp_284_i_i_fu_809_p4; + +assign weight_vecs_0_2_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_0_2_d0 = tmp_292_i_i_fu_869_p4; + +assign weight_vecs_0_3_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_0_3_d0 = tmp_300_i_i_fu_929_p4; + +assign weight_vecs_1_0_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_1_0_d0 = trunc_ln55_20_fu_756_p1; + +assign weight_vecs_1_1_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_1_1_d0 = tmp_286_i_i_fu_824_p4; + +assign weight_vecs_1_2_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_1_2_d0 = tmp_294_i_i_fu_884_p4; + +assign weight_vecs_1_3_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_1_3_d0 = tmp_302_i_i_fu_944_p4; + +assign weight_vecs_2_0_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_2_0_d0 = trunc_ln55_21_fu_778_p1; + +assign weight_vecs_2_1_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_2_1_d0 = tmp_288_i_i_fu_839_p4; + +assign weight_vecs_2_2_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_2_2_d0 = tmp_296_i_i_fu_899_p4; + +assign weight_vecs_2_3_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_2_3_d0 = tmp_304_i_i_fu_959_p4; + +assign weight_vecs_3_0_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_3_0_d0 = trunc_ln55_22_fu_800_p1; + +assign weight_vecs_3_1_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_3_1_d0 = tmp_290_i_i_fu_854_p4; + +assign weight_vecs_3_2_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_3_2_d0 = tmp_298_i_i_fu_914_p4; + +assign weight_vecs_3_3_address0 = sext_ln55_13_fu_701_p1; + +assign weight_vecs_3_3_d0 = tmp_306_i_i_fu_974_p4; + +assign xor_ln49_fu_558_p2 = (tmp_89_fu_550_p3 ^ 1'd1); + +assign zext_ln55_44_fu_479_p1 = tmp_56_fu_471_p3; + +assign zext_ln55_45_fu_622_p1 = select_ln47_13_reg_1003; + +assign zext_ln55_46_fu_541_p1 = select_ln47_13_fu_533_p3; + +assign zext_ln55_47_fu_652_p1 = tmp_57_fu_645_p3; + +assign zext_ln55_48_fu_666_p1 = select_ln48_13_reg_1016; + +assign zext_ln55_49_fu_669_p1 = select_ln48_13_reg_1016; + +assign zext_ln55_fu_467_p1 = indices_23_dout; + +endmodule //td_fused_top_tdf11_readFilters77 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_readInputs78 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_0_address0, + ifmap_vec_0_ce0, + ifmap_vec_0_we0, + ifmap_vec_0_d0, + ifmap_vec_1_address0, + ifmap_vec_1_ce0, + ifmap_vec_1_we0, + ifmap_vec_1_d0, + ifmap_vec_2_address0, + ifmap_vec_2_ce0, + ifmap_vec_2_we0, + ifmap_vec_2_d0, + ifmap_vec_3_address0, + ifmap_vec_3_ce0, + ifmap_vec_3_we0, + ifmap_vec_3_d0, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_pp0_stage0 = 4'd4; +parameter ap_ST_fsm_state8 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [11:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [7:0] ifmap_vec_0_address0; +output ifmap_vec_0_ce0; +output ifmap_vec_0_we0; +output [15:0] ifmap_vec_0_d0; +output [7:0] ifmap_vec_1_address0; +output ifmap_vec_1_ce0; +output ifmap_vec_1_we0; +output [15:0] ifmap_vec_1_d0; +output [7:0] ifmap_vec_2_address0; +output ifmap_vec_2_ce0; +output ifmap_vec_2_we0; +output [15:0] ifmap_vec_2_d0; +output [7:0] ifmap_vec_3_address0; +output ifmap_vec_3_ce0; +output ifmap_vec_3_we0; +output [15:0] ifmap_vec_3_d0; +output [3:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [7:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg ifmap_vec_0_ce0; +reg ifmap_vec_0_we0; +reg ifmap_vec_1_ce0; +reg ifmap_vec_1_we0; +reg ifmap_vec_2_ce0; +reg ifmap_vec_2_we0; +reg ifmap_vec_3_ce0; +reg ifmap_vec_3_we0; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [7:0] indvar_flatten47_reg_231; +reg [1:0] ii_reg_242; +reg [6:0] indvar_flatten_reg_254; +reg [1:0] jj_reg_265; +reg [6:0] kk_reg_277; +reg [15:0] indices_01_read_reg_905; +wire [3:0] trunc_ln289_fu_288_p1; +reg [3:0] trunc_ln289_reg_910; +reg [15:0] indices_12_read_reg_915; +wire [7:0] empty_fu_293_p1; +reg [7:0] empty_reg_920; +wire [17:0] p_cast_i_i_fu_310_p1; +reg [17:0] p_cast_i_i_reg_927; +wire ap_CS_fsm_state2; +wire [17:0] sext_ln22_fu_320_p1; +reg [17:0] sext_ln22_reg_933; +wire [3:0] p_cast_fu_324_p2; +reg [3:0] p_cast_reg_939; +wire [0:0] or_ln23_31_fu_343_p2; +reg [0:0] or_ln23_31_reg_945; +wire [7:0] p_mid137_fu_349_p2; +reg [7:0] p_mid137_reg_950; +wire [7:0] add_ln19_7_fu_354_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state4_pp0_stage0_iter1; +wire ap_block_state5_pp0_stage0_iter2; +wire ap_block_state6_pp0_stage0_iter3; +wire ap_block_state7_pp0_stage0_iter4; +wire ap_block_pp0_stage0_11001; +wire [0:0] empty_151_fu_369_p2; +reg [0:0] empty_151_reg_960; +wire [0:0] is_padding_fu_404_p2; +reg [0:0] is_padding_reg_965; +wire [0:0] icmp_ln19_fu_410_p2; +reg [0:0] icmp_ln19_reg_972; +reg [0:0] icmp_ln19_reg_972_pp0_iter1_reg; +reg [0:0] icmp_ln19_reg_972_pp0_iter2_reg; +reg [0:0] icmp_ln19_reg_972_pp0_iter3_reg; +wire [1:0] add_ln19_fu_416_p2; +reg [1:0] add_ln19_reg_976; +wire [0:0] icmp_ln20_fu_422_p2; +reg [0:0] icmp_ln20_reg_981; +wire [1:0] select_ln19_42_fu_444_p3; +reg [1:0] select_ln19_42_reg_990; +wire [0:0] p_mid113_fu_461_p2; +reg [0:0] p_mid113_reg_997; +wire [0:0] or_ln19_fu_481_p2; +reg [0:0] or_ln19_reg_1003; +reg [0:0] or_ln19_reg_1003_pp0_iter1_reg; +wire [1:0] add_ln20_fu_487_p2; +reg [1:0] add_ln20_reg_1010; +wire [1:0] select_ln20_30_fu_501_p3; +reg [1:0] select_ln20_30_reg_1015; +wire [17:0] add_ln22_8_fu_513_p2; +reg [17:0] add_ln22_8_reg_1021; +reg [3:0] lshr_ln_reg_1027; +reg [3:0] lshr_ln_reg_1027_pp0_iter1_reg; +reg [3:0] lshr_ln_reg_1027_pp0_iter2_reg; +reg [3:0] lshr_ln_reg_1027_pp0_iter3_reg; +wire [6:0] add_ln25_fu_528_p2; +wire [6:0] select_ln20_34_fu_540_p3; +wire [7:0] select_ln19_47_fu_666_p3; +reg [7:0] select_ln19_47_reg_1043; +wire [5:0] add_ln33_fu_676_p2; +reg [5:0] add_ln33_reg_1048; +reg [5:0] add_ln33_reg_1048_pp0_iter2_reg; +reg [5:0] add_ln33_reg_1048_pp0_iter3_reg; +wire [0:0] or_ln23_35_fu_703_p2; +reg [0:0] or_ln23_35_reg_1053; +wire [0:0] select_ln20_31_fu_709_p3; +reg [0:0] select_ln20_31_reg_1058; +reg [0:0] select_ln20_31_reg_1058_pp0_iter2_reg; +wire [7:0] p_mid1_fu_734_p2; +reg [7:0] p_mid1_reg_1066; +wire [8:0] sub_ln32_fu_770_p2; +reg [8:0] sub_ln32_reg_1071; +wire [15:0] select_ln33_fu_821_p3; +reg [15:0] select_ln33_reg_1081; +wire [15:0] select_ln33_20_fu_842_p3; +reg [15:0] select_ln33_20_reg_1086; +wire [15:0] select_ln33_21_fu_863_p3; +reg [15:0] select_ln33_21_reg_1091; +wire [15:0] select_ln33_22_fu_884_p3; +reg [15:0] select_ln33_22_reg_1096; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state4; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg [1:0] ap_phi_mux_ii_phi_fu_246_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_269_p4; +wire [63:0] sext_ln32_fu_808_p1; +wire [63:0] sext_ln33_fu_897_p1; +reg ap_block_state1; +wire [16:0] zext_ln19_fu_301_p1; +wire [16:0] empty_149_fu_304_p2; +wire [16:0] j_cast_i_i_fu_298_p1; +wire [16:0] add_ln22_fu_314_p2; +wire [0:0] tmp_82_fu_329_p3; +wire [0:0] icmp_ln24_fu_337_p2; +wire [17:0] ii_cast_i_i_fu_360_p1; +wire [17:0] empty_150_fu_364_p2; +wire [17:0] zext_ln20_fu_375_p1; +wire [17:0] add_ln22_7_fu_379_p2; +wire [0:0] tmp_83_fu_384_p3; +wire [0:0] icmp_ln24_7_fu_392_p2; +wire [0:0] or_ln23_fu_398_p2; +wire [17:0] ii_cast_i_i_mid1_fu_452_p1; +wire [17:0] p_mid111_fu_456_p2; +wire [0:0] tmp_84_fu_467_p3; +wire [0:0] xor_ln25_fu_475_p2; +wire [1:0] select_ln19_fu_428_p3; +wire [6:0] select_ln19_41_fu_436_p3; +wire [17:0] zext_ln20_7_fu_509_p1; +wire [6:0] select_ln20_fu_493_p3; +wire [6:0] add_ln20_7_fu_534_p2; +wire [3:0] ii_cast_fu_548_p1; +wire [3:0] p_cast28_i_i_fu_552_p2; +wire [2:0] zext_ln22_fu_557_p1; +wire [2:0] tmp1_fu_568_p2; +wire [7:0] tmp1_cast_fu_574_p1; +wire [7:0] empty_152_fu_578_p2; +wire [3:0] tmp_fu_593_p3; +wire [4:0] zext_ln33_16_fu_600_p1; +wire [4:0] zext_ln33_fu_590_p1; +wire [4:0] sub_ln33_fu_604_p2; +wire [3:0] ii_cast_mid1_fu_614_p1; +wire [3:0] p_cast28_i_i_mid1_fu_617_p2; +wire [0:0] or_ln23_33_fu_634_p2; +wire [3:0] row_coord_int_mid131_fu_644_p3; +wire [3:0] row_coord_int_fu_561_p3; +wire [7:0] col_coord_int_mid139_fu_652_p3; +wire [7:0] col_coord_int_fu_583_p3; +wire [5:0] sub_ln33_cast_fu_610_p1; +wire [5:0] zext_ln33_17_fu_673_p1; +wire [0:0] tmp_85_fu_685_p3; +wire [0:0] icmp_ln24_8_fu_692_p2; +wire [0:0] or_ln23_34_fu_697_p2; +wire [0:0] select_ln19_44_fu_629_p3; +wire [0:0] select_ln19_45_fu_638_p3; +wire [3:0] select_ln19_43_fu_622_p3; +wire [2:0] zext_ln22_7_fu_682_p1; +wire [2:0] tmp1_mid1_fu_724_p2; +wire [7:0] tmp1_cast_mid1_fu_730_p1; +wire [3:0] select_ln19_46_fu_659_p3; +wire [3:0] row_coord_int_mid1_fu_716_p3; +wire [3:0] select_ln20_32_fu_739_p3; +wire [7:0] tmp_s_fu_746_p3; +wire [4:0] tmp_55_fu_758_p3; +wire [8:0] zext_ln32_fu_754_p1; +wire [8:0] zext_ln32_63_fu_766_p1; +wire [7:0] col_coord_int_mid1_fu_776_p3; +wire [7:0] select_ln20_33_fu_785_p3; +wire [9:0] sext_ln20_fu_782_p1; +wire [9:0] zext_ln32_64_fu_791_p1; +wire [9:0] add_ln32_fu_795_p2; +wire [13:0] tmp_86_fu_801_p3; +wire [15:0] trunc_ln32_fu_813_p1; +wire [15:0] in_data_elem_fu_817_p1; +wire [15:0] tmp_273_i_i_fu_828_p4; +wire [15:0] in_data_elem_10_fu_838_p1; +wire [15:0] tmp_274_i_i_fu_849_p4; +wire [15:0] in_data_elem_11_fu_859_p1; +wire [15:0] tmp_275_i_i_fu_870_p4; +wire [15:0] in_data_elem_12_fu_880_p1; +wire [9:0] tmp_87_fu_891_p3; +wire ap_CS_fsm_state8; +reg [3:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state4)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_972 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_242 <= select_ln19_42_reg_990; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ii_reg_242 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten47_reg_231 <= add_ln19_7_fu_354_p2; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + indvar_flatten47_reg_231 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten_reg_254 <= select_ln20_34_fu_540_p3; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + indvar_flatten_reg_254 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_972 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_265 <= select_ln20_30_reg_1015; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + jj_reg_265 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + kk_reg_277 <= add_ln25_fu_528_p2; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + kk_reg_277 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln19_reg_976 <= add_ln19_fu_416_p2; + add_ln20_reg_1010 <= add_ln20_fu_487_p2; + add_ln22_8_reg_1021 <= add_ln22_8_fu_513_p2; + icmp_ln20_reg_981 <= icmp_ln20_fu_422_p2; + lshr_ln_reg_1027 <= {{select_ln20_fu_493_p3[5:2]}}; + or_ln19_reg_1003 <= or_ln19_fu_481_p2; + p_mid113_reg_997 <= p_mid113_fu_461_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_972 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln33_reg_1048 <= add_ln33_fu_676_p2; + or_ln23_35_reg_1053 <= or_ln23_35_fu_703_p2; + select_ln20_31_reg_1058 <= select_ln20_31_fu_709_p3; + sub_ln32_reg_1071[8 : 1] <= sub_ln32_fu_770_p2[8 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln33_reg_1048_pp0_iter2_reg <= add_ln33_reg_1048; + add_ln33_reg_1048_pp0_iter3_reg <= add_ln33_reg_1048_pp0_iter2_reg; + icmp_ln19_reg_972_pp0_iter2_reg <= icmp_ln19_reg_972_pp0_iter1_reg; + icmp_ln19_reg_972_pp0_iter3_reg <= icmp_ln19_reg_972_pp0_iter2_reg; + lshr_ln_reg_1027_pp0_iter2_reg <= lshr_ln_reg_1027_pp0_iter1_reg; + lshr_ln_reg_1027_pp0_iter3_reg <= lshr_ln_reg_1027_pp0_iter2_reg; + select_ln20_31_reg_1058_pp0_iter2_reg <= select_ln20_31_reg_1058; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + empty_151_reg_960 <= empty_151_fu_369_p2; + icmp_ln19_reg_972 <= icmp_ln19_fu_410_p2; + icmp_ln19_reg_972_pp0_iter1_reg <= icmp_ln19_reg_972; + is_padding_reg_965 <= is_padding_fu_404_p2; + lshr_ln_reg_1027_pp0_iter1_reg <= lshr_ln_reg_1027; + or_ln19_reg_1003_pp0_iter1_reg <= or_ln19_reg_1003; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + empty_reg_920 <= empty_fu_293_p1; + indices_01_read_reg_905 <= indices_01_dout; + indices_12_read_reg_915 <= indices_12_dout; + trunc_ln289_reg_910 <= trunc_ln289_fu_288_p1; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + or_ln23_31_reg_945 <= or_ln23_31_fu_343_p2; + p_cast_i_i_reg_927 <= p_cast_i_i_fu_310_p1; + p_cast_reg_939 <= p_cast_fu_324_p2; + p_mid137_reg_950 <= p_mid137_fu_349_p2; + sext_ln22_reg_933 <= sext_ln22_fu_320_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (or_ln19_reg_1003 == 1'd0) & (icmp_ln19_reg_972 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + p_mid1_reg_1066 <= p_mid1_fu_734_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln19_42_reg_990 <= select_ln19_42_fu_444_p3; + select_ln20_30_reg_1015 <= select_ln20_30_fu_501_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (or_ln19_reg_1003 == 1'd1) & (icmp_ln19_reg_972 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + select_ln19_47_reg_1043 <= select_ln19_47_fu_666_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_972_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + select_ln33_20_reg_1086 <= select_ln33_20_fu_842_p3; + select_ln33_21_reg_1091 <= select_ln33_21_fu_863_p3; + select_ln33_22_reg_1096 <= select_ln33_22_fu_884_p3; + select_ln33_reg_1081 <= select_ln33_fu_821_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_condition_pp0_exit_iter1_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state4 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_972 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_246_p4 = select_ln19_42_reg_990; + end else begin + ap_phi_mux_ii_phi_fu_246_p4 = ii_reg_242; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_972 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_269_p4 = select_ln20_30_reg_1015; + end else begin + ap_phi_mux_jj_phi_fu_269_p4 = jj_reg_265; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (icmp_ln19_reg_972_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_we0 = 1'b1; + end else begin + ifmap_vec_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_1_ce0 = 1'b1; + end else begin + ifmap_vec_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (icmp_ln19_reg_972_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_1_we0 = 1'b1; + end else begin + ifmap_vec_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_2_ce0 = 1'b1; + end else begin + ifmap_vec_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (icmp_ln19_reg_972_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_2_we0 = 1'b1; + end else begin + ifmap_vec_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_3_ce0 = 1'b1; + end else begin + ifmap_vec_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (icmp_ln19_reg_972_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_3_we0 = 1'b1; + end else begin + ifmap_vec_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0)) & ~((ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state8; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln19_7_fu_354_p2 = (indvar_flatten47_reg_231 + 8'd1); + +assign add_ln19_fu_416_p2 = (ap_phi_mux_ii_phi_fu_246_p4 + 2'd1); + +assign add_ln20_7_fu_534_p2 = (indvar_flatten_reg_254 + 7'd1); + +assign add_ln20_fu_487_p2 = (select_ln19_fu_428_p3 + 2'd1); + +assign add_ln22_7_fu_379_p2 = ((sext_ln22_reg_933) + (zext_ln20_fu_375_p1)); + +assign add_ln22_8_fu_513_p2 = ((sext_ln22_reg_933) + (zext_ln20_7_fu_509_p1)); + +assign add_ln22_fu_314_p2 = ((j_cast_i_i_fu_298_p1) + (17'd131071)); + +assign add_ln25_fu_528_p2 = (select_ln20_fu_493_p3 + 7'd4); + +assign add_ln32_fu_795_p2 = ((sext_ln20_fu_782_p1) + (zext_ln32_64_fu_791_p1)); + +assign add_ln33_fu_676_p2 = ((sub_ln33_cast_fu_610_p1) + (zext_ln33_17_fu_673_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd3]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign col_coord_int_fu_583_p3 = ((is_padding_reg_965[0:0] == 1'b1) ? 8'd0 : empty_152_fu_578_p2); + +assign col_coord_int_mid139_fu_652_p3 = ((or_ln23_33_fu_634_p2[0:0] == 1'b1) ? 8'd0 : p_mid137_reg_950); + +assign col_coord_int_mid1_fu_776_p3 = ((or_ln23_35_reg_1053[0:0] == 1'b1) ? 8'd0 : p_mid1_reg_1066); + +assign empty_149_fu_304_p2 = ((zext_ln19_fu_301_p1) + (17'd131071)); + +assign empty_150_fu_364_p2 = ((p_cast_i_i_reg_927) + (ii_cast_i_i_fu_360_p1)); + +assign empty_151_fu_369_p2 = ((empty_150_fu_364_p2 > 18'd13) ? 1'b1 : 1'b0); + +assign empty_152_fu_578_p2 = ((tmp1_cast_fu_574_p1) + (empty_reg_920)); + +assign empty_fu_293_p1 = indices_12_dout[7:0]; + +assign icmp_ln19_fu_410_p2 = ((indvar_flatten47_reg_231 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_422_p2 = ((indvar_flatten_reg_254 == 7'd48) ? 1'b1 : 1'b0); + +assign icmp_ln24_7_fu_392_p2 = (((add_ln22_7_fu_379_p2) > (18'd13)) ? 1'b1 : 1'b0); + +assign icmp_ln24_8_fu_692_p2 = (((add_ln22_8_reg_1021) > (18'd13)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_337_p2 = (((add_ln22_fu_314_p2) > (17'd13)) ? 1'b1 : 1'b0); + +assign ifmap_vec_0_address0 = sext_ln33_fu_897_p1; + +assign ifmap_vec_0_d0 = select_ln33_reg_1081; + +assign ifmap_vec_1_address0 = sext_ln33_fu_897_p1; + +assign ifmap_vec_1_d0 = select_ln33_20_reg_1086; + +assign ifmap_vec_2_address0 = sext_ln33_fu_897_p1; + +assign ifmap_vec_2_d0 = select_ln33_21_reg_1091; + +assign ifmap_vec_3_address0 = sext_ln33_fu_897_p1; + +assign ifmap_vec_3_d0 = select_ln33_22_reg_1096; + +assign ii_cast_fu_548_p1 = ii_reg_242; + +assign ii_cast_i_i_fu_360_p1 = ap_phi_mux_ii_phi_fu_246_p4; + +assign ii_cast_i_i_mid1_fu_452_p1 = add_ln19_fu_416_p2; + +assign ii_cast_mid1_fu_614_p1 = add_ln19_reg_976; + +assign in_data_address0 = sext_ln32_fu_808_p1; + +assign in_data_elem_10_fu_838_p1 = tmp_273_i_i_fu_828_p4; + +assign in_data_elem_11_fu_859_p1 = tmp_274_i_i_fu_849_p4; + +assign in_data_elem_12_fu_880_p1 = tmp_275_i_i_fu_870_p4; + +assign in_data_elem_fu_817_p1 = trunc_ln32_fu_813_p1; + +assign indices_01_out_din = indices_01_dout[3:0]; + +assign indices_12_out_din = indices_12_dout[7:0]; + +assign is_padding_fu_404_p2 = (or_ln23_fu_398_p2 | empty_151_fu_369_p2); + +assign j_cast_i_i_fu_298_p1 = indices_12_read_reg_915; + +assign or_ln19_fu_481_p2 = (xor_ln25_fu_475_p2 | icmp_ln20_fu_422_p2); + +assign or_ln23_31_fu_343_p2 = (tmp_82_fu_329_p3 | icmp_ln24_fu_337_p2); + +assign or_ln23_33_fu_634_p2 = (p_mid113_reg_997 | or_ln23_31_reg_945); + +assign or_ln23_34_fu_697_p2 = (tmp_85_fu_685_p3 | icmp_ln24_8_fu_692_p2); + +assign or_ln23_35_fu_703_p2 = (select_ln19_44_fu_629_p3 | or_ln23_34_fu_697_p2); + +assign or_ln23_fu_398_p2 = (tmp_83_fu_384_p3 | icmp_ln24_7_fu_392_p2); + +assign p_cast28_i_i_fu_552_p2 = (p_cast_reg_939 + ii_cast_fu_548_p1); + +assign p_cast28_i_i_mid1_fu_617_p2 = (p_cast_reg_939 + ii_cast_mid1_fu_614_p1); + +assign p_cast_fu_324_p2 = ((trunc_ln289_reg_910) + (4'd15)); + +assign p_cast_i_i_fu_310_p1 = (empty_149_fu_304_p2); + +assign p_mid111_fu_456_p2 = ((p_cast_i_i_reg_927) + (ii_cast_i_i_mid1_fu_452_p1)); + +assign p_mid113_fu_461_p2 = ((p_mid111_fu_456_p2 > 18'd13) ? 1'b1 : 1'b0); + +assign p_mid137_fu_349_p2 = ((empty_reg_920) + (8'd255)); + +assign p_mid1_fu_734_p2 = ((tmp1_cast_mid1_fu_730_p1) + (empty_reg_920)); + +assign row_coord_int_fu_561_p3 = ((is_padding_reg_965[0:0] == 1'b1) ? 4'd0 : p_cast28_i_i_fu_552_p2); + +assign row_coord_int_mid131_fu_644_p3 = ((or_ln23_33_fu_634_p2[0:0] == 1'b1) ? 4'd0 : p_cast28_i_i_mid1_fu_617_p2); + +assign row_coord_int_mid1_fu_716_p3 = ((or_ln23_35_fu_703_p2[0:0] == 1'b1) ? 4'd0 : select_ln19_43_fu_622_p3); + +assign select_ln19_41_fu_436_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? 7'd0 : kk_reg_277); + +assign select_ln19_42_fu_444_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? add_ln19_fu_416_p2 : ap_phi_mux_ii_phi_fu_246_p4); + +assign select_ln19_43_fu_622_p3 = ((icmp_ln20_reg_981[0:0] == 1'b1) ? p_cast28_i_i_mid1_fu_617_p2 : p_cast28_i_i_fu_552_p2); + +assign select_ln19_44_fu_629_p3 = ((icmp_ln20_reg_981[0:0] == 1'b1) ? p_mid113_reg_997 : empty_151_reg_960); + +assign select_ln19_45_fu_638_p3 = ((icmp_ln20_reg_981[0:0] == 1'b1) ? or_ln23_33_fu_634_p2 : is_padding_reg_965); + +assign select_ln19_46_fu_659_p3 = ((icmp_ln20_reg_981[0:0] == 1'b1) ? row_coord_int_mid131_fu_644_p3 : row_coord_int_fu_561_p3); + +assign select_ln19_47_fu_666_p3 = ((icmp_ln20_reg_981[0:0] == 1'b1) ? col_coord_int_mid139_fu_652_p3 : col_coord_int_fu_583_p3); + +assign select_ln19_fu_428_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_269_p4); + +assign select_ln20_30_fu_501_p3 = ((or_ln19_fu_481_p2[0:0] == 1'b1) ? select_ln19_fu_428_p3 : add_ln20_fu_487_p2); + +assign select_ln20_31_fu_709_p3 = ((or_ln19_reg_1003[0:0] == 1'b1) ? select_ln19_45_fu_638_p3 : or_ln23_35_fu_703_p2); + +assign select_ln20_32_fu_739_p3 = ((or_ln19_reg_1003[0:0] == 1'b1) ? select_ln19_46_fu_659_p3 : row_coord_int_mid1_fu_716_p3); + +assign select_ln20_33_fu_785_p3 = ((or_ln19_reg_1003_pp0_iter1_reg[0:0] == 1'b1) ? select_ln19_47_reg_1043 : col_coord_int_mid1_fu_776_p3); + +assign select_ln20_34_fu_540_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? 7'd1 : add_ln20_7_fu_534_p2); + +assign select_ln20_fu_493_p3 = ((or_ln19_fu_481_p2[0:0] == 1'b1) ? select_ln19_41_fu_436_p3 : 7'd0); + +assign select_ln33_20_fu_842_p3 = ((select_ln20_31_reg_1058_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_10_fu_838_p1); + +assign select_ln33_21_fu_863_p3 = ((select_ln20_31_reg_1058_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_11_fu_859_p1); + +assign select_ln33_22_fu_884_p3 = ((select_ln20_31_reg_1058_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_12_fu_880_p1); + +assign select_ln33_fu_821_p3 = ((select_ln20_31_reg_1058_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_fu_817_p1); + +assign sext_ln20_fu_782_p1 = (sub_ln32_reg_1071); + +assign sext_ln22_fu_320_p1 = add_ln22_fu_314_p2; + +assign sext_ln32_fu_808_p1 = (tmp_86_fu_801_p3); + +assign sext_ln33_fu_897_p1 = (tmp_87_fu_891_p3); + +assign sub_ln32_fu_770_p2 = (zext_ln32_fu_754_p1 - zext_ln32_63_fu_766_p1); + +assign sub_ln33_cast_fu_610_p1 = (sub_ln33_fu_604_p2); + +assign sub_ln33_fu_604_p2 = (zext_ln33_16_fu_600_p1 - zext_ln33_fu_590_p1); + +assign tmp1_cast_fu_574_p1 = (tmp1_fu_568_p2); + +assign tmp1_cast_mid1_fu_730_p1 = (tmp1_mid1_fu_724_p2); + +assign tmp1_fu_568_p2 = ((zext_ln22_fu_557_p1) + (3'd7)); + +assign tmp1_mid1_fu_724_p2 = ((zext_ln22_7_fu_682_p1) + (3'd7)); + +assign tmp_273_i_i_fu_828_p4 = {{in_data_q0[31:16]}}; + +assign tmp_274_i_i_fu_849_p4 = {{in_data_q0[47:32]}}; + +assign tmp_275_i_i_fu_870_p4 = {{in_data_q0[63:48]}}; + +assign tmp_55_fu_758_p3 = {{select_ln20_32_fu_739_p3}, {1'd0}}; + +assign tmp_82_fu_329_p3 = add_ln22_fu_314_p2[32'd16]; + +assign tmp_83_fu_384_p3 = add_ln22_7_fu_379_p2[32'd17]; + +assign tmp_84_fu_467_p3 = kk_reg_277[32'd6]; + +assign tmp_85_fu_685_p3 = add_ln22_8_reg_1021[32'd17]; + +assign tmp_86_fu_801_p3 = {{add_ln32_fu_795_p2}, {lshr_ln_reg_1027_pp0_iter1_reg}}; + +assign tmp_87_fu_891_p3 = {{add_ln33_reg_1048_pp0_iter3_reg}, {lshr_ln_reg_1027_pp0_iter3_reg}}; + +assign tmp_fu_593_p3 = {{select_ln19_42_reg_990}, {2'd0}}; + +assign tmp_s_fu_746_p3 = {{select_ln20_32_fu_739_p3}, {4'd0}}; + +assign trunc_ln289_fu_288_p1 = indices_01_dout[3:0]; + +assign trunc_ln32_fu_813_p1 = in_data_q0[15:0]; + +assign xor_ln25_fu_475_p2 = (tmp_84_fu_467_p3 ^ 1'd1); + +assign zext_ln19_fu_301_p1 = indices_01_read_reg_905; + +assign zext_ln20_7_fu_509_p1 = add_ln20_fu_487_p2; + +assign zext_ln20_fu_375_p1 = ap_phi_mux_jj_phi_fu_269_p4; + +assign zext_ln22_7_fu_682_p1 = add_ln20_reg_1010; + +assign zext_ln22_fu_557_p1 = jj_reg_265; + +assign zext_ln32_63_fu_766_p1 = tmp_55_fu_758_p3; + +assign zext_ln32_64_fu_791_p1 = select_ln20_33_fu_785_p3; + +assign zext_ln32_fu_754_p1 = tmp_s_fu_746_p3; + +assign zext_ln33_16_fu_600_p1 = tmp_fu_593_p3; + +assign zext_ln33_17_fu_673_p1 = select_ln20_30_reg_1015; + +assign zext_ln33_fu_590_p1 = select_ln19_42_reg_990; + +always @ (posedge ap_clk) begin + sub_ln32_reg_1071[0] <= 1'b0; +end + +endmodule //td_fused_top_tdf11_readInputs78 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_13 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_0_address0, + filter_data_0_ce0, + filter_data_0_d0, + filter_data_0_q0, + filter_data_0_we0, + filter_data_0_address1, + filter_data_0_ce1, + filter_data_0_d1, + filter_data_0_q1, + filter_data_0_we1, + filter_data_1_address0, + filter_data_1_ce0, + filter_data_1_d0, + filter_data_1_q0, + filter_data_1_we0, + filter_data_1_address1, + filter_data_1_ce1, + filter_data_1_d1, + filter_data_1_q1, + filter_data_1_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [12:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [12:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [15:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [15:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [14:0] filter_data_0_address0; +output filter_data_0_ce0; +output [31:0] filter_data_0_d0; +input [31:0] filter_data_0_q0; +output filter_data_0_we0; +output [14:0] filter_data_0_address1; +output filter_data_0_ce1; +output [31:0] filter_data_0_d1; +input [31:0] filter_data_0_q1; +output filter_data_0_we1; +output [14:0] filter_data_1_address0; +output filter_data_1_ce0; +output [31:0] filter_data_1_d0; +input [31:0] filter_data_1_q0; +output filter_data_1_we0; +output [14:0] filter_data_1_address1; +output filter_data_1_ce1; +output [31:0] filter_data_1_d1; +input [31:0] filter_data_1_q1; +output filter_data_1_we1; +output [9:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [9:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [12:0] dataflow_in_loop_TOP_LOOP47680_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP47680_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP47680_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP47680_U0_in_data_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP47680_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP47680_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP47680_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP47680_U0_in_data_we1; +wire [14:0] dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_address0; +wire dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_ce0; +wire [31:0] dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_d0; +wire dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_address1; +wire dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_ce1; +wire [31:0] dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_d1; +wire dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_we1; +wire [14:0] dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_address0; +wire dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_ce0; +wire [31:0] dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_d0; +wire dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_address1; +wire dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_ce1; +wire [31:0] dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_d1; +wire dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_we1; +wire [9:0] dataflow_in_loop_TOP_LOOP47680_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP47680_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP47680_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP47680_U0_adjustments_we0; +wire [9:0] dataflow_in_loop_TOP_LOOP47680_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP47680_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP47680_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP47680_U0_adjustments_we1; +wire [15:0] dataflow_in_loop_TOP_LOOP47680_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP47680_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP47680_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP47680_U0_out_data_we0; +wire [15:0] dataflow_in_loop_TOP_LOOP47680_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP47680_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP47680_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP47680_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP47680_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP47680_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP47680_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP47680_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP47680_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP47680_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP47680_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP47680_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP47680_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [16:0] loop_dataflow_input_count; +reg [16:0] loop_dataflow_output_count; +wire [16:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP47680_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP47680_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 17'd0; +#0 loop_dataflow_output_count = 17'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP47680 dataflow_in_loop_TOP_LOOP47680_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP47680_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP47680_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP47680_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP47680_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP47680_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP47680_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP47680_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP47680_U0_in_data_we1), + .filter_data_0_address0(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_address0), + .filter_data_0_ce0(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_ce0), + .filter_data_0_d0(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_d0), + .filter_data_0_q0(filter_data_0_q0), + .filter_data_0_we0(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_we0), + .filter_data_0_address1(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_address1), + .filter_data_0_ce1(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_ce1), + .filter_data_0_d1(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_d1), + .filter_data_0_q1(32'd0), + .filter_data_0_we1(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_we1), + .filter_data_1_address0(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_address0), + .filter_data_1_ce0(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_ce0), + .filter_data_1_d0(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_d0), + .filter_data_1_q0(filter_data_1_q0), + .filter_data_1_we0(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_we0), + .filter_data_1_address1(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_address1), + .filter_data_1_ce1(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_ce1), + .filter_data_1_d1(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_d1), + .filter_data_1_q1(32'd0), + .filter_data_1_we1(dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP47680_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP47680_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP47680_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP47680_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP47680_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP47680_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP47680_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP47680_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP47680_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP47680_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP47680_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP47680_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP47680_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP47680_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP47680_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP47680_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP47680_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP47680_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP47680_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP47680_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP47680_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP47680_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP47680_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 17'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP47680_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 17'd1); + end else if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP47680_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= 17'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 17'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP47680_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP47680_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 17'd1); + end else if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP47680_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP47680_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= 17'd0; + end + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP47680_U0_ap_done == 1'b1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == 17'd0) & (ap_start == 1'b0) & (dataflow_in_loop_TOP_LOOP47680_U0_ap_idle == 1'b1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP47680_U0_ap_ready == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP47680_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP47680_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP47680_U0_adjustments_address0; + +assign adjustments_address1 = 10'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP47680_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP47680_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP47680_U0_ap_ready; + +assign bound_minus_1 = (17'd98000 - 17'd1); + +assign dataflow_in_loop_TOP_LOOP47680_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP47680_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP47680_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP47680_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP47680_U0_start_write = 1'b0; + +assign filter_data_0_address0 = dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_address0; + +assign filter_data_0_address1 = 15'd0; + +assign filter_data_0_ce0 = dataflow_in_loop_TOP_LOOP47680_U0_filter_data_0_ce0; + +assign filter_data_0_ce1 = 1'b0; + +assign filter_data_0_d0 = 32'd0; + +assign filter_data_0_d1 = 32'd0; + +assign filter_data_0_we0 = 1'b0; + +assign filter_data_0_we1 = 1'b0; + +assign filter_data_1_address0 = dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_address0; + +assign filter_data_1_address1 = 15'd0; + +assign filter_data_1_ce0 = dataflow_in_loop_TOP_LOOP47680_U0_filter_data_1_ce0; + +assign filter_data_1_ce1 = 1'b0; + +assign filter_data_1_d0 = 32'd0; + +assign filter_data_1_d1 = 32'd0; + +assign filter_data_1_we0 = 1'b0; + +assign filter_data_1_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP47680_U0_in_data_address0; + +assign in_data_address1 = 13'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP47680_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP47680_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 16'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP47680_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP47680_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP47680_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP47680_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP47680_U0_out_data_write; + +endmodule //td_fused_top_tdf12_13 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_in1_address0, + accum_in1_ce0, + accum_in1_q0, + accum_in1_address1, + accum_in1_ce1, + accum_in1_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_pp0_stage0 = 11'd2; +parameter ap_ST_fsm_pp0_stage1 = 11'd4; +parameter ap_ST_fsm_pp0_stage2 = 11'd8; +parameter ap_ST_fsm_pp0_stage3 = 11'd16; +parameter ap_ST_fsm_pp0_stage4 = 11'd32; +parameter ap_ST_fsm_pp0_stage5 = 11'd64; +parameter ap_ST_fsm_pp0_stage6 = 11'd128; +parameter ap_ST_fsm_state17 = 11'd256; +parameter ap_ST_fsm_state18 = 11'd512; +parameter ap_ST_fsm_state19 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [5:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [5:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [5:0] accum_in1_address0; +output accum_in1_ce0; +input [15:0] accum_in1_q0; +output [5:0] accum_in1_address1; +output accum_in1_ce1; +input [15:0] accum_in1_q1; +output [3:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [3:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[5:0] accum_in_address0; +reg accum_in_ce0; +reg[5:0] accum_in_address1; +reg accum_in_ce1; +reg[5:0] accum_in1_address0; +reg accum_in1_ce0; +reg[5:0] accum_in1_address1; +reg accum_in1_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] x_reg_263; +reg [15:0] psum_2_03_reg_274; +reg [15:0] psum_1_02_reg_286; +reg [15:0] psum_0_01_reg_298; +reg [15:0] psum_15_016_reg_310; +reg [15:0] psum_14_015_reg_322; +reg [15:0] psum_13_014_reg_334; +reg [15:0] psum_12_013_reg_346; +reg [15:0] psum_11_012_reg_358; +reg [15:0] psum_10_011_reg_370; +reg [15:0] psum_9_010_reg_382; +reg [15:0] psum_8_09_reg_394; +reg [15:0] psum_7_08_reg_406; +reg [15:0] psum_6_07_reg_418; +reg [15:0] psum_5_06_reg_430; +reg [15:0] psum_4_05_reg_442; +reg [15:0] psum_3_04_reg_454; +wire [0:0] tmp_fu_535_p3; +reg [0:0] tmp_reg_776; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state9_pp0_stage0_iter1; +wire ap_block_state16_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] tmp_reg_776_pp0_iter1_reg; +wire [7:0] add_ln25_fu_543_p2; +reg [7:0] add_ln25_reg_780; +reg ap_enable_reg_pp0_iter0; +wire [5:0] lshr_ln_fu_549_p4; +reg [5:0] lshr_ln_reg_785; +reg [15:0] accum_in_load_reg_815; +wire ap_CS_fsm_pp0_stage1; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state10_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in1_load_reg_820; +reg [15:0] accum_in_load_36_reg_825; +reg [15:0] accum_in1_load_22_reg_830; +reg [15:0] accum_in_load_37_reg_855; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state11_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in1_load_23_reg_860; +reg [15:0] accum_in_load_38_reg_865; +reg [15:0] accum_in1_load_24_reg_870; +reg [15:0] accum_in_load_39_reg_895; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state12_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in1_load_25_reg_900; +reg [15:0] accum_in_load_40_reg_905; +reg [15:0] accum_in1_load_26_reg_910; +reg [15:0] accum_in_load_41_reg_935; +wire ap_CS_fsm_pp0_stage4; +wire ap_block_state6_pp0_stage4_iter0; +wire ap_block_state13_pp0_stage4_iter1; +wire ap_block_pp0_stage4_11001; +reg [15:0] accum_in1_load_27_reg_940; +reg [15:0] accum_in_load_42_reg_945; +reg [15:0] accum_in1_load_28_reg_950; +wire [15:0] grp_fu_507_p2; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_512_p2; +wire [15:0] grp_fu_517_p2; +wire ap_CS_fsm_pp0_stage5; +wire ap_block_state7_pp0_stage5_iter0; +wire ap_block_state14_pp0_stage5_iter1; +wire ap_block_pp0_stage5_11001; +wire ap_CS_fsm_pp0_stage6; +wire ap_block_state8_pp0_stage6_iter0; +wire ap_block_state15_pp0_stage6_iter1; +wire ap_block_pp0_stage6_11001; +reg ap_enable_reg_pp0_iter2; +wire [4:0] add_ln33_fu_660_p2; +wire ap_CS_fsm_state18; +wire [0:0] tmp_81_fu_643_p3; +reg ap_block_state1; +wire ap_block_pp0_stage3_subdone; +reg ap_condition_pp0_exit_iter0_state5; +wire ap_block_pp0_stage6_subdone; +wire ap_block_pp0_stage0_subdone; +reg [7:0] ap_phi_mux_x_phi_fu_267_p4; +wire ap_block_pp0_stage0; +wire ap_block_pp0_stage2; +wire [15:0] ap_phi_mux_psum_15_016_phi_fu_314_p4; +wire [15:0] ap_phi_mux_psum_14_015_phi_fu_326_p4; +wire ap_block_pp0_stage6; +wire [15:0] ap_phi_mux_psum_13_014_phi_fu_338_p4; +wire [15:0] ap_phi_mux_psum_12_013_phi_fu_350_p4; +wire [15:0] ap_phi_mux_psum_11_012_phi_fu_362_p4; +wire ap_block_pp0_stage5; +wire [15:0] ap_phi_mux_psum_10_011_phi_fu_374_p4; +wire [15:0] ap_phi_mux_psum_9_010_phi_fu_386_p4; +wire [15:0] ap_phi_mux_psum_8_09_phi_fu_398_p4; +wire ap_block_pp0_stage4; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_410_p4; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_422_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_434_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_446_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_458_p4; +reg [4:0] q_reg_466; +wire ap_CS_fsm_state17; +reg [15:0] ap_phi_mux_phi_ln45_phi_fu_480_p16; +wire [3:0] trunc_ln33_fu_656_p1; +wire [63:0] zext_ln29_fu_559_p1; +wire [63:0] zext_ln29_22_fu_571_p1; +wire [63:0] zext_ln29_23_fu_582_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln29_24_fu_593_p1; +wire [63:0] zext_ln29_25_fu_604_p1; +wire [63:0] zext_ln29_26_fu_615_p1; +wire [63:0] zext_ln29_27_fu_626_p1; +wire [63:0] zext_ln29_28_fu_637_p1; +wire [63:0] zext_ln33_fu_651_p1; +wire [63:0] zext_ln33_4_fu_672_p1; +reg [15:0] grp_fu_507_p0; +reg [15:0] grp_fu_507_p1; +reg [15:0] grp_fu_512_p0; +reg [15:0] grp_fu_512_p1; +reg [15:0] grp_fu_517_p0; +reg [15:0] grp_fu_517_p1; +wire [5:0] or_ln29_fu_565_p2; +wire [5:0] or_ln29_19_fu_577_p2; +wire [5:0] or_ln29_20_fu_588_p2; +wire [5:0] or_ln29_21_fu_599_p2; +wire [5:0] or_ln29_22_fu_610_p2; +wire [5:0] or_ln29_23_fu_621_p2; +wire [5:0] or_ln29_24_fu_632_p2; +wire [3:0] or_ln33_fu_666_p2; +wire [0:0] icmp_ln45_fu_677_p2; +wire [0:0] icmp_ln45_7_fu_691_p2; +wire [15:0] select_ln45_fu_683_p3; +wire [0:0] icmp_ln45_8_fu_705_p2; +wire [15:0] select_ln45_7_fu_697_p3; +wire [0:0] icmp_ln45_9_fu_719_p2; +wire [15:0] select_ln45_8_fu_711_p3; +wire [0:0] icmp_ln45_10_fu_733_p2; +wire [15:0] select_ln45_9_fu_725_p3; +wire [0:0] icmp_ln45_11_fu_747_p2; +wire [15:0] select_ln45_10_fu_739_p3; +wire [0:0] icmp_ln45_12_fu_761_p2; +wire [15:0] select_ln45_11_fu_753_p3; +wire ap_CS_fsm_state19; +reg [10:0] ap_NS_fsm; +wire ap_block_pp0_stage1_subdone; +wire ap_block_pp0_stage2_subdone; +wire ap_block_pp0_stage4_subdone; +wire ap_block_pp0_stage5_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_726; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1901( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_507_p0), + .din1(grp_fu_507_p1), + .dout(grp_fu_507_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1902( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_512_p0), + .din1(grp_fu_512_p1), + .dout(grp_fu_512_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1903( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_517_p0), + .din1(grp_fu_517_p1), + .dout(grp_fu_517_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state19)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state5) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6_subdone))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6_subdone)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + q_reg_466 <= 5'd0; + end else if (((tmp_81_fu_643_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + q_reg_466 <= add_ln33_fu_660_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_776 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + x_reg_263 <= add_ln25_reg_780; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_263 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_776 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + accum_in1_load_22_reg_830 <= accum_in1_q0; + accum_in1_load_reg_820 <= accum_in1_q1; + accum_in_load_36_reg_825 <= accum_in_q0; + accum_in_load_reg_815 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_776 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001))) begin + accum_in1_load_23_reg_860 <= accum_in1_q1; + accum_in1_load_24_reg_870 <= accum_in1_q0; + accum_in_load_37_reg_855 <= accum_in_q1; + accum_in_load_38_reg_865 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_776 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + accum_in1_load_25_reg_900 <= accum_in1_q1; + accum_in1_load_26_reg_910 <= accum_in1_q0; + accum_in_load_39_reg_895 <= accum_in_q1; + accum_in_load_40_reg_905 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_776 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4_11001))) begin + accum_in1_load_27_reg_940 <= accum_in1_q1; + accum_in1_load_28_reg_950 <= accum_in1_q0; + accum_in_load_41_reg_935 <= accum_in_q1; + accum_in_load_42_reg_945 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_fu_535_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln25_reg_780 <= add_ln25_fu_543_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_fu_535_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + lshr_ln_reg_785 <= {{ap_phi_mux_x_phi_fu_267_p4[6:1]}}; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (tmp_reg_776_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage2_11001))) begin + psum_0_01_reg_298 <= grp_fu_507_p2; + psum_1_02_reg_286 <= grp_fu_512_p2; + psum_2_03_reg_274 <= grp_fu_517_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (tmp_reg_776_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage5_11001))) begin + psum_10_011_reg_370 <= grp_fu_512_p2; + psum_11_012_reg_358 <= grp_fu_517_p2; + psum_9_010_reg_382 <= grp_fu_507_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage6) & (tmp_reg_776_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage6_11001))) begin + psum_12_013_reg_346 <= grp_fu_507_p2; + psum_13_014_reg_334 <= grp_fu_512_p2; + psum_14_015_reg_322 <= grp_fu_517_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (tmp_reg_776_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + psum_15_016_reg_310 <= grp_fu_507_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (tmp_reg_776_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001))) begin + psum_3_04_reg_454 <= grp_fu_507_p2; + psum_4_05_reg_442 <= grp_fu_512_p2; + psum_5_06_reg_430 <= grp_fu_517_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (tmp_reg_776_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage4_11001))) begin + psum_6_07_reg_418 <= grp_fu_507_p2; + psum_7_08_reg_406 <= grp_fu_512_p2; + psum_8_09_reg_394 <= grp_fu_517_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + tmp_reg_776 <= ap_phi_mux_x_phi_fu_267_p4[32'd7]; + tmp_reg_776_pp0_iter1_reg <= tmp_reg_776; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in1_address0 = zext_ln29_28_fu_637_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in1_address0 = zext_ln29_26_fu_615_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in1_address0 = zext_ln29_24_fu_593_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in1_address0 = zext_ln29_22_fu_571_p1; + end else begin + accum_in1_address0 = 'bx; + end + end else begin + accum_in1_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in1_address1 = zext_ln29_27_fu_626_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in1_address1 = zext_ln29_25_fu_604_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in1_address1 = zext_ln29_23_fu_582_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in1_address1 = zext_ln29_fu_559_p1; + end else begin + accum_in1_address1 = 'bx; + end + end else begin + accum_in1_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in1_ce0 = 1'b1; + end else begin + accum_in1_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in1_ce1 = 1'b1; + end else begin + accum_in1_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in_address0 = zext_ln29_28_fu_637_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in_address0 = zext_ln29_26_fu_615_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in_address0 = zext_ln29_24_fu_593_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in_address0 = zext_ln29_22_fu_571_p1; + end else begin + accum_in_address0 = 'bx; + end + end else begin + accum_in_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in_address1 = zext_ln29_27_fu_626_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in_address1 = zext_ln29_25_fu_604_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in_address1 = zext_ln29_23_fu_582_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in_address1 = zext_ln29_fu_559_p1; + end else begin + accum_in_address1 = 'bx; + end + end else begin + accum_in_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state18)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state18)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_81_fu_643_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_81_fu_643_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_reg_776 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state5 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state5 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state19)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_81_fu_643_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + if ((trunc_ln33_fu_656_p1 == 4'd0)) begin + ap_phi_mux_phi_ln45_phi_fu_480_p16 = psum_0_01_reg_298; + end else if ((1'b1 == ap_condition_726)) begin + ap_phi_mux_phi_ln45_phi_fu_480_p16 = psum_14_015_reg_322; + end else if ((trunc_ln33_fu_656_p1 == 4'd12)) begin + ap_phi_mux_phi_ln45_phi_fu_480_p16 = psum_12_013_reg_346; + end else if ((trunc_ln33_fu_656_p1 == 4'd10)) begin + ap_phi_mux_phi_ln45_phi_fu_480_p16 = psum_10_011_reg_370; + end else if ((trunc_ln33_fu_656_p1 == 4'd8)) begin + ap_phi_mux_phi_ln45_phi_fu_480_p16 = psum_8_09_reg_394; + end else if ((trunc_ln33_fu_656_p1 == 4'd6)) begin + ap_phi_mux_phi_ln45_phi_fu_480_p16 = psum_6_07_reg_418; + end else if ((trunc_ln33_fu_656_p1 == 4'd4)) begin + ap_phi_mux_phi_ln45_phi_fu_480_p16 = psum_4_05_reg_442; + end else if ((trunc_ln33_fu_656_p1 == 4'd2)) begin + ap_phi_mux_phi_ln45_phi_fu_480_p16 = psum_2_03_reg_274; + end else begin + ap_phi_mux_phi_ln45_phi_fu_480_p16 = 'bx; + end + end else begin + ap_phi_mux_phi_ln45_phi_fu_480_p16 = 'bx; + end +end + +always @ (*) begin + if (((tmp_reg_776 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_x_phi_fu_267_p4 = add_ln25_reg_780; + end else begin + ap_phi_mux_x_phi_fu_267_p4 = x_reg_263; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state19)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_507_p0 = ap_phi_mux_psum_15_016_phi_fu_314_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_507_p0 = ap_phi_mux_psum_12_013_phi_fu_350_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_507_p0 = ap_phi_mux_psum_9_010_phi_fu_386_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_507_p0 = ap_phi_mux_psum_6_07_phi_fu_422_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_507_p0 = ap_phi_mux_psum_3_04_phi_fu_458_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_507_p0 = grp_fu_507_p2; + end else begin + grp_fu_507_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_507_p1 = accum_in1_load_28_reg_950; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_507_p1 = accum_in_load_41_reg_935; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_507_p1 = accum_in1_load_25_reg_900; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_507_p1 = accum_in_load_38_reg_865; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_507_p1 = accum_in1_load_22_reg_830; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_507_p1 = accum_in_load_reg_815; + end else begin + grp_fu_507_p1 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_512_p0 = ap_phi_mux_psum_13_014_phi_fu_338_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_512_p0 = ap_phi_mux_psum_10_011_phi_fu_374_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_512_p0 = ap_phi_mux_psum_7_08_phi_fu_410_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_512_p0 = ap_phi_mux_psum_4_05_phi_fu_446_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_512_p0 = grp_fu_512_p2; + end else begin + grp_fu_512_p0 = 'bx; + end + end else begin + grp_fu_512_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_512_p1 = accum_in1_load_27_reg_940; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_512_p1 = accum_in_load_40_reg_905; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_512_p1 = accum_in1_load_24_reg_870; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_512_p1 = accum_in_load_37_reg_855; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_512_p1 = accum_in1_load_reg_820; + end else begin + grp_fu_512_p1 = 'bx; + end + end else begin + grp_fu_512_p1 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_517_p0 = ap_phi_mux_psum_14_015_phi_fu_326_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_517_p0 = ap_phi_mux_psum_11_012_phi_fu_362_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_517_p0 = ap_phi_mux_psum_8_09_phi_fu_398_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_517_p0 = ap_phi_mux_psum_5_06_phi_fu_434_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_517_p0 = grp_fu_517_p2; + end else begin + grp_fu_517_p0 = 'bx; + end + end else begin + grp_fu_517_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_517_p1 = accum_in_load_42_reg_945; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_517_p1 = accum_in1_load_26_reg_910; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_517_p1 = accum_in_load_39_reg_895; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_517_p1 = accum_in1_load_23_reg_860; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_517_p1 = accum_in_load_36_reg_825; + end else begin + grp_fu_517_p1 = 'bx; + end + end else begin + grp_fu_517_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if (((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state17; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((1'b0 == ap_block_pp0_stage2_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((~((tmp_reg_776 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_subdone)) & (1'b0 == ap_block_pp0_stage3_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end else if (((tmp_reg_776 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state17; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_pp0_stage4 : begin + if ((1'b0 == ap_block_pp0_stage4_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end + end + ap_ST_fsm_pp0_stage5 : begin + if ((1'b0 == ap_block_pp0_stage5_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end + end + ap_ST_fsm_pp0_stage6 : begin + if ((1'b0 == ap_block_pp0_stage6_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state18; + end + ap_ST_fsm_state18 : begin + if (((tmp_81_fu_643_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + ap_NS_fsm = ap_ST_fsm_state18; + end else begin + ap_NS_fsm = ap_ST_fsm_state19; + end + end + ap_ST_fsm_state19 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln33_4_fu_672_p1; + +assign accum_out_address1 = zext_ln33_fu_651_p1; + +assign accum_out_d0 = ((icmp_ln45_12_fu_761_p2[0:0] == 1'b1) ? psum_13_014_reg_334 : select_ln45_11_fu_753_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln45_phi_fu_480_p16; + +assign add_ln25_fu_543_p2 = (ap_phi_mux_x_phi_fu_267_p4 + 8'd16); + +assign add_ln33_fu_660_p2 = (q_reg_466 + 5'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd8]; + +assign ap_CS_fsm_state18 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state19 = ap_CS_fsm[32'd10]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage4_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage5_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage6_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_726 = (~(trunc_ln33_fu_656_p1 == 4'd0) & ~(trunc_ln33_fu_656_p1 == 4'd12) & ~(trunc_ln33_fu_656_p1 == 4'd10) & ~(trunc_ln33_fu_656_p1 == 4'd8) & ~(trunc_ln33_fu_656_p1 == 4'd6) & ~(trunc_ln33_fu_656_p1 == 4'd4) & ~(trunc_ln33_fu_656_p1 == 4'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_10_011_phi_fu_374_p4 = grp_fu_512_p2; + +assign ap_phi_mux_psum_11_012_phi_fu_362_p4 = grp_fu_517_p2; + +assign ap_phi_mux_psum_12_013_phi_fu_350_p4 = grp_fu_507_p2; + +assign ap_phi_mux_psum_13_014_phi_fu_338_p4 = grp_fu_512_p2; + +assign ap_phi_mux_psum_14_015_phi_fu_326_p4 = grp_fu_517_p2; + +assign ap_phi_mux_psum_15_016_phi_fu_314_p4 = grp_fu_507_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_458_p4 = grp_fu_507_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_446_p4 = grp_fu_512_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_434_p4 = grp_fu_517_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_422_p4 = grp_fu_507_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_410_p4 = grp_fu_512_p2; + +assign ap_phi_mux_psum_8_09_phi_fu_398_p4 = grp_fu_517_p2; + +assign ap_phi_mux_psum_9_010_phi_fu_386_p4 = grp_fu_507_p2; + +assign icmp_ln45_10_fu_733_p2 = ((or_ln33_fu_666_p2 == 4'd9) ? 1'b1 : 1'b0); + +assign icmp_ln45_11_fu_747_p2 = ((or_ln33_fu_666_p2 == 4'd11) ? 1'b1 : 1'b0); + +assign icmp_ln45_12_fu_761_p2 = ((or_ln33_fu_666_p2 == 4'd13) ? 1'b1 : 1'b0); + +assign icmp_ln45_7_fu_691_p2 = ((or_ln33_fu_666_p2 == 4'd3) ? 1'b1 : 1'b0); + +assign icmp_ln45_8_fu_705_p2 = ((or_ln33_fu_666_p2 == 4'd5) ? 1'b1 : 1'b0); + +assign icmp_ln45_9_fu_719_p2 = ((or_ln33_fu_666_p2 == 4'd7) ? 1'b1 : 1'b0); + +assign icmp_ln45_fu_677_p2 = ((or_ln33_fu_666_p2 == 4'd1) ? 1'b1 : 1'b0); + +assign lshr_ln_fu_549_p4 = {{ap_phi_mux_x_phi_fu_267_p4[6:1]}}; + +assign or_ln29_19_fu_577_p2 = (lshr_ln_reg_785 | 6'd2); + +assign or_ln29_20_fu_588_p2 = (lshr_ln_reg_785 | 6'd3); + +assign or_ln29_21_fu_599_p2 = (lshr_ln_reg_785 | 6'd4); + +assign or_ln29_22_fu_610_p2 = (lshr_ln_reg_785 | 6'd5); + +assign or_ln29_23_fu_621_p2 = (lshr_ln_reg_785 | 6'd6); + +assign or_ln29_24_fu_632_p2 = (lshr_ln_reg_785 | 6'd7); + +assign or_ln29_fu_565_p2 = (lshr_ln_fu_549_p4 | 6'd1); + +assign or_ln33_fu_666_p2 = (trunc_ln33_fu_656_p1 | 4'd1); + +assign select_ln45_10_fu_739_p3 = ((icmp_ln45_10_fu_733_p2[0:0] == 1'b1) ? psum_9_010_reg_382 : select_ln45_9_fu_725_p3); + +assign select_ln45_11_fu_753_p3 = ((icmp_ln45_11_fu_747_p2[0:0] == 1'b1) ? psum_11_012_reg_358 : select_ln45_10_fu_739_p3); + +assign select_ln45_7_fu_697_p3 = ((icmp_ln45_7_fu_691_p2[0:0] == 1'b1) ? psum_3_04_reg_454 : select_ln45_fu_683_p3); + +assign select_ln45_8_fu_711_p3 = ((icmp_ln45_8_fu_705_p2[0:0] == 1'b1) ? psum_5_06_reg_430 : select_ln45_7_fu_697_p3); + +assign select_ln45_9_fu_725_p3 = ((icmp_ln45_9_fu_719_p2[0:0] == 1'b1) ? psum_7_08_reg_406 : select_ln45_8_fu_711_p3); + +assign select_ln45_fu_683_p3 = ((icmp_ln45_fu_677_p2[0:0] == 1'b1) ? psum_1_02_reg_286 : psum_15_016_reg_310); + +assign tmp_81_fu_643_p3 = q_reg_466[32'd4]; + +assign tmp_fu_535_p3 = ap_phi_mux_x_phi_fu_267_p4[32'd7]; + +assign trunc_ln33_fu_656_p1 = q_reg_466[3:0]; + +assign zext_ln29_22_fu_571_p1 = or_ln29_fu_565_p2; + +assign zext_ln29_23_fu_582_p1 = or_ln29_19_fu_577_p2; + +assign zext_ln29_24_fu_593_p1 = or_ln29_20_fu_588_p2; + +assign zext_ln29_25_fu_604_p1 = or_ln29_21_fu_599_p2; + +assign zext_ln29_26_fu_615_p1 = or_ln29_22_fu_610_p2; + +assign zext_ln29_27_fu_626_p1 = or_ln29_23_fu_621_p2; + +assign zext_ln29_28_fu_637_p1 = or_ln29_24_fu_632_p2; + +assign zext_ln29_fu_559_p1 = lshr_ln_fu_549_p4; + +assign zext_ln33_4_fu_672_p1 = or_ln33_fu_666_p2; + +assign zext_ln33_fu_651_p1 = q_reg_466; + +endmodule //td_fused_top_tdf12_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state13 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [3:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [3:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_ce0; +reg accum_in_ce1; +reg accum_out_ce0; +reg accum_out_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [3:0] out_idx_reg_66; +reg [3:0] out_idx_reg_66_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_pp0_stage0_11001; +reg [3:0] out_idx_reg_66_pp0_iter2_reg; +reg [3:0] out_idx_reg_66_pp0_iter3_reg; +reg [3:0] out_idx_reg_66_pp0_iter4_reg; +reg [3:0] out_idx_reg_66_pp0_iter5_reg; +reg [3:0] out_idx_reg_66_pp0_iter6_reg; +reg [3:0] out_idx_reg_66_pp0_iter7_reg; +reg [3:0] out_idx_reg_66_pp0_iter8_reg; +reg [3:0] out_idx_reg_66_pp0_iter9_reg; +wire [3:0] add_ln74_fu_82_p2; +reg [3:0] add_ln74_reg_121; +reg ap_enable_reg_pp0_iter0; +wire [0:0] icmp_ln60_fu_88_p2; +reg [0:0] icmp_ln60_reg_126; +reg [0:0] icmp_ln60_reg_126_pp0_iter1_reg; +reg [0:0] icmp_ln60_reg_126_pp0_iter2_reg; +reg [0:0] icmp_ln60_reg_126_pp0_iter3_reg; +reg [0:0] icmp_ln60_reg_126_pp0_iter4_reg; +reg [0:0] icmp_ln60_reg_126_pp0_iter5_reg; +reg [0:0] icmp_ln60_reg_126_pp0_iter6_reg; +reg [0:0] icmp_ln60_reg_126_pp0_iter7_reg; +reg [0:0] icmp_ln60_reg_126_pp0_iter8_reg; +reg [0:0] icmp_ln60_reg_126_pp0_iter9_reg; +reg [15:0] accum_in_load_reg_140; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_load_1_reg_145; +wire [15:0] grp_fu_78_p2; +reg [15:0] sum0_reg_150; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg [3:0] ap_phi_mux_out_idx_phi_fu_70_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln70_fu_100_p1; +wire [63:0] zext_ln70_2_fu_111_p1; +wire [63:0] zext_ln60_fu_116_p1; +wire [3:0] i_12_fu_94_p2; +wire [3:0] or_ln70_fu_105_p2; +wire ap_CS_fsm_state13; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1907( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(accum_in_load_1_reg_145), + .din1(accum_in_load_reg_140), + .dout(grp_fu_78_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_66 <= 4'd0; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln60_reg_126 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + out_idx_reg_66 <= add_ln74_reg_121; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln60_reg_126 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_load_1_reg_145 <= accum_in_q0; + accum_in_load_reg_140 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln74_reg_121 <= add_ln74_fu_82_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln60_reg_126 <= icmp_ln60_fu_88_p2; + icmp_ln60_reg_126_pp0_iter1_reg <= icmp_ln60_reg_126; + out_idx_reg_66_pp0_iter1_reg <= out_idx_reg_66; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln60_reg_126_pp0_iter2_reg <= icmp_ln60_reg_126_pp0_iter1_reg; + icmp_ln60_reg_126_pp0_iter3_reg <= icmp_ln60_reg_126_pp0_iter2_reg; + icmp_ln60_reg_126_pp0_iter4_reg <= icmp_ln60_reg_126_pp0_iter3_reg; + icmp_ln60_reg_126_pp0_iter5_reg <= icmp_ln60_reg_126_pp0_iter4_reg; + icmp_ln60_reg_126_pp0_iter6_reg <= icmp_ln60_reg_126_pp0_iter5_reg; + icmp_ln60_reg_126_pp0_iter7_reg <= icmp_ln60_reg_126_pp0_iter6_reg; + icmp_ln60_reg_126_pp0_iter8_reg <= icmp_ln60_reg_126_pp0_iter7_reg; + icmp_ln60_reg_126_pp0_iter9_reg <= icmp_ln60_reg_126_pp0_iter8_reg; + out_idx_reg_66_pp0_iter2_reg <= out_idx_reg_66_pp0_iter1_reg; + out_idx_reg_66_pp0_iter3_reg <= out_idx_reg_66_pp0_iter2_reg; + out_idx_reg_66_pp0_iter4_reg <= out_idx_reg_66_pp0_iter3_reg; + out_idx_reg_66_pp0_iter5_reg <= out_idx_reg_66_pp0_iter4_reg; + out_idx_reg_66_pp0_iter6_reg <= out_idx_reg_66_pp0_iter5_reg; + out_idx_reg_66_pp0_iter7_reg <= out_idx_reg_66_pp0_iter6_reg; + out_idx_reg_66_pp0_iter8_reg <= out_idx_reg_66_pp0_iter7_reg; + out_idx_reg_66_pp0_iter9_reg <= out_idx_reg_66_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln60_reg_126_pp0_iter8_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sum0_reg_150 <= grp_fu_78_p2; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln60_reg_126_pp0_iter9_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln60_fu_88_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln60_reg_126 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_out_idx_phi_fu_70_p4 = add_ln74_reg_121; + end else begin + ap_phi_mux_out_idx_phi_fu_70_p4 = out_idx_reg_66; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln60_fu_88_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_enable_reg_pp0_iter9 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln60_fu_88_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_enable_reg_pp0_iter9 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln70_2_fu_111_p1; + +assign accum_in_address1 = zext_ln70_fu_100_p1; + +assign accum_out_address0 = zext_ln60_fu_116_p1; + +assign accum_out_d0 = sum0_reg_150; + +assign add_ln74_fu_82_p2 = (ap_phi_mux_out_idx_phi_fu_70_p4 + 4'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign i_12_fu_94_p2 = ap_phi_mux_out_idx_phi_fu_70_p4 << 4'd1; + +assign icmp_ln60_fu_88_p2 = ((ap_phi_mux_out_idx_phi_fu_70_p4 == 4'd8) ? 1'b1 : 1'b0); + +assign or_ln70_fu_105_p2 = (i_12_fu_94_p2 | 4'd1); + +assign zext_ln60_fu_116_p1 = out_idx_reg_66_pp0_iter9_reg; + +assign zext_ln70_2_fu_111_p1 = or_ln70_fu_105_p2; + +assign zext_ln70_fu_100_p1 = i_12_fu_94_p2; + +endmodule //td_fused_top_tdf12_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_accum_3_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_38, + accum_in_38_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_38; +output accum_in_38_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_38; +reg accum_in_38_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln87_fu_73_p2; +reg [3:0] add_ln87_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln87_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln87_fu_79_p1; +reg [15:0] accum_in_38_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_38_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1914( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_38_preg <= 16'd0; + end else begin + if (((icmp_ln87_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_38_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln87_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln87_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln87_reg_90 <= add_ln87_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln87_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_38 = sum_01_reg_55; + end else begin + accum_in_38 = accum_in_38_preg; + end +end + +always @ (*) begin + if (((icmp_ln87_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_38_ap_vld = 1'b1; + end else begin + accum_in_38_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln87_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln87_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln87_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln87_fu_79_p1; + +assign add_ln87_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln87_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln87_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf12_accum_3_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_accum_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_40, + accum_in_40_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_40; +output accum_in_40_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_40; +reg accum_in_40_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln87_fu_73_p2; +reg [3:0] add_ln87_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln87_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln87_fu_79_p1; +reg [15:0] accum_in_40_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_40_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1910( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_40_preg <= 16'd0; + end else begin + if (((icmp_ln87_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_40_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln87_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln87_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln87_reg_90 <= add_ln87_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln87_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_40 = sum_01_reg_55; + end else begin + accum_in_40 = accum_in_40_preg; + end +end + +always @ (*) begin + if (((icmp_ln87_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_40_ap_vld = 1'b1; + end else begin + accum_in_40_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln87_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln87_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln87_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln87_fu_79_p1; + +assign add_ln87_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln87_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln87_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf12_accum_3 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf12_adjustments_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 48; +parameter AWIDTH = 10; +parameter MEM_SIZE = 1000; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf12_adjustments( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd48; +parameter AddressRange = 32'd1000; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf12_adjustments_ram td_fused_top_tdf12_adjustments_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_0_read, + sums_1_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + ap_return_0, + ap_return_1 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state25 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_0_read; +input [15:0] sums_1_read; +output [9:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [8:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [15:0] ap_return_0; +output [15:0] ap_return_1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg indices_23_read; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [1:0] o_reg_111; +reg [15:0] outputs_0_05_reg_122; +reg [15:0] outputs_1_04_reg_134; +reg [8:0] indices_23_read_reg_281; +wire [1:0] add_ln213_fu_158_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_state13_pp0_stage0_iter11; +wire ap_block_state14_pp0_stage0_iter12; +wire ap_block_state15_pp0_stage0_iter13; +wire ap_block_state16_pp0_stage0_iter14; +wire ap_block_state17_pp0_stage0_iter15; +wire ap_block_state18_pp0_stage0_iter16; +wire ap_block_state19_pp0_stage0_iter17; +wire ap_block_state20_pp0_stage0_iter18; +wire ap_block_state21_pp0_stage0_iter19; +wire ap_block_state22_pp0_stage0_iter20; +wire ap_block_state23_pp0_stage0_iter21; +wire ap_block_state24_pp0_stage0_iter22; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln213_fu_164_p2; +reg [0:0] icmp_ln213_reg_291; +reg [0:0] icmp_ln213_reg_291_pp0_iter1_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter2_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter3_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter4_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter5_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter6_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter7_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter8_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter9_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter10_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter11_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter12_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter13_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter14_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter15_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter16_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter17_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter18_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter19_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter20_reg; +reg [0:0] icmp_ln213_reg_291_pp0_iter21_reg; +wire [0:0] trunc_ln219_fu_170_p1; +reg [0:0] trunc_ln219_reg_295; +reg [0:0] trunc_ln219_reg_295_pp0_iter1_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter2_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter3_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter4_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter5_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter6_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter7_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter8_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter9_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter10_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter11_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter12_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter13_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter14_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter15_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter16_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter17_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter18_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter19_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter20_reg; +reg [0:0] trunc_ln219_reg_295_pp0_iter21_reg; +wire [15:0] trunc_ln220_fu_186_p1; +reg [15:0] trunc_ln220_reg_307; +reg [15:0] tmp_270_i_i_reg_312; +reg [15:0] tmp_270_i_i_reg_312_pp0_iter2_reg; +reg [15:0] tmp_270_i_i_reg_312_pp0_iter3_reg; +reg [15:0] tmp_270_i_i_reg_312_pp0_iter4_reg; +reg [15:0] tmp_270_i_i_reg_312_pp0_iter5_reg; +reg [15:0] tmp_270_i_i_reg_312_pp0_iter6_reg; +reg [15:0] tmp_270_i_i_reg_312_pp0_iter7_reg; +reg [15:0] tmp_270_i_i_reg_312_pp0_iter8_reg; +reg [15:0] tmp_271_i_i_reg_317; +reg [15:0] tmp_271_i_i_reg_317_pp0_iter2_reg; +reg [15:0] tmp_271_i_i_reg_317_pp0_iter3_reg; +reg [15:0] tmp_271_i_i_reg_317_pp0_iter4_reg; +reg [15:0] tmp_271_i_i_reg_317_pp0_iter5_reg; +reg [15:0] tmp_271_i_i_reg_317_pp0_iter6_reg; +reg [15:0] tmp_271_i_i_reg_317_pp0_iter7_reg; +reg [15:0] tmp_271_i_i_reg_317_pp0_iter8_reg; +reg [15:0] tmp_271_i_i_reg_317_pp0_iter9_reg; +reg [15:0] tmp_271_i_i_reg_317_pp0_iter10_reg; +reg [15:0] tmp_271_i_i_reg_317_pp0_iter11_reg; +reg [15:0] tmp_271_i_i_reg_317_pp0_iter12_reg; +reg [15:0] tmp_271_i_i_reg_317_pp0_iter13_reg; +wire [15:0] select_ln219_fu_210_p3; +reg [15:0] select_ln219_reg_322; +wire [15:0] grp_fu_150_p2; +reg [15:0] sub_i_i_i_reg_332; +wire [15:0] grp_fu_154_p2; +reg [15:0] normalized_reg_342; +wire [15:0] grp_fu_146_p2; +reg [15:0] biased_reg_352; +wire [15:0] select_ln223_fu_245_p3; +reg ap_enable_reg_pp0_iter22; +wire [15:0] select_ln223_25_fu_252_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_condition_pp0_exit_iter21_state23; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln220_fu_181_p1; +wire [15:0] grp_fu_146_p1; +wire [15:0] grp_fu_150_p1; +wire [15:0] grp_fu_154_p1; +wire [9:0] ochan_fu_174_p3; +wire [15:0] data_V_fu_227_p1; +wire [0:0] p_Result_s_fu_230_p3; +wire [15:0] activated_fu_238_p3; +wire ap_CS_fsm_state25; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1918( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(normalized_reg_342), + .din1(grp_fu_146_p1), + .dout(grp_fu_146_p2) +); + +td_fused_top_hsub_16ns_16ns_16_7_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 7 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_7_full_dsp_1_U1919( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(select_ln219_reg_322), + .din1(grp_fu_150_p1), + .dout(grp_fu_150_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1920( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_332), + .din1(grp_fu_154_p1), + .dout(grp_fu_154_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter20 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter21_state23)) | (~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter21_state23))) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter20; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_fu_164_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + o_reg_111 <= add_ln213_fu_158_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + o_reg_111 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln213_reg_291_pp0_iter20_reg == 1'd0))) begin + biased_reg_352 <= grp_fu_146_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln213_reg_291 <= icmp_ln213_fu_164_p2; + icmp_ln213_reg_291_pp0_iter1_reg <= icmp_ln213_reg_291; + trunc_ln219_reg_295_pp0_iter1_reg <= trunc_ln219_reg_295; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln213_reg_291_pp0_iter10_reg <= icmp_ln213_reg_291_pp0_iter9_reg; + icmp_ln213_reg_291_pp0_iter11_reg <= icmp_ln213_reg_291_pp0_iter10_reg; + icmp_ln213_reg_291_pp0_iter12_reg <= icmp_ln213_reg_291_pp0_iter11_reg; + icmp_ln213_reg_291_pp0_iter13_reg <= icmp_ln213_reg_291_pp0_iter12_reg; + icmp_ln213_reg_291_pp0_iter14_reg <= icmp_ln213_reg_291_pp0_iter13_reg; + icmp_ln213_reg_291_pp0_iter15_reg <= icmp_ln213_reg_291_pp0_iter14_reg; + icmp_ln213_reg_291_pp0_iter16_reg <= icmp_ln213_reg_291_pp0_iter15_reg; + icmp_ln213_reg_291_pp0_iter17_reg <= icmp_ln213_reg_291_pp0_iter16_reg; + icmp_ln213_reg_291_pp0_iter18_reg <= icmp_ln213_reg_291_pp0_iter17_reg; + icmp_ln213_reg_291_pp0_iter19_reg <= icmp_ln213_reg_291_pp0_iter18_reg; + icmp_ln213_reg_291_pp0_iter20_reg <= icmp_ln213_reg_291_pp0_iter19_reg; + icmp_ln213_reg_291_pp0_iter21_reg <= icmp_ln213_reg_291_pp0_iter20_reg; + icmp_ln213_reg_291_pp0_iter2_reg <= icmp_ln213_reg_291_pp0_iter1_reg; + icmp_ln213_reg_291_pp0_iter3_reg <= icmp_ln213_reg_291_pp0_iter2_reg; + icmp_ln213_reg_291_pp0_iter4_reg <= icmp_ln213_reg_291_pp0_iter3_reg; + icmp_ln213_reg_291_pp0_iter5_reg <= icmp_ln213_reg_291_pp0_iter4_reg; + icmp_ln213_reg_291_pp0_iter6_reg <= icmp_ln213_reg_291_pp0_iter5_reg; + icmp_ln213_reg_291_pp0_iter7_reg <= icmp_ln213_reg_291_pp0_iter6_reg; + icmp_ln213_reg_291_pp0_iter8_reg <= icmp_ln213_reg_291_pp0_iter7_reg; + icmp_ln213_reg_291_pp0_iter9_reg <= icmp_ln213_reg_291_pp0_iter8_reg; + tmp_270_i_i_reg_312_pp0_iter2_reg <= tmp_270_i_i_reg_312; + tmp_270_i_i_reg_312_pp0_iter3_reg <= tmp_270_i_i_reg_312_pp0_iter2_reg; + tmp_270_i_i_reg_312_pp0_iter4_reg <= tmp_270_i_i_reg_312_pp0_iter3_reg; + tmp_270_i_i_reg_312_pp0_iter5_reg <= tmp_270_i_i_reg_312_pp0_iter4_reg; + tmp_270_i_i_reg_312_pp0_iter6_reg <= tmp_270_i_i_reg_312_pp0_iter5_reg; + tmp_270_i_i_reg_312_pp0_iter7_reg <= tmp_270_i_i_reg_312_pp0_iter6_reg; + tmp_270_i_i_reg_312_pp0_iter8_reg <= tmp_270_i_i_reg_312_pp0_iter7_reg; + tmp_271_i_i_reg_317_pp0_iter10_reg <= tmp_271_i_i_reg_317_pp0_iter9_reg; + tmp_271_i_i_reg_317_pp0_iter11_reg <= tmp_271_i_i_reg_317_pp0_iter10_reg; + tmp_271_i_i_reg_317_pp0_iter12_reg <= tmp_271_i_i_reg_317_pp0_iter11_reg; + tmp_271_i_i_reg_317_pp0_iter13_reg <= tmp_271_i_i_reg_317_pp0_iter12_reg; + tmp_271_i_i_reg_317_pp0_iter2_reg <= tmp_271_i_i_reg_317; + tmp_271_i_i_reg_317_pp0_iter3_reg <= tmp_271_i_i_reg_317_pp0_iter2_reg; + tmp_271_i_i_reg_317_pp0_iter4_reg <= tmp_271_i_i_reg_317_pp0_iter3_reg; + tmp_271_i_i_reg_317_pp0_iter5_reg <= tmp_271_i_i_reg_317_pp0_iter4_reg; + tmp_271_i_i_reg_317_pp0_iter6_reg <= tmp_271_i_i_reg_317_pp0_iter5_reg; + tmp_271_i_i_reg_317_pp0_iter7_reg <= tmp_271_i_i_reg_317_pp0_iter6_reg; + tmp_271_i_i_reg_317_pp0_iter8_reg <= tmp_271_i_i_reg_317_pp0_iter7_reg; + tmp_271_i_i_reg_317_pp0_iter9_reg <= tmp_271_i_i_reg_317_pp0_iter8_reg; + trunc_ln219_reg_295_pp0_iter10_reg <= trunc_ln219_reg_295_pp0_iter9_reg; + trunc_ln219_reg_295_pp0_iter11_reg <= trunc_ln219_reg_295_pp0_iter10_reg; + trunc_ln219_reg_295_pp0_iter12_reg <= trunc_ln219_reg_295_pp0_iter11_reg; + trunc_ln219_reg_295_pp0_iter13_reg <= trunc_ln219_reg_295_pp0_iter12_reg; + trunc_ln219_reg_295_pp0_iter14_reg <= trunc_ln219_reg_295_pp0_iter13_reg; + trunc_ln219_reg_295_pp0_iter15_reg <= trunc_ln219_reg_295_pp0_iter14_reg; + trunc_ln219_reg_295_pp0_iter16_reg <= trunc_ln219_reg_295_pp0_iter15_reg; + trunc_ln219_reg_295_pp0_iter17_reg <= trunc_ln219_reg_295_pp0_iter16_reg; + trunc_ln219_reg_295_pp0_iter18_reg <= trunc_ln219_reg_295_pp0_iter17_reg; + trunc_ln219_reg_295_pp0_iter19_reg <= trunc_ln219_reg_295_pp0_iter18_reg; + trunc_ln219_reg_295_pp0_iter20_reg <= trunc_ln219_reg_295_pp0_iter19_reg; + trunc_ln219_reg_295_pp0_iter21_reg <= trunc_ln219_reg_295_pp0_iter20_reg; + trunc_ln219_reg_295_pp0_iter2_reg <= trunc_ln219_reg_295_pp0_iter1_reg; + trunc_ln219_reg_295_pp0_iter3_reg <= trunc_ln219_reg_295_pp0_iter2_reg; + trunc_ln219_reg_295_pp0_iter4_reg <= trunc_ln219_reg_295_pp0_iter3_reg; + trunc_ln219_reg_295_pp0_iter5_reg <= trunc_ln219_reg_295_pp0_iter4_reg; + trunc_ln219_reg_295_pp0_iter6_reg <= trunc_ln219_reg_295_pp0_iter5_reg; + trunc_ln219_reg_295_pp0_iter7_reg <= trunc_ln219_reg_295_pp0_iter6_reg; + trunc_ln219_reg_295_pp0_iter8_reg <= trunc_ln219_reg_295_pp0_iter7_reg; + trunc_ln219_reg_295_pp0_iter9_reg <= trunc_ln219_reg_295_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + indices_23_read_reg_281 <= indices_23_dout; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln213_reg_291_pp0_iter12_reg == 1'd0))) begin + normalized_reg_342 <= grp_fu_154_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter22 == 1'b1) & (icmp_ln213_reg_291_pp0_iter21_reg == 1'd0))) begin + outputs_0_05_reg_122 <= select_ln223_fu_245_p3; + outputs_1_04_reg_134 <= select_ln223_25_fu_252_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_291 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln219_reg_322 <= select_ln219_fu_210_p3; + tmp_270_i_i_reg_312 <= {{adjustments_q0[31:16]}}; + tmp_271_i_i_reg_317 <= {{adjustments_q0[47:32]}}; + trunc_ln220_reg_307 <= trunc_ln220_fu_186_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln213_reg_291_pp0_iter7_reg == 1'd0))) begin + sub_i_i_i_reg_332 <= grp_fu_150_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_fu_164_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln219_reg_295 <= trunc_ln219_fu_170_p1; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0))) begin + ap_condition_pp0_exit_iter21_state23 = 1'b1; + end else begin + ap_condition_pp0_exit_iter21_state23 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln213_fu_164_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state25; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state25 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign activated_fu_238_p3 = ((p_Result_s_fu_230_p3[0:0] == 1'b1) ? 16'd0 : biased_reg_352); + +assign add_ln213_fu_158_p2 = (o_reg_111 + 2'd1); + +assign adjustments_address0 = zext_ln220_fu_181_p1; + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state25 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = outputs_0_05_reg_122; + +assign ap_return_1 = outputs_1_04_reg_134; + +assign data_V_fu_227_p1 = biased_reg_352; + +assign grp_fu_146_p1 = tmp_271_i_i_reg_317_pp0_iter13_reg; + +assign grp_fu_150_p1 = trunc_ln220_reg_307; + +assign grp_fu_154_p1 = tmp_270_i_i_reg_312_pp0_iter8_reg; + +assign icmp_ln213_fu_164_p2 = ((o_reg_111 == 2'd2) ? 1'b1 : 1'b0); + +assign ochan_fu_174_p3 = {{indices_23_read_reg_281}, {trunc_ln219_fu_170_p1}}; + +assign p_Result_s_fu_230_p3 = data_V_fu_227_p1[32'd15]; + +assign select_ln219_fu_210_p3 = ((trunc_ln219_reg_295[0:0] == 1'b1) ? sums_1_read : sums_0_read); + +assign select_ln223_25_fu_252_p3 = ((trunc_ln219_reg_295_pp0_iter21_reg[0:0] == 1'b1) ? activated_fu_238_p3 : outputs_1_04_reg_134); + +assign select_ln223_fu_245_p3 = ((trunc_ln219_reg_295_pp0_iter21_reg[0:0] == 1'b1) ? outputs_0_05_reg_122 : activated_fu_238_p3); + +assign trunc_ln219_fu_170_p1 = o_reg_111[0:0]; + +assign trunc_ln220_fu_186_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_181_p1 = ochan_fu_174_p3; + +endmodule //td_fused_top_tdf12_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_0_0_0_address0, + ifmap_vec_0_0_0_ce0, + ifmap_vec_0_0_0_q0, + ifmap_vec_1_0_0_address0, + ifmap_vec_1_0_0_ce0, + ifmap_vec_1_0_0_q0, + weight_vecs_0_0_0_0_address0, + weight_vecs_0_0_0_0_ce0, + weight_vecs_0_0_0_0_q0, + weight_vecs_0_1_0_0_address0, + weight_vecs_0_1_0_0_ce0, + weight_vecs_0_1_0_0_q0, + weight_vecs_1_0_0_0_address0, + weight_vecs_1_0_0_0_ce0, + weight_vecs_1_0_0_0_q0, + weight_vecs_1_1_0_0_address0, + weight_vecs_1_1_0_0_ce0, + weight_vecs_1_1_0_0_q0, + products_0_0_address0, + products_0_0_ce0, + products_0_0_we0, + products_0_0_d0, + products_0_1_address0, + products_0_1_ce0, + products_0_1_we0, + products_0_1_d0, + products_1_0_address0, + products_1_0_ce0, + products_1_0_we0, + products_1_0_d0, + products_1_1_address0, + products_1_1_ce0, + products_1_1_we0, + products_1_1_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [5:0] ifmap_vec_0_0_0_address0; +output ifmap_vec_0_0_0_ce0; +input [15:0] ifmap_vec_0_0_0_q0; +output [5:0] ifmap_vec_1_0_0_address0; +output ifmap_vec_1_0_0_ce0; +input [15:0] ifmap_vec_1_0_0_q0; +output [5:0] weight_vecs_0_0_0_0_address0; +output weight_vecs_0_0_0_0_ce0; +input [15:0] weight_vecs_0_0_0_0_q0; +output [5:0] weight_vecs_0_1_0_0_address0; +output weight_vecs_0_1_0_0_ce0; +input [15:0] weight_vecs_0_1_0_0_q0; +output [5:0] weight_vecs_1_0_0_0_address0; +output weight_vecs_1_0_0_0_ce0; +input [15:0] weight_vecs_1_0_0_0_q0; +output [5:0] weight_vecs_1_1_0_0_address0; +output weight_vecs_1_1_0_0_ce0; +input [15:0] weight_vecs_1_1_0_0_q0; +output [5:0] products_0_0_address0; +output products_0_0_ce0; +output products_0_0_we0; +output [15:0] products_0_0_d0; +output [5:0] products_0_1_address0; +output products_0_1_ce0; +output products_0_1_we0; +output [15:0] products_0_1_d0; +output [5:0] products_1_0_address0; +output products_1_0_ce0; +output products_1_0_we0; +output [15:0] products_1_0_d0; +output [5:0] products_1_1_address0; +output products_1_1_ce0; +output products_1_1_we0; +output [15:0] products_1_1_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_0_0_0_ce0; +reg ifmap_vec_1_0_0_ce0; +reg weight_vecs_0_0_0_0_ce0; +reg weight_vecs_0_1_0_0_ce0; +reg weight_vecs_1_0_0_0_ce0; +reg weight_vecs_1_1_0_0_ce0; +reg products_0_0_ce0; +reg products_0_0_we0; +reg products_0_1_ce0; +reg products_0_1_we0; +reg products_1_0_ce0; +reg products_1_0_we0; +reg products_1_1_ce0; +reg products_1_1_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] ic_0_0_0_reg_180; +wire [0:0] icmp_ln149_fu_207_p2; +reg [0:0] icmp_ln149_reg_239; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln149_reg_239_pp0_iter1_reg; +reg [0:0] icmp_ln149_reg_239_pp0_iter2_reg; +reg [0:0] icmp_ln149_reg_239_pp0_iter3_reg; +reg [0:0] icmp_ln149_reg_239_pp0_iter4_reg; +reg [0:0] icmp_ln149_reg_239_pp0_iter5_reg; +reg [0:0] icmp_ln149_reg_239_pp0_iter6_reg; +wire [7:0] add_ln149_fu_213_p2; +reg ap_enable_reg_pp0_iter0; +wire [63:0] newIndex78_fu_229_p1; +reg [63:0] newIndex78_reg_248; +reg [63:0] newIndex78_reg_248_pp0_iter1_reg; +reg [63:0] newIndex78_reg_248_pp0_iter2_reg; +reg [63:0] newIndex78_reg_248_pp0_iter3_reg; +reg [63:0] newIndex78_reg_248_pp0_iter4_reg; +reg [63:0] newIndex78_reg_248_pp0_iter5_reg; +reg [63:0] newIndex78_reg_248_pp0_iter6_reg; +reg [15:0] ifmap_vec_0_0_0_load_reg_286; +reg [15:0] weight_vecs_0_0_0_0_load_reg_292; +reg [15:0] weight_vecs_1_0_0_0_load_reg_297; +reg [15:0] ifmap_vec_1_0_0_load_reg_302; +reg [15:0] weight_vecs_0_1_0_0_load_reg_308; +reg [15:0] weight_vecs_1_1_0_0_load_reg_313; +wire [15:0] grp_fu_191_p2; +reg [15:0] mul_reg_318; +wire [15:0] grp_fu_195_p2; +reg [15:0] mul_0_0_0_1_reg_323; +wire [15:0] grp_fu_199_p2; +reg [15:0] mul_0_0_1_reg_328; +wire [15:0] grp_fu_203_p2; +reg [15:0] mul_0_0_1_1_reg_333; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +wire ap_block_pp0_stage0; +wire [5:0] newIndex7_fu_219_p4; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1887( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_0_0_load_reg_286), + .din1(weight_vecs_0_0_0_0_load_reg_292), + .dout(grp_fu_191_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1888( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_0_0_load_reg_286), + .din1(weight_vecs_1_0_0_0_load_reg_297), + .dout(grp_fu_195_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1889( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_0_0_load_reg_302), + .din1(weight_vecs_0_1_0_0_load_reg_308), + .dout(grp_fu_199_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1890( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_0_0_load_reg_302), + .din1(weight_vecs_1_1_0_0_load_reg_313), + .dout(grp_fu_203_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_fu_207_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ic_0_0_0_reg_180 <= add_ln149_fu_213_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_0_0_0_reg_180 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln149_reg_239 <= icmp_ln149_fu_207_p2; + icmp_ln149_reg_239_pp0_iter1_reg <= icmp_ln149_reg_239; + newIndex78_reg_248_pp0_iter1_reg[5 : 0] <= newIndex78_reg_248[5 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln149_reg_239_pp0_iter2_reg <= icmp_ln149_reg_239_pp0_iter1_reg; + icmp_ln149_reg_239_pp0_iter3_reg <= icmp_ln149_reg_239_pp0_iter2_reg; + icmp_ln149_reg_239_pp0_iter4_reg <= icmp_ln149_reg_239_pp0_iter3_reg; + icmp_ln149_reg_239_pp0_iter5_reg <= icmp_ln149_reg_239_pp0_iter4_reg; + icmp_ln149_reg_239_pp0_iter6_reg <= icmp_ln149_reg_239_pp0_iter5_reg; + newIndex78_reg_248_pp0_iter2_reg[5 : 0] <= newIndex78_reg_248_pp0_iter1_reg[5 : 0]; + newIndex78_reg_248_pp0_iter3_reg[5 : 0] <= newIndex78_reg_248_pp0_iter2_reg[5 : 0]; + newIndex78_reg_248_pp0_iter4_reg[5 : 0] <= newIndex78_reg_248_pp0_iter3_reg[5 : 0]; + newIndex78_reg_248_pp0_iter5_reg[5 : 0] <= newIndex78_reg_248_pp0_iter4_reg[5 : 0]; + newIndex78_reg_248_pp0_iter6_reg[5 : 0] <= newIndex78_reg_248_pp0_iter5_reg[5 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_reg_239 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_0_0_load_reg_286 <= ifmap_vec_0_0_0_q0; + ifmap_vec_1_0_0_load_reg_302 <= ifmap_vec_1_0_0_q0; + weight_vecs_0_0_0_0_load_reg_292 <= weight_vecs_0_0_0_0_q0; + weight_vecs_0_1_0_0_load_reg_308 <= weight_vecs_0_1_0_0_q0; + weight_vecs_1_0_0_0_load_reg_297 <= weight_vecs_1_0_0_0_q0; + weight_vecs_1_1_0_0_load_reg_313 <= weight_vecs_1_1_0_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_reg_239_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_0_0_0_1_reg_323 <= grp_fu_195_p2; + mul_0_0_1_1_reg_333 <= grp_fu_203_p2; + mul_0_0_1_reg_328 <= grp_fu_199_p2; + mul_reg_318 <= grp_fu_191_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_fu_207_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + newIndex78_reg_248[5 : 0] <= newIndex78_fu_229_p1[5 : 0]; + end +end + +always @ (*) begin + if ((icmp_ln149_fu_207_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_1_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_1_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_0_ce0 = 1'b1; + end else begin + products_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln149_reg_239_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_0_we0 = 1'b1; + end else begin + products_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_1_ce0 = 1'b1; + end else begin + products_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln149_reg_239_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_1_we0 = 1'b1; + end else begin + products_0_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_0_ce0 = 1'b1; + end else begin + products_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln149_reg_239_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_0_we0 = 1'b1; + end else begin + products_1_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_1_ce0 = 1'b1; + end else begin + products_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln149_reg_239_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_1_we0 = 1'b1; + end else begin + products_1_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_1_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_1_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_0_0_ce0 = 1'b1; + end else begin + weight_vecs_1_1_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln149_fu_207_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((icmp_ln149_fu_207_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln149_fu_213_p2 = (ic_0_0_0_reg_180 + 8'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign icmp_ln149_fu_207_p2 = ((ic_0_0_0_reg_180 == 8'd128) ? 1'b1 : 1'b0); + +assign ifmap_vec_0_0_0_address0 = newIndex78_fu_229_p1; + +assign ifmap_vec_1_0_0_address0 = newIndex78_fu_229_p1; + +assign newIndex78_fu_229_p1 = newIndex7_fu_219_p4; + +assign newIndex7_fu_219_p4 = {{ic_0_0_0_reg_180[6:1]}}; + +assign products_0_0_address0 = newIndex78_reg_248_pp0_iter6_reg; + +assign products_0_0_d0 = mul_reg_318; + +assign products_0_1_address0 = newIndex78_reg_248_pp0_iter6_reg; + +assign products_0_1_d0 = mul_0_0_1_reg_328; + +assign products_1_0_address0 = newIndex78_reg_248_pp0_iter6_reg; + +assign products_1_0_d0 = mul_0_0_0_1_reg_323; + +assign products_1_1_address0 = newIndex78_reg_248_pp0_iter6_reg; + +assign products_1_1_d0 = mul_0_0_1_1_reg_333; + +assign weight_vecs_0_0_0_0_address0 = newIndex78_fu_229_p1; + +assign weight_vecs_0_1_0_0_address0 = newIndex78_fu_229_p1; + +assign weight_vecs_1_0_0_0_address0 = newIndex78_fu_229_p1; + +assign weight_vecs_1_1_0_0_address0 = newIndex78_fu_229_p1; + +always @ (posedge ap_clk) begin + newIndex78_reg_248[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + newIndex78_reg_248_pp0_iter1_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + newIndex78_reg_248_pp0_iter2_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + newIndex78_reg_248_pp0_iter3_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + newIndex78_reg_248_pp0_iter4_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + newIndex78_reg_248_pp0_iter5_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + newIndex78_reg_248_pp0_iter6_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf12_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf12_filters_0_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 32; +parameter AWIDTH = 15; +parameter MEM_SIZE = 32000; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf12_filters_0( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd32; +parameter AddressRange = 32'd32000; +parameter AddressWidth = 32'd15; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf12_filters_0_ram td_fused_top_tdf12_filters_0_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + module td_fused_top_tdf12_filters_1_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 32; +parameter AWIDTH = 15; +parameter MEM_SIZE = 32000; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf12_filters_1_rom.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf12_filters_1( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd32; +parameter AddressRange = 32'd32000; +parameter AddressWidth = 32'd15; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +td_fused_top_tdf12_filters_1_rom td_fused_top_tdf12_filters_1_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + indices_2_out_din, + indices_2_out_full_n, + indices_2_out_write, + indices_2_out1_din, + indices_2_out1_full_n, + indices_2_out1_write +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [8:0] indices_2_out_din; +input indices_2_out_full_n; +output indices_2_out_write; +output [8:0] indices_2_out1_din; +input indices_2_out1_full_n; +output indices_2_out1_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg indices_0_write; +reg indices_1_write; +reg indices_2_out_write; +reg indices_2_out1_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [15:0] i_5; +reg [15:0] j_5; +reg [15:0] k_5; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg indices_2_out_blk_n; +reg indices_2_out1_blk_n; +reg [0:0] ap_phi_mux_j_9_flag_0_i_phi_fu_77_p6; +reg ap_block_state1; +wire [0:0] icmp_ln108_fu_141_p2; +wire [0:0] icmp_ln111_fu_154_p2; +reg [15:0] ap_phi_mux_j_9_new_0_i_phi_fu_91_p6; +wire [15:0] add_ln110_fu_147_p2; +reg [15:0] ap_phi_mux_k_9_new_0_i_phi_fu_104_p6; +wire [15:0] add_ln107_fu_134_p2; +wire [15:0] select_ln114_fu_172_p3; +wire [8:0] trunc_ln106_fu_128_p1; +wire [15:0] add_ln113_fu_160_p2; +wire [0:0] icmp_ln114_fu_166_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_5 = 16'd0; +#0 j_5 = 16'd0; +#0 k_5 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln111_fu_154_p2 == 1'd1) & (icmp_ln108_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_5 <= select_ln114_fu_172_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_9_flag_0_i_phi_fu_77_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j_5 <= ap_phi_mux_j_9_new_0_i_phi_fu_91_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k_5 <= ap_phi_mux_k_9_new_0_i_phi_fu_104_p6; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln108_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_9_flag_0_i_phi_fu_77_p6 = 1'd0; + end else if ((((icmp_ln111_fu_154_p2 == 1'd0) & (icmp_ln108_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln111_fu_154_p2 == 1'd1) & (icmp_ln108_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_9_flag_0_i_phi_fu_77_p6 = 1'd1; + end else begin + ap_phi_mux_j_9_flag_0_i_phi_fu_77_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln108_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln111_fu_154_p2 == 1'd0)) begin + ap_phi_mux_j_9_new_0_i_phi_fu_91_p6 = add_ln110_fu_147_p2; + end else if ((icmp_ln111_fu_154_p2 == 1'd1)) begin + ap_phi_mux_j_9_new_0_i_phi_fu_91_p6 = 16'd0; + end else begin + ap_phi_mux_j_9_new_0_i_phi_fu_91_p6 = 'bx; + end + end else begin + ap_phi_mux_j_9_new_0_i_phi_fu_91_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln108_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_9_new_0_i_phi_fu_104_p6 = add_ln107_fu_134_p2; + end else if ((((icmp_ln111_fu_154_p2 == 1'd0) & (icmp_ln108_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln111_fu_154_p2 == 1'd1) & (icmp_ln108_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_9_new_0_i_phi_fu_104_p6 = 16'd0; + end else begin + ap_phi_mux_k_9_new_0_i_phi_fu_104_p6 = 'bx; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_blk_n = indices_2_out1_full_n; + end else begin + indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_write = 1'b1; + end else begin + indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_blk_n = indices_2_out_full_n; + end else begin + indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_write = 1'b1; + end else begin + indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln107_fu_134_p2 = (k_5 + 16'd1); + +assign add_ln110_fu_147_p2 = (j_5 + 16'd1); + +assign add_ln113_fu_160_p2 = (i_5 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign icmp_ln108_fu_141_p2 = ((add_ln107_fu_134_p2 == 16'd500) ? 1'b1 : 1'b0); + +assign icmp_ln111_fu_154_p2 = ((add_ln110_fu_147_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign icmp_ln114_fu_166_p2 = ((add_ln113_fu_160_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign indices_0_din = i_5; + +assign indices_1_din = j_5; + +assign indices_2_out1_din = trunc_ln106_fu_128_p1; + +assign indices_2_out_din = trunc_ln106_fu_128_p1; + +assign select_ln114_fu_172_p3 = ((icmp_ln114_fu_166_p2[0:0] == 1'b1) ? 16'd0 : add_ln113_fu_160_p2); + +assign start_out = real_start; + +assign trunc_ln106_fu_128_p1 = k_5[8:0]; + +endmodule //td_fused_top_tdf12_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_readFilters82 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_0_address0, + filter_data_0_ce0, + filter_data_0_q0, + filter_data_1_address0, + filter_data_1_ce0, + filter_data_1_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + weight_vecs_0_0_0_0_address0, + weight_vecs_0_0_0_0_ce0, + weight_vecs_0_0_0_0_we0, + weight_vecs_0_0_0_0_d0, + weight_vecs_0_1_0_0_address0, + weight_vecs_0_1_0_0_ce0, + weight_vecs_0_1_0_0_we0, + weight_vecs_0_1_0_0_d0, + weight_vecs_1_0_0_0_address0, + weight_vecs_1_0_0_0_ce0, + weight_vecs_1_0_0_0_we0, + weight_vecs_1_0_0_0_d0, + weight_vecs_1_1_0_0_address0, + weight_vecs_1_1_0_0_ce0, + weight_vecs_1_1_0_0_we0, + weight_vecs_1_1_0_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state4 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [14:0] filter_data_0_address0; +output filter_data_0_ce0; +input [31:0] filter_data_0_q0; +output [14:0] filter_data_1_address0; +output filter_data_1_ce0; +input [31:0] filter_data_1_q0; +input [8:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [5:0] weight_vecs_0_0_0_0_address0; +output weight_vecs_0_0_0_0_ce0; +output weight_vecs_0_0_0_0_we0; +output [15:0] weight_vecs_0_0_0_0_d0; +output [5:0] weight_vecs_0_1_0_0_address0; +output weight_vecs_0_1_0_0_ce0; +output weight_vecs_0_1_0_0_we0; +output [15:0] weight_vecs_0_1_0_0_d0; +output [5:0] weight_vecs_1_0_0_0_address0; +output weight_vecs_1_0_0_0_ce0; +output weight_vecs_1_0_0_0_we0; +output [15:0] weight_vecs_1_0_0_0_d0; +output [5:0] weight_vecs_1_1_0_0_address0; +output weight_vecs_1_1_0_0_ce0; +output weight_vecs_1_1_0_0_we0; +output [15:0] weight_vecs_1_1_0_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_0_ce0; +reg filter_data_1_ce0; +reg indices_23_read; +reg weight_vecs_0_0_0_0_ce0; +reg weight_vecs_0_0_0_0_we0; +reg weight_vecs_0_1_0_0_ce0; +reg weight_vecs_0_1_0_0_we0; +reg weight_vecs_1_0_0_0_ce0; +reg weight_vecs_1_0_0_0_we0; +reg weight_vecs_1_1_0_0_ce0; +reg weight_vecs_1_1_0_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [7:0] kk_0_0_0_i_i_reg_160; +reg [8:0] indices_23_read_reg_261; +wire [0:0] icmp_ln49_fu_171_p2; +reg [0:0] icmp_ln49_reg_266; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +wire [7:0] add_ln49_fu_177_p2; +reg ap_enable_reg_pp0_iter0; +wire [5:0] lshr_ln_fu_183_p4; +reg [5:0] lshr_ln_reg_275; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +wire [63:0] zext_ln55_fu_200_p1; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln55_7_fu_206_p1; +wire [14:0] tmp_s_fu_193_p3; +wire [15:0] trunc_ln55_fu_213_p1; +wire [15:0] trunc_ln55_19_fu_222_p1; +wire [15:0] tmp_268_i_i_fu_231_p4; +wire [15:0] tmp_269_i_i_fu_246_p4; +wire ap_CS_fsm_state4; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state4)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln49_fu_171_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_0_0_0_i_i_reg_160 <= add_ln49_fu_177_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_0_0_0_i_i_reg_160 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln49_reg_266 <= icmp_ln49_fu_171_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + indices_23_read_reg_261 <= indices_23_dout; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln49_fu_171_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + lshr_ln_reg_275 <= {{kk_0_0_0_i_i_reg_160[6:1]}}; + end +end + +always @ (*) begin + if ((icmp_ln49_fu_171_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + filter_data_0_ce0 = 1'b1; + end else begin + filter_data_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + filter_data_1_ce0 = 1'b1; + end else begin + filter_data_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln49_reg_266 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_0_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_0_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_1_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_1_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln49_reg_266 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_1_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_1_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_1_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_1_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln49_reg_266 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_1_0_0_0_we0 = 1'b1; + end else begin + weight_vecs_1_0_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_1_1_0_0_ce0 = 1'b1; + end else begin + weight_vecs_1_1_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln49_reg_266 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_1_1_0_0_we0 = 1'b1; + end else begin + weight_vecs_1_1_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln49_fu_171_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln49_fu_171_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln49_fu_177_p2 = (kk_0_0_0_i_i_reg_160 + 8'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_0_address0 = zext_ln55_fu_200_p1; + +assign filter_data_1_address0 = zext_ln55_fu_200_p1; + +assign icmp_ln49_fu_171_p2 = ((kk_0_0_0_i_i_reg_160 == 8'd128) ? 1'b1 : 1'b0); + +assign lshr_ln_fu_183_p4 = {{kk_0_0_0_i_i_reg_160[6:1]}}; + +assign tmp_268_i_i_fu_231_p4 = {{filter_data_0_q0[31:16]}}; + +assign tmp_269_i_i_fu_246_p4 = {{filter_data_1_q0[31:16]}}; + +assign tmp_s_fu_193_p3 = {{indices_23_read_reg_261}, {lshr_ln_fu_183_p4}}; + +assign trunc_ln55_19_fu_222_p1 = filter_data_1_q0[15:0]; + +assign trunc_ln55_fu_213_p1 = filter_data_0_q0[15:0]; + +assign weight_vecs_0_0_0_0_address0 = zext_ln55_7_fu_206_p1; + +assign weight_vecs_0_0_0_0_d0 = trunc_ln55_fu_213_p1; + +assign weight_vecs_0_1_0_0_address0 = zext_ln55_7_fu_206_p1; + +assign weight_vecs_0_1_0_0_d0 = tmp_268_i_i_fu_231_p4; + +assign weight_vecs_1_0_0_0_address0 = zext_ln55_7_fu_206_p1; + +assign weight_vecs_1_0_0_0_d0 = trunc_ln55_19_fu_222_p1; + +assign weight_vecs_1_1_0_0_address0 = zext_ln55_7_fu_206_p1; + +assign weight_vecs_1_1_0_0_d0 = tmp_269_i_i_fu_246_p4; + +assign zext_ln55_7_fu_206_p1 = lshr_ln_reg_275; + +assign zext_ln55_fu_200_p1 = tmp_s_fu_193_p3; + +endmodule //td_fused_top_tdf12_readFilters82 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_readInputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_0_0_0_address0, + ifmap_vec_0_0_0_ce0, + ifmap_vec_0_0_0_we0, + ifmap_vec_0_0_0_d0, + ifmap_vec_1_0_0_address0, + ifmap_vec_1_0_0_ce0, + ifmap_vec_1_0_0_we0, + ifmap_vec_1_0_0_d0, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_pp0_stage0 = 4'd4; +parameter ap_ST_fsm_state6 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [12:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [5:0] ifmap_vec_0_0_0_address0; +output ifmap_vec_0_0_0_ce0; +output ifmap_vec_0_0_0_we0; +output [15:0] ifmap_vec_0_0_0_d0; +output [5:0] ifmap_vec_1_0_0_address0; +output ifmap_vec_1_0_0_ce0; +output ifmap_vec_1_0_0_we0; +output [15:0] ifmap_vec_1_0_0_d0; +output [3:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [7:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg ifmap_vec_0_0_0_ce0; +reg ifmap_vec_0_0_0_we0; +reg ifmap_vec_1_0_0_ce0; +reg ifmap_vec_1_0_0_we0; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [7:0] kk_0_i_i_reg_165; +wire [3:0] trunc_ln165_fu_176_p1; +reg [3:0] trunc_ln165_reg_566; +reg [15:0] col_coord_reg_571; +wire [0:0] is_padding_fu_198_p2; +reg [0:0] is_padding_reg_576; +wire [9:0] add_ln32_fu_258_p2; +reg [9:0] add_ln32_reg_584; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln25_fu_264_p2; +reg [0:0] icmp_ln25_reg_589; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state4_pp0_stage0_iter1; +wire ap_block_state5_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln25_reg_589_pp0_iter1_reg; +wire [7:0] add_ln25_fu_270_p2; +reg ap_enable_reg_pp0_iter0; +wire [1:0] empty_144_fu_298_p1; +reg [1:0] empty_144_reg_603; +reg [5:0] lshr_ln5_reg_608; +reg [5:0] lshr_ln5_reg_608_pp0_iter1_reg; +wire [6:0] sub_ln32_24_fu_391_p2; +reg [6:0] sub_ln32_24_reg_613; +wire [63:0] lshr_ln32_fu_401_p2; +reg [63:0] lshr_ln32_reg_618; +wire [6:0] sub_ln32_27_fu_485_p2; +reg [6:0] sub_ln32_27_reg_623; +wire [63:0] lshr_ln32_12_fu_495_p2; +reg [63:0] lshr_ln32_12_reg_628; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state3; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +wire [63:0] sext_ln32_fu_293_p1; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln33_fu_531_p1; +reg ap_block_state1; +wire [0:0] cmp7_i_i_fu_186_p2; +wire [0:0] icmp_ln24_fu_192_p2; +wire [3:0] empty_142_fu_204_p1; +wire [3:0] row_coord_int_fu_207_p3; +wire [7:0] tmp_fu_220_p3; +wire [4:0] tmp_s_fu_232_p3; +wire [8:0] zext_ln32_fu_228_p1; +wire [8:0] zext_ln32_53_fu_240_p1; +wire [8:0] sub_ln32_fu_244_p2; +wire [3:0] col_coord_int_fu_213_p3; +wire [9:0] sub_ln32_cast_fu_250_p1; +wire [9:0] zext_ln32_54_fu_254_p1; +wire [4:0] lshr_ln_fu_276_p4; +wire [14:0] tmp_78_fu_286_p3; +wire [5:0] tmp_54_fu_312_p3; +wire [5:0] empty_145_fu_319_p2; +wire [6:0] zext_ln32_55_fu_331_p1; +wire [6:0] zext_ln32_56_fu_335_p1; +wire [0:0] icmp_ln32_fu_325_p2; +wire [6:0] sub_ln32_22_fu_349_p2; +wire [6:0] sub_ln32_23_fu_361_p2; +reg [63:0] tmp_79_fu_339_p4; +wire [6:0] xor_ln32_fu_355_p2; +wire [6:0] select_ln32_fu_367_p3; +wire [6:0] select_ln32_19_fu_383_p3; +wire [63:0] select_ln32_18_fu_375_p3; +wire [63:0] zext_ln32_57_fu_397_p1; +wire [5:0] empty_146_fu_407_p2; +wire [5:0] empty_147_fu_413_p2; +wire [6:0] zext_ln32_59_fu_425_p1; +wire [6:0] zext_ln32_60_fu_429_p1; +wire [0:0] icmp_ln32_4_fu_419_p2; +wire [6:0] sub_ln32_25_fu_443_p2; +wire [6:0] sub_ln32_26_fu_455_p2; +reg [63:0] tmp_80_fu_433_p4; +wire [6:0] xor_ln32_4_fu_449_p2; +wire [6:0] select_ln32_20_fu_461_p3; +wire [6:0] select_ln32_22_fu_477_p3; +wire [63:0] select_ln32_21_fu_469_p3; +wire [63:0] zext_ln32_61_fu_491_p1; +wire [63:0] zext_ln32_58_fu_501_p1; +wire [63:0] lshr_ln32_11_fu_504_p2; +wire [63:0] and_ln32_fu_510_p2; +wire [15:0] trunc_ln32_fu_515_p1; +wire [15:0] bitcast_ln32_fu_519_p1; +wire [63:0] zext_ln32_62_fu_536_p1; +wire [63:0] lshr_ln32_13_fu_539_p2; +wire [63:0] and_ln32_4_fu_545_p2; +wire [15:0] trunc_ln32_7_fu_550_p1; +wire [15:0] bitcast_ln32_10_fu_554_p1; +wire ap_CS_fsm_state6; +reg [3:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state3)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state3); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln25_fu_264_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + kk_0_i_i_reg_165 <= add_ln25_fu_270_p2; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + kk_0_i_i_reg_165 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln32_reg_584 <= add_ln32_fu_258_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + col_coord_reg_571 <= indices_12_dout; + is_padding_reg_576 <= is_padding_fu_198_p2; + trunc_ln165_reg_566 <= trunc_ln165_fu_176_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln25_fu_264_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + empty_144_reg_603 <= empty_144_fu_298_p1; + lshr_ln5_reg_608 <= {{kk_0_i_i_reg_165[6:1]}}; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln25_reg_589 <= icmp_ln25_fu_264_p2; + icmp_ln25_reg_589_pp0_iter1_reg <= icmp_ln25_reg_589; + lshr_ln5_reg_608_pp0_iter1_reg <= lshr_ln5_reg_608; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln25_reg_589 == 1'd0) & (is_padding_reg_576 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + lshr_ln32_12_reg_628 <= lshr_ln32_12_fu_495_p2; + lshr_ln32_reg_618 <= lshr_ln32_fu_401_p2; + sub_ln32_24_reg_613[6 : 1] <= sub_ln32_24_fu_391_p2[6 : 1]; + sub_ln32_27_reg_623[6 : 1] <= sub_ln32_27_fu_485_p2[6 : 1]; + end +end + +always @ (*) begin + if ((icmp_ln25_fu_264_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln25_reg_589_pp0_iter1_reg == 1'd0))) begin + ifmap_vec_0_0_0_we0 = 1'b1; + end else begin + ifmap_vec_0_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_1_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_1_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln25_reg_589_pp0_iter1_reg == 1'd0))) begin + ifmap_vec_1_0_0_we0 = 1'b1; + end else begin + ifmap_vec_1_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln25_fu_264_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln25_fu_264_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln25_fu_270_p2 = (kk_0_i_i_reg_165 + 8'd2); + +assign add_ln32_fu_258_p2 = ((sub_ln32_cast_fu_250_p1) + (zext_ln32_54_fu_254_p1)); + +assign and_ln32_4_fu_545_p2 = (lshr_ln32_13_fu_539_p2 & lshr_ln32_12_reg_628); + +assign and_ln32_fu_510_p2 = (lshr_ln32_reg_618 & lshr_ln32_11_fu_504_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd3]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln32_10_fu_554_p1 = trunc_ln32_7_fu_550_p1; + +assign bitcast_ln32_fu_519_p1 = trunc_ln32_fu_515_p1; + +assign cmp7_i_i_fu_186_p2 = ((indices_01_dout > 16'd13) ? 1'b1 : 1'b0); + +assign col_coord_int_fu_213_p3 = ((is_padding_reg_576[0:0] == 1'b1) ? 4'd0 : empty_142_fu_204_p1); + +assign empty_142_fu_204_p1 = col_coord_reg_571[3:0]; + +assign empty_144_fu_298_p1 = kk_0_i_i_reg_165[1:0]; + +assign empty_145_fu_319_p2 = (tmp_54_fu_312_p3 | 6'd15); + +assign empty_146_fu_407_p2 = (tmp_54_fu_312_p3 | 6'd16); + +assign empty_147_fu_413_p2 = (tmp_54_fu_312_p3 | 6'd31); + +assign icmp_ln24_fu_192_p2 = ((indices_12_dout > 16'd13) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_264_p2 = ((kk_0_i_i_reg_165 == 8'd128) ? 1'b1 : 1'b0); + +assign icmp_ln32_4_fu_419_p2 = ((empty_146_fu_407_p2 > empty_147_fu_413_p2) ? 1'b1 : 1'b0); + +assign icmp_ln32_fu_325_p2 = ((tmp_54_fu_312_p3 > empty_145_fu_319_p2) ? 1'b1 : 1'b0); + +assign ifmap_vec_0_0_0_address0 = zext_ln33_fu_531_p1; + +assign ifmap_vec_0_0_0_d0 = ((is_padding_reg_576[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_fu_519_p1); + +assign ifmap_vec_1_0_0_address0 = zext_ln33_fu_531_p1; + +assign ifmap_vec_1_0_0_d0 = ((is_padding_reg_576[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_10_fu_554_p1); + +assign in_data_address0 = sext_ln32_fu_293_p1; + +assign indices_01_out_din = indices_01_dout[3:0]; + +assign indices_12_out_din = indices_12_dout[7:0]; + +assign is_padding_fu_198_p2 = (icmp_ln24_fu_192_p2 | cmp7_i_i_fu_186_p2); + +assign lshr_ln32_11_fu_504_p2 = 64'd18446744073709551615 >> zext_ln32_58_fu_501_p1; + +assign lshr_ln32_12_fu_495_p2 = select_ln32_21_fu_469_p3 >> zext_ln32_61_fu_491_p1; + +assign lshr_ln32_13_fu_539_p2 = 64'd18446744073709551615 >> zext_ln32_62_fu_536_p1; + +assign lshr_ln32_fu_401_p2 = select_ln32_18_fu_375_p3 >> zext_ln32_57_fu_397_p1; + +assign lshr_ln_fu_276_p4 = {{kk_0_i_i_reg_165[6:2]}}; + +assign row_coord_int_fu_207_p3 = ((is_padding_reg_576[0:0] == 1'b1) ? 4'd0 : trunc_ln165_reg_566); + +assign select_ln32_18_fu_375_p3 = ((icmp_ln32_fu_325_p2[0:0] == 1'b1) ? tmp_79_fu_339_p4 : in_data_q0); + +assign select_ln32_19_fu_383_p3 = ((icmp_ln32_fu_325_p2[0:0] == 1'b1) ? xor_ln32_fu_355_p2 : zext_ln32_55_fu_331_p1); + +assign select_ln32_20_fu_461_p3 = ((icmp_ln32_4_fu_419_p2[0:0] == 1'b1) ? sub_ln32_25_fu_443_p2 : sub_ln32_26_fu_455_p2); + +assign select_ln32_21_fu_469_p3 = ((icmp_ln32_4_fu_419_p2[0:0] == 1'b1) ? tmp_80_fu_433_p4 : in_data_q0); + +assign select_ln32_22_fu_477_p3 = ((icmp_ln32_4_fu_419_p2[0:0] == 1'b1) ? xor_ln32_4_fu_449_p2 : zext_ln32_59_fu_425_p1); + +assign select_ln32_fu_367_p3 = ((icmp_ln32_fu_325_p2[0:0] == 1'b1) ? sub_ln32_22_fu_349_p2 : sub_ln32_23_fu_361_p2); + +assign sext_ln32_fu_293_p1 = (tmp_78_fu_286_p3); + +assign sub_ln32_22_fu_349_p2 = (zext_ln32_55_fu_331_p1 - zext_ln32_56_fu_335_p1); + +assign sub_ln32_23_fu_361_p2 = (zext_ln32_56_fu_335_p1 - zext_ln32_55_fu_331_p1); + +assign sub_ln32_24_fu_391_p2 = (7'd63 - select_ln32_fu_367_p3); + +assign sub_ln32_25_fu_443_p2 = (zext_ln32_59_fu_425_p1 - zext_ln32_60_fu_429_p1); + +assign sub_ln32_26_fu_455_p2 = (zext_ln32_60_fu_429_p1 - zext_ln32_59_fu_425_p1); + +assign sub_ln32_27_fu_485_p2 = (7'd63 - select_ln32_20_fu_461_p3); + +assign sub_ln32_cast_fu_250_p1 = (sub_ln32_fu_244_p2); + +assign sub_ln32_fu_244_p2 = (zext_ln32_fu_228_p1 - zext_ln32_53_fu_240_p1); + +assign tmp_54_fu_312_p3 = {{empty_144_reg_603}, {4'd0}}; + +assign tmp_78_fu_286_p3 = {{add_ln32_reg_584}, {lshr_ln_fu_276_p4}}; + +integer ap_tvar_int_0; + +always @ (in_data_q0) begin + //for (ap_tvar_int_0 = 64 - 1; ap_tvar_int_0 >= 0; ap_tvar_int_0 = ap_tvar_int_0 - 1) begin + for (ap_tvar_int_0 = 0; ap_tvar_int_0 < 64; ap_tvar_int_0 = ap_tvar_int_0 + 1) begin + if (ap_tvar_int_0 > 63 - 0) begin + tmp_79_fu_339_p4[ap_tvar_int_0] = 1'b0; + end else begin + tmp_79_fu_339_p4[ap_tvar_int_0] = in_data_q0[63 - ap_tvar_int_0]; + end + end +end + +integer ap_tvar_int_1; + +always @ (in_data_q0) begin + //for (ap_tvar_int_1 = 64 - 1; ap_tvar_int_1 >= 0; ap_tvar_int_1 = ap_tvar_int_1 - 1) begin + for (ap_tvar_int_1 = 0; ap_tvar_int_1 < 64; ap_tvar_int_1 = ap_tvar_int_1 + 1) begin + if (ap_tvar_int_1 > 63 - 0) begin + tmp_80_fu_433_p4[ap_tvar_int_1] = 1'b0; + end else begin + tmp_80_fu_433_p4[ap_tvar_int_1] = in_data_q0[63 - ap_tvar_int_1]; + end + end +end + +assign tmp_fu_220_p3 = {{row_coord_int_fu_207_p3}, {4'd0}}; + +assign tmp_s_fu_232_p3 = {{row_coord_int_fu_207_p3}, {1'd0}}; + +assign trunc_ln165_fu_176_p1 = indices_01_dout[3:0]; + +assign trunc_ln32_7_fu_550_p1 = and_ln32_4_fu_545_p2[15:0]; + +assign trunc_ln32_fu_515_p1 = and_ln32_fu_510_p2[15:0]; + +assign xor_ln32_4_fu_449_p2 = (zext_ln32_59_fu_425_p1 ^ 7'd63); + +assign xor_ln32_fu_355_p2 = (zext_ln32_55_fu_331_p1 ^ 7'd63); + +assign zext_ln32_53_fu_240_p1 = tmp_s_fu_232_p3; + +assign zext_ln32_54_fu_254_p1 = col_coord_int_fu_213_p3; + +assign zext_ln32_55_fu_331_p1 = tmp_54_fu_312_p3; + +assign zext_ln32_56_fu_335_p1 = empty_145_fu_319_p2; + +assign zext_ln32_57_fu_397_p1 = select_ln32_19_fu_383_p3; + +assign zext_ln32_58_fu_501_p1 = sub_ln32_24_reg_613; + +assign zext_ln32_59_fu_425_p1 = empty_146_fu_407_p2; + +assign zext_ln32_60_fu_429_p1 = empty_147_fu_413_p2; + +assign zext_ln32_61_fu_491_p1 = select_ln32_22_fu_477_p3; + +assign zext_ln32_62_fu_536_p1 = sub_ln32_27_reg_623; + +assign zext_ln32_fu_228_p1 = tmp_fu_220_p3; + +assign zext_ln33_fu_531_p1 = lshr_ln5_reg_608_pp0_iter1_reg; + +always @ (posedge ap_clk) begin + sub_ln32_24_reg_613[0] <= 1'b0; + sub_ln32_27_reg_623[0] <= 1'b0; +end + +endmodule //td_fused_top_tdf12_readInputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_writeOutputs_unaligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + p_read, + p_read1, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 5'd1; +parameter ap_ST_fsm_state2 = 5'd2; +parameter ap_ST_fsm_state3 = 5'd4; +parameter ap_ST_fsm_state4 = 5'd8; +parameter ap_ST_fsm_state5 = 5'd16; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [3:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [7:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [15:0] p_read; +input [15:0] p_read1; +output [15:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg out_data_ce1; +reg out_data_we1; + +reg ap_done_reg; + reg [4:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] outputCount_3; +reg [15:0] outputChanIdx_3; +reg [15:0] outputRow_3_0; +reg [15:0] outputRow_3_1; +reg [15:0] outputRow_3_2; +reg [15:0] outputRow_3_3; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg [3:0] indices_01_read_reg_387; +reg [7:0] indices_12_read_reg_393; +wire [9:0] add_ln94_fu_189_p2; +reg [9:0] add_ln94_reg_398; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire [15:0] mul_ln89_fu_198_p2; +reg [15:0] mul_ln89_reg_413; +wire [1:0] add_ln85_fu_204_p2; +reg [1:0] add_ln85_reg_418; +wire ap_CS_fsm_state4; +wire [0:0] icmp_ln88_fu_263_p2; +reg [0:0] icmp_ln88_reg_429; +wire [0:0] icmp_ln85_fu_210_p2; +reg [1:0] o_reg_131; +wire ap_CS_fsm_state5; +wire [63:0] zext_ln94_12_fu_301_p1; +wire [15:0] select_ln97_fu_359_p3; +wire [15:0] select_ln86_fu_220_p3; +wire [1:0] trunc_ln86_1_fu_226_p1; +reg [15:0] empty_fu_86; +wire [15:0] add_ln87_fu_257_p2; +reg ap_block_state1; +wire [7:0] tmp_fu_154_p3; +wire [4:0] tmp_s_fu_165_p3; +wire [8:0] zext_ln94_fu_161_p1; +wire [8:0] zext_ln94_9_fu_172_p1; +wire [8:0] sub_ln94_fu_176_p2; +wire [9:0] sub_ln94_cast_fu_182_p1; +wire [9:0] zext_ln94_10_fu_186_p1; +wire [8:0] mul_ln89_fu_198_p1; +wire [0:0] trunc_ln86_fu_216_p1; +wire [8:0] trunc_ln94_fu_288_p1; +wire [15:0] zext_ln94_11_fu_292_p1; +wire [15:0] add_ln94_4_fu_296_p2; +wire [15:0] bitcast_ln94_12_fu_330_p1; +wire [15:0] bitcast_ln94_11_fu_322_p1; +wire [15:0] bitcast_ln94_10_fu_314_p1; +wire [15:0] bitcast_ln94_fu_306_p1; +wire [15:0] add_ln96_fu_347_p2; +wire [0:0] icmp_ln97_fu_353_p2; +reg [4:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 5'd1; +#0 outputCount_3 = 16'd0; +#0 outputChanIdx_3 = 16'd0; +#0 outputRow_3_0 = 16'd0; +#0 outputRow_3_1 = 16'd0; +#0 outputRow_3_2 = 16'd0; +#0 outputRow_3_3 = 16'd0; +end + +td_fused_top_mul_10s_9ns_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 10 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 16 )) +mul_10s_9ns_16_1_1_U1925( + .din0(add_ln94_reg_398), + .din1(mul_ln89_fu_198_p1), + .dout(mul_ln89_fu_198_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln85_fu_210_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + empty_fu_86 <= outputCount_3; + end else if (((icmp_ln85_fu_210_p2 == 1'd0) & (icmp_ln88_fu_263_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin + empty_fu_86 <= add_ln87_fu_257_p2; + end else if (((icmp_ln88_reg_429 == 1'd1) & (1'b1 == ap_CS_fsm_state5))) begin + empty_fu_86 <= 16'd0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state5)) begin + o_reg_131 <= add_ln85_reg_418; + end else if ((1'b1 == ap_CS_fsm_state3)) begin + o_reg_131 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + add_ln85_reg_418 <= add_ln85_fu_204_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln94_reg_398 <= add_ln94_fu_189_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_fu_210_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin + icmp_ln88_reg_429 <= icmp_ln88_fu_263_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + indices_01_read_reg_387 <= indices_01_dout; + indices_12_read_reg_393 <= indices_12_dout; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + mul_ln89_reg_413 <= mul_ln89_fu_198_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_reg_429 == 1'd1) & (1'b1 == ap_CS_fsm_state5))) begin + outputChanIdx_3 <= select_ln97_fu_359_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_fu_210_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin + outputCount_3 <= empty_fu_86; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_fu_210_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4) & (trunc_ln86_1_fu_226_p1 == 2'd0))) begin + outputRow_3_0 <= select_ln86_fu_220_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_fu_210_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4) & (trunc_ln86_1_fu_226_p1 == 2'd1))) begin + outputRow_3_1 <= select_ln86_fu_220_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_fu_210_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4) & (trunc_ln86_1_fu_226_p1 == 2'd2))) begin + outputRow_3_2 <= select_ln86_fu_220_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln85_fu_210_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4) & (trunc_ln86_1_fu_226_p1 == 2'd3))) begin + outputRow_3_3 <= select_ln86_fu_220_p3; + end +end + +always @ (*) begin + if (((icmp_ln85_fu_210_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln85_fu_210_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state5)) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_reg_429 == 1'd1) & (1'b1 == ap_CS_fsm_state5))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + if (((icmp_ln85_fu_210_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state5; + end + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln85_fu_204_p2 = (o_reg_131 + 2'd1); + +assign add_ln87_fu_257_p2 = (empty_fu_86 + 16'd1); + +assign add_ln94_4_fu_296_p2 = (mul_ln89_reg_413 + zext_ln94_11_fu_292_p1); + +assign add_ln94_fu_189_p2 = ((sub_ln94_cast_fu_182_p1) + (zext_ln94_10_fu_186_p1)); + +assign add_ln96_fu_347_p2 = (outputChanIdx_3 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; + +always @ (*) begin + ap_block_state1 = ((indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign bitcast_ln94_10_fu_314_p1 = outputRow_3_1; + +assign bitcast_ln94_11_fu_322_p1 = outputRow_3_2; + +assign bitcast_ln94_12_fu_330_p1 = outputRow_3_3; + +assign bitcast_ln94_fu_306_p1 = outputRow_3_0; + +assign icmp_ln85_fu_210_p2 = ((o_reg_131 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln88_fu_263_p2 = ((add_ln87_fu_257_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign icmp_ln97_fu_353_p2 = ((add_ln96_fu_347_p2 == 16'd250) ? 1'b1 : 1'b0); + +assign mul_ln89_fu_198_p1 = 16'd250; + +assign out_data_address1 = zext_ln94_12_fu_301_p1; + +assign out_data_d1 = {{{{bitcast_ln94_12_fu_330_p1}, {bitcast_ln94_11_fu_322_p1}}, {bitcast_ln94_10_fu_314_p1}}, {bitcast_ln94_fu_306_p1}}; + +assign select_ln86_fu_220_p3 = ((trunc_ln86_fu_216_p1[0:0] == 1'b1) ? p_read1 : p_read); + +assign select_ln97_fu_359_p3 = ((icmp_ln97_fu_353_p2[0:0] == 1'b1) ? 16'd0 : add_ln96_fu_347_p2); + +assign sub_ln94_cast_fu_182_p1 = (sub_ln94_fu_176_p2); + +assign sub_ln94_fu_176_p2 = (zext_ln94_fu_161_p1 - zext_ln94_9_fu_172_p1); + +assign tmp_fu_154_p3 = {{indices_01_read_reg_387}, {4'd0}}; + +assign tmp_s_fu_165_p3 = {{indices_01_read_reg_387}, {1'd0}}; + +assign trunc_ln86_1_fu_226_p1 = empty_fu_86[1:0]; + +assign trunc_ln86_fu_216_p1 = o_reg_131[0:0]; + +assign trunc_ln94_fu_288_p1 = outputChanIdx_3[8:0]; + +assign zext_ln94_10_fu_186_p1 = indices_12_read_reg_393; + +assign zext_ln94_11_fu_292_p1 = trunc_ln94_fu_288_p1; + +assign zext_ln94_12_fu_301_p1 = add_ln94_4_fu_296_p2; + +assign zext_ln94_9_fu_172_p1 = tmp_s_fu_165_p3; + +assign zext_ln94_fu_161_p1 = tmp_fu_154_p3; + +endmodule //td_fused_top_tdf12_writeOutputs_unaligned +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state13 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [4:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [4:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [3:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_ce0; +reg accum_in_ce1; +reg accum_out_ce0; +reg accum_out_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [3:0] out_idx_reg_76; +reg [3:0] out_idx_reg_76_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_pp0_stage0_11001; +reg [3:0] out_idx_reg_76_pp0_iter2_reg; +reg [3:0] out_idx_reg_76_pp0_iter3_reg; +reg [3:0] out_idx_reg_76_pp0_iter4_reg; +reg [3:0] out_idx_reg_76_pp0_iter5_reg; +reg [3:0] out_idx_reg_76_pp0_iter6_reg; +reg [3:0] out_idx_reg_76_pp0_iter7_reg; +reg [3:0] out_idx_reg_76_pp0_iter8_reg; +reg [3:0] out_idx_reg_76_pp0_iter9_reg; +wire [3:0] add_ln59_fu_92_p2; +reg [3:0] add_ln59_reg_146; +reg ap_enable_reg_pp0_iter0; +wire [0:0] icmp_ln45_fu_98_p2; +reg [0:0] icmp_ln45_reg_151; +reg [0:0] icmp_ln45_reg_151_pp0_iter1_reg; +reg [0:0] icmp_ln45_reg_151_pp0_iter2_reg; +reg [0:0] icmp_ln45_reg_151_pp0_iter3_reg; +reg [0:0] icmp_ln45_reg_151_pp0_iter4_reg; +reg [0:0] icmp_ln45_reg_151_pp0_iter5_reg; +reg [0:0] icmp_ln45_reg_151_pp0_iter6_reg; +reg [0:0] icmp_ln45_reg_151_pp0_iter7_reg; +reg [0:0] icmp_ln45_reg_151_pp0_iter8_reg; +reg [0:0] icmp_ln45_reg_151_pp0_iter9_reg; +wire [0:0] icmp_ln55_fu_123_p2; +reg [0:0] icmp_ln55_reg_160; +reg [15:0] accum_in_load_011_reg_170; +reg ap_enable_reg_pp0_iter1; +wire [15:0] select_ln55_fu_134_p3; +reg [15:0] select_ln55_reg_175; +wire [15:0] grp_fu_88_p2; +reg [15:0] sum0_reg_180; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg [3:0] ap_phi_mux_out_idx_phi_fu_80_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln55_fu_112_p1; +wire [63:0] zext_ln55_6_fu_129_p1; +wire [63:0] zext_ln45_fu_141_p1; +wire [4:0] i_1_1_fu_104_p3; +wire [4:0] or_ln55_fu_117_p2; +wire ap_CS_fsm_state13; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U45( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(select_ln55_reg_175), + .din1(accum_in_load_011_reg_170), + .dout(grp_fu_88_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_76 <= 4'd0; + end else if (((icmp_ln45_reg_151 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + out_idx_reg_76 <= add_ln59_reg_146; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln45_reg_151 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_load_011_reg_170 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln59_reg_146 <= add_ln59_fu_92_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln45_reg_151 <= icmp_ln45_fu_98_p2; + icmp_ln45_reg_151_pp0_iter1_reg <= icmp_ln45_reg_151; + out_idx_reg_76_pp0_iter1_reg <= out_idx_reg_76; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln45_reg_151_pp0_iter2_reg <= icmp_ln45_reg_151_pp0_iter1_reg; + icmp_ln45_reg_151_pp0_iter3_reg <= icmp_ln45_reg_151_pp0_iter2_reg; + icmp_ln45_reg_151_pp0_iter4_reg <= icmp_ln45_reg_151_pp0_iter3_reg; + icmp_ln45_reg_151_pp0_iter5_reg <= icmp_ln45_reg_151_pp0_iter4_reg; + icmp_ln45_reg_151_pp0_iter6_reg <= icmp_ln45_reg_151_pp0_iter5_reg; + icmp_ln45_reg_151_pp0_iter7_reg <= icmp_ln45_reg_151_pp0_iter6_reg; + icmp_ln45_reg_151_pp0_iter8_reg <= icmp_ln45_reg_151_pp0_iter7_reg; + icmp_ln45_reg_151_pp0_iter9_reg <= icmp_ln45_reg_151_pp0_iter8_reg; + out_idx_reg_76_pp0_iter2_reg <= out_idx_reg_76_pp0_iter1_reg; + out_idx_reg_76_pp0_iter3_reg <= out_idx_reg_76_pp0_iter2_reg; + out_idx_reg_76_pp0_iter4_reg <= out_idx_reg_76_pp0_iter3_reg; + out_idx_reg_76_pp0_iter5_reg <= out_idx_reg_76_pp0_iter4_reg; + out_idx_reg_76_pp0_iter6_reg <= out_idx_reg_76_pp0_iter5_reg; + out_idx_reg_76_pp0_iter7_reg <= out_idx_reg_76_pp0_iter6_reg; + out_idx_reg_76_pp0_iter8_reg <= out_idx_reg_76_pp0_iter7_reg; + out_idx_reg_76_pp0_iter9_reg <= out_idx_reg_76_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln45_fu_98_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln55_reg_160 <= icmp_ln55_fu_123_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln45_reg_151 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln55_reg_175 <= select_ln55_fu_134_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln45_reg_151_pp0_iter8_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sum0_reg_180 <= grp_fu_88_p2; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_reg_151_pp0_iter9_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln45_fu_98_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_reg_151 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_out_idx_phi_fu_80_p4 = add_ln59_reg_146; + end else begin + ap_phi_mux_out_idx_phi_fu_80_p4 = out_idx_reg_76; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln45_fu_98_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_enable_reg_pp0_iter9 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln45_fu_98_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_enable_reg_pp0_iter9 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln55_6_fu_129_p1; + +assign accum_in_address1 = zext_ln55_fu_112_p1; + +assign accum_out_address0 = zext_ln45_fu_141_p1; + +assign accum_out_d0 = sum0_reg_180; + +assign add_ln59_fu_92_p2 = (ap_phi_mux_out_idx_phi_fu_80_p4 + 4'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign i_1_1_fu_104_p3 = {{ap_phi_mux_out_idx_phi_fu_80_p4}, {1'd0}}; + +assign icmp_ln45_fu_98_p2 = ((ap_phi_mux_out_idx_phi_fu_80_p4 == 4'd14) ? 1'b1 : 1'b0); + +assign icmp_ln55_fu_123_p2 = ((or_ln55_fu_117_p2 < 5'd27) ? 1'b1 : 1'b0); + +assign or_ln55_fu_117_p2 = (i_1_1_fu_104_p3 | 5'd1); + +assign select_ln55_fu_134_p3 = ((icmp_ln55_reg_160[0:0] == 1'b1) ? accum_in_q0 : 16'd0); + +assign zext_ln45_fu_141_p1 = out_idx_reg_76_pp0_iter9_reg; + +assign zext_ln55_6_fu_129_p1 = or_ln55_fu_117_p2; + +assign zext_ln55_fu_112_p1 = i_1_1_fu_104_p3; + +endmodule //td_fused_top_tdf1_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state13 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [3:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [3:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_ce0; +reg accum_in_ce1; +reg accum_out_ce0; +reg accum_out_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [2:0] out_idx_reg_72; +reg [2:0] out_idx_reg_72_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_pp0_stage0_11001; +reg [2:0] out_idx_reg_72_pp0_iter2_reg; +reg [2:0] out_idx_reg_72_pp0_iter3_reg; +reg [2:0] out_idx_reg_72_pp0_iter4_reg; +reg [2:0] out_idx_reg_72_pp0_iter5_reg; +reg [2:0] out_idx_reg_72_pp0_iter6_reg; +reg [2:0] out_idx_reg_72_pp0_iter7_reg; +reg [2:0] out_idx_reg_72_pp0_iter8_reg; +reg [2:0] out_idx_reg_72_pp0_iter9_reg; +wire [2:0] add_ln89_fu_88_p2; +reg [2:0] add_ln89_reg_129; +reg ap_enable_reg_pp0_iter0; +wire [0:0] icmp_ln75_fu_94_p2; +reg [0:0] icmp_ln75_reg_134; +reg [0:0] icmp_ln75_reg_134_pp0_iter1_reg; +reg [0:0] icmp_ln75_reg_134_pp0_iter2_reg; +reg [0:0] icmp_ln75_reg_134_pp0_iter3_reg; +reg [0:0] icmp_ln75_reg_134_pp0_iter4_reg; +reg [0:0] icmp_ln75_reg_134_pp0_iter5_reg; +reg [0:0] icmp_ln75_reg_134_pp0_iter6_reg; +reg [0:0] icmp_ln75_reg_134_pp0_iter7_reg; +reg [0:0] icmp_ln75_reg_134_pp0_iter8_reg; +reg [0:0] icmp_ln75_reg_134_pp0_iter9_reg; +reg [15:0] accum_in_load_reg_148; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_load_1_reg_153; +wire [15:0] grp_fu_84_p2; +reg [15:0] sum0_reg_158; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg [2:0] ap_phi_mux_out_idx_phi_fu_76_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln85_fu_108_p1; +wire [63:0] zext_ln85_1_fu_119_p1; +wire [63:0] zext_ln75_fu_124_p1; +wire [3:0] i_1_1_fu_100_p3; +wire [3:0] or_ln85_fu_113_p2; +wire ap_CS_fsm_state13; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U49( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(accum_in_load_1_reg_153), + .din1(accum_in_load_reg_148), + .dout(grp_fu_84_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_72 <= 3'd0; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln75_reg_134 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + out_idx_reg_72 <= add_ln89_reg_129; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln75_reg_134 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_load_1_reg_153 <= accum_in_q0; + accum_in_load_reg_148 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln89_reg_129 <= add_ln89_fu_88_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln75_reg_134 <= icmp_ln75_fu_94_p2; + icmp_ln75_reg_134_pp0_iter1_reg <= icmp_ln75_reg_134; + out_idx_reg_72_pp0_iter1_reg <= out_idx_reg_72; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln75_reg_134_pp0_iter2_reg <= icmp_ln75_reg_134_pp0_iter1_reg; + icmp_ln75_reg_134_pp0_iter3_reg <= icmp_ln75_reg_134_pp0_iter2_reg; + icmp_ln75_reg_134_pp0_iter4_reg <= icmp_ln75_reg_134_pp0_iter3_reg; + icmp_ln75_reg_134_pp0_iter5_reg <= icmp_ln75_reg_134_pp0_iter4_reg; + icmp_ln75_reg_134_pp0_iter6_reg <= icmp_ln75_reg_134_pp0_iter5_reg; + icmp_ln75_reg_134_pp0_iter7_reg <= icmp_ln75_reg_134_pp0_iter6_reg; + icmp_ln75_reg_134_pp0_iter8_reg <= icmp_ln75_reg_134_pp0_iter7_reg; + icmp_ln75_reg_134_pp0_iter9_reg <= icmp_ln75_reg_134_pp0_iter8_reg; + out_idx_reg_72_pp0_iter2_reg <= out_idx_reg_72_pp0_iter1_reg; + out_idx_reg_72_pp0_iter3_reg <= out_idx_reg_72_pp0_iter2_reg; + out_idx_reg_72_pp0_iter4_reg <= out_idx_reg_72_pp0_iter3_reg; + out_idx_reg_72_pp0_iter5_reg <= out_idx_reg_72_pp0_iter4_reg; + out_idx_reg_72_pp0_iter6_reg <= out_idx_reg_72_pp0_iter5_reg; + out_idx_reg_72_pp0_iter7_reg <= out_idx_reg_72_pp0_iter6_reg; + out_idx_reg_72_pp0_iter8_reg <= out_idx_reg_72_pp0_iter7_reg; + out_idx_reg_72_pp0_iter9_reg <= out_idx_reg_72_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln75_reg_134_pp0_iter8_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sum0_reg_158 <= grp_fu_84_p2; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln75_reg_134_pp0_iter9_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln75_fu_94_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln75_reg_134 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_out_idx_phi_fu_76_p4 = add_ln89_reg_129; + end else begin + ap_phi_mux_out_idx_phi_fu_76_p4 = out_idx_reg_72; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln75_fu_94_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_enable_reg_pp0_iter9 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln75_fu_94_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_enable_reg_pp0_iter9 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln85_1_fu_119_p1; + +assign accum_in_address1 = zext_ln85_fu_108_p1; + +assign accum_out_address0 = zext_ln75_fu_124_p1; + +assign accum_out_d0 = sum0_reg_158; + +assign add_ln89_fu_88_p2 = (ap_phi_mux_out_idx_phi_fu_76_p4 + 3'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign i_1_1_fu_100_p3 = {{ap_phi_mux_out_idx_phi_fu_76_p4}, {1'd0}}; + +assign icmp_ln75_fu_94_p2 = ((ap_phi_mux_out_idx_phi_fu_76_p4 == 3'd7) ? 1'b1 : 1'b0); + +assign or_ln85_fu_113_p2 = (i_1_1_fu_100_p3 | 4'd1); + +assign zext_ln75_fu_124_p1 = out_idx_reg_72_pp0_iter9_reg; + +assign zext_ln85_1_fu_119_p1 = or_ln85_fu_113_p2; + +assign zext_ln85_fu_108_p1 = i_1_1_fu_100_p3; + +endmodule //td_fused_top_tdf1_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_accum_3_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state13 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [2:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_ce0; +reg accum_in_ce1; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [0:0] write_flag3_0_reg_71; +reg [0:0] write_flag6_0_reg_82; +reg [0:0] write_flag9_0_reg_93; +reg [0:0] write_flag_0_reg_104; +reg [2:0] out_idx_reg_115; +reg [15:0] accum_out_1_07_reg_126; +reg [15:0] accum_out_0_06_reg_138; +reg [15:0] accum_out_2_05_reg_150; +reg [15:0] accum_out_3_04_reg_162; +wire [2:0] add_ln119_fu_178_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln105_fu_184_p2; +reg [0:0] icmp_ln105_reg_397; +reg [0:0] icmp_ln105_reg_397_pp0_iter1_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter2_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter3_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter4_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter5_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter6_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter7_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter8_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter9_reg; +wire [1:0] trunc_ln106_fu_190_p1; +reg [1:0] trunc_ln106_reg_401; +reg [1:0] trunc_ln106_reg_401_pp0_iter1_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter2_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter3_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter4_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter5_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter6_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter7_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter8_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter9_reg; +wire [0:0] icmp_ln115_fu_211_p2; +reg [0:0] icmp_ln115_reg_413; +wire [0:0] write_flag_1_fu_222_p6; +wire [0:0] write_flag9_1_fu_236_p6; +wire [0:0] write_flag6_1_fu_250_p6; +wire [0:0] write_flag3_1_fu_264_p6; +reg [15:0] accum_in_load_reg_443; +reg ap_enable_reg_pp0_iter1; +wire [15:0] select_ln115_fu_278_p3; +reg [15:0] select_ln115_reg_448; +wire [15:0] grp_fu_174_p2; +reg [15:0] sum0_reg_453; +wire [15:0] accum_out_3_1_fu_315_p3; +reg ap_enable_reg_pp0_iter10; +wire [15:0] accum_out_2_1_fu_323_p3; +wire [15:0] accum_out_0_1_fu_345_p3; +wire [15:0] accum_out_1_1_fu_360_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_condition_pp0_exit_iter9_state11; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln115_fu_200_p1; +wire [63:0] zext_ln115_1_fu_217_p1; +wire [2:0] i_12_fu_194_p2; +wire [2:0] or_ln115_fu_205_p2; +wire [0:0] icmp_ln118_fu_285_p2; +wire [0:0] icmp_ln118_5_fu_297_p2; +wire [15:0] select_ln118_fu_290_p3; +wire [0:0] icmp_ln118_6_fu_310_p2; +wire [15:0] select_ln118_9_fu_302_p3; +wire [15:0] select_ln118_10_fu_330_p3; +wire [15:0] select_ln118_11_fu_337_p3; +wire [15:0] select_ln118_12_fu_353_p3; +wire ap_CS_fsm_state13; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U62( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(select_ln115_reg_448), + .din1(accum_in_load_reg_443), + .dout(grp_fu_174_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U63( + .din0(1'd1), + .din1(write_flag_0_reg_104), + .din2(write_flag_0_reg_104), + .din3(write_flag_0_reg_104), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag_1_fu_222_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U64( + .din0(write_flag9_0_reg_93), + .din1(write_flag9_0_reg_93), + .din2(write_flag9_0_reg_93), + .din3(1'd1), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag9_1_fu_236_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U65( + .din0(write_flag6_0_reg_82), + .din1(write_flag6_0_reg_82), + .din2(1'd1), + .din3(write_flag6_0_reg_82), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag6_1_fu_250_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U66( + .din0(write_flag3_0_reg_71), + .din1(1'd1), + .din2(write_flag3_0_reg_71), + .din3(write_flag3_0_reg_71), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag3_1_fu_264_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter9_state11))) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter8; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter8 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter9_state11)) | (~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + out_idx_reg_115 <= add_ln119_fu_178_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_115 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag3_0_reg_71 <= write_flag3_1_fu_264_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag3_0_reg_71 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag6_0_reg_82 <= write_flag6_1_fu_250_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_82 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag9_0_reg_93 <= write_flag9_1_fu_236_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_93 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag_0_reg_104 <= write_flag_1_fu_222_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_104 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_load_reg_443 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397_pp0_iter9_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_0_06_reg_138 <= accum_out_0_1_fu_345_p3; + accum_out_1_07_reg_126 <= accum_out_1_1_fu_360_p3; + accum_out_2_05_reg_150 <= accum_out_2_1_fu_323_p3; + accum_out_3_04_reg_162 <= accum_out_3_1_fu_315_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln105_reg_397 <= icmp_ln105_fu_184_p2; + icmp_ln105_reg_397_pp0_iter1_reg <= icmp_ln105_reg_397; + trunc_ln106_reg_401_pp0_iter1_reg <= trunc_ln106_reg_401; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln105_reg_397_pp0_iter2_reg <= icmp_ln105_reg_397_pp0_iter1_reg; + icmp_ln105_reg_397_pp0_iter3_reg <= icmp_ln105_reg_397_pp0_iter2_reg; + icmp_ln105_reg_397_pp0_iter4_reg <= icmp_ln105_reg_397_pp0_iter3_reg; + icmp_ln105_reg_397_pp0_iter5_reg <= icmp_ln105_reg_397_pp0_iter4_reg; + icmp_ln105_reg_397_pp0_iter6_reg <= icmp_ln105_reg_397_pp0_iter5_reg; + icmp_ln105_reg_397_pp0_iter7_reg <= icmp_ln105_reg_397_pp0_iter6_reg; + icmp_ln105_reg_397_pp0_iter8_reg <= icmp_ln105_reg_397_pp0_iter7_reg; + icmp_ln105_reg_397_pp0_iter9_reg <= icmp_ln105_reg_397_pp0_iter8_reg; + trunc_ln106_reg_401_pp0_iter2_reg <= trunc_ln106_reg_401_pp0_iter1_reg; + trunc_ln106_reg_401_pp0_iter3_reg <= trunc_ln106_reg_401_pp0_iter2_reg; + trunc_ln106_reg_401_pp0_iter4_reg <= trunc_ln106_reg_401_pp0_iter3_reg; + trunc_ln106_reg_401_pp0_iter5_reg <= trunc_ln106_reg_401_pp0_iter4_reg; + trunc_ln106_reg_401_pp0_iter6_reg <= trunc_ln106_reg_401_pp0_iter5_reg; + trunc_ln106_reg_401_pp0_iter7_reg <= trunc_ln106_reg_401_pp0_iter6_reg; + trunc_ln106_reg_401_pp0_iter8_reg <= trunc_ln106_reg_401_pp0_iter7_reg; + trunc_ln106_reg_401_pp0_iter9_reg <= trunc_ln106_reg_401_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln115_reg_413 <= icmp_ln115_fu_211_p2; + trunc_ln106_reg_401 <= trunc_ln106_fu_190_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln115_reg_448 <= select_ln115_fu_278_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397_pp0_iter8_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sum0_reg_453 <= grp_fu_174_p2; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_condition_pp0_exit_iter9_state11 = 1'b1; + end else begin + ap_condition_pp0_exit_iter9_state11 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln105_fu_184_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln115_1_fu_217_p1; + +assign accum_in_address1 = zext_ln115_fu_200_p1; + +assign accum_out_0_1_fu_345_p3 = ((icmp_ln118_6_fu_310_p2[0:0] == 1'b1) ? accum_out_0_06_reg_138 : select_ln118_11_fu_337_p3); + +assign accum_out_1_1_fu_360_p3 = ((icmp_ln118_6_fu_310_p2[0:0] == 1'b1) ? accum_out_1_07_reg_126 : select_ln118_12_fu_353_p3); + +assign accum_out_2_1_fu_323_p3 = ((icmp_ln118_6_fu_310_p2[0:0] == 1'b1) ? sum0_reg_453 : accum_out_2_05_reg_150); + +assign accum_out_3_1_fu_315_p3 = ((icmp_ln118_6_fu_310_p2[0:0] == 1'b1) ? accum_out_3_04_reg_162 : select_ln118_9_fu_302_p3); + +assign add_ln119_fu_178_p2 = (out_idx_reg_115 + 3'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = accum_out_0_06_reg_138; + +assign ap_return_1 = accum_out_1_07_reg_126; + +assign ap_return_2 = accum_out_2_05_reg_150; + +assign ap_return_3 = accum_out_3_04_reg_162; + +assign i_12_fu_194_p2 = out_idx_reg_115 << 3'd1; + +assign icmp_ln105_fu_184_p2 = ((out_idx_reg_115 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln115_fu_211_p2 = ((or_ln115_fu_205_p2 == 3'd7) ? 1'b1 : 1'b0); + +assign icmp_ln118_5_fu_297_p2 = ((trunc_ln106_reg_401_pp0_iter9_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln118_6_fu_310_p2 = ((trunc_ln106_reg_401_pp0_iter9_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln118_fu_285_p2 = ((trunc_ln106_reg_401_pp0_iter9_reg == 2'd0) ? 1'b1 : 1'b0); + +assign or_ln115_fu_205_p2 = (i_12_fu_194_p2 | 3'd1); + +assign select_ln115_fu_278_p3 = ((icmp_ln115_reg_413[0:0] == 1'b1) ? 16'd0 : accum_in_q0); + +assign select_ln118_10_fu_330_p3 = ((icmp_ln118_fu_285_p2[0:0] == 1'b1) ? sum0_reg_453 : accum_out_0_06_reg_138); + +assign select_ln118_11_fu_337_p3 = ((icmp_ln118_5_fu_297_p2[0:0] == 1'b1) ? accum_out_0_06_reg_138 : select_ln118_10_fu_330_p3); + +assign select_ln118_12_fu_353_p3 = ((icmp_ln118_5_fu_297_p2[0:0] == 1'b1) ? sum0_reg_453 : accum_out_1_07_reg_126); + +assign select_ln118_9_fu_302_p3 = ((icmp_ln118_5_fu_297_p2[0:0] == 1'b1) ? accum_out_3_04_reg_162 : select_ln118_fu_290_p3); + +assign select_ln118_fu_290_p3 = ((icmp_ln118_fu_285_p2[0:0] == 1'b1) ? accum_out_3_04_reg_162 : sum0_reg_453); + +assign trunc_ln106_fu_190_p1 = out_idx_reg_115[1:0]; + +assign zext_ln115_1_fu_217_p1 = or_ln115_fu_205_p2; + +assign zext_ln115_fu_200_p1 = i_12_fu_194_p2; + +endmodule //td_fused_top_tdf1_accum_3_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_accum_3_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state13 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [2:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_ce0; +reg accum_in_ce1; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [0:0] write_flag3_0_reg_71; +reg [0:0] write_flag6_0_reg_82; +reg [0:0] write_flag9_0_reg_93; +reg [0:0] write_flag_0_reg_104; +reg [2:0] out_idx_reg_115; +reg [15:0] accum_out_1_07_reg_126; +reg [15:0] accum_out_0_06_reg_138; +reg [15:0] accum_out_2_05_reg_150; +reg [15:0] accum_out_3_04_reg_162; +wire [2:0] add_ln119_fu_178_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln105_fu_184_p2; +reg [0:0] icmp_ln105_reg_397; +reg [0:0] icmp_ln105_reg_397_pp0_iter1_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter2_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter3_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter4_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter5_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter6_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter7_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter8_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter9_reg; +wire [1:0] trunc_ln106_fu_190_p1; +reg [1:0] trunc_ln106_reg_401; +reg [1:0] trunc_ln106_reg_401_pp0_iter1_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter2_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter3_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter4_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter5_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter6_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter7_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter8_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter9_reg; +wire [0:0] icmp_ln115_fu_211_p2; +reg [0:0] icmp_ln115_reg_413; +wire [0:0] write_flag_1_fu_222_p6; +wire [0:0] write_flag9_1_fu_236_p6; +wire [0:0] write_flag6_1_fu_250_p6; +wire [0:0] write_flag3_1_fu_264_p6; +reg [15:0] accum_in_load_reg_443; +reg ap_enable_reg_pp0_iter1; +wire [15:0] select_ln115_fu_278_p3; +reg [15:0] select_ln115_reg_448; +wire [15:0] grp_fu_174_p2; +reg [15:0] sum0_reg_453; +wire [15:0] accum_out_3_1_fu_315_p3; +reg ap_enable_reg_pp0_iter10; +wire [15:0] accum_out_2_1_fu_323_p3; +wire [15:0] accum_out_0_1_fu_345_p3; +wire [15:0] accum_out_1_1_fu_360_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_condition_pp0_exit_iter9_state11; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln115_fu_200_p1; +wire [63:0] zext_ln115_1_fu_217_p1; +wire [2:0] i_12_fu_194_p2; +wire [2:0] or_ln115_fu_205_p2; +wire [0:0] icmp_ln118_fu_285_p2; +wire [0:0] icmp_ln118_3_fu_297_p2; +wire [15:0] select_ln118_fu_290_p3; +wire [0:0] icmp_ln118_4_fu_310_p2; +wire [15:0] select_ln118_5_fu_302_p3; +wire [15:0] select_ln118_6_fu_330_p3; +wire [15:0] select_ln118_7_fu_337_p3; +wire [15:0] select_ln118_8_fu_353_p3; +wire ap_CS_fsm_state13; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U68( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(select_ln115_reg_448), + .din1(accum_in_load_reg_443), + .dout(grp_fu_174_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U69( + .din0(1'd1), + .din1(write_flag_0_reg_104), + .din2(write_flag_0_reg_104), + .din3(write_flag_0_reg_104), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag_1_fu_222_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U70( + .din0(write_flag9_0_reg_93), + .din1(write_flag9_0_reg_93), + .din2(write_flag9_0_reg_93), + .din3(1'd1), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag9_1_fu_236_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U71( + .din0(write_flag6_0_reg_82), + .din1(write_flag6_0_reg_82), + .din2(1'd1), + .din3(write_flag6_0_reg_82), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag6_1_fu_250_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U72( + .din0(write_flag3_0_reg_71), + .din1(1'd1), + .din2(write_flag3_0_reg_71), + .din3(write_flag3_0_reg_71), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag3_1_fu_264_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter9_state11))) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter8; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter8 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter9_state11)) | (~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + out_idx_reg_115 <= add_ln119_fu_178_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_115 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag3_0_reg_71 <= write_flag3_1_fu_264_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag3_0_reg_71 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag6_0_reg_82 <= write_flag6_1_fu_250_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_82 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag9_0_reg_93 <= write_flag9_1_fu_236_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_93 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag_0_reg_104 <= write_flag_1_fu_222_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_104 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_load_reg_443 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397_pp0_iter9_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_0_06_reg_138 <= accum_out_0_1_fu_345_p3; + accum_out_1_07_reg_126 <= accum_out_1_1_fu_360_p3; + accum_out_2_05_reg_150 <= accum_out_2_1_fu_323_p3; + accum_out_3_04_reg_162 <= accum_out_3_1_fu_315_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln105_reg_397 <= icmp_ln105_fu_184_p2; + icmp_ln105_reg_397_pp0_iter1_reg <= icmp_ln105_reg_397; + trunc_ln106_reg_401_pp0_iter1_reg <= trunc_ln106_reg_401; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln105_reg_397_pp0_iter2_reg <= icmp_ln105_reg_397_pp0_iter1_reg; + icmp_ln105_reg_397_pp0_iter3_reg <= icmp_ln105_reg_397_pp0_iter2_reg; + icmp_ln105_reg_397_pp0_iter4_reg <= icmp_ln105_reg_397_pp0_iter3_reg; + icmp_ln105_reg_397_pp0_iter5_reg <= icmp_ln105_reg_397_pp0_iter4_reg; + icmp_ln105_reg_397_pp0_iter6_reg <= icmp_ln105_reg_397_pp0_iter5_reg; + icmp_ln105_reg_397_pp0_iter7_reg <= icmp_ln105_reg_397_pp0_iter6_reg; + icmp_ln105_reg_397_pp0_iter8_reg <= icmp_ln105_reg_397_pp0_iter7_reg; + icmp_ln105_reg_397_pp0_iter9_reg <= icmp_ln105_reg_397_pp0_iter8_reg; + trunc_ln106_reg_401_pp0_iter2_reg <= trunc_ln106_reg_401_pp0_iter1_reg; + trunc_ln106_reg_401_pp0_iter3_reg <= trunc_ln106_reg_401_pp0_iter2_reg; + trunc_ln106_reg_401_pp0_iter4_reg <= trunc_ln106_reg_401_pp0_iter3_reg; + trunc_ln106_reg_401_pp0_iter5_reg <= trunc_ln106_reg_401_pp0_iter4_reg; + trunc_ln106_reg_401_pp0_iter6_reg <= trunc_ln106_reg_401_pp0_iter5_reg; + trunc_ln106_reg_401_pp0_iter7_reg <= trunc_ln106_reg_401_pp0_iter6_reg; + trunc_ln106_reg_401_pp0_iter8_reg <= trunc_ln106_reg_401_pp0_iter7_reg; + trunc_ln106_reg_401_pp0_iter9_reg <= trunc_ln106_reg_401_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln115_reg_413 <= icmp_ln115_fu_211_p2; + trunc_ln106_reg_401 <= trunc_ln106_fu_190_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln115_reg_448 <= select_ln115_fu_278_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397_pp0_iter8_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sum0_reg_453 <= grp_fu_174_p2; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_condition_pp0_exit_iter9_state11 = 1'b1; + end else begin + ap_condition_pp0_exit_iter9_state11 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln105_fu_184_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln115_1_fu_217_p1; + +assign accum_in_address1 = zext_ln115_fu_200_p1; + +assign accum_out_0_1_fu_345_p3 = ((icmp_ln118_4_fu_310_p2[0:0] == 1'b1) ? accum_out_0_06_reg_138 : select_ln118_7_fu_337_p3); + +assign accum_out_1_1_fu_360_p3 = ((icmp_ln118_4_fu_310_p2[0:0] == 1'b1) ? accum_out_1_07_reg_126 : select_ln118_8_fu_353_p3); + +assign accum_out_2_1_fu_323_p3 = ((icmp_ln118_4_fu_310_p2[0:0] == 1'b1) ? sum0_reg_453 : accum_out_2_05_reg_150); + +assign accum_out_3_1_fu_315_p3 = ((icmp_ln118_4_fu_310_p2[0:0] == 1'b1) ? accum_out_3_04_reg_162 : select_ln118_5_fu_302_p3); + +assign add_ln119_fu_178_p2 = (out_idx_reg_115 + 3'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = accum_out_0_06_reg_138; + +assign ap_return_1 = accum_out_1_07_reg_126; + +assign ap_return_2 = accum_out_2_05_reg_150; + +assign ap_return_3 = accum_out_3_04_reg_162; + +assign i_12_fu_194_p2 = out_idx_reg_115 << 3'd1; + +assign icmp_ln105_fu_184_p2 = ((out_idx_reg_115 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln115_fu_211_p2 = ((or_ln115_fu_205_p2 == 3'd7) ? 1'b1 : 1'b0); + +assign icmp_ln118_3_fu_297_p2 = ((trunc_ln106_reg_401_pp0_iter9_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln118_4_fu_310_p2 = ((trunc_ln106_reg_401_pp0_iter9_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln118_fu_285_p2 = ((trunc_ln106_reg_401_pp0_iter9_reg == 2'd0) ? 1'b1 : 1'b0); + +assign or_ln115_fu_205_p2 = (i_12_fu_194_p2 | 3'd1); + +assign select_ln115_fu_278_p3 = ((icmp_ln115_reg_413[0:0] == 1'b1) ? 16'd0 : accum_in_q0); + +assign select_ln118_5_fu_302_p3 = ((icmp_ln118_3_fu_297_p2[0:0] == 1'b1) ? accum_out_3_04_reg_162 : select_ln118_fu_290_p3); + +assign select_ln118_6_fu_330_p3 = ((icmp_ln118_fu_285_p2[0:0] == 1'b1) ? sum0_reg_453 : accum_out_0_06_reg_138); + +assign select_ln118_7_fu_337_p3 = ((icmp_ln118_3_fu_297_p2[0:0] == 1'b1) ? accum_out_0_06_reg_138 : select_ln118_6_fu_330_p3); + +assign select_ln118_8_fu_353_p3 = ((icmp_ln118_3_fu_297_p2[0:0] == 1'b1) ? sum0_reg_453 : accum_out_1_07_reg_126); + +assign select_ln118_fu_290_p3 = ((icmp_ln118_fu_285_p2[0:0] == 1'b1) ? accum_out_3_04_reg_162 : sum0_reg_453); + +assign trunc_ln106_fu_190_p1 = out_idx_reg_115[1:0]; + +assign zext_ln115_1_fu_217_p1 = or_ln115_fu_205_p2; + +assign zext_ln115_fu_200_p1 = i_12_fu_194_p2; + +endmodule //td_fused_top_tdf1_accum_3_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_accum_3_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state13 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [2:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_ce0; +reg accum_in_ce1; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [0:0] write_flag3_0_reg_71; +reg [0:0] write_flag6_0_reg_82; +reg [0:0] write_flag9_0_reg_93; +reg [0:0] write_flag_0_reg_104; +reg [2:0] out_idx_reg_115; +reg [15:0] accum_out_1_07_reg_126; +reg [15:0] accum_out_0_06_reg_138; +reg [15:0] accum_out_2_05_reg_150; +reg [15:0] accum_out_3_04_reg_162; +wire [2:0] add_ln119_fu_178_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln105_fu_184_p2; +reg [0:0] icmp_ln105_reg_397; +reg [0:0] icmp_ln105_reg_397_pp0_iter1_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter2_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter3_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter4_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter5_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter6_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter7_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter8_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter9_reg; +wire [1:0] trunc_ln106_fu_190_p1; +reg [1:0] trunc_ln106_reg_401; +reg [1:0] trunc_ln106_reg_401_pp0_iter1_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter2_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter3_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter4_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter5_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter6_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter7_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter8_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter9_reg; +wire [0:0] icmp_ln115_fu_211_p2; +reg [0:0] icmp_ln115_reg_413; +wire [0:0] write_flag_1_fu_222_p6; +wire [0:0] write_flag9_1_fu_236_p6; +wire [0:0] write_flag6_1_fu_250_p6; +wire [0:0] write_flag3_1_fu_264_p6; +reg [15:0] accum_in_load_reg_443; +reg ap_enable_reg_pp0_iter1; +wire [15:0] select_ln115_fu_278_p3; +reg [15:0] select_ln115_reg_448; +wire [15:0] grp_fu_174_p2; +reg [15:0] sum0_reg_453; +wire [15:0] accum_out_3_1_fu_315_p3; +reg ap_enable_reg_pp0_iter10; +wire [15:0] accum_out_2_1_fu_323_p3; +wire [15:0] accum_out_0_1_fu_345_p3; +wire [15:0] accum_out_1_1_fu_360_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_condition_pp0_exit_iter9_state11; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln115_fu_200_p1; +wire [63:0] zext_ln115_1_fu_217_p1; +wire [2:0] i_12_fu_194_p2; +wire [2:0] or_ln115_fu_205_p2; +wire [0:0] icmp_ln118_fu_285_p2; +wire [0:0] icmp_ln118_1_fu_297_p2; +wire [15:0] select_ln118_fu_290_p3; +wire [0:0] icmp_ln118_2_fu_310_p2; +wire [15:0] select_ln118_1_fu_302_p3; +wire [15:0] select_ln118_2_fu_330_p3; +wire [15:0] select_ln118_3_fu_337_p3; +wire [15:0] select_ln118_4_fu_353_p3; +wire ap_CS_fsm_state13; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U74( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(select_ln115_reg_448), + .din1(accum_in_load_reg_443), + .dout(grp_fu_174_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U75( + .din0(1'd1), + .din1(write_flag_0_reg_104), + .din2(write_flag_0_reg_104), + .din3(write_flag_0_reg_104), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag_1_fu_222_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U76( + .din0(write_flag9_0_reg_93), + .din1(write_flag9_0_reg_93), + .din2(write_flag9_0_reg_93), + .din3(1'd1), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag9_1_fu_236_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U77( + .din0(write_flag6_0_reg_82), + .din1(write_flag6_0_reg_82), + .din2(1'd1), + .din3(write_flag6_0_reg_82), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag6_1_fu_250_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U78( + .din0(write_flag3_0_reg_71), + .din1(1'd1), + .din2(write_flag3_0_reg_71), + .din3(write_flag3_0_reg_71), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag3_1_fu_264_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter9_state11))) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter8; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter8 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter9_state11)) | (~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + out_idx_reg_115 <= add_ln119_fu_178_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_115 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag3_0_reg_71 <= write_flag3_1_fu_264_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag3_0_reg_71 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag6_0_reg_82 <= write_flag6_1_fu_250_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_82 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag9_0_reg_93 <= write_flag9_1_fu_236_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_93 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag_0_reg_104 <= write_flag_1_fu_222_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_104 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_load_reg_443 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397_pp0_iter9_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_0_06_reg_138 <= accum_out_0_1_fu_345_p3; + accum_out_1_07_reg_126 <= accum_out_1_1_fu_360_p3; + accum_out_2_05_reg_150 <= accum_out_2_1_fu_323_p3; + accum_out_3_04_reg_162 <= accum_out_3_1_fu_315_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln105_reg_397 <= icmp_ln105_fu_184_p2; + icmp_ln105_reg_397_pp0_iter1_reg <= icmp_ln105_reg_397; + trunc_ln106_reg_401_pp0_iter1_reg <= trunc_ln106_reg_401; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln105_reg_397_pp0_iter2_reg <= icmp_ln105_reg_397_pp0_iter1_reg; + icmp_ln105_reg_397_pp0_iter3_reg <= icmp_ln105_reg_397_pp0_iter2_reg; + icmp_ln105_reg_397_pp0_iter4_reg <= icmp_ln105_reg_397_pp0_iter3_reg; + icmp_ln105_reg_397_pp0_iter5_reg <= icmp_ln105_reg_397_pp0_iter4_reg; + icmp_ln105_reg_397_pp0_iter6_reg <= icmp_ln105_reg_397_pp0_iter5_reg; + icmp_ln105_reg_397_pp0_iter7_reg <= icmp_ln105_reg_397_pp0_iter6_reg; + icmp_ln105_reg_397_pp0_iter8_reg <= icmp_ln105_reg_397_pp0_iter7_reg; + icmp_ln105_reg_397_pp0_iter9_reg <= icmp_ln105_reg_397_pp0_iter8_reg; + trunc_ln106_reg_401_pp0_iter2_reg <= trunc_ln106_reg_401_pp0_iter1_reg; + trunc_ln106_reg_401_pp0_iter3_reg <= trunc_ln106_reg_401_pp0_iter2_reg; + trunc_ln106_reg_401_pp0_iter4_reg <= trunc_ln106_reg_401_pp0_iter3_reg; + trunc_ln106_reg_401_pp0_iter5_reg <= trunc_ln106_reg_401_pp0_iter4_reg; + trunc_ln106_reg_401_pp0_iter6_reg <= trunc_ln106_reg_401_pp0_iter5_reg; + trunc_ln106_reg_401_pp0_iter7_reg <= trunc_ln106_reg_401_pp0_iter6_reg; + trunc_ln106_reg_401_pp0_iter8_reg <= trunc_ln106_reg_401_pp0_iter7_reg; + trunc_ln106_reg_401_pp0_iter9_reg <= trunc_ln106_reg_401_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln115_reg_413 <= icmp_ln115_fu_211_p2; + trunc_ln106_reg_401 <= trunc_ln106_fu_190_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln115_reg_448 <= select_ln115_fu_278_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397_pp0_iter8_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sum0_reg_453 <= grp_fu_174_p2; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_condition_pp0_exit_iter9_state11 = 1'b1; + end else begin + ap_condition_pp0_exit_iter9_state11 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln105_fu_184_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln115_1_fu_217_p1; + +assign accum_in_address1 = zext_ln115_fu_200_p1; + +assign accum_out_0_1_fu_345_p3 = ((icmp_ln118_2_fu_310_p2[0:0] == 1'b1) ? accum_out_0_06_reg_138 : select_ln118_3_fu_337_p3); + +assign accum_out_1_1_fu_360_p3 = ((icmp_ln118_2_fu_310_p2[0:0] == 1'b1) ? accum_out_1_07_reg_126 : select_ln118_4_fu_353_p3); + +assign accum_out_2_1_fu_323_p3 = ((icmp_ln118_2_fu_310_p2[0:0] == 1'b1) ? sum0_reg_453 : accum_out_2_05_reg_150); + +assign accum_out_3_1_fu_315_p3 = ((icmp_ln118_2_fu_310_p2[0:0] == 1'b1) ? accum_out_3_04_reg_162 : select_ln118_1_fu_302_p3); + +assign add_ln119_fu_178_p2 = (out_idx_reg_115 + 3'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = accum_out_0_06_reg_138; + +assign ap_return_1 = accum_out_1_07_reg_126; + +assign ap_return_2 = accum_out_2_05_reg_150; + +assign ap_return_3 = accum_out_3_04_reg_162; + +assign i_12_fu_194_p2 = out_idx_reg_115 << 3'd1; + +assign icmp_ln105_fu_184_p2 = ((out_idx_reg_115 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln115_fu_211_p2 = ((or_ln115_fu_205_p2 == 3'd7) ? 1'b1 : 1'b0); + +assign icmp_ln118_1_fu_297_p2 = ((trunc_ln106_reg_401_pp0_iter9_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln118_2_fu_310_p2 = ((trunc_ln106_reg_401_pp0_iter9_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln118_fu_285_p2 = ((trunc_ln106_reg_401_pp0_iter9_reg == 2'd0) ? 1'b1 : 1'b0); + +assign or_ln115_fu_205_p2 = (i_12_fu_194_p2 | 3'd1); + +assign select_ln115_fu_278_p3 = ((icmp_ln115_reg_413[0:0] == 1'b1) ? 16'd0 : accum_in_q0); + +assign select_ln118_1_fu_302_p3 = ((icmp_ln118_1_fu_297_p2[0:0] == 1'b1) ? accum_out_3_04_reg_162 : select_ln118_fu_290_p3); + +assign select_ln118_2_fu_330_p3 = ((icmp_ln118_fu_285_p2[0:0] == 1'b1) ? sum0_reg_453 : accum_out_0_06_reg_138); + +assign select_ln118_3_fu_337_p3 = ((icmp_ln118_1_fu_297_p2[0:0] == 1'b1) ? accum_out_0_06_reg_138 : select_ln118_2_fu_330_p3); + +assign select_ln118_4_fu_353_p3 = ((icmp_ln118_1_fu_297_p2[0:0] == 1'b1) ? sum0_reg_453 : accum_out_1_07_reg_126); + +assign select_ln118_fu_290_p3 = ((icmp_ln118_fu_285_p2[0:0] == 1'b1) ? accum_out_3_04_reg_162 : sum0_reg_453); + +assign trunc_ln106_fu_190_p1 = out_idx_reg_115[1:0]; + +assign zext_ln115_1_fu_217_p1 = or_ln115_fu_205_p2; + +assign zext_ln115_fu_200_p1 = i_12_fu_194_p2; + +endmodule //td_fused_top_tdf1_accum_3_3 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_accum_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state13 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [2:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_ce0; +reg accum_in_ce1; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [0:0] write_flag3_0_reg_71; +reg [0:0] write_flag6_0_reg_82; +reg [0:0] write_flag9_0_reg_93; +reg [0:0] write_flag_0_reg_104; +reg [2:0] out_idx_reg_115; +reg [15:0] accum_out_1_07_reg_126; +reg [15:0] accum_out_0_06_reg_138; +reg [15:0] accum_out_2_05_reg_150; +reg [15:0] accum_out_3_04_reg_162; +wire [2:0] add_ln119_fu_178_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln105_fu_184_p2; +reg [0:0] icmp_ln105_reg_397; +reg [0:0] icmp_ln105_reg_397_pp0_iter1_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter2_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter3_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter4_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter5_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter6_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter7_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter8_reg; +reg [0:0] icmp_ln105_reg_397_pp0_iter9_reg; +wire [1:0] trunc_ln106_fu_190_p1; +reg [1:0] trunc_ln106_reg_401; +reg [1:0] trunc_ln106_reg_401_pp0_iter1_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter2_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter3_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter4_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter5_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter6_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter7_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter8_reg; +reg [1:0] trunc_ln106_reg_401_pp0_iter9_reg; +wire [0:0] icmp_ln115_fu_211_p2; +reg [0:0] icmp_ln115_reg_413; +wire [0:0] write_flag_1_fu_222_p6; +wire [0:0] write_flag9_1_fu_236_p6; +wire [0:0] write_flag6_1_fu_250_p6; +wire [0:0] write_flag3_1_fu_264_p6; +reg [15:0] accum_in_load_reg_443; +reg ap_enable_reg_pp0_iter1; +wire [15:0] select_ln115_fu_278_p3; +reg [15:0] select_ln115_reg_448; +wire [15:0] grp_fu_174_p2; +reg [15:0] sum0_reg_453; +wire [15:0] accum_out_3_1_fu_315_p3; +reg ap_enable_reg_pp0_iter10; +wire [15:0] accum_out_2_1_fu_323_p3; +wire [15:0] accum_out_0_1_fu_345_p3; +wire [15:0] accum_out_1_1_fu_360_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_condition_pp0_exit_iter9_state11; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln115_fu_200_p1; +wire [63:0] zext_ln115_1_fu_217_p1; +wire [2:0] i_12_fu_194_p2; +wire [2:0] or_ln115_fu_205_p2; +wire [0:0] icmp_ln118_fu_285_p2; +wire [0:0] icmp_ln118_7_fu_297_p2; +wire [15:0] select_ln118_fu_290_p3; +wire [0:0] icmp_ln118_8_fu_310_p2; +wire [15:0] select_ln118_13_fu_302_p3; +wire [15:0] select_ln118_14_fu_330_p3; +wire [15:0] select_ln118_15_fu_337_p3; +wire [15:0] select_ln118_16_fu_353_p3; +wire ap_CS_fsm_state13; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U52( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(select_ln115_reg_448), + .din1(accum_in_load_reg_443), + .dout(grp_fu_174_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U53( + .din0(1'd1), + .din1(write_flag_0_reg_104), + .din2(write_flag_0_reg_104), + .din3(write_flag_0_reg_104), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag_1_fu_222_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U54( + .din0(write_flag9_0_reg_93), + .din1(write_flag9_0_reg_93), + .din2(write_flag9_0_reg_93), + .din3(1'd1), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag9_1_fu_236_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U55( + .din0(write_flag6_0_reg_82), + .din1(write_flag6_0_reg_82), + .din2(1'd1), + .din3(write_flag6_0_reg_82), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag6_1_fu_250_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U56( + .din0(write_flag3_0_reg_71), + .din1(1'd1), + .din2(write_flag3_0_reg_71), + .din3(write_flag3_0_reg_71), + .din4(trunc_ln106_fu_190_p1), + .dout(write_flag3_1_fu_264_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter9_state11))) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter8; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter8 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter9_state11)) | (~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + out_idx_reg_115 <= add_ln119_fu_178_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_115 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag3_0_reg_71 <= write_flag3_1_fu_264_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag3_0_reg_71 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag6_0_reg_82 <= write_flag6_1_fu_250_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_82 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag9_0_reg_93 <= write_flag9_1_fu_236_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_93 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag_0_reg_104 <= write_flag_1_fu_222_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_104 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_load_reg_443 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397_pp0_iter9_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_0_06_reg_138 <= accum_out_0_1_fu_345_p3; + accum_out_1_07_reg_126 <= accum_out_1_1_fu_360_p3; + accum_out_2_05_reg_150 <= accum_out_2_1_fu_323_p3; + accum_out_3_04_reg_162 <= accum_out_3_1_fu_315_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln105_reg_397 <= icmp_ln105_fu_184_p2; + icmp_ln105_reg_397_pp0_iter1_reg <= icmp_ln105_reg_397; + trunc_ln106_reg_401_pp0_iter1_reg <= trunc_ln106_reg_401; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln105_reg_397_pp0_iter2_reg <= icmp_ln105_reg_397_pp0_iter1_reg; + icmp_ln105_reg_397_pp0_iter3_reg <= icmp_ln105_reg_397_pp0_iter2_reg; + icmp_ln105_reg_397_pp0_iter4_reg <= icmp_ln105_reg_397_pp0_iter3_reg; + icmp_ln105_reg_397_pp0_iter5_reg <= icmp_ln105_reg_397_pp0_iter4_reg; + icmp_ln105_reg_397_pp0_iter6_reg <= icmp_ln105_reg_397_pp0_iter5_reg; + icmp_ln105_reg_397_pp0_iter7_reg <= icmp_ln105_reg_397_pp0_iter6_reg; + icmp_ln105_reg_397_pp0_iter8_reg <= icmp_ln105_reg_397_pp0_iter7_reg; + icmp_ln105_reg_397_pp0_iter9_reg <= icmp_ln105_reg_397_pp0_iter8_reg; + trunc_ln106_reg_401_pp0_iter2_reg <= trunc_ln106_reg_401_pp0_iter1_reg; + trunc_ln106_reg_401_pp0_iter3_reg <= trunc_ln106_reg_401_pp0_iter2_reg; + trunc_ln106_reg_401_pp0_iter4_reg <= trunc_ln106_reg_401_pp0_iter3_reg; + trunc_ln106_reg_401_pp0_iter5_reg <= trunc_ln106_reg_401_pp0_iter4_reg; + trunc_ln106_reg_401_pp0_iter6_reg <= trunc_ln106_reg_401_pp0_iter5_reg; + trunc_ln106_reg_401_pp0_iter7_reg <= trunc_ln106_reg_401_pp0_iter6_reg; + trunc_ln106_reg_401_pp0_iter8_reg <= trunc_ln106_reg_401_pp0_iter7_reg; + trunc_ln106_reg_401_pp0_iter9_reg <= trunc_ln106_reg_401_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_fu_184_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln115_reg_413 <= icmp_ln115_fu_211_p2; + trunc_ln106_reg_401 <= trunc_ln106_fu_190_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln115_reg_448 <= select_ln115_fu_278_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln105_reg_397_pp0_iter8_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sum0_reg_453 <= grp_fu_174_p2; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_condition_pp0_exit_iter9_state11 = 1'b1; + end else begin + ap_condition_pp0_exit_iter9_state11 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln105_fu_184_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln115_1_fu_217_p1; + +assign accum_in_address1 = zext_ln115_fu_200_p1; + +assign accum_out_0_1_fu_345_p3 = ((icmp_ln118_8_fu_310_p2[0:0] == 1'b1) ? accum_out_0_06_reg_138 : select_ln118_15_fu_337_p3); + +assign accum_out_1_1_fu_360_p3 = ((icmp_ln118_8_fu_310_p2[0:0] == 1'b1) ? accum_out_1_07_reg_126 : select_ln118_16_fu_353_p3); + +assign accum_out_2_1_fu_323_p3 = ((icmp_ln118_8_fu_310_p2[0:0] == 1'b1) ? sum0_reg_453 : accum_out_2_05_reg_150); + +assign accum_out_3_1_fu_315_p3 = ((icmp_ln118_8_fu_310_p2[0:0] == 1'b1) ? accum_out_3_04_reg_162 : select_ln118_13_fu_302_p3); + +assign add_ln119_fu_178_p2 = (out_idx_reg_115 + 3'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = accum_out_0_06_reg_138; + +assign ap_return_1 = accum_out_1_07_reg_126; + +assign ap_return_2 = accum_out_2_05_reg_150; + +assign ap_return_3 = accum_out_3_04_reg_162; + +assign i_12_fu_194_p2 = out_idx_reg_115 << 3'd1; + +assign icmp_ln105_fu_184_p2 = ((out_idx_reg_115 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln115_fu_211_p2 = ((or_ln115_fu_205_p2 == 3'd7) ? 1'b1 : 1'b0); + +assign icmp_ln118_7_fu_297_p2 = ((trunc_ln106_reg_401_pp0_iter9_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln118_8_fu_310_p2 = ((trunc_ln106_reg_401_pp0_iter9_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln118_fu_285_p2 = ((trunc_ln106_reg_401_pp0_iter9_reg == 2'd0) ? 1'b1 : 1'b0); + +assign or_ln115_fu_205_p2 = (i_12_fu_194_p2 | 3'd1); + +assign select_ln115_fu_278_p3 = ((icmp_ln115_reg_413[0:0] == 1'b1) ? 16'd0 : accum_in_q0); + +assign select_ln118_13_fu_302_p3 = ((icmp_ln118_7_fu_297_p2[0:0] == 1'b1) ? accum_out_3_04_reg_162 : select_ln118_fu_290_p3); + +assign select_ln118_14_fu_330_p3 = ((icmp_ln118_fu_285_p2[0:0] == 1'b1) ? sum0_reg_453 : accum_out_0_06_reg_138); + +assign select_ln118_15_fu_337_p3 = ((icmp_ln118_7_fu_297_p2[0:0] == 1'b1) ? accum_out_0_06_reg_138 : select_ln118_14_fu_330_p3); + +assign select_ln118_16_fu_353_p3 = ((icmp_ln118_7_fu_297_p2[0:0] == 1'b1) ? sum0_reg_453 : accum_out_1_07_reg_126); + +assign select_ln118_fu_290_p3 = ((icmp_ln118_fu_285_p2[0:0] == 1'b1) ? accum_out_3_04_reg_162 : sum0_reg_453); + +assign trunc_ln106_fu_190_p1 = out_idx_reg_115[1:0]; + +assign zext_ln115_1_fu_217_p1 = or_ln115_fu_205_p2; + +assign zext_ln115_fu_200_p1 = i_12_fu_194_p2; + +endmodule //td_fused_top_tdf1_accum_3 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_accum_4_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0, + accum_in_0_ap_vld, + p_read, + accum_in_1_read, + accum_in_2_read, + accum_in_3_read +); + +parameter ap_ST_fsm_state1 = 16'd1; +parameter ap_ST_fsm_state2 = 16'd2; +parameter ap_ST_fsm_state3 = 16'd4; +parameter ap_ST_fsm_state4 = 16'd8; +parameter ap_ST_fsm_state5 = 16'd16; +parameter ap_ST_fsm_state6 = 16'd32; +parameter ap_ST_fsm_state7 = 16'd64; +parameter ap_ST_fsm_state8 = 16'd128; +parameter ap_ST_fsm_state9 = 16'd256; +parameter ap_ST_fsm_state10 = 16'd512; +parameter ap_ST_fsm_state11 = 16'd1024; +parameter ap_ST_fsm_state12 = 16'd2048; +parameter ap_ST_fsm_state13 = 16'd4096; +parameter ap_ST_fsm_state14 = 16'd8192; +parameter ap_ST_fsm_state15 = 16'd16384; +parameter ap_ST_fsm_state16 = 16'd32768; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_0; +output accum_in_0_ap_vld; +input [15:0] p_read; +input [15:0] accum_in_1_read; +input [15:0] accum_in_2_read; +input [15:0] accum_in_3_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_0; +reg accum_in_0_ap_vld; + +reg ap_done_reg; + reg [15:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [15:0] grp_fu_45_p2; +reg [15:0] sum0_reg_78; +wire ap_CS_fsm_state8; +wire [15:0] grp_fu_51_p2; +reg [15:0] sum1_reg_83; +reg ap_block_state1; +reg [15:0] accum_in_0_preg; +wire ap_CS_fsm_state16; +reg [15:0] grp_fu_45_p0; +reg [15:0] grp_fu_45_p1; +wire ap_CS_fsm_state9; +reg grp_fu_45_ce; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire ap_CS_fsm_state4; +wire ap_CS_fsm_state5; +wire ap_CS_fsm_state6; +wire ap_CS_fsm_state7; +reg grp_fu_51_ce; +reg [15:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 16'd1; +#0 accum_in_0_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U88( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_45_ce), + .din0(grp_fu_45_p0), + .din1(grp_fu_45_p1), + .dout(grp_fu_45_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U89( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_51_ce), + .din0(accum_in_1_read), + .din1(p_read), + .dout(grp_fu_51_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_0_preg <= 16'd0; + end else begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_in_0_preg <= grp_fu_45_p2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state16)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sum0_reg_78 <= grp_fu_45_p2; + sum1_reg_83 <= grp_fu_51_p2; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_in_0 = grp_fu_45_p2; + end else begin + accum_in_0 = accum_in_0_preg; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_in_0_ap_vld = 1'b1; + end else begin + accum_in_0_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & ((ap_done_reg == 1'b1) | (ap_start == 1'b0)))) begin + grp_fu_45_ce = 1'b0; + end else begin + grp_fu_45_ce = 1'b1; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + grp_fu_45_p0 = sum0_reg_78; + end else if ((1'b1 == ap_CS_fsm_state1)) begin + grp_fu_45_p0 = accum_in_3_read; + end else begin + grp_fu_45_p0 = 'bx; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + grp_fu_45_p1 = sum1_reg_83; + end else if ((1'b1 == ap_CS_fsm_state1)) begin + grp_fu_45_p1 = accum_in_2_read; + end else begin + grp_fu_45_p1 = 'bx; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state8) | (1'b1 == ap_CS_fsm_state7) | (1'b1 == ap_CS_fsm_state6) | (1'b1 == ap_CS_fsm_state5) | (~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + grp_fu_51_ce = 1'b1; + end else begin + grp_fu_51_ce = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state16 = ap_CS_fsm[32'd15]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +endmodule //td_fused_top_tdf1_accum_4_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_accum_4_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0, + accum_in_0_ap_vld, + p_read, + accum_in_1_read, + accum_in_2_read, + accum_in_3_read +); + +parameter ap_ST_fsm_state1 = 16'd1; +parameter ap_ST_fsm_state2 = 16'd2; +parameter ap_ST_fsm_state3 = 16'd4; +parameter ap_ST_fsm_state4 = 16'd8; +parameter ap_ST_fsm_state5 = 16'd16; +parameter ap_ST_fsm_state6 = 16'd32; +parameter ap_ST_fsm_state7 = 16'd64; +parameter ap_ST_fsm_state8 = 16'd128; +parameter ap_ST_fsm_state9 = 16'd256; +parameter ap_ST_fsm_state10 = 16'd512; +parameter ap_ST_fsm_state11 = 16'd1024; +parameter ap_ST_fsm_state12 = 16'd2048; +parameter ap_ST_fsm_state13 = 16'd4096; +parameter ap_ST_fsm_state14 = 16'd8192; +parameter ap_ST_fsm_state15 = 16'd16384; +parameter ap_ST_fsm_state16 = 16'd32768; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_0; +output accum_in_0_ap_vld; +input [15:0] p_read; +input [15:0] accum_in_1_read; +input [15:0] accum_in_2_read; +input [15:0] accum_in_3_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_0; +reg accum_in_0_ap_vld; + +reg ap_done_reg; + reg [15:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [15:0] grp_fu_45_p2; +reg [15:0] sum0_reg_78; +wire ap_CS_fsm_state8; +wire [15:0] grp_fu_51_p2; +reg [15:0] sum1_reg_83; +reg ap_block_state1; +reg [15:0] accum_in_0_preg; +wire ap_CS_fsm_state16; +reg [15:0] grp_fu_45_p0; +reg [15:0] grp_fu_45_p1; +wire ap_CS_fsm_state9; +reg grp_fu_45_ce; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire ap_CS_fsm_state4; +wire ap_CS_fsm_state5; +wire ap_CS_fsm_state6; +wire ap_CS_fsm_state7; +reg grp_fu_51_ce; +reg [15:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 16'd1; +#0 accum_in_0_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U96( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_45_ce), + .din0(grp_fu_45_p0), + .din1(grp_fu_45_p1), + .dout(grp_fu_45_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U97( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_51_ce), + .din0(accum_in_1_read), + .din1(p_read), + .dout(grp_fu_51_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_0_preg <= 16'd0; + end else begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_in_0_preg <= grp_fu_45_p2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state16)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sum0_reg_78 <= grp_fu_45_p2; + sum1_reg_83 <= grp_fu_51_p2; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_in_0 = grp_fu_45_p2; + end else begin + accum_in_0 = accum_in_0_preg; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_in_0_ap_vld = 1'b1; + end else begin + accum_in_0_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & ((ap_done_reg == 1'b1) | (ap_start == 1'b0)))) begin + grp_fu_45_ce = 1'b0; + end else begin + grp_fu_45_ce = 1'b1; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + grp_fu_45_p0 = sum0_reg_78; + end else if ((1'b1 == ap_CS_fsm_state1)) begin + grp_fu_45_p0 = accum_in_3_read; + end else begin + grp_fu_45_p0 = 'bx; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + grp_fu_45_p1 = sum1_reg_83; + end else if ((1'b1 == ap_CS_fsm_state1)) begin + grp_fu_45_p1 = accum_in_2_read; + end else begin + grp_fu_45_p1 = 'bx; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state8) | (1'b1 == ap_CS_fsm_state7) | (1'b1 == ap_CS_fsm_state6) | (1'b1 == ap_CS_fsm_state5) | (~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + grp_fu_51_ce = 1'b1; + end else begin + grp_fu_51_ce = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state16 = ap_CS_fsm[32'd15]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +endmodule //td_fused_top_tdf1_accum_4_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_accum_4_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0, + accum_in_0_ap_vld, + p_read, + accum_in_1_read, + accum_in_2_read, + accum_in_3_read +); + +parameter ap_ST_fsm_state1 = 16'd1; +parameter ap_ST_fsm_state2 = 16'd2; +parameter ap_ST_fsm_state3 = 16'd4; +parameter ap_ST_fsm_state4 = 16'd8; +parameter ap_ST_fsm_state5 = 16'd16; +parameter ap_ST_fsm_state6 = 16'd32; +parameter ap_ST_fsm_state7 = 16'd64; +parameter ap_ST_fsm_state8 = 16'd128; +parameter ap_ST_fsm_state9 = 16'd256; +parameter ap_ST_fsm_state10 = 16'd512; +parameter ap_ST_fsm_state11 = 16'd1024; +parameter ap_ST_fsm_state12 = 16'd2048; +parameter ap_ST_fsm_state13 = 16'd4096; +parameter ap_ST_fsm_state14 = 16'd8192; +parameter ap_ST_fsm_state15 = 16'd16384; +parameter ap_ST_fsm_state16 = 16'd32768; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_0; +output accum_in_0_ap_vld; +input [15:0] p_read; +input [15:0] accum_in_1_read; +input [15:0] accum_in_2_read; +input [15:0] accum_in_3_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_0; +reg accum_in_0_ap_vld; + +reg ap_done_reg; + reg [15:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [15:0] grp_fu_45_p2; +reg [15:0] sum0_reg_78; +wire ap_CS_fsm_state8; +wire [15:0] grp_fu_51_p2; +reg [15:0] sum1_reg_83; +reg ap_block_state1; +reg [15:0] accum_in_0_preg; +wire ap_CS_fsm_state16; +reg [15:0] grp_fu_45_p0; +reg [15:0] grp_fu_45_p1; +wire ap_CS_fsm_state9; +reg grp_fu_45_ce; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire ap_CS_fsm_state4; +wire ap_CS_fsm_state5; +wire ap_CS_fsm_state6; +wire ap_CS_fsm_state7; +reg grp_fu_51_ce; +reg [15:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 16'd1; +#0 accum_in_0_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U104( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_45_ce), + .din0(grp_fu_45_p0), + .din1(grp_fu_45_p1), + .dout(grp_fu_45_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U105( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_51_ce), + .din0(accum_in_1_read), + .din1(p_read), + .dout(grp_fu_51_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_0_preg <= 16'd0; + end else begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_in_0_preg <= grp_fu_45_p2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state16)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sum0_reg_78 <= grp_fu_45_p2; + sum1_reg_83 <= grp_fu_51_p2; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_in_0 = grp_fu_45_p2; + end else begin + accum_in_0 = accum_in_0_preg; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_in_0_ap_vld = 1'b1; + end else begin + accum_in_0_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & ((ap_done_reg == 1'b1) | (ap_start == 1'b0)))) begin + grp_fu_45_ce = 1'b0; + end else begin + grp_fu_45_ce = 1'b1; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + grp_fu_45_p0 = sum0_reg_78; + end else if ((1'b1 == ap_CS_fsm_state1)) begin + grp_fu_45_p0 = accum_in_3_read; + end else begin + grp_fu_45_p0 = 'bx; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + grp_fu_45_p1 = sum1_reg_83; + end else if ((1'b1 == ap_CS_fsm_state1)) begin + grp_fu_45_p1 = accum_in_2_read; + end else begin + grp_fu_45_p1 = 'bx; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state8) | (1'b1 == ap_CS_fsm_state7) | (1'b1 == ap_CS_fsm_state6) | (1'b1 == ap_CS_fsm_state5) | (~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + grp_fu_51_ce = 1'b1; + end else begin + grp_fu_51_ce = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state16 = ap_CS_fsm[32'd15]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +endmodule //td_fused_top_tdf1_accum_4_3 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_accum_4 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0, + accum_in_0_ap_vld, + p_read, + accum_in_1_read, + accum_in_2_read, + accum_in_3_read +); + +parameter ap_ST_fsm_state1 = 16'd1; +parameter ap_ST_fsm_state2 = 16'd2; +parameter ap_ST_fsm_state3 = 16'd4; +parameter ap_ST_fsm_state4 = 16'd8; +parameter ap_ST_fsm_state5 = 16'd16; +parameter ap_ST_fsm_state6 = 16'd32; +parameter ap_ST_fsm_state7 = 16'd64; +parameter ap_ST_fsm_state8 = 16'd128; +parameter ap_ST_fsm_state9 = 16'd256; +parameter ap_ST_fsm_state10 = 16'd512; +parameter ap_ST_fsm_state11 = 16'd1024; +parameter ap_ST_fsm_state12 = 16'd2048; +parameter ap_ST_fsm_state13 = 16'd4096; +parameter ap_ST_fsm_state14 = 16'd8192; +parameter ap_ST_fsm_state15 = 16'd16384; +parameter ap_ST_fsm_state16 = 16'd32768; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_0; +output accum_in_0_ap_vld; +input [15:0] p_read; +input [15:0] accum_in_1_read; +input [15:0] accum_in_2_read; +input [15:0] accum_in_3_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_0; +reg accum_in_0_ap_vld; + +reg ap_done_reg; + reg [15:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [15:0] grp_fu_45_p2; +reg [15:0] sum0_reg_78; +wire ap_CS_fsm_state8; +wire [15:0] grp_fu_51_p2; +reg [15:0] sum1_reg_83; +reg ap_block_state1; +reg [15:0] accum_in_0_preg; +wire ap_CS_fsm_state16; +reg [15:0] grp_fu_45_p0; +reg [15:0] grp_fu_45_p1; +wire ap_CS_fsm_state9; +reg grp_fu_45_ce; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire ap_CS_fsm_state4; +wire ap_CS_fsm_state5; +wire ap_CS_fsm_state6; +wire ap_CS_fsm_state7; +reg grp_fu_51_ce; +reg [15:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 16'd1; +#0 accum_in_0_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U80( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_45_ce), + .din0(grp_fu_45_p0), + .din1(grp_fu_45_p1), + .dout(grp_fu_45_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U81( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_51_ce), + .din0(accum_in_1_read), + .din1(p_read), + .dout(grp_fu_51_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_0_preg <= 16'd0; + end else begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_in_0_preg <= grp_fu_45_p2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state16)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sum0_reg_78 <= grp_fu_45_p2; + sum1_reg_83 <= grp_fu_51_p2; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_in_0 = grp_fu_45_p2; + end else begin + accum_in_0 = accum_in_0_preg; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_in_0_ap_vld = 1'b1; + end else begin + accum_in_0_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & ((ap_done_reg == 1'b1) | (ap_start == 1'b0)))) begin + grp_fu_45_ce = 1'b0; + end else begin + grp_fu_45_ce = 1'b1; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + grp_fu_45_p0 = sum0_reg_78; + end else if ((1'b1 == ap_CS_fsm_state1)) begin + grp_fu_45_p0 = accum_in_3_read; + end else begin + grp_fu_45_p0 = 'bx; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + grp_fu_45_p1 = sum1_reg_83; + end else if ((1'b1 == ap_CS_fsm_state1)) begin + grp_fu_45_p1 = accum_in_2_read; + end else begin + grp_fu_45_p1 = 'bx; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state8) | (1'b1 == ap_CS_fsm_state7) | (1'b1 == ap_CS_fsm_state6) | (1'b1 == ap_CS_fsm_state5) | (~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + grp_fu_51_ce = 1'b1; + end else begin + grp_fu_51_ce = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state16 = ap_CS_fsm[32'd15]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +endmodule //td_fused_top_tdf1_accum_4 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf1_adjustments_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 48; +parameter AWIDTH = 4; +parameter MEM_SIZE = 16; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf1_adjustments( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd48; +parameter AddressRange = 32'd16; +parameter AddressWidth = 32'd4; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf1_adjustments_ram td_fused_top_tdf1_adjustments_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_0_read, + sums_1_read, + sums_2_read, + sums_3_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + input_indices_23_out_din, + input_indices_23_out_full_n, + input_indices_23_out_write, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state25 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_0_read; +input [15:0] sums_1_read; +input [15:0] sums_2_read; +input [15:0] sums_3_read; +output [3:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [3:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [3:0] input_indices_23_out_din; +input input_indices_23_out_full_n; +output input_indices_23_out_write; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg input_indices_23_read; +reg input_indices_23_out_write; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +reg input_indices_23_out_blk_n; +reg [0:0] write_flag6_0_reg_153; +reg [0:0] write_flag9_0_reg_164; +reg [0:0] write_flag12_0_reg_175; +reg [0:0] write_flag_0_reg_186; +reg [2:0] o_reg_197; +reg [15:0] outputs_1_011_reg_208; +reg [15:0] outputs_0_010_reg_220; +reg [15:0] outputs_2_09_reg_232; +reg [15:0] outputs_3_08_reg_244; +wire [1:0] trunc_ln258_fu_268_p1; +reg [1:0] trunc_ln258_reg_550; +wire [2:0] add_ln213_fu_272_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_state13_pp0_stage0_iter11; +wire ap_block_state14_pp0_stage0_iter12; +wire ap_block_state15_pp0_stage0_iter13; +wire ap_block_state16_pp0_stage0_iter14; +wire ap_block_state17_pp0_stage0_iter15; +wire ap_block_state18_pp0_stage0_iter16; +wire ap_block_state19_pp0_stage0_iter17; +wire ap_block_state20_pp0_stage0_iter18; +wire ap_block_state21_pp0_stage0_iter19; +wire ap_block_state22_pp0_stage0_iter20; +wire ap_block_state23_pp0_stage0_iter21; +wire ap_block_state24_pp0_stage0_iter22; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln213_fu_278_p2; +reg [0:0] icmp_ln213_reg_560; +reg [0:0] icmp_ln213_reg_560_pp0_iter1_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter2_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter3_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter4_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter5_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter6_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter7_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter8_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter9_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter10_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter11_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter12_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter13_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter14_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter15_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter16_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter17_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter18_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter19_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter20_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter21_reg; +wire [1:0] trunc_ln219_fu_284_p1; +reg [1:0] trunc_ln219_reg_564; +reg [1:0] trunc_ln219_reg_564_pp0_iter1_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter2_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter3_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter4_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter5_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter6_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter7_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter8_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter9_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter10_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter11_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter12_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter13_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter14_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter15_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter16_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter17_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter18_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter19_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter20_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter21_reg; +wire [0:0] write_flag_1_fu_300_p6; +wire [0:0] write_flag12_1_fu_314_p6; +wire [0:0] write_flag9_1_fu_328_p6; +wire [0:0] write_flag6_1_fu_342_p6; +wire [15:0] trunc_ln220_fu_356_p1; +reg [15:0] trunc_ln220_reg_597; +reg [15:0] tmp_260_i_i_reg_602; +reg [15:0] tmp_260_i_i_reg_602_pp0_iter2_reg; +reg [15:0] tmp_260_i_i_reg_602_pp0_iter3_reg; +reg [15:0] tmp_260_i_i_reg_602_pp0_iter4_reg; +reg [15:0] tmp_260_i_i_reg_602_pp0_iter5_reg; +reg [15:0] tmp_260_i_i_reg_602_pp0_iter6_reg; +reg [15:0] tmp_260_i_i_reg_602_pp0_iter7_reg; +reg [15:0] tmp_260_i_i_reg_602_pp0_iter8_reg; +reg [15:0] tmp_261_i_i_reg_607; +reg [15:0] tmp_261_i_i_reg_607_pp0_iter2_reg; +reg [15:0] tmp_261_i_i_reg_607_pp0_iter3_reg; +reg [15:0] tmp_261_i_i_reg_607_pp0_iter4_reg; +reg [15:0] tmp_261_i_i_reg_607_pp0_iter5_reg; +reg [15:0] tmp_261_i_i_reg_607_pp0_iter6_reg; +reg [15:0] tmp_261_i_i_reg_607_pp0_iter7_reg; +reg [15:0] tmp_261_i_i_reg_607_pp0_iter8_reg; +reg [15:0] tmp_261_i_i_reg_607_pp0_iter9_reg; +reg [15:0] tmp_261_i_i_reg_607_pp0_iter10_reg; +reg [15:0] tmp_261_i_i_reg_607_pp0_iter11_reg; +reg [15:0] tmp_261_i_i_reg_607_pp0_iter12_reg; +reg [15:0] tmp_261_i_i_reg_607_pp0_iter13_reg; +wire [15:0] val_in_assign_fu_380_p6; +reg [15:0] val_in_assign_reg_612; +wire [15:0] grp_fu_260_p2; +reg [15:0] sub_i_i_i_reg_622; +wire [15:0] grp_fu_264_p2; +reg [15:0] normalized_reg_632; +wire [15:0] grp_fu_256_p2; +reg [15:0] biased_reg_642; +wire [15:0] outputs_3_1_fu_450_p3; +reg ap_enable_reg_pp0_iter22; +wire [15:0] outputs_2_1_fu_458_p3; +wire [15:0] outputs_0_1_fu_482_p3; +wire [15:0] outputs_1_1_fu_498_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_condition_pp0_exit_iter21_state23; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln220_fu_295_p1; +wire [15:0] grp_fu_256_p1; +wire [15:0] grp_fu_260_p1; +wire [15:0] grp_fu_264_p1; +wire [3:0] ochan_fu_288_p3; +wire [15:0] data_V_fu_401_p1; +wire [0:0] p_Result_s_fu_404_p3; +wire [0:0] icmp_ln223_fu_419_p2; +wire [15:0] activated_fu_412_p3; +wire [0:0] icmp_ln223_11_fu_432_p2; +wire [15:0] select_ln223_fu_424_p3; +wire [0:0] icmp_ln223_12_fu_445_p2; +wire [15:0] select_ln223_21_fu_437_p3; +wire [15:0] select_ln223_22_fu_466_p3; +wire [15:0] select_ln223_23_fu_474_p3; +wire [15:0] select_ln223_24_fu_490_p3; +wire ap_CS_fsm_state25; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U112( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(normalized_reg_632), + .din1(grp_fu_256_p1), + .dout(grp_fu_256_p2) +); + +td_fused_top_hsub_16ns_16ns_16_7_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 7 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_7_full_dsp_1_U113( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(val_in_assign_reg_612), + .din1(grp_fu_260_p1), + .dout(grp_fu_260_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U114( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_622), + .din1(grp_fu_264_p1), + .dout(grp_fu_264_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U115( + .din0(1'd1), + .din1(write_flag_0_reg_186), + .din2(write_flag_0_reg_186), + .din3(write_flag_0_reg_186), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag_1_fu_300_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U116( + .din0(write_flag12_0_reg_175), + .din1(write_flag12_0_reg_175), + .din2(write_flag12_0_reg_175), + .din3(1'd1), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag12_1_fu_314_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U117( + .din0(write_flag9_0_reg_164), + .din1(write_flag9_0_reg_164), + .din2(1'd1), + .din3(write_flag9_0_reg_164), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag9_1_fu_328_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U118( + .din0(write_flag6_0_reg_153), + .din1(1'd1), + .din2(write_flag6_0_reg_153), + .din3(write_flag6_0_reg_153), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag6_1_fu_342_p6) +); + +td_fused_top_mux_42_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 16 )) +mux_42_16_1_1_U119( + .din0(sums_0_read), + .din1(sums_1_read), + .din2(sums_2_read), + .din3(sums_3_read), + .din4(trunc_ln219_reg_564), + .dout(val_in_assign_fu_380_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end else if ((((ap_enable_reg_pp0_iter20 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter21_state23) & (1'b0 == ap_block_pp0_stage0_subdone)) | (~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter21_state23) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter20; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + o_reg_197 <= add_ln213_fu_272_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + o_reg_197 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag12_0_reg_175 <= write_flag12_1_fu_314_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag12_0_reg_175 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag6_0_reg_153 <= write_flag6_1_fu_342_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_153 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag9_0_reg_164 <= write_flag9_1_fu_328_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_164 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag_0_reg_186 <= write_flag_1_fu_300_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_186 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_560_pp0_iter20_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + biased_reg_642 <= grp_fu_256_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln213_reg_560 <= icmp_ln213_fu_278_p2; + icmp_ln213_reg_560_pp0_iter1_reg <= icmp_ln213_reg_560; + trunc_ln219_reg_564_pp0_iter1_reg <= trunc_ln219_reg_564; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln213_reg_560_pp0_iter10_reg <= icmp_ln213_reg_560_pp0_iter9_reg; + icmp_ln213_reg_560_pp0_iter11_reg <= icmp_ln213_reg_560_pp0_iter10_reg; + icmp_ln213_reg_560_pp0_iter12_reg <= icmp_ln213_reg_560_pp0_iter11_reg; + icmp_ln213_reg_560_pp0_iter13_reg <= icmp_ln213_reg_560_pp0_iter12_reg; + icmp_ln213_reg_560_pp0_iter14_reg <= icmp_ln213_reg_560_pp0_iter13_reg; + icmp_ln213_reg_560_pp0_iter15_reg <= icmp_ln213_reg_560_pp0_iter14_reg; + icmp_ln213_reg_560_pp0_iter16_reg <= icmp_ln213_reg_560_pp0_iter15_reg; + icmp_ln213_reg_560_pp0_iter17_reg <= icmp_ln213_reg_560_pp0_iter16_reg; + icmp_ln213_reg_560_pp0_iter18_reg <= icmp_ln213_reg_560_pp0_iter17_reg; + icmp_ln213_reg_560_pp0_iter19_reg <= icmp_ln213_reg_560_pp0_iter18_reg; + icmp_ln213_reg_560_pp0_iter20_reg <= icmp_ln213_reg_560_pp0_iter19_reg; + icmp_ln213_reg_560_pp0_iter21_reg <= icmp_ln213_reg_560_pp0_iter20_reg; + icmp_ln213_reg_560_pp0_iter2_reg <= icmp_ln213_reg_560_pp0_iter1_reg; + icmp_ln213_reg_560_pp0_iter3_reg <= icmp_ln213_reg_560_pp0_iter2_reg; + icmp_ln213_reg_560_pp0_iter4_reg <= icmp_ln213_reg_560_pp0_iter3_reg; + icmp_ln213_reg_560_pp0_iter5_reg <= icmp_ln213_reg_560_pp0_iter4_reg; + icmp_ln213_reg_560_pp0_iter6_reg <= icmp_ln213_reg_560_pp0_iter5_reg; + icmp_ln213_reg_560_pp0_iter7_reg <= icmp_ln213_reg_560_pp0_iter6_reg; + icmp_ln213_reg_560_pp0_iter8_reg <= icmp_ln213_reg_560_pp0_iter7_reg; + icmp_ln213_reg_560_pp0_iter9_reg <= icmp_ln213_reg_560_pp0_iter8_reg; + tmp_260_i_i_reg_602_pp0_iter2_reg <= tmp_260_i_i_reg_602; + tmp_260_i_i_reg_602_pp0_iter3_reg <= tmp_260_i_i_reg_602_pp0_iter2_reg; + tmp_260_i_i_reg_602_pp0_iter4_reg <= tmp_260_i_i_reg_602_pp0_iter3_reg; + tmp_260_i_i_reg_602_pp0_iter5_reg <= tmp_260_i_i_reg_602_pp0_iter4_reg; + tmp_260_i_i_reg_602_pp0_iter6_reg <= tmp_260_i_i_reg_602_pp0_iter5_reg; + tmp_260_i_i_reg_602_pp0_iter7_reg <= tmp_260_i_i_reg_602_pp0_iter6_reg; + tmp_260_i_i_reg_602_pp0_iter8_reg <= tmp_260_i_i_reg_602_pp0_iter7_reg; + tmp_261_i_i_reg_607_pp0_iter10_reg <= tmp_261_i_i_reg_607_pp0_iter9_reg; + tmp_261_i_i_reg_607_pp0_iter11_reg <= tmp_261_i_i_reg_607_pp0_iter10_reg; + tmp_261_i_i_reg_607_pp0_iter12_reg <= tmp_261_i_i_reg_607_pp0_iter11_reg; + tmp_261_i_i_reg_607_pp0_iter13_reg <= tmp_261_i_i_reg_607_pp0_iter12_reg; + tmp_261_i_i_reg_607_pp0_iter2_reg <= tmp_261_i_i_reg_607; + tmp_261_i_i_reg_607_pp0_iter3_reg <= tmp_261_i_i_reg_607_pp0_iter2_reg; + tmp_261_i_i_reg_607_pp0_iter4_reg <= tmp_261_i_i_reg_607_pp0_iter3_reg; + tmp_261_i_i_reg_607_pp0_iter5_reg <= tmp_261_i_i_reg_607_pp0_iter4_reg; + tmp_261_i_i_reg_607_pp0_iter6_reg <= tmp_261_i_i_reg_607_pp0_iter5_reg; + tmp_261_i_i_reg_607_pp0_iter7_reg <= tmp_261_i_i_reg_607_pp0_iter6_reg; + tmp_261_i_i_reg_607_pp0_iter8_reg <= tmp_261_i_i_reg_607_pp0_iter7_reg; + tmp_261_i_i_reg_607_pp0_iter9_reg <= tmp_261_i_i_reg_607_pp0_iter8_reg; + trunc_ln219_reg_564_pp0_iter10_reg <= trunc_ln219_reg_564_pp0_iter9_reg; + trunc_ln219_reg_564_pp0_iter11_reg <= trunc_ln219_reg_564_pp0_iter10_reg; + trunc_ln219_reg_564_pp0_iter12_reg <= trunc_ln219_reg_564_pp0_iter11_reg; + trunc_ln219_reg_564_pp0_iter13_reg <= trunc_ln219_reg_564_pp0_iter12_reg; + trunc_ln219_reg_564_pp0_iter14_reg <= trunc_ln219_reg_564_pp0_iter13_reg; + trunc_ln219_reg_564_pp0_iter15_reg <= trunc_ln219_reg_564_pp0_iter14_reg; + trunc_ln219_reg_564_pp0_iter16_reg <= trunc_ln219_reg_564_pp0_iter15_reg; + trunc_ln219_reg_564_pp0_iter17_reg <= trunc_ln219_reg_564_pp0_iter16_reg; + trunc_ln219_reg_564_pp0_iter18_reg <= trunc_ln219_reg_564_pp0_iter17_reg; + trunc_ln219_reg_564_pp0_iter19_reg <= trunc_ln219_reg_564_pp0_iter18_reg; + trunc_ln219_reg_564_pp0_iter20_reg <= trunc_ln219_reg_564_pp0_iter19_reg; + trunc_ln219_reg_564_pp0_iter21_reg <= trunc_ln219_reg_564_pp0_iter20_reg; + trunc_ln219_reg_564_pp0_iter2_reg <= trunc_ln219_reg_564_pp0_iter1_reg; + trunc_ln219_reg_564_pp0_iter3_reg <= trunc_ln219_reg_564_pp0_iter2_reg; + trunc_ln219_reg_564_pp0_iter4_reg <= trunc_ln219_reg_564_pp0_iter3_reg; + trunc_ln219_reg_564_pp0_iter5_reg <= trunc_ln219_reg_564_pp0_iter4_reg; + trunc_ln219_reg_564_pp0_iter6_reg <= trunc_ln219_reg_564_pp0_iter5_reg; + trunc_ln219_reg_564_pp0_iter7_reg <= trunc_ln219_reg_564_pp0_iter6_reg; + trunc_ln219_reg_564_pp0_iter8_reg <= trunc_ln219_reg_564_pp0_iter7_reg; + trunc_ln219_reg_564_pp0_iter9_reg <= trunc_ln219_reg_564_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_560_pp0_iter12_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + normalized_reg_632 <= grp_fu_264_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter22 == 1'b1) & (icmp_ln213_reg_560_pp0_iter21_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + outputs_0_010_reg_220 <= outputs_0_1_fu_482_p3; + outputs_1_011_reg_208 <= outputs_1_1_fu_498_p3; + outputs_2_09_reg_232 <= outputs_2_1_fu_458_p3; + outputs_3_08_reg_244 <= outputs_3_1_fu_450_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_560_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sub_i_i_i_reg_622 <= grp_fu_260_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_reg_560 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + tmp_260_i_i_reg_602 <= {{adjustments_q0[31:16]}}; + tmp_261_i_i_reg_607 <= {{adjustments_q0[47:32]}}; + trunc_ln220_reg_597 <= trunc_ln220_fu_356_p1; + val_in_assign_reg_612 <= val_in_assign_fu_380_p6; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + trunc_ln219_reg_564 <= trunc_ln219_fu_284_p1; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + trunc_ln258_reg_550 <= trunc_ln258_fu_268_p1; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0))) begin + ap_condition_pp0_exit_iter21_state23 = 1'b1; + end else begin + ap_condition_pp0_exit_iter21_state23 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_out_blk_n = input_indices_23_out_full_n; + end else begin + input_indices_23_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_out_write = 1'b1; + end else begin + input_indices_23_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state25; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state25 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign activated_fu_412_p3 = ((p_Result_s_fu_404_p3[0:0] == 1'b1) ? 16'd0 : biased_reg_642); + +assign add_ln213_fu_272_p2 = (o_reg_197 + 3'd1); + +assign adjustments_address0 = zext_ln220_fu_295_p1; + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state25 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = outputs_0_010_reg_220; + +assign ap_return_1 = outputs_1_011_reg_208; + +assign ap_return_2 = outputs_2_09_reg_232; + +assign ap_return_3 = outputs_3_08_reg_244; + +assign data_V_fu_401_p1 = biased_reg_642; + +assign grp_fu_256_p1 = tmp_261_i_i_reg_607_pp0_iter13_reg; + +assign grp_fu_260_p1 = trunc_ln220_reg_597; + +assign grp_fu_264_p1 = tmp_260_i_i_reg_602_pp0_iter8_reg; + +assign icmp_ln213_fu_278_p2 = ((o_reg_197 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln223_11_fu_432_p2 = ((trunc_ln219_reg_564_pp0_iter21_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln223_12_fu_445_p2 = ((trunc_ln219_reg_564_pp0_iter21_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln223_fu_419_p2 = ((trunc_ln219_reg_564_pp0_iter21_reg == 2'd0) ? 1'b1 : 1'b0); + +assign input_indices_23_out_din = input_indices_23_dout; + +assign ochan_fu_288_p3 = {{trunc_ln258_reg_550}, {trunc_ln219_fu_284_p1}}; + +assign outputs_0_1_fu_482_p3 = ((icmp_ln223_12_fu_445_p2[0:0] == 1'b1) ? outputs_0_010_reg_220 : select_ln223_23_fu_474_p3); + +assign outputs_1_1_fu_498_p3 = ((icmp_ln223_12_fu_445_p2[0:0] == 1'b1) ? outputs_1_011_reg_208 : select_ln223_24_fu_490_p3); + +assign outputs_2_1_fu_458_p3 = ((icmp_ln223_12_fu_445_p2[0:0] == 1'b1) ? activated_fu_412_p3 : outputs_2_09_reg_232); + +assign outputs_3_1_fu_450_p3 = ((icmp_ln223_12_fu_445_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : select_ln223_21_fu_437_p3); + +assign p_Result_s_fu_404_p3 = data_V_fu_401_p1[32'd15]; + +assign select_ln223_21_fu_437_p3 = ((icmp_ln223_11_fu_432_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : select_ln223_fu_424_p3); + +assign select_ln223_22_fu_466_p3 = ((icmp_ln223_fu_419_p2[0:0] == 1'b1) ? activated_fu_412_p3 : outputs_0_010_reg_220); + +assign select_ln223_23_fu_474_p3 = ((icmp_ln223_11_fu_432_p2[0:0] == 1'b1) ? outputs_0_010_reg_220 : select_ln223_22_fu_466_p3); + +assign select_ln223_24_fu_490_p3 = ((icmp_ln223_11_fu_432_p2[0:0] == 1'b1) ? activated_fu_412_p3 : outputs_1_011_reg_208); + +assign select_ln223_fu_424_p3 = ((icmp_ln223_fu_419_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : activated_fu_412_p3); + +assign trunc_ln219_fu_284_p1 = o_reg_197[1:0]; + +assign trunc_ln220_fu_356_p1 = adjustments_q0[15:0]; + +assign trunc_ln258_fu_268_p1 = input_indices_23_dout[1:0]; + +assign zext_ln220_fu_295_p1 = ochan_fu_288_p3; + +endmodule //td_fused_top_tdf1_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_q0, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_q0, + weight_vecs_1_address0, + weight_vecs_1_ce0, + weight_vecs_1_q0, + weight_vecs_2_address0, + weight_vecs_2_ce0, + weight_vecs_2_q0, + weight_vecs_3_address0, + weight_vecs_3_ce0, + weight_vecs_3_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0, + products_1_address0, + products_1_ce0, + products_1_we0, + products_1_d0, + products_2_address0, + products_2_ce0, + products_2_we0, + products_2_d0, + products_3_address0, + products_3_ce0, + products_3_we0, + products_3_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state11 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [4:0] ifmap_vec_address0; +output ifmap_vec_ce0; +input [15:0] ifmap_vec_q0; +output [4:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +input [15:0] weight_vecs_0_q0; +output [4:0] weight_vecs_1_address0; +output weight_vecs_1_ce0; +input [15:0] weight_vecs_1_q0; +output [4:0] weight_vecs_2_address0; +output weight_vecs_2_ce0; +input [15:0] weight_vecs_2_q0; +output [4:0] weight_vecs_3_address0; +output weight_vecs_3_ce0; +input [15:0] weight_vecs_3_q0; +output [4:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; +output [4:0] products_1_address0; +output products_1_ce0; +output products_1_we0; +output [15:0] products_1_d0; +output [4:0] products_2_address0; +output products_2_ce0; +output products_2_we0; +output [15:0] products_2_d0; +output [4:0] products_3_address0; +output products_3_ce0; +output products_3_we0; +output [15:0] products_3_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_ce0; +reg weight_vecs_0_ce0; +reg weight_vecs_1_ce0; +reg weight_vecs_2_ce0; +reg weight_vecs_3_ce0; +reg products_0_ce0; +reg products_0_we0; +reg products_1_ce0; +reg products_1_we0; +reg products_2_ce0; +reg products_2_we0; +reg products_3_ce0; +reg products_3_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [4:0] indvar_flatten21_reg_183; +reg [1:0] ii_reg_194; +reg [3:0] indvar_flatten_reg_205; +reg [1:0] jj_reg_216; +reg [1:0] ic_reg_227; +wire [4:0] add_ln147_6_fu_254_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_pp0_stage0_11001; +wire [4:0] sub_ln150_1_fu_298_p2; +reg [4:0] sub_ln150_1_reg_569; +wire [0:0] icmp_ln147_fu_304_p2; +reg [0:0] icmp_ln147_reg_574; +reg [0:0] icmp_ln147_reg_574_pp0_iter1_reg; +reg [0:0] icmp_ln147_reg_574_pp0_iter2_reg; +reg [0:0] icmp_ln147_reg_574_pp0_iter3_reg; +reg [0:0] icmp_ln147_reg_574_pp0_iter4_reg; +reg [0:0] icmp_ln147_reg_574_pp0_iter5_reg; +reg [0:0] icmp_ln147_reg_574_pp0_iter6_reg; +reg [0:0] icmp_ln147_reg_574_pp0_iter7_reg; +wire [0:0] icmp_ln148_fu_316_p2; +reg [0:0] icmp_ln148_reg_578; +wire [1:0] select_ln147_22_fu_330_p3; +reg [1:0] select_ln147_22_reg_583; +wire [4:0] sub_ln150_6_fu_380_p2; +reg [4:0] sub_ln150_6_reg_588; +wire [0:0] and_ln147_fu_406_p2; +reg [0:0] and_ln147_reg_594; +wire [1:0] select_ln148_fu_424_p3; +reg [1:0] select_ln148_reg_599; +wire [1:0] select_ln148_16_fu_432_p3; +reg [1:0] select_ln148_16_reg_604; +wire [4:0] empty_137_fu_450_p1; +reg [4:0] empty_137_reg_609; +wire [2:0] empty_138_fu_454_p1; +reg [2:0] empty_138_reg_614; +wire [4:0] add_ln150_6_fu_462_p2; +reg [4:0] add_ln150_6_reg_619; +wire [1:0] add_ln149_fu_468_p2; +wire [3:0] select_ln148_18_fu_480_p3; +wire [4:0] p_fu_551_p2; +reg [4:0] p_reg_660; +reg [4:0] p_reg_660_pp0_iter2_reg; +reg [4:0] p_reg_660_pp0_iter3_reg; +reg [4:0] p_reg_660_pp0_iter4_reg; +reg [4:0] p_reg_660_pp0_iter5_reg; +reg [4:0] p_reg_660_pp0_iter6_reg; +reg [4:0] p_reg_660_pp0_iter7_reg; +reg [15:0] ifmap_vec_load_reg_665; +reg [15:0] weight_vecs_0_load_reg_673; +reg [15:0] weight_vecs_1_load_reg_678; +reg [15:0] weight_vecs_2_load_reg_683; +reg [15:0] weight_vecs_3_load_reg_688; +wire [15:0] grp_fu_238_p2; +reg [15:0] mul_reg_693; +wire [15:0] grp_fu_242_p2; +reg [15:0] mul_1_reg_698; +wire [15:0] grp_fu_246_p2; +reg [15:0] mul_2_reg_703; +wire [15:0] grp_fu_250_p2; +reg [15:0] mul_3_reg_708; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg [1:0] ap_phi_mux_ii_phi_fu_198_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_220_p4; +wire [63:0] p_cast63_fu_542_p1; +wire [63:0] idxprom30_fu_557_p1; +wire [3:0] shl_ln_fu_264_p3; +wire [4:0] zext_ln150_7_fu_272_p1; +wire [4:0] zext_ln150_fu_260_p1; +wire [4:0] sub_ln150_fu_276_p2; +wire [4:0] zext_ln150_8_fu_282_p1; +wire [4:0] add_ln150_fu_286_p2; +wire [4:0] shl_ln150_fu_292_p2; +wire [1:0] add_ln147_fu_310_p2; +wire [3:0] tmp_s_fu_342_p3; +wire [4:0] tmp_168_cast_fu_350_p1; +wire [4:0] select_ln147_27_cast_fu_338_p1; +wire [4:0] empty_135_fu_354_p2; +wire [3:0] shl_ln150_mid1_fu_368_p3; +wire [4:0] zext_ln150_13_fu_376_p1; +wire [4:0] zext_ln150_12_fu_364_p1; +wire [0:0] icmp_ln149_fu_400_p2; +wire [0:0] xor_ln147_fu_394_p2; +wire [1:0] select_ln147_fu_322_p3; +wire [0:0] or_ln148_fu_418_p2; +wire [1:0] add_ln148_fu_412_p2; +wire [5:0] sext_ln150_fu_360_p1; +wire [5:0] select_ln148_21_cast_fu_440_p1; +wire [5:0] empty_136_fu_444_p2; +wire [4:0] select_ln147_23_fu_386_p3; +wire [4:0] zext_ln150_14_fu_458_p1; +wire [3:0] add_ln148_6_fu_474_p2; +wire [4:0] shl_ln150_1_fu_488_p2; +wire [4:0] sub_ln150_7_fu_493_p2; +wire [4:0] p_shl_cast_fu_504_p3; +wire [4:0] shl_ln150_2_fu_516_p2; +wire [4:0] sub_ln150_8_fu_521_p2; +wire [4:0] select_ln147_24_fu_498_p3; +wire [4:0] empty_139_fu_511_p2; +wire [4:0] select_ln148_cast_fu_533_p1; +wire [4:0] empty_140_fu_536_p2; +wire [4:0] select_ln148_17_fu_526_p3; +wire ap_CS_fsm_state11; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U31( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_load_reg_665), + .din1(weight_vecs_0_load_reg_673), + .dout(grp_fu_238_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U32( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_load_reg_665), + .din1(weight_vecs_1_load_reg_678), + .dout(grp_fu_242_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U33( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_load_reg_665), + .din1(weight_vecs_2_load_reg_683), + .dout(grp_fu_246_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U34( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_load_reg_665), + .din1(weight_vecs_3_load_reg_688), + .dout(grp_fu_250_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_304_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ic_reg_227 <= add_ln149_fu_468_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_reg_227 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_574 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_194 <= select_ln147_22_reg_583; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_194 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_304_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten21_reg_183 <= add_ln147_6_fu_254_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten21_reg_183 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_304_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten_reg_205 <= select_ln148_18_fu_480_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_205 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_574 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_216 <= select_ln148_16_reg_604; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_216 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_304_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln150_6_reg_619 <= add_ln150_6_fu_462_p2; + and_ln147_reg_594 <= and_ln147_fu_406_p2; + empty_137_reg_609 <= empty_137_fu_450_p1; + empty_138_reg_614 <= empty_138_fu_454_p1; + icmp_ln148_reg_578 <= icmp_ln148_fu_316_p2; + select_ln148_reg_599 <= select_ln148_fu_424_p3; + sub_ln150_6_reg_588 <= sub_ln150_6_fu_380_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln147_reg_574 <= icmp_ln147_fu_304_p2; + icmp_ln147_reg_574_pp0_iter1_reg <= icmp_ln147_reg_574; + sub_ln150_1_reg_569 <= sub_ln150_1_fu_298_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln147_reg_574_pp0_iter2_reg <= icmp_ln147_reg_574_pp0_iter1_reg; + icmp_ln147_reg_574_pp0_iter3_reg <= icmp_ln147_reg_574_pp0_iter2_reg; + icmp_ln147_reg_574_pp0_iter4_reg <= icmp_ln147_reg_574_pp0_iter3_reg; + icmp_ln147_reg_574_pp0_iter5_reg <= icmp_ln147_reg_574_pp0_iter4_reg; + icmp_ln147_reg_574_pp0_iter6_reg <= icmp_ln147_reg_574_pp0_iter5_reg; + icmp_ln147_reg_574_pp0_iter7_reg <= icmp_ln147_reg_574_pp0_iter6_reg; + p_reg_660_pp0_iter2_reg <= p_reg_660; + p_reg_660_pp0_iter3_reg <= p_reg_660_pp0_iter2_reg; + p_reg_660_pp0_iter4_reg <= p_reg_660_pp0_iter3_reg; + p_reg_660_pp0_iter5_reg <= p_reg_660_pp0_iter4_reg; + p_reg_660_pp0_iter6_reg <= p_reg_660_pp0_iter5_reg; + p_reg_660_pp0_iter7_reg <= p_reg_660_pp0_iter6_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_574_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_load_reg_665 <= ifmap_vec_q0; + weight_vecs_0_load_reg_673 <= weight_vecs_0_q0; + weight_vecs_1_load_reg_678 <= weight_vecs_1_q0; + weight_vecs_2_load_reg_683 <= weight_vecs_2_q0; + weight_vecs_3_load_reg_688 <= weight_vecs_3_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_574_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_1_reg_698 <= grp_fu_242_p2; + mul_2_reg_703 <= grp_fu_246_p2; + mul_3_reg_708 <= grp_fu_250_p2; + mul_reg_693 <= grp_fu_238_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_574 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + p_reg_660 <= p_fu_551_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_304_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln147_22_reg_583 <= select_ln147_22_fu_330_p3; + select_ln148_16_reg_604 <= select_ln148_16_fu_432_p3; + end +end + +always @ (*) begin + if ((icmp_ln147_fu_304_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_574 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_198_p4 = select_ln147_22_reg_583; + end else begin + ap_phi_mux_ii_phi_fu_198_p4 = ii_reg_194; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_574 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_220_p4 = select_ln148_16_reg_604; + end else begin + ap_phi_mux_jj_phi_fu_220_p4 = jj_reg_216; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_574_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_ce0 = 1'b1; + end else begin + products_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_574_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_we0 = 1'b1; + end else begin + products_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_ce0 = 1'b1; + end else begin + products_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_574_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_we0 = 1'b1; + end else begin + products_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_ce0 = 1'b1; + end else begin + products_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_574_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_we0 = 1'b1; + end else begin + products_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_ce0 = 1'b1; + end else begin + weight_vecs_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_ce0 = 1'b1; + end else begin + weight_vecs_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_ce0 = 1'b1; + end else begin + weight_vecs_3_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln147_fu_304_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter8 == 1'b1) & (ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter8 == 1'b1) & (ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln147_fu_304_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state11; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_6_fu_254_p2 = (indvar_flatten21_reg_183 + 5'd1); + +assign add_ln147_fu_310_p2 = (ap_phi_mux_ii_phi_fu_198_p4 + 2'd1); + +assign add_ln148_6_fu_474_p2 = (indvar_flatten_reg_205 + 4'd1); + +assign add_ln148_fu_412_p2 = (select_ln147_fu_322_p3 + 2'd1); + +assign add_ln149_fu_468_p2 = (select_ln148_fu_424_p3 + 2'd1); + +assign add_ln150_6_fu_462_p2 = (select_ln147_23_fu_386_p3 + zext_ln150_14_fu_458_p1); + +assign add_ln150_fu_286_p2 = (sub_ln150_fu_276_p2 + zext_ln150_8_fu_282_p1); + +assign and_ln147_fu_406_p2 = (xor_ln147_fu_394_p2 & icmp_ln149_fu_400_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign empty_135_fu_354_p2 = (tmp_168_cast_fu_350_p1 - select_ln147_27_cast_fu_338_p1); + +assign empty_136_fu_444_p2 = ((sext_ln150_fu_360_p1) + (select_ln148_21_cast_fu_440_p1)); + +assign empty_137_fu_450_p1 = empty_136_fu_444_p2[4:0]; + +assign empty_138_fu_454_p1 = empty_136_fu_444_p2[2:0]; + +assign empty_139_fu_511_p2 = (p_shl_cast_fu_504_p3 - empty_137_reg_609); + +assign empty_140_fu_536_p2 = (empty_139_fu_511_p2 + select_ln148_cast_fu_533_p1); + +assign icmp_ln147_fu_304_p2 = ((indvar_flatten21_reg_183 == 5'd27) ? 1'b1 : 1'b0); + +assign icmp_ln148_fu_316_p2 = ((indvar_flatten_reg_205 == 4'd9) ? 1'b1 : 1'b0); + +assign icmp_ln149_fu_400_p2 = ((ic_reg_227 == 2'd3) ? 1'b1 : 1'b0); + +assign idxprom30_fu_557_p1 = p_reg_660_pp0_iter7_reg; + +assign ifmap_vec_address0 = p_cast63_fu_542_p1; + +assign or_ln148_fu_418_p2 = (icmp_ln148_fu_316_p2 | and_ln147_fu_406_p2); + +assign p_cast63_fu_542_p1 = empty_140_fu_536_p2; + +assign p_fu_551_p2 = (select_ln148_17_fu_526_p3 + select_ln148_cast_fu_533_p1); + +assign p_shl_cast_fu_504_p3 = {{empty_138_reg_614}, {2'd0}}; + +assign products_0_address0 = idxprom30_fu_557_p1; + +assign products_0_d0 = mul_reg_693; + +assign products_1_address0 = idxprom30_fu_557_p1; + +assign products_1_d0 = mul_1_reg_698; + +assign products_2_address0 = idxprom30_fu_557_p1; + +assign products_2_d0 = mul_2_reg_703; + +assign products_3_address0 = idxprom30_fu_557_p1; + +assign products_3_d0 = mul_3_reg_708; + +assign select_ln147_22_fu_330_p3 = ((icmp_ln148_fu_316_p2[0:0] == 1'b1) ? add_ln147_fu_310_p2 : ap_phi_mux_ii_phi_fu_198_p4); + +assign select_ln147_23_fu_386_p3 = ((icmp_ln148_fu_316_p2[0:0] == 1'b1) ? sub_ln150_6_fu_380_p2 : sub_ln150_fu_276_p2); + +assign select_ln147_24_fu_498_p3 = ((icmp_ln148_reg_578[0:0] == 1'b1) ? sub_ln150_7_fu_493_p2 : sub_ln150_1_reg_569); + +assign select_ln147_27_cast_fu_338_p1 = select_ln147_22_fu_330_p3; + +assign select_ln147_fu_322_p3 = ((icmp_ln148_fu_316_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_220_p4); + +assign select_ln148_16_fu_432_p3 = ((and_ln147_fu_406_p2[0:0] == 1'b1) ? add_ln148_fu_412_p2 : select_ln147_fu_322_p3); + +assign select_ln148_17_fu_526_p3 = ((and_ln147_reg_594[0:0] == 1'b1) ? sub_ln150_8_fu_521_p2 : select_ln147_24_fu_498_p3); + +assign select_ln148_18_fu_480_p3 = ((icmp_ln148_fu_316_p2[0:0] == 1'b1) ? 4'd1 : add_ln148_6_fu_474_p2); + +assign select_ln148_21_cast_fu_440_p1 = select_ln148_16_fu_432_p3; + +assign select_ln148_cast_fu_533_p1 = select_ln148_reg_599; + +assign select_ln148_fu_424_p3 = ((or_ln148_fu_418_p2[0:0] == 1'b1) ? 2'd0 : ic_reg_227); + +assign sext_ln150_fu_360_p1 = (empty_135_fu_354_p2); + +assign shl_ln150_1_fu_488_p2 = sub_ln150_6_reg_588 << 5'd2; + +assign shl_ln150_2_fu_516_p2 = add_ln150_6_reg_619 << 5'd2; + +assign shl_ln150_fu_292_p2 = add_ln150_fu_286_p2 << 5'd2; + +assign shl_ln150_mid1_fu_368_p3 = {{add_ln147_fu_310_p2}, {2'd0}}; + +assign shl_ln_fu_264_p3 = {{ap_phi_mux_ii_phi_fu_198_p4}, {2'd0}}; + +assign sub_ln150_1_fu_298_p2 = (shl_ln150_fu_292_p2 - add_ln150_fu_286_p2); + +assign sub_ln150_6_fu_380_p2 = (zext_ln150_13_fu_376_p1 - zext_ln150_12_fu_364_p1); + +assign sub_ln150_7_fu_493_p2 = (shl_ln150_1_fu_488_p2 - sub_ln150_6_reg_588); + +assign sub_ln150_8_fu_521_p2 = (shl_ln150_2_fu_516_p2 - add_ln150_6_reg_619); + +assign sub_ln150_fu_276_p2 = (zext_ln150_7_fu_272_p1 - zext_ln150_fu_260_p1); + +assign tmp_168_cast_fu_350_p1 = tmp_s_fu_342_p3; + +assign tmp_s_fu_342_p3 = {{select_ln147_22_fu_330_p3}, {2'd0}}; + +assign weight_vecs_0_address0 = p_cast63_fu_542_p1; + +assign weight_vecs_1_address0 = p_cast63_fu_542_p1; + +assign weight_vecs_2_address0 = p_cast63_fu_542_p1; + +assign weight_vecs_3_address0 = p_cast63_fu_542_p1; + +assign xor_ln147_fu_394_p2 = (icmp_ln148_fu_316_p2 ^ 1'd1); + +assign zext_ln150_12_fu_364_p1 = add_ln147_fu_310_p2; + +assign zext_ln150_13_fu_376_p1 = shl_ln150_mid1_fu_368_p3; + +assign zext_ln150_14_fu_458_p1 = add_ln148_fu_412_p2; + +assign zext_ln150_7_fu_272_p1 = shl_ln_fu_264_p3; + +assign zext_ln150_8_fu_282_p1 = ap_phi_mux_jj_phi_fu_220_p4; + +assign zext_ln150_fu_260_p1 = ap_phi_mux_ii_phi_fu_198_p4; + +endmodule //td_fused_top_tdf1_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf1_filters_0_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 7; +parameter MEM_SIZE = 108; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf1_filters_0( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd108; +parameter AddressWidth = 32'd7; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf1_filters_0_ram td_fused_top_tdf1_filters_0_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + module td_fused_top_tdf1_filters_1_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 7; +parameter MEM_SIZE = 108; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf1_filters_1_rom.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf1_filters_1( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd108; +parameter AddressWidth = 32'd7; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +td_fused_top_tdf1_filters_1_rom td_fused_top_tdf1_filters_1_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + input_indices_2_out_din, + input_indices_2_out_full_n, + input_indices_2_out_write, + input_indices_2_out1_din, + input_indices_2_out1_full_n, + input_indices_2_out1_write, + output_indices_0_din, + output_indices_0_full_n, + output_indices_0_write, + output_indices_1_din, + output_indices_1_full_n, + output_indices_1_write, + resetMaximum_din, + resetMaximum_full_n, + resetMaximum_write, + storeOutput_din, + storeOutput_full_n, + storeOutput_write, + ap_return_0, + ap_return_1 +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [1:0] input_indices_2_out_din; +input input_indices_2_out_full_n; +output input_indices_2_out_write; +output [3:0] input_indices_2_out1_din; +input input_indices_2_out1_full_n; +output input_indices_2_out1_write; +output [6:0] output_indices_0_din; +input output_indices_0_full_n; +output output_indices_0_write; +output [13:0] output_indices_1_din; +input output_indices_1_full_n; +output output_indices_1_write; +output resetMaximum_din; +input resetMaximum_full_n; +output resetMaximum_write; +output storeOutput_din; +input storeOutput_full_n; +output storeOutput_write; +output [15:0] ap_return_0; +output [15:0] ap_return_1; + +reg ap_done; +reg ap_idle; +reg start_write; +reg input_indices_2_out_write; +reg input_indices_2_out1_write; +reg output_indices_0_write; +reg output_indices_1_write; +reg resetMaximum_write; +reg storeOutput_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [1:0] i_p_3; +reg [1:0] j_p_3; +reg [15:0] i_7; +reg [15:0] j_7; +reg [15:0] k_7; +reg [15:0] i_out_3; +reg [15:0] j_out_3; +reg input_indices_2_out_blk_n; +reg input_indices_2_out1_blk_n; +reg output_indices_0_blk_n; +reg output_indices_1_blk_n; +reg resetMaximum_blk_n; +reg storeOutput_blk_n; +wire [1:0] select_ln195_fu_344_p3; +reg ap_block_state1; +wire [0:0] or_ln195_fu_318_p2; +wire [1:0] select_ln195_1_fu_352_p3; +wire [15:0] select_ln200_fu_284_p3; +wire [0:0] and_ln195_1_fu_312_p2; +wire [15:0] select_ln195_2_fu_366_p3; +wire [0:0] and_ln185_fu_360_p2; +wire [15:0] select_ln195_3_fu_394_p3; +wire [0:0] and_ln188_fu_300_p2; +wire [15:0] select_ln200_1_fu_292_p3; +wire [15:0] select_ln195_4_fu_402_p3; +wire [1:0] or_ln177_fu_128_p2; +wire [0:0] icmp_ln178_fu_141_p2; +wire [0:0] icmp_ln178_1_fu_147_p2; +wire [15:0] zext_ln179_fu_116_p1; +wire [15:0] zext_ln180_fu_124_p1; +wire [1:0] add_ln184_fu_212_p2; +wire [1:0] add_ln187_fu_224_p2; +wire [15:0] add_ln190_fu_236_p2; +wire [15:0] add_ln194_fu_254_p2; +wire [15:0] add_ln199_fu_272_p2; +wire [0:0] icmp_ln200_fu_278_p2; +wire [15:0] add_ln198_fu_266_p2; +wire [0:0] icmp_ln185_fu_218_p2; +wire [0:0] icmp_ln188_fu_230_p2; +wire [0:0] icmp_ln191_fu_242_p2; +wire [0:0] icmp_ln195_fu_260_p2; +wire [0:0] and_ln195_fu_306_p2; +wire [0:0] xor_ln188_fu_324_p2; +wire [0:0] and_ln188_1_fu_330_p2; +wire [1:0] select_ln188_fu_336_p3; +wire [15:0] add_ln193_fu_248_p2; +wire [0:0] xor_ln191_fu_374_p2; +wire [0:0] and_ln191_fu_380_p2; +wire [15:0] select_ln191_fu_386_p3; +wire [15:0] add_ln179_fu_164_p2; +wire [15:0] add_ln180_fu_174_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_p_3 = 2'd0; +#0 j_p_3 = 2'd0; +#0 i_7 = 16'd0; +#0 j_7 = 16'd0; +#0 k_7 = 16'd0; +#0 i_out_3 = 16'd0; +#0 j_out_3 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln195_1_fu_312_p2))) begin + i_7 <= select_ln200_fu_284_p3; + i_out_3 <= select_ln200_1_fu_292_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (or_ln195_fu_318_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_p_3 <= select_ln195_fu_344_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln185_fu_360_p2))) begin + j_7 <= select_ln195_2_fu_366_p3; + j_out_3 <= select_ln195_4_fu_402_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + j_p_3 <= select_ln195_1_fu_352_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln188_fu_300_p2))) begin + k_7 <= select_ln195_3_fu_394_p3; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_blk_n = input_indices_2_out1_full_n; + end else begin + input_indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_write = 1'b1; + end else begin + input_indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_blk_n = input_indices_2_out_full_n; + end else begin + input_indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_write = 1'b1; + end else begin + input_indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_blk_n = output_indices_0_full_n; + end else begin + output_indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_write = 1'b1; + end else begin + output_indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_blk_n = output_indices_1_full_n; + end else begin + output_indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_write = 1'b1; + end else begin + output_indices_1_write = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_blk_n = resetMaximum_full_n; + end else begin + resetMaximum_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_write = 1'b1; + end else begin + resetMaximum_write = 1'b0; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_blk_n = storeOutput_full_n; + end else begin + storeOutput_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_write = 1'b1; + end else begin + storeOutput_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln179_fu_164_p2 = (i_7 + zext_ln179_fu_116_p1); + +assign add_ln180_fu_174_p2 = (j_7 + zext_ln180_fu_124_p1); + +assign add_ln184_fu_212_p2 = (j_p_3 + 2'd1); + +assign add_ln187_fu_224_p2 = (i_p_3 + 2'd1); + +assign add_ln190_fu_236_p2 = (k_7 + 16'd1); + +assign add_ln193_fu_248_p2 = (j_7 + 16'd2); + +assign add_ln194_fu_254_p2 = (j_out_3 + 16'd1); + +assign add_ln198_fu_266_p2 = (i_7 + 16'd2); + +assign add_ln199_fu_272_p2 = (i_out_3 + 16'd1); + +assign and_ln185_fu_360_p2 = (icmp_ln191_fu_242_p2 & and_ln188_fu_300_p2); + +assign and_ln188_1_fu_330_p2 = (xor_ln188_fu_324_p2 & icmp_ln185_fu_218_p2); + +assign and_ln188_fu_300_p2 = (icmp_ln188_fu_230_p2 & icmp_ln185_fu_218_p2); + +assign and_ln191_fu_380_p2 = (xor_ln191_fu_374_p2 & and_ln188_fu_300_p2); + +assign and_ln195_1_fu_312_p2 = (and_ln195_fu_306_p2 & and_ln188_fu_300_p2); + +assign and_ln195_fu_306_p2 = (icmp_ln195_fu_260_p2 & icmp_ln191_fu_242_p2); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign ap_return_0 = add_ln179_fu_164_p2; + +assign ap_return_1 = add_ln180_fu_174_p2; + +assign icmp_ln178_1_fu_147_p2 = ((j_p_3 == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln178_fu_141_p2 = ((i_p_3 == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln185_fu_218_p2 = ((add_ln184_fu_212_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln188_fu_230_p2 = ((add_ln187_fu_224_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln191_fu_242_p2 = ((add_ln190_fu_236_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign icmp_ln195_fu_260_p2 = ((add_ln194_fu_254_p2 == 16'd112) ? 1'b1 : 1'b0); + +assign icmp_ln200_fu_278_p2 = ((add_ln199_fu_272_p2 == 16'd112) ? 1'b1 : 1'b0); + +assign input_indices_2_out1_din = k_7[3:0]; + +assign input_indices_2_out_din = k_7[1:0]; + +assign or_ln177_fu_128_p2 = (j_p_3 | i_p_3); + +assign or_ln195_fu_318_p2 = (icmp_ln185_fu_218_p2 | and_ln195_1_fu_312_p2); + +assign output_indices_0_din = i_out_3[6:0]; + +assign output_indices_1_din = j_out_3[13:0]; + +assign resetMaximum_din = ((or_ln177_fu_128_p2 == 2'd0) ? 1'b1 : 1'b0); + +assign select_ln188_fu_336_p3 = ((and_ln188_1_fu_330_p2[0:0] == 1'b1) ? add_ln187_fu_224_p2 : 2'd0); + +assign select_ln191_fu_386_p3 = ((and_ln191_fu_380_p2[0:0] == 1'b1) ? add_ln190_fu_236_p2 : 16'd0); + +assign select_ln195_1_fu_352_p3 = ((or_ln195_fu_318_p2[0:0] == 1'b1) ? 2'd0 : add_ln184_fu_212_p2); + +assign select_ln195_2_fu_366_p3 = ((and_ln195_1_fu_312_p2[0:0] == 1'b1) ? 16'd0 : add_ln193_fu_248_p2); + +assign select_ln195_3_fu_394_p3 = ((and_ln195_1_fu_312_p2[0:0] == 1'b1) ? 16'd0 : select_ln191_fu_386_p3); + +assign select_ln195_4_fu_402_p3 = ((and_ln195_1_fu_312_p2[0:0] == 1'b1) ? 16'd0 : add_ln194_fu_254_p2); + +assign select_ln195_fu_344_p3 = ((and_ln195_1_fu_312_p2[0:0] == 1'b1) ? 2'd0 : select_ln188_fu_336_p3); + +assign select_ln200_1_fu_292_p3 = ((icmp_ln200_fu_278_p2[0:0] == 1'b1) ? 16'd0 : add_ln199_fu_272_p2); + +assign select_ln200_fu_284_p3 = ((icmp_ln200_fu_278_p2[0:0] == 1'b1) ? 16'd0 : add_ln198_fu_266_p2); + +assign start_out = real_start; + +assign storeOutput_din = (icmp_ln178_fu_141_p2 & icmp_ln178_1_fu_147_p2); + +assign xor_ln188_fu_324_p2 = (icmp_ln188_fu_230_p2 ^ 1'd1); + +assign xor_ln191_fu_374_p2 = (icmp_ln191_fu_242_p2 ^ 1'd1); + +assign zext_ln179_fu_116_p1 = i_p_3; + +assign zext_ln180_fu_124_p1 = j_p_3; + +endmodule //td_fused_top_tdf1_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_poolOutputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + output_indices_04_dout, + output_indices_04_empty_n, + output_indices_04_read, + output_indices_15_dout, + output_indices_15_empty_n, + output_indices_15_read, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + resetMaximum6_dout, + resetMaximum6_empty_n, + resetMaximum6_read, + storeOutput7_dout, + storeOutput7_empty_n, + storeOutput7_read, + outputs_0_read, + outputs_1_read, + outputs_2_read, + outputs_3_read, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_state3 = 4'd4; +parameter ap_ST_fsm_state4 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [6:0] output_indices_04_dout; +input output_indices_04_empty_n; +output output_indices_04_read; +input [13:0] output_indices_15_dout; +input output_indices_15_empty_n; +output output_indices_15_read; +input [3:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +input [0:0] resetMaximum6_dout; +input resetMaximum6_empty_n; +output resetMaximum6_read; +input [0:0] storeOutput7_dout; +input storeOutput7_empty_n; +output storeOutput7_read; +input [15:0] outputs_0_read; +input [15:0] outputs_1_read; +input [15:0] outputs_2_read; +input [15:0] outputs_3_read; +output [15:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg output_indices_04_read; +reg output_indices_15_read; +reg input_indices_23_read; +reg resetMaximum6_read; +reg storeOutput7_read; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] max_vals_3_0; +reg [15:0] max_vals_3_1; +reg [15:0] max_vals_3_2; +reg [15:0] max_vals_3_3; +reg output_indices_04_blk_n; +wire ap_CS_fsm_state2; +reg output_indices_15_blk_n; +reg input_indices_23_blk_n; +reg resetMaximum6_blk_n; +reg storeOutput7_blk_n; +reg [6:0] output_indices_04_read_reg_281; +reg [13:0] output_indices_15_read_reg_286; +reg [3:0] input_indices_23_read_reg_291; +wire [0:0] storeOutput7_read_read_fu_110_p2; +reg [0:0] storeOutput7_read_reg_296; +wire grp_tdf1_writeOutputs_aligned_fu_116_ap_start; +wire grp_tdf1_writeOutputs_aligned_fu_116_ap_done; +wire grp_tdf1_writeOutputs_aligned_fu_116_ap_idle; +wire grp_tdf1_writeOutputs_aligned_fu_116_ap_ready; +wire [15:0] grp_tdf1_writeOutputs_aligned_fu_116_out_data_address1; +wire grp_tdf1_writeOutputs_aligned_fu_116_out_data_ce1; +wire grp_tdf1_writeOutputs_aligned_fu_116_out_data_we1; +wire [63:0] grp_tdf1_writeOutputs_aligned_fu_116_out_data_d1; +reg grp_tdf1_writeOutputs_aligned_fu_116_ap_start_reg; +wire ap_CS_fsm_state3; +wire ap_CS_fsm_state4; +wire [15:0] select_ln24_fu_179_p3; +reg ap_block_state2; +wire [15:0] select_ln24_10_fu_197_p3; +wire [15:0] select_ln24_11_fu_215_p3; +wire [15:0] select_ln24_12_fu_233_p3; +reg ap_block_state1; +wire [0:0] grp_fu_133_p2; +wire [0:0] or_ln24_fu_173_p2; +wire [0:0] grp_fu_138_p2; +wire [0:0] or_ln24_10_fu_191_p2; +wire [0:0] grp_fu_143_p2; +wire [0:0] or_ln24_11_fu_209_p2; +wire [0:0] grp_fu_148_p2; +wire [0:0] or_ln24_12_fu_227_p2; +reg grp_fu_133_ce; +reg grp_fu_138_ce; +reg grp_fu_143_ce; +reg grp_fu_148_ce; +reg ap_block_state4_on_subcall_done; +reg [3:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 max_vals_3_0 = 16'd0; +#0 max_vals_3_1 = 16'd0; +#0 max_vals_3_2 = 16'd0; +#0 max_vals_3_3 = 16'd0; +#0 grp_tdf1_writeOutputs_aligned_fu_116_ap_start_reg = 1'b0; +end + +td_fused_top_tdf1_writeOutputs_aligned grp_tdf1_writeOutputs_aligned_fu_116( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(grp_tdf1_writeOutputs_aligned_fu_116_ap_start), + .ap_done(grp_tdf1_writeOutputs_aligned_fu_116_ap_done), + .ap_idle(grp_tdf1_writeOutputs_aligned_fu_116_ap_idle), + .ap_ready(grp_tdf1_writeOutputs_aligned_fu_116_ap_ready), + .i(output_indices_04_read_reg_281), + .j(output_indices_15_read_reg_286), + .k(input_indices_23_read_reg_291), + .out_data_address1(grp_tdf1_writeOutputs_aligned_fu_116_out_data_address1), + .out_data_ce1(grp_tdf1_writeOutputs_aligned_fu_116_out_data_ce1), + .out_data_we1(grp_tdf1_writeOutputs_aligned_fu_116_out_data_we1), + .out_data_d1(grp_tdf1_writeOutputs_aligned_fu_116_out_data_d1), + .max_vals_3_0(max_vals_3_0), + .max_vals_3_1(max_vals_3_1), + .max_vals_3_2(max_vals_3_2), + .max_vals_3_3(max_vals_3_3) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U137( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_133_ce), + .din0(max_vals_3_0), + .din1(outputs_0_read), + .opcode(5'd4), + .dout(grp_fu_133_p2) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U138( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_138_ce), + .din0(max_vals_3_1), + .din1(outputs_1_read), + .opcode(5'd4), + .dout(grp_fu_138_p2) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U139( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_143_ce), + .din0(max_vals_3_2), + .din1(outputs_2_read), + .opcode(5'd4), + .dout(grp_fu_143_p2) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U140( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_148_ce), + .din0(max_vals_3_3), + .din1(outputs_3_read), + .opcode(5'd4), + .dout(grp_fu_148_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + grp_tdf1_writeOutputs_aligned_fu_116_ap_start_reg <= 1'b0; + end else begin + if ((1'b1 == ap_CS_fsm_state3)) begin + grp_tdf1_writeOutputs_aligned_fu_116_ap_start_reg <= 1'b1; + end else if ((grp_tdf1_writeOutputs_aligned_fu_116_ap_ready == 1'b1)) begin + grp_tdf1_writeOutputs_aligned_fu_116_ap_start_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + input_indices_23_read_reg_291 <= input_indices_23_dout; + output_indices_04_read_reg_281 <= output_indices_04_dout; + output_indices_15_read_reg_286 <= output_indices_15_dout; + storeOutput7_read_reg_296 <= storeOutput7_dout; + end +end + +always @ (posedge ap_clk) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + max_vals_3_0 <= select_ln24_fu_179_p3; + max_vals_3_1 <= select_ln24_10_fu_197_p3; + max_vals_3_2 <= select_ln24_11_fu_215_p3; + max_vals_3_3 <= select_ln24_12_fu_233_p3; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_133_ce = 1'b1; + end else begin + grp_fu_133_ce = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_138_ce = 1'b1; + end else begin + grp_fu_138_ce = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_143_ce = 1'b1; + end else begin + grp_fu_143_ce = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_148_ce = 1'b1; + end else begin + grp_fu_148_ce = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_04_blk_n = output_indices_04_empty_n; + end else begin + output_indices_04_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_04_read = 1'b1; + end else begin + output_indices_04_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_15_blk_n = output_indices_15_empty_n; + end else begin + output_indices_15_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_15_read = 1'b1; + end else begin + output_indices_15_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + resetMaximum6_blk_n = resetMaximum6_empty_n; + end else begin + resetMaximum6_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + resetMaximum6_read = 1'b1; + end else begin + resetMaximum6_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + storeOutput7_blk_n = storeOutput7_empty_n; + end else begin + storeOutput7_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + storeOutput7_read = 1'b1; + end else begin + storeOutput7_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_110_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_110_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state3; + end else begin + ap_NS_fsm = ap_ST_fsm_state2; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +always @ (*) begin + ap_block_state2 = ((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)); +end + +always @ (*) begin + ap_block_state4_on_subcall_done = ((grp_tdf1_writeOutputs_aligned_fu_116_ap_done == 1'b0) & (storeOutput7_read_reg_296 == 1'd1)); +end + +assign grp_tdf1_writeOutputs_aligned_fu_116_ap_start = grp_tdf1_writeOutputs_aligned_fu_116_ap_start_reg; + +assign or_ln24_10_fu_191_p2 = (resetMaximum6_dout | grp_fu_138_p2); + +assign or_ln24_11_fu_209_p2 = (resetMaximum6_dout | grp_fu_143_p2); + +assign or_ln24_12_fu_227_p2 = (resetMaximum6_dout | grp_fu_148_p2); + +assign or_ln24_fu_173_p2 = (resetMaximum6_dout | grp_fu_133_p2); + +assign out_data_address1 = grp_tdf1_writeOutputs_aligned_fu_116_out_data_address1; + +assign out_data_ce1 = grp_tdf1_writeOutputs_aligned_fu_116_out_data_ce1; + +assign out_data_d1 = grp_tdf1_writeOutputs_aligned_fu_116_out_data_d1; + +assign out_data_we1 = grp_tdf1_writeOutputs_aligned_fu_116_out_data_we1; + +assign select_ln24_10_fu_197_p3 = ((or_ln24_10_fu_191_p2[0:0] == 1'b1) ? outputs_1_read : max_vals_3_1); + +assign select_ln24_11_fu_215_p3 = ((or_ln24_11_fu_209_p2[0:0] == 1'b1) ? outputs_2_read : max_vals_3_2); + +assign select_ln24_12_fu_233_p3 = ((or_ln24_12_fu_227_p2[0:0] == 1'b1) ? outputs_3_read : max_vals_3_3); + +assign select_ln24_fu_179_p3 = ((or_ln24_fu_173_p2[0:0] == 1'b1) ? outputs_0_read : max_vals_3_0); + +assign storeOutput7_read_read_fu_110_p2 = storeOutput7_dout; + +endmodule //td_fused_top_tdf1_poolOutputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_readFilters18 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_0_address0, + filter_data_0_ce0, + filter_data_0_q0, + filter_data_1_address0, + filter_data_1_ce0, + filter_data_1_q0, + filter_data_2_address0, + filter_data_2_ce0, + filter_data_2_q0, + filter_data_3_address0, + filter_data_3_ce0, + filter_data_3_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_we0, + weight_vecs_0_d0, + weight_vecs_1_address0, + weight_vecs_1_ce0, + weight_vecs_1_we0, + weight_vecs_1_d0, + weight_vecs_2_address0, + weight_vecs_2_ce0, + weight_vecs_2_we0, + weight_vecs_2_d0, + weight_vecs_3_address0, + weight_vecs_3_ce0, + weight_vecs_3_we0, + weight_vecs_3_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state6 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [6:0] filter_data_0_address0; +output filter_data_0_ce0; +input [15:0] filter_data_0_q0; +output [6:0] filter_data_1_address0; +output filter_data_1_ce0; +input [15:0] filter_data_1_q0; +output [6:0] filter_data_2_address0; +output filter_data_2_ce0; +input [15:0] filter_data_2_q0; +output [6:0] filter_data_3_address0; +output filter_data_3_ce0; +input [15:0] filter_data_3_q0; +input [1:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [4:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +output weight_vecs_0_we0; +output [15:0] weight_vecs_0_d0; +output [4:0] weight_vecs_1_address0; +output weight_vecs_1_ce0; +output weight_vecs_1_we0; +output [15:0] weight_vecs_1_d0; +output [4:0] weight_vecs_2_address0; +output weight_vecs_2_ce0; +output weight_vecs_2_we0; +output [15:0] weight_vecs_2_d0; +output [4:0] weight_vecs_3_address0; +output weight_vecs_3_ce0; +output weight_vecs_3_we0; +output [15:0] weight_vecs_3_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_0_ce0; +reg filter_data_1_ce0; +reg filter_data_2_ce0; +reg filter_data_3_ce0; +reg input_indices_23_read; +reg weight_vecs_0_ce0; +reg weight_vecs_0_we0; +reg weight_vecs_1_ce0; +reg weight_vecs_1_we0; +reg weight_vecs_2_ce0; +reg weight_vecs_2_we0; +reg weight_vecs_3_ce0; +reg weight_vecs_3_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +reg [4:0] indvar_flatten13_reg_210; +reg [3:0] indvar_flatten_reg_221; +reg [1:0] ii_reg_232; +reg [1:0] jj_reg_243; +reg [1:0] kk_reg_254; +wire [5:0] sext_ln47_fu_287_p1; +reg [5:0] sext_ln47_reg_602; +wire [4:0] add_ln47_6_fu_291_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln47_fu_297_p2; +reg [0:0] icmp_ln47_reg_612; +reg [0:0] icmp_ln47_reg_612_pp0_iter1_reg; +reg [0:0] icmp_ln47_reg_612_pp0_iter2_reg; +wire [0:0] icmp_ln48_fu_303_p2; +reg [0:0] icmp_ln48_reg_616; +wire [3:0] select_ln48_12_fu_315_p3; +wire [1:0] select_ln47_11_fu_336_p3; +reg [1:0] select_ln47_11_reg_629; +reg ap_enable_reg_pp0_iter1; +wire [1:0] select_ln48_fu_402_p3; +reg [1:0] select_ln48_reg_636; +wire [1:0] select_ln48_11_fu_410_p3; +reg [1:0] select_ln48_11_reg_642; +wire [6:0] trunc_ln55_fu_428_p1; +reg [6:0] trunc_ln55_reg_648; +wire [4:0] trunc_ln55_16_fu_432_p1; +reg [4:0] trunc_ln55_16_reg_653; +wire [1:0] add_ln49_fu_436_p2; +wire [4:0] add_ln55_14_fu_529_p2; +reg [4:0] add_ln55_14_reg_683; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg [1:0] ap_phi_mux_ii_phi_fu_236_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_247_p4; +wire [63:0] zext_ln55_42_fu_521_p1; +wire [63:0] zext_ln55_43_fu_535_p1; +wire [15:0] tmp_fu_542_p6; +wire [15:0] tmp_s_fu_557_p6; +wire [15:0] tmp_5_fu_572_p6; +wire [15:0] tmp_6_fu_587_p6; +wire [3:0] tmp_52_fu_269_p3; +wire [4:0] zext_ln55_34_fu_277_p1; +wire [4:0] zext_ln55_fu_265_p1; +wire [4:0] sub_ln55_fu_281_p2; +wire [3:0] add_ln48_6_fu_309_p2; +wire [1:0] add_ln47_fu_323_p2; +wire [5:0] zext_ln55_36_fu_343_p1; +wire [5:0] add_ln55_fu_347_p2; +wire [7:0] tmp_77_fu_356_p3; +wire [61:0] sext_ln55_11_fu_364_p1; +wire [61:0] sext_ln55_fu_352_p1; +wire [0:0] icmp_ln49_fu_379_p2; +wire [0:0] xor_ln47_fu_374_p2; +wire [1:0] select_ln47_fu_329_p3; +wire [0:0] and_ln47_fu_385_p2; +wire [0:0] or_ln48_fu_397_p2; +wire [1:0] add_ln48_fu_391_p2; +wire [61:0] sub_ln55_11_fu_368_p2; +wire [61:0] zext_ln55_39_fu_418_p1; +wire [61:0] add_ln55_11_fu_422_p2; +wire [3:0] tmp_53_fu_445_p3; +wire [4:0] zext_ln55_37_fu_452_p1; +wire [4:0] zext_ln55_35_fu_442_p1; +wire [4:0] sub_ln55_12_fu_456_p2; +wire [6:0] p_shl2_cast_fu_469_p3; +wire [5:0] sext_ln48_fu_462_p1; +wire [5:0] zext_ln55_38_fu_466_p1; +wire [5:0] add_ln55_12_fu_481_p2; +wire [2:0] trunc_ln55_18_fu_491_p1; +wire [4:0] p_shl1_cast_fu_495_p3; +wire [4:0] trunc_ln55_17_fu_487_p1; +wire [6:0] sub_ln55_13_fu_476_p2; +wire [6:0] zext_ln55_41_fu_512_p1; +wire [6:0] add_ln55_13_fu_515_p2; +wire [4:0] sub_ln55_14_fu_503_p2; +wire [4:0] zext_ln55_40_fu_509_p1; +wire ap_CS_fsm_state6; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +end + +td_fused_top_mux_416_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 16 )) +mux_416_16_1_1_U17( + .din0(filter_data_0_q0), + .din1(16'd0), + .din2(16'd0), + .din3(16'd0), + .din4(16'd0), + .dout(tmp_fu_542_p6) +); + +td_fused_top_mux_416_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 16 )) +mux_416_16_1_1_U18( + .din0(filter_data_1_q0), + .din1(16'd0), + .din2(16'd0), + .din3(16'd0), + .din4(16'd0), + .dout(tmp_s_fu_557_p6) +); + +td_fused_top_mux_416_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 16 )) +mux_416_16_1_1_U19( + .din0(filter_data_2_q0), + .din1(16'd0), + .din2(16'd0), + .din3(16'd0), + .din4(16'd0), + .dout(tmp_5_fu_572_p6) +); + +td_fused_top_mux_416_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 16 )) +mux_416_16_1_1_U20( + .din0(filter_data_3_q0), + .din1(16'd0), + .din2(16'd0), + .din3(16'd0), + .din4(16'd0), + .dout(tmp_6_fu_587_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_612_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_232 <= select_ln47_11_reg_629; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_232 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_297_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten13_reg_210 <= add_ln47_6_fu_291_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_210 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_297_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten_reg_221 <= select_ln48_12_fu_315_p3; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_221 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_612_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_243 <= select_ln48_11_reg_642; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_243 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_612 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + kk_reg_254 <= add_ln49_fu_436_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_254 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_612_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln55_14_reg_683 <= add_ln55_14_fu_529_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln47_reg_612 <= icmp_ln47_fu_297_p2; + icmp_ln47_reg_612_pp0_iter1_reg <= icmp_ln47_reg_612; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln47_reg_612_pp0_iter2_reg <= icmp_ln47_reg_612_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_297_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln48_reg_616 <= icmp_ln48_fu_303_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_612 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + select_ln47_11_reg_629 <= select_ln47_11_fu_336_p3; + select_ln48_11_reg_642 <= select_ln48_11_fu_410_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_612 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + select_ln48_reg_636 <= select_ln48_fu_402_p3; + trunc_ln55_16_reg_653 <= trunc_ln55_16_fu_432_p1; + trunc_ln55_reg_648 <= trunc_ln55_fu_428_p1; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sext_ln47_reg_602 <= sext_ln47_fu_287_p1; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_297_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_612_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_236_p4 = select_ln47_11_reg_629; + end else begin + ap_phi_mux_ii_phi_fu_236_p4 = ii_reg_232; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_612_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_247_p4 = select_ln48_11_reg_642; + end else begin + ap_phi_mux_jj_phi_fu_247_p4 = jj_reg_243; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_0_ce0 = 1'b1; + end else begin + filter_data_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_1_ce0 = 1'b1; + end else begin + filter_data_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_2_ce0 = 1'b1; + end else begin + filter_data_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_3_ce0 = 1'b1; + end else begin + filter_data_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_612_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_we0 = 1'b1; + end else begin + weight_vecs_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_ce0 = 1'b1; + end else begin + weight_vecs_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_612_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_we0 = 1'b1; + end else begin + weight_vecs_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_ce0 = 1'b1; + end else begin + weight_vecs_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_612_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_we0 = 1'b1; + end else begin + weight_vecs_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_ce0 = 1'b1; + end else begin + weight_vecs_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_612_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_we0 = 1'b1; + end else begin + weight_vecs_3_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0)) & ~((ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln47_6_fu_291_p2 = (indvar_flatten13_reg_210 + 5'd1); + +assign add_ln47_fu_323_p2 = (ap_phi_mux_ii_phi_fu_236_p4 + 2'd1); + +assign add_ln48_6_fu_309_p2 = (indvar_flatten_reg_221 + 4'd1); + +assign add_ln48_fu_391_p2 = (select_ln47_fu_329_p3 + 2'd1); + +assign add_ln49_fu_436_p2 = (select_ln48_fu_402_p3 + 2'd1); + +assign add_ln55_11_fu_422_p2 = (sub_ln55_11_fu_368_p2 + zext_ln55_39_fu_418_p1); + +assign add_ln55_12_fu_481_p2 = ((sext_ln48_fu_462_p1) + (zext_ln55_38_fu_466_p1)); + +assign add_ln55_13_fu_515_p2 = (sub_ln55_13_fu_476_p2 + zext_ln55_41_fu_512_p1); + +assign add_ln55_14_fu_529_p2 = (sub_ln55_14_fu_503_p2 + zext_ln55_40_fu_509_p1); + +assign add_ln55_fu_347_p2 = ((sext_ln47_reg_602) + (zext_ln55_36_fu_343_p1)); + +assign and_ln47_fu_385_p2 = (xor_ln47_fu_374_p2 & icmp_ln49_fu_379_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_0_address0 = zext_ln55_42_fu_521_p1; + +assign filter_data_1_address0 = zext_ln55_42_fu_521_p1; + +assign filter_data_2_address0 = zext_ln55_42_fu_521_p1; + +assign filter_data_3_address0 = zext_ln55_42_fu_521_p1; + +assign icmp_ln47_fu_297_p2 = ((indvar_flatten13_reg_210 == 5'd27) ? 1'b1 : 1'b0); + +assign icmp_ln48_fu_303_p2 = ((indvar_flatten_reg_221 == 4'd9) ? 1'b1 : 1'b0); + +assign icmp_ln49_fu_379_p2 = ((kk_reg_254 == 2'd3) ? 1'b1 : 1'b0); + +assign or_ln48_fu_397_p2 = (icmp_ln48_reg_616 | and_ln47_fu_385_p2); + +assign p_shl1_cast_fu_495_p3 = {{trunc_ln55_18_fu_491_p1}, {2'd0}}; + +assign p_shl2_cast_fu_469_p3 = {{trunc_ln55_16_reg_653}, {2'd0}}; + +assign select_ln47_11_fu_336_p3 = ((icmp_ln48_reg_616[0:0] == 1'b1) ? add_ln47_fu_323_p2 : ap_phi_mux_ii_phi_fu_236_p4); + +assign select_ln47_fu_329_p3 = ((icmp_ln48_reg_616[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_247_p4); + +assign select_ln48_11_fu_410_p3 = ((and_ln47_fu_385_p2[0:0] == 1'b1) ? add_ln48_fu_391_p2 : select_ln47_fu_329_p3); + +assign select_ln48_12_fu_315_p3 = ((icmp_ln48_fu_303_p2[0:0] == 1'b1) ? 4'd1 : add_ln48_6_fu_309_p2); + +assign select_ln48_fu_402_p3 = ((or_ln48_fu_397_p2[0:0] == 1'b1) ? 2'd0 : kk_reg_254); + +assign sext_ln47_fu_287_p1 = (sub_ln55_fu_281_p2); + +assign sext_ln48_fu_462_p1 = (sub_ln55_12_fu_456_p2); + +assign sext_ln55_11_fu_364_p1 = (tmp_77_fu_356_p3); + +assign sext_ln55_fu_352_p1 = add_ln55_fu_347_p2; + +assign sub_ln55_11_fu_368_p2 = ((sext_ln55_11_fu_364_p1) - (sext_ln55_fu_352_p1)); + +assign sub_ln55_12_fu_456_p2 = (zext_ln55_37_fu_452_p1 - zext_ln55_35_fu_442_p1); + +assign sub_ln55_13_fu_476_p2 = (p_shl2_cast_fu_469_p3 - trunc_ln55_reg_648); + +assign sub_ln55_14_fu_503_p2 = (p_shl1_cast_fu_495_p3 - trunc_ln55_17_fu_487_p1); + +assign sub_ln55_fu_281_p2 = (zext_ln55_34_fu_277_p1 - zext_ln55_fu_265_p1); + +assign tmp_52_fu_269_p3 = {{input_indices_23_dout}, {2'd0}}; + +assign tmp_53_fu_445_p3 = {{select_ln47_11_reg_629}, {2'd0}}; + +assign tmp_77_fu_356_p3 = {{add_ln55_fu_347_p2}, {2'd0}}; + +assign trunc_ln55_16_fu_432_p1 = add_ln55_11_fu_422_p2[4:0]; + +assign trunc_ln55_17_fu_487_p1 = add_ln55_12_fu_481_p2[4:0]; + +assign trunc_ln55_18_fu_491_p1 = add_ln55_12_fu_481_p2[2:0]; + +assign trunc_ln55_fu_428_p1 = add_ln55_11_fu_422_p2[6:0]; + +assign weight_vecs_0_address0 = zext_ln55_43_fu_535_p1; + +assign weight_vecs_0_d0 = tmp_fu_542_p6; + +assign weight_vecs_1_address0 = zext_ln55_43_fu_535_p1; + +assign weight_vecs_1_d0 = tmp_s_fu_557_p6; + +assign weight_vecs_2_address0 = zext_ln55_43_fu_535_p1; + +assign weight_vecs_2_d0 = tmp_5_fu_572_p6; + +assign weight_vecs_3_address0 = zext_ln55_43_fu_535_p1; + +assign weight_vecs_3_d0 = tmp_6_fu_587_p6; + +assign xor_ln47_fu_374_p2 = (icmp_ln48_reg_616 ^ 1'd1); + +assign zext_ln55_34_fu_277_p1 = tmp_52_fu_269_p3; + +assign zext_ln55_35_fu_442_p1 = select_ln47_11_reg_629; + +assign zext_ln55_36_fu_343_p1 = select_ln47_11_fu_336_p3; + +assign zext_ln55_37_fu_452_p1 = tmp_53_fu_445_p3; + +assign zext_ln55_38_fu_466_p1 = select_ln48_11_reg_642; + +assign zext_ln55_39_fu_418_p1 = select_ln48_11_fu_410_p3; + +assign zext_ln55_40_fu_509_p1 = select_ln48_reg_636; + +assign zext_ln55_41_fu_512_p1 = select_ln48_reg_636; + +assign zext_ln55_42_fu_521_p1 = add_ln55_13_fu_515_p2; + +assign zext_ln55_43_fu_535_p1 = add_ln55_14_reg_683; + +assign zext_ln55_fu_265_p1 = input_indices_23_dout; + +endmodule //td_fused_top_tdf1_readFilters18 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_readInputs19 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + i_19, + j_19, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_we0, + ifmap_vec_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state7 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] i_19; +input [15:0] j_19; +output [4:0] ifmap_vec_address0; +output ifmap_vec_ce0; +output ifmap_vec_we0; +output [15:0] ifmap_vec_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg ifmap_vec_ce0; +reg ifmap_vec_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [4:0] indvar_flatten52_reg_142; +reg [3:0] indvar_flatten_reg_153; +reg [1:0] jj_reg_164; +reg [1:0] kk_reg_176; +reg [1:0] ii_reg_187; +wire [17:0] p_cast_i_fu_216_p1; +reg [17:0] p_cast_i_reg_901; +wire [17:0] sext_ln22_fu_226_p1; +reg [17:0] sext_ln22_reg_907; +wire [7:0] p_cast_fu_230_p2; +reg [7:0] p_cast_reg_913; +wire [0:0] or_ln23_26_fu_250_p2; +reg [0:0] or_ln23_26_reg_919; +wire [15:0] p_mid140_fu_256_p2; +reg [15:0] p_mid140_reg_924; +wire [4:0] add_ln19_6_fu_262_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln19_fu_268_p2; +reg [0:0] icmp_ln19_reg_934; +reg [0:0] icmp_ln19_reg_934_pp0_iter1_reg; +reg [0:0] icmp_ln19_reg_934_pp0_iter2_reg; +reg [0:0] icmp_ln19_reg_934_pp0_iter3_reg; +wire [0:0] icmp_ln20_fu_274_p2; +reg [0:0] icmp_ln20_reg_938; +reg [0:0] icmp_ln20_reg_938_pp0_iter1_reg; +reg [0:0] icmp_ln20_reg_938_pp0_iter2_reg; +reg [0:0] icmp_ln20_reg_938_pp0_iter3_reg; +wire [0:0] and_ln19_fu_300_p2; +reg [0:0] and_ln19_reg_947; +reg [0:0] and_ln19_reg_947_pp0_iter1_reg; +reg [0:0] and_ln19_reg_947_pp0_iter2_reg; +reg [0:0] and_ln19_reg_947_pp0_iter3_reg; +wire [1:0] add_ln20_fu_306_p2; +reg [1:0] add_ln20_reg_953; +wire [1:0] select_ln20_fu_318_p3; +reg [1:0] select_ln20_reg_959; +reg [1:0] select_ln20_reg_959_pp0_iter1_reg; +reg [1:0] select_ln20_reg_959_pp0_iter2_reg; +wire [1:0] select_ln20_26_fu_326_p3; +reg [1:0] select_ln20_26_reg_965; +reg [1:0] select_ln20_26_reg_965_pp0_iter1_reg; +reg [1:0] select_ln20_26_reg_965_pp0_iter2_reg; +wire [1:0] add_ln25_fu_334_p2; +wire [3:0] select_ln20_29_fu_346_p3; +wire [7:0] p_cast1_i_fu_367_p2; +reg [7:0] p_cast1_i_reg_981; +wire [0:0] is_padding_fu_411_p2; +reg [0:0] is_padding_reg_987; +reg [0:0] is_padding_reg_987_pp0_iter2_reg; +reg [0:0] is_padding_reg_987_pp0_iter3_reg; +wire [15:0] empty_132_fu_427_p2; +reg [15:0] empty_132_reg_994; +wire [1:0] select_ln19_36_fu_438_p3; +reg [1:0] select_ln19_36_reg_999; +reg ap_enable_reg_pp0_iter1; +reg [1:0] select_ln19_36_reg_999_pp0_iter2_reg; +wire [7:0] p_cast1_i_mid1_fu_458_p2; +reg [7:0] p_cast1_i_mid1_reg_1006; +wire [0:0] or_ln23_28_fu_476_p2; +reg [0:0] or_ln23_28_reg_1012; +reg [0:0] or_ln23_28_reg_1012_pp0_iter2_reg; +reg [0:0] or_ln23_28_reg_1012_pp0_iter3_reg; +wire [0:0] or_ln23_30_fu_512_p2; +reg [0:0] or_ln23_30_reg_1019; +reg [0:0] or_ln23_30_reg_1019_pp0_iter2_reg; +reg [0:0] or_ln23_30_reg_1019_pp0_iter3_reg; +wire [15:0] p_mid1_fu_528_p2; +reg [15:0] p_mid1_reg_1026; +wire [4:0] add_ln33_1_fu_748_p2; +reg [4:0] add_ln33_1_reg_1036; +wire [6:0] sub_ln32_21_fu_833_p2; +reg [6:0] sub_ln32_21_reg_1041; +wire [63:0] lshr_ln32_fu_843_p2; +reg [63:0] lshr_ln32_reg_1046; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_condition_pp0_exit_iter2_state4; +reg ap_enable_reg_pp0_iter4; +reg [1:0] ap_phi_mux_jj_phi_fu_168_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_191_p4; +wire [63:0] zext_ln32_48_fu_685_p1; +wire [63:0] zext_ln33_15_fu_860_p1; +wire [16:0] zext_ln19_fu_202_p1; +wire [16:0] empty_129_fu_210_p2; +wire [16:0] j_cast_i_fu_198_p1; +wire [16:0] add_ln22_fu_220_p2; +wire [7:0] empty_fu_206_p1; +wire [0:0] tmp_fu_236_p3; +wire [0:0] icmp_ln24_fu_244_p2; +wire [0:0] icmp_ln25_fu_294_p2; +wire [0:0] xor_ln19_fu_288_p2; +wire [1:0] select_ln19_fu_280_p3; +wire [0:0] or_ln20_fu_312_p2; +wire [3:0] add_ln20_6_fu_340_p2; +wire [17:0] ii_cast_i_fu_354_p1; +wire [7:0] ii_cast_fu_358_p1; +wire [17:0] empty_130_fu_362_p2; +wire [17:0] zext_ln20_fu_378_p1; +wire [17:0] add_ln22_6_fu_386_p2; +wire [0:0] tmp_74_fu_391_p3; +wire [0:0] icmp_ln24_6_fu_399_p2; +wire [0:0] or_ln23_fu_405_p2; +wire [0:0] empty_131_fu_372_p2; +wire [2:0] zext_ln22_fu_382_p1; +wire [2:0] tmp2_fu_417_p2; +wire [15:0] tmp2_cast_fu_423_p1; +wire [1:0] add_ln19_fu_432_p2; +wire [17:0] ii_cast_i_mid1_fu_445_p1; +wire [7:0] ii_cast_mid1_fu_449_p1; +wire [17:0] p_mid114_fu_453_p2; +wire [0:0] p_mid116_fu_463_p2; +wire [17:0] zext_ln20_6_fu_481_p1; +wire [17:0] add_ln22_7_fu_487_p2; +wire [0:0] tmp_75_fu_492_p3; +wire [0:0] icmp_ln24_7_fu_500_p2; +wire [0:0] or_ln23_29_fu_506_p2; +wire [0:0] select_ln19_38_fu_469_p3; +wire [2:0] zext_ln22_6_fu_484_p1; +wire [2:0] tmp2_mid1_fu_518_p2; +wire [15:0] tmp2_cast_mid1_fu_524_p1; +wire [7:0] row_coord_int_fu_533_p3; +wire [12:0] tmp_45_fu_553_p3; +wire [15:0] tmp_s_fu_545_p3; +wire [15:0] zext_ln32_fu_561_p1; +wire [15:0] sub_ln32_fu_565_p2; +wire [15:0] col_coord_int_fu_539_p3; +wire [7:0] row_coord_int_mid134_fu_582_p3; +wire [12:0] tmp_48_fu_602_p3; +wire [15:0] tmp_47_fu_594_p3; +wire [15:0] zext_ln32_46_fu_610_p1; +wire [15:0] sub_ln32_1_fu_614_p2; +wire [15:0] col_coord_int_mid142_fu_588_p3; +wire [15:0] add_ln32_1_fu_620_p2; +wire [15:0] add_ln32_fu_571_p2; +wire [7:0] select_ln19_37_fu_577_p3; +wire [7:0] row_coord_int_mid1_fu_633_p3; +wire [12:0] tmp_50_fu_654_p3; +wire [15:0] tmp_49_fu_646_p3; +wire [15:0] zext_ln32_47_fu_662_p1; +wire [15:0] sub_ln32_2_fu_666_p2; +wire [15:0] col_coord_int_mid1_fu_640_p3; +wire [15:0] add_ln32_2_fu_672_p2; +wire [15:0] select_ln19_40_fu_626_p3; +wire [15:0] select_ln20_28_fu_678_p3; +wire [3:0] tmp_46_fu_693_p3; +wire [4:0] zext_ln33_12_fu_700_p1; +wire [4:0] zext_ln33_fu_690_p1; +wire [4:0] sub_ln33_fu_704_p2; +wire [5:0] sub_ln33_cast_fu_710_p1; +wire [5:0] zext_ln33_13_fu_714_p1; +wire [5:0] add_ln33_fu_717_p2; +wire [2:0] trunc_ln33_1_fu_727_p1; +wire [4:0] p_shl4_cast_fu_731_p3; +wire [4:0] trunc_ln33_fu_723_p1; +wire [4:0] sub_ln33_1_fu_739_p2; +wire [4:0] zext_ln33_14_fu_745_p1; +wire [5:0] tmp_51_fu_754_p3; +wire [5:0] empty_134_fu_761_p2; +wire [6:0] zext_ln32_49_fu_773_p1; +wire [6:0] zext_ln32_50_fu_777_p1; +wire [0:0] icmp_ln32_fu_767_p2; +wire [6:0] sub_ln32_19_fu_791_p2; +wire [6:0] sub_ln32_20_fu_803_p2; +reg [63:0] tmp_76_fu_781_p4; +wire [6:0] xor_ln32_fu_797_p2; +wire [6:0] select_ln32_fu_809_p3; +wire [6:0] select_ln32_17_fu_825_p3; +wire [63:0] select_ln32_16_fu_817_p3; +wire [63:0] zext_ln32_51_fu_839_p1; +wire [0:0] select_ln19_39_fu_849_p3; +wire [63:0] zext_ln32_52_fu_864_p1; +wire [63:0] lshr_ln32_10_fu_867_p2; +wire [63:0] and_ln32_fu_873_p2; +wire [15:0] trunc_ln32_fu_878_p1; +wire [0:0] select_ln20_27_fu_854_p3; +wire [15:0] in_data_elem_fu_882_p1; +wire ap_CS_fsm_state7; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter2_state4)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter1; + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_934_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ii_reg_187 <= select_ln19_36_reg_999; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_187 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_268_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten52_reg_142 <= add_ln19_6_fu_262_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten52_reg_142 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_268_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_153 <= select_ln20_29_fu_346_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_153 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_934 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_164 <= select_ln20_26_reg_965; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_164 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_268_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_reg_176 <= add_ln25_fu_334_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_176 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_268_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln20_reg_953 <= add_ln20_fu_306_p2; + and_ln19_reg_947 <= and_ln19_fu_300_p2; + icmp_ln20_reg_938 <= icmp_ln20_fu_274_p2; + select_ln20_reg_959 <= select_ln20_fu_318_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_934_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln33_1_reg_1036 <= add_ln33_1_fu_748_p2; + lshr_ln32_reg_1046 <= lshr_ln32_fu_843_p2; + sub_ln32_21_reg_1041[6 : 1] <= sub_ln32_21_fu_833_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + and_ln19_reg_947_pp0_iter1_reg <= and_ln19_reg_947; + icmp_ln19_reg_934 <= icmp_ln19_fu_268_p2; + icmp_ln19_reg_934_pp0_iter1_reg <= icmp_ln19_reg_934; + icmp_ln20_reg_938_pp0_iter1_reg <= icmp_ln20_reg_938; + is_padding_reg_987 <= is_padding_fu_411_p2; + p_cast1_i_reg_981 <= p_cast1_i_fu_367_p2; + select_ln20_26_reg_965_pp0_iter1_reg <= select_ln20_26_reg_965; + select_ln20_reg_959_pp0_iter1_reg <= select_ln20_reg_959; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + and_ln19_reg_947_pp0_iter2_reg <= and_ln19_reg_947_pp0_iter1_reg; + and_ln19_reg_947_pp0_iter3_reg <= and_ln19_reg_947_pp0_iter2_reg; + icmp_ln19_reg_934_pp0_iter2_reg <= icmp_ln19_reg_934_pp0_iter1_reg; + icmp_ln19_reg_934_pp0_iter3_reg <= icmp_ln19_reg_934_pp0_iter2_reg; + icmp_ln20_reg_938_pp0_iter2_reg <= icmp_ln20_reg_938_pp0_iter1_reg; + icmp_ln20_reg_938_pp0_iter3_reg <= icmp_ln20_reg_938_pp0_iter2_reg; + is_padding_reg_987_pp0_iter2_reg <= is_padding_reg_987; + is_padding_reg_987_pp0_iter3_reg <= is_padding_reg_987_pp0_iter2_reg; + or_ln23_28_reg_1012_pp0_iter2_reg <= or_ln23_28_reg_1012; + or_ln23_28_reg_1012_pp0_iter3_reg <= or_ln23_28_reg_1012_pp0_iter2_reg; + or_ln23_30_reg_1019_pp0_iter2_reg <= or_ln23_30_reg_1019; + or_ln23_30_reg_1019_pp0_iter3_reg <= or_ln23_30_reg_1019_pp0_iter2_reg; + select_ln19_36_reg_999_pp0_iter2_reg <= select_ln19_36_reg_999; + select_ln20_26_reg_965_pp0_iter2_reg <= select_ln20_26_reg_965_pp0_iter1_reg; + select_ln20_reg_959_pp0_iter2_reg <= select_ln20_reg_959_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'd0 == and_ln19_reg_947) & (icmp_ln20_reg_938 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + empty_132_reg_994 <= empty_132_fu_427_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + or_ln23_26_reg_919 <= or_ln23_26_fu_250_p2; + p_cast_i_reg_901 <= p_cast_i_fu_216_p1; + p_cast_reg_913 <= p_cast_fu_230_p2; + p_mid140_reg_924 <= p_mid140_fu_256_p2; + sext_ln22_reg_907 <= sext_ln22_fu_226_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_934 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + or_ln23_28_reg_1012 <= or_ln23_28_fu_476_p2; + or_ln23_30_reg_1019 <= or_ln23_30_fu_512_p2; + p_cast1_i_mid1_reg_1006 <= p_cast1_i_mid1_fu_458_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_934 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'd1 == and_ln19_reg_947))) begin + p_mid1_reg_1026 <= p_mid1_fu_528_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_934 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + select_ln19_36_reg_999 <= select_ln19_36_fu_438_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_268_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln20_26_reg_965 <= select_ln20_26_fu_326_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_condition_pp0_exit_iter2_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter2_state4 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_fu_268_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_934_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_191_p4 = select_ln19_36_reg_999; + end else begin + ap_phi_mux_ii_phi_fu_191_p4 = ii_reg_187; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_934 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_168_p4 = select_ln20_26_reg_965; + end else begin + ap_phi_mux_jj_phi_fu_168_p4 = jj_reg_164; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_934_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + ifmap_vec_we0 = 1'b1; + end else begin + ifmap_vec_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln19_6_fu_262_p2 = (indvar_flatten52_reg_142 + 5'd1); + +assign add_ln19_fu_432_p2 = (ap_phi_mux_ii_phi_fu_191_p4 + 2'd1); + +assign add_ln20_6_fu_340_p2 = (indvar_flatten_reg_153 + 4'd1); + +assign add_ln20_fu_306_p2 = (select_ln19_fu_280_p3 + 2'd1); + +assign add_ln22_6_fu_386_p2 = ((sext_ln22_reg_907) + (zext_ln20_fu_378_p1)); + +assign add_ln22_7_fu_487_p2 = ((sext_ln22_reg_907) + (zext_ln20_6_fu_481_p1)); + +assign add_ln22_fu_220_p2 = ((j_cast_i_fu_198_p1) + (17'd131071)); + +assign add_ln25_fu_334_p2 = (select_ln20_fu_318_p3 + 2'd1); + +assign add_ln32_1_fu_620_p2 = (sub_ln32_1_fu_614_p2 + col_coord_int_mid142_fu_588_p3); + +assign add_ln32_2_fu_672_p2 = (sub_ln32_2_fu_666_p2 + col_coord_int_mid1_fu_640_p3); + +assign add_ln32_fu_571_p2 = (sub_ln32_fu_565_p2 + col_coord_int_fu_539_p3); + +assign add_ln33_1_fu_748_p2 = (sub_ln33_1_fu_739_p2 + zext_ln33_14_fu_745_p1); + +assign add_ln33_fu_717_p2 = ((sub_ln33_cast_fu_710_p1) + (zext_ln33_13_fu_714_p1)); + +assign and_ln19_fu_300_p2 = (xor_ln19_fu_288_p2 & icmp_ln25_fu_294_p2); + +assign and_ln32_fu_873_p2 = (lshr_ln32_reg_1046 & lshr_ln32_10_fu_867_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign col_coord_int_fu_539_p3 = ((is_padding_reg_987[0:0] == 1'b1) ? 16'd0 : empty_132_reg_994); + +assign col_coord_int_mid142_fu_588_p3 = ((or_ln23_28_reg_1012[0:0] == 1'b1) ? 16'd0 : p_mid140_reg_924); + +assign col_coord_int_mid1_fu_640_p3 = ((or_ln23_30_reg_1019[0:0] == 1'b1) ? 16'd0 : p_mid1_reg_1026); + +assign empty_129_fu_210_p2 = ((zext_ln19_fu_202_p1) + (17'd131071)); + +assign empty_130_fu_362_p2 = ((p_cast_i_reg_901) + (ii_cast_i_fu_354_p1)); + +assign empty_131_fu_372_p2 = ((empty_130_fu_362_p2 > 18'd223) ? 1'b1 : 1'b0); + +assign empty_132_fu_427_p2 = ((tmp2_cast_fu_423_p1) + (j_19)); + +assign empty_134_fu_761_p2 = (tmp_51_fu_754_p3 | 6'd15); + +assign empty_fu_206_p1 = i_19[7:0]; + +assign icmp_ln19_fu_268_p2 = ((indvar_flatten52_reg_142 == 5'd27) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_274_p2 = ((indvar_flatten_reg_153 == 4'd9) ? 1'b1 : 1'b0); + +assign icmp_ln24_6_fu_399_p2 = (((add_ln22_6_fu_386_p2) > (18'd223)) ? 1'b1 : 1'b0); + +assign icmp_ln24_7_fu_500_p2 = (((add_ln22_7_fu_487_p2) > (18'd223)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_244_p2 = (((add_ln22_fu_220_p2) > (17'd223)) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_294_p2 = ((kk_reg_176 == 2'd3) ? 1'b1 : 1'b0); + +assign icmp_ln32_fu_767_p2 = ((tmp_51_fu_754_p3 > empty_134_fu_761_p2) ? 1'b1 : 1'b0); + +assign ifmap_vec_address0 = zext_ln33_15_fu_860_p1; + +assign ifmap_vec_d0 = ((select_ln20_27_fu_854_p3[0:0] == 1'b1) ? 16'd0 : in_data_elem_fu_882_p1); + +assign ii_cast_fu_358_p1 = ap_phi_mux_ii_phi_fu_191_p4; + +assign ii_cast_i_fu_354_p1 = ap_phi_mux_ii_phi_fu_191_p4; + +assign ii_cast_i_mid1_fu_445_p1 = add_ln19_fu_432_p2; + +assign ii_cast_mid1_fu_449_p1 = add_ln19_fu_432_p2; + +assign in_data_address0 = zext_ln32_48_fu_685_p1; + +assign in_data_elem_fu_882_p1 = trunc_ln32_fu_878_p1; + +assign is_padding_fu_411_p2 = (or_ln23_fu_405_p2 | empty_131_fu_372_p2); + +assign j_cast_i_fu_198_p1 = j_19; + +assign lshr_ln32_10_fu_867_p2 = 64'd18446744073709551615 >> zext_ln32_52_fu_864_p1; + +assign lshr_ln32_fu_843_p2 = select_ln32_16_fu_817_p3 >> zext_ln32_51_fu_839_p1; + +assign or_ln20_fu_312_p2 = (icmp_ln20_fu_274_p2 | and_ln19_fu_300_p2); + +assign or_ln23_26_fu_250_p2 = (tmp_fu_236_p3 | icmp_ln24_fu_244_p2); + +assign or_ln23_28_fu_476_p2 = (p_mid116_fu_463_p2 | or_ln23_26_reg_919); + +assign or_ln23_29_fu_506_p2 = (tmp_75_fu_492_p3 | icmp_ln24_7_fu_500_p2); + +assign or_ln23_30_fu_512_p2 = (select_ln19_38_fu_469_p3 | or_ln23_29_fu_506_p2); + +assign or_ln23_fu_405_p2 = (tmp_74_fu_391_p3 | icmp_ln24_6_fu_399_p2); + +assign p_cast1_i_fu_367_p2 = (p_cast_reg_913 + ii_cast_fu_358_p1); + +assign p_cast1_i_mid1_fu_458_p2 = (p_cast_reg_913 + ii_cast_mid1_fu_449_p1); + +assign p_cast_fu_230_p2 = ((empty_fu_206_p1) + (8'd255)); + +assign p_cast_i_fu_216_p1 = (empty_129_fu_210_p2); + +assign p_mid114_fu_453_p2 = ((p_cast_i_reg_901) + (ii_cast_i_mid1_fu_445_p1)); + +assign p_mid116_fu_463_p2 = ((p_mid114_fu_453_p2 > 18'd223) ? 1'b1 : 1'b0); + +assign p_mid140_fu_256_p2 = ((j_19) + (16'd65535)); + +assign p_mid1_fu_528_p2 = ((tmp2_cast_mid1_fu_524_p1) + (j_19)); + +assign p_shl4_cast_fu_731_p3 = {{trunc_ln33_1_fu_727_p1}, {2'd0}}; + +assign row_coord_int_fu_533_p3 = ((is_padding_reg_987[0:0] == 1'b1) ? 8'd0 : p_cast1_i_reg_981); + +assign row_coord_int_mid134_fu_582_p3 = ((or_ln23_28_reg_1012[0:0] == 1'b1) ? 8'd0 : p_cast1_i_mid1_reg_1006); + +assign row_coord_int_mid1_fu_633_p3 = ((or_ln23_30_reg_1019[0:0] == 1'b1) ? 8'd0 : select_ln19_37_fu_577_p3); + +assign select_ln19_36_fu_438_p3 = ((icmp_ln20_reg_938[0:0] == 1'b1) ? add_ln19_fu_432_p2 : ap_phi_mux_ii_phi_fu_191_p4); + +assign select_ln19_37_fu_577_p3 = ((icmp_ln20_reg_938_pp0_iter1_reg[0:0] == 1'b1) ? p_cast1_i_mid1_reg_1006 : p_cast1_i_reg_981); + +assign select_ln19_38_fu_469_p3 = ((icmp_ln20_reg_938[0:0] == 1'b1) ? p_mid116_fu_463_p2 : empty_131_fu_372_p2); + +assign select_ln19_39_fu_849_p3 = ((icmp_ln20_reg_938_pp0_iter3_reg[0:0] == 1'b1) ? or_ln23_28_reg_1012_pp0_iter3_reg : is_padding_reg_987_pp0_iter3_reg); + +assign select_ln19_40_fu_626_p3 = ((icmp_ln20_reg_938_pp0_iter1_reg[0:0] == 1'b1) ? add_ln32_1_fu_620_p2 : add_ln32_fu_571_p2); + +assign select_ln19_fu_280_p3 = ((icmp_ln20_fu_274_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_168_p4); + +assign select_ln20_26_fu_326_p3 = ((and_ln19_fu_300_p2[0:0] == 1'b1) ? add_ln20_fu_306_p2 : select_ln19_fu_280_p3); + +assign select_ln20_27_fu_854_p3 = ((and_ln19_reg_947_pp0_iter3_reg[0:0] == 1'b1) ? or_ln23_30_reg_1019_pp0_iter3_reg : select_ln19_39_fu_849_p3); + +assign select_ln20_28_fu_678_p3 = ((and_ln19_reg_947_pp0_iter1_reg[0:0] == 1'b1) ? add_ln32_2_fu_672_p2 : select_ln19_40_fu_626_p3); + +assign select_ln20_29_fu_346_p3 = ((icmp_ln20_fu_274_p2[0:0] == 1'b1) ? 4'd1 : add_ln20_6_fu_340_p2); + +assign select_ln20_fu_318_p3 = ((or_ln20_fu_312_p2[0:0] == 1'b1) ? 2'd0 : kk_reg_176); + +assign select_ln32_16_fu_817_p3 = ((icmp_ln32_fu_767_p2[0:0] == 1'b1) ? tmp_76_fu_781_p4 : in_data_q0); + +assign select_ln32_17_fu_825_p3 = ((icmp_ln32_fu_767_p2[0:0] == 1'b1) ? xor_ln32_fu_797_p2 : zext_ln32_49_fu_773_p1); + +assign select_ln32_fu_809_p3 = ((icmp_ln32_fu_767_p2[0:0] == 1'b1) ? sub_ln32_19_fu_791_p2 : sub_ln32_20_fu_803_p2); + +assign sext_ln22_fu_226_p1 = add_ln22_fu_220_p2; + +assign sub_ln32_19_fu_791_p2 = (zext_ln32_49_fu_773_p1 - zext_ln32_50_fu_777_p1); + +assign sub_ln32_1_fu_614_p2 = (tmp_47_fu_594_p3 - zext_ln32_46_fu_610_p1); + +assign sub_ln32_20_fu_803_p2 = (zext_ln32_50_fu_777_p1 - zext_ln32_49_fu_773_p1); + +assign sub_ln32_21_fu_833_p2 = (7'd63 - select_ln32_fu_809_p3); + +assign sub_ln32_2_fu_666_p2 = (tmp_49_fu_646_p3 - zext_ln32_47_fu_662_p1); + +assign sub_ln32_fu_565_p2 = (tmp_s_fu_545_p3 - zext_ln32_fu_561_p1); + +assign sub_ln33_1_fu_739_p2 = (p_shl4_cast_fu_731_p3 - trunc_ln33_fu_723_p1); + +assign sub_ln33_cast_fu_710_p1 = (sub_ln33_fu_704_p2); + +assign sub_ln33_fu_704_p2 = (zext_ln33_12_fu_700_p1 - zext_ln33_fu_690_p1); + +assign tmp2_cast_fu_423_p1 = (tmp2_fu_417_p2); + +assign tmp2_cast_mid1_fu_524_p1 = (tmp2_mid1_fu_518_p2); + +assign tmp2_fu_417_p2 = ((zext_ln22_fu_382_p1) + (3'd7)); + +assign tmp2_mid1_fu_518_p2 = ((zext_ln22_6_fu_484_p1) + (3'd7)); + +assign tmp_45_fu_553_p3 = {{row_coord_int_fu_533_p3}, {5'd0}}; + +assign tmp_46_fu_693_p3 = {{select_ln19_36_reg_999_pp0_iter2_reg}, {2'd0}}; + +assign tmp_47_fu_594_p3 = {{row_coord_int_mid134_fu_582_p3}, {8'd0}}; + +assign tmp_48_fu_602_p3 = {{row_coord_int_mid134_fu_582_p3}, {5'd0}}; + +assign tmp_49_fu_646_p3 = {{row_coord_int_mid1_fu_633_p3}, {8'd0}}; + +assign tmp_50_fu_654_p3 = {{row_coord_int_mid1_fu_633_p3}, {5'd0}}; + +assign tmp_51_fu_754_p3 = {{select_ln20_reg_959_pp0_iter2_reg}, {4'd0}}; + +assign tmp_74_fu_391_p3 = add_ln22_6_fu_386_p2[32'd17]; + +assign tmp_75_fu_492_p3 = add_ln22_7_fu_487_p2[32'd17]; + +integer ap_tvar_int_0; + +always @ (in_data_q0) begin + //for (ap_tvar_int_0 = 64 - 1; ap_tvar_int_0 >= 0; ap_tvar_int_0 = ap_tvar_int_0 - 1) begin + for (ap_tvar_int_0 = 0; ap_tvar_int_0 < 64; ap_tvar_int_0 = ap_tvar_int_0 + 1) begin + if (ap_tvar_int_0 > 63 - 0) begin + tmp_76_fu_781_p4[ap_tvar_int_0] = 1'b0; + end else begin + tmp_76_fu_781_p4[ap_tvar_int_0] = in_data_q0[63 - ap_tvar_int_0]; + end + end +end + +assign tmp_fu_236_p3 = add_ln22_fu_220_p2[32'd16]; + +assign tmp_s_fu_545_p3 = {{row_coord_int_fu_533_p3}, {8'd0}}; + +assign trunc_ln32_fu_878_p1 = and_ln32_fu_873_p2[15:0]; + +assign trunc_ln33_1_fu_727_p1 = add_ln33_fu_717_p2[2:0]; + +assign trunc_ln33_fu_723_p1 = add_ln33_fu_717_p2[4:0]; + +assign xor_ln19_fu_288_p2 = (icmp_ln20_fu_274_p2 ^ 1'd1); + +assign xor_ln32_fu_797_p2 = (zext_ln32_49_fu_773_p1 ^ 7'd63); + +assign zext_ln19_fu_202_p1 = i_19; + +assign zext_ln20_6_fu_481_p1 = add_ln20_reg_953; + +assign zext_ln20_fu_378_p1 = jj_reg_164; + +assign zext_ln22_6_fu_484_p1 = add_ln20_reg_953; + +assign zext_ln22_fu_382_p1 = jj_reg_164; + +assign zext_ln32_46_fu_610_p1 = tmp_48_fu_602_p3; + +assign zext_ln32_47_fu_662_p1 = tmp_50_fu_654_p3; + +assign zext_ln32_48_fu_685_p1 = select_ln20_28_fu_678_p3; + +assign zext_ln32_49_fu_773_p1 = tmp_51_fu_754_p3; + +assign zext_ln32_50_fu_777_p1 = empty_134_fu_761_p2; + +assign zext_ln32_51_fu_839_p1 = select_ln32_17_fu_825_p3; + +assign zext_ln32_52_fu_864_p1 = sub_ln32_21_reg_1041; + +assign zext_ln32_fu_561_p1 = tmp_45_fu_553_p3; + +assign zext_ln33_12_fu_700_p1 = tmp_46_fu_693_p3; + +assign zext_ln33_13_fu_714_p1 = select_ln20_26_reg_965_pp0_iter2_reg; + +assign zext_ln33_14_fu_745_p1 = select_ln20_reg_959_pp0_iter2_reg; + +assign zext_ln33_15_fu_860_p1 = add_ln33_1_reg_1036; + +assign zext_ln33_fu_690_p1 = select_ln19_36_reg_999_pp0_iter2_reg; + +always @ (posedge ap_clk) begin + sub_ln32_21_reg_1041[0] <= 1'b0; +end + +endmodule //td_fused_top_tdf1_readInputs19 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_writeOutputs_aligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_idle, + ap_ready, + i, + j, + k, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1, + max_vals_3_0, + max_vals_3_1, + max_vals_3_2, + max_vals_3_3 +); + +parameter ap_ST_fsm_state1 = 2'd1; +parameter ap_ST_fsm_state2 = 2'd2; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +input [6:0] i; +input [13:0] j; +input [3:0] k; +output [15:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; +input [15:0] max_vals_3_0; +input [15:0] max_vals_3_1; +input [15:0] max_vals_3_2; +input [15:0] max_vals_3_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg out_data_ce1; +reg out_data_we1; + + reg [1:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [15:0] add_ln123_fu_117_p2; +reg [15:0] add_ln123_reg_188; +wire [63:0] zext_ln123_10_fu_142_p1; +wire ap_CS_fsm_state2; +wire [13:0] tmp_fu_79_p3; +wire [10:0] tmp_s_fu_91_p3; +wire [14:0] zext_ln123_fu_87_p1; +wire [14:0] zext_ln123_7_fu_99_p1; +wire [14:0] sub_ln123_fu_103_p2; +wire [15:0] sub_ln123_cast15_fu_109_p1; +wire [15:0] zext_ln123_8_fu_113_p1; +wire [15:0] shl_ln123_fu_123_p2; +wire [15:0] zext_ln123_9_fu_132_p1; +wire [15:0] add_ln123_4_fu_136_p2; +wire [15:0] bitcast_ln123_12_fu_171_p1; +wire [15:0] bitcast_ln123_11_fu_163_p1; +wire [15:0] bitcast_ln123_10_fu_155_p1; +wire [15:0] bitcast_ln123_fu_147_p1; +reg [1:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 2'd1; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + add_ln123_reg_188 <= add_ln123_fu_117_p2; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln123_4_fu_136_p2 = (shl_ln123_fu_123_p2 + zext_ln123_9_fu_132_p1); + +assign add_ln123_fu_117_p2 = (sub_ln123_cast15_fu_109_p1 + zext_ln123_8_fu_113_p1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign bitcast_ln123_10_fu_155_p1 = max_vals_3_1; + +assign bitcast_ln123_11_fu_163_p1 = max_vals_3_2; + +assign bitcast_ln123_12_fu_171_p1 = max_vals_3_3; + +assign bitcast_ln123_fu_147_p1 = max_vals_3_0; + +assign out_data_address1 = zext_ln123_10_fu_142_p1; + +assign out_data_d1 = {{{{bitcast_ln123_12_fu_171_p1}, {bitcast_ln123_11_fu_163_p1}}, {bitcast_ln123_10_fu_155_p1}}, {bitcast_ln123_fu_147_p1}}; + +assign shl_ln123_fu_123_p2 = add_ln123_reg_188 << 16'd2; + +assign sub_ln123_cast15_fu_109_p1 = sub_ln123_fu_103_p2; + +assign sub_ln123_fu_103_p2 = (zext_ln123_fu_87_p1 - zext_ln123_7_fu_99_p1); + +assign tmp_fu_79_p3 = {{i}, {7'd0}}; + +assign tmp_s_fu_91_p3 = {{i}, {4'd0}}; + +assign zext_ln123_10_fu_142_p1 = add_ln123_4_fu_136_p2; + +assign zext_ln123_7_fu_99_p1 = tmp_s_fu_91_p3; + +assign zext_ln123_8_fu_113_p1 = j; + +assign zext_ln123_9_fu_132_p1 = k; + +assign zext_ln123_fu_87_p1 = tmp_fu_79_p3; + +endmodule //td_fused_top_tdf1_writeOutputs_aligned +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_113 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_0_address0, + filter_data_0_ce0, + filter_data_0_d0, + filter_data_0_q0, + filter_data_0_we0, + filter_data_0_address1, + filter_data_0_ce1, + filter_data_0_d1, + filter_data_0_q1, + filter_data_0_we1, + filter_data_1_address0, + filter_data_1_ce0, + filter_data_1_d0, + filter_data_1_q0, + filter_data_1_we0, + filter_data_1_address1, + filter_data_1_ce1, + filter_data_1_d1, + filter_data_1_q1, + filter_data_1_we1, + filter_data_2_address0, + filter_data_2_ce0, + filter_data_2_d0, + filter_data_2_q0, + filter_data_2_we0, + filter_data_2_address1, + filter_data_2_ce1, + filter_data_2_d1, + filter_data_2_q1, + filter_data_2_we1, + filter_data_3_address0, + filter_data_3_ce0, + filter_data_3_d0, + filter_data_3_q0, + filter_data_3_we0, + filter_data_3_address1, + filter_data_3_ce1, + filter_data_3_d1, + filter_data_3_q1, + filter_data_3_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [15:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [15:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [14:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [14:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [9:0] filter_data_0_address0; +output filter_data_0_ce0; +output [31:0] filter_data_0_d0; +input [31:0] filter_data_0_q0; +output filter_data_0_we0; +output [9:0] filter_data_0_address1; +output filter_data_0_ce1; +output [31:0] filter_data_0_d1; +input [31:0] filter_data_0_q1; +output filter_data_0_we1; +output [9:0] filter_data_1_address0; +output filter_data_1_ce0; +output [31:0] filter_data_1_d0; +input [31:0] filter_data_1_q0; +output filter_data_1_we0; +output [9:0] filter_data_1_address1; +output filter_data_1_ce1; +output [31:0] filter_data_1_d1; +input [31:0] filter_data_1_q1; +output filter_data_1_we1; +output [9:0] filter_data_2_address0; +output filter_data_2_ce0; +output [31:0] filter_data_2_d0; +input [31:0] filter_data_2_q0; +output filter_data_2_we0; +output [9:0] filter_data_2_address1; +output filter_data_2_ce1; +output [31:0] filter_data_2_d1; +input [31:0] filter_data_2_q1; +output filter_data_2_we1; +output [9:0] filter_data_3_address0; +output filter_data_3_ce0; +output [31:0] filter_data_3_d0; +input [31:0] filter_data_3_q0; +output filter_data_3_we0; +output [9:0] filter_data_3_address1; +output filter_data_3_ce1; +output [31:0] filter_data_3_d1; +input [31:0] filter_data_3_q1; +output filter_data_3_we1; +output [4:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [4:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [15:0] dataflow_in_loop_TOP_LOOP48322_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP48322_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48322_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP48322_U0_in_data_we0; +wire [15:0] dataflow_in_loop_TOP_LOOP48322_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP48322_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48322_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP48322_U0_in_data_we1; +wire [9:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_address0; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_ce0; +wire [31:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_d0; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_we0; +wire [9:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_address1; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_ce1; +wire [31:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_d1; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_we1; +wire [9:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_address0; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_ce0; +wire [31:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_d0; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_we0; +wire [9:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_address1; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_ce1; +wire [31:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_d1; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_we1; +wire [9:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_address0; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_ce0; +wire [31:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_d0; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_we0; +wire [9:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_address1; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_ce1; +wire [31:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_d1; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_we1; +wire [9:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_address0; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_ce0; +wire [31:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_d0; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_we0; +wire [9:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_address1; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_ce1; +wire [31:0] dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_d1; +wire dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_we1; +wire [4:0] dataflow_in_loop_TOP_LOOP48322_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP48322_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP48322_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP48322_U0_adjustments_we0; +wire [4:0] dataflow_in_loop_TOP_LOOP48322_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP48322_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP48322_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP48322_U0_adjustments_we1; +wire [14:0] dataflow_in_loop_TOP_LOOP48322_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP48322_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48322_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP48322_U0_out_data_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP48322_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP48322_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48322_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP48322_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP48322_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP48322_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP48322_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP48322_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP48322_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP48322_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP48322_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP48322_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP48322_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [16:0] loop_dataflow_input_count; +reg [16:0] loop_dataflow_output_count; +wire [16:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP48322_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP48322_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 17'd0; +#0 loop_dataflow_output_count = 17'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP48322 dataflow_in_loop_TOP_LOOP48322_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP48322_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP48322_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP48322_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP48322_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP48322_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP48322_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP48322_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP48322_U0_in_data_we1), + .filter_data_0_address0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_address0), + .filter_data_0_ce0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_ce0), + .filter_data_0_d0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_d0), + .filter_data_0_q0(filter_data_0_q0), + .filter_data_0_we0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_we0), + .filter_data_0_address1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_address1), + .filter_data_0_ce1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_ce1), + .filter_data_0_d1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_d1), + .filter_data_0_q1(32'd0), + .filter_data_0_we1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_we1), + .filter_data_1_address0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_address0), + .filter_data_1_ce0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_ce0), + .filter_data_1_d0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_d0), + .filter_data_1_q0(filter_data_1_q0), + .filter_data_1_we0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_we0), + .filter_data_1_address1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_address1), + .filter_data_1_ce1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_ce1), + .filter_data_1_d1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_d1), + .filter_data_1_q1(32'd0), + .filter_data_1_we1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_we1), + .filter_data_2_address0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_address0), + .filter_data_2_ce0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_ce0), + .filter_data_2_d0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_d0), + .filter_data_2_q0(filter_data_2_q0), + .filter_data_2_we0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_we0), + .filter_data_2_address1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_address1), + .filter_data_2_ce1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_ce1), + .filter_data_2_d1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_d1), + .filter_data_2_q1(32'd0), + .filter_data_2_we1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_we1), + .filter_data_3_address0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_address0), + .filter_data_3_ce0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_ce0), + .filter_data_3_d0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_d0), + .filter_data_3_q0(filter_data_3_q0), + .filter_data_3_we0(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_we0), + .filter_data_3_address1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_address1), + .filter_data_3_ce1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_ce1), + .filter_data_3_d1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_d1), + .filter_data_3_q1(32'd0), + .filter_data_3_we1(dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP48322_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP48322_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP48322_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP48322_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP48322_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP48322_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP48322_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP48322_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP48322_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP48322_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP48322_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP48322_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP48322_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP48322_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP48322_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP48322_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP48322_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP48322_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP48322_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP48322_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP48322_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP48322_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP48322_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 17'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP48322_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 17'd1); + end else if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP48322_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= 17'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 17'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48322_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP48322_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 17'd1); + end else if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48322_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP48322_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= 17'd0; + end + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48322_U0_ap_done == 1'b1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == 17'd0) & (ap_start == 1'b0) & (dataflow_in_loop_TOP_LOOP48322_U0_ap_idle == 1'b1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP48322_U0_ap_ready == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP48322_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP48322_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP48322_U0_adjustments_address0; + +assign adjustments_address1 = 5'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP48322_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP48322_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP48322_U0_ap_ready; + +assign bound_minus_1 = (17'd100352 - 17'd1); + +assign dataflow_in_loop_TOP_LOOP48322_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP48322_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP48322_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP48322_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP48322_U0_start_write = 1'b0; + +assign filter_data_0_address0 = dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_address0; + +assign filter_data_0_address1 = 10'd0; + +assign filter_data_0_ce0 = dataflow_in_loop_TOP_LOOP48322_U0_filter_data_0_ce0; + +assign filter_data_0_ce1 = 1'b0; + +assign filter_data_0_d0 = 32'd0; + +assign filter_data_0_d1 = 32'd0; + +assign filter_data_0_we0 = 1'b0; + +assign filter_data_0_we1 = 1'b0; + +assign filter_data_1_address0 = dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_address0; + +assign filter_data_1_address1 = 10'd0; + +assign filter_data_1_ce0 = dataflow_in_loop_TOP_LOOP48322_U0_filter_data_1_ce0; + +assign filter_data_1_ce1 = 1'b0; + +assign filter_data_1_d0 = 32'd0; + +assign filter_data_1_d1 = 32'd0; + +assign filter_data_1_we0 = 1'b0; + +assign filter_data_1_we1 = 1'b0; + +assign filter_data_2_address0 = dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_address0; + +assign filter_data_2_address1 = 10'd0; + +assign filter_data_2_ce0 = dataflow_in_loop_TOP_LOOP48322_U0_filter_data_2_ce0; + +assign filter_data_2_ce1 = 1'b0; + +assign filter_data_2_d0 = 32'd0; + +assign filter_data_2_d1 = 32'd0; + +assign filter_data_2_we0 = 1'b0; + +assign filter_data_2_we1 = 1'b0; + +assign filter_data_3_address0 = dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_address0; + +assign filter_data_3_address1 = 10'd0; + +assign filter_data_3_ce0 = dataflow_in_loop_TOP_LOOP48322_U0_filter_data_3_ce0; + +assign filter_data_3_ce1 = 1'b0; + +assign filter_data_3_d0 = 32'd0; + +assign filter_data_3_d1 = 32'd0; + +assign filter_data_3_we0 = 1'b0; + +assign filter_data_3_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP48322_U0_in_data_address0; + +assign in_data_address1 = 16'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP48322_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP48322_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 15'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP48322_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP48322_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP48322_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP48322_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP48322_U0_out_data_write; + +endmodule //td_fused_top_tdf2_113 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_in1_address0, + accum_in1_ce0, + accum_in1_q0, + accum_in1_address1, + accum_in1_ce1, + accum_in1_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_pp0_stage0 = 11'd2; +parameter ap_ST_fsm_pp0_stage1 = 11'd4; +parameter ap_ST_fsm_pp0_stage2 = 11'd8; +parameter ap_ST_fsm_pp0_stage3 = 11'd16; +parameter ap_ST_fsm_pp0_stage4 = 11'd32; +parameter ap_ST_fsm_pp0_stage5 = 11'd64; +parameter ap_ST_fsm_pp0_stage6 = 11'd128; +parameter ap_ST_fsm_state17 = 11'd256; +parameter ap_ST_fsm_state18 = 11'd512; +parameter ap_ST_fsm_state19 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [6:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [6:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [6:0] accum_in1_address0; +output accum_in1_ce0; +input [15:0] accum_in1_q0; +output [6:0] accum_in1_address1; +output accum_in1_ce1; +input [15:0] accum_in1_q1; +output [3:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [3:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[6:0] accum_in_address0; +reg accum_in_ce0; +reg[6:0] accum_in_address1; +reg accum_in_ce1; +reg[6:0] accum_in1_address0; +reg accum_in1_ce0; +reg[6:0] accum_in1_address1; +reg accum_in1_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] x_reg_263; +reg [15:0] psum_2_03_reg_275; +reg [15:0] psum_1_02_reg_287; +reg [15:0] psum_0_01_reg_299; +reg [15:0] psum_15_016_reg_311; +reg [15:0] psum_14_015_reg_323; +reg [15:0] psum_13_014_reg_335; +reg [15:0] psum_12_013_reg_347; +reg [15:0] psum_11_012_reg_359; +reg [15:0] psum_10_011_reg_371; +reg [15:0] psum_9_010_reg_383; +reg [15:0] psum_8_09_reg_395; +reg [15:0] psum_7_08_reg_407; +reg [15:0] psum_6_07_reg_419; +reg [15:0] psum_5_06_reg_431; +reg [15:0] psum_4_05_reg_443; +reg [15:0] psum_3_04_reg_455; +wire [0:0] icmp_ln49_fu_536_p2; +reg [0:0] icmp_ln49_reg_775; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state9_pp0_stage0_iter1; +wire ap_block_state16_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln49_reg_775_pp0_iter1_reg; +wire [6:0] lshr_ln_fu_542_p4; +reg [6:0] lshr_ln_reg_779; +reg [15:0] accum_in_load_reg_809; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state10_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in1_load_reg_814; +reg [15:0] accum_in_load_29_reg_819; +reg [15:0] accum_in1_load_15_reg_824; +reg [15:0] accum_in_load_30_reg_849; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state11_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in1_load_16_reg_854; +reg [15:0] accum_in_load_31_reg_859; +reg [15:0] accum_in1_load_17_reg_864; +reg [15:0] accum_in_load_32_reg_889; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state12_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in1_load_18_reg_894; +reg [15:0] accum_in_load_33_reg_899; +reg [15:0] accum_in1_load_19_reg_904; +reg [15:0] accum_in_load_34_reg_929; +wire ap_CS_fsm_pp0_stage4; +wire ap_block_state6_pp0_stage4_iter0; +wire ap_block_state13_pp0_stage4_iter1; +wire ap_block_pp0_stage4_11001; +reg [15:0] accum_in1_load_20_reg_934; +reg [15:0] accum_in_load_35_reg_939; +reg [15:0] accum_in1_load_21_reg_944; +wire [7:0] add_ln49_fu_636_p2; +reg [7:0] add_ln49_reg_949; +wire ap_CS_fsm_pp0_stage6; +wire ap_block_state8_pp0_stage6_iter0; +wire ap_block_state15_pp0_stage6_iter1; +wire ap_block_pp0_stage6_11001; +wire [15:0] grp_fu_508_p2; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_513_p2; +wire [15:0] grp_fu_518_p2; +wire ap_CS_fsm_pp0_stage5; +wire ap_block_state7_pp0_stage5_iter0; +wire ap_block_state14_pp0_stage5_iter1; +wire ap_block_pp0_stage5_11001; +reg ap_enable_reg_pp0_iter2; +wire [4:0] add_ln57_fu_659_p2; +wire ap_CS_fsm_state18; +wire [0:0] tmp_fu_642_p3; +reg ap_block_state1; +wire ap_block_pp0_stage3_subdone; +reg ap_condition_pp0_exit_iter0_state5; +wire ap_block_pp0_stage6_subdone; +wire ap_block_pp0_stage0_subdone; +reg [7:0] ap_phi_mux_x_phi_fu_267_p4; +wire ap_block_pp0_stage0; +wire ap_block_pp0_stage2; +wire [15:0] ap_phi_mux_psum_15_016_phi_fu_315_p4; +wire [15:0] ap_phi_mux_psum_14_015_phi_fu_327_p4; +wire ap_block_pp0_stage6; +wire [15:0] ap_phi_mux_psum_13_014_phi_fu_339_p4; +wire [15:0] ap_phi_mux_psum_12_013_phi_fu_351_p4; +wire [15:0] ap_phi_mux_psum_11_012_phi_fu_363_p4; +wire ap_block_pp0_stage5; +wire [15:0] ap_phi_mux_psum_10_011_phi_fu_375_p4; +wire [15:0] ap_phi_mux_psum_9_010_phi_fu_387_p4; +wire [15:0] ap_phi_mux_psum_8_09_phi_fu_399_p4; +wire ap_block_pp0_stage4; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_411_p4; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_423_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_435_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_447_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_459_p4; +reg [4:0] q_reg_467; +wire ap_CS_fsm_state17; +reg [15:0] ap_phi_mux_phi_ln69_phi_fu_481_p16; +wire [3:0] trunc_ln57_fu_655_p1; +wire [63:0] zext_ln53_fu_552_p1; +wire [63:0] zext_ln53_15_fu_564_p1; +wire [63:0] zext_ln53_16_fu_575_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln53_17_fu_586_p1; +wire [63:0] zext_ln53_18_fu_597_p1; +wire [63:0] zext_ln53_19_fu_608_p1; +wire [63:0] zext_ln53_20_fu_619_p1; +wire [63:0] zext_ln53_21_fu_630_p1; +wire [63:0] zext_ln57_fu_650_p1; +wire [63:0] zext_ln57_3_fu_671_p1; +reg [15:0] grp_fu_508_p0; +reg [15:0] grp_fu_508_p1; +reg [15:0] grp_fu_513_p0; +reg [15:0] grp_fu_513_p1; +reg [15:0] grp_fu_518_p0; +reg [15:0] grp_fu_518_p1; +wire [6:0] or_ln53_fu_558_p2; +wire [6:0] or_ln53_13_fu_570_p2; +wire [6:0] or_ln53_14_fu_581_p2; +wire [6:0] or_ln53_15_fu_592_p2; +wire [6:0] or_ln53_16_fu_603_p2; +wire [6:0] or_ln53_17_fu_614_p2; +wire [6:0] or_ln53_18_fu_625_p2; +wire [3:0] or_ln57_fu_665_p2; +wire [0:0] icmp_ln69_fu_676_p2; +wire [0:0] icmp_ln69_13_fu_690_p2; +wire [15:0] select_ln69_fu_682_p3; +wire [0:0] icmp_ln69_14_fu_704_p2; +wire [15:0] select_ln69_13_fu_696_p3; +wire [0:0] icmp_ln69_15_fu_718_p2; +wire [15:0] select_ln69_14_fu_710_p3; +wire [0:0] icmp_ln69_16_fu_732_p2; +wire [15:0] select_ln69_15_fu_724_p3; +wire [0:0] icmp_ln69_17_fu_746_p2; +wire [15:0] select_ln69_16_fu_738_p3; +wire [0:0] icmp_ln69_18_fu_760_p2; +wire [15:0] select_ln69_17_fu_752_p3; +wire ap_CS_fsm_state19; +reg [10:0] ap_NS_fsm; +wire ap_block_pp0_stage1_subdone; +wire ap_block_pp0_stage2_subdone; +wire ap_block_pp0_stage4_subdone; +wire ap_block_pp0_stage5_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_728; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U263( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_508_p0), + .din1(grp_fu_508_p1), + .dout(grp_fu_508_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U264( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_513_p0), + .din1(grp_fu_513_p1), + .dout(grp_fu_513_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U265( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_518_p0), + .din1(grp_fu_518_p1), + .dout(grp_fu_518_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state19)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state5) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6_subdone))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6_subdone)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + q_reg_467 <= 5'd0; + end else if (((tmp_fu_642_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + q_reg_467 <= add_ln57_fu_659_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + x_reg_263 <= add_ln49_reg_949; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_263 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + accum_in1_load_15_reg_824 <= accum_in1_q0; + accum_in1_load_reg_814 <= accum_in1_q1; + accum_in_load_29_reg_819 <= accum_in_q0; + accum_in_load_reg_809 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001))) begin + accum_in1_load_16_reg_854 <= accum_in1_q1; + accum_in1_load_17_reg_864 <= accum_in1_q0; + accum_in_load_30_reg_849 <= accum_in_q1; + accum_in_load_31_reg_859 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + accum_in1_load_18_reg_894 <= accum_in1_q1; + accum_in1_load_19_reg_904 <= accum_in1_q0; + accum_in_load_32_reg_889 <= accum_in_q1; + accum_in_load_33_reg_899 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4_11001))) begin + accum_in1_load_20_reg_934 <= accum_in1_q1; + accum_in1_load_21_reg_944 <= accum_in1_q0; + accum_in_load_34_reg_929 <= accum_in_q1; + accum_in_load_35_reg_939 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6_11001))) begin + add_ln49_reg_949 <= add_ln49_fu_636_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln49_reg_775 <= icmp_ln49_fu_536_p2; + icmp_ln49_reg_775_pp0_iter1_reg <= icmp_ln49_reg_775; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_fu_536_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + lshr_ln_reg_779 <= {{ap_phi_mux_x_phi_fu_267_p4[7:1]}}; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage2_11001))) begin + psum_0_01_reg_299 <= grp_fu_508_p2; + psum_1_02_reg_287 <= grp_fu_513_p2; + psum_2_03_reg_275 <= grp_fu_518_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage5_11001))) begin + psum_10_011_reg_371 <= grp_fu_513_p2; + psum_11_012_reg_359 <= grp_fu_518_p2; + psum_9_010_reg_383 <= grp_fu_508_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage6) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage6_11001))) begin + psum_12_013_reg_347 <= grp_fu_508_p2; + psum_13_014_reg_335 <= grp_fu_513_p2; + psum_14_015_reg_323 <= grp_fu_518_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + psum_15_016_reg_311 <= grp_fu_508_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + psum_3_04_reg_455 <= grp_fu_508_p2; + psum_4_05_reg_443 <= grp_fu_513_p2; + psum_5_06_reg_431 <= grp_fu_518_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage4_11001))) begin + psum_6_07_reg_419 <= grp_fu_508_p2; + psum_7_08_reg_407 <= grp_fu_513_p2; + psum_8_09_reg_395 <= grp_fu_518_p2; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in1_address0 = zext_ln53_21_fu_630_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in1_address0 = zext_ln53_19_fu_608_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in1_address0 = zext_ln53_17_fu_586_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in1_address0 = zext_ln53_15_fu_564_p1; + end else begin + accum_in1_address0 = 'bx; + end + end else begin + accum_in1_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in1_address1 = zext_ln53_20_fu_619_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in1_address1 = zext_ln53_18_fu_597_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in1_address1 = zext_ln53_16_fu_575_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in1_address1 = zext_ln53_fu_552_p1; + end else begin + accum_in1_address1 = 'bx; + end + end else begin + accum_in1_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in1_ce0 = 1'b1; + end else begin + accum_in1_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in1_ce1 = 1'b1; + end else begin + accum_in1_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in_address0 = zext_ln53_21_fu_630_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in_address0 = zext_ln53_19_fu_608_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in_address0 = zext_ln53_17_fu_586_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in_address0 = zext_ln53_15_fu_564_p1; + end else begin + accum_in_address0 = 'bx; + end + end else begin + accum_in_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in_address1 = zext_ln53_20_fu_619_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in_address1 = zext_ln53_18_fu_597_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in_address1 = zext_ln53_16_fu_575_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in_address1 = zext_ln53_fu_552_p1; + end else begin + accum_in_address1 = 'bx; + end + end else begin + accum_in_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state18)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state18)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_642_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_642_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln49_reg_775 == 1'd0)) begin + ap_condition_pp0_exit_iter0_state5 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state5 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state19)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_642_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + if ((trunc_ln57_fu_655_p1 == 4'd0)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_0_01_reg_299; + end else if ((1'b1 == ap_condition_728)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_14_015_reg_323; + end else if ((trunc_ln57_fu_655_p1 == 4'd12)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_12_013_reg_347; + end else if ((trunc_ln57_fu_655_p1 == 4'd10)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_10_011_reg_371; + end else if ((trunc_ln57_fu_655_p1 == 4'd8)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_8_09_reg_395; + end else if ((trunc_ln57_fu_655_p1 == 4'd6)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_6_07_reg_419; + end else if ((trunc_ln57_fu_655_p1 == 4'd4)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_4_05_reg_443; + end else if ((trunc_ln57_fu_655_p1 == 4'd2)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_2_03_reg_275; + end else begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = 'bx; + end + end else begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln49_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_x_phi_fu_267_p4 = add_ln49_reg_949; + end else begin + ap_phi_mux_x_phi_fu_267_p4 = x_reg_263; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state19)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_508_p0 = ap_phi_mux_psum_15_016_phi_fu_315_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_508_p0 = ap_phi_mux_psum_12_013_phi_fu_351_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_508_p0 = ap_phi_mux_psum_9_010_phi_fu_387_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_508_p0 = ap_phi_mux_psum_6_07_phi_fu_423_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_508_p0 = ap_phi_mux_psum_3_04_phi_fu_459_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_508_p0 = grp_fu_508_p2; + end else begin + grp_fu_508_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_508_p1 = accum_in1_load_21_reg_944; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_508_p1 = accum_in_load_34_reg_929; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_508_p1 = accum_in1_load_18_reg_894; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_508_p1 = accum_in_load_31_reg_859; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_508_p1 = accum_in1_load_15_reg_824; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_508_p1 = accum_in_load_reg_809; + end else begin + grp_fu_508_p1 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_513_p0 = ap_phi_mux_psum_13_014_phi_fu_339_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_513_p0 = ap_phi_mux_psum_10_011_phi_fu_375_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_513_p0 = ap_phi_mux_psum_7_08_phi_fu_411_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_513_p0 = ap_phi_mux_psum_4_05_phi_fu_447_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_513_p0 = grp_fu_513_p2; + end else begin + grp_fu_513_p0 = 'bx; + end + end else begin + grp_fu_513_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_513_p1 = accum_in1_load_20_reg_934; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_513_p1 = accum_in_load_33_reg_899; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_513_p1 = accum_in1_load_17_reg_864; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_513_p1 = accum_in_load_30_reg_849; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_513_p1 = accum_in1_load_reg_814; + end else begin + grp_fu_513_p1 = 'bx; + end + end else begin + grp_fu_513_p1 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_518_p0 = ap_phi_mux_psum_14_015_phi_fu_327_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_518_p0 = ap_phi_mux_psum_11_012_phi_fu_363_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_518_p0 = ap_phi_mux_psum_8_09_phi_fu_399_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_518_p0 = ap_phi_mux_psum_5_06_phi_fu_435_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_518_p0 = grp_fu_518_p2; + end else begin + grp_fu_518_p0 = 'bx; + end + end else begin + grp_fu_518_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_518_p1 = accum_in_load_35_reg_939; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_518_p1 = accum_in1_load_19_reg_904; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_518_p1 = accum_in_load_32_reg_889; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_518_p1 = accum_in1_load_16_reg_854; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_518_p1 = accum_in_load_29_reg_819; + end else begin + grp_fu_518_p1 = 'bx; + end + end else begin + grp_fu_518_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if (((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state17; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((1'b0 == ap_block_pp0_stage2_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((~((icmp_ln49_reg_775 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_subdone)) & (1'b0 == ap_block_pp0_stage3_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end else if (((icmp_ln49_reg_775 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state17; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_pp0_stage4 : begin + if ((1'b0 == ap_block_pp0_stage4_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end + end + ap_ST_fsm_pp0_stage5 : begin + if ((1'b0 == ap_block_pp0_stage5_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end + end + ap_ST_fsm_pp0_stage6 : begin + if ((1'b0 == ap_block_pp0_stage6_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state18; + end + ap_ST_fsm_state18 : begin + if (((tmp_fu_642_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + ap_NS_fsm = ap_ST_fsm_state18; + end else begin + ap_NS_fsm = ap_ST_fsm_state19; + end + end + ap_ST_fsm_state19 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln57_3_fu_671_p1; + +assign accum_out_address1 = zext_ln57_fu_650_p1; + +assign accum_out_d0 = ((icmp_ln69_18_fu_760_p2[0:0] == 1'b1) ? psum_13_014_reg_335 : select_ln69_17_fu_752_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln69_phi_fu_481_p16; + +assign add_ln49_fu_636_p2 = (x_reg_263 + 8'd16); + +assign add_ln57_fu_659_p2 = (q_reg_467 + 5'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd8]; + +assign ap_CS_fsm_state18 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state19 = ap_CS_fsm[32'd10]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage4_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage5_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage6_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_728 = (~(trunc_ln57_fu_655_p1 == 4'd0) & ~(trunc_ln57_fu_655_p1 == 4'd12) & ~(trunc_ln57_fu_655_p1 == 4'd10) & ~(trunc_ln57_fu_655_p1 == 4'd8) & ~(trunc_ln57_fu_655_p1 == 4'd6) & ~(trunc_ln57_fu_655_p1 == 4'd4) & ~(trunc_ln57_fu_655_p1 == 4'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_10_011_phi_fu_375_p4 = grp_fu_513_p2; + +assign ap_phi_mux_psum_11_012_phi_fu_363_p4 = grp_fu_518_p2; + +assign ap_phi_mux_psum_12_013_phi_fu_351_p4 = grp_fu_508_p2; + +assign ap_phi_mux_psum_13_014_phi_fu_339_p4 = grp_fu_513_p2; + +assign ap_phi_mux_psum_14_015_phi_fu_327_p4 = grp_fu_518_p2; + +assign ap_phi_mux_psum_15_016_phi_fu_315_p4 = grp_fu_508_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_459_p4 = grp_fu_508_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_447_p4 = grp_fu_513_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_435_p4 = grp_fu_518_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_423_p4 = grp_fu_508_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_411_p4 = grp_fu_513_p2; + +assign ap_phi_mux_psum_8_09_phi_fu_399_p4 = grp_fu_518_p2; + +assign ap_phi_mux_psum_9_010_phi_fu_387_p4 = grp_fu_508_p2; + +assign icmp_ln49_fu_536_p2 = ((ap_phi_mux_x_phi_fu_267_p4 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln69_13_fu_690_p2 = ((or_ln57_fu_665_p2 == 4'd3) ? 1'b1 : 1'b0); + +assign icmp_ln69_14_fu_704_p2 = ((or_ln57_fu_665_p2 == 4'd5) ? 1'b1 : 1'b0); + +assign icmp_ln69_15_fu_718_p2 = ((or_ln57_fu_665_p2 == 4'd7) ? 1'b1 : 1'b0); + +assign icmp_ln69_16_fu_732_p2 = ((or_ln57_fu_665_p2 == 4'd9) ? 1'b1 : 1'b0); + +assign icmp_ln69_17_fu_746_p2 = ((or_ln57_fu_665_p2 == 4'd11) ? 1'b1 : 1'b0); + +assign icmp_ln69_18_fu_760_p2 = ((or_ln57_fu_665_p2 == 4'd13) ? 1'b1 : 1'b0); + +assign icmp_ln69_fu_676_p2 = ((or_ln57_fu_665_p2 == 4'd1) ? 1'b1 : 1'b0); + +assign lshr_ln_fu_542_p4 = {{ap_phi_mux_x_phi_fu_267_p4[7:1]}}; + +assign or_ln53_13_fu_570_p2 = (lshr_ln_reg_779 | 7'd2); + +assign or_ln53_14_fu_581_p2 = (lshr_ln_reg_779 | 7'd3); + +assign or_ln53_15_fu_592_p2 = (lshr_ln_reg_779 | 7'd4); + +assign or_ln53_16_fu_603_p2 = (lshr_ln_reg_779 | 7'd5); + +assign or_ln53_17_fu_614_p2 = (lshr_ln_reg_779 | 7'd6); + +assign or_ln53_18_fu_625_p2 = (lshr_ln_reg_779 | 7'd7); + +assign or_ln53_fu_558_p2 = (lshr_ln_fu_542_p4 | 7'd1); + +assign or_ln57_fu_665_p2 = (trunc_ln57_fu_655_p1 | 4'd1); + +assign select_ln69_13_fu_696_p3 = ((icmp_ln69_13_fu_690_p2[0:0] == 1'b1) ? psum_3_04_reg_455 : select_ln69_fu_682_p3); + +assign select_ln69_14_fu_710_p3 = ((icmp_ln69_14_fu_704_p2[0:0] == 1'b1) ? psum_5_06_reg_431 : select_ln69_13_fu_696_p3); + +assign select_ln69_15_fu_724_p3 = ((icmp_ln69_15_fu_718_p2[0:0] == 1'b1) ? psum_7_08_reg_407 : select_ln69_14_fu_710_p3); + +assign select_ln69_16_fu_738_p3 = ((icmp_ln69_16_fu_732_p2[0:0] == 1'b1) ? psum_9_010_reg_383 : select_ln69_15_fu_724_p3); + +assign select_ln69_17_fu_752_p3 = ((icmp_ln69_17_fu_746_p2[0:0] == 1'b1) ? psum_11_012_reg_359 : select_ln69_16_fu_738_p3); + +assign select_ln69_fu_682_p3 = ((icmp_ln69_fu_676_p2[0:0] == 1'b1) ? psum_1_02_reg_287 : psum_15_016_reg_311); + +assign tmp_fu_642_p3 = q_reg_467[32'd4]; + +assign trunc_ln57_fu_655_p1 = q_reg_467[3:0]; + +assign zext_ln53_15_fu_564_p1 = or_ln53_fu_558_p2; + +assign zext_ln53_16_fu_575_p1 = or_ln53_13_fu_570_p2; + +assign zext_ln53_17_fu_586_p1 = or_ln53_14_fu_581_p2; + +assign zext_ln53_18_fu_597_p1 = or_ln53_15_fu_592_p2; + +assign zext_ln53_19_fu_608_p1 = or_ln53_16_fu_603_p2; + +assign zext_ln53_20_fu_619_p1 = or_ln53_17_fu_614_p2; + +assign zext_ln53_21_fu_630_p1 = or_ln53_18_fu_625_p2; + +assign zext_ln53_fu_552_p1 = lshr_ln_fu_542_p4; + +assign zext_ln57_3_fu_671_p1 = or_ln57_fu_665_p2; + +assign zext_ln57_fu_650_p1 = q_reg_467; + +endmodule //td_fused_top_tdf2_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state13 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [3:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [3:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_ce0; +reg accum_in_ce1; +reg accum_out_ce0; +reg accum_out_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [3:0] out_idx_reg_66; +reg [3:0] out_idx_reg_66_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_pp0_stage0_11001; +reg [3:0] out_idx_reg_66_pp0_iter2_reg; +reg [3:0] out_idx_reg_66_pp0_iter3_reg; +reg [3:0] out_idx_reg_66_pp0_iter4_reg; +reg [3:0] out_idx_reg_66_pp0_iter5_reg; +reg [3:0] out_idx_reg_66_pp0_iter6_reg; +reg [3:0] out_idx_reg_66_pp0_iter7_reg; +reg [3:0] out_idx_reg_66_pp0_iter8_reg; +reg [3:0] out_idx_reg_66_pp0_iter9_reg; +wire [3:0] add_ln98_fu_82_p2; +reg [3:0] add_ln98_reg_121; +reg ap_enable_reg_pp0_iter0; +wire [0:0] icmp_ln84_fu_88_p2; +reg [0:0] icmp_ln84_reg_126; +reg [0:0] icmp_ln84_reg_126_pp0_iter1_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter2_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter3_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter4_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter5_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter6_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter7_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter8_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter9_reg; +reg [15:0] accum_in_load_reg_140; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_load_1_reg_145; +wire [15:0] grp_fu_78_p2; +reg [15:0] sum0_reg_150; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg [3:0] ap_phi_mux_out_idx_phi_fu_70_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln94_fu_100_p1; +wire [63:0] zext_ln94_2_fu_111_p1; +wire [63:0] zext_ln84_fu_116_p1; +wire [3:0] i_12_fu_94_p2; +wire [3:0] or_ln94_fu_105_p2; +wire ap_CS_fsm_state13; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U269( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(accum_in_load_1_reg_145), + .din1(accum_in_load_reg_140), + .dout(grp_fu_78_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_66 <= 4'd0; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln84_reg_126 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + out_idx_reg_66 <= add_ln98_reg_121; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln84_reg_126 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_load_1_reg_145 <= accum_in_q0; + accum_in_load_reg_140 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln98_reg_121 <= add_ln98_fu_82_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln84_reg_126 <= icmp_ln84_fu_88_p2; + icmp_ln84_reg_126_pp0_iter1_reg <= icmp_ln84_reg_126; + out_idx_reg_66_pp0_iter1_reg <= out_idx_reg_66; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln84_reg_126_pp0_iter2_reg <= icmp_ln84_reg_126_pp0_iter1_reg; + icmp_ln84_reg_126_pp0_iter3_reg <= icmp_ln84_reg_126_pp0_iter2_reg; + icmp_ln84_reg_126_pp0_iter4_reg <= icmp_ln84_reg_126_pp0_iter3_reg; + icmp_ln84_reg_126_pp0_iter5_reg <= icmp_ln84_reg_126_pp0_iter4_reg; + icmp_ln84_reg_126_pp0_iter6_reg <= icmp_ln84_reg_126_pp0_iter5_reg; + icmp_ln84_reg_126_pp0_iter7_reg <= icmp_ln84_reg_126_pp0_iter6_reg; + icmp_ln84_reg_126_pp0_iter8_reg <= icmp_ln84_reg_126_pp0_iter7_reg; + icmp_ln84_reg_126_pp0_iter9_reg <= icmp_ln84_reg_126_pp0_iter8_reg; + out_idx_reg_66_pp0_iter2_reg <= out_idx_reg_66_pp0_iter1_reg; + out_idx_reg_66_pp0_iter3_reg <= out_idx_reg_66_pp0_iter2_reg; + out_idx_reg_66_pp0_iter4_reg <= out_idx_reg_66_pp0_iter3_reg; + out_idx_reg_66_pp0_iter5_reg <= out_idx_reg_66_pp0_iter4_reg; + out_idx_reg_66_pp0_iter6_reg <= out_idx_reg_66_pp0_iter5_reg; + out_idx_reg_66_pp0_iter7_reg <= out_idx_reg_66_pp0_iter6_reg; + out_idx_reg_66_pp0_iter8_reg <= out_idx_reg_66_pp0_iter7_reg; + out_idx_reg_66_pp0_iter9_reg <= out_idx_reg_66_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln84_reg_126_pp0_iter8_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sum0_reg_150 <= grp_fu_78_p2; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln84_reg_126_pp0_iter9_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln84_fu_88_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln84_reg_126 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_out_idx_phi_fu_70_p4 = add_ln98_reg_121; + end else begin + ap_phi_mux_out_idx_phi_fu_70_p4 = out_idx_reg_66; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln84_fu_88_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_enable_reg_pp0_iter9 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln84_fu_88_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_enable_reg_pp0_iter9 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln94_2_fu_111_p1; + +assign accum_in_address1 = zext_ln94_fu_100_p1; + +assign accum_out_address0 = zext_ln84_fu_116_p1; + +assign accum_out_d0 = sum0_reg_150; + +assign add_ln98_fu_82_p2 = (ap_phi_mux_out_idx_phi_fu_70_p4 + 4'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign i_12_fu_94_p2 = ap_phi_mux_out_idx_phi_fu_70_p4 << 4'd1; + +assign icmp_ln84_fu_88_p2 = ((ap_phi_mux_out_idx_phi_fu_70_p4 == 4'd8) ? 1'b1 : 1'b0); + +assign or_ln94_fu_105_p2 = (i_12_fu_94_p2 | 4'd1); + +assign zext_ln84_fu_116_p1 = out_idx_reg_66_pp0_iter9_reg; + +assign zext_ln94_2_fu_111_p1 = or_ln94_fu_105_p2; + +assign zext_ln94_fu_100_p1 = i_12_fu_94_p2; + +endmodule //td_fused_top_tdf2_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_accum_3_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_34, + accum_in_34_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_34; +output accum_in_34_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_34; +reg accum_in_34_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln111_fu_73_p2; +reg [3:0] add_ln111_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln111_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln111_fu_79_p1; +reg [15:0] accum_in_34_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_34_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U276( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_34_preg <= 16'd0; + end else begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_34_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln111_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln111_reg_90 <= add_ln111_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_34 = sum_01_reg_55; + end else begin + accum_in_34 = accum_in_34_preg; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_34_ap_vld = 1'b1; + end else begin + accum_in_34_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln111_fu_79_p1; + +assign add_ln111_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln111_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln111_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf2_accum_3_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_accum_3_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_32, + accum_in_32_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_32; +output accum_in_32_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_32; +reg accum_in_32_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln111_fu_73_p2; +reg [3:0] add_ln111_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln111_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln111_fu_79_p1; +reg [15:0] accum_in_32_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_32_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U280( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_32_preg <= 16'd0; + end else begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_32_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln111_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln111_reg_90 <= add_ln111_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_32 = sum_01_reg_55; + end else begin + accum_in_32 = accum_in_32_preg; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_32_ap_vld = 1'b1; + end else begin + accum_in_32_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln111_fu_79_p1; + +assign add_ln111_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln111_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln111_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf2_accum_3_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_accum_3_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_30, + accum_in_30_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_30; +output accum_in_30_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_30; +reg accum_in_30_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln111_fu_73_p2; +reg [3:0] add_ln111_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln111_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln111_fu_79_p1; +reg [15:0] accum_in_30_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_30_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U284( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_30_preg <= 16'd0; + end else begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_30_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln111_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln111_reg_90 <= add_ln111_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_30 = sum_01_reg_55; + end else begin + accum_in_30 = accum_in_30_preg; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_30_ap_vld = 1'b1; + end else begin + accum_in_30_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln111_fu_79_p1; + +assign add_ln111_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln111_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln111_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf2_accum_3_3 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_accum_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_36, + accum_in_36_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_36; +output accum_in_36_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_36; +reg accum_in_36_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln111_fu_73_p2; +reg [3:0] add_ln111_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln111_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln111_fu_79_p1; +reg [15:0] accum_in_36_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_36_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U272( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_36_preg <= 16'd0; + end else begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_36_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln111_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln111_reg_90 <= add_ln111_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_36 = sum_01_reg_55; + end else begin + accum_in_36 = accum_in_36_preg; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_36_ap_vld = 1'b1; + end else begin + accum_in_36_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln111_fu_79_p1; + +assign add_ln111_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln111_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln111_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf2_accum_3 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf2_adjustments_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 48; +parameter AWIDTH = 5; +parameter MEM_SIZE = 32; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf2_adjustments( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd48; +parameter AddressRange = 32'd32; +parameter AddressWidth = 32'd5; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf2_adjustments_ram td_fused_top_tdf2_adjustments_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_0_read, + sums_1_read, + sums_2_read, + sums_3_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + input_indices_23_out_din, + input_indices_23_out_full_n, + input_indices_23_out_write, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state25 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_0_read; +input [15:0] sums_1_read; +input [15:0] sums_2_read; +input [15:0] sums_3_read; +output [4:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [4:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [4:0] input_indices_23_out_din; +input input_indices_23_out_full_n; +output input_indices_23_out_write; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg input_indices_23_read; +reg input_indices_23_out_write; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +reg input_indices_23_out_blk_n; +reg [0:0] write_flag6_0_reg_153; +reg [0:0] write_flag9_0_reg_164; +reg [0:0] write_flag12_0_reg_175; +reg [0:0] write_flag_0_reg_186; +reg [2:0] o_reg_197; +reg [15:0] outputs_1_011_reg_208; +reg [15:0] outputs_0_010_reg_220; +reg [15:0] outputs_2_09_reg_232; +reg [15:0] outputs_3_08_reg_244; +wire [2:0] trunc_ln235_fu_268_p1; +reg [2:0] trunc_ln235_reg_550; +wire [2:0] add_ln213_fu_272_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_state13_pp0_stage0_iter11; +wire ap_block_state14_pp0_stage0_iter12; +wire ap_block_state15_pp0_stage0_iter13; +wire ap_block_state16_pp0_stage0_iter14; +wire ap_block_state17_pp0_stage0_iter15; +wire ap_block_state18_pp0_stage0_iter16; +wire ap_block_state19_pp0_stage0_iter17; +wire ap_block_state20_pp0_stage0_iter18; +wire ap_block_state21_pp0_stage0_iter19; +wire ap_block_state22_pp0_stage0_iter20; +wire ap_block_state23_pp0_stage0_iter21; +wire ap_block_state24_pp0_stage0_iter22; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln213_fu_278_p2; +reg [0:0] icmp_ln213_reg_560; +reg [0:0] icmp_ln213_reg_560_pp0_iter1_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter2_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter3_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter4_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter5_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter6_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter7_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter8_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter9_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter10_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter11_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter12_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter13_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter14_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter15_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter16_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter17_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter18_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter19_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter20_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter21_reg; +wire [1:0] trunc_ln219_fu_284_p1; +reg [1:0] trunc_ln219_reg_564; +reg [1:0] trunc_ln219_reg_564_pp0_iter1_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter2_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter3_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter4_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter5_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter6_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter7_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter8_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter9_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter10_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter11_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter12_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter13_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter14_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter15_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter16_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter17_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter18_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter19_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter20_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter21_reg; +wire [0:0] write_flag_1_fu_300_p6; +wire [0:0] write_flag12_1_fu_314_p6; +wire [0:0] write_flag9_1_fu_328_p6; +wire [0:0] write_flag6_1_fu_342_p6; +wire [15:0] trunc_ln220_fu_356_p1; +reg [15:0] trunc_ln220_reg_597; +reg [15:0] tmp_248_i_i_reg_602; +reg [15:0] tmp_248_i_i_reg_602_pp0_iter2_reg; +reg [15:0] tmp_248_i_i_reg_602_pp0_iter3_reg; +reg [15:0] tmp_248_i_i_reg_602_pp0_iter4_reg; +reg [15:0] tmp_248_i_i_reg_602_pp0_iter5_reg; +reg [15:0] tmp_248_i_i_reg_602_pp0_iter6_reg; +reg [15:0] tmp_248_i_i_reg_602_pp0_iter7_reg; +reg [15:0] tmp_248_i_i_reg_602_pp0_iter8_reg; +reg [15:0] tmp_249_i_i_reg_607; +reg [15:0] tmp_249_i_i_reg_607_pp0_iter2_reg; +reg [15:0] tmp_249_i_i_reg_607_pp0_iter3_reg; +reg [15:0] tmp_249_i_i_reg_607_pp0_iter4_reg; +reg [15:0] tmp_249_i_i_reg_607_pp0_iter5_reg; +reg [15:0] tmp_249_i_i_reg_607_pp0_iter6_reg; +reg [15:0] tmp_249_i_i_reg_607_pp0_iter7_reg; +reg [15:0] tmp_249_i_i_reg_607_pp0_iter8_reg; +reg [15:0] tmp_249_i_i_reg_607_pp0_iter9_reg; +reg [15:0] tmp_249_i_i_reg_607_pp0_iter10_reg; +reg [15:0] tmp_249_i_i_reg_607_pp0_iter11_reg; +reg [15:0] tmp_249_i_i_reg_607_pp0_iter12_reg; +reg [15:0] tmp_249_i_i_reg_607_pp0_iter13_reg; +wire [15:0] val_in_assign_fu_380_p6; +reg [15:0] val_in_assign_reg_612; +wire [15:0] grp_fu_260_p2; +reg [15:0] sub_i_i_i_reg_622; +wire [15:0] grp_fu_264_p2; +reg [15:0] normalized_reg_632; +wire [15:0] grp_fu_256_p2; +reg [15:0] biased_reg_642; +wire [15:0] outputs_3_1_fu_450_p3; +reg ap_enable_reg_pp0_iter22; +wire [15:0] outputs_2_1_fu_458_p3; +wire [15:0] outputs_0_1_fu_482_p3; +wire [15:0] outputs_1_1_fu_498_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_condition_pp0_exit_iter21_state23; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln220_fu_295_p1; +wire [15:0] grp_fu_256_p1; +wire [15:0] grp_fu_260_p1; +wire [15:0] grp_fu_264_p1; +wire [4:0] ochan_fu_288_p3; +wire [15:0] data_V_fu_401_p1; +wire [0:0] p_Result_s_fu_404_p3; +wire [0:0] icmp_ln223_fu_419_p2; +wire [15:0] activated_fu_412_p3; +wire [0:0] icmp_ln223_9_fu_432_p2; +wire [15:0] select_ln223_fu_424_p3; +wire [0:0] icmp_ln223_10_fu_445_p2; +wire [15:0] select_ln223_17_fu_437_p3; +wire [15:0] select_ln223_18_fu_466_p3; +wire [15:0] select_ln223_19_fu_474_p3; +wire [15:0] select_ln223_20_fu_490_p3; +wire ap_CS_fsm_state25; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U288( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(normalized_reg_632), + .din1(grp_fu_256_p1), + .dout(grp_fu_256_p2) +); + +td_fused_top_hsub_16ns_16ns_16_7_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 7 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_7_full_dsp_1_U289( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(val_in_assign_reg_612), + .din1(grp_fu_260_p1), + .dout(grp_fu_260_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U290( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_622), + .din1(grp_fu_264_p1), + .dout(grp_fu_264_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U291( + .din0(1'd1), + .din1(write_flag_0_reg_186), + .din2(write_flag_0_reg_186), + .din3(write_flag_0_reg_186), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag_1_fu_300_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U292( + .din0(write_flag12_0_reg_175), + .din1(write_flag12_0_reg_175), + .din2(write_flag12_0_reg_175), + .din3(1'd1), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag12_1_fu_314_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U293( + .din0(write_flag9_0_reg_164), + .din1(write_flag9_0_reg_164), + .din2(1'd1), + .din3(write_flag9_0_reg_164), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag9_1_fu_328_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U294( + .din0(write_flag6_0_reg_153), + .din1(1'd1), + .din2(write_flag6_0_reg_153), + .din3(write_flag6_0_reg_153), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag6_1_fu_342_p6) +); + +td_fused_top_mux_42_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 16 )) +mux_42_16_1_1_U295( + .din0(sums_0_read), + .din1(sums_1_read), + .din2(sums_2_read), + .din3(sums_3_read), + .din4(trunc_ln219_reg_564), + .dout(val_in_assign_fu_380_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end else if ((((ap_enable_reg_pp0_iter20 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter21_state23) & (1'b0 == ap_block_pp0_stage0_subdone)) | (~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter21_state23) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter20; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + o_reg_197 <= add_ln213_fu_272_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + o_reg_197 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag12_0_reg_175 <= write_flag12_1_fu_314_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag12_0_reg_175 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag6_0_reg_153 <= write_flag6_1_fu_342_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_153 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag9_0_reg_164 <= write_flag9_1_fu_328_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_164 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag_0_reg_186 <= write_flag_1_fu_300_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_186 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_560_pp0_iter20_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + biased_reg_642 <= grp_fu_256_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln213_reg_560 <= icmp_ln213_fu_278_p2; + icmp_ln213_reg_560_pp0_iter1_reg <= icmp_ln213_reg_560; + trunc_ln219_reg_564_pp0_iter1_reg <= trunc_ln219_reg_564; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln213_reg_560_pp0_iter10_reg <= icmp_ln213_reg_560_pp0_iter9_reg; + icmp_ln213_reg_560_pp0_iter11_reg <= icmp_ln213_reg_560_pp0_iter10_reg; + icmp_ln213_reg_560_pp0_iter12_reg <= icmp_ln213_reg_560_pp0_iter11_reg; + icmp_ln213_reg_560_pp0_iter13_reg <= icmp_ln213_reg_560_pp0_iter12_reg; + icmp_ln213_reg_560_pp0_iter14_reg <= icmp_ln213_reg_560_pp0_iter13_reg; + icmp_ln213_reg_560_pp0_iter15_reg <= icmp_ln213_reg_560_pp0_iter14_reg; + icmp_ln213_reg_560_pp0_iter16_reg <= icmp_ln213_reg_560_pp0_iter15_reg; + icmp_ln213_reg_560_pp0_iter17_reg <= icmp_ln213_reg_560_pp0_iter16_reg; + icmp_ln213_reg_560_pp0_iter18_reg <= icmp_ln213_reg_560_pp0_iter17_reg; + icmp_ln213_reg_560_pp0_iter19_reg <= icmp_ln213_reg_560_pp0_iter18_reg; + icmp_ln213_reg_560_pp0_iter20_reg <= icmp_ln213_reg_560_pp0_iter19_reg; + icmp_ln213_reg_560_pp0_iter21_reg <= icmp_ln213_reg_560_pp0_iter20_reg; + icmp_ln213_reg_560_pp0_iter2_reg <= icmp_ln213_reg_560_pp0_iter1_reg; + icmp_ln213_reg_560_pp0_iter3_reg <= icmp_ln213_reg_560_pp0_iter2_reg; + icmp_ln213_reg_560_pp0_iter4_reg <= icmp_ln213_reg_560_pp0_iter3_reg; + icmp_ln213_reg_560_pp0_iter5_reg <= icmp_ln213_reg_560_pp0_iter4_reg; + icmp_ln213_reg_560_pp0_iter6_reg <= icmp_ln213_reg_560_pp0_iter5_reg; + icmp_ln213_reg_560_pp0_iter7_reg <= icmp_ln213_reg_560_pp0_iter6_reg; + icmp_ln213_reg_560_pp0_iter8_reg <= icmp_ln213_reg_560_pp0_iter7_reg; + icmp_ln213_reg_560_pp0_iter9_reg <= icmp_ln213_reg_560_pp0_iter8_reg; + tmp_248_i_i_reg_602_pp0_iter2_reg <= tmp_248_i_i_reg_602; + tmp_248_i_i_reg_602_pp0_iter3_reg <= tmp_248_i_i_reg_602_pp0_iter2_reg; + tmp_248_i_i_reg_602_pp0_iter4_reg <= tmp_248_i_i_reg_602_pp0_iter3_reg; + tmp_248_i_i_reg_602_pp0_iter5_reg <= tmp_248_i_i_reg_602_pp0_iter4_reg; + tmp_248_i_i_reg_602_pp0_iter6_reg <= tmp_248_i_i_reg_602_pp0_iter5_reg; + tmp_248_i_i_reg_602_pp0_iter7_reg <= tmp_248_i_i_reg_602_pp0_iter6_reg; + tmp_248_i_i_reg_602_pp0_iter8_reg <= tmp_248_i_i_reg_602_pp0_iter7_reg; + tmp_249_i_i_reg_607_pp0_iter10_reg <= tmp_249_i_i_reg_607_pp0_iter9_reg; + tmp_249_i_i_reg_607_pp0_iter11_reg <= tmp_249_i_i_reg_607_pp0_iter10_reg; + tmp_249_i_i_reg_607_pp0_iter12_reg <= tmp_249_i_i_reg_607_pp0_iter11_reg; + tmp_249_i_i_reg_607_pp0_iter13_reg <= tmp_249_i_i_reg_607_pp0_iter12_reg; + tmp_249_i_i_reg_607_pp0_iter2_reg <= tmp_249_i_i_reg_607; + tmp_249_i_i_reg_607_pp0_iter3_reg <= tmp_249_i_i_reg_607_pp0_iter2_reg; + tmp_249_i_i_reg_607_pp0_iter4_reg <= tmp_249_i_i_reg_607_pp0_iter3_reg; + tmp_249_i_i_reg_607_pp0_iter5_reg <= tmp_249_i_i_reg_607_pp0_iter4_reg; + tmp_249_i_i_reg_607_pp0_iter6_reg <= tmp_249_i_i_reg_607_pp0_iter5_reg; + tmp_249_i_i_reg_607_pp0_iter7_reg <= tmp_249_i_i_reg_607_pp0_iter6_reg; + tmp_249_i_i_reg_607_pp0_iter8_reg <= tmp_249_i_i_reg_607_pp0_iter7_reg; + tmp_249_i_i_reg_607_pp0_iter9_reg <= tmp_249_i_i_reg_607_pp0_iter8_reg; + trunc_ln219_reg_564_pp0_iter10_reg <= trunc_ln219_reg_564_pp0_iter9_reg; + trunc_ln219_reg_564_pp0_iter11_reg <= trunc_ln219_reg_564_pp0_iter10_reg; + trunc_ln219_reg_564_pp0_iter12_reg <= trunc_ln219_reg_564_pp0_iter11_reg; + trunc_ln219_reg_564_pp0_iter13_reg <= trunc_ln219_reg_564_pp0_iter12_reg; + trunc_ln219_reg_564_pp0_iter14_reg <= trunc_ln219_reg_564_pp0_iter13_reg; + trunc_ln219_reg_564_pp0_iter15_reg <= trunc_ln219_reg_564_pp0_iter14_reg; + trunc_ln219_reg_564_pp0_iter16_reg <= trunc_ln219_reg_564_pp0_iter15_reg; + trunc_ln219_reg_564_pp0_iter17_reg <= trunc_ln219_reg_564_pp0_iter16_reg; + trunc_ln219_reg_564_pp0_iter18_reg <= trunc_ln219_reg_564_pp0_iter17_reg; + trunc_ln219_reg_564_pp0_iter19_reg <= trunc_ln219_reg_564_pp0_iter18_reg; + trunc_ln219_reg_564_pp0_iter20_reg <= trunc_ln219_reg_564_pp0_iter19_reg; + trunc_ln219_reg_564_pp0_iter21_reg <= trunc_ln219_reg_564_pp0_iter20_reg; + trunc_ln219_reg_564_pp0_iter2_reg <= trunc_ln219_reg_564_pp0_iter1_reg; + trunc_ln219_reg_564_pp0_iter3_reg <= trunc_ln219_reg_564_pp0_iter2_reg; + trunc_ln219_reg_564_pp0_iter4_reg <= trunc_ln219_reg_564_pp0_iter3_reg; + trunc_ln219_reg_564_pp0_iter5_reg <= trunc_ln219_reg_564_pp0_iter4_reg; + trunc_ln219_reg_564_pp0_iter6_reg <= trunc_ln219_reg_564_pp0_iter5_reg; + trunc_ln219_reg_564_pp0_iter7_reg <= trunc_ln219_reg_564_pp0_iter6_reg; + trunc_ln219_reg_564_pp0_iter8_reg <= trunc_ln219_reg_564_pp0_iter7_reg; + trunc_ln219_reg_564_pp0_iter9_reg <= trunc_ln219_reg_564_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_560_pp0_iter12_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + normalized_reg_632 <= grp_fu_264_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter22 == 1'b1) & (icmp_ln213_reg_560_pp0_iter21_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + outputs_0_010_reg_220 <= outputs_0_1_fu_482_p3; + outputs_1_011_reg_208 <= outputs_1_1_fu_498_p3; + outputs_2_09_reg_232 <= outputs_2_1_fu_458_p3; + outputs_3_08_reg_244 <= outputs_3_1_fu_450_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_560_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sub_i_i_i_reg_622 <= grp_fu_260_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_reg_560 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + tmp_248_i_i_reg_602 <= {{adjustments_q0[31:16]}}; + tmp_249_i_i_reg_607 <= {{adjustments_q0[47:32]}}; + trunc_ln220_reg_597 <= trunc_ln220_fu_356_p1; + val_in_assign_reg_612 <= val_in_assign_fu_380_p6; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + trunc_ln219_reg_564 <= trunc_ln219_fu_284_p1; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + trunc_ln235_reg_550 <= trunc_ln235_fu_268_p1; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0))) begin + ap_condition_pp0_exit_iter21_state23 = 1'b1; + end else begin + ap_condition_pp0_exit_iter21_state23 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_out_blk_n = input_indices_23_out_full_n; + end else begin + input_indices_23_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_out_write = 1'b1; + end else begin + input_indices_23_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state25; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state25 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign activated_fu_412_p3 = ((p_Result_s_fu_404_p3[0:0] == 1'b1) ? 16'd0 : biased_reg_642); + +assign add_ln213_fu_272_p2 = (o_reg_197 + 3'd1); + +assign adjustments_address0 = zext_ln220_fu_295_p1; + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state25 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = outputs_0_010_reg_220; + +assign ap_return_1 = outputs_1_011_reg_208; + +assign ap_return_2 = outputs_2_09_reg_232; + +assign ap_return_3 = outputs_3_08_reg_244; + +assign data_V_fu_401_p1 = biased_reg_642; + +assign grp_fu_256_p1 = tmp_249_i_i_reg_607_pp0_iter13_reg; + +assign grp_fu_260_p1 = trunc_ln220_reg_597; + +assign grp_fu_264_p1 = tmp_248_i_i_reg_602_pp0_iter8_reg; + +assign icmp_ln213_fu_278_p2 = ((o_reg_197 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln223_10_fu_445_p2 = ((trunc_ln219_reg_564_pp0_iter21_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln223_9_fu_432_p2 = ((trunc_ln219_reg_564_pp0_iter21_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln223_fu_419_p2 = ((trunc_ln219_reg_564_pp0_iter21_reg == 2'd0) ? 1'b1 : 1'b0); + +assign input_indices_23_out_din = input_indices_23_dout; + +assign ochan_fu_288_p3 = {{trunc_ln235_reg_550}, {trunc_ln219_fu_284_p1}}; + +assign outputs_0_1_fu_482_p3 = ((icmp_ln223_10_fu_445_p2[0:0] == 1'b1) ? outputs_0_010_reg_220 : select_ln223_19_fu_474_p3); + +assign outputs_1_1_fu_498_p3 = ((icmp_ln223_10_fu_445_p2[0:0] == 1'b1) ? outputs_1_011_reg_208 : select_ln223_20_fu_490_p3); + +assign outputs_2_1_fu_458_p3 = ((icmp_ln223_10_fu_445_p2[0:0] == 1'b1) ? activated_fu_412_p3 : outputs_2_09_reg_232); + +assign outputs_3_1_fu_450_p3 = ((icmp_ln223_10_fu_445_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : select_ln223_17_fu_437_p3); + +assign p_Result_s_fu_404_p3 = data_V_fu_401_p1[32'd15]; + +assign select_ln223_17_fu_437_p3 = ((icmp_ln223_9_fu_432_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : select_ln223_fu_424_p3); + +assign select_ln223_18_fu_466_p3 = ((icmp_ln223_fu_419_p2[0:0] == 1'b1) ? activated_fu_412_p3 : outputs_0_010_reg_220); + +assign select_ln223_19_fu_474_p3 = ((icmp_ln223_9_fu_432_p2[0:0] == 1'b1) ? outputs_0_010_reg_220 : select_ln223_18_fu_466_p3); + +assign select_ln223_20_fu_490_p3 = ((icmp_ln223_9_fu_432_p2[0:0] == 1'b1) ? activated_fu_412_p3 : outputs_1_011_reg_208); + +assign select_ln223_fu_424_p3 = ((icmp_ln223_fu_419_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : activated_fu_412_p3); + +assign trunc_ln219_fu_284_p1 = o_reg_197[1:0]; + +assign trunc_ln220_fu_356_p1 = adjustments_q0[15:0]; + +assign trunc_ln235_fu_268_p1 = input_indices_23_dout[2:0]; + +assign zext_ln220_fu_295_p1 = ochan_fu_288_p3; + +endmodule //td_fused_top_tdf2_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_0_address0, + ifmap_vec_0_ce0, + ifmap_vec_0_q0, + ifmap_vec_1_address0, + ifmap_vec_1_ce0, + ifmap_vec_1_q0, + weight_vecs_0_0_address0, + weight_vecs_0_0_ce0, + weight_vecs_0_0_q0, + weight_vecs_0_1_address0, + weight_vecs_0_1_ce0, + weight_vecs_0_1_q0, + weight_vecs_1_0_address0, + weight_vecs_1_0_ce0, + weight_vecs_1_0_q0, + weight_vecs_1_1_address0, + weight_vecs_1_1_ce0, + weight_vecs_1_1_q0, + weight_vecs_2_0_address0, + weight_vecs_2_0_ce0, + weight_vecs_2_0_q0, + weight_vecs_2_1_address0, + weight_vecs_2_1_ce0, + weight_vecs_2_1_q0, + weight_vecs_3_0_address0, + weight_vecs_3_0_ce0, + weight_vecs_3_0_q0, + weight_vecs_3_1_address0, + weight_vecs_3_1_ce0, + weight_vecs_3_1_q0, + products_0_0_address0, + products_0_0_ce0, + products_0_0_we0, + products_0_0_d0, + products_0_1_address0, + products_0_1_ce0, + products_0_1_we0, + products_0_1_d0, + products_1_0_address0, + products_1_0_ce0, + products_1_0_we0, + products_1_0_d0, + products_1_1_address0, + products_1_1_ce0, + products_1_1_we0, + products_1_1_d0, + products_2_0_address0, + products_2_0_ce0, + products_2_0_we0, + products_2_0_d0, + products_2_1_address0, + products_2_1_ce0, + products_2_1_we0, + products_2_1_d0, + products_3_0_address0, + products_3_0_ce0, + products_3_0_we0, + products_3_0_d0, + products_3_1_address0, + products_3_1_ce0, + products_3_1_we0, + products_3_1_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state11 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [6:0] ifmap_vec_0_address0; +output ifmap_vec_0_ce0; +input [15:0] ifmap_vec_0_q0; +output [6:0] ifmap_vec_1_address0; +output ifmap_vec_1_ce0; +input [15:0] ifmap_vec_1_q0; +output [6:0] weight_vecs_0_0_address0; +output weight_vecs_0_0_ce0; +input [15:0] weight_vecs_0_0_q0; +output [6:0] weight_vecs_0_1_address0; +output weight_vecs_0_1_ce0; +input [15:0] weight_vecs_0_1_q0; +output [6:0] weight_vecs_1_0_address0; +output weight_vecs_1_0_ce0; +input [15:0] weight_vecs_1_0_q0; +output [6:0] weight_vecs_1_1_address0; +output weight_vecs_1_1_ce0; +input [15:0] weight_vecs_1_1_q0; +output [6:0] weight_vecs_2_0_address0; +output weight_vecs_2_0_ce0; +input [15:0] weight_vecs_2_0_q0; +output [6:0] weight_vecs_2_1_address0; +output weight_vecs_2_1_ce0; +input [15:0] weight_vecs_2_1_q0; +output [6:0] weight_vecs_3_0_address0; +output weight_vecs_3_0_ce0; +input [15:0] weight_vecs_3_0_q0; +output [6:0] weight_vecs_3_1_address0; +output weight_vecs_3_1_ce0; +input [15:0] weight_vecs_3_1_q0; +output [6:0] products_0_0_address0; +output products_0_0_ce0; +output products_0_0_we0; +output [15:0] products_0_0_d0; +output [6:0] products_0_1_address0; +output products_0_1_ce0; +output products_0_1_we0; +output [15:0] products_0_1_d0; +output [6:0] products_1_0_address0; +output products_1_0_ce0; +output products_1_0_we0; +output [15:0] products_1_0_d0; +output [6:0] products_1_1_address0; +output products_1_1_ce0; +output products_1_1_we0; +output [15:0] products_1_1_d0; +output [6:0] products_2_0_address0; +output products_2_0_ce0; +output products_2_0_we0; +output [15:0] products_2_0_d0; +output [6:0] products_2_1_address0; +output products_2_1_ce0; +output products_2_1_we0; +output [15:0] products_2_1_d0; +output [6:0] products_3_0_address0; +output products_3_0_ce0; +output products_3_0_we0; +output [15:0] products_3_0_d0; +output [6:0] products_3_1_address0; +output products_3_1_ce0; +output products_3_1_we0; +output [15:0] products_3_1_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_0_ce0; +reg ifmap_vec_1_ce0; +reg weight_vecs_0_0_ce0; +reg weight_vecs_0_1_ce0; +reg weight_vecs_1_0_ce0; +reg weight_vecs_1_1_ce0; +reg weight_vecs_2_0_ce0; +reg weight_vecs_2_1_ce0; +reg weight_vecs_3_0_ce0; +reg weight_vecs_3_1_ce0; +reg products_0_0_ce0; +reg products_0_0_we0; +reg products_0_1_ce0; +reg products_0_1_we0; +reg products_1_0_ce0; +reg products_1_0_we0; +reg products_1_1_ce0; +reg products_1_1_we0; +reg products_2_0_ce0; +reg products_2_0_we0; +reg products_2_1_ce0; +reg products_2_1_we0; +reg products_3_0_ce0; +reg products_3_0_we0; +reg products_3_1_ce0; +reg products_3_1_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [6:0] indvar_flatten17_reg_334; +reg [1:0] ii_reg_345; +reg [5:0] indvar_flatten_reg_356; +reg [1:0] jj_reg_367; +reg [4:0] ic_reg_378; +wire [6:0] add_ln147_5_fu_421_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln147_fu_455_p2; +reg [0:0] icmp_ln147_reg_730; +reg [0:0] icmp_ln147_reg_730_pp0_iter1_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter2_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter3_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter4_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter5_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter6_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter7_reg; +wire [1:0] select_ln147_19_fu_489_p3; +reg [1:0] select_ln147_19_reg_734; +wire [1:0] select_ln148_13_fu_591_p3; +reg [1:0] select_ln148_13_reg_739; +wire [5:0] empty_127_fu_603_p2; +reg [5:0] empty_127_reg_744; +wire [3:0] select_ln148_14_fu_619_p3; +reg [3:0] select_ln148_14_reg_749; +reg [3:0] select_ln148_14_reg_749_pp0_iter1_reg; +reg [3:0] select_ln148_14_reg_749_pp0_iter2_reg; +reg [3:0] select_ln148_14_reg_749_pp0_iter3_reg; +reg [3:0] select_ln148_14_reg_749_pp0_iter4_reg; +reg [3:0] select_ln148_14_reg_749_pp0_iter5_reg; +reg [3:0] select_ln148_14_reg_749_pp0_iter6_reg; +reg [3:0] select_ln148_14_reg_749_pp0_iter7_reg; +reg [2:0] newIndex_reg_755; +reg [2:0] newIndex_reg_755_pp0_iter1_reg; +reg [2:0] newIndex_reg_755_pp0_iter2_reg; +reg [2:0] newIndex_reg_755_pp0_iter3_reg; +reg [2:0] newIndex_reg_755_pp0_iter4_reg; +reg [2:0] newIndex_reg_755_pp0_iter5_reg; +reg [2:0] newIndex_reg_755_pp0_iter6_reg; +reg [2:0] newIndex_reg_755_pp0_iter7_reg; +reg [2:0] tmp_s_reg_761; +reg [2:0] tmp_s_reg_761_pp0_iter1_reg; +reg [2:0] tmp_s_reg_761_pp0_iter2_reg; +reg [2:0] tmp_s_reg_761_pp0_iter3_reg; +reg [2:0] tmp_s_reg_761_pp0_iter4_reg; +reg [2:0] tmp_s_reg_761_pp0_iter5_reg; +reg [2:0] tmp_s_reg_761_pp0_iter6_reg; +reg [2:0] tmp_s_reg_761_pp0_iter7_reg; +wire [4:0] add_ln149_fu_657_p2; +wire [5:0] select_ln148_15_fu_669_p3; +reg [15:0] ifmap_vec_0_load_reg_826; +reg [15:0] weight_vecs_0_0_load_reg_834; +reg [15:0] weight_vecs_1_0_load_reg_839; +reg [15:0] weight_vecs_2_0_load_reg_844; +reg [15:0] weight_vecs_3_0_load_reg_849; +reg [15:0] ifmap_vec_1_load_reg_854; +reg [15:0] weight_vecs_0_1_load_reg_862; +reg [15:0] weight_vecs_1_1_load_reg_867; +reg [15:0] weight_vecs_2_1_load_reg_872; +reg [15:0] weight_vecs_3_1_load_reg_877; +wire [15:0] grp_fu_389_p2; +reg [15:0] mul_reg_882; +wire [15:0] grp_fu_393_p2; +reg [15:0] mul_1_reg_887; +wire [15:0] grp_fu_397_p2; +reg [15:0] mul_2_reg_892; +wire [15:0] grp_fu_401_p2; +reg [15:0] mul_3_reg_897; +wire [15:0] grp_fu_405_p2; +reg [15:0] mul27_1_reg_902; +wire [15:0] grp_fu_409_p2; +reg [15:0] mul27_1_1_reg_907; +wire [15:0] grp_fu_413_p2; +reg [15:0] mul27_1_2_reg_912; +wire [15:0] grp_fu_417_p2; +reg [15:0] mul27_1_3_reg_917; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg [1:0] ap_phi_mux_ii_phi_fu_349_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_371_p4; +wire [63:0] tmp_148_fu_683_p1; +wire [63:0] zext_ln153_fu_703_p1; +wire [63:0] zext_ln153_9_fu_717_p1; +wire [3:0] shl_ln_fu_431_p3; +wire [3:0] zext_ln150_fu_427_p1; +wire [3:0] sub_ln150_fu_439_p2; +wire [3:0] zext_ln150_5_fu_445_p1; +wire [0:0] icmp_ln148_fu_467_p2; +wire [1:0] add_ln147_fu_461_p2; +wire [3:0] tmp_fu_501_p3; +wire [4:0] tmp_cast_fu_509_p1; +wire [4:0] select_ln147_23_cast_fu_497_p1; +wire [4:0] empty_126_fu_513_p2; +wire [3:0] shl_ln150_mid1_fu_527_p3; +wire [3:0] zext_ln150_10_fu_523_p1; +wire [3:0] sub_ln150_5_fu_535_p2; +wire [3:0] add_ln150_fu_449_p2; +wire [0:0] tmp_72_fu_557_p3; +wire [0:0] xor_ln149_fu_565_p2; +wire [1:0] select_ln147_fu_473_p3; +wire [0:0] or_ln147_fu_571_p2; +wire [4:0] select_ln147_18_fu_481_p3; +wire [1:0] add_ln148_fu_577_p2; +wire [5:0] sext_ln150_fu_519_p1; +wire [5:0] select_ln148_17_cast_fu_599_p1; +wire [3:0] select_ln147_20_fu_541_p3; +wire [3:0] zext_ln150_11_fu_609_p1; +wire [3:0] select_ln147_21_fu_549_p3; +wire [3:0] add_ln150_5_fu_613_p2; +wire [4:0] select_ln148_fu_583_p3; +wire [3:0] trunc_ln149_fu_627_p1; +wire [3:0] or_ln150_fu_641_p2; +wire [5:0] add_ln148_5_fu_663_p2; +wire [8:0] tmp_73_fu_677_p3; +wire [6:0] lshr_ln_fu_697_p3; +wire [6:0] lshr_ln153_9_fu_711_p3; +wire ap_CS_fsm_state11; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U237( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_826), + .din1(weight_vecs_0_0_load_reg_834), + .dout(grp_fu_389_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U238( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_826), + .din1(weight_vecs_1_0_load_reg_839), + .dout(grp_fu_393_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U239( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_826), + .din1(weight_vecs_2_0_load_reg_844), + .dout(grp_fu_397_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U240( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_826), + .din1(weight_vecs_3_0_load_reg_849), + .dout(grp_fu_401_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U241( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_854), + .din1(weight_vecs_0_1_load_reg_862), + .dout(grp_fu_405_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U242( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_854), + .din1(weight_vecs_1_1_load_reg_867), + .dout(grp_fu_409_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U243( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_854), + .din1(weight_vecs_2_1_load_reg_872), + .dout(grp_fu_413_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U244( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_854), + .din1(weight_vecs_3_1_load_reg_877), + .dout(grp_fu_417_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_455_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ic_reg_378 <= add_ln149_fu_657_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_reg_378 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_730 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_345 <= select_ln147_19_reg_734; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_345 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_455_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten17_reg_334 <= add_ln147_5_fu_421_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten17_reg_334 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_455_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten_reg_356 <= select_ln148_15_fu_669_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_356 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_730 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_367 <= select_ln148_13_reg_739; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_367 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_455_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + empty_127_reg_744 <= empty_127_fu_603_p2; + newIndex_reg_755 <= {{select_ln148_fu_583_p3[3:1]}}; + select_ln148_14_reg_749 <= select_ln148_14_fu_619_p3; + tmp_s_reg_761 <= {{or_ln150_fu_641_p2[3:1]}}; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln147_reg_730 <= icmp_ln147_fu_455_p2; + icmp_ln147_reg_730_pp0_iter1_reg <= icmp_ln147_reg_730; + newIndex_reg_755_pp0_iter1_reg <= newIndex_reg_755; + select_ln148_14_reg_749_pp0_iter1_reg <= select_ln148_14_reg_749; + tmp_s_reg_761_pp0_iter1_reg <= tmp_s_reg_761; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln147_reg_730_pp0_iter2_reg <= icmp_ln147_reg_730_pp0_iter1_reg; + icmp_ln147_reg_730_pp0_iter3_reg <= icmp_ln147_reg_730_pp0_iter2_reg; + icmp_ln147_reg_730_pp0_iter4_reg <= icmp_ln147_reg_730_pp0_iter3_reg; + icmp_ln147_reg_730_pp0_iter5_reg <= icmp_ln147_reg_730_pp0_iter4_reg; + icmp_ln147_reg_730_pp0_iter6_reg <= icmp_ln147_reg_730_pp0_iter5_reg; + icmp_ln147_reg_730_pp0_iter7_reg <= icmp_ln147_reg_730_pp0_iter6_reg; + newIndex_reg_755_pp0_iter2_reg <= newIndex_reg_755_pp0_iter1_reg; + newIndex_reg_755_pp0_iter3_reg <= newIndex_reg_755_pp0_iter2_reg; + newIndex_reg_755_pp0_iter4_reg <= newIndex_reg_755_pp0_iter3_reg; + newIndex_reg_755_pp0_iter5_reg <= newIndex_reg_755_pp0_iter4_reg; + newIndex_reg_755_pp0_iter6_reg <= newIndex_reg_755_pp0_iter5_reg; + newIndex_reg_755_pp0_iter7_reg <= newIndex_reg_755_pp0_iter6_reg; + select_ln148_14_reg_749_pp0_iter2_reg <= select_ln148_14_reg_749_pp0_iter1_reg; + select_ln148_14_reg_749_pp0_iter3_reg <= select_ln148_14_reg_749_pp0_iter2_reg; + select_ln148_14_reg_749_pp0_iter4_reg <= select_ln148_14_reg_749_pp0_iter3_reg; + select_ln148_14_reg_749_pp0_iter5_reg <= select_ln148_14_reg_749_pp0_iter4_reg; + select_ln148_14_reg_749_pp0_iter6_reg <= select_ln148_14_reg_749_pp0_iter5_reg; + select_ln148_14_reg_749_pp0_iter7_reg <= select_ln148_14_reg_749_pp0_iter6_reg; + tmp_s_reg_761_pp0_iter2_reg <= tmp_s_reg_761_pp0_iter1_reg; + tmp_s_reg_761_pp0_iter3_reg <= tmp_s_reg_761_pp0_iter2_reg; + tmp_s_reg_761_pp0_iter4_reg <= tmp_s_reg_761_pp0_iter3_reg; + tmp_s_reg_761_pp0_iter5_reg <= tmp_s_reg_761_pp0_iter4_reg; + tmp_s_reg_761_pp0_iter6_reg <= tmp_s_reg_761_pp0_iter5_reg; + tmp_s_reg_761_pp0_iter7_reg <= tmp_s_reg_761_pp0_iter6_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_730_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_load_reg_826 <= ifmap_vec_0_q0; + ifmap_vec_1_load_reg_854 <= ifmap_vec_1_q0; + weight_vecs_0_0_load_reg_834 <= weight_vecs_0_0_q0; + weight_vecs_0_1_load_reg_862 <= weight_vecs_0_1_q0; + weight_vecs_1_0_load_reg_839 <= weight_vecs_1_0_q0; + weight_vecs_1_1_load_reg_867 <= weight_vecs_1_1_q0; + weight_vecs_2_0_load_reg_844 <= weight_vecs_2_0_q0; + weight_vecs_2_1_load_reg_872 <= weight_vecs_2_1_q0; + weight_vecs_3_0_load_reg_849 <= weight_vecs_3_0_q0; + weight_vecs_3_1_load_reg_877 <= weight_vecs_3_1_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_730_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul27_1_1_reg_907 <= grp_fu_409_p2; + mul27_1_2_reg_912 <= grp_fu_413_p2; + mul27_1_3_reg_917 <= grp_fu_417_p2; + mul27_1_reg_902 <= grp_fu_405_p2; + mul_1_reg_887 <= grp_fu_393_p2; + mul_2_reg_892 <= grp_fu_397_p2; + mul_3_reg_897 <= grp_fu_401_p2; + mul_reg_882 <= grp_fu_389_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_455_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln147_19_reg_734 <= select_ln147_19_fu_489_p3; + select_ln148_13_reg_739 <= select_ln148_13_fu_591_p3; + end +end + +always @ (*) begin + if ((icmp_ln147_fu_455_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_730 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_349_p4 = select_ln147_19_reg_734; + end else begin + ap_phi_mux_ii_phi_fu_349_p4 = ii_reg_345; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_730 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_371_p4 = select_ln148_13_reg_739; + end else begin + ap_phi_mux_jj_phi_fu_371_p4 = jj_reg_367; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_1_ce0 = 1'b1; + end else begin + ifmap_vec_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_0_ce0 = 1'b1; + end else begin + products_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_0_we0 = 1'b1; + end else begin + products_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_1_ce0 = 1'b1; + end else begin + products_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_1_we0 = 1'b1; + end else begin + products_0_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_0_ce0 = 1'b1; + end else begin + products_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_0_we0 = 1'b1; + end else begin + products_1_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_1_ce0 = 1'b1; + end else begin + products_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_1_we0 = 1'b1; + end else begin + products_1_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_0_ce0 = 1'b1; + end else begin + products_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_0_we0 = 1'b1; + end else begin + products_2_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_1_ce0 = 1'b1; + end else begin + products_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_1_we0 = 1'b1; + end else begin + products_2_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_0_ce0 = 1'b1; + end else begin + products_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_0_we0 = 1'b1; + end else begin + products_3_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_1_ce0 = 1'b1; + end else begin + products_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_1_we0 = 1'b1; + end else begin + products_3_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_ce0 = 1'b1; + end else begin + weight_vecs_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_ce0 = 1'b1; + end else begin + weight_vecs_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_ce0 = 1'b1; + end else begin + weight_vecs_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_0_ce0 = 1'b1; + end else begin + weight_vecs_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_1_ce0 = 1'b1; + end else begin + weight_vecs_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_0_ce0 = 1'b1; + end else begin + weight_vecs_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_1_ce0 = 1'b1; + end else begin + weight_vecs_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln147_fu_455_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter8 == 1'b1) & (ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter8 == 1'b1) & (ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln147_fu_455_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state11; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_5_fu_421_p2 = (indvar_flatten17_reg_334 + 7'd1); + +assign add_ln147_fu_461_p2 = (ap_phi_mux_ii_phi_fu_349_p4 + 2'd1); + +assign add_ln148_5_fu_663_p2 = (indvar_flatten_reg_356 + 6'd1); + +assign add_ln148_fu_577_p2 = (select_ln147_fu_473_p3 + 2'd1); + +assign add_ln149_fu_657_p2 = (select_ln148_fu_583_p3 + 5'd2); + +assign add_ln150_5_fu_613_p2 = (select_ln147_20_fu_541_p3 + zext_ln150_11_fu_609_p1); + +assign add_ln150_fu_449_p2 = (sub_ln150_fu_439_p2 + zext_ln150_5_fu_445_p1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign empty_126_fu_513_p2 = (tmp_cast_fu_509_p1 - select_ln147_23_cast_fu_497_p1); + +assign empty_127_fu_603_p2 = ((sext_ln150_fu_519_p1) + (select_ln148_17_cast_fu_599_p1)); + +assign icmp_ln147_fu_455_p2 = ((indvar_flatten17_reg_334 == 7'd72) ? 1'b1 : 1'b0); + +assign icmp_ln148_fu_467_p2 = ((indvar_flatten_reg_356 == 6'd24) ? 1'b1 : 1'b0); + +assign ifmap_vec_0_address0 = tmp_148_fu_683_p1; + +assign ifmap_vec_1_address0 = tmp_148_fu_683_p1; + +assign lshr_ln153_9_fu_711_p3 = {{select_ln148_14_reg_749_pp0_iter7_reg}, {tmp_s_reg_761_pp0_iter7_reg}}; + +assign lshr_ln_fu_697_p3 = {{select_ln148_14_reg_749_pp0_iter7_reg}, {newIndex_reg_755_pp0_iter7_reg}}; + +assign or_ln147_fu_571_p2 = (xor_ln149_fu_565_p2 | icmp_ln148_fu_467_p2); + +assign or_ln150_fu_641_p2 = (trunc_ln149_fu_627_p1 | 4'd1); + +assign products_0_0_address0 = zext_ln153_fu_703_p1; + +assign products_0_0_d0 = mul_reg_882; + +assign products_0_1_address0 = zext_ln153_9_fu_717_p1; + +assign products_0_1_d0 = mul27_1_reg_902; + +assign products_1_0_address0 = zext_ln153_fu_703_p1; + +assign products_1_0_d0 = mul_1_reg_887; + +assign products_1_1_address0 = zext_ln153_9_fu_717_p1; + +assign products_1_1_d0 = mul27_1_1_reg_907; + +assign products_2_0_address0 = zext_ln153_fu_703_p1; + +assign products_2_0_d0 = mul_2_reg_892; + +assign products_2_1_address0 = zext_ln153_9_fu_717_p1; + +assign products_2_1_d0 = mul27_1_2_reg_912; + +assign products_3_0_address0 = zext_ln153_fu_703_p1; + +assign products_3_0_d0 = mul_3_reg_897; + +assign products_3_1_address0 = zext_ln153_9_fu_717_p1; + +assign products_3_1_d0 = mul27_1_3_reg_917; + +assign select_ln147_18_fu_481_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? 5'd0 : ic_reg_378); + +assign select_ln147_19_fu_489_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? add_ln147_fu_461_p2 : ap_phi_mux_ii_phi_fu_349_p4); + +assign select_ln147_20_fu_541_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? sub_ln150_5_fu_535_p2 : sub_ln150_fu_439_p2); + +assign select_ln147_21_fu_549_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? sub_ln150_5_fu_535_p2 : add_ln150_fu_449_p2); + +assign select_ln147_23_cast_fu_497_p1 = select_ln147_19_fu_489_p3; + +assign select_ln147_fu_473_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_371_p4); + +assign select_ln148_13_fu_591_p3 = ((or_ln147_fu_571_p2[0:0] == 1'b1) ? select_ln147_fu_473_p3 : add_ln148_fu_577_p2); + +assign select_ln148_14_fu_619_p3 = ((or_ln147_fu_571_p2[0:0] == 1'b1) ? select_ln147_21_fu_549_p3 : add_ln150_5_fu_613_p2); + +assign select_ln148_15_fu_669_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? 6'd1 : add_ln148_5_fu_663_p2); + +assign select_ln148_17_cast_fu_599_p1 = select_ln148_13_fu_591_p3; + +assign select_ln148_fu_583_p3 = ((or_ln147_fu_571_p2[0:0] == 1'b1) ? select_ln147_18_fu_481_p3 : 5'd0); + +assign sext_ln150_fu_519_p1 = (empty_126_fu_513_p2); + +assign shl_ln150_mid1_fu_527_p3 = {{add_ln147_fu_461_p2}, {2'd0}}; + +assign shl_ln_fu_431_p3 = {{ap_phi_mux_ii_phi_fu_349_p4}, {2'd0}}; + +assign sub_ln150_5_fu_535_p2 = (shl_ln150_mid1_fu_527_p3 - zext_ln150_10_fu_523_p1); + +assign sub_ln150_fu_439_p2 = (shl_ln_fu_431_p3 - zext_ln150_fu_427_p1); + +assign tmp_148_fu_683_p1 = (tmp_73_fu_677_p3); + +assign tmp_72_fu_557_p3 = ic_reg_378[32'd4]; + +assign tmp_73_fu_677_p3 = {{empty_127_reg_744}, {newIndex_reg_755}}; + +assign tmp_cast_fu_509_p1 = tmp_fu_501_p3; + +assign tmp_fu_501_p3 = {{select_ln147_19_fu_489_p3}, {2'd0}}; + +assign trunc_ln149_fu_627_p1 = select_ln148_fu_583_p3[3:0]; + +assign weight_vecs_0_0_address0 = tmp_148_fu_683_p1; + +assign weight_vecs_0_1_address0 = tmp_148_fu_683_p1; + +assign weight_vecs_1_0_address0 = tmp_148_fu_683_p1; + +assign weight_vecs_1_1_address0 = tmp_148_fu_683_p1; + +assign weight_vecs_2_0_address0 = tmp_148_fu_683_p1; + +assign weight_vecs_2_1_address0 = tmp_148_fu_683_p1; + +assign weight_vecs_3_0_address0 = tmp_148_fu_683_p1; + +assign weight_vecs_3_1_address0 = tmp_148_fu_683_p1; + +assign xor_ln149_fu_565_p2 = (tmp_72_fu_557_p3 ^ 1'd1); + +assign zext_ln150_10_fu_523_p1 = add_ln147_fu_461_p2; + +assign zext_ln150_11_fu_609_p1 = add_ln148_fu_577_p2; + +assign zext_ln150_5_fu_445_p1 = ap_phi_mux_jj_phi_fu_371_p4; + +assign zext_ln150_fu_427_p1 = ap_phi_mux_ii_phi_fu_349_p4; + +assign zext_ln153_9_fu_717_p1 = lshr_ln153_9_fu_711_p3; + +assign zext_ln153_fu_703_p1 = lshr_ln_fu_697_p3; + +endmodule //td_fused_top_tdf2_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf2_filters_0_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 32; +parameter AWIDTH = 10; +parameter MEM_SIZE = 576; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf2_filters_0( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd32; +parameter AddressRange = 32'd576; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf2_filters_0_ram td_fused_top_tdf2_filters_0_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + module td_fused_top_tdf2_filters_1_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 32; +parameter AWIDTH = 10; +parameter MEM_SIZE = 576; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf2_filters_1_rom.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf2_filters_1( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd32; +parameter AddressRange = 32'd576; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +td_fused_top_tdf2_filters_1_rom td_fused_top_tdf2_filters_1_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + input_indices_2_out_din, + input_indices_2_out_full_n, + input_indices_2_out_write, + input_indices_2_out1_din, + input_indices_2_out1_full_n, + input_indices_2_out1_write, + output_indices_0_din, + output_indices_0_full_n, + output_indices_0_write, + output_indices_1_din, + output_indices_1_full_n, + output_indices_1_write, + resetMaximum_din, + resetMaximum_full_n, + resetMaximum_write, + storeOutput_din, + storeOutput_full_n, + storeOutput_write, + ap_return_0, + ap_return_1 +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [2:0] input_indices_2_out_din; +input input_indices_2_out_full_n; +output input_indices_2_out_write; +output [4:0] input_indices_2_out1_din; +input input_indices_2_out1_full_n; +output input_indices_2_out1_write; +output [5:0] output_indices_0_din; +input output_indices_0_full_n; +output output_indices_0_write; +output [11:0] output_indices_1_din; +input output_indices_1_full_n; +output output_indices_1_write; +output resetMaximum_din; +input resetMaximum_full_n; +output resetMaximum_write; +output storeOutput_din; +input storeOutput_full_n; +output storeOutput_write; +output [15:0] ap_return_0; +output [15:0] ap_return_1; + +reg ap_done; +reg ap_idle; +reg start_write; +reg input_indices_2_out_write; +reg input_indices_2_out1_write; +reg output_indices_0_write; +reg output_indices_1_write; +reg resetMaximum_write; +reg storeOutput_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [1:0] i_p_2; +reg [1:0] j_p_2; +reg [15:0] i_6; +reg [15:0] j_6; +reg [15:0] k_6; +reg [15:0] i_out_2; +reg [15:0] j_out_2; +reg input_indices_2_out_blk_n; +reg input_indices_2_out1_blk_n; +reg output_indices_0_blk_n; +reg output_indices_1_blk_n; +reg resetMaximum_blk_n; +reg storeOutput_blk_n; +wire [1:0] select_ln172_fu_344_p3; +reg ap_block_state1; +wire [0:0] or_ln172_fu_318_p2; +wire [1:0] select_ln172_5_fu_352_p3; +wire [15:0] select_ln177_fu_284_p3; +wire [0:0] and_ln172_2_fu_312_p2; +wire [15:0] select_ln172_6_fu_366_p3; +wire [0:0] and_ln162_fu_360_p2; +wire [15:0] select_ln172_7_fu_394_p3; +wire [0:0] and_ln165_fu_300_p2; +wire [15:0] select_ln177_2_fu_292_p3; +wire [15:0] select_ln172_8_fu_402_p3; +wire [1:0] or_ln154_fu_128_p2; +wire [0:0] icmp_ln155_fu_141_p2; +wire [0:0] icmp_ln155_2_fu_147_p2; +wire [15:0] zext_ln156_fu_116_p1; +wire [15:0] zext_ln157_fu_124_p1; +wire [1:0] add_ln161_fu_212_p2; +wire [1:0] add_ln164_fu_224_p2; +wire [15:0] add_ln167_fu_236_p2; +wire [15:0] add_ln171_fu_254_p2; +wire [15:0] add_ln176_fu_272_p2; +wire [0:0] icmp_ln177_fu_278_p2; +wire [15:0] add_ln175_fu_266_p2; +wire [0:0] icmp_ln162_fu_218_p2; +wire [0:0] icmp_ln165_fu_230_p2; +wire [0:0] icmp_ln168_fu_242_p2; +wire [0:0] icmp_ln172_fu_260_p2; +wire [0:0] and_ln172_fu_306_p2; +wire [0:0] xor_ln165_fu_324_p2; +wire [0:0] and_ln165_2_fu_330_p2; +wire [1:0] select_ln165_fu_336_p3; +wire [15:0] add_ln170_fu_248_p2; +wire [0:0] xor_ln168_fu_374_p2; +wire [0:0] and_ln168_fu_380_p2; +wire [15:0] select_ln168_fu_386_p3; +wire [15:0] add_ln156_fu_164_p2; +wire [15:0] add_ln157_fu_174_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_p_2 = 2'd0; +#0 j_p_2 = 2'd0; +#0 i_6 = 16'd0; +#0 j_6 = 16'd0; +#0 k_6 = 16'd0; +#0 i_out_2 = 16'd0; +#0 j_out_2 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln172_2_fu_312_p2))) begin + i_6 <= select_ln177_fu_284_p3; + i_out_2 <= select_ln177_2_fu_292_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (or_ln172_fu_318_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_p_2 <= select_ln172_fu_344_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln162_fu_360_p2))) begin + j_6 <= select_ln172_6_fu_366_p3; + j_out_2 <= select_ln172_8_fu_402_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + j_p_2 <= select_ln172_5_fu_352_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln165_fu_300_p2))) begin + k_6 <= select_ln172_7_fu_394_p3; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_blk_n = input_indices_2_out1_full_n; + end else begin + input_indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_write = 1'b1; + end else begin + input_indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_blk_n = input_indices_2_out_full_n; + end else begin + input_indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_write = 1'b1; + end else begin + input_indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_blk_n = output_indices_0_full_n; + end else begin + output_indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_write = 1'b1; + end else begin + output_indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_blk_n = output_indices_1_full_n; + end else begin + output_indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_write = 1'b1; + end else begin + output_indices_1_write = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_blk_n = resetMaximum_full_n; + end else begin + resetMaximum_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_write = 1'b1; + end else begin + resetMaximum_write = 1'b0; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_blk_n = storeOutput_full_n; + end else begin + storeOutput_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_write = 1'b1; + end else begin + storeOutput_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln156_fu_164_p2 = (i_6 + zext_ln156_fu_116_p1); + +assign add_ln157_fu_174_p2 = (j_6 + zext_ln157_fu_124_p1); + +assign add_ln161_fu_212_p2 = (j_p_2 + 2'd1); + +assign add_ln164_fu_224_p2 = (i_p_2 + 2'd1); + +assign add_ln167_fu_236_p2 = (k_6 + 16'd1); + +assign add_ln170_fu_248_p2 = (j_6 + 16'd2); + +assign add_ln171_fu_254_p2 = (j_out_2 + 16'd1); + +assign add_ln175_fu_266_p2 = (i_6 + 16'd2); + +assign add_ln176_fu_272_p2 = (i_out_2 + 16'd1); + +assign and_ln162_fu_360_p2 = (icmp_ln168_fu_242_p2 & and_ln165_fu_300_p2); + +assign and_ln165_2_fu_330_p2 = (xor_ln165_fu_324_p2 & icmp_ln162_fu_218_p2); + +assign and_ln165_fu_300_p2 = (icmp_ln165_fu_230_p2 & icmp_ln162_fu_218_p2); + +assign and_ln168_fu_380_p2 = (xor_ln168_fu_374_p2 & and_ln165_fu_300_p2); + +assign and_ln172_2_fu_312_p2 = (and_ln172_fu_306_p2 & and_ln165_fu_300_p2); + +assign and_ln172_fu_306_p2 = (icmp_ln172_fu_260_p2 & icmp_ln168_fu_242_p2); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign ap_return_0 = add_ln156_fu_164_p2; + +assign ap_return_1 = add_ln157_fu_174_p2; + +assign icmp_ln155_2_fu_147_p2 = ((j_p_2 == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln155_fu_141_p2 = ((i_p_2 == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln162_fu_218_p2 = ((add_ln161_fu_212_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln165_fu_230_p2 = ((add_ln164_fu_224_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln168_fu_242_p2 = ((add_ln167_fu_236_p2 == 16'd8) ? 1'b1 : 1'b0); + +assign icmp_ln172_fu_260_p2 = ((add_ln171_fu_254_p2 == 16'd56) ? 1'b1 : 1'b0); + +assign icmp_ln177_fu_278_p2 = ((add_ln176_fu_272_p2 == 16'd56) ? 1'b1 : 1'b0); + +assign input_indices_2_out1_din = k_6[4:0]; + +assign input_indices_2_out_din = k_6[2:0]; + +assign or_ln154_fu_128_p2 = (j_p_2 | i_p_2); + +assign or_ln172_fu_318_p2 = (icmp_ln162_fu_218_p2 | and_ln172_2_fu_312_p2); + +assign output_indices_0_din = i_out_2[5:0]; + +assign output_indices_1_din = j_out_2[11:0]; + +assign resetMaximum_din = ((or_ln154_fu_128_p2 == 2'd0) ? 1'b1 : 1'b0); + +assign select_ln165_fu_336_p3 = ((and_ln165_2_fu_330_p2[0:0] == 1'b1) ? add_ln164_fu_224_p2 : 2'd0); + +assign select_ln168_fu_386_p3 = ((and_ln168_fu_380_p2[0:0] == 1'b1) ? add_ln167_fu_236_p2 : 16'd0); + +assign select_ln172_5_fu_352_p3 = ((or_ln172_fu_318_p2[0:0] == 1'b1) ? 2'd0 : add_ln161_fu_212_p2); + +assign select_ln172_6_fu_366_p3 = ((and_ln172_2_fu_312_p2[0:0] == 1'b1) ? 16'd0 : add_ln170_fu_248_p2); + +assign select_ln172_7_fu_394_p3 = ((and_ln172_2_fu_312_p2[0:0] == 1'b1) ? 16'd0 : select_ln168_fu_386_p3); + +assign select_ln172_8_fu_402_p3 = ((and_ln172_2_fu_312_p2[0:0] == 1'b1) ? 16'd0 : add_ln171_fu_254_p2); + +assign select_ln172_fu_344_p3 = ((and_ln172_2_fu_312_p2[0:0] == 1'b1) ? 2'd0 : select_ln165_fu_336_p3); + +assign select_ln177_2_fu_292_p3 = ((icmp_ln177_fu_278_p2[0:0] == 1'b1) ? 16'd0 : add_ln176_fu_272_p2); + +assign select_ln177_fu_284_p3 = ((icmp_ln177_fu_278_p2[0:0] == 1'b1) ? 16'd0 : add_ln175_fu_266_p2); + +assign start_out = real_start; + +assign storeOutput_din = (icmp_ln155_fu_141_p2 & icmp_ln155_2_fu_147_p2); + +assign xor_ln165_fu_324_p2 = (icmp_ln165_fu_230_p2 ^ 1'd1); + +assign xor_ln168_fu_374_p2 = (icmp_ln168_fu_242_p2 ^ 1'd1); + +assign zext_ln156_fu_116_p1 = i_p_2; + +assign zext_ln157_fu_124_p1 = j_p_2; + +endmodule //td_fused_top_tdf2_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_poolOutputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + output_indices_04_dout, + output_indices_04_empty_n, + output_indices_04_read, + output_indices_15_dout, + output_indices_15_empty_n, + output_indices_15_read, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + resetMaximum6_dout, + resetMaximum6_empty_n, + resetMaximum6_read, + storeOutput7_dout, + storeOutput7_empty_n, + storeOutput7_read, + outputs_0_read, + outputs_1_read, + outputs_2_read, + outputs_3_read, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_state3 = 4'd4; +parameter ap_ST_fsm_state4 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [5:0] output_indices_04_dout; +input output_indices_04_empty_n; +output output_indices_04_read; +input [11:0] output_indices_15_dout; +input output_indices_15_empty_n; +output output_indices_15_read; +input [4:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +input [0:0] resetMaximum6_dout; +input resetMaximum6_empty_n; +output resetMaximum6_read; +input [0:0] storeOutput7_dout; +input storeOutput7_empty_n; +output storeOutput7_read; +input [15:0] outputs_0_read; +input [15:0] outputs_1_read; +input [15:0] outputs_2_read; +input [15:0] outputs_3_read; +output [14:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg output_indices_04_read; +reg output_indices_15_read; +reg input_indices_23_read; +reg resetMaximum6_read; +reg storeOutput7_read; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] max_vals_4_0; +reg [15:0] max_vals_4_1; +reg [15:0] max_vals_4_2; +reg [15:0] max_vals_4_3; +reg output_indices_04_blk_n; +wire ap_CS_fsm_state2; +reg output_indices_15_blk_n; +reg input_indices_23_blk_n; +reg resetMaximum6_blk_n; +reg storeOutput7_blk_n; +reg [5:0] output_indices_04_read_reg_281; +reg [11:0] output_indices_15_read_reg_286; +reg [4:0] input_indices_23_read_reg_291; +wire [0:0] storeOutput7_read_read_fu_110_p2; +reg [0:0] storeOutput7_read_reg_296; +wire grp_tdf2_writeOutputs_aligned_fu_116_ap_start; +wire grp_tdf2_writeOutputs_aligned_fu_116_ap_done; +wire grp_tdf2_writeOutputs_aligned_fu_116_ap_idle; +wire grp_tdf2_writeOutputs_aligned_fu_116_ap_ready; +wire [14:0] grp_tdf2_writeOutputs_aligned_fu_116_out_data_address1; +wire grp_tdf2_writeOutputs_aligned_fu_116_out_data_ce1; +wire grp_tdf2_writeOutputs_aligned_fu_116_out_data_we1; +wire [63:0] grp_tdf2_writeOutputs_aligned_fu_116_out_data_d1; +reg grp_tdf2_writeOutputs_aligned_fu_116_ap_start_reg; +wire ap_CS_fsm_state3; +wire ap_CS_fsm_state4; +wire [15:0] select_ln24_fu_179_p3; +reg ap_block_state2; +wire [15:0] select_ln24_7_fu_197_p3; +wire [15:0] select_ln24_8_fu_215_p3; +wire [15:0] select_ln24_9_fu_233_p3; +reg ap_block_state1; +wire [0:0] grp_fu_133_p2; +wire [0:0] or_ln24_fu_173_p2; +wire [0:0] grp_fu_138_p2; +wire [0:0] or_ln24_7_fu_191_p2; +wire [0:0] grp_fu_143_p2; +wire [0:0] or_ln24_8_fu_209_p2; +wire [0:0] grp_fu_148_p2; +wire [0:0] or_ln24_9_fu_227_p2; +reg grp_fu_133_ce; +reg grp_fu_138_ce; +reg grp_fu_143_ce; +reg grp_fu_148_ce; +reg ap_block_state4_on_subcall_done; +reg [3:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 max_vals_4_0 = 16'd0; +#0 max_vals_4_1 = 16'd0; +#0 max_vals_4_2 = 16'd0; +#0 max_vals_4_3 = 16'd0; +#0 grp_tdf2_writeOutputs_aligned_fu_116_ap_start_reg = 1'b0; +end + +td_fused_top_tdf2_writeOutputs_aligned grp_tdf2_writeOutputs_aligned_fu_116( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(grp_tdf2_writeOutputs_aligned_fu_116_ap_start), + .ap_done(grp_tdf2_writeOutputs_aligned_fu_116_ap_done), + .ap_idle(grp_tdf2_writeOutputs_aligned_fu_116_ap_idle), + .ap_ready(grp_tdf2_writeOutputs_aligned_fu_116_ap_ready), + .i(output_indices_04_read_reg_281), + .j(output_indices_15_read_reg_286), + .k(input_indices_23_read_reg_291), + .out_data_address1(grp_tdf2_writeOutputs_aligned_fu_116_out_data_address1), + .out_data_ce1(grp_tdf2_writeOutputs_aligned_fu_116_out_data_ce1), + .out_data_we1(grp_tdf2_writeOutputs_aligned_fu_116_out_data_we1), + .out_data_d1(grp_tdf2_writeOutputs_aligned_fu_116_out_data_d1), + .max_vals_4_0(max_vals_4_0), + .max_vals_4_1(max_vals_4_1), + .max_vals_4_2(max_vals_4_2), + .max_vals_4_3(max_vals_4_3) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U311( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_133_ce), + .din0(max_vals_4_0), + .din1(outputs_0_read), + .opcode(5'd4), + .dout(grp_fu_133_p2) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U312( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_138_ce), + .din0(max_vals_4_1), + .din1(outputs_1_read), + .opcode(5'd4), + .dout(grp_fu_138_p2) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U313( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_143_ce), + .din0(max_vals_4_2), + .din1(outputs_2_read), + .opcode(5'd4), + .dout(grp_fu_143_p2) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U314( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_148_ce), + .din0(max_vals_4_3), + .din1(outputs_3_read), + .opcode(5'd4), + .dout(grp_fu_148_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + grp_tdf2_writeOutputs_aligned_fu_116_ap_start_reg <= 1'b0; + end else begin + if ((1'b1 == ap_CS_fsm_state3)) begin + grp_tdf2_writeOutputs_aligned_fu_116_ap_start_reg <= 1'b1; + end else if ((grp_tdf2_writeOutputs_aligned_fu_116_ap_ready == 1'b1)) begin + grp_tdf2_writeOutputs_aligned_fu_116_ap_start_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + input_indices_23_read_reg_291 <= input_indices_23_dout; + output_indices_04_read_reg_281 <= output_indices_04_dout; + output_indices_15_read_reg_286 <= output_indices_15_dout; + storeOutput7_read_reg_296 <= storeOutput7_dout; + end +end + +always @ (posedge ap_clk) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + max_vals_4_0 <= select_ln24_fu_179_p3; + max_vals_4_1 <= select_ln24_7_fu_197_p3; + max_vals_4_2 <= select_ln24_8_fu_215_p3; + max_vals_4_3 <= select_ln24_9_fu_233_p3; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_133_ce = 1'b1; + end else begin + grp_fu_133_ce = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_138_ce = 1'b1; + end else begin + grp_fu_138_ce = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_143_ce = 1'b1; + end else begin + grp_fu_143_ce = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_148_ce = 1'b1; + end else begin + grp_fu_148_ce = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_04_blk_n = output_indices_04_empty_n; + end else begin + output_indices_04_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_04_read = 1'b1; + end else begin + output_indices_04_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_15_blk_n = output_indices_15_empty_n; + end else begin + output_indices_15_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_15_read = 1'b1; + end else begin + output_indices_15_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + resetMaximum6_blk_n = resetMaximum6_empty_n; + end else begin + resetMaximum6_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + resetMaximum6_read = 1'b1; + end else begin + resetMaximum6_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + storeOutput7_blk_n = storeOutput7_empty_n; + end else begin + storeOutput7_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + storeOutput7_read = 1'b1; + end else begin + storeOutput7_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_110_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_110_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state3; + end else begin + ap_NS_fsm = ap_ST_fsm_state2; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +always @ (*) begin + ap_block_state2 = ((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)); +end + +always @ (*) begin + ap_block_state4_on_subcall_done = ((grp_tdf2_writeOutputs_aligned_fu_116_ap_done == 1'b0) & (storeOutput7_read_reg_296 == 1'd1)); +end + +assign grp_tdf2_writeOutputs_aligned_fu_116_ap_start = grp_tdf2_writeOutputs_aligned_fu_116_ap_start_reg; + +assign or_ln24_7_fu_191_p2 = (resetMaximum6_dout | grp_fu_138_p2); + +assign or_ln24_8_fu_209_p2 = (resetMaximum6_dout | grp_fu_143_p2); + +assign or_ln24_9_fu_227_p2 = (resetMaximum6_dout | grp_fu_148_p2); + +assign or_ln24_fu_173_p2 = (resetMaximum6_dout | grp_fu_133_p2); + +assign out_data_address1 = grp_tdf2_writeOutputs_aligned_fu_116_out_data_address1; + +assign out_data_ce1 = grp_tdf2_writeOutputs_aligned_fu_116_out_data_ce1; + +assign out_data_d1 = grp_tdf2_writeOutputs_aligned_fu_116_out_data_d1; + +assign out_data_we1 = grp_tdf2_writeOutputs_aligned_fu_116_out_data_we1; + +assign select_ln24_7_fu_197_p3 = ((or_ln24_7_fu_191_p2[0:0] == 1'b1) ? outputs_1_read : max_vals_4_1); + +assign select_ln24_8_fu_215_p3 = ((or_ln24_8_fu_209_p2[0:0] == 1'b1) ? outputs_2_read : max_vals_4_2); + +assign select_ln24_9_fu_233_p3 = ((or_ln24_9_fu_227_p2[0:0] == 1'b1) ? outputs_3_read : max_vals_4_3); + +assign select_ln24_fu_179_p3 = ((or_ln24_fu_173_p2[0:0] == 1'b1) ? outputs_0_read : max_vals_4_0); + +assign storeOutput7_read_read_fu_110_p2 = storeOutput7_dout; + +endmodule //td_fused_top_tdf2_poolOutputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_readFilters24 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_0_address0, + filter_data_0_ce0, + filter_data_0_q0, + filter_data_1_address0, + filter_data_1_ce0, + filter_data_1_q0, + filter_data_2_address0, + filter_data_2_ce0, + filter_data_2_q0, + filter_data_3_address0, + filter_data_3_ce0, + filter_data_3_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + weight_vecs_0_0_address0, + weight_vecs_0_0_ce0, + weight_vecs_0_0_we0, + weight_vecs_0_0_d0, + weight_vecs_0_1_address0, + weight_vecs_0_1_ce0, + weight_vecs_0_1_we0, + weight_vecs_0_1_d0, + weight_vecs_1_0_address0, + weight_vecs_1_0_ce0, + weight_vecs_1_0_we0, + weight_vecs_1_0_d0, + weight_vecs_1_1_address0, + weight_vecs_1_1_ce0, + weight_vecs_1_1_we0, + weight_vecs_1_1_d0, + weight_vecs_2_0_address0, + weight_vecs_2_0_ce0, + weight_vecs_2_0_we0, + weight_vecs_2_0_d0, + weight_vecs_2_1_address0, + weight_vecs_2_1_ce0, + weight_vecs_2_1_we0, + weight_vecs_2_1_d0, + weight_vecs_3_0_address0, + weight_vecs_3_0_ce0, + weight_vecs_3_0_we0, + weight_vecs_3_0_d0, + weight_vecs_3_1_address0, + weight_vecs_3_1_ce0, + weight_vecs_3_1_we0, + weight_vecs_3_1_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state6 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [9:0] filter_data_0_address0; +output filter_data_0_ce0; +input [31:0] filter_data_0_q0; +output [9:0] filter_data_1_address0; +output filter_data_1_ce0; +input [31:0] filter_data_1_q0; +output [9:0] filter_data_2_address0; +output filter_data_2_ce0; +input [31:0] filter_data_2_q0; +output [9:0] filter_data_3_address0; +output filter_data_3_ce0; +input [31:0] filter_data_3_q0; +input [2:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [6:0] weight_vecs_0_0_address0; +output weight_vecs_0_0_ce0; +output weight_vecs_0_0_we0; +output [15:0] weight_vecs_0_0_d0; +output [6:0] weight_vecs_0_1_address0; +output weight_vecs_0_1_ce0; +output weight_vecs_0_1_we0; +output [15:0] weight_vecs_0_1_d0; +output [6:0] weight_vecs_1_0_address0; +output weight_vecs_1_0_ce0; +output weight_vecs_1_0_we0; +output [15:0] weight_vecs_1_0_d0; +output [6:0] weight_vecs_1_1_address0; +output weight_vecs_1_1_ce0; +output weight_vecs_1_1_we0; +output [15:0] weight_vecs_1_1_d0; +output [6:0] weight_vecs_2_0_address0; +output weight_vecs_2_0_ce0; +output weight_vecs_2_0_we0; +output [15:0] weight_vecs_2_0_d0; +output [6:0] weight_vecs_2_1_address0; +output weight_vecs_2_1_ce0; +output weight_vecs_2_1_we0; +output [15:0] weight_vecs_2_1_d0; +output [6:0] weight_vecs_3_0_address0; +output weight_vecs_3_0_ce0; +output weight_vecs_3_0_we0; +output [15:0] weight_vecs_3_0_d0; +output [6:0] weight_vecs_3_1_address0; +output weight_vecs_3_1_ce0; +output weight_vecs_3_1_we0; +output [15:0] weight_vecs_3_1_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_0_ce0; +reg filter_data_1_ce0; +reg filter_data_2_ce0; +reg filter_data_3_ce0; +reg input_indices_23_read; +reg weight_vecs_0_0_ce0; +reg weight_vecs_0_0_we0; +reg weight_vecs_0_1_ce0; +reg weight_vecs_0_1_we0; +reg weight_vecs_1_0_ce0; +reg weight_vecs_1_0_we0; +reg weight_vecs_1_1_ce0; +reg weight_vecs_1_1_we0; +reg weight_vecs_2_0_ce0; +reg weight_vecs_2_0_we0; +reg weight_vecs_2_1_ce0; +reg weight_vecs_2_1_we0; +reg weight_vecs_3_0_ce0; +reg weight_vecs_3_0_we0; +reg weight_vecs_3_1_ce0; +reg weight_vecs_3_1_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +reg [6:0] indvar_flatten13_reg_288; +reg [1:0] ii_reg_299; +reg [5:0] indvar_flatten_reg_310; +reg [1:0] jj_reg_321; +reg [4:0] kk_reg_332; +wire [6:0] sext_ln47_fu_365_p1; +reg [6:0] sext_ln47_reg_737; +wire [6:0] add_ln47_5_fu_369_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln47_fu_375_p2; +reg [0:0] icmp_ln47_reg_747; +reg [0:0] icmp_ln47_reg_747_pp0_iter1_reg; +reg [0:0] icmp_ln47_reg_747_pp0_iter2_reg; +wire [1:0] select_ln47_10_fu_409_p3; +reg [1:0] select_ln47_10_reg_751; +wire [6:0] add_ln55_fu_421_p2; +reg [6:0] add_ln55_reg_758; +wire [1:0] select_ln48_9_fu_460_p3; +reg [1:0] select_ln48_9_reg_764; +reg [2:0] lshr_ln_reg_771; +reg [2:0] lshr_ln_reg_771_pp0_iter1_reg; +reg [2:0] lshr_ln_reg_771_pp0_iter2_reg; +wire [4:0] add_ln49_fu_478_p2; +wire [5:0] select_ln48_10_fu_490_p3; +wire [5:0] add_ln55_10_fu_554_p2; +reg [5:0] add_ln55_10_reg_787; +reg [5:0] add_ln55_10_reg_787_pp0_iter2_reg; +reg [31:0] filter_data_0_load_reg_812; +reg [31:0] filter_data_1_load_reg_817; +reg [31:0] filter_data_2_load_reg_822; +reg [31:0] filter_data_3_load_reg_827; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg [1:0] ap_phi_mux_ii_phi_fu_303_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_325_p4; +wire [63:0] tmp_44_fu_560_p3; +wire [63:0] sext_ln55_10_fu_577_p1; +wire [4:0] tmp_42_fu_347_p3; +wire [5:0] zext_ln55_28_fu_355_p1; +wire [5:0] zext_ln55_fu_343_p1; +wire [5:0] sub_ln55_fu_359_p2; +wire [0:0] icmp_ln48_fu_387_p2; +wire [1:0] add_ln47_fu_381_p2; +wire [6:0] zext_ln55_30_fu_417_p1; +wire [0:0] tmp_70_fu_426_p3; +wire [0:0] xor_ln49_fu_434_p2; +wire [1:0] select_ln47_fu_393_p3; +wire [0:0] or_ln47_fu_440_p2; +wire [4:0] select_ln47_9_fu_401_p3; +wire [1:0] add_ln48_fu_446_p2; +wire [4:0] select_ln48_fu_452_p3; +wire [5:0] add_ln48_5_fu_484_p2; +wire [8:0] tmp_69_fu_504_p3; +wire [60:0] sext_ln55_9_fu_511_p1; +wire [60:0] sext_ln55_fu_501_p1; +wire [3:0] tmp_43_fu_521_p3; +wire [4:0] zext_ln55_31_fu_528_p1; +wire [4:0] zext_ln55_29_fu_498_p1; +wire [4:0] sub_ln55_10_fu_532_p2; +wire [60:0] sub_ln55_9_fu_515_p2; +wire [60:0] zext_ln55_33_fu_545_p1; +wire [5:0] sext_ln48_fu_538_p1; +wire [5:0] zext_ln55_32_fu_542_p1; +wire [60:0] add_ln55_9_fu_548_p2; +wire [8:0] tmp_71_fu_571_p3; +wire [31:0] tmp_fu_589_p6; +wire [15:0] trunc_ln55_fu_602_p1; +wire [31:0] tmp_s_fu_611_p6; +wire [15:0] trunc_ln55_13_fu_624_p1; +wire [31:0] tmp_3_fu_633_p6; +wire [15:0] trunc_ln55_14_fu_646_p1; +wire [31:0] tmp_4_fu_655_p6; +wire [15:0] trunc_ln55_15_fu_668_p1; +wire [15:0] tmp_241_i_i_fu_677_p4; +wire [15:0] tmp_243_i_i_fu_692_p4; +wire [15:0] tmp_245_i_i_fu_707_p4; +wire [15:0] tmp_247_i_i_fu_722_p4; +wire ap_CS_fsm_state6; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +end + +td_fused_top_mux_416_32_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 32 ), + .din2_WIDTH( 32 ), + .din3_WIDTH( 32 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 32 )) +mux_416_32_1_1_U219( + .din0(filter_data_0_load_reg_812), + .din1(32'd0), + .din2(32'd0), + .din3(32'd0), + .din4(16'd0), + .dout(tmp_fu_589_p6) +); + +td_fused_top_mux_416_32_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 32 ), + .din2_WIDTH( 32 ), + .din3_WIDTH( 32 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 32 )) +mux_416_32_1_1_U220( + .din0(filter_data_1_load_reg_817), + .din1(32'd0), + .din2(32'd0), + .din3(32'd0), + .din4(16'd0), + .dout(tmp_s_fu_611_p6) +); + +td_fused_top_mux_416_32_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 32 ), + .din2_WIDTH( 32 ), + .din3_WIDTH( 32 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 32 )) +mux_416_32_1_1_U221( + .din0(filter_data_2_load_reg_822), + .din1(32'd0), + .din2(32'd0), + .din3(32'd0), + .din4(16'd0), + .dout(tmp_3_fu_633_p6) +); + +td_fused_top_mux_416_32_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 32 ), + .din2_WIDTH( 32 ), + .din3_WIDTH( 32 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 32 )) +mux_416_32_1_1_U222( + .din0(filter_data_3_load_reg_827), + .din1(32'd0), + .din2(32'd0), + .din3(32'd0), + .din4(16'd0), + .dout(tmp_4_fu_655_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_747 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_299 <= select_ln47_10_reg_751; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_299 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_375_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten13_reg_288 <= add_ln47_5_fu_369_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_288 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_375_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten_reg_310 <= select_ln48_10_fu_490_p3; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_310 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_747 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_321 <= select_ln48_9_reg_764; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_321 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_375_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + kk_reg_332 <= add_ln49_fu_478_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_332 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_747 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln55_10_reg_787 <= add_ln55_10_fu_554_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln55_10_reg_787_pp0_iter2_reg <= add_ln55_10_reg_787; + icmp_ln47_reg_747_pp0_iter2_reg <= icmp_ln47_reg_747_pp0_iter1_reg; + lshr_ln_reg_771_pp0_iter2_reg <= lshr_ln_reg_771_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_375_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln55_reg_758 <= add_ln55_fu_421_p2; + lshr_ln_reg_771 <= {{select_ln48_fu_452_p3[3:1]}}; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_747_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_0_load_reg_812 <= filter_data_0_q0; + filter_data_1_load_reg_817 <= filter_data_1_q0; + filter_data_2_load_reg_822 <= filter_data_2_q0; + filter_data_3_load_reg_827 <= filter_data_3_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln47_reg_747 <= icmp_ln47_fu_375_p2; + icmp_ln47_reg_747_pp0_iter1_reg <= icmp_ln47_reg_747; + lshr_ln_reg_771_pp0_iter1_reg <= lshr_ln_reg_771; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_375_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln47_10_reg_751 <= select_ln47_10_fu_409_p3; + select_ln48_9_reg_764 <= select_ln48_9_fu_460_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sext_ln47_reg_737 <= sext_ln47_fu_365_p1; + end +end + +always @ (*) begin + if ((icmp_ln47_fu_375_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_747 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_303_p4 = select_ln47_10_reg_751; + end else begin + ap_phi_mux_ii_phi_fu_303_p4 = ii_reg_299; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_747 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_325_p4 = select_ln48_9_reg_764; + end else begin + ap_phi_mux_jj_phi_fu_325_p4 = jj_reg_321; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_0_ce0 = 1'b1; + end else begin + filter_data_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_1_ce0 = 1'b1; + end else begin + filter_data_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_2_ce0 = 1'b1; + end else begin + filter_data_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_3_ce0 = 1'b1; + end else begin + filter_data_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_ce0 = 1'b1; + end else begin + weight_vecs_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_we0 = 1'b1; + end else begin + weight_vecs_0_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_ce0 = 1'b1; + end else begin + weight_vecs_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_we0 = 1'b1; + end else begin + weight_vecs_1_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_ce0 = 1'b1; + end else begin + weight_vecs_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_we0 = 1'b1; + end else begin + weight_vecs_1_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_0_ce0 = 1'b1; + end else begin + weight_vecs_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_0_we0 = 1'b1; + end else begin + weight_vecs_2_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_1_ce0 = 1'b1; + end else begin + weight_vecs_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_1_we0 = 1'b1; + end else begin + weight_vecs_2_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_0_ce0 = 1'b1; + end else begin + weight_vecs_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_0_we0 = 1'b1; + end else begin + weight_vecs_3_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_1_ce0 = 1'b1; + end else begin + weight_vecs_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_1_we0 = 1'b1; + end else begin + weight_vecs_3_1_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln47_fu_375_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln47_fu_375_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln47_5_fu_369_p2 = (indvar_flatten13_reg_288 + 7'd1); + +assign add_ln47_fu_381_p2 = (ap_phi_mux_ii_phi_fu_303_p4 + 2'd1); + +assign add_ln48_5_fu_484_p2 = (indvar_flatten_reg_310 + 6'd1); + +assign add_ln48_fu_446_p2 = (select_ln47_fu_393_p3 + 2'd1); + +assign add_ln49_fu_478_p2 = (select_ln48_fu_452_p3 + 5'd2); + +assign add_ln55_10_fu_554_p2 = ((sext_ln48_fu_538_p1) + (zext_ln55_32_fu_542_p1)); + +assign add_ln55_9_fu_548_p2 = (sub_ln55_9_fu_515_p2 + zext_ln55_33_fu_545_p1); + +assign add_ln55_fu_421_p2 = ((sext_ln47_reg_737) + (zext_ln55_30_fu_417_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_0_address0 = tmp_44_fu_560_p3; + +assign filter_data_1_address0 = tmp_44_fu_560_p3; + +assign filter_data_2_address0 = tmp_44_fu_560_p3; + +assign filter_data_3_address0 = tmp_44_fu_560_p3; + +assign icmp_ln47_fu_375_p2 = ((indvar_flatten13_reg_288 == 7'd72) ? 1'b1 : 1'b0); + +assign icmp_ln48_fu_387_p2 = ((indvar_flatten_reg_310 == 6'd24) ? 1'b1 : 1'b0); + +assign or_ln47_fu_440_p2 = (xor_ln49_fu_434_p2 | icmp_ln48_fu_387_p2); + +assign select_ln47_10_fu_409_p3 = ((icmp_ln48_fu_387_p2[0:0] == 1'b1) ? add_ln47_fu_381_p2 : ap_phi_mux_ii_phi_fu_303_p4); + +assign select_ln47_9_fu_401_p3 = ((icmp_ln48_fu_387_p2[0:0] == 1'b1) ? 5'd0 : kk_reg_332); + +assign select_ln47_fu_393_p3 = ((icmp_ln48_fu_387_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_325_p4); + +assign select_ln48_10_fu_490_p3 = ((icmp_ln48_fu_387_p2[0:0] == 1'b1) ? 6'd1 : add_ln48_5_fu_484_p2); + +assign select_ln48_9_fu_460_p3 = ((or_ln47_fu_440_p2[0:0] == 1'b1) ? select_ln47_fu_393_p3 : add_ln48_fu_446_p2); + +assign select_ln48_fu_452_p3 = ((or_ln47_fu_440_p2[0:0] == 1'b1) ? select_ln47_9_fu_401_p3 : 5'd0); + +assign sext_ln47_fu_365_p1 = (sub_ln55_fu_359_p2); + +assign sext_ln48_fu_538_p1 = (sub_ln55_10_fu_532_p2); + +assign sext_ln55_10_fu_577_p1 = (tmp_71_fu_571_p3); + +assign sext_ln55_9_fu_511_p1 = (tmp_69_fu_504_p3); + +assign sext_ln55_fu_501_p1 = add_ln55_reg_758; + +assign sub_ln55_10_fu_532_p2 = (zext_ln55_31_fu_528_p1 - zext_ln55_29_fu_498_p1); + +assign sub_ln55_9_fu_515_p2 = ((sext_ln55_9_fu_511_p1) - (sext_ln55_fu_501_p1)); + +assign sub_ln55_fu_359_p2 = (zext_ln55_28_fu_355_p1 - zext_ln55_fu_343_p1); + +assign tmp_241_i_i_fu_677_p4 = {{tmp_fu_589_p6[31:16]}}; + +assign tmp_243_i_i_fu_692_p4 = {{tmp_s_fu_611_p6[31:16]}}; + +assign tmp_245_i_i_fu_707_p4 = {{tmp_3_fu_633_p6[31:16]}}; + +assign tmp_247_i_i_fu_722_p4 = {{tmp_4_fu_655_p6[31:16]}}; + +assign tmp_42_fu_347_p3 = {{input_indices_23_dout}, {2'd0}}; + +assign tmp_43_fu_521_p3 = {{select_ln47_10_reg_751}, {2'd0}}; + +assign tmp_44_fu_560_p3 = {{add_ln55_9_fu_548_p2}, {lshr_ln_reg_771}}; + +assign tmp_69_fu_504_p3 = {{add_ln55_reg_758}, {2'd0}}; + +assign tmp_70_fu_426_p3 = kk_reg_332[32'd4]; + +assign tmp_71_fu_571_p3 = {{add_ln55_10_reg_787_pp0_iter2_reg}, {lshr_ln_reg_771_pp0_iter2_reg}}; + +assign trunc_ln55_13_fu_624_p1 = tmp_s_fu_611_p6[15:0]; + +assign trunc_ln55_14_fu_646_p1 = tmp_3_fu_633_p6[15:0]; + +assign trunc_ln55_15_fu_668_p1 = tmp_4_fu_655_p6[15:0]; + +assign trunc_ln55_fu_602_p1 = tmp_fu_589_p6[15:0]; + +assign weight_vecs_0_0_address0 = sext_ln55_10_fu_577_p1; + +assign weight_vecs_0_0_d0 = trunc_ln55_fu_602_p1; + +assign weight_vecs_0_1_address0 = sext_ln55_10_fu_577_p1; + +assign weight_vecs_0_1_d0 = tmp_241_i_i_fu_677_p4; + +assign weight_vecs_1_0_address0 = sext_ln55_10_fu_577_p1; + +assign weight_vecs_1_0_d0 = trunc_ln55_13_fu_624_p1; + +assign weight_vecs_1_1_address0 = sext_ln55_10_fu_577_p1; + +assign weight_vecs_1_1_d0 = tmp_243_i_i_fu_692_p4; + +assign weight_vecs_2_0_address0 = sext_ln55_10_fu_577_p1; + +assign weight_vecs_2_0_d0 = trunc_ln55_14_fu_646_p1; + +assign weight_vecs_2_1_address0 = sext_ln55_10_fu_577_p1; + +assign weight_vecs_2_1_d0 = tmp_245_i_i_fu_707_p4; + +assign weight_vecs_3_0_address0 = sext_ln55_10_fu_577_p1; + +assign weight_vecs_3_0_d0 = trunc_ln55_15_fu_668_p1; + +assign weight_vecs_3_1_address0 = sext_ln55_10_fu_577_p1; + +assign weight_vecs_3_1_d0 = tmp_247_i_i_fu_722_p4; + +assign xor_ln49_fu_434_p2 = (tmp_70_fu_426_p3 ^ 1'd1); + +assign zext_ln55_28_fu_355_p1 = tmp_42_fu_347_p3; + +assign zext_ln55_29_fu_498_p1 = select_ln47_10_reg_751; + +assign zext_ln55_30_fu_417_p1 = select_ln47_10_fu_409_p3; + +assign zext_ln55_31_fu_528_p1 = tmp_43_fu_521_p3; + +assign zext_ln55_32_fu_542_p1 = select_ln48_9_reg_764; + +assign zext_ln55_33_fu_545_p1 = select_ln48_9_reg_764; + +assign zext_ln55_fu_343_p1 = input_indices_23_dout; + +endmodule //td_fused_top_tdf2_readFilters24 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_readInputs25 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + i_17, + j_17, + ifmap_vec_0_address0, + ifmap_vec_0_ce0, + ifmap_vec_0_we0, + ifmap_vec_0_d0, + ifmap_vec_1_address0, + ifmap_vec_1_ce0, + ifmap_vec_1_we0, + ifmap_vec_1_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state8 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] i_17; +input [15:0] j_17; +output [6:0] ifmap_vec_0_address0; +output ifmap_vec_0_ce0; +output ifmap_vec_0_we0; +output [15:0] ifmap_vec_0_d0; +output [6:0] ifmap_vec_1_address0; +output ifmap_vec_1_ce0; +output ifmap_vec_1_we0; +output [15:0] ifmap_vec_1_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg ifmap_vec_0_ce0; +reg ifmap_vec_0_we0; +reg ifmap_vec_1_ce0; +reg ifmap_vec_1_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [6:0] indvar_flatten47_reg_175; +reg [5:0] indvar_flatten_reg_186; +reg [1:0] jj_reg_197; +reg [4:0] kk_reg_209; +reg [1:0] ii_reg_220; +wire [17:0] p_cast_i_fu_249_p1; +reg [17:0] p_cast_i_reg_1036; +wire [13:0] trunc_ln22_fu_253_p1; +reg [13:0] trunc_ln22_reg_1042; +wire [17:0] sext_ln22_fu_263_p1; +reg [17:0] sext_ln22_reg_1048; +wire [6:0] p_cast_fu_267_p2; +reg [6:0] p_cast_reg_1054; +wire [0:0] or_ln23_21_fu_287_p2; +reg [0:0] or_ln23_21_reg_1060; +wire [13:0] p_mid137_fu_293_p2; +reg [13:0] p_mid137_reg_1065; +wire [6:0] add_ln19_5_fu_299_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln19_fu_305_p2; +reg [0:0] icmp_ln19_reg_1075; +reg [0:0] icmp_ln19_reg_1075_pp0_iter1_reg; +reg [0:0] icmp_ln19_reg_1075_pp0_iter2_reg; +reg [0:0] icmp_ln19_reg_1075_pp0_iter3_reg; +reg [0:0] icmp_ln19_reg_1075_pp0_iter4_reg; +wire [0:0] icmp_ln20_fu_311_p2; +reg [0:0] icmp_ln20_reg_1079; +reg [0:0] icmp_ln20_reg_1079_pp0_iter1_reg; +wire [0:0] or_ln19_fu_347_p2; +reg [0:0] or_ln19_reg_1089; +reg [0:0] or_ln19_reg_1089_pp0_iter1_reg; +wire [1:0] add_ln20_fu_353_p2; +reg [1:0] add_ln20_reg_1096; +reg [1:0] add_ln20_reg_1096_pp0_iter1_reg; +wire [1:0] select_ln20_21_fu_367_p3; +reg [1:0] select_ln20_21_reg_1102; +reg [1:0] select_ln20_21_reg_1102_pp0_iter1_reg; +reg [1:0] lshr_ln_reg_1108; +reg [1:0] lshr_ln_reg_1108_pp0_iter1_reg; +reg [1:0] lshr_ln_reg_1108_pp0_iter2_reg; +wire [1:0] trunc_ln32_fu_385_p1; +reg [1:0] trunc_ln32_reg_1113; +reg [1:0] trunc_ln32_reg_1113_pp0_iter1_reg; +reg [1:0] trunc_ln32_reg_1113_pp0_iter2_reg; +reg [1:0] trunc_ln32_reg_1113_pp0_iter3_reg; +reg [2:0] lshr_ln4_reg_1119; +reg [2:0] lshr_ln4_reg_1119_pp0_iter1_reg; +reg [2:0] lshr_ln4_reg_1119_pp0_iter2_reg; +reg [2:0] lshr_ln4_reg_1119_pp0_iter3_reg; +reg [2:0] lshr_ln4_reg_1119_pp0_iter4_reg; +wire [4:0] add_ln25_fu_399_p2; +wire [5:0] select_ln20_25_fu_411_p3; +wire [6:0] p_cast14_i_fu_432_p2; +reg [6:0] p_cast14_i_reg_1134; +wire [0:0] is_padding_fu_476_p2; +reg [0:0] is_padding_reg_1140; +wire [2:0] tmp2_fu_482_p2; +reg [2:0] tmp2_reg_1147; +wire [1:0] select_ln19_30_fu_494_p3; +reg [1:0] select_ln19_30_reg_1152; +reg ap_enable_reg_pp0_iter1; +wire [6:0] p_cast14_i_mid1_fu_514_p2; +reg [6:0] p_cast14_i_mid1_reg_1159; +wire [0:0] or_ln23_23_fu_532_p2; +reg [0:0] or_ln23_23_reg_1165; +wire [0:0] or_ln23_25_fu_565_p2; +reg [0:0] or_ln23_25_reg_1172; +wire [5:0] add_ln33_fu_655_p2; +reg [5:0] add_ln33_reg_1179; +reg [5:0] add_ln33_reg_1179_pp0_iter3_reg; +reg [5:0] add_ln33_reg_1179_pp0_iter4_reg; +wire [0:0] select_ln20_22_fu_664_p3; +reg [0:0] select_ln20_22_reg_1184; +reg [0:0] select_ln20_22_reg_1184_pp0_iter3_reg; +reg [0:0] select_ln20_22_reg_1184_pp0_iter4_reg; +wire [15:0] add_ln32_fu_751_p2; +reg [15:0] add_ln32_reg_1190; +wire [6:0] sub_ln32_15_fu_847_p2; +reg [6:0] sub_ln32_15_reg_1200; +wire [63:0] lshr_ln32_fu_857_p2; +reg [63:0] lshr_ln32_reg_1205; +wire [6:0] sub_ln32_18_fu_948_p2; +reg [6:0] sub_ln32_18_reg_1210; +wire [63:0] lshr_ln32_8_fu_958_p2; +reg [63:0] lshr_ln32_8_reg_1215; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_condition_pp0_exit_iter2_state4; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg [1:0] ap_phi_mux_jj_phi_fu_201_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_224_p4; +wire [63:0] sext_ln32_fu_763_p1; +wire [63:0] sext_ln33_fu_1000_p1; +wire [16:0] zext_ln19_fu_235_p1; +wire [16:0] empty_119_fu_243_p2; +wire [16:0] j_cast_i_fu_231_p1; +wire [16:0] add_ln22_fu_257_p2; +wire [6:0] empty_fu_239_p1; +wire [0:0] tmp_fu_273_p3; +wire [0:0] icmp_ln24_fu_281_p2; +wire [0:0] tmp_63_fu_333_p3; +wire [0:0] xor_ln25_fu_341_p2; +wire [1:0] select_ln19_fu_317_p3; +wire [4:0] select_ln19_29_fu_325_p3; +wire [4:0] select_ln20_fu_359_p3; +wire [5:0] add_ln20_5_fu_405_p2; +wire [17:0] ii_cast_i_fu_419_p1; +wire [6:0] ii_cast_fu_423_p1; +wire [17:0] empty_120_fu_427_p2; +wire [17:0] zext_ln20_fu_443_p1; +wire [17:0] add_ln22_5_fu_451_p2; +wire [0:0] tmp_62_fu_456_p3; +wire [0:0] icmp_ln24_5_fu_464_p2; +wire [0:0] or_ln23_fu_470_p2; +wire [0:0] empty_121_fu_437_p2; +wire [2:0] zext_ln22_fu_447_p1; +wire [1:0] add_ln19_fu_488_p2; +wire [17:0] ii_cast_i_mid1_fu_501_p1; +wire [6:0] ii_cast_mid1_fu_505_p1; +wire [17:0] p_mid111_fu_509_p2; +wire [0:0] p_mid113_fu_519_p2; +wire [17:0] zext_ln20_5_fu_537_p1; +wire [17:0] add_ln22_6_fu_540_p2; +wire [0:0] tmp_64_fu_545_p3; +wire [0:0] icmp_ln24_6_fu_553_p2; +wire [0:0] or_ln23_24_fu_559_p2; +wire [0:0] select_ln19_32_fu_525_p3; +wire [13:0] tmp2_cast_fu_577_p1; +wire [13:0] empty_122_fu_580_p2; +wire [3:0] tmp_s_fu_595_p3; +wire [4:0] zext_ln33_10_fu_602_p1; +wire [4:0] zext_ln33_fu_592_p1; +wire [4:0] sub_ln33_fu_606_p2; +wire [6:0] row_coord_int_mid131_fu_626_p3; +wire [6:0] row_coord_int_fu_571_p3; +wire [13:0] col_coord_int_mid139_fu_632_p3; +wire [13:0] col_coord_int_fu_585_p3; +wire [5:0] sub_ln33_cast_fu_612_p1; +wire [5:0] zext_ln33_11_fu_652_p1; +wire [0:0] select_ln19_33_fu_621_p3; +wire [6:0] select_ln19_31_fu_616_p3; +wire [2:0] zext_ln22_5_fu_661_p1; +wire [2:0] tmp2_mid1_fu_677_p2; +wire [13:0] tmp2_cast_mid1_fu_683_p1; +wire [13:0] p_mid1_fu_687_p2; +wire [6:0] select_ln19_34_fu_638_p3; +wire [6:0] row_coord_int_mid1_fu_670_p3; +wire [6:0] select_ln20_23_fu_699_p3; +wire [13:0] tmp_38_fu_706_p3; +wire [10:0] tmp_39_fu_718_p3; +wire [14:0] zext_ln32_fu_714_p1; +wire [14:0] zext_ln32_36_fu_726_p1; +wire [14:0] sub_ln32_fu_730_p2; +wire [13:0] select_ln19_35_fu_645_p3; +wire [13:0] col_coord_int_mid1_fu_692_p3; +wire [13:0] select_ln20_24_fu_740_p3; +wire [15:0] sext_ln20_fu_736_p1; +wire [15:0] zext_ln32_37_fu_747_p1; +wire [17:0] tmp_65_fu_757_p3; +wire [5:0] tmp_40_fu_768_p3; +wire [5:0] empty_124_fu_775_p2; +wire [6:0] zext_ln32_38_fu_787_p1; +wire [6:0] zext_ln32_39_fu_791_p1; +wire [0:0] icmp_ln32_fu_781_p2; +wire [6:0] sub_ln32_13_fu_805_p2; +wire [6:0] sub_ln32_14_fu_817_p2; +reg [63:0] tmp_66_fu_795_p4; +wire [6:0] xor_ln32_fu_811_p2; +wire [6:0] select_ln32_fu_823_p3; +wire [6:0] select_ln32_12_fu_839_p3; +wire [63:0] select_ln32_11_fu_831_p3; +wire [63:0] zext_ln32_40_fu_853_p1; +wire [1:0] or_ln329_i_fu_863_p2; +wire [5:0] tmp_41_fu_868_p3; +wire [5:0] empty_125_fu_876_p2; +wire [6:0] zext_ln32_42_fu_888_p1; +wire [6:0] zext_ln32_43_fu_892_p1; +wire [0:0] icmp_ln32_3_fu_882_p2; +wire [6:0] sub_ln32_16_fu_906_p2; +wire [6:0] sub_ln32_17_fu_918_p2; +reg [63:0] tmp_68_fu_896_p4; +wire [6:0] xor_ln32_3_fu_912_p2; +wire [6:0] select_ln32_13_fu_924_p3; +wire [6:0] select_ln32_15_fu_940_p3; +wire [63:0] select_ln32_14_fu_932_p3; +wire [63:0] zext_ln32_44_fu_954_p1; +wire [63:0] zext_ln32_41_fu_964_p1; +wire [63:0] lshr_ln32_7_fu_967_p2; +wire [63:0] and_ln32_fu_973_p2; +wire [15:0] trunc_ln32_5_fu_978_p1; +wire [15:0] in_data_elem_fu_982_p1; +wire [8:0] tmp_67_fu_994_p3; +wire [63:0] zext_ln32_45_fu_1006_p1; +wire [63:0] lshr_ln32_9_fu_1009_p2; +wire [63:0] and_ln32_3_fu_1015_p2; +wire [15:0] trunc_ln32_6_fu_1020_p1; +wire [15:0] in_data_elem_9_fu_1024_p1; +wire ap_CS_fsm_state8; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter2_state4)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter1; + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1075_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ii_reg_220 <= select_ln19_30_reg_1152; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_220 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_305_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten47_reg_175 <= add_ln19_5_fu_299_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten47_reg_175 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_305_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_186 <= select_ln20_25_fu_411_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_186 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1075 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_197 <= select_ln20_21_reg_1102; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_197 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_305_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_reg_209 <= add_ln25_fu_399_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_209 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_305_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln20_reg_1096 <= add_ln20_fu_353_p2; + icmp_ln20_reg_1079 <= icmp_ln20_fu_311_p2; + lshr_ln4_reg_1119 <= {{select_ln20_fu_359_p3[3:1]}}; + lshr_ln_reg_1108 <= {{select_ln20_fu_359_p3[3:2]}}; + or_ln19_reg_1089 <= or_ln19_fu_347_p2; + trunc_ln32_reg_1113 <= trunc_ln32_fu_385_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln20_reg_1096_pp0_iter1_reg <= add_ln20_reg_1096; + icmp_ln19_reg_1075 <= icmp_ln19_fu_305_p2; + icmp_ln19_reg_1075_pp0_iter1_reg <= icmp_ln19_reg_1075; + icmp_ln20_reg_1079_pp0_iter1_reg <= icmp_ln20_reg_1079; + is_padding_reg_1140 <= is_padding_fu_476_p2; + lshr_ln4_reg_1119_pp0_iter1_reg <= lshr_ln4_reg_1119; + lshr_ln_reg_1108_pp0_iter1_reg <= lshr_ln_reg_1108; + or_ln19_reg_1089_pp0_iter1_reg <= or_ln19_reg_1089; + p_cast14_i_reg_1134 <= p_cast14_i_fu_432_p2; + select_ln20_21_reg_1102_pp0_iter1_reg <= select_ln20_21_reg_1102; + trunc_ln32_reg_1113_pp0_iter1_reg <= trunc_ln32_reg_1113; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1075_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln32_reg_1190 <= add_ln32_fu_751_p2; + add_ln33_reg_1179 <= add_ln33_fu_655_p2; + select_ln20_22_reg_1184 <= select_ln20_22_fu_664_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln33_reg_1179_pp0_iter3_reg <= add_ln33_reg_1179; + add_ln33_reg_1179_pp0_iter4_reg <= add_ln33_reg_1179_pp0_iter3_reg; + icmp_ln19_reg_1075_pp0_iter2_reg <= icmp_ln19_reg_1075_pp0_iter1_reg; + icmp_ln19_reg_1075_pp0_iter3_reg <= icmp_ln19_reg_1075_pp0_iter2_reg; + icmp_ln19_reg_1075_pp0_iter4_reg <= icmp_ln19_reg_1075_pp0_iter3_reg; + lshr_ln4_reg_1119_pp0_iter2_reg <= lshr_ln4_reg_1119_pp0_iter1_reg; + lshr_ln4_reg_1119_pp0_iter3_reg <= lshr_ln4_reg_1119_pp0_iter2_reg; + lshr_ln4_reg_1119_pp0_iter4_reg <= lshr_ln4_reg_1119_pp0_iter3_reg; + lshr_ln_reg_1108_pp0_iter2_reg <= lshr_ln_reg_1108_pp0_iter1_reg; + select_ln20_22_reg_1184_pp0_iter3_reg <= select_ln20_22_reg_1184; + select_ln20_22_reg_1184_pp0_iter4_reg <= select_ln20_22_reg_1184_pp0_iter3_reg; + trunc_ln32_reg_1113_pp0_iter2_reg <= trunc_ln32_reg_1113_pp0_iter1_reg; + trunc_ln32_reg_1113_pp0_iter3_reg <= trunc_ln32_reg_1113_pp0_iter2_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1075_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (select_ln20_22_reg_1184_pp0_iter3_reg == 1'd0))) begin + lshr_ln32_8_reg_1215 <= lshr_ln32_8_fu_958_p2; + lshr_ln32_reg_1205 <= lshr_ln32_fu_857_p2; + sub_ln32_15_reg_1200[6 : 1] <= sub_ln32_15_fu_847_p2[6 : 1]; + sub_ln32_18_reg_1210[6 : 1] <= sub_ln32_18_fu_948_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + or_ln23_21_reg_1060 <= or_ln23_21_fu_287_p2; + p_cast_i_reg_1036 <= p_cast_i_fu_249_p1; + p_cast_reg_1054 <= p_cast_fu_267_p2; + p_mid137_reg_1065 <= p_mid137_fu_293_p2; + sext_ln22_reg_1048 <= sext_ln22_fu_263_p1; + trunc_ln22_reg_1042 <= trunc_ln22_fu_253_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1075 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + or_ln23_23_reg_1165 <= or_ln23_23_fu_532_p2; + or_ln23_25_reg_1172 <= or_ln23_25_fu_565_p2; + p_cast14_i_mid1_reg_1159 <= p_cast14_i_mid1_fu_514_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1075 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + select_ln19_30_reg_1152 <= select_ln19_30_fu_494_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_305_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln20_21_reg_1102 <= select_ln20_21_fu_367_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln20_reg_1079 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (or_ln19_reg_1089 == 1'd1))) begin + tmp2_reg_1147 <= tmp2_fu_482_p2; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_condition_pp0_exit_iter2_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter2_state4 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_fu_305_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_1075_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_224_p4 = select_ln19_30_reg_1152; + end else begin + ap_phi_mux_ii_phi_fu_224_p4 = ii_reg_220; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_1075 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_201_p4 = select_ln20_21_reg_1102; + end else begin + ap_phi_mux_jj_phi_fu_201_p4 = jj_reg_197; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin + ifmap_vec_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_1075_pp0_iter4_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin + ifmap_vec_0_we0 = 1'b1; + end else begin + ifmap_vec_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin + ifmap_vec_1_ce0 = 1'b1; + end else begin + ifmap_vec_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_1075_pp0_iter4_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin + ifmap_vec_1_we0 = 1'b1; + end else begin + ifmap_vec_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter5 == 1'b1) & (ap_enable_reg_pp0_iter4 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter5 == 1'b1) & (ap_enable_reg_pp0_iter4 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state8; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln19_5_fu_299_p2 = (indvar_flatten47_reg_175 + 7'd1); + +assign add_ln19_fu_488_p2 = (ap_phi_mux_ii_phi_fu_224_p4 + 2'd1); + +assign add_ln20_5_fu_405_p2 = (indvar_flatten_reg_186 + 6'd1); + +assign add_ln20_fu_353_p2 = (select_ln19_fu_317_p3 + 2'd1); + +assign add_ln22_5_fu_451_p2 = ((sext_ln22_reg_1048) + (zext_ln20_fu_443_p1)); + +assign add_ln22_6_fu_540_p2 = ((sext_ln22_reg_1048) + (zext_ln20_5_fu_537_p1)); + +assign add_ln22_fu_257_p2 = ((j_cast_i_fu_231_p1) + (17'd131071)); + +assign add_ln25_fu_399_p2 = (select_ln20_fu_359_p3 + 5'd2); + +assign add_ln32_fu_751_p2 = ((sext_ln20_fu_736_p1) + (zext_ln32_37_fu_747_p1)); + +assign add_ln33_fu_655_p2 = ((sub_ln33_cast_fu_612_p1) + (zext_ln33_11_fu_652_p1)); + +assign and_ln32_3_fu_1015_p2 = (lshr_ln32_9_fu_1009_p2 & lshr_ln32_8_reg_1215); + +assign and_ln32_fu_973_p2 = (lshr_ln32_reg_1205 & lshr_ln32_7_fu_967_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign col_coord_int_fu_585_p3 = ((is_padding_reg_1140[0:0] == 1'b1) ? 14'd0 : empty_122_fu_580_p2); + +assign col_coord_int_mid139_fu_632_p3 = ((or_ln23_23_reg_1165[0:0] == 1'b1) ? 14'd0 : p_mid137_reg_1065); + +assign col_coord_int_mid1_fu_692_p3 = ((or_ln23_25_reg_1172[0:0] == 1'b1) ? 14'd0 : p_mid1_fu_687_p2); + +assign empty_119_fu_243_p2 = ((zext_ln19_fu_235_p1) + (17'd131071)); + +assign empty_120_fu_427_p2 = ((p_cast_i_reg_1036) + (ii_cast_i_fu_419_p1)); + +assign empty_121_fu_437_p2 = ((empty_120_fu_427_p2 > 18'd111) ? 1'b1 : 1'b0); + +assign empty_122_fu_580_p2 = ((tmp2_cast_fu_577_p1) + (trunc_ln22_reg_1042)); + +assign empty_124_fu_775_p2 = (tmp_40_fu_768_p3 | 6'd15); + +assign empty_125_fu_876_p2 = (tmp_41_fu_868_p3 | 6'd15); + +assign empty_fu_239_p1 = i_17[6:0]; + +assign icmp_ln19_fu_305_p2 = ((indvar_flatten47_reg_175 == 7'd72) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_311_p2 = ((indvar_flatten_reg_186 == 6'd24) ? 1'b1 : 1'b0); + +assign icmp_ln24_5_fu_464_p2 = (((add_ln22_5_fu_451_p2) > (18'd111)) ? 1'b1 : 1'b0); + +assign icmp_ln24_6_fu_553_p2 = (((add_ln22_6_fu_540_p2) > (18'd111)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_281_p2 = (((add_ln22_fu_257_p2) > (17'd111)) ? 1'b1 : 1'b0); + +assign icmp_ln32_3_fu_882_p2 = ((tmp_41_fu_868_p3 > empty_125_fu_876_p2) ? 1'b1 : 1'b0); + +assign icmp_ln32_fu_781_p2 = ((tmp_40_fu_768_p3 > empty_124_fu_775_p2) ? 1'b1 : 1'b0); + +assign ifmap_vec_0_address0 = sext_ln33_fu_1000_p1; + +assign ifmap_vec_0_d0 = ((select_ln20_22_reg_1184_pp0_iter4_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_fu_982_p1); + +assign ifmap_vec_1_address0 = sext_ln33_fu_1000_p1; + +assign ifmap_vec_1_d0 = ((select_ln20_22_reg_1184_pp0_iter4_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_9_fu_1024_p1); + +assign ii_cast_fu_423_p1 = ap_phi_mux_ii_phi_fu_224_p4; + +assign ii_cast_i_fu_419_p1 = ap_phi_mux_ii_phi_fu_224_p4; + +assign ii_cast_i_mid1_fu_501_p1 = add_ln19_fu_488_p2; + +assign ii_cast_mid1_fu_505_p1 = add_ln19_fu_488_p2; + +assign in_data_address0 = sext_ln32_fu_763_p1; + +assign in_data_elem_9_fu_1024_p1 = trunc_ln32_6_fu_1020_p1; + +assign in_data_elem_fu_982_p1 = trunc_ln32_5_fu_978_p1; + +assign is_padding_fu_476_p2 = (or_ln23_fu_470_p2 | empty_121_fu_437_p2); + +assign j_cast_i_fu_231_p1 = j_17; + +assign lshr_ln32_7_fu_967_p2 = 64'd18446744073709551615 >> zext_ln32_41_fu_964_p1; + +assign lshr_ln32_8_fu_958_p2 = select_ln32_14_fu_932_p3 >> zext_ln32_44_fu_954_p1; + +assign lshr_ln32_9_fu_1009_p2 = 64'd18446744073709551615 >> zext_ln32_45_fu_1006_p1; + +assign lshr_ln32_fu_857_p2 = select_ln32_11_fu_831_p3 >> zext_ln32_40_fu_853_p1; + +assign or_ln19_fu_347_p2 = (xor_ln25_fu_341_p2 | icmp_ln20_fu_311_p2); + +assign or_ln23_21_fu_287_p2 = (tmp_fu_273_p3 | icmp_ln24_fu_281_p2); + +assign or_ln23_23_fu_532_p2 = (p_mid113_fu_519_p2 | or_ln23_21_reg_1060); + +assign or_ln23_24_fu_559_p2 = (tmp_64_fu_545_p3 | icmp_ln24_6_fu_553_p2); + +assign or_ln23_25_fu_565_p2 = (select_ln19_32_fu_525_p3 | or_ln23_24_fu_559_p2); + +assign or_ln23_fu_470_p2 = (tmp_62_fu_456_p3 | icmp_ln24_5_fu_464_p2); + +assign or_ln329_i_fu_863_p2 = (trunc_ln32_reg_1113_pp0_iter3_reg | 2'd1); + +assign p_cast14_i_fu_432_p2 = (p_cast_reg_1054 + ii_cast_fu_423_p1); + +assign p_cast14_i_mid1_fu_514_p2 = (p_cast_reg_1054 + ii_cast_mid1_fu_505_p1); + +assign p_cast_fu_267_p2 = ((empty_fu_239_p1) + (7'd127)); + +assign p_cast_i_fu_249_p1 = (empty_119_fu_243_p2); + +assign p_mid111_fu_509_p2 = ((p_cast_i_reg_1036) + (ii_cast_i_mid1_fu_501_p1)); + +assign p_mid113_fu_519_p2 = ((p_mid111_fu_509_p2 > 18'd111) ? 1'b1 : 1'b0); + +assign p_mid137_fu_293_p2 = ((trunc_ln22_fu_253_p1) + (14'd16383)); + +assign p_mid1_fu_687_p2 = ((tmp2_cast_mid1_fu_683_p1) + (trunc_ln22_reg_1042)); + +assign row_coord_int_fu_571_p3 = ((is_padding_reg_1140[0:0] == 1'b1) ? 7'd0 : p_cast14_i_reg_1134); + +assign row_coord_int_mid131_fu_626_p3 = ((or_ln23_23_reg_1165[0:0] == 1'b1) ? 7'd0 : p_cast14_i_mid1_reg_1159); + +assign row_coord_int_mid1_fu_670_p3 = ((or_ln23_25_reg_1172[0:0] == 1'b1) ? 7'd0 : select_ln19_31_fu_616_p3); + +assign select_ln19_29_fu_325_p3 = ((icmp_ln20_fu_311_p2[0:0] == 1'b1) ? 5'd0 : kk_reg_209); + +assign select_ln19_30_fu_494_p3 = ((icmp_ln20_reg_1079[0:0] == 1'b1) ? add_ln19_fu_488_p2 : ap_phi_mux_ii_phi_fu_224_p4); + +assign select_ln19_31_fu_616_p3 = ((icmp_ln20_reg_1079_pp0_iter1_reg[0:0] == 1'b1) ? p_cast14_i_mid1_reg_1159 : p_cast14_i_reg_1134); + +assign select_ln19_32_fu_525_p3 = ((icmp_ln20_reg_1079[0:0] == 1'b1) ? p_mid113_fu_519_p2 : empty_121_fu_437_p2); + +assign select_ln19_33_fu_621_p3 = ((icmp_ln20_reg_1079_pp0_iter1_reg[0:0] == 1'b1) ? or_ln23_23_reg_1165 : is_padding_reg_1140); + +assign select_ln19_34_fu_638_p3 = ((icmp_ln20_reg_1079_pp0_iter1_reg[0:0] == 1'b1) ? row_coord_int_mid131_fu_626_p3 : row_coord_int_fu_571_p3); + +assign select_ln19_35_fu_645_p3 = ((icmp_ln20_reg_1079_pp0_iter1_reg[0:0] == 1'b1) ? col_coord_int_mid139_fu_632_p3 : col_coord_int_fu_585_p3); + +assign select_ln19_fu_317_p3 = ((icmp_ln20_fu_311_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_201_p4); + +assign select_ln20_21_fu_367_p3 = ((or_ln19_fu_347_p2[0:0] == 1'b1) ? select_ln19_fu_317_p3 : add_ln20_fu_353_p2); + +assign select_ln20_22_fu_664_p3 = ((or_ln19_reg_1089_pp0_iter1_reg[0:0] == 1'b1) ? select_ln19_33_fu_621_p3 : or_ln23_25_reg_1172); + +assign select_ln20_23_fu_699_p3 = ((or_ln19_reg_1089_pp0_iter1_reg[0:0] == 1'b1) ? select_ln19_34_fu_638_p3 : row_coord_int_mid1_fu_670_p3); + +assign select_ln20_24_fu_740_p3 = ((or_ln19_reg_1089_pp0_iter1_reg[0:0] == 1'b1) ? select_ln19_35_fu_645_p3 : col_coord_int_mid1_fu_692_p3); + +assign select_ln20_25_fu_411_p3 = ((icmp_ln20_fu_311_p2[0:0] == 1'b1) ? 6'd1 : add_ln20_5_fu_405_p2); + +assign select_ln20_fu_359_p3 = ((or_ln19_fu_347_p2[0:0] == 1'b1) ? select_ln19_29_fu_325_p3 : 5'd0); + +assign select_ln32_11_fu_831_p3 = ((icmp_ln32_fu_781_p2[0:0] == 1'b1) ? tmp_66_fu_795_p4 : in_data_q0); + +assign select_ln32_12_fu_839_p3 = ((icmp_ln32_fu_781_p2[0:0] == 1'b1) ? xor_ln32_fu_811_p2 : zext_ln32_38_fu_787_p1); + +assign select_ln32_13_fu_924_p3 = ((icmp_ln32_3_fu_882_p2[0:0] == 1'b1) ? sub_ln32_16_fu_906_p2 : sub_ln32_17_fu_918_p2); + +assign select_ln32_14_fu_932_p3 = ((icmp_ln32_3_fu_882_p2[0:0] == 1'b1) ? tmp_68_fu_896_p4 : in_data_q0); + +assign select_ln32_15_fu_940_p3 = ((icmp_ln32_3_fu_882_p2[0:0] == 1'b1) ? xor_ln32_3_fu_912_p2 : zext_ln32_42_fu_888_p1); + +assign select_ln32_fu_823_p3 = ((icmp_ln32_fu_781_p2[0:0] == 1'b1) ? sub_ln32_13_fu_805_p2 : sub_ln32_14_fu_817_p2); + +assign sext_ln20_fu_736_p1 = (sub_ln32_fu_730_p2); + +assign sext_ln22_fu_263_p1 = add_ln22_fu_257_p2; + +assign sext_ln32_fu_763_p1 = (tmp_65_fu_757_p3); + +assign sext_ln33_fu_1000_p1 = (tmp_67_fu_994_p3); + +assign sub_ln32_13_fu_805_p2 = (zext_ln32_38_fu_787_p1 - zext_ln32_39_fu_791_p1); + +assign sub_ln32_14_fu_817_p2 = (zext_ln32_39_fu_791_p1 - zext_ln32_38_fu_787_p1); + +assign sub_ln32_15_fu_847_p2 = (7'd63 - select_ln32_fu_823_p3); + +assign sub_ln32_16_fu_906_p2 = (zext_ln32_42_fu_888_p1 - zext_ln32_43_fu_892_p1); + +assign sub_ln32_17_fu_918_p2 = (zext_ln32_43_fu_892_p1 - zext_ln32_42_fu_888_p1); + +assign sub_ln32_18_fu_948_p2 = (7'd63 - select_ln32_13_fu_924_p3); + +assign sub_ln32_fu_730_p2 = (zext_ln32_fu_714_p1 - zext_ln32_36_fu_726_p1); + +assign sub_ln33_cast_fu_612_p1 = (sub_ln33_fu_606_p2); + +assign sub_ln33_fu_606_p2 = (zext_ln33_10_fu_602_p1 - zext_ln33_fu_592_p1); + +assign tmp2_cast_fu_577_p1 = (tmp2_reg_1147); + +assign tmp2_cast_mid1_fu_683_p1 = (tmp2_mid1_fu_677_p2); + +assign tmp2_fu_482_p2 = ((zext_ln22_fu_447_p1) + (3'd7)); + +assign tmp2_mid1_fu_677_p2 = ((zext_ln22_5_fu_661_p1) + (3'd7)); + +assign tmp_38_fu_706_p3 = {{select_ln20_23_fu_699_p3}, {7'd0}}; + +assign tmp_39_fu_718_p3 = {{select_ln20_23_fu_699_p3}, {4'd0}}; + +assign tmp_40_fu_768_p3 = {{trunc_ln32_reg_1113_pp0_iter3_reg}, {4'd0}}; + +assign tmp_41_fu_868_p3 = {{or_ln329_i_fu_863_p2}, {4'd0}}; + +assign tmp_62_fu_456_p3 = add_ln22_5_fu_451_p2[32'd17]; + +assign tmp_63_fu_333_p3 = kk_reg_209[32'd4]; + +assign tmp_64_fu_545_p3 = add_ln22_6_fu_540_p2[32'd17]; + +assign tmp_65_fu_757_p3 = {{add_ln32_reg_1190}, {lshr_ln_reg_1108_pp0_iter2_reg}}; + +integer ap_tvar_int_0; + +always @ (in_data_q0) begin + //for (ap_tvar_int_0 = 64 - 1; ap_tvar_int_0 >= 0; ap_tvar_int_0 = ap_tvar_int_0 - 1) begin + for (ap_tvar_int_0 = 0; ap_tvar_int_0 < 64; ap_tvar_int_0 = ap_tvar_int_0 + 1) begin + if (ap_tvar_int_0 > 63 - 0) begin + tmp_66_fu_795_p4[ap_tvar_int_0] = 1'b0; + end else begin + tmp_66_fu_795_p4[ap_tvar_int_0] = in_data_q0[63 - ap_tvar_int_0]; + end + end +end + +assign tmp_67_fu_994_p3 = {{add_ln33_reg_1179_pp0_iter4_reg}, {lshr_ln4_reg_1119_pp0_iter4_reg}}; + +integer ap_tvar_int_1; + +always @ (in_data_q0) begin + //for (ap_tvar_int_1 = 64 - 1; ap_tvar_int_1 >= 0; ap_tvar_int_1 = ap_tvar_int_1 - 1) begin + for (ap_tvar_int_1 = 0; ap_tvar_int_1 < 64; ap_tvar_int_1 = ap_tvar_int_1 + 1) begin + if (ap_tvar_int_1 > 63 - 0) begin + tmp_68_fu_896_p4[ap_tvar_int_1] = 1'b0; + end else begin + tmp_68_fu_896_p4[ap_tvar_int_1] = in_data_q0[63 - ap_tvar_int_1]; + end + end +end + +assign tmp_fu_273_p3 = add_ln22_fu_257_p2[32'd16]; + +assign tmp_s_fu_595_p3 = {{select_ln19_30_reg_1152}, {2'd0}}; + +assign trunc_ln22_fu_253_p1 = j_17[13:0]; + +assign trunc_ln32_5_fu_978_p1 = and_ln32_fu_973_p2[15:0]; + +assign trunc_ln32_6_fu_1020_p1 = and_ln32_3_fu_1015_p2[15:0]; + +assign trunc_ln32_fu_385_p1 = select_ln20_fu_359_p3[1:0]; + +assign xor_ln25_fu_341_p2 = (tmp_63_fu_333_p3 ^ 1'd1); + +assign xor_ln32_3_fu_912_p2 = (zext_ln32_42_fu_888_p1 ^ 7'd63); + +assign xor_ln32_fu_811_p2 = (zext_ln32_38_fu_787_p1 ^ 7'd63); + +assign zext_ln19_fu_235_p1 = i_17; + +assign zext_ln20_5_fu_537_p1 = add_ln20_reg_1096; + +assign zext_ln20_fu_443_p1 = jj_reg_197; + +assign zext_ln22_5_fu_661_p1 = add_ln20_reg_1096_pp0_iter1_reg; + +assign zext_ln22_fu_447_p1 = jj_reg_197; + +assign zext_ln32_36_fu_726_p1 = tmp_39_fu_718_p3; + +assign zext_ln32_37_fu_747_p1 = select_ln20_24_fu_740_p3; + +assign zext_ln32_38_fu_787_p1 = tmp_40_fu_768_p3; + +assign zext_ln32_39_fu_791_p1 = empty_124_fu_775_p2; + +assign zext_ln32_40_fu_853_p1 = select_ln32_12_fu_839_p3; + +assign zext_ln32_41_fu_964_p1 = sub_ln32_15_reg_1200; + +assign zext_ln32_42_fu_888_p1 = tmp_41_fu_868_p3; + +assign zext_ln32_43_fu_892_p1 = empty_125_fu_876_p2; + +assign zext_ln32_44_fu_954_p1 = select_ln32_15_fu_940_p3; + +assign zext_ln32_45_fu_1006_p1 = sub_ln32_18_reg_1210; + +assign zext_ln32_fu_714_p1 = tmp_38_fu_706_p3; + +assign zext_ln33_10_fu_602_p1 = tmp_s_fu_595_p3; + +assign zext_ln33_11_fu_652_p1 = select_ln20_21_reg_1102_pp0_iter1_reg; + +assign zext_ln33_fu_592_p1 = select_ln19_30_reg_1152; + +always @ (posedge ap_clk) begin + sub_ln32_15_reg_1200[0] <= 1'b0; + sub_ln32_18_reg_1210[0] <= 1'b0; +end + +endmodule //td_fused_top_tdf2_readInputs25 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_writeOutputs_aligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_idle, + ap_ready, + i, + j, + k, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1, + max_vals_4_0, + max_vals_4_1, + max_vals_4_2, + max_vals_4_3 +); + +parameter ap_ST_fsm_state1 = 2'd1; +parameter ap_ST_fsm_state2 = 2'd2; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +input [5:0] i; +input [11:0] j; +input [4:0] k; +output [14:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; +input [15:0] max_vals_4_0; +input [15:0] max_vals_4_1; +input [15:0] max_vals_4_2; +input [15:0] max_vals_4_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg out_data_ce1; +reg out_data_we1; + + reg [1:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [11:0] add_ln123_fu_105_p2; +reg [11:0] add_ln123_reg_178; +wire [63:0] zext_ln123_6_fu_132_p1; +wire ap_CS_fsm_state2; +wire [8:0] tmp_s_fu_87_p3; +wire [11:0] tmp_fu_79_p3; +wire [11:0] zext_ln123_fu_95_p1; +wire [11:0] sub_ln123_fu_99_p2; +wire [14:0] tmp_129_cast_fu_111_p3; +wire [14:0] zext_ln123_5_fu_122_p1; +wire [14:0] add_ln123_3_fu_126_p2; +wire [15:0] bitcast_ln123_9_fu_161_p1; +wire [15:0] bitcast_ln123_8_fu_153_p1; +wire [15:0] bitcast_ln123_7_fu_145_p1; +wire [15:0] bitcast_ln123_fu_137_p1; +reg [1:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 2'd1; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + add_ln123_reg_178 <= add_ln123_fu_105_p2; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln123_3_fu_126_p2 = (tmp_129_cast_fu_111_p3 + zext_ln123_5_fu_122_p1); + +assign add_ln123_fu_105_p2 = (sub_ln123_fu_99_p2 + j); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign bitcast_ln123_7_fu_145_p1 = max_vals_4_1; + +assign bitcast_ln123_8_fu_153_p1 = max_vals_4_2; + +assign bitcast_ln123_9_fu_161_p1 = max_vals_4_3; + +assign bitcast_ln123_fu_137_p1 = max_vals_4_0; + +assign out_data_address1 = zext_ln123_6_fu_132_p1; + +assign out_data_d1 = {{{{bitcast_ln123_9_fu_161_p1}, {bitcast_ln123_8_fu_153_p1}}, {bitcast_ln123_7_fu_145_p1}}, {bitcast_ln123_fu_137_p1}}; + +assign sub_ln123_fu_99_p2 = (tmp_fu_79_p3 - zext_ln123_fu_95_p1); + +assign tmp_129_cast_fu_111_p3 = {{add_ln123_reg_178}, {3'd0}}; + +assign tmp_fu_79_p3 = {{i}, {6'd0}}; + +assign tmp_s_fu_87_p3 = {{i}, {3'd0}}; + +assign zext_ln123_5_fu_122_p1 = k; + +assign zext_ln123_6_fu_132_p1 = add_ln123_3_fu_126_p2; + +assign zext_ln123_fu_95_p1 = tmp_s_fu_87_p3; + +endmodule //td_fused_top_tdf2_writeOutputs_aligned +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_112 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [14:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [14:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [13:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [13:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [8:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [8:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [3:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [3:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [14:0] dataflow_in_loop_TOP_LOOP48628_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP48628_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48628_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP48628_U0_in_data_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP48628_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP48628_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48628_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP48628_U0_in_data_we1; +wire [8:0] dataflow_in_loop_TOP_LOOP48628_U0_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP48628_U0_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP48628_U0_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP48628_U0_filter_data_we0; +wire [8:0] dataflow_in_loop_TOP_LOOP48628_U0_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP48628_U0_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP48628_U0_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP48628_U0_filter_data_we1; +wire [3:0] dataflow_in_loop_TOP_LOOP48628_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP48628_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP48628_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP48628_U0_adjustments_we0; +wire [3:0] dataflow_in_loop_TOP_LOOP48628_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP48628_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP48628_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP48628_U0_adjustments_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP48628_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP48628_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48628_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP48628_U0_out_data_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP48628_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP48628_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48628_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP48628_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP48628_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP48628_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP48628_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP48628_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP48628_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP48628_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP48628_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP48628_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP48628_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [15:0] loop_dataflow_input_count; +reg [15:0] loop_dataflow_output_count; +wire [15:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP48628_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP48628_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 16'd0; +#0 loop_dataflow_output_count = 16'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP48628 dataflow_in_loop_TOP_LOOP48628_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP48628_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP48628_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP48628_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP48628_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP48628_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP48628_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP48628_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP48628_U0_in_data_we1), + .filter_data_address0(dataflow_in_loop_TOP_LOOP48628_U0_filter_data_address0), + .filter_data_ce0(dataflow_in_loop_TOP_LOOP48628_U0_filter_data_ce0), + .filter_data_d0(dataflow_in_loop_TOP_LOOP48628_U0_filter_data_d0), + .filter_data_q0(filter_data_q0), + .filter_data_we0(dataflow_in_loop_TOP_LOOP48628_U0_filter_data_we0), + .filter_data_address1(dataflow_in_loop_TOP_LOOP48628_U0_filter_data_address1), + .filter_data_ce1(dataflow_in_loop_TOP_LOOP48628_U0_filter_data_ce1), + .filter_data_d1(dataflow_in_loop_TOP_LOOP48628_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(dataflow_in_loop_TOP_LOOP48628_U0_filter_data_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP48628_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP48628_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP48628_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP48628_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP48628_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP48628_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP48628_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP48628_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP48628_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP48628_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP48628_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP48628_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP48628_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP48628_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP48628_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP48628_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP48628_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP48628_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP48628_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP48628_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP48628_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP48628_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP48628_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 16'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48628_U0_ap_ready == 1'b1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 16'd1); + end else if (((dataflow_in_loop_TOP_LOOP48628_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= 16'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 16'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48628_U0_ap_done == 1'b1) & (dataflow_in_loop_TOP_LOOP48628_U0_ap_continue == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 16'd1); + end else if (((dataflow_in_loop_TOP_LOOP48628_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48628_U0_ap_continue == 1'b1))) begin + loop_dataflow_output_count <= 16'd0; + end + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP48628_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP48628_U0_ap_idle == 1'b1) & (loop_dataflow_output_count == 16'd0) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP48628_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP48628_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP48628_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP48628_U0_adjustments_address0; + +assign adjustments_address1 = 4'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP48628_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP48628_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP48628_U0_ap_ready; + +assign bound_minus_1 = (16'd50176 - 16'd1); + +assign dataflow_in_loop_TOP_LOOP48628_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP48628_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP48628_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP48628_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP48628_U0_start_write = 1'b0; + +assign filter_data_address0 = dataflow_in_loop_TOP_LOOP48628_U0_filter_data_address0; + +assign filter_data_address1 = 9'd0; + +assign filter_data_ce0 = dataflow_in_loop_TOP_LOOP48628_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP48628_U0_in_data_address0; + +assign in_data_address1 = 15'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP48628_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP48628_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 14'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP48628_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP48628_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP48628_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP48628_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP48628_U0_out_data_write; + +endmodule //td_fused_top_tdf3_112 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_pp0_stage0 = 11'd2; +parameter ap_ST_fsm_pp0_stage1 = 11'd4; +parameter ap_ST_fsm_pp0_stage2 = 11'd8; +parameter ap_ST_fsm_pp0_stage3 = 11'd16; +parameter ap_ST_fsm_pp0_stage4 = 11'd32; +parameter ap_ST_fsm_pp0_stage5 = 11'd64; +parameter ap_ST_fsm_pp0_stage6 = 11'd128; +parameter ap_ST_fsm_state15 = 11'd256; +parameter ap_ST_fsm_state16 = 11'd512; +parameter ap_ST_fsm_state17 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [4:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [4:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[4:0] accum_in_0_address0; +reg accum_in_0_ce0; +reg[4:0] accum_in_0_address1; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [5:0] x_reg_168; +reg [15:0] psum_7_08_reg_180; +reg [15:0] psum_6_07_reg_192; +reg [15:0] psum_5_06_reg_204; +reg [15:0] psum_4_05_reg_216; +reg [15:0] psum_3_04_reg_228; +reg [15:0] psum_2_03_reg_240; +reg [15:0] psum_1_02_reg_252; +reg [15:0] psum_0_01_reg_264; +wire [0:0] tmp_fu_321_p3; +reg [0:0] tmp_reg_492; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state9_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +reg [0:0] tmp_reg_492_pp0_iter1_reg; +wire [4:0] trunc_ln25_fu_334_p1; +reg [4:0] trunc_ln25_reg_496; +reg [15:0] accum_in_0_load_reg_516; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state10_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_0_load_15_reg_521; +reg [15:0] accum_in_0_load_16_reg_536; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state11_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_0_load_17_reg_541; +reg [15:0] accum_in_0_load_18_reg_556; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state12_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_0_load_19_reg_561; +reg [15:0] accum_in_0_load_20_reg_576; +wire ap_CS_fsm_pp0_stage4; +wire ap_block_state6_pp0_stage4_iter0; +wire ap_block_state13_pp0_stage4_iter1; +wire ap_block_pp0_stage4_11001; +reg [15:0] accum_in_0_load_21_reg_581; +wire [5:0] add_ln25_fu_409_p2; +reg [5:0] add_ln25_reg_586; +wire ap_CS_fsm_pp0_stage6; +wire ap_block_state8_pp0_stage6_iter0; +wire ap_block_pp0_stage6_11001; +wire [15:0] grp_fu_305_p2; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_310_p2; +wire ap_CS_fsm_pp0_stage5; +wire ap_block_state7_pp0_stage5_iter0; +wire ap_block_state14_pp0_stage5_iter1; +wire ap_block_pp0_stage5_11001; +wire [3:0] add_ln33_fu_432_p2; +wire ap_CS_fsm_state16; +wire [0:0] tmp_61_fu_415_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage6_subdone; +wire ap_block_pp0_stage5_subdone; +reg [5:0] ap_phi_mux_x_phi_fu_172_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_184_p4; +wire ap_block_pp0_stage5; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_196_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_208_p4; +wire ap_block_pp0_stage4; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_220_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_232_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_03_phi_fu_244_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_276; +wire ap_CS_fsm_state15; +reg [15:0] ap_phi_mux_phi_ln45_phi_fu_290_p8; +wire [2:0] trunc_ln33_fu_428_p1; +wire [63:0] zext_ln25_fu_329_p1; +wire [63:0] zext_ln29_fu_344_p1; +wire [63:0] zext_ln29_16_fu_354_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln29_17_fu_364_p1; +wire [63:0] zext_ln29_18_fu_374_p1; +wire [63:0] zext_ln29_19_fu_384_p1; +wire [63:0] zext_ln29_20_fu_394_p1; +wire [63:0] zext_ln29_21_fu_404_p1; +wire [63:0] zext_ln33_fu_423_p1; +wire [63:0] zext_ln33_3_fu_444_p1; +reg [15:0] grp_fu_305_p0; +reg [15:0] grp_fu_305_p1; +reg [15:0] grp_fu_310_p0; +reg [15:0] grp_fu_310_p1; +wire [4:0] or_ln29_fu_338_p2; +wire [4:0] or_ln29_13_fu_349_p2; +wire [4:0] or_ln29_14_fu_359_p2; +wire [4:0] or_ln29_15_fu_369_p2; +wire [4:0] or_ln29_16_fu_379_p2; +wire [4:0] or_ln29_17_fu_389_p2; +wire [4:0] or_ln29_18_fu_399_p2; +wire ap_block_pp0_stage6; +wire [2:0] or_ln33_fu_438_p2; +wire [0:0] icmp_ln45_fu_449_p2; +wire [0:0] icmp_ln45_5_fu_463_p2; +wire [15:0] select_ln45_fu_455_p3; +wire [0:0] icmp_ln45_6_fu_477_p2; +wire [15:0] select_ln45_5_fu_469_p3; +wire ap_CS_fsm_state17; +reg [10:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +wire ap_block_pp0_stage1_subdone; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage4_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_570; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U382( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_305_p0), + .din1(grp_fu_305_p1), + .dout(grp_fu_305_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U383( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_310_p0), + .din1(grp_fu_310_p1), + .dout(grp_fu_310_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage5_subdone) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0)) | ((1'b0 == ap_block_pp0_stage6_subdone) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state15)) begin + q_reg_276 <= 4'd0; + end else if (((tmp_61_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + q_reg_276 <= add_ln33_fu_432_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + x_reg_168 <= add_ln25_reg_586; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_168 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_15_reg_521 <= accum_in_0_q0; + accum_in_0_load_reg_516 <= accum_in_0_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage2_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_16_reg_536 <= accum_in_0_q1; + accum_in_0_load_17_reg_541 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage3_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_18_reg_556 <= accum_in_0_q1; + accum_in_0_load_19_reg_561 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage4_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_20_reg_576 <= accum_in_0_q1; + accum_in_0_load_21_reg_581 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage6_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln25_reg_586 <= add_ln25_fu_409_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage2_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + psum_0_01_reg_264 <= grp_fu_305_p2; + psum_1_02_reg_252 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + psum_2_03_reg_240 <= grp_fu_305_p2; + psum_3_04_reg_228 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage4_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + psum_4_05_reg_216 <= grp_fu_305_p2; + psum_5_06_reg_204 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage5_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + psum_6_07_reg_192 <= grp_fu_305_p2; + psum_7_08_reg_180 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + tmp_reg_492 <= ap_phi_mux_x_phi_fu_172_p4[32'd5]; + tmp_reg_492_pp0_iter1_reg <= tmp_reg_492; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_fu_321_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln25_reg_496 <= trunc_ln25_fu_334_p1; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address0 = zext_ln29_21_fu_404_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address0 = zext_ln29_19_fu_384_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address0 = zext_ln29_17_fu_364_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address0 = zext_ln29_fu_344_p1; + end else begin + accum_in_0_address0 = 'bx; + end + end else begin + accum_in_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address1 = zext_ln29_20_fu_394_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address1 = zext_ln29_18_fu_374_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address1 = zext_ln29_16_fu_354_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address1 = zext_ln25_fu_329_p1; + end else begin + accum_in_0_address1 = 'bx; + end + end else begin + accum_in_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_61_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_61_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_reg_492 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_61_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + if ((trunc_ln33_fu_428_p1 == 3'd0)) begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = psum_0_01_reg_264; + end else if ((1'b1 == ap_condition_570)) begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = psum_6_07_reg_192; + end else if ((trunc_ln33_fu_428_p1 == 3'd4)) begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = psum_4_05_reg_216; + end else if ((trunc_ln33_fu_428_p1 == 3'd2)) begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = psum_2_03_reg_240; + end else begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (tmp_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_x_phi_fu_172_p4 = add_ln25_reg_586; + end else begin + ap_phi_mux_x_phi_fu_172_p4 = x_reg_168; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_305_p0 = ap_phi_mux_psum_6_07_phi_fu_196_p4; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_305_p0 = ap_phi_mux_psum_4_05_phi_fu_220_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p0 = ap_phi_mux_psum_2_03_phi_fu_244_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p0 = grp_fu_305_p2; + end else begin + grp_fu_305_p0 = 'bx; + end + end else begin + grp_fu_305_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_305_p1 = accum_in_0_load_20_reg_576; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_305_p1 = accum_in_0_load_18_reg_556; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p1 = accum_in_0_load_16_reg_536; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p1 = accum_in_0_load_reg_516; + end else begin + grp_fu_305_p1 = 'bx; + end + end else begin + grp_fu_305_p1 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_310_p0 = ap_phi_mux_psum_7_08_phi_fu_184_p4; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_310_p0 = ap_phi_mux_psum_5_06_phi_fu_208_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p0 = ap_phi_mux_psum_3_04_phi_fu_232_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p0 = grp_fu_310_p2; + end else begin + grp_fu_310_p0 = 'bx; + end + end else begin + grp_fu_310_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_310_p1 = accum_in_0_load_21_reg_581; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_310_p1 = accum_in_0_load_19_reg_561; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p1 = accum_in_0_load_17_reg_541; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p1 = accum_in_0_load_15_reg_521; + end else begin + grp_fu_310_p1 = 'bx; + end + end else begin + grp_fu_310_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_492 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_492 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state15; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_pp0_stage4 : begin + if ((1'b0 == ap_block_pp0_stage4_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end + end + ap_ST_fsm_pp0_stage5 : begin + if ((~((1'b0 == ap_block_pp0_stage5_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0)) & (1'b0 == ap_block_pp0_stage5_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end else if (((1'b0 == ap_block_pp0_stage5_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state15; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end + end + ap_ST_fsm_pp0_stage6 : begin + if ((1'b0 == ap_block_pp0_stage6_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + if (((tmp_61_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + ap_NS_fsm = ap_ST_fsm_state16; + end else begin + ap_NS_fsm = ap_ST_fsm_state17; + end + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln33_3_fu_444_p1; + +assign accum_out_address1 = zext_ln33_fu_423_p1; + +assign accum_out_d0 = ((icmp_ln45_6_fu_477_p2[0:0] == 1'b1) ? psum_5_06_reg_204 : select_ln45_5_fu_469_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln45_phi_fu_290_p8; + +assign add_ln25_fu_409_p2 = (x_reg_168 + 6'd8); + +assign add_ln33_fu_432_p2 = (q_reg_276 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state15 = ap_CS_fsm[32'd8]; + +assign ap_CS_fsm_state16 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd10]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage4_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage5_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_570 = (~(trunc_ln33_fu_428_p1 == 3'd0) & ~(trunc_ln33_fu_428_p1 == 3'd4) & ~(trunc_ln33_fu_428_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_03_phi_fu_244_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_232_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_220_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_208_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_196_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_184_p4 = grp_fu_310_p2; + +assign icmp_ln45_5_fu_463_p2 = ((or_ln33_fu_438_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln45_6_fu_477_p2 = ((or_ln33_fu_438_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln45_fu_449_p2 = ((or_ln33_fu_438_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln29_13_fu_349_p2 = (trunc_ln25_reg_496 | 5'd2); + +assign or_ln29_14_fu_359_p2 = (trunc_ln25_reg_496 | 5'd3); + +assign or_ln29_15_fu_369_p2 = (trunc_ln25_reg_496 | 5'd4); + +assign or_ln29_16_fu_379_p2 = (trunc_ln25_reg_496 | 5'd5); + +assign or_ln29_17_fu_389_p2 = (trunc_ln25_reg_496 | 5'd6); + +assign or_ln29_18_fu_399_p2 = (trunc_ln25_reg_496 | 5'd7); + +assign or_ln29_fu_338_p2 = (trunc_ln25_fu_334_p1 | 5'd1); + +assign or_ln33_fu_438_p2 = (trunc_ln33_fu_428_p1 | 3'd1); + +assign select_ln45_5_fu_469_p3 = ((icmp_ln45_5_fu_463_p2[0:0] == 1'b1) ? psum_3_04_reg_228 : select_ln45_fu_455_p3); + +assign select_ln45_fu_455_p3 = ((icmp_ln45_fu_449_p2[0:0] == 1'b1) ? psum_1_02_reg_252 : psum_7_08_reg_180); + +assign tmp_61_fu_415_p3 = q_reg_276[32'd3]; + +assign tmp_fu_321_p3 = ap_phi_mux_x_phi_fu_172_p4[32'd5]; + +assign trunc_ln25_fu_334_p1 = ap_phi_mux_x_phi_fu_172_p4[4:0]; + +assign trunc_ln33_fu_428_p1 = q_reg_276[2:0]; + +assign zext_ln25_fu_329_p1 = ap_phi_mux_x_phi_fu_172_p4; + +assign zext_ln29_16_fu_354_p1 = or_ln29_13_fu_349_p2; + +assign zext_ln29_17_fu_364_p1 = or_ln29_14_fu_359_p2; + +assign zext_ln29_18_fu_374_p1 = or_ln29_15_fu_369_p2; + +assign zext_ln29_19_fu_384_p1 = or_ln29_16_fu_379_p2; + +assign zext_ln29_20_fu_394_p1 = or_ln29_17_fu_389_p2; + +assign zext_ln29_21_fu_404_p1 = or_ln29_18_fu_399_p2; + +assign zext_ln29_fu_344_p1 = or_ln29_fu_338_p2; + +assign zext_ln33_3_fu_444_p1 = or_ln33_fu_438_p2; + +assign zext_ln33_fu_423_p1 = q_reg_276; + +endmodule //td_fused_top_tdf3_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state13 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [2:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_ce0; +reg accum_in_ce1; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [0:0] write_flag3_0_reg_67; +reg [0:0] write_flag6_0_reg_78; +reg [0:0] write_flag9_0_reg_89; +reg [0:0] write_flag_0_reg_100; +reg [2:0] out_idx_reg_111; +reg [15:0] accum_out_1_07_reg_122; +reg [15:0] accum_out_0_06_reg_134; +reg [15:0] accum_out_2_05_reg_146; +reg [15:0] accum_out_3_04_reg_158; +wire [2:0] add_ln74_fu_174_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln60_fu_180_p2; +reg [0:0] icmp_ln60_reg_380; +reg [0:0] icmp_ln60_reg_380_pp0_iter1_reg; +reg [0:0] icmp_ln60_reg_380_pp0_iter2_reg; +reg [0:0] icmp_ln60_reg_380_pp0_iter3_reg; +reg [0:0] icmp_ln60_reg_380_pp0_iter4_reg; +reg [0:0] icmp_ln60_reg_380_pp0_iter5_reg; +reg [0:0] icmp_ln60_reg_380_pp0_iter6_reg; +reg [0:0] icmp_ln60_reg_380_pp0_iter7_reg; +reg [0:0] icmp_ln60_reg_380_pp0_iter8_reg; +reg [0:0] icmp_ln60_reg_380_pp0_iter9_reg; +wire [1:0] trunc_ln61_fu_186_p1; +reg [1:0] trunc_ln61_reg_384; +reg [1:0] trunc_ln61_reg_384_pp0_iter1_reg; +reg [1:0] trunc_ln61_reg_384_pp0_iter2_reg; +reg [1:0] trunc_ln61_reg_384_pp0_iter3_reg; +reg [1:0] trunc_ln61_reg_384_pp0_iter4_reg; +reg [1:0] trunc_ln61_reg_384_pp0_iter5_reg; +reg [1:0] trunc_ln61_reg_384_pp0_iter6_reg; +reg [1:0] trunc_ln61_reg_384_pp0_iter7_reg; +reg [1:0] trunc_ln61_reg_384_pp0_iter8_reg; +reg [1:0] trunc_ln61_reg_384_pp0_iter9_reg; +wire [0:0] write_flag_1_fu_212_p6; +wire [0:0] write_flag9_1_fu_226_p6; +wire [0:0] write_flag6_1_fu_240_p6; +wire [0:0] write_flag3_1_fu_254_p6; +reg [15:0] accum_in_load_reg_421; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_load_1_reg_426; +wire [15:0] grp_fu_170_p2; +reg [15:0] sum0_reg_431; +wire [15:0] accum_out_3_1_fu_298_p3; +reg ap_enable_reg_pp0_iter10; +wire [15:0] accum_out_2_1_fu_306_p3; +wire [15:0] accum_out_0_1_fu_328_p3; +wire [15:0] accum_out_1_1_fu_343_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_condition_pp0_exit_iter9_state11; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln70_fu_196_p1; +wire [63:0] zext_ln70_1_fu_207_p1; +wire [2:0] i_12_fu_190_p2; +wire [2:0] or_ln70_fu_201_p2; +wire [0:0] icmp_ln73_fu_268_p2; +wire [0:0] icmp_ln73_1_fu_280_p2; +wire [15:0] select_ln73_fu_273_p3; +wire [0:0] icmp_ln73_2_fu_293_p2; +wire [15:0] select_ln73_1_fu_285_p3; +wire [15:0] select_ln73_2_fu_313_p3; +wire [15:0] select_ln73_3_fu_320_p3; +wire [15:0] select_ln73_4_fu_336_p3; +wire ap_CS_fsm_state13; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U386( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(accum_in_load_1_reg_426), + .din1(accum_in_load_reg_421), + .dout(grp_fu_170_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U387( + .din0(1'd1), + .din1(write_flag_0_reg_100), + .din2(write_flag_0_reg_100), + .din3(write_flag_0_reg_100), + .din4(trunc_ln61_fu_186_p1), + .dout(write_flag_1_fu_212_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U388( + .din0(write_flag9_0_reg_89), + .din1(write_flag9_0_reg_89), + .din2(write_flag9_0_reg_89), + .din3(1'd1), + .din4(trunc_ln61_fu_186_p1), + .dout(write_flag9_1_fu_226_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U389( + .din0(write_flag6_0_reg_78), + .din1(write_flag6_0_reg_78), + .din2(1'd1), + .din3(write_flag6_0_reg_78), + .din4(trunc_ln61_fu_186_p1), + .dout(write_flag6_1_fu_240_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U390( + .din0(write_flag3_0_reg_67), + .din1(1'd1), + .din2(write_flag3_0_reg_67), + .din3(write_flag3_0_reg_67), + .din4(trunc_ln61_fu_186_p1), + .dout(write_flag3_1_fu_254_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter9_state11))) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter8; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter9_state11) & (ap_enable_reg_pp0_iter8 == 1'b0)) | (~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln60_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + out_idx_reg_111 <= add_ln74_fu_174_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_111 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln60_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag3_0_reg_67 <= write_flag3_1_fu_254_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag3_0_reg_67 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln60_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag6_0_reg_78 <= write_flag6_1_fu_240_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_78 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln60_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag9_0_reg_89 <= write_flag9_1_fu_226_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_89 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln60_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag_0_reg_100 <= write_flag_1_fu_212_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_100 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln60_reg_380 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_load_1_reg_426 <= accum_in_q0; + accum_in_load_reg_421 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln60_reg_380_pp0_iter9_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_0_06_reg_134 <= accum_out_0_1_fu_328_p3; + accum_out_1_07_reg_122 <= accum_out_1_1_fu_343_p3; + accum_out_2_05_reg_146 <= accum_out_2_1_fu_306_p3; + accum_out_3_04_reg_158 <= accum_out_3_1_fu_298_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln60_reg_380 <= icmp_ln60_fu_180_p2; + icmp_ln60_reg_380_pp0_iter1_reg <= icmp_ln60_reg_380; + trunc_ln61_reg_384_pp0_iter1_reg <= trunc_ln61_reg_384; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln60_reg_380_pp0_iter2_reg <= icmp_ln60_reg_380_pp0_iter1_reg; + icmp_ln60_reg_380_pp0_iter3_reg <= icmp_ln60_reg_380_pp0_iter2_reg; + icmp_ln60_reg_380_pp0_iter4_reg <= icmp_ln60_reg_380_pp0_iter3_reg; + icmp_ln60_reg_380_pp0_iter5_reg <= icmp_ln60_reg_380_pp0_iter4_reg; + icmp_ln60_reg_380_pp0_iter6_reg <= icmp_ln60_reg_380_pp0_iter5_reg; + icmp_ln60_reg_380_pp0_iter7_reg <= icmp_ln60_reg_380_pp0_iter6_reg; + icmp_ln60_reg_380_pp0_iter8_reg <= icmp_ln60_reg_380_pp0_iter7_reg; + icmp_ln60_reg_380_pp0_iter9_reg <= icmp_ln60_reg_380_pp0_iter8_reg; + trunc_ln61_reg_384_pp0_iter2_reg <= trunc_ln61_reg_384_pp0_iter1_reg; + trunc_ln61_reg_384_pp0_iter3_reg <= trunc_ln61_reg_384_pp0_iter2_reg; + trunc_ln61_reg_384_pp0_iter4_reg <= trunc_ln61_reg_384_pp0_iter3_reg; + trunc_ln61_reg_384_pp0_iter5_reg <= trunc_ln61_reg_384_pp0_iter4_reg; + trunc_ln61_reg_384_pp0_iter6_reg <= trunc_ln61_reg_384_pp0_iter5_reg; + trunc_ln61_reg_384_pp0_iter7_reg <= trunc_ln61_reg_384_pp0_iter6_reg; + trunc_ln61_reg_384_pp0_iter8_reg <= trunc_ln61_reg_384_pp0_iter7_reg; + trunc_ln61_reg_384_pp0_iter9_reg <= trunc_ln61_reg_384_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln60_reg_380_pp0_iter8_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sum0_reg_431 <= grp_fu_170_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln60_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln61_reg_384 <= trunc_ln61_fu_186_p1; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_condition_pp0_exit_iter9_state11 = 1'b1; + end else begin + ap_condition_pp0_exit_iter9_state11 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln60_fu_180_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln70_1_fu_207_p1; + +assign accum_in_address1 = zext_ln70_fu_196_p1; + +assign accum_out_0_1_fu_328_p3 = ((icmp_ln73_2_fu_293_p2[0:0] == 1'b1) ? accum_out_0_06_reg_134 : select_ln73_3_fu_320_p3); + +assign accum_out_1_1_fu_343_p3 = ((icmp_ln73_2_fu_293_p2[0:0] == 1'b1) ? accum_out_1_07_reg_122 : select_ln73_4_fu_336_p3); + +assign accum_out_2_1_fu_306_p3 = ((icmp_ln73_2_fu_293_p2[0:0] == 1'b1) ? sum0_reg_431 : accum_out_2_05_reg_146); + +assign accum_out_3_1_fu_298_p3 = ((icmp_ln73_2_fu_293_p2[0:0] == 1'b1) ? accum_out_3_04_reg_158 : select_ln73_1_fu_285_p3); + +assign add_ln74_fu_174_p2 = (out_idx_reg_111 + 3'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = accum_out_0_06_reg_134; + +assign ap_return_1 = accum_out_1_07_reg_122; + +assign ap_return_2 = accum_out_2_05_reg_146; + +assign ap_return_3 = accum_out_3_04_reg_158; + +assign i_12_fu_190_p2 = out_idx_reg_111 << 3'd1; + +assign icmp_ln60_fu_180_p2 = ((out_idx_reg_111 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln73_1_fu_280_p2 = ((trunc_ln61_reg_384_pp0_iter9_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln73_2_fu_293_p2 = ((trunc_ln61_reg_384_pp0_iter9_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln73_fu_268_p2 = ((trunc_ln61_reg_384_pp0_iter9_reg == 2'd0) ? 1'b1 : 1'b0); + +assign or_ln70_fu_201_p2 = (i_12_fu_190_p2 | 3'd1); + +assign select_ln73_1_fu_285_p3 = ((icmp_ln73_1_fu_280_p2[0:0] == 1'b1) ? accum_out_3_04_reg_158 : select_ln73_fu_273_p3); + +assign select_ln73_2_fu_313_p3 = ((icmp_ln73_fu_268_p2[0:0] == 1'b1) ? sum0_reg_431 : accum_out_0_06_reg_134); + +assign select_ln73_3_fu_320_p3 = ((icmp_ln73_1_fu_280_p2[0:0] == 1'b1) ? accum_out_0_06_reg_134 : select_ln73_2_fu_313_p3); + +assign select_ln73_4_fu_336_p3 = ((icmp_ln73_1_fu_280_p2[0:0] == 1'b1) ? sum0_reg_431 : accum_out_1_07_reg_122); + +assign select_ln73_fu_273_p3 = ((icmp_ln73_fu_268_p2[0:0] == 1'b1) ? accum_out_3_04_reg_158 : sum0_reg_431); + +assign trunc_ln61_fu_186_p1 = out_idx_reg_111[1:0]; + +assign zext_ln70_1_fu_207_p1 = or_ln70_fu_201_p2; + +assign zext_ln70_fu_196_p1 = i_12_fu_190_p2; + +endmodule //td_fused_top_tdf3_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_accum_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0, + accum_in_0_ap_vld, + p_read, + accum_in_1_read, + accum_in_2_read, + accum_in_3_read +); + +parameter ap_ST_fsm_state1 = 10'd1; +parameter ap_ST_fsm_state2 = 10'd2; +parameter ap_ST_fsm_state3 = 10'd4; +parameter ap_ST_fsm_state4 = 10'd8; +parameter ap_ST_fsm_state5 = 10'd16; +parameter ap_ST_fsm_state6 = 10'd32; +parameter ap_ST_fsm_state7 = 10'd64; +parameter ap_ST_fsm_state8 = 10'd128; +parameter ap_ST_fsm_state9 = 10'd256; +parameter ap_ST_fsm_state10 = 10'd512; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_0; +output accum_in_0_ap_vld; +input [15:0] p_read; +input [15:0] accum_in_1_read; +input [15:0] accum_in_2_read; +input [15:0] accum_in_3_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_0; +reg accum_in_0_ap_vld; + +reg ap_done_reg; + reg [9:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [2:0] add_ln87_fu_92_p2; +reg [2:0] add_ln87_reg_138; +wire ap_CS_fsm_state2; +wire [15:0] tmp_fu_108_p6; +reg [15:0] tmp_reg_146; +wire [0:0] icmp_ln87_fu_98_p2; +wire [15:0] grp_fu_87_p2; +wire ap_CS_fsm_state10; +reg [2:0] i_1_1_reg_63; +reg ap_block_state1; +reg [15:0] sum_01_reg_74; +reg [15:0] accum_in_0_preg; +wire ap_CS_fsm_state3; +wire [1:0] tmp_fu_108_p5; +reg [9:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 10'd1; +#0 accum_in_0_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U392( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_74), + .din1(tmp_reg_146), + .dout(grp_fu_87_p2) +); + +td_fused_top_mux_42_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 16 )) +mux_42_16_1_1_U393( + .din0(p_read), + .din1(accum_in_1_read), + .din2(accum_in_2_read), + .din3(accum_in_3_read), + .din4(tmp_fu_108_p5), + .dout(tmp_fu_108_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_0_preg <= 16'd0; + end else begin + if (((icmp_ln87_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_0_preg <= sum_01_reg_74; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln87_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_63 <= 3'd0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + i_1_1_reg_63 <= add_ln87_reg_138; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_74 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + sum_01_reg_74 <= grp_fu_87_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln87_reg_138 <= add_ln87_fu_92_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln87_fu_98_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + tmp_reg_146 <= tmp_fu_108_p6; + end +end + +always @ (*) begin + if (((icmp_ln87_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_0 = sum_01_reg_74; + end else begin + accum_in_0 = accum_in_0_preg; + end +end + +always @ (*) begin + if (((icmp_ln87_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_0_ap_vld = 1'b1; + end else begin + accum_in_0_ap_vld = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln87_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln87_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln87_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln87_fu_92_p2 = (i_1_1_reg_63 + 3'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln87_fu_98_p2 = ((i_1_1_reg_63 == 3'd4) ? 1'b1 : 1'b0); + +assign tmp_fu_108_p5 = i_1_1_reg_63[1:0]; + +endmodule //td_fused_top_tdf3_accum_3 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 23'd1; +parameter ap_ST_fsm_state2 = 23'd2; +parameter ap_ST_fsm_state3 = 23'd4; +parameter ap_ST_fsm_state4 = 23'd8; +parameter ap_ST_fsm_state5 = 23'd16; +parameter ap_ST_fsm_state6 = 23'd32; +parameter ap_ST_fsm_state7 = 23'd64; +parameter ap_ST_fsm_state8 = 23'd128; +parameter ap_ST_fsm_state9 = 23'd256; +parameter ap_ST_fsm_state10 = 23'd512; +parameter ap_ST_fsm_state11 = 23'd1024; +parameter ap_ST_fsm_state12 = 23'd2048; +parameter ap_ST_fsm_state13 = 23'd4096; +parameter ap_ST_fsm_state14 = 23'd8192; +parameter ap_ST_fsm_state15 = 23'd16384; +parameter ap_ST_fsm_state16 = 23'd32768; +parameter ap_ST_fsm_state17 = 23'd65536; +parameter ap_ST_fsm_state18 = 23'd131072; +parameter ap_ST_fsm_state19 = 23'd262144; +parameter ap_ST_fsm_state20 = 23'd524288; +parameter ap_ST_fsm_state21 = 23'd1048576; +parameter ap_ST_fsm_state22 = 23'd2097152; +parameter ap_ST_fsm_state23 = 23'd4194304; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_read; +output [3:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [3:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg indices_23_read; + +reg ap_done_reg; + reg [22:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +wire [15:0] trunc_ln220_fu_95_p1; +reg [15:0] trunc_ln220_reg_154; +wire ap_CS_fsm_state2; +reg [15:0] tmp_227_i_i_reg_159; +reg [15:0] tmp_228_i_i_reg_164; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_81_p2; +reg [15:0] sub_i_i_i_reg_179; +wire ap_CS_fsm_state9; +wire ap_CS_fsm_state10; +wire [15:0] grp_fu_86_p2; +reg [15:0] mul_i_i_i_reg_189; +wire ap_CS_fsm_state14; +wire ap_CS_fsm_state15; +wire [15:0] grp_fu_77_p2; +reg [15:0] add_i_i_i_reg_199; +wire ap_CS_fsm_state22; +wire [63:0] zext_ln220_fu_90_p1; +reg ap_block_state1; +wire [15:0] grp_fu_77_p1; +wire [15:0] grp_fu_81_p1; +wire [15:0] grp_fu_86_p1; +wire ap_CS_fsm_state23; +wire [15:0] bitcast_ln648_fu_131_p1; +wire [0:0] tmp_fu_134_p3; +reg [22:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 23'd1; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U400( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(mul_i_i_i_reg_189), + .din1(grp_fu_77_p1), + .dout(grp_fu_77_p2) +); + +td_fused_top_hsub_16ns_16ns_16_7_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 7 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_7_full_dsp_1_U401( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sums_read), + .din1(grp_fu_81_p1), + .dout(grp_fu_81_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U402( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_179), + .din1(grp_fu_86_p1), + .dout(grp_fu_86_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state23)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state22)) begin + add_i_i_i_reg_199 <= grp_fu_77_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + mul_i_i_i_reg_189 <= grp_fu_86_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + sub_i_i_i_reg_179 <= grp_fu_81_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + tmp_227_i_i_reg_159 <= {{adjustments_q0[31:16]}}; + tmp_228_i_i_reg_164 <= {{adjustments_q0[47:32]}}; + trunc_ln220_reg_154 <= trunc_ln220_fu_95_p1; + end +end + +always @ (*) begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state23)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state23)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state18; + end + ap_ST_fsm_state18 : begin + ap_NS_fsm = ap_ST_fsm_state19; + end + ap_ST_fsm_state19 : begin + ap_NS_fsm = ap_ST_fsm_state20; + end + ap_ST_fsm_state20 : begin + ap_NS_fsm = ap_ST_fsm_state21; + end + ap_ST_fsm_state21 : begin + ap_NS_fsm = ap_ST_fsm_state22; + end + ap_ST_fsm_state22 : begin + ap_NS_fsm = ap_ST_fsm_state23; + end + ap_ST_fsm_state23 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign adjustments_address0 = zext_ln220_fu_90_p1; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state14 = ap_CS_fsm[32'd13]; + +assign ap_CS_fsm_state15 = ap_CS_fsm[32'd14]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state22 = ap_CS_fsm[32'd21]; + +assign ap_CS_fsm_state23 = ap_CS_fsm[32'd22]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_return = ((tmp_fu_134_p3[0:0] == 1'b1) ? 16'd0 : add_i_i_i_reg_199); + +assign bitcast_ln648_fu_131_p1 = add_i_i_i_reg_199; + +assign grp_fu_77_p1 = tmp_228_i_i_reg_164; + +assign grp_fu_81_p1 = trunc_ln220_reg_154; + +assign grp_fu_86_p1 = tmp_227_i_i_reg_159; + +assign tmp_fu_134_p3 = bitcast_ln648_fu_131_p1[32'd15]; + +assign trunc_ln220_fu_95_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_90_p1 = indices_23_dout; + +endmodule //td_fused_top_tdf3_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_q0, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [4:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +input [15:0] ifmap_vec_0_0_q0; +output [4:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +input [15:0] weight_vecs_0_0_0_q0; +output [4:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_0_0_ce0; +reg weight_vecs_0_0_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [5:0] ic_0_0_reg_69; +wire [5:0] add_ln149_fu_84_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln149_fu_90_p2; +reg [0:0] icmp_ln149_reg_115; +reg [0:0] icmp_ln149_reg_115_pp0_iter1_reg; +reg [0:0] icmp_ln149_reg_115_pp0_iter2_reg; +reg [0:0] icmp_ln149_reg_115_pp0_iter3_reg; +reg [0:0] icmp_ln149_reg_115_pp0_iter4_reg; +reg [0:0] icmp_ln149_reg_115_pp0_iter5_reg; +reg [0:0] icmp_ln149_reg_115_pp0_iter6_reg; +wire [4:0] trunc_ln150_fu_102_p1; +reg [4:0] trunc_ln150_reg_119; +reg [4:0] trunc_ln150_reg_119_pp0_iter1_reg; +reg [4:0] trunc_ln150_reg_119_pp0_iter2_reg; +reg [4:0] trunc_ln150_reg_119_pp0_iter3_reg; +reg [4:0] trunc_ln150_reg_119_pp0_iter4_reg; +reg [4:0] trunc_ln150_reg_119_pp0_iter5_reg; +reg [4:0] trunc_ln150_reg_119_pp0_iter6_reg; +reg [15:0] ifmap_vec_0_0_load_reg_134; +reg [15:0] weight_vecs_0_0_0_load_reg_139; +wire [15:0] grp_fu_80_p2; +reg [15:0] mul_reg_144; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +wire [63:0] zext_ln149_fu_96_p1; +wire ap_block_pp0_stage0; +wire [63:0] idxprom30_0_0_fu_106_p1; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U378( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_0_load_reg_134), + .din1(weight_vecs_0_0_0_load_reg_139), + .dout(grp_fu_80_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_0_0_reg_69 <= 6'd0; + end else if (((icmp_ln149_fu_90_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_0_0_reg_69 <= add_ln149_fu_84_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln149_reg_115 <= icmp_ln149_fu_90_p2; + icmp_ln149_reg_115_pp0_iter1_reg <= icmp_ln149_reg_115; + trunc_ln150_reg_119_pp0_iter1_reg <= trunc_ln150_reg_119; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln149_reg_115_pp0_iter2_reg <= icmp_ln149_reg_115_pp0_iter1_reg; + icmp_ln149_reg_115_pp0_iter3_reg <= icmp_ln149_reg_115_pp0_iter2_reg; + icmp_ln149_reg_115_pp0_iter4_reg <= icmp_ln149_reg_115_pp0_iter3_reg; + icmp_ln149_reg_115_pp0_iter5_reg <= icmp_ln149_reg_115_pp0_iter4_reg; + icmp_ln149_reg_115_pp0_iter6_reg <= icmp_ln149_reg_115_pp0_iter5_reg; + trunc_ln150_reg_119_pp0_iter2_reg <= trunc_ln150_reg_119_pp0_iter1_reg; + trunc_ln150_reg_119_pp0_iter3_reg <= trunc_ln150_reg_119_pp0_iter2_reg; + trunc_ln150_reg_119_pp0_iter4_reg <= trunc_ln150_reg_119_pp0_iter3_reg; + trunc_ln150_reg_119_pp0_iter5_reg <= trunc_ln150_reg_119_pp0_iter4_reg; + trunc_ln150_reg_119_pp0_iter6_reg <= trunc_ln150_reg_119_pp0_iter5_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_reg_115 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_load_reg_134 <= ifmap_vec_0_0_q0; + weight_vecs_0_0_0_load_reg_139 <= weight_vecs_0_0_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_reg_115_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_reg_144 <= grp_fu_80_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_fu_90_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln150_reg_119 <= trunc_ln150_fu_102_p1; + end +end + +always @ (*) begin + if ((icmp_ln149_fu_90_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln149_reg_115_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln149_fu_90_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln149_fu_90_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln149_fu_84_p2 = (ic_0_0_reg_69 + 6'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign icmp_ln149_fu_90_p2 = ((ic_0_0_reg_69 == 6'd32) ? 1'b1 : 1'b0); + +assign idxprom30_0_0_fu_106_p1 = trunc_ln150_reg_119_pp0_iter6_reg; + +assign ifmap_vec_0_0_address0 = zext_ln149_fu_96_p1; + +assign products_0_address0 = idxprom30_0_0_fu_106_p1; + +assign products_0_d0 = mul_reg_144; + +assign trunc_ln150_fu_102_p1 = ic_0_0_reg_69[4:0]; + +assign weight_vecs_0_0_0_address0 = zext_ln149_fu_96_p1; + +assign zext_ln149_fu_96_p1 = ic_0_0_reg_69; + +endmodule //td_fused_top_tdf3_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf3_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 9; +parameter MEM_SIZE = 512; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf3_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd512; +parameter AddressWidth = 32'd9; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf3_filters_ram td_fused_top_tdf3_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + indices_2_out_din, + indices_2_out_full_n, + indices_2_out_write, + indices_2_out1_din, + indices_2_out1_full_n, + indices_2_out1_write +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [3:0] indices_2_out_din; +input indices_2_out_full_n; +output indices_2_out_write; +output [3:0] indices_2_out1_din; +input indices_2_out1_full_n; +output indices_2_out1_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg indices_0_write; +reg indices_1_write; +reg indices_2_out_write; +reg indices_2_out1_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [15:0] i_2; +reg [15:0] j_2; +reg [15:0] k_2; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg indices_2_out_blk_n; +reg indices_2_out1_blk_n; +reg [0:0] ap_phi_mux_j_14_flag_0_i_phi_fu_77_p6; +reg ap_block_state1; +wire [0:0] icmp_ln108_fu_141_p2; +wire [0:0] icmp_ln111_fu_154_p2; +reg [15:0] ap_phi_mux_j_14_new_0_i_phi_fu_91_p6; +wire [15:0] add_ln110_fu_147_p2; +reg [15:0] ap_phi_mux_k_14_new_0_i_phi_fu_104_p6; +wire [15:0] add_ln107_fu_134_p2; +wire [15:0] select_ln114_fu_172_p3; +wire [3:0] trunc_ln106_fu_128_p1; +wire [15:0] add_ln113_fu_160_p2; +wire [0:0] icmp_ln114_fu_166_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_2 = 16'd0; +#0 j_2 = 16'd0; +#0 k_2 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln111_fu_154_p2 == 1'd1) & (icmp_ln108_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_2 <= select_ln114_fu_172_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_14_flag_0_i_phi_fu_77_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j_2 <= ap_phi_mux_j_14_new_0_i_phi_fu_91_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k_2 <= ap_phi_mux_k_14_new_0_i_phi_fu_104_p6; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln108_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_14_flag_0_i_phi_fu_77_p6 = 1'd0; + end else if ((((icmp_ln111_fu_154_p2 == 1'd0) & (icmp_ln108_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln111_fu_154_p2 == 1'd1) & (icmp_ln108_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_14_flag_0_i_phi_fu_77_p6 = 1'd1; + end else begin + ap_phi_mux_j_14_flag_0_i_phi_fu_77_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln108_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln111_fu_154_p2 == 1'd0)) begin + ap_phi_mux_j_14_new_0_i_phi_fu_91_p6 = add_ln110_fu_147_p2; + end else if ((icmp_ln111_fu_154_p2 == 1'd1)) begin + ap_phi_mux_j_14_new_0_i_phi_fu_91_p6 = 16'd0; + end else begin + ap_phi_mux_j_14_new_0_i_phi_fu_91_p6 = 'bx; + end + end else begin + ap_phi_mux_j_14_new_0_i_phi_fu_91_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln108_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_14_new_0_i_phi_fu_104_p6 = add_ln107_fu_134_p2; + end else if ((((icmp_ln111_fu_154_p2 == 1'd0) & (icmp_ln108_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln111_fu_154_p2 == 1'd1) & (icmp_ln108_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_14_new_0_i_phi_fu_104_p6 = 16'd0; + end else begin + ap_phi_mux_k_14_new_0_i_phi_fu_104_p6 = 'bx; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_blk_n = indices_2_out1_full_n; + end else begin + indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_write = 1'b1; + end else begin + indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_blk_n = indices_2_out_full_n; + end else begin + indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_write = 1'b1; + end else begin + indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln107_fu_134_p2 = (k_2 + 16'd1); + +assign add_ln110_fu_147_p2 = (j_2 + 16'd1); + +assign add_ln113_fu_160_p2 = (i_2 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign icmp_ln108_fu_141_p2 = ((add_ln107_fu_134_p2 == 16'd16) ? 1'b1 : 1'b0); + +assign icmp_ln111_fu_154_p2 = ((add_ln110_fu_147_p2 == 16'd56) ? 1'b1 : 1'b0); + +assign icmp_ln114_fu_166_p2 = ((add_ln113_fu_160_p2 == 16'd56) ? 1'b1 : 1'b0); + +assign indices_0_din = i_2; + +assign indices_1_din = j_2; + +assign indices_2_out1_din = trunc_ln106_fu_128_p1; + +assign indices_2_out_din = trunc_ln106_fu_128_p1; + +assign select_ln114_fu_172_p3 = ((icmp_ln114_fu_166_p2[0:0] == 1'b1) ? 16'd0 : add_ln113_fu_160_p2); + +assign start_out = real_start; + +assign trunc_ln106_fu_128_p1 = k_2[3:0]; + +endmodule //td_fused_top_tdf3_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_readFilters30 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_we0, + weight_vecs_0_0_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state4 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [8:0] filter_data_address0; +output filter_data_ce0; +input [15:0] filter_data_q0; +input [3:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [4:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +output weight_vecs_0_0_0_we0; +output [15:0] weight_vecs_0_0_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg indices_23_read; +reg weight_vecs_0_0_0_ce0; +reg weight_vecs_0_0_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [5:0] kk_0_0_i_i_reg_93; +wire [8:0] tmp_fu_105_p3; +reg [8:0] tmp_reg_144; +wire [5:0] add_ln49_fu_113_p2; +reg [5:0] add_ln49_reg_149; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln49_fu_119_p2; +reg [0:0] icmp_ln49_reg_154; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg [5:0] ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln55_27_fu_134_p1; +wire [63:0] zext_ln49_fu_139_p1; +wire [8:0] zext_ln55_fu_125_p1; +wire [8:0] add_ln55_fu_129_p2; +wire ap_CS_fsm_state4; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state4)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_0_0_i_i_reg_93 <= add_ln49_reg_149; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_0_0_i_i_reg_93 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln49_reg_149 <= add_ln49_fu_113_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln49_reg_154 <= icmp_ln49_fu_119_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + tmp_reg_144[8 : 5] <= tmp_fu_105_p3[8 : 5]; + end +end + +always @ (*) begin + if ((icmp_ln49_fu_119_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 = add_ln49_reg_149; + end else begin + ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 = kk_0_0_i_i_reg_93; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((icmp_ln49_fu_119_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((icmp_ln49_fu_119_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln49_fu_113_p2 = (ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 + 6'd1); + +assign add_ln55_fu_129_p2 = (tmp_reg_144 + zext_ln55_fu_125_p1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_address0 = zext_ln55_27_fu_134_p1; + +assign icmp_ln49_fu_119_p2 = ((ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 == 6'd32) ? 1'b1 : 1'b0); + +assign tmp_fu_105_p3 = {{indices_23_dout}, {5'd0}}; + +assign weight_vecs_0_0_0_address0 = zext_ln49_fu_139_p1; + +assign weight_vecs_0_0_0_d0 = filter_data_q0; + +assign zext_ln49_fu_139_p1 = kk_0_0_i_i_reg_93; + +assign zext_ln55_27_fu_134_p1 = add_ln55_fu_129_p2; + +assign zext_ln55_fu_125_p1 = ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4; + +always @ (posedge ap_clk) begin + tmp_reg_144[4:0] <= 5'b00000; +end + +endmodule //td_fused_top_tdf3_readFilters30 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_readInputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_we0, + ifmap_vec_0_0_d0, + ifmap_vec_0_0_address1, + ifmap_vec_0_0_ce1, + ifmap_vec_0_0_we1, + ifmap_vec_0_0_d1, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 5'd1; +parameter ap_ST_fsm_state2 = 5'd2; +parameter ap_ST_fsm_pp0_stage0 = 5'd4; +parameter ap_ST_fsm_pp0_stage1 = 5'd8; +parameter ap_ST_fsm_state6 = 5'd16; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [14:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [4:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +output ifmap_vec_0_0_we0; +output [15:0] ifmap_vec_0_0_d0; +output [4:0] ifmap_vec_0_0_address1; +output ifmap_vec_0_0_ce1; +output ifmap_vec_0_0_we1; +output [15:0] ifmap_vec_0_0_d1; +output [5:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [11:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg[4:0] ifmap_vec_0_0_address0; +reg ifmap_vec_0_0_ce0; +reg ifmap_vec_0_0_we0; +reg[15:0] ifmap_vec_0_0_d0; +reg[4:0] ifmap_vec_0_0_address1; +reg ifmap_vec_0_0_ce1; +reg ifmap_vec_0_0_we1; +reg[15:0] ifmap_vec_0_0_d1; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [4:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [5:0] kk_0_i_i_reg_178; +wire [5:0] trunc_ln165_fu_190_p1; +reg [5:0] trunc_ln165_reg_432; +reg [15:0] col_coord_reg_437; +wire [0:0] is_padding_fu_212_p2; +reg [0:0] is_padding_reg_442; +wire [13:0] add_ln32_fu_272_p2; +reg [13:0] add_ln32_reg_452; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln25_fu_278_p2; +reg [0:0] icmp_ln25_reg_457; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state5_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +wire [5:0] add_ln25_fu_306_p2; +reg [5:0] add_ln25_reg_466; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state4_pp0_stage1_iter0; +wire ap_block_pp0_stage1_11001; +wire [4:0] empty_117_fu_317_p1; +reg [4:0] empty_117_reg_471; +wire [15:0] select_ln33_16_fu_384_p3; +reg [15:0] select_ln33_16_reg_477; +wire [15:0] select_ln33_17_fu_405_p3; +reg [15:0] select_ln33_17_reg_482; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state3; +reg ap_enable_reg_pp0_iter1; +wire ap_block_pp0_stage1_subdone; +reg [5:0] ap_phi_mux_kk_0_i_i_phi_fu_182_p4; +wire ap_block_pp0_stage0; +wire [63:0] sext_ln32_fu_301_p1; +wire [63:0] kk_0_cast4_i_i_fu_312_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln32_13_fu_343_p1; +wire [63:0] zext_ln32_14_fu_417_p1; +wire [63:0] zext_ln32_15_fu_427_p1; +reg ap_block_state1; +wire [15:0] select_ln33_fu_329_p3; +wire [15:0] select_ln33_15_fu_362_p3; +wire [0:0] cmp7_i_i_fu_200_p2; +wire [0:0] icmp_ln24_fu_206_p2; +wire [5:0] empty_115_fu_218_p1; +wire [5:0] row_coord_int_fu_221_p3; +wire [11:0] tmp_fu_234_p3; +wire [8:0] tmp_s_fu_246_p3; +wire [12:0] zext_ln32_fu_242_p1; +wire [12:0] zext_ln32_34_fu_254_p1; +wire [12:0] sub_ln32_fu_258_p2; +wire [5:0] col_coord_int_fu_227_p3; +wire [13:0] sub_ln32_cast_fu_264_p1; +wire [13:0] zext_ln32_35_fu_268_p1; +wire [2:0] lshr_ln_fu_284_p4; +wire [16:0] tmp_60_fu_294_p3; +wire [15:0] trunc_ln32_fu_321_p1; +wire [15:0] bitcast_ln32_fu_325_p1; +wire [4:0] or_ln25_fu_337_p2; +wire [15:0] tmp_224_i_i_fu_348_p4; +wire [15:0] bitcast_ln32_7_fu_358_p1; +wire [15:0] tmp_225_i_i_fu_370_p4; +wire [15:0] bitcast_ln32_8_fu_380_p1; +wire [15:0] tmp_226_i_i_fu_391_p4; +wire [15:0] bitcast_ln32_9_fu_401_p1; +wire [4:0] or_ln25_5_fu_412_p2; +wire [4:0] or_ln25_6_fu_422_p2; +wire ap_CS_fsm_state6; +reg [4:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 5'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b0)))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_i_i_reg_178 <= add_ln25_reg_466; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + kk_0_i_i_reg_178 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln25_reg_466 <= add_ln25_fu_306_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln32_reg_452 <= add_ln32_fu_272_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + col_coord_reg_437 <= indices_12_dout; + is_padding_reg_442 <= is_padding_fu_212_p2; + trunc_ln165_reg_432 <= trunc_ln165_fu_190_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + empty_117_reg_471 <= empty_117_fu_317_p1; + select_ln33_16_reg_477 <= select_ln33_16_fu_384_p3; + select_ln33_17_reg_482 <= select_ln33_17_fu_405_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln25_reg_457 <= icmp_ln25_fu_278_p2; + end +end + +always @ (*) begin + if ((icmp_ln25_fu_278_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_i_i_phi_fu_182_p4 = add_ln25_reg_466; + end else begin + ap_phi_mux_kk_0_i_i_phi_fu_182_p4 = kk_0_i_i_reg_178; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_address0 = zext_ln32_15_fu_427_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ifmap_vec_0_0_address0 = zext_ln32_13_fu_343_p1; + end else begin + ifmap_vec_0_0_address0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_address1 = zext_ln32_14_fu_417_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ifmap_vec_0_0_address1 = kk_0_cast4_i_i_fu_312_p1; + end else begin + ifmap_vec_0_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ifmap_vec_0_0_ce1 = 1'b1; + end else begin + ifmap_vec_0_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_d0 = select_ln33_17_reg_482; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ifmap_vec_0_0_d0 = select_ln33_15_fu_362_p3; + end else begin + ifmap_vec_0_0_d0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_d1 = select_ln33_16_reg_477; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ifmap_vec_0_0_d1 = select_ln33_fu_329_p3; + end else begin + ifmap_vec_0_0_d1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ifmap_vec_0_0_we0 = 1'b1; + end else begin + ifmap_vec_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ifmap_vec_0_0_we1 = 1'b1; + end else begin + ifmap_vec_0_0_we1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln25_fu_278_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln25_fu_278_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln25_fu_306_p2 = (kk_0_i_i_reg_178 + 6'd4); + +assign add_ln32_fu_272_p2 = ((sub_ln32_cast_fu_264_p1) + (zext_ln32_35_fu_268_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd4]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln32_7_fu_358_p1 = tmp_224_i_i_fu_348_p4; + +assign bitcast_ln32_8_fu_380_p1 = tmp_225_i_i_fu_370_p4; + +assign bitcast_ln32_9_fu_401_p1 = tmp_226_i_i_fu_391_p4; + +assign bitcast_ln32_fu_325_p1 = trunc_ln32_fu_321_p1; + +assign cmp7_i_i_fu_200_p2 = ((indices_01_dout > 16'd55) ? 1'b1 : 1'b0); + +assign col_coord_int_fu_227_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 6'd0 : empty_115_fu_218_p1); + +assign empty_115_fu_218_p1 = col_coord_reg_437[5:0]; + +assign empty_117_fu_317_p1 = kk_0_i_i_reg_178[4:0]; + +assign icmp_ln24_fu_206_p2 = ((indices_12_dout > 16'd55) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_278_p2 = ((ap_phi_mux_kk_0_i_i_phi_fu_182_p4 == 6'd32) ? 1'b1 : 1'b0); + +assign in_data_address0 = sext_ln32_fu_301_p1; + +assign indices_01_out_din = indices_01_dout[5:0]; + +assign indices_12_out_din = indices_12_dout[11:0]; + +assign is_padding_fu_212_p2 = (icmp_ln24_fu_206_p2 | cmp7_i_i_fu_200_p2); + +assign kk_0_cast4_i_i_fu_312_p1 = kk_0_i_i_reg_178; + +assign lshr_ln_fu_284_p4 = {{ap_phi_mux_kk_0_i_i_phi_fu_182_p4[4:2]}}; + +assign or_ln25_5_fu_412_p2 = (empty_117_reg_471 | 5'd2); + +assign or_ln25_6_fu_422_p2 = (empty_117_reg_471 | 5'd3); + +assign or_ln25_fu_337_p2 = (empty_117_fu_317_p1 | 5'd1); + +assign row_coord_int_fu_221_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 6'd0 : trunc_ln165_reg_432); + +assign select_ln33_15_fu_362_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_7_fu_358_p1); + +assign select_ln33_16_fu_384_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_8_fu_380_p1); + +assign select_ln33_17_fu_405_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_9_fu_401_p1); + +assign select_ln33_fu_329_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_fu_325_p1); + +assign sext_ln32_fu_301_p1 = (tmp_60_fu_294_p3); + +assign sub_ln32_cast_fu_264_p1 = (sub_ln32_fu_258_p2); + +assign sub_ln32_fu_258_p2 = (zext_ln32_fu_242_p1 - zext_ln32_34_fu_254_p1); + +assign tmp_224_i_i_fu_348_p4 = {{in_data_q0[31:16]}}; + +assign tmp_225_i_i_fu_370_p4 = {{in_data_q0[47:32]}}; + +assign tmp_226_i_i_fu_391_p4 = {{in_data_q0[63:48]}}; + +assign tmp_60_fu_294_p3 = {{add_ln32_reg_452}, {lshr_ln_fu_284_p4}}; + +assign tmp_fu_234_p3 = {{row_coord_int_fu_221_p3}, {6'd0}}; + +assign tmp_s_fu_246_p3 = {{row_coord_int_fu_221_p3}, {3'd0}}; + +assign trunc_ln165_fu_190_p1 = indices_01_dout[5:0]; + +assign trunc_ln32_fu_321_p1 = in_data_q0[15:0]; + +assign zext_ln32_13_fu_343_p1 = or_ln25_fu_337_p2; + +assign zext_ln32_14_fu_417_p1 = or_ln25_5_fu_412_p2; + +assign zext_ln32_15_fu_427_p1 = or_ln25_6_fu_422_p2; + +assign zext_ln32_34_fu_254_p1 = tmp_s_fu_246_p3; + +assign zext_ln32_35_fu_268_p1 = col_coord_int_fu_227_p3; + +assign zext_ln32_fu_242_p1 = tmp_fu_234_p3; + +endmodule //td_fused_top_tdf3_readInputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_writeOutputs_unaligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + p_read, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_state2 = 3'd2; +parameter ap_ST_fsm_state3 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [5:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [11:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [15:0] p_read; +output [13:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg out_data_ce1; +reg out_data_we1; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] outputCount_2; +reg [15:0] outputChanIdx_2; +reg [15:0] outputRow_4_0; +reg [15:0] outputRow_4_1; +reg [15:0] outputRow_4_2; +reg [15:0] outputRow_4_3; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg [5:0] indices_01_read_reg_309; +reg [11:0] indices_12_read_reg_315; +wire [13:0] shl_ln89_fu_160_p2; +reg [13:0] shl_ln89_reg_320; +wire ap_CS_fsm_state2; +wire [15:0] add_ln87_fu_198_p2; +wire [0:0] icmp_ln88_fu_204_p2; +reg [0:0] icmp_ln88_reg_333; +reg [15:0] ap_phi_mux_empty_phi_fu_112_p4; +reg [15:0] empty_reg_109; +wire ap_CS_fsm_state3; +wire [63:0] zext_ln94_8_fu_231_p1; +wire [15:0] select_ln97_fu_289_p3; +wire [1:0] trunc_ln86_fu_170_p1; +reg ap_block_state1; +wire [11:0] tmp_fu_119_p3; +wire [8:0] tmp_s_fu_130_p3; +wire [12:0] zext_ln94_fu_126_p1; +wire [12:0] zext_ln94_5_fu_137_p1; +wire [12:0] sub_ln94_fu_141_p2; +wire [13:0] sub_ln94_cast13_fu_147_p1; +wire [13:0] zext_ln94_6_fu_151_p1; +wire [13:0] add_ln94_fu_154_p2; +wire [3:0] trunc_ln94_fu_218_p1; +wire [13:0] zext_ln94_7_fu_222_p1; +wire [13:0] add_ln94_3_fu_226_p2; +wire [15:0] bitcast_ln94_9_fu_260_p1; +wire [15:0] bitcast_ln94_8_fu_252_p1; +wire [15:0] bitcast_ln94_7_fu_244_p1; +wire [15:0] bitcast_ln94_fu_236_p1; +wire [15:0] add_ln96_fu_277_p2; +wire [0:0] icmp_ln97_fu_283_p2; +reg [2:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 outputCount_2 = 16'd0; +#0 outputChanIdx_2 = 16'd0; +#0 outputRow_4_0 = 16'd0; +#0 outputRow_4_1 = 16'd0; +#0 outputRow_4_2 = 16'd0; +#0 outputRow_4_3 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state3)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_reg_333 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + empty_reg_109 <= 16'd0; + end else if (((icmp_ln88_fu_204_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + empty_reg_109 <= add_ln87_fu_198_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + icmp_ln88_reg_333 <= icmp_ln88_fu_204_p2; + shl_ln89_reg_320[13 : 2] <= shl_ln89_fu_160_p2[13 : 2]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + indices_01_read_reg_309 <= indices_01_dout; + indices_12_read_reg_315 <= indices_12_dout; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_reg_333 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + outputChanIdx_2 <= select_ln97_fu_289_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + outputCount_2 <= ap_phi_mux_empty_phi_fu_112_p4; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_170_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_4_0 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_170_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_4_1 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_170_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_4_2 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_170_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_4_3 <= p_read; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_reg_333 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + ap_phi_mux_empty_phi_fu_112_p4 = 16'd0; + end else begin + ap_phi_mux_empty_phi_fu_112_p4 = empty_reg_109; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_reg_333 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln87_fu_198_p2 = (outputCount_2 + 16'd1); + +assign add_ln94_3_fu_226_p2 = (shl_ln89_reg_320 + zext_ln94_7_fu_222_p1); + +assign add_ln94_fu_154_p2 = (sub_ln94_cast13_fu_147_p1 + zext_ln94_6_fu_151_p1); + +assign add_ln96_fu_277_p2 = (outputChanIdx_2 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign bitcast_ln94_7_fu_244_p1 = outputRow_4_1; + +assign bitcast_ln94_8_fu_252_p1 = outputRow_4_2; + +assign bitcast_ln94_9_fu_260_p1 = outputRow_4_3; + +assign bitcast_ln94_fu_236_p1 = outputRow_4_0; + +assign icmp_ln88_fu_204_p2 = ((add_ln87_fu_198_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign icmp_ln97_fu_283_p2 = ((add_ln96_fu_277_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign out_data_address1 = zext_ln94_8_fu_231_p1; + +assign out_data_d1 = {{{{bitcast_ln94_9_fu_260_p1}, {bitcast_ln94_8_fu_252_p1}}, {bitcast_ln94_7_fu_244_p1}}, {bitcast_ln94_fu_236_p1}}; + +assign select_ln97_fu_289_p3 = ((icmp_ln97_fu_283_p2[0:0] == 1'b1) ? 16'd0 : add_ln96_fu_277_p2); + +assign shl_ln89_fu_160_p2 = add_ln94_fu_154_p2 << 14'd2; + +assign sub_ln94_cast13_fu_147_p1 = sub_ln94_fu_141_p2; + +assign sub_ln94_fu_141_p2 = (zext_ln94_fu_126_p1 - zext_ln94_5_fu_137_p1); + +assign tmp_fu_119_p3 = {{indices_01_read_reg_309}, {6'd0}}; + +assign tmp_s_fu_130_p3 = {{indices_01_read_reg_309}, {3'd0}}; + +assign trunc_ln86_fu_170_p1 = outputCount_2[1:0]; + +assign trunc_ln94_fu_218_p1 = outputChanIdx_2[3:0]; + +assign zext_ln94_5_fu_137_p1 = tmp_s_fu_130_p3; + +assign zext_ln94_6_fu_151_p1 = indices_12_read_reg_315; + +assign zext_ln94_7_fu_222_p1 = trunc_ln94_fu_218_p1; + +assign zext_ln94_8_fu_231_p1 = add_ln94_3_fu_226_p2; + +assign zext_ln94_fu_126_p1 = tmp_fu_119_p3; + +always @ (posedge ap_clk) begin + shl_ln89_reg_320[1:0] <= 2'b00; +end + +endmodule //td_fused_top_tdf3_writeOutputs_unaligned +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_111 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + l1_filter_data_0_address0, + l1_filter_data_0_ce0, + l1_filter_data_0_d0, + l1_filter_data_0_q0, + l1_filter_data_0_we0, + l1_filter_data_0_address1, + l1_filter_data_0_ce1, + l1_filter_data_0_d1, + l1_filter_data_0_q1, + l1_filter_data_0_we1, + l1_filter_data_1_address0, + l1_filter_data_1_ce0, + l1_filter_data_1_d0, + l1_filter_data_1_q0, + l1_filter_data_1_we0, + l1_filter_data_1_address1, + l1_filter_data_1_ce1, + l1_filter_data_1_d1, + l1_filter_data_1_q1, + l1_filter_data_1_we1, + l1_filter_data_2_address0, + l1_filter_data_2_ce0, + l1_filter_data_2_d0, + l1_filter_data_2_q0, + l1_filter_data_2_we0, + l1_filter_data_2_address1, + l1_filter_data_2_ce1, + l1_filter_data_2_d1, + l1_filter_data_2_q1, + l1_filter_data_2_we1, + l1_filter_data_3_address0, + l1_filter_data_3_ce0, + l1_filter_data_3_d0, + l1_filter_data_3_q0, + l1_filter_data_3_we0, + l1_filter_data_3_address1, + l1_filter_data_3_ce1, + l1_filter_data_3_d1, + l1_filter_data_3_q1, + l1_filter_data_3_we1, + l2_filter_data_0_address0, + l2_filter_data_0_ce0, + l2_filter_data_0_d0, + l2_filter_data_0_q0, + l2_filter_data_0_we0, + l2_filter_data_0_address1, + l2_filter_data_0_ce1, + l2_filter_data_0_d1, + l2_filter_data_0_q1, + l2_filter_data_0_we1, + l2_filter_data_1_address0, + l2_filter_data_1_ce0, + l2_filter_data_1_d0, + l2_filter_data_1_q0, + l2_filter_data_1_we0, + l2_filter_data_1_address1, + l2_filter_data_1_ce1, + l2_filter_data_1_d1, + l2_filter_data_1_q1, + l2_filter_data_1_we1, + l1_adjustments_address0, + l1_adjustments_ce0, + l1_adjustments_d0, + l1_adjustments_q0, + l1_adjustments_we0, + l1_adjustments_address1, + l1_adjustments_ce1, + l1_adjustments_d1, + l1_adjustments_q1, + l1_adjustments_we1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_d0, + l2_adjustments_q0, + l2_adjustments_we0, + l2_adjustments_address1, + l2_adjustments_ce1, + l2_adjustments_d1, + l2_adjustments_q1, + l2_adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [13:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [13:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [13:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [13:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [10:0] l1_filter_data_0_address0; +output l1_filter_data_0_ce0; +output [63:0] l1_filter_data_0_d0; +input [63:0] l1_filter_data_0_q0; +output l1_filter_data_0_we0; +output [10:0] l1_filter_data_0_address1; +output l1_filter_data_0_ce1; +output [63:0] l1_filter_data_0_d1; +input [63:0] l1_filter_data_0_q1; +output l1_filter_data_0_we1; +output [10:0] l1_filter_data_1_address0; +output l1_filter_data_1_ce0; +output [63:0] l1_filter_data_1_d0; +input [63:0] l1_filter_data_1_q0; +output l1_filter_data_1_we0; +output [10:0] l1_filter_data_1_address1; +output l1_filter_data_1_ce1; +output [63:0] l1_filter_data_1_d1; +input [63:0] l1_filter_data_1_q1; +output l1_filter_data_1_we1; +output [10:0] l1_filter_data_2_address0; +output l1_filter_data_2_ce0; +output [63:0] l1_filter_data_2_d0; +input [63:0] l1_filter_data_2_q0; +output l1_filter_data_2_we0; +output [10:0] l1_filter_data_2_address1; +output l1_filter_data_2_ce1; +output [63:0] l1_filter_data_2_d1; +input [63:0] l1_filter_data_2_q1; +output l1_filter_data_2_we1; +output [10:0] l1_filter_data_3_address0; +output l1_filter_data_3_ce0; +output [63:0] l1_filter_data_3_d0; +input [63:0] l1_filter_data_3_q0; +output l1_filter_data_3_we0; +output [10:0] l1_filter_data_3_address1; +output l1_filter_data_3_ce1; +output [63:0] l1_filter_data_3_d1; +input [63:0] l1_filter_data_3_q1; +output l1_filter_data_3_we1; +output [9:0] l2_filter_data_0_address0; +output l2_filter_data_0_ce0; +output [15:0] l2_filter_data_0_d0; +input [15:0] l2_filter_data_0_q0; +output l2_filter_data_0_we0; +output [9:0] l2_filter_data_0_address1; +output l2_filter_data_0_ce1; +output [15:0] l2_filter_data_0_d1; +input [15:0] l2_filter_data_0_q1; +output l2_filter_data_0_we1; +output [9:0] l2_filter_data_1_address0; +output l2_filter_data_1_ce0; +output [15:0] l2_filter_data_1_d0; +input [15:0] l2_filter_data_1_q0; +output l2_filter_data_1_we0; +output [9:0] l2_filter_data_1_address1; +output l2_filter_data_1_ce1; +output [15:0] l2_filter_data_1_d1; +input [15:0] l2_filter_data_1_q1; +output l2_filter_data_1_we1; +output [6:0] l1_adjustments_address0; +output l1_adjustments_ce0; +output [47:0] l1_adjustments_d0; +input [47:0] l1_adjustments_q0; +output l1_adjustments_we0; +output [6:0] l1_adjustments_address1; +output l1_adjustments_ce1; +output [47:0] l1_adjustments_d1; +input [47:0] l1_adjustments_q1; +output l1_adjustments_we1; +output [3:0] l2_adjustments_address0; +output l2_adjustments_ce0; +output [47:0] l2_adjustments_d0; +input [47:0] l2_adjustments_q0; +output l2_adjustments_we0; +output [3:0] l2_adjustments_address1; +output l2_adjustments_ce1; +output [47:0] l2_adjustments_d1; +input [47:0] l2_adjustments_q1; +output l2_adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [13:0] dataflow_in_loop_TOP_LOOP48232_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP48232_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48232_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP48232_U0_in_data_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP48232_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP48232_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48232_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP48232_U0_in_data_we1; +wire [10:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_address0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_d0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_we0; +wire [10:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_address1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_d1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_we1; +wire [10:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_address0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_d0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_we0; +wire [10:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_address1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_d1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_we1; +wire [10:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_address0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_d0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_we0; +wire [10:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_address1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_d1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_we1; +wire [10:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_address0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_d0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_we0; +wire [10:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_address1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_d1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_we1; +wire [6:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_we0; +wire [6:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_we1; +wire [9:0] dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_address0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_d0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_we0; +wire [9:0] dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_address1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_d1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_we1; +wire [9:0] dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_address0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_d0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_we0; +wire [9:0] dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_address1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_d1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP48232_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP48232_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48232_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP48232_U0_out_data_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP48232_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP48232_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48232_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP48232_U0_out_data_we1; +wire [3:0] dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_we0; +wire [3:0] dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_we1; +wire dataflow_in_loop_TOP_LOOP48232_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP48232_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP48232_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP48232_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP48232_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP48232_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP48232_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP48232_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP48232_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [16:0] loop_dataflow_input_count; +reg [16:0] loop_dataflow_output_count; +wire [16:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP48232_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP48232_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 17'd0; +#0 loop_dataflow_output_count = 17'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP48232 dataflow_in_loop_TOP_LOOP48232_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP48232_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP48232_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP48232_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP48232_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP48232_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP48232_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP48232_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP48232_U0_in_data_we1), + .l1_filter_data_0_address0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_address0), + .l1_filter_data_0_ce0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_ce0), + .l1_filter_data_0_d0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_d0), + .l1_filter_data_0_q0(l1_filter_data_0_q0), + .l1_filter_data_0_we0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_we0), + .l1_filter_data_0_address1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_address1), + .l1_filter_data_0_ce1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_ce1), + .l1_filter_data_0_d1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_d1), + .l1_filter_data_0_q1(64'd0), + .l1_filter_data_0_we1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_we1), + .l1_filter_data_1_address0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_address0), + .l1_filter_data_1_ce0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_ce0), + .l1_filter_data_1_d0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_d0), + .l1_filter_data_1_q0(l1_filter_data_1_q0), + .l1_filter_data_1_we0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_we0), + .l1_filter_data_1_address1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_address1), + .l1_filter_data_1_ce1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_ce1), + .l1_filter_data_1_d1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_d1), + .l1_filter_data_1_q1(64'd0), + .l1_filter_data_1_we1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_we1), + .l1_filter_data_2_address0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_address0), + .l1_filter_data_2_ce0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_ce0), + .l1_filter_data_2_d0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_d0), + .l1_filter_data_2_q0(l1_filter_data_2_q0), + .l1_filter_data_2_we0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_we0), + .l1_filter_data_2_address1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_address1), + .l1_filter_data_2_ce1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_ce1), + .l1_filter_data_2_d1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_d1), + .l1_filter_data_2_q1(64'd0), + .l1_filter_data_2_we1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_we1), + .l1_filter_data_3_address0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_address0), + .l1_filter_data_3_ce0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_ce0), + .l1_filter_data_3_d0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_d0), + .l1_filter_data_3_q0(l1_filter_data_3_q0), + .l1_filter_data_3_we0(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_we0), + .l1_filter_data_3_address1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_address1), + .l1_filter_data_3_ce1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_ce1), + .l1_filter_data_3_d1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_d1), + .l1_filter_data_3_q1(64'd0), + .l1_filter_data_3_we1(dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_we1), + .l1_adjustments_address0(dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_address0), + .l1_adjustments_ce0(dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_ce0), + .l1_adjustments_d0(dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_d0), + .l1_adjustments_q0(l1_adjustments_q0), + .l1_adjustments_we0(dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_we0), + .l1_adjustments_address1(dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_address1), + .l1_adjustments_ce1(dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_ce1), + .l1_adjustments_d1(dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_d1), + .l1_adjustments_q1(48'd0), + .l1_adjustments_we1(dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_we1), + .l2_filter_data_0_address0(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_address0), + .l2_filter_data_0_ce0(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_ce0), + .l2_filter_data_0_d0(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_d0), + .l2_filter_data_0_q0(l2_filter_data_0_q0), + .l2_filter_data_0_we0(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_we0), + .l2_filter_data_0_address1(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_address1), + .l2_filter_data_0_ce1(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_ce1), + .l2_filter_data_0_d1(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_d1), + .l2_filter_data_0_q1(l2_filter_data_0_q1), + .l2_filter_data_0_we1(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_we1), + .l2_filter_data_1_address0(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_address0), + .l2_filter_data_1_ce0(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_ce0), + .l2_filter_data_1_d0(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_d0), + .l2_filter_data_1_q0(l2_filter_data_1_q0), + .l2_filter_data_1_we0(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_we0), + .l2_filter_data_1_address1(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_address1), + .l2_filter_data_1_ce1(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_ce1), + .l2_filter_data_1_d1(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_d1), + .l2_filter_data_1_q1(l2_filter_data_1_q1), + .l2_filter_data_1_we1(dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP48232_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP48232_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP48232_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP48232_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP48232_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP48232_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP48232_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP48232_U0_out_data_we1), + .l2_adjustments_address0(dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_address0), + .l2_adjustments_ce0(dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_ce0), + .l2_adjustments_d0(dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_d0), + .l2_adjustments_q0(l2_adjustments_q0), + .l2_adjustments_we0(dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_we0), + .l2_adjustments_address1(dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_address1), + .l2_adjustments_ce1(dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_ce1), + .l2_adjustments_d1(dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_d1), + .l2_adjustments_q1(48'd0), + .l2_adjustments_we1(dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_we1), + .ap_start(dataflow_in_loop_TOP_LOOP48232_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP48232_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP48232_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP48232_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP48232_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP48232_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP48232_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 17'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP48232_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 17'd1); + end else if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP48232_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= 17'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 17'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48232_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP48232_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 17'd1); + end else if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48232_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP48232_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= 17'd0; + end + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48232_U0_ap_done == 1'b1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == 17'd0) & (ap_start == 1'b0) & (dataflow_in_loop_TOP_LOOP48232_U0_ap_idle == 1'b1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP48232_U0_ap_ready == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP48232_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP48232_U0_ap_continue = 1'b0; + end +end + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP48232_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP48232_U0_ap_ready; + +assign bound_minus_1 = (17'd100352 - 17'd1); + +assign dataflow_in_loop_TOP_LOOP48232_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP48232_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP48232_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP48232_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP48232_U0_start_write = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP48232_U0_in_data_address0; + +assign in_data_address1 = 14'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP48232_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP48232_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign l1_adjustments_address0 = dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_address0; + +assign l1_adjustments_address1 = 7'd0; + +assign l1_adjustments_ce0 = dataflow_in_loop_TOP_LOOP48232_U0_l1_adjustments_ce0; + +assign l1_adjustments_ce1 = 1'b0; + +assign l1_adjustments_d0 = 48'd0; + +assign l1_adjustments_d1 = 48'd0; + +assign l1_adjustments_we0 = 1'b0; + +assign l1_adjustments_we1 = 1'b0; + +assign l1_filter_data_0_address0 = dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_address0; + +assign l1_filter_data_0_address1 = 11'd0; + +assign l1_filter_data_0_ce0 = dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_0_ce0; + +assign l1_filter_data_0_ce1 = 1'b0; + +assign l1_filter_data_0_d0 = 64'd0; + +assign l1_filter_data_0_d1 = 64'd0; + +assign l1_filter_data_0_we0 = 1'b0; + +assign l1_filter_data_0_we1 = 1'b0; + +assign l1_filter_data_1_address0 = dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_address0; + +assign l1_filter_data_1_address1 = 11'd0; + +assign l1_filter_data_1_ce0 = dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_1_ce0; + +assign l1_filter_data_1_ce1 = 1'b0; + +assign l1_filter_data_1_d0 = 64'd0; + +assign l1_filter_data_1_d1 = 64'd0; + +assign l1_filter_data_1_we0 = 1'b0; + +assign l1_filter_data_1_we1 = 1'b0; + +assign l1_filter_data_2_address0 = dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_address0; + +assign l1_filter_data_2_address1 = 11'd0; + +assign l1_filter_data_2_ce0 = dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_2_ce0; + +assign l1_filter_data_2_ce1 = 1'b0; + +assign l1_filter_data_2_d0 = 64'd0; + +assign l1_filter_data_2_d1 = 64'd0; + +assign l1_filter_data_2_we0 = 1'b0; + +assign l1_filter_data_2_we1 = 1'b0; + +assign l1_filter_data_3_address0 = dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_address0; + +assign l1_filter_data_3_address1 = 11'd0; + +assign l1_filter_data_3_ce0 = dataflow_in_loop_TOP_LOOP48232_U0_l1_filter_data_3_ce0; + +assign l1_filter_data_3_ce1 = 1'b0; + +assign l1_filter_data_3_d0 = 64'd0; + +assign l1_filter_data_3_d1 = 64'd0; + +assign l1_filter_data_3_we0 = 1'b0; + +assign l1_filter_data_3_we1 = 1'b0; + +assign l2_adjustments_address0 = dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_address0; + +assign l2_adjustments_address1 = 4'd0; + +assign l2_adjustments_ce0 = dataflow_in_loop_TOP_LOOP48232_U0_l2_adjustments_ce0; + +assign l2_adjustments_ce1 = 1'b0; + +assign l2_adjustments_d0 = 48'd0; + +assign l2_adjustments_d1 = 48'd0; + +assign l2_adjustments_we0 = 1'b0; + +assign l2_adjustments_we1 = 1'b0; + +assign l2_filter_data_0_address0 = dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_address0; + +assign l2_filter_data_0_address1 = dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_address1; + +assign l2_filter_data_0_ce0 = dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_ce0; + +assign l2_filter_data_0_ce1 = dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_0_ce1; + +assign l2_filter_data_0_d0 = 16'd0; + +assign l2_filter_data_0_d1 = 16'd0; + +assign l2_filter_data_0_we0 = 1'b0; + +assign l2_filter_data_0_we1 = 1'b0; + +assign l2_filter_data_1_address0 = dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_address0; + +assign l2_filter_data_1_address1 = dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_address1; + +assign l2_filter_data_1_ce0 = dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_ce0; + +assign l2_filter_data_1_ce1 = dataflow_in_loop_TOP_LOOP48232_U0_l2_filter_data_1_ce1; + +assign l2_filter_data_1_d0 = 16'd0; + +assign l2_filter_data_1_d1 = 16'd0; + +assign l2_filter_data_1_we0 = 1'b0; + +assign l2_filter_data_1_we1 = 1'b0; + +assign out_data_address0 = 14'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP48232_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP48232_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP48232_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP48232_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP48232_U0_out_data_write; + +endmodule //td_fused_top_tdf4_111 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_in1_address0, + accum_in1_ce0, + accum_in1_q0, + accum_in1_address1, + accum_in1_ce1, + accum_in1_q1, + accum_in2_address0, + accum_in2_ce0, + accum_in2_q0, + accum_in2_address1, + accum_in2_ce1, + accum_in2_q1, + accum_in3_address0, + accum_in3_ce0, + accum_in3_q0, + accum_in3_address1, + accum_in3_ce1, + accum_in3_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_pp0_stage0 = 11'd2; +parameter ap_ST_fsm_pp0_stage1 = 11'd4; +parameter ap_ST_fsm_pp0_stage2 = 11'd8; +parameter ap_ST_fsm_pp0_stage3 = 11'd16; +parameter ap_ST_fsm_pp0_stage4 = 11'd32; +parameter ap_ST_fsm_pp0_stage5 = 11'd64; +parameter ap_ST_fsm_pp0_stage6 = 11'd128; +parameter ap_ST_fsm_state18 = 11'd256; +parameter ap_ST_fsm_pp1_stage0 = 11'd512; +parameter ap_ST_fsm_state21 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [5:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [5:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [5:0] accum_in1_address0; +output accum_in1_ce0; +input [15:0] accum_in1_q0; +output [5:0] accum_in1_address1; +output accum_in1_ce1; +input [15:0] accum_in1_q1; +output [5:0] accum_in2_address0; +output accum_in2_ce0; +input [15:0] accum_in2_q0; +output [5:0] accum_in2_address1; +output accum_in2_ce1; +input [15:0] accum_in2_q1; +output [5:0] accum_in3_address0; +output accum_in3_ce0; +input [15:0] accum_in3_q0; +output [5:0] accum_in3_address1; +output accum_in3_ce1; +input [15:0] accum_in3_q1; +output [4:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [4:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[5:0] accum_in_address0; +reg accum_in_ce0; +reg[5:0] accum_in_address1; +reg accum_in_ce1; +reg[5:0] accum_in1_address0; +reg accum_in1_ce0; +reg[5:0] accum_in1_address1; +reg accum_in1_ce1; +reg[5:0] accum_in2_address0; +reg accum_in2_ce0; +reg[5:0] accum_in2_address1; +reg accum_in2_ce1; +reg[5:0] accum_in3_address0; +reg accum_in3_ce0; +reg[5:0] accum_in3_address1; +reg accum_in3_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] x_reg_471; +reg [15:0] psum_4_05_reg_483; +reg [15:0] psum_3_04_reg_495; +reg [15:0] psum_2_03_reg_507; +reg [15:0] psum_1_02_reg_519; +reg [15:0] psum_0_01_reg_531; +reg [15:0] psum_9_010_reg_543; +reg [15:0] psum_8_09_reg_555; +reg [15:0] psum_7_08_reg_567; +reg [15:0] psum_6_07_reg_579; +reg [15:0] psum_5_06_reg_591; +reg [15:0] psum_31_032_reg_603; +reg [15:0] psum_30_031_reg_615; +reg [15:0] psum_29_030_reg_627; +reg [15:0] psum_28_029_reg_639; +reg [15:0] psum_27_028_reg_651; +reg [15:0] psum_26_027_reg_663; +reg [15:0] psum_25_026_reg_675; +reg [15:0] psum_24_025_reg_687; +reg [15:0] psum_23_024_reg_699; +reg [15:0] psum_22_023_reg_711; +reg [15:0] psum_21_022_reg_723; +reg [15:0] psum_20_021_reg_735; +reg [15:0] psum_19_020_reg_747; +reg [15:0] psum_18_019_reg_759; +reg [15:0] psum_17_018_reg_771; +reg [15:0] psum_16_017_reg_783; +reg [15:0] psum_15_016_reg_795; +reg [15:0] psum_14_015_reg_807; +reg [15:0] psum_13_014_reg_819; +reg [15:0] psum_12_013_reg_831; +reg [15:0] psum_11_012_reg_843; +reg [15:0] psum_10_011_reg_855; +reg [5:0] q_reg_867; +wire [0:0] icmp_ln132_fu_984_p2; +reg [0:0] icmp_ln132_reg_1838; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state9_pp0_stage0_iter1; +wire ap_block_state16_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln132_reg_1838_pp0_iter1_reg; +reg [0:0] icmp_ln132_reg_1838_pp0_iter2_reg; +wire [5:0] lshr_ln_fu_990_p4; +reg [5:0] lshr_ln_reg_1842; +reg [15:0] accum_in_load_reg_1888; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state10_pp0_stage1_iter1; +wire ap_block_state17_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in1_load_reg_1893; +reg [15:0] accum_in2_load_reg_1898; +reg [15:0] accum_in3_load_reg_1903; +reg [15:0] accum_in_load_29_reg_1908; +reg [15:0] accum_in1_load_15_reg_1913; +reg [15:0] accum_in2_load_8_reg_1918; +reg [15:0] accum_in3_load_8_reg_1923; +reg [15:0] accum_in_load_30_reg_1968; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state11_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in1_load_16_reg_1973; +reg [15:0] accum_in2_load_9_reg_1978; +reg [15:0] accum_in3_load_9_reg_1983; +reg [15:0] accum_in_load_31_reg_1988; +reg [15:0] accum_in1_load_17_reg_1993; +reg [15:0] accum_in2_load_10_reg_1998; +reg [15:0] accum_in3_load_10_reg_2003; +wire [0:0] icmp_ln136_fu_1054_p2; +reg [0:0] icmp_ln136_reg_2008; +wire [0:0] icmp_ln136_1_fu_1081_p2; +reg [0:0] icmp_ln136_1_reg_2018; +wire [0:0] icmp_ln136_2_fu_1108_p2; +reg [0:0] icmp_ln136_2_reg_2028; +wire [0:0] icmp_ln136_3_fu_1135_p2; +reg [0:0] icmp_ln136_3_reg_2038; +wire [0:0] icmp_ln136_4_fu_1162_p2; +reg [0:0] icmp_ln136_4_reg_2048; +wire [0:0] icmp_ln136_5_fu_1189_p2; +reg [0:0] icmp_ln136_5_reg_2058; +wire [0:0] icmp_ln136_6_fu_1216_p2; +reg [0:0] icmp_ln136_6_reg_2068; +wire [0:0] icmp_ln136_7_fu_1243_p2; +reg [0:0] icmp_ln136_7_reg_2078; +wire [15:0] select_ln136_fu_1264_p3; +reg [15:0] select_ln136_reg_2088; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state12_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +wire [15:0] select_ln136_1_fu_1271_p3; +reg [15:0] select_ln136_1_reg_2093; +wire [15:0] select_ln136_2_fu_1278_p3; +reg [15:0] select_ln136_2_reg_2098; +wire [15:0] select_ln136_3_fu_1285_p3; +reg [15:0] select_ln136_3_reg_2103; +wire [15:0] select_ln136_4_fu_1292_p3; +reg [15:0] select_ln136_4_reg_2108; +wire [15:0] select_ln136_5_fu_1299_p3; +reg [15:0] select_ln136_5_reg_2113; +wire [15:0] select_ln136_6_fu_1306_p3; +reg [15:0] select_ln136_6_reg_2118; +wire [15:0] select_ln136_7_fu_1313_p3; +reg [15:0] select_ln136_7_reg_2123; +wire [0:0] icmp_ln136_8_fu_1326_p2; +reg [0:0] icmp_ln136_8_reg_2128; +wire [0:0] icmp_ln136_9_fu_1353_p2; +reg [0:0] icmp_ln136_9_reg_2138; +wire [0:0] icmp_ln136_10_fu_1380_p2; +reg [0:0] icmp_ln136_10_reg_2148; +wire [0:0] icmp_ln136_11_fu_1407_p2; +reg [0:0] icmp_ln136_11_reg_2158; +wire [0:0] icmp_ln136_12_fu_1434_p2; +reg [0:0] icmp_ln136_12_reg_2168; +wire [0:0] icmp_ln136_13_fu_1461_p2; +reg [0:0] icmp_ln136_13_reg_2178; +wire [0:0] icmp_ln136_14_fu_1488_p2; +reg [0:0] icmp_ln136_14_reg_2188; +wire [0:0] icmp_ln136_15_fu_1515_p2; +reg [0:0] icmp_ln136_15_reg_2198; +wire [15:0] select_ln136_8_fu_1536_p3; +reg [15:0] select_ln136_8_reg_2208; +wire ap_CS_fsm_pp0_stage4; +wire ap_block_state6_pp0_stage4_iter0; +wire ap_block_state13_pp0_stage4_iter1; +wire ap_block_pp0_stage4_11001; +wire [15:0] select_ln136_9_fu_1543_p3; +reg [15:0] select_ln136_9_reg_2213; +wire [15:0] select_ln136_10_fu_1550_p3; +reg [15:0] select_ln136_10_reg_2218; +wire [15:0] select_ln136_11_fu_1557_p3; +reg [15:0] select_ln136_11_reg_2223; +wire [15:0] select_ln136_12_fu_1564_p3; +reg [15:0] select_ln136_12_reg_2228; +wire [15:0] select_ln136_13_fu_1571_p3; +reg [15:0] select_ln136_13_reg_2233; +wire [15:0] select_ln136_14_fu_1578_p3; +reg [15:0] select_ln136_14_reg_2238; +wire [15:0] select_ln136_15_fu_1585_p3; +reg [15:0] select_ln136_15_reg_2243; +wire [7:0] add_ln132_fu_1592_p2; +reg [7:0] add_ln132_reg_2248; +wire ap_CS_fsm_pp0_stage6; +wire ap_block_state8_pp0_stage6_iter0; +wire ap_block_state15_pp0_stage6_iter1; +wire ap_block_pp0_stage6_11001; +wire [15:0] grp_fu_932_p2; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_937_p2; +wire [15:0] grp_fu_942_p2; +wire [15:0] grp_fu_947_p2; +wire [15:0] grp_fu_952_p2; +wire ap_CS_fsm_pp0_stage5; +wire ap_block_state7_pp0_stage5_iter0; +wire ap_block_state14_pp0_stage5_iter1; +wire ap_block_pp0_stage5_11001; +reg ap_enable_reg_pp0_iter2; +wire [0:0] tmp_fu_1598_p3; +reg [0:0] tmp_reg_2413; +wire ap_CS_fsm_pp1_stage0; +wire ap_block_state19_pp1_stage0_iter0; +wire ap_block_state20_pp1_stage0_iter1; +wire ap_block_pp1_stage0_11001; +wire [4:0] trunc_ln140_fu_1611_p1; +wire [5:0] add_ln140_fu_1615_p2; +reg ap_enable_reg_pp1_iter0; +wire [4:0] or_ln140_fu_1621_p2; +reg [4:0] or_ln140_reg_2426; +wire [15:0] select_ln152_25_fu_1787_p3; +reg [15:0] select_ln152_25_reg_2434; +reg ap_block_state1; +wire ap_block_pp0_stage4_subdone; +reg ap_condition_pp0_exit_iter0_state6; +wire ap_block_pp0_stage6_subdone; +wire ap_block_pp0_stage1_subdone; +wire ap_CS_fsm_state18; +wire ap_block_pp1_stage0_subdone; +reg ap_condition_pp1_exit_iter0_state19; +reg ap_enable_reg_pp1_iter1; +reg [7:0] ap_phi_mux_x_phi_fu_475_p4; +wire ap_block_pp0_stage0; +wire ap_block_pp0_stage2; +wire [15:0] ap_phi_mux_psum_9_010_phi_fu_547_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_8_09_phi_fu_559_p4; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_571_p4; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_583_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_595_p4; +wire [15:0] ap_phi_mux_psum_31_032_phi_fu_607_p4; +wire ap_block_pp0_stage1; +wire [15:0] ap_phi_mux_psum_30_031_phi_fu_619_p4; +wire [15:0] ap_phi_mux_psum_29_030_phi_fu_631_p4; +wire [15:0] ap_phi_mux_psum_28_029_phi_fu_643_p4; +wire [15:0] ap_phi_mux_psum_27_028_phi_fu_655_p4; +wire [15:0] ap_phi_mux_psum_26_027_phi_fu_667_p4; +wire [15:0] ap_phi_mux_psum_25_026_phi_fu_679_p4; +wire [15:0] ap_phi_mux_psum_24_025_phi_fu_691_p4; +wire ap_block_pp0_stage6; +wire [15:0] ap_phi_mux_psum_23_024_phi_fu_703_p4; +wire [15:0] ap_phi_mux_psum_22_023_phi_fu_715_p4; +wire [15:0] ap_phi_mux_psum_21_022_phi_fu_727_p4; +wire [15:0] ap_phi_mux_psum_20_021_phi_fu_739_p4; +wire [15:0] ap_phi_mux_psum_19_020_phi_fu_751_p4; +wire ap_block_pp0_stage5; +wire [15:0] ap_phi_mux_psum_18_019_phi_fu_763_p4; +wire [15:0] ap_phi_mux_psum_17_018_phi_fu_775_p4; +wire [15:0] ap_phi_mux_psum_16_017_phi_fu_787_p4; +wire [15:0] ap_phi_mux_psum_15_016_phi_fu_799_p4; +wire [15:0] ap_phi_mux_psum_14_015_phi_fu_811_p4; +wire ap_block_pp0_stage4; +wire [15:0] ap_phi_mux_psum_13_014_phi_fu_823_p4; +wire [15:0] ap_phi_mux_psum_12_013_phi_fu_835_p4; +wire [15:0] ap_phi_mux_psum_11_012_phi_fu_847_p4; +wire [15:0] ap_phi_mux_psum_10_011_phi_fu_859_p4; +reg [15:0] ap_phi_mux_phi_ln152_phi_fu_881_p32; +wire [15:0] ap_phi_reg_pp1_iter0_phi_ln152_reg_878; +wire [63:0] zext_ln136_fu_1000_p1; +wire [63:0] zext_ln136_8_fu_1014_p1; +wire [63:0] zext_ln136_9_fu_1027_p1; +wire [63:0] zext_ln136_10_fu_1040_p1; +wire [63:0] zext_ln136_11_fu_1070_p1; +wire [63:0] zext_ln136_12_fu_1097_p1; +wire [63:0] zext_ln136_13_fu_1124_p1; +wire [63:0] zext_ln136_14_fu_1151_p1; +wire [63:0] zext_ln136_15_fu_1178_p1; +wire [63:0] zext_ln136_16_fu_1205_p1; +wire [63:0] zext_ln136_17_fu_1232_p1; +wire [63:0] zext_ln136_18_fu_1259_p1; +wire [63:0] zext_ln136_19_fu_1342_p1; +wire [63:0] zext_ln136_20_fu_1369_p1; +wire [63:0] zext_ln136_21_fu_1396_p1; +wire [63:0] zext_ln136_22_fu_1423_p1; +wire [63:0] zext_ln136_23_fu_1450_p1; +wire [63:0] zext_ln136_24_fu_1477_p1; +wire [63:0] zext_ln136_25_fu_1504_p1; +wire [63:0] zext_ln136_26_fu_1531_p1; +wire [63:0] zext_ln140_fu_1606_p1; +wire ap_block_pp1_stage0; +wire [63:0] zext_ln140_2_fu_1795_p1; +reg [15:0] grp_fu_932_p0; +reg [15:0] grp_fu_932_p1; +reg [15:0] grp_fu_937_p0; +reg [15:0] grp_fu_937_p1; +reg [15:0] grp_fu_942_p0; +reg [15:0] grp_fu_942_p1; +reg [15:0] grp_fu_947_p0; +reg [15:0] grp_fu_947_p1; +reg [15:0] grp_fu_952_p0; +reg [15:0] grp_fu_952_p1; +wire [5:0] or_ln136_fu_1008_p2; +wire [5:0] or_ln136_7_fu_1022_p2; +wire [5:0] or_ln136_8_fu_1035_p2; +wire [7:0] or_ln136_9_fu_1048_p2; +wire [5:0] lshr_ln136_1_fu_1060_p4; +wire [7:0] or_ln136_10_fu_1075_p2; +wire [5:0] lshr_ln136_2_fu_1087_p4; +wire [7:0] or_ln136_11_fu_1102_p2; +wire [5:0] lshr_ln136_3_fu_1114_p4; +wire [7:0] or_ln136_12_fu_1129_p2; +wire [5:0] lshr_ln136_4_fu_1141_p4; +wire [7:0] or_ln136_13_fu_1156_p2; +wire [5:0] lshr_ln136_5_fu_1168_p4; +wire [7:0] or_ln136_14_fu_1183_p2; +wire [5:0] lshr_ln136_6_fu_1195_p4; +wire [7:0] or_ln136_15_fu_1210_p2; +wire [5:0] lshr_ln136_7_fu_1222_p4; +wire [7:0] or_ln136_16_fu_1237_p2; +wire [5:0] lshr_ln136_8_fu_1249_p4; +wire [7:0] or_ln136_17_fu_1320_p2; +wire [5:0] lshr_ln136_9_fu_1332_p4; +wire [7:0] or_ln136_18_fu_1347_p2; +wire [5:0] lshr_ln136_s_fu_1359_p4; +wire [7:0] or_ln136_19_fu_1374_p2; +wire [5:0] lshr_ln136_10_fu_1386_p4; +wire [7:0] or_ln136_20_fu_1401_p2; +wire [5:0] lshr_ln136_11_fu_1413_p4; +wire [7:0] or_ln136_21_fu_1428_p2; +wire [5:0] lshr_ln136_12_fu_1440_p4; +wire [7:0] or_ln136_22_fu_1455_p2; +wire [5:0] lshr_ln136_13_fu_1467_p4; +wire [7:0] or_ln136_23_fu_1482_p2; +wire [5:0] lshr_ln136_14_fu_1494_p4; +wire [7:0] or_ln136_24_fu_1509_p2; +wire [5:0] lshr_ln136_15_fu_1521_p4; +wire [0:0] icmp_ln152_fu_1627_p2; +wire [0:0] icmp_ln152_15_fu_1641_p2; +wire [15:0] select_ln152_fu_1633_p3; +wire [0:0] icmp_ln152_16_fu_1655_p2; +wire [15:0] select_ln152_15_fu_1647_p3; +wire [0:0] icmp_ln152_17_fu_1669_p2; +wire [15:0] select_ln152_16_fu_1661_p3; +wire [0:0] icmp_ln152_18_fu_1683_p2; +wire [15:0] select_ln152_17_fu_1675_p3; +wire [0:0] icmp_ln152_19_fu_1697_p2; +wire [15:0] select_ln152_18_fu_1689_p3; +wire [0:0] icmp_ln152_20_fu_1711_p2; +wire [15:0] select_ln152_19_fu_1703_p3; +wire [0:0] icmp_ln152_21_fu_1725_p2; +wire [15:0] select_ln152_20_fu_1717_p3; +wire [0:0] icmp_ln152_22_fu_1739_p2; +wire [15:0] select_ln152_21_fu_1731_p3; +wire [0:0] icmp_ln152_23_fu_1753_p2; +wire [15:0] select_ln152_22_fu_1745_p3; +wire [0:0] icmp_ln152_24_fu_1767_p2; +wire [15:0] select_ln152_23_fu_1759_p3; +wire [0:0] icmp_ln152_25_fu_1781_p2; +wire [15:0] select_ln152_24_fu_1773_p3; +wire [0:0] icmp_ln152_26_fu_1799_p2; +wire [0:0] icmp_ln152_27_fu_1811_p2; +wire [15:0] select_ln152_26_fu_1804_p3; +wire [0:0] icmp_ln152_28_fu_1824_p2; +wire [15:0] select_ln152_27_fu_1816_p3; +wire ap_CS_fsm_state21; +reg [10:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +wire ap_block_pp0_stage2_subdone; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage5_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_idle_pp1; +wire ap_enable_pp1; +reg ap_condition_1463; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp1_iter0 = 1'b0; +#0 ap_enable_reg_pp1_iter1 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U528( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_932_p0), + .din1(grp_fu_932_p1), + .dout(grp_fu_932_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U529( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_937_p0), + .din1(grp_fu_937_p1), + .dout(grp_fu_937_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U530( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_942_p0), + .din1(grp_fu_942_p1), + .dout(grp_fu_942_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U531( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_947_p0), + .din1(grp_fu_947_p1), + .dout(grp_fu_947_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U532( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_952_p0), + .din1(grp_fu_952_p1), + .dout(grp_fu_952_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state21)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state6) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6_subdone))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone)) | ((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6_subdone)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp1_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp1_exit_iter0_state19) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_subdone))) begin + ap_enable_reg_pp1_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state18)) begin + ap_enable_reg_pp1_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp1_iter1 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp1_exit_iter0_state19) & (1'b0 == ap_block_pp1_stage0_subdone))) begin + ap_enable_reg_pp1_iter1 <= (1'b1 ^ ap_condition_pp1_exit_iter0_state19); + end else if ((1'b0 == ap_block_pp1_stage0_subdone)) begin + ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0; + end else if ((1'b1 == ap_CS_fsm_state18)) begin + ap_enable_reg_pp1_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state18)) begin + q_reg_867 <= 6'd0; + end else if (((ap_enable_reg_pp1_iter0 == 1'b1) & (tmp_fu_1598_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + q_reg_867 <= add_ln140_fu_1615_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln132_reg_1838 == 1'd1))) begin + x_reg_471 <= add_ln132_reg_2248; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_471 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln132_reg_1838 == 1'd1))) begin + accum_in1_load_15_reg_1913 <= accum_in1_q0; + accum_in1_load_reg_1893 <= accum_in1_q1; + accum_in2_load_8_reg_1918 <= accum_in2_q0; + accum_in2_load_reg_1898 <= accum_in2_q1; + accum_in3_load_8_reg_1923 <= accum_in3_q0; + accum_in3_load_reg_1903 <= accum_in3_q1; + accum_in_load_29_reg_1908 <= accum_in_q0; + accum_in_load_reg_1888 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (icmp_ln132_reg_1838 == 1'd1))) begin + accum_in1_load_16_reg_1973 <= accum_in1_q1; + accum_in1_load_17_reg_1993 <= accum_in1_q0; + accum_in2_load_10_reg_1998 <= accum_in2_q0; + accum_in2_load_9_reg_1978 <= accum_in2_q1; + accum_in3_load_10_reg_2003 <= accum_in3_q0; + accum_in3_load_9_reg_1983 <= accum_in3_q1; + accum_in_load_30_reg_1968 <= accum_in_q1; + accum_in_load_31_reg_1988 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6_11001) & (icmp_ln132_reg_1838 == 1'd1))) begin + add_ln132_reg_2248 <= add_ln132_fu_1592_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln132_reg_1838 <= icmp_ln132_fu_984_p2; + icmp_ln132_reg_1838_pp0_iter1_reg <= icmp_ln132_reg_1838; + icmp_ln132_reg_1838_pp0_iter2_reg <= icmp_ln132_reg_1838_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3_11001) & (icmp_ln132_reg_1838 == 1'd1))) begin + icmp_ln136_10_reg_2148 <= icmp_ln136_10_fu_1380_p2; + icmp_ln136_11_reg_2158 <= icmp_ln136_11_fu_1407_p2; + icmp_ln136_12_reg_2168 <= icmp_ln136_12_fu_1434_p2; + icmp_ln136_13_reg_2178 <= icmp_ln136_13_fu_1461_p2; + icmp_ln136_14_reg_2188 <= icmp_ln136_14_fu_1488_p2; + icmp_ln136_15_reg_2198 <= icmp_ln136_15_fu_1515_p2; + icmp_ln136_8_reg_2128 <= icmp_ln136_8_fu_1326_p2; + icmp_ln136_9_reg_2138 <= icmp_ln136_9_fu_1353_p2; + select_ln136_1_reg_2093 <= select_ln136_1_fu_1271_p3; + select_ln136_2_reg_2098 <= select_ln136_2_fu_1278_p3; + select_ln136_3_reg_2103 <= select_ln136_3_fu_1285_p3; + select_ln136_4_reg_2108 <= select_ln136_4_fu_1292_p3; + select_ln136_5_reg_2113 <= select_ln136_5_fu_1299_p3; + select_ln136_6_reg_2118 <= select_ln136_6_fu_1306_p3; + select_ln136_7_reg_2123 <= select_ln136_7_fu_1313_p3; + select_ln136_reg_2088 <= select_ln136_fu_1264_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2_11001) & (icmp_ln132_reg_1838 == 1'd1))) begin + icmp_ln136_1_reg_2018 <= icmp_ln136_1_fu_1081_p2; + icmp_ln136_2_reg_2028 <= icmp_ln136_2_fu_1108_p2; + icmp_ln136_3_reg_2038 <= icmp_ln136_3_fu_1135_p2; + icmp_ln136_4_reg_2048 <= icmp_ln136_4_fu_1162_p2; + icmp_ln136_5_reg_2058 <= icmp_ln136_5_fu_1189_p2; + icmp_ln136_6_reg_2068 <= icmp_ln136_6_fu_1216_p2; + icmp_ln136_7_reg_2078 <= icmp_ln136_7_fu_1243_p2; + icmp_ln136_reg_2008 <= icmp_ln136_fu_1054_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln132_fu_984_p2 == 1'd1))) begin + lshr_ln_reg_1842 <= {{ap_phi_mux_x_phi_fu_475_p4[7:2]}}; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_fu_1598_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + or_ln140_reg_2426[4 : 1] <= or_ln140_fu_1621_p2[4 : 1]; + select_ln152_25_reg_2434 <= select_ln152_25_fu_1787_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (icmp_ln132_reg_1838_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage2_11001))) begin + psum_0_01_reg_531 <= grp_fu_932_p2; + psum_1_02_reg_519 <= grp_fu_937_p2; + psum_2_03_reg_507 <= grp_fu_942_p2; + psum_3_04_reg_495 <= grp_fu_947_p2; + psum_4_05_reg_483 <= grp_fu_952_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (icmp_ln132_reg_1838_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage4_11001))) begin + psum_10_011_reg_855 <= grp_fu_932_p2; + psum_11_012_reg_843 <= grp_fu_937_p2; + psum_12_013_reg_831 <= grp_fu_942_p2; + psum_13_014_reg_819 <= grp_fu_947_p2; + psum_14_015_reg_807 <= grp_fu_952_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (icmp_ln132_reg_1838_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage5_11001))) begin + psum_15_016_reg_795 <= grp_fu_932_p2; + psum_16_017_reg_783 <= grp_fu_937_p2; + psum_17_018_reg_771 <= grp_fu_942_p2; + psum_18_019_reg_759 <= grp_fu_947_p2; + psum_19_020_reg_747 <= grp_fu_952_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage6) & (icmp_ln132_reg_1838_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage6_11001))) begin + psum_20_021_reg_735 <= grp_fu_932_p2; + psum_21_022_reg_723 <= grp_fu_937_p2; + psum_22_023_reg_711 <= grp_fu_942_p2; + psum_23_024_reg_699 <= grp_fu_947_p2; + psum_24_025_reg_687 <= grp_fu_952_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln132_reg_1838_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + psum_25_026_reg_675 <= grp_fu_932_p2; + psum_26_027_reg_663 <= grp_fu_937_p2; + psum_27_028_reg_651 <= grp_fu_942_p2; + psum_28_029_reg_639 <= grp_fu_947_p2; + psum_29_030_reg_627 <= grp_fu_952_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln132_reg_1838_pp0_iter2_reg == 1'd1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + psum_30_031_reg_615 <= grp_fu_932_p2; + psum_31_032_reg_603 <= grp_fu_937_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (icmp_ln132_reg_1838_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + psum_5_06_reg_591 <= grp_fu_932_p2; + psum_6_07_reg_579 <= grp_fu_937_p2; + psum_7_08_reg_567 <= grp_fu_942_p2; + psum_8_09_reg_555 <= grp_fu_947_p2; + psum_9_010_reg_543 <= grp_fu_952_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4_11001) & (icmp_ln132_reg_1838 == 1'd1))) begin + select_ln136_10_reg_2218 <= select_ln136_10_fu_1550_p3; + select_ln136_11_reg_2223 <= select_ln136_11_fu_1557_p3; + select_ln136_12_reg_2228 <= select_ln136_12_fu_1564_p3; + select_ln136_13_reg_2233 <= select_ln136_13_fu_1571_p3; + select_ln136_14_reg_2238 <= select_ln136_14_fu_1578_p3; + select_ln136_15_reg_2243 <= select_ln136_15_fu_1585_p3; + select_ln136_8_reg_2208 <= select_ln136_8_fu_1536_p3; + select_ln136_9_reg_2213 <= select_ln136_9_fu_1543_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + tmp_reg_2413 <= q_reg_867[32'd5]; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in1_address0 = zext_ln136_24_fu_1477_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in1_address0 = zext_ln136_16_fu_1205_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in1_address0 = zext_ln136_10_fu_1040_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in1_address0 = zext_ln136_8_fu_1014_p1; + end else begin + accum_in1_address0 = 'bx; + end + end else begin + accum_in1_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in1_address1 = zext_ln136_20_fu_1369_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in1_address1 = zext_ln136_12_fu_1097_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in1_address1 = zext_ln136_9_fu_1027_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in1_address1 = zext_ln136_fu_1000_p1; + end else begin + accum_in1_address1 = 'bx; + end + end else begin + accum_in1_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in1_ce0 = 1'b1; + end else begin + accum_in1_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in1_ce1 = 1'b1; + end else begin + accum_in1_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in2_address0 = zext_ln136_25_fu_1504_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in2_address0 = zext_ln136_17_fu_1232_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in2_address0 = zext_ln136_10_fu_1040_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in2_address0 = zext_ln136_8_fu_1014_p1; + end else begin + accum_in2_address0 = 'bx; + end + end else begin + accum_in2_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in2_address1 = zext_ln136_21_fu_1396_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in2_address1 = zext_ln136_13_fu_1124_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in2_address1 = zext_ln136_9_fu_1027_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in2_address1 = zext_ln136_fu_1000_p1; + end else begin + accum_in2_address1 = 'bx; + end + end else begin + accum_in2_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in2_ce0 = 1'b1; + end else begin + accum_in2_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in2_ce1 = 1'b1; + end else begin + accum_in2_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in3_address0 = zext_ln136_26_fu_1531_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in3_address0 = zext_ln136_18_fu_1259_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in3_address0 = zext_ln136_10_fu_1040_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in3_address0 = zext_ln136_8_fu_1014_p1; + end else begin + accum_in3_address0 = 'bx; + end + end else begin + accum_in3_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in3_address1 = zext_ln136_22_fu_1423_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in3_address1 = zext_ln136_14_fu_1151_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in3_address1 = zext_ln136_9_fu_1027_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in3_address1 = zext_ln136_fu_1000_p1; + end else begin + accum_in3_address1 = 'bx; + end + end else begin + accum_in3_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in3_ce0 = 1'b1; + end else begin + accum_in3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in3_ce1 = 1'b1; + end else begin + accum_in3_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in_address0 = zext_ln136_23_fu_1450_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in_address0 = zext_ln136_15_fu_1178_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in_address0 = zext_ln136_10_fu_1040_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in_address0 = zext_ln136_8_fu_1014_p1; + end else begin + accum_in_address0 = 'bx; + end + end else begin + accum_in_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in_address1 = zext_ln136_19_fu_1342_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in_address1 = zext_ln136_11_fu_1070_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in_address1 = zext_ln136_9_fu_1027_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in_address1 = zext_ln136_fu_1000_p1; + end else begin + accum_in_address1 = 'bx; + end + end else begin + accum_in_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp1_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp1_iter1 == 1'b1) & (tmp_reg_2413 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp1_iter0 == 1'b1) & (tmp_fu_1598_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln132_reg_1838 == 1'd0)) begin + ap_condition_pp0_exit_iter0_state6 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state6 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_fu_1598_p3 == 1'd1)) begin + ap_condition_pp1_exit_iter0_state19 = 1'b1; + end else begin + ap_condition_pp1_exit_iter0_state19 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state21)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b0))) begin + ap_idle_pp1 = 1'b1; + end else begin + ap_idle_pp1 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_fu_1598_p3 == 1'd0)) begin + if ((trunc_ln140_fu_1611_p1 == 5'd0)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_0_01_reg_531; + end else if ((1'b1 == ap_condition_1463)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_30_031_reg_615; + end else if ((trunc_ln140_fu_1611_p1 == 5'd28)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_28_029_reg_639; + end else if ((trunc_ln140_fu_1611_p1 == 5'd26)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_26_027_reg_663; + end else if ((trunc_ln140_fu_1611_p1 == 5'd24)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_24_025_reg_687; + end else if ((trunc_ln140_fu_1611_p1 == 5'd22)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_22_023_reg_711; + end else if ((trunc_ln140_fu_1611_p1 == 5'd20)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_20_021_reg_735; + end else if ((trunc_ln140_fu_1611_p1 == 5'd18)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_18_019_reg_759; + end else if ((trunc_ln140_fu_1611_p1 == 5'd16)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_16_017_reg_783; + end else if ((trunc_ln140_fu_1611_p1 == 5'd14)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_14_015_reg_807; + end else if ((trunc_ln140_fu_1611_p1 == 5'd12)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_12_013_reg_831; + end else if ((trunc_ln140_fu_1611_p1 == 5'd10)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_10_011_reg_855; + end else if ((trunc_ln140_fu_1611_p1 == 5'd8)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_8_09_reg_555; + end else if ((trunc_ln140_fu_1611_p1 == 5'd6)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_6_07_reg_579; + end else if ((trunc_ln140_fu_1611_p1 == 5'd4)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_4_05_reg_483; + end else if ((trunc_ln140_fu_1611_p1 == 5'd2)) begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = psum_2_03_reg_507; + end else begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = ap_phi_reg_pp1_iter0_phi_ln152_reg_878; + end + end else begin + ap_phi_mux_phi_ln152_phi_fu_881_p32 = ap_phi_reg_pp1_iter0_phi_ln152_reg_878; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0) & (icmp_ln132_reg_1838 == 1'd1))) begin + ap_phi_mux_x_phi_fu_475_p4 = add_ln132_reg_2248; + end else begin + ap_phi_mux_x_phi_fu_475_p4 = x_reg_471; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state21)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + grp_fu_932_p0 = ap_phi_mux_psum_30_031_phi_fu_619_p4; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_932_p0 = ap_phi_mux_psum_25_026_phi_fu_679_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_932_p0 = ap_phi_mux_psum_20_021_phi_fu_739_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_932_p0 = ap_phi_mux_psum_15_016_phi_fu_799_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_932_p0 = ap_phi_mux_psum_10_011_phi_fu_859_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_932_p0 = ap_phi_mux_psum_5_06_phi_fu_595_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_932_p0 = grp_fu_932_p2; + end else begin + grp_fu_932_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + grp_fu_932_p1 = select_ln136_14_reg_2238; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_932_p1 = select_ln136_9_reg_2213; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_932_p1 = select_ln136_4_reg_2108; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_932_p1 = accum_in3_load_10_reg_2003; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_932_p1 = accum_in2_load_9_reg_1978; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_932_p1 = accum_in1_load_15_reg_1913; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_932_p1 = accum_in_load_reg_1888; + end else begin + grp_fu_932_p1 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + grp_fu_937_p0 = ap_phi_mux_psum_31_032_phi_fu_607_p4; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_937_p0 = ap_phi_mux_psum_26_027_phi_fu_667_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_937_p0 = ap_phi_mux_psum_21_022_phi_fu_727_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_937_p0 = ap_phi_mux_psum_16_017_phi_fu_787_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_937_p0 = ap_phi_mux_psum_11_012_phi_fu_847_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_937_p0 = ap_phi_mux_psum_6_07_phi_fu_583_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_937_p0 = grp_fu_937_p2; + end else begin + grp_fu_937_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + grp_fu_937_p1 = select_ln136_15_reg_2243; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_937_p1 = select_ln136_10_reg_2218; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_937_p1 = select_ln136_5_reg_2113; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_937_p1 = select_ln136_reg_2088; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_937_p1 = accum_in3_load_9_reg_1983; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_937_p1 = accum_in2_load_8_reg_1918; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_937_p1 = accum_in1_load_reg_1893; + end else begin + grp_fu_937_p1 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_942_p0 = ap_phi_mux_psum_27_028_phi_fu_655_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_942_p0 = ap_phi_mux_psum_22_023_phi_fu_715_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_942_p0 = ap_phi_mux_psum_17_018_phi_fu_775_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_942_p0 = ap_phi_mux_psum_12_013_phi_fu_835_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_942_p0 = ap_phi_mux_psum_7_08_phi_fu_571_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_942_p0 = grp_fu_942_p2; + end else begin + grp_fu_942_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_942_p1 = select_ln136_11_reg_2223; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_942_p1 = select_ln136_6_reg_2118; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_942_p1 = select_ln136_1_reg_2093; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_942_p1 = accum_in_load_31_reg_1988; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_942_p1 = accum_in3_load_8_reg_1923; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_942_p1 = accum_in2_load_reg_1898; + end else begin + grp_fu_942_p1 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_947_p0 = ap_phi_mux_psum_28_029_phi_fu_643_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_947_p0 = ap_phi_mux_psum_23_024_phi_fu_703_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_947_p0 = ap_phi_mux_psum_18_019_phi_fu_763_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_947_p0 = ap_phi_mux_psum_13_014_phi_fu_823_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_947_p0 = ap_phi_mux_psum_8_09_phi_fu_559_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_947_p0 = grp_fu_947_p2; + end else begin + grp_fu_947_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_947_p1 = select_ln136_12_reg_2228; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_947_p1 = select_ln136_7_reg_2123; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_947_p1 = select_ln136_2_reg_2098; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_947_p1 = accum_in1_load_17_reg_1993; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_947_p1 = accum_in_load_30_reg_1968; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_947_p1 = accum_in3_load_reg_1903; + end else begin + grp_fu_947_p1 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_952_p0 = ap_phi_mux_psum_29_030_phi_fu_631_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_952_p0 = ap_phi_mux_psum_24_025_phi_fu_691_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_952_p0 = ap_phi_mux_psum_19_020_phi_fu_751_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_952_p0 = ap_phi_mux_psum_14_015_phi_fu_811_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_952_p0 = ap_phi_mux_psum_9_010_phi_fu_547_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_952_p0 = grp_fu_952_p2; + end else begin + grp_fu_952_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_952_p1 = select_ln136_13_reg_2233; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_952_p1 = select_ln136_8_reg_2208; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_952_p1 = select_ln136_3_reg_2103; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_952_p1 = accum_in2_load_10_reg_1998; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_952_p1 = accum_in1_load_16_reg_1973; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_952_p1 = accum_in_load_29_reg_1908; + end else begin + grp_fu_952_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state18; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((1'b0 == ap_block_pp0_stage2_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_pp0_stage4 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4_subdone) & (icmp_ln132_reg_1838 == 1'd0)) & (1'b0 == ap_block_pp0_stage4_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end else if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4_subdone) & (icmp_ln132_reg_1838 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state18; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end + end + ap_ST_fsm_pp0_stage5 : begin + if ((1'b0 == ap_block_pp0_stage5_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end + end + ap_ST_fsm_pp0_stage6 : begin + if ((1'b0 == ap_block_pp0_stage6_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end + end + ap_ST_fsm_state18 : begin + ap_NS_fsm = ap_ST_fsm_pp1_stage0; + end + ap_ST_fsm_pp1_stage0 : begin + if (~((ap_enable_reg_pp1_iter0 == 1'b1) & (tmp_fu_1598_p3 == 1'd1) & (1'b0 == ap_block_pp1_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp1_stage0; + end else if (((ap_enable_reg_pp1_iter0 == 1'b1) & (tmp_fu_1598_p3 == 1'd1) & (1'b0 == ap_block_pp1_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state21; + end else begin + ap_NS_fsm = ap_ST_fsm_pp1_stage0; + end + end + ap_ST_fsm_state21 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln140_2_fu_1795_p1; + +assign accum_out_address1 = zext_ln140_fu_1606_p1; + +assign accum_out_d0 = ((icmp_ln152_28_fu_1824_p2[0:0] == 1'b1) ? psum_29_030_reg_627 : select_ln152_27_fu_1816_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln152_phi_fu_881_p32; + +assign add_ln132_fu_1592_p2 = (x_reg_471 + 8'd32); + +assign add_ln140_fu_1615_p2 = (q_reg_867 + 6'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_pp1_stage0 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state18 = ap_CS_fsm[32'd8]; + +assign ap_CS_fsm_state21 = ap_CS_fsm[32'd10]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp1_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp1_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp1_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage4_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage5_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage6_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp1_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp1_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_1463 = (~(trunc_ln140_fu_1611_p1 == 5'd0) & ~(trunc_ln140_fu_1611_p1 == 5'd28) & ~(trunc_ln140_fu_1611_p1 == 5'd26) & ~(trunc_ln140_fu_1611_p1 == 5'd24) & ~(trunc_ln140_fu_1611_p1 == 5'd22) & ~(trunc_ln140_fu_1611_p1 == 5'd20) & ~(trunc_ln140_fu_1611_p1 == 5'd18) & ~(trunc_ln140_fu_1611_p1 == 5'd16) & ~(trunc_ln140_fu_1611_p1 == 5'd14) & ~(trunc_ln140_fu_1611_p1 == 5'd12) & ~(trunc_ln140_fu_1611_p1 == 5'd10) & ~(trunc_ln140_fu_1611_p1 == 5'd8) & ~(trunc_ln140_fu_1611_p1 == 5'd6) & ~(trunc_ln140_fu_1611_p1 == 5'd4) & ~(trunc_ln140_fu_1611_p1 == 5'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_enable_pp1 = (ap_idle_pp1 ^ 1'b1); + +assign ap_phi_mux_psum_10_011_phi_fu_859_p4 = grp_fu_932_p2; + +assign ap_phi_mux_psum_11_012_phi_fu_847_p4 = grp_fu_937_p2; + +assign ap_phi_mux_psum_12_013_phi_fu_835_p4 = grp_fu_942_p2; + +assign ap_phi_mux_psum_13_014_phi_fu_823_p4 = grp_fu_947_p2; + +assign ap_phi_mux_psum_14_015_phi_fu_811_p4 = grp_fu_952_p2; + +assign ap_phi_mux_psum_15_016_phi_fu_799_p4 = grp_fu_932_p2; + +assign ap_phi_mux_psum_16_017_phi_fu_787_p4 = grp_fu_937_p2; + +assign ap_phi_mux_psum_17_018_phi_fu_775_p4 = grp_fu_942_p2; + +assign ap_phi_mux_psum_18_019_phi_fu_763_p4 = grp_fu_947_p2; + +assign ap_phi_mux_psum_19_020_phi_fu_751_p4 = grp_fu_952_p2; + +assign ap_phi_mux_psum_20_021_phi_fu_739_p4 = grp_fu_932_p2; + +assign ap_phi_mux_psum_21_022_phi_fu_727_p4 = grp_fu_937_p2; + +assign ap_phi_mux_psum_22_023_phi_fu_715_p4 = grp_fu_942_p2; + +assign ap_phi_mux_psum_23_024_phi_fu_703_p4 = grp_fu_947_p2; + +assign ap_phi_mux_psum_24_025_phi_fu_691_p4 = grp_fu_952_p2; + +assign ap_phi_mux_psum_25_026_phi_fu_679_p4 = grp_fu_932_p2; + +assign ap_phi_mux_psum_26_027_phi_fu_667_p4 = grp_fu_937_p2; + +assign ap_phi_mux_psum_27_028_phi_fu_655_p4 = grp_fu_942_p2; + +assign ap_phi_mux_psum_28_029_phi_fu_643_p4 = grp_fu_947_p2; + +assign ap_phi_mux_psum_29_030_phi_fu_631_p4 = grp_fu_952_p2; + +assign ap_phi_mux_psum_30_031_phi_fu_619_p4 = grp_fu_932_p2; + +assign ap_phi_mux_psum_31_032_phi_fu_607_p4 = grp_fu_937_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_595_p4 = grp_fu_932_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_583_p4 = grp_fu_937_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_571_p4 = grp_fu_942_p2; + +assign ap_phi_mux_psum_8_09_phi_fu_559_p4 = grp_fu_947_p2; + +assign ap_phi_mux_psum_9_010_phi_fu_547_p4 = grp_fu_952_p2; + +assign ap_phi_reg_pp1_iter0_phi_ln152_reg_878 = 'bx; + +assign icmp_ln132_fu_984_p2 = ((ap_phi_mux_x_phi_fu_475_p4 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_10_fu_1380_p2 = ((or_ln136_19_fu_1374_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_11_fu_1407_p2 = ((or_ln136_20_fu_1401_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_12_fu_1434_p2 = ((or_ln136_21_fu_1428_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_13_fu_1461_p2 = ((or_ln136_22_fu_1455_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_14_fu_1488_p2 = ((or_ln136_23_fu_1482_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_15_fu_1515_p2 = ((or_ln136_24_fu_1509_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_1_fu_1081_p2 = ((or_ln136_10_fu_1075_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_2_fu_1108_p2 = ((or_ln136_11_fu_1102_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_3_fu_1135_p2 = ((or_ln136_12_fu_1129_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_4_fu_1162_p2 = ((or_ln136_13_fu_1156_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_5_fu_1189_p2 = ((or_ln136_14_fu_1183_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_6_fu_1216_p2 = ((or_ln136_15_fu_1210_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_7_fu_1243_p2 = ((or_ln136_16_fu_1237_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_8_fu_1326_p2 = ((or_ln136_17_fu_1320_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_9_fu_1353_p2 = ((or_ln136_18_fu_1347_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln136_fu_1054_p2 = ((or_ln136_9_fu_1048_p2 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln152_15_fu_1641_p2 = ((or_ln140_fu_1621_p2 == 5'd3) ? 1'b1 : 1'b0); + +assign icmp_ln152_16_fu_1655_p2 = ((or_ln140_fu_1621_p2 == 5'd5) ? 1'b1 : 1'b0); + +assign icmp_ln152_17_fu_1669_p2 = ((or_ln140_fu_1621_p2 == 5'd7) ? 1'b1 : 1'b0); + +assign icmp_ln152_18_fu_1683_p2 = ((or_ln140_fu_1621_p2 == 5'd9) ? 1'b1 : 1'b0); + +assign icmp_ln152_19_fu_1697_p2 = ((or_ln140_fu_1621_p2 == 5'd11) ? 1'b1 : 1'b0); + +assign icmp_ln152_20_fu_1711_p2 = ((or_ln140_fu_1621_p2 == 5'd13) ? 1'b1 : 1'b0); + +assign icmp_ln152_21_fu_1725_p2 = ((or_ln140_fu_1621_p2 == 5'd15) ? 1'b1 : 1'b0); + +assign icmp_ln152_22_fu_1739_p2 = ((or_ln140_fu_1621_p2 == 5'd17) ? 1'b1 : 1'b0); + +assign icmp_ln152_23_fu_1753_p2 = ((or_ln140_fu_1621_p2 == 5'd19) ? 1'b1 : 1'b0); + +assign icmp_ln152_24_fu_1767_p2 = ((or_ln140_fu_1621_p2 == 5'd21) ? 1'b1 : 1'b0); + +assign icmp_ln152_25_fu_1781_p2 = ((or_ln140_fu_1621_p2 == 5'd23) ? 1'b1 : 1'b0); + +assign icmp_ln152_26_fu_1799_p2 = ((or_ln140_reg_2426 == 5'd25) ? 1'b1 : 1'b0); + +assign icmp_ln152_27_fu_1811_p2 = ((or_ln140_reg_2426 == 5'd27) ? 1'b1 : 1'b0); + +assign icmp_ln152_28_fu_1824_p2 = ((or_ln140_reg_2426 == 5'd29) ? 1'b1 : 1'b0); + +assign icmp_ln152_fu_1627_p2 = ((or_ln140_fu_1621_p2 == 5'd1) ? 1'b1 : 1'b0); + +assign lshr_ln136_10_fu_1386_p4 = {{or_ln136_19_fu_1374_p2[7:2]}}; + +assign lshr_ln136_11_fu_1413_p4 = {{or_ln136_20_fu_1401_p2[7:2]}}; + +assign lshr_ln136_12_fu_1440_p4 = {{or_ln136_21_fu_1428_p2[7:2]}}; + +assign lshr_ln136_13_fu_1467_p4 = {{or_ln136_22_fu_1455_p2[7:2]}}; + +assign lshr_ln136_14_fu_1494_p4 = {{or_ln136_23_fu_1482_p2[7:2]}}; + +assign lshr_ln136_15_fu_1521_p4 = {{or_ln136_24_fu_1509_p2[7:2]}}; + +assign lshr_ln136_1_fu_1060_p4 = {{or_ln136_9_fu_1048_p2[7:2]}}; + +assign lshr_ln136_2_fu_1087_p4 = {{or_ln136_10_fu_1075_p2[7:2]}}; + +assign lshr_ln136_3_fu_1114_p4 = {{or_ln136_11_fu_1102_p2[7:2]}}; + +assign lshr_ln136_4_fu_1141_p4 = {{or_ln136_12_fu_1129_p2[7:2]}}; + +assign lshr_ln136_5_fu_1168_p4 = {{or_ln136_13_fu_1156_p2[7:2]}}; + +assign lshr_ln136_6_fu_1195_p4 = {{or_ln136_14_fu_1183_p2[7:2]}}; + +assign lshr_ln136_7_fu_1222_p4 = {{or_ln136_15_fu_1210_p2[7:2]}}; + +assign lshr_ln136_8_fu_1249_p4 = {{or_ln136_16_fu_1237_p2[7:2]}}; + +assign lshr_ln136_9_fu_1332_p4 = {{or_ln136_17_fu_1320_p2[7:2]}}; + +assign lshr_ln136_s_fu_1359_p4 = {{or_ln136_18_fu_1347_p2[7:2]}}; + +assign lshr_ln_fu_990_p4 = {{ap_phi_mux_x_phi_fu_475_p4[7:2]}}; + +assign or_ln136_10_fu_1075_p2 = (x_reg_471 | 8'd17); + +assign or_ln136_11_fu_1102_p2 = (x_reg_471 | 8'd18); + +assign or_ln136_12_fu_1129_p2 = (x_reg_471 | 8'd19); + +assign or_ln136_13_fu_1156_p2 = (x_reg_471 | 8'd20); + +assign or_ln136_14_fu_1183_p2 = (x_reg_471 | 8'd21); + +assign or_ln136_15_fu_1210_p2 = (x_reg_471 | 8'd22); + +assign or_ln136_16_fu_1237_p2 = (x_reg_471 | 8'd23); + +assign or_ln136_17_fu_1320_p2 = (x_reg_471 | 8'd24); + +assign or_ln136_18_fu_1347_p2 = (x_reg_471 | 8'd25); + +assign or_ln136_19_fu_1374_p2 = (x_reg_471 | 8'd26); + +assign or_ln136_20_fu_1401_p2 = (x_reg_471 | 8'd27); + +assign or_ln136_21_fu_1428_p2 = (x_reg_471 | 8'd28); + +assign or_ln136_22_fu_1455_p2 = (x_reg_471 | 8'd29); + +assign or_ln136_23_fu_1482_p2 = (x_reg_471 | 8'd30); + +assign or_ln136_24_fu_1509_p2 = (x_reg_471 | 8'd31); + +assign or_ln136_7_fu_1022_p2 = (lshr_ln_reg_1842 | 6'd2); + +assign or_ln136_8_fu_1035_p2 = (lshr_ln_reg_1842 | 6'd3); + +assign or_ln136_9_fu_1048_p2 = (x_reg_471 | 8'd16); + +assign or_ln136_fu_1008_p2 = (lshr_ln_fu_990_p4 | 6'd1); + +assign or_ln140_fu_1621_p2 = (trunc_ln140_fu_1611_p1 | 5'd1); + +assign select_ln136_10_fu_1550_p3 = ((icmp_ln136_10_reg_2148[0:0] == 1'b1) ? accum_in2_q1 : 16'd0); + +assign select_ln136_11_fu_1557_p3 = ((icmp_ln136_11_reg_2158[0:0] == 1'b1) ? accum_in3_q1 : 16'd0); + +assign select_ln136_12_fu_1564_p3 = ((icmp_ln136_12_reg_2168[0:0] == 1'b1) ? accum_in_q0 : 16'd0); + +assign select_ln136_13_fu_1571_p3 = ((icmp_ln136_13_reg_2178[0:0] == 1'b1) ? accum_in1_q0 : 16'd0); + +assign select_ln136_14_fu_1578_p3 = ((icmp_ln136_14_reg_2188[0:0] == 1'b1) ? accum_in2_q0 : 16'd0); + +assign select_ln136_15_fu_1585_p3 = ((icmp_ln136_15_reg_2198[0:0] == 1'b1) ? accum_in3_q0 : 16'd0); + +assign select_ln136_1_fu_1271_p3 = ((icmp_ln136_1_reg_2018[0:0] == 1'b1) ? accum_in1_q1 : 16'd0); + +assign select_ln136_2_fu_1278_p3 = ((icmp_ln136_2_reg_2028[0:0] == 1'b1) ? accum_in2_q1 : 16'd0); + +assign select_ln136_3_fu_1285_p3 = ((icmp_ln136_3_reg_2038[0:0] == 1'b1) ? accum_in3_q1 : 16'd0); + +assign select_ln136_4_fu_1292_p3 = ((icmp_ln136_4_reg_2048[0:0] == 1'b1) ? accum_in_q0 : 16'd0); + +assign select_ln136_5_fu_1299_p3 = ((icmp_ln136_5_reg_2058[0:0] == 1'b1) ? accum_in1_q0 : 16'd0); + +assign select_ln136_6_fu_1306_p3 = ((icmp_ln136_6_reg_2068[0:0] == 1'b1) ? accum_in2_q0 : 16'd0); + +assign select_ln136_7_fu_1313_p3 = ((icmp_ln136_7_reg_2078[0:0] == 1'b1) ? accum_in3_q0 : 16'd0); + +assign select_ln136_8_fu_1536_p3 = ((icmp_ln136_8_reg_2128[0:0] == 1'b1) ? accum_in_q1 : 16'd0); + +assign select_ln136_9_fu_1543_p3 = ((icmp_ln136_9_reg_2138[0:0] == 1'b1) ? accum_in1_q1 : 16'd0); + +assign select_ln136_fu_1264_p3 = ((icmp_ln136_reg_2008[0:0] == 1'b1) ? accum_in_q1 : 16'd0); + +assign select_ln152_15_fu_1647_p3 = ((icmp_ln152_15_fu_1641_p2[0:0] == 1'b1) ? psum_3_04_reg_495 : select_ln152_fu_1633_p3); + +assign select_ln152_16_fu_1661_p3 = ((icmp_ln152_16_fu_1655_p2[0:0] == 1'b1) ? psum_5_06_reg_591 : select_ln152_15_fu_1647_p3); + +assign select_ln152_17_fu_1675_p3 = ((icmp_ln152_17_fu_1669_p2[0:0] == 1'b1) ? psum_7_08_reg_567 : select_ln152_16_fu_1661_p3); + +assign select_ln152_18_fu_1689_p3 = ((icmp_ln152_18_fu_1683_p2[0:0] == 1'b1) ? psum_9_010_reg_543 : select_ln152_17_fu_1675_p3); + +assign select_ln152_19_fu_1703_p3 = ((icmp_ln152_19_fu_1697_p2[0:0] == 1'b1) ? psum_11_012_reg_843 : select_ln152_18_fu_1689_p3); + +assign select_ln152_20_fu_1717_p3 = ((icmp_ln152_20_fu_1711_p2[0:0] == 1'b1) ? psum_13_014_reg_819 : select_ln152_19_fu_1703_p3); + +assign select_ln152_21_fu_1731_p3 = ((icmp_ln152_21_fu_1725_p2[0:0] == 1'b1) ? psum_15_016_reg_795 : select_ln152_20_fu_1717_p3); + +assign select_ln152_22_fu_1745_p3 = ((icmp_ln152_22_fu_1739_p2[0:0] == 1'b1) ? psum_17_018_reg_771 : select_ln152_21_fu_1731_p3); + +assign select_ln152_23_fu_1759_p3 = ((icmp_ln152_23_fu_1753_p2[0:0] == 1'b1) ? psum_19_020_reg_747 : select_ln152_22_fu_1745_p3); + +assign select_ln152_24_fu_1773_p3 = ((icmp_ln152_24_fu_1767_p2[0:0] == 1'b1) ? psum_21_022_reg_723 : select_ln152_23_fu_1759_p3); + +assign select_ln152_25_fu_1787_p3 = ((icmp_ln152_25_fu_1781_p2[0:0] == 1'b1) ? psum_23_024_reg_699 : select_ln152_24_fu_1773_p3); + +assign select_ln152_26_fu_1804_p3 = ((icmp_ln152_26_fu_1799_p2[0:0] == 1'b1) ? psum_25_026_reg_675 : select_ln152_25_reg_2434); + +assign select_ln152_27_fu_1816_p3 = ((icmp_ln152_27_fu_1811_p2[0:0] == 1'b1) ? psum_27_028_reg_651 : select_ln152_26_fu_1804_p3); + +assign select_ln152_fu_1633_p3 = ((icmp_ln152_fu_1627_p2[0:0] == 1'b1) ? psum_1_02_reg_519 : psum_31_032_reg_603); + +assign tmp_fu_1598_p3 = q_reg_867[32'd5]; + +assign trunc_ln140_fu_1611_p1 = q_reg_867[4:0]; + +assign zext_ln136_10_fu_1040_p1 = or_ln136_8_fu_1035_p2; + +assign zext_ln136_11_fu_1070_p1 = lshr_ln136_1_fu_1060_p4; + +assign zext_ln136_12_fu_1097_p1 = lshr_ln136_2_fu_1087_p4; + +assign zext_ln136_13_fu_1124_p1 = lshr_ln136_3_fu_1114_p4; + +assign zext_ln136_14_fu_1151_p1 = lshr_ln136_4_fu_1141_p4; + +assign zext_ln136_15_fu_1178_p1 = lshr_ln136_5_fu_1168_p4; + +assign zext_ln136_16_fu_1205_p1 = lshr_ln136_6_fu_1195_p4; + +assign zext_ln136_17_fu_1232_p1 = lshr_ln136_7_fu_1222_p4; + +assign zext_ln136_18_fu_1259_p1 = lshr_ln136_8_fu_1249_p4; + +assign zext_ln136_19_fu_1342_p1 = lshr_ln136_9_fu_1332_p4; + +assign zext_ln136_20_fu_1369_p1 = lshr_ln136_s_fu_1359_p4; + +assign zext_ln136_21_fu_1396_p1 = lshr_ln136_10_fu_1386_p4; + +assign zext_ln136_22_fu_1423_p1 = lshr_ln136_11_fu_1413_p4; + +assign zext_ln136_23_fu_1450_p1 = lshr_ln136_12_fu_1440_p4; + +assign zext_ln136_24_fu_1477_p1 = lshr_ln136_13_fu_1467_p4; + +assign zext_ln136_25_fu_1504_p1 = lshr_ln136_14_fu_1494_p4; + +assign zext_ln136_26_fu_1531_p1 = lshr_ln136_15_fu_1521_p4; + +assign zext_ln136_8_fu_1014_p1 = or_ln136_fu_1008_p2; + +assign zext_ln136_9_fu_1027_p1 = or_ln136_7_fu_1022_p2; + +assign zext_ln136_fu_1000_p1 = lshr_ln_fu_990_p4; + +assign zext_ln140_2_fu_1795_p1 = or_ln140_reg_2426; + +assign zext_ln140_fu_1606_p1 = q_reg_867; + +always @ (posedge ap_clk) begin + or_ln140_reg_2426[0] <= 1'b1; +end + +endmodule //td_fused_top_tdf4_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_pp0_stage0 = 11'd2; +parameter ap_ST_fsm_pp0_stage1 = 11'd4; +parameter ap_ST_fsm_pp0_stage2 = 11'd8; +parameter ap_ST_fsm_pp0_stage3 = 11'd16; +parameter ap_ST_fsm_pp0_stage4 = 11'd32; +parameter ap_ST_fsm_pp0_stage5 = 11'd64; +parameter ap_ST_fsm_pp0_stage6 = 11'd128; +parameter ap_ST_fsm_state15 = 11'd256; +parameter ap_ST_fsm_state16 = 11'd512; +parameter ap_ST_fsm_state17 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [4:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [4:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[4:0] accum_in_address0; +reg accum_in_ce0; +reg[4:0] accum_in_address1; +reg accum_in_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [5:0] x_reg_168; +reg [15:0] psum_7_0134_reg_180; +reg [15:0] psum_6_0133_reg_192; +reg [15:0] psum_5_0132_reg_204; +reg [15:0] psum_4_0131_reg_216; +reg [15:0] psum_3_0130_reg_228; +reg [15:0] psum_2_0129_reg_240; +reg [15:0] psum_1_0128_reg_252; +reg [15:0] psum_0_0127_reg_264; +wire [0:0] tmp_fu_321_p3; +reg [0:0] tmp_reg_492; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state9_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +reg [0:0] tmp_reg_492_pp0_iter1_reg; +wire [4:0] trunc_ln171_fu_334_p1; +reg [4:0] trunc_ln171_reg_496; +reg [15:0] accum_in_load_reg_516; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state10_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_load_22_reg_521; +reg [15:0] accum_in_load_23_reg_536; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state11_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_load_24_reg_541; +reg [15:0] accum_in_load_25_reg_556; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state12_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_load_26_reg_561; +reg [15:0] accum_in_load_27_reg_576; +wire ap_CS_fsm_pp0_stage4; +wire ap_block_state6_pp0_stage4_iter0; +wire ap_block_state13_pp0_stage4_iter1; +wire ap_block_pp0_stage4_11001; +reg [15:0] accum_in_load_28_reg_581; +wire [5:0] add_ln171_fu_409_p2; +reg [5:0] add_ln171_reg_586; +wire ap_CS_fsm_pp0_stage6; +wire ap_block_state8_pp0_stage6_iter0; +wire ap_block_pp0_stage6_11001; +wire [15:0] grp_fu_305_p2; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_310_p2; +wire ap_CS_fsm_pp0_stage5; +wire ap_block_state7_pp0_stage5_iter0; +wire ap_block_state14_pp0_stage5_iter1; +wire ap_block_pp0_stage5_11001; +wire [3:0] add_ln179_fu_432_p2; +wire ap_CS_fsm_state16; +wire [0:0] tmp_59_fu_415_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage6_subdone; +wire ap_block_pp0_stage5_subdone; +reg [5:0] ap_phi_mux_x_phi_fu_172_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_0134_phi_fu_184_p4; +wire ap_block_pp0_stage5; +wire [15:0] ap_phi_mux_psum_6_0133_phi_fu_196_p4; +wire [15:0] ap_phi_mux_psum_5_0132_phi_fu_208_p4; +wire ap_block_pp0_stage4; +wire [15:0] ap_phi_mux_psum_4_0131_phi_fu_220_p4; +wire [15:0] ap_phi_mux_psum_3_0130_phi_fu_232_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_0129_phi_fu_244_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_276; +wire ap_CS_fsm_state15; +reg [15:0] ap_phi_mux_phi_ln191_phi_fu_290_p8; +wire [2:0] trunc_ln179_fu_428_p1; +wire [63:0] zext_ln171_fu_329_p1; +wire [63:0] zext_ln175_fu_344_p1; +wire [63:0] zext_ln175_7_fu_354_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln175_8_fu_364_p1; +wire [63:0] zext_ln175_9_fu_374_p1; +wire [63:0] zext_ln175_10_fu_384_p1; +wire [63:0] zext_ln175_11_fu_394_p1; +wire [63:0] zext_ln175_12_fu_404_p1; +wire [63:0] zext_ln179_fu_423_p1; +wire [63:0] zext_ln179_2_fu_444_p1; +reg [15:0] grp_fu_305_p0; +reg [15:0] grp_fu_305_p1; +reg [15:0] grp_fu_310_p0; +reg [15:0] grp_fu_310_p1; +wire [4:0] or_ln175_fu_338_p2; +wire [4:0] or_ln175_7_fu_349_p2; +wire [4:0] or_ln175_8_fu_359_p2; +wire [4:0] or_ln175_9_fu_369_p2; +wire [4:0] or_ln175_10_fu_379_p2; +wire [4:0] or_ln175_11_fu_389_p2; +wire [4:0] or_ln175_12_fu_399_p2; +wire ap_block_pp0_stage6; +wire [2:0] or_ln179_fu_438_p2; +wire [0:0] icmp_ln191_fu_449_p2; +wire [0:0] icmp_ln191_3_fu_463_p2; +wire [15:0] select_ln191_fu_455_p3; +wire [0:0] icmp_ln191_4_fu_477_p2; +wire [15:0] select_ln191_3_fu_469_p3; +wire ap_CS_fsm_state17; +reg [10:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +wire ap_block_pp0_stage1_subdone; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage4_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_570; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U538( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_305_p0), + .din1(grp_fu_305_p1), + .dout(grp_fu_305_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U539( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_310_p0), + .din1(grp_fu_310_p1), + .dout(grp_fu_310_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage5_subdone) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0)) | ((1'b0 == ap_block_pp0_stage6_subdone) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state15)) begin + q_reg_276 <= 4'd0; + end else if (((tmp_59_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + q_reg_276 <= add_ln179_fu_432_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + x_reg_168 <= add_ln171_reg_586; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_168 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_load_22_reg_521 <= accum_in_q0; + accum_in_load_reg_516 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage2_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_load_23_reg_536 <= accum_in_q1; + accum_in_load_24_reg_541 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage3_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_load_25_reg_556 <= accum_in_q1; + accum_in_load_26_reg_561 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage4_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_load_27_reg_576 <= accum_in_q1; + accum_in_load_28_reg_581 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage6_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln171_reg_586 <= add_ln171_fu_409_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage2_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + psum_0_0127_reg_264 <= grp_fu_305_p2; + psum_1_0128_reg_252 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + psum_2_0129_reg_240 <= grp_fu_305_p2; + psum_3_0130_reg_228 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage4_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + psum_4_0131_reg_216 <= grp_fu_305_p2; + psum_5_0132_reg_204 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage5_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + psum_6_0133_reg_192 <= grp_fu_305_p2; + psum_7_0134_reg_180 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + tmp_reg_492 <= ap_phi_mux_x_phi_fu_172_p4[32'd5]; + tmp_reg_492_pp0_iter1_reg <= tmp_reg_492; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_fu_321_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln171_reg_496 <= trunc_ln171_fu_334_p1; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_address0 = zext_ln175_12_fu_404_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_address0 = zext_ln175_10_fu_384_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_address0 = zext_ln175_8_fu_364_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_address0 = zext_ln175_fu_344_p1; + end else begin + accum_in_address0 = 'bx; + end + end else begin + accum_in_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_address1 = zext_ln175_11_fu_394_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_address1 = zext_ln175_9_fu_374_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_address1 = zext_ln175_7_fu_354_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_address1 = zext_ln171_fu_329_p1; + end else begin + accum_in_address1 = 'bx; + end + end else begin + accum_in_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_59_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_59_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_reg_492 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_59_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + if ((trunc_ln179_fu_428_p1 == 3'd0)) begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = psum_0_0127_reg_264; + end else if ((1'b1 == ap_condition_570)) begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = psum_6_0133_reg_192; + end else if ((trunc_ln179_fu_428_p1 == 3'd4)) begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = psum_4_0131_reg_216; + end else if ((trunc_ln179_fu_428_p1 == 3'd2)) begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = psum_2_0129_reg_240; + end else begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (tmp_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_x_phi_fu_172_p4 = add_ln171_reg_586; + end else begin + ap_phi_mux_x_phi_fu_172_p4 = x_reg_168; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_305_p0 = ap_phi_mux_psum_6_0133_phi_fu_196_p4; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_305_p0 = ap_phi_mux_psum_4_0131_phi_fu_220_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p0 = ap_phi_mux_psum_2_0129_phi_fu_244_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p0 = grp_fu_305_p2; + end else begin + grp_fu_305_p0 = 'bx; + end + end else begin + grp_fu_305_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_305_p1 = accum_in_load_27_reg_576; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_305_p1 = accum_in_load_25_reg_556; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p1 = accum_in_load_23_reg_536; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p1 = accum_in_load_reg_516; + end else begin + grp_fu_305_p1 = 'bx; + end + end else begin + grp_fu_305_p1 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_310_p0 = ap_phi_mux_psum_7_0134_phi_fu_184_p4; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_310_p0 = ap_phi_mux_psum_5_0132_phi_fu_208_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p0 = ap_phi_mux_psum_3_0130_phi_fu_232_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p0 = grp_fu_310_p2; + end else begin + grp_fu_310_p0 = 'bx; + end + end else begin + grp_fu_310_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_310_p1 = accum_in_load_28_reg_581; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_310_p1 = accum_in_load_26_reg_561; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p1 = accum_in_load_24_reg_541; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p1 = accum_in_load_22_reg_521; + end else begin + grp_fu_310_p1 = 'bx; + end + end else begin + grp_fu_310_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_492 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_492 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state15; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_pp0_stage4 : begin + if ((1'b0 == ap_block_pp0_stage4_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end + end + ap_ST_fsm_pp0_stage5 : begin + if ((~((1'b0 == ap_block_pp0_stage5_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0)) & (1'b0 == ap_block_pp0_stage5_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end else if (((1'b0 == ap_block_pp0_stage5_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state15; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end + end + ap_ST_fsm_pp0_stage6 : begin + if ((1'b0 == ap_block_pp0_stage6_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + if (((tmp_59_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + ap_NS_fsm = ap_ST_fsm_state16; + end else begin + ap_NS_fsm = ap_ST_fsm_state17; + end + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln179_2_fu_444_p1; + +assign accum_out_address1 = zext_ln179_fu_423_p1; + +assign accum_out_d0 = ((icmp_ln191_4_fu_477_p2[0:0] == 1'b1) ? psum_5_0132_reg_204 : select_ln191_3_fu_469_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln191_phi_fu_290_p8; + +assign add_ln171_fu_409_p2 = (x_reg_168 + 6'd8); + +assign add_ln179_fu_432_p2 = (q_reg_276 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state15 = ap_CS_fsm[32'd8]; + +assign ap_CS_fsm_state16 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd10]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage4_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage5_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_570 = (~(trunc_ln179_fu_428_p1 == 3'd0) & ~(trunc_ln179_fu_428_p1 == 3'd4) & ~(trunc_ln179_fu_428_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_0129_phi_fu_244_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_3_0130_phi_fu_232_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_4_0131_phi_fu_220_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_5_0132_phi_fu_208_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_6_0133_phi_fu_196_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_7_0134_phi_fu_184_p4 = grp_fu_310_p2; + +assign icmp_ln191_3_fu_463_p2 = ((or_ln179_fu_438_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln191_4_fu_477_p2 = ((or_ln179_fu_438_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln191_fu_449_p2 = ((or_ln179_fu_438_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln175_10_fu_379_p2 = (trunc_ln171_reg_496 | 5'd5); + +assign or_ln175_11_fu_389_p2 = (trunc_ln171_reg_496 | 5'd6); + +assign or_ln175_12_fu_399_p2 = (trunc_ln171_reg_496 | 5'd7); + +assign or_ln175_7_fu_349_p2 = (trunc_ln171_reg_496 | 5'd2); + +assign or_ln175_8_fu_359_p2 = (trunc_ln171_reg_496 | 5'd3); + +assign or_ln175_9_fu_369_p2 = (trunc_ln171_reg_496 | 5'd4); + +assign or_ln175_fu_338_p2 = (trunc_ln171_fu_334_p1 | 5'd1); + +assign or_ln179_fu_438_p2 = (trunc_ln179_fu_428_p1 | 3'd1); + +assign select_ln191_3_fu_469_p3 = ((icmp_ln191_3_fu_463_p2[0:0] == 1'b1) ? psum_3_0130_reg_228 : select_ln191_fu_455_p3); + +assign select_ln191_fu_455_p3 = ((icmp_ln191_fu_449_p2[0:0] == 1'b1) ? psum_1_0128_reg_252 : psum_7_0134_reg_180); + +assign tmp_59_fu_415_p3 = q_reg_276[32'd3]; + +assign tmp_fu_321_p3 = ap_phi_mux_x_phi_fu_172_p4[32'd5]; + +assign trunc_ln171_fu_334_p1 = ap_phi_mux_x_phi_fu_172_p4[4:0]; + +assign trunc_ln179_fu_428_p1 = q_reg_276[2:0]; + +assign zext_ln171_fu_329_p1 = ap_phi_mux_x_phi_fu_172_p4; + +assign zext_ln175_10_fu_384_p1 = or_ln175_10_fu_379_p2; + +assign zext_ln175_11_fu_394_p1 = or_ln175_11_fu_389_p2; + +assign zext_ln175_12_fu_404_p1 = or_ln175_12_fu_399_p2; + +assign zext_ln175_7_fu_354_p1 = or_ln175_7_fu_349_p2; + +assign zext_ln175_8_fu_364_p1 = or_ln175_8_fu_359_p2; + +assign zext_ln175_9_fu_374_p1 = or_ln175_9_fu_369_p2; + +assign zext_ln175_fu_344_p1 = or_ln175_fu_338_p2; + +assign zext_ln179_2_fu_444_p1 = or_ln179_fu_438_p2; + +assign zext_ln179_fu_423_p1 = q_reg_276; + +endmodule //td_fused_top_tdf4_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_accum_3_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state13 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [2:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_ce0; +reg accum_in_ce1; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [0:0] write_flag3_0_reg_67; +reg [0:0] write_flag6_0_reg_78; +reg [0:0] write_flag9_0_reg_89; +reg [0:0] write_flag_0_reg_100; +reg [2:0] out_idx_reg_111; +reg [15:0] accum_out_1_07_reg_122; +reg [15:0] accum_out_0_06_reg_134; +reg [15:0] accum_out_2_05_reg_146; +reg [15:0] accum_out_3_04_reg_158; +wire [2:0] add_ln220_fu_174_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln206_fu_180_p2; +reg [0:0] icmp_ln206_reg_380; +reg [0:0] icmp_ln206_reg_380_pp0_iter1_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter2_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter3_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter4_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter5_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter6_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter7_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter8_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter9_reg; +wire [1:0] trunc_ln207_fu_186_p1; +reg [1:0] trunc_ln207_reg_384; +reg [1:0] trunc_ln207_reg_384_pp0_iter1_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter2_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter3_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter4_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter5_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter6_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter7_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter8_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter9_reg; +wire [0:0] write_flag_1_fu_212_p6; +wire [0:0] write_flag9_1_fu_226_p6; +wire [0:0] write_flag6_1_fu_240_p6; +wire [0:0] write_flag3_1_fu_254_p6; +reg [15:0] accum_in_load_reg_421; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_load_1_reg_426; +wire [15:0] grp_fu_170_p2; +reg [15:0] sum0_reg_431; +wire [15:0] accum_out_3_1_fu_298_p3; +reg ap_enable_reg_pp0_iter10; +wire [15:0] accum_out_2_1_fu_306_p3; +wire [15:0] accum_out_0_1_fu_328_p3; +wire [15:0] accum_out_1_1_fu_343_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_condition_pp0_exit_iter9_state11; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln216_fu_196_p1; +wire [63:0] zext_ln216_1_fu_207_p1; +wire [2:0] i_12_fu_190_p2; +wire [2:0] or_ln216_fu_201_p2; +wire [0:0] icmp_ln219_fu_268_p2; +wire [0:0] icmp_ln219_5_fu_280_p2; +wire [15:0] select_ln219_fu_273_p3; +wire [0:0] icmp_ln219_6_fu_293_p2; +wire [15:0] select_ln219_9_fu_285_p3; +wire [15:0] select_ln219_10_fu_313_p3; +wire [15:0] select_ln219_11_fu_320_p3; +wire [15:0] select_ln219_12_fu_336_p3; +wire ap_CS_fsm_state13; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U548( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(accum_in_load_1_reg_426), + .din1(accum_in_load_reg_421), + .dout(grp_fu_170_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U549( + .din0(1'd1), + .din1(write_flag_0_reg_100), + .din2(write_flag_0_reg_100), + .din3(write_flag_0_reg_100), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag_1_fu_212_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U550( + .din0(write_flag9_0_reg_89), + .din1(write_flag9_0_reg_89), + .din2(write_flag9_0_reg_89), + .din3(1'd1), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag9_1_fu_226_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U551( + .din0(write_flag6_0_reg_78), + .din1(write_flag6_0_reg_78), + .din2(1'd1), + .din3(write_flag6_0_reg_78), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag6_1_fu_240_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U552( + .din0(write_flag3_0_reg_67), + .din1(1'd1), + .din2(write_flag3_0_reg_67), + .din3(write_flag3_0_reg_67), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag3_1_fu_254_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter9_state11))) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter8; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter9_state11) & (ap_enable_reg_pp0_iter8 == 1'b0)) | (~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + out_idx_reg_111 <= add_ln220_fu_174_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_111 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag3_0_reg_67 <= write_flag3_1_fu_254_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag3_0_reg_67 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag6_0_reg_78 <= write_flag6_1_fu_240_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_78 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag9_0_reg_89 <= write_flag9_1_fu_226_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_89 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag_0_reg_100 <= write_flag_1_fu_212_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_100 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_reg_380 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_load_1_reg_426 <= accum_in_q0; + accum_in_load_reg_421 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_reg_380_pp0_iter9_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_0_06_reg_134 <= accum_out_0_1_fu_328_p3; + accum_out_1_07_reg_122 <= accum_out_1_1_fu_343_p3; + accum_out_2_05_reg_146 <= accum_out_2_1_fu_306_p3; + accum_out_3_04_reg_158 <= accum_out_3_1_fu_298_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln206_reg_380 <= icmp_ln206_fu_180_p2; + icmp_ln206_reg_380_pp0_iter1_reg <= icmp_ln206_reg_380; + trunc_ln207_reg_384_pp0_iter1_reg <= trunc_ln207_reg_384; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln206_reg_380_pp0_iter2_reg <= icmp_ln206_reg_380_pp0_iter1_reg; + icmp_ln206_reg_380_pp0_iter3_reg <= icmp_ln206_reg_380_pp0_iter2_reg; + icmp_ln206_reg_380_pp0_iter4_reg <= icmp_ln206_reg_380_pp0_iter3_reg; + icmp_ln206_reg_380_pp0_iter5_reg <= icmp_ln206_reg_380_pp0_iter4_reg; + icmp_ln206_reg_380_pp0_iter6_reg <= icmp_ln206_reg_380_pp0_iter5_reg; + icmp_ln206_reg_380_pp0_iter7_reg <= icmp_ln206_reg_380_pp0_iter6_reg; + icmp_ln206_reg_380_pp0_iter8_reg <= icmp_ln206_reg_380_pp0_iter7_reg; + icmp_ln206_reg_380_pp0_iter9_reg <= icmp_ln206_reg_380_pp0_iter8_reg; + trunc_ln207_reg_384_pp0_iter2_reg <= trunc_ln207_reg_384_pp0_iter1_reg; + trunc_ln207_reg_384_pp0_iter3_reg <= trunc_ln207_reg_384_pp0_iter2_reg; + trunc_ln207_reg_384_pp0_iter4_reg <= trunc_ln207_reg_384_pp0_iter3_reg; + trunc_ln207_reg_384_pp0_iter5_reg <= trunc_ln207_reg_384_pp0_iter4_reg; + trunc_ln207_reg_384_pp0_iter6_reg <= trunc_ln207_reg_384_pp0_iter5_reg; + trunc_ln207_reg_384_pp0_iter7_reg <= trunc_ln207_reg_384_pp0_iter6_reg; + trunc_ln207_reg_384_pp0_iter8_reg <= trunc_ln207_reg_384_pp0_iter7_reg; + trunc_ln207_reg_384_pp0_iter9_reg <= trunc_ln207_reg_384_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_reg_380_pp0_iter8_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sum0_reg_431 <= grp_fu_170_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln207_reg_384 <= trunc_ln207_fu_186_p1; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_condition_pp0_exit_iter9_state11 = 1'b1; + end else begin + ap_condition_pp0_exit_iter9_state11 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln206_fu_180_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln216_1_fu_207_p1; + +assign accum_in_address1 = zext_ln216_fu_196_p1; + +assign accum_out_0_1_fu_328_p3 = ((icmp_ln219_6_fu_293_p2[0:0] == 1'b1) ? accum_out_0_06_reg_134 : select_ln219_11_fu_320_p3); + +assign accum_out_1_1_fu_343_p3 = ((icmp_ln219_6_fu_293_p2[0:0] == 1'b1) ? accum_out_1_07_reg_122 : select_ln219_12_fu_336_p3); + +assign accum_out_2_1_fu_306_p3 = ((icmp_ln219_6_fu_293_p2[0:0] == 1'b1) ? sum0_reg_431 : accum_out_2_05_reg_146); + +assign accum_out_3_1_fu_298_p3 = ((icmp_ln219_6_fu_293_p2[0:0] == 1'b1) ? accum_out_3_04_reg_158 : select_ln219_9_fu_285_p3); + +assign add_ln220_fu_174_p2 = (out_idx_reg_111 + 3'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = accum_out_0_06_reg_134; + +assign ap_return_1 = accum_out_1_07_reg_122; + +assign ap_return_2 = accum_out_2_05_reg_146; + +assign ap_return_3 = accum_out_3_04_reg_158; + +assign i_12_fu_190_p2 = out_idx_reg_111 << 3'd1; + +assign icmp_ln206_fu_180_p2 = ((out_idx_reg_111 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln219_5_fu_280_p2 = ((trunc_ln207_reg_384_pp0_iter9_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln219_6_fu_293_p2 = ((trunc_ln207_reg_384_pp0_iter9_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln219_fu_268_p2 = ((trunc_ln207_reg_384_pp0_iter9_reg == 2'd0) ? 1'b1 : 1'b0); + +assign or_ln216_fu_201_p2 = (i_12_fu_190_p2 | 3'd1); + +assign select_ln219_10_fu_313_p3 = ((icmp_ln219_fu_268_p2[0:0] == 1'b1) ? sum0_reg_431 : accum_out_0_06_reg_134); + +assign select_ln219_11_fu_320_p3 = ((icmp_ln219_5_fu_280_p2[0:0] == 1'b1) ? accum_out_0_06_reg_134 : select_ln219_10_fu_313_p3); + +assign select_ln219_12_fu_336_p3 = ((icmp_ln219_5_fu_280_p2[0:0] == 1'b1) ? sum0_reg_431 : accum_out_1_07_reg_122); + +assign select_ln219_9_fu_285_p3 = ((icmp_ln219_5_fu_280_p2[0:0] == 1'b1) ? accum_out_3_04_reg_158 : select_ln219_fu_273_p3); + +assign select_ln219_fu_273_p3 = ((icmp_ln219_fu_268_p2[0:0] == 1'b1) ? accum_out_3_04_reg_158 : sum0_reg_431); + +assign trunc_ln207_fu_186_p1 = out_idx_reg_111[1:0]; + +assign zext_ln216_1_fu_207_p1 = or_ln216_fu_201_p2; + +assign zext_ln216_fu_196_p1 = i_12_fu_190_p2; + +endmodule //td_fused_top_tdf4_accum_3_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_accum_3_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state13 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [2:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_ce0; +reg accum_in_ce1; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [0:0] write_flag3_0_reg_67; +reg [0:0] write_flag6_0_reg_78; +reg [0:0] write_flag9_0_reg_89; +reg [0:0] write_flag_0_reg_100; +reg [2:0] out_idx_reg_111; +reg [15:0] accum_out_1_07_reg_122; +reg [15:0] accum_out_0_06_reg_134; +reg [15:0] accum_out_2_05_reg_146; +reg [15:0] accum_out_3_04_reg_158; +wire [2:0] add_ln220_fu_174_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln206_fu_180_p2; +reg [0:0] icmp_ln206_reg_380; +reg [0:0] icmp_ln206_reg_380_pp0_iter1_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter2_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter3_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter4_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter5_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter6_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter7_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter8_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter9_reg; +wire [1:0] trunc_ln207_fu_186_p1; +reg [1:0] trunc_ln207_reg_384; +reg [1:0] trunc_ln207_reg_384_pp0_iter1_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter2_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter3_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter4_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter5_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter6_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter7_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter8_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter9_reg; +wire [0:0] write_flag_1_fu_212_p6; +wire [0:0] write_flag9_1_fu_226_p6; +wire [0:0] write_flag6_1_fu_240_p6; +wire [0:0] write_flag3_1_fu_254_p6; +reg [15:0] accum_in_load_reg_421; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_load_1_reg_426; +wire [15:0] grp_fu_170_p2; +reg [15:0] sum0_reg_431; +wire [15:0] accum_out_3_1_fu_298_p3; +reg ap_enable_reg_pp0_iter10; +wire [15:0] accum_out_2_1_fu_306_p3; +wire [15:0] accum_out_0_1_fu_328_p3; +wire [15:0] accum_out_1_1_fu_343_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_condition_pp0_exit_iter9_state11; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln216_fu_196_p1; +wire [63:0] zext_ln216_1_fu_207_p1; +wire [2:0] i_12_fu_190_p2; +wire [2:0] or_ln216_fu_201_p2; +wire [0:0] icmp_ln219_fu_268_p2; +wire [0:0] icmp_ln219_3_fu_280_p2; +wire [15:0] select_ln219_fu_273_p3; +wire [0:0] icmp_ln219_4_fu_293_p2; +wire [15:0] select_ln219_5_fu_285_p3; +wire [15:0] select_ln219_6_fu_313_p3; +wire [15:0] select_ln219_7_fu_320_p3; +wire [15:0] select_ln219_8_fu_336_p3; +wire ap_CS_fsm_state13; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U554( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(accum_in_load_1_reg_426), + .din1(accum_in_load_reg_421), + .dout(grp_fu_170_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U555( + .din0(1'd1), + .din1(write_flag_0_reg_100), + .din2(write_flag_0_reg_100), + .din3(write_flag_0_reg_100), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag_1_fu_212_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U556( + .din0(write_flag9_0_reg_89), + .din1(write_flag9_0_reg_89), + .din2(write_flag9_0_reg_89), + .din3(1'd1), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag9_1_fu_226_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U557( + .din0(write_flag6_0_reg_78), + .din1(write_flag6_0_reg_78), + .din2(1'd1), + .din3(write_flag6_0_reg_78), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag6_1_fu_240_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U558( + .din0(write_flag3_0_reg_67), + .din1(1'd1), + .din2(write_flag3_0_reg_67), + .din3(write_flag3_0_reg_67), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag3_1_fu_254_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter9_state11))) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter8; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter9_state11) & (ap_enable_reg_pp0_iter8 == 1'b0)) | (~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + out_idx_reg_111 <= add_ln220_fu_174_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_111 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag3_0_reg_67 <= write_flag3_1_fu_254_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag3_0_reg_67 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag6_0_reg_78 <= write_flag6_1_fu_240_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_78 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag9_0_reg_89 <= write_flag9_1_fu_226_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_89 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag_0_reg_100 <= write_flag_1_fu_212_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_100 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_reg_380 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_load_1_reg_426 <= accum_in_q0; + accum_in_load_reg_421 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_reg_380_pp0_iter9_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_0_06_reg_134 <= accum_out_0_1_fu_328_p3; + accum_out_1_07_reg_122 <= accum_out_1_1_fu_343_p3; + accum_out_2_05_reg_146 <= accum_out_2_1_fu_306_p3; + accum_out_3_04_reg_158 <= accum_out_3_1_fu_298_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln206_reg_380 <= icmp_ln206_fu_180_p2; + icmp_ln206_reg_380_pp0_iter1_reg <= icmp_ln206_reg_380; + trunc_ln207_reg_384_pp0_iter1_reg <= trunc_ln207_reg_384; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln206_reg_380_pp0_iter2_reg <= icmp_ln206_reg_380_pp0_iter1_reg; + icmp_ln206_reg_380_pp0_iter3_reg <= icmp_ln206_reg_380_pp0_iter2_reg; + icmp_ln206_reg_380_pp0_iter4_reg <= icmp_ln206_reg_380_pp0_iter3_reg; + icmp_ln206_reg_380_pp0_iter5_reg <= icmp_ln206_reg_380_pp0_iter4_reg; + icmp_ln206_reg_380_pp0_iter6_reg <= icmp_ln206_reg_380_pp0_iter5_reg; + icmp_ln206_reg_380_pp0_iter7_reg <= icmp_ln206_reg_380_pp0_iter6_reg; + icmp_ln206_reg_380_pp0_iter8_reg <= icmp_ln206_reg_380_pp0_iter7_reg; + icmp_ln206_reg_380_pp0_iter9_reg <= icmp_ln206_reg_380_pp0_iter8_reg; + trunc_ln207_reg_384_pp0_iter2_reg <= trunc_ln207_reg_384_pp0_iter1_reg; + trunc_ln207_reg_384_pp0_iter3_reg <= trunc_ln207_reg_384_pp0_iter2_reg; + trunc_ln207_reg_384_pp0_iter4_reg <= trunc_ln207_reg_384_pp0_iter3_reg; + trunc_ln207_reg_384_pp0_iter5_reg <= trunc_ln207_reg_384_pp0_iter4_reg; + trunc_ln207_reg_384_pp0_iter6_reg <= trunc_ln207_reg_384_pp0_iter5_reg; + trunc_ln207_reg_384_pp0_iter7_reg <= trunc_ln207_reg_384_pp0_iter6_reg; + trunc_ln207_reg_384_pp0_iter8_reg <= trunc_ln207_reg_384_pp0_iter7_reg; + trunc_ln207_reg_384_pp0_iter9_reg <= trunc_ln207_reg_384_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_reg_380_pp0_iter8_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sum0_reg_431 <= grp_fu_170_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln207_reg_384 <= trunc_ln207_fu_186_p1; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_condition_pp0_exit_iter9_state11 = 1'b1; + end else begin + ap_condition_pp0_exit_iter9_state11 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln206_fu_180_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln216_1_fu_207_p1; + +assign accum_in_address1 = zext_ln216_fu_196_p1; + +assign accum_out_0_1_fu_328_p3 = ((icmp_ln219_4_fu_293_p2[0:0] == 1'b1) ? accum_out_0_06_reg_134 : select_ln219_7_fu_320_p3); + +assign accum_out_1_1_fu_343_p3 = ((icmp_ln219_4_fu_293_p2[0:0] == 1'b1) ? accum_out_1_07_reg_122 : select_ln219_8_fu_336_p3); + +assign accum_out_2_1_fu_306_p3 = ((icmp_ln219_4_fu_293_p2[0:0] == 1'b1) ? sum0_reg_431 : accum_out_2_05_reg_146); + +assign accum_out_3_1_fu_298_p3 = ((icmp_ln219_4_fu_293_p2[0:0] == 1'b1) ? accum_out_3_04_reg_158 : select_ln219_5_fu_285_p3); + +assign add_ln220_fu_174_p2 = (out_idx_reg_111 + 3'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = accum_out_0_06_reg_134; + +assign ap_return_1 = accum_out_1_07_reg_122; + +assign ap_return_2 = accum_out_2_05_reg_146; + +assign ap_return_3 = accum_out_3_04_reg_158; + +assign i_12_fu_190_p2 = out_idx_reg_111 << 3'd1; + +assign icmp_ln206_fu_180_p2 = ((out_idx_reg_111 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln219_3_fu_280_p2 = ((trunc_ln207_reg_384_pp0_iter9_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln219_4_fu_293_p2 = ((trunc_ln207_reg_384_pp0_iter9_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln219_fu_268_p2 = ((trunc_ln207_reg_384_pp0_iter9_reg == 2'd0) ? 1'b1 : 1'b0); + +assign or_ln216_fu_201_p2 = (i_12_fu_190_p2 | 3'd1); + +assign select_ln219_5_fu_285_p3 = ((icmp_ln219_3_fu_280_p2[0:0] == 1'b1) ? accum_out_3_04_reg_158 : select_ln219_fu_273_p3); + +assign select_ln219_6_fu_313_p3 = ((icmp_ln219_fu_268_p2[0:0] == 1'b1) ? sum0_reg_431 : accum_out_0_06_reg_134); + +assign select_ln219_7_fu_320_p3 = ((icmp_ln219_3_fu_280_p2[0:0] == 1'b1) ? accum_out_0_06_reg_134 : select_ln219_6_fu_313_p3); + +assign select_ln219_8_fu_336_p3 = ((icmp_ln219_3_fu_280_p2[0:0] == 1'b1) ? sum0_reg_431 : accum_out_1_07_reg_122); + +assign select_ln219_fu_273_p3 = ((icmp_ln219_fu_268_p2[0:0] == 1'b1) ? accum_out_3_04_reg_158 : sum0_reg_431); + +assign trunc_ln207_fu_186_p1 = out_idx_reg_111[1:0]; + +assign zext_ln216_1_fu_207_p1 = or_ln216_fu_201_p2; + +assign zext_ln216_fu_196_p1 = i_12_fu_190_p2; + +endmodule //td_fused_top_tdf4_accum_3_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_accum_3_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state13 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [2:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_ce0; +reg accum_in_ce1; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [0:0] write_flag3_0_reg_67; +reg [0:0] write_flag6_0_reg_78; +reg [0:0] write_flag9_0_reg_89; +reg [0:0] write_flag_0_reg_100; +reg [2:0] out_idx_reg_111; +reg [15:0] accum_out_1_07_reg_122; +reg [15:0] accum_out_0_06_reg_134; +reg [15:0] accum_out_2_05_reg_146; +reg [15:0] accum_out_3_04_reg_158; +wire [2:0] add_ln220_fu_174_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln206_fu_180_p2; +reg [0:0] icmp_ln206_reg_380; +reg [0:0] icmp_ln206_reg_380_pp0_iter1_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter2_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter3_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter4_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter5_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter6_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter7_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter8_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter9_reg; +wire [1:0] trunc_ln207_fu_186_p1; +reg [1:0] trunc_ln207_reg_384; +reg [1:0] trunc_ln207_reg_384_pp0_iter1_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter2_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter3_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter4_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter5_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter6_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter7_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter8_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter9_reg; +wire [0:0] write_flag_1_fu_212_p6; +wire [0:0] write_flag9_1_fu_226_p6; +wire [0:0] write_flag6_1_fu_240_p6; +wire [0:0] write_flag3_1_fu_254_p6; +reg [15:0] accum_in_load_reg_421; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_load_1_reg_426; +wire [15:0] grp_fu_170_p2; +reg [15:0] sum0_reg_431; +wire [15:0] accum_out_3_1_fu_298_p3; +reg ap_enable_reg_pp0_iter10; +wire [15:0] accum_out_2_1_fu_306_p3; +wire [15:0] accum_out_0_1_fu_328_p3; +wire [15:0] accum_out_1_1_fu_343_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_condition_pp0_exit_iter9_state11; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln216_fu_196_p1; +wire [63:0] zext_ln216_1_fu_207_p1; +wire [2:0] i_12_fu_190_p2; +wire [2:0] or_ln216_fu_201_p2; +wire [0:0] icmp_ln219_fu_268_p2; +wire [0:0] icmp_ln219_1_fu_280_p2; +wire [15:0] select_ln219_fu_273_p3; +wire [0:0] icmp_ln219_2_fu_293_p2; +wire [15:0] select_ln219_1_fu_285_p3; +wire [15:0] select_ln219_2_fu_313_p3; +wire [15:0] select_ln219_3_fu_320_p3; +wire [15:0] select_ln219_4_fu_336_p3; +wire ap_CS_fsm_state13; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U560( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(accum_in_load_1_reg_426), + .din1(accum_in_load_reg_421), + .dout(grp_fu_170_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U561( + .din0(1'd1), + .din1(write_flag_0_reg_100), + .din2(write_flag_0_reg_100), + .din3(write_flag_0_reg_100), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag_1_fu_212_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U562( + .din0(write_flag9_0_reg_89), + .din1(write_flag9_0_reg_89), + .din2(write_flag9_0_reg_89), + .din3(1'd1), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag9_1_fu_226_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U563( + .din0(write_flag6_0_reg_78), + .din1(write_flag6_0_reg_78), + .din2(1'd1), + .din3(write_flag6_0_reg_78), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag6_1_fu_240_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U564( + .din0(write_flag3_0_reg_67), + .din1(1'd1), + .din2(write_flag3_0_reg_67), + .din3(write_flag3_0_reg_67), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag3_1_fu_254_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter9_state11))) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter8; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter9_state11) & (ap_enable_reg_pp0_iter8 == 1'b0)) | (~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + out_idx_reg_111 <= add_ln220_fu_174_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_111 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag3_0_reg_67 <= write_flag3_1_fu_254_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag3_0_reg_67 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag6_0_reg_78 <= write_flag6_1_fu_240_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_78 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag9_0_reg_89 <= write_flag9_1_fu_226_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_89 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag_0_reg_100 <= write_flag_1_fu_212_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_100 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_reg_380 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_load_1_reg_426 <= accum_in_q0; + accum_in_load_reg_421 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_reg_380_pp0_iter9_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_0_06_reg_134 <= accum_out_0_1_fu_328_p3; + accum_out_1_07_reg_122 <= accum_out_1_1_fu_343_p3; + accum_out_2_05_reg_146 <= accum_out_2_1_fu_306_p3; + accum_out_3_04_reg_158 <= accum_out_3_1_fu_298_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln206_reg_380 <= icmp_ln206_fu_180_p2; + icmp_ln206_reg_380_pp0_iter1_reg <= icmp_ln206_reg_380; + trunc_ln207_reg_384_pp0_iter1_reg <= trunc_ln207_reg_384; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln206_reg_380_pp0_iter2_reg <= icmp_ln206_reg_380_pp0_iter1_reg; + icmp_ln206_reg_380_pp0_iter3_reg <= icmp_ln206_reg_380_pp0_iter2_reg; + icmp_ln206_reg_380_pp0_iter4_reg <= icmp_ln206_reg_380_pp0_iter3_reg; + icmp_ln206_reg_380_pp0_iter5_reg <= icmp_ln206_reg_380_pp0_iter4_reg; + icmp_ln206_reg_380_pp0_iter6_reg <= icmp_ln206_reg_380_pp0_iter5_reg; + icmp_ln206_reg_380_pp0_iter7_reg <= icmp_ln206_reg_380_pp0_iter6_reg; + icmp_ln206_reg_380_pp0_iter8_reg <= icmp_ln206_reg_380_pp0_iter7_reg; + icmp_ln206_reg_380_pp0_iter9_reg <= icmp_ln206_reg_380_pp0_iter8_reg; + trunc_ln207_reg_384_pp0_iter2_reg <= trunc_ln207_reg_384_pp0_iter1_reg; + trunc_ln207_reg_384_pp0_iter3_reg <= trunc_ln207_reg_384_pp0_iter2_reg; + trunc_ln207_reg_384_pp0_iter4_reg <= trunc_ln207_reg_384_pp0_iter3_reg; + trunc_ln207_reg_384_pp0_iter5_reg <= trunc_ln207_reg_384_pp0_iter4_reg; + trunc_ln207_reg_384_pp0_iter6_reg <= trunc_ln207_reg_384_pp0_iter5_reg; + trunc_ln207_reg_384_pp0_iter7_reg <= trunc_ln207_reg_384_pp0_iter6_reg; + trunc_ln207_reg_384_pp0_iter8_reg <= trunc_ln207_reg_384_pp0_iter7_reg; + trunc_ln207_reg_384_pp0_iter9_reg <= trunc_ln207_reg_384_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_reg_380_pp0_iter8_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sum0_reg_431 <= grp_fu_170_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln207_reg_384 <= trunc_ln207_fu_186_p1; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_condition_pp0_exit_iter9_state11 = 1'b1; + end else begin + ap_condition_pp0_exit_iter9_state11 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln206_fu_180_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln216_1_fu_207_p1; + +assign accum_in_address1 = zext_ln216_fu_196_p1; + +assign accum_out_0_1_fu_328_p3 = ((icmp_ln219_2_fu_293_p2[0:0] == 1'b1) ? accum_out_0_06_reg_134 : select_ln219_3_fu_320_p3); + +assign accum_out_1_1_fu_343_p3 = ((icmp_ln219_2_fu_293_p2[0:0] == 1'b1) ? accum_out_1_07_reg_122 : select_ln219_4_fu_336_p3); + +assign accum_out_2_1_fu_306_p3 = ((icmp_ln219_2_fu_293_p2[0:0] == 1'b1) ? sum0_reg_431 : accum_out_2_05_reg_146); + +assign accum_out_3_1_fu_298_p3 = ((icmp_ln219_2_fu_293_p2[0:0] == 1'b1) ? accum_out_3_04_reg_158 : select_ln219_1_fu_285_p3); + +assign add_ln220_fu_174_p2 = (out_idx_reg_111 + 3'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = accum_out_0_06_reg_134; + +assign ap_return_1 = accum_out_1_07_reg_122; + +assign ap_return_2 = accum_out_2_05_reg_146; + +assign ap_return_3 = accum_out_3_04_reg_158; + +assign i_12_fu_190_p2 = out_idx_reg_111 << 3'd1; + +assign icmp_ln206_fu_180_p2 = ((out_idx_reg_111 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln219_1_fu_280_p2 = ((trunc_ln207_reg_384_pp0_iter9_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln219_2_fu_293_p2 = ((trunc_ln207_reg_384_pp0_iter9_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln219_fu_268_p2 = ((trunc_ln207_reg_384_pp0_iter9_reg == 2'd0) ? 1'b1 : 1'b0); + +assign or_ln216_fu_201_p2 = (i_12_fu_190_p2 | 3'd1); + +assign select_ln219_1_fu_285_p3 = ((icmp_ln219_1_fu_280_p2[0:0] == 1'b1) ? accum_out_3_04_reg_158 : select_ln219_fu_273_p3); + +assign select_ln219_2_fu_313_p3 = ((icmp_ln219_fu_268_p2[0:0] == 1'b1) ? sum0_reg_431 : accum_out_0_06_reg_134); + +assign select_ln219_3_fu_320_p3 = ((icmp_ln219_1_fu_280_p2[0:0] == 1'b1) ? accum_out_0_06_reg_134 : select_ln219_2_fu_313_p3); + +assign select_ln219_4_fu_336_p3 = ((icmp_ln219_1_fu_280_p2[0:0] == 1'b1) ? sum0_reg_431 : accum_out_1_07_reg_122); + +assign select_ln219_fu_273_p3 = ((icmp_ln219_fu_268_p2[0:0] == 1'b1) ? accum_out_3_04_reg_158 : sum0_reg_431); + +assign trunc_ln207_fu_186_p1 = out_idx_reg_111[1:0]; + +assign zext_ln216_1_fu_207_p1 = or_ln216_fu_201_p2; + +assign zext_ln216_fu_196_p1 = i_12_fu_190_p2; + +endmodule //td_fused_top_tdf4_accum_3_3 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_accum_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state13 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [2:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_ce0; +reg accum_in_ce1; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [0:0] write_flag3_0_reg_67; +reg [0:0] write_flag6_0_reg_78; +reg [0:0] write_flag9_0_reg_89; +reg [0:0] write_flag_0_reg_100; +reg [2:0] out_idx_reg_111; +reg [15:0] accum_out_1_07_reg_122; +reg [15:0] accum_out_0_06_reg_134; +reg [15:0] accum_out_2_05_reg_146; +reg [15:0] accum_out_3_04_reg_158; +wire [2:0] add_ln220_fu_174_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln206_fu_180_p2; +reg [0:0] icmp_ln206_reg_380; +reg [0:0] icmp_ln206_reg_380_pp0_iter1_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter2_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter3_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter4_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter5_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter6_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter7_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter8_reg; +reg [0:0] icmp_ln206_reg_380_pp0_iter9_reg; +wire [1:0] trunc_ln207_fu_186_p1; +reg [1:0] trunc_ln207_reg_384; +reg [1:0] trunc_ln207_reg_384_pp0_iter1_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter2_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter3_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter4_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter5_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter6_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter7_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter8_reg; +reg [1:0] trunc_ln207_reg_384_pp0_iter9_reg; +wire [0:0] write_flag_1_fu_212_p6; +wire [0:0] write_flag9_1_fu_226_p6; +wire [0:0] write_flag6_1_fu_240_p6; +wire [0:0] write_flag3_1_fu_254_p6; +reg [15:0] accum_in_load_reg_421; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_load_1_reg_426; +wire [15:0] grp_fu_170_p2; +reg [15:0] sum0_reg_431; +wire [15:0] accum_out_3_1_fu_298_p3; +reg ap_enable_reg_pp0_iter10; +wire [15:0] accum_out_2_1_fu_306_p3; +wire [15:0] accum_out_0_1_fu_328_p3; +wire [15:0] accum_out_1_1_fu_343_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_condition_pp0_exit_iter9_state11; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln216_fu_196_p1; +wire [63:0] zext_ln216_1_fu_207_p1; +wire [2:0] i_12_fu_190_p2; +wire [2:0] or_ln216_fu_201_p2; +wire [0:0] icmp_ln219_fu_268_p2; +wire [0:0] icmp_ln219_7_fu_280_p2; +wire [15:0] select_ln219_fu_273_p3; +wire [0:0] icmp_ln219_8_fu_293_p2; +wire [15:0] select_ln219_13_fu_285_p3; +wire [15:0] select_ln219_14_fu_313_p3; +wire [15:0] select_ln219_15_fu_320_p3; +wire [15:0] select_ln219_16_fu_336_p3; +wire ap_CS_fsm_state13; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U542( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(accum_in_load_1_reg_426), + .din1(accum_in_load_reg_421), + .dout(grp_fu_170_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U543( + .din0(1'd1), + .din1(write_flag_0_reg_100), + .din2(write_flag_0_reg_100), + .din3(write_flag_0_reg_100), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag_1_fu_212_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U544( + .din0(write_flag9_0_reg_89), + .din1(write_flag9_0_reg_89), + .din2(write_flag9_0_reg_89), + .din3(1'd1), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag9_1_fu_226_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U545( + .din0(write_flag6_0_reg_78), + .din1(write_flag6_0_reg_78), + .din2(1'd1), + .din3(write_flag6_0_reg_78), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag6_1_fu_240_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U546( + .din0(write_flag3_0_reg_67), + .din1(1'd1), + .din2(write_flag3_0_reg_67), + .din3(write_flag3_0_reg_67), + .din4(trunc_ln207_fu_186_p1), + .dout(write_flag3_1_fu_254_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter9_state11))) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter8; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter9_state11) & (ap_enable_reg_pp0_iter8 == 1'b0)) | (~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + out_idx_reg_111 <= add_ln220_fu_174_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_111 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag3_0_reg_67 <= write_flag3_1_fu_254_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag3_0_reg_67 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag6_0_reg_78 <= write_flag6_1_fu_240_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_78 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag9_0_reg_89 <= write_flag9_1_fu_226_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_89 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + write_flag_0_reg_100 <= write_flag_1_fu_212_p6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_100 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_reg_380 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_load_1_reg_426 <= accum_in_q0; + accum_in_load_reg_421 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_reg_380_pp0_iter9_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_0_06_reg_134 <= accum_out_0_1_fu_328_p3; + accum_out_1_07_reg_122 <= accum_out_1_1_fu_343_p3; + accum_out_2_05_reg_146 <= accum_out_2_1_fu_306_p3; + accum_out_3_04_reg_158 <= accum_out_3_1_fu_298_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln206_reg_380 <= icmp_ln206_fu_180_p2; + icmp_ln206_reg_380_pp0_iter1_reg <= icmp_ln206_reg_380; + trunc_ln207_reg_384_pp0_iter1_reg <= trunc_ln207_reg_384; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln206_reg_380_pp0_iter2_reg <= icmp_ln206_reg_380_pp0_iter1_reg; + icmp_ln206_reg_380_pp0_iter3_reg <= icmp_ln206_reg_380_pp0_iter2_reg; + icmp_ln206_reg_380_pp0_iter4_reg <= icmp_ln206_reg_380_pp0_iter3_reg; + icmp_ln206_reg_380_pp0_iter5_reg <= icmp_ln206_reg_380_pp0_iter4_reg; + icmp_ln206_reg_380_pp0_iter6_reg <= icmp_ln206_reg_380_pp0_iter5_reg; + icmp_ln206_reg_380_pp0_iter7_reg <= icmp_ln206_reg_380_pp0_iter6_reg; + icmp_ln206_reg_380_pp0_iter8_reg <= icmp_ln206_reg_380_pp0_iter7_reg; + icmp_ln206_reg_380_pp0_iter9_reg <= icmp_ln206_reg_380_pp0_iter8_reg; + trunc_ln207_reg_384_pp0_iter2_reg <= trunc_ln207_reg_384_pp0_iter1_reg; + trunc_ln207_reg_384_pp0_iter3_reg <= trunc_ln207_reg_384_pp0_iter2_reg; + trunc_ln207_reg_384_pp0_iter4_reg <= trunc_ln207_reg_384_pp0_iter3_reg; + trunc_ln207_reg_384_pp0_iter5_reg <= trunc_ln207_reg_384_pp0_iter4_reg; + trunc_ln207_reg_384_pp0_iter6_reg <= trunc_ln207_reg_384_pp0_iter5_reg; + trunc_ln207_reg_384_pp0_iter7_reg <= trunc_ln207_reg_384_pp0_iter6_reg; + trunc_ln207_reg_384_pp0_iter8_reg <= trunc_ln207_reg_384_pp0_iter7_reg; + trunc_ln207_reg_384_pp0_iter9_reg <= trunc_ln207_reg_384_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_reg_380_pp0_iter8_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sum0_reg_431 <= grp_fu_170_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln206_fu_180_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln207_reg_384 <= trunc_ln207_fu_186_p1; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_condition_pp0_exit_iter9_state11 = 1'b1; + end else begin + ap_condition_pp0_exit_iter9_state11 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln206_fu_180_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter9 == 1'b1) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln216_1_fu_207_p1; + +assign accum_in_address1 = zext_ln216_fu_196_p1; + +assign accum_out_0_1_fu_328_p3 = ((icmp_ln219_8_fu_293_p2[0:0] == 1'b1) ? accum_out_0_06_reg_134 : select_ln219_15_fu_320_p3); + +assign accum_out_1_1_fu_343_p3 = ((icmp_ln219_8_fu_293_p2[0:0] == 1'b1) ? accum_out_1_07_reg_122 : select_ln219_16_fu_336_p3); + +assign accum_out_2_1_fu_306_p3 = ((icmp_ln219_8_fu_293_p2[0:0] == 1'b1) ? sum0_reg_431 : accum_out_2_05_reg_146); + +assign accum_out_3_1_fu_298_p3 = ((icmp_ln219_8_fu_293_p2[0:0] == 1'b1) ? accum_out_3_04_reg_158 : select_ln219_13_fu_285_p3); + +assign add_ln220_fu_174_p2 = (out_idx_reg_111 + 3'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = accum_out_0_06_reg_134; + +assign ap_return_1 = accum_out_1_07_reg_122; + +assign ap_return_2 = accum_out_2_05_reg_146; + +assign ap_return_3 = accum_out_3_04_reg_158; + +assign i_12_fu_190_p2 = out_idx_reg_111 << 3'd1; + +assign icmp_ln206_fu_180_p2 = ((out_idx_reg_111 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln219_7_fu_280_p2 = ((trunc_ln207_reg_384_pp0_iter9_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln219_8_fu_293_p2 = ((trunc_ln207_reg_384_pp0_iter9_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln219_fu_268_p2 = ((trunc_ln207_reg_384_pp0_iter9_reg == 2'd0) ? 1'b1 : 1'b0); + +assign or_ln216_fu_201_p2 = (i_12_fu_190_p2 | 3'd1); + +assign select_ln219_13_fu_285_p3 = ((icmp_ln219_7_fu_280_p2[0:0] == 1'b1) ? accum_out_3_04_reg_158 : select_ln219_fu_273_p3); + +assign select_ln219_14_fu_313_p3 = ((icmp_ln219_fu_268_p2[0:0] == 1'b1) ? sum0_reg_431 : accum_out_0_06_reg_134); + +assign select_ln219_15_fu_320_p3 = ((icmp_ln219_7_fu_280_p2[0:0] == 1'b1) ? accum_out_0_06_reg_134 : select_ln219_14_fu_313_p3); + +assign select_ln219_16_fu_336_p3 = ((icmp_ln219_7_fu_280_p2[0:0] == 1'b1) ? sum0_reg_431 : accum_out_1_07_reg_122); + +assign select_ln219_fu_273_p3 = ((icmp_ln219_fu_268_p2[0:0] == 1'b1) ? accum_out_3_04_reg_158 : sum0_reg_431); + +assign trunc_ln207_fu_186_p1 = out_idx_reg_111[1:0]; + +assign zext_ln216_1_fu_207_p1 = or_ln216_fu_201_p2; + +assign zext_ln216_fu_196_p1 = i_12_fu_190_p2; + +endmodule //td_fused_top_tdf4_accum_3 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_accum_4_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0, + accum_in_0_ap_vld, + p_read, + accum_in_1_read, + accum_in_2_read, + accum_in_3_read +); + +parameter ap_ST_fsm_state1 = 10'd1; +parameter ap_ST_fsm_state2 = 10'd2; +parameter ap_ST_fsm_state3 = 10'd4; +parameter ap_ST_fsm_state4 = 10'd8; +parameter ap_ST_fsm_state5 = 10'd16; +parameter ap_ST_fsm_state6 = 10'd32; +parameter ap_ST_fsm_state7 = 10'd64; +parameter ap_ST_fsm_state8 = 10'd128; +parameter ap_ST_fsm_state9 = 10'd256; +parameter ap_ST_fsm_state10 = 10'd512; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_0; +output accum_in_0_ap_vld; +input [15:0] p_read; +input [15:0] accum_in_1_read; +input [15:0] accum_in_2_read; +input [15:0] accum_in_3_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_0; +reg accum_in_0_ap_vld; + +reg ap_done_reg; + reg [9:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [2:0] add_ln233_fu_92_p2; +reg [2:0] add_ln233_reg_138; +wire ap_CS_fsm_state2; +wire [15:0] tmp_fu_108_p6; +reg [15:0] tmp_reg_146; +wire [0:0] icmp_ln233_fu_98_p2; +wire [15:0] grp_fu_87_p2; +wire ap_CS_fsm_state10; +reg [2:0] i_1_1_reg_63; +reg ap_block_state1; +reg [15:0] sum_01_reg_74; +reg [15:0] accum_in_0_preg; +wire ap_CS_fsm_state3; +wire [1:0] tmp_fu_108_p5; +reg [9:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 10'd1; +#0 accum_in_0_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U574( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_74), + .din1(tmp_reg_146), + .dout(grp_fu_87_p2) +); + +td_fused_top_mux_42_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 16 )) +mux_42_16_1_1_U575( + .din0(p_read), + .din1(accum_in_1_read), + .din2(accum_in_2_read), + .din3(accum_in_3_read), + .din4(tmp_fu_108_p5), + .dout(tmp_fu_108_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_0_preg <= 16'd0; + end else begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_0_preg <= sum_01_reg_74; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_63 <= 3'd0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + i_1_1_reg_63 <= add_ln233_reg_138; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_74 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + sum_01_reg_74 <= grp_fu_87_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln233_reg_138 <= add_ln233_fu_92_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln233_fu_98_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + tmp_reg_146 <= tmp_fu_108_p6; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_0 = sum_01_reg_74; + end else begin + accum_in_0 = accum_in_0_preg; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_0_ap_vld = 1'b1; + end else begin + accum_in_0_ap_vld = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln233_fu_92_p2 = (i_1_1_reg_63 + 3'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln233_fu_98_p2 = ((i_1_1_reg_63 == 3'd4) ? 1'b1 : 1'b0); + +assign tmp_fu_108_p5 = i_1_1_reg_63[1:0]; + +endmodule //td_fused_top_tdf4_accum_4_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_accum_4_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0, + accum_in_0_ap_vld, + p_read, + accum_in_1_read, + accum_in_2_read, + accum_in_3_read +); + +parameter ap_ST_fsm_state1 = 10'd1; +parameter ap_ST_fsm_state2 = 10'd2; +parameter ap_ST_fsm_state3 = 10'd4; +parameter ap_ST_fsm_state4 = 10'd8; +parameter ap_ST_fsm_state5 = 10'd16; +parameter ap_ST_fsm_state6 = 10'd32; +parameter ap_ST_fsm_state7 = 10'd64; +parameter ap_ST_fsm_state8 = 10'd128; +parameter ap_ST_fsm_state9 = 10'd256; +parameter ap_ST_fsm_state10 = 10'd512; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_0; +output accum_in_0_ap_vld; +input [15:0] p_read; +input [15:0] accum_in_1_read; +input [15:0] accum_in_2_read; +input [15:0] accum_in_3_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_0; +reg accum_in_0_ap_vld; + +reg ap_done_reg; + reg [9:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [2:0] add_ln233_fu_92_p2; +reg [2:0] add_ln233_reg_138; +wire ap_CS_fsm_state2; +wire [15:0] tmp_fu_108_p6; +reg [15:0] tmp_reg_146; +wire [0:0] icmp_ln233_fu_98_p2; +wire [15:0] grp_fu_87_p2; +wire ap_CS_fsm_state10; +reg [2:0] i_1_1_reg_63; +reg ap_block_state1; +reg [15:0] sum_01_reg_74; +reg [15:0] accum_in_0_preg; +wire ap_CS_fsm_state3; +wire [1:0] tmp_fu_108_p5; +reg [9:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 10'd1; +#0 accum_in_0_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U582( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_74), + .din1(tmp_reg_146), + .dout(grp_fu_87_p2) +); + +td_fused_top_mux_42_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 16 )) +mux_42_16_1_1_U583( + .din0(p_read), + .din1(accum_in_1_read), + .din2(accum_in_2_read), + .din3(accum_in_3_read), + .din4(tmp_fu_108_p5), + .dout(tmp_fu_108_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_0_preg <= 16'd0; + end else begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_0_preg <= sum_01_reg_74; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_63 <= 3'd0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + i_1_1_reg_63 <= add_ln233_reg_138; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_74 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + sum_01_reg_74 <= grp_fu_87_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln233_reg_138 <= add_ln233_fu_92_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln233_fu_98_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + tmp_reg_146 <= tmp_fu_108_p6; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_0 = sum_01_reg_74; + end else begin + accum_in_0 = accum_in_0_preg; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_0_ap_vld = 1'b1; + end else begin + accum_in_0_ap_vld = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln233_fu_92_p2 = (i_1_1_reg_63 + 3'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln233_fu_98_p2 = ((i_1_1_reg_63 == 3'd4) ? 1'b1 : 1'b0); + +assign tmp_fu_108_p5 = i_1_1_reg_63[1:0]; + +endmodule //td_fused_top_tdf4_accum_4_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_accum_4_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0, + accum_in_0_ap_vld, + p_read, + accum_in_1_read, + accum_in_2_read, + accum_in_3_read +); + +parameter ap_ST_fsm_state1 = 10'd1; +parameter ap_ST_fsm_state2 = 10'd2; +parameter ap_ST_fsm_state3 = 10'd4; +parameter ap_ST_fsm_state4 = 10'd8; +parameter ap_ST_fsm_state5 = 10'd16; +parameter ap_ST_fsm_state6 = 10'd32; +parameter ap_ST_fsm_state7 = 10'd64; +parameter ap_ST_fsm_state8 = 10'd128; +parameter ap_ST_fsm_state9 = 10'd256; +parameter ap_ST_fsm_state10 = 10'd512; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_0; +output accum_in_0_ap_vld; +input [15:0] p_read; +input [15:0] accum_in_1_read; +input [15:0] accum_in_2_read; +input [15:0] accum_in_3_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_0; +reg accum_in_0_ap_vld; + +reg ap_done_reg; + reg [9:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [2:0] add_ln233_fu_92_p2; +reg [2:0] add_ln233_reg_138; +wire ap_CS_fsm_state2; +wire [15:0] tmp_fu_108_p6; +reg [15:0] tmp_reg_146; +wire [0:0] icmp_ln233_fu_98_p2; +wire [15:0] grp_fu_87_p2; +wire ap_CS_fsm_state10; +reg [2:0] i_1_1_reg_63; +reg ap_block_state1; +reg [15:0] sum_01_reg_74; +reg [15:0] accum_in_0_preg; +wire ap_CS_fsm_state3; +wire [1:0] tmp_fu_108_p5; +reg [9:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 10'd1; +#0 accum_in_0_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U590( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_74), + .din1(tmp_reg_146), + .dout(grp_fu_87_p2) +); + +td_fused_top_mux_42_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 16 )) +mux_42_16_1_1_U591( + .din0(p_read), + .din1(accum_in_1_read), + .din2(accum_in_2_read), + .din3(accum_in_3_read), + .din4(tmp_fu_108_p5), + .dout(tmp_fu_108_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_0_preg <= 16'd0; + end else begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_0_preg <= sum_01_reg_74; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_63 <= 3'd0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + i_1_1_reg_63 <= add_ln233_reg_138; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_74 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + sum_01_reg_74 <= grp_fu_87_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln233_reg_138 <= add_ln233_fu_92_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln233_fu_98_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + tmp_reg_146 <= tmp_fu_108_p6; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_0 = sum_01_reg_74; + end else begin + accum_in_0 = accum_in_0_preg; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_0_ap_vld = 1'b1; + end else begin + accum_in_0_ap_vld = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln233_fu_92_p2 = (i_1_1_reg_63 + 3'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln233_fu_98_p2 = ((i_1_1_reg_63 == 3'd4) ? 1'b1 : 1'b0); + +assign tmp_fu_108_p5 = i_1_1_reg_63[1:0]; + +endmodule //td_fused_top_tdf4_accum_4_3 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_accum_4 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0, + accum_in_0_ap_vld, + p_read, + accum_in_1_read, + accum_in_2_read, + accum_in_3_read +); + +parameter ap_ST_fsm_state1 = 10'd1; +parameter ap_ST_fsm_state2 = 10'd2; +parameter ap_ST_fsm_state3 = 10'd4; +parameter ap_ST_fsm_state4 = 10'd8; +parameter ap_ST_fsm_state5 = 10'd16; +parameter ap_ST_fsm_state6 = 10'd32; +parameter ap_ST_fsm_state7 = 10'd64; +parameter ap_ST_fsm_state8 = 10'd128; +parameter ap_ST_fsm_state9 = 10'd256; +parameter ap_ST_fsm_state10 = 10'd512; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_0; +output accum_in_0_ap_vld; +input [15:0] p_read; +input [15:0] accum_in_1_read; +input [15:0] accum_in_2_read; +input [15:0] accum_in_3_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_0; +reg accum_in_0_ap_vld; + +reg ap_done_reg; + reg [9:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [2:0] add_ln233_fu_92_p2; +reg [2:0] add_ln233_reg_138; +wire ap_CS_fsm_state2; +wire [15:0] tmp_fu_108_p6; +reg [15:0] tmp_reg_146; +wire [0:0] icmp_ln233_fu_98_p2; +wire [15:0] grp_fu_87_p2; +wire ap_CS_fsm_state10; +reg [2:0] i_1_1_reg_63; +reg ap_block_state1; +reg [15:0] sum_01_reg_74; +reg [15:0] accum_in_0_preg; +wire ap_CS_fsm_state3; +wire [1:0] tmp_fu_108_p5; +reg [9:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 10'd1; +#0 accum_in_0_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U566( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_74), + .din1(tmp_reg_146), + .dout(grp_fu_87_p2) +); + +td_fused_top_mux_42_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 16 )) +mux_42_16_1_1_U567( + .din0(p_read), + .din1(accum_in_1_read), + .din2(accum_in_2_read), + .din3(accum_in_3_read), + .din4(tmp_fu_108_p5), + .dout(tmp_fu_108_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_0_preg <= 16'd0; + end else begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_0_preg <= sum_01_reg_74; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_63 <= 3'd0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + i_1_1_reg_63 <= add_ln233_reg_138; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_74 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + sum_01_reg_74 <= grp_fu_87_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln233_reg_138 <= add_ln233_fu_92_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln233_fu_98_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + tmp_reg_146 <= tmp_fu_108_p6; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_0 = sum_01_reg_74; + end else begin + accum_in_0 = accum_in_0_preg; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_0_ap_vld = 1'b1; + end else begin + accum_in_0_ap_vld = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln233_fu_98_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln233_fu_92_p2 = (i_1_1_reg_63 + 3'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln233_fu_98_p2 = ((i_1_1_reg_63 == 3'd4) ? 1'b1 : 1'b0); + +assign tmp_fu_108_p5 = i_1_1_reg_63[1:0]; + +endmodule //td_fused_top_tdf4_accum_4 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_adjustments_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 48; +parameter AWIDTH = 7; +parameter MEM_SIZE = 128; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_adjustments( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd48; +parameter AddressRange = 32'd128; +parameter AddressWidth = 32'd7; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf4_adjustments_ram td_fused_top_tdf4_adjustments_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_0_read, + sums_1_read, + sums_2_read, + sums_3_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + indices_23_out_din, + indices_23_out_full_n, + indices_23_out_write, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state25 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_0_read; +input [15:0] sums_1_read; +input [15:0] sums_2_read; +input [15:0] sums_3_read; +output [6:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [4:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [4:0] indices_23_out_din; +input indices_23_out_full_n; +output indices_23_out_write; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg indices_23_read; +reg indices_23_out_write; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg indices_23_out_blk_n; +reg [0:0] write_flag6_0_reg_153; +reg [0:0] write_flag9_0_reg_164; +reg [0:0] write_flag12_0_reg_175; +reg [0:0] write_flag_0_reg_186; +reg [2:0] o_reg_197; +reg [15:0] outputs_1_011_reg_208; +reg [15:0] outputs_0_010_reg_220; +reg [15:0] outputs_2_09_reg_232; +reg [15:0] outputs_3_08_reg_244; +reg [4:0] indices_23_read_reg_546; +wire [2:0] add_ln213_fu_268_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_state13_pp0_stage0_iter11; +wire ap_block_state14_pp0_stage0_iter12; +wire ap_block_state15_pp0_stage0_iter13; +wire ap_block_state16_pp0_stage0_iter14; +wire ap_block_state17_pp0_stage0_iter15; +wire ap_block_state18_pp0_stage0_iter16; +wire ap_block_state19_pp0_stage0_iter17; +wire ap_block_state20_pp0_stage0_iter18; +wire ap_block_state21_pp0_stage0_iter19; +wire ap_block_state22_pp0_stage0_iter20; +wire ap_block_state23_pp0_stage0_iter21; +wire ap_block_state24_pp0_stage0_iter22; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln213_fu_274_p2; +reg [0:0] icmp_ln213_reg_556; +reg [0:0] icmp_ln213_reg_556_pp0_iter1_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter2_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter3_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter4_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter5_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter6_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter7_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter8_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter9_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter10_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter11_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter12_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter13_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter14_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter15_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter16_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter17_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter18_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter19_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter20_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter21_reg; +wire [1:0] trunc_ln219_fu_280_p1; +reg [1:0] trunc_ln219_reg_560; +reg [1:0] trunc_ln219_reg_560_pp0_iter1_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter2_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter3_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter4_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter5_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter6_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter7_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter8_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter9_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter10_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter11_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter12_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter13_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter14_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter15_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter16_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter17_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter18_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter19_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter20_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter21_reg; +wire [0:0] write_flag_1_fu_296_p6; +wire [0:0] write_flag12_1_fu_310_p6; +wire [0:0] write_flag9_1_fu_324_p6; +wire [0:0] write_flag6_1_fu_338_p6; +wire [15:0] trunc_ln220_fu_352_p1; +reg [15:0] trunc_ln220_reg_593; +reg [15:0] tmp_184_i_i_reg_598; +reg [15:0] tmp_184_i_i_reg_598_pp0_iter2_reg; +reg [15:0] tmp_184_i_i_reg_598_pp0_iter3_reg; +reg [15:0] tmp_184_i_i_reg_598_pp0_iter4_reg; +reg [15:0] tmp_184_i_i_reg_598_pp0_iter5_reg; +reg [15:0] tmp_184_i_i_reg_598_pp0_iter6_reg; +reg [15:0] tmp_184_i_i_reg_598_pp0_iter7_reg; +reg [15:0] tmp_184_i_i_reg_598_pp0_iter8_reg; +reg [15:0] tmp_185_i_i_reg_603; +reg [15:0] tmp_185_i_i_reg_603_pp0_iter2_reg; +reg [15:0] tmp_185_i_i_reg_603_pp0_iter3_reg; +reg [15:0] tmp_185_i_i_reg_603_pp0_iter4_reg; +reg [15:0] tmp_185_i_i_reg_603_pp0_iter5_reg; +reg [15:0] tmp_185_i_i_reg_603_pp0_iter6_reg; +reg [15:0] tmp_185_i_i_reg_603_pp0_iter7_reg; +reg [15:0] tmp_185_i_i_reg_603_pp0_iter8_reg; +reg [15:0] tmp_185_i_i_reg_603_pp0_iter9_reg; +reg [15:0] tmp_185_i_i_reg_603_pp0_iter10_reg; +reg [15:0] tmp_185_i_i_reg_603_pp0_iter11_reg; +reg [15:0] tmp_185_i_i_reg_603_pp0_iter12_reg; +reg [15:0] tmp_185_i_i_reg_603_pp0_iter13_reg; +wire [15:0] val_in_assign_fu_376_p6; +reg [15:0] val_in_assign_reg_608; +wire [15:0] grp_fu_260_p2; +reg [15:0] sub_i_i_i_reg_618; +wire [15:0] grp_fu_264_p2; +reg [15:0] normalized_reg_628; +wire [15:0] grp_fu_256_p2; +reg [15:0] biased_reg_638; +wire [15:0] outputs_3_1_fu_446_p3; +reg ap_enable_reg_pp0_iter22; +wire [15:0] outputs_2_1_fu_454_p3; +wire [15:0] outputs_0_1_fu_478_p3; +wire [15:0] outputs_1_1_fu_494_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_condition_pp0_exit_iter21_state23; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln220_fu_291_p1; +wire [15:0] grp_fu_256_p1; +wire [15:0] grp_fu_260_p1; +wire [15:0] grp_fu_264_p1; +wire [6:0] ochan_fu_284_p3; +wire [15:0] data_V_fu_397_p1; +wire [0:0] p_Result_s_fu_400_p3; +wire [0:0] icmp_ln223_fu_415_p2; +wire [15:0] activated_fu_408_p3; +wire [0:0] icmp_ln223_7_fu_428_p2; +wire [15:0] select_ln223_fu_420_p3; +wire [0:0] icmp_ln223_8_fu_441_p2; +wire [15:0] select_ln223_13_fu_433_p3; +wire [15:0] select_ln223_14_fu_462_p3; +wire [15:0] select_ln223_15_fu_470_p3; +wire [15:0] select_ln223_16_fu_486_p3; +wire ap_CS_fsm_state25; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U598( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(normalized_reg_628), + .din1(grp_fu_256_p1), + .dout(grp_fu_256_p2) +); + +td_fused_top_hsub_16ns_16ns_16_7_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 7 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_7_full_dsp_1_U599( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(val_in_assign_reg_608), + .din1(grp_fu_260_p1), + .dout(grp_fu_260_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U600( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_618), + .din1(grp_fu_264_p1), + .dout(grp_fu_264_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U601( + .din0(1'd1), + .din1(write_flag_0_reg_186), + .din2(write_flag_0_reg_186), + .din3(write_flag_0_reg_186), + .din4(trunc_ln219_fu_280_p1), + .dout(write_flag_1_fu_296_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U602( + .din0(write_flag12_0_reg_175), + .din1(write_flag12_0_reg_175), + .din2(write_flag12_0_reg_175), + .din3(1'd1), + .din4(trunc_ln219_fu_280_p1), + .dout(write_flag12_1_fu_310_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U603( + .din0(write_flag9_0_reg_164), + .din1(write_flag9_0_reg_164), + .din2(1'd1), + .din3(write_flag9_0_reg_164), + .din4(trunc_ln219_fu_280_p1), + .dout(write_flag9_1_fu_324_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U604( + .din0(write_flag6_0_reg_153), + .din1(1'd1), + .din2(write_flag6_0_reg_153), + .din3(write_flag6_0_reg_153), + .din4(trunc_ln219_fu_280_p1), + .dout(write_flag6_1_fu_338_p6) +); + +td_fused_top_mux_42_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 16 )) +mux_42_16_1_1_U605( + .din0(sums_0_read), + .din1(sums_1_read), + .din2(sums_2_read), + .din3(sums_3_read), + .din4(trunc_ln219_reg_560), + .dout(val_in_assign_fu_376_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end else if ((((ap_enable_reg_pp0_iter20 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter21_state23) & (1'b0 == ap_block_pp0_stage0_subdone)) | (~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter21_state23) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter20; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + o_reg_197 <= add_ln213_fu_268_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + o_reg_197 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag12_0_reg_175 <= write_flag12_1_fu_310_p6; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag12_0_reg_175 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag6_0_reg_153 <= write_flag6_1_fu_338_p6; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_153 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag9_0_reg_164 <= write_flag9_1_fu_324_p6; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_164 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag_0_reg_186 <= write_flag_1_fu_296_p6; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_186 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_556_pp0_iter20_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + biased_reg_638 <= grp_fu_256_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln213_reg_556 <= icmp_ln213_fu_274_p2; + icmp_ln213_reg_556_pp0_iter1_reg <= icmp_ln213_reg_556; + trunc_ln219_reg_560_pp0_iter1_reg <= trunc_ln219_reg_560; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln213_reg_556_pp0_iter10_reg <= icmp_ln213_reg_556_pp0_iter9_reg; + icmp_ln213_reg_556_pp0_iter11_reg <= icmp_ln213_reg_556_pp0_iter10_reg; + icmp_ln213_reg_556_pp0_iter12_reg <= icmp_ln213_reg_556_pp0_iter11_reg; + icmp_ln213_reg_556_pp0_iter13_reg <= icmp_ln213_reg_556_pp0_iter12_reg; + icmp_ln213_reg_556_pp0_iter14_reg <= icmp_ln213_reg_556_pp0_iter13_reg; + icmp_ln213_reg_556_pp0_iter15_reg <= icmp_ln213_reg_556_pp0_iter14_reg; + icmp_ln213_reg_556_pp0_iter16_reg <= icmp_ln213_reg_556_pp0_iter15_reg; + icmp_ln213_reg_556_pp0_iter17_reg <= icmp_ln213_reg_556_pp0_iter16_reg; + icmp_ln213_reg_556_pp0_iter18_reg <= icmp_ln213_reg_556_pp0_iter17_reg; + icmp_ln213_reg_556_pp0_iter19_reg <= icmp_ln213_reg_556_pp0_iter18_reg; + icmp_ln213_reg_556_pp0_iter20_reg <= icmp_ln213_reg_556_pp0_iter19_reg; + icmp_ln213_reg_556_pp0_iter21_reg <= icmp_ln213_reg_556_pp0_iter20_reg; + icmp_ln213_reg_556_pp0_iter2_reg <= icmp_ln213_reg_556_pp0_iter1_reg; + icmp_ln213_reg_556_pp0_iter3_reg <= icmp_ln213_reg_556_pp0_iter2_reg; + icmp_ln213_reg_556_pp0_iter4_reg <= icmp_ln213_reg_556_pp0_iter3_reg; + icmp_ln213_reg_556_pp0_iter5_reg <= icmp_ln213_reg_556_pp0_iter4_reg; + icmp_ln213_reg_556_pp0_iter6_reg <= icmp_ln213_reg_556_pp0_iter5_reg; + icmp_ln213_reg_556_pp0_iter7_reg <= icmp_ln213_reg_556_pp0_iter6_reg; + icmp_ln213_reg_556_pp0_iter8_reg <= icmp_ln213_reg_556_pp0_iter7_reg; + icmp_ln213_reg_556_pp0_iter9_reg <= icmp_ln213_reg_556_pp0_iter8_reg; + tmp_184_i_i_reg_598_pp0_iter2_reg <= tmp_184_i_i_reg_598; + tmp_184_i_i_reg_598_pp0_iter3_reg <= tmp_184_i_i_reg_598_pp0_iter2_reg; + tmp_184_i_i_reg_598_pp0_iter4_reg <= tmp_184_i_i_reg_598_pp0_iter3_reg; + tmp_184_i_i_reg_598_pp0_iter5_reg <= tmp_184_i_i_reg_598_pp0_iter4_reg; + tmp_184_i_i_reg_598_pp0_iter6_reg <= tmp_184_i_i_reg_598_pp0_iter5_reg; + tmp_184_i_i_reg_598_pp0_iter7_reg <= tmp_184_i_i_reg_598_pp0_iter6_reg; + tmp_184_i_i_reg_598_pp0_iter8_reg <= tmp_184_i_i_reg_598_pp0_iter7_reg; + tmp_185_i_i_reg_603_pp0_iter10_reg <= tmp_185_i_i_reg_603_pp0_iter9_reg; + tmp_185_i_i_reg_603_pp0_iter11_reg <= tmp_185_i_i_reg_603_pp0_iter10_reg; + tmp_185_i_i_reg_603_pp0_iter12_reg <= tmp_185_i_i_reg_603_pp0_iter11_reg; + tmp_185_i_i_reg_603_pp0_iter13_reg <= tmp_185_i_i_reg_603_pp0_iter12_reg; + tmp_185_i_i_reg_603_pp0_iter2_reg <= tmp_185_i_i_reg_603; + tmp_185_i_i_reg_603_pp0_iter3_reg <= tmp_185_i_i_reg_603_pp0_iter2_reg; + tmp_185_i_i_reg_603_pp0_iter4_reg <= tmp_185_i_i_reg_603_pp0_iter3_reg; + tmp_185_i_i_reg_603_pp0_iter5_reg <= tmp_185_i_i_reg_603_pp0_iter4_reg; + tmp_185_i_i_reg_603_pp0_iter6_reg <= tmp_185_i_i_reg_603_pp0_iter5_reg; + tmp_185_i_i_reg_603_pp0_iter7_reg <= tmp_185_i_i_reg_603_pp0_iter6_reg; + tmp_185_i_i_reg_603_pp0_iter8_reg <= tmp_185_i_i_reg_603_pp0_iter7_reg; + tmp_185_i_i_reg_603_pp0_iter9_reg <= tmp_185_i_i_reg_603_pp0_iter8_reg; + trunc_ln219_reg_560_pp0_iter10_reg <= trunc_ln219_reg_560_pp0_iter9_reg; + trunc_ln219_reg_560_pp0_iter11_reg <= trunc_ln219_reg_560_pp0_iter10_reg; + trunc_ln219_reg_560_pp0_iter12_reg <= trunc_ln219_reg_560_pp0_iter11_reg; + trunc_ln219_reg_560_pp0_iter13_reg <= trunc_ln219_reg_560_pp0_iter12_reg; + trunc_ln219_reg_560_pp0_iter14_reg <= trunc_ln219_reg_560_pp0_iter13_reg; + trunc_ln219_reg_560_pp0_iter15_reg <= trunc_ln219_reg_560_pp0_iter14_reg; + trunc_ln219_reg_560_pp0_iter16_reg <= trunc_ln219_reg_560_pp0_iter15_reg; + trunc_ln219_reg_560_pp0_iter17_reg <= trunc_ln219_reg_560_pp0_iter16_reg; + trunc_ln219_reg_560_pp0_iter18_reg <= trunc_ln219_reg_560_pp0_iter17_reg; + trunc_ln219_reg_560_pp0_iter19_reg <= trunc_ln219_reg_560_pp0_iter18_reg; + trunc_ln219_reg_560_pp0_iter20_reg <= trunc_ln219_reg_560_pp0_iter19_reg; + trunc_ln219_reg_560_pp0_iter21_reg <= trunc_ln219_reg_560_pp0_iter20_reg; + trunc_ln219_reg_560_pp0_iter2_reg <= trunc_ln219_reg_560_pp0_iter1_reg; + trunc_ln219_reg_560_pp0_iter3_reg <= trunc_ln219_reg_560_pp0_iter2_reg; + trunc_ln219_reg_560_pp0_iter4_reg <= trunc_ln219_reg_560_pp0_iter3_reg; + trunc_ln219_reg_560_pp0_iter5_reg <= trunc_ln219_reg_560_pp0_iter4_reg; + trunc_ln219_reg_560_pp0_iter6_reg <= trunc_ln219_reg_560_pp0_iter5_reg; + trunc_ln219_reg_560_pp0_iter7_reg <= trunc_ln219_reg_560_pp0_iter6_reg; + trunc_ln219_reg_560_pp0_iter8_reg <= trunc_ln219_reg_560_pp0_iter7_reg; + trunc_ln219_reg_560_pp0_iter9_reg <= trunc_ln219_reg_560_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + indices_23_read_reg_546 <= indices_23_dout; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_556_pp0_iter12_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + normalized_reg_628 <= grp_fu_264_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter22 == 1'b1) & (icmp_ln213_reg_556_pp0_iter21_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + outputs_0_010_reg_220 <= outputs_0_1_fu_478_p3; + outputs_1_011_reg_208 <= outputs_1_1_fu_494_p3; + outputs_2_09_reg_232 <= outputs_2_1_fu_454_p3; + outputs_3_08_reg_244 <= outputs_3_1_fu_446_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_556_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sub_i_i_i_reg_618 <= grp_fu_260_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_reg_556 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + tmp_184_i_i_reg_598 <= {{adjustments_q0[31:16]}}; + tmp_185_i_i_reg_603 <= {{adjustments_q0[47:32]}}; + trunc_ln220_reg_593 <= trunc_ln220_fu_352_p1; + val_in_assign_reg_608 <= val_in_assign_fu_376_p6; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + trunc_ln219_reg_560 <= trunc_ln219_fu_280_p1; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0))) begin + ap_condition_pp0_exit_iter21_state23 = 1'b1; + end else begin + ap_condition_pp0_exit_iter21_state23 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_out_blk_n = indices_23_out_full_n; + end else begin + indices_23_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_out_write = 1'b1; + end else begin + indices_23_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state25; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state25 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign activated_fu_408_p3 = ((p_Result_s_fu_400_p3[0:0] == 1'b1) ? 16'd0 : biased_reg_638); + +assign add_ln213_fu_268_p2 = (o_reg_197 + 3'd1); + +assign adjustments_address0 = zext_ln220_fu_291_p1; + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state25 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = outputs_0_010_reg_220; + +assign ap_return_1 = outputs_1_011_reg_208; + +assign ap_return_2 = outputs_2_09_reg_232; + +assign ap_return_3 = outputs_3_08_reg_244; + +assign data_V_fu_397_p1 = biased_reg_638; + +assign grp_fu_256_p1 = tmp_185_i_i_reg_603_pp0_iter13_reg; + +assign grp_fu_260_p1 = trunc_ln220_reg_593; + +assign grp_fu_264_p1 = tmp_184_i_i_reg_598_pp0_iter8_reg; + +assign icmp_ln213_fu_274_p2 = ((o_reg_197 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln223_7_fu_428_p2 = ((trunc_ln219_reg_560_pp0_iter21_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln223_8_fu_441_p2 = ((trunc_ln219_reg_560_pp0_iter21_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln223_fu_415_p2 = ((trunc_ln219_reg_560_pp0_iter21_reg == 2'd0) ? 1'b1 : 1'b0); + +assign indices_23_out_din = indices_23_dout; + +assign ochan_fu_284_p3 = {{indices_23_read_reg_546}, {trunc_ln219_fu_280_p1}}; + +assign outputs_0_1_fu_478_p3 = ((icmp_ln223_8_fu_441_p2[0:0] == 1'b1) ? outputs_0_010_reg_220 : select_ln223_15_fu_470_p3); + +assign outputs_1_1_fu_494_p3 = ((icmp_ln223_8_fu_441_p2[0:0] == 1'b1) ? outputs_1_011_reg_208 : select_ln223_16_fu_486_p3); + +assign outputs_2_1_fu_454_p3 = ((icmp_ln223_8_fu_441_p2[0:0] == 1'b1) ? activated_fu_408_p3 : outputs_2_09_reg_232); + +assign outputs_3_1_fu_446_p3 = ((icmp_ln223_8_fu_441_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : select_ln223_13_fu_433_p3); + +assign p_Result_s_fu_400_p3 = data_V_fu_397_p1[32'd15]; + +assign select_ln223_13_fu_433_p3 = ((icmp_ln223_7_fu_428_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : select_ln223_fu_420_p3); + +assign select_ln223_14_fu_462_p3 = ((icmp_ln223_fu_415_p2[0:0] == 1'b1) ? activated_fu_408_p3 : outputs_0_010_reg_220); + +assign select_ln223_15_fu_470_p3 = ((icmp_ln223_7_fu_428_p2[0:0] == 1'b1) ? outputs_0_010_reg_220 : select_ln223_14_fu_462_p3); + +assign select_ln223_16_fu_486_p3 = ((icmp_ln223_7_fu_428_p2[0:0] == 1'b1) ? activated_fu_408_p3 : outputs_1_011_reg_208); + +assign select_ln223_fu_420_p3 = ((icmp_ln223_fu_415_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : activated_fu_408_p3); + +assign trunc_ln219_fu_280_p1 = o_reg_197[1:0]; + +assign trunc_ln220_fu_352_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_291_p1 = ochan_fu_284_p3; + +endmodule //td_fused_top_tdf4_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_0_address0, + ifmap_vec_0_ce0, + ifmap_vec_0_q0, + ifmap_vec_1_address0, + ifmap_vec_1_ce0, + ifmap_vec_1_q0, + ifmap_vec_2_address0, + ifmap_vec_2_ce0, + ifmap_vec_2_q0, + ifmap_vec_3_address0, + ifmap_vec_3_ce0, + ifmap_vec_3_q0, + weight_vecs_0_0_address0, + weight_vecs_0_0_ce0, + weight_vecs_0_0_q0, + weight_vecs_0_1_address0, + weight_vecs_0_1_ce0, + weight_vecs_0_1_q0, + weight_vecs_0_2_address0, + weight_vecs_0_2_ce0, + weight_vecs_0_2_q0, + weight_vecs_0_3_address0, + weight_vecs_0_3_ce0, + weight_vecs_0_3_q0, + weight_vecs_1_0_address0, + weight_vecs_1_0_ce0, + weight_vecs_1_0_q0, + weight_vecs_1_1_address0, + weight_vecs_1_1_ce0, + weight_vecs_1_1_q0, + weight_vecs_1_2_address0, + weight_vecs_1_2_ce0, + weight_vecs_1_2_q0, + weight_vecs_1_3_address0, + weight_vecs_1_3_ce0, + weight_vecs_1_3_q0, + weight_vecs_2_0_address0, + weight_vecs_2_0_ce0, + weight_vecs_2_0_q0, + weight_vecs_2_1_address0, + weight_vecs_2_1_ce0, + weight_vecs_2_1_q0, + weight_vecs_2_2_address0, + weight_vecs_2_2_ce0, + weight_vecs_2_2_q0, + weight_vecs_2_3_address0, + weight_vecs_2_3_ce0, + weight_vecs_2_3_q0, + weight_vecs_3_0_address0, + weight_vecs_3_0_ce0, + weight_vecs_3_0_q0, + weight_vecs_3_1_address0, + weight_vecs_3_1_ce0, + weight_vecs_3_1_q0, + weight_vecs_3_2_address0, + weight_vecs_3_2_ce0, + weight_vecs_3_2_q0, + weight_vecs_3_3_address0, + weight_vecs_3_3_ce0, + weight_vecs_3_3_q0, + products_0_0_address0, + products_0_0_ce0, + products_0_0_we0, + products_0_0_d0, + products_0_1_address0, + products_0_1_ce0, + products_0_1_we0, + products_0_1_d0, + products_0_2_address0, + products_0_2_ce0, + products_0_2_we0, + products_0_2_d0, + products_0_3_address0, + products_0_3_ce0, + products_0_3_we0, + products_0_3_d0, + products_1_0_address0, + products_1_0_ce0, + products_1_0_we0, + products_1_0_d0, + products_1_1_address0, + products_1_1_ce0, + products_1_1_we0, + products_1_1_d0, + products_1_2_address0, + products_1_2_ce0, + products_1_2_we0, + products_1_2_d0, + products_1_3_address0, + products_1_3_ce0, + products_1_3_we0, + products_1_3_d0, + products_2_0_address0, + products_2_0_ce0, + products_2_0_we0, + products_2_0_d0, + products_2_1_address0, + products_2_1_ce0, + products_2_1_we0, + products_2_1_d0, + products_2_2_address0, + products_2_2_ce0, + products_2_2_we0, + products_2_2_d0, + products_2_3_address0, + products_2_3_ce0, + products_2_3_we0, + products_2_3_d0, + products_3_0_address0, + products_3_0_ce0, + products_3_0_we0, + products_3_0_d0, + products_3_1_address0, + products_3_1_ce0, + products_3_1_we0, + products_3_1_d0, + products_3_2_address0, + products_3_2_ce0, + products_3_2_we0, + products_3_2_d0, + products_3_3_address0, + products_3_3_ce0, + products_3_3_we0, + products_3_3_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state11 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [5:0] ifmap_vec_0_address0; +output ifmap_vec_0_ce0; +input [15:0] ifmap_vec_0_q0; +output [5:0] ifmap_vec_1_address0; +output ifmap_vec_1_ce0; +input [15:0] ifmap_vec_1_q0; +output [5:0] ifmap_vec_2_address0; +output ifmap_vec_2_ce0; +input [15:0] ifmap_vec_2_q0; +output [5:0] ifmap_vec_3_address0; +output ifmap_vec_3_ce0; +input [15:0] ifmap_vec_3_q0; +output [5:0] weight_vecs_0_0_address0; +output weight_vecs_0_0_ce0; +input [15:0] weight_vecs_0_0_q0; +output [5:0] weight_vecs_0_1_address0; +output weight_vecs_0_1_ce0; +input [15:0] weight_vecs_0_1_q0; +output [5:0] weight_vecs_0_2_address0; +output weight_vecs_0_2_ce0; +input [15:0] weight_vecs_0_2_q0; +output [5:0] weight_vecs_0_3_address0; +output weight_vecs_0_3_ce0; +input [15:0] weight_vecs_0_3_q0; +output [5:0] weight_vecs_1_0_address0; +output weight_vecs_1_0_ce0; +input [15:0] weight_vecs_1_0_q0; +output [5:0] weight_vecs_1_1_address0; +output weight_vecs_1_1_ce0; +input [15:0] weight_vecs_1_1_q0; +output [5:0] weight_vecs_1_2_address0; +output weight_vecs_1_2_ce0; +input [15:0] weight_vecs_1_2_q0; +output [5:0] weight_vecs_1_3_address0; +output weight_vecs_1_3_ce0; +input [15:0] weight_vecs_1_3_q0; +output [5:0] weight_vecs_2_0_address0; +output weight_vecs_2_0_ce0; +input [15:0] weight_vecs_2_0_q0; +output [5:0] weight_vecs_2_1_address0; +output weight_vecs_2_1_ce0; +input [15:0] weight_vecs_2_1_q0; +output [5:0] weight_vecs_2_2_address0; +output weight_vecs_2_2_ce0; +input [15:0] weight_vecs_2_2_q0; +output [5:0] weight_vecs_2_3_address0; +output weight_vecs_2_3_ce0; +input [15:0] weight_vecs_2_3_q0; +output [5:0] weight_vecs_3_0_address0; +output weight_vecs_3_0_ce0; +input [15:0] weight_vecs_3_0_q0; +output [5:0] weight_vecs_3_1_address0; +output weight_vecs_3_1_ce0; +input [15:0] weight_vecs_3_1_q0; +output [5:0] weight_vecs_3_2_address0; +output weight_vecs_3_2_ce0; +input [15:0] weight_vecs_3_2_q0; +output [5:0] weight_vecs_3_3_address0; +output weight_vecs_3_3_ce0; +input [15:0] weight_vecs_3_3_q0; +output [5:0] products_0_0_address0; +output products_0_0_ce0; +output products_0_0_we0; +output [15:0] products_0_0_d0; +output [5:0] products_0_1_address0; +output products_0_1_ce0; +output products_0_1_we0; +output [15:0] products_0_1_d0; +output [5:0] products_0_2_address0; +output products_0_2_ce0; +output products_0_2_we0; +output [15:0] products_0_2_d0; +output [5:0] products_0_3_address0; +output products_0_3_ce0; +output products_0_3_we0; +output [15:0] products_0_3_d0; +output [5:0] products_1_0_address0; +output products_1_0_ce0; +output products_1_0_we0; +output [15:0] products_1_0_d0; +output [5:0] products_1_1_address0; +output products_1_1_ce0; +output products_1_1_we0; +output [15:0] products_1_1_d0; +output [5:0] products_1_2_address0; +output products_1_2_ce0; +output products_1_2_we0; +output [15:0] products_1_2_d0; +output [5:0] products_1_3_address0; +output products_1_3_ce0; +output products_1_3_we0; +output [15:0] products_1_3_d0; +output [5:0] products_2_0_address0; +output products_2_0_ce0; +output products_2_0_we0; +output [15:0] products_2_0_d0; +output [5:0] products_2_1_address0; +output products_2_1_ce0; +output products_2_1_we0; +output [15:0] products_2_1_d0; +output [5:0] products_2_2_address0; +output products_2_2_ce0; +output products_2_2_we0; +output [15:0] products_2_2_d0; +output [5:0] products_2_3_address0; +output products_2_3_ce0; +output products_2_3_we0; +output [15:0] products_2_3_d0; +output [5:0] products_3_0_address0; +output products_3_0_ce0; +output products_3_0_we0; +output [15:0] products_3_0_d0; +output [5:0] products_3_1_address0; +output products_3_1_ce0; +output products_3_1_we0; +output [15:0] products_3_1_d0; +output [5:0] products_3_2_address0; +output products_3_2_ce0; +output products_3_2_we0; +output [15:0] products_3_2_d0; +output [5:0] products_3_3_address0; +output products_3_3_ce0; +output products_3_3_we0; +output [15:0] products_3_3_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_0_ce0; +reg ifmap_vec_1_ce0; +reg ifmap_vec_2_ce0; +reg ifmap_vec_3_ce0; +reg weight_vecs_0_0_ce0; +reg weight_vecs_0_1_ce0; +reg weight_vecs_0_2_ce0; +reg weight_vecs_0_3_ce0; +reg weight_vecs_1_0_ce0; +reg weight_vecs_1_1_ce0; +reg weight_vecs_1_2_ce0; +reg weight_vecs_1_3_ce0; +reg weight_vecs_2_0_ce0; +reg weight_vecs_2_1_ce0; +reg weight_vecs_2_2_ce0; +reg weight_vecs_2_3_ce0; +reg weight_vecs_3_0_ce0; +reg weight_vecs_3_1_ce0; +reg weight_vecs_3_2_ce0; +reg weight_vecs_3_3_ce0; +reg products_0_0_ce0; +reg products_0_0_we0; +reg products_0_1_ce0; +reg products_0_1_we0; +reg products_0_2_ce0; +reg products_0_2_we0; +reg products_0_3_ce0; +reg products_0_3_we0; +reg products_1_0_ce0; +reg products_1_0_we0; +reg products_1_1_ce0; +reg products_1_1_we0; +reg products_1_2_ce0; +reg products_1_2_we0; +reg products_1_3_ce0; +reg products_1_3_we0; +reg products_2_0_ce0; +reg products_2_0_we0; +reg products_2_1_ce0; +reg products_2_1_we0; +reg products_2_2_ce0; +reg products_2_2_we0; +reg products_2_3_ce0; +reg products_2_3_we0; +reg products_3_0_ce0; +reg products_3_0_we0; +reg products_3_1_ce0; +reg products_3_1_we0; +reg products_3_2_ce0; +reg products_3_2_we0; +reg products_3_3_ce0; +reg products_3_3_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [5:0] indvar_flatten17_reg_606; +reg [1:0] ii_reg_617; +reg [4:0] indvar_flatten_reg_629; +reg [1:0] jj_reg_640; +reg [4:0] ic_reg_651; +wire [5:0] add_ln147_4_fu_726_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln147_fu_732_p2; +reg [0:0] icmp_ln147_reg_1098; +reg [0:0] icmp_ln147_reg_1098_pp0_iter1_reg; +reg [0:0] icmp_ln147_reg_1098_pp0_iter2_reg; +reg [0:0] icmp_ln147_reg_1098_pp0_iter3_reg; +reg [0:0] icmp_ln147_reg_1098_pp0_iter4_reg; +reg [0:0] icmp_ln147_reg_1098_pp0_iter5_reg; +reg [0:0] icmp_ln147_reg_1098_pp0_iter6_reg; +reg [0:0] icmp_ln147_reg_1098_pp0_iter7_reg; +wire [1:0] add_ln147_fu_738_p2; +reg [1:0] add_ln147_reg_1102; +wire [0:0] icmp_ln148_fu_744_p2; +reg [0:0] icmp_ln148_reg_1108; +wire [1:0] select_ln147_15_fu_750_p3; +reg [1:0] select_ln147_15_reg_1117; +wire [4:0] select_ln148_12_fu_764_p3; +wire [1:0] select_ln148_10_fu_901_p3; +reg [1:0] select_ln148_10_reg_1129; +reg ap_enable_reg_pp0_iter1; +wire [3:0] select_ln148_11_fu_929_p3; +reg [3:0] select_ln148_11_reg_1134; +reg [3:0] select_ln148_11_reg_1134_pp0_iter2_reg; +reg [3:0] select_ln148_11_reg_1134_pp0_iter3_reg; +reg [3:0] select_ln148_11_reg_1134_pp0_iter4_reg; +reg [3:0] select_ln148_11_reg_1134_pp0_iter5_reg; +reg [3:0] select_ln148_11_reg_1134_pp0_iter6_reg; +reg [3:0] select_ln148_11_reg_1134_pp0_iter7_reg; +wire [3:0] trunc_ln149_fu_937_p1; +reg [3:0] trunc_ln149_reg_1142; +reg [3:0] trunc_ln149_reg_1142_pp0_iter2_reg; +reg [3:0] trunc_ln149_reg_1142_pp0_iter3_reg; +reg [3:0] trunc_ln149_reg_1142_pp0_iter4_reg; +reg [3:0] trunc_ln149_reg_1142_pp0_iter5_reg; +reg [3:0] trunc_ln149_reg_1142_pp0_iter6_reg; +reg [3:0] trunc_ln149_reg_1142_pp0_iter7_reg; +wire [1:0] newIndex_fu_941_p4; +reg [1:0] newIndex_reg_1149; +reg [1:0] newIndex_reg_1149_pp0_iter2_reg; +reg [1:0] newIndex_reg_1149_pp0_iter3_reg; +reg [1:0] newIndex_reg_1149_pp0_iter4_reg; +reg [1:0] newIndex_reg_1149_pp0_iter5_reg; +reg [1:0] newIndex_reg_1149_pp0_iter6_reg; +reg [1:0] newIndex_reg_1149_pp0_iter7_reg; +wire [4:0] add_ln149_fu_983_p2; +reg [15:0] ifmap_vec_0_load_reg_1259; +reg [15:0] weight_vecs_0_0_load_reg_1267; +reg [15:0] weight_vecs_1_0_load_reg_1272; +reg [15:0] weight_vecs_2_0_load_reg_1277; +reg [15:0] weight_vecs_3_0_load_reg_1282; +reg [15:0] ifmap_vec_1_load_reg_1287; +reg [15:0] weight_vecs_0_1_load_reg_1295; +reg [15:0] weight_vecs_1_1_load_reg_1300; +reg [15:0] weight_vecs_2_1_load_reg_1305; +reg [15:0] weight_vecs_3_1_load_reg_1310; +reg [15:0] ifmap_vec_2_load_reg_1315; +reg [15:0] weight_vecs_0_2_load_reg_1323; +reg [15:0] weight_vecs_1_2_load_reg_1328; +reg [15:0] weight_vecs_2_2_load_reg_1333; +reg [15:0] weight_vecs_3_2_load_reg_1338; +reg [15:0] ifmap_vec_3_load_reg_1343; +reg [15:0] weight_vecs_0_3_load_reg_1351; +reg [15:0] weight_vecs_1_3_load_reg_1356; +reg [15:0] weight_vecs_2_3_load_reg_1361; +reg [15:0] weight_vecs_3_3_load_reg_1366; +wire [15:0] grp_fu_662_p2; +reg [15:0] mul_reg_1371; +wire [15:0] grp_fu_666_p2; +reg [15:0] mul_1_reg_1376; +wire [15:0] grp_fu_670_p2; +reg [15:0] mul_2_reg_1381; +wire [15:0] grp_fu_674_p2; +reg [15:0] mul_3_reg_1386; +wire [15:0] grp_fu_678_p2; +reg [15:0] mul27_1_reg_1391; +wire [15:0] grp_fu_682_p2; +reg [15:0] mul27_1_1_reg_1396; +wire [15:0] grp_fu_686_p2; +reg [15:0] mul27_1_2_reg_1401; +wire [15:0] grp_fu_690_p2; +reg [15:0] mul27_1_3_reg_1406; +wire [15:0] grp_fu_694_p2; +reg [15:0] mul27_2_reg_1411; +wire [15:0] grp_fu_698_p2; +reg [15:0] mul27_2_1_reg_1416; +wire [15:0] grp_fu_702_p2; +reg [15:0] mul27_2_2_reg_1421; +wire [15:0] grp_fu_706_p2; +reg [15:0] mul27_2_3_reg_1426; +wire [15:0] grp_fu_710_p2; +reg [15:0] mul27_3_reg_1431; +wire [15:0] grp_fu_714_p2; +reg [15:0] mul27_3_1_reg_1436; +wire [15:0] grp_fu_718_p2; +reg [15:0] mul27_3_2_reg_1441; +wire [15:0] grp_fu_722_p2; +reg [15:0] mul27_3_3_reg_1446; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg [1:0] ap_phi_mux_ii_phi_fu_621_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_644_p4; +wire [63:0] tmp_115_fu_959_p1; +wire [63:0] zext_ln153_fu_995_p1; +wire [63:0] zext_ln153_6_fu_1025_p1; +wire [63:0] zext_ln153_7_fu_1055_p1; +wire [63:0] zext_ln153_8_fu_1085_p1; +wire [4:0] add_ln148_4_fu_758_p2; +wire [3:0] shl_ln_fu_776_p3; +wire [3:0] zext_ln150_fu_772_p1; +wire [3:0] sub_ln150_fu_784_p2; +wire [3:0] zext_ln150_4_fu_790_p1; +wire [3:0] tmp_fu_817_p3; +wire [4:0] tmp_cast_fu_824_p1; +wire [4:0] select_ln147_18_cast_fu_814_p1; +wire [4:0] empty_111_fu_828_p2; +wire [3:0] shl_ln150_mid1_fu_841_p3; +wire [3:0] zext_ln150_8_fu_838_p1; +wire [3:0] sub_ln150_4_fu_848_p2; +wire [3:0] add_ln150_fu_794_p2; +wire [0:0] tmp_57_fu_868_p3; +wire [0:0] xor_ln149_fu_876_p2; +wire [1:0] select_ln147_fu_800_p3; +wire [0:0] or_ln147_fu_882_p2; +wire [4:0] select_ln147_14_fu_807_p3; +wire [1:0] add_ln148_fu_887_p2; +wire [5:0] sext_ln150_fu_834_p1; +wire [5:0] select_ln148_13_cast_fu_909_p1; +wire [3:0] select_ln147_16_fu_854_p3; +wire [3:0] zext_ln150_9_fu_919_p1; +wire [3:0] select_ln147_17_fu_861_p3; +wire [3:0] add_ln150_4_fu_923_p2; +wire [4:0] select_ln148_fu_893_p3; +wire [5:0] empty_112_fu_913_p2; +wire [7:0] tmp_58_fu_951_p3; +wire [5:0] lshr_ln_fu_989_p3; +wire [3:0] or_ln150_fu_1003_p2; +wire [1:0] tmp_s_fu_1008_p4; +wire [5:0] lshr_ln153_6_fu_1018_p3; +wire [3:0] or_ln150_3_fu_1033_p2; +wire [1:0] tmp_36_fu_1038_p4; +wire [5:0] lshr_ln153_7_fu_1048_p3; +wire [3:0] or_ln150_4_fu_1063_p2; +wire [1:0] tmp_37_fu_1068_p4; +wire [5:0] lshr_ln153_8_fu_1078_p3; +wire ap_CS_fsm_state11; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U476( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_1259), + .din1(weight_vecs_0_0_load_reg_1267), + .dout(grp_fu_662_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U477( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_1259), + .din1(weight_vecs_1_0_load_reg_1272), + .dout(grp_fu_666_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U478( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_1259), + .din1(weight_vecs_2_0_load_reg_1277), + .dout(grp_fu_670_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U479( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_1259), + .din1(weight_vecs_3_0_load_reg_1282), + .dout(grp_fu_674_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U480( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_1287), + .din1(weight_vecs_0_1_load_reg_1295), + .dout(grp_fu_678_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U481( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_1287), + .din1(weight_vecs_1_1_load_reg_1300), + .dout(grp_fu_682_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U482( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_1287), + .din1(weight_vecs_2_1_load_reg_1305), + .dout(grp_fu_686_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U483( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_1287), + .din1(weight_vecs_3_1_load_reg_1310), + .dout(grp_fu_690_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U484( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_2_load_reg_1315), + .din1(weight_vecs_0_2_load_reg_1323), + .dout(grp_fu_694_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U485( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_2_load_reg_1315), + .din1(weight_vecs_1_2_load_reg_1328), + .dout(grp_fu_698_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U486( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_2_load_reg_1315), + .din1(weight_vecs_2_2_load_reg_1333), + .dout(grp_fu_702_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U487( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_2_load_reg_1315), + .din1(weight_vecs_3_2_load_reg_1338), + .dout(grp_fu_706_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U488( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_3_load_reg_1343), + .din1(weight_vecs_0_3_load_reg_1351), + .dout(grp_fu_710_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U489( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_3_load_reg_1343), + .din1(weight_vecs_1_3_load_reg_1356), + .dout(grp_fu_714_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U490( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_3_load_reg_1343), + .din1(weight_vecs_2_3_load_reg_1361), + .dout(grp_fu_718_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U491( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_3_load_reg_1343), + .din1(weight_vecs_3_3_load_reg_1366), + .dout(grp_fu_722_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_1098 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_reg_651 <= add_ln149_fu_983_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_reg_651 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_1098 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ii_reg_617 <= select_ln147_15_reg_1117; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_617 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_732_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten17_reg_606 <= add_ln147_4_fu_726_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten17_reg_606 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_732_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_629 <= select_ln148_12_fu_764_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_629 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_640 <= select_ln148_10_reg_1129; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_640 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_732_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln147_reg_1102 <= add_ln147_fu_738_p2; + icmp_ln148_reg_1108 <= icmp_ln148_fu_744_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln147_reg_1098 <= icmp_ln147_fu_732_p2; + icmp_ln147_reg_1098_pp0_iter1_reg <= icmp_ln147_reg_1098; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln147_reg_1098_pp0_iter2_reg <= icmp_ln147_reg_1098_pp0_iter1_reg; + icmp_ln147_reg_1098_pp0_iter3_reg <= icmp_ln147_reg_1098_pp0_iter2_reg; + icmp_ln147_reg_1098_pp0_iter4_reg <= icmp_ln147_reg_1098_pp0_iter3_reg; + icmp_ln147_reg_1098_pp0_iter5_reg <= icmp_ln147_reg_1098_pp0_iter4_reg; + icmp_ln147_reg_1098_pp0_iter6_reg <= icmp_ln147_reg_1098_pp0_iter5_reg; + icmp_ln147_reg_1098_pp0_iter7_reg <= icmp_ln147_reg_1098_pp0_iter6_reg; + newIndex_reg_1149_pp0_iter2_reg <= newIndex_reg_1149; + newIndex_reg_1149_pp0_iter3_reg <= newIndex_reg_1149_pp0_iter2_reg; + newIndex_reg_1149_pp0_iter4_reg <= newIndex_reg_1149_pp0_iter3_reg; + newIndex_reg_1149_pp0_iter5_reg <= newIndex_reg_1149_pp0_iter4_reg; + newIndex_reg_1149_pp0_iter6_reg <= newIndex_reg_1149_pp0_iter5_reg; + newIndex_reg_1149_pp0_iter7_reg <= newIndex_reg_1149_pp0_iter6_reg; + select_ln148_11_reg_1134_pp0_iter2_reg <= select_ln148_11_reg_1134; + select_ln148_11_reg_1134_pp0_iter3_reg <= select_ln148_11_reg_1134_pp0_iter2_reg; + select_ln148_11_reg_1134_pp0_iter4_reg <= select_ln148_11_reg_1134_pp0_iter3_reg; + select_ln148_11_reg_1134_pp0_iter5_reg <= select_ln148_11_reg_1134_pp0_iter4_reg; + select_ln148_11_reg_1134_pp0_iter6_reg <= select_ln148_11_reg_1134_pp0_iter5_reg; + select_ln148_11_reg_1134_pp0_iter7_reg <= select_ln148_11_reg_1134_pp0_iter6_reg; + trunc_ln149_reg_1142_pp0_iter2_reg <= trunc_ln149_reg_1142; + trunc_ln149_reg_1142_pp0_iter3_reg <= trunc_ln149_reg_1142_pp0_iter2_reg; + trunc_ln149_reg_1142_pp0_iter4_reg <= trunc_ln149_reg_1142_pp0_iter3_reg; + trunc_ln149_reg_1142_pp0_iter5_reg <= trunc_ln149_reg_1142_pp0_iter4_reg; + trunc_ln149_reg_1142_pp0_iter6_reg <= trunc_ln149_reg_1142_pp0_iter5_reg; + trunc_ln149_reg_1142_pp0_iter7_reg <= trunc_ln149_reg_1142_pp0_iter6_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_1098_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_load_reg_1259 <= ifmap_vec_0_q0; + ifmap_vec_1_load_reg_1287 <= ifmap_vec_1_q0; + ifmap_vec_2_load_reg_1315 <= ifmap_vec_2_q0; + ifmap_vec_3_load_reg_1343 <= ifmap_vec_3_q0; + weight_vecs_0_0_load_reg_1267 <= weight_vecs_0_0_q0; + weight_vecs_0_1_load_reg_1295 <= weight_vecs_0_1_q0; + weight_vecs_0_2_load_reg_1323 <= weight_vecs_0_2_q0; + weight_vecs_0_3_load_reg_1351 <= weight_vecs_0_3_q0; + weight_vecs_1_0_load_reg_1272 <= weight_vecs_1_0_q0; + weight_vecs_1_1_load_reg_1300 <= weight_vecs_1_1_q0; + weight_vecs_1_2_load_reg_1328 <= weight_vecs_1_2_q0; + weight_vecs_1_3_load_reg_1356 <= weight_vecs_1_3_q0; + weight_vecs_2_0_load_reg_1277 <= weight_vecs_2_0_q0; + weight_vecs_2_1_load_reg_1305 <= weight_vecs_2_1_q0; + weight_vecs_2_2_load_reg_1333 <= weight_vecs_2_2_q0; + weight_vecs_2_3_load_reg_1361 <= weight_vecs_2_3_q0; + weight_vecs_3_0_load_reg_1282 <= weight_vecs_3_0_q0; + weight_vecs_3_1_load_reg_1310 <= weight_vecs_3_1_q0; + weight_vecs_3_2_load_reg_1338 <= weight_vecs_3_2_q0; + weight_vecs_3_3_load_reg_1366 <= weight_vecs_3_3_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_1098_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul27_1_1_reg_1396 <= grp_fu_682_p2; + mul27_1_2_reg_1401 <= grp_fu_686_p2; + mul27_1_3_reg_1406 <= grp_fu_690_p2; + mul27_1_reg_1391 <= grp_fu_678_p2; + mul27_2_1_reg_1416 <= grp_fu_698_p2; + mul27_2_2_reg_1421 <= grp_fu_702_p2; + mul27_2_3_reg_1426 <= grp_fu_706_p2; + mul27_2_reg_1411 <= grp_fu_694_p2; + mul27_3_1_reg_1436 <= grp_fu_714_p2; + mul27_3_2_reg_1441 <= grp_fu_718_p2; + mul27_3_3_reg_1446 <= grp_fu_722_p2; + mul27_3_reg_1431 <= grp_fu_710_p2; + mul_1_reg_1376 <= grp_fu_666_p2; + mul_2_reg_1381 <= grp_fu_670_p2; + mul_3_reg_1386 <= grp_fu_674_p2; + mul_reg_1371 <= grp_fu_662_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_1098 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + newIndex_reg_1149 <= {{select_ln148_fu_893_p3[3:2]}}; + select_ln148_11_reg_1134 <= select_ln148_11_fu_929_p3; + trunc_ln149_reg_1142 <= trunc_ln149_fu_937_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_732_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln147_15_reg_1117 <= select_ln147_15_fu_750_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_1098 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_10_reg_1129 <= select_ln148_10_fu_901_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_fu_732_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_1098 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_621_p4 = select_ln147_15_reg_1117; + end else begin + ap_phi_mux_ii_phi_fu_621_p4 = ii_reg_617; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_644_p4 = select_ln148_10_reg_1129; + end else begin + ap_phi_mux_jj_phi_fu_644_p4 = jj_reg_640; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_1_ce0 = 1'b1; + end else begin + ifmap_vec_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_2_ce0 = 1'b1; + end else begin + ifmap_vec_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_3_ce0 = 1'b1; + end else begin + ifmap_vec_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_0_ce0 = 1'b1; + end else begin + products_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_0_we0 = 1'b1; + end else begin + products_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_1_ce0 = 1'b1; + end else begin + products_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_1_we0 = 1'b1; + end else begin + products_0_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_2_ce0 = 1'b1; + end else begin + products_0_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_2_we0 = 1'b1; + end else begin + products_0_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_3_ce0 = 1'b1; + end else begin + products_0_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_3_we0 = 1'b1; + end else begin + products_0_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_0_ce0 = 1'b1; + end else begin + products_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_0_we0 = 1'b1; + end else begin + products_1_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_1_ce0 = 1'b1; + end else begin + products_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_1_we0 = 1'b1; + end else begin + products_1_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_2_ce0 = 1'b1; + end else begin + products_1_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_2_we0 = 1'b1; + end else begin + products_1_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_3_ce0 = 1'b1; + end else begin + products_1_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_3_we0 = 1'b1; + end else begin + products_1_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_0_ce0 = 1'b1; + end else begin + products_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_0_we0 = 1'b1; + end else begin + products_2_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_1_ce0 = 1'b1; + end else begin + products_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_1_we0 = 1'b1; + end else begin + products_2_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_2_ce0 = 1'b1; + end else begin + products_2_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_2_we0 = 1'b1; + end else begin + products_2_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_3_ce0 = 1'b1; + end else begin + products_2_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_3_we0 = 1'b1; + end else begin + products_2_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_0_ce0 = 1'b1; + end else begin + products_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_0_we0 = 1'b1; + end else begin + products_3_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_1_ce0 = 1'b1; + end else begin + products_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_1_we0 = 1'b1; + end else begin + products_3_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_2_ce0 = 1'b1; + end else begin + products_3_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_2_we0 = 1'b1; + end else begin + products_3_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_3_ce0 = 1'b1; + end else begin + products_3_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1098_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_3_we0 = 1'b1; + end else begin + products_3_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_1_ce0 = 1'b1; + end else begin + weight_vecs_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_2_ce0 = 1'b1; + end else begin + weight_vecs_0_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_3_ce0 = 1'b1; + end else begin + weight_vecs_0_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_1_0_ce0 = 1'b1; + end else begin + weight_vecs_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_1_1_ce0 = 1'b1; + end else begin + weight_vecs_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_1_2_ce0 = 1'b1; + end else begin + weight_vecs_1_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_1_3_ce0 = 1'b1; + end else begin + weight_vecs_1_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_2_0_ce0 = 1'b1; + end else begin + weight_vecs_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_2_1_ce0 = 1'b1; + end else begin + weight_vecs_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_2_2_ce0 = 1'b1; + end else begin + weight_vecs_2_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_2_3_ce0 = 1'b1; + end else begin + weight_vecs_2_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_3_0_ce0 = 1'b1; + end else begin + weight_vecs_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_3_1_ce0 = 1'b1; + end else begin + weight_vecs_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_3_2_ce0 = 1'b1; + end else begin + weight_vecs_3_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_3_3_ce0 = 1'b1; + end else begin + weight_vecs_3_3_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0)) & ~((ap_enable_reg_pp0_iter8 == 1'b1) & (ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter8 == 1'b1) & (ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin + ap_NS_fsm = ap_ST_fsm_state11; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_4_fu_726_p2 = (indvar_flatten17_reg_606 + 6'd1); + +assign add_ln147_fu_738_p2 = (ap_phi_mux_ii_phi_fu_621_p4 + 2'd1); + +assign add_ln148_4_fu_758_p2 = (indvar_flatten_reg_629 + 5'd1); + +assign add_ln148_fu_887_p2 = (select_ln147_fu_800_p3 + 2'd1); + +assign add_ln149_fu_983_p2 = (select_ln148_fu_893_p3 + 5'd4); + +assign add_ln150_4_fu_923_p2 = (select_ln147_16_fu_854_p3 + zext_ln150_9_fu_919_p1); + +assign add_ln150_fu_794_p2 = (sub_ln150_fu_784_p2 + zext_ln150_4_fu_790_p1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign empty_111_fu_828_p2 = (tmp_cast_fu_824_p1 - select_ln147_18_cast_fu_814_p1); + +assign empty_112_fu_913_p2 = ((sext_ln150_fu_834_p1) + (select_ln148_13_cast_fu_909_p1)); + +assign icmp_ln147_fu_732_p2 = ((indvar_flatten17_reg_606 == 6'd36) ? 1'b1 : 1'b0); + +assign icmp_ln148_fu_744_p2 = ((indvar_flatten_reg_629 == 5'd12) ? 1'b1 : 1'b0); + +assign ifmap_vec_0_address0 = tmp_115_fu_959_p1; + +assign ifmap_vec_1_address0 = tmp_115_fu_959_p1; + +assign ifmap_vec_2_address0 = tmp_115_fu_959_p1; + +assign ifmap_vec_3_address0 = tmp_115_fu_959_p1; + +assign lshr_ln153_6_fu_1018_p3 = {{select_ln148_11_reg_1134_pp0_iter7_reg}, {tmp_s_fu_1008_p4}}; + +assign lshr_ln153_7_fu_1048_p3 = {{select_ln148_11_reg_1134_pp0_iter7_reg}, {tmp_36_fu_1038_p4}}; + +assign lshr_ln153_8_fu_1078_p3 = {{select_ln148_11_reg_1134_pp0_iter7_reg}, {tmp_37_fu_1068_p4}}; + +assign lshr_ln_fu_989_p3 = {{select_ln148_11_reg_1134_pp0_iter7_reg}, {newIndex_reg_1149_pp0_iter7_reg}}; + +assign newIndex_fu_941_p4 = {{select_ln148_fu_893_p3[3:2]}}; + +assign or_ln147_fu_882_p2 = (xor_ln149_fu_876_p2 | icmp_ln148_reg_1108); + +assign or_ln150_3_fu_1033_p2 = (trunc_ln149_reg_1142_pp0_iter7_reg | 4'd2); + +assign or_ln150_4_fu_1063_p2 = (trunc_ln149_reg_1142_pp0_iter7_reg | 4'd3); + +assign or_ln150_fu_1003_p2 = (trunc_ln149_reg_1142_pp0_iter7_reg | 4'd1); + +assign products_0_0_address0 = zext_ln153_fu_995_p1; + +assign products_0_0_d0 = mul_reg_1371; + +assign products_0_1_address0 = zext_ln153_6_fu_1025_p1; + +assign products_0_1_d0 = mul27_1_reg_1391; + +assign products_0_2_address0 = zext_ln153_7_fu_1055_p1; + +assign products_0_2_d0 = mul27_2_reg_1411; + +assign products_0_3_address0 = zext_ln153_8_fu_1085_p1; + +assign products_0_3_d0 = mul27_3_reg_1431; + +assign products_1_0_address0 = zext_ln153_fu_995_p1; + +assign products_1_0_d0 = mul_1_reg_1376; + +assign products_1_1_address0 = zext_ln153_6_fu_1025_p1; + +assign products_1_1_d0 = mul27_1_1_reg_1396; + +assign products_1_2_address0 = zext_ln153_7_fu_1055_p1; + +assign products_1_2_d0 = mul27_2_1_reg_1416; + +assign products_1_3_address0 = zext_ln153_8_fu_1085_p1; + +assign products_1_3_d0 = mul27_3_1_reg_1436; + +assign products_2_0_address0 = zext_ln153_fu_995_p1; + +assign products_2_0_d0 = mul_2_reg_1381; + +assign products_2_1_address0 = zext_ln153_6_fu_1025_p1; + +assign products_2_1_d0 = mul27_1_2_reg_1401; + +assign products_2_2_address0 = zext_ln153_7_fu_1055_p1; + +assign products_2_2_d0 = mul27_2_2_reg_1421; + +assign products_2_3_address0 = zext_ln153_8_fu_1085_p1; + +assign products_2_3_d0 = mul27_3_2_reg_1441; + +assign products_3_0_address0 = zext_ln153_fu_995_p1; + +assign products_3_0_d0 = mul_3_reg_1386; + +assign products_3_1_address0 = zext_ln153_6_fu_1025_p1; + +assign products_3_1_d0 = mul27_1_3_reg_1406; + +assign products_3_2_address0 = zext_ln153_7_fu_1055_p1; + +assign products_3_2_d0 = mul27_2_3_reg_1426; + +assign products_3_3_address0 = zext_ln153_8_fu_1085_p1; + +assign products_3_3_d0 = mul27_3_3_reg_1446; + +assign select_ln147_14_fu_807_p3 = ((icmp_ln148_reg_1108[0:0] == 1'b1) ? 5'd0 : ic_reg_651); + +assign select_ln147_15_fu_750_p3 = ((icmp_ln148_fu_744_p2[0:0] == 1'b1) ? add_ln147_fu_738_p2 : ap_phi_mux_ii_phi_fu_621_p4); + +assign select_ln147_16_fu_854_p3 = ((icmp_ln148_reg_1108[0:0] == 1'b1) ? sub_ln150_4_fu_848_p2 : sub_ln150_fu_784_p2); + +assign select_ln147_17_fu_861_p3 = ((icmp_ln148_reg_1108[0:0] == 1'b1) ? sub_ln150_4_fu_848_p2 : add_ln150_fu_794_p2); + +assign select_ln147_18_cast_fu_814_p1 = select_ln147_15_reg_1117; + +assign select_ln147_fu_800_p3 = ((icmp_ln148_reg_1108[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_644_p4); + +assign select_ln148_10_fu_901_p3 = ((or_ln147_fu_882_p2[0:0] == 1'b1) ? select_ln147_fu_800_p3 : add_ln148_fu_887_p2); + +assign select_ln148_11_fu_929_p3 = ((or_ln147_fu_882_p2[0:0] == 1'b1) ? select_ln147_17_fu_861_p3 : add_ln150_4_fu_923_p2); + +assign select_ln148_12_fu_764_p3 = ((icmp_ln148_fu_744_p2[0:0] == 1'b1) ? 5'd1 : add_ln148_4_fu_758_p2); + +assign select_ln148_13_cast_fu_909_p1 = select_ln148_10_fu_901_p3; + +assign select_ln148_fu_893_p3 = ((or_ln147_fu_882_p2[0:0] == 1'b1) ? select_ln147_14_fu_807_p3 : 5'd0); + +assign sext_ln150_fu_834_p1 = (empty_111_fu_828_p2); + +assign shl_ln150_mid1_fu_841_p3 = {{add_ln147_reg_1102}, {2'd0}}; + +assign shl_ln_fu_776_p3 = {{ii_reg_617}, {2'd0}}; + +assign sub_ln150_4_fu_848_p2 = (shl_ln150_mid1_fu_841_p3 - zext_ln150_8_fu_838_p1); + +assign sub_ln150_fu_784_p2 = (shl_ln_fu_776_p3 - zext_ln150_fu_772_p1); + +assign tmp_115_fu_959_p1 = (tmp_58_fu_951_p3); + +assign tmp_36_fu_1038_p4 = {{or_ln150_3_fu_1033_p2[3:2]}}; + +assign tmp_37_fu_1068_p4 = {{or_ln150_4_fu_1063_p2[3:2]}}; + +assign tmp_57_fu_868_p3 = ic_reg_651[32'd4]; + +assign tmp_58_fu_951_p3 = {{empty_112_fu_913_p2}, {newIndex_fu_941_p4}}; + +assign tmp_cast_fu_824_p1 = tmp_fu_817_p3; + +assign tmp_fu_817_p3 = {{select_ln147_15_reg_1117}, {2'd0}}; + +assign tmp_s_fu_1008_p4 = {{or_ln150_fu_1003_p2[3:2]}}; + +assign trunc_ln149_fu_937_p1 = select_ln148_fu_893_p3[3:0]; + +assign weight_vecs_0_0_address0 = tmp_115_fu_959_p1; + +assign weight_vecs_0_1_address0 = tmp_115_fu_959_p1; + +assign weight_vecs_0_2_address0 = tmp_115_fu_959_p1; + +assign weight_vecs_0_3_address0 = tmp_115_fu_959_p1; + +assign weight_vecs_1_0_address0 = tmp_115_fu_959_p1; + +assign weight_vecs_1_1_address0 = tmp_115_fu_959_p1; + +assign weight_vecs_1_2_address0 = tmp_115_fu_959_p1; + +assign weight_vecs_1_3_address0 = tmp_115_fu_959_p1; + +assign weight_vecs_2_0_address0 = tmp_115_fu_959_p1; + +assign weight_vecs_2_1_address0 = tmp_115_fu_959_p1; + +assign weight_vecs_2_2_address0 = tmp_115_fu_959_p1; + +assign weight_vecs_2_3_address0 = tmp_115_fu_959_p1; + +assign weight_vecs_3_0_address0 = tmp_115_fu_959_p1; + +assign weight_vecs_3_1_address0 = tmp_115_fu_959_p1; + +assign weight_vecs_3_2_address0 = tmp_115_fu_959_p1; + +assign weight_vecs_3_3_address0 = tmp_115_fu_959_p1; + +assign xor_ln149_fu_876_p2 = (tmp_57_fu_868_p3 ^ 1'd1); + +assign zext_ln150_4_fu_790_p1 = ap_phi_mux_jj_phi_fu_644_p4; + +assign zext_ln150_8_fu_838_p1 = add_ln147_reg_1102; + +assign zext_ln150_9_fu_919_p1 = add_ln148_fu_887_p2; + +assign zext_ln150_fu_772_p1 = ii_reg_617; + +assign zext_ln153_6_fu_1025_p1 = lshr_ln153_6_fu_1018_p3; + +assign zext_ln153_7_fu_1055_p1 = lshr_ln153_7_fu_1048_p3; + +assign zext_ln153_8_fu_1085_p1 = lshr_ln153_8_fu_1078_p3; + +assign zext_ln153_fu_995_p1 = lshr_ln_fu_989_p3; + +endmodule //td_fused_top_tdf4_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_filters_0_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 11; +parameter MEM_SIZE = 1152; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_filters_0( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd1152; +parameter AddressWidth = 32'd11; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf4_filters_0_ram td_fused_top_tdf4_filters_0_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + module td_fused_top_tdf4_filters_1_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 11; +parameter MEM_SIZE = 1152; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf4_filters_1_rom.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_filters_1( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd1152; +parameter AddressWidth = 32'd11; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +td_fused_top_tdf4_filters_1_rom td_fused_top_tdf4_filters_1_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + indices_2_out_din, + indices_2_out_full_n, + indices_2_out_write, + indices_2_out1_din, + indices_2_out1_full_n, + indices_2_out1_write, + write_r_din, + write_r_full_n, + write_r_write +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [4:0] indices_2_out_din; +input indices_2_out_full_n; +output indices_2_out_write; +output [4:0] indices_2_out1_din; +input indices_2_out1_full_n; +output indices_2_out1_write; +output write_r_din; +input write_r_full_n; +output write_r_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg indices_0_write; +reg indices_1_write; +reg indices_2_out_write; +reg indices_2_out1_write; +reg write_r_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [15:0] i_4; +reg [15:0] j_4; +reg [15:0] k_4; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg indices_2_out_blk_n; +reg indices_2_out1_blk_n; +reg write_r_blk_n; +reg [0:0] ap_phi_mux_j_15_flag_0_i_phi_fu_90_p6; +reg ap_block_state1; +wire [0:0] icmp_ln257_fu_161_p2; +wire [0:0] icmp_ln260_fu_174_p2; +reg [15:0] ap_phi_mux_j_15_new_0_i_phi_fu_104_p6; +wire [15:0] add_ln259_fu_167_p2; +reg [15:0] ap_phi_mux_k_15_new_0_i_phi_fu_117_p6; +wire [15:0] add_ln256_fu_154_p2; +wire [15:0] select_ln263_fu_192_p3; +wire [4:0] trunc_ln254_fu_141_p1; +wire [15:0] add_ln262_fu_180_p2; +wire [0:0] icmp_ln263_fu_186_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_4 = 16'd0; +#0 j_4 = 16'd0; +#0 k_4 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln260_fu_174_p2 == 1'd1) & (icmp_ln257_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_4 <= select_ln263_fu_192_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_15_flag_0_i_phi_fu_90_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j_4 <= ap_phi_mux_j_15_new_0_i_phi_fu_104_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k_4 <= ap_phi_mux_k_15_new_0_i_phi_fu_117_p6; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln257_fu_161_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_15_flag_0_i_phi_fu_90_p6 = 1'd0; + end else if ((((icmp_ln260_fu_174_p2 == 1'd0) & (icmp_ln257_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln260_fu_174_p2 == 1'd1) & (icmp_ln257_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_15_flag_0_i_phi_fu_90_p6 = 1'd1; + end else begin + ap_phi_mux_j_15_flag_0_i_phi_fu_90_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln257_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln260_fu_174_p2 == 1'd0)) begin + ap_phi_mux_j_15_new_0_i_phi_fu_104_p6 = add_ln259_fu_167_p2; + end else if ((icmp_ln260_fu_174_p2 == 1'd1)) begin + ap_phi_mux_j_15_new_0_i_phi_fu_104_p6 = 16'd0; + end else begin + ap_phi_mux_j_15_new_0_i_phi_fu_104_p6 = 'bx; + end + end else begin + ap_phi_mux_j_15_new_0_i_phi_fu_104_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln257_fu_161_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_15_new_0_i_phi_fu_117_p6 = add_ln256_fu_154_p2; + end else if ((((icmp_ln260_fu_174_p2 == 1'd0) & (icmp_ln257_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln260_fu_174_p2 == 1'd1) & (icmp_ln257_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_15_new_0_i_phi_fu_117_p6 = 16'd0; + end else begin + ap_phi_mux_k_15_new_0_i_phi_fu_117_p6 = 'bx; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_blk_n = indices_2_out1_full_n; + end else begin + indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_write = 1'b1; + end else begin + indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_blk_n = indices_2_out_full_n; + end else begin + indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_write = 1'b1; + end else begin + indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_r_blk_n = write_r_full_n; + end else begin + write_r_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_r_write = 1'b1; + end else begin + write_r_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln256_fu_154_p2 = (k_4 + 16'd1); + +assign add_ln259_fu_167_p2 = (j_4 + 16'd1); + +assign add_ln262_fu_180_p2 = (i_4 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign icmp_ln257_fu_161_p2 = ((add_ln256_fu_154_p2 == 16'd32) ? 1'b1 : 1'b0); + +assign icmp_ln260_fu_174_p2 = ((add_ln259_fu_167_p2 == 16'd56) ? 1'b1 : 1'b0); + +assign icmp_ln263_fu_186_p2 = ((add_ln262_fu_180_p2 == 16'd56) ? 1'b1 : 1'b0); + +assign indices_0_din = i_4; + +assign indices_1_din = j_4; + +assign indices_2_out1_din = trunc_ln254_fu_141_p1; + +assign indices_2_out_din = trunc_ln254_fu_141_p1; + +assign select_ln263_fu_192_p3 = ((icmp_ln263_fu_186_p2[0:0] == 1'b1) ? 16'd0 : add_ln262_fu_180_p2); + +assign start_out = real_start; + +assign trunc_ln254_fu_141_p1 = k_4[4:0]; + +assign write_r_din = ((k_4 == 16'd31) ? 1'b1 : 1'b0); + +endmodule //td_fused_top_tdf4_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_l2_accum ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + l2_products_0_address0, + l2_products_0_ce0, + l2_products_0_q0, + l2_products_0_address1, + l2_products_0_ce1, + l2_products_0_q1, + l2_products_1_address0, + l2_products_1_ce0, + l2_products_1_q0, + l2_products_1_address1, + l2_products_1_ce1, + l2_products_1_q1, + l2_products_2_address0, + l2_products_2_ce0, + l2_products_2_q0, + l2_products_2_address1, + l2_products_2_ce1, + l2_products_2_q1, + l2_products_3_address0, + l2_products_3_ce0, + l2_products_3_q0, + l2_products_3_address1, + l2_products_3_ce1, + l2_products_3_q1, + l2_partial_sums_0_address0, + l2_partial_sums_0_ce0, + l2_partial_sums_0_we0, + l2_partial_sums_0_d0, + l2_partial_sums_0_address1, + l2_partial_sums_0_ce1, + l2_partial_sums_0_we1, + l2_partial_sums_0_d1, + l2_partial_sums_1_address0, + l2_partial_sums_1_ce0, + l2_partial_sums_1_we0, + l2_partial_sums_1_d0, + l2_partial_sums_1_address1, + l2_partial_sums_1_ce1, + l2_partial_sums_1_we1, + l2_partial_sums_1_d1, + l2_partial_sums_2_address0, + l2_partial_sums_2_ce0, + l2_partial_sums_2_we0, + l2_partial_sums_2_d0, + l2_partial_sums_2_address1, + l2_partial_sums_2_ce1, + l2_partial_sums_2_we1, + l2_partial_sums_2_d1, + l2_partial_sums_3_address0, + l2_partial_sums_3_ce0, + l2_partial_sums_3_we0, + l2_partial_sums_3_d0, + l2_partial_sums_3_address1, + l2_partial_sums_3_ce1, + l2_partial_sums_3_we1, + l2_partial_sums_3_d1 +); + +parameter ap_ST_fsm_state1 = 12'd1; +parameter ap_ST_fsm_state2 = 12'd2; +parameter ap_ST_fsm_state3 = 12'd4; +parameter ap_ST_fsm_state4 = 12'd8; +parameter ap_ST_fsm_state5 = 12'd16; +parameter ap_ST_fsm_state6 = 12'd32; +parameter ap_ST_fsm_state7 = 12'd64; +parameter ap_ST_fsm_state8 = 12'd128; +parameter ap_ST_fsm_state9 = 12'd256; +parameter ap_ST_fsm_state10 = 12'd512; +parameter ap_ST_fsm_state11 = 12'd1024; +parameter ap_ST_fsm_state12 = 12'd2048; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [3:0] l2_products_0_address0; +output l2_products_0_ce0; +input [15:0] l2_products_0_q0; +output [3:0] l2_products_0_address1; +output l2_products_0_ce1; +input [15:0] l2_products_0_q1; +output [3:0] l2_products_1_address0; +output l2_products_1_ce0; +input [15:0] l2_products_1_q0; +output [3:0] l2_products_1_address1; +output l2_products_1_ce1; +input [15:0] l2_products_1_q1; +output [3:0] l2_products_2_address0; +output l2_products_2_ce0; +input [15:0] l2_products_2_q0; +output [3:0] l2_products_2_address1; +output l2_products_2_ce1; +input [15:0] l2_products_2_q1; +output [3:0] l2_products_3_address0; +output l2_products_3_ce0; +input [15:0] l2_products_3_q0; +output [3:0] l2_products_3_address1; +output l2_products_3_ce1; +input [15:0] l2_products_3_q1; +output [1:0] l2_partial_sums_0_address0; +output l2_partial_sums_0_ce0; +output l2_partial_sums_0_we0; +output [15:0] l2_partial_sums_0_d0; +output [1:0] l2_partial_sums_0_address1; +output l2_partial_sums_0_ce1; +output l2_partial_sums_0_we1; +output [15:0] l2_partial_sums_0_d1; +output [1:0] l2_partial_sums_1_address0; +output l2_partial_sums_1_ce0; +output l2_partial_sums_1_we0; +output [15:0] l2_partial_sums_1_d0; +output [1:0] l2_partial_sums_1_address1; +output l2_partial_sums_1_ce1; +output l2_partial_sums_1_we1; +output [15:0] l2_partial_sums_1_d1; +output [1:0] l2_partial_sums_2_address0; +output l2_partial_sums_2_ce0; +output l2_partial_sums_2_we0; +output [15:0] l2_partial_sums_2_d0; +output [1:0] l2_partial_sums_2_address1; +output l2_partial_sums_2_ce1; +output l2_partial_sums_2_we1; +output [15:0] l2_partial_sums_2_d1; +output [1:0] l2_partial_sums_3_address0; +output l2_partial_sums_3_ce0; +output l2_partial_sums_3_we0; +output [15:0] l2_partial_sums_3_d0; +output [1:0] l2_partial_sums_3_address1; +output l2_partial_sums_3_ce1; +output l2_partial_sums_3_we1; +output [15:0] l2_partial_sums_3_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg l2_products_0_ce0; +reg l2_products_0_ce1; +reg l2_products_1_ce0; +reg l2_products_1_ce1; +reg l2_products_2_ce0; +reg l2_products_2_ce1; +reg l2_products_3_ce0; +reg l2_products_3_ce1; +reg l2_partial_sums_0_ce0; +reg l2_partial_sums_0_we0; +reg l2_partial_sums_0_ce1; +reg l2_partial_sums_0_we1; +reg l2_partial_sums_1_ce0; +reg l2_partial_sums_1_we0; +reg l2_partial_sums_1_ce1; +reg l2_partial_sums_1_we1; +reg l2_partial_sums_2_ce0; +reg l2_partial_sums_2_we0; +reg l2_partial_sums_2_ce1; +reg l2_partial_sums_2_we1; +reg l2_partial_sums_3_ce0; +reg l2_partial_sums_3_we0; +reg l2_partial_sums_3_ce1; +reg l2_partial_sums_3_we1; + +reg ap_done_reg; + reg [11:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [1:0] add_ln40_fu_384_p2; +reg [1:0] add_ln40_reg_552; +wire ap_CS_fsm_state2; +wire [0:0] trunc_ln52_fu_396_p1; +reg [0:0] trunc_ln52_reg_560; +wire [0:0] icmp_ln40_fu_390_p2; +wire [1:0] out_idx_2_fu_406_p2; +reg [1:0] out_idx_2_reg_565; +wire [63:0] zext_ln54_fu_412_p1; +reg [63:0] zext_ln54_reg_570; +wire [63:0] zext_ln54_4_fu_416_p1; +reg [63:0] zext_ln54_4_reg_578; +wire [2:0] add_ln45_fu_420_p2; +reg [2:0] add_ln45_reg_586; +wire ap_CS_fsm_state3; +reg [15:0] l2_products_0_load_reg_634; +wire ap_CS_fsm_state4; +reg [15:0] l2_products_1_load_reg_639; +reg [15:0] l2_products_2_load_reg_644; +reg [15:0] l2_products_3_load_reg_649; +reg [15:0] l2_products_0_load_2_reg_654; +reg [15:0] l2_products_1_load_2_reg_659; +reg [15:0] l2_products_2_load_2_reg_664; +reg [15:0] l2_products_3_load_2_reg_669; +wire ap_CS_fsm_state5; +reg [1:0] group_reg_290; +wire [0:0] icmp_ln45_fu_458_p2; +reg ap_block_state1; +reg [2:0] i_1_1_reg_301; +wire ap_CS_fsm_state12; +wire [63:0] zext_ln54_5_fu_435_p1; +wire [63:0] zext_ln54_6_fu_450_p1; +reg [15:0] add14_lcssa15_fu_58; +wire [15:0] grp_fu_312_p2; +reg [15:0] add14_1_lcssa17_fu_62; +wire [15:0] grp_fu_316_p2; +reg [15:0] add14_2_lcssa19_fu_66; +wire [15:0] grp_fu_320_p2; +reg [15:0] add14_3_lcssa21_fu_70; +wire [15:0] grp_fu_324_p2; +reg [15:0] add14_4_lcssa23_fu_74; +wire [15:0] grp_fu_328_p2; +reg [15:0] add14_5_lcssa25_fu_78; +wire [15:0] grp_fu_332_p2; +reg [15:0] add14_6_lcssa27_fu_82; +wire [15:0] grp_fu_336_p2; +reg [15:0] add14_7_lcssa29_fu_86; +wire [15:0] grp_fu_340_p2; +wire [1:0] out_idx_fu_400_p2; +wire [4:0] tmp_s_fu_426_p4; +wire [4:0] tmp_35_fu_443_p3; +reg [11:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 12'd1; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U629( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_lcssa15_fu_58), + .din1(l2_products_0_load_reg_634), + .dout(grp_fu_312_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U630( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_1_lcssa17_fu_62), + .din1(l2_products_1_load_reg_639), + .dout(grp_fu_316_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U631( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_2_lcssa19_fu_66), + .din1(l2_products_2_load_reg_644), + .dout(grp_fu_320_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U632( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_3_lcssa21_fu_70), + .din1(l2_products_3_load_reg_649), + .dout(grp_fu_324_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U633( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_4_lcssa23_fu_74), + .din1(l2_products_0_load_2_reg_654), + .dout(grp_fu_328_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U634( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_5_lcssa25_fu_78), + .din1(l2_products_1_load_2_reg_659), + .dout(grp_fu_332_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U635( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_6_lcssa27_fu_82), + .din1(l2_products_2_load_2_reg_664), + .dout(grp_fu_336_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U636( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_7_lcssa29_fu_86), + .din1(l2_products_3_load_2_reg_669), + .dout(grp_fu_340_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((1'b1 == ap_CS_fsm_state2) & (icmp_ln40_fu_390_p2 == 1'd1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + group_reg_290 <= 2'd0; + end else if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_458_p2 == 1'd1))) begin + group_reg_290 <= add_ln40_reg_552; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + i_1_1_reg_301 <= add_ln45_reg_586; + end else if (((1'b1 == ap_CS_fsm_state2) & (icmp_ln40_fu_390_p2 == 1'd0))) begin + i_1_1_reg_301 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + add14_1_lcssa17_fu_62 <= grp_fu_316_p2; + add14_2_lcssa19_fu_66 <= grp_fu_320_p2; + add14_3_lcssa21_fu_70 <= grp_fu_324_p2; + add14_4_lcssa23_fu_74 <= grp_fu_328_p2; + add14_5_lcssa25_fu_78 <= grp_fu_332_p2; + add14_6_lcssa27_fu_82 <= grp_fu_336_p2; + add14_7_lcssa29_fu_86 <= grp_fu_340_p2; + add14_lcssa15_fu_58 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln40_reg_552 <= add_ln40_fu_384_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + add_ln45_reg_586 <= add_ln45_fu_420_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + l2_products_0_load_2_reg_654 <= l2_products_0_q0; + l2_products_0_load_reg_634 <= l2_products_0_q1; + l2_products_1_load_2_reg_659 <= l2_products_1_q0; + l2_products_1_load_reg_639 <= l2_products_1_q1; + l2_products_2_load_2_reg_664 <= l2_products_2_q0; + l2_products_2_load_reg_644 <= l2_products_2_q1; + l2_products_3_load_2_reg_669 <= l2_products_3_q0; + l2_products_3_load_reg_649 <= l2_products_3_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_state2) & (icmp_ln40_fu_390_p2 == 1'd0))) begin + out_idx_2_reg_565[1] <= out_idx_2_fu_406_p2[1]; + trunc_ln52_reg_560 <= trunc_ln52_fu_396_p1; + zext_ln54_4_reg_578[1] <= zext_ln54_4_fu_416_p1[1]; + zext_ln54_reg_570[1] <= zext_ln54_fu_412_p1[1]; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) & (icmp_ln40_fu_390_p2 == 1'd1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) & (icmp_ln40_fu_390_p2 == 1'd1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_0_ce0 = 1'b1; + end else begin + l2_partial_sums_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_0_ce1 = 1'b1; + end else begin + l2_partial_sums_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_458_p2 == 1'd1))) begin + l2_partial_sums_0_we0 = 1'b1; + end else begin + l2_partial_sums_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_458_p2 == 1'd1))) begin + l2_partial_sums_0_we1 = 1'b1; + end else begin + l2_partial_sums_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_1_ce0 = 1'b1; + end else begin + l2_partial_sums_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_1_ce1 = 1'b1; + end else begin + l2_partial_sums_1_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_458_p2 == 1'd1))) begin + l2_partial_sums_1_we0 = 1'b1; + end else begin + l2_partial_sums_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_458_p2 == 1'd1))) begin + l2_partial_sums_1_we1 = 1'b1; + end else begin + l2_partial_sums_1_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_2_ce0 = 1'b1; + end else begin + l2_partial_sums_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_2_ce1 = 1'b1; + end else begin + l2_partial_sums_2_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_458_p2 == 1'd1))) begin + l2_partial_sums_2_we0 = 1'b1; + end else begin + l2_partial_sums_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_458_p2 == 1'd1))) begin + l2_partial_sums_2_we1 = 1'b1; + end else begin + l2_partial_sums_2_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_3_ce0 = 1'b1; + end else begin + l2_partial_sums_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_3_ce1 = 1'b1; + end else begin + l2_partial_sums_3_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_458_p2 == 1'd1))) begin + l2_partial_sums_3_we0 = 1'b1; + end else begin + l2_partial_sums_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_458_p2 == 1'd1))) begin + l2_partial_sums_3_we1 = 1'b1; + end else begin + l2_partial_sums_3_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_0_ce0 = 1'b1; + end else begin + l2_products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_0_ce1 = 1'b1; + end else begin + l2_products_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_1_ce0 = 1'b1; + end else begin + l2_products_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_1_ce1 = 1'b1; + end else begin + l2_products_1_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_2_ce0 = 1'b1; + end else begin + l2_products_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_2_ce1 = 1'b1; + end else begin + l2_products_2_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_3_ce0 = 1'b1; + end else begin + l2_products_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_3_ce1 = 1'b1; + end else begin + l2_products_3_ce1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((1'b1 == ap_CS_fsm_state2) & (icmp_ln40_fu_390_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_458_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln40_fu_384_p2 = (group_reg_290 + 2'd1); + +assign add_ln45_fu_420_p2 = (i_1_1_reg_301 + 3'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln40_fu_390_p2 = ((group_reg_290 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln45_fu_458_p2 = ((i_1_1_reg_301 == 3'd4) ? 1'b1 : 1'b0); + +assign l2_partial_sums_0_address0 = zext_ln54_4_reg_578; + +assign l2_partial_sums_0_address1 = zext_ln54_reg_570; + +assign l2_partial_sums_0_d0 = add14_4_lcssa23_fu_74; + +assign l2_partial_sums_0_d1 = add14_lcssa15_fu_58; + +assign l2_partial_sums_1_address0 = zext_ln54_4_reg_578; + +assign l2_partial_sums_1_address1 = zext_ln54_reg_570; + +assign l2_partial_sums_1_d0 = add14_5_lcssa25_fu_78; + +assign l2_partial_sums_1_d1 = add14_1_lcssa17_fu_62; + +assign l2_partial_sums_2_address0 = zext_ln54_4_reg_578; + +assign l2_partial_sums_2_address1 = zext_ln54_reg_570; + +assign l2_partial_sums_2_d0 = add14_6_lcssa27_fu_82; + +assign l2_partial_sums_2_d1 = add14_2_lcssa19_fu_66; + +assign l2_partial_sums_3_address0 = zext_ln54_4_reg_578; + +assign l2_partial_sums_3_address1 = zext_ln54_reg_570; + +assign l2_partial_sums_3_d0 = add14_7_lcssa29_fu_86; + +assign l2_partial_sums_3_d1 = add14_3_lcssa21_fu_70; + +assign l2_products_0_address0 = zext_ln54_6_fu_450_p1; + +assign l2_products_0_address1 = zext_ln54_5_fu_435_p1; + +assign l2_products_1_address0 = zext_ln54_6_fu_450_p1; + +assign l2_products_1_address1 = zext_ln54_5_fu_435_p1; + +assign l2_products_2_address0 = zext_ln54_6_fu_450_p1; + +assign l2_products_2_address1 = zext_ln54_5_fu_435_p1; + +assign l2_products_3_address0 = zext_ln54_6_fu_450_p1; + +assign l2_products_3_address1 = zext_ln54_5_fu_435_p1; + +assign out_idx_2_fu_406_p2 = (out_idx_fu_400_p2 | 2'd1); + +assign out_idx_fu_400_p2 = group_reg_290 << 2'd1; + +assign tmp_35_fu_443_p3 = {{i_1_1_reg_301}, {out_idx_2_reg_565}}; + +assign tmp_s_fu_426_p4 = {{{i_1_1_reg_301}, {trunc_ln52_reg_560}}, {1'd0}}; + +assign trunc_ln52_fu_396_p1 = group_reg_290[0:0]; + +assign zext_ln54_4_fu_416_p1 = out_idx_2_fu_406_p2; + +assign zext_ln54_5_fu_435_p1 = tmp_s_fu_426_p4; + +assign zext_ln54_6_fu_450_p1 = tmp_35_fu_443_p3; + +assign zext_ln54_fu_412_p1 = out_idx_fu_400_p2; + +always @ (posedge ap_clk) begin + out_idx_2_reg_565[0] <= 1'b1; + zext_ln54_reg_570[0] <= 1'b0; + zext_ln54_reg_570[63:2] <= 62'b00000000000000000000000000000000000000000000000000000000000000; + zext_ln54_4_reg_578[0] <= 1'b1; + zext_ln54_4_reg_578[63:2] <= 62'b00000000000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf4_l2_accum +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_l2_filters_0_ram (addr0, ce0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 10; +parameter MEM_SIZE = 1024; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_l2_filters_0( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd1024; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_tdf4_l2_filters_0_ram td_fused_top_tdf4_l2_filters_0_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + module td_fused_top_tdf4_l2_filters_1_rom ( +addr0, ce0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 10; +parameter MEM_SIZE = 1024; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf4_l2_filters_1_rom.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +always @(posedge clk) +begin + if (ce1) + begin + q1 <= ram[addr1]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_l2_filters_1( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd1024; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_tdf4_l2_filters_1_rom td_fused_top_tdf4_l2_filters_1_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_l2_multiply34 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + intermediate_fmaps_0_read, + intermediate_fmaps_1_read, + intermediate_fmaps_2_read, + intermediate_fmaps_3_read, + l2_filter_data_0_address0, + l2_filter_data_0_ce0, + l2_filter_data_0_q0, + l2_filter_data_0_address1, + l2_filter_data_0_ce1, + l2_filter_data_0_q1, + l2_filter_data_1_address0, + l2_filter_data_1_ce0, + l2_filter_data_1_q0, + l2_filter_data_1_address1, + l2_filter_data_1_ce1, + l2_filter_data_1_q1, + l2_products_0_address0, + l2_products_0_ce0, + l2_products_0_we0, + l2_products_0_d0, + l2_products_1_address0, + l2_products_1_ce0, + l2_products_1_we0, + l2_products_1_d0, + l2_products_2_address0, + l2_products_2_ce0, + l2_products_2_we0, + l2_products_2_d0, + l2_products_3_address0, + l2_products_3_ce0, + l2_products_3_we0, + l2_products_3_d0, + indices_23_dout, + indices_23_empty_n, + indices_23_read +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] intermediate_fmaps_0_read; +input [15:0] intermediate_fmaps_1_read; +input [15:0] intermediate_fmaps_2_read; +input [15:0] intermediate_fmaps_3_read; +output [9:0] l2_filter_data_0_address0; +output l2_filter_data_0_ce0; +input [15:0] l2_filter_data_0_q0; +output [9:0] l2_filter_data_0_address1; +output l2_filter_data_0_ce1; +input [15:0] l2_filter_data_0_q1; +output [9:0] l2_filter_data_1_address0; +output l2_filter_data_1_ce0; +input [15:0] l2_filter_data_1_q0; +output [9:0] l2_filter_data_1_address1; +output l2_filter_data_1_ce1; +input [15:0] l2_filter_data_1_q1; +output [3:0] l2_products_0_address0; +output l2_products_0_ce0; +output l2_products_0_we0; +output [15:0] l2_products_0_d0; +output [3:0] l2_products_1_address0; +output l2_products_1_ce0; +output l2_products_1_we0; +output [15:0] l2_products_1_d0; +output [3:0] l2_products_2_address0; +output l2_products_2_ce0; +output l2_products_2_we0; +output [15:0] l2_products_2_d0; +output [3:0] l2_products_3_address0; +output l2_products_3_ce0; +output l2_products_3_we0; +output [15:0] l2_products_3_d0; +input [4:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg l2_filter_data_0_ce0; +reg l2_filter_data_0_ce1; +reg l2_filter_data_1_ce0; +reg l2_filter_data_1_ce1; +reg l2_products_0_ce0; +reg l2_products_0_we0; +reg l2_products_1_ce0; +reg l2_products_1_we0; +reg l2_products_2_ce0; +reg l2_products_2_we0; +reg l2_products_3_ce0; +reg l2_products_3_we0; +reg indices_23_read; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [6:0] i_1_1_reg_234; +reg [4:0] indices_23_read_reg_381; +wire [0:0] tmp_56_fu_261_p3; +reg [0:0] tmp_56_reg_387; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +reg [0:0] tmp_56_reg_387_pp0_iter1_reg; +reg [0:0] tmp_56_reg_387_pp0_iter2_reg; +reg [0:0] tmp_56_reg_387_pp0_iter3_reg; +reg [0:0] tmp_56_reg_387_pp0_iter4_reg; +reg [0:0] tmp_56_reg_387_pp0_iter5_reg; +reg [0:0] tmp_56_reg_387_pp0_iter6_reg; +wire [6:0] add_ln20_fu_269_p2; +reg ap_enable_reg_pp0_iter0; +wire [1:0] l2_i_fu_275_p4; +reg [1:0] l2_i_reg_396; +reg [3:0] tmp_32_reg_411; +reg [3:0] tmp_32_reg_411_pp0_iter1_reg; +reg [3:0] tmp_32_reg_411_pp0_iter2_reg; +reg [3:0] tmp_32_reg_411_pp0_iter3_reg; +reg [3:0] tmp_32_reg_411_pp0_iter4_reg; +reg [3:0] tmp_32_reg_411_pp0_iter5_reg; +reg [3:0] tmp_32_reg_411_pp0_iter6_reg; +wire [15:0] tmp_fu_341_p6; +reg [15:0] tmp_reg_426; +reg [15:0] l2_filter_data_0_load_reg_434; +reg ap_enable_reg_pp0_iter1; +reg [15:0] l2_filter_data_1_load_reg_439; +reg [15:0] l2_filter_data_0_load_2_reg_444; +reg [15:0] l2_filter_data_1_load_2_reg_449; +wire [15:0] grp_fu_245_p2; +reg [15:0] mul_i_i_reg_454; +wire [15:0] grp_fu_249_p2; +reg [15:0] mul18_1_i_i_reg_459; +wire [15:0] grp_fu_253_p2; +reg [15:0] mul18_2_i_i_reg_464; +wire [15:0] grp_fu_257_p2; +reg [15:0] mul18_3_i_i_reg_469; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +wire [63:0] zext_ln29_fu_304_p1; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln29_15_fu_335_p1; +wire [63:0] tmp_33_fu_350_p3; +wire [2:0] lshr_ln_fu_285_p4; +wire [9:0] tmp_s_fu_295_p4; +wire [2:0] or_ln29_fu_320_p2; +wire [9:0] tmp_34_fu_326_p4; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U613( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_426), + .din1(l2_filter_data_0_load_reg_434), + .dout(grp_fu_245_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U614( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_426), + .din1(l2_filter_data_1_load_reg_439), + .dout(grp_fu_249_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U615( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_426), + .din1(l2_filter_data_0_load_2_reg_444), + .dout(grp_fu_253_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U616( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_426), + .din1(l2_filter_data_1_load_2_reg_449), + .dout(grp_fu_257_p2) +); + +td_fused_top_mux_42_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 16 )) +mux_42_16_1_1_U617( + .din0(intermediate_fmaps_0_read), + .din1(intermediate_fmaps_1_read), + .din2(intermediate_fmaps_2_read), + .din3(intermediate_fmaps_3_read), + .din4(l2_i_reg_396), + .dout(tmp_fu_341_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_234 <= 7'd0; + end else if (((tmp_56_fu_261_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + i_1_1_reg_234 <= add_ln20_fu_269_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + indices_23_read_reg_381 <= indices_23_dout; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_56_reg_387 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_0_load_2_reg_444 <= l2_filter_data_0_q0; + l2_filter_data_0_load_reg_434 <= l2_filter_data_0_q1; + l2_filter_data_1_load_2_reg_449 <= l2_filter_data_1_q0; + l2_filter_data_1_load_reg_439 <= l2_filter_data_1_q1; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_56_fu_261_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_i_reg_396 <= {{i_1_1_reg_234[5:4]}}; + tmp_32_reg_411 <= {{i_1_1_reg_234[5:2]}}; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_56_reg_387_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul18_1_i_i_reg_459 <= grp_fu_249_p2; + mul18_2_i_i_reg_464 <= grp_fu_253_p2; + mul18_3_i_i_reg_469 <= grp_fu_257_p2; + mul_i_i_reg_454 <= grp_fu_245_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + tmp_32_reg_411_pp0_iter1_reg <= tmp_32_reg_411; + tmp_56_reg_387 <= i_1_1_reg_234[32'd6]; + tmp_56_reg_387_pp0_iter1_reg <= tmp_56_reg_387; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + tmp_32_reg_411_pp0_iter2_reg <= tmp_32_reg_411_pp0_iter1_reg; + tmp_32_reg_411_pp0_iter3_reg <= tmp_32_reg_411_pp0_iter2_reg; + tmp_32_reg_411_pp0_iter4_reg <= tmp_32_reg_411_pp0_iter3_reg; + tmp_32_reg_411_pp0_iter5_reg <= tmp_32_reg_411_pp0_iter4_reg; + tmp_32_reg_411_pp0_iter6_reg <= tmp_32_reg_411_pp0_iter5_reg; + tmp_56_reg_387_pp0_iter2_reg <= tmp_56_reg_387_pp0_iter1_reg; + tmp_56_reg_387_pp0_iter3_reg <= tmp_56_reg_387_pp0_iter2_reg; + tmp_56_reg_387_pp0_iter4_reg <= tmp_56_reg_387_pp0_iter3_reg; + tmp_56_reg_387_pp0_iter5_reg <= tmp_56_reg_387_pp0_iter4_reg; + tmp_56_reg_387_pp0_iter6_reg <= tmp_56_reg_387_pp0_iter5_reg; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_56_reg_387 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + tmp_reg_426 <= tmp_fu_341_p6; + end +end + +always @ (*) begin + if ((tmp_56_fu_261_p3 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_0_ce0 = 1'b1; + end else begin + l2_filter_data_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_0_ce1 = 1'b1; + end else begin + l2_filter_data_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_1_ce0 = 1'b1; + end else begin + l2_filter_data_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_1_ce1 = 1'b1; + end else begin + l2_filter_data_1_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_0_ce0 = 1'b1; + end else begin + l2_products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (tmp_56_reg_387_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_0_we0 = 1'b1; + end else begin + l2_products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_1_ce0 = 1'b1; + end else begin + l2_products_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (tmp_56_reg_387_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_1_we0 = 1'b1; + end else begin + l2_products_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_2_ce0 = 1'b1; + end else begin + l2_products_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (tmp_56_reg_387_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_2_we0 = 1'b1; + end else begin + l2_products_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_3_ce0 = 1'b1; + end else begin + l2_products_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (tmp_56_reg_387_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_3_we0 = 1'b1; + end else begin + l2_products_3_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((tmp_56_fu_261_p3 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((tmp_56_fu_261_p3 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln20_fu_269_p2 = (i_1_1_reg_234 + 7'd4); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign l2_filter_data_0_address0 = zext_ln29_15_fu_335_p1; + +assign l2_filter_data_0_address1 = zext_ln29_fu_304_p1; + +assign l2_filter_data_1_address0 = zext_ln29_15_fu_335_p1; + +assign l2_filter_data_1_address1 = zext_ln29_fu_304_p1; + +assign l2_i_fu_275_p4 = {{i_1_1_reg_234[5:4]}}; + +assign l2_products_0_address0 = tmp_33_fu_350_p3; + +assign l2_products_0_d0 = mul_i_i_reg_454; + +assign l2_products_1_address0 = tmp_33_fu_350_p3; + +assign l2_products_1_d0 = mul18_1_i_i_reg_459; + +assign l2_products_2_address0 = tmp_33_fu_350_p3; + +assign l2_products_2_d0 = mul18_2_i_i_reg_464; + +assign l2_products_3_address0 = tmp_33_fu_350_p3; + +assign l2_products_3_d0 = mul18_3_i_i_reg_469; + +assign lshr_ln_fu_285_p4 = {{i_1_1_reg_234[3:1]}}; + +assign or_ln29_fu_320_p2 = (lshr_ln_fu_285_p4 | 3'd1); + +assign tmp_33_fu_350_p3 = {{60'd0}, {tmp_32_reg_411_pp0_iter6_reg}}; + +assign tmp_34_fu_326_p4 = {{{or_ln29_fu_320_p2}, {indices_23_read_reg_381}}, {l2_i_fu_275_p4}}; + +assign tmp_56_fu_261_p3 = i_1_1_reg_234[32'd6]; + +assign tmp_s_fu_295_p4 = {{{lshr_ln_fu_285_p4}, {indices_23_read_reg_381}}, {l2_i_fu_275_p4}}; + +assign zext_ln29_15_fu_335_p1 = tmp_34_fu_326_p4; + +assign zext_ln29_fu_304_p1 = tmp_s_fu_295_p4; + +endmodule //td_fused_top_tdf4_l2_multiply34 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_l2_writeOutputs_1_running_sums_1_ram (addr0, ce0, d0, we0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 4; +parameter MEM_SIZE = 16; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf4_l2_writeOutputs_1_running_sums_1_ram.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_l2_writeOutputs_1_running_sums_1( + reset, + clk, + address0, + ce0, + we0, + d0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd16; +parameter AddressWidth = 32'd4; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_tdf4_l2_writeOutputs_1_running_sums_1_ram td_fused_top_tdf4_l2_writeOutputs_1_running_sums_1_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_l2_writeOutputs_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + write4_dout, + write4_empty_n, + write4_read, + l2_partial_sums_0_address0, + l2_partial_sums_0_ce0, + l2_partial_sums_0_q0, + l2_partial_sums_1_address0, + l2_partial_sums_1_ce0, + l2_partial_sums_1_q0, + l2_partial_sums_2_address0, + l2_partial_sums_2_ce0, + l2_partial_sums_2_q0, + l2_partial_sums_3_address0, + l2_partial_sums_3_ce0, + l2_partial_sums_3_q0, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_q0 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_pp0_stage0 = 4'd4; +parameter ap_ST_fsm_state34 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [5:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [11:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [0:0] write4_dout; +input write4_empty_n; +output write4_read; +output [1:0] l2_partial_sums_0_address0; +output l2_partial_sums_0_ce0; +input [15:0] l2_partial_sums_0_q0; +output [1:0] l2_partial_sums_1_address0; +output l2_partial_sums_1_ce0; +input [15:0] l2_partial_sums_1_q0; +output [1:0] l2_partial_sums_2_address0; +output l2_partial_sums_2_ce0; +input [15:0] l2_partial_sums_2_q0; +output [1:0] l2_partial_sums_3_address0; +output l2_partial_sums_3_ce0; +input [15:0] l2_partial_sums_3_q0; +output [13:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; +output [3:0] l2_adjustments_address0; +output l2_adjustments_ce0; +input [47:0] l2_adjustments_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg write4_read; +reg l2_partial_sums_0_ce0; +reg l2_partial_sums_1_ce0; +reg l2_partial_sums_2_ce0; +reg l2_partial_sums_3_ce0; +reg out_data_ce1; +reg out_data_we1; +reg l2_adjustments_ce0; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg running_sums_1_ce0; +reg running_sums_1_we0; +wire [15:0] running_sums_1_d0; +wire [3:0] running_sums_1_address1; +reg running_sums_1_ce1; +wire [15:0] running_sums_1_q1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg write4_blk_n; +reg [4:0] ochan_reg_253; +reg [5:0] indices_01_read_reg_632; +reg [11:0] indices_12_read_reg_638; +reg [0:0] write4_read_reg_643; +wire [13:0] add_ln109_fu_315_p2; +reg [13:0] add_ln109_reg_649; +wire ap_CS_fsm_state2; +wire [4:0] add_ln86_fu_321_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state4_pp0_stage0_iter1; +wire ap_block_state5_pp0_stage0_iter2; +wire ap_block_state6_pp0_stage0_iter3; +wire ap_block_state7_pp0_stage0_iter4; +wire ap_block_state8_pp0_stage0_iter5; +wire ap_block_state9_pp0_stage0_iter6; +wire ap_block_state10_pp0_stage0_iter7; +wire ap_block_state11_pp0_stage0_iter8; +wire ap_block_state12_pp0_stage0_iter9; +wire ap_block_state13_pp0_stage0_iter10; +wire ap_block_state14_pp0_stage0_iter11; +wire ap_block_state15_pp0_stage0_iter12; +wire ap_block_state16_pp0_stage0_iter13; +wire ap_block_state17_pp0_stage0_iter14; +wire ap_block_state18_pp0_stage0_iter15; +wire ap_block_state19_pp0_stage0_iter16; +wire ap_block_state20_pp0_stage0_iter17; +wire ap_block_state21_pp0_stage0_iter18; +wire ap_block_state22_pp0_stage0_iter19; +wire ap_block_state23_pp0_stage0_iter20; +wire ap_block_state24_pp0_stage0_iter21; +wire ap_block_state25_pp0_stage0_iter22; +wire ap_block_state26_pp0_stage0_iter23; +wire ap_block_state27_pp0_stage0_iter24; +wire ap_block_state28_pp0_stage0_iter25; +wire ap_block_state29_pp0_stage0_iter26; +wire ap_block_state30_pp0_stage0_iter27; +wire ap_block_state31_pp0_stage0_iter28; +wire ap_block_state32_pp0_stage0_iter29; +wire ap_block_state33_pp0_stage0_iter30; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln86_fu_327_p2; +wire [63:0] zext_ln86_fu_333_p1; +reg [63:0] zext_ln86_reg_663; +reg [63:0] zext_ln86_reg_663_pp0_iter1_reg; +reg [63:0] zext_ln86_reg_663_pp0_iter2_reg; +reg [63:0] zext_ln86_reg_663_pp0_iter3_reg; +reg [63:0] zext_ln86_reg_663_pp0_iter4_reg; +reg [63:0] zext_ln86_reg_663_pp0_iter5_reg; +reg [63:0] zext_ln86_reg_663_pp0_iter6_reg; +reg [63:0] zext_ln86_reg_663_pp0_iter7_reg; +wire [1:0] trunc_ln89_fu_338_p1; +reg [1:0] trunc_ln89_reg_668; +reg [1:0] trunc_ln89_reg_668_pp0_iter1_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter2_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter3_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter4_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter5_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter6_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter7_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter8_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter9_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter10_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter11_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter12_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter13_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter14_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter15_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter16_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter17_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter18_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter19_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter20_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter21_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter22_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter23_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter24_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter25_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter26_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter27_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter28_reg; +reg [1:0] trunc_ln89_reg_668_pp0_iter29_reg; +wire [1:0] lshr_ln_fu_342_p4; +reg [1:0] lshr_ln_reg_676; +reg [1:0] lshr_ln_reg_676_pp0_iter1_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter2_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter3_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter4_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter5_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter6_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter7_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter8_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter9_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter10_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter11_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter12_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter13_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter14_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter15_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter16_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter17_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter18_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter19_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter20_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter21_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter22_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter23_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter24_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter25_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter26_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter27_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter28_reg; +reg [1:0] lshr_ln_reg_676_pp0_iter29_reg; +reg [3:0] running_sums_1_addr_reg_701; +reg [3:0] running_sums_1_addr_reg_701_pp0_iter1_reg; +reg [3:0] running_sums_1_addr_reg_701_pp0_iter2_reg; +reg [3:0] running_sums_1_addr_reg_701_pp0_iter3_reg; +reg [3:0] running_sums_1_addr_reg_701_pp0_iter4_reg; +reg [3:0] running_sums_1_addr_reg_701_pp0_iter5_reg; +reg [3:0] running_sums_1_addr_reg_701_pp0_iter6_reg; +reg [3:0] running_sums_1_addr_reg_701_pp0_iter7_reg; +reg [3:0] running_sums_1_addr_reg_701_pp0_iter8_reg; +reg [3:0] running_sums_1_addr_reg_701_pp0_iter9_reg; +wire [0:0] and_ln103_fu_366_p2; +reg [0:0] and_ln103_reg_707; +reg [0:0] and_ln103_reg_707_pp0_iter1_reg; +reg [0:0] and_ln103_reg_707_pp0_iter2_reg; +reg [0:0] and_ln103_reg_707_pp0_iter3_reg; +reg [0:0] and_ln103_reg_707_pp0_iter4_reg; +reg [0:0] and_ln103_reg_707_pp0_iter5_reg; +reg [0:0] and_ln103_reg_707_pp0_iter6_reg; +reg [0:0] and_ln103_reg_707_pp0_iter7_reg; +reg [0:0] and_ln103_reg_707_pp0_iter8_reg; +reg [0:0] and_ln103_reg_707_pp0_iter9_reg; +reg [0:0] and_ln103_reg_707_pp0_iter10_reg; +reg [0:0] and_ln103_reg_707_pp0_iter11_reg; +reg [0:0] and_ln103_reg_707_pp0_iter12_reg; +reg [0:0] and_ln103_reg_707_pp0_iter13_reg; +reg [0:0] and_ln103_reg_707_pp0_iter14_reg; +reg [0:0] and_ln103_reg_707_pp0_iter15_reg; +reg [0:0] and_ln103_reg_707_pp0_iter16_reg; +reg [0:0] and_ln103_reg_707_pp0_iter17_reg; +reg [0:0] and_ln103_reg_707_pp0_iter18_reg; +reg [0:0] and_ln103_reg_707_pp0_iter19_reg; +reg [0:0] and_ln103_reg_707_pp0_iter20_reg; +reg [0:0] and_ln103_reg_707_pp0_iter21_reg; +reg [0:0] and_ln103_reg_707_pp0_iter22_reg; +reg [0:0] and_ln103_reg_707_pp0_iter23_reg; +reg [0:0] and_ln103_reg_707_pp0_iter24_reg; +reg [0:0] and_ln103_reg_707_pp0_iter25_reg; +reg [0:0] and_ln103_reg_707_pp0_iter26_reg; +reg [0:0] and_ln103_reg_707_pp0_iter27_reg; +reg [0:0] and_ln103_reg_707_pp0_iter28_reg; +reg [0:0] and_ln103_reg_707_pp0_iter29_reg; +wire [15:0] val_fu_374_p6; +reg [15:0] val_reg_711; +reg [15:0] running_sums_1_load_reg_716; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_264_p2; +reg [15:0] sum_reg_726; +wire [15:0] trunc_ln95_fu_388_p1; +reg [15:0] trunc_ln95_reg_732; +reg [15:0] tmp_178_i_i_reg_737; +reg [15:0] tmp_178_i_i_reg_737_pp0_iter10_reg; +reg [15:0] tmp_178_i_i_reg_737_pp0_iter11_reg; +reg [15:0] tmp_178_i_i_reg_737_pp0_iter12_reg; +reg [15:0] tmp_178_i_i_reg_737_pp0_iter13_reg; +reg [15:0] tmp_178_i_i_reg_737_pp0_iter14_reg; +reg [15:0] tmp_178_i_i_reg_737_pp0_iter15_reg; +reg [15:0] tmp_178_i_i_reg_737_pp0_iter16_reg; +reg [15:0] tmp_179_i_i_reg_742; +reg [15:0] tmp_179_i_i_reg_742_pp0_iter10_reg; +reg [15:0] tmp_179_i_i_reg_742_pp0_iter11_reg; +reg [15:0] tmp_179_i_i_reg_742_pp0_iter12_reg; +reg [15:0] tmp_179_i_i_reg_742_pp0_iter13_reg; +reg [15:0] tmp_179_i_i_reg_742_pp0_iter14_reg; +reg [15:0] tmp_179_i_i_reg_742_pp0_iter15_reg; +reg [15:0] tmp_179_i_i_reg_742_pp0_iter16_reg; +reg [15:0] tmp_179_i_i_reg_742_pp0_iter17_reg; +reg [15:0] tmp_179_i_i_reg_742_pp0_iter18_reg; +reg [15:0] tmp_179_i_i_reg_742_pp0_iter19_reg; +reg [15:0] tmp_179_i_i_reg_742_pp0_iter20_reg; +reg [15:0] tmp_179_i_i_reg_742_pp0_iter21_reg; +wire [15:0] grp_fu_272_p2; +reg [15:0] sub_i_i_i_reg_752; +wire [15:0] grp_fu_276_p2; +reg [15:0] normalized_reg_762; +wire [15:0] grp_fu_268_p2; +reg [15:0] biased_reg_772; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state3; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_enable_reg_pp0_iter22; +reg ap_enable_reg_pp0_iter23; +reg ap_enable_reg_pp0_iter24; +reg ap_enable_reg_pp0_iter25; +reg ap_enable_reg_pp0_iter26; +reg ap_enable_reg_pp0_iter27; +reg ap_enable_reg_pp0_iter28; +reg ap_enable_reg_pp0_iter29; +reg ap_enable_reg_pp0_iter30; +wire [63:0] zext_ln89_2_fu_352_p1; +wire ap_block_pp0_stage0; +wire [63:0] sext_ln109_fu_449_p1; +reg [15:0] quad_3_14_fu_120; +wire [15:0] quad_3_26_fu_551_p3; +reg [15:0] quad_3_15_fu_124; +wire [15:0] quad_3_25_fu_543_p3; +reg [15:0] quad_3_16_fu_128; +wire [15:0] quad_3_23_fu_527_p3; +reg [15:0] quad_3_17_fu_132; +wire [15:0] quad_3_20_fu_503_p3; +reg ap_block_state1; +wire [15:0] grp_fu_268_p1; +wire [15:0] grp_fu_272_p1; +wire [15:0] grp_fu_276_p1; +wire [11:0] tmp_fu_280_p3; +wire [8:0] tmp_s_fu_291_p3; +wire [12:0] zext_ln109_fu_287_p1; +wire [12:0] zext_ln109_3_fu_298_p1; +wire [12:0] sub_ln109_fu_302_p2; +wire [13:0] sub_ln109_cast_fu_308_p1; +wire [13:0] zext_ln109_4_fu_312_p1; +wire [0:0] icmp_ln103_fu_360_p2; +wire [63:0] val_fu_374_p5; +wire [15:0] tmp_54_fu_443_p3; +wire [15:0] data_V_fu_454_p1; +wire [0:0] p_Result_s_fu_457_p3; +wire [0:0] icmp_ln99_fu_472_p2; +wire [15:0] quad_0_fu_465_p3; +wire [0:0] icmp_ln99_3_fu_485_p2; +wire [15:0] quad_3_fu_477_p3; +wire [0:0] icmp_ln99_4_fu_498_p2; +wire [15:0] quad_3_19_fu_490_p3; +wire [15:0] quad_3_21_fu_511_p3; +wire [15:0] quad_3_22_fu_519_p3; +wire [15:0] quad_3_24_fu_535_p3; +wire [15:0] bitcast_ln109_6_fu_591_p1; +wire [15:0] bitcast_ln109_5_fu_587_p1; +wire [15:0] bitcast_ln109_4_fu_583_p1; +wire [15:0] bitcast_ln109_fu_579_p1; +wire ap_CS_fsm_state34; +reg [3:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +#0 ap_enable_reg_pp0_iter23 = 1'b0; +#0 ap_enable_reg_pp0_iter24 = 1'b0; +#0 ap_enable_reg_pp0_iter25 = 1'b0; +#0 ap_enable_reg_pp0_iter26 = 1'b0; +#0 ap_enable_reg_pp0_iter27 = 1'b0; +#0 ap_enable_reg_pp0_iter28 = 1'b0; +#0 ap_enable_reg_pp0_iter29 = 1'b0; +#0 ap_enable_reg_pp0_iter30 = 1'b0; +end + +td_fused_top_tdf4_l2_writeOutputs_1_running_sums_1 #( + .DataWidth( 16 ), + .AddressRange( 16 ), + .AddressWidth( 4 )) +running_sums_1_U( + .reset(ap_rst), + .clk(ap_clk), + .address0(running_sums_1_addr_reg_701_pp0_iter9_reg), + .ce0(running_sums_1_ce0), + .we0(running_sums_1_we0), + .d0(running_sums_1_d0), + .address1(running_sums_1_address1), + .ce1(running_sums_1_ce1), + .q1(running_sums_1_q1) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U645( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(running_sums_1_load_reg_716), + .din1(val_reg_711), + .dout(grp_fu_264_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U646( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(normalized_reg_762), + .din1(grp_fu_268_p1), + .dout(grp_fu_268_p2) +); + +td_fused_top_hsub_16ns_16ns_16_7_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 7 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_7_full_dsp_1_U647( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_reg_726), + .din1(grp_fu_272_p1), + .dout(grp_fu_272_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U648( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_752), + .din1(grp_fu_276_p1), + .dout(grp_fu_276_p2) +); + +td_fused_top_mux_464_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 64 ), + .dout_WIDTH( 16 )) +mux_464_16_1_1_U649( + .din0(l2_partial_sums_0_q0), + .din1(l2_partial_sums_1_q0), + .din2(l2_partial_sums_2_q0), + .din3(l2_partial_sums_3_q0), + .din4(val_fu_374_p5), + .dout(val_fu_374_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state34)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state3) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state3)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state3); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter23 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter23 <= ap_enable_reg_pp0_iter22; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter24 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter24 <= ap_enable_reg_pp0_iter23; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter25 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter25 <= ap_enable_reg_pp0_iter24; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter26 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter26 <= ap_enable_reg_pp0_iter25; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter27 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter27 <= ap_enable_reg_pp0_iter26; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter28 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter28 <= ap_enable_reg_pp0_iter27; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter29 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter29 <= ap_enable_reg_pp0_iter28; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter30 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter30 <= ap_enable_reg_pp0_iter29; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter30 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_327_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ochan_reg_253 <= add_ln86_fu_321_p2; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ochan_reg_253 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln109_reg_649 <= add_ln109_fu_315_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_327_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + and_ln103_reg_707 <= and_ln103_fu_366_p2; + lshr_ln_reg_676 <= {{ochan_reg_253[3:2]}}; + running_sums_1_addr_reg_701 <= zext_ln86_fu_333_p1; + trunc_ln89_reg_668 <= trunc_ln89_fu_338_p1; + zext_ln86_reg_663[4 : 0] <= zext_ln86_fu_333_p1[4 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + and_ln103_reg_707_pp0_iter10_reg <= and_ln103_reg_707_pp0_iter9_reg; + and_ln103_reg_707_pp0_iter11_reg <= and_ln103_reg_707_pp0_iter10_reg; + and_ln103_reg_707_pp0_iter12_reg <= and_ln103_reg_707_pp0_iter11_reg; + and_ln103_reg_707_pp0_iter13_reg <= and_ln103_reg_707_pp0_iter12_reg; + and_ln103_reg_707_pp0_iter14_reg <= and_ln103_reg_707_pp0_iter13_reg; + and_ln103_reg_707_pp0_iter15_reg <= and_ln103_reg_707_pp0_iter14_reg; + and_ln103_reg_707_pp0_iter16_reg <= and_ln103_reg_707_pp0_iter15_reg; + and_ln103_reg_707_pp0_iter17_reg <= and_ln103_reg_707_pp0_iter16_reg; + and_ln103_reg_707_pp0_iter18_reg <= and_ln103_reg_707_pp0_iter17_reg; + and_ln103_reg_707_pp0_iter19_reg <= and_ln103_reg_707_pp0_iter18_reg; + and_ln103_reg_707_pp0_iter20_reg <= and_ln103_reg_707_pp0_iter19_reg; + and_ln103_reg_707_pp0_iter21_reg <= and_ln103_reg_707_pp0_iter20_reg; + and_ln103_reg_707_pp0_iter22_reg <= and_ln103_reg_707_pp0_iter21_reg; + and_ln103_reg_707_pp0_iter23_reg <= and_ln103_reg_707_pp0_iter22_reg; + and_ln103_reg_707_pp0_iter24_reg <= and_ln103_reg_707_pp0_iter23_reg; + and_ln103_reg_707_pp0_iter25_reg <= and_ln103_reg_707_pp0_iter24_reg; + and_ln103_reg_707_pp0_iter26_reg <= and_ln103_reg_707_pp0_iter25_reg; + and_ln103_reg_707_pp0_iter27_reg <= and_ln103_reg_707_pp0_iter26_reg; + and_ln103_reg_707_pp0_iter28_reg <= and_ln103_reg_707_pp0_iter27_reg; + and_ln103_reg_707_pp0_iter29_reg <= and_ln103_reg_707_pp0_iter28_reg; + and_ln103_reg_707_pp0_iter2_reg <= and_ln103_reg_707_pp0_iter1_reg; + and_ln103_reg_707_pp0_iter3_reg <= and_ln103_reg_707_pp0_iter2_reg; + and_ln103_reg_707_pp0_iter4_reg <= and_ln103_reg_707_pp0_iter3_reg; + and_ln103_reg_707_pp0_iter5_reg <= and_ln103_reg_707_pp0_iter4_reg; + and_ln103_reg_707_pp0_iter6_reg <= and_ln103_reg_707_pp0_iter5_reg; + and_ln103_reg_707_pp0_iter7_reg <= and_ln103_reg_707_pp0_iter6_reg; + and_ln103_reg_707_pp0_iter8_reg <= and_ln103_reg_707_pp0_iter7_reg; + and_ln103_reg_707_pp0_iter9_reg <= and_ln103_reg_707_pp0_iter8_reg; + biased_reg_772 <= grp_fu_268_p2; + lshr_ln_reg_676_pp0_iter10_reg <= lshr_ln_reg_676_pp0_iter9_reg; + lshr_ln_reg_676_pp0_iter11_reg <= lshr_ln_reg_676_pp0_iter10_reg; + lshr_ln_reg_676_pp0_iter12_reg <= lshr_ln_reg_676_pp0_iter11_reg; + lshr_ln_reg_676_pp0_iter13_reg <= lshr_ln_reg_676_pp0_iter12_reg; + lshr_ln_reg_676_pp0_iter14_reg <= lshr_ln_reg_676_pp0_iter13_reg; + lshr_ln_reg_676_pp0_iter15_reg <= lshr_ln_reg_676_pp0_iter14_reg; + lshr_ln_reg_676_pp0_iter16_reg <= lshr_ln_reg_676_pp0_iter15_reg; + lshr_ln_reg_676_pp0_iter17_reg <= lshr_ln_reg_676_pp0_iter16_reg; + lshr_ln_reg_676_pp0_iter18_reg <= lshr_ln_reg_676_pp0_iter17_reg; + lshr_ln_reg_676_pp0_iter19_reg <= lshr_ln_reg_676_pp0_iter18_reg; + lshr_ln_reg_676_pp0_iter20_reg <= lshr_ln_reg_676_pp0_iter19_reg; + lshr_ln_reg_676_pp0_iter21_reg <= lshr_ln_reg_676_pp0_iter20_reg; + lshr_ln_reg_676_pp0_iter22_reg <= lshr_ln_reg_676_pp0_iter21_reg; + lshr_ln_reg_676_pp0_iter23_reg <= lshr_ln_reg_676_pp0_iter22_reg; + lshr_ln_reg_676_pp0_iter24_reg <= lshr_ln_reg_676_pp0_iter23_reg; + lshr_ln_reg_676_pp0_iter25_reg <= lshr_ln_reg_676_pp0_iter24_reg; + lshr_ln_reg_676_pp0_iter26_reg <= lshr_ln_reg_676_pp0_iter25_reg; + lshr_ln_reg_676_pp0_iter27_reg <= lshr_ln_reg_676_pp0_iter26_reg; + lshr_ln_reg_676_pp0_iter28_reg <= lshr_ln_reg_676_pp0_iter27_reg; + lshr_ln_reg_676_pp0_iter29_reg <= lshr_ln_reg_676_pp0_iter28_reg; + lshr_ln_reg_676_pp0_iter2_reg <= lshr_ln_reg_676_pp0_iter1_reg; + lshr_ln_reg_676_pp0_iter3_reg <= lshr_ln_reg_676_pp0_iter2_reg; + lshr_ln_reg_676_pp0_iter4_reg <= lshr_ln_reg_676_pp0_iter3_reg; + lshr_ln_reg_676_pp0_iter5_reg <= lshr_ln_reg_676_pp0_iter4_reg; + lshr_ln_reg_676_pp0_iter6_reg <= lshr_ln_reg_676_pp0_iter5_reg; + lshr_ln_reg_676_pp0_iter7_reg <= lshr_ln_reg_676_pp0_iter6_reg; + lshr_ln_reg_676_pp0_iter8_reg <= lshr_ln_reg_676_pp0_iter7_reg; + lshr_ln_reg_676_pp0_iter9_reg <= lshr_ln_reg_676_pp0_iter8_reg; + normalized_reg_762 <= grp_fu_276_p2; + running_sums_1_addr_reg_701_pp0_iter2_reg <= running_sums_1_addr_reg_701_pp0_iter1_reg; + running_sums_1_addr_reg_701_pp0_iter3_reg <= running_sums_1_addr_reg_701_pp0_iter2_reg; + running_sums_1_addr_reg_701_pp0_iter4_reg <= running_sums_1_addr_reg_701_pp0_iter3_reg; + running_sums_1_addr_reg_701_pp0_iter5_reg <= running_sums_1_addr_reg_701_pp0_iter4_reg; + running_sums_1_addr_reg_701_pp0_iter6_reg <= running_sums_1_addr_reg_701_pp0_iter5_reg; + running_sums_1_addr_reg_701_pp0_iter7_reg <= running_sums_1_addr_reg_701_pp0_iter6_reg; + running_sums_1_addr_reg_701_pp0_iter8_reg <= running_sums_1_addr_reg_701_pp0_iter7_reg; + running_sums_1_addr_reg_701_pp0_iter9_reg <= running_sums_1_addr_reg_701_pp0_iter8_reg; + sub_i_i_i_reg_752 <= grp_fu_272_p2; + sum_reg_726 <= grp_fu_264_p2; + tmp_178_i_i_reg_737 <= {{l2_adjustments_q0[31:16]}}; + tmp_178_i_i_reg_737_pp0_iter10_reg <= tmp_178_i_i_reg_737; + tmp_178_i_i_reg_737_pp0_iter11_reg <= tmp_178_i_i_reg_737_pp0_iter10_reg; + tmp_178_i_i_reg_737_pp0_iter12_reg <= tmp_178_i_i_reg_737_pp0_iter11_reg; + tmp_178_i_i_reg_737_pp0_iter13_reg <= tmp_178_i_i_reg_737_pp0_iter12_reg; + tmp_178_i_i_reg_737_pp0_iter14_reg <= tmp_178_i_i_reg_737_pp0_iter13_reg; + tmp_178_i_i_reg_737_pp0_iter15_reg <= tmp_178_i_i_reg_737_pp0_iter14_reg; + tmp_178_i_i_reg_737_pp0_iter16_reg <= tmp_178_i_i_reg_737_pp0_iter15_reg; + tmp_179_i_i_reg_742 <= {{l2_adjustments_q0[47:32]}}; + tmp_179_i_i_reg_742_pp0_iter10_reg <= tmp_179_i_i_reg_742; + tmp_179_i_i_reg_742_pp0_iter11_reg <= tmp_179_i_i_reg_742_pp0_iter10_reg; + tmp_179_i_i_reg_742_pp0_iter12_reg <= tmp_179_i_i_reg_742_pp0_iter11_reg; + tmp_179_i_i_reg_742_pp0_iter13_reg <= tmp_179_i_i_reg_742_pp0_iter12_reg; + tmp_179_i_i_reg_742_pp0_iter14_reg <= tmp_179_i_i_reg_742_pp0_iter13_reg; + tmp_179_i_i_reg_742_pp0_iter15_reg <= tmp_179_i_i_reg_742_pp0_iter14_reg; + tmp_179_i_i_reg_742_pp0_iter16_reg <= tmp_179_i_i_reg_742_pp0_iter15_reg; + tmp_179_i_i_reg_742_pp0_iter17_reg <= tmp_179_i_i_reg_742_pp0_iter16_reg; + tmp_179_i_i_reg_742_pp0_iter18_reg <= tmp_179_i_i_reg_742_pp0_iter17_reg; + tmp_179_i_i_reg_742_pp0_iter19_reg <= tmp_179_i_i_reg_742_pp0_iter18_reg; + tmp_179_i_i_reg_742_pp0_iter20_reg <= tmp_179_i_i_reg_742_pp0_iter19_reg; + tmp_179_i_i_reg_742_pp0_iter21_reg <= tmp_179_i_i_reg_742_pp0_iter20_reg; + trunc_ln89_reg_668_pp0_iter10_reg <= trunc_ln89_reg_668_pp0_iter9_reg; + trunc_ln89_reg_668_pp0_iter11_reg <= trunc_ln89_reg_668_pp0_iter10_reg; + trunc_ln89_reg_668_pp0_iter12_reg <= trunc_ln89_reg_668_pp0_iter11_reg; + trunc_ln89_reg_668_pp0_iter13_reg <= trunc_ln89_reg_668_pp0_iter12_reg; + trunc_ln89_reg_668_pp0_iter14_reg <= trunc_ln89_reg_668_pp0_iter13_reg; + trunc_ln89_reg_668_pp0_iter15_reg <= trunc_ln89_reg_668_pp0_iter14_reg; + trunc_ln89_reg_668_pp0_iter16_reg <= trunc_ln89_reg_668_pp0_iter15_reg; + trunc_ln89_reg_668_pp0_iter17_reg <= trunc_ln89_reg_668_pp0_iter16_reg; + trunc_ln89_reg_668_pp0_iter18_reg <= trunc_ln89_reg_668_pp0_iter17_reg; + trunc_ln89_reg_668_pp0_iter19_reg <= trunc_ln89_reg_668_pp0_iter18_reg; + trunc_ln89_reg_668_pp0_iter20_reg <= trunc_ln89_reg_668_pp0_iter19_reg; + trunc_ln89_reg_668_pp0_iter21_reg <= trunc_ln89_reg_668_pp0_iter20_reg; + trunc_ln89_reg_668_pp0_iter22_reg <= trunc_ln89_reg_668_pp0_iter21_reg; + trunc_ln89_reg_668_pp0_iter23_reg <= trunc_ln89_reg_668_pp0_iter22_reg; + trunc_ln89_reg_668_pp0_iter24_reg <= trunc_ln89_reg_668_pp0_iter23_reg; + trunc_ln89_reg_668_pp0_iter25_reg <= trunc_ln89_reg_668_pp0_iter24_reg; + trunc_ln89_reg_668_pp0_iter26_reg <= trunc_ln89_reg_668_pp0_iter25_reg; + trunc_ln89_reg_668_pp0_iter27_reg <= trunc_ln89_reg_668_pp0_iter26_reg; + trunc_ln89_reg_668_pp0_iter28_reg <= trunc_ln89_reg_668_pp0_iter27_reg; + trunc_ln89_reg_668_pp0_iter29_reg <= trunc_ln89_reg_668_pp0_iter28_reg; + trunc_ln89_reg_668_pp0_iter2_reg <= trunc_ln89_reg_668_pp0_iter1_reg; + trunc_ln89_reg_668_pp0_iter3_reg <= trunc_ln89_reg_668_pp0_iter2_reg; + trunc_ln89_reg_668_pp0_iter4_reg <= trunc_ln89_reg_668_pp0_iter3_reg; + trunc_ln89_reg_668_pp0_iter5_reg <= trunc_ln89_reg_668_pp0_iter4_reg; + trunc_ln89_reg_668_pp0_iter6_reg <= trunc_ln89_reg_668_pp0_iter5_reg; + trunc_ln89_reg_668_pp0_iter7_reg <= trunc_ln89_reg_668_pp0_iter6_reg; + trunc_ln89_reg_668_pp0_iter8_reg <= trunc_ln89_reg_668_pp0_iter7_reg; + trunc_ln89_reg_668_pp0_iter9_reg <= trunc_ln89_reg_668_pp0_iter8_reg; + trunc_ln95_reg_732 <= trunc_ln95_fu_388_p1; + zext_ln86_reg_663_pp0_iter2_reg[4 : 0] <= zext_ln86_reg_663_pp0_iter1_reg[4 : 0]; + zext_ln86_reg_663_pp0_iter3_reg[4 : 0] <= zext_ln86_reg_663_pp0_iter2_reg[4 : 0]; + zext_ln86_reg_663_pp0_iter4_reg[4 : 0] <= zext_ln86_reg_663_pp0_iter3_reg[4 : 0]; + zext_ln86_reg_663_pp0_iter5_reg[4 : 0] <= zext_ln86_reg_663_pp0_iter4_reg[4 : 0]; + zext_ln86_reg_663_pp0_iter6_reg[4 : 0] <= zext_ln86_reg_663_pp0_iter5_reg[4 : 0]; + zext_ln86_reg_663_pp0_iter7_reg[4 : 0] <= zext_ln86_reg_663_pp0_iter6_reg[4 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + and_ln103_reg_707_pp0_iter1_reg <= and_ln103_reg_707; + lshr_ln_reg_676_pp0_iter1_reg <= lshr_ln_reg_676; + running_sums_1_addr_reg_701_pp0_iter1_reg <= running_sums_1_addr_reg_701; + trunc_ln89_reg_668_pp0_iter1_reg <= trunc_ln89_reg_668; + val_reg_711 <= val_fu_374_p6; + zext_ln86_reg_663_pp0_iter1_reg[4 : 0] <= zext_ln86_reg_663[4 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + indices_01_read_reg_632 <= indices_01_dout; + indices_12_read_reg_638 <= indices_12_dout; + write4_read_reg_643 <= write4_dout; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter30 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + quad_3_14_fu_120 <= quad_3_26_fu_551_p3; + quad_3_15_fu_124 <= quad_3_25_fu_543_p3; + quad_3_16_fu_128 <= quad_3_23_fu_527_p3; + quad_3_17_fu_132 <= quad_3_20_fu_503_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_1_load_reg_716 <= running_sums_1_q1; + end +end + +always @ (*) begin + if ((icmp_ln86_fu_327_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state34)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter30 == 1'b0) & (ap_enable_reg_pp0_iter29 == 1'b0) & (ap_enable_reg_pp0_iter28 == 1'b0) & (ap_enable_reg_pp0_iter27 == 1'b0) & (ap_enable_reg_pp0_iter26 == 1'b0) & (ap_enable_reg_pp0_iter25 == 1'b0) & (ap_enable_reg_pp0_iter24 == 1'b0) & (ap_enable_reg_pp0_iter23 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state34)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_adjustments_ce0 = 1'b1; + end else begin + l2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_0_ce0 = 1'b1; + end else begin + l2_partial_sums_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_1_ce0 = 1'b1; + end else begin + l2_partial_sums_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_2_ce0 = 1'b1; + end else begin + l2_partial_sums_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_3_ce0 = 1'b1; + end else begin + l2_partial_sums_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter30 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter30 == 1'b1) & (1'd1 == and_ln103_reg_707_pp0_iter29_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter10 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_1_ce0 = 1'b1; + end else begin + running_sums_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + running_sums_1_ce1 = 1'b1; + end else begin + running_sums_1_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter10 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_1_we0 = 1'b1; + end else begin + running_sums_1_we0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write4_blk_n = write4_empty_n; + end else begin + write4_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write4_read = 1'b1; + end else begin + write4_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln86_fu_327_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter30 == 1'b1) & (ap_enable_reg_pp0_iter29 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter30 == 1'b1) & (ap_enable_reg_pp0_iter29 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln86_fu_327_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state34; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state34 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln109_fu_315_p2 = ((sub_ln109_cast_fu_308_p1) + (zext_ln109_4_fu_312_p1)); + +assign add_ln86_fu_321_p2 = (ochan_reg_253 + 5'd1); + +assign and_ln103_fu_366_p2 = (write4_read_reg_643 & icmp_ln103_fu_360_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state34 = ap_CS_fsm[32'd3]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state25_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state26_pp0_stage0_iter23 = ~(1'b1 == 1'b1); + +assign ap_block_state27_pp0_stage0_iter24 = ~(1'b1 == 1'b1); + +assign ap_block_state28_pp0_stage0_iter25 = ~(1'b1 == 1'b1); + +assign ap_block_state29_pp0_stage0_iter26 = ~(1'b1 == 1'b1); + +assign ap_block_state30_pp0_stage0_iter27 = ~(1'b1 == 1'b1); + +assign ap_block_state31_pp0_stage0_iter28 = ~(1'b1 == 1'b1); + +assign ap_block_state32_pp0_stage0_iter29 = ~(1'b1 == 1'b1); + +assign ap_block_state33_pp0_stage0_iter30 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln109_4_fu_583_p1 = quad_3_25_fu_543_p3; + +assign bitcast_ln109_5_fu_587_p1 = quad_3_23_fu_527_p3; + +assign bitcast_ln109_6_fu_591_p1 = quad_3_20_fu_503_p3; + +assign bitcast_ln109_fu_579_p1 = quad_3_26_fu_551_p3; + +assign data_V_fu_454_p1 = biased_reg_772; + +assign grp_fu_268_p1 = tmp_179_i_i_reg_742_pp0_iter21_reg; + +assign grp_fu_272_p1 = trunc_ln95_reg_732; + +assign grp_fu_276_p1 = tmp_178_i_i_reg_737_pp0_iter16_reg; + +assign icmp_ln103_fu_360_p2 = ((trunc_ln89_fu_338_p1 == 2'd3) ? 1'b1 : 1'b0); + +assign icmp_ln86_fu_327_p2 = ((ochan_reg_253 == 5'd16) ? 1'b1 : 1'b0); + +assign icmp_ln99_3_fu_485_p2 = ((trunc_ln89_reg_668_pp0_iter29_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln99_4_fu_498_p2 = ((trunc_ln89_reg_668_pp0_iter29_reg == 2'd0) ? 1'b1 : 1'b0); + +assign icmp_ln99_fu_472_p2 = ((trunc_ln89_reg_668_pp0_iter29_reg == 2'd2) ? 1'b1 : 1'b0); + +assign l2_adjustments_address0 = zext_ln86_reg_663_pp0_iter7_reg; + +assign l2_partial_sums_0_address0 = zext_ln89_2_fu_352_p1; + +assign l2_partial_sums_1_address0 = zext_ln89_2_fu_352_p1; + +assign l2_partial_sums_2_address0 = zext_ln89_2_fu_352_p1; + +assign l2_partial_sums_3_address0 = zext_ln89_2_fu_352_p1; + +assign lshr_ln_fu_342_p4 = {{ochan_reg_253[3:2]}}; + +assign out_data_address1 = sext_ln109_fu_449_p1; + +assign out_data_d1 = {{{{bitcast_ln109_6_fu_591_p1}, {bitcast_ln109_5_fu_587_p1}}, {bitcast_ln109_4_fu_583_p1}}, {bitcast_ln109_fu_579_p1}}; + +assign p_Result_s_fu_457_p3 = data_V_fu_454_p1[32'd15]; + +assign quad_0_fu_465_p3 = ((p_Result_s_fu_457_p3[0:0] == 1'b1) ? 16'd0 : biased_reg_772); + +assign quad_3_19_fu_490_p3 = ((icmp_ln99_3_fu_485_p2[0:0] == 1'b1) ? quad_3_17_fu_132 : quad_3_fu_477_p3); + +assign quad_3_20_fu_503_p3 = ((icmp_ln99_4_fu_498_p2[0:0] == 1'b1) ? quad_3_17_fu_132 : quad_3_19_fu_490_p3); + +assign quad_3_21_fu_511_p3 = ((icmp_ln99_fu_472_p2[0:0] == 1'b1) ? quad_0_fu_465_p3 : quad_3_16_fu_128); + +assign quad_3_22_fu_519_p3 = ((icmp_ln99_3_fu_485_p2[0:0] == 1'b1) ? quad_3_16_fu_128 : quad_3_21_fu_511_p3); + +assign quad_3_23_fu_527_p3 = ((icmp_ln99_4_fu_498_p2[0:0] == 1'b1) ? quad_3_16_fu_128 : quad_3_22_fu_519_p3); + +assign quad_3_24_fu_535_p3 = ((icmp_ln99_3_fu_485_p2[0:0] == 1'b1) ? quad_0_fu_465_p3 : quad_3_15_fu_124); + +assign quad_3_25_fu_543_p3 = ((icmp_ln99_4_fu_498_p2[0:0] == 1'b1) ? quad_3_15_fu_124 : quad_3_24_fu_535_p3); + +assign quad_3_26_fu_551_p3 = ((icmp_ln99_4_fu_498_p2[0:0] == 1'b1) ? quad_0_fu_465_p3 : quad_3_14_fu_120); + +assign quad_3_fu_477_p3 = ((icmp_ln99_fu_472_p2[0:0] == 1'b1) ? quad_3_17_fu_132 : quad_0_fu_465_p3); + +assign running_sums_1_address1 = zext_ln86_fu_333_p1; + +assign running_sums_1_d0 = ((write4_read_reg_643[0:0] == 1'b1) ? 16'd0 : sum_reg_726); + +assign sext_ln109_fu_449_p1 = (tmp_54_fu_443_p3); + +assign sub_ln109_cast_fu_308_p1 = (sub_ln109_fu_302_p2); + +assign sub_ln109_fu_302_p2 = (zext_ln109_fu_287_p1 - zext_ln109_3_fu_298_p1); + +assign tmp_54_fu_443_p3 = {{add_ln109_reg_649}, {lshr_ln_reg_676_pp0_iter29_reg}}; + +assign tmp_fu_280_p3 = {{indices_01_read_reg_632}, {6'd0}}; + +assign tmp_s_fu_291_p3 = {{indices_01_read_reg_632}, {3'd0}}; + +assign trunc_ln89_fu_338_p1 = ochan_reg_253[1:0]; + +assign trunc_ln95_fu_388_p1 = l2_adjustments_q0[15:0]; + +assign val_fu_374_p5 = trunc_ln89_reg_668; + +assign zext_ln109_3_fu_298_p1 = tmp_s_fu_291_p3; + +assign zext_ln109_4_fu_312_p1 = indices_12_read_reg_638; + +assign zext_ln109_fu_287_p1 = tmp_fu_280_p3; + +assign zext_ln86_fu_333_p1 = ochan_reg_253; + +assign zext_ln89_2_fu_352_p1 = lshr_ln_fu_342_p4; + +always @ (posedge ap_clk) begin + zext_ln86_reg_663[63:5] <= 59'b00000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_663_pp0_iter1_reg[63:5] <= 59'b00000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_663_pp0_iter2_reg[63:5] <= 59'b00000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_663_pp0_iter3_reg[63:5] <= 59'b00000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_663_pp0_iter4_reg[63:5] <= 59'b00000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_663_pp0_iter5_reg[63:5] <= 59'b00000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_663_pp0_iter6_reg[63:5] <= 59'b00000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_663_pp0_iter7_reg[63:5] <= 59'b00000000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf4_l2_writeOutputs_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_readFilters36 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_0_address0, + filter_data_0_ce0, + filter_data_0_q0, + filter_data_1_address0, + filter_data_1_ce0, + filter_data_1_q0, + filter_data_2_address0, + filter_data_2_ce0, + filter_data_2_q0, + filter_data_3_address0, + filter_data_3_ce0, + filter_data_3_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + weight_vecs_0_0_address0, + weight_vecs_0_0_ce0, + weight_vecs_0_0_we0, + weight_vecs_0_0_d0, + weight_vecs_0_1_address0, + weight_vecs_0_1_ce0, + weight_vecs_0_1_we0, + weight_vecs_0_1_d0, + weight_vecs_0_2_address0, + weight_vecs_0_2_ce0, + weight_vecs_0_2_we0, + weight_vecs_0_2_d0, + weight_vecs_0_3_address0, + weight_vecs_0_3_ce0, + weight_vecs_0_3_we0, + weight_vecs_0_3_d0, + weight_vecs_1_0_address0, + weight_vecs_1_0_ce0, + weight_vecs_1_0_we0, + weight_vecs_1_0_d0, + weight_vecs_1_1_address0, + weight_vecs_1_1_ce0, + weight_vecs_1_1_we0, + weight_vecs_1_1_d0, + weight_vecs_1_2_address0, + weight_vecs_1_2_ce0, + weight_vecs_1_2_we0, + weight_vecs_1_2_d0, + weight_vecs_1_3_address0, + weight_vecs_1_3_ce0, + weight_vecs_1_3_we0, + weight_vecs_1_3_d0, + weight_vecs_2_0_address0, + weight_vecs_2_0_ce0, + weight_vecs_2_0_we0, + weight_vecs_2_0_d0, + weight_vecs_2_1_address0, + weight_vecs_2_1_ce0, + weight_vecs_2_1_we0, + weight_vecs_2_1_d0, + weight_vecs_2_2_address0, + weight_vecs_2_2_ce0, + weight_vecs_2_2_we0, + weight_vecs_2_2_d0, + weight_vecs_2_3_address0, + weight_vecs_2_3_ce0, + weight_vecs_2_3_we0, + weight_vecs_2_3_d0, + weight_vecs_3_0_address0, + weight_vecs_3_0_ce0, + weight_vecs_3_0_we0, + weight_vecs_3_0_d0, + weight_vecs_3_1_address0, + weight_vecs_3_1_ce0, + weight_vecs_3_1_we0, + weight_vecs_3_1_d0, + weight_vecs_3_2_address0, + weight_vecs_3_2_ce0, + weight_vecs_3_2_we0, + weight_vecs_3_2_d0, + weight_vecs_3_3_address0, + weight_vecs_3_3_ce0, + weight_vecs_3_3_we0, + weight_vecs_3_3_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state5 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [10:0] filter_data_0_address0; +output filter_data_0_ce0; +input [63:0] filter_data_0_q0; +output [10:0] filter_data_1_address0; +output filter_data_1_ce0; +input [63:0] filter_data_1_q0; +output [10:0] filter_data_2_address0; +output filter_data_2_ce0; +input [63:0] filter_data_2_q0; +output [10:0] filter_data_3_address0; +output filter_data_3_ce0; +input [63:0] filter_data_3_q0; +input [4:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [5:0] weight_vecs_0_0_address0; +output weight_vecs_0_0_ce0; +output weight_vecs_0_0_we0; +output [15:0] weight_vecs_0_0_d0; +output [5:0] weight_vecs_0_1_address0; +output weight_vecs_0_1_ce0; +output weight_vecs_0_1_we0; +output [15:0] weight_vecs_0_1_d0; +output [5:0] weight_vecs_0_2_address0; +output weight_vecs_0_2_ce0; +output weight_vecs_0_2_we0; +output [15:0] weight_vecs_0_2_d0; +output [5:0] weight_vecs_0_3_address0; +output weight_vecs_0_3_ce0; +output weight_vecs_0_3_we0; +output [15:0] weight_vecs_0_3_d0; +output [5:0] weight_vecs_1_0_address0; +output weight_vecs_1_0_ce0; +output weight_vecs_1_0_we0; +output [15:0] weight_vecs_1_0_d0; +output [5:0] weight_vecs_1_1_address0; +output weight_vecs_1_1_ce0; +output weight_vecs_1_1_we0; +output [15:0] weight_vecs_1_1_d0; +output [5:0] weight_vecs_1_2_address0; +output weight_vecs_1_2_ce0; +output weight_vecs_1_2_we0; +output [15:0] weight_vecs_1_2_d0; +output [5:0] weight_vecs_1_3_address0; +output weight_vecs_1_3_ce0; +output weight_vecs_1_3_we0; +output [15:0] weight_vecs_1_3_d0; +output [5:0] weight_vecs_2_0_address0; +output weight_vecs_2_0_ce0; +output weight_vecs_2_0_we0; +output [15:0] weight_vecs_2_0_d0; +output [5:0] weight_vecs_2_1_address0; +output weight_vecs_2_1_ce0; +output weight_vecs_2_1_we0; +output [15:0] weight_vecs_2_1_d0; +output [5:0] weight_vecs_2_2_address0; +output weight_vecs_2_2_ce0; +output weight_vecs_2_2_we0; +output [15:0] weight_vecs_2_2_d0; +output [5:0] weight_vecs_2_3_address0; +output weight_vecs_2_3_ce0; +output weight_vecs_2_3_we0; +output [15:0] weight_vecs_2_3_d0; +output [5:0] weight_vecs_3_0_address0; +output weight_vecs_3_0_ce0; +output weight_vecs_3_0_we0; +output [15:0] weight_vecs_3_0_d0; +output [5:0] weight_vecs_3_1_address0; +output weight_vecs_3_1_ce0; +output weight_vecs_3_1_we0; +output [15:0] weight_vecs_3_1_d0; +output [5:0] weight_vecs_3_2_address0; +output weight_vecs_3_2_ce0; +output weight_vecs_3_2_we0; +output [15:0] weight_vecs_3_2_d0; +output [5:0] weight_vecs_3_3_address0; +output weight_vecs_3_3_ce0; +output weight_vecs_3_3_we0; +output [15:0] weight_vecs_3_3_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_0_ce0; +reg filter_data_1_ce0; +reg filter_data_2_ce0; +reg filter_data_3_ce0; +reg indices_23_read; +reg weight_vecs_0_0_ce0; +reg weight_vecs_0_0_we0; +reg weight_vecs_0_1_ce0; +reg weight_vecs_0_1_we0; +reg weight_vecs_0_2_ce0; +reg weight_vecs_0_2_we0; +reg weight_vecs_0_3_ce0; +reg weight_vecs_0_3_we0; +reg weight_vecs_1_0_ce0; +reg weight_vecs_1_0_we0; +reg weight_vecs_1_1_ce0; +reg weight_vecs_1_1_we0; +reg weight_vecs_1_2_ce0; +reg weight_vecs_1_2_we0; +reg weight_vecs_1_3_ce0; +reg weight_vecs_1_3_we0; +reg weight_vecs_2_0_ce0; +reg weight_vecs_2_0_we0; +reg weight_vecs_2_1_ce0; +reg weight_vecs_2_1_we0; +reg weight_vecs_2_2_ce0; +reg weight_vecs_2_2_we0; +reg weight_vecs_2_3_ce0; +reg weight_vecs_2_3_we0; +reg weight_vecs_3_0_ce0; +reg weight_vecs_3_0_we0; +reg weight_vecs_3_1_ce0; +reg weight_vecs_3_1_we0; +reg weight_vecs_3_2_ce0; +reg weight_vecs_3_2_we0; +reg weight_vecs_3_3_ce0; +reg weight_vecs_3_3_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [5:0] indvar_flatten13_reg_412; +reg [1:0] ii_reg_423; +reg [4:0] indvar_flatten_reg_434; +reg [1:0] jj_reg_445; +reg [4:0] kk_reg_456; +wire [8:0] sext_ln47_fu_489_p1; +reg [8:0] sext_ln47_reg_993; +wire [5:0] add_ln47_4_fu_493_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln47_fu_499_p2; +reg [0:0] icmp_ln47_reg_1003; +reg [0:0] icmp_ln47_reg_1003_pp0_iter1_reg; +wire [1:0] select_ln47_8_fu_533_p3; +reg [1:0] select_ln47_8_reg_1007; +wire [8:0] add_ln55_fu_545_p2; +reg [8:0] add_ln55_reg_1014; +wire [1:0] select_ln48_7_fu_584_p3; +reg [1:0] select_ln48_7_reg_1020; +reg [1:0] lshr_ln_reg_1027; +reg [1:0] lshr_ln_reg_1027_pp0_iter1_reg; +wire [4:0] add_ln49_fu_602_p2; +wire [4:0] select_ln48_8_fu_614_p3; +wire [5:0] add_ln55_8_fu_678_p2; +reg [5:0] add_ln55_8_reg_1043; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg [1:0] ap_phi_mux_ii_phi_fu_427_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_449_p4; +wire [63:0] tmp_31_fu_684_p3; +wire [63:0] sext_ln55_8_fu_701_p1; +wire [6:0] tmp_29_fu_471_p3; +wire [7:0] zext_ln55_21_fu_479_p1; +wire [7:0] zext_ln55_fu_467_p1; +wire [7:0] sub_ln55_fu_483_p2; +wire [0:0] icmp_ln48_fu_511_p2; +wire [1:0] add_ln47_fu_505_p2; +wire [8:0] zext_ln55_23_fu_541_p1; +wire [0:0] tmp_52_fu_550_p3; +wire [0:0] xor_ln49_fu_558_p2; +wire [1:0] select_ln47_fu_517_p3; +wire [0:0] or_ln47_fu_564_p2; +wire [4:0] select_ln47_7_fu_525_p3; +wire [1:0] add_ln48_fu_570_p2; +wire [4:0] select_ln48_fu_576_p3; +wire [4:0] add_ln48_4_fu_608_p2; +wire [10:0] tmp_51_fu_628_p3; +wire [61:0] sext_ln55_7_fu_635_p1; +wire [61:0] sext_ln55_fu_625_p1; +wire [3:0] tmp_30_fu_645_p3; +wire [4:0] zext_ln55_24_fu_652_p1; +wire [4:0] zext_ln55_22_fu_622_p1; +wire [4:0] sub_ln55_8_fu_656_p2; +wire [61:0] sub_ln55_7_fu_639_p2; +wire [61:0] zext_ln55_26_fu_669_p1; +wire [5:0] sext_ln48_fu_662_p1; +wire [5:0] zext_ln55_25_fu_666_p1; +wire [61:0] add_ln55_7_fu_672_p2; +wire [7:0] tmp_53_fu_695_p3; +wire [63:0] tmp_fu_721_p6; +wire [15:0] trunc_ln55_fu_735_p1; +wire [63:0] tmp_s_fu_744_p6; +wire [15:0] trunc_ln55_10_fu_758_p1; +wire [63:0] tmp_1_fu_767_p6; +wire [15:0] trunc_ln55_11_fu_781_p1; +wire [63:0] tmp_2_fu_790_p6; +wire [15:0] trunc_ln55_12_fu_804_p1; +wire [15:0] tmp_155_i_i_fu_813_p4; +wire [15:0] tmp_157_i_i_fu_828_p4; +wire [15:0] tmp_159_i_i_fu_843_p4; +wire [15:0] tmp_161_i_i_fu_858_p4; +wire [15:0] tmp_163_i_i_fu_873_p4; +wire [15:0] tmp_165_i_i_fu_888_p4; +wire [15:0] tmp_167_i_i_fu_903_p4; +wire [15:0] tmp_169_i_i_fu_918_p4; +wire [15:0] tmp_171_i_i_fu_933_p4; +wire [15:0] tmp_173_i_i_fu_948_p4; +wire [15:0] tmp_175_i_i_fu_963_p4; +wire [15:0] tmp_177_i_i_fu_978_p4; +wire ap_CS_fsm_state5; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_mux_416_64_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 64 ), + .din1_WIDTH( 64 ), + .din2_WIDTH( 64 ), + .din3_WIDTH( 64 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 64 )) +mux_416_64_1_1_U450( + .din0(filter_data_0_q0), + .din1(64'd0), + .din2(64'd0), + .din3(64'd0), + .din4(16'd0), + .dout(tmp_fu_721_p6) +); + +td_fused_top_mux_416_64_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 64 ), + .din1_WIDTH( 64 ), + .din2_WIDTH( 64 ), + .din3_WIDTH( 64 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 64 )) +mux_416_64_1_1_U451( + .din0(filter_data_1_q0), + .din1(64'd0), + .din2(64'd0), + .din3(64'd0), + .din4(16'd0), + .dout(tmp_s_fu_744_p6) +); + +td_fused_top_mux_416_64_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 64 ), + .din1_WIDTH( 64 ), + .din2_WIDTH( 64 ), + .din3_WIDTH( 64 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 64 )) +mux_416_64_1_1_U452( + .din0(filter_data_2_q0), + .din1(64'd0), + .din2(64'd0), + .din3(64'd0), + .din4(16'd0), + .dout(tmp_1_fu_767_p6) +); + +td_fused_top_mux_416_64_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 64 ), + .din1_WIDTH( 64 ), + .din2_WIDTH( 64 ), + .din3_WIDTH( 64 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 64 )) +mux_416_64_1_1_U453( + .din0(filter_data_3_q0), + .din1(64'd0), + .din2(64'd0), + .din3(64'd0), + .din4(16'd0), + .dout(tmp_2_fu_790_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state5)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_1003 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_423 <= select_ln47_8_reg_1007; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_423 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_499_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten13_reg_412 <= add_ln47_4_fu_493_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_412 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_499_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten_reg_434 <= select_ln48_8_fu_614_p3; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_434 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_1003 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_445 <= select_ln48_7_reg_1020; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_445 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_499_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + kk_reg_456 <= add_ln49_fu_602_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_456 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_1003 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln55_8_reg_1043 <= add_ln55_8_fu_678_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_499_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln55_reg_1014 <= add_ln55_fu_545_p2; + lshr_ln_reg_1027 <= {{select_ln48_fu_576_p3[3:2]}}; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln47_reg_1003 <= icmp_ln47_fu_499_p2; + icmp_ln47_reg_1003_pp0_iter1_reg <= icmp_ln47_reg_1003; + lshr_ln_reg_1027_pp0_iter1_reg <= lshr_ln_reg_1027; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_499_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln47_8_reg_1007 <= select_ln47_8_fu_533_p3; + select_ln48_7_reg_1020 <= select_ln48_7_fu_584_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sext_ln47_reg_993 <= sext_ln47_fu_489_p1; + end +end + +always @ (*) begin + if ((icmp_ln47_fu_499_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state5)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_1003 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_427_p4 = select_ln47_8_reg_1007; + end else begin + ap_phi_mux_ii_phi_fu_427_p4 = ii_reg_423; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_1003 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_449_p4 = select_ln48_7_reg_1020; + end else begin + ap_phi_mux_jj_phi_fu_449_p4 = jj_reg_445; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state5)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_0_ce0 = 1'b1; + end else begin + filter_data_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_1_ce0 = 1'b1; + end else begin + filter_data_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_2_ce0 = 1'b1; + end else begin + filter_data_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_3_ce0 = 1'b1; + end else begin + filter_data_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_ce0 = 1'b1; + end else begin + weight_vecs_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_we0 = 1'b1; + end else begin + weight_vecs_0_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_2_ce0 = 1'b1; + end else begin + weight_vecs_0_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_2_we0 = 1'b1; + end else begin + weight_vecs_0_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_3_ce0 = 1'b1; + end else begin + weight_vecs_0_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_3_we0 = 1'b1; + end else begin + weight_vecs_0_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_ce0 = 1'b1; + end else begin + weight_vecs_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_we0 = 1'b1; + end else begin + weight_vecs_1_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_ce0 = 1'b1; + end else begin + weight_vecs_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_we0 = 1'b1; + end else begin + weight_vecs_1_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_2_ce0 = 1'b1; + end else begin + weight_vecs_1_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_2_we0 = 1'b1; + end else begin + weight_vecs_1_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_3_ce0 = 1'b1; + end else begin + weight_vecs_1_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_3_we0 = 1'b1; + end else begin + weight_vecs_1_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_0_ce0 = 1'b1; + end else begin + weight_vecs_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_0_we0 = 1'b1; + end else begin + weight_vecs_2_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_1_ce0 = 1'b1; + end else begin + weight_vecs_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_1_we0 = 1'b1; + end else begin + weight_vecs_2_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_2_ce0 = 1'b1; + end else begin + weight_vecs_2_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_2_we0 = 1'b1; + end else begin + weight_vecs_2_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_3_ce0 = 1'b1; + end else begin + weight_vecs_2_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_3_we0 = 1'b1; + end else begin + weight_vecs_2_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_0_ce0 = 1'b1; + end else begin + weight_vecs_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_0_we0 = 1'b1; + end else begin + weight_vecs_3_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_1_ce0 = 1'b1; + end else begin + weight_vecs_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_1_we0 = 1'b1; + end else begin + weight_vecs_3_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_2_ce0 = 1'b1; + end else begin + weight_vecs_3_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_2_we0 = 1'b1; + end else begin + weight_vecs_3_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_3_ce0 = 1'b1; + end else begin + weight_vecs_3_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln47_reg_1003_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_3_we0 = 1'b1; + end else begin + weight_vecs_3_3_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln47_fu_499_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln47_fu_499_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state5; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln47_4_fu_493_p2 = (indvar_flatten13_reg_412 + 6'd1); + +assign add_ln47_fu_505_p2 = (ap_phi_mux_ii_phi_fu_427_p4 + 2'd1); + +assign add_ln48_4_fu_608_p2 = (indvar_flatten_reg_434 + 5'd1); + +assign add_ln48_fu_570_p2 = (select_ln47_fu_517_p3 + 2'd1); + +assign add_ln49_fu_602_p2 = (select_ln48_fu_576_p3 + 5'd4); + +assign add_ln55_7_fu_672_p2 = (sub_ln55_7_fu_639_p2 + zext_ln55_26_fu_669_p1); + +assign add_ln55_8_fu_678_p2 = ((sext_ln48_fu_662_p1) + (zext_ln55_25_fu_666_p1)); + +assign add_ln55_fu_545_p2 = ((sext_ln47_reg_993) + (zext_ln55_23_fu_541_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state5 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_0_address0 = tmp_31_fu_684_p3; + +assign filter_data_1_address0 = tmp_31_fu_684_p3; + +assign filter_data_2_address0 = tmp_31_fu_684_p3; + +assign filter_data_3_address0 = tmp_31_fu_684_p3; + +assign icmp_ln47_fu_499_p2 = ((indvar_flatten13_reg_412 == 6'd36) ? 1'b1 : 1'b0); + +assign icmp_ln48_fu_511_p2 = ((indvar_flatten_reg_434 == 5'd12) ? 1'b1 : 1'b0); + +assign or_ln47_fu_564_p2 = (xor_ln49_fu_558_p2 | icmp_ln48_fu_511_p2); + +assign select_ln47_7_fu_525_p3 = ((icmp_ln48_fu_511_p2[0:0] == 1'b1) ? 5'd0 : kk_reg_456); + +assign select_ln47_8_fu_533_p3 = ((icmp_ln48_fu_511_p2[0:0] == 1'b1) ? add_ln47_fu_505_p2 : ap_phi_mux_ii_phi_fu_427_p4); + +assign select_ln47_fu_517_p3 = ((icmp_ln48_fu_511_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_449_p4); + +assign select_ln48_7_fu_584_p3 = ((or_ln47_fu_564_p2[0:0] == 1'b1) ? select_ln47_fu_517_p3 : add_ln48_fu_570_p2); + +assign select_ln48_8_fu_614_p3 = ((icmp_ln48_fu_511_p2[0:0] == 1'b1) ? 5'd1 : add_ln48_4_fu_608_p2); + +assign select_ln48_fu_576_p3 = ((or_ln47_fu_564_p2[0:0] == 1'b1) ? select_ln47_7_fu_525_p3 : 5'd0); + +assign sext_ln47_fu_489_p1 = (sub_ln55_fu_483_p2); + +assign sext_ln48_fu_662_p1 = (sub_ln55_8_fu_656_p2); + +assign sext_ln55_7_fu_635_p1 = (tmp_51_fu_628_p3); + +assign sext_ln55_8_fu_701_p1 = (tmp_53_fu_695_p3); + +assign sext_ln55_fu_625_p1 = add_ln55_reg_1014; + +assign sub_ln55_7_fu_639_p2 = ((sext_ln55_7_fu_635_p1) - (sext_ln55_fu_625_p1)); + +assign sub_ln55_8_fu_656_p2 = (zext_ln55_24_fu_652_p1 - zext_ln55_22_fu_622_p1); + +assign sub_ln55_fu_483_p2 = (zext_ln55_21_fu_479_p1 - zext_ln55_fu_467_p1); + +assign tmp_155_i_i_fu_813_p4 = {{tmp_fu_721_p6[31:16]}}; + +assign tmp_157_i_i_fu_828_p4 = {{tmp_s_fu_744_p6[31:16]}}; + +assign tmp_159_i_i_fu_843_p4 = {{tmp_1_fu_767_p6[31:16]}}; + +assign tmp_161_i_i_fu_858_p4 = {{tmp_2_fu_790_p6[31:16]}}; + +assign tmp_163_i_i_fu_873_p4 = {{tmp_fu_721_p6[47:32]}}; + +assign tmp_165_i_i_fu_888_p4 = {{tmp_s_fu_744_p6[47:32]}}; + +assign tmp_167_i_i_fu_903_p4 = {{tmp_1_fu_767_p6[47:32]}}; + +assign tmp_169_i_i_fu_918_p4 = {{tmp_2_fu_790_p6[47:32]}}; + +assign tmp_171_i_i_fu_933_p4 = {{tmp_fu_721_p6[63:48]}}; + +assign tmp_173_i_i_fu_948_p4 = {{tmp_s_fu_744_p6[63:48]}}; + +assign tmp_175_i_i_fu_963_p4 = {{tmp_1_fu_767_p6[63:48]}}; + +assign tmp_177_i_i_fu_978_p4 = {{tmp_2_fu_790_p6[63:48]}}; + +assign tmp_29_fu_471_p3 = {{indices_23_dout}, {2'd0}}; + +assign tmp_30_fu_645_p3 = {{select_ln47_8_reg_1007}, {2'd0}}; + +assign tmp_31_fu_684_p3 = {{add_ln55_7_fu_672_p2}, {lshr_ln_reg_1027}}; + +assign tmp_51_fu_628_p3 = {{add_ln55_reg_1014}, {2'd0}}; + +assign tmp_52_fu_550_p3 = kk_reg_456[32'd4]; + +assign tmp_53_fu_695_p3 = {{add_ln55_8_reg_1043}, {lshr_ln_reg_1027_pp0_iter1_reg}}; + +assign trunc_ln55_10_fu_758_p1 = tmp_s_fu_744_p6[15:0]; + +assign trunc_ln55_11_fu_781_p1 = tmp_1_fu_767_p6[15:0]; + +assign trunc_ln55_12_fu_804_p1 = tmp_2_fu_790_p6[15:0]; + +assign trunc_ln55_fu_735_p1 = tmp_fu_721_p6[15:0]; + +assign weight_vecs_0_0_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_0_0_d0 = trunc_ln55_fu_735_p1; + +assign weight_vecs_0_1_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_0_1_d0 = tmp_155_i_i_fu_813_p4; + +assign weight_vecs_0_2_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_0_2_d0 = tmp_163_i_i_fu_873_p4; + +assign weight_vecs_0_3_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_0_3_d0 = tmp_171_i_i_fu_933_p4; + +assign weight_vecs_1_0_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_1_0_d0 = trunc_ln55_10_fu_758_p1; + +assign weight_vecs_1_1_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_1_1_d0 = tmp_157_i_i_fu_828_p4; + +assign weight_vecs_1_2_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_1_2_d0 = tmp_165_i_i_fu_888_p4; + +assign weight_vecs_1_3_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_1_3_d0 = tmp_173_i_i_fu_948_p4; + +assign weight_vecs_2_0_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_2_0_d0 = trunc_ln55_11_fu_781_p1; + +assign weight_vecs_2_1_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_2_1_d0 = tmp_159_i_i_fu_843_p4; + +assign weight_vecs_2_2_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_2_2_d0 = tmp_167_i_i_fu_903_p4; + +assign weight_vecs_2_3_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_2_3_d0 = tmp_175_i_i_fu_963_p4; + +assign weight_vecs_3_0_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_3_0_d0 = trunc_ln55_12_fu_804_p1; + +assign weight_vecs_3_1_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_3_1_d0 = tmp_161_i_i_fu_858_p4; + +assign weight_vecs_3_2_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_3_2_d0 = tmp_169_i_i_fu_918_p4; + +assign weight_vecs_3_3_address0 = sext_ln55_8_fu_701_p1; + +assign weight_vecs_3_3_d0 = tmp_177_i_i_fu_978_p4; + +assign xor_ln49_fu_558_p2 = (tmp_52_fu_550_p3 ^ 1'd1); + +assign zext_ln55_21_fu_479_p1 = tmp_29_fu_471_p3; + +assign zext_ln55_22_fu_622_p1 = select_ln47_8_reg_1007; + +assign zext_ln55_23_fu_541_p1 = select_ln47_8_fu_533_p3; + +assign zext_ln55_24_fu_652_p1 = tmp_30_fu_645_p3; + +assign zext_ln55_25_fu_666_p1 = select_ln48_7_reg_1020; + +assign zext_ln55_26_fu_669_p1 = select_ln48_7_reg_1020; + +assign zext_ln55_fu_467_p1 = indices_23_dout; + +endmodule //td_fused_top_tdf4_readFilters36 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_readInputs37 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_0_address0, + ifmap_vec_0_ce0, + ifmap_vec_0_we0, + ifmap_vec_0_d0, + ifmap_vec_1_address0, + ifmap_vec_1_ce0, + ifmap_vec_1_we0, + ifmap_vec_1_d0, + ifmap_vec_2_address0, + ifmap_vec_2_ce0, + ifmap_vec_2_we0, + ifmap_vec_2_d0, + ifmap_vec_3_address0, + ifmap_vec_3_ce0, + ifmap_vec_3_we0, + ifmap_vec_3_d0, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_pp0_stage0 = 4'd4; +parameter ap_ST_fsm_state7 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [13:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [5:0] ifmap_vec_0_address0; +output ifmap_vec_0_ce0; +output ifmap_vec_0_we0; +output [15:0] ifmap_vec_0_d0; +output [5:0] ifmap_vec_1_address0; +output ifmap_vec_1_ce0; +output ifmap_vec_1_we0; +output [15:0] ifmap_vec_1_d0; +output [5:0] ifmap_vec_2_address0; +output ifmap_vec_2_ce0; +output ifmap_vec_2_we0; +output [15:0] ifmap_vec_2_d0; +output [5:0] ifmap_vec_3_address0; +output ifmap_vec_3_ce0; +output ifmap_vec_3_we0; +output [15:0] ifmap_vec_3_d0; +output [5:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [11:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg ifmap_vec_0_ce0; +reg ifmap_vec_0_we0; +reg ifmap_vec_1_ce0; +reg ifmap_vec_1_we0; +reg ifmap_vec_2_ce0; +reg ifmap_vec_2_we0; +reg ifmap_vec_3_ce0; +reg ifmap_vec_3_we0; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [5:0] indvar_flatten47_reg_231; +reg [1:0] ii_reg_242; +reg [4:0] indvar_flatten_reg_254; +reg [1:0] jj_reg_265; +reg [4:0] kk_reg_277; +reg [15:0] indices_01_read_reg_909; +wire [5:0] trunc_ln319_fu_288_p1; +reg [5:0] trunc_ln319_reg_914; +reg [15:0] indices_12_read_reg_919; +wire [11:0] empty_fu_293_p1; +reg [11:0] empty_reg_924; +wire [17:0] p_cast_i_i_fu_310_p1; +reg [17:0] p_cast_i_i_reg_931; +wire ap_CS_fsm_state2; +wire [17:0] sext_ln22_fu_320_p1; +reg [17:0] sext_ln22_reg_937; +wire [5:0] p_cast_fu_324_p2; +reg [5:0] p_cast_reg_943; +wire [0:0] or_ln23_16_fu_343_p2; +reg [0:0] or_ln23_16_reg_949; +wire [11:0] p_mid137_fu_349_p2; +reg [11:0] p_mid137_reg_954; +wire [5:0] add_ln19_4_fu_354_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state4_pp0_stage0_iter1; +wire ap_block_state5_pp0_stage0_iter2; +wire ap_block_state6_pp0_stage0_iter3; +wire ap_block_pp0_stage0_11001; +wire [0:0] empty_107_fu_369_p2; +reg [0:0] empty_107_reg_964; +wire [0:0] is_padding_fu_404_p2; +reg [0:0] is_padding_reg_969; +wire [0:0] icmp_ln19_fu_410_p2; +reg [0:0] icmp_ln19_reg_976; +reg [0:0] icmp_ln19_reg_976_pp0_iter1_reg; +reg [0:0] icmp_ln19_reg_976_pp0_iter2_reg; +wire [1:0] add_ln19_fu_416_p2; +reg [1:0] add_ln19_reg_980; +wire [0:0] icmp_ln20_fu_422_p2; +reg [0:0] icmp_ln20_reg_985; +wire [1:0] select_ln19_23_fu_444_p3; +reg [1:0] select_ln19_23_reg_994; +wire [0:0] p_mid113_fu_461_p2; +reg [0:0] p_mid113_reg_1001; +wire [0:0] or_ln19_fu_481_p2; +reg [0:0] or_ln19_reg_1007; +reg [0:0] or_ln19_reg_1007_pp0_iter1_reg; +wire [1:0] add_ln20_fu_487_p2; +reg [1:0] add_ln20_reg_1014; +wire [1:0] select_ln20_16_fu_501_p3; +reg [1:0] select_ln20_16_reg_1019; +wire [17:0] add_ln22_5_fu_513_p2; +reg [17:0] add_ln22_5_reg_1025; +reg [1:0] lshr_ln_reg_1031; +reg [1:0] lshr_ln_reg_1031_pp0_iter1_reg; +reg [1:0] lshr_ln_reg_1031_pp0_iter2_reg; +wire [4:0] add_ln25_fu_528_p2; +wire [4:0] select_ln20_20_fu_540_p3; +wire [11:0] select_ln19_28_fu_666_p3; +reg [11:0] select_ln19_28_reg_1047; +wire [5:0] add_ln33_fu_676_p2; +reg [5:0] add_ln33_reg_1052; +reg [5:0] add_ln33_reg_1052_pp0_iter2_reg; +wire [0:0] or_ln23_20_fu_703_p2; +reg [0:0] or_ln23_20_reg_1057; +wire [0:0] select_ln20_17_fu_709_p3; +reg [0:0] select_ln20_17_reg_1062; +reg [0:0] select_ln20_17_reg_1062_pp0_iter2_reg; +wire [11:0] p_mid1_fu_734_p2; +reg [11:0] p_mid1_reg_1070; +wire [12:0] sub_ln32_fu_770_p2; +reg [12:0] sub_ln32_reg_1075; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state4; +reg ap_enable_reg_pp0_iter3; +reg [1:0] ap_phi_mux_ii_phi_fu_246_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_269_p4; +wire [63:0] sext_ln32_fu_808_p1; +wire [63:0] sext_ln33_fu_819_p1; +reg ap_block_state1; +wire [16:0] zext_ln19_fu_301_p1; +wire [16:0] empty_105_fu_304_p2; +wire [16:0] j_cast_i_i_fu_298_p1; +wire [16:0] add_ln22_fu_314_p2; +wire [0:0] tmp_45_fu_329_p3; +wire [0:0] icmp_ln24_fu_337_p2; +wire [17:0] ii_cast_i_i_fu_360_p1; +wire [17:0] empty_106_fu_364_p2; +wire [17:0] zext_ln20_fu_375_p1; +wire [17:0] add_ln22_4_fu_379_p2; +wire [0:0] tmp_46_fu_384_p3; +wire [0:0] icmp_ln24_4_fu_392_p2; +wire [0:0] or_ln23_fu_398_p2; +wire [17:0] ii_cast_i_i_mid1_fu_452_p1; +wire [17:0] p_mid111_fu_456_p2; +wire [0:0] tmp_47_fu_467_p3; +wire [0:0] xor_ln25_fu_475_p2; +wire [1:0] select_ln19_fu_428_p3; +wire [4:0] select_ln19_22_fu_436_p3; +wire [17:0] zext_ln20_4_fu_509_p1; +wire [4:0] select_ln20_fu_493_p3; +wire [4:0] add_ln20_4_fu_534_p2; +wire [5:0] ii_cast_fu_548_p1; +wire [5:0] p_cast28_i_i_fu_552_p2; +wire [2:0] zext_ln22_fu_557_p1; +wire [2:0] tmp1_fu_568_p2; +wire [11:0] tmp1_cast_fu_574_p1; +wire [11:0] empty_108_fu_578_p2; +wire [3:0] tmp_fu_593_p3; +wire [4:0] zext_ln33_8_fu_600_p1; +wire [4:0] zext_ln33_fu_590_p1; +wire [4:0] sub_ln33_fu_604_p2; +wire [5:0] ii_cast_mid1_fu_614_p1; +wire [5:0] p_cast28_i_i_mid1_fu_617_p2; +wire [0:0] or_ln23_18_fu_634_p2; +wire [5:0] row_coord_int_mid131_fu_644_p3; +wire [5:0] row_coord_int_fu_561_p3; +wire [11:0] col_coord_int_mid139_fu_652_p3; +wire [11:0] col_coord_int_fu_583_p3; +wire [5:0] sub_ln33_cast_fu_610_p1; +wire [5:0] zext_ln33_9_fu_673_p1; +wire [0:0] tmp_48_fu_685_p3; +wire [0:0] icmp_ln24_5_fu_692_p2; +wire [0:0] or_ln23_19_fu_697_p2; +wire [0:0] select_ln19_25_fu_629_p3; +wire [0:0] select_ln19_26_fu_638_p3; +wire [5:0] select_ln19_24_fu_622_p3; +wire [2:0] zext_ln22_4_fu_682_p1; +wire [2:0] tmp1_mid1_fu_724_p2; +wire [11:0] tmp1_cast_mid1_fu_730_p1; +wire [5:0] select_ln19_27_fu_659_p3; +wire [5:0] row_coord_int_mid1_fu_716_p3; +wire [5:0] select_ln20_18_fu_739_p3; +wire [11:0] tmp_s_fu_746_p3; +wire [8:0] tmp_28_fu_758_p3; +wire [12:0] zext_ln32_fu_754_p1; +wire [12:0] zext_ln32_32_fu_766_p1; +wire [11:0] col_coord_int_mid1_fu_776_p3; +wire [11:0] select_ln20_19_fu_785_p3; +wire [13:0] sext_ln20_fu_782_p1; +wire [13:0] zext_ln32_33_fu_791_p1; +wire [13:0] add_ln32_fu_795_p2; +wire [15:0] tmp_49_fu_801_p3; +wire [7:0] tmp_50_fu_813_p3; +wire [15:0] trunc_ln32_fu_827_p1; +wire [15:0] in_data_elem_fu_831_p1; +wire [15:0] tmp_144_i_i_fu_843_p4; +wire [15:0] in_data_elem_6_fu_853_p1; +wire [15:0] tmp_145_i_i_fu_865_p4; +wire [15:0] in_data_elem_7_fu_875_p1; +wire [15:0] tmp_146_i_i_fu_887_p4; +wire [15:0] in_data_elem_8_fu_897_p1; +wire ap_CS_fsm_state7; +reg [3:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state4)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_242 <= select_ln19_23_reg_994; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ii_reg_242 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten47_reg_231 <= add_ln19_4_fu_354_p2; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + indvar_flatten47_reg_231 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten_reg_254 <= select_ln20_20_fu_540_p3; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + indvar_flatten_reg_254 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_265 <= select_ln20_16_reg_1019; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + jj_reg_265 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + kk_reg_277 <= add_ln25_fu_528_p2; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + kk_reg_277 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln19_reg_980 <= add_ln19_fu_416_p2; + add_ln20_reg_1014 <= add_ln20_fu_487_p2; + add_ln22_5_reg_1025 <= add_ln22_5_fu_513_p2; + icmp_ln20_reg_985 <= icmp_ln20_fu_422_p2; + lshr_ln_reg_1031 <= {{select_ln20_fu_493_p3[3:2]}}; + or_ln19_reg_1007 <= or_ln19_fu_481_p2; + p_mid113_reg_1001 <= p_mid113_fu_461_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln33_reg_1052 <= add_ln33_fu_676_p2; + or_ln23_20_reg_1057 <= or_ln23_20_fu_703_p2; + select_ln20_17_reg_1062 <= select_ln20_17_fu_709_p3; + sub_ln32_reg_1075[12 : 3] <= sub_ln32_fu_770_p2[12 : 3]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln33_reg_1052_pp0_iter2_reg <= add_ln33_reg_1052; + icmp_ln19_reg_976_pp0_iter2_reg <= icmp_ln19_reg_976_pp0_iter1_reg; + lshr_ln_reg_1031_pp0_iter2_reg <= lshr_ln_reg_1031_pp0_iter1_reg; + select_ln20_17_reg_1062_pp0_iter2_reg <= select_ln20_17_reg_1062; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + empty_107_reg_964 <= empty_107_fu_369_p2; + icmp_ln19_reg_976 <= icmp_ln19_fu_410_p2; + icmp_ln19_reg_976_pp0_iter1_reg <= icmp_ln19_reg_976; + is_padding_reg_969 <= is_padding_fu_404_p2; + lshr_ln_reg_1031_pp0_iter1_reg <= lshr_ln_reg_1031; + or_ln19_reg_1007_pp0_iter1_reg <= or_ln19_reg_1007; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + empty_reg_924 <= empty_fu_293_p1; + indices_01_read_reg_909 <= indices_01_dout; + indices_12_read_reg_919 <= indices_12_dout; + trunc_ln319_reg_914 <= trunc_ln319_fu_288_p1; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + or_ln23_16_reg_949 <= or_ln23_16_fu_343_p2; + p_cast_i_i_reg_931 <= p_cast_i_i_fu_310_p1; + p_cast_reg_943 <= p_cast_fu_324_p2; + p_mid137_reg_954 <= p_mid137_fu_349_p2; + sext_ln22_reg_937 <= sext_ln22_fu_320_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (or_ln19_reg_1007 == 1'd0) & (icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + p_mid1_reg_1070 <= p_mid1_fu_734_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln19_23_reg_994 <= select_ln19_23_fu_444_p3; + select_ln20_16_reg_1019 <= select_ln20_16_fu_501_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (or_ln19_reg_1007 == 1'd1) & (icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + select_ln19_28_reg_1047 <= select_ln19_28_fu_666_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_condition_pp0_exit_iter1_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state4 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_246_p4 = select_ln19_23_reg_994; + end else begin + ap_phi_mux_ii_phi_fu_246_p4 = ii_reg_242; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_269_p4 = select_ln20_16_reg_1019; + end else begin + ap_phi_mux_jj_phi_fu_269_p4 = jj_reg_265; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln19_reg_976_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_we0 = 1'b1; + end else begin + ifmap_vec_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_1_ce0 = 1'b1; + end else begin + ifmap_vec_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln19_reg_976_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_1_we0 = 1'b1; + end else begin + ifmap_vec_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_2_ce0 = 1'b1; + end else begin + ifmap_vec_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln19_reg_976_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_2_we0 = 1'b1; + end else begin + ifmap_vec_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_3_ce0 = 1'b1; + end else begin + ifmap_vec_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln19_reg_976_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_3_we0 = 1'b1; + end else begin + ifmap_vec_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0)) & ~((ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln19_4_fu_354_p2 = (indvar_flatten47_reg_231 + 6'd1); + +assign add_ln19_fu_416_p2 = (ap_phi_mux_ii_phi_fu_246_p4 + 2'd1); + +assign add_ln20_4_fu_534_p2 = (indvar_flatten_reg_254 + 5'd1); + +assign add_ln20_fu_487_p2 = (select_ln19_fu_428_p3 + 2'd1); + +assign add_ln22_4_fu_379_p2 = ((sext_ln22_reg_937) + (zext_ln20_fu_375_p1)); + +assign add_ln22_5_fu_513_p2 = ((sext_ln22_reg_937) + (zext_ln20_4_fu_509_p1)); + +assign add_ln22_fu_314_p2 = ((j_cast_i_i_fu_298_p1) + (17'd131071)); + +assign add_ln25_fu_528_p2 = (select_ln20_fu_493_p3 + 5'd4); + +assign add_ln32_fu_795_p2 = ((sext_ln20_fu_782_p1) + (zext_ln32_33_fu_791_p1)); + +assign add_ln33_fu_676_p2 = ((sub_ln33_cast_fu_610_p1) + (zext_ln33_9_fu_673_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd3]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign col_coord_int_fu_583_p3 = ((is_padding_reg_969[0:0] == 1'b1) ? 12'd0 : empty_108_fu_578_p2); + +assign col_coord_int_mid139_fu_652_p3 = ((or_ln23_18_fu_634_p2[0:0] == 1'b1) ? 12'd0 : p_mid137_reg_954); + +assign col_coord_int_mid1_fu_776_p3 = ((or_ln23_20_reg_1057[0:0] == 1'b1) ? 12'd0 : p_mid1_reg_1070); + +assign empty_105_fu_304_p2 = ((zext_ln19_fu_301_p1) + (17'd131071)); + +assign empty_106_fu_364_p2 = ((p_cast_i_i_reg_931) + (ii_cast_i_i_fu_360_p1)); + +assign empty_107_fu_369_p2 = ((empty_106_fu_364_p2 > 18'd55) ? 1'b1 : 1'b0); + +assign empty_108_fu_578_p2 = ((tmp1_cast_fu_574_p1) + (empty_reg_924)); + +assign empty_fu_293_p1 = indices_12_dout[11:0]; + +assign icmp_ln19_fu_410_p2 = ((indvar_flatten47_reg_231 == 6'd36) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_422_p2 = ((indvar_flatten_reg_254 == 5'd12) ? 1'b1 : 1'b0); + +assign icmp_ln24_4_fu_392_p2 = (((add_ln22_4_fu_379_p2) > (18'd55)) ? 1'b1 : 1'b0); + +assign icmp_ln24_5_fu_692_p2 = (((add_ln22_5_reg_1025) > (18'd55)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_337_p2 = (((add_ln22_fu_314_p2) > (17'd55)) ? 1'b1 : 1'b0); + +assign ifmap_vec_0_address0 = sext_ln33_fu_819_p1; + +assign ifmap_vec_0_d0 = ((select_ln20_17_reg_1062_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_fu_831_p1); + +assign ifmap_vec_1_address0 = sext_ln33_fu_819_p1; + +assign ifmap_vec_1_d0 = ((select_ln20_17_reg_1062_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_6_fu_853_p1); + +assign ifmap_vec_2_address0 = sext_ln33_fu_819_p1; + +assign ifmap_vec_2_d0 = ((select_ln20_17_reg_1062_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_7_fu_875_p1); + +assign ifmap_vec_3_address0 = sext_ln33_fu_819_p1; + +assign ifmap_vec_3_d0 = ((select_ln20_17_reg_1062_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_8_fu_897_p1); + +assign ii_cast_fu_548_p1 = ii_reg_242; + +assign ii_cast_i_i_fu_360_p1 = ap_phi_mux_ii_phi_fu_246_p4; + +assign ii_cast_i_i_mid1_fu_452_p1 = add_ln19_fu_416_p2; + +assign ii_cast_mid1_fu_614_p1 = add_ln19_reg_980; + +assign in_data_address0 = sext_ln32_fu_808_p1; + +assign in_data_elem_6_fu_853_p1 = tmp_144_i_i_fu_843_p4; + +assign in_data_elem_7_fu_875_p1 = tmp_145_i_i_fu_865_p4; + +assign in_data_elem_8_fu_897_p1 = tmp_146_i_i_fu_887_p4; + +assign in_data_elem_fu_831_p1 = trunc_ln32_fu_827_p1; + +assign indices_01_out_din = indices_01_dout[5:0]; + +assign indices_12_out_din = indices_12_dout[11:0]; + +assign is_padding_fu_404_p2 = (or_ln23_fu_398_p2 | empty_107_fu_369_p2); + +assign j_cast_i_i_fu_298_p1 = indices_12_read_reg_919; + +assign or_ln19_fu_481_p2 = (xor_ln25_fu_475_p2 | icmp_ln20_fu_422_p2); + +assign or_ln23_16_fu_343_p2 = (tmp_45_fu_329_p3 | icmp_ln24_fu_337_p2); + +assign or_ln23_18_fu_634_p2 = (p_mid113_reg_1001 | or_ln23_16_reg_949); + +assign or_ln23_19_fu_697_p2 = (tmp_48_fu_685_p3 | icmp_ln24_5_fu_692_p2); + +assign or_ln23_20_fu_703_p2 = (select_ln19_25_fu_629_p3 | or_ln23_19_fu_697_p2); + +assign or_ln23_fu_398_p2 = (tmp_46_fu_384_p3 | icmp_ln24_4_fu_392_p2); + +assign p_cast28_i_i_fu_552_p2 = (p_cast_reg_943 + ii_cast_fu_548_p1); + +assign p_cast28_i_i_mid1_fu_617_p2 = (p_cast_reg_943 + ii_cast_mid1_fu_614_p1); + +assign p_cast_fu_324_p2 = ((trunc_ln319_reg_914) + (6'd63)); + +assign p_cast_i_i_fu_310_p1 = (empty_105_fu_304_p2); + +assign p_mid111_fu_456_p2 = ((p_cast_i_i_reg_931) + (ii_cast_i_i_mid1_fu_452_p1)); + +assign p_mid113_fu_461_p2 = ((p_mid111_fu_456_p2 > 18'd55) ? 1'b1 : 1'b0); + +assign p_mid137_fu_349_p2 = ((empty_reg_924) + (12'd4095)); + +assign p_mid1_fu_734_p2 = ((tmp1_cast_mid1_fu_730_p1) + (empty_reg_924)); + +assign row_coord_int_fu_561_p3 = ((is_padding_reg_969[0:0] == 1'b1) ? 6'd0 : p_cast28_i_i_fu_552_p2); + +assign row_coord_int_mid131_fu_644_p3 = ((or_ln23_18_fu_634_p2[0:0] == 1'b1) ? 6'd0 : p_cast28_i_i_mid1_fu_617_p2); + +assign row_coord_int_mid1_fu_716_p3 = ((or_ln23_20_fu_703_p2[0:0] == 1'b1) ? 6'd0 : select_ln19_24_fu_622_p3); + +assign select_ln19_22_fu_436_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? 5'd0 : kk_reg_277); + +assign select_ln19_23_fu_444_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? add_ln19_fu_416_p2 : ap_phi_mux_ii_phi_fu_246_p4); + +assign select_ln19_24_fu_622_p3 = ((icmp_ln20_reg_985[0:0] == 1'b1) ? p_cast28_i_i_mid1_fu_617_p2 : p_cast28_i_i_fu_552_p2); + +assign select_ln19_25_fu_629_p3 = ((icmp_ln20_reg_985[0:0] == 1'b1) ? p_mid113_reg_1001 : empty_107_reg_964); + +assign select_ln19_26_fu_638_p3 = ((icmp_ln20_reg_985[0:0] == 1'b1) ? or_ln23_18_fu_634_p2 : is_padding_reg_969); + +assign select_ln19_27_fu_659_p3 = ((icmp_ln20_reg_985[0:0] == 1'b1) ? row_coord_int_mid131_fu_644_p3 : row_coord_int_fu_561_p3); + +assign select_ln19_28_fu_666_p3 = ((icmp_ln20_reg_985[0:0] == 1'b1) ? col_coord_int_mid139_fu_652_p3 : col_coord_int_fu_583_p3); + +assign select_ln19_fu_428_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_269_p4); + +assign select_ln20_16_fu_501_p3 = ((or_ln19_fu_481_p2[0:0] == 1'b1) ? select_ln19_fu_428_p3 : add_ln20_fu_487_p2); + +assign select_ln20_17_fu_709_p3 = ((or_ln19_reg_1007[0:0] == 1'b1) ? select_ln19_26_fu_638_p3 : or_ln23_20_fu_703_p2); + +assign select_ln20_18_fu_739_p3 = ((or_ln19_reg_1007[0:0] == 1'b1) ? select_ln19_27_fu_659_p3 : row_coord_int_mid1_fu_716_p3); + +assign select_ln20_19_fu_785_p3 = ((or_ln19_reg_1007_pp0_iter1_reg[0:0] == 1'b1) ? select_ln19_28_reg_1047 : col_coord_int_mid1_fu_776_p3); + +assign select_ln20_20_fu_540_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? 5'd1 : add_ln20_4_fu_534_p2); + +assign select_ln20_fu_493_p3 = ((or_ln19_fu_481_p2[0:0] == 1'b1) ? select_ln19_22_fu_436_p3 : 5'd0); + +assign sext_ln20_fu_782_p1 = (sub_ln32_reg_1075); + +assign sext_ln22_fu_320_p1 = add_ln22_fu_314_p2; + +assign sext_ln32_fu_808_p1 = (tmp_49_fu_801_p3); + +assign sext_ln33_fu_819_p1 = (tmp_50_fu_813_p3); + +assign sub_ln32_fu_770_p2 = (zext_ln32_fu_754_p1 - zext_ln32_32_fu_766_p1); + +assign sub_ln33_cast_fu_610_p1 = (sub_ln33_fu_604_p2); + +assign sub_ln33_fu_604_p2 = (zext_ln33_8_fu_600_p1 - zext_ln33_fu_590_p1); + +assign tmp1_cast_fu_574_p1 = (tmp1_fu_568_p2); + +assign tmp1_cast_mid1_fu_730_p1 = (tmp1_mid1_fu_724_p2); + +assign tmp1_fu_568_p2 = ((zext_ln22_fu_557_p1) + (3'd7)); + +assign tmp1_mid1_fu_724_p2 = ((zext_ln22_4_fu_682_p1) + (3'd7)); + +assign tmp_144_i_i_fu_843_p4 = {{in_data_q0[31:16]}}; + +assign tmp_145_i_i_fu_865_p4 = {{in_data_q0[47:32]}}; + +assign tmp_146_i_i_fu_887_p4 = {{in_data_q0[63:48]}}; + +assign tmp_28_fu_758_p3 = {{select_ln20_18_fu_739_p3}, {3'd0}}; + +assign tmp_45_fu_329_p3 = add_ln22_fu_314_p2[32'd16]; + +assign tmp_46_fu_384_p3 = add_ln22_4_fu_379_p2[32'd17]; + +assign tmp_47_fu_467_p3 = kk_reg_277[32'd4]; + +assign tmp_48_fu_685_p3 = add_ln22_5_reg_1025[32'd17]; + +assign tmp_49_fu_801_p3 = {{add_ln32_fu_795_p2}, {lshr_ln_reg_1031_pp0_iter1_reg}}; + +assign tmp_50_fu_813_p3 = {{add_ln33_reg_1052_pp0_iter2_reg}, {lshr_ln_reg_1031_pp0_iter2_reg}}; + +assign tmp_fu_593_p3 = {{select_ln19_23_reg_994}, {2'd0}}; + +assign tmp_s_fu_746_p3 = {{select_ln20_18_fu_739_p3}, {6'd0}}; + +assign trunc_ln319_fu_288_p1 = indices_01_dout[5:0]; + +assign trunc_ln32_fu_827_p1 = in_data_q0[15:0]; + +assign xor_ln25_fu_475_p2 = (tmp_47_fu_467_p3 ^ 1'd1); + +assign zext_ln19_fu_301_p1 = indices_01_read_reg_909; + +assign zext_ln20_4_fu_509_p1 = add_ln20_fu_487_p2; + +assign zext_ln20_fu_375_p1 = ap_phi_mux_jj_phi_fu_269_p4; + +assign zext_ln22_4_fu_682_p1 = add_ln20_reg_1014; + +assign zext_ln22_fu_557_p1 = jj_reg_265; + +assign zext_ln32_32_fu_766_p1 = tmp_28_fu_758_p3; + +assign zext_ln32_33_fu_791_p1 = select_ln20_19_fu_785_p3; + +assign zext_ln32_fu_754_p1 = tmp_s_fu_746_p3; + +assign zext_ln33_8_fu_600_p1 = tmp_fu_593_p3; + +assign zext_ln33_9_fu_673_p1 = select_ln20_16_reg_1019; + +assign zext_ln33_fu_590_p1 = select_ln19_23_reg_994; + +always @ (posedge ap_clk) begin + sub_ln32_reg_1075[2:0] <= 3'b000; +end + +endmodule //td_fused_top_tdf4_readInputs37 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_110 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_0_address0, + filter_data_0_ce0, + filter_data_0_d0, + filter_data_0_q0, + filter_data_0_we0, + filter_data_0_address1, + filter_data_0_ce1, + filter_data_0_d1, + filter_data_0_q1, + filter_data_0_we1, + filter_data_1_address0, + filter_data_1_ce0, + filter_data_1_d0, + filter_data_1_q0, + filter_data_1_we0, + filter_data_1_address1, + filter_data_1_ce1, + filter_data_1_d1, + filter_data_1_q1, + filter_data_1_we1, + filter_data_2_address0, + filter_data_2_ce0, + filter_data_2_d0, + filter_data_2_q0, + filter_data_2_we0, + filter_data_2_address1, + filter_data_2_ce1, + filter_data_2_d1, + filter_data_2_q1, + filter_data_2_we1, + filter_data_3_address0, + filter_data_3_ce0, + filter_data_3_d0, + filter_data_3_q0, + filter_data_3_we0, + filter_data_3_address1, + filter_data_3_ce1, + filter_data_3_d1, + filter_data_3_q1, + filter_data_3_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [13:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [13:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [14:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [14:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [11:0] filter_data_0_address0; +output filter_data_0_ce0; +output [31:0] filter_data_0_d0; +input [31:0] filter_data_0_q0; +output filter_data_0_we0; +output [11:0] filter_data_0_address1; +output filter_data_0_ce1; +output [31:0] filter_data_0_d1; +input [31:0] filter_data_0_q1; +output filter_data_0_we1; +output [11:0] filter_data_1_address0; +output filter_data_1_ce0; +output [31:0] filter_data_1_d0; +input [31:0] filter_data_1_q0; +output filter_data_1_we0; +output [11:0] filter_data_1_address1; +output filter_data_1_ce1; +output [31:0] filter_data_1_d1; +input [31:0] filter_data_1_q1; +output filter_data_1_we1; +output [11:0] filter_data_2_address0; +output filter_data_2_ce0; +output [31:0] filter_data_2_d0; +input [31:0] filter_data_2_q0; +output filter_data_2_we0; +output [11:0] filter_data_2_address1; +output filter_data_2_ce1; +output [31:0] filter_data_2_d1; +input [31:0] filter_data_2_q1; +output filter_data_2_we1; +output [11:0] filter_data_3_address0; +output filter_data_3_ce0; +output [31:0] filter_data_3_d0; +input [31:0] filter_data_3_q0; +output filter_data_3_we0; +output [11:0] filter_data_3_address1; +output filter_data_3_ce1; +output [31:0] filter_data_3_d1; +input [31:0] filter_data_3_q1; +output filter_data_3_we1; +output [6:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [6:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [13:0] dataflow_in_loop_TOP_LOOP48139_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP48139_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48139_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP48139_U0_in_data_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP48139_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP48139_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48139_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP48139_U0_in_data_we1; +wire [11:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_address0; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_ce0; +wire [31:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_d0; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_we0; +wire [11:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_address1; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_ce1; +wire [31:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_d1; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_we1; +wire [11:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_address0; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_ce0; +wire [31:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_d0; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_we0; +wire [11:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_address1; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_ce1; +wire [31:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_d1; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_we1; +wire [11:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_address0; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_ce0; +wire [31:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_d0; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_we0; +wire [11:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_address1; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_ce1; +wire [31:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_d1; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_we1; +wire [11:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_address0; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_ce0; +wire [31:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_d0; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_we0; +wire [11:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_address1; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_ce1; +wire [31:0] dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_d1; +wire dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_we1; +wire [6:0] dataflow_in_loop_TOP_LOOP48139_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP48139_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP48139_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP48139_U0_adjustments_we0; +wire [6:0] dataflow_in_loop_TOP_LOOP48139_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP48139_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP48139_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP48139_U0_adjustments_we1; +wire [14:0] dataflow_in_loop_TOP_LOOP48139_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP48139_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48139_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP48139_U0_out_data_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP48139_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP48139_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48139_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP48139_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP48139_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP48139_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP48139_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP48139_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP48139_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP48139_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP48139_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP48139_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP48139_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [16:0] loop_dataflow_input_count; +reg [16:0] loop_dataflow_output_count; +wire [16:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP48139_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP48139_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 17'd0; +#0 loop_dataflow_output_count = 17'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP48139 dataflow_in_loop_TOP_LOOP48139_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP48139_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP48139_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP48139_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP48139_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP48139_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP48139_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP48139_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP48139_U0_in_data_we1), + .filter_data_0_address0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_address0), + .filter_data_0_ce0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_ce0), + .filter_data_0_d0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_d0), + .filter_data_0_q0(filter_data_0_q0), + .filter_data_0_we0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_we0), + .filter_data_0_address1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_address1), + .filter_data_0_ce1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_ce1), + .filter_data_0_d1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_d1), + .filter_data_0_q1(32'd0), + .filter_data_0_we1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_we1), + .filter_data_1_address0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_address0), + .filter_data_1_ce0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_ce0), + .filter_data_1_d0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_d0), + .filter_data_1_q0(filter_data_1_q0), + .filter_data_1_we0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_we0), + .filter_data_1_address1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_address1), + .filter_data_1_ce1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_ce1), + .filter_data_1_d1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_d1), + .filter_data_1_q1(32'd0), + .filter_data_1_we1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_we1), + .filter_data_2_address0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_address0), + .filter_data_2_ce0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_ce0), + .filter_data_2_d0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_d0), + .filter_data_2_q0(filter_data_2_q0), + .filter_data_2_we0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_we0), + .filter_data_2_address1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_address1), + .filter_data_2_ce1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_ce1), + .filter_data_2_d1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_d1), + .filter_data_2_q1(32'd0), + .filter_data_2_we1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_we1), + .filter_data_3_address0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_address0), + .filter_data_3_ce0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_ce0), + .filter_data_3_d0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_d0), + .filter_data_3_q0(filter_data_3_q0), + .filter_data_3_we0(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_we0), + .filter_data_3_address1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_address1), + .filter_data_3_ce1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_ce1), + .filter_data_3_d1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_d1), + .filter_data_3_q1(32'd0), + .filter_data_3_we1(dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP48139_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP48139_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP48139_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP48139_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP48139_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP48139_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP48139_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP48139_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP48139_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP48139_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP48139_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP48139_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP48139_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP48139_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP48139_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP48139_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP48139_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP48139_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP48139_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP48139_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP48139_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP48139_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP48139_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 17'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP48139_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 17'd1); + end else if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP48139_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= 17'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 17'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48139_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP48139_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 17'd1); + end else if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48139_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP48139_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= 17'd0; + end + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48139_U0_ap_done == 1'b1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == 17'd0) & (ap_start == 1'b0) & (dataflow_in_loop_TOP_LOOP48139_U0_ap_idle == 1'b1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP48139_U0_ap_ready == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP48139_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP48139_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP48139_U0_adjustments_address0; + +assign adjustments_address1 = 7'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP48139_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP48139_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP48139_U0_ap_ready; + +assign bound_minus_1 = (17'd100352 - 17'd1); + +assign dataflow_in_loop_TOP_LOOP48139_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP48139_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP48139_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP48139_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP48139_U0_start_write = 1'b0; + +assign filter_data_0_address0 = dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_address0; + +assign filter_data_0_address1 = 12'd0; + +assign filter_data_0_ce0 = dataflow_in_loop_TOP_LOOP48139_U0_filter_data_0_ce0; + +assign filter_data_0_ce1 = 1'b0; + +assign filter_data_0_d0 = 32'd0; + +assign filter_data_0_d1 = 32'd0; + +assign filter_data_0_we0 = 1'b0; + +assign filter_data_0_we1 = 1'b0; + +assign filter_data_1_address0 = dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_address0; + +assign filter_data_1_address1 = 12'd0; + +assign filter_data_1_ce0 = dataflow_in_loop_TOP_LOOP48139_U0_filter_data_1_ce0; + +assign filter_data_1_ce1 = 1'b0; + +assign filter_data_1_d0 = 32'd0; + +assign filter_data_1_d1 = 32'd0; + +assign filter_data_1_we0 = 1'b0; + +assign filter_data_1_we1 = 1'b0; + +assign filter_data_2_address0 = dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_address0; + +assign filter_data_2_address1 = 12'd0; + +assign filter_data_2_ce0 = dataflow_in_loop_TOP_LOOP48139_U0_filter_data_2_ce0; + +assign filter_data_2_ce1 = 1'b0; + +assign filter_data_2_d0 = 32'd0; + +assign filter_data_2_d1 = 32'd0; + +assign filter_data_2_we0 = 1'b0; + +assign filter_data_2_we1 = 1'b0; + +assign filter_data_3_address0 = dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_address0; + +assign filter_data_3_address1 = 12'd0; + +assign filter_data_3_ce0 = dataflow_in_loop_TOP_LOOP48139_U0_filter_data_3_ce0; + +assign filter_data_3_ce1 = 1'b0; + +assign filter_data_3_d0 = 32'd0; + +assign filter_data_3_d1 = 32'd0; + +assign filter_data_3_we0 = 1'b0; + +assign filter_data_3_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP48139_U0_in_data_address0; + +assign in_data_address1 = 14'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP48139_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP48139_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 15'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP48139_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP48139_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP48139_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP48139_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP48139_U0_out_data_write; + +endmodule //td_fused_top_tdf5_110 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_in1_address0, + accum_in1_ce0, + accum_in1_q0, + accum_in1_address1, + accum_in1_ce1, + accum_in1_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_pp0_stage0 = 11'd2; +parameter ap_ST_fsm_pp0_stage1 = 11'd4; +parameter ap_ST_fsm_pp0_stage2 = 11'd8; +parameter ap_ST_fsm_pp0_stage3 = 11'd16; +parameter ap_ST_fsm_pp0_stage4 = 11'd32; +parameter ap_ST_fsm_pp0_stage5 = 11'd64; +parameter ap_ST_fsm_pp0_stage6 = 11'd128; +parameter ap_ST_fsm_state17 = 11'd256; +parameter ap_ST_fsm_state18 = 11'd512; +parameter ap_ST_fsm_state19 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [6:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [6:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [6:0] accum_in1_address0; +output accum_in1_ce0; +input [15:0] accum_in1_q0; +output [6:0] accum_in1_address1; +output accum_in1_ce1; +input [15:0] accum_in1_q1; +output [3:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [3:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[6:0] accum_in_address0; +reg accum_in_ce0; +reg[6:0] accum_in_address1; +reg accum_in_ce1; +reg[6:0] accum_in1_address0; +reg accum_in1_ce0; +reg[6:0] accum_in1_address1; +reg accum_in1_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] x_reg_263; +reg [15:0] psum_2_03_reg_275; +reg [15:0] psum_1_02_reg_287; +reg [15:0] psum_0_01_reg_299; +reg [15:0] psum_15_016_reg_311; +reg [15:0] psum_14_015_reg_323; +reg [15:0] psum_13_014_reg_335; +reg [15:0] psum_12_013_reg_347; +reg [15:0] psum_11_012_reg_359; +reg [15:0] psum_10_011_reg_371; +reg [15:0] psum_9_010_reg_383; +reg [15:0] psum_8_09_reg_395; +reg [15:0] psum_7_08_reg_407; +reg [15:0] psum_6_07_reg_419; +reg [15:0] psum_5_06_reg_431; +reg [15:0] psum_4_05_reg_443; +reg [15:0] psum_3_04_reg_455; +wire [0:0] icmp_ln49_fu_536_p2; +reg [0:0] icmp_ln49_reg_775; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state9_pp0_stage0_iter1; +wire ap_block_state16_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln49_reg_775_pp0_iter1_reg; +wire [6:0] lshr_ln_fu_542_p4; +reg [6:0] lshr_ln_reg_779; +reg [15:0] accum_in_load_reg_809; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state10_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in1_load_reg_814; +reg [15:0] accum_in_load_15_reg_819; +reg [15:0] accum_in1_load_8_reg_824; +reg [15:0] accum_in_load_16_reg_849; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state11_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in1_load_9_reg_854; +reg [15:0] accum_in_load_17_reg_859; +reg [15:0] accum_in1_load_10_reg_864; +reg [15:0] accum_in_load_18_reg_889; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state12_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in1_load_11_reg_894; +reg [15:0] accum_in_load_19_reg_899; +reg [15:0] accum_in1_load_12_reg_904; +reg [15:0] accum_in_load_20_reg_929; +wire ap_CS_fsm_pp0_stage4; +wire ap_block_state6_pp0_stage4_iter0; +wire ap_block_state13_pp0_stage4_iter1; +wire ap_block_pp0_stage4_11001; +reg [15:0] accum_in1_load_13_reg_934; +reg [15:0] accum_in_load_21_reg_939; +reg [15:0] accum_in1_load_14_reg_944; +wire [7:0] add_ln49_fu_636_p2; +reg [7:0] add_ln49_reg_949; +wire ap_CS_fsm_pp0_stage6; +wire ap_block_state8_pp0_stage6_iter0; +wire ap_block_state15_pp0_stage6_iter1; +wire ap_block_pp0_stage6_11001; +wire [15:0] grp_fu_508_p2; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_513_p2; +wire [15:0] grp_fu_518_p2; +wire ap_CS_fsm_pp0_stage5; +wire ap_block_state7_pp0_stage5_iter0; +wire ap_block_state14_pp0_stage5_iter1; +wire ap_block_pp0_stage5_11001; +reg ap_enable_reg_pp0_iter2; +wire [4:0] add_ln57_fu_659_p2; +wire ap_CS_fsm_state18; +wire [0:0] tmp_fu_642_p3; +reg ap_block_state1; +wire ap_block_pp0_stage3_subdone; +reg ap_condition_pp0_exit_iter0_state5; +wire ap_block_pp0_stage6_subdone; +wire ap_block_pp0_stage0_subdone; +reg [7:0] ap_phi_mux_x_phi_fu_267_p4; +wire ap_block_pp0_stage0; +wire ap_block_pp0_stage2; +wire [15:0] ap_phi_mux_psum_15_016_phi_fu_315_p4; +wire [15:0] ap_phi_mux_psum_14_015_phi_fu_327_p4; +wire ap_block_pp0_stage6; +wire [15:0] ap_phi_mux_psum_13_014_phi_fu_339_p4; +wire [15:0] ap_phi_mux_psum_12_013_phi_fu_351_p4; +wire [15:0] ap_phi_mux_psum_11_012_phi_fu_363_p4; +wire ap_block_pp0_stage5; +wire [15:0] ap_phi_mux_psum_10_011_phi_fu_375_p4; +wire [15:0] ap_phi_mux_psum_9_010_phi_fu_387_p4; +wire [15:0] ap_phi_mux_psum_8_09_phi_fu_399_p4; +wire ap_block_pp0_stage4; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_411_p4; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_423_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_435_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_447_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_459_p4; +reg [4:0] q_reg_467; +wire ap_CS_fsm_state17; +reg [15:0] ap_phi_mux_phi_ln69_phi_fu_481_p16; +wire [3:0] trunc_ln57_fu_655_p1; +wire [63:0] zext_ln53_fu_552_p1; +wire [63:0] zext_ln53_8_fu_564_p1; +wire [63:0] zext_ln53_9_fu_575_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln53_10_fu_586_p1; +wire [63:0] zext_ln53_11_fu_597_p1; +wire [63:0] zext_ln53_12_fu_608_p1; +wire [63:0] zext_ln53_13_fu_619_p1; +wire [63:0] zext_ln53_14_fu_630_p1; +wire [63:0] zext_ln57_fu_650_p1; +wire [63:0] zext_ln57_2_fu_671_p1; +reg [15:0] grp_fu_508_p0; +reg [15:0] grp_fu_508_p1; +reg [15:0] grp_fu_513_p0; +reg [15:0] grp_fu_513_p1; +reg [15:0] grp_fu_518_p0; +reg [15:0] grp_fu_518_p1; +wire [6:0] or_ln53_fu_558_p2; +wire [6:0] or_ln53_7_fu_570_p2; +wire [6:0] or_ln53_8_fu_581_p2; +wire [6:0] or_ln53_9_fu_592_p2; +wire [6:0] or_ln53_10_fu_603_p2; +wire [6:0] or_ln53_11_fu_614_p2; +wire [6:0] or_ln53_12_fu_625_p2; +wire [3:0] or_ln57_fu_665_p2; +wire [0:0] icmp_ln69_fu_676_p2; +wire [0:0] icmp_ln69_7_fu_690_p2; +wire [15:0] select_ln69_fu_682_p3; +wire [0:0] icmp_ln69_8_fu_704_p2; +wire [15:0] select_ln69_7_fu_696_p3; +wire [0:0] icmp_ln69_9_fu_718_p2; +wire [15:0] select_ln69_8_fu_710_p3; +wire [0:0] icmp_ln69_10_fu_732_p2; +wire [15:0] select_ln69_9_fu_724_p3; +wire [0:0] icmp_ln69_11_fu_746_p2; +wire [15:0] select_ln69_10_fu_738_p3; +wire [0:0] icmp_ln69_12_fu_760_p2; +wire [15:0] select_ln69_11_fu_752_p3; +wire ap_CS_fsm_state19; +reg [10:0] ap_NS_fsm; +wire ap_block_pp0_stage1_subdone; +wire ap_block_pp0_stage2_subdone; +wire ap_block_pp0_stage4_subdone; +wire ap_block_pp0_stage5_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_728; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U778( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_508_p0), + .din1(grp_fu_508_p1), + .dout(grp_fu_508_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U779( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_513_p0), + .din1(grp_fu_513_p1), + .dout(grp_fu_513_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U780( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_518_p0), + .din1(grp_fu_518_p1), + .dout(grp_fu_518_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state19)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state5) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6_subdone))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6_subdone)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + q_reg_467 <= 5'd0; + end else if (((tmp_fu_642_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + q_reg_467 <= add_ln57_fu_659_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + x_reg_263 <= add_ln49_reg_949; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_263 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001))) begin + accum_in1_load_10_reg_864 <= accum_in1_q0; + accum_in1_load_9_reg_854 <= accum_in1_q1; + accum_in_load_16_reg_849 <= accum_in_q1; + accum_in_load_17_reg_859 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + accum_in1_load_11_reg_894 <= accum_in1_q1; + accum_in1_load_12_reg_904 <= accum_in1_q0; + accum_in_load_18_reg_889 <= accum_in_q1; + accum_in_load_19_reg_899 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4_11001))) begin + accum_in1_load_13_reg_934 <= accum_in1_q1; + accum_in1_load_14_reg_944 <= accum_in1_q0; + accum_in_load_20_reg_929 <= accum_in_q1; + accum_in_load_21_reg_939 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + accum_in1_load_8_reg_824 <= accum_in1_q0; + accum_in1_load_reg_814 <= accum_in1_q1; + accum_in_load_15_reg_819 <= accum_in_q0; + accum_in_load_reg_809 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6_11001))) begin + add_ln49_reg_949 <= add_ln49_fu_636_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln49_reg_775 <= icmp_ln49_fu_536_p2; + icmp_ln49_reg_775_pp0_iter1_reg <= icmp_ln49_reg_775; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_fu_536_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + lshr_ln_reg_779 <= {{ap_phi_mux_x_phi_fu_267_p4[7:1]}}; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage2_11001))) begin + psum_0_01_reg_299 <= grp_fu_508_p2; + psum_1_02_reg_287 <= grp_fu_513_p2; + psum_2_03_reg_275 <= grp_fu_518_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage5_11001))) begin + psum_10_011_reg_371 <= grp_fu_513_p2; + psum_11_012_reg_359 <= grp_fu_518_p2; + psum_9_010_reg_383 <= grp_fu_508_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage6) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage6_11001))) begin + psum_12_013_reg_347 <= grp_fu_508_p2; + psum_13_014_reg_335 <= grp_fu_513_p2; + psum_14_015_reg_323 <= grp_fu_518_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + psum_15_016_reg_311 <= grp_fu_508_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + psum_3_04_reg_455 <= grp_fu_508_p2; + psum_4_05_reg_443 <= grp_fu_513_p2; + psum_5_06_reg_431 <= grp_fu_518_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage4_11001))) begin + psum_6_07_reg_419 <= grp_fu_508_p2; + psum_7_08_reg_407 <= grp_fu_513_p2; + psum_8_09_reg_395 <= grp_fu_518_p2; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in1_address0 = zext_ln53_14_fu_630_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in1_address0 = zext_ln53_12_fu_608_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in1_address0 = zext_ln53_10_fu_586_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in1_address0 = zext_ln53_8_fu_564_p1; + end else begin + accum_in1_address0 = 'bx; + end + end else begin + accum_in1_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in1_address1 = zext_ln53_13_fu_619_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in1_address1 = zext_ln53_11_fu_597_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in1_address1 = zext_ln53_9_fu_575_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in1_address1 = zext_ln53_fu_552_p1; + end else begin + accum_in1_address1 = 'bx; + end + end else begin + accum_in1_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in1_ce0 = 1'b1; + end else begin + accum_in1_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in1_ce1 = 1'b1; + end else begin + accum_in1_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in_address0 = zext_ln53_14_fu_630_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in_address0 = zext_ln53_12_fu_608_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in_address0 = zext_ln53_10_fu_586_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in_address0 = zext_ln53_8_fu_564_p1; + end else begin + accum_in_address0 = 'bx; + end + end else begin + accum_in_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in_address1 = zext_ln53_13_fu_619_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in_address1 = zext_ln53_11_fu_597_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in_address1 = zext_ln53_9_fu_575_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in_address1 = zext_ln53_fu_552_p1; + end else begin + accum_in_address1 = 'bx; + end + end else begin + accum_in_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state18)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state18)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_642_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_642_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln49_reg_775 == 1'd0)) begin + ap_condition_pp0_exit_iter0_state5 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state5 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state19)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_642_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + if ((trunc_ln57_fu_655_p1 == 4'd0)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_0_01_reg_299; + end else if ((1'b1 == ap_condition_728)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_14_015_reg_323; + end else if ((trunc_ln57_fu_655_p1 == 4'd12)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_12_013_reg_347; + end else if ((trunc_ln57_fu_655_p1 == 4'd10)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_10_011_reg_371; + end else if ((trunc_ln57_fu_655_p1 == 4'd8)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_8_09_reg_395; + end else if ((trunc_ln57_fu_655_p1 == 4'd6)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_6_07_reg_419; + end else if ((trunc_ln57_fu_655_p1 == 4'd4)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_4_05_reg_443; + end else if ((trunc_ln57_fu_655_p1 == 4'd2)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_2_03_reg_275; + end else begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = 'bx; + end + end else begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln49_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_x_phi_fu_267_p4 = add_ln49_reg_949; + end else begin + ap_phi_mux_x_phi_fu_267_p4 = x_reg_263; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state19)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_508_p0 = ap_phi_mux_psum_15_016_phi_fu_315_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_508_p0 = ap_phi_mux_psum_12_013_phi_fu_351_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_508_p0 = ap_phi_mux_psum_9_010_phi_fu_387_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_508_p0 = ap_phi_mux_psum_6_07_phi_fu_423_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_508_p0 = ap_phi_mux_psum_3_04_phi_fu_459_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_508_p0 = grp_fu_508_p2; + end else begin + grp_fu_508_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_508_p1 = accum_in1_load_14_reg_944; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_508_p1 = accum_in_load_20_reg_929; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_508_p1 = accum_in1_load_11_reg_894; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_508_p1 = accum_in_load_17_reg_859; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_508_p1 = accum_in1_load_8_reg_824; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_508_p1 = accum_in_load_reg_809; + end else begin + grp_fu_508_p1 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_513_p0 = ap_phi_mux_psum_13_014_phi_fu_339_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_513_p0 = ap_phi_mux_psum_10_011_phi_fu_375_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_513_p0 = ap_phi_mux_psum_7_08_phi_fu_411_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_513_p0 = ap_phi_mux_psum_4_05_phi_fu_447_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_513_p0 = grp_fu_513_p2; + end else begin + grp_fu_513_p0 = 'bx; + end + end else begin + grp_fu_513_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_513_p1 = accum_in1_load_13_reg_934; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_513_p1 = accum_in_load_19_reg_899; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_513_p1 = accum_in1_load_10_reg_864; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_513_p1 = accum_in_load_16_reg_849; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_513_p1 = accum_in1_load_reg_814; + end else begin + grp_fu_513_p1 = 'bx; + end + end else begin + grp_fu_513_p1 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_518_p0 = ap_phi_mux_psum_14_015_phi_fu_327_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_518_p0 = ap_phi_mux_psum_11_012_phi_fu_363_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_518_p0 = ap_phi_mux_psum_8_09_phi_fu_399_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_518_p0 = ap_phi_mux_psum_5_06_phi_fu_435_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_518_p0 = grp_fu_518_p2; + end else begin + grp_fu_518_p0 = 'bx; + end + end else begin + grp_fu_518_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_518_p1 = accum_in_load_21_reg_939; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_518_p1 = accum_in1_load_12_reg_904; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_518_p1 = accum_in_load_18_reg_889; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_518_p1 = accum_in1_load_9_reg_854; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_518_p1 = accum_in_load_15_reg_819; + end else begin + grp_fu_518_p1 = 'bx; + end + end else begin + grp_fu_518_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if (((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state17; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((1'b0 == ap_block_pp0_stage2_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((~((icmp_ln49_reg_775 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_subdone)) & (1'b0 == ap_block_pp0_stage3_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end else if (((icmp_ln49_reg_775 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state17; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_pp0_stage4 : begin + if ((1'b0 == ap_block_pp0_stage4_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end + end + ap_ST_fsm_pp0_stage5 : begin + if ((1'b0 == ap_block_pp0_stage5_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end + end + ap_ST_fsm_pp0_stage6 : begin + if ((1'b0 == ap_block_pp0_stage6_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state18; + end + ap_ST_fsm_state18 : begin + if (((tmp_fu_642_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + ap_NS_fsm = ap_ST_fsm_state18; + end else begin + ap_NS_fsm = ap_ST_fsm_state19; + end + end + ap_ST_fsm_state19 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln57_2_fu_671_p1; + +assign accum_out_address1 = zext_ln57_fu_650_p1; + +assign accum_out_d0 = ((icmp_ln69_12_fu_760_p2[0:0] == 1'b1) ? psum_13_014_reg_335 : select_ln69_11_fu_752_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln69_phi_fu_481_p16; + +assign add_ln49_fu_636_p2 = (x_reg_263 + 8'd16); + +assign add_ln57_fu_659_p2 = (q_reg_467 + 5'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd8]; + +assign ap_CS_fsm_state18 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state19 = ap_CS_fsm[32'd10]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage4_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage5_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage6_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_728 = (~(trunc_ln57_fu_655_p1 == 4'd0) & ~(trunc_ln57_fu_655_p1 == 4'd12) & ~(trunc_ln57_fu_655_p1 == 4'd10) & ~(trunc_ln57_fu_655_p1 == 4'd8) & ~(trunc_ln57_fu_655_p1 == 4'd6) & ~(trunc_ln57_fu_655_p1 == 4'd4) & ~(trunc_ln57_fu_655_p1 == 4'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_10_011_phi_fu_375_p4 = grp_fu_513_p2; + +assign ap_phi_mux_psum_11_012_phi_fu_363_p4 = grp_fu_518_p2; + +assign ap_phi_mux_psum_12_013_phi_fu_351_p4 = grp_fu_508_p2; + +assign ap_phi_mux_psum_13_014_phi_fu_339_p4 = grp_fu_513_p2; + +assign ap_phi_mux_psum_14_015_phi_fu_327_p4 = grp_fu_518_p2; + +assign ap_phi_mux_psum_15_016_phi_fu_315_p4 = grp_fu_508_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_459_p4 = grp_fu_508_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_447_p4 = grp_fu_513_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_435_p4 = grp_fu_518_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_423_p4 = grp_fu_508_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_411_p4 = grp_fu_513_p2; + +assign ap_phi_mux_psum_8_09_phi_fu_399_p4 = grp_fu_518_p2; + +assign ap_phi_mux_psum_9_010_phi_fu_387_p4 = grp_fu_508_p2; + +assign icmp_ln49_fu_536_p2 = ((ap_phi_mux_x_phi_fu_267_p4 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln69_10_fu_732_p2 = ((or_ln57_fu_665_p2 == 4'd9) ? 1'b1 : 1'b0); + +assign icmp_ln69_11_fu_746_p2 = ((or_ln57_fu_665_p2 == 4'd11) ? 1'b1 : 1'b0); + +assign icmp_ln69_12_fu_760_p2 = ((or_ln57_fu_665_p2 == 4'd13) ? 1'b1 : 1'b0); + +assign icmp_ln69_7_fu_690_p2 = ((or_ln57_fu_665_p2 == 4'd3) ? 1'b1 : 1'b0); + +assign icmp_ln69_8_fu_704_p2 = ((or_ln57_fu_665_p2 == 4'd5) ? 1'b1 : 1'b0); + +assign icmp_ln69_9_fu_718_p2 = ((or_ln57_fu_665_p2 == 4'd7) ? 1'b1 : 1'b0); + +assign icmp_ln69_fu_676_p2 = ((or_ln57_fu_665_p2 == 4'd1) ? 1'b1 : 1'b0); + +assign lshr_ln_fu_542_p4 = {{ap_phi_mux_x_phi_fu_267_p4[7:1]}}; + +assign or_ln53_10_fu_603_p2 = (lshr_ln_reg_779 | 7'd5); + +assign or_ln53_11_fu_614_p2 = (lshr_ln_reg_779 | 7'd6); + +assign or_ln53_12_fu_625_p2 = (lshr_ln_reg_779 | 7'd7); + +assign or_ln53_7_fu_570_p2 = (lshr_ln_reg_779 | 7'd2); + +assign or_ln53_8_fu_581_p2 = (lshr_ln_reg_779 | 7'd3); + +assign or_ln53_9_fu_592_p2 = (lshr_ln_reg_779 | 7'd4); + +assign or_ln53_fu_558_p2 = (lshr_ln_fu_542_p4 | 7'd1); + +assign or_ln57_fu_665_p2 = (trunc_ln57_fu_655_p1 | 4'd1); + +assign select_ln69_10_fu_738_p3 = ((icmp_ln69_10_fu_732_p2[0:0] == 1'b1) ? psum_9_010_reg_383 : select_ln69_9_fu_724_p3); + +assign select_ln69_11_fu_752_p3 = ((icmp_ln69_11_fu_746_p2[0:0] == 1'b1) ? psum_11_012_reg_359 : select_ln69_10_fu_738_p3); + +assign select_ln69_7_fu_696_p3 = ((icmp_ln69_7_fu_690_p2[0:0] == 1'b1) ? psum_3_04_reg_455 : select_ln69_fu_682_p3); + +assign select_ln69_8_fu_710_p3 = ((icmp_ln69_8_fu_704_p2[0:0] == 1'b1) ? psum_5_06_reg_431 : select_ln69_7_fu_696_p3); + +assign select_ln69_9_fu_724_p3 = ((icmp_ln69_9_fu_718_p2[0:0] == 1'b1) ? psum_7_08_reg_407 : select_ln69_8_fu_710_p3); + +assign select_ln69_fu_682_p3 = ((icmp_ln69_fu_676_p2[0:0] == 1'b1) ? psum_1_02_reg_287 : psum_15_016_reg_311); + +assign tmp_fu_642_p3 = q_reg_467[32'd4]; + +assign trunc_ln57_fu_655_p1 = q_reg_467[3:0]; + +assign zext_ln53_10_fu_586_p1 = or_ln53_8_fu_581_p2; + +assign zext_ln53_11_fu_597_p1 = or_ln53_9_fu_592_p2; + +assign zext_ln53_12_fu_608_p1 = or_ln53_10_fu_603_p2; + +assign zext_ln53_13_fu_619_p1 = or_ln53_11_fu_614_p2; + +assign zext_ln53_14_fu_630_p1 = or_ln53_12_fu_625_p2; + +assign zext_ln53_8_fu_564_p1 = or_ln53_fu_558_p2; + +assign zext_ln53_9_fu_575_p1 = or_ln53_7_fu_570_p2; + +assign zext_ln53_fu_552_p1 = lshr_ln_fu_542_p4; + +assign zext_ln57_2_fu_671_p1 = or_ln57_fu_665_p2; + +assign zext_ln57_fu_650_p1 = q_reg_467; + +endmodule //td_fused_top_tdf5_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state13 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [3:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [3:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_ce0; +reg accum_in_ce1; +reg accum_out_ce0; +reg accum_out_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [3:0] out_idx_reg_66; +reg [3:0] out_idx_reg_66_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_pp0_stage0_11001; +reg [3:0] out_idx_reg_66_pp0_iter2_reg; +reg [3:0] out_idx_reg_66_pp0_iter3_reg; +reg [3:0] out_idx_reg_66_pp0_iter4_reg; +reg [3:0] out_idx_reg_66_pp0_iter5_reg; +reg [3:0] out_idx_reg_66_pp0_iter6_reg; +reg [3:0] out_idx_reg_66_pp0_iter7_reg; +reg [3:0] out_idx_reg_66_pp0_iter8_reg; +reg [3:0] out_idx_reg_66_pp0_iter9_reg; +wire [3:0] add_ln98_fu_82_p2; +reg [3:0] add_ln98_reg_121; +reg ap_enable_reg_pp0_iter0; +wire [0:0] icmp_ln84_fu_88_p2; +reg [0:0] icmp_ln84_reg_126; +reg [0:0] icmp_ln84_reg_126_pp0_iter1_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter2_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter3_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter4_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter5_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter6_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter7_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter8_reg; +reg [0:0] icmp_ln84_reg_126_pp0_iter9_reg; +reg [15:0] accum_in_load_reg_140; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_load_1_reg_145; +wire [15:0] grp_fu_78_p2; +reg [15:0] sum0_reg_150; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg [3:0] ap_phi_mux_out_idx_phi_fu_70_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln94_fu_100_p1; +wire [63:0] zext_ln94_1_fu_111_p1; +wire [63:0] zext_ln84_fu_116_p1; +wire [3:0] i_12_fu_94_p2; +wire [3:0] or_ln94_fu_105_p2; +wire ap_CS_fsm_state13; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U784( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(accum_in_load_1_reg_145), + .din1(accum_in_load_reg_140), + .dout(grp_fu_78_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_66 <= 4'd0; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln84_reg_126 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + out_idx_reg_66 <= add_ln98_reg_121; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln84_reg_126 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_load_1_reg_145 <= accum_in_q0; + accum_in_load_reg_140 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln98_reg_121 <= add_ln98_fu_82_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln84_reg_126 <= icmp_ln84_fu_88_p2; + icmp_ln84_reg_126_pp0_iter1_reg <= icmp_ln84_reg_126; + out_idx_reg_66_pp0_iter1_reg <= out_idx_reg_66; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln84_reg_126_pp0_iter2_reg <= icmp_ln84_reg_126_pp0_iter1_reg; + icmp_ln84_reg_126_pp0_iter3_reg <= icmp_ln84_reg_126_pp0_iter2_reg; + icmp_ln84_reg_126_pp0_iter4_reg <= icmp_ln84_reg_126_pp0_iter3_reg; + icmp_ln84_reg_126_pp0_iter5_reg <= icmp_ln84_reg_126_pp0_iter4_reg; + icmp_ln84_reg_126_pp0_iter6_reg <= icmp_ln84_reg_126_pp0_iter5_reg; + icmp_ln84_reg_126_pp0_iter7_reg <= icmp_ln84_reg_126_pp0_iter6_reg; + icmp_ln84_reg_126_pp0_iter8_reg <= icmp_ln84_reg_126_pp0_iter7_reg; + icmp_ln84_reg_126_pp0_iter9_reg <= icmp_ln84_reg_126_pp0_iter8_reg; + out_idx_reg_66_pp0_iter2_reg <= out_idx_reg_66_pp0_iter1_reg; + out_idx_reg_66_pp0_iter3_reg <= out_idx_reg_66_pp0_iter2_reg; + out_idx_reg_66_pp0_iter4_reg <= out_idx_reg_66_pp0_iter3_reg; + out_idx_reg_66_pp0_iter5_reg <= out_idx_reg_66_pp0_iter4_reg; + out_idx_reg_66_pp0_iter6_reg <= out_idx_reg_66_pp0_iter5_reg; + out_idx_reg_66_pp0_iter7_reg <= out_idx_reg_66_pp0_iter6_reg; + out_idx_reg_66_pp0_iter8_reg <= out_idx_reg_66_pp0_iter7_reg; + out_idx_reg_66_pp0_iter9_reg <= out_idx_reg_66_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln84_reg_126_pp0_iter8_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sum0_reg_150 <= grp_fu_78_p2; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln84_reg_126_pp0_iter9_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter10 == 1'b1))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln84_fu_88_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln84_reg_126 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_out_idx_phi_fu_70_p4 = add_ln98_reg_121; + end else begin + ap_phi_mux_out_idx_phi_fu_70_p4 = out_idx_reg_66; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln84_fu_88_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_enable_reg_pp0_iter9 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln84_fu_88_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_enable_reg_pp0_iter9 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln94_1_fu_111_p1; + +assign accum_in_address1 = zext_ln94_fu_100_p1; + +assign accum_out_address0 = zext_ln84_fu_116_p1; + +assign accum_out_d0 = sum0_reg_150; + +assign add_ln98_fu_82_p2 = (ap_phi_mux_out_idx_phi_fu_70_p4 + 4'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign i_12_fu_94_p2 = ap_phi_mux_out_idx_phi_fu_70_p4 << 4'd1; + +assign icmp_ln84_fu_88_p2 = ((ap_phi_mux_out_idx_phi_fu_70_p4 == 4'd8) ? 1'b1 : 1'b0); + +assign or_ln94_fu_105_p2 = (i_12_fu_94_p2 | 4'd1); + +assign zext_ln84_fu_116_p1 = out_idx_reg_66_pp0_iter9_reg; + +assign zext_ln94_1_fu_111_p1 = or_ln94_fu_105_p2; + +assign zext_ln94_fu_100_p1 = i_12_fu_94_p2; + +endmodule //td_fused_top_tdf5_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_accum_3_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_26, + accum_in_26_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_26; +output accum_in_26_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_26; +reg accum_in_26_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln111_fu_73_p2; +reg [3:0] add_ln111_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln111_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln111_fu_79_p1; +reg [15:0] accum_in_26_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_26_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U791( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_26_preg <= 16'd0; + end else begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_26_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln111_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln111_reg_90 <= add_ln111_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_26 = sum_01_reg_55; + end else begin + accum_in_26 = accum_in_26_preg; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_26_ap_vld = 1'b1; + end else begin + accum_in_26_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln111_fu_79_p1; + +assign add_ln111_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln111_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln111_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf5_accum_3_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_accum_3_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_24, + accum_in_24_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_24; +output accum_in_24_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_24; +reg accum_in_24_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln111_fu_73_p2; +reg [3:0] add_ln111_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln111_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln111_fu_79_p1; +reg [15:0] accum_in_24_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_24_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U795( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_24_preg <= 16'd0; + end else begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_24_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln111_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln111_reg_90 <= add_ln111_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_24 = sum_01_reg_55; + end else begin + accum_in_24 = accum_in_24_preg; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_24_ap_vld = 1'b1; + end else begin + accum_in_24_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln111_fu_79_p1; + +assign add_ln111_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln111_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln111_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf5_accum_3_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_accum_3_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_22, + accum_in_22_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_22; +output accum_in_22_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_22; +reg accum_in_22_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln111_fu_73_p2; +reg [3:0] add_ln111_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln111_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln111_fu_79_p1; +reg [15:0] accum_in_22_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_22_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U799( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_22_preg <= 16'd0; + end else begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_22_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln111_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln111_reg_90 <= add_ln111_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_22 = sum_01_reg_55; + end else begin + accum_in_22 = accum_in_22_preg; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_22_ap_vld = 1'b1; + end else begin + accum_in_22_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln111_fu_79_p1; + +assign add_ln111_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln111_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln111_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf5_accum_3_3 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_accum_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_28, + accum_in_28_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_28; +output accum_in_28_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_28; +reg accum_in_28_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln111_fu_73_p2; +reg [3:0] add_ln111_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln111_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln111_fu_79_p1; +reg [15:0] accum_in_28_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_28_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U787( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_28_preg <= 16'd0; + end else begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_28_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln111_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln111_reg_90 <= add_ln111_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_28 = sum_01_reg_55; + end else begin + accum_in_28 = accum_in_28_preg; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_28_ap_vld = 1'b1; + end else begin + accum_in_28_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln111_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln111_fu_79_p1; + +assign add_ln111_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln111_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln111_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf5_accum_3 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_0_read, + sums_1_read, + sums_2_read, + sums_3_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + input_indices_23_out_din, + input_indices_23_out_full_n, + input_indices_23_out_write, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state25 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_0_read; +input [15:0] sums_1_read; +input [15:0] sums_2_read; +input [15:0] sums_3_read; +output [6:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [6:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [6:0] input_indices_23_out_din; +input input_indices_23_out_full_n; +output input_indices_23_out_write; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg input_indices_23_read; +reg input_indices_23_out_write; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +reg input_indices_23_out_blk_n; +reg [0:0] write_flag6_0_reg_153; +reg [0:0] write_flag9_0_reg_164; +reg [0:0] write_flag12_0_reg_175; +reg [0:0] write_flag_0_reg_186; +reg [2:0] o_reg_197; +reg [15:0] outputs_1_011_reg_208; +reg [15:0] outputs_0_010_reg_220; +reg [15:0] outputs_2_09_reg_232; +reg [15:0] outputs_3_08_reg_244; +wire [4:0] trunc_ln235_fu_268_p1; +reg [4:0] trunc_ln235_reg_550; +wire [2:0] add_ln213_fu_272_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_state13_pp0_stage0_iter11; +wire ap_block_state14_pp0_stage0_iter12; +wire ap_block_state15_pp0_stage0_iter13; +wire ap_block_state16_pp0_stage0_iter14; +wire ap_block_state17_pp0_stage0_iter15; +wire ap_block_state18_pp0_stage0_iter16; +wire ap_block_state19_pp0_stage0_iter17; +wire ap_block_state20_pp0_stage0_iter18; +wire ap_block_state21_pp0_stage0_iter19; +wire ap_block_state22_pp0_stage0_iter20; +wire ap_block_state23_pp0_stage0_iter21; +wire ap_block_state24_pp0_stage0_iter22; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln213_fu_278_p2; +reg [0:0] icmp_ln213_reg_560; +reg [0:0] icmp_ln213_reg_560_pp0_iter1_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter2_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter3_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter4_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter5_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter6_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter7_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter8_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter9_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter10_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter11_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter12_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter13_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter14_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter15_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter16_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter17_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter18_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter19_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter20_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter21_reg; +wire [1:0] trunc_ln219_fu_284_p1; +reg [1:0] trunc_ln219_reg_564; +reg [1:0] trunc_ln219_reg_564_pp0_iter1_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter2_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter3_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter4_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter5_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter6_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter7_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter8_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter9_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter10_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter11_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter12_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter13_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter14_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter15_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter16_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter17_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter18_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter19_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter20_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter21_reg; +wire [0:0] write_flag_1_fu_300_p6; +wire [0:0] write_flag12_1_fu_314_p6; +wire [0:0] write_flag9_1_fu_328_p6; +wire [0:0] write_flag6_1_fu_342_p6; +wire [15:0] trunc_ln220_fu_356_p1; +reg [15:0] trunc_ln220_reg_597; +reg [15:0] tmp_138_i_i_reg_602; +reg [15:0] tmp_138_i_i_reg_602_pp0_iter2_reg; +reg [15:0] tmp_138_i_i_reg_602_pp0_iter3_reg; +reg [15:0] tmp_138_i_i_reg_602_pp0_iter4_reg; +reg [15:0] tmp_138_i_i_reg_602_pp0_iter5_reg; +reg [15:0] tmp_138_i_i_reg_602_pp0_iter6_reg; +reg [15:0] tmp_138_i_i_reg_602_pp0_iter7_reg; +reg [15:0] tmp_138_i_i_reg_602_pp0_iter8_reg; +reg [15:0] tmp_139_i_i_reg_607; +reg [15:0] tmp_139_i_i_reg_607_pp0_iter2_reg; +reg [15:0] tmp_139_i_i_reg_607_pp0_iter3_reg; +reg [15:0] tmp_139_i_i_reg_607_pp0_iter4_reg; +reg [15:0] tmp_139_i_i_reg_607_pp0_iter5_reg; +reg [15:0] tmp_139_i_i_reg_607_pp0_iter6_reg; +reg [15:0] tmp_139_i_i_reg_607_pp0_iter7_reg; +reg [15:0] tmp_139_i_i_reg_607_pp0_iter8_reg; +reg [15:0] tmp_139_i_i_reg_607_pp0_iter9_reg; +reg [15:0] tmp_139_i_i_reg_607_pp0_iter10_reg; +reg [15:0] tmp_139_i_i_reg_607_pp0_iter11_reg; +reg [15:0] tmp_139_i_i_reg_607_pp0_iter12_reg; +reg [15:0] tmp_139_i_i_reg_607_pp0_iter13_reg; +wire [15:0] val_in_assign_fu_380_p6; +reg [15:0] val_in_assign_reg_612; +wire [15:0] grp_fu_260_p2; +reg [15:0] sub_i_i_i_reg_622; +wire [15:0] grp_fu_264_p2; +reg [15:0] normalized_reg_632; +wire [15:0] grp_fu_256_p2; +reg [15:0] biased_reg_642; +wire [15:0] outputs_3_1_fu_450_p3; +reg ap_enable_reg_pp0_iter22; +wire [15:0] outputs_2_1_fu_458_p3; +wire [15:0] outputs_0_1_fu_482_p3; +wire [15:0] outputs_1_1_fu_498_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_condition_pp0_exit_iter21_state23; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln220_fu_295_p1; +wire [15:0] grp_fu_256_p1; +wire [15:0] grp_fu_260_p1; +wire [15:0] grp_fu_264_p1; +wire [6:0] ochan_fu_288_p3; +wire [15:0] data_V_fu_401_p1; +wire [0:0] p_Result_s_fu_404_p3; +wire [0:0] icmp_ln223_fu_419_p2; +wire [15:0] activated_fu_412_p3; +wire [0:0] icmp_ln223_5_fu_432_p2; +wire [15:0] select_ln223_fu_424_p3; +wire [0:0] icmp_ln223_6_fu_445_p2; +wire [15:0] select_ln223_9_fu_437_p3; +wire [15:0] select_ln223_10_fu_466_p3; +wire [15:0] select_ln223_11_fu_474_p3; +wire [15:0] select_ln223_12_fu_490_p3; +wire ap_CS_fsm_state25; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U803( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(normalized_reg_632), + .din1(grp_fu_256_p1), + .dout(grp_fu_256_p2) +); + +td_fused_top_hsub_16ns_16ns_16_7_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 7 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_7_full_dsp_1_U804( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(val_in_assign_reg_612), + .din1(grp_fu_260_p1), + .dout(grp_fu_260_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U805( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_622), + .din1(grp_fu_264_p1), + .dout(grp_fu_264_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U806( + .din0(1'd1), + .din1(write_flag_0_reg_186), + .din2(write_flag_0_reg_186), + .din3(write_flag_0_reg_186), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag_1_fu_300_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U807( + .din0(write_flag12_0_reg_175), + .din1(write_flag12_0_reg_175), + .din2(write_flag12_0_reg_175), + .din3(1'd1), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag12_1_fu_314_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U808( + .din0(write_flag9_0_reg_164), + .din1(write_flag9_0_reg_164), + .din2(1'd1), + .din3(write_flag9_0_reg_164), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag9_1_fu_328_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U809( + .din0(write_flag6_0_reg_153), + .din1(1'd1), + .din2(write_flag6_0_reg_153), + .din3(write_flag6_0_reg_153), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag6_1_fu_342_p6) +); + +td_fused_top_mux_42_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 16 )) +mux_42_16_1_1_U810( + .din0(sums_0_read), + .din1(sums_1_read), + .din2(sums_2_read), + .din3(sums_3_read), + .din4(trunc_ln219_reg_564), + .dout(val_in_assign_fu_380_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end else if ((((ap_enable_reg_pp0_iter20 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter21_state23) & (1'b0 == ap_block_pp0_stage0_subdone)) | (~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter21_state23) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter20; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + o_reg_197 <= add_ln213_fu_272_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + o_reg_197 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag12_0_reg_175 <= write_flag12_1_fu_314_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag12_0_reg_175 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag6_0_reg_153 <= write_flag6_1_fu_342_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_153 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag9_0_reg_164 <= write_flag9_1_fu_328_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_164 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag_0_reg_186 <= write_flag_1_fu_300_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_186 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_560_pp0_iter20_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + biased_reg_642 <= grp_fu_256_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln213_reg_560 <= icmp_ln213_fu_278_p2; + icmp_ln213_reg_560_pp0_iter1_reg <= icmp_ln213_reg_560; + trunc_ln219_reg_564_pp0_iter1_reg <= trunc_ln219_reg_564; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln213_reg_560_pp0_iter10_reg <= icmp_ln213_reg_560_pp0_iter9_reg; + icmp_ln213_reg_560_pp0_iter11_reg <= icmp_ln213_reg_560_pp0_iter10_reg; + icmp_ln213_reg_560_pp0_iter12_reg <= icmp_ln213_reg_560_pp0_iter11_reg; + icmp_ln213_reg_560_pp0_iter13_reg <= icmp_ln213_reg_560_pp0_iter12_reg; + icmp_ln213_reg_560_pp0_iter14_reg <= icmp_ln213_reg_560_pp0_iter13_reg; + icmp_ln213_reg_560_pp0_iter15_reg <= icmp_ln213_reg_560_pp0_iter14_reg; + icmp_ln213_reg_560_pp0_iter16_reg <= icmp_ln213_reg_560_pp0_iter15_reg; + icmp_ln213_reg_560_pp0_iter17_reg <= icmp_ln213_reg_560_pp0_iter16_reg; + icmp_ln213_reg_560_pp0_iter18_reg <= icmp_ln213_reg_560_pp0_iter17_reg; + icmp_ln213_reg_560_pp0_iter19_reg <= icmp_ln213_reg_560_pp0_iter18_reg; + icmp_ln213_reg_560_pp0_iter20_reg <= icmp_ln213_reg_560_pp0_iter19_reg; + icmp_ln213_reg_560_pp0_iter21_reg <= icmp_ln213_reg_560_pp0_iter20_reg; + icmp_ln213_reg_560_pp0_iter2_reg <= icmp_ln213_reg_560_pp0_iter1_reg; + icmp_ln213_reg_560_pp0_iter3_reg <= icmp_ln213_reg_560_pp0_iter2_reg; + icmp_ln213_reg_560_pp0_iter4_reg <= icmp_ln213_reg_560_pp0_iter3_reg; + icmp_ln213_reg_560_pp0_iter5_reg <= icmp_ln213_reg_560_pp0_iter4_reg; + icmp_ln213_reg_560_pp0_iter6_reg <= icmp_ln213_reg_560_pp0_iter5_reg; + icmp_ln213_reg_560_pp0_iter7_reg <= icmp_ln213_reg_560_pp0_iter6_reg; + icmp_ln213_reg_560_pp0_iter8_reg <= icmp_ln213_reg_560_pp0_iter7_reg; + icmp_ln213_reg_560_pp0_iter9_reg <= icmp_ln213_reg_560_pp0_iter8_reg; + tmp_138_i_i_reg_602_pp0_iter2_reg <= tmp_138_i_i_reg_602; + tmp_138_i_i_reg_602_pp0_iter3_reg <= tmp_138_i_i_reg_602_pp0_iter2_reg; + tmp_138_i_i_reg_602_pp0_iter4_reg <= tmp_138_i_i_reg_602_pp0_iter3_reg; + tmp_138_i_i_reg_602_pp0_iter5_reg <= tmp_138_i_i_reg_602_pp0_iter4_reg; + tmp_138_i_i_reg_602_pp0_iter6_reg <= tmp_138_i_i_reg_602_pp0_iter5_reg; + tmp_138_i_i_reg_602_pp0_iter7_reg <= tmp_138_i_i_reg_602_pp0_iter6_reg; + tmp_138_i_i_reg_602_pp0_iter8_reg <= tmp_138_i_i_reg_602_pp0_iter7_reg; + tmp_139_i_i_reg_607_pp0_iter10_reg <= tmp_139_i_i_reg_607_pp0_iter9_reg; + tmp_139_i_i_reg_607_pp0_iter11_reg <= tmp_139_i_i_reg_607_pp0_iter10_reg; + tmp_139_i_i_reg_607_pp0_iter12_reg <= tmp_139_i_i_reg_607_pp0_iter11_reg; + tmp_139_i_i_reg_607_pp0_iter13_reg <= tmp_139_i_i_reg_607_pp0_iter12_reg; + tmp_139_i_i_reg_607_pp0_iter2_reg <= tmp_139_i_i_reg_607; + tmp_139_i_i_reg_607_pp0_iter3_reg <= tmp_139_i_i_reg_607_pp0_iter2_reg; + tmp_139_i_i_reg_607_pp0_iter4_reg <= tmp_139_i_i_reg_607_pp0_iter3_reg; + tmp_139_i_i_reg_607_pp0_iter5_reg <= tmp_139_i_i_reg_607_pp0_iter4_reg; + tmp_139_i_i_reg_607_pp0_iter6_reg <= tmp_139_i_i_reg_607_pp0_iter5_reg; + tmp_139_i_i_reg_607_pp0_iter7_reg <= tmp_139_i_i_reg_607_pp0_iter6_reg; + tmp_139_i_i_reg_607_pp0_iter8_reg <= tmp_139_i_i_reg_607_pp0_iter7_reg; + tmp_139_i_i_reg_607_pp0_iter9_reg <= tmp_139_i_i_reg_607_pp0_iter8_reg; + trunc_ln219_reg_564_pp0_iter10_reg <= trunc_ln219_reg_564_pp0_iter9_reg; + trunc_ln219_reg_564_pp0_iter11_reg <= trunc_ln219_reg_564_pp0_iter10_reg; + trunc_ln219_reg_564_pp0_iter12_reg <= trunc_ln219_reg_564_pp0_iter11_reg; + trunc_ln219_reg_564_pp0_iter13_reg <= trunc_ln219_reg_564_pp0_iter12_reg; + trunc_ln219_reg_564_pp0_iter14_reg <= trunc_ln219_reg_564_pp0_iter13_reg; + trunc_ln219_reg_564_pp0_iter15_reg <= trunc_ln219_reg_564_pp0_iter14_reg; + trunc_ln219_reg_564_pp0_iter16_reg <= trunc_ln219_reg_564_pp0_iter15_reg; + trunc_ln219_reg_564_pp0_iter17_reg <= trunc_ln219_reg_564_pp0_iter16_reg; + trunc_ln219_reg_564_pp0_iter18_reg <= trunc_ln219_reg_564_pp0_iter17_reg; + trunc_ln219_reg_564_pp0_iter19_reg <= trunc_ln219_reg_564_pp0_iter18_reg; + trunc_ln219_reg_564_pp0_iter20_reg <= trunc_ln219_reg_564_pp0_iter19_reg; + trunc_ln219_reg_564_pp0_iter21_reg <= trunc_ln219_reg_564_pp0_iter20_reg; + trunc_ln219_reg_564_pp0_iter2_reg <= trunc_ln219_reg_564_pp0_iter1_reg; + trunc_ln219_reg_564_pp0_iter3_reg <= trunc_ln219_reg_564_pp0_iter2_reg; + trunc_ln219_reg_564_pp0_iter4_reg <= trunc_ln219_reg_564_pp0_iter3_reg; + trunc_ln219_reg_564_pp0_iter5_reg <= trunc_ln219_reg_564_pp0_iter4_reg; + trunc_ln219_reg_564_pp0_iter6_reg <= trunc_ln219_reg_564_pp0_iter5_reg; + trunc_ln219_reg_564_pp0_iter7_reg <= trunc_ln219_reg_564_pp0_iter6_reg; + trunc_ln219_reg_564_pp0_iter8_reg <= trunc_ln219_reg_564_pp0_iter7_reg; + trunc_ln219_reg_564_pp0_iter9_reg <= trunc_ln219_reg_564_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_560_pp0_iter12_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + normalized_reg_632 <= grp_fu_264_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter22 == 1'b1) & (icmp_ln213_reg_560_pp0_iter21_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + outputs_0_010_reg_220 <= outputs_0_1_fu_482_p3; + outputs_1_011_reg_208 <= outputs_1_1_fu_498_p3; + outputs_2_09_reg_232 <= outputs_2_1_fu_458_p3; + outputs_3_08_reg_244 <= outputs_3_1_fu_450_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_560_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sub_i_i_i_reg_622 <= grp_fu_260_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_reg_560 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + tmp_138_i_i_reg_602 <= {{adjustments_q0[31:16]}}; + tmp_139_i_i_reg_607 <= {{adjustments_q0[47:32]}}; + trunc_ln220_reg_597 <= trunc_ln220_fu_356_p1; + val_in_assign_reg_612 <= val_in_assign_fu_380_p6; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + trunc_ln219_reg_564 <= trunc_ln219_fu_284_p1; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + trunc_ln235_reg_550 <= trunc_ln235_fu_268_p1; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0))) begin + ap_condition_pp0_exit_iter21_state23 = 1'b1; + end else begin + ap_condition_pp0_exit_iter21_state23 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_out_blk_n = input_indices_23_out_full_n; + end else begin + input_indices_23_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_out_write = 1'b1; + end else begin + input_indices_23_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state25; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state25 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign activated_fu_412_p3 = ((p_Result_s_fu_404_p3[0:0] == 1'b1) ? 16'd0 : biased_reg_642); + +assign add_ln213_fu_272_p2 = (o_reg_197 + 3'd1); + +assign adjustments_address0 = zext_ln220_fu_295_p1; + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state25 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = outputs_0_010_reg_220; + +assign ap_return_1 = outputs_1_011_reg_208; + +assign ap_return_2 = outputs_2_09_reg_232; + +assign ap_return_3 = outputs_3_08_reg_244; + +assign data_V_fu_401_p1 = biased_reg_642; + +assign grp_fu_256_p1 = tmp_139_i_i_reg_607_pp0_iter13_reg; + +assign grp_fu_260_p1 = trunc_ln220_reg_597; + +assign grp_fu_264_p1 = tmp_138_i_i_reg_602_pp0_iter8_reg; + +assign icmp_ln213_fu_278_p2 = ((o_reg_197 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln223_5_fu_432_p2 = ((trunc_ln219_reg_564_pp0_iter21_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln223_6_fu_445_p2 = ((trunc_ln219_reg_564_pp0_iter21_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln223_fu_419_p2 = ((trunc_ln219_reg_564_pp0_iter21_reg == 2'd0) ? 1'b1 : 1'b0); + +assign input_indices_23_out_din = input_indices_23_dout; + +assign ochan_fu_288_p3 = {{trunc_ln235_reg_550}, {trunc_ln219_fu_284_p1}}; + +assign outputs_0_1_fu_482_p3 = ((icmp_ln223_6_fu_445_p2[0:0] == 1'b1) ? outputs_0_010_reg_220 : select_ln223_11_fu_474_p3); + +assign outputs_1_1_fu_498_p3 = ((icmp_ln223_6_fu_445_p2[0:0] == 1'b1) ? outputs_1_011_reg_208 : select_ln223_12_fu_490_p3); + +assign outputs_2_1_fu_458_p3 = ((icmp_ln223_6_fu_445_p2[0:0] == 1'b1) ? activated_fu_412_p3 : outputs_2_09_reg_232); + +assign outputs_3_1_fu_450_p3 = ((icmp_ln223_6_fu_445_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : select_ln223_9_fu_437_p3); + +assign p_Result_s_fu_404_p3 = data_V_fu_401_p1[32'd15]; + +assign select_ln223_10_fu_466_p3 = ((icmp_ln223_fu_419_p2[0:0] == 1'b1) ? activated_fu_412_p3 : outputs_0_010_reg_220); + +assign select_ln223_11_fu_474_p3 = ((icmp_ln223_5_fu_432_p2[0:0] == 1'b1) ? outputs_0_010_reg_220 : select_ln223_10_fu_466_p3); + +assign select_ln223_12_fu_490_p3 = ((icmp_ln223_5_fu_432_p2[0:0] == 1'b1) ? activated_fu_412_p3 : outputs_1_011_reg_208); + +assign select_ln223_9_fu_437_p3 = ((icmp_ln223_5_fu_432_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : select_ln223_fu_424_p3); + +assign select_ln223_fu_424_p3 = ((icmp_ln223_fu_419_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : activated_fu_412_p3); + +assign trunc_ln219_fu_284_p1 = o_reg_197[1:0]; + +assign trunc_ln220_fu_356_p1 = adjustments_q0[15:0]; + +assign trunc_ln235_fu_268_p1 = input_indices_23_dout[4:0]; + +assign zext_ln220_fu_295_p1 = ochan_fu_288_p3; + +endmodule //td_fused_top_tdf5_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_0_address0, + ifmap_vec_0_ce0, + ifmap_vec_0_q0, + ifmap_vec_1_address0, + ifmap_vec_1_ce0, + ifmap_vec_1_q0, + weight_vecs_0_0_address0, + weight_vecs_0_0_ce0, + weight_vecs_0_0_q0, + weight_vecs_0_1_address0, + weight_vecs_0_1_ce0, + weight_vecs_0_1_q0, + weight_vecs_1_0_address0, + weight_vecs_1_0_ce0, + weight_vecs_1_0_q0, + weight_vecs_1_1_address0, + weight_vecs_1_1_ce0, + weight_vecs_1_1_q0, + weight_vecs_2_0_address0, + weight_vecs_2_0_ce0, + weight_vecs_2_0_q0, + weight_vecs_2_1_address0, + weight_vecs_2_1_ce0, + weight_vecs_2_1_q0, + weight_vecs_3_0_address0, + weight_vecs_3_0_ce0, + weight_vecs_3_0_q0, + weight_vecs_3_1_address0, + weight_vecs_3_1_ce0, + weight_vecs_3_1_q0, + products_0_0_address0, + products_0_0_ce0, + products_0_0_we0, + products_0_0_d0, + products_0_1_address0, + products_0_1_ce0, + products_0_1_we0, + products_0_1_d0, + products_1_0_address0, + products_1_0_ce0, + products_1_0_we0, + products_1_0_d0, + products_1_1_address0, + products_1_1_ce0, + products_1_1_we0, + products_1_1_d0, + products_2_0_address0, + products_2_0_ce0, + products_2_0_we0, + products_2_0_d0, + products_2_1_address0, + products_2_1_ce0, + products_2_1_we0, + products_2_1_d0, + products_3_0_address0, + products_3_0_ce0, + products_3_0_we0, + products_3_0_d0, + products_3_1_address0, + products_3_1_ce0, + products_3_1_we0, + products_3_1_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state11 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [6:0] ifmap_vec_0_address0; +output ifmap_vec_0_ce0; +input [15:0] ifmap_vec_0_q0; +output [6:0] ifmap_vec_1_address0; +output ifmap_vec_1_ce0; +input [15:0] ifmap_vec_1_q0; +output [6:0] weight_vecs_0_0_address0; +output weight_vecs_0_0_ce0; +input [15:0] weight_vecs_0_0_q0; +output [6:0] weight_vecs_0_1_address0; +output weight_vecs_0_1_ce0; +input [15:0] weight_vecs_0_1_q0; +output [6:0] weight_vecs_1_0_address0; +output weight_vecs_1_0_ce0; +input [15:0] weight_vecs_1_0_q0; +output [6:0] weight_vecs_1_1_address0; +output weight_vecs_1_1_ce0; +input [15:0] weight_vecs_1_1_q0; +output [6:0] weight_vecs_2_0_address0; +output weight_vecs_2_0_ce0; +input [15:0] weight_vecs_2_0_q0; +output [6:0] weight_vecs_2_1_address0; +output weight_vecs_2_1_ce0; +input [15:0] weight_vecs_2_1_q0; +output [6:0] weight_vecs_3_0_address0; +output weight_vecs_3_0_ce0; +input [15:0] weight_vecs_3_0_q0; +output [6:0] weight_vecs_3_1_address0; +output weight_vecs_3_1_ce0; +input [15:0] weight_vecs_3_1_q0; +output [6:0] products_0_0_address0; +output products_0_0_ce0; +output products_0_0_we0; +output [15:0] products_0_0_d0; +output [6:0] products_0_1_address0; +output products_0_1_ce0; +output products_0_1_we0; +output [15:0] products_0_1_d0; +output [6:0] products_1_0_address0; +output products_1_0_ce0; +output products_1_0_we0; +output [15:0] products_1_0_d0; +output [6:0] products_1_1_address0; +output products_1_1_ce0; +output products_1_1_we0; +output [15:0] products_1_1_d0; +output [6:0] products_2_0_address0; +output products_2_0_ce0; +output products_2_0_we0; +output [15:0] products_2_0_d0; +output [6:0] products_2_1_address0; +output products_2_1_ce0; +output products_2_1_we0; +output [15:0] products_2_1_d0; +output [6:0] products_3_0_address0; +output products_3_0_ce0; +output products_3_0_we0; +output [15:0] products_3_0_d0; +output [6:0] products_3_1_address0; +output products_3_1_ce0; +output products_3_1_we0; +output [15:0] products_3_1_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_0_ce0; +reg ifmap_vec_1_ce0; +reg weight_vecs_0_0_ce0; +reg weight_vecs_0_1_ce0; +reg weight_vecs_1_0_ce0; +reg weight_vecs_1_1_ce0; +reg weight_vecs_2_0_ce0; +reg weight_vecs_2_1_ce0; +reg weight_vecs_3_0_ce0; +reg weight_vecs_3_1_ce0; +reg products_0_0_ce0; +reg products_0_0_we0; +reg products_0_1_ce0; +reg products_0_1_we0; +reg products_1_0_ce0; +reg products_1_0_we0; +reg products_1_1_ce0; +reg products_1_1_we0; +reg products_2_0_ce0; +reg products_2_0_we0; +reg products_2_1_ce0; +reg products_2_1_we0; +reg products_3_0_ce0; +reg products_3_0_we0; +reg products_3_1_ce0; +reg products_3_1_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [6:0] indvar_flatten17_reg_334; +reg [1:0] ii_reg_345; +reg [5:0] indvar_flatten_reg_356; +reg [1:0] jj_reg_367; +reg [4:0] ic_reg_378; +wire [6:0] add_ln147_3_fu_421_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln147_fu_455_p2; +reg [0:0] icmp_ln147_reg_730; +reg [0:0] icmp_ln147_reg_730_pp0_iter1_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter2_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter3_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter4_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter5_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter6_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter7_reg; +wire [1:0] select_ln147_11_fu_489_p3; +reg [1:0] select_ln147_11_reg_734; +wire [1:0] select_ln148_7_fu_591_p3; +reg [1:0] select_ln148_7_reg_739; +wire [5:0] empty_103_fu_603_p2; +reg [5:0] empty_103_reg_744; +wire [3:0] select_ln148_8_fu_619_p3; +reg [3:0] select_ln148_8_reg_749; +reg [3:0] select_ln148_8_reg_749_pp0_iter1_reg; +reg [3:0] select_ln148_8_reg_749_pp0_iter2_reg; +reg [3:0] select_ln148_8_reg_749_pp0_iter3_reg; +reg [3:0] select_ln148_8_reg_749_pp0_iter4_reg; +reg [3:0] select_ln148_8_reg_749_pp0_iter5_reg; +reg [3:0] select_ln148_8_reg_749_pp0_iter6_reg; +reg [3:0] select_ln148_8_reg_749_pp0_iter7_reg; +reg [2:0] newIndex_reg_755; +reg [2:0] newIndex_reg_755_pp0_iter1_reg; +reg [2:0] newIndex_reg_755_pp0_iter2_reg; +reg [2:0] newIndex_reg_755_pp0_iter3_reg; +reg [2:0] newIndex_reg_755_pp0_iter4_reg; +reg [2:0] newIndex_reg_755_pp0_iter5_reg; +reg [2:0] newIndex_reg_755_pp0_iter6_reg; +reg [2:0] newIndex_reg_755_pp0_iter7_reg; +reg [2:0] tmp_s_reg_761; +reg [2:0] tmp_s_reg_761_pp0_iter1_reg; +reg [2:0] tmp_s_reg_761_pp0_iter2_reg; +reg [2:0] tmp_s_reg_761_pp0_iter3_reg; +reg [2:0] tmp_s_reg_761_pp0_iter4_reg; +reg [2:0] tmp_s_reg_761_pp0_iter5_reg; +reg [2:0] tmp_s_reg_761_pp0_iter6_reg; +reg [2:0] tmp_s_reg_761_pp0_iter7_reg; +wire [4:0] add_ln149_fu_657_p2; +wire [5:0] select_ln148_9_fu_669_p3; +reg [15:0] ifmap_vec_0_load_reg_826; +reg [15:0] weight_vecs_0_0_load_reg_834; +reg [15:0] weight_vecs_1_0_load_reg_839; +reg [15:0] weight_vecs_2_0_load_reg_844; +reg [15:0] weight_vecs_3_0_load_reg_849; +reg [15:0] ifmap_vec_1_load_reg_854; +reg [15:0] weight_vecs_0_1_load_reg_862; +reg [15:0] weight_vecs_1_1_load_reg_867; +reg [15:0] weight_vecs_2_1_load_reg_872; +reg [15:0] weight_vecs_3_1_load_reg_877; +wire [15:0] grp_fu_389_p2; +reg [15:0] mul_reg_882; +wire [15:0] grp_fu_393_p2; +reg [15:0] mul_1_reg_887; +wire [15:0] grp_fu_397_p2; +reg [15:0] mul_2_reg_892; +wire [15:0] grp_fu_401_p2; +reg [15:0] mul_3_reg_897; +wire [15:0] grp_fu_405_p2; +reg [15:0] mul27_1_reg_902; +wire [15:0] grp_fu_409_p2; +reg [15:0] mul27_1_1_reg_907; +wire [15:0] grp_fu_413_p2; +reg [15:0] mul27_1_2_reg_912; +wire [15:0] grp_fu_417_p2; +reg [15:0] mul27_1_3_reg_917; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg [1:0] ap_phi_mux_ii_phi_fu_349_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_371_p4; +wire [63:0] tmp_88_fu_683_p1; +wire [63:0] zext_ln153_fu_703_p1; +wire [63:0] zext_ln153_5_fu_717_p1; +wire [3:0] shl_ln_fu_431_p3; +wire [3:0] zext_ln150_fu_427_p1; +wire [3:0] sub_ln150_fu_439_p2; +wire [3:0] zext_ln150_3_fu_445_p1; +wire [0:0] icmp_ln148_fu_467_p2; +wire [1:0] add_ln147_fu_461_p2; +wire [3:0] tmp_fu_501_p3; +wire [4:0] tmp_cast_fu_509_p1; +wire [4:0] select_ln147_13_cast_fu_497_p1; +wire [4:0] empty_102_fu_513_p2; +wire [3:0] shl_ln150_mid1_fu_527_p3; +wire [3:0] zext_ln150_6_fu_523_p1; +wire [3:0] sub_ln150_3_fu_535_p2; +wire [3:0] add_ln150_fu_449_p2; +wire [0:0] tmp_43_fu_557_p3; +wire [0:0] xor_ln149_fu_565_p2; +wire [1:0] select_ln147_fu_473_p3; +wire [0:0] or_ln147_fu_571_p2; +wire [4:0] select_ln147_10_fu_481_p3; +wire [1:0] add_ln148_fu_577_p2; +wire [5:0] sext_ln150_fu_519_p1; +wire [5:0] select_ln148_9_cast_fu_599_p1; +wire [3:0] select_ln147_12_fu_541_p3; +wire [3:0] zext_ln150_7_fu_609_p1; +wire [3:0] select_ln147_13_fu_549_p3; +wire [3:0] add_ln150_3_fu_613_p2; +wire [4:0] select_ln148_fu_583_p3; +wire [3:0] trunc_ln149_fu_627_p1; +wire [3:0] or_ln150_fu_641_p2; +wire [5:0] add_ln148_3_fu_663_p2; +wire [8:0] tmp_44_fu_677_p3; +wire [6:0] lshr_ln_fu_697_p3; +wire [6:0] lshr_ln153_5_fu_711_p3; +wire ap_CS_fsm_state11; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U752( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_826), + .din1(weight_vecs_0_0_load_reg_834), + .dout(grp_fu_389_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U753( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_826), + .din1(weight_vecs_1_0_load_reg_839), + .dout(grp_fu_393_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U754( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_826), + .din1(weight_vecs_2_0_load_reg_844), + .dout(grp_fu_397_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U755( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_826), + .din1(weight_vecs_3_0_load_reg_849), + .dout(grp_fu_401_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U756( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_854), + .din1(weight_vecs_0_1_load_reg_862), + .dout(grp_fu_405_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U757( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_854), + .din1(weight_vecs_1_1_load_reg_867), + .dout(grp_fu_409_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U758( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_854), + .din1(weight_vecs_2_1_load_reg_872), + .dout(grp_fu_413_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U759( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_854), + .din1(weight_vecs_3_1_load_reg_877), + .dout(grp_fu_417_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_455_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ic_reg_378 <= add_ln149_fu_657_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_reg_378 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_730 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_345 <= select_ln147_11_reg_734; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_345 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_455_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten17_reg_334 <= add_ln147_3_fu_421_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten17_reg_334 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_455_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten_reg_356 <= select_ln148_9_fu_669_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_356 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_730 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_367 <= select_ln148_7_reg_739; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_367 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_455_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + empty_103_reg_744 <= empty_103_fu_603_p2; + newIndex_reg_755 <= {{select_ln148_fu_583_p3[3:1]}}; + select_ln148_8_reg_749 <= select_ln148_8_fu_619_p3; + tmp_s_reg_761 <= {{or_ln150_fu_641_p2[3:1]}}; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln147_reg_730 <= icmp_ln147_fu_455_p2; + icmp_ln147_reg_730_pp0_iter1_reg <= icmp_ln147_reg_730; + newIndex_reg_755_pp0_iter1_reg <= newIndex_reg_755; + select_ln148_8_reg_749_pp0_iter1_reg <= select_ln148_8_reg_749; + tmp_s_reg_761_pp0_iter1_reg <= tmp_s_reg_761; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln147_reg_730_pp0_iter2_reg <= icmp_ln147_reg_730_pp0_iter1_reg; + icmp_ln147_reg_730_pp0_iter3_reg <= icmp_ln147_reg_730_pp0_iter2_reg; + icmp_ln147_reg_730_pp0_iter4_reg <= icmp_ln147_reg_730_pp0_iter3_reg; + icmp_ln147_reg_730_pp0_iter5_reg <= icmp_ln147_reg_730_pp0_iter4_reg; + icmp_ln147_reg_730_pp0_iter6_reg <= icmp_ln147_reg_730_pp0_iter5_reg; + icmp_ln147_reg_730_pp0_iter7_reg <= icmp_ln147_reg_730_pp0_iter6_reg; + newIndex_reg_755_pp0_iter2_reg <= newIndex_reg_755_pp0_iter1_reg; + newIndex_reg_755_pp0_iter3_reg <= newIndex_reg_755_pp0_iter2_reg; + newIndex_reg_755_pp0_iter4_reg <= newIndex_reg_755_pp0_iter3_reg; + newIndex_reg_755_pp0_iter5_reg <= newIndex_reg_755_pp0_iter4_reg; + newIndex_reg_755_pp0_iter6_reg <= newIndex_reg_755_pp0_iter5_reg; + newIndex_reg_755_pp0_iter7_reg <= newIndex_reg_755_pp0_iter6_reg; + select_ln148_8_reg_749_pp0_iter2_reg <= select_ln148_8_reg_749_pp0_iter1_reg; + select_ln148_8_reg_749_pp0_iter3_reg <= select_ln148_8_reg_749_pp0_iter2_reg; + select_ln148_8_reg_749_pp0_iter4_reg <= select_ln148_8_reg_749_pp0_iter3_reg; + select_ln148_8_reg_749_pp0_iter5_reg <= select_ln148_8_reg_749_pp0_iter4_reg; + select_ln148_8_reg_749_pp0_iter6_reg <= select_ln148_8_reg_749_pp0_iter5_reg; + select_ln148_8_reg_749_pp0_iter7_reg <= select_ln148_8_reg_749_pp0_iter6_reg; + tmp_s_reg_761_pp0_iter2_reg <= tmp_s_reg_761_pp0_iter1_reg; + tmp_s_reg_761_pp0_iter3_reg <= tmp_s_reg_761_pp0_iter2_reg; + tmp_s_reg_761_pp0_iter4_reg <= tmp_s_reg_761_pp0_iter3_reg; + tmp_s_reg_761_pp0_iter5_reg <= tmp_s_reg_761_pp0_iter4_reg; + tmp_s_reg_761_pp0_iter6_reg <= tmp_s_reg_761_pp0_iter5_reg; + tmp_s_reg_761_pp0_iter7_reg <= tmp_s_reg_761_pp0_iter6_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_730_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_load_reg_826 <= ifmap_vec_0_q0; + ifmap_vec_1_load_reg_854 <= ifmap_vec_1_q0; + weight_vecs_0_0_load_reg_834 <= weight_vecs_0_0_q0; + weight_vecs_0_1_load_reg_862 <= weight_vecs_0_1_q0; + weight_vecs_1_0_load_reg_839 <= weight_vecs_1_0_q0; + weight_vecs_1_1_load_reg_867 <= weight_vecs_1_1_q0; + weight_vecs_2_0_load_reg_844 <= weight_vecs_2_0_q0; + weight_vecs_2_1_load_reg_872 <= weight_vecs_2_1_q0; + weight_vecs_3_0_load_reg_849 <= weight_vecs_3_0_q0; + weight_vecs_3_1_load_reg_877 <= weight_vecs_3_1_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_730_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul27_1_1_reg_907 <= grp_fu_409_p2; + mul27_1_2_reg_912 <= grp_fu_413_p2; + mul27_1_3_reg_917 <= grp_fu_417_p2; + mul27_1_reg_902 <= grp_fu_405_p2; + mul_1_reg_887 <= grp_fu_393_p2; + mul_2_reg_892 <= grp_fu_397_p2; + mul_3_reg_897 <= grp_fu_401_p2; + mul_reg_882 <= grp_fu_389_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_455_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln147_11_reg_734 <= select_ln147_11_fu_489_p3; + select_ln148_7_reg_739 <= select_ln148_7_fu_591_p3; + end +end + +always @ (*) begin + if ((icmp_ln147_fu_455_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_730 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_349_p4 = select_ln147_11_reg_734; + end else begin + ap_phi_mux_ii_phi_fu_349_p4 = ii_reg_345; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_730 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_371_p4 = select_ln148_7_reg_739; + end else begin + ap_phi_mux_jj_phi_fu_371_p4 = jj_reg_367; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_1_ce0 = 1'b1; + end else begin + ifmap_vec_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_0_ce0 = 1'b1; + end else begin + products_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_0_we0 = 1'b1; + end else begin + products_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_1_ce0 = 1'b1; + end else begin + products_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_1_we0 = 1'b1; + end else begin + products_0_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_0_ce0 = 1'b1; + end else begin + products_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_0_we0 = 1'b1; + end else begin + products_1_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_1_ce0 = 1'b1; + end else begin + products_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_1_we0 = 1'b1; + end else begin + products_1_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_0_ce0 = 1'b1; + end else begin + products_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_0_we0 = 1'b1; + end else begin + products_2_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_1_ce0 = 1'b1; + end else begin + products_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_1_we0 = 1'b1; + end else begin + products_2_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_0_ce0 = 1'b1; + end else begin + products_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_0_we0 = 1'b1; + end else begin + products_3_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_1_ce0 = 1'b1; + end else begin + products_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_1_we0 = 1'b1; + end else begin + products_3_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_ce0 = 1'b1; + end else begin + weight_vecs_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_ce0 = 1'b1; + end else begin + weight_vecs_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_ce0 = 1'b1; + end else begin + weight_vecs_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_0_ce0 = 1'b1; + end else begin + weight_vecs_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_1_ce0 = 1'b1; + end else begin + weight_vecs_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_0_ce0 = 1'b1; + end else begin + weight_vecs_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_1_ce0 = 1'b1; + end else begin + weight_vecs_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln147_fu_455_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter8 == 1'b1) & (ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter8 == 1'b1) & (ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln147_fu_455_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state11; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_3_fu_421_p2 = (indvar_flatten17_reg_334 + 7'd1); + +assign add_ln147_fu_461_p2 = (ap_phi_mux_ii_phi_fu_349_p4 + 2'd1); + +assign add_ln148_3_fu_663_p2 = (indvar_flatten_reg_356 + 6'd1); + +assign add_ln148_fu_577_p2 = (select_ln147_fu_473_p3 + 2'd1); + +assign add_ln149_fu_657_p2 = (select_ln148_fu_583_p3 + 5'd2); + +assign add_ln150_3_fu_613_p2 = (select_ln147_12_fu_541_p3 + zext_ln150_7_fu_609_p1); + +assign add_ln150_fu_449_p2 = (sub_ln150_fu_439_p2 + zext_ln150_3_fu_445_p1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign empty_102_fu_513_p2 = (tmp_cast_fu_509_p1 - select_ln147_13_cast_fu_497_p1); + +assign empty_103_fu_603_p2 = ((sext_ln150_fu_519_p1) + (select_ln148_9_cast_fu_599_p1)); + +assign icmp_ln147_fu_455_p2 = ((indvar_flatten17_reg_334 == 7'd72) ? 1'b1 : 1'b0); + +assign icmp_ln148_fu_467_p2 = ((indvar_flatten_reg_356 == 6'd24) ? 1'b1 : 1'b0); + +assign ifmap_vec_0_address0 = tmp_88_fu_683_p1; + +assign ifmap_vec_1_address0 = tmp_88_fu_683_p1; + +assign lshr_ln153_5_fu_711_p3 = {{select_ln148_8_reg_749_pp0_iter7_reg}, {tmp_s_reg_761_pp0_iter7_reg}}; + +assign lshr_ln_fu_697_p3 = {{select_ln148_8_reg_749_pp0_iter7_reg}, {newIndex_reg_755_pp0_iter7_reg}}; + +assign or_ln147_fu_571_p2 = (xor_ln149_fu_565_p2 | icmp_ln148_fu_467_p2); + +assign or_ln150_fu_641_p2 = (trunc_ln149_fu_627_p1 | 4'd1); + +assign products_0_0_address0 = zext_ln153_fu_703_p1; + +assign products_0_0_d0 = mul_reg_882; + +assign products_0_1_address0 = zext_ln153_5_fu_717_p1; + +assign products_0_1_d0 = mul27_1_reg_902; + +assign products_1_0_address0 = zext_ln153_fu_703_p1; + +assign products_1_0_d0 = mul_1_reg_887; + +assign products_1_1_address0 = zext_ln153_5_fu_717_p1; + +assign products_1_1_d0 = mul27_1_1_reg_907; + +assign products_2_0_address0 = zext_ln153_fu_703_p1; + +assign products_2_0_d0 = mul_2_reg_892; + +assign products_2_1_address0 = zext_ln153_5_fu_717_p1; + +assign products_2_1_d0 = mul27_1_2_reg_912; + +assign products_3_0_address0 = zext_ln153_fu_703_p1; + +assign products_3_0_d0 = mul_3_reg_897; + +assign products_3_1_address0 = zext_ln153_5_fu_717_p1; + +assign products_3_1_d0 = mul27_1_3_reg_917; + +assign select_ln147_10_fu_481_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? 5'd0 : ic_reg_378); + +assign select_ln147_11_fu_489_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? add_ln147_fu_461_p2 : ap_phi_mux_ii_phi_fu_349_p4); + +assign select_ln147_12_fu_541_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? sub_ln150_3_fu_535_p2 : sub_ln150_fu_439_p2); + +assign select_ln147_13_cast_fu_497_p1 = select_ln147_11_fu_489_p3; + +assign select_ln147_13_fu_549_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? sub_ln150_3_fu_535_p2 : add_ln150_fu_449_p2); + +assign select_ln147_fu_473_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_371_p4); + +assign select_ln148_7_fu_591_p3 = ((or_ln147_fu_571_p2[0:0] == 1'b1) ? select_ln147_fu_473_p3 : add_ln148_fu_577_p2); + +assign select_ln148_8_fu_619_p3 = ((or_ln147_fu_571_p2[0:0] == 1'b1) ? select_ln147_13_fu_549_p3 : add_ln150_3_fu_613_p2); + +assign select_ln148_9_cast_fu_599_p1 = select_ln148_7_fu_591_p3; + +assign select_ln148_9_fu_669_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? 6'd1 : add_ln148_3_fu_663_p2); + +assign select_ln148_fu_583_p3 = ((or_ln147_fu_571_p2[0:0] == 1'b1) ? select_ln147_10_fu_481_p3 : 5'd0); + +assign sext_ln150_fu_519_p1 = (empty_102_fu_513_p2); + +assign shl_ln150_mid1_fu_527_p3 = {{add_ln147_fu_461_p2}, {2'd0}}; + +assign shl_ln_fu_431_p3 = {{ap_phi_mux_ii_phi_fu_349_p4}, {2'd0}}; + +assign sub_ln150_3_fu_535_p2 = (shl_ln150_mid1_fu_527_p3 - zext_ln150_6_fu_523_p1); + +assign sub_ln150_fu_439_p2 = (shl_ln_fu_431_p3 - zext_ln150_fu_427_p1); + +assign tmp_43_fu_557_p3 = ic_reg_378[32'd4]; + +assign tmp_44_fu_677_p3 = {{empty_103_reg_744}, {newIndex_reg_755}}; + +assign tmp_88_fu_683_p1 = (tmp_44_fu_677_p3); + +assign tmp_cast_fu_509_p1 = tmp_fu_501_p3; + +assign tmp_fu_501_p3 = {{select_ln147_11_fu_489_p3}, {2'd0}}; + +assign trunc_ln149_fu_627_p1 = select_ln148_fu_583_p3[3:0]; + +assign weight_vecs_0_0_address0 = tmp_88_fu_683_p1; + +assign weight_vecs_0_1_address0 = tmp_88_fu_683_p1; + +assign weight_vecs_1_0_address0 = tmp_88_fu_683_p1; + +assign weight_vecs_1_1_address0 = tmp_88_fu_683_p1; + +assign weight_vecs_2_0_address0 = tmp_88_fu_683_p1; + +assign weight_vecs_2_1_address0 = tmp_88_fu_683_p1; + +assign weight_vecs_3_0_address0 = tmp_88_fu_683_p1; + +assign weight_vecs_3_1_address0 = tmp_88_fu_683_p1; + +assign xor_ln149_fu_565_p2 = (tmp_43_fu_557_p3 ^ 1'd1); + +assign zext_ln150_3_fu_445_p1 = ap_phi_mux_jj_phi_fu_371_p4; + +assign zext_ln150_6_fu_523_p1 = add_ln147_fu_461_p2; + +assign zext_ln150_7_fu_609_p1 = add_ln148_fu_577_p2; + +assign zext_ln150_fu_427_p1 = ap_phi_mux_ii_phi_fu_349_p4; + +assign zext_ln153_5_fu_717_p1 = lshr_ln153_5_fu_711_p3; + +assign zext_ln153_fu_703_p1 = lshr_ln_fu_697_p3; + +endmodule //td_fused_top_tdf5_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf5_filters_0_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 32; +parameter AWIDTH = 12; +parameter MEM_SIZE = 2304; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf5_filters_0( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd32; +parameter AddressRange = 32'd2304; +parameter AddressWidth = 32'd12; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf5_filters_0_ram td_fused_top_tdf5_filters_0_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + module td_fused_top_tdf5_filters_1_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 32; +parameter AWIDTH = 12; +parameter MEM_SIZE = 2304; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf5_filters_1_rom.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf5_filters_1( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd32; +parameter AddressRange = 32'd2304; +parameter AddressWidth = 32'd12; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +td_fused_top_tdf5_filters_1_rom td_fused_top_tdf5_filters_1_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + input_indices_2_out_din, + input_indices_2_out_full_n, + input_indices_2_out_write, + input_indices_2_out1_din, + input_indices_2_out1_full_n, + input_indices_2_out1_write, + output_indices_0_din, + output_indices_0_full_n, + output_indices_0_write, + output_indices_1_din, + output_indices_1_full_n, + output_indices_1_write, + resetMaximum_din, + resetMaximum_full_n, + resetMaximum_write, + storeOutput_din, + storeOutput_full_n, + storeOutput_write, + ap_return_0, + ap_return_1 +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [4:0] input_indices_2_out_din; +input input_indices_2_out_full_n; +output input_indices_2_out_write; +output [6:0] input_indices_2_out1_din; +input input_indices_2_out1_full_n; +output input_indices_2_out1_write; +output [4:0] output_indices_0_din; +input output_indices_0_full_n; +output output_indices_0_write; +output [9:0] output_indices_1_din; +input output_indices_1_full_n; +output output_indices_1_write; +output resetMaximum_din; +input resetMaximum_full_n; +output resetMaximum_write; +output storeOutput_din; +input storeOutput_full_n; +output storeOutput_write; +output [15:0] ap_return_0; +output [15:0] ap_return_1; + +reg ap_done; +reg ap_idle; +reg start_write; +reg input_indices_2_out_write; +reg input_indices_2_out1_write; +reg output_indices_0_write; +reg output_indices_1_write; +reg resetMaximum_write; +reg storeOutput_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [1:0] i_p_1; +reg [1:0] j_p_1; +reg [15:0] i_3; +reg [15:0] j_3; +reg [15:0] k_3; +reg [15:0] i_out_1; +reg [15:0] j_out_1; +reg input_indices_2_out_blk_n; +reg input_indices_2_out1_blk_n; +reg output_indices_0_blk_n; +reg output_indices_1_blk_n; +reg resetMaximum_blk_n; +reg storeOutput_blk_n; +wire [1:0] select_ln172_fu_342_p3; +reg ap_block_state1; +wire [0:0] or_ln172_fu_316_p2; +wire [1:0] select_ln172_1_fu_350_p3; +wire [15:0] select_ln177_fu_282_p3; +wire [0:0] and_ln172_1_fu_310_p2; +wire [15:0] select_ln172_2_fu_364_p3; +wire [0:0] and_ln162_fu_358_p2; +wire [15:0] select_ln172_3_fu_392_p3; +wire [0:0] and_ln165_fu_298_p2; +wire [15:0] select_ln177_1_fu_290_p3; +wire [15:0] select_ln172_4_fu_400_p3; +wire [1:0] or_ln154_fu_126_p2; +wire [0:0] icmp_ln155_fu_139_p2; +wire [0:0] icmp_ln155_1_fu_145_p2; +wire [15:0] zext_ln156_fu_114_p1; +wire [15:0] zext_ln157_fu_122_p1; +wire [1:0] add_ln161_fu_210_p2; +wire [1:0] add_ln164_fu_222_p2; +wire [15:0] add_ln167_fu_234_p2; +wire [15:0] add_ln171_fu_252_p2; +wire [15:0] add_ln176_fu_270_p2; +wire [0:0] icmp_ln177_fu_276_p2; +wire [15:0] add_ln175_fu_264_p2; +wire [0:0] icmp_ln162_fu_216_p2; +wire [0:0] icmp_ln165_fu_228_p2; +wire [0:0] icmp_ln168_fu_240_p2; +wire [0:0] icmp_ln172_fu_258_p2; +wire [0:0] and_ln172_fu_304_p2; +wire [0:0] xor_ln165_fu_322_p2; +wire [0:0] and_ln165_1_fu_328_p2; +wire [1:0] select_ln165_fu_334_p3; +wire [15:0] add_ln170_fu_246_p2; +wire [0:0] xor_ln168_fu_372_p2; +wire [0:0] and_ln168_fu_378_p2; +wire [15:0] select_ln168_fu_384_p3; +wire [15:0] add_ln156_fu_162_p2; +wire [15:0] add_ln157_fu_172_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_p_1 = 2'd0; +#0 j_p_1 = 2'd0; +#0 i_3 = 16'd0; +#0 j_3 = 16'd0; +#0 k_3 = 16'd0; +#0 i_out_1 = 16'd0; +#0 j_out_1 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln172_1_fu_310_p2))) begin + i_3 <= select_ln177_fu_282_p3; + i_out_1 <= select_ln177_1_fu_290_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (or_ln172_fu_316_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_p_1 <= select_ln172_fu_342_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln162_fu_358_p2))) begin + j_3 <= select_ln172_2_fu_364_p3; + j_out_1 <= select_ln172_4_fu_400_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + j_p_1 <= select_ln172_1_fu_350_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln165_fu_298_p2))) begin + k_3 <= select_ln172_3_fu_392_p3; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_blk_n = input_indices_2_out1_full_n; + end else begin + input_indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_write = 1'b1; + end else begin + input_indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_blk_n = input_indices_2_out_full_n; + end else begin + input_indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_write = 1'b1; + end else begin + input_indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_blk_n = output_indices_0_full_n; + end else begin + output_indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_write = 1'b1; + end else begin + output_indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_blk_n = output_indices_1_full_n; + end else begin + output_indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_write = 1'b1; + end else begin + output_indices_1_write = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_blk_n = resetMaximum_full_n; + end else begin + resetMaximum_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_write = 1'b1; + end else begin + resetMaximum_write = 1'b0; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_blk_n = storeOutput_full_n; + end else begin + storeOutput_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_write = 1'b1; + end else begin + storeOutput_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln156_fu_162_p2 = (i_3 + zext_ln156_fu_114_p1); + +assign add_ln157_fu_172_p2 = (j_3 + zext_ln157_fu_122_p1); + +assign add_ln161_fu_210_p2 = (j_p_1 + 2'd1); + +assign add_ln164_fu_222_p2 = (i_p_1 + 2'd1); + +assign add_ln167_fu_234_p2 = (k_3 + 16'd1); + +assign add_ln170_fu_246_p2 = (j_3 + 16'd2); + +assign add_ln171_fu_252_p2 = (j_out_1 + 16'd1); + +assign add_ln175_fu_264_p2 = (i_3 + 16'd2); + +assign add_ln176_fu_270_p2 = (i_out_1 + 16'd1); + +assign and_ln162_fu_358_p2 = (icmp_ln168_fu_240_p2 & and_ln165_fu_298_p2); + +assign and_ln165_1_fu_328_p2 = (xor_ln165_fu_322_p2 & icmp_ln162_fu_216_p2); + +assign and_ln165_fu_298_p2 = (icmp_ln165_fu_228_p2 & icmp_ln162_fu_216_p2); + +assign and_ln168_fu_378_p2 = (xor_ln168_fu_372_p2 & and_ln165_fu_298_p2); + +assign and_ln172_1_fu_310_p2 = (and_ln172_fu_304_p2 & and_ln165_fu_298_p2); + +assign and_ln172_fu_304_p2 = (icmp_ln172_fu_258_p2 & icmp_ln168_fu_240_p2); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign ap_return_0 = add_ln156_fu_162_p2; + +assign ap_return_1 = add_ln157_fu_172_p2; + +assign icmp_ln155_1_fu_145_p2 = ((j_p_1 == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln155_fu_139_p2 = ((i_p_1 == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln162_fu_216_p2 = ((add_ln161_fu_210_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln165_fu_228_p2 = ((add_ln164_fu_222_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln168_fu_240_p2 = ((add_ln167_fu_234_p2 == 16'd32) ? 1'b1 : 1'b0); + +assign icmp_ln172_fu_258_p2 = ((add_ln171_fu_252_p2 == 16'd28) ? 1'b1 : 1'b0); + +assign icmp_ln177_fu_276_p2 = ((add_ln176_fu_270_p2 == 16'd28) ? 1'b1 : 1'b0); + +assign input_indices_2_out1_din = k_3[6:0]; + +assign input_indices_2_out_din = k_3[4:0]; + +assign or_ln154_fu_126_p2 = (j_p_1 | i_p_1); + +assign or_ln172_fu_316_p2 = (icmp_ln162_fu_216_p2 | and_ln172_1_fu_310_p2); + +assign output_indices_0_din = i_out_1[4:0]; + +assign output_indices_1_din = j_out_1[9:0]; + +assign resetMaximum_din = ((or_ln154_fu_126_p2 == 2'd0) ? 1'b1 : 1'b0); + +assign select_ln165_fu_334_p3 = ((and_ln165_1_fu_328_p2[0:0] == 1'b1) ? add_ln164_fu_222_p2 : 2'd0); + +assign select_ln168_fu_384_p3 = ((and_ln168_fu_378_p2[0:0] == 1'b1) ? add_ln167_fu_234_p2 : 16'd0); + +assign select_ln172_1_fu_350_p3 = ((or_ln172_fu_316_p2[0:0] == 1'b1) ? 2'd0 : add_ln161_fu_210_p2); + +assign select_ln172_2_fu_364_p3 = ((and_ln172_1_fu_310_p2[0:0] == 1'b1) ? 16'd0 : add_ln170_fu_246_p2); + +assign select_ln172_3_fu_392_p3 = ((and_ln172_1_fu_310_p2[0:0] == 1'b1) ? 16'd0 : select_ln168_fu_384_p3); + +assign select_ln172_4_fu_400_p3 = ((and_ln172_1_fu_310_p2[0:0] == 1'b1) ? 16'd0 : add_ln171_fu_252_p2); + +assign select_ln172_fu_342_p3 = ((and_ln172_1_fu_310_p2[0:0] == 1'b1) ? 2'd0 : select_ln165_fu_334_p3); + +assign select_ln177_1_fu_290_p3 = ((icmp_ln177_fu_276_p2[0:0] == 1'b1) ? 16'd0 : add_ln176_fu_270_p2); + +assign select_ln177_fu_282_p3 = ((icmp_ln177_fu_276_p2[0:0] == 1'b1) ? 16'd0 : add_ln175_fu_264_p2); + +assign start_out = real_start; + +assign storeOutput_din = (icmp_ln155_fu_139_p2 & icmp_ln155_1_fu_145_p2); + +assign xor_ln165_fu_322_p2 = (icmp_ln165_fu_228_p2 ^ 1'd1); + +assign xor_ln168_fu_372_p2 = (icmp_ln168_fu_240_p2 ^ 1'd1); + +assign zext_ln156_fu_114_p1 = i_p_1; + +assign zext_ln157_fu_122_p1 = j_p_1; + +endmodule //td_fused_top_tdf5_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_poolOutputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + output_indices_04_dout, + output_indices_04_empty_n, + output_indices_04_read, + output_indices_15_dout, + output_indices_15_empty_n, + output_indices_15_read, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + resetMaximum6_dout, + resetMaximum6_empty_n, + resetMaximum6_read, + storeOutput7_dout, + storeOutput7_empty_n, + storeOutput7_read, + outputs_0_read, + outputs_1_read, + outputs_2_read, + outputs_3_read, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_state3 = 4'd4; +parameter ap_ST_fsm_state4 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [4:0] output_indices_04_dout; +input output_indices_04_empty_n; +output output_indices_04_read; +input [9:0] output_indices_15_dout; +input output_indices_15_empty_n; +output output_indices_15_read; +input [6:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +input [0:0] resetMaximum6_dout; +input resetMaximum6_empty_n; +output resetMaximum6_read; +input [0:0] storeOutput7_dout; +input storeOutput7_empty_n; +output storeOutput7_read; +input [15:0] outputs_0_read; +input [15:0] outputs_1_read; +input [15:0] outputs_2_read; +input [15:0] outputs_3_read; +output [14:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg output_indices_04_read; +reg output_indices_15_read; +reg input_indices_23_read; +reg resetMaximum6_read; +reg storeOutput7_read; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] max_vals_5_0; +reg [15:0] max_vals_5_1; +reg [15:0] max_vals_5_2; +reg [15:0] max_vals_5_3; +reg output_indices_04_blk_n; +wire ap_CS_fsm_state2; +reg output_indices_15_blk_n; +reg input_indices_23_blk_n; +reg resetMaximum6_blk_n; +reg storeOutput7_blk_n; +reg [4:0] output_indices_04_read_reg_281; +reg [9:0] output_indices_15_read_reg_286; +reg [6:0] input_indices_23_read_reg_291; +wire [0:0] storeOutput7_read_read_fu_110_p2; +reg [0:0] storeOutput7_read_reg_296; +wire grp_tdf5_writeOutputs_aligned_fu_116_ap_start; +wire grp_tdf5_writeOutputs_aligned_fu_116_ap_done; +wire grp_tdf5_writeOutputs_aligned_fu_116_ap_idle; +wire grp_tdf5_writeOutputs_aligned_fu_116_ap_ready; +wire [14:0] grp_tdf5_writeOutputs_aligned_fu_116_out_data_address1; +wire grp_tdf5_writeOutputs_aligned_fu_116_out_data_ce1; +wire grp_tdf5_writeOutputs_aligned_fu_116_out_data_we1; +wire [63:0] grp_tdf5_writeOutputs_aligned_fu_116_out_data_d1; +reg grp_tdf5_writeOutputs_aligned_fu_116_ap_start_reg; +wire ap_CS_fsm_state3; +wire ap_CS_fsm_state4; +wire [15:0] select_ln24_fu_179_p3; +reg ap_block_state2; +wire [15:0] select_ln24_4_fu_197_p3; +wire [15:0] select_ln24_5_fu_215_p3; +wire [15:0] select_ln24_6_fu_233_p3; +reg ap_block_state1; +wire [0:0] grp_fu_133_p2; +wire [0:0] or_ln24_fu_173_p2; +wire [0:0] grp_fu_138_p2; +wire [0:0] or_ln24_4_fu_191_p2; +wire [0:0] grp_fu_143_p2; +wire [0:0] or_ln24_5_fu_209_p2; +wire [0:0] grp_fu_148_p2; +wire [0:0] or_ln24_6_fu_227_p2; +reg grp_fu_133_ce; +reg grp_fu_138_ce; +reg grp_fu_143_ce; +reg grp_fu_148_ce; +reg ap_block_state4_on_subcall_done; +reg [3:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 max_vals_5_0 = 16'd0; +#0 max_vals_5_1 = 16'd0; +#0 max_vals_5_2 = 16'd0; +#0 max_vals_5_3 = 16'd0; +#0 grp_tdf5_writeOutputs_aligned_fu_116_ap_start_reg = 1'b0; +end + +td_fused_top_tdf5_writeOutputs_aligned grp_tdf5_writeOutputs_aligned_fu_116( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(grp_tdf5_writeOutputs_aligned_fu_116_ap_start), + .ap_done(grp_tdf5_writeOutputs_aligned_fu_116_ap_done), + .ap_idle(grp_tdf5_writeOutputs_aligned_fu_116_ap_idle), + .ap_ready(grp_tdf5_writeOutputs_aligned_fu_116_ap_ready), + .i(output_indices_04_read_reg_281), + .j(output_indices_15_read_reg_286), + .k(input_indices_23_read_reg_291), + .out_data_address1(grp_tdf5_writeOutputs_aligned_fu_116_out_data_address1), + .out_data_ce1(grp_tdf5_writeOutputs_aligned_fu_116_out_data_ce1), + .out_data_we1(grp_tdf5_writeOutputs_aligned_fu_116_out_data_we1), + .out_data_d1(grp_tdf5_writeOutputs_aligned_fu_116_out_data_d1), + .max_vals_5_0(max_vals_5_0), + .max_vals_5_1(max_vals_5_1), + .max_vals_5_2(max_vals_5_2), + .max_vals_5_3(max_vals_5_3) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U826( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_133_ce), + .din0(max_vals_5_0), + .din1(outputs_0_read), + .opcode(5'd4), + .dout(grp_fu_133_p2) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U827( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_138_ce), + .din0(max_vals_5_1), + .din1(outputs_1_read), + .opcode(5'd4), + .dout(grp_fu_138_p2) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U828( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_143_ce), + .din0(max_vals_5_2), + .din1(outputs_2_read), + .opcode(5'd4), + .dout(grp_fu_143_p2) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U829( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_148_ce), + .din0(max_vals_5_3), + .din1(outputs_3_read), + .opcode(5'd4), + .dout(grp_fu_148_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + grp_tdf5_writeOutputs_aligned_fu_116_ap_start_reg <= 1'b0; + end else begin + if ((1'b1 == ap_CS_fsm_state3)) begin + grp_tdf5_writeOutputs_aligned_fu_116_ap_start_reg <= 1'b1; + end else if ((grp_tdf5_writeOutputs_aligned_fu_116_ap_ready == 1'b1)) begin + grp_tdf5_writeOutputs_aligned_fu_116_ap_start_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + input_indices_23_read_reg_291 <= input_indices_23_dout; + output_indices_04_read_reg_281 <= output_indices_04_dout; + output_indices_15_read_reg_286 <= output_indices_15_dout; + storeOutput7_read_reg_296 <= storeOutput7_dout; + end +end + +always @ (posedge ap_clk) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + max_vals_5_0 <= select_ln24_fu_179_p3; + max_vals_5_1 <= select_ln24_4_fu_197_p3; + max_vals_5_2 <= select_ln24_5_fu_215_p3; + max_vals_5_3 <= select_ln24_6_fu_233_p3; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_133_ce = 1'b1; + end else begin + grp_fu_133_ce = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_138_ce = 1'b1; + end else begin + grp_fu_138_ce = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_143_ce = 1'b1; + end else begin + grp_fu_143_ce = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_148_ce = 1'b1; + end else begin + grp_fu_148_ce = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_04_blk_n = output_indices_04_empty_n; + end else begin + output_indices_04_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_04_read = 1'b1; + end else begin + output_indices_04_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_15_blk_n = output_indices_15_empty_n; + end else begin + output_indices_15_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_15_read = 1'b1; + end else begin + output_indices_15_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + resetMaximum6_blk_n = resetMaximum6_empty_n; + end else begin + resetMaximum6_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + resetMaximum6_read = 1'b1; + end else begin + resetMaximum6_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + storeOutput7_blk_n = storeOutput7_empty_n; + end else begin + storeOutput7_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + storeOutput7_read = 1'b1; + end else begin + storeOutput7_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_110_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_110_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state3; + end else begin + ap_NS_fsm = ap_ST_fsm_state2; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +always @ (*) begin + ap_block_state2 = ((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)); +end + +always @ (*) begin + ap_block_state4_on_subcall_done = ((grp_tdf5_writeOutputs_aligned_fu_116_ap_done == 1'b0) & (storeOutput7_read_reg_296 == 1'd1)); +end + +assign grp_tdf5_writeOutputs_aligned_fu_116_ap_start = grp_tdf5_writeOutputs_aligned_fu_116_ap_start_reg; + +assign or_ln24_4_fu_191_p2 = (resetMaximum6_dout | grp_fu_138_p2); + +assign or_ln24_5_fu_209_p2 = (resetMaximum6_dout | grp_fu_143_p2); + +assign or_ln24_6_fu_227_p2 = (resetMaximum6_dout | grp_fu_148_p2); + +assign or_ln24_fu_173_p2 = (resetMaximum6_dout | grp_fu_133_p2); + +assign out_data_address1 = grp_tdf5_writeOutputs_aligned_fu_116_out_data_address1; + +assign out_data_ce1 = grp_tdf5_writeOutputs_aligned_fu_116_out_data_ce1; + +assign out_data_d1 = grp_tdf5_writeOutputs_aligned_fu_116_out_data_d1; + +assign out_data_we1 = grp_tdf5_writeOutputs_aligned_fu_116_out_data_we1; + +assign select_ln24_4_fu_197_p3 = ((or_ln24_4_fu_191_p2[0:0] == 1'b1) ? outputs_1_read : max_vals_5_1); + +assign select_ln24_5_fu_215_p3 = ((or_ln24_5_fu_209_p2[0:0] == 1'b1) ? outputs_2_read : max_vals_5_2); + +assign select_ln24_6_fu_233_p3 = ((or_ln24_6_fu_227_p2[0:0] == 1'b1) ? outputs_3_read : max_vals_5_3); + +assign select_ln24_fu_179_p3 = ((or_ln24_fu_173_p2[0:0] == 1'b1) ? outputs_0_read : max_vals_5_0); + +assign storeOutput7_read_read_fu_110_p2 = storeOutput7_dout; + +endmodule //td_fused_top_tdf5_poolOutputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_readFilters41 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_0_address0, + filter_data_0_ce0, + filter_data_0_q0, + filter_data_1_address0, + filter_data_1_ce0, + filter_data_1_q0, + filter_data_2_address0, + filter_data_2_ce0, + filter_data_2_q0, + filter_data_3_address0, + filter_data_3_ce0, + filter_data_3_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + weight_vecs_0_0_address0, + weight_vecs_0_0_ce0, + weight_vecs_0_0_we0, + weight_vecs_0_0_d0, + weight_vecs_0_1_address0, + weight_vecs_0_1_ce0, + weight_vecs_0_1_we0, + weight_vecs_0_1_d0, + weight_vecs_1_0_address0, + weight_vecs_1_0_ce0, + weight_vecs_1_0_we0, + weight_vecs_1_0_d0, + weight_vecs_1_1_address0, + weight_vecs_1_1_ce0, + weight_vecs_1_1_we0, + weight_vecs_1_1_d0, + weight_vecs_2_0_address0, + weight_vecs_2_0_ce0, + weight_vecs_2_0_we0, + weight_vecs_2_0_d0, + weight_vecs_2_1_address0, + weight_vecs_2_1_ce0, + weight_vecs_2_1_we0, + weight_vecs_2_1_d0, + weight_vecs_3_0_address0, + weight_vecs_3_0_ce0, + weight_vecs_3_0_we0, + weight_vecs_3_0_d0, + weight_vecs_3_1_address0, + weight_vecs_3_1_ce0, + weight_vecs_3_1_we0, + weight_vecs_3_1_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state6 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [11:0] filter_data_0_address0; +output filter_data_0_ce0; +input [31:0] filter_data_0_q0; +output [11:0] filter_data_1_address0; +output filter_data_1_ce0; +input [31:0] filter_data_1_q0; +output [11:0] filter_data_2_address0; +output filter_data_2_ce0; +input [31:0] filter_data_2_q0; +output [11:0] filter_data_3_address0; +output filter_data_3_ce0; +input [31:0] filter_data_3_q0; +input [4:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [6:0] weight_vecs_0_0_address0; +output weight_vecs_0_0_ce0; +output weight_vecs_0_0_we0; +output [15:0] weight_vecs_0_0_d0; +output [6:0] weight_vecs_0_1_address0; +output weight_vecs_0_1_ce0; +output weight_vecs_0_1_we0; +output [15:0] weight_vecs_0_1_d0; +output [6:0] weight_vecs_1_0_address0; +output weight_vecs_1_0_ce0; +output weight_vecs_1_0_we0; +output [15:0] weight_vecs_1_0_d0; +output [6:0] weight_vecs_1_1_address0; +output weight_vecs_1_1_ce0; +output weight_vecs_1_1_we0; +output [15:0] weight_vecs_1_1_d0; +output [6:0] weight_vecs_2_0_address0; +output weight_vecs_2_0_ce0; +output weight_vecs_2_0_we0; +output [15:0] weight_vecs_2_0_d0; +output [6:0] weight_vecs_2_1_address0; +output weight_vecs_2_1_ce0; +output weight_vecs_2_1_we0; +output [15:0] weight_vecs_2_1_d0; +output [6:0] weight_vecs_3_0_address0; +output weight_vecs_3_0_ce0; +output weight_vecs_3_0_we0; +output [15:0] weight_vecs_3_0_d0; +output [6:0] weight_vecs_3_1_address0; +output weight_vecs_3_1_ce0; +output weight_vecs_3_1_we0; +output [15:0] weight_vecs_3_1_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_0_ce0; +reg filter_data_1_ce0; +reg filter_data_2_ce0; +reg filter_data_3_ce0; +reg input_indices_23_read; +reg weight_vecs_0_0_ce0; +reg weight_vecs_0_0_we0; +reg weight_vecs_0_1_ce0; +reg weight_vecs_0_1_we0; +reg weight_vecs_1_0_ce0; +reg weight_vecs_1_0_we0; +reg weight_vecs_1_1_ce0; +reg weight_vecs_1_1_we0; +reg weight_vecs_2_0_ce0; +reg weight_vecs_2_0_we0; +reg weight_vecs_2_1_ce0; +reg weight_vecs_2_1_we0; +reg weight_vecs_3_0_ce0; +reg weight_vecs_3_0_we0; +reg weight_vecs_3_1_ce0; +reg weight_vecs_3_1_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +reg [6:0] indvar_flatten13_reg_288; +reg [1:0] ii_reg_299; +reg [5:0] indvar_flatten_reg_310; +reg [1:0] jj_reg_321; +reg [4:0] kk_reg_332; +wire [8:0] sext_ln47_fu_365_p1; +reg [8:0] sext_ln47_reg_737; +wire [6:0] add_ln47_3_fu_369_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln47_fu_375_p2; +reg [0:0] icmp_ln47_reg_747; +reg [0:0] icmp_ln47_reg_747_pp0_iter1_reg; +reg [0:0] icmp_ln47_reg_747_pp0_iter2_reg; +wire [1:0] select_ln47_6_fu_409_p3; +reg [1:0] select_ln47_6_reg_751; +wire [8:0] add_ln55_fu_421_p2; +reg [8:0] add_ln55_reg_758; +wire [1:0] select_ln48_5_fu_460_p3; +reg [1:0] select_ln48_5_reg_764; +reg [2:0] lshr_ln_reg_771; +reg [2:0] lshr_ln_reg_771_pp0_iter1_reg; +reg [2:0] lshr_ln_reg_771_pp0_iter2_reg; +wire [4:0] add_ln49_fu_478_p2; +wire [5:0] select_ln48_6_fu_490_p3; +wire [5:0] add_ln55_6_fu_554_p2; +reg [5:0] add_ln55_6_reg_787; +reg [5:0] add_ln55_6_reg_787_pp0_iter2_reg; +reg [31:0] filter_data_0_load_reg_812; +reg [31:0] filter_data_1_load_reg_817; +reg [31:0] filter_data_2_load_reg_822; +reg [31:0] filter_data_3_load_reg_827; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg [1:0] ap_phi_mux_ii_phi_fu_303_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_325_p4; +wire [63:0] tmp_27_fu_560_p3; +wire [63:0] sext_ln55_6_fu_577_p1; +wire [6:0] tmp_s_fu_347_p3; +wire [7:0] zext_ln55_15_fu_355_p1; +wire [7:0] zext_ln55_fu_343_p1; +wire [7:0] sub_ln55_fu_359_p2; +wire [0:0] icmp_ln48_fu_387_p2; +wire [1:0] add_ln47_fu_381_p2; +wire [8:0] zext_ln55_17_fu_417_p1; +wire [0:0] tmp_41_fu_426_p3; +wire [0:0] xor_ln49_fu_434_p2; +wire [1:0] select_ln47_fu_393_p3; +wire [0:0] or_ln47_fu_440_p2; +wire [4:0] select_ln47_5_fu_401_p3; +wire [1:0] add_ln48_fu_446_p2; +wire [4:0] select_ln48_fu_452_p3; +wire [5:0] add_ln48_3_fu_484_p2; +wire [10:0] tmp_40_fu_504_p3; +wire [60:0] sext_ln55_5_fu_511_p1; +wire [60:0] sext_ln55_fu_501_p1; +wire [3:0] tmp_26_fu_521_p3; +wire [4:0] zext_ln55_18_fu_528_p1; +wire [4:0] zext_ln55_16_fu_498_p1; +wire [4:0] sub_ln55_6_fu_532_p2; +wire [60:0] sub_ln55_5_fu_515_p2; +wire [60:0] zext_ln55_20_fu_545_p1; +wire [5:0] sext_ln48_fu_538_p1; +wire [5:0] zext_ln55_19_fu_542_p1; +wire [60:0] add_ln55_5_fu_548_p2; +wire [8:0] tmp_42_fu_571_p3; +wire [31:0] tmp_fu_589_p6; +wire [15:0] trunc_ln55_fu_602_p1; +wire [31:0] tmp_7_fu_611_p6; +wire [15:0] trunc_ln55_7_fu_624_p1; +wire [31:0] tmp_8_fu_633_p6; +wire [15:0] trunc_ln55_8_fu_646_p1; +wire [31:0] tmp_9_fu_655_p6; +wire [15:0] trunc_ln55_9_fu_668_p1; +wire [15:0] tmp_131_i_i_fu_677_p4; +wire [15:0] tmp_133_i_i_fu_692_p4; +wire [15:0] tmp_135_i_i_fu_707_p4; +wire [15:0] tmp_137_i_i_fu_722_p4; +wire ap_CS_fsm_state6; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +end + +td_fused_top_mux_416_32_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 32 ), + .din2_WIDTH( 32 ), + .din3_WIDTH( 32 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 32 )) +mux_416_32_1_1_U735( + .din0(filter_data_0_load_reg_812), + .din1(32'd0), + .din2(32'd0), + .din3(32'd0), + .din4(16'd0), + .dout(tmp_fu_589_p6) +); + +td_fused_top_mux_416_32_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 32 ), + .din2_WIDTH( 32 ), + .din3_WIDTH( 32 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 32 )) +mux_416_32_1_1_U736( + .din0(filter_data_1_load_reg_817), + .din1(32'd0), + .din2(32'd0), + .din3(32'd0), + .din4(16'd0), + .dout(tmp_7_fu_611_p6) +); + +td_fused_top_mux_416_32_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 32 ), + .din2_WIDTH( 32 ), + .din3_WIDTH( 32 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 32 )) +mux_416_32_1_1_U737( + .din0(filter_data_2_load_reg_822), + .din1(32'd0), + .din2(32'd0), + .din3(32'd0), + .din4(16'd0), + .dout(tmp_8_fu_633_p6) +); + +td_fused_top_mux_416_32_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 32 ), + .din2_WIDTH( 32 ), + .din3_WIDTH( 32 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 32 )) +mux_416_32_1_1_U738( + .din0(filter_data_3_load_reg_827), + .din1(32'd0), + .din2(32'd0), + .din3(32'd0), + .din4(16'd0), + .dout(tmp_9_fu_655_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_747 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_299 <= select_ln47_6_reg_751; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_299 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_375_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten13_reg_288 <= add_ln47_3_fu_369_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_288 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_375_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten_reg_310 <= select_ln48_6_fu_490_p3; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_310 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_747 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_321 <= select_ln48_5_reg_764; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_321 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_375_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + kk_reg_332 <= add_ln49_fu_478_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_332 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_747 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln55_6_reg_787 <= add_ln55_6_fu_554_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln55_6_reg_787_pp0_iter2_reg <= add_ln55_6_reg_787; + icmp_ln47_reg_747_pp0_iter2_reg <= icmp_ln47_reg_747_pp0_iter1_reg; + lshr_ln_reg_771_pp0_iter2_reg <= lshr_ln_reg_771_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_375_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln55_reg_758 <= add_ln55_fu_421_p2; + lshr_ln_reg_771 <= {{select_ln48_fu_452_p3[3:1]}}; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_747_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_0_load_reg_812 <= filter_data_0_q0; + filter_data_1_load_reg_817 <= filter_data_1_q0; + filter_data_2_load_reg_822 <= filter_data_2_q0; + filter_data_3_load_reg_827 <= filter_data_3_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln47_reg_747 <= icmp_ln47_fu_375_p2; + icmp_ln47_reg_747_pp0_iter1_reg <= icmp_ln47_reg_747; + lshr_ln_reg_771_pp0_iter1_reg <= lshr_ln_reg_771; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_375_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln47_6_reg_751 <= select_ln47_6_fu_409_p3; + select_ln48_5_reg_764 <= select_ln48_5_fu_460_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sext_ln47_reg_737 <= sext_ln47_fu_365_p1; + end +end + +always @ (*) begin + if ((icmp_ln47_fu_375_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_747 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_303_p4 = select_ln47_6_reg_751; + end else begin + ap_phi_mux_ii_phi_fu_303_p4 = ii_reg_299; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_747 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_325_p4 = select_ln48_5_reg_764; + end else begin + ap_phi_mux_jj_phi_fu_325_p4 = jj_reg_321; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_0_ce0 = 1'b1; + end else begin + filter_data_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_1_ce0 = 1'b1; + end else begin + filter_data_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_2_ce0 = 1'b1; + end else begin + filter_data_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_3_ce0 = 1'b1; + end else begin + filter_data_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_ce0 = 1'b1; + end else begin + weight_vecs_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_we0 = 1'b1; + end else begin + weight_vecs_0_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_ce0 = 1'b1; + end else begin + weight_vecs_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_we0 = 1'b1; + end else begin + weight_vecs_1_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_ce0 = 1'b1; + end else begin + weight_vecs_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_we0 = 1'b1; + end else begin + weight_vecs_1_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_0_ce0 = 1'b1; + end else begin + weight_vecs_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_0_we0 = 1'b1; + end else begin + weight_vecs_2_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_1_ce0 = 1'b1; + end else begin + weight_vecs_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_1_we0 = 1'b1; + end else begin + weight_vecs_2_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_0_ce0 = 1'b1; + end else begin + weight_vecs_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_0_we0 = 1'b1; + end else begin + weight_vecs_3_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_1_ce0 = 1'b1; + end else begin + weight_vecs_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_1_we0 = 1'b1; + end else begin + weight_vecs_3_1_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln47_fu_375_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln47_fu_375_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln47_3_fu_369_p2 = (indvar_flatten13_reg_288 + 7'd1); + +assign add_ln47_fu_381_p2 = (ap_phi_mux_ii_phi_fu_303_p4 + 2'd1); + +assign add_ln48_3_fu_484_p2 = (indvar_flatten_reg_310 + 6'd1); + +assign add_ln48_fu_446_p2 = (select_ln47_fu_393_p3 + 2'd1); + +assign add_ln49_fu_478_p2 = (select_ln48_fu_452_p3 + 5'd2); + +assign add_ln55_5_fu_548_p2 = (sub_ln55_5_fu_515_p2 + zext_ln55_20_fu_545_p1); + +assign add_ln55_6_fu_554_p2 = ((sext_ln48_fu_538_p1) + (zext_ln55_19_fu_542_p1)); + +assign add_ln55_fu_421_p2 = ((sext_ln47_reg_737) + (zext_ln55_17_fu_417_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_0_address0 = tmp_27_fu_560_p3; + +assign filter_data_1_address0 = tmp_27_fu_560_p3; + +assign filter_data_2_address0 = tmp_27_fu_560_p3; + +assign filter_data_3_address0 = tmp_27_fu_560_p3; + +assign icmp_ln47_fu_375_p2 = ((indvar_flatten13_reg_288 == 7'd72) ? 1'b1 : 1'b0); + +assign icmp_ln48_fu_387_p2 = ((indvar_flatten_reg_310 == 6'd24) ? 1'b1 : 1'b0); + +assign or_ln47_fu_440_p2 = (xor_ln49_fu_434_p2 | icmp_ln48_fu_387_p2); + +assign select_ln47_5_fu_401_p3 = ((icmp_ln48_fu_387_p2[0:0] == 1'b1) ? 5'd0 : kk_reg_332); + +assign select_ln47_6_fu_409_p3 = ((icmp_ln48_fu_387_p2[0:0] == 1'b1) ? add_ln47_fu_381_p2 : ap_phi_mux_ii_phi_fu_303_p4); + +assign select_ln47_fu_393_p3 = ((icmp_ln48_fu_387_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_325_p4); + +assign select_ln48_5_fu_460_p3 = ((or_ln47_fu_440_p2[0:0] == 1'b1) ? select_ln47_fu_393_p3 : add_ln48_fu_446_p2); + +assign select_ln48_6_fu_490_p3 = ((icmp_ln48_fu_387_p2[0:0] == 1'b1) ? 6'd1 : add_ln48_3_fu_484_p2); + +assign select_ln48_fu_452_p3 = ((or_ln47_fu_440_p2[0:0] == 1'b1) ? select_ln47_5_fu_401_p3 : 5'd0); + +assign sext_ln47_fu_365_p1 = (sub_ln55_fu_359_p2); + +assign sext_ln48_fu_538_p1 = (sub_ln55_6_fu_532_p2); + +assign sext_ln55_5_fu_511_p1 = (tmp_40_fu_504_p3); + +assign sext_ln55_6_fu_577_p1 = (tmp_42_fu_571_p3); + +assign sext_ln55_fu_501_p1 = add_ln55_reg_758; + +assign sub_ln55_5_fu_515_p2 = ((sext_ln55_5_fu_511_p1) - (sext_ln55_fu_501_p1)); + +assign sub_ln55_6_fu_532_p2 = (zext_ln55_18_fu_528_p1 - zext_ln55_16_fu_498_p1); + +assign sub_ln55_fu_359_p2 = (zext_ln55_15_fu_355_p1 - zext_ln55_fu_343_p1); + +assign tmp_131_i_i_fu_677_p4 = {{tmp_fu_589_p6[31:16]}}; + +assign tmp_133_i_i_fu_692_p4 = {{tmp_7_fu_611_p6[31:16]}}; + +assign tmp_135_i_i_fu_707_p4 = {{tmp_8_fu_633_p6[31:16]}}; + +assign tmp_137_i_i_fu_722_p4 = {{tmp_9_fu_655_p6[31:16]}}; + +assign tmp_26_fu_521_p3 = {{select_ln47_6_reg_751}, {2'd0}}; + +assign tmp_27_fu_560_p3 = {{add_ln55_5_fu_548_p2}, {lshr_ln_reg_771}}; + +assign tmp_40_fu_504_p3 = {{add_ln55_reg_758}, {2'd0}}; + +assign tmp_41_fu_426_p3 = kk_reg_332[32'd4]; + +assign tmp_42_fu_571_p3 = {{add_ln55_6_reg_787_pp0_iter2_reg}, {lshr_ln_reg_771_pp0_iter2_reg}}; + +assign tmp_s_fu_347_p3 = {{input_indices_23_dout}, {2'd0}}; + +assign trunc_ln55_7_fu_624_p1 = tmp_7_fu_611_p6[15:0]; + +assign trunc_ln55_8_fu_646_p1 = tmp_8_fu_633_p6[15:0]; + +assign trunc_ln55_9_fu_668_p1 = tmp_9_fu_655_p6[15:0]; + +assign trunc_ln55_fu_602_p1 = tmp_fu_589_p6[15:0]; + +assign weight_vecs_0_0_address0 = sext_ln55_6_fu_577_p1; + +assign weight_vecs_0_0_d0 = trunc_ln55_fu_602_p1; + +assign weight_vecs_0_1_address0 = sext_ln55_6_fu_577_p1; + +assign weight_vecs_0_1_d0 = tmp_131_i_i_fu_677_p4; + +assign weight_vecs_1_0_address0 = sext_ln55_6_fu_577_p1; + +assign weight_vecs_1_0_d0 = trunc_ln55_7_fu_624_p1; + +assign weight_vecs_1_1_address0 = sext_ln55_6_fu_577_p1; + +assign weight_vecs_1_1_d0 = tmp_133_i_i_fu_692_p4; + +assign weight_vecs_2_0_address0 = sext_ln55_6_fu_577_p1; + +assign weight_vecs_2_0_d0 = trunc_ln55_8_fu_646_p1; + +assign weight_vecs_2_1_address0 = sext_ln55_6_fu_577_p1; + +assign weight_vecs_2_1_d0 = tmp_135_i_i_fu_707_p4; + +assign weight_vecs_3_0_address0 = sext_ln55_6_fu_577_p1; + +assign weight_vecs_3_0_d0 = trunc_ln55_9_fu_668_p1; + +assign weight_vecs_3_1_address0 = sext_ln55_6_fu_577_p1; + +assign weight_vecs_3_1_d0 = tmp_137_i_i_fu_722_p4; + +assign xor_ln49_fu_434_p2 = (tmp_41_fu_426_p3 ^ 1'd1); + +assign zext_ln55_15_fu_355_p1 = tmp_s_fu_347_p3; + +assign zext_ln55_16_fu_498_p1 = select_ln47_6_reg_751; + +assign zext_ln55_17_fu_417_p1 = select_ln47_6_fu_409_p3; + +assign zext_ln55_18_fu_528_p1 = tmp_26_fu_521_p3; + +assign zext_ln55_19_fu_542_p1 = select_ln48_5_reg_764; + +assign zext_ln55_20_fu_545_p1 = select_ln48_5_reg_764; + +assign zext_ln55_fu_343_p1 = input_indices_23_dout; + +endmodule //td_fused_top_tdf5_readFilters41 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_readInputs42 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + i_15, + j_15, + ifmap_vec_0_address0, + ifmap_vec_0_ce0, + ifmap_vec_0_we0, + ifmap_vec_0_d0, + ifmap_vec_1_address0, + ifmap_vec_1_ce0, + ifmap_vec_1_we0, + ifmap_vec_1_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state7 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [13:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] i_15; +input [15:0] j_15; +output [6:0] ifmap_vec_0_address0; +output ifmap_vec_0_ce0; +output ifmap_vec_0_we0; +output [15:0] ifmap_vec_0_d0; +output [6:0] ifmap_vec_1_address0; +output ifmap_vec_1_ce0; +output ifmap_vec_1_we0; +output [15:0] ifmap_vec_1_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg ifmap_vec_0_ce0; +reg ifmap_vec_0_we0; +reg ifmap_vec_1_ce0; +reg ifmap_vec_1_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [6:0] indvar_flatten47_reg_175; +reg [1:0] ii_reg_186; +reg [5:0] indvar_flatten_reg_198; +reg [1:0] jj_reg_209; +reg [4:0] kk_reg_221; +wire [17:0] p_cast_i_fu_250_p1; +reg [17:0] p_cast_i_reg_1041; +wire [11:0] trunc_ln22_fu_254_p1; +reg [11:0] trunc_ln22_reg_1047; +wire [17:0] sext_ln22_fu_264_p1; +reg [17:0] sext_ln22_reg_1053; +wire [5:0] p_cast_fu_268_p2; +reg [5:0] p_cast_reg_1059; +wire [0:0] or_ln23_11_fu_288_p2; +reg [0:0] or_ln23_11_reg_1065; +wire [11:0] p_mid137_fu_294_p2; +reg [11:0] p_mid137_reg_1070; +wire [6:0] add_ln19_3_fu_300_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_pp0_stage0_11001; +wire [0:0] empty_97_fu_315_p2; +reg [0:0] empty_97_reg_1080; +wire [0:0] is_padding_fu_350_p2; +reg [0:0] is_padding_reg_1085; +wire [0:0] icmp_ln19_fu_356_p2; +reg [0:0] icmp_ln19_reg_1092; +reg [0:0] icmp_ln19_reg_1092_pp0_iter1_reg; +reg [0:0] icmp_ln19_reg_1092_pp0_iter2_reg; +reg [0:0] icmp_ln19_reg_1092_pp0_iter3_reg; +wire [1:0] add_ln19_fu_362_p2; +reg [1:0] add_ln19_reg_1096; +wire [0:0] icmp_ln20_fu_368_p2; +reg [0:0] icmp_ln20_reg_1101; +wire [1:0] select_ln19_16_fu_390_p3; +reg [1:0] select_ln19_16_reg_1110; +wire [0:0] p_mid113_fu_407_p2; +reg [0:0] p_mid113_reg_1117; +wire [0:0] or_ln19_fu_427_p2; +reg [0:0] or_ln19_reg_1123; +reg [0:0] or_ln19_reg_1123_pp0_iter1_reg; +wire [1:0] add_ln20_fu_433_p2; +reg [1:0] add_ln20_reg_1130; +wire [1:0] select_ln20_11_fu_447_p3; +reg [1:0] select_ln20_11_reg_1135; +wire [17:0] add_ln22_4_fu_459_p2; +reg [17:0] add_ln22_4_reg_1141; +reg [1:0] lshr_ln_reg_1147; +reg [1:0] lshr_ln_reg_1147_pp0_iter1_reg; +wire [1:0] trunc_ln32_fu_474_p1; +reg [1:0] trunc_ln32_reg_1152; +reg [1:0] trunc_ln32_reg_1152_pp0_iter1_reg; +reg [1:0] trunc_ln32_reg_1152_pp0_iter2_reg; +reg [2:0] lshr_ln3_reg_1158; +reg [2:0] lshr_ln3_reg_1158_pp0_iter1_reg; +reg [2:0] lshr_ln3_reg_1158_pp0_iter2_reg; +reg [2:0] lshr_ln3_reg_1158_pp0_iter3_reg; +wire [4:0] add_ln25_fu_488_p2; +wire [5:0] select_ln20_15_fu_500_p3; +wire [11:0] select_ln19_21_fu_626_p3; +reg [11:0] select_ln19_21_reg_1173; +wire [5:0] add_ln33_fu_636_p2; +reg [5:0] add_ln33_reg_1178; +reg [5:0] add_ln33_reg_1178_pp0_iter2_reg; +reg [5:0] add_ln33_reg_1178_pp0_iter3_reg; +wire [0:0] or_ln23_15_fu_663_p2; +reg [0:0] or_ln23_15_reg_1183; +wire [0:0] select_ln20_12_fu_669_p3; +reg [0:0] select_ln20_12_reg_1188; +reg [0:0] select_ln20_12_reg_1188_pp0_iter2_reg; +reg [0:0] select_ln20_12_reg_1188_pp0_iter3_reg; +wire [11:0] p_mid1_fu_694_p2; +reg [11:0] p_mid1_reg_1194; +wire [12:0] sub_ln32_fu_730_p2; +reg [12:0] sub_ln32_reg_1199; +wire [6:0] sub_ln32_9_fu_852_p2; +reg [6:0] sub_ln32_9_reg_1209; +wire [63:0] lshr_ln32_fu_862_p2; +reg [63:0] lshr_ln32_reg_1214; +wire [6:0] sub_ln32_12_fu_953_p2; +reg [6:0] sub_ln32_12_reg_1219; +wire [63:0] lshr_ln32_5_fu_963_p2; +reg [63:0] lshr_ln32_5_reg_1224; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg [1:0] ap_phi_mux_ii_phi_fu_190_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_213_p4; +wire [63:0] sext_ln32_fu_768_p1; +wire [63:0] sext_ln33_fu_1005_p1; +wire [16:0] zext_ln19_fu_236_p1; +wire [16:0] empty_95_fu_244_p2; +wire [16:0] j_cast_i_fu_232_p1; +wire [16:0] add_ln22_fu_258_p2; +wire [5:0] empty_fu_240_p1; +wire [0:0] tmp_fu_274_p3; +wire [0:0] icmp_ln24_fu_282_p2; +wire [17:0] ii_cast_i_fu_306_p1; +wire [17:0] empty_96_fu_310_p2; +wire [17:0] zext_ln20_fu_321_p1; +wire [17:0] add_ln22_3_fu_325_p2; +wire [0:0] tmp_33_fu_330_p3; +wire [0:0] icmp_ln24_3_fu_338_p2; +wire [0:0] or_ln23_fu_344_p2; +wire [17:0] ii_cast_i_mid1_fu_398_p1; +wire [17:0] p_mid111_fu_402_p2; +wire [0:0] tmp_34_fu_413_p3; +wire [0:0] xor_ln25_fu_421_p2; +wire [1:0] select_ln19_fu_374_p3; +wire [4:0] select_ln19_15_fu_382_p3; +wire [17:0] zext_ln20_3_fu_455_p1; +wire [4:0] select_ln20_fu_439_p3; +wire [5:0] add_ln20_3_fu_494_p2; +wire [5:0] ii_cast_fu_508_p1; +wire [5:0] p_cast14_i_fu_512_p2; +wire [2:0] zext_ln22_fu_517_p1; +wire [2:0] tmp2_fu_528_p2; +wire [11:0] tmp2_cast_fu_534_p1; +wire [11:0] empty_98_fu_538_p2; +wire [3:0] tmp_s_fu_553_p3; +wire [4:0] zext_ln33_6_fu_560_p1; +wire [4:0] zext_ln33_fu_550_p1; +wire [4:0] sub_ln33_fu_564_p2; +wire [5:0] ii_cast_mid1_fu_574_p1; +wire [5:0] p_cast14_i_mid1_fu_577_p2; +wire [0:0] or_ln23_13_fu_594_p2; +wire [5:0] row_coord_int_mid131_fu_604_p3; +wire [5:0] row_coord_int_fu_521_p3; +wire [11:0] col_coord_int_mid139_fu_612_p3; +wire [11:0] col_coord_int_fu_543_p3; +wire [5:0] sub_ln33_cast_fu_570_p1; +wire [5:0] zext_ln33_7_fu_633_p1; +wire [0:0] tmp_35_fu_645_p3; +wire [0:0] icmp_ln24_4_fu_652_p2; +wire [0:0] or_ln23_14_fu_657_p2; +wire [0:0] select_ln19_18_fu_589_p3; +wire [0:0] select_ln19_19_fu_598_p3; +wire [5:0] select_ln19_17_fu_582_p3; +wire [2:0] zext_ln22_3_fu_642_p1; +wire [2:0] tmp2_mid1_fu_684_p2; +wire [11:0] tmp2_cast_mid1_fu_690_p1; +wire [5:0] select_ln19_20_fu_619_p3; +wire [5:0] row_coord_int_mid1_fu_676_p3; +wire [5:0] select_ln20_13_fu_699_p3; +wire [11:0] tmp_22_fu_706_p3; +wire [8:0] tmp_23_fu_718_p3; +wire [12:0] zext_ln32_fu_714_p1; +wire [12:0] zext_ln32_22_fu_726_p1; +wire [11:0] col_coord_int_mid1_fu_736_p3; +wire [11:0] select_ln20_14_fu_745_p3; +wire [13:0] sext_ln20_fu_742_p1; +wire [13:0] zext_ln32_23_fu_751_p1; +wire [13:0] add_ln32_fu_755_p2; +wire [15:0] tmp_36_fu_761_p3; +wire [5:0] tmp_24_fu_773_p3; +wire [5:0] empty_100_fu_780_p2; +wire [6:0] zext_ln32_24_fu_792_p1; +wire [6:0] zext_ln32_25_fu_796_p1; +wire [0:0] icmp_ln32_fu_786_p2; +wire [6:0] sub_ln32_7_fu_810_p2; +wire [6:0] sub_ln32_8_fu_822_p2; +reg [63:0] tmp_37_fu_800_p4; +wire [6:0] xor_ln32_fu_816_p2; +wire [6:0] select_ln32_fu_828_p3; +wire [6:0] select_ln32_7_fu_844_p3; +wire [63:0] select_ln32_6_fu_836_p3; +wire [63:0] zext_ln32_26_fu_858_p1; +wire [1:0] or_ln329_i_fu_868_p2; +wire [5:0] tmp_25_fu_873_p3; +wire [5:0] empty_101_fu_881_p2; +wire [6:0] zext_ln32_28_fu_893_p1; +wire [6:0] zext_ln32_29_fu_897_p1; +wire [0:0] icmp_ln32_2_fu_887_p2; +wire [6:0] sub_ln32_10_fu_911_p2; +wire [6:0] sub_ln32_11_fu_923_p2; +reg [63:0] tmp_39_fu_901_p4; +wire [6:0] xor_ln32_2_fu_917_p2; +wire [6:0] select_ln32_8_fu_929_p3; +wire [6:0] select_ln32_10_fu_945_p3; +wire [63:0] select_ln32_9_fu_937_p3; +wire [63:0] zext_ln32_30_fu_959_p1; +wire [63:0] zext_ln32_27_fu_969_p1; +wire [63:0] lshr_ln32_4_fu_972_p2; +wire [63:0] and_ln32_fu_978_p2; +wire [15:0] trunc_ln32_3_fu_983_p1; +wire [15:0] in_data_elem_fu_987_p1; +wire [8:0] tmp_38_fu_999_p3; +wire [63:0] zext_ln32_31_fu_1011_p1; +wire [63:0] lshr_ln32_6_fu_1014_p2; +wire [63:0] and_ln32_2_fu_1020_p2; +wire [15:0] trunc_ln32_4_fu_1025_p1; +wire [15:0] in_data_elem_5_fu_1029_p1; +wire ap_CS_fsm_state7; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1092 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ii_reg_186 <= select_ln19_16_reg_1110; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_186 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_356_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten47_reg_175 <= add_ln19_3_fu_300_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten47_reg_175 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_356_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_198 <= select_ln20_15_fu_500_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_198 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1092 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_209 <= select_ln20_11_reg_1135; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_209 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_356_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_reg_221 <= add_ln25_fu_488_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_221 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_356_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln19_reg_1096 <= add_ln19_fu_362_p2; + add_ln20_reg_1130 <= add_ln20_fu_433_p2; + add_ln22_4_reg_1141 <= add_ln22_4_fu_459_p2; + icmp_ln20_reg_1101 <= icmp_ln20_fu_368_p2; + lshr_ln3_reg_1158 <= {{select_ln20_fu_439_p3[3:1]}}; + lshr_ln_reg_1147 <= {{select_ln20_fu_439_p3[3:2]}}; + or_ln19_reg_1123 <= or_ln19_fu_427_p2; + p_mid113_reg_1117 <= p_mid113_fu_407_p2; + trunc_ln32_reg_1152 <= trunc_ln32_fu_474_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1092 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln33_reg_1178 <= add_ln33_fu_636_p2; + or_ln23_15_reg_1183 <= or_ln23_15_fu_663_p2; + select_ln20_12_reg_1188 <= select_ln20_12_fu_669_p3; + sub_ln32_reg_1199[12 : 3] <= sub_ln32_fu_730_p2[12 : 3]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln33_reg_1178_pp0_iter2_reg <= add_ln33_reg_1178; + add_ln33_reg_1178_pp0_iter3_reg <= add_ln33_reg_1178_pp0_iter2_reg; + icmp_ln19_reg_1092_pp0_iter2_reg <= icmp_ln19_reg_1092_pp0_iter1_reg; + icmp_ln19_reg_1092_pp0_iter3_reg <= icmp_ln19_reg_1092_pp0_iter2_reg; + lshr_ln3_reg_1158_pp0_iter2_reg <= lshr_ln3_reg_1158_pp0_iter1_reg; + lshr_ln3_reg_1158_pp0_iter3_reg <= lshr_ln3_reg_1158_pp0_iter2_reg; + select_ln20_12_reg_1188_pp0_iter2_reg <= select_ln20_12_reg_1188; + select_ln20_12_reg_1188_pp0_iter3_reg <= select_ln20_12_reg_1188_pp0_iter2_reg; + trunc_ln32_reg_1152_pp0_iter2_reg <= trunc_ln32_reg_1152_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + empty_97_reg_1080 <= empty_97_fu_315_p2; + icmp_ln19_reg_1092 <= icmp_ln19_fu_356_p2; + icmp_ln19_reg_1092_pp0_iter1_reg <= icmp_ln19_reg_1092; + is_padding_reg_1085 <= is_padding_fu_350_p2; + lshr_ln3_reg_1158_pp0_iter1_reg <= lshr_ln3_reg_1158; + lshr_ln_reg_1147_pp0_iter1_reg <= lshr_ln_reg_1147; + or_ln19_reg_1123_pp0_iter1_reg <= or_ln19_reg_1123; + trunc_ln32_reg_1152_pp0_iter1_reg <= trunc_ln32_reg_1152; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1092_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (select_ln20_12_reg_1188_pp0_iter2_reg == 1'd0))) begin + lshr_ln32_5_reg_1224 <= lshr_ln32_5_fu_963_p2; + lshr_ln32_reg_1214 <= lshr_ln32_fu_862_p2; + sub_ln32_12_reg_1219[6 : 1] <= sub_ln32_12_fu_953_p2[6 : 1]; + sub_ln32_9_reg_1209[6 : 1] <= sub_ln32_9_fu_852_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + or_ln23_11_reg_1065 <= or_ln23_11_fu_288_p2; + p_cast_i_reg_1041 <= p_cast_i_fu_250_p1; + p_cast_reg_1059 <= p_cast_fu_268_p2; + p_mid137_reg_1070 <= p_mid137_fu_294_p2; + sext_ln22_reg_1053 <= sext_ln22_fu_264_p1; + trunc_ln22_reg_1047 <= trunc_ln22_fu_254_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1092 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (or_ln19_reg_1123 == 1'd0))) begin + p_mid1_reg_1194 <= p_mid1_fu_694_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_356_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln19_16_reg_1110 <= select_ln19_16_fu_390_p3; + select_ln20_11_reg_1135 <= select_ln20_11_fu_447_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1092 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (or_ln19_reg_1123 == 1'd1))) begin + select_ln19_21_reg_1173 <= select_ln19_21_fu_626_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_fu_356_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_1092 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_190_p4 = select_ln19_16_reg_1110; + end else begin + ap_phi_mux_ii_phi_fu_190_p4 = ii_reg_186; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_1092 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_213_p4 = select_ln20_11_reg_1135; + end else begin + ap_phi_mux_jj_phi_fu_213_p4 = jj_reg_209; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + ifmap_vec_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_1092_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + ifmap_vec_0_we0 = 1'b1; + end else begin + ifmap_vec_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + ifmap_vec_1_ce0 = 1'b1; + end else begin + ifmap_vec_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_1092_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + ifmap_vec_1_we0 = 1'b1; + end else begin + ifmap_vec_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln19_3_fu_300_p2 = (indvar_flatten47_reg_175 + 7'd1); + +assign add_ln19_fu_362_p2 = (ap_phi_mux_ii_phi_fu_190_p4 + 2'd1); + +assign add_ln20_3_fu_494_p2 = (indvar_flatten_reg_198 + 6'd1); + +assign add_ln20_fu_433_p2 = (select_ln19_fu_374_p3 + 2'd1); + +assign add_ln22_3_fu_325_p2 = ((sext_ln22_reg_1053) + (zext_ln20_fu_321_p1)); + +assign add_ln22_4_fu_459_p2 = ((sext_ln22_reg_1053) + (zext_ln20_3_fu_455_p1)); + +assign add_ln22_fu_258_p2 = ((j_cast_i_fu_232_p1) + (17'd131071)); + +assign add_ln25_fu_488_p2 = (select_ln20_fu_439_p3 + 5'd2); + +assign add_ln32_fu_755_p2 = ((sext_ln20_fu_742_p1) + (zext_ln32_23_fu_751_p1)); + +assign add_ln33_fu_636_p2 = ((sub_ln33_cast_fu_570_p1) + (zext_ln33_7_fu_633_p1)); + +assign and_ln32_2_fu_1020_p2 = (lshr_ln32_6_fu_1014_p2 & lshr_ln32_5_reg_1224); + +assign and_ln32_fu_978_p2 = (lshr_ln32_reg_1214 & lshr_ln32_4_fu_972_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign col_coord_int_fu_543_p3 = ((is_padding_reg_1085[0:0] == 1'b1) ? 12'd0 : empty_98_fu_538_p2); + +assign col_coord_int_mid139_fu_612_p3 = ((or_ln23_13_fu_594_p2[0:0] == 1'b1) ? 12'd0 : p_mid137_reg_1070); + +assign col_coord_int_mid1_fu_736_p3 = ((or_ln23_15_reg_1183[0:0] == 1'b1) ? 12'd0 : p_mid1_reg_1194); + +assign empty_100_fu_780_p2 = (tmp_24_fu_773_p3 | 6'd15); + +assign empty_101_fu_881_p2 = (tmp_25_fu_873_p3 | 6'd15); + +assign empty_95_fu_244_p2 = ((zext_ln19_fu_236_p1) + (17'd131071)); + +assign empty_96_fu_310_p2 = ((p_cast_i_reg_1041) + (ii_cast_i_fu_306_p1)); + +assign empty_97_fu_315_p2 = ((empty_96_fu_310_p2 > 18'd55) ? 1'b1 : 1'b0); + +assign empty_98_fu_538_p2 = ((tmp2_cast_fu_534_p1) + (trunc_ln22_reg_1047)); + +assign empty_fu_240_p1 = i_15[5:0]; + +assign icmp_ln19_fu_356_p2 = ((indvar_flatten47_reg_175 == 7'd72) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_368_p2 = ((indvar_flatten_reg_198 == 6'd24) ? 1'b1 : 1'b0); + +assign icmp_ln24_3_fu_338_p2 = (((add_ln22_3_fu_325_p2) > (18'd55)) ? 1'b1 : 1'b0); + +assign icmp_ln24_4_fu_652_p2 = (((add_ln22_4_reg_1141) > (18'd55)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_282_p2 = (((add_ln22_fu_258_p2) > (17'd55)) ? 1'b1 : 1'b0); + +assign icmp_ln32_2_fu_887_p2 = ((tmp_25_fu_873_p3 > empty_101_fu_881_p2) ? 1'b1 : 1'b0); + +assign icmp_ln32_fu_786_p2 = ((tmp_24_fu_773_p3 > empty_100_fu_780_p2) ? 1'b1 : 1'b0); + +assign ifmap_vec_0_address0 = sext_ln33_fu_1005_p1; + +assign ifmap_vec_0_d0 = ((select_ln20_12_reg_1188_pp0_iter3_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_fu_987_p1); + +assign ifmap_vec_1_address0 = sext_ln33_fu_1005_p1; + +assign ifmap_vec_1_d0 = ((select_ln20_12_reg_1188_pp0_iter3_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_5_fu_1029_p1); + +assign ii_cast_fu_508_p1 = ii_reg_186; + +assign ii_cast_i_fu_306_p1 = ap_phi_mux_ii_phi_fu_190_p4; + +assign ii_cast_i_mid1_fu_398_p1 = add_ln19_fu_362_p2; + +assign ii_cast_mid1_fu_574_p1 = add_ln19_reg_1096; + +assign in_data_address0 = sext_ln32_fu_768_p1; + +assign in_data_elem_5_fu_1029_p1 = trunc_ln32_4_fu_1025_p1; + +assign in_data_elem_fu_987_p1 = trunc_ln32_3_fu_983_p1; + +assign is_padding_fu_350_p2 = (or_ln23_fu_344_p2 | empty_97_fu_315_p2); + +assign j_cast_i_fu_232_p1 = j_15; + +assign lshr_ln32_4_fu_972_p2 = 64'd18446744073709551615 >> zext_ln32_27_fu_969_p1; + +assign lshr_ln32_5_fu_963_p2 = select_ln32_9_fu_937_p3 >> zext_ln32_30_fu_959_p1; + +assign lshr_ln32_6_fu_1014_p2 = 64'd18446744073709551615 >> zext_ln32_31_fu_1011_p1; + +assign lshr_ln32_fu_862_p2 = select_ln32_6_fu_836_p3 >> zext_ln32_26_fu_858_p1; + +assign or_ln19_fu_427_p2 = (xor_ln25_fu_421_p2 | icmp_ln20_fu_368_p2); + +assign or_ln23_11_fu_288_p2 = (tmp_fu_274_p3 | icmp_ln24_fu_282_p2); + +assign or_ln23_13_fu_594_p2 = (p_mid113_reg_1117 | or_ln23_11_reg_1065); + +assign or_ln23_14_fu_657_p2 = (tmp_35_fu_645_p3 | icmp_ln24_4_fu_652_p2); + +assign or_ln23_15_fu_663_p2 = (select_ln19_18_fu_589_p3 | or_ln23_14_fu_657_p2); + +assign or_ln23_fu_344_p2 = (tmp_33_fu_330_p3 | icmp_ln24_3_fu_338_p2); + +assign or_ln329_i_fu_868_p2 = (trunc_ln32_reg_1152_pp0_iter2_reg | 2'd1); + +assign p_cast14_i_fu_512_p2 = (p_cast_reg_1059 + ii_cast_fu_508_p1); + +assign p_cast14_i_mid1_fu_577_p2 = (p_cast_reg_1059 + ii_cast_mid1_fu_574_p1); + +assign p_cast_fu_268_p2 = ((empty_fu_240_p1) + (6'd63)); + +assign p_cast_i_fu_250_p1 = (empty_95_fu_244_p2); + +assign p_mid111_fu_402_p2 = ((p_cast_i_reg_1041) + (ii_cast_i_mid1_fu_398_p1)); + +assign p_mid113_fu_407_p2 = ((p_mid111_fu_402_p2 > 18'd55) ? 1'b1 : 1'b0); + +assign p_mid137_fu_294_p2 = ((trunc_ln22_fu_254_p1) + (12'd4095)); + +assign p_mid1_fu_694_p2 = ((tmp2_cast_mid1_fu_690_p1) + (trunc_ln22_reg_1047)); + +assign row_coord_int_fu_521_p3 = ((is_padding_reg_1085[0:0] == 1'b1) ? 6'd0 : p_cast14_i_fu_512_p2); + +assign row_coord_int_mid131_fu_604_p3 = ((or_ln23_13_fu_594_p2[0:0] == 1'b1) ? 6'd0 : p_cast14_i_mid1_fu_577_p2); + +assign row_coord_int_mid1_fu_676_p3 = ((or_ln23_15_fu_663_p2[0:0] == 1'b1) ? 6'd0 : select_ln19_17_fu_582_p3); + +assign select_ln19_15_fu_382_p3 = ((icmp_ln20_fu_368_p2[0:0] == 1'b1) ? 5'd0 : kk_reg_221); + +assign select_ln19_16_fu_390_p3 = ((icmp_ln20_fu_368_p2[0:0] == 1'b1) ? add_ln19_fu_362_p2 : ap_phi_mux_ii_phi_fu_190_p4); + +assign select_ln19_17_fu_582_p3 = ((icmp_ln20_reg_1101[0:0] == 1'b1) ? p_cast14_i_mid1_fu_577_p2 : p_cast14_i_fu_512_p2); + +assign select_ln19_18_fu_589_p3 = ((icmp_ln20_reg_1101[0:0] == 1'b1) ? p_mid113_reg_1117 : empty_97_reg_1080); + +assign select_ln19_19_fu_598_p3 = ((icmp_ln20_reg_1101[0:0] == 1'b1) ? or_ln23_13_fu_594_p2 : is_padding_reg_1085); + +assign select_ln19_20_fu_619_p3 = ((icmp_ln20_reg_1101[0:0] == 1'b1) ? row_coord_int_mid131_fu_604_p3 : row_coord_int_fu_521_p3); + +assign select_ln19_21_fu_626_p3 = ((icmp_ln20_reg_1101[0:0] == 1'b1) ? col_coord_int_mid139_fu_612_p3 : col_coord_int_fu_543_p3); + +assign select_ln19_fu_374_p3 = ((icmp_ln20_fu_368_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_213_p4); + +assign select_ln20_11_fu_447_p3 = ((or_ln19_fu_427_p2[0:0] == 1'b1) ? select_ln19_fu_374_p3 : add_ln20_fu_433_p2); + +assign select_ln20_12_fu_669_p3 = ((or_ln19_reg_1123[0:0] == 1'b1) ? select_ln19_19_fu_598_p3 : or_ln23_15_fu_663_p2); + +assign select_ln20_13_fu_699_p3 = ((or_ln19_reg_1123[0:0] == 1'b1) ? select_ln19_20_fu_619_p3 : row_coord_int_mid1_fu_676_p3); + +assign select_ln20_14_fu_745_p3 = ((or_ln19_reg_1123_pp0_iter1_reg[0:0] == 1'b1) ? select_ln19_21_reg_1173 : col_coord_int_mid1_fu_736_p3); + +assign select_ln20_15_fu_500_p3 = ((icmp_ln20_fu_368_p2[0:0] == 1'b1) ? 6'd1 : add_ln20_3_fu_494_p2); + +assign select_ln20_fu_439_p3 = ((or_ln19_fu_427_p2[0:0] == 1'b1) ? select_ln19_15_fu_382_p3 : 5'd0); + +assign select_ln32_10_fu_945_p3 = ((icmp_ln32_2_fu_887_p2[0:0] == 1'b1) ? xor_ln32_2_fu_917_p2 : zext_ln32_28_fu_893_p1); + +assign select_ln32_6_fu_836_p3 = ((icmp_ln32_fu_786_p2[0:0] == 1'b1) ? tmp_37_fu_800_p4 : in_data_q0); + +assign select_ln32_7_fu_844_p3 = ((icmp_ln32_fu_786_p2[0:0] == 1'b1) ? xor_ln32_fu_816_p2 : zext_ln32_24_fu_792_p1); + +assign select_ln32_8_fu_929_p3 = ((icmp_ln32_2_fu_887_p2[0:0] == 1'b1) ? sub_ln32_10_fu_911_p2 : sub_ln32_11_fu_923_p2); + +assign select_ln32_9_fu_937_p3 = ((icmp_ln32_2_fu_887_p2[0:0] == 1'b1) ? tmp_39_fu_901_p4 : in_data_q0); + +assign select_ln32_fu_828_p3 = ((icmp_ln32_fu_786_p2[0:0] == 1'b1) ? sub_ln32_7_fu_810_p2 : sub_ln32_8_fu_822_p2); + +assign sext_ln20_fu_742_p1 = (sub_ln32_reg_1199); + +assign sext_ln22_fu_264_p1 = add_ln22_fu_258_p2; + +assign sext_ln32_fu_768_p1 = (tmp_36_fu_761_p3); + +assign sext_ln33_fu_1005_p1 = (tmp_38_fu_999_p3); + +assign sub_ln32_10_fu_911_p2 = (zext_ln32_28_fu_893_p1 - zext_ln32_29_fu_897_p1); + +assign sub_ln32_11_fu_923_p2 = (zext_ln32_29_fu_897_p1 - zext_ln32_28_fu_893_p1); + +assign sub_ln32_12_fu_953_p2 = (7'd63 - select_ln32_8_fu_929_p3); + +assign sub_ln32_7_fu_810_p2 = (zext_ln32_24_fu_792_p1 - zext_ln32_25_fu_796_p1); + +assign sub_ln32_8_fu_822_p2 = (zext_ln32_25_fu_796_p1 - zext_ln32_24_fu_792_p1); + +assign sub_ln32_9_fu_852_p2 = (7'd63 - select_ln32_fu_828_p3); + +assign sub_ln32_fu_730_p2 = (zext_ln32_fu_714_p1 - zext_ln32_22_fu_726_p1); + +assign sub_ln33_cast_fu_570_p1 = (sub_ln33_fu_564_p2); + +assign sub_ln33_fu_564_p2 = (zext_ln33_6_fu_560_p1 - zext_ln33_fu_550_p1); + +assign tmp2_cast_fu_534_p1 = (tmp2_fu_528_p2); + +assign tmp2_cast_mid1_fu_690_p1 = (tmp2_mid1_fu_684_p2); + +assign tmp2_fu_528_p2 = ((zext_ln22_fu_517_p1) + (3'd7)); + +assign tmp2_mid1_fu_684_p2 = ((zext_ln22_3_fu_642_p1) + (3'd7)); + +assign tmp_22_fu_706_p3 = {{select_ln20_13_fu_699_p3}, {6'd0}}; + +assign tmp_23_fu_718_p3 = {{select_ln20_13_fu_699_p3}, {3'd0}}; + +assign tmp_24_fu_773_p3 = {{trunc_ln32_reg_1152_pp0_iter2_reg}, {4'd0}}; + +assign tmp_25_fu_873_p3 = {{or_ln329_i_fu_868_p2}, {4'd0}}; + +assign tmp_33_fu_330_p3 = add_ln22_3_fu_325_p2[32'd17]; + +assign tmp_34_fu_413_p3 = kk_reg_221[32'd4]; + +assign tmp_35_fu_645_p3 = add_ln22_4_reg_1141[32'd17]; + +assign tmp_36_fu_761_p3 = {{add_ln32_fu_755_p2}, {lshr_ln_reg_1147_pp0_iter1_reg}}; + +integer ap_tvar_int_0; + +always @ (in_data_q0) begin + //for (ap_tvar_int_0 = 64 - 1; ap_tvar_int_0 >= 0; ap_tvar_int_0 = ap_tvar_int_0 - 1) begin + for (ap_tvar_int_0 = 0; ap_tvar_int_0 < 64; ap_tvar_int_0 = ap_tvar_int_0 + 1) begin + if (ap_tvar_int_0 > 63 - 0) begin + tmp_37_fu_800_p4[ap_tvar_int_0] = 1'b0; + end else begin + tmp_37_fu_800_p4[ap_tvar_int_0] = in_data_q0[63 - ap_tvar_int_0]; + end + end +end + +assign tmp_38_fu_999_p3 = {{add_ln33_reg_1178_pp0_iter3_reg}, {lshr_ln3_reg_1158_pp0_iter3_reg}}; + +integer ap_tvar_int_1; + +always @ (in_data_q0) begin + //for (ap_tvar_int_1 = 64 - 1; ap_tvar_int_1 >= 0; ap_tvar_int_1 = ap_tvar_int_1 - 1) begin + for (ap_tvar_int_1 = 0; ap_tvar_int_1 < 64; ap_tvar_int_1 = ap_tvar_int_1 + 1) begin + if (ap_tvar_int_1 > 63 - 0) begin + tmp_39_fu_901_p4[ap_tvar_int_1] = 1'b0; + end else begin + tmp_39_fu_901_p4[ap_tvar_int_1] = in_data_q0[63 - ap_tvar_int_1]; + end + end +end + +assign tmp_fu_274_p3 = add_ln22_fu_258_p2[32'd16]; + +assign tmp_s_fu_553_p3 = {{select_ln19_16_reg_1110}, {2'd0}}; + +assign trunc_ln22_fu_254_p1 = j_15[11:0]; + +assign trunc_ln32_3_fu_983_p1 = and_ln32_fu_978_p2[15:0]; + +assign trunc_ln32_4_fu_1025_p1 = and_ln32_2_fu_1020_p2[15:0]; + +assign trunc_ln32_fu_474_p1 = select_ln20_fu_439_p3[1:0]; + +assign xor_ln25_fu_421_p2 = (tmp_34_fu_413_p3 ^ 1'd1); + +assign xor_ln32_2_fu_917_p2 = (zext_ln32_28_fu_893_p1 ^ 7'd63); + +assign xor_ln32_fu_816_p2 = (zext_ln32_24_fu_792_p1 ^ 7'd63); + +assign zext_ln19_fu_236_p1 = i_15; + +assign zext_ln20_3_fu_455_p1 = add_ln20_fu_433_p2; + +assign zext_ln20_fu_321_p1 = ap_phi_mux_jj_phi_fu_213_p4; + +assign zext_ln22_3_fu_642_p1 = add_ln20_reg_1130; + +assign zext_ln22_fu_517_p1 = jj_reg_209; + +assign zext_ln32_22_fu_726_p1 = tmp_23_fu_718_p3; + +assign zext_ln32_23_fu_751_p1 = select_ln20_14_fu_745_p3; + +assign zext_ln32_24_fu_792_p1 = tmp_24_fu_773_p3; + +assign zext_ln32_25_fu_796_p1 = empty_100_fu_780_p2; + +assign zext_ln32_26_fu_858_p1 = select_ln32_7_fu_844_p3; + +assign zext_ln32_27_fu_969_p1 = sub_ln32_9_reg_1209; + +assign zext_ln32_28_fu_893_p1 = tmp_25_fu_873_p3; + +assign zext_ln32_29_fu_897_p1 = empty_101_fu_881_p2; + +assign zext_ln32_30_fu_959_p1 = select_ln32_10_fu_945_p3; + +assign zext_ln32_31_fu_1011_p1 = sub_ln32_12_reg_1219; + +assign zext_ln32_fu_714_p1 = tmp_22_fu_706_p3; + +assign zext_ln33_6_fu_560_p1 = tmp_s_fu_553_p3; + +assign zext_ln33_7_fu_633_p1 = select_ln20_11_reg_1135; + +assign zext_ln33_fu_550_p1 = select_ln19_16_reg_1110; + +always @ (posedge ap_clk) begin + sub_ln32_reg_1199[2:0] <= 3'b000; + sub_ln32_9_reg_1209[0] <= 1'b0; + sub_ln32_12_reg_1219[0] <= 1'b0; +end + +endmodule //td_fused_top_tdf5_readInputs42 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_writeOutputs_aligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_idle, + ap_ready, + i, + j, + k, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1, + max_vals_5_0, + max_vals_5_1, + max_vals_5_2, + max_vals_5_3 +); + +parameter ap_ST_fsm_state1 = 2'd1; +parameter ap_ST_fsm_state2 = 2'd2; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +input [4:0] i; +input [9:0] j; +input [6:0] k; +output [14:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; +input [15:0] max_vals_5_0; +input [15:0] max_vals_5_1; +input [15:0] max_vals_5_2; +input [15:0] max_vals_5_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg out_data_ce1; +reg out_data_we1; + + reg [1:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [9:0] add_ln123_fu_105_p2; +reg [9:0] add_ln123_reg_178; +wire [63:0] zext_ln123_4_fu_132_p1; +wire ap_CS_fsm_state2; +wire [6:0] tmp_s_fu_87_p3; +wire [9:0] tmp_fu_79_p3; +wire [9:0] zext_ln123_fu_95_p1; +wire [9:0] sub_ln123_fu_99_p2; +wire [14:0] tmp_69_cast_fu_111_p3; +wire [14:0] zext_ln123_3_fu_122_p1; +wire [14:0] add_ln123_2_fu_126_p2; +wire [15:0] bitcast_ln123_6_fu_161_p1; +wire [15:0] bitcast_ln123_5_fu_153_p1; +wire [15:0] bitcast_ln123_4_fu_145_p1; +wire [15:0] bitcast_ln123_fu_137_p1; +reg [1:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 2'd1; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + add_ln123_reg_178 <= add_ln123_fu_105_p2; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln123_2_fu_126_p2 = (tmp_69_cast_fu_111_p3 + zext_ln123_3_fu_122_p1); + +assign add_ln123_fu_105_p2 = (sub_ln123_fu_99_p2 + j); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign bitcast_ln123_4_fu_145_p1 = max_vals_5_1; + +assign bitcast_ln123_5_fu_153_p1 = max_vals_5_2; + +assign bitcast_ln123_6_fu_161_p1 = max_vals_5_3; + +assign bitcast_ln123_fu_137_p1 = max_vals_5_0; + +assign out_data_address1 = zext_ln123_4_fu_132_p1; + +assign out_data_d1 = {{{{bitcast_ln123_6_fu_161_p1}, {bitcast_ln123_5_fu_153_p1}}, {bitcast_ln123_4_fu_145_p1}}, {bitcast_ln123_fu_137_p1}}; + +assign sub_ln123_fu_99_p2 = (tmp_fu_79_p3 - zext_ln123_fu_95_p1); + +assign tmp_69_cast_fu_111_p3 = {{add_ln123_reg_178}, {5'd0}}; + +assign tmp_fu_79_p3 = {{i}, {5'd0}}; + +assign tmp_s_fu_87_p3 = {{i}, {2'd0}}; + +assign zext_ln123_3_fu_122_p1 = k; + +assign zext_ln123_4_fu_132_p1 = add_ln123_2_fu_126_p2; + +assign zext_ln123_fu_95_p1 = tmp_s_fu_87_p3; + +endmodule //td_fused_top_tdf5_writeOutputs_aligned +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_19 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [14:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [14:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [12:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [12:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [11:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [11:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [4:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [4:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [14:0] dataflow_in_loop_TOP_LOOP48545_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP48545_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48545_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP48545_U0_in_data_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP48545_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP48545_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48545_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP48545_U0_in_data_we1; +wire [11:0] dataflow_in_loop_TOP_LOOP48545_U0_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP48545_U0_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP48545_U0_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP48545_U0_filter_data_we0; +wire [11:0] dataflow_in_loop_TOP_LOOP48545_U0_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP48545_U0_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP48545_U0_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP48545_U0_filter_data_we1; +wire [4:0] dataflow_in_loop_TOP_LOOP48545_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP48545_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP48545_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP48545_U0_adjustments_we0; +wire [4:0] dataflow_in_loop_TOP_LOOP48545_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP48545_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP48545_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP48545_U0_adjustments_we1; +wire [12:0] dataflow_in_loop_TOP_LOOP48545_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP48545_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48545_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP48545_U0_out_data_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP48545_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP48545_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48545_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP48545_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP48545_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP48545_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP48545_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP48545_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP48545_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP48545_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP48545_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP48545_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP48545_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [14:0] loop_dataflow_input_count; +reg [14:0] loop_dataflow_output_count; +wire [14:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP48545_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP48545_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 15'd0; +#0 loop_dataflow_output_count = 15'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP48545 dataflow_in_loop_TOP_LOOP48545_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP48545_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP48545_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP48545_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP48545_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP48545_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP48545_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP48545_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP48545_U0_in_data_we1), + .filter_data_address0(dataflow_in_loop_TOP_LOOP48545_U0_filter_data_address0), + .filter_data_ce0(dataflow_in_loop_TOP_LOOP48545_U0_filter_data_ce0), + .filter_data_d0(dataflow_in_loop_TOP_LOOP48545_U0_filter_data_d0), + .filter_data_q0(filter_data_q0), + .filter_data_we0(dataflow_in_loop_TOP_LOOP48545_U0_filter_data_we0), + .filter_data_address1(dataflow_in_loop_TOP_LOOP48545_U0_filter_data_address1), + .filter_data_ce1(dataflow_in_loop_TOP_LOOP48545_U0_filter_data_ce1), + .filter_data_d1(dataflow_in_loop_TOP_LOOP48545_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(dataflow_in_loop_TOP_LOOP48545_U0_filter_data_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP48545_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP48545_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP48545_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP48545_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP48545_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP48545_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP48545_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP48545_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP48545_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP48545_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP48545_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP48545_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP48545_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP48545_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP48545_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP48545_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP48545_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP48545_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP48545_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP48545_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP48545_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP48545_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP48545_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 15'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48545_U0_ap_ready == 1'b1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 15'd1); + end else if (((dataflow_in_loop_TOP_LOOP48545_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= 15'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 15'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48545_U0_ap_done == 1'b1) & (dataflow_in_loop_TOP_LOOP48545_U0_ap_continue == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 15'd1); + end else if (((dataflow_in_loop_TOP_LOOP48545_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48545_U0_ap_continue == 1'b1))) begin + loop_dataflow_output_count <= 15'd0; + end + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP48545_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP48545_U0_ap_idle == 1'b1) & (loop_dataflow_output_count == 15'd0) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP48545_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP48545_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP48545_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP48545_U0_adjustments_address0; + +assign adjustments_address1 = 5'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP48545_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP48545_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP48545_U0_ap_ready; + +assign bound_minus_1 = (15'd25088 - 15'd1); + +assign dataflow_in_loop_TOP_LOOP48545_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP48545_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP48545_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP48545_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP48545_U0_start_write = 1'b0; + +assign filter_data_address0 = dataflow_in_loop_TOP_LOOP48545_U0_filter_data_address0; + +assign filter_data_address1 = 12'd0; + +assign filter_data_ce0 = dataflow_in_loop_TOP_LOOP48545_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP48545_U0_in_data_address0; + +assign in_data_address1 = 15'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP48545_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP48545_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 13'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP48545_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP48545_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP48545_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP48545_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP48545_U0_out_data_write; + +endmodule //td_fused_top_tdf6_19 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_pp0_stage0 = 11'd2; +parameter ap_ST_fsm_pp0_stage1 = 11'd4; +parameter ap_ST_fsm_pp0_stage2 = 11'd8; +parameter ap_ST_fsm_pp0_stage3 = 11'd16; +parameter ap_ST_fsm_pp0_stage4 = 11'd32; +parameter ap_ST_fsm_pp0_stage5 = 11'd64; +parameter ap_ST_fsm_pp0_stage6 = 11'd128; +parameter ap_ST_fsm_state15 = 11'd256; +parameter ap_ST_fsm_state16 = 11'd512; +parameter ap_ST_fsm_state17 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [6:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [6:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[6:0] accum_in_0_address0; +reg accum_in_0_ce0; +reg[6:0] accum_in_0_address1; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] x_reg_170; +reg [15:0] psum_7_08_reg_182; +reg [15:0] psum_6_07_reg_194; +reg [15:0] psum_5_06_reg_206; +reg [15:0] psum_4_05_reg_218; +reg [15:0] psum_3_04_reg_230; +reg [15:0] psum_2_03_reg_242; +reg [15:0] psum_1_02_reg_254; +reg [15:0] psum_0_01_reg_266; +wire [0:0] tmp_fu_323_p3; +reg [0:0] tmp_reg_494; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state9_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +reg [0:0] tmp_reg_494_pp0_iter1_reg; +wire [6:0] trunc_ln25_fu_336_p1; +reg [6:0] trunc_ln25_reg_498; +reg [15:0] accum_in_0_load_reg_518; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state10_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_0_load_8_reg_523; +reg [15:0] accum_in_0_load_9_reg_538; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state11_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_0_load_10_reg_543; +reg [15:0] accum_in_0_load_11_reg_558; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state12_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_0_load_12_reg_563; +reg [15:0] accum_in_0_load_13_reg_578; +wire ap_CS_fsm_pp0_stage4; +wire ap_block_state6_pp0_stage4_iter0; +wire ap_block_state13_pp0_stage4_iter1; +wire ap_block_pp0_stage4_11001; +reg [15:0] accum_in_0_load_14_reg_583; +wire [7:0] add_ln25_fu_411_p2; +reg [7:0] add_ln25_reg_588; +wire ap_CS_fsm_pp0_stage6; +wire ap_block_state8_pp0_stage6_iter0; +wire ap_block_pp0_stage6_11001; +wire [15:0] grp_fu_307_p2; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_312_p2; +wire ap_CS_fsm_pp0_stage5; +wire ap_block_state7_pp0_stage5_iter0; +wire ap_block_state14_pp0_stage5_iter1; +wire ap_block_pp0_stage5_11001; +wire [3:0] add_ln33_fu_434_p2; +wire ap_CS_fsm_state16; +wire [0:0] tmp_32_fu_417_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage6_subdone; +wire ap_block_pp0_stage5_subdone; +reg [7:0] ap_phi_mux_x_phi_fu_174_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_186_p4; +wire ap_block_pp0_stage5; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_198_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_210_p4; +wire ap_block_pp0_stage4; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_222_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_234_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_03_phi_fu_246_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_278; +wire ap_CS_fsm_state15; +reg [15:0] ap_phi_mux_phi_ln45_phi_fu_292_p8; +wire [2:0] trunc_ln33_fu_430_p1; +wire [63:0] zext_ln25_fu_331_p1; +wire [63:0] zext_ln29_fu_346_p1; +wire [63:0] zext_ln29_9_fu_356_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln29_10_fu_366_p1; +wire [63:0] zext_ln29_11_fu_376_p1; +wire [63:0] zext_ln29_12_fu_386_p1; +wire [63:0] zext_ln29_13_fu_396_p1; +wire [63:0] zext_ln29_14_fu_406_p1; +wire [63:0] zext_ln33_fu_425_p1; +wire [63:0] zext_ln33_2_fu_446_p1; +reg [15:0] grp_fu_307_p0; +reg [15:0] grp_fu_307_p1; +reg [15:0] grp_fu_312_p0; +reg [15:0] grp_fu_312_p1; +wire [6:0] or_ln29_fu_340_p2; +wire [6:0] or_ln29_7_fu_351_p2; +wire [6:0] or_ln29_8_fu_361_p2; +wire [6:0] or_ln29_9_fu_371_p2; +wire [6:0] or_ln29_10_fu_381_p2; +wire [6:0] or_ln29_11_fu_391_p2; +wire [6:0] or_ln29_12_fu_401_p2; +wire ap_block_pp0_stage6; +wire [2:0] or_ln33_fu_440_p2; +wire [0:0] icmp_ln45_fu_451_p2; +wire [0:0] icmp_ln45_3_fu_465_p2; +wire [15:0] select_ln45_fu_457_p3; +wire [0:0] icmp_ln45_4_fu_479_p2; +wire [15:0] select_ln45_3_fu_471_p3; +wire ap_CS_fsm_state17; +reg [10:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +wire ap_block_pp0_stage1_subdone; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage4_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_570; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U897( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_307_p0), + .din1(grp_fu_307_p1), + .dout(grp_fu_307_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U898( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_312_p0), + .din1(grp_fu_312_p1), + .dout(grp_fu_312_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage5_subdone) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0)) | ((1'b0 == ap_block_pp0_stage6_subdone) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state15)) begin + q_reg_278 <= 4'd0; + end else if (((tmp_32_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + q_reg_278 <= add_ln33_fu_434_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_reg_494 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + x_reg_170 <= add_ln25_reg_588; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_170 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage2_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_10_reg_543 <= accum_in_0_q0; + accum_in_0_load_9_reg_538 <= accum_in_0_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage3_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_11_reg_558 <= accum_in_0_q1; + accum_in_0_load_12_reg_563 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage4_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_13_reg_578 <= accum_in_0_q1; + accum_in_0_load_14_reg_583 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_8_reg_523 <= accum_in_0_q0; + accum_in_0_load_reg_518 <= accum_in_0_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage6_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln25_reg_588 <= add_ln25_fu_411_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage2_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + psum_0_01_reg_266 <= grp_fu_307_p2; + psum_1_02_reg_254 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + psum_2_03_reg_242 <= grp_fu_307_p2; + psum_3_04_reg_230 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage4_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + psum_4_05_reg_218 <= grp_fu_307_p2; + psum_5_06_reg_206 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage5_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + psum_6_07_reg_194 <= grp_fu_307_p2; + psum_7_08_reg_182 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + tmp_reg_494 <= ap_phi_mux_x_phi_fu_174_p4[32'd7]; + tmp_reg_494_pp0_iter1_reg <= tmp_reg_494; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_fu_323_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln25_reg_498 <= trunc_ln25_fu_336_p1; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address0 = zext_ln29_14_fu_406_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address0 = zext_ln29_12_fu_386_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address0 = zext_ln29_10_fu_366_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address0 = zext_ln29_fu_346_p1; + end else begin + accum_in_0_address0 = 'bx; + end + end else begin + accum_in_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address1 = zext_ln29_13_fu_396_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address1 = zext_ln29_11_fu_376_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address1 = zext_ln29_9_fu_356_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address1 = zext_ln25_fu_331_p1; + end else begin + accum_in_0_address1 = 'bx; + end + end else begin + accum_in_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_32_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_32_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_reg_494 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_32_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + if ((trunc_ln33_fu_430_p1 == 3'd0)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_0_01_reg_266; + end else if ((1'b1 == ap_condition_570)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_6_07_reg_194; + end else if ((trunc_ln33_fu_430_p1 == 3'd4)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_4_05_reg_218; + end else if ((trunc_ln33_fu_430_p1 == 3'd2)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_2_03_reg_242; + end else begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (tmp_reg_494 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_x_phi_fu_174_p4 = add_ln25_reg_588; + end else begin + ap_phi_mux_x_phi_fu_174_p4 = x_reg_170; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_307_p0 = ap_phi_mux_psum_6_07_phi_fu_198_p4; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_307_p0 = ap_phi_mux_psum_4_05_phi_fu_222_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_307_p0 = ap_phi_mux_psum_2_03_phi_fu_246_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_307_p0 = grp_fu_307_p2; + end else begin + grp_fu_307_p0 = 'bx; + end + end else begin + grp_fu_307_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_307_p1 = accum_in_0_load_13_reg_578; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_307_p1 = accum_in_0_load_11_reg_558; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_307_p1 = accum_in_0_load_9_reg_538; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_307_p1 = accum_in_0_load_reg_518; + end else begin + grp_fu_307_p1 = 'bx; + end + end else begin + grp_fu_307_p1 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_312_p0 = ap_phi_mux_psum_7_08_phi_fu_186_p4; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_312_p0 = ap_phi_mux_psum_5_06_phi_fu_210_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_312_p0 = ap_phi_mux_psum_3_04_phi_fu_234_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_312_p0 = grp_fu_312_p2; + end else begin + grp_fu_312_p0 = 'bx; + end + end else begin + grp_fu_312_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_312_p1 = accum_in_0_load_14_reg_583; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_312_p1 = accum_in_0_load_12_reg_563; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_312_p1 = accum_in_0_load_10_reg_543; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_312_p1 = accum_in_0_load_8_reg_523; + end else begin + grp_fu_312_p1 = 'bx; + end + end else begin + grp_fu_312_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_494 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_494 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state15; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_pp0_stage4 : begin + if ((1'b0 == ap_block_pp0_stage4_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end + end + ap_ST_fsm_pp0_stage5 : begin + if ((~((1'b0 == ap_block_pp0_stage5_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0)) & (1'b0 == ap_block_pp0_stage5_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end else if (((1'b0 == ap_block_pp0_stage5_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state15; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end + end + ap_ST_fsm_pp0_stage6 : begin + if ((1'b0 == ap_block_pp0_stage6_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + if (((tmp_32_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + ap_NS_fsm = ap_ST_fsm_state16; + end else begin + ap_NS_fsm = ap_ST_fsm_state17; + end + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln33_2_fu_446_p1; + +assign accum_out_address1 = zext_ln33_fu_425_p1; + +assign accum_out_d0 = ((icmp_ln45_4_fu_479_p2[0:0] == 1'b1) ? psum_5_06_reg_206 : select_ln45_3_fu_471_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln45_phi_fu_292_p8; + +assign add_ln25_fu_411_p2 = (x_reg_170 + 8'd8); + +assign add_ln33_fu_434_p2 = (q_reg_278 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state15 = ap_CS_fsm[32'd8]; + +assign ap_CS_fsm_state16 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd10]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage4_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage5_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_570 = (~(trunc_ln33_fu_430_p1 == 3'd0) & ~(trunc_ln33_fu_430_p1 == 3'd4) & ~(trunc_ln33_fu_430_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_03_phi_fu_246_p4 = grp_fu_307_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_234_p4 = grp_fu_312_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_222_p4 = grp_fu_307_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_210_p4 = grp_fu_312_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_198_p4 = grp_fu_307_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_186_p4 = grp_fu_312_p2; + +assign icmp_ln45_3_fu_465_p2 = ((or_ln33_fu_440_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln45_4_fu_479_p2 = ((or_ln33_fu_440_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln45_fu_451_p2 = ((or_ln33_fu_440_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln29_10_fu_381_p2 = (trunc_ln25_reg_498 | 7'd5); + +assign or_ln29_11_fu_391_p2 = (trunc_ln25_reg_498 | 7'd6); + +assign or_ln29_12_fu_401_p2 = (trunc_ln25_reg_498 | 7'd7); + +assign or_ln29_7_fu_351_p2 = (trunc_ln25_reg_498 | 7'd2); + +assign or_ln29_8_fu_361_p2 = (trunc_ln25_reg_498 | 7'd3); + +assign or_ln29_9_fu_371_p2 = (trunc_ln25_reg_498 | 7'd4); + +assign or_ln29_fu_340_p2 = (trunc_ln25_fu_336_p1 | 7'd1); + +assign or_ln33_fu_440_p2 = (trunc_ln33_fu_430_p1 | 3'd1); + +assign select_ln45_3_fu_471_p3 = ((icmp_ln45_3_fu_465_p2[0:0] == 1'b1) ? psum_3_04_reg_230 : select_ln45_fu_457_p3); + +assign select_ln45_fu_457_p3 = ((icmp_ln45_fu_451_p2[0:0] == 1'b1) ? psum_1_02_reg_254 : psum_7_08_reg_182); + +assign tmp_32_fu_417_p3 = q_reg_278[32'd3]; + +assign tmp_fu_323_p3 = ap_phi_mux_x_phi_fu_174_p4[32'd7]; + +assign trunc_ln25_fu_336_p1 = ap_phi_mux_x_phi_fu_174_p4[6:0]; + +assign trunc_ln33_fu_430_p1 = q_reg_278[2:0]; + +assign zext_ln25_fu_331_p1 = ap_phi_mux_x_phi_fu_174_p4; + +assign zext_ln29_10_fu_366_p1 = or_ln29_8_fu_361_p2; + +assign zext_ln29_11_fu_376_p1 = or_ln29_9_fu_371_p2; + +assign zext_ln29_12_fu_386_p1 = or_ln29_10_fu_381_p2; + +assign zext_ln29_13_fu_396_p1 = or_ln29_11_fu_391_p2; + +assign zext_ln29_14_fu_406_p1 = or_ln29_12_fu_401_p2; + +assign zext_ln29_9_fu_356_p1 = or_ln29_7_fu_351_p2; + +assign zext_ln29_fu_346_p1 = or_ln29_fu_340_p2; + +assign zext_ln33_2_fu_446_p1 = or_ln33_fu_440_p2; + +assign zext_ln33_fu_425_p1 = q_reg_278; + +endmodule //td_fused_top_tdf6_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_20, + accum_in_20_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_20; +output accum_in_20_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_20; +reg accum_in_20_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln57_fu_73_p2; +reg [3:0] add_ln57_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln57_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln57_fu_79_p1; +reg [15:0] accum_in_20_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_20_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U901( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_20_preg <= 16'd0; + end else begin + if (((icmp_ln57_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_20_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln57_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln57_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln57_reg_90 <= add_ln57_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_20 = sum_01_reg_55; + end else begin + accum_in_20 = accum_in_20_preg; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_20_ap_vld = 1'b1; + end else begin + accum_in_20_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln57_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln57_fu_79_p1; + +assign add_ln57_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln57_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln57_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf6_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 23'd1; +parameter ap_ST_fsm_state2 = 23'd2; +parameter ap_ST_fsm_state3 = 23'd4; +parameter ap_ST_fsm_state4 = 23'd8; +parameter ap_ST_fsm_state5 = 23'd16; +parameter ap_ST_fsm_state6 = 23'd32; +parameter ap_ST_fsm_state7 = 23'd64; +parameter ap_ST_fsm_state8 = 23'd128; +parameter ap_ST_fsm_state9 = 23'd256; +parameter ap_ST_fsm_state10 = 23'd512; +parameter ap_ST_fsm_state11 = 23'd1024; +parameter ap_ST_fsm_state12 = 23'd2048; +parameter ap_ST_fsm_state13 = 23'd4096; +parameter ap_ST_fsm_state14 = 23'd8192; +parameter ap_ST_fsm_state15 = 23'd16384; +parameter ap_ST_fsm_state16 = 23'd32768; +parameter ap_ST_fsm_state17 = 23'd65536; +parameter ap_ST_fsm_state18 = 23'd131072; +parameter ap_ST_fsm_state19 = 23'd262144; +parameter ap_ST_fsm_state20 = 23'd524288; +parameter ap_ST_fsm_state21 = 23'd1048576; +parameter ap_ST_fsm_state22 = 23'd2097152; +parameter ap_ST_fsm_state23 = 23'd4194304; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_read; +output [4:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [4:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg indices_23_read; + +reg ap_done_reg; + reg [22:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +wire [15:0] trunc_ln220_fu_95_p1; +reg [15:0] trunc_ln220_reg_154; +wire ap_CS_fsm_state2; +reg [15:0] tmp_117_i_i_reg_159; +reg [15:0] tmp_118_i_i_reg_164; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_81_p2; +reg [15:0] sub_i_i_i_reg_179; +wire ap_CS_fsm_state9; +wire ap_CS_fsm_state10; +wire [15:0] grp_fu_86_p2; +reg [15:0] mul_i_i_i_reg_189; +wire ap_CS_fsm_state14; +wire ap_CS_fsm_state15; +wire [15:0] grp_fu_77_p2; +reg [15:0] add_i_i_i_reg_199; +wire ap_CS_fsm_state22; +wire [63:0] zext_ln220_fu_90_p1; +reg ap_block_state1; +wire [15:0] grp_fu_77_p1; +wire [15:0] grp_fu_81_p1; +wire [15:0] grp_fu_86_p1; +wire ap_CS_fsm_state23; +wire [15:0] bitcast_ln648_fu_131_p1; +wire [0:0] tmp_fu_134_p3; +reg [22:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 23'd1; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U905( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(mul_i_i_i_reg_189), + .din1(grp_fu_77_p1), + .dout(grp_fu_77_p2) +); + +td_fused_top_hsub_16ns_16ns_16_7_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 7 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_7_full_dsp_1_U906( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sums_read), + .din1(grp_fu_81_p1), + .dout(grp_fu_81_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U907( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_179), + .din1(grp_fu_86_p1), + .dout(grp_fu_86_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state23)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state22)) begin + add_i_i_i_reg_199 <= grp_fu_77_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + mul_i_i_i_reg_189 <= grp_fu_86_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + sub_i_i_i_reg_179 <= grp_fu_81_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + tmp_117_i_i_reg_159 <= {{adjustments_q0[31:16]}}; + tmp_118_i_i_reg_164 <= {{adjustments_q0[47:32]}}; + trunc_ln220_reg_154 <= trunc_ln220_fu_95_p1; + end +end + +always @ (*) begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state23)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state23)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state18; + end + ap_ST_fsm_state18 : begin + ap_NS_fsm = ap_ST_fsm_state19; + end + ap_ST_fsm_state19 : begin + ap_NS_fsm = ap_ST_fsm_state20; + end + ap_ST_fsm_state20 : begin + ap_NS_fsm = ap_ST_fsm_state21; + end + ap_ST_fsm_state21 : begin + ap_NS_fsm = ap_ST_fsm_state22; + end + ap_ST_fsm_state22 : begin + ap_NS_fsm = ap_ST_fsm_state23; + end + ap_ST_fsm_state23 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign adjustments_address0 = zext_ln220_fu_90_p1; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state14 = ap_CS_fsm[32'd13]; + +assign ap_CS_fsm_state15 = ap_CS_fsm[32'd14]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state22 = ap_CS_fsm[32'd21]; + +assign ap_CS_fsm_state23 = ap_CS_fsm[32'd22]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_return = ((tmp_fu_134_p3[0:0] == 1'b1) ? 16'd0 : add_i_i_i_reg_199); + +assign bitcast_ln648_fu_131_p1 = add_i_i_i_reg_199; + +assign grp_fu_77_p1 = tmp_118_i_i_reg_164; + +assign grp_fu_81_p1 = trunc_ln220_reg_154; + +assign grp_fu_86_p1 = tmp_117_i_i_reg_159; + +assign tmp_fu_134_p3 = bitcast_ln648_fu_131_p1[32'd15]; + +assign trunc_ln220_fu_95_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_90_p1 = indices_23_dout; + +endmodule //td_fused_top_tdf6_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_q0, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [6:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +input [15:0] ifmap_vec_0_0_q0; +output [6:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +input [15:0] weight_vecs_0_0_0_q0; +output [6:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_0_0_ce0; +reg weight_vecs_0_0_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] ic_0_0_reg_69; +wire [7:0] add_ln149_fu_84_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln149_fu_90_p2; +reg [0:0] icmp_ln149_reg_107; +reg [0:0] icmp_ln149_reg_107_pp0_iter1_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter2_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter3_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter4_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter5_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter6_reg; +wire [63:0] idxprom17_0_0_fu_96_p1; +reg [63:0] idxprom17_0_0_reg_111; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter1_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter2_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter3_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter4_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter5_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter6_reg; +reg [15:0] ifmap_vec_0_0_load_reg_126; +reg [15:0] weight_vecs_0_0_0_load_reg_131; +wire [15:0] grp_fu_80_p2; +reg [15:0] mul_reg_136; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +wire ap_block_pp0_stage0; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U893( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_0_load_reg_126), + .din1(weight_vecs_0_0_0_load_reg_131), + .dout(grp_fu_80_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_fu_90_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_0_0_reg_69 <= add_ln149_fu_84_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_0_0_reg_69 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln149_reg_107 <= icmp_ln149_fu_90_p2; + icmp_ln149_reg_107_pp0_iter1_reg <= icmp_ln149_reg_107; + idxprom17_0_0_reg_111_pp0_iter1_reg[7 : 0] <= idxprom17_0_0_reg_111[7 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln149_reg_107_pp0_iter2_reg <= icmp_ln149_reg_107_pp0_iter1_reg; + icmp_ln149_reg_107_pp0_iter3_reg <= icmp_ln149_reg_107_pp0_iter2_reg; + icmp_ln149_reg_107_pp0_iter4_reg <= icmp_ln149_reg_107_pp0_iter3_reg; + icmp_ln149_reg_107_pp0_iter5_reg <= icmp_ln149_reg_107_pp0_iter4_reg; + icmp_ln149_reg_107_pp0_iter6_reg <= icmp_ln149_reg_107_pp0_iter5_reg; + idxprom17_0_0_reg_111_pp0_iter2_reg[7 : 0] <= idxprom17_0_0_reg_111_pp0_iter1_reg[7 : 0]; + idxprom17_0_0_reg_111_pp0_iter3_reg[7 : 0] <= idxprom17_0_0_reg_111_pp0_iter2_reg[7 : 0]; + idxprom17_0_0_reg_111_pp0_iter4_reg[7 : 0] <= idxprom17_0_0_reg_111_pp0_iter3_reg[7 : 0]; + idxprom17_0_0_reg_111_pp0_iter5_reg[7 : 0] <= idxprom17_0_0_reg_111_pp0_iter4_reg[7 : 0]; + idxprom17_0_0_reg_111_pp0_iter6_reg[7 : 0] <= idxprom17_0_0_reg_111_pp0_iter5_reg[7 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_fu_90_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + idxprom17_0_0_reg_111[7 : 0] <= idxprom17_0_0_fu_96_p1[7 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_reg_107 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_load_reg_126 <= ifmap_vec_0_0_q0; + weight_vecs_0_0_0_load_reg_131 <= weight_vecs_0_0_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_reg_107_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_reg_136 <= grp_fu_80_p2; + end +end + +always @ (*) begin + if ((icmp_ln149_fu_90_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln149_reg_107_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln149_fu_90_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln149_fu_90_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln149_fu_84_p2 = (ic_0_0_reg_69 + 8'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign icmp_ln149_fu_90_p2 = ((ic_0_0_reg_69 == 8'd128) ? 1'b1 : 1'b0); + +assign idxprom17_0_0_fu_96_p1 = ic_0_0_reg_69; + +assign ifmap_vec_0_0_address0 = idxprom17_0_0_fu_96_p1; + +assign products_0_address0 = idxprom17_0_0_reg_111_pp0_iter6_reg; + +assign products_0_d0 = mul_reg_136; + +assign weight_vecs_0_0_0_address0 = idxprom17_0_0_fu_96_p1; + +always @ (posedge ap_clk) begin + idxprom17_0_0_reg_111[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter1_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter2_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter3_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter4_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter5_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter6_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf6_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf6_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 12; +parameter MEM_SIZE = 4096; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf6_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd4096; +parameter AddressWidth = 32'd12; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf6_filters_ram td_fused_top_tdf6_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + indices_2_out_din, + indices_2_out_full_n, + indices_2_out_write, + indices_2_out1_din, + indices_2_out1_full_n, + indices_2_out1_write +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [4:0] indices_2_out_din; +input indices_2_out_full_n; +output indices_2_out_write; +output [4:0] indices_2_out1_din; +input indices_2_out1_full_n; +output indices_2_out1_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg indices_0_write; +reg indices_1_write; +reg indices_2_out_write; +reg indices_2_out1_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [15:0] i_1; +reg [15:0] j_1; +reg [15:0] k_1; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg indices_2_out_blk_n; +reg indices_2_out1_blk_n; +reg [0:0] ap_phi_mux_j_17_flag_0_i_phi_fu_77_p6; +reg ap_block_state1; +wire [0:0] icmp_ln78_fu_141_p2; +wire [0:0] icmp_ln81_fu_154_p2; +reg [15:0] ap_phi_mux_j_17_new_0_i_phi_fu_91_p6; +wire [15:0] add_ln80_fu_147_p2; +reg [15:0] ap_phi_mux_k_17_new_0_i_phi_fu_104_p6; +wire [15:0] add_ln77_fu_134_p2; +wire [15:0] select_ln84_fu_172_p3; +wire [4:0] trunc_ln76_fu_128_p1; +wire [15:0] add_ln83_fu_160_p2; +wire [0:0] icmp_ln84_fu_166_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_1 = 16'd0; +#0 j_1 = 16'd0; +#0 k_1 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_1 <= select_ln84_fu_172_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_17_flag_0_i_phi_fu_77_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j_1 <= ap_phi_mux_j_17_new_0_i_phi_fu_91_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k_1 <= ap_phi_mux_k_17_new_0_i_phi_fu_104_p6; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_17_flag_0_i_phi_fu_77_p6 = 1'd0; + end else if ((((icmp_ln81_fu_154_p2 == 1'd0) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_17_flag_0_i_phi_fu_77_p6 = 1'd1; + end else begin + ap_phi_mux_j_17_flag_0_i_phi_fu_77_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln81_fu_154_p2 == 1'd0)) begin + ap_phi_mux_j_17_new_0_i_phi_fu_91_p6 = add_ln80_fu_147_p2; + end else if ((icmp_ln81_fu_154_p2 == 1'd1)) begin + ap_phi_mux_j_17_new_0_i_phi_fu_91_p6 = 16'd0; + end else begin + ap_phi_mux_j_17_new_0_i_phi_fu_91_p6 = 'bx; + end + end else begin + ap_phi_mux_j_17_new_0_i_phi_fu_91_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_17_new_0_i_phi_fu_104_p6 = add_ln77_fu_134_p2; + end else if ((((icmp_ln81_fu_154_p2 == 1'd0) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_17_new_0_i_phi_fu_104_p6 = 16'd0; + end else begin + ap_phi_mux_k_17_new_0_i_phi_fu_104_p6 = 'bx; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_blk_n = indices_2_out1_full_n; + end else begin + indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_write = 1'b1; + end else begin + indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_blk_n = indices_2_out_full_n; + end else begin + indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_write = 1'b1; + end else begin + indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln77_fu_134_p2 = (k_1 + 16'd1); + +assign add_ln80_fu_147_p2 = (j_1 + 16'd1); + +assign add_ln83_fu_160_p2 = (i_1 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign icmp_ln78_fu_141_p2 = ((add_ln77_fu_134_p2 == 16'd32) ? 1'b1 : 1'b0); + +assign icmp_ln81_fu_154_p2 = ((add_ln80_fu_147_p2 == 16'd28) ? 1'b1 : 1'b0); + +assign icmp_ln84_fu_166_p2 = ((add_ln83_fu_160_p2 == 16'd28) ? 1'b1 : 1'b0); + +assign indices_0_din = i_1; + +assign indices_1_din = j_1; + +assign indices_2_out1_din = trunc_ln76_fu_128_p1; + +assign indices_2_out_din = trunc_ln76_fu_128_p1; + +assign select_ln84_fu_172_p3 = ((icmp_ln84_fu_166_p2[0:0] == 1'b1) ? 16'd0 : add_ln83_fu_160_p2); + +assign start_out = real_start; + +assign trunc_ln76_fu_128_p1 = k_1[4:0]; + +endmodule //td_fused_top_tdf6_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_readFilters47 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_we0, + weight_vecs_0_0_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state4 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [11:0] filter_data_address0; +output filter_data_ce0; +input [15:0] filter_data_q0; +input [4:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [6:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +output weight_vecs_0_0_0_we0; +output [15:0] weight_vecs_0_0_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg indices_23_read; +reg weight_vecs_0_0_0_ce0; +reg weight_vecs_0_0_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [7:0] kk_0_0_i_i_reg_93; +wire [11:0] tmp_fu_105_p3; +reg [11:0] tmp_reg_144; +wire [7:0] add_ln49_fu_113_p2; +reg [7:0] add_ln49_reg_149; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln49_fu_119_p2; +reg [0:0] icmp_ln49_reg_154; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg [7:0] ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln55_14_fu_134_p1; +wire [63:0] idxprom16_0_0_i_i_fu_139_p1; +wire [11:0] zext_ln55_fu_125_p1; +wire [11:0] add_ln55_fu_129_p2; +wire ap_CS_fsm_state4; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state4)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_0_0_i_i_reg_93 <= add_ln49_reg_149; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_0_0_i_i_reg_93 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln49_reg_149 <= add_ln49_fu_113_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln49_reg_154 <= icmp_ln49_fu_119_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + tmp_reg_144[11 : 7] <= tmp_fu_105_p3[11 : 7]; + end +end + +always @ (*) begin + if ((icmp_ln49_fu_119_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 = add_ln49_reg_149; + end else begin + ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 = kk_0_0_i_i_reg_93; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((icmp_ln49_fu_119_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((icmp_ln49_fu_119_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln49_fu_113_p2 = (ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 + 8'd1); + +assign add_ln55_fu_129_p2 = (tmp_reg_144 + zext_ln55_fu_125_p1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_address0 = zext_ln55_14_fu_134_p1; + +assign icmp_ln49_fu_119_p2 = ((ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 == 8'd128) ? 1'b1 : 1'b0); + +assign idxprom16_0_0_i_i_fu_139_p1 = kk_0_0_i_i_reg_93; + +assign tmp_fu_105_p3 = {{indices_23_dout}, {7'd0}}; + +assign weight_vecs_0_0_0_address0 = idxprom16_0_0_i_i_fu_139_p1; + +assign weight_vecs_0_0_0_d0 = filter_data_q0; + +assign zext_ln55_14_fu_134_p1 = add_ln55_fu_129_p2; + +assign zext_ln55_fu_125_p1 = ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4; + +always @ (posedge ap_clk) begin + tmp_reg_144[6:0] <= 7'b0000000; +end + +endmodule //td_fused_top_tdf6_readFilters47 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_readInputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_we0, + ifmap_vec_0_0_d0, + ifmap_vec_0_0_address1, + ifmap_vec_0_0_ce1, + ifmap_vec_0_0_we1, + ifmap_vec_0_0_d1, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 5'd1; +parameter ap_ST_fsm_state2 = 5'd2; +parameter ap_ST_fsm_pp0_stage0 = 5'd4; +parameter ap_ST_fsm_pp0_stage1 = 5'd8; +parameter ap_ST_fsm_state7 = 5'd16; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [14:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [6:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +output ifmap_vec_0_0_we0; +output [15:0] ifmap_vec_0_0_d0; +output [6:0] ifmap_vec_0_0_address1; +output ifmap_vec_0_0_ce1; +output ifmap_vec_0_0_we1; +output [15:0] ifmap_vec_0_0_d1; +output [4:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [9:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg[6:0] ifmap_vec_0_0_address0; +reg ifmap_vec_0_0_ce0; +reg ifmap_vec_0_0_we0; +reg[15:0] ifmap_vec_0_0_d0; +reg[6:0] ifmap_vec_0_0_address1; +reg ifmap_vec_0_0_ce1; +reg ifmap_vec_0_0_we1; +reg[15:0] ifmap_vec_0_0_d1; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [4:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [7:0] kk_0_i_i_reg_180; +wire [4:0] trunc_ln135_fu_192_p1; +reg [4:0] trunc_ln135_reg_432; +reg [15:0] col_coord_reg_437; +wire [0:0] is_padding_fu_214_p2; +reg [0:0] is_padding_reg_442; +wire [11:0] add_ln32_fu_274_p2; +reg [11:0] add_ln32_reg_452; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln25_fu_280_p2; +reg [0:0] icmp_ln25_reg_457; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state5_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln25_reg_457_pp0_iter1_reg; +wire [7:0] add_ln25_fu_308_p2; +reg [7:0] add_ln25_reg_466; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state4_pp0_stage1_iter0; +wire ap_block_state6_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +wire [15:0] select_ln33_fu_322_p3; +reg [15:0] select_ln33_reg_471; +wire [15:0] select_ln33_8_fu_343_p3; +reg [15:0] select_ln33_8_reg_476; +wire [15:0] select_ln33_9_fu_364_p3; +reg [15:0] select_ln33_9_reg_481; +wire [15:0] select_ln33_10_fu_385_p3; +reg [15:0] select_ln33_10_reg_486; +wire [6:0] empty_93_fu_392_p1; +reg [6:0] empty_93_reg_491; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state3; +reg ap_enable_reg_pp0_iter1; +wire ap_block_pp0_stage1_subdone; +reg [7:0] ap_phi_mux_kk_0_i_i_phi_fu_184_p4; +wire ap_block_pp0_stage0; +wire [63:0] sext_ln32_fu_303_p1; +wire [63:0] zext_ln32_fu_396_p1; +wire [63:0] zext_ln32_8_fu_407_p1; +wire [63:0] zext_ln32_9_fu_417_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln32_10_fu_427_p1; +reg ap_block_state1; +wire [0:0] cmp7_i_i_fu_202_p2; +wire [0:0] icmp_ln24_fu_208_p2; +wire [4:0] empty_91_fu_220_p1; +wire [4:0] row_coord_int_fu_223_p3; +wire [9:0] tmp_fu_236_p3; +wire [6:0] tmp_s_fu_248_p3; +wire [10:0] zext_ln32_19_fu_244_p1; +wire [10:0] zext_ln32_20_fu_256_p1; +wire [10:0] sub_ln32_fu_260_p2; +wire [4:0] col_coord_int_fu_229_p3; +wire [11:0] sub_ln32_cast_fu_266_p1; +wire [11:0] zext_ln32_21_fu_270_p1; +wire [4:0] lshr_ln_fu_286_p4; +wire [16:0] tmp_31_fu_296_p3; +wire [15:0] trunc_ln32_fu_314_p1; +wire [15:0] bitcast_ln32_fu_318_p1; +wire [15:0] tmp_114_i_i_fu_329_p4; +wire [15:0] bitcast_ln32_4_fu_339_p1; +wire [15:0] tmp_115_i_i_fu_350_p4; +wire [15:0] bitcast_ln32_5_fu_360_p1; +wire [15:0] tmp_116_i_i_fu_371_p4; +wire [15:0] bitcast_ln32_6_fu_381_p1; +wire [6:0] or_ln25_fu_401_p2; +wire [6:0] or_ln25_3_fu_412_p2; +wire [6:0] or_ln25_4_fu_422_p2; +wire ap_CS_fsm_state7; +reg [4:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 5'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_i_i_reg_180 <= add_ln25_reg_466; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + kk_0_i_i_reg_180 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln25_reg_466 <= add_ln25_fu_308_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln32_reg_452 <= add_ln32_fu_274_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + col_coord_reg_437 <= indices_12_dout; + is_padding_reg_442 <= is_padding_fu_214_p2; + trunc_ln135_reg_432 <= trunc_ln135_fu_192_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + empty_93_reg_491 <= empty_93_fu_392_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln25_reg_457 <= icmp_ln25_fu_280_p2; + icmp_ln25_reg_457_pp0_iter1_reg <= icmp_ln25_reg_457; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + select_ln33_10_reg_486 <= select_ln33_10_fu_385_p3; + select_ln33_8_reg_476 <= select_ln33_8_fu_343_p3; + select_ln33_9_reg_481 <= select_ln33_9_fu_364_p3; + select_ln33_reg_471 <= select_ln33_fu_322_p3; + end +end + +always @ (*) begin + if ((icmp_ln25_fu_280_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_i_i_phi_fu_184_p4 = add_ln25_reg_466; + end else begin + ap_phi_mux_kk_0_i_i_phi_fu_184_p4 = kk_0_i_i_reg_180; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter1 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_0_0_address0 = zext_ln32_10_fu_427_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_address0 = zext_ln32_8_fu_407_p1; + end else begin + ifmap_vec_0_0_address0 = 'bx; + end + end else begin + ifmap_vec_0_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter1 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_0_0_address1 = zext_ln32_9_fu_417_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_address1 = zext_ln32_fu_396_p1; + end else begin + ifmap_vec_0_0_address1 = 'bx; + end + end else begin + ifmap_vec_0_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_ce1 = 1'b1; + end else begin + ifmap_vec_0_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter1 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_0_0_d0 = select_ln33_10_reg_486; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_d0 = select_ln33_8_reg_476; + end else begin + ifmap_vec_0_0_d0 = 'bx; + end + end else begin + ifmap_vec_0_0_d0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter1 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_0_0_d1 = select_ln33_9_reg_481; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_d1 = select_ln33_reg_471; + end else begin + ifmap_vec_0_0_d1 = 'bx; + end + end else begin + ifmap_vec_0_0_d1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((icmp_ln25_reg_457_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_we0 = 1'b1; + end else begin + ifmap_vec_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((icmp_ln25_reg_457_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_we1 = 1'b1; + end else begin + ifmap_vec_0_0_we1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln25_fu_280_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln25_fu_280_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln25_fu_308_p2 = (kk_0_i_i_reg_180 + 8'd4); + +assign add_ln32_fu_274_p2 = ((sub_ln32_cast_fu_266_p1) + (zext_ln32_21_fu_270_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd4]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln32_4_fu_339_p1 = tmp_114_i_i_fu_329_p4; + +assign bitcast_ln32_5_fu_360_p1 = tmp_115_i_i_fu_350_p4; + +assign bitcast_ln32_6_fu_381_p1 = tmp_116_i_i_fu_371_p4; + +assign bitcast_ln32_fu_318_p1 = trunc_ln32_fu_314_p1; + +assign cmp7_i_i_fu_202_p2 = ((indices_01_dout > 16'd27) ? 1'b1 : 1'b0); + +assign col_coord_int_fu_229_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 5'd0 : empty_91_fu_220_p1); + +assign empty_91_fu_220_p1 = col_coord_reg_437[4:0]; + +assign empty_93_fu_392_p1 = kk_0_i_i_reg_180[6:0]; + +assign icmp_ln24_fu_208_p2 = ((indices_12_dout > 16'd27) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_280_p2 = ((ap_phi_mux_kk_0_i_i_phi_fu_184_p4 == 8'd128) ? 1'b1 : 1'b0); + +assign in_data_address0 = sext_ln32_fu_303_p1; + +assign indices_01_out_din = indices_01_dout[4:0]; + +assign indices_12_out_din = indices_12_dout[9:0]; + +assign is_padding_fu_214_p2 = (icmp_ln24_fu_208_p2 | cmp7_i_i_fu_202_p2); + +assign lshr_ln_fu_286_p4 = {{ap_phi_mux_kk_0_i_i_phi_fu_184_p4[6:2]}}; + +assign or_ln25_3_fu_412_p2 = (empty_93_reg_491 | 7'd2); + +assign or_ln25_4_fu_422_p2 = (empty_93_reg_491 | 7'd3); + +assign or_ln25_fu_401_p2 = (empty_93_fu_392_p1 | 7'd1); + +assign row_coord_int_fu_223_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 5'd0 : trunc_ln135_reg_432); + +assign select_ln33_10_fu_385_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_6_fu_381_p1); + +assign select_ln33_8_fu_343_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_4_fu_339_p1); + +assign select_ln33_9_fu_364_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_5_fu_360_p1); + +assign select_ln33_fu_322_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_fu_318_p1); + +assign sext_ln32_fu_303_p1 = (tmp_31_fu_296_p3); + +assign sub_ln32_cast_fu_266_p1 = (sub_ln32_fu_260_p2); + +assign sub_ln32_fu_260_p2 = (zext_ln32_19_fu_244_p1 - zext_ln32_20_fu_256_p1); + +assign tmp_114_i_i_fu_329_p4 = {{in_data_q0[31:16]}}; + +assign tmp_115_i_i_fu_350_p4 = {{in_data_q0[47:32]}}; + +assign tmp_116_i_i_fu_371_p4 = {{in_data_q0[63:48]}}; + +assign tmp_31_fu_296_p3 = {{add_ln32_reg_452}, {lshr_ln_fu_286_p4}}; + +assign tmp_fu_236_p3 = {{row_coord_int_fu_223_p3}, {5'd0}}; + +assign tmp_s_fu_248_p3 = {{row_coord_int_fu_223_p3}, {2'd0}}; + +assign trunc_ln135_fu_192_p1 = indices_01_dout[4:0]; + +assign trunc_ln32_fu_314_p1 = in_data_q0[15:0]; + +assign zext_ln32_10_fu_427_p1 = or_ln25_4_fu_422_p2; + +assign zext_ln32_19_fu_244_p1 = tmp_fu_236_p3; + +assign zext_ln32_20_fu_256_p1 = tmp_s_fu_248_p3; + +assign zext_ln32_21_fu_270_p1 = col_coord_int_fu_229_p3; + +assign zext_ln32_8_fu_407_p1 = or_ln25_fu_401_p2; + +assign zext_ln32_9_fu_417_p1 = or_ln25_3_fu_412_p2; + +assign zext_ln32_fu_396_p1 = kk_0_i_i_reg_180; + +endmodule //td_fused_top_tdf6_readInputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_writeOutputs_unaligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + p_read, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 2'd1; +parameter ap_ST_fsm_state2 = 2'd2; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [4:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [9:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [15:0] p_read; +output [12:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg out_data_ce1; +reg out_data_we1; + +reg ap_done_reg; + reg [1:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] outputCount_1; +reg [15:0] outputChanIdx_1; +reg [15:0] outputRow_5_0; +reg [15:0] outputRow_5_1; +reg [15:0] outputRow_5_2; +reg [15:0] outputRow_5_3; +reg indices_01_blk_n; +reg indices_12_blk_n; +wire [12:0] tmp_62_cast_fu_153_p3; +reg [12:0] tmp_62_cast_reg_304; +wire [15:0] add_ln87_fu_193_p2; +wire [0:0] icmp_ln88_fu_199_p2; +reg [0:0] icmp_ln88_reg_317; +reg [15:0] ap_phi_mux_empty_phi_fu_114_p4; +reg [15:0] empty_reg_111; +reg ap_block_state1; +wire ap_CS_fsm_state2; +wire [63:0] zext_ln94_4_fu_226_p1; +wire [15:0] select_ln97_fu_284_p3; +wire [1:0] trunc_ln86_fu_165_p1; +wire [6:0] tmp_s_fu_129_p3; +wire [9:0] tmp_fu_121_p3; +wire [9:0] zext_ln94_fu_137_p1; +wire [9:0] sub_ln94_fu_141_p2; +wire [9:0] add_ln94_fu_147_p2; +wire [4:0] trunc_ln94_fu_213_p1; +wire [12:0] zext_ln94_3_fu_217_p1; +wire [12:0] add_ln94_2_fu_221_p2; +wire [15:0] bitcast_ln94_6_fu_255_p1; +wire [15:0] bitcast_ln94_5_fu_247_p1; +wire [15:0] bitcast_ln94_4_fu_239_p1; +wire [15:0] bitcast_ln94_fu_231_p1; +wire [15:0] add_ln96_fu_272_p2; +wire [0:0] icmp_ln97_fu_278_p2; +reg [1:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 2'd1; +#0 outputCount_1 = 16'd0; +#0 outputChanIdx_1 = 16'd0; +#0 outputRow_5_0 = 16'd0; +#0 outputRow_5_1 = 16'd0; +#0 outputRow_5_2 = 16'd0; +#0 outputRow_5_3 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_reg_317 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + empty_reg_111 <= 16'd0; + end else if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln88_fu_199_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + empty_reg_111 <= add_ln87_fu_193_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + icmp_ln88_reg_317 <= icmp_ln88_fu_199_p2; + tmp_62_cast_reg_304[12 : 3] <= tmp_62_cast_fu_153_p3[12 : 3]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_reg_317 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + outputChanIdx_1 <= select_ln97_fu_284_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + outputCount_1 <= ap_phi_mux_empty_phi_fu_114_p4; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (trunc_ln86_fu_165_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_5_0 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (trunc_ln86_fu_165_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_5_1 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (trunc_ln86_fu_165_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_5_2 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (trunc_ln86_fu_165_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_5_3 <= p_read; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_reg_317 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_phi_mux_empty_phi_fu_114_p4 = 16'd0; + end else begin + ap_phi_mux_empty_phi_fu_114_p4 = empty_reg_111; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_reg_317 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln87_fu_193_p2 = (outputCount_1 + 16'd1); + +assign add_ln94_2_fu_221_p2 = (tmp_62_cast_reg_304 + zext_ln94_3_fu_217_p1); + +assign add_ln94_fu_147_p2 = (sub_ln94_fu_141_p2 + indices_12_dout); + +assign add_ln96_fu_272_p2 = (outputChanIdx_1 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign bitcast_ln94_4_fu_239_p1 = outputRow_5_1; + +assign bitcast_ln94_5_fu_247_p1 = outputRow_5_2; + +assign bitcast_ln94_6_fu_255_p1 = outputRow_5_3; + +assign bitcast_ln94_fu_231_p1 = outputRow_5_0; + +assign icmp_ln88_fu_199_p2 = ((add_ln87_fu_193_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign icmp_ln97_fu_278_p2 = ((add_ln96_fu_272_p2 == 16'd8) ? 1'b1 : 1'b0); + +assign out_data_address1 = zext_ln94_4_fu_226_p1; + +assign out_data_d1 = {{{{bitcast_ln94_6_fu_255_p1}, {bitcast_ln94_5_fu_247_p1}}, {bitcast_ln94_4_fu_239_p1}}, {bitcast_ln94_fu_231_p1}}; + +assign select_ln97_fu_284_p3 = ((icmp_ln97_fu_278_p2[0:0] == 1'b1) ? 16'd0 : add_ln96_fu_272_p2); + +assign sub_ln94_fu_141_p2 = (tmp_fu_121_p3 - zext_ln94_fu_137_p1); + +assign tmp_62_cast_fu_153_p3 = {{add_ln94_fu_147_p2}, {3'd0}}; + +assign tmp_fu_121_p3 = {{indices_01_dout}, {5'd0}}; + +assign tmp_s_fu_129_p3 = {{indices_01_dout}, {2'd0}}; + +assign trunc_ln86_fu_165_p1 = outputCount_1[1:0]; + +assign trunc_ln94_fu_213_p1 = outputChanIdx_1[4:0]; + +assign zext_ln94_3_fu_217_p1 = trunc_ln94_fu_213_p1; + +assign zext_ln94_4_fu_226_p1 = add_ln94_2_fu_221_p2; + +assign zext_ln94_fu_137_p1 = tmp_s_fu_129_p3; + +always @ (posedge ap_clk) begin + tmp_62_cast_reg_304[2:0] <= 3'b000; +end + +endmodule //td_fused_top_tdf6_writeOutputs_unaligned +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_18 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + l1_filter_data_0_address0, + l1_filter_data_0_ce0, + l1_filter_data_0_d0, + l1_filter_data_0_q0, + l1_filter_data_0_we0, + l1_filter_data_0_address1, + l1_filter_data_0_ce1, + l1_filter_data_0_d1, + l1_filter_data_0_q1, + l1_filter_data_0_we1, + l1_filter_data_1_address0, + l1_filter_data_1_ce0, + l1_filter_data_1_d0, + l1_filter_data_1_q0, + l1_filter_data_1_we0, + l1_filter_data_1_address1, + l1_filter_data_1_ce1, + l1_filter_data_1_d1, + l1_filter_data_1_q1, + l1_filter_data_1_we1, + l1_filter_data_2_address0, + l1_filter_data_2_ce0, + l1_filter_data_2_d0, + l1_filter_data_2_q0, + l1_filter_data_2_we0, + l1_filter_data_2_address1, + l1_filter_data_2_ce1, + l1_filter_data_2_d1, + l1_filter_data_2_q1, + l1_filter_data_2_we1, + l1_filter_data_3_address0, + l1_filter_data_3_ce0, + l1_filter_data_3_d0, + l1_filter_data_3_q0, + l1_filter_data_3_we0, + l1_filter_data_3_address1, + l1_filter_data_3_ce1, + l1_filter_data_3_d1, + l1_filter_data_3_q1, + l1_filter_data_3_we1, + l2_filter_data_0_address0, + l2_filter_data_0_ce0, + l2_filter_data_0_d0, + l2_filter_data_0_q0, + l2_filter_data_0_we0, + l2_filter_data_0_address1, + l2_filter_data_0_ce1, + l2_filter_data_0_d1, + l2_filter_data_0_q1, + l2_filter_data_0_we1, + l2_filter_data_1_address0, + l2_filter_data_1_ce0, + l2_filter_data_1_d0, + l2_filter_data_1_q0, + l2_filter_data_1_we0, + l2_filter_data_1_address1, + l2_filter_data_1_ce1, + l2_filter_data_1_d1, + l2_filter_data_1_q1, + l2_filter_data_1_we1, + l1_adjustments_address0, + l1_adjustments_ce0, + l1_adjustments_d0, + l1_adjustments_q0, + l1_adjustments_we0, + l1_adjustments_address1, + l1_adjustments_ce1, + l1_adjustments_d1, + l1_adjustments_q1, + l1_adjustments_we1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_d0, + l2_adjustments_q0, + l2_adjustments_we0, + l2_adjustments_address1, + l2_adjustments_ce1, + l2_adjustments_d1, + l2_adjustments_q1, + l2_adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [12:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [12:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [12:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [12:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [12:0] l1_filter_data_0_address0; +output l1_filter_data_0_ce0; +output [63:0] l1_filter_data_0_d0; +input [63:0] l1_filter_data_0_q0; +output l1_filter_data_0_we0; +output [12:0] l1_filter_data_0_address1; +output l1_filter_data_0_ce1; +output [63:0] l1_filter_data_0_d1; +input [63:0] l1_filter_data_0_q1; +output l1_filter_data_0_we1; +output [12:0] l1_filter_data_1_address0; +output l1_filter_data_1_ce0; +output [63:0] l1_filter_data_1_d0; +input [63:0] l1_filter_data_1_q0; +output l1_filter_data_1_we0; +output [12:0] l1_filter_data_1_address1; +output l1_filter_data_1_ce1; +output [63:0] l1_filter_data_1_d1; +input [63:0] l1_filter_data_1_q1; +output l1_filter_data_1_we1; +output [12:0] l1_filter_data_2_address0; +output l1_filter_data_2_ce0; +output [63:0] l1_filter_data_2_d0; +input [63:0] l1_filter_data_2_q0; +output l1_filter_data_2_we0; +output [12:0] l1_filter_data_2_address1; +output l1_filter_data_2_ce1; +output [63:0] l1_filter_data_2_d1; +input [63:0] l1_filter_data_2_q1; +output l1_filter_data_2_we1; +output [12:0] l1_filter_data_3_address0; +output l1_filter_data_3_ce0; +output [63:0] l1_filter_data_3_d0; +input [63:0] l1_filter_data_3_q0; +output l1_filter_data_3_we0; +output [12:0] l1_filter_data_3_address1; +output l1_filter_data_3_ce1; +output [63:0] l1_filter_data_3_d1; +input [63:0] l1_filter_data_3_q1; +output l1_filter_data_3_we1; +output [11:0] l2_filter_data_0_address0; +output l2_filter_data_0_ce0; +output [15:0] l2_filter_data_0_d0; +input [15:0] l2_filter_data_0_q0; +output l2_filter_data_0_we0; +output [11:0] l2_filter_data_0_address1; +output l2_filter_data_0_ce1; +output [15:0] l2_filter_data_0_d1; +input [15:0] l2_filter_data_0_q1; +output l2_filter_data_0_we1; +output [11:0] l2_filter_data_1_address0; +output l2_filter_data_1_ce0; +output [15:0] l2_filter_data_1_d0; +input [15:0] l2_filter_data_1_q0; +output l2_filter_data_1_we0; +output [11:0] l2_filter_data_1_address1; +output l2_filter_data_1_ce1; +output [15:0] l2_filter_data_1_d1; +input [15:0] l2_filter_data_1_q1; +output l2_filter_data_1_we1; +output [7:0] l1_adjustments_address0; +output l1_adjustments_ce0; +output [47:0] l1_adjustments_d0; +input [47:0] l1_adjustments_q0; +output l1_adjustments_we0; +output [7:0] l1_adjustments_address1; +output l1_adjustments_ce1; +output [47:0] l1_adjustments_d1; +input [47:0] l1_adjustments_q1; +output l1_adjustments_we1; +output [4:0] l2_adjustments_address0; +output l2_adjustments_ce0; +output [47:0] l2_adjustments_d0; +input [47:0] l2_adjustments_q0; +output l2_adjustments_we0; +output [4:0] l2_adjustments_address1; +output l2_adjustments_ce1; +output [47:0] l2_adjustments_d1; +input [47:0] l2_adjustments_q1; +output l2_adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [12:0] dataflow_in_loop_TOP_LOOP48049_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP48049_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48049_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP48049_U0_in_data_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP48049_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP48049_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48049_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP48049_U0_in_data_we1; +wire [12:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_address0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_d0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_address1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_d1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_we1; +wire [12:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_address0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_d0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_address1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_d1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_we1; +wire [12:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_address0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_d0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_address1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_d1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_we1; +wire [12:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_address0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_d0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_address1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_d1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_we1; +wire [7:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_we0; +wire [7:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_we1; +wire [11:0] dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_address0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_d0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_we0; +wire [11:0] dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_address1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_d1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_we1; +wire [11:0] dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_address0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_d0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_we0; +wire [11:0] dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_address1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_d1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_we1; +wire [12:0] dataflow_in_loop_TOP_LOOP48049_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP48049_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48049_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP48049_U0_out_data_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP48049_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP48049_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48049_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP48049_U0_out_data_we1; +wire [4:0] dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_we0; +wire [4:0] dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_we1; +wire dataflow_in_loop_TOP_LOOP48049_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP48049_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP48049_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP48049_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP48049_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP48049_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP48049_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP48049_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP48049_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [15:0] loop_dataflow_input_count; +reg [15:0] loop_dataflow_output_count; +wire [15:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP48049_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP48049_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 16'd0; +#0 loop_dataflow_output_count = 16'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP48049 dataflow_in_loop_TOP_LOOP48049_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP48049_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP48049_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP48049_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP48049_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP48049_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP48049_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP48049_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP48049_U0_in_data_we1), + .l1_filter_data_0_address0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_address0), + .l1_filter_data_0_ce0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_ce0), + .l1_filter_data_0_d0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_d0), + .l1_filter_data_0_q0(l1_filter_data_0_q0), + .l1_filter_data_0_we0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_we0), + .l1_filter_data_0_address1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_address1), + .l1_filter_data_0_ce1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_ce1), + .l1_filter_data_0_d1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_d1), + .l1_filter_data_0_q1(64'd0), + .l1_filter_data_0_we1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_we1), + .l1_filter_data_1_address0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_address0), + .l1_filter_data_1_ce0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_ce0), + .l1_filter_data_1_d0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_d0), + .l1_filter_data_1_q0(l1_filter_data_1_q0), + .l1_filter_data_1_we0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_we0), + .l1_filter_data_1_address1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_address1), + .l1_filter_data_1_ce1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_ce1), + .l1_filter_data_1_d1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_d1), + .l1_filter_data_1_q1(64'd0), + .l1_filter_data_1_we1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_we1), + .l1_filter_data_2_address0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_address0), + .l1_filter_data_2_ce0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_ce0), + .l1_filter_data_2_d0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_d0), + .l1_filter_data_2_q0(l1_filter_data_2_q0), + .l1_filter_data_2_we0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_we0), + .l1_filter_data_2_address1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_address1), + .l1_filter_data_2_ce1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_ce1), + .l1_filter_data_2_d1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_d1), + .l1_filter_data_2_q1(64'd0), + .l1_filter_data_2_we1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_we1), + .l1_filter_data_3_address0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_address0), + .l1_filter_data_3_ce0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_ce0), + .l1_filter_data_3_d0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_d0), + .l1_filter_data_3_q0(l1_filter_data_3_q0), + .l1_filter_data_3_we0(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_we0), + .l1_filter_data_3_address1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_address1), + .l1_filter_data_3_ce1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_ce1), + .l1_filter_data_3_d1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_d1), + .l1_filter_data_3_q1(64'd0), + .l1_filter_data_3_we1(dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_we1), + .l1_adjustments_address0(dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_address0), + .l1_adjustments_ce0(dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_ce0), + .l1_adjustments_d0(dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_d0), + .l1_adjustments_q0(l1_adjustments_q0), + .l1_adjustments_we0(dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_we0), + .l1_adjustments_address1(dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_address1), + .l1_adjustments_ce1(dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_ce1), + .l1_adjustments_d1(dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_d1), + .l1_adjustments_q1(48'd0), + .l1_adjustments_we1(dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_we1), + .l2_filter_data_0_address0(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_address0), + .l2_filter_data_0_ce0(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_ce0), + .l2_filter_data_0_d0(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_d0), + .l2_filter_data_0_q0(l2_filter_data_0_q0), + .l2_filter_data_0_we0(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_we0), + .l2_filter_data_0_address1(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_address1), + .l2_filter_data_0_ce1(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_ce1), + .l2_filter_data_0_d1(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_d1), + .l2_filter_data_0_q1(l2_filter_data_0_q1), + .l2_filter_data_0_we1(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_we1), + .l2_filter_data_1_address0(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_address0), + .l2_filter_data_1_ce0(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_ce0), + .l2_filter_data_1_d0(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_d0), + .l2_filter_data_1_q0(l2_filter_data_1_q0), + .l2_filter_data_1_we0(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_we0), + .l2_filter_data_1_address1(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_address1), + .l2_filter_data_1_ce1(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_ce1), + .l2_filter_data_1_d1(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_d1), + .l2_filter_data_1_q1(l2_filter_data_1_q1), + .l2_filter_data_1_we1(dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP48049_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP48049_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP48049_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP48049_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP48049_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP48049_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP48049_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP48049_U0_out_data_we1), + .l2_adjustments_address0(dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_address0), + .l2_adjustments_ce0(dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_ce0), + .l2_adjustments_d0(dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_d0), + .l2_adjustments_q0(l2_adjustments_q0), + .l2_adjustments_we0(dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_we0), + .l2_adjustments_address1(dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_address1), + .l2_adjustments_ce1(dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_ce1), + .l2_adjustments_d1(dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_d1), + .l2_adjustments_q1(48'd0), + .l2_adjustments_we1(dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_we1), + .ap_start(dataflow_in_loop_TOP_LOOP48049_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP48049_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP48049_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP48049_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP48049_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP48049_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP48049_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 16'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP48049_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 16'd1); + end else if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP48049_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= 16'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 16'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48049_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP48049_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 16'd1); + end else if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48049_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP48049_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= 16'd0; + end + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48049_U0_ap_done == 1'b1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == 16'd0) & (ap_start == 1'b0) & (dataflow_in_loop_TOP_LOOP48049_U0_ap_idle == 1'b1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP48049_U0_ap_ready == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP48049_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP48049_U0_ap_continue = 1'b0; + end +end + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP48049_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP48049_U0_ap_ready; + +assign bound_minus_1 = (16'd50176 - 16'd1); + +assign dataflow_in_loop_TOP_LOOP48049_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP48049_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP48049_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP48049_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP48049_U0_start_write = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP48049_U0_in_data_address0; + +assign in_data_address1 = 13'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP48049_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP48049_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign l1_adjustments_address0 = dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_address0; + +assign l1_adjustments_address1 = 8'd0; + +assign l1_adjustments_ce0 = dataflow_in_loop_TOP_LOOP48049_U0_l1_adjustments_ce0; + +assign l1_adjustments_ce1 = 1'b0; + +assign l1_adjustments_d0 = 48'd0; + +assign l1_adjustments_d1 = 48'd0; + +assign l1_adjustments_we0 = 1'b0; + +assign l1_adjustments_we1 = 1'b0; + +assign l1_filter_data_0_address0 = dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_address0; + +assign l1_filter_data_0_address1 = 13'd0; + +assign l1_filter_data_0_ce0 = dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_0_ce0; + +assign l1_filter_data_0_ce1 = 1'b0; + +assign l1_filter_data_0_d0 = 64'd0; + +assign l1_filter_data_0_d1 = 64'd0; + +assign l1_filter_data_0_we0 = 1'b0; + +assign l1_filter_data_0_we1 = 1'b0; + +assign l1_filter_data_1_address0 = dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_address0; + +assign l1_filter_data_1_address1 = 13'd0; + +assign l1_filter_data_1_ce0 = dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_1_ce0; + +assign l1_filter_data_1_ce1 = 1'b0; + +assign l1_filter_data_1_d0 = 64'd0; + +assign l1_filter_data_1_d1 = 64'd0; + +assign l1_filter_data_1_we0 = 1'b0; + +assign l1_filter_data_1_we1 = 1'b0; + +assign l1_filter_data_2_address0 = dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_address0; + +assign l1_filter_data_2_address1 = 13'd0; + +assign l1_filter_data_2_ce0 = dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_2_ce0; + +assign l1_filter_data_2_ce1 = 1'b0; + +assign l1_filter_data_2_d0 = 64'd0; + +assign l1_filter_data_2_d1 = 64'd0; + +assign l1_filter_data_2_we0 = 1'b0; + +assign l1_filter_data_2_we1 = 1'b0; + +assign l1_filter_data_3_address0 = dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_address0; + +assign l1_filter_data_3_address1 = 13'd0; + +assign l1_filter_data_3_ce0 = dataflow_in_loop_TOP_LOOP48049_U0_l1_filter_data_3_ce0; + +assign l1_filter_data_3_ce1 = 1'b0; + +assign l1_filter_data_3_d0 = 64'd0; + +assign l1_filter_data_3_d1 = 64'd0; + +assign l1_filter_data_3_we0 = 1'b0; + +assign l1_filter_data_3_we1 = 1'b0; + +assign l2_adjustments_address0 = dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_address0; + +assign l2_adjustments_address1 = 5'd0; + +assign l2_adjustments_ce0 = dataflow_in_loop_TOP_LOOP48049_U0_l2_adjustments_ce0; + +assign l2_adjustments_ce1 = 1'b0; + +assign l2_adjustments_d0 = 48'd0; + +assign l2_adjustments_d1 = 48'd0; + +assign l2_adjustments_we0 = 1'b0; + +assign l2_adjustments_we1 = 1'b0; + +assign l2_filter_data_0_address0 = dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_address0; + +assign l2_filter_data_0_address1 = dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_address1; + +assign l2_filter_data_0_ce0 = dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_ce0; + +assign l2_filter_data_0_ce1 = dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_0_ce1; + +assign l2_filter_data_0_d0 = 16'd0; + +assign l2_filter_data_0_d1 = 16'd0; + +assign l2_filter_data_0_we0 = 1'b0; + +assign l2_filter_data_0_we1 = 1'b0; + +assign l2_filter_data_1_address0 = dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_address0; + +assign l2_filter_data_1_address1 = dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_address1; + +assign l2_filter_data_1_ce0 = dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_ce0; + +assign l2_filter_data_1_ce1 = dataflow_in_loop_TOP_LOOP48049_U0_l2_filter_data_1_ce1; + +assign l2_filter_data_1_d0 = 16'd0; + +assign l2_filter_data_1_d1 = 16'd0; + +assign l2_filter_data_1_we0 = 1'b0; + +assign l2_filter_data_1_we1 = 1'b0; + +assign out_data_address0 = 13'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP48049_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP48049_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP48049_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP48049_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP48049_U0_out_data_write; + +endmodule //td_fused_top_tdf7_18 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_in1_address0, + accum_in1_ce0, + accum_in1_q0, + accum_in1_address1, + accum_in1_ce1, + accum_in1_q1, + accum_in2_address0, + accum_in2_ce0, + accum_in2_q0, + accum_in2_address1, + accum_in2_ce1, + accum_in2_q1, + accum_in3_address0, + accum_in3_ce0, + accum_in3_q0, + accum_in3_address1, + accum_in3_ce1, + accum_in3_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_pp0_stage0 = 11'd2; +parameter ap_ST_fsm_pp0_stage1 = 11'd4; +parameter ap_ST_fsm_pp0_stage2 = 11'd8; +parameter ap_ST_fsm_pp0_stage3 = 11'd16; +parameter ap_ST_fsm_pp0_stage4 = 11'd32; +parameter ap_ST_fsm_pp0_stage5 = 11'd64; +parameter ap_ST_fsm_pp0_stage6 = 11'd128; +parameter ap_ST_fsm_state18 = 11'd256; +parameter ap_ST_fsm_pp1_stage0 = 11'd512; +parameter ap_ST_fsm_state21 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [6:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [6:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [6:0] accum_in1_address0; +output accum_in1_ce0; +input [15:0] accum_in1_q0; +output [6:0] accum_in1_address1; +output accum_in1_ce1; +input [15:0] accum_in1_q1; +output [6:0] accum_in2_address0; +output accum_in2_ce0; +input [15:0] accum_in2_q0; +output [6:0] accum_in2_address1; +output accum_in2_ce1; +input [15:0] accum_in2_q1; +output [6:0] accum_in3_address0; +output accum_in3_ce0; +input [15:0] accum_in3_q0; +output [6:0] accum_in3_address1; +output accum_in3_ce1; +input [15:0] accum_in3_q1; +output [4:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [4:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[6:0] accum_in_address0; +reg accum_in_ce0; +reg[6:0] accum_in_address1; +reg accum_in_ce1; +reg[6:0] accum_in1_address0; +reg accum_in1_ce0; +reg[6:0] accum_in1_address1; +reg accum_in1_ce1; +reg[6:0] accum_in2_address0; +reg accum_in2_ce0; +reg[6:0] accum_in2_address1; +reg accum_in2_ce1; +reg[6:0] accum_in3_address0; +reg accum_in3_ce0; +reg[6:0] accum_in3_address1; +reg accum_in3_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [8:0] x_reg_447; +reg [15:0] psum_4_05_reg_459; +reg [15:0] psum_3_04_reg_471; +reg [15:0] psum_2_03_reg_483; +reg [15:0] psum_1_02_reg_495; +reg [15:0] psum_0_01_reg_507; +reg [15:0] psum_9_010_reg_519; +reg [15:0] psum_8_09_reg_531; +reg [15:0] psum_7_08_reg_543; +reg [15:0] psum_6_07_reg_555; +reg [15:0] psum_5_06_reg_567; +reg [15:0] psum_31_032_reg_579; +reg [15:0] psum_30_031_reg_591; +reg [15:0] psum_29_030_reg_603; +reg [15:0] psum_28_029_reg_615; +reg [15:0] psum_27_028_reg_627; +reg [15:0] psum_26_027_reg_639; +reg [15:0] psum_25_026_reg_651; +reg [15:0] psum_24_025_reg_663; +reg [15:0] psum_23_024_reg_675; +reg [15:0] psum_22_023_reg_687; +reg [15:0] psum_21_022_reg_699; +reg [15:0] psum_20_021_reg_711; +reg [15:0] psum_19_020_reg_723; +reg [15:0] psum_18_019_reg_735; +reg [15:0] psum_17_018_reg_747; +reg [15:0] psum_16_017_reg_759; +reg [15:0] psum_15_016_reg_771; +reg [15:0] psum_14_015_reg_783; +reg [15:0] psum_13_014_reg_795; +reg [15:0] psum_12_013_reg_807; +reg [15:0] psum_11_012_reg_819; +reg [15:0] psum_10_011_reg_831; +reg [5:0] q_reg_843; +wire [0:0] icmp_ln132_fu_960_p2; +reg [0:0] icmp_ln132_reg_1322; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state9_pp0_stage0_iter1; +wire ap_block_state16_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln132_reg_1322_pp0_iter1_reg; +reg [0:0] icmp_ln132_reg_1322_pp0_iter2_reg; +wire [6:0] lshr_ln_fu_966_p4; +reg [6:0] lshr_ln_reg_1326; +reg [15:0] accum_in_load_reg_1376; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state10_pp0_stage1_iter1; +wire ap_block_state17_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in1_load_reg_1381; +reg [15:0] accum_in2_load_reg_1386; +reg [15:0] accum_in3_load_reg_1391; +reg [15:0] accum_in_load_15_reg_1396; +reg [15:0] accum_in1_load_8_reg_1401; +reg [15:0] accum_in2_load_1_reg_1406; +reg [15:0] accum_in3_load_1_reg_1411; +reg [15:0] accum_in_load_16_reg_1456; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state11_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in1_load_9_reg_1461; +reg [15:0] accum_in2_load_2_reg_1466; +reg [15:0] accum_in3_load_2_reg_1471; +reg [15:0] accum_in_load_17_reg_1476; +reg [15:0] accum_in1_load_10_reg_1481; +reg [15:0] accum_in2_load_3_reg_1486; +reg [15:0] accum_in3_load_3_reg_1491; +reg [15:0] accum_in_load_18_reg_1536; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state12_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in1_load_11_reg_1541; +reg [15:0] accum_in2_load_4_reg_1546; +reg [15:0] accum_in3_load_4_reg_1551; +reg [15:0] accum_in_load_19_reg_1556; +reg [15:0] accum_in1_load_12_reg_1561; +reg [15:0] accum_in2_load_5_reg_1566; +reg [15:0] accum_in3_load_5_reg_1571; +reg [15:0] accum_in_load_20_reg_1616; +wire ap_CS_fsm_pp0_stage4; +wire ap_block_state6_pp0_stage4_iter0; +wire ap_block_state13_pp0_stage4_iter1; +wire ap_block_pp0_stage4_11001; +reg [15:0] accum_in1_load_13_reg_1621; +reg [15:0] accum_in2_load_6_reg_1626; +reg [15:0] accum_in3_load_6_reg_1631; +reg [15:0] accum_in_load_21_reg_1636; +reg [15:0] accum_in1_load_14_reg_1641; +reg [15:0] accum_in2_load_7_reg_1646; +reg [15:0] accum_in3_load_7_reg_1651; +wire [8:0] add_ln132_fu_1076_p2; +reg [8:0] add_ln132_reg_1656; +wire ap_CS_fsm_pp0_stage6; +wire ap_block_state8_pp0_stage6_iter0; +wire ap_block_state15_pp0_stage6_iter1; +wire ap_block_pp0_stage6_11001; +wire [15:0] grp_fu_908_p2; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_913_p2; +wire [15:0] grp_fu_918_p2; +wire [15:0] grp_fu_923_p2; +wire [15:0] grp_fu_928_p2; +wire ap_CS_fsm_pp0_stage5; +wire ap_block_state7_pp0_stage5_iter0; +wire ap_block_state14_pp0_stage5_iter1; +wire ap_block_pp0_stage5_11001; +reg ap_enable_reg_pp0_iter2; +wire [0:0] tmp_fu_1082_p3; +reg [0:0] tmp_reg_1821; +wire ap_CS_fsm_pp1_stage0; +wire ap_block_state19_pp1_stage0_iter0; +wire ap_block_state20_pp1_stage0_iter1; +wire ap_block_pp1_stage0_11001; +wire [4:0] trunc_ln140_fu_1095_p1; +wire [5:0] add_ln140_fu_1099_p2; +reg ap_enable_reg_pp1_iter0; +wire [4:0] or_ln140_fu_1105_p2; +reg [4:0] or_ln140_reg_1834; +wire [15:0] select_ln152_11_fu_1271_p3; +reg [15:0] select_ln152_11_reg_1842; +reg ap_block_state1; +wire ap_block_pp0_stage4_subdone; +reg ap_condition_pp0_exit_iter0_state6; +wire ap_block_pp0_stage6_subdone; +wire ap_block_pp0_stage1_subdone; +wire ap_CS_fsm_state18; +wire ap_block_pp1_stage0_subdone; +reg ap_condition_pp1_exit_iter0_state19; +reg ap_enable_reg_pp1_iter1; +reg [8:0] ap_phi_mux_x_phi_fu_451_p4; +wire ap_block_pp0_stage0; +wire ap_block_pp0_stage2; +wire [15:0] ap_phi_mux_psum_9_010_phi_fu_523_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_8_09_phi_fu_535_p4; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_547_p4; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_559_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_571_p4; +wire [15:0] ap_phi_mux_psum_31_032_phi_fu_583_p4; +wire ap_block_pp0_stage1; +wire [15:0] ap_phi_mux_psum_30_031_phi_fu_595_p4; +wire [15:0] ap_phi_mux_psum_29_030_phi_fu_607_p4; +wire [15:0] ap_phi_mux_psum_28_029_phi_fu_619_p4; +wire [15:0] ap_phi_mux_psum_27_028_phi_fu_631_p4; +wire [15:0] ap_phi_mux_psum_26_027_phi_fu_643_p4; +wire [15:0] ap_phi_mux_psum_25_026_phi_fu_655_p4; +wire [15:0] ap_phi_mux_psum_24_025_phi_fu_667_p4; +wire ap_block_pp0_stage6; +wire [15:0] ap_phi_mux_psum_23_024_phi_fu_679_p4; +wire [15:0] ap_phi_mux_psum_22_023_phi_fu_691_p4; +wire [15:0] ap_phi_mux_psum_21_022_phi_fu_703_p4; +wire [15:0] ap_phi_mux_psum_20_021_phi_fu_715_p4; +wire [15:0] ap_phi_mux_psum_19_020_phi_fu_727_p4; +wire ap_block_pp0_stage5; +wire [15:0] ap_phi_mux_psum_18_019_phi_fu_739_p4; +wire [15:0] ap_phi_mux_psum_17_018_phi_fu_751_p4; +wire [15:0] ap_phi_mux_psum_16_017_phi_fu_763_p4; +wire [15:0] ap_phi_mux_psum_15_016_phi_fu_775_p4; +wire [15:0] ap_phi_mux_psum_14_015_phi_fu_787_p4; +wire ap_block_pp0_stage4; +wire [15:0] ap_phi_mux_psum_13_014_phi_fu_799_p4; +wire [15:0] ap_phi_mux_psum_12_013_phi_fu_811_p4; +wire [15:0] ap_phi_mux_psum_11_012_phi_fu_823_p4; +wire [15:0] ap_phi_mux_psum_10_011_phi_fu_835_p4; +reg [15:0] ap_phi_mux_phi_ln152_phi_fu_857_p32; +wire [15:0] ap_phi_reg_pp1_iter0_phi_ln152_reg_854; +wire [63:0] zext_ln136_fu_976_p1; +wire [63:0] zext_ln136_1_fu_990_p1; +wire [63:0] zext_ln136_2_fu_1003_p1; +wire [63:0] zext_ln136_3_fu_1016_p1; +wire [63:0] zext_ln136_4_fu_1029_p1; +wire [63:0] zext_ln136_5_fu_1042_p1; +wire [63:0] zext_ln136_6_fu_1055_p1; +wire [63:0] zext_ln136_7_fu_1068_p1; +wire [63:0] zext_ln140_fu_1090_p1; +wire ap_block_pp1_stage0; +wire [63:0] zext_ln140_1_fu_1279_p1; +reg [15:0] grp_fu_908_p0; +reg [15:0] grp_fu_908_p1; +reg [15:0] grp_fu_913_p0; +reg [15:0] grp_fu_913_p1; +reg [15:0] grp_fu_918_p0; +reg [15:0] grp_fu_918_p1; +reg [15:0] grp_fu_923_p0; +reg [15:0] grp_fu_923_p1; +reg [15:0] grp_fu_928_p0; +reg [15:0] grp_fu_928_p1; +wire [6:0] or_ln136_fu_984_p2; +wire [6:0] or_ln136_1_fu_998_p2; +wire [6:0] or_ln136_2_fu_1011_p2; +wire [6:0] or_ln136_3_fu_1024_p2; +wire [6:0] or_ln136_4_fu_1037_p2; +wire [6:0] or_ln136_5_fu_1050_p2; +wire [6:0] or_ln136_6_fu_1063_p2; +wire [0:0] icmp_ln152_fu_1111_p2; +wire [0:0] icmp_ln152_1_fu_1125_p2; +wire [15:0] select_ln152_fu_1117_p3; +wire [0:0] icmp_ln152_2_fu_1139_p2; +wire [15:0] select_ln152_1_fu_1131_p3; +wire [0:0] icmp_ln152_3_fu_1153_p2; +wire [15:0] select_ln152_2_fu_1145_p3; +wire [0:0] icmp_ln152_4_fu_1167_p2; +wire [15:0] select_ln152_3_fu_1159_p3; +wire [0:0] icmp_ln152_5_fu_1181_p2; +wire [15:0] select_ln152_4_fu_1173_p3; +wire [0:0] icmp_ln152_6_fu_1195_p2; +wire [15:0] select_ln152_5_fu_1187_p3; +wire [0:0] icmp_ln152_7_fu_1209_p2; +wire [15:0] select_ln152_6_fu_1201_p3; +wire [0:0] icmp_ln152_8_fu_1223_p2; +wire [15:0] select_ln152_7_fu_1215_p3; +wire [0:0] icmp_ln152_9_fu_1237_p2; +wire [15:0] select_ln152_8_fu_1229_p3; +wire [0:0] icmp_ln152_10_fu_1251_p2; +wire [15:0] select_ln152_9_fu_1243_p3; +wire [0:0] icmp_ln152_11_fu_1265_p2; +wire [15:0] select_ln152_10_fu_1257_p3; +wire [0:0] icmp_ln152_12_fu_1283_p2; +wire [0:0] icmp_ln152_13_fu_1295_p2; +wire [15:0] select_ln152_12_fu_1288_p3; +wire [0:0] icmp_ln152_14_fu_1308_p2; +wire [15:0] select_ln152_13_fu_1300_p3; +wire ap_CS_fsm_state21; +reg [10:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +wire ap_block_pp0_stage2_subdone; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage5_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_idle_pp1; +wire ap_enable_pp1; +reg ap_condition_1097; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp1_iter0 = 1'b0; +#0 ap_enable_reg_pp1_iter1 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1028( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_908_p0), + .din1(grp_fu_908_p1), + .dout(grp_fu_908_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1029( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_913_p0), + .din1(grp_fu_913_p1), + .dout(grp_fu_913_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1030( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_918_p0), + .din1(grp_fu_918_p1), + .dout(grp_fu_918_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1031( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_923_p0), + .din1(grp_fu_923_p1), + .dout(grp_fu_923_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1032( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_928_p0), + .din1(grp_fu_928_p1), + .dout(grp_fu_928_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state21)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state6) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6_subdone))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone)) | ((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6_subdone)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp1_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp1_exit_iter0_state19) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_subdone))) begin + ap_enable_reg_pp1_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state18)) begin + ap_enable_reg_pp1_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp1_iter1 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp1_exit_iter0_state19) & (1'b0 == ap_block_pp1_stage0_subdone))) begin + ap_enable_reg_pp1_iter1 <= (1'b1 ^ ap_condition_pp1_exit_iter0_state19); + end else if ((1'b0 == ap_block_pp1_stage0_subdone)) begin + ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0; + end else if ((1'b1 == ap_CS_fsm_state18)) begin + ap_enable_reg_pp1_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state18)) begin + q_reg_843 <= 6'd0; + end else if (((ap_enable_reg_pp1_iter0 == 1'b1) & (tmp_fu_1082_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + q_reg_843 <= add_ln140_fu_1099_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln132_reg_1322 == 1'd1))) begin + x_reg_447 <= add_ln132_reg_1656; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_447 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (icmp_ln132_reg_1322 == 1'd1))) begin + accum_in1_load_10_reg_1481 <= accum_in1_q0; + accum_in1_load_9_reg_1461 <= accum_in1_q1; + accum_in2_load_2_reg_1466 <= accum_in2_q1; + accum_in2_load_3_reg_1486 <= accum_in2_q0; + accum_in3_load_2_reg_1471 <= accum_in3_q1; + accum_in3_load_3_reg_1491 <= accum_in3_q0; + accum_in_load_16_reg_1456 <= accum_in_q1; + accum_in_load_17_reg_1476 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (icmp_ln132_reg_1322 == 1'd1))) begin + accum_in1_load_11_reg_1541 <= accum_in1_q1; + accum_in1_load_12_reg_1561 <= accum_in1_q0; + accum_in2_load_4_reg_1546 <= accum_in2_q1; + accum_in2_load_5_reg_1566 <= accum_in2_q0; + accum_in3_load_4_reg_1551 <= accum_in3_q1; + accum_in3_load_5_reg_1571 <= accum_in3_q0; + accum_in_load_18_reg_1536 <= accum_in_q1; + accum_in_load_19_reg_1556 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4_11001) & (icmp_ln132_reg_1322 == 1'd1))) begin + accum_in1_load_13_reg_1621 <= accum_in1_q1; + accum_in1_load_14_reg_1641 <= accum_in1_q0; + accum_in2_load_6_reg_1626 <= accum_in2_q1; + accum_in2_load_7_reg_1646 <= accum_in2_q0; + accum_in3_load_6_reg_1631 <= accum_in3_q1; + accum_in3_load_7_reg_1651 <= accum_in3_q0; + accum_in_load_20_reg_1616 <= accum_in_q1; + accum_in_load_21_reg_1636 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln132_reg_1322 == 1'd1))) begin + accum_in1_load_8_reg_1401 <= accum_in1_q0; + accum_in1_load_reg_1381 <= accum_in1_q1; + accum_in2_load_1_reg_1406 <= accum_in2_q0; + accum_in2_load_reg_1386 <= accum_in2_q1; + accum_in3_load_1_reg_1411 <= accum_in3_q0; + accum_in3_load_reg_1391 <= accum_in3_q1; + accum_in_load_15_reg_1396 <= accum_in_q0; + accum_in_load_reg_1376 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6_11001) & (icmp_ln132_reg_1322 == 1'd1))) begin + add_ln132_reg_1656 <= add_ln132_fu_1076_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln132_reg_1322 <= icmp_ln132_fu_960_p2; + icmp_ln132_reg_1322_pp0_iter1_reg <= icmp_ln132_reg_1322; + icmp_ln132_reg_1322_pp0_iter2_reg <= icmp_ln132_reg_1322_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln132_fu_960_p2 == 1'd1))) begin + lshr_ln_reg_1326 <= {{ap_phi_mux_x_phi_fu_451_p4[8:2]}}; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_fu_1082_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + or_ln140_reg_1834[4 : 1] <= or_ln140_fu_1105_p2[4 : 1]; + select_ln152_11_reg_1842 <= select_ln152_11_fu_1271_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (icmp_ln132_reg_1322_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage2_11001))) begin + psum_0_01_reg_507 <= grp_fu_908_p2; + psum_1_02_reg_495 <= grp_fu_913_p2; + psum_2_03_reg_483 <= grp_fu_918_p2; + psum_3_04_reg_471 <= grp_fu_923_p2; + psum_4_05_reg_459 <= grp_fu_928_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (icmp_ln132_reg_1322_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage4_11001))) begin + psum_10_011_reg_831 <= grp_fu_908_p2; + psum_11_012_reg_819 <= grp_fu_913_p2; + psum_12_013_reg_807 <= grp_fu_918_p2; + psum_13_014_reg_795 <= grp_fu_923_p2; + psum_14_015_reg_783 <= grp_fu_928_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (icmp_ln132_reg_1322_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage5_11001))) begin + psum_15_016_reg_771 <= grp_fu_908_p2; + psum_16_017_reg_759 <= grp_fu_913_p2; + psum_17_018_reg_747 <= grp_fu_918_p2; + psum_18_019_reg_735 <= grp_fu_923_p2; + psum_19_020_reg_723 <= grp_fu_928_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage6) & (icmp_ln132_reg_1322_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage6_11001))) begin + psum_20_021_reg_711 <= grp_fu_908_p2; + psum_21_022_reg_699 <= grp_fu_913_p2; + psum_22_023_reg_687 <= grp_fu_918_p2; + psum_23_024_reg_675 <= grp_fu_923_p2; + psum_24_025_reg_663 <= grp_fu_928_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln132_reg_1322_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + psum_25_026_reg_651 <= grp_fu_908_p2; + psum_26_027_reg_639 <= grp_fu_913_p2; + psum_27_028_reg_627 <= grp_fu_918_p2; + psum_28_029_reg_615 <= grp_fu_923_p2; + psum_29_030_reg_603 <= grp_fu_928_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln132_reg_1322_pp0_iter2_reg == 1'd1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + psum_30_031_reg_591 <= grp_fu_908_p2; + psum_31_032_reg_579 <= grp_fu_913_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (icmp_ln132_reg_1322_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + psum_5_06_reg_567 <= grp_fu_908_p2; + psum_6_07_reg_555 <= grp_fu_913_p2; + psum_7_08_reg_543 <= grp_fu_918_p2; + psum_8_09_reg_531 <= grp_fu_923_p2; + psum_9_010_reg_519 <= grp_fu_928_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + tmp_reg_1821 <= q_reg_843[32'd5]; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in1_address0 = zext_ln136_7_fu_1068_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in1_address0 = zext_ln136_5_fu_1042_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in1_address0 = zext_ln136_3_fu_1016_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in1_address0 = zext_ln136_1_fu_990_p1; + end else begin + accum_in1_address0 = 'bx; + end + end else begin + accum_in1_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in1_address1 = zext_ln136_6_fu_1055_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in1_address1 = zext_ln136_4_fu_1029_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in1_address1 = zext_ln136_2_fu_1003_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in1_address1 = zext_ln136_fu_976_p1; + end else begin + accum_in1_address1 = 'bx; + end + end else begin + accum_in1_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in1_ce0 = 1'b1; + end else begin + accum_in1_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in1_ce1 = 1'b1; + end else begin + accum_in1_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in2_address0 = zext_ln136_7_fu_1068_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in2_address0 = zext_ln136_5_fu_1042_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in2_address0 = zext_ln136_3_fu_1016_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in2_address0 = zext_ln136_1_fu_990_p1; + end else begin + accum_in2_address0 = 'bx; + end + end else begin + accum_in2_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in2_address1 = zext_ln136_6_fu_1055_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in2_address1 = zext_ln136_4_fu_1029_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in2_address1 = zext_ln136_2_fu_1003_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in2_address1 = zext_ln136_fu_976_p1; + end else begin + accum_in2_address1 = 'bx; + end + end else begin + accum_in2_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in2_ce0 = 1'b1; + end else begin + accum_in2_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in2_ce1 = 1'b1; + end else begin + accum_in2_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in3_address0 = zext_ln136_7_fu_1068_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in3_address0 = zext_ln136_5_fu_1042_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in3_address0 = zext_ln136_3_fu_1016_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in3_address0 = zext_ln136_1_fu_990_p1; + end else begin + accum_in3_address0 = 'bx; + end + end else begin + accum_in3_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in3_address1 = zext_ln136_6_fu_1055_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in3_address1 = zext_ln136_4_fu_1029_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in3_address1 = zext_ln136_2_fu_1003_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in3_address1 = zext_ln136_fu_976_p1; + end else begin + accum_in3_address1 = 'bx; + end + end else begin + accum_in3_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in3_ce0 = 1'b1; + end else begin + accum_in3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in3_ce1 = 1'b1; + end else begin + accum_in3_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in_address0 = zext_ln136_7_fu_1068_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in_address0 = zext_ln136_5_fu_1042_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in_address0 = zext_ln136_3_fu_1016_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in_address0 = zext_ln136_1_fu_990_p1; + end else begin + accum_in_address0 = 'bx; + end + end else begin + accum_in_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in_address1 = zext_ln136_6_fu_1055_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in_address1 = zext_ln136_4_fu_1029_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in_address1 = zext_ln136_2_fu_1003_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in_address1 = zext_ln136_fu_976_p1; + end else begin + accum_in_address1 = 'bx; + end + end else begin + accum_in_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp1_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp1_iter1 == 1'b1) & (tmp_reg_1821 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp1_iter0 == 1'b1) & (tmp_fu_1082_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b0 == ap_block_pp1_stage0_11001))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln132_reg_1322 == 1'd0)) begin + ap_condition_pp0_exit_iter0_state6 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state6 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_fu_1082_p3 == 1'd1)) begin + ap_condition_pp1_exit_iter0_state19 = 1'b1; + end else begin + ap_condition_pp1_exit_iter0_state19 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state21)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b0))) begin + ap_idle_pp1 = 1'b1; + end else begin + ap_idle_pp1 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_fu_1082_p3 == 1'd0)) begin + if ((trunc_ln140_fu_1095_p1 == 5'd0)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_0_01_reg_507; + end else if ((1'b1 == ap_condition_1097)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_30_031_reg_591; + end else if ((trunc_ln140_fu_1095_p1 == 5'd28)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_28_029_reg_615; + end else if ((trunc_ln140_fu_1095_p1 == 5'd26)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_26_027_reg_639; + end else if ((trunc_ln140_fu_1095_p1 == 5'd24)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_24_025_reg_663; + end else if ((trunc_ln140_fu_1095_p1 == 5'd22)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_22_023_reg_687; + end else if ((trunc_ln140_fu_1095_p1 == 5'd20)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_20_021_reg_711; + end else if ((trunc_ln140_fu_1095_p1 == 5'd18)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_18_019_reg_735; + end else if ((trunc_ln140_fu_1095_p1 == 5'd16)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_16_017_reg_759; + end else if ((trunc_ln140_fu_1095_p1 == 5'd14)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_14_015_reg_783; + end else if ((trunc_ln140_fu_1095_p1 == 5'd12)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_12_013_reg_807; + end else if ((trunc_ln140_fu_1095_p1 == 5'd10)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_10_011_reg_831; + end else if ((trunc_ln140_fu_1095_p1 == 5'd8)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_8_09_reg_531; + end else if ((trunc_ln140_fu_1095_p1 == 5'd6)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_6_07_reg_555; + end else if ((trunc_ln140_fu_1095_p1 == 5'd4)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_4_05_reg_459; + end else if ((trunc_ln140_fu_1095_p1 == 5'd2)) begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = psum_2_03_reg_483; + end else begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = ap_phi_reg_pp1_iter0_phi_ln152_reg_854; + end + end else begin + ap_phi_mux_phi_ln152_phi_fu_857_p32 = ap_phi_reg_pp1_iter0_phi_ln152_reg_854; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0) & (icmp_ln132_reg_1322 == 1'd1))) begin + ap_phi_mux_x_phi_fu_451_p4 = add_ln132_reg_1656; + end else begin + ap_phi_mux_x_phi_fu_451_p4 = x_reg_447; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state21)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + grp_fu_908_p0 = ap_phi_mux_psum_30_031_phi_fu_595_p4; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_908_p0 = ap_phi_mux_psum_25_026_phi_fu_655_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_908_p0 = ap_phi_mux_psum_20_021_phi_fu_715_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_908_p0 = ap_phi_mux_psum_15_016_phi_fu_775_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_908_p0 = ap_phi_mux_psum_10_011_phi_fu_835_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_908_p0 = ap_phi_mux_psum_5_06_phi_fu_571_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_908_p0 = grp_fu_908_p2; + end else begin + grp_fu_908_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + grp_fu_908_p1 = accum_in2_load_7_reg_1646; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_908_p1 = accum_in1_load_13_reg_1621; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_908_p1 = accum_in_load_19_reg_1556; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_908_p1 = accum_in3_load_3_reg_1491; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_908_p1 = accum_in2_load_2_reg_1466; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_908_p1 = accum_in1_load_8_reg_1401; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_908_p1 = accum_in_load_reg_1376; + end else begin + grp_fu_908_p1 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + grp_fu_913_p0 = ap_phi_mux_psum_31_032_phi_fu_583_p4; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_913_p0 = ap_phi_mux_psum_26_027_phi_fu_643_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_913_p0 = ap_phi_mux_psum_21_022_phi_fu_703_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_913_p0 = ap_phi_mux_psum_16_017_phi_fu_763_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_913_p0 = ap_phi_mux_psum_11_012_phi_fu_823_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_913_p0 = ap_phi_mux_psum_6_07_phi_fu_559_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_913_p0 = grp_fu_913_p2; + end else begin + grp_fu_913_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + grp_fu_913_p1 = accum_in3_load_7_reg_1651; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_913_p1 = accum_in2_load_6_reg_1626; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_913_p1 = accum_in1_load_12_reg_1561; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_913_p1 = accum_in_load_18_reg_1536; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_913_p1 = accum_in3_load_2_reg_1471; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_913_p1 = accum_in2_load_1_reg_1406; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_913_p1 = accum_in1_load_reg_1381; + end else begin + grp_fu_913_p1 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_918_p0 = ap_phi_mux_psum_27_028_phi_fu_631_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_918_p0 = ap_phi_mux_psum_22_023_phi_fu_691_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_918_p0 = ap_phi_mux_psum_17_018_phi_fu_751_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_918_p0 = ap_phi_mux_psum_12_013_phi_fu_811_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_918_p0 = ap_phi_mux_psum_7_08_phi_fu_547_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_918_p0 = grp_fu_918_p2; + end else begin + grp_fu_918_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_918_p1 = accum_in3_load_6_reg_1631; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_918_p1 = accum_in2_load_5_reg_1566; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_918_p1 = accum_in1_load_11_reg_1541; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_918_p1 = accum_in_load_17_reg_1476; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_918_p1 = accum_in3_load_1_reg_1411; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_918_p1 = accum_in2_load_reg_1386; + end else begin + grp_fu_918_p1 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_923_p0 = ap_phi_mux_psum_28_029_phi_fu_619_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_923_p0 = ap_phi_mux_psum_23_024_phi_fu_679_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_923_p0 = ap_phi_mux_psum_18_019_phi_fu_739_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_923_p0 = ap_phi_mux_psum_13_014_phi_fu_799_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_923_p0 = ap_phi_mux_psum_8_09_phi_fu_535_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_923_p0 = grp_fu_923_p2; + end else begin + grp_fu_923_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_923_p1 = accum_in_load_21_reg_1636; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_923_p1 = accum_in3_load_5_reg_1571; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_923_p1 = accum_in2_load_4_reg_1546; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_923_p1 = accum_in1_load_10_reg_1481; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_923_p1 = accum_in_load_16_reg_1456; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_923_p1 = accum_in3_load_reg_1391; + end else begin + grp_fu_923_p1 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_928_p0 = ap_phi_mux_psum_29_030_phi_fu_607_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_928_p0 = ap_phi_mux_psum_24_025_phi_fu_667_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_928_p0 = ap_phi_mux_psum_19_020_phi_fu_727_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_928_p0 = ap_phi_mux_psum_14_015_phi_fu_787_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_928_p0 = ap_phi_mux_psum_9_010_phi_fu_523_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_928_p0 = grp_fu_928_p2; + end else begin + grp_fu_928_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_928_p1 = accum_in1_load_14_reg_1641; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_928_p1 = accum_in_load_20_reg_1616; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_928_p1 = accum_in3_load_4_reg_1551; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_928_p1 = accum_in2_load_3_reg_1486; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_928_p1 = accum_in1_load_9_reg_1461; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_928_p1 = accum_in_load_15_reg_1396; + end else begin + grp_fu_928_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state18; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((1'b0 == ap_block_pp0_stage2_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_pp0_stage4 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4_subdone) & (icmp_ln132_reg_1322 == 1'd0)) & (1'b0 == ap_block_pp0_stage4_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end else if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4_subdone) & (icmp_ln132_reg_1322 == 1'd0))) begin + ap_NS_fsm = ap_ST_fsm_state18; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end + end + ap_ST_fsm_pp0_stage5 : begin + if ((1'b0 == ap_block_pp0_stage5_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end + end + ap_ST_fsm_pp0_stage6 : begin + if ((1'b0 == ap_block_pp0_stage6_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end + end + ap_ST_fsm_state18 : begin + ap_NS_fsm = ap_ST_fsm_pp1_stage0; + end + ap_ST_fsm_pp1_stage0 : begin + if (~((ap_enable_reg_pp1_iter0 == 1'b1) & (tmp_fu_1082_p3 == 1'd1) & (1'b0 == ap_block_pp1_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp1_stage0; + end else if (((ap_enable_reg_pp1_iter0 == 1'b1) & (tmp_fu_1082_p3 == 1'd1) & (1'b0 == ap_block_pp1_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state21; + end else begin + ap_NS_fsm = ap_ST_fsm_pp1_stage0; + end + end + ap_ST_fsm_state21 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln140_1_fu_1279_p1; + +assign accum_out_address1 = zext_ln140_fu_1090_p1; + +assign accum_out_d0 = ((icmp_ln152_14_fu_1308_p2[0:0] == 1'b1) ? psum_29_030_reg_603 : select_ln152_13_fu_1300_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln152_phi_fu_857_p32; + +assign add_ln132_fu_1076_p2 = (x_reg_447 + 9'd32); + +assign add_ln140_fu_1099_p2 = (q_reg_843 + 6'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_pp1_stage0 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state18 = ap_CS_fsm[32'd8]; + +assign ap_CS_fsm_state21 = ap_CS_fsm[32'd10]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp1_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp1_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp1_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage4_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage5_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage6_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp1_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp1_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_1097 = (~(trunc_ln140_fu_1095_p1 == 5'd0) & ~(trunc_ln140_fu_1095_p1 == 5'd28) & ~(trunc_ln140_fu_1095_p1 == 5'd26) & ~(trunc_ln140_fu_1095_p1 == 5'd24) & ~(trunc_ln140_fu_1095_p1 == 5'd22) & ~(trunc_ln140_fu_1095_p1 == 5'd20) & ~(trunc_ln140_fu_1095_p1 == 5'd18) & ~(trunc_ln140_fu_1095_p1 == 5'd16) & ~(trunc_ln140_fu_1095_p1 == 5'd14) & ~(trunc_ln140_fu_1095_p1 == 5'd12) & ~(trunc_ln140_fu_1095_p1 == 5'd10) & ~(trunc_ln140_fu_1095_p1 == 5'd8) & ~(trunc_ln140_fu_1095_p1 == 5'd6) & ~(trunc_ln140_fu_1095_p1 == 5'd4) & ~(trunc_ln140_fu_1095_p1 == 5'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_enable_pp1 = (ap_idle_pp1 ^ 1'b1); + +assign ap_phi_mux_psum_10_011_phi_fu_835_p4 = grp_fu_908_p2; + +assign ap_phi_mux_psum_11_012_phi_fu_823_p4 = grp_fu_913_p2; + +assign ap_phi_mux_psum_12_013_phi_fu_811_p4 = grp_fu_918_p2; + +assign ap_phi_mux_psum_13_014_phi_fu_799_p4 = grp_fu_923_p2; + +assign ap_phi_mux_psum_14_015_phi_fu_787_p4 = grp_fu_928_p2; + +assign ap_phi_mux_psum_15_016_phi_fu_775_p4 = grp_fu_908_p2; + +assign ap_phi_mux_psum_16_017_phi_fu_763_p4 = grp_fu_913_p2; + +assign ap_phi_mux_psum_17_018_phi_fu_751_p4 = grp_fu_918_p2; + +assign ap_phi_mux_psum_18_019_phi_fu_739_p4 = grp_fu_923_p2; + +assign ap_phi_mux_psum_19_020_phi_fu_727_p4 = grp_fu_928_p2; + +assign ap_phi_mux_psum_20_021_phi_fu_715_p4 = grp_fu_908_p2; + +assign ap_phi_mux_psum_21_022_phi_fu_703_p4 = grp_fu_913_p2; + +assign ap_phi_mux_psum_22_023_phi_fu_691_p4 = grp_fu_918_p2; + +assign ap_phi_mux_psum_23_024_phi_fu_679_p4 = grp_fu_923_p2; + +assign ap_phi_mux_psum_24_025_phi_fu_667_p4 = grp_fu_928_p2; + +assign ap_phi_mux_psum_25_026_phi_fu_655_p4 = grp_fu_908_p2; + +assign ap_phi_mux_psum_26_027_phi_fu_643_p4 = grp_fu_913_p2; + +assign ap_phi_mux_psum_27_028_phi_fu_631_p4 = grp_fu_918_p2; + +assign ap_phi_mux_psum_28_029_phi_fu_619_p4 = grp_fu_923_p2; + +assign ap_phi_mux_psum_29_030_phi_fu_607_p4 = grp_fu_928_p2; + +assign ap_phi_mux_psum_30_031_phi_fu_595_p4 = grp_fu_908_p2; + +assign ap_phi_mux_psum_31_032_phi_fu_583_p4 = grp_fu_913_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_571_p4 = grp_fu_908_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_559_p4 = grp_fu_913_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_547_p4 = grp_fu_918_p2; + +assign ap_phi_mux_psum_8_09_phi_fu_535_p4 = grp_fu_923_p2; + +assign ap_phi_mux_psum_9_010_phi_fu_523_p4 = grp_fu_928_p2; + +assign ap_phi_reg_pp1_iter0_phi_ln152_reg_854 = 'bx; + +assign icmp_ln132_fu_960_p2 = ((ap_phi_mux_x_phi_fu_451_p4 < 9'd288) ? 1'b1 : 1'b0); + +assign icmp_ln152_10_fu_1251_p2 = ((or_ln140_fu_1105_p2 == 5'd21) ? 1'b1 : 1'b0); + +assign icmp_ln152_11_fu_1265_p2 = ((or_ln140_fu_1105_p2 == 5'd23) ? 1'b1 : 1'b0); + +assign icmp_ln152_12_fu_1283_p2 = ((or_ln140_reg_1834 == 5'd25) ? 1'b1 : 1'b0); + +assign icmp_ln152_13_fu_1295_p2 = ((or_ln140_reg_1834 == 5'd27) ? 1'b1 : 1'b0); + +assign icmp_ln152_14_fu_1308_p2 = ((or_ln140_reg_1834 == 5'd29) ? 1'b1 : 1'b0); + +assign icmp_ln152_1_fu_1125_p2 = ((or_ln140_fu_1105_p2 == 5'd3) ? 1'b1 : 1'b0); + +assign icmp_ln152_2_fu_1139_p2 = ((or_ln140_fu_1105_p2 == 5'd5) ? 1'b1 : 1'b0); + +assign icmp_ln152_3_fu_1153_p2 = ((or_ln140_fu_1105_p2 == 5'd7) ? 1'b1 : 1'b0); + +assign icmp_ln152_4_fu_1167_p2 = ((or_ln140_fu_1105_p2 == 5'd9) ? 1'b1 : 1'b0); + +assign icmp_ln152_5_fu_1181_p2 = ((or_ln140_fu_1105_p2 == 5'd11) ? 1'b1 : 1'b0); + +assign icmp_ln152_6_fu_1195_p2 = ((or_ln140_fu_1105_p2 == 5'd13) ? 1'b1 : 1'b0); + +assign icmp_ln152_7_fu_1209_p2 = ((or_ln140_fu_1105_p2 == 5'd15) ? 1'b1 : 1'b0); + +assign icmp_ln152_8_fu_1223_p2 = ((or_ln140_fu_1105_p2 == 5'd17) ? 1'b1 : 1'b0); + +assign icmp_ln152_9_fu_1237_p2 = ((or_ln140_fu_1105_p2 == 5'd19) ? 1'b1 : 1'b0); + +assign icmp_ln152_fu_1111_p2 = ((or_ln140_fu_1105_p2 == 5'd1) ? 1'b1 : 1'b0); + +assign lshr_ln_fu_966_p4 = {{ap_phi_mux_x_phi_fu_451_p4[8:2]}}; + +assign or_ln136_1_fu_998_p2 = (lshr_ln_reg_1326 | 7'd2); + +assign or_ln136_2_fu_1011_p2 = (lshr_ln_reg_1326 | 7'd3); + +assign or_ln136_3_fu_1024_p2 = (lshr_ln_reg_1326 | 7'd4); + +assign or_ln136_4_fu_1037_p2 = (lshr_ln_reg_1326 | 7'd5); + +assign or_ln136_5_fu_1050_p2 = (lshr_ln_reg_1326 | 7'd6); + +assign or_ln136_6_fu_1063_p2 = (lshr_ln_reg_1326 | 7'd7); + +assign or_ln136_fu_984_p2 = (lshr_ln_fu_966_p4 | 7'd1); + +assign or_ln140_fu_1105_p2 = (trunc_ln140_fu_1095_p1 | 5'd1); + +assign select_ln152_10_fu_1257_p3 = ((icmp_ln152_10_fu_1251_p2[0:0] == 1'b1) ? psum_21_022_reg_699 : select_ln152_9_fu_1243_p3); + +assign select_ln152_11_fu_1271_p3 = ((icmp_ln152_11_fu_1265_p2[0:0] == 1'b1) ? psum_23_024_reg_675 : select_ln152_10_fu_1257_p3); + +assign select_ln152_12_fu_1288_p3 = ((icmp_ln152_12_fu_1283_p2[0:0] == 1'b1) ? psum_25_026_reg_651 : select_ln152_11_reg_1842); + +assign select_ln152_13_fu_1300_p3 = ((icmp_ln152_13_fu_1295_p2[0:0] == 1'b1) ? psum_27_028_reg_627 : select_ln152_12_fu_1288_p3); + +assign select_ln152_1_fu_1131_p3 = ((icmp_ln152_1_fu_1125_p2[0:0] == 1'b1) ? psum_3_04_reg_471 : select_ln152_fu_1117_p3); + +assign select_ln152_2_fu_1145_p3 = ((icmp_ln152_2_fu_1139_p2[0:0] == 1'b1) ? psum_5_06_reg_567 : select_ln152_1_fu_1131_p3); + +assign select_ln152_3_fu_1159_p3 = ((icmp_ln152_3_fu_1153_p2[0:0] == 1'b1) ? psum_7_08_reg_543 : select_ln152_2_fu_1145_p3); + +assign select_ln152_4_fu_1173_p3 = ((icmp_ln152_4_fu_1167_p2[0:0] == 1'b1) ? psum_9_010_reg_519 : select_ln152_3_fu_1159_p3); + +assign select_ln152_5_fu_1187_p3 = ((icmp_ln152_5_fu_1181_p2[0:0] == 1'b1) ? psum_11_012_reg_819 : select_ln152_4_fu_1173_p3); + +assign select_ln152_6_fu_1201_p3 = ((icmp_ln152_6_fu_1195_p2[0:0] == 1'b1) ? psum_13_014_reg_795 : select_ln152_5_fu_1187_p3); + +assign select_ln152_7_fu_1215_p3 = ((icmp_ln152_7_fu_1209_p2[0:0] == 1'b1) ? psum_15_016_reg_771 : select_ln152_6_fu_1201_p3); + +assign select_ln152_8_fu_1229_p3 = ((icmp_ln152_8_fu_1223_p2[0:0] == 1'b1) ? psum_17_018_reg_747 : select_ln152_7_fu_1215_p3); + +assign select_ln152_9_fu_1243_p3 = ((icmp_ln152_9_fu_1237_p2[0:0] == 1'b1) ? psum_19_020_reg_723 : select_ln152_8_fu_1229_p3); + +assign select_ln152_fu_1117_p3 = ((icmp_ln152_fu_1111_p2[0:0] == 1'b1) ? psum_1_02_reg_495 : psum_31_032_reg_579); + +assign tmp_fu_1082_p3 = q_reg_843[32'd5]; + +assign trunc_ln140_fu_1095_p1 = q_reg_843[4:0]; + +assign zext_ln136_1_fu_990_p1 = or_ln136_fu_984_p2; + +assign zext_ln136_2_fu_1003_p1 = or_ln136_1_fu_998_p2; + +assign zext_ln136_3_fu_1016_p1 = or_ln136_2_fu_1011_p2; + +assign zext_ln136_4_fu_1029_p1 = or_ln136_3_fu_1024_p2; + +assign zext_ln136_5_fu_1042_p1 = or_ln136_4_fu_1037_p2; + +assign zext_ln136_6_fu_1055_p1 = or_ln136_5_fu_1050_p2; + +assign zext_ln136_7_fu_1068_p1 = or_ln136_6_fu_1063_p2; + +assign zext_ln136_fu_976_p1 = lshr_ln_fu_966_p4; + +assign zext_ln140_1_fu_1279_p1 = or_ln140_reg_1834; + +assign zext_ln140_fu_1090_p1 = q_reg_843; + +always @ (posedge ap_clk) begin + or_ln140_reg_1834[0] <= 1'b1; +end + +endmodule //td_fused_top_tdf7_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_pp0_stage0 = 11'd2; +parameter ap_ST_fsm_pp0_stage1 = 11'd4; +parameter ap_ST_fsm_pp0_stage2 = 11'd8; +parameter ap_ST_fsm_pp0_stage3 = 11'd16; +parameter ap_ST_fsm_pp0_stage4 = 11'd32; +parameter ap_ST_fsm_pp0_stage5 = 11'd64; +parameter ap_ST_fsm_pp0_stage6 = 11'd128; +parameter ap_ST_fsm_state15 = 11'd256; +parameter ap_ST_fsm_state16 = 11'd512; +parameter ap_ST_fsm_state17 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [4:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [4:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[4:0] accum_in_address0; +reg accum_in_ce0; +reg[4:0] accum_in_address1; +reg accum_in_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [5:0] x_reg_168; +reg [15:0] psum_7_0136_reg_180; +reg [15:0] psum_6_0135_reg_192; +reg [15:0] psum_5_0134_reg_204; +reg [15:0] psum_4_0133_reg_216; +reg [15:0] psum_3_0132_reg_228; +reg [15:0] psum_2_0131_reg_240; +reg [15:0] psum_1_0130_reg_252; +reg [15:0] psum_0_0129_reg_264; +wire [0:0] tmp_fu_321_p3; +reg [0:0] tmp_reg_492; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state9_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +reg [0:0] tmp_reg_492_pp0_iter1_reg; +wire [4:0] trunc_ln171_fu_334_p1; +reg [4:0] trunc_ln171_reg_496; +reg [15:0] accum_in_load_reg_516; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state10_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_load_8_reg_521; +reg [15:0] accum_in_load_9_reg_536; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state11_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_load_10_reg_541; +reg [15:0] accum_in_load_11_reg_556; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state12_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_load_12_reg_561; +reg [15:0] accum_in_load_13_reg_576; +wire ap_CS_fsm_pp0_stage4; +wire ap_block_state6_pp0_stage4_iter0; +wire ap_block_state13_pp0_stage4_iter1; +wire ap_block_pp0_stage4_11001; +reg [15:0] accum_in_load_14_reg_581; +wire [5:0] add_ln171_fu_409_p2; +reg [5:0] add_ln171_reg_586; +wire ap_CS_fsm_pp0_stage6; +wire ap_block_state8_pp0_stage6_iter0; +wire ap_block_pp0_stage6_11001; +wire [15:0] grp_fu_305_p2; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_310_p2; +wire ap_CS_fsm_pp0_stage5; +wire ap_block_state7_pp0_stage5_iter0; +wire ap_block_state14_pp0_stage5_iter1; +wire ap_block_pp0_stage5_11001; +wire [3:0] add_ln179_fu_432_p2; +wire ap_CS_fsm_state16; +wire [0:0] tmp_30_fu_415_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage6_subdone; +wire ap_block_pp0_stage5_subdone; +reg [5:0] ap_phi_mux_x_phi_fu_172_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_0136_phi_fu_184_p4; +wire ap_block_pp0_stage5; +wire [15:0] ap_phi_mux_psum_6_0135_phi_fu_196_p4; +wire [15:0] ap_phi_mux_psum_5_0134_phi_fu_208_p4; +wire ap_block_pp0_stage4; +wire [15:0] ap_phi_mux_psum_4_0133_phi_fu_220_p4; +wire [15:0] ap_phi_mux_psum_3_0132_phi_fu_232_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_0131_phi_fu_244_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_276; +wire ap_CS_fsm_state15; +reg [15:0] ap_phi_mux_phi_ln191_phi_fu_290_p8; +wire [2:0] trunc_ln179_fu_428_p1; +wire [63:0] zext_ln171_fu_329_p1; +wire [63:0] zext_ln175_fu_344_p1; +wire [63:0] zext_ln175_1_fu_354_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln175_2_fu_364_p1; +wire [63:0] zext_ln175_3_fu_374_p1; +wire [63:0] zext_ln175_4_fu_384_p1; +wire [63:0] zext_ln175_5_fu_394_p1; +wire [63:0] zext_ln175_6_fu_404_p1; +wire [63:0] zext_ln179_fu_423_p1; +wire [63:0] zext_ln179_1_fu_444_p1; +reg [15:0] grp_fu_305_p0; +reg [15:0] grp_fu_305_p1; +reg [15:0] grp_fu_310_p0; +reg [15:0] grp_fu_310_p1; +wire [4:0] or_ln175_fu_338_p2; +wire [4:0] or_ln175_1_fu_349_p2; +wire [4:0] or_ln175_2_fu_359_p2; +wire [4:0] or_ln175_3_fu_369_p2; +wire [4:0] or_ln175_4_fu_379_p2; +wire [4:0] or_ln175_5_fu_389_p2; +wire [4:0] or_ln175_6_fu_399_p2; +wire ap_block_pp0_stage6; +wire [2:0] or_ln179_fu_438_p2; +wire [0:0] icmp_ln191_fu_449_p2; +wire [0:0] icmp_ln191_1_fu_463_p2; +wire [15:0] select_ln191_fu_455_p3; +wire [0:0] icmp_ln191_2_fu_477_p2; +wire [15:0] select_ln191_1_fu_469_p3; +wire ap_CS_fsm_state17; +reg [10:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +wire ap_block_pp0_stage1_subdone; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage4_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_570; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1038( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_305_p0), + .din1(grp_fu_305_p1), + .dout(grp_fu_305_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1039( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_310_p0), + .din1(grp_fu_310_p1), + .dout(grp_fu_310_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage5_subdone) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0)) | ((1'b0 == ap_block_pp0_stage6_subdone) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state15)) begin + q_reg_276 <= 4'd0; + end else if (((tmp_30_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + q_reg_276 <= add_ln179_fu_432_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + x_reg_168 <= add_ln171_reg_586; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_168 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage2_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_load_10_reg_541 <= accum_in_q0; + accum_in_load_9_reg_536 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage3_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_load_11_reg_556 <= accum_in_q1; + accum_in_load_12_reg_561 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage4_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_load_13_reg_576 <= accum_in_q1; + accum_in_load_14_reg_581 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_load_8_reg_521 <= accum_in_q0; + accum_in_load_reg_516 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage6_11001) & (tmp_reg_492 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln171_reg_586 <= add_ln171_fu_409_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage2_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + psum_0_0129_reg_264 <= grp_fu_305_p2; + psum_1_0130_reg_252 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + psum_2_0131_reg_240 <= grp_fu_305_p2; + psum_3_0132_reg_228 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage4_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + psum_4_0133_reg_216 <= grp_fu_305_p2; + psum_5_0134_reg_204 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_492_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage5_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + psum_6_0135_reg_192 <= grp_fu_305_p2; + psum_7_0136_reg_180 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + tmp_reg_492 <= ap_phi_mux_x_phi_fu_172_p4[32'd5]; + tmp_reg_492_pp0_iter1_reg <= tmp_reg_492; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_fu_321_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln171_reg_496 <= trunc_ln171_fu_334_p1; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_address0 = zext_ln175_6_fu_404_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_address0 = zext_ln175_4_fu_384_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_address0 = zext_ln175_2_fu_364_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_address0 = zext_ln175_fu_344_p1; + end else begin + accum_in_address0 = 'bx; + end + end else begin + accum_in_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_address1 = zext_ln175_5_fu_394_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_address1 = zext_ln175_3_fu_374_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_address1 = zext_ln175_1_fu_354_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_address1 = zext_ln171_fu_329_p1; + end else begin + accum_in_address1 = 'bx; + end + end else begin + accum_in_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_30_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_30_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_reg_492 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_30_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + if ((trunc_ln179_fu_428_p1 == 3'd0)) begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = psum_0_0129_reg_264; + end else if ((1'b1 == ap_condition_570)) begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = psum_6_0135_reg_192; + end else if ((trunc_ln179_fu_428_p1 == 3'd4)) begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = psum_4_0133_reg_216; + end else if ((trunc_ln179_fu_428_p1 == 3'd2)) begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = psum_2_0131_reg_240; + end else begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln191_phi_fu_290_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (tmp_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_x_phi_fu_172_p4 = add_ln171_reg_586; + end else begin + ap_phi_mux_x_phi_fu_172_p4 = x_reg_168; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_305_p0 = ap_phi_mux_psum_6_0135_phi_fu_196_p4; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_305_p0 = ap_phi_mux_psum_4_0133_phi_fu_220_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p0 = ap_phi_mux_psum_2_0131_phi_fu_244_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p0 = grp_fu_305_p2; + end else begin + grp_fu_305_p0 = 'bx; + end + end else begin + grp_fu_305_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_305_p1 = accum_in_load_13_reg_576; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_305_p1 = accum_in_load_11_reg_556; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p1 = accum_in_load_9_reg_536; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p1 = accum_in_load_reg_516; + end else begin + grp_fu_305_p1 = 'bx; + end + end else begin + grp_fu_305_p1 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_310_p0 = ap_phi_mux_psum_7_0136_phi_fu_184_p4; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_310_p0 = ap_phi_mux_psum_5_0134_phi_fu_208_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p0 = ap_phi_mux_psum_3_0132_phi_fu_232_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p0 = grp_fu_310_p2; + end else begin + grp_fu_310_p0 = 'bx; + end + end else begin + grp_fu_310_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_310_p1 = accum_in_load_14_reg_581; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_310_p1 = accum_in_load_12_reg_561; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p1 = accum_in_load_10_reg_541; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p1 = accum_in_load_8_reg_521; + end else begin + grp_fu_310_p1 = 'bx; + end + end else begin + grp_fu_310_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_492 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_492 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state15; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_pp0_stage4 : begin + if ((1'b0 == ap_block_pp0_stage4_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end + end + ap_ST_fsm_pp0_stage5 : begin + if ((~((1'b0 == ap_block_pp0_stage5_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0)) & (1'b0 == ap_block_pp0_stage5_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end else if (((1'b0 == ap_block_pp0_stage5_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state15; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end + end + ap_ST_fsm_pp0_stage6 : begin + if ((1'b0 == ap_block_pp0_stage6_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + if (((tmp_30_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + ap_NS_fsm = ap_ST_fsm_state16; + end else begin + ap_NS_fsm = ap_ST_fsm_state17; + end + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln179_1_fu_444_p1; + +assign accum_out_address1 = zext_ln179_fu_423_p1; + +assign accum_out_d0 = ((icmp_ln191_2_fu_477_p2[0:0] == 1'b1) ? psum_5_0134_reg_204 : select_ln191_1_fu_469_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln191_phi_fu_290_p8; + +assign add_ln171_fu_409_p2 = (x_reg_168 + 6'd8); + +assign add_ln179_fu_432_p2 = (q_reg_276 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state15 = ap_CS_fsm[32'd8]; + +assign ap_CS_fsm_state16 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd10]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage4_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage5_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_570 = (~(trunc_ln179_fu_428_p1 == 3'd0) & ~(trunc_ln179_fu_428_p1 == 3'd4) & ~(trunc_ln179_fu_428_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_0131_phi_fu_244_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_3_0132_phi_fu_232_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_4_0133_phi_fu_220_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_5_0134_phi_fu_208_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_6_0135_phi_fu_196_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_7_0136_phi_fu_184_p4 = grp_fu_310_p2; + +assign icmp_ln191_1_fu_463_p2 = ((or_ln179_fu_438_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln191_2_fu_477_p2 = ((or_ln179_fu_438_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln191_fu_449_p2 = ((or_ln179_fu_438_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln175_1_fu_349_p2 = (trunc_ln171_reg_496 | 5'd2); + +assign or_ln175_2_fu_359_p2 = (trunc_ln171_reg_496 | 5'd3); + +assign or_ln175_3_fu_369_p2 = (trunc_ln171_reg_496 | 5'd4); + +assign or_ln175_4_fu_379_p2 = (trunc_ln171_reg_496 | 5'd5); + +assign or_ln175_5_fu_389_p2 = (trunc_ln171_reg_496 | 5'd6); + +assign or_ln175_6_fu_399_p2 = (trunc_ln171_reg_496 | 5'd7); + +assign or_ln175_fu_338_p2 = (trunc_ln171_fu_334_p1 | 5'd1); + +assign or_ln179_fu_438_p2 = (trunc_ln179_fu_428_p1 | 3'd1); + +assign select_ln191_1_fu_469_p3 = ((icmp_ln191_1_fu_463_p2[0:0] == 1'b1) ? psum_3_0132_reg_228 : select_ln191_fu_455_p3); + +assign select_ln191_fu_455_p3 = ((icmp_ln191_fu_449_p2[0:0] == 1'b1) ? psum_1_0130_reg_252 : psum_7_0136_reg_180); + +assign tmp_30_fu_415_p3 = q_reg_276[32'd3]; + +assign tmp_fu_321_p3 = ap_phi_mux_x_phi_fu_172_p4[32'd5]; + +assign trunc_ln171_fu_334_p1 = ap_phi_mux_x_phi_fu_172_p4[4:0]; + +assign trunc_ln179_fu_428_p1 = q_reg_276[2:0]; + +assign zext_ln171_fu_329_p1 = ap_phi_mux_x_phi_fu_172_p4; + +assign zext_ln175_1_fu_354_p1 = or_ln175_1_fu_349_p2; + +assign zext_ln175_2_fu_364_p1 = or_ln175_2_fu_359_p2; + +assign zext_ln175_3_fu_374_p1 = or_ln175_3_fu_369_p2; + +assign zext_ln175_4_fu_384_p1 = or_ln175_4_fu_379_p2; + +assign zext_ln175_5_fu_394_p1 = or_ln175_5_fu_389_p2; + +assign zext_ln175_6_fu_404_p1 = or_ln175_6_fu_399_p2; + +assign zext_ln175_fu_344_p1 = or_ln175_fu_338_p2; + +assign zext_ln179_1_fu_444_p1 = or_ln179_fu_438_p2; + +assign zext_ln179_fu_423_p1 = q_reg_276; + +endmodule //td_fused_top_tdf7_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_accum_3_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_16, + accum_in_16_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_16; +output accum_in_16_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_16; +reg accum_in_16_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln203_fu_73_p2; +reg [3:0] add_ln203_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln203_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln203_fu_79_p1; +reg [15:0] accum_in_16_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_16_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1046( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_16_preg <= 16'd0; + end else begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_16_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln203_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln203_reg_90 <= add_ln203_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_16 = sum_01_reg_55; + end else begin + accum_in_16 = accum_in_16_preg; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_16_ap_vld = 1'b1; + end else begin + accum_in_16_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln203_fu_79_p1; + +assign add_ln203_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln203_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln203_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf7_accum_3_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_accum_3_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_14, + accum_in_14_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_14; +output accum_in_14_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_14; +reg accum_in_14_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln203_fu_73_p2; +reg [3:0] add_ln203_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln203_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln203_fu_79_p1; +reg [15:0] accum_in_14_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_14_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1050( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_14_preg <= 16'd0; + end else begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_14_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln203_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln203_reg_90 <= add_ln203_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_14 = sum_01_reg_55; + end else begin + accum_in_14 = accum_in_14_preg; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_14_ap_vld = 1'b1; + end else begin + accum_in_14_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln203_fu_79_p1; + +assign add_ln203_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln203_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln203_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf7_accum_3_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_accum_3_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_12, + accum_in_12_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_12; +output accum_in_12_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_12; +reg accum_in_12_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln203_fu_73_p2; +reg [3:0] add_ln203_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln203_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln203_fu_79_p1; +reg [15:0] accum_in_12_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_12_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1054( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_12_preg <= 16'd0; + end else begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_12_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln203_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln203_reg_90 <= add_ln203_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_12 = sum_01_reg_55; + end else begin + accum_in_12 = accum_in_12_preg; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_12_ap_vld = 1'b1; + end else begin + accum_in_12_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln203_fu_79_p1; + +assign add_ln203_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln203_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln203_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf7_accum_3_3 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_accum_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_18, + accum_in_18_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_18; +output accum_in_18_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_18; +reg accum_in_18_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln203_fu_73_p2; +reg [3:0] add_ln203_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln203_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln203_fu_79_p1; +reg [15:0] accum_in_18_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_18_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1042( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_18_preg <= 16'd0; + end else begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_18_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln203_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln203_reg_90 <= add_ln203_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_18 = sum_01_reg_55; + end else begin + accum_in_18 = accum_in_18_preg; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_18_ap_vld = 1'b1; + end else begin + accum_in_18_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln203_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln203_fu_79_p1; + +assign add_ln203_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln203_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln203_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf7_accum_3 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_adjustments_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 48; +parameter AWIDTH = 8; +parameter MEM_SIZE = 256; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_adjustments( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd48; +parameter AddressRange = 32'd256; +parameter AddressWidth = 32'd8; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf7_adjustments_ram td_fused_top_tdf7_adjustments_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_0_read, + sums_1_read, + sums_2_read, + sums_3_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + indices_23_out_din, + indices_23_out_full_n, + indices_23_out_write, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state25 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_0_read; +input [15:0] sums_1_read; +input [15:0] sums_2_read; +input [15:0] sums_3_read; +output [7:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [5:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [5:0] indices_23_out_din; +input indices_23_out_full_n; +output indices_23_out_write; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg indices_23_read; +reg indices_23_out_write; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg indices_23_out_blk_n; +reg [0:0] write_flag6_0_reg_153; +reg [0:0] write_flag9_0_reg_164; +reg [0:0] write_flag12_0_reg_175; +reg [0:0] write_flag_0_reg_186; +reg [2:0] o_reg_197; +reg [15:0] outputs_1_011_reg_208; +reg [15:0] outputs_0_010_reg_220; +reg [15:0] outputs_2_09_reg_232; +reg [15:0] outputs_3_08_reg_244; +reg [5:0] indices_23_read_reg_546; +wire [2:0] add_ln213_fu_268_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_state13_pp0_stage0_iter11; +wire ap_block_state14_pp0_stage0_iter12; +wire ap_block_state15_pp0_stage0_iter13; +wire ap_block_state16_pp0_stage0_iter14; +wire ap_block_state17_pp0_stage0_iter15; +wire ap_block_state18_pp0_stage0_iter16; +wire ap_block_state19_pp0_stage0_iter17; +wire ap_block_state20_pp0_stage0_iter18; +wire ap_block_state21_pp0_stage0_iter19; +wire ap_block_state22_pp0_stage0_iter20; +wire ap_block_state23_pp0_stage0_iter21; +wire ap_block_state24_pp0_stage0_iter22; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln213_fu_274_p2; +reg [0:0] icmp_ln213_reg_556; +reg [0:0] icmp_ln213_reg_556_pp0_iter1_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter2_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter3_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter4_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter5_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter6_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter7_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter8_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter9_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter10_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter11_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter12_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter13_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter14_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter15_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter16_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter17_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter18_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter19_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter20_reg; +reg [0:0] icmp_ln213_reg_556_pp0_iter21_reg; +wire [1:0] trunc_ln219_fu_280_p1; +reg [1:0] trunc_ln219_reg_560; +reg [1:0] trunc_ln219_reg_560_pp0_iter1_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter2_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter3_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter4_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter5_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter6_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter7_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter8_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter9_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter10_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter11_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter12_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter13_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter14_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter15_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter16_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter17_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter18_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter19_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter20_reg; +reg [1:0] trunc_ln219_reg_560_pp0_iter21_reg; +wire [0:0] write_flag_1_fu_296_p6; +wire [0:0] write_flag12_1_fu_310_p6; +wire [0:0] write_flag9_1_fu_324_p6; +wire [0:0] write_flag6_1_fu_338_p6; +wire [15:0] trunc_ln220_fu_352_p1; +reg [15:0] trunc_ln220_reg_593; +reg [15:0] tmp_74_i_i_reg_598; +reg [15:0] tmp_74_i_i_reg_598_pp0_iter2_reg; +reg [15:0] tmp_74_i_i_reg_598_pp0_iter3_reg; +reg [15:0] tmp_74_i_i_reg_598_pp0_iter4_reg; +reg [15:0] tmp_74_i_i_reg_598_pp0_iter5_reg; +reg [15:0] tmp_74_i_i_reg_598_pp0_iter6_reg; +reg [15:0] tmp_74_i_i_reg_598_pp0_iter7_reg; +reg [15:0] tmp_74_i_i_reg_598_pp0_iter8_reg; +reg [15:0] tmp_75_i_i_reg_603; +reg [15:0] tmp_75_i_i_reg_603_pp0_iter2_reg; +reg [15:0] tmp_75_i_i_reg_603_pp0_iter3_reg; +reg [15:0] tmp_75_i_i_reg_603_pp0_iter4_reg; +reg [15:0] tmp_75_i_i_reg_603_pp0_iter5_reg; +reg [15:0] tmp_75_i_i_reg_603_pp0_iter6_reg; +reg [15:0] tmp_75_i_i_reg_603_pp0_iter7_reg; +reg [15:0] tmp_75_i_i_reg_603_pp0_iter8_reg; +reg [15:0] tmp_75_i_i_reg_603_pp0_iter9_reg; +reg [15:0] tmp_75_i_i_reg_603_pp0_iter10_reg; +reg [15:0] tmp_75_i_i_reg_603_pp0_iter11_reg; +reg [15:0] tmp_75_i_i_reg_603_pp0_iter12_reg; +reg [15:0] tmp_75_i_i_reg_603_pp0_iter13_reg; +wire [15:0] val_in_assign_fu_376_p6; +reg [15:0] val_in_assign_reg_608; +wire [15:0] grp_fu_260_p2; +reg [15:0] sub_i_i_i_reg_618; +wire [15:0] grp_fu_264_p2; +reg [15:0] normalized_reg_628; +wire [15:0] grp_fu_256_p2; +reg [15:0] biased_reg_638; +wire [15:0] outputs_3_1_fu_446_p3; +reg ap_enable_reg_pp0_iter22; +wire [15:0] outputs_2_1_fu_454_p3; +wire [15:0] outputs_0_1_fu_478_p3; +wire [15:0] outputs_1_1_fu_494_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_condition_pp0_exit_iter21_state23; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln220_fu_291_p1; +wire [15:0] grp_fu_256_p1; +wire [15:0] grp_fu_260_p1; +wire [15:0] grp_fu_264_p1; +wire [7:0] ochan_fu_284_p3; +wire [15:0] data_V_fu_397_p1; +wire [0:0] p_Result_s_fu_400_p3; +wire [0:0] icmp_ln223_fu_415_p2; +wire [15:0] activated_fu_408_p3; +wire [0:0] icmp_ln223_3_fu_428_p2; +wire [15:0] select_ln223_fu_420_p3; +wire [0:0] icmp_ln223_4_fu_441_p2; +wire [15:0] select_ln223_5_fu_433_p3; +wire [15:0] select_ln223_6_fu_462_p3; +wire [15:0] select_ln223_7_fu_470_p3; +wire [15:0] select_ln223_8_fu_486_p3; +wire ap_CS_fsm_state25; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1058( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(normalized_reg_628), + .din1(grp_fu_256_p1), + .dout(grp_fu_256_p2) +); + +td_fused_top_hsub_16ns_16ns_16_7_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 7 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_7_full_dsp_1_U1059( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(val_in_assign_reg_608), + .din1(grp_fu_260_p1), + .dout(grp_fu_260_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1060( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_618), + .din1(grp_fu_264_p1), + .dout(grp_fu_264_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U1061( + .din0(1'd1), + .din1(write_flag_0_reg_186), + .din2(write_flag_0_reg_186), + .din3(write_flag_0_reg_186), + .din4(trunc_ln219_fu_280_p1), + .dout(write_flag_1_fu_296_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U1062( + .din0(write_flag12_0_reg_175), + .din1(write_flag12_0_reg_175), + .din2(write_flag12_0_reg_175), + .din3(1'd1), + .din4(trunc_ln219_fu_280_p1), + .dout(write_flag12_1_fu_310_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U1063( + .din0(write_flag9_0_reg_164), + .din1(write_flag9_0_reg_164), + .din2(1'd1), + .din3(write_flag9_0_reg_164), + .din4(trunc_ln219_fu_280_p1), + .dout(write_flag9_1_fu_324_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U1064( + .din0(write_flag6_0_reg_153), + .din1(1'd1), + .din2(write_flag6_0_reg_153), + .din3(write_flag6_0_reg_153), + .din4(trunc_ln219_fu_280_p1), + .dout(write_flag6_1_fu_338_p6) +); + +td_fused_top_mux_42_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 16 )) +mux_42_16_1_1_U1065( + .din0(sums_0_read), + .din1(sums_1_read), + .din2(sums_2_read), + .din3(sums_3_read), + .din4(trunc_ln219_reg_560), + .dout(val_in_assign_fu_376_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end else if ((((ap_enable_reg_pp0_iter20 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter21_state23) & (1'b0 == ap_block_pp0_stage0_subdone)) | (~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter21_state23) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter20; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + o_reg_197 <= add_ln213_fu_268_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + o_reg_197 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag12_0_reg_175 <= write_flag12_1_fu_310_p6; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag12_0_reg_175 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag6_0_reg_153 <= write_flag6_1_fu_338_p6; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_153 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag9_0_reg_164 <= write_flag9_1_fu_324_p6; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_164 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag_0_reg_186 <= write_flag_1_fu_296_p6; + end else if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_186 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_556_pp0_iter20_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + biased_reg_638 <= grp_fu_256_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln213_reg_556 <= icmp_ln213_fu_274_p2; + icmp_ln213_reg_556_pp0_iter1_reg <= icmp_ln213_reg_556; + trunc_ln219_reg_560_pp0_iter1_reg <= trunc_ln219_reg_560; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln213_reg_556_pp0_iter10_reg <= icmp_ln213_reg_556_pp0_iter9_reg; + icmp_ln213_reg_556_pp0_iter11_reg <= icmp_ln213_reg_556_pp0_iter10_reg; + icmp_ln213_reg_556_pp0_iter12_reg <= icmp_ln213_reg_556_pp0_iter11_reg; + icmp_ln213_reg_556_pp0_iter13_reg <= icmp_ln213_reg_556_pp0_iter12_reg; + icmp_ln213_reg_556_pp0_iter14_reg <= icmp_ln213_reg_556_pp0_iter13_reg; + icmp_ln213_reg_556_pp0_iter15_reg <= icmp_ln213_reg_556_pp0_iter14_reg; + icmp_ln213_reg_556_pp0_iter16_reg <= icmp_ln213_reg_556_pp0_iter15_reg; + icmp_ln213_reg_556_pp0_iter17_reg <= icmp_ln213_reg_556_pp0_iter16_reg; + icmp_ln213_reg_556_pp0_iter18_reg <= icmp_ln213_reg_556_pp0_iter17_reg; + icmp_ln213_reg_556_pp0_iter19_reg <= icmp_ln213_reg_556_pp0_iter18_reg; + icmp_ln213_reg_556_pp0_iter20_reg <= icmp_ln213_reg_556_pp0_iter19_reg; + icmp_ln213_reg_556_pp0_iter21_reg <= icmp_ln213_reg_556_pp0_iter20_reg; + icmp_ln213_reg_556_pp0_iter2_reg <= icmp_ln213_reg_556_pp0_iter1_reg; + icmp_ln213_reg_556_pp0_iter3_reg <= icmp_ln213_reg_556_pp0_iter2_reg; + icmp_ln213_reg_556_pp0_iter4_reg <= icmp_ln213_reg_556_pp0_iter3_reg; + icmp_ln213_reg_556_pp0_iter5_reg <= icmp_ln213_reg_556_pp0_iter4_reg; + icmp_ln213_reg_556_pp0_iter6_reg <= icmp_ln213_reg_556_pp0_iter5_reg; + icmp_ln213_reg_556_pp0_iter7_reg <= icmp_ln213_reg_556_pp0_iter6_reg; + icmp_ln213_reg_556_pp0_iter8_reg <= icmp_ln213_reg_556_pp0_iter7_reg; + icmp_ln213_reg_556_pp0_iter9_reg <= icmp_ln213_reg_556_pp0_iter8_reg; + tmp_74_i_i_reg_598_pp0_iter2_reg <= tmp_74_i_i_reg_598; + tmp_74_i_i_reg_598_pp0_iter3_reg <= tmp_74_i_i_reg_598_pp0_iter2_reg; + tmp_74_i_i_reg_598_pp0_iter4_reg <= tmp_74_i_i_reg_598_pp0_iter3_reg; + tmp_74_i_i_reg_598_pp0_iter5_reg <= tmp_74_i_i_reg_598_pp0_iter4_reg; + tmp_74_i_i_reg_598_pp0_iter6_reg <= tmp_74_i_i_reg_598_pp0_iter5_reg; + tmp_74_i_i_reg_598_pp0_iter7_reg <= tmp_74_i_i_reg_598_pp0_iter6_reg; + tmp_74_i_i_reg_598_pp0_iter8_reg <= tmp_74_i_i_reg_598_pp0_iter7_reg; + tmp_75_i_i_reg_603_pp0_iter10_reg <= tmp_75_i_i_reg_603_pp0_iter9_reg; + tmp_75_i_i_reg_603_pp0_iter11_reg <= tmp_75_i_i_reg_603_pp0_iter10_reg; + tmp_75_i_i_reg_603_pp0_iter12_reg <= tmp_75_i_i_reg_603_pp0_iter11_reg; + tmp_75_i_i_reg_603_pp0_iter13_reg <= tmp_75_i_i_reg_603_pp0_iter12_reg; + tmp_75_i_i_reg_603_pp0_iter2_reg <= tmp_75_i_i_reg_603; + tmp_75_i_i_reg_603_pp0_iter3_reg <= tmp_75_i_i_reg_603_pp0_iter2_reg; + tmp_75_i_i_reg_603_pp0_iter4_reg <= tmp_75_i_i_reg_603_pp0_iter3_reg; + tmp_75_i_i_reg_603_pp0_iter5_reg <= tmp_75_i_i_reg_603_pp0_iter4_reg; + tmp_75_i_i_reg_603_pp0_iter6_reg <= tmp_75_i_i_reg_603_pp0_iter5_reg; + tmp_75_i_i_reg_603_pp0_iter7_reg <= tmp_75_i_i_reg_603_pp0_iter6_reg; + tmp_75_i_i_reg_603_pp0_iter8_reg <= tmp_75_i_i_reg_603_pp0_iter7_reg; + tmp_75_i_i_reg_603_pp0_iter9_reg <= tmp_75_i_i_reg_603_pp0_iter8_reg; + trunc_ln219_reg_560_pp0_iter10_reg <= trunc_ln219_reg_560_pp0_iter9_reg; + trunc_ln219_reg_560_pp0_iter11_reg <= trunc_ln219_reg_560_pp0_iter10_reg; + trunc_ln219_reg_560_pp0_iter12_reg <= trunc_ln219_reg_560_pp0_iter11_reg; + trunc_ln219_reg_560_pp0_iter13_reg <= trunc_ln219_reg_560_pp0_iter12_reg; + trunc_ln219_reg_560_pp0_iter14_reg <= trunc_ln219_reg_560_pp0_iter13_reg; + trunc_ln219_reg_560_pp0_iter15_reg <= trunc_ln219_reg_560_pp0_iter14_reg; + trunc_ln219_reg_560_pp0_iter16_reg <= trunc_ln219_reg_560_pp0_iter15_reg; + trunc_ln219_reg_560_pp0_iter17_reg <= trunc_ln219_reg_560_pp0_iter16_reg; + trunc_ln219_reg_560_pp0_iter18_reg <= trunc_ln219_reg_560_pp0_iter17_reg; + trunc_ln219_reg_560_pp0_iter19_reg <= trunc_ln219_reg_560_pp0_iter18_reg; + trunc_ln219_reg_560_pp0_iter20_reg <= trunc_ln219_reg_560_pp0_iter19_reg; + trunc_ln219_reg_560_pp0_iter21_reg <= trunc_ln219_reg_560_pp0_iter20_reg; + trunc_ln219_reg_560_pp0_iter2_reg <= trunc_ln219_reg_560_pp0_iter1_reg; + trunc_ln219_reg_560_pp0_iter3_reg <= trunc_ln219_reg_560_pp0_iter2_reg; + trunc_ln219_reg_560_pp0_iter4_reg <= trunc_ln219_reg_560_pp0_iter3_reg; + trunc_ln219_reg_560_pp0_iter5_reg <= trunc_ln219_reg_560_pp0_iter4_reg; + trunc_ln219_reg_560_pp0_iter6_reg <= trunc_ln219_reg_560_pp0_iter5_reg; + trunc_ln219_reg_560_pp0_iter7_reg <= trunc_ln219_reg_560_pp0_iter6_reg; + trunc_ln219_reg_560_pp0_iter8_reg <= trunc_ln219_reg_560_pp0_iter7_reg; + trunc_ln219_reg_560_pp0_iter9_reg <= trunc_ln219_reg_560_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + indices_23_read_reg_546 <= indices_23_dout; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_556_pp0_iter12_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + normalized_reg_628 <= grp_fu_264_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter22 == 1'b1) & (icmp_ln213_reg_556_pp0_iter21_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + outputs_0_010_reg_220 <= outputs_0_1_fu_478_p3; + outputs_1_011_reg_208 <= outputs_1_1_fu_494_p3; + outputs_2_09_reg_232 <= outputs_2_1_fu_454_p3; + outputs_3_08_reg_244 <= outputs_3_1_fu_446_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_556_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sub_i_i_i_reg_618 <= grp_fu_260_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_reg_556 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + tmp_74_i_i_reg_598 <= {{adjustments_q0[31:16]}}; + tmp_75_i_i_reg_603 <= {{adjustments_q0[47:32]}}; + trunc_ln220_reg_593 <= trunc_ln220_fu_352_p1; + val_in_assign_reg_608 <= val_in_assign_fu_376_p6; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + trunc_ln219_reg_560 <= trunc_ln219_fu_280_p1; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0))) begin + ap_condition_pp0_exit_iter21_state23 = 1'b1; + end else begin + ap_condition_pp0_exit_iter21_state23 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_274_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_out_blk_n = indices_23_out_full_n; + end else begin + indices_23_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_out_write = 1'b1; + end else begin + indices_23_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state25; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state25 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign activated_fu_408_p3 = ((p_Result_s_fu_400_p3[0:0] == 1'b1) ? 16'd0 : biased_reg_638); + +assign add_ln213_fu_268_p2 = (o_reg_197 + 3'd1); + +assign adjustments_address0 = zext_ln220_fu_291_p1; + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state25 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = outputs_0_010_reg_220; + +assign ap_return_1 = outputs_1_011_reg_208; + +assign ap_return_2 = outputs_2_09_reg_232; + +assign ap_return_3 = outputs_3_08_reg_244; + +assign data_V_fu_397_p1 = biased_reg_638; + +assign grp_fu_256_p1 = tmp_75_i_i_reg_603_pp0_iter13_reg; + +assign grp_fu_260_p1 = trunc_ln220_reg_593; + +assign grp_fu_264_p1 = tmp_74_i_i_reg_598_pp0_iter8_reg; + +assign icmp_ln213_fu_274_p2 = ((o_reg_197 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln223_3_fu_428_p2 = ((trunc_ln219_reg_560_pp0_iter21_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln223_4_fu_441_p2 = ((trunc_ln219_reg_560_pp0_iter21_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln223_fu_415_p2 = ((trunc_ln219_reg_560_pp0_iter21_reg == 2'd0) ? 1'b1 : 1'b0); + +assign indices_23_out_din = indices_23_dout; + +assign ochan_fu_284_p3 = {{indices_23_read_reg_546}, {trunc_ln219_fu_280_p1}}; + +assign outputs_0_1_fu_478_p3 = ((icmp_ln223_4_fu_441_p2[0:0] == 1'b1) ? outputs_0_010_reg_220 : select_ln223_7_fu_470_p3); + +assign outputs_1_1_fu_494_p3 = ((icmp_ln223_4_fu_441_p2[0:0] == 1'b1) ? outputs_1_011_reg_208 : select_ln223_8_fu_486_p3); + +assign outputs_2_1_fu_454_p3 = ((icmp_ln223_4_fu_441_p2[0:0] == 1'b1) ? activated_fu_408_p3 : outputs_2_09_reg_232); + +assign outputs_3_1_fu_446_p3 = ((icmp_ln223_4_fu_441_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : select_ln223_5_fu_433_p3); + +assign p_Result_s_fu_400_p3 = data_V_fu_397_p1[32'd15]; + +assign select_ln223_5_fu_433_p3 = ((icmp_ln223_3_fu_428_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : select_ln223_fu_420_p3); + +assign select_ln223_6_fu_462_p3 = ((icmp_ln223_fu_415_p2[0:0] == 1'b1) ? activated_fu_408_p3 : outputs_0_010_reg_220); + +assign select_ln223_7_fu_470_p3 = ((icmp_ln223_3_fu_428_p2[0:0] == 1'b1) ? outputs_0_010_reg_220 : select_ln223_6_fu_462_p3); + +assign select_ln223_8_fu_486_p3 = ((icmp_ln223_3_fu_428_p2[0:0] == 1'b1) ? activated_fu_408_p3 : outputs_1_011_reg_208); + +assign select_ln223_fu_420_p3 = ((icmp_ln223_fu_415_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : activated_fu_408_p3); + +assign trunc_ln219_fu_280_p1 = o_reg_197[1:0]; + +assign trunc_ln220_fu_352_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_291_p1 = ochan_fu_284_p3; + +endmodule //td_fused_top_tdf7_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_0_address0, + ifmap_vec_0_ce0, + ifmap_vec_0_q0, + ifmap_vec_1_address0, + ifmap_vec_1_ce0, + ifmap_vec_1_q0, + ifmap_vec_2_address0, + ifmap_vec_2_ce0, + ifmap_vec_2_q0, + ifmap_vec_3_address0, + ifmap_vec_3_ce0, + ifmap_vec_3_q0, + weight_vecs_0_0_address0, + weight_vecs_0_0_ce0, + weight_vecs_0_0_q0, + weight_vecs_0_1_address0, + weight_vecs_0_1_ce0, + weight_vecs_0_1_q0, + weight_vecs_0_2_address0, + weight_vecs_0_2_ce0, + weight_vecs_0_2_q0, + weight_vecs_0_3_address0, + weight_vecs_0_3_ce0, + weight_vecs_0_3_q0, + weight_vecs_1_0_address0, + weight_vecs_1_0_ce0, + weight_vecs_1_0_q0, + weight_vecs_1_1_address0, + weight_vecs_1_1_ce0, + weight_vecs_1_1_q0, + weight_vecs_1_2_address0, + weight_vecs_1_2_ce0, + weight_vecs_1_2_q0, + weight_vecs_1_3_address0, + weight_vecs_1_3_ce0, + weight_vecs_1_3_q0, + weight_vecs_2_0_address0, + weight_vecs_2_0_ce0, + weight_vecs_2_0_q0, + weight_vecs_2_1_address0, + weight_vecs_2_1_ce0, + weight_vecs_2_1_q0, + weight_vecs_2_2_address0, + weight_vecs_2_2_ce0, + weight_vecs_2_2_q0, + weight_vecs_2_3_address0, + weight_vecs_2_3_ce0, + weight_vecs_2_3_q0, + weight_vecs_3_0_address0, + weight_vecs_3_0_ce0, + weight_vecs_3_0_q0, + weight_vecs_3_1_address0, + weight_vecs_3_1_ce0, + weight_vecs_3_1_q0, + weight_vecs_3_2_address0, + weight_vecs_3_2_ce0, + weight_vecs_3_2_q0, + weight_vecs_3_3_address0, + weight_vecs_3_3_ce0, + weight_vecs_3_3_q0, + products_0_0_address0, + products_0_0_ce0, + products_0_0_we0, + products_0_0_d0, + products_0_1_address0, + products_0_1_ce0, + products_0_1_we0, + products_0_1_d0, + products_0_2_address0, + products_0_2_ce0, + products_0_2_we0, + products_0_2_d0, + products_0_3_address0, + products_0_3_ce0, + products_0_3_we0, + products_0_3_d0, + products_1_0_address0, + products_1_0_ce0, + products_1_0_we0, + products_1_0_d0, + products_1_1_address0, + products_1_1_ce0, + products_1_1_we0, + products_1_1_d0, + products_1_2_address0, + products_1_2_ce0, + products_1_2_we0, + products_1_2_d0, + products_1_3_address0, + products_1_3_ce0, + products_1_3_we0, + products_1_3_d0, + products_2_0_address0, + products_2_0_ce0, + products_2_0_we0, + products_2_0_d0, + products_2_1_address0, + products_2_1_ce0, + products_2_1_we0, + products_2_1_d0, + products_2_2_address0, + products_2_2_ce0, + products_2_2_we0, + products_2_2_d0, + products_2_3_address0, + products_2_3_ce0, + products_2_3_we0, + products_2_3_d0, + products_3_0_address0, + products_3_0_ce0, + products_3_0_we0, + products_3_0_d0, + products_3_1_address0, + products_3_1_ce0, + products_3_1_we0, + products_3_1_d0, + products_3_2_address0, + products_3_2_ce0, + products_3_2_we0, + products_3_2_d0, + products_3_3_address0, + products_3_3_ce0, + products_3_3_we0, + products_3_3_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state11 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [6:0] ifmap_vec_0_address0; +output ifmap_vec_0_ce0; +input [15:0] ifmap_vec_0_q0; +output [6:0] ifmap_vec_1_address0; +output ifmap_vec_1_ce0; +input [15:0] ifmap_vec_1_q0; +output [6:0] ifmap_vec_2_address0; +output ifmap_vec_2_ce0; +input [15:0] ifmap_vec_2_q0; +output [6:0] ifmap_vec_3_address0; +output ifmap_vec_3_ce0; +input [15:0] ifmap_vec_3_q0; +output [6:0] weight_vecs_0_0_address0; +output weight_vecs_0_0_ce0; +input [15:0] weight_vecs_0_0_q0; +output [6:0] weight_vecs_0_1_address0; +output weight_vecs_0_1_ce0; +input [15:0] weight_vecs_0_1_q0; +output [6:0] weight_vecs_0_2_address0; +output weight_vecs_0_2_ce0; +input [15:0] weight_vecs_0_2_q0; +output [6:0] weight_vecs_0_3_address0; +output weight_vecs_0_3_ce0; +input [15:0] weight_vecs_0_3_q0; +output [6:0] weight_vecs_1_0_address0; +output weight_vecs_1_0_ce0; +input [15:0] weight_vecs_1_0_q0; +output [6:0] weight_vecs_1_1_address0; +output weight_vecs_1_1_ce0; +input [15:0] weight_vecs_1_1_q0; +output [6:0] weight_vecs_1_2_address0; +output weight_vecs_1_2_ce0; +input [15:0] weight_vecs_1_2_q0; +output [6:0] weight_vecs_1_3_address0; +output weight_vecs_1_3_ce0; +input [15:0] weight_vecs_1_3_q0; +output [6:0] weight_vecs_2_0_address0; +output weight_vecs_2_0_ce0; +input [15:0] weight_vecs_2_0_q0; +output [6:0] weight_vecs_2_1_address0; +output weight_vecs_2_1_ce0; +input [15:0] weight_vecs_2_1_q0; +output [6:0] weight_vecs_2_2_address0; +output weight_vecs_2_2_ce0; +input [15:0] weight_vecs_2_2_q0; +output [6:0] weight_vecs_2_3_address0; +output weight_vecs_2_3_ce0; +input [15:0] weight_vecs_2_3_q0; +output [6:0] weight_vecs_3_0_address0; +output weight_vecs_3_0_ce0; +input [15:0] weight_vecs_3_0_q0; +output [6:0] weight_vecs_3_1_address0; +output weight_vecs_3_1_ce0; +input [15:0] weight_vecs_3_1_q0; +output [6:0] weight_vecs_3_2_address0; +output weight_vecs_3_2_ce0; +input [15:0] weight_vecs_3_2_q0; +output [6:0] weight_vecs_3_3_address0; +output weight_vecs_3_3_ce0; +input [15:0] weight_vecs_3_3_q0; +output [6:0] products_0_0_address0; +output products_0_0_ce0; +output products_0_0_we0; +output [15:0] products_0_0_d0; +output [6:0] products_0_1_address0; +output products_0_1_ce0; +output products_0_1_we0; +output [15:0] products_0_1_d0; +output [6:0] products_0_2_address0; +output products_0_2_ce0; +output products_0_2_we0; +output [15:0] products_0_2_d0; +output [6:0] products_0_3_address0; +output products_0_3_ce0; +output products_0_3_we0; +output [15:0] products_0_3_d0; +output [6:0] products_1_0_address0; +output products_1_0_ce0; +output products_1_0_we0; +output [15:0] products_1_0_d0; +output [6:0] products_1_1_address0; +output products_1_1_ce0; +output products_1_1_we0; +output [15:0] products_1_1_d0; +output [6:0] products_1_2_address0; +output products_1_2_ce0; +output products_1_2_we0; +output [15:0] products_1_2_d0; +output [6:0] products_1_3_address0; +output products_1_3_ce0; +output products_1_3_we0; +output [15:0] products_1_3_d0; +output [6:0] products_2_0_address0; +output products_2_0_ce0; +output products_2_0_we0; +output [15:0] products_2_0_d0; +output [6:0] products_2_1_address0; +output products_2_1_ce0; +output products_2_1_we0; +output [15:0] products_2_1_d0; +output [6:0] products_2_2_address0; +output products_2_2_ce0; +output products_2_2_we0; +output [15:0] products_2_2_d0; +output [6:0] products_2_3_address0; +output products_2_3_ce0; +output products_2_3_we0; +output [15:0] products_2_3_d0; +output [6:0] products_3_0_address0; +output products_3_0_ce0; +output products_3_0_we0; +output [15:0] products_3_0_d0; +output [6:0] products_3_1_address0; +output products_3_1_ce0; +output products_3_1_we0; +output [15:0] products_3_1_d0; +output [6:0] products_3_2_address0; +output products_3_2_ce0; +output products_3_2_we0; +output [15:0] products_3_2_d0; +output [6:0] products_3_3_address0; +output products_3_3_ce0; +output products_3_3_we0; +output [15:0] products_3_3_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_0_ce0; +reg ifmap_vec_1_ce0; +reg ifmap_vec_2_ce0; +reg ifmap_vec_3_ce0; +reg weight_vecs_0_0_ce0; +reg weight_vecs_0_1_ce0; +reg weight_vecs_0_2_ce0; +reg weight_vecs_0_3_ce0; +reg weight_vecs_1_0_ce0; +reg weight_vecs_1_1_ce0; +reg weight_vecs_1_2_ce0; +reg weight_vecs_1_3_ce0; +reg weight_vecs_2_0_ce0; +reg weight_vecs_2_1_ce0; +reg weight_vecs_2_2_ce0; +reg weight_vecs_2_3_ce0; +reg weight_vecs_3_0_ce0; +reg weight_vecs_3_1_ce0; +reg weight_vecs_3_2_ce0; +reg weight_vecs_3_3_ce0; +reg products_0_0_ce0; +reg products_0_0_we0; +reg products_0_1_ce0; +reg products_0_1_we0; +reg products_0_2_ce0; +reg products_0_2_we0; +reg products_0_3_ce0; +reg products_0_3_we0; +reg products_1_0_ce0; +reg products_1_0_we0; +reg products_1_1_ce0; +reg products_1_1_we0; +reg products_1_2_ce0; +reg products_1_2_we0; +reg products_1_3_ce0; +reg products_1_3_we0; +reg products_2_0_ce0; +reg products_2_0_we0; +reg products_2_1_ce0; +reg products_2_1_we0; +reg products_2_2_ce0; +reg products_2_2_we0; +reg products_2_3_ce0; +reg products_2_3_we0; +reg products_3_0_ce0; +reg products_3_0_we0; +reg products_3_1_ce0; +reg products_3_1_we0; +reg products_3_2_ce0; +reg products_3_2_we0; +reg products_3_3_ce0; +reg products_3_3_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [6:0] indvar_flatten17_reg_606; +reg [1:0] ii_reg_617; +reg [5:0] indvar_flatten_reg_628; +reg [1:0] jj_reg_639; +reg [5:0] ic_reg_650; +wire [6:0] add_ln147_2_fu_725_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln147_fu_759_p2; +reg [0:0] icmp_ln147_reg_1104; +reg [0:0] icmp_ln147_reg_1104_pp0_iter1_reg; +reg [0:0] icmp_ln147_reg_1104_pp0_iter2_reg; +reg [0:0] icmp_ln147_reg_1104_pp0_iter3_reg; +reg [0:0] icmp_ln147_reg_1104_pp0_iter4_reg; +reg [0:0] icmp_ln147_reg_1104_pp0_iter5_reg; +reg [0:0] icmp_ln147_reg_1104_pp0_iter6_reg; +reg [0:0] icmp_ln147_reg_1104_pp0_iter7_reg; +wire [1:0] select_ln147_7_fu_793_p3; +reg [1:0] select_ln147_7_reg_1108; +wire [1:0] select_ln148_4_fu_895_p3; +reg [1:0] select_ln148_4_reg_1113; +wire [5:0] empty_88_fu_907_p2; +reg [5:0] empty_88_reg_1118; +wire [3:0] select_ln148_5_fu_923_p3; +reg [3:0] select_ln148_5_reg_1123; +reg [3:0] select_ln148_5_reg_1123_pp0_iter1_reg; +reg [3:0] select_ln148_5_reg_1123_pp0_iter2_reg; +reg [3:0] select_ln148_5_reg_1123_pp0_iter3_reg; +reg [3:0] select_ln148_5_reg_1123_pp0_iter4_reg; +reg [3:0] select_ln148_5_reg_1123_pp0_iter5_reg; +reg [3:0] select_ln148_5_reg_1123_pp0_iter6_reg; +reg [3:0] select_ln148_5_reg_1123_pp0_iter7_reg; +wire [4:0] trunc_ln149_fu_931_p1; +reg [4:0] trunc_ln149_reg_1131; +reg [4:0] trunc_ln149_reg_1131_pp0_iter1_reg; +reg [4:0] trunc_ln149_reg_1131_pp0_iter2_reg; +reg [4:0] trunc_ln149_reg_1131_pp0_iter3_reg; +reg [4:0] trunc_ln149_reg_1131_pp0_iter4_reg; +reg [4:0] trunc_ln149_reg_1131_pp0_iter5_reg; +reg [4:0] trunc_ln149_reg_1131_pp0_iter6_reg; +reg [4:0] trunc_ln149_reg_1131_pp0_iter7_reg; +reg [2:0] newIndex_reg_1138; +reg [2:0] newIndex_reg_1138_pp0_iter1_reg; +reg [2:0] newIndex_reg_1138_pp0_iter2_reg; +reg [2:0] newIndex_reg_1138_pp0_iter3_reg; +reg [2:0] newIndex_reg_1138_pp0_iter4_reg; +reg [2:0] newIndex_reg_1138_pp0_iter5_reg; +reg [2:0] newIndex_reg_1138_pp0_iter6_reg; +reg [2:0] newIndex_reg_1138_pp0_iter7_reg; +wire [5:0] add_ln149_fu_945_p2; +wire [5:0] select_ln148_6_fu_957_p3; +reg [15:0] ifmap_vec_0_load_reg_1254; +reg [15:0] weight_vecs_0_0_load_reg_1262; +reg [15:0] weight_vecs_1_0_load_reg_1267; +reg [15:0] weight_vecs_2_0_load_reg_1272; +reg [15:0] weight_vecs_3_0_load_reg_1277; +reg [15:0] ifmap_vec_1_load_reg_1282; +reg [15:0] weight_vecs_0_1_load_reg_1290; +reg [15:0] weight_vecs_1_1_load_reg_1295; +reg [15:0] weight_vecs_2_1_load_reg_1300; +reg [15:0] weight_vecs_3_1_load_reg_1305; +reg [15:0] ifmap_vec_2_load_reg_1310; +reg [15:0] weight_vecs_0_2_load_reg_1318; +reg [15:0] weight_vecs_1_2_load_reg_1323; +reg [15:0] weight_vecs_2_2_load_reg_1328; +reg [15:0] weight_vecs_3_2_load_reg_1333; +reg [15:0] ifmap_vec_3_load_reg_1338; +reg [15:0] weight_vecs_0_3_load_reg_1346; +reg [15:0] weight_vecs_1_3_load_reg_1351; +reg [15:0] weight_vecs_2_3_load_reg_1356; +reg [15:0] weight_vecs_3_3_load_reg_1361; +wire [15:0] grp_fu_661_p2; +reg [15:0] mul_reg_1366; +wire [15:0] grp_fu_665_p2; +reg [15:0] mul_1_reg_1371; +wire [15:0] grp_fu_669_p2; +reg [15:0] mul_2_reg_1376; +wire [15:0] grp_fu_673_p2; +reg [15:0] mul_3_reg_1381; +wire [15:0] grp_fu_677_p2; +reg [15:0] mul27_1_reg_1386; +wire [15:0] grp_fu_681_p2; +reg [15:0] mul27_1_1_reg_1391; +wire [15:0] grp_fu_685_p2; +reg [15:0] mul27_1_2_reg_1396; +wire [15:0] grp_fu_689_p2; +reg [15:0] mul27_1_3_reg_1401; +wire [15:0] grp_fu_693_p2; +reg [15:0] mul27_2_reg_1406; +wire [15:0] grp_fu_697_p2; +reg [15:0] mul27_2_1_reg_1411; +wire [15:0] grp_fu_701_p2; +reg [15:0] mul27_2_2_reg_1416; +wire [15:0] grp_fu_705_p2; +reg [15:0] mul27_2_3_reg_1421; +wire [15:0] grp_fu_709_p2; +reg [15:0] mul27_3_reg_1426; +wire [15:0] grp_fu_713_p2; +reg [15:0] mul27_3_1_reg_1431; +wire [15:0] grp_fu_717_p2; +reg [15:0] mul27_3_2_reg_1436; +wire [15:0] grp_fu_721_p2; +reg [15:0] mul27_3_3_reg_1441; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg [1:0] ap_phi_mux_ii_phi_fu_621_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_643_p4; +wire [63:0] tmp_55_fu_971_p1; +wire [63:0] zext_ln153_fu_1001_p1; +wire [63:0] zext_ln153_2_fu_1031_p1; +wire [63:0] zext_ln153_3_fu_1061_p1; +wire [63:0] zext_ln153_4_fu_1091_p1; +wire [3:0] shl_ln_fu_735_p3; +wire [3:0] zext_ln150_fu_731_p1; +wire [3:0] sub_ln150_fu_743_p2; +wire [3:0] zext_ln150_2_fu_749_p1; +wire [0:0] icmp_ln148_fu_771_p2; +wire [1:0] add_ln147_fu_765_p2; +wire [3:0] tmp_fu_805_p3; +wire [4:0] tmp_cast_fu_813_p1; +wire [4:0] select_ln147_8_cast_fu_801_p1; +wire [4:0] empty_87_fu_817_p2; +wire [3:0] shl_ln150_mid1_fu_831_p3; +wire [3:0] zext_ln150_4_fu_827_p1; +wire [3:0] sub_ln150_2_fu_839_p2; +wire [3:0] add_ln150_fu_753_p2; +wire [0:0] tmp_28_fu_861_p3; +wire [0:0] xor_ln149_fu_869_p2; +wire [1:0] select_ln147_fu_777_p3; +wire [0:0] or_ln147_fu_875_p2; +wire [5:0] select_ln147_6_fu_785_p3; +wire [1:0] add_ln148_fu_881_p2; +wire [5:0] sext_ln150_fu_823_p1; +wire [5:0] select_ln148_5_cast_fu_903_p1; +wire [3:0] select_ln147_8_fu_845_p3; +wire [3:0] zext_ln150_5_fu_913_p1; +wire [3:0] select_ln147_9_fu_853_p3; +wire [3:0] add_ln150_2_fu_917_p2; +wire [5:0] select_ln148_fu_887_p3; +wire [5:0] add_ln148_2_fu_951_p2; +wire [8:0] tmp_29_fu_965_p3; +wire [6:0] lshr_ln_fu_995_p3; +wire [4:0] or_ln150_fu_1009_p2; +wire [2:0] tmp_s_fu_1014_p4; +wire [6:0] lshr_ln153_2_fu_1024_p3; +wire [4:0] or_ln150_1_fu_1039_p2; +wire [2:0] tmp_20_fu_1044_p4; +wire [6:0] lshr_ln153_3_fu_1054_p3; +wire [4:0] or_ln150_2_fu_1069_p2; +wire [2:0] tmp_21_fu_1074_p4; +wire [6:0] lshr_ln153_4_fu_1084_p3; +wire ap_CS_fsm_state11; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U976( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_1254), + .din1(weight_vecs_0_0_load_reg_1262), + .dout(grp_fu_661_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U977( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_1254), + .din1(weight_vecs_1_0_load_reg_1267), + .dout(grp_fu_665_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U978( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_1254), + .din1(weight_vecs_2_0_load_reg_1272), + .dout(grp_fu_669_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U979( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_1254), + .din1(weight_vecs_3_0_load_reg_1277), + .dout(grp_fu_673_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U980( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_1282), + .din1(weight_vecs_0_1_load_reg_1290), + .dout(grp_fu_677_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U981( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_1282), + .din1(weight_vecs_1_1_load_reg_1295), + .dout(grp_fu_681_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U982( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_1282), + .din1(weight_vecs_2_1_load_reg_1300), + .dout(grp_fu_685_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U983( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_1282), + .din1(weight_vecs_3_1_load_reg_1305), + .dout(grp_fu_689_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U984( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_2_load_reg_1310), + .din1(weight_vecs_0_2_load_reg_1318), + .dout(grp_fu_693_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U985( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_2_load_reg_1310), + .din1(weight_vecs_1_2_load_reg_1323), + .dout(grp_fu_697_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U986( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_2_load_reg_1310), + .din1(weight_vecs_2_2_load_reg_1328), + .dout(grp_fu_701_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U987( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_2_load_reg_1310), + .din1(weight_vecs_3_2_load_reg_1333), + .dout(grp_fu_705_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U988( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_3_load_reg_1338), + .din1(weight_vecs_0_3_load_reg_1346), + .dout(grp_fu_709_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U989( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_3_load_reg_1338), + .din1(weight_vecs_1_3_load_reg_1351), + .dout(grp_fu_713_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U990( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_3_load_reg_1338), + .din1(weight_vecs_2_3_load_reg_1356), + .dout(grp_fu_717_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U991( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_3_load_reg_1338), + .din1(weight_vecs_3_3_load_reg_1361), + .dout(grp_fu_721_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_759_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_reg_650 <= add_ln149_fu_945_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_reg_650 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_1104 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ii_reg_617 <= select_ln147_7_reg_1108; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_617 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_759_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten17_reg_606 <= add_ln147_2_fu_725_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten17_reg_606 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_759_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_628 <= select_ln148_6_fu_957_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_628 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_1104 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + jj_reg_639 <= select_ln148_4_reg_1113; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_639 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_759_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + empty_88_reg_1118 <= empty_88_fu_907_p2; + newIndex_reg_1138 <= {{select_ln148_fu_887_p3[4:2]}}; + select_ln148_5_reg_1123 <= select_ln148_5_fu_923_p3; + trunc_ln149_reg_1131 <= trunc_ln149_fu_931_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln147_reg_1104 <= icmp_ln147_fu_759_p2; + icmp_ln147_reg_1104_pp0_iter1_reg <= icmp_ln147_reg_1104; + newIndex_reg_1138_pp0_iter1_reg <= newIndex_reg_1138; + select_ln148_5_reg_1123_pp0_iter1_reg <= select_ln148_5_reg_1123; + trunc_ln149_reg_1131_pp0_iter1_reg <= trunc_ln149_reg_1131; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln147_reg_1104_pp0_iter2_reg <= icmp_ln147_reg_1104_pp0_iter1_reg; + icmp_ln147_reg_1104_pp0_iter3_reg <= icmp_ln147_reg_1104_pp0_iter2_reg; + icmp_ln147_reg_1104_pp0_iter4_reg <= icmp_ln147_reg_1104_pp0_iter3_reg; + icmp_ln147_reg_1104_pp0_iter5_reg <= icmp_ln147_reg_1104_pp0_iter4_reg; + icmp_ln147_reg_1104_pp0_iter6_reg <= icmp_ln147_reg_1104_pp0_iter5_reg; + icmp_ln147_reg_1104_pp0_iter7_reg <= icmp_ln147_reg_1104_pp0_iter6_reg; + newIndex_reg_1138_pp0_iter2_reg <= newIndex_reg_1138_pp0_iter1_reg; + newIndex_reg_1138_pp0_iter3_reg <= newIndex_reg_1138_pp0_iter2_reg; + newIndex_reg_1138_pp0_iter4_reg <= newIndex_reg_1138_pp0_iter3_reg; + newIndex_reg_1138_pp0_iter5_reg <= newIndex_reg_1138_pp0_iter4_reg; + newIndex_reg_1138_pp0_iter6_reg <= newIndex_reg_1138_pp0_iter5_reg; + newIndex_reg_1138_pp0_iter7_reg <= newIndex_reg_1138_pp0_iter6_reg; + select_ln148_5_reg_1123_pp0_iter2_reg <= select_ln148_5_reg_1123_pp0_iter1_reg; + select_ln148_5_reg_1123_pp0_iter3_reg <= select_ln148_5_reg_1123_pp0_iter2_reg; + select_ln148_5_reg_1123_pp0_iter4_reg <= select_ln148_5_reg_1123_pp0_iter3_reg; + select_ln148_5_reg_1123_pp0_iter5_reg <= select_ln148_5_reg_1123_pp0_iter4_reg; + select_ln148_5_reg_1123_pp0_iter6_reg <= select_ln148_5_reg_1123_pp0_iter5_reg; + select_ln148_5_reg_1123_pp0_iter7_reg <= select_ln148_5_reg_1123_pp0_iter6_reg; + trunc_ln149_reg_1131_pp0_iter2_reg <= trunc_ln149_reg_1131_pp0_iter1_reg; + trunc_ln149_reg_1131_pp0_iter3_reg <= trunc_ln149_reg_1131_pp0_iter2_reg; + trunc_ln149_reg_1131_pp0_iter4_reg <= trunc_ln149_reg_1131_pp0_iter3_reg; + trunc_ln149_reg_1131_pp0_iter5_reg <= trunc_ln149_reg_1131_pp0_iter4_reg; + trunc_ln149_reg_1131_pp0_iter6_reg <= trunc_ln149_reg_1131_pp0_iter5_reg; + trunc_ln149_reg_1131_pp0_iter7_reg <= trunc_ln149_reg_1131_pp0_iter6_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_1104_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_load_reg_1254 <= ifmap_vec_0_q0; + ifmap_vec_1_load_reg_1282 <= ifmap_vec_1_q0; + ifmap_vec_2_load_reg_1310 <= ifmap_vec_2_q0; + ifmap_vec_3_load_reg_1338 <= ifmap_vec_3_q0; + weight_vecs_0_0_load_reg_1262 <= weight_vecs_0_0_q0; + weight_vecs_0_1_load_reg_1290 <= weight_vecs_0_1_q0; + weight_vecs_0_2_load_reg_1318 <= weight_vecs_0_2_q0; + weight_vecs_0_3_load_reg_1346 <= weight_vecs_0_3_q0; + weight_vecs_1_0_load_reg_1267 <= weight_vecs_1_0_q0; + weight_vecs_1_1_load_reg_1295 <= weight_vecs_1_1_q0; + weight_vecs_1_2_load_reg_1323 <= weight_vecs_1_2_q0; + weight_vecs_1_3_load_reg_1351 <= weight_vecs_1_3_q0; + weight_vecs_2_0_load_reg_1272 <= weight_vecs_2_0_q0; + weight_vecs_2_1_load_reg_1300 <= weight_vecs_2_1_q0; + weight_vecs_2_2_load_reg_1328 <= weight_vecs_2_2_q0; + weight_vecs_2_3_load_reg_1356 <= weight_vecs_2_3_q0; + weight_vecs_3_0_load_reg_1277 <= weight_vecs_3_0_q0; + weight_vecs_3_1_load_reg_1305 <= weight_vecs_3_1_q0; + weight_vecs_3_2_load_reg_1333 <= weight_vecs_3_2_q0; + weight_vecs_3_3_load_reg_1361 <= weight_vecs_3_3_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_1104_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul27_1_1_reg_1391 <= grp_fu_681_p2; + mul27_1_2_reg_1396 <= grp_fu_685_p2; + mul27_1_3_reg_1401 <= grp_fu_689_p2; + mul27_1_reg_1386 <= grp_fu_677_p2; + mul27_2_1_reg_1411 <= grp_fu_697_p2; + mul27_2_2_reg_1416 <= grp_fu_701_p2; + mul27_2_3_reg_1421 <= grp_fu_705_p2; + mul27_2_reg_1406 <= grp_fu_693_p2; + mul27_3_1_reg_1431 <= grp_fu_713_p2; + mul27_3_2_reg_1436 <= grp_fu_717_p2; + mul27_3_3_reg_1441 <= grp_fu_721_p2; + mul27_3_reg_1426 <= grp_fu_709_p2; + mul_1_reg_1371 <= grp_fu_665_p2; + mul_2_reg_1376 <= grp_fu_669_p2; + mul_3_reg_1381 <= grp_fu_673_p2; + mul_reg_1366 <= grp_fu_661_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_759_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln147_7_reg_1108 <= select_ln147_7_fu_793_p3; + select_ln148_4_reg_1113 <= select_ln148_4_fu_895_p3; + end +end + +always @ (*) begin + if ((icmp_ln147_fu_759_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_1104 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_621_p4 = select_ln147_7_reg_1108; + end else begin + ap_phi_mux_ii_phi_fu_621_p4 = ii_reg_617; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_1104 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_643_p4 = select_ln148_4_reg_1113; + end else begin + ap_phi_mux_jj_phi_fu_643_p4 = jj_reg_639; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_1_ce0 = 1'b1; + end else begin + ifmap_vec_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_2_ce0 = 1'b1; + end else begin + ifmap_vec_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_3_ce0 = 1'b1; + end else begin + ifmap_vec_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_0_ce0 = 1'b1; + end else begin + products_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_0_we0 = 1'b1; + end else begin + products_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_1_ce0 = 1'b1; + end else begin + products_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_1_we0 = 1'b1; + end else begin + products_0_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_2_ce0 = 1'b1; + end else begin + products_0_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_2_we0 = 1'b1; + end else begin + products_0_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_3_ce0 = 1'b1; + end else begin + products_0_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_3_we0 = 1'b1; + end else begin + products_0_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_0_ce0 = 1'b1; + end else begin + products_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_0_we0 = 1'b1; + end else begin + products_1_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_1_ce0 = 1'b1; + end else begin + products_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_1_we0 = 1'b1; + end else begin + products_1_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_2_ce0 = 1'b1; + end else begin + products_1_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_2_we0 = 1'b1; + end else begin + products_1_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_3_ce0 = 1'b1; + end else begin + products_1_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_3_we0 = 1'b1; + end else begin + products_1_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_0_ce0 = 1'b1; + end else begin + products_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_0_we0 = 1'b1; + end else begin + products_2_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_1_ce0 = 1'b1; + end else begin + products_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_1_we0 = 1'b1; + end else begin + products_2_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_2_ce0 = 1'b1; + end else begin + products_2_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_2_we0 = 1'b1; + end else begin + products_2_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_3_ce0 = 1'b1; + end else begin + products_2_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_3_we0 = 1'b1; + end else begin + products_2_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_0_ce0 = 1'b1; + end else begin + products_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_0_we0 = 1'b1; + end else begin + products_3_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_1_ce0 = 1'b1; + end else begin + products_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_1_we0 = 1'b1; + end else begin + products_3_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_2_ce0 = 1'b1; + end else begin + products_3_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_2_we0 = 1'b1; + end else begin + products_3_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_3_ce0 = 1'b1; + end else begin + products_3_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_1104_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_3_we0 = 1'b1; + end else begin + products_3_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_1_ce0 = 1'b1; + end else begin + weight_vecs_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_2_ce0 = 1'b1; + end else begin + weight_vecs_0_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_3_ce0 = 1'b1; + end else begin + weight_vecs_0_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_1_0_ce0 = 1'b1; + end else begin + weight_vecs_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_1_1_ce0 = 1'b1; + end else begin + weight_vecs_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_1_2_ce0 = 1'b1; + end else begin + weight_vecs_1_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_1_3_ce0 = 1'b1; + end else begin + weight_vecs_1_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_2_0_ce0 = 1'b1; + end else begin + weight_vecs_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_2_1_ce0 = 1'b1; + end else begin + weight_vecs_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_2_2_ce0 = 1'b1; + end else begin + weight_vecs_2_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_2_3_ce0 = 1'b1; + end else begin + weight_vecs_2_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_3_0_ce0 = 1'b1; + end else begin + weight_vecs_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_3_1_ce0 = 1'b1; + end else begin + weight_vecs_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_3_2_ce0 = 1'b1; + end else begin + weight_vecs_3_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_3_3_ce0 = 1'b1; + end else begin + weight_vecs_3_3_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln147_fu_759_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter8 == 1'b1) & (ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter8 == 1'b1) & (ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln147_fu_759_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state11; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_2_fu_725_p2 = (indvar_flatten17_reg_606 + 7'd1); + +assign add_ln147_fu_765_p2 = (ap_phi_mux_ii_phi_fu_621_p4 + 2'd1); + +assign add_ln148_2_fu_951_p2 = (indvar_flatten_reg_628 + 6'd1); + +assign add_ln148_fu_881_p2 = (select_ln147_fu_777_p3 + 2'd1); + +assign add_ln149_fu_945_p2 = (select_ln148_fu_887_p3 + 6'd4); + +assign add_ln150_2_fu_917_p2 = (select_ln147_8_fu_845_p3 + zext_ln150_5_fu_913_p1); + +assign add_ln150_fu_753_p2 = (sub_ln150_fu_743_p2 + zext_ln150_2_fu_749_p1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign empty_87_fu_817_p2 = (tmp_cast_fu_813_p1 - select_ln147_8_cast_fu_801_p1); + +assign empty_88_fu_907_p2 = ((sext_ln150_fu_823_p1) + (select_ln148_5_cast_fu_903_p1)); + +assign icmp_ln147_fu_759_p2 = ((indvar_flatten17_reg_606 == 7'd72) ? 1'b1 : 1'b0); + +assign icmp_ln148_fu_771_p2 = ((indvar_flatten_reg_628 == 6'd24) ? 1'b1 : 1'b0); + +assign ifmap_vec_0_address0 = tmp_55_fu_971_p1; + +assign ifmap_vec_1_address0 = tmp_55_fu_971_p1; + +assign ifmap_vec_2_address0 = tmp_55_fu_971_p1; + +assign ifmap_vec_3_address0 = tmp_55_fu_971_p1; + +assign lshr_ln153_2_fu_1024_p3 = {{select_ln148_5_reg_1123_pp0_iter7_reg}, {tmp_s_fu_1014_p4}}; + +assign lshr_ln153_3_fu_1054_p3 = {{select_ln148_5_reg_1123_pp0_iter7_reg}, {tmp_20_fu_1044_p4}}; + +assign lshr_ln153_4_fu_1084_p3 = {{select_ln148_5_reg_1123_pp0_iter7_reg}, {tmp_21_fu_1074_p4}}; + +assign lshr_ln_fu_995_p3 = {{select_ln148_5_reg_1123_pp0_iter7_reg}, {newIndex_reg_1138_pp0_iter7_reg}}; + +assign or_ln147_fu_875_p2 = (xor_ln149_fu_869_p2 | icmp_ln148_fu_771_p2); + +assign or_ln150_1_fu_1039_p2 = (trunc_ln149_reg_1131_pp0_iter7_reg | 5'd2); + +assign or_ln150_2_fu_1069_p2 = (trunc_ln149_reg_1131_pp0_iter7_reg | 5'd3); + +assign or_ln150_fu_1009_p2 = (trunc_ln149_reg_1131_pp0_iter7_reg | 5'd1); + +assign products_0_0_address0 = zext_ln153_fu_1001_p1; + +assign products_0_0_d0 = mul_reg_1366; + +assign products_0_1_address0 = zext_ln153_2_fu_1031_p1; + +assign products_0_1_d0 = mul27_1_reg_1386; + +assign products_0_2_address0 = zext_ln153_3_fu_1061_p1; + +assign products_0_2_d0 = mul27_2_reg_1406; + +assign products_0_3_address0 = zext_ln153_4_fu_1091_p1; + +assign products_0_3_d0 = mul27_3_reg_1426; + +assign products_1_0_address0 = zext_ln153_fu_1001_p1; + +assign products_1_0_d0 = mul_1_reg_1371; + +assign products_1_1_address0 = zext_ln153_2_fu_1031_p1; + +assign products_1_1_d0 = mul27_1_1_reg_1391; + +assign products_1_2_address0 = zext_ln153_3_fu_1061_p1; + +assign products_1_2_d0 = mul27_2_1_reg_1411; + +assign products_1_3_address0 = zext_ln153_4_fu_1091_p1; + +assign products_1_3_d0 = mul27_3_1_reg_1431; + +assign products_2_0_address0 = zext_ln153_fu_1001_p1; + +assign products_2_0_d0 = mul_2_reg_1376; + +assign products_2_1_address0 = zext_ln153_2_fu_1031_p1; + +assign products_2_1_d0 = mul27_1_2_reg_1396; + +assign products_2_2_address0 = zext_ln153_3_fu_1061_p1; + +assign products_2_2_d0 = mul27_2_2_reg_1416; + +assign products_2_3_address0 = zext_ln153_4_fu_1091_p1; + +assign products_2_3_d0 = mul27_3_2_reg_1436; + +assign products_3_0_address0 = zext_ln153_fu_1001_p1; + +assign products_3_0_d0 = mul_3_reg_1381; + +assign products_3_1_address0 = zext_ln153_2_fu_1031_p1; + +assign products_3_1_d0 = mul27_1_3_reg_1401; + +assign products_3_2_address0 = zext_ln153_3_fu_1061_p1; + +assign products_3_2_d0 = mul27_2_3_reg_1421; + +assign products_3_3_address0 = zext_ln153_4_fu_1091_p1; + +assign products_3_3_d0 = mul27_3_3_reg_1441; + +assign select_ln147_6_fu_785_p3 = ((icmp_ln148_fu_771_p2[0:0] == 1'b1) ? 6'd0 : ic_reg_650); + +assign select_ln147_7_fu_793_p3 = ((icmp_ln148_fu_771_p2[0:0] == 1'b1) ? add_ln147_fu_765_p2 : ap_phi_mux_ii_phi_fu_621_p4); + +assign select_ln147_8_cast_fu_801_p1 = select_ln147_7_fu_793_p3; + +assign select_ln147_8_fu_845_p3 = ((icmp_ln148_fu_771_p2[0:0] == 1'b1) ? sub_ln150_2_fu_839_p2 : sub_ln150_fu_743_p2); + +assign select_ln147_9_fu_853_p3 = ((icmp_ln148_fu_771_p2[0:0] == 1'b1) ? sub_ln150_2_fu_839_p2 : add_ln150_fu_753_p2); + +assign select_ln147_fu_777_p3 = ((icmp_ln148_fu_771_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_643_p4); + +assign select_ln148_4_fu_895_p3 = ((or_ln147_fu_875_p2[0:0] == 1'b1) ? select_ln147_fu_777_p3 : add_ln148_fu_881_p2); + +assign select_ln148_5_cast_fu_903_p1 = select_ln148_4_fu_895_p3; + +assign select_ln148_5_fu_923_p3 = ((or_ln147_fu_875_p2[0:0] == 1'b1) ? select_ln147_9_fu_853_p3 : add_ln150_2_fu_917_p2); + +assign select_ln148_6_fu_957_p3 = ((icmp_ln148_fu_771_p2[0:0] == 1'b1) ? 6'd1 : add_ln148_2_fu_951_p2); + +assign select_ln148_fu_887_p3 = ((or_ln147_fu_875_p2[0:0] == 1'b1) ? select_ln147_6_fu_785_p3 : 6'd0); + +assign sext_ln150_fu_823_p1 = (empty_87_fu_817_p2); + +assign shl_ln150_mid1_fu_831_p3 = {{add_ln147_fu_765_p2}, {2'd0}}; + +assign shl_ln_fu_735_p3 = {{ap_phi_mux_ii_phi_fu_621_p4}, {2'd0}}; + +assign sub_ln150_2_fu_839_p2 = (shl_ln150_mid1_fu_831_p3 - zext_ln150_4_fu_827_p1); + +assign sub_ln150_fu_743_p2 = (shl_ln_fu_735_p3 - zext_ln150_fu_731_p1); + +assign tmp_20_fu_1044_p4 = {{or_ln150_1_fu_1039_p2[4:2]}}; + +assign tmp_21_fu_1074_p4 = {{or_ln150_2_fu_1069_p2[4:2]}}; + +assign tmp_28_fu_861_p3 = ic_reg_650[32'd5]; + +assign tmp_29_fu_965_p3 = {{empty_88_reg_1118}, {newIndex_reg_1138}}; + +assign tmp_55_fu_971_p1 = (tmp_29_fu_965_p3); + +assign tmp_cast_fu_813_p1 = tmp_fu_805_p3; + +assign tmp_fu_805_p3 = {{select_ln147_7_fu_793_p3}, {2'd0}}; + +assign tmp_s_fu_1014_p4 = {{or_ln150_fu_1009_p2[4:2]}}; + +assign trunc_ln149_fu_931_p1 = select_ln148_fu_887_p3[4:0]; + +assign weight_vecs_0_0_address0 = tmp_55_fu_971_p1; + +assign weight_vecs_0_1_address0 = tmp_55_fu_971_p1; + +assign weight_vecs_0_2_address0 = tmp_55_fu_971_p1; + +assign weight_vecs_0_3_address0 = tmp_55_fu_971_p1; + +assign weight_vecs_1_0_address0 = tmp_55_fu_971_p1; + +assign weight_vecs_1_1_address0 = tmp_55_fu_971_p1; + +assign weight_vecs_1_2_address0 = tmp_55_fu_971_p1; + +assign weight_vecs_1_3_address0 = tmp_55_fu_971_p1; + +assign weight_vecs_2_0_address0 = tmp_55_fu_971_p1; + +assign weight_vecs_2_1_address0 = tmp_55_fu_971_p1; + +assign weight_vecs_2_2_address0 = tmp_55_fu_971_p1; + +assign weight_vecs_2_3_address0 = tmp_55_fu_971_p1; + +assign weight_vecs_3_0_address0 = tmp_55_fu_971_p1; + +assign weight_vecs_3_1_address0 = tmp_55_fu_971_p1; + +assign weight_vecs_3_2_address0 = tmp_55_fu_971_p1; + +assign weight_vecs_3_3_address0 = tmp_55_fu_971_p1; + +assign xor_ln149_fu_869_p2 = (tmp_28_fu_861_p3 ^ 1'd1); + +assign zext_ln150_2_fu_749_p1 = ap_phi_mux_jj_phi_fu_643_p4; + +assign zext_ln150_4_fu_827_p1 = add_ln147_fu_765_p2; + +assign zext_ln150_5_fu_913_p1 = add_ln148_fu_881_p2; + +assign zext_ln150_fu_731_p1 = ap_phi_mux_ii_phi_fu_621_p4; + +assign zext_ln153_2_fu_1031_p1 = lshr_ln153_2_fu_1024_p3; + +assign zext_ln153_3_fu_1061_p1 = lshr_ln153_3_fu_1054_p3; + +assign zext_ln153_4_fu_1091_p1 = lshr_ln153_4_fu_1084_p3; + +assign zext_ln153_fu_1001_p1 = lshr_ln_fu_995_p3; + +endmodule //td_fused_top_tdf7_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_filters_0_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 13; +parameter MEM_SIZE = 4608; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_filters_0( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd4608; +parameter AddressWidth = 32'd13; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf7_filters_0_ram td_fused_top_tdf7_filters_0_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + module td_fused_top_tdf7_filters_1_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 13; +parameter MEM_SIZE = 4608; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf7_filters_1_rom.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_filters_1( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd4608; +parameter AddressWidth = 32'd13; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +td_fused_top_tdf7_filters_1_rom td_fused_top_tdf7_filters_1_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + indices_2_out_din, + indices_2_out_full_n, + indices_2_out_write, + indices_2_out1_din, + indices_2_out1_full_n, + indices_2_out1_write, + write_r_din, + write_r_full_n, + write_r_write +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [5:0] indices_2_out_din; +input indices_2_out_full_n; +output indices_2_out_write; +output [5:0] indices_2_out1_din; +input indices_2_out1_full_n; +output indices_2_out1_write; +output write_r_din; +input write_r_full_n; +output write_r_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg indices_0_write; +reg indices_1_write; +reg indices_2_out_write; +reg indices_2_out1_write; +reg write_r_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [15:0] i_11; +reg [15:0] j_11; +reg [15:0] k_11; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg indices_2_out_blk_n; +reg indices_2_out1_blk_n; +reg write_r_blk_n; +reg [0:0] ap_phi_mux_j_18_flag_0_i_phi_fu_90_p6; +reg ap_block_state1; +wire [0:0] icmp_ln227_fu_161_p2; +wire [0:0] icmp_ln230_fu_174_p2; +reg [15:0] ap_phi_mux_j_18_new_0_i_phi_fu_104_p6; +wire [15:0] add_ln229_fu_167_p2; +reg [15:0] ap_phi_mux_k_18_new_0_i_phi_fu_117_p6; +wire [15:0] add_ln226_fu_154_p2; +wire [15:0] select_ln233_fu_192_p3; +wire [5:0] trunc_ln224_fu_141_p1; +wire [15:0] add_ln232_fu_180_p2; +wire [0:0] icmp_ln233_fu_186_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_11 = 16'd0; +#0 j_11 = 16'd0; +#0 k_11 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln230_fu_174_p2 == 1'd1) & (icmp_ln227_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_11 <= select_ln233_fu_192_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_18_flag_0_i_phi_fu_90_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j_11 <= ap_phi_mux_j_18_new_0_i_phi_fu_104_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k_11 <= ap_phi_mux_k_18_new_0_i_phi_fu_117_p6; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln227_fu_161_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_18_flag_0_i_phi_fu_90_p6 = 1'd0; + end else if ((((icmp_ln230_fu_174_p2 == 1'd0) & (icmp_ln227_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln230_fu_174_p2 == 1'd1) & (icmp_ln227_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_18_flag_0_i_phi_fu_90_p6 = 1'd1; + end else begin + ap_phi_mux_j_18_flag_0_i_phi_fu_90_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln227_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln230_fu_174_p2 == 1'd0)) begin + ap_phi_mux_j_18_new_0_i_phi_fu_104_p6 = add_ln229_fu_167_p2; + end else if ((icmp_ln230_fu_174_p2 == 1'd1)) begin + ap_phi_mux_j_18_new_0_i_phi_fu_104_p6 = 16'd0; + end else begin + ap_phi_mux_j_18_new_0_i_phi_fu_104_p6 = 'bx; + end + end else begin + ap_phi_mux_j_18_new_0_i_phi_fu_104_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln227_fu_161_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_18_new_0_i_phi_fu_117_p6 = add_ln226_fu_154_p2; + end else if ((((icmp_ln230_fu_174_p2 == 1'd0) & (icmp_ln227_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln230_fu_174_p2 == 1'd1) & (icmp_ln227_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_18_new_0_i_phi_fu_117_p6 = 16'd0; + end else begin + ap_phi_mux_k_18_new_0_i_phi_fu_117_p6 = 'bx; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_blk_n = indices_2_out1_full_n; + end else begin + indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_write = 1'b1; + end else begin + indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_blk_n = indices_2_out_full_n; + end else begin + indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_write = 1'b1; + end else begin + indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_r_blk_n = write_r_full_n; + end else begin + write_r_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_r_write = 1'b1; + end else begin + write_r_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln226_fu_154_p2 = (k_11 + 16'd1); + +assign add_ln229_fu_167_p2 = (j_11 + 16'd1); + +assign add_ln232_fu_180_p2 = (i_11 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign icmp_ln227_fu_161_p2 = ((add_ln226_fu_154_p2 == 16'd64) ? 1'b1 : 1'b0); + +assign icmp_ln230_fu_174_p2 = ((add_ln229_fu_167_p2 == 16'd28) ? 1'b1 : 1'b0); + +assign icmp_ln233_fu_186_p2 = ((add_ln232_fu_180_p2 == 16'd28) ? 1'b1 : 1'b0); + +assign indices_0_din = i_11; + +assign indices_1_din = j_11; + +assign indices_2_out1_din = trunc_ln224_fu_141_p1; + +assign indices_2_out_din = trunc_ln224_fu_141_p1; + +assign select_ln233_fu_192_p3 = ((icmp_ln233_fu_186_p2[0:0] == 1'b1) ? 16'd0 : add_ln232_fu_180_p2); + +assign start_out = real_start; + +assign trunc_ln224_fu_141_p1 = k_11[5:0]; + +assign write_r_din = ((k_11 == 16'd63) ? 1'b1 : 1'b0); + +endmodule //td_fused_top_tdf7_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_l2_accum ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + l2_products_0_address0, + l2_products_0_ce0, + l2_products_0_q0, + l2_products_0_address1, + l2_products_0_ce1, + l2_products_0_q1, + l2_products_1_address0, + l2_products_1_ce0, + l2_products_1_q0, + l2_products_1_address1, + l2_products_1_ce1, + l2_products_1_q1, + l2_products_2_address0, + l2_products_2_ce0, + l2_products_2_q0, + l2_products_2_address1, + l2_products_2_ce1, + l2_products_2_q1, + l2_products_3_address0, + l2_products_3_ce0, + l2_products_3_q0, + l2_products_3_address1, + l2_products_3_ce1, + l2_products_3_q1, + l2_partial_sums_0_address0, + l2_partial_sums_0_ce0, + l2_partial_sums_0_we0, + l2_partial_sums_0_d0, + l2_partial_sums_0_address1, + l2_partial_sums_0_ce1, + l2_partial_sums_0_we1, + l2_partial_sums_0_d1, + l2_partial_sums_1_address0, + l2_partial_sums_1_ce0, + l2_partial_sums_1_we0, + l2_partial_sums_1_d0, + l2_partial_sums_1_address1, + l2_partial_sums_1_ce1, + l2_partial_sums_1_we1, + l2_partial_sums_1_d1, + l2_partial_sums_2_address0, + l2_partial_sums_2_ce0, + l2_partial_sums_2_we0, + l2_partial_sums_2_d0, + l2_partial_sums_2_address1, + l2_partial_sums_2_ce1, + l2_partial_sums_2_we1, + l2_partial_sums_2_d1, + l2_partial_sums_3_address0, + l2_partial_sums_3_ce0, + l2_partial_sums_3_we0, + l2_partial_sums_3_d0, + l2_partial_sums_3_address1, + l2_partial_sums_3_ce1, + l2_partial_sums_3_we1, + l2_partial_sums_3_d1 +); + +parameter ap_ST_fsm_state1 = 12'd1; +parameter ap_ST_fsm_state2 = 12'd2; +parameter ap_ST_fsm_state3 = 12'd4; +parameter ap_ST_fsm_state4 = 12'd8; +parameter ap_ST_fsm_state5 = 12'd16; +parameter ap_ST_fsm_state6 = 12'd32; +parameter ap_ST_fsm_state7 = 12'd64; +parameter ap_ST_fsm_state8 = 12'd128; +parameter ap_ST_fsm_state9 = 12'd256; +parameter ap_ST_fsm_state10 = 12'd512; +parameter ap_ST_fsm_state11 = 12'd1024; +parameter ap_ST_fsm_state12 = 12'd2048; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [4:0] l2_products_0_address0; +output l2_products_0_ce0; +input [15:0] l2_products_0_q0; +output [4:0] l2_products_0_address1; +output l2_products_0_ce1; +input [15:0] l2_products_0_q1; +output [4:0] l2_products_1_address0; +output l2_products_1_ce0; +input [15:0] l2_products_1_q0; +output [4:0] l2_products_1_address1; +output l2_products_1_ce1; +input [15:0] l2_products_1_q1; +output [4:0] l2_products_2_address0; +output l2_products_2_ce0; +input [15:0] l2_products_2_q0; +output [4:0] l2_products_2_address1; +output l2_products_2_ce1; +input [15:0] l2_products_2_q1; +output [4:0] l2_products_3_address0; +output l2_products_3_ce0; +input [15:0] l2_products_3_q0; +output [4:0] l2_products_3_address1; +output l2_products_3_ce1; +input [15:0] l2_products_3_q1; +output [2:0] l2_partial_sums_0_address0; +output l2_partial_sums_0_ce0; +output l2_partial_sums_0_we0; +output [15:0] l2_partial_sums_0_d0; +output [2:0] l2_partial_sums_0_address1; +output l2_partial_sums_0_ce1; +output l2_partial_sums_0_we1; +output [15:0] l2_partial_sums_0_d1; +output [2:0] l2_partial_sums_1_address0; +output l2_partial_sums_1_ce0; +output l2_partial_sums_1_we0; +output [15:0] l2_partial_sums_1_d0; +output [2:0] l2_partial_sums_1_address1; +output l2_partial_sums_1_ce1; +output l2_partial_sums_1_we1; +output [15:0] l2_partial_sums_1_d1; +output [2:0] l2_partial_sums_2_address0; +output l2_partial_sums_2_ce0; +output l2_partial_sums_2_we0; +output [15:0] l2_partial_sums_2_d0; +output [2:0] l2_partial_sums_2_address1; +output l2_partial_sums_2_ce1; +output l2_partial_sums_2_we1; +output [15:0] l2_partial_sums_2_d1; +output [2:0] l2_partial_sums_3_address0; +output l2_partial_sums_3_ce0; +output l2_partial_sums_3_we0; +output [15:0] l2_partial_sums_3_d0; +output [2:0] l2_partial_sums_3_address1; +output l2_partial_sums_3_ce1; +output l2_partial_sums_3_we1; +output [15:0] l2_partial_sums_3_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg l2_products_0_ce0; +reg l2_products_0_ce1; +reg l2_products_1_ce0; +reg l2_products_1_ce1; +reg l2_products_2_ce0; +reg l2_products_2_ce1; +reg l2_products_3_ce0; +reg l2_products_3_ce1; +reg l2_partial_sums_0_ce0; +reg l2_partial_sums_0_we0; +reg l2_partial_sums_0_ce1; +reg l2_partial_sums_0_we1; +reg l2_partial_sums_1_ce0; +reg l2_partial_sums_1_we0; +reg l2_partial_sums_1_ce1; +reg l2_partial_sums_1_we1; +reg l2_partial_sums_2_ce0; +reg l2_partial_sums_2_we0; +reg l2_partial_sums_2_ce1; +reg l2_partial_sums_2_we1; +reg l2_partial_sums_3_ce0; +reg l2_partial_sums_3_we0; +reg l2_partial_sums_3_ce1; +reg l2_partial_sums_3_we1; + +reg ap_done_reg; + reg [11:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [2:0] add_ln40_fu_376_p2; +reg [2:0] add_ln40_reg_544; +wire ap_CS_fsm_state2; +wire [1:0] trunc_ln52_fu_388_p1; +reg [1:0] trunc_ln52_reg_552; +wire [0:0] icmp_ln40_fu_382_p2; +wire [2:0] out_idx_1_fu_398_p2; +reg [2:0] out_idx_1_reg_557; +wire [63:0] zext_ln54_fu_404_p1; +reg [63:0] zext_ln54_reg_562; +wire [63:0] zext_ln54_1_fu_408_p1; +reg [63:0] zext_ln54_1_reg_570; +wire [2:0] add_ln45_fu_412_p2; +reg [2:0] add_ln45_reg_578; +wire ap_CS_fsm_state3; +reg [15:0] l2_products_0_load_reg_626; +wire ap_CS_fsm_state4; +reg [15:0] l2_products_1_load_reg_631; +reg [15:0] l2_products_2_load_reg_636; +reg [15:0] l2_products_3_load_reg_641; +reg [15:0] l2_products_0_load_1_reg_646; +reg [15:0] l2_products_1_load_1_reg_651; +reg [15:0] l2_products_2_load_1_reg_656; +reg [15:0] l2_products_3_load_1_reg_661; +wire ap_CS_fsm_state5; +reg [2:0] group_reg_282; +wire [0:0] icmp_ln45_fu_450_p2; +reg ap_block_state1; +reg [2:0] i_1_1_reg_293; +wire ap_CS_fsm_state12; +wire [63:0] zext_ln54_2_fu_427_p1; +wire [63:0] zext_ln54_3_fu_442_p1; +reg [15:0] add14_lcssa15_fu_50; +wire [15:0] grp_fu_304_p2; +reg [15:0] add14_1_lcssa17_fu_54; +wire [15:0] grp_fu_308_p2; +reg [15:0] add14_2_lcssa19_fu_58; +wire [15:0] grp_fu_312_p2; +reg [15:0] add14_3_lcssa21_fu_62; +wire [15:0] grp_fu_316_p2; +reg [15:0] add14_4_lcssa23_fu_66; +wire [15:0] grp_fu_320_p2; +reg [15:0] add14_5_lcssa25_fu_70; +wire [15:0] grp_fu_324_p2; +reg [15:0] add14_6_lcssa27_fu_74; +wire [15:0] grp_fu_328_p2; +reg [15:0] add14_7_lcssa29_fu_78; +wire [15:0] grp_fu_332_p2; +wire [2:0] out_idx_fu_392_p2; +wire [5:0] tmp_s_fu_418_p4; +wire [5:0] tmp_19_fu_435_p3; +reg [11:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 12'd1; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1089( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_lcssa15_fu_50), + .din1(l2_products_0_load_reg_626), + .dout(grp_fu_304_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1090( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_1_lcssa17_fu_54), + .din1(l2_products_1_load_reg_631), + .dout(grp_fu_308_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1091( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_2_lcssa19_fu_58), + .din1(l2_products_2_load_reg_636), + .dout(grp_fu_312_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1092( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_3_lcssa21_fu_62), + .din1(l2_products_3_load_reg_641), + .dout(grp_fu_316_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1093( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_4_lcssa23_fu_66), + .din1(l2_products_0_load_1_reg_646), + .dout(grp_fu_320_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1094( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_5_lcssa25_fu_70), + .din1(l2_products_1_load_1_reg_651), + .dout(grp_fu_324_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1095( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_6_lcssa27_fu_74), + .din1(l2_products_2_load_1_reg_656), + .dout(grp_fu_328_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1096( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(add14_7_lcssa29_fu_78), + .din1(l2_products_3_load_1_reg_661), + .dout(grp_fu_332_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((1'b1 == ap_CS_fsm_state2) & (icmp_ln40_fu_382_p2 == 1'd1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + group_reg_282 <= 3'd0; + end else if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_450_p2 == 1'd1))) begin + group_reg_282 <= add_ln40_reg_544; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + i_1_1_reg_293 <= add_ln45_reg_578; + end else if (((1'b1 == ap_CS_fsm_state2) & (icmp_ln40_fu_382_p2 == 1'd0))) begin + i_1_1_reg_293 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + add14_1_lcssa17_fu_54 <= grp_fu_308_p2; + add14_2_lcssa19_fu_58 <= grp_fu_312_p2; + add14_3_lcssa21_fu_62 <= grp_fu_316_p2; + add14_4_lcssa23_fu_66 <= grp_fu_320_p2; + add14_5_lcssa25_fu_70 <= grp_fu_324_p2; + add14_6_lcssa27_fu_74 <= grp_fu_328_p2; + add14_7_lcssa29_fu_78 <= grp_fu_332_p2; + add14_lcssa15_fu_50 <= grp_fu_304_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln40_reg_544 <= add_ln40_fu_376_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + add_ln45_reg_578 <= add_ln45_fu_412_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + l2_products_0_load_1_reg_646 <= l2_products_0_q0; + l2_products_0_load_reg_626 <= l2_products_0_q1; + l2_products_1_load_1_reg_651 <= l2_products_1_q0; + l2_products_1_load_reg_631 <= l2_products_1_q1; + l2_products_2_load_1_reg_656 <= l2_products_2_q0; + l2_products_2_load_reg_636 <= l2_products_2_q1; + l2_products_3_load_1_reg_661 <= l2_products_3_q0; + l2_products_3_load_reg_641 <= l2_products_3_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_state2) & (icmp_ln40_fu_382_p2 == 1'd0))) begin + out_idx_1_reg_557[2 : 1] <= out_idx_1_fu_398_p2[2 : 1]; + trunc_ln52_reg_552 <= trunc_ln52_fu_388_p1; + zext_ln54_1_reg_570[2 : 1] <= zext_ln54_1_fu_408_p1[2 : 1]; + zext_ln54_reg_562[2 : 1] <= zext_ln54_fu_404_p1[2 : 1]; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) & (icmp_ln40_fu_382_p2 == 1'd1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) & (icmp_ln40_fu_382_p2 == 1'd1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_0_ce0 = 1'b1; + end else begin + l2_partial_sums_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_0_ce1 = 1'b1; + end else begin + l2_partial_sums_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_450_p2 == 1'd1))) begin + l2_partial_sums_0_we0 = 1'b1; + end else begin + l2_partial_sums_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_450_p2 == 1'd1))) begin + l2_partial_sums_0_we1 = 1'b1; + end else begin + l2_partial_sums_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_1_ce0 = 1'b1; + end else begin + l2_partial_sums_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_1_ce1 = 1'b1; + end else begin + l2_partial_sums_1_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_450_p2 == 1'd1))) begin + l2_partial_sums_1_we0 = 1'b1; + end else begin + l2_partial_sums_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_450_p2 == 1'd1))) begin + l2_partial_sums_1_we1 = 1'b1; + end else begin + l2_partial_sums_1_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_2_ce0 = 1'b1; + end else begin + l2_partial_sums_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_2_ce1 = 1'b1; + end else begin + l2_partial_sums_2_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_450_p2 == 1'd1))) begin + l2_partial_sums_2_we0 = 1'b1; + end else begin + l2_partial_sums_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_450_p2 == 1'd1))) begin + l2_partial_sums_2_we1 = 1'b1; + end else begin + l2_partial_sums_2_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_3_ce0 = 1'b1; + end else begin + l2_partial_sums_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_partial_sums_3_ce1 = 1'b1; + end else begin + l2_partial_sums_3_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_450_p2 == 1'd1))) begin + l2_partial_sums_3_we0 = 1'b1; + end else begin + l2_partial_sums_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_450_p2 == 1'd1))) begin + l2_partial_sums_3_we1 = 1'b1; + end else begin + l2_partial_sums_3_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_0_ce0 = 1'b1; + end else begin + l2_products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_0_ce1 = 1'b1; + end else begin + l2_products_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_1_ce0 = 1'b1; + end else begin + l2_products_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_1_ce1 = 1'b1; + end else begin + l2_products_1_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_2_ce0 = 1'b1; + end else begin + l2_products_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_2_ce1 = 1'b1; + end else begin + l2_products_2_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_3_ce0 = 1'b1; + end else begin + l2_products_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + l2_products_3_ce1 = 1'b1; + end else begin + l2_products_3_ce1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((1'b1 == ap_CS_fsm_state2) & (icmp_ln40_fu_382_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln45_fu_450_p2 == 1'd1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln40_fu_376_p2 = (group_reg_282 + 3'd1); + +assign add_ln45_fu_412_p2 = (i_1_1_reg_293 + 3'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln40_fu_382_p2 = ((group_reg_282 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln45_fu_450_p2 = ((i_1_1_reg_293 == 3'd4) ? 1'b1 : 1'b0); + +assign l2_partial_sums_0_address0 = zext_ln54_1_reg_570; + +assign l2_partial_sums_0_address1 = zext_ln54_reg_562; + +assign l2_partial_sums_0_d0 = add14_4_lcssa23_fu_66; + +assign l2_partial_sums_0_d1 = add14_lcssa15_fu_50; + +assign l2_partial_sums_1_address0 = zext_ln54_1_reg_570; + +assign l2_partial_sums_1_address1 = zext_ln54_reg_562; + +assign l2_partial_sums_1_d0 = add14_5_lcssa25_fu_70; + +assign l2_partial_sums_1_d1 = add14_1_lcssa17_fu_54; + +assign l2_partial_sums_2_address0 = zext_ln54_1_reg_570; + +assign l2_partial_sums_2_address1 = zext_ln54_reg_562; + +assign l2_partial_sums_2_d0 = add14_6_lcssa27_fu_74; + +assign l2_partial_sums_2_d1 = add14_2_lcssa19_fu_58; + +assign l2_partial_sums_3_address0 = zext_ln54_1_reg_570; + +assign l2_partial_sums_3_address1 = zext_ln54_reg_562; + +assign l2_partial_sums_3_d0 = add14_7_lcssa29_fu_78; + +assign l2_partial_sums_3_d1 = add14_3_lcssa21_fu_62; + +assign l2_products_0_address0 = zext_ln54_3_fu_442_p1; + +assign l2_products_0_address1 = zext_ln54_2_fu_427_p1; + +assign l2_products_1_address0 = zext_ln54_3_fu_442_p1; + +assign l2_products_1_address1 = zext_ln54_2_fu_427_p1; + +assign l2_products_2_address0 = zext_ln54_3_fu_442_p1; + +assign l2_products_2_address1 = zext_ln54_2_fu_427_p1; + +assign l2_products_3_address0 = zext_ln54_3_fu_442_p1; + +assign l2_products_3_address1 = zext_ln54_2_fu_427_p1; + +assign out_idx_1_fu_398_p2 = (out_idx_fu_392_p2 | 3'd1); + +assign out_idx_fu_392_p2 = group_reg_282 << 3'd1; + +assign tmp_19_fu_435_p3 = {{i_1_1_reg_293}, {out_idx_1_reg_557}}; + +assign tmp_s_fu_418_p4 = {{{i_1_1_reg_293}, {trunc_ln52_reg_552}}, {1'd0}}; + +assign trunc_ln52_fu_388_p1 = group_reg_282[1:0]; + +assign zext_ln54_1_fu_408_p1 = out_idx_1_fu_398_p2; + +assign zext_ln54_2_fu_427_p1 = tmp_s_fu_418_p4; + +assign zext_ln54_3_fu_442_p1 = tmp_19_fu_435_p3; + +assign zext_ln54_fu_404_p1 = out_idx_fu_392_p2; + +always @ (posedge ap_clk) begin + out_idx_1_reg_557[0] <= 1'b1; + zext_ln54_reg_562[0] <= 1'b0; + zext_ln54_reg_562[63:3] <= 61'b0000000000000000000000000000000000000000000000000000000000000; + zext_ln54_1_reg_570[0] <= 1'b1; + zext_ln54_1_reg_570[63:3] <= 61'b0000000000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf7_l2_accum +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_l2_filters_0_ram (addr0, ce0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 12; +parameter MEM_SIZE = 4096; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_l2_filters_0( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd4096; +parameter AddressWidth = 32'd12; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_tdf7_l2_filters_0_ram td_fused_top_tdf7_l2_filters_0_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + module td_fused_top_tdf7_l2_filters_1_rom ( +addr0, ce0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 12; +parameter MEM_SIZE = 4096; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf7_l2_filters_1_rom.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +always @(posedge clk) +begin + if (ce1) + begin + q1 <= ram[addr1]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_l2_filters_1( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd4096; +parameter AddressWidth = 32'd12; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_tdf7_l2_filters_1_rom td_fused_top_tdf7_l2_filters_1_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_l2_multiply51 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + intermediate_fmaps_0_read, + intermediate_fmaps_1_read, + intermediate_fmaps_2_read, + intermediate_fmaps_3_read, + l2_filter_data_0_address0, + l2_filter_data_0_ce0, + l2_filter_data_0_q0, + l2_filter_data_0_address1, + l2_filter_data_0_ce1, + l2_filter_data_0_q1, + l2_filter_data_1_address0, + l2_filter_data_1_ce0, + l2_filter_data_1_q0, + l2_filter_data_1_address1, + l2_filter_data_1_ce1, + l2_filter_data_1_q1, + l2_products_0_address0, + l2_products_0_ce0, + l2_products_0_we0, + l2_products_0_d0, + l2_products_1_address0, + l2_products_1_ce0, + l2_products_1_we0, + l2_products_1_d0, + l2_products_2_address0, + l2_products_2_ce0, + l2_products_2_we0, + l2_products_2_d0, + l2_products_3_address0, + l2_products_3_ce0, + l2_products_3_we0, + l2_products_3_d0, + indices_23_dout, + indices_23_empty_n, + indices_23_read +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] intermediate_fmaps_0_read; +input [15:0] intermediate_fmaps_1_read; +input [15:0] intermediate_fmaps_2_read; +input [15:0] intermediate_fmaps_3_read; +output [11:0] l2_filter_data_0_address0; +output l2_filter_data_0_ce0; +input [15:0] l2_filter_data_0_q0; +output [11:0] l2_filter_data_0_address1; +output l2_filter_data_0_ce1; +input [15:0] l2_filter_data_0_q1; +output [11:0] l2_filter_data_1_address0; +output l2_filter_data_1_ce0; +input [15:0] l2_filter_data_1_q0; +output [11:0] l2_filter_data_1_address1; +output l2_filter_data_1_ce1; +input [15:0] l2_filter_data_1_q1; +output [4:0] l2_products_0_address0; +output l2_products_0_ce0; +output l2_products_0_we0; +output [15:0] l2_products_0_d0; +output [4:0] l2_products_1_address0; +output l2_products_1_ce0; +output l2_products_1_we0; +output [15:0] l2_products_1_d0; +output [4:0] l2_products_2_address0; +output l2_products_2_ce0; +output l2_products_2_we0; +output [15:0] l2_products_2_d0; +output [4:0] l2_products_3_address0; +output l2_products_3_ce0; +output l2_products_3_we0; +output [15:0] l2_products_3_d0; +input [5:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg l2_filter_data_0_ce0; +reg l2_filter_data_0_ce1; +reg l2_filter_data_1_ce0; +reg l2_filter_data_1_ce1; +reg l2_products_0_ce0; +reg l2_products_0_we0; +reg l2_products_1_ce0; +reg l2_products_1_we0; +reg l2_products_2_ce0; +reg l2_products_2_we0; +reg l2_products_3_ce0; +reg l2_products_3_we0; +reg indices_23_read; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [7:0] i_03_0_i_i_reg_236; +wire [7:0] shl_ln_fu_263_p3; +reg [7:0] shl_ln_reg_402; +wire [0:0] icmp_ln20_fu_271_p2; +reg [0:0] icmp_ln20_reg_407; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln20_reg_407_pp0_iter1_reg; +reg [0:0] icmp_ln20_reg_407_pp0_iter2_reg; +reg [0:0] icmp_ln20_reg_407_pp0_iter3_reg; +reg [0:0] icmp_ln20_reg_407_pp0_iter4_reg; +reg [0:0] icmp_ln20_reg_407_pp0_iter5_reg; +reg [0:0] icmp_ln20_reg_407_pp0_iter6_reg; +wire [7:0] add_ln20_fu_277_p2; +reg ap_enable_reg_pp0_iter0; +reg [1:0] trunc_ln_reg_416; +reg [5:0] tmp_17_reg_431; +reg [5:0] tmp_17_reg_431_pp0_iter1_reg; +reg [5:0] tmp_17_reg_431_pp0_iter2_reg; +reg [5:0] tmp_17_reg_431_pp0_iter3_reg; +reg [5:0] tmp_17_reg_431_pp0_iter4_reg; +reg [5:0] tmp_17_reg_431_pp0_iter5_reg; +reg [5:0] tmp_17_reg_431_pp0_iter6_reg; +wire [15:0] tmp_fu_366_p6; +reg [15:0] tmp_reg_446; +reg [15:0] l2_filter_data_0_load_reg_454; +reg ap_enable_reg_pp0_iter1; +reg [15:0] l2_filter_data_1_load_reg_459; +reg [15:0] l2_filter_data_0_load_1_reg_464; +reg [15:0] l2_filter_data_1_load_1_reg_469; +wire [15:0] grp_fu_247_p2; +reg [15:0] mul_i_i_reg_474; +wire [15:0] grp_fu_251_p2; +reg [15:0] mul_1_i_i_reg_479; +wire [15:0] grp_fu_255_p2; +reg [15:0] mul_2_i_i_reg_484; +wire [15:0] grp_fu_259_p2; +reg [15:0] mul_3_i_i_reg_489; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +wire [63:0] zext_ln29_fu_330_p1; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln29_8_fu_360_p1; +wire [63:0] zext_ln29_7_fu_375_p1; +wire [2:0] lshr_ln_fu_283_p4; +wire [7:0] zext_ln23_fu_293_p1; +wire [3:0] lshr_ln2_fu_312_p4; +wire [7:0] add_ln25_fu_297_p2; +wire [11:0] tmp_s_fu_322_p3; +wire [3:0] or_ln29_fu_346_p2; +wire [11:0] tmp_18_fu_352_p3; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1073( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_446), + .din1(l2_filter_data_0_load_reg_454), + .dout(grp_fu_247_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1074( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_446), + .din1(l2_filter_data_1_load_reg_459), + .dout(grp_fu_251_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1075( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_446), + .din1(l2_filter_data_0_load_1_reg_464), + .dout(grp_fu_255_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1076( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(tmp_reg_446), + .din1(l2_filter_data_1_load_1_reg_469), + .dout(grp_fu_259_p2) +); + +td_fused_top_mux_42_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 16 )) +mux_42_16_1_1_U1077( + .din0(intermediate_fmaps_0_read), + .din1(intermediate_fmaps_1_read), + .din2(intermediate_fmaps_2_read), + .din3(intermediate_fmaps_3_read), + .din4(trunc_ln_reg_416), + .dout(tmp_fu_366_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln20_fu_271_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + i_03_0_i_i_reg_236 <= add_ln20_fu_277_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + i_03_0_i_i_reg_236 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln20_reg_407 <= icmp_ln20_fu_271_p2; + icmp_ln20_reg_407_pp0_iter1_reg <= icmp_ln20_reg_407; + tmp_17_reg_431_pp0_iter1_reg <= tmp_17_reg_431; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln20_reg_407_pp0_iter2_reg <= icmp_ln20_reg_407_pp0_iter1_reg; + icmp_ln20_reg_407_pp0_iter3_reg <= icmp_ln20_reg_407_pp0_iter2_reg; + icmp_ln20_reg_407_pp0_iter4_reg <= icmp_ln20_reg_407_pp0_iter3_reg; + icmp_ln20_reg_407_pp0_iter5_reg <= icmp_ln20_reg_407_pp0_iter4_reg; + icmp_ln20_reg_407_pp0_iter6_reg <= icmp_ln20_reg_407_pp0_iter5_reg; + tmp_17_reg_431_pp0_iter2_reg <= tmp_17_reg_431_pp0_iter1_reg; + tmp_17_reg_431_pp0_iter3_reg <= tmp_17_reg_431_pp0_iter2_reg; + tmp_17_reg_431_pp0_iter4_reg <= tmp_17_reg_431_pp0_iter3_reg; + tmp_17_reg_431_pp0_iter5_reg <= tmp_17_reg_431_pp0_iter4_reg; + tmp_17_reg_431_pp0_iter6_reg <= tmp_17_reg_431_pp0_iter5_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln20_reg_407 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_0_load_1_reg_464 <= l2_filter_data_0_q0; + l2_filter_data_0_load_reg_454 <= l2_filter_data_0_q1; + l2_filter_data_1_load_1_reg_469 <= l2_filter_data_1_q0; + l2_filter_data_1_load_reg_459 <= l2_filter_data_1_q1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln20_reg_407_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_1_i_i_reg_479 <= grp_fu_251_p2; + mul_2_i_i_reg_484 <= grp_fu_255_p2; + mul_3_i_i_reg_489 <= grp_fu_259_p2; + mul_i_i_reg_474 <= grp_fu_247_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + shl_ln_reg_402[7 : 2] <= shl_ln_fu_263_p3[7 : 2]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln20_fu_271_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + tmp_17_reg_431 <= {{i_03_0_i_i_reg_236[7:2]}}; + trunc_ln_reg_416 <= {{i_03_0_i_i_reg_236[6:5]}}; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln20_reg_407 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + tmp_reg_446 <= tmp_fu_366_p6; + end +end + +always @ (*) begin + if ((icmp_ln20_fu_271_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_0_ce0 = 1'b1; + end else begin + l2_filter_data_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_0_ce1 = 1'b1; + end else begin + l2_filter_data_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_1_ce0 = 1'b1; + end else begin + l2_filter_data_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_filter_data_1_ce1 = 1'b1; + end else begin + l2_filter_data_1_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_0_ce0 = 1'b1; + end else begin + l2_products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln20_reg_407_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_0_we0 = 1'b1; + end else begin + l2_products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_1_ce0 = 1'b1; + end else begin + l2_products_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln20_reg_407_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_1_we0 = 1'b1; + end else begin + l2_products_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_2_ce0 = 1'b1; + end else begin + l2_products_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln20_reg_407_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_2_we0 = 1'b1; + end else begin + l2_products_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_3_ce0 = 1'b1; + end else begin + l2_products_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (icmp_ln20_reg_407_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_products_3_we0 = 1'b1; + end else begin + l2_products_3_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln20_fu_271_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((icmp_ln20_fu_271_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln20_fu_277_p2 = (i_03_0_i_i_reg_236 + 8'd4); + +assign add_ln25_fu_297_p2 = (zext_ln23_fu_293_p1 + shl_ln_reg_402); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign icmp_ln20_fu_271_p2 = ((i_03_0_i_i_reg_236 == 8'd128) ? 1'b1 : 1'b0); + +assign l2_filter_data_0_address0 = zext_ln29_8_fu_360_p1; + +assign l2_filter_data_0_address1 = zext_ln29_fu_330_p1; + +assign l2_filter_data_1_address0 = zext_ln29_8_fu_360_p1; + +assign l2_filter_data_1_address1 = zext_ln29_fu_330_p1; + +assign l2_products_0_address0 = zext_ln29_7_fu_375_p1; + +assign l2_products_0_d0 = mul_i_i_reg_474; + +assign l2_products_1_address0 = zext_ln29_7_fu_375_p1; + +assign l2_products_1_d0 = mul_1_i_i_reg_479; + +assign l2_products_2_address0 = zext_ln29_7_fu_375_p1; + +assign l2_products_2_d0 = mul_2_i_i_reg_484; + +assign l2_products_3_address0 = zext_ln29_7_fu_375_p1; + +assign l2_products_3_d0 = mul_3_i_i_reg_489; + +assign lshr_ln2_fu_312_p4 = {{i_03_0_i_i_reg_236[4:1]}}; + +assign lshr_ln_fu_283_p4 = {{i_03_0_i_i_reg_236[7:5]}}; + +assign or_ln29_fu_346_p2 = (lshr_ln2_fu_312_p4 | 4'd1); + +assign shl_ln_fu_263_p3 = {{indices_23_dout}, {2'd0}}; + +assign tmp_18_fu_352_p3 = {{or_ln29_fu_346_p2}, {add_ln25_fu_297_p2}}; + +assign tmp_s_fu_322_p3 = {{lshr_ln2_fu_312_p4}, {add_ln25_fu_297_p2}}; + +assign zext_ln23_fu_293_p1 = lshr_ln_fu_283_p4; + +assign zext_ln29_7_fu_375_p1 = tmp_17_reg_431_pp0_iter6_reg; + +assign zext_ln29_8_fu_360_p1 = tmp_18_fu_352_p3; + +assign zext_ln29_fu_330_p1 = tmp_s_fu_322_p3; + +always @ (posedge ap_clk) begin + shl_ln_reg_402[1:0] <= 2'b00; +end + +endmodule //td_fused_top_tdf7_l2_multiply51 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_l2_writeOutputs_1_running_sums_ram (addr0, ce0, d0, we0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 5; +parameter MEM_SIZE = 32; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf7_l2_writeOutputs_1_running_sums_ram.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_l2_writeOutputs_1_running_sums( + reset, + clk, + address0, + ce0, + we0, + d0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd32; +parameter AddressWidth = 32'd5; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_tdf7_l2_writeOutputs_1_running_sums_ram td_fused_top_tdf7_l2_writeOutputs_1_running_sums_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_l2_writeOutputs_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + write4_dout, + write4_empty_n, + write4_read, + l2_partial_sums_0_address0, + l2_partial_sums_0_ce0, + l2_partial_sums_0_q0, + l2_partial_sums_1_address0, + l2_partial_sums_1_ce0, + l2_partial_sums_1_q0, + l2_partial_sums_2_address0, + l2_partial_sums_2_ce0, + l2_partial_sums_2_q0, + l2_partial_sums_3_address0, + l2_partial_sums_3_ce0, + l2_partial_sums_3_q0, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_q0 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_pp0_stage0 = 4'd4; +parameter ap_ST_fsm_state34 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [4:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [9:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [0:0] write4_dout; +input write4_empty_n; +output write4_read; +output [2:0] l2_partial_sums_0_address0; +output l2_partial_sums_0_ce0; +input [15:0] l2_partial_sums_0_q0; +output [2:0] l2_partial_sums_1_address0; +output l2_partial_sums_1_ce0; +input [15:0] l2_partial_sums_1_q0; +output [2:0] l2_partial_sums_2_address0; +output l2_partial_sums_2_ce0; +input [15:0] l2_partial_sums_2_q0; +output [2:0] l2_partial_sums_3_address0; +output l2_partial_sums_3_ce0; +input [15:0] l2_partial_sums_3_q0; +output [12:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; +output [4:0] l2_adjustments_address0; +output l2_adjustments_ce0; +input [47:0] l2_adjustments_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg write4_read; +reg l2_partial_sums_0_ce0; +reg l2_partial_sums_1_ce0; +reg l2_partial_sums_2_ce0; +reg l2_partial_sums_3_ce0; +reg out_data_ce1; +reg out_data_we1; +reg l2_adjustments_ce0; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg running_sums_ce0; +reg running_sums_we0; +wire [15:0] running_sums_d0; +wire [4:0] running_sums_address1; +reg running_sums_ce1; +wire [15:0] running_sums_q1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg write4_blk_n; +reg [5:0] ochan_reg_251; +reg [4:0] indices_01_read_reg_630; +reg [9:0] indices_12_read_reg_636; +reg [0:0] write4_read_reg_641; +wire [11:0] add_ln109_fu_313_p2; +reg [11:0] add_ln109_reg_647; +wire ap_CS_fsm_state2; +wire [5:0] add_ln86_fu_319_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state4_pp0_stage0_iter1; +wire ap_block_state5_pp0_stage0_iter2; +wire ap_block_state6_pp0_stage0_iter3; +wire ap_block_state7_pp0_stage0_iter4; +wire ap_block_state8_pp0_stage0_iter5; +wire ap_block_state9_pp0_stage0_iter6; +wire ap_block_state10_pp0_stage0_iter7; +wire ap_block_state11_pp0_stage0_iter8; +wire ap_block_state12_pp0_stage0_iter9; +wire ap_block_state13_pp0_stage0_iter10; +wire ap_block_state14_pp0_stage0_iter11; +wire ap_block_state15_pp0_stage0_iter12; +wire ap_block_state16_pp0_stage0_iter13; +wire ap_block_state17_pp0_stage0_iter14; +wire ap_block_state18_pp0_stage0_iter15; +wire ap_block_state19_pp0_stage0_iter16; +wire ap_block_state20_pp0_stage0_iter17; +wire ap_block_state21_pp0_stage0_iter18; +wire ap_block_state22_pp0_stage0_iter19; +wire ap_block_state23_pp0_stage0_iter20; +wire ap_block_state24_pp0_stage0_iter21; +wire ap_block_state25_pp0_stage0_iter22; +wire ap_block_state26_pp0_stage0_iter23; +wire ap_block_state27_pp0_stage0_iter24; +wire ap_block_state28_pp0_stage0_iter25; +wire ap_block_state29_pp0_stage0_iter26; +wire ap_block_state30_pp0_stage0_iter27; +wire ap_block_state31_pp0_stage0_iter28; +wire ap_block_state32_pp0_stage0_iter29; +wire ap_block_state33_pp0_stage0_iter30; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln86_fu_325_p2; +wire [63:0] zext_ln86_fu_331_p1; +reg [63:0] zext_ln86_reg_661; +reg [63:0] zext_ln86_reg_661_pp0_iter1_reg; +reg [63:0] zext_ln86_reg_661_pp0_iter2_reg; +reg [63:0] zext_ln86_reg_661_pp0_iter3_reg; +reg [63:0] zext_ln86_reg_661_pp0_iter4_reg; +reg [63:0] zext_ln86_reg_661_pp0_iter5_reg; +reg [63:0] zext_ln86_reg_661_pp0_iter6_reg; +reg [63:0] zext_ln86_reg_661_pp0_iter7_reg; +wire [1:0] trunc_ln89_fu_336_p1; +reg [1:0] trunc_ln89_reg_666; +reg [1:0] trunc_ln89_reg_666_pp0_iter1_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter2_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter3_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter4_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter5_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter6_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter7_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter8_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter9_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter10_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter11_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter12_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter13_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter14_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter15_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter16_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter17_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter18_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter19_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter20_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter21_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter22_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter23_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter24_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter25_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter26_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter27_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter28_reg; +reg [1:0] trunc_ln89_reg_666_pp0_iter29_reg; +wire [2:0] lshr_ln_fu_340_p4; +reg [2:0] lshr_ln_reg_674; +reg [2:0] lshr_ln_reg_674_pp0_iter1_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter2_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter3_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter4_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter5_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter6_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter7_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter8_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter9_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter10_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter11_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter12_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter13_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter14_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter15_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter16_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter17_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter18_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter19_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter20_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter21_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter22_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter23_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter24_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter25_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter26_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter27_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter28_reg; +reg [2:0] lshr_ln_reg_674_pp0_iter29_reg; +reg [4:0] running_sums_addr_reg_699; +reg [4:0] running_sums_addr_reg_699_pp0_iter1_reg; +reg [4:0] running_sums_addr_reg_699_pp0_iter2_reg; +reg [4:0] running_sums_addr_reg_699_pp0_iter3_reg; +reg [4:0] running_sums_addr_reg_699_pp0_iter4_reg; +reg [4:0] running_sums_addr_reg_699_pp0_iter5_reg; +reg [4:0] running_sums_addr_reg_699_pp0_iter6_reg; +reg [4:0] running_sums_addr_reg_699_pp0_iter7_reg; +reg [4:0] running_sums_addr_reg_699_pp0_iter8_reg; +reg [4:0] running_sums_addr_reg_699_pp0_iter9_reg; +wire [0:0] and_ln103_fu_364_p2; +reg [0:0] and_ln103_reg_705; +reg [0:0] and_ln103_reg_705_pp0_iter1_reg; +reg [0:0] and_ln103_reg_705_pp0_iter2_reg; +reg [0:0] and_ln103_reg_705_pp0_iter3_reg; +reg [0:0] and_ln103_reg_705_pp0_iter4_reg; +reg [0:0] and_ln103_reg_705_pp0_iter5_reg; +reg [0:0] and_ln103_reg_705_pp0_iter6_reg; +reg [0:0] and_ln103_reg_705_pp0_iter7_reg; +reg [0:0] and_ln103_reg_705_pp0_iter8_reg; +reg [0:0] and_ln103_reg_705_pp0_iter9_reg; +reg [0:0] and_ln103_reg_705_pp0_iter10_reg; +reg [0:0] and_ln103_reg_705_pp0_iter11_reg; +reg [0:0] and_ln103_reg_705_pp0_iter12_reg; +reg [0:0] and_ln103_reg_705_pp0_iter13_reg; +reg [0:0] and_ln103_reg_705_pp0_iter14_reg; +reg [0:0] and_ln103_reg_705_pp0_iter15_reg; +reg [0:0] and_ln103_reg_705_pp0_iter16_reg; +reg [0:0] and_ln103_reg_705_pp0_iter17_reg; +reg [0:0] and_ln103_reg_705_pp0_iter18_reg; +reg [0:0] and_ln103_reg_705_pp0_iter19_reg; +reg [0:0] and_ln103_reg_705_pp0_iter20_reg; +reg [0:0] and_ln103_reg_705_pp0_iter21_reg; +reg [0:0] and_ln103_reg_705_pp0_iter22_reg; +reg [0:0] and_ln103_reg_705_pp0_iter23_reg; +reg [0:0] and_ln103_reg_705_pp0_iter24_reg; +reg [0:0] and_ln103_reg_705_pp0_iter25_reg; +reg [0:0] and_ln103_reg_705_pp0_iter26_reg; +reg [0:0] and_ln103_reg_705_pp0_iter27_reg; +reg [0:0] and_ln103_reg_705_pp0_iter28_reg; +reg [0:0] and_ln103_reg_705_pp0_iter29_reg; +wire [15:0] val_fu_372_p6; +reg [15:0] val_reg_709; +reg [15:0] running_sums_load_reg_714; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_262_p2; +reg [15:0] sum_reg_724; +wire [15:0] trunc_ln95_fu_386_p1; +reg [15:0] trunc_ln95_reg_730; +reg [15:0] tmp_68_i_i_reg_735; +reg [15:0] tmp_68_i_i_reg_735_pp0_iter10_reg; +reg [15:0] tmp_68_i_i_reg_735_pp0_iter11_reg; +reg [15:0] tmp_68_i_i_reg_735_pp0_iter12_reg; +reg [15:0] tmp_68_i_i_reg_735_pp0_iter13_reg; +reg [15:0] tmp_68_i_i_reg_735_pp0_iter14_reg; +reg [15:0] tmp_68_i_i_reg_735_pp0_iter15_reg; +reg [15:0] tmp_68_i_i_reg_735_pp0_iter16_reg; +reg [15:0] tmp_69_i_i_reg_740; +reg [15:0] tmp_69_i_i_reg_740_pp0_iter10_reg; +reg [15:0] tmp_69_i_i_reg_740_pp0_iter11_reg; +reg [15:0] tmp_69_i_i_reg_740_pp0_iter12_reg; +reg [15:0] tmp_69_i_i_reg_740_pp0_iter13_reg; +reg [15:0] tmp_69_i_i_reg_740_pp0_iter14_reg; +reg [15:0] tmp_69_i_i_reg_740_pp0_iter15_reg; +reg [15:0] tmp_69_i_i_reg_740_pp0_iter16_reg; +reg [15:0] tmp_69_i_i_reg_740_pp0_iter17_reg; +reg [15:0] tmp_69_i_i_reg_740_pp0_iter18_reg; +reg [15:0] tmp_69_i_i_reg_740_pp0_iter19_reg; +reg [15:0] tmp_69_i_i_reg_740_pp0_iter20_reg; +reg [15:0] tmp_69_i_i_reg_740_pp0_iter21_reg; +wire [15:0] grp_fu_270_p2; +reg [15:0] sub_i_i_i_reg_750; +wire [15:0] grp_fu_274_p2; +reg [15:0] normalized_reg_760; +wire [15:0] grp_fu_266_p2; +reg [15:0] biased_reg_770; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state3; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_enable_reg_pp0_iter22; +reg ap_enable_reg_pp0_iter23; +reg ap_enable_reg_pp0_iter24; +reg ap_enable_reg_pp0_iter25; +reg ap_enable_reg_pp0_iter26; +reg ap_enable_reg_pp0_iter27; +reg ap_enable_reg_pp0_iter28; +reg ap_enable_reg_pp0_iter29; +reg ap_enable_reg_pp0_iter30; +wire [63:0] zext_ln89_1_fu_350_p1; +wire ap_block_pp0_stage0; +wire [63:0] sext_ln109_fu_447_p1; +reg [15:0] quad_3_1_fu_118; +wire [15:0] quad_3_13_fu_549_p3; +reg [15:0] quad_3_2_fu_122; +wire [15:0] quad_3_12_fu_541_p3; +reg [15:0] quad_3_3_fu_126; +wire [15:0] quad_3_10_fu_525_p3; +reg [15:0] quad_3_4_fu_130; +wire [15:0] quad_3_7_fu_501_p3; +reg ap_block_state1; +wire [15:0] grp_fu_266_p1; +wire [15:0] grp_fu_270_p1; +wire [15:0] grp_fu_274_p1; +wire [9:0] tmp_fu_278_p3; +wire [6:0] tmp_s_fu_289_p3; +wire [10:0] zext_ln109_fu_285_p1; +wire [10:0] zext_ln109_1_fu_296_p1; +wire [10:0] sub_ln109_fu_300_p2; +wire [11:0] sub_ln109_cast_fu_306_p1; +wire [11:0] zext_ln109_2_fu_310_p1; +wire [0:0] icmp_ln103_fu_358_p2; +wire [63:0] val_fu_372_p5; +wire [14:0] tmp_26_fu_441_p3; +wire [15:0] data_V_fu_452_p1; +wire [0:0] p_Result_s_fu_455_p3; +wire [0:0] icmp_ln99_fu_470_p2; +wire [15:0] quad_0_fu_463_p3; +wire [0:0] icmp_ln99_1_fu_483_p2; +wire [15:0] quad_3_fu_475_p3; +wire [0:0] icmp_ln99_2_fu_496_p2; +wire [15:0] quad_3_6_fu_488_p3; +wire [15:0] quad_3_8_fu_509_p3; +wire [15:0] quad_3_9_fu_517_p3; +wire [15:0] quad_3_11_fu_533_p3; +wire [15:0] bitcast_ln109_3_fu_589_p1; +wire [15:0] bitcast_ln109_2_fu_585_p1; +wire [15:0] bitcast_ln109_1_fu_581_p1; +wire [15:0] bitcast_ln109_fu_577_p1; +wire ap_CS_fsm_state34; +reg [3:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +#0 ap_enable_reg_pp0_iter23 = 1'b0; +#0 ap_enable_reg_pp0_iter24 = 1'b0; +#0 ap_enable_reg_pp0_iter25 = 1'b0; +#0 ap_enable_reg_pp0_iter26 = 1'b0; +#0 ap_enable_reg_pp0_iter27 = 1'b0; +#0 ap_enable_reg_pp0_iter28 = 1'b0; +#0 ap_enable_reg_pp0_iter29 = 1'b0; +#0 ap_enable_reg_pp0_iter30 = 1'b0; +end + +td_fused_top_tdf7_l2_writeOutputs_1_running_sums #( + .DataWidth( 16 ), + .AddressRange( 32 ), + .AddressWidth( 5 )) +running_sums_U( + .reset(ap_rst), + .clk(ap_clk), + .address0(running_sums_addr_reg_699_pp0_iter9_reg), + .ce0(running_sums_ce0), + .we0(running_sums_we0), + .d0(running_sums_d0), + .address1(running_sums_address1), + .ce1(running_sums_ce1), + .q1(running_sums_q1) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1105( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(running_sums_load_reg_714), + .din1(val_reg_709), + .dout(grp_fu_262_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1106( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(normalized_reg_760), + .din1(grp_fu_266_p1), + .dout(grp_fu_266_p2) +); + +td_fused_top_hsub_16ns_16ns_16_7_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 7 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_7_full_dsp_1_U1107( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_reg_724), + .din1(grp_fu_270_p1), + .dout(grp_fu_270_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1108( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_750), + .din1(grp_fu_274_p1), + .dout(grp_fu_274_p2) +); + +td_fused_top_mux_464_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 64 ), + .dout_WIDTH( 16 )) +mux_464_16_1_1_U1109( + .din0(l2_partial_sums_0_q0), + .din1(l2_partial_sums_1_q0), + .din2(l2_partial_sums_2_q0), + .din3(l2_partial_sums_3_q0), + .din4(val_fu_372_p5), + .dout(val_fu_372_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state34)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state3) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state3)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state3); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter23 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter23 <= ap_enable_reg_pp0_iter22; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter24 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter24 <= ap_enable_reg_pp0_iter23; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter25 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter25 <= ap_enable_reg_pp0_iter24; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter26 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter26 <= ap_enable_reg_pp0_iter25; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter27 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter27 <= ap_enable_reg_pp0_iter26; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter28 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter28 <= ap_enable_reg_pp0_iter27; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter29 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter29 <= ap_enable_reg_pp0_iter28; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter30 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter30 <= ap_enable_reg_pp0_iter29; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter30 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_325_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ochan_reg_251 <= add_ln86_fu_319_p2; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ochan_reg_251 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln109_reg_647 <= add_ln109_fu_313_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_325_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + and_ln103_reg_705 <= and_ln103_fu_364_p2; + lshr_ln_reg_674 <= {{ochan_reg_251[4:2]}}; + running_sums_addr_reg_699 <= zext_ln86_fu_331_p1; + trunc_ln89_reg_666 <= trunc_ln89_fu_336_p1; + zext_ln86_reg_661[5 : 0] <= zext_ln86_fu_331_p1[5 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + and_ln103_reg_705_pp0_iter10_reg <= and_ln103_reg_705_pp0_iter9_reg; + and_ln103_reg_705_pp0_iter11_reg <= and_ln103_reg_705_pp0_iter10_reg; + and_ln103_reg_705_pp0_iter12_reg <= and_ln103_reg_705_pp0_iter11_reg; + and_ln103_reg_705_pp0_iter13_reg <= and_ln103_reg_705_pp0_iter12_reg; + and_ln103_reg_705_pp0_iter14_reg <= and_ln103_reg_705_pp0_iter13_reg; + and_ln103_reg_705_pp0_iter15_reg <= and_ln103_reg_705_pp0_iter14_reg; + and_ln103_reg_705_pp0_iter16_reg <= and_ln103_reg_705_pp0_iter15_reg; + and_ln103_reg_705_pp0_iter17_reg <= and_ln103_reg_705_pp0_iter16_reg; + and_ln103_reg_705_pp0_iter18_reg <= and_ln103_reg_705_pp0_iter17_reg; + and_ln103_reg_705_pp0_iter19_reg <= and_ln103_reg_705_pp0_iter18_reg; + and_ln103_reg_705_pp0_iter20_reg <= and_ln103_reg_705_pp0_iter19_reg; + and_ln103_reg_705_pp0_iter21_reg <= and_ln103_reg_705_pp0_iter20_reg; + and_ln103_reg_705_pp0_iter22_reg <= and_ln103_reg_705_pp0_iter21_reg; + and_ln103_reg_705_pp0_iter23_reg <= and_ln103_reg_705_pp0_iter22_reg; + and_ln103_reg_705_pp0_iter24_reg <= and_ln103_reg_705_pp0_iter23_reg; + and_ln103_reg_705_pp0_iter25_reg <= and_ln103_reg_705_pp0_iter24_reg; + and_ln103_reg_705_pp0_iter26_reg <= and_ln103_reg_705_pp0_iter25_reg; + and_ln103_reg_705_pp0_iter27_reg <= and_ln103_reg_705_pp0_iter26_reg; + and_ln103_reg_705_pp0_iter28_reg <= and_ln103_reg_705_pp0_iter27_reg; + and_ln103_reg_705_pp0_iter29_reg <= and_ln103_reg_705_pp0_iter28_reg; + and_ln103_reg_705_pp0_iter2_reg <= and_ln103_reg_705_pp0_iter1_reg; + and_ln103_reg_705_pp0_iter3_reg <= and_ln103_reg_705_pp0_iter2_reg; + and_ln103_reg_705_pp0_iter4_reg <= and_ln103_reg_705_pp0_iter3_reg; + and_ln103_reg_705_pp0_iter5_reg <= and_ln103_reg_705_pp0_iter4_reg; + and_ln103_reg_705_pp0_iter6_reg <= and_ln103_reg_705_pp0_iter5_reg; + and_ln103_reg_705_pp0_iter7_reg <= and_ln103_reg_705_pp0_iter6_reg; + and_ln103_reg_705_pp0_iter8_reg <= and_ln103_reg_705_pp0_iter7_reg; + and_ln103_reg_705_pp0_iter9_reg <= and_ln103_reg_705_pp0_iter8_reg; + biased_reg_770 <= grp_fu_266_p2; + lshr_ln_reg_674_pp0_iter10_reg <= lshr_ln_reg_674_pp0_iter9_reg; + lshr_ln_reg_674_pp0_iter11_reg <= lshr_ln_reg_674_pp0_iter10_reg; + lshr_ln_reg_674_pp0_iter12_reg <= lshr_ln_reg_674_pp0_iter11_reg; + lshr_ln_reg_674_pp0_iter13_reg <= lshr_ln_reg_674_pp0_iter12_reg; + lshr_ln_reg_674_pp0_iter14_reg <= lshr_ln_reg_674_pp0_iter13_reg; + lshr_ln_reg_674_pp0_iter15_reg <= lshr_ln_reg_674_pp0_iter14_reg; + lshr_ln_reg_674_pp0_iter16_reg <= lshr_ln_reg_674_pp0_iter15_reg; + lshr_ln_reg_674_pp0_iter17_reg <= lshr_ln_reg_674_pp0_iter16_reg; + lshr_ln_reg_674_pp0_iter18_reg <= lshr_ln_reg_674_pp0_iter17_reg; + lshr_ln_reg_674_pp0_iter19_reg <= lshr_ln_reg_674_pp0_iter18_reg; + lshr_ln_reg_674_pp0_iter20_reg <= lshr_ln_reg_674_pp0_iter19_reg; + lshr_ln_reg_674_pp0_iter21_reg <= lshr_ln_reg_674_pp0_iter20_reg; + lshr_ln_reg_674_pp0_iter22_reg <= lshr_ln_reg_674_pp0_iter21_reg; + lshr_ln_reg_674_pp0_iter23_reg <= lshr_ln_reg_674_pp0_iter22_reg; + lshr_ln_reg_674_pp0_iter24_reg <= lshr_ln_reg_674_pp0_iter23_reg; + lshr_ln_reg_674_pp0_iter25_reg <= lshr_ln_reg_674_pp0_iter24_reg; + lshr_ln_reg_674_pp0_iter26_reg <= lshr_ln_reg_674_pp0_iter25_reg; + lshr_ln_reg_674_pp0_iter27_reg <= lshr_ln_reg_674_pp0_iter26_reg; + lshr_ln_reg_674_pp0_iter28_reg <= lshr_ln_reg_674_pp0_iter27_reg; + lshr_ln_reg_674_pp0_iter29_reg <= lshr_ln_reg_674_pp0_iter28_reg; + lshr_ln_reg_674_pp0_iter2_reg <= lshr_ln_reg_674_pp0_iter1_reg; + lshr_ln_reg_674_pp0_iter3_reg <= lshr_ln_reg_674_pp0_iter2_reg; + lshr_ln_reg_674_pp0_iter4_reg <= lshr_ln_reg_674_pp0_iter3_reg; + lshr_ln_reg_674_pp0_iter5_reg <= lshr_ln_reg_674_pp0_iter4_reg; + lshr_ln_reg_674_pp0_iter6_reg <= lshr_ln_reg_674_pp0_iter5_reg; + lshr_ln_reg_674_pp0_iter7_reg <= lshr_ln_reg_674_pp0_iter6_reg; + lshr_ln_reg_674_pp0_iter8_reg <= lshr_ln_reg_674_pp0_iter7_reg; + lshr_ln_reg_674_pp0_iter9_reg <= lshr_ln_reg_674_pp0_iter8_reg; + normalized_reg_760 <= grp_fu_274_p2; + running_sums_addr_reg_699_pp0_iter2_reg <= running_sums_addr_reg_699_pp0_iter1_reg; + running_sums_addr_reg_699_pp0_iter3_reg <= running_sums_addr_reg_699_pp0_iter2_reg; + running_sums_addr_reg_699_pp0_iter4_reg <= running_sums_addr_reg_699_pp0_iter3_reg; + running_sums_addr_reg_699_pp0_iter5_reg <= running_sums_addr_reg_699_pp0_iter4_reg; + running_sums_addr_reg_699_pp0_iter6_reg <= running_sums_addr_reg_699_pp0_iter5_reg; + running_sums_addr_reg_699_pp0_iter7_reg <= running_sums_addr_reg_699_pp0_iter6_reg; + running_sums_addr_reg_699_pp0_iter8_reg <= running_sums_addr_reg_699_pp0_iter7_reg; + running_sums_addr_reg_699_pp0_iter9_reg <= running_sums_addr_reg_699_pp0_iter8_reg; + sub_i_i_i_reg_750 <= grp_fu_270_p2; + sum_reg_724 <= grp_fu_262_p2; + tmp_68_i_i_reg_735 <= {{l2_adjustments_q0[31:16]}}; + tmp_68_i_i_reg_735_pp0_iter10_reg <= tmp_68_i_i_reg_735; + tmp_68_i_i_reg_735_pp0_iter11_reg <= tmp_68_i_i_reg_735_pp0_iter10_reg; + tmp_68_i_i_reg_735_pp0_iter12_reg <= tmp_68_i_i_reg_735_pp0_iter11_reg; + tmp_68_i_i_reg_735_pp0_iter13_reg <= tmp_68_i_i_reg_735_pp0_iter12_reg; + tmp_68_i_i_reg_735_pp0_iter14_reg <= tmp_68_i_i_reg_735_pp0_iter13_reg; + tmp_68_i_i_reg_735_pp0_iter15_reg <= tmp_68_i_i_reg_735_pp0_iter14_reg; + tmp_68_i_i_reg_735_pp0_iter16_reg <= tmp_68_i_i_reg_735_pp0_iter15_reg; + tmp_69_i_i_reg_740 <= {{l2_adjustments_q0[47:32]}}; + tmp_69_i_i_reg_740_pp0_iter10_reg <= tmp_69_i_i_reg_740; + tmp_69_i_i_reg_740_pp0_iter11_reg <= tmp_69_i_i_reg_740_pp0_iter10_reg; + tmp_69_i_i_reg_740_pp0_iter12_reg <= tmp_69_i_i_reg_740_pp0_iter11_reg; + tmp_69_i_i_reg_740_pp0_iter13_reg <= tmp_69_i_i_reg_740_pp0_iter12_reg; + tmp_69_i_i_reg_740_pp0_iter14_reg <= tmp_69_i_i_reg_740_pp0_iter13_reg; + tmp_69_i_i_reg_740_pp0_iter15_reg <= tmp_69_i_i_reg_740_pp0_iter14_reg; + tmp_69_i_i_reg_740_pp0_iter16_reg <= tmp_69_i_i_reg_740_pp0_iter15_reg; + tmp_69_i_i_reg_740_pp0_iter17_reg <= tmp_69_i_i_reg_740_pp0_iter16_reg; + tmp_69_i_i_reg_740_pp0_iter18_reg <= tmp_69_i_i_reg_740_pp0_iter17_reg; + tmp_69_i_i_reg_740_pp0_iter19_reg <= tmp_69_i_i_reg_740_pp0_iter18_reg; + tmp_69_i_i_reg_740_pp0_iter20_reg <= tmp_69_i_i_reg_740_pp0_iter19_reg; + tmp_69_i_i_reg_740_pp0_iter21_reg <= tmp_69_i_i_reg_740_pp0_iter20_reg; + trunc_ln89_reg_666_pp0_iter10_reg <= trunc_ln89_reg_666_pp0_iter9_reg; + trunc_ln89_reg_666_pp0_iter11_reg <= trunc_ln89_reg_666_pp0_iter10_reg; + trunc_ln89_reg_666_pp0_iter12_reg <= trunc_ln89_reg_666_pp0_iter11_reg; + trunc_ln89_reg_666_pp0_iter13_reg <= trunc_ln89_reg_666_pp0_iter12_reg; + trunc_ln89_reg_666_pp0_iter14_reg <= trunc_ln89_reg_666_pp0_iter13_reg; + trunc_ln89_reg_666_pp0_iter15_reg <= trunc_ln89_reg_666_pp0_iter14_reg; + trunc_ln89_reg_666_pp0_iter16_reg <= trunc_ln89_reg_666_pp0_iter15_reg; + trunc_ln89_reg_666_pp0_iter17_reg <= trunc_ln89_reg_666_pp0_iter16_reg; + trunc_ln89_reg_666_pp0_iter18_reg <= trunc_ln89_reg_666_pp0_iter17_reg; + trunc_ln89_reg_666_pp0_iter19_reg <= trunc_ln89_reg_666_pp0_iter18_reg; + trunc_ln89_reg_666_pp0_iter20_reg <= trunc_ln89_reg_666_pp0_iter19_reg; + trunc_ln89_reg_666_pp0_iter21_reg <= trunc_ln89_reg_666_pp0_iter20_reg; + trunc_ln89_reg_666_pp0_iter22_reg <= trunc_ln89_reg_666_pp0_iter21_reg; + trunc_ln89_reg_666_pp0_iter23_reg <= trunc_ln89_reg_666_pp0_iter22_reg; + trunc_ln89_reg_666_pp0_iter24_reg <= trunc_ln89_reg_666_pp0_iter23_reg; + trunc_ln89_reg_666_pp0_iter25_reg <= trunc_ln89_reg_666_pp0_iter24_reg; + trunc_ln89_reg_666_pp0_iter26_reg <= trunc_ln89_reg_666_pp0_iter25_reg; + trunc_ln89_reg_666_pp0_iter27_reg <= trunc_ln89_reg_666_pp0_iter26_reg; + trunc_ln89_reg_666_pp0_iter28_reg <= trunc_ln89_reg_666_pp0_iter27_reg; + trunc_ln89_reg_666_pp0_iter29_reg <= trunc_ln89_reg_666_pp0_iter28_reg; + trunc_ln89_reg_666_pp0_iter2_reg <= trunc_ln89_reg_666_pp0_iter1_reg; + trunc_ln89_reg_666_pp0_iter3_reg <= trunc_ln89_reg_666_pp0_iter2_reg; + trunc_ln89_reg_666_pp0_iter4_reg <= trunc_ln89_reg_666_pp0_iter3_reg; + trunc_ln89_reg_666_pp0_iter5_reg <= trunc_ln89_reg_666_pp0_iter4_reg; + trunc_ln89_reg_666_pp0_iter6_reg <= trunc_ln89_reg_666_pp0_iter5_reg; + trunc_ln89_reg_666_pp0_iter7_reg <= trunc_ln89_reg_666_pp0_iter6_reg; + trunc_ln89_reg_666_pp0_iter8_reg <= trunc_ln89_reg_666_pp0_iter7_reg; + trunc_ln89_reg_666_pp0_iter9_reg <= trunc_ln89_reg_666_pp0_iter8_reg; + trunc_ln95_reg_730 <= trunc_ln95_fu_386_p1; + zext_ln86_reg_661_pp0_iter2_reg[5 : 0] <= zext_ln86_reg_661_pp0_iter1_reg[5 : 0]; + zext_ln86_reg_661_pp0_iter3_reg[5 : 0] <= zext_ln86_reg_661_pp0_iter2_reg[5 : 0]; + zext_ln86_reg_661_pp0_iter4_reg[5 : 0] <= zext_ln86_reg_661_pp0_iter3_reg[5 : 0]; + zext_ln86_reg_661_pp0_iter5_reg[5 : 0] <= zext_ln86_reg_661_pp0_iter4_reg[5 : 0]; + zext_ln86_reg_661_pp0_iter6_reg[5 : 0] <= zext_ln86_reg_661_pp0_iter5_reg[5 : 0]; + zext_ln86_reg_661_pp0_iter7_reg[5 : 0] <= zext_ln86_reg_661_pp0_iter6_reg[5 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + and_ln103_reg_705_pp0_iter1_reg <= and_ln103_reg_705; + lshr_ln_reg_674_pp0_iter1_reg <= lshr_ln_reg_674; + running_sums_addr_reg_699_pp0_iter1_reg <= running_sums_addr_reg_699; + trunc_ln89_reg_666_pp0_iter1_reg <= trunc_ln89_reg_666; + val_reg_709 <= val_fu_372_p6; + zext_ln86_reg_661_pp0_iter1_reg[5 : 0] <= zext_ln86_reg_661[5 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + indices_01_read_reg_630 <= indices_01_dout; + indices_12_read_reg_636 <= indices_12_dout; + write4_read_reg_641 <= write4_dout; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter30 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + quad_3_1_fu_118 <= quad_3_13_fu_549_p3; + quad_3_2_fu_122 <= quad_3_12_fu_541_p3; + quad_3_3_fu_126 <= quad_3_10_fu_525_p3; + quad_3_4_fu_130 <= quad_3_7_fu_501_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_load_reg_714 <= running_sums_q1; + end +end + +always @ (*) begin + if ((icmp_ln86_fu_325_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state34)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter30 == 1'b0) & (ap_enable_reg_pp0_iter29 == 1'b0) & (ap_enable_reg_pp0_iter28 == 1'b0) & (ap_enable_reg_pp0_iter27 == 1'b0) & (ap_enable_reg_pp0_iter26 == 1'b0) & (ap_enable_reg_pp0_iter25 == 1'b0) & (ap_enable_reg_pp0_iter24 == 1'b0) & (ap_enable_reg_pp0_iter23 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state34)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_adjustments_ce0 = 1'b1; + end else begin + l2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_0_ce0 = 1'b1; + end else begin + l2_partial_sums_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_1_ce0 = 1'b1; + end else begin + l2_partial_sums_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_2_ce0 = 1'b1; + end else begin + l2_partial_sums_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + l2_partial_sums_3_ce0 = 1'b1; + end else begin + l2_partial_sums_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter30 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter30 == 1'b1) & (1'd1 == and_ln103_reg_705_pp0_iter29_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter10 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_ce0 = 1'b1; + end else begin + running_sums_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + running_sums_ce1 = 1'b1; + end else begin + running_sums_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter10 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_we0 = 1'b1; + end else begin + running_sums_we0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write4_blk_n = write4_empty_n; + end else begin + write4_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write4_read = 1'b1; + end else begin + write4_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln86_fu_325_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter30 == 1'b1) & (ap_enable_reg_pp0_iter29 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter30 == 1'b1) & (ap_enable_reg_pp0_iter29 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln86_fu_325_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state34; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state34 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln109_fu_313_p2 = ((sub_ln109_cast_fu_306_p1) + (zext_ln109_2_fu_310_p1)); + +assign add_ln86_fu_319_p2 = (ochan_reg_251 + 6'd1); + +assign and_ln103_fu_364_p2 = (write4_read_reg_641 & icmp_ln103_fu_358_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state34 = ap_CS_fsm[32'd3]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state25_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state26_pp0_stage0_iter23 = ~(1'b1 == 1'b1); + +assign ap_block_state27_pp0_stage0_iter24 = ~(1'b1 == 1'b1); + +assign ap_block_state28_pp0_stage0_iter25 = ~(1'b1 == 1'b1); + +assign ap_block_state29_pp0_stage0_iter26 = ~(1'b1 == 1'b1); + +assign ap_block_state30_pp0_stage0_iter27 = ~(1'b1 == 1'b1); + +assign ap_block_state31_pp0_stage0_iter28 = ~(1'b1 == 1'b1); + +assign ap_block_state32_pp0_stage0_iter29 = ~(1'b1 == 1'b1); + +assign ap_block_state33_pp0_stage0_iter30 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln109_1_fu_581_p1 = quad_3_12_fu_541_p3; + +assign bitcast_ln109_2_fu_585_p1 = quad_3_10_fu_525_p3; + +assign bitcast_ln109_3_fu_589_p1 = quad_3_7_fu_501_p3; + +assign bitcast_ln109_fu_577_p1 = quad_3_13_fu_549_p3; + +assign data_V_fu_452_p1 = biased_reg_770; + +assign grp_fu_266_p1 = tmp_69_i_i_reg_740_pp0_iter21_reg; + +assign grp_fu_270_p1 = trunc_ln95_reg_730; + +assign grp_fu_274_p1 = tmp_68_i_i_reg_735_pp0_iter16_reg; + +assign icmp_ln103_fu_358_p2 = ((trunc_ln89_fu_336_p1 == 2'd3) ? 1'b1 : 1'b0); + +assign icmp_ln86_fu_325_p2 = ((ochan_reg_251 == 6'd32) ? 1'b1 : 1'b0); + +assign icmp_ln99_1_fu_483_p2 = ((trunc_ln89_reg_666_pp0_iter29_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln99_2_fu_496_p2 = ((trunc_ln89_reg_666_pp0_iter29_reg == 2'd0) ? 1'b1 : 1'b0); + +assign icmp_ln99_fu_470_p2 = ((trunc_ln89_reg_666_pp0_iter29_reg == 2'd2) ? 1'b1 : 1'b0); + +assign l2_adjustments_address0 = zext_ln86_reg_661_pp0_iter7_reg; + +assign l2_partial_sums_0_address0 = zext_ln89_1_fu_350_p1; + +assign l2_partial_sums_1_address0 = zext_ln89_1_fu_350_p1; + +assign l2_partial_sums_2_address0 = zext_ln89_1_fu_350_p1; + +assign l2_partial_sums_3_address0 = zext_ln89_1_fu_350_p1; + +assign lshr_ln_fu_340_p4 = {{ochan_reg_251[4:2]}}; + +assign out_data_address1 = sext_ln109_fu_447_p1; + +assign out_data_d1 = {{{{bitcast_ln109_3_fu_589_p1}, {bitcast_ln109_2_fu_585_p1}}, {bitcast_ln109_1_fu_581_p1}}, {bitcast_ln109_fu_577_p1}}; + +assign p_Result_s_fu_455_p3 = data_V_fu_452_p1[32'd15]; + +assign quad_0_fu_463_p3 = ((p_Result_s_fu_455_p3[0:0] == 1'b1) ? 16'd0 : biased_reg_770); + +assign quad_3_10_fu_525_p3 = ((icmp_ln99_2_fu_496_p2[0:0] == 1'b1) ? quad_3_3_fu_126 : quad_3_9_fu_517_p3); + +assign quad_3_11_fu_533_p3 = ((icmp_ln99_1_fu_483_p2[0:0] == 1'b1) ? quad_0_fu_463_p3 : quad_3_2_fu_122); + +assign quad_3_12_fu_541_p3 = ((icmp_ln99_2_fu_496_p2[0:0] == 1'b1) ? quad_3_2_fu_122 : quad_3_11_fu_533_p3); + +assign quad_3_13_fu_549_p3 = ((icmp_ln99_2_fu_496_p2[0:0] == 1'b1) ? quad_0_fu_463_p3 : quad_3_1_fu_118); + +assign quad_3_6_fu_488_p3 = ((icmp_ln99_1_fu_483_p2[0:0] == 1'b1) ? quad_3_4_fu_130 : quad_3_fu_475_p3); + +assign quad_3_7_fu_501_p3 = ((icmp_ln99_2_fu_496_p2[0:0] == 1'b1) ? quad_3_4_fu_130 : quad_3_6_fu_488_p3); + +assign quad_3_8_fu_509_p3 = ((icmp_ln99_fu_470_p2[0:0] == 1'b1) ? quad_0_fu_463_p3 : quad_3_3_fu_126); + +assign quad_3_9_fu_517_p3 = ((icmp_ln99_1_fu_483_p2[0:0] == 1'b1) ? quad_3_3_fu_126 : quad_3_8_fu_509_p3); + +assign quad_3_fu_475_p3 = ((icmp_ln99_fu_470_p2[0:0] == 1'b1) ? quad_3_4_fu_130 : quad_0_fu_463_p3); + +assign running_sums_address1 = zext_ln86_fu_331_p1; + +assign running_sums_d0 = ((write4_read_reg_641[0:0] == 1'b1) ? 16'd0 : sum_reg_724); + +assign sext_ln109_fu_447_p1 = (tmp_26_fu_441_p3); + +assign sub_ln109_cast_fu_306_p1 = (sub_ln109_fu_300_p2); + +assign sub_ln109_fu_300_p2 = (zext_ln109_fu_285_p1 - zext_ln109_1_fu_296_p1); + +assign tmp_26_fu_441_p3 = {{add_ln109_reg_647}, {lshr_ln_reg_674_pp0_iter29_reg}}; + +assign tmp_fu_278_p3 = {{indices_01_read_reg_630}, {5'd0}}; + +assign tmp_s_fu_289_p3 = {{indices_01_read_reg_630}, {2'd0}}; + +assign trunc_ln89_fu_336_p1 = ochan_reg_251[1:0]; + +assign trunc_ln95_fu_386_p1 = l2_adjustments_q0[15:0]; + +assign val_fu_372_p5 = trunc_ln89_reg_666; + +assign zext_ln109_1_fu_296_p1 = tmp_s_fu_289_p3; + +assign zext_ln109_2_fu_310_p1 = indices_12_read_reg_636; + +assign zext_ln109_fu_285_p1 = tmp_fu_278_p3; + +assign zext_ln86_fu_331_p1 = ochan_reg_251; + +assign zext_ln89_1_fu_350_p1 = lshr_ln_fu_340_p4; + +always @ (posedge ap_clk) begin + zext_ln86_reg_661[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_661_pp0_iter1_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_661_pp0_iter2_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_661_pp0_iter3_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_661_pp0_iter4_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_661_pp0_iter5_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_661_pp0_iter6_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_661_pp0_iter7_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf7_l2_writeOutputs_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_readFilters53 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_0_address0, + filter_data_0_ce0, + filter_data_0_q0, + filter_data_1_address0, + filter_data_1_ce0, + filter_data_1_q0, + filter_data_2_address0, + filter_data_2_ce0, + filter_data_2_q0, + filter_data_3_address0, + filter_data_3_ce0, + filter_data_3_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + weight_vecs_0_0_address0, + weight_vecs_0_0_ce0, + weight_vecs_0_0_we0, + weight_vecs_0_0_d0, + weight_vecs_0_1_address0, + weight_vecs_0_1_ce0, + weight_vecs_0_1_we0, + weight_vecs_0_1_d0, + weight_vecs_0_2_address0, + weight_vecs_0_2_ce0, + weight_vecs_0_2_we0, + weight_vecs_0_2_d0, + weight_vecs_0_3_address0, + weight_vecs_0_3_ce0, + weight_vecs_0_3_we0, + weight_vecs_0_3_d0, + weight_vecs_1_0_address0, + weight_vecs_1_0_ce0, + weight_vecs_1_0_we0, + weight_vecs_1_0_d0, + weight_vecs_1_1_address0, + weight_vecs_1_1_ce0, + weight_vecs_1_1_we0, + weight_vecs_1_1_d0, + weight_vecs_1_2_address0, + weight_vecs_1_2_ce0, + weight_vecs_1_2_we0, + weight_vecs_1_2_d0, + weight_vecs_1_3_address0, + weight_vecs_1_3_ce0, + weight_vecs_1_3_we0, + weight_vecs_1_3_d0, + weight_vecs_2_0_address0, + weight_vecs_2_0_ce0, + weight_vecs_2_0_we0, + weight_vecs_2_0_d0, + weight_vecs_2_1_address0, + weight_vecs_2_1_ce0, + weight_vecs_2_1_we0, + weight_vecs_2_1_d0, + weight_vecs_2_2_address0, + weight_vecs_2_2_ce0, + weight_vecs_2_2_we0, + weight_vecs_2_2_d0, + weight_vecs_2_3_address0, + weight_vecs_2_3_ce0, + weight_vecs_2_3_we0, + weight_vecs_2_3_d0, + weight_vecs_3_0_address0, + weight_vecs_3_0_ce0, + weight_vecs_3_0_we0, + weight_vecs_3_0_d0, + weight_vecs_3_1_address0, + weight_vecs_3_1_ce0, + weight_vecs_3_1_we0, + weight_vecs_3_1_d0, + weight_vecs_3_2_address0, + weight_vecs_3_2_ce0, + weight_vecs_3_2_we0, + weight_vecs_3_2_d0, + weight_vecs_3_3_address0, + weight_vecs_3_3_ce0, + weight_vecs_3_3_we0, + weight_vecs_3_3_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state6 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [12:0] filter_data_0_address0; +output filter_data_0_ce0; +input [63:0] filter_data_0_q0; +output [12:0] filter_data_1_address0; +output filter_data_1_ce0; +input [63:0] filter_data_1_q0; +output [12:0] filter_data_2_address0; +output filter_data_2_ce0; +input [63:0] filter_data_2_q0; +output [12:0] filter_data_3_address0; +output filter_data_3_ce0; +input [63:0] filter_data_3_q0; +input [5:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [6:0] weight_vecs_0_0_address0; +output weight_vecs_0_0_ce0; +output weight_vecs_0_0_we0; +output [15:0] weight_vecs_0_0_d0; +output [6:0] weight_vecs_0_1_address0; +output weight_vecs_0_1_ce0; +output weight_vecs_0_1_we0; +output [15:0] weight_vecs_0_1_d0; +output [6:0] weight_vecs_0_2_address0; +output weight_vecs_0_2_ce0; +output weight_vecs_0_2_we0; +output [15:0] weight_vecs_0_2_d0; +output [6:0] weight_vecs_0_3_address0; +output weight_vecs_0_3_ce0; +output weight_vecs_0_3_we0; +output [15:0] weight_vecs_0_3_d0; +output [6:0] weight_vecs_1_0_address0; +output weight_vecs_1_0_ce0; +output weight_vecs_1_0_we0; +output [15:0] weight_vecs_1_0_d0; +output [6:0] weight_vecs_1_1_address0; +output weight_vecs_1_1_ce0; +output weight_vecs_1_1_we0; +output [15:0] weight_vecs_1_1_d0; +output [6:0] weight_vecs_1_2_address0; +output weight_vecs_1_2_ce0; +output weight_vecs_1_2_we0; +output [15:0] weight_vecs_1_2_d0; +output [6:0] weight_vecs_1_3_address0; +output weight_vecs_1_3_ce0; +output weight_vecs_1_3_we0; +output [15:0] weight_vecs_1_3_d0; +output [6:0] weight_vecs_2_0_address0; +output weight_vecs_2_0_ce0; +output weight_vecs_2_0_we0; +output [15:0] weight_vecs_2_0_d0; +output [6:0] weight_vecs_2_1_address0; +output weight_vecs_2_1_ce0; +output weight_vecs_2_1_we0; +output [15:0] weight_vecs_2_1_d0; +output [6:0] weight_vecs_2_2_address0; +output weight_vecs_2_2_ce0; +output weight_vecs_2_2_we0; +output [15:0] weight_vecs_2_2_d0; +output [6:0] weight_vecs_2_3_address0; +output weight_vecs_2_3_ce0; +output weight_vecs_2_3_we0; +output [15:0] weight_vecs_2_3_d0; +output [6:0] weight_vecs_3_0_address0; +output weight_vecs_3_0_ce0; +output weight_vecs_3_0_we0; +output [15:0] weight_vecs_3_0_d0; +output [6:0] weight_vecs_3_1_address0; +output weight_vecs_3_1_ce0; +output weight_vecs_3_1_we0; +output [15:0] weight_vecs_3_1_d0; +output [6:0] weight_vecs_3_2_address0; +output weight_vecs_3_2_ce0; +output weight_vecs_3_2_we0; +output [15:0] weight_vecs_3_2_d0; +output [6:0] weight_vecs_3_3_address0; +output weight_vecs_3_3_ce0; +output weight_vecs_3_3_we0; +output [15:0] weight_vecs_3_3_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_0_ce0; +reg filter_data_1_ce0; +reg filter_data_2_ce0; +reg filter_data_3_ce0; +reg indices_23_read; +reg weight_vecs_0_0_ce0; +reg weight_vecs_0_0_we0; +reg weight_vecs_0_1_ce0; +reg weight_vecs_0_1_we0; +reg weight_vecs_0_2_ce0; +reg weight_vecs_0_2_we0; +reg weight_vecs_0_3_ce0; +reg weight_vecs_0_3_we0; +reg weight_vecs_1_0_ce0; +reg weight_vecs_1_0_we0; +reg weight_vecs_1_1_ce0; +reg weight_vecs_1_1_we0; +reg weight_vecs_1_2_ce0; +reg weight_vecs_1_2_we0; +reg weight_vecs_1_3_ce0; +reg weight_vecs_1_3_we0; +reg weight_vecs_2_0_ce0; +reg weight_vecs_2_0_we0; +reg weight_vecs_2_1_ce0; +reg weight_vecs_2_1_we0; +reg weight_vecs_2_2_ce0; +reg weight_vecs_2_2_we0; +reg weight_vecs_2_3_ce0; +reg weight_vecs_2_3_we0; +reg weight_vecs_3_0_ce0; +reg weight_vecs_3_0_we0; +reg weight_vecs_3_1_ce0; +reg weight_vecs_3_1_we0; +reg weight_vecs_3_2_ce0; +reg weight_vecs_3_2_we0; +reg weight_vecs_3_3_ce0; +reg weight_vecs_3_3_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [6:0] indvar_flatten13_reg_412; +reg [1:0] ii_reg_423; +reg [5:0] indvar_flatten_reg_434; +reg [1:0] jj_reg_445; +reg [5:0] kk_reg_456; +wire [9:0] sext_ln47_fu_489_p1; +reg [9:0] sext_ln47_reg_989; +wire [6:0] add_ln47_2_fu_493_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln47_fu_499_p2; +reg [0:0] icmp_ln47_reg_999; +reg [0:0] icmp_ln47_reg_999_pp0_iter1_reg; +reg [0:0] icmp_ln47_reg_999_pp0_iter2_reg; +wire [1:0] select_ln47_4_fu_533_p3; +reg [1:0] select_ln47_4_reg_1003; +wire [9:0] add_ln55_fu_545_p2; +reg [9:0] add_ln55_reg_1010; +wire [1:0] select_ln48_3_fu_584_p3; +reg [1:0] select_ln48_3_reg_1016; +reg [2:0] lshr_ln_reg_1023; +reg [2:0] lshr_ln_reg_1023_pp0_iter1_reg; +reg [2:0] lshr_ln_reg_1023_pp0_iter2_reg; +wire [5:0] add_ln49_fu_602_p2; +wire [5:0] select_ln48_4_fu_614_p3; +wire [5:0] add_ln55_4_fu_678_p2; +reg [5:0] add_ln55_4_reg_1039; +reg [5:0] add_ln55_4_reg_1039_pp0_iter2_reg; +reg [63:0] filter_data_0_load_reg_1064; +reg [63:0] filter_data_1_load_reg_1069; +reg [63:0] filter_data_2_load_reg_1074; +reg [63:0] filter_data_3_load_reg_1079; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg [1:0] ap_phi_mux_ii_phi_fu_427_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_449_p4; +wire [63:0] tmp_16_fu_684_p3; +wire [63:0] sext_ln55_4_fu_701_p1; +wire [7:0] tmp_s_fu_471_p3; +wire [8:0] zext_ln55_8_fu_479_p1; +wire [8:0] zext_ln55_fu_467_p1; +wire [8:0] sub_ln55_fu_483_p2; +wire [0:0] icmp_ln48_fu_511_p2; +wire [1:0] add_ln47_fu_505_p2; +wire [9:0] zext_ln55_10_fu_541_p1; +wire [0:0] tmp_24_fu_550_p3; +wire [0:0] xor_ln49_fu_558_p2; +wire [1:0] select_ln47_fu_517_p3; +wire [0:0] or_ln47_fu_564_p2; +wire [5:0] select_ln47_3_fu_525_p3; +wire [1:0] add_ln48_fu_570_p2; +wire [5:0] select_ln48_fu_576_p3; +wire [5:0] add_ln48_2_fu_608_p2; +wire [11:0] tmp_23_fu_628_p3; +wire [60:0] sext_ln55_3_fu_635_p1; +wire [60:0] sext_ln55_fu_625_p1; +wire [3:0] tmp_15_fu_645_p3; +wire [4:0] zext_ln55_11_fu_652_p1; +wire [4:0] zext_ln55_9_fu_622_p1; +wire [4:0] sub_ln55_4_fu_656_p2; +wire [60:0] sub_ln55_3_fu_639_p2; +wire [60:0] zext_ln55_13_fu_669_p1; +wire [5:0] sext_ln48_fu_662_p1; +wire [5:0] zext_ln55_12_fu_666_p1; +wire [60:0] add_ln55_3_fu_672_p2; +wire [8:0] tmp_25_fu_695_p3; +wire [63:0] tmp_fu_721_p6; +wire [15:0] trunc_ln55_fu_734_p1; +wire [63:0] tmp_4_fu_743_p6; +wire [15:0] trunc_ln55_4_fu_756_p1; +wire [63:0] tmp_5_fu_765_p6; +wire [15:0] trunc_ln55_5_fu_778_p1; +wire [63:0] tmp_6_fu_787_p6; +wire [15:0] trunc_ln55_6_fu_800_p1; +wire [15:0] tmp_45_i_i_fu_809_p4; +wire [15:0] tmp_47_i_i_fu_824_p4; +wire [15:0] tmp_49_i_i_fu_839_p4; +wire [15:0] tmp_51_i_i_fu_854_p4; +wire [15:0] tmp_53_i_i_fu_869_p4; +wire [15:0] tmp_55_i_i_fu_884_p4; +wire [15:0] tmp_57_i_i_fu_899_p4; +wire [15:0] tmp_59_i_i_fu_914_p4; +wire [15:0] tmp_61_i_i_fu_929_p4; +wire [15:0] tmp_63_i_i_fu_944_p4; +wire [15:0] tmp_65_i_i_fu_959_p4; +wire [15:0] tmp_67_i_i_fu_974_p4; +wire ap_CS_fsm_state6; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +end + +td_fused_top_mux_416_64_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 64 ), + .din1_WIDTH( 64 ), + .din2_WIDTH( 64 ), + .din3_WIDTH( 64 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 64 )) +mux_416_64_1_1_U951( + .din0(filter_data_0_load_reg_1064), + .din1(64'd0), + .din2(64'd0), + .din3(64'd0), + .din4(16'd0), + .dout(tmp_fu_721_p6) +); + +td_fused_top_mux_416_64_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 64 ), + .din1_WIDTH( 64 ), + .din2_WIDTH( 64 ), + .din3_WIDTH( 64 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 64 )) +mux_416_64_1_1_U952( + .din0(filter_data_1_load_reg_1069), + .din1(64'd0), + .din2(64'd0), + .din3(64'd0), + .din4(16'd0), + .dout(tmp_4_fu_743_p6) +); + +td_fused_top_mux_416_64_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 64 ), + .din1_WIDTH( 64 ), + .din2_WIDTH( 64 ), + .din3_WIDTH( 64 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 64 )) +mux_416_64_1_1_U953( + .din0(filter_data_2_load_reg_1074), + .din1(64'd0), + .din2(64'd0), + .din3(64'd0), + .din4(16'd0), + .dout(tmp_5_fu_765_p6) +); + +td_fused_top_mux_416_64_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 64 ), + .din1_WIDTH( 64 ), + .din2_WIDTH( 64 ), + .din3_WIDTH( 64 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 64 )) +mux_416_64_1_1_U954( + .din0(filter_data_3_load_reg_1079), + .din1(64'd0), + .din2(64'd0), + .din3(64'd0), + .din4(16'd0), + .dout(tmp_6_fu_787_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_999 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_423 <= select_ln47_4_reg_1003; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_423 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_499_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten13_reg_412 <= add_ln47_2_fu_493_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_412 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_499_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten_reg_434 <= select_ln48_4_fu_614_p3; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_434 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_999 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_445 <= select_ln48_3_reg_1016; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_445 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_499_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + kk_reg_456 <= add_ln49_fu_602_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_456 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_999 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln55_4_reg_1039 <= add_ln55_4_fu_678_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln55_4_reg_1039_pp0_iter2_reg <= add_ln55_4_reg_1039; + icmp_ln47_reg_999_pp0_iter2_reg <= icmp_ln47_reg_999_pp0_iter1_reg; + lshr_ln_reg_1023_pp0_iter2_reg <= lshr_ln_reg_1023_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_499_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln55_reg_1010 <= add_ln55_fu_545_p2; + lshr_ln_reg_1023 <= {{select_ln48_fu_576_p3[4:2]}}; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_999_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_0_load_reg_1064 <= filter_data_0_q0; + filter_data_1_load_reg_1069 <= filter_data_1_q0; + filter_data_2_load_reg_1074 <= filter_data_2_q0; + filter_data_3_load_reg_1079 <= filter_data_3_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln47_reg_999 <= icmp_ln47_fu_499_p2; + icmp_ln47_reg_999_pp0_iter1_reg <= icmp_ln47_reg_999; + lshr_ln_reg_1023_pp0_iter1_reg <= lshr_ln_reg_1023; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_499_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln47_4_reg_1003 <= select_ln47_4_fu_533_p3; + select_ln48_3_reg_1016 <= select_ln48_3_fu_584_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sext_ln47_reg_989 <= sext_ln47_fu_489_p1; + end +end + +always @ (*) begin + if ((icmp_ln47_fu_499_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_999 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_427_p4 = select_ln47_4_reg_1003; + end else begin + ap_phi_mux_ii_phi_fu_427_p4 = ii_reg_423; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_999 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_449_p4 = select_ln48_3_reg_1016; + end else begin + ap_phi_mux_jj_phi_fu_449_p4 = jj_reg_445; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_0_ce0 = 1'b1; + end else begin + filter_data_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_1_ce0 = 1'b1; + end else begin + filter_data_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_2_ce0 = 1'b1; + end else begin + filter_data_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_3_ce0 = 1'b1; + end else begin + filter_data_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_ce0 = 1'b1; + end else begin + weight_vecs_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_we0 = 1'b1; + end else begin + weight_vecs_0_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_2_ce0 = 1'b1; + end else begin + weight_vecs_0_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_2_we0 = 1'b1; + end else begin + weight_vecs_0_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_3_ce0 = 1'b1; + end else begin + weight_vecs_0_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_3_we0 = 1'b1; + end else begin + weight_vecs_0_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_ce0 = 1'b1; + end else begin + weight_vecs_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_we0 = 1'b1; + end else begin + weight_vecs_1_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_ce0 = 1'b1; + end else begin + weight_vecs_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_we0 = 1'b1; + end else begin + weight_vecs_1_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_2_ce0 = 1'b1; + end else begin + weight_vecs_1_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_2_we0 = 1'b1; + end else begin + weight_vecs_1_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_3_ce0 = 1'b1; + end else begin + weight_vecs_1_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_3_we0 = 1'b1; + end else begin + weight_vecs_1_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_0_ce0 = 1'b1; + end else begin + weight_vecs_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_0_we0 = 1'b1; + end else begin + weight_vecs_2_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_1_ce0 = 1'b1; + end else begin + weight_vecs_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_1_we0 = 1'b1; + end else begin + weight_vecs_2_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_2_ce0 = 1'b1; + end else begin + weight_vecs_2_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_2_we0 = 1'b1; + end else begin + weight_vecs_2_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_3_ce0 = 1'b1; + end else begin + weight_vecs_2_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_3_we0 = 1'b1; + end else begin + weight_vecs_2_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_0_ce0 = 1'b1; + end else begin + weight_vecs_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_0_we0 = 1'b1; + end else begin + weight_vecs_3_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_1_ce0 = 1'b1; + end else begin + weight_vecs_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_1_we0 = 1'b1; + end else begin + weight_vecs_3_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_2_ce0 = 1'b1; + end else begin + weight_vecs_3_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_2_we0 = 1'b1; + end else begin + weight_vecs_3_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_3_ce0 = 1'b1; + end else begin + weight_vecs_3_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_999_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_3_we0 = 1'b1; + end else begin + weight_vecs_3_3_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln47_fu_499_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln47_fu_499_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln47_2_fu_493_p2 = (indvar_flatten13_reg_412 + 7'd1); + +assign add_ln47_fu_505_p2 = (ap_phi_mux_ii_phi_fu_427_p4 + 2'd1); + +assign add_ln48_2_fu_608_p2 = (indvar_flatten_reg_434 + 6'd1); + +assign add_ln48_fu_570_p2 = (select_ln47_fu_517_p3 + 2'd1); + +assign add_ln49_fu_602_p2 = (select_ln48_fu_576_p3 + 6'd4); + +assign add_ln55_3_fu_672_p2 = (sub_ln55_3_fu_639_p2 + zext_ln55_13_fu_669_p1); + +assign add_ln55_4_fu_678_p2 = ((sext_ln48_fu_662_p1) + (zext_ln55_12_fu_666_p1)); + +assign add_ln55_fu_545_p2 = ((sext_ln47_reg_989) + (zext_ln55_10_fu_541_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_0_address0 = tmp_16_fu_684_p3; + +assign filter_data_1_address0 = tmp_16_fu_684_p3; + +assign filter_data_2_address0 = tmp_16_fu_684_p3; + +assign filter_data_3_address0 = tmp_16_fu_684_p3; + +assign icmp_ln47_fu_499_p2 = ((indvar_flatten13_reg_412 == 7'd72) ? 1'b1 : 1'b0); + +assign icmp_ln48_fu_511_p2 = ((indvar_flatten_reg_434 == 6'd24) ? 1'b1 : 1'b0); + +assign or_ln47_fu_564_p2 = (xor_ln49_fu_558_p2 | icmp_ln48_fu_511_p2); + +assign select_ln47_3_fu_525_p3 = ((icmp_ln48_fu_511_p2[0:0] == 1'b1) ? 6'd0 : kk_reg_456); + +assign select_ln47_4_fu_533_p3 = ((icmp_ln48_fu_511_p2[0:0] == 1'b1) ? add_ln47_fu_505_p2 : ap_phi_mux_ii_phi_fu_427_p4); + +assign select_ln47_fu_517_p3 = ((icmp_ln48_fu_511_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_449_p4); + +assign select_ln48_3_fu_584_p3 = ((or_ln47_fu_564_p2[0:0] == 1'b1) ? select_ln47_fu_517_p3 : add_ln48_fu_570_p2); + +assign select_ln48_4_fu_614_p3 = ((icmp_ln48_fu_511_p2[0:0] == 1'b1) ? 6'd1 : add_ln48_2_fu_608_p2); + +assign select_ln48_fu_576_p3 = ((or_ln47_fu_564_p2[0:0] == 1'b1) ? select_ln47_3_fu_525_p3 : 6'd0); + +assign sext_ln47_fu_489_p1 = (sub_ln55_fu_483_p2); + +assign sext_ln48_fu_662_p1 = (sub_ln55_4_fu_656_p2); + +assign sext_ln55_3_fu_635_p1 = (tmp_23_fu_628_p3); + +assign sext_ln55_4_fu_701_p1 = (tmp_25_fu_695_p3); + +assign sext_ln55_fu_625_p1 = add_ln55_reg_1010; + +assign sub_ln55_3_fu_639_p2 = ((sext_ln55_3_fu_635_p1) - (sext_ln55_fu_625_p1)); + +assign sub_ln55_4_fu_656_p2 = (zext_ln55_11_fu_652_p1 - zext_ln55_9_fu_622_p1); + +assign sub_ln55_fu_483_p2 = (zext_ln55_8_fu_479_p1 - zext_ln55_fu_467_p1); + +assign tmp_15_fu_645_p3 = {{select_ln47_4_reg_1003}, {2'd0}}; + +assign tmp_16_fu_684_p3 = {{add_ln55_3_fu_672_p2}, {lshr_ln_reg_1023}}; + +assign tmp_23_fu_628_p3 = {{add_ln55_reg_1010}, {2'd0}}; + +assign tmp_24_fu_550_p3 = kk_reg_456[32'd5]; + +assign tmp_25_fu_695_p3 = {{add_ln55_4_reg_1039_pp0_iter2_reg}, {lshr_ln_reg_1023_pp0_iter2_reg}}; + +assign tmp_45_i_i_fu_809_p4 = {{tmp_fu_721_p6[31:16]}}; + +assign tmp_47_i_i_fu_824_p4 = {{tmp_4_fu_743_p6[31:16]}}; + +assign tmp_49_i_i_fu_839_p4 = {{tmp_5_fu_765_p6[31:16]}}; + +assign tmp_51_i_i_fu_854_p4 = {{tmp_6_fu_787_p6[31:16]}}; + +assign tmp_53_i_i_fu_869_p4 = {{tmp_fu_721_p6[47:32]}}; + +assign tmp_55_i_i_fu_884_p4 = {{tmp_4_fu_743_p6[47:32]}}; + +assign tmp_57_i_i_fu_899_p4 = {{tmp_5_fu_765_p6[47:32]}}; + +assign tmp_59_i_i_fu_914_p4 = {{tmp_6_fu_787_p6[47:32]}}; + +assign tmp_61_i_i_fu_929_p4 = {{tmp_fu_721_p6[63:48]}}; + +assign tmp_63_i_i_fu_944_p4 = {{tmp_4_fu_743_p6[63:48]}}; + +assign tmp_65_i_i_fu_959_p4 = {{tmp_5_fu_765_p6[63:48]}}; + +assign tmp_67_i_i_fu_974_p4 = {{tmp_6_fu_787_p6[63:48]}}; + +assign tmp_s_fu_471_p3 = {{indices_23_dout}, {2'd0}}; + +assign trunc_ln55_4_fu_756_p1 = tmp_4_fu_743_p6[15:0]; + +assign trunc_ln55_5_fu_778_p1 = tmp_5_fu_765_p6[15:0]; + +assign trunc_ln55_6_fu_800_p1 = tmp_6_fu_787_p6[15:0]; + +assign trunc_ln55_fu_734_p1 = tmp_fu_721_p6[15:0]; + +assign weight_vecs_0_0_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_0_0_d0 = trunc_ln55_fu_734_p1; + +assign weight_vecs_0_1_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_0_1_d0 = tmp_45_i_i_fu_809_p4; + +assign weight_vecs_0_2_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_0_2_d0 = tmp_53_i_i_fu_869_p4; + +assign weight_vecs_0_3_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_0_3_d0 = tmp_61_i_i_fu_929_p4; + +assign weight_vecs_1_0_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_1_0_d0 = trunc_ln55_4_fu_756_p1; + +assign weight_vecs_1_1_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_1_1_d0 = tmp_47_i_i_fu_824_p4; + +assign weight_vecs_1_2_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_1_2_d0 = tmp_55_i_i_fu_884_p4; + +assign weight_vecs_1_3_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_1_3_d0 = tmp_63_i_i_fu_944_p4; + +assign weight_vecs_2_0_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_2_0_d0 = trunc_ln55_5_fu_778_p1; + +assign weight_vecs_2_1_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_2_1_d0 = tmp_49_i_i_fu_839_p4; + +assign weight_vecs_2_2_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_2_2_d0 = tmp_57_i_i_fu_899_p4; + +assign weight_vecs_2_3_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_2_3_d0 = tmp_65_i_i_fu_959_p4; + +assign weight_vecs_3_0_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_3_0_d0 = trunc_ln55_6_fu_800_p1; + +assign weight_vecs_3_1_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_3_1_d0 = tmp_51_i_i_fu_854_p4; + +assign weight_vecs_3_2_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_3_2_d0 = tmp_59_i_i_fu_914_p4; + +assign weight_vecs_3_3_address0 = sext_ln55_4_fu_701_p1; + +assign weight_vecs_3_3_d0 = tmp_67_i_i_fu_974_p4; + +assign xor_ln49_fu_558_p2 = (tmp_24_fu_550_p3 ^ 1'd1); + +assign zext_ln55_10_fu_541_p1 = select_ln47_4_fu_533_p3; + +assign zext_ln55_11_fu_652_p1 = tmp_15_fu_645_p3; + +assign zext_ln55_12_fu_666_p1 = select_ln48_3_reg_1016; + +assign zext_ln55_13_fu_669_p1 = select_ln48_3_reg_1016; + +assign zext_ln55_8_fu_479_p1 = tmp_s_fu_471_p3; + +assign zext_ln55_9_fu_622_p1 = select_ln47_4_reg_1003; + +assign zext_ln55_fu_467_p1 = indices_23_dout; + +endmodule //td_fused_top_tdf7_readFilters53 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_readInputs54 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_0_address0, + ifmap_vec_0_ce0, + ifmap_vec_0_we0, + ifmap_vec_0_d0, + ifmap_vec_1_address0, + ifmap_vec_1_ce0, + ifmap_vec_1_we0, + ifmap_vec_1_d0, + ifmap_vec_2_address0, + ifmap_vec_2_ce0, + ifmap_vec_2_we0, + ifmap_vec_2_d0, + ifmap_vec_3_address0, + ifmap_vec_3_ce0, + ifmap_vec_3_we0, + ifmap_vec_3_d0, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_pp0_stage0 = 4'd4; +parameter ap_ST_fsm_state8 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [12:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [6:0] ifmap_vec_0_address0; +output ifmap_vec_0_ce0; +output ifmap_vec_0_we0; +output [15:0] ifmap_vec_0_d0; +output [6:0] ifmap_vec_1_address0; +output ifmap_vec_1_ce0; +output ifmap_vec_1_we0; +output [15:0] ifmap_vec_1_d0; +output [6:0] ifmap_vec_2_address0; +output ifmap_vec_2_ce0; +output ifmap_vec_2_we0; +output [15:0] ifmap_vec_2_d0; +output [6:0] ifmap_vec_3_address0; +output ifmap_vec_3_ce0; +output ifmap_vec_3_we0; +output [15:0] ifmap_vec_3_d0; +output [4:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [9:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg ifmap_vec_0_ce0; +reg ifmap_vec_0_we0; +reg ifmap_vec_1_ce0; +reg ifmap_vec_1_we0; +reg ifmap_vec_2_ce0; +reg ifmap_vec_2_we0; +reg ifmap_vec_3_ce0; +reg ifmap_vec_3_we0; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [6:0] indvar_flatten47_reg_231; +reg [1:0] ii_reg_242; +reg [5:0] indvar_flatten_reg_254; +reg [1:0] jj_reg_265; +reg [5:0] kk_reg_277; +reg [15:0] indices_01_read_reg_905; +wire [4:0] trunc_ln289_fu_288_p1; +reg [4:0] trunc_ln289_reg_910; +reg [15:0] indices_12_read_reg_915; +wire [9:0] empty_fu_293_p1; +reg [9:0] empty_reg_920; +wire [17:0] p_cast_i_i_fu_310_p1; +reg [17:0] p_cast_i_i_reg_927; +wire ap_CS_fsm_state2; +wire [17:0] sext_ln22_fu_320_p1; +reg [17:0] sext_ln22_reg_933; +wire [4:0] p_cast_fu_324_p2; +reg [4:0] p_cast_reg_939; +wire [0:0] or_ln23_6_fu_343_p2; +reg [0:0] or_ln23_6_reg_945; +wire [9:0] p_mid137_fu_349_p2; +reg [9:0] p_mid137_reg_950; +wire [6:0] add_ln19_2_fu_354_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state4_pp0_stage0_iter1; +wire ap_block_state5_pp0_stage0_iter2; +wire ap_block_state6_pp0_stage0_iter3; +wire ap_block_state7_pp0_stage0_iter4; +wire ap_block_pp0_stage0_11001; +wire [0:0] empty_83_fu_369_p2; +reg [0:0] empty_83_reg_960; +wire [0:0] is_padding_fu_404_p2; +reg [0:0] is_padding_reg_965; +wire [0:0] icmp_ln19_fu_410_p2; +reg [0:0] icmp_ln19_reg_972; +reg [0:0] icmp_ln19_reg_972_pp0_iter1_reg; +reg [0:0] icmp_ln19_reg_972_pp0_iter2_reg; +reg [0:0] icmp_ln19_reg_972_pp0_iter3_reg; +wire [1:0] add_ln19_fu_416_p2; +reg [1:0] add_ln19_reg_976; +wire [0:0] icmp_ln20_fu_422_p2; +reg [0:0] icmp_ln20_reg_981; +wire [1:0] select_ln19_9_fu_444_p3; +reg [1:0] select_ln19_9_reg_990; +wire [0:0] p_mid113_fu_461_p2; +reg [0:0] p_mid113_reg_997; +wire [0:0] or_ln19_fu_481_p2; +reg [0:0] or_ln19_reg_1003; +reg [0:0] or_ln19_reg_1003_pp0_iter1_reg; +wire [1:0] add_ln20_fu_487_p2; +reg [1:0] add_ln20_reg_1010; +wire [1:0] select_ln20_6_fu_501_p3; +reg [1:0] select_ln20_6_reg_1015; +wire [17:0] add_ln22_3_fu_513_p2; +reg [17:0] add_ln22_3_reg_1021; +reg [2:0] lshr_ln_reg_1027; +reg [2:0] lshr_ln_reg_1027_pp0_iter1_reg; +reg [2:0] lshr_ln_reg_1027_pp0_iter2_reg; +reg [2:0] lshr_ln_reg_1027_pp0_iter3_reg; +wire [5:0] add_ln25_fu_528_p2; +wire [5:0] select_ln20_10_fu_540_p3; +wire [9:0] select_ln19_14_fu_666_p3; +reg [9:0] select_ln19_14_reg_1043; +wire [5:0] add_ln33_fu_676_p2; +reg [5:0] add_ln33_reg_1048; +reg [5:0] add_ln33_reg_1048_pp0_iter2_reg; +reg [5:0] add_ln33_reg_1048_pp0_iter3_reg; +wire [0:0] or_ln23_10_fu_703_p2; +reg [0:0] or_ln23_10_reg_1053; +wire [0:0] select_ln20_7_fu_709_p3; +reg [0:0] select_ln20_7_reg_1058; +reg [0:0] select_ln20_7_reg_1058_pp0_iter2_reg; +wire [9:0] p_mid1_fu_734_p2; +reg [9:0] p_mid1_reg_1066; +wire [10:0] sub_ln32_fu_770_p2; +reg [10:0] sub_ln32_reg_1071; +wire [15:0] select_ln33_fu_821_p3; +reg [15:0] select_ln33_reg_1081; +wire [15:0] select_ln33_5_fu_842_p3; +reg [15:0] select_ln33_5_reg_1086; +wire [15:0] select_ln33_6_fu_863_p3; +reg [15:0] select_ln33_6_reg_1091; +wire [15:0] select_ln33_7_fu_884_p3; +reg [15:0] select_ln33_7_reg_1096; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state4; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg [1:0] ap_phi_mux_ii_phi_fu_246_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_269_p4; +wire [63:0] sext_ln32_fu_808_p1; +wire [63:0] sext_ln33_fu_897_p1; +reg ap_block_state1; +wire [16:0] zext_ln19_fu_301_p1; +wire [16:0] empty_81_fu_304_p2; +wire [16:0] j_cast_i_i_fu_298_p1; +wire [16:0] add_ln22_fu_314_p2; +wire [0:0] tmp_17_fu_329_p3; +wire [0:0] icmp_ln24_fu_337_p2; +wire [17:0] ii_cast_i_i_fu_360_p1; +wire [17:0] empty_82_fu_364_p2; +wire [17:0] zext_ln20_fu_375_p1; +wire [17:0] add_ln22_2_fu_379_p2; +wire [0:0] tmp_18_fu_384_p3; +wire [0:0] icmp_ln24_2_fu_392_p2; +wire [0:0] or_ln23_fu_398_p2; +wire [17:0] ii_cast_i_i_mid1_fu_452_p1; +wire [17:0] p_mid111_fu_456_p2; +wire [0:0] tmp_19_fu_467_p3; +wire [0:0] xor_ln25_fu_475_p2; +wire [1:0] select_ln19_fu_428_p3; +wire [5:0] select_ln19_8_fu_436_p3; +wire [17:0] zext_ln20_2_fu_509_p1; +wire [5:0] select_ln20_fu_493_p3; +wire [5:0] add_ln20_2_fu_534_p2; +wire [4:0] ii_cast_fu_548_p1; +wire [4:0] p_cast28_i_i_fu_552_p2; +wire [2:0] zext_ln22_fu_557_p1; +wire [2:0] tmp1_fu_568_p2; +wire [9:0] tmp1_cast_fu_574_p1; +wire [9:0] empty_84_fu_578_p2; +wire [3:0] tmp_fu_593_p3; +wire [4:0] zext_ln33_4_fu_600_p1; +wire [4:0] zext_ln33_fu_590_p1; +wire [4:0] sub_ln33_fu_604_p2; +wire [4:0] ii_cast_mid1_fu_614_p1; +wire [4:0] p_cast28_i_i_mid1_fu_617_p2; +wire [0:0] or_ln23_8_fu_634_p2; +wire [4:0] row_coord_int_mid131_fu_644_p3; +wire [4:0] row_coord_int_fu_561_p3; +wire [9:0] col_coord_int_mid139_fu_652_p3; +wire [9:0] col_coord_int_fu_583_p3; +wire [5:0] sub_ln33_cast_fu_610_p1; +wire [5:0] zext_ln33_5_fu_673_p1; +wire [0:0] tmp_20_fu_685_p3; +wire [0:0] icmp_ln24_3_fu_692_p2; +wire [0:0] or_ln23_9_fu_697_p2; +wire [0:0] select_ln19_11_fu_629_p3; +wire [0:0] select_ln19_12_fu_638_p3; +wire [4:0] select_ln19_10_fu_622_p3; +wire [2:0] zext_ln22_2_fu_682_p1; +wire [2:0] tmp1_mid1_fu_724_p2; +wire [9:0] tmp1_cast_mid1_fu_730_p1; +wire [4:0] select_ln19_13_fu_659_p3; +wire [4:0] row_coord_int_mid1_fu_716_p3; +wire [4:0] select_ln20_8_fu_739_p3; +wire [9:0] tmp_s_fu_746_p3; +wire [6:0] tmp_14_fu_758_p3; +wire [10:0] zext_ln32_fu_754_p1; +wire [10:0] zext_ln32_17_fu_766_p1; +wire [9:0] col_coord_int_mid1_fu_776_p3; +wire [9:0] select_ln20_9_fu_785_p3; +wire [11:0] sext_ln20_fu_782_p1; +wire [11:0] zext_ln32_18_fu_791_p1; +wire [11:0] add_ln32_fu_795_p2; +wire [14:0] tmp_21_fu_801_p3; +wire [15:0] trunc_ln32_fu_813_p1; +wire [15:0] in_data_elem_fu_817_p1; +wire [15:0] tmp_34_i_i_fu_828_p4; +wire [15:0] in_data_elem_2_fu_838_p1; +wire [15:0] tmp_35_i_i_fu_849_p4; +wire [15:0] in_data_elem_3_fu_859_p1; +wire [15:0] tmp_36_i_i_fu_870_p4; +wire [15:0] in_data_elem_4_fu_880_p1; +wire [8:0] tmp_22_fu_891_p3; +wire ap_CS_fsm_state8; +reg [3:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state4)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_972 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_242 <= select_ln19_9_reg_990; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ii_reg_242 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten47_reg_231 <= add_ln19_2_fu_354_p2; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + indvar_flatten47_reg_231 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten_reg_254 <= select_ln20_10_fu_540_p3; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + indvar_flatten_reg_254 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_972 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_265 <= select_ln20_6_reg_1015; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + jj_reg_265 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + kk_reg_277 <= add_ln25_fu_528_p2; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + kk_reg_277 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln19_reg_976 <= add_ln19_fu_416_p2; + add_ln20_reg_1010 <= add_ln20_fu_487_p2; + add_ln22_3_reg_1021 <= add_ln22_3_fu_513_p2; + icmp_ln20_reg_981 <= icmp_ln20_fu_422_p2; + lshr_ln_reg_1027 <= {{select_ln20_fu_493_p3[4:2]}}; + or_ln19_reg_1003 <= or_ln19_fu_481_p2; + p_mid113_reg_997 <= p_mid113_fu_461_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_972 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln33_reg_1048 <= add_ln33_fu_676_p2; + or_ln23_10_reg_1053 <= or_ln23_10_fu_703_p2; + select_ln20_7_reg_1058 <= select_ln20_7_fu_709_p3; + sub_ln32_reg_1071[10 : 2] <= sub_ln32_fu_770_p2[10 : 2]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln33_reg_1048_pp0_iter2_reg <= add_ln33_reg_1048; + add_ln33_reg_1048_pp0_iter3_reg <= add_ln33_reg_1048_pp0_iter2_reg; + icmp_ln19_reg_972_pp0_iter2_reg <= icmp_ln19_reg_972_pp0_iter1_reg; + icmp_ln19_reg_972_pp0_iter3_reg <= icmp_ln19_reg_972_pp0_iter2_reg; + lshr_ln_reg_1027_pp0_iter2_reg <= lshr_ln_reg_1027_pp0_iter1_reg; + lshr_ln_reg_1027_pp0_iter3_reg <= lshr_ln_reg_1027_pp0_iter2_reg; + select_ln20_7_reg_1058_pp0_iter2_reg <= select_ln20_7_reg_1058; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + empty_83_reg_960 <= empty_83_fu_369_p2; + icmp_ln19_reg_972 <= icmp_ln19_fu_410_p2; + icmp_ln19_reg_972_pp0_iter1_reg <= icmp_ln19_reg_972; + is_padding_reg_965 <= is_padding_fu_404_p2; + lshr_ln_reg_1027_pp0_iter1_reg <= lshr_ln_reg_1027; + or_ln19_reg_1003_pp0_iter1_reg <= or_ln19_reg_1003; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + empty_reg_920 <= empty_fu_293_p1; + indices_01_read_reg_905 <= indices_01_dout; + indices_12_read_reg_915 <= indices_12_dout; + trunc_ln289_reg_910 <= trunc_ln289_fu_288_p1; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + or_ln23_6_reg_945 <= or_ln23_6_fu_343_p2; + p_cast_i_i_reg_927 <= p_cast_i_i_fu_310_p1; + p_cast_reg_939 <= p_cast_fu_324_p2; + p_mid137_reg_950 <= p_mid137_fu_349_p2; + sext_ln22_reg_933 <= sext_ln22_fu_320_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (or_ln19_reg_1003 == 1'd0) & (icmp_ln19_reg_972 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + p_mid1_reg_1066 <= p_mid1_fu_734_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (or_ln19_reg_1003 == 1'd1) & (icmp_ln19_reg_972 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + select_ln19_14_reg_1043 <= select_ln19_14_fu_666_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln19_9_reg_990 <= select_ln19_9_fu_444_p3; + select_ln20_6_reg_1015 <= select_ln20_6_fu_501_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_972_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + select_ln33_5_reg_1086 <= select_ln33_5_fu_842_p3; + select_ln33_6_reg_1091 <= select_ln33_6_fu_863_p3; + select_ln33_7_reg_1096 <= select_ln33_7_fu_884_p3; + select_ln33_reg_1081 <= select_ln33_fu_821_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_condition_pp0_exit_iter1_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state4 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_410_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_972 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_246_p4 = select_ln19_9_reg_990; + end else begin + ap_phi_mux_ii_phi_fu_246_p4 = ii_reg_242; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_972 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_269_p4 = select_ln20_6_reg_1015; + end else begin + ap_phi_mux_jj_phi_fu_269_p4 = jj_reg_265; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (icmp_ln19_reg_972_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_we0 = 1'b1; + end else begin + ifmap_vec_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_1_ce0 = 1'b1; + end else begin + ifmap_vec_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (icmp_ln19_reg_972_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_1_we0 = 1'b1; + end else begin + ifmap_vec_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_2_ce0 = 1'b1; + end else begin + ifmap_vec_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (icmp_ln19_reg_972_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_2_we0 = 1'b1; + end else begin + ifmap_vec_2_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_3_ce0 = 1'b1; + end else begin + ifmap_vec_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter4 == 1'b1) & (icmp_ln19_reg_972_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_3_we0 = 1'b1; + end else begin + ifmap_vec_3_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0)) & ~((ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state8; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln19_2_fu_354_p2 = (indvar_flatten47_reg_231 + 7'd1); + +assign add_ln19_fu_416_p2 = (ap_phi_mux_ii_phi_fu_246_p4 + 2'd1); + +assign add_ln20_2_fu_534_p2 = (indvar_flatten_reg_254 + 6'd1); + +assign add_ln20_fu_487_p2 = (select_ln19_fu_428_p3 + 2'd1); + +assign add_ln22_2_fu_379_p2 = ((sext_ln22_reg_933) + (zext_ln20_fu_375_p1)); + +assign add_ln22_3_fu_513_p2 = ((sext_ln22_reg_933) + (zext_ln20_2_fu_509_p1)); + +assign add_ln22_fu_314_p2 = ((j_cast_i_i_fu_298_p1) + (17'd131071)); + +assign add_ln25_fu_528_p2 = (select_ln20_fu_493_p3 + 6'd4); + +assign add_ln32_fu_795_p2 = ((sext_ln20_fu_782_p1) + (zext_ln32_18_fu_791_p1)); + +assign add_ln33_fu_676_p2 = ((sub_ln33_cast_fu_610_p1) + (zext_ln33_5_fu_673_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd3]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign col_coord_int_fu_583_p3 = ((is_padding_reg_965[0:0] == 1'b1) ? 10'd0 : empty_84_fu_578_p2); + +assign col_coord_int_mid139_fu_652_p3 = ((or_ln23_8_fu_634_p2[0:0] == 1'b1) ? 10'd0 : p_mid137_reg_950); + +assign col_coord_int_mid1_fu_776_p3 = ((or_ln23_10_reg_1053[0:0] == 1'b1) ? 10'd0 : p_mid1_reg_1066); + +assign empty_81_fu_304_p2 = ((zext_ln19_fu_301_p1) + (17'd131071)); + +assign empty_82_fu_364_p2 = ((p_cast_i_i_reg_927) + (ii_cast_i_i_fu_360_p1)); + +assign empty_83_fu_369_p2 = ((empty_82_fu_364_p2 > 18'd27) ? 1'b1 : 1'b0); + +assign empty_84_fu_578_p2 = ((tmp1_cast_fu_574_p1) + (empty_reg_920)); + +assign empty_fu_293_p1 = indices_12_dout[9:0]; + +assign icmp_ln19_fu_410_p2 = ((indvar_flatten47_reg_231 == 7'd72) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_422_p2 = ((indvar_flatten_reg_254 == 6'd24) ? 1'b1 : 1'b0); + +assign icmp_ln24_2_fu_392_p2 = (((add_ln22_2_fu_379_p2) > (18'd27)) ? 1'b1 : 1'b0); + +assign icmp_ln24_3_fu_692_p2 = (((add_ln22_3_reg_1021) > (18'd27)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_337_p2 = (((add_ln22_fu_314_p2) > (17'd27)) ? 1'b1 : 1'b0); + +assign ifmap_vec_0_address0 = sext_ln33_fu_897_p1; + +assign ifmap_vec_0_d0 = select_ln33_reg_1081; + +assign ifmap_vec_1_address0 = sext_ln33_fu_897_p1; + +assign ifmap_vec_1_d0 = select_ln33_5_reg_1086; + +assign ifmap_vec_2_address0 = sext_ln33_fu_897_p1; + +assign ifmap_vec_2_d0 = select_ln33_6_reg_1091; + +assign ifmap_vec_3_address0 = sext_ln33_fu_897_p1; + +assign ifmap_vec_3_d0 = select_ln33_7_reg_1096; + +assign ii_cast_fu_548_p1 = ii_reg_242; + +assign ii_cast_i_i_fu_360_p1 = ap_phi_mux_ii_phi_fu_246_p4; + +assign ii_cast_i_i_mid1_fu_452_p1 = add_ln19_fu_416_p2; + +assign ii_cast_mid1_fu_614_p1 = add_ln19_reg_976; + +assign in_data_address0 = sext_ln32_fu_808_p1; + +assign in_data_elem_2_fu_838_p1 = tmp_34_i_i_fu_828_p4; + +assign in_data_elem_3_fu_859_p1 = tmp_35_i_i_fu_849_p4; + +assign in_data_elem_4_fu_880_p1 = tmp_36_i_i_fu_870_p4; + +assign in_data_elem_fu_817_p1 = trunc_ln32_fu_813_p1; + +assign indices_01_out_din = indices_01_dout[4:0]; + +assign indices_12_out_din = indices_12_dout[9:0]; + +assign is_padding_fu_404_p2 = (or_ln23_fu_398_p2 | empty_83_fu_369_p2); + +assign j_cast_i_i_fu_298_p1 = indices_12_read_reg_915; + +assign or_ln19_fu_481_p2 = (xor_ln25_fu_475_p2 | icmp_ln20_fu_422_p2); + +assign or_ln23_10_fu_703_p2 = (select_ln19_11_fu_629_p3 | or_ln23_9_fu_697_p2); + +assign or_ln23_6_fu_343_p2 = (tmp_17_fu_329_p3 | icmp_ln24_fu_337_p2); + +assign or_ln23_8_fu_634_p2 = (p_mid113_reg_997 | or_ln23_6_reg_945); + +assign or_ln23_9_fu_697_p2 = (tmp_20_fu_685_p3 | icmp_ln24_3_fu_692_p2); + +assign or_ln23_fu_398_p2 = (tmp_18_fu_384_p3 | icmp_ln24_2_fu_392_p2); + +assign p_cast28_i_i_fu_552_p2 = (p_cast_reg_939 + ii_cast_fu_548_p1); + +assign p_cast28_i_i_mid1_fu_617_p2 = (p_cast_reg_939 + ii_cast_mid1_fu_614_p1); + +assign p_cast_fu_324_p2 = ((trunc_ln289_reg_910) + (5'd31)); + +assign p_cast_i_i_fu_310_p1 = (empty_81_fu_304_p2); + +assign p_mid111_fu_456_p2 = ((p_cast_i_i_reg_927) + (ii_cast_i_i_mid1_fu_452_p1)); + +assign p_mid113_fu_461_p2 = ((p_mid111_fu_456_p2 > 18'd27) ? 1'b1 : 1'b0); + +assign p_mid137_fu_349_p2 = ((empty_reg_920) + (10'd1023)); + +assign p_mid1_fu_734_p2 = ((tmp1_cast_mid1_fu_730_p1) + (empty_reg_920)); + +assign row_coord_int_fu_561_p3 = ((is_padding_reg_965[0:0] == 1'b1) ? 5'd0 : p_cast28_i_i_fu_552_p2); + +assign row_coord_int_mid131_fu_644_p3 = ((or_ln23_8_fu_634_p2[0:0] == 1'b1) ? 5'd0 : p_cast28_i_i_mid1_fu_617_p2); + +assign row_coord_int_mid1_fu_716_p3 = ((or_ln23_10_fu_703_p2[0:0] == 1'b1) ? 5'd0 : select_ln19_10_fu_622_p3); + +assign select_ln19_10_fu_622_p3 = ((icmp_ln20_reg_981[0:0] == 1'b1) ? p_cast28_i_i_mid1_fu_617_p2 : p_cast28_i_i_fu_552_p2); + +assign select_ln19_11_fu_629_p3 = ((icmp_ln20_reg_981[0:0] == 1'b1) ? p_mid113_reg_997 : empty_83_reg_960); + +assign select_ln19_12_fu_638_p3 = ((icmp_ln20_reg_981[0:0] == 1'b1) ? or_ln23_8_fu_634_p2 : is_padding_reg_965); + +assign select_ln19_13_fu_659_p3 = ((icmp_ln20_reg_981[0:0] == 1'b1) ? row_coord_int_mid131_fu_644_p3 : row_coord_int_fu_561_p3); + +assign select_ln19_14_fu_666_p3 = ((icmp_ln20_reg_981[0:0] == 1'b1) ? col_coord_int_mid139_fu_652_p3 : col_coord_int_fu_583_p3); + +assign select_ln19_8_fu_436_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? 6'd0 : kk_reg_277); + +assign select_ln19_9_fu_444_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? add_ln19_fu_416_p2 : ap_phi_mux_ii_phi_fu_246_p4); + +assign select_ln19_fu_428_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_269_p4); + +assign select_ln20_10_fu_540_p3 = ((icmp_ln20_fu_422_p2[0:0] == 1'b1) ? 6'd1 : add_ln20_2_fu_534_p2); + +assign select_ln20_6_fu_501_p3 = ((or_ln19_fu_481_p2[0:0] == 1'b1) ? select_ln19_fu_428_p3 : add_ln20_fu_487_p2); + +assign select_ln20_7_fu_709_p3 = ((or_ln19_reg_1003[0:0] == 1'b1) ? select_ln19_12_fu_638_p3 : or_ln23_10_fu_703_p2); + +assign select_ln20_8_fu_739_p3 = ((or_ln19_reg_1003[0:0] == 1'b1) ? select_ln19_13_fu_659_p3 : row_coord_int_mid1_fu_716_p3); + +assign select_ln20_9_fu_785_p3 = ((or_ln19_reg_1003_pp0_iter1_reg[0:0] == 1'b1) ? select_ln19_14_reg_1043 : col_coord_int_mid1_fu_776_p3); + +assign select_ln20_fu_493_p3 = ((or_ln19_fu_481_p2[0:0] == 1'b1) ? select_ln19_8_fu_436_p3 : 6'd0); + +assign select_ln33_5_fu_842_p3 = ((select_ln20_7_reg_1058_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_2_fu_838_p1); + +assign select_ln33_6_fu_863_p3 = ((select_ln20_7_reg_1058_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_3_fu_859_p1); + +assign select_ln33_7_fu_884_p3 = ((select_ln20_7_reg_1058_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_4_fu_880_p1); + +assign select_ln33_fu_821_p3 = ((select_ln20_7_reg_1058_pp0_iter2_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_fu_817_p1); + +assign sext_ln20_fu_782_p1 = (sub_ln32_reg_1071); + +assign sext_ln22_fu_320_p1 = add_ln22_fu_314_p2; + +assign sext_ln32_fu_808_p1 = (tmp_21_fu_801_p3); + +assign sext_ln33_fu_897_p1 = (tmp_22_fu_891_p3); + +assign sub_ln32_fu_770_p2 = (zext_ln32_fu_754_p1 - zext_ln32_17_fu_766_p1); + +assign sub_ln33_cast_fu_610_p1 = (sub_ln33_fu_604_p2); + +assign sub_ln33_fu_604_p2 = (zext_ln33_4_fu_600_p1 - zext_ln33_fu_590_p1); + +assign tmp1_cast_fu_574_p1 = (tmp1_fu_568_p2); + +assign tmp1_cast_mid1_fu_730_p1 = (tmp1_mid1_fu_724_p2); + +assign tmp1_fu_568_p2 = ((zext_ln22_fu_557_p1) + (3'd7)); + +assign tmp1_mid1_fu_724_p2 = ((zext_ln22_2_fu_682_p1) + (3'd7)); + +assign tmp_14_fu_758_p3 = {{select_ln20_8_fu_739_p3}, {2'd0}}; + +assign tmp_17_fu_329_p3 = add_ln22_fu_314_p2[32'd16]; + +assign tmp_18_fu_384_p3 = add_ln22_2_fu_379_p2[32'd17]; + +assign tmp_19_fu_467_p3 = kk_reg_277[32'd5]; + +assign tmp_20_fu_685_p3 = add_ln22_3_reg_1021[32'd17]; + +assign tmp_21_fu_801_p3 = {{add_ln32_fu_795_p2}, {lshr_ln_reg_1027_pp0_iter1_reg}}; + +assign tmp_22_fu_891_p3 = {{add_ln33_reg_1048_pp0_iter3_reg}, {lshr_ln_reg_1027_pp0_iter3_reg}}; + +assign tmp_34_i_i_fu_828_p4 = {{in_data_q0[31:16]}}; + +assign tmp_35_i_i_fu_849_p4 = {{in_data_q0[47:32]}}; + +assign tmp_36_i_i_fu_870_p4 = {{in_data_q0[63:48]}}; + +assign tmp_fu_593_p3 = {{select_ln19_9_reg_990}, {2'd0}}; + +assign tmp_s_fu_746_p3 = {{select_ln20_8_fu_739_p3}, {5'd0}}; + +assign trunc_ln289_fu_288_p1 = indices_01_dout[4:0]; + +assign trunc_ln32_fu_813_p1 = in_data_q0[15:0]; + +assign xor_ln25_fu_475_p2 = (tmp_19_fu_467_p3 ^ 1'd1); + +assign zext_ln19_fu_301_p1 = indices_01_read_reg_905; + +assign zext_ln20_2_fu_509_p1 = add_ln20_fu_487_p2; + +assign zext_ln20_fu_375_p1 = ap_phi_mux_jj_phi_fu_269_p4; + +assign zext_ln22_2_fu_682_p1 = add_ln20_reg_1010; + +assign zext_ln22_fu_557_p1 = jj_reg_265; + +assign zext_ln32_17_fu_766_p1 = tmp_14_fu_758_p3; + +assign zext_ln32_18_fu_791_p1 = select_ln20_9_fu_785_p3; + +assign zext_ln32_fu_754_p1 = tmp_s_fu_746_p3; + +assign zext_ln33_4_fu_600_p1 = tmp_fu_593_p3; + +assign zext_ln33_5_fu_673_p1 = select_ln20_6_reg_1015; + +assign zext_ln33_fu_590_p1 = select_ln19_9_reg_990; + +always @ (posedge ap_clk) begin + sub_ln32_reg_1071[1:0] <= 2'b00; +end + +endmodule //td_fused_top_tdf7_readInputs54 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_17 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_0_address0, + filter_data_0_ce0, + filter_data_0_d0, + filter_data_0_q0, + filter_data_0_we0, + filter_data_0_address1, + filter_data_0_ce1, + filter_data_0_d1, + filter_data_0_q1, + filter_data_0_we1, + filter_data_1_address0, + filter_data_1_ce0, + filter_data_1_d0, + filter_data_1_q0, + filter_data_1_we0, + filter_data_1_address1, + filter_data_1_ce1, + filter_data_1_d1, + filter_data_1_q1, + filter_data_1_we1, + filter_data_2_address0, + filter_data_2_ce0, + filter_data_2_d0, + filter_data_2_q0, + filter_data_2_we0, + filter_data_2_address1, + filter_data_2_ce1, + filter_data_2_d1, + filter_data_2_q1, + filter_data_2_we1, + filter_data_3_address0, + filter_data_3_ce0, + filter_data_3_d0, + filter_data_3_q0, + filter_data_3_we0, + filter_data_3_address1, + filter_data_3_ce1, + filter_data_3_d1, + filter_data_3_q1, + filter_data_3_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [12:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [12:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [13:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [13:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [13:0] filter_data_0_address0; +output filter_data_0_ce0; +output [31:0] filter_data_0_d0; +input [31:0] filter_data_0_q0; +output filter_data_0_we0; +output [13:0] filter_data_0_address1; +output filter_data_0_ce1; +output [31:0] filter_data_0_d1; +input [31:0] filter_data_0_q1; +output filter_data_0_we1; +output [13:0] filter_data_1_address0; +output filter_data_1_ce0; +output [31:0] filter_data_1_d0; +input [31:0] filter_data_1_q0; +output filter_data_1_we0; +output [13:0] filter_data_1_address1; +output filter_data_1_ce1; +output [31:0] filter_data_1_d1; +input [31:0] filter_data_1_q1; +output filter_data_1_we1; +output [13:0] filter_data_2_address0; +output filter_data_2_ce0; +output [31:0] filter_data_2_d0; +input [31:0] filter_data_2_q0; +output filter_data_2_we0; +output [13:0] filter_data_2_address1; +output filter_data_2_ce1; +output [31:0] filter_data_2_d1; +input [31:0] filter_data_2_q1; +output filter_data_2_we1; +output [13:0] filter_data_3_address0; +output filter_data_3_ce0; +output [31:0] filter_data_3_d0; +input [31:0] filter_data_3_q0; +output filter_data_3_we0; +output [13:0] filter_data_3_address1; +output filter_data_3_ce1; +output [31:0] filter_data_3_d1; +input [31:0] filter_data_3_q1; +output filter_data_3_we1; +output [7:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [7:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [12:0] dataflow_in_loop_TOP_LOOP47956_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP47956_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP47956_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP47956_U0_in_data_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP47956_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP47956_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP47956_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP47956_U0_in_data_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_address0; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_ce0; +wire [31:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_d0; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_address1; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_ce1; +wire [31:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_d1; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_address0; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_ce0; +wire [31:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_d0; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_address1; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_ce1; +wire [31:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_d1; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_address0; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_ce0; +wire [31:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_d0; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_address1; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_ce1; +wire [31:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_d1; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_address0; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_ce0; +wire [31:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_d0; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_address1; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_ce1; +wire [31:0] dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_d1; +wire dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_we1; +wire [7:0] dataflow_in_loop_TOP_LOOP47956_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP47956_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP47956_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP47956_U0_adjustments_we0; +wire [7:0] dataflow_in_loop_TOP_LOOP47956_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP47956_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP47956_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP47956_U0_adjustments_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP47956_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP47956_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP47956_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP47956_U0_out_data_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP47956_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP47956_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP47956_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP47956_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP47956_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP47956_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP47956_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP47956_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP47956_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP47956_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP47956_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP47956_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP47956_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [15:0] loop_dataflow_input_count; +reg [15:0] loop_dataflow_output_count; +wire [15:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP47956_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP47956_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 16'd0; +#0 loop_dataflow_output_count = 16'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP47956 dataflow_in_loop_TOP_LOOP47956_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP47956_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP47956_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP47956_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP47956_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP47956_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP47956_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP47956_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP47956_U0_in_data_we1), + .filter_data_0_address0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_address0), + .filter_data_0_ce0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_ce0), + .filter_data_0_d0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_d0), + .filter_data_0_q0(filter_data_0_q0), + .filter_data_0_we0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_we0), + .filter_data_0_address1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_address1), + .filter_data_0_ce1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_ce1), + .filter_data_0_d1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_d1), + .filter_data_0_q1(32'd0), + .filter_data_0_we1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_we1), + .filter_data_1_address0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_address0), + .filter_data_1_ce0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_ce0), + .filter_data_1_d0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_d0), + .filter_data_1_q0(filter_data_1_q0), + .filter_data_1_we0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_we0), + .filter_data_1_address1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_address1), + .filter_data_1_ce1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_ce1), + .filter_data_1_d1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_d1), + .filter_data_1_q1(32'd0), + .filter_data_1_we1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_we1), + .filter_data_2_address0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_address0), + .filter_data_2_ce0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_ce0), + .filter_data_2_d0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_d0), + .filter_data_2_q0(filter_data_2_q0), + .filter_data_2_we0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_we0), + .filter_data_2_address1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_address1), + .filter_data_2_ce1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_ce1), + .filter_data_2_d1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_d1), + .filter_data_2_q1(32'd0), + .filter_data_2_we1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_we1), + .filter_data_3_address0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_address0), + .filter_data_3_ce0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_ce0), + .filter_data_3_d0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_d0), + .filter_data_3_q0(filter_data_3_q0), + .filter_data_3_we0(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_we0), + .filter_data_3_address1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_address1), + .filter_data_3_ce1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_ce1), + .filter_data_3_d1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_d1), + .filter_data_3_q1(32'd0), + .filter_data_3_we1(dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP47956_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP47956_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP47956_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP47956_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP47956_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP47956_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP47956_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP47956_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP47956_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP47956_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP47956_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP47956_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP47956_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP47956_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP47956_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP47956_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP47956_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP47956_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP47956_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP47956_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP47956_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP47956_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP47956_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 16'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP47956_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 16'd1); + end else if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP47956_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= 16'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 16'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP47956_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP47956_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 16'd1); + end else if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP47956_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP47956_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= 16'd0; + end + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP47956_U0_ap_done == 1'b1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == 16'd0) & (ap_start == 1'b0) & (dataflow_in_loop_TOP_LOOP47956_U0_ap_idle == 1'b1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP47956_U0_ap_ready == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP47956_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP47956_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP47956_U0_adjustments_address0; + +assign adjustments_address1 = 8'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP47956_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP47956_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP47956_U0_ap_ready; + +assign bound_minus_1 = (16'd50176 - 16'd1); + +assign dataflow_in_loop_TOP_LOOP47956_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP47956_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP47956_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP47956_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP47956_U0_start_write = 1'b0; + +assign filter_data_0_address0 = dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_address0; + +assign filter_data_0_address1 = 14'd0; + +assign filter_data_0_ce0 = dataflow_in_loop_TOP_LOOP47956_U0_filter_data_0_ce0; + +assign filter_data_0_ce1 = 1'b0; + +assign filter_data_0_d0 = 32'd0; + +assign filter_data_0_d1 = 32'd0; + +assign filter_data_0_we0 = 1'b0; + +assign filter_data_0_we1 = 1'b0; + +assign filter_data_1_address0 = dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_address0; + +assign filter_data_1_address1 = 14'd0; + +assign filter_data_1_ce0 = dataflow_in_loop_TOP_LOOP47956_U0_filter_data_1_ce0; + +assign filter_data_1_ce1 = 1'b0; + +assign filter_data_1_d0 = 32'd0; + +assign filter_data_1_d1 = 32'd0; + +assign filter_data_1_we0 = 1'b0; + +assign filter_data_1_we1 = 1'b0; + +assign filter_data_2_address0 = dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_address0; + +assign filter_data_2_address1 = 14'd0; + +assign filter_data_2_ce0 = dataflow_in_loop_TOP_LOOP47956_U0_filter_data_2_ce0; + +assign filter_data_2_ce1 = 1'b0; + +assign filter_data_2_d0 = 32'd0; + +assign filter_data_2_d1 = 32'd0; + +assign filter_data_2_we0 = 1'b0; + +assign filter_data_2_we1 = 1'b0; + +assign filter_data_3_address0 = dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_address0; + +assign filter_data_3_address1 = 14'd0; + +assign filter_data_3_ce0 = dataflow_in_loop_TOP_LOOP47956_U0_filter_data_3_ce0; + +assign filter_data_3_ce1 = 1'b0; + +assign filter_data_3_d0 = 32'd0; + +assign filter_data_3_d1 = 32'd0; + +assign filter_data_3_we0 = 1'b0; + +assign filter_data_3_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP47956_U0_in_data_address0; + +assign in_data_address1 = 13'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP47956_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP47956_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 14'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP47956_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP47956_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP47956_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP47956_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP47956_U0_out_data_write; + +endmodule //td_fused_top_tdf8_17 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_in1_address0, + accum_in1_ce0, + accum_in1_q0, + accum_in1_address1, + accum_in1_ce1, + accum_in1_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_pp0_stage0 = 11'd2; +parameter ap_ST_fsm_pp0_stage1 = 11'd4; +parameter ap_ST_fsm_pp0_stage2 = 11'd8; +parameter ap_ST_fsm_pp0_stage3 = 11'd16; +parameter ap_ST_fsm_pp0_stage4 = 11'd32; +parameter ap_ST_fsm_pp0_stage5 = 11'd64; +parameter ap_ST_fsm_pp0_stage6 = 11'd128; +parameter ap_ST_fsm_state17 = 11'd256; +parameter ap_ST_fsm_state18 = 11'd512; +parameter ap_ST_fsm_state19 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [7:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [7:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [7:0] accum_in1_address0; +output accum_in1_ce0; +input [15:0] accum_in1_q0; +output [7:0] accum_in1_address1; +output accum_in1_ce1; +input [15:0] accum_in1_q1; +output [3:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [3:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[7:0] accum_in_address0; +reg accum_in_ce0; +reg[7:0] accum_in_address1; +reg accum_in_ce1; +reg[7:0] accum_in1_address0; +reg accum_in1_ce0; +reg[7:0] accum_in1_address1; +reg accum_in1_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [8:0] x_reg_263; +reg [15:0] psum_2_03_reg_275; +reg [15:0] psum_1_02_reg_287; +reg [15:0] psum_0_01_reg_299; +reg [15:0] psum_15_016_reg_311; +reg [15:0] psum_14_015_reg_323; +reg [15:0] psum_13_014_reg_335; +reg [15:0] psum_12_013_reg_347; +reg [15:0] psum_11_012_reg_359; +reg [15:0] psum_10_011_reg_371; +reg [15:0] psum_9_010_reg_383; +reg [15:0] psum_8_09_reg_395; +reg [15:0] psum_7_08_reg_407; +reg [15:0] psum_6_07_reg_419; +reg [15:0] psum_5_06_reg_431; +reg [15:0] psum_4_05_reg_443; +reg [15:0] psum_3_04_reg_455; +wire [0:0] icmp_ln49_fu_536_p2; +reg [0:0] icmp_ln49_reg_775; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state9_pp0_stage0_iter1; +wire ap_block_state16_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln49_reg_775_pp0_iter1_reg; +wire [7:0] lshr_ln_fu_542_p4; +reg [7:0] lshr_ln_reg_779; +reg [15:0] accum_in_load_reg_809; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state10_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in1_load_reg_814; +reg [15:0] accum_in_load_1_reg_819; +reg [15:0] accum_in1_load_1_reg_824; +reg [15:0] accum_in_load_2_reg_849; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state11_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in1_load_2_reg_854; +reg [15:0] accum_in_load_3_reg_859; +reg [15:0] accum_in1_load_3_reg_864; +reg [15:0] accum_in_load_4_reg_889; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state12_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in1_load_4_reg_894; +reg [15:0] accum_in_load_5_reg_899; +reg [15:0] accum_in1_load_5_reg_904; +reg [15:0] accum_in_load_6_reg_929; +wire ap_CS_fsm_pp0_stage4; +wire ap_block_state6_pp0_stage4_iter0; +wire ap_block_state13_pp0_stage4_iter1; +wire ap_block_pp0_stage4_11001; +reg [15:0] accum_in1_load_6_reg_934; +reg [15:0] accum_in_load_7_reg_939; +reg [15:0] accum_in1_load_7_reg_944; +wire [8:0] add_ln49_fu_636_p2; +reg [8:0] add_ln49_reg_949; +wire ap_CS_fsm_pp0_stage6; +wire ap_block_state8_pp0_stage6_iter0; +wire ap_block_state15_pp0_stage6_iter1; +wire ap_block_pp0_stage6_11001; +wire [15:0] grp_fu_508_p2; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_513_p2; +wire [15:0] grp_fu_518_p2; +wire ap_CS_fsm_pp0_stage5; +wire ap_block_state7_pp0_stage5_iter0; +wire ap_block_state14_pp0_stage5_iter1; +wire ap_block_pp0_stage5_11001; +reg ap_enable_reg_pp0_iter2; +wire [4:0] add_ln57_fu_659_p2; +wire ap_CS_fsm_state18; +wire [0:0] tmp_fu_642_p3; +reg ap_block_state1; +wire ap_block_pp0_stage3_subdone; +reg ap_condition_pp0_exit_iter0_state5; +wire ap_block_pp0_stage6_subdone; +wire ap_block_pp0_stage0_subdone; +reg [8:0] ap_phi_mux_x_phi_fu_267_p4; +wire ap_block_pp0_stage0; +wire ap_block_pp0_stage2; +wire [15:0] ap_phi_mux_psum_15_016_phi_fu_315_p4; +wire [15:0] ap_phi_mux_psum_14_015_phi_fu_327_p4; +wire ap_block_pp0_stage6; +wire [15:0] ap_phi_mux_psum_13_014_phi_fu_339_p4; +wire [15:0] ap_phi_mux_psum_12_013_phi_fu_351_p4; +wire [15:0] ap_phi_mux_psum_11_012_phi_fu_363_p4; +wire ap_block_pp0_stage5; +wire [15:0] ap_phi_mux_psum_10_011_phi_fu_375_p4; +wire [15:0] ap_phi_mux_psum_9_010_phi_fu_387_p4; +wire [15:0] ap_phi_mux_psum_8_09_phi_fu_399_p4; +wire ap_block_pp0_stage4; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_411_p4; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_423_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_435_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_447_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_459_p4; +reg [4:0] q_reg_467; +wire ap_CS_fsm_state17; +reg [15:0] ap_phi_mux_phi_ln69_phi_fu_481_p16; +wire [3:0] trunc_ln57_fu_655_p1; +wire [63:0] zext_ln53_fu_552_p1; +wire [63:0] zext_ln53_1_fu_564_p1; +wire [63:0] zext_ln53_2_fu_575_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln53_3_fu_586_p1; +wire [63:0] zext_ln53_4_fu_597_p1; +wire [63:0] zext_ln53_5_fu_608_p1; +wire [63:0] zext_ln53_6_fu_619_p1; +wire [63:0] zext_ln53_7_fu_630_p1; +wire [63:0] zext_ln57_fu_650_p1; +wire [63:0] zext_ln57_1_fu_671_p1; +reg [15:0] grp_fu_508_p0; +reg [15:0] grp_fu_508_p1; +reg [15:0] grp_fu_513_p0; +reg [15:0] grp_fu_513_p1; +reg [15:0] grp_fu_518_p0; +reg [15:0] grp_fu_518_p1; +wire [7:0] or_ln53_fu_558_p2; +wire [7:0] or_ln53_1_fu_570_p2; +wire [7:0] or_ln53_2_fu_581_p2; +wire [7:0] or_ln53_3_fu_592_p2; +wire [7:0] or_ln53_4_fu_603_p2; +wire [7:0] or_ln53_5_fu_614_p2; +wire [7:0] or_ln53_6_fu_625_p2; +wire [3:0] or_ln57_fu_665_p2; +wire [0:0] icmp_ln69_fu_676_p2; +wire [0:0] icmp_ln69_1_fu_690_p2; +wire [15:0] select_ln69_fu_682_p3; +wire [0:0] icmp_ln69_2_fu_704_p2; +wire [15:0] select_ln69_1_fu_696_p3; +wire [0:0] icmp_ln69_3_fu_718_p2; +wire [15:0] select_ln69_2_fu_710_p3; +wire [0:0] icmp_ln69_4_fu_732_p2; +wire [15:0] select_ln69_3_fu_724_p3; +wire [0:0] icmp_ln69_5_fu_746_p2; +wire [15:0] select_ln69_4_fu_738_p3; +wire [0:0] icmp_ln69_6_fu_760_p2; +wire [15:0] select_ln69_5_fu_752_p3; +wire ap_CS_fsm_state19; +reg [10:0] ap_NS_fsm; +wire ap_block_pp0_stage1_subdone; +wire ap_block_pp0_stage2_subdone; +wire ap_block_pp0_stage4_subdone; +wire ap_block_pp0_stage5_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_728; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1221( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_508_p0), + .din1(grp_fu_508_p1), + .dout(grp_fu_508_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1222( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_513_p0), + .din1(grp_fu_513_p1), + .dout(grp_fu_513_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1223( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_518_p0), + .din1(grp_fu_518_p1), + .dout(grp_fu_518_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state19)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state5) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6_subdone))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6_subdone)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + q_reg_467 <= 5'd0; + end else if (((tmp_fu_642_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + q_reg_467 <= add_ln57_fu_659_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + x_reg_263 <= add_ln49_reg_949; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_263 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + accum_in1_load_1_reg_824 <= accum_in1_q0; + accum_in1_load_reg_814 <= accum_in1_q1; + accum_in_load_1_reg_819 <= accum_in_q0; + accum_in_load_reg_809 <= accum_in_q1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001))) begin + accum_in1_load_2_reg_854 <= accum_in1_q1; + accum_in1_load_3_reg_864 <= accum_in1_q0; + accum_in_load_2_reg_849 <= accum_in_q1; + accum_in_load_3_reg_859 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + accum_in1_load_4_reg_894 <= accum_in1_q1; + accum_in1_load_5_reg_904 <= accum_in1_q0; + accum_in_load_4_reg_889 <= accum_in_q1; + accum_in_load_5_reg_899 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4_11001))) begin + accum_in1_load_6_reg_934 <= accum_in1_q1; + accum_in1_load_7_reg_944 <= accum_in1_q0; + accum_in_load_6_reg_929 <= accum_in_q1; + accum_in_load_7_reg_939 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6_11001))) begin + add_ln49_reg_949 <= add_ln49_fu_636_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln49_reg_775 <= icmp_ln49_fu_536_p2; + icmp_ln49_reg_775_pp0_iter1_reg <= icmp_ln49_reg_775; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_fu_536_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + lshr_ln_reg_779 <= {{ap_phi_mux_x_phi_fu_267_p4[8:1]}}; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage2_11001))) begin + psum_0_01_reg_299 <= grp_fu_508_p2; + psum_1_02_reg_287 <= grp_fu_513_p2; + psum_2_03_reg_275 <= grp_fu_518_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage5_11001))) begin + psum_10_011_reg_371 <= grp_fu_513_p2; + psum_11_012_reg_359 <= grp_fu_518_p2; + psum_9_010_reg_383 <= grp_fu_508_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage6) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage6_11001))) begin + psum_12_013_reg_347 <= grp_fu_508_p2; + psum_13_014_reg_335 <= grp_fu_513_p2; + psum_14_015_reg_323 <= grp_fu_518_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + psum_15_016_reg_311 <= grp_fu_508_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage3_11001))) begin + psum_3_04_reg_455 <= grp_fu_508_p2; + psum_4_05_reg_443 <= grp_fu_513_p2; + psum_5_06_reg_431 <= grp_fu_518_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (icmp_ln49_reg_775_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage4_11001))) begin + psum_6_07_reg_419 <= grp_fu_508_p2; + psum_7_08_reg_407 <= grp_fu_513_p2; + psum_8_09_reg_395 <= grp_fu_518_p2; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in1_address0 = zext_ln53_7_fu_630_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in1_address0 = zext_ln53_5_fu_608_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in1_address0 = zext_ln53_3_fu_586_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in1_address0 = zext_ln53_1_fu_564_p1; + end else begin + accum_in1_address0 = 'bx; + end + end else begin + accum_in1_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in1_address1 = zext_ln53_6_fu_619_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in1_address1 = zext_ln53_4_fu_597_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in1_address1 = zext_ln53_2_fu_575_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in1_address1 = zext_ln53_fu_552_p1; + end else begin + accum_in1_address1 = 'bx; + end + end else begin + accum_in1_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in1_ce0 = 1'b1; + end else begin + accum_in1_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in1_ce1 = 1'b1; + end else begin + accum_in1_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in_address0 = zext_ln53_7_fu_630_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in_address0 = zext_ln53_5_fu_608_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in_address0 = zext_ln53_3_fu_586_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in_address0 = zext_ln53_1_fu_564_p1; + end else begin + accum_in_address0 = 'bx; + end + end else begin + accum_in_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + accum_in_address1 = zext_ln53_6_fu_619_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + accum_in_address1 = zext_ln53_4_fu_597_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + accum_in_address1 = zext_ln53_2_fu_575_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + accum_in_address1 = zext_ln53_fu_552_p1; + end else begin + accum_in_address1 = 'bx; + end + end else begin + accum_in_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state18)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state18)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_642_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_642_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln49_reg_775 == 1'd0)) begin + ap_condition_pp0_exit_iter0_state5 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state5 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state19)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_642_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + if ((trunc_ln57_fu_655_p1 == 4'd0)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_0_01_reg_299; + end else if ((1'b1 == ap_condition_728)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_14_015_reg_323; + end else if ((trunc_ln57_fu_655_p1 == 4'd12)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_12_013_reg_347; + end else if ((trunc_ln57_fu_655_p1 == 4'd10)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_10_011_reg_371; + end else if ((trunc_ln57_fu_655_p1 == 4'd8)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_8_09_reg_395; + end else if ((trunc_ln57_fu_655_p1 == 4'd6)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_6_07_reg_419; + end else if ((trunc_ln57_fu_655_p1 == 4'd4)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_4_05_reg_443; + end else if ((trunc_ln57_fu_655_p1 == 4'd2)) begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = psum_2_03_reg_275; + end else begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = 'bx; + end + end else begin + ap_phi_mux_phi_ln69_phi_fu_481_p16 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln49_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_x_phi_fu_267_p4 = add_ln49_reg_949; + end else begin + ap_phi_mux_x_phi_fu_267_p4 = x_reg_263; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state19)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_508_p0 = ap_phi_mux_psum_15_016_phi_fu_315_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_508_p0 = ap_phi_mux_psum_12_013_phi_fu_351_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_508_p0 = ap_phi_mux_psum_9_010_phi_fu_387_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_508_p0 = ap_phi_mux_psum_6_07_phi_fu_423_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_508_p0 = ap_phi_mux_psum_3_04_phi_fu_459_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_508_p0 = grp_fu_508_p2; + end else begin + grp_fu_508_p0 = 'bx; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + grp_fu_508_p1 = accum_in1_load_7_reg_944; + end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_508_p1 = accum_in_load_6_reg_929; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_508_p1 = accum_in1_load_4_reg_894; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_508_p1 = accum_in_load_3_reg_859; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_508_p1 = accum_in1_load_1_reg_824; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_508_p1 = accum_in_load_reg_809; + end else begin + grp_fu_508_p1 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_513_p0 = ap_phi_mux_psum_13_014_phi_fu_339_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_513_p0 = ap_phi_mux_psum_10_011_phi_fu_375_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_513_p0 = ap_phi_mux_psum_7_08_phi_fu_411_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_513_p0 = ap_phi_mux_psum_4_05_phi_fu_447_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_513_p0 = grp_fu_513_p2; + end else begin + grp_fu_513_p0 = 'bx; + end + end else begin + grp_fu_513_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_513_p1 = accum_in1_load_6_reg_934; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_513_p1 = accum_in_load_5_reg_899; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_513_p1 = accum_in1_load_3_reg_864; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_513_p1 = accum_in_load_2_reg_849; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_513_p1 = accum_in1_load_reg_814; + end else begin + grp_fu_513_p1 = 'bx; + end + end else begin + grp_fu_513_p1 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_518_p0 = ap_phi_mux_psum_14_015_phi_fu_327_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_518_p0 = ap_phi_mux_psum_11_012_phi_fu_363_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_518_p0 = ap_phi_mux_psum_8_09_phi_fu_399_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_518_p0 = ap_phi_mux_psum_5_06_phi_fu_435_p4; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_518_p0 = grp_fu_518_p2; + end else begin + grp_fu_518_p0 = 'bx; + end + end else begin + grp_fu_518_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6))) begin + grp_fu_518_p1 = accum_in_load_7_reg_939; + end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5))) begin + grp_fu_518_p1 = accum_in1_load_5_reg_904; + end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b0 == ap_block_pp0_stage4))) begin + grp_fu_518_p1 = accum_in_load_4_reg_889; + end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b0 == ap_block_pp0_stage3))) begin + grp_fu_518_p1 = accum_in1_load_2_reg_854; + end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b0 == ap_block_pp0_stage2))) begin + grp_fu_518_p1 = accum_in_load_1_reg_819; + end else begin + grp_fu_518_p1 = 'bx; + end + end else begin + grp_fu_518_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if (((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state17; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((1'b0 == ap_block_pp0_stage2_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((~((icmp_ln49_reg_775 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_subdone)) & (1'b0 == ap_block_pp0_stage3_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end else if (((icmp_ln49_reg_775 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state17; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_pp0_stage4 : begin + if ((1'b0 == ap_block_pp0_stage4_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end + end + ap_ST_fsm_pp0_stage5 : begin + if ((1'b0 == ap_block_pp0_stage5_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end + end + ap_ST_fsm_pp0_stage6 : begin + if ((1'b0 == ap_block_pp0_stage6_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state18; + end + ap_ST_fsm_state18 : begin + if (((tmp_fu_642_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state18))) begin + ap_NS_fsm = ap_ST_fsm_state18; + end else begin + ap_NS_fsm = ap_ST_fsm_state19; + end + end + ap_ST_fsm_state19 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln57_1_fu_671_p1; + +assign accum_out_address1 = zext_ln57_fu_650_p1; + +assign accum_out_d0 = ((icmp_ln69_6_fu_760_p2[0:0] == 1'b1) ? psum_13_014_reg_335 : select_ln69_5_fu_752_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln69_phi_fu_481_p16; + +assign add_ln49_fu_636_p2 = (x_reg_263 + 9'd16); + +assign add_ln57_fu_659_p2 = (q_reg_467 + 5'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd8]; + +assign ap_CS_fsm_state18 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state19 = ap_CS_fsm[32'd10]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage4_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage5_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage6_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_728 = (~(trunc_ln57_fu_655_p1 == 4'd0) & ~(trunc_ln57_fu_655_p1 == 4'd12) & ~(trunc_ln57_fu_655_p1 == 4'd10) & ~(trunc_ln57_fu_655_p1 == 4'd8) & ~(trunc_ln57_fu_655_p1 == 4'd6) & ~(trunc_ln57_fu_655_p1 == 4'd4) & ~(trunc_ln57_fu_655_p1 == 4'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_10_011_phi_fu_375_p4 = grp_fu_513_p2; + +assign ap_phi_mux_psum_11_012_phi_fu_363_p4 = grp_fu_518_p2; + +assign ap_phi_mux_psum_12_013_phi_fu_351_p4 = grp_fu_508_p2; + +assign ap_phi_mux_psum_13_014_phi_fu_339_p4 = grp_fu_513_p2; + +assign ap_phi_mux_psum_14_015_phi_fu_327_p4 = grp_fu_518_p2; + +assign ap_phi_mux_psum_15_016_phi_fu_315_p4 = grp_fu_508_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_459_p4 = grp_fu_508_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_447_p4 = grp_fu_513_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_435_p4 = grp_fu_518_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_423_p4 = grp_fu_508_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_411_p4 = grp_fu_513_p2; + +assign ap_phi_mux_psum_8_09_phi_fu_399_p4 = grp_fu_518_p2; + +assign ap_phi_mux_psum_9_010_phi_fu_387_p4 = grp_fu_508_p2; + +assign icmp_ln49_fu_536_p2 = ((ap_phi_mux_x_phi_fu_267_p4 < 9'd288) ? 1'b1 : 1'b0); + +assign icmp_ln69_1_fu_690_p2 = ((or_ln57_fu_665_p2 == 4'd3) ? 1'b1 : 1'b0); + +assign icmp_ln69_2_fu_704_p2 = ((or_ln57_fu_665_p2 == 4'd5) ? 1'b1 : 1'b0); + +assign icmp_ln69_3_fu_718_p2 = ((or_ln57_fu_665_p2 == 4'd7) ? 1'b1 : 1'b0); + +assign icmp_ln69_4_fu_732_p2 = ((or_ln57_fu_665_p2 == 4'd9) ? 1'b1 : 1'b0); + +assign icmp_ln69_5_fu_746_p2 = ((or_ln57_fu_665_p2 == 4'd11) ? 1'b1 : 1'b0); + +assign icmp_ln69_6_fu_760_p2 = ((or_ln57_fu_665_p2 == 4'd13) ? 1'b1 : 1'b0); + +assign icmp_ln69_fu_676_p2 = ((or_ln57_fu_665_p2 == 4'd1) ? 1'b1 : 1'b0); + +assign lshr_ln_fu_542_p4 = {{ap_phi_mux_x_phi_fu_267_p4[8:1]}}; + +assign or_ln53_1_fu_570_p2 = (lshr_ln_reg_779 | 8'd2); + +assign or_ln53_2_fu_581_p2 = (lshr_ln_reg_779 | 8'd3); + +assign or_ln53_3_fu_592_p2 = (lshr_ln_reg_779 | 8'd4); + +assign or_ln53_4_fu_603_p2 = (lshr_ln_reg_779 | 8'd5); + +assign or_ln53_5_fu_614_p2 = (lshr_ln_reg_779 | 8'd6); + +assign or_ln53_6_fu_625_p2 = (lshr_ln_reg_779 | 8'd7); + +assign or_ln53_fu_558_p2 = (lshr_ln_fu_542_p4 | 8'd1); + +assign or_ln57_fu_665_p2 = (trunc_ln57_fu_655_p1 | 4'd1); + +assign select_ln69_1_fu_696_p3 = ((icmp_ln69_1_fu_690_p2[0:0] == 1'b1) ? psum_3_04_reg_455 : select_ln69_fu_682_p3); + +assign select_ln69_2_fu_710_p3 = ((icmp_ln69_2_fu_704_p2[0:0] == 1'b1) ? psum_5_06_reg_431 : select_ln69_1_fu_696_p3); + +assign select_ln69_3_fu_724_p3 = ((icmp_ln69_3_fu_718_p2[0:0] == 1'b1) ? psum_7_08_reg_407 : select_ln69_2_fu_710_p3); + +assign select_ln69_4_fu_738_p3 = ((icmp_ln69_4_fu_732_p2[0:0] == 1'b1) ? psum_9_010_reg_383 : select_ln69_3_fu_724_p3); + +assign select_ln69_5_fu_752_p3 = ((icmp_ln69_5_fu_746_p2[0:0] == 1'b1) ? psum_11_012_reg_359 : select_ln69_4_fu_738_p3); + +assign select_ln69_fu_682_p3 = ((icmp_ln69_fu_676_p2[0:0] == 1'b1) ? psum_1_02_reg_287 : psum_15_016_reg_311); + +assign tmp_fu_642_p3 = q_reg_467[32'd4]; + +assign trunc_ln57_fu_655_p1 = q_reg_467[3:0]; + +assign zext_ln53_1_fu_564_p1 = or_ln53_fu_558_p2; + +assign zext_ln53_2_fu_575_p1 = or_ln53_1_fu_570_p2; + +assign zext_ln53_3_fu_586_p1 = or_ln53_2_fu_581_p2; + +assign zext_ln53_4_fu_597_p1 = or_ln53_3_fu_592_p2; + +assign zext_ln53_5_fu_608_p1 = or_ln53_4_fu_603_p2; + +assign zext_ln53_6_fu_619_p1 = or_ln53_5_fu_614_p2; + +assign zext_ln53_7_fu_630_p1 = or_ln53_6_fu_625_p2; + +assign zext_ln53_fu_552_p1 = lshr_ln_fu_542_p4; + +assign zext_ln57_1_fu_671_p1 = or_ln57_fu_665_p2; + +assign zext_ln57_fu_650_p1 = q_reg_467; + +endmodule //td_fused_top_tdf8_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_accum_2_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_8, + accum_in_8_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_8; +output accum_in_8_ap_vld; +output [3:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_8; +reg accum_in_8_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [4:0] add_ln81_fu_73_p2; +reg [4:0] add_ln81_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln81_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [4:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln81_fu_79_p1; +reg [15:0] accum_in_8_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_8_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1231( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_8_preg <= 16'd0; + end else begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_8_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 5'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln81_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln81_reg_90 <= add_ln81_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_8 = sum_01_reg_55; + end else begin + accum_in_8 = accum_in_8_preg; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_8_ap_vld = 1'b1; + end else begin + accum_in_8_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln81_fu_79_p1; + +assign add_ln81_fu_73_p2 = (i_1_1_reg_44 + 5'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln81_fu_84_p2 = ((i_1_1_reg_44 == 5'd16) ? 1'b1 : 1'b0); + +assign zext_ln81_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf8_accum_2_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_accum_2_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_6, + accum_in_6_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_6; +output accum_in_6_ap_vld; +output [3:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_6; +reg accum_in_6_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [4:0] add_ln81_fu_73_p2; +reg [4:0] add_ln81_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln81_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [4:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln81_fu_79_p1; +reg [15:0] accum_in_6_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_6_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1235( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_6_preg <= 16'd0; + end else begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_6_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 5'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln81_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln81_reg_90 <= add_ln81_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_6 = sum_01_reg_55; + end else begin + accum_in_6 = accum_in_6_preg; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_6_ap_vld = 1'b1; + end else begin + accum_in_6_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln81_fu_79_p1; + +assign add_ln81_fu_73_p2 = (i_1_1_reg_44 + 5'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln81_fu_84_p2 = ((i_1_1_reg_44 == 5'd16) ? 1'b1 : 1'b0); + +assign zext_ln81_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf8_accum_2_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_accum_2_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_4, + accum_in_4_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_4; +output accum_in_4_ap_vld; +output [3:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_4; +reg accum_in_4_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [4:0] add_ln81_fu_73_p2; +reg [4:0] add_ln81_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln81_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [4:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln81_fu_79_p1; +reg [15:0] accum_in_4_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_4_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1239( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_4_preg <= 16'd0; + end else begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_4_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 5'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln81_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln81_reg_90 <= add_ln81_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_4 = sum_01_reg_55; + end else begin + accum_in_4 = accum_in_4_preg; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_4_ap_vld = 1'b1; + end else begin + accum_in_4_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln81_fu_79_p1; + +assign add_ln81_fu_73_p2 = (i_1_1_reg_44 + 5'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln81_fu_84_p2 = ((i_1_1_reg_44 == 5'd16) ? 1'b1 : 1'b0); + +assign zext_ln81_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf8_accum_2_3 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_10, + accum_in_10_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_10; +output accum_in_10_ap_vld; +output [3:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_10; +reg accum_in_10_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [4:0] add_ln81_fu_73_p2; +reg [4:0] add_ln81_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln81_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [4:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln81_fu_79_p1; +reg [15:0] accum_in_10_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_10_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1227( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_10_preg <= 16'd0; + end else begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_10_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 5'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln81_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln81_reg_90 <= add_ln81_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_10 = sum_01_reg_55; + end else begin + accum_in_10 = accum_in_10_preg; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_10_ap_vld = 1'b1; + end else begin + accum_in_10_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln81_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln81_fu_79_p1; + +assign add_ln81_fu_73_p2 = (i_1_1_reg_44 + 5'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln81_fu_84_p2 = ((i_1_1_reg_44 == 5'd16) ? 1'b1 : 1'b0); + +assign zext_ln81_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf8_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_0_read, + sums_1_read, + sums_2_read, + sums_3_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + input_indices_23_out_din, + input_indices_23_out_full_n, + input_indices_23_out_write, + ap_return_0, + ap_return_1, + ap_return_2, + ap_return_3 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state25 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_0_read; +input [15:0] sums_1_read; +input [15:0] sums_2_read; +input [15:0] sums_3_read; +output [7:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [7:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [7:0] input_indices_23_out_din; +input input_indices_23_out_full_n; +output input_indices_23_out_write; +output [15:0] ap_return_0; +output [15:0] ap_return_1; +output [15:0] ap_return_2; +output [15:0] ap_return_3; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg input_indices_23_read; +reg input_indices_23_out_write; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +reg input_indices_23_out_blk_n; +reg [0:0] write_flag6_0_reg_153; +reg [0:0] write_flag9_0_reg_164; +reg [0:0] write_flag12_0_reg_175; +reg [0:0] write_flag_0_reg_186; +reg [2:0] o_reg_197; +reg [15:0] outputs_1_011_reg_208; +reg [15:0] outputs_0_010_reg_220; +reg [15:0] outputs_2_09_reg_232; +reg [15:0] outputs_3_08_reg_244; +wire [5:0] trunc_ln205_fu_268_p1; +reg [5:0] trunc_ln205_reg_550; +wire [2:0] add_ln213_fu_272_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_state13_pp0_stage0_iter11; +wire ap_block_state14_pp0_stage0_iter12; +wire ap_block_state15_pp0_stage0_iter13; +wire ap_block_state16_pp0_stage0_iter14; +wire ap_block_state17_pp0_stage0_iter15; +wire ap_block_state18_pp0_stage0_iter16; +wire ap_block_state19_pp0_stage0_iter17; +wire ap_block_state20_pp0_stage0_iter18; +wire ap_block_state21_pp0_stage0_iter19; +wire ap_block_state22_pp0_stage0_iter20; +wire ap_block_state23_pp0_stage0_iter21; +wire ap_block_state24_pp0_stage0_iter22; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln213_fu_278_p2; +reg [0:0] icmp_ln213_reg_560; +reg [0:0] icmp_ln213_reg_560_pp0_iter1_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter2_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter3_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter4_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter5_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter6_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter7_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter8_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter9_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter10_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter11_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter12_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter13_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter14_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter15_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter16_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter17_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter18_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter19_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter20_reg; +reg [0:0] icmp_ln213_reg_560_pp0_iter21_reg; +wire [1:0] trunc_ln219_fu_284_p1; +reg [1:0] trunc_ln219_reg_564; +reg [1:0] trunc_ln219_reg_564_pp0_iter1_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter2_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter3_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter4_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter5_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter6_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter7_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter8_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter9_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter10_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter11_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter12_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter13_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter14_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter15_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter16_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter17_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter18_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter19_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter20_reg; +reg [1:0] trunc_ln219_reg_564_pp0_iter21_reg; +wire [0:0] write_flag_1_fu_300_p6; +wire [0:0] write_flag12_1_fu_314_p6; +wire [0:0] write_flag9_1_fu_328_p6; +wire [0:0] write_flag6_1_fu_342_p6; +wire [15:0] trunc_ln220_fu_356_p1; +reg [15:0] trunc_ln220_reg_597; +reg [15:0] tmp_28_i_i_reg_602; +reg [15:0] tmp_28_i_i_reg_602_pp0_iter2_reg; +reg [15:0] tmp_28_i_i_reg_602_pp0_iter3_reg; +reg [15:0] tmp_28_i_i_reg_602_pp0_iter4_reg; +reg [15:0] tmp_28_i_i_reg_602_pp0_iter5_reg; +reg [15:0] tmp_28_i_i_reg_602_pp0_iter6_reg; +reg [15:0] tmp_28_i_i_reg_602_pp0_iter7_reg; +reg [15:0] tmp_28_i_i_reg_602_pp0_iter8_reg; +reg [15:0] tmp_29_i_i_reg_607; +reg [15:0] tmp_29_i_i_reg_607_pp0_iter2_reg; +reg [15:0] tmp_29_i_i_reg_607_pp0_iter3_reg; +reg [15:0] tmp_29_i_i_reg_607_pp0_iter4_reg; +reg [15:0] tmp_29_i_i_reg_607_pp0_iter5_reg; +reg [15:0] tmp_29_i_i_reg_607_pp0_iter6_reg; +reg [15:0] tmp_29_i_i_reg_607_pp0_iter7_reg; +reg [15:0] tmp_29_i_i_reg_607_pp0_iter8_reg; +reg [15:0] tmp_29_i_i_reg_607_pp0_iter9_reg; +reg [15:0] tmp_29_i_i_reg_607_pp0_iter10_reg; +reg [15:0] tmp_29_i_i_reg_607_pp0_iter11_reg; +reg [15:0] tmp_29_i_i_reg_607_pp0_iter12_reg; +reg [15:0] tmp_29_i_i_reg_607_pp0_iter13_reg; +wire [15:0] val_in_assign_fu_380_p6; +reg [15:0] val_in_assign_reg_612; +wire [15:0] grp_fu_260_p2; +reg [15:0] sub_i_i_i_reg_622; +wire [15:0] grp_fu_264_p2; +reg [15:0] normalized_reg_632; +wire [15:0] grp_fu_256_p2; +reg [15:0] biased_reg_642; +wire [15:0] outputs_3_1_fu_450_p3; +reg ap_enable_reg_pp0_iter22; +wire [15:0] outputs_2_1_fu_458_p3; +wire [15:0] outputs_0_1_fu_482_p3; +wire [15:0] outputs_1_1_fu_498_p3; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_condition_pp0_exit_iter21_state23; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln220_fu_295_p1; +wire [15:0] grp_fu_256_p1; +wire [15:0] grp_fu_260_p1; +wire [15:0] grp_fu_264_p1; +wire [7:0] ochan_fu_288_p3; +wire [15:0] data_V_fu_401_p1; +wire [0:0] p_Result_s_fu_404_p3; +wire [0:0] icmp_ln223_fu_419_p2; +wire [15:0] activated_fu_412_p3; +wire [0:0] icmp_ln223_1_fu_432_p2; +wire [15:0] select_ln223_fu_424_p3; +wire [0:0] icmp_ln223_2_fu_445_p2; +wire [15:0] select_ln223_1_fu_437_p3; +wire [15:0] select_ln223_2_fu_466_p3; +wire [15:0] select_ln223_3_fu_474_p3; +wire [15:0] select_ln223_4_fu_490_p3; +wire ap_CS_fsm_state25; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1243( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(normalized_reg_632), + .din1(grp_fu_256_p1), + .dout(grp_fu_256_p2) +); + +td_fused_top_hsub_16ns_16ns_16_7_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 7 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_7_full_dsp_1_U1244( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(val_in_assign_reg_612), + .din1(grp_fu_260_p1), + .dout(grp_fu_260_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1245( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_622), + .din1(grp_fu_264_p1), + .dout(grp_fu_264_p2) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U1246( + .din0(1'd1), + .din1(write_flag_0_reg_186), + .din2(write_flag_0_reg_186), + .din3(write_flag_0_reg_186), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag_1_fu_300_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U1247( + .din0(write_flag12_0_reg_175), + .din1(write_flag12_0_reg_175), + .din2(write_flag12_0_reg_175), + .din3(1'd1), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag12_1_fu_314_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U1248( + .din0(write_flag9_0_reg_164), + .din1(write_flag9_0_reg_164), + .din2(1'd1), + .din3(write_flag9_0_reg_164), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag9_1_fu_328_p6) +); + +td_fused_top_mux_42_1_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 1 ), + .din1_WIDTH( 1 ), + .din2_WIDTH( 1 ), + .din3_WIDTH( 1 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 1 )) +mux_42_1_1_1_U1249( + .din0(write_flag6_0_reg_153), + .din1(1'd1), + .din2(write_flag6_0_reg_153), + .din3(write_flag6_0_reg_153), + .din4(trunc_ln219_fu_284_p1), + .dout(write_flag6_1_fu_342_p6) +); + +td_fused_top_mux_42_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .din2_WIDTH( 16 ), + .din3_WIDTH( 16 ), + .din4_WIDTH( 2 ), + .dout_WIDTH( 16 )) +mux_42_16_1_1_U1250( + .din0(sums_0_read), + .din1(sums_1_read), + .din2(sums_2_read), + .din3(sums_3_read), + .din4(trunc_ln219_reg_564), + .dout(val_in_assign_fu_380_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end else if ((((ap_enable_reg_pp0_iter20 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter21_state23) & (1'b0 == ap_block_pp0_stage0_subdone)) | (~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter21_state23) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter20; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + o_reg_197 <= add_ln213_fu_272_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + o_reg_197 <= 3'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag12_0_reg_175 <= write_flag12_1_fu_314_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag12_0_reg_175 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag6_0_reg_153 <= write_flag6_1_fu_342_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag6_0_reg_153 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag9_0_reg_164 <= write_flag9_1_fu_328_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag9_0_reg_164 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + write_flag_0_reg_186 <= write_flag_1_fu_300_p6; + end else if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_flag_0_reg_186 <= 1'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_560_pp0_iter20_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + biased_reg_642 <= grp_fu_256_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln213_reg_560 <= icmp_ln213_fu_278_p2; + icmp_ln213_reg_560_pp0_iter1_reg <= icmp_ln213_reg_560; + trunc_ln219_reg_564_pp0_iter1_reg <= trunc_ln219_reg_564; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln213_reg_560_pp0_iter10_reg <= icmp_ln213_reg_560_pp0_iter9_reg; + icmp_ln213_reg_560_pp0_iter11_reg <= icmp_ln213_reg_560_pp0_iter10_reg; + icmp_ln213_reg_560_pp0_iter12_reg <= icmp_ln213_reg_560_pp0_iter11_reg; + icmp_ln213_reg_560_pp0_iter13_reg <= icmp_ln213_reg_560_pp0_iter12_reg; + icmp_ln213_reg_560_pp0_iter14_reg <= icmp_ln213_reg_560_pp0_iter13_reg; + icmp_ln213_reg_560_pp0_iter15_reg <= icmp_ln213_reg_560_pp0_iter14_reg; + icmp_ln213_reg_560_pp0_iter16_reg <= icmp_ln213_reg_560_pp0_iter15_reg; + icmp_ln213_reg_560_pp0_iter17_reg <= icmp_ln213_reg_560_pp0_iter16_reg; + icmp_ln213_reg_560_pp0_iter18_reg <= icmp_ln213_reg_560_pp0_iter17_reg; + icmp_ln213_reg_560_pp0_iter19_reg <= icmp_ln213_reg_560_pp0_iter18_reg; + icmp_ln213_reg_560_pp0_iter20_reg <= icmp_ln213_reg_560_pp0_iter19_reg; + icmp_ln213_reg_560_pp0_iter21_reg <= icmp_ln213_reg_560_pp0_iter20_reg; + icmp_ln213_reg_560_pp0_iter2_reg <= icmp_ln213_reg_560_pp0_iter1_reg; + icmp_ln213_reg_560_pp0_iter3_reg <= icmp_ln213_reg_560_pp0_iter2_reg; + icmp_ln213_reg_560_pp0_iter4_reg <= icmp_ln213_reg_560_pp0_iter3_reg; + icmp_ln213_reg_560_pp0_iter5_reg <= icmp_ln213_reg_560_pp0_iter4_reg; + icmp_ln213_reg_560_pp0_iter6_reg <= icmp_ln213_reg_560_pp0_iter5_reg; + icmp_ln213_reg_560_pp0_iter7_reg <= icmp_ln213_reg_560_pp0_iter6_reg; + icmp_ln213_reg_560_pp0_iter8_reg <= icmp_ln213_reg_560_pp0_iter7_reg; + icmp_ln213_reg_560_pp0_iter9_reg <= icmp_ln213_reg_560_pp0_iter8_reg; + tmp_28_i_i_reg_602_pp0_iter2_reg <= tmp_28_i_i_reg_602; + tmp_28_i_i_reg_602_pp0_iter3_reg <= tmp_28_i_i_reg_602_pp0_iter2_reg; + tmp_28_i_i_reg_602_pp0_iter4_reg <= tmp_28_i_i_reg_602_pp0_iter3_reg; + tmp_28_i_i_reg_602_pp0_iter5_reg <= tmp_28_i_i_reg_602_pp0_iter4_reg; + tmp_28_i_i_reg_602_pp0_iter6_reg <= tmp_28_i_i_reg_602_pp0_iter5_reg; + tmp_28_i_i_reg_602_pp0_iter7_reg <= tmp_28_i_i_reg_602_pp0_iter6_reg; + tmp_28_i_i_reg_602_pp0_iter8_reg <= tmp_28_i_i_reg_602_pp0_iter7_reg; + tmp_29_i_i_reg_607_pp0_iter10_reg <= tmp_29_i_i_reg_607_pp0_iter9_reg; + tmp_29_i_i_reg_607_pp0_iter11_reg <= tmp_29_i_i_reg_607_pp0_iter10_reg; + tmp_29_i_i_reg_607_pp0_iter12_reg <= tmp_29_i_i_reg_607_pp0_iter11_reg; + tmp_29_i_i_reg_607_pp0_iter13_reg <= tmp_29_i_i_reg_607_pp0_iter12_reg; + tmp_29_i_i_reg_607_pp0_iter2_reg <= tmp_29_i_i_reg_607; + tmp_29_i_i_reg_607_pp0_iter3_reg <= tmp_29_i_i_reg_607_pp0_iter2_reg; + tmp_29_i_i_reg_607_pp0_iter4_reg <= tmp_29_i_i_reg_607_pp0_iter3_reg; + tmp_29_i_i_reg_607_pp0_iter5_reg <= tmp_29_i_i_reg_607_pp0_iter4_reg; + tmp_29_i_i_reg_607_pp0_iter6_reg <= tmp_29_i_i_reg_607_pp0_iter5_reg; + tmp_29_i_i_reg_607_pp0_iter7_reg <= tmp_29_i_i_reg_607_pp0_iter6_reg; + tmp_29_i_i_reg_607_pp0_iter8_reg <= tmp_29_i_i_reg_607_pp0_iter7_reg; + tmp_29_i_i_reg_607_pp0_iter9_reg <= tmp_29_i_i_reg_607_pp0_iter8_reg; + trunc_ln219_reg_564_pp0_iter10_reg <= trunc_ln219_reg_564_pp0_iter9_reg; + trunc_ln219_reg_564_pp0_iter11_reg <= trunc_ln219_reg_564_pp0_iter10_reg; + trunc_ln219_reg_564_pp0_iter12_reg <= trunc_ln219_reg_564_pp0_iter11_reg; + trunc_ln219_reg_564_pp0_iter13_reg <= trunc_ln219_reg_564_pp0_iter12_reg; + trunc_ln219_reg_564_pp0_iter14_reg <= trunc_ln219_reg_564_pp0_iter13_reg; + trunc_ln219_reg_564_pp0_iter15_reg <= trunc_ln219_reg_564_pp0_iter14_reg; + trunc_ln219_reg_564_pp0_iter16_reg <= trunc_ln219_reg_564_pp0_iter15_reg; + trunc_ln219_reg_564_pp0_iter17_reg <= trunc_ln219_reg_564_pp0_iter16_reg; + trunc_ln219_reg_564_pp0_iter18_reg <= trunc_ln219_reg_564_pp0_iter17_reg; + trunc_ln219_reg_564_pp0_iter19_reg <= trunc_ln219_reg_564_pp0_iter18_reg; + trunc_ln219_reg_564_pp0_iter20_reg <= trunc_ln219_reg_564_pp0_iter19_reg; + trunc_ln219_reg_564_pp0_iter21_reg <= trunc_ln219_reg_564_pp0_iter20_reg; + trunc_ln219_reg_564_pp0_iter2_reg <= trunc_ln219_reg_564_pp0_iter1_reg; + trunc_ln219_reg_564_pp0_iter3_reg <= trunc_ln219_reg_564_pp0_iter2_reg; + trunc_ln219_reg_564_pp0_iter4_reg <= trunc_ln219_reg_564_pp0_iter3_reg; + trunc_ln219_reg_564_pp0_iter5_reg <= trunc_ln219_reg_564_pp0_iter4_reg; + trunc_ln219_reg_564_pp0_iter6_reg <= trunc_ln219_reg_564_pp0_iter5_reg; + trunc_ln219_reg_564_pp0_iter7_reg <= trunc_ln219_reg_564_pp0_iter6_reg; + trunc_ln219_reg_564_pp0_iter8_reg <= trunc_ln219_reg_564_pp0_iter7_reg; + trunc_ln219_reg_564_pp0_iter9_reg <= trunc_ln219_reg_564_pp0_iter8_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_560_pp0_iter12_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + normalized_reg_632 <= grp_fu_264_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter22 == 1'b1) & (icmp_ln213_reg_560_pp0_iter21_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + outputs_0_010_reg_220 <= outputs_0_1_fu_482_p3; + outputs_1_011_reg_208 <= outputs_1_1_fu_498_p3; + outputs_2_09_reg_232 <= outputs_2_1_fu_458_p3; + outputs_3_08_reg_244 <= outputs_3_1_fu_450_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln213_reg_560_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + sub_i_i_i_reg_622 <= grp_fu_260_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_reg_560 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + tmp_28_i_i_reg_602 <= {{adjustments_q0[31:16]}}; + tmp_29_i_i_reg_607 <= {{adjustments_q0[47:32]}}; + trunc_ln220_reg_597 <= trunc_ln220_fu_356_p1; + val_in_assign_reg_612 <= val_in_assign_fu_380_p6; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + trunc_ln205_reg_550 <= trunc_ln205_fu_268_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + trunc_ln219_reg_564 <= trunc_ln219_fu_284_p1; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0))) begin + ap_condition_pp0_exit_iter21_state23 = 1'b1; + end else begin + ap_condition_pp0_exit_iter21_state23 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln213_fu_278_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_out_blk_n = input_indices_23_out_full_n; + end else begin + input_indices_23_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_out_write = 1'b1; + end else begin + input_indices_23_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((ap_enable_reg_pp0_iter21 == 1'b1) & (ap_enable_reg_pp0_iter20 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_state25; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state25 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign activated_fu_412_p3 = ((p_Result_s_fu_404_p3[0:0] == 1'b1) ? 16'd0 : biased_reg_642); + +assign add_ln213_fu_272_p2 = (o_reg_197 + 3'd1); + +assign adjustments_address0 = zext_ln220_fu_295_p1; + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state25 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (input_indices_23_out_full_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_return_0 = outputs_0_010_reg_220; + +assign ap_return_1 = outputs_1_011_reg_208; + +assign ap_return_2 = outputs_2_09_reg_232; + +assign ap_return_3 = outputs_3_08_reg_244; + +assign data_V_fu_401_p1 = biased_reg_642; + +assign grp_fu_256_p1 = tmp_29_i_i_reg_607_pp0_iter13_reg; + +assign grp_fu_260_p1 = trunc_ln220_reg_597; + +assign grp_fu_264_p1 = tmp_28_i_i_reg_602_pp0_iter8_reg; + +assign icmp_ln213_fu_278_p2 = ((o_reg_197 == 3'd4) ? 1'b1 : 1'b0); + +assign icmp_ln223_1_fu_432_p2 = ((trunc_ln219_reg_564_pp0_iter21_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln223_2_fu_445_p2 = ((trunc_ln219_reg_564_pp0_iter21_reg == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln223_fu_419_p2 = ((trunc_ln219_reg_564_pp0_iter21_reg == 2'd0) ? 1'b1 : 1'b0); + +assign input_indices_23_out_din = input_indices_23_dout; + +assign ochan_fu_288_p3 = {{trunc_ln205_reg_550}, {trunc_ln219_fu_284_p1}}; + +assign outputs_0_1_fu_482_p3 = ((icmp_ln223_2_fu_445_p2[0:0] == 1'b1) ? outputs_0_010_reg_220 : select_ln223_3_fu_474_p3); + +assign outputs_1_1_fu_498_p3 = ((icmp_ln223_2_fu_445_p2[0:0] == 1'b1) ? outputs_1_011_reg_208 : select_ln223_4_fu_490_p3); + +assign outputs_2_1_fu_458_p3 = ((icmp_ln223_2_fu_445_p2[0:0] == 1'b1) ? activated_fu_412_p3 : outputs_2_09_reg_232); + +assign outputs_3_1_fu_450_p3 = ((icmp_ln223_2_fu_445_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : select_ln223_1_fu_437_p3); + +assign p_Result_s_fu_404_p3 = data_V_fu_401_p1[32'd15]; + +assign select_ln223_1_fu_437_p3 = ((icmp_ln223_1_fu_432_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : select_ln223_fu_424_p3); + +assign select_ln223_2_fu_466_p3 = ((icmp_ln223_fu_419_p2[0:0] == 1'b1) ? activated_fu_412_p3 : outputs_0_010_reg_220); + +assign select_ln223_3_fu_474_p3 = ((icmp_ln223_1_fu_432_p2[0:0] == 1'b1) ? outputs_0_010_reg_220 : select_ln223_2_fu_466_p3); + +assign select_ln223_4_fu_490_p3 = ((icmp_ln223_1_fu_432_p2[0:0] == 1'b1) ? activated_fu_412_p3 : outputs_1_011_reg_208); + +assign select_ln223_fu_424_p3 = ((icmp_ln223_fu_419_p2[0:0] == 1'b1) ? outputs_3_08_reg_244 : activated_fu_412_p3); + +assign trunc_ln205_fu_268_p1 = input_indices_23_dout[5:0]; + +assign trunc_ln219_fu_284_p1 = o_reg_197[1:0]; + +assign trunc_ln220_fu_356_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_295_p1 = ochan_fu_288_p3; + +endmodule //td_fused_top_tdf8_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_0_address0, + ifmap_vec_0_ce0, + ifmap_vec_0_q0, + ifmap_vec_1_address0, + ifmap_vec_1_ce0, + ifmap_vec_1_q0, + weight_vecs_0_0_address0, + weight_vecs_0_0_ce0, + weight_vecs_0_0_q0, + weight_vecs_0_1_address0, + weight_vecs_0_1_ce0, + weight_vecs_0_1_q0, + weight_vecs_1_0_address0, + weight_vecs_1_0_ce0, + weight_vecs_1_0_q0, + weight_vecs_1_1_address0, + weight_vecs_1_1_ce0, + weight_vecs_1_1_q0, + weight_vecs_2_0_address0, + weight_vecs_2_0_ce0, + weight_vecs_2_0_q0, + weight_vecs_2_1_address0, + weight_vecs_2_1_ce0, + weight_vecs_2_1_q0, + weight_vecs_3_0_address0, + weight_vecs_3_0_ce0, + weight_vecs_3_0_q0, + weight_vecs_3_1_address0, + weight_vecs_3_1_ce0, + weight_vecs_3_1_q0, + products_0_0_address0, + products_0_0_ce0, + products_0_0_we0, + products_0_0_d0, + products_0_1_address0, + products_0_1_ce0, + products_0_1_we0, + products_0_1_d0, + products_1_0_address0, + products_1_0_ce0, + products_1_0_we0, + products_1_0_d0, + products_1_1_address0, + products_1_1_ce0, + products_1_1_we0, + products_1_1_d0, + products_2_0_address0, + products_2_0_ce0, + products_2_0_we0, + products_2_0_d0, + products_2_1_address0, + products_2_1_ce0, + products_2_1_we0, + products_2_1_d0, + products_3_0_address0, + products_3_0_ce0, + products_3_0_we0, + products_3_0_d0, + products_3_1_address0, + products_3_1_ce0, + products_3_1_we0, + products_3_1_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state11 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [7:0] ifmap_vec_0_address0; +output ifmap_vec_0_ce0; +input [15:0] ifmap_vec_0_q0; +output [7:0] ifmap_vec_1_address0; +output ifmap_vec_1_ce0; +input [15:0] ifmap_vec_1_q0; +output [7:0] weight_vecs_0_0_address0; +output weight_vecs_0_0_ce0; +input [15:0] weight_vecs_0_0_q0; +output [7:0] weight_vecs_0_1_address0; +output weight_vecs_0_1_ce0; +input [15:0] weight_vecs_0_1_q0; +output [7:0] weight_vecs_1_0_address0; +output weight_vecs_1_0_ce0; +input [15:0] weight_vecs_1_0_q0; +output [7:0] weight_vecs_1_1_address0; +output weight_vecs_1_1_ce0; +input [15:0] weight_vecs_1_1_q0; +output [7:0] weight_vecs_2_0_address0; +output weight_vecs_2_0_ce0; +input [15:0] weight_vecs_2_0_q0; +output [7:0] weight_vecs_2_1_address0; +output weight_vecs_2_1_ce0; +input [15:0] weight_vecs_2_1_q0; +output [7:0] weight_vecs_3_0_address0; +output weight_vecs_3_0_ce0; +input [15:0] weight_vecs_3_0_q0; +output [7:0] weight_vecs_3_1_address0; +output weight_vecs_3_1_ce0; +input [15:0] weight_vecs_3_1_q0; +output [7:0] products_0_0_address0; +output products_0_0_ce0; +output products_0_0_we0; +output [15:0] products_0_0_d0; +output [7:0] products_0_1_address0; +output products_0_1_ce0; +output products_0_1_we0; +output [15:0] products_0_1_d0; +output [7:0] products_1_0_address0; +output products_1_0_ce0; +output products_1_0_we0; +output [15:0] products_1_0_d0; +output [7:0] products_1_1_address0; +output products_1_1_ce0; +output products_1_1_we0; +output [15:0] products_1_1_d0; +output [7:0] products_2_0_address0; +output products_2_0_ce0; +output products_2_0_we0; +output [15:0] products_2_0_d0; +output [7:0] products_2_1_address0; +output products_2_1_ce0; +output products_2_1_we0; +output [15:0] products_2_1_d0; +output [7:0] products_3_0_address0; +output products_3_0_ce0; +output products_3_0_we0; +output [15:0] products_3_0_d0; +output [7:0] products_3_1_address0; +output products_3_1_ce0; +output products_3_1_we0; +output [15:0] products_3_1_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_0_ce0; +reg ifmap_vec_1_ce0; +reg weight_vecs_0_0_ce0; +reg weight_vecs_0_1_ce0; +reg weight_vecs_1_0_ce0; +reg weight_vecs_1_1_ce0; +reg weight_vecs_2_0_ce0; +reg weight_vecs_2_1_ce0; +reg weight_vecs_3_0_ce0; +reg weight_vecs_3_1_ce0; +reg products_0_0_ce0; +reg products_0_0_we0; +reg products_0_1_ce0; +reg products_0_1_we0; +reg products_1_0_ce0; +reg products_1_0_we0; +reg products_1_1_ce0; +reg products_1_1_we0; +reg products_2_0_ce0; +reg products_2_0_we0; +reg products_2_1_ce0; +reg products_2_1_we0; +reg products_3_0_ce0; +reg products_3_0_we0; +reg products_3_1_ce0; +reg products_3_1_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] indvar_flatten17_reg_334; +reg [1:0] ii_reg_345; +reg [6:0] indvar_flatten_reg_356; +reg [1:0] jj_reg_367; +reg [5:0] ic_reg_378; +wire [7:0] add_ln147_1_fu_421_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln147_fu_455_p2; +reg [0:0] icmp_ln147_reg_730; +reg [0:0] icmp_ln147_reg_730_pp0_iter1_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter2_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter3_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter4_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter5_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter6_reg; +reg [0:0] icmp_ln147_reg_730_pp0_iter7_reg; +wire [1:0] select_ln147_3_fu_489_p3; +reg [1:0] select_ln147_3_reg_734; +wire [1:0] select_ln148_1_fu_591_p3; +reg [1:0] select_ln148_1_reg_739; +wire [5:0] empty_79_fu_603_p2; +reg [5:0] empty_79_reg_744; +wire [3:0] select_ln148_2_fu_619_p3; +reg [3:0] select_ln148_2_reg_749; +reg [3:0] select_ln148_2_reg_749_pp0_iter1_reg; +reg [3:0] select_ln148_2_reg_749_pp0_iter2_reg; +reg [3:0] select_ln148_2_reg_749_pp0_iter3_reg; +reg [3:0] select_ln148_2_reg_749_pp0_iter4_reg; +reg [3:0] select_ln148_2_reg_749_pp0_iter5_reg; +reg [3:0] select_ln148_2_reg_749_pp0_iter6_reg; +reg [3:0] select_ln148_2_reg_749_pp0_iter7_reg; +reg [3:0] newIndex_reg_755; +reg [3:0] newIndex_reg_755_pp0_iter1_reg; +reg [3:0] newIndex_reg_755_pp0_iter2_reg; +reg [3:0] newIndex_reg_755_pp0_iter3_reg; +reg [3:0] newIndex_reg_755_pp0_iter4_reg; +reg [3:0] newIndex_reg_755_pp0_iter5_reg; +reg [3:0] newIndex_reg_755_pp0_iter6_reg; +reg [3:0] newIndex_reg_755_pp0_iter7_reg; +reg [3:0] tmp_s_reg_761; +reg [3:0] tmp_s_reg_761_pp0_iter1_reg; +reg [3:0] tmp_s_reg_761_pp0_iter2_reg; +reg [3:0] tmp_s_reg_761_pp0_iter3_reg; +reg [3:0] tmp_s_reg_761_pp0_iter4_reg; +reg [3:0] tmp_s_reg_761_pp0_iter5_reg; +reg [3:0] tmp_s_reg_761_pp0_iter6_reg; +reg [3:0] tmp_s_reg_761_pp0_iter7_reg; +wire [5:0] add_ln149_fu_657_p2; +wire [6:0] select_ln148_3_fu_669_p3; +reg [15:0] ifmap_vec_0_load_reg_826; +reg [15:0] weight_vecs_0_0_load_reg_834; +reg [15:0] weight_vecs_1_0_load_reg_839; +reg [15:0] weight_vecs_2_0_load_reg_844; +reg [15:0] weight_vecs_3_0_load_reg_849; +reg [15:0] ifmap_vec_1_load_reg_854; +reg [15:0] weight_vecs_0_1_load_reg_862; +reg [15:0] weight_vecs_1_1_load_reg_867; +reg [15:0] weight_vecs_2_1_load_reg_872; +reg [15:0] weight_vecs_3_1_load_reg_877; +wire [15:0] grp_fu_389_p2; +reg [15:0] mul_reg_882; +wire [15:0] grp_fu_393_p2; +reg [15:0] mul_1_reg_887; +wire [15:0] grp_fu_397_p2; +reg [15:0] mul_2_reg_892; +wire [15:0] grp_fu_401_p2; +reg [15:0] mul_3_reg_897; +wire [15:0] grp_fu_405_p2; +reg [15:0] mul27_1_reg_902; +wire [15:0] grp_fu_409_p2; +reg [15:0] mul27_1_1_reg_907; +wire [15:0] grp_fu_413_p2; +reg [15:0] mul27_1_2_reg_912; +wire [15:0] grp_fu_417_p2; +reg [15:0] mul27_1_3_reg_917; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg [1:0] ap_phi_mux_ii_phi_fu_349_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_371_p4; +wire [63:0] tmp_29_fu_683_p1; +wire [63:0] zext_ln153_fu_703_p1; +wire [63:0] zext_ln153_1_fu_717_p1; +wire [3:0] shl_ln_fu_431_p3; +wire [3:0] zext_ln150_fu_427_p1; +wire [3:0] sub_ln150_fu_439_p2; +wire [3:0] zext_ln150_1_fu_445_p1; +wire [0:0] icmp_ln148_fu_467_p2; +wire [1:0] add_ln147_fu_461_p2; +wire [3:0] tmp_fu_501_p3; +wire [4:0] tmp_cast_fu_509_p1; +wire [4:0] select_ln147_3_cast_fu_497_p1; +wire [4:0] empty_78_fu_513_p2; +wire [3:0] shl_ln150_mid1_fu_527_p3; +wire [3:0] zext_ln150_2_fu_523_p1; +wire [3:0] sub_ln150_1_fu_535_p2; +wire [3:0] add_ln150_fu_449_p2; +wire [0:0] tmp_15_fu_557_p3; +wire [0:0] xor_ln149_fu_565_p2; +wire [1:0] select_ln147_fu_473_p3; +wire [0:0] or_ln147_fu_571_p2; +wire [5:0] select_ln147_2_fu_481_p3; +wire [1:0] add_ln148_fu_577_p2; +wire [5:0] sext_ln150_fu_519_p1; +wire [5:0] select_ln148_1_cast_fu_599_p1; +wire [3:0] select_ln147_4_fu_541_p3; +wire [3:0] zext_ln150_3_fu_609_p1; +wire [3:0] select_ln147_5_fu_549_p3; +wire [3:0] add_ln150_1_fu_613_p2; +wire [5:0] select_ln148_fu_583_p3; +wire [4:0] trunc_ln149_fu_627_p1; +wire [4:0] or_ln150_fu_641_p2; +wire [6:0] add_ln148_1_fu_663_p2; +wire [9:0] tmp_16_fu_677_p3; +wire [7:0] lshr_ln_fu_697_p3; +wire [7:0] lshr_ln153_1_fu_711_p3; +wire ap_CS_fsm_state11; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1195( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_826), + .din1(weight_vecs_0_0_load_reg_834), + .dout(grp_fu_389_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1196( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_826), + .din1(weight_vecs_1_0_load_reg_839), + .dout(grp_fu_393_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1197( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_826), + .din1(weight_vecs_2_0_load_reg_844), + .dout(grp_fu_397_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1198( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_load_reg_826), + .din1(weight_vecs_3_0_load_reg_849), + .dout(grp_fu_401_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1199( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_854), + .din1(weight_vecs_0_1_load_reg_862), + .dout(grp_fu_405_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1200( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_854), + .din1(weight_vecs_1_1_load_reg_867), + .dout(grp_fu_409_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1201( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_854), + .din1(weight_vecs_2_1_load_reg_872), + .dout(grp_fu_413_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1202( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_1_load_reg_854), + .din1(weight_vecs_3_1_load_reg_877), + .dout(grp_fu_417_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_455_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ic_reg_378 <= add_ln149_fu_657_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_reg_378 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_730 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_345 <= select_ln147_3_reg_734; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_345 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_455_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten17_reg_334 <= add_ln147_1_fu_421_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten17_reg_334 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_455_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten_reg_356 <= select_ln148_3_fu_669_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_356 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_730 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_367 <= select_ln148_1_reg_739; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_367 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_455_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + empty_79_reg_744 <= empty_79_fu_603_p2; + newIndex_reg_755 <= {{select_ln148_fu_583_p3[4:1]}}; + select_ln148_2_reg_749 <= select_ln148_2_fu_619_p3; + tmp_s_reg_761 <= {{or_ln150_fu_641_p2[4:1]}}; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln147_reg_730 <= icmp_ln147_fu_455_p2; + icmp_ln147_reg_730_pp0_iter1_reg <= icmp_ln147_reg_730; + newIndex_reg_755_pp0_iter1_reg <= newIndex_reg_755; + select_ln148_2_reg_749_pp0_iter1_reg <= select_ln148_2_reg_749; + tmp_s_reg_761_pp0_iter1_reg <= tmp_s_reg_761; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln147_reg_730_pp0_iter2_reg <= icmp_ln147_reg_730_pp0_iter1_reg; + icmp_ln147_reg_730_pp0_iter3_reg <= icmp_ln147_reg_730_pp0_iter2_reg; + icmp_ln147_reg_730_pp0_iter4_reg <= icmp_ln147_reg_730_pp0_iter3_reg; + icmp_ln147_reg_730_pp0_iter5_reg <= icmp_ln147_reg_730_pp0_iter4_reg; + icmp_ln147_reg_730_pp0_iter6_reg <= icmp_ln147_reg_730_pp0_iter5_reg; + icmp_ln147_reg_730_pp0_iter7_reg <= icmp_ln147_reg_730_pp0_iter6_reg; + newIndex_reg_755_pp0_iter2_reg <= newIndex_reg_755_pp0_iter1_reg; + newIndex_reg_755_pp0_iter3_reg <= newIndex_reg_755_pp0_iter2_reg; + newIndex_reg_755_pp0_iter4_reg <= newIndex_reg_755_pp0_iter3_reg; + newIndex_reg_755_pp0_iter5_reg <= newIndex_reg_755_pp0_iter4_reg; + newIndex_reg_755_pp0_iter6_reg <= newIndex_reg_755_pp0_iter5_reg; + newIndex_reg_755_pp0_iter7_reg <= newIndex_reg_755_pp0_iter6_reg; + select_ln148_2_reg_749_pp0_iter2_reg <= select_ln148_2_reg_749_pp0_iter1_reg; + select_ln148_2_reg_749_pp0_iter3_reg <= select_ln148_2_reg_749_pp0_iter2_reg; + select_ln148_2_reg_749_pp0_iter4_reg <= select_ln148_2_reg_749_pp0_iter3_reg; + select_ln148_2_reg_749_pp0_iter5_reg <= select_ln148_2_reg_749_pp0_iter4_reg; + select_ln148_2_reg_749_pp0_iter6_reg <= select_ln148_2_reg_749_pp0_iter5_reg; + select_ln148_2_reg_749_pp0_iter7_reg <= select_ln148_2_reg_749_pp0_iter6_reg; + tmp_s_reg_761_pp0_iter2_reg <= tmp_s_reg_761_pp0_iter1_reg; + tmp_s_reg_761_pp0_iter3_reg <= tmp_s_reg_761_pp0_iter2_reg; + tmp_s_reg_761_pp0_iter4_reg <= tmp_s_reg_761_pp0_iter3_reg; + tmp_s_reg_761_pp0_iter5_reg <= tmp_s_reg_761_pp0_iter4_reg; + tmp_s_reg_761_pp0_iter6_reg <= tmp_s_reg_761_pp0_iter5_reg; + tmp_s_reg_761_pp0_iter7_reg <= tmp_s_reg_761_pp0_iter6_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_730_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_load_reg_826 <= ifmap_vec_0_q0; + ifmap_vec_1_load_reg_854 <= ifmap_vec_1_q0; + weight_vecs_0_0_load_reg_834 <= weight_vecs_0_0_q0; + weight_vecs_0_1_load_reg_862 <= weight_vecs_0_1_q0; + weight_vecs_1_0_load_reg_839 <= weight_vecs_1_0_q0; + weight_vecs_1_1_load_reg_867 <= weight_vecs_1_1_q0; + weight_vecs_2_0_load_reg_844 <= weight_vecs_2_0_q0; + weight_vecs_2_1_load_reg_872 <= weight_vecs_2_1_q0; + weight_vecs_3_0_load_reg_849 <= weight_vecs_3_0_q0; + weight_vecs_3_1_load_reg_877 <= weight_vecs_3_1_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_730_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul27_1_1_reg_907 <= grp_fu_409_p2; + mul27_1_2_reg_912 <= grp_fu_413_p2; + mul27_1_3_reg_917 <= grp_fu_417_p2; + mul27_1_reg_902 <= grp_fu_405_p2; + mul_1_reg_887 <= grp_fu_393_p2; + mul_2_reg_892 <= grp_fu_397_p2; + mul_3_reg_897 <= grp_fu_401_p2; + mul_reg_882 <= grp_fu_389_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_fu_455_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln147_3_reg_734 <= select_ln147_3_fu_489_p3; + select_ln148_1_reg_739 <= select_ln148_1_fu_591_p3; + end +end + +always @ (*) begin + if ((icmp_ln147_fu_455_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_730 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_349_p4 = select_ln147_3_reg_734; + end else begin + ap_phi_mux_ii_phi_fu_349_p4 = ii_reg_345; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln147_reg_730 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_371_p4 = select_ln148_1_reg_739; + end else begin + ap_phi_mux_jj_phi_fu_371_p4 = jj_reg_367; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_1_ce0 = 1'b1; + end else begin + ifmap_vec_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_0_ce0 = 1'b1; + end else begin + products_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_0_we0 = 1'b1; + end else begin + products_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_1_ce0 = 1'b1; + end else begin + products_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_0_1_we0 = 1'b1; + end else begin + products_0_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_0_ce0 = 1'b1; + end else begin + products_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_0_we0 = 1'b1; + end else begin + products_1_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_1_ce0 = 1'b1; + end else begin + products_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_1_1_we0 = 1'b1; + end else begin + products_1_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_0_ce0 = 1'b1; + end else begin + products_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_0_we0 = 1'b1; + end else begin + products_2_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_1_ce0 = 1'b1; + end else begin + products_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_2_1_we0 = 1'b1; + end else begin + products_2_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_0_ce0 = 1'b1; + end else begin + products_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_0_we0 = 1'b1; + end else begin + products_3_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_1_ce0 = 1'b1; + end else begin + products_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter8 == 1'b1) & (icmp_ln147_reg_730_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + products_3_1_we0 = 1'b1; + end else begin + products_3_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_ce0 = 1'b1; + end else begin + weight_vecs_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_ce0 = 1'b1; + end else begin + weight_vecs_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_ce0 = 1'b1; + end else begin + weight_vecs_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_0_ce0 = 1'b1; + end else begin + weight_vecs_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_1_ce0 = 1'b1; + end else begin + weight_vecs_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_0_ce0 = 1'b1; + end else begin + weight_vecs_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_1_ce0 = 1'b1; + end else begin + weight_vecs_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln147_fu_455_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter8 == 1'b1) & (ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter8 == 1'b1) & (ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln147_fu_455_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state11; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_1_fu_421_p2 = (indvar_flatten17_reg_334 + 8'd1); + +assign add_ln147_fu_461_p2 = (ap_phi_mux_ii_phi_fu_349_p4 + 2'd1); + +assign add_ln148_1_fu_663_p2 = (indvar_flatten_reg_356 + 7'd1); + +assign add_ln148_fu_577_p2 = (select_ln147_fu_473_p3 + 2'd1); + +assign add_ln149_fu_657_p2 = (select_ln148_fu_583_p3 + 6'd2); + +assign add_ln150_1_fu_613_p2 = (select_ln147_4_fu_541_p3 + zext_ln150_3_fu_609_p1); + +assign add_ln150_fu_449_p2 = (sub_ln150_fu_439_p2 + zext_ln150_1_fu_445_p1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign empty_78_fu_513_p2 = (tmp_cast_fu_509_p1 - select_ln147_3_cast_fu_497_p1); + +assign empty_79_fu_603_p2 = ((sext_ln150_fu_519_p1) + (select_ln148_1_cast_fu_599_p1)); + +assign icmp_ln147_fu_455_p2 = ((indvar_flatten17_reg_334 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln148_fu_467_p2 = ((indvar_flatten_reg_356 == 7'd48) ? 1'b1 : 1'b0); + +assign ifmap_vec_0_address0 = tmp_29_fu_683_p1; + +assign ifmap_vec_1_address0 = tmp_29_fu_683_p1; + +assign lshr_ln153_1_fu_711_p3 = {{select_ln148_2_reg_749_pp0_iter7_reg}, {tmp_s_reg_761_pp0_iter7_reg}}; + +assign lshr_ln_fu_697_p3 = {{select_ln148_2_reg_749_pp0_iter7_reg}, {newIndex_reg_755_pp0_iter7_reg}}; + +assign or_ln147_fu_571_p2 = (xor_ln149_fu_565_p2 | icmp_ln148_fu_467_p2); + +assign or_ln150_fu_641_p2 = (trunc_ln149_fu_627_p1 | 5'd1); + +assign products_0_0_address0 = zext_ln153_fu_703_p1; + +assign products_0_0_d0 = mul_reg_882; + +assign products_0_1_address0 = zext_ln153_1_fu_717_p1; + +assign products_0_1_d0 = mul27_1_reg_902; + +assign products_1_0_address0 = zext_ln153_fu_703_p1; + +assign products_1_0_d0 = mul_1_reg_887; + +assign products_1_1_address0 = zext_ln153_1_fu_717_p1; + +assign products_1_1_d0 = mul27_1_1_reg_907; + +assign products_2_0_address0 = zext_ln153_fu_703_p1; + +assign products_2_0_d0 = mul_2_reg_892; + +assign products_2_1_address0 = zext_ln153_1_fu_717_p1; + +assign products_2_1_d0 = mul27_1_2_reg_912; + +assign products_3_0_address0 = zext_ln153_fu_703_p1; + +assign products_3_0_d0 = mul_3_reg_897; + +assign products_3_1_address0 = zext_ln153_1_fu_717_p1; + +assign products_3_1_d0 = mul27_1_3_reg_917; + +assign select_ln147_2_fu_481_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? 6'd0 : ic_reg_378); + +assign select_ln147_3_cast_fu_497_p1 = select_ln147_3_fu_489_p3; + +assign select_ln147_3_fu_489_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? add_ln147_fu_461_p2 : ap_phi_mux_ii_phi_fu_349_p4); + +assign select_ln147_4_fu_541_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? sub_ln150_1_fu_535_p2 : sub_ln150_fu_439_p2); + +assign select_ln147_5_fu_549_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? sub_ln150_1_fu_535_p2 : add_ln150_fu_449_p2); + +assign select_ln147_fu_473_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_371_p4); + +assign select_ln148_1_cast_fu_599_p1 = select_ln148_1_fu_591_p3; + +assign select_ln148_1_fu_591_p3 = ((or_ln147_fu_571_p2[0:0] == 1'b1) ? select_ln147_fu_473_p3 : add_ln148_fu_577_p2); + +assign select_ln148_2_fu_619_p3 = ((or_ln147_fu_571_p2[0:0] == 1'b1) ? select_ln147_5_fu_549_p3 : add_ln150_1_fu_613_p2); + +assign select_ln148_3_fu_669_p3 = ((icmp_ln148_fu_467_p2[0:0] == 1'b1) ? 7'd1 : add_ln148_1_fu_663_p2); + +assign select_ln148_fu_583_p3 = ((or_ln147_fu_571_p2[0:0] == 1'b1) ? select_ln147_2_fu_481_p3 : 6'd0); + +assign sext_ln150_fu_519_p1 = (empty_78_fu_513_p2); + +assign shl_ln150_mid1_fu_527_p3 = {{add_ln147_fu_461_p2}, {2'd0}}; + +assign shl_ln_fu_431_p3 = {{ap_phi_mux_ii_phi_fu_349_p4}, {2'd0}}; + +assign sub_ln150_1_fu_535_p2 = (shl_ln150_mid1_fu_527_p3 - zext_ln150_2_fu_523_p1); + +assign sub_ln150_fu_439_p2 = (shl_ln_fu_431_p3 - zext_ln150_fu_427_p1); + +assign tmp_15_fu_557_p3 = ic_reg_378[32'd5]; + +assign tmp_16_fu_677_p3 = {{empty_79_reg_744}, {newIndex_reg_755}}; + +assign tmp_29_fu_683_p1 = (tmp_16_fu_677_p3); + +assign tmp_cast_fu_509_p1 = tmp_fu_501_p3; + +assign tmp_fu_501_p3 = {{select_ln147_3_fu_489_p3}, {2'd0}}; + +assign trunc_ln149_fu_627_p1 = select_ln148_fu_583_p3[4:0]; + +assign weight_vecs_0_0_address0 = tmp_29_fu_683_p1; + +assign weight_vecs_0_1_address0 = tmp_29_fu_683_p1; + +assign weight_vecs_1_0_address0 = tmp_29_fu_683_p1; + +assign weight_vecs_1_1_address0 = tmp_29_fu_683_p1; + +assign weight_vecs_2_0_address0 = tmp_29_fu_683_p1; + +assign weight_vecs_2_1_address0 = tmp_29_fu_683_p1; + +assign weight_vecs_3_0_address0 = tmp_29_fu_683_p1; + +assign weight_vecs_3_1_address0 = tmp_29_fu_683_p1; + +assign xor_ln149_fu_565_p2 = (tmp_15_fu_557_p3 ^ 1'd1); + +assign zext_ln150_1_fu_445_p1 = ap_phi_mux_jj_phi_fu_371_p4; + +assign zext_ln150_2_fu_523_p1 = add_ln147_fu_461_p2; + +assign zext_ln150_3_fu_609_p1 = add_ln148_fu_577_p2; + +assign zext_ln150_fu_427_p1 = ap_phi_mux_ii_phi_fu_349_p4; + +assign zext_ln153_1_fu_717_p1 = lshr_ln153_1_fu_711_p3; + +assign zext_ln153_fu_703_p1 = lshr_ln_fu_697_p3; + +endmodule //td_fused_top_tdf8_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf8_filters_0_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 32; +parameter AWIDTH = 14; +parameter MEM_SIZE = 9216; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf8_filters_0( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd32; +parameter AddressRange = 32'd9216; +parameter AddressWidth = 32'd14; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf8_filters_0_ram td_fused_top_tdf8_filters_0_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + module td_fused_top_tdf8_filters_1_rom ( +addr0, ce0, q0, clk); + +parameter DWIDTH = 32; +parameter AWIDTH = 14; +parameter MEM_SIZE = 9216; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf8_filters_1_rom.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) + begin + q0 <= ram[addr0]; + end +end + + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf8_filters_1( + reset, + clk, + address0, + ce0, + q0); + +parameter DataWidth = 32'd32; +parameter AddressRange = 32'd9216; +parameter AddressWidth = 32'd14; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; + + + +td_fused_top_tdf8_filters_1_rom td_fused_top_tdf8_filters_1_rom_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + input_indices_2_out_din, + input_indices_2_out_full_n, + input_indices_2_out_write, + input_indices_2_out1_din, + input_indices_2_out1_full_n, + input_indices_2_out1_write, + output_indices_0_din, + output_indices_0_full_n, + output_indices_0_write, + output_indices_1_din, + output_indices_1_full_n, + output_indices_1_write, + resetMaximum_din, + resetMaximum_full_n, + resetMaximum_write, + storeOutput_din, + storeOutput_full_n, + storeOutput_write, + ap_return_0, + ap_return_1 +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [5:0] input_indices_2_out_din; +input input_indices_2_out_full_n; +output input_indices_2_out_write; +output [7:0] input_indices_2_out1_din; +input input_indices_2_out1_full_n; +output input_indices_2_out1_write; +output [3:0] output_indices_0_din; +input output_indices_0_full_n; +output output_indices_0_write; +output [7:0] output_indices_1_din; +input output_indices_1_full_n; +output output_indices_1_write; +output resetMaximum_din; +input resetMaximum_full_n; +output resetMaximum_write; +output storeOutput_din; +input storeOutput_full_n; +output storeOutput_write; +output [15:0] ap_return_0; +output [15:0] ap_return_1; + +reg ap_done; +reg ap_idle; +reg start_write; +reg input_indices_2_out_write; +reg input_indices_2_out1_write; +reg output_indices_0_write; +reg output_indices_1_write; +reg resetMaximum_write; +reg storeOutput_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [1:0] i_p; +reg [1:0] j_p; +reg [15:0] i_8; +reg [15:0] j_8; +reg [15:0] k_8; +reg [15:0] i_out; +reg [15:0] j_out; +reg input_indices_2_out_blk_n; +reg input_indices_2_out1_blk_n; +reg output_indices_0_blk_n; +reg output_indices_1_blk_n; +reg resetMaximum_blk_n; +reg storeOutput_blk_n; +wire [1:0] select_ln142_fu_342_p3; +reg ap_block_state1; +wire [0:0] or_ln142_fu_316_p2; +wire [1:0] select_ln142_1_fu_350_p3; +wire [15:0] select_ln147_fu_282_p3; +wire [0:0] and_ln142_1_fu_310_p2; +wire [15:0] select_ln142_2_fu_364_p3; +wire [0:0] and_ln132_fu_358_p2; +wire [15:0] select_ln142_3_fu_392_p3; +wire [0:0] and_ln135_fu_298_p2; +wire [15:0] select_ln147_1_fu_290_p3; +wire [15:0] select_ln142_4_fu_400_p3; +wire [1:0] or_ln124_fu_126_p2; +wire [0:0] icmp_ln125_fu_139_p2; +wire [0:0] icmp_ln125_1_fu_145_p2; +wire [15:0] zext_ln126_fu_114_p1; +wire [15:0] zext_ln127_fu_122_p1; +wire [1:0] add_ln131_fu_210_p2; +wire [1:0] add_ln134_fu_222_p2; +wire [15:0] add_ln137_fu_234_p2; +wire [15:0] add_ln141_fu_252_p2; +wire [15:0] add_ln146_fu_270_p2; +wire [0:0] icmp_ln147_fu_276_p2; +wire [15:0] add_ln145_fu_264_p2; +wire [0:0] icmp_ln132_fu_216_p2; +wire [0:0] icmp_ln135_fu_228_p2; +wire [0:0] icmp_ln138_fu_240_p2; +wire [0:0] icmp_ln142_fu_258_p2; +wire [0:0] and_ln142_fu_304_p2; +wire [0:0] xor_ln135_fu_322_p2; +wire [0:0] and_ln135_1_fu_328_p2; +wire [1:0] select_ln135_fu_334_p3; +wire [15:0] add_ln140_fu_246_p2; +wire [0:0] xor_ln138_fu_372_p2; +wire [0:0] and_ln138_fu_378_p2; +wire [15:0] select_ln138_fu_384_p3; +wire [15:0] add_ln126_fu_162_p2; +wire [15:0] add_ln127_fu_172_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_p = 2'd0; +#0 j_p = 2'd0; +#0 i_8 = 16'd0; +#0 j_8 = 16'd0; +#0 k_8 = 16'd0; +#0 i_out = 16'd0; +#0 j_out = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln142_1_fu_310_p2))) begin + i_8 <= select_ln147_fu_282_p3; + i_out <= select_ln147_1_fu_290_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (or_ln142_fu_316_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_p <= select_ln142_fu_342_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln132_fu_358_p2))) begin + j_8 <= select_ln142_2_fu_364_p3; + j_out <= select_ln142_4_fu_400_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + j_p <= select_ln142_1_fu_350_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln135_fu_298_p2))) begin + k_8 <= select_ln142_3_fu_392_p3; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_blk_n = input_indices_2_out1_full_n; + end else begin + input_indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_write = 1'b1; + end else begin + input_indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_blk_n = input_indices_2_out_full_n; + end else begin + input_indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_write = 1'b1; + end else begin + input_indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_blk_n = output_indices_0_full_n; + end else begin + output_indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_write = 1'b1; + end else begin + output_indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_blk_n = output_indices_1_full_n; + end else begin + output_indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_write = 1'b1; + end else begin + output_indices_1_write = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_blk_n = resetMaximum_full_n; + end else begin + resetMaximum_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_write = 1'b1; + end else begin + resetMaximum_write = 1'b0; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_blk_n = storeOutput_full_n; + end else begin + storeOutput_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_write = 1'b1; + end else begin + storeOutput_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln126_fu_162_p2 = (i_8 + zext_ln126_fu_114_p1); + +assign add_ln127_fu_172_p2 = (j_8 + zext_ln127_fu_122_p1); + +assign add_ln131_fu_210_p2 = (j_p + 2'd1); + +assign add_ln134_fu_222_p2 = (i_p + 2'd1); + +assign add_ln137_fu_234_p2 = (k_8 + 16'd1); + +assign add_ln140_fu_246_p2 = (j_8 + 16'd2); + +assign add_ln141_fu_252_p2 = (j_out + 16'd1); + +assign add_ln145_fu_264_p2 = (i_8 + 16'd2); + +assign add_ln146_fu_270_p2 = (i_out + 16'd1); + +assign and_ln132_fu_358_p2 = (icmp_ln138_fu_240_p2 & and_ln135_fu_298_p2); + +assign and_ln135_1_fu_328_p2 = (xor_ln135_fu_322_p2 & icmp_ln132_fu_216_p2); + +assign and_ln135_fu_298_p2 = (icmp_ln135_fu_228_p2 & icmp_ln132_fu_216_p2); + +assign and_ln138_fu_378_p2 = (xor_ln138_fu_372_p2 & and_ln135_fu_298_p2); + +assign and_ln142_1_fu_310_p2 = (and_ln142_fu_304_p2 & and_ln135_fu_298_p2); + +assign and_ln142_fu_304_p2 = (icmp_ln142_fu_258_p2 & icmp_ln138_fu_240_p2); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign ap_return_0 = add_ln126_fu_162_p2; + +assign ap_return_1 = add_ln127_fu_172_p2; + +assign icmp_ln125_1_fu_145_p2 = ((j_p == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln125_fu_139_p2 = ((i_p == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln132_fu_216_p2 = ((add_ln131_fu_210_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln135_fu_228_p2 = ((add_ln134_fu_222_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln138_fu_240_p2 = ((add_ln137_fu_234_p2 == 16'd64) ? 1'b1 : 1'b0); + +assign icmp_ln142_fu_258_p2 = ((add_ln141_fu_252_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign icmp_ln147_fu_276_p2 = ((add_ln146_fu_270_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign input_indices_2_out1_din = k_8[7:0]; + +assign input_indices_2_out_din = k_8[5:0]; + +assign or_ln124_fu_126_p2 = (j_p | i_p); + +assign or_ln142_fu_316_p2 = (icmp_ln132_fu_216_p2 | and_ln142_1_fu_310_p2); + +assign output_indices_0_din = i_out[3:0]; + +assign output_indices_1_din = j_out[7:0]; + +assign resetMaximum_din = ((or_ln124_fu_126_p2 == 2'd0) ? 1'b1 : 1'b0); + +assign select_ln135_fu_334_p3 = ((and_ln135_1_fu_328_p2[0:0] == 1'b1) ? add_ln134_fu_222_p2 : 2'd0); + +assign select_ln138_fu_384_p3 = ((and_ln138_fu_378_p2[0:0] == 1'b1) ? add_ln137_fu_234_p2 : 16'd0); + +assign select_ln142_1_fu_350_p3 = ((or_ln142_fu_316_p2[0:0] == 1'b1) ? 2'd0 : add_ln131_fu_210_p2); + +assign select_ln142_2_fu_364_p3 = ((and_ln142_1_fu_310_p2[0:0] == 1'b1) ? 16'd0 : add_ln140_fu_246_p2); + +assign select_ln142_3_fu_392_p3 = ((and_ln142_1_fu_310_p2[0:0] == 1'b1) ? 16'd0 : select_ln138_fu_384_p3); + +assign select_ln142_4_fu_400_p3 = ((and_ln142_1_fu_310_p2[0:0] == 1'b1) ? 16'd0 : add_ln141_fu_252_p2); + +assign select_ln142_fu_342_p3 = ((and_ln142_1_fu_310_p2[0:0] == 1'b1) ? 2'd0 : select_ln135_fu_334_p3); + +assign select_ln147_1_fu_290_p3 = ((icmp_ln147_fu_276_p2[0:0] == 1'b1) ? 16'd0 : add_ln146_fu_270_p2); + +assign select_ln147_fu_282_p3 = ((icmp_ln147_fu_276_p2[0:0] == 1'b1) ? 16'd0 : add_ln145_fu_264_p2); + +assign start_out = real_start; + +assign storeOutput_din = (icmp_ln125_fu_139_p2 & icmp_ln125_1_fu_145_p2); + +assign xor_ln135_fu_322_p2 = (icmp_ln135_fu_228_p2 ^ 1'd1); + +assign xor_ln138_fu_372_p2 = (icmp_ln138_fu_240_p2 ^ 1'd1); + +assign zext_ln126_fu_114_p1 = i_p; + +assign zext_ln127_fu_122_p1 = j_p; + +endmodule //td_fused_top_tdf8_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_poolOutputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + output_indices_04_dout, + output_indices_04_empty_n, + output_indices_04_read, + output_indices_15_dout, + output_indices_15_empty_n, + output_indices_15_read, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + resetMaximum6_dout, + resetMaximum6_empty_n, + resetMaximum6_read, + storeOutput7_dout, + storeOutput7_empty_n, + storeOutput7_read, + outputs_0_read, + outputs_1_read, + outputs_2_read, + outputs_3_read, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_state3 = 4'd4; +parameter ap_ST_fsm_state4 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [3:0] output_indices_04_dout; +input output_indices_04_empty_n; +output output_indices_04_read; +input [7:0] output_indices_15_dout; +input output_indices_15_empty_n; +output output_indices_15_read; +input [7:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +input [0:0] resetMaximum6_dout; +input resetMaximum6_empty_n; +output resetMaximum6_read; +input [0:0] storeOutput7_dout; +input storeOutput7_empty_n; +output storeOutput7_read; +input [15:0] outputs_0_read; +input [15:0] outputs_1_read; +input [15:0] outputs_2_read; +input [15:0] outputs_3_read; +output [13:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg output_indices_04_read; +reg output_indices_15_read; +reg input_indices_23_read; +reg resetMaximum6_read; +reg storeOutput7_read; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] max_vals_0; +reg [15:0] max_vals_1; +reg [15:0] max_vals_2; +reg [15:0] max_vals; +reg output_indices_04_blk_n; +wire ap_CS_fsm_state2; +reg output_indices_15_blk_n; +reg input_indices_23_blk_n; +reg resetMaximum6_blk_n; +reg storeOutput7_blk_n; +reg [3:0] output_indices_04_read_reg_279; +reg [7:0] output_indices_15_read_reg_284; +reg [7:0] input_indices_23_read_reg_289; +wire [0:0] storeOutput7_read_read_fu_108_p2; +reg [0:0] storeOutput7_read_reg_294; +wire grp_tdf8_writeOutputs_aligned_fu_114_ap_start; +wire grp_tdf8_writeOutputs_aligned_fu_114_ap_done; +wire grp_tdf8_writeOutputs_aligned_fu_114_ap_idle; +wire grp_tdf8_writeOutputs_aligned_fu_114_ap_ready; +wire [13:0] grp_tdf8_writeOutputs_aligned_fu_114_out_data_address1; +wire grp_tdf8_writeOutputs_aligned_fu_114_out_data_ce1; +wire grp_tdf8_writeOutputs_aligned_fu_114_out_data_we1; +wire [63:0] grp_tdf8_writeOutputs_aligned_fu_114_out_data_d1; +reg grp_tdf8_writeOutputs_aligned_fu_114_ap_start_reg; +wire ap_CS_fsm_state3; +wire ap_CS_fsm_state4; +wire [15:0] select_ln24_fu_177_p3; +reg ap_block_state2; +wire [15:0] select_ln24_1_fu_195_p3; +wire [15:0] select_ln24_2_fu_213_p3; +wire [15:0] select_ln24_3_fu_231_p3; +reg ap_block_state1; +wire [0:0] grp_fu_131_p2; +wire [0:0] or_ln24_fu_171_p2; +wire [0:0] grp_fu_136_p2; +wire [0:0] or_ln24_1_fu_189_p2; +wire [0:0] grp_fu_141_p2; +wire [0:0] or_ln24_2_fu_207_p2; +wire [0:0] grp_fu_146_p2; +wire [0:0] or_ln24_3_fu_225_p2; +reg grp_fu_131_ce; +reg grp_fu_136_ce; +reg grp_fu_141_ce; +reg grp_fu_146_ce; +reg ap_block_state4_on_subcall_done; +reg [3:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 max_vals_0 = 16'd0; +#0 max_vals_1 = 16'd0; +#0 max_vals_2 = 16'd0; +#0 max_vals = 16'd0; +#0 grp_tdf8_writeOutputs_aligned_fu_114_ap_start_reg = 1'b0; +end + +td_fused_top_tdf8_writeOutputs_aligned grp_tdf8_writeOutputs_aligned_fu_114( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(grp_tdf8_writeOutputs_aligned_fu_114_ap_start), + .ap_done(grp_tdf8_writeOutputs_aligned_fu_114_ap_done), + .ap_idle(grp_tdf8_writeOutputs_aligned_fu_114_ap_idle), + .ap_ready(grp_tdf8_writeOutputs_aligned_fu_114_ap_ready), + .i(output_indices_04_read_reg_279), + .j(output_indices_15_read_reg_284), + .k(input_indices_23_read_reg_289), + .out_data_address1(grp_tdf8_writeOutputs_aligned_fu_114_out_data_address1), + .out_data_ce1(grp_tdf8_writeOutputs_aligned_fu_114_out_data_ce1), + .out_data_we1(grp_tdf8_writeOutputs_aligned_fu_114_out_data_we1), + .out_data_d1(grp_tdf8_writeOutputs_aligned_fu_114_out_data_d1), + .max_vals_0(max_vals_0), + .max_vals_1(max_vals_1), + .max_vals_2(max_vals_2), + .max_vals(max_vals) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U1266( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_131_ce), + .din0(max_vals_0), + .din1(outputs_0_read), + .opcode(5'd4), + .dout(grp_fu_131_p2) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U1267( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_136_ce), + .din0(max_vals_1), + .din1(outputs_1_read), + .opcode(5'd4), + .dout(grp_fu_136_p2) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U1268( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_141_ce), + .din0(max_vals_2), + .din1(outputs_2_read), + .opcode(5'd4), + .dout(grp_fu_141_p2) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U1269( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_146_ce), + .din0(max_vals), + .din1(outputs_3_read), + .opcode(5'd4), + .dout(grp_fu_146_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + grp_tdf8_writeOutputs_aligned_fu_114_ap_start_reg <= 1'b0; + end else begin + if ((1'b1 == ap_CS_fsm_state3)) begin + grp_tdf8_writeOutputs_aligned_fu_114_ap_start_reg <= 1'b1; + end else if ((grp_tdf8_writeOutputs_aligned_fu_114_ap_ready == 1'b1)) begin + grp_tdf8_writeOutputs_aligned_fu_114_ap_start_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + input_indices_23_read_reg_289 <= input_indices_23_dout; + output_indices_04_read_reg_279 <= output_indices_04_dout; + output_indices_15_read_reg_284 <= output_indices_15_dout; + storeOutput7_read_reg_294 <= storeOutput7_dout; + end +end + +always @ (posedge ap_clk) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + max_vals <= select_ln24_3_fu_231_p3; + max_vals_0 <= select_ln24_fu_177_p3; + max_vals_1 <= select_ln24_1_fu_195_p3; + max_vals_2 <= select_ln24_2_fu_213_p3; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_131_ce = 1'b1; + end else begin + grp_fu_131_ce = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_136_ce = 1'b1; + end else begin + grp_fu_136_ce = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_141_ce = 1'b1; + end else begin + grp_fu_141_ce = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_146_ce = 1'b1; + end else begin + grp_fu_146_ce = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_04_blk_n = output_indices_04_empty_n; + end else begin + output_indices_04_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_04_read = 1'b1; + end else begin + output_indices_04_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_15_blk_n = output_indices_15_empty_n; + end else begin + output_indices_15_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_15_read = 1'b1; + end else begin + output_indices_15_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + resetMaximum6_blk_n = resetMaximum6_empty_n; + end else begin + resetMaximum6_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + resetMaximum6_read = 1'b1; + end else begin + resetMaximum6_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + storeOutput7_blk_n = storeOutput7_empty_n; + end else begin + storeOutput7_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + storeOutput7_read = 1'b1; + end else begin + storeOutput7_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_108_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_108_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state3; + end else begin + ap_NS_fsm = ap_ST_fsm_state2; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +always @ (*) begin + ap_block_state2 = ((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (input_indices_23_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)); +end + +always @ (*) begin + ap_block_state4_on_subcall_done = ((grp_tdf8_writeOutputs_aligned_fu_114_ap_done == 1'b0) & (storeOutput7_read_reg_294 == 1'd1)); +end + +assign grp_tdf8_writeOutputs_aligned_fu_114_ap_start = grp_tdf8_writeOutputs_aligned_fu_114_ap_start_reg; + +assign or_ln24_1_fu_189_p2 = (resetMaximum6_dout | grp_fu_136_p2); + +assign or_ln24_2_fu_207_p2 = (resetMaximum6_dout | grp_fu_141_p2); + +assign or_ln24_3_fu_225_p2 = (resetMaximum6_dout | grp_fu_146_p2); + +assign or_ln24_fu_171_p2 = (resetMaximum6_dout | grp_fu_131_p2); + +assign out_data_address1 = grp_tdf8_writeOutputs_aligned_fu_114_out_data_address1; + +assign out_data_ce1 = grp_tdf8_writeOutputs_aligned_fu_114_out_data_ce1; + +assign out_data_d1 = grp_tdf8_writeOutputs_aligned_fu_114_out_data_d1; + +assign out_data_we1 = grp_tdf8_writeOutputs_aligned_fu_114_out_data_we1; + +assign select_ln24_1_fu_195_p3 = ((or_ln24_1_fu_189_p2[0:0] == 1'b1) ? outputs_1_read : max_vals_1); + +assign select_ln24_2_fu_213_p3 = ((or_ln24_2_fu_207_p2[0:0] == 1'b1) ? outputs_2_read : max_vals_2); + +assign select_ln24_3_fu_231_p3 = ((or_ln24_3_fu_225_p2[0:0] == 1'b1) ? outputs_3_read : max_vals); + +assign select_ln24_fu_177_p3 = ((or_ln24_fu_171_p2[0:0] == 1'b1) ? outputs_0_read : max_vals_0); + +assign storeOutput7_read_read_fu_108_p2 = storeOutput7_dout; + +endmodule //td_fused_top_tdf8_poolOutputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_readFilters58 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_0_address0, + filter_data_0_ce0, + filter_data_0_q0, + filter_data_1_address0, + filter_data_1_ce0, + filter_data_1_q0, + filter_data_2_address0, + filter_data_2_ce0, + filter_data_2_q0, + filter_data_3_address0, + filter_data_3_ce0, + filter_data_3_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + weight_vecs_0_0_address0, + weight_vecs_0_0_ce0, + weight_vecs_0_0_we0, + weight_vecs_0_0_d0, + weight_vecs_0_1_address0, + weight_vecs_0_1_ce0, + weight_vecs_0_1_we0, + weight_vecs_0_1_d0, + weight_vecs_1_0_address0, + weight_vecs_1_0_ce0, + weight_vecs_1_0_we0, + weight_vecs_1_0_d0, + weight_vecs_1_1_address0, + weight_vecs_1_1_ce0, + weight_vecs_1_1_we0, + weight_vecs_1_1_d0, + weight_vecs_2_0_address0, + weight_vecs_2_0_ce0, + weight_vecs_2_0_we0, + weight_vecs_2_0_d0, + weight_vecs_2_1_address0, + weight_vecs_2_1_ce0, + weight_vecs_2_1_we0, + weight_vecs_2_1_d0, + weight_vecs_3_0_address0, + weight_vecs_3_0_ce0, + weight_vecs_3_0_we0, + weight_vecs_3_0_d0, + weight_vecs_3_1_address0, + weight_vecs_3_1_ce0, + weight_vecs_3_1_we0, + weight_vecs_3_1_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state6 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [13:0] filter_data_0_address0; +output filter_data_0_ce0; +input [31:0] filter_data_0_q0; +output [13:0] filter_data_1_address0; +output filter_data_1_ce0; +input [31:0] filter_data_1_q0; +output [13:0] filter_data_2_address0; +output filter_data_2_ce0; +input [31:0] filter_data_2_q0; +output [13:0] filter_data_3_address0; +output filter_data_3_ce0; +input [31:0] filter_data_3_q0; +input [5:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [7:0] weight_vecs_0_0_address0; +output weight_vecs_0_0_ce0; +output weight_vecs_0_0_we0; +output [15:0] weight_vecs_0_0_d0; +output [7:0] weight_vecs_0_1_address0; +output weight_vecs_0_1_ce0; +output weight_vecs_0_1_we0; +output [15:0] weight_vecs_0_1_d0; +output [7:0] weight_vecs_1_0_address0; +output weight_vecs_1_0_ce0; +output weight_vecs_1_0_we0; +output [15:0] weight_vecs_1_0_d0; +output [7:0] weight_vecs_1_1_address0; +output weight_vecs_1_1_ce0; +output weight_vecs_1_1_we0; +output [15:0] weight_vecs_1_1_d0; +output [7:0] weight_vecs_2_0_address0; +output weight_vecs_2_0_ce0; +output weight_vecs_2_0_we0; +output [15:0] weight_vecs_2_0_d0; +output [7:0] weight_vecs_2_1_address0; +output weight_vecs_2_1_ce0; +output weight_vecs_2_1_we0; +output [15:0] weight_vecs_2_1_d0; +output [7:0] weight_vecs_3_0_address0; +output weight_vecs_3_0_ce0; +output weight_vecs_3_0_we0; +output [15:0] weight_vecs_3_0_d0; +output [7:0] weight_vecs_3_1_address0; +output weight_vecs_3_1_ce0; +output weight_vecs_3_1_we0; +output [15:0] weight_vecs_3_1_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_0_ce0; +reg filter_data_1_ce0; +reg filter_data_2_ce0; +reg filter_data_3_ce0; +reg input_indices_23_read; +reg weight_vecs_0_0_ce0; +reg weight_vecs_0_0_we0; +reg weight_vecs_0_1_ce0; +reg weight_vecs_0_1_we0; +reg weight_vecs_1_0_ce0; +reg weight_vecs_1_0_we0; +reg weight_vecs_1_1_ce0; +reg weight_vecs_1_1_we0; +reg weight_vecs_2_0_ce0; +reg weight_vecs_2_0_we0; +reg weight_vecs_2_1_ce0; +reg weight_vecs_2_1_we0; +reg weight_vecs_3_0_ce0; +reg weight_vecs_3_0_we0; +reg weight_vecs_3_1_ce0; +reg weight_vecs_3_1_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +reg [7:0] indvar_flatten13_reg_288; +reg [1:0] ii_reg_299; +reg [6:0] indvar_flatten_reg_310; +reg [1:0] jj_reg_321; +reg [5:0] kk_reg_332; +wire [9:0] sext_ln47_fu_365_p1; +reg [9:0] sext_ln47_reg_737; +wire [7:0] add_ln47_1_fu_369_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln47_fu_375_p2; +reg [0:0] icmp_ln47_reg_747; +reg [0:0] icmp_ln47_reg_747_pp0_iter1_reg; +reg [0:0] icmp_ln47_reg_747_pp0_iter2_reg; +wire [1:0] select_ln47_2_fu_409_p3; +reg [1:0] select_ln47_2_reg_751; +wire [9:0] add_ln55_fu_421_p2; +reg [9:0] add_ln55_reg_758; +wire [1:0] select_ln48_1_fu_460_p3; +reg [1:0] select_ln48_1_reg_764; +reg [3:0] lshr_ln_reg_771; +reg [3:0] lshr_ln_reg_771_pp0_iter1_reg; +reg [3:0] lshr_ln_reg_771_pp0_iter2_reg; +wire [5:0] add_ln49_fu_478_p2; +wire [6:0] select_ln48_2_fu_490_p3; +wire [5:0] add_ln55_2_fu_554_p2; +reg [5:0] add_ln55_2_reg_787; +reg [5:0] add_ln55_2_reg_787_pp0_iter2_reg; +reg [31:0] filter_data_0_load_reg_812; +reg [31:0] filter_data_1_load_reg_817; +reg [31:0] filter_data_2_load_reg_822; +reg [31:0] filter_data_3_load_reg_827; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg [1:0] ap_phi_mux_ii_phi_fu_303_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_325_p4; +wire [63:0] tmp_13_fu_560_p3; +wire [63:0] sext_ln55_2_fu_577_p1; +wire [7:0] tmp_s_fu_347_p3; +wire [8:0] zext_ln55_2_fu_355_p1; +wire [8:0] zext_ln55_fu_343_p1; +wire [8:0] sub_ln55_fu_359_p2; +wire [0:0] icmp_ln48_fu_387_p2; +wire [1:0] add_ln47_fu_381_p2; +wire [9:0] zext_ln55_4_fu_417_p1; +wire [0:0] tmp_12_fu_426_p3; +wire [0:0] xor_ln49_fu_434_p2; +wire [1:0] select_ln47_fu_393_p3; +wire [0:0] or_ln47_fu_440_p2; +wire [5:0] select_ln47_1_fu_401_p3; +wire [1:0] add_ln48_fu_446_p2; +wire [5:0] select_ln48_fu_452_p3; +wire [6:0] add_ln48_1_fu_484_p2; +wire [11:0] tmp_11_fu_504_p3; +wire [59:0] sext_ln55_1_fu_511_p1; +wire [59:0] sext_ln55_fu_501_p1; +wire [3:0] tmp_10_fu_521_p3; +wire [4:0] zext_ln55_5_fu_528_p1; +wire [4:0] zext_ln55_3_fu_498_p1; +wire [4:0] sub_ln55_2_fu_532_p2; +wire [59:0] sub_ln55_1_fu_515_p2; +wire [59:0] zext_ln55_7_fu_545_p1; +wire [5:0] sext_ln48_fu_538_p1; +wire [5:0] zext_ln55_6_fu_542_p1; +wire [59:0] add_ln55_1_fu_548_p2; +wire [9:0] tmp_14_fu_571_p3; +wire [31:0] tmp_fu_589_p6; +wire [15:0] trunc_ln55_fu_602_p1; +wire [31:0] tmp_1_fu_611_p6; +wire [15:0] trunc_ln55_1_fu_624_p1; +wire [31:0] tmp_2_fu_633_p6; +wire [15:0] trunc_ln55_2_fu_646_p1; +wire [31:0] tmp_3_fu_655_p6; +wire [15:0] trunc_ln55_3_fu_668_p1; +wire [15:0] tmp_21_i_i_fu_677_p4; +wire [15:0] tmp_23_i_i_fu_692_p4; +wire [15:0] tmp_25_i_i_fu_707_p4; +wire [15:0] tmp_27_i_i_fu_722_p4; +wire ap_CS_fsm_state6; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +end + +td_fused_top_mux_416_32_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 32 ), + .din2_WIDTH( 32 ), + .din3_WIDTH( 32 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 32 )) +mux_416_32_1_1_U1178( + .din0(filter_data_0_load_reg_812), + .din1(32'd0), + .din2(32'd0), + .din3(32'd0), + .din4(16'd0), + .dout(tmp_fu_589_p6) +); + +td_fused_top_mux_416_32_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 32 ), + .din2_WIDTH( 32 ), + .din3_WIDTH( 32 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 32 )) +mux_416_32_1_1_U1179( + .din0(filter_data_1_load_reg_817), + .din1(32'd0), + .din2(32'd0), + .din3(32'd0), + .din4(16'd0), + .dout(tmp_1_fu_611_p6) +); + +td_fused_top_mux_416_32_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 32 ), + .din2_WIDTH( 32 ), + .din3_WIDTH( 32 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 32 )) +mux_416_32_1_1_U1180( + .din0(filter_data_2_load_reg_822), + .din1(32'd0), + .din2(32'd0), + .din3(32'd0), + .din4(16'd0), + .dout(tmp_2_fu_633_p6) +); + +td_fused_top_mux_416_32_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 32 ), + .din1_WIDTH( 32 ), + .din2_WIDTH( 32 ), + .din3_WIDTH( 32 ), + .din4_WIDTH( 16 ), + .dout_WIDTH( 32 )) +mux_416_32_1_1_U1181( + .din0(filter_data_3_load_reg_827), + .din1(32'd0), + .din2(32'd0), + .din3(32'd0), + .din4(16'd0), + .dout(tmp_3_fu_655_p6) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_747 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_299 <= select_ln47_2_reg_751; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_299 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_375_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten13_reg_288 <= add_ln47_1_fu_369_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_288 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_375_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + indvar_flatten_reg_310 <= select_ln48_2_fu_490_p3; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_310 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_747 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_321 <= select_ln48_1_reg_764; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_321 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_375_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + kk_reg_332 <= add_ln49_fu_478_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_332 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_747 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln55_2_reg_787 <= add_ln55_2_fu_554_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln55_2_reg_787_pp0_iter2_reg <= add_ln55_2_reg_787; + icmp_ln47_reg_747_pp0_iter2_reg <= icmp_ln47_reg_747_pp0_iter1_reg; + lshr_ln_reg_771_pp0_iter2_reg <= lshr_ln_reg_771_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_375_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln55_reg_758 <= add_ln55_fu_421_p2; + lshr_ln_reg_771 <= {{select_ln48_fu_452_p3[4:1]}}; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_747_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_0_load_reg_812 <= filter_data_0_q0; + filter_data_1_load_reg_817 <= filter_data_1_q0; + filter_data_2_load_reg_822 <= filter_data_2_q0; + filter_data_3_load_reg_827 <= filter_data_3_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln47_reg_747 <= icmp_ln47_fu_375_p2; + icmp_ln47_reg_747_pp0_iter1_reg <= icmp_ln47_reg_747; + lshr_ln_reg_771_pp0_iter1_reg <= lshr_ln_reg_771; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_fu_375_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln47_2_reg_751 <= select_ln47_2_fu_409_p3; + select_ln48_1_reg_764 <= select_ln48_1_fu_460_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sext_ln47_reg_737 <= sext_ln47_fu_365_p1; + end +end + +always @ (*) begin + if ((icmp_ln47_fu_375_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_747 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_303_p4 = select_ln47_2_reg_751; + end else begin + ap_phi_mux_ii_phi_fu_303_p4 = ii_reg_299; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln47_reg_747 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_325_p4 = select_ln48_1_reg_764; + end else begin + ap_phi_mux_jj_phi_fu_325_p4 = jj_reg_321; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_0_ce0 = 1'b1; + end else begin + filter_data_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_1_ce0 = 1'b1; + end else begin + filter_data_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_2_ce0 = 1'b1; + end else begin + filter_data_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + filter_data_3_ce0 = 1'b1; + end else begin + filter_data_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_ce0 = 1'b1; + end else begin + weight_vecs_0_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_0_1_we0 = 1'b1; + end else begin + weight_vecs_0_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_ce0 = 1'b1; + end else begin + weight_vecs_1_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_0_we0 = 1'b1; + end else begin + weight_vecs_1_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_ce0 = 1'b1; + end else begin + weight_vecs_1_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_1_1_we0 = 1'b1; + end else begin + weight_vecs_1_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_0_ce0 = 1'b1; + end else begin + weight_vecs_2_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_0_we0 = 1'b1; + end else begin + weight_vecs_2_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_1_ce0 = 1'b1; + end else begin + weight_vecs_2_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_2_1_we0 = 1'b1; + end else begin + weight_vecs_2_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_0_ce0 = 1'b1; + end else begin + weight_vecs_3_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_0_we0 = 1'b1; + end else begin + weight_vecs_3_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_1_ce0 = 1'b1; + end else begin + weight_vecs_3_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter3 == 1'b1) & (icmp_ln47_reg_747_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + weight_vecs_3_1_we0 = 1'b1; + end else begin + weight_vecs_3_1_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln47_fu_375_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln47_fu_375_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln47_1_fu_369_p2 = (indvar_flatten13_reg_288 + 8'd1); + +assign add_ln47_fu_381_p2 = (ap_phi_mux_ii_phi_fu_303_p4 + 2'd1); + +assign add_ln48_1_fu_484_p2 = (indvar_flatten_reg_310 + 7'd1); + +assign add_ln48_fu_446_p2 = (select_ln47_fu_393_p3 + 2'd1); + +assign add_ln49_fu_478_p2 = (select_ln48_fu_452_p3 + 6'd2); + +assign add_ln55_1_fu_548_p2 = (sub_ln55_1_fu_515_p2 + zext_ln55_7_fu_545_p1); + +assign add_ln55_2_fu_554_p2 = ((sext_ln48_fu_538_p1) + (zext_ln55_6_fu_542_p1)); + +assign add_ln55_fu_421_p2 = ((sext_ln47_reg_737) + (zext_ln55_4_fu_417_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_0_address0 = tmp_13_fu_560_p3; + +assign filter_data_1_address0 = tmp_13_fu_560_p3; + +assign filter_data_2_address0 = tmp_13_fu_560_p3; + +assign filter_data_3_address0 = tmp_13_fu_560_p3; + +assign icmp_ln47_fu_375_p2 = ((indvar_flatten13_reg_288 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln48_fu_387_p2 = ((indvar_flatten_reg_310 == 7'd48) ? 1'b1 : 1'b0); + +assign or_ln47_fu_440_p2 = (xor_ln49_fu_434_p2 | icmp_ln48_fu_387_p2); + +assign select_ln47_1_fu_401_p3 = ((icmp_ln48_fu_387_p2[0:0] == 1'b1) ? 6'd0 : kk_reg_332); + +assign select_ln47_2_fu_409_p3 = ((icmp_ln48_fu_387_p2[0:0] == 1'b1) ? add_ln47_fu_381_p2 : ap_phi_mux_ii_phi_fu_303_p4); + +assign select_ln47_fu_393_p3 = ((icmp_ln48_fu_387_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_325_p4); + +assign select_ln48_1_fu_460_p3 = ((or_ln47_fu_440_p2[0:0] == 1'b1) ? select_ln47_fu_393_p3 : add_ln48_fu_446_p2); + +assign select_ln48_2_fu_490_p3 = ((icmp_ln48_fu_387_p2[0:0] == 1'b1) ? 7'd1 : add_ln48_1_fu_484_p2); + +assign select_ln48_fu_452_p3 = ((or_ln47_fu_440_p2[0:0] == 1'b1) ? select_ln47_1_fu_401_p3 : 6'd0); + +assign sext_ln47_fu_365_p1 = (sub_ln55_fu_359_p2); + +assign sext_ln48_fu_538_p1 = (sub_ln55_2_fu_532_p2); + +assign sext_ln55_1_fu_511_p1 = (tmp_11_fu_504_p3); + +assign sext_ln55_2_fu_577_p1 = (tmp_14_fu_571_p3); + +assign sext_ln55_fu_501_p1 = add_ln55_reg_758; + +assign sub_ln55_1_fu_515_p2 = ((sext_ln55_1_fu_511_p1) - (sext_ln55_fu_501_p1)); + +assign sub_ln55_2_fu_532_p2 = (zext_ln55_5_fu_528_p1 - zext_ln55_3_fu_498_p1); + +assign sub_ln55_fu_359_p2 = (zext_ln55_2_fu_355_p1 - zext_ln55_fu_343_p1); + +assign tmp_10_fu_521_p3 = {{select_ln47_2_reg_751}, {2'd0}}; + +assign tmp_11_fu_504_p3 = {{add_ln55_reg_758}, {2'd0}}; + +assign tmp_12_fu_426_p3 = kk_reg_332[32'd5]; + +assign tmp_13_fu_560_p3 = {{add_ln55_1_fu_548_p2}, {lshr_ln_reg_771}}; + +assign tmp_14_fu_571_p3 = {{add_ln55_2_reg_787_pp0_iter2_reg}, {lshr_ln_reg_771_pp0_iter2_reg}}; + +assign tmp_21_i_i_fu_677_p4 = {{tmp_fu_589_p6[31:16]}}; + +assign tmp_23_i_i_fu_692_p4 = {{tmp_1_fu_611_p6[31:16]}}; + +assign tmp_25_i_i_fu_707_p4 = {{tmp_2_fu_633_p6[31:16]}}; + +assign tmp_27_i_i_fu_722_p4 = {{tmp_3_fu_655_p6[31:16]}}; + +assign tmp_s_fu_347_p3 = {{input_indices_23_dout}, {2'd0}}; + +assign trunc_ln55_1_fu_624_p1 = tmp_1_fu_611_p6[15:0]; + +assign trunc_ln55_2_fu_646_p1 = tmp_2_fu_633_p6[15:0]; + +assign trunc_ln55_3_fu_668_p1 = tmp_3_fu_655_p6[15:0]; + +assign trunc_ln55_fu_602_p1 = tmp_fu_589_p6[15:0]; + +assign weight_vecs_0_0_address0 = sext_ln55_2_fu_577_p1; + +assign weight_vecs_0_0_d0 = trunc_ln55_fu_602_p1; + +assign weight_vecs_0_1_address0 = sext_ln55_2_fu_577_p1; + +assign weight_vecs_0_1_d0 = tmp_21_i_i_fu_677_p4; + +assign weight_vecs_1_0_address0 = sext_ln55_2_fu_577_p1; + +assign weight_vecs_1_0_d0 = trunc_ln55_1_fu_624_p1; + +assign weight_vecs_1_1_address0 = sext_ln55_2_fu_577_p1; + +assign weight_vecs_1_1_d0 = tmp_23_i_i_fu_692_p4; + +assign weight_vecs_2_0_address0 = sext_ln55_2_fu_577_p1; + +assign weight_vecs_2_0_d0 = trunc_ln55_2_fu_646_p1; + +assign weight_vecs_2_1_address0 = sext_ln55_2_fu_577_p1; + +assign weight_vecs_2_1_d0 = tmp_25_i_i_fu_707_p4; + +assign weight_vecs_3_0_address0 = sext_ln55_2_fu_577_p1; + +assign weight_vecs_3_0_d0 = trunc_ln55_3_fu_668_p1; + +assign weight_vecs_3_1_address0 = sext_ln55_2_fu_577_p1; + +assign weight_vecs_3_1_d0 = tmp_27_i_i_fu_722_p4; + +assign xor_ln49_fu_434_p2 = (tmp_12_fu_426_p3 ^ 1'd1); + +assign zext_ln55_2_fu_355_p1 = tmp_s_fu_347_p3; + +assign zext_ln55_3_fu_498_p1 = select_ln47_2_reg_751; + +assign zext_ln55_4_fu_417_p1 = select_ln47_2_fu_409_p3; + +assign zext_ln55_5_fu_528_p1 = tmp_10_fu_521_p3; + +assign zext_ln55_6_fu_542_p1 = select_ln48_1_reg_764; + +assign zext_ln55_7_fu_545_p1 = select_ln48_1_reg_764; + +assign zext_ln55_fu_343_p1 = input_indices_23_dout; + +endmodule //td_fused_top_tdf8_readFilters58 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_readInputs59 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + i_13, + j_13, + ifmap_vec_0_address0, + ifmap_vec_0_ce0, + ifmap_vec_0_we0, + ifmap_vec_0_d0, + ifmap_vec_1_address0, + ifmap_vec_1_ce0, + ifmap_vec_1_we0, + ifmap_vec_1_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state7 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [12:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] i_13; +input [15:0] j_13; +output [7:0] ifmap_vec_0_address0; +output ifmap_vec_0_ce0; +output ifmap_vec_0_we0; +output [15:0] ifmap_vec_0_d0; +output [7:0] ifmap_vec_1_address0; +output ifmap_vec_1_ce0; +output ifmap_vec_1_we0; +output [15:0] ifmap_vec_1_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg ifmap_vec_0_ce0; +reg ifmap_vec_0_we0; +reg ifmap_vec_1_ce0; +reg ifmap_vec_1_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] indvar_flatten47_reg_179; +reg [1:0] ii_reg_190; +reg [6:0] indvar_flatten_reg_202; +reg [1:0] jj_reg_213; +reg [5:0] kk_reg_225; +wire [17:0] p_cast_i_fu_254_p1; +reg [17:0] p_cast_i_reg_1043; +wire [9:0] trunc_ln22_fu_258_p1; +reg [9:0] trunc_ln22_reg_1049; +wire [17:0] sext_ln22_fu_268_p1; +reg [17:0] sext_ln22_reg_1055; +wire [4:0] p_cast_fu_272_p2; +reg [4:0] p_cast_reg_1061; +wire [0:0] or_ln23_1_fu_292_p2; +reg [0:0] or_ln23_1_reg_1067; +wire [9:0] p_mid137_fu_298_p2; +reg [9:0] p_mid137_reg_1072; +wire [7:0] add_ln19_1_fu_304_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_pp0_stage0_11001; +wire [0:0] empty_72_fu_319_p2; +reg [0:0] empty_72_reg_1082; +wire [0:0] is_padding_fu_354_p2; +reg [0:0] is_padding_reg_1087; +wire [0:0] icmp_ln19_fu_360_p2; +reg [0:0] icmp_ln19_reg_1094; +reg [0:0] icmp_ln19_reg_1094_pp0_iter1_reg; +reg [0:0] icmp_ln19_reg_1094_pp0_iter2_reg; +reg [0:0] icmp_ln19_reg_1094_pp0_iter3_reg; +wire [1:0] add_ln19_fu_366_p2; +reg [1:0] add_ln19_reg_1098; +wire [0:0] icmp_ln20_fu_372_p2; +reg [0:0] icmp_ln20_reg_1103; +wire [1:0] select_ln19_2_fu_394_p3; +reg [1:0] select_ln19_2_reg_1112; +reg [1:0] select_ln19_2_reg_1112_pp0_iter1_reg; +reg [1:0] select_ln19_2_reg_1112_pp0_iter2_reg; +wire [0:0] p_mid113_fu_411_p2; +reg [0:0] p_mid113_reg_1119; +wire [0:0] or_ln19_fu_431_p2; +reg [0:0] or_ln19_reg_1125; +reg [0:0] or_ln19_reg_1125_pp0_iter1_reg; +wire [1:0] add_ln20_fu_437_p2; +reg [1:0] add_ln20_reg_1132; +wire [5:0] select_ln20_fu_443_p3; +reg [5:0] select_ln20_reg_1137; +reg [5:0] select_ln20_reg_1137_pp0_iter1_reg; +reg [5:0] select_ln20_reg_1137_pp0_iter2_reg; +wire [1:0] select_ln20_1_fu_451_p3; +reg [1:0] select_ln20_1_reg_1142; +reg [1:0] select_ln20_1_reg_1142_pp0_iter1_reg; +reg [1:0] select_ln20_1_reg_1142_pp0_iter2_reg; +wire [17:0] add_ln22_2_fu_463_p2; +reg [17:0] add_ln22_2_reg_1148; +reg [2:0] lshr_ln_reg_1154; +reg [2:0] lshr_ln_reg_1154_pp0_iter1_reg; +wire [1:0] trunc_ln32_fu_478_p1; +reg [1:0] trunc_ln32_reg_1159; +reg [1:0] trunc_ln32_reg_1159_pp0_iter1_reg; +reg [1:0] trunc_ln32_reg_1159_pp0_iter2_reg; +reg [3:0] lshr_ln1_reg_1164; +reg [3:0] lshr_ln1_reg_1164_pp0_iter1_reg; +reg [3:0] lshr_ln1_reg_1164_pp0_iter2_reg; +reg [3:0] lshr_ln1_reg_1164_pp0_iter3_reg; +wire [5:0] add_ln25_fu_492_p2; +wire [6:0] select_ln20_5_fu_504_p3; +wire [9:0] select_ln19_7_fu_606_p3; +reg [9:0] select_ln19_7_reg_1179; +wire [0:0] or_ln23_5_fu_634_p2; +reg [0:0] or_ln23_5_reg_1184; +wire [0:0] select_ln20_2_fu_640_p3; +reg [0:0] select_ln20_2_reg_1189; +reg [0:0] select_ln20_2_reg_1189_pp0_iter2_reg; +reg [0:0] select_ln20_2_reg_1189_pp0_iter3_reg; +wire [9:0] p_mid1_fu_665_p2; +reg [9:0] p_mid1_reg_1195; +wire [10:0] sub_ln32_fu_701_p2; +reg [10:0] sub_ln32_reg_1200; +wire [5:0] add_ln33_fu_771_p2; +reg [5:0] add_ln33_reg_1210; +wire [6:0] sub_ln32_3_fu_854_p2; +reg [6:0] sub_ln32_3_reg_1215; +wire [63:0] lshr_ln32_fu_864_p2; +reg [63:0] lshr_ln32_reg_1220; +wire [6:0] sub_ln32_6_fu_955_p2; +reg [6:0] sub_ln32_6_reg_1225; +wire [63:0] lshr_ln32_2_fu_965_p2; +reg [63:0] lshr_ln32_2_reg_1230; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg [1:0] ap_phi_mux_ii_phi_fu_194_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_217_p4; +wire [63:0] sext_ln32_fu_739_p1; +wire [63:0] sext_ln33_fu_1007_p1; +wire [16:0] zext_ln19_fu_240_p1; +wire [16:0] empty_70_fu_248_p2; +wire [16:0] j_cast_i_fu_236_p1; +wire [16:0] add_ln22_fu_262_p2; +wire [4:0] empty_fu_244_p1; +wire [0:0] tmp_fu_278_p3; +wire [0:0] icmp_ln24_fu_286_p2; +wire [17:0] ii_cast_i_fu_310_p1; +wire [17:0] empty_71_fu_314_p2; +wire [17:0] zext_ln20_fu_325_p1; +wire [17:0] add_ln22_1_fu_329_p2; +wire [0:0] tmp_3_fu_334_p3; +wire [0:0] icmp_ln24_1_fu_342_p2; +wire [0:0] or_ln23_fu_348_p2; +wire [17:0] ii_cast_i_mid1_fu_402_p1; +wire [17:0] p_mid111_fu_406_p2; +wire [0:0] tmp_4_fu_417_p3; +wire [0:0] xor_ln25_fu_425_p2; +wire [1:0] select_ln19_fu_378_p3; +wire [5:0] select_ln19_1_fu_386_p3; +wire [17:0] zext_ln20_1_fu_459_p1; +wire [6:0] add_ln20_1_fu_498_p2; +wire [4:0] ii_cast_fu_512_p1; +wire [4:0] p_cast14_i_fu_516_p2; +wire [2:0] zext_ln22_fu_521_p1; +wire [2:0] tmp2_fu_532_p2; +wire [9:0] tmp2_cast_fu_538_p1; +wire [9:0] empty_73_fu_542_p2; +wire [4:0] ii_cast_mid1_fu_554_p1; +wire [4:0] p_cast14_i_mid1_fu_557_p2; +wire [0:0] or_ln23_3_fu_574_p2; +wire [4:0] row_coord_int_mid131_fu_584_p3; +wire [4:0] row_coord_int_fu_525_p3; +wire [9:0] col_coord_int_mid139_fu_592_p3; +wire [9:0] col_coord_int_fu_547_p3; +wire [0:0] tmp_5_fu_616_p3; +wire [0:0] icmp_ln24_2_fu_623_p2; +wire [0:0] or_ln23_4_fu_628_p2; +wire [0:0] select_ln19_4_fu_569_p3; +wire [0:0] select_ln19_5_fu_578_p3; +wire [4:0] select_ln19_3_fu_562_p3; +wire [2:0] zext_ln22_1_fu_613_p1; +wire [2:0] tmp2_mid1_fu_655_p2; +wire [9:0] tmp2_cast_mid1_fu_661_p1; +wire [4:0] select_ln19_6_fu_599_p3; +wire [4:0] row_coord_int_mid1_fu_647_p3; +wire [4:0] select_ln20_3_fu_670_p3; +wire [9:0] tmp_1_fu_677_p3; +wire [6:0] tmp_2_fu_689_p3; +wire [10:0] zext_ln32_fu_685_p1; +wire [10:0] zext_ln32_7_fu_697_p1; +wire [9:0] col_coord_int_mid1_fu_707_p3; +wire [9:0] select_ln20_4_fu_716_p3; +wire [11:0] sext_ln20_fu_713_p1; +wire [11:0] zext_ln32_8_fu_722_p1; +wire [11:0] add_ln32_fu_726_p2; +wire [14:0] tmp_6_fu_732_p3; +wire [3:0] tmp_s_fu_747_p3; +wire [4:0] zext_ln33_2_fu_754_p1; +wire [4:0] zext_ln33_fu_744_p1; +wire [4:0] sub_ln33_fu_758_p2; +wire [5:0] sub_ln33_cast_fu_764_p1; +wire [5:0] zext_ln33_3_fu_768_p1; +wire [5:0] empty_75_fu_777_p2; +wire [5:0] empty_76_fu_782_p2; +wire [6:0] zext_ln32_9_fu_794_p1; +wire [6:0] zext_ln32_10_fu_798_p1; +wire [0:0] icmp_ln32_fu_788_p2; +wire [6:0] sub_ln32_1_fu_812_p2; +wire [6:0] sub_ln32_2_fu_824_p2; +reg [63:0] tmp_7_fu_802_p4; +wire [6:0] xor_ln32_fu_818_p2; +wire [6:0] select_ln32_fu_830_p3; +wire [6:0] select_ln32_2_fu_846_p3; +wire [63:0] select_ln32_1_fu_838_p3; +wire [63:0] zext_ln32_11_fu_860_p1; +wire [1:0] or_ln329_i_fu_870_p2; +wire [5:0] tmp_9_fu_875_p3; +wire [5:0] empty_77_fu_883_p2; +wire [6:0] zext_ln32_13_fu_895_p1; +wire [6:0] zext_ln32_14_fu_899_p1; +wire [0:0] icmp_ln32_1_fu_889_p2; +wire [6:0] sub_ln32_4_fu_913_p2; +wire [6:0] sub_ln32_5_fu_925_p2; +reg [63:0] tmp_10_fu_903_p4; +wire [6:0] xor_ln32_1_fu_919_p2; +wire [6:0] select_ln32_3_fu_931_p3; +wire [6:0] select_ln32_5_fu_947_p3; +wire [63:0] select_ln32_4_fu_939_p3; +wire [63:0] zext_ln32_15_fu_961_p1; +wire [63:0] zext_ln32_12_fu_971_p1; +wire [63:0] lshr_ln32_1_fu_974_p2; +wire [63:0] and_ln32_fu_980_p2; +wire [15:0] trunc_ln32_1_fu_985_p1; +wire [15:0] in_data_elem_fu_989_p1; +wire [9:0] tmp_8_fu_1001_p3; +wire [63:0] zext_ln32_16_fu_1013_p1; +wire [63:0] lshr_ln32_3_fu_1016_p2; +wire [63:0] and_ln32_1_fu_1022_p2; +wire [15:0] trunc_ln32_2_fu_1027_p1; +wire [15:0] in_data_elem_1_fu_1031_p1; +wire ap_CS_fsm_state7; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1094 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ii_reg_190 <= select_ln19_2_reg_1112; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_190 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_360_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten47_reg_179 <= add_ln19_1_fu_304_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten47_reg_179 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_360_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_202 <= select_ln20_5_fu_504_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_202 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1094 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + jj_reg_213 <= select_ln20_1_reg_1142; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_213 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_360_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_reg_225 <= add_ln25_fu_492_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_225 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_360_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln19_reg_1098 <= add_ln19_fu_366_p2; + add_ln20_reg_1132 <= add_ln20_fu_437_p2; + add_ln22_2_reg_1148 <= add_ln22_2_fu_463_p2; + icmp_ln20_reg_1103 <= icmp_ln20_fu_372_p2; + lshr_ln1_reg_1164 <= {{select_ln20_fu_443_p3[4:1]}}; + lshr_ln_reg_1154 <= {{select_ln20_fu_443_p3[4:2]}}; + or_ln19_reg_1125 <= or_ln19_fu_431_p2; + p_mid113_reg_1119 <= p_mid113_fu_411_p2; + select_ln20_reg_1137 <= select_ln20_fu_443_p3; + trunc_ln32_reg_1159 <= trunc_ln32_fu_478_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1094_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln33_reg_1210 <= add_ln33_fu_771_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + empty_72_reg_1082 <= empty_72_fu_319_p2; + icmp_ln19_reg_1094 <= icmp_ln19_fu_360_p2; + icmp_ln19_reg_1094_pp0_iter1_reg <= icmp_ln19_reg_1094; + is_padding_reg_1087 <= is_padding_fu_354_p2; + lshr_ln1_reg_1164_pp0_iter1_reg <= lshr_ln1_reg_1164; + lshr_ln_reg_1154_pp0_iter1_reg <= lshr_ln_reg_1154; + or_ln19_reg_1125_pp0_iter1_reg <= or_ln19_reg_1125; + select_ln19_2_reg_1112_pp0_iter1_reg <= select_ln19_2_reg_1112; + select_ln20_1_reg_1142_pp0_iter1_reg <= select_ln20_1_reg_1142; + select_ln20_reg_1137_pp0_iter1_reg <= select_ln20_reg_1137; + trunc_ln32_reg_1159_pp0_iter1_reg <= trunc_ln32_reg_1159; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln19_reg_1094_pp0_iter2_reg <= icmp_ln19_reg_1094_pp0_iter1_reg; + icmp_ln19_reg_1094_pp0_iter3_reg <= icmp_ln19_reg_1094_pp0_iter2_reg; + lshr_ln1_reg_1164_pp0_iter2_reg <= lshr_ln1_reg_1164_pp0_iter1_reg; + lshr_ln1_reg_1164_pp0_iter3_reg <= lshr_ln1_reg_1164_pp0_iter2_reg; + select_ln19_2_reg_1112_pp0_iter2_reg <= select_ln19_2_reg_1112_pp0_iter1_reg; + select_ln20_1_reg_1142_pp0_iter2_reg <= select_ln20_1_reg_1142_pp0_iter1_reg; + select_ln20_2_reg_1189_pp0_iter2_reg <= select_ln20_2_reg_1189; + select_ln20_2_reg_1189_pp0_iter3_reg <= select_ln20_2_reg_1189_pp0_iter2_reg; + select_ln20_reg_1137_pp0_iter2_reg <= select_ln20_reg_1137_pp0_iter1_reg; + trunc_ln32_reg_1159_pp0_iter2_reg <= trunc_ln32_reg_1159_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1094_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (select_ln20_2_reg_1189_pp0_iter2_reg == 1'd0))) begin + lshr_ln32_2_reg_1230 <= lshr_ln32_2_fu_965_p2; + lshr_ln32_reg_1220 <= lshr_ln32_fu_864_p2; + sub_ln32_3_reg_1215[6 : 1] <= sub_ln32_3_fu_854_p2[6 : 1]; + sub_ln32_6_reg_1225[6 : 1] <= sub_ln32_6_fu_955_p2[6 : 1]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + or_ln23_1_reg_1067 <= or_ln23_1_fu_292_p2; + p_cast_i_reg_1043 <= p_cast_i_fu_254_p1; + p_cast_reg_1061 <= p_cast_fu_272_p2; + p_mid137_reg_1072 <= p_mid137_fu_298_p2; + sext_ln22_reg_1055 <= sext_ln22_fu_268_p1; + trunc_ln22_reg_1049 <= trunc_ln22_fu_258_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1094 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + or_ln23_5_reg_1184 <= or_ln23_5_fu_634_p2; + select_ln20_2_reg_1189 <= select_ln20_2_fu_640_p3; + sub_ln32_reg_1200[10 : 2] <= sub_ln32_fu_701_p2[10 : 2]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1094 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (or_ln19_reg_1125 == 1'd0))) begin + p_mid1_reg_1195 <= p_mid1_fu_665_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_360_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln19_2_reg_1112 <= select_ln19_2_fu_394_p3; + select_ln20_1_reg_1142 <= select_ln20_1_fu_451_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_1094 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (or_ln19_reg_1125 == 1'd1))) begin + select_ln19_7_reg_1179 <= select_ln19_7_fu_606_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_fu_360_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_1094 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_194_p4 = select_ln19_2_reg_1112; + end else begin + ap_phi_mux_ii_phi_fu_194_p4 = ii_reg_190; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_1094 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_217_p4 = select_ln20_1_reg_1142; + end else begin + ap_phi_mux_jj_phi_fu_217_p4 = jj_reg_213; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + ifmap_vec_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_1094_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + ifmap_vec_0_we0 = 1'b1; + end else begin + ifmap_vec_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + ifmap_vec_1_ce0 = 1'b1; + end else begin + ifmap_vec_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_1094_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + ifmap_vec_1_we0 = 1'b1; + end else begin + ifmap_vec_1_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln19_1_fu_304_p2 = (indvar_flatten47_reg_179 + 8'd1); + +assign add_ln19_fu_366_p2 = (ap_phi_mux_ii_phi_fu_194_p4 + 2'd1); + +assign add_ln20_1_fu_498_p2 = (indvar_flatten_reg_202 + 7'd1); + +assign add_ln20_fu_437_p2 = (select_ln19_fu_378_p3 + 2'd1); + +assign add_ln22_1_fu_329_p2 = ((sext_ln22_reg_1055) + (zext_ln20_fu_325_p1)); + +assign add_ln22_2_fu_463_p2 = ((sext_ln22_reg_1055) + (zext_ln20_1_fu_459_p1)); + +assign add_ln22_fu_262_p2 = ((j_cast_i_fu_236_p1) + (17'd131071)); + +assign add_ln25_fu_492_p2 = (select_ln20_fu_443_p3 + 6'd2); + +assign add_ln32_fu_726_p2 = ((sext_ln20_fu_713_p1) + (zext_ln32_8_fu_722_p1)); + +assign add_ln33_fu_771_p2 = ((sub_ln33_cast_fu_764_p1) + (zext_ln33_3_fu_768_p1)); + +assign and_ln32_1_fu_1022_p2 = (lshr_ln32_3_fu_1016_p2 & lshr_ln32_2_reg_1230); + +assign and_ln32_fu_980_p2 = (lshr_ln32_reg_1220 & lshr_ln32_1_fu_974_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign col_coord_int_fu_547_p3 = ((is_padding_reg_1087[0:0] == 1'b1) ? 10'd0 : empty_73_fu_542_p2); + +assign col_coord_int_mid139_fu_592_p3 = ((or_ln23_3_fu_574_p2[0:0] == 1'b1) ? 10'd0 : p_mid137_reg_1072); + +assign col_coord_int_mid1_fu_707_p3 = ((or_ln23_5_reg_1184[0:0] == 1'b1) ? 10'd0 : p_mid1_reg_1195); + +assign empty_70_fu_248_p2 = ((zext_ln19_fu_240_p1) + (17'd131071)); + +assign empty_71_fu_314_p2 = ((p_cast_i_reg_1043) + (ii_cast_i_fu_310_p1)); + +assign empty_72_fu_319_p2 = ((empty_71_fu_314_p2 > 18'd27) ? 1'b1 : 1'b0); + +assign empty_73_fu_542_p2 = ((tmp2_cast_fu_538_p1) + (trunc_ln22_reg_1049)); + +assign empty_75_fu_777_p2 = select_ln20_reg_1137_pp0_iter2_reg << 6'd4; + +assign empty_76_fu_782_p2 = (empty_75_fu_777_p2 | 6'd15); + +assign empty_77_fu_883_p2 = (tmp_9_fu_875_p3 | 6'd15); + +assign empty_fu_244_p1 = i_13[4:0]; + +assign icmp_ln19_fu_360_p2 = ((indvar_flatten47_reg_179 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_372_p2 = ((indvar_flatten_reg_202 == 7'd48) ? 1'b1 : 1'b0); + +assign icmp_ln24_1_fu_342_p2 = (((add_ln22_1_fu_329_p2) > (18'd27)) ? 1'b1 : 1'b0); + +assign icmp_ln24_2_fu_623_p2 = (((add_ln22_2_reg_1148) > (18'd27)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_286_p2 = (((add_ln22_fu_262_p2) > (17'd27)) ? 1'b1 : 1'b0); + +assign icmp_ln32_1_fu_889_p2 = ((tmp_9_fu_875_p3 > empty_77_fu_883_p2) ? 1'b1 : 1'b0); + +assign icmp_ln32_fu_788_p2 = ((empty_75_fu_777_p2 > empty_76_fu_782_p2) ? 1'b1 : 1'b0); + +assign ifmap_vec_0_address0 = sext_ln33_fu_1007_p1; + +assign ifmap_vec_0_d0 = ((select_ln20_2_reg_1189_pp0_iter3_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_fu_989_p1); + +assign ifmap_vec_1_address0 = sext_ln33_fu_1007_p1; + +assign ifmap_vec_1_d0 = ((select_ln20_2_reg_1189_pp0_iter3_reg[0:0] == 1'b1) ? 16'd0 : in_data_elem_1_fu_1031_p1); + +assign ii_cast_fu_512_p1 = ii_reg_190; + +assign ii_cast_i_fu_310_p1 = ap_phi_mux_ii_phi_fu_194_p4; + +assign ii_cast_i_mid1_fu_402_p1 = add_ln19_fu_366_p2; + +assign ii_cast_mid1_fu_554_p1 = add_ln19_reg_1098; + +assign in_data_address0 = sext_ln32_fu_739_p1; + +assign in_data_elem_1_fu_1031_p1 = trunc_ln32_2_fu_1027_p1; + +assign in_data_elem_fu_989_p1 = trunc_ln32_1_fu_985_p1; + +assign is_padding_fu_354_p2 = (or_ln23_fu_348_p2 | empty_72_fu_319_p2); + +assign j_cast_i_fu_236_p1 = j_13; + +assign lshr_ln32_1_fu_974_p2 = 64'd18446744073709551615 >> zext_ln32_12_fu_971_p1; + +assign lshr_ln32_2_fu_965_p2 = select_ln32_4_fu_939_p3 >> zext_ln32_15_fu_961_p1; + +assign lshr_ln32_3_fu_1016_p2 = 64'd18446744073709551615 >> zext_ln32_16_fu_1013_p1; + +assign lshr_ln32_fu_864_p2 = select_ln32_1_fu_838_p3 >> zext_ln32_11_fu_860_p1; + +assign or_ln19_fu_431_p2 = (xor_ln25_fu_425_p2 | icmp_ln20_fu_372_p2); + +assign or_ln23_1_fu_292_p2 = (tmp_fu_278_p3 | icmp_ln24_fu_286_p2); + +assign or_ln23_3_fu_574_p2 = (p_mid113_reg_1119 | or_ln23_1_reg_1067); + +assign or_ln23_4_fu_628_p2 = (tmp_5_fu_616_p3 | icmp_ln24_2_fu_623_p2); + +assign or_ln23_5_fu_634_p2 = (select_ln19_4_fu_569_p3 | or_ln23_4_fu_628_p2); + +assign or_ln23_fu_348_p2 = (tmp_3_fu_334_p3 | icmp_ln24_1_fu_342_p2); + +assign or_ln329_i_fu_870_p2 = (trunc_ln32_reg_1159_pp0_iter2_reg | 2'd1); + +assign p_cast14_i_fu_516_p2 = (p_cast_reg_1061 + ii_cast_fu_512_p1); + +assign p_cast14_i_mid1_fu_557_p2 = (p_cast_reg_1061 + ii_cast_mid1_fu_554_p1); + +assign p_cast_fu_272_p2 = ((empty_fu_244_p1) + (5'd31)); + +assign p_cast_i_fu_254_p1 = (empty_70_fu_248_p2); + +assign p_mid111_fu_406_p2 = ((p_cast_i_reg_1043) + (ii_cast_i_mid1_fu_402_p1)); + +assign p_mid113_fu_411_p2 = ((p_mid111_fu_406_p2 > 18'd27) ? 1'b1 : 1'b0); + +assign p_mid137_fu_298_p2 = ((trunc_ln22_fu_258_p1) + (10'd1023)); + +assign p_mid1_fu_665_p2 = ((tmp2_cast_mid1_fu_661_p1) + (trunc_ln22_reg_1049)); + +assign row_coord_int_fu_525_p3 = ((is_padding_reg_1087[0:0] == 1'b1) ? 5'd0 : p_cast14_i_fu_516_p2); + +assign row_coord_int_mid131_fu_584_p3 = ((or_ln23_3_fu_574_p2[0:0] == 1'b1) ? 5'd0 : p_cast14_i_mid1_fu_557_p2); + +assign row_coord_int_mid1_fu_647_p3 = ((or_ln23_5_fu_634_p2[0:0] == 1'b1) ? 5'd0 : select_ln19_3_fu_562_p3); + +assign select_ln19_1_fu_386_p3 = ((icmp_ln20_fu_372_p2[0:0] == 1'b1) ? 6'd0 : kk_reg_225); + +assign select_ln19_2_fu_394_p3 = ((icmp_ln20_fu_372_p2[0:0] == 1'b1) ? add_ln19_fu_366_p2 : ap_phi_mux_ii_phi_fu_194_p4); + +assign select_ln19_3_fu_562_p3 = ((icmp_ln20_reg_1103[0:0] == 1'b1) ? p_cast14_i_mid1_fu_557_p2 : p_cast14_i_fu_516_p2); + +assign select_ln19_4_fu_569_p3 = ((icmp_ln20_reg_1103[0:0] == 1'b1) ? p_mid113_reg_1119 : empty_72_reg_1082); + +assign select_ln19_5_fu_578_p3 = ((icmp_ln20_reg_1103[0:0] == 1'b1) ? or_ln23_3_fu_574_p2 : is_padding_reg_1087); + +assign select_ln19_6_fu_599_p3 = ((icmp_ln20_reg_1103[0:0] == 1'b1) ? row_coord_int_mid131_fu_584_p3 : row_coord_int_fu_525_p3); + +assign select_ln19_7_fu_606_p3 = ((icmp_ln20_reg_1103[0:0] == 1'b1) ? col_coord_int_mid139_fu_592_p3 : col_coord_int_fu_547_p3); + +assign select_ln19_fu_378_p3 = ((icmp_ln20_fu_372_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_217_p4); + +assign select_ln20_1_fu_451_p3 = ((or_ln19_fu_431_p2[0:0] == 1'b1) ? select_ln19_fu_378_p3 : add_ln20_fu_437_p2); + +assign select_ln20_2_fu_640_p3 = ((or_ln19_reg_1125[0:0] == 1'b1) ? select_ln19_5_fu_578_p3 : or_ln23_5_fu_634_p2); + +assign select_ln20_3_fu_670_p3 = ((or_ln19_reg_1125[0:0] == 1'b1) ? select_ln19_6_fu_599_p3 : row_coord_int_mid1_fu_647_p3); + +assign select_ln20_4_fu_716_p3 = ((or_ln19_reg_1125_pp0_iter1_reg[0:0] == 1'b1) ? select_ln19_7_reg_1179 : col_coord_int_mid1_fu_707_p3); + +assign select_ln20_5_fu_504_p3 = ((icmp_ln20_fu_372_p2[0:0] == 1'b1) ? 7'd1 : add_ln20_1_fu_498_p2); + +assign select_ln20_fu_443_p3 = ((or_ln19_fu_431_p2[0:0] == 1'b1) ? select_ln19_1_fu_386_p3 : 6'd0); + +assign select_ln32_1_fu_838_p3 = ((icmp_ln32_fu_788_p2[0:0] == 1'b1) ? tmp_7_fu_802_p4 : in_data_q0); + +assign select_ln32_2_fu_846_p3 = ((icmp_ln32_fu_788_p2[0:0] == 1'b1) ? xor_ln32_fu_818_p2 : zext_ln32_9_fu_794_p1); + +assign select_ln32_3_fu_931_p3 = ((icmp_ln32_1_fu_889_p2[0:0] == 1'b1) ? sub_ln32_4_fu_913_p2 : sub_ln32_5_fu_925_p2); + +assign select_ln32_4_fu_939_p3 = ((icmp_ln32_1_fu_889_p2[0:0] == 1'b1) ? tmp_10_fu_903_p4 : in_data_q0); + +assign select_ln32_5_fu_947_p3 = ((icmp_ln32_1_fu_889_p2[0:0] == 1'b1) ? xor_ln32_1_fu_919_p2 : zext_ln32_13_fu_895_p1); + +assign select_ln32_fu_830_p3 = ((icmp_ln32_fu_788_p2[0:0] == 1'b1) ? sub_ln32_1_fu_812_p2 : sub_ln32_2_fu_824_p2); + +assign sext_ln20_fu_713_p1 = (sub_ln32_reg_1200); + +assign sext_ln22_fu_268_p1 = add_ln22_fu_262_p2; + +assign sext_ln32_fu_739_p1 = (tmp_6_fu_732_p3); + +assign sext_ln33_fu_1007_p1 = (tmp_8_fu_1001_p3); + +assign sub_ln32_1_fu_812_p2 = (zext_ln32_9_fu_794_p1 - zext_ln32_10_fu_798_p1); + +assign sub_ln32_2_fu_824_p2 = (zext_ln32_10_fu_798_p1 - zext_ln32_9_fu_794_p1); + +assign sub_ln32_3_fu_854_p2 = (7'd63 - select_ln32_fu_830_p3); + +assign sub_ln32_4_fu_913_p2 = (zext_ln32_13_fu_895_p1 - zext_ln32_14_fu_899_p1); + +assign sub_ln32_5_fu_925_p2 = (zext_ln32_14_fu_899_p1 - zext_ln32_13_fu_895_p1); + +assign sub_ln32_6_fu_955_p2 = (7'd63 - select_ln32_3_fu_931_p3); + +assign sub_ln32_fu_701_p2 = (zext_ln32_fu_685_p1 - zext_ln32_7_fu_697_p1); + +assign sub_ln33_cast_fu_764_p1 = (sub_ln33_fu_758_p2); + +assign sub_ln33_fu_758_p2 = (zext_ln33_2_fu_754_p1 - zext_ln33_fu_744_p1); + +assign tmp2_cast_fu_538_p1 = (tmp2_fu_532_p2); + +assign tmp2_cast_mid1_fu_661_p1 = (tmp2_mid1_fu_655_p2); + +assign tmp2_fu_532_p2 = ((zext_ln22_fu_521_p1) + (3'd7)); + +assign tmp2_mid1_fu_655_p2 = ((zext_ln22_1_fu_613_p1) + (3'd7)); + +integer ap_tvar_int_0; + +always @ (in_data_q0) begin + //for (ap_tvar_int_0 = 64 - 1; ap_tvar_int_0 >= 0; ap_tvar_int_0 = ap_tvar_int_0 - 1) begin + for (ap_tvar_int_0 = 0; ap_tvar_int_0 < 64; ap_tvar_int_0 = ap_tvar_int_0 + 1) begin + if (ap_tvar_int_0 > 63 - 0) begin + tmp_10_fu_903_p4[ap_tvar_int_0] = 1'b0; + end else begin + tmp_10_fu_903_p4[ap_tvar_int_0] = in_data_q0[63 - ap_tvar_int_0]; + end + end +end + +assign tmp_1_fu_677_p3 = {{select_ln20_3_fu_670_p3}, {5'd0}}; + +assign tmp_2_fu_689_p3 = {{select_ln20_3_fu_670_p3}, {2'd0}}; + +assign tmp_3_fu_334_p3 = add_ln22_1_fu_329_p2[32'd17]; + +assign tmp_4_fu_417_p3 = kk_reg_225[32'd5]; + +assign tmp_5_fu_616_p3 = add_ln22_2_reg_1148[32'd17]; + +assign tmp_6_fu_732_p3 = {{add_ln32_fu_726_p2}, {lshr_ln_reg_1154_pp0_iter1_reg}}; + +integer ap_tvar_int_1; + +always @ (in_data_q0) begin + //for (ap_tvar_int_1 = 64 - 1; ap_tvar_int_1 >= 0; ap_tvar_int_1 = ap_tvar_int_1 - 1) begin + for (ap_tvar_int_1 = 0; ap_tvar_int_1 < 64; ap_tvar_int_1 = ap_tvar_int_1 + 1) begin + if (ap_tvar_int_1 > 63 - 0) begin + tmp_7_fu_802_p4[ap_tvar_int_1] = 1'b0; + end else begin + tmp_7_fu_802_p4[ap_tvar_int_1] = in_data_q0[63 - ap_tvar_int_1]; + end + end +end + +assign tmp_8_fu_1001_p3 = {{add_ln33_reg_1210}, {lshr_ln1_reg_1164_pp0_iter3_reg}}; + +assign tmp_9_fu_875_p3 = {{or_ln329_i_fu_870_p2}, {4'd0}}; + +assign tmp_fu_278_p3 = add_ln22_fu_262_p2[32'd16]; + +assign tmp_s_fu_747_p3 = {{select_ln19_2_reg_1112_pp0_iter2_reg}, {2'd0}}; + +assign trunc_ln22_fu_258_p1 = j_13[9:0]; + +assign trunc_ln32_1_fu_985_p1 = and_ln32_fu_980_p2[15:0]; + +assign trunc_ln32_2_fu_1027_p1 = and_ln32_1_fu_1022_p2[15:0]; + +assign trunc_ln32_fu_478_p1 = select_ln20_fu_443_p3[1:0]; + +assign xor_ln25_fu_425_p2 = (tmp_4_fu_417_p3 ^ 1'd1); + +assign xor_ln32_1_fu_919_p2 = (zext_ln32_13_fu_895_p1 ^ 7'd63); + +assign xor_ln32_fu_818_p2 = (zext_ln32_9_fu_794_p1 ^ 7'd63); + +assign zext_ln19_fu_240_p1 = i_13; + +assign zext_ln20_1_fu_459_p1 = add_ln20_fu_437_p2; + +assign zext_ln20_fu_325_p1 = ap_phi_mux_jj_phi_fu_217_p4; + +assign zext_ln22_1_fu_613_p1 = add_ln20_reg_1132; + +assign zext_ln22_fu_521_p1 = jj_reg_213; + +assign zext_ln32_10_fu_798_p1 = empty_76_fu_782_p2; + +assign zext_ln32_11_fu_860_p1 = select_ln32_2_fu_846_p3; + +assign zext_ln32_12_fu_971_p1 = sub_ln32_3_reg_1215; + +assign zext_ln32_13_fu_895_p1 = tmp_9_fu_875_p3; + +assign zext_ln32_14_fu_899_p1 = empty_77_fu_883_p2; + +assign zext_ln32_15_fu_961_p1 = select_ln32_5_fu_947_p3; + +assign zext_ln32_16_fu_1013_p1 = sub_ln32_6_reg_1225; + +assign zext_ln32_7_fu_697_p1 = tmp_2_fu_689_p3; + +assign zext_ln32_8_fu_722_p1 = select_ln20_4_fu_716_p3; + +assign zext_ln32_9_fu_794_p1 = empty_75_fu_777_p2; + +assign zext_ln32_fu_685_p1 = tmp_1_fu_677_p3; + +assign zext_ln33_2_fu_754_p1 = tmp_s_fu_747_p3; + +assign zext_ln33_3_fu_768_p1 = select_ln20_1_reg_1142_pp0_iter2_reg; + +assign zext_ln33_fu_744_p1 = select_ln19_2_reg_1112_pp0_iter2_reg; + +always @ (posedge ap_clk) begin + sub_ln32_reg_1200[1:0] <= 2'b00; + sub_ln32_3_reg_1215[0] <= 1'b0; + sub_ln32_6_reg_1225[0] <= 1'b0; +end + +endmodule //td_fused_top_tdf8_readInputs59 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_writeOutputs_aligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_idle, + ap_ready, + i, + j, + k, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1, + max_vals_0, + max_vals_1, + max_vals_2, + max_vals +); + +parameter ap_ST_fsm_state1 = 2'd1; +parameter ap_ST_fsm_state2 = 2'd2; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +input [3:0] i; +input [7:0] j; +input [7:0] k; +output [13:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; +input [15:0] max_vals_0; +input [15:0] max_vals_1; +input [15:0] max_vals_2; +input [15:0] max_vals; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg out_data_ce1; +reg out_data_we1; + + reg [1:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [7:0] add_ln123_fu_105_p2; +reg [7:0] add_ln123_reg_178; +wire [63:0] zext_ln123_2_fu_132_p1; +wire ap_CS_fsm_state2; +wire [4:0] tmp_8_fu_87_p3; +wire [7:0] tmp_fu_79_p3; +wire [7:0] zext_ln123_fu_95_p1; +wire [7:0] sub_ln123_fu_99_p2; +wire [13:0] tmp_10_cast_fu_111_p3; +wire [13:0] zext_ln123_1_fu_122_p1; +wire [13:0] add_ln123_1_fu_126_p2; +wire [15:0] bitcast_ln123_3_fu_161_p1; +wire [15:0] bitcast_ln123_2_fu_153_p1; +wire [15:0] bitcast_ln123_1_fu_145_p1; +wire [15:0] bitcast_ln123_fu_137_p1; +reg [1:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 2'd1; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + add_ln123_reg_178 <= add_ln123_fu_105_p2; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln123_1_fu_126_p2 = (tmp_10_cast_fu_111_p3 + zext_ln123_1_fu_122_p1); + +assign add_ln123_fu_105_p2 = (sub_ln123_fu_99_p2 + j); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign bitcast_ln123_1_fu_145_p1 = max_vals_1; + +assign bitcast_ln123_2_fu_153_p1 = max_vals_2; + +assign bitcast_ln123_3_fu_161_p1 = max_vals; + +assign bitcast_ln123_fu_137_p1 = max_vals_0; + +assign out_data_address1 = zext_ln123_2_fu_132_p1; + +assign out_data_d1 = {{{{bitcast_ln123_3_fu_161_p1}, {bitcast_ln123_2_fu_153_p1}}, {bitcast_ln123_1_fu_145_p1}}, {bitcast_ln123_fu_137_p1}}; + +assign sub_ln123_fu_99_p2 = (tmp_fu_79_p3 - zext_ln123_fu_95_p1); + +assign tmp_10_cast_fu_111_p3 = {{add_ln123_reg_178}, {6'd0}}; + +assign tmp_8_fu_87_p3 = {{i}, {1'd0}}; + +assign tmp_fu_79_p3 = {{i}, {4'd0}}; + +assign zext_ln123_1_fu_122_p1 = k; + +assign zext_ln123_2_fu_132_p1 = add_ln123_1_fu_126_p2; + +assign zext_ln123_fu_95_p1 = tmp_8_fu_87_p3; + +endmodule //td_fused_top_tdf8_writeOutputs_aligned +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_16 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [13:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [13:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [11:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [11:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [13:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [13:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [5:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [5:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [13:0] dataflow_in_loop_TOP_LOOP48462_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP48462_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48462_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP48462_U0_in_data_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP48462_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP48462_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48462_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP48462_U0_in_data_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP48462_U0_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP48462_U0_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP48462_U0_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP48462_U0_filter_data_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP48462_U0_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP48462_U0_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP48462_U0_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP48462_U0_filter_data_we1; +wire [5:0] dataflow_in_loop_TOP_LOOP48462_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP48462_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP48462_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP48462_U0_adjustments_we0; +wire [5:0] dataflow_in_loop_TOP_LOOP48462_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP48462_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP48462_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP48462_U0_adjustments_we1; +wire [11:0] dataflow_in_loop_TOP_LOOP48462_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP48462_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP48462_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP48462_U0_out_data_we0; +wire [11:0] dataflow_in_loop_TOP_LOOP48462_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP48462_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP48462_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP48462_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP48462_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP48462_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP48462_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP48462_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP48462_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP48462_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP48462_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP48462_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP48462_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [13:0] loop_dataflow_input_count; +reg [13:0] loop_dataflow_output_count; +wire [13:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP48462_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP48462_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 14'd0; +#0 loop_dataflow_output_count = 14'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP48462 dataflow_in_loop_TOP_LOOP48462_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP48462_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP48462_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP48462_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP48462_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP48462_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP48462_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP48462_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP48462_U0_in_data_we1), + .filter_data_address0(dataflow_in_loop_TOP_LOOP48462_U0_filter_data_address0), + .filter_data_ce0(dataflow_in_loop_TOP_LOOP48462_U0_filter_data_ce0), + .filter_data_d0(dataflow_in_loop_TOP_LOOP48462_U0_filter_data_d0), + .filter_data_q0(filter_data_q0), + .filter_data_we0(dataflow_in_loop_TOP_LOOP48462_U0_filter_data_we0), + .filter_data_address1(dataflow_in_loop_TOP_LOOP48462_U0_filter_data_address1), + .filter_data_ce1(dataflow_in_loop_TOP_LOOP48462_U0_filter_data_ce1), + .filter_data_d1(dataflow_in_loop_TOP_LOOP48462_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(dataflow_in_loop_TOP_LOOP48462_U0_filter_data_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP48462_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP48462_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP48462_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP48462_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP48462_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP48462_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP48462_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP48462_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP48462_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP48462_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP48462_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP48462_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP48462_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP48462_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP48462_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP48462_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP48462_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP48462_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP48462_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP48462_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP48462_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP48462_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP48462_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 14'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48462_U0_ap_ready == 1'b1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 14'd1); + end else if (((dataflow_in_loop_TOP_LOOP48462_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= 14'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 14'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP48462_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP48462_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 14'd1); + end else if (((dataflow_in_loop_TOP_LOOP48462_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP48462_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + loop_dataflow_output_count <= 14'd0; + end + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP48462_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP48462_U0_ap_idle == 1'b1) & (loop_dataflow_output_count == 14'd0) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP48462_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP48462_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP48462_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP48462_U0_adjustments_address0; + +assign adjustments_address1 = 6'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP48462_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP48462_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP48462_U0_ap_ready; + +assign bound_minus_1 = (14'd12544 - 14'd1); + +assign dataflow_in_loop_TOP_LOOP48462_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP48462_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP48462_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP48462_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP48462_U0_start_write = 1'b0; + +assign filter_data_address0 = dataflow_in_loop_TOP_LOOP48462_U0_filter_data_address0; + +assign filter_data_address1 = 14'd0; + +assign filter_data_ce0 = dataflow_in_loop_TOP_LOOP48462_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP48462_U0_in_data_address0; + +assign in_data_address1 = 14'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP48462_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP48462_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 12'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP48462_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP48462_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP48462_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP48462_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP48462_U0_out_data_write; + +endmodule //td_fused_top_tdf9_16 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_pp0_stage0 = 11'd2; +parameter ap_ST_fsm_pp0_stage1 = 11'd4; +parameter ap_ST_fsm_pp0_stage2 = 11'd8; +parameter ap_ST_fsm_pp0_stage3 = 11'd16; +parameter ap_ST_fsm_pp0_stage4 = 11'd32; +parameter ap_ST_fsm_pp0_stage5 = 11'd64; +parameter ap_ST_fsm_pp0_stage6 = 11'd128; +parameter ap_ST_fsm_state15 = 11'd256; +parameter ap_ST_fsm_state16 = 11'd512; +parameter ap_ST_fsm_state17 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [7:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [7:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[7:0] accum_in_0_address0; +reg accum_in_0_ce0; +reg[7:0] accum_in_0_address1; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [8:0] x_reg_170; +reg [15:0] psum_7_08_reg_182; +reg [15:0] psum_6_07_reg_194; +reg [15:0] psum_5_06_reg_206; +reg [15:0] psum_4_05_reg_218; +reg [15:0] psum_3_04_reg_230; +reg [15:0] psum_2_03_reg_242; +reg [15:0] psum_1_02_reg_254; +reg [15:0] psum_0_01_reg_266; +wire [0:0] tmp_fu_323_p3; +reg [0:0] tmp_reg_494; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state9_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +reg [0:0] tmp_reg_494_pp0_iter1_reg; +wire [7:0] trunc_ln25_fu_336_p1; +reg [7:0] trunc_ln25_reg_498; +reg [15:0] accum_in_0_load_reg_518; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state10_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_0_load_1_reg_523; +reg [15:0] accum_in_0_load_2_reg_538; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state11_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_0_load_3_reg_543; +reg [15:0] accum_in_0_load_4_reg_558; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state12_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_0_load_5_reg_563; +reg [15:0] accum_in_0_load_6_reg_578; +wire ap_CS_fsm_pp0_stage4; +wire ap_block_state6_pp0_stage4_iter0; +wire ap_block_state13_pp0_stage4_iter1; +wire ap_block_pp0_stage4_11001; +reg [15:0] accum_in_0_load_7_reg_583; +wire [8:0] add_ln25_fu_411_p2; +reg [8:0] add_ln25_reg_588; +wire ap_CS_fsm_pp0_stage6; +wire ap_block_state8_pp0_stage6_iter0; +wire ap_block_pp0_stage6_11001; +wire [15:0] grp_fu_307_p2; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_312_p2; +wire ap_CS_fsm_pp0_stage5; +wire ap_block_state7_pp0_stage5_iter0; +wire ap_block_state14_pp0_stage5_iter1; +wire ap_block_pp0_stage5_11001; +wire [3:0] add_ln33_fu_434_p2; +wire ap_CS_fsm_state16; +wire [0:0] tmp_2_fu_417_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage6_subdone; +wire ap_block_pp0_stage5_subdone; +reg [8:0] ap_phi_mux_x_phi_fu_174_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_186_p4; +wire ap_block_pp0_stage5; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_198_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_210_p4; +wire ap_block_pp0_stage4; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_222_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_234_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_03_phi_fu_246_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_278; +wire ap_CS_fsm_state15; +reg [15:0] ap_phi_mux_phi_ln45_phi_fu_292_p8; +wire [2:0] trunc_ln33_fu_430_p1; +wire [63:0] zext_ln25_fu_331_p1; +wire [63:0] zext_ln29_fu_346_p1; +wire [63:0] zext_ln29_1_fu_356_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln29_2_fu_366_p1; +wire [63:0] zext_ln29_3_fu_376_p1; +wire [63:0] zext_ln29_4_fu_386_p1; +wire [63:0] zext_ln29_5_fu_396_p1; +wire [63:0] zext_ln29_6_fu_406_p1; +wire [63:0] zext_ln33_fu_425_p1; +wire [63:0] zext_ln33_1_fu_446_p1; +reg [15:0] grp_fu_307_p0; +reg [15:0] grp_fu_307_p1; +reg [15:0] grp_fu_312_p0; +reg [15:0] grp_fu_312_p1; +wire [7:0] or_ln29_fu_340_p2; +wire [7:0] or_ln29_1_fu_351_p2; +wire [7:0] or_ln29_2_fu_361_p2; +wire [7:0] or_ln29_3_fu_371_p2; +wire [7:0] or_ln29_4_fu_381_p2; +wire [7:0] or_ln29_5_fu_391_p2; +wire [7:0] or_ln29_6_fu_401_p2; +wire ap_block_pp0_stage6; +wire [2:0] or_ln33_fu_440_p2; +wire [0:0] icmp_ln45_fu_451_p2; +wire [0:0] icmp_ln45_1_fu_465_p2; +wire [15:0] select_ln45_fu_457_p3; +wire [0:0] icmp_ln45_2_fu_479_p2; +wire [15:0] select_ln45_1_fu_471_p3; +wire ap_CS_fsm_state17; +reg [10:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +wire ap_block_pp0_stage1_subdone; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage4_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_570; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1336( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_307_p0), + .din1(grp_fu_307_p1), + .dout(grp_fu_307_p2) +); + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1337( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_312_p0), + .din1(grp_fu_312_p1), + .dout(grp_fu_312_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage5_subdone) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0)) | ((1'b0 == ap_block_pp0_stage6_subdone) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state15)) begin + q_reg_278 <= 4'd0; + end else if (((tmp_2_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + q_reg_278 <= add_ln33_fu_434_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_reg_494 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + x_reg_170 <= add_ln25_reg_588; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_170 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_1_reg_523 <= accum_in_0_q0; + accum_in_0_load_reg_518 <= accum_in_0_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage2_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_2_reg_538 <= accum_in_0_q1; + accum_in_0_load_3_reg_543 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage3_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_4_reg_558 <= accum_in_0_q1; + accum_in_0_load_5_reg_563 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage4_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_6_reg_578 <= accum_in_0_q1; + accum_in_0_load_7_reg_583 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage6_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln25_reg_588 <= add_ln25_fu_411_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage2_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + psum_0_01_reg_266 <= grp_fu_307_p2; + psum_1_02_reg_254 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + psum_2_03_reg_242 <= grp_fu_307_p2; + psum_3_04_reg_230 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage4_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + psum_4_05_reg_218 <= grp_fu_307_p2; + psum_5_06_reg_206 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage5_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + psum_6_07_reg_194 <= grp_fu_307_p2; + psum_7_08_reg_182 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + tmp_reg_494 <= ap_phi_mux_x_phi_fu_174_p4[32'd8]; + tmp_reg_494_pp0_iter1_reg <= tmp_reg_494; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_fu_323_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln25_reg_498 <= trunc_ln25_fu_336_p1; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address0 = zext_ln29_6_fu_406_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address0 = zext_ln29_4_fu_386_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address0 = zext_ln29_2_fu_366_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address0 = zext_ln29_fu_346_p1; + end else begin + accum_in_0_address0 = 'bx; + end + end else begin + accum_in_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address1 = zext_ln29_5_fu_396_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address1 = zext_ln29_3_fu_376_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address1 = zext_ln29_1_fu_356_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address1 = zext_ln25_fu_331_p1; + end else begin + accum_in_0_address1 = 'bx; + end + end else begin + accum_in_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state16)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_2_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_2_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_reg_494 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_2_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + if ((trunc_ln33_fu_430_p1 == 3'd0)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_0_01_reg_266; + end else if ((1'b1 == ap_condition_570)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_6_07_reg_194; + end else if ((trunc_ln33_fu_430_p1 == 3'd4)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_4_05_reg_218; + end else if ((trunc_ln33_fu_430_p1 == 3'd2)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_2_03_reg_242; + end else begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (tmp_reg_494 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_x_phi_fu_174_p4 = add_ln25_reg_588; + end else begin + ap_phi_mux_x_phi_fu_174_p4 = x_reg_170; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_307_p0 = ap_phi_mux_psum_6_07_phi_fu_198_p4; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_307_p0 = ap_phi_mux_psum_4_05_phi_fu_222_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_307_p0 = ap_phi_mux_psum_2_03_phi_fu_246_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_307_p0 = grp_fu_307_p2; + end else begin + grp_fu_307_p0 = 'bx; + end + end else begin + grp_fu_307_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_307_p1 = accum_in_0_load_6_reg_578; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_307_p1 = accum_in_0_load_4_reg_558; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_307_p1 = accum_in_0_load_2_reg_538; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_307_p1 = accum_in_0_load_reg_518; + end else begin + grp_fu_307_p1 = 'bx; + end + end else begin + grp_fu_307_p1 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_312_p0 = ap_phi_mux_psum_7_08_phi_fu_186_p4; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_312_p0 = ap_phi_mux_psum_5_06_phi_fu_210_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_312_p0 = ap_phi_mux_psum_3_04_phi_fu_234_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_312_p0 = grp_fu_312_p2; + end else begin + grp_fu_312_p0 = 'bx; + end + end else begin + grp_fu_312_p0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage5) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin + grp_fu_312_p1 = accum_in_0_load_7_reg_583; + end else if (((1'b0 == ap_block_pp0_stage4) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin + grp_fu_312_p1 = accum_in_0_load_5_reg_563; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_312_p1 = accum_in_0_load_3_reg_543; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_312_p1 = accum_in_0_load_1_reg_523; + end else begin + grp_fu_312_p1 = 'bx; + end + end else begin + grp_fu_312_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_494 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_494 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state15; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_pp0_stage4 : begin + if ((1'b0 == ap_block_pp0_stage4_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage4; + end + end + ap_ST_fsm_pp0_stage5 : begin + if ((~((1'b0 == ap_block_pp0_stage5_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0)) & (1'b0 == ap_block_pp0_stage5_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end else if (((1'b0 == ap_block_pp0_stage5_subdone) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state15; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage5; + end + end + ap_ST_fsm_pp0_stage6 : begin + if ((1'b0 == ap_block_pp0_stage6_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage6; + end + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + if (((tmp_2_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state16))) begin + ap_NS_fsm = ap_ST_fsm_state16; + end else begin + ap_NS_fsm = ap_ST_fsm_state17; + end + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln33_1_fu_446_p1; + +assign accum_out_address1 = zext_ln33_fu_425_p1; + +assign accum_out_d0 = ((icmp_ln45_2_fu_479_p2[0:0] == 1'b1) ? psum_5_06_reg_206 : select_ln45_1_fu_471_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln45_phi_fu_292_p8; + +assign add_ln25_fu_411_p2 = (x_reg_170 + 9'd8); + +assign add_ln33_fu_434_p2 = (q_reg_278 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state15 = ap_CS_fsm[32'd8]; + +assign ap_CS_fsm_state16 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd10]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage4_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage5_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage6_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage4_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage5_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_570 = (~(trunc_ln33_fu_430_p1 == 3'd0) & ~(trunc_ln33_fu_430_p1 == 3'd4) & ~(trunc_ln33_fu_430_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_03_phi_fu_246_p4 = grp_fu_307_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_234_p4 = grp_fu_312_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_222_p4 = grp_fu_307_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_210_p4 = grp_fu_312_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_198_p4 = grp_fu_307_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_186_p4 = grp_fu_312_p2; + +assign icmp_ln45_1_fu_465_p2 = ((or_ln33_fu_440_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln45_2_fu_479_p2 = ((or_ln33_fu_440_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln45_fu_451_p2 = ((or_ln33_fu_440_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln29_1_fu_351_p2 = (trunc_ln25_reg_498 | 8'd2); + +assign or_ln29_2_fu_361_p2 = (trunc_ln25_reg_498 | 8'd3); + +assign or_ln29_3_fu_371_p2 = (trunc_ln25_reg_498 | 8'd4); + +assign or_ln29_4_fu_381_p2 = (trunc_ln25_reg_498 | 8'd5); + +assign or_ln29_5_fu_391_p2 = (trunc_ln25_reg_498 | 8'd6); + +assign or_ln29_6_fu_401_p2 = (trunc_ln25_reg_498 | 8'd7); + +assign or_ln29_fu_340_p2 = (trunc_ln25_fu_336_p1 | 8'd1); + +assign or_ln33_fu_440_p2 = (trunc_ln33_fu_430_p1 | 3'd1); + +assign select_ln45_1_fu_471_p3 = ((icmp_ln45_1_fu_465_p2[0:0] == 1'b1) ? psum_3_04_reg_230 : select_ln45_fu_457_p3); + +assign select_ln45_fu_457_p3 = ((icmp_ln45_fu_451_p2[0:0] == 1'b1) ? psum_1_02_reg_254 : psum_7_08_reg_182); + +assign tmp_2_fu_417_p3 = q_reg_278[32'd3]; + +assign tmp_fu_323_p3 = ap_phi_mux_x_phi_fu_174_p4[32'd8]; + +assign trunc_ln25_fu_336_p1 = ap_phi_mux_x_phi_fu_174_p4[7:0]; + +assign trunc_ln33_fu_430_p1 = q_reg_278[2:0]; + +assign zext_ln25_fu_331_p1 = ap_phi_mux_x_phi_fu_174_p4; + +assign zext_ln29_1_fu_356_p1 = or_ln29_1_fu_351_p2; + +assign zext_ln29_2_fu_366_p1 = or_ln29_2_fu_361_p2; + +assign zext_ln29_3_fu_376_p1 = or_ln29_3_fu_371_p2; + +assign zext_ln29_4_fu_386_p1 = or_ln29_4_fu_381_p2; + +assign zext_ln29_5_fu_396_p1 = or_ln29_5_fu_391_p2; + +assign zext_ln29_6_fu_406_p1 = or_ln29_6_fu_401_p2; + +assign zext_ln29_fu_346_p1 = or_ln29_fu_340_p2; + +assign zext_ln33_1_fu_446_p1 = or_ln33_fu_440_p2; + +assign zext_ln33_fu_425_p1 = q_reg_278; + +endmodule //td_fused_top_tdf9_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_2, + accum_in_2_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 11'd1; +parameter ap_ST_fsm_state2 = 11'd2; +parameter ap_ST_fsm_state3 = 11'd4; +parameter ap_ST_fsm_state4 = 11'd8; +parameter ap_ST_fsm_state5 = 11'd16; +parameter ap_ST_fsm_state6 = 11'd32; +parameter ap_ST_fsm_state7 = 11'd64; +parameter ap_ST_fsm_state8 = 11'd128; +parameter ap_ST_fsm_state9 = 11'd256; +parameter ap_ST_fsm_state10 = 11'd512; +parameter ap_ST_fsm_state11 = 11'd1024; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_2; +output accum_in_2_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_2; +reg accum_in_2_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [10:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln57_fu_73_p2; +reg [3:0] add_ln57_reg_90; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln57_fu_84_p2; +reg [15:0] accum_in_load_reg_103; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state11; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_reg_55; +wire [63:0] zext_ln57_fu_79_p1; +reg [15:0] accum_in_2_preg; +wire ap_CS_fsm_state4; +reg [10:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 11'd1; +#0 accum_in_2_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1340( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_reg_55), + .din1(accum_in_load_reg_103), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_2_preg <= 16'd0; + end else begin + if (((icmp_ln57_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_2_preg <= sum_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln57_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + i_1_1_reg_44 <= add_ln57_reg_90; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + sum_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + accum_in_load_reg_103 <= accum_in_q0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln57_reg_90 <= add_ln57_fu_73_p2; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_2 = sum_reg_55; + end else begin + accum_in_2 = accum_in_2_preg; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_2_ap_vld = 1'b1; + end else begin + accum_in_2_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln57_fu_84_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln57_fu_79_p1; + +assign add_ln57_fu_73_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln57_fu_84_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln57_fu_79_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf9_accum_2 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf9_adjustments_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 48; +parameter AWIDTH = 6; +parameter MEM_SIZE = 64; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf9_adjustments( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd48; +parameter AddressRange = 32'd64; +parameter AddressWidth = 32'd6; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf9_adjustments_ram td_fused_top_tdf9_adjustments_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 23'd1; +parameter ap_ST_fsm_state2 = 23'd2; +parameter ap_ST_fsm_state3 = 23'd4; +parameter ap_ST_fsm_state4 = 23'd8; +parameter ap_ST_fsm_state5 = 23'd16; +parameter ap_ST_fsm_state6 = 23'd32; +parameter ap_ST_fsm_state7 = 23'd64; +parameter ap_ST_fsm_state8 = 23'd128; +parameter ap_ST_fsm_state9 = 23'd256; +parameter ap_ST_fsm_state10 = 23'd512; +parameter ap_ST_fsm_state11 = 23'd1024; +parameter ap_ST_fsm_state12 = 23'd2048; +parameter ap_ST_fsm_state13 = 23'd4096; +parameter ap_ST_fsm_state14 = 23'd8192; +parameter ap_ST_fsm_state15 = 23'd16384; +parameter ap_ST_fsm_state16 = 23'd32768; +parameter ap_ST_fsm_state17 = 23'd65536; +parameter ap_ST_fsm_state18 = 23'd131072; +parameter ap_ST_fsm_state19 = 23'd262144; +parameter ap_ST_fsm_state20 = 23'd524288; +parameter ap_ST_fsm_state21 = 23'd1048576; +parameter ap_ST_fsm_state22 = 23'd2097152; +parameter ap_ST_fsm_state23 = 23'd4194304; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_read; +output [5:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [5:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg indices_23_read; + +reg ap_done_reg; + reg [22:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +wire [15:0] trunc_ln220_fu_95_p1; +reg [15:0] trunc_ln220_reg_154; +wire ap_CS_fsm_state2; +reg [15:0] tmp_7_i_i_reg_159; +reg [15:0] tmp_8_i_i_reg_164; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_81_p2; +reg [15:0] sub_i_i_i_reg_179; +wire ap_CS_fsm_state9; +wire ap_CS_fsm_state10; +wire [15:0] grp_fu_86_p2; +reg [15:0] mul_i_i_i_reg_189; +wire ap_CS_fsm_state14; +wire ap_CS_fsm_state15; +wire [15:0] grp_fu_77_p2; +reg [15:0] add_i_i_i_reg_199; +wire ap_CS_fsm_state22; +wire [63:0] zext_ln220_fu_90_p1; +reg ap_block_state1; +wire [15:0] grp_fu_77_p1; +wire [15:0] grp_fu_81_p1; +wire [15:0] grp_fu_86_p1; +wire ap_CS_fsm_state23; +wire [15:0] bitcast_ln648_fu_131_p1; +wire [0:0] tmp_fu_134_p3; +reg [22:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 23'd1; +end + +td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 8 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_8_full_dsp_1_U1344( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(mul_i_i_i_reg_189), + .din1(grp_fu_77_p1), + .dout(grp_fu_77_p2) +); + +td_fused_top_hsub_16ns_16ns_16_7_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 7 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_7_full_dsp_1_U1345( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sums_read), + .din1(grp_fu_81_p1), + .dout(grp_fu_81_p2) +); + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1346( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_179), + .din1(grp_fu_86_p1), + .dout(grp_fu_86_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state23)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state22)) begin + add_i_i_i_reg_199 <= grp_fu_77_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + mul_i_i_i_reg_189 <= grp_fu_86_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + sub_i_i_i_reg_179 <= grp_fu_81_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + tmp_7_i_i_reg_159 <= {{adjustments_q0[31:16]}}; + tmp_8_i_i_reg_164 <= {{adjustments_q0[47:32]}}; + trunc_ln220_reg_154 <= trunc_ln220_fu_95_p1; + end +end + +always @ (*) begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state23)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state23)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state18; + end + ap_ST_fsm_state18 : begin + ap_NS_fsm = ap_ST_fsm_state19; + end + ap_ST_fsm_state19 : begin + ap_NS_fsm = ap_ST_fsm_state20; + end + ap_ST_fsm_state20 : begin + ap_NS_fsm = ap_ST_fsm_state21; + end + ap_ST_fsm_state21 : begin + ap_NS_fsm = ap_ST_fsm_state22; + end + ap_ST_fsm_state22 : begin + ap_NS_fsm = ap_ST_fsm_state23; + end + ap_ST_fsm_state23 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign adjustments_address0 = zext_ln220_fu_90_p1; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd9]; + +assign ap_CS_fsm_state14 = ap_CS_fsm[32'd13]; + +assign ap_CS_fsm_state15 = ap_CS_fsm[32'd14]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state22 = ap_CS_fsm[32'd21]; + +assign ap_CS_fsm_state23 = ap_CS_fsm[32'd22]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_return = ((tmp_fu_134_p3[0:0] == 1'b1) ? 16'd0 : add_i_i_i_reg_199); + +assign bitcast_ln648_fu_131_p1 = add_i_i_i_reg_199; + +assign grp_fu_77_p1 = tmp_8_i_i_reg_164; + +assign grp_fu_81_p1 = trunc_ln220_reg_154; + +assign grp_fu_86_p1 = tmp_7_i_i_reg_159; + +assign tmp_fu_134_p3 = bitcast_ln648_fu_131_p1[32'd15]; + +assign trunc_ln220_fu_95_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_90_p1 = indices_23_dout; + +endmodule //td_fused_top_tdf9_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_q0, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [7:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +input [15:0] ifmap_vec_0_0_q0; +output [7:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +input [15:0] weight_vecs_0_0_0_q0; +output [7:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_0_0_ce0; +reg weight_vecs_0_0_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [8:0] ic_0_0_reg_69; +wire [8:0] add_ln149_fu_84_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln149_fu_90_p2; +reg [0:0] icmp_ln149_reg_107; +reg [0:0] icmp_ln149_reg_107_pp0_iter1_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter2_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter3_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter4_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter5_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter6_reg; +wire [63:0] idxprom17_0_0_fu_96_p1; +reg [63:0] idxprom17_0_0_reg_111; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter1_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter2_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter3_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter4_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter5_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter6_reg; +reg [15:0] ifmap_vec_0_0_load_reg_126; +reg [15:0] weight_vecs_0_0_0_load_reg_131; +wire [15:0] grp_fu_80_p2; +reg [15:0] mul_reg_136; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +wire ap_block_pp0_stage0; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_5_max_dsp_1_U1332( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_0_load_reg_126), + .din1(weight_vecs_0_0_0_load_reg_131), + .dout(grp_fu_80_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b1 == 1'b1)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_fu_90_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_0_0_reg_69 <= add_ln149_fu_84_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_0_0_reg_69 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln149_reg_107 <= icmp_ln149_fu_90_p2; + icmp_ln149_reg_107_pp0_iter1_reg <= icmp_ln149_reg_107; + idxprom17_0_0_reg_111_pp0_iter1_reg[8 : 0] <= idxprom17_0_0_reg_111[8 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln149_reg_107_pp0_iter2_reg <= icmp_ln149_reg_107_pp0_iter1_reg; + icmp_ln149_reg_107_pp0_iter3_reg <= icmp_ln149_reg_107_pp0_iter2_reg; + icmp_ln149_reg_107_pp0_iter4_reg <= icmp_ln149_reg_107_pp0_iter3_reg; + icmp_ln149_reg_107_pp0_iter5_reg <= icmp_ln149_reg_107_pp0_iter4_reg; + icmp_ln149_reg_107_pp0_iter6_reg <= icmp_ln149_reg_107_pp0_iter5_reg; + idxprom17_0_0_reg_111_pp0_iter2_reg[8 : 0] <= idxprom17_0_0_reg_111_pp0_iter1_reg[8 : 0]; + idxprom17_0_0_reg_111_pp0_iter3_reg[8 : 0] <= idxprom17_0_0_reg_111_pp0_iter2_reg[8 : 0]; + idxprom17_0_0_reg_111_pp0_iter4_reg[8 : 0] <= idxprom17_0_0_reg_111_pp0_iter3_reg[8 : 0]; + idxprom17_0_0_reg_111_pp0_iter5_reg[8 : 0] <= idxprom17_0_0_reg_111_pp0_iter4_reg[8 : 0]; + idxprom17_0_0_reg_111_pp0_iter6_reg[8 : 0] <= idxprom17_0_0_reg_111_pp0_iter5_reg[8 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_fu_90_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + idxprom17_0_0_reg_111[8 : 0] <= idxprom17_0_0_fu_96_p1[8 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_reg_107 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_load_reg_126 <= ifmap_vec_0_0_q0; + weight_vecs_0_0_0_load_reg_131 <= weight_vecs_0_0_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_reg_107_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_reg_136 <= grp_fu_80_p2; + end +end + +always @ (*) begin + if ((icmp_ln149_fu_90_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln149_reg_107_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln149_fu_90_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln149_fu_90_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln149_fu_84_p2 = (ic_0_0_reg_69 + 9'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign icmp_ln149_fu_90_p2 = ((ic_0_0_reg_69 == 9'd256) ? 1'b1 : 1'b0); + +assign idxprom17_0_0_fu_96_p1 = ic_0_0_reg_69; + +assign ifmap_vec_0_0_address0 = idxprom17_0_0_fu_96_p1; + +assign products_0_address0 = idxprom17_0_0_reg_111_pp0_iter6_reg; + +assign products_0_d0 = mul_reg_136; + +assign weight_vecs_0_0_0_address0 = idxprom17_0_0_fu_96_p1; + +always @ (posedge ap_clk) begin + idxprom17_0_0_reg_111[63:9] <= 55'b0000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter1_reg[63:9] <= 55'b0000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter2_reg[63:9] <= 55'b0000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter3_reg[63:9] <= 55'b0000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter4_reg[63:9] <= 55'b0000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter5_reg[63:9] <= 55'b0000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter6_reg[63:9] <= 55'b0000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf9_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf9_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 14; +parameter MEM_SIZE = 16384; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf9_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd16384; +parameter AddressWidth = 32'd14; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf9_filters_ram td_fused_top_tdf9_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + indices_2_out_din, + indices_2_out_full_n, + indices_2_out_write, + indices_2_out1_din, + indices_2_out1_full_n, + indices_2_out1_write +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [5:0] indices_2_out_din; +input indices_2_out_full_n; +output indices_2_out_write; +output [5:0] indices_2_out1_din; +input indices_2_out1_full_n; +output indices_2_out1_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg indices_0_write; +reg indices_1_write; +reg indices_2_out_write; +reg indices_2_out1_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [15:0] i; +reg [15:0] j; +reg [15:0] k; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg indices_2_out_blk_n; +reg indices_2_out1_blk_n; +reg [0:0] ap_phi_mux_j_flag_0_i_phi_fu_77_p6; +reg ap_block_state1; +wire [0:0] icmp_ln78_fu_141_p2; +wire [0:0] icmp_ln81_fu_154_p2; +reg [15:0] ap_phi_mux_j_new_0_i_phi_fu_91_p6; +wire [15:0] add_ln80_fu_147_p2; +reg [15:0] ap_phi_mux_k_new_0_i_phi_fu_104_p6; +wire [15:0] add_ln77_fu_134_p2; +wire [15:0] select_ln84_fu_172_p3; +wire [5:0] trunc_ln76_fu_128_p1; +wire [15:0] add_ln83_fu_160_p2; +wire [0:0] icmp_ln84_fu_166_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i = 16'd0; +#0 j = 16'd0; +#0 k = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i <= select_ln84_fu_172_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_flag_0_i_phi_fu_77_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j <= ap_phi_mux_j_new_0_i_phi_fu_91_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k <= ap_phi_mux_k_new_0_i_phi_fu_104_p6; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_flag_0_i_phi_fu_77_p6 = 1'd0; + end else if ((((icmp_ln81_fu_154_p2 == 1'd0) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_flag_0_i_phi_fu_77_p6 = 1'd1; + end else begin + ap_phi_mux_j_flag_0_i_phi_fu_77_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln81_fu_154_p2 == 1'd0)) begin + ap_phi_mux_j_new_0_i_phi_fu_91_p6 = add_ln80_fu_147_p2; + end else if ((icmp_ln81_fu_154_p2 == 1'd1)) begin + ap_phi_mux_j_new_0_i_phi_fu_91_p6 = 16'd0; + end else begin + ap_phi_mux_j_new_0_i_phi_fu_91_p6 = 'bx; + end + end else begin + ap_phi_mux_j_new_0_i_phi_fu_91_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_new_0_i_phi_fu_104_p6 = add_ln77_fu_134_p2; + end else if ((((icmp_ln81_fu_154_p2 == 1'd0) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_new_0_i_phi_fu_104_p6 = 16'd0; + end else begin + ap_phi_mux_k_new_0_i_phi_fu_104_p6 = 'bx; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_blk_n = indices_2_out1_full_n; + end else begin + indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_write = 1'b1; + end else begin + indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_blk_n = indices_2_out_full_n; + end else begin + indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_write = 1'b1; + end else begin + indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln77_fu_134_p2 = (k + 16'd1); + +assign add_ln80_fu_147_p2 = (j + 16'd1); + +assign add_ln83_fu_160_p2 = (i + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign icmp_ln78_fu_141_p2 = ((add_ln77_fu_134_p2 == 16'd64) ? 1'b1 : 1'b0); + +assign icmp_ln81_fu_154_p2 = ((add_ln80_fu_147_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign icmp_ln84_fu_166_p2 = ((add_ln83_fu_160_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign indices_0_din = i; + +assign indices_1_din = j; + +assign indices_2_out1_din = trunc_ln76_fu_128_p1; + +assign indices_2_out_din = trunc_ln76_fu_128_p1; + +assign select_ln84_fu_172_p3 = ((icmp_ln84_fu_166_p2[0:0] == 1'b1) ? 16'd0 : add_ln83_fu_160_p2); + +assign start_out = real_start; + +assign trunc_ln76_fu_128_p1 = k[5:0]; + +endmodule //td_fused_top_tdf9_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_readFilters64 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_we0, + weight_vecs_0_0_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state4 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [13:0] filter_data_address0; +output filter_data_ce0; +input [15:0] filter_data_q0; +input [5:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [7:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +output weight_vecs_0_0_0_we0; +output [15:0] weight_vecs_0_0_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg indices_23_read; +reg weight_vecs_0_0_0_ce0; +reg weight_vecs_0_0_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [8:0] kk_0_0_i_i_reg_93; +wire [13:0] tmp_fu_105_p3; +reg [13:0] tmp_reg_144; +wire [8:0] add_ln49_fu_113_p2; +reg [8:0] add_ln49_reg_149; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln49_fu_119_p2; +reg [0:0] icmp_ln49_reg_154; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg [8:0] ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln55_1_fu_134_p1; +wire [63:0] idxprom16_0_0_i_i_fu_139_p1; +wire [13:0] zext_ln55_fu_125_p1; +wire [13:0] add_ln55_fu_129_p2; +wire ap_CS_fsm_state4; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state4)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_0_0_i_i_reg_93 <= add_ln49_reg_149; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_0_0_i_i_reg_93 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln49_reg_149 <= add_ln49_fu_113_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln49_reg_154 <= icmp_ln49_fu_119_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + tmp_reg_144[13 : 8] <= tmp_fu_105_p3[13 : 8]; + end +end + +always @ (*) begin + if ((icmp_ln49_fu_119_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 = add_ln49_reg_149; + end else begin + ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 = kk_0_0_i_i_reg_93; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((icmp_ln49_fu_119_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((icmp_ln49_fu_119_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln49_fu_113_p2 = (ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 + 9'd1); + +assign add_ln55_fu_129_p2 = (tmp_reg_144 + zext_ln55_fu_125_p1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_address0 = zext_ln55_1_fu_134_p1; + +assign icmp_ln49_fu_119_p2 = ((ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 == 9'd256) ? 1'b1 : 1'b0); + +assign idxprom16_0_0_i_i_fu_139_p1 = kk_0_0_i_i_reg_93; + +assign tmp_fu_105_p3 = {{indices_23_dout}, {8'd0}}; + +assign weight_vecs_0_0_0_address0 = idxprom16_0_0_i_i_fu_139_p1; + +assign weight_vecs_0_0_0_d0 = filter_data_q0; + +assign zext_ln55_1_fu_134_p1 = add_ln55_fu_129_p2; + +assign zext_ln55_fu_125_p1 = ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4; + +always @ (posedge ap_clk) begin + tmp_reg_144[7:0] <= 8'b00000000; +end + +endmodule //td_fused_top_tdf9_readFilters64 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_readInputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_we0, + ifmap_vec_0_0_d0, + ifmap_vec_0_0_address1, + ifmap_vec_0_0_ce1, + ifmap_vec_0_0_we1, + ifmap_vec_0_0_d1, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 5'd1; +parameter ap_ST_fsm_state2 = 5'd2; +parameter ap_ST_fsm_pp0_stage0 = 5'd4; +parameter ap_ST_fsm_pp0_stage1 = 5'd8; +parameter ap_ST_fsm_state7 = 5'd16; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [13:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [7:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +output ifmap_vec_0_0_we0; +output [15:0] ifmap_vec_0_0_d0; +output [7:0] ifmap_vec_0_0_address1; +output ifmap_vec_0_0_ce1; +output ifmap_vec_0_0_we1; +output [15:0] ifmap_vec_0_0_d1; +output [3:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [7:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg[7:0] ifmap_vec_0_0_address0; +reg ifmap_vec_0_0_ce0; +reg ifmap_vec_0_0_we0; +reg[15:0] ifmap_vec_0_0_d0; +reg[7:0] ifmap_vec_0_0_address1; +reg ifmap_vec_0_0_ce1; +reg ifmap_vec_0_0_we1; +reg[15:0] ifmap_vec_0_0_d1; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [4:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [8:0] kk_0_i_i_reg_180; +wire [3:0] trunc_ln135_fu_192_p1; +reg [3:0] trunc_ln135_reg_432; +reg [15:0] col_coord_reg_437; +wire [0:0] is_padding_fu_214_p2; +reg [0:0] is_padding_reg_442; +wire [9:0] add_ln32_fu_274_p2; +reg [9:0] add_ln32_reg_452; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln25_fu_280_p2; +reg [0:0] icmp_ln25_reg_457; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state5_pp0_stage0_iter1; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln25_reg_457_pp0_iter1_reg; +wire [8:0] add_ln25_fu_308_p2; +reg [8:0] add_ln25_reg_466; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state4_pp0_stage1_iter0; +wire ap_block_state6_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +wire [15:0] select_ln33_fu_322_p3; +reg [15:0] select_ln33_reg_471; +wire [15:0] select_ln33_1_fu_343_p3; +reg [15:0] select_ln33_1_reg_476; +wire [15:0] select_ln33_2_fu_364_p3; +reg [15:0] select_ln33_2_reg_481; +wire [15:0] select_ln33_3_fu_385_p3; +reg [15:0] select_ln33_3_reg_486; +wire [7:0] empty_68_fu_392_p1; +reg [7:0] empty_68_reg_491; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state3; +reg ap_enable_reg_pp0_iter1; +wire ap_block_pp0_stage1_subdone; +reg [8:0] ap_phi_mux_kk_0_i_i_phi_fu_184_p4; +wire ap_block_pp0_stage0; +wire [63:0] sext_ln32_fu_303_p1; +wire [63:0] zext_ln32_fu_396_p1; +wire [63:0] zext_ln32_2_fu_407_p1; +wire [63:0] zext_ln32_3_fu_417_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln32_4_fu_427_p1; +reg ap_block_state1; +wire [0:0] cmp7_i_i_fu_202_p2; +wire [0:0] icmp_ln24_fu_208_p2; +wire [3:0] empty_66_fu_220_p1; +wire [3:0] row_coord_int_fu_223_p3; +wire [7:0] tmp_fu_236_p3; +wire [4:0] tmp_4_fu_248_p3; +wire [8:0] zext_ln32_1_fu_244_p1; +wire [8:0] zext_ln32_5_fu_256_p1; +wire [8:0] sub_ln32_fu_260_p2; +wire [3:0] col_coord_int_fu_229_p3; +wire [9:0] sub_ln32_cast_fu_266_p1; +wire [9:0] zext_ln32_6_fu_270_p1; +wire [5:0] lshr_ln_fu_286_p4; +wire [15:0] tmp_1_fu_296_p3; +wire [15:0] trunc_ln32_fu_314_p1; +wire [15:0] bitcast_ln32_fu_318_p1; +wire [15:0] tmp_4_i_i_fu_329_p4; +wire [15:0] bitcast_ln32_1_fu_339_p1; +wire [15:0] tmp_5_i_i_fu_350_p4; +wire [15:0] bitcast_ln32_2_fu_360_p1; +wire [15:0] tmp_6_i_i_fu_371_p4; +wire [15:0] bitcast_ln32_3_fu_381_p1; +wire [7:0] or_ln25_fu_401_p2; +wire [7:0] or_ln25_1_fu_412_p2; +wire [7:0] or_ln25_2_fu_422_p2; +wire ap_CS_fsm_state7; +reg [4:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 5'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_i_i_reg_180 <= add_ln25_reg_466; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + kk_0_i_i_reg_180 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln25_reg_466 <= add_ln25_fu_308_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln32_reg_452 <= add_ln32_fu_274_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + col_coord_reg_437 <= indices_12_dout; + is_padding_reg_442 <= is_padding_fu_214_p2; + trunc_ln135_reg_432 <= trunc_ln135_fu_192_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + empty_68_reg_491 <= empty_68_fu_392_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln25_reg_457 <= icmp_ln25_fu_280_p2; + icmp_ln25_reg_457_pp0_iter1_reg <= icmp_ln25_reg_457; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + select_ln33_1_reg_476 <= select_ln33_1_fu_343_p3; + select_ln33_2_reg_481 <= select_ln33_2_fu_364_p3; + select_ln33_3_reg_486 <= select_ln33_3_fu_385_p3; + select_ln33_reg_471 <= select_ln33_fu_322_p3; + end +end + +always @ (*) begin + if ((icmp_ln25_fu_280_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_i_i_phi_fu_184_p4 = add_ln25_reg_466; + end else begin + ap_phi_mux_kk_0_i_i_phi_fu_184_p4 = kk_0_i_i_reg_180; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter1 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_0_0_address0 = zext_ln32_4_fu_427_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_address0 = zext_ln32_2_fu_407_p1; + end else begin + ifmap_vec_0_0_address0 = 'bx; + end + end else begin + ifmap_vec_0_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter1 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_0_0_address1 = zext_ln32_3_fu_417_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_address1 = zext_ln32_fu_396_p1; + end else begin + ifmap_vec_0_0_address1 = 'bx; + end + end else begin + ifmap_vec_0_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_ce1 = 1'b1; + end else begin + ifmap_vec_0_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter1 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_0_0_d0 = select_ln33_3_reg_486; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_d0 = select_ln33_1_reg_476; + end else begin + ifmap_vec_0_0_d0 = 'bx; + end + end else begin + ifmap_vec_0_0_d0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter1 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_0_0_d1 = select_ln33_2_reg_481; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_d1 = select_ln33_reg_471; + end else begin + ifmap_vec_0_0_d1 = 'bx; + end + end else begin + ifmap_vec_0_0_d1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((icmp_ln25_reg_457_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_we0 = 1'b1; + end else begin + ifmap_vec_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln25_reg_457 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((icmp_ln25_reg_457_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_we1 = 1'b1; + end else begin + ifmap_vec_0_0_we1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln25_fu_280_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln25_fu_280_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln25_fu_308_p2 = (kk_0_i_i_reg_180 + 9'd4); + +assign add_ln32_fu_274_p2 = ((sub_ln32_cast_fu_266_p1) + (zext_ln32_6_fu_270_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd4]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln32_1_fu_339_p1 = tmp_4_i_i_fu_329_p4; + +assign bitcast_ln32_2_fu_360_p1 = tmp_5_i_i_fu_350_p4; + +assign bitcast_ln32_3_fu_381_p1 = tmp_6_i_i_fu_371_p4; + +assign bitcast_ln32_fu_318_p1 = trunc_ln32_fu_314_p1; + +assign cmp7_i_i_fu_202_p2 = ((indices_01_dout > 16'd13) ? 1'b1 : 1'b0); + +assign col_coord_int_fu_229_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 4'd0 : empty_66_fu_220_p1); + +assign empty_66_fu_220_p1 = col_coord_reg_437[3:0]; + +assign empty_68_fu_392_p1 = kk_0_i_i_reg_180[7:0]; + +assign icmp_ln24_fu_208_p2 = ((indices_12_dout > 16'd13) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_280_p2 = ((ap_phi_mux_kk_0_i_i_phi_fu_184_p4 == 9'd256) ? 1'b1 : 1'b0); + +assign in_data_address0 = sext_ln32_fu_303_p1; + +assign indices_01_out_din = indices_01_dout[3:0]; + +assign indices_12_out_din = indices_12_dout[7:0]; + +assign is_padding_fu_214_p2 = (icmp_ln24_fu_208_p2 | cmp7_i_i_fu_202_p2); + +assign lshr_ln_fu_286_p4 = {{ap_phi_mux_kk_0_i_i_phi_fu_184_p4[7:2]}}; + +assign or_ln25_1_fu_412_p2 = (empty_68_reg_491 | 8'd2); + +assign or_ln25_2_fu_422_p2 = (empty_68_reg_491 | 8'd3); + +assign or_ln25_fu_401_p2 = (empty_68_fu_392_p1 | 8'd1); + +assign row_coord_int_fu_223_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 4'd0 : trunc_ln135_reg_432); + +assign select_ln33_1_fu_343_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_1_fu_339_p1); + +assign select_ln33_2_fu_364_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_2_fu_360_p1); + +assign select_ln33_3_fu_385_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_3_fu_381_p1); + +assign select_ln33_fu_322_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_fu_318_p1); + +assign sext_ln32_fu_303_p1 = (tmp_1_fu_296_p3); + +assign sub_ln32_cast_fu_266_p1 = (sub_ln32_fu_260_p2); + +assign sub_ln32_fu_260_p2 = (zext_ln32_1_fu_244_p1 - zext_ln32_5_fu_256_p1); + +assign tmp_1_fu_296_p3 = {{add_ln32_reg_452}, {lshr_ln_fu_286_p4}}; + +assign tmp_4_fu_248_p3 = {{row_coord_int_fu_223_p3}, {1'd0}}; + +assign tmp_4_i_i_fu_329_p4 = {{in_data_q0[31:16]}}; + +assign tmp_5_i_i_fu_350_p4 = {{in_data_q0[47:32]}}; + +assign tmp_6_i_i_fu_371_p4 = {{in_data_q0[63:48]}}; + +assign tmp_fu_236_p3 = {{row_coord_int_fu_223_p3}, {4'd0}}; + +assign trunc_ln135_fu_192_p1 = indices_01_dout[3:0]; + +assign trunc_ln32_fu_314_p1 = in_data_q0[15:0]; + +assign zext_ln32_1_fu_244_p1 = tmp_fu_236_p3; + +assign zext_ln32_2_fu_407_p1 = or_ln25_fu_401_p2; + +assign zext_ln32_3_fu_417_p1 = or_ln25_1_fu_412_p2; + +assign zext_ln32_4_fu_427_p1 = or_ln25_2_fu_422_p2; + +assign zext_ln32_5_fu_256_p1 = tmp_4_fu_248_p3; + +assign zext_ln32_6_fu_270_p1 = col_coord_int_fu_229_p3; + +assign zext_ln32_fu_396_p1 = kk_0_i_i_reg_180; + +endmodule //td_fused_top_tdf9_readInputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_writeOutputs_unaligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + p_read, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 2'd1; +parameter ap_ST_fsm_state2 = 2'd2; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [3:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [7:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [15:0] p_read; +output [11:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg out_data_ce1; +reg out_data_we1; + +reg ap_done_reg; + reg [1:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] outputCount; +reg [15:0] outputChanIdx; +reg [15:0] outputRow_0; +reg [15:0] outputRow_1; +reg [15:0] outputRow_2; +reg [15:0] outputRow; +reg indices_01_blk_n; +reg indices_12_blk_n; +wire [11:0] tmp_3_cast_fu_153_p3; +reg [11:0] tmp_3_cast_reg_304; +wire [15:0] add_ln87_fu_193_p2; +wire [0:0] icmp_ln88_fu_199_p2; +reg [0:0] icmp_ln88_reg_317; +reg [15:0] ap_phi_mux_empty_phi_fu_114_p4; +reg [15:0] empty_reg_111; +reg ap_block_state1; +wire ap_CS_fsm_state2; +wire [63:0] zext_ln94_2_fu_226_p1; +wire [15:0] select_ln97_fu_284_p3; +wire [1:0] trunc_ln86_fu_165_p1; +wire [4:0] tmp_1_fu_129_p3; +wire [7:0] tmp_fu_121_p3; +wire [7:0] zext_ln94_fu_137_p1; +wire [7:0] sub_ln94_fu_141_p2; +wire [7:0] add_ln94_fu_147_p2; +wire [5:0] trunc_ln94_fu_213_p1; +wire [11:0] zext_ln94_1_fu_217_p1; +wire [11:0] add_ln94_1_fu_221_p2; +wire [15:0] bitcast_ln94_3_fu_255_p1; +wire [15:0] bitcast_ln94_2_fu_247_p1; +wire [15:0] bitcast_ln94_1_fu_239_p1; +wire [15:0] bitcast_ln94_fu_231_p1; +wire [15:0] add_ln96_fu_272_p2; +wire [0:0] icmp_ln97_fu_278_p2; +reg [1:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 2'd1; +#0 outputCount = 16'd0; +#0 outputChanIdx = 16'd0; +#0 outputRow_0 = 16'd0; +#0 outputRow_1 = 16'd0; +#0 outputRow_2 = 16'd0; +#0 outputRow = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_reg_317 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + empty_reg_111 <= 16'd0; + end else if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln88_fu_199_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + empty_reg_111 <= add_ln87_fu_193_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + icmp_ln88_reg_317 <= icmp_ln88_fu_199_p2; + tmp_3_cast_reg_304[11 : 4] <= tmp_3_cast_fu_153_p3[11 : 4]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_reg_317 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + outputChanIdx <= select_ln97_fu_284_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + outputCount <= ap_phi_mux_empty_phi_fu_114_p4; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (trunc_ln86_fu_165_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow <= p_read; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (trunc_ln86_fu_165_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_0 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (trunc_ln86_fu_165_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_1 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (trunc_ln86_fu_165_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_2 <= p_read; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_reg_317 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_phi_mux_empty_phi_fu_114_p4 = 16'd0; + end else begin + ap_phi_mux_empty_phi_fu_114_p4 = empty_reg_111; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_reg_317 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln87_fu_193_p2 = (outputCount + 16'd1); + +assign add_ln94_1_fu_221_p2 = (tmp_3_cast_reg_304 + zext_ln94_1_fu_217_p1); + +assign add_ln94_fu_147_p2 = (sub_ln94_fu_141_p2 + indices_12_dout); + +assign add_ln96_fu_272_p2 = (outputChanIdx + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign bitcast_ln94_1_fu_239_p1 = outputRow_1; + +assign bitcast_ln94_2_fu_247_p1 = outputRow_2; + +assign bitcast_ln94_3_fu_255_p1 = outputRow; + +assign bitcast_ln94_fu_231_p1 = outputRow_0; + +assign icmp_ln88_fu_199_p2 = ((add_ln87_fu_193_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign icmp_ln97_fu_278_p2 = ((add_ln96_fu_272_p2 == 16'd16) ? 1'b1 : 1'b0); + +assign out_data_address1 = zext_ln94_2_fu_226_p1; + +assign out_data_d1 = {{{{bitcast_ln94_3_fu_255_p1}, {bitcast_ln94_2_fu_247_p1}}, {bitcast_ln94_1_fu_239_p1}}, {bitcast_ln94_fu_231_p1}}; + +assign select_ln97_fu_284_p3 = ((icmp_ln97_fu_278_p2[0:0] == 1'b1) ? 16'd0 : add_ln96_fu_272_p2); + +assign sub_ln94_fu_141_p2 = (tmp_fu_121_p3 - zext_ln94_fu_137_p1); + +assign tmp_1_fu_129_p3 = {{indices_01_dout}, {1'd0}}; + +assign tmp_3_cast_fu_153_p3 = {{add_ln94_fu_147_p2}, {4'd0}}; + +assign tmp_fu_121_p3 = {{indices_01_dout}, {4'd0}}; + +assign trunc_ln86_fu_165_p1 = outputCount[1:0]; + +assign trunc_ln94_fu_213_p1 = outputChanIdx[5:0]; + +assign zext_ln94_1_fu_217_p1 = trunc_ln94_fu_213_p1; + +assign zext_ln94_2_fu_226_p1 = add_ln94_1_fu_221_p2; + +assign zext_ln94_fu_137_p1 = tmp_1_fu_129_p3; + +always @ (posedge ap_clk) begin + tmp_3_cast_reg_304[3:0] <= 4'b0000; +end + +endmodule //td_fused_top_tdf9_writeOutputs_unaligned +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_axi_in_p_ram (addr0, ce0, d0, we0, addr1, ce1, q1, addr2, ce2, q2, addr3, ce3, q3, addr4, ce4, q4, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 2; +parameter MEM_SIZE = 4; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input[AWIDTH-1:0] addr2; +input ce2; +output reg[DWIDTH-1:0] q2; +input[AWIDTH-1:0] addr3; +input ce3; +output reg[DWIDTH-1:0] q3; +input[AWIDTH-1:0] addr4; +input ce4; +output reg[DWIDTH-1:0] q4; +input clk; + +reg [DWIDTH-1:0] ram0[MEM_SIZE-1:0]; +reg [DWIDTH-1:0] ram1[MEM_SIZE-1:0]; +reg [DWIDTH-1:0] ram2[MEM_SIZE-1:0]; +reg [DWIDTH-1:0] ram3[MEM_SIZE-1:0]; + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram0[addr0] <= d0; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram0[addr1]; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram1[addr0] <= d0; + end +end + +always @(posedge clk) +begin + if (ce2) begin + q2 <= ram1[addr2]; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram2[addr0] <= d0; + end +end + +always @(posedge clk) +begin + if (ce3) begin + q3 <= ram2[addr3]; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram3[addr0] <= d0; + end +end + +always @(posedge clk) +begin + if (ce4) begin + q4 <= ram3[addr4]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_axi_in_p( + reset, + clk, + address0, + ce0, + we0, + d0, + address1, + ce1, + q1, + address2, + ce2, + q2, + address3, + ce3, + q3, + address4, + ce4, + q4); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd4; +parameter AddressWidth = 32'd2; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; +input[AddressWidth - 1:0] address2; +input ce2; +output[DataWidth - 1:0] q2; +input[AddressWidth - 1:0] address3; +input ce3; +output[DataWidth - 1:0] q3; +input[AddressWidth - 1:0] address4; +input ce4; +output[DataWidth - 1:0] q4; + + + +td_fused_top_td_fused_axi_in_p_ram td_fused_top_td_fused_axi_in_p_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ), + .addr2( address2 ), + .ce2( ce2 ), + .q2( q2 ), + .addr3( address3 ), + .ce3( ce3 ), + .q3( q3 ), + .addr4( address4 ), + .ce4( ce4 ), + .q4( q4 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_td_fused_axi_in ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + stream_in_TDATA, + stream_in_TVALID, + stream_in_TREADY, + stream_in_TKEEP, + stream_in_TSTRB, + stream_in_TLAST, + fmaps_address1, + fmaps_ce1, + fmaps_we1, + fmaps_d1 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state5 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] stream_in_TDATA; +input stream_in_TVALID; +output stream_in_TREADY; +input [1:0] stream_in_TKEEP; +input [1:0] stream_in_TSTRB; +input [0:0] stream_in_TLAST; +output [15:0] fmaps_address1; +output fmaps_ce1; +output fmaps_we1; +output [63:0] fmaps_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg stream_in_TREADY; +reg fmaps_ce1; +reg fmaps_we1; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [17:0] indvar_flatten16_reg_187; +reg [9:0] indvar_flatten_reg_198; +reg [1:0] ch_reg_209; +reg [7:0] r_reg_220; +reg [7:0] c_reg_231; +wire [17:0] add_ln17_fu_242_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln17_fu_248_p2; +reg [0:0] icmp_ln17_reg_482; +reg [0:0] icmp_ln17_reg_482_pp0_iter1_reg; +wire [0:0] icmp_ln18_fu_257_p2; +reg [0:0] icmp_ln18_reg_486; +wire [0:0] and_ln22_fu_275_p2; +reg [0:0] and_ln22_reg_492; +wire [0:0] icmp_ln25_fu_321_p2; +reg [0:0] icmp_ln25_reg_497; +reg [0:0] icmp_ln25_reg_497_pp0_iter1_reg; +wire [1:0] add_ln20_fu_332_p2; +wire [9:0] select_ln18_fu_344_p3; +wire [7:0] select_ln22_1_fu_365_p3; +reg [7:0] select_ln22_1_reg_511; +reg ap_enable_reg_pp0_iter1; +wire [7:0] select_ln19_55_fu_378_p3; +reg [7:0] select_ln19_55_reg_518; +wire [15:0] p_q4; +reg [15:0] p_load_3_reg_524; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter2; +wire [1:0] p_address0; +reg p_ce0; +reg p_we0; +wire [15:0] p_d0; +wire [1:0] p_address1; +reg p_ce1; +wire [15:0] p_q1; +wire [1:0] p_address2; +reg p_ce2; +wire [15:0] p_q2; +wire [1:0] p_address3; +reg p_ce3; +wire [15:0] p_q3; +wire [1:0] p_address4; +reg p_ce4; +reg [7:0] ap_phi_mux_r_phi_fu_224_p4; +wire ap_block_pp0_stage0; +reg [7:0] ap_phi_mux_c_phi_fu_235_p4; +wire [63:0] zext_ln20_fu_295_p1; +wire [63:0] zext_ln27_2_fu_418_p1; +reg [15:0] tmp_data_1_fu_90; +wire [15:0] tmp_data_fu_312_p3; +wire [0:0] empty_169_nbread_fu_98_p5_0; +wire [0:0] icmp_ln20_fu_269_p2; +wire [0:0] xor_ln22_fu_263_p2; +wire [0:0] or_ln19_fu_281_p2; +wire [1:0] select_ln19_fu_287_p3; +wire [15:0] tmp_data_2_fu_308_p1; +wire [9:0] add_ln18_2_fu_338_p2; +wire [7:0] r_2_fu_352_p2; +wire [7:0] select_ln22_fu_358_p3; +wire [7:0] c_2_fu_372_p2; +wire [12:0] tmp_76_fu_392_p3; +wire [15:0] tmp_fu_385_p3; +wire [15:0] zext_ln27_fu_399_p1; +wire [15:0] sub_ln27_fu_403_p2; +wire [15:0] zext_ln27_1_fu_409_p1; +wire [15:0] add_ln27_fu_412_p2; +wire [15:0] bitcast_ln27_3_fu_435_p1; +wire [15:0] bitcast_ln27_2_fu_431_p1; +wire [15:0] bitcast_ln27_1_fu_427_p1; +wire [15:0] bitcast_ln27_fu_423_p1; +wire ap_CS_fsm_state5; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_td_fused_axi_in_p #( + .DataWidth( 16 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +p_U( + .reset(ap_rst), + .clk(ap_clk), + .address0(p_address0), + .ce0(p_ce0), + .we0(p_we0), + .d0(p_d0), + .address1(p_address1), + .ce1(p_ce1), + .q1(p_q1), + .address2(p_address2), + .ce2(p_ce2), + .q2(p_q2), + .address3(p_address3), + .ce3(p_ce3), + .q3(p_q3), + .address4(p_address4), + .ce4(p_ce4), + .q4(p_q4) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state5)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter1_state3)) | (~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter1_state3))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_482_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + c_reg_231 <= select_ln19_55_reg_518; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + c_reg_231 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_fu_248_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ch_reg_209 <= add_ln20_fu_332_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ch_reg_209 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_fu_248_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten16_reg_187 <= add_ln17_fu_242_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten16_reg_187 <= 18'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_fu_248_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_198 <= select_ln18_fu_344_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_198 <= 10'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_482_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + r_reg_220 <= select_ln22_1_reg_511; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + r_reg_220 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_fu_248_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + and_ln22_reg_492 <= and_ln22_fu_275_p2; + icmp_ln18_reg_486 <= icmp_ln18_fu_257_p2; + icmp_ln25_reg_497 <= icmp_ln25_fu_321_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln17_reg_482 <= icmp_ln17_fu_248_p2; + icmp_ln17_reg_482_pp0_iter1_reg <= icmp_ln17_reg_482; + icmp_ln25_reg_497_pp0_iter1_reg <= icmp_ln25_reg_497; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln25_reg_497 == 1'd1) & (icmp_ln17_reg_482 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + p_load_3_reg_524 <= p_q4; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln17_reg_482 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln19_55_reg_518 <= select_ln19_55_fu_378_p3; + select_ln22_1_reg_511 <= select_ln22_1_fu_365_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_fu_248_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + tmp_data_1_fu_90 <= tmp_data_fu_312_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln17_fu_248_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state5)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln17_reg_482_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_c_phi_fu_235_p4 = select_ln19_55_reg_518; + end else begin + ap_phi_mux_c_phi_fu_235_p4 = c_reg_231; + end +end + +always @ (*) begin + if (((icmp_ln17_reg_482_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_r_phi_fu_224_p4 = select_ln22_1_reg_511; + end else begin + ap_phi_mux_r_phi_fu_224_p4 = r_reg_220; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state5)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + fmaps_ce1 = 1'b1; + end else begin + fmaps_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln25_reg_497_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + fmaps_we1 = 1'b1; + end else begin + fmaps_we1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + p_ce0 = 1'b1; + end else begin + p_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + p_ce1 = 1'b1; + end else begin + p_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + p_ce2 = 1'b1; + end else begin + p_ce2 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + p_ce3 = 1'b1; + end else begin + p_ce3 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + p_ce4 = 1'b1; + end else begin + p_ce4 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln17_fu_248_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + p_we0 = 1'b1; + end else begin + p_we0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln17_fu_248_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (stream_in_TVALID == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + stream_in_TREADY = 1'b1; + end else begin + stream_in_TREADY = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_NS_fsm = ap_ST_fsm_state5; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln17_fu_242_p2 = (indvar_flatten16_reg_187 + 18'd1); + +assign add_ln18_2_fu_338_p2 = (indvar_flatten_reg_198 + 10'd1); + +assign add_ln20_fu_332_p2 = (select_ln19_fu_287_p3 + 2'd1); + +assign add_ln27_fu_412_p2 = (sub_ln27_fu_403_p2 + zext_ln27_1_fu_409_p1); + +assign and_ln22_fu_275_p2 = (xor_ln22_fu_263_p2 & icmp_ln20_fu_269_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state5 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln27_1_fu_427_p1 = p_q2; + +assign bitcast_ln27_2_fu_431_p1 = p_q1; + +assign bitcast_ln27_3_fu_435_p1 = p_load_3_reg_524; + +assign bitcast_ln27_fu_423_p1 = p_q3; + +assign c_2_fu_372_p2 = (select_ln22_fu_358_p3 + 8'd1); + +assign empty_169_nbread_fu_98_p5_0 = stream_in_TVALID; + +assign fmaps_address1 = zext_ln27_2_fu_418_p1; + +assign fmaps_d1 = {{{{bitcast_ln27_3_fu_435_p1}, {bitcast_ln27_2_fu_431_p1}}, {bitcast_ln27_1_fu_427_p1}}, {bitcast_ln27_fu_423_p1}}; + +assign icmp_ln17_fu_248_p2 = ((indvar_flatten16_reg_187 == 18'd150528) ? 1'b1 : 1'b0); + +assign icmp_ln18_fu_257_p2 = ((indvar_flatten_reg_198 == 10'd672) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_269_p2 = ((ch_reg_209 == 2'd3) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_321_p2 = ((select_ln19_fu_287_p3 == 2'd2) ? 1'b1 : 1'b0); + +assign or_ln19_fu_281_p2 = (icmp_ln18_fu_257_p2 | and_ln22_fu_275_p2); + +assign p_address0 = zext_ln20_fu_295_p1; + +assign p_address1 = 64'd2; + +assign p_address2 = 64'd1; + +assign p_address3 = 64'd0; + +assign p_address4 = 64'd3; + +assign p_d0 = ((empty_169_nbread_fu_98_p5_0[0:0] == 1'b1) ? tmp_data_2_fu_308_p1 : tmp_data_1_fu_90); + +assign r_2_fu_352_p2 = (ap_phi_mux_r_phi_fu_224_p4 + 8'd1); + +assign select_ln18_fu_344_p3 = ((icmp_ln18_fu_257_p2[0:0] == 1'b1) ? 10'd1 : add_ln18_2_fu_338_p2); + +assign select_ln19_55_fu_378_p3 = ((and_ln22_reg_492[0:0] == 1'b1) ? c_2_fu_372_p2 : select_ln22_fu_358_p3); + +assign select_ln19_fu_287_p3 = ((or_ln19_fu_281_p2[0:0] == 1'b1) ? 2'd0 : ch_reg_209); + +assign select_ln22_1_fu_365_p3 = ((icmp_ln18_reg_486[0:0] == 1'b1) ? r_2_fu_352_p2 : ap_phi_mux_r_phi_fu_224_p4); + +assign select_ln22_fu_358_p3 = ((icmp_ln18_reg_486[0:0] == 1'b1) ? 8'd0 : ap_phi_mux_c_phi_fu_235_p4); + +assign sub_ln27_fu_403_p2 = (tmp_fu_385_p3 - zext_ln27_fu_399_p1); + +assign tmp_76_fu_392_p3 = {{select_ln22_1_reg_511}, {5'd0}}; + +assign tmp_data_2_fu_308_p1 = stream_in_TDATA; + +assign tmp_data_fu_312_p3 = ((empty_169_nbread_fu_98_p5_0[0:0] == 1'b1) ? tmp_data_2_fu_308_p1 : tmp_data_1_fu_90); + +assign tmp_fu_385_p3 = {{select_ln22_1_reg_511}, {8'd0}}; + +assign xor_ln22_fu_263_p2 = (icmp_ln18_fu_257_p2 ^ 1'd1); + +assign zext_ln20_fu_295_p1 = select_ln19_fu_287_p3; + +assign zext_ln27_1_fu_409_p1 = select_ln19_55_reg_518; + +assign zext_ln27_2_fu_418_p1 = add_ln27_fu_412_p2; + +assign zext_ln27_fu_399_p1 = tmp_76_fu_392_p3; + +endmodule //td_fused_top_td_fused_axi_in +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_td_fused_axi_out ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + fmaps_address0, + fmaps_ce0, + fmaps_q0, + stream_out_TDATA, + stream_out_TVALID, + stream_out_TREADY, + stream_out_TKEEP, + stream_out_TSTRB, + stream_out_TLAST +); + +parameter ap_ST_fsm_state1 = 6'd1; +parameter ap_ST_fsm_pp0_stage0 = 6'd2; +parameter ap_ST_fsm_pp0_stage1 = 6'd4; +parameter ap_ST_fsm_pp0_stage2 = 6'd8; +parameter ap_ST_fsm_pp0_stage3 = 6'd16; +parameter ap_ST_fsm_state11 = 6'd32; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] fmaps_address0; +output fmaps_ce0; +input [63:0] fmaps_q0; +output [15:0] stream_out_TDATA; +output stream_out_TVALID; +input stream_out_TREADY; +output [1:0] stream_out_TKEEP; +output [1:0] stream_out_TSTRB; +output [0:0] stream_out_TLAST; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg fmaps_ce0; +reg[15:0] stream_out_TDATA; +reg stream_out_TVALID; + +reg ap_done_reg; + reg [5:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg stream_out_TDATA_blk_n; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter1; +wire ap_block_pp0_stage1; +reg [0:0] icmp_ln17_reg_406; +reg [0:0] icmp_ln17_reg_406_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_pp0_stage2; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_pp0_stage3; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter2; +wire ap_block_pp0_stage0; +reg [15:0] indvar_flatten13_reg_134; +reg [3:0] r_reg_145; +reg [11:0] indvar_flatten_reg_156; +reg [3:0] c_reg_167; +reg [9:0] phi_ln25_reg_178; +wire [15:0] add_ln17_1_fu_189_p2; +reg [15:0] add_ln17_1_reg_401; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state6_pp0_stage0_iter1; +reg ap_block_state10_pp0_stage0_iter2; +reg ap_block_state10_io; +reg ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln17_fu_195_p2; +wire [3:0] select_ln17_1_fu_221_p3; +reg [3:0] select_ln17_1_reg_410; +wire [8:0] sub_ln25_fu_253_p2; +reg [8:0] sub_ln25_reg_415; +wire [9:0] select_ln18_fu_289_p3; +reg [9:0] select_ln18_reg_420; +wire [3:0] select_ln18_1_fu_297_p3; +reg [3:0] select_ln18_1_reg_425; +reg [7:0] lshr_ln_reg_431; +wire [11:0] select_ln18_2_fu_321_p3; +reg [11:0] select_ln18_2_reg_436; +wire ap_block_state3_pp0_stage1_iter0; +reg ap_block_state7_pp0_stage1_iter1; +reg ap_block_state7_io; +reg ap_block_pp0_stage1_11001; +wire ap_block_state5_pp0_stage3_iter0; +reg ap_block_state9_pp0_stage3_iter1; +reg ap_block_state9_io; +reg ap_block_pp0_stage3_11001; +wire [9:0] add_ln19_fu_348_p2; +reg [9:0] add_ln19_reg_451; +reg [15:0] tmp_s_reg_461; +reg [15:0] tmp_1_reg_466; +reg [15:0] tmp_2_reg_471; +reg ap_block_state1; +reg ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_block_pp0_stage3_subdone; +reg [15:0] ap_phi_mux_indvar_flatten13_phi_fu_138_p4; +reg [3:0] ap_phi_mux_r_phi_fu_149_p4; +reg [11:0] ap_phi_mux_indvar_flatten_phi_fu_160_p4; +reg [3:0] ap_phi_mux_c_phi_fu_171_p4; +reg [9:0] ap_phi_mux_phi_ln25_phi_fu_182_p4; +wire [63:0] zext_ln25_4_fu_353_p1; +wire [15:0] trunc_ln25_fu_357_p1; +reg ap_block_pp0_stage1_01001; +wire ap_block_state4_pp0_stage2_iter0; +reg ap_block_state8_pp0_stage2_iter1; +reg ap_block_pp0_stage2_01001; +reg ap_block_pp0_stage3_01001; +reg ap_block_pp0_stage0_01001; +reg ap_block_state8_io; +reg ap_block_pp0_stage2_11001; +wire [0:0] icmp_ln18_fu_207_p2; +wire [3:0] add_ln17_fu_201_p2; +wire [7:0] tmp_74_fu_229_p3; +wire [4:0] tmp_75_fu_241_p3; +wire [8:0] zext_ln25_fu_237_p1; +wire [8:0] zext_ln25_1_fu_249_p1; +wire [0:0] icmp_ln19_fu_265_p2; +wire [0:0] xor_ln17_fu_259_p2; +wire [3:0] select_ln17_fu_213_p3; +wire [0:0] and_ln17_fu_271_p2; +wire [0:0] or_ln18_fu_283_p2; +wire [3:0] add_ln18_fu_277_p2; +wire [11:0] add_ln18_1_fu_315_p2; +wire [9:0] sext_ln18_fu_329_p1; +wire [9:0] zext_ln25_2_fu_332_p1; +wire [9:0] add_ln25_fu_335_p2; +wire [15:0] grp_fu_392_p3; +wire [8:0] grp_fu_392_p1; +wire [7:0] grp_fu_392_p2; +reg grp_fu_392_ce; +wire ap_CS_fsm_state11; +reg [5:0] ap_NS_fsm; +reg ap_block_pp0_stage1_subdone; +reg ap_block_pp0_stage2_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire [15:0] grp_fu_392_p20; +reg ap_condition_229; +reg ap_condition_236; +reg ap_condition_241; +reg ap_condition_247; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 6'd1; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +end + +td_fused_top_mac_muladd_10s_9ns_8ns_16_4_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 10 ), + .din1_WIDTH( 9 ), + .din2_WIDTH( 8 ), + .dout_WIDTH( 16 )) +mac_muladd_10s_9ns_8ns_16_4_1_U1959( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_392_ce), + .din0(add_ln25_fu_335_p2), + .din1(grp_fu_392_p1), + .din2(grp_fu_392_p2), + .dout(grp_fu_392_p3) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_406 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + c_reg_167 <= select_ln18_1_reg_425; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + c_reg_167 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_406 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten13_reg_134 <= add_ln17_1_reg_401; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_134 <= 16'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_406 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_156 <= select_ln18_2_reg_436; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_156 <= 12'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_406 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + phi_ln25_reg_178 <= add_ln19_reg_451; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + phi_ln25_reg_178 <= 10'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_406 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + r_reg_145 <= select_ln17_1_reg_410; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + r_reg_145 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln17_1_reg_401 <= add_ln17_1_fu_189_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_406 == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln19_reg_451 <= add_ln19_fu_348_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln17_reg_406 <= icmp_ln17_fu_195_p2; + icmp_ln17_reg_406_pp0_iter1_reg <= icmp_ln17_reg_406; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln17_fu_195_p2 == 1'd0))) begin + lshr_ln_reg_431 <= {{select_ln18_fu_289_p3[9:2]}}; + select_ln18_reg_420 <= select_ln18_fu_289_p3; + sub_ln25_reg_415[8 : 1] <= sub_ln25_fu_253_p2[8 : 1]; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln17_fu_195_p2 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln17_1_reg_410 <= select_ln17_1_fu_221_p3; + select_ln18_1_reg_425 <= select_ln18_1_fu_297_p3; + select_ln18_2_reg_436 <= select_ln18_2_fu_321_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + tmp_1_reg_466 <= {{fmaps_q0[47:32]}}; + tmp_2_reg_471 <= {{fmaps_q0[63:48]}}; + tmp_s_reg_461 <= {{fmaps_q0[31:16]}}; + end +end + +always @ (*) begin + if ((icmp_ln17_fu_195_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln17_reg_406 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_c_phi_fu_171_p4 = select_ln18_1_reg_425; + end else begin + ap_phi_mux_c_phi_fu_171_p4 = c_reg_167; + end +end + +always @ (*) begin + if (((icmp_ln17_reg_406 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_indvar_flatten13_phi_fu_138_p4 = add_ln17_1_reg_401; + end else begin + ap_phi_mux_indvar_flatten13_phi_fu_138_p4 = indvar_flatten13_reg_134; + end +end + +always @ (*) begin + if (((icmp_ln17_reg_406 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_indvar_flatten_phi_fu_160_p4 = select_ln18_2_reg_436; + end else begin + ap_phi_mux_indvar_flatten_phi_fu_160_p4 = indvar_flatten_reg_156; + end +end + +always @ (*) begin + if (((icmp_ln17_reg_406 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_phi_ln25_phi_fu_182_p4 = add_ln19_reg_451; + end else begin + ap_phi_mux_phi_ln25_phi_fu_182_p4 = phi_ln25_reg_178; + end +end + +always @ (*) begin + if (((icmp_ln17_reg_406 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_r_phi_fu_149_p4 = select_ln17_1_reg_410; + end else begin + ap_phi_mux_r_phi_fu_149_p4 = r_reg_145; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + fmaps_ce0 = 1'b1; + end else begin + fmaps_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin + grp_fu_392_ce = 1'b1; + end else begin + grp_fu_392_ce = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0)) begin + if ((1'b1 == ap_condition_247)) begin + stream_out_TDATA = tmp_2_reg_471; + end else if ((1'b1 == ap_condition_241)) begin + stream_out_TDATA = tmp_1_reg_466; + end else if ((1'b1 == ap_condition_236)) begin + stream_out_TDATA = tmp_s_reg_461; + end else if ((1'b1 == ap_condition_229)) begin + stream_out_TDATA = trunc_ln25_fu_357_p1; + end else begin + stream_out_TDATA = 'bx; + end + end else begin + stream_out_TDATA = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + stream_out_TDATA_blk_n = stream_out_TREADY; + end else begin + stream_out_TDATA_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage2_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + stream_out_TVALID = 1'b1; + end else begin + stream_out_TVALID = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln17_fu_195_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln17_fu_195_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state11; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((1'b0 == ap_block_pp0_stage2_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln17_1_fu_189_p2 = (ap_phi_mux_indvar_flatten13_phi_fu_138_p4 + 16'd1); + +assign add_ln17_fu_201_p2 = (ap_phi_mux_r_phi_fu_149_p4 + 4'd1); + +assign add_ln18_1_fu_315_p2 = (ap_phi_mux_indvar_flatten_phi_fu_160_p4 + 12'd1); + +assign add_ln18_fu_277_p2 = (select_ln17_fu_213_p3 + 4'd1); + +assign add_ln19_fu_348_p2 = (select_ln18_reg_420 + 10'd4); + +assign add_ln25_fu_335_p2 = ((sext_ln18_fu_329_p1) + (zext_ln25_2_fu_332_p1)); + +assign and_ln17_fu_271_p2 = (xor_ln17_fu_259_p2 & icmp_ln19_fu_265_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd5]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_pp0_stage0_01001 = ((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_pp0_stage0_11001 = ((ap_enable_reg_pp0_iter2 == 1'b1) & ((1'b1 == ap_block_state10_io) | ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +always @ (*) begin + ap_block_pp0_stage0_subdone = ((ap_enable_reg_pp0_iter2 == 1'b1) & ((1'b1 == ap_block_state10_io) | ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_pp0_stage1_01001 = ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_pp0_stage1_11001 = ((ap_enable_reg_pp0_iter1 == 1'b1) & ((1'b1 == ap_block_state7_io) | ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +always @ (*) begin + ap_block_pp0_stage1_subdone = ((ap_enable_reg_pp0_iter1 == 1'b1) & ((1'b1 == ap_block_state7_io) | ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_pp0_stage2_01001 = ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_pp0_stage2_11001 = ((ap_enable_reg_pp0_iter1 == 1'b1) & ((1'b1 == ap_block_state8_io) | ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +always @ (*) begin + ap_block_pp0_stage2_subdone = ((ap_enable_reg_pp0_iter1 == 1'b1) & ((1'b1 == ap_block_state8_io) | ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_pp0_stage3_01001 = ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_pp0_stage3_11001 = ((ap_enable_reg_pp0_iter1 == 1'b1) & ((1'b1 == ap_block_state9_io) | ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +always @ (*) begin + ap_block_pp0_stage3_subdone = ((ap_enable_reg_pp0_iter1 == 1'b1) & ((1'b1 == ap_block_state9_io) | ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +always @ (*) begin + ap_block_state10_io = ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_state10_pp0_stage0_iter2 = ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state7_io = ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_state7_pp0_stage1_iter1 = ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_state8_io = ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_state8_pp0_stage2_iter1 = ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_state9_io = ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_state9_pp0_stage3_iter1 = ((icmp_ln17_reg_406_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_condition_229 = ((1'b0 == ap_block_pp0_stage1_01001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1)); +end + +always @ (*) begin + ap_condition_236 = ((1'b0 == ap_block_pp0_stage2_01001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2)); +end + +always @ (*) begin + ap_condition_241 = ((1'b0 == ap_block_pp0_stage3_01001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3)); +end + +always @ (*) begin + ap_condition_247 = ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_01001) & (1'b1 == ap_CS_fsm_pp0_stage0)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign fmaps_address0 = zext_ln25_4_fu_353_p1; + +assign grp_fu_392_p1 = 16'd250; + +assign grp_fu_392_p2 = grp_fu_392_p20; + +assign grp_fu_392_p20 = lshr_ln_reg_431; + +assign icmp_ln17_fu_195_p2 = ((ap_phi_mux_indvar_flatten13_phi_fu_138_p4 == 16'd49000) ? 1'b1 : 1'b0); + +assign icmp_ln18_fu_207_p2 = ((ap_phi_mux_indvar_flatten_phi_fu_160_p4 == 12'd3500) ? 1'b1 : 1'b0); + +assign icmp_ln19_fu_265_p2 = ((ap_phi_mux_phi_ln25_phi_fu_182_p4 == 10'd1000) ? 1'b1 : 1'b0); + +assign or_ln18_fu_283_p2 = (icmp_ln18_fu_207_p2 | and_ln17_fu_271_p2); + +assign select_ln17_1_fu_221_p3 = ((icmp_ln18_fu_207_p2[0:0] == 1'b1) ? add_ln17_fu_201_p2 : ap_phi_mux_r_phi_fu_149_p4); + +assign select_ln17_fu_213_p3 = ((icmp_ln18_fu_207_p2[0:0] == 1'b1) ? 4'd0 : ap_phi_mux_c_phi_fu_171_p4); + +assign select_ln18_1_fu_297_p3 = ((and_ln17_fu_271_p2[0:0] == 1'b1) ? add_ln18_fu_277_p2 : select_ln17_fu_213_p3); + +assign select_ln18_2_fu_321_p3 = ((icmp_ln18_fu_207_p2[0:0] == 1'b1) ? 12'd1 : add_ln18_1_fu_315_p2); + +assign select_ln18_fu_289_p3 = ((or_ln18_fu_283_p2[0:0] == 1'b1) ? 10'd0 : ap_phi_mux_phi_ln25_phi_fu_182_p4); + +assign sext_ln18_fu_329_p1 = (sub_ln25_reg_415); + +assign stream_out_TKEEP = 2'd0; + +assign stream_out_TLAST = 1'd0; + +assign stream_out_TSTRB = 2'd0; + +assign sub_ln25_fu_253_p2 = (zext_ln25_fu_237_p1 - zext_ln25_1_fu_249_p1); + +assign tmp_74_fu_229_p3 = {{select_ln17_1_fu_221_p3}, {4'd0}}; + +assign tmp_75_fu_241_p3 = {{select_ln17_1_fu_221_p3}, {1'd0}}; + +assign trunc_ln25_fu_357_p1 = fmaps_q0[15:0]; + +assign xor_ln17_fu_259_p2 = (icmp_ln18_fu_207_p2 ^ 1'd1); + +assign zext_ln25_1_fu_249_p1 = tmp_75_fu_241_p3; + +assign zext_ln25_2_fu_332_p1 = select_ln18_1_reg_425; + +assign zext_ln25_4_fu_353_p1 = (grp_fu_392_p3); + +assign zext_ln25_fu_237_p1 = tmp_74_fu_229_p3; + +always @ (posedge ap_clk) begin + sub_ln25_reg_415[0] <= 1'b0; +end + +endmodule //td_fused_top_td_fused_axi_out +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_final_fmaps_memcore_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 16; +parameter MEM_SIZE = 49000; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_final_fmaps_memcore( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd49000; +parameter AddressWidth = 32'd16; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_td_fused_final_fmaps_memcore_ram td_fused_top_td_fused_final_fmaps_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_td_fused_final_fmaps +#(parameter + DataWidth = 64, + AddressRange = 32, + AddressWidth = 16, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire [AddressWidth-1:0] i_address0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire [AddressWidth-1:0] t_address0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_td_fused_final_fmaps_memcore td_fused_top_td_fused_final_fmaps_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_td_fused_final_fmaps_memcore td_fused_top_td_fused_final_fmaps_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf10_fmaps_memcore_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 12; +parameter MEM_SIZE = 3136; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf10_fmaps_memcore( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd3136; +parameter AddressWidth = 32'd12; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_td_fused_tdf10_fmaps_memcore_ram td_fused_top_td_fused_tdf10_fmaps_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_td_fused_tdf10_fmaps +#(parameter + DataWidth = 64, + AddressRange = 32, + AddressWidth = 12, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire [AddressWidth-1:0] i_address0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire [AddressWidth-1:0] t_address0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_td_fused_tdf10_fmaps_memcore td_fused_top_td_fused_tdf10_fmaps_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_td_fused_tdf10_fmaps_memcore td_fused_top_td_fused_tdf10_fmaps_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf1_fmaps_memcore_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 16; +parameter MEM_SIZE = 50176; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf1_fmaps_memcore( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd50176; +parameter AddressWidth = 32'd16; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_td_fused_tdf1_fmaps_memcore_ram td_fused_top_td_fused_tdf1_fmaps_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_td_fused_tdf1_fmaps +#(parameter + DataWidth = 64, + AddressRange = 32, + AddressWidth = 16, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire [AddressWidth-1:0] i_address0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire [AddressWidth-1:0] t_address0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_td_fused_tdf1_fmaps_memcore td_fused_top_td_fused_tdf1_fmaps_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_td_fused_tdf1_fmaps_memcore td_fused_top_td_fused_tdf1_fmaps_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf3_fmaps_memcore_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 15; +parameter MEM_SIZE = 25088; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf3_fmaps_memcore( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd25088; +parameter AddressWidth = 32'd15; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_td_fused_tdf3_fmaps_memcore_ram td_fused_top_td_fused_tdf3_fmaps_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_td_fused_tdf3_fmaps +#(parameter + DataWidth = 64, + AddressRange = 32, + AddressWidth = 15, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire [AddressWidth-1:0] i_address0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire [AddressWidth-1:0] t_address0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_td_fused_tdf3_fmaps_memcore td_fused_top_td_fused_tdf3_fmaps_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_td_fused_tdf3_fmaps_memcore td_fused_top_td_fused_tdf3_fmaps_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf4_fmaps_memcore_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 14; +parameter MEM_SIZE = 12544; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf4_fmaps_memcore( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd12544; +parameter AddressWidth = 32'd14; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_td_fused_tdf4_fmaps_memcore_ram td_fused_top_td_fused_tdf4_fmaps_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_td_fused_tdf4_fmaps +#(parameter + DataWidth = 64, + AddressRange = 32, + AddressWidth = 14, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire [AddressWidth-1:0] i_address0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire [AddressWidth-1:0] t_address0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_td_fused_tdf4_fmaps_memcore td_fused_top_td_fused_tdf4_fmaps_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_td_fused_tdf4_fmaps_memcore td_fused_top_td_fused_tdf4_fmaps_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf7_fmaps_memcore_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 13; +parameter MEM_SIZE = 6272; + +input[AWIDTH-1:0] addr0; +input ce0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf7_fmaps_memcore( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd6272; +parameter AddressWidth = 32'd13; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_td_fused_tdf7_fmaps_memcore_ram td_fused_top_td_fused_tdf7_fmaps_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_td_fused_tdf7_fmaps +#(parameter + DataWidth = 64, + AddressRange = 32, + AddressWidth = 13, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire [AddressWidth-1:0] i_address0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire [AddressWidth-1:0] t_address0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_td_fused_tdf7_fmaps_memcore td_fused_top_td_fused_tdf7_fmaps_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_td_fused_tdf7_fmaps_memcore td_fused_top_td_fused_tdf7_fmaps_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_td_fused ( + ap_clk, + ap_rst, + tdf1_filters_0_address0, + tdf1_filters_0_ce0, + tdf1_filters_0_d0, + tdf1_filters_0_q0, + tdf1_filters_0_we0, + tdf1_filters_0_address1, + tdf1_filters_0_ce1, + tdf1_filters_0_d1, + tdf1_filters_0_q1, + tdf1_filters_0_we1, + tdf1_filters_1_address0, + tdf1_filters_1_ce0, + tdf1_filters_1_d0, + tdf1_filters_1_q0, + tdf1_filters_1_we0, + tdf1_filters_1_address1, + tdf1_filters_1_ce1, + tdf1_filters_1_d1, + tdf1_filters_1_q1, + tdf1_filters_1_we1, + tdf1_filters_2_address0, + tdf1_filters_2_ce0, + tdf1_filters_2_d0, + tdf1_filters_2_q0, + tdf1_filters_2_we0, + tdf1_filters_2_address1, + tdf1_filters_2_ce1, + tdf1_filters_2_d1, + tdf1_filters_2_q1, + tdf1_filters_2_we1, + tdf1_filters_3_address0, + tdf1_filters_3_ce0, + tdf1_filters_3_d0, + tdf1_filters_3_q0, + tdf1_filters_3_we0, + tdf1_filters_3_address1, + tdf1_filters_3_ce1, + tdf1_filters_3_d1, + tdf1_filters_3_q1, + tdf1_filters_3_we1, + tdf2_filters_0_address0, + tdf2_filters_0_ce0, + tdf2_filters_0_d0, + tdf2_filters_0_q0, + tdf2_filters_0_we0, + tdf2_filters_0_address1, + tdf2_filters_0_ce1, + tdf2_filters_0_d1, + tdf2_filters_0_q1, + tdf2_filters_0_we1, + tdf2_filters_1_address0, + tdf2_filters_1_ce0, + tdf2_filters_1_d0, + tdf2_filters_1_q0, + tdf2_filters_1_we0, + tdf2_filters_1_address1, + tdf2_filters_1_ce1, + tdf2_filters_1_d1, + tdf2_filters_1_q1, + tdf2_filters_1_we1, + tdf2_filters_2_address0, + tdf2_filters_2_ce0, + tdf2_filters_2_d0, + tdf2_filters_2_q0, + tdf2_filters_2_we0, + tdf2_filters_2_address1, + tdf2_filters_2_ce1, + tdf2_filters_2_d1, + tdf2_filters_2_q1, + tdf2_filters_2_we1, + tdf2_filters_3_address0, + tdf2_filters_3_ce0, + tdf2_filters_3_d0, + tdf2_filters_3_q0, + tdf2_filters_3_we0, + tdf2_filters_3_address1, + tdf2_filters_3_ce1, + tdf2_filters_3_d1, + tdf2_filters_3_q1, + tdf2_filters_3_we1, + tdf3_filters_address0, + tdf3_filters_ce0, + tdf3_filters_d0, + tdf3_filters_q0, + tdf3_filters_we0, + tdf3_filters_address1, + tdf3_filters_ce1, + tdf3_filters_d1, + tdf3_filters_q1, + tdf3_filters_we1, + tdf4_filters_0_address0, + tdf4_filters_0_ce0, + tdf4_filters_0_d0, + tdf4_filters_0_q0, + tdf4_filters_0_we0, + tdf4_filters_0_address1, + tdf4_filters_0_ce1, + tdf4_filters_0_d1, + tdf4_filters_0_q1, + tdf4_filters_0_we1, + tdf4_filters_1_address0, + tdf4_filters_1_ce0, + tdf4_filters_1_d0, + tdf4_filters_1_q0, + tdf4_filters_1_we0, + tdf4_filters_1_address1, + tdf4_filters_1_ce1, + tdf4_filters_1_d1, + tdf4_filters_1_q1, + tdf4_filters_1_we1, + tdf4_filters_2_address0, + tdf4_filters_2_ce0, + tdf4_filters_2_d0, + tdf4_filters_2_q0, + tdf4_filters_2_we0, + tdf4_filters_2_address1, + tdf4_filters_2_ce1, + tdf4_filters_2_d1, + tdf4_filters_2_q1, + tdf4_filters_2_we1, + tdf4_filters_3_address0, + tdf4_filters_3_ce0, + tdf4_filters_3_d0, + tdf4_filters_3_q0, + tdf4_filters_3_we0, + tdf4_filters_3_address1, + tdf4_filters_3_ce1, + tdf4_filters_3_d1, + tdf4_filters_3_q1, + tdf4_filters_3_we1, + tdf4_l2_filters_0_address0, + tdf4_l2_filters_0_ce0, + tdf4_l2_filters_0_d0, + tdf4_l2_filters_0_q0, + tdf4_l2_filters_0_we0, + tdf4_l2_filters_0_address1, + tdf4_l2_filters_0_ce1, + tdf4_l2_filters_0_d1, + tdf4_l2_filters_0_q1, + tdf4_l2_filters_0_we1, + tdf4_l2_filters_1_address0, + tdf4_l2_filters_1_ce0, + tdf4_l2_filters_1_d0, + tdf4_l2_filters_1_q0, + tdf4_l2_filters_1_we0, + tdf4_l2_filters_1_address1, + tdf4_l2_filters_1_ce1, + tdf4_l2_filters_1_d1, + tdf4_l2_filters_1_q1, + tdf4_l2_filters_1_we1, + tdf5_filters_0_address0, + tdf5_filters_0_ce0, + tdf5_filters_0_d0, + tdf5_filters_0_q0, + tdf5_filters_0_we0, + tdf5_filters_0_address1, + tdf5_filters_0_ce1, + tdf5_filters_0_d1, + tdf5_filters_0_q1, + tdf5_filters_0_we1, + tdf5_filters_1_address0, + tdf5_filters_1_ce0, + tdf5_filters_1_d0, + tdf5_filters_1_q0, + tdf5_filters_1_we0, + tdf5_filters_1_address1, + tdf5_filters_1_ce1, + tdf5_filters_1_d1, + tdf5_filters_1_q1, + tdf5_filters_1_we1, + tdf5_filters_2_address0, + tdf5_filters_2_ce0, + tdf5_filters_2_d0, + tdf5_filters_2_q0, + tdf5_filters_2_we0, + tdf5_filters_2_address1, + tdf5_filters_2_ce1, + tdf5_filters_2_d1, + tdf5_filters_2_q1, + tdf5_filters_2_we1, + tdf5_filters_3_address0, + tdf5_filters_3_ce0, + tdf5_filters_3_d0, + tdf5_filters_3_q0, + tdf5_filters_3_we0, + tdf5_filters_3_address1, + tdf5_filters_3_ce1, + tdf5_filters_3_d1, + tdf5_filters_3_q1, + tdf5_filters_3_we1, + tdf6_filters_address0, + tdf6_filters_ce0, + tdf6_filters_d0, + tdf6_filters_q0, + tdf6_filters_we0, + tdf6_filters_address1, + tdf6_filters_ce1, + tdf6_filters_d1, + tdf6_filters_q1, + tdf6_filters_we1, + tdf7_filters_0_address0, + tdf7_filters_0_ce0, + tdf7_filters_0_d0, + tdf7_filters_0_q0, + tdf7_filters_0_we0, + tdf7_filters_0_address1, + tdf7_filters_0_ce1, + tdf7_filters_0_d1, + tdf7_filters_0_q1, + tdf7_filters_0_we1, + tdf7_filters_1_address0, + tdf7_filters_1_ce0, + tdf7_filters_1_d0, + tdf7_filters_1_q0, + tdf7_filters_1_we0, + tdf7_filters_1_address1, + tdf7_filters_1_ce1, + tdf7_filters_1_d1, + tdf7_filters_1_q1, + tdf7_filters_1_we1, + tdf7_filters_2_address0, + tdf7_filters_2_ce0, + tdf7_filters_2_d0, + tdf7_filters_2_q0, + tdf7_filters_2_we0, + tdf7_filters_2_address1, + tdf7_filters_2_ce1, + tdf7_filters_2_d1, + tdf7_filters_2_q1, + tdf7_filters_2_we1, + tdf7_filters_3_address0, + tdf7_filters_3_ce0, + tdf7_filters_3_d0, + tdf7_filters_3_q0, + tdf7_filters_3_we0, + tdf7_filters_3_address1, + tdf7_filters_3_ce1, + tdf7_filters_3_d1, + tdf7_filters_3_q1, + tdf7_filters_3_we1, + tdf7_l2_filters_0_address0, + tdf7_l2_filters_0_ce0, + tdf7_l2_filters_0_d0, + tdf7_l2_filters_0_q0, + tdf7_l2_filters_0_we0, + tdf7_l2_filters_0_address1, + tdf7_l2_filters_0_ce1, + tdf7_l2_filters_0_d1, + tdf7_l2_filters_0_q1, + tdf7_l2_filters_0_we1, + tdf7_l2_filters_1_address0, + tdf7_l2_filters_1_ce0, + tdf7_l2_filters_1_d0, + tdf7_l2_filters_1_q0, + tdf7_l2_filters_1_we0, + tdf7_l2_filters_1_address1, + tdf7_l2_filters_1_ce1, + tdf7_l2_filters_1_d1, + tdf7_l2_filters_1_q1, + tdf7_l2_filters_1_we1, + tdf8_filters_0_address0, + tdf8_filters_0_ce0, + tdf8_filters_0_d0, + tdf8_filters_0_q0, + tdf8_filters_0_we0, + tdf8_filters_0_address1, + tdf8_filters_0_ce1, + tdf8_filters_0_d1, + tdf8_filters_0_q1, + tdf8_filters_0_we1, + tdf8_filters_1_address0, + tdf8_filters_1_ce0, + tdf8_filters_1_d0, + tdf8_filters_1_q0, + tdf8_filters_1_we0, + tdf8_filters_1_address1, + tdf8_filters_1_ce1, + tdf8_filters_1_d1, + tdf8_filters_1_q1, + tdf8_filters_1_we1, + tdf8_filters_2_address0, + tdf8_filters_2_ce0, + tdf8_filters_2_d0, + tdf8_filters_2_q0, + tdf8_filters_2_we0, + tdf8_filters_2_address1, + tdf8_filters_2_ce1, + tdf8_filters_2_d1, + tdf8_filters_2_q1, + tdf8_filters_2_we1, + tdf8_filters_3_address0, + tdf8_filters_3_ce0, + tdf8_filters_3_d0, + tdf8_filters_3_q0, + tdf8_filters_3_we0, + tdf8_filters_3_address1, + tdf8_filters_3_ce1, + tdf8_filters_3_d1, + tdf8_filters_3_q1, + tdf8_filters_3_we1, + tdf9_filters_address0, + tdf9_filters_ce0, + tdf9_filters_d0, + tdf9_filters_q0, + tdf9_filters_we0, + tdf9_filters_address1, + tdf9_filters_ce1, + tdf9_filters_d1, + tdf9_filters_q1, + tdf9_filters_we1, + tdf10_filters_0_address0, + tdf10_filters_0_ce0, + tdf10_filters_0_d0, + tdf10_filters_0_q0, + tdf10_filters_0_we0, + tdf10_filters_0_address1, + tdf10_filters_0_ce1, + tdf10_filters_0_d1, + tdf10_filters_0_q1, + tdf10_filters_0_we1, + tdf10_filters_1_address0, + tdf10_filters_1_ce0, + tdf10_filters_1_d0, + tdf10_filters_1_q0, + tdf10_filters_1_we0, + tdf10_filters_1_address1, + tdf10_filters_1_ce1, + tdf10_filters_1_d1, + tdf10_filters_1_q1, + tdf10_filters_1_we1, + tdf10_filters_2_address0, + tdf10_filters_2_ce0, + tdf10_filters_2_d0, + tdf10_filters_2_q0, + tdf10_filters_2_we0, + tdf10_filters_2_address1, + tdf10_filters_2_ce1, + tdf10_filters_2_d1, + tdf10_filters_2_q1, + tdf10_filters_2_we1, + tdf10_filters_3_address0, + tdf10_filters_3_ce0, + tdf10_filters_3_d0, + tdf10_filters_3_q0, + tdf10_filters_3_we0, + tdf10_filters_3_address1, + tdf10_filters_3_ce1, + tdf10_filters_3_d1, + tdf10_filters_3_q1, + tdf10_filters_3_we1, + tdf10_l2_filters_0_address0, + tdf10_l2_filters_0_ce0, + tdf10_l2_filters_0_d0, + tdf10_l2_filters_0_q0, + tdf10_l2_filters_0_we0, + tdf10_l2_filters_0_address1, + tdf10_l2_filters_0_ce1, + tdf10_l2_filters_0_d1, + tdf10_l2_filters_0_q1, + tdf10_l2_filters_0_we1, + tdf10_l2_filters_1_address0, + tdf10_l2_filters_1_ce0, + tdf10_l2_filters_1_d0, + tdf10_l2_filters_1_q0, + tdf10_l2_filters_1_we0, + tdf10_l2_filters_1_address1, + tdf10_l2_filters_1_ce1, + tdf10_l2_filters_1_d1, + tdf10_l2_filters_1_q1, + tdf10_l2_filters_1_we1, + tdf11_filters_0_address0, + tdf11_filters_0_ce0, + tdf11_filters_0_d0, + tdf11_filters_0_q0, + tdf11_filters_0_we0, + tdf11_filters_0_address1, + tdf11_filters_0_ce1, + tdf11_filters_0_d1, + tdf11_filters_0_q1, + tdf11_filters_0_we1, + tdf11_filters_1_address0, + tdf11_filters_1_ce0, + tdf11_filters_1_d0, + tdf11_filters_1_q0, + tdf11_filters_1_we0, + tdf11_filters_1_address1, + tdf11_filters_1_ce1, + tdf11_filters_1_d1, + tdf11_filters_1_q1, + tdf11_filters_1_we1, + tdf11_filters_2_address0, + tdf11_filters_2_ce0, + tdf11_filters_2_d0, + tdf11_filters_2_q0, + tdf11_filters_2_we0, + tdf11_filters_2_address1, + tdf11_filters_2_ce1, + tdf11_filters_2_d1, + tdf11_filters_2_q1, + tdf11_filters_2_we1, + tdf11_filters_3_address0, + tdf11_filters_3_ce0, + tdf11_filters_3_d0, + tdf11_filters_3_q0, + tdf11_filters_3_we0, + tdf11_filters_3_address1, + tdf11_filters_3_ce1, + tdf11_filters_3_d1, + tdf11_filters_3_q1, + tdf11_filters_3_we1, + tdf11_l2_filters_0_address0, + tdf11_l2_filters_0_ce0, + tdf11_l2_filters_0_d0, + tdf11_l2_filters_0_q0, + tdf11_l2_filters_0_we0, + tdf11_l2_filters_0_address1, + tdf11_l2_filters_0_ce1, + tdf11_l2_filters_0_d1, + tdf11_l2_filters_0_q1, + tdf11_l2_filters_0_we1, + tdf11_l2_filters_1_address0, + tdf11_l2_filters_1_ce0, + tdf11_l2_filters_1_d0, + tdf11_l2_filters_1_q0, + tdf11_l2_filters_1_we0, + tdf11_l2_filters_1_address1, + tdf11_l2_filters_1_ce1, + tdf11_l2_filters_1_d1, + tdf11_l2_filters_1_q1, + tdf11_l2_filters_1_we1, + tdf11_l2_filters_2_address0, + tdf11_l2_filters_2_ce0, + tdf11_l2_filters_2_d0, + tdf11_l2_filters_2_q0, + tdf11_l2_filters_2_we0, + tdf11_l2_filters_2_address1, + tdf11_l2_filters_2_ce1, + tdf11_l2_filters_2_d1, + tdf11_l2_filters_2_q1, + tdf11_l2_filters_2_we1, + tdf11_l2_filters_3_address0, + tdf11_l2_filters_3_ce0, + tdf11_l2_filters_3_d0, + tdf11_l2_filters_3_q0, + tdf11_l2_filters_3_we0, + tdf11_l2_filters_3_address1, + tdf11_l2_filters_3_ce1, + tdf11_l2_filters_3_d1, + tdf11_l2_filters_3_q1, + tdf11_l2_filters_3_we1, + tdf12_filters_0_address0, + tdf12_filters_0_ce0, + tdf12_filters_0_d0, + tdf12_filters_0_q0, + tdf12_filters_0_we0, + tdf12_filters_0_address1, + tdf12_filters_0_ce1, + tdf12_filters_0_d1, + tdf12_filters_0_q1, + tdf12_filters_0_we1, + tdf12_filters_1_address0, + tdf12_filters_1_ce0, + tdf12_filters_1_d0, + tdf12_filters_1_q0, + tdf12_filters_1_we0, + tdf12_filters_1_address1, + tdf12_filters_1_ce1, + tdf12_filters_1_d1, + tdf12_filters_1_q1, + tdf12_filters_1_we1, + tdf1_adjustments_address0, + tdf1_adjustments_ce0, + tdf1_adjustments_d0, + tdf1_adjustments_q0, + tdf1_adjustments_we0, + tdf1_adjustments_address1, + tdf1_adjustments_ce1, + tdf1_adjustments_d1, + tdf1_adjustments_q1, + tdf1_adjustments_we1, + tdf2_adjustments_address0, + tdf2_adjustments_ce0, + tdf2_adjustments_d0, + tdf2_adjustments_q0, + tdf2_adjustments_we0, + tdf2_adjustments_address1, + tdf2_adjustments_ce1, + tdf2_adjustments_d1, + tdf2_adjustments_q1, + tdf2_adjustments_we1, + tdf3_adjustments_address0, + tdf3_adjustments_ce0, + tdf3_adjustments_d0, + tdf3_adjustments_q0, + tdf3_adjustments_we0, + tdf3_adjustments_address1, + tdf3_adjustments_ce1, + tdf3_adjustments_d1, + tdf3_adjustments_q1, + tdf3_adjustments_we1, + tdf4_adjustments_address0, + tdf4_adjustments_ce0, + tdf4_adjustments_d0, + tdf4_adjustments_q0, + tdf4_adjustments_we0, + tdf4_adjustments_address1, + tdf4_adjustments_ce1, + tdf4_adjustments_d1, + tdf4_adjustments_q1, + tdf4_adjustments_we1, + tdf4_l2_adjustments_address0, + tdf4_l2_adjustments_ce0, + tdf4_l2_adjustments_d0, + tdf4_l2_adjustments_q0, + tdf4_l2_adjustments_we0, + tdf4_l2_adjustments_address1, + tdf4_l2_adjustments_ce1, + tdf4_l2_adjustments_d1, + tdf4_l2_adjustments_q1, + tdf4_l2_adjustments_we1, + tdf5_adjustments_address0, + tdf5_adjustments_ce0, + tdf5_adjustments_d0, + tdf5_adjustments_q0, + tdf5_adjustments_we0, + tdf5_adjustments_address1, + tdf5_adjustments_ce1, + tdf5_adjustments_d1, + tdf5_adjustments_q1, + tdf5_adjustments_we1, + tdf6_adjustments_address0, + tdf6_adjustments_ce0, + tdf6_adjustments_d0, + tdf6_adjustments_q0, + tdf6_adjustments_we0, + tdf6_adjustments_address1, + tdf6_adjustments_ce1, + tdf6_adjustments_d1, + tdf6_adjustments_q1, + tdf6_adjustments_we1, + tdf7_adjustments_address0, + tdf7_adjustments_ce0, + tdf7_adjustments_d0, + tdf7_adjustments_q0, + tdf7_adjustments_we0, + tdf7_adjustments_address1, + tdf7_adjustments_ce1, + tdf7_adjustments_d1, + tdf7_adjustments_q1, + tdf7_adjustments_we1, + tdf7_l2_adjustments_address0, + tdf7_l2_adjustments_ce0, + tdf7_l2_adjustments_d0, + tdf7_l2_adjustments_q0, + tdf7_l2_adjustments_we0, + tdf7_l2_adjustments_address1, + tdf7_l2_adjustments_ce1, + tdf7_l2_adjustments_d1, + tdf7_l2_adjustments_q1, + tdf7_l2_adjustments_we1, + tdf8_adjustments_address0, + tdf8_adjustments_ce0, + tdf8_adjustments_d0, + tdf8_adjustments_q0, + tdf8_adjustments_we0, + tdf8_adjustments_address1, + tdf8_adjustments_ce1, + tdf8_adjustments_d1, + tdf8_adjustments_q1, + tdf8_adjustments_we1, + tdf9_adjustments_address0, + tdf9_adjustments_ce0, + tdf9_adjustments_d0, + tdf9_adjustments_q0, + tdf9_adjustments_we0, + tdf9_adjustments_address1, + tdf9_adjustments_ce1, + tdf9_adjustments_d1, + tdf9_adjustments_q1, + tdf9_adjustments_we1, + tdf10_adjustments_address0, + tdf10_adjustments_ce0, + tdf10_adjustments_d0, + tdf10_adjustments_q0, + tdf10_adjustments_we0, + tdf10_adjustments_address1, + tdf10_adjustments_ce1, + tdf10_adjustments_d1, + tdf10_adjustments_q1, + tdf10_adjustments_we1, + tdf10_l2_adjustments_address0, + tdf10_l2_adjustments_ce0, + tdf10_l2_adjustments_d0, + tdf10_l2_adjustments_q0, + tdf10_l2_adjustments_we0, + tdf10_l2_adjustments_address1, + tdf10_l2_adjustments_ce1, + tdf10_l2_adjustments_d1, + tdf10_l2_adjustments_q1, + tdf10_l2_adjustments_we1, + tdf11_adjustments_address0, + tdf11_adjustments_ce0, + tdf11_adjustments_d0, + tdf11_adjustments_q0, + tdf11_adjustments_we0, + tdf11_adjustments_address1, + tdf11_adjustments_ce1, + tdf11_adjustments_d1, + tdf11_adjustments_q1, + tdf11_adjustments_we1, + tdf11_l2_adjustments_address0, + tdf11_l2_adjustments_ce0, + tdf11_l2_adjustments_d0, + tdf11_l2_adjustments_q0, + tdf11_l2_adjustments_we0, + tdf11_l2_adjustments_address1, + tdf11_l2_adjustments_ce1, + tdf11_l2_adjustments_d1, + tdf11_l2_adjustments_q1, + tdf11_l2_adjustments_we1, + tdf12_adjustments_address0, + tdf12_adjustments_ce0, + tdf12_adjustments_d0, + tdf12_adjustments_q0, + tdf12_adjustments_we0, + tdf12_adjustments_address1, + tdf12_adjustments_ce1, + tdf12_adjustments_d1, + tdf12_adjustments_q1, + tdf12_adjustments_we1, + stream_in_TDATA, + stream_in_TKEEP, + stream_in_TSTRB, + stream_in_TLAST, + stream_out_TDATA, + stream_out_TKEEP, + stream_out_TSTRB, + stream_out_TLAST, + stream_in_TVALID, + stream_in_TREADY, + ap_start, + stream_out_TVALID, + stream_out_TREADY, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +input ap_clk; +input ap_rst; +output [6:0] tdf1_filters_0_address0; +output tdf1_filters_0_ce0; +output [15:0] tdf1_filters_0_d0; +input [15:0] tdf1_filters_0_q0; +output tdf1_filters_0_we0; +output [6:0] tdf1_filters_0_address1; +output tdf1_filters_0_ce1; +output [15:0] tdf1_filters_0_d1; +input [15:0] tdf1_filters_0_q1; +output tdf1_filters_0_we1; +output [6:0] tdf1_filters_1_address0; +output tdf1_filters_1_ce0; +output [15:0] tdf1_filters_1_d0; +input [15:0] tdf1_filters_1_q0; +output tdf1_filters_1_we0; +output [6:0] tdf1_filters_1_address1; +output tdf1_filters_1_ce1; +output [15:0] tdf1_filters_1_d1; +input [15:0] tdf1_filters_1_q1; +output tdf1_filters_1_we1; +output [6:0] tdf1_filters_2_address0; +output tdf1_filters_2_ce0; +output [15:0] tdf1_filters_2_d0; +input [15:0] tdf1_filters_2_q0; +output tdf1_filters_2_we0; +output [6:0] tdf1_filters_2_address1; +output tdf1_filters_2_ce1; +output [15:0] tdf1_filters_2_d1; +input [15:0] tdf1_filters_2_q1; +output tdf1_filters_2_we1; +output [6:0] tdf1_filters_3_address0; +output tdf1_filters_3_ce0; +output [15:0] tdf1_filters_3_d0; +input [15:0] tdf1_filters_3_q0; +output tdf1_filters_3_we0; +output [6:0] tdf1_filters_3_address1; +output tdf1_filters_3_ce1; +output [15:0] tdf1_filters_3_d1; +input [15:0] tdf1_filters_3_q1; +output tdf1_filters_3_we1; +output [9:0] tdf2_filters_0_address0; +output tdf2_filters_0_ce0; +output [31:0] tdf2_filters_0_d0; +input [31:0] tdf2_filters_0_q0; +output tdf2_filters_0_we0; +output [9:0] tdf2_filters_0_address1; +output tdf2_filters_0_ce1; +output [31:0] tdf2_filters_0_d1; +input [31:0] tdf2_filters_0_q1; +output tdf2_filters_0_we1; +output [9:0] tdf2_filters_1_address0; +output tdf2_filters_1_ce0; +output [31:0] tdf2_filters_1_d0; +input [31:0] tdf2_filters_1_q0; +output tdf2_filters_1_we0; +output [9:0] tdf2_filters_1_address1; +output tdf2_filters_1_ce1; +output [31:0] tdf2_filters_1_d1; +input [31:0] tdf2_filters_1_q1; +output tdf2_filters_1_we1; +output [9:0] tdf2_filters_2_address0; +output tdf2_filters_2_ce0; +output [31:0] tdf2_filters_2_d0; +input [31:0] tdf2_filters_2_q0; +output tdf2_filters_2_we0; +output [9:0] tdf2_filters_2_address1; +output tdf2_filters_2_ce1; +output [31:0] tdf2_filters_2_d1; +input [31:0] tdf2_filters_2_q1; +output tdf2_filters_2_we1; +output [9:0] tdf2_filters_3_address0; +output tdf2_filters_3_ce0; +output [31:0] tdf2_filters_3_d0; +input [31:0] tdf2_filters_3_q0; +output tdf2_filters_3_we0; +output [9:0] tdf2_filters_3_address1; +output tdf2_filters_3_ce1; +output [31:0] tdf2_filters_3_d1; +input [31:0] tdf2_filters_3_q1; +output tdf2_filters_3_we1; +output [8:0] tdf3_filters_address0; +output tdf3_filters_ce0; +output [15:0] tdf3_filters_d0; +input [15:0] tdf3_filters_q0; +output tdf3_filters_we0; +output [8:0] tdf3_filters_address1; +output tdf3_filters_ce1; +output [15:0] tdf3_filters_d1; +input [15:0] tdf3_filters_q1; +output tdf3_filters_we1; +output [10:0] tdf4_filters_0_address0; +output tdf4_filters_0_ce0; +output [63:0] tdf4_filters_0_d0; +input [63:0] tdf4_filters_0_q0; +output tdf4_filters_0_we0; +output [10:0] tdf4_filters_0_address1; +output tdf4_filters_0_ce1; +output [63:0] tdf4_filters_0_d1; +input [63:0] tdf4_filters_0_q1; +output tdf4_filters_0_we1; +output [10:0] tdf4_filters_1_address0; +output tdf4_filters_1_ce0; +output [63:0] tdf4_filters_1_d0; +input [63:0] tdf4_filters_1_q0; +output tdf4_filters_1_we0; +output [10:0] tdf4_filters_1_address1; +output tdf4_filters_1_ce1; +output [63:0] tdf4_filters_1_d1; +input [63:0] tdf4_filters_1_q1; +output tdf4_filters_1_we1; +output [10:0] tdf4_filters_2_address0; +output tdf4_filters_2_ce0; +output [63:0] tdf4_filters_2_d0; +input [63:0] tdf4_filters_2_q0; +output tdf4_filters_2_we0; +output [10:0] tdf4_filters_2_address1; +output tdf4_filters_2_ce1; +output [63:0] tdf4_filters_2_d1; +input [63:0] tdf4_filters_2_q1; +output tdf4_filters_2_we1; +output [10:0] tdf4_filters_3_address0; +output tdf4_filters_3_ce0; +output [63:0] tdf4_filters_3_d0; +input [63:0] tdf4_filters_3_q0; +output tdf4_filters_3_we0; +output [10:0] tdf4_filters_3_address1; +output tdf4_filters_3_ce1; +output [63:0] tdf4_filters_3_d1; +input [63:0] tdf4_filters_3_q1; +output tdf4_filters_3_we1; +output [9:0] tdf4_l2_filters_0_address0; +output tdf4_l2_filters_0_ce0; +output [15:0] tdf4_l2_filters_0_d0; +input [15:0] tdf4_l2_filters_0_q0; +output tdf4_l2_filters_0_we0; +output [9:0] tdf4_l2_filters_0_address1; +output tdf4_l2_filters_0_ce1; +output [15:0] tdf4_l2_filters_0_d1; +input [15:0] tdf4_l2_filters_0_q1; +output tdf4_l2_filters_0_we1; +output [9:0] tdf4_l2_filters_1_address0; +output tdf4_l2_filters_1_ce0; +output [15:0] tdf4_l2_filters_1_d0; +input [15:0] tdf4_l2_filters_1_q0; +output tdf4_l2_filters_1_we0; +output [9:0] tdf4_l2_filters_1_address1; +output tdf4_l2_filters_1_ce1; +output [15:0] tdf4_l2_filters_1_d1; +input [15:0] tdf4_l2_filters_1_q1; +output tdf4_l2_filters_1_we1; +output [11:0] tdf5_filters_0_address0; +output tdf5_filters_0_ce0; +output [31:0] tdf5_filters_0_d0; +input [31:0] tdf5_filters_0_q0; +output tdf5_filters_0_we0; +output [11:0] tdf5_filters_0_address1; +output tdf5_filters_0_ce1; +output [31:0] tdf5_filters_0_d1; +input [31:0] tdf5_filters_0_q1; +output tdf5_filters_0_we1; +output [11:0] tdf5_filters_1_address0; +output tdf5_filters_1_ce0; +output [31:0] tdf5_filters_1_d0; +input [31:0] tdf5_filters_1_q0; +output tdf5_filters_1_we0; +output [11:0] tdf5_filters_1_address1; +output tdf5_filters_1_ce1; +output [31:0] tdf5_filters_1_d1; +input [31:0] tdf5_filters_1_q1; +output tdf5_filters_1_we1; +output [11:0] tdf5_filters_2_address0; +output tdf5_filters_2_ce0; +output [31:0] tdf5_filters_2_d0; +input [31:0] tdf5_filters_2_q0; +output tdf5_filters_2_we0; +output [11:0] tdf5_filters_2_address1; +output tdf5_filters_2_ce1; +output [31:0] tdf5_filters_2_d1; +input [31:0] tdf5_filters_2_q1; +output tdf5_filters_2_we1; +output [11:0] tdf5_filters_3_address0; +output tdf5_filters_3_ce0; +output [31:0] tdf5_filters_3_d0; +input [31:0] tdf5_filters_3_q0; +output tdf5_filters_3_we0; +output [11:0] tdf5_filters_3_address1; +output tdf5_filters_3_ce1; +output [31:0] tdf5_filters_3_d1; +input [31:0] tdf5_filters_3_q1; +output tdf5_filters_3_we1; +output [11:0] tdf6_filters_address0; +output tdf6_filters_ce0; +output [15:0] tdf6_filters_d0; +input [15:0] tdf6_filters_q0; +output tdf6_filters_we0; +output [11:0] tdf6_filters_address1; +output tdf6_filters_ce1; +output [15:0] tdf6_filters_d1; +input [15:0] tdf6_filters_q1; +output tdf6_filters_we1; +output [12:0] tdf7_filters_0_address0; +output tdf7_filters_0_ce0; +output [63:0] tdf7_filters_0_d0; +input [63:0] tdf7_filters_0_q0; +output tdf7_filters_0_we0; +output [12:0] tdf7_filters_0_address1; +output tdf7_filters_0_ce1; +output [63:0] tdf7_filters_0_d1; +input [63:0] tdf7_filters_0_q1; +output tdf7_filters_0_we1; +output [12:0] tdf7_filters_1_address0; +output tdf7_filters_1_ce0; +output [63:0] tdf7_filters_1_d0; +input [63:0] tdf7_filters_1_q0; +output tdf7_filters_1_we0; +output [12:0] tdf7_filters_1_address1; +output tdf7_filters_1_ce1; +output [63:0] tdf7_filters_1_d1; +input [63:0] tdf7_filters_1_q1; +output tdf7_filters_1_we1; +output [12:0] tdf7_filters_2_address0; +output tdf7_filters_2_ce0; +output [63:0] tdf7_filters_2_d0; +input [63:0] tdf7_filters_2_q0; +output tdf7_filters_2_we0; +output [12:0] tdf7_filters_2_address1; +output tdf7_filters_2_ce1; +output [63:0] tdf7_filters_2_d1; +input [63:0] tdf7_filters_2_q1; +output tdf7_filters_2_we1; +output [12:0] tdf7_filters_3_address0; +output tdf7_filters_3_ce0; +output [63:0] tdf7_filters_3_d0; +input [63:0] tdf7_filters_3_q0; +output tdf7_filters_3_we0; +output [12:0] tdf7_filters_3_address1; +output tdf7_filters_3_ce1; +output [63:0] tdf7_filters_3_d1; +input [63:0] tdf7_filters_3_q1; +output tdf7_filters_3_we1; +output [11:0] tdf7_l2_filters_0_address0; +output tdf7_l2_filters_0_ce0; +output [15:0] tdf7_l2_filters_0_d0; +input [15:0] tdf7_l2_filters_0_q0; +output tdf7_l2_filters_0_we0; +output [11:0] tdf7_l2_filters_0_address1; +output tdf7_l2_filters_0_ce1; +output [15:0] tdf7_l2_filters_0_d1; +input [15:0] tdf7_l2_filters_0_q1; +output tdf7_l2_filters_0_we1; +output [11:0] tdf7_l2_filters_1_address0; +output tdf7_l2_filters_1_ce0; +output [15:0] tdf7_l2_filters_1_d0; +input [15:0] tdf7_l2_filters_1_q0; +output tdf7_l2_filters_1_we0; +output [11:0] tdf7_l2_filters_1_address1; +output tdf7_l2_filters_1_ce1; +output [15:0] tdf7_l2_filters_1_d1; +input [15:0] tdf7_l2_filters_1_q1; +output tdf7_l2_filters_1_we1; +output [13:0] tdf8_filters_0_address0; +output tdf8_filters_0_ce0; +output [31:0] tdf8_filters_0_d0; +input [31:0] tdf8_filters_0_q0; +output tdf8_filters_0_we0; +output [13:0] tdf8_filters_0_address1; +output tdf8_filters_0_ce1; +output [31:0] tdf8_filters_0_d1; +input [31:0] tdf8_filters_0_q1; +output tdf8_filters_0_we1; +output [13:0] tdf8_filters_1_address0; +output tdf8_filters_1_ce0; +output [31:0] tdf8_filters_1_d0; +input [31:0] tdf8_filters_1_q0; +output tdf8_filters_1_we0; +output [13:0] tdf8_filters_1_address1; +output tdf8_filters_1_ce1; +output [31:0] tdf8_filters_1_d1; +input [31:0] tdf8_filters_1_q1; +output tdf8_filters_1_we1; +output [13:0] tdf8_filters_2_address0; +output tdf8_filters_2_ce0; +output [31:0] tdf8_filters_2_d0; +input [31:0] tdf8_filters_2_q0; +output tdf8_filters_2_we0; +output [13:0] tdf8_filters_2_address1; +output tdf8_filters_2_ce1; +output [31:0] tdf8_filters_2_d1; +input [31:0] tdf8_filters_2_q1; +output tdf8_filters_2_we1; +output [13:0] tdf8_filters_3_address0; +output tdf8_filters_3_ce0; +output [31:0] tdf8_filters_3_d0; +input [31:0] tdf8_filters_3_q0; +output tdf8_filters_3_we0; +output [13:0] tdf8_filters_3_address1; +output tdf8_filters_3_ce1; +output [31:0] tdf8_filters_3_d1; +input [31:0] tdf8_filters_3_q1; +output tdf8_filters_3_we1; +output [13:0] tdf9_filters_address0; +output tdf9_filters_ce0; +output [15:0] tdf9_filters_d0; +input [15:0] tdf9_filters_q0; +output tdf9_filters_we0; +output [13:0] tdf9_filters_address1; +output tdf9_filters_ce1; +output [15:0] tdf9_filters_d1; +input [15:0] tdf9_filters_q1; +output tdf9_filters_we1; +output [14:0] tdf10_filters_0_address0; +output tdf10_filters_0_ce0; +output [63:0] tdf10_filters_0_d0; +input [63:0] tdf10_filters_0_q0; +output tdf10_filters_0_we0; +output [14:0] tdf10_filters_0_address1; +output tdf10_filters_0_ce1; +output [63:0] tdf10_filters_0_d1; +input [63:0] tdf10_filters_0_q1; +output tdf10_filters_0_we1; +output [14:0] tdf10_filters_1_address0; +output tdf10_filters_1_ce0; +output [63:0] tdf10_filters_1_d0; +input [63:0] tdf10_filters_1_q0; +output tdf10_filters_1_we0; +output [14:0] tdf10_filters_1_address1; +output tdf10_filters_1_ce1; +output [63:0] tdf10_filters_1_d1; +input [63:0] tdf10_filters_1_q1; +output tdf10_filters_1_we1; +output [14:0] tdf10_filters_2_address0; +output tdf10_filters_2_ce0; +output [63:0] tdf10_filters_2_d0; +input [63:0] tdf10_filters_2_q0; +output tdf10_filters_2_we0; +output [14:0] tdf10_filters_2_address1; +output tdf10_filters_2_ce1; +output [63:0] tdf10_filters_2_d1; +input [63:0] tdf10_filters_2_q1; +output tdf10_filters_2_we1; +output [14:0] tdf10_filters_3_address0; +output tdf10_filters_3_ce0; +output [63:0] tdf10_filters_3_d0; +input [63:0] tdf10_filters_3_q0; +output tdf10_filters_3_we0; +output [14:0] tdf10_filters_3_address1; +output tdf10_filters_3_ce1; +output [63:0] tdf10_filters_3_d1; +input [63:0] tdf10_filters_3_q1; +output tdf10_filters_3_we1; +output [13:0] tdf10_l2_filters_0_address0; +output tdf10_l2_filters_0_ce0; +output [15:0] tdf10_l2_filters_0_d0; +input [15:0] tdf10_l2_filters_0_q0; +output tdf10_l2_filters_0_we0; +output [13:0] tdf10_l2_filters_0_address1; +output tdf10_l2_filters_0_ce1; +output [15:0] tdf10_l2_filters_0_d1; +input [15:0] tdf10_l2_filters_0_q1; +output tdf10_l2_filters_0_we1; +output [13:0] tdf10_l2_filters_1_address0; +output tdf10_l2_filters_1_ce0; +output [15:0] tdf10_l2_filters_1_d0; +input [15:0] tdf10_l2_filters_1_q0; +output tdf10_l2_filters_1_we0; +output [13:0] tdf10_l2_filters_1_address1; +output tdf10_l2_filters_1_ce1; +output [15:0] tdf10_l2_filters_1_d1; +input [15:0] tdf10_l2_filters_1_q1; +output tdf10_l2_filters_1_we1; +output [14:0] tdf11_filters_0_address0; +output tdf11_filters_0_ce0; +output [63:0] tdf11_filters_0_d0; +input [63:0] tdf11_filters_0_q0; +output tdf11_filters_0_we0; +output [14:0] tdf11_filters_0_address1; +output tdf11_filters_0_ce1; +output [63:0] tdf11_filters_0_d1; +input [63:0] tdf11_filters_0_q1; +output tdf11_filters_0_we1; +output [14:0] tdf11_filters_1_address0; +output tdf11_filters_1_ce0; +output [63:0] tdf11_filters_1_d0; +input [63:0] tdf11_filters_1_q0; +output tdf11_filters_1_we0; +output [14:0] tdf11_filters_1_address1; +output tdf11_filters_1_ce1; +output [63:0] tdf11_filters_1_d1; +input [63:0] tdf11_filters_1_q1; +output tdf11_filters_1_we1; +output [14:0] tdf11_filters_2_address0; +output tdf11_filters_2_ce0; +output [63:0] tdf11_filters_2_d0; +input [63:0] tdf11_filters_2_q0; +output tdf11_filters_2_we0; +output [14:0] tdf11_filters_2_address1; +output tdf11_filters_2_ce1; +output [63:0] tdf11_filters_2_d1; +input [63:0] tdf11_filters_2_q1; +output tdf11_filters_2_we1; +output [14:0] tdf11_filters_3_address0; +output tdf11_filters_3_ce0; +output [63:0] tdf11_filters_3_d0; +input [63:0] tdf11_filters_3_q0; +output tdf11_filters_3_we0; +output [14:0] tdf11_filters_3_address1; +output tdf11_filters_3_ce1; +output [63:0] tdf11_filters_3_d1; +input [63:0] tdf11_filters_3_q1; +output tdf11_filters_3_we1; +output [13:0] tdf11_l2_filters_0_address0; +output tdf11_l2_filters_0_ce0; +output [15:0] tdf11_l2_filters_0_d0; +input [15:0] tdf11_l2_filters_0_q0; +output tdf11_l2_filters_0_we0; +output [13:0] tdf11_l2_filters_0_address1; +output tdf11_l2_filters_0_ce1; +output [15:0] tdf11_l2_filters_0_d1; +input [15:0] tdf11_l2_filters_0_q1; +output tdf11_l2_filters_0_we1; +output [13:0] tdf11_l2_filters_1_address0; +output tdf11_l2_filters_1_ce0; +output [15:0] tdf11_l2_filters_1_d0; +input [15:0] tdf11_l2_filters_1_q0; +output tdf11_l2_filters_1_we0; +output [13:0] tdf11_l2_filters_1_address1; +output tdf11_l2_filters_1_ce1; +output [15:0] tdf11_l2_filters_1_d1; +input [15:0] tdf11_l2_filters_1_q1; +output tdf11_l2_filters_1_we1; +output [13:0] tdf11_l2_filters_2_address0; +output tdf11_l2_filters_2_ce0; +output [15:0] tdf11_l2_filters_2_d0; +input [15:0] tdf11_l2_filters_2_q0; +output tdf11_l2_filters_2_we0; +output [13:0] tdf11_l2_filters_2_address1; +output tdf11_l2_filters_2_ce1; +output [15:0] tdf11_l2_filters_2_d1; +input [15:0] tdf11_l2_filters_2_q1; +output tdf11_l2_filters_2_we1; +output [13:0] tdf11_l2_filters_3_address0; +output tdf11_l2_filters_3_ce0; +output [15:0] tdf11_l2_filters_3_d0; +input [15:0] tdf11_l2_filters_3_q0; +output tdf11_l2_filters_3_we0; +output [13:0] tdf11_l2_filters_3_address1; +output tdf11_l2_filters_3_ce1; +output [15:0] tdf11_l2_filters_3_d1; +input [15:0] tdf11_l2_filters_3_q1; +output tdf11_l2_filters_3_we1; +output [14:0] tdf12_filters_0_address0; +output tdf12_filters_0_ce0; +output [31:0] tdf12_filters_0_d0; +input [31:0] tdf12_filters_0_q0; +output tdf12_filters_0_we0; +output [14:0] tdf12_filters_0_address1; +output tdf12_filters_0_ce1; +output [31:0] tdf12_filters_0_d1; +input [31:0] tdf12_filters_0_q1; +output tdf12_filters_0_we1; +output [14:0] tdf12_filters_1_address0; +output tdf12_filters_1_ce0; +output [31:0] tdf12_filters_1_d0; +input [31:0] tdf12_filters_1_q0; +output tdf12_filters_1_we0; +output [14:0] tdf12_filters_1_address1; +output tdf12_filters_1_ce1; +output [31:0] tdf12_filters_1_d1; +input [31:0] tdf12_filters_1_q1; +output tdf12_filters_1_we1; +output [3:0] tdf1_adjustments_address0; +output tdf1_adjustments_ce0; +output [47:0] tdf1_adjustments_d0; +input [47:0] tdf1_adjustments_q0; +output tdf1_adjustments_we0; +output [3:0] tdf1_adjustments_address1; +output tdf1_adjustments_ce1; +output [47:0] tdf1_adjustments_d1; +input [47:0] tdf1_adjustments_q1; +output tdf1_adjustments_we1; +output [4:0] tdf2_adjustments_address0; +output tdf2_adjustments_ce0; +output [47:0] tdf2_adjustments_d0; +input [47:0] tdf2_adjustments_q0; +output tdf2_adjustments_we0; +output [4:0] tdf2_adjustments_address1; +output tdf2_adjustments_ce1; +output [47:0] tdf2_adjustments_d1; +input [47:0] tdf2_adjustments_q1; +output tdf2_adjustments_we1; +output [3:0] tdf3_adjustments_address0; +output tdf3_adjustments_ce0; +output [47:0] tdf3_adjustments_d0; +input [47:0] tdf3_adjustments_q0; +output tdf3_adjustments_we0; +output [3:0] tdf3_adjustments_address1; +output tdf3_adjustments_ce1; +output [47:0] tdf3_adjustments_d1; +input [47:0] tdf3_adjustments_q1; +output tdf3_adjustments_we1; +output [6:0] tdf4_adjustments_address0; +output tdf4_adjustments_ce0; +output [47:0] tdf4_adjustments_d0; +input [47:0] tdf4_adjustments_q0; +output tdf4_adjustments_we0; +output [6:0] tdf4_adjustments_address1; +output tdf4_adjustments_ce1; +output [47:0] tdf4_adjustments_d1; +input [47:0] tdf4_adjustments_q1; +output tdf4_adjustments_we1; +output [3:0] tdf4_l2_adjustments_address0; +output tdf4_l2_adjustments_ce0; +output [47:0] tdf4_l2_adjustments_d0; +input [47:0] tdf4_l2_adjustments_q0; +output tdf4_l2_adjustments_we0; +output [3:0] tdf4_l2_adjustments_address1; +output tdf4_l2_adjustments_ce1; +output [47:0] tdf4_l2_adjustments_d1; +input [47:0] tdf4_l2_adjustments_q1; +output tdf4_l2_adjustments_we1; +output [6:0] tdf5_adjustments_address0; +output tdf5_adjustments_ce0; +output [47:0] tdf5_adjustments_d0; +input [47:0] tdf5_adjustments_q0; +output tdf5_adjustments_we0; +output [6:0] tdf5_adjustments_address1; +output tdf5_adjustments_ce1; +output [47:0] tdf5_adjustments_d1; +input [47:0] tdf5_adjustments_q1; +output tdf5_adjustments_we1; +output [4:0] tdf6_adjustments_address0; +output tdf6_adjustments_ce0; +output [47:0] tdf6_adjustments_d0; +input [47:0] tdf6_adjustments_q0; +output tdf6_adjustments_we0; +output [4:0] tdf6_adjustments_address1; +output tdf6_adjustments_ce1; +output [47:0] tdf6_adjustments_d1; +input [47:0] tdf6_adjustments_q1; +output tdf6_adjustments_we1; +output [7:0] tdf7_adjustments_address0; +output tdf7_adjustments_ce0; +output [47:0] tdf7_adjustments_d0; +input [47:0] tdf7_adjustments_q0; +output tdf7_adjustments_we0; +output [7:0] tdf7_adjustments_address1; +output tdf7_adjustments_ce1; +output [47:0] tdf7_adjustments_d1; +input [47:0] tdf7_adjustments_q1; +output tdf7_adjustments_we1; +output [4:0] tdf7_l2_adjustments_address0; +output tdf7_l2_adjustments_ce0; +output [47:0] tdf7_l2_adjustments_d0; +input [47:0] tdf7_l2_adjustments_q0; +output tdf7_l2_adjustments_we0; +output [4:0] tdf7_l2_adjustments_address1; +output tdf7_l2_adjustments_ce1; +output [47:0] tdf7_l2_adjustments_d1; +input [47:0] tdf7_l2_adjustments_q1; +output tdf7_l2_adjustments_we1; +output [7:0] tdf8_adjustments_address0; +output tdf8_adjustments_ce0; +output [47:0] tdf8_adjustments_d0; +input [47:0] tdf8_adjustments_q0; +output tdf8_adjustments_we0; +output [7:0] tdf8_adjustments_address1; +output tdf8_adjustments_ce1; +output [47:0] tdf8_adjustments_d1; +input [47:0] tdf8_adjustments_q1; +output tdf8_adjustments_we1; +output [5:0] tdf9_adjustments_address0; +output tdf9_adjustments_ce0; +output [47:0] tdf9_adjustments_d0; +input [47:0] tdf9_adjustments_q0; +output tdf9_adjustments_we0; +output [5:0] tdf9_adjustments_address1; +output tdf9_adjustments_ce1; +output [47:0] tdf9_adjustments_d1; +input [47:0] tdf9_adjustments_q1; +output tdf9_adjustments_we1; +output [8:0] tdf10_adjustments_address0; +output tdf10_adjustments_ce0; +output [47:0] tdf10_adjustments_d0; +input [47:0] tdf10_adjustments_q0; +output tdf10_adjustments_we0; +output [8:0] tdf10_adjustments_address1; +output tdf10_adjustments_ce1; +output [47:0] tdf10_adjustments_d1; +input [47:0] tdf10_adjustments_q1; +output tdf10_adjustments_we1; +output [5:0] tdf10_l2_adjustments_address0; +output tdf10_l2_adjustments_ce0; +output [47:0] tdf10_l2_adjustments_d0; +input [47:0] tdf10_l2_adjustments_q0; +output tdf10_l2_adjustments_we0; +output [5:0] tdf10_l2_adjustments_address1; +output tdf10_l2_adjustments_ce1; +output [47:0] tdf10_l2_adjustments_d1; +input [47:0] tdf10_l2_adjustments_q1; +output tdf10_l2_adjustments_we1; +output [8:0] tdf11_adjustments_address0; +output tdf11_adjustments_ce0; +output [47:0] tdf11_adjustments_d0; +input [47:0] tdf11_adjustments_q0; +output tdf11_adjustments_we0; +output [8:0] tdf11_adjustments_address1; +output tdf11_adjustments_ce1; +output [47:0] tdf11_adjustments_d1; +input [47:0] tdf11_adjustments_q1; +output tdf11_adjustments_we1; +output [6:0] tdf11_l2_adjustments_address0; +output tdf11_l2_adjustments_ce0; +output [47:0] tdf11_l2_adjustments_d0; +input [47:0] tdf11_l2_adjustments_q0; +output tdf11_l2_adjustments_we0; +output [6:0] tdf11_l2_adjustments_address1; +output tdf11_l2_adjustments_ce1; +output [47:0] tdf11_l2_adjustments_d1; +input [47:0] tdf11_l2_adjustments_q1; +output tdf11_l2_adjustments_we1; +output [9:0] tdf12_adjustments_address0; +output tdf12_adjustments_ce0; +output [47:0] tdf12_adjustments_d0; +input [47:0] tdf12_adjustments_q0; +output tdf12_adjustments_we0; +output [9:0] tdf12_adjustments_address1; +output tdf12_adjustments_ce1; +output [47:0] tdf12_adjustments_d1; +input [47:0] tdf12_adjustments_q1; +output tdf12_adjustments_we1; +input [15:0] stream_in_TDATA; +input [1:0] stream_in_TKEEP; +input [1:0] stream_in_TSTRB; +input [0:0] stream_in_TLAST; +output [15:0] stream_out_TDATA; +output [1:0] stream_out_TKEEP; +output [1:0] stream_out_TSTRB; +output [0:0] stream_out_TLAST; +input stream_in_TVALID; +output stream_in_TREADY; +input ap_start; +output stream_out_TVALID; +input stream_out_TREADY; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +wire [63:0] tdf1_fmaps_i_q0; +wire [63:0] tdf1_fmaps_t_q0; +wire [63:0] tdf2_fmaps_i_q0; +wire [63:0] tdf2_fmaps_t_q0; +wire [63:0] tdf3_fmaps_i_q0; +wire [63:0] tdf3_fmaps_t_q0; +wire [63:0] tdf4_fmaps_i_q0; +wire [63:0] tdf4_fmaps_t_q0; +wire [63:0] tdf5_fmaps_i_q0; +wire [63:0] tdf5_fmaps_t_q0; +wire [63:0] tdf6_fmaps_i_q0; +wire [63:0] tdf6_fmaps_t_q0; +wire [63:0] tdf7_fmaps_i_q0; +wire [63:0] tdf7_fmaps_t_q0; +wire [63:0] tdf8_fmaps_i_q0; +wire [63:0] tdf8_fmaps_t_q0; +wire [63:0] tdf9_fmaps_i_q0; +wire [63:0] tdf9_fmaps_t_q0; +wire [63:0] tdf10_fmaps_i_q0; +wire [63:0] tdf10_fmaps_t_q0; +wire [63:0] tdf11_fmaps_i_q0; +wire [63:0] tdf11_fmaps_t_q0; +wire [63:0] tdf12_fmaps_i_q0; +wire [63:0] tdf12_fmaps_t_q0; +wire [63:0] final_fmaps_i_q0; +wire [63:0] final_fmaps_t_q0; +wire td_fused_axi_in_U0_ap_start; +wire td_fused_axi_in_U0_ap_done; +wire td_fused_axi_in_U0_ap_continue; +wire td_fused_axi_in_U0_ap_idle; +wire td_fused_axi_in_U0_ap_ready; +wire td_fused_axi_in_U0_stream_in_TREADY; +wire [15:0] td_fused_axi_in_U0_fmaps_address1; +wire td_fused_axi_in_U0_fmaps_ce1; +wire td_fused_axi_in_U0_fmaps_we1; +wire [63:0] td_fused_axi_in_U0_fmaps_d1; +wire ap_channel_done_tdf1_fmaps; +wire td_fused_axi_in_U0_fmaps_full_n; +wire [15:0] tdf1_114_U0_in_data_address0; +wire tdf1_114_U0_in_data_ce0; +wire [63:0] tdf1_114_U0_in_data_d0; +wire tdf1_114_U0_in_data_we0; +wire [15:0] tdf1_114_U0_in_data_address1; +wire tdf1_114_U0_in_data_ce1; +wire [63:0] tdf1_114_U0_in_data_d1; +wire tdf1_114_U0_in_data_we1; +wire [15:0] tdf1_114_U0_out_data_address0; +wire tdf1_114_U0_out_data_ce0; +wire [63:0] tdf1_114_U0_out_data_d0; +wire tdf1_114_U0_out_data_we0; +wire [15:0] tdf1_114_U0_out_data_address1; +wire tdf1_114_U0_out_data_ce1; +wire [63:0] tdf1_114_U0_out_data_d1; +wire tdf1_114_U0_out_data_we1; +wire [6:0] tdf1_114_U0_filter_data_0_address0; +wire tdf1_114_U0_filter_data_0_ce0; +wire [15:0] tdf1_114_U0_filter_data_0_d0; +wire tdf1_114_U0_filter_data_0_we0; +wire [6:0] tdf1_114_U0_filter_data_0_address1; +wire tdf1_114_U0_filter_data_0_ce1; +wire [15:0] tdf1_114_U0_filter_data_0_d1; +wire tdf1_114_U0_filter_data_0_we1; +wire [6:0] tdf1_114_U0_filter_data_1_address0; +wire tdf1_114_U0_filter_data_1_ce0; +wire [15:0] tdf1_114_U0_filter_data_1_d0; +wire tdf1_114_U0_filter_data_1_we0; +wire [6:0] tdf1_114_U0_filter_data_1_address1; +wire tdf1_114_U0_filter_data_1_ce1; +wire [15:0] tdf1_114_U0_filter_data_1_d1; +wire tdf1_114_U0_filter_data_1_we1; +wire [6:0] tdf1_114_U0_filter_data_2_address0; +wire tdf1_114_U0_filter_data_2_ce0; +wire [15:0] tdf1_114_U0_filter_data_2_d0; +wire tdf1_114_U0_filter_data_2_we0; +wire [6:0] tdf1_114_U0_filter_data_2_address1; +wire tdf1_114_U0_filter_data_2_ce1; +wire [15:0] tdf1_114_U0_filter_data_2_d1; +wire tdf1_114_U0_filter_data_2_we1; +wire [6:0] tdf1_114_U0_filter_data_3_address0; +wire tdf1_114_U0_filter_data_3_ce0; +wire [15:0] tdf1_114_U0_filter_data_3_d0; +wire tdf1_114_U0_filter_data_3_we0; +wire [6:0] tdf1_114_U0_filter_data_3_address1; +wire tdf1_114_U0_filter_data_3_ce1; +wire [15:0] tdf1_114_U0_filter_data_3_d1; +wire tdf1_114_U0_filter_data_3_we1; +wire [3:0] tdf1_114_U0_adjustments_address0; +wire tdf1_114_U0_adjustments_ce0; +wire [47:0] tdf1_114_U0_adjustments_d0; +wire tdf1_114_U0_adjustments_we0; +wire [3:0] tdf1_114_U0_adjustments_address1; +wire tdf1_114_U0_adjustments_ce1; +wire [47:0] tdf1_114_U0_adjustments_d1; +wire tdf1_114_U0_adjustments_we1; +wire tdf1_114_U0_in_data_read; +wire tdf1_114_U0_out_data_full_n; +wire tdf1_114_U0_out_data_write; +wire tdf1_114_U0_ap_start; +wire tdf1_114_U0_ap_done; +wire tdf1_114_U0_ap_ready; +wire tdf1_114_U0_ap_idle; +wire tdf1_114_U0_ap_continue; +wire ap_channel_done_tdf2_fmaps; +wire [15:0] tdf2_113_U0_in_data_address0; +wire tdf2_113_U0_in_data_ce0; +wire [63:0] tdf2_113_U0_in_data_d0; +wire tdf2_113_U0_in_data_we0; +wire [15:0] tdf2_113_U0_in_data_address1; +wire tdf2_113_U0_in_data_ce1; +wire [63:0] tdf2_113_U0_in_data_d1; +wire tdf2_113_U0_in_data_we1; +wire [14:0] tdf2_113_U0_out_data_address0; +wire tdf2_113_U0_out_data_ce0; +wire [63:0] tdf2_113_U0_out_data_d0; +wire tdf2_113_U0_out_data_we0; +wire [14:0] tdf2_113_U0_out_data_address1; +wire tdf2_113_U0_out_data_ce1; +wire [63:0] tdf2_113_U0_out_data_d1; +wire tdf2_113_U0_out_data_we1; +wire [9:0] tdf2_113_U0_filter_data_0_address0; +wire tdf2_113_U0_filter_data_0_ce0; +wire [31:0] tdf2_113_U0_filter_data_0_d0; +wire tdf2_113_U0_filter_data_0_we0; +wire [9:0] tdf2_113_U0_filter_data_0_address1; +wire tdf2_113_U0_filter_data_0_ce1; +wire [31:0] tdf2_113_U0_filter_data_0_d1; +wire tdf2_113_U0_filter_data_0_we1; +wire [9:0] tdf2_113_U0_filter_data_1_address0; +wire tdf2_113_U0_filter_data_1_ce0; +wire [31:0] tdf2_113_U0_filter_data_1_d0; +wire tdf2_113_U0_filter_data_1_we0; +wire [9:0] tdf2_113_U0_filter_data_1_address1; +wire tdf2_113_U0_filter_data_1_ce1; +wire [31:0] tdf2_113_U0_filter_data_1_d1; +wire tdf2_113_U0_filter_data_1_we1; +wire [9:0] tdf2_113_U0_filter_data_2_address0; +wire tdf2_113_U0_filter_data_2_ce0; +wire [31:0] tdf2_113_U0_filter_data_2_d0; +wire tdf2_113_U0_filter_data_2_we0; +wire [9:0] tdf2_113_U0_filter_data_2_address1; +wire tdf2_113_U0_filter_data_2_ce1; +wire [31:0] tdf2_113_U0_filter_data_2_d1; +wire tdf2_113_U0_filter_data_2_we1; +wire [9:0] tdf2_113_U0_filter_data_3_address0; +wire tdf2_113_U0_filter_data_3_ce0; +wire [31:0] tdf2_113_U0_filter_data_3_d0; +wire tdf2_113_U0_filter_data_3_we0; +wire [9:0] tdf2_113_U0_filter_data_3_address1; +wire tdf2_113_U0_filter_data_3_ce1; +wire [31:0] tdf2_113_U0_filter_data_3_d1; +wire tdf2_113_U0_filter_data_3_we1; +wire [4:0] tdf2_113_U0_adjustments_address0; +wire tdf2_113_U0_adjustments_ce0; +wire [47:0] tdf2_113_U0_adjustments_d0; +wire tdf2_113_U0_adjustments_we0; +wire [4:0] tdf2_113_U0_adjustments_address1; +wire tdf2_113_U0_adjustments_ce1; +wire [47:0] tdf2_113_U0_adjustments_d1; +wire tdf2_113_U0_adjustments_we1; +wire tdf2_113_U0_in_data_read; +wire tdf2_113_U0_out_data_full_n; +wire tdf2_113_U0_out_data_write; +wire tdf2_113_U0_ap_start; +wire tdf2_113_U0_ap_done; +wire tdf2_113_U0_ap_ready; +wire tdf2_113_U0_ap_idle; +wire tdf2_113_U0_ap_continue; +wire ap_channel_done_tdf3_fmaps; +wire [14:0] tdf3_112_U0_in_data_address0; +wire tdf3_112_U0_in_data_ce0; +wire [63:0] tdf3_112_U0_in_data_d0; +wire tdf3_112_U0_in_data_we0; +wire [14:0] tdf3_112_U0_in_data_address1; +wire tdf3_112_U0_in_data_ce1; +wire [63:0] tdf3_112_U0_in_data_d1; +wire tdf3_112_U0_in_data_we1; +wire [13:0] tdf3_112_U0_out_data_address0; +wire tdf3_112_U0_out_data_ce0; +wire [63:0] tdf3_112_U0_out_data_d0; +wire tdf3_112_U0_out_data_we0; +wire [13:0] tdf3_112_U0_out_data_address1; +wire tdf3_112_U0_out_data_ce1; +wire [63:0] tdf3_112_U0_out_data_d1; +wire tdf3_112_U0_out_data_we1; +wire [8:0] tdf3_112_U0_filter_data_address0; +wire tdf3_112_U0_filter_data_ce0; +wire [15:0] tdf3_112_U0_filter_data_d0; +wire tdf3_112_U0_filter_data_we0; +wire [8:0] tdf3_112_U0_filter_data_address1; +wire tdf3_112_U0_filter_data_ce1; +wire [15:0] tdf3_112_U0_filter_data_d1; +wire tdf3_112_U0_filter_data_we1; +wire [3:0] tdf3_112_U0_adjustments_address0; +wire tdf3_112_U0_adjustments_ce0; +wire [47:0] tdf3_112_U0_adjustments_d0; +wire tdf3_112_U0_adjustments_we0; +wire [3:0] tdf3_112_U0_adjustments_address1; +wire tdf3_112_U0_adjustments_ce1; +wire [47:0] tdf3_112_U0_adjustments_d1; +wire tdf3_112_U0_adjustments_we1; +wire tdf3_112_U0_in_data_read; +wire tdf3_112_U0_out_data_full_n; +wire tdf3_112_U0_out_data_write; +wire tdf3_112_U0_ap_start; +wire tdf3_112_U0_ap_done; +wire tdf3_112_U0_ap_ready; +wire tdf3_112_U0_ap_idle; +wire tdf3_112_U0_ap_continue; +wire ap_channel_done_tdf4_fmaps; +wire [13:0] tdf4_111_U0_in_data_address0; +wire tdf4_111_U0_in_data_ce0; +wire [63:0] tdf4_111_U0_in_data_d0; +wire tdf4_111_U0_in_data_we0; +wire [13:0] tdf4_111_U0_in_data_address1; +wire tdf4_111_U0_in_data_ce1; +wire [63:0] tdf4_111_U0_in_data_d1; +wire tdf4_111_U0_in_data_we1; +wire [13:0] tdf4_111_U0_out_data_address0; +wire tdf4_111_U0_out_data_ce0; +wire [63:0] tdf4_111_U0_out_data_d0; +wire tdf4_111_U0_out_data_we0; +wire [13:0] tdf4_111_U0_out_data_address1; +wire tdf4_111_U0_out_data_ce1; +wire [63:0] tdf4_111_U0_out_data_d1; +wire tdf4_111_U0_out_data_we1; +wire [10:0] tdf4_111_U0_l1_filter_data_0_address0; +wire tdf4_111_U0_l1_filter_data_0_ce0; +wire [63:0] tdf4_111_U0_l1_filter_data_0_d0; +wire tdf4_111_U0_l1_filter_data_0_we0; +wire [10:0] tdf4_111_U0_l1_filter_data_0_address1; +wire tdf4_111_U0_l1_filter_data_0_ce1; +wire [63:0] tdf4_111_U0_l1_filter_data_0_d1; +wire tdf4_111_U0_l1_filter_data_0_we1; +wire [10:0] tdf4_111_U0_l1_filter_data_1_address0; +wire tdf4_111_U0_l1_filter_data_1_ce0; +wire [63:0] tdf4_111_U0_l1_filter_data_1_d0; +wire tdf4_111_U0_l1_filter_data_1_we0; +wire [10:0] tdf4_111_U0_l1_filter_data_1_address1; +wire tdf4_111_U0_l1_filter_data_1_ce1; +wire [63:0] tdf4_111_U0_l1_filter_data_1_d1; +wire tdf4_111_U0_l1_filter_data_1_we1; +wire [10:0] tdf4_111_U0_l1_filter_data_2_address0; +wire tdf4_111_U0_l1_filter_data_2_ce0; +wire [63:0] tdf4_111_U0_l1_filter_data_2_d0; +wire tdf4_111_U0_l1_filter_data_2_we0; +wire [10:0] tdf4_111_U0_l1_filter_data_2_address1; +wire tdf4_111_U0_l1_filter_data_2_ce1; +wire [63:0] tdf4_111_U0_l1_filter_data_2_d1; +wire tdf4_111_U0_l1_filter_data_2_we1; +wire [10:0] tdf4_111_U0_l1_filter_data_3_address0; +wire tdf4_111_U0_l1_filter_data_3_ce0; +wire [63:0] tdf4_111_U0_l1_filter_data_3_d0; +wire tdf4_111_U0_l1_filter_data_3_we0; +wire [10:0] tdf4_111_U0_l1_filter_data_3_address1; +wire tdf4_111_U0_l1_filter_data_3_ce1; +wire [63:0] tdf4_111_U0_l1_filter_data_3_d1; +wire tdf4_111_U0_l1_filter_data_3_we1; +wire [9:0] tdf4_111_U0_l2_filter_data_0_address0; +wire tdf4_111_U0_l2_filter_data_0_ce0; +wire [15:0] tdf4_111_U0_l2_filter_data_0_d0; +wire tdf4_111_U0_l2_filter_data_0_we0; +wire [9:0] tdf4_111_U0_l2_filter_data_0_address1; +wire tdf4_111_U0_l2_filter_data_0_ce1; +wire [15:0] tdf4_111_U0_l2_filter_data_0_d1; +wire tdf4_111_U0_l2_filter_data_0_we1; +wire [9:0] tdf4_111_U0_l2_filter_data_1_address0; +wire tdf4_111_U0_l2_filter_data_1_ce0; +wire [15:0] tdf4_111_U0_l2_filter_data_1_d0; +wire tdf4_111_U0_l2_filter_data_1_we0; +wire [9:0] tdf4_111_U0_l2_filter_data_1_address1; +wire tdf4_111_U0_l2_filter_data_1_ce1; +wire [15:0] tdf4_111_U0_l2_filter_data_1_d1; +wire tdf4_111_U0_l2_filter_data_1_we1; +wire [6:0] tdf4_111_U0_l1_adjustments_address0; +wire tdf4_111_U0_l1_adjustments_ce0; +wire [47:0] tdf4_111_U0_l1_adjustments_d0; +wire tdf4_111_U0_l1_adjustments_we0; +wire [6:0] tdf4_111_U0_l1_adjustments_address1; +wire tdf4_111_U0_l1_adjustments_ce1; +wire [47:0] tdf4_111_U0_l1_adjustments_d1; +wire tdf4_111_U0_l1_adjustments_we1; +wire [3:0] tdf4_111_U0_l2_adjustments_address0; +wire tdf4_111_U0_l2_adjustments_ce0; +wire [47:0] tdf4_111_U0_l2_adjustments_d0; +wire tdf4_111_U0_l2_adjustments_we0; +wire [3:0] tdf4_111_U0_l2_adjustments_address1; +wire tdf4_111_U0_l2_adjustments_ce1; +wire [47:0] tdf4_111_U0_l2_adjustments_d1; +wire tdf4_111_U0_l2_adjustments_we1; +wire tdf4_111_U0_in_data_read; +wire tdf4_111_U0_out_data_full_n; +wire tdf4_111_U0_out_data_write; +wire tdf4_111_U0_ap_start; +wire tdf4_111_U0_ap_done; +wire tdf4_111_U0_ap_ready; +wire tdf4_111_U0_ap_idle; +wire tdf4_111_U0_ap_continue; +wire ap_channel_done_tdf5_fmaps; +wire [13:0] tdf5_110_U0_in_data_address0; +wire tdf5_110_U0_in_data_ce0; +wire [63:0] tdf5_110_U0_in_data_d0; +wire tdf5_110_U0_in_data_we0; +wire [13:0] tdf5_110_U0_in_data_address1; +wire tdf5_110_U0_in_data_ce1; +wire [63:0] tdf5_110_U0_in_data_d1; +wire tdf5_110_U0_in_data_we1; +wire [14:0] tdf5_110_U0_out_data_address0; +wire tdf5_110_U0_out_data_ce0; +wire [63:0] tdf5_110_U0_out_data_d0; +wire tdf5_110_U0_out_data_we0; +wire [14:0] tdf5_110_U0_out_data_address1; +wire tdf5_110_U0_out_data_ce1; +wire [63:0] tdf5_110_U0_out_data_d1; +wire tdf5_110_U0_out_data_we1; +wire [11:0] tdf5_110_U0_filter_data_0_address0; +wire tdf5_110_U0_filter_data_0_ce0; +wire [31:0] tdf5_110_U0_filter_data_0_d0; +wire tdf5_110_U0_filter_data_0_we0; +wire [11:0] tdf5_110_U0_filter_data_0_address1; +wire tdf5_110_U0_filter_data_0_ce1; +wire [31:0] tdf5_110_U0_filter_data_0_d1; +wire tdf5_110_U0_filter_data_0_we1; +wire [11:0] tdf5_110_U0_filter_data_1_address0; +wire tdf5_110_U0_filter_data_1_ce0; +wire [31:0] tdf5_110_U0_filter_data_1_d0; +wire tdf5_110_U0_filter_data_1_we0; +wire [11:0] tdf5_110_U0_filter_data_1_address1; +wire tdf5_110_U0_filter_data_1_ce1; +wire [31:0] tdf5_110_U0_filter_data_1_d1; +wire tdf5_110_U0_filter_data_1_we1; +wire [11:0] tdf5_110_U0_filter_data_2_address0; +wire tdf5_110_U0_filter_data_2_ce0; +wire [31:0] tdf5_110_U0_filter_data_2_d0; +wire tdf5_110_U0_filter_data_2_we0; +wire [11:0] tdf5_110_U0_filter_data_2_address1; +wire tdf5_110_U0_filter_data_2_ce1; +wire [31:0] tdf5_110_U0_filter_data_2_d1; +wire tdf5_110_U0_filter_data_2_we1; +wire [11:0] tdf5_110_U0_filter_data_3_address0; +wire tdf5_110_U0_filter_data_3_ce0; +wire [31:0] tdf5_110_U0_filter_data_3_d0; +wire tdf5_110_U0_filter_data_3_we0; +wire [11:0] tdf5_110_U0_filter_data_3_address1; +wire tdf5_110_U0_filter_data_3_ce1; +wire [31:0] tdf5_110_U0_filter_data_3_d1; +wire tdf5_110_U0_filter_data_3_we1; +wire [6:0] tdf5_110_U0_adjustments_address0; +wire tdf5_110_U0_adjustments_ce0; +wire [47:0] tdf5_110_U0_adjustments_d0; +wire tdf5_110_U0_adjustments_we0; +wire [6:0] tdf5_110_U0_adjustments_address1; +wire tdf5_110_U0_adjustments_ce1; +wire [47:0] tdf5_110_U0_adjustments_d1; +wire tdf5_110_U0_adjustments_we1; +wire tdf5_110_U0_in_data_read; +wire tdf5_110_U0_out_data_full_n; +wire tdf5_110_U0_out_data_write; +wire tdf5_110_U0_ap_start; +wire tdf5_110_U0_ap_done; +wire tdf5_110_U0_ap_ready; +wire tdf5_110_U0_ap_idle; +wire tdf5_110_U0_ap_continue; +wire ap_channel_done_tdf6_fmaps; +wire [14:0] tdf6_19_U0_in_data_address0; +wire tdf6_19_U0_in_data_ce0; +wire [63:0] tdf6_19_U0_in_data_d0; +wire tdf6_19_U0_in_data_we0; +wire [14:0] tdf6_19_U0_in_data_address1; +wire tdf6_19_U0_in_data_ce1; +wire [63:0] tdf6_19_U0_in_data_d1; +wire tdf6_19_U0_in_data_we1; +wire [12:0] tdf6_19_U0_out_data_address0; +wire tdf6_19_U0_out_data_ce0; +wire [63:0] tdf6_19_U0_out_data_d0; +wire tdf6_19_U0_out_data_we0; +wire [12:0] tdf6_19_U0_out_data_address1; +wire tdf6_19_U0_out_data_ce1; +wire [63:0] tdf6_19_U0_out_data_d1; +wire tdf6_19_U0_out_data_we1; +wire [11:0] tdf6_19_U0_filter_data_address0; +wire tdf6_19_U0_filter_data_ce0; +wire [15:0] tdf6_19_U0_filter_data_d0; +wire tdf6_19_U0_filter_data_we0; +wire [11:0] tdf6_19_U0_filter_data_address1; +wire tdf6_19_U0_filter_data_ce1; +wire [15:0] tdf6_19_U0_filter_data_d1; +wire tdf6_19_U0_filter_data_we1; +wire [4:0] tdf6_19_U0_adjustments_address0; +wire tdf6_19_U0_adjustments_ce0; +wire [47:0] tdf6_19_U0_adjustments_d0; +wire tdf6_19_U0_adjustments_we0; +wire [4:0] tdf6_19_U0_adjustments_address1; +wire tdf6_19_U0_adjustments_ce1; +wire [47:0] tdf6_19_U0_adjustments_d1; +wire tdf6_19_U0_adjustments_we1; +wire tdf6_19_U0_in_data_read; +wire tdf6_19_U0_out_data_full_n; +wire tdf6_19_U0_out_data_write; +wire tdf6_19_U0_ap_start; +wire tdf6_19_U0_ap_done; +wire tdf6_19_U0_ap_ready; +wire tdf6_19_U0_ap_idle; +wire tdf6_19_U0_ap_continue; +wire ap_channel_done_tdf7_fmaps; +wire [12:0] tdf7_18_U0_in_data_address0; +wire tdf7_18_U0_in_data_ce0; +wire [63:0] tdf7_18_U0_in_data_d0; +wire tdf7_18_U0_in_data_we0; +wire [12:0] tdf7_18_U0_in_data_address1; +wire tdf7_18_U0_in_data_ce1; +wire [63:0] tdf7_18_U0_in_data_d1; +wire tdf7_18_U0_in_data_we1; +wire [12:0] tdf7_18_U0_out_data_address0; +wire tdf7_18_U0_out_data_ce0; +wire [63:0] tdf7_18_U0_out_data_d0; +wire tdf7_18_U0_out_data_we0; +wire [12:0] tdf7_18_U0_out_data_address1; +wire tdf7_18_U0_out_data_ce1; +wire [63:0] tdf7_18_U0_out_data_d1; +wire tdf7_18_U0_out_data_we1; +wire [12:0] tdf7_18_U0_l1_filter_data_0_address0; +wire tdf7_18_U0_l1_filter_data_0_ce0; +wire [63:0] tdf7_18_U0_l1_filter_data_0_d0; +wire tdf7_18_U0_l1_filter_data_0_we0; +wire [12:0] tdf7_18_U0_l1_filter_data_0_address1; +wire tdf7_18_U0_l1_filter_data_0_ce1; +wire [63:0] tdf7_18_U0_l1_filter_data_0_d1; +wire tdf7_18_U0_l1_filter_data_0_we1; +wire [12:0] tdf7_18_U0_l1_filter_data_1_address0; +wire tdf7_18_U0_l1_filter_data_1_ce0; +wire [63:0] tdf7_18_U0_l1_filter_data_1_d0; +wire tdf7_18_U0_l1_filter_data_1_we0; +wire [12:0] tdf7_18_U0_l1_filter_data_1_address1; +wire tdf7_18_U0_l1_filter_data_1_ce1; +wire [63:0] tdf7_18_U0_l1_filter_data_1_d1; +wire tdf7_18_U0_l1_filter_data_1_we1; +wire [12:0] tdf7_18_U0_l1_filter_data_2_address0; +wire tdf7_18_U0_l1_filter_data_2_ce0; +wire [63:0] tdf7_18_U0_l1_filter_data_2_d0; +wire tdf7_18_U0_l1_filter_data_2_we0; +wire [12:0] tdf7_18_U0_l1_filter_data_2_address1; +wire tdf7_18_U0_l1_filter_data_2_ce1; +wire [63:0] tdf7_18_U0_l1_filter_data_2_d1; +wire tdf7_18_U0_l1_filter_data_2_we1; +wire [12:0] tdf7_18_U0_l1_filter_data_3_address0; +wire tdf7_18_U0_l1_filter_data_3_ce0; +wire [63:0] tdf7_18_U0_l1_filter_data_3_d0; +wire tdf7_18_U0_l1_filter_data_3_we0; +wire [12:0] tdf7_18_U0_l1_filter_data_3_address1; +wire tdf7_18_U0_l1_filter_data_3_ce1; +wire [63:0] tdf7_18_U0_l1_filter_data_3_d1; +wire tdf7_18_U0_l1_filter_data_3_we1; +wire [11:0] tdf7_18_U0_l2_filter_data_0_address0; +wire tdf7_18_U0_l2_filter_data_0_ce0; +wire [15:0] tdf7_18_U0_l2_filter_data_0_d0; +wire tdf7_18_U0_l2_filter_data_0_we0; +wire [11:0] tdf7_18_U0_l2_filter_data_0_address1; +wire tdf7_18_U0_l2_filter_data_0_ce1; +wire [15:0] tdf7_18_U0_l2_filter_data_0_d1; +wire tdf7_18_U0_l2_filter_data_0_we1; +wire [11:0] tdf7_18_U0_l2_filter_data_1_address0; +wire tdf7_18_U0_l2_filter_data_1_ce0; +wire [15:0] tdf7_18_U0_l2_filter_data_1_d0; +wire tdf7_18_U0_l2_filter_data_1_we0; +wire [11:0] tdf7_18_U0_l2_filter_data_1_address1; +wire tdf7_18_U0_l2_filter_data_1_ce1; +wire [15:0] tdf7_18_U0_l2_filter_data_1_d1; +wire tdf7_18_U0_l2_filter_data_1_we1; +wire [7:0] tdf7_18_U0_l1_adjustments_address0; +wire tdf7_18_U0_l1_adjustments_ce0; +wire [47:0] tdf7_18_U0_l1_adjustments_d0; +wire tdf7_18_U0_l1_adjustments_we0; +wire [7:0] tdf7_18_U0_l1_adjustments_address1; +wire tdf7_18_U0_l1_adjustments_ce1; +wire [47:0] tdf7_18_U0_l1_adjustments_d1; +wire tdf7_18_U0_l1_adjustments_we1; +wire [4:0] tdf7_18_U0_l2_adjustments_address0; +wire tdf7_18_U0_l2_adjustments_ce0; +wire [47:0] tdf7_18_U0_l2_adjustments_d0; +wire tdf7_18_U0_l2_adjustments_we0; +wire [4:0] tdf7_18_U0_l2_adjustments_address1; +wire tdf7_18_U0_l2_adjustments_ce1; +wire [47:0] tdf7_18_U0_l2_adjustments_d1; +wire tdf7_18_U0_l2_adjustments_we1; +wire tdf7_18_U0_in_data_read; +wire tdf7_18_U0_out_data_full_n; +wire tdf7_18_U0_out_data_write; +wire tdf7_18_U0_ap_start; +wire tdf7_18_U0_ap_done; +wire tdf7_18_U0_ap_ready; +wire tdf7_18_U0_ap_idle; +wire tdf7_18_U0_ap_continue; +wire ap_channel_done_tdf8_fmaps; +wire [12:0] tdf8_17_U0_in_data_address0; +wire tdf8_17_U0_in_data_ce0; +wire [63:0] tdf8_17_U0_in_data_d0; +wire tdf8_17_U0_in_data_we0; +wire [12:0] tdf8_17_U0_in_data_address1; +wire tdf8_17_U0_in_data_ce1; +wire [63:0] tdf8_17_U0_in_data_d1; +wire tdf8_17_U0_in_data_we1; +wire [13:0] tdf8_17_U0_out_data_address0; +wire tdf8_17_U0_out_data_ce0; +wire [63:0] tdf8_17_U0_out_data_d0; +wire tdf8_17_U0_out_data_we0; +wire [13:0] tdf8_17_U0_out_data_address1; +wire tdf8_17_U0_out_data_ce1; +wire [63:0] tdf8_17_U0_out_data_d1; +wire tdf8_17_U0_out_data_we1; +wire [13:0] tdf8_17_U0_filter_data_0_address0; +wire tdf8_17_U0_filter_data_0_ce0; +wire [31:0] tdf8_17_U0_filter_data_0_d0; +wire tdf8_17_U0_filter_data_0_we0; +wire [13:0] tdf8_17_U0_filter_data_0_address1; +wire tdf8_17_U0_filter_data_0_ce1; +wire [31:0] tdf8_17_U0_filter_data_0_d1; +wire tdf8_17_U0_filter_data_0_we1; +wire [13:0] tdf8_17_U0_filter_data_1_address0; +wire tdf8_17_U0_filter_data_1_ce0; +wire [31:0] tdf8_17_U0_filter_data_1_d0; +wire tdf8_17_U0_filter_data_1_we0; +wire [13:0] tdf8_17_U0_filter_data_1_address1; +wire tdf8_17_U0_filter_data_1_ce1; +wire [31:0] tdf8_17_U0_filter_data_1_d1; +wire tdf8_17_U0_filter_data_1_we1; +wire [13:0] tdf8_17_U0_filter_data_2_address0; +wire tdf8_17_U0_filter_data_2_ce0; +wire [31:0] tdf8_17_U0_filter_data_2_d0; +wire tdf8_17_U0_filter_data_2_we0; +wire [13:0] tdf8_17_U0_filter_data_2_address1; +wire tdf8_17_U0_filter_data_2_ce1; +wire [31:0] tdf8_17_U0_filter_data_2_d1; +wire tdf8_17_U0_filter_data_2_we1; +wire [13:0] tdf8_17_U0_filter_data_3_address0; +wire tdf8_17_U0_filter_data_3_ce0; +wire [31:0] tdf8_17_U0_filter_data_3_d0; +wire tdf8_17_U0_filter_data_3_we0; +wire [13:0] tdf8_17_U0_filter_data_3_address1; +wire tdf8_17_U0_filter_data_3_ce1; +wire [31:0] tdf8_17_U0_filter_data_3_d1; +wire tdf8_17_U0_filter_data_3_we1; +wire [7:0] tdf8_17_U0_adjustments_address0; +wire tdf8_17_U0_adjustments_ce0; +wire [47:0] tdf8_17_U0_adjustments_d0; +wire tdf8_17_U0_adjustments_we0; +wire [7:0] tdf8_17_U0_adjustments_address1; +wire tdf8_17_U0_adjustments_ce1; +wire [47:0] tdf8_17_U0_adjustments_d1; +wire tdf8_17_U0_adjustments_we1; +wire tdf8_17_U0_in_data_read; +wire tdf8_17_U0_out_data_full_n; +wire tdf8_17_U0_out_data_write; +wire tdf8_17_U0_ap_start; +wire tdf8_17_U0_ap_done; +wire tdf8_17_U0_ap_ready; +wire tdf8_17_U0_ap_idle; +wire tdf8_17_U0_ap_continue; +wire ap_channel_done_tdf9_fmaps; +wire [13:0] tdf9_16_U0_in_data_address0; +wire tdf9_16_U0_in_data_ce0; +wire [63:0] tdf9_16_U0_in_data_d0; +wire tdf9_16_U0_in_data_we0; +wire [13:0] tdf9_16_U0_in_data_address1; +wire tdf9_16_U0_in_data_ce1; +wire [63:0] tdf9_16_U0_in_data_d1; +wire tdf9_16_U0_in_data_we1; +wire [11:0] tdf9_16_U0_out_data_address0; +wire tdf9_16_U0_out_data_ce0; +wire [63:0] tdf9_16_U0_out_data_d0; +wire tdf9_16_U0_out_data_we0; +wire [11:0] tdf9_16_U0_out_data_address1; +wire tdf9_16_U0_out_data_ce1; +wire [63:0] tdf9_16_U0_out_data_d1; +wire tdf9_16_U0_out_data_we1; +wire [13:0] tdf9_16_U0_filter_data_address0; +wire tdf9_16_U0_filter_data_ce0; +wire [15:0] tdf9_16_U0_filter_data_d0; +wire tdf9_16_U0_filter_data_we0; +wire [13:0] tdf9_16_U0_filter_data_address1; +wire tdf9_16_U0_filter_data_ce1; +wire [15:0] tdf9_16_U0_filter_data_d1; +wire tdf9_16_U0_filter_data_we1; +wire [5:0] tdf9_16_U0_adjustments_address0; +wire tdf9_16_U0_adjustments_ce0; +wire [47:0] tdf9_16_U0_adjustments_d0; +wire tdf9_16_U0_adjustments_we0; +wire [5:0] tdf9_16_U0_adjustments_address1; +wire tdf9_16_U0_adjustments_ce1; +wire [47:0] tdf9_16_U0_adjustments_d1; +wire tdf9_16_U0_adjustments_we1; +wire tdf9_16_U0_in_data_read; +wire tdf9_16_U0_out_data_full_n; +wire tdf9_16_U0_out_data_write; +wire tdf9_16_U0_ap_start; +wire tdf9_16_U0_ap_done; +wire tdf9_16_U0_ap_ready; +wire tdf9_16_U0_ap_idle; +wire tdf9_16_U0_ap_continue; +wire ap_channel_done_tdf10_fmaps; +wire [11:0] tdf10_15_U0_in_data_address0; +wire tdf10_15_U0_in_data_ce0; +wire [63:0] tdf10_15_U0_in_data_d0; +wire tdf10_15_U0_in_data_we0; +wire [11:0] tdf10_15_U0_in_data_address1; +wire tdf10_15_U0_in_data_ce1; +wire [63:0] tdf10_15_U0_in_data_d1; +wire tdf10_15_U0_in_data_we1; +wire [11:0] tdf10_15_U0_out_data_address0; +wire tdf10_15_U0_out_data_ce0; +wire [63:0] tdf10_15_U0_out_data_d0; +wire tdf10_15_U0_out_data_we0; +wire [11:0] tdf10_15_U0_out_data_address1; +wire tdf10_15_U0_out_data_ce1; +wire [63:0] tdf10_15_U0_out_data_d1; +wire tdf10_15_U0_out_data_we1; +wire [14:0] tdf10_15_U0_l1_filter_data_0_address0; +wire tdf10_15_U0_l1_filter_data_0_ce0; +wire [63:0] tdf10_15_U0_l1_filter_data_0_d0; +wire tdf10_15_U0_l1_filter_data_0_we0; +wire [14:0] tdf10_15_U0_l1_filter_data_0_address1; +wire tdf10_15_U0_l1_filter_data_0_ce1; +wire [63:0] tdf10_15_U0_l1_filter_data_0_d1; +wire tdf10_15_U0_l1_filter_data_0_we1; +wire [14:0] tdf10_15_U0_l1_filter_data_1_address0; +wire tdf10_15_U0_l1_filter_data_1_ce0; +wire [63:0] tdf10_15_U0_l1_filter_data_1_d0; +wire tdf10_15_U0_l1_filter_data_1_we0; +wire [14:0] tdf10_15_U0_l1_filter_data_1_address1; +wire tdf10_15_U0_l1_filter_data_1_ce1; +wire [63:0] tdf10_15_U0_l1_filter_data_1_d1; +wire tdf10_15_U0_l1_filter_data_1_we1; +wire [14:0] tdf10_15_U0_l1_filter_data_2_address0; +wire tdf10_15_U0_l1_filter_data_2_ce0; +wire [63:0] tdf10_15_U0_l1_filter_data_2_d0; +wire tdf10_15_U0_l1_filter_data_2_we0; +wire [14:0] tdf10_15_U0_l1_filter_data_2_address1; +wire tdf10_15_U0_l1_filter_data_2_ce1; +wire [63:0] tdf10_15_U0_l1_filter_data_2_d1; +wire tdf10_15_U0_l1_filter_data_2_we1; +wire [14:0] tdf10_15_U0_l1_filter_data_3_address0; +wire tdf10_15_U0_l1_filter_data_3_ce0; +wire [63:0] tdf10_15_U0_l1_filter_data_3_d0; +wire tdf10_15_U0_l1_filter_data_3_we0; +wire [14:0] tdf10_15_U0_l1_filter_data_3_address1; +wire tdf10_15_U0_l1_filter_data_3_ce1; +wire [63:0] tdf10_15_U0_l1_filter_data_3_d1; +wire tdf10_15_U0_l1_filter_data_3_we1; +wire [13:0] tdf10_15_U0_l2_filter_data_0_address0; +wire tdf10_15_U0_l2_filter_data_0_ce0; +wire [15:0] tdf10_15_U0_l2_filter_data_0_d0; +wire tdf10_15_U0_l2_filter_data_0_we0; +wire [13:0] tdf10_15_U0_l2_filter_data_0_address1; +wire tdf10_15_U0_l2_filter_data_0_ce1; +wire [15:0] tdf10_15_U0_l2_filter_data_0_d1; +wire tdf10_15_U0_l2_filter_data_0_we1; +wire [13:0] tdf10_15_U0_l2_filter_data_1_address0; +wire tdf10_15_U0_l2_filter_data_1_ce0; +wire [15:0] tdf10_15_U0_l2_filter_data_1_d0; +wire tdf10_15_U0_l2_filter_data_1_we0; +wire [13:0] tdf10_15_U0_l2_filter_data_1_address1; +wire tdf10_15_U0_l2_filter_data_1_ce1; +wire [15:0] tdf10_15_U0_l2_filter_data_1_d1; +wire tdf10_15_U0_l2_filter_data_1_we1; +wire [8:0] tdf10_15_U0_l1_adjustments_address0; +wire tdf10_15_U0_l1_adjustments_ce0; +wire [47:0] tdf10_15_U0_l1_adjustments_d0; +wire tdf10_15_U0_l1_adjustments_we0; +wire [8:0] tdf10_15_U0_l1_adjustments_address1; +wire tdf10_15_U0_l1_adjustments_ce1; +wire [47:0] tdf10_15_U0_l1_adjustments_d1; +wire tdf10_15_U0_l1_adjustments_we1; +wire [5:0] tdf10_15_U0_l2_adjustments_address0; +wire tdf10_15_U0_l2_adjustments_ce0; +wire [47:0] tdf10_15_U0_l2_adjustments_d0; +wire tdf10_15_U0_l2_adjustments_we0; +wire [5:0] tdf10_15_U0_l2_adjustments_address1; +wire tdf10_15_U0_l2_adjustments_ce1; +wire [47:0] tdf10_15_U0_l2_adjustments_d1; +wire tdf10_15_U0_l2_adjustments_we1; +wire tdf10_15_U0_in_data_read; +wire tdf10_15_U0_out_data_full_n; +wire tdf10_15_U0_out_data_write; +wire tdf10_15_U0_ap_start; +wire tdf10_15_U0_ap_done; +wire tdf10_15_U0_ap_ready; +wire tdf10_15_U0_ap_idle; +wire tdf10_15_U0_ap_continue; +wire ap_channel_done_tdf11_fmaps; +wire [11:0] tdf11_14_U0_in_data_address0; +wire tdf11_14_U0_in_data_ce0; +wire [63:0] tdf11_14_U0_in_data_d0; +wire tdf11_14_U0_in_data_we0; +wire [11:0] tdf11_14_U0_in_data_address1; +wire tdf11_14_U0_in_data_ce1; +wire [63:0] tdf11_14_U0_in_data_d1; +wire tdf11_14_U0_in_data_we1; +wire [12:0] tdf11_14_U0_out_data_address0; +wire tdf11_14_U0_out_data_ce0; +wire [63:0] tdf11_14_U0_out_data_d0; +wire tdf11_14_U0_out_data_we0; +wire [12:0] tdf11_14_U0_out_data_address1; +wire tdf11_14_U0_out_data_ce1; +wire [63:0] tdf11_14_U0_out_data_d1; +wire tdf11_14_U0_out_data_we1; +wire [14:0] tdf11_14_U0_l1_filter_data_0_address0; +wire tdf11_14_U0_l1_filter_data_0_ce0; +wire [63:0] tdf11_14_U0_l1_filter_data_0_d0; +wire tdf11_14_U0_l1_filter_data_0_we0; +wire [14:0] tdf11_14_U0_l1_filter_data_0_address1; +wire tdf11_14_U0_l1_filter_data_0_ce1; +wire [63:0] tdf11_14_U0_l1_filter_data_0_d1; +wire tdf11_14_U0_l1_filter_data_0_we1; +wire [14:0] tdf11_14_U0_l1_filter_data_1_address0; +wire tdf11_14_U0_l1_filter_data_1_ce0; +wire [63:0] tdf11_14_U0_l1_filter_data_1_d0; +wire tdf11_14_U0_l1_filter_data_1_we0; +wire [14:0] tdf11_14_U0_l1_filter_data_1_address1; +wire tdf11_14_U0_l1_filter_data_1_ce1; +wire [63:0] tdf11_14_U0_l1_filter_data_1_d1; +wire tdf11_14_U0_l1_filter_data_1_we1; +wire [14:0] tdf11_14_U0_l1_filter_data_2_address0; +wire tdf11_14_U0_l1_filter_data_2_ce0; +wire [63:0] tdf11_14_U0_l1_filter_data_2_d0; +wire tdf11_14_U0_l1_filter_data_2_we0; +wire [14:0] tdf11_14_U0_l1_filter_data_2_address1; +wire tdf11_14_U0_l1_filter_data_2_ce1; +wire [63:0] tdf11_14_U0_l1_filter_data_2_d1; +wire tdf11_14_U0_l1_filter_data_2_we1; +wire [14:0] tdf11_14_U0_l1_filter_data_3_address0; +wire tdf11_14_U0_l1_filter_data_3_ce0; +wire [63:0] tdf11_14_U0_l1_filter_data_3_d0; +wire tdf11_14_U0_l1_filter_data_3_we0; +wire [14:0] tdf11_14_U0_l1_filter_data_3_address1; +wire tdf11_14_U0_l1_filter_data_3_ce1; +wire [63:0] tdf11_14_U0_l1_filter_data_3_d1; +wire tdf11_14_U0_l1_filter_data_3_we1; +wire [13:0] tdf11_14_U0_l2_filter_data_0_address0; +wire tdf11_14_U0_l2_filter_data_0_ce0; +wire [15:0] tdf11_14_U0_l2_filter_data_0_d0; +wire tdf11_14_U0_l2_filter_data_0_we0; +wire [13:0] tdf11_14_U0_l2_filter_data_0_address1; +wire tdf11_14_U0_l2_filter_data_0_ce1; +wire [15:0] tdf11_14_U0_l2_filter_data_0_d1; +wire tdf11_14_U0_l2_filter_data_0_we1; +wire [13:0] tdf11_14_U0_l2_filter_data_1_address0; +wire tdf11_14_U0_l2_filter_data_1_ce0; +wire [15:0] tdf11_14_U0_l2_filter_data_1_d0; +wire tdf11_14_U0_l2_filter_data_1_we0; +wire [13:0] tdf11_14_U0_l2_filter_data_1_address1; +wire tdf11_14_U0_l2_filter_data_1_ce1; +wire [15:0] tdf11_14_U0_l2_filter_data_1_d1; +wire tdf11_14_U0_l2_filter_data_1_we1; +wire [13:0] tdf11_14_U0_l2_filter_data_2_address0; +wire tdf11_14_U0_l2_filter_data_2_ce0; +wire [15:0] tdf11_14_U0_l2_filter_data_2_d0; +wire tdf11_14_U0_l2_filter_data_2_we0; +wire [13:0] tdf11_14_U0_l2_filter_data_2_address1; +wire tdf11_14_U0_l2_filter_data_2_ce1; +wire [15:0] tdf11_14_U0_l2_filter_data_2_d1; +wire tdf11_14_U0_l2_filter_data_2_we1; +wire [13:0] tdf11_14_U0_l2_filter_data_3_address0; +wire tdf11_14_U0_l2_filter_data_3_ce0; +wire [15:0] tdf11_14_U0_l2_filter_data_3_d0; +wire tdf11_14_U0_l2_filter_data_3_we0; +wire [13:0] tdf11_14_U0_l2_filter_data_3_address1; +wire tdf11_14_U0_l2_filter_data_3_ce1; +wire [15:0] tdf11_14_U0_l2_filter_data_3_d1; +wire tdf11_14_U0_l2_filter_data_3_we1; +wire [8:0] tdf11_14_U0_l1_adjustments_address0; +wire tdf11_14_U0_l1_adjustments_ce0; +wire [47:0] tdf11_14_U0_l1_adjustments_d0; +wire tdf11_14_U0_l1_adjustments_we0; +wire [8:0] tdf11_14_U0_l1_adjustments_address1; +wire tdf11_14_U0_l1_adjustments_ce1; +wire [47:0] tdf11_14_U0_l1_adjustments_d1; +wire tdf11_14_U0_l1_adjustments_we1; +wire [6:0] tdf11_14_U0_l2_adjustments_address0; +wire tdf11_14_U0_l2_adjustments_ce0; +wire [47:0] tdf11_14_U0_l2_adjustments_d0; +wire tdf11_14_U0_l2_adjustments_we0; +wire [6:0] tdf11_14_U0_l2_adjustments_address1; +wire tdf11_14_U0_l2_adjustments_ce1; +wire [47:0] tdf11_14_U0_l2_adjustments_d1; +wire tdf11_14_U0_l2_adjustments_we1; +wire tdf11_14_U0_in_data_read; +wire tdf11_14_U0_out_data_full_n; +wire tdf11_14_U0_out_data_write; +wire tdf11_14_U0_ap_start; +wire tdf11_14_U0_ap_done; +wire tdf11_14_U0_ap_ready; +wire tdf11_14_U0_ap_idle; +wire tdf11_14_U0_ap_continue; +wire ap_channel_done_tdf12_fmaps; +wire [12:0] tdf12_13_U0_in_data_address0; +wire tdf12_13_U0_in_data_ce0; +wire [63:0] tdf12_13_U0_in_data_d0; +wire tdf12_13_U0_in_data_we0; +wire [12:0] tdf12_13_U0_in_data_address1; +wire tdf12_13_U0_in_data_ce1; +wire [63:0] tdf12_13_U0_in_data_d1; +wire tdf12_13_U0_in_data_we1; +wire [15:0] tdf12_13_U0_out_data_address0; +wire tdf12_13_U0_out_data_ce0; +wire [63:0] tdf12_13_U0_out_data_d0; +wire tdf12_13_U0_out_data_we0; +wire [15:0] tdf12_13_U0_out_data_address1; +wire tdf12_13_U0_out_data_ce1; +wire [63:0] tdf12_13_U0_out_data_d1; +wire tdf12_13_U0_out_data_we1; +wire [14:0] tdf12_13_U0_filter_data_0_address0; +wire tdf12_13_U0_filter_data_0_ce0; +wire [31:0] tdf12_13_U0_filter_data_0_d0; +wire tdf12_13_U0_filter_data_0_we0; +wire [14:0] tdf12_13_U0_filter_data_0_address1; +wire tdf12_13_U0_filter_data_0_ce1; +wire [31:0] tdf12_13_U0_filter_data_0_d1; +wire tdf12_13_U0_filter_data_0_we1; +wire [14:0] tdf12_13_U0_filter_data_1_address0; +wire tdf12_13_U0_filter_data_1_ce0; +wire [31:0] tdf12_13_U0_filter_data_1_d0; +wire tdf12_13_U0_filter_data_1_we0; +wire [14:0] tdf12_13_U0_filter_data_1_address1; +wire tdf12_13_U0_filter_data_1_ce1; +wire [31:0] tdf12_13_U0_filter_data_1_d1; +wire tdf12_13_U0_filter_data_1_we1; +wire [9:0] tdf12_13_U0_adjustments_address0; +wire tdf12_13_U0_adjustments_ce0; +wire [47:0] tdf12_13_U0_adjustments_d0; +wire tdf12_13_U0_adjustments_we0; +wire [9:0] tdf12_13_U0_adjustments_address1; +wire tdf12_13_U0_adjustments_ce1; +wire [47:0] tdf12_13_U0_adjustments_d1; +wire tdf12_13_U0_adjustments_we1; +wire tdf12_13_U0_in_data_read; +wire tdf12_13_U0_out_data_full_n; +wire tdf12_13_U0_out_data_write; +wire tdf12_13_U0_ap_start; +wire tdf12_13_U0_ap_done; +wire tdf12_13_U0_ap_ready; +wire tdf12_13_U0_ap_idle; +wire tdf12_13_U0_ap_continue; +wire ap_channel_done_final_fmaps; +wire td_fused_axi_out_U0_ap_start; +wire td_fused_axi_out_U0_ap_done; +wire td_fused_axi_out_U0_ap_continue; +wire td_fused_axi_out_U0_ap_idle; +wire td_fused_axi_out_U0_ap_ready; +wire [15:0] td_fused_axi_out_U0_fmaps_address0; +wire td_fused_axi_out_U0_fmaps_ce0; +wire [15:0] td_fused_axi_out_U0_stream_out_TDATA; +wire td_fused_axi_out_U0_stream_out_TVALID; +wire [1:0] td_fused_axi_out_U0_stream_out_TKEEP; +wire [1:0] td_fused_axi_out_U0_stream_out_TSTRB; +wire [0:0] td_fused_axi_out_U0_stream_out_TLAST; +wire ap_sync_continue; +wire tdf1_fmaps_i_full_n; +wire tdf1_fmaps_t_empty_n; +wire [63:0] tdf1_fmaps_t_d0; +wire tdf1_fmaps_t_we0; +wire tdf2_fmaps_i_full_n; +wire tdf2_fmaps_t_empty_n; +wire [63:0] tdf2_fmaps_t_d0; +wire tdf2_fmaps_t_we0; +wire tdf3_fmaps_i_full_n; +wire tdf3_fmaps_t_empty_n; +wire [63:0] tdf3_fmaps_t_d0; +wire tdf3_fmaps_t_we0; +wire tdf4_fmaps_i_full_n; +wire tdf4_fmaps_t_empty_n; +wire [63:0] tdf4_fmaps_t_d0; +wire tdf4_fmaps_t_we0; +wire tdf5_fmaps_i_full_n; +wire tdf5_fmaps_t_empty_n; +wire [63:0] tdf5_fmaps_t_d0; +wire tdf5_fmaps_t_we0; +wire tdf6_fmaps_i_full_n; +wire tdf6_fmaps_t_empty_n; +wire [63:0] tdf6_fmaps_t_d0; +wire tdf6_fmaps_t_we0; +wire tdf7_fmaps_i_full_n; +wire tdf7_fmaps_t_empty_n; +wire [63:0] tdf7_fmaps_t_d0; +wire tdf7_fmaps_t_we0; +wire tdf8_fmaps_i_full_n; +wire tdf8_fmaps_t_empty_n; +wire [63:0] tdf8_fmaps_t_d0; +wire tdf8_fmaps_t_we0; +wire tdf9_fmaps_i_full_n; +wire tdf9_fmaps_t_empty_n; +wire [63:0] tdf9_fmaps_t_d0; +wire tdf9_fmaps_t_we0; +wire tdf10_fmaps_i_full_n; +wire tdf10_fmaps_t_empty_n; +wire [63:0] tdf10_fmaps_t_d0; +wire tdf10_fmaps_t_we0; +wire tdf11_fmaps_i_full_n; +wire tdf11_fmaps_t_empty_n; +wire [63:0] tdf11_fmaps_t_d0; +wire tdf11_fmaps_t_we0; +wire tdf12_fmaps_i_full_n; +wire tdf12_fmaps_t_empty_n; +wire [63:0] tdf12_fmaps_t_d0; +wire tdf12_fmaps_t_we0; +wire final_fmaps_i_full_n; +wire final_fmaps_t_empty_n; +wire [63:0] final_fmaps_t_d0; +wire final_fmaps_t_we0; +wire ap_sync_done; +wire ap_sync_ready; +wire td_fused_axi_in_U0_start_full_n; +wire td_fused_axi_in_U0_start_write; +wire tdf1_114_U0_start_full_n; +wire tdf1_114_U0_start_write; +wire tdf2_113_U0_start_full_n; +wire tdf2_113_U0_start_write; +wire tdf3_112_U0_start_full_n; +wire tdf3_112_U0_start_write; +wire tdf4_111_U0_start_full_n; +wire tdf4_111_U0_start_write; +wire tdf5_110_U0_start_full_n; +wire tdf5_110_U0_start_write; +wire tdf6_19_U0_start_full_n; +wire tdf6_19_U0_start_write; +wire tdf7_18_U0_start_full_n; +wire tdf7_18_U0_start_write; +wire tdf8_17_U0_start_full_n; +wire tdf8_17_U0_start_write; +wire tdf9_16_U0_start_full_n; +wire tdf9_16_U0_start_write; +wire tdf10_15_U0_start_full_n; +wire tdf10_15_U0_start_write; +wire tdf11_14_U0_start_full_n; +wire tdf11_14_U0_start_write; +wire tdf12_13_U0_start_full_n; +wire tdf12_13_U0_start_write; +wire td_fused_axi_out_U0_start_full_n; +wire td_fused_axi_out_U0_start_write; + +td_fused_top_td_fused_tdf1_fmaps #( + .DataWidth( 64 ), + .AddressRange( 50176 ), + .AddressWidth( 16 )) +tdf1_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(td_fused_axi_in_U0_ap_done), + .i_full_n(tdf1_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(16'd0), + .i_q0(tdf1_fmaps_i_q0), + .i_ce1(td_fused_axi_in_U0_fmaps_ce1), + .i_we1(td_fused_axi_in_U0_fmaps_we1), + .i_address1(td_fused_axi_in_U0_fmaps_address1), + .i_d1(td_fused_axi_in_U0_fmaps_d1), + .t_ce(1'b1), + .t_read(tdf1_114_U0_ap_ready), + .t_empty_n(tdf1_fmaps_t_empty_n), + .t_ce0(tdf1_114_U0_in_data_ce0), + .t_address0(tdf1_114_U0_in_data_address0), + .t_q0(tdf1_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(16'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf1_fmaps #( + .DataWidth( 64 ), + .AddressRange( 50176 ), + .AddressWidth( 16 )) +tdf2_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf1_114_U0_ap_done), + .i_full_n(tdf2_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(16'd0), + .i_q0(tdf2_fmaps_i_q0), + .i_ce1(tdf1_114_U0_out_data_ce1), + .i_we1(tdf1_114_U0_out_data_we1), + .i_address1(tdf1_114_U0_out_data_address1), + .i_d1(tdf1_114_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf2_113_U0_ap_ready), + .t_empty_n(tdf2_fmaps_t_empty_n), + .t_ce0(tdf2_113_U0_in_data_ce0), + .t_address0(tdf2_113_U0_in_data_address0), + .t_q0(tdf2_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(16'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf3_fmaps #( + .DataWidth( 64 ), + .AddressRange( 25088 ), + .AddressWidth( 15 )) +tdf3_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf2_113_U0_ap_done), + .i_full_n(tdf3_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(15'd0), + .i_q0(tdf3_fmaps_i_q0), + .i_ce1(tdf2_113_U0_out_data_ce1), + .i_we1(tdf2_113_U0_out_data_we1), + .i_address1(tdf2_113_U0_out_data_address1), + .i_d1(tdf2_113_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf3_112_U0_ap_ready), + .t_empty_n(tdf3_fmaps_t_empty_n), + .t_ce0(tdf3_112_U0_in_data_ce0), + .t_address0(tdf3_112_U0_in_data_address0), + .t_q0(tdf3_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(15'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf4_fmaps #( + .DataWidth( 64 ), + .AddressRange( 12544 ), + .AddressWidth( 14 )) +tdf4_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf3_112_U0_ap_done), + .i_full_n(tdf4_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(14'd0), + .i_q0(tdf4_fmaps_i_q0), + .i_ce1(tdf3_112_U0_out_data_ce1), + .i_we1(tdf3_112_U0_out_data_we1), + .i_address1(tdf3_112_U0_out_data_address1), + .i_d1(tdf3_112_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf4_111_U0_ap_ready), + .t_empty_n(tdf4_fmaps_t_empty_n), + .t_ce0(tdf4_111_U0_in_data_ce0), + .t_address0(tdf4_111_U0_in_data_address0), + .t_q0(tdf4_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(14'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf4_fmaps #( + .DataWidth( 64 ), + .AddressRange( 12544 ), + .AddressWidth( 14 )) +tdf5_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf4_111_U0_ap_done), + .i_full_n(tdf5_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(14'd0), + .i_q0(tdf5_fmaps_i_q0), + .i_ce1(tdf4_111_U0_out_data_ce1), + .i_we1(tdf4_111_U0_out_data_we1), + .i_address1(tdf4_111_U0_out_data_address1), + .i_d1(tdf4_111_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf5_110_U0_ap_ready), + .t_empty_n(tdf5_fmaps_t_empty_n), + .t_ce0(tdf5_110_U0_in_data_ce0), + .t_address0(tdf5_110_U0_in_data_address0), + .t_q0(tdf5_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(14'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf3_fmaps #( + .DataWidth( 64 ), + .AddressRange( 25088 ), + .AddressWidth( 15 )) +tdf6_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf5_110_U0_ap_done), + .i_full_n(tdf6_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(15'd0), + .i_q0(tdf6_fmaps_i_q0), + .i_ce1(tdf5_110_U0_out_data_ce1), + .i_we1(tdf5_110_U0_out_data_we1), + .i_address1(tdf5_110_U0_out_data_address1), + .i_d1(tdf5_110_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf6_19_U0_ap_ready), + .t_empty_n(tdf6_fmaps_t_empty_n), + .t_ce0(tdf6_19_U0_in_data_ce0), + .t_address0(tdf6_19_U0_in_data_address0), + .t_q0(tdf6_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(15'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf7_fmaps #( + .DataWidth( 64 ), + .AddressRange( 6272 ), + .AddressWidth( 13 )) +tdf7_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf6_19_U0_ap_done), + .i_full_n(tdf7_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(13'd0), + .i_q0(tdf7_fmaps_i_q0), + .i_ce1(tdf6_19_U0_out_data_ce1), + .i_we1(tdf6_19_U0_out_data_we1), + .i_address1(tdf6_19_U0_out_data_address1), + .i_d1(tdf6_19_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf7_18_U0_ap_ready), + .t_empty_n(tdf7_fmaps_t_empty_n), + .t_ce0(tdf7_18_U0_in_data_ce0), + .t_address0(tdf7_18_U0_in_data_address0), + .t_q0(tdf7_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(13'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf7_fmaps #( + .DataWidth( 64 ), + .AddressRange( 6272 ), + .AddressWidth( 13 )) +tdf8_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf7_18_U0_ap_done), + .i_full_n(tdf8_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(13'd0), + .i_q0(tdf8_fmaps_i_q0), + .i_ce1(tdf7_18_U0_out_data_ce1), + .i_we1(tdf7_18_U0_out_data_we1), + .i_address1(tdf7_18_U0_out_data_address1), + .i_d1(tdf7_18_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf8_17_U0_ap_ready), + .t_empty_n(tdf8_fmaps_t_empty_n), + .t_ce0(tdf8_17_U0_in_data_ce0), + .t_address0(tdf8_17_U0_in_data_address0), + .t_q0(tdf8_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(13'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf4_fmaps #( + .DataWidth( 64 ), + .AddressRange( 12544 ), + .AddressWidth( 14 )) +tdf9_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf8_17_U0_ap_done), + .i_full_n(tdf9_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(14'd0), + .i_q0(tdf9_fmaps_i_q0), + .i_ce1(tdf8_17_U0_out_data_ce1), + .i_we1(tdf8_17_U0_out_data_we1), + .i_address1(tdf8_17_U0_out_data_address1), + .i_d1(tdf8_17_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf9_16_U0_ap_ready), + .t_empty_n(tdf9_fmaps_t_empty_n), + .t_ce0(tdf9_16_U0_in_data_ce0), + .t_address0(tdf9_16_U0_in_data_address0), + .t_q0(tdf9_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(14'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf10_fmaps #( + .DataWidth( 64 ), + .AddressRange( 3136 ), + .AddressWidth( 12 )) +tdf10_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf9_16_U0_ap_done), + .i_full_n(tdf10_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(12'd0), + .i_q0(tdf10_fmaps_i_q0), + .i_ce1(tdf9_16_U0_out_data_ce1), + .i_we1(tdf9_16_U0_out_data_we1), + .i_address1(tdf9_16_U0_out_data_address1), + .i_d1(tdf9_16_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf10_15_U0_ap_ready), + .t_empty_n(tdf10_fmaps_t_empty_n), + .t_ce0(tdf10_15_U0_in_data_ce0), + .t_address0(tdf10_15_U0_in_data_address0), + .t_q0(tdf10_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(12'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf10_fmaps #( + .DataWidth( 64 ), + .AddressRange( 3136 ), + .AddressWidth( 12 )) +tdf11_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf10_15_U0_ap_done), + .i_full_n(tdf11_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(12'd0), + .i_q0(tdf11_fmaps_i_q0), + .i_ce1(tdf10_15_U0_out_data_ce1), + .i_we1(tdf10_15_U0_out_data_we1), + .i_address1(tdf10_15_U0_out_data_address1), + .i_d1(tdf10_15_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf11_14_U0_ap_ready), + .t_empty_n(tdf11_fmaps_t_empty_n), + .t_ce0(tdf11_14_U0_in_data_ce0), + .t_address0(tdf11_14_U0_in_data_address0), + .t_q0(tdf11_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(12'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf7_fmaps #( + .DataWidth( 64 ), + .AddressRange( 6272 ), + .AddressWidth( 13 )) +tdf12_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf11_14_U0_ap_done), + .i_full_n(tdf12_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(13'd0), + .i_q0(tdf12_fmaps_i_q0), + .i_ce1(tdf11_14_U0_out_data_ce1), + .i_we1(tdf11_14_U0_out_data_we1), + .i_address1(tdf11_14_U0_out_data_address1), + .i_d1(tdf11_14_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf12_13_U0_ap_ready), + .t_empty_n(tdf12_fmaps_t_empty_n), + .t_ce0(tdf12_13_U0_in_data_ce0), + .t_address0(tdf12_13_U0_in_data_address0), + .t_q0(tdf12_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(13'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_final_fmaps #( + .DataWidth( 64 ), + .AddressRange( 49000 ), + .AddressWidth( 16 )) +final_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf12_13_U0_ap_done), + .i_full_n(final_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(16'd0), + .i_q0(final_fmaps_i_q0), + .i_ce1(tdf12_13_U0_out_data_ce1), + .i_we1(tdf12_13_U0_out_data_we1), + .i_address1(tdf12_13_U0_out_data_address1), + .i_d1(tdf12_13_U0_out_data_d1), + .t_ce(1'b1), + .t_read(td_fused_axi_out_U0_ap_ready), + .t_empty_n(final_fmaps_t_empty_n), + .t_ce0(td_fused_axi_out_U0_fmaps_ce0), + .t_address0(td_fused_axi_out_U0_fmaps_address0), + .t_q0(final_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(16'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_axi_in td_fused_axi_in_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(td_fused_axi_in_U0_ap_start), + .ap_done(td_fused_axi_in_U0_ap_done), + .ap_continue(td_fused_axi_in_U0_ap_continue), + .ap_idle(td_fused_axi_in_U0_ap_idle), + .ap_ready(td_fused_axi_in_U0_ap_ready), + .stream_in_TDATA(stream_in_TDATA), + .stream_in_TVALID(stream_in_TVALID), + .stream_in_TREADY(td_fused_axi_in_U0_stream_in_TREADY), + .stream_in_TKEEP(stream_in_TKEEP), + .stream_in_TSTRB(stream_in_TSTRB), + .stream_in_TLAST(stream_in_TLAST), + .fmaps_address1(td_fused_axi_in_U0_fmaps_address1), + .fmaps_ce1(td_fused_axi_in_U0_fmaps_ce1), + .fmaps_we1(td_fused_axi_in_U0_fmaps_we1), + .fmaps_d1(td_fused_axi_in_U0_fmaps_d1) +); + +td_fused_top_tdf1_114 tdf1_114_U0( + .in_data_address0(tdf1_114_U0_in_data_address0), + .in_data_ce0(tdf1_114_U0_in_data_ce0), + .in_data_d0(tdf1_114_U0_in_data_d0), + .in_data_q0(tdf1_fmaps_t_q0), + .in_data_we0(tdf1_114_U0_in_data_we0), + .in_data_address1(tdf1_114_U0_in_data_address1), + .in_data_ce1(tdf1_114_U0_in_data_ce1), + .in_data_d1(tdf1_114_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf1_114_U0_in_data_we1), + .out_data_address0(tdf1_114_U0_out_data_address0), + .out_data_ce0(tdf1_114_U0_out_data_ce0), + .out_data_d0(tdf1_114_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf1_114_U0_out_data_we0), + .out_data_address1(tdf1_114_U0_out_data_address1), + .out_data_ce1(tdf1_114_U0_out_data_ce1), + .out_data_d1(tdf1_114_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf1_114_U0_out_data_we1), + .filter_data_0_address0(tdf1_114_U0_filter_data_0_address0), + .filter_data_0_ce0(tdf1_114_U0_filter_data_0_ce0), + .filter_data_0_d0(tdf1_114_U0_filter_data_0_d0), + .filter_data_0_q0(tdf1_filters_0_q0), + .filter_data_0_we0(tdf1_114_U0_filter_data_0_we0), + .filter_data_0_address1(tdf1_114_U0_filter_data_0_address1), + .filter_data_0_ce1(tdf1_114_U0_filter_data_0_ce1), + .filter_data_0_d1(tdf1_114_U0_filter_data_0_d1), + .filter_data_0_q1(16'd0), + .filter_data_0_we1(tdf1_114_U0_filter_data_0_we1), + .filter_data_1_address0(tdf1_114_U0_filter_data_1_address0), + .filter_data_1_ce0(tdf1_114_U0_filter_data_1_ce0), + .filter_data_1_d0(tdf1_114_U0_filter_data_1_d0), + .filter_data_1_q0(tdf1_filters_1_q0), + .filter_data_1_we0(tdf1_114_U0_filter_data_1_we0), + .filter_data_1_address1(tdf1_114_U0_filter_data_1_address1), + .filter_data_1_ce1(tdf1_114_U0_filter_data_1_ce1), + .filter_data_1_d1(tdf1_114_U0_filter_data_1_d1), + .filter_data_1_q1(16'd0), + .filter_data_1_we1(tdf1_114_U0_filter_data_1_we1), + .filter_data_2_address0(tdf1_114_U0_filter_data_2_address0), + .filter_data_2_ce0(tdf1_114_U0_filter_data_2_ce0), + .filter_data_2_d0(tdf1_114_U0_filter_data_2_d0), + .filter_data_2_q0(tdf1_filters_2_q0), + .filter_data_2_we0(tdf1_114_U0_filter_data_2_we0), + .filter_data_2_address1(tdf1_114_U0_filter_data_2_address1), + .filter_data_2_ce1(tdf1_114_U0_filter_data_2_ce1), + .filter_data_2_d1(tdf1_114_U0_filter_data_2_d1), + .filter_data_2_q1(16'd0), + .filter_data_2_we1(tdf1_114_U0_filter_data_2_we1), + .filter_data_3_address0(tdf1_114_U0_filter_data_3_address0), + .filter_data_3_ce0(tdf1_114_U0_filter_data_3_ce0), + .filter_data_3_d0(tdf1_114_U0_filter_data_3_d0), + .filter_data_3_q0(tdf1_filters_3_q0), + .filter_data_3_we0(tdf1_114_U0_filter_data_3_we0), + .filter_data_3_address1(tdf1_114_U0_filter_data_3_address1), + .filter_data_3_ce1(tdf1_114_U0_filter_data_3_ce1), + .filter_data_3_d1(tdf1_114_U0_filter_data_3_d1), + .filter_data_3_q1(16'd0), + .filter_data_3_we1(tdf1_114_U0_filter_data_3_we1), + .adjustments_address0(tdf1_114_U0_adjustments_address0), + .adjustments_ce0(tdf1_114_U0_adjustments_ce0), + .adjustments_d0(tdf1_114_U0_adjustments_d0), + .adjustments_q0(tdf1_adjustments_q0), + .adjustments_we0(tdf1_114_U0_adjustments_we0), + .adjustments_address1(tdf1_114_U0_adjustments_address1), + .adjustments_ce1(tdf1_114_U0_adjustments_ce1), + .adjustments_d1(tdf1_114_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf1_114_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf1_114_U0_in_data_read), + .out_data_full_n(tdf2_fmaps_i_full_n), + .out_data_write(tdf1_114_U0_out_data_write), + .ap_start(tdf1_114_U0_ap_start), + .ap_done(tdf1_114_U0_ap_done), + .ap_ready(tdf1_114_U0_ap_ready), + .ap_idle(tdf1_114_U0_ap_idle), + .ap_continue(tdf1_114_U0_ap_continue) +); + +td_fused_top_tdf2_113 tdf2_113_U0( + .in_data_address0(tdf2_113_U0_in_data_address0), + .in_data_ce0(tdf2_113_U0_in_data_ce0), + .in_data_d0(tdf2_113_U0_in_data_d0), + .in_data_q0(tdf2_fmaps_t_q0), + .in_data_we0(tdf2_113_U0_in_data_we0), + .in_data_address1(tdf2_113_U0_in_data_address1), + .in_data_ce1(tdf2_113_U0_in_data_ce1), + .in_data_d1(tdf2_113_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf2_113_U0_in_data_we1), + .out_data_address0(tdf2_113_U0_out_data_address0), + .out_data_ce0(tdf2_113_U0_out_data_ce0), + .out_data_d0(tdf2_113_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf2_113_U0_out_data_we0), + .out_data_address1(tdf2_113_U0_out_data_address1), + .out_data_ce1(tdf2_113_U0_out_data_ce1), + .out_data_d1(tdf2_113_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf2_113_U0_out_data_we1), + .filter_data_0_address0(tdf2_113_U0_filter_data_0_address0), + .filter_data_0_ce0(tdf2_113_U0_filter_data_0_ce0), + .filter_data_0_d0(tdf2_113_U0_filter_data_0_d0), + .filter_data_0_q0(tdf2_filters_0_q0), + .filter_data_0_we0(tdf2_113_U0_filter_data_0_we0), + .filter_data_0_address1(tdf2_113_U0_filter_data_0_address1), + .filter_data_0_ce1(tdf2_113_U0_filter_data_0_ce1), + .filter_data_0_d1(tdf2_113_U0_filter_data_0_d1), + .filter_data_0_q1(32'd0), + .filter_data_0_we1(tdf2_113_U0_filter_data_0_we1), + .filter_data_1_address0(tdf2_113_U0_filter_data_1_address0), + .filter_data_1_ce0(tdf2_113_U0_filter_data_1_ce0), + .filter_data_1_d0(tdf2_113_U0_filter_data_1_d0), + .filter_data_1_q0(tdf2_filters_1_q0), + .filter_data_1_we0(tdf2_113_U0_filter_data_1_we0), + .filter_data_1_address1(tdf2_113_U0_filter_data_1_address1), + .filter_data_1_ce1(tdf2_113_U0_filter_data_1_ce1), + .filter_data_1_d1(tdf2_113_U0_filter_data_1_d1), + .filter_data_1_q1(32'd0), + .filter_data_1_we1(tdf2_113_U0_filter_data_1_we1), + .filter_data_2_address0(tdf2_113_U0_filter_data_2_address0), + .filter_data_2_ce0(tdf2_113_U0_filter_data_2_ce0), + .filter_data_2_d0(tdf2_113_U0_filter_data_2_d0), + .filter_data_2_q0(tdf2_filters_2_q0), + .filter_data_2_we0(tdf2_113_U0_filter_data_2_we0), + .filter_data_2_address1(tdf2_113_U0_filter_data_2_address1), + .filter_data_2_ce1(tdf2_113_U0_filter_data_2_ce1), + .filter_data_2_d1(tdf2_113_U0_filter_data_2_d1), + .filter_data_2_q1(32'd0), + .filter_data_2_we1(tdf2_113_U0_filter_data_2_we1), + .filter_data_3_address0(tdf2_113_U0_filter_data_3_address0), + .filter_data_3_ce0(tdf2_113_U0_filter_data_3_ce0), + .filter_data_3_d0(tdf2_113_U0_filter_data_3_d0), + .filter_data_3_q0(tdf2_filters_3_q0), + .filter_data_3_we0(tdf2_113_U0_filter_data_3_we0), + .filter_data_3_address1(tdf2_113_U0_filter_data_3_address1), + .filter_data_3_ce1(tdf2_113_U0_filter_data_3_ce1), + .filter_data_3_d1(tdf2_113_U0_filter_data_3_d1), + .filter_data_3_q1(32'd0), + .filter_data_3_we1(tdf2_113_U0_filter_data_3_we1), + .adjustments_address0(tdf2_113_U0_adjustments_address0), + .adjustments_ce0(tdf2_113_U0_adjustments_ce0), + .adjustments_d0(tdf2_113_U0_adjustments_d0), + .adjustments_q0(tdf2_adjustments_q0), + .adjustments_we0(tdf2_113_U0_adjustments_we0), + .adjustments_address1(tdf2_113_U0_adjustments_address1), + .adjustments_ce1(tdf2_113_U0_adjustments_ce1), + .adjustments_d1(tdf2_113_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf2_113_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf2_113_U0_in_data_read), + .out_data_full_n(tdf3_fmaps_i_full_n), + .out_data_write(tdf2_113_U0_out_data_write), + .ap_start(tdf2_113_U0_ap_start), + .ap_done(tdf2_113_U0_ap_done), + .ap_ready(tdf2_113_U0_ap_ready), + .ap_idle(tdf2_113_U0_ap_idle), + .ap_continue(tdf2_113_U0_ap_continue) +); + +td_fused_top_tdf3_112 tdf3_112_U0( + .in_data_address0(tdf3_112_U0_in_data_address0), + .in_data_ce0(tdf3_112_U0_in_data_ce0), + .in_data_d0(tdf3_112_U0_in_data_d0), + .in_data_q0(tdf3_fmaps_t_q0), + .in_data_we0(tdf3_112_U0_in_data_we0), + .in_data_address1(tdf3_112_U0_in_data_address1), + .in_data_ce1(tdf3_112_U0_in_data_ce1), + .in_data_d1(tdf3_112_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf3_112_U0_in_data_we1), + .out_data_address0(tdf3_112_U0_out_data_address0), + .out_data_ce0(tdf3_112_U0_out_data_ce0), + .out_data_d0(tdf3_112_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf3_112_U0_out_data_we0), + .out_data_address1(tdf3_112_U0_out_data_address1), + .out_data_ce1(tdf3_112_U0_out_data_ce1), + .out_data_d1(tdf3_112_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf3_112_U0_out_data_we1), + .filter_data_address0(tdf3_112_U0_filter_data_address0), + .filter_data_ce0(tdf3_112_U0_filter_data_ce0), + .filter_data_d0(tdf3_112_U0_filter_data_d0), + .filter_data_q0(tdf3_filters_q0), + .filter_data_we0(tdf3_112_U0_filter_data_we0), + .filter_data_address1(tdf3_112_U0_filter_data_address1), + .filter_data_ce1(tdf3_112_U0_filter_data_ce1), + .filter_data_d1(tdf3_112_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(tdf3_112_U0_filter_data_we1), + .adjustments_address0(tdf3_112_U0_adjustments_address0), + .adjustments_ce0(tdf3_112_U0_adjustments_ce0), + .adjustments_d0(tdf3_112_U0_adjustments_d0), + .adjustments_q0(tdf3_adjustments_q0), + .adjustments_we0(tdf3_112_U0_adjustments_we0), + .adjustments_address1(tdf3_112_U0_adjustments_address1), + .adjustments_ce1(tdf3_112_U0_adjustments_ce1), + .adjustments_d1(tdf3_112_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf3_112_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf3_112_U0_in_data_read), + .out_data_full_n(tdf4_fmaps_i_full_n), + .out_data_write(tdf3_112_U0_out_data_write), + .ap_start(tdf3_112_U0_ap_start), + .ap_done(tdf3_112_U0_ap_done), + .ap_ready(tdf3_112_U0_ap_ready), + .ap_idle(tdf3_112_U0_ap_idle), + .ap_continue(tdf3_112_U0_ap_continue) +); + +td_fused_top_tdf4_111 tdf4_111_U0( + .in_data_address0(tdf4_111_U0_in_data_address0), + .in_data_ce0(tdf4_111_U0_in_data_ce0), + .in_data_d0(tdf4_111_U0_in_data_d0), + .in_data_q0(tdf4_fmaps_t_q0), + .in_data_we0(tdf4_111_U0_in_data_we0), + .in_data_address1(tdf4_111_U0_in_data_address1), + .in_data_ce1(tdf4_111_U0_in_data_ce1), + .in_data_d1(tdf4_111_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf4_111_U0_in_data_we1), + .out_data_address0(tdf4_111_U0_out_data_address0), + .out_data_ce0(tdf4_111_U0_out_data_ce0), + .out_data_d0(tdf4_111_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf4_111_U0_out_data_we0), + .out_data_address1(tdf4_111_U0_out_data_address1), + .out_data_ce1(tdf4_111_U0_out_data_ce1), + .out_data_d1(tdf4_111_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf4_111_U0_out_data_we1), + .l1_filter_data_0_address0(tdf4_111_U0_l1_filter_data_0_address0), + .l1_filter_data_0_ce0(tdf4_111_U0_l1_filter_data_0_ce0), + .l1_filter_data_0_d0(tdf4_111_U0_l1_filter_data_0_d0), + .l1_filter_data_0_q0(tdf4_filters_0_q0), + .l1_filter_data_0_we0(tdf4_111_U0_l1_filter_data_0_we0), + .l1_filter_data_0_address1(tdf4_111_U0_l1_filter_data_0_address1), + .l1_filter_data_0_ce1(tdf4_111_U0_l1_filter_data_0_ce1), + .l1_filter_data_0_d1(tdf4_111_U0_l1_filter_data_0_d1), + .l1_filter_data_0_q1(64'd0), + .l1_filter_data_0_we1(tdf4_111_U0_l1_filter_data_0_we1), + .l1_filter_data_1_address0(tdf4_111_U0_l1_filter_data_1_address0), + .l1_filter_data_1_ce0(tdf4_111_U0_l1_filter_data_1_ce0), + .l1_filter_data_1_d0(tdf4_111_U0_l1_filter_data_1_d0), + .l1_filter_data_1_q0(tdf4_filters_1_q0), + .l1_filter_data_1_we0(tdf4_111_U0_l1_filter_data_1_we0), + .l1_filter_data_1_address1(tdf4_111_U0_l1_filter_data_1_address1), + .l1_filter_data_1_ce1(tdf4_111_U0_l1_filter_data_1_ce1), + .l1_filter_data_1_d1(tdf4_111_U0_l1_filter_data_1_d1), + .l1_filter_data_1_q1(64'd0), + .l1_filter_data_1_we1(tdf4_111_U0_l1_filter_data_1_we1), + .l1_filter_data_2_address0(tdf4_111_U0_l1_filter_data_2_address0), + .l1_filter_data_2_ce0(tdf4_111_U0_l1_filter_data_2_ce0), + .l1_filter_data_2_d0(tdf4_111_U0_l1_filter_data_2_d0), + .l1_filter_data_2_q0(tdf4_filters_2_q0), + .l1_filter_data_2_we0(tdf4_111_U0_l1_filter_data_2_we0), + .l1_filter_data_2_address1(tdf4_111_U0_l1_filter_data_2_address1), + .l1_filter_data_2_ce1(tdf4_111_U0_l1_filter_data_2_ce1), + .l1_filter_data_2_d1(tdf4_111_U0_l1_filter_data_2_d1), + .l1_filter_data_2_q1(64'd0), + .l1_filter_data_2_we1(tdf4_111_U0_l1_filter_data_2_we1), + .l1_filter_data_3_address0(tdf4_111_U0_l1_filter_data_3_address0), + .l1_filter_data_3_ce0(tdf4_111_U0_l1_filter_data_3_ce0), + .l1_filter_data_3_d0(tdf4_111_U0_l1_filter_data_3_d0), + .l1_filter_data_3_q0(tdf4_filters_3_q0), + .l1_filter_data_3_we0(tdf4_111_U0_l1_filter_data_3_we0), + .l1_filter_data_3_address1(tdf4_111_U0_l1_filter_data_3_address1), + .l1_filter_data_3_ce1(tdf4_111_U0_l1_filter_data_3_ce1), + .l1_filter_data_3_d1(tdf4_111_U0_l1_filter_data_3_d1), + .l1_filter_data_3_q1(64'd0), + .l1_filter_data_3_we1(tdf4_111_U0_l1_filter_data_3_we1), + .l2_filter_data_0_address0(tdf4_111_U0_l2_filter_data_0_address0), + .l2_filter_data_0_ce0(tdf4_111_U0_l2_filter_data_0_ce0), + .l2_filter_data_0_d0(tdf4_111_U0_l2_filter_data_0_d0), + .l2_filter_data_0_q0(tdf4_l2_filters_0_q0), + .l2_filter_data_0_we0(tdf4_111_U0_l2_filter_data_0_we0), + .l2_filter_data_0_address1(tdf4_111_U0_l2_filter_data_0_address1), + .l2_filter_data_0_ce1(tdf4_111_U0_l2_filter_data_0_ce1), + .l2_filter_data_0_d1(tdf4_111_U0_l2_filter_data_0_d1), + .l2_filter_data_0_q1(tdf4_l2_filters_0_q1), + .l2_filter_data_0_we1(tdf4_111_U0_l2_filter_data_0_we1), + .l2_filter_data_1_address0(tdf4_111_U0_l2_filter_data_1_address0), + .l2_filter_data_1_ce0(tdf4_111_U0_l2_filter_data_1_ce0), + .l2_filter_data_1_d0(tdf4_111_U0_l2_filter_data_1_d0), + .l2_filter_data_1_q0(tdf4_l2_filters_1_q0), + .l2_filter_data_1_we0(tdf4_111_U0_l2_filter_data_1_we0), + .l2_filter_data_1_address1(tdf4_111_U0_l2_filter_data_1_address1), + .l2_filter_data_1_ce1(tdf4_111_U0_l2_filter_data_1_ce1), + .l2_filter_data_1_d1(tdf4_111_U0_l2_filter_data_1_d1), + .l2_filter_data_1_q1(tdf4_l2_filters_1_q1), + .l2_filter_data_1_we1(tdf4_111_U0_l2_filter_data_1_we1), + .l1_adjustments_address0(tdf4_111_U0_l1_adjustments_address0), + .l1_adjustments_ce0(tdf4_111_U0_l1_adjustments_ce0), + .l1_adjustments_d0(tdf4_111_U0_l1_adjustments_d0), + .l1_adjustments_q0(tdf4_adjustments_q0), + .l1_adjustments_we0(tdf4_111_U0_l1_adjustments_we0), + .l1_adjustments_address1(tdf4_111_U0_l1_adjustments_address1), + .l1_adjustments_ce1(tdf4_111_U0_l1_adjustments_ce1), + .l1_adjustments_d1(tdf4_111_U0_l1_adjustments_d1), + .l1_adjustments_q1(48'd0), + .l1_adjustments_we1(tdf4_111_U0_l1_adjustments_we1), + .l2_adjustments_address0(tdf4_111_U0_l2_adjustments_address0), + .l2_adjustments_ce0(tdf4_111_U0_l2_adjustments_ce0), + .l2_adjustments_d0(tdf4_111_U0_l2_adjustments_d0), + .l2_adjustments_q0(tdf4_l2_adjustments_q0), + .l2_adjustments_we0(tdf4_111_U0_l2_adjustments_we0), + .l2_adjustments_address1(tdf4_111_U0_l2_adjustments_address1), + .l2_adjustments_ce1(tdf4_111_U0_l2_adjustments_ce1), + .l2_adjustments_d1(tdf4_111_U0_l2_adjustments_d1), + .l2_adjustments_q1(48'd0), + .l2_adjustments_we1(tdf4_111_U0_l2_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf4_111_U0_in_data_read), + .out_data_full_n(tdf5_fmaps_i_full_n), + .out_data_write(tdf4_111_U0_out_data_write), + .ap_start(tdf4_111_U0_ap_start), + .ap_done(tdf4_111_U0_ap_done), + .ap_ready(tdf4_111_U0_ap_ready), + .ap_idle(tdf4_111_U0_ap_idle), + .ap_continue(tdf4_111_U0_ap_continue) +); + +td_fused_top_tdf5_110 tdf5_110_U0( + .in_data_address0(tdf5_110_U0_in_data_address0), + .in_data_ce0(tdf5_110_U0_in_data_ce0), + .in_data_d0(tdf5_110_U0_in_data_d0), + .in_data_q0(tdf5_fmaps_t_q0), + .in_data_we0(tdf5_110_U0_in_data_we0), + .in_data_address1(tdf5_110_U0_in_data_address1), + .in_data_ce1(tdf5_110_U0_in_data_ce1), + .in_data_d1(tdf5_110_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf5_110_U0_in_data_we1), + .out_data_address0(tdf5_110_U0_out_data_address0), + .out_data_ce0(tdf5_110_U0_out_data_ce0), + .out_data_d0(tdf5_110_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf5_110_U0_out_data_we0), + .out_data_address1(tdf5_110_U0_out_data_address1), + .out_data_ce1(tdf5_110_U0_out_data_ce1), + .out_data_d1(tdf5_110_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf5_110_U0_out_data_we1), + .filter_data_0_address0(tdf5_110_U0_filter_data_0_address0), + .filter_data_0_ce0(tdf5_110_U0_filter_data_0_ce0), + .filter_data_0_d0(tdf5_110_U0_filter_data_0_d0), + .filter_data_0_q0(tdf5_filters_0_q0), + .filter_data_0_we0(tdf5_110_U0_filter_data_0_we0), + .filter_data_0_address1(tdf5_110_U0_filter_data_0_address1), + .filter_data_0_ce1(tdf5_110_U0_filter_data_0_ce1), + .filter_data_0_d1(tdf5_110_U0_filter_data_0_d1), + .filter_data_0_q1(32'd0), + .filter_data_0_we1(tdf5_110_U0_filter_data_0_we1), + .filter_data_1_address0(tdf5_110_U0_filter_data_1_address0), + .filter_data_1_ce0(tdf5_110_U0_filter_data_1_ce0), + .filter_data_1_d0(tdf5_110_U0_filter_data_1_d0), + .filter_data_1_q0(tdf5_filters_1_q0), + .filter_data_1_we0(tdf5_110_U0_filter_data_1_we0), + .filter_data_1_address1(tdf5_110_U0_filter_data_1_address1), + .filter_data_1_ce1(tdf5_110_U0_filter_data_1_ce1), + .filter_data_1_d1(tdf5_110_U0_filter_data_1_d1), + .filter_data_1_q1(32'd0), + .filter_data_1_we1(tdf5_110_U0_filter_data_1_we1), + .filter_data_2_address0(tdf5_110_U0_filter_data_2_address0), + .filter_data_2_ce0(tdf5_110_U0_filter_data_2_ce0), + .filter_data_2_d0(tdf5_110_U0_filter_data_2_d0), + .filter_data_2_q0(tdf5_filters_2_q0), + .filter_data_2_we0(tdf5_110_U0_filter_data_2_we0), + .filter_data_2_address1(tdf5_110_U0_filter_data_2_address1), + .filter_data_2_ce1(tdf5_110_U0_filter_data_2_ce1), + .filter_data_2_d1(tdf5_110_U0_filter_data_2_d1), + .filter_data_2_q1(32'd0), + .filter_data_2_we1(tdf5_110_U0_filter_data_2_we1), + .filter_data_3_address0(tdf5_110_U0_filter_data_3_address0), + .filter_data_3_ce0(tdf5_110_U0_filter_data_3_ce0), + .filter_data_3_d0(tdf5_110_U0_filter_data_3_d0), + .filter_data_3_q0(tdf5_filters_3_q0), + .filter_data_3_we0(tdf5_110_U0_filter_data_3_we0), + .filter_data_3_address1(tdf5_110_U0_filter_data_3_address1), + .filter_data_3_ce1(tdf5_110_U0_filter_data_3_ce1), + .filter_data_3_d1(tdf5_110_U0_filter_data_3_d1), + .filter_data_3_q1(32'd0), + .filter_data_3_we1(tdf5_110_U0_filter_data_3_we1), + .adjustments_address0(tdf5_110_U0_adjustments_address0), + .adjustments_ce0(tdf5_110_U0_adjustments_ce0), + .adjustments_d0(tdf5_110_U0_adjustments_d0), + .adjustments_q0(tdf5_adjustments_q0), + .adjustments_we0(tdf5_110_U0_adjustments_we0), + .adjustments_address1(tdf5_110_U0_adjustments_address1), + .adjustments_ce1(tdf5_110_U0_adjustments_ce1), + .adjustments_d1(tdf5_110_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf5_110_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf5_110_U0_in_data_read), + .out_data_full_n(tdf6_fmaps_i_full_n), + .out_data_write(tdf5_110_U0_out_data_write), + .ap_start(tdf5_110_U0_ap_start), + .ap_done(tdf5_110_U0_ap_done), + .ap_ready(tdf5_110_U0_ap_ready), + .ap_idle(tdf5_110_U0_ap_idle), + .ap_continue(tdf5_110_U0_ap_continue) +); + +td_fused_top_tdf6_19 tdf6_19_U0( + .in_data_address0(tdf6_19_U0_in_data_address0), + .in_data_ce0(tdf6_19_U0_in_data_ce0), + .in_data_d0(tdf6_19_U0_in_data_d0), + .in_data_q0(tdf6_fmaps_t_q0), + .in_data_we0(tdf6_19_U0_in_data_we0), + .in_data_address1(tdf6_19_U0_in_data_address1), + .in_data_ce1(tdf6_19_U0_in_data_ce1), + .in_data_d1(tdf6_19_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf6_19_U0_in_data_we1), + .out_data_address0(tdf6_19_U0_out_data_address0), + .out_data_ce0(tdf6_19_U0_out_data_ce0), + .out_data_d0(tdf6_19_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf6_19_U0_out_data_we0), + .out_data_address1(tdf6_19_U0_out_data_address1), + .out_data_ce1(tdf6_19_U0_out_data_ce1), + .out_data_d1(tdf6_19_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf6_19_U0_out_data_we1), + .filter_data_address0(tdf6_19_U0_filter_data_address0), + .filter_data_ce0(tdf6_19_U0_filter_data_ce0), + .filter_data_d0(tdf6_19_U0_filter_data_d0), + .filter_data_q0(tdf6_filters_q0), + .filter_data_we0(tdf6_19_U0_filter_data_we0), + .filter_data_address1(tdf6_19_U0_filter_data_address1), + .filter_data_ce1(tdf6_19_U0_filter_data_ce1), + .filter_data_d1(tdf6_19_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(tdf6_19_U0_filter_data_we1), + .adjustments_address0(tdf6_19_U0_adjustments_address0), + .adjustments_ce0(tdf6_19_U0_adjustments_ce0), + .adjustments_d0(tdf6_19_U0_adjustments_d0), + .adjustments_q0(tdf6_adjustments_q0), + .adjustments_we0(tdf6_19_U0_adjustments_we0), + .adjustments_address1(tdf6_19_U0_adjustments_address1), + .adjustments_ce1(tdf6_19_U0_adjustments_ce1), + .adjustments_d1(tdf6_19_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf6_19_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf6_19_U0_in_data_read), + .out_data_full_n(tdf7_fmaps_i_full_n), + .out_data_write(tdf6_19_U0_out_data_write), + .ap_start(tdf6_19_U0_ap_start), + .ap_done(tdf6_19_U0_ap_done), + .ap_ready(tdf6_19_U0_ap_ready), + .ap_idle(tdf6_19_U0_ap_idle), + .ap_continue(tdf6_19_U0_ap_continue) +); + +td_fused_top_tdf7_18 tdf7_18_U0( + .in_data_address0(tdf7_18_U0_in_data_address0), + .in_data_ce0(tdf7_18_U0_in_data_ce0), + .in_data_d0(tdf7_18_U0_in_data_d0), + .in_data_q0(tdf7_fmaps_t_q0), + .in_data_we0(tdf7_18_U0_in_data_we0), + .in_data_address1(tdf7_18_U0_in_data_address1), + .in_data_ce1(tdf7_18_U0_in_data_ce1), + .in_data_d1(tdf7_18_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf7_18_U0_in_data_we1), + .out_data_address0(tdf7_18_U0_out_data_address0), + .out_data_ce0(tdf7_18_U0_out_data_ce0), + .out_data_d0(tdf7_18_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf7_18_U0_out_data_we0), + .out_data_address1(tdf7_18_U0_out_data_address1), + .out_data_ce1(tdf7_18_U0_out_data_ce1), + .out_data_d1(tdf7_18_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf7_18_U0_out_data_we1), + .l1_filter_data_0_address0(tdf7_18_U0_l1_filter_data_0_address0), + .l1_filter_data_0_ce0(tdf7_18_U0_l1_filter_data_0_ce0), + .l1_filter_data_0_d0(tdf7_18_U0_l1_filter_data_0_d0), + .l1_filter_data_0_q0(tdf7_filters_0_q0), + .l1_filter_data_0_we0(tdf7_18_U0_l1_filter_data_0_we0), + .l1_filter_data_0_address1(tdf7_18_U0_l1_filter_data_0_address1), + .l1_filter_data_0_ce1(tdf7_18_U0_l1_filter_data_0_ce1), + .l1_filter_data_0_d1(tdf7_18_U0_l1_filter_data_0_d1), + .l1_filter_data_0_q1(64'd0), + .l1_filter_data_0_we1(tdf7_18_U0_l1_filter_data_0_we1), + .l1_filter_data_1_address0(tdf7_18_U0_l1_filter_data_1_address0), + .l1_filter_data_1_ce0(tdf7_18_U0_l1_filter_data_1_ce0), + .l1_filter_data_1_d0(tdf7_18_U0_l1_filter_data_1_d0), + .l1_filter_data_1_q0(tdf7_filters_1_q0), + .l1_filter_data_1_we0(tdf7_18_U0_l1_filter_data_1_we0), + .l1_filter_data_1_address1(tdf7_18_U0_l1_filter_data_1_address1), + .l1_filter_data_1_ce1(tdf7_18_U0_l1_filter_data_1_ce1), + .l1_filter_data_1_d1(tdf7_18_U0_l1_filter_data_1_d1), + .l1_filter_data_1_q1(64'd0), + .l1_filter_data_1_we1(tdf7_18_U0_l1_filter_data_1_we1), + .l1_filter_data_2_address0(tdf7_18_U0_l1_filter_data_2_address0), + .l1_filter_data_2_ce0(tdf7_18_U0_l1_filter_data_2_ce0), + .l1_filter_data_2_d0(tdf7_18_U0_l1_filter_data_2_d0), + .l1_filter_data_2_q0(tdf7_filters_2_q0), + .l1_filter_data_2_we0(tdf7_18_U0_l1_filter_data_2_we0), + .l1_filter_data_2_address1(tdf7_18_U0_l1_filter_data_2_address1), + .l1_filter_data_2_ce1(tdf7_18_U0_l1_filter_data_2_ce1), + .l1_filter_data_2_d1(tdf7_18_U0_l1_filter_data_2_d1), + .l1_filter_data_2_q1(64'd0), + .l1_filter_data_2_we1(tdf7_18_U0_l1_filter_data_2_we1), + .l1_filter_data_3_address0(tdf7_18_U0_l1_filter_data_3_address0), + .l1_filter_data_3_ce0(tdf7_18_U0_l1_filter_data_3_ce0), + .l1_filter_data_3_d0(tdf7_18_U0_l1_filter_data_3_d0), + .l1_filter_data_3_q0(tdf7_filters_3_q0), + .l1_filter_data_3_we0(tdf7_18_U0_l1_filter_data_3_we0), + .l1_filter_data_3_address1(tdf7_18_U0_l1_filter_data_3_address1), + .l1_filter_data_3_ce1(tdf7_18_U0_l1_filter_data_3_ce1), + .l1_filter_data_3_d1(tdf7_18_U0_l1_filter_data_3_d1), + .l1_filter_data_3_q1(64'd0), + .l1_filter_data_3_we1(tdf7_18_U0_l1_filter_data_3_we1), + .l2_filter_data_0_address0(tdf7_18_U0_l2_filter_data_0_address0), + .l2_filter_data_0_ce0(tdf7_18_U0_l2_filter_data_0_ce0), + .l2_filter_data_0_d0(tdf7_18_U0_l2_filter_data_0_d0), + .l2_filter_data_0_q0(tdf7_l2_filters_0_q0), + .l2_filter_data_0_we0(tdf7_18_U0_l2_filter_data_0_we0), + .l2_filter_data_0_address1(tdf7_18_U0_l2_filter_data_0_address1), + .l2_filter_data_0_ce1(tdf7_18_U0_l2_filter_data_0_ce1), + .l2_filter_data_0_d1(tdf7_18_U0_l2_filter_data_0_d1), + .l2_filter_data_0_q1(tdf7_l2_filters_0_q1), + .l2_filter_data_0_we1(tdf7_18_U0_l2_filter_data_0_we1), + .l2_filter_data_1_address0(tdf7_18_U0_l2_filter_data_1_address0), + .l2_filter_data_1_ce0(tdf7_18_U0_l2_filter_data_1_ce0), + .l2_filter_data_1_d0(tdf7_18_U0_l2_filter_data_1_d0), + .l2_filter_data_1_q0(tdf7_l2_filters_1_q0), + .l2_filter_data_1_we0(tdf7_18_U0_l2_filter_data_1_we0), + .l2_filter_data_1_address1(tdf7_18_U0_l2_filter_data_1_address1), + .l2_filter_data_1_ce1(tdf7_18_U0_l2_filter_data_1_ce1), + .l2_filter_data_1_d1(tdf7_18_U0_l2_filter_data_1_d1), + .l2_filter_data_1_q1(tdf7_l2_filters_1_q1), + .l2_filter_data_1_we1(tdf7_18_U0_l2_filter_data_1_we1), + .l1_adjustments_address0(tdf7_18_U0_l1_adjustments_address0), + .l1_adjustments_ce0(tdf7_18_U0_l1_adjustments_ce0), + .l1_adjustments_d0(tdf7_18_U0_l1_adjustments_d0), + .l1_adjustments_q0(tdf7_adjustments_q0), + .l1_adjustments_we0(tdf7_18_U0_l1_adjustments_we0), + .l1_adjustments_address1(tdf7_18_U0_l1_adjustments_address1), + .l1_adjustments_ce1(tdf7_18_U0_l1_adjustments_ce1), + .l1_adjustments_d1(tdf7_18_U0_l1_adjustments_d1), + .l1_adjustments_q1(48'd0), + .l1_adjustments_we1(tdf7_18_U0_l1_adjustments_we1), + .l2_adjustments_address0(tdf7_18_U0_l2_adjustments_address0), + .l2_adjustments_ce0(tdf7_18_U0_l2_adjustments_ce0), + .l2_adjustments_d0(tdf7_18_U0_l2_adjustments_d0), + .l2_adjustments_q0(tdf7_l2_adjustments_q0), + .l2_adjustments_we0(tdf7_18_U0_l2_adjustments_we0), + .l2_adjustments_address1(tdf7_18_U0_l2_adjustments_address1), + .l2_adjustments_ce1(tdf7_18_U0_l2_adjustments_ce1), + .l2_adjustments_d1(tdf7_18_U0_l2_adjustments_d1), + .l2_adjustments_q1(48'd0), + .l2_adjustments_we1(tdf7_18_U0_l2_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf7_18_U0_in_data_read), + .out_data_full_n(tdf8_fmaps_i_full_n), + .out_data_write(tdf7_18_U0_out_data_write), + .ap_start(tdf7_18_U0_ap_start), + .ap_done(tdf7_18_U0_ap_done), + .ap_ready(tdf7_18_U0_ap_ready), + .ap_idle(tdf7_18_U0_ap_idle), + .ap_continue(tdf7_18_U0_ap_continue) +); + +td_fused_top_tdf8_17 tdf8_17_U0( + .in_data_address0(tdf8_17_U0_in_data_address0), + .in_data_ce0(tdf8_17_U0_in_data_ce0), + .in_data_d0(tdf8_17_U0_in_data_d0), + .in_data_q0(tdf8_fmaps_t_q0), + .in_data_we0(tdf8_17_U0_in_data_we0), + .in_data_address1(tdf8_17_U0_in_data_address1), + .in_data_ce1(tdf8_17_U0_in_data_ce1), + .in_data_d1(tdf8_17_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf8_17_U0_in_data_we1), + .out_data_address0(tdf8_17_U0_out_data_address0), + .out_data_ce0(tdf8_17_U0_out_data_ce0), + .out_data_d0(tdf8_17_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf8_17_U0_out_data_we0), + .out_data_address1(tdf8_17_U0_out_data_address1), + .out_data_ce1(tdf8_17_U0_out_data_ce1), + .out_data_d1(tdf8_17_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf8_17_U0_out_data_we1), + .filter_data_0_address0(tdf8_17_U0_filter_data_0_address0), + .filter_data_0_ce0(tdf8_17_U0_filter_data_0_ce0), + .filter_data_0_d0(tdf8_17_U0_filter_data_0_d0), + .filter_data_0_q0(tdf8_filters_0_q0), + .filter_data_0_we0(tdf8_17_U0_filter_data_0_we0), + .filter_data_0_address1(tdf8_17_U0_filter_data_0_address1), + .filter_data_0_ce1(tdf8_17_U0_filter_data_0_ce1), + .filter_data_0_d1(tdf8_17_U0_filter_data_0_d1), + .filter_data_0_q1(32'd0), + .filter_data_0_we1(tdf8_17_U0_filter_data_0_we1), + .filter_data_1_address0(tdf8_17_U0_filter_data_1_address0), + .filter_data_1_ce0(tdf8_17_U0_filter_data_1_ce0), + .filter_data_1_d0(tdf8_17_U0_filter_data_1_d0), + .filter_data_1_q0(tdf8_filters_1_q0), + .filter_data_1_we0(tdf8_17_U0_filter_data_1_we0), + .filter_data_1_address1(tdf8_17_U0_filter_data_1_address1), + .filter_data_1_ce1(tdf8_17_U0_filter_data_1_ce1), + .filter_data_1_d1(tdf8_17_U0_filter_data_1_d1), + .filter_data_1_q1(32'd0), + .filter_data_1_we1(tdf8_17_U0_filter_data_1_we1), + .filter_data_2_address0(tdf8_17_U0_filter_data_2_address0), + .filter_data_2_ce0(tdf8_17_U0_filter_data_2_ce0), + .filter_data_2_d0(tdf8_17_U0_filter_data_2_d0), + .filter_data_2_q0(tdf8_filters_2_q0), + .filter_data_2_we0(tdf8_17_U0_filter_data_2_we0), + .filter_data_2_address1(tdf8_17_U0_filter_data_2_address1), + .filter_data_2_ce1(tdf8_17_U0_filter_data_2_ce1), + .filter_data_2_d1(tdf8_17_U0_filter_data_2_d1), + .filter_data_2_q1(32'd0), + .filter_data_2_we1(tdf8_17_U0_filter_data_2_we1), + .filter_data_3_address0(tdf8_17_U0_filter_data_3_address0), + .filter_data_3_ce0(tdf8_17_U0_filter_data_3_ce0), + .filter_data_3_d0(tdf8_17_U0_filter_data_3_d0), + .filter_data_3_q0(tdf8_filters_3_q0), + .filter_data_3_we0(tdf8_17_U0_filter_data_3_we0), + .filter_data_3_address1(tdf8_17_U0_filter_data_3_address1), + .filter_data_3_ce1(tdf8_17_U0_filter_data_3_ce1), + .filter_data_3_d1(tdf8_17_U0_filter_data_3_d1), + .filter_data_3_q1(32'd0), + .filter_data_3_we1(tdf8_17_U0_filter_data_3_we1), + .adjustments_address0(tdf8_17_U0_adjustments_address0), + .adjustments_ce0(tdf8_17_U0_adjustments_ce0), + .adjustments_d0(tdf8_17_U0_adjustments_d0), + .adjustments_q0(tdf8_adjustments_q0), + .adjustments_we0(tdf8_17_U0_adjustments_we0), + .adjustments_address1(tdf8_17_U0_adjustments_address1), + .adjustments_ce1(tdf8_17_U0_adjustments_ce1), + .adjustments_d1(tdf8_17_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf8_17_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf8_17_U0_in_data_read), + .out_data_full_n(tdf9_fmaps_i_full_n), + .out_data_write(tdf8_17_U0_out_data_write), + .ap_start(tdf8_17_U0_ap_start), + .ap_done(tdf8_17_U0_ap_done), + .ap_ready(tdf8_17_U0_ap_ready), + .ap_idle(tdf8_17_U0_ap_idle), + .ap_continue(tdf8_17_U0_ap_continue) +); + +td_fused_top_tdf9_16 tdf9_16_U0( + .in_data_address0(tdf9_16_U0_in_data_address0), + .in_data_ce0(tdf9_16_U0_in_data_ce0), + .in_data_d0(tdf9_16_U0_in_data_d0), + .in_data_q0(tdf9_fmaps_t_q0), + .in_data_we0(tdf9_16_U0_in_data_we0), + .in_data_address1(tdf9_16_U0_in_data_address1), + .in_data_ce1(tdf9_16_U0_in_data_ce1), + .in_data_d1(tdf9_16_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf9_16_U0_in_data_we1), + .out_data_address0(tdf9_16_U0_out_data_address0), + .out_data_ce0(tdf9_16_U0_out_data_ce0), + .out_data_d0(tdf9_16_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf9_16_U0_out_data_we0), + .out_data_address1(tdf9_16_U0_out_data_address1), + .out_data_ce1(tdf9_16_U0_out_data_ce1), + .out_data_d1(tdf9_16_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf9_16_U0_out_data_we1), + .filter_data_address0(tdf9_16_U0_filter_data_address0), + .filter_data_ce0(tdf9_16_U0_filter_data_ce0), + .filter_data_d0(tdf9_16_U0_filter_data_d0), + .filter_data_q0(tdf9_filters_q0), + .filter_data_we0(tdf9_16_U0_filter_data_we0), + .filter_data_address1(tdf9_16_U0_filter_data_address1), + .filter_data_ce1(tdf9_16_U0_filter_data_ce1), + .filter_data_d1(tdf9_16_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(tdf9_16_U0_filter_data_we1), + .adjustments_address0(tdf9_16_U0_adjustments_address0), + .adjustments_ce0(tdf9_16_U0_adjustments_ce0), + .adjustments_d0(tdf9_16_U0_adjustments_d0), + .adjustments_q0(tdf9_adjustments_q0), + .adjustments_we0(tdf9_16_U0_adjustments_we0), + .adjustments_address1(tdf9_16_U0_adjustments_address1), + .adjustments_ce1(tdf9_16_U0_adjustments_ce1), + .adjustments_d1(tdf9_16_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf9_16_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf9_16_U0_in_data_read), + .out_data_full_n(tdf10_fmaps_i_full_n), + .out_data_write(tdf9_16_U0_out_data_write), + .ap_start(tdf9_16_U0_ap_start), + .ap_done(tdf9_16_U0_ap_done), + .ap_ready(tdf9_16_U0_ap_ready), + .ap_idle(tdf9_16_U0_ap_idle), + .ap_continue(tdf9_16_U0_ap_continue) +); + +td_fused_top_tdf10_15 tdf10_15_U0( + .in_data_address0(tdf10_15_U0_in_data_address0), + .in_data_ce0(tdf10_15_U0_in_data_ce0), + .in_data_d0(tdf10_15_U0_in_data_d0), + .in_data_q0(tdf10_fmaps_t_q0), + .in_data_we0(tdf10_15_U0_in_data_we0), + .in_data_address1(tdf10_15_U0_in_data_address1), + .in_data_ce1(tdf10_15_U0_in_data_ce1), + .in_data_d1(tdf10_15_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf10_15_U0_in_data_we1), + .out_data_address0(tdf10_15_U0_out_data_address0), + .out_data_ce0(tdf10_15_U0_out_data_ce0), + .out_data_d0(tdf10_15_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf10_15_U0_out_data_we0), + .out_data_address1(tdf10_15_U0_out_data_address1), + .out_data_ce1(tdf10_15_U0_out_data_ce1), + .out_data_d1(tdf10_15_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf10_15_U0_out_data_we1), + .l1_filter_data_0_address0(tdf10_15_U0_l1_filter_data_0_address0), + .l1_filter_data_0_ce0(tdf10_15_U0_l1_filter_data_0_ce0), + .l1_filter_data_0_d0(tdf10_15_U0_l1_filter_data_0_d0), + .l1_filter_data_0_q0(tdf10_filters_0_q0), + .l1_filter_data_0_we0(tdf10_15_U0_l1_filter_data_0_we0), + .l1_filter_data_0_address1(tdf10_15_U0_l1_filter_data_0_address1), + .l1_filter_data_0_ce1(tdf10_15_U0_l1_filter_data_0_ce1), + .l1_filter_data_0_d1(tdf10_15_U0_l1_filter_data_0_d1), + .l1_filter_data_0_q1(64'd0), + .l1_filter_data_0_we1(tdf10_15_U0_l1_filter_data_0_we1), + .l1_filter_data_1_address0(tdf10_15_U0_l1_filter_data_1_address0), + .l1_filter_data_1_ce0(tdf10_15_U0_l1_filter_data_1_ce0), + .l1_filter_data_1_d0(tdf10_15_U0_l1_filter_data_1_d0), + .l1_filter_data_1_q0(tdf10_filters_1_q0), + .l1_filter_data_1_we0(tdf10_15_U0_l1_filter_data_1_we0), + .l1_filter_data_1_address1(tdf10_15_U0_l1_filter_data_1_address1), + .l1_filter_data_1_ce1(tdf10_15_U0_l1_filter_data_1_ce1), + .l1_filter_data_1_d1(tdf10_15_U0_l1_filter_data_1_d1), + .l1_filter_data_1_q1(64'd0), + .l1_filter_data_1_we1(tdf10_15_U0_l1_filter_data_1_we1), + .l1_filter_data_2_address0(tdf10_15_U0_l1_filter_data_2_address0), + .l1_filter_data_2_ce0(tdf10_15_U0_l1_filter_data_2_ce0), + .l1_filter_data_2_d0(tdf10_15_U0_l1_filter_data_2_d0), + .l1_filter_data_2_q0(tdf10_filters_2_q0), + .l1_filter_data_2_we0(tdf10_15_U0_l1_filter_data_2_we0), + .l1_filter_data_2_address1(tdf10_15_U0_l1_filter_data_2_address1), + .l1_filter_data_2_ce1(tdf10_15_U0_l1_filter_data_2_ce1), + .l1_filter_data_2_d1(tdf10_15_U0_l1_filter_data_2_d1), + .l1_filter_data_2_q1(64'd0), + .l1_filter_data_2_we1(tdf10_15_U0_l1_filter_data_2_we1), + .l1_filter_data_3_address0(tdf10_15_U0_l1_filter_data_3_address0), + .l1_filter_data_3_ce0(tdf10_15_U0_l1_filter_data_3_ce0), + .l1_filter_data_3_d0(tdf10_15_U0_l1_filter_data_3_d0), + .l1_filter_data_3_q0(tdf10_filters_3_q0), + .l1_filter_data_3_we0(tdf10_15_U0_l1_filter_data_3_we0), + .l1_filter_data_3_address1(tdf10_15_U0_l1_filter_data_3_address1), + .l1_filter_data_3_ce1(tdf10_15_U0_l1_filter_data_3_ce1), + .l1_filter_data_3_d1(tdf10_15_U0_l1_filter_data_3_d1), + .l1_filter_data_3_q1(64'd0), + .l1_filter_data_3_we1(tdf10_15_U0_l1_filter_data_3_we1), + .l2_filter_data_0_address0(tdf10_15_U0_l2_filter_data_0_address0), + .l2_filter_data_0_ce0(tdf10_15_U0_l2_filter_data_0_ce0), + .l2_filter_data_0_d0(tdf10_15_U0_l2_filter_data_0_d0), + .l2_filter_data_0_q0(tdf10_l2_filters_0_q0), + .l2_filter_data_0_we0(tdf10_15_U0_l2_filter_data_0_we0), + .l2_filter_data_0_address1(tdf10_15_U0_l2_filter_data_0_address1), + .l2_filter_data_0_ce1(tdf10_15_U0_l2_filter_data_0_ce1), + .l2_filter_data_0_d1(tdf10_15_U0_l2_filter_data_0_d1), + .l2_filter_data_0_q1(tdf10_l2_filters_0_q1), + .l2_filter_data_0_we1(tdf10_15_U0_l2_filter_data_0_we1), + .l2_filter_data_1_address0(tdf10_15_U0_l2_filter_data_1_address0), + .l2_filter_data_1_ce0(tdf10_15_U0_l2_filter_data_1_ce0), + .l2_filter_data_1_d0(tdf10_15_U0_l2_filter_data_1_d0), + .l2_filter_data_1_q0(tdf10_l2_filters_1_q0), + .l2_filter_data_1_we0(tdf10_15_U0_l2_filter_data_1_we0), + .l2_filter_data_1_address1(tdf10_15_U0_l2_filter_data_1_address1), + .l2_filter_data_1_ce1(tdf10_15_U0_l2_filter_data_1_ce1), + .l2_filter_data_1_d1(tdf10_15_U0_l2_filter_data_1_d1), + .l2_filter_data_1_q1(tdf10_l2_filters_1_q1), + .l2_filter_data_1_we1(tdf10_15_U0_l2_filter_data_1_we1), + .l1_adjustments_address0(tdf10_15_U0_l1_adjustments_address0), + .l1_adjustments_ce0(tdf10_15_U0_l1_adjustments_ce0), + .l1_adjustments_d0(tdf10_15_U0_l1_adjustments_d0), + .l1_adjustments_q0(tdf10_adjustments_q0), + .l1_adjustments_we0(tdf10_15_U0_l1_adjustments_we0), + .l1_adjustments_address1(tdf10_15_U0_l1_adjustments_address1), + .l1_adjustments_ce1(tdf10_15_U0_l1_adjustments_ce1), + .l1_adjustments_d1(tdf10_15_U0_l1_adjustments_d1), + .l1_adjustments_q1(48'd0), + .l1_adjustments_we1(tdf10_15_U0_l1_adjustments_we1), + .l2_adjustments_address0(tdf10_15_U0_l2_adjustments_address0), + .l2_adjustments_ce0(tdf10_15_U0_l2_adjustments_ce0), + .l2_adjustments_d0(tdf10_15_U0_l2_adjustments_d0), + .l2_adjustments_q0(tdf10_l2_adjustments_q0), + .l2_adjustments_we0(tdf10_15_U0_l2_adjustments_we0), + .l2_adjustments_address1(tdf10_15_U0_l2_adjustments_address1), + .l2_adjustments_ce1(tdf10_15_U0_l2_adjustments_ce1), + .l2_adjustments_d1(tdf10_15_U0_l2_adjustments_d1), + .l2_adjustments_q1(48'd0), + .l2_adjustments_we1(tdf10_15_U0_l2_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf10_15_U0_in_data_read), + .out_data_full_n(tdf11_fmaps_i_full_n), + .out_data_write(tdf10_15_U0_out_data_write), + .ap_start(tdf10_15_U0_ap_start), + .ap_done(tdf10_15_U0_ap_done), + .ap_ready(tdf10_15_U0_ap_ready), + .ap_idle(tdf10_15_U0_ap_idle), + .ap_continue(tdf10_15_U0_ap_continue) +); + +td_fused_top_tdf11_14 tdf11_14_U0( + .in_data_address0(tdf11_14_U0_in_data_address0), + .in_data_ce0(tdf11_14_U0_in_data_ce0), + .in_data_d0(tdf11_14_U0_in_data_d0), + .in_data_q0(tdf11_fmaps_t_q0), + .in_data_we0(tdf11_14_U0_in_data_we0), + .in_data_address1(tdf11_14_U0_in_data_address1), + .in_data_ce1(tdf11_14_U0_in_data_ce1), + .in_data_d1(tdf11_14_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf11_14_U0_in_data_we1), + .out_data_address0(tdf11_14_U0_out_data_address0), + .out_data_ce0(tdf11_14_U0_out_data_ce0), + .out_data_d0(tdf11_14_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf11_14_U0_out_data_we0), + .out_data_address1(tdf11_14_U0_out_data_address1), + .out_data_ce1(tdf11_14_U0_out_data_ce1), + .out_data_d1(tdf11_14_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf11_14_U0_out_data_we1), + .l1_filter_data_0_address0(tdf11_14_U0_l1_filter_data_0_address0), + .l1_filter_data_0_ce0(tdf11_14_U0_l1_filter_data_0_ce0), + .l1_filter_data_0_d0(tdf11_14_U0_l1_filter_data_0_d0), + .l1_filter_data_0_q0(tdf11_filters_0_q0), + .l1_filter_data_0_we0(tdf11_14_U0_l1_filter_data_0_we0), + .l1_filter_data_0_address1(tdf11_14_U0_l1_filter_data_0_address1), + .l1_filter_data_0_ce1(tdf11_14_U0_l1_filter_data_0_ce1), + .l1_filter_data_0_d1(tdf11_14_U0_l1_filter_data_0_d1), + .l1_filter_data_0_q1(64'd0), + .l1_filter_data_0_we1(tdf11_14_U0_l1_filter_data_0_we1), + .l1_filter_data_1_address0(tdf11_14_U0_l1_filter_data_1_address0), + .l1_filter_data_1_ce0(tdf11_14_U0_l1_filter_data_1_ce0), + .l1_filter_data_1_d0(tdf11_14_U0_l1_filter_data_1_d0), + .l1_filter_data_1_q0(tdf11_filters_1_q0), + .l1_filter_data_1_we0(tdf11_14_U0_l1_filter_data_1_we0), + .l1_filter_data_1_address1(tdf11_14_U0_l1_filter_data_1_address1), + .l1_filter_data_1_ce1(tdf11_14_U0_l1_filter_data_1_ce1), + .l1_filter_data_1_d1(tdf11_14_U0_l1_filter_data_1_d1), + .l1_filter_data_1_q1(64'd0), + .l1_filter_data_1_we1(tdf11_14_U0_l1_filter_data_1_we1), + .l1_filter_data_2_address0(tdf11_14_U0_l1_filter_data_2_address0), + .l1_filter_data_2_ce0(tdf11_14_U0_l1_filter_data_2_ce0), + .l1_filter_data_2_d0(tdf11_14_U0_l1_filter_data_2_d0), + .l1_filter_data_2_q0(tdf11_filters_2_q0), + .l1_filter_data_2_we0(tdf11_14_U0_l1_filter_data_2_we0), + .l1_filter_data_2_address1(tdf11_14_U0_l1_filter_data_2_address1), + .l1_filter_data_2_ce1(tdf11_14_U0_l1_filter_data_2_ce1), + .l1_filter_data_2_d1(tdf11_14_U0_l1_filter_data_2_d1), + .l1_filter_data_2_q1(64'd0), + .l1_filter_data_2_we1(tdf11_14_U0_l1_filter_data_2_we1), + .l1_filter_data_3_address0(tdf11_14_U0_l1_filter_data_3_address0), + .l1_filter_data_3_ce0(tdf11_14_U0_l1_filter_data_3_ce0), + .l1_filter_data_3_d0(tdf11_14_U0_l1_filter_data_3_d0), + .l1_filter_data_3_q0(tdf11_filters_3_q0), + .l1_filter_data_3_we0(tdf11_14_U0_l1_filter_data_3_we0), + .l1_filter_data_3_address1(tdf11_14_U0_l1_filter_data_3_address1), + .l1_filter_data_3_ce1(tdf11_14_U0_l1_filter_data_3_ce1), + .l1_filter_data_3_d1(tdf11_14_U0_l1_filter_data_3_d1), + .l1_filter_data_3_q1(64'd0), + .l1_filter_data_3_we1(tdf11_14_U0_l1_filter_data_3_we1), + .l2_filter_data_0_address0(tdf11_14_U0_l2_filter_data_0_address0), + .l2_filter_data_0_ce0(tdf11_14_U0_l2_filter_data_0_ce0), + .l2_filter_data_0_d0(tdf11_14_U0_l2_filter_data_0_d0), + .l2_filter_data_0_q0(tdf11_l2_filters_0_q0), + .l2_filter_data_0_we0(tdf11_14_U0_l2_filter_data_0_we0), + .l2_filter_data_0_address1(tdf11_14_U0_l2_filter_data_0_address1), + .l2_filter_data_0_ce1(tdf11_14_U0_l2_filter_data_0_ce1), + .l2_filter_data_0_d1(tdf11_14_U0_l2_filter_data_0_d1), + .l2_filter_data_0_q1(tdf11_l2_filters_0_q1), + .l2_filter_data_0_we1(tdf11_14_U0_l2_filter_data_0_we1), + .l2_filter_data_1_address0(tdf11_14_U0_l2_filter_data_1_address0), + .l2_filter_data_1_ce0(tdf11_14_U0_l2_filter_data_1_ce0), + .l2_filter_data_1_d0(tdf11_14_U0_l2_filter_data_1_d0), + .l2_filter_data_1_q0(tdf11_l2_filters_1_q0), + .l2_filter_data_1_we0(tdf11_14_U0_l2_filter_data_1_we0), + .l2_filter_data_1_address1(tdf11_14_U0_l2_filter_data_1_address1), + .l2_filter_data_1_ce1(tdf11_14_U0_l2_filter_data_1_ce1), + .l2_filter_data_1_d1(tdf11_14_U0_l2_filter_data_1_d1), + .l2_filter_data_1_q1(tdf11_l2_filters_1_q1), + .l2_filter_data_1_we1(tdf11_14_U0_l2_filter_data_1_we1), + .l2_filter_data_2_address0(tdf11_14_U0_l2_filter_data_2_address0), + .l2_filter_data_2_ce0(tdf11_14_U0_l2_filter_data_2_ce0), + .l2_filter_data_2_d0(tdf11_14_U0_l2_filter_data_2_d0), + .l2_filter_data_2_q0(tdf11_l2_filters_2_q0), + .l2_filter_data_2_we0(tdf11_14_U0_l2_filter_data_2_we0), + .l2_filter_data_2_address1(tdf11_14_U0_l2_filter_data_2_address1), + .l2_filter_data_2_ce1(tdf11_14_U0_l2_filter_data_2_ce1), + .l2_filter_data_2_d1(tdf11_14_U0_l2_filter_data_2_d1), + .l2_filter_data_2_q1(tdf11_l2_filters_2_q1), + .l2_filter_data_2_we1(tdf11_14_U0_l2_filter_data_2_we1), + .l2_filter_data_3_address0(tdf11_14_U0_l2_filter_data_3_address0), + .l2_filter_data_3_ce0(tdf11_14_U0_l2_filter_data_3_ce0), + .l2_filter_data_3_d0(tdf11_14_U0_l2_filter_data_3_d0), + .l2_filter_data_3_q0(tdf11_l2_filters_3_q0), + .l2_filter_data_3_we0(tdf11_14_U0_l2_filter_data_3_we0), + .l2_filter_data_3_address1(tdf11_14_U0_l2_filter_data_3_address1), + .l2_filter_data_3_ce1(tdf11_14_U0_l2_filter_data_3_ce1), + .l2_filter_data_3_d1(tdf11_14_U0_l2_filter_data_3_d1), + .l2_filter_data_3_q1(tdf11_l2_filters_3_q1), + .l2_filter_data_3_we1(tdf11_14_U0_l2_filter_data_3_we1), + .l1_adjustments_address0(tdf11_14_U0_l1_adjustments_address0), + .l1_adjustments_ce0(tdf11_14_U0_l1_adjustments_ce0), + .l1_adjustments_d0(tdf11_14_U0_l1_adjustments_d0), + .l1_adjustments_q0(tdf11_adjustments_q0), + .l1_adjustments_we0(tdf11_14_U0_l1_adjustments_we0), + .l1_adjustments_address1(tdf11_14_U0_l1_adjustments_address1), + .l1_adjustments_ce1(tdf11_14_U0_l1_adjustments_ce1), + .l1_adjustments_d1(tdf11_14_U0_l1_adjustments_d1), + .l1_adjustments_q1(48'd0), + .l1_adjustments_we1(tdf11_14_U0_l1_adjustments_we1), + .l2_adjustments_address0(tdf11_14_U0_l2_adjustments_address0), + .l2_adjustments_ce0(tdf11_14_U0_l2_adjustments_ce0), + .l2_adjustments_d0(tdf11_14_U0_l2_adjustments_d0), + .l2_adjustments_q0(tdf11_l2_adjustments_q0), + .l2_adjustments_we0(tdf11_14_U0_l2_adjustments_we0), + .l2_adjustments_address1(tdf11_14_U0_l2_adjustments_address1), + .l2_adjustments_ce1(tdf11_14_U0_l2_adjustments_ce1), + .l2_adjustments_d1(tdf11_14_U0_l2_adjustments_d1), + .l2_adjustments_q1(48'd0), + .l2_adjustments_we1(tdf11_14_U0_l2_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf11_14_U0_in_data_read), + .out_data_full_n(tdf12_fmaps_i_full_n), + .out_data_write(tdf11_14_U0_out_data_write), + .ap_start(tdf11_14_U0_ap_start), + .ap_done(tdf11_14_U0_ap_done), + .ap_ready(tdf11_14_U0_ap_ready), + .ap_idle(tdf11_14_U0_ap_idle), + .ap_continue(tdf11_14_U0_ap_continue) +); + +td_fused_top_tdf12_13 tdf12_13_U0( + .in_data_address0(tdf12_13_U0_in_data_address0), + .in_data_ce0(tdf12_13_U0_in_data_ce0), + .in_data_d0(tdf12_13_U0_in_data_d0), + .in_data_q0(tdf12_fmaps_t_q0), + .in_data_we0(tdf12_13_U0_in_data_we0), + .in_data_address1(tdf12_13_U0_in_data_address1), + .in_data_ce1(tdf12_13_U0_in_data_ce1), + .in_data_d1(tdf12_13_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf12_13_U0_in_data_we1), + .out_data_address0(tdf12_13_U0_out_data_address0), + .out_data_ce0(tdf12_13_U0_out_data_ce0), + .out_data_d0(tdf12_13_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf12_13_U0_out_data_we0), + .out_data_address1(tdf12_13_U0_out_data_address1), + .out_data_ce1(tdf12_13_U0_out_data_ce1), + .out_data_d1(tdf12_13_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf12_13_U0_out_data_we1), + .filter_data_0_address0(tdf12_13_U0_filter_data_0_address0), + .filter_data_0_ce0(tdf12_13_U0_filter_data_0_ce0), + .filter_data_0_d0(tdf12_13_U0_filter_data_0_d0), + .filter_data_0_q0(tdf12_filters_0_q0), + .filter_data_0_we0(tdf12_13_U0_filter_data_0_we0), + .filter_data_0_address1(tdf12_13_U0_filter_data_0_address1), + .filter_data_0_ce1(tdf12_13_U0_filter_data_0_ce1), + .filter_data_0_d1(tdf12_13_U0_filter_data_0_d1), + .filter_data_0_q1(32'd0), + .filter_data_0_we1(tdf12_13_U0_filter_data_0_we1), + .filter_data_1_address0(tdf12_13_U0_filter_data_1_address0), + .filter_data_1_ce0(tdf12_13_U0_filter_data_1_ce0), + .filter_data_1_d0(tdf12_13_U0_filter_data_1_d0), + .filter_data_1_q0(tdf12_filters_1_q0), + .filter_data_1_we0(tdf12_13_U0_filter_data_1_we0), + .filter_data_1_address1(tdf12_13_U0_filter_data_1_address1), + .filter_data_1_ce1(tdf12_13_U0_filter_data_1_ce1), + .filter_data_1_d1(tdf12_13_U0_filter_data_1_d1), + .filter_data_1_q1(32'd0), + .filter_data_1_we1(tdf12_13_U0_filter_data_1_we1), + .adjustments_address0(tdf12_13_U0_adjustments_address0), + .adjustments_ce0(tdf12_13_U0_adjustments_ce0), + .adjustments_d0(tdf12_13_U0_adjustments_d0), + .adjustments_q0(tdf12_adjustments_q0), + .adjustments_we0(tdf12_13_U0_adjustments_we0), + .adjustments_address1(tdf12_13_U0_adjustments_address1), + .adjustments_ce1(tdf12_13_U0_adjustments_ce1), + .adjustments_d1(tdf12_13_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf12_13_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf12_13_U0_in_data_read), + .out_data_full_n(final_fmaps_i_full_n), + .out_data_write(tdf12_13_U0_out_data_write), + .ap_start(tdf12_13_U0_ap_start), + .ap_done(tdf12_13_U0_ap_done), + .ap_ready(tdf12_13_U0_ap_ready), + .ap_idle(tdf12_13_U0_ap_idle), + .ap_continue(tdf12_13_U0_ap_continue) +); + +td_fused_top_td_fused_axi_out td_fused_axi_out_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(td_fused_axi_out_U0_ap_start), + .ap_done(td_fused_axi_out_U0_ap_done), + .ap_continue(td_fused_axi_out_U0_ap_continue), + .ap_idle(td_fused_axi_out_U0_ap_idle), + .ap_ready(td_fused_axi_out_U0_ap_ready), + .fmaps_address0(td_fused_axi_out_U0_fmaps_address0), + .fmaps_ce0(td_fused_axi_out_U0_fmaps_ce0), + .fmaps_q0(final_fmaps_t_q0), + .stream_out_TDATA(td_fused_axi_out_U0_stream_out_TDATA), + .stream_out_TVALID(td_fused_axi_out_U0_stream_out_TVALID), + .stream_out_TREADY(stream_out_TREADY), + .stream_out_TKEEP(td_fused_axi_out_U0_stream_out_TKEEP), + .stream_out_TSTRB(td_fused_axi_out_U0_stream_out_TSTRB), + .stream_out_TLAST(td_fused_axi_out_U0_stream_out_TLAST) +); + +assign ap_channel_done_final_fmaps = tdf12_13_U0_ap_done; + +assign ap_channel_done_tdf10_fmaps = tdf9_16_U0_ap_done; + +assign ap_channel_done_tdf11_fmaps = tdf10_15_U0_ap_done; + +assign ap_channel_done_tdf12_fmaps = tdf11_14_U0_ap_done; + +assign ap_channel_done_tdf1_fmaps = td_fused_axi_in_U0_ap_done; + +assign ap_channel_done_tdf2_fmaps = tdf1_114_U0_ap_done; + +assign ap_channel_done_tdf3_fmaps = tdf2_113_U0_ap_done; + +assign ap_channel_done_tdf4_fmaps = tdf3_112_U0_ap_done; + +assign ap_channel_done_tdf5_fmaps = tdf4_111_U0_ap_done; + +assign ap_channel_done_tdf6_fmaps = tdf5_110_U0_ap_done; + +assign ap_channel_done_tdf7_fmaps = tdf6_19_U0_ap_done; + +assign ap_channel_done_tdf8_fmaps = tdf7_18_U0_ap_done; + +assign ap_channel_done_tdf9_fmaps = tdf8_17_U0_ap_done; + +assign ap_done = td_fused_axi_out_U0_ap_done; + +assign ap_idle = (tdf9_16_U0_ap_idle & tdf8_17_U0_ap_idle & tdf7_18_U0_ap_idle & tdf6_19_U0_ap_idle & tdf5_110_U0_ap_idle & tdf4_111_U0_ap_idle & tdf3_112_U0_ap_idle & tdf2_113_U0_ap_idle & tdf1_114_U0_ap_idle & tdf12_13_U0_ap_idle & tdf11_14_U0_ap_idle & tdf10_15_U0_ap_idle & td_fused_axi_out_U0_ap_idle & td_fused_axi_in_U0_ap_idle & (final_fmaps_t_empty_n ^ 1'b1) & (tdf12_fmaps_t_empty_n ^ 1'b1) & (tdf11_fmaps_t_empty_n ^ 1'b1) & (tdf10_fmaps_t_empty_n ^ 1'b1) & (tdf9_fmaps_t_empty_n ^ 1'b1) & (tdf8_fmaps_t_empty_n ^ 1'b1) & (tdf7_fmaps_t_empty_n ^ 1'b1) & (tdf6_fmaps_t_empty_n ^ 1'b1) & (tdf5_fmaps_t_empty_n ^ 1'b1) & (tdf4_fmaps_t_empty_n ^ 1'b1) & (tdf3_fmaps_t_empty_n ^ 1'b1) & (tdf2_fmaps_t_empty_n ^ 1'b1) & (tdf1_fmaps_t_empty_n ^ 1'b1)); + +assign ap_ready = td_fused_axi_in_U0_ap_ready; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = td_fused_axi_out_U0_ap_done; + +assign ap_sync_ready = td_fused_axi_in_U0_ap_ready; + +assign final_fmaps_t_d0 = 64'd0; + +assign final_fmaps_t_we0 = 1'b0; + +assign stream_in_TREADY = td_fused_axi_in_U0_stream_in_TREADY; + +assign stream_out_TDATA = td_fused_axi_out_U0_stream_out_TDATA; + +assign stream_out_TKEEP = td_fused_axi_out_U0_stream_out_TKEEP; + +assign stream_out_TLAST = td_fused_axi_out_U0_stream_out_TLAST; + +assign stream_out_TSTRB = td_fused_axi_out_U0_stream_out_TSTRB; + +assign stream_out_TVALID = td_fused_axi_out_U0_stream_out_TVALID; + +assign td_fused_axi_in_U0_ap_continue = tdf1_fmaps_i_full_n; + +assign td_fused_axi_in_U0_ap_start = ap_start; + +assign td_fused_axi_in_U0_fmaps_full_n = tdf1_fmaps_i_full_n; + +assign td_fused_axi_in_U0_start_full_n = 1'b1; + +assign td_fused_axi_in_U0_start_write = 1'b0; + +assign td_fused_axi_out_U0_ap_continue = ap_continue; + +assign td_fused_axi_out_U0_ap_start = final_fmaps_t_empty_n; + +assign td_fused_axi_out_U0_start_full_n = 1'b1; + +assign td_fused_axi_out_U0_start_write = 1'b0; + +assign tdf10_15_U0_ap_continue = tdf10_15_U0_out_data_full_n; + +assign tdf10_15_U0_ap_start = tdf10_fmaps_t_empty_n; + +assign tdf10_15_U0_out_data_full_n = tdf11_fmaps_i_full_n; + +assign tdf10_15_U0_start_full_n = 1'b1; + +assign tdf10_15_U0_start_write = 1'b0; + +assign tdf10_adjustments_address0 = tdf10_15_U0_l1_adjustments_address0; + +assign tdf10_adjustments_address1 = 9'd0; + +assign tdf10_adjustments_ce0 = tdf10_15_U0_l1_adjustments_ce0; + +assign tdf10_adjustments_ce1 = 1'b0; + +assign tdf10_adjustments_d0 = 48'd0; + +assign tdf10_adjustments_d1 = 48'd0; + +assign tdf10_adjustments_we0 = 1'b0; + +assign tdf10_adjustments_we1 = 1'b0; + +assign tdf10_filters_0_address0 = tdf10_15_U0_l1_filter_data_0_address0; + +assign tdf10_filters_0_address1 = 15'd0; + +assign tdf10_filters_0_ce0 = tdf10_15_U0_l1_filter_data_0_ce0; + +assign tdf10_filters_0_ce1 = 1'b0; + +assign tdf10_filters_0_d0 = 64'd0; + +assign tdf10_filters_0_d1 = 64'd0; + +assign tdf10_filters_0_we0 = 1'b0; + +assign tdf10_filters_0_we1 = 1'b0; + +assign tdf10_filters_1_address0 = tdf10_15_U0_l1_filter_data_1_address0; + +assign tdf10_filters_1_address1 = 15'd0; + +assign tdf10_filters_1_ce0 = tdf10_15_U0_l1_filter_data_1_ce0; + +assign tdf10_filters_1_ce1 = 1'b0; + +assign tdf10_filters_1_d0 = 64'd0; + +assign tdf10_filters_1_d1 = 64'd0; + +assign tdf10_filters_1_we0 = 1'b0; + +assign tdf10_filters_1_we1 = 1'b0; + +assign tdf10_filters_2_address0 = tdf10_15_U0_l1_filter_data_2_address0; + +assign tdf10_filters_2_address1 = 15'd0; + +assign tdf10_filters_2_ce0 = tdf10_15_U0_l1_filter_data_2_ce0; + +assign tdf10_filters_2_ce1 = 1'b0; + +assign tdf10_filters_2_d0 = 64'd0; + +assign tdf10_filters_2_d1 = 64'd0; + +assign tdf10_filters_2_we0 = 1'b0; + +assign tdf10_filters_2_we1 = 1'b0; + +assign tdf10_filters_3_address0 = tdf10_15_U0_l1_filter_data_3_address0; + +assign tdf10_filters_3_address1 = 15'd0; + +assign tdf10_filters_3_ce0 = tdf10_15_U0_l1_filter_data_3_ce0; + +assign tdf10_filters_3_ce1 = 1'b0; + +assign tdf10_filters_3_d0 = 64'd0; + +assign tdf10_filters_3_d1 = 64'd0; + +assign tdf10_filters_3_we0 = 1'b0; + +assign tdf10_filters_3_we1 = 1'b0; + +assign tdf10_fmaps_t_d0 = 64'd0; + +assign tdf10_fmaps_t_we0 = 1'b0; + +assign tdf10_l2_adjustments_address0 = tdf10_15_U0_l2_adjustments_address0; + +assign tdf10_l2_adjustments_address1 = 6'd0; + +assign tdf10_l2_adjustments_ce0 = tdf10_15_U0_l2_adjustments_ce0; + +assign tdf10_l2_adjustments_ce1 = 1'b0; + +assign tdf10_l2_adjustments_d0 = 48'd0; + +assign tdf10_l2_adjustments_d1 = 48'd0; + +assign tdf10_l2_adjustments_we0 = 1'b0; + +assign tdf10_l2_adjustments_we1 = 1'b0; + +assign tdf10_l2_filters_0_address0 = tdf10_15_U0_l2_filter_data_0_address0; + +assign tdf10_l2_filters_0_address1 = tdf10_15_U0_l2_filter_data_0_address1; + +assign tdf10_l2_filters_0_ce0 = tdf10_15_U0_l2_filter_data_0_ce0; + +assign tdf10_l2_filters_0_ce1 = tdf10_15_U0_l2_filter_data_0_ce1; + +assign tdf10_l2_filters_0_d0 = 16'd0; + +assign tdf10_l2_filters_0_d1 = 16'd0; + +assign tdf10_l2_filters_0_we0 = 1'b0; + +assign tdf10_l2_filters_0_we1 = 1'b0; + +assign tdf10_l2_filters_1_address0 = tdf10_15_U0_l2_filter_data_1_address0; + +assign tdf10_l2_filters_1_address1 = tdf10_15_U0_l2_filter_data_1_address1; + +assign tdf10_l2_filters_1_ce0 = tdf10_15_U0_l2_filter_data_1_ce0; + +assign tdf10_l2_filters_1_ce1 = tdf10_15_U0_l2_filter_data_1_ce1; + +assign tdf10_l2_filters_1_d0 = 16'd0; + +assign tdf10_l2_filters_1_d1 = 16'd0; + +assign tdf10_l2_filters_1_we0 = 1'b0; + +assign tdf10_l2_filters_1_we1 = 1'b0; + +assign tdf11_14_U0_ap_continue = tdf11_14_U0_out_data_full_n; + +assign tdf11_14_U0_ap_start = tdf11_fmaps_t_empty_n; + +assign tdf11_14_U0_out_data_full_n = tdf12_fmaps_i_full_n; + +assign tdf11_14_U0_start_full_n = 1'b1; + +assign tdf11_14_U0_start_write = 1'b0; + +assign tdf11_adjustments_address0 = tdf11_14_U0_l1_adjustments_address0; + +assign tdf11_adjustments_address1 = 9'd0; + +assign tdf11_adjustments_ce0 = tdf11_14_U0_l1_adjustments_ce0; + +assign tdf11_adjustments_ce1 = 1'b0; + +assign tdf11_adjustments_d0 = 48'd0; + +assign tdf11_adjustments_d1 = 48'd0; + +assign tdf11_adjustments_we0 = 1'b0; + +assign tdf11_adjustments_we1 = 1'b0; + +assign tdf11_filters_0_address0 = tdf11_14_U0_l1_filter_data_0_address0; + +assign tdf11_filters_0_address1 = 15'd0; + +assign tdf11_filters_0_ce0 = tdf11_14_U0_l1_filter_data_0_ce0; + +assign tdf11_filters_0_ce1 = 1'b0; + +assign tdf11_filters_0_d0 = 64'd0; + +assign tdf11_filters_0_d1 = 64'd0; + +assign tdf11_filters_0_we0 = 1'b0; + +assign tdf11_filters_0_we1 = 1'b0; + +assign tdf11_filters_1_address0 = tdf11_14_U0_l1_filter_data_1_address0; + +assign tdf11_filters_1_address1 = 15'd0; + +assign tdf11_filters_1_ce0 = tdf11_14_U0_l1_filter_data_1_ce0; + +assign tdf11_filters_1_ce1 = 1'b0; + +assign tdf11_filters_1_d0 = 64'd0; + +assign tdf11_filters_1_d1 = 64'd0; + +assign tdf11_filters_1_we0 = 1'b0; + +assign tdf11_filters_1_we1 = 1'b0; + +assign tdf11_filters_2_address0 = tdf11_14_U0_l1_filter_data_2_address0; + +assign tdf11_filters_2_address1 = 15'd0; + +assign tdf11_filters_2_ce0 = tdf11_14_U0_l1_filter_data_2_ce0; + +assign tdf11_filters_2_ce1 = 1'b0; + +assign tdf11_filters_2_d0 = 64'd0; + +assign tdf11_filters_2_d1 = 64'd0; + +assign tdf11_filters_2_we0 = 1'b0; + +assign tdf11_filters_2_we1 = 1'b0; + +assign tdf11_filters_3_address0 = tdf11_14_U0_l1_filter_data_3_address0; + +assign tdf11_filters_3_address1 = 15'd0; + +assign tdf11_filters_3_ce0 = tdf11_14_U0_l1_filter_data_3_ce0; + +assign tdf11_filters_3_ce1 = 1'b0; + +assign tdf11_filters_3_d0 = 64'd0; + +assign tdf11_filters_3_d1 = 64'd0; + +assign tdf11_filters_3_we0 = 1'b0; + +assign tdf11_filters_3_we1 = 1'b0; + +assign tdf11_fmaps_t_d0 = 64'd0; + +assign tdf11_fmaps_t_we0 = 1'b0; + +assign tdf11_l2_adjustments_address0 = tdf11_14_U0_l2_adjustments_address0; + +assign tdf11_l2_adjustments_address1 = 7'd0; + +assign tdf11_l2_adjustments_ce0 = tdf11_14_U0_l2_adjustments_ce0; + +assign tdf11_l2_adjustments_ce1 = 1'b0; + +assign tdf11_l2_adjustments_d0 = 48'd0; + +assign tdf11_l2_adjustments_d1 = 48'd0; + +assign tdf11_l2_adjustments_we0 = 1'b0; + +assign tdf11_l2_adjustments_we1 = 1'b0; + +assign tdf11_l2_filters_0_address0 = tdf11_14_U0_l2_filter_data_0_address0; + +assign tdf11_l2_filters_0_address1 = tdf11_14_U0_l2_filter_data_0_address1; + +assign tdf11_l2_filters_0_ce0 = tdf11_14_U0_l2_filter_data_0_ce0; + +assign tdf11_l2_filters_0_ce1 = tdf11_14_U0_l2_filter_data_0_ce1; + +assign tdf11_l2_filters_0_d0 = 16'd0; + +assign tdf11_l2_filters_0_d1 = 16'd0; + +assign tdf11_l2_filters_0_we0 = 1'b0; + +assign tdf11_l2_filters_0_we1 = 1'b0; + +assign tdf11_l2_filters_1_address0 = tdf11_14_U0_l2_filter_data_1_address0; + +assign tdf11_l2_filters_1_address1 = tdf11_14_U0_l2_filter_data_1_address1; + +assign tdf11_l2_filters_1_ce0 = tdf11_14_U0_l2_filter_data_1_ce0; + +assign tdf11_l2_filters_1_ce1 = tdf11_14_U0_l2_filter_data_1_ce1; + +assign tdf11_l2_filters_1_d0 = 16'd0; + +assign tdf11_l2_filters_1_d1 = 16'd0; + +assign tdf11_l2_filters_1_we0 = 1'b0; + +assign tdf11_l2_filters_1_we1 = 1'b0; + +assign tdf11_l2_filters_2_address0 = tdf11_14_U0_l2_filter_data_2_address0; + +assign tdf11_l2_filters_2_address1 = tdf11_14_U0_l2_filter_data_2_address1; + +assign tdf11_l2_filters_2_ce0 = tdf11_14_U0_l2_filter_data_2_ce0; + +assign tdf11_l2_filters_2_ce1 = tdf11_14_U0_l2_filter_data_2_ce1; + +assign tdf11_l2_filters_2_d0 = 16'd0; + +assign tdf11_l2_filters_2_d1 = 16'd0; + +assign tdf11_l2_filters_2_we0 = 1'b0; + +assign tdf11_l2_filters_2_we1 = 1'b0; + +assign tdf11_l2_filters_3_address0 = tdf11_14_U0_l2_filter_data_3_address0; + +assign tdf11_l2_filters_3_address1 = tdf11_14_U0_l2_filter_data_3_address1; + +assign tdf11_l2_filters_3_ce0 = tdf11_14_U0_l2_filter_data_3_ce0; + +assign tdf11_l2_filters_3_ce1 = tdf11_14_U0_l2_filter_data_3_ce1; + +assign tdf11_l2_filters_3_d0 = 16'd0; + +assign tdf11_l2_filters_3_d1 = 16'd0; + +assign tdf11_l2_filters_3_we0 = 1'b0; + +assign tdf11_l2_filters_3_we1 = 1'b0; + +assign tdf12_13_U0_ap_continue = tdf12_13_U0_out_data_full_n; + +assign tdf12_13_U0_ap_start = tdf12_fmaps_t_empty_n; + +assign tdf12_13_U0_out_data_full_n = final_fmaps_i_full_n; + +assign tdf12_13_U0_start_full_n = 1'b1; + +assign tdf12_13_U0_start_write = 1'b0; + +assign tdf12_adjustments_address0 = tdf12_13_U0_adjustments_address0; + +assign tdf12_adjustments_address1 = 10'd0; + +assign tdf12_adjustments_ce0 = tdf12_13_U0_adjustments_ce0; + +assign tdf12_adjustments_ce1 = 1'b0; + +assign tdf12_adjustments_d0 = 48'd0; + +assign tdf12_adjustments_d1 = 48'd0; + +assign tdf12_adjustments_we0 = 1'b0; + +assign tdf12_adjustments_we1 = 1'b0; + +assign tdf12_filters_0_address0 = tdf12_13_U0_filter_data_0_address0; + +assign tdf12_filters_0_address1 = 15'd0; + +assign tdf12_filters_0_ce0 = tdf12_13_U0_filter_data_0_ce0; + +assign tdf12_filters_0_ce1 = 1'b0; + +assign tdf12_filters_0_d0 = 32'd0; + +assign tdf12_filters_0_d1 = 32'd0; + +assign tdf12_filters_0_we0 = 1'b0; + +assign tdf12_filters_0_we1 = 1'b0; + +assign tdf12_filters_1_address0 = tdf12_13_U0_filter_data_1_address0; + +assign tdf12_filters_1_address1 = 15'd0; + +assign tdf12_filters_1_ce0 = tdf12_13_U0_filter_data_1_ce0; + +assign tdf12_filters_1_ce1 = 1'b0; + +assign tdf12_filters_1_d0 = 32'd0; + +assign tdf12_filters_1_d1 = 32'd0; + +assign tdf12_filters_1_we0 = 1'b0; + +assign tdf12_filters_1_we1 = 1'b0; + +assign tdf12_fmaps_t_d0 = 64'd0; + +assign tdf12_fmaps_t_we0 = 1'b0; + +assign tdf1_114_U0_ap_continue = tdf1_114_U0_out_data_full_n; + +assign tdf1_114_U0_ap_start = tdf1_fmaps_t_empty_n; + +assign tdf1_114_U0_out_data_full_n = tdf2_fmaps_i_full_n; + +assign tdf1_114_U0_start_full_n = 1'b1; + +assign tdf1_114_U0_start_write = 1'b0; + +assign tdf1_adjustments_address0 = tdf1_114_U0_adjustments_address0; + +assign tdf1_adjustments_address1 = 4'd0; + +assign tdf1_adjustments_ce0 = tdf1_114_U0_adjustments_ce0; + +assign tdf1_adjustments_ce1 = 1'b0; + +assign tdf1_adjustments_d0 = 48'd0; + +assign tdf1_adjustments_d1 = 48'd0; + +assign tdf1_adjustments_we0 = 1'b0; + +assign tdf1_adjustments_we1 = 1'b0; + +assign tdf1_filters_0_address0 = tdf1_114_U0_filter_data_0_address0; + +assign tdf1_filters_0_address1 = 7'd0; + +assign tdf1_filters_0_ce0 = tdf1_114_U0_filter_data_0_ce0; + +assign tdf1_filters_0_ce1 = 1'b0; + +assign tdf1_filters_0_d0 = 16'd0; + +assign tdf1_filters_0_d1 = 16'd0; + +assign tdf1_filters_0_we0 = 1'b0; + +assign tdf1_filters_0_we1 = 1'b0; + +assign tdf1_filters_1_address0 = tdf1_114_U0_filter_data_1_address0; + +assign tdf1_filters_1_address1 = 7'd0; + +assign tdf1_filters_1_ce0 = tdf1_114_U0_filter_data_1_ce0; + +assign tdf1_filters_1_ce1 = 1'b0; + +assign tdf1_filters_1_d0 = 16'd0; + +assign tdf1_filters_1_d1 = 16'd0; + +assign tdf1_filters_1_we0 = 1'b0; + +assign tdf1_filters_1_we1 = 1'b0; + +assign tdf1_filters_2_address0 = tdf1_114_U0_filter_data_2_address0; + +assign tdf1_filters_2_address1 = 7'd0; + +assign tdf1_filters_2_ce0 = tdf1_114_U0_filter_data_2_ce0; + +assign tdf1_filters_2_ce1 = 1'b0; + +assign tdf1_filters_2_d0 = 16'd0; + +assign tdf1_filters_2_d1 = 16'd0; + +assign tdf1_filters_2_we0 = 1'b0; + +assign tdf1_filters_2_we1 = 1'b0; + +assign tdf1_filters_3_address0 = tdf1_114_U0_filter_data_3_address0; + +assign tdf1_filters_3_address1 = 7'd0; + +assign tdf1_filters_3_ce0 = tdf1_114_U0_filter_data_3_ce0; + +assign tdf1_filters_3_ce1 = 1'b0; + +assign tdf1_filters_3_d0 = 16'd0; + +assign tdf1_filters_3_d1 = 16'd0; + +assign tdf1_filters_3_we0 = 1'b0; + +assign tdf1_filters_3_we1 = 1'b0; + +assign tdf1_fmaps_t_d0 = 64'd0; + +assign tdf1_fmaps_t_we0 = 1'b0; + +assign tdf2_113_U0_ap_continue = tdf2_113_U0_out_data_full_n; + +assign tdf2_113_U0_ap_start = tdf2_fmaps_t_empty_n; + +assign tdf2_113_U0_out_data_full_n = tdf3_fmaps_i_full_n; + +assign tdf2_113_U0_start_full_n = 1'b1; + +assign tdf2_113_U0_start_write = 1'b0; + +assign tdf2_adjustments_address0 = tdf2_113_U0_adjustments_address0; + +assign tdf2_adjustments_address1 = 5'd0; + +assign tdf2_adjustments_ce0 = tdf2_113_U0_adjustments_ce0; + +assign tdf2_adjustments_ce1 = 1'b0; + +assign tdf2_adjustments_d0 = 48'd0; + +assign tdf2_adjustments_d1 = 48'd0; + +assign tdf2_adjustments_we0 = 1'b0; + +assign tdf2_adjustments_we1 = 1'b0; + +assign tdf2_filters_0_address0 = tdf2_113_U0_filter_data_0_address0; + +assign tdf2_filters_0_address1 = 10'd0; + +assign tdf2_filters_0_ce0 = tdf2_113_U0_filter_data_0_ce0; + +assign tdf2_filters_0_ce1 = 1'b0; + +assign tdf2_filters_0_d0 = 32'd0; + +assign tdf2_filters_0_d1 = 32'd0; + +assign tdf2_filters_0_we0 = 1'b0; + +assign tdf2_filters_0_we1 = 1'b0; + +assign tdf2_filters_1_address0 = tdf2_113_U0_filter_data_1_address0; + +assign tdf2_filters_1_address1 = 10'd0; + +assign tdf2_filters_1_ce0 = tdf2_113_U0_filter_data_1_ce0; + +assign tdf2_filters_1_ce1 = 1'b0; + +assign tdf2_filters_1_d0 = 32'd0; + +assign tdf2_filters_1_d1 = 32'd0; + +assign tdf2_filters_1_we0 = 1'b0; + +assign tdf2_filters_1_we1 = 1'b0; + +assign tdf2_filters_2_address0 = tdf2_113_U0_filter_data_2_address0; + +assign tdf2_filters_2_address1 = 10'd0; + +assign tdf2_filters_2_ce0 = tdf2_113_U0_filter_data_2_ce0; + +assign tdf2_filters_2_ce1 = 1'b0; + +assign tdf2_filters_2_d0 = 32'd0; + +assign tdf2_filters_2_d1 = 32'd0; + +assign tdf2_filters_2_we0 = 1'b0; + +assign tdf2_filters_2_we1 = 1'b0; + +assign tdf2_filters_3_address0 = tdf2_113_U0_filter_data_3_address0; + +assign tdf2_filters_3_address1 = 10'd0; + +assign tdf2_filters_3_ce0 = tdf2_113_U0_filter_data_3_ce0; + +assign tdf2_filters_3_ce1 = 1'b0; + +assign tdf2_filters_3_d0 = 32'd0; + +assign tdf2_filters_3_d1 = 32'd0; + +assign tdf2_filters_3_we0 = 1'b0; + +assign tdf2_filters_3_we1 = 1'b0; + +assign tdf2_fmaps_t_d0 = 64'd0; + +assign tdf2_fmaps_t_we0 = 1'b0; + +assign tdf3_112_U0_ap_continue = tdf3_112_U0_out_data_full_n; + +assign tdf3_112_U0_ap_start = tdf3_fmaps_t_empty_n; + +assign tdf3_112_U0_out_data_full_n = tdf4_fmaps_i_full_n; + +assign tdf3_112_U0_start_full_n = 1'b1; + +assign tdf3_112_U0_start_write = 1'b0; + +assign tdf3_adjustments_address0 = tdf3_112_U0_adjustments_address0; + +assign tdf3_adjustments_address1 = 4'd0; + +assign tdf3_adjustments_ce0 = tdf3_112_U0_adjustments_ce0; + +assign tdf3_adjustments_ce1 = 1'b0; + +assign tdf3_adjustments_d0 = 48'd0; + +assign tdf3_adjustments_d1 = 48'd0; + +assign tdf3_adjustments_we0 = 1'b0; + +assign tdf3_adjustments_we1 = 1'b0; + +assign tdf3_filters_address0 = tdf3_112_U0_filter_data_address0; + +assign tdf3_filters_address1 = 9'd0; + +assign tdf3_filters_ce0 = tdf3_112_U0_filter_data_ce0; + +assign tdf3_filters_ce1 = 1'b0; + +assign tdf3_filters_d0 = 16'd0; + +assign tdf3_filters_d1 = 16'd0; + +assign tdf3_filters_we0 = 1'b0; + +assign tdf3_filters_we1 = 1'b0; + +assign tdf3_fmaps_t_d0 = 64'd0; + +assign tdf3_fmaps_t_we0 = 1'b0; + +assign tdf4_111_U0_ap_continue = tdf4_111_U0_out_data_full_n; + +assign tdf4_111_U0_ap_start = tdf4_fmaps_t_empty_n; + +assign tdf4_111_U0_out_data_full_n = tdf5_fmaps_i_full_n; + +assign tdf4_111_U0_start_full_n = 1'b1; + +assign tdf4_111_U0_start_write = 1'b0; + +assign tdf4_adjustments_address0 = tdf4_111_U0_l1_adjustments_address0; + +assign tdf4_adjustments_address1 = 7'd0; + +assign tdf4_adjustments_ce0 = tdf4_111_U0_l1_adjustments_ce0; + +assign tdf4_adjustments_ce1 = 1'b0; + +assign tdf4_adjustments_d0 = 48'd0; + +assign tdf4_adjustments_d1 = 48'd0; + +assign tdf4_adjustments_we0 = 1'b0; + +assign tdf4_adjustments_we1 = 1'b0; + +assign tdf4_filters_0_address0 = tdf4_111_U0_l1_filter_data_0_address0; + +assign tdf4_filters_0_address1 = 11'd0; + +assign tdf4_filters_0_ce0 = tdf4_111_U0_l1_filter_data_0_ce0; + +assign tdf4_filters_0_ce1 = 1'b0; + +assign tdf4_filters_0_d0 = 64'd0; + +assign tdf4_filters_0_d1 = 64'd0; + +assign tdf4_filters_0_we0 = 1'b0; + +assign tdf4_filters_0_we1 = 1'b0; + +assign tdf4_filters_1_address0 = tdf4_111_U0_l1_filter_data_1_address0; + +assign tdf4_filters_1_address1 = 11'd0; + +assign tdf4_filters_1_ce0 = tdf4_111_U0_l1_filter_data_1_ce0; + +assign tdf4_filters_1_ce1 = 1'b0; + +assign tdf4_filters_1_d0 = 64'd0; + +assign tdf4_filters_1_d1 = 64'd0; + +assign tdf4_filters_1_we0 = 1'b0; + +assign tdf4_filters_1_we1 = 1'b0; + +assign tdf4_filters_2_address0 = tdf4_111_U0_l1_filter_data_2_address0; + +assign tdf4_filters_2_address1 = 11'd0; + +assign tdf4_filters_2_ce0 = tdf4_111_U0_l1_filter_data_2_ce0; + +assign tdf4_filters_2_ce1 = 1'b0; + +assign tdf4_filters_2_d0 = 64'd0; + +assign tdf4_filters_2_d1 = 64'd0; + +assign tdf4_filters_2_we0 = 1'b0; + +assign tdf4_filters_2_we1 = 1'b0; + +assign tdf4_filters_3_address0 = tdf4_111_U0_l1_filter_data_3_address0; + +assign tdf4_filters_3_address1 = 11'd0; + +assign tdf4_filters_3_ce0 = tdf4_111_U0_l1_filter_data_3_ce0; + +assign tdf4_filters_3_ce1 = 1'b0; + +assign tdf4_filters_3_d0 = 64'd0; + +assign tdf4_filters_3_d1 = 64'd0; + +assign tdf4_filters_3_we0 = 1'b0; + +assign tdf4_filters_3_we1 = 1'b0; + +assign tdf4_fmaps_t_d0 = 64'd0; + +assign tdf4_fmaps_t_we0 = 1'b0; + +assign tdf4_l2_adjustments_address0 = tdf4_111_U0_l2_adjustments_address0; + +assign tdf4_l2_adjustments_address1 = 4'd0; + +assign tdf4_l2_adjustments_ce0 = tdf4_111_U0_l2_adjustments_ce0; + +assign tdf4_l2_adjustments_ce1 = 1'b0; + +assign tdf4_l2_adjustments_d0 = 48'd0; + +assign tdf4_l2_adjustments_d1 = 48'd0; + +assign tdf4_l2_adjustments_we0 = 1'b0; + +assign tdf4_l2_adjustments_we1 = 1'b0; + +assign tdf4_l2_filters_0_address0 = tdf4_111_U0_l2_filter_data_0_address0; + +assign tdf4_l2_filters_0_address1 = tdf4_111_U0_l2_filter_data_0_address1; + +assign tdf4_l2_filters_0_ce0 = tdf4_111_U0_l2_filter_data_0_ce0; + +assign tdf4_l2_filters_0_ce1 = tdf4_111_U0_l2_filter_data_0_ce1; + +assign tdf4_l2_filters_0_d0 = 16'd0; + +assign tdf4_l2_filters_0_d1 = 16'd0; + +assign tdf4_l2_filters_0_we0 = 1'b0; + +assign tdf4_l2_filters_0_we1 = 1'b0; + +assign tdf4_l2_filters_1_address0 = tdf4_111_U0_l2_filter_data_1_address0; + +assign tdf4_l2_filters_1_address1 = tdf4_111_U0_l2_filter_data_1_address1; + +assign tdf4_l2_filters_1_ce0 = tdf4_111_U0_l2_filter_data_1_ce0; + +assign tdf4_l2_filters_1_ce1 = tdf4_111_U0_l2_filter_data_1_ce1; + +assign tdf4_l2_filters_1_d0 = 16'd0; + +assign tdf4_l2_filters_1_d1 = 16'd0; + +assign tdf4_l2_filters_1_we0 = 1'b0; + +assign tdf4_l2_filters_1_we1 = 1'b0; + +assign tdf5_110_U0_ap_continue = tdf5_110_U0_out_data_full_n; + +assign tdf5_110_U0_ap_start = tdf5_fmaps_t_empty_n; + +assign tdf5_110_U0_out_data_full_n = tdf6_fmaps_i_full_n; + +assign tdf5_110_U0_start_full_n = 1'b1; + +assign tdf5_110_U0_start_write = 1'b0; + +assign tdf5_adjustments_address0 = tdf5_110_U0_adjustments_address0; + +assign tdf5_adjustments_address1 = 7'd0; + +assign tdf5_adjustments_ce0 = tdf5_110_U0_adjustments_ce0; + +assign tdf5_adjustments_ce1 = 1'b0; + +assign tdf5_adjustments_d0 = 48'd0; + +assign tdf5_adjustments_d1 = 48'd0; + +assign tdf5_adjustments_we0 = 1'b0; + +assign tdf5_adjustments_we1 = 1'b0; + +assign tdf5_filters_0_address0 = tdf5_110_U0_filter_data_0_address0; + +assign tdf5_filters_0_address1 = 12'd0; + +assign tdf5_filters_0_ce0 = tdf5_110_U0_filter_data_0_ce0; + +assign tdf5_filters_0_ce1 = 1'b0; + +assign tdf5_filters_0_d0 = 32'd0; + +assign tdf5_filters_0_d1 = 32'd0; + +assign tdf5_filters_0_we0 = 1'b0; + +assign tdf5_filters_0_we1 = 1'b0; + +assign tdf5_filters_1_address0 = tdf5_110_U0_filter_data_1_address0; + +assign tdf5_filters_1_address1 = 12'd0; + +assign tdf5_filters_1_ce0 = tdf5_110_U0_filter_data_1_ce0; + +assign tdf5_filters_1_ce1 = 1'b0; + +assign tdf5_filters_1_d0 = 32'd0; + +assign tdf5_filters_1_d1 = 32'd0; + +assign tdf5_filters_1_we0 = 1'b0; + +assign tdf5_filters_1_we1 = 1'b0; + +assign tdf5_filters_2_address0 = tdf5_110_U0_filter_data_2_address0; + +assign tdf5_filters_2_address1 = 12'd0; + +assign tdf5_filters_2_ce0 = tdf5_110_U0_filter_data_2_ce0; + +assign tdf5_filters_2_ce1 = 1'b0; + +assign tdf5_filters_2_d0 = 32'd0; + +assign tdf5_filters_2_d1 = 32'd0; + +assign tdf5_filters_2_we0 = 1'b0; + +assign tdf5_filters_2_we1 = 1'b0; + +assign tdf5_filters_3_address0 = tdf5_110_U0_filter_data_3_address0; + +assign tdf5_filters_3_address1 = 12'd0; + +assign tdf5_filters_3_ce0 = tdf5_110_U0_filter_data_3_ce0; + +assign tdf5_filters_3_ce1 = 1'b0; + +assign tdf5_filters_3_d0 = 32'd0; + +assign tdf5_filters_3_d1 = 32'd0; + +assign tdf5_filters_3_we0 = 1'b0; + +assign tdf5_filters_3_we1 = 1'b0; + +assign tdf5_fmaps_t_d0 = 64'd0; + +assign tdf5_fmaps_t_we0 = 1'b0; + +assign tdf6_19_U0_ap_continue = tdf6_19_U0_out_data_full_n; + +assign tdf6_19_U0_ap_start = tdf6_fmaps_t_empty_n; + +assign tdf6_19_U0_out_data_full_n = tdf7_fmaps_i_full_n; + +assign tdf6_19_U0_start_full_n = 1'b1; + +assign tdf6_19_U0_start_write = 1'b0; + +assign tdf6_adjustments_address0 = tdf6_19_U0_adjustments_address0; + +assign tdf6_adjustments_address1 = 5'd0; + +assign tdf6_adjustments_ce0 = tdf6_19_U0_adjustments_ce0; + +assign tdf6_adjustments_ce1 = 1'b0; + +assign tdf6_adjustments_d0 = 48'd0; + +assign tdf6_adjustments_d1 = 48'd0; + +assign tdf6_adjustments_we0 = 1'b0; + +assign tdf6_adjustments_we1 = 1'b0; + +assign tdf6_filters_address0 = tdf6_19_U0_filter_data_address0; + +assign tdf6_filters_address1 = 12'd0; + +assign tdf6_filters_ce0 = tdf6_19_U0_filter_data_ce0; + +assign tdf6_filters_ce1 = 1'b0; + +assign tdf6_filters_d0 = 16'd0; + +assign tdf6_filters_d1 = 16'd0; + +assign tdf6_filters_we0 = 1'b0; + +assign tdf6_filters_we1 = 1'b0; + +assign tdf6_fmaps_t_d0 = 64'd0; + +assign tdf6_fmaps_t_we0 = 1'b0; + +assign tdf7_18_U0_ap_continue = tdf7_18_U0_out_data_full_n; + +assign tdf7_18_U0_ap_start = tdf7_fmaps_t_empty_n; + +assign tdf7_18_U0_out_data_full_n = tdf8_fmaps_i_full_n; + +assign tdf7_18_U0_start_full_n = 1'b1; + +assign tdf7_18_U0_start_write = 1'b0; + +assign tdf7_adjustments_address0 = tdf7_18_U0_l1_adjustments_address0; + +assign tdf7_adjustments_address1 = 8'd0; + +assign tdf7_adjustments_ce0 = tdf7_18_U0_l1_adjustments_ce0; + +assign tdf7_adjustments_ce1 = 1'b0; + +assign tdf7_adjustments_d0 = 48'd0; + +assign tdf7_adjustments_d1 = 48'd0; + +assign tdf7_adjustments_we0 = 1'b0; + +assign tdf7_adjustments_we1 = 1'b0; + +assign tdf7_filters_0_address0 = tdf7_18_U0_l1_filter_data_0_address0; + +assign tdf7_filters_0_address1 = 13'd0; + +assign tdf7_filters_0_ce0 = tdf7_18_U0_l1_filter_data_0_ce0; + +assign tdf7_filters_0_ce1 = 1'b0; + +assign tdf7_filters_0_d0 = 64'd0; + +assign tdf7_filters_0_d1 = 64'd0; + +assign tdf7_filters_0_we0 = 1'b0; + +assign tdf7_filters_0_we1 = 1'b0; + +assign tdf7_filters_1_address0 = tdf7_18_U0_l1_filter_data_1_address0; + +assign tdf7_filters_1_address1 = 13'd0; + +assign tdf7_filters_1_ce0 = tdf7_18_U0_l1_filter_data_1_ce0; + +assign tdf7_filters_1_ce1 = 1'b0; + +assign tdf7_filters_1_d0 = 64'd0; + +assign tdf7_filters_1_d1 = 64'd0; + +assign tdf7_filters_1_we0 = 1'b0; + +assign tdf7_filters_1_we1 = 1'b0; + +assign tdf7_filters_2_address0 = tdf7_18_U0_l1_filter_data_2_address0; + +assign tdf7_filters_2_address1 = 13'd0; + +assign tdf7_filters_2_ce0 = tdf7_18_U0_l1_filter_data_2_ce0; + +assign tdf7_filters_2_ce1 = 1'b0; + +assign tdf7_filters_2_d0 = 64'd0; + +assign tdf7_filters_2_d1 = 64'd0; + +assign tdf7_filters_2_we0 = 1'b0; + +assign tdf7_filters_2_we1 = 1'b0; + +assign tdf7_filters_3_address0 = tdf7_18_U0_l1_filter_data_3_address0; + +assign tdf7_filters_3_address1 = 13'd0; + +assign tdf7_filters_3_ce0 = tdf7_18_U0_l1_filter_data_3_ce0; + +assign tdf7_filters_3_ce1 = 1'b0; + +assign tdf7_filters_3_d0 = 64'd0; + +assign tdf7_filters_3_d1 = 64'd0; + +assign tdf7_filters_3_we0 = 1'b0; + +assign tdf7_filters_3_we1 = 1'b0; + +assign tdf7_fmaps_t_d0 = 64'd0; + +assign tdf7_fmaps_t_we0 = 1'b0; + +assign tdf7_l2_adjustments_address0 = tdf7_18_U0_l2_adjustments_address0; + +assign tdf7_l2_adjustments_address1 = 5'd0; + +assign tdf7_l2_adjustments_ce0 = tdf7_18_U0_l2_adjustments_ce0; + +assign tdf7_l2_adjustments_ce1 = 1'b0; + +assign tdf7_l2_adjustments_d0 = 48'd0; + +assign tdf7_l2_adjustments_d1 = 48'd0; + +assign tdf7_l2_adjustments_we0 = 1'b0; + +assign tdf7_l2_adjustments_we1 = 1'b0; + +assign tdf7_l2_filters_0_address0 = tdf7_18_U0_l2_filter_data_0_address0; + +assign tdf7_l2_filters_0_address1 = tdf7_18_U0_l2_filter_data_0_address1; + +assign tdf7_l2_filters_0_ce0 = tdf7_18_U0_l2_filter_data_0_ce0; + +assign tdf7_l2_filters_0_ce1 = tdf7_18_U0_l2_filter_data_0_ce1; + +assign tdf7_l2_filters_0_d0 = 16'd0; + +assign tdf7_l2_filters_0_d1 = 16'd0; + +assign tdf7_l2_filters_0_we0 = 1'b0; + +assign tdf7_l2_filters_0_we1 = 1'b0; + +assign tdf7_l2_filters_1_address0 = tdf7_18_U0_l2_filter_data_1_address0; + +assign tdf7_l2_filters_1_address1 = tdf7_18_U0_l2_filter_data_1_address1; + +assign tdf7_l2_filters_1_ce0 = tdf7_18_U0_l2_filter_data_1_ce0; + +assign tdf7_l2_filters_1_ce1 = tdf7_18_U0_l2_filter_data_1_ce1; + +assign tdf7_l2_filters_1_d0 = 16'd0; + +assign tdf7_l2_filters_1_d1 = 16'd0; + +assign tdf7_l2_filters_1_we0 = 1'b0; + +assign tdf7_l2_filters_1_we1 = 1'b0; + +assign tdf8_17_U0_ap_continue = tdf8_17_U0_out_data_full_n; + +assign tdf8_17_U0_ap_start = tdf8_fmaps_t_empty_n; + +assign tdf8_17_U0_out_data_full_n = tdf9_fmaps_i_full_n; + +assign tdf8_17_U0_start_full_n = 1'b1; + +assign tdf8_17_U0_start_write = 1'b0; + +assign tdf8_adjustments_address0 = tdf8_17_U0_adjustments_address0; + +assign tdf8_adjustments_address1 = 8'd0; + +assign tdf8_adjustments_ce0 = tdf8_17_U0_adjustments_ce0; + +assign tdf8_adjustments_ce1 = 1'b0; + +assign tdf8_adjustments_d0 = 48'd0; + +assign tdf8_adjustments_d1 = 48'd0; + +assign tdf8_adjustments_we0 = 1'b0; + +assign tdf8_adjustments_we1 = 1'b0; + +assign tdf8_filters_0_address0 = tdf8_17_U0_filter_data_0_address0; + +assign tdf8_filters_0_address1 = 14'd0; + +assign tdf8_filters_0_ce0 = tdf8_17_U0_filter_data_0_ce0; + +assign tdf8_filters_0_ce1 = 1'b0; + +assign tdf8_filters_0_d0 = 32'd0; + +assign tdf8_filters_0_d1 = 32'd0; + +assign tdf8_filters_0_we0 = 1'b0; + +assign tdf8_filters_0_we1 = 1'b0; + +assign tdf8_filters_1_address0 = tdf8_17_U0_filter_data_1_address0; + +assign tdf8_filters_1_address1 = 14'd0; + +assign tdf8_filters_1_ce0 = tdf8_17_U0_filter_data_1_ce0; + +assign tdf8_filters_1_ce1 = 1'b0; + +assign tdf8_filters_1_d0 = 32'd0; + +assign tdf8_filters_1_d1 = 32'd0; + +assign tdf8_filters_1_we0 = 1'b0; + +assign tdf8_filters_1_we1 = 1'b0; + +assign tdf8_filters_2_address0 = tdf8_17_U0_filter_data_2_address0; + +assign tdf8_filters_2_address1 = 14'd0; + +assign tdf8_filters_2_ce0 = tdf8_17_U0_filter_data_2_ce0; + +assign tdf8_filters_2_ce1 = 1'b0; + +assign tdf8_filters_2_d0 = 32'd0; + +assign tdf8_filters_2_d1 = 32'd0; + +assign tdf8_filters_2_we0 = 1'b0; + +assign tdf8_filters_2_we1 = 1'b0; + +assign tdf8_filters_3_address0 = tdf8_17_U0_filter_data_3_address0; + +assign tdf8_filters_3_address1 = 14'd0; + +assign tdf8_filters_3_ce0 = tdf8_17_U0_filter_data_3_ce0; + +assign tdf8_filters_3_ce1 = 1'b0; + +assign tdf8_filters_3_d0 = 32'd0; + +assign tdf8_filters_3_d1 = 32'd0; + +assign tdf8_filters_3_we0 = 1'b0; + +assign tdf8_filters_3_we1 = 1'b0; + +assign tdf8_fmaps_t_d0 = 64'd0; + +assign tdf8_fmaps_t_we0 = 1'b0; + +assign tdf9_16_U0_ap_continue = tdf9_16_U0_out_data_full_n; + +assign tdf9_16_U0_ap_start = tdf9_fmaps_t_empty_n; + +assign tdf9_16_U0_out_data_full_n = tdf10_fmaps_i_full_n; + +assign tdf9_16_U0_start_full_n = 1'b1; + +assign tdf9_16_U0_start_write = 1'b0; + +assign tdf9_adjustments_address0 = tdf9_16_U0_adjustments_address0; + +assign tdf9_adjustments_address1 = 6'd0; + +assign tdf9_adjustments_ce0 = tdf9_16_U0_adjustments_ce0; + +assign tdf9_adjustments_ce1 = 1'b0; + +assign tdf9_adjustments_d0 = 48'd0; + +assign tdf9_adjustments_d1 = 48'd0; + +assign tdf9_adjustments_we0 = 1'b0; + +assign tdf9_adjustments_we1 = 1'b0; + +assign tdf9_filters_address0 = tdf9_16_U0_filter_data_address0; + +assign tdf9_filters_address1 = 14'd0; + +assign tdf9_filters_ce0 = tdf9_16_U0_filter_data_ce0; + +assign tdf9_filters_ce1 = 1'b0; + +assign tdf9_filters_d0 = 16'd0; + +assign tdf9_filters_d1 = 16'd0; + +assign tdf9_filters_we0 = 1'b0; + +assign tdf9_filters_we1 = 1'b0; + +assign tdf9_fmaps_t_d0 = 64'd0; + +assign tdf9_fmaps_t_we0 = 1'b0; + +endmodule //td_fused_top_td_fused +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + + + +module td_fused_top ( + ap_clk, + ap_rst_n, + ap_start, + ap_done, + ap_idle, + ap_ready, + stream_in_TDATA, + stream_in_TVALID, + stream_in_TREADY, + stream_in_TKEEP, + stream_in_TSTRB, + stream_in_TLAST, + stream_out_TDATA, + stream_out_TVALID, + stream_out_TREADY, + stream_out_TKEEP, + stream_out_TSTRB, + stream_out_TLAST +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_state3 = 4'd4; +parameter ap_ST_fsm_state4 = 4'd8; +parameter ap_const_lv32_0 = 32'd0; +parameter ap_const_lv64_0 = 64'd0; + +input ap_clk; +input ap_rst_n; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +input [15:0] stream_in_TDATA; +input stream_in_TVALID; +output stream_in_TREADY; +input [1:0] stream_in_TKEEP; +input [1:0] stream_in_TSTRB; +input [0:0] stream_in_TLAST; +output [15:0] stream_out_TDATA; +output stream_out_TVALID; +input stream_out_TREADY; +output [1:0] stream_out_TKEEP; +output [1:0] stream_out_TSTRB; +output [0:0] stream_out_TLAST; + +reg ap_done; +reg ap_idle; +reg ap_ready; + + reg ap_rst_n_inv; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg tdf1_filters_0_ce0; +wire [15:0] tdf1_filters_0_q0; +wire [6:0] tdf1_filters_0_address1; +reg tdf1_filters_0_ce1; +reg tdf1_filters_0_we1; +wire [15:0] tdf1_filters_1_q0; +wire [15:0] tdf1_filters_2_q0; +wire [15:0] tdf1_filters_3_q0; +reg tdf2_filters_0_ce0; +wire [31:0] tdf2_filters_0_q0; +wire [9:0] tdf2_filters_0_address1; +reg tdf2_filters_0_ce1; +reg tdf2_filters_0_we1; +wire [31:0] tdf2_filters_1_q0; +wire [31:0] tdf2_filters_2_q0; +wire [31:0] tdf2_filters_3_q0; +reg tdf3_filters_ce0; +wire [15:0] tdf3_filters_q0; +wire [8:0] tdf3_filters_address1; +reg tdf3_filters_ce1; +reg tdf3_filters_we1; +reg tdf4_filters_0_ce0; +wire [63:0] tdf4_filters_0_q0; +wire [10:0] tdf4_filters_0_address1; +reg tdf4_filters_0_ce1; +reg tdf4_filters_0_we1; +wire [63:0] tdf4_filters_1_q0; +wire [63:0] tdf4_filters_2_q0; +wire [63:0] tdf4_filters_3_q0; +reg tdf4_l2_filters_0_ce0; +wire [15:0] tdf4_l2_filters_0_q0; +reg [9:0] tdf4_l2_filters_0_address1; +reg tdf4_l2_filters_0_ce1; +reg tdf4_l2_filters_0_we1; +wire [15:0] tdf4_l2_filters_0_q1; +wire [15:0] tdf4_l2_filters_1_q0; +wire [15:0] tdf4_l2_filters_1_q1; +reg tdf5_filters_0_ce0; +wire [31:0] tdf5_filters_0_q0; +wire [11:0] tdf5_filters_0_address1; +reg tdf5_filters_0_ce1; +reg tdf5_filters_0_we1; +wire [31:0] tdf5_filters_1_q0; +wire [31:0] tdf5_filters_2_q0; +wire [31:0] tdf5_filters_3_q0; +reg tdf6_filters_ce0; +wire [15:0] tdf6_filters_q0; +wire [11:0] tdf6_filters_address1; +reg tdf6_filters_ce1; +reg tdf6_filters_we1; +reg tdf7_filters_0_ce0; +wire [63:0] tdf7_filters_0_q0; +wire [12:0] tdf7_filters_0_address1; +reg tdf7_filters_0_ce1; +reg tdf7_filters_0_we1; +wire [63:0] tdf7_filters_1_q0; +wire [63:0] tdf7_filters_2_q0; +wire [63:0] tdf7_filters_3_q0; +reg tdf7_l2_filters_0_ce0; +wire [15:0] tdf7_l2_filters_0_q0; +reg [11:0] tdf7_l2_filters_0_address1; +reg tdf7_l2_filters_0_ce1; +reg tdf7_l2_filters_0_we1; +wire [15:0] tdf7_l2_filters_0_q1; +wire [15:0] tdf7_l2_filters_1_q0; +wire [15:0] tdf7_l2_filters_1_q1; +reg tdf8_filters_0_ce0; +wire [31:0] tdf8_filters_0_q0; +wire [13:0] tdf8_filters_0_address1; +reg tdf8_filters_0_ce1; +reg tdf8_filters_0_we1; +wire [31:0] tdf8_filters_1_q0; +wire [31:0] tdf8_filters_2_q0; +wire [31:0] tdf8_filters_3_q0; +reg tdf9_filters_ce0; +wire [15:0] tdf9_filters_q0; +wire [13:0] tdf9_filters_address1; +reg tdf9_filters_ce1; +reg tdf9_filters_we1; +reg tdf10_filters_0_ce0; +wire [63:0] tdf10_filters_0_q0; +wire [14:0] tdf10_filters_0_address1; +reg tdf10_filters_0_ce1; +reg tdf10_filters_0_we1; +wire [63:0] tdf10_filters_1_q0; +wire [63:0] tdf10_filters_2_q0; +wire [63:0] tdf10_filters_3_q0; +reg tdf10_l2_filters_0_ce0; +wire [15:0] tdf10_l2_filters_0_q0; +reg [13:0] tdf10_l2_filters_0_address1; +reg tdf10_l2_filters_0_ce1; +reg tdf10_l2_filters_0_we1; +wire [15:0] tdf10_l2_filters_0_q1; +wire [15:0] tdf10_l2_filters_1_q0; +wire [15:0] tdf10_l2_filters_1_q1; +reg tdf11_filters_0_ce0; +wire [63:0] tdf11_filters_0_q0; +wire [14:0] tdf11_filters_0_address1; +reg tdf11_filters_0_ce1; +reg tdf11_filters_0_we1; +wire [63:0] tdf11_filters_1_q0; +wire [63:0] tdf11_filters_2_q0; +wire [63:0] tdf11_filters_3_q0; +reg tdf11_l2_filters_0_ce0; +wire [15:0] tdf11_l2_filters_0_q0; +reg [13:0] tdf11_l2_filters_0_address1; +reg tdf11_l2_filters_0_ce1; +reg tdf11_l2_filters_0_we1; +wire [15:0] tdf11_l2_filters_0_q1; +wire [15:0] tdf11_l2_filters_1_q0; +wire [15:0] tdf11_l2_filters_1_q1; +wire [15:0] tdf11_l2_filters_2_q0; +wire [15:0] tdf11_l2_filters_2_q1; +wire [15:0] tdf11_l2_filters_3_q0; +wire [15:0] tdf11_l2_filters_3_q1; +reg tdf12_filters_0_ce0; +wire [31:0] tdf12_filters_0_q0; +wire [14:0] tdf12_filters_0_address1; +reg tdf12_filters_0_ce1; +reg tdf12_filters_0_we1; +wire [31:0] tdf12_filters_1_q0; +reg tdf1_adjustments_ce0; +wire [47:0] tdf1_adjustments_q0; +wire [3:0] tdf1_adjustments_address1; +reg tdf1_adjustments_ce1; +reg tdf1_adjustments_we1; +reg tdf2_adjustments_ce0; +wire [47:0] tdf2_adjustments_q0; +wire [4:0] tdf2_adjustments_address1; +reg tdf2_adjustments_ce1; +reg tdf2_adjustments_we1; +reg tdf3_adjustments_ce0; +wire [47:0] tdf3_adjustments_q0; +wire [3:0] tdf3_adjustments_address1; +reg tdf3_adjustments_ce1; +reg tdf3_adjustments_we1; +reg tdf4_adjustments_ce0; +wire [47:0] tdf4_adjustments_q0; +wire [6:0] tdf4_adjustments_address1; +reg tdf4_adjustments_ce1; +reg tdf4_adjustments_we1; +reg tdf4_l2_adjustments_ce0; +wire [47:0] tdf4_l2_adjustments_q0; +wire [3:0] tdf4_l2_adjustments_address1; +reg tdf4_l2_adjustments_ce1; +reg tdf4_l2_adjustments_we1; +reg tdf5_adjustments_ce0; +wire [47:0] tdf5_adjustments_q0; +wire [6:0] tdf5_adjustments_address1; +reg tdf5_adjustments_ce1; +reg tdf5_adjustments_we1; +reg tdf6_adjustments_ce0; +wire [47:0] tdf6_adjustments_q0; +wire [4:0] tdf6_adjustments_address1; +reg tdf6_adjustments_ce1; +reg tdf6_adjustments_we1; +reg tdf7_adjustments_ce0; +wire [47:0] tdf7_adjustments_q0; +wire [7:0] tdf7_adjustments_address1; +reg tdf7_adjustments_ce1; +reg tdf7_adjustments_we1; +reg tdf7_l2_adjustments_ce0; +wire [47:0] tdf7_l2_adjustments_q0; +wire [4:0] tdf7_l2_adjustments_address1; +reg tdf7_l2_adjustments_ce1; +reg tdf7_l2_adjustments_we1; +reg tdf8_adjustments_ce0; +wire [47:0] tdf8_adjustments_q0; +wire [7:0] tdf8_adjustments_address1; +reg tdf8_adjustments_ce1; +reg tdf8_adjustments_we1; +reg tdf9_adjustments_ce0; +wire [47:0] tdf9_adjustments_q0; +wire [5:0] tdf9_adjustments_address1; +reg tdf9_adjustments_ce1; +reg tdf9_adjustments_we1; +reg tdf10_adjustments_ce0; +wire [47:0] tdf10_adjustments_q0; +wire [8:0] tdf10_adjustments_address1; +reg tdf10_adjustments_ce1; +reg tdf10_adjustments_we1; +reg tdf10_l2_adjustments_ce0; +wire [47:0] tdf10_l2_adjustments_q0; +wire [5:0] tdf10_l2_adjustments_address1; +reg tdf10_l2_adjustments_ce1; +reg tdf10_l2_adjustments_we1; +reg tdf11_adjustments_ce0; +wire [47:0] tdf11_adjustments_q0; +wire [8:0] tdf11_adjustments_address1; +reg tdf11_adjustments_ce1; +reg tdf11_adjustments_we1; +reg tdf11_l2_adjustments_ce0; +wire [47:0] tdf11_l2_adjustments_q0; +wire [6:0] tdf11_l2_adjustments_address1; +reg tdf11_l2_adjustments_ce1; +reg tdf11_l2_adjustments_we1; +reg tdf12_adjustments_ce0; +wire [47:0] tdf12_adjustments_q0; +wire [9:0] tdf12_adjustments_address1; +reg tdf12_adjustments_ce1; +reg tdf12_adjustments_we1; +wire [6:0] grp_td_fused_fu_1094_tdf1_filters_0_address0; +wire grp_td_fused_fu_1094_tdf1_filters_0_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf1_filters_0_d0; +wire grp_td_fused_fu_1094_tdf1_filters_0_we0; +wire [6:0] grp_td_fused_fu_1094_tdf1_filters_0_address1; +wire grp_td_fused_fu_1094_tdf1_filters_0_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf1_filters_0_d1; +wire grp_td_fused_fu_1094_tdf1_filters_0_we1; +wire [6:0] grp_td_fused_fu_1094_tdf1_filters_1_address0; +wire grp_td_fused_fu_1094_tdf1_filters_1_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf1_filters_1_d0; +wire grp_td_fused_fu_1094_tdf1_filters_1_we0; +wire [6:0] grp_td_fused_fu_1094_tdf1_filters_1_address1; +wire grp_td_fused_fu_1094_tdf1_filters_1_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf1_filters_1_d1; +wire grp_td_fused_fu_1094_tdf1_filters_1_we1; +wire [6:0] grp_td_fused_fu_1094_tdf1_filters_2_address0; +wire grp_td_fused_fu_1094_tdf1_filters_2_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf1_filters_2_d0; +wire grp_td_fused_fu_1094_tdf1_filters_2_we0; +wire [6:0] grp_td_fused_fu_1094_tdf1_filters_2_address1; +wire grp_td_fused_fu_1094_tdf1_filters_2_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf1_filters_2_d1; +wire grp_td_fused_fu_1094_tdf1_filters_2_we1; +wire [6:0] grp_td_fused_fu_1094_tdf1_filters_3_address0; +wire grp_td_fused_fu_1094_tdf1_filters_3_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf1_filters_3_d0; +wire grp_td_fused_fu_1094_tdf1_filters_3_we0; +wire [6:0] grp_td_fused_fu_1094_tdf1_filters_3_address1; +wire grp_td_fused_fu_1094_tdf1_filters_3_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf1_filters_3_d1; +wire grp_td_fused_fu_1094_tdf1_filters_3_we1; +wire [9:0] grp_td_fused_fu_1094_tdf2_filters_0_address0; +wire grp_td_fused_fu_1094_tdf2_filters_0_ce0; +wire [31:0] grp_td_fused_fu_1094_tdf2_filters_0_d0; +wire grp_td_fused_fu_1094_tdf2_filters_0_we0; +wire [9:0] grp_td_fused_fu_1094_tdf2_filters_0_address1; +wire grp_td_fused_fu_1094_tdf2_filters_0_ce1; +wire [31:0] grp_td_fused_fu_1094_tdf2_filters_0_d1; +wire grp_td_fused_fu_1094_tdf2_filters_0_we1; +wire [9:0] grp_td_fused_fu_1094_tdf2_filters_1_address0; +wire grp_td_fused_fu_1094_tdf2_filters_1_ce0; +wire [31:0] grp_td_fused_fu_1094_tdf2_filters_1_d0; +wire grp_td_fused_fu_1094_tdf2_filters_1_we0; +wire [9:0] grp_td_fused_fu_1094_tdf2_filters_1_address1; +wire grp_td_fused_fu_1094_tdf2_filters_1_ce1; +wire [31:0] grp_td_fused_fu_1094_tdf2_filters_1_d1; +wire grp_td_fused_fu_1094_tdf2_filters_1_we1; +wire [9:0] grp_td_fused_fu_1094_tdf2_filters_2_address0; +wire grp_td_fused_fu_1094_tdf2_filters_2_ce0; +wire [31:0] grp_td_fused_fu_1094_tdf2_filters_2_d0; +wire grp_td_fused_fu_1094_tdf2_filters_2_we0; +wire [9:0] grp_td_fused_fu_1094_tdf2_filters_2_address1; +wire grp_td_fused_fu_1094_tdf2_filters_2_ce1; +wire [31:0] grp_td_fused_fu_1094_tdf2_filters_2_d1; +wire grp_td_fused_fu_1094_tdf2_filters_2_we1; +wire [9:0] grp_td_fused_fu_1094_tdf2_filters_3_address0; +wire grp_td_fused_fu_1094_tdf2_filters_3_ce0; +wire [31:0] grp_td_fused_fu_1094_tdf2_filters_3_d0; +wire grp_td_fused_fu_1094_tdf2_filters_3_we0; +wire [9:0] grp_td_fused_fu_1094_tdf2_filters_3_address1; +wire grp_td_fused_fu_1094_tdf2_filters_3_ce1; +wire [31:0] grp_td_fused_fu_1094_tdf2_filters_3_d1; +wire grp_td_fused_fu_1094_tdf2_filters_3_we1; +wire [8:0] grp_td_fused_fu_1094_tdf3_filters_address0; +wire grp_td_fused_fu_1094_tdf3_filters_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf3_filters_d0; +wire grp_td_fused_fu_1094_tdf3_filters_we0; +wire [8:0] grp_td_fused_fu_1094_tdf3_filters_address1; +wire grp_td_fused_fu_1094_tdf3_filters_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf3_filters_d1; +wire grp_td_fused_fu_1094_tdf3_filters_we1; +wire [10:0] grp_td_fused_fu_1094_tdf4_filters_0_address0; +wire grp_td_fused_fu_1094_tdf4_filters_0_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf4_filters_0_d0; +wire grp_td_fused_fu_1094_tdf4_filters_0_we0; +wire [10:0] grp_td_fused_fu_1094_tdf4_filters_0_address1; +wire grp_td_fused_fu_1094_tdf4_filters_0_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf4_filters_0_d1; +wire grp_td_fused_fu_1094_tdf4_filters_0_we1; +wire [10:0] grp_td_fused_fu_1094_tdf4_filters_1_address0; +wire grp_td_fused_fu_1094_tdf4_filters_1_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf4_filters_1_d0; +wire grp_td_fused_fu_1094_tdf4_filters_1_we0; +wire [10:0] grp_td_fused_fu_1094_tdf4_filters_1_address1; +wire grp_td_fused_fu_1094_tdf4_filters_1_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf4_filters_1_d1; +wire grp_td_fused_fu_1094_tdf4_filters_1_we1; +wire [10:0] grp_td_fused_fu_1094_tdf4_filters_2_address0; +wire grp_td_fused_fu_1094_tdf4_filters_2_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf4_filters_2_d0; +wire grp_td_fused_fu_1094_tdf4_filters_2_we0; +wire [10:0] grp_td_fused_fu_1094_tdf4_filters_2_address1; +wire grp_td_fused_fu_1094_tdf4_filters_2_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf4_filters_2_d1; +wire grp_td_fused_fu_1094_tdf4_filters_2_we1; +wire [10:0] grp_td_fused_fu_1094_tdf4_filters_3_address0; +wire grp_td_fused_fu_1094_tdf4_filters_3_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf4_filters_3_d0; +wire grp_td_fused_fu_1094_tdf4_filters_3_we0; +wire [10:0] grp_td_fused_fu_1094_tdf4_filters_3_address1; +wire grp_td_fused_fu_1094_tdf4_filters_3_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf4_filters_3_d1; +wire grp_td_fused_fu_1094_tdf4_filters_3_we1; +wire [9:0] grp_td_fused_fu_1094_tdf4_l2_filters_0_address0; +wire grp_td_fused_fu_1094_tdf4_l2_filters_0_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf4_l2_filters_0_d0; +wire grp_td_fused_fu_1094_tdf4_l2_filters_0_we0; +wire [9:0] grp_td_fused_fu_1094_tdf4_l2_filters_0_address1; +wire grp_td_fused_fu_1094_tdf4_l2_filters_0_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf4_l2_filters_0_d1; +wire grp_td_fused_fu_1094_tdf4_l2_filters_0_we1; +wire [9:0] grp_td_fused_fu_1094_tdf4_l2_filters_1_address0; +wire grp_td_fused_fu_1094_tdf4_l2_filters_1_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf4_l2_filters_1_d0; +wire grp_td_fused_fu_1094_tdf4_l2_filters_1_we0; +wire [9:0] grp_td_fused_fu_1094_tdf4_l2_filters_1_address1; +wire grp_td_fused_fu_1094_tdf4_l2_filters_1_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf4_l2_filters_1_d1; +wire grp_td_fused_fu_1094_tdf4_l2_filters_1_we1; +wire [11:0] grp_td_fused_fu_1094_tdf5_filters_0_address0; +wire grp_td_fused_fu_1094_tdf5_filters_0_ce0; +wire [31:0] grp_td_fused_fu_1094_tdf5_filters_0_d0; +wire grp_td_fused_fu_1094_tdf5_filters_0_we0; +wire [11:0] grp_td_fused_fu_1094_tdf5_filters_0_address1; +wire grp_td_fused_fu_1094_tdf5_filters_0_ce1; +wire [31:0] grp_td_fused_fu_1094_tdf5_filters_0_d1; +wire grp_td_fused_fu_1094_tdf5_filters_0_we1; +wire [11:0] grp_td_fused_fu_1094_tdf5_filters_1_address0; +wire grp_td_fused_fu_1094_tdf5_filters_1_ce0; +wire [31:0] grp_td_fused_fu_1094_tdf5_filters_1_d0; +wire grp_td_fused_fu_1094_tdf5_filters_1_we0; +wire [11:0] grp_td_fused_fu_1094_tdf5_filters_1_address1; +wire grp_td_fused_fu_1094_tdf5_filters_1_ce1; +wire [31:0] grp_td_fused_fu_1094_tdf5_filters_1_d1; +wire grp_td_fused_fu_1094_tdf5_filters_1_we1; +wire [11:0] grp_td_fused_fu_1094_tdf5_filters_2_address0; +wire grp_td_fused_fu_1094_tdf5_filters_2_ce0; +wire [31:0] grp_td_fused_fu_1094_tdf5_filters_2_d0; +wire grp_td_fused_fu_1094_tdf5_filters_2_we0; +wire [11:0] grp_td_fused_fu_1094_tdf5_filters_2_address1; +wire grp_td_fused_fu_1094_tdf5_filters_2_ce1; +wire [31:0] grp_td_fused_fu_1094_tdf5_filters_2_d1; +wire grp_td_fused_fu_1094_tdf5_filters_2_we1; +wire [11:0] grp_td_fused_fu_1094_tdf5_filters_3_address0; +wire grp_td_fused_fu_1094_tdf5_filters_3_ce0; +wire [31:0] grp_td_fused_fu_1094_tdf5_filters_3_d0; +wire grp_td_fused_fu_1094_tdf5_filters_3_we0; +wire [11:0] grp_td_fused_fu_1094_tdf5_filters_3_address1; +wire grp_td_fused_fu_1094_tdf5_filters_3_ce1; +wire [31:0] grp_td_fused_fu_1094_tdf5_filters_3_d1; +wire grp_td_fused_fu_1094_tdf5_filters_3_we1; +wire [11:0] grp_td_fused_fu_1094_tdf6_filters_address0; +wire grp_td_fused_fu_1094_tdf6_filters_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf6_filters_d0; +wire grp_td_fused_fu_1094_tdf6_filters_we0; +wire [11:0] grp_td_fused_fu_1094_tdf6_filters_address1; +wire grp_td_fused_fu_1094_tdf6_filters_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf6_filters_d1; +wire grp_td_fused_fu_1094_tdf6_filters_we1; +wire [12:0] grp_td_fused_fu_1094_tdf7_filters_0_address0; +wire grp_td_fused_fu_1094_tdf7_filters_0_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf7_filters_0_d0; +wire grp_td_fused_fu_1094_tdf7_filters_0_we0; +wire [12:0] grp_td_fused_fu_1094_tdf7_filters_0_address1; +wire grp_td_fused_fu_1094_tdf7_filters_0_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf7_filters_0_d1; +wire grp_td_fused_fu_1094_tdf7_filters_0_we1; +wire [12:0] grp_td_fused_fu_1094_tdf7_filters_1_address0; +wire grp_td_fused_fu_1094_tdf7_filters_1_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf7_filters_1_d0; +wire grp_td_fused_fu_1094_tdf7_filters_1_we0; +wire [12:0] grp_td_fused_fu_1094_tdf7_filters_1_address1; +wire grp_td_fused_fu_1094_tdf7_filters_1_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf7_filters_1_d1; +wire grp_td_fused_fu_1094_tdf7_filters_1_we1; +wire [12:0] grp_td_fused_fu_1094_tdf7_filters_2_address0; +wire grp_td_fused_fu_1094_tdf7_filters_2_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf7_filters_2_d0; +wire grp_td_fused_fu_1094_tdf7_filters_2_we0; +wire [12:0] grp_td_fused_fu_1094_tdf7_filters_2_address1; +wire grp_td_fused_fu_1094_tdf7_filters_2_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf7_filters_2_d1; +wire grp_td_fused_fu_1094_tdf7_filters_2_we1; +wire [12:0] grp_td_fused_fu_1094_tdf7_filters_3_address0; +wire grp_td_fused_fu_1094_tdf7_filters_3_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf7_filters_3_d0; +wire grp_td_fused_fu_1094_tdf7_filters_3_we0; +wire [12:0] grp_td_fused_fu_1094_tdf7_filters_3_address1; +wire grp_td_fused_fu_1094_tdf7_filters_3_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf7_filters_3_d1; +wire grp_td_fused_fu_1094_tdf7_filters_3_we1; +wire [11:0] grp_td_fused_fu_1094_tdf7_l2_filters_0_address0; +wire grp_td_fused_fu_1094_tdf7_l2_filters_0_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf7_l2_filters_0_d0; +wire grp_td_fused_fu_1094_tdf7_l2_filters_0_we0; +wire [11:0] grp_td_fused_fu_1094_tdf7_l2_filters_0_address1; +wire grp_td_fused_fu_1094_tdf7_l2_filters_0_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf7_l2_filters_0_d1; +wire grp_td_fused_fu_1094_tdf7_l2_filters_0_we1; +wire [11:0] grp_td_fused_fu_1094_tdf7_l2_filters_1_address0; +wire grp_td_fused_fu_1094_tdf7_l2_filters_1_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf7_l2_filters_1_d0; +wire grp_td_fused_fu_1094_tdf7_l2_filters_1_we0; +wire [11:0] grp_td_fused_fu_1094_tdf7_l2_filters_1_address1; +wire grp_td_fused_fu_1094_tdf7_l2_filters_1_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf7_l2_filters_1_d1; +wire grp_td_fused_fu_1094_tdf7_l2_filters_1_we1; +wire [13:0] grp_td_fused_fu_1094_tdf8_filters_0_address0; +wire grp_td_fused_fu_1094_tdf8_filters_0_ce0; +wire [31:0] grp_td_fused_fu_1094_tdf8_filters_0_d0; +wire grp_td_fused_fu_1094_tdf8_filters_0_we0; +wire [13:0] grp_td_fused_fu_1094_tdf8_filters_0_address1; +wire grp_td_fused_fu_1094_tdf8_filters_0_ce1; +wire [31:0] grp_td_fused_fu_1094_tdf8_filters_0_d1; +wire grp_td_fused_fu_1094_tdf8_filters_0_we1; +wire [13:0] grp_td_fused_fu_1094_tdf8_filters_1_address0; +wire grp_td_fused_fu_1094_tdf8_filters_1_ce0; +wire [31:0] grp_td_fused_fu_1094_tdf8_filters_1_d0; +wire grp_td_fused_fu_1094_tdf8_filters_1_we0; +wire [13:0] grp_td_fused_fu_1094_tdf8_filters_1_address1; +wire grp_td_fused_fu_1094_tdf8_filters_1_ce1; +wire [31:0] grp_td_fused_fu_1094_tdf8_filters_1_d1; +wire grp_td_fused_fu_1094_tdf8_filters_1_we1; +wire [13:0] grp_td_fused_fu_1094_tdf8_filters_2_address0; +wire grp_td_fused_fu_1094_tdf8_filters_2_ce0; +wire [31:0] grp_td_fused_fu_1094_tdf8_filters_2_d0; +wire grp_td_fused_fu_1094_tdf8_filters_2_we0; +wire [13:0] grp_td_fused_fu_1094_tdf8_filters_2_address1; +wire grp_td_fused_fu_1094_tdf8_filters_2_ce1; +wire [31:0] grp_td_fused_fu_1094_tdf8_filters_2_d1; +wire grp_td_fused_fu_1094_tdf8_filters_2_we1; +wire [13:0] grp_td_fused_fu_1094_tdf8_filters_3_address0; +wire grp_td_fused_fu_1094_tdf8_filters_3_ce0; +wire [31:0] grp_td_fused_fu_1094_tdf8_filters_3_d0; +wire grp_td_fused_fu_1094_tdf8_filters_3_we0; +wire [13:0] grp_td_fused_fu_1094_tdf8_filters_3_address1; +wire grp_td_fused_fu_1094_tdf8_filters_3_ce1; +wire [31:0] grp_td_fused_fu_1094_tdf8_filters_3_d1; +wire grp_td_fused_fu_1094_tdf8_filters_3_we1; +wire [13:0] grp_td_fused_fu_1094_tdf9_filters_address0; +wire grp_td_fused_fu_1094_tdf9_filters_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf9_filters_d0; +wire grp_td_fused_fu_1094_tdf9_filters_we0; +wire [13:0] grp_td_fused_fu_1094_tdf9_filters_address1; +wire grp_td_fused_fu_1094_tdf9_filters_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf9_filters_d1; +wire grp_td_fused_fu_1094_tdf9_filters_we1; +wire [14:0] grp_td_fused_fu_1094_tdf10_filters_0_address0; +wire grp_td_fused_fu_1094_tdf10_filters_0_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf10_filters_0_d0; +wire grp_td_fused_fu_1094_tdf10_filters_0_we0; +wire [14:0] grp_td_fused_fu_1094_tdf10_filters_0_address1; +wire grp_td_fused_fu_1094_tdf10_filters_0_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf10_filters_0_d1; +wire grp_td_fused_fu_1094_tdf10_filters_0_we1; +wire [14:0] grp_td_fused_fu_1094_tdf10_filters_1_address0; +wire grp_td_fused_fu_1094_tdf10_filters_1_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf10_filters_1_d0; +wire grp_td_fused_fu_1094_tdf10_filters_1_we0; +wire [14:0] grp_td_fused_fu_1094_tdf10_filters_1_address1; +wire grp_td_fused_fu_1094_tdf10_filters_1_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf10_filters_1_d1; +wire grp_td_fused_fu_1094_tdf10_filters_1_we1; +wire [14:0] grp_td_fused_fu_1094_tdf10_filters_2_address0; +wire grp_td_fused_fu_1094_tdf10_filters_2_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf10_filters_2_d0; +wire grp_td_fused_fu_1094_tdf10_filters_2_we0; +wire [14:0] grp_td_fused_fu_1094_tdf10_filters_2_address1; +wire grp_td_fused_fu_1094_tdf10_filters_2_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf10_filters_2_d1; +wire grp_td_fused_fu_1094_tdf10_filters_2_we1; +wire [14:0] grp_td_fused_fu_1094_tdf10_filters_3_address0; +wire grp_td_fused_fu_1094_tdf10_filters_3_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf10_filters_3_d0; +wire grp_td_fused_fu_1094_tdf10_filters_3_we0; +wire [14:0] grp_td_fused_fu_1094_tdf10_filters_3_address1; +wire grp_td_fused_fu_1094_tdf10_filters_3_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf10_filters_3_d1; +wire grp_td_fused_fu_1094_tdf10_filters_3_we1; +wire [13:0] grp_td_fused_fu_1094_tdf10_l2_filters_0_address0; +wire grp_td_fused_fu_1094_tdf10_l2_filters_0_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf10_l2_filters_0_d0; +wire grp_td_fused_fu_1094_tdf10_l2_filters_0_we0; +wire [13:0] grp_td_fused_fu_1094_tdf10_l2_filters_0_address1; +wire grp_td_fused_fu_1094_tdf10_l2_filters_0_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf10_l2_filters_0_d1; +wire grp_td_fused_fu_1094_tdf10_l2_filters_0_we1; +wire [13:0] grp_td_fused_fu_1094_tdf10_l2_filters_1_address0; +wire grp_td_fused_fu_1094_tdf10_l2_filters_1_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf10_l2_filters_1_d0; +wire grp_td_fused_fu_1094_tdf10_l2_filters_1_we0; +wire [13:0] grp_td_fused_fu_1094_tdf10_l2_filters_1_address1; +wire grp_td_fused_fu_1094_tdf10_l2_filters_1_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf10_l2_filters_1_d1; +wire grp_td_fused_fu_1094_tdf10_l2_filters_1_we1; +wire [14:0] grp_td_fused_fu_1094_tdf11_filters_0_address0; +wire grp_td_fused_fu_1094_tdf11_filters_0_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf11_filters_0_d0; +wire grp_td_fused_fu_1094_tdf11_filters_0_we0; +wire [14:0] grp_td_fused_fu_1094_tdf11_filters_0_address1; +wire grp_td_fused_fu_1094_tdf11_filters_0_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf11_filters_0_d1; +wire grp_td_fused_fu_1094_tdf11_filters_0_we1; +wire [14:0] grp_td_fused_fu_1094_tdf11_filters_1_address0; +wire grp_td_fused_fu_1094_tdf11_filters_1_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf11_filters_1_d0; +wire grp_td_fused_fu_1094_tdf11_filters_1_we0; +wire [14:0] grp_td_fused_fu_1094_tdf11_filters_1_address1; +wire grp_td_fused_fu_1094_tdf11_filters_1_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf11_filters_1_d1; +wire grp_td_fused_fu_1094_tdf11_filters_1_we1; +wire [14:0] grp_td_fused_fu_1094_tdf11_filters_2_address0; +wire grp_td_fused_fu_1094_tdf11_filters_2_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf11_filters_2_d0; +wire grp_td_fused_fu_1094_tdf11_filters_2_we0; +wire [14:0] grp_td_fused_fu_1094_tdf11_filters_2_address1; +wire grp_td_fused_fu_1094_tdf11_filters_2_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf11_filters_2_d1; +wire grp_td_fused_fu_1094_tdf11_filters_2_we1; +wire [14:0] grp_td_fused_fu_1094_tdf11_filters_3_address0; +wire grp_td_fused_fu_1094_tdf11_filters_3_ce0; +wire [63:0] grp_td_fused_fu_1094_tdf11_filters_3_d0; +wire grp_td_fused_fu_1094_tdf11_filters_3_we0; +wire [14:0] grp_td_fused_fu_1094_tdf11_filters_3_address1; +wire grp_td_fused_fu_1094_tdf11_filters_3_ce1; +wire [63:0] grp_td_fused_fu_1094_tdf11_filters_3_d1; +wire grp_td_fused_fu_1094_tdf11_filters_3_we1; +wire [13:0] grp_td_fused_fu_1094_tdf11_l2_filters_0_address0; +wire grp_td_fused_fu_1094_tdf11_l2_filters_0_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf11_l2_filters_0_d0; +wire grp_td_fused_fu_1094_tdf11_l2_filters_0_we0; +wire [13:0] grp_td_fused_fu_1094_tdf11_l2_filters_0_address1; +wire grp_td_fused_fu_1094_tdf11_l2_filters_0_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf11_l2_filters_0_d1; +wire grp_td_fused_fu_1094_tdf11_l2_filters_0_we1; +wire [13:0] grp_td_fused_fu_1094_tdf11_l2_filters_1_address0; +wire grp_td_fused_fu_1094_tdf11_l2_filters_1_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf11_l2_filters_1_d0; +wire grp_td_fused_fu_1094_tdf11_l2_filters_1_we0; +wire [13:0] grp_td_fused_fu_1094_tdf11_l2_filters_1_address1; +wire grp_td_fused_fu_1094_tdf11_l2_filters_1_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf11_l2_filters_1_d1; +wire grp_td_fused_fu_1094_tdf11_l2_filters_1_we1; +wire [13:0] grp_td_fused_fu_1094_tdf11_l2_filters_2_address0; +wire grp_td_fused_fu_1094_tdf11_l2_filters_2_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf11_l2_filters_2_d0; +wire grp_td_fused_fu_1094_tdf11_l2_filters_2_we0; +wire [13:0] grp_td_fused_fu_1094_tdf11_l2_filters_2_address1; +wire grp_td_fused_fu_1094_tdf11_l2_filters_2_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf11_l2_filters_2_d1; +wire grp_td_fused_fu_1094_tdf11_l2_filters_2_we1; +wire [13:0] grp_td_fused_fu_1094_tdf11_l2_filters_3_address0; +wire grp_td_fused_fu_1094_tdf11_l2_filters_3_ce0; +wire [15:0] grp_td_fused_fu_1094_tdf11_l2_filters_3_d0; +wire grp_td_fused_fu_1094_tdf11_l2_filters_3_we0; +wire [13:0] grp_td_fused_fu_1094_tdf11_l2_filters_3_address1; +wire grp_td_fused_fu_1094_tdf11_l2_filters_3_ce1; +wire [15:0] grp_td_fused_fu_1094_tdf11_l2_filters_3_d1; +wire grp_td_fused_fu_1094_tdf11_l2_filters_3_we1; +wire [14:0] grp_td_fused_fu_1094_tdf12_filters_0_address0; +wire grp_td_fused_fu_1094_tdf12_filters_0_ce0; +wire [31:0] grp_td_fused_fu_1094_tdf12_filters_0_d0; +wire grp_td_fused_fu_1094_tdf12_filters_0_we0; +wire [14:0] grp_td_fused_fu_1094_tdf12_filters_0_address1; +wire grp_td_fused_fu_1094_tdf12_filters_0_ce1; +wire [31:0] grp_td_fused_fu_1094_tdf12_filters_0_d1; +wire grp_td_fused_fu_1094_tdf12_filters_0_we1; +wire [14:0] grp_td_fused_fu_1094_tdf12_filters_1_address0; +wire grp_td_fused_fu_1094_tdf12_filters_1_ce0; +wire [31:0] grp_td_fused_fu_1094_tdf12_filters_1_d0; +wire grp_td_fused_fu_1094_tdf12_filters_1_we0; +wire [14:0] grp_td_fused_fu_1094_tdf12_filters_1_address1; +wire grp_td_fused_fu_1094_tdf12_filters_1_ce1; +wire [31:0] grp_td_fused_fu_1094_tdf12_filters_1_d1; +wire grp_td_fused_fu_1094_tdf12_filters_1_we1; +wire [3:0] grp_td_fused_fu_1094_tdf1_adjustments_address0; +wire grp_td_fused_fu_1094_tdf1_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf1_adjustments_d0; +wire grp_td_fused_fu_1094_tdf1_adjustments_we0; +wire [3:0] grp_td_fused_fu_1094_tdf1_adjustments_address1; +wire grp_td_fused_fu_1094_tdf1_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf1_adjustments_d1; +wire grp_td_fused_fu_1094_tdf1_adjustments_we1; +wire [4:0] grp_td_fused_fu_1094_tdf2_adjustments_address0; +wire grp_td_fused_fu_1094_tdf2_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf2_adjustments_d0; +wire grp_td_fused_fu_1094_tdf2_adjustments_we0; +wire [4:0] grp_td_fused_fu_1094_tdf2_adjustments_address1; +wire grp_td_fused_fu_1094_tdf2_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf2_adjustments_d1; +wire grp_td_fused_fu_1094_tdf2_adjustments_we1; +wire [3:0] grp_td_fused_fu_1094_tdf3_adjustments_address0; +wire grp_td_fused_fu_1094_tdf3_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf3_adjustments_d0; +wire grp_td_fused_fu_1094_tdf3_adjustments_we0; +wire [3:0] grp_td_fused_fu_1094_tdf3_adjustments_address1; +wire grp_td_fused_fu_1094_tdf3_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf3_adjustments_d1; +wire grp_td_fused_fu_1094_tdf3_adjustments_we1; +wire [6:0] grp_td_fused_fu_1094_tdf4_adjustments_address0; +wire grp_td_fused_fu_1094_tdf4_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf4_adjustments_d0; +wire grp_td_fused_fu_1094_tdf4_adjustments_we0; +wire [6:0] grp_td_fused_fu_1094_tdf4_adjustments_address1; +wire grp_td_fused_fu_1094_tdf4_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf4_adjustments_d1; +wire grp_td_fused_fu_1094_tdf4_adjustments_we1; +wire [3:0] grp_td_fused_fu_1094_tdf4_l2_adjustments_address0; +wire grp_td_fused_fu_1094_tdf4_l2_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf4_l2_adjustments_d0; +wire grp_td_fused_fu_1094_tdf4_l2_adjustments_we0; +wire [3:0] grp_td_fused_fu_1094_tdf4_l2_adjustments_address1; +wire grp_td_fused_fu_1094_tdf4_l2_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf4_l2_adjustments_d1; +wire grp_td_fused_fu_1094_tdf4_l2_adjustments_we1; +wire [6:0] grp_td_fused_fu_1094_tdf5_adjustments_address0; +wire grp_td_fused_fu_1094_tdf5_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf5_adjustments_d0; +wire grp_td_fused_fu_1094_tdf5_adjustments_we0; +wire [6:0] grp_td_fused_fu_1094_tdf5_adjustments_address1; +wire grp_td_fused_fu_1094_tdf5_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf5_adjustments_d1; +wire grp_td_fused_fu_1094_tdf5_adjustments_we1; +wire [4:0] grp_td_fused_fu_1094_tdf6_adjustments_address0; +wire grp_td_fused_fu_1094_tdf6_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf6_adjustments_d0; +wire grp_td_fused_fu_1094_tdf6_adjustments_we0; +wire [4:0] grp_td_fused_fu_1094_tdf6_adjustments_address1; +wire grp_td_fused_fu_1094_tdf6_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf6_adjustments_d1; +wire grp_td_fused_fu_1094_tdf6_adjustments_we1; +wire [7:0] grp_td_fused_fu_1094_tdf7_adjustments_address0; +wire grp_td_fused_fu_1094_tdf7_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf7_adjustments_d0; +wire grp_td_fused_fu_1094_tdf7_adjustments_we0; +wire [7:0] grp_td_fused_fu_1094_tdf7_adjustments_address1; +wire grp_td_fused_fu_1094_tdf7_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf7_adjustments_d1; +wire grp_td_fused_fu_1094_tdf7_adjustments_we1; +wire [4:0] grp_td_fused_fu_1094_tdf7_l2_adjustments_address0; +wire grp_td_fused_fu_1094_tdf7_l2_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf7_l2_adjustments_d0; +wire grp_td_fused_fu_1094_tdf7_l2_adjustments_we0; +wire [4:0] grp_td_fused_fu_1094_tdf7_l2_adjustments_address1; +wire grp_td_fused_fu_1094_tdf7_l2_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf7_l2_adjustments_d1; +wire grp_td_fused_fu_1094_tdf7_l2_adjustments_we1; +wire [7:0] grp_td_fused_fu_1094_tdf8_adjustments_address0; +wire grp_td_fused_fu_1094_tdf8_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf8_adjustments_d0; +wire grp_td_fused_fu_1094_tdf8_adjustments_we0; +wire [7:0] grp_td_fused_fu_1094_tdf8_adjustments_address1; +wire grp_td_fused_fu_1094_tdf8_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf8_adjustments_d1; +wire grp_td_fused_fu_1094_tdf8_adjustments_we1; +wire [5:0] grp_td_fused_fu_1094_tdf9_adjustments_address0; +wire grp_td_fused_fu_1094_tdf9_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf9_adjustments_d0; +wire grp_td_fused_fu_1094_tdf9_adjustments_we0; +wire [5:0] grp_td_fused_fu_1094_tdf9_adjustments_address1; +wire grp_td_fused_fu_1094_tdf9_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf9_adjustments_d1; +wire grp_td_fused_fu_1094_tdf9_adjustments_we1; +wire [8:0] grp_td_fused_fu_1094_tdf10_adjustments_address0; +wire grp_td_fused_fu_1094_tdf10_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf10_adjustments_d0; +wire grp_td_fused_fu_1094_tdf10_adjustments_we0; +wire [8:0] grp_td_fused_fu_1094_tdf10_adjustments_address1; +wire grp_td_fused_fu_1094_tdf10_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf10_adjustments_d1; +wire grp_td_fused_fu_1094_tdf10_adjustments_we1; +wire [5:0] grp_td_fused_fu_1094_tdf10_l2_adjustments_address0; +wire grp_td_fused_fu_1094_tdf10_l2_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf10_l2_adjustments_d0; +wire grp_td_fused_fu_1094_tdf10_l2_adjustments_we0; +wire [5:0] grp_td_fused_fu_1094_tdf10_l2_adjustments_address1; +wire grp_td_fused_fu_1094_tdf10_l2_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf10_l2_adjustments_d1; +wire grp_td_fused_fu_1094_tdf10_l2_adjustments_we1; +wire [8:0] grp_td_fused_fu_1094_tdf11_adjustments_address0; +wire grp_td_fused_fu_1094_tdf11_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf11_adjustments_d0; +wire grp_td_fused_fu_1094_tdf11_adjustments_we0; +wire [8:0] grp_td_fused_fu_1094_tdf11_adjustments_address1; +wire grp_td_fused_fu_1094_tdf11_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf11_adjustments_d1; +wire grp_td_fused_fu_1094_tdf11_adjustments_we1; +wire [6:0] grp_td_fused_fu_1094_tdf11_l2_adjustments_address0; +wire grp_td_fused_fu_1094_tdf11_l2_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf11_l2_adjustments_d0; +wire grp_td_fused_fu_1094_tdf11_l2_adjustments_we0; +wire [6:0] grp_td_fused_fu_1094_tdf11_l2_adjustments_address1; +wire grp_td_fused_fu_1094_tdf11_l2_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf11_l2_adjustments_d1; +wire grp_td_fused_fu_1094_tdf11_l2_adjustments_we1; +wire [9:0] grp_td_fused_fu_1094_tdf12_adjustments_address0; +wire grp_td_fused_fu_1094_tdf12_adjustments_ce0; +wire [47:0] grp_td_fused_fu_1094_tdf12_adjustments_d0; +wire grp_td_fused_fu_1094_tdf12_adjustments_we0; +wire [9:0] grp_td_fused_fu_1094_tdf12_adjustments_address1; +wire grp_td_fused_fu_1094_tdf12_adjustments_ce1; +wire [47:0] grp_td_fused_fu_1094_tdf12_adjustments_d1; +wire grp_td_fused_fu_1094_tdf12_adjustments_we1; +wire [15:0] grp_td_fused_fu_1094_stream_out_TDATA; +wire [1:0] grp_td_fused_fu_1094_stream_out_TKEEP; +wire [1:0] grp_td_fused_fu_1094_stream_out_TSTRB; +wire [0:0] grp_td_fused_fu_1094_stream_out_TLAST; +wire grp_td_fused_fu_1094_stream_in_TREADY; +wire grp_td_fused_fu_1094_ap_start; +wire grp_td_fused_fu_1094_stream_out_TVALID; +wire grp_td_fused_fu_1094_stream_out_TREADY; +wire grp_td_fused_fu_1094_ap_done; +wire grp_td_fused_fu_1094_ap_ready; +wire grp_td_fused_fu_1094_ap_idle; +reg grp_td_fused_fu_1094_ap_continue; +reg grp_td_fused_fu_1094_ap_start_reg; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire ap_sync_grp_td_fused_fu_1094_ap_ready; +wire ap_sync_grp_td_fused_fu_1094_ap_done; +reg ap_block_state3_on_subcall_done; +reg ap_sync_reg_grp_td_fused_fu_1094_ap_ready; +reg ap_sync_reg_grp_td_fused_fu_1094_ap_done; +wire [15:0] tmp_data_fu_1373_p1; +wire [31:0] tmp_fu_1385_p5; +wire [63:0] tmp_s_fu_1401_p5; +wire [47:0] trunc_ln143_fu_1417_p1; +wire ap_CS_fsm_state4; +wire regslice_both_stream_out_V_data_V_U_apdone_blk; +reg [3:0] ap_NS_fsm; +wire regslice_both_stream_in_V_data_V_U_apdone_blk; +wire [15:0] stream_in_TDATA_int_regslice; +wire stream_in_TVALID_int_regslice; +reg stream_in_TREADY_int_regslice; +wire regslice_both_stream_in_V_data_V_U_ack_in; +wire regslice_both_stream_in_V_keep_V_U_apdone_blk; +wire [1:0] stream_in_TKEEP_int_regslice; +wire regslice_both_stream_in_V_keep_V_U_vld_out; +wire regslice_both_stream_in_V_keep_V_U_ack_in; +wire regslice_both_stream_in_V_strb_V_U_apdone_blk; +wire [1:0] stream_in_TSTRB_int_regslice; +wire regslice_both_stream_in_V_strb_V_U_vld_out; +wire regslice_both_stream_in_V_strb_V_U_ack_in; +wire regslice_both_stream_in_V_last_V_U_apdone_blk; +wire [0:0] stream_in_TLAST_int_regslice; +wire regslice_both_stream_in_V_last_V_U_vld_out; +wire regslice_both_stream_in_V_last_V_U_ack_in; +wire stream_out_TREADY_int_regslice; +wire regslice_both_stream_out_V_data_V_U_vld_out; +wire regslice_both_stream_out_V_keep_V_U_apdone_blk; +wire regslice_both_stream_out_V_keep_V_U_ack_in_dummy; +wire regslice_both_stream_out_V_keep_V_U_vld_out; +wire regslice_both_stream_out_V_strb_V_U_apdone_blk; +wire regslice_both_stream_out_V_strb_V_U_ack_in_dummy; +wire regslice_both_stream_out_V_strb_V_U_vld_out; +wire regslice_both_stream_out_V_last_V_U_apdone_blk; +wire regslice_both_stream_out_V_last_V_U_ack_in_dummy; +wire regslice_both_stream_out_V_last_V_U_vld_out; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 4'd1; +#0 grp_td_fused_fu_1094_ap_start_reg = 1'b0; +#0 ap_sync_reg_grp_td_fused_fu_1094_ap_ready = 1'b0; +#0 ap_sync_reg_grp_td_fused_fu_1094_ap_done = 1'b0; +end + +td_fused_top_tdf1_filters_0 #( + .DataWidth( 16 ), + .AddressRange( 108 ), + .AddressWidth( 7 )) +tdf1_filters_0_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf1_filters_0_address0), + .ce0(tdf1_filters_0_ce0), + .q0(tdf1_filters_0_q0), + .address1(tdf1_filters_0_address1), + .ce1(tdf1_filters_0_ce1), + .we1(tdf1_filters_0_we1), + .d1(tmp_data_fu_1373_p1) +); + +td_fused_top_tdf1_filters_1 #( + .DataWidth( 16 ), + .AddressRange( 108 ), + .AddressWidth( 7 )) +tdf1_filters_1_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf1_filters_1_address0), + .ce0(grp_td_fused_fu_1094_tdf1_filters_1_ce0), + .q0(tdf1_filters_1_q0) +); + +td_fused_top_tdf1_filters_1 #( + .DataWidth( 16 ), + .AddressRange( 108 ), + .AddressWidth( 7 )) +tdf1_filters_2_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf1_filters_2_address0), + .ce0(grp_td_fused_fu_1094_tdf1_filters_2_ce0), + .q0(tdf1_filters_2_q0) +); + +td_fused_top_tdf1_filters_1 #( + .DataWidth( 16 ), + .AddressRange( 108 ), + .AddressWidth( 7 )) +tdf1_filters_3_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf1_filters_3_address0), + .ce0(grp_td_fused_fu_1094_tdf1_filters_3_ce0), + .q0(tdf1_filters_3_q0) +); + +td_fused_top_tdf2_filters_0 #( + .DataWidth( 32 ), + .AddressRange( 576 ), + .AddressWidth( 10 )) +tdf2_filters_0_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf2_filters_0_address0), + .ce0(tdf2_filters_0_ce0), + .q0(tdf2_filters_0_q0), + .address1(tdf2_filters_0_address1), + .ce1(tdf2_filters_0_ce1), + .we1(tdf2_filters_0_we1), + .d1(tmp_fu_1385_p5) +); + +td_fused_top_tdf2_filters_1 #( + .DataWidth( 32 ), + .AddressRange( 576 ), + .AddressWidth( 10 )) +tdf2_filters_1_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf2_filters_1_address0), + .ce0(grp_td_fused_fu_1094_tdf2_filters_1_ce0), + .q0(tdf2_filters_1_q0) +); + +td_fused_top_tdf2_filters_1 #( + .DataWidth( 32 ), + .AddressRange( 576 ), + .AddressWidth( 10 )) +tdf2_filters_2_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf2_filters_2_address0), + .ce0(grp_td_fused_fu_1094_tdf2_filters_2_ce0), + .q0(tdf2_filters_2_q0) +); + +td_fused_top_tdf2_filters_1 #( + .DataWidth( 32 ), + .AddressRange( 576 ), + .AddressWidth( 10 )) +tdf2_filters_3_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf2_filters_3_address0), + .ce0(grp_td_fused_fu_1094_tdf2_filters_3_ce0), + .q0(tdf2_filters_3_q0) +); + +td_fused_top_tdf3_filters #( + .DataWidth( 16 ), + .AddressRange( 512 ), + .AddressWidth( 9 )) +tdf3_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf3_filters_address0), + .ce0(tdf3_filters_ce0), + .q0(tdf3_filters_q0), + .address1(tdf3_filters_address1), + .ce1(tdf3_filters_ce1), + .we1(tdf3_filters_we1), + .d1(tmp_data_fu_1373_p1) +); + +td_fused_top_tdf4_filters_0 #( + .DataWidth( 64 ), + .AddressRange( 1152 ), + .AddressWidth( 11 )) +tdf4_filters_0_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf4_filters_0_address0), + .ce0(tdf4_filters_0_ce0), + .q0(tdf4_filters_0_q0), + .address1(tdf4_filters_0_address1), + .ce1(tdf4_filters_0_ce1), + .we1(tdf4_filters_0_we1), + .d1(tmp_s_fu_1401_p5) +); + +td_fused_top_tdf4_filters_1 #( + .DataWidth( 64 ), + .AddressRange( 1152 ), + .AddressWidth( 11 )) +tdf4_filters_1_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf4_filters_1_address0), + .ce0(grp_td_fused_fu_1094_tdf4_filters_1_ce0), + .q0(tdf4_filters_1_q0) +); + +td_fused_top_tdf4_filters_1 #( + .DataWidth( 64 ), + .AddressRange( 1152 ), + .AddressWidth( 11 )) +tdf4_filters_2_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf4_filters_2_address0), + .ce0(grp_td_fused_fu_1094_tdf4_filters_2_ce0), + .q0(tdf4_filters_2_q0) +); + +td_fused_top_tdf4_filters_1 #( + .DataWidth( 64 ), + .AddressRange( 1152 ), + .AddressWidth( 11 )) +tdf4_filters_3_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf4_filters_3_address0), + .ce0(grp_td_fused_fu_1094_tdf4_filters_3_ce0), + .q0(tdf4_filters_3_q0) +); + +td_fused_top_tdf4_l2_filters_0 #( + .DataWidth( 16 ), + .AddressRange( 1024 ), + .AddressWidth( 10 )) +tdf4_l2_filters_0_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf4_l2_filters_0_address0), + .ce0(tdf4_l2_filters_0_ce0), + .q0(tdf4_l2_filters_0_q0), + .address1(tdf4_l2_filters_0_address1), + .ce1(tdf4_l2_filters_0_ce1), + .we1(tdf4_l2_filters_0_we1), + .d1(tmp_data_fu_1373_p1), + .q1(tdf4_l2_filters_0_q1) +); + +td_fused_top_tdf4_l2_filters_1 #( + .DataWidth( 16 ), + .AddressRange( 1024 ), + .AddressWidth( 10 )) +tdf4_l2_filters_1_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf4_l2_filters_1_address0), + .ce0(grp_td_fused_fu_1094_tdf4_l2_filters_1_ce0), + .q0(tdf4_l2_filters_1_q0), + .address1(grp_td_fused_fu_1094_tdf4_l2_filters_1_address1), + .ce1(grp_td_fused_fu_1094_tdf4_l2_filters_1_ce1), + .q1(tdf4_l2_filters_1_q1) +); + +td_fused_top_tdf5_filters_0 #( + .DataWidth( 32 ), + .AddressRange( 2304 ), + .AddressWidth( 12 )) +tdf5_filters_0_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf5_filters_0_address0), + .ce0(tdf5_filters_0_ce0), + .q0(tdf5_filters_0_q0), + .address1(tdf5_filters_0_address1), + .ce1(tdf5_filters_0_ce1), + .we1(tdf5_filters_0_we1), + .d1(tmp_fu_1385_p5) +); + +td_fused_top_tdf5_filters_1 #( + .DataWidth( 32 ), + .AddressRange( 2304 ), + .AddressWidth( 12 )) +tdf5_filters_1_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf5_filters_1_address0), + .ce0(grp_td_fused_fu_1094_tdf5_filters_1_ce0), + .q0(tdf5_filters_1_q0) +); + +td_fused_top_tdf5_filters_1 #( + .DataWidth( 32 ), + .AddressRange( 2304 ), + .AddressWidth( 12 )) +tdf5_filters_2_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf5_filters_2_address0), + .ce0(grp_td_fused_fu_1094_tdf5_filters_2_ce0), + .q0(tdf5_filters_2_q0) +); + +td_fused_top_tdf5_filters_1 #( + .DataWidth( 32 ), + .AddressRange( 2304 ), + .AddressWidth( 12 )) +tdf5_filters_3_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf5_filters_3_address0), + .ce0(grp_td_fused_fu_1094_tdf5_filters_3_ce0), + .q0(tdf5_filters_3_q0) +); + +td_fused_top_tdf6_filters #( + .DataWidth( 16 ), + .AddressRange( 4096 ), + .AddressWidth( 12 )) +tdf6_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf6_filters_address0), + .ce0(tdf6_filters_ce0), + .q0(tdf6_filters_q0), + .address1(tdf6_filters_address1), + .ce1(tdf6_filters_ce1), + .we1(tdf6_filters_we1), + .d1(tmp_data_fu_1373_p1) +); + +td_fused_top_tdf7_filters_0 #( + .DataWidth( 64 ), + .AddressRange( 4608 ), + .AddressWidth( 13 )) +tdf7_filters_0_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf7_filters_0_address0), + .ce0(tdf7_filters_0_ce0), + .q0(tdf7_filters_0_q0), + .address1(tdf7_filters_0_address1), + .ce1(tdf7_filters_0_ce1), + .we1(tdf7_filters_0_we1), + .d1(tmp_s_fu_1401_p5) +); + +td_fused_top_tdf7_filters_1 #( + .DataWidth( 64 ), + .AddressRange( 4608 ), + .AddressWidth( 13 )) +tdf7_filters_1_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf7_filters_1_address0), + .ce0(grp_td_fused_fu_1094_tdf7_filters_1_ce0), + .q0(tdf7_filters_1_q0) +); + +td_fused_top_tdf7_filters_1 #( + .DataWidth( 64 ), + .AddressRange( 4608 ), + .AddressWidth( 13 )) +tdf7_filters_2_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf7_filters_2_address0), + .ce0(grp_td_fused_fu_1094_tdf7_filters_2_ce0), + .q0(tdf7_filters_2_q0) +); + +td_fused_top_tdf7_filters_1 #( + .DataWidth( 64 ), + .AddressRange( 4608 ), + .AddressWidth( 13 )) +tdf7_filters_3_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf7_filters_3_address0), + .ce0(grp_td_fused_fu_1094_tdf7_filters_3_ce0), + .q0(tdf7_filters_3_q0) +); + +td_fused_top_tdf7_l2_filters_0 #( + .DataWidth( 16 ), + .AddressRange( 4096 ), + .AddressWidth( 12 )) +tdf7_l2_filters_0_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf7_l2_filters_0_address0), + .ce0(tdf7_l2_filters_0_ce0), + .q0(tdf7_l2_filters_0_q0), + .address1(tdf7_l2_filters_0_address1), + .ce1(tdf7_l2_filters_0_ce1), + .we1(tdf7_l2_filters_0_we1), + .d1(tmp_data_fu_1373_p1), + .q1(tdf7_l2_filters_0_q1) +); + +td_fused_top_tdf7_l2_filters_1 #( + .DataWidth( 16 ), + .AddressRange( 4096 ), + .AddressWidth( 12 )) +tdf7_l2_filters_1_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf7_l2_filters_1_address0), + .ce0(grp_td_fused_fu_1094_tdf7_l2_filters_1_ce0), + .q0(tdf7_l2_filters_1_q0), + .address1(grp_td_fused_fu_1094_tdf7_l2_filters_1_address1), + .ce1(grp_td_fused_fu_1094_tdf7_l2_filters_1_ce1), + .q1(tdf7_l2_filters_1_q1) +); + +td_fused_top_tdf8_filters_0 #( + .DataWidth( 32 ), + .AddressRange( 9216 ), + .AddressWidth( 14 )) +tdf8_filters_0_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf8_filters_0_address0), + .ce0(tdf8_filters_0_ce0), + .q0(tdf8_filters_0_q0), + .address1(tdf8_filters_0_address1), + .ce1(tdf8_filters_0_ce1), + .we1(tdf8_filters_0_we1), + .d1(tmp_fu_1385_p5) +); + +td_fused_top_tdf8_filters_1 #( + .DataWidth( 32 ), + .AddressRange( 9216 ), + .AddressWidth( 14 )) +tdf8_filters_1_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf8_filters_1_address0), + .ce0(grp_td_fused_fu_1094_tdf8_filters_1_ce0), + .q0(tdf8_filters_1_q0) +); + +td_fused_top_tdf8_filters_1 #( + .DataWidth( 32 ), + .AddressRange( 9216 ), + .AddressWidth( 14 )) +tdf8_filters_2_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf8_filters_2_address0), + .ce0(grp_td_fused_fu_1094_tdf8_filters_2_ce0), + .q0(tdf8_filters_2_q0) +); + +td_fused_top_tdf8_filters_1 #( + .DataWidth( 32 ), + .AddressRange( 9216 ), + .AddressWidth( 14 )) +tdf8_filters_3_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf8_filters_3_address0), + .ce0(grp_td_fused_fu_1094_tdf8_filters_3_ce0), + .q0(tdf8_filters_3_q0) +); + +td_fused_top_tdf9_filters #( + .DataWidth( 16 ), + .AddressRange( 16384 ), + .AddressWidth( 14 )) +tdf9_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf9_filters_address0), + .ce0(tdf9_filters_ce0), + .q0(tdf9_filters_q0), + .address1(tdf9_filters_address1), + .ce1(tdf9_filters_ce1), + .we1(tdf9_filters_we1), + .d1(tmp_data_fu_1373_p1) +); + +td_fused_top_tdf10_filters_0 #( + .DataWidth( 64 ), + .AddressRange( 18432 ), + .AddressWidth( 15 )) +tdf10_filters_0_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf10_filters_0_address0), + .ce0(tdf10_filters_0_ce0), + .q0(tdf10_filters_0_q0), + .address1(tdf10_filters_0_address1), + .ce1(tdf10_filters_0_ce1), + .we1(tdf10_filters_0_we1), + .d1(tmp_s_fu_1401_p5) +); + +td_fused_top_tdf10_filters_1 #( + .DataWidth( 64 ), + .AddressRange( 18432 ), + .AddressWidth( 15 )) +tdf10_filters_1_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf10_filters_1_address0), + .ce0(grp_td_fused_fu_1094_tdf10_filters_1_ce0), + .q0(tdf10_filters_1_q0) +); + +td_fused_top_tdf10_filters_1 #( + .DataWidth( 64 ), + .AddressRange( 18432 ), + .AddressWidth( 15 )) +tdf10_filters_2_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf10_filters_2_address0), + .ce0(grp_td_fused_fu_1094_tdf10_filters_2_ce0), + .q0(tdf10_filters_2_q0) +); + +td_fused_top_tdf10_filters_1 #( + .DataWidth( 64 ), + .AddressRange( 18432 ), + .AddressWidth( 15 )) +tdf10_filters_3_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf10_filters_3_address0), + .ce0(grp_td_fused_fu_1094_tdf10_filters_3_ce0), + .q0(tdf10_filters_3_q0) +); + +td_fused_top_tdf10_l2_filters_0 #( + .DataWidth( 16 ), + .AddressRange( 16384 ), + .AddressWidth( 14 )) +tdf10_l2_filters_0_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf10_l2_filters_0_address0), + .ce0(tdf10_l2_filters_0_ce0), + .q0(tdf10_l2_filters_0_q0), + .address1(tdf10_l2_filters_0_address1), + .ce1(tdf10_l2_filters_0_ce1), + .we1(tdf10_l2_filters_0_we1), + .d1(tmp_data_fu_1373_p1), + .q1(tdf10_l2_filters_0_q1) +); + +td_fused_top_tdf10_l2_filters_1 #( + .DataWidth( 16 ), + .AddressRange( 16384 ), + .AddressWidth( 14 )) +tdf10_l2_filters_1_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf10_l2_filters_1_address0), + .ce0(grp_td_fused_fu_1094_tdf10_l2_filters_1_ce0), + .q0(tdf10_l2_filters_1_q0), + .address1(grp_td_fused_fu_1094_tdf10_l2_filters_1_address1), + .ce1(grp_td_fused_fu_1094_tdf10_l2_filters_1_ce1), + .q1(tdf10_l2_filters_1_q1) +); + +td_fused_top_tdf10_filters_0 #( + .DataWidth( 64 ), + .AddressRange( 18432 ), + .AddressWidth( 15 )) +tdf11_filters_0_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf11_filters_0_address0), + .ce0(tdf11_filters_0_ce0), + .q0(tdf11_filters_0_q0), + .address1(tdf11_filters_0_address1), + .ce1(tdf11_filters_0_ce1), + .we1(tdf11_filters_0_we1), + .d1(tmp_s_fu_1401_p5) +); + +td_fused_top_tdf10_filters_1 #( + .DataWidth( 64 ), + .AddressRange( 18432 ), + .AddressWidth( 15 )) +tdf11_filters_1_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf11_filters_1_address0), + .ce0(grp_td_fused_fu_1094_tdf11_filters_1_ce0), + .q0(tdf11_filters_1_q0) +); + +td_fused_top_tdf10_filters_1 #( + .DataWidth( 64 ), + .AddressRange( 18432 ), + .AddressWidth( 15 )) +tdf11_filters_2_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf11_filters_2_address0), + .ce0(grp_td_fused_fu_1094_tdf11_filters_2_ce0), + .q0(tdf11_filters_2_q0) +); + +td_fused_top_tdf10_filters_1 #( + .DataWidth( 64 ), + .AddressRange( 18432 ), + .AddressWidth( 15 )) +tdf11_filters_3_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf11_filters_3_address0), + .ce0(grp_td_fused_fu_1094_tdf11_filters_3_ce0), + .q0(tdf11_filters_3_q0) +); + +td_fused_top_tdf10_l2_filters_0 #( + .DataWidth( 16 ), + .AddressRange( 16384 ), + .AddressWidth( 14 )) +tdf11_l2_filters_0_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf11_l2_filters_0_address0), + .ce0(tdf11_l2_filters_0_ce0), + .q0(tdf11_l2_filters_0_q0), + .address1(tdf11_l2_filters_0_address1), + .ce1(tdf11_l2_filters_0_ce1), + .we1(tdf11_l2_filters_0_we1), + .d1(tmp_data_fu_1373_p1), + .q1(tdf11_l2_filters_0_q1) +); + +td_fused_top_tdf10_l2_filters_1 #( + .DataWidth( 16 ), + .AddressRange( 16384 ), + .AddressWidth( 14 )) +tdf11_l2_filters_1_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf11_l2_filters_1_address0), + .ce0(grp_td_fused_fu_1094_tdf11_l2_filters_1_ce0), + .q0(tdf11_l2_filters_1_q0), + .address1(grp_td_fused_fu_1094_tdf11_l2_filters_1_address1), + .ce1(grp_td_fused_fu_1094_tdf11_l2_filters_1_ce1), + .q1(tdf11_l2_filters_1_q1) +); + +td_fused_top_tdf10_l2_filters_1 #( + .DataWidth( 16 ), + .AddressRange( 16384 ), + .AddressWidth( 14 )) +tdf11_l2_filters_2_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf11_l2_filters_2_address0), + .ce0(grp_td_fused_fu_1094_tdf11_l2_filters_2_ce0), + .q0(tdf11_l2_filters_2_q0), + .address1(grp_td_fused_fu_1094_tdf11_l2_filters_2_address1), + .ce1(grp_td_fused_fu_1094_tdf11_l2_filters_2_ce1), + .q1(tdf11_l2_filters_2_q1) +); + +td_fused_top_tdf10_l2_filters_1 #( + .DataWidth( 16 ), + .AddressRange( 16384 ), + .AddressWidth( 14 )) +tdf11_l2_filters_3_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf11_l2_filters_3_address0), + .ce0(grp_td_fused_fu_1094_tdf11_l2_filters_3_ce0), + .q0(tdf11_l2_filters_3_q0), + .address1(grp_td_fused_fu_1094_tdf11_l2_filters_3_address1), + .ce1(grp_td_fused_fu_1094_tdf11_l2_filters_3_ce1), + .q1(tdf11_l2_filters_3_q1) +); + +td_fused_top_tdf12_filters_0 #( + .DataWidth( 32 ), + .AddressRange( 32000 ), + .AddressWidth( 15 )) +tdf12_filters_0_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf12_filters_0_address0), + .ce0(tdf12_filters_0_ce0), + .q0(tdf12_filters_0_q0), + .address1(tdf12_filters_0_address1), + .ce1(tdf12_filters_0_ce1), + .we1(tdf12_filters_0_we1), + .d1(tmp_fu_1385_p5) +); + +td_fused_top_tdf12_filters_1 #( + .DataWidth( 32 ), + .AddressRange( 32000 ), + .AddressWidth( 15 )) +tdf12_filters_1_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf12_filters_1_address0), + .ce0(grp_td_fused_fu_1094_tdf12_filters_1_ce0), + .q0(tdf12_filters_1_q0) +); + +td_fused_top_tdf1_adjustments #( + .DataWidth( 48 ), + .AddressRange( 16 ), + .AddressWidth( 4 )) +tdf1_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf1_adjustments_address0), + .ce0(tdf1_adjustments_ce0), + .q0(tdf1_adjustments_q0), + .address1(tdf1_adjustments_address1), + .ce1(tdf1_adjustments_ce1), + .we1(tdf1_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_tdf2_adjustments #( + .DataWidth( 48 ), + .AddressRange( 32 ), + .AddressWidth( 5 )) +tdf2_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf2_adjustments_address0), + .ce0(tdf2_adjustments_ce0), + .q0(tdf2_adjustments_q0), + .address1(tdf2_adjustments_address1), + .ce1(tdf2_adjustments_ce1), + .we1(tdf2_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_tdf1_adjustments #( + .DataWidth( 48 ), + .AddressRange( 16 ), + .AddressWidth( 4 )) +tdf3_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf3_adjustments_address0), + .ce0(tdf3_adjustments_ce0), + .q0(tdf3_adjustments_q0), + .address1(tdf3_adjustments_address1), + .ce1(tdf3_adjustments_ce1), + .we1(tdf3_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_tdf4_adjustments #( + .DataWidth( 48 ), + .AddressRange( 128 ), + .AddressWidth( 7 )) +tdf4_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf4_adjustments_address0), + .ce0(tdf4_adjustments_ce0), + .q0(tdf4_adjustments_q0), + .address1(tdf4_adjustments_address1), + .ce1(tdf4_adjustments_ce1), + .we1(tdf4_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_tdf1_adjustments #( + .DataWidth( 48 ), + .AddressRange( 16 ), + .AddressWidth( 4 )) +tdf4_l2_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf4_l2_adjustments_address0), + .ce0(tdf4_l2_adjustments_ce0), + .q0(tdf4_l2_adjustments_q0), + .address1(tdf4_l2_adjustments_address1), + .ce1(tdf4_l2_adjustments_ce1), + .we1(tdf4_l2_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_tdf4_adjustments #( + .DataWidth( 48 ), + .AddressRange( 128 ), + .AddressWidth( 7 )) +tdf5_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf5_adjustments_address0), + .ce0(tdf5_adjustments_ce0), + .q0(tdf5_adjustments_q0), + .address1(tdf5_adjustments_address1), + .ce1(tdf5_adjustments_ce1), + .we1(tdf5_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_tdf2_adjustments #( + .DataWidth( 48 ), + .AddressRange( 32 ), + .AddressWidth( 5 )) +tdf6_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf6_adjustments_address0), + .ce0(tdf6_adjustments_ce0), + .q0(tdf6_adjustments_q0), + .address1(tdf6_adjustments_address1), + .ce1(tdf6_adjustments_ce1), + .we1(tdf6_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_tdf7_adjustments #( + .DataWidth( 48 ), + .AddressRange( 256 ), + .AddressWidth( 8 )) +tdf7_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf7_adjustments_address0), + .ce0(tdf7_adjustments_ce0), + .q0(tdf7_adjustments_q0), + .address1(tdf7_adjustments_address1), + .ce1(tdf7_adjustments_ce1), + .we1(tdf7_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_tdf2_adjustments #( + .DataWidth( 48 ), + .AddressRange( 32 ), + .AddressWidth( 5 )) +tdf7_l2_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf7_l2_adjustments_address0), + .ce0(tdf7_l2_adjustments_ce0), + .q0(tdf7_l2_adjustments_q0), + .address1(tdf7_l2_adjustments_address1), + .ce1(tdf7_l2_adjustments_ce1), + .we1(tdf7_l2_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_tdf7_adjustments #( + .DataWidth( 48 ), + .AddressRange( 256 ), + .AddressWidth( 8 )) +tdf8_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf8_adjustments_address0), + .ce0(tdf8_adjustments_ce0), + .q0(tdf8_adjustments_q0), + .address1(tdf8_adjustments_address1), + .ce1(tdf8_adjustments_ce1), + .we1(tdf8_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_tdf9_adjustments #( + .DataWidth( 48 ), + .AddressRange( 64 ), + .AddressWidth( 6 )) +tdf9_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf9_adjustments_address0), + .ce0(tdf9_adjustments_ce0), + .q0(tdf9_adjustments_q0), + .address1(tdf9_adjustments_address1), + .ce1(tdf9_adjustments_ce1), + .we1(tdf9_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_tdf10_adjustments #( + .DataWidth( 48 ), + .AddressRange( 512 ), + .AddressWidth( 9 )) +tdf10_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf10_adjustments_address0), + .ce0(tdf10_adjustments_ce0), + .q0(tdf10_adjustments_q0), + .address1(tdf10_adjustments_address1), + .ce1(tdf10_adjustments_ce1), + .we1(tdf10_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_tdf9_adjustments #( + .DataWidth( 48 ), + .AddressRange( 64 ), + .AddressWidth( 6 )) +tdf10_l2_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf10_l2_adjustments_address0), + .ce0(tdf10_l2_adjustments_ce0), + .q0(tdf10_l2_adjustments_q0), + .address1(tdf10_l2_adjustments_address1), + .ce1(tdf10_l2_adjustments_ce1), + .we1(tdf10_l2_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_tdf10_adjustments #( + .DataWidth( 48 ), + .AddressRange( 512 ), + .AddressWidth( 9 )) +tdf11_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf11_adjustments_address0), + .ce0(tdf11_adjustments_ce0), + .q0(tdf11_adjustments_q0), + .address1(tdf11_adjustments_address1), + .ce1(tdf11_adjustments_ce1), + .we1(tdf11_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_tdf4_adjustments #( + .DataWidth( 48 ), + .AddressRange( 128 ), + .AddressWidth( 7 )) +tdf11_l2_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf11_l2_adjustments_address0), + .ce0(tdf11_l2_adjustments_ce0), + .q0(tdf11_l2_adjustments_q0), + .address1(tdf11_l2_adjustments_address1), + .ce1(tdf11_l2_adjustments_ce1), + .we1(tdf11_l2_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_tdf12_adjustments #( + .DataWidth( 48 ), + .AddressRange( 1000 ), + .AddressWidth( 10 )) +tdf12_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_1094_tdf12_adjustments_address0), + .ce0(tdf12_adjustments_ce0), + .q0(tdf12_adjustments_q0), + .address1(tdf12_adjustments_address1), + .ce1(tdf12_adjustments_ce1), + .we1(tdf12_adjustments_we1), + .d1(trunc_ln143_fu_1417_p1) +); + +td_fused_top_td_fused grp_td_fused_fu_1094( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .tdf1_filters_0_address0(grp_td_fused_fu_1094_tdf1_filters_0_address0), + .tdf1_filters_0_ce0(grp_td_fused_fu_1094_tdf1_filters_0_ce0), + .tdf1_filters_0_d0(grp_td_fused_fu_1094_tdf1_filters_0_d0), + .tdf1_filters_0_q0(tdf1_filters_0_q0), + .tdf1_filters_0_we0(grp_td_fused_fu_1094_tdf1_filters_0_we0), + .tdf1_filters_0_address1(grp_td_fused_fu_1094_tdf1_filters_0_address1), + .tdf1_filters_0_ce1(grp_td_fused_fu_1094_tdf1_filters_0_ce1), + .tdf1_filters_0_d1(grp_td_fused_fu_1094_tdf1_filters_0_d1), + .tdf1_filters_0_q1(16'd0), + .tdf1_filters_0_we1(grp_td_fused_fu_1094_tdf1_filters_0_we1), + .tdf1_filters_1_address0(grp_td_fused_fu_1094_tdf1_filters_1_address0), + .tdf1_filters_1_ce0(grp_td_fused_fu_1094_tdf1_filters_1_ce0), + .tdf1_filters_1_d0(grp_td_fused_fu_1094_tdf1_filters_1_d0), + .tdf1_filters_1_q0(tdf1_filters_1_q0), + .tdf1_filters_1_we0(grp_td_fused_fu_1094_tdf1_filters_1_we0), + .tdf1_filters_1_address1(grp_td_fused_fu_1094_tdf1_filters_1_address1), + .tdf1_filters_1_ce1(grp_td_fused_fu_1094_tdf1_filters_1_ce1), + .tdf1_filters_1_d1(grp_td_fused_fu_1094_tdf1_filters_1_d1), + .tdf1_filters_1_q1(16'd0), + .tdf1_filters_1_we1(grp_td_fused_fu_1094_tdf1_filters_1_we1), + .tdf1_filters_2_address0(grp_td_fused_fu_1094_tdf1_filters_2_address0), + .tdf1_filters_2_ce0(grp_td_fused_fu_1094_tdf1_filters_2_ce0), + .tdf1_filters_2_d0(grp_td_fused_fu_1094_tdf1_filters_2_d0), + .tdf1_filters_2_q0(tdf1_filters_2_q0), + .tdf1_filters_2_we0(grp_td_fused_fu_1094_tdf1_filters_2_we0), + .tdf1_filters_2_address1(grp_td_fused_fu_1094_tdf1_filters_2_address1), + .tdf1_filters_2_ce1(grp_td_fused_fu_1094_tdf1_filters_2_ce1), + .tdf1_filters_2_d1(grp_td_fused_fu_1094_tdf1_filters_2_d1), + .tdf1_filters_2_q1(16'd0), + .tdf1_filters_2_we1(grp_td_fused_fu_1094_tdf1_filters_2_we1), + .tdf1_filters_3_address0(grp_td_fused_fu_1094_tdf1_filters_3_address0), + .tdf1_filters_3_ce0(grp_td_fused_fu_1094_tdf1_filters_3_ce0), + .tdf1_filters_3_d0(grp_td_fused_fu_1094_tdf1_filters_3_d0), + .tdf1_filters_3_q0(tdf1_filters_3_q0), + .tdf1_filters_3_we0(grp_td_fused_fu_1094_tdf1_filters_3_we0), + .tdf1_filters_3_address1(grp_td_fused_fu_1094_tdf1_filters_3_address1), + .tdf1_filters_3_ce1(grp_td_fused_fu_1094_tdf1_filters_3_ce1), + .tdf1_filters_3_d1(grp_td_fused_fu_1094_tdf1_filters_3_d1), + .tdf1_filters_3_q1(16'd0), + .tdf1_filters_3_we1(grp_td_fused_fu_1094_tdf1_filters_3_we1), + .tdf2_filters_0_address0(grp_td_fused_fu_1094_tdf2_filters_0_address0), + .tdf2_filters_0_ce0(grp_td_fused_fu_1094_tdf2_filters_0_ce0), + .tdf2_filters_0_d0(grp_td_fused_fu_1094_tdf2_filters_0_d0), + .tdf2_filters_0_q0(tdf2_filters_0_q0), + .tdf2_filters_0_we0(grp_td_fused_fu_1094_tdf2_filters_0_we0), + .tdf2_filters_0_address1(grp_td_fused_fu_1094_tdf2_filters_0_address1), + .tdf2_filters_0_ce1(grp_td_fused_fu_1094_tdf2_filters_0_ce1), + .tdf2_filters_0_d1(grp_td_fused_fu_1094_tdf2_filters_0_d1), + .tdf2_filters_0_q1(32'd0), + .tdf2_filters_0_we1(grp_td_fused_fu_1094_tdf2_filters_0_we1), + .tdf2_filters_1_address0(grp_td_fused_fu_1094_tdf2_filters_1_address0), + .tdf2_filters_1_ce0(grp_td_fused_fu_1094_tdf2_filters_1_ce0), + .tdf2_filters_1_d0(grp_td_fused_fu_1094_tdf2_filters_1_d0), + .tdf2_filters_1_q0(tdf2_filters_1_q0), + .tdf2_filters_1_we0(grp_td_fused_fu_1094_tdf2_filters_1_we0), + .tdf2_filters_1_address1(grp_td_fused_fu_1094_tdf2_filters_1_address1), + .tdf2_filters_1_ce1(grp_td_fused_fu_1094_tdf2_filters_1_ce1), + .tdf2_filters_1_d1(grp_td_fused_fu_1094_tdf2_filters_1_d1), + .tdf2_filters_1_q1(32'd0), + .tdf2_filters_1_we1(grp_td_fused_fu_1094_tdf2_filters_1_we1), + .tdf2_filters_2_address0(grp_td_fused_fu_1094_tdf2_filters_2_address0), + .tdf2_filters_2_ce0(grp_td_fused_fu_1094_tdf2_filters_2_ce0), + .tdf2_filters_2_d0(grp_td_fused_fu_1094_tdf2_filters_2_d0), + .tdf2_filters_2_q0(tdf2_filters_2_q0), + .tdf2_filters_2_we0(grp_td_fused_fu_1094_tdf2_filters_2_we0), + .tdf2_filters_2_address1(grp_td_fused_fu_1094_tdf2_filters_2_address1), + .tdf2_filters_2_ce1(grp_td_fused_fu_1094_tdf2_filters_2_ce1), + .tdf2_filters_2_d1(grp_td_fused_fu_1094_tdf2_filters_2_d1), + .tdf2_filters_2_q1(32'd0), + .tdf2_filters_2_we1(grp_td_fused_fu_1094_tdf2_filters_2_we1), + .tdf2_filters_3_address0(grp_td_fused_fu_1094_tdf2_filters_3_address0), + .tdf2_filters_3_ce0(grp_td_fused_fu_1094_tdf2_filters_3_ce0), + .tdf2_filters_3_d0(grp_td_fused_fu_1094_tdf2_filters_3_d0), + .tdf2_filters_3_q0(tdf2_filters_3_q0), + .tdf2_filters_3_we0(grp_td_fused_fu_1094_tdf2_filters_3_we0), + .tdf2_filters_3_address1(grp_td_fused_fu_1094_tdf2_filters_3_address1), + .tdf2_filters_3_ce1(grp_td_fused_fu_1094_tdf2_filters_3_ce1), + .tdf2_filters_3_d1(grp_td_fused_fu_1094_tdf2_filters_3_d1), + .tdf2_filters_3_q1(32'd0), + .tdf2_filters_3_we1(grp_td_fused_fu_1094_tdf2_filters_3_we1), + .tdf3_filters_address0(grp_td_fused_fu_1094_tdf3_filters_address0), + .tdf3_filters_ce0(grp_td_fused_fu_1094_tdf3_filters_ce0), + .tdf3_filters_d0(grp_td_fused_fu_1094_tdf3_filters_d0), + .tdf3_filters_q0(tdf3_filters_q0), + .tdf3_filters_we0(grp_td_fused_fu_1094_tdf3_filters_we0), + .tdf3_filters_address1(grp_td_fused_fu_1094_tdf3_filters_address1), + .tdf3_filters_ce1(grp_td_fused_fu_1094_tdf3_filters_ce1), + .tdf3_filters_d1(grp_td_fused_fu_1094_tdf3_filters_d1), + .tdf3_filters_q1(16'd0), + .tdf3_filters_we1(grp_td_fused_fu_1094_tdf3_filters_we1), + .tdf4_filters_0_address0(grp_td_fused_fu_1094_tdf4_filters_0_address0), + .tdf4_filters_0_ce0(grp_td_fused_fu_1094_tdf4_filters_0_ce0), + .tdf4_filters_0_d0(grp_td_fused_fu_1094_tdf4_filters_0_d0), + .tdf4_filters_0_q0(tdf4_filters_0_q0), + .tdf4_filters_0_we0(grp_td_fused_fu_1094_tdf4_filters_0_we0), + .tdf4_filters_0_address1(grp_td_fused_fu_1094_tdf4_filters_0_address1), + .tdf4_filters_0_ce1(grp_td_fused_fu_1094_tdf4_filters_0_ce1), + .tdf4_filters_0_d1(grp_td_fused_fu_1094_tdf4_filters_0_d1), + .tdf4_filters_0_q1(64'd0), + .tdf4_filters_0_we1(grp_td_fused_fu_1094_tdf4_filters_0_we1), + .tdf4_filters_1_address0(grp_td_fused_fu_1094_tdf4_filters_1_address0), + .tdf4_filters_1_ce0(grp_td_fused_fu_1094_tdf4_filters_1_ce0), + .tdf4_filters_1_d0(grp_td_fused_fu_1094_tdf4_filters_1_d0), + .tdf4_filters_1_q0(tdf4_filters_1_q0), + .tdf4_filters_1_we0(grp_td_fused_fu_1094_tdf4_filters_1_we0), + .tdf4_filters_1_address1(grp_td_fused_fu_1094_tdf4_filters_1_address1), + .tdf4_filters_1_ce1(grp_td_fused_fu_1094_tdf4_filters_1_ce1), + .tdf4_filters_1_d1(grp_td_fused_fu_1094_tdf4_filters_1_d1), + .tdf4_filters_1_q1(64'd0), + .tdf4_filters_1_we1(grp_td_fused_fu_1094_tdf4_filters_1_we1), + .tdf4_filters_2_address0(grp_td_fused_fu_1094_tdf4_filters_2_address0), + .tdf4_filters_2_ce0(grp_td_fused_fu_1094_tdf4_filters_2_ce0), + .tdf4_filters_2_d0(grp_td_fused_fu_1094_tdf4_filters_2_d0), + .tdf4_filters_2_q0(tdf4_filters_2_q0), + .tdf4_filters_2_we0(grp_td_fused_fu_1094_tdf4_filters_2_we0), + .tdf4_filters_2_address1(grp_td_fused_fu_1094_tdf4_filters_2_address1), + .tdf4_filters_2_ce1(grp_td_fused_fu_1094_tdf4_filters_2_ce1), + .tdf4_filters_2_d1(grp_td_fused_fu_1094_tdf4_filters_2_d1), + .tdf4_filters_2_q1(64'd0), + .tdf4_filters_2_we1(grp_td_fused_fu_1094_tdf4_filters_2_we1), + .tdf4_filters_3_address0(grp_td_fused_fu_1094_tdf4_filters_3_address0), + .tdf4_filters_3_ce0(grp_td_fused_fu_1094_tdf4_filters_3_ce0), + .tdf4_filters_3_d0(grp_td_fused_fu_1094_tdf4_filters_3_d0), + .tdf4_filters_3_q0(tdf4_filters_3_q0), + .tdf4_filters_3_we0(grp_td_fused_fu_1094_tdf4_filters_3_we0), + .tdf4_filters_3_address1(grp_td_fused_fu_1094_tdf4_filters_3_address1), + .tdf4_filters_3_ce1(grp_td_fused_fu_1094_tdf4_filters_3_ce1), + .tdf4_filters_3_d1(grp_td_fused_fu_1094_tdf4_filters_3_d1), + .tdf4_filters_3_q1(64'd0), + .tdf4_filters_3_we1(grp_td_fused_fu_1094_tdf4_filters_3_we1), + .tdf4_l2_filters_0_address0(grp_td_fused_fu_1094_tdf4_l2_filters_0_address0), + .tdf4_l2_filters_0_ce0(grp_td_fused_fu_1094_tdf4_l2_filters_0_ce0), + .tdf4_l2_filters_0_d0(grp_td_fused_fu_1094_tdf4_l2_filters_0_d0), + .tdf4_l2_filters_0_q0(tdf4_l2_filters_0_q0), + .tdf4_l2_filters_0_we0(grp_td_fused_fu_1094_tdf4_l2_filters_0_we0), + .tdf4_l2_filters_0_address1(grp_td_fused_fu_1094_tdf4_l2_filters_0_address1), + .tdf4_l2_filters_0_ce1(grp_td_fused_fu_1094_tdf4_l2_filters_0_ce1), + .tdf4_l2_filters_0_d1(grp_td_fused_fu_1094_tdf4_l2_filters_0_d1), + .tdf4_l2_filters_0_q1(tdf4_l2_filters_0_q1), + .tdf4_l2_filters_0_we1(grp_td_fused_fu_1094_tdf4_l2_filters_0_we1), + .tdf4_l2_filters_1_address0(grp_td_fused_fu_1094_tdf4_l2_filters_1_address0), + .tdf4_l2_filters_1_ce0(grp_td_fused_fu_1094_tdf4_l2_filters_1_ce0), + .tdf4_l2_filters_1_d0(grp_td_fused_fu_1094_tdf4_l2_filters_1_d0), + .tdf4_l2_filters_1_q0(tdf4_l2_filters_1_q0), + .tdf4_l2_filters_1_we0(grp_td_fused_fu_1094_tdf4_l2_filters_1_we0), + .tdf4_l2_filters_1_address1(grp_td_fused_fu_1094_tdf4_l2_filters_1_address1), + .tdf4_l2_filters_1_ce1(grp_td_fused_fu_1094_tdf4_l2_filters_1_ce1), + .tdf4_l2_filters_1_d1(grp_td_fused_fu_1094_tdf4_l2_filters_1_d1), + .tdf4_l2_filters_1_q1(tdf4_l2_filters_1_q1), + .tdf4_l2_filters_1_we1(grp_td_fused_fu_1094_tdf4_l2_filters_1_we1), + .tdf5_filters_0_address0(grp_td_fused_fu_1094_tdf5_filters_0_address0), + .tdf5_filters_0_ce0(grp_td_fused_fu_1094_tdf5_filters_0_ce0), + .tdf5_filters_0_d0(grp_td_fused_fu_1094_tdf5_filters_0_d0), + .tdf5_filters_0_q0(tdf5_filters_0_q0), + .tdf5_filters_0_we0(grp_td_fused_fu_1094_tdf5_filters_0_we0), + .tdf5_filters_0_address1(grp_td_fused_fu_1094_tdf5_filters_0_address1), + .tdf5_filters_0_ce1(grp_td_fused_fu_1094_tdf5_filters_0_ce1), + .tdf5_filters_0_d1(grp_td_fused_fu_1094_tdf5_filters_0_d1), + .tdf5_filters_0_q1(32'd0), + .tdf5_filters_0_we1(grp_td_fused_fu_1094_tdf5_filters_0_we1), + .tdf5_filters_1_address0(grp_td_fused_fu_1094_tdf5_filters_1_address0), + .tdf5_filters_1_ce0(grp_td_fused_fu_1094_tdf5_filters_1_ce0), + .tdf5_filters_1_d0(grp_td_fused_fu_1094_tdf5_filters_1_d0), + .tdf5_filters_1_q0(tdf5_filters_1_q0), + .tdf5_filters_1_we0(grp_td_fused_fu_1094_tdf5_filters_1_we0), + .tdf5_filters_1_address1(grp_td_fused_fu_1094_tdf5_filters_1_address1), + .tdf5_filters_1_ce1(grp_td_fused_fu_1094_tdf5_filters_1_ce1), + .tdf5_filters_1_d1(grp_td_fused_fu_1094_tdf5_filters_1_d1), + .tdf5_filters_1_q1(32'd0), + .tdf5_filters_1_we1(grp_td_fused_fu_1094_tdf5_filters_1_we1), + .tdf5_filters_2_address0(grp_td_fused_fu_1094_tdf5_filters_2_address0), + .tdf5_filters_2_ce0(grp_td_fused_fu_1094_tdf5_filters_2_ce0), + .tdf5_filters_2_d0(grp_td_fused_fu_1094_tdf5_filters_2_d0), + .tdf5_filters_2_q0(tdf5_filters_2_q0), + .tdf5_filters_2_we0(grp_td_fused_fu_1094_tdf5_filters_2_we0), + .tdf5_filters_2_address1(grp_td_fused_fu_1094_tdf5_filters_2_address1), + .tdf5_filters_2_ce1(grp_td_fused_fu_1094_tdf5_filters_2_ce1), + .tdf5_filters_2_d1(grp_td_fused_fu_1094_tdf5_filters_2_d1), + .tdf5_filters_2_q1(32'd0), + .tdf5_filters_2_we1(grp_td_fused_fu_1094_tdf5_filters_2_we1), + .tdf5_filters_3_address0(grp_td_fused_fu_1094_tdf5_filters_3_address0), + .tdf5_filters_3_ce0(grp_td_fused_fu_1094_tdf5_filters_3_ce0), + .tdf5_filters_3_d0(grp_td_fused_fu_1094_tdf5_filters_3_d0), + .tdf5_filters_3_q0(tdf5_filters_3_q0), + .tdf5_filters_3_we0(grp_td_fused_fu_1094_tdf5_filters_3_we0), + .tdf5_filters_3_address1(grp_td_fused_fu_1094_tdf5_filters_3_address1), + .tdf5_filters_3_ce1(grp_td_fused_fu_1094_tdf5_filters_3_ce1), + .tdf5_filters_3_d1(grp_td_fused_fu_1094_tdf5_filters_3_d1), + .tdf5_filters_3_q1(32'd0), + .tdf5_filters_3_we1(grp_td_fused_fu_1094_tdf5_filters_3_we1), + .tdf6_filters_address0(grp_td_fused_fu_1094_tdf6_filters_address0), + .tdf6_filters_ce0(grp_td_fused_fu_1094_tdf6_filters_ce0), + .tdf6_filters_d0(grp_td_fused_fu_1094_tdf6_filters_d0), + .tdf6_filters_q0(tdf6_filters_q0), + .tdf6_filters_we0(grp_td_fused_fu_1094_tdf6_filters_we0), + .tdf6_filters_address1(grp_td_fused_fu_1094_tdf6_filters_address1), + .tdf6_filters_ce1(grp_td_fused_fu_1094_tdf6_filters_ce1), + .tdf6_filters_d1(grp_td_fused_fu_1094_tdf6_filters_d1), + .tdf6_filters_q1(16'd0), + .tdf6_filters_we1(grp_td_fused_fu_1094_tdf6_filters_we1), + .tdf7_filters_0_address0(grp_td_fused_fu_1094_tdf7_filters_0_address0), + .tdf7_filters_0_ce0(grp_td_fused_fu_1094_tdf7_filters_0_ce0), + .tdf7_filters_0_d0(grp_td_fused_fu_1094_tdf7_filters_0_d0), + .tdf7_filters_0_q0(tdf7_filters_0_q0), + .tdf7_filters_0_we0(grp_td_fused_fu_1094_tdf7_filters_0_we0), + .tdf7_filters_0_address1(grp_td_fused_fu_1094_tdf7_filters_0_address1), + .tdf7_filters_0_ce1(grp_td_fused_fu_1094_tdf7_filters_0_ce1), + .tdf7_filters_0_d1(grp_td_fused_fu_1094_tdf7_filters_0_d1), + .tdf7_filters_0_q1(64'd0), + .tdf7_filters_0_we1(grp_td_fused_fu_1094_tdf7_filters_0_we1), + .tdf7_filters_1_address0(grp_td_fused_fu_1094_tdf7_filters_1_address0), + .tdf7_filters_1_ce0(grp_td_fused_fu_1094_tdf7_filters_1_ce0), + .tdf7_filters_1_d0(grp_td_fused_fu_1094_tdf7_filters_1_d0), + .tdf7_filters_1_q0(tdf7_filters_1_q0), + .tdf7_filters_1_we0(grp_td_fused_fu_1094_tdf7_filters_1_we0), + .tdf7_filters_1_address1(grp_td_fused_fu_1094_tdf7_filters_1_address1), + .tdf7_filters_1_ce1(grp_td_fused_fu_1094_tdf7_filters_1_ce1), + .tdf7_filters_1_d1(grp_td_fused_fu_1094_tdf7_filters_1_d1), + .tdf7_filters_1_q1(64'd0), + .tdf7_filters_1_we1(grp_td_fused_fu_1094_tdf7_filters_1_we1), + .tdf7_filters_2_address0(grp_td_fused_fu_1094_tdf7_filters_2_address0), + .tdf7_filters_2_ce0(grp_td_fused_fu_1094_tdf7_filters_2_ce0), + .tdf7_filters_2_d0(grp_td_fused_fu_1094_tdf7_filters_2_d0), + .tdf7_filters_2_q0(tdf7_filters_2_q0), + .tdf7_filters_2_we0(grp_td_fused_fu_1094_tdf7_filters_2_we0), + .tdf7_filters_2_address1(grp_td_fused_fu_1094_tdf7_filters_2_address1), + .tdf7_filters_2_ce1(grp_td_fused_fu_1094_tdf7_filters_2_ce1), + .tdf7_filters_2_d1(grp_td_fused_fu_1094_tdf7_filters_2_d1), + .tdf7_filters_2_q1(64'd0), + .tdf7_filters_2_we1(grp_td_fused_fu_1094_tdf7_filters_2_we1), + .tdf7_filters_3_address0(grp_td_fused_fu_1094_tdf7_filters_3_address0), + .tdf7_filters_3_ce0(grp_td_fused_fu_1094_tdf7_filters_3_ce0), + .tdf7_filters_3_d0(grp_td_fused_fu_1094_tdf7_filters_3_d0), + .tdf7_filters_3_q0(tdf7_filters_3_q0), + .tdf7_filters_3_we0(grp_td_fused_fu_1094_tdf7_filters_3_we0), + .tdf7_filters_3_address1(grp_td_fused_fu_1094_tdf7_filters_3_address1), + .tdf7_filters_3_ce1(grp_td_fused_fu_1094_tdf7_filters_3_ce1), + .tdf7_filters_3_d1(grp_td_fused_fu_1094_tdf7_filters_3_d1), + .tdf7_filters_3_q1(64'd0), + .tdf7_filters_3_we1(grp_td_fused_fu_1094_tdf7_filters_3_we1), + .tdf7_l2_filters_0_address0(grp_td_fused_fu_1094_tdf7_l2_filters_0_address0), + .tdf7_l2_filters_0_ce0(grp_td_fused_fu_1094_tdf7_l2_filters_0_ce0), + .tdf7_l2_filters_0_d0(grp_td_fused_fu_1094_tdf7_l2_filters_0_d0), + .tdf7_l2_filters_0_q0(tdf7_l2_filters_0_q0), + .tdf7_l2_filters_0_we0(grp_td_fused_fu_1094_tdf7_l2_filters_0_we0), + .tdf7_l2_filters_0_address1(grp_td_fused_fu_1094_tdf7_l2_filters_0_address1), + .tdf7_l2_filters_0_ce1(grp_td_fused_fu_1094_tdf7_l2_filters_0_ce1), + .tdf7_l2_filters_0_d1(grp_td_fused_fu_1094_tdf7_l2_filters_0_d1), + .tdf7_l2_filters_0_q1(tdf7_l2_filters_0_q1), + .tdf7_l2_filters_0_we1(grp_td_fused_fu_1094_tdf7_l2_filters_0_we1), + .tdf7_l2_filters_1_address0(grp_td_fused_fu_1094_tdf7_l2_filters_1_address0), + .tdf7_l2_filters_1_ce0(grp_td_fused_fu_1094_tdf7_l2_filters_1_ce0), + .tdf7_l2_filters_1_d0(grp_td_fused_fu_1094_tdf7_l2_filters_1_d0), + .tdf7_l2_filters_1_q0(tdf7_l2_filters_1_q0), + .tdf7_l2_filters_1_we0(grp_td_fused_fu_1094_tdf7_l2_filters_1_we0), + .tdf7_l2_filters_1_address1(grp_td_fused_fu_1094_tdf7_l2_filters_1_address1), + .tdf7_l2_filters_1_ce1(grp_td_fused_fu_1094_tdf7_l2_filters_1_ce1), + .tdf7_l2_filters_1_d1(grp_td_fused_fu_1094_tdf7_l2_filters_1_d1), + .tdf7_l2_filters_1_q1(tdf7_l2_filters_1_q1), + .tdf7_l2_filters_1_we1(grp_td_fused_fu_1094_tdf7_l2_filters_1_we1), + .tdf8_filters_0_address0(grp_td_fused_fu_1094_tdf8_filters_0_address0), + .tdf8_filters_0_ce0(grp_td_fused_fu_1094_tdf8_filters_0_ce0), + .tdf8_filters_0_d0(grp_td_fused_fu_1094_tdf8_filters_0_d0), + .tdf8_filters_0_q0(tdf8_filters_0_q0), + .tdf8_filters_0_we0(grp_td_fused_fu_1094_tdf8_filters_0_we0), + .tdf8_filters_0_address1(grp_td_fused_fu_1094_tdf8_filters_0_address1), + .tdf8_filters_0_ce1(grp_td_fused_fu_1094_tdf8_filters_0_ce1), + .tdf8_filters_0_d1(grp_td_fused_fu_1094_tdf8_filters_0_d1), + .tdf8_filters_0_q1(32'd0), + .tdf8_filters_0_we1(grp_td_fused_fu_1094_tdf8_filters_0_we1), + .tdf8_filters_1_address0(grp_td_fused_fu_1094_tdf8_filters_1_address0), + .tdf8_filters_1_ce0(grp_td_fused_fu_1094_tdf8_filters_1_ce0), + .tdf8_filters_1_d0(grp_td_fused_fu_1094_tdf8_filters_1_d0), + .tdf8_filters_1_q0(tdf8_filters_1_q0), + .tdf8_filters_1_we0(grp_td_fused_fu_1094_tdf8_filters_1_we0), + .tdf8_filters_1_address1(grp_td_fused_fu_1094_tdf8_filters_1_address1), + .tdf8_filters_1_ce1(grp_td_fused_fu_1094_tdf8_filters_1_ce1), + .tdf8_filters_1_d1(grp_td_fused_fu_1094_tdf8_filters_1_d1), + .tdf8_filters_1_q1(32'd0), + .tdf8_filters_1_we1(grp_td_fused_fu_1094_tdf8_filters_1_we1), + .tdf8_filters_2_address0(grp_td_fused_fu_1094_tdf8_filters_2_address0), + .tdf8_filters_2_ce0(grp_td_fused_fu_1094_tdf8_filters_2_ce0), + .tdf8_filters_2_d0(grp_td_fused_fu_1094_tdf8_filters_2_d0), + .tdf8_filters_2_q0(tdf8_filters_2_q0), + .tdf8_filters_2_we0(grp_td_fused_fu_1094_tdf8_filters_2_we0), + .tdf8_filters_2_address1(grp_td_fused_fu_1094_tdf8_filters_2_address1), + .tdf8_filters_2_ce1(grp_td_fused_fu_1094_tdf8_filters_2_ce1), + .tdf8_filters_2_d1(grp_td_fused_fu_1094_tdf8_filters_2_d1), + .tdf8_filters_2_q1(32'd0), + .tdf8_filters_2_we1(grp_td_fused_fu_1094_tdf8_filters_2_we1), + .tdf8_filters_3_address0(grp_td_fused_fu_1094_tdf8_filters_3_address0), + .tdf8_filters_3_ce0(grp_td_fused_fu_1094_tdf8_filters_3_ce0), + .tdf8_filters_3_d0(grp_td_fused_fu_1094_tdf8_filters_3_d0), + .tdf8_filters_3_q0(tdf8_filters_3_q0), + .tdf8_filters_3_we0(grp_td_fused_fu_1094_tdf8_filters_3_we0), + .tdf8_filters_3_address1(grp_td_fused_fu_1094_tdf8_filters_3_address1), + .tdf8_filters_3_ce1(grp_td_fused_fu_1094_tdf8_filters_3_ce1), + .tdf8_filters_3_d1(grp_td_fused_fu_1094_tdf8_filters_3_d1), + .tdf8_filters_3_q1(32'd0), + .tdf8_filters_3_we1(grp_td_fused_fu_1094_tdf8_filters_3_we1), + .tdf9_filters_address0(grp_td_fused_fu_1094_tdf9_filters_address0), + .tdf9_filters_ce0(grp_td_fused_fu_1094_tdf9_filters_ce0), + .tdf9_filters_d0(grp_td_fused_fu_1094_tdf9_filters_d0), + .tdf9_filters_q0(tdf9_filters_q0), + .tdf9_filters_we0(grp_td_fused_fu_1094_tdf9_filters_we0), + .tdf9_filters_address1(grp_td_fused_fu_1094_tdf9_filters_address1), + .tdf9_filters_ce1(grp_td_fused_fu_1094_tdf9_filters_ce1), + .tdf9_filters_d1(grp_td_fused_fu_1094_tdf9_filters_d1), + .tdf9_filters_q1(16'd0), + .tdf9_filters_we1(grp_td_fused_fu_1094_tdf9_filters_we1), + .tdf10_filters_0_address0(grp_td_fused_fu_1094_tdf10_filters_0_address0), + .tdf10_filters_0_ce0(grp_td_fused_fu_1094_tdf10_filters_0_ce0), + .tdf10_filters_0_d0(grp_td_fused_fu_1094_tdf10_filters_0_d0), + .tdf10_filters_0_q0(tdf10_filters_0_q0), + .tdf10_filters_0_we0(grp_td_fused_fu_1094_tdf10_filters_0_we0), + .tdf10_filters_0_address1(grp_td_fused_fu_1094_tdf10_filters_0_address1), + .tdf10_filters_0_ce1(grp_td_fused_fu_1094_tdf10_filters_0_ce1), + .tdf10_filters_0_d1(grp_td_fused_fu_1094_tdf10_filters_0_d1), + .tdf10_filters_0_q1(64'd0), + .tdf10_filters_0_we1(grp_td_fused_fu_1094_tdf10_filters_0_we1), + .tdf10_filters_1_address0(grp_td_fused_fu_1094_tdf10_filters_1_address0), + .tdf10_filters_1_ce0(grp_td_fused_fu_1094_tdf10_filters_1_ce0), + .tdf10_filters_1_d0(grp_td_fused_fu_1094_tdf10_filters_1_d0), + .tdf10_filters_1_q0(tdf10_filters_1_q0), + .tdf10_filters_1_we0(grp_td_fused_fu_1094_tdf10_filters_1_we0), + .tdf10_filters_1_address1(grp_td_fused_fu_1094_tdf10_filters_1_address1), + .tdf10_filters_1_ce1(grp_td_fused_fu_1094_tdf10_filters_1_ce1), + .tdf10_filters_1_d1(grp_td_fused_fu_1094_tdf10_filters_1_d1), + .tdf10_filters_1_q1(64'd0), + .tdf10_filters_1_we1(grp_td_fused_fu_1094_tdf10_filters_1_we1), + .tdf10_filters_2_address0(grp_td_fused_fu_1094_tdf10_filters_2_address0), + .tdf10_filters_2_ce0(grp_td_fused_fu_1094_tdf10_filters_2_ce0), + .tdf10_filters_2_d0(grp_td_fused_fu_1094_tdf10_filters_2_d0), + .tdf10_filters_2_q0(tdf10_filters_2_q0), + .tdf10_filters_2_we0(grp_td_fused_fu_1094_tdf10_filters_2_we0), + .tdf10_filters_2_address1(grp_td_fused_fu_1094_tdf10_filters_2_address1), + .tdf10_filters_2_ce1(grp_td_fused_fu_1094_tdf10_filters_2_ce1), + .tdf10_filters_2_d1(grp_td_fused_fu_1094_tdf10_filters_2_d1), + .tdf10_filters_2_q1(64'd0), + .tdf10_filters_2_we1(grp_td_fused_fu_1094_tdf10_filters_2_we1), + .tdf10_filters_3_address0(grp_td_fused_fu_1094_tdf10_filters_3_address0), + .tdf10_filters_3_ce0(grp_td_fused_fu_1094_tdf10_filters_3_ce0), + .tdf10_filters_3_d0(grp_td_fused_fu_1094_tdf10_filters_3_d0), + .tdf10_filters_3_q0(tdf10_filters_3_q0), + .tdf10_filters_3_we0(grp_td_fused_fu_1094_tdf10_filters_3_we0), + .tdf10_filters_3_address1(grp_td_fused_fu_1094_tdf10_filters_3_address1), + .tdf10_filters_3_ce1(grp_td_fused_fu_1094_tdf10_filters_3_ce1), + .tdf10_filters_3_d1(grp_td_fused_fu_1094_tdf10_filters_3_d1), + .tdf10_filters_3_q1(64'd0), + .tdf10_filters_3_we1(grp_td_fused_fu_1094_tdf10_filters_3_we1), + .tdf10_l2_filters_0_address0(grp_td_fused_fu_1094_tdf10_l2_filters_0_address0), + .tdf10_l2_filters_0_ce0(grp_td_fused_fu_1094_tdf10_l2_filters_0_ce0), + .tdf10_l2_filters_0_d0(grp_td_fused_fu_1094_tdf10_l2_filters_0_d0), + .tdf10_l2_filters_0_q0(tdf10_l2_filters_0_q0), + .tdf10_l2_filters_0_we0(grp_td_fused_fu_1094_tdf10_l2_filters_0_we0), + .tdf10_l2_filters_0_address1(grp_td_fused_fu_1094_tdf10_l2_filters_0_address1), + .tdf10_l2_filters_0_ce1(grp_td_fused_fu_1094_tdf10_l2_filters_0_ce1), + .tdf10_l2_filters_0_d1(grp_td_fused_fu_1094_tdf10_l2_filters_0_d1), + .tdf10_l2_filters_0_q1(tdf10_l2_filters_0_q1), + .tdf10_l2_filters_0_we1(grp_td_fused_fu_1094_tdf10_l2_filters_0_we1), + .tdf10_l2_filters_1_address0(grp_td_fused_fu_1094_tdf10_l2_filters_1_address0), + .tdf10_l2_filters_1_ce0(grp_td_fused_fu_1094_tdf10_l2_filters_1_ce0), + .tdf10_l2_filters_1_d0(grp_td_fused_fu_1094_tdf10_l2_filters_1_d0), + .tdf10_l2_filters_1_q0(tdf10_l2_filters_1_q0), + .tdf10_l2_filters_1_we0(grp_td_fused_fu_1094_tdf10_l2_filters_1_we0), + .tdf10_l2_filters_1_address1(grp_td_fused_fu_1094_tdf10_l2_filters_1_address1), + .tdf10_l2_filters_1_ce1(grp_td_fused_fu_1094_tdf10_l2_filters_1_ce1), + .tdf10_l2_filters_1_d1(grp_td_fused_fu_1094_tdf10_l2_filters_1_d1), + .tdf10_l2_filters_1_q1(tdf10_l2_filters_1_q1), + .tdf10_l2_filters_1_we1(grp_td_fused_fu_1094_tdf10_l2_filters_1_we1), + .tdf11_filters_0_address0(grp_td_fused_fu_1094_tdf11_filters_0_address0), + .tdf11_filters_0_ce0(grp_td_fused_fu_1094_tdf11_filters_0_ce0), + .tdf11_filters_0_d0(grp_td_fused_fu_1094_tdf11_filters_0_d0), + .tdf11_filters_0_q0(tdf11_filters_0_q0), + .tdf11_filters_0_we0(grp_td_fused_fu_1094_tdf11_filters_0_we0), + .tdf11_filters_0_address1(grp_td_fused_fu_1094_tdf11_filters_0_address1), + .tdf11_filters_0_ce1(grp_td_fused_fu_1094_tdf11_filters_0_ce1), + .tdf11_filters_0_d1(grp_td_fused_fu_1094_tdf11_filters_0_d1), + .tdf11_filters_0_q1(64'd0), + .tdf11_filters_0_we1(grp_td_fused_fu_1094_tdf11_filters_0_we1), + .tdf11_filters_1_address0(grp_td_fused_fu_1094_tdf11_filters_1_address0), + .tdf11_filters_1_ce0(grp_td_fused_fu_1094_tdf11_filters_1_ce0), + .tdf11_filters_1_d0(grp_td_fused_fu_1094_tdf11_filters_1_d0), + .tdf11_filters_1_q0(tdf11_filters_1_q0), + .tdf11_filters_1_we0(grp_td_fused_fu_1094_tdf11_filters_1_we0), + .tdf11_filters_1_address1(grp_td_fused_fu_1094_tdf11_filters_1_address1), + .tdf11_filters_1_ce1(grp_td_fused_fu_1094_tdf11_filters_1_ce1), + .tdf11_filters_1_d1(grp_td_fused_fu_1094_tdf11_filters_1_d1), + .tdf11_filters_1_q1(64'd0), + .tdf11_filters_1_we1(grp_td_fused_fu_1094_tdf11_filters_1_we1), + .tdf11_filters_2_address0(grp_td_fused_fu_1094_tdf11_filters_2_address0), + .tdf11_filters_2_ce0(grp_td_fused_fu_1094_tdf11_filters_2_ce0), + .tdf11_filters_2_d0(grp_td_fused_fu_1094_tdf11_filters_2_d0), + .tdf11_filters_2_q0(tdf11_filters_2_q0), + .tdf11_filters_2_we0(grp_td_fused_fu_1094_tdf11_filters_2_we0), + .tdf11_filters_2_address1(grp_td_fused_fu_1094_tdf11_filters_2_address1), + .tdf11_filters_2_ce1(grp_td_fused_fu_1094_tdf11_filters_2_ce1), + .tdf11_filters_2_d1(grp_td_fused_fu_1094_tdf11_filters_2_d1), + .tdf11_filters_2_q1(64'd0), + .tdf11_filters_2_we1(grp_td_fused_fu_1094_tdf11_filters_2_we1), + .tdf11_filters_3_address0(grp_td_fused_fu_1094_tdf11_filters_3_address0), + .tdf11_filters_3_ce0(grp_td_fused_fu_1094_tdf11_filters_3_ce0), + .tdf11_filters_3_d0(grp_td_fused_fu_1094_tdf11_filters_3_d0), + .tdf11_filters_3_q0(tdf11_filters_3_q0), + .tdf11_filters_3_we0(grp_td_fused_fu_1094_tdf11_filters_3_we0), + .tdf11_filters_3_address1(grp_td_fused_fu_1094_tdf11_filters_3_address1), + .tdf11_filters_3_ce1(grp_td_fused_fu_1094_tdf11_filters_3_ce1), + .tdf11_filters_3_d1(grp_td_fused_fu_1094_tdf11_filters_3_d1), + .tdf11_filters_3_q1(64'd0), + .tdf11_filters_3_we1(grp_td_fused_fu_1094_tdf11_filters_3_we1), + .tdf11_l2_filters_0_address0(grp_td_fused_fu_1094_tdf11_l2_filters_0_address0), + .tdf11_l2_filters_0_ce0(grp_td_fused_fu_1094_tdf11_l2_filters_0_ce0), + .tdf11_l2_filters_0_d0(grp_td_fused_fu_1094_tdf11_l2_filters_0_d0), + .tdf11_l2_filters_0_q0(tdf11_l2_filters_0_q0), + .tdf11_l2_filters_0_we0(grp_td_fused_fu_1094_tdf11_l2_filters_0_we0), + .tdf11_l2_filters_0_address1(grp_td_fused_fu_1094_tdf11_l2_filters_0_address1), + .tdf11_l2_filters_0_ce1(grp_td_fused_fu_1094_tdf11_l2_filters_0_ce1), + .tdf11_l2_filters_0_d1(grp_td_fused_fu_1094_tdf11_l2_filters_0_d1), + .tdf11_l2_filters_0_q1(tdf11_l2_filters_0_q1), + .tdf11_l2_filters_0_we1(grp_td_fused_fu_1094_tdf11_l2_filters_0_we1), + .tdf11_l2_filters_1_address0(grp_td_fused_fu_1094_tdf11_l2_filters_1_address0), + .tdf11_l2_filters_1_ce0(grp_td_fused_fu_1094_tdf11_l2_filters_1_ce0), + .tdf11_l2_filters_1_d0(grp_td_fused_fu_1094_tdf11_l2_filters_1_d0), + .tdf11_l2_filters_1_q0(tdf11_l2_filters_1_q0), + .tdf11_l2_filters_1_we0(grp_td_fused_fu_1094_tdf11_l2_filters_1_we0), + .tdf11_l2_filters_1_address1(grp_td_fused_fu_1094_tdf11_l2_filters_1_address1), + .tdf11_l2_filters_1_ce1(grp_td_fused_fu_1094_tdf11_l2_filters_1_ce1), + .tdf11_l2_filters_1_d1(grp_td_fused_fu_1094_tdf11_l2_filters_1_d1), + .tdf11_l2_filters_1_q1(tdf11_l2_filters_1_q1), + .tdf11_l2_filters_1_we1(grp_td_fused_fu_1094_tdf11_l2_filters_1_we1), + .tdf11_l2_filters_2_address0(grp_td_fused_fu_1094_tdf11_l2_filters_2_address0), + .tdf11_l2_filters_2_ce0(grp_td_fused_fu_1094_tdf11_l2_filters_2_ce0), + .tdf11_l2_filters_2_d0(grp_td_fused_fu_1094_tdf11_l2_filters_2_d0), + .tdf11_l2_filters_2_q0(tdf11_l2_filters_2_q0), + .tdf11_l2_filters_2_we0(grp_td_fused_fu_1094_tdf11_l2_filters_2_we0), + .tdf11_l2_filters_2_address1(grp_td_fused_fu_1094_tdf11_l2_filters_2_address1), + .tdf11_l2_filters_2_ce1(grp_td_fused_fu_1094_tdf11_l2_filters_2_ce1), + .tdf11_l2_filters_2_d1(grp_td_fused_fu_1094_tdf11_l2_filters_2_d1), + .tdf11_l2_filters_2_q1(tdf11_l2_filters_2_q1), + .tdf11_l2_filters_2_we1(grp_td_fused_fu_1094_tdf11_l2_filters_2_we1), + .tdf11_l2_filters_3_address0(grp_td_fused_fu_1094_tdf11_l2_filters_3_address0), + .tdf11_l2_filters_3_ce0(grp_td_fused_fu_1094_tdf11_l2_filters_3_ce0), + .tdf11_l2_filters_3_d0(grp_td_fused_fu_1094_tdf11_l2_filters_3_d0), + .tdf11_l2_filters_3_q0(tdf11_l2_filters_3_q0), + .tdf11_l2_filters_3_we0(grp_td_fused_fu_1094_tdf11_l2_filters_3_we0), + .tdf11_l2_filters_3_address1(grp_td_fused_fu_1094_tdf11_l2_filters_3_address1), + .tdf11_l2_filters_3_ce1(grp_td_fused_fu_1094_tdf11_l2_filters_3_ce1), + .tdf11_l2_filters_3_d1(grp_td_fused_fu_1094_tdf11_l2_filters_3_d1), + .tdf11_l2_filters_3_q1(tdf11_l2_filters_3_q1), + .tdf11_l2_filters_3_we1(grp_td_fused_fu_1094_tdf11_l2_filters_3_we1), + .tdf12_filters_0_address0(grp_td_fused_fu_1094_tdf12_filters_0_address0), + .tdf12_filters_0_ce0(grp_td_fused_fu_1094_tdf12_filters_0_ce0), + .tdf12_filters_0_d0(grp_td_fused_fu_1094_tdf12_filters_0_d0), + .tdf12_filters_0_q0(tdf12_filters_0_q0), + .tdf12_filters_0_we0(grp_td_fused_fu_1094_tdf12_filters_0_we0), + .tdf12_filters_0_address1(grp_td_fused_fu_1094_tdf12_filters_0_address1), + .tdf12_filters_0_ce1(grp_td_fused_fu_1094_tdf12_filters_0_ce1), + .tdf12_filters_0_d1(grp_td_fused_fu_1094_tdf12_filters_0_d1), + .tdf12_filters_0_q1(32'd0), + .tdf12_filters_0_we1(grp_td_fused_fu_1094_tdf12_filters_0_we1), + .tdf12_filters_1_address0(grp_td_fused_fu_1094_tdf12_filters_1_address0), + .tdf12_filters_1_ce0(grp_td_fused_fu_1094_tdf12_filters_1_ce0), + .tdf12_filters_1_d0(grp_td_fused_fu_1094_tdf12_filters_1_d0), + .tdf12_filters_1_q0(tdf12_filters_1_q0), + .tdf12_filters_1_we0(grp_td_fused_fu_1094_tdf12_filters_1_we0), + .tdf12_filters_1_address1(grp_td_fused_fu_1094_tdf12_filters_1_address1), + .tdf12_filters_1_ce1(grp_td_fused_fu_1094_tdf12_filters_1_ce1), + .tdf12_filters_1_d1(grp_td_fused_fu_1094_tdf12_filters_1_d1), + .tdf12_filters_1_q1(32'd0), + .tdf12_filters_1_we1(grp_td_fused_fu_1094_tdf12_filters_1_we1), + .tdf1_adjustments_address0(grp_td_fused_fu_1094_tdf1_adjustments_address0), + .tdf1_adjustments_ce0(grp_td_fused_fu_1094_tdf1_adjustments_ce0), + .tdf1_adjustments_d0(grp_td_fused_fu_1094_tdf1_adjustments_d0), + .tdf1_adjustments_q0(tdf1_adjustments_q0), + .tdf1_adjustments_we0(grp_td_fused_fu_1094_tdf1_adjustments_we0), + .tdf1_adjustments_address1(grp_td_fused_fu_1094_tdf1_adjustments_address1), + .tdf1_adjustments_ce1(grp_td_fused_fu_1094_tdf1_adjustments_ce1), + .tdf1_adjustments_d1(grp_td_fused_fu_1094_tdf1_adjustments_d1), + .tdf1_adjustments_q1(48'd0), + .tdf1_adjustments_we1(grp_td_fused_fu_1094_tdf1_adjustments_we1), + .tdf2_adjustments_address0(grp_td_fused_fu_1094_tdf2_adjustments_address0), + .tdf2_adjustments_ce0(grp_td_fused_fu_1094_tdf2_adjustments_ce0), + .tdf2_adjustments_d0(grp_td_fused_fu_1094_tdf2_adjustments_d0), + .tdf2_adjustments_q0(tdf2_adjustments_q0), + .tdf2_adjustments_we0(grp_td_fused_fu_1094_tdf2_adjustments_we0), + .tdf2_adjustments_address1(grp_td_fused_fu_1094_tdf2_adjustments_address1), + .tdf2_adjustments_ce1(grp_td_fused_fu_1094_tdf2_adjustments_ce1), + .tdf2_adjustments_d1(grp_td_fused_fu_1094_tdf2_adjustments_d1), + .tdf2_adjustments_q1(48'd0), + .tdf2_adjustments_we1(grp_td_fused_fu_1094_tdf2_adjustments_we1), + .tdf3_adjustments_address0(grp_td_fused_fu_1094_tdf3_adjustments_address0), + .tdf3_adjustments_ce0(grp_td_fused_fu_1094_tdf3_adjustments_ce0), + .tdf3_adjustments_d0(grp_td_fused_fu_1094_tdf3_adjustments_d0), + .tdf3_adjustments_q0(tdf3_adjustments_q0), + .tdf3_adjustments_we0(grp_td_fused_fu_1094_tdf3_adjustments_we0), + .tdf3_adjustments_address1(grp_td_fused_fu_1094_tdf3_adjustments_address1), + .tdf3_adjustments_ce1(grp_td_fused_fu_1094_tdf3_adjustments_ce1), + .tdf3_adjustments_d1(grp_td_fused_fu_1094_tdf3_adjustments_d1), + .tdf3_adjustments_q1(48'd0), + .tdf3_adjustments_we1(grp_td_fused_fu_1094_tdf3_adjustments_we1), + .tdf4_adjustments_address0(grp_td_fused_fu_1094_tdf4_adjustments_address0), + .tdf4_adjustments_ce0(grp_td_fused_fu_1094_tdf4_adjustments_ce0), + .tdf4_adjustments_d0(grp_td_fused_fu_1094_tdf4_adjustments_d0), + .tdf4_adjustments_q0(tdf4_adjustments_q0), + .tdf4_adjustments_we0(grp_td_fused_fu_1094_tdf4_adjustments_we0), + .tdf4_adjustments_address1(grp_td_fused_fu_1094_tdf4_adjustments_address1), + .tdf4_adjustments_ce1(grp_td_fused_fu_1094_tdf4_adjustments_ce1), + .tdf4_adjustments_d1(grp_td_fused_fu_1094_tdf4_adjustments_d1), + .tdf4_adjustments_q1(48'd0), + .tdf4_adjustments_we1(grp_td_fused_fu_1094_tdf4_adjustments_we1), + .tdf4_l2_adjustments_address0(grp_td_fused_fu_1094_tdf4_l2_adjustments_address0), + .tdf4_l2_adjustments_ce0(grp_td_fused_fu_1094_tdf4_l2_adjustments_ce0), + .tdf4_l2_adjustments_d0(grp_td_fused_fu_1094_tdf4_l2_adjustments_d0), + .tdf4_l2_adjustments_q0(tdf4_l2_adjustments_q0), + .tdf4_l2_adjustments_we0(grp_td_fused_fu_1094_tdf4_l2_adjustments_we0), + .tdf4_l2_adjustments_address1(grp_td_fused_fu_1094_tdf4_l2_adjustments_address1), + .tdf4_l2_adjustments_ce1(grp_td_fused_fu_1094_tdf4_l2_adjustments_ce1), + .tdf4_l2_adjustments_d1(grp_td_fused_fu_1094_tdf4_l2_adjustments_d1), + .tdf4_l2_adjustments_q1(48'd0), + .tdf4_l2_adjustments_we1(grp_td_fused_fu_1094_tdf4_l2_adjustments_we1), + .tdf5_adjustments_address0(grp_td_fused_fu_1094_tdf5_adjustments_address0), + .tdf5_adjustments_ce0(grp_td_fused_fu_1094_tdf5_adjustments_ce0), + .tdf5_adjustments_d0(grp_td_fused_fu_1094_tdf5_adjustments_d0), + .tdf5_adjustments_q0(tdf5_adjustments_q0), + .tdf5_adjustments_we0(grp_td_fused_fu_1094_tdf5_adjustments_we0), + .tdf5_adjustments_address1(grp_td_fused_fu_1094_tdf5_adjustments_address1), + .tdf5_adjustments_ce1(grp_td_fused_fu_1094_tdf5_adjustments_ce1), + .tdf5_adjustments_d1(grp_td_fused_fu_1094_tdf5_adjustments_d1), + .tdf5_adjustments_q1(48'd0), + .tdf5_adjustments_we1(grp_td_fused_fu_1094_tdf5_adjustments_we1), + .tdf6_adjustments_address0(grp_td_fused_fu_1094_tdf6_adjustments_address0), + .tdf6_adjustments_ce0(grp_td_fused_fu_1094_tdf6_adjustments_ce0), + .tdf6_adjustments_d0(grp_td_fused_fu_1094_tdf6_adjustments_d0), + .tdf6_adjustments_q0(tdf6_adjustments_q0), + .tdf6_adjustments_we0(grp_td_fused_fu_1094_tdf6_adjustments_we0), + .tdf6_adjustments_address1(grp_td_fused_fu_1094_tdf6_adjustments_address1), + .tdf6_adjustments_ce1(grp_td_fused_fu_1094_tdf6_adjustments_ce1), + .tdf6_adjustments_d1(grp_td_fused_fu_1094_tdf6_adjustments_d1), + .tdf6_adjustments_q1(48'd0), + .tdf6_adjustments_we1(grp_td_fused_fu_1094_tdf6_adjustments_we1), + .tdf7_adjustments_address0(grp_td_fused_fu_1094_tdf7_adjustments_address0), + .tdf7_adjustments_ce0(grp_td_fused_fu_1094_tdf7_adjustments_ce0), + .tdf7_adjustments_d0(grp_td_fused_fu_1094_tdf7_adjustments_d0), + .tdf7_adjustments_q0(tdf7_adjustments_q0), + .tdf7_adjustments_we0(grp_td_fused_fu_1094_tdf7_adjustments_we0), + .tdf7_adjustments_address1(grp_td_fused_fu_1094_tdf7_adjustments_address1), + .tdf7_adjustments_ce1(grp_td_fused_fu_1094_tdf7_adjustments_ce1), + .tdf7_adjustments_d1(grp_td_fused_fu_1094_tdf7_adjustments_d1), + .tdf7_adjustments_q1(48'd0), + .tdf7_adjustments_we1(grp_td_fused_fu_1094_tdf7_adjustments_we1), + .tdf7_l2_adjustments_address0(grp_td_fused_fu_1094_tdf7_l2_adjustments_address0), + .tdf7_l2_adjustments_ce0(grp_td_fused_fu_1094_tdf7_l2_adjustments_ce0), + .tdf7_l2_adjustments_d0(grp_td_fused_fu_1094_tdf7_l2_adjustments_d0), + .tdf7_l2_adjustments_q0(tdf7_l2_adjustments_q0), + .tdf7_l2_adjustments_we0(grp_td_fused_fu_1094_tdf7_l2_adjustments_we0), + .tdf7_l2_adjustments_address1(grp_td_fused_fu_1094_tdf7_l2_adjustments_address1), + .tdf7_l2_adjustments_ce1(grp_td_fused_fu_1094_tdf7_l2_adjustments_ce1), + .tdf7_l2_adjustments_d1(grp_td_fused_fu_1094_tdf7_l2_adjustments_d1), + .tdf7_l2_adjustments_q1(48'd0), + .tdf7_l2_adjustments_we1(grp_td_fused_fu_1094_tdf7_l2_adjustments_we1), + .tdf8_adjustments_address0(grp_td_fused_fu_1094_tdf8_adjustments_address0), + .tdf8_adjustments_ce0(grp_td_fused_fu_1094_tdf8_adjustments_ce0), + .tdf8_adjustments_d0(grp_td_fused_fu_1094_tdf8_adjustments_d0), + .tdf8_adjustments_q0(tdf8_adjustments_q0), + .tdf8_adjustments_we0(grp_td_fused_fu_1094_tdf8_adjustments_we0), + .tdf8_adjustments_address1(grp_td_fused_fu_1094_tdf8_adjustments_address1), + .tdf8_adjustments_ce1(grp_td_fused_fu_1094_tdf8_adjustments_ce1), + .tdf8_adjustments_d1(grp_td_fused_fu_1094_tdf8_adjustments_d1), + .tdf8_adjustments_q1(48'd0), + .tdf8_adjustments_we1(grp_td_fused_fu_1094_tdf8_adjustments_we1), + .tdf9_adjustments_address0(grp_td_fused_fu_1094_tdf9_adjustments_address0), + .tdf9_adjustments_ce0(grp_td_fused_fu_1094_tdf9_adjustments_ce0), + .tdf9_adjustments_d0(grp_td_fused_fu_1094_tdf9_adjustments_d0), + .tdf9_adjustments_q0(tdf9_adjustments_q0), + .tdf9_adjustments_we0(grp_td_fused_fu_1094_tdf9_adjustments_we0), + .tdf9_adjustments_address1(grp_td_fused_fu_1094_tdf9_adjustments_address1), + .tdf9_adjustments_ce1(grp_td_fused_fu_1094_tdf9_adjustments_ce1), + .tdf9_adjustments_d1(grp_td_fused_fu_1094_tdf9_adjustments_d1), + .tdf9_adjustments_q1(48'd0), + .tdf9_adjustments_we1(grp_td_fused_fu_1094_tdf9_adjustments_we1), + .tdf10_adjustments_address0(grp_td_fused_fu_1094_tdf10_adjustments_address0), + .tdf10_adjustments_ce0(grp_td_fused_fu_1094_tdf10_adjustments_ce0), + .tdf10_adjustments_d0(grp_td_fused_fu_1094_tdf10_adjustments_d0), + .tdf10_adjustments_q0(tdf10_adjustments_q0), + .tdf10_adjustments_we0(grp_td_fused_fu_1094_tdf10_adjustments_we0), + .tdf10_adjustments_address1(grp_td_fused_fu_1094_tdf10_adjustments_address1), + .tdf10_adjustments_ce1(grp_td_fused_fu_1094_tdf10_adjustments_ce1), + .tdf10_adjustments_d1(grp_td_fused_fu_1094_tdf10_adjustments_d1), + .tdf10_adjustments_q1(48'd0), + .tdf10_adjustments_we1(grp_td_fused_fu_1094_tdf10_adjustments_we1), + .tdf10_l2_adjustments_address0(grp_td_fused_fu_1094_tdf10_l2_adjustments_address0), + .tdf10_l2_adjustments_ce0(grp_td_fused_fu_1094_tdf10_l2_adjustments_ce0), + .tdf10_l2_adjustments_d0(grp_td_fused_fu_1094_tdf10_l2_adjustments_d0), + .tdf10_l2_adjustments_q0(tdf10_l2_adjustments_q0), + .tdf10_l2_adjustments_we0(grp_td_fused_fu_1094_tdf10_l2_adjustments_we0), + .tdf10_l2_adjustments_address1(grp_td_fused_fu_1094_tdf10_l2_adjustments_address1), + .tdf10_l2_adjustments_ce1(grp_td_fused_fu_1094_tdf10_l2_adjustments_ce1), + .tdf10_l2_adjustments_d1(grp_td_fused_fu_1094_tdf10_l2_adjustments_d1), + .tdf10_l2_adjustments_q1(48'd0), + .tdf10_l2_adjustments_we1(grp_td_fused_fu_1094_tdf10_l2_adjustments_we1), + .tdf11_adjustments_address0(grp_td_fused_fu_1094_tdf11_adjustments_address0), + .tdf11_adjustments_ce0(grp_td_fused_fu_1094_tdf11_adjustments_ce0), + .tdf11_adjustments_d0(grp_td_fused_fu_1094_tdf11_adjustments_d0), + .tdf11_adjustments_q0(tdf11_adjustments_q0), + .tdf11_adjustments_we0(grp_td_fused_fu_1094_tdf11_adjustments_we0), + .tdf11_adjustments_address1(grp_td_fused_fu_1094_tdf11_adjustments_address1), + .tdf11_adjustments_ce1(grp_td_fused_fu_1094_tdf11_adjustments_ce1), + .tdf11_adjustments_d1(grp_td_fused_fu_1094_tdf11_adjustments_d1), + .tdf11_adjustments_q1(48'd0), + .tdf11_adjustments_we1(grp_td_fused_fu_1094_tdf11_adjustments_we1), + .tdf11_l2_adjustments_address0(grp_td_fused_fu_1094_tdf11_l2_adjustments_address0), + .tdf11_l2_adjustments_ce0(grp_td_fused_fu_1094_tdf11_l2_adjustments_ce0), + .tdf11_l2_adjustments_d0(grp_td_fused_fu_1094_tdf11_l2_adjustments_d0), + .tdf11_l2_adjustments_q0(tdf11_l2_adjustments_q0), + .tdf11_l2_adjustments_we0(grp_td_fused_fu_1094_tdf11_l2_adjustments_we0), + .tdf11_l2_adjustments_address1(grp_td_fused_fu_1094_tdf11_l2_adjustments_address1), + .tdf11_l2_adjustments_ce1(grp_td_fused_fu_1094_tdf11_l2_adjustments_ce1), + .tdf11_l2_adjustments_d1(grp_td_fused_fu_1094_tdf11_l2_adjustments_d1), + .tdf11_l2_adjustments_q1(48'd0), + .tdf11_l2_adjustments_we1(grp_td_fused_fu_1094_tdf11_l2_adjustments_we1), + .tdf12_adjustments_address0(grp_td_fused_fu_1094_tdf12_adjustments_address0), + .tdf12_adjustments_ce0(grp_td_fused_fu_1094_tdf12_adjustments_ce0), + .tdf12_adjustments_d0(grp_td_fused_fu_1094_tdf12_adjustments_d0), + .tdf12_adjustments_q0(tdf12_adjustments_q0), + .tdf12_adjustments_we0(grp_td_fused_fu_1094_tdf12_adjustments_we0), + .tdf12_adjustments_address1(grp_td_fused_fu_1094_tdf12_adjustments_address1), + .tdf12_adjustments_ce1(grp_td_fused_fu_1094_tdf12_adjustments_ce1), + .tdf12_adjustments_d1(grp_td_fused_fu_1094_tdf12_adjustments_d1), + .tdf12_adjustments_q1(48'd0), + .tdf12_adjustments_we1(grp_td_fused_fu_1094_tdf12_adjustments_we1), + .stream_in_TDATA(stream_in_TDATA_int_regslice), + .stream_in_TKEEP(stream_in_TKEEP_int_regslice), + .stream_in_TSTRB(stream_in_TSTRB_int_regslice), + .stream_in_TLAST(stream_in_TLAST_int_regslice), + .stream_out_TDATA(grp_td_fused_fu_1094_stream_out_TDATA), + .stream_out_TKEEP(grp_td_fused_fu_1094_stream_out_TKEEP), + .stream_out_TSTRB(grp_td_fused_fu_1094_stream_out_TSTRB), + .stream_out_TLAST(grp_td_fused_fu_1094_stream_out_TLAST), + .stream_in_TVALID(stream_in_TVALID_int_regslice), + .stream_in_TREADY(grp_td_fused_fu_1094_stream_in_TREADY), + .ap_start(grp_td_fused_fu_1094_ap_start), + .stream_out_TVALID(grp_td_fused_fu_1094_stream_out_TVALID), + .stream_out_TREADY(grp_td_fused_fu_1094_stream_out_TREADY), + .ap_done(grp_td_fused_fu_1094_ap_done), + .ap_ready(grp_td_fused_fu_1094_ap_ready), + .ap_idle(grp_td_fused_fu_1094_ap_idle), + .ap_continue(grp_td_fused_fu_1094_ap_continue) +); + +td_fused_top_regslice_both #( + .DataWidth( 16 )) +regslice_both_stream_in_V_data_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(stream_in_TDATA), + .vld_in(stream_in_TVALID), + .ack_in(regslice_both_stream_in_V_data_V_U_ack_in), + .data_out(stream_in_TDATA_int_regslice), + .vld_out(stream_in_TVALID_int_regslice), + .ack_out(stream_in_TREADY_int_regslice), + .apdone_blk(regslice_both_stream_in_V_data_V_U_apdone_blk) +); + +td_fused_top_regslice_both #( + .DataWidth( 2 )) +regslice_both_stream_in_V_keep_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(stream_in_TKEEP), + .vld_in(stream_in_TVALID), + .ack_in(regslice_both_stream_in_V_keep_V_U_ack_in), + .data_out(stream_in_TKEEP_int_regslice), + .vld_out(regslice_both_stream_in_V_keep_V_U_vld_out), + .ack_out(stream_in_TREADY_int_regslice), + .apdone_blk(regslice_both_stream_in_V_keep_V_U_apdone_blk) +); + +td_fused_top_regslice_both #( + .DataWidth( 2 )) +regslice_both_stream_in_V_strb_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(stream_in_TSTRB), + .vld_in(stream_in_TVALID), + .ack_in(regslice_both_stream_in_V_strb_V_U_ack_in), + .data_out(stream_in_TSTRB_int_regslice), + .vld_out(regslice_both_stream_in_V_strb_V_U_vld_out), + .ack_out(stream_in_TREADY_int_regslice), + .apdone_blk(regslice_both_stream_in_V_strb_V_U_apdone_blk) +); + +td_fused_top_regslice_both #( + .DataWidth( 1 )) +regslice_both_stream_in_V_last_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(stream_in_TLAST), + .vld_in(stream_in_TVALID), + .ack_in(regslice_both_stream_in_V_last_V_U_ack_in), + .data_out(stream_in_TLAST_int_regslice), + .vld_out(regslice_both_stream_in_V_last_V_U_vld_out), + .ack_out(stream_in_TREADY_int_regslice), + .apdone_blk(regslice_both_stream_in_V_last_V_U_apdone_blk) +); + +td_fused_top_regslice_both #( + .DataWidth( 16 )) +regslice_both_stream_out_V_data_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(grp_td_fused_fu_1094_stream_out_TDATA), + .vld_in(grp_td_fused_fu_1094_stream_out_TVALID), + .ack_in(stream_out_TREADY_int_regslice), + .data_out(stream_out_TDATA), + .vld_out(regslice_both_stream_out_V_data_V_U_vld_out), + .ack_out(stream_out_TREADY), + .apdone_blk(regslice_both_stream_out_V_data_V_U_apdone_blk) +); + +td_fused_top_regslice_both #( + .DataWidth( 2 )) +regslice_both_stream_out_V_keep_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(grp_td_fused_fu_1094_stream_out_TKEEP), + .vld_in(grp_td_fused_fu_1094_stream_out_TVALID), + .ack_in(regslice_both_stream_out_V_keep_V_U_ack_in_dummy), + .data_out(stream_out_TKEEP), + .vld_out(regslice_both_stream_out_V_keep_V_U_vld_out), + .ack_out(stream_out_TREADY), + .apdone_blk(regslice_both_stream_out_V_keep_V_U_apdone_blk) +); + +td_fused_top_regslice_both #( + .DataWidth( 2 )) +regslice_both_stream_out_V_strb_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(grp_td_fused_fu_1094_stream_out_TSTRB), + .vld_in(grp_td_fused_fu_1094_stream_out_TVALID), + .ack_in(regslice_both_stream_out_V_strb_V_U_ack_in_dummy), + .data_out(stream_out_TSTRB), + .vld_out(regslice_both_stream_out_V_strb_V_U_vld_out), + .ack_out(stream_out_TREADY), + .apdone_blk(regslice_both_stream_out_V_strb_V_U_apdone_blk) +); + +td_fused_top_regslice_both #( + .DataWidth( 1 )) +regslice_both_stream_out_V_last_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(grp_td_fused_fu_1094_stream_out_TLAST), + .vld_in(grp_td_fused_fu_1094_stream_out_TVALID), + .ack_in(regslice_both_stream_out_V_last_V_U_ack_in_dummy), + .data_out(stream_out_TLAST), + .vld_out(regslice_both_stream_out_V_last_V_U_vld_out), + .ack_out(stream_out_TREADY), + .apdone_blk(regslice_both_stream_out_V_last_V_U_apdone_blk) +); + +always @ (posedge ap_clk) begin + if (ap_rst_n_inv == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst_n_inv == 1'b1) begin + ap_sync_reg_grp_td_fused_fu_1094_ap_done <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_state3) & (1'b0 == ap_block_state3_on_subcall_done))) begin + ap_sync_reg_grp_td_fused_fu_1094_ap_done <= 1'b0; + end else if ((grp_td_fused_fu_1094_ap_done == 1'b1)) begin + ap_sync_reg_grp_td_fused_fu_1094_ap_done <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst_n_inv == 1'b1) begin + ap_sync_reg_grp_td_fused_fu_1094_ap_ready <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_state3) & (1'b0 == ap_block_state3_on_subcall_done))) begin + ap_sync_reg_grp_td_fused_fu_1094_ap_ready <= 1'b0; + end else if ((grp_td_fused_fu_1094_ap_ready == 1'b1)) begin + ap_sync_reg_grp_td_fused_fu_1094_ap_ready <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst_n_inv == 1'b1) begin + grp_td_fused_fu_1094_ap_start_reg <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state3) & (ap_sync_grp_td_fused_fu_1094_ap_ready == 1'b0)))) begin + grp_td_fused_fu_1094_ap_start_reg <= 1'b1; + end else if ((grp_td_fused_fu_1094_ap_ready == 1'b1)) begin + grp_td_fused_fu_1094_ap_start_reg <= 1'b0; + end + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) & (regslice_both_stream_out_V_data_V_U_apdone_blk == 1'b0))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) & (regslice_both_stream_out_V_data_V_U_apdone_blk == 1'b0))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) & (1'b0 == ap_block_state3_on_subcall_done))) begin + grp_td_fused_fu_1094_ap_continue = 1'b1; + end else begin + grp_td_fused_fu_1094_ap_continue = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (stream_in_TVALID_int_regslice == 1'b1) & (ap_start == 1'b1))) begin + stream_in_TREADY_int_regslice = 1'b1; + end else if ((1'b1 == ap_CS_fsm_state3)) begin + stream_in_TREADY_int_regslice = grp_td_fused_fu_1094_stream_in_TREADY; + end else begin + stream_in_TREADY_int_regslice = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf10_adjustments_ce0 = grp_td_fused_fu_1094_tdf10_adjustments_ce0; + end else begin + tdf10_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf10_adjustments_ce1 = 1'b1; + end else begin + tdf10_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf10_adjustments_we1 = 1'b1; + end else begin + tdf10_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf10_filters_0_ce0 = grp_td_fused_fu_1094_tdf10_filters_0_ce0; + end else begin + tdf10_filters_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf10_filters_0_ce1 = 1'b1; + end else begin + tdf10_filters_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf10_filters_0_we1 = 1'b1; + end else begin + tdf10_filters_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf10_l2_adjustments_ce0 = grp_td_fused_fu_1094_tdf10_l2_adjustments_ce0; + end else begin + tdf10_l2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf10_l2_adjustments_ce1 = 1'b1; + end else begin + tdf10_l2_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf10_l2_adjustments_we1 = 1'b1; + end else begin + tdf10_l2_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + tdf10_l2_filters_0_address1 = 64'd0; + end else if ((1'b1 == ap_CS_fsm_state3)) begin + tdf10_l2_filters_0_address1 = grp_td_fused_fu_1094_tdf10_l2_filters_0_address1; + end else begin + tdf10_l2_filters_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf10_l2_filters_0_ce0 = grp_td_fused_fu_1094_tdf10_l2_filters_0_ce0; + end else begin + tdf10_l2_filters_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf10_l2_filters_0_ce1 = 1'b1; + end else if ((1'b1 == ap_CS_fsm_state3)) begin + tdf10_l2_filters_0_ce1 = grp_td_fused_fu_1094_tdf10_l2_filters_0_ce1; + end else begin + tdf10_l2_filters_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf10_l2_filters_0_we1 = 1'b1; + end else begin + tdf10_l2_filters_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf11_adjustments_ce0 = grp_td_fused_fu_1094_tdf11_adjustments_ce0; + end else begin + tdf11_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf11_adjustments_ce1 = 1'b1; + end else begin + tdf11_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf11_adjustments_we1 = 1'b1; + end else begin + tdf11_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf11_filters_0_ce0 = grp_td_fused_fu_1094_tdf11_filters_0_ce0; + end else begin + tdf11_filters_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf11_filters_0_ce1 = 1'b1; + end else begin + tdf11_filters_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf11_filters_0_we1 = 1'b1; + end else begin + tdf11_filters_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf11_l2_adjustments_ce0 = grp_td_fused_fu_1094_tdf11_l2_adjustments_ce0; + end else begin + tdf11_l2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf11_l2_adjustments_ce1 = 1'b1; + end else begin + tdf11_l2_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf11_l2_adjustments_we1 = 1'b1; + end else begin + tdf11_l2_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + tdf11_l2_filters_0_address1 = 64'd0; + end else if ((1'b1 == ap_CS_fsm_state3)) begin + tdf11_l2_filters_0_address1 = grp_td_fused_fu_1094_tdf11_l2_filters_0_address1; + end else begin + tdf11_l2_filters_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf11_l2_filters_0_ce0 = grp_td_fused_fu_1094_tdf11_l2_filters_0_ce0; + end else begin + tdf11_l2_filters_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf11_l2_filters_0_ce1 = 1'b1; + end else if ((1'b1 == ap_CS_fsm_state3)) begin + tdf11_l2_filters_0_ce1 = grp_td_fused_fu_1094_tdf11_l2_filters_0_ce1; + end else begin + tdf11_l2_filters_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf11_l2_filters_0_we1 = 1'b1; + end else begin + tdf11_l2_filters_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf12_adjustments_ce0 = grp_td_fused_fu_1094_tdf12_adjustments_ce0; + end else begin + tdf12_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf12_adjustments_ce1 = 1'b1; + end else begin + tdf12_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf12_adjustments_we1 = 1'b1; + end else begin + tdf12_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf12_filters_0_ce0 = grp_td_fused_fu_1094_tdf12_filters_0_ce0; + end else begin + tdf12_filters_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf12_filters_0_ce1 = 1'b1; + end else begin + tdf12_filters_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf12_filters_0_we1 = 1'b1; + end else begin + tdf12_filters_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf1_adjustments_ce0 = grp_td_fused_fu_1094_tdf1_adjustments_ce0; + end else begin + tdf1_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf1_adjustments_ce1 = 1'b1; + end else begin + tdf1_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf1_adjustments_we1 = 1'b1; + end else begin + tdf1_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf1_filters_0_ce0 = grp_td_fused_fu_1094_tdf1_filters_0_ce0; + end else begin + tdf1_filters_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf1_filters_0_ce1 = 1'b1; + end else begin + tdf1_filters_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf1_filters_0_we1 = 1'b1; + end else begin + tdf1_filters_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf2_adjustments_ce0 = grp_td_fused_fu_1094_tdf2_adjustments_ce0; + end else begin + tdf2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf2_adjustments_ce1 = 1'b1; + end else begin + tdf2_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf2_adjustments_we1 = 1'b1; + end else begin + tdf2_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf2_filters_0_ce0 = grp_td_fused_fu_1094_tdf2_filters_0_ce0; + end else begin + tdf2_filters_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf2_filters_0_ce1 = 1'b1; + end else begin + tdf2_filters_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf2_filters_0_we1 = 1'b1; + end else begin + tdf2_filters_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf3_adjustments_ce0 = grp_td_fused_fu_1094_tdf3_adjustments_ce0; + end else begin + tdf3_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf3_adjustments_ce1 = 1'b1; + end else begin + tdf3_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf3_adjustments_we1 = 1'b1; + end else begin + tdf3_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf3_filters_ce0 = grp_td_fused_fu_1094_tdf3_filters_ce0; + end else begin + tdf3_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf3_filters_ce1 = 1'b1; + end else begin + tdf3_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf3_filters_we1 = 1'b1; + end else begin + tdf3_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf4_adjustments_ce0 = grp_td_fused_fu_1094_tdf4_adjustments_ce0; + end else begin + tdf4_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf4_adjustments_ce1 = 1'b1; + end else begin + tdf4_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf4_adjustments_we1 = 1'b1; + end else begin + tdf4_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf4_filters_0_ce0 = grp_td_fused_fu_1094_tdf4_filters_0_ce0; + end else begin + tdf4_filters_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf4_filters_0_ce1 = 1'b1; + end else begin + tdf4_filters_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf4_filters_0_we1 = 1'b1; + end else begin + tdf4_filters_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf4_l2_adjustments_ce0 = grp_td_fused_fu_1094_tdf4_l2_adjustments_ce0; + end else begin + tdf4_l2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf4_l2_adjustments_ce1 = 1'b1; + end else begin + tdf4_l2_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf4_l2_adjustments_we1 = 1'b1; + end else begin + tdf4_l2_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + tdf4_l2_filters_0_address1 = 64'd0; + end else if ((1'b1 == ap_CS_fsm_state3)) begin + tdf4_l2_filters_0_address1 = grp_td_fused_fu_1094_tdf4_l2_filters_0_address1; + end else begin + tdf4_l2_filters_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf4_l2_filters_0_ce0 = grp_td_fused_fu_1094_tdf4_l2_filters_0_ce0; + end else begin + tdf4_l2_filters_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf4_l2_filters_0_ce1 = 1'b1; + end else if ((1'b1 == ap_CS_fsm_state3)) begin + tdf4_l2_filters_0_ce1 = grp_td_fused_fu_1094_tdf4_l2_filters_0_ce1; + end else begin + tdf4_l2_filters_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf4_l2_filters_0_we1 = 1'b1; + end else begin + tdf4_l2_filters_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf5_adjustments_ce0 = grp_td_fused_fu_1094_tdf5_adjustments_ce0; + end else begin + tdf5_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf5_adjustments_ce1 = 1'b1; + end else begin + tdf5_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf5_adjustments_we1 = 1'b1; + end else begin + tdf5_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf5_filters_0_ce0 = grp_td_fused_fu_1094_tdf5_filters_0_ce0; + end else begin + tdf5_filters_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf5_filters_0_ce1 = 1'b1; + end else begin + tdf5_filters_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf5_filters_0_we1 = 1'b1; + end else begin + tdf5_filters_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf6_adjustments_ce0 = grp_td_fused_fu_1094_tdf6_adjustments_ce0; + end else begin + tdf6_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf6_adjustments_ce1 = 1'b1; + end else begin + tdf6_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf6_adjustments_we1 = 1'b1; + end else begin + tdf6_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf6_filters_ce0 = grp_td_fused_fu_1094_tdf6_filters_ce0; + end else begin + tdf6_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf6_filters_ce1 = 1'b1; + end else begin + tdf6_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf6_filters_we1 = 1'b1; + end else begin + tdf6_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf7_adjustments_ce0 = grp_td_fused_fu_1094_tdf7_adjustments_ce0; + end else begin + tdf7_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf7_adjustments_ce1 = 1'b1; + end else begin + tdf7_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf7_adjustments_we1 = 1'b1; + end else begin + tdf7_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf7_filters_0_ce0 = grp_td_fused_fu_1094_tdf7_filters_0_ce0; + end else begin + tdf7_filters_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf7_filters_0_ce1 = 1'b1; + end else begin + tdf7_filters_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf7_filters_0_we1 = 1'b1; + end else begin + tdf7_filters_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf7_l2_adjustments_ce0 = grp_td_fused_fu_1094_tdf7_l2_adjustments_ce0; + end else begin + tdf7_l2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf7_l2_adjustments_ce1 = 1'b1; + end else begin + tdf7_l2_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf7_l2_adjustments_we1 = 1'b1; + end else begin + tdf7_l2_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + tdf7_l2_filters_0_address1 = 64'd0; + end else if ((1'b1 == ap_CS_fsm_state3)) begin + tdf7_l2_filters_0_address1 = grp_td_fused_fu_1094_tdf7_l2_filters_0_address1; + end else begin + tdf7_l2_filters_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf7_l2_filters_0_ce0 = grp_td_fused_fu_1094_tdf7_l2_filters_0_ce0; + end else begin + tdf7_l2_filters_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf7_l2_filters_0_ce1 = 1'b1; + end else if ((1'b1 == ap_CS_fsm_state3)) begin + tdf7_l2_filters_0_ce1 = grp_td_fused_fu_1094_tdf7_l2_filters_0_ce1; + end else begin + tdf7_l2_filters_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf7_l2_filters_0_we1 = 1'b1; + end else begin + tdf7_l2_filters_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf8_adjustments_ce0 = grp_td_fused_fu_1094_tdf8_adjustments_ce0; + end else begin + tdf8_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf8_adjustments_ce1 = 1'b1; + end else begin + tdf8_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf8_adjustments_we1 = 1'b1; + end else begin + tdf8_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf8_filters_0_ce0 = grp_td_fused_fu_1094_tdf8_filters_0_ce0; + end else begin + tdf8_filters_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf8_filters_0_ce1 = 1'b1; + end else begin + tdf8_filters_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf8_filters_0_we1 = 1'b1; + end else begin + tdf8_filters_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf9_adjustments_ce0 = grp_td_fused_fu_1094_tdf9_adjustments_ce0; + end else begin + tdf9_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf9_adjustments_ce1 = 1'b1; + end else begin + tdf9_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf9_adjustments_we1 = 1'b1; + end else begin + tdf9_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + tdf9_filters_ce0 = grp_td_fused_fu_1094_tdf9_filters_ce0; + end else begin + tdf9_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf9_filters_ce1 = 1'b1; + end else begin + tdf9_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf9_filters_we1 = 1'b1; + end else begin + tdf9_filters_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + if (((1'b1 == ap_CS_fsm_state3) & (1'b0 == ap_block_state3_on_subcall_done))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state4 : begin + if (((1'b1 == ap_CS_fsm_state4) & (regslice_both_stream_out_V_data_V_U_apdone_blk == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state3_on_subcall_done = ((ap_sync_grp_td_fused_fu_1094_ap_ready & ap_sync_grp_td_fused_fu_1094_ap_done) == 1'b0); +end + +always @ (*) begin + ap_rst_n_inv = ~ap_rst_n; +end + +assign ap_sync_grp_td_fused_fu_1094_ap_done = (grp_td_fused_fu_1094_ap_done | ap_sync_reg_grp_td_fused_fu_1094_ap_done); + +assign ap_sync_grp_td_fused_fu_1094_ap_ready = (grp_td_fused_fu_1094_ap_ready | ap_sync_reg_grp_td_fused_fu_1094_ap_ready); + +assign grp_td_fused_fu_1094_ap_start = grp_td_fused_fu_1094_ap_start_reg; + +assign grp_td_fused_fu_1094_stream_out_TREADY = (stream_out_TREADY_int_regslice & ap_CS_fsm_state3); + +assign stream_in_TREADY = regslice_both_stream_in_V_data_V_U_ack_in; + +assign stream_out_TVALID = regslice_both_stream_out_V_data_V_U_vld_out; + +assign tdf10_adjustments_address1 = 64'd0; + +assign tdf10_filters_0_address1 = 64'd0; + +assign tdf10_l2_adjustments_address1 = 64'd0; + +assign tdf11_adjustments_address1 = 64'd0; + +assign tdf11_filters_0_address1 = 64'd0; + +assign tdf11_l2_adjustments_address1 = 64'd0; + +assign tdf12_adjustments_address1 = 64'd0; + +assign tdf12_filters_0_address1 = 64'd0; + +assign tdf1_adjustments_address1 = 64'd0; + +assign tdf1_filters_0_address1 = 64'd0; + +assign tdf2_adjustments_address1 = 64'd0; + +assign tdf2_filters_0_address1 = 64'd0; + +assign tdf3_adjustments_address1 = 64'd0; + +assign tdf3_filters_address1 = 64'd0; + +assign tdf4_adjustments_address1 = 64'd0; + +assign tdf4_filters_0_address1 = 64'd0; + +assign tdf4_l2_adjustments_address1 = 64'd0; + +assign tdf5_adjustments_address1 = 64'd0; + +assign tdf5_filters_0_address1 = 64'd0; + +assign tdf6_adjustments_address1 = 64'd0; + +assign tdf6_filters_address1 = 64'd0; + +assign tdf7_adjustments_address1 = 64'd0; + +assign tdf7_filters_0_address1 = 64'd0; + +assign tdf7_l2_adjustments_address1 = 64'd0; + +assign tdf8_adjustments_address1 = 64'd0; + +assign tdf8_filters_0_address1 = 64'd0; + +assign tdf9_adjustments_address1 = 64'd0; + +assign tdf9_filters_address1 = 64'd0; + +assign tmp_data_fu_1373_p1 = stream_in_TDATA_int_regslice; + +assign tmp_fu_1385_p5 = {{ap_const_lv32_0[31:16]}, {stream_in_TDATA_int_regslice}}; + +assign tmp_s_fu_1401_p5 = {{ap_const_lv64_0[63:16]}, {stream_in_TDATA_int_regslice}}; + +assign trunc_ln143_fu_1417_p1 = tmp_s_fu_1401_p5[47:0]; + +endmodule //td_fused_top + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Floating point 16-bit multiplier +// This is a heavily modified version of: +// https://github.com/fbrosser/DSP48E1-FP/tree/master/src/FPMult +// Original author: Fredrik Brosser +// Abridged by: Samidh Mehta +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// + +`ifndef complex_dsp + +`define EXPONENT 5 +`define MANTISSA 10 +`define ACTUAL_MANTISSA 11 +`define EXPONENT_LSB 10 +`define EXPONENT_MSB 14 +`define MANTISSA_LSB 0 +`define MANTISSA_MSB 9 +`define MANTISSA_MUL_SPLIT_LSB 3 +`define MANTISSA_MUL_SPLIT_MSB 9 +`define SIGN 1 +`define SIGN_LOC 15 +`define DWIDTH (`SIGN+`EXPONENT+`MANTISSA) +`define IEEE_COMPLIANCE 1 + +module FPMult_16( + clk, + rst, + a, + b, + result, + flags + ); + + // Input Ports + input clk ; // Clock + input rst ; // Reset signal + input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number + + // Output ports + output [`DWIDTH-1:0] result ; // Product, result of the operation, 32-bit FP number + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Internal signals + wire [31:0] Z_int ; // Product, result of the operation, 32-bit FP number + wire [4:0] Flags_int ; // Flags indicating exceptions according to IEEE754 + + wire Sa ; // A's sign + wire Sb ; // B's sign + wire Sp ; // Product sign + wire [`EXPONENT-1:0] Ea ; // A's exponent + wire [`EXPONENT-1:0] Eb ; // B's exponent + wire [2*`MANTISSA+1:0] Mp ; // Product mantissa + wire [4:0] InputExc ; // Exceptions in inputs + wire [`MANTISSA-1:0] NormM ; // Normalized mantissa + wire [`EXPONENT:0] NormE ; // Normalized exponent + wire [`MANTISSA:0] RoundM ; // Normalized mantissa + wire [`EXPONENT:0] RoundE ; // Normalized exponent + wire [`MANTISSA:0] RoundMP ; // Normalized mantissa + wire [`EXPONENT:0] RoundEP ; // Normalized exponent + wire GRS ; + + //reg [63:0] pipe_0; // Pipeline register Input->Prep + reg [2*`DWIDTH-1:0] pipe_0; // Pipeline register Input->Prep + + //reg [92:0] pipe_1; // Pipeline register Prep->Execute + reg [3*`MANTISSA+2*`EXPONENT+7:0] pipe_1; // Pipeline register Prep->Execute + + //reg [38:0] pipe_2; // Pipeline register Execute->Normalize + reg [`MANTISSA+`EXPONENT+7:0] pipe_2; // Pipeline register Execute->Normalize + + //reg [72:0] pipe_3; // Pipeline register Normalize->Round + reg [2*`MANTISSA+2*`EXPONENT+10:0] pipe_3; // Pipeline register Normalize->Round + + //reg [36:0] pipe_4; // Pipeline register Round->Output + reg [`DWIDTH+4:0] pipe_4; // Pipeline register Round->Output + + assign result = pipe_4[`DWIDTH+4:5] ; + assign flags = pipe_4[4:0] ; + + // Prepare the operands for alignment and check for exceptions + FPMult_PrepModule PrepModule(clk, rst, pipe_0[2*`DWIDTH-1:`DWIDTH], pipe_0[`DWIDTH-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]) ; + + // Perform (unsigned) mantissa multiplication + FPMult_ExecuteModule ExecuteModule(pipe_1[3*`MANTISSA+`EXPONENT*2+7:2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7:2*`MANTISSA+7], pipe_1[2*`MANTISSA+6:5], pipe_1[2*`MANTISSA+2*`EXPONENT+6:2*`MANTISSA+`EXPONENT+7], pipe_1[2*`MANTISSA+`EXPONENT+6:2*`MANTISSA+7], pipe_1[2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7], Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0], GRS) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + FPMult_NormalizeModule NormalizeModule(pipe_2[`MANTISSA-1:0], pipe_2[`MANTISSA+`EXPONENT:`MANTISSA], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + //FPMult_RoundModule RoundModule(pipe_3[47:24], pipe_3[23:0], pipe_3[65:57], pipe_3[56:48], pipe_3[66], pipe_3[67], pipe_3[72:68], Z_int[31:0], Flags_int[4:0]) ; + FPMult_RoundModule RoundModule(pipe_3[2*`MANTISSA+1:`MANTISSA+1], pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+2*`EXPONENT+3:2*`MANTISSA+`EXPONENT+3], pipe_3[2*`MANTISSA+`EXPONENT+2:2*`MANTISSA+2], pipe_3[2*`MANTISSA+2*`EXPONENT+4], pipe_3[2*`MANTISSA+2*`EXPONENT+5], pipe_3[2*`MANTISSA+2*`EXPONENT+10:2*`MANTISSA+2*`EXPONENT+6], Z_int[`DWIDTH-1:0], Flags_int[4:0]) ; + + always @ (*) begin + if(rst) begin + pipe_0 = 0; + pipe_1 = 0; + pipe_2 = 0; + pipe_3 = 0; + pipe_4 = 0; + end + else begin + /* PIPE 0 + [63:32] A + [31:0] B + */ + pipe_0 = {a, b} ; + + /* PIPE 1 + [70] Sa + [69] Sb + [68:61] Ea + [60:53] Eb + [52:5] Mp + [4:0] InputExc + */ + //pipe_1 <= {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[`MANTISSA_MUL_SPLIT_LSB-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA-1:0], InputExc[4:0]} ; + pipe_1 = {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[8:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]} ; + /* PIPE 2 + [38:34] InputExc + [33] GRS + [32] Sp + [31:23] NormE + [22:0] NormM + */ + pipe_2 = {pipe_1[4:0], GRS, Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0]} ; + /* PIPE 3 + [72:68] InputExc + [67] GRS + [66] Sp + [65:57] RoundE + [56:48] RoundEP + [47:24] RoundM + [23:0] RoundMP + */ + pipe_3 = {pipe_2[`EXPONENT+`MANTISSA+7:`EXPONENT+`MANTISSA+1], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]} ; + /* PIPE 4 + [36:5] Z + [4:0] Flags + */ + pipe_4 = {Z_int[`DWIDTH-1:0], Flags_int[4:0]} ; + end + end + +endmodule + + +module FPMult_PrepModule ( + clk, + rst, + a, + b, + Sa, + Sb, + Ea, + Eb, + Mp, + InputExc + ); + + // Input ports + input clk ; + input rst ; + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [`EXPONENT-1:0] Ea ; // A's exponent + output [`EXPONENT-1:0] Eb ; // B's exponent + output [2*`MANTISSA+1:0] Mp ; // Mantissa product + output [4:0] InputExc ; // Input numbers are exceptions + + // Internal signals // If signal is high... + wire ANaN ; // A is a signalling NaN + wire BNaN ; // B is a signalling NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`MANTISSA-1:0] Ma; + wire [`MANTISSA-1:0] Mb; + + assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + + // Check for any exceptions and put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + //assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ; + + // Take input numbers apart + assign Sa = a[`DWIDTH-1] ; // A's sign + assign Sb = b[`DWIDTH-1] ; // B's sign + assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception + assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception +// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB]; + // assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB]; + + + + //assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ; + assign Mp = ({1'b1,a[`MANTISSA-1:0]}*{1'b1, b[`MANTISSA-1:0]}) ; + + + //We multiply part of the mantissa here + //Full mantissa of A + //Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B + // wire [`ACTUAL_MANTISSA-1:0] inp_A; + // wire [`ACTUAL_MANTISSA-1:0] inp_B; + // assign inp_A = {1'b1, Ma}; + // assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp)); +endmodule + + +module FPMult_ExecuteModule( + a, + b, + MpC, + Ea, + Eb, + Sa, + Sb, + Sp, + NormE, + NormM, + GRS + ); + + // Input ports + input [`MANTISSA-1:0] a ; + input [2*`EXPONENT:0] b ; + input [2*`MANTISSA+1:0] MpC ; + input [`EXPONENT-1:0] Ea ; // A's exponent + input [`EXPONENT-1:0] Eb ; // B's exponent + input Sa ; // A's sign + input Sb ; // B's sign + + // Output ports + output Sp ; // Product sign + output [`EXPONENT:0] NormE ; // Normalized exponent + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output GRS ; + + wire [2*`MANTISSA+1:0] Mp ; + + assign Sp = (Sa ^ Sb) ; // Equal signs give a positive product + + // wire [`ACTUAL_MANTISSA-1:0] inp_a; + // wire [`ACTUAL_MANTISSA-1:0] inp_b; + // assign inp_a = {1'b1, a}; + // assign inp_b = {{(`MANTISSA-`MANTISSA_MUL_SPLIT_LSB){1'b0}}, 1'b0, b}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_a), .B(inp_b), .TC(1'b0), .PRODUCT(Mp_temp)); + // DW01_add #(2*`ACTUAL_MANTISSA) u_add(.A(Mp_temp), .B(MpC<<`MANTISSA_MUL_SPLIT_LSB), .CI(1'b0), .SUM(Mp), .CO()); + + //assign Mp = (MpC<<(2*`EXPONENT+1)) + ({4'b0001, a[`MANTISSA-1:0]}*{1'b0, b[2*`EXPONENT:0]}) ; + assign Mp = MpC; + + + assign NormM = (Mp[2*`MANTISSA+1] ? Mp[2*`MANTISSA:`MANTISSA+1] : Mp[2*`MANTISSA-1:`MANTISSA]); // Check for overflow + assign NormE = (Ea + Eb + Mp[2*`MANTISSA+1]); // If so, increment exponent + + assign GRS = ((Mp[`MANTISSA]&(Mp[`MANTISSA+1]))|(|Mp[`MANTISSA-1:0])) ; + +endmodule + +module FPMult_NormalizeModule( + NormM, + NormE, + RoundE, + RoundEP, + RoundM, + RoundMP + ); + + // Input Ports + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input [`EXPONENT:0] NormE ; // Normalized exponent + + // Output Ports + output [`EXPONENT:0] RoundE ; + output [`EXPONENT:0] RoundEP ; + output [`MANTISSA:0] RoundM ; + output [`MANTISSA:0] RoundMP ; + + assign RoundE = NormE - 15 ; + assign RoundEP = NormE - 14 ; + assign RoundM = NormM ; + assign RoundMP = NormM ; + +endmodule + +module FPMult_RoundModule( + RoundM, + RoundMP, + RoundE, + RoundEP, + Sp, + GRS, + InputExc, + Z, + Flags + ); + + // Input Ports + input [`MANTISSA:0] RoundM ; // Normalized mantissa + input [`MANTISSA:0] RoundMP ; // Normalized exponent + input [`EXPONENT:0] RoundE ; // Normalized mantissa + 1 + input [`EXPONENT:0] RoundEP ; // Normalized exponent + 1 + input Sp ; // Product sign + input GRS ; + input [4:0] InputExc ; + + // Output Ports + output [`DWIDTH-1:0] Z ; // Final product + output [4:0] Flags ; + + // Internal Signals + wire [`EXPONENT:0] FinalE ; // Rounded exponent + wire [`MANTISSA:0] FinalM; + wire [`MANTISSA:0] PreShiftM; + + assign PreShiftM = GRS ? RoundMP : RoundM ; // Round up if R and (G or S) + + // Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow) + assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]) ; + + assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done + + assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]} ; // Putting the pieces together + assign Flags = InputExc[4:0]; + +endmodule + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Definition of a 16-bit floating point adder/subtractor +// This is a heavily modified version of: +// https://github.com/fbrosser/DSP48E1-FP/tree/master/src/FP_AddSub +// Original author: Fredrik Brosser +// Abridged by: Samidh Mehta +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// + +module FPAddSub( + clk, + rst, + a, + b, + operation, // 0 add, 1 sub + result, + flags + ); + + // Clock and reset + input clk ; // Clock signal + input rst ; // Reset (active high, resets pipeline registers) + + // Input ports + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + input operation ; // Operation select signal + + // Output ports + output [`DWIDTH-1:0] result ; // Result of the operation + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Pipeline Registers + //reg [79:0] pipe_1; // Pipeline register PreAlign->Align1 + reg [`DWIDTH*2+15:0] pipe_1; // Pipeline register PreAlign->Align1 + + //reg [67:0] pipe_2; // Pipeline register Align1->Align3 + reg [`MANTISSA*2+`EXPONENT+13:0] pipe_2; // Pipeline register Align1->Align3 + + //reg [76:0] pipe_3; 68 // Pipeline register Align1->Align3 + reg [`MANTISSA*2+`EXPONENT+14:0] pipe_3; // Pipeline register Align1->Align3 + + //reg [69:0] pipe_4; // Pipeline register Align3->Execute + reg [`MANTISSA*2+`EXPONENT+15:0] pipe_4; // Pipeline register Align3->Execute + + //reg [51:0] pipe_5; // Pipeline register Execute->Normalize + reg [`DWIDTH+`EXPONENT+11:0] pipe_5; // Pipeline register Execute->Normalize + + //reg [56:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + reg [`DWIDTH+`EXPONENT+16:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + + //reg [56:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + reg [`DWIDTH+`EXPONENT+16:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + + //reg [54:0] pipe_8; // Pipeline register NormalizeShift3->Round + reg [`EXPONENT*2+`MANTISSA+15:0] pipe_8; // Pipeline register NormalizeShift3->Round + + //reg [40:0] pipe_9; // Pipeline register NormalizeShift3->Round + reg [`DWIDTH+8:0] pipe_9; // Pipeline register NormalizeShift3->Round + + // Internal wires between modules + wire [`DWIDTH-2:0] Aout_0 ; // A - sign + wire [`DWIDTH-2:0] Bout_0 ; // B - sign + wire Opout_0 ; // A's sign + wire Sa_0 ; // A's sign + wire Sb_0 ; // B's sign + wire MaxAB_1 ; // Indicates the larger of A and B(0/A, 1/B) + wire [`EXPONENT-1:0] CExp_1 ; // Common Exponent + wire [4:0] Shift_1 ; // Number of steps to smaller mantissa shift right (align) + wire [`MANTISSA-1:0] Mmax_1 ; // Larger mantissa + wire [4:0] InputExc_0 ; // Input numbers are exceptions + wire [9:0] ShiftDet_0 ; + wire [`MANTISSA-1:0] MminS_1 ; // Smaller mantissa after 0/16 shift + wire [`MANTISSA:0] MminS_2 ; // Smaller mantissa after 0/4/8/12 shift + wire [`MANTISSA:0] Mmin_3 ; // Smaller mantissa after 0/1/2/3 shift + wire [`DWIDTH:0] Sum_4 ; + wire PSgn_4 ; + wire Opr_4 ; + wire [4:0] Shift_5 ; // Number of steps to shift sum left (normalize) + wire [`DWIDTH:0] SumS_5 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_6 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_7 ; // Sum after 0/16 shift + wire [`MANTISSA-1:0] NormM_8 ; // Normalized mantissa + wire [`EXPONENT:0] NormE_8; // Adjusted exponent + wire ZeroSum_8 ; // Zero flag + wire NegE_8 ; // Flag indicating negative exponent + wire R_8 ; // Round bit + wire S_8 ; // Final sticky bit + wire FG_8 ; // Final sticky bit + wire [`DWIDTH-1:0] P_int ; + wire EOF ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_PrealignModule PrealignModule + ( // Inputs + a, b, operation, + // Outputs + Sa_0, Sb_0, ShiftDet_0[9:0], InputExc_0[4:0], Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Opout_0) ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_AlignModule AlignModule + ( // Inputs + pipe_1[14+2*`DWIDTH:16+`DWIDTH], pipe_1[15+`DWIDTH:17], pipe_1[14:5], + // Outputs + CExp_1[`EXPONENT-1:0], MaxAB_1, Shift_1[4:0], MminS_1[`MANTISSA-1:0], Mmax_1[`MANTISSA-1:0]) ; + + // Alignment Shift Stage 1 + FPAddSub_AlignShift1 AlignShift1 + ( // Inputs + pipe_2[`MANTISSA-1:0], pipe_2[2*`MANTISSA+9:2*`MANTISSA+7], + // Outputs + MminS_2[`MANTISSA:0]) ; + + // Alignment Shift Stage 3 and compution of guard and sticky bits + FPAddSub_AlignShift2 AlignShift2 + ( // Inputs + pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+7:2*`MANTISSA+6], + // Outputs + Mmin_3[`MANTISSA:0]) ; + + // Perform mantissa addition + FPAddSub_ExecutionModule ExecutionModule + ( // Inputs + pipe_4[`MANTISSA*2+5:`MANTISSA+6], pipe_4[`MANTISSA:0], pipe_4[`MANTISSA*2+`EXPONENT+13], pipe_4[`MANTISSA*2+`EXPONENT+12], pipe_4[`MANTISSA*2+`EXPONENT+11], pipe_4[`MANTISSA*2+`EXPONENT+14], + // Outputs + Sum_4[`DWIDTH:0], PSgn_4, Opr_4) ; + + // Prepare normalization of result + FPAddSub_NormalizeModule NormalizeModule + ( // Inputs + pipe_5[`DWIDTH:0], + // Outputs + SumS_5[`DWIDTH:0], Shift_5[4:0]) ; + + // Normalization Shift Stage 1 + FPAddSub_NormalizeShift1 NormalizeShift1 + ( // Inputs + pipe_6[`DWIDTH:0], pipe_6[`DWIDTH+`EXPONENT+14:`DWIDTH+`EXPONENT+11], + // Outputs + SumS_7[`DWIDTH:0]) ; + + // Normalization Shift Stage 3 and final guard, sticky and round bits + FPAddSub_NormalizeShift2 NormalizeShift2 + ( // Inputs + pipe_7[`DWIDTH:0], pipe_7[`DWIDTH+`EXPONENT+5:`DWIDTH+6], pipe_7[`DWIDTH+`EXPONENT+15:`DWIDTH+`EXPONENT+11], + // Outputs + NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8, FG_8) ; + + // Round and put result together + FPAddSub_RoundModule RoundModule + ( // Inputs + pipe_8[3], pipe_8[4+`EXPONENT:4], pipe_8[`EXPONENT+`MANTISSA+4:5+`EXPONENT], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT*2+`MANTISSA+15], pipe_8[`EXPONENT*2+`MANTISSA+12], pipe_8[`EXPONENT*2+`MANTISSA+11], pipe_8[`EXPONENT*2+`MANTISSA+14], pipe_8[`EXPONENT*2+`MANTISSA+10], + // Outputs + P_int[`DWIDTH-1:0], EOF) ; + + // Check for exceptions + FPAddSub_ExceptionModule Exceptionmodule + ( // Inputs + pipe_9[8+`DWIDTH:9], pipe_9[8], pipe_9[7], pipe_9[6], pipe_9[5:1], pipe_9[0], + // Outputs + result[`DWIDTH-1:0], flags[4:0]) ; + + always @ (*) begin + if(rst) begin + pipe_1 = 0; + pipe_2 = 0; + pipe_3 = 0; + pipe_4 = 0; + pipe_5 = 0; + pipe_6 = 0; + pipe_7 = 0; + pipe_8 = 0; + pipe_9 = 0; + end + else begin + + pipe_1 = {Opout_0, Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Sa_0, Sb_0, ShiftDet_0[9:0], InputExc_0[4:0]} ; + // PIPE_2 : + //[67] operation + //[66] Sa_0 + //[65] Sb_0 + //[64] MaxAB_0 + //[63:56] CExp_0 + //[55:51] Shift_0 + //[50:28] Mmax_0 + //[27:23] InputExc_0 + //[22:0] MminS_1 + // + pipe_2 = {pipe_1[`DWIDTH*2+15], pipe_1[16:15], MaxAB_1, CExp_1[`EXPONENT-1:0], Shift_1[4:0], Mmax_1[`MANTISSA-1:0], pipe_1[4:0], MminS_1[`MANTISSA-1:0]} ; + // PIPE_3 : + //[68] operation + //[67] Sa_0 + //[66] Sb_0 + //[65] MaxAB_0 + //[64:57] CExp_0 + //[56:52] Shift_0 + //[51:29] Mmax_0 + //[28:24] InputExc_0 + //[23:0] MminS_1 + // + pipe_3 = {pipe_2[`MANTISSA*2+`EXPONENT+13:`MANTISSA], MminS_2[`MANTISSA:0]} ; + // PIPE_4 : + //[68] operation + //[67] Sa_0 + //[66] Sb_0 + //[65] MaxAB_0 + //[64:57] CExp_0 + //[56:52] Shift_0 + //[51:29] Mmax_0 + //[28:24] InputExc_0 + //[23:0] Mmin_3 + // + pipe_4 = {pipe_3[`MANTISSA*2+`EXPONENT+14:`MANTISSA+1], Mmin_3[`MANTISSA:0]} ; + // PIPE_5 : + //[51] operation + //[50] PSgn_4 + //[49] Opr_4 + //[48] Sa_0 + //[47] Sb_0 + //[46] MaxAB_0 + //[45:38] CExp_0 + //[37:33] InputExc_0 + //[32:0] Sum_4 + // + pipe_5 = {pipe_4[2*`MANTISSA+`EXPONENT+14], PSgn_4, Opr_4, pipe_4[2*`MANTISSA+`EXPONENT+13:2*`MANTISSA+11], pipe_4[`MANTISSA+5:`MANTISSA+1], Sum_4[`DWIDTH:0]} ; + // PIPE_6 : + //[56] operation + //[55:51] Shift_5 + //[50] PSgn_4 + //[49] Opr_4 + //[48] Sa_0 + //[47] Sb_0 + //[46] MaxAB_0 + //[45:38] CExp_0 + //[37:33] InputExc_0 + //[32:0] Sum_4 + // + pipe_6 = {pipe_5[`EXPONENT+`EXPONENT+11], Shift_5[4:0], pipe_5[`DWIDTH+`EXPONENT+10:`DWIDTH+1], SumS_5[`DWIDTH:0]} ; + // pipe_7 : + //[56] operation + //[55:51] Shift_5 + //[50] PSgn_4 + //[49] Opr_4 + //[48] Sa_0 + //[47] Sb_0 + //[46] MaxAB_0 + //[45:38] CExp_0 + //[37:33] InputExc_0 + //[32:0] Sum_4 + // + pipe_7 = {pipe_6[`DWIDTH+`EXPONENT+16:`DWIDTH+1], SumS_7[`DWIDTH:0]} ; + // pipe_8: + //[54] FG_8 + //[53] operation + //[52] PSgn_4 + //[51] Sa_0 + //[50] Sb_0 + //[49] MaxAB_0 + //[48:41] CExp_0 + //[40:36] InputExc_8 + //[35:13] NormM_8 + //[12:4] NormE_8 + //[3] ZeroSum_8 + //[2] NegE_8 + //[1] R_8 + //[0] S_8 + // + pipe_8 = {FG_8, pipe_7[`DWIDTH+`EXPONENT+16], pipe_7[`DWIDTH+`EXPONENT+10], pipe_7[`DWIDTH+`EXPONENT+8:`DWIDTH+1], NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8} ; + // pipe_9: + //[40:9] P_int + //[8] NegE_8 + //[7] R_8 + //[6] S_8 + //[5:1] InputExc_8 + //[0] EOF + // + pipe_9 = {P_int[`DWIDTH-1:0], pipe_8[2], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT+`MANTISSA+9:`EXPONENT+`MANTISSA+5], EOF} ; + end + end + +endmodule + +// Description: The pre-alignment module is responsible for taking the inputs +// apart and checking the parts for exceptions. +// The exponent difference is also calculated in this module. + +module FPAddSub_PrealignModule( + A, + B, + operation, + Sa, + Sb, + ShiftDet, + InputExc, + Aout, + Bout, + Opout + ); + + // Input ports + input [`DWIDTH-1:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] B ; // Input B, a 32-bit floating point number + input operation ; + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [9:0] ShiftDet ; + output [4:0] InputExc ; // Input numbers are exceptions + output [`DWIDTH-2:0] Aout ; + output [`DWIDTH-2:0] Bout ; + output Opout ; + + // Internal signals // If signal is high... + wire ANaN ; // A is a NaN (Not-a-Number) + wire BNaN ; // B is a NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`EXPONENT-1:0] DAB ; // ExpA - ExpB + wire [`EXPONENT-1:0] DBA ; // ExpB - ExpA + + assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + + // Put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + + //assign DAB = (A[30:23] - B[30:23]) ; + //assign DBA = (B[30:23] - A[30:23]) ; + assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1) ; + assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1) ; + + assign Sa = A[`DWIDTH-1] ; // A's sign bit + assign Sb = B[`DWIDTH-1] ; // B's sign bit + assign ShiftDet = {DBA[4:0], DAB[4:0]} ; // Shift data + assign Opout = operation ; + assign Aout = A[`DWIDTH-2:0] ; + assign Bout = B[`DWIDTH-2:0] ; + +endmodule + +// Description: The alignment module determines the larger input operand and +// sets the mantissas, shift and common exponent accordingly. + +module FPAddSub_AlignModule ( + A, + B, + ShiftDet, + CExp, + MaxAB, + Shift, + Mmin, + Mmax + ); + + // Input ports + input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-2:0] B ; // Input B, a 32-bit floating point number + input [9:0] ShiftDet ; + + // Output ports + output [`EXPONENT-1:0] CExp ; // Common Exponent + output MaxAB ; // Incidates larger of A and B (0/A, 1/B) + output [4:0] Shift ; // Number of steps to smaller mantissa shift right + output [`MANTISSA-1:0] Mmin ; // Smaller mantissa + output [`MANTISSA-1:0] Mmax ; // Larger mantissa + + // Internal signals + //wire BOF ; // Check for shifting overflow if B is larger + //wire AOF ; // Check for shifting overflow if A is larger + + assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]) ; + //assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits + //assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits + + // Determine final shift value + //assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ; + + assign Shift = MaxAB ? ShiftDet[9:5] : ShiftDet[4:0] ; + + // Take out smaller mantissa and append shift space + assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0] ; + + // Take out larger mantissa + assign Mmax = MaxAB ? B[`MANTISSA-1:0]: A[`MANTISSA-1:0] ; + + // Common exponent + assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]) ; + +endmodule + +// Description: Alignment shift stage 1, performs 16|12|8|4 shift + +module FPAddSub_AlignShift1( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`MANTISSA-1:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [2:0] Shift ; // Shift amount + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + // Internal signals + reg [`MANTISSA:0] Lvl1; + reg [`MANTISSA:0] Lvl2; + wire [2*`MANTISSA+1:0] Stage1; + integer i; // Loop variable + + always @(*) begin + // Rotate by 16? + //Lvl1 <= Shift[2] ? {17'b00000000000000001, MminP[22:16]} : {1'b1, MminP}; + Lvl1 <= Shift[2] ? {11'b0000000000} : {1'b1, MminP}; + + end + + assign Stage1 = { Lvl1, Lvl1}; + + always @(*) begin // Rotate {0 | 4 | 8 | 12} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl2 <= Stage1[`MANTISSA:0]; + // Rotate by 4 + 2'b01: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+4]; end /*Lvl2[`MANTISSA:`MANTISSA-3] <= 0;*/ end + // Rotate by 8 + 2'b10: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+8]; end /*Lvl2[`MANTISSA:`MANTISSA-7] <= 0;*/ end + // Rotate by 12 + 2'b11: Lvl2[`MANTISSA: 0] <= 0; + //2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end + endcase + end + + // Assign output to next shift stage + assign Mmin = Lvl2; + +endmodule + +// Description: Alignment shift stage 2, performs 3|2|1 shift + +module FPAddSub_AlignShift2( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`MANTISSA:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [1:0] Shift ; // Shift amount + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + // Internal Signal + reg [`MANTISSA:0] Lvl3; + wire [2*`MANTISSA+1:0] Stage2; + integer j; // Loop variable + + assign Stage2 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl3 <= Stage2[`MANTISSA:0]; + // Rotate by 1 + 2'b01: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+1]; end /*Lvl3[`MANTISSA] <= 0; */end + // Rotate by 2 + 2'b10: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+2]; end /*Lvl3[`MANTISSA:`MANTISSA-1] <= 0;*/ end + // Rotate by 3 + 2'b11: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+3]; end /*Lvl3[`MANTISSA:`MANTISSA-2] <= 0;*/ end + endcase + end + + // Assign output + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + +// Description: Module that executes the addition or subtraction on mantissas. + +module FPAddSub_ExecutionModule( + Mmax, + Mmin, + Sa, + Sb, + MaxAB, + OpMode, + Sum, + PSgn, + Opr + ); + + // Input ports + input [`MANTISSA-1:0] Mmax ; // The larger mantissa + input [`MANTISSA:0] Mmin ; // The smaller mantissa + input Sa ; // Sign bit of larger number + input Sb ; // Sign bit of smaller number + input MaxAB ; // Indicates the larger number (0/A, 1/B) + input OpMode ; // Operation to be performed (0/Add, 1/Sub) + + // Output ports + output [`DWIDTH:0] Sum ; // The result of the operation + output PSgn ; // The sign for the result + output Opr ; // The effective (performed) operation + + assign Opr = (OpMode^Sa^Sb); // Resolve sign to determine operation + + // Perform effective operation + assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, 5'b00000} - {Mmin, 5'b00000}) : ({1'b1, Mmax, 5'b00000} + {Mmin, 5'b00000}) ; + + // Assign result sign + assign PSgn = (MaxAB ? Sb : Sa) ; + +endmodule + +// Description: Determine the normalization shift amount and perform 16-shift + +module FPAddSub_NormalizeModule( + Sum, + Mmin, + Shift + ); + + // Input ports + input [`DWIDTH:0] Sum ; // Mantissa sum including hidden 1 and GRS + + // Output ports + output [`DWIDTH:0] Mmin ; // Mantissa after 16|0 shift + output [4:0] Shift ; // Shift amount + + // Determine normalization shift amount by finding leading nought + assign Shift = ( + Sum[16] ? 5'b00000 : + Sum[15] ? 5'b00001 : + Sum[14] ? 5'b00010 : + Sum[13] ? 5'b00011 : + Sum[12] ? 5'b00100 : + Sum[11] ? 5'b00101 : + Sum[10] ? 5'b00110 : + Sum[9] ? 5'b00111 : + Sum[8] ? 5'b01000 : + Sum[7] ? 5'b01001 : + Sum[6] ? 5'b01010 : + Sum[5] ? 5'b01011 : + Sum[4] ? 5'b01100 : 5'b01101 + // Sum[19] ? 5'b01101 : + // Sum[18] ? 5'b01110 : + // Sum[17] ? 5'b01111 : + // Sum[16] ? 5'b10000 : + // Sum[15] ? 5'b10001 : + // Sum[14] ? 5'b10010 : + // Sum[13] ? 5'b10011 : + // Sum[12] ? 5'b10100 : + // Sum[11] ? 5'b10101 : + // Sum[10] ? 5'b10110 : + // Sum[9] ? 5'b10111 : + // Sum[8] ? 5'b11000 : + // Sum[7] ? 5'b11001 : 5'b11010 + ); + + reg [`DWIDTH:0] Lvl1; + + always @(*) begin + // Rotate by 16? + Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum; + end + + // Assign outputs + assign Mmin = Lvl1; // Take out smaller mantissa + +endmodule + +// Description: Normalization shift stage 1, performs 12|8|4|3|2|1|0 shift + +module FPAddSub_NormalizeShift1( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`DWIDTH:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [3:0] Shift ; // Shift amount + + // Output ports + output [`DWIDTH:0] Mmin ; // The smaller mantissa + + reg [`DWIDTH:0] Lvl2; + wire [2*`DWIDTH+1:0] Stage1; + reg [`DWIDTH:0] Lvl3; + wire [2*`DWIDTH+1:0] Stage2; + integer i; // Loop variable + + assign Stage1 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 4 | 8 | 12} bits + case (Shift[3:2]) + // Rotate by 0 + 2'b00: //Lvl2 <= Stage1[`DWIDTH:0]; + begin Lvl2 = Stage1[`DWIDTH:0]; end + // Rotate by 4 + 2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-4]; end Lvl2[3:0] <= 0; end + begin Lvl2[`DWIDTH: (`DWIDTH-4)] = Stage1[3:0]; Lvl2[`DWIDTH-4-1:0] = Stage1[`DWIDTH-4]; end + // Rotate by 8 + 2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-8]; end Lvl2[7:0] <= 0; end + begin Lvl2[`DWIDTH: (`DWIDTH-8)] = Stage1[3:0]; Lvl2[`DWIDTH-8-1:0] = Stage1[`DWIDTH-8]; end + // Rotate by 12 + 2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end + begin Lvl2[`DWIDTH: (`DWIDTH-12)] = Stage1[3:0]; Lvl2[`DWIDTH-12-1:0] = Stage1[`DWIDTH-12]; end + endcase + end + + assign Stage2 = {Lvl2, Lvl2}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: //Lvl3 <= Stage2[`DWIDTH:0]; + begin Lvl3 = Stage2[`DWIDTH:0]; end + // Rotate by 1 + 2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-1]; end Lvl3[0] <= 0; end + begin Lvl3[`DWIDTH: (`DWIDTH-1)] = Stage2[3:0]; Lvl3[`DWIDTH-1-1:0] = Stage2[`DWIDTH-1]; end + // Rotate by 2 + 2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-2]; end Lvl3[1:0] <= 0; end + begin Lvl3[`DWIDTH: (`DWIDTH-2)] = Stage2[3:0]; Lvl3[`DWIDTH-2-1:0] = Stage2[`DWIDTH-2]; end + // Rotate by 3 + 2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end + begin Lvl3[`DWIDTH: (`DWIDTH-3)] = Stage2[3:0]; Lvl3[`DWIDTH-3-1:0] = Stage2[`DWIDTH-3]; end + endcase + end + + // Assign outputs + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + +// Description: Normalization shift stage 2, calculates post-normalization +// mantissa and exponent, as well as the bits used in rounding + +module FPAddSub_NormalizeShift2( + PSSum, + CExp, + Shift, + NormM, + NormE, + ZeroSum, + NegE, + R, + S, + FG + ); + + // Input ports + input [`DWIDTH:0] PSSum ; // The Pre-Shift-Sum + input [`EXPONENT-1:0] CExp ; + input [4:0] Shift ; // Amount to be shifted + + // Output ports + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output [`EXPONENT:0] NormE ; // Adjusted exponent + output ZeroSum ; // Zero flag + output NegE ; // Flag indicating negative exponent + output R ; // Round bit + output S ; // Final sticky bit + output FG ; + + // Internal signals + wire MSBShift ; // Flag indicating that a second shift is needed + wire [`EXPONENT:0] ExpOF ; // MSB set in sum indicates overflow + wire [`EXPONENT:0] ExpOK ; // MSB not set, no adjustment + + // Calculate normalized exponent and mantissa, check for all-zero sum + assign MSBShift = PSSum[`DWIDTH] ; // Check MSB in unnormalized sum + assign ZeroSum = ~|PSSum ; // Check for all zero sum + assign ExpOK = CExp - Shift ; // Adjust exponent for new normalized mantissa + assign NegE = ExpOK[`EXPONENT] ; // Check for exponent overflow + assign ExpOF = CExp - Shift + 1'b1 ; // If MSB set, add one to exponent(x2) + assign NormE = MSBShift ? ExpOF : ExpOK ; // Check for exponent overflow + assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1] ; // The new, normalized mantissa + + // Also need to compute sticky and round bits for the rounding stage + assign FG = PSSum[`EXPONENT] ; + assign R = PSSum[`EXPONENT-1] ; + assign S = |PSSum[`EXPONENT-2:0] ; + +endmodule + +// Description: Performs 'Round to nearest, tie to even'-rounding on the +// normalized mantissa according to the G, R, S bits. Calculates +// final result and checks for exponent overflow. + +module FPAddSub_RoundModule( + ZeroSum, + NormE, + NormM, + R, + S, + G, + Sa, + Sb, + Ctrl, + MaxAB, + Z, + EOF + ); + + // Input ports + input ZeroSum ; // Sum is zero + input [`EXPONENT:0] NormE ; // Normalized exponent + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input R ; // Round bit + input S ; // Sticky bit + input G ; + input Sa ; // A's sign bit + input Sb ; // B's sign bit + input Ctrl ; // Control bit (operation) + input MaxAB ; + + // Output ports + output [`DWIDTH-1:0] Z ; // Final result + output EOF ; + + // Internal signals + wire [`MANTISSA:0] RoundUpM ; // Rounded up sum with room for overflow + wire [`MANTISSA-1:0] RoundM ; // The final rounded sum + wire [`EXPONENT:0] RoundE ; // Rounded exponent (note extra bit due to poential overflow ) + wire RoundUp ; // Flag indicating that the sum should be rounded up + wire FSgn; + wire ExpAdd ; // May have to add 1 to compensate for overflow + wire RoundOF ; // Rounding overflow + + // The cases where we need to round upwards (= adding one) in Round to nearest, tie to even + assign RoundUp = (G & ((R | S) | NormM[0])) ; + + // Note that in the other cases (rounding down), the sum is already 'rounded' + assign RoundUpM = (NormM + 1) ; // The sum, rounded up by 1 + assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM) ; // Compute final mantissa + assign RoundOF = RoundUp & RoundUpM[`MANTISSA] ; // Check for overflow when rounding up + + // Calculate post-rounding exponent + assign ExpAdd = (RoundOF ? 1'b1 : 1'b0) ; // Add 1 to exponent to compensate for overflow + assign RoundE = ZeroSum ? 5'b00000 : (NormE + ExpAdd) ; // Final exponent + + // If zero, need to determine sign according to rounding + assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ; + + // Assign final result + assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]} ; + + // Indicate exponent overflow + assign EOF = RoundE[`EXPONENT]; + +endmodule + +// Description: Check the final result for exception conditions and set +// flags accordingly. + +module FPAddSub_ExceptionModule( + Z, + NegE, + R, + S, + InputExc, + EOF, + P, + Flags + ); + + // Input ports + input [`DWIDTH-1:0] Z ; // Final product + input NegE ; // Negative exponent? + input R ; // Round bit + input S ; // Sticky bit + input [4:0] InputExc ; // Exceptions in inputs A and B + input EOF ; + + // Output ports + output [`DWIDTH-1:0] P ; // Final result + output [4:0] Flags ; // Exception flags + + // Internal signals + wire Overflow ; // Overflow flag + wire Underflow ; // Underflow flag + wire DivideByZero ; // Divide-by-Zero flag (always 0 in Add/Sub) + wire Invalid ; // Invalid inputs or result + wire Inexact ; // Result is inexact because of rounding + + // Exception flags + + // Result is too big to be represented + assign Overflow = EOF | InputExc[1] | InputExc[0] ; + + // Result is too small to be represented + assign Underflow = NegE & (R | S); + + // Infinite result computed exactly from finite operands + assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0]; + + // Invalid inputs or operation + assign Invalid = |(InputExc[4:2]) ; + + // Inexact answer due to rounding, overflow or underflow + assign Inexact = (R | S) | Overflow | Underflow; + + // Put pieces together to form final result + assign P = Z ; + + // Collect exception flags + assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact} ; + +endmodule +`endif + + diff --git a/designs/koios/tdarknet_like.small/design.yaml b/designs/koios/tdarknet_like.small/design.yaml new file mode 100644 index 000000000..527a1211b --- /dev/null +++ b/designs/koios/tdarknet_like.small/design.yaml @@ -0,0 +1 @@ +top: td_fused_top diff --git a/designs/koios/tdarknet_like.small/tdarknet_like.small.v b/designs/koios/tdarknet_like.small/tdarknet_like.small.v new file mode 100644 index 000000000..d69f7b9aa --- /dev/null +++ b/designs/koios/tdarknet_like.small/tdarknet_like.small.v @@ -0,0 +1,114900 @@ +////////////////////////////////////////////////////////////////////////////// +// HLS generated design for Tiny Darknet neural network (https://pjreddie.com/darknet/tiny-darknet/) +// IEEE FP16 is used. +// Pairs of layers are fused. Separate buffers for weights of each layer. Double buffering for activations. +////////////////////////////////////////////////////////////////////////////// + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +////////////////////////////////////////////////////////////////////////////// +// Abridged for VTR by: Daniel Rauch +////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns / 1 ps + +module td_fused_top_Block_entry_proc_proc392 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + tmp, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] tmp; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg ap_block_state1; +reg [15:0] ap_return_preg; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 ap_return_preg = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 16'd0; + end else begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return_preg <= tmp; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return = tmp; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //td_fused_top_Block_entry_proc_proc392 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_Block_entry_proc_proc397 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + tmp, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] tmp; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg ap_block_state1; +reg [15:0] ap_return_preg; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 ap_return_preg = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 16'd0; + end else begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return_preg <= tmp; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return = tmp; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //td_fused_top_Block_entry_proc_proc397 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_Block_entry_proc_proc403 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + tmp, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] tmp; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg ap_block_state1; +reg [15:0] ap_return_preg; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 ap_return_preg = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 16'd0; + end else begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return_preg <= tmp; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return = tmp; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //td_fused_top_Block_entry_proc_proc403 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_Block_entry_proc_proc408 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + tmp, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] tmp; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg ap_block_state1; +reg [15:0] ap_return_preg; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 ap_return_preg = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 16'd0; + end else begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return_preg <= tmp; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return = tmp; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //td_fused_top_Block_entry_proc_proc408 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_Block_entry_proc_proc413 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + tmp, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] tmp; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg ap_block_state1; +reg [15:0] ap_return_preg; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 ap_return_preg = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 16'd0; + end else begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return_preg <= tmp; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return = tmp; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //td_fused_top_Block_entry_proc_proc413 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_Block_entry_proc_proc419 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + tmp, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] tmp; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg ap_block_state1; +reg [15:0] ap_return_preg; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 ap_return_preg = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 16'd0; + end else begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return_preg <= tmp; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return = tmp; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //td_fused_top_Block_entry_proc_proc419 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_Block_entry_proc_proc424 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + tmp, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] tmp; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg ap_block_state1; +reg [15:0] ap_return_preg; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 ap_return_preg = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 16'd0; + end else begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return_preg <= tmp; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return = tmp; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //td_fused_top_Block_entry_proc_proc424 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_Block_entry_proc_proc429 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + tmp, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] tmp; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg ap_block_state1; +reg [15:0] ap_return_preg; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 ap_return_preg = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 16'd0; + end else begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return_preg <= tmp; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return = tmp; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //td_fused_top_Block_entry_proc_proc429 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_Block_entry_proc_proc435 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + tmp, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] tmp; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg ap_block_state1; +reg [15:0] ap_return_preg; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 ap_return_preg = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 16'd0; + end else begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return_preg <= tmp; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return = tmp; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //td_fused_top_Block_entry_proc_proc435 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_Block_entry_proc_proc441 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + tmp, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] tmp; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg ap_block_state1; +reg [15:0] ap_return_preg; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 ap_return_preg = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 16'd0; + end else begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return_preg <= tmp; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return = tmp; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //td_fused_top_Block_entry_proc_proc441 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_Block_entry_proc_proc446 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + tmp, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] tmp; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg ap_block_state1; +reg [15:0] ap_return_preg; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 ap_return_preg = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 16'd0; + end else begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return_preg <= tmp; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return = tmp; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //td_fused_top_Block_entry_proc_proc446 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_Block_entry_proc_proc ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + tmp, + ap_return +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] tmp; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] ap_return; + +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg ap_block_state1; +reg [15:0] ap_return_preg; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 ap_return_preg = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_return_preg <= 16'd0; + end else begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return_preg <= tmp; + end + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_return = tmp; + end else begin + ap_return = ap_return_preg; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +endmodule //td_fused_top_Block_entry_proc_proc +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37360_accum1_out_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 3; +parameter MEM_SIZE = 8; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37360_accum1_out_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd8; +parameter AddressWidth = 32'd3; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37360_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37360_accum1_out_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37360_accum1_out_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 3, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37360_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37360_accum1_out_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37360_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37360_accum1_out_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37360_ifmap_vec_0_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 8; +parameter MEM_SIZE = 256; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37360_ifmap_vec_0_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd256; +parameter AddressWidth = 32'd8; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37360_ifmap_vec_0_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37360_ifmap_vec_0_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37360_ifmap_vec_0_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 8, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37360_ifmap_vec_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37360_ifmap_vec_0_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37360_ifmap_vec_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37360_ifmap_vec_0_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37360_products_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 8; +parameter MEM_SIZE = 256; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37360_products_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd256; +parameter AddressWidth = 32'd8; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37360_products_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37360_products_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37360_products_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 8, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire [AddressWidth-1:0] i_address1, + output wire [DataWidth-1:0] i_q1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire [AddressWidth-1:0] t_address1, + output wire [DataWidth-1:0] t_q1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_q1_0, buf_q1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37360_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37360_products_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .q1 ( buf_q1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37360_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37360_products_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .q1 ( buf_q1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign i_q1 = (prev_iptr == 1'b1 ? buf_q1_1 : buf_q1_0); +assign t_q1 = reg_valid1 ? reg_q1 : (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// reg_q1 and reg_valid1 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q1 <= 1'b0; + reg_valid1 <= 1'b0; + end else if (!t_ce1 && !reg_valid1) begin + reg_q1 <= (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + reg_valid1 <= 1'b1; + end else if (t_ce1) begin + reg_valid1 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37360 ( + ap_clk, + ap_rst, + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + ap_start, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +input ap_clk; +input ap_rst; +output [13:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [13:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [13:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [13:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [5:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [5:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +output [11:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [11:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +input ap_start; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +wire [15:0] ifmap_vec_0_0_i_q0; +wire [15:0] ifmap_vec_0_0_t_q0; +wire [15:0] weight_vecs_0_0_0_i_q0; +wire [15:0] weight_vecs_0_0_0_t_q0; +wire [15:0] products_0_i_q0; +wire [15:0] products_0_i_q1; +wire [15:0] products_0_t_q0; +wire [15:0] products_0_t_q1; +wire [15:0] accum1_out_0_i_q0; +wire [15:0] accum1_out_0_t_q0; +wire tdf9_get_next_ijk_U0_ap_start; +wire tdf9_get_next_ijk_U0_ap_done; +wire tdf9_get_next_ijk_U0_ap_continue; +wire tdf9_get_next_ijk_U0_ap_idle; +wire tdf9_get_next_ijk_U0_ap_ready; +wire tdf9_get_next_ijk_U0_start_out; +wire tdf9_get_next_ijk_U0_start_write; +wire [15:0] tdf9_get_next_ijk_U0_indices_0_din; +wire tdf9_get_next_ijk_U0_indices_0_write; +wire [15:0] tdf9_get_next_ijk_U0_indices_1_din; +wire tdf9_get_next_ijk_U0_indices_1_write; +wire [5:0] tdf9_get_next_ijk_U0_indices_2_out_din; +wire tdf9_get_next_ijk_U0_indices_2_out_write; +wire [5:0] tdf9_get_next_ijk_U0_indices_2_out1_din; +wire tdf9_get_next_ijk_U0_indices_2_out1_write; +wire tdf9_readInputs_U0_ap_start; +wire tdf9_readInputs_U0_ap_done; +wire tdf9_readInputs_U0_ap_continue; +wire tdf9_readInputs_U0_ap_idle; +wire tdf9_readInputs_U0_ap_ready; +wire [13:0] tdf9_readInputs_U0_in_data_address0; +wire tdf9_readInputs_U0_in_data_ce0; +wire tdf9_readInputs_U0_indices_01_read; +wire tdf9_readInputs_U0_indices_12_read; +wire [7:0] tdf9_readInputs_U0_ifmap_vec_0_0_address0; +wire tdf9_readInputs_U0_ifmap_vec_0_0_ce0; +wire tdf9_readInputs_U0_ifmap_vec_0_0_we0; +wire [15:0] tdf9_readInputs_U0_ifmap_vec_0_0_d0; +wire [7:0] tdf9_readInputs_U0_ifmap_vec_0_0_address1; +wire tdf9_readInputs_U0_ifmap_vec_0_0_ce1; +wire tdf9_readInputs_U0_ifmap_vec_0_0_we1; +wire [15:0] tdf9_readInputs_U0_ifmap_vec_0_0_d1; +wire [3:0] tdf9_readInputs_U0_indices_01_out_din; +wire tdf9_readInputs_U0_indices_01_out_write; +wire [7:0] tdf9_readInputs_U0_indices_12_out_din; +wire tdf9_readInputs_U0_indices_12_out_write; +wire tdf9_readInputs_U0_in_data_full_n; +wire tdf9_readInputs_U0_in_data_write; +wire ap_channel_done_ifmap_vec_0_0; +wire tdf9_readInputs_U0_ifmap_vec_0_0_full_n; +wire tdf9_readFilters62_U0_ap_start; +wire tdf9_readFilters62_U0_ap_done; +wire tdf9_readFilters62_U0_ap_continue; +wire tdf9_readFilters62_U0_ap_idle; +wire tdf9_readFilters62_U0_ap_ready; +wire [13:0] tdf9_readFilters62_U0_filter_data_address0; +wire tdf9_readFilters62_U0_filter_data_ce0; +wire tdf9_readFilters62_U0_indices_23_read; +wire [7:0] tdf9_readFilters62_U0_weight_vecs_0_0_0_address0; +wire tdf9_readFilters62_U0_weight_vecs_0_0_0_ce0; +wire tdf9_readFilters62_U0_weight_vecs_0_0_0_we0; +wire [15:0] tdf9_readFilters62_U0_weight_vecs_0_0_0_d0; +wire ap_channel_done_weight_vecs_0_0_0; +wire tdf9_readFilters62_U0_weight_vecs_0_0_0_full_n; +wire tdf9_dot_product_U0_ap_start; +wire tdf9_dot_product_U0_ap_done; +wire tdf9_dot_product_U0_ap_continue; +wire tdf9_dot_product_U0_ap_idle; +wire tdf9_dot_product_U0_ap_ready; +wire [7:0] tdf9_dot_product_U0_ifmap_vec_0_0_address0; +wire tdf9_dot_product_U0_ifmap_vec_0_0_ce0; +wire [7:0] tdf9_dot_product_U0_weight_vecs_0_0_0_address0; +wire tdf9_dot_product_U0_weight_vecs_0_0_0_ce0; +wire [7:0] tdf9_dot_product_U0_products_0_address0; +wire tdf9_dot_product_U0_products_0_ce0; +wire tdf9_dot_product_U0_products_0_we0; +wire [15:0] tdf9_dot_product_U0_products_0_d0; +wire ap_channel_done_products_0; +wire tdf9_dot_product_U0_products_0_full_n; +wire tdf9_accum_1_U0_ap_start; +wire tdf9_accum_1_U0_ap_done; +wire tdf9_accum_1_U0_ap_continue; +wire tdf9_accum_1_U0_ap_idle; +wire tdf9_accum_1_U0_ap_ready; +wire [7:0] tdf9_accum_1_U0_accum_in_0_address0; +wire tdf9_accum_1_U0_accum_in_0_ce0; +wire [7:0] tdf9_accum_1_U0_accum_in_0_address1; +wire tdf9_accum_1_U0_accum_in_0_ce1; +wire [2:0] tdf9_accum_1_U0_accum_out_address0; +wire tdf9_accum_1_U0_accum_out_ce0; +wire tdf9_accum_1_U0_accum_out_we0; +wire [15:0] tdf9_accum_1_U0_accum_out_d0; +wire [2:0] tdf9_accum_1_U0_accum_out_address1; +wire tdf9_accum_1_U0_accum_out_ce1; +wire tdf9_accum_1_U0_accum_out_we1; +wire [15:0] tdf9_accum_1_U0_accum_out_d1; +wire ap_channel_done_accum1_out_0; +wire tdf9_accum_1_U0_accum_out_full_n; +wire tdf9_accum_2_U0_ap_start; +wire tdf9_accum_2_U0_ap_done; +wire tdf9_accum_2_U0_ap_continue; +wire tdf9_accum_2_U0_ap_idle; +wire tdf9_accum_2_U0_ap_ready; +wire [15:0] tdf9_accum_2_U0_accum_in_2; +wire tdf9_accum_2_U0_accum_in_2_ap_vld; +wire [2:0] tdf9_accum_2_U0_accum_in_address0; +wire tdf9_accum_2_U0_accum_in_ce0; +wire ap_channel_done_tmp_channel; +wire tmp_channel_full_n; +wire Block_entry_proc_proc429_U0_ap_start; +wire Block_entry_proc_proc429_U0_ap_done; +wire Block_entry_proc_proc429_U0_ap_continue; +wire Block_entry_proc_proc429_U0_ap_idle; +wire Block_entry_proc_proc429_U0_ap_ready; +wire [15:0] Block_entry_proc_proc429_U0_ap_return; +wire ap_channel_done_sums_0; +wire sums_0_full_n; +wire tdf9_adjust_U0_ap_start; +wire tdf9_adjust_U0_ap_done; +wire tdf9_adjust_U0_ap_continue; +wire tdf9_adjust_U0_ap_idle; +wire tdf9_adjust_U0_ap_ready; +wire [5:0] tdf9_adjust_U0_adjustments_address0; +wire tdf9_adjust_U0_adjustments_ce0; +wire tdf9_adjust_U0_indices_23_read; +wire [15:0] tdf9_adjust_U0_ap_return; +wire ap_channel_done_outputs_0; +wire outputs_0_full_n; +wire tdf9_writeOutputs_unaligned_U0_ap_start; +wire tdf9_writeOutputs_unaligned_U0_ap_done; +wire tdf9_writeOutputs_unaligned_U0_ap_continue; +wire tdf9_writeOutputs_unaligned_U0_ap_idle; +wire tdf9_writeOutputs_unaligned_U0_ap_ready; +wire tdf9_writeOutputs_unaligned_U0_indices_01_read; +wire tdf9_writeOutputs_unaligned_U0_indices_12_read; +wire [11:0] tdf9_writeOutputs_unaligned_U0_out_data_address1; +wire tdf9_writeOutputs_unaligned_U0_out_data_ce1; +wire tdf9_writeOutputs_unaligned_U0_out_data_we1; +wire [63:0] tdf9_writeOutputs_unaligned_U0_out_data_d1; +wire tdf9_writeOutputs_unaligned_U0_out_data_full_n; +wire tdf9_writeOutputs_unaligned_U0_out_data_write; +wire ap_sync_continue; +wire ifmap_vec_0_0_i_full_n; +wire ifmap_vec_0_0_t_empty_n; +wire weight_vecs_0_0_0_i_full_n; +wire weight_vecs_0_0_0_t_empty_n; +wire products_0_i_full_n; +wire products_0_t_empty_n; +wire [15:0] products_0_t_d1; +wire products_0_t_we1; +wire accum1_out_0_i_full_n; +wire accum1_out_0_t_empty_n; +wire indices_01_c_full_n; +wire [15:0] indices_01_c_dout; +wire indices_01_c_empty_n; +wire indices_12_c_full_n; +wire [15:0] indices_12_c_dout; +wire indices_12_c_empty_n; +wire indices_23_c_full_n; +wire [5:0] indices_23_c_dout; +wire indices_23_c_empty_n; +wire indices_23_c1_full_n; +wire [5:0] indices_23_c1_dout; +wire indices_23_c1_empty_n; +wire indices_01_c2_full_n; +wire [3:0] indices_01_c2_dout; +wire indices_01_c2_empty_n; +wire indices_12_c3_full_n; +wire [7:0] indices_12_c3_dout; +wire indices_12_c3_empty_n; +wire [15:0] tmp_channel_dout; +wire tmp_channel_empty_n; +wire [15:0] sums_0_dout; +wire sums_0_empty_n; +wire [15:0] outputs_0_dout; +wire outputs_0_empty_n; +wire ap_sync_done; +wire ap_sync_ready; +reg ap_sync_reg_tdf9_get_next_ijk_U0_ap_ready; +wire ap_sync_tdf9_get_next_ijk_U0_ap_ready; +reg ap_sync_reg_tdf9_readInputs_U0_ap_ready; +wire ap_sync_tdf9_readInputs_U0_ap_ready; +wire [0:0] start_for_tdf9_readFilters62_U0_din; +wire start_for_tdf9_readFilters62_U0_full_n; +wire [0:0] start_for_tdf9_readFilters62_U0_dout; +wire start_for_tdf9_readFilters62_U0_empty_n; +wire tdf9_readInputs_U0_start_full_n; +wire tdf9_readInputs_U0_start_write; +wire tdf9_readFilters62_U0_start_full_n; +wire tdf9_readFilters62_U0_start_write; +wire tdf9_dot_product_U0_start_full_n; +wire tdf9_dot_product_U0_start_write; +wire tdf9_accum_1_U0_start_full_n; +wire tdf9_accum_1_U0_start_write; +wire tdf9_accum_2_U0_start_full_n; +wire tdf9_accum_2_U0_start_write; +wire Block_entry_proc_proc429_U0_start_full_n; +wire Block_entry_proc_proc429_U0_start_write; +wire tdf9_adjust_U0_start_full_n; +wire tdf9_adjust_U0_start_write; +wire tdf9_writeOutputs_unaligned_U0_start_full_n; +wire tdf9_writeOutputs_unaligned_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_sync_reg_tdf9_get_next_ijk_U0_ap_ready = 1'b0; +#0 ap_sync_reg_tdf9_readInputs_U0_ap_ready = 1'b0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP37360_ifmap_vec_0_0 #( + .DataWidth( 16 ), + .AddressRange( 256 ), + .AddressWidth( 8 )) +ifmap_vec_0_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf9_readInputs_U0_ap_done), + .i_full_n(ifmap_vec_0_0_i_full_n), + .i_ce0(tdf9_readInputs_U0_ifmap_vec_0_0_ce0), + .i_we0(tdf9_readInputs_U0_ifmap_vec_0_0_we0), + .i_address0(tdf9_readInputs_U0_ifmap_vec_0_0_address0), + .i_d0(tdf9_readInputs_U0_ifmap_vec_0_0_d0), + .i_q0(ifmap_vec_0_0_i_q0), + .i_ce1(tdf9_readInputs_U0_ifmap_vec_0_0_ce1), + .i_we1(tdf9_readInputs_U0_ifmap_vec_0_0_we1), + .i_address1(tdf9_readInputs_U0_ifmap_vec_0_0_address1), + .i_d1(tdf9_readInputs_U0_ifmap_vec_0_0_d1), + .t_ce(1'b1), + .t_read(tdf9_dot_product_U0_ap_ready), + .t_empty_n(ifmap_vec_0_0_t_empty_n), + .t_ce0(tdf9_dot_product_U0_ifmap_vec_0_0_ce0), + .t_we0(1'b0), + .t_address0(tdf9_dot_product_U0_ifmap_vec_0_0_address0), + .t_d0(16'd0), + .t_q0(ifmap_vec_0_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(8'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37360_weight_vecs_0_0_0 #( + .DataWidth( 16 ), + .AddressRange( 256 ), + .AddressWidth( 8 )) +weight_vecs_0_0_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf9_readFilters62_U0_ap_done), + .i_full_n(weight_vecs_0_0_0_i_full_n), + .i_ce0(tdf9_readFilters62_U0_weight_vecs_0_0_0_ce0), + .i_we0(tdf9_readFilters62_U0_weight_vecs_0_0_0_we0), + .i_address0(tdf9_readFilters62_U0_weight_vecs_0_0_0_address0), + .i_d0(tdf9_readFilters62_U0_weight_vecs_0_0_0_d0), + .i_q0(weight_vecs_0_0_0_i_q0), + .t_ce(1'b1), + .t_read(tdf9_dot_product_U0_ap_ready), + .t_empty_n(weight_vecs_0_0_0_t_empty_n), + .t_ce0(tdf9_dot_product_U0_weight_vecs_0_0_0_ce0), + .t_we0(1'b0), + .t_address0(tdf9_dot_product_U0_weight_vecs_0_0_0_address0), + .t_d0(16'd0), + .t_q0(weight_vecs_0_0_0_t_q0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37360_products_0 #( + .DataWidth( 16 ), + .AddressRange( 256 ), + .AddressWidth( 8 )) +products_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf9_dot_product_U0_ap_done), + .i_full_n(products_0_i_full_n), + .i_ce0(tdf9_dot_product_U0_products_0_ce0), + .i_we0(tdf9_dot_product_U0_products_0_we0), + .i_address0(tdf9_dot_product_U0_products_0_address0), + .i_d0(tdf9_dot_product_U0_products_0_d0), + .i_q0(products_0_i_q0), + .i_ce1(1'b0), + .i_address1(8'd0), + .i_q1(products_0_i_q1), + .t_ce(1'b1), + .t_read(tdf9_accum_1_U0_ap_ready), + .t_empty_n(products_0_t_empty_n), + .t_ce0(tdf9_accum_1_U0_accum_in_0_ce0), + .t_we0(1'b0), + .t_address0(tdf9_accum_1_U0_accum_in_0_address0), + .t_d0(16'd0), + .t_q0(products_0_t_q0), + .t_ce1(tdf9_accum_1_U0_accum_in_0_ce1), + .t_address1(tdf9_accum_1_U0_accum_in_0_address1), + .t_q1(products_0_t_q1) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37360_accum1_out_0 #( + .DataWidth( 16 ), + .AddressRange( 8 ), + .AddressWidth( 3 )) +accum1_out_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf9_accum_1_U0_ap_done), + .i_full_n(accum1_out_0_i_full_n), + .i_ce0(tdf9_accum_1_U0_accum_out_ce0), + .i_we0(tdf9_accum_1_U0_accum_out_we0), + .i_address0(tdf9_accum_1_U0_accum_out_address0), + .i_d0(tdf9_accum_1_U0_accum_out_d0), + .i_q0(accum1_out_0_i_q0), + .i_ce1(tdf9_accum_1_U0_accum_out_ce1), + .i_we1(tdf9_accum_1_U0_accum_out_we1), + .i_address1(tdf9_accum_1_U0_accum_out_address1), + .i_d1(tdf9_accum_1_U0_accum_out_d1), + .t_ce(1'b1), + .t_read(tdf9_accum_2_U0_ap_ready), + .t_empty_n(accum1_out_0_t_empty_n), + .t_ce0(tdf9_accum_2_U0_accum_in_ce0), + .t_we0(1'b0), + .t_address0(tdf9_accum_2_U0_accum_in_address0), + .t_d0(16'd0), + .t_q0(accum1_out_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(3'd0), + .t_d1(16'd0) +); + +td_fused_top_tdf9_get_next_ijk tdf9_get_next_ijk_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf9_get_next_ijk_U0_ap_start), + .start_full_n(start_for_tdf9_readFilters62_U0_full_n), + .ap_done(tdf9_get_next_ijk_U0_ap_done), + .ap_continue(tdf9_get_next_ijk_U0_ap_continue), + .ap_idle(tdf9_get_next_ijk_U0_ap_idle), + .ap_ready(tdf9_get_next_ijk_U0_ap_ready), + .start_out(tdf9_get_next_ijk_U0_start_out), + .start_write(tdf9_get_next_ijk_U0_start_write), + .indices_0_din(tdf9_get_next_ijk_U0_indices_0_din), + .indices_0_full_n(indices_01_c_full_n), + .indices_0_write(tdf9_get_next_ijk_U0_indices_0_write), + .indices_1_din(tdf9_get_next_ijk_U0_indices_1_din), + .indices_1_full_n(indices_12_c_full_n), + .indices_1_write(tdf9_get_next_ijk_U0_indices_1_write), + .indices_2_out_din(tdf9_get_next_ijk_U0_indices_2_out_din), + .indices_2_out_full_n(indices_23_c_full_n), + .indices_2_out_write(tdf9_get_next_ijk_U0_indices_2_out_write), + .indices_2_out1_din(tdf9_get_next_ijk_U0_indices_2_out1_din), + .indices_2_out1_full_n(indices_23_c1_full_n), + .indices_2_out1_write(tdf9_get_next_ijk_U0_indices_2_out1_write) +); + +td_fused_top_tdf9_readInputs tdf9_readInputs_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf9_readInputs_U0_ap_start), + .ap_done(tdf9_readInputs_U0_ap_done), + .ap_continue(tdf9_readInputs_U0_ap_continue), + .ap_idle(tdf9_readInputs_U0_ap_idle), + .ap_ready(tdf9_readInputs_U0_ap_ready), + .in_data_address0(tdf9_readInputs_U0_in_data_address0), + .in_data_ce0(tdf9_readInputs_U0_in_data_ce0), + .in_data_q0(in_data_q0), + .indices_01_dout(indices_01_c_dout), + .indices_01_empty_n(indices_01_c_empty_n), + .indices_01_read(tdf9_readInputs_U0_indices_01_read), + .indices_12_dout(indices_12_c_dout), + .indices_12_empty_n(indices_12_c_empty_n), + .indices_12_read(tdf9_readInputs_U0_indices_12_read), + .ifmap_vec_0_0_address0(tdf9_readInputs_U0_ifmap_vec_0_0_address0), + .ifmap_vec_0_0_ce0(tdf9_readInputs_U0_ifmap_vec_0_0_ce0), + .ifmap_vec_0_0_we0(tdf9_readInputs_U0_ifmap_vec_0_0_we0), + .ifmap_vec_0_0_d0(tdf9_readInputs_U0_ifmap_vec_0_0_d0), + .ifmap_vec_0_0_address1(tdf9_readInputs_U0_ifmap_vec_0_0_address1), + .ifmap_vec_0_0_ce1(tdf9_readInputs_U0_ifmap_vec_0_0_ce1), + .ifmap_vec_0_0_we1(tdf9_readInputs_U0_ifmap_vec_0_0_we1), + .ifmap_vec_0_0_d1(tdf9_readInputs_U0_ifmap_vec_0_0_d1), + .indices_01_out_din(tdf9_readInputs_U0_indices_01_out_din), + .indices_01_out_full_n(indices_01_c2_full_n), + .indices_01_out_write(tdf9_readInputs_U0_indices_01_out_write), + .indices_12_out_din(tdf9_readInputs_U0_indices_12_out_din), + .indices_12_out_full_n(indices_12_c3_full_n), + .indices_12_out_write(tdf9_readInputs_U0_indices_12_out_write) +); + +td_fused_top_tdf9_readFilters62 tdf9_readFilters62_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf9_readFilters62_U0_ap_start), + .ap_done(tdf9_readFilters62_U0_ap_done), + .ap_continue(tdf9_readFilters62_U0_ap_continue), + .ap_idle(tdf9_readFilters62_U0_ap_idle), + .ap_ready(tdf9_readFilters62_U0_ap_ready), + .filter_data_address0(tdf9_readFilters62_U0_filter_data_address0), + .filter_data_ce0(tdf9_readFilters62_U0_filter_data_ce0), + .filter_data_q0(filter_data_q0), + .indices_23_dout(indices_23_c_dout), + .indices_23_empty_n(indices_23_c_empty_n), + .indices_23_read(tdf9_readFilters62_U0_indices_23_read), + .weight_vecs_0_0_0_address0(tdf9_readFilters62_U0_weight_vecs_0_0_0_address0), + .weight_vecs_0_0_0_ce0(tdf9_readFilters62_U0_weight_vecs_0_0_0_ce0), + .weight_vecs_0_0_0_we0(tdf9_readFilters62_U0_weight_vecs_0_0_0_we0), + .weight_vecs_0_0_0_d0(tdf9_readFilters62_U0_weight_vecs_0_0_0_d0) +); + +td_fused_top_tdf9_dot_product tdf9_dot_product_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf9_dot_product_U0_ap_start), + .ap_done(tdf9_dot_product_U0_ap_done), + .ap_continue(tdf9_dot_product_U0_ap_continue), + .ap_idle(tdf9_dot_product_U0_ap_idle), + .ap_ready(tdf9_dot_product_U0_ap_ready), + .ifmap_vec_0_0_address0(tdf9_dot_product_U0_ifmap_vec_0_0_address0), + .ifmap_vec_0_0_ce0(tdf9_dot_product_U0_ifmap_vec_0_0_ce0), + .ifmap_vec_0_0_q0(ifmap_vec_0_0_t_q0), + .weight_vecs_0_0_0_address0(tdf9_dot_product_U0_weight_vecs_0_0_0_address0), + .weight_vecs_0_0_0_ce0(tdf9_dot_product_U0_weight_vecs_0_0_0_ce0), + .weight_vecs_0_0_0_q0(weight_vecs_0_0_0_t_q0), + .products_0_address0(tdf9_dot_product_U0_products_0_address0), + .products_0_ce0(tdf9_dot_product_U0_products_0_ce0), + .products_0_we0(tdf9_dot_product_U0_products_0_we0), + .products_0_d0(tdf9_dot_product_U0_products_0_d0) +); + +td_fused_top_tdf9_accum_1 tdf9_accum_1_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf9_accum_1_U0_ap_start), + .ap_done(tdf9_accum_1_U0_ap_done), + .ap_continue(tdf9_accum_1_U0_ap_continue), + .ap_idle(tdf9_accum_1_U0_ap_idle), + .ap_ready(tdf9_accum_1_U0_ap_ready), + .accum_in_0_address0(tdf9_accum_1_U0_accum_in_0_address0), + .accum_in_0_ce0(tdf9_accum_1_U0_accum_in_0_ce0), + .accum_in_0_q0(products_0_t_q0), + .accum_in_0_address1(tdf9_accum_1_U0_accum_in_0_address1), + .accum_in_0_ce1(tdf9_accum_1_U0_accum_in_0_ce1), + .accum_in_0_q1(products_0_t_q1), + .accum_out_address0(tdf9_accum_1_U0_accum_out_address0), + .accum_out_ce0(tdf9_accum_1_U0_accum_out_ce0), + .accum_out_we0(tdf9_accum_1_U0_accum_out_we0), + .accum_out_d0(tdf9_accum_1_U0_accum_out_d0), + .accum_out_address1(tdf9_accum_1_U0_accum_out_address1), + .accum_out_ce1(tdf9_accum_1_U0_accum_out_ce1), + .accum_out_we1(tdf9_accum_1_U0_accum_out_we1), + .accum_out_d1(tdf9_accum_1_U0_accum_out_d1) +); + +td_fused_top_tdf9_accum_2 tdf9_accum_2_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf9_accum_2_U0_ap_start), + .ap_done(tdf9_accum_2_U0_ap_done), + .ap_continue(tdf9_accum_2_U0_ap_continue), + .ap_idle(tdf9_accum_2_U0_ap_idle), + .ap_ready(tdf9_accum_2_U0_ap_ready), + .accum_in_2(tdf9_accum_2_U0_accum_in_2), + .accum_in_2_ap_vld(tdf9_accum_2_U0_accum_in_2_ap_vld), + .accum_in_address0(tdf9_accum_2_U0_accum_in_address0), + .accum_in_ce0(tdf9_accum_2_U0_accum_in_ce0), + .accum_in_q0(accum1_out_0_t_q0) +); + +td_fused_top_Block_entry_proc_proc429 Block_entry_proc_proc429_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(Block_entry_proc_proc429_U0_ap_start), + .ap_done(Block_entry_proc_proc429_U0_ap_done), + .ap_continue(Block_entry_proc_proc429_U0_ap_continue), + .ap_idle(Block_entry_proc_proc429_U0_ap_idle), + .ap_ready(Block_entry_proc_proc429_U0_ap_ready), + .tmp(tmp_channel_dout), + .ap_return(Block_entry_proc_proc429_U0_ap_return) +); + +td_fused_top_tdf9_adjust tdf9_adjust_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf9_adjust_U0_ap_start), + .ap_done(tdf9_adjust_U0_ap_done), + .ap_continue(tdf9_adjust_U0_ap_continue), + .ap_idle(tdf9_adjust_U0_ap_idle), + .ap_ready(tdf9_adjust_U0_ap_ready), + .sums_read(sums_0_dout), + .adjustments_address0(tdf9_adjust_U0_adjustments_address0), + .adjustments_ce0(tdf9_adjust_U0_adjustments_ce0), + .adjustments_q0(adjustments_q0), + .indices_23_dout(indices_23_c1_dout), + .indices_23_empty_n(indices_23_c1_empty_n), + .indices_23_read(tdf9_adjust_U0_indices_23_read), + .ap_return(tdf9_adjust_U0_ap_return) +); + +td_fused_top_tdf9_writeOutputs_unaligned tdf9_writeOutputs_unaligned_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf9_writeOutputs_unaligned_U0_ap_start), + .ap_done(tdf9_writeOutputs_unaligned_U0_ap_done), + .ap_continue(tdf9_writeOutputs_unaligned_U0_ap_continue), + .ap_idle(tdf9_writeOutputs_unaligned_U0_ap_idle), + .ap_ready(tdf9_writeOutputs_unaligned_U0_ap_ready), + .indices_01_dout(indices_01_c2_dout), + .indices_01_empty_n(indices_01_c2_empty_n), + .indices_01_read(tdf9_writeOutputs_unaligned_U0_indices_01_read), + .indices_12_dout(indices_12_c3_dout), + .indices_12_empty_n(indices_12_c3_empty_n), + .indices_12_read(tdf9_writeOutputs_unaligned_U0_indices_12_read), + .p_read(outputs_0_dout), + .out_data_address1(tdf9_writeOutputs_unaligned_U0_out_data_address1), + .out_data_ce1(tdf9_writeOutputs_unaligned_U0_out_data_ce1), + .out_data_we1(tdf9_writeOutputs_unaligned_U0_out_data_we1), + .out_data_d1(tdf9_writeOutputs_unaligned_U0_out_data_d1) +); + +td_fused_top_fifo_w16_d2_S_x6 indices_01_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf9_readInputs_U0_indices_01_read), + .if_dout(indices_01_c_dout), + .if_full_n(indices_01_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf9_get_next_ijk_U0_indices_0_write), + .if_din(tdf9_get_next_ijk_U0_indices_0_din) +); + +td_fused_top_fifo_w16_d2_S_x6 indices_12_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf9_readInputs_U0_indices_12_read), + .if_dout(indices_12_c_dout), + .if_full_n(indices_12_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf9_get_next_ijk_U0_indices_1_write), + .if_din(tdf9_get_next_ijk_U0_indices_1_din) +); + +td_fused_top_fifo_w6_d2_S indices_23_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf9_readFilters62_U0_indices_23_read), + .if_dout(indices_23_c_dout), + .if_full_n(indices_23_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf9_get_next_ijk_U0_indices_2_out_write), + .if_din(tdf9_get_next_ijk_U0_indices_2_out_din) +); + +td_fused_top_fifo_w6_d7_S_x indices_23_c1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf9_adjust_U0_indices_23_read), + .if_dout(indices_23_c1_dout), + .if_full_n(indices_23_c1_full_n), + .if_write_ce(1'b1), + .if_write(tdf9_get_next_ijk_U0_indices_2_out1_write), + .if_din(tdf9_get_next_ijk_U0_indices_2_out1_din) +); + +td_fused_top_fifo_w4_d7_S_x indices_01_c2_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c2_empty_n), + .if_read_ce(1'b1), + .if_read(tdf9_writeOutputs_unaligned_U0_indices_01_read), + .if_dout(indices_01_c2_dout), + .if_full_n(indices_01_c2_full_n), + .if_write_ce(1'b1), + .if_write(tdf9_readInputs_U0_indices_01_out_write), + .if_din(tdf9_readInputs_U0_indices_01_out_din) +); + +td_fused_top_fifo_w8_d7_S_x indices_12_c3_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c3_empty_n), + .if_read_ce(1'b1), + .if_read(tdf9_writeOutputs_unaligned_U0_indices_12_read), + .if_dout(indices_12_c3_dout), + .if_full_n(indices_12_c3_full_n), + .if_write_ce(1'b1), + .if_write(tdf9_readInputs_U0_indices_12_out_write), + .if_din(tdf9_readInputs_U0_indices_12_out_din) +); + +td_fused_top_fifo_w16_d2_S_x6 tmp_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(tmp_channel_empty_n), + .if_read_ce(1'b1), + .if_read(Block_entry_proc_proc429_U0_ap_ready), + .if_dout(tmp_channel_dout), + .if_full_n(tmp_channel_full_n), + .if_write_ce(1'b1), + .if_write(tdf9_accum_2_U0_ap_done), + .if_din(tdf9_accum_2_U0_accum_in_2) +); + +td_fused_top_fifo_w16_d2_S_x6 sums_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(sums_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf9_adjust_U0_ap_ready), + .if_dout(sums_0_dout), + .if_full_n(sums_0_full_n), + .if_write_ce(1'b1), + .if_write(Block_entry_proc_proc429_U0_ap_done), + .if_din(Block_entry_proc_proc429_U0_ap_return) +); + +td_fused_top_fifo_w16_d2_S_x6 outputs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(outputs_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf9_writeOutputs_unaligned_U0_ap_ready), + .if_dout(outputs_0_dout), + .if_full_n(outputs_0_full_n), + .if_write_ce(1'b1), + .if_write(tdf9_adjust_U0_ap_done), + .if_din(tdf9_adjust_U0_ap_return) +); + +td_fused_top_start_for_tdf9_readFilters62_U0 start_for_tdf9_readFilters62_U0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(start_for_tdf9_readFilters62_U0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf9_readFilters62_U0_ap_ready), + .if_dout(start_for_tdf9_readFilters62_U0_dout), + .if_full_n(start_for_tdf9_readFilters62_U0_full_n), + .if_write_ce(1'b1), + .if_write(tdf9_get_next_ijk_U0_start_write), + .if_din(start_for_tdf9_readFilters62_U0_din) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf9_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf9_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf9_get_next_ijk_U0_ap_ready <= ap_sync_tdf9_get_next_ijk_U0_ap_ready; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf9_readInputs_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf9_readInputs_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf9_readInputs_U0_ap_ready <= ap_sync_tdf9_readInputs_U0_ap_ready; + end + end +end + +assign Block_entry_proc_proc429_U0_ap_continue = sums_0_full_n; + +assign Block_entry_proc_proc429_U0_ap_start = tmp_channel_empty_n; + +assign Block_entry_proc_proc429_U0_start_full_n = 1'b1; + +assign Block_entry_proc_proc429_U0_start_write = 1'b0; + +assign adjustments_address0 = tdf9_adjust_U0_adjustments_address0; + +assign adjustments_address1 = 6'd0; + +assign adjustments_ce0 = tdf9_adjust_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_channel_done_accum1_out_0 = tdf9_accum_1_U0_ap_done; + +assign ap_channel_done_ifmap_vec_0_0 = tdf9_readInputs_U0_ap_done; + +assign ap_channel_done_outputs_0 = tdf9_adjust_U0_ap_done; + +assign ap_channel_done_products_0 = tdf9_dot_product_U0_ap_done; + +assign ap_channel_done_sums_0 = Block_entry_proc_proc429_U0_ap_done; + +assign ap_channel_done_tmp_channel = tdf9_accum_2_U0_ap_done; + +assign ap_channel_done_weight_vecs_0_0_0 = tdf9_readFilters62_U0_ap_done; + +assign ap_done = tdf9_writeOutputs_unaligned_U0_ap_done; + +assign ap_idle = (tdf9_writeOutputs_unaligned_U0_ap_idle & tdf9_readInputs_U0_ap_idle & tdf9_readFilters62_U0_ap_idle & tdf9_get_next_ijk_U0_ap_idle & tdf9_dot_product_U0_ap_idle & tdf9_adjust_U0_ap_idle & tdf9_accum_2_U0_ap_idle & tdf9_accum_1_U0_ap_idle & (outputs_0_empty_n ^ 1'b1) & (sums_0_empty_n ^ 1'b1) & (tmp_channel_empty_n ^ 1'b1) & (products_0_t_empty_n ^ 1'b1) & (weight_vecs_0_0_0_t_empty_n ^ 1'b1) & (ifmap_vec_0_0_t_empty_n ^ 1'b1) & (1'b1 ^ accum1_out_0_t_empty_n) & Block_entry_proc_proc429_U0_ap_idle); + +assign ap_ready = ap_sync_ready; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = tdf9_writeOutputs_unaligned_U0_ap_done; + +assign ap_sync_ready = (ap_sync_tdf9_readInputs_U0_ap_ready & ap_sync_tdf9_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf9_get_next_ijk_U0_ap_ready = (tdf9_get_next_ijk_U0_ap_ready | ap_sync_reg_tdf9_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf9_readInputs_U0_ap_ready = (tdf9_readInputs_U0_ap_ready | ap_sync_reg_tdf9_readInputs_U0_ap_ready); + +assign filter_data_address0 = tdf9_readFilters62_U0_filter_data_address0; + +assign filter_data_address1 = 14'd0; + +assign filter_data_ce0 = tdf9_readFilters62_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = tdf9_readInputs_U0_in_data_address0; + +assign in_data_address1 = 14'd0; + +assign in_data_ce0 = tdf9_readInputs_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = tdf9_readInputs_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 12'd0; + +assign out_data_address1 = tdf9_writeOutputs_unaligned_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = tdf9_writeOutputs_unaligned_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = tdf9_writeOutputs_unaligned_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = tdf9_writeOutputs_unaligned_U0_out_data_we1; + +assign out_data_write = tdf9_writeOutputs_unaligned_U0_out_data_write; + +assign products_0_t_d1 = 16'd0; + +assign products_0_t_we1 = 1'b0; + +assign start_for_tdf9_readFilters62_U0_din = 1'b1; + +assign tdf9_accum_1_U0_accum_out_full_n = accum1_out_0_i_full_n; + +assign tdf9_accum_1_U0_ap_continue = accum1_out_0_i_full_n; + +assign tdf9_accum_1_U0_ap_start = products_0_t_empty_n; + +assign tdf9_accum_1_U0_start_full_n = 1'b1; + +assign tdf9_accum_1_U0_start_write = 1'b0; + +assign tdf9_accum_2_U0_ap_continue = tmp_channel_full_n; + +assign tdf9_accum_2_U0_ap_start = accum1_out_0_t_empty_n; + +assign tdf9_accum_2_U0_start_full_n = 1'b1; + +assign tdf9_accum_2_U0_start_write = 1'b0; + +assign tdf9_adjust_U0_ap_continue = outputs_0_full_n; + +assign tdf9_adjust_U0_ap_start = sums_0_empty_n; + +assign tdf9_adjust_U0_start_full_n = 1'b1; + +assign tdf9_adjust_U0_start_write = 1'b0; + +assign tdf9_dot_product_U0_ap_continue = products_0_i_full_n; + +assign tdf9_dot_product_U0_ap_start = (weight_vecs_0_0_0_t_empty_n & ifmap_vec_0_0_t_empty_n); + +assign tdf9_dot_product_U0_products_0_full_n = products_0_i_full_n; + +assign tdf9_dot_product_U0_start_full_n = 1'b1; + +assign tdf9_dot_product_U0_start_write = 1'b0; + +assign tdf9_get_next_ijk_U0_ap_continue = 1'b1; + +assign tdf9_get_next_ijk_U0_ap_start = ((ap_sync_reg_tdf9_get_next_ijk_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf9_readFilters62_U0_ap_continue = weight_vecs_0_0_0_i_full_n; + +assign tdf9_readFilters62_U0_ap_start = start_for_tdf9_readFilters62_U0_empty_n; + +assign tdf9_readFilters62_U0_start_full_n = 1'b1; + +assign tdf9_readFilters62_U0_start_write = 1'b0; + +assign tdf9_readFilters62_U0_weight_vecs_0_0_0_full_n = weight_vecs_0_0_0_i_full_n; + +assign tdf9_readInputs_U0_ap_continue = ifmap_vec_0_0_i_full_n; + +assign tdf9_readInputs_U0_ap_start = ((ap_sync_reg_tdf9_readInputs_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf9_readInputs_U0_ifmap_vec_0_0_full_n = ifmap_vec_0_0_i_full_n; + +assign tdf9_readInputs_U0_in_data_full_n = in_data_empty_n; + +assign tdf9_readInputs_U0_in_data_write = 1'b0; + +assign tdf9_readInputs_U0_start_full_n = 1'b1; + +assign tdf9_readInputs_U0_start_write = 1'b0; + +assign tdf9_writeOutputs_unaligned_U0_ap_continue = ap_continue; + +assign tdf9_writeOutputs_unaligned_U0_ap_start = outputs_0_empty_n; + +assign tdf9_writeOutputs_unaligned_U0_out_data_full_n = out_data_full_n; + +assign tdf9_writeOutputs_unaligned_U0_out_data_write = 1'b0; + +assign tdf9_writeOutputs_unaligned_U0_start_full_n = 1'b1; + +assign tdf9_writeOutputs_unaligned_U0_start_write = 1'b0; + +endmodule //td_fused_top_dataflow_in_loop_TOP_LOOP37360 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37360_weight_vecs_0_0_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 9; +parameter MEM_SIZE = 512; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37360_weight_vecs_0_0_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd512; +parameter AddressWidth = 32'd9; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37360_weight_vecs_0_0_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37360_weight_vecs_0_0_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37360_weight_vecs_0_0_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 8, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP37360_weight_vecs_0_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37360_weight_vecs_0_0_0_memcore_U ( + .reset ( reset ), + .clk ( clk ), + .address0 ( memcore_iaddr ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + .address1 ( memcore_taddr ), + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .d1 ( t_d0 ), + .q1 ( t_q0 ) + +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37454_accum1_out_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 3; +parameter MEM_SIZE = 8; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37454_accum1_out_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd8; +parameter AddressWidth = 32'd3; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37454_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37454_accum1_out_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37454_accum1_out_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 3, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37454_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37454_accum1_out_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37454_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37454_accum1_out_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37454_ifmap_vec_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 9; +parameter MEM_SIZE = 288; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37454_ifmap_vec_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd288; +parameter AddressWidth = 32'd9; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37454_ifmap_vec_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37454_ifmap_vec_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37454_ifmap_vec +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 9, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37454_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37454_ifmap_vec_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37454_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37454_ifmap_vec_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37454_products_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 9; +parameter MEM_SIZE = 288; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37454_products_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd288; +parameter AddressWidth = 32'd9; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37454_products_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37454_products_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37454_products_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 9, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire [AddressWidth-1:0] i_address1, + output wire [DataWidth-1:0] i_q1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire [AddressWidth-1:0] t_address1, + output wire [DataWidth-1:0] t_q1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_q1_0, buf_q1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37454_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37454_products_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .q1 ( buf_q1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37454_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37454_products_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .q1 ( buf_q1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign i_q1 = (prev_iptr == 1'b1 ? buf_q1_1 : buf_q1_0); +assign t_q1 = reg_valid1 ? reg_q1 : (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// reg_q1 and reg_valid1 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q1 <= 1'b0; + reg_valid1 <= 1'b0; + end else if (!t_ce1 && !reg_valid1) begin + reg_q1 <= (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + reg_valid1 <= 1'b1; + end else if (t_ce1) begin + reg_valid1 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37454 ( + ap_clk, + ap_rst, + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + ap_start, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +input ap_clk; +input ap_rst; +output [12:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [12:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [16:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [16:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [7:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [7:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +output [13:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [13:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +input ap_start; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +wire [15:0] ifmap_vec_i_q0; +wire [15:0] ifmap_vec_t_q0; +wire [15:0] weight_vecs_0_i_q0; +wire [15:0] weight_vecs_0_t_q0; +wire [15:0] products_0_i_q0; +wire [15:0] products_0_i_q1; +wire [15:0] products_0_t_q0; +wire [15:0] products_0_t_q1; +wire [15:0] accum1_out_0_i_q0; +wire [15:0] accum1_out_0_t_q0; +wire tdf8_get_next_ijk_U0_ap_start; +wire tdf8_get_next_ijk_U0_ap_done; +wire tdf8_get_next_ijk_U0_ap_continue; +wire tdf8_get_next_ijk_U0_ap_idle; +wire tdf8_get_next_ijk_U0_ap_ready; +wire tdf8_get_next_ijk_U0_start_out; +wire tdf8_get_next_ijk_U0_start_write; +wire [7:0] tdf8_get_next_ijk_U0_input_indices_2_out_din; +wire tdf8_get_next_ijk_U0_input_indices_2_out_write; +wire [7:0] tdf8_get_next_ijk_U0_input_indices_2_out1_din; +wire tdf8_get_next_ijk_U0_input_indices_2_out1_write; +wire [3:0] tdf8_get_next_ijk_U0_output_indices_0_din; +wire tdf8_get_next_ijk_U0_output_indices_0_write; +wire [7:0] tdf8_get_next_ijk_U0_output_indices_1_din; +wire tdf8_get_next_ijk_U0_output_indices_1_write; +wire tdf8_get_next_ijk_U0_resetMaximum_din; +wire tdf8_get_next_ijk_U0_resetMaximum_write; +wire tdf8_get_next_ijk_U0_storeOutput_din; +wire tdf8_get_next_ijk_U0_storeOutput_write; +wire [15:0] tdf8_get_next_ijk_U0_ap_return_0; +wire [15:0] tdf8_get_next_ijk_U0_ap_return_1; +wire ap_channel_done_input_indices_1; +wire input_indices_1_full_n; +reg ap_sync_reg_channel_write_input_indices_1; +wire ap_sync_channel_write_input_indices_1; +wire ap_channel_done_input_indices_0; +wire input_indices_0_full_n; +reg ap_sync_reg_channel_write_input_indices_0; +wire ap_sync_channel_write_input_indices_0; +wire tdf8_readInputs57_U0_ap_start; +wire tdf8_readInputs57_U0_ap_done; +wire tdf8_readInputs57_U0_ap_continue; +wire tdf8_readInputs57_U0_ap_idle; +wire tdf8_readInputs57_U0_ap_ready; +wire [12:0] tdf8_readInputs57_U0_in_data_address0; +wire tdf8_readInputs57_U0_in_data_ce0; +wire [8:0] tdf8_readInputs57_U0_ifmap_vec_address0; +wire tdf8_readInputs57_U0_ifmap_vec_ce0; +wire tdf8_readInputs57_U0_ifmap_vec_we0; +wire [15:0] tdf8_readInputs57_U0_ifmap_vec_d0; +wire [8:0] tdf8_readInputs57_U0_ifmap_vec_address1; +wire tdf8_readInputs57_U0_ifmap_vec_ce1; +wire tdf8_readInputs57_U0_ifmap_vec_we1; +wire [15:0] tdf8_readInputs57_U0_ifmap_vec_d1; +wire tdf8_readInputs57_U0_in_data_full_n; +wire tdf8_readInputs57_U0_in_data_write; +wire ap_channel_done_ifmap_vec; +wire tdf8_readInputs57_U0_ifmap_vec_full_n; +wire tdf8_readFilters56_U0_ap_start; +wire tdf8_readFilters56_U0_ap_done; +wire tdf8_readFilters56_U0_ap_continue; +wire tdf8_readFilters56_U0_ap_idle; +wire tdf8_readFilters56_U0_ap_ready; +wire [16:0] tdf8_readFilters56_U0_filter_data_address0; +wire tdf8_readFilters56_U0_filter_data_ce0; +wire tdf8_readFilters56_U0_input_indices_23_read; +wire [8:0] tdf8_readFilters56_U0_weight_vecs_0_address0; +wire tdf8_readFilters56_U0_weight_vecs_0_ce0; +wire tdf8_readFilters56_U0_weight_vecs_0_we0; +wire [15:0] tdf8_readFilters56_U0_weight_vecs_0_d0; +wire ap_channel_done_weight_vecs_0; +wire tdf8_readFilters56_U0_weight_vecs_0_full_n; +wire tdf8_dot_product_U0_ap_start; +wire tdf8_dot_product_U0_ap_done; +wire tdf8_dot_product_U0_ap_continue; +wire tdf8_dot_product_U0_ap_idle; +wire tdf8_dot_product_U0_ap_ready; +wire [8:0] tdf8_dot_product_U0_ifmap_vec_address0; +wire tdf8_dot_product_U0_ifmap_vec_ce0; +wire [8:0] tdf8_dot_product_U0_weight_vecs_0_address0; +wire tdf8_dot_product_U0_weight_vecs_0_ce0; +wire [8:0] tdf8_dot_product_U0_products_0_address0; +wire tdf8_dot_product_U0_products_0_ce0; +wire tdf8_dot_product_U0_products_0_we0; +wire [15:0] tdf8_dot_product_U0_products_0_d0; +wire ap_channel_done_products_0; +wire tdf8_dot_product_U0_products_0_full_n; +wire tdf8_accum_1_U0_ap_start; +wire tdf8_accum_1_U0_ap_done; +wire tdf8_accum_1_U0_ap_continue; +wire tdf8_accum_1_U0_ap_idle; +wire tdf8_accum_1_U0_ap_ready; +wire [8:0] tdf8_accum_1_U0_accum_in_0_address0; +wire tdf8_accum_1_U0_accum_in_0_ce0; +wire [8:0] tdf8_accum_1_U0_accum_in_0_address1; +wire tdf8_accum_1_U0_accum_in_0_ce1; +wire [2:0] tdf8_accum_1_U0_accum_out_address0; +wire tdf8_accum_1_U0_accum_out_ce0; +wire tdf8_accum_1_U0_accum_out_we0; +wire [15:0] tdf8_accum_1_U0_accum_out_d0; +wire [2:0] tdf8_accum_1_U0_accum_out_address1; +wire tdf8_accum_1_U0_accum_out_ce1; +wire tdf8_accum_1_U0_accum_out_we1; +wire [15:0] tdf8_accum_1_U0_accum_out_d1; +wire ap_channel_done_accum1_out_0; +wire tdf8_accum_1_U0_accum_out_full_n; +wire tdf8_accum_2_U0_ap_start; +wire tdf8_accum_2_U0_ap_done; +wire tdf8_accum_2_U0_ap_continue; +wire tdf8_accum_2_U0_ap_idle; +wire tdf8_accum_2_U0_ap_ready; +wire [15:0] tdf8_accum_2_U0_accum_in_4; +wire tdf8_accum_2_U0_accum_in_4_ap_vld; +wire [2:0] tdf8_accum_2_U0_accum_in_address0; +wire tdf8_accum_2_U0_accum_in_ce0; +wire ap_channel_done_tmp_channel; +wire tmp_channel_full_n; +wire Block_entry_proc_proc424_U0_ap_start; +wire Block_entry_proc_proc424_U0_ap_done; +wire Block_entry_proc_proc424_U0_ap_continue; +wire Block_entry_proc_proc424_U0_ap_idle; +wire Block_entry_proc_proc424_U0_ap_ready; +wire [15:0] Block_entry_proc_proc424_U0_ap_return; +wire ap_channel_done_sums_0; +wire sums_0_full_n; +wire tdf8_adjust_U0_ap_start; +wire tdf8_adjust_U0_ap_done; +wire tdf8_adjust_U0_ap_continue; +wire tdf8_adjust_U0_ap_idle; +wire tdf8_adjust_U0_ap_ready; +wire [7:0] tdf8_adjust_U0_adjustments_address0; +wire tdf8_adjust_U0_adjustments_ce0; +wire tdf8_adjust_U0_input_indices_23_read; +wire [15:0] tdf8_adjust_U0_ap_return; +wire ap_channel_done_outputs_0; +wire outputs_0_full_n; +wire tdf8_poolOutputs_U0_ap_start; +wire tdf8_poolOutputs_U0_ap_done; +wire tdf8_poolOutputs_U0_ap_continue; +wire tdf8_poolOutputs_U0_ap_idle; +wire tdf8_poolOutputs_U0_ap_ready; +wire tdf8_poolOutputs_U0_output_indices_04_read; +wire tdf8_poolOutputs_U0_output_indices_15_read; +wire tdf8_poolOutputs_U0_resetMaximum6_read; +wire tdf8_poolOutputs_U0_storeOutput7_read; +wire [13:0] tdf8_poolOutputs_U0_out_data_address1; +wire tdf8_poolOutputs_U0_out_data_ce1; +wire tdf8_poolOutputs_U0_out_data_we1; +wire [63:0] tdf8_poolOutputs_U0_out_data_d1; +wire tdf8_poolOutputs_U0_out_data_full_n; +wire tdf8_poolOutputs_U0_out_data_write; +wire ap_sync_continue; +wire ifmap_vec_i_full_n; +wire ifmap_vec_t_empty_n; +wire weight_vecs_0_i_full_n; +wire weight_vecs_0_t_empty_n; +wire products_0_i_full_n; +wire products_0_t_empty_n; +wire [15:0] products_0_t_d1; +wire products_0_t_we1; +wire accum1_out_0_i_full_n; +wire accum1_out_0_t_empty_n; +wire input_indices_23_c_full_n; +wire [7:0] input_indices_23_c_dout; +wire input_indices_23_c_empty_n; +wire input_indices_23_c1_full_n; +wire [7:0] input_indices_23_c1_dout; +wire input_indices_23_c1_empty_n; +wire output_indices_04_c_full_n; +wire [3:0] output_indices_04_c_dout; +wire output_indices_04_c_empty_n; +wire output_indices_15_c_full_n; +wire [7:0] output_indices_15_c_dout; +wire output_indices_15_c_empty_n; +wire [0:0] resetMaximum6_c_din; +wire resetMaximum6_c_full_n; +wire [0:0] resetMaximum6_c_dout; +wire resetMaximum6_c_empty_n; +wire [0:0] storeOutput7_c_din; +wire storeOutput7_c_full_n; +wire [0:0] storeOutput7_c_dout; +wire storeOutput7_c_empty_n; +wire [15:0] input_indices_0_dout; +wire input_indices_0_empty_n; +wire [15:0] input_indices_1_dout; +wire input_indices_1_empty_n; +wire [15:0] tmp_channel_dout; +wire tmp_channel_empty_n; +wire [15:0] sums_0_dout; +wire sums_0_empty_n; +wire [15:0] outputs_0_dout; +wire outputs_0_empty_n; +wire ap_sync_done; +wire ap_sync_ready; +reg ap_sync_reg_tdf8_get_next_ijk_U0_ap_ready; +wire ap_sync_tdf8_get_next_ijk_U0_ap_ready; +reg ap_sync_reg_tdf8_readInputs57_U0_ap_ready; +wire ap_sync_tdf8_readInputs57_U0_ap_ready; +wire [0:0] start_for_tdf8_readFilters56_U0_din; +wire start_for_tdf8_readFilters56_U0_full_n; +wire [0:0] start_for_tdf8_readFilters56_U0_dout; +wire start_for_tdf8_readFilters56_U0_empty_n; +wire tdf8_readInputs57_U0_start_full_n; +wire tdf8_readInputs57_U0_start_write; +wire tdf8_readFilters56_U0_start_full_n; +wire tdf8_readFilters56_U0_start_write; +wire tdf8_dot_product_U0_start_full_n; +wire tdf8_dot_product_U0_start_write; +wire tdf8_accum_1_U0_start_full_n; +wire tdf8_accum_1_U0_start_write; +wire tdf8_accum_2_U0_start_full_n; +wire tdf8_accum_2_U0_start_write; +wire Block_entry_proc_proc424_U0_start_full_n; +wire Block_entry_proc_proc424_U0_start_write; +wire tdf8_adjust_U0_start_full_n; +wire tdf8_adjust_U0_start_write; +wire tdf8_poolOutputs_U0_start_full_n; +wire tdf8_poolOutputs_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_sync_reg_channel_write_input_indices_1 = 1'b0; +#0 ap_sync_reg_channel_write_input_indices_0 = 1'b0; +#0 ap_sync_reg_tdf8_get_next_ijk_U0_ap_ready = 1'b0; +#0 ap_sync_reg_tdf8_readInputs57_U0_ap_ready = 1'b0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP37454_ifmap_vec #( + .DataWidth( 16 ), + .AddressRange( 288 ), + .AddressWidth( 9 )) +ifmap_vec_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf8_readInputs57_U0_ap_done), + .i_full_n(ifmap_vec_i_full_n), + .i_ce0(tdf8_readInputs57_U0_ifmap_vec_ce0), + .i_we0(tdf8_readInputs57_U0_ifmap_vec_we0), + .i_address0(tdf8_readInputs57_U0_ifmap_vec_address0), + .i_d0(tdf8_readInputs57_U0_ifmap_vec_d0), + .i_q0(ifmap_vec_i_q0), + .i_ce1(tdf8_readInputs57_U0_ifmap_vec_ce1), + .i_we1(tdf8_readInputs57_U0_ifmap_vec_we1), + .i_address1(tdf8_readInputs57_U0_ifmap_vec_address1), + .i_d1(tdf8_readInputs57_U0_ifmap_vec_d1), + .t_ce(1'b1), + .t_read(tdf8_dot_product_U0_ap_ready), + .t_empty_n(ifmap_vec_t_empty_n), + .t_ce0(tdf8_dot_product_U0_ifmap_vec_ce0), + .t_we0(1'b0), + .t_address0(tdf8_dot_product_U0_ifmap_vec_address0), + .t_d0(16'd0), + .t_q0(ifmap_vec_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(9'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37454_weight_vecs_0 #( + .DataWidth( 16 ), + .AddressRange( 288 ), + .AddressWidth( 9 )) +weight_vecs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf8_readFilters56_U0_ap_done), + .i_full_n(weight_vecs_0_i_full_n), + .i_ce0(tdf8_readFilters56_U0_weight_vecs_0_ce0), + .i_we0(tdf8_readFilters56_U0_weight_vecs_0_we0), + .i_address0(tdf8_readFilters56_U0_weight_vecs_0_address0), + .i_d0(tdf8_readFilters56_U0_weight_vecs_0_d0), + .i_q0(weight_vecs_0_i_q0), + .t_ce(1'b1), + .t_read(tdf8_dot_product_U0_ap_ready), + .t_empty_n(weight_vecs_0_t_empty_n), + .t_ce0(tdf8_dot_product_U0_weight_vecs_0_ce0), + .t_we0(1'b0), + .t_address0(tdf8_dot_product_U0_weight_vecs_0_address0), + .t_d0(16'd0), + .t_q0(weight_vecs_0_t_q0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37454_products_0 #( + .DataWidth( 16 ), + .AddressRange( 288 ), + .AddressWidth( 9 )) +products_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf8_dot_product_U0_ap_done), + .i_full_n(products_0_i_full_n), + .i_ce0(tdf8_dot_product_U0_products_0_ce0), + .i_we0(tdf8_dot_product_U0_products_0_we0), + .i_address0(tdf8_dot_product_U0_products_0_address0), + .i_d0(tdf8_dot_product_U0_products_0_d0), + .i_q0(products_0_i_q0), + .i_ce1(1'b0), + .i_address1(9'd0), + .i_q1(products_0_i_q1), + .t_ce(1'b1), + .t_read(tdf8_accum_1_U0_ap_ready), + .t_empty_n(products_0_t_empty_n), + .t_ce0(tdf8_accum_1_U0_accum_in_0_ce0), + .t_we0(1'b0), + .t_address0(tdf8_accum_1_U0_accum_in_0_address0), + .t_d0(16'd0), + .t_q0(products_0_t_q0), + .t_ce1(tdf8_accum_1_U0_accum_in_0_ce1), + .t_address1(tdf8_accum_1_U0_accum_in_0_address1), + .t_q1(products_0_t_q1) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37454_accum1_out_0 #( + .DataWidth( 16 ), + .AddressRange( 8 ), + .AddressWidth( 3 )) +accum1_out_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf8_accum_1_U0_ap_done), + .i_full_n(accum1_out_0_i_full_n), + .i_ce0(tdf8_accum_1_U0_accum_out_ce0), + .i_we0(tdf8_accum_1_U0_accum_out_we0), + .i_address0(tdf8_accum_1_U0_accum_out_address0), + .i_d0(tdf8_accum_1_U0_accum_out_d0), + .i_q0(accum1_out_0_i_q0), + .i_ce1(tdf8_accum_1_U0_accum_out_ce1), + .i_we1(tdf8_accum_1_U0_accum_out_we1), + .i_address1(tdf8_accum_1_U0_accum_out_address1), + .i_d1(tdf8_accum_1_U0_accum_out_d1), + .t_ce(1'b1), + .t_read(tdf8_accum_2_U0_ap_ready), + .t_empty_n(accum1_out_0_t_empty_n), + .t_ce0(tdf8_accum_2_U0_accum_in_ce0), + .t_we0(1'b0), + .t_address0(tdf8_accum_2_U0_accum_in_address0), + .t_d0(16'd0), + .t_q0(accum1_out_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(3'd0), + .t_d1(16'd0) +); + +td_fused_top_tdf8_get_next_ijk tdf8_get_next_ijk_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf8_get_next_ijk_U0_ap_start), + .start_full_n(start_for_tdf8_readFilters56_U0_full_n), + .ap_done(tdf8_get_next_ijk_U0_ap_done), + .ap_continue(tdf8_get_next_ijk_U0_ap_continue), + .ap_idle(tdf8_get_next_ijk_U0_ap_idle), + .ap_ready(tdf8_get_next_ijk_U0_ap_ready), + .start_out(tdf8_get_next_ijk_U0_start_out), + .start_write(tdf8_get_next_ijk_U0_start_write), + .input_indices_2_out_din(tdf8_get_next_ijk_U0_input_indices_2_out_din), + .input_indices_2_out_full_n(input_indices_23_c_full_n), + .input_indices_2_out_write(tdf8_get_next_ijk_U0_input_indices_2_out_write), + .input_indices_2_out1_din(tdf8_get_next_ijk_U0_input_indices_2_out1_din), + .input_indices_2_out1_full_n(input_indices_23_c1_full_n), + .input_indices_2_out1_write(tdf8_get_next_ijk_U0_input_indices_2_out1_write), + .output_indices_0_din(tdf8_get_next_ijk_U0_output_indices_0_din), + .output_indices_0_full_n(output_indices_04_c_full_n), + .output_indices_0_write(tdf8_get_next_ijk_U0_output_indices_0_write), + .output_indices_1_din(tdf8_get_next_ijk_U0_output_indices_1_din), + .output_indices_1_full_n(output_indices_15_c_full_n), + .output_indices_1_write(tdf8_get_next_ijk_U0_output_indices_1_write), + .resetMaximum_din(tdf8_get_next_ijk_U0_resetMaximum_din), + .resetMaximum_full_n(resetMaximum6_c_full_n), + .resetMaximum_write(tdf8_get_next_ijk_U0_resetMaximum_write), + .storeOutput_din(tdf8_get_next_ijk_U0_storeOutput_din), + .storeOutput_full_n(storeOutput7_c_full_n), + .storeOutput_write(tdf8_get_next_ijk_U0_storeOutput_write), + .ap_return_0(tdf8_get_next_ijk_U0_ap_return_0), + .ap_return_1(tdf8_get_next_ijk_U0_ap_return_1) +); + +td_fused_top_tdf8_readInputs57 tdf8_readInputs57_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf8_readInputs57_U0_ap_start), + .ap_done(tdf8_readInputs57_U0_ap_done), + .ap_continue(tdf8_readInputs57_U0_ap_continue), + .ap_idle(tdf8_readInputs57_U0_ap_idle), + .ap_ready(tdf8_readInputs57_U0_ap_ready), + .in_data_address0(tdf8_readInputs57_U0_in_data_address0), + .in_data_ce0(tdf8_readInputs57_U0_in_data_ce0), + .in_data_q0(in_data_q0), + .i_13(input_indices_0_dout), + .j_13(input_indices_1_dout), + .ifmap_vec_address0(tdf8_readInputs57_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf8_readInputs57_U0_ifmap_vec_ce0), + .ifmap_vec_we0(tdf8_readInputs57_U0_ifmap_vec_we0), + .ifmap_vec_d0(tdf8_readInputs57_U0_ifmap_vec_d0), + .ifmap_vec_address1(tdf8_readInputs57_U0_ifmap_vec_address1), + .ifmap_vec_ce1(tdf8_readInputs57_U0_ifmap_vec_ce1), + .ifmap_vec_we1(tdf8_readInputs57_U0_ifmap_vec_we1), + .ifmap_vec_d1(tdf8_readInputs57_U0_ifmap_vec_d1) +); + +td_fused_top_tdf8_readFilters56 tdf8_readFilters56_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf8_readFilters56_U0_ap_start), + .ap_done(tdf8_readFilters56_U0_ap_done), + .ap_continue(tdf8_readFilters56_U0_ap_continue), + .ap_idle(tdf8_readFilters56_U0_ap_idle), + .ap_ready(tdf8_readFilters56_U0_ap_ready), + .filter_data_address0(tdf8_readFilters56_U0_filter_data_address0), + .filter_data_ce0(tdf8_readFilters56_U0_filter_data_ce0), + .filter_data_q0(filter_data_q0), + .input_indices_23_dout(input_indices_23_c_dout), + .input_indices_23_empty_n(input_indices_23_c_empty_n), + .input_indices_23_read(tdf8_readFilters56_U0_input_indices_23_read), + .weight_vecs_0_address0(tdf8_readFilters56_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf8_readFilters56_U0_weight_vecs_0_ce0), + .weight_vecs_0_we0(tdf8_readFilters56_U0_weight_vecs_0_we0), + .weight_vecs_0_d0(tdf8_readFilters56_U0_weight_vecs_0_d0) +); + +td_fused_top_tdf8_dot_product tdf8_dot_product_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf8_dot_product_U0_ap_start), + .ap_done(tdf8_dot_product_U0_ap_done), + .ap_continue(tdf8_dot_product_U0_ap_continue), + .ap_idle(tdf8_dot_product_U0_ap_idle), + .ap_ready(tdf8_dot_product_U0_ap_ready), + .ifmap_vec_address0(tdf8_dot_product_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf8_dot_product_U0_ifmap_vec_ce0), + .ifmap_vec_q0(ifmap_vec_t_q0), + .weight_vecs_0_address0(tdf8_dot_product_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf8_dot_product_U0_weight_vecs_0_ce0), + .weight_vecs_0_q0(weight_vecs_0_t_q0), + .products_0_address0(tdf8_dot_product_U0_products_0_address0), + .products_0_ce0(tdf8_dot_product_U0_products_0_ce0), + .products_0_we0(tdf8_dot_product_U0_products_0_we0), + .products_0_d0(tdf8_dot_product_U0_products_0_d0) +); + +td_fused_top_tdf8_accum_1 tdf8_accum_1_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf8_accum_1_U0_ap_start), + .ap_done(tdf8_accum_1_U0_ap_done), + .ap_continue(tdf8_accum_1_U0_ap_continue), + .ap_idle(tdf8_accum_1_U0_ap_idle), + .ap_ready(tdf8_accum_1_U0_ap_ready), + .accum_in_0_address0(tdf8_accum_1_U0_accum_in_0_address0), + .accum_in_0_ce0(tdf8_accum_1_U0_accum_in_0_ce0), + .accum_in_0_q0(products_0_t_q0), + .accum_in_0_address1(tdf8_accum_1_U0_accum_in_0_address1), + .accum_in_0_ce1(tdf8_accum_1_U0_accum_in_0_ce1), + .accum_in_0_q1(products_0_t_q1), + .accum_out_address0(tdf8_accum_1_U0_accum_out_address0), + .accum_out_ce0(tdf8_accum_1_U0_accum_out_ce0), + .accum_out_we0(tdf8_accum_1_U0_accum_out_we0), + .accum_out_d0(tdf8_accum_1_U0_accum_out_d0), + .accum_out_address1(tdf8_accum_1_U0_accum_out_address1), + .accum_out_ce1(tdf8_accum_1_U0_accum_out_ce1), + .accum_out_we1(tdf8_accum_1_U0_accum_out_we1), + .accum_out_d1(tdf8_accum_1_U0_accum_out_d1) +); + +td_fused_top_tdf8_accum_2 tdf8_accum_2_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf8_accum_2_U0_ap_start), + .ap_done(tdf8_accum_2_U0_ap_done), + .ap_continue(tdf8_accum_2_U0_ap_continue), + .ap_idle(tdf8_accum_2_U0_ap_idle), + .ap_ready(tdf8_accum_2_U0_ap_ready), + .accum_in_4(tdf8_accum_2_U0_accum_in_4), + .accum_in_4_ap_vld(tdf8_accum_2_U0_accum_in_4_ap_vld), + .accum_in_address0(tdf8_accum_2_U0_accum_in_address0), + .accum_in_ce0(tdf8_accum_2_U0_accum_in_ce0), + .accum_in_q0(accum1_out_0_t_q0) +); + +td_fused_top_Block_entry_proc_proc424 Block_entry_proc_proc424_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(Block_entry_proc_proc424_U0_ap_start), + .ap_done(Block_entry_proc_proc424_U0_ap_done), + .ap_continue(Block_entry_proc_proc424_U0_ap_continue), + .ap_idle(Block_entry_proc_proc424_U0_ap_idle), + .ap_ready(Block_entry_proc_proc424_U0_ap_ready), + .tmp(tmp_channel_dout), + .ap_return(Block_entry_proc_proc424_U0_ap_return) +); + +td_fused_top_tdf8_adjust tdf8_adjust_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf8_adjust_U0_ap_start), + .ap_done(tdf8_adjust_U0_ap_done), + .ap_continue(tdf8_adjust_U0_ap_continue), + .ap_idle(tdf8_adjust_U0_ap_idle), + .ap_ready(tdf8_adjust_U0_ap_ready), + .sums_read(sums_0_dout), + .adjustments_address0(tdf8_adjust_U0_adjustments_address0), + .adjustments_ce0(tdf8_adjust_U0_adjustments_ce0), + .adjustments_q0(adjustments_q0), + .input_indices_23_dout(input_indices_23_c1_dout), + .input_indices_23_empty_n(input_indices_23_c1_empty_n), + .input_indices_23_read(tdf8_adjust_U0_input_indices_23_read), + .ap_return(tdf8_adjust_U0_ap_return) +); + +td_fused_top_tdf8_poolOutputs tdf8_poolOutputs_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf8_poolOutputs_U0_ap_start), + .ap_done(tdf8_poolOutputs_U0_ap_done), + .ap_continue(tdf8_poolOutputs_U0_ap_continue), + .ap_idle(tdf8_poolOutputs_U0_ap_idle), + .ap_ready(tdf8_poolOutputs_U0_ap_ready), + .output_indices_04_dout(output_indices_04_c_dout), + .output_indices_04_empty_n(output_indices_04_c_empty_n), + .output_indices_04_read(tdf8_poolOutputs_U0_output_indices_04_read), + .output_indices_15_dout(output_indices_15_c_dout), + .output_indices_15_empty_n(output_indices_15_c_empty_n), + .output_indices_15_read(tdf8_poolOutputs_U0_output_indices_15_read), + .resetMaximum6_dout(resetMaximum6_c_dout), + .resetMaximum6_empty_n(resetMaximum6_c_empty_n), + .resetMaximum6_read(tdf8_poolOutputs_U0_resetMaximum6_read), + .storeOutput7_dout(storeOutput7_c_dout), + .storeOutput7_empty_n(storeOutput7_c_empty_n), + .storeOutput7_read(tdf8_poolOutputs_U0_storeOutput7_read), + .p_read(outputs_0_dout), + .out_data_address1(tdf8_poolOutputs_U0_out_data_address1), + .out_data_ce1(tdf8_poolOutputs_U0_out_data_ce1), + .out_data_we1(tdf8_poolOutputs_U0_out_data_we1), + .out_data_d1(tdf8_poolOutputs_U0_out_data_d1) +); + +td_fused_top_fifo_w8_d2_S_x input_indices_23_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_23_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf8_readFilters56_U0_input_indices_23_read), + .if_dout(input_indices_23_c_dout), + .if_full_n(input_indices_23_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf8_get_next_ijk_U0_input_indices_2_out_write), + .if_din(tdf8_get_next_ijk_U0_input_indices_2_out_din) +); + +td_fused_top_fifo_w8_d7_S input_indices_23_c1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_23_c1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf8_adjust_U0_input_indices_23_read), + .if_dout(input_indices_23_c1_dout), + .if_full_n(input_indices_23_c1_full_n), + .if_write_ce(1'b1), + .if_write(tdf8_get_next_ijk_U0_input_indices_2_out1_write), + .if_din(tdf8_get_next_ijk_U0_input_indices_2_out1_din) +); + +td_fused_top_fifo_w4_d8_S_x output_indices_04_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(output_indices_04_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf8_poolOutputs_U0_output_indices_04_read), + .if_dout(output_indices_04_c_dout), + .if_full_n(output_indices_04_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf8_get_next_ijk_U0_output_indices_0_write), + .if_din(tdf8_get_next_ijk_U0_output_indices_0_din) +); + +td_fused_top_fifo_w8_d8_S output_indices_15_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(output_indices_15_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf8_poolOutputs_U0_output_indices_15_read), + .if_dout(output_indices_15_c_dout), + .if_full_n(output_indices_15_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf8_get_next_ijk_U0_output_indices_1_write), + .if_din(tdf8_get_next_ijk_U0_output_indices_1_din) +); + +td_fused_top_fifo_w1_d8_S_x0 resetMaximum6_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(resetMaximum6_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf8_poolOutputs_U0_resetMaximum6_read), + .if_dout(resetMaximum6_c_dout), + .if_full_n(resetMaximum6_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf8_get_next_ijk_U0_resetMaximum_write), + .if_din(resetMaximum6_c_din) +); + +td_fused_top_fifo_w1_d8_S_x0 storeOutput7_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(storeOutput7_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf8_poolOutputs_U0_storeOutput7_read), + .if_dout(storeOutput7_c_dout), + .if_full_n(storeOutput7_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf8_get_next_ijk_U0_storeOutput_write), + .if_din(storeOutput7_c_din) +); + +td_fused_top_fifo_w16_d2_S_x5 input_indices_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf8_readInputs57_U0_ap_ready), + .if_dout(input_indices_0_dout), + .if_full_n(input_indices_0_full_n), + .if_write_ce(1'b1), + .if_write(ap_channel_done_input_indices_0), + .if_din(tdf8_get_next_ijk_U0_ap_return_0) +); + +td_fused_top_fifo_w16_d2_S_x5 input_indices_1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf8_readInputs57_U0_ap_ready), + .if_dout(input_indices_1_dout), + .if_full_n(input_indices_1_full_n), + .if_write_ce(1'b1), + .if_write(ap_channel_done_input_indices_1), + .if_din(tdf8_get_next_ijk_U0_ap_return_1) +); + +td_fused_top_fifo_w16_d2_S_x5 tmp_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(tmp_channel_empty_n), + .if_read_ce(1'b1), + .if_read(Block_entry_proc_proc424_U0_ap_ready), + .if_dout(tmp_channel_dout), + .if_full_n(tmp_channel_full_n), + .if_write_ce(1'b1), + .if_write(tdf8_accum_2_U0_ap_done), + .if_din(tdf8_accum_2_U0_accum_in_4) +); + +td_fused_top_fifo_w16_d2_S_x5 sums_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(sums_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf8_adjust_U0_ap_ready), + .if_dout(sums_0_dout), + .if_full_n(sums_0_full_n), + .if_write_ce(1'b1), + .if_write(Block_entry_proc_proc424_U0_ap_done), + .if_din(Block_entry_proc_proc424_U0_ap_return) +); + +td_fused_top_fifo_w16_d2_S_x5 outputs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(outputs_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf8_poolOutputs_U0_ap_ready), + .if_dout(outputs_0_dout), + .if_full_n(outputs_0_full_n), + .if_write_ce(1'b1), + .if_write(tdf8_adjust_U0_ap_done), + .if_din(tdf8_adjust_U0_ap_return) +); + +td_fused_top_start_for_tdf8_readFilters56_U0 start_for_tdf8_readFilters56_U0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(start_for_tdf8_readFilters56_U0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf8_readFilters56_U0_ap_ready), + .if_dout(start_for_tdf8_readFilters56_U0_dout), + .if_full_n(start_for_tdf8_readFilters56_U0_full_n), + .if_write_ce(1'b1), + .if_write(tdf8_get_next_ijk_U0_start_write), + .if_din(start_for_tdf8_readFilters56_U0_din) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_input_indices_0 <= 1'b0; + end else begin + if (((tdf8_get_next_ijk_U0_ap_done & tdf8_get_next_ijk_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_input_indices_0 <= 1'b0; + end else begin + ap_sync_reg_channel_write_input_indices_0 <= ap_sync_channel_write_input_indices_0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_input_indices_1 <= 1'b0; + end else begin + if (((tdf8_get_next_ijk_U0_ap_done & tdf8_get_next_ijk_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_input_indices_1 <= 1'b0; + end else begin + ap_sync_reg_channel_write_input_indices_1 <= ap_sync_channel_write_input_indices_1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf8_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf8_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf8_get_next_ijk_U0_ap_ready <= ap_sync_tdf8_get_next_ijk_U0_ap_ready; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf8_readInputs57_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf8_readInputs57_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf8_readInputs57_U0_ap_ready <= ap_sync_tdf8_readInputs57_U0_ap_ready; + end + end +end + +assign Block_entry_proc_proc424_U0_ap_continue = sums_0_full_n; + +assign Block_entry_proc_proc424_U0_ap_start = tmp_channel_empty_n; + +assign Block_entry_proc_proc424_U0_start_full_n = 1'b1; + +assign Block_entry_proc_proc424_U0_start_write = 1'b0; + +assign adjustments_address0 = tdf8_adjust_U0_adjustments_address0; + +assign adjustments_address1 = 8'd0; + +assign adjustments_ce0 = tdf8_adjust_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_channel_done_accum1_out_0 = tdf8_accum_1_U0_ap_done; + +assign ap_channel_done_ifmap_vec = tdf8_readInputs57_U0_ap_done; + +assign ap_channel_done_input_indices_0 = (tdf8_get_next_ijk_U0_ap_done & (ap_sync_reg_channel_write_input_indices_0 ^ 1'b1)); + +assign ap_channel_done_input_indices_1 = (tdf8_get_next_ijk_U0_ap_done & (ap_sync_reg_channel_write_input_indices_1 ^ 1'b1)); + +assign ap_channel_done_outputs_0 = tdf8_adjust_U0_ap_done; + +assign ap_channel_done_products_0 = tdf8_dot_product_U0_ap_done; + +assign ap_channel_done_sums_0 = Block_entry_proc_proc424_U0_ap_done; + +assign ap_channel_done_tmp_channel = tdf8_accum_2_U0_ap_done; + +assign ap_channel_done_weight_vecs_0 = tdf8_readFilters56_U0_ap_done; + +assign ap_done = tdf8_poolOutputs_U0_ap_done; + +assign ap_idle = (tdf8_readInputs57_U0_ap_idle & tdf8_readFilters56_U0_ap_idle & tdf8_poolOutputs_U0_ap_idle & tdf8_get_next_ijk_U0_ap_idle & tdf8_dot_product_U0_ap_idle & tdf8_adjust_U0_ap_idle & tdf8_accum_2_U0_ap_idle & tdf8_accum_1_U0_ap_idle & (outputs_0_empty_n ^ 1'b1) & (sums_0_empty_n ^ 1'b1) & (tmp_channel_empty_n ^ 1'b1) & (input_indices_1_empty_n ^ 1'b1) & (input_indices_0_empty_n ^ 1'b1) & (products_0_t_empty_n ^ 1'b1) & (weight_vecs_0_t_empty_n ^ 1'b1) & (ifmap_vec_t_empty_n ^ 1'b1) & (1'b1 ^ accum1_out_0_t_empty_n) & Block_entry_proc_proc424_U0_ap_idle); + +assign ap_ready = ap_sync_ready; + +assign ap_sync_channel_write_input_indices_0 = ((input_indices_0_full_n & ap_channel_done_input_indices_0) | ap_sync_reg_channel_write_input_indices_0); + +assign ap_sync_channel_write_input_indices_1 = ((input_indices_1_full_n & ap_channel_done_input_indices_1) | ap_sync_reg_channel_write_input_indices_1); + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = tdf8_poolOutputs_U0_ap_done; + +assign ap_sync_ready = (ap_sync_tdf8_readInputs57_U0_ap_ready & ap_sync_tdf8_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf8_get_next_ijk_U0_ap_ready = (tdf8_get_next_ijk_U0_ap_ready | ap_sync_reg_tdf8_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf8_readInputs57_U0_ap_ready = (tdf8_readInputs57_U0_ap_ready | ap_sync_reg_tdf8_readInputs57_U0_ap_ready); + +assign filter_data_address0 = tdf8_readFilters56_U0_filter_data_address0; + +assign filter_data_address1 = 17'd0; + +assign filter_data_ce0 = tdf8_readFilters56_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = tdf8_readInputs57_U0_in_data_address0; + +assign in_data_address1 = 13'd0; + +assign in_data_ce0 = tdf8_readInputs57_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = tdf8_readInputs57_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 14'd0; + +assign out_data_address1 = tdf8_poolOutputs_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = tdf8_poolOutputs_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = tdf8_poolOutputs_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = tdf8_poolOutputs_U0_out_data_we1; + +assign out_data_write = tdf8_poolOutputs_U0_out_data_write; + +assign products_0_t_d1 = 16'd0; + +assign products_0_t_we1 = 1'b0; + +assign resetMaximum6_c_din = tdf8_get_next_ijk_U0_resetMaximum_din; + +assign start_for_tdf8_readFilters56_U0_din = 1'b1; + +assign storeOutput7_c_din = tdf8_get_next_ijk_U0_storeOutput_din; + +assign tdf8_accum_1_U0_accum_out_full_n = accum1_out_0_i_full_n; + +assign tdf8_accum_1_U0_ap_continue = accum1_out_0_i_full_n; + +assign tdf8_accum_1_U0_ap_start = products_0_t_empty_n; + +assign tdf8_accum_1_U0_start_full_n = 1'b1; + +assign tdf8_accum_1_U0_start_write = 1'b0; + +assign tdf8_accum_2_U0_ap_continue = tmp_channel_full_n; + +assign tdf8_accum_2_U0_ap_start = accum1_out_0_t_empty_n; + +assign tdf8_accum_2_U0_start_full_n = 1'b1; + +assign tdf8_accum_2_U0_start_write = 1'b0; + +assign tdf8_adjust_U0_ap_continue = outputs_0_full_n; + +assign tdf8_adjust_U0_ap_start = sums_0_empty_n; + +assign tdf8_adjust_U0_start_full_n = 1'b1; + +assign tdf8_adjust_U0_start_write = 1'b0; + +assign tdf8_dot_product_U0_ap_continue = products_0_i_full_n; + +assign tdf8_dot_product_U0_ap_start = (weight_vecs_0_t_empty_n & ifmap_vec_t_empty_n); + +assign tdf8_dot_product_U0_products_0_full_n = products_0_i_full_n; + +assign tdf8_dot_product_U0_start_full_n = 1'b1; + +assign tdf8_dot_product_U0_start_write = 1'b0; + +assign tdf8_get_next_ijk_U0_ap_continue = (ap_sync_channel_write_input_indices_1 & ap_sync_channel_write_input_indices_0); + +assign tdf8_get_next_ijk_U0_ap_start = ((ap_sync_reg_tdf8_get_next_ijk_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf8_poolOutputs_U0_ap_continue = ap_continue; + +assign tdf8_poolOutputs_U0_ap_start = outputs_0_empty_n; + +assign tdf8_poolOutputs_U0_out_data_full_n = out_data_full_n; + +assign tdf8_poolOutputs_U0_out_data_write = 1'b0; + +assign tdf8_poolOutputs_U0_start_full_n = 1'b1; + +assign tdf8_poolOutputs_U0_start_write = 1'b0; + +assign tdf8_readFilters56_U0_ap_continue = weight_vecs_0_i_full_n; + +assign tdf8_readFilters56_U0_ap_start = start_for_tdf8_readFilters56_U0_empty_n; + +assign tdf8_readFilters56_U0_start_full_n = 1'b1; + +assign tdf8_readFilters56_U0_start_write = 1'b0; + +assign tdf8_readFilters56_U0_weight_vecs_0_full_n = weight_vecs_0_i_full_n; + +assign tdf8_readInputs57_U0_ap_continue = ifmap_vec_i_full_n; + +assign tdf8_readInputs57_U0_ap_start = (input_indices_1_empty_n & input_indices_0_empty_n & (ap_sync_reg_tdf8_readInputs57_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf8_readInputs57_U0_ifmap_vec_full_n = ifmap_vec_i_full_n; + +assign tdf8_readInputs57_U0_in_data_full_n = in_data_empty_n; + +assign tdf8_readInputs57_U0_in_data_write = 1'b0; + +assign tdf8_readInputs57_U0_start_full_n = 1'b1; + +assign tdf8_readInputs57_U0_start_write = 1'b0; + +endmodule //td_fused_top_dataflow_in_loop_TOP_LOOP37454 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37454_weight_vecs_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 10; +parameter MEM_SIZE = 576; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37454_weight_vecs_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd576; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37454_weight_vecs_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37454_weight_vecs_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37454_weight_vecs_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 9, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP37454_weight_vecs_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37454_weight_vecs_0_memcore_U ( + .reset ( reset ), + .clk ( clk ), + .address0 ( memcore_iaddr ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + .address1 ( memcore_taddr ), + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .d1 ( t_d0 ), + .q1 ( t_q0 ) + +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37548_accum1_out_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 3; +parameter MEM_SIZE = 8; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37548_accum1_out_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd8; +parameter AddressWidth = 32'd3; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37548_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37548_accum1_out_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37548_accum1_out_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 3, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37548_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37548_accum1_out_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37548_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37548_accum1_out_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37548_ifmap_vec_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 9; +parameter MEM_SIZE = 288; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37548_ifmap_vec_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd288; +parameter AddressWidth = 32'd9; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37548_ifmap_vec_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37548_ifmap_vec_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37548_ifmap_vec +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 9, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37548_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37548_ifmap_vec_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37548_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37548_ifmap_vec_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37548_l2_products_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 6; +parameter MEM_SIZE = 64; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37548_l2_products_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd64; +parameter AddressWidth = 32'd6; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37548_l2_products_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37548_l2_products_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37548_l2_products +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 5, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP37548_l2_products_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37548_l2_products_memcore_U ( + .reset ( reset ), + .clk ( clk ), + .address0 ( memcore_iaddr ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + .address1 ( memcore_taddr ), + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .d1 ( t_d0 ), + .q1 ( t_q0 ) + +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37548_products_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 9; +parameter MEM_SIZE = 288; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37548_products_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd288; +parameter AddressWidth = 32'd9; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37548_products_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37548_products_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37548_products_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 9, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire [AddressWidth-1:0] i_address1, + output wire [DataWidth-1:0] i_q1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire [AddressWidth-1:0] t_address1, + output wire [DataWidth-1:0] t_q1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_q1_0, buf_q1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37548_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37548_products_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .q1 ( buf_q1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37548_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37548_products_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .q1 ( buf_q1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign i_q1 = (prev_iptr == 1'b1 ? buf_q1_1 : buf_q1_0); +assign t_q1 = reg_valid1 ? reg_q1 : (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// reg_q1 and reg_valid1 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q1 <= 1'b0; + reg_valid1 <= 1'b0; + end else if (!t_ce1 && !reg_valid1) begin + reg_q1 <= (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + reg_valid1 <= 1'b1; + end else if (t_ce1) begin + reg_valid1 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37548 ( + ap_clk, + ap_rst, + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + l1_filter_data_address0, + l1_filter_data_ce0, + l1_filter_data_d0, + l1_filter_data_q0, + l1_filter_data_we0, + l1_filter_data_address1, + l1_filter_data_ce1, + l1_filter_data_d1, + l1_filter_data_q1, + l1_filter_data_we1, + l1_adjustments_address0, + l1_adjustments_ce0, + l1_adjustments_d0, + l1_adjustments_q0, + l1_adjustments_we0, + l1_adjustments_address1, + l1_adjustments_ce1, + l1_adjustments_d1, + l1_adjustments_q1, + l1_adjustments_we1, + l2_filter_data_address0, + l2_filter_data_ce0, + l2_filter_data_d0, + l2_filter_data_q0, + l2_filter_data_we0, + l2_filter_data_address1, + l2_filter_data_ce1, + l2_filter_data_d1, + l2_filter_data_q1, + l2_filter_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_d0, + l2_adjustments_q0, + l2_adjustments_we0, + l2_adjustments_address1, + l2_adjustments_ce1, + l2_adjustments_d1, + l2_adjustments_q1, + l2_adjustments_we1, + ap_start, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +input ap_clk; +input ap_rst; +output [12:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [12:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [16:0] l1_filter_data_address0; +output l1_filter_data_ce0; +output [15:0] l1_filter_data_d0; +input [15:0] l1_filter_data_q0; +output l1_filter_data_we0; +output [16:0] l1_filter_data_address1; +output l1_filter_data_ce1; +output [15:0] l1_filter_data_d1; +input [15:0] l1_filter_data_q1; +output l1_filter_data_we1; +output [7:0] l1_adjustments_address0; +output l1_adjustments_ce0; +output [47:0] l1_adjustments_d0; +input [47:0] l1_adjustments_q0; +output l1_adjustments_we0; +output [7:0] l1_adjustments_address1; +output l1_adjustments_ce1; +output [47:0] l1_adjustments_d1; +input [47:0] l1_adjustments_q1; +output l1_adjustments_we1; +output [12:0] l2_filter_data_address0; +output l2_filter_data_ce0; +output [15:0] l2_filter_data_d0; +input [15:0] l2_filter_data_q0; +output l2_filter_data_we0; +output [12:0] l2_filter_data_address1; +output l2_filter_data_ce1; +output [15:0] l2_filter_data_d1; +input [15:0] l2_filter_data_q1; +output l2_filter_data_we1; +output [12:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [12:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [4:0] l2_adjustments_address0; +output l2_adjustments_ce0; +output [47:0] l2_adjustments_d0; +input [47:0] l2_adjustments_q0; +output l2_adjustments_we0; +output [4:0] l2_adjustments_address1; +output l2_adjustments_ce1; +output [47:0] l2_adjustments_d1; +input [47:0] l2_adjustments_q1; +output l2_adjustments_we1; +input ap_start; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +wire [15:0] ifmap_vec_i_q0; +wire [15:0] ifmap_vec_t_q0; +wire [15:0] weight_vecs_0_i_q0; +wire [15:0] weight_vecs_0_t_q0; +wire [15:0] products_0_i_q0; +wire [15:0] products_0_i_q1; +wire [15:0] products_0_t_q0; +wire [15:0] products_0_t_q1; +wire [15:0] accum1_out_0_i_q0; +wire [15:0] accum1_out_0_t_q0; +wire [15:0] l2_products_i_q0; +wire [15:0] l2_products_t_q0; +wire tdf7_get_next_ijk_U0_ap_start; +wire tdf7_get_next_ijk_U0_ap_done; +wire tdf7_get_next_ijk_U0_ap_continue; +wire tdf7_get_next_ijk_U0_ap_idle; +wire tdf7_get_next_ijk_U0_ap_ready; +wire tdf7_get_next_ijk_U0_start_out; +wire tdf7_get_next_ijk_U0_start_write; +wire [15:0] tdf7_get_next_ijk_U0_indices_0_din; +wire tdf7_get_next_ijk_U0_indices_0_write; +wire [15:0] tdf7_get_next_ijk_U0_indices_1_din; +wire tdf7_get_next_ijk_U0_indices_1_write; +wire [7:0] tdf7_get_next_ijk_U0_indices_2_out_din; +wire tdf7_get_next_ijk_U0_indices_2_out_write; +wire [12:0] tdf7_get_next_ijk_U0_indices_2_out1_din; +wire tdf7_get_next_ijk_U0_indices_2_out1_write; +wire tdf7_get_next_ijk_U0_write_r_din; +wire tdf7_get_next_ijk_U0_write_r_write; +wire tdf7_readInputs53_U0_ap_start; +wire tdf7_readInputs53_U0_ap_done; +wire tdf7_readInputs53_U0_ap_continue; +wire tdf7_readInputs53_U0_ap_idle; +wire tdf7_readInputs53_U0_ap_ready; +wire [12:0] tdf7_readInputs53_U0_in_data_address0; +wire tdf7_readInputs53_U0_in_data_ce0; +wire tdf7_readInputs53_U0_indices_01_read; +wire tdf7_readInputs53_U0_indices_12_read; +wire [8:0] tdf7_readInputs53_U0_ifmap_vec_address0; +wire tdf7_readInputs53_U0_ifmap_vec_ce0; +wire tdf7_readInputs53_U0_ifmap_vec_we0; +wire [15:0] tdf7_readInputs53_U0_ifmap_vec_d0; +wire [8:0] tdf7_readInputs53_U0_ifmap_vec_address1; +wire tdf7_readInputs53_U0_ifmap_vec_ce1; +wire tdf7_readInputs53_U0_ifmap_vec_we1; +wire [15:0] tdf7_readInputs53_U0_ifmap_vec_d1; +wire [4:0] tdf7_readInputs53_U0_indices_01_out_din; +wire tdf7_readInputs53_U0_indices_01_out_write; +wire [9:0] tdf7_readInputs53_U0_indices_12_out_din; +wire tdf7_readInputs53_U0_indices_12_out_write; +wire tdf7_readInputs53_U0_in_data_full_n; +wire tdf7_readInputs53_U0_in_data_write; +wire ap_channel_done_ifmap_vec; +wire tdf7_readInputs53_U0_ifmap_vec_full_n; +wire tdf7_readFilters52_U0_ap_start; +wire tdf7_readFilters52_U0_ap_done; +wire tdf7_readFilters52_U0_ap_continue; +wire tdf7_readFilters52_U0_ap_idle; +wire tdf7_readFilters52_U0_ap_ready; +wire [16:0] tdf7_readFilters52_U0_filter_data_address0; +wire tdf7_readFilters52_U0_filter_data_ce0; +wire tdf7_readFilters52_U0_indices_23_read; +wire [8:0] tdf7_readFilters52_U0_weight_vecs_0_address0; +wire tdf7_readFilters52_U0_weight_vecs_0_ce0; +wire tdf7_readFilters52_U0_weight_vecs_0_we0; +wire [15:0] tdf7_readFilters52_U0_weight_vecs_0_d0; +wire ap_channel_done_weight_vecs_0; +wire tdf7_readFilters52_U0_weight_vecs_0_full_n; +wire tdf7_dot_product_U0_ap_start; +wire tdf7_dot_product_U0_ap_done; +wire tdf7_dot_product_U0_ap_continue; +wire tdf7_dot_product_U0_ap_idle; +wire tdf7_dot_product_U0_ap_ready; +wire [8:0] tdf7_dot_product_U0_ifmap_vec_address0; +wire tdf7_dot_product_U0_ifmap_vec_ce0; +wire [8:0] tdf7_dot_product_U0_weight_vecs_0_address0; +wire tdf7_dot_product_U0_weight_vecs_0_ce0; +wire [8:0] tdf7_dot_product_U0_products_0_address0; +wire tdf7_dot_product_U0_products_0_ce0; +wire tdf7_dot_product_U0_products_0_we0; +wire [15:0] tdf7_dot_product_U0_products_0_d0; +wire ap_channel_done_products_0; +wire tdf7_dot_product_U0_products_0_full_n; +wire tdf7_accum_1_U0_ap_start; +wire tdf7_accum_1_U0_ap_done; +wire tdf7_accum_1_U0_ap_continue; +wire tdf7_accum_1_U0_ap_idle; +wire tdf7_accum_1_U0_ap_ready; +wire [8:0] tdf7_accum_1_U0_accum_in_0_address0; +wire tdf7_accum_1_U0_accum_in_0_ce0; +wire [8:0] tdf7_accum_1_U0_accum_in_0_address1; +wire tdf7_accum_1_U0_accum_in_0_ce1; +wire [2:0] tdf7_accum_1_U0_accum_out_address0; +wire tdf7_accum_1_U0_accum_out_ce0; +wire tdf7_accum_1_U0_accum_out_we0; +wire [15:0] tdf7_accum_1_U0_accum_out_d0; +wire [2:0] tdf7_accum_1_U0_accum_out_address1; +wire tdf7_accum_1_U0_accum_out_ce1; +wire tdf7_accum_1_U0_accum_out_we1; +wire [15:0] tdf7_accum_1_U0_accum_out_d1; +wire ap_channel_done_accum1_out_0; +wire tdf7_accum_1_U0_accum_out_full_n; +wire tdf7_accum_2_U0_ap_start; +wire tdf7_accum_2_U0_ap_done; +wire tdf7_accum_2_U0_ap_continue; +wire tdf7_accum_2_U0_ap_idle; +wire tdf7_accum_2_U0_ap_ready; +wire [15:0] tdf7_accum_2_U0_accum_in_6; +wire tdf7_accum_2_U0_accum_in_6_ap_vld; +wire [2:0] tdf7_accum_2_U0_accum_in_address0; +wire tdf7_accum_2_U0_accum_in_ce0; +wire ap_channel_done_tmp_channel; +wire tmp_channel_full_n; +wire Block_entry_proc_proc419_U0_ap_start; +wire Block_entry_proc_proc419_U0_ap_done; +wire Block_entry_proc_proc419_U0_ap_continue; +wire Block_entry_proc_proc419_U0_ap_idle; +wire Block_entry_proc_proc419_U0_ap_ready; +wire [15:0] Block_entry_proc_proc419_U0_ap_return; +wire ap_channel_done_sums_0; +wire sums_0_full_n; +wire tdf7_adjust_U0_ap_start; +wire tdf7_adjust_U0_ap_done; +wire tdf7_adjust_U0_ap_continue; +wire tdf7_adjust_U0_ap_idle; +wire tdf7_adjust_U0_ap_ready; +wire [7:0] tdf7_adjust_U0_adjustments_address0; +wire tdf7_adjust_U0_adjustments_ce0; +wire tdf7_adjust_U0_indices_23_read; +wire [12:0] tdf7_adjust_U0_indices_23_out_din; +wire tdf7_adjust_U0_indices_23_out_write; +wire [15:0] tdf7_adjust_U0_ap_return; +wire ap_channel_done_intermediate_fmaps_0; +wire intermediate_fmaps_0_full_n; +wire tdf7_l2_multiply50_U0_ap_start; +wire tdf7_l2_multiply50_U0_ap_done; +wire tdf7_l2_multiply50_U0_ap_continue; +wire tdf7_l2_multiply50_U0_ap_idle; +wire tdf7_l2_multiply50_U0_ap_ready; +wire [12:0] tdf7_l2_multiply50_U0_l2_filter_data_address0; +wire tdf7_l2_multiply50_U0_l2_filter_data_ce0; +wire [4:0] tdf7_l2_multiply50_U0_l2_products_address0; +wire tdf7_l2_multiply50_U0_l2_products_ce0; +wire tdf7_l2_multiply50_U0_l2_products_we0; +wire [15:0] tdf7_l2_multiply50_U0_l2_products_d0; +wire tdf7_l2_multiply50_U0_indices_23_read; +wire ap_channel_done_l2_products; +wire tdf7_l2_multiply50_U0_l2_products_full_n; +wire tdf7_l2_writeOutputs_149_U0_ap_start; +wire tdf7_l2_writeOutputs_149_U0_ap_done; +wire tdf7_l2_writeOutputs_149_U0_ap_continue; +wire tdf7_l2_writeOutputs_149_U0_ap_idle; +wire tdf7_l2_writeOutputs_149_U0_ap_ready; +wire tdf7_l2_writeOutputs_149_U0_indices_01_read; +wire tdf7_l2_writeOutputs_149_U0_indices_12_read; +wire tdf7_l2_writeOutputs_149_U0_write4_read; +wire [4:0] tdf7_l2_writeOutputs_149_U0_l2_partial_sums_address0; +wire tdf7_l2_writeOutputs_149_U0_l2_partial_sums_ce0; +wire [12:0] tdf7_l2_writeOutputs_149_U0_out_data_address1; +wire tdf7_l2_writeOutputs_149_U0_out_data_ce1; +wire tdf7_l2_writeOutputs_149_U0_out_data_we1; +wire [63:0] tdf7_l2_writeOutputs_149_U0_out_data_d1; +wire [4:0] tdf7_l2_writeOutputs_149_U0_l2_adjustments_address0; +wire tdf7_l2_writeOutputs_149_U0_l2_adjustments_ce0; +wire tdf7_l2_writeOutputs_149_U0_out_data_full_n; +wire tdf7_l2_writeOutputs_149_U0_out_data_write; +wire ap_sync_continue; +wire ifmap_vec_i_full_n; +wire ifmap_vec_t_empty_n; +wire weight_vecs_0_i_full_n; +wire weight_vecs_0_t_empty_n; +wire products_0_i_full_n; +wire products_0_t_empty_n; +wire [15:0] products_0_t_d1; +wire products_0_t_we1; +wire accum1_out_0_i_full_n; +wire accum1_out_0_t_empty_n; +wire l2_products_i_full_n; +wire l2_products_t_empty_n; +wire indices_01_c_full_n; +wire [15:0] indices_01_c_dout; +wire indices_01_c_empty_n; +wire indices_12_c_full_n; +wire [15:0] indices_12_c_dout; +wire indices_12_c_empty_n; +wire indices_23_c_full_n; +wire [7:0] indices_23_c_dout; +wire indices_23_c_empty_n; +wire indices_23_c1_full_n; +wire [12:0] indices_23_c1_dout; +wire indices_23_c1_empty_n; +wire [0:0] write4_c_din; +wire write4_c_full_n; +wire [0:0] write4_c_dout; +wire write4_c_empty_n; +wire indices_01_c2_full_n; +wire [4:0] indices_01_c2_dout; +wire indices_01_c2_empty_n; +wire indices_12_c3_full_n; +wire [9:0] indices_12_c3_dout; +wire indices_12_c3_empty_n; +wire [15:0] tmp_channel_dout; +wire tmp_channel_empty_n; +wire [15:0] sums_0_dout; +wire sums_0_empty_n; +wire indices_23_c4_full_n; +wire [12:0] indices_23_c4_dout; +wire indices_23_c4_empty_n; +wire [15:0] intermediate_fmaps_0_dout; +wire intermediate_fmaps_0_empty_n; +wire ap_sync_done; +wire ap_sync_ready; +reg ap_sync_reg_tdf7_get_next_ijk_U0_ap_ready; +wire ap_sync_tdf7_get_next_ijk_U0_ap_ready; +reg ap_sync_reg_tdf7_readInputs53_U0_ap_ready; +wire ap_sync_tdf7_readInputs53_U0_ap_ready; +wire [0:0] start_for_tdf7_readFilters52_U0_din; +wire start_for_tdf7_readFilters52_U0_full_n; +wire [0:0] start_for_tdf7_readFilters52_U0_dout; +wire start_for_tdf7_readFilters52_U0_empty_n; +wire tdf7_readInputs53_U0_start_full_n; +wire tdf7_readInputs53_U0_start_write; +wire tdf7_readFilters52_U0_start_full_n; +wire tdf7_readFilters52_U0_start_write; +wire tdf7_dot_product_U0_start_full_n; +wire tdf7_dot_product_U0_start_write; +wire tdf7_accum_1_U0_start_full_n; +wire tdf7_accum_1_U0_start_write; +wire tdf7_accum_2_U0_start_full_n; +wire tdf7_accum_2_U0_start_write; +wire Block_entry_proc_proc419_U0_start_full_n; +wire Block_entry_proc_proc419_U0_start_write; +wire tdf7_adjust_U0_start_full_n; +wire tdf7_adjust_U0_start_write; +wire tdf7_l2_multiply50_U0_start_full_n; +wire tdf7_l2_multiply50_U0_start_write; +wire tdf7_l2_writeOutputs_149_U0_start_full_n; +wire tdf7_l2_writeOutputs_149_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_sync_reg_tdf7_get_next_ijk_U0_ap_ready = 1'b0; +#0 ap_sync_reg_tdf7_readInputs53_U0_ap_ready = 1'b0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP37548_ifmap_vec #( + .DataWidth( 16 ), + .AddressRange( 288 ), + .AddressWidth( 9 )) +ifmap_vec_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf7_readInputs53_U0_ap_done), + .i_full_n(ifmap_vec_i_full_n), + .i_ce0(tdf7_readInputs53_U0_ifmap_vec_ce0), + .i_we0(tdf7_readInputs53_U0_ifmap_vec_we0), + .i_address0(tdf7_readInputs53_U0_ifmap_vec_address0), + .i_d0(tdf7_readInputs53_U0_ifmap_vec_d0), + .i_q0(ifmap_vec_i_q0), + .i_ce1(tdf7_readInputs53_U0_ifmap_vec_ce1), + .i_we1(tdf7_readInputs53_U0_ifmap_vec_we1), + .i_address1(tdf7_readInputs53_U0_ifmap_vec_address1), + .i_d1(tdf7_readInputs53_U0_ifmap_vec_d1), + .t_ce(1'b1), + .t_read(tdf7_dot_product_U0_ap_ready), + .t_empty_n(ifmap_vec_t_empty_n), + .t_ce0(tdf7_dot_product_U0_ifmap_vec_ce0), + .t_we0(1'b0), + .t_address0(tdf7_dot_product_U0_ifmap_vec_address0), + .t_d0(16'd0), + .t_q0(ifmap_vec_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(9'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37548_weight_vecs_0 #( + .DataWidth( 16 ), + .AddressRange( 288 ), + .AddressWidth( 9 )) +weight_vecs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf7_readFilters52_U0_ap_done), + .i_full_n(weight_vecs_0_i_full_n), + .i_ce0(tdf7_readFilters52_U0_weight_vecs_0_ce0), + .i_we0(tdf7_readFilters52_U0_weight_vecs_0_we0), + .i_address0(tdf7_readFilters52_U0_weight_vecs_0_address0), + .i_d0(tdf7_readFilters52_U0_weight_vecs_0_d0), + .i_q0(weight_vecs_0_i_q0), + .t_ce(1'b1), + .t_read(tdf7_dot_product_U0_ap_ready), + .t_empty_n(weight_vecs_0_t_empty_n), + .t_ce0(tdf7_dot_product_U0_weight_vecs_0_ce0), + .t_we0(1'b0), + .t_address0(tdf7_dot_product_U0_weight_vecs_0_address0), + .t_d0(16'd0), + .t_q0(weight_vecs_0_t_q0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37548_products_0 #( + .DataWidth( 16 ), + .AddressRange( 288 ), + .AddressWidth( 9 )) +products_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf7_dot_product_U0_ap_done), + .i_full_n(products_0_i_full_n), + .i_ce0(tdf7_dot_product_U0_products_0_ce0), + .i_we0(tdf7_dot_product_U0_products_0_we0), + .i_address0(tdf7_dot_product_U0_products_0_address0), + .i_d0(tdf7_dot_product_U0_products_0_d0), + .i_q0(products_0_i_q0), + .i_ce1(1'b0), + .i_address1(9'd0), + .i_q1(products_0_i_q1), + .t_ce(1'b1), + .t_read(tdf7_accum_1_U0_ap_ready), + .t_empty_n(products_0_t_empty_n), + .t_ce0(tdf7_accum_1_U0_accum_in_0_ce0), + .t_we0(1'b0), + .t_address0(tdf7_accum_1_U0_accum_in_0_address0), + .t_d0(16'd0), + .t_q0(products_0_t_q0), + .t_ce1(tdf7_accum_1_U0_accum_in_0_ce1), + .t_address1(tdf7_accum_1_U0_accum_in_0_address1), + .t_q1(products_0_t_q1) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37548_accum1_out_0 #( + .DataWidth( 16 ), + .AddressRange( 8 ), + .AddressWidth( 3 )) +accum1_out_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf7_accum_1_U0_ap_done), + .i_full_n(accum1_out_0_i_full_n), + .i_ce0(tdf7_accum_1_U0_accum_out_ce0), + .i_we0(tdf7_accum_1_U0_accum_out_we0), + .i_address0(tdf7_accum_1_U0_accum_out_address0), + .i_d0(tdf7_accum_1_U0_accum_out_d0), + .i_q0(accum1_out_0_i_q0), + .i_ce1(tdf7_accum_1_U0_accum_out_ce1), + .i_we1(tdf7_accum_1_U0_accum_out_we1), + .i_address1(tdf7_accum_1_U0_accum_out_address1), + .i_d1(tdf7_accum_1_U0_accum_out_d1), + .t_ce(1'b1), + .t_read(tdf7_accum_2_U0_ap_ready), + .t_empty_n(accum1_out_0_t_empty_n), + .t_ce0(tdf7_accum_2_U0_accum_in_ce0), + .t_we0(1'b0), + .t_address0(tdf7_accum_2_U0_accum_in_address0), + .t_d0(16'd0), + .t_q0(accum1_out_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(3'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37548_l2_products #( + .DataWidth( 16 ), + .AddressRange( 32 ), + .AddressWidth( 5 )) +l2_products_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf7_l2_multiply50_U0_ap_done), + .i_full_n(l2_products_i_full_n), + .i_ce0(tdf7_l2_multiply50_U0_l2_products_ce0), + .i_we0(tdf7_l2_multiply50_U0_l2_products_we0), + .i_address0(tdf7_l2_multiply50_U0_l2_products_address0), + .i_d0(tdf7_l2_multiply50_U0_l2_products_d0), + .i_q0(l2_products_i_q0), + .t_ce(1'b1), + .t_read(tdf7_l2_writeOutputs_149_U0_ap_ready), + .t_empty_n(l2_products_t_empty_n), + .t_ce0(tdf7_l2_writeOutputs_149_U0_l2_partial_sums_ce0), + .t_we0(1'b0), + .t_address0(tdf7_l2_writeOutputs_149_U0_l2_partial_sums_address0), + .t_d0(16'd0), + .t_q0(l2_products_t_q0) +); + +td_fused_top_tdf7_get_next_ijk tdf7_get_next_ijk_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf7_get_next_ijk_U0_ap_start), + .start_full_n(start_for_tdf7_readFilters52_U0_full_n), + .ap_done(tdf7_get_next_ijk_U0_ap_done), + .ap_continue(tdf7_get_next_ijk_U0_ap_continue), + .ap_idle(tdf7_get_next_ijk_U0_ap_idle), + .ap_ready(tdf7_get_next_ijk_U0_ap_ready), + .start_out(tdf7_get_next_ijk_U0_start_out), + .start_write(tdf7_get_next_ijk_U0_start_write), + .indices_0_din(tdf7_get_next_ijk_U0_indices_0_din), + .indices_0_full_n(indices_01_c_full_n), + .indices_0_write(tdf7_get_next_ijk_U0_indices_0_write), + .indices_1_din(tdf7_get_next_ijk_U0_indices_1_din), + .indices_1_full_n(indices_12_c_full_n), + .indices_1_write(tdf7_get_next_ijk_U0_indices_1_write), + .indices_2_out_din(tdf7_get_next_ijk_U0_indices_2_out_din), + .indices_2_out_full_n(indices_23_c_full_n), + .indices_2_out_write(tdf7_get_next_ijk_U0_indices_2_out_write), + .indices_2_out1_din(tdf7_get_next_ijk_U0_indices_2_out1_din), + .indices_2_out1_full_n(indices_23_c1_full_n), + .indices_2_out1_write(tdf7_get_next_ijk_U0_indices_2_out1_write), + .write_r_din(tdf7_get_next_ijk_U0_write_r_din), + .write_r_full_n(write4_c_full_n), + .write_r_write(tdf7_get_next_ijk_U0_write_r_write) +); + +td_fused_top_tdf7_readInputs53 tdf7_readInputs53_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf7_readInputs53_U0_ap_start), + .ap_done(tdf7_readInputs53_U0_ap_done), + .ap_continue(tdf7_readInputs53_U0_ap_continue), + .ap_idle(tdf7_readInputs53_U0_ap_idle), + .ap_ready(tdf7_readInputs53_U0_ap_ready), + .in_data_address0(tdf7_readInputs53_U0_in_data_address0), + .in_data_ce0(tdf7_readInputs53_U0_in_data_ce0), + .in_data_q0(in_data_q0), + .indices_01_dout(indices_01_c_dout), + .indices_01_empty_n(indices_01_c_empty_n), + .indices_01_read(tdf7_readInputs53_U0_indices_01_read), + .indices_12_dout(indices_12_c_dout), + .indices_12_empty_n(indices_12_c_empty_n), + .indices_12_read(tdf7_readInputs53_U0_indices_12_read), + .ifmap_vec_address0(tdf7_readInputs53_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf7_readInputs53_U0_ifmap_vec_ce0), + .ifmap_vec_we0(tdf7_readInputs53_U0_ifmap_vec_we0), + .ifmap_vec_d0(tdf7_readInputs53_U0_ifmap_vec_d0), + .ifmap_vec_address1(tdf7_readInputs53_U0_ifmap_vec_address1), + .ifmap_vec_ce1(tdf7_readInputs53_U0_ifmap_vec_ce1), + .ifmap_vec_we1(tdf7_readInputs53_U0_ifmap_vec_we1), + .ifmap_vec_d1(tdf7_readInputs53_U0_ifmap_vec_d1), + .indices_01_out_din(tdf7_readInputs53_U0_indices_01_out_din), + .indices_01_out_full_n(indices_01_c2_full_n), + .indices_01_out_write(tdf7_readInputs53_U0_indices_01_out_write), + .indices_12_out_din(tdf7_readInputs53_U0_indices_12_out_din), + .indices_12_out_full_n(indices_12_c3_full_n), + .indices_12_out_write(tdf7_readInputs53_U0_indices_12_out_write) +); + +td_fused_top_tdf7_readFilters52 tdf7_readFilters52_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf7_readFilters52_U0_ap_start), + .ap_done(tdf7_readFilters52_U0_ap_done), + .ap_continue(tdf7_readFilters52_U0_ap_continue), + .ap_idle(tdf7_readFilters52_U0_ap_idle), + .ap_ready(tdf7_readFilters52_U0_ap_ready), + .filter_data_address0(tdf7_readFilters52_U0_filter_data_address0), + .filter_data_ce0(tdf7_readFilters52_U0_filter_data_ce0), + .filter_data_q0(l1_filter_data_q0), + .indices_23_dout(indices_23_c_dout), + .indices_23_empty_n(indices_23_c_empty_n), + .indices_23_read(tdf7_readFilters52_U0_indices_23_read), + .weight_vecs_0_address0(tdf7_readFilters52_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf7_readFilters52_U0_weight_vecs_0_ce0), + .weight_vecs_0_we0(tdf7_readFilters52_U0_weight_vecs_0_we0), + .weight_vecs_0_d0(tdf7_readFilters52_U0_weight_vecs_0_d0) +); + +td_fused_top_tdf7_dot_product tdf7_dot_product_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf7_dot_product_U0_ap_start), + .ap_done(tdf7_dot_product_U0_ap_done), + .ap_continue(tdf7_dot_product_U0_ap_continue), + .ap_idle(tdf7_dot_product_U0_ap_idle), + .ap_ready(tdf7_dot_product_U0_ap_ready), + .ifmap_vec_address0(tdf7_dot_product_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf7_dot_product_U0_ifmap_vec_ce0), + .ifmap_vec_q0(ifmap_vec_t_q0), + .weight_vecs_0_address0(tdf7_dot_product_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf7_dot_product_U0_weight_vecs_0_ce0), + .weight_vecs_0_q0(weight_vecs_0_t_q0), + .products_0_address0(tdf7_dot_product_U0_products_0_address0), + .products_0_ce0(tdf7_dot_product_U0_products_0_ce0), + .products_0_we0(tdf7_dot_product_U0_products_0_we0), + .products_0_d0(tdf7_dot_product_U0_products_0_d0) +); + +td_fused_top_tdf7_accum_1 tdf7_accum_1_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf7_accum_1_U0_ap_start), + .ap_done(tdf7_accum_1_U0_ap_done), + .ap_continue(tdf7_accum_1_U0_ap_continue), + .ap_idle(tdf7_accum_1_U0_ap_idle), + .ap_ready(tdf7_accum_1_U0_ap_ready), + .accum_in_0_address0(tdf7_accum_1_U0_accum_in_0_address0), + .accum_in_0_ce0(tdf7_accum_1_U0_accum_in_0_ce0), + .accum_in_0_q0(products_0_t_q0), + .accum_in_0_address1(tdf7_accum_1_U0_accum_in_0_address1), + .accum_in_0_ce1(tdf7_accum_1_U0_accum_in_0_ce1), + .accum_in_0_q1(products_0_t_q1), + .accum_out_address0(tdf7_accum_1_U0_accum_out_address0), + .accum_out_ce0(tdf7_accum_1_U0_accum_out_ce0), + .accum_out_we0(tdf7_accum_1_U0_accum_out_we0), + .accum_out_d0(tdf7_accum_1_U0_accum_out_d0), + .accum_out_address1(tdf7_accum_1_U0_accum_out_address1), + .accum_out_ce1(tdf7_accum_1_U0_accum_out_ce1), + .accum_out_we1(tdf7_accum_1_U0_accum_out_we1), + .accum_out_d1(tdf7_accum_1_U0_accum_out_d1) +); + +td_fused_top_tdf7_accum_2 tdf7_accum_2_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf7_accum_2_U0_ap_start), + .ap_done(tdf7_accum_2_U0_ap_done), + .ap_continue(tdf7_accum_2_U0_ap_continue), + .ap_idle(tdf7_accum_2_U0_ap_idle), + .ap_ready(tdf7_accum_2_U0_ap_ready), + .accum_in_6(tdf7_accum_2_U0_accum_in_6), + .accum_in_6_ap_vld(tdf7_accum_2_U0_accum_in_6_ap_vld), + .accum_in_address0(tdf7_accum_2_U0_accum_in_address0), + .accum_in_ce0(tdf7_accum_2_U0_accum_in_ce0), + .accum_in_q0(accum1_out_0_t_q0) +); + +td_fused_top_Block_entry_proc_proc419 Block_entry_proc_proc419_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(Block_entry_proc_proc419_U0_ap_start), + .ap_done(Block_entry_proc_proc419_U0_ap_done), + .ap_continue(Block_entry_proc_proc419_U0_ap_continue), + .ap_idle(Block_entry_proc_proc419_U0_ap_idle), + .ap_ready(Block_entry_proc_proc419_U0_ap_ready), + .tmp(tmp_channel_dout), + .ap_return(Block_entry_proc_proc419_U0_ap_return) +); + +td_fused_top_tdf7_adjust tdf7_adjust_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf7_adjust_U0_ap_start), + .ap_done(tdf7_adjust_U0_ap_done), + .ap_continue(tdf7_adjust_U0_ap_continue), + .ap_idle(tdf7_adjust_U0_ap_idle), + .ap_ready(tdf7_adjust_U0_ap_ready), + .sums_read(sums_0_dout), + .adjustments_address0(tdf7_adjust_U0_adjustments_address0), + .adjustments_ce0(tdf7_adjust_U0_adjustments_ce0), + .adjustments_q0(l1_adjustments_q0), + .indices_23_dout(indices_23_c1_dout), + .indices_23_empty_n(indices_23_c1_empty_n), + .indices_23_read(tdf7_adjust_U0_indices_23_read), + .indices_23_out_din(tdf7_adjust_U0_indices_23_out_din), + .indices_23_out_full_n(indices_23_c4_full_n), + .indices_23_out_write(tdf7_adjust_U0_indices_23_out_write), + .ap_return(tdf7_adjust_U0_ap_return) +); + +td_fused_top_tdf7_l2_multiply50 tdf7_l2_multiply50_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf7_l2_multiply50_U0_ap_start), + .ap_done(tdf7_l2_multiply50_U0_ap_done), + .ap_continue(tdf7_l2_multiply50_U0_ap_continue), + .ap_idle(tdf7_l2_multiply50_U0_ap_idle), + .ap_ready(tdf7_l2_multiply50_U0_ap_ready), + .intermediate_fmaps_read(intermediate_fmaps_0_dout), + .l2_filter_data_address0(tdf7_l2_multiply50_U0_l2_filter_data_address0), + .l2_filter_data_ce0(tdf7_l2_multiply50_U0_l2_filter_data_ce0), + .l2_filter_data_q0(l2_filter_data_q0), + .l2_products_address0(tdf7_l2_multiply50_U0_l2_products_address0), + .l2_products_ce0(tdf7_l2_multiply50_U0_l2_products_ce0), + .l2_products_we0(tdf7_l2_multiply50_U0_l2_products_we0), + .l2_products_d0(tdf7_l2_multiply50_U0_l2_products_d0), + .indices_23_dout(indices_23_c4_dout), + .indices_23_empty_n(indices_23_c4_empty_n), + .indices_23_read(tdf7_l2_multiply50_U0_indices_23_read) +); + +td_fused_top_tdf7_l2_writeOutputs_149 tdf7_l2_writeOutputs_149_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf7_l2_writeOutputs_149_U0_ap_start), + .ap_done(tdf7_l2_writeOutputs_149_U0_ap_done), + .ap_continue(tdf7_l2_writeOutputs_149_U0_ap_continue), + .ap_idle(tdf7_l2_writeOutputs_149_U0_ap_idle), + .ap_ready(tdf7_l2_writeOutputs_149_U0_ap_ready), + .indices_01_dout(indices_01_c2_dout), + .indices_01_empty_n(indices_01_c2_empty_n), + .indices_01_read(tdf7_l2_writeOutputs_149_U0_indices_01_read), + .indices_12_dout(indices_12_c3_dout), + .indices_12_empty_n(indices_12_c3_empty_n), + .indices_12_read(tdf7_l2_writeOutputs_149_U0_indices_12_read), + .write4_dout(write4_c_dout), + .write4_empty_n(write4_c_empty_n), + .write4_read(tdf7_l2_writeOutputs_149_U0_write4_read), + .l2_partial_sums_address0(tdf7_l2_writeOutputs_149_U0_l2_partial_sums_address0), + .l2_partial_sums_ce0(tdf7_l2_writeOutputs_149_U0_l2_partial_sums_ce0), + .l2_partial_sums_q0(l2_products_t_q0), + .out_data_address1(tdf7_l2_writeOutputs_149_U0_out_data_address1), + .out_data_ce1(tdf7_l2_writeOutputs_149_U0_out_data_ce1), + .out_data_we1(tdf7_l2_writeOutputs_149_U0_out_data_we1), + .out_data_d1(tdf7_l2_writeOutputs_149_U0_out_data_d1), + .l2_adjustments_address0(tdf7_l2_writeOutputs_149_U0_l2_adjustments_address0), + .l2_adjustments_ce0(tdf7_l2_writeOutputs_149_U0_l2_adjustments_ce0), + .l2_adjustments_q0(l2_adjustments_q0) +); + +td_fused_top_fifo_w16_d2_S_x4 indices_01_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf7_readInputs53_U0_indices_01_read), + .if_dout(indices_01_c_dout), + .if_full_n(indices_01_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf7_get_next_ijk_U0_indices_0_write), + .if_din(tdf7_get_next_ijk_U0_indices_0_din) +); + +td_fused_top_fifo_w16_d2_S_x4 indices_12_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf7_readInputs53_U0_indices_12_read), + .if_dout(indices_12_c_dout), + .if_full_n(indices_12_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf7_get_next_ijk_U0_indices_1_write), + .if_din(tdf7_get_next_ijk_U0_indices_1_din) +); + +td_fused_top_fifo_w8_d2_S indices_23_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf7_readFilters52_U0_indices_23_read), + .if_dout(indices_23_c_dout), + .if_full_n(indices_23_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf7_get_next_ijk_U0_indices_2_out_write), + .if_din(tdf7_get_next_ijk_U0_indices_2_out_din) +); + +td_fused_top_fifo_w13_d7_S indices_23_c1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf7_adjust_U0_indices_23_read), + .if_dout(indices_23_c1_dout), + .if_full_n(indices_23_c1_full_n), + .if_write_ce(1'b1), + .if_write(tdf7_get_next_ijk_U0_indices_2_out1_write), + .if_din(tdf7_get_next_ijk_U0_indices_2_out1_din) +); + +td_fused_top_fifo_w1_d9_S_x0 write4_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(write4_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf7_l2_writeOutputs_149_U0_write4_read), + .if_dout(write4_c_dout), + .if_full_n(write4_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf7_get_next_ijk_U0_write_r_write), + .if_din(write4_c_din) +); + +td_fused_top_fifo_w5_d8_S_x indices_01_c2_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c2_empty_n), + .if_read_ce(1'b1), + .if_read(tdf7_l2_writeOutputs_149_U0_indices_01_read), + .if_dout(indices_01_c2_dout), + .if_full_n(indices_01_c2_full_n), + .if_write_ce(1'b1), + .if_write(tdf7_readInputs53_U0_indices_01_out_write), + .if_din(tdf7_readInputs53_U0_indices_01_out_din) +); + +td_fused_top_fifo_w10_d8_S_x indices_12_c3_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c3_empty_n), + .if_read_ce(1'b1), + .if_read(tdf7_l2_writeOutputs_149_U0_indices_12_read), + .if_dout(indices_12_c3_dout), + .if_full_n(indices_12_c3_full_n), + .if_write_ce(1'b1), + .if_write(tdf7_readInputs53_U0_indices_12_out_write), + .if_din(tdf7_readInputs53_U0_indices_12_out_din) +); + +td_fused_top_fifo_w16_d2_S_x4 tmp_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(tmp_channel_empty_n), + .if_read_ce(1'b1), + .if_read(Block_entry_proc_proc419_U0_ap_ready), + .if_dout(tmp_channel_dout), + .if_full_n(tmp_channel_full_n), + .if_write_ce(1'b1), + .if_write(tdf7_accum_2_U0_ap_done), + .if_din(tdf7_accum_2_U0_accum_in_6) +); + +td_fused_top_fifo_w16_d2_S_x4 sums_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(sums_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf7_adjust_U0_ap_ready), + .if_dout(sums_0_dout), + .if_full_n(sums_0_full_n), + .if_write_ce(1'b1), + .if_write(Block_entry_proc_proc419_U0_ap_done), + .if_din(Block_entry_proc_proc419_U0_ap_return) +); + +td_fused_top_fifo_w13_d2_S indices_23_c4_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c4_empty_n), + .if_read_ce(1'b1), + .if_read(tdf7_l2_multiply50_U0_indices_23_read), + .if_dout(indices_23_c4_dout), + .if_full_n(indices_23_c4_full_n), + .if_write_ce(1'b1), + .if_write(tdf7_adjust_U0_indices_23_out_write), + .if_din(tdf7_adjust_U0_indices_23_out_din) +); + +td_fused_top_fifo_w16_d2_S_x4 intermediate_fmaps_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(intermediate_fmaps_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf7_l2_multiply50_U0_ap_ready), + .if_dout(intermediate_fmaps_0_dout), + .if_full_n(intermediate_fmaps_0_full_n), + .if_write_ce(1'b1), + .if_write(tdf7_adjust_U0_ap_done), + .if_din(tdf7_adjust_U0_ap_return) +); + +td_fused_top_start_for_tdf7_readFilters52_U0 start_for_tdf7_readFilters52_U0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(start_for_tdf7_readFilters52_U0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf7_readFilters52_U0_ap_ready), + .if_dout(start_for_tdf7_readFilters52_U0_dout), + .if_full_n(start_for_tdf7_readFilters52_U0_full_n), + .if_write_ce(1'b1), + .if_write(tdf7_get_next_ijk_U0_start_write), + .if_din(start_for_tdf7_readFilters52_U0_din) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf7_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf7_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf7_get_next_ijk_U0_ap_ready <= ap_sync_tdf7_get_next_ijk_U0_ap_ready; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf7_readInputs53_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf7_readInputs53_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf7_readInputs53_U0_ap_ready <= ap_sync_tdf7_readInputs53_U0_ap_ready; + end + end +end + +assign Block_entry_proc_proc419_U0_ap_continue = sums_0_full_n; + +assign Block_entry_proc_proc419_U0_ap_start = tmp_channel_empty_n; + +assign Block_entry_proc_proc419_U0_start_full_n = 1'b1; + +assign Block_entry_proc_proc419_U0_start_write = 1'b0; + +assign ap_channel_done_accum1_out_0 = tdf7_accum_1_U0_ap_done; + +assign ap_channel_done_ifmap_vec = tdf7_readInputs53_U0_ap_done; + +assign ap_channel_done_intermediate_fmaps_0 = tdf7_adjust_U0_ap_done; + +assign ap_channel_done_l2_products = tdf7_l2_multiply50_U0_ap_done; + +assign ap_channel_done_products_0 = tdf7_dot_product_U0_ap_done; + +assign ap_channel_done_sums_0 = Block_entry_proc_proc419_U0_ap_done; + +assign ap_channel_done_tmp_channel = tdf7_accum_2_U0_ap_done; + +assign ap_channel_done_weight_vecs_0 = tdf7_readFilters52_U0_ap_done; + +assign ap_done = tdf7_l2_writeOutputs_149_U0_ap_done; + +assign ap_idle = (tdf7_readInputs53_U0_ap_idle & tdf7_readFilters52_U0_ap_idle & tdf7_l2_writeOutputs_149_U0_ap_idle & tdf7_l2_multiply50_U0_ap_idle & tdf7_get_next_ijk_U0_ap_idle & tdf7_dot_product_U0_ap_idle & tdf7_adjust_U0_ap_idle & tdf7_accum_2_U0_ap_idle & tdf7_accum_1_U0_ap_idle & (intermediate_fmaps_0_empty_n ^ 1'b1) & (sums_0_empty_n ^ 1'b1) & (tmp_channel_empty_n ^ 1'b1) & (l2_products_t_empty_n ^ 1'b1) & (products_0_t_empty_n ^ 1'b1) & (weight_vecs_0_t_empty_n ^ 1'b1) & (ifmap_vec_t_empty_n ^ 1'b1) & (1'b1 ^ accum1_out_0_t_empty_n) & Block_entry_proc_proc419_U0_ap_idle); + +assign ap_ready = ap_sync_ready; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = tdf7_l2_writeOutputs_149_U0_ap_done; + +assign ap_sync_ready = (ap_sync_tdf7_readInputs53_U0_ap_ready & ap_sync_tdf7_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf7_get_next_ijk_U0_ap_ready = (tdf7_get_next_ijk_U0_ap_ready | ap_sync_reg_tdf7_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf7_readInputs53_U0_ap_ready = (tdf7_readInputs53_U0_ap_ready | ap_sync_reg_tdf7_readInputs53_U0_ap_ready); + +assign in_data_address0 = tdf7_readInputs53_U0_in_data_address0; + +assign in_data_address1 = 13'd0; + +assign in_data_ce0 = tdf7_readInputs53_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = tdf7_readInputs53_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign l1_adjustments_address0 = tdf7_adjust_U0_adjustments_address0; + +assign l1_adjustments_address1 = 8'd0; + +assign l1_adjustments_ce0 = tdf7_adjust_U0_adjustments_ce0; + +assign l1_adjustments_ce1 = 1'b0; + +assign l1_adjustments_d0 = 48'd0; + +assign l1_adjustments_d1 = 48'd0; + +assign l1_adjustments_we0 = 1'b0; + +assign l1_adjustments_we1 = 1'b0; + +assign l1_filter_data_address0 = tdf7_readFilters52_U0_filter_data_address0; + +assign l1_filter_data_address1 = 17'd0; + +assign l1_filter_data_ce0 = tdf7_readFilters52_U0_filter_data_ce0; + +assign l1_filter_data_ce1 = 1'b0; + +assign l1_filter_data_d0 = 16'd0; + +assign l1_filter_data_d1 = 16'd0; + +assign l1_filter_data_we0 = 1'b0; + +assign l1_filter_data_we1 = 1'b0; + +assign l2_adjustments_address0 = tdf7_l2_writeOutputs_149_U0_l2_adjustments_address0; + +assign l2_adjustments_address1 = 5'd0; + +assign l2_adjustments_ce0 = tdf7_l2_writeOutputs_149_U0_l2_adjustments_ce0; + +assign l2_adjustments_ce1 = 1'b0; + +assign l2_adjustments_d0 = 48'd0; + +assign l2_adjustments_d1 = 48'd0; + +assign l2_adjustments_we0 = 1'b0; + +assign l2_adjustments_we1 = 1'b0; + +assign l2_filter_data_address0 = tdf7_l2_multiply50_U0_l2_filter_data_address0; + +assign l2_filter_data_address1 = 13'd0; + +assign l2_filter_data_ce0 = tdf7_l2_multiply50_U0_l2_filter_data_ce0; + +assign l2_filter_data_ce1 = 1'b0; + +assign l2_filter_data_d0 = 16'd0; + +assign l2_filter_data_d1 = 16'd0; + +assign l2_filter_data_we0 = 1'b0; + +assign l2_filter_data_we1 = 1'b0; + +assign out_data_address0 = 13'd0; + +assign out_data_address1 = tdf7_l2_writeOutputs_149_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = tdf7_l2_writeOutputs_149_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = tdf7_l2_writeOutputs_149_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = tdf7_l2_writeOutputs_149_U0_out_data_we1; + +assign out_data_write = tdf7_l2_writeOutputs_149_U0_out_data_write; + +assign products_0_t_d1 = 16'd0; + +assign products_0_t_we1 = 1'b0; + +assign start_for_tdf7_readFilters52_U0_din = 1'b1; + +assign tdf7_accum_1_U0_accum_out_full_n = accum1_out_0_i_full_n; + +assign tdf7_accum_1_U0_ap_continue = accum1_out_0_i_full_n; + +assign tdf7_accum_1_U0_ap_start = products_0_t_empty_n; + +assign tdf7_accum_1_U0_start_full_n = 1'b1; + +assign tdf7_accum_1_U0_start_write = 1'b0; + +assign tdf7_accum_2_U0_ap_continue = tmp_channel_full_n; + +assign tdf7_accum_2_U0_ap_start = accum1_out_0_t_empty_n; + +assign tdf7_accum_2_U0_start_full_n = 1'b1; + +assign tdf7_accum_2_U0_start_write = 1'b0; + +assign tdf7_adjust_U0_ap_continue = intermediate_fmaps_0_full_n; + +assign tdf7_adjust_U0_ap_start = sums_0_empty_n; + +assign tdf7_adjust_U0_start_full_n = 1'b1; + +assign tdf7_adjust_U0_start_write = 1'b0; + +assign tdf7_dot_product_U0_ap_continue = products_0_i_full_n; + +assign tdf7_dot_product_U0_ap_start = (weight_vecs_0_t_empty_n & ifmap_vec_t_empty_n); + +assign tdf7_dot_product_U0_products_0_full_n = products_0_i_full_n; + +assign tdf7_dot_product_U0_start_full_n = 1'b1; + +assign tdf7_dot_product_U0_start_write = 1'b0; + +assign tdf7_get_next_ijk_U0_ap_continue = 1'b1; + +assign tdf7_get_next_ijk_U0_ap_start = ((ap_sync_reg_tdf7_get_next_ijk_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf7_l2_multiply50_U0_ap_continue = l2_products_i_full_n; + +assign tdf7_l2_multiply50_U0_ap_start = intermediate_fmaps_0_empty_n; + +assign tdf7_l2_multiply50_U0_l2_products_full_n = l2_products_i_full_n; + +assign tdf7_l2_multiply50_U0_start_full_n = 1'b1; + +assign tdf7_l2_multiply50_U0_start_write = 1'b0; + +assign tdf7_l2_writeOutputs_149_U0_ap_continue = ap_continue; + +assign tdf7_l2_writeOutputs_149_U0_ap_start = l2_products_t_empty_n; + +assign tdf7_l2_writeOutputs_149_U0_out_data_full_n = out_data_full_n; + +assign tdf7_l2_writeOutputs_149_U0_out_data_write = 1'b0; + +assign tdf7_l2_writeOutputs_149_U0_start_full_n = 1'b1; + +assign tdf7_l2_writeOutputs_149_U0_start_write = 1'b0; + +assign tdf7_readFilters52_U0_ap_continue = weight_vecs_0_i_full_n; + +assign tdf7_readFilters52_U0_ap_start = start_for_tdf7_readFilters52_U0_empty_n; + +assign tdf7_readFilters52_U0_start_full_n = 1'b1; + +assign tdf7_readFilters52_U0_start_write = 1'b0; + +assign tdf7_readFilters52_U0_weight_vecs_0_full_n = weight_vecs_0_i_full_n; + +assign tdf7_readInputs53_U0_ap_continue = ifmap_vec_i_full_n; + +assign tdf7_readInputs53_U0_ap_start = ((ap_sync_reg_tdf7_readInputs53_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf7_readInputs53_U0_ifmap_vec_full_n = ifmap_vec_i_full_n; + +assign tdf7_readInputs53_U0_in_data_full_n = in_data_empty_n; + +assign tdf7_readInputs53_U0_in_data_write = 1'b0; + +assign tdf7_readInputs53_U0_start_full_n = 1'b1; + +assign tdf7_readInputs53_U0_start_write = 1'b0; + +assign write4_c_din = tdf7_get_next_ijk_U0_write_r_din; + +endmodule //td_fused_top_dataflow_in_loop_TOP_LOOP37548 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37548_weight_vecs_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 10; +parameter MEM_SIZE = 576; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37548_weight_vecs_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd576; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37548_weight_vecs_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37548_weight_vecs_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37548_weight_vecs_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 9, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP37548_weight_vecs_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37548_weight_vecs_0_memcore_U ( + .reset ( reset ), + .clk ( clk ), + .address0 ( memcore_iaddr ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + .address1 ( memcore_taddr ), + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .d1 ( t_d0 ), + .q1 ( t_q0 ) + +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37644_accum1_out_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 3; +parameter MEM_SIZE = 8; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37644_accum1_out_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd8; +parameter AddressWidth = 32'd3; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37644_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37644_accum1_out_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37644_accum1_out_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 3, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37644_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37644_accum1_out_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37644_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37644_accum1_out_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37644_ifmap_vec_0_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 7; +parameter MEM_SIZE = 128; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37644_ifmap_vec_0_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd128; +parameter AddressWidth = 32'd7; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37644_ifmap_vec_0_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37644_ifmap_vec_0_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37644_ifmap_vec_0_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 7, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37644_ifmap_vec_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37644_ifmap_vec_0_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37644_ifmap_vec_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37644_ifmap_vec_0_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37644_products_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 7; +parameter MEM_SIZE = 128; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37644_products_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd128; +parameter AddressWidth = 32'd7; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37644_products_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37644_products_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37644_products_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 7, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire [AddressWidth-1:0] i_address1, + output wire [DataWidth-1:0] i_q1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire [AddressWidth-1:0] t_address1, + output wire [DataWidth-1:0] t_q1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_q1_0, buf_q1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37644_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37644_products_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .q1 ( buf_q1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37644_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37644_products_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .q1 ( buf_q1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign i_q1 = (prev_iptr == 1'b1 ? buf_q1_1 : buf_q1_0); +assign t_q1 = reg_valid1 ? reg_q1 : (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// reg_q1 and reg_valid1 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q1 <= 1'b0; + reg_valid1 <= 1'b0; + end else if (!t_ce1 && !reg_valid1) begin + reg_q1 <= (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + reg_valid1 <= 1'b1; + end else if (t_ce1) begin + reg_valid1 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37644 ( + ap_clk, + ap_rst, + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + ap_start, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +input ap_clk; +input ap_rst; +output [14:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [14:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [11:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [11:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [4:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [4:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +output [12:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [12:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +input ap_start; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +wire [15:0] ifmap_vec_0_0_i_q0; +wire [15:0] ifmap_vec_0_0_t_q0; +wire [15:0] weight_vecs_0_0_0_i_q0; +wire [15:0] weight_vecs_0_0_0_t_q0; +wire [15:0] products_0_i_q0; +wire [15:0] products_0_i_q1; +wire [15:0] products_0_t_q0; +wire [15:0] products_0_t_q1; +wire [15:0] accum1_out_0_i_q0; +wire [15:0] accum1_out_0_t_q0; +wire tdf6_get_next_ijk_U0_ap_start; +wire tdf6_get_next_ijk_U0_ap_done; +wire tdf6_get_next_ijk_U0_ap_continue; +wire tdf6_get_next_ijk_U0_ap_idle; +wire tdf6_get_next_ijk_U0_ap_ready; +wire tdf6_get_next_ijk_U0_start_out; +wire tdf6_get_next_ijk_U0_start_write; +wire [15:0] tdf6_get_next_ijk_U0_indices_0_din; +wire tdf6_get_next_ijk_U0_indices_0_write; +wire [15:0] tdf6_get_next_ijk_U0_indices_1_din; +wire tdf6_get_next_ijk_U0_indices_1_write; +wire [4:0] tdf6_get_next_ijk_U0_indices_2_out_din; +wire tdf6_get_next_ijk_U0_indices_2_out_write; +wire [4:0] tdf6_get_next_ijk_U0_indices_2_out1_din; +wire tdf6_get_next_ijk_U0_indices_2_out1_write; +wire tdf6_readInputs_U0_ap_start; +wire tdf6_readInputs_U0_ap_done; +wire tdf6_readInputs_U0_ap_continue; +wire tdf6_readInputs_U0_ap_idle; +wire tdf6_readInputs_U0_ap_ready; +wire [14:0] tdf6_readInputs_U0_in_data_address0; +wire tdf6_readInputs_U0_in_data_ce0; +wire tdf6_readInputs_U0_indices_01_read; +wire tdf6_readInputs_U0_indices_12_read; +wire [6:0] tdf6_readInputs_U0_ifmap_vec_0_0_address0; +wire tdf6_readInputs_U0_ifmap_vec_0_0_ce0; +wire tdf6_readInputs_U0_ifmap_vec_0_0_we0; +wire [15:0] tdf6_readInputs_U0_ifmap_vec_0_0_d0; +wire [6:0] tdf6_readInputs_U0_ifmap_vec_0_0_address1; +wire tdf6_readInputs_U0_ifmap_vec_0_0_ce1; +wire tdf6_readInputs_U0_ifmap_vec_0_0_we1; +wire [15:0] tdf6_readInputs_U0_ifmap_vec_0_0_d1; +wire [4:0] tdf6_readInputs_U0_indices_01_out_din; +wire tdf6_readInputs_U0_indices_01_out_write; +wire [9:0] tdf6_readInputs_U0_indices_12_out_din; +wire tdf6_readInputs_U0_indices_12_out_write; +wire tdf6_readInputs_U0_in_data_full_n; +wire tdf6_readInputs_U0_in_data_write; +wire ap_channel_done_ifmap_vec_0_0; +wire tdf6_readInputs_U0_ifmap_vec_0_0_full_n; +wire tdf6_readFilters46_U0_ap_start; +wire tdf6_readFilters46_U0_ap_done; +wire tdf6_readFilters46_U0_ap_continue; +wire tdf6_readFilters46_U0_ap_idle; +wire tdf6_readFilters46_U0_ap_ready; +wire [11:0] tdf6_readFilters46_U0_filter_data_address0; +wire tdf6_readFilters46_U0_filter_data_ce0; +wire tdf6_readFilters46_U0_indices_23_read; +wire [6:0] tdf6_readFilters46_U0_weight_vecs_0_0_0_address0; +wire tdf6_readFilters46_U0_weight_vecs_0_0_0_ce0; +wire tdf6_readFilters46_U0_weight_vecs_0_0_0_we0; +wire [15:0] tdf6_readFilters46_U0_weight_vecs_0_0_0_d0; +wire ap_channel_done_weight_vecs_0_0_0; +wire tdf6_readFilters46_U0_weight_vecs_0_0_0_full_n; +wire tdf6_dot_product_U0_ap_start; +wire tdf6_dot_product_U0_ap_done; +wire tdf6_dot_product_U0_ap_continue; +wire tdf6_dot_product_U0_ap_idle; +wire tdf6_dot_product_U0_ap_ready; +wire [6:0] tdf6_dot_product_U0_ifmap_vec_0_0_address0; +wire tdf6_dot_product_U0_ifmap_vec_0_0_ce0; +wire [6:0] tdf6_dot_product_U0_weight_vecs_0_0_0_address0; +wire tdf6_dot_product_U0_weight_vecs_0_0_0_ce0; +wire [6:0] tdf6_dot_product_U0_products_0_address0; +wire tdf6_dot_product_U0_products_0_ce0; +wire tdf6_dot_product_U0_products_0_we0; +wire [15:0] tdf6_dot_product_U0_products_0_d0; +wire ap_channel_done_products_0; +wire tdf6_dot_product_U0_products_0_full_n; +wire tdf6_accum_1_U0_ap_start; +wire tdf6_accum_1_U0_ap_done; +wire tdf6_accum_1_U0_ap_continue; +wire tdf6_accum_1_U0_ap_idle; +wire tdf6_accum_1_U0_ap_ready; +wire [6:0] tdf6_accum_1_U0_accum_in_0_address0; +wire tdf6_accum_1_U0_accum_in_0_ce0; +wire [6:0] tdf6_accum_1_U0_accum_in_0_address1; +wire tdf6_accum_1_U0_accum_in_0_ce1; +wire [2:0] tdf6_accum_1_U0_accum_out_address0; +wire tdf6_accum_1_U0_accum_out_ce0; +wire tdf6_accum_1_U0_accum_out_we0; +wire [15:0] tdf6_accum_1_U0_accum_out_d0; +wire [2:0] tdf6_accum_1_U0_accum_out_address1; +wire tdf6_accum_1_U0_accum_out_ce1; +wire tdf6_accum_1_U0_accum_out_we1; +wire [15:0] tdf6_accum_1_U0_accum_out_d1; +wire ap_channel_done_accum1_out_0; +wire tdf6_accum_1_U0_accum_out_full_n; +wire tdf6_accum_2_U0_ap_start; +wire tdf6_accum_2_U0_ap_done; +wire tdf6_accum_2_U0_ap_continue; +wire tdf6_accum_2_U0_ap_idle; +wire tdf6_accum_2_U0_ap_ready; +wire [15:0] tdf6_accum_2_U0_accum_in_8; +wire tdf6_accum_2_U0_accum_in_8_ap_vld; +wire [2:0] tdf6_accum_2_U0_accum_in_address0; +wire tdf6_accum_2_U0_accum_in_ce0; +wire ap_channel_done_tmp_channel; +wire tmp_channel_full_n; +wire Block_entry_proc_proc413_U0_ap_start; +wire Block_entry_proc_proc413_U0_ap_done; +wire Block_entry_proc_proc413_U0_ap_continue; +wire Block_entry_proc_proc413_U0_ap_idle; +wire Block_entry_proc_proc413_U0_ap_ready; +wire [15:0] Block_entry_proc_proc413_U0_ap_return; +wire ap_channel_done_sums_0; +wire sums_0_full_n; +wire tdf6_adjust_U0_ap_start; +wire tdf6_adjust_U0_ap_done; +wire tdf6_adjust_U0_ap_continue; +wire tdf6_adjust_U0_ap_idle; +wire tdf6_adjust_U0_ap_ready; +wire [4:0] tdf6_adjust_U0_adjustments_address0; +wire tdf6_adjust_U0_adjustments_ce0; +wire tdf6_adjust_U0_indices_23_read; +wire [15:0] tdf6_adjust_U0_ap_return; +wire ap_channel_done_outputs_0; +wire outputs_0_full_n; +wire tdf6_writeOutputs_unaligned_U0_ap_start; +wire tdf6_writeOutputs_unaligned_U0_ap_done; +wire tdf6_writeOutputs_unaligned_U0_ap_continue; +wire tdf6_writeOutputs_unaligned_U0_ap_idle; +wire tdf6_writeOutputs_unaligned_U0_ap_ready; +wire tdf6_writeOutputs_unaligned_U0_indices_01_read; +wire tdf6_writeOutputs_unaligned_U0_indices_12_read; +wire [12:0] tdf6_writeOutputs_unaligned_U0_out_data_address1; +wire tdf6_writeOutputs_unaligned_U0_out_data_ce1; +wire tdf6_writeOutputs_unaligned_U0_out_data_we1; +wire [63:0] tdf6_writeOutputs_unaligned_U0_out_data_d1; +wire tdf6_writeOutputs_unaligned_U0_out_data_full_n; +wire tdf6_writeOutputs_unaligned_U0_out_data_write; +wire ap_sync_continue; +wire ifmap_vec_0_0_i_full_n; +wire ifmap_vec_0_0_t_empty_n; +wire weight_vecs_0_0_0_i_full_n; +wire weight_vecs_0_0_0_t_empty_n; +wire products_0_i_full_n; +wire products_0_t_empty_n; +wire [15:0] products_0_t_d1; +wire products_0_t_we1; +wire accum1_out_0_i_full_n; +wire accum1_out_0_t_empty_n; +wire indices_01_c_full_n; +wire [15:0] indices_01_c_dout; +wire indices_01_c_empty_n; +wire indices_12_c_full_n; +wire [15:0] indices_12_c_dout; +wire indices_12_c_empty_n; +wire indices_23_c_full_n; +wire [4:0] indices_23_c_dout; +wire indices_23_c_empty_n; +wire indices_23_c1_full_n; +wire [4:0] indices_23_c1_dout; +wire indices_23_c1_empty_n; +wire indices_01_c2_full_n; +wire [4:0] indices_01_c2_dout; +wire indices_01_c2_empty_n; +wire indices_12_c3_full_n; +wire [9:0] indices_12_c3_dout; +wire indices_12_c3_empty_n; +wire [15:0] tmp_channel_dout; +wire tmp_channel_empty_n; +wire [15:0] sums_0_dout; +wire sums_0_empty_n; +wire [15:0] outputs_0_dout; +wire outputs_0_empty_n; +wire ap_sync_done; +wire ap_sync_ready; +reg ap_sync_reg_tdf6_get_next_ijk_U0_ap_ready; +wire ap_sync_tdf6_get_next_ijk_U0_ap_ready; +reg ap_sync_reg_tdf6_readInputs_U0_ap_ready; +wire ap_sync_tdf6_readInputs_U0_ap_ready; +wire [0:0] start_for_tdf6_readFilters46_U0_din; +wire start_for_tdf6_readFilters46_U0_full_n; +wire [0:0] start_for_tdf6_readFilters46_U0_dout; +wire start_for_tdf6_readFilters46_U0_empty_n; +wire tdf6_readInputs_U0_start_full_n; +wire tdf6_readInputs_U0_start_write; +wire tdf6_readFilters46_U0_start_full_n; +wire tdf6_readFilters46_U0_start_write; +wire tdf6_dot_product_U0_start_full_n; +wire tdf6_dot_product_U0_start_write; +wire tdf6_accum_1_U0_start_full_n; +wire tdf6_accum_1_U0_start_write; +wire tdf6_accum_2_U0_start_full_n; +wire tdf6_accum_2_U0_start_write; +wire Block_entry_proc_proc413_U0_start_full_n; +wire Block_entry_proc_proc413_U0_start_write; +wire tdf6_adjust_U0_start_full_n; +wire tdf6_adjust_U0_start_write; +wire tdf6_writeOutputs_unaligned_U0_start_full_n; +wire tdf6_writeOutputs_unaligned_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_sync_reg_tdf6_get_next_ijk_U0_ap_ready = 1'b0; +#0 ap_sync_reg_tdf6_readInputs_U0_ap_ready = 1'b0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP37644_ifmap_vec_0_0 #( + .DataWidth( 16 ), + .AddressRange( 128 ), + .AddressWidth( 7 )) +ifmap_vec_0_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf6_readInputs_U0_ap_done), + .i_full_n(ifmap_vec_0_0_i_full_n), + .i_ce0(tdf6_readInputs_U0_ifmap_vec_0_0_ce0), + .i_we0(tdf6_readInputs_U0_ifmap_vec_0_0_we0), + .i_address0(tdf6_readInputs_U0_ifmap_vec_0_0_address0), + .i_d0(tdf6_readInputs_U0_ifmap_vec_0_0_d0), + .i_q0(ifmap_vec_0_0_i_q0), + .i_ce1(tdf6_readInputs_U0_ifmap_vec_0_0_ce1), + .i_we1(tdf6_readInputs_U0_ifmap_vec_0_0_we1), + .i_address1(tdf6_readInputs_U0_ifmap_vec_0_0_address1), + .i_d1(tdf6_readInputs_U0_ifmap_vec_0_0_d1), + .t_ce(1'b1), + .t_read(tdf6_dot_product_U0_ap_ready), + .t_empty_n(ifmap_vec_0_0_t_empty_n), + .t_ce0(tdf6_dot_product_U0_ifmap_vec_0_0_ce0), + .t_we0(1'b0), + .t_address0(tdf6_dot_product_U0_ifmap_vec_0_0_address0), + .t_d0(16'd0), + .t_q0(ifmap_vec_0_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(7'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37644_weight_vecs_0_0_0 #( + .DataWidth( 16 ), + .AddressRange( 128 ), + .AddressWidth( 7 )) +weight_vecs_0_0_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf6_readFilters46_U0_ap_done), + .i_full_n(weight_vecs_0_0_0_i_full_n), + .i_ce0(tdf6_readFilters46_U0_weight_vecs_0_0_0_ce0), + .i_we0(tdf6_readFilters46_U0_weight_vecs_0_0_0_we0), + .i_address0(tdf6_readFilters46_U0_weight_vecs_0_0_0_address0), + .i_d0(tdf6_readFilters46_U0_weight_vecs_0_0_0_d0), + .i_q0(weight_vecs_0_0_0_i_q0), + .t_ce(1'b1), + .t_read(tdf6_dot_product_U0_ap_ready), + .t_empty_n(weight_vecs_0_0_0_t_empty_n), + .t_ce0(tdf6_dot_product_U0_weight_vecs_0_0_0_ce0), + .t_we0(1'b0), + .t_address0(tdf6_dot_product_U0_weight_vecs_0_0_0_address0), + .t_d0(16'd0), + .t_q0(weight_vecs_0_0_0_t_q0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37644_products_0 #( + .DataWidth( 16 ), + .AddressRange( 128 ), + .AddressWidth( 7 )) +products_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf6_dot_product_U0_ap_done), + .i_full_n(products_0_i_full_n), + .i_ce0(tdf6_dot_product_U0_products_0_ce0), + .i_we0(tdf6_dot_product_U0_products_0_we0), + .i_address0(tdf6_dot_product_U0_products_0_address0), + .i_d0(tdf6_dot_product_U0_products_0_d0), + .i_q0(products_0_i_q0), + .i_ce1(1'b0), + .i_address1(7'd0), + .i_q1(products_0_i_q1), + .t_ce(1'b1), + .t_read(tdf6_accum_1_U0_ap_ready), + .t_empty_n(products_0_t_empty_n), + .t_ce0(tdf6_accum_1_U0_accum_in_0_ce0), + .t_we0(1'b0), + .t_address0(tdf6_accum_1_U0_accum_in_0_address0), + .t_d0(16'd0), + .t_q0(products_0_t_q0), + .t_ce1(tdf6_accum_1_U0_accum_in_0_ce1), + .t_address1(tdf6_accum_1_U0_accum_in_0_address1), + .t_q1(products_0_t_q1) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37644_accum1_out_0 #( + .DataWidth( 16 ), + .AddressRange( 8 ), + .AddressWidth( 3 )) +accum1_out_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf6_accum_1_U0_ap_done), + .i_full_n(accum1_out_0_i_full_n), + .i_ce0(tdf6_accum_1_U0_accum_out_ce0), + .i_we0(tdf6_accum_1_U0_accum_out_we0), + .i_address0(tdf6_accum_1_U0_accum_out_address0), + .i_d0(tdf6_accum_1_U0_accum_out_d0), + .i_q0(accum1_out_0_i_q0), + .i_ce1(tdf6_accum_1_U0_accum_out_ce1), + .i_we1(tdf6_accum_1_U0_accum_out_we1), + .i_address1(tdf6_accum_1_U0_accum_out_address1), + .i_d1(tdf6_accum_1_U0_accum_out_d1), + .t_ce(1'b1), + .t_read(tdf6_accum_2_U0_ap_ready), + .t_empty_n(accum1_out_0_t_empty_n), + .t_ce0(tdf6_accum_2_U0_accum_in_ce0), + .t_we0(1'b0), + .t_address0(tdf6_accum_2_U0_accum_in_address0), + .t_d0(16'd0), + .t_q0(accum1_out_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(3'd0), + .t_d1(16'd0) +); + +td_fused_top_tdf6_get_next_ijk tdf6_get_next_ijk_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf6_get_next_ijk_U0_ap_start), + .start_full_n(start_for_tdf6_readFilters46_U0_full_n), + .ap_done(tdf6_get_next_ijk_U0_ap_done), + .ap_continue(tdf6_get_next_ijk_U0_ap_continue), + .ap_idle(tdf6_get_next_ijk_U0_ap_idle), + .ap_ready(tdf6_get_next_ijk_U0_ap_ready), + .start_out(tdf6_get_next_ijk_U0_start_out), + .start_write(tdf6_get_next_ijk_U0_start_write), + .indices_0_din(tdf6_get_next_ijk_U0_indices_0_din), + .indices_0_full_n(indices_01_c_full_n), + .indices_0_write(tdf6_get_next_ijk_U0_indices_0_write), + .indices_1_din(tdf6_get_next_ijk_U0_indices_1_din), + .indices_1_full_n(indices_12_c_full_n), + .indices_1_write(tdf6_get_next_ijk_U0_indices_1_write), + .indices_2_out_din(tdf6_get_next_ijk_U0_indices_2_out_din), + .indices_2_out_full_n(indices_23_c_full_n), + .indices_2_out_write(tdf6_get_next_ijk_U0_indices_2_out_write), + .indices_2_out1_din(tdf6_get_next_ijk_U0_indices_2_out1_din), + .indices_2_out1_full_n(indices_23_c1_full_n), + .indices_2_out1_write(tdf6_get_next_ijk_U0_indices_2_out1_write) +); + +td_fused_top_tdf6_readInputs tdf6_readInputs_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf6_readInputs_U0_ap_start), + .ap_done(tdf6_readInputs_U0_ap_done), + .ap_continue(tdf6_readInputs_U0_ap_continue), + .ap_idle(tdf6_readInputs_U0_ap_idle), + .ap_ready(tdf6_readInputs_U0_ap_ready), + .in_data_address0(tdf6_readInputs_U0_in_data_address0), + .in_data_ce0(tdf6_readInputs_U0_in_data_ce0), + .in_data_q0(in_data_q0), + .indices_01_dout(indices_01_c_dout), + .indices_01_empty_n(indices_01_c_empty_n), + .indices_01_read(tdf6_readInputs_U0_indices_01_read), + .indices_12_dout(indices_12_c_dout), + .indices_12_empty_n(indices_12_c_empty_n), + .indices_12_read(tdf6_readInputs_U0_indices_12_read), + .ifmap_vec_0_0_address0(tdf6_readInputs_U0_ifmap_vec_0_0_address0), + .ifmap_vec_0_0_ce0(tdf6_readInputs_U0_ifmap_vec_0_0_ce0), + .ifmap_vec_0_0_we0(tdf6_readInputs_U0_ifmap_vec_0_0_we0), + .ifmap_vec_0_0_d0(tdf6_readInputs_U0_ifmap_vec_0_0_d0), + .ifmap_vec_0_0_address1(tdf6_readInputs_U0_ifmap_vec_0_0_address1), + .ifmap_vec_0_0_ce1(tdf6_readInputs_U0_ifmap_vec_0_0_ce1), + .ifmap_vec_0_0_we1(tdf6_readInputs_U0_ifmap_vec_0_0_we1), + .ifmap_vec_0_0_d1(tdf6_readInputs_U0_ifmap_vec_0_0_d1), + .indices_01_out_din(tdf6_readInputs_U0_indices_01_out_din), + .indices_01_out_full_n(indices_01_c2_full_n), + .indices_01_out_write(tdf6_readInputs_U0_indices_01_out_write), + .indices_12_out_din(tdf6_readInputs_U0_indices_12_out_din), + .indices_12_out_full_n(indices_12_c3_full_n), + .indices_12_out_write(tdf6_readInputs_U0_indices_12_out_write) +); + +td_fused_top_tdf6_readFilters46 tdf6_readFilters46_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf6_readFilters46_U0_ap_start), + .ap_done(tdf6_readFilters46_U0_ap_done), + .ap_continue(tdf6_readFilters46_U0_ap_continue), + .ap_idle(tdf6_readFilters46_U0_ap_idle), + .ap_ready(tdf6_readFilters46_U0_ap_ready), + .filter_data_address0(tdf6_readFilters46_U0_filter_data_address0), + .filter_data_ce0(tdf6_readFilters46_U0_filter_data_ce0), + .filter_data_q0(filter_data_q0), + .indices_23_dout(indices_23_c_dout), + .indices_23_empty_n(indices_23_c_empty_n), + .indices_23_read(tdf6_readFilters46_U0_indices_23_read), + .weight_vecs_0_0_0_address0(tdf6_readFilters46_U0_weight_vecs_0_0_0_address0), + .weight_vecs_0_0_0_ce0(tdf6_readFilters46_U0_weight_vecs_0_0_0_ce0), + .weight_vecs_0_0_0_we0(tdf6_readFilters46_U0_weight_vecs_0_0_0_we0), + .weight_vecs_0_0_0_d0(tdf6_readFilters46_U0_weight_vecs_0_0_0_d0) +); + +td_fused_top_tdf6_dot_product tdf6_dot_product_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf6_dot_product_U0_ap_start), + .ap_done(tdf6_dot_product_U0_ap_done), + .ap_continue(tdf6_dot_product_U0_ap_continue), + .ap_idle(tdf6_dot_product_U0_ap_idle), + .ap_ready(tdf6_dot_product_U0_ap_ready), + .ifmap_vec_0_0_address0(tdf6_dot_product_U0_ifmap_vec_0_0_address0), + .ifmap_vec_0_0_ce0(tdf6_dot_product_U0_ifmap_vec_0_0_ce0), + .ifmap_vec_0_0_q0(ifmap_vec_0_0_t_q0), + .weight_vecs_0_0_0_address0(tdf6_dot_product_U0_weight_vecs_0_0_0_address0), + .weight_vecs_0_0_0_ce0(tdf6_dot_product_U0_weight_vecs_0_0_0_ce0), + .weight_vecs_0_0_0_q0(weight_vecs_0_0_0_t_q0), + .products_0_address0(tdf6_dot_product_U0_products_0_address0), + .products_0_ce0(tdf6_dot_product_U0_products_0_ce0), + .products_0_we0(tdf6_dot_product_U0_products_0_we0), + .products_0_d0(tdf6_dot_product_U0_products_0_d0) +); + +td_fused_top_tdf6_accum_1 tdf6_accum_1_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf6_accum_1_U0_ap_start), + .ap_done(tdf6_accum_1_U0_ap_done), + .ap_continue(tdf6_accum_1_U0_ap_continue), + .ap_idle(tdf6_accum_1_U0_ap_idle), + .ap_ready(tdf6_accum_1_U0_ap_ready), + .accum_in_0_address0(tdf6_accum_1_U0_accum_in_0_address0), + .accum_in_0_ce0(tdf6_accum_1_U0_accum_in_0_ce0), + .accum_in_0_q0(products_0_t_q0), + .accum_in_0_address1(tdf6_accum_1_U0_accum_in_0_address1), + .accum_in_0_ce1(tdf6_accum_1_U0_accum_in_0_ce1), + .accum_in_0_q1(products_0_t_q1), + .accum_out_address0(tdf6_accum_1_U0_accum_out_address0), + .accum_out_ce0(tdf6_accum_1_U0_accum_out_ce0), + .accum_out_we0(tdf6_accum_1_U0_accum_out_we0), + .accum_out_d0(tdf6_accum_1_U0_accum_out_d0), + .accum_out_address1(tdf6_accum_1_U0_accum_out_address1), + .accum_out_ce1(tdf6_accum_1_U0_accum_out_ce1), + .accum_out_we1(tdf6_accum_1_U0_accum_out_we1), + .accum_out_d1(tdf6_accum_1_U0_accum_out_d1) +); + +td_fused_top_tdf6_accum_2 tdf6_accum_2_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf6_accum_2_U0_ap_start), + .ap_done(tdf6_accum_2_U0_ap_done), + .ap_continue(tdf6_accum_2_U0_ap_continue), + .ap_idle(tdf6_accum_2_U0_ap_idle), + .ap_ready(tdf6_accum_2_U0_ap_ready), + .accum_in_8(tdf6_accum_2_U0_accum_in_8), + .accum_in_8_ap_vld(tdf6_accum_2_U0_accum_in_8_ap_vld), + .accum_in_address0(tdf6_accum_2_U0_accum_in_address0), + .accum_in_ce0(tdf6_accum_2_U0_accum_in_ce0), + .accum_in_q0(accum1_out_0_t_q0) +); + +td_fused_top_Block_entry_proc_proc413 Block_entry_proc_proc413_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(Block_entry_proc_proc413_U0_ap_start), + .ap_done(Block_entry_proc_proc413_U0_ap_done), + .ap_continue(Block_entry_proc_proc413_U0_ap_continue), + .ap_idle(Block_entry_proc_proc413_U0_ap_idle), + .ap_ready(Block_entry_proc_proc413_U0_ap_ready), + .tmp(tmp_channel_dout), + .ap_return(Block_entry_proc_proc413_U0_ap_return) +); + +td_fused_top_tdf6_adjust tdf6_adjust_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf6_adjust_U0_ap_start), + .ap_done(tdf6_adjust_U0_ap_done), + .ap_continue(tdf6_adjust_U0_ap_continue), + .ap_idle(tdf6_adjust_U0_ap_idle), + .ap_ready(tdf6_adjust_U0_ap_ready), + .sums_read(sums_0_dout), + .adjustments_address0(tdf6_adjust_U0_adjustments_address0), + .adjustments_ce0(tdf6_adjust_U0_adjustments_ce0), + .adjustments_q0(adjustments_q0), + .indices_23_dout(indices_23_c1_dout), + .indices_23_empty_n(indices_23_c1_empty_n), + .indices_23_read(tdf6_adjust_U0_indices_23_read), + .ap_return(tdf6_adjust_U0_ap_return) +); + +td_fused_top_tdf6_writeOutputs_unaligned tdf6_writeOutputs_unaligned_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf6_writeOutputs_unaligned_U0_ap_start), + .ap_done(tdf6_writeOutputs_unaligned_U0_ap_done), + .ap_continue(tdf6_writeOutputs_unaligned_U0_ap_continue), + .ap_idle(tdf6_writeOutputs_unaligned_U0_ap_idle), + .ap_ready(tdf6_writeOutputs_unaligned_U0_ap_ready), + .indices_01_dout(indices_01_c2_dout), + .indices_01_empty_n(indices_01_c2_empty_n), + .indices_01_read(tdf6_writeOutputs_unaligned_U0_indices_01_read), + .indices_12_dout(indices_12_c3_dout), + .indices_12_empty_n(indices_12_c3_empty_n), + .indices_12_read(tdf6_writeOutputs_unaligned_U0_indices_12_read), + .p_read(outputs_0_dout), + .out_data_address1(tdf6_writeOutputs_unaligned_U0_out_data_address1), + .out_data_ce1(tdf6_writeOutputs_unaligned_U0_out_data_ce1), + .out_data_we1(tdf6_writeOutputs_unaligned_U0_out_data_we1), + .out_data_d1(tdf6_writeOutputs_unaligned_U0_out_data_d1) +); + +td_fused_top_fifo_w16_d2_S_x3 indices_01_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf6_readInputs_U0_indices_01_read), + .if_dout(indices_01_c_dout), + .if_full_n(indices_01_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf6_get_next_ijk_U0_indices_0_write), + .if_din(tdf6_get_next_ijk_U0_indices_0_din) +); + +td_fused_top_fifo_w16_d2_S_x3 indices_12_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf6_readInputs_U0_indices_12_read), + .if_dout(indices_12_c_dout), + .if_full_n(indices_12_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf6_get_next_ijk_U0_indices_1_write), + .if_din(tdf6_get_next_ijk_U0_indices_1_din) +); + +td_fused_top_fifo_w5_d2_S_x indices_23_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf6_readFilters46_U0_indices_23_read), + .if_dout(indices_23_c_dout), + .if_full_n(indices_23_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf6_get_next_ijk_U0_indices_2_out_write), + .if_din(tdf6_get_next_ijk_U0_indices_2_out_din) +); + +td_fused_top_fifo_w5_d7_S_x indices_23_c1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf6_adjust_U0_indices_23_read), + .if_dout(indices_23_c1_dout), + .if_full_n(indices_23_c1_full_n), + .if_write_ce(1'b1), + .if_write(tdf6_get_next_ijk_U0_indices_2_out1_write), + .if_din(tdf6_get_next_ijk_U0_indices_2_out1_din) +); + +td_fused_top_fifo_w5_d7_S_x indices_01_c2_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c2_empty_n), + .if_read_ce(1'b1), + .if_read(tdf6_writeOutputs_unaligned_U0_indices_01_read), + .if_dout(indices_01_c2_dout), + .if_full_n(indices_01_c2_full_n), + .if_write_ce(1'b1), + .if_write(tdf6_readInputs_U0_indices_01_out_write), + .if_din(tdf6_readInputs_U0_indices_01_out_din) +); + +td_fused_top_fifo_w10_d7_S indices_12_c3_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c3_empty_n), + .if_read_ce(1'b1), + .if_read(tdf6_writeOutputs_unaligned_U0_indices_12_read), + .if_dout(indices_12_c3_dout), + .if_full_n(indices_12_c3_full_n), + .if_write_ce(1'b1), + .if_write(tdf6_readInputs_U0_indices_12_out_write), + .if_din(tdf6_readInputs_U0_indices_12_out_din) +); + +td_fused_top_fifo_w16_d2_S_x3 tmp_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(tmp_channel_empty_n), + .if_read_ce(1'b1), + .if_read(Block_entry_proc_proc413_U0_ap_ready), + .if_dout(tmp_channel_dout), + .if_full_n(tmp_channel_full_n), + .if_write_ce(1'b1), + .if_write(tdf6_accum_2_U0_ap_done), + .if_din(tdf6_accum_2_U0_accum_in_8) +); + +td_fused_top_fifo_w16_d2_S_x3 sums_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(sums_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf6_adjust_U0_ap_ready), + .if_dout(sums_0_dout), + .if_full_n(sums_0_full_n), + .if_write_ce(1'b1), + .if_write(Block_entry_proc_proc413_U0_ap_done), + .if_din(Block_entry_proc_proc413_U0_ap_return) +); + +td_fused_top_fifo_w16_d2_S_x3 outputs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(outputs_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf6_writeOutputs_unaligned_U0_ap_ready), + .if_dout(outputs_0_dout), + .if_full_n(outputs_0_full_n), + .if_write_ce(1'b1), + .if_write(tdf6_adjust_U0_ap_done), + .if_din(tdf6_adjust_U0_ap_return) +); + +td_fused_top_start_for_tdf6_readFilters46_U0 start_for_tdf6_readFilters46_U0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(start_for_tdf6_readFilters46_U0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf6_readFilters46_U0_ap_ready), + .if_dout(start_for_tdf6_readFilters46_U0_dout), + .if_full_n(start_for_tdf6_readFilters46_U0_full_n), + .if_write_ce(1'b1), + .if_write(tdf6_get_next_ijk_U0_start_write), + .if_din(start_for_tdf6_readFilters46_U0_din) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf6_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf6_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf6_get_next_ijk_U0_ap_ready <= ap_sync_tdf6_get_next_ijk_U0_ap_ready; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf6_readInputs_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf6_readInputs_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf6_readInputs_U0_ap_ready <= ap_sync_tdf6_readInputs_U0_ap_ready; + end + end +end + +assign Block_entry_proc_proc413_U0_ap_continue = sums_0_full_n; + +assign Block_entry_proc_proc413_U0_ap_start = tmp_channel_empty_n; + +assign Block_entry_proc_proc413_U0_start_full_n = 1'b1; + +assign Block_entry_proc_proc413_U0_start_write = 1'b0; + +assign adjustments_address0 = tdf6_adjust_U0_adjustments_address0; + +assign adjustments_address1 = 5'd0; + +assign adjustments_ce0 = tdf6_adjust_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_channel_done_accum1_out_0 = tdf6_accum_1_U0_ap_done; + +assign ap_channel_done_ifmap_vec_0_0 = tdf6_readInputs_U0_ap_done; + +assign ap_channel_done_outputs_0 = tdf6_adjust_U0_ap_done; + +assign ap_channel_done_products_0 = tdf6_dot_product_U0_ap_done; + +assign ap_channel_done_sums_0 = Block_entry_proc_proc413_U0_ap_done; + +assign ap_channel_done_tmp_channel = tdf6_accum_2_U0_ap_done; + +assign ap_channel_done_weight_vecs_0_0_0 = tdf6_readFilters46_U0_ap_done; + +assign ap_done = tdf6_writeOutputs_unaligned_U0_ap_done; + +assign ap_idle = (tdf6_writeOutputs_unaligned_U0_ap_idle & tdf6_readInputs_U0_ap_idle & tdf6_readFilters46_U0_ap_idle & tdf6_get_next_ijk_U0_ap_idle & tdf6_dot_product_U0_ap_idle & tdf6_adjust_U0_ap_idle & tdf6_accum_2_U0_ap_idle & tdf6_accum_1_U0_ap_idle & (outputs_0_empty_n ^ 1'b1) & (sums_0_empty_n ^ 1'b1) & (tmp_channel_empty_n ^ 1'b1) & (products_0_t_empty_n ^ 1'b1) & (weight_vecs_0_0_0_t_empty_n ^ 1'b1) & (ifmap_vec_0_0_t_empty_n ^ 1'b1) & (1'b1 ^ accum1_out_0_t_empty_n) & Block_entry_proc_proc413_U0_ap_idle); + +assign ap_ready = ap_sync_ready; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = tdf6_writeOutputs_unaligned_U0_ap_done; + +assign ap_sync_ready = (ap_sync_tdf6_readInputs_U0_ap_ready & ap_sync_tdf6_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf6_get_next_ijk_U0_ap_ready = (tdf6_get_next_ijk_U0_ap_ready | ap_sync_reg_tdf6_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf6_readInputs_U0_ap_ready = (tdf6_readInputs_U0_ap_ready | ap_sync_reg_tdf6_readInputs_U0_ap_ready); + +assign filter_data_address0 = tdf6_readFilters46_U0_filter_data_address0; + +assign filter_data_address1 = 12'd0; + +assign filter_data_ce0 = tdf6_readFilters46_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = tdf6_readInputs_U0_in_data_address0; + +assign in_data_address1 = 15'd0; + +assign in_data_ce0 = tdf6_readInputs_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = tdf6_readInputs_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 13'd0; + +assign out_data_address1 = tdf6_writeOutputs_unaligned_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = tdf6_writeOutputs_unaligned_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = tdf6_writeOutputs_unaligned_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = tdf6_writeOutputs_unaligned_U0_out_data_we1; + +assign out_data_write = tdf6_writeOutputs_unaligned_U0_out_data_write; + +assign products_0_t_d1 = 16'd0; + +assign products_0_t_we1 = 1'b0; + +assign start_for_tdf6_readFilters46_U0_din = 1'b1; + +assign tdf6_accum_1_U0_accum_out_full_n = accum1_out_0_i_full_n; + +assign tdf6_accum_1_U0_ap_continue = accum1_out_0_i_full_n; + +assign tdf6_accum_1_U0_ap_start = products_0_t_empty_n; + +assign tdf6_accum_1_U0_start_full_n = 1'b1; + +assign tdf6_accum_1_U0_start_write = 1'b0; + +assign tdf6_accum_2_U0_ap_continue = tmp_channel_full_n; + +assign tdf6_accum_2_U0_ap_start = accum1_out_0_t_empty_n; + +assign tdf6_accum_2_U0_start_full_n = 1'b1; + +assign tdf6_accum_2_U0_start_write = 1'b0; + +assign tdf6_adjust_U0_ap_continue = outputs_0_full_n; + +assign tdf6_adjust_U0_ap_start = sums_0_empty_n; + +assign tdf6_adjust_U0_start_full_n = 1'b1; + +assign tdf6_adjust_U0_start_write = 1'b0; + +assign tdf6_dot_product_U0_ap_continue = products_0_i_full_n; + +assign tdf6_dot_product_U0_ap_start = (weight_vecs_0_0_0_t_empty_n & ifmap_vec_0_0_t_empty_n); + +assign tdf6_dot_product_U0_products_0_full_n = products_0_i_full_n; + +assign tdf6_dot_product_U0_start_full_n = 1'b1; + +assign tdf6_dot_product_U0_start_write = 1'b0; + +assign tdf6_get_next_ijk_U0_ap_continue = 1'b1; + +assign tdf6_get_next_ijk_U0_ap_start = ((ap_sync_reg_tdf6_get_next_ijk_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf6_readFilters46_U0_ap_continue = weight_vecs_0_0_0_i_full_n; + +assign tdf6_readFilters46_U0_ap_start = start_for_tdf6_readFilters46_U0_empty_n; + +assign tdf6_readFilters46_U0_start_full_n = 1'b1; + +assign tdf6_readFilters46_U0_start_write = 1'b0; + +assign tdf6_readFilters46_U0_weight_vecs_0_0_0_full_n = weight_vecs_0_0_0_i_full_n; + +assign tdf6_readInputs_U0_ap_continue = ifmap_vec_0_0_i_full_n; + +assign tdf6_readInputs_U0_ap_start = ((ap_sync_reg_tdf6_readInputs_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf6_readInputs_U0_ifmap_vec_0_0_full_n = ifmap_vec_0_0_i_full_n; + +assign tdf6_readInputs_U0_in_data_full_n = in_data_empty_n; + +assign tdf6_readInputs_U0_in_data_write = 1'b0; + +assign tdf6_readInputs_U0_start_full_n = 1'b1; + +assign tdf6_readInputs_U0_start_write = 1'b0; + +assign tdf6_writeOutputs_unaligned_U0_ap_continue = ap_continue; + +assign tdf6_writeOutputs_unaligned_U0_ap_start = outputs_0_empty_n; + +assign tdf6_writeOutputs_unaligned_U0_out_data_full_n = out_data_full_n; + +assign tdf6_writeOutputs_unaligned_U0_out_data_write = 1'b0; + +assign tdf6_writeOutputs_unaligned_U0_start_full_n = 1'b1; + +assign tdf6_writeOutputs_unaligned_U0_start_write = 1'b0; + +endmodule //td_fused_top_dataflow_in_loop_TOP_LOOP37644 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37644_weight_vecs_0_0_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 8; +parameter MEM_SIZE = 256; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37644_weight_vecs_0_0_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd256; +parameter AddressWidth = 32'd8; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37644_weight_vecs_0_0_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37644_weight_vecs_0_0_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37644_weight_vecs_0_0_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 7, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP37644_weight_vecs_0_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37644_weight_vecs_0_0_0_memcore_U ( + .reset ( reset ), + .clk ( clk ), + .address0 ( memcore_iaddr ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + .address1 ( memcore_taddr ), + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .d1 ( t_d0 ), + .q1 ( t_q0 ) + +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37738_accum1_out_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 3; +parameter MEM_SIZE = 8; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37738_accum1_out_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd8; +parameter AddressWidth = 32'd3; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37738_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37738_accum1_out_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37738_accum1_out_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 3, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37738_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37738_accum1_out_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37738_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37738_accum1_out_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37738_ifmap_vec_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 8; +parameter MEM_SIZE = 144; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37738_ifmap_vec_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd144; +parameter AddressWidth = 32'd8; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37738_ifmap_vec_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37738_ifmap_vec_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37738_ifmap_vec +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 8, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37738_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37738_ifmap_vec_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37738_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37738_ifmap_vec_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37738_products_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 8; +parameter MEM_SIZE = 144; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37738_products_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd144; +parameter AddressWidth = 32'd8; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37738_products_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37738_products_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37738_products_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 8, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire [AddressWidth-1:0] i_address1, + output wire [DataWidth-1:0] i_q1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire [AddressWidth-1:0] t_address1, + output wire [DataWidth-1:0] t_q1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_q1_0, buf_q1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37738_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37738_products_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .q1 ( buf_q1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37738_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37738_products_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .q1 ( buf_q1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign i_q1 = (prev_iptr == 1'b1 ? buf_q1_1 : buf_q1_0); +assign t_q1 = reg_valid1 ? reg_q1 : (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// reg_q1 and reg_valid1 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q1 <= 1'b0; + reg_valid1 <= 1'b0; + end else if (!t_ce1 && !reg_valid1) begin + reg_q1 <= (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + reg_valid1 <= 1'b1; + end else if (t_ce1) begin + reg_valid1 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37738 ( + ap_clk, + ap_rst, + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + ap_start, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +input ap_clk; +input ap_rst; +output [13:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [13:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [14:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [14:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [6:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [6:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +output [14:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [14:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +input ap_start; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +wire [15:0] ifmap_vec_i_q0; +wire [15:0] ifmap_vec_t_q0; +wire [15:0] weight_vecs_0_i_q0; +wire [15:0] weight_vecs_0_t_q0; +wire [15:0] products_0_i_q0; +wire [15:0] products_0_i_q1; +wire [15:0] products_0_t_q0; +wire [15:0] products_0_t_q1; +wire [15:0] accum1_out_0_i_q0; +wire [15:0] accum1_out_0_t_q0; +wire tdf5_get_next_ijk_U0_ap_start; +wire tdf5_get_next_ijk_U0_ap_done; +wire tdf5_get_next_ijk_U0_ap_continue; +wire tdf5_get_next_ijk_U0_ap_idle; +wire tdf5_get_next_ijk_U0_ap_ready; +wire tdf5_get_next_ijk_U0_start_out; +wire tdf5_get_next_ijk_U0_start_write; +wire [6:0] tdf5_get_next_ijk_U0_input_indices_2_out_din; +wire tdf5_get_next_ijk_U0_input_indices_2_out_write; +wire [6:0] tdf5_get_next_ijk_U0_input_indices_2_out1_din; +wire tdf5_get_next_ijk_U0_input_indices_2_out1_write; +wire [4:0] tdf5_get_next_ijk_U0_output_indices_0_din; +wire tdf5_get_next_ijk_U0_output_indices_0_write; +wire [9:0] tdf5_get_next_ijk_U0_output_indices_1_din; +wire tdf5_get_next_ijk_U0_output_indices_1_write; +wire tdf5_get_next_ijk_U0_resetMaximum_din; +wire tdf5_get_next_ijk_U0_resetMaximum_write; +wire tdf5_get_next_ijk_U0_storeOutput_din; +wire tdf5_get_next_ijk_U0_storeOutput_write; +wire [15:0] tdf5_get_next_ijk_U0_ap_return_0; +wire [15:0] tdf5_get_next_ijk_U0_ap_return_1; +wire ap_channel_done_input_indices_1; +wire input_indices_1_full_n; +reg ap_sync_reg_channel_write_input_indices_1; +wire ap_sync_channel_write_input_indices_1; +wire ap_channel_done_input_indices_0; +wire input_indices_0_full_n; +reg ap_sync_reg_channel_write_input_indices_0; +wire ap_sync_channel_write_input_indices_0; +wire tdf5_readInputs41_U0_ap_start; +wire tdf5_readInputs41_U0_ap_done; +wire tdf5_readInputs41_U0_ap_continue; +wire tdf5_readInputs41_U0_ap_idle; +wire tdf5_readInputs41_U0_ap_ready; +wire [13:0] tdf5_readInputs41_U0_in_data_address0; +wire tdf5_readInputs41_U0_in_data_ce0; +wire [7:0] tdf5_readInputs41_U0_ifmap_vec_address0; +wire tdf5_readInputs41_U0_ifmap_vec_ce0; +wire tdf5_readInputs41_U0_ifmap_vec_we0; +wire [15:0] tdf5_readInputs41_U0_ifmap_vec_d0; +wire [7:0] tdf5_readInputs41_U0_ifmap_vec_address1; +wire tdf5_readInputs41_U0_ifmap_vec_ce1; +wire tdf5_readInputs41_U0_ifmap_vec_we1; +wire [15:0] tdf5_readInputs41_U0_ifmap_vec_d1; +wire tdf5_readInputs41_U0_in_data_full_n; +wire tdf5_readInputs41_U0_in_data_write; +wire ap_channel_done_ifmap_vec; +wire tdf5_readInputs41_U0_ifmap_vec_full_n; +wire tdf5_readFilters40_U0_ap_start; +wire tdf5_readFilters40_U0_ap_done; +wire tdf5_readFilters40_U0_ap_continue; +wire tdf5_readFilters40_U0_ap_idle; +wire tdf5_readFilters40_U0_ap_ready; +wire [14:0] tdf5_readFilters40_U0_filter_data_address0; +wire tdf5_readFilters40_U0_filter_data_ce0; +wire tdf5_readFilters40_U0_input_indices_23_read; +wire [7:0] tdf5_readFilters40_U0_weight_vecs_0_address0; +wire tdf5_readFilters40_U0_weight_vecs_0_ce0; +wire tdf5_readFilters40_U0_weight_vecs_0_we0; +wire [15:0] tdf5_readFilters40_U0_weight_vecs_0_d0; +wire ap_channel_done_weight_vecs_0; +wire tdf5_readFilters40_U0_weight_vecs_0_full_n; +wire tdf5_dot_product_U0_ap_start; +wire tdf5_dot_product_U0_ap_done; +wire tdf5_dot_product_U0_ap_continue; +wire tdf5_dot_product_U0_ap_idle; +wire tdf5_dot_product_U0_ap_ready; +wire [7:0] tdf5_dot_product_U0_ifmap_vec_address0; +wire tdf5_dot_product_U0_ifmap_vec_ce0; +wire [7:0] tdf5_dot_product_U0_weight_vecs_0_address0; +wire tdf5_dot_product_U0_weight_vecs_0_ce0; +wire [7:0] tdf5_dot_product_U0_products_0_address0; +wire tdf5_dot_product_U0_products_0_ce0; +wire tdf5_dot_product_U0_products_0_we0; +wire [15:0] tdf5_dot_product_U0_products_0_d0; +wire ap_channel_done_products_0; +wire tdf5_dot_product_U0_products_0_full_n; +wire tdf5_accum_1_U0_ap_start; +wire tdf5_accum_1_U0_ap_done; +wire tdf5_accum_1_U0_ap_continue; +wire tdf5_accum_1_U0_ap_idle; +wire tdf5_accum_1_U0_ap_ready; +wire [7:0] tdf5_accum_1_U0_accum_in_0_address0; +wire tdf5_accum_1_U0_accum_in_0_ce0; +wire [7:0] tdf5_accum_1_U0_accum_in_0_address1; +wire tdf5_accum_1_U0_accum_in_0_ce1; +wire [2:0] tdf5_accum_1_U0_accum_out_address0; +wire tdf5_accum_1_U0_accum_out_ce0; +wire tdf5_accum_1_U0_accum_out_we0; +wire [15:0] tdf5_accum_1_U0_accum_out_d0; +wire [2:0] tdf5_accum_1_U0_accum_out_address1; +wire tdf5_accum_1_U0_accum_out_ce1; +wire tdf5_accum_1_U0_accum_out_we1; +wire [15:0] tdf5_accum_1_U0_accum_out_d1; +wire ap_channel_done_accum1_out_0; +wire tdf5_accum_1_U0_accum_out_full_n; +wire tdf5_accum_2_U0_ap_start; +wire tdf5_accum_2_U0_ap_done; +wire tdf5_accum_2_U0_ap_continue; +wire tdf5_accum_2_U0_ap_idle; +wire tdf5_accum_2_U0_ap_ready; +wire [15:0] tdf5_accum_2_U0_accum_in_10; +wire tdf5_accum_2_U0_accum_in_10_ap_vld; +wire [2:0] tdf5_accum_2_U0_accum_in_address0; +wire tdf5_accum_2_U0_accum_in_ce0; +wire ap_channel_done_tmp_channel; +wire tmp_channel_full_n; +wire Block_entry_proc_proc408_U0_ap_start; +wire Block_entry_proc_proc408_U0_ap_done; +wire Block_entry_proc_proc408_U0_ap_continue; +wire Block_entry_proc_proc408_U0_ap_idle; +wire Block_entry_proc_proc408_U0_ap_ready; +wire [15:0] Block_entry_proc_proc408_U0_ap_return; +wire ap_channel_done_sums_0; +wire sums_0_full_n; +wire tdf5_adjust_U0_ap_start; +wire tdf5_adjust_U0_ap_done; +wire tdf5_adjust_U0_ap_continue; +wire tdf5_adjust_U0_ap_idle; +wire tdf5_adjust_U0_ap_ready; +wire [6:0] tdf5_adjust_U0_adjustments_address0; +wire tdf5_adjust_U0_adjustments_ce0; +wire tdf5_adjust_U0_input_indices_23_read; +wire [15:0] tdf5_adjust_U0_ap_return; +wire ap_channel_done_outputs_0; +wire outputs_0_full_n; +wire tdf5_poolOutputs_U0_ap_start; +wire tdf5_poolOutputs_U0_ap_done; +wire tdf5_poolOutputs_U0_ap_continue; +wire tdf5_poolOutputs_U0_ap_idle; +wire tdf5_poolOutputs_U0_ap_ready; +wire tdf5_poolOutputs_U0_output_indices_04_read; +wire tdf5_poolOutputs_U0_output_indices_15_read; +wire tdf5_poolOutputs_U0_resetMaximum6_read; +wire tdf5_poolOutputs_U0_storeOutput7_read; +wire [14:0] tdf5_poolOutputs_U0_out_data_address1; +wire tdf5_poolOutputs_U0_out_data_ce1; +wire tdf5_poolOutputs_U0_out_data_we1; +wire [63:0] tdf5_poolOutputs_U0_out_data_d1; +wire tdf5_poolOutputs_U0_out_data_full_n; +wire tdf5_poolOutputs_U0_out_data_write; +wire ap_sync_continue; +wire ifmap_vec_i_full_n; +wire ifmap_vec_t_empty_n; +wire weight_vecs_0_i_full_n; +wire weight_vecs_0_t_empty_n; +wire products_0_i_full_n; +wire products_0_t_empty_n; +wire [15:0] products_0_t_d1; +wire products_0_t_we1; +wire accum1_out_0_i_full_n; +wire accum1_out_0_t_empty_n; +wire input_indices_23_c_full_n; +wire [6:0] input_indices_23_c_dout; +wire input_indices_23_c_empty_n; +wire input_indices_23_c1_full_n; +wire [6:0] input_indices_23_c1_dout; +wire input_indices_23_c1_empty_n; +wire output_indices_04_c_full_n; +wire [4:0] output_indices_04_c_dout; +wire output_indices_04_c_empty_n; +wire output_indices_15_c_full_n; +wire [9:0] output_indices_15_c_dout; +wire output_indices_15_c_empty_n; +wire [0:0] resetMaximum6_c_din; +wire resetMaximum6_c_full_n; +wire [0:0] resetMaximum6_c_dout; +wire resetMaximum6_c_empty_n; +wire [0:0] storeOutput7_c_din; +wire storeOutput7_c_full_n; +wire [0:0] storeOutput7_c_dout; +wire storeOutput7_c_empty_n; +wire [15:0] input_indices_0_dout; +wire input_indices_0_empty_n; +wire [15:0] input_indices_1_dout; +wire input_indices_1_empty_n; +wire [15:0] tmp_channel_dout; +wire tmp_channel_empty_n; +wire [15:0] sums_0_dout; +wire sums_0_empty_n; +wire [15:0] outputs_0_dout; +wire outputs_0_empty_n; +wire ap_sync_done; +wire ap_sync_ready; +reg ap_sync_reg_tdf5_get_next_ijk_U0_ap_ready; +wire ap_sync_tdf5_get_next_ijk_U0_ap_ready; +reg ap_sync_reg_tdf5_readInputs41_U0_ap_ready; +wire ap_sync_tdf5_readInputs41_U0_ap_ready; +wire [0:0] start_for_tdf5_readFilters40_U0_din; +wire start_for_tdf5_readFilters40_U0_full_n; +wire [0:0] start_for_tdf5_readFilters40_U0_dout; +wire start_for_tdf5_readFilters40_U0_empty_n; +wire tdf5_readInputs41_U0_start_full_n; +wire tdf5_readInputs41_U0_start_write; +wire tdf5_readFilters40_U0_start_full_n; +wire tdf5_readFilters40_U0_start_write; +wire tdf5_dot_product_U0_start_full_n; +wire tdf5_dot_product_U0_start_write; +wire tdf5_accum_1_U0_start_full_n; +wire tdf5_accum_1_U0_start_write; +wire tdf5_accum_2_U0_start_full_n; +wire tdf5_accum_2_U0_start_write; +wire Block_entry_proc_proc408_U0_start_full_n; +wire Block_entry_proc_proc408_U0_start_write; +wire tdf5_adjust_U0_start_full_n; +wire tdf5_adjust_U0_start_write; +wire tdf5_poolOutputs_U0_start_full_n; +wire tdf5_poolOutputs_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_sync_reg_channel_write_input_indices_1 = 1'b0; +#0 ap_sync_reg_channel_write_input_indices_0 = 1'b0; +#0 ap_sync_reg_tdf5_get_next_ijk_U0_ap_ready = 1'b0; +#0 ap_sync_reg_tdf5_readInputs41_U0_ap_ready = 1'b0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP37738_ifmap_vec #( + .DataWidth( 16 ), + .AddressRange( 144 ), + .AddressWidth( 8 )) +ifmap_vec_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf5_readInputs41_U0_ap_done), + .i_full_n(ifmap_vec_i_full_n), + .i_ce0(tdf5_readInputs41_U0_ifmap_vec_ce0), + .i_we0(tdf5_readInputs41_U0_ifmap_vec_we0), + .i_address0(tdf5_readInputs41_U0_ifmap_vec_address0), + .i_d0(tdf5_readInputs41_U0_ifmap_vec_d0), + .i_q0(ifmap_vec_i_q0), + .i_ce1(tdf5_readInputs41_U0_ifmap_vec_ce1), + .i_we1(tdf5_readInputs41_U0_ifmap_vec_we1), + .i_address1(tdf5_readInputs41_U0_ifmap_vec_address1), + .i_d1(tdf5_readInputs41_U0_ifmap_vec_d1), + .t_ce(1'b1), + .t_read(tdf5_dot_product_U0_ap_ready), + .t_empty_n(ifmap_vec_t_empty_n), + .t_ce0(tdf5_dot_product_U0_ifmap_vec_ce0), + .t_we0(1'b0), + .t_address0(tdf5_dot_product_U0_ifmap_vec_address0), + .t_d0(16'd0), + .t_q0(ifmap_vec_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(8'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37738_weight_vecs_0 #( + .DataWidth( 16 ), + .AddressRange( 144 ), + .AddressWidth( 8 )) +weight_vecs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf5_readFilters40_U0_ap_done), + .i_full_n(weight_vecs_0_i_full_n), + .i_ce0(tdf5_readFilters40_U0_weight_vecs_0_ce0), + .i_we0(tdf5_readFilters40_U0_weight_vecs_0_we0), + .i_address0(tdf5_readFilters40_U0_weight_vecs_0_address0), + .i_d0(tdf5_readFilters40_U0_weight_vecs_0_d0), + .i_q0(weight_vecs_0_i_q0), + .t_ce(1'b1), + .t_read(tdf5_dot_product_U0_ap_ready), + .t_empty_n(weight_vecs_0_t_empty_n), + .t_ce0(tdf5_dot_product_U0_weight_vecs_0_ce0), + .t_we0(1'b0), + .t_address0(tdf5_dot_product_U0_weight_vecs_0_address0), + .t_d0(16'd0), + .t_q0(weight_vecs_0_t_q0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37738_products_0 #( + .DataWidth( 16 ), + .AddressRange( 144 ), + .AddressWidth( 8 )) +products_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf5_dot_product_U0_ap_done), + .i_full_n(products_0_i_full_n), + .i_ce0(tdf5_dot_product_U0_products_0_ce0), + .i_we0(tdf5_dot_product_U0_products_0_we0), + .i_address0(tdf5_dot_product_U0_products_0_address0), + .i_d0(tdf5_dot_product_U0_products_0_d0), + .i_q0(products_0_i_q0), + .i_ce1(1'b0), + .i_address1(8'd0), + .i_q1(products_0_i_q1), + .t_ce(1'b1), + .t_read(tdf5_accum_1_U0_ap_ready), + .t_empty_n(products_0_t_empty_n), + .t_ce0(tdf5_accum_1_U0_accum_in_0_ce0), + .t_we0(1'b0), + .t_address0(tdf5_accum_1_U0_accum_in_0_address0), + .t_d0(16'd0), + .t_q0(products_0_t_q0), + .t_ce1(tdf5_accum_1_U0_accum_in_0_ce1), + .t_address1(tdf5_accum_1_U0_accum_in_0_address1), + .t_q1(products_0_t_q1) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37738_accum1_out_0 #( + .DataWidth( 16 ), + .AddressRange( 8 ), + .AddressWidth( 3 )) +accum1_out_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf5_accum_1_U0_ap_done), + .i_full_n(accum1_out_0_i_full_n), + .i_ce0(tdf5_accum_1_U0_accum_out_ce0), + .i_we0(tdf5_accum_1_U0_accum_out_we0), + .i_address0(tdf5_accum_1_U0_accum_out_address0), + .i_d0(tdf5_accum_1_U0_accum_out_d0), + .i_q0(accum1_out_0_i_q0), + .i_ce1(tdf5_accum_1_U0_accum_out_ce1), + .i_we1(tdf5_accum_1_U0_accum_out_we1), + .i_address1(tdf5_accum_1_U0_accum_out_address1), + .i_d1(tdf5_accum_1_U0_accum_out_d1), + .t_ce(1'b1), + .t_read(tdf5_accum_2_U0_ap_ready), + .t_empty_n(accum1_out_0_t_empty_n), + .t_ce0(tdf5_accum_2_U0_accum_in_ce0), + .t_we0(1'b0), + .t_address0(tdf5_accum_2_U0_accum_in_address0), + .t_d0(16'd0), + .t_q0(accum1_out_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(3'd0), + .t_d1(16'd0) +); + +td_fused_top_tdf5_get_next_ijk tdf5_get_next_ijk_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf5_get_next_ijk_U0_ap_start), + .start_full_n(start_for_tdf5_readFilters40_U0_full_n), + .ap_done(tdf5_get_next_ijk_U0_ap_done), + .ap_continue(tdf5_get_next_ijk_U0_ap_continue), + .ap_idle(tdf5_get_next_ijk_U0_ap_idle), + .ap_ready(tdf5_get_next_ijk_U0_ap_ready), + .start_out(tdf5_get_next_ijk_U0_start_out), + .start_write(tdf5_get_next_ijk_U0_start_write), + .input_indices_2_out_din(tdf5_get_next_ijk_U0_input_indices_2_out_din), + .input_indices_2_out_full_n(input_indices_23_c_full_n), + .input_indices_2_out_write(tdf5_get_next_ijk_U0_input_indices_2_out_write), + .input_indices_2_out1_din(tdf5_get_next_ijk_U0_input_indices_2_out1_din), + .input_indices_2_out1_full_n(input_indices_23_c1_full_n), + .input_indices_2_out1_write(tdf5_get_next_ijk_U0_input_indices_2_out1_write), + .output_indices_0_din(tdf5_get_next_ijk_U0_output_indices_0_din), + .output_indices_0_full_n(output_indices_04_c_full_n), + .output_indices_0_write(tdf5_get_next_ijk_U0_output_indices_0_write), + .output_indices_1_din(tdf5_get_next_ijk_U0_output_indices_1_din), + .output_indices_1_full_n(output_indices_15_c_full_n), + .output_indices_1_write(tdf5_get_next_ijk_U0_output_indices_1_write), + .resetMaximum_din(tdf5_get_next_ijk_U0_resetMaximum_din), + .resetMaximum_full_n(resetMaximum6_c_full_n), + .resetMaximum_write(tdf5_get_next_ijk_U0_resetMaximum_write), + .storeOutput_din(tdf5_get_next_ijk_U0_storeOutput_din), + .storeOutput_full_n(storeOutput7_c_full_n), + .storeOutput_write(tdf5_get_next_ijk_U0_storeOutput_write), + .ap_return_0(tdf5_get_next_ijk_U0_ap_return_0), + .ap_return_1(tdf5_get_next_ijk_U0_ap_return_1) +); + +td_fused_top_tdf5_readInputs41 tdf5_readInputs41_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf5_readInputs41_U0_ap_start), + .ap_done(tdf5_readInputs41_U0_ap_done), + .ap_continue(tdf5_readInputs41_U0_ap_continue), + .ap_idle(tdf5_readInputs41_U0_ap_idle), + .ap_ready(tdf5_readInputs41_U0_ap_ready), + .in_data_address0(tdf5_readInputs41_U0_in_data_address0), + .in_data_ce0(tdf5_readInputs41_U0_in_data_ce0), + .in_data_q0(in_data_q0), + .i_15(input_indices_0_dout), + .j_15(input_indices_1_dout), + .ifmap_vec_address0(tdf5_readInputs41_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf5_readInputs41_U0_ifmap_vec_ce0), + .ifmap_vec_we0(tdf5_readInputs41_U0_ifmap_vec_we0), + .ifmap_vec_d0(tdf5_readInputs41_U0_ifmap_vec_d0), + .ifmap_vec_address1(tdf5_readInputs41_U0_ifmap_vec_address1), + .ifmap_vec_ce1(tdf5_readInputs41_U0_ifmap_vec_ce1), + .ifmap_vec_we1(tdf5_readInputs41_U0_ifmap_vec_we1), + .ifmap_vec_d1(tdf5_readInputs41_U0_ifmap_vec_d1) +); + +td_fused_top_tdf5_readFilters40 tdf5_readFilters40_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf5_readFilters40_U0_ap_start), + .ap_done(tdf5_readFilters40_U0_ap_done), + .ap_continue(tdf5_readFilters40_U0_ap_continue), + .ap_idle(tdf5_readFilters40_U0_ap_idle), + .ap_ready(tdf5_readFilters40_U0_ap_ready), + .filter_data_address0(tdf5_readFilters40_U0_filter_data_address0), + .filter_data_ce0(tdf5_readFilters40_U0_filter_data_ce0), + .filter_data_q0(filter_data_q0), + .input_indices_23_dout(input_indices_23_c_dout), + .input_indices_23_empty_n(input_indices_23_c_empty_n), + .input_indices_23_read(tdf5_readFilters40_U0_input_indices_23_read), + .weight_vecs_0_address0(tdf5_readFilters40_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf5_readFilters40_U0_weight_vecs_0_ce0), + .weight_vecs_0_we0(tdf5_readFilters40_U0_weight_vecs_0_we0), + .weight_vecs_0_d0(tdf5_readFilters40_U0_weight_vecs_0_d0) +); + +td_fused_top_tdf5_dot_product tdf5_dot_product_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf5_dot_product_U0_ap_start), + .ap_done(tdf5_dot_product_U0_ap_done), + .ap_continue(tdf5_dot_product_U0_ap_continue), + .ap_idle(tdf5_dot_product_U0_ap_idle), + .ap_ready(tdf5_dot_product_U0_ap_ready), + .ifmap_vec_address0(tdf5_dot_product_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf5_dot_product_U0_ifmap_vec_ce0), + .ifmap_vec_q0(ifmap_vec_t_q0), + .weight_vecs_0_address0(tdf5_dot_product_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf5_dot_product_U0_weight_vecs_0_ce0), + .weight_vecs_0_q0(weight_vecs_0_t_q0), + .products_0_address0(tdf5_dot_product_U0_products_0_address0), + .products_0_ce0(tdf5_dot_product_U0_products_0_ce0), + .products_0_we0(tdf5_dot_product_U0_products_0_we0), + .products_0_d0(tdf5_dot_product_U0_products_0_d0) +); + +td_fused_top_tdf5_accum_1 tdf5_accum_1_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf5_accum_1_U0_ap_start), + .ap_done(tdf5_accum_1_U0_ap_done), + .ap_continue(tdf5_accum_1_U0_ap_continue), + .ap_idle(tdf5_accum_1_U0_ap_idle), + .ap_ready(tdf5_accum_1_U0_ap_ready), + .accum_in_0_address0(tdf5_accum_1_U0_accum_in_0_address0), + .accum_in_0_ce0(tdf5_accum_1_U0_accum_in_0_ce0), + .accum_in_0_q0(products_0_t_q0), + .accum_in_0_address1(tdf5_accum_1_U0_accum_in_0_address1), + .accum_in_0_ce1(tdf5_accum_1_U0_accum_in_0_ce1), + .accum_in_0_q1(products_0_t_q1), + .accum_out_address0(tdf5_accum_1_U0_accum_out_address0), + .accum_out_ce0(tdf5_accum_1_U0_accum_out_ce0), + .accum_out_we0(tdf5_accum_1_U0_accum_out_we0), + .accum_out_d0(tdf5_accum_1_U0_accum_out_d0), + .accum_out_address1(tdf5_accum_1_U0_accum_out_address1), + .accum_out_ce1(tdf5_accum_1_U0_accum_out_ce1), + .accum_out_we1(tdf5_accum_1_U0_accum_out_we1), + .accum_out_d1(tdf5_accum_1_U0_accum_out_d1) +); + +td_fused_top_tdf5_accum_2 tdf5_accum_2_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf5_accum_2_U0_ap_start), + .ap_done(tdf5_accum_2_U0_ap_done), + .ap_continue(tdf5_accum_2_U0_ap_continue), + .ap_idle(tdf5_accum_2_U0_ap_idle), + .ap_ready(tdf5_accum_2_U0_ap_ready), + .accum_in_10(tdf5_accum_2_U0_accum_in_10), + .accum_in_10_ap_vld(tdf5_accum_2_U0_accum_in_10_ap_vld), + .accum_in_address0(tdf5_accum_2_U0_accum_in_address0), + .accum_in_ce0(tdf5_accum_2_U0_accum_in_ce0), + .accum_in_q0(accum1_out_0_t_q0) +); + +td_fused_top_Block_entry_proc_proc408 Block_entry_proc_proc408_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(Block_entry_proc_proc408_U0_ap_start), + .ap_done(Block_entry_proc_proc408_U0_ap_done), + .ap_continue(Block_entry_proc_proc408_U0_ap_continue), + .ap_idle(Block_entry_proc_proc408_U0_ap_idle), + .ap_ready(Block_entry_proc_proc408_U0_ap_ready), + .tmp(tmp_channel_dout), + .ap_return(Block_entry_proc_proc408_U0_ap_return) +); + +td_fused_top_tdf5_adjust tdf5_adjust_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf5_adjust_U0_ap_start), + .ap_done(tdf5_adjust_U0_ap_done), + .ap_continue(tdf5_adjust_U0_ap_continue), + .ap_idle(tdf5_adjust_U0_ap_idle), + .ap_ready(tdf5_adjust_U0_ap_ready), + .sums_read(sums_0_dout), + .adjustments_address0(tdf5_adjust_U0_adjustments_address0), + .adjustments_ce0(tdf5_adjust_U0_adjustments_ce0), + .adjustments_q0(adjustments_q0), + .input_indices_23_dout(input_indices_23_c1_dout), + .input_indices_23_empty_n(input_indices_23_c1_empty_n), + .input_indices_23_read(tdf5_adjust_U0_input_indices_23_read), + .ap_return(tdf5_adjust_U0_ap_return) +); + +td_fused_top_tdf5_poolOutputs tdf5_poolOutputs_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf5_poolOutputs_U0_ap_start), + .ap_done(tdf5_poolOutputs_U0_ap_done), + .ap_continue(tdf5_poolOutputs_U0_ap_continue), + .ap_idle(tdf5_poolOutputs_U0_ap_idle), + .ap_ready(tdf5_poolOutputs_U0_ap_ready), + .output_indices_04_dout(output_indices_04_c_dout), + .output_indices_04_empty_n(output_indices_04_c_empty_n), + .output_indices_04_read(tdf5_poolOutputs_U0_output_indices_04_read), + .output_indices_15_dout(output_indices_15_c_dout), + .output_indices_15_empty_n(output_indices_15_c_empty_n), + .output_indices_15_read(tdf5_poolOutputs_U0_output_indices_15_read), + .resetMaximum6_dout(resetMaximum6_c_dout), + .resetMaximum6_empty_n(resetMaximum6_c_empty_n), + .resetMaximum6_read(tdf5_poolOutputs_U0_resetMaximum6_read), + .storeOutput7_dout(storeOutput7_c_dout), + .storeOutput7_empty_n(storeOutput7_c_empty_n), + .storeOutput7_read(tdf5_poolOutputs_U0_storeOutput7_read), + .p_read(outputs_0_dout), + .out_data_address1(tdf5_poolOutputs_U0_out_data_address1), + .out_data_ce1(tdf5_poolOutputs_U0_out_data_ce1), + .out_data_we1(tdf5_poolOutputs_U0_out_data_we1), + .out_data_d1(tdf5_poolOutputs_U0_out_data_d1) +); + +td_fused_top_fifo_w7_d2_S_x input_indices_23_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_23_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf5_readFilters40_U0_input_indices_23_read), + .if_dout(input_indices_23_c_dout), + .if_full_n(input_indices_23_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf5_get_next_ijk_U0_input_indices_2_out_write), + .if_din(tdf5_get_next_ijk_U0_input_indices_2_out_din) +); + +td_fused_top_fifo_w7_d7_S input_indices_23_c1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_23_c1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf5_adjust_U0_input_indices_23_read), + .if_dout(input_indices_23_c1_dout), + .if_full_n(input_indices_23_c1_full_n), + .if_write_ce(1'b1), + .if_write(tdf5_get_next_ijk_U0_input_indices_2_out1_write), + .if_din(tdf5_get_next_ijk_U0_input_indices_2_out1_din) +); + +td_fused_top_fifo_w5_d8_S output_indices_04_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(output_indices_04_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf5_poolOutputs_U0_output_indices_04_read), + .if_dout(output_indices_04_c_dout), + .if_full_n(output_indices_04_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf5_get_next_ijk_U0_output_indices_0_write), + .if_din(tdf5_get_next_ijk_U0_output_indices_0_din) +); + +td_fused_top_fifo_w10_d8_S output_indices_15_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(output_indices_15_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf5_poolOutputs_U0_output_indices_15_read), + .if_dout(output_indices_15_c_dout), + .if_full_n(output_indices_15_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf5_get_next_ijk_U0_output_indices_1_write), + .if_din(tdf5_get_next_ijk_U0_output_indices_1_din) +); + +td_fused_top_fifo_w1_d8_S_x resetMaximum6_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(resetMaximum6_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf5_poolOutputs_U0_resetMaximum6_read), + .if_dout(resetMaximum6_c_dout), + .if_full_n(resetMaximum6_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf5_get_next_ijk_U0_resetMaximum_write), + .if_din(resetMaximum6_c_din) +); + +td_fused_top_fifo_w1_d8_S_x storeOutput7_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(storeOutput7_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf5_poolOutputs_U0_storeOutput7_read), + .if_dout(storeOutput7_c_dout), + .if_full_n(storeOutput7_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf5_get_next_ijk_U0_storeOutput_write), + .if_din(storeOutput7_c_din) +); + +td_fused_top_fifo_w16_d2_S_x2 input_indices_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf5_readInputs41_U0_ap_ready), + .if_dout(input_indices_0_dout), + .if_full_n(input_indices_0_full_n), + .if_write_ce(1'b1), + .if_write(ap_channel_done_input_indices_0), + .if_din(tdf5_get_next_ijk_U0_ap_return_0) +); + +td_fused_top_fifo_w16_d2_S_x2 input_indices_1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf5_readInputs41_U0_ap_ready), + .if_dout(input_indices_1_dout), + .if_full_n(input_indices_1_full_n), + .if_write_ce(1'b1), + .if_write(ap_channel_done_input_indices_1), + .if_din(tdf5_get_next_ijk_U0_ap_return_1) +); + +td_fused_top_fifo_w16_d2_S_x2 tmp_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(tmp_channel_empty_n), + .if_read_ce(1'b1), + .if_read(Block_entry_proc_proc408_U0_ap_ready), + .if_dout(tmp_channel_dout), + .if_full_n(tmp_channel_full_n), + .if_write_ce(1'b1), + .if_write(tdf5_accum_2_U0_ap_done), + .if_din(tdf5_accum_2_U0_accum_in_10) +); + +td_fused_top_fifo_w16_d2_S_x2 sums_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(sums_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf5_adjust_U0_ap_ready), + .if_dout(sums_0_dout), + .if_full_n(sums_0_full_n), + .if_write_ce(1'b1), + .if_write(Block_entry_proc_proc408_U0_ap_done), + .if_din(Block_entry_proc_proc408_U0_ap_return) +); + +td_fused_top_fifo_w16_d2_S_x2 outputs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(outputs_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf5_poolOutputs_U0_ap_ready), + .if_dout(outputs_0_dout), + .if_full_n(outputs_0_full_n), + .if_write_ce(1'b1), + .if_write(tdf5_adjust_U0_ap_done), + .if_din(tdf5_adjust_U0_ap_return) +); + +td_fused_top_start_for_tdf5_readFilters40_U0 start_for_tdf5_readFilters40_U0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(start_for_tdf5_readFilters40_U0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf5_readFilters40_U0_ap_ready), + .if_dout(start_for_tdf5_readFilters40_U0_dout), + .if_full_n(start_for_tdf5_readFilters40_U0_full_n), + .if_write_ce(1'b1), + .if_write(tdf5_get_next_ijk_U0_start_write), + .if_din(start_for_tdf5_readFilters40_U0_din) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_input_indices_0 <= 1'b0; + end else begin + if (((tdf5_get_next_ijk_U0_ap_done & tdf5_get_next_ijk_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_input_indices_0 <= 1'b0; + end else begin + ap_sync_reg_channel_write_input_indices_0 <= ap_sync_channel_write_input_indices_0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_input_indices_1 <= 1'b0; + end else begin + if (((tdf5_get_next_ijk_U0_ap_done & tdf5_get_next_ijk_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_input_indices_1 <= 1'b0; + end else begin + ap_sync_reg_channel_write_input_indices_1 <= ap_sync_channel_write_input_indices_1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf5_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf5_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf5_get_next_ijk_U0_ap_ready <= ap_sync_tdf5_get_next_ijk_U0_ap_ready; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf5_readInputs41_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf5_readInputs41_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf5_readInputs41_U0_ap_ready <= ap_sync_tdf5_readInputs41_U0_ap_ready; + end + end +end + +assign Block_entry_proc_proc408_U0_ap_continue = sums_0_full_n; + +assign Block_entry_proc_proc408_U0_ap_start = tmp_channel_empty_n; + +assign Block_entry_proc_proc408_U0_start_full_n = 1'b1; + +assign Block_entry_proc_proc408_U0_start_write = 1'b0; + +assign adjustments_address0 = tdf5_adjust_U0_adjustments_address0; + +assign adjustments_address1 = 7'd0; + +assign adjustments_ce0 = tdf5_adjust_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_channel_done_accum1_out_0 = tdf5_accum_1_U0_ap_done; + +assign ap_channel_done_ifmap_vec = tdf5_readInputs41_U0_ap_done; + +assign ap_channel_done_input_indices_0 = (tdf5_get_next_ijk_U0_ap_done & (ap_sync_reg_channel_write_input_indices_0 ^ 1'b1)); + +assign ap_channel_done_input_indices_1 = (tdf5_get_next_ijk_U0_ap_done & (ap_sync_reg_channel_write_input_indices_1 ^ 1'b1)); + +assign ap_channel_done_outputs_0 = tdf5_adjust_U0_ap_done; + +assign ap_channel_done_products_0 = tdf5_dot_product_U0_ap_done; + +assign ap_channel_done_sums_0 = Block_entry_proc_proc408_U0_ap_done; + +assign ap_channel_done_tmp_channel = tdf5_accum_2_U0_ap_done; + +assign ap_channel_done_weight_vecs_0 = tdf5_readFilters40_U0_ap_done; + +assign ap_done = tdf5_poolOutputs_U0_ap_done; + +assign ap_idle = (tdf5_readInputs41_U0_ap_idle & tdf5_readFilters40_U0_ap_idle & tdf5_poolOutputs_U0_ap_idle & tdf5_get_next_ijk_U0_ap_idle & tdf5_dot_product_U0_ap_idle & tdf5_adjust_U0_ap_idle & tdf5_accum_2_U0_ap_idle & tdf5_accum_1_U0_ap_idle & (outputs_0_empty_n ^ 1'b1) & (sums_0_empty_n ^ 1'b1) & (tmp_channel_empty_n ^ 1'b1) & (input_indices_1_empty_n ^ 1'b1) & (input_indices_0_empty_n ^ 1'b1) & (products_0_t_empty_n ^ 1'b1) & (weight_vecs_0_t_empty_n ^ 1'b1) & (ifmap_vec_t_empty_n ^ 1'b1) & (1'b1 ^ accum1_out_0_t_empty_n) & Block_entry_proc_proc408_U0_ap_idle); + +assign ap_ready = ap_sync_ready; + +assign ap_sync_channel_write_input_indices_0 = ((input_indices_0_full_n & ap_channel_done_input_indices_0) | ap_sync_reg_channel_write_input_indices_0); + +assign ap_sync_channel_write_input_indices_1 = ((input_indices_1_full_n & ap_channel_done_input_indices_1) | ap_sync_reg_channel_write_input_indices_1); + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = tdf5_poolOutputs_U0_ap_done; + +assign ap_sync_ready = (ap_sync_tdf5_readInputs41_U0_ap_ready & ap_sync_tdf5_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf5_get_next_ijk_U0_ap_ready = (tdf5_get_next_ijk_U0_ap_ready | ap_sync_reg_tdf5_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf5_readInputs41_U0_ap_ready = (tdf5_readInputs41_U0_ap_ready | ap_sync_reg_tdf5_readInputs41_U0_ap_ready); + +assign filter_data_address0 = tdf5_readFilters40_U0_filter_data_address0; + +assign filter_data_address1 = 15'd0; + +assign filter_data_ce0 = tdf5_readFilters40_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = tdf5_readInputs41_U0_in_data_address0; + +assign in_data_address1 = 14'd0; + +assign in_data_ce0 = tdf5_readInputs41_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = tdf5_readInputs41_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 15'd0; + +assign out_data_address1 = tdf5_poolOutputs_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = tdf5_poolOutputs_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = tdf5_poolOutputs_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = tdf5_poolOutputs_U0_out_data_we1; + +assign out_data_write = tdf5_poolOutputs_U0_out_data_write; + +assign products_0_t_d1 = 16'd0; + +assign products_0_t_we1 = 1'b0; + +assign resetMaximum6_c_din = tdf5_get_next_ijk_U0_resetMaximum_din; + +assign start_for_tdf5_readFilters40_U0_din = 1'b1; + +assign storeOutput7_c_din = tdf5_get_next_ijk_U0_storeOutput_din; + +assign tdf5_accum_1_U0_accum_out_full_n = accum1_out_0_i_full_n; + +assign tdf5_accum_1_U0_ap_continue = accum1_out_0_i_full_n; + +assign tdf5_accum_1_U0_ap_start = products_0_t_empty_n; + +assign tdf5_accum_1_U0_start_full_n = 1'b1; + +assign tdf5_accum_1_U0_start_write = 1'b0; + +assign tdf5_accum_2_U0_ap_continue = tmp_channel_full_n; + +assign tdf5_accum_2_U0_ap_start = accum1_out_0_t_empty_n; + +assign tdf5_accum_2_U0_start_full_n = 1'b1; + +assign tdf5_accum_2_U0_start_write = 1'b0; + +assign tdf5_adjust_U0_ap_continue = outputs_0_full_n; + +assign tdf5_adjust_U0_ap_start = sums_0_empty_n; + +assign tdf5_adjust_U0_start_full_n = 1'b1; + +assign tdf5_adjust_U0_start_write = 1'b0; + +assign tdf5_dot_product_U0_ap_continue = products_0_i_full_n; + +assign tdf5_dot_product_U0_ap_start = (weight_vecs_0_t_empty_n & ifmap_vec_t_empty_n); + +assign tdf5_dot_product_U0_products_0_full_n = products_0_i_full_n; + +assign tdf5_dot_product_U0_start_full_n = 1'b1; + +assign tdf5_dot_product_U0_start_write = 1'b0; + +assign tdf5_get_next_ijk_U0_ap_continue = (ap_sync_channel_write_input_indices_1 & ap_sync_channel_write_input_indices_0); + +assign tdf5_get_next_ijk_U0_ap_start = ((ap_sync_reg_tdf5_get_next_ijk_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf5_poolOutputs_U0_ap_continue = ap_continue; + +assign tdf5_poolOutputs_U0_ap_start = outputs_0_empty_n; + +assign tdf5_poolOutputs_U0_out_data_full_n = out_data_full_n; + +assign tdf5_poolOutputs_U0_out_data_write = 1'b0; + +assign tdf5_poolOutputs_U0_start_full_n = 1'b1; + +assign tdf5_poolOutputs_U0_start_write = 1'b0; + +assign tdf5_readFilters40_U0_ap_continue = weight_vecs_0_i_full_n; + +assign tdf5_readFilters40_U0_ap_start = start_for_tdf5_readFilters40_U0_empty_n; + +assign tdf5_readFilters40_U0_start_full_n = 1'b1; + +assign tdf5_readFilters40_U0_start_write = 1'b0; + +assign tdf5_readFilters40_U0_weight_vecs_0_full_n = weight_vecs_0_i_full_n; + +assign tdf5_readInputs41_U0_ap_continue = ifmap_vec_i_full_n; + +assign tdf5_readInputs41_U0_ap_start = (input_indices_1_empty_n & input_indices_0_empty_n & (ap_sync_reg_tdf5_readInputs41_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf5_readInputs41_U0_ifmap_vec_full_n = ifmap_vec_i_full_n; + +assign tdf5_readInputs41_U0_in_data_full_n = in_data_empty_n; + +assign tdf5_readInputs41_U0_in_data_write = 1'b0; + +assign tdf5_readInputs41_U0_start_full_n = 1'b1; + +assign tdf5_readInputs41_U0_start_write = 1'b0; + +endmodule //td_fused_top_dataflow_in_loop_TOP_LOOP37738 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37738_weight_vecs_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 9; +parameter MEM_SIZE = 288; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37738_weight_vecs_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd288; +parameter AddressWidth = 32'd9; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37738_weight_vecs_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37738_weight_vecs_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37738_weight_vecs_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 8, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP37738_weight_vecs_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37738_weight_vecs_0_memcore_U ( + .reset ( reset ), + .clk ( clk ), + .address0 ( memcore_iaddr ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + .address1 ( memcore_taddr ), + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .d1 ( t_d0 ), + .q1 ( t_q0 ) + +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37832_accum1_out_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 3; +parameter MEM_SIZE = 8; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37832_accum1_out_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd8; +parameter AddressWidth = 32'd3; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37832_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37832_accum1_out_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37832_accum1_out_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 3, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37832_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37832_accum1_out_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37832_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37832_accum1_out_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37832_ifmap_vec_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 8; +parameter MEM_SIZE = 144; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37832_ifmap_vec_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd144; +parameter AddressWidth = 32'd8; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37832_ifmap_vec_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37832_ifmap_vec_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37832_ifmap_vec +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 8, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37832_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37832_ifmap_vec_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37832_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37832_ifmap_vec_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37832_l2_products_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 5; +parameter MEM_SIZE = 32; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37832_l2_products_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd32; +parameter AddressWidth = 32'd5; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37832_l2_products_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37832_l2_products_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37832_l2_products +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 4, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP37832_l2_products_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37832_l2_products_memcore_U ( + .reset ( reset ), + .clk ( clk ), + .address0 ( memcore_iaddr ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + .address1 ( memcore_taddr ), + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .d1 ( t_d0 ), + .q1 ( t_q0 ) + +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37832_products_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 8; +parameter MEM_SIZE = 144; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37832_products_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd144; +parameter AddressWidth = 32'd8; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37832_products_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37832_products_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37832_products_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 8, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire [AddressWidth-1:0] i_address1, + output wire [DataWidth-1:0] i_q1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire [AddressWidth-1:0] t_address1, + output wire [DataWidth-1:0] t_q1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_q1_0, buf_q1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37832_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37832_products_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .q1 ( buf_q1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37832_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37832_products_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .q1 ( buf_q1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign i_q1 = (prev_iptr == 1'b1 ? buf_q1_1 : buf_q1_0); +assign t_q1 = reg_valid1 ? reg_q1 : (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// reg_q1 and reg_valid1 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q1 <= 1'b0; + reg_valid1 <= 1'b0; + end else if (!t_ce1 && !reg_valid1) begin + reg_q1 <= (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + reg_valid1 <= 1'b1; + end else if (t_ce1) begin + reg_valid1 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37832 ( + ap_clk, + ap_rst, + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + l1_filter_data_address0, + l1_filter_data_ce0, + l1_filter_data_d0, + l1_filter_data_q0, + l1_filter_data_we0, + l1_filter_data_address1, + l1_filter_data_ce1, + l1_filter_data_d1, + l1_filter_data_q1, + l1_filter_data_we1, + l1_adjustments_address0, + l1_adjustments_ce0, + l1_adjustments_d0, + l1_adjustments_q0, + l1_adjustments_we0, + l1_adjustments_address1, + l1_adjustments_ce1, + l1_adjustments_d1, + l1_adjustments_q1, + l1_adjustments_we1, + l2_filter_data_address0, + l2_filter_data_ce0, + l2_filter_data_d0, + l2_filter_data_q0, + l2_filter_data_we0, + l2_filter_data_address1, + l2_filter_data_ce1, + l2_filter_data_d1, + l2_filter_data_q1, + l2_filter_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_d0, + l2_adjustments_q0, + l2_adjustments_we0, + l2_adjustments_address1, + l2_adjustments_ce1, + l2_adjustments_d1, + l2_adjustments_q1, + l2_adjustments_we1, + ap_start, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +input ap_clk; +input ap_rst; +output [13:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [13:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [14:0] l1_filter_data_address0; +output l1_filter_data_ce0; +output [15:0] l1_filter_data_d0; +input [15:0] l1_filter_data_q0; +output l1_filter_data_we0; +output [14:0] l1_filter_data_address1; +output l1_filter_data_ce1; +output [15:0] l1_filter_data_d1; +input [15:0] l1_filter_data_q1; +output l1_filter_data_we1; +output [6:0] l1_adjustments_address0; +output l1_adjustments_ce0; +output [47:0] l1_adjustments_d0; +input [47:0] l1_adjustments_q0; +output l1_adjustments_we0; +output [6:0] l1_adjustments_address1; +output l1_adjustments_ce1; +output [47:0] l1_adjustments_d1; +input [47:0] l1_adjustments_q1; +output l1_adjustments_we1; +output [10:0] l2_filter_data_address0; +output l2_filter_data_ce0; +output [15:0] l2_filter_data_d0; +input [15:0] l2_filter_data_q0; +output l2_filter_data_we0; +output [10:0] l2_filter_data_address1; +output l2_filter_data_ce1; +output [15:0] l2_filter_data_d1; +input [15:0] l2_filter_data_q1; +output l2_filter_data_we1; +output [13:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [13:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [3:0] l2_adjustments_address0; +output l2_adjustments_ce0; +output [47:0] l2_adjustments_d0; +input [47:0] l2_adjustments_q0; +output l2_adjustments_we0; +output [3:0] l2_adjustments_address1; +output l2_adjustments_ce1; +output [47:0] l2_adjustments_d1; +input [47:0] l2_adjustments_q1; +output l2_adjustments_we1; +input ap_start; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +wire [15:0] ifmap_vec_i_q0; +wire [15:0] ifmap_vec_t_q0; +wire [15:0] weight_vecs_0_i_q0; +wire [15:0] weight_vecs_0_t_q0; +wire [15:0] products_0_i_q0; +wire [15:0] products_0_i_q1; +wire [15:0] products_0_t_q0; +wire [15:0] products_0_t_q1; +wire [15:0] accum1_out_0_i_q0; +wire [15:0] accum1_out_0_t_q0; +wire [15:0] l2_products_i_q0; +wire [15:0] l2_products_t_q0; +wire tdf4_get_next_ijk_U0_ap_start; +wire tdf4_get_next_ijk_U0_ap_done; +wire tdf4_get_next_ijk_U0_ap_continue; +wire tdf4_get_next_ijk_U0_ap_idle; +wire tdf4_get_next_ijk_U0_ap_ready; +wire tdf4_get_next_ijk_U0_start_out; +wire tdf4_get_next_ijk_U0_start_write; +wire [15:0] tdf4_get_next_ijk_U0_indices_0_din; +wire tdf4_get_next_ijk_U0_indices_0_write; +wire [15:0] tdf4_get_next_ijk_U0_indices_1_din; +wire tdf4_get_next_ijk_U0_indices_1_write; +wire [6:0] tdf4_get_next_ijk_U0_indices_2_out_din; +wire tdf4_get_next_ijk_U0_indices_2_out_write; +wire [10:0] tdf4_get_next_ijk_U0_indices_2_out1_din; +wire tdf4_get_next_ijk_U0_indices_2_out1_write; +wire tdf4_get_next_ijk_U0_write_r_din; +wire tdf4_get_next_ijk_U0_write_r_write; +wire tdf4_readInputs37_U0_ap_start; +wire tdf4_readInputs37_U0_ap_done; +wire tdf4_readInputs37_U0_ap_continue; +wire tdf4_readInputs37_U0_ap_idle; +wire tdf4_readInputs37_U0_ap_ready; +wire [13:0] tdf4_readInputs37_U0_in_data_address0; +wire tdf4_readInputs37_U0_in_data_ce0; +wire tdf4_readInputs37_U0_indices_01_read; +wire tdf4_readInputs37_U0_indices_12_read; +wire [7:0] tdf4_readInputs37_U0_ifmap_vec_address0; +wire tdf4_readInputs37_U0_ifmap_vec_ce0; +wire tdf4_readInputs37_U0_ifmap_vec_we0; +wire [15:0] tdf4_readInputs37_U0_ifmap_vec_d0; +wire [7:0] tdf4_readInputs37_U0_ifmap_vec_address1; +wire tdf4_readInputs37_U0_ifmap_vec_ce1; +wire tdf4_readInputs37_U0_ifmap_vec_we1; +wire [15:0] tdf4_readInputs37_U0_ifmap_vec_d1; +wire [5:0] tdf4_readInputs37_U0_indices_01_out_din; +wire tdf4_readInputs37_U0_indices_01_out_write; +wire [11:0] tdf4_readInputs37_U0_indices_12_out_din; +wire tdf4_readInputs37_U0_indices_12_out_write; +wire tdf4_readInputs37_U0_in_data_full_n; +wire tdf4_readInputs37_U0_in_data_write; +wire ap_channel_done_ifmap_vec; +wire tdf4_readInputs37_U0_ifmap_vec_full_n; +wire tdf4_readFilters36_U0_ap_start; +wire tdf4_readFilters36_U0_ap_done; +wire tdf4_readFilters36_U0_ap_continue; +wire tdf4_readFilters36_U0_ap_idle; +wire tdf4_readFilters36_U0_ap_ready; +wire [14:0] tdf4_readFilters36_U0_filter_data_address0; +wire tdf4_readFilters36_U0_filter_data_ce0; +wire tdf4_readFilters36_U0_indices_23_read; +wire [7:0] tdf4_readFilters36_U0_weight_vecs_0_address0; +wire tdf4_readFilters36_U0_weight_vecs_0_ce0; +wire tdf4_readFilters36_U0_weight_vecs_0_we0; +wire [15:0] tdf4_readFilters36_U0_weight_vecs_0_d0; +wire ap_channel_done_weight_vecs_0; +wire tdf4_readFilters36_U0_weight_vecs_0_full_n; +wire tdf4_dot_product_U0_ap_start; +wire tdf4_dot_product_U0_ap_done; +wire tdf4_dot_product_U0_ap_continue; +wire tdf4_dot_product_U0_ap_idle; +wire tdf4_dot_product_U0_ap_ready; +wire [7:0] tdf4_dot_product_U0_ifmap_vec_address0; +wire tdf4_dot_product_U0_ifmap_vec_ce0; +wire [7:0] tdf4_dot_product_U0_weight_vecs_0_address0; +wire tdf4_dot_product_U0_weight_vecs_0_ce0; +wire [7:0] tdf4_dot_product_U0_products_0_address0; +wire tdf4_dot_product_U0_products_0_ce0; +wire tdf4_dot_product_U0_products_0_we0; +wire [15:0] tdf4_dot_product_U0_products_0_d0; +wire ap_channel_done_products_0; +wire tdf4_dot_product_U0_products_0_full_n; +wire tdf4_accum_1_U0_ap_start; +wire tdf4_accum_1_U0_ap_done; +wire tdf4_accum_1_U0_ap_continue; +wire tdf4_accum_1_U0_ap_idle; +wire tdf4_accum_1_U0_ap_ready; +wire [7:0] tdf4_accum_1_U0_accum_in_0_address0; +wire tdf4_accum_1_U0_accum_in_0_ce0; +wire [7:0] tdf4_accum_1_U0_accum_in_0_address1; +wire tdf4_accum_1_U0_accum_in_0_ce1; +wire [2:0] tdf4_accum_1_U0_accum_out_address0; +wire tdf4_accum_1_U0_accum_out_ce0; +wire tdf4_accum_1_U0_accum_out_we0; +wire [15:0] tdf4_accum_1_U0_accum_out_d0; +wire [2:0] tdf4_accum_1_U0_accum_out_address1; +wire tdf4_accum_1_U0_accum_out_ce1; +wire tdf4_accum_1_U0_accum_out_we1; +wire [15:0] tdf4_accum_1_U0_accum_out_d1; +wire ap_channel_done_accum1_out_0; +wire tdf4_accum_1_U0_accum_out_full_n; +wire tdf4_accum_2_U0_ap_start; +wire tdf4_accum_2_U0_ap_done; +wire tdf4_accum_2_U0_ap_continue; +wire tdf4_accum_2_U0_ap_idle; +wire tdf4_accum_2_U0_ap_ready; +wire [15:0] tdf4_accum_2_U0_accum_in_12; +wire tdf4_accum_2_U0_accum_in_12_ap_vld; +wire [2:0] tdf4_accum_2_U0_accum_in_address0; +wire tdf4_accum_2_U0_accum_in_ce0; +wire ap_channel_done_tmp_channel; +wire tmp_channel_full_n; +wire Block_entry_proc_proc403_U0_ap_start; +wire Block_entry_proc_proc403_U0_ap_done; +wire Block_entry_proc_proc403_U0_ap_continue; +wire Block_entry_proc_proc403_U0_ap_idle; +wire Block_entry_proc_proc403_U0_ap_ready; +wire [15:0] Block_entry_proc_proc403_U0_ap_return; +wire ap_channel_done_sums_0; +wire sums_0_full_n; +wire tdf4_adjust_U0_ap_start; +wire tdf4_adjust_U0_ap_done; +wire tdf4_adjust_U0_ap_continue; +wire tdf4_adjust_U0_ap_idle; +wire tdf4_adjust_U0_ap_ready; +wire [6:0] tdf4_adjust_U0_adjustments_address0; +wire tdf4_adjust_U0_adjustments_ce0; +wire tdf4_adjust_U0_indices_23_read; +wire [10:0] tdf4_adjust_U0_indices_23_out_din; +wire tdf4_adjust_U0_indices_23_out_write; +wire [15:0] tdf4_adjust_U0_ap_return; +wire ap_channel_done_intermediate_fmaps_0; +wire intermediate_fmaps_0_full_n; +wire tdf4_l2_multiply34_U0_ap_start; +wire tdf4_l2_multiply34_U0_ap_done; +wire tdf4_l2_multiply34_U0_ap_continue; +wire tdf4_l2_multiply34_U0_ap_idle; +wire tdf4_l2_multiply34_U0_ap_ready; +wire [10:0] tdf4_l2_multiply34_U0_l2_filter_data_address0; +wire tdf4_l2_multiply34_U0_l2_filter_data_ce0; +wire [3:0] tdf4_l2_multiply34_U0_l2_products_address0; +wire tdf4_l2_multiply34_U0_l2_products_ce0; +wire tdf4_l2_multiply34_U0_l2_products_we0; +wire [15:0] tdf4_l2_multiply34_U0_l2_products_d0; +wire tdf4_l2_multiply34_U0_indices_23_read; +wire ap_channel_done_l2_products; +wire tdf4_l2_multiply34_U0_l2_products_full_n; +wire tdf4_l2_writeOutputs_133_U0_ap_start; +wire tdf4_l2_writeOutputs_133_U0_ap_done; +wire tdf4_l2_writeOutputs_133_U0_ap_continue; +wire tdf4_l2_writeOutputs_133_U0_ap_idle; +wire tdf4_l2_writeOutputs_133_U0_ap_ready; +wire tdf4_l2_writeOutputs_133_U0_indices_01_read; +wire tdf4_l2_writeOutputs_133_U0_indices_12_read; +wire tdf4_l2_writeOutputs_133_U0_write4_read; +wire [3:0] tdf4_l2_writeOutputs_133_U0_l2_partial_sums_address0; +wire tdf4_l2_writeOutputs_133_U0_l2_partial_sums_ce0; +wire [13:0] tdf4_l2_writeOutputs_133_U0_out_data_address1; +wire tdf4_l2_writeOutputs_133_U0_out_data_ce1; +wire tdf4_l2_writeOutputs_133_U0_out_data_we1; +wire [63:0] tdf4_l2_writeOutputs_133_U0_out_data_d1; +wire [3:0] tdf4_l2_writeOutputs_133_U0_l2_adjustments_address0; +wire tdf4_l2_writeOutputs_133_U0_l2_adjustments_ce0; +wire tdf4_l2_writeOutputs_133_U0_out_data_full_n; +wire tdf4_l2_writeOutputs_133_U0_out_data_write; +wire ap_sync_continue; +wire ifmap_vec_i_full_n; +wire ifmap_vec_t_empty_n; +wire weight_vecs_0_i_full_n; +wire weight_vecs_0_t_empty_n; +wire products_0_i_full_n; +wire products_0_t_empty_n; +wire [15:0] products_0_t_d1; +wire products_0_t_we1; +wire accum1_out_0_i_full_n; +wire accum1_out_0_t_empty_n; +wire l2_products_i_full_n; +wire l2_products_t_empty_n; +wire indices_01_c_full_n; +wire [15:0] indices_01_c_dout; +wire indices_01_c_empty_n; +wire indices_12_c_full_n; +wire [15:0] indices_12_c_dout; +wire indices_12_c_empty_n; +wire indices_23_c_full_n; +wire [6:0] indices_23_c_dout; +wire indices_23_c_empty_n; +wire indices_23_c1_full_n; +wire [10:0] indices_23_c1_dout; +wire indices_23_c1_empty_n; +wire [0:0] write4_c_din; +wire write4_c_full_n; +wire [0:0] write4_c_dout; +wire write4_c_empty_n; +wire indices_01_c2_full_n; +wire [5:0] indices_01_c2_dout; +wire indices_01_c2_empty_n; +wire indices_12_c3_full_n; +wire [11:0] indices_12_c3_dout; +wire indices_12_c3_empty_n; +wire [15:0] tmp_channel_dout; +wire tmp_channel_empty_n; +wire [15:0] sums_0_dout; +wire sums_0_empty_n; +wire indices_23_c4_full_n; +wire [10:0] indices_23_c4_dout; +wire indices_23_c4_empty_n; +wire [15:0] intermediate_fmaps_0_dout; +wire intermediate_fmaps_0_empty_n; +wire ap_sync_done; +wire ap_sync_ready; +reg ap_sync_reg_tdf4_get_next_ijk_U0_ap_ready; +wire ap_sync_tdf4_get_next_ijk_U0_ap_ready; +reg ap_sync_reg_tdf4_readInputs37_U0_ap_ready; +wire ap_sync_tdf4_readInputs37_U0_ap_ready; +wire [0:0] start_for_tdf4_readFilters36_U0_din; +wire start_for_tdf4_readFilters36_U0_full_n; +wire [0:0] start_for_tdf4_readFilters36_U0_dout; +wire start_for_tdf4_readFilters36_U0_empty_n; +wire tdf4_readInputs37_U0_start_full_n; +wire tdf4_readInputs37_U0_start_write; +wire tdf4_readFilters36_U0_start_full_n; +wire tdf4_readFilters36_U0_start_write; +wire tdf4_dot_product_U0_start_full_n; +wire tdf4_dot_product_U0_start_write; +wire tdf4_accum_1_U0_start_full_n; +wire tdf4_accum_1_U0_start_write; +wire tdf4_accum_2_U0_start_full_n; +wire tdf4_accum_2_U0_start_write; +wire Block_entry_proc_proc403_U0_start_full_n; +wire Block_entry_proc_proc403_U0_start_write; +wire tdf4_adjust_U0_start_full_n; +wire tdf4_adjust_U0_start_write; +wire tdf4_l2_multiply34_U0_start_full_n; +wire tdf4_l2_multiply34_U0_start_write; +wire tdf4_l2_writeOutputs_133_U0_start_full_n; +wire tdf4_l2_writeOutputs_133_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_sync_reg_tdf4_get_next_ijk_U0_ap_ready = 1'b0; +#0 ap_sync_reg_tdf4_readInputs37_U0_ap_ready = 1'b0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP37832_ifmap_vec #( + .DataWidth( 16 ), + .AddressRange( 144 ), + .AddressWidth( 8 )) +ifmap_vec_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf4_readInputs37_U0_ap_done), + .i_full_n(ifmap_vec_i_full_n), + .i_ce0(tdf4_readInputs37_U0_ifmap_vec_ce0), + .i_we0(tdf4_readInputs37_U0_ifmap_vec_we0), + .i_address0(tdf4_readInputs37_U0_ifmap_vec_address0), + .i_d0(tdf4_readInputs37_U0_ifmap_vec_d0), + .i_q0(ifmap_vec_i_q0), + .i_ce1(tdf4_readInputs37_U0_ifmap_vec_ce1), + .i_we1(tdf4_readInputs37_U0_ifmap_vec_we1), + .i_address1(tdf4_readInputs37_U0_ifmap_vec_address1), + .i_d1(tdf4_readInputs37_U0_ifmap_vec_d1), + .t_ce(1'b1), + .t_read(tdf4_dot_product_U0_ap_ready), + .t_empty_n(ifmap_vec_t_empty_n), + .t_ce0(tdf4_dot_product_U0_ifmap_vec_ce0), + .t_we0(1'b0), + .t_address0(tdf4_dot_product_U0_ifmap_vec_address0), + .t_d0(16'd0), + .t_q0(ifmap_vec_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(8'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37832_weight_vecs_0 #( + .DataWidth( 16 ), + .AddressRange( 144 ), + .AddressWidth( 8 )) +weight_vecs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf4_readFilters36_U0_ap_done), + .i_full_n(weight_vecs_0_i_full_n), + .i_ce0(tdf4_readFilters36_U0_weight_vecs_0_ce0), + .i_we0(tdf4_readFilters36_U0_weight_vecs_0_we0), + .i_address0(tdf4_readFilters36_U0_weight_vecs_0_address0), + .i_d0(tdf4_readFilters36_U0_weight_vecs_0_d0), + .i_q0(weight_vecs_0_i_q0), + .t_ce(1'b1), + .t_read(tdf4_dot_product_U0_ap_ready), + .t_empty_n(weight_vecs_0_t_empty_n), + .t_ce0(tdf4_dot_product_U0_weight_vecs_0_ce0), + .t_we0(1'b0), + .t_address0(tdf4_dot_product_U0_weight_vecs_0_address0), + .t_d0(16'd0), + .t_q0(weight_vecs_0_t_q0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37832_products_0 #( + .DataWidth( 16 ), + .AddressRange( 144 ), + .AddressWidth( 8 )) +products_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf4_dot_product_U0_ap_done), + .i_full_n(products_0_i_full_n), + .i_ce0(tdf4_dot_product_U0_products_0_ce0), + .i_we0(tdf4_dot_product_U0_products_0_we0), + .i_address0(tdf4_dot_product_U0_products_0_address0), + .i_d0(tdf4_dot_product_U0_products_0_d0), + .i_q0(products_0_i_q0), + .i_ce1(1'b0), + .i_address1(8'd0), + .i_q1(products_0_i_q1), + .t_ce(1'b1), + .t_read(tdf4_accum_1_U0_ap_ready), + .t_empty_n(products_0_t_empty_n), + .t_ce0(tdf4_accum_1_U0_accum_in_0_ce0), + .t_we0(1'b0), + .t_address0(tdf4_accum_1_U0_accum_in_0_address0), + .t_d0(16'd0), + .t_q0(products_0_t_q0), + .t_ce1(tdf4_accum_1_U0_accum_in_0_ce1), + .t_address1(tdf4_accum_1_U0_accum_in_0_address1), + .t_q1(products_0_t_q1) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37832_accum1_out_0 #( + .DataWidth( 16 ), + .AddressRange( 8 ), + .AddressWidth( 3 )) +accum1_out_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf4_accum_1_U0_ap_done), + .i_full_n(accum1_out_0_i_full_n), + .i_ce0(tdf4_accum_1_U0_accum_out_ce0), + .i_we0(tdf4_accum_1_U0_accum_out_we0), + .i_address0(tdf4_accum_1_U0_accum_out_address0), + .i_d0(tdf4_accum_1_U0_accum_out_d0), + .i_q0(accum1_out_0_i_q0), + .i_ce1(tdf4_accum_1_U0_accum_out_ce1), + .i_we1(tdf4_accum_1_U0_accum_out_we1), + .i_address1(tdf4_accum_1_U0_accum_out_address1), + .i_d1(tdf4_accum_1_U0_accum_out_d1), + .t_ce(1'b1), + .t_read(tdf4_accum_2_U0_ap_ready), + .t_empty_n(accum1_out_0_t_empty_n), + .t_ce0(tdf4_accum_2_U0_accum_in_ce0), + .t_we0(1'b0), + .t_address0(tdf4_accum_2_U0_accum_in_address0), + .t_d0(16'd0), + .t_q0(accum1_out_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(3'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37832_l2_products #( + .DataWidth( 16 ), + .AddressRange( 16 ), + .AddressWidth( 4 )) +l2_products_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf4_l2_multiply34_U0_ap_done), + .i_full_n(l2_products_i_full_n), + .i_ce0(tdf4_l2_multiply34_U0_l2_products_ce0), + .i_we0(tdf4_l2_multiply34_U0_l2_products_we0), + .i_address0(tdf4_l2_multiply34_U0_l2_products_address0), + .i_d0(tdf4_l2_multiply34_U0_l2_products_d0), + .i_q0(l2_products_i_q0), + .t_ce(1'b1), + .t_read(tdf4_l2_writeOutputs_133_U0_ap_ready), + .t_empty_n(l2_products_t_empty_n), + .t_ce0(tdf4_l2_writeOutputs_133_U0_l2_partial_sums_ce0), + .t_we0(1'b0), + .t_address0(tdf4_l2_writeOutputs_133_U0_l2_partial_sums_address0), + .t_d0(16'd0), + .t_q0(l2_products_t_q0) +); + +td_fused_top_tdf4_get_next_ijk tdf4_get_next_ijk_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf4_get_next_ijk_U0_ap_start), + .start_full_n(start_for_tdf4_readFilters36_U0_full_n), + .ap_done(tdf4_get_next_ijk_U0_ap_done), + .ap_continue(tdf4_get_next_ijk_U0_ap_continue), + .ap_idle(tdf4_get_next_ijk_U0_ap_idle), + .ap_ready(tdf4_get_next_ijk_U0_ap_ready), + .start_out(tdf4_get_next_ijk_U0_start_out), + .start_write(tdf4_get_next_ijk_U0_start_write), + .indices_0_din(tdf4_get_next_ijk_U0_indices_0_din), + .indices_0_full_n(indices_01_c_full_n), + .indices_0_write(tdf4_get_next_ijk_U0_indices_0_write), + .indices_1_din(tdf4_get_next_ijk_U0_indices_1_din), + .indices_1_full_n(indices_12_c_full_n), + .indices_1_write(tdf4_get_next_ijk_U0_indices_1_write), + .indices_2_out_din(tdf4_get_next_ijk_U0_indices_2_out_din), + .indices_2_out_full_n(indices_23_c_full_n), + .indices_2_out_write(tdf4_get_next_ijk_U0_indices_2_out_write), + .indices_2_out1_din(tdf4_get_next_ijk_U0_indices_2_out1_din), + .indices_2_out1_full_n(indices_23_c1_full_n), + .indices_2_out1_write(tdf4_get_next_ijk_U0_indices_2_out1_write), + .write_r_din(tdf4_get_next_ijk_U0_write_r_din), + .write_r_full_n(write4_c_full_n), + .write_r_write(tdf4_get_next_ijk_U0_write_r_write) +); + +td_fused_top_tdf4_readInputs37 tdf4_readInputs37_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf4_readInputs37_U0_ap_start), + .ap_done(tdf4_readInputs37_U0_ap_done), + .ap_continue(tdf4_readInputs37_U0_ap_continue), + .ap_idle(tdf4_readInputs37_U0_ap_idle), + .ap_ready(tdf4_readInputs37_U0_ap_ready), + .in_data_address0(tdf4_readInputs37_U0_in_data_address0), + .in_data_ce0(tdf4_readInputs37_U0_in_data_ce0), + .in_data_q0(in_data_q0), + .indices_01_dout(indices_01_c_dout), + .indices_01_empty_n(indices_01_c_empty_n), + .indices_01_read(tdf4_readInputs37_U0_indices_01_read), + .indices_12_dout(indices_12_c_dout), + .indices_12_empty_n(indices_12_c_empty_n), + .indices_12_read(tdf4_readInputs37_U0_indices_12_read), + .ifmap_vec_address0(tdf4_readInputs37_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf4_readInputs37_U0_ifmap_vec_ce0), + .ifmap_vec_we0(tdf4_readInputs37_U0_ifmap_vec_we0), + .ifmap_vec_d0(tdf4_readInputs37_U0_ifmap_vec_d0), + .ifmap_vec_address1(tdf4_readInputs37_U0_ifmap_vec_address1), + .ifmap_vec_ce1(tdf4_readInputs37_U0_ifmap_vec_ce1), + .ifmap_vec_we1(tdf4_readInputs37_U0_ifmap_vec_we1), + .ifmap_vec_d1(tdf4_readInputs37_U0_ifmap_vec_d1), + .indices_01_out_din(tdf4_readInputs37_U0_indices_01_out_din), + .indices_01_out_full_n(indices_01_c2_full_n), + .indices_01_out_write(tdf4_readInputs37_U0_indices_01_out_write), + .indices_12_out_din(tdf4_readInputs37_U0_indices_12_out_din), + .indices_12_out_full_n(indices_12_c3_full_n), + .indices_12_out_write(tdf4_readInputs37_U0_indices_12_out_write) +); + +td_fused_top_tdf4_readFilters36 tdf4_readFilters36_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf4_readFilters36_U0_ap_start), + .ap_done(tdf4_readFilters36_U0_ap_done), + .ap_continue(tdf4_readFilters36_U0_ap_continue), + .ap_idle(tdf4_readFilters36_U0_ap_idle), + .ap_ready(tdf4_readFilters36_U0_ap_ready), + .filter_data_address0(tdf4_readFilters36_U0_filter_data_address0), + .filter_data_ce0(tdf4_readFilters36_U0_filter_data_ce0), + .filter_data_q0(l1_filter_data_q0), + .indices_23_dout(indices_23_c_dout), + .indices_23_empty_n(indices_23_c_empty_n), + .indices_23_read(tdf4_readFilters36_U0_indices_23_read), + .weight_vecs_0_address0(tdf4_readFilters36_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf4_readFilters36_U0_weight_vecs_0_ce0), + .weight_vecs_0_we0(tdf4_readFilters36_U0_weight_vecs_0_we0), + .weight_vecs_0_d0(tdf4_readFilters36_U0_weight_vecs_0_d0) +); + +td_fused_top_tdf4_dot_product tdf4_dot_product_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf4_dot_product_U0_ap_start), + .ap_done(tdf4_dot_product_U0_ap_done), + .ap_continue(tdf4_dot_product_U0_ap_continue), + .ap_idle(tdf4_dot_product_U0_ap_idle), + .ap_ready(tdf4_dot_product_U0_ap_ready), + .ifmap_vec_address0(tdf4_dot_product_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf4_dot_product_U0_ifmap_vec_ce0), + .ifmap_vec_q0(ifmap_vec_t_q0), + .weight_vecs_0_address0(tdf4_dot_product_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf4_dot_product_U0_weight_vecs_0_ce0), + .weight_vecs_0_q0(weight_vecs_0_t_q0), + .products_0_address0(tdf4_dot_product_U0_products_0_address0), + .products_0_ce0(tdf4_dot_product_U0_products_0_ce0), + .products_0_we0(tdf4_dot_product_U0_products_0_we0), + .products_0_d0(tdf4_dot_product_U0_products_0_d0) +); + +td_fused_top_tdf4_accum_1 tdf4_accum_1_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf4_accum_1_U0_ap_start), + .ap_done(tdf4_accum_1_U0_ap_done), + .ap_continue(tdf4_accum_1_U0_ap_continue), + .ap_idle(tdf4_accum_1_U0_ap_idle), + .ap_ready(tdf4_accum_1_U0_ap_ready), + .accum_in_0_address0(tdf4_accum_1_U0_accum_in_0_address0), + .accum_in_0_ce0(tdf4_accum_1_U0_accum_in_0_ce0), + .accum_in_0_q0(products_0_t_q0), + .accum_in_0_address1(tdf4_accum_1_U0_accum_in_0_address1), + .accum_in_0_ce1(tdf4_accum_1_U0_accum_in_0_ce1), + .accum_in_0_q1(products_0_t_q1), + .accum_out_address0(tdf4_accum_1_U0_accum_out_address0), + .accum_out_ce0(tdf4_accum_1_U0_accum_out_ce0), + .accum_out_we0(tdf4_accum_1_U0_accum_out_we0), + .accum_out_d0(tdf4_accum_1_U0_accum_out_d0), + .accum_out_address1(tdf4_accum_1_U0_accum_out_address1), + .accum_out_ce1(tdf4_accum_1_U0_accum_out_ce1), + .accum_out_we1(tdf4_accum_1_U0_accum_out_we1), + .accum_out_d1(tdf4_accum_1_U0_accum_out_d1) +); + +td_fused_top_tdf4_accum_2 tdf4_accum_2_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf4_accum_2_U0_ap_start), + .ap_done(tdf4_accum_2_U0_ap_done), + .ap_continue(tdf4_accum_2_U0_ap_continue), + .ap_idle(tdf4_accum_2_U0_ap_idle), + .ap_ready(tdf4_accum_2_U0_ap_ready), + .accum_in_12(tdf4_accum_2_U0_accum_in_12), + .accum_in_12_ap_vld(tdf4_accum_2_U0_accum_in_12_ap_vld), + .accum_in_address0(tdf4_accum_2_U0_accum_in_address0), + .accum_in_ce0(tdf4_accum_2_U0_accum_in_ce0), + .accum_in_q0(accum1_out_0_t_q0) +); + +td_fused_top_Block_entry_proc_proc403 Block_entry_proc_proc403_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(Block_entry_proc_proc403_U0_ap_start), + .ap_done(Block_entry_proc_proc403_U0_ap_done), + .ap_continue(Block_entry_proc_proc403_U0_ap_continue), + .ap_idle(Block_entry_proc_proc403_U0_ap_idle), + .ap_ready(Block_entry_proc_proc403_U0_ap_ready), + .tmp(tmp_channel_dout), + .ap_return(Block_entry_proc_proc403_U0_ap_return) +); + +td_fused_top_tdf4_adjust tdf4_adjust_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf4_adjust_U0_ap_start), + .ap_done(tdf4_adjust_U0_ap_done), + .ap_continue(tdf4_adjust_U0_ap_continue), + .ap_idle(tdf4_adjust_U0_ap_idle), + .ap_ready(tdf4_adjust_U0_ap_ready), + .sums_read(sums_0_dout), + .adjustments_address0(tdf4_adjust_U0_adjustments_address0), + .adjustments_ce0(tdf4_adjust_U0_adjustments_ce0), + .adjustments_q0(l1_adjustments_q0), + .indices_23_dout(indices_23_c1_dout), + .indices_23_empty_n(indices_23_c1_empty_n), + .indices_23_read(tdf4_adjust_U0_indices_23_read), + .indices_23_out_din(tdf4_adjust_U0_indices_23_out_din), + .indices_23_out_full_n(indices_23_c4_full_n), + .indices_23_out_write(tdf4_adjust_U0_indices_23_out_write), + .ap_return(tdf4_adjust_U0_ap_return) +); + +td_fused_top_tdf4_l2_multiply34 tdf4_l2_multiply34_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf4_l2_multiply34_U0_ap_start), + .ap_done(tdf4_l2_multiply34_U0_ap_done), + .ap_continue(tdf4_l2_multiply34_U0_ap_continue), + .ap_idle(tdf4_l2_multiply34_U0_ap_idle), + .ap_ready(tdf4_l2_multiply34_U0_ap_ready), + .intermediate_fmaps_read(intermediate_fmaps_0_dout), + .l2_filter_data_address0(tdf4_l2_multiply34_U0_l2_filter_data_address0), + .l2_filter_data_ce0(tdf4_l2_multiply34_U0_l2_filter_data_ce0), + .l2_filter_data_q0(l2_filter_data_q0), + .l2_products_address0(tdf4_l2_multiply34_U0_l2_products_address0), + .l2_products_ce0(tdf4_l2_multiply34_U0_l2_products_ce0), + .l2_products_we0(tdf4_l2_multiply34_U0_l2_products_we0), + .l2_products_d0(tdf4_l2_multiply34_U0_l2_products_d0), + .indices_23_dout(indices_23_c4_dout), + .indices_23_empty_n(indices_23_c4_empty_n), + .indices_23_read(tdf4_l2_multiply34_U0_indices_23_read) +); + +td_fused_top_tdf4_l2_writeOutputs_133 tdf4_l2_writeOutputs_133_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf4_l2_writeOutputs_133_U0_ap_start), + .ap_done(tdf4_l2_writeOutputs_133_U0_ap_done), + .ap_continue(tdf4_l2_writeOutputs_133_U0_ap_continue), + .ap_idle(tdf4_l2_writeOutputs_133_U0_ap_idle), + .ap_ready(tdf4_l2_writeOutputs_133_U0_ap_ready), + .indices_01_dout(indices_01_c2_dout), + .indices_01_empty_n(indices_01_c2_empty_n), + .indices_01_read(tdf4_l2_writeOutputs_133_U0_indices_01_read), + .indices_12_dout(indices_12_c3_dout), + .indices_12_empty_n(indices_12_c3_empty_n), + .indices_12_read(tdf4_l2_writeOutputs_133_U0_indices_12_read), + .write4_dout(write4_c_dout), + .write4_empty_n(write4_c_empty_n), + .write4_read(tdf4_l2_writeOutputs_133_U0_write4_read), + .l2_partial_sums_address0(tdf4_l2_writeOutputs_133_U0_l2_partial_sums_address0), + .l2_partial_sums_ce0(tdf4_l2_writeOutputs_133_U0_l2_partial_sums_ce0), + .l2_partial_sums_q0(l2_products_t_q0), + .out_data_address1(tdf4_l2_writeOutputs_133_U0_out_data_address1), + .out_data_ce1(tdf4_l2_writeOutputs_133_U0_out_data_ce1), + .out_data_we1(tdf4_l2_writeOutputs_133_U0_out_data_we1), + .out_data_d1(tdf4_l2_writeOutputs_133_U0_out_data_d1), + .l2_adjustments_address0(tdf4_l2_writeOutputs_133_U0_l2_adjustments_address0), + .l2_adjustments_ce0(tdf4_l2_writeOutputs_133_U0_l2_adjustments_ce0), + .l2_adjustments_q0(l2_adjustments_q0) +); + +td_fused_top_fifo_w16_d2_S_x1 indices_01_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf4_readInputs37_U0_indices_01_read), + .if_dout(indices_01_c_dout), + .if_full_n(indices_01_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf4_get_next_ijk_U0_indices_0_write), + .if_din(tdf4_get_next_ijk_U0_indices_0_din) +); + +td_fused_top_fifo_w16_d2_S_x1 indices_12_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf4_readInputs37_U0_indices_12_read), + .if_dout(indices_12_c_dout), + .if_full_n(indices_12_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf4_get_next_ijk_U0_indices_1_write), + .if_din(tdf4_get_next_ijk_U0_indices_1_din) +); + +td_fused_top_fifo_w7_d2_S indices_23_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf4_readFilters36_U0_indices_23_read), + .if_dout(indices_23_c_dout), + .if_full_n(indices_23_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf4_get_next_ijk_U0_indices_2_out_write), + .if_din(tdf4_get_next_ijk_U0_indices_2_out_din) +); + +td_fused_top_fifo_w11_d7_S indices_23_c1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf4_adjust_U0_indices_23_read), + .if_dout(indices_23_c1_dout), + .if_full_n(indices_23_c1_full_n), + .if_write_ce(1'b1), + .if_write(tdf4_get_next_ijk_U0_indices_2_out1_write), + .if_din(tdf4_get_next_ijk_U0_indices_2_out1_din) +); + +td_fused_top_fifo_w1_d9_S_x write4_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(write4_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf4_l2_writeOutputs_133_U0_write4_read), + .if_dout(write4_c_dout), + .if_full_n(write4_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf4_get_next_ijk_U0_write_r_write), + .if_din(write4_c_din) +); + +td_fused_top_fifo_w6_d8_S_x indices_01_c2_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c2_empty_n), + .if_read_ce(1'b1), + .if_read(tdf4_l2_writeOutputs_133_U0_indices_01_read), + .if_dout(indices_01_c2_dout), + .if_full_n(indices_01_c2_full_n), + .if_write_ce(1'b1), + .if_write(tdf4_readInputs37_U0_indices_01_out_write), + .if_din(tdf4_readInputs37_U0_indices_01_out_din) +); + +td_fused_top_fifo_w12_d8_S_x indices_12_c3_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c3_empty_n), + .if_read_ce(1'b1), + .if_read(tdf4_l2_writeOutputs_133_U0_indices_12_read), + .if_dout(indices_12_c3_dout), + .if_full_n(indices_12_c3_full_n), + .if_write_ce(1'b1), + .if_write(tdf4_readInputs37_U0_indices_12_out_write), + .if_din(tdf4_readInputs37_U0_indices_12_out_din) +); + +td_fused_top_fifo_w16_d2_S_x1 tmp_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(tmp_channel_empty_n), + .if_read_ce(1'b1), + .if_read(Block_entry_proc_proc403_U0_ap_ready), + .if_dout(tmp_channel_dout), + .if_full_n(tmp_channel_full_n), + .if_write_ce(1'b1), + .if_write(tdf4_accum_2_U0_ap_done), + .if_din(tdf4_accum_2_U0_accum_in_12) +); + +td_fused_top_fifo_w16_d2_S_x1 sums_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(sums_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf4_adjust_U0_ap_ready), + .if_dout(sums_0_dout), + .if_full_n(sums_0_full_n), + .if_write_ce(1'b1), + .if_write(Block_entry_proc_proc403_U0_ap_done), + .if_din(Block_entry_proc_proc403_U0_ap_return) +); + +td_fused_top_fifo_w11_d2_S indices_23_c4_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c4_empty_n), + .if_read_ce(1'b1), + .if_read(tdf4_l2_multiply34_U0_indices_23_read), + .if_dout(indices_23_c4_dout), + .if_full_n(indices_23_c4_full_n), + .if_write_ce(1'b1), + .if_write(tdf4_adjust_U0_indices_23_out_write), + .if_din(tdf4_adjust_U0_indices_23_out_din) +); + +td_fused_top_fifo_w16_d2_S_x1 intermediate_fmaps_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(intermediate_fmaps_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf4_l2_multiply34_U0_ap_ready), + .if_dout(intermediate_fmaps_0_dout), + .if_full_n(intermediate_fmaps_0_full_n), + .if_write_ce(1'b1), + .if_write(tdf4_adjust_U0_ap_done), + .if_din(tdf4_adjust_U0_ap_return) +); + +td_fused_top_start_for_tdf4_readFilters36_U0 start_for_tdf4_readFilters36_U0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(start_for_tdf4_readFilters36_U0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf4_readFilters36_U0_ap_ready), + .if_dout(start_for_tdf4_readFilters36_U0_dout), + .if_full_n(start_for_tdf4_readFilters36_U0_full_n), + .if_write_ce(1'b1), + .if_write(tdf4_get_next_ijk_U0_start_write), + .if_din(start_for_tdf4_readFilters36_U0_din) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf4_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf4_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf4_get_next_ijk_U0_ap_ready <= ap_sync_tdf4_get_next_ijk_U0_ap_ready; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf4_readInputs37_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf4_readInputs37_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf4_readInputs37_U0_ap_ready <= ap_sync_tdf4_readInputs37_U0_ap_ready; + end + end +end + +assign Block_entry_proc_proc403_U0_ap_continue = sums_0_full_n; + +assign Block_entry_proc_proc403_U0_ap_start = tmp_channel_empty_n; + +assign Block_entry_proc_proc403_U0_start_full_n = 1'b1; + +assign Block_entry_proc_proc403_U0_start_write = 1'b0; + +assign ap_channel_done_accum1_out_0 = tdf4_accum_1_U0_ap_done; + +assign ap_channel_done_ifmap_vec = tdf4_readInputs37_U0_ap_done; + +assign ap_channel_done_intermediate_fmaps_0 = tdf4_adjust_U0_ap_done; + +assign ap_channel_done_l2_products = tdf4_l2_multiply34_U0_ap_done; + +assign ap_channel_done_products_0 = tdf4_dot_product_U0_ap_done; + +assign ap_channel_done_sums_0 = Block_entry_proc_proc403_U0_ap_done; + +assign ap_channel_done_tmp_channel = tdf4_accum_2_U0_ap_done; + +assign ap_channel_done_weight_vecs_0 = tdf4_readFilters36_U0_ap_done; + +assign ap_done = tdf4_l2_writeOutputs_133_U0_ap_done; + +assign ap_idle = (tdf4_readInputs37_U0_ap_idle & tdf4_readFilters36_U0_ap_idle & tdf4_l2_writeOutputs_133_U0_ap_idle & tdf4_l2_multiply34_U0_ap_idle & tdf4_get_next_ijk_U0_ap_idle & tdf4_dot_product_U0_ap_idle & tdf4_adjust_U0_ap_idle & tdf4_accum_2_U0_ap_idle & tdf4_accum_1_U0_ap_idle & (intermediate_fmaps_0_empty_n ^ 1'b1) & (sums_0_empty_n ^ 1'b1) & (tmp_channel_empty_n ^ 1'b1) & (l2_products_t_empty_n ^ 1'b1) & (products_0_t_empty_n ^ 1'b1) & (weight_vecs_0_t_empty_n ^ 1'b1) & (ifmap_vec_t_empty_n ^ 1'b1) & (1'b1 ^ accum1_out_0_t_empty_n) & Block_entry_proc_proc403_U0_ap_idle); + +assign ap_ready = ap_sync_ready; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = tdf4_l2_writeOutputs_133_U0_ap_done; + +assign ap_sync_ready = (ap_sync_tdf4_readInputs37_U0_ap_ready & ap_sync_tdf4_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf4_get_next_ijk_U0_ap_ready = (tdf4_get_next_ijk_U0_ap_ready | ap_sync_reg_tdf4_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf4_readInputs37_U0_ap_ready = (tdf4_readInputs37_U0_ap_ready | ap_sync_reg_tdf4_readInputs37_U0_ap_ready); + +assign in_data_address0 = tdf4_readInputs37_U0_in_data_address0; + +assign in_data_address1 = 14'd0; + +assign in_data_ce0 = tdf4_readInputs37_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = tdf4_readInputs37_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign l1_adjustments_address0 = tdf4_adjust_U0_adjustments_address0; + +assign l1_adjustments_address1 = 7'd0; + +assign l1_adjustments_ce0 = tdf4_adjust_U0_adjustments_ce0; + +assign l1_adjustments_ce1 = 1'b0; + +assign l1_adjustments_d0 = 48'd0; + +assign l1_adjustments_d1 = 48'd0; + +assign l1_adjustments_we0 = 1'b0; + +assign l1_adjustments_we1 = 1'b0; + +assign l1_filter_data_address0 = tdf4_readFilters36_U0_filter_data_address0; + +assign l1_filter_data_address1 = 15'd0; + +assign l1_filter_data_ce0 = tdf4_readFilters36_U0_filter_data_ce0; + +assign l1_filter_data_ce1 = 1'b0; + +assign l1_filter_data_d0 = 16'd0; + +assign l1_filter_data_d1 = 16'd0; + +assign l1_filter_data_we0 = 1'b0; + +assign l1_filter_data_we1 = 1'b0; + +assign l2_adjustments_address0 = tdf4_l2_writeOutputs_133_U0_l2_adjustments_address0; + +assign l2_adjustments_address1 = 4'd0; + +assign l2_adjustments_ce0 = tdf4_l2_writeOutputs_133_U0_l2_adjustments_ce0; + +assign l2_adjustments_ce1 = 1'b0; + +assign l2_adjustments_d0 = 48'd0; + +assign l2_adjustments_d1 = 48'd0; + +assign l2_adjustments_we0 = 1'b0; + +assign l2_adjustments_we1 = 1'b0; + +assign l2_filter_data_address0 = tdf4_l2_multiply34_U0_l2_filter_data_address0; + +assign l2_filter_data_address1 = 11'd0; + +assign l2_filter_data_ce0 = tdf4_l2_multiply34_U0_l2_filter_data_ce0; + +assign l2_filter_data_ce1 = 1'b0; + +assign l2_filter_data_d0 = 16'd0; + +assign l2_filter_data_d1 = 16'd0; + +assign l2_filter_data_we0 = 1'b0; + +assign l2_filter_data_we1 = 1'b0; + +assign out_data_address0 = 14'd0; + +assign out_data_address1 = tdf4_l2_writeOutputs_133_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = tdf4_l2_writeOutputs_133_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = tdf4_l2_writeOutputs_133_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = tdf4_l2_writeOutputs_133_U0_out_data_we1; + +assign out_data_write = tdf4_l2_writeOutputs_133_U0_out_data_write; + +assign products_0_t_d1 = 16'd0; + +assign products_0_t_we1 = 1'b0; + +assign start_for_tdf4_readFilters36_U0_din = 1'b1; + +assign tdf4_accum_1_U0_accum_out_full_n = accum1_out_0_i_full_n; + +assign tdf4_accum_1_U0_ap_continue = accum1_out_0_i_full_n; + +assign tdf4_accum_1_U0_ap_start = products_0_t_empty_n; + +assign tdf4_accum_1_U0_start_full_n = 1'b1; + +assign tdf4_accum_1_U0_start_write = 1'b0; + +assign tdf4_accum_2_U0_ap_continue = tmp_channel_full_n; + +assign tdf4_accum_2_U0_ap_start = accum1_out_0_t_empty_n; + +assign tdf4_accum_2_U0_start_full_n = 1'b1; + +assign tdf4_accum_2_U0_start_write = 1'b0; + +assign tdf4_adjust_U0_ap_continue = intermediate_fmaps_0_full_n; + +assign tdf4_adjust_U0_ap_start = sums_0_empty_n; + +assign tdf4_adjust_U0_start_full_n = 1'b1; + +assign tdf4_adjust_U0_start_write = 1'b0; + +assign tdf4_dot_product_U0_ap_continue = products_0_i_full_n; + +assign tdf4_dot_product_U0_ap_start = (weight_vecs_0_t_empty_n & ifmap_vec_t_empty_n); + +assign tdf4_dot_product_U0_products_0_full_n = products_0_i_full_n; + +assign tdf4_dot_product_U0_start_full_n = 1'b1; + +assign tdf4_dot_product_U0_start_write = 1'b0; + +assign tdf4_get_next_ijk_U0_ap_continue = 1'b1; + +assign tdf4_get_next_ijk_U0_ap_start = ((ap_sync_reg_tdf4_get_next_ijk_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf4_l2_multiply34_U0_ap_continue = l2_products_i_full_n; + +assign tdf4_l2_multiply34_U0_ap_start = intermediate_fmaps_0_empty_n; + +assign tdf4_l2_multiply34_U0_l2_products_full_n = l2_products_i_full_n; + +assign tdf4_l2_multiply34_U0_start_full_n = 1'b1; + +assign tdf4_l2_multiply34_U0_start_write = 1'b0; + +assign tdf4_l2_writeOutputs_133_U0_ap_continue = ap_continue; + +assign tdf4_l2_writeOutputs_133_U0_ap_start = l2_products_t_empty_n; + +assign tdf4_l2_writeOutputs_133_U0_out_data_full_n = out_data_full_n; + +assign tdf4_l2_writeOutputs_133_U0_out_data_write = 1'b0; + +assign tdf4_l2_writeOutputs_133_U0_start_full_n = 1'b1; + +assign tdf4_l2_writeOutputs_133_U0_start_write = 1'b0; + +assign tdf4_readFilters36_U0_ap_continue = weight_vecs_0_i_full_n; + +assign tdf4_readFilters36_U0_ap_start = start_for_tdf4_readFilters36_U0_empty_n; + +assign tdf4_readFilters36_U0_start_full_n = 1'b1; + +assign tdf4_readFilters36_U0_start_write = 1'b0; + +assign tdf4_readFilters36_U0_weight_vecs_0_full_n = weight_vecs_0_i_full_n; + +assign tdf4_readInputs37_U0_ap_continue = ifmap_vec_i_full_n; + +assign tdf4_readInputs37_U0_ap_start = ((ap_sync_reg_tdf4_readInputs37_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf4_readInputs37_U0_ifmap_vec_full_n = ifmap_vec_i_full_n; + +assign tdf4_readInputs37_U0_in_data_full_n = in_data_empty_n; + +assign tdf4_readInputs37_U0_in_data_write = 1'b0; + +assign tdf4_readInputs37_U0_start_full_n = 1'b1; + +assign tdf4_readInputs37_U0_start_write = 1'b0; + +assign write4_c_din = tdf4_get_next_ijk_U0_write_r_din; + +endmodule //td_fused_top_dataflow_in_loop_TOP_LOOP37832 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37832_weight_vecs_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 9; +parameter MEM_SIZE = 288; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37832_weight_vecs_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd288; +parameter AddressWidth = 32'd9; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37832_weight_vecs_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37832_weight_vecs_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37832_weight_vecs_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 8, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP37832_weight_vecs_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37832_weight_vecs_0_memcore_U ( + .reset ( reset ), + .clk ( clk ), + .address0 ( memcore_iaddr ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + .address1 ( memcore_taddr ), + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .d1 ( t_d0 ), + .q1 ( t_q0 ) + +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37928_accum1_out_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 3; +parameter MEM_SIZE = 8; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37928_accum1_out_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd8; +parameter AddressWidth = 32'd3; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37928_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37928_accum1_out_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37928_accum1_out_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 3, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37928_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37928_accum1_out_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37928_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37928_accum1_out_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37928_ifmap_vec_0_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 5; +parameter MEM_SIZE = 32; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37928_ifmap_vec_0_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd32; +parameter AddressWidth = 32'd5; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37928_ifmap_vec_0_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37928_ifmap_vec_0_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37928_ifmap_vec_0_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 5, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37928_ifmap_vec_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37928_ifmap_vec_0_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37928_ifmap_vec_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37928_ifmap_vec_0_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37928_products_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 5; +parameter MEM_SIZE = 32; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37928_products_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd32; +parameter AddressWidth = 32'd5; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37928_products_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37928_products_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37928_products_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 5, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire [AddressWidth-1:0] i_address1, + output wire [DataWidth-1:0] i_q1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire [AddressWidth-1:0] t_address1, + output wire [DataWidth-1:0] t_q1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_q1_0, buf_q1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP37928_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37928_products_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .q1 ( buf_q1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP37928_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37928_products_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .q1 ( buf_q1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign i_q1 = (prev_iptr == 1'b1 ? buf_q1_1 : buf_q1_0); +assign t_q1 = reg_valid1 ? reg_q1 : (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// reg_q1 and reg_valid1 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q1 <= 1'b0; + reg_valid1 <= 1'b0; + end else if (!t_ce1 && !reg_valid1) begin + reg_q1 <= (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + reg_valid1 <= 1'b1; + end else if (t_ce1) begin + reg_valid1 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37928 ( + ap_clk, + ap_rst, + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + ap_start, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +input ap_clk; +input ap_rst; +output [14:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [14:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [8:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [8:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [3:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [3:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +output [13:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [13:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +input ap_start; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +wire [15:0] ifmap_vec_0_0_i_q0; +wire [15:0] ifmap_vec_0_0_t_q0; +wire [15:0] weight_vecs_0_0_0_i_q0; +wire [15:0] weight_vecs_0_0_0_t_q0; +wire [15:0] products_0_i_q0; +wire [15:0] products_0_i_q1; +wire [15:0] products_0_t_q0; +wire [15:0] products_0_t_q1; +wire [15:0] accum1_out_0_i_q0; +wire [15:0] accum1_out_0_t_q0; +wire tdf3_get_next_ijk_U0_ap_start; +wire tdf3_get_next_ijk_U0_ap_done; +wire tdf3_get_next_ijk_U0_ap_continue; +wire tdf3_get_next_ijk_U0_ap_idle; +wire tdf3_get_next_ijk_U0_ap_ready; +wire tdf3_get_next_ijk_U0_start_out; +wire tdf3_get_next_ijk_U0_start_write; +wire [15:0] tdf3_get_next_ijk_U0_indices_0_din; +wire tdf3_get_next_ijk_U0_indices_0_write; +wire [15:0] tdf3_get_next_ijk_U0_indices_1_din; +wire tdf3_get_next_ijk_U0_indices_1_write; +wire [3:0] tdf3_get_next_ijk_U0_indices_2_out_din; +wire tdf3_get_next_ijk_U0_indices_2_out_write; +wire [3:0] tdf3_get_next_ijk_U0_indices_2_out1_din; +wire tdf3_get_next_ijk_U0_indices_2_out1_write; +wire tdf3_readInputs_U0_ap_start; +wire tdf3_readInputs_U0_ap_done; +wire tdf3_readInputs_U0_ap_continue; +wire tdf3_readInputs_U0_ap_idle; +wire tdf3_readInputs_U0_ap_ready; +wire [14:0] tdf3_readInputs_U0_in_data_address0; +wire tdf3_readInputs_U0_in_data_ce0; +wire tdf3_readInputs_U0_indices_01_read; +wire tdf3_readInputs_U0_indices_12_read; +wire [4:0] tdf3_readInputs_U0_ifmap_vec_0_0_address0; +wire tdf3_readInputs_U0_ifmap_vec_0_0_ce0; +wire tdf3_readInputs_U0_ifmap_vec_0_0_we0; +wire [15:0] tdf3_readInputs_U0_ifmap_vec_0_0_d0; +wire [4:0] tdf3_readInputs_U0_ifmap_vec_0_0_address1; +wire tdf3_readInputs_U0_ifmap_vec_0_0_ce1; +wire tdf3_readInputs_U0_ifmap_vec_0_0_we1; +wire [15:0] tdf3_readInputs_U0_ifmap_vec_0_0_d1; +wire [5:0] tdf3_readInputs_U0_indices_01_out_din; +wire tdf3_readInputs_U0_indices_01_out_write; +wire [11:0] tdf3_readInputs_U0_indices_12_out_din; +wire tdf3_readInputs_U0_indices_12_out_write; +wire tdf3_readInputs_U0_in_data_full_n; +wire tdf3_readInputs_U0_in_data_write; +wire ap_channel_done_ifmap_vec_0_0; +wire tdf3_readInputs_U0_ifmap_vec_0_0_full_n; +wire tdf3_readFilters30_U0_ap_start; +wire tdf3_readFilters30_U0_ap_done; +wire tdf3_readFilters30_U0_ap_continue; +wire tdf3_readFilters30_U0_ap_idle; +wire tdf3_readFilters30_U0_ap_ready; +wire [8:0] tdf3_readFilters30_U0_filter_data_address0; +wire tdf3_readFilters30_U0_filter_data_ce0; +wire tdf3_readFilters30_U0_indices_23_read; +wire [4:0] tdf3_readFilters30_U0_weight_vecs_0_0_0_address0; +wire tdf3_readFilters30_U0_weight_vecs_0_0_0_ce0; +wire tdf3_readFilters30_U0_weight_vecs_0_0_0_we0; +wire [15:0] tdf3_readFilters30_U0_weight_vecs_0_0_0_d0; +wire ap_channel_done_weight_vecs_0_0_0; +wire tdf3_readFilters30_U0_weight_vecs_0_0_0_full_n; +wire tdf3_dot_product_U0_ap_start; +wire tdf3_dot_product_U0_ap_done; +wire tdf3_dot_product_U0_ap_continue; +wire tdf3_dot_product_U0_ap_idle; +wire tdf3_dot_product_U0_ap_ready; +wire [4:0] tdf3_dot_product_U0_ifmap_vec_0_0_address0; +wire tdf3_dot_product_U0_ifmap_vec_0_0_ce0; +wire [4:0] tdf3_dot_product_U0_weight_vecs_0_0_0_address0; +wire tdf3_dot_product_U0_weight_vecs_0_0_0_ce0; +wire [4:0] tdf3_dot_product_U0_products_0_address0; +wire tdf3_dot_product_U0_products_0_ce0; +wire tdf3_dot_product_U0_products_0_we0; +wire [15:0] tdf3_dot_product_U0_products_0_d0; +wire ap_channel_done_products_0; +wire tdf3_dot_product_U0_products_0_full_n; +wire tdf3_accum_1_U0_ap_start; +wire tdf3_accum_1_U0_ap_done; +wire tdf3_accum_1_U0_ap_continue; +wire tdf3_accum_1_U0_ap_idle; +wire tdf3_accum_1_U0_ap_ready; +wire [4:0] tdf3_accum_1_U0_accum_in_0_address0; +wire tdf3_accum_1_U0_accum_in_0_ce0; +wire [4:0] tdf3_accum_1_U0_accum_in_0_address1; +wire tdf3_accum_1_U0_accum_in_0_ce1; +wire [2:0] tdf3_accum_1_U0_accum_out_address0; +wire tdf3_accum_1_U0_accum_out_ce0; +wire tdf3_accum_1_U0_accum_out_we0; +wire [15:0] tdf3_accum_1_U0_accum_out_d0; +wire [2:0] tdf3_accum_1_U0_accum_out_address1; +wire tdf3_accum_1_U0_accum_out_ce1; +wire tdf3_accum_1_U0_accum_out_we1; +wire [15:0] tdf3_accum_1_U0_accum_out_d1; +wire ap_channel_done_accum1_out_0; +wire tdf3_accum_1_U0_accum_out_full_n; +wire tdf3_accum_2_U0_ap_start; +wire tdf3_accum_2_U0_ap_done; +wire tdf3_accum_2_U0_ap_continue; +wire tdf3_accum_2_U0_ap_idle; +wire tdf3_accum_2_U0_ap_ready; +wire [15:0] tdf3_accum_2_U0_accum_in_14; +wire tdf3_accum_2_U0_accum_in_14_ap_vld; +wire [2:0] tdf3_accum_2_U0_accum_in_address0; +wire tdf3_accum_2_U0_accum_in_ce0; +wire ap_channel_done_tmp_channel; +wire tmp_channel_full_n; +wire Block_entry_proc_proc397_U0_ap_start; +wire Block_entry_proc_proc397_U0_ap_done; +wire Block_entry_proc_proc397_U0_ap_continue; +wire Block_entry_proc_proc397_U0_ap_idle; +wire Block_entry_proc_proc397_U0_ap_ready; +wire [15:0] Block_entry_proc_proc397_U0_ap_return; +wire ap_channel_done_sums_0; +wire sums_0_full_n; +wire tdf3_adjust_U0_ap_start; +wire tdf3_adjust_U0_ap_done; +wire tdf3_adjust_U0_ap_continue; +wire tdf3_adjust_U0_ap_idle; +wire tdf3_adjust_U0_ap_ready; +wire [3:0] tdf3_adjust_U0_adjustments_address0; +wire tdf3_adjust_U0_adjustments_ce0; +wire tdf3_adjust_U0_indices_23_read; +wire [15:0] tdf3_adjust_U0_ap_return; +wire ap_channel_done_outputs_0; +wire outputs_0_full_n; +wire tdf3_writeOutputs_unaligned_U0_ap_start; +wire tdf3_writeOutputs_unaligned_U0_ap_done; +wire tdf3_writeOutputs_unaligned_U0_ap_continue; +wire tdf3_writeOutputs_unaligned_U0_ap_idle; +wire tdf3_writeOutputs_unaligned_U0_ap_ready; +wire tdf3_writeOutputs_unaligned_U0_indices_01_read; +wire tdf3_writeOutputs_unaligned_U0_indices_12_read; +wire [13:0] tdf3_writeOutputs_unaligned_U0_out_data_address1; +wire tdf3_writeOutputs_unaligned_U0_out_data_ce1; +wire tdf3_writeOutputs_unaligned_U0_out_data_we1; +wire [63:0] tdf3_writeOutputs_unaligned_U0_out_data_d1; +wire tdf3_writeOutputs_unaligned_U0_out_data_full_n; +wire tdf3_writeOutputs_unaligned_U0_out_data_write; +wire ap_sync_continue; +wire ifmap_vec_0_0_i_full_n; +wire ifmap_vec_0_0_t_empty_n; +wire weight_vecs_0_0_0_i_full_n; +wire weight_vecs_0_0_0_t_empty_n; +wire products_0_i_full_n; +wire products_0_t_empty_n; +wire [15:0] products_0_t_d1; +wire products_0_t_we1; +wire accum1_out_0_i_full_n; +wire accum1_out_0_t_empty_n; +wire indices_01_c_full_n; +wire [15:0] indices_01_c_dout; +wire indices_01_c_empty_n; +wire indices_12_c_full_n; +wire [15:0] indices_12_c_dout; +wire indices_12_c_empty_n; +wire indices_23_c_full_n; +wire [3:0] indices_23_c_dout; +wire indices_23_c_empty_n; +wire indices_23_c1_full_n; +wire [3:0] indices_23_c1_dout; +wire indices_23_c1_empty_n; +wire indices_01_c2_full_n; +wire [5:0] indices_01_c2_dout; +wire indices_01_c2_empty_n; +wire indices_12_c3_full_n; +wire [11:0] indices_12_c3_dout; +wire indices_12_c3_empty_n; +wire [15:0] tmp_channel_dout; +wire tmp_channel_empty_n; +wire [15:0] sums_0_dout; +wire sums_0_empty_n; +wire [15:0] outputs_0_dout; +wire outputs_0_empty_n; +wire ap_sync_done; +wire ap_sync_ready; +reg ap_sync_reg_tdf3_get_next_ijk_U0_ap_ready; +wire ap_sync_tdf3_get_next_ijk_U0_ap_ready; +reg ap_sync_reg_tdf3_readInputs_U0_ap_ready; +wire ap_sync_tdf3_readInputs_U0_ap_ready; +wire [0:0] start_for_tdf3_readFilters30_U0_din; +wire start_for_tdf3_readFilters30_U0_full_n; +wire [0:0] start_for_tdf3_readFilters30_U0_dout; +wire start_for_tdf3_readFilters30_U0_empty_n; +wire tdf3_readInputs_U0_start_full_n; +wire tdf3_readInputs_U0_start_write; +wire tdf3_readFilters30_U0_start_full_n; +wire tdf3_readFilters30_U0_start_write; +wire tdf3_dot_product_U0_start_full_n; +wire tdf3_dot_product_U0_start_write; +wire tdf3_accum_1_U0_start_full_n; +wire tdf3_accum_1_U0_start_write; +wire tdf3_accum_2_U0_start_full_n; +wire tdf3_accum_2_U0_start_write; +wire Block_entry_proc_proc397_U0_start_full_n; +wire Block_entry_proc_proc397_U0_start_write; +wire tdf3_adjust_U0_start_full_n; +wire tdf3_adjust_U0_start_write; +wire tdf3_writeOutputs_unaligned_U0_start_full_n; +wire tdf3_writeOutputs_unaligned_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_sync_reg_tdf3_get_next_ijk_U0_ap_ready = 1'b0; +#0 ap_sync_reg_tdf3_readInputs_U0_ap_ready = 1'b0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP37928_ifmap_vec_0_0 #( + .DataWidth( 16 ), + .AddressRange( 32 ), + .AddressWidth( 5 )) +ifmap_vec_0_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf3_readInputs_U0_ap_done), + .i_full_n(ifmap_vec_0_0_i_full_n), + .i_ce0(tdf3_readInputs_U0_ifmap_vec_0_0_ce0), + .i_we0(tdf3_readInputs_U0_ifmap_vec_0_0_we0), + .i_address0(tdf3_readInputs_U0_ifmap_vec_0_0_address0), + .i_d0(tdf3_readInputs_U0_ifmap_vec_0_0_d0), + .i_q0(ifmap_vec_0_0_i_q0), + .i_ce1(tdf3_readInputs_U0_ifmap_vec_0_0_ce1), + .i_we1(tdf3_readInputs_U0_ifmap_vec_0_0_we1), + .i_address1(tdf3_readInputs_U0_ifmap_vec_0_0_address1), + .i_d1(tdf3_readInputs_U0_ifmap_vec_0_0_d1), + .t_ce(1'b1), + .t_read(tdf3_dot_product_U0_ap_ready), + .t_empty_n(ifmap_vec_0_0_t_empty_n), + .t_ce0(tdf3_dot_product_U0_ifmap_vec_0_0_ce0), + .t_we0(1'b0), + .t_address0(tdf3_dot_product_U0_ifmap_vec_0_0_address0), + .t_d0(16'd0), + .t_q0(ifmap_vec_0_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(5'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37928_weight_vecs_0_0_0 #( + .DataWidth( 16 ), + .AddressRange( 32 ), + .AddressWidth( 5 )) +weight_vecs_0_0_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf3_readFilters30_U0_ap_done), + .i_full_n(weight_vecs_0_0_0_i_full_n), + .i_ce0(tdf3_readFilters30_U0_weight_vecs_0_0_0_ce0), + .i_we0(tdf3_readFilters30_U0_weight_vecs_0_0_0_we0), + .i_address0(tdf3_readFilters30_U0_weight_vecs_0_0_0_address0), + .i_d0(tdf3_readFilters30_U0_weight_vecs_0_0_0_d0), + .i_q0(weight_vecs_0_0_0_i_q0), + .t_ce(1'b1), + .t_read(tdf3_dot_product_U0_ap_ready), + .t_empty_n(weight_vecs_0_0_0_t_empty_n), + .t_ce0(tdf3_dot_product_U0_weight_vecs_0_0_0_ce0), + .t_we0(1'b0), + .t_address0(tdf3_dot_product_U0_weight_vecs_0_0_0_address0), + .t_d0(16'd0), + .t_q0(weight_vecs_0_0_0_t_q0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37928_products_0 #( + .DataWidth( 16 ), + .AddressRange( 32 ), + .AddressWidth( 5 )) +products_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf3_dot_product_U0_ap_done), + .i_full_n(products_0_i_full_n), + .i_ce0(tdf3_dot_product_U0_products_0_ce0), + .i_we0(tdf3_dot_product_U0_products_0_we0), + .i_address0(tdf3_dot_product_U0_products_0_address0), + .i_d0(tdf3_dot_product_U0_products_0_d0), + .i_q0(products_0_i_q0), + .i_ce1(1'b0), + .i_address1(5'd0), + .i_q1(products_0_i_q1), + .t_ce(1'b1), + .t_read(tdf3_accum_1_U0_ap_ready), + .t_empty_n(products_0_t_empty_n), + .t_ce0(tdf3_accum_1_U0_accum_in_0_ce0), + .t_we0(1'b0), + .t_address0(tdf3_accum_1_U0_accum_in_0_address0), + .t_d0(16'd0), + .t_q0(products_0_t_q0), + .t_ce1(tdf3_accum_1_U0_accum_in_0_ce1), + .t_address1(tdf3_accum_1_U0_accum_in_0_address1), + .t_q1(products_0_t_q1) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP37928_accum1_out_0 #( + .DataWidth( 16 ), + .AddressRange( 8 ), + .AddressWidth( 3 )) +accum1_out_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf3_accum_1_U0_ap_done), + .i_full_n(accum1_out_0_i_full_n), + .i_ce0(tdf3_accum_1_U0_accum_out_ce0), + .i_we0(tdf3_accum_1_U0_accum_out_we0), + .i_address0(tdf3_accum_1_U0_accum_out_address0), + .i_d0(tdf3_accum_1_U0_accum_out_d0), + .i_q0(accum1_out_0_i_q0), + .i_ce1(tdf3_accum_1_U0_accum_out_ce1), + .i_we1(tdf3_accum_1_U0_accum_out_we1), + .i_address1(tdf3_accum_1_U0_accum_out_address1), + .i_d1(tdf3_accum_1_U0_accum_out_d1), + .t_ce(1'b1), + .t_read(tdf3_accum_2_U0_ap_ready), + .t_empty_n(accum1_out_0_t_empty_n), + .t_ce0(tdf3_accum_2_U0_accum_in_ce0), + .t_we0(1'b0), + .t_address0(tdf3_accum_2_U0_accum_in_address0), + .t_d0(16'd0), + .t_q0(accum1_out_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(3'd0), + .t_d1(16'd0) +); + +td_fused_top_tdf3_get_next_ijk tdf3_get_next_ijk_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf3_get_next_ijk_U0_ap_start), + .start_full_n(start_for_tdf3_readFilters30_U0_full_n), + .ap_done(tdf3_get_next_ijk_U0_ap_done), + .ap_continue(tdf3_get_next_ijk_U0_ap_continue), + .ap_idle(tdf3_get_next_ijk_U0_ap_idle), + .ap_ready(tdf3_get_next_ijk_U0_ap_ready), + .start_out(tdf3_get_next_ijk_U0_start_out), + .start_write(tdf3_get_next_ijk_U0_start_write), + .indices_0_din(tdf3_get_next_ijk_U0_indices_0_din), + .indices_0_full_n(indices_01_c_full_n), + .indices_0_write(tdf3_get_next_ijk_U0_indices_0_write), + .indices_1_din(tdf3_get_next_ijk_U0_indices_1_din), + .indices_1_full_n(indices_12_c_full_n), + .indices_1_write(tdf3_get_next_ijk_U0_indices_1_write), + .indices_2_out_din(tdf3_get_next_ijk_U0_indices_2_out_din), + .indices_2_out_full_n(indices_23_c_full_n), + .indices_2_out_write(tdf3_get_next_ijk_U0_indices_2_out_write), + .indices_2_out1_din(tdf3_get_next_ijk_U0_indices_2_out1_din), + .indices_2_out1_full_n(indices_23_c1_full_n), + .indices_2_out1_write(tdf3_get_next_ijk_U0_indices_2_out1_write) +); + +td_fused_top_tdf3_readInputs tdf3_readInputs_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf3_readInputs_U0_ap_start), + .ap_done(tdf3_readInputs_U0_ap_done), + .ap_continue(tdf3_readInputs_U0_ap_continue), + .ap_idle(tdf3_readInputs_U0_ap_idle), + .ap_ready(tdf3_readInputs_U0_ap_ready), + .in_data_address0(tdf3_readInputs_U0_in_data_address0), + .in_data_ce0(tdf3_readInputs_U0_in_data_ce0), + .in_data_q0(in_data_q0), + .indices_01_dout(indices_01_c_dout), + .indices_01_empty_n(indices_01_c_empty_n), + .indices_01_read(tdf3_readInputs_U0_indices_01_read), + .indices_12_dout(indices_12_c_dout), + .indices_12_empty_n(indices_12_c_empty_n), + .indices_12_read(tdf3_readInputs_U0_indices_12_read), + .ifmap_vec_0_0_address0(tdf3_readInputs_U0_ifmap_vec_0_0_address0), + .ifmap_vec_0_0_ce0(tdf3_readInputs_U0_ifmap_vec_0_0_ce0), + .ifmap_vec_0_0_we0(tdf3_readInputs_U0_ifmap_vec_0_0_we0), + .ifmap_vec_0_0_d0(tdf3_readInputs_U0_ifmap_vec_0_0_d0), + .ifmap_vec_0_0_address1(tdf3_readInputs_U0_ifmap_vec_0_0_address1), + .ifmap_vec_0_0_ce1(tdf3_readInputs_U0_ifmap_vec_0_0_ce1), + .ifmap_vec_0_0_we1(tdf3_readInputs_U0_ifmap_vec_0_0_we1), + .ifmap_vec_0_0_d1(tdf3_readInputs_U0_ifmap_vec_0_0_d1), + .indices_01_out_din(tdf3_readInputs_U0_indices_01_out_din), + .indices_01_out_full_n(indices_01_c2_full_n), + .indices_01_out_write(tdf3_readInputs_U0_indices_01_out_write), + .indices_12_out_din(tdf3_readInputs_U0_indices_12_out_din), + .indices_12_out_full_n(indices_12_c3_full_n), + .indices_12_out_write(tdf3_readInputs_U0_indices_12_out_write) +); + +td_fused_top_tdf3_readFilters30 tdf3_readFilters30_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf3_readFilters30_U0_ap_start), + .ap_done(tdf3_readFilters30_U0_ap_done), + .ap_continue(tdf3_readFilters30_U0_ap_continue), + .ap_idle(tdf3_readFilters30_U0_ap_idle), + .ap_ready(tdf3_readFilters30_U0_ap_ready), + .filter_data_address0(tdf3_readFilters30_U0_filter_data_address0), + .filter_data_ce0(tdf3_readFilters30_U0_filter_data_ce0), + .filter_data_q0(filter_data_q0), + .indices_23_dout(indices_23_c_dout), + .indices_23_empty_n(indices_23_c_empty_n), + .indices_23_read(tdf3_readFilters30_U0_indices_23_read), + .weight_vecs_0_0_0_address0(tdf3_readFilters30_U0_weight_vecs_0_0_0_address0), + .weight_vecs_0_0_0_ce0(tdf3_readFilters30_U0_weight_vecs_0_0_0_ce0), + .weight_vecs_0_0_0_we0(tdf3_readFilters30_U0_weight_vecs_0_0_0_we0), + .weight_vecs_0_0_0_d0(tdf3_readFilters30_U0_weight_vecs_0_0_0_d0) +); + +td_fused_top_tdf3_dot_product tdf3_dot_product_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf3_dot_product_U0_ap_start), + .ap_done(tdf3_dot_product_U0_ap_done), + .ap_continue(tdf3_dot_product_U0_ap_continue), + .ap_idle(tdf3_dot_product_U0_ap_idle), + .ap_ready(tdf3_dot_product_U0_ap_ready), + .ifmap_vec_0_0_address0(tdf3_dot_product_U0_ifmap_vec_0_0_address0), + .ifmap_vec_0_0_ce0(tdf3_dot_product_U0_ifmap_vec_0_0_ce0), + .ifmap_vec_0_0_q0(ifmap_vec_0_0_t_q0), + .weight_vecs_0_0_0_address0(tdf3_dot_product_U0_weight_vecs_0_0_0_address0), + .weight_vecs_0_0_0_ce0(tdf3_dot_product_U0_weight_vecs_0_0_0_ce0), + .weight_vecs_0_0_0_q0(weight_vecs_0_0_0_t_q0), + .products_0_address0(tdf3_dot_product_U0_products_0_address0), + .products_0_ce0(tdf3_dot_product_U0_products_0_ce0), + .products_0_we0(tdf3_dot_product_U0_products_0_we0), + .products_0_d0(tdf3_dot_product_U0_products_0_d0) +); + +td_fused_top_tdf3_accum_1 tdf3_accum_1_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf3_accum_1_U0_ap_start), + .ap_done(tdf3_accum_1_U0_ap_done), + .ap_continue(tdf3_accum_1_U0_ap_continue), + .ap_idle(tdf3_accum_1_U0_ap_idle), + .ap_ready(tdf3_accum_1_U0_ap_ready), + .accum_in_0_address0(tdf3_accum_1_U0_accum_in_0_address0), + .accum_in_0_ce0(tdf3_accum_1_U0_accum_in_0_ce0), + .accum_in_0_q0(products_0_t_q0), + .accum_in_0_address1(tdf3_accum_1_U0_accum_in_0_address1), + .accum_in_0_ce1(tdf3_accum_1_U0_accum_in_0_ce1), + .accum_in_0_q1(products_0_t_q1), + .accum_out_address0(tdf3_accum_1_U0_accum_out_address0), + .accum_out_ce0(tdf3_accum_1_U0_accum_out_ce0), + .accum_out_we0(tdf3_accum_1_U0_accum_out_we0), + .accum_out_d0(tdf3_accum_1_U0_accum_out_d0), + .accum_out_address1(tdf3_accum_1_U0_accum_out_address1), + .accum_out_ce1(tdf3_accum_1_U0_accum_out_ce1), + .accum_out_we1(tdf3_accum_1_U0_accum_out_we1), + .accum_out_d1(tdf3_accum_1_U0_accum_out_d1) +); + +td_fused_top_tdf3_accum_2 tdf3_accum_2_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf3_accum_2_U0_ap_start), + .ap_done(tdf3_accum_2_U0_ap_done), + .ap_continue(tdf3_accum_2_U0_ap_continue), + .ap_idle(tdf3_accum_2_U0_ap_idle), + .ap_ready(tdf3_accum_2_U0_ap_ready), + .accum_in_14(tdf3_accum_2_U0_accum_in_14), + .accum_in_14_ap_vld(tdf3_accum_2_U0_accum_in_14_ap_vld), + .accum_in_address0(tdf3_accum_2_U0_accum_in_address0), + .accum_in_ce0(tdf3_accum_2_U0_accum_in_ce0), + .accum_in_q0(accum1_out_0_t_q0) +); + +td_fused_top_Block_entry_proc_proc397 Block_entry_proc_proc397_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(Block_entry_proc_proc397_U0_ap_start), + .ap_done(Block_entry_proc_proc397_U0_ap_done), + .ap_continue(Block_entry_proc_proc397_U0_ap_continue), + .ap_idle(Block_entry_proc_proc397_U0_ap_idle), + .ap_ready(Block_entry_proc_proc397_U0_ap_ready), + .tmp(tmp_channel_dout), + .ap_return(Block_entry_proc_proc397_U0_ap_return) +); + +td_fused_top_tdf3_adjust tdf3_adjust_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf3_adjust_U0_ap_start), + .ap_done(tdf3_adjust_U0_ap_done), + .ap_continue(tdf3_adjust_U0_ap_continue), + .ap_idle(tdf3_adjust_U0_ap_idle), + .ap_ready(tdf3_adjust_U0_ap_ready), + .sums_read(sums_0_dout), + .adjustments_address0(tdf3_adjust_U0_adjustments_address0), + .adjustments_ce0(tdf3_adjust_U0_adjustments_ce0), + .adjustments_q0(adjustments_q0), + .indices_23_dout(indices_23_c1_dout), + .indices_23_empty_n(indices_23_c1_empty_n), + .indices_23_read(tdf3_adjust_U0_indices_23_read), + .ap_return(tdf3_adjust_U0_ap_return) +); + +td_fused_top_tdf3_writeOutputs_unaligned tdf3_writeOutputs_unaligned_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf3_writeOutputs_unaligned_U0_ap_start), + .ap_done(tdf3_writeOutputs_unaligned_U0_ap_done), + .ap_continue(tdf3_writeOutputs_unaligned_U0_ap_continue), + .ap_idle(tdf3_writeOutputs_unaligned_U0_ap_idle), + .ap_ready(tdf3_writeOutputs_unaligned_U0_ap_ready), + .indices_01_dout(indices_01_c2_dout), + .indices_01_empty_n(indices_01_c2_empty_n), + .indices_01_read(tdf3_writeOutputs_unaligned_U0_indices_01_read), + .indices_12_dout(indices_12_c3_dout), + .indices_12_empty_n(indices_12_c3_empty_n), + .indices_12_read(tdf3_writeOutputs_unaligned_U0_indices_12_read), + .p_read(outputs_0_dout), + .out_data_address1(tdf3_writeOutputs_unaligned_U0_out_data_address1), + .out_data_ce1(tdf3_writeOutputs_unaligned_U0_out_data_ce1), + .out_data_we1(tdf3_writeOutputs_unaligned_U0_out_data_we1), + .out_data_d1(tdf3_writeOutputs_unaligned_U0_out_data_d1) +); + +td_fused_top_fifo_w16_d2_S_x0 indices_01_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf3_readInputs_U0_indices_01_read), + .if_dout(indices_01_c_dout), + .if_full_n(indices_01_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf3_get_next_ijk_U0_indices_0_write), + .if_din(tdf3_get_next_ijk_U0_indices_0_din) +); + +td_fused_top_fifo_w16_d2_S_x0 indices_12_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf3_readInputs_U0_indices_12_read), + .if_dout(indices_12_c_dout), + .if_full_n(indices_12_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf3_get_next_ijk_U0_indices_1_write), + .if_din(tdf3_get_next_ijk_U0_indices_1_din) +); + +td_fused_top_fifo_w4_d2_S_x indices_23_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf3_readFilters30_U0_indices_23_read), + .if_dout(indices_23_c_dout), + .if_full_n(indices_23_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf3_get_next_ijk_U0_indices_2_out_write), + .if_din(tdf3_get_next_ijk_U0_indices_2_out_din) +); + +td_fused_top_fifo_w4_d7_S indices_23_c1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf3_adjust_U0_indices_23_read), + .if_dout(indices_23_c1_dout), + .if_full_n(indices_23_c1_full_n), + .if_write_ce(1'b1), + .if_write(tdf3_get_next_ijk_U0_indices_2_out1_write), + .if_din(tdf3_get_next_ijk_U0_indices_2_out1_din) +); + +td_fused_top_fifo_w6_d7_S indices_01_c2_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c2_empty_n), + .if_read_ce(1'b1), + .if_read(tdf3_writeOutputs_unaligned_U0_indices_01_read), + .if_dout(indices_01_c2_dout), + .if_full_n(indices_01_c2_full_n), + .if_write_ce(1'b1), + .if_write(tdf3_readInputs_U0_indices_01_out_write), + .if_din(tdf3_readInputs_U0_indices_01_out_din) +); + +td_fused_top_fifo_w12_d7_S indices_12_c3_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c3_empty_n), + .if_read_ce(1'b1), + .if_read(tdf3_writeOutputs_unaligned_U0_indices_12_read), + .if_dout(indices_12_c3_dout), + .if_full_n(indices_12_c3_full_n), + .if_write_ce(1'b1), + .if_write(tdf3_readInputs_U0_indices_12_out_write), + .if_din(tdf3_readInputs_U0_indices_12_out_din) +); + +td_fused_top_fifo_w16_d2_S_x0 tmp_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(tmp_channel_empty_n), + .if_read_ce(1'b1), + .if_read(Block_entry_proc_proc397_U0_ap_ready), + .if_dout(tmp_channel_dout), + .if_full_n(tmp_channel_full_n), + .if_write_ce(1'b1), + .if_write(tdf3_accum_2_U0_ap_done), + .if_din(tdf3_accum_2_U0_accum_in_14) +); + +td_fused_top_fifo_w16_d2_S_x0 sums_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(sums_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf3_adjust_U0_ap_ready), + .if_dout(sums_0_dout), + .if_full_n(sums_0_full_n), + .if_write_ce(1'b1), + .if_write(Block_entry_proc_proc397_U0_ap_done), + .if_din(Block_entry_proc_proc397_U0_ap_return) +); + +td_fused_top_fifo_w16_d2_S_x0 outputs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(outputs_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf3_writeOutputs_unaligned_U0_ap_ready), + .if_dout(outputs_0_dout), + .if_full_n(outputs_0_full_n), + .if_write_ce(1'b1), + .if_write(tdf3_adjust_U0_ap_done), + .if_din(tdf3_adjust_U0_ap_return) +); + +td_fused_top_start_for_tdf3_readFilters30_U0 start_for_tdf3_readFilters30_U0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(start_for_tdf3_readFilters30_U0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf3_readFilters30_U0_ap_ready), + .if_dout(start_for_tdf3_readFilters30_U0_dout), + .if_full_n(start_for_tdf3_readFilters30_U0_full_n), + .if_write_ce(1'b1), + .if_write(tdf3_get_next_ijk_U0_start_write), + .if_din(start_for_tdf3_readFilters30_U0_din) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf3_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf3_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf3_get_next_ijk_U0_ap_ready <= ap_sync_tdf3_get_next_ijk_U0_ap_ready; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf3_readInputs_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf3_readInputs_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf3_readInputs_U0_ap_ready <= ap_sync_tdf3_readInputs_U0_ap_ready; + end + end +end + +assign Block_entry_proc_proc397_U0_ap_continue = sums_0_full_n; + +assign Block_entry_proc_proc397_U0_ap_start = tmp_channel_empty_n; + +assign Block_entry_proc_proc397_U0_start_full_n = 1'b1; + +assign Block_entry_proc_proc397_U0_start_write = 1'b0; + +assign adjustments_address0 = tdf3_adjust_U0_adjustments_address0; + +assign adjustments_address1 = 4'd0; + +assign adjustments_ce0 = tdf3_adjust_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_channel_done_accum1_out_0 = tdf3_accum_1_U0_ap_done; + +assign ap_channel_done_ifmap_vec_0_0 = tdf3_readInputs_U0_ap_done; + +assign ap_channel_done_outputs_0 = tdf3_adjust_U0_ap_done; + +assign ap_channel_done_products_0 = tdf3_dot_product_U0_ap_done; + +assign ap_channel_done_sums_0 = Block_entry_proc_proc397_U0_ap_done; + +assign ap_channel_done_tmp_channel = tdf3_accum_2_U0_ap_done; + +assign ap_channel_done_weight_vecs_0_0_0 = tdf3_readFilters30_U0_ap_done; + +assign ap_done = tdf3_writeOutputs_unaligned_U0_ap_done; + +assign ap_idle = (tdf3_writeOutputs_unaligned_U0_ap_idle & tdf3_readInputs_U0_ap_idle & tdf3_readFilters30_U0_ap_idle & tdf3_get_next_ijk_U0_ap_idle & tdf3_dot_product_U0_ap_idle & tdf3_adjust_U0_ap_idle & tdf3_accum_2_U0_ap_idle & tdf3_accum_1_U0_ap_idle & (outputs_0_empty_n ^ 1'b1) & (sums_0_empty_n ^ 1'b1) & (tmp_channel_empty_n ^ 1'b1) & (products_0_t_empty_n ^ 1'b1) & (weight_vecs_0_0_0_t_empty_n ^ 1'b1) & (ifmap_vec_0_0_t_empty_n ^ 1'b1) & (1'b1 ^ accum1_out_0_t_empty_n) & Block_entry_proc_proc397_U0_ap_idle); + +assign ap_ready = ap_sync_ready; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = tdf3_writeOutputs_unaligned_U0_ap_done; + +assign ap_sync_ready = (ap_sync_tdf3_readInputs_U0_ap_ready & ap_sync_tdf3_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf3_get_next_ijk_U0_ap_ready = (tdf3_get_next_ijk_U0_ap_ready | ap_sync_reg_tdf3_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf3_readInputs_U0_ap_ready = (tdf3_readInputs_U0_ap_ready | ap_sync_reg_tdf3_readInputs_U0_ap_ready); + +assign filter_data_address0 = tdf3_readFilters30_U0_filter_data_address0; + +assign filter_data_address1 = 9'd0; + +assign filter_data_ce0 = tdf3_readFilters30_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = tdf3_readInputs_U0_in_data_address0; + +assign in_data_address1 = 15'd0; + +assign in_data_ce0 = tdf3_readInputs_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = tdf3_readInputs_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 14'd0; + +assign out_data_address1 = tdf3_writeOutputs_unaligned_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = tdf3_writeOutputs_unaligned_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = tdf3_writeOutputs_unaligned_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = tdf3_writeOutputs_unaligned_U0_out_data_we1; + +assign out_data_write = tdf3_writeOutputs_unaligned_U0_out_data_write; + +assign products_0_t_d1 = 16'd0; + +assign products_0_t_we1 = 1'b0; + +assign start_for_tdf3_readFilters30_U0_din = 1'b1; + +assign tdf3_accum_1_U0_accum_out_full_n = accum1_out_0_i_full_n; + +assign tdf3_accum_1_U0_ap_continue = accum1_out_0_i_full_n; + +assign tdf3_accum_1_U0_ap_start = products_0_t_empty_n; + +assign tdf3_accum_1_U0_start_full_n = 1'b1; + +assign tdf3_accum_1_U0_start_write = 1'b0; + +assign tdf3_accum_2_U0_ap_continue = tmp_channel_full_n; + +assign tdf3_accum_2_U0_ap_start = accum1_out_0_t_empty_n; + +assign tdf3_accum_2_U0_start_full_n = 1'b1; + +assign tdf3_accum_2_U0_start_write = 1'b0; + +assign tdf3_adjust_U0_ap_continue = outputs_0_full_n; + +assign tdf3_adjust_U0_ap_start = sums_0_empty_n; + +assign tdf3_adjust_U0_start_full_n = 1'b1; + +assign tdf3_adjust_U0_start_write = 1'b0; + +assign tdf3_dot_product_U0_ap_continue = products_0_i_full_n; + +assign tdf3_dot_product_U0_ap_start = (weight_vecs_0_0_0_t_empty_n & ifmap_vec_0_0_t_empty_n); + +assign tdf3_dot_product_U0_products_0_full_n = products_0_i_full_n; + +assign tdf3_dot_product_U0_start_full_n = 1'b1; + +assign tdf3_dot_product_U0_start_write = 1'b0; + +assign tdf3_get_next_ijk_U0_ap_continue = 1'b1; + +assign tdf3_get_next_ijk_U0_ap_start = ((ap_sync_reg_tdf3_get_next_ijk_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf3_readFilters30_U0_ap_continue = weight_vecs_0_0_0_i_full_n; + +assign tdf3_readFilters30_U0_ap_start = start_for_tdf3_readFilters30_U0_empty_n; + +assign tdf3_readFilters30_U0_start_full_n = 1'b1; + +assign tdf3_readFilters30_U0_start_write = 1'b0; + +assign tdf3_readFilters30_U0_weight_vecs_0_0_0_full_n = weight_vecs_0_0_0_i_full_n; + +assign tdf3_readInputs_U0_ap_continue = ifmap_vec_0_0_i_full_n; + +assign tdf3_readInputs_U0_ap_start = ((ap_sync_reg_tdf3_readInputs_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf3_readInputs_U0_ifmap_vec_0_0_full_n = ifmap_vec_0_0_i_full_n; + +assign tdf3_readInputs_U0_in_data_full_n = in_data_empty_n; + +assign tdf3_readInputs_U0_in_data_write = 1'b0; + +assign tdf3_readInputs_U0_start_full_n = 1'b1; + +assign tdf3_readInputs_U0_start_write = 1'b0; + +assign tdf3_writeOutputs_unaligned_U0_ap_continue = ap_continue; + +assign tdf3_writeOutputs_unaligned_U0_ap_start = outputs_0_empty_n; + +assign tdf3_writeOutputs_unaligned_U0_out_data_full_n = out_data_full_n; + +assign tdf3_writeOutputs_unaligned_U0_out_data_write = 1'b0; + +assign tdf3_writeOutputs_unaligned_U0_start_full_n = 1'b1; + +assign tdf3_writeOutputs_unaligned_U0_start_write = 1'b0; + +endmodule //td_fused_top_dataflow_in_loop_TOP_LOOP37928 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37928_weight_vecs_0_0_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 6; +parameter MEM_SIZE = 64; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP37928_weight_vecs_0_0_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd64; +parameter AddressWidth = 32'd6; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP37928_weight_vecs_0_0_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP37928_weight_vecs_0_0_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP37928_weight_vecs_0_0_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 5, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP37928_weight_vecs_0_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP37928_weight_vecs_0_0_0_memcore_U ( + .reset ( reset ), + .clk ( clk ), + .address0 ( memcore_iaddr ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + .address1 ( memcore_taddr ), + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .d1 ( t_d0 ), + .q1 ( t_q0 ) + +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38022_accum1_out_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 3; +parameter MEM_SIZE = 8; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38022_accum1_out_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd8; +parameter AddressWidth = 32'd3; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38022_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38022_accum1_out_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38022_accum1_out_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 3, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP38022_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38022_accum1_out_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP38022_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38022_accum1_out_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38022_ifmap_vec_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 8; +parameter MEM_SIZE = 144; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38022_ifmap_vec_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd144; +parameter AddressWidth = 32'd8; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38022_ifmap_vec_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38022_ifmap_vec_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38022_ifmap_vec +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 8, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP38022_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38022_ifmap_vec_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP38022_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38022_ifmap_vec_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38022_products_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 8; +parameter MEM_SIZE = 144; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38022_products_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd144; +parameter AddressWidth = 32'd8; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38022_products_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38022_products_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38022_products_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 8, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire [AddressWidth-1:0] i_address1, + output wire [DataWidth-1:0] i_q1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire [AddressWidth-1:0] t_address1, + output wire [DataWidth-1:0] t_q1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_q1_0, buf_q1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP38022_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38022_products_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .q1 ( buf_q1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP38022_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38022_products_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .q1 ( buf_q1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign i_q1 = (prev_iptr == 1'b1 ? buf_q1_1 : buf_q1_0); +assign t_q1 = reg_valid1 ? reg_q1 : (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// reg_q1 and reg_valid1 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q1 <= 1'b0; + reg_valid1 <= 1'b0; + end else if (!t_ce1 && !reg_valid1) begin + reg_q1 <= (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + reg_valid1 <= 1'b1; + end else if (t_ce1) begin + reg_valid1 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38022 ( + ap_clk, + ap_rst, + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + ap_start, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +input ap_clk; +input ap_rst; +output [15:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [15:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [12:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [12:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [4:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [4:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +output [14:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [14:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +input ap_start; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +wire [15:0] ifmap_vec_i_q0; +wire [15:0] ifmap_vec_t_q0; +wire [15:0] weight_vecs_0_i_q0; +wire [15:0] weight_vecs_0_t_q0; +wire [15:0] products_0_i_q0; +wire [15:0] products_0_i_q1; +wire [15:0] products_0_t_q0; +wire [15:0] products_0_t_q1; +wire [15:0] accum1_out_0_i_q0; +wire [15:0] accum1_out_0_t_q0; +wire tdf2_get_next_ijk_U0_ap_start; +wire tdf2_get_next_ijk_U0_ap_done; +wire tdf2_get_next_ijk_U0_ap_continue; +wire tdf2_get_next_ijk_U0_ap_idle; +wire tdf2_get_next_ijk_U0_ap_ready; +wire tdf2_get_next_ijk_U0_start_out; +wire tdf2_get_next_ijk_U0_start_write; +wire [4:0] tdf2_get_next_ijk_U0_input_indices_2_out_din; +wire tdf2_get_next_ijk_U0_input_indices_2_out_write; +wire [4:0] tdf2_get_next_ijk_U0_input_indices_2_out1_din; +wire tdf2_get_next_ijk_U0_input_indices_2_out1_write; +wire [5:0] tdf2_get_next_ijk_U0_output_indices_0_din; +wire tdf2_get_next_ijk_U0_output_indices_0_write; +wire [11:0] tdf2_get_next_ijk_U0_output_indices_1_din; +wire tdf2_get_next_ijk_U0_output_indices_1_write; +wire tdf2_get_next_ijk_U0_resetMaximum_din; +wire tdf2_get_next_ijk_U0_resetMaximum_write; +wire tdf2_get_next_ijk_U0_storeOutput_din; +wire tdf2_get_next_ijk_U0_storeOutput_write; +wire [15:0] tdf2_get_next_ijk_U0_ap_return_0; +wire [15:0] tdf2_get_next_ijk_U0_ap_return_1; +wire ap_channel_done_input_indices_1; +wire input_indices_1_full_n; +reg ap_sync_reg_channel_write_input_indices_1; +wire ap_sync_channel_write_input_indices_1; +wire ap_channel_done_input_indices_0; +wire input_indices_0_full_n; +reg ap_sync_reg_channel_write_input_indices_0; +wire ap_sync_channel_write_input_indices_0; +wire tdf2_readInputs25_U0_ap_start; +wire tdf2_readInputs25_U0_ap_done; +wire tdf2_readInputs25_U0_ap_continue; +wire tdf2_readInputs25_U0_ap_idle; +wire tdf2_readInputs25_U0_ap_ready; +wire [15:0] tdf2_readInputs25_U0_in_data_address0; +wire tdf2_readInputs25_U0_in_data_ce0; +wire [7:0] tdf2_readInputs25_U0_ifmap_vec_address0; +wire tdf2_readInputs25_U0_ifmap_vec_ce0; +wire tdf2_readInputs25_U0_ifmap_vec_we0; +wire [15:0] tdf2_readInputs25_U0_ifmap_vec_d0; +wire [7:0] tdf2_readInputs25_U0_ifmap_vec_address1; +wire tdf2_readInputs25_U0_ifmap_vec_ce1; +wire tdf2_readInputs25_U0_ifmap_vec_we1; +wire [15:0] tdf2_readInputs25_U0_ifmap_vec_d1; +wire tdf2_readInputs25_U0_in_data_full_n; +wire tdf2_readInputs25_U0_in_data_write; +wire ap_channel_done_ifmap_vec; +wire tdf2_readInputs25_U0_ifmap_vec_full_n; +wire tdf2_readFilters24_U0_ap_start; +wire tdf2_readFilters24_U0_ap_done; +wire tdf2_readFilters24_U0_ap_continue; +wire tdf2_readFilters24_U0_ap_idle; +wire tdf2_readFilters24_U0_ap_ready; +wire [12:0] tdf2_readFilters24_U0_filter_data_address0; +wire tdf2_readFilters24_U0_filter_data_ce0; +wire tdf2_readFilters24_U0_input_indices_23_read; +wire [7:0] tdf2_readFilters24_U0_weight_vecs_0_address0; +wire tdf2_readFilters24_U0_weight_vecs_0_ce0; +wire tdf2_readFilters24_U0_weight_vecs_0_we0; +wire [15:0] tdf2_readFilters24_U0_weight_vecs_0_d0; +wire ap_channel_done_weight_vecs_0; +wire tdf2_readFilters24_U0_weight_vecs_0_full_n; +wire tdf2_dot_product_U0_ap_start; +wire tdf2_dot_product_U0_ap_done; +wire tdf2_dot_product_U0_ap_continue; +wire tdf2_dot_product_U0_ap_idle; +wire tdf2_dot_product_U0_ap_ready; +wire [7:0] tdf2_dot_product_U0_ifmap_vec_address0; +wire tdf2_dot_product_U0_ifmap_vec_ce0; +wire [7:0] tdf2_dot_product_U0_weight_vecs_0_address0; +wire tdf2_dot_product_U0_weight_vecs_0_ce0; +wire [7:0] tdf2_dot_product_U0_products_0_address0; +wire tdf2_dot_product_U0_products_0_ce0; +wire tdf2_dot_product_U0_products_0_we0; +wire [15:0] tdf2_dot_product_U0_products_0_d0; +wire ap_channel_done_products_0; +wire tdf2_dot_product_U0_products_0_full_n; +wire tdf2_accum_1_U0_ap_start; +wire tdf2_accum_1_U0_ap_done; +wire tdf2_accum_1_U0_ap_continue; +wire tdf2_accum_1_U0_ap_idle; +wire tdf2_accum_1_U0_ap_ready; +wire [7:0] tdf2_accum_1_U0_accum_in_0_address0; +wire tdf2_accum_1_U0_accum_in_0_ce0; +wire [7:0] tdf2_accum_1_U0_accum_in_0_address1; +wire tdf2_accum_1_U0_accum_in_0_ce1; +wire [2:0] tdf2_accum_1_U0_accum_out_address0; +wire tdf2_accum_1_U0_accum_out_ce0; +wire tdf2_accum_1_U0_accum_out_we0; +wire [15:0] tdf2_accum_1_U0_accum_out_d0; +wire [2:0] tdf2_accum_1_U0_accum_out_address1; +wire tdf2_accum_1_U0_accum_out_ce1; +wire tdf2_accum_1_U0_accum_out_we1; +wire [15:0] tdf2_accum_1_U0_accum_out_d1; +wire ap_channel_done_accum1_out_0; +wire tdf2_accum_1_U0_accum_out_full_n; +wire tdf2_accum_2_U0_ap_start; +wire tdf2_accum_2_U0_ap_done; +wire tdf2_accum_2_U0_ap_continue; +wire tdf2_accum_2_U0_ap_idle; +wire tdf2_accum_2_U0_ap_ready; +wire [15:0] tdf2_accum_2_U0_accum_in_16; +wire tdf2_accum_2_U0_accum_in_16_ap_vld; +wire [2:0] tdf2_accum_2_U0_accum_in_address0; +wire tdf2_accum_2_U0_accum_in_ce0; +wire ap_channel_done_tmp_channel; +wire tmp_channel_full_n; +wire Block_entry_proc_proc392_U0_ap_start; +wire Block_entry_proc_proc392_U0_ap_done; +wire Block_entry_proc_proc392_U0_ap_continue; +wire Block_entry_proc_proc392_U0_ap_idle; +wire Block_entry_proc_proc392_U0_ap_ready; +wire [15:0] Block_entry_proc_proc392_U0_ap_return; +wire ap_channel_done_sums_0; +wire sums_0_full_n; +wire tdf2_adjust_U0_ap_start; +wire tdf2_adjust_U0_ap_done; +wire tdf2_adjust_U0_ap_continue; +wire tdf2_adjust_U0_ap_idle; +wire tdf2_adjust_U0_ap_ready; +wire [4:0] tdf2_adjust_U0_adjustments_address0; +wire tdf2_adjust_U0_adjustments_ce0; +wire tdf2_adjust_U0_input_indices_23_read; +wire [15:0] tdf2_adjust_U0_ap_return; +wire ap_channel_done_outputs_0; +wire outputs_0_full_n; +wire tdf2_poolOutputs_U0_ap_start; +wire tdf2_poolOutputs_U0_ap_done; +wire tdf2_poolOutputs_U0_ap_continue; +wire tdf2_poolOutputs_U0_ap_idle; +wire tdf2_poolOutputs_U0_ap_ready; +wire tdf2_poolOutputs_U0_output_indices_04_read; +wire tdf2_poolOutputs_U0_output_indices_15_read; +wire tdf2_poolOutputs_U0_resetMaximum6_read; +wire tdf2_poolOutputs_U0_storeOutput7_read; +wire [14:0] tdf2_poolOutputs_U0_out_data_address1; +wire tdf2_poolOutputs_U0_out_data_ce1; +wire tdf2_poolOutputs_U0_out_data_we1; +wire [63:0] tdf2_poolOutputs_U0_out_data_d1; +wire tdf2_poolOutputs_U0_out_data_full_n; +wire tdf2_poolOutputs_U0_out_data_write; +wire ap_sync_continue; +wire ifmap_vec_i_full_n; +wire ifmap_vec_t_empty_n; +wire weight_vecs_0_i_full_n; +wire weight_vecs_0_t_empty_n; +wire products_0_i_full_n; +wire products_0_t_empty_n; +wire [15:0] products_0_t_d1; +wire products_0_t_we1; +wire accum1_out_0_i_full_n; +wire accum1_out_0_t_empty_n; +wire input_indices_23_c_full_n; +wire [4:0] input_indices_23_c_dout; +wire input_indices_23_c_empty_n; +wire input_indices_23_c1_full_n; +wire [4:0] input_indices_23_c1_dout; +wire input_indices_23_c1_empty_n; +wire output_indices_04_c_full_n; +wire [5:0] output_indices_04_c_dout; +wire output_indices_04_c_empty_n; +wire output_indices_15_c_full_n; +wire [11:0] output_indices_15_c_dout; +wire output_indices_15_c_empty_n; +wire [0:0] resetMaximum6_c_din; +wire resetMaximum6_c_full_n; +wire [0:0] resetMaximum6_c_dout; +wire resetMaximum6_c_empty_n; +wire [0:0] storeOutput7_c_din; +wire storeOutput7_c_full_n; +wire [0:0] storeOutput7_c_dout; +wire storeOutput7_c_empty_n; +wire [15:0] input_indices_0_dout; +wire input_indices_0_empty_n; +wire [15:0] input_indices_1_dout; +wire input_indices_1_empty_n; +wire [15:0] tmp_channel_dout; +wire tmp_channel_empty_n; +wire [15:0] sums_0_dout; +wire sums_0_empty_n; +wire [15:0] outputs_0_dout; +wire outputs_0_empty_n; +wire ap_sync_done; +wire ap_sync_ready; +reg ap_sync_reg_tdf2_get_next_ijk_U0_ap_ready; +wire ap_sync_tdf2_get_next_ijk_U0_ap_ready; +reg ap_sync_reg_tdf2_readInputs25_U0_ap_ready; +wire ap_sync_tdf2_readInputs25_U0_ap_ready; +wire [0:0] start_for_tdf2_readFilters24_U0_din; +wire start_for_tdf2_readFilters24_U0_full_n; +wire [0:0] start_for_tdf2_readFilters24_U0_dout; +wire start_for_tdf2_readFilters24_U0_empty_n; +wire tdf2_readInputs25_U0_start_full_n; +wire tdf2_readInputs25_U0_start_write; +wire tdf2_readFilters24_U0_start_full_n; +wire tdf2_readFilters24_U0_start_write; +wire tdf2_dot_product_U0_start_full_n; +wire tdf2_dot_product_U0_start_write; +wire tdf2_accum_1_U0_start_full_n; +wire tdf2_accum_1_U0_start_write; +wire tdf2_accum_2_U0_start_full_n; +wire tdf2_accum_2_U0_start_write; +wire Block_entry_proc_proc392_U0_start_full_n; +wire Block_entry_proc_proc392_U0_start_write; +wire tdf2_adjust_U0_start_full_n; +wire tdf2_adjust_U0_start_write; +wire tdf2_poolOutputs_U0_start_full_n; +wire tdf2_poolOutputs_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_sync_reg_channel_write_input_indices_1 = 1'b0; +#0 ap_sync_reg_channel_write_input_indices_0 = 1'b0; +#0 ap_sync_reg_tdf2_get_next_ijk_U0_ap_ready = 1'b0; +#0 ap_sync_reg_tdf2_readInputs25_U0_ap_ready = 1'b0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP38022_ifmap_vec #( + .DataWidth( 16 ), + .AddressRange( 144 ), + .AddressWidth( 8 )) +ifmap_vec_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf2_readInputs25_U0_ap_done), + .i_full_n(ifmap_vec_i_full_n), + .i_ce0(tdf2_readInputs25_U0_ifmap_vec_ce0), + .i_we0(tdf2_readInputs25_U0_ifmap_vec_we0), + .i_address0(tdf2_readInputs25_U0_ifmap_vec_address0), + .i_d0(tdf2_readInputs25_U0_ifmap_vec_d0), + .i_q0(ifmap_vec_i_q0), + .i_ce1(tdf2_readInputs25_U0_ifmap_vec_ce1), + .i_we1(tdf2_readInputs25_U0_ifmap_vec_we1), + .i_address1(tdf2_readInputs25_U0_ifmap_vec_address1), + .i_d1(tdf2_readInputs25_U0_ifmap_vec_d1), + .t_ce(1'b1), + .t_read(tdf2_dot_product_U0_ap_ready), + .t_empty_n(ifmap_vec_t_empty_n), + .t_ce0(tdf2_dot_product_U0_ifmap_vec_ce0), + .t_we0(1'b0), + .t_address0(tdf2_dot_product_U0_ifmap_vec_address0), + .t_d0(16'd0), + .t_q0(ifmap_vec_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(8'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP38022_weight_vecs_0 #( + .DataWidth( 16 ), + .AddressRange( 144 ), + .AddressWidth( 8 )) +weight_vecs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf2_readFilters24_U0_ap_done), + .i_full_n(weight_vecs_0_i_full_n), + .i_ce0(tdf2_readFilters24_U0_weight_vecs_0_ce0), + .i_we0(tdf2_readFilters24_U0_weight_vecs_0_we0), + .i_address0(tdf2_readFilters24_U0_weight_vecs_0_address0), + .i_d0(tdf2_readFilters24_U0_weight_vecs_0_d0), + .i_q0(weight_vecs_0_i_q0), + .t_ce(1'b1), + .t_read(tdf2_dot_product_U0_ap_ready), + .t_empty_n(weight_vecs_0_t_empty_n), + .t_ce0(tdf2_dot_product_U0_weight_vecs_0_ce0), + .t_we0(1'b0), + .t_address0(tdf2_dot_product_U0_weight_vecs_0_address0), + .t_d0(16'd0), + .t_q0(weight_vecs_0_t_q0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP38022_products_0 #( + .DataWidth( 16 ), + .AddressRange( 144 ), + .AddressWidth( 8 )) +products_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf2_dot_product_U0_ap_done), + .i_full_n(products_0_i_full_n), + .i_ce0(tdf2_dot_product_U0_products_0_ce0), + .i_we0(tdf2_dot_product_U0_products_0_we0), + .i_address0(tdf2_dot_product_U0_products_0_address0), + .i_d0(tdf2_dot_product_U0_products_0_d0), + .i_q0(products_0_i_q0), + .i_ce1(1'b0), + .i_address1(8'd0), + .i_q1(products_0_i_q1), + .t_ce(1'b1), + .t_read(tdf2_accum_1_U0_ap_ready), + .t_empty_n(products_0_t_empty_n), + .t_ce0(tdf2_accum_1_U0_accum_in_0_ce0), + .t_we0(1'b0), + .t_address0(tdf2_accum_1_U0_accum_in_0_address0), + .t_d0(16'd0), + .t_q0(products_0_t_q0), + .t_ce1(tdf2_accum_1_U0_accum_in_0_ce1), + .t_address1(tdf2_accum_1_U0_accum_in_0_address1), + .t_q1(products_0_t_q1) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP38022_accum1_out_0 #( + .DataWidth( 16 ), + .AddressRange( 8 ), + .AddressWidth( 3 )) +accum1_out_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf2_accum_1_U0_ap_done), + .i_full_n(accum1_out_0_i_full_n), + .i_ce0(tdf2_accum_1_U0_accum_out_ce0), + .i_we0(tdf2_accum_1_U0_accum_out_we0), + .i_address0(tdf2_accum_1_U0_accum_out_address0), + .i_d0(tdf2_accum_1_U0_accum_out_d0), + .i_q0(accum1_out_0_i_q0), + .i_ce1(tdf2_accum_1_U0_accum_out_ce1), + .i_we1(tdf2_accum_1_U0_accum_out_we1), + .i_address1(tdf2_accum_1_U0_accum_out_address1), + .i_d1(tdf2_accum_1_U0_accum_out_d1), + .t_ce(1'b1), + .t_read(tdf2_accum_2_U0_ap_ready), + .t_empty_n(accum1_out_0_t_empty_n), + .t_ce0(tdf2_accum_2_U0_accum_in_ce0), + .t_we0(1'b0), + .t_address0(tdf2_accum_2_U0_accum_in_address0), + .t_d0(16'd0), + .t_q0(accum1_out_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(3'd0), + .t_d1(16'd0) +); + +td_fused_top_tdf2_get_next_ijk tdf2_get_next_ijk_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf2_get_next_ijk_U0_ap_start), + .start_full_n(start_for_tdf2_readFilters24_U0_full_n), + .ap_done(tdf2_get_next_ijk_U0_ap_done), + .ap_continue(tdf2_get_next_ijk_U0_ap_continue), + .ap_idle(tdf2_get_next_ijk_U0_ap_idle), + .ap_ready(tdf2_get_next_ijk_U0_ap_ready), + .start_out(tdf2_get_next_ijk_U0_start_out), + .start_write(tdf2_get_next_ijk_U0_start_write), + .input_indices_2_out_din(tdf2_get_next_ijk_U0_input_indices_2_out_din), + .input_indices_2_out_full_n(input_indices_23_c_full_n), + .input_indices_2_out_write(tdf2_get_next_ijk_U0_input_indices_2_out_write), + .input_indices_2_out1_din(tdf2_get_next_ijk_U0_input_indices_2_out1_din), + .input_indices_2_out1_full_n(input_indices_23_c1_full_n), + .input_indices_2_out1_write(tdf2_get_next_ijk_U0_input_indices_2_out1_write), + .output_indices_0_din(tdf2_get_next_ijk_U0_output_indices_0_din), + .output_indices_0_full_n(output_indices_04_c_full_n), + .output_indices_0_write(tdf2_get_next_ijk_U0_output_indices_0_write), + .output_indices_1_din(tdf2_get_next_ijk_U0_output_indices_1_din), + .output_indices_1_full_n(output_indices_15_c_full_n), + .output_indices_1_write(tdf2_get_next_ijk_U0_output_indices_1_write), + .resetMaximum_din(tdf2_get_next_ijk_U0_resetMaximum_din), + .resetMaximum_full_n(resetMaximum6_c_full_n), + .resetMaximum_write(tdf2_get_next_ijk_U0_resetMaximum_write), + .storeOutput_din(tdf2_get_next_ijk_U0_storeOutput_din), + .storeOutput_full_n(storeOutput7_c_full_n), + .storeOutput_write(tdf2_get_next_ijk_U0_storeOutput_write), + .ap_return_0(tdf2_get_next_ijk_U0_ap_return_0), + .ap_return_1(tdf2_get_next_ijk_U0_ap_return_1) +); + +td_fused_top_tdf2_readInputs25 tdf2_readInputs25_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf2_readInputs25_U0_ap_start), + .ap_done(tdf2_readInputs25_U0_ap_done), + .ap_continue(tdf2_readInputs25_U0_ap_continue), + .ap_idle(tdf2_readInputs25_U0_ap_idle), + .ap_ready(tdf2_readInputs25_U0_ap_ready), + .in_data_address0(tdf2_readInputs25_U0_in_data_address0), + .in_data_ce0(tdf2_readInputs25_U0_in_data_ce0), + .in_data_q0(in_data_q0), + .i_17(input_indices_0_dout), + .j_17(input_indices_1_dout), + .ifmap_vec_address0(tdf2_readInputs25_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf2_readInputs25_U0_ifmap_vec_ce0), + .ifmap_vec_we0(tdf2_readInputs25_U0_ifmap_vec_we0), + .ifmap_vec_d0(tdf2_readInputs25_U0_ifmap_vec_d0), + .ifmap_vec_address1(tdf2_readInputs25_U0_ifmap_vec_address1), + .ifmap_vec_ce1(tdf2_readInputs25_U0_ifmap_vec_ce1), + .ifmap_vec_we1(tdf2_readInputs25_U0_ifmap_vec_we1), + .ifmap_vec_d1(tdf2_readInputs25_U0_ifmap_vec_d1) +); + +td_fused_top_tdf2_readFilters24 tdf2_readFilters24_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf2_readFilters24_U0_ap_start), + .ap_done(tdf2_readFilters24_U0_ap_done), + .ap_continue(tdf2_readFilters24_U0_ap_continue), + .ap_idle(tdf2_readFilters24_U0_ap_idle), + .ap_ready(tdf2_readFilters24_U0_ap_ready), + .filter_data_address0(tdf2_readFilters24_U0_filter_data_address0), + .filter_data_ce0(tdf2_readFilters24_U0_filter_data_ce0), + .filter_data_q0(filter_data_q0), + .input_indices_23_dout(input_indices_23_c_dout), + .input_indices_23_empty_n(input_indices_23_c_empty_n), + .input_indices_23_read(tdf2_readFilters24_U0_input_indices_23_read), + .weight_vecs_0_address0(tdf2_readFilters24_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf2_readFilters24_U0_weight_vecs_0_ce0), + .weight_vecs_0_we0(tdf2_readFilters24_U0_weight_vecs_0_we0), + .weight_vecs_0_d0(tdf2_readFilters24_U0_weight_vecs_0_d0) +); + +td_fused_top_tdf2_dot_product tdf2_dot_product_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf2_dot_product_U0_ap_start), + .ap_done(tdf2_dot_product_U0_ap_done), + .ap_continue(tdf2_dot_product_U0_ap_continue), + .ap_idle(tdf2_dot_product_U0_ap_idle), + .ap_ready(tdf2_dot_product_U0_ap_ready), + .ifmap_vec_address0(tdf2_dot_product_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf2_dot_product_U0_ifmap_vec_ce0), + .ifmap_vec_q0(ifmap_vec_t_q0), + .weight_vecs_0_address0(tdf2_dot_product_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf2_dot_product_U0_weight_vecs_0_ce0), + .weight_vecs_0_q0(weight_vecs_0_t_q0), + .products_0_address0(tdf2_dot_product_U0_products_0_address0), + .products_0_ce0(tdf2_dot_product_U0_products_0_ce0), + .products_0_we0(tdf2_dot_product_U0_products_0_we0), + .products_0_d0(tdf2_dot_product_U0_products_0_d0) +); + +td_fused_top_tdf2_accum_1 tdf2_accum_1_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf2_accum_1_U0_ap_start), + .ap_done(tdf2_accum_1_U0_ap_done), + .ap_continue(tdf2_accum_1_U0_ap_continue), + .ap_idle(tdf2_accum_1_U0_ap_idle), + .ap_ready(tdf2_accum_1_U0_ap_ready), + .accum_in_0_address0(tdf2_accum_1_U0_accum_in_0_address0), + .accum_in_0_ce0(tdf2_accum_1_U0_accum_in_0_ce0), + .accum_in_0_q0(products_0_t_q0), + .accum_in_0_address1(tdf2_accum_1_U0_accum_in_0_address1), + .accum_in_0_ce1(tdf2_accum_1_U0_accum_in_0_ce1), + .accum_in_0_q1(products_0_t_q1), + .accum_out_address0(tdf2_accum_1_U0_accum_out_address0), + .accum_out_ce0(tdf2_accum_1_U0_accum_out_ce0), + .accum_out_we0(tdf2_accum_1_U0_accum_out_we0), + .accum_out_d0(tdf2_accum_1_U0_accum_out_d0), + .accum_out_address1(tdf2_accum_1_U0_accum_out_address1), + .accum_out_ce1(tdf2_accum_1_U0_accum_out_ce1), + .accum_out_we1(tdf2_accum_1_U0_accum_out_we1), + .accum_out_d1(tdf2_accum_1_U0_accum_out_d1) +); + +td_fused_top_tdf2_accum_2 tdf2_accum_2_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf2_accum_2_U0_ap_start), + .ap_done(tdf2_accum_2_U0_ap_done), + .ap_continue(tdf2_accum_2_U0_ap_continue), + .ap_idle(tdf2_accum_2_U0_ap_idle), + .ap_ready(tdf2_accum_2_U0_ap_ready), + .accum_in_16(tdf2_accum_2_U0_accum_in_16), + .accum_in_16_ap_vld(tdf2_accum_2_U0_accum_in_16_ap_vld), + .accum_in_address0(tdf2_accum_2_U0_accum_in_address0), + .accum_in_ce0(tdf2_accum_2_U0_accum_in_ce0), + .accum_in_q0(accum1_out_0_t_q0) +); + +td_fused_top_Block_entry_proc_proc392 Block_entry_proc_proc392_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(Block_entry_proc_proc392_U0_ap_start), + .ap_done(Block_entry_proc_proc392_U0_ap_done), + .ap_continue(Block_entry_proc_proc392_U0_ap_continue), + .ap_idle(Block_entry_proc_proc392_U0_ap_idle), + .ap_ready(Block_entry_proc_proc392_U0_ap_ready), + .tmp(tmp_channel_dout), + .ap_return(Block_entry_proc_proc392_U0_ap_return) +); + +td_fused_top_tdf2_adjust tdf2_adjust_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf2_adjust_U0_ap_start), + .ap_done(tdf2_adjust_U0_ap_done), + .ap_continue(tdf2_adjust_U0_ap_continue), + .ap_idle(tdf2_adjust_U0_ap_idle), + .ap_ready(tdf2_adjust_U0_ap_ready), + .sums_read(sums_0_dout), + .adjustments_address0(tdf2_adjust_U0_adjustments_address0), + .adjustments_ce0(tdf2_adjust_U0_adjustments_ce0), + .adjustments_q0(adjustments_q0), + .input_indices_23_dout(input_indices_23_c1_dout), + .input_indices_23_empty_n(input_indices_23_c1_empty_n), + .input_indices_23_read(tdf2_adjust_U0_input_indices_23_read), + .ap_return(tdf2_adjust_U0_ap_return) +); + +td_fused_top_tdf2_poolOutputs tdf2_poolOutputs_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf2_poolOutputs_U0_ap_start), + .ap_done(tdf2_poolOutputs_U0_ap_done), + .ap_continue(tdf2_poolOutputs_U0_ap_continue), + .ap_idle(tdf2_poolOutputs_U0_ap_idle), + .ap_ready(tdf2_poolOutputs_U0_ap_ready), + .output_indices_04_dout(output_indices_04_c_dout), + .output_indices_04_empty_n(output_indices_04_c_empty_n), + .output_indices_04_read(tdf2_poolOutputs_U0_output_indices_04_read), + .output_indices_15_dout(output_indices_15_c_dout), + .output_indices_15_empty_n(output_indices_15_c_empty_n), + .output_indices_15_read(tdf2_poolOutputs_U0_output_indices_15_read), + .resetMaximum6_dout(resetMaximum6_c_dout), + .resetMaximum6_empty_n(resetMaximum6_c_empty_n), + .resetMaximum6_read(tdf2_poolOutputs_U0_resetMaximum6_read), + .storeOutput7_dout(storeOutput7_c_dout), + .storeOutput7_empty_n(storeOutput7_c_empty_n), + .storeOutput7_read(tdf2_poolOutputs_U0_storeOutput7_read), + .p_read(outputs_0_dout), + .out_data_address1(tdf2_poolOutputs_U0_out_data_address1), + .out_data_ce1(tdf2_poolOutputs_U0_out_data_ce1), + .out_data_we1(tdf2_poolOutputs_U0_out_data_we1), + .out_data_d1(tdf2_poolOutputs_U0_out_data_d1) +); + +td_fused_top_fifo_w5_d2_S input_indices_23_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_23_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf2_readFilters24_U0_input_indices_23_read), + .if_dout(input_indices_23_c_dout), + .if_full_n(input_indices_23_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf2_get_next_ijk_U0_input_indices_2_out_write), + .if_din(tdf2_get_next_ijk_U0_input_indices_2_out_din) +); + +td_fused_top_fifo_w5_d7_S input_indices_23_c1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_23_c1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf2_adjust_U0_input_indices_23_read), + .if_dout(input_indices_23_c1_dout), + .if_full_n(input_indices_23_c1_full_n), + .if_write_ce(1'b1), + .if_write(tdf2_get_next_ijk_U0_input_indices_2_out1_write), + .if_din(tdf2_get_next_ijk_U0_input_indices_2_out1_din) +); + +td_fused_top_fifo_w6_d8_S output_indices_04_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(output_indices_04_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf2_poolOutputs_U0_output_indices_04_read), + .if_dout(output_indices_04_c_dout), + .if_full_n(output_indices_04_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf2_get_next_ijk_U0_output_indices_0_write), + .if_din(tdf2_get_next_ijk_U0_output_indices_0_din) +); + +td_fused_top_fifo_w12_d8_S output_indices_15_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(output_indices_15_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf2_poolOutputs_U0_output_indices_15_read), + .if_dout(output_indices_15_c_dout), + .if_full_n(output_indices_15_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf2_get_next_ijk_U0_output_indices_1_write), + .if_din(tdf2_get_next_ijk_U0_output_indices_1_din) +); + +td_fused_top_fifo_w1_d8_S resetMaximum6_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(resetMaximum6_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf2_poolOutputs_U0_resetMaximum6_read), + .if_dout(resetMaximum6_c_dout), + .if_full_n(resetMaximum6_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf2_get_next_ijk_U0_resetMaximum_write), + .if_din(resetMaximum6_c_din) +); + +td_fused_top_fifo_w1_d8_S storeOutput7_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(storeOutput7_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf2_poolOutputs_U0_storeOutput7_read), + .if_dout(storeOutput7_c_dout), + .if_full_n(storeOutput7_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf2_get_next_ijk_U0_storeOutput_write), + .if_din(storeOutput7_c_din) +); + +td_fused_top_fifo_w16_d2_S_x input_indices_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf2_readInputs25_U0_ap_ready), + .if_dout(input_indices_0_dout), + .if_full_n(input_indices_0_full_n), + .if_write_ce(1'b1), + .if_write(ap_channel_done_input_indices_0), + .if_din(tdf2_get_next_ijk_U0_ap_return_0) +); + +td_fused_top_fifo_w16_d2_S_x input_indices_1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf2_readInputs25_U0_ap_ready), + .if_dout(input_indices_1_dout), + .if_full_n(input_indices_1_full_n), + .if_write_ce(1'b1), + .if_write(ap_channel_done_input_indices_1), + .if_din(tdf2_get_next_ijk_U0_ap_return_1) +); + +td_fused_top_fifo_w16_d2_S_x tmp_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(tmp_channel_empty_n), + .if_read_ce(1'b1), + .if_read(Block_entry_proc_proc392_U0_ap_ready), + .if_dout(tmp_channel_dout), + .if_full_n(tmp_channel_full_n), + .if_write_ce(1'b1), + .if_write(tdf2_accum_2_U0_ap_done), + .if_din(tdf2_accum_2_U0_accum_in_16) +); + +td_fused_top_fifo_w16_d2_S_x sums_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(sums_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf2_adjust_U0_ap_ready), + .if_dout(sums_0_dout), + .if_full_n(sums_0_full_n), + .if_write_ce(1'b1), + .if_write(Block_entry_proc_proc392_U0_ap_done), + .if_din(Block_entry_proc_proc392_U0_ap_return) +); + +td_fused_top_fifo_w16_d2_S_x outputs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(outputs_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf2_poolOutputs_U0_ap_ready), + .if_dout(outputs_0_dout), + .if_full_n(outputs_0_full_n), + .if_write_ce(1'b1), + .if_write(tdf2_adjust_U0_ap_done), + .if_din(tdf2_adjust_U0_ap_return) +); + +td_fused_top_start_for_tdf2_readFilters24_U0 start_for_tdf2_readFilters24_U0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(start_for_tdf2_readFilters24_U0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf2_readFilters24_U0_ap_ready), + .if_dout(start_for_tdf2_readFilters24_U0_dout), + .if_full_n(start_for_tdf2_readFilters24_U0_full_n), + .if_write_ce(1'b1), + .if_write(tdf2_get_next_ijk_U0_start_write), + .if_din(start_for_tdf2_readFilters24_U0_din) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_input_indices_0 <= 1'b0; + end else begin + if (((tdf2_get_next_ijk_U0_ap_done & tdf2_get_next_ijk_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_input_indices_0 <= 1'b0; + end else begin + ap_sync_reg_channel_write_input_indices_0 <= ap_sync_channel_write_input_indices_0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_input_indices_1 <= 1'b0; + end else begin + if (((tdf2_get_next_ijk_U0_ap_done & tdf2_get_next_ijk_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_input_indices_1 <= 1'b0; + end else begin + ap_sync_reg_channel_write_input_indices_1 <= ap_sync_channel_write_input_indices_1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf2_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf2_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf2_get_next_ijk_U0_ap_ready <= ap_sync_tdf2_get_next_ijk_U0_ap_ready; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf2_readInputs25_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf2_readInputs25_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf2_readInputs25_U0_ap_ready <= ap_sync_tdf2_readInputs25_U0_ap_ready; + end + end +end + +assign Block_entry_proc_proc392_U0_ap_continue = sums_0_full_n; + +assign Block_entry_proc_proc392_U0_ap_start = tmp_channel_empty_n; + +assign Block_entry_proc_proc392_U0_start_full_n = 1'b1; + +assign Block_entry_proc_proc392_U0_start_write = 1'b0; + +assign adjustments_address0 = tdf2_adjust_U0_adjustments_address0; + +assign adjustments_address1 = 5'd0; + +assign adjustments_ce0 = tdf2_adjust_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_channel_done_accum1_out_0 = tdf2_accum_1_U0_ap_done; + +assign ap_channel_done_ifmap_vec = tdf2_readInputs25_U0_ap_done; + +assign ap_channel_done_input_indices_0 = (tdf2_get_next_ijk_U0_ap_done & (ap_sync_reg_channel_write_input_indices_0 ^ 1'b1)); + +assign ap_channel_done_input_indices_1 = (tdf2_get_next_ijk_U0_ap_done & (ap_sync_reg_channel_write_input_indices_1 ^ 1'b1)); + +assign ap_channel_done_outputs_0 = tdf2_adjust_U0_ap_done; + +assign ap_channel_done_products_0 = tdf2_dot_product_U0_ap_done; + +assign ap_channel_done_sums_0 = Block_entry_proc_proc392_U0_ap_done; + +assign ap_channel_done_tmp_channel = tdf2_accum_2_U0_ap_done; + +assign ap_channel_done_weight_vecs_0 = tdf2_readFilters24_U0_ap_done; + +assign ap_done = tdf2_poolOutputs_U0_ap_done; + +assign ap_idle = (tdf2_readInputs25_U0_ap_idle & tdf2_readFilters24_U0_ap_idle & tdf2_poolOutputs_U0_ap_idle & tdf2_get_next_ijk_U0_ap_idle & tdf2_dot_product_U0_ap_idle & tdf2_adjust_U0_ap_idle & tdf2_accum_2_U0_ap_idle & tdf2_accum_1_U0_ap_idle & (outputs_0_empty_n ^ 1'b1) & (sums_0_empty_n ^ 1'b1) & (tmp_channel_empty_n ^ 1'b1) & (input_indices_1_empty_n ^ 1'b1) & (input_indices_0_empty_n ^ 1'b1) & (products_0_t_empty_n ^ 1'b1) & (weight_vecs_0_t_empty_n ^ 1'b1) & (ifmap_vec_t_empty_n ^ 1'b1) & (1'b1 ^ accum1_out_0_t_empty_n) & Block_entry_proc_proc392_U0_ap_idle); + +assign ap_ready = ap_sync_ready; + +assign ap_sync_channel_write_input_indices_0 = ((input_indices_0_full_n & ap_channel_done_input_indices_0) | ap_sync_reg_channel_write_input_indices_0); + +assign ap_sync_channel_write_input_indices_1 = ((input_indices_1_full_n & ap_channel_done_input_indices_1) | ap_sync_reg_channel_write_input_indices_1); + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = tdf2_poolOutputs_U0_ap_done; + +assign ap_sync_ready = (ap_sync_tdf2_readInputs25_U0_ap_ready & ap_sync_tdf2_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf2_get_next_ijk_U0_ap_ready = (tdf2_get_next_ijk_U0_ap_ready | ap_sync_reg_tdf2_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf2_readInputs25_U0_ap_ready = (tdf2_readInputs25_U0_ap_ready | ap_sync_reg_tdf2_readInputs25_U0_ap_ready); + +assign filter_data_address0 = tdf2_readFilters24_U0_filter_data_address0; + +assign filter_data_address1 = 13'd0; + +assign filter_data_ce0 = tdf2_readFilters24_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = tdf2_readInputs25_U0_in_data_address0; + +assign in_data_address1 = 16'd0; + +assign in_data_ce0 = tdf2_readInputs25_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = tdf2_readInputs25_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 15'd0; + +assign out_data_address1 = tdf2_poolOutputs_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = tdf2_poolOutputs_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = tdf2_poolOutputs_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = tdf2_poolOutputs_U0_out_data_we1; + +assign out_data_write = tdf2_poolOutputs_U0_out_data_write; + +assign products_0_t_d1 = 16'd0; + +assign products_0_t_we1 = 1'b0; + +assign resetMaximum6_c_din = tdf2_get_next_ijk_U0_resetMaximum_din; + +assign start_for_tdf2_readFilters24_U0_din = 1'b1; + +assign storeOutput7_c_din = tdf2_get_next_ijk_U0_storeOutput_din; + +assign tdf2_accum_1_U0_accum_out_full_n = accum1_out_0_i_full_n; + +assign tdf2_accum_1_U0_ap_continue = accum1_out_0_i_full_n; + +assign tdf2_accum_1_U0_ap_start = products_0_t_empty_n; + +assign tdf2_accum_1_U0_start_full_n = 1'b1; + +assign tdf2_accum_1_U0_start_write = 1'b0; + +assign tdf2_accum_2_U0_ap_continue = tmp_channel_full_n; + +assign tdf2_accum_2_U0_ap_start = accum1_out_0_t_empty_n; + +assign tdf2_accum_2_U0_start_full_n = 1'b1; + +assign tdf2_accum_2_U0_start_write = 1'b0; + +assign tdf2_adjust_U0_ap_continue = outputs_0_full_n; + +assign tdf2_adjust_U0_ap_start = sums_0_empty_n; + +assign tdf2_adjust_U0_start_full_n = 1'b1; + +assign tdf2_adjust_U0_start_write = 1'b0; + +assign tdf2_dot_product_U0_ap_continue = products_0_i_full_n; + +assign tdf2_dot_product_U0_ap_start = (weight_vecs_0_t_empty_n & ifmap_vec_t_empty_n); + +assign tdf2_dot_product_U0_products_0_full_n = products_0_i_full_n; + +assign tdf2_dot_product_U0_start_full_n = 1'b1; + +assign tdf2_dot_product_U0_start_write = 1'b0; + +assign tdf2_get_next_ijk_U0_ap_continue = (ap_sync_channel_write_input_indices_1 & ap_sync_channel_write_input_indices_0); + +assign tdf2_get_next_ijk_U0_ap_start = ((ap_sync_reg_tdf2_get_next_ijk_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf2_poolOutputs_U0_ap_continue = ap_continue; + +assign tdf2_poolOutputs_U0_ap_start = outputs_0_empty_n; + +assign tdf2_poolOutputs_U0_out_data_full_n = out_data_full_n; + +assign tdf2_poolOutputs_U0_out_data_write = 1'b0; + +assign tdf2_poolOutputs_U0_start_full_n = 1'b1; + +assign tdf2_poolOutputs_U0_start_write = 1'b0; + +assign tdf2_readFilters24_U0_ap_continue = weight_vecs_0_i_full_n; + +assign tdf2_readFilters24_U0_ap_start = start_for_tdf2_readFilters24_U0_empty_n; + +assign tdf2_readFilters24_U0_start_full_n = 1'b1; + +assign tdf2_readFilters24_U0_start_write = 1'b0; + +assign tdf2_readFilters24_U0_weight_vecs_0_full_n = weight_vecs_0_i_full_n; + +assign tdf2_readInputs25_U0_ap_continue = ifmap_vec_i_full_n; + +assign tdf2_readInputs25_U0_ap_start = (input_indices_1_empty_n & input_indices_0_empty_n & (ap_sync_reg_tdf2_readInputs25_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf2_readInputs25_U0_ifmap_vec_full_n = ifmap_vec_i_full_n; + +assign tdf2_readInputs25_U0_in_data_full_n = in_data_empty_n; + +assign tdf2_readInputs25_U0_in_data_write = 1'b0; + +assign tdf2_readInputs25_U0_start_full_n = 1'b1; + +assign tdf2_readInputs25_U0_start_write = 1'b0; + +endmodule //td_fused_top_dataflow_in_loop_TOP_LOOP38022 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38022_weight_vecs_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 9; +parameter MEM_SIZE = 288; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38022_weight_vecs_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd288; +parameter AddressWidth = 32'd9; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38022_weight_vecs_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38022_weight_vecs_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38022_weight_vecs_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 8, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP38022_weight_vecs_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38022_weight_vecs_0_memcore_U ( + .reset ( reset ), + .clk ( clk ), + .address0 ( memcore_iaddr ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + .address1 ( memcore_taddr ), + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .d1 ( t_d0 ), + .q1 ( t_q0 ) + +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 4; +parameter MEM_SIZE = 14; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd14; +parameter AddressWidth = 32'd4; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 4, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire [AddressWidth-1:0] i_address1, + output wire [DataWidth-1:0] i_q1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire [AddressWidth-1:0] t_address1, + output wire [DataWidth-1:0] t_q1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_q1_0, buf_q1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .q1 ( buf_q1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .q1 ( buf_q1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign i_q1 = (prev_iptr == 1'b1 ? buf_q1_1 : buf_q1_0); +assign t_q1 = reg_valid1 ? reg_q1 : (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// reg_q1 and reg_valid1 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q1 <= 1'b0; + reg_valid1 <= 1'b0; + end else if (!t_ce1 && !reg_valid1) begin + reg_q1 <= (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + reg_valid1 <= 1'b1; + end else if (t_ce1) begin + reg_valid1 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 4; +parameter MEM_SIZE = 14; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd14; +parameter AddressWidth = 32'd4; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 3, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0_memcore_U ( + .reset ( reset ), + .clk ( clk ), + .address0 ( memcore_iaddr ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + .address1 ( memcore_taddr ), + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .d1 ( t_d0 ), + .q1 ( t_q0 ) + +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 6; +parameter MEM_SIZE = 54; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd54; +parameter AddressWidth = 32'd6; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 5, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec_memcore_U ( + .reset ( reset ), + .clk ( clk ), + .address0 ( memcore_iaddr ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + .address1 ( memcore_taddr ), + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .d1 ( t_d0 ), + .q1 ( t_q0 ) + +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 5; +parameter MEM_SIZE = 27; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd27; +parameter AddressWidth = 32'd5; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 5, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire [AddressWidth-1:0] i_address1, + output wire [DataWidth-1:0] i_q1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire [AddressWidth-1:0] t_address1, + output wire [DataWidth-1:0] t_q1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_q1_0, buf_q1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .q1 ( buf_q1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .q1 ( buf_q1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign i_q1 = (prev_iptr == 1'b1 ? buf_q1_1 : buf_q1_0); +assign t_q1 = reg_valid1 ? reg_q1 : (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// reg_q1 and reg_valid1 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q1 <= 1'b0; + reg_valid1 <= 1'b0; + end else if (!t_ce1 && !reg_valid1) begin + reg_q1 <= (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + reg_valid1 <= 1'b1; + end else if (t_ce1) begin + reg_valid1 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38116 ( + ap_clk, + ap_rst, + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + ap_start, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +input ap_clk; +input ap_rst; +output [15:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [15:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [8:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [8:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [3:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [3:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +output [15:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [15:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +input ap_start; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +wire [15:0] ifmap_vec_i_q0; +wire [15:0] ifmap_vec_t_q0; +wire [15:0] weight_vecs_0_i_q0; +wire [15:0] weight_vecs_0_t_q0; +wire [15:0] products_0_i_q0; +wire [15:0] products_0_i_q1; +wire [15:0] products_0_t_q0; +wire [15:0] products_0_t_q1; +wire [15:0] accum1_out_0_i_q0; +wire [15:0] accum1_out_0_i_q1; +wire [15:0] accum1_out_0_t_q0; +wire [15:0] accum1_out_0_t_q1; +wire [15:0] accum2_out_0_i_q0; +wire [15:0] accum2_out_0_t_q0; +wire tdf1_get_next_ijk_U0_ap_start; +wire tdf1_get_next_ijk_U0_ap_done; +wire tdf1_get_next_ijk_U0_ap_continue; +wire tdf1_get_next_ijk_U0_ap_idle; +wire tdf1_get_next_ijk_U0_ap_ready; +wire tdf1_get_next_ijk_U0_start_out; +wire tdf1_get_next_ijk_U0_start_write; +wire [3:0] tdf1_get_next_ijk_U0_input_indices_2_out_din; +wire tdf1_get_next_ijk_U0_input_indices_2_out_write; +wire [3:0] tdf1_get_next_ijk_U0_input_indices_2_out1_din; +wire tdf1_get_next_ijk_U0_input_indices_2_out1_write; +wire [6:0] tdf1_get_next_ijk_U0_output_indices_0_din; +wire tdf1_get_next_ijk_U0_output_indices_0_write; +wire [13:0] tdf1_get_next_ijk_U0_output_indices_1_din; +wire tdf1_get_next_ijk_U0_output_indices_1_write; +wire tdf1_get_next_ijk_U0_resetMaximum_din; +wire tdf1_get_next_ijk_U0_resetMaximum_write; +wire tdf1_get_next_ijk_U0_storeOutput_din; +wire tdf1_get_next_ijk_U0_storeOutput_write; +wire [15:0] tdf1_get_next_ijk_U0_ap_return_0; +wire [15:0] tdf1_get_next_ijk_U0_ap_return_1; +wire ap_channel_done_input_indices_1; +wire input_indices_1_full_n; +reg ap_sync_reg_channel_write_input_indices_1; +wire ap_sync_channel_write_input_indices_1; +wire ap_channel_done_input_indices_0; +wire input_indices_0_full_n; +reg ap_sync_reg_channel_write_input_indices_0; +wire ap_sync_channel_write_input_indices_0; +wire tdf1_readInputs19_U0_ap_start; +wire tdf1_readInputs19_U0_ap_done; +wire tdf1_readInputs19_U0_ap_continue; +wire tdf1_readInputs19_U0_ap_idle; +wire tdf1_readInputs19_U0_ap_ready; +wire [15:0] tdf1_readInputs19_U0_in_data_address0; +wire tdf1_readInputs19_U0_in_data_ce0; +wire [4:0] tdf1_readInputs19_U0_ifmap_vec_address0; +wire tdf1_readInputs19_U0_ifmap_vec_ce0; +wire tdf1_readInputs19_U0_ifmap_vec_we0; +wire [15:0] tdf1_readInputs19_U0_ifmap_vec_d0; +wire tdf1_readInputs19_U0_in_data_full_n; +wire tdf1_readInputs19_U0_in_data_write; +wire ap_channel_done_ifmap_vec; +wire tdf1_readInputs19_U0_ifmap_vec_full_n; +wire tdf1_readFilters18_U0_ap_start; +wire tdf1_readFilters18_U0_ap_done; +wire tdf1_readFilters18_U0_ap_continue; +wire tdf1_readFilters18_U0_ap_idle; +wire tdf1_readFilters18_U0_ap_ready; +wire [8:0] tdf1_readFilters18_U0_filter_data_address0; +wire tdf1_readFilters18_U0_filter_data_ce0; +wire tdf1_readFilters18_U0_input_indices_23_read; +wire [4:0] tdf1_readFilters18_U0_weight_vecs_0_address0; +wire tdf1_readFilters18_U0_weight_vecs_0_ce0; +wire tdf1_readFilters18_U0_weight_vecs_0_we0; +wire [15:0] tdf1_readFilters18_U0_weight_vecs_0_d0; +wire ap_channel_done_weight_vecs_0; +wire tdf1_readFilters18_U0_weight_vecs_0_full_n; +wire tdf1_dot_product_U0_ap_start; +wire tdf1_dot_product_U0_ap_done; +wire tdf1_dot_product_U0_ap_continue; +wire tdf1_dot_product_U0_ap_idle; +wire tdf1_dot_product_U0_ap_ready; +wire [4:0] tdf1_dot_product_U0_ifmap_vec_address0; +wire tdf1_dot_product_U0_ifmap_vec_ce0; +wire [4:0] tdf1_dot_product_U0_weight_vecs_0_address0; +wire tdf1_dot_product_U0_weight_vecs_0_ce0; +wire [4:0] tdf1_dot_product_U0_products_0_address0; +wire tdf1_dot_product_U0_products_0_ce0; +wire tdf1_dot_product_U0_products_0_we0; +wire [15:0] tdf1_dot_product_U0_products_0_d0; +wire ap_channel_done_products_0; +wire tdf1_dot_product_U0_products_0_full_n; +wire tdf1_accum_1_U0_ap_start; +wire tdf1_accum_1_U0_ap_done; +wire tdf1_accum_1_U0_ap_continue; +wire tdf1_accum_1_U0_ap_idle; +wire tdf1_accum_1_U0_ap_ready; +wire [4:0] tdf1_accum_1_U0_accum_in_0_address0; +wire tdf1_accum_1_U0_accum_in_0_ce0; +wire [4:0] tdf1_accum_1_U0_accum_in_0_address1; +wire tdf1_accum_1_U0_accum_in_0_ce1; +wire [3:0] tdf1_accum_1_U0_accum_out_address0; +wire tdf1_accum_1_U0_accum_out_ce0; +wire tdf1_accum_1_U0_accum_out_we0; +wire [15:0] tdf1_accum_1_U0_accum_out_d0; +wire ap_channel_done_accum1_out_0; +wire tdf1_accum_1_U0_accum_out_full_n; +wire tdf1_accum_2_U0_ap_start; +wire tdf1_accum_2_U0_ap_done; +wire tdf1_accum_2_U0_ap_continue; +wire tdf1_accum_2_U0_ap_idle; +wire tdf1_accum_2_U0_ap_ready; +wire [3:0] tdf1_accum_2_U0_accum_in_address0; +wire tdf1_accum_2_U0_accum_in_ce0; +wire [3:0] tdf1_accum_2_U0_accum_in_address1; +wire tdf1_accum_2_U0_accum_in_ce1; +wire [2:0] tdf1_accum_2_U0_accum_out_address0; +wire tdf1_accum_2_U0_accum_out_ce0; +wire tdf1_accum_2_U0_accum_out_we0; +wire [15:0] tdf1_accum_2_U0_accum_out_d0; +wire ap_channel_done_accum2_out_0; +wire tdf1_accum_2_U0_accum_out_full_n; +wire tdf1_accum_3_U0_ap_start; +wire tdf1_accum_3_U0_ap_done; +wire tdf1_accum_3_U0_ap_continue; +wire tdf1_accum_3_U0_ap_idle; +wire tdf1_accum_3_U0_ap_ready; +wire [15:0] tdf1_accum_3_U0_accum_in_18; +wire tdf1_accum_3_U0_accum_in_18_ap_vld; +wire [2:0] tdf1_accum_3_U0_accum_in_address0; +wire tdf1_accum_3_U0_accum_in_ce0; +wire ap_channel_done_tmp_channel; +wire tmp_channel_full_n; +wire Block_entry_proc_proc_U0_ap_start; +wire Block_entry_proc_proc_U0_ap_done; +wire Block_entry_proc_proc_U0_ap_continue; +wire Block_entry_proc_proc_U0_ap_idle; +wire Block_entry_proc_proc_U0_ap_ready; +wire [15:0] Block_entry_proc_proc_U0_ap_return; +wire ap_channel_done_sums_0; +wire sums_0_full_n; +wire tdf1_adjust_U0_ap_start; +wire tdf1_adjust_U0_ap_done; +wire tdf1_adjust_U0_ap_continue; +wire tdf1_adjust_U0_ap_idle; +wire tdf1_adjust_U0_ap_ready; +wire [3:0] tdf1_adjust_U0_adjustments_address0; +wire tdf1_adjust_U0_adjustments_ce0; +wire tdf1_adjust_U0_input_indices_23_read; +wire [15:0] tdf1_adjust_U0_ap_return; +wire ap_channel_done_outputs_0; +wire outputs_0_full_n; +wire tdf1_poolOutputs_U0_ap_start; +wire tdf1_poolOutputs_U0_ap_done; +wire tdf1_poolOutputs_U0_ap_continue; +wire tdf1_poolOutputs_U0_ap_idle; +wire tdf1_poolOutputs_U0_ap_ready; +wire tdf1_poolOutputs_U0_output_indices_04_read; +wire tdf1_poolOutputs_U0_output_indices_15_read; +wire tdf1_poolOutputs_U0_resetMaximum6_read; +wire tdf1_poolOutputs_U0_storeOutput7_read; +wire [15:0] tdf1_poolOutputs_U0_out_data_address1; +wire tdf1_poolOutputs_U0_out_data_ce1; +wire tdf1_poolOutputs_U0_out_data_we1; +wire [63:0] tdf1_poolOutputs_U0_out_data_d1; +wire tdf1_poolOutputs_U0_out_data_full_n; +wire tdf1_poolOutputs_U0_out_data_write; +wire ap_sync_continue; +wire ifmap_vec_i_full_n; +wire ifmap_vec_t_empty_n; +wire weight_vecs_0_i_full_n; +wire weight_vecs_0_t_empty_n; +wire products_0_i_full_n; +wire products_0_t_empty_n; +wire [15:0] products_0_t_d1; +wire products_0_t_we1; +wire accum1_out_0_i_full_n; +wire accum1_out_0_t_empty_n; +wire [15:0] accum1_out_0_t_d1; +wire accum1_out_0_t_we1; +wire accum2_out_0_i_full_n; +wire accum2_out_0_t_empty_n; +wire input_indices_23_c_full_n; +wire [3:0] input_indices_23_c_dout; +wire input_indices_23_c_empty_n; +wire input_indices_23_c1_full_n; +wire [3:0] input_indices_23_c1_dout; +wire input_indices_23_c1_empty_n; +wire output_indices_04_c_full_n; +wire [6:0] output_indices_04_c_dout; +wire output_indices_04_c_empty_n; +wire output_indices_15_c_full_n; +wire [13:0] output_indices_15_c_dout; +wire output_indices_15_c_empty_n; +wire [0:0] resetMaximum6_c_din; +wire resetMaximum6_c_full_n; +wire [0:0] resetMaximum6_c_dout; +wire resetMaximum6_c_empty_n; +wire [0:0] storeOutput7_c_din; +wire storeOutput7_c_full_n; +wire [0:0] storeOutput7_c_dout; +wire storeOutput7_c_empty_n; +wire [15:0] input_indices_0_dout; +wire input_indices_0_empty_n; +wire [15:0] input_indices_1_dout; +wire input_indices_1_empty_n; +wire [15:0] tmp_channel_dout; +wire tmp_channel_empty_n; +wire [15:0] sums_0_dout; +wire sums_0_empty_n; +wire [15:0] outputs_0_dout; +wire outputs_0_empty_n; +wire ap_sync_done; +wire ap_sync_ready; +reg ap_sync_reg_tdf1_get_next_ijk_U0_ap_ready; +wire ap_sync_tdf1_get_next_ijk_U0_ap_ready; +reg ap_sync_reg_tdf1_readInputs19_U0_ap_ready; +wire ap_sync_tdf1_readInputs19_U0_ap_ready; +wire [0:0] start_for_tdf1_readFilters18_U0_din; +wire start_for_tdf1_readFilters18_U0_full_n; +wire [0:0] start_for_tdf1_readFilters18_U0_dout; +wire start_for_tdf1_readFilters18_U0_empty_n; +wire tdf1_readInputs19_U0_start_full_n; +wire tdf1_readInputs19_U0_start_write; +wire tdf1_readFilters18_U0_start_full_n; +wire tdf1_readFilters18_U0_start_write; +wire tdf1_dot_product_U0_start_full_n; +wire tdf1_dot_product_U0_start_write; +wire tdf1_accum_1_U0_start_full_n; +wire tdf1_accum_1_U0_start_write; +wire tdf1_accum_2_U0_start_full_n; +wire tdf1_accum_2_U0_start_write; +wire tdf1_accum_3_U0_start_full_n; +wire tdf1_accum_3_U0_start_write; +wire Block_entry_proc_proc_U0_start_full_n; +wire Block_entry_proc_proc_U0_start_write; +wire tdf1_adjust_U0_start_full_n; +wire tdf1_adjust_U0_start_write; +wire tdf1_poolOutputs_U0_start_full_n; +wire tdf1_poolOutputs_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_sync_reg_channel_write_input_indices_1 = 1'b0; +#0 ap_sync_reg_channel_write_input_indices_0 = 1'b0; +#0 ap_sync_reg_tdf1_get_next_ijk_U0_ap_ready = 1'b0; +#0 ap_sync_reg_tdf1_readInputs19_U0_ap_ready = 1'b0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec #( + .DataWidth( 16 ), + .AddressRange( 27 ), + .AddressWidth( 5 )) +ifmap_vec_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf1_readInputs19_U0_ap_done), + .i_full_n(ifmap_vec_i_full_n), + .i_ce0(tdf1_readInputs19_U0_ifmap_vec_ce0), + .i_we0(tdf1_readInputs19_U0_ifmap_vec_we0), + .i_address0(tdf1_readInputs19_U0_ifmap_vec_address0), + .i_d0(tdf1_readInputs19_U0_ifmap_vec_d0), + .i_q0(ifmap_vec_i_q0), + .t_ce(1'b1), + .t_read(tdf1_dot_product_U0_ap_ready), + .t_empty_n(ifmap_vec_t_empty_n), + .t_ce0(tdf1_dot_product_U0_ifmap_vec_ce0), + .t_we0(1'b0), + .t_address0(tdf1_dot_product_U0_ifmap_vec_address0), + .t_d0(16'd0), + .t_q0(ifmap_vec_t_q0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec #( + .DataWidth( 16 ), + .AddressRange( 27 ), + .AddressWidth( 5 )) +weight_vecs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf1_readFilters18_U0_ap_done), + .i_full_n(weight_vecs_0_i_full_n), + .i_ce0(tdf1_readFilters18_U0_weight_vecs_0_ce0), + .i_we0(tdf1_readFilters18_U0_weight_vecs_0_we0), + .i_address0(tdf1_readFilters18_U0_weight_vecs_0_address0), + .i_d0(tdf1_readFilters18_U0_weight_vecs_0_d0), + .i_q0(weight_vecs_0_i_q0), + .t_ce(1'b1), + .t_read(tdf1_dot_product_U0_ap_ready), + .t_empty_n(weight_vecs_0_t_empty_n), + .t_ce0(tdf1_dot_product_U0_weight_vecs_0_ce0), + .t_we0(1'b0), + .t_address0(tdf1_dot_product_U0_weight_vecs_0_address0), + .t_d0(16'd0), + .t_q0(weight_vecs_0_t_q0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0 #( + .DataWidth( 16 ), + .AddressRange( 27 ), + .AddressWidth( 5 )) +products_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf1_dot_product_U0_ap_done), + .i_full_n(products_0_i_full_n), + .i_ce0(tdf1_dot_product_U0_products_0_ce0), + .i_we0(tdf1_dot_product_U0_products_0_we0), + .i_address0(tdf1_dot_product_U0_products_0_address0), + .i_d0(tdf1_dot_product_U0_products_0_d0), + .i_q0(products_0_i_q0), + .i_ce1(1'b0), + .i_address1(5'd0), + .i_q1(products_0_i_q1), + .t_ce(1'b1), + .t_read(tdf1_accum_1_U0_ap_ready), + .t_empty_n(products_0_t_empty_n), + .t_ce0(tdf1_accum_1_U0_accum_in_0_ce0), + .t_we0(1'b0), + .t_address0(tdf1_accum_1_U0_accum_in_0_address0), + .t_d0(16'd0), + .t_q0(products_0_t_q0), + .t_ce1(tdf1_accum_1_U0_accum_in_0_ce1), + .t_address1(tdf1_accum_1_U0_accum_in_0_address1), + .t_q1(products_0_t_q1) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0 #( + .DataWidth( 16 ), + .AddressRange( 14 ), + .AddressWidth( 4 )) +accum1_out_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf1_accum_1_U0_ap_done), + .i_full_n(accum1_out_0_i_full_n), + .i_ce0(tdf1_accum_1_U0_accum_out_ce0), + .i_we0(tdf1_accum_1_U0_accum_out_we0), + .i_address0(tdf1_accum_1_U0_accum_out_address0), + .i_d0(tdf1_accum_1_U0_accum_out_d0), + .i_q0(accum1_out_0_i_q0), + .i_ce1(1'b0), + .i_address1(4'd0), + .i_q1(accum1_out_0_i_q1), + .t_ce(1'b1), + .t_read(tdf1_accum_2_U0_ap_ready), + .t_empty_n(accum1_out_0_t_empty_n), + .t_ce0(tdf1_accum_2_U0_accum_in_ce0), + .t_we0(1'b0), + .t_address0(tdf1_accum_2_U0_accum_in_address0), + .t_d0(16'd0), + .t_q0(accum1_out_0_t_q0), + .t_ce1(tdf1_accum_2_U0_accum_in_ce1), + .t_address1(tdf1_accum_2_U0_accum_in_address1), + .t_q1(accum1_out_0_t_q1) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0 #( + .DataWidth( 16 ), + .AddressRange( 7 ), + .AddressWidth( 3 )) +accum2_out_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf1_accum_2_U0_ap_done), + .i_full_n(accum2_out_0_i_full_n), + .i_ce0(tdf1_accum_2_U0_accum_out_ce0), + .i_we0(tdf1_accum_2_U0_accum_out_we0), + .i_address0(tdf1_accum_2_U0_accum_out_address0), + .i_d0(tdf1_accum_2_U0_accum_out_d0), + .i_q0(accum2_out_0_i_q0), + .t_ce(1'b1), + .t_read(tdf1_accum_3_U0_ap_ready), + .t_empty_n(accum2_out_0_t_empty_n), + .t_ce0(tdf1_accum_3_U0_accum_in_ce0), + .t_we0(1'b0), + .t_address0(tdf1_accum_3_U0_accum_in_address0), + .t_d0(16'd0), + .t_q0(accum2_out_0_t_q0) +); + +td_fused_top_tdf1_get_next_ijk tdf1_get_next_ijk_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf1_get_next_ijk_U0_ap_start), + .start_full_n(start_for_tdf1_readFilters18_U0_full_n), + .ap_done(tdf1_get_next_ijk_U0_ap_done), + .ap_continue(tdf1_get_next_ijk_U0_ap_continue), + .ap_idle(tdf1_get_next_ijk_U0_ap_idle), + .ap_ready(tdf1_get_next_ijk_U0_ap_ready), + .start_out(tdf1_get_next_ijk_U0_start_out), + .start_write(tdf1_get_next_ijk_U0_start_write), + .input_indices_2_out_din(tdf1_get_next_ijk_U0_input_indices_2_out_din), + .input_indices_2_out_full_n(input_indices_23_c_full_n), + .input_indices_2_out_write(tdf1_get_next_ijk_U0_input_indices_2_out_write), + .input_indices_2_out1_din(tdf1_get_next_ijk_U0_input_indices_2_out1_din), + .input_indices_2_out1_full_n(input_indices_23_c1_full_n), + .input_indices_2_out1_write(tdf1_get_next_ijk_U0_input_indices_2_out1_write), + .output_indices_0_din(tdf1_get_next_ijk_U0_output_indices_0_din), + .output_indices_0_full_n(output_indices_04_c_full_n), + .output_indices_0_write(tdf1_get_next_ijk_U0_output_indices_0_write), + .output_indices_1_din(tdf1_get_next_ijk_U0_output_indices_1_din), + .output_indices_1_full_n(output_indices_15_c_full_n), + .output_indices_1_write(tdf1_get_next_ijk_U0_output_indices_1_write), + .resetMaximum_din(tdf1_get_next_ijk_U0_resetMaximum_din), + .resetMaximum_full_n(resetMaximum6_c_full_n), + .resetMaximum_write(tdf1_get_next_ijk_U0_resetMaximum_write), + .storeOutput_din(tdf1_get_next_ijk_U0_storeOutput_din), + .storeOutput_full_n(storeOutput7_c_full_n), + .storeOutput_write(tdf1_get_next_ijk_U0_storeOutput_write), + .ap_return_0(tdf1_get_next_ijk_U0_ap_return_0), + .ap_return_1(tdf1_get_next_ijk_U0_ap_return_1) +); + +td_fused_top_tdf1_readInputs19 tdf1_readInputs19_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf1_readInputs19_U0_ap_start), + .ap_done(tdf1_readInputs19_U0_ap_done), + .ap_continue(tdf1_readInputs19_U0_ap_continue), + .ap_idle(tdf1_readInputs19_U0_ap_idle), + .ap_ready(tdf1_readInputs19_U0_ap_ready), + .in_data_address0(tdf1_readInputs19_U0_in_data_address0), + .in_data_ce0(tdf1_readInputs19_U0_in_data_ce0), + .in_data_q0(in_data_q0), + .i_19(input_indices_0_dout), + .j_19(input_indices_1_dout), + .ifmap_vec_address0(tdf1_readInputs19_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf1_readInputs19_U0_ifmap_vec_ce0), + .ifmap_vec_we0(tdf1_readInputs19_U0_ifmap_vec_we0), + .ifmap_vec_d0(tdf1_readInputs19_U0_ifmap_vec_d0) +); + +td_fused_top_tdf1_readFilters18 tdf1_readFilters18_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf1_readFilters18_U0_ap_start), + .ap_done(tdf1_readFilters18_U0_ap_done), + .ap_continue(tdf1_readFilters18_U0_ap_continue), + .ap_idle(tdf1_readFilters18_U0_ap_idle), + .ap_ready(tdf1_readFilters18_U0_ap_ready), + .filter_data_address0(tdf1_readFilters18_U0_filter_data_address0), + .filter_data_ce0(tdf1_readFilters18_U0_filter_data_ce0), + .filter_data_q0(filter_data_q0), + .input_indices_23_dout(input_indices_23_c_dout), + .input_indices_23_empty_n(input_indices_23_c_empty_n), + .input_indices_23_read(tdf1_readFilters18_U0_input_indices_23_read), + .weight_vecs_0_address0(tdf1_readFilters18_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf1_readFilters18_U0_weight_vecs_0_ce0), + .weight_vecs_0_we0(tdf1_readFilters18_U0_weight_vecs_0_we0), + .weight_vecs_0_d0(tdf1_readFilters18_U0_weight_vecs_0_d0) +); + +td_fused_top_tdf1_dot_product tdf1_dot_product_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf1_dot_product_U0_ap_start), + .ap_done(tdf1_dot_product_U0_ap_done), + .ap_continue(tdf1_dot_product_U0_ap_continue), + .ap_idle(tdf1_dot_product_U0_ap_idle), + .ap_ready(tdf1_dot_product_U0_ap_ready), + .ifmap_vec_address0(tdf1_dot_product_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf1_dot_product_U0_ifmap_vec_ce0), + .ifmap_vec_q0(ifmap_vec_t_q0), + .weight_vecs_0_address0(tdf1_dot_product_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf1_dot_product_U0_weight_vecs_0_ce0), + .weight_vecs_0_q0(weight_vecs_0_t_q0), + .products_0_address0(tdf1_dot_product_U0_products_0_address0), + .products_0_ce0(tdf1_dot_product_U0_products_0_ce0), + .products_0_we0(tdf1_dot_product_U0_products_0_we0), + .products_0_d0(tdf1_dot_product_U0_products_0_d0) +); + +td_fused_top_tdf1_accum_1 tdf1_accum_1_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf1_accum_1_U0_ap_start), + .ap_done(tdf1_accum_1_U0_ap_done), + .ap_continue(tdf1_accum_1_U0_ap_continue), + .ap_idle(tdf1_accum_1_U0_ap_idle), + .ap_ready(tdf1_accum_1_U0_ap_ready), + .accum_in_0_address0(tdf1_accum_1_U0_accum_in_0_address0), + .accum_in_0_ce0(tdf1_accum_1_U0_accum_in_0_ce0), + .accum_in_0_q0(products_0_t_q0), + .accum_in_0_address1(tdf1_accum_1_U0_accum_in_0_address1), + .accum_in_0_ce1(tdf1_accum_1_U0_accum_in_0_ce1), + .accum_in_0_q1(products_0_t_q1), + .accum_out_address0(tdf1_accum_1_U0_accum_out_address0), + .accum_out_ce0(tdf1_accum_1_U0_accum_out_ce0), + .accum_out_we0(tdf1_accum_1_U0_accum_out_we0), + .accum_out_d0(tdf1_accum_1_U0_accum_out_d0) +); + +td_fused_top_tdf1_accum_2 tdf1_accum_2_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf1_accum_2_U0_ap_start), + .ap_done(tdf1_accum_2_U0_ap_done), + .ap_continue(tdf1_accum_2_U0_ap_continue), + .ap_idle(tdf1_accum_2_U0_ap_idle), + .ap_ready(tdf1_accum_2_U0_ap_ready), + .accum_in_address0(tdf1_accum_2_U0_accum_in_address0), + .accum_in_ce0(tdf1_accum_2_U0_accum_in_ce0), + .accum_in_q0(accum1_out_0_t_q0), + .accum_in_address1(tdf1_accum_2_U0_accum_in_address1), + .accum_in_ce1(tdf1_accum_2_U0_accum_in_ce1), + .accum_in_q1(accum1_out_0_t_q1), + .accum_out_address0(tdf1_accum_2_U0_accum_out_address0), + .accum_out_ce0(tdf1_accum_2_U0_accum_out_ce0), + .accum_out_we0(tdf1_accum_2_U0_accum_out_we0), + .accum_out_d0(tdf1_accum_2_U0_accum_out_d0) +); + +td_fused_top_tdf1_accum_3 tdf1_accum_3_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf1_accum_3_U0_ap_start), + .ap_done(tdf1_accum_3_U0_ap_done), + .ap_continue(tdf1_accum_3_U0_ap_continue), + .ap_idle(tdf1_accum_3_U0_ap_idle), + .ap_ready(tdf1_accum_3_U0_ap_ready), + .accum_in_18(tdf1_accum_3_U0_accum_in_18), + .accum_in_18_ap_vld(tdf1_accum_3_U0_accum_in_18_ap_vld), + .accum_in_address0(tdf1_accum_3_U0_accum_in_address0), + .accum_in_ce0(tdf1_accum_3_U0_accum_in_ce0), + .accum_in_q0(accum2_out_0_t_q0) +); + +td_fused_top_Block_entry_proc_proc Block_entry_proc_proc_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(Block_entry_proc_proc_U0_ap_start), + .ap_done(Block_entry_proc_proc_U0_ap_done), + .ap_continue(Block_entry_proc_proc_U0_ap_continue), + .ap_idle(Block_entry_proc_proc_U0_ap_idle), + .ap_ready(Block_entry_proc_proc_U0_ap_ready), + .tmp(tmp_channel_dout), + .ap_return(Block_entry_proc_proc_U0_ap_return) +); + +td_fused_top_tdf1_adjust tdf1_adjust_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf1_adjust_U0_ap_start), + .ap_done(tdf1_adjust_U0_ap_done), + .ap_continue(tdf1_adjust_U0_ap_continue), + .ap_idle(tdf1_adjust_U0_ap_idle), + .ap_ready(tdf1_adjust_U0_ap_ready), + .sums_read(sums_0_dout), + .adjustments_address0(tdf1_adjust_U0_adjustments_address0), + .adjustments_ce0(tdf1_adjust_U0_adjustments_ce0), + .adjustments_q0(adjustments_q0), + .input_indices_23_dout(input_indices_23_c1_dout), + .input_indices_23_empty_n(input_indices_23_c1_empty_n), + .input_indices_23_read(tdf1_adjust_U0_input_indices_23_read), + .ap_return(tdf1_adjust_U0_ap_return) +); + +td_fused_top_tdf1_poolOutputs tdf1_poolOutputs_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf1_poolOutputs_U0_ap_start), + .ap_done(tdf1_poolOutputs_U0_ap_done), + .ap_continue(tdf1_poolOutputs_U0_ap_continue), + .ap_idle(tdf1_poolOutputs_U0_ap_idle), + .ap_ready(tdf1_poolOutputs_U0_ap_ready), + .output_indices_04_dout(output_indices_04_c_dout), + .output_indices_04_empty_n(output_indices_04_c_empty_n), + .output_indices_04_read(tdf1_poolOutputs_U0_output_indices_04_read), + .output_indices_15_dout(output_indices_15_c_dout), + .output_indices_15_empty_n(output_indices_15_c_empty_n), + .output_indices_15_read(tdf1_poolOutputs_U0_output_indices_15_read), + .resetMaximum6_dout(resetMaximum6_c_dout), + .resetMaximum6_empty_n(resetMaximum6_c_empty_n), + .resetMaximum6_read(tdf1_poolOutputs_U0_resetMaximum6_read), + .storeOutput7_dout(storeOutput7_c_dout), + .storeOutput7_empty_n(storeOutput7_c_empty_n), + .storeOutput7_read(tdf1_poolOutputs_U0_storeOutput7_read), + .p_read(outputs_0_dout), + .out_data_address1(tdf1_poolOutputs_U0_out_data_address1), + .out_data_ce1(tdf1_poolOutputs_U0_out_data_ce1), + .out_data_we1(tdf1_poolOutputs_U0_out_data_we1), + .out_data_d1(tdf1_poolOutputs_U0_out_data_d1) +); + +td_fused_top_fifo_w4_d2_S input_indices_23_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_23_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf1_readFilters18_U0_input_indices_23_read), + .if_dout(input_indices_23_c_dout), + .if_full_n(input_indices_23_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf1_get_next_ijk_U0_input_indices_2_out_write), + .if_din(tdf1_get_next_ijk_U0_input_indices_2_out_din) +); + +td_fused_top_fifo_w4_d8_S input_indices_23_c1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_23_c1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf1_adjust_U0_input_indices_23_read), + .if_dout(input_indices_23_c1_dout), + .if_full_n(input_indices_23_c1_full_n), + .if_write_ce(1'b1), + .if_write(tdf1_get_next_ijk_U0_input_indices_2_out1_write), + .if_din(tdf1_get_next_ijk_U0_input_indices_2_out1_din) +); + +td_fused_top_fifo_w7_d9_S output_indices_04_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(output_indices_04_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf1_poolOutputs_U0_output_indices_04_read), + .if_dout(output_indices_04_c_dout), + .if_full_n(output_indices_04_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf1_get_next_ijk_U0_output_indices_0_write), + .if_din(tdf1_get_next_ijk_U0_output_indices_0_din) +); + +td_fused_top_fifo_w14_d9_S output_indices_15_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(output_indices_15_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf1_poolOutputs_U0_output_indices_15_read), + .if_dout(output_indices_15_c_dout), + .if_full_n(output_indices_15_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf1_get_next_ijk_U0_output_indices_1_write), + .if_din(tdf1_get_next_ijk_U0_output_indices_1_din) +); + +td_fused_top_fifo_w1_d9_S resetMaximum6_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(resetMaximum6_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf1_poolOutputs_U0_resetMaximum6_read), + .if_dout(resetMaximum6_c_dout), + .if_full_n(resetMaximum6_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf1_get_next_ijk_U0_resetMaximum_write), + .if_din(resetMaximum6_c_din) +); + +td_fused_top_fifo_w1_d9_S storeOutput7_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(storeOutput7_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf1_poolOutputs_U0_storeOutput7_read), + .if_dout(storeOutput7_c_dout), + .if_full_n(storeOutput7_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf1_get_next_ijk_U0_storeOutput_write), + .if_din(storeOutput7_c_din) +); + +td_fused_top_fifo_w16_d2_S input_indices_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf1_readInputs19_U0_ap_ready), + .if_dout(input_indices_0_dout), + .if_full_n(input_indices_0_full_n), + .if_write_ce(1'b1), + .if_write(ap_channel_done_input_indices_0), + .if_din(tdf1_get_next_ijk_U0_ap_return_0) +); + +td_fused_top_fifo_w16_d2_S input_indices_1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(input_indices_1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf1_readInputs19_U0_ap_ready), + .if_dout(input_indices_1_dout), + .if_full_n(input_indices_1_full_n), + .if_write_ce(1'b1), + .if_write(ap_channel_done_input_indices_1), + .if_din(tdf1_get_next_ijk_U0_ap_return_1) +); + +td_fused_top_fifo_w16_d2_S tmp_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(tmp_channel_empty_n), + .if_read_ce(1'b1), + .if_read(Block_entry_proc_proc_U0_ap_ready), + .if_dout(tmp_channel_dout), + .if_full_n(tmp_channel_full_n), + .if_write_ce(1'b1), + .if_write(tdf1_accum_3_U0_ap_done), + .if_din(tdf1_accum_3_U0_accum_in_18) +); + +td_fused_top_fifo_w16_d2_S sums_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(sums_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf1_adjust_U0_ap_ready), + .if_dout(sums_0_dout), + .if_full_n(sums_0_full_n), + .if_write_ce(1'b1), + .if_write(Block_entry_proc_proc_U0_ap_done), + .if_din(Block_entry_proc_proc_U0_ap_return) +); + +td_fused_top_fifo_w16_d2_S outputs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(outputs_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf1_poolOutputs_U0_ap_ready), + .if_dout(outputs_0_dout), + .if_full_n(outputs_0_full_n), + .if_write_ce(1'b1), + .if_write(tdf1_adjust_U0_ap_done), + .if_din(tdf1_adjust_U0_ap_return) +); + +td_fused_top_start_for_tdf1_readFilters18_U0 start_for_tdf1_readFilters18_U0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(start_for_tdf1_readFilters18_U0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf1_readFilters18_U0_ap_ready), + .if_dout(start_for_tdf1_readFilters18_U0_dout), + .if_full_n(start_for_tdf1_readFilters18_U0_full_n), + .if_write_ce(1'b1), + .if_write(tdf1_get_next_ijk_U0_start_write), + .if_din(start_for_tdf1_readFilters18_U0_din) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_input_indices_0 <= 1'b0; + end else begin + if (((tdf1_get_next_ijk_U0_ap_done & tdf1_get_next_ijk_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_input_indices_0 <= 1'b0; + end else begin + ap_sync_reg_channel_write_input_indices_0 <= ap_sync_channel_write_input_indices_0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_channel_write_input_indices_1 <= 1'b0; + end else begin + if (((tdf1_get_next_ijk_U0_ap_done & tdf1_get_next_ijk_U0_ap_continue) == 1'b1)) begin + ap_sync_reg_channel_write_input_indices_1 <= 1'b0; + end else begin + ap_sync_reg_channel_write_input_indices_1 <= ap_sync_channel_write_input_indices_1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf1_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf1_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf1_get_next_ijk_U0_ap_ready <= ap_sync_tdf1_get_next_ijk_U0_ap_ready; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf1_readInputs19_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf1_readInputs19_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf1_readInputs19_U0_ap_ready <= ap_sync_tdf1_readInputs19_U0_ap_ready; + end + end +end + +assign Block_entry_proc_proc_U0_ap_continue = sums_0_full_n; + +assign Block_entry_proc_proc_U0_ap_start = tmp_channel_empty_n; + +assign Block_entry_proc_proc_U0_start_full_n = 1'b1; + +assign Block_entry_proc_proc_U0_start_write = 1'b0; + +assign accum1_out_0_t_d1 = 16'd0; + +assign accum1_out_0_t_we1 = 1'b0; + +assign adjustments_address0 = tdf1_adjust_U0_adjustments_address0; + +assign adjustments_address1 = 4'd0; + +assign adjustments_ce0 = tdf1_adjust_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_channel_done_accum1_out_0 = tdf1_accum_1_U0_ap_done; + +assign ap_channel_done_accum2_out_0 = tdf1_accum_2_U0_ap_done; + +assign ap_channel_done_ifmap_vec = tdf1_readInputs19_U0_ap_done; + +assign ap_channel_done_input_indices_0 = (tdf1_get_next_ijk_U0_ap_done & (ap_sync_reg_channel_write_input_indices_0 ^ 1'b1)); + +assign ap_channel_done_input_indices_1 = (tdf1_get_next_ijk_U0_ap_done & (ap_sync_reg_channel_write_input_indices_1 ^ 1'b1)); + +assign ap_channel_done_outputs_0 = tdf1_adjust_U0_ap_done; + +assign ap_channel_done_products_0 = tdf1_dot_product_U0_ap_done; + +assign ap_channel_done_sums_0 = Block_entry_proc_proc_U0_ap_done; + +assign ap_channel_done_tmp_channel = tdf1_accum_3_U0_ap_done; + +assign ap_channel_done_weight_vecs_0 = tdf1_readFilters18_U0_ap_done; + +assign ap_done = tdf1_poolOutputs_U0_ap_done; + +assign ap_idle = (tdf1_readInputs19_U0_ap_idle & tdf1_readFilters18_U0_ap_idle & tdf1_poolOutputs_U0_ap_idle & tdf1_get_next_ijk_U0_ap_idle & tdf1_dot_product_U0_ap_idle & tdf1_adjust_U0_ap_idle & tdf1_accum_3_U0_ap_idle & tdf1_accum_2_U0_ap_idle & tdf1_accum_1_U0_ap_idle & (outputs_0_empty_n ^ 1'b1) & (sums_0_empty_n ^ 1'b1) & (tmp_channel_empty_n ^ 1'b1) & (input_indices_1_empty_n ^ 1'b1) & (input_indices_0_empty_n ^ 1'b1) & (products_0_t_empty_n ^ 1'b1) & (weight_vecs_0_t_empty_n ^ 1'b1) & (ifmap_vec_t_empty_n ^ 1'b1) & (1'b1 ^ accum2_out_0_t_empty_n) & (1'b1 ^ accum1_out_0_t_empty_n) & Block_entry_proc_proc_U0_ap_idle); + +assign ap_ready = ap_sync_ready; + +assign ap_sync_channel_write_input_indices_0 = ((input_indices_0_full_n & ap_channel_done_input_indices_0) | ap_sync_reg_channel_write_input_indices_0); + +assign ap_sync_channel_write_input_indices_1 = ((input_indices_1_full_n & ap_channel_done_input_indices_1) | ap_sync_reg_channel_write_input_indices_1); + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = tdf1_poolOutputs_U0_ap_done; + +assign ap_sync_ready = (ap_sync_tdf1_readInputs19_U0_ap_ready & ap_sync_tdf1_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf1_get_next_ijk_U0_ap_ready = (tdf1_get_next_ijk_U0_ap_ready | ap_sync_reg_tdf1_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf1_readInputs19_U0_ap_ready = (tdf1_readInputs19_U0_ap_ready | ap_sync_reg_tdf1_readInputs19_U0_ap_ready); + +assign filter_data_address0 = tdf1_readFilters18_U0_filter_data_address0; + +assign filter_data_address1 = 9'd0; + +assign filter_data_ce0 = tdf1_readFilters18_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = tdf1_readInputs19_U0_in_data_address0; + +assign in_data_address1 = 16'd0; + +assign in_data_ce0 = tdf1_readInputs19_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = tdf1_readInputs19_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 16'd0; + +assign out_data_address1 = tdf1_poolOutputs_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = tdf1_poolOutputs_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = tdf1_poolOutputs_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = tdf1_poolOutputs_U0_out_data_we1; + +assign out_data_write = tdf1_poolOutputs_U0_out_data_write; + +assign products_0_t_d1 = 16'd0; + +assign products_0_t_we1 = 1'b0; + +assign resetMaximum6_c_din = tdf1_get_next_ijk_U0_resetMaximum_din; + +assign start_for_tdf1_readFilters18_U0_din = 1'b1; + +assign storeOutput7_c_din = tdf1_get_next_ijk_U0_storeOutput_din; + +assign tdf1_accum_1_U0_accum_out_full_n = accum1_out_0_i_full_n; + +assign tdf1_accum_1_U0_ap_continue = accum1_out_0_i_full_n; + +assign tdf1_accum_1_U0_ap_start = products_0_t_empty_n; + +assign tdf1_accum_1_U0_start_full_n = 1'b1; + +assign tdf1_accum_1_U0_start_write = 1'b0; + +assign tdf1_accum_2_U0_accum_out_full_n = accum2_out_0_i_full_n; + +assign tdf1_accum_2_U0_ap_continue = accum2_out_0_i_full_n; + +assign tdf1_accum_2_U0_ap_start = accum1_out_0_t_empty_n; + +assign tdf1_accum_2_U0_start_full_n = 1'b1; + +assign tdf1_accum_2_U0_start_write = 1'b0; + +assign tdf1_accum_3_U0_ap_continue = tmp_channel_full_n; + +assign tdf1_accum_3_U0_ap_start = accum2_out_0_t_empty_n; + +assign tdf1_accum_3_U0_start_full_n = 1'b1; + +assign tdf1_accum_3_U0_start_write = 1'b0; + +assign tdf1_adjust_U0_ap_continue = outputs_0_full_n; + +assign tdf1_adjust_U0_ap_start = sums_0_empty_n; + +assign tdf1_adjust_U0_start_full_n = 1'b1; + +assign tdf1_adjust_U0_start_write = 1'b0; + +assign tdf1_dot_product_U0_ap_continue = products_0_i_full_n; + +assign tdf1_dot_product_U0_ap_start = (weight_vecs_0_t_empty_n & ifmap_vec_t_empty_n); + +assign tdf1_dot_product_U0_products_0_full_n = products_0_i_full_n; + +assign tdf1_dot_product_U0_start_full_n = 1'b1; + +assign tdf1_dot_product_U0_start_write = 1'b0; + +assign tdf1_get_next_ijk_U0_ap_continue = (ap_sync_channel_write_input_indices_1 & ap_sync_channel_write_input_indices_0); + +assign tdf1_get_next_ijk_U0_ap_start = ((ap_sync_reg_tdf1_get_next_ijk_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf1_poolOutputs_U0_ap_continue = ap_continue; + +assign tdf1_poolOutputs_U0_ap_start = outputs_0_empty_n; + +assign tdf1_poolOutputs_U0_out_data_full_n = out_data_full_n; + +assign tdf1_poolOutputs_U0_out_data_write = 1'b0; + +assign tdf1_poolOutputs_U0_start_full_n = 1'b1; + +assign tdf1_poolOutputs_U0_start_write = 1'b0; + +assign tdf1_readFilters18_U0_ap_continue = weight_vecs_0_i_full_n; + +assign tdf1_readFilters18_U0_ap_start = start_for_tdf1_readFilters18_U0_empty_n; + +assign tdf1_readFilters18_U0_start_full_n = 1'b1; + +assign tdf1_readFilters18_U0_start_write = 1'b0; + +assign tdf1_readFilters18_U0_weight_vecs_0_full_n = weight_vecs_0_i_full_n; + +assign tdf1_readInputs19_U0_ap_continue = ifmap_vec_i_full_n; + +assign tdf1_readInputs19_U0_ap_start = (input_indices_1_empty_n & input_indices_0_empty_n & (ap_sync_reg_tdf1_readInputs19_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf1_readInputs19_U0_ifmap_vec_full_n = ifmap_vec_i_full_n; + +assign tdf1_readInputs19_U0_in_data_full_n = in_data_empty_n; + +assign tdf1_readInputs19_U0_in_data_write = 1'b0; + +assign tdf1_readInputs19_U0_start_full_n = 1'b1; + +assign tdf1_readInputs19_U0_start_write = 1'b0; + +endmodule //td_fused_top_dataflow_in_loop_TOP_LOOP38116 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38270_accum1_out_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 3; +parameter MEM_SIZE = 8; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38270_accum1_out_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd8; +parameter AddressWidth = 32'd3; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38270_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38270_accum1_out_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38270_accum1_out_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 3, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP38270_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38270_accum1_out_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP38270_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38270_accum1_out_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38270_ifmap_vec_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 10; +parameter MEM_SIZE = 576; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38270_ifmap_vec_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd576; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38270_ifmap_vec_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38270_ifmap_vec_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38270_ifmap_vec +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 10, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP38270_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38270_ifmap_vec_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP38270_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38270_ifmap_vec_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38270_l2_products_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 8; +parameter MEM_SIZE = 256; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38270_l2_products_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd256; +parameter AddressWidth = 32'd8; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38270_l2_products_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38270_l2_products_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38270_l2_products +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 7, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP38270_l2_products_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38270_l2_products_memcore_U ( + .reset ( reset ), + .clk ( clk ), + .address0 ( memcore_iaddr ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + .address1 ( memcore_taddr ), + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .d1 ( t_d0 ), + .q1 ( t_q0 ) + +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38270_products_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 10; +parameter MEM_SIZE = 576; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38270_products_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd576; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38270_products_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38270_products_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38270_products_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 10, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire [AddressWidth-1:0] i_address1, + output wire [DataWidth-1:0] i_q1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire [AddressWidth-1:0] t_address1, + output wire [DataWidth-1:0] t_q1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_q1_0, buf_q1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP38270_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38270_products_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .q1 ( buf_q1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP38270_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38270_products_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .q1 ( buf_q1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign i_q1 = (prev_iptr == 1'b1 ? buf_q1_1 : buf_q1_0); +assign t_q1 = reg_valid1 ? reg_q1 : (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// reg_q1 and reg_valid1 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q1 <= 1'b0; + reg_valid1 <= 1'b0; + end else if (!t_ce1 && !reg_valid1) begin + reg_q1 <= (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + reg_valid1 <= 1'b1; + end else if (t_ce1) begin + reg_valid1 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38270 ( + ap_clk, + ap_rst, + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + l1_filter_data_address0, + l1_filter_data_ce0, + l1_filter_data_d0, + l1_filter_data_q0, + l1_filter_data_we0, + l1_filter_data_address1, + l1_filter_data_ce1, + l1_filter_data_d1, + l1_filter_data_q1, + l1_filter_data_we1, + l1_adjustments_address0, + l1_adjustments_ce0, + l1_adjustments_d0, + l1_adjustments_q0, + l1_adjustments_we0, + l1_adjustments_address1, + l1_adjustments_ce1, + l1_adjustments_d1, + l1_adjustments_q1, + l1_adjustments_we1, + l2_filter_data_address0, + l2_filter_data_ce0, + l2_filter_data_d0, + l2_filter_data_q0, + l2_filter_data_we0, + l2_filter_data_address1, + l2_filter_data_ce1, + l2_filter_data_d1, + l2_filter_data_q1, + l2_filter_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_d0, + l2_adjustments_q0, + l2_adjustments_we0, + l2_adjustments_address1, + l2_adjustments_ce1, + l2_adjustments_d1, + l2_adjustments_q1, + l2_adjustments_we1, + ap_start, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +input ap_clk; +input ap_rst; +output [11:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [11:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [16:0] l1_filter_data_address0; +output l1_filter_data_ce0; +output [63:0] l1_filter_data_d0; +input [63:0] l1_filter_data_q0; +output l1_filter_data_we0; +output [16:0] l1_filter_data_address1; +output l1_filter_data_ce1; +output [63:0] l1_filter_data_d1; +input [63:0] l1_filter_data_q1; +output l1_filter_data_we1; +output [8:0] l1_adjustments_address0; +output l1_adjustments_ce0; +output [47:0] l1_adjustments_d0; +input [47:0] l1_adjustments_q0; +output l1_adjustments_we0; +output [8:0] l1_adjustments_address1; +output l1_adjustments_ce1; +output [47:0] l1_adjustments_d1; +input [47:0] l1_adjustments_q1; +output l1_adjustments_we1; +output [15:0] l2_filter_data_address0; +output l2_filter_data_ce0; +output [15:0] l2_filter_data_d0; +input [15:0] l2_filter_data_q0; +output l2_filter_data_we0; +output [15:0] l2_filter_data_address1; +output l2_filter_data_ce1; +output [15:0] l2_filter_data_d1; +input [15:0] l2_filter_data_q1; +output l2_filter_data_we1; +output [12:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [12:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [6:0] l2_adjustments_address0; +output l2_adjustments_ce0; +output [47:0] l2_adjustments_d0; +input [47:0] l2_adjustments_q0; +output l2_adjustments_we0; +output [6:0] l2_adjustments_address1; +output l2_adjustments_ce1; +output [47:0] l2_adjustments_d1; +input [47:0] l2_adjustments_q1; +output l2_adjustments_we1; +input ap_start; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +wire [15:0] ifmap_vec_i_q0; +wire [15:0] ifmap_vec_t_q0; +wire [15:0] weight_vecs_0_i_q0; +wire [15:0] weight_vecs_0_t_q0; +wire [15:0] products_0_i_q0; +wire [15:0] products_0_i_q1; +wire [15:0] products_0_t_q0; +wire [15:0] products_0_t_q1; +wire [15:0] accum1_out_0_i_q0; +wire [15:0] accum1_out_0_t_q0; +wire [15:0] l2_products_i_q0; +wire [15:0] l2_products_t_q0; +wire tdf11_get_next_ijk_U0_ap_start; +wire tdf11_get_next_ijk_U0_ap_done; +wire tdf11_get_next_ijk_U0_ap_continue; +wire tdf11_get_next_ijk_U0_ap_idle; +wire tdf11_get_next_ijk_U0_ap_ready; +wire tdf11_get_next_ijk_U0_start_out; +wire tdf11_get_next_ijk_U0_start_write; +wire [15:0] tdf11_get_next_ijk_U0_indices_0_din; +wire tdf11_get_next_ijk_U0_indices_0_write; +wire [15:0] tdf11_get_next_ijk_U0_indices_1_din; +wire tdf11_get_next_ijk_U0_indices_1_write; +wire [8:0] tdf11_get_next_ijk_U0_indices_2_out_din; +wire tdf11_get_next_ijk_U0_indices_2_out_write; +wire [8:0] tdf11_get_next_ijk_U0_indices_2_out1_din; +wire tdf11_get_next_ijk_U0_indices_2_out1_write; +wire tdf11_get_next_ijk_U0_write_r_din; +wire tdf11_get_next_ijk_U0_write_r_write; +wire tdf11_readInputs75_U0_ap_start; +wire tdf11_readInputs75_U0_ap_done; +wire tdf11_readInputs75_U0_ap_continue; +wire tdf11_readInputs75_U0_ap_idle; +wire tdf11_readInputs75_U0_ap_ready; +wire [11:0] tdf11_readInputs75_U0_in_data_address0; +wire tdf11_readInputs75_U0_in_data_ce0; +wire tdf11_readInputs75_U0_indices_01_read; +wire tdf11_readInputs75_U0_indices_12_read; +wire [9:0] tdf11_readInputs75_U0_ifmap_vec_address0; +wire tdf11_readInputs75_U0_ifmap_vec_ce0; +wire tdf11_readInputs75_U0_ifmap_vec_we0; +wire [15:0] tdf11_readInputs75_U0_ifmap_vec_d0; +wire [9:0] tdf11_readInputs75_U0_ifmap_vec_address1; +wire tdf11_readInputs75_U0_ifmap_vec_ce1; +wire tdf11_readInputs75_U0_ifmap_vec_we1; +wire [15:0] tdf11_readInputs75_U0_ifmap_vec_d1; +wire [3:0] tdf11_readInputs75_U0_indices_01_out_din; +wire tdf11_readInputs75_U0_indices_01_out_write; +wire [7:0] tdf11_readInputs75_U0_indices_12_out_din; +wire tdf11_readInputs75_U0_indices_12_out_write; +wire tdf11_readInputs75_U0_in_data_full_n; +wire tdf11_readInputs75_U0_in_data_write; +wire ap_channel_done_ifmap_vec; +wire tdf11_readInputs75_U0_ifmap_vec_full_n; +wire tdf11_readFilters74_U0_ap_start; +wire tdf11_readFilters74_U0_ap_done; +wire tdf11_readFilters74_U0_ap_continue; +wire tdf11_readFilters74_U0_ap_idle; +wire tdf11_readFilters74_U0_ap_ready; +wire [16:0] tdf11_readFilters74_U0_filter_data_address0; +wire tdf11_readFilters74_U0_filter_data_ce0; +wire tdf11_readFilters74_U0_indices_23_read; +wire [9:0] tdf11_readFilters74_U0_weight_vecs_0_address0; +wire tdf11_readFilters74_U0_weight_vecs_0_ce0; +wire tdf11_readFilters74_U0_weight_vecs_0_we0; +wire [15:0] tdf11_readFilters74_U0_weight_vecs_0_d0; +wire [9:0] tdf11_readFilters74_U0_weight_vecs_0_address1; +wire tdf11_readFilters74_U0_weight_vecs_0_ce1; +wire tdf11_readFilters74_U0_weight_vecs_0_we1; +wire [15:0] tdf11_readFilters74_U0_weight_vecs_0_d1; +wire ap_channel_done_weight_vecs_0; +wire tdf11_readFilters74_U0_weight_vecs_0_full_n; +wire tdf11_dot_product_U0_ap_start; +wire tdf11_dot_product_U0_ap_done; +wire tdf11_dot_product_U0_ap_continue; +wire tdf11_dot_product_U0_ap_idle; +wire tdf11_dot_product_U0_ap_ready; +wire [9:0] tdf11_dot_product_U0_ifmap_vec_address0; +wire tdf11_dot_product_U0_ifmap_vec_ce0; +wire [9:0] tdf11_dot_product_U0_weight_vecs_0_address0; +wire tdf11_dot_product_U0_weight_vecs_0_ce0; +wire [9:0] tdf11_dot_product_U0_products_0_address0; +wire tdf11_dot_product_U0_products_0_ce0; +wire tdf11_dot_product_U0_products_0_we0; +wire [15:0] tdf11_dot_product_U0_products_0_d0; +wire ap_channel_done_products_0; +wire tdf11_dot_product_U0_products_0_full_n; +wire tdf11_accum_1_U0_ap_start; +wire tdf11_accum_1_U0_ap_done; +wire tdf11_accum_1_U0_ap_continue; +wire tdf11_accum_1_U0_ap_idle; +wire tdf11_accum_1_U0_ap_ready; +wire [9:0] tdf11_accum_1_U0_accum_in_0_address0; +wire tdf11_accum_1_U0_accum_in_0_ce0; +wire [9:0] tdf11_accum_1_U0_accum_in_0_address1; +wire tdf11_accum_1_U0_accum_in_0_ce1; +wire [2:0] tdf11_accum_1_U0_accum_out_address0; +wire tdf11_accum_1_U0_accum_out_ce0; +wire tdf11_accum_1_U0_accum_out_we0; +wire [15:0] tdf11_accum_1_U0_accum_out_d0; +wire [2:0] tdf11_accum_1_U0_accum_out_address1; +wire tdf11_accum_1_U0_accum_out_ce1; +wire tdf11_accum_1_U0_accum_out_we1; +wire [15:0] tdf11_accum_1_U0_accum_out_d1; +wire ap_channel_done_accum1_out_0; +wire tdf11_accum_1_U0_accum_out_full_n; +wire tdf11_accum_2_U0_ap_start; +wire tdf11_accum_2_U0_ap_done; +wire tdf11_accum_2_U0_ap_continue; +wire tdf11_accum_2_U0_ap_idle; +wire tdf11_accum_2_U0_ap_ready; +wire [15:0] tdf11_accum_2_U0_accum_in_22; +wire tdf11_accum_2_U0_accum_in_22_ap_vld; +wire [2:0] tdf11_accum_2_U0_accum_in_address0; +wire tdf11_accum_2_U0_accum_in_ce0; +wire ap_channel_done_tmp_channel; +wire tmp_channel_full_n; +wire Block_entry_proc_proc441_U0_ap_start; +wire Block_entry_proc_proc441_U0_ap_done; +wire Block_entry_proc_proc441_U0_ap_continue; +wire Block_entry_proc_proc441_U0_ap_idle; +wire Block_entry_proc_proc441_U0_ap_ready; +wire [15:0] Block_entry_proc_proc441_U0_ap_return; +wire ap_channel_done_sums_0; +wire sums_0_full_n; +wire tdf11_adjust_U0_ap_start; +wire tdf11_adjust_U0_ap_done; +wire tdf11_adjust_U0_ap_continue; +wire tdf11_adjust_U0_ap_idle; +wire tdf11_adjust_U0_ap_ready; +wire [8:0] tdf11_adjust_U0_adjustments_address0; +wire tdf11_adjust_U0_adjustments_ce0; +wire tdf11_adjust_U0_indices_23_read; +wire [8:0] tdf11_adjust_U0_indices_23_out_din; +wire tdf11_adjust_U0_indices_23_out_write; +wire [15:0] tdf11_adjust_U0_ap_return; +wire ap_channel_done_intermediate_fmaps_0; +wire intermediate_fmaps_0_full_n; +wire tdf11_l2_multiply72_U0_ap_start; +wire tdf11_l2_multiply72_U0_ap_done; +wire tdf11_l2_multiply72_U0_ap_continue; +wire tdf11_l2_multiply72_U0_ap_idle; +wire tdf11_l2_multiply72_U0_ap_ready; +wire [15:0] tdf11_l2_multiply72_U0_l2_filter_data_address0; +wire tdf11_l2_multiply72_U0_l2_filter_data_ce0; +wire [6:0] tdf11_l2_multiply72_U0_l2_products_address0; +wire tdf11_l2_multiply72_U0_l2_products_ce0; +wire tdf11_l2_multiply72_U0_l2_products_we0; +wire [15:0] tdf11_l2_multiply72_U0_l2_products_d0; +wire tdf11_l2_multiply72_U0_indices_23_read; +wire ap_channel_done_l2_products; +wire tdf11_l2_multiply72_U0_l2_products_full_n; +wire tdf11_l2_writeOutputs_171_U0_ap_start; +wire tdf11_l2_writeOutputs_171_U0_ap_done; +wire tdf11_l2_writeOutputs_171_U0_ap_continue; +wire tdf11_l2_writeOutputs_171_U0_ap_idle; +wire tdf11_l2_writeOutputs_171_U0_ap_ready; +wire tdf11_l2_writeOutputs_171_U0_indices_01_read; +wire tdf11_l2_writeOutputs_171_U0_indices_12_read; +wire tdf11_l2_writeOutputs_171_U0_write4_read; +wire [6:0] tdf11_l2_writeOutputs_171_U0_l2_partial_sums_address0; +wire tdf11_l2_writeOutputs_171_U0_l2_partial_sums_ce0; +wire [12:0] tdf11_l2_writeOutputs_171_U0_out_data_address1; +wire tdf11_l2_writeOutputs_171_U0_out_data_ce1; +wire tdf11_l2_writeOutputs_171_U0_out_data_we1; +wire [63:0] tdf11_l2_writeOutputs_171_U0_out_data_d1; +wire [6:0] tdf11_l2_writeOutputs_171_U0_l2_adjustments_address0; +wire tdf11_l2_writeOutputs_171_U0_l2_adjustments_ce0; +wire tdf11_l2_writeOutputs_171_U0_out_data_full_n; +wire tdf11_l2_writeOutputs_171_U0_out_data_write; +wire ap_sync_continue; +wire ifmap_vec_i_full_n; +wire ifmap_vec_t_empty_n; +wire weight_vecs_0_i_full_n; +wire weight_vecs_0_t_empty_n; +wire products_0_i_full_n; +wire products_0_t_empty_n; +wire [15:0] products_0_t_d1; +wire products_0_t_we1; +wire accum1_out_0_i_full_n; +wire accum1_out_0_t_empty_n; +wire l2_products_i_full_n; +wire l2_products_t_empty_n; +wire indices_01_c_full_n; +wire [15:0] indices_01_c_dout; +wire indices_01_c_empty_n; +wire indices_12_c_full_n; +wire [15:0] indices_12_c_dout; +wire indices_12_c_empty_n; +wire indices_23_c_full_n; +wire [8:0] indices_23_c_dout; +wire indices_23_c_empty_n; +wire indices_23_c1_full_n; +wire [8:0] indices_23_c1_dout; +wire indices_23_c1_empty_n; +wire [0:0] write4_c_din; +wire write4_c_full_n; +wire [0:0] write4_c_dout; +wire write4_c_empty_n; +wire indices_01_c2_full_n; +wire [3:0] indices_01_c2_dout; +wire indices_01_c2_empty_n; +wire indices_12_c3_full_n; +wire [7:0] indices_12_c3_dout; +wire indices_12_c3_empty_n; +wire [15:0] tmp_channel_dout; +wire tmp_channel_empty_n; +wire [15:0] sums_0_dout; +wire sums_0_empty_n; +wire indices_23_c4_full_n; +wire [8:0] indices_23_c4_dout; +wire indices_23_c4_empty_n; +wire [15:0] intermediate_fmaps_0_dout; +wire intermediate_fmaps_0_empty_n; +wire ap_sync_done; +wire ap_sync_ready; +reg ap_sync_reg_tdf11_get_next_ijk_U0_ap_ready; +wire ap_sync_tdf11_get_next_ijk_U0_ap_ready; +reg ap_sync_reg_tdf11_readInputs75_U0_ap_ready; +wire ap_sync_tdf11_readInputs75_U0_ap_ready; +wire [0:0] start_for_tdf11_readFilters74_U0_din; +wire start_for_tdf11_readFilters74_U0_full_n; +wire [0:0] start_for_tdf11_readFilters74_U0_dout; +wire start_for_tdf11_readFilters74_U0_empty_n; +wire tdf11_readInputs75_U0_start_full_n; +wire tdf11_readInputs75_U0_start_write; +wire tdf11_readFilters74_U0_start_full_n; +wire tdf11_readFilters74_U0_start_write; +wire tdf11_dot_product_U0_start_full_n; +wire tdf11_dot_product_U0_start_write; +wire tdf11_accum_1_U0_start_full_n; +wire tdf11_accum_1_U0_start_write; +wire tdf11_accum_2_U0_start_full_n; +wire tdf11_accum_2_U0_start_write; +wire Block_entry_proc_proc441_U0_start_full_n; +wire Block_entry_proc_proc441_U0_start_write; +wire tdf11_adjust_U0_start_full_n; +wire tdf11_adjust_U0_start_write; +wire tdf11_l2_multiply72_U0_start_full_n; +wire tdf11_l2_multiply72_U0_start_write; +wire tdf11_l2_writeOutputs_171_U0_start_full_n; +wire tdf11_l2_writeOutputs_171_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_sync_reg_tdf11_get_next_ijk_U0_ap_ready = 1'b0; +#0 ap_sync_reg_tdf11_readInputs75_U0_ap_ready = 1'b0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP38270_ifmap_vec #( + .DataWidth( 16 ), + .AddressRange( 576 ), + .AddressWidth( 10 )) +ifmap_vec_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf11_readInputs75_U0_ap_done), + .i_full_n(ifmap_vec_i_full_n), + .i_ce0(tdf11_readInputs75_U0_ifmap_vec_ce0), + .i_we0(tdf11_readInputs75_U0_ifmap_vec_we0), + .i_address0(tdf11_readInputs75_U0_ifmap_vec_address0), + .i_d0(tdf11_readInputs75_U0_ifmap_vec_d0), + .i_q0(ifmap_vec_i_q0), + .i_ce1(tdf11_readInputs75_U0_ifmap_vec_ce1), + .i_we1(tdf11_readInputs75_U0_ifmap_vec_we1), + .i_address1(tdf11_readInputs75_U0_ifmap_vec_address1), + .i_d1(tdf11_readInputs75_U0_ifmap_vec_d1), + .t_ce(1'b1), + .t_read(tdf11_dot_product_U0_ap_ready), + .t_empty_n(ifmap_vec_t_empty_n), + .t_ce0(tdf11_dot_product_U0_ifmap_vec_ce0), + .t_we0(1'b0), + .t_address0(tdf11_dot_product_U0_ifmap_vec_address0), + .t_d0(16'd0), + .t_q0(ifmap_vec_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(10'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP38270_ifmap_vec #( + .DataWidth( 16 ), + .AddressRange( 576 ), + .AddressWidth( 10 )) +weight_vecs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf11_readFilters74_U0_ap_done), + .i_full_n(weight_vecs_0_i_full_n), + .i_ce0(tdf11_readFilters74_U0_weight_vecs_0_ce0), + .i_we0(tdf11_readFilters74_U0_weight_vecs_0_we0), + .i_address0(tdf11_readFilters74_U0_weight_vecs_0_address0), + .i_d0(tdf11_readFilters74_U0_weight_vecs_0_d0), + .i_q0(weight_vecs_0_i_q0), + .i_ce1(tdf11_readFilters74_U0_weight_vecs_0_ce1), + .i_we1(tdf11_readFilters74_U0_weight_vecs_0_we1), + .i_address1(tdf11_readFilters74_U0_weight_vecs_0_address1), + .i_d1(tdf11_readFilters74_U0_weight_vecs_0_d1), + .t_ce(1'b1), + .t_read(tdf11_dot_product_U0_ap_ready), + .t_empty_n(weight_vecs_0_t_empty_n), + .t_ce0(tdf11_dot_product_U0_weight_vecs_0_ce0), + .t_we0(1'b0), + .t_address0(tdf11_dot_product_U0_weight_vecs_0_address0), + .t_d0(16'd0), + .t_q0(weight_vecs_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(10'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP38270_products_0 #( + .DataWidth( 16 ), + .AddressRange( 576 ), + .AddressWidth( 10 )) +products_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf11_dot_product_U0_ap_done), + .i_full_n(products_0_i_full_n), + .i_ce0(tdf11_dot_product_U0_products_0_ce0), + .i_we0(tdf11_dot_product_U0_products_0_we0), + .i_address0(tdf11_dot_product_U0_products_0_address0), + .i_d0(tdf11_dot_product_U0_products_0_d0), + .i_q0(products_0_i_q0), + .i_ce1(1'b0), + .i_address1(10'd0), + .i_q1(products_0_i_q1), + .t_ce(1'b1), + .t_read(tdf11_accum_1_U0_ap_ready), + .t_empty_n(products_0_t_empty_n), + .t_ce0(tdf11_accum_1_U0_accum_in_0_ce0), + .t_we0(1'b0), + .t_address0(tdf11_accum_1_U0_accum_in_0_address0), + .t_d0(16'd0), + .t_q0(products_0_t_q0), + .t_ce1(tdf11_accum_1_U0_accum_in_0_ce1), + .t_address1(tdf11_accum_1_U0_accum_in_0_address1), + .t_q1(products_0_t_q1) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP38270_accum1_out_0 #( + .DataWidth( 16 ), + .AddressRange( 8 ), + .AddressWidth( 3 )) +accum1_out_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf11_accum_1_U0_ap_done), + .i_full_n(accum1_out_0_i_full_n), + .i_ce0(tdf11_accum_1_U0_accum_out_ce0), + .i_we0(tdf11_accum_1_U0_accum_out_we0), + .i_address0(tdf11_accum_1_U0_accum_out_address0), + .i_d0(tdf11_accum_1_U0_accum_out_d0), + .i_q0(accum1_out_0_i_q0), + .i_ce1(tdf11_accum_1_U0_accum_out_ce1), + .i_we1(tdf11_accum_1_U0_accum_out_we1), + .i_address1(tdf11_accum_1_U0_accum_out_address1), + .i_d1(tdf11_accum_1_U0_accum_out_d1), + .t_ce(1'b1), + .t_read(tdf11_accum_2_U0_ap_ready), + .t_empty_n(accum1_out_0_t_empty_n), + .t_ce0(tdf11_accum_2_U0_accum_in_ce0), + .t_we0(1'b0), + .t_address0(tdf11_accum_2_U0_accum_in_address0), + .t_d0(16'd0), + .t_q0(accum1_out_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(3'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP38270_l2_products #( + .DataWidth( 16 ), + .AddressRange( 128 ), + .AddressWidth( 7 )) +l2_products_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf11_l2_multiply72_U0_ap_done), + .i_full_n(l2_products_i_full_n), + .i_ce0(tdf11_l2_multiply72_U0_l2_products_ce0), + .i_we0(tdf11_l2_multiply72_U0_l2_products_we0), + .i_address0(tdf11_l2_multiply72_U0_l2_products_address0), + .i_d0(tdf11_l2_multiply72_U0_l2_products_d0), + .i_q0(l2_products_i_q0), + .t_ce(1'b1), + .t_read(tdf11_l2_writeOutputs_171_U0_ap_ready), + .t_empty_n(l2_products_t_empty_n), + .t_ce0(tdf11_l2_writeOutputs_171_U0_l2_partial_sums_ce0), + .t_we0(1'b0), + .t_address0(tdf11_l2_writeOutputs_171_U0_l2_partial_sums_address0), + .t_d0(16'd0), + .t_q0(l2_products_t_q0) +); + +td_fused_top_tdf11_get_next_ijk tdf11_get_next_ijk_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf11_get_next_ijk_U0_ap_start), + .start_full_n(start_for_tdf11_readFilters74_U0_full_n), + .ap_done(tdf11_get_next_ijk_U0_ap_done), + .ap_continue(tdf11_get_next_ijk_U0_ap_continue), + .ap_idle(tdf11_get_next_ijk_U0_ap_idle), + .ap_ready(tdf11_get_next_ijk_U0_ap_ready), + .start_out(tdf11_get_next_ijk_U0_start_out), + .start_write(tdf11_get_next_ijk_U0_start_write), + .indices_0_din(tdf11_get_next_ijk_U0_indices_0_din), + .indices_0_full_n(indices_01_c_full_n), + .indices_0_write(tdf11_get_next_ijk_U0_indices_0_write), + .indices_1_din(tdf11_get_next_ijk_U0_indices_1_din), + .indices_1_full_n(indices_12_c_full_n), + .indices_1_write(tdf11_get_next_ijk_U0_indices_1_write), + .indices_2_out_din(tdf11_get_next_ijk_U0_indices_2_out_din), + .indices_2_out_full_n(indices_23_c_full_n), + .indices_2_out_write(tdf11_get_next_ijk_U0_indices_2_out_write), + .indices_2_out1_din(tdf11_get_next_ijk_U0_indices_2_out1_din), + .indices_2_out1_full_n(indices_23_c1_full_n), + .indices_2_out1_write(tdf11_get_next_ijk_U0_indices_2_out1_write), + .write_r_din(tdf11_get_next_ijk_U0_write_r_din), + .write_r_full_n(write4_c_full_n), + .write_r_write(tdf11_get_next_ijk_U0_write_r_write) +); + +td_fused_top_tdf11_readInputs75 tdf11_readInputs75_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf11_readInputs75_U0_ap_start), + .ap_done(tdf11_readInputs75_U0_ap_done), + .ap_continue(tdf11_readInputs75_U0_ap_continue), + .ap_idle(tdf11_readInputs75_U0_ap_idle), + .ap_ready(tdf11_readInputs75_U0_ap_ready), + .in_data_address0(tdf11_readInputs75_U0_in_data_address0), + .in_data_ce0(tdf11_readInputs75_U0_in_data_ce0), + .in_data_q0(in_data_q0), + .indices_01_dout(indices_01_c_dout), + .indices_01_empty_n(indices_01_c_empty_n), + .indices_01_read(tdf11_readInputs75_U0_indices_01_read), + .indices_12_dout(indices_12_c_dout), + .indices_12_empty_n(indices_12_c_empty_n), + .indices_12_read(tdf11_readInputs75_U0_indices_12_read), + .ifmap_vec_address0(tdf11_readInputs75_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf11_readInputs75_U0_ifmap_vec_ce0), + .ifmap_vec_we0(tdf11_readInputs75_U0_ifmap_vec_we0), + .ifmap_vec_d0(tdf11_readInputs75_U0_ifmap_vec_d0), + .ifmap_vec_address1(tdf11_readInputs75_U0_ifmap_vec_address1), + .ifmap_vec_ce1(tdf11_readInputs75_U0_ifmap_vec_ce1), + .ifmap_vec_we1(tdf11_readInputs75_U0_ifmap_vec_we1), + .ifmap_vec_d1(tdf11_readInputs75_U0_ifmap_vec_d1), + .indices_01_out_din(tdf11_readInputs75_U0_indices_01_out_din), + .indices_01_out_full_n(indices_01_c2_full_n), + .indices_01_out_write(tdf11_readInputs75_U0_indices_01_out_write), + .indices_12_out_din(tdf11_readInputs75_U0_indices_12_out_din), + .indices_12_out_full_n(indices_12_c3_full_n), + .indices_12_out_write(tdf11_readInputs75_U0_indices_12_out_write) +); + +td_fused_top_tdf11_readFilters74 tdf11_readFilters74_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf11_readFilters74_U0_ap_start), + .ap_done(tdf11_readFilters74_U0_ap_done), + .ap_continue(tdf11_readFilters74_U0_ap_continue), + .ap_idle(tdf11_readFilters74_U0_ap_idle), + .ap_ready(tdf11_readFilters74_U0_ap_ready), + .filter_data_address0(tdf11_readFilters74_U0_filter_data_address0), + .filter_data_ce0(tdf11_readFilters74_U0_filter_data_ce0), + .filter_data_q0(l1_filter_data_q0), + .indices_23_dout(indices_23_c_dout), + .indices_23_empty_n(indices_23_c_empty_n), + .indices_23_read(tdf11_readFilters74_U0_indices_23_read), + .weight_vecs_0_address0(tdf11_readFilters74_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf11_readFilters74_U0_weight_vecs_0_ce0), + .weight_vecs_0_we0(tdf11_readFilters74_U0_weight_vecs_0_we0), + .weight_vecs_0_d0(tdf11_readFilters74_U0_weight_vecs_0_d0), + .weight_vecs_0_address1(tdf11_readFilters74_U0_weight_vecs_0_address1), + .weight_vecs_0_ce1(tdf11_readFilters74_U0_weight_vecs_0_ce1), + .weight_vecs_0_we1(tdf11_readFilters74_U0_weight_vecs_0_we1), + .weight_vecs_0_d1(tdf11_readFilters74_U0_weight_vecs_0_d1) +); + +td_fused_top_tdf11_dot_product tdf11_dot_product_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf11_dot_product_U0_ap_start), + .ap_done(tdf11_dot_product_U0_ap_done), + .ap_continue(tdf11_dot_product_U0_ap_continue), + .ap_idle(tdf11_dot_product_U0_ap_idle), + .ap_ready(tdf11_dot_product_U0_ap_ready), + .ifmap_vec_address0(tdf11_dot_product_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf11_dot_product_U0_ifmap_vec_ce0), + .ifmap_vec_q0(ifmap_vec_t_q0), + .weight_vecs_0_address0(tdf11_dot_product_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf11_dot_product_U0_weight_vecs_0_ce0), + .weight_vecs_0_q0(weight_vecs_0_t_q0), + .products_0_address0(tdf11_dot_product_U0_products_0_address0), + .products_0_ce0(tdf11_dot_product_U0_products_0_ce0), + .products_0_we0(tdf11_dot_product_U0_products_0_we0), + .products_0_d0(tdf11_dot_product_U0_products_0_d0) +); + +td_fused_top_tdf11_accum_1 tdf11_accum_1_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf11_accum_1_U0_ap_start), + .ap_done(tdf11_accum_1_U0_ap_done), + .ap_continue(tdf11_accum_1_U0_ap_continue), + .ap_idle(tdf11_accum_1_U0_ap_idle), + .ap_ready(tdf11_accum_1_U0_ap_ready), + .accum_in_0_address0(tdf11_accum_1_U0_accum_in_0_address0), + .accum_in_0_ce0(tdf11_accum_1_U0_accum_in_0_ce0), + .accum_in_0_q0(products_0_t_q0), + .accum_in_0_address1(tdf11_accum_1_U0_accum_in_0_address1), + .accum_in_0_ce1(tdf11_accum_1_U0_accum_in_0_ce1), + .accum_in_0_q1(products_0_t_q1), + .accum_out_address0(tdf11_accum_1_U0_accum_out_address0), + .accum_out_ce0(tdf11_accum_1_U0_accum_out_ce0), + .accum_out_we0(tdf11_accum_1_U0_accum_out_we0), + .accum_out_d0(tdf11_accum_1_U0_accum_out_d0), + .accum_out_address1(tdf11_accum_1_U0_accum_out_address1), + .accum_out_ce1(tdf11_accum_1_U0_accum_out_ce1), + .accum_out_we1(tdf11_accum_1_U0_accum_out_we1), + .accum_out_d1(tdf11_accum_1_U0_accum_out_d1) +); + +td_fused_top_tdf11_accum_2 tdf11_accum_2_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf11_accum_2_U0_ap_start), + .ap_done(tdf11_accum_2_U0_ap_done), + .ap_continue(tdf11_accum_2_U0_ap_continue), + .ap_idle(tdf11_accum_2_U0_ap_idle), + .ap_ready(tdf11_accum_2_U0_ap_ready), + .accum_in_22(tdf11_accum_2_U0_accum_in_22), + .accum_in_22_ap_vld(tdf11_accum_2_U0_accum_in_22_ap_vld), + .accum_in_address0(tdf11_accum_2_U0_accum_in_address0), + .accum_in_ce0(tdf11_accum_2_U0_accum_in_ce0), + .accum_in_q0(accum1_out_0_t_q0) +); + +td_fused_top_Block_entry_proc_proc441 Block_entry_proc_proc441_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(Block_entry_proc_proc441_U0_ap_start), + .ap_done(Block_entry_proc_proc441_U0_ap_done), + .ap_continue(Block_entry_proc_proc441_U0_ap_continue), + .ap_idle(Block_entry_proc_proc441_U0_ap_idle), + .ap_ready(Block_entry_proc_proc441_U0_ap_ready), + .tmp(tmp_channel_dout), + .ap_return(Block_entry_proc_proc441_U0_ap_return) +); + +td_fused_top_tdf11_adjust tdf11_adjust_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf11_adjust_U0_ap_start), + .ap_done(tdf11_adjust_U0_ap_done), + .ap_continue(tdf11_adjust_U0_ap_continue), + .ap_idle(tdf11_adjust_U0_ap_idle), + .ap_ready(tdf11_adjust_U0_ap_ready), + .sums_read(sums_0_dout), + .adjustments_address0(tdf11_adjust_U0_adjustments_address0), + .adjustments_ce0(tdf11_adjust_U0_adjustments_ce0), + .adjustments_q0(l1_adjustments_q0), + .indices_23_dout(indices_23_c1_dout), + .indices_23_empty_n(indices_23_c1_empty_n), + .indices_23_read(tdf11_adjust_U0_indices_23_read), + .indices_23_out_din(tdf11_adjust_U0_indices_23_out_din), + .indices_23_out_full_n(indices_23_c4_full_n), + .indices_23_out_write(tdf11_adjust_U0_indices_23_out_write), + .ap_return(tdf11_adjust_U0_ap_return) +); + +td_fused_top_tdf11_l2_multiply72 tdf11_l2_multiply72_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf11_l2_multiply72_U0_ap_start), + .ap_done(tdf11_l2_multiply72_U0_ap_done), + .ap_continue(tdf11_l2_multiply72_U0_ap_continue), + .ap_idle(tdf11_l2_multiply72_U0_ap_idle), + .ap_ready(tdf11_l2_multiply72_U0_ap_ready), + .intermediate_fmaps_read(intermediate_fmaps_0_dout), + .l2_filter_data_address0(tdf11_l2_multiply72_U0_l2_filter_data_address0), + .l2_filter_data_ce0(tdf11_l2_multiply72_U0_l2_filter_data_ce0), + .l2_filter_data_q0(l2_filter_data_q0), + .l2_products_address0(tdf11_l2_multiply72_U0_l2_products_address0), + .l2_products_ce0(tdf11_l2_multiply72_U0_l2_products_ce0), + .l2_products_we0(tdf11_l2_multiply72_U0_l2_products_we0), + .l2_products_d0(tdf11_l2_multiply72_U0_l2_products_d0), + .indices_23_dout(indices_23_c4_dout), + .indices_23_empty_n(indices_23_c4_empty_n), + .indices_23_read(tdf11_l2_multiply72_U0_indices_23_read) +); + +td_fused_top_tdf11_l2_writeOutputs_171 tdf11_l2_writeOutputs_171_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf11_l2_writeOutputs_171_U0_ap_start), + .ap_done(tdf11_l2_writeOutputs_171_U0_ap_done), + .ap_continue(tdf11_l2_writeOutputs_171_U0_ap_continue), + .ap_idle(tdf11_l2_writeOutputs_171_U0_ap_idle), + .ap_ready(tdf11_l2_writeOutputs_171_U0_ap_ready), + .indices_01_dout(indices_01_c2_dout), + .indices_01_empty_n(indices_01_c2_empty_n), + .indices_01_read(tdf11_l2_writeOutputs_171_U0_indices_01_read), + .indices_12_dout(indices_12_c3_dout), + .indices_12_empty_n(indices_12_c3_empty_n), + .indices_12_read(tdf11_l2_writeOutputs_171_U0_indices_12_read), + .write4_dout(write4_c_dout), + .write4_empty_n(write4_c_empty_n), + .write4_read(tdf11_l2_writeOutputs_171_U0_write4_read), + .l2_partial_sums_address0(tdf11_l2_writeOutputs_171_U0_l2_partial_sums_address0), + .l2_partial_sums_ce0(tdf11_l2_writeOutputs_171_U0_l2_partial_sums_ce0), + .l2_partial_sums_q0(l2_products_t_q0), + .out_data_address1(tdf11_l2_writeOutputs_171_U0_out_data_address1), + .out_data_ce1(tdf11_l2_writeOutputs_171_U0_out_data_ce1), + .out_data_we1(tdf11_l2_writeOutputs_171_U0_out_data_we1), + .out_data_d1(tdf11_l2_writeOutputs_171_U0_out_data_d1), + .l2_adjustments_address0(tdf11_l2_writeOutputs_171_U0_l2_adjustments_address0), + .l2_adjustments_ce0(tdf11_l2_writeOutputs_171_U0_l2_adjustments_ce0), + .l2_adjustments_q0(l2_adjustments_q0) +); + +td_fused_top_fifo_w16_d2_S_x8 indices_01_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf11_readInputs75_U0_indices_01_read), + .if_dout(indices_01_c_dout), + .if_full_n(indices_01_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf11_get_next_ijk_U0_indices_0_write), + .if_din(tdf11_get_next_ijk_U0_indices_0_din) +); + +td_fused_top_fifo_w16_d2_S_x8 indices_12_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf11_readInputs75_U0_indices_12_read), + .if_dout(indices_12_c_dout), + .if_full_n(indices_12_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf11_get_next_ijk_U0_indices_1_write), + .if_din(tdf11_get_next_ijk_U0_indices_1_din) +); + +td_fused_top_fifo_w9_d2_S_x indices_23_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf11_readFilters74_U0_indices_23_read), + .if_dout(indices_23_c_dout), + .if_full_n(indices_23_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf11_get_next_ijk_U0_indices_2_out_write), + .if_din(tdf11_get_next_ijk_U0_indices_2_out_din) +); + +td_fused_top_fifo_w9_d7_S indices_23_c1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf11_adjust_U0_indices_23_read), + .if_dout(indices_23_c1_dout), + .if_full_n(indices_23_c1_full_n), + .if_write_ce(1'b1), + .if_write(tdf11_get_next_ijk_U0_indices_2_out1_write), + .if_din(tdf11_get_next_ijk_U0_indices_2_out1_din) +); + +td_fused_top_fifo_w1_d9_S_x2 write4_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(write4_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf11_l2_writeOutputs_171_U0_write4_read), + .if_dout(write4_c_dout), + .if_full_n(write4_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf11_get_next_ijk_U0_write_r_write), + .if_din(write4_c_din) +); + +td_fused_top_fifo_w4_d8_S_x1 indices_01_c2_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c2_empty_n), + .if_read_ce(1'b1), + .if_read(tdf11_l2_writeOutputs_171_U0_indices_01_read), + .if_dout(indices_01_c2_dout), + .if_full_n(indices_01_c2_full_n), + .if_write_ce(1'b1), + .if_write(tdf11_readInputs75_U0_indices_01_out_write), + .if_din(tdf11_readInputs75_U0_indices_01_out_din) +); + +td_fused_top_fifo_w8_d8_S_x0 indices_12_c3_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c3_empty_n), + .if_read_ce(1'b1), + .if_read(tdf11_l2_writeOutputs_171_U0_indices_12_read), + .if_dout(indices_12_c3_dout), + .if_full_n(indices_12_c3_full_n), + .if_write_ce(1'b1), + .if_write(tdf11_readInputs75_U0_indices_12_out_write), + .if_din(tdf11_readInputs75_U0_indices_12_out_din) +); + +td_fused_top_fifo_w16_d2_S_x8 tmp_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(tmp_channel_empty_n), + .if_read_ce(1'b1), + .if_read(Block_entry_proc_proc441_U0_ap_ready), + .if_dout(tmp_channel_dout), + .if_full_n(tmp_channel_full_n), + .if_write_ce(1'b1), + .if_write(tdf11_accum_2_U0_ap_done), + .if_din(tdf11_accum_2_U0_accum_in_22) +); + +td_fused_top_fifo_w16_d2_S_x8 sums_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(sums_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf11_adjust_U0_ap_ready), + .if_dout(sums_0_dout), + .if_full_n(sums_0_full_n), + .if_write_ce(1'b1), + .if_write(Block_entry_proc_proc441_U0_ap_done), + .if_din(Block_entry_proc_proc441_U0_ap_return) +); + +td_fused_top_fifo_w9_d2_S_x indices_23_c4_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c4_empty_n), + .if_read_ce(1'b1), + .if_read(tdf11_l2_multiply72_U0_indices_23_read), + .if_dout(indices_23_c4_dout), + .if_full_n(indices_23_c4_full_n), + .if_write_ce(1'b1), + .if_write(tdf11_adjust_U0_indices_23_out_write), + .if_din(tdf11_adjust_U0_indices_23_out_din) +); + +td_fused_top_fifo_w16_d2_S_x8 intermediate_fmaps_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(intermediate_fmaps_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf11_l2_multiply72_U0_ap_ready), + .if_dout(intermediate_fmaps_0_dout), + .if_full_n(intermediate_fmaps_0_full_n), + .if_write_ce(1'b1), + .if_write(tdf11_adjust_U0_ap_done), + .if_din(tdf11_adjust_U0_ap_return) +); + +td_fused_top_start_for_tdf11_readFilters74_U0 start_for_tdf11_readFilters74_U0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(start_for_tdf11_readFilters74_U0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf11_readFilters74_U0_ap_ready), + .if_dout(start_for_tdf11_readFilters74_U0_dout), + .if_full_n(start_for_tdf11_readFilters74_U0_full_n), + .if_write_ce(1'b1), + .if_write(tdf11_get_next_ijk_U0_start_write), + .if_din(start_for_tdf11_readFilters74_U0_din) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf11_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf11_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf11_get_next_ijk_U0_ap_ready <= ap_sync_tdf11_get_next_ijk_U0_ap_ready; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf11_readInputs75_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf11_readInputs75_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf11_readInputs75_U0_ap_ready <= ap_sync_tdf11_readInputs75_U0_ap_ready; + end + end +end + +assign Block_entry_proc_proc441_U0_ap_continue = sums_0_full_n; + +assign Block_entry_proc_proc441_U0_ap_start = tmp_channel_empty_n; + +assign Block_entry_proc_proc441_U0_start_full_n = 1'b1; + +assign Block_entry_proc_proc441_U0_start_write = 1'b0; + +assign ap_channel_done_accum1_out_0 = tdf11_accum_1_U0_ap_done; + +assign ap_channel_done_ifmap_vec = tdf11_readInputs75_U0_ap_done; + +assign ap_channel_done_intermediate_fmaps_0 = tdf11_adjust_U0_ap_done; + +assign ap_channel_done_l2_products = tdf11_l2_multiply72_U0_ap_done; + +assign ap_channel_done_products_0 = tdf11_dot_product_U0_ap_done; + +assign ap_channel_done_sums_0 = Block_entry_proc_proc441_U0_ap_done; + +assign ap_channel_done_tmp_channel = tdf11_accum_2_U0_ap_done; + +assign ap_channel_done_weight_vecs_0 = tdf11_readFilters74_U0_ap_done; + +assign ap_done = tdf11_l2_writeOutputs_171_U0_ap_done; + +assign ap_idle = (tdf11_readInputs75_U0_ap_idle & tdf11_readFilters74_U0_ap_idle & tdf11_l2_writeOutputs_171_U0_ap_idle & tdf11_l2_multiply72_U0_ap_idle & tdf11_get_next_ijk_U0_ap_idle & tdf11_dot_product_U0_ap_idle & tdf11_adjust_U0_ap_idle & tdf11_accum_2_U0_ap_idle & tdf11_accum_1_U0_ap_idle & (intermediate_fmaps_0_empty_n ^ 1'b1) & (sums_0_empty_n ^ 1'b1) & (tmp_channel_empty_n ^ 1'b1) & (l2_products_t_empty_n ^ 1'b1) & (products_0_t_empty_n ^ 1'b1) & (weight_vecs_0_t_empty_n ^ 1'b1) & (ifmap_vec_t_empty_n ^ 1'b1) & (1'b1 ^ accum1_out_0_t_empty_n) & Block_entry_proc_proc441_U0_ap_idle); + +assign ap_ready = ap_sync_ready; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = tdf11_l2_writeOutputs_171_U0_ap_done; + +assign ap_sync_ready = (ap_sync_tdf11_readInputs75_U0_ap_ready & ap_sync_tdf11_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf11_get_next_ijk_U0_ap_ready = (tdf11_get_next_ijk_U0_ap_ready | ap_sync_reg_tdf11_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf11_readInputs75_U0_ap_ready = (tdf11_readInputs75_U0_ap_ready | ap_sync_reg_tdf11_readInputs75_U0_ap_ready); + +assign in_data_address0 = tdf11_readInputs75_U0_in_data_address0; + +assign in_data_address1 = 12'd0; + +assign in_data_ce0 = tdf11_readInputs75_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = tdf11_readInputs75_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign l1_adjustments_address0 = tdf11_adjust_U0_adjustments_address0; + +assign l1_adjustments_address1 = 9'd0; + +assign l1_adjustments_ce0 = tdf11_adjust_U0_adjustments_ce0; + +assign l1_adjustments_ce1 = 1'b0; + +assign l1_adjustments_d0 = 48'd0; + +assign l1_adjustments_d1 = 48'd0; + +assign l1_adjustments_we0 = 1'b0; + +assign l1_adjustments_we1 = 1'b0; + +assign l1_filter_data_address0 = tdf11_readFilters74_U0_filter_data_address0; + +assign l1_filter_data_address1 = 17'd0; + +assign l1_filter_data_ce0 = tdf11_readFilters74_U0_filter_data_ce0; + +assign l1_filter_data_ce1 = 1'b0; + +assign l1_filter_data_d0 = 64'd0; + +assign l1_filter_data_d1 = 64'd0; + +assign l1_filter_data_we0 = 1'b0; + +assign l1_filter_data_we1 = 1'b0; + +assign l2_adjustments_address0 = tdf11_l2_writeOutputs_171_U0_l2_adjustments_address0; + +assign l2_adjustments_address1 = 7'd0; + +assign l2_adjustments_ce0 = tdf11_l2_writeOutputs_171_U0_l2_adjustments_ce0; + +assign l2_adjustments_ce1 = 1'b0; + +assign l2_adjustments_d0 = 48'd0; + +assign l2_adjustments_d1 = 48'd0; + +assign l2_adjustments_we0 = 1'b0; + +assign l2_adjustments_we1 = 1'b0; + +assign l2_filter_data_address0 = tdf11_l2_multiply72_U0_l2_filter_data_address0; + +assign l2_filter_data_address1 = 16'd0; + +assign l2_filter_data_ce0 = tdf11_l2_multiply72_U0_l2_filter_data_ce0; + +assign l2_filter_data_ce1 = 1'b0; + +assign l2_filter_data_d0 = 16'd0; + +assign l2_filter_data_d1 = 16'd0; + +assign l2_filter_data_we0 = 1'b0; + +assign l2_filter_data_we1 = 1'b0; + +assign out_data_address0 = 13'd0; + +assign out_data_address1 = tdf11_l2_writeOutputs_171_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = tdf11_l2_writeOutputs_171_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = tdf11_l2_writeOutputs_171_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = tdf11_l2_writeOutputs_171_U0_out_data_we1; + +assign out_data_write = tdf11_l2_writeOutputs_171_U0_out_data_write; + +assign products_0_t_d1 = 16'd0; + +assign products_0_t_we1 = 1'b0; + +assign start_for_tdf11_readFilters74_U0_din = 1'b1; + +assign tdf11_accum_1_U0_accum_out_full_n = accum1_out_0_i_full_n; + +assign tdf11_accum_1_U0_ap_continue = accum1_out_0_i_full_n; + +assign tdf11_accum_1_U0_ap_start = products_0_t_empty_n; + +assign tdf11_accum_1_U0_start_full_n = 1'b1; + +assign tdf11_accum_1_U0_start_write = 1'b0; + +assign tdf11_accum_2_U0_ap_continue = tmp_channel_full_n; + +assign tdf11_accum_2_U0_ap_start = accum1_out_0_t_empty_n; + +assign tdf11_accum_2_U0_start_full_n = 1'b1; + +assign tdf11_accum_2_U0_start_write = 1'b0; + +assign tdf11_adjust_U0_ap_continue = intermediate_fmaps_0_full_n; + +assign tdf11_adjust_U0_ap_start = sums_0_empty_n; + +assign tdf11_adjust_U0_start_full_n = 1'b1; + +assign tdf11_adjust_U0_start_write = 1'b0; + +assign tdf11_dot_product_U0_ap_continue = products_0_i_full_n; + +assign tdf11_dot_product_U0_ap_start = (weight_vecs_0_t_empty_n & ifmap_vec_t_empty_n); + +assign tdf11_dot_product_U0_products_0_full_n = products_0_i_full_n; + +assign tdf11_dot_product_U0_start_full_n = 1'b1; + +assign tdf11_dot_product_U0_start_write = 1'b0; + +assign tdf11_get_next_ijk_U0_ap_continue = 1'b1; + +assign tdf11_get_next_ijk_U0_ap_start = ((ap_sync_reg_tdf11_get_next_ijk_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf11_l2_multiply72_U0_ap_continue = l2_products_i_full_n; + +assign tdf11_l2_multiply72_U0_ap_start = intermediate_fmaps_0_empty_n; + +assign tdf11_l2_multiply72_U0_l2_products_full_n = l2_products_i_full_n; + +assign tdf11_l2_multiply72_U0_start_full_n = 1'b1; + +assign tdf11_l2_multiply72_U0_start_write = 1'b0; + +assign tdf11_l2_writeOutputs_171_U0_ap_continue = ap_continue; + +assign tdf11_l2_writeOutputs_171_U0_ap_start = l2_products_t_empty_n; + +assign tdf11_l2_writeOutputs_171_U0_out_data_full_n = out_data_full_n; + +assign tdf11_l2_writeOutputs_171_U0_out_data_write = 1'b0; + +assign tdf11_l2_writeOutputs_171_U0_start_full_n = 1'b1; + +assign tdf11_l2_writeOutputs_171_U0_start_write = 1'b0; + +assign tdf11_readFilters74_U0_ap_continue = weight_vecs_0_i_full_n; + +assign tdf11_readFilters74_U0_ap_start = start_for_tdf11_readFilters74_U0_empty_n; + +assign tdf11_readFilters74_U0_start_full_n = 1'b1; + +assign tdf11_readFilters74_U0_start_write = 1'b0; + +assign tdf11_readFilters74_U0_weight_vecs_0_full_n = weight_vecs_0_i_full_n; + +assign tdf11_readInputs75_U0_ap_continue = ifmap_vec_i_full_n; + +assign tdf11_readInputs75_U0_ap_start = ((ap_sync_reg_tdf11_readInputs75_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf11_readInputs75_U0_ifmap_vec_full_n = ifmap_vec_i_full_n; + +assign tdf11_readInputs75_U0_in_data_full_n = in_data_empty_n; + +assign tdf11_readInputs75_U0_in_data_write = 1'b0; + +assign tdf11_readInputs75_U0_start_full_n = 1'b1; + +assign tdf11_readInputs75_U0_start_write = 1'b0; + +assign write4_c_din = tdf11_get_next_ijk_U0_write_r_din; + +endmodule //td_fused_top_dataflow_in_loop_TOP_LOOP38270 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38364_accum1_out_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 3; +parameter MEM_SIZE = 8; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38364_accum1_out_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd8; +parameter AddressWidth = 32'd3; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38364_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38364_accum1_out_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38364_accum1_out_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 3, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP38364_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38364_accum1_out_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP38364_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38364_accum1_out_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38364_ifmap_vec_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 10; +parameter MEM_SIZE = 576; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38364_ifmap_vec_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd576; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38364_ifmap_vec_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38364_ifmap_vec_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38364_ifmap_vec +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 10, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP38364_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38364_ifmap_vec_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP38364_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38364_ifmap_vec_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38364_l2_products_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 7; +parameter MEM_SIZE = 128; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38364_l2_products_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd128; +parameter AddressWidth = 32'd7; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38364_l2_products_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38364_l2_products_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38364_l2_products +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 6, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP38364_l2_products_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38364_l2_products_memcore_U ( + .reset ( reset ), + .clk ( clk ), + .address0 ( memcore_iaddr ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + .address1 ( memcore_taddr ), + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .d1 ( t_d0 ), + .q1 ( t_q0 ) + +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38364_products_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 10; +parameter MEM_SIZE = 576; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP38364_products_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd576; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP38364_products_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38364_products_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38364_products_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 10, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire [AddressWidth-1:0] i_address1, + output wire [DataWidth-1:0] i_q1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire [AddressWidth-1:0] t_address1, + output wire [DataWidth-1:0] t_q1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_q1_0, buf_q1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP38364_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38364_products_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .q1 ( buf_q1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP38364_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38364_products_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .q1 ( buf_q1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign i_q1 = (prev_iptr == 1'b1 ? buf_q1_1 : buf_q1_0); +assign t_q1 = reg_valid1 ? reg_q1 : (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// reg_q1 and reg_valid1 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q1 <= 1'b0; + reg_valid1 <= 1'b0; + end else if (!t_ce1 && !reg_valid1) begin + reg_q1 <= (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + reg_valid1 <= 1'b1; + end else if (t_ce1) begin + reg_valid1 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP38364 ( + ap_clk, + ap_rst, + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + l1_filter_data_address0, + l1_filter_data_ce0, + l1_filter_data_d0, + l1_filter_data_q0, + l1_filter_data_we0, + l1_filter_data_address1, + l1_filter_data_ce1, + l1_filter_data_d1, + l1_filter_data_q1, + l1_filter_data_we1, + l1_adjustments_address0, + l1_adjustments_ce0, + l1_adjustments_d0, + l1_adjustments_q0, + l1_adjustments_we0, + l1_adjustments_address1, + l1_adjustments_ce1, + l1_adjustments_d1, + l1_adjustments_q1, + l1_adjustments_we1, + l2_filter_data_address0, + l2_filter_data_ce0, + l2_filter_data_d0, + l2_filter_data_q0, + l2_filter_data_we0, + l2_filter_data_address1, + l2_filter_data_ce1, + l2_filter_data_d1, + l2_filter_data_q1, + l2_filter_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_d0, + l2_adjustments_q0, + l2_adjustments_we0, + l2_adjustments_address1, + l2_adjustments_ce1, + l2_adjustments_d1, + l2_adjustments_q1, + l2_adjustments_we1, + ap_start, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +input ap_clk; +input ap_rst; +output [11:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [11:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [16:0] l1_filter_data_address0; +output l1_filter_data_ce0; +output [63:0] l1_filter_data_d0; +input [63:0] l1_filter_data_q0; +output l1_filter_data_we0; +output [16:0] l1_filter_data_address1; +output l1_filter_data_ce1; +output [63:0] l1_filter_data_d1; +input [63:0] l1_filter_data_q1; +output l1_filter_data_we1; +output [8:0] l1_adjustments_address0; +output l1_adjustments_ce0; +output [47:0] l1_adjustments_d0; +input [47:0] l1_adjustments_q0; +output l1_adjustments_we0; +output [8:0] l1_adjustments_address1; +output l1_adjustments_ce1; +output [47:0] l1_adjustments_d1; +input [47:0] l1_adjustments_q1; +output l1_adjustments_we1; +output [14:0] l2_filter_data_address0; +output l2_filter_data_ce0; +output [15:0] l2_filter_data_d0; +input [15:0] l2_filter_data_q0; +output l2_filter_data_we0; +output [14:0] l2_filter_data_address1; +output l2_filter_data_ce1; +output [15:0] l2_filter_data_d1; +input [15:0] l2_filter_data_q1; +output l2_filter_data_we1; +output [11:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [11:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [5:0] l2_adjustments_address0; +output l2_adjustments_ce0; +output [47:0] l2_adjustments_d0; +input [47:0] l2_adjustments_q0; +output l2_adjustments_we0; +output [5:0] l2_adjustments_address1; +output l2_adjustments_ce1; +output [47:0] l2_adjustments_d1; +input [47:0] l2_adjustments_q1; +output l2_adjustments_we1; +input ap_start; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +wire [15:0] ifmap_vec_i_q0; +wire [15:0] ifmap_vec_t_q0; +wire [15:0] weight_vecs_0_i_q0; +wire [15:0] weight_vecs_0_t_q0; +wire [15:0] products_0_i_q0; +wire [15:0] products_0_i_q1; +wire [15:0] products_0_t_q0; +wire [15:0] products_0_t_q1; +wire [15:0] accum1_out_0_i_q0; +wire [15:0] accum1_out_0_t_q0; +wire [15:0] l2_products_i_q0; +wire [15:0] l2_products_t_q0; +wire tdf10_get_next_ijk_U0_ap_start; +wire tdf10_get_next_ijk_U0_ap_done; +wire tdf10_get_next_ijk_U0_ap_continue; +wire tdf10_get_next_ijk_U0_ap_idle; +wire tdf10_get_next_ijk_U0_ap_ready; +wire tdf10_get_next_ijk_U0_start_out; +wire tdf10_get_next_ijk_U0_start_write; +wire [15:0] tdf10_get_next_ijk_U0_indices_0_din; +wire tdf10_get_next_ijk_U0_indices_0_write; +wire [15:0] tdf10_get_next_ijk_U0_indices_1_din; +wire tdf10_get_next_ijk_U0_indices_1_write; +wire [8:0] tdf10_get_next_ijk_U0_indices_2_out_din; +wire tdf10_get_next_ijk_U0_indices_2_out_write; +wire [14:0] tdf10_get_next_ijk_U0_indices_2_out1_din; +wire tdf10_get_next_ijk_U0_indices_2_out1_write; +wire tdf10_get_next_ijk_U0_write_r_din; +wire tdf10_get_next_ijk_U0_write_r_write; +wire tdf10_readInputs69_U0_ap_start; +wire tdf10_readInputs69_U0_ap_done; +wire tdf10_readInputs69_U0_ap_continue; +wire tdf10_readInputs69_U0_ap_idle; +wire tdf10_readInputs69_U0_ap_ready; +wire [11:0] tdf10_readInputs69_U0_in_data_address0; +wire tdf10_readInputs69_U0_in_data_ce0; +wire tdf10_readInputs69_U0_indices_01_read; +wire tdf10_readInputs69_U0_indices_12_read; +wire [9:0] tdf10_readInputs69_U0_ifmap_vec_address0; +wire tdf10_readInputs69_U0_ifmap_vec_ce0; +wire tdf10_readInputs69_U0_ifmap_vec_we0; +wire [15:0] tdf10_readInputs69_U0_ifmap_vec_d0; +wire [9:0] tdf10_readInputs69_U0_ifmap_vec_address1; +wire tdf10_readInputs69_U0_ifmap_vec_ce1; +wire tdf10_readInputs69_U0_ifmap_vec_we1; +wire [15:0] tdf10_readInputs69_U0_ifmap_vec_d1; +wire [3:0] tdf10_readInputs69_U0_indices_01_out_din; +wire tdf10_readInputs69_U0_indices_01_out_write; +wire [7:0] tdf10_readInputs69_U0_indices_12_out_din; +wire tdf10_readInputs69_U0_indices_12_out_write; +wire tdf10_readInputs69_U0_in_data_full_n; +wire tdf10_readInputs69_U0_in_data_write; +wire ap_channel_done_ifmap_vec; +wire tdf10_readInputs69_U0_ifmap_vec_full_n; +wire tdf10_readFilters68_U0_ap_start; +wire tdf10_readFilters68_U0_ap_done; +wire tdf10_readFilters68_U0_ap_continue; +wire tdf10_readFilters68_U0_ap_idle; +wire tdf10_readFilters68_U0_ap_ready; +wire [16:0] tdf10_readFilters68_U0_filter_data_address0; +wire tdf10_readFilters68_U0_filter_data_ce0; +wire tdf10_readFilters68_U0_indices_23_read; +wire [9:0] tdf10_readFilters68_U0_weight_vecs_0_address0; +wire tdf10_readFilters68_U0_weight_vecs_0_ce0; +wire tdf10_readFilters68_U0_weight_vecs_0_we0; +wire [15:0] tdf10_readFilters68_U0_weight_vecs_0_d0; +wire [9:0] tdf10_readFilters68_U0_weight_vecs_0_address1; +wire tdf10_readFilters68_U0_weight_vecs_0_ce1; +wire tdf10_readFilters68_U0_weight_vecs_0_we1; +wire [15:0] tdf10_readFilters68_U0_weight_vecs_0_d1; +wire ap_channel_done_weight_vecs_0; +wire tdf10_readFilters68_U0_weight_vecs_0_full_n; +wire tdf10_dot_product_U0_ap_start; +wire tdf10_dot_product_U0_ap_done; +wire tdf10_dot_product_U0_ap_continue; +wire tdf10_dot_product_U0_ap_idle; +wire tdf10_dot_product_U0_ap_ready; +wire [9:0] tdf10_dot_product_U0_ifmap_vec_address0; +wire tdf10_dot_product_U0_ifmap_vec_ce0; +wire [9:0] tdf10_dot_product_U0_weight_vecs_0_address0; +wire tdf10_dot_product_U0_weight_vecs_0_ce0; +wire [9:0] tdf10_dot_product_U0_products_0_address0; +wire tdf10_dot_product_U0_products_0_ce0; +wire tdf10_dot_product_U0_products_0_we0; +wire [15:0] tdf10_dot_product_U0_products_0_d0; +wire ap_channel_done_products_0; +wire tdf10_dot_product_U0_products_0_full_n; +wire tdf10_accum_1_U0_ap_start; +wire tdf10_accum_1_U0_ap_done; +wire tdf10_accum_1_U0_ap_continue; +wire tdf10_accum_1_U0_ap_idle; +wire tdf10_accum_1_U0_ap_ready; +wire [9:0] tdf10_accum_1_U0_accum_in_0_address0; +wire tdf10_accum_1_U0_accum_in_0_ce0; +wire [9:0] tdf10_accum_1_U0_accum_in_0_address1; +wire tdf10_accum_1_U0_accum_in_0_ce1; +wire [2:0] tdf10_accum_1_U0_accum_out_address0; +wire tdf10_accum_1_U0_accum_out_ce0; +wire tdf10_accum_1_U0_accum_out_we0; +wire [15:0] tdf10_accum_1_U0_accum_out_d0; +wire [2:0] tdf10_accum_1_U0_accum_out_address1; +wire tdf10_accum_1_U0_accum_out_ce1; +wire tdf10_accum_1_U0_accum_out_we1; +wire [15:0] tdf10_accum_1_U0_accum_out_d1; +wire ap_channel_done_accum1_out_0; +wire tdf10_accum_1_U0_accum_out_full_n; +wire tdf10_accum_2_U0_ap_start; +wire tdf10_accum_2_U0_ap_done; +wire tdf10_accum_2_U0_ap_continue; +wire tdf10_accum_2_U0_ap_idle; +wire tdf10_accum_2_U0_ap_ready; +wire [15:0] tdf10_accum_2_U0_accum_in_24; +wire tdf10_accum_2_U0_accum_in_24_ap_vld; +wire [2:0] tdf10_accum_2_U0_accum_in_address0; +wire tdf10_accum_2_U0_accum_in_ce0; +wire ap_channel_done_tmp_channel; +wire tmp_channel_full_n; +wire Block_entry_proc_proc435_U0_ap_start; +wire Block_entry_proc_proc435_U0_ap_done; +wire Block_entry_proc_proc435_U0_ap_continue; +wire Block_entry_proc_proc435_U0_ap_idle; +wire Block_entry_proc_proc435_U0_ap_ready; +wire [15:0] Block_entry_proc_proc435_U0_ap_return; +wire ap_channel_done_sums_0; +wire sums_0_full_n; +wire tdf10_adjust_U0_ap_start; +wire tdf10_adjust_U0_ap_done; +wire tdf10_adjust_U0_ap_continue; +wire tdf10_adjust_U0_ap_idle; +wire tdf10_adjust_U0_ap_ready; +wire [8:0] tdf10_adjust_U0_adjustments_address0; +wire tdf10_adjust_U0_adjustments_ce0; +wire tdf10_adjust_U0_indices_23_read; +wire [14:0] tdf10_adjust_U0_indices_23_out_din; +wire tdf10_adjust_U0_indices_23_out_write; +wire [15:0] tdf10_adjust_U0_ap_return; +wire ap_channel_done_intermediate_fmaps_0; +wire intermediate_fmaps_0_full_n; +wire tdf10_l2_multiply66_U0_ap_start; +wire tdf10_l2_multiply66_U0_ap_done; +wire tdf10_l2_multiply66_U0_ap_continue; +wire tdf10_l2_multiply66_U0_ap_idle; +wire tdf10_l2_multiply66_U0_ap_ready; +wire [14:0] tdf10_l2_multiply66_U0_l2_filter_data_address0; +wire tdf10_l2_multiply66_U0_l2_filter_data_ce0; +wire [5:0] tdf10_l2_multiply66_U0_l2_products_address0; +wire tdf10_l2_multiply66_U0_l2_products_ce0; +wire tdf10_l2_multiply66_U0_l2_products_we0; +wire [15:0] tdf10_l2_multiply66_U0_l2_products_d0; +wire tdf10_l2_multiply66_U0_indices_23_read; +wire ap_channel_done_l2_products; +wire tdf10_l2_multiply66_U0_l2_products_full_n; +wire tdf10_l2_writeOutputs_165_U0_ap_start; +wire tdf10_l2_writeOutputs_165_U0_ap_done; +wire tdf10_l2_writeOutputs_165_U0_ap_continue; +wire tdf10_l2_writeOutputs_165_U0_ap_idle; +wire tdf10_l2_writeOutputs_165_U0_ap_ready; +wire tdf10_l2_writeOutputs_165_U0_indices_01_read; +wire tdf10_l2_writeOutputs_165_U0_indices_12_read; +wire tdf10_l2_writeOutputs_165_U0_write4_read; +wire [5:0] tdf10_l2_writeOutputs_165_U0_l2_partial_sums_address0; +wire tdf10_l2_writeOutputs_165_U0_l2_partial_sums_ce0; +wire [11:0] tdf10_l2_writeOutputs_165_U0_out_data_address1; +wire tdf10_l2_writeOutputs_165_U0_out_data_ce1; +wire tdf10_l2_writeOutputs_165_U0_out_data_we1; +wire [63:0] tdf10_l2_writeOutputs_165_U0_out_data_d1; +wire [5:0] tdf10_l2_writeOutputs_165_U0_l2_adjustments_address0; +wire tdf10_l2_writeOutputs_165_U0_l2_adjustments_ce0; +wire tdf10_l2_writeOutputs_165_U0_out_data_full_n; +wire tdf10_l2_writeOutputs_165_U0_out_data_write; +wire ap_sync_continue; +wire ifmap_vec_i_full_n; +wire ifmap_vec_t_empty_n; +wire weight_vecs_0_i_full_n; +wire weight_vecs_0_t_empty_n; +wire products_0_i_full_n; +wire products_0_t_empty_n; +wire [15:0] products_0_t_d1; +wire products_0_t_we1; +wire accum1_out_0_i_full_n; +wire accum1_out_0_t_empty_n; +wire l2_products_i_full_n; +wire l2_products_t_empty_n; +wire indices_01_c_full_n; +wire [15:0] indices_01_c_dout; +wire indices_01_c_empty_n; +wire indices_12_c_full_n; +wire [15:0] indices_12_c_dout; +wire indices_12_c_empty_n; +wire indices_23_c_full_n; +wire [8:0] indices_23_c_dout; +wire indices_23_c_empty_n; +wire indices_23_c1_full_n; +wire [14:0] indices_23_c1_dout; +wire indices_23_c1_empty_n; +wire [0:0] write4_c_din; +wire write4_c_full_n; +wire [0:0] write4_c_dout; +wire write4_c_empty_n; +wire indices_01_c2_full_n; +wire [3:0] indices_01_c2_dout; +wire indices_01_c2_empty_n; +wire indices_12_c3_full_n; +wire [7:0] indices_12_c3_dout; +wire indices_12_c3_empty_n; +wire [15:0] tmp_channel_dout; +wire tmp_channel_empty_n; +wire [15:0] sums_0_dout; +wire sums_0_empty_n; +wire indices_23_c4_full_n; +wire [14:0] indices_23_c4_dout; +wire indices_23_c4_empty_n; +wire [15:0] intermediate_fmaps_0_dout; +wire intermediate_fmaps_0_empty_n; +wire ap_sync_done; +wire ap_sync_ready; +reg ap_sync_reg_tdf10_get_next_ijk_U0_ap_ready; +wire ap_sync_tdf10_get_next_ijk_U0_ap_ready; +reg ap_sync_reg_tdf10_readInputs69_U0_ap_ready; +wire ap_sync_tdf10_readInputs69_U0_ap_ready; +wire [0:0] start_for_tdf10_readFilters68_U0_din; +wire start_for_tdf10_readFilters68_U0_full_n; +wire [0:0] start_for_tdf10_readFilters68_U0_dout; +wire start_for_tdf10_readFilters68_U0_empty_n; +wire tdf10_readInputs69_U0_start_full_n; +wire tdf10_readInputs69_U0_start_write; +wire tdf10_readFilters68_U0_start_full_n; +wire tdf10_readFilters68_U0_start_write; +wire tdf10_dot_product_U0_start_full_n; +wire tdf10_dot_product_U0_start_write; +wire tdf10_accum_1_U0_start_full_n; +wire tdf10_accum_1_U0_start_write; +wire tdf10_accum_2_U0_start_full_n; +wire tdf10_accum_2_U0_start_write; +wire Block_entry_proc_proc435_U0_start_full_n; +wire Block_entry_proc_proc435_U0_start_write; +wire tdf10_adjust_U0_start_full_n; +wire tdf10_adjust_U0_start_write; +wire tdf10_l2_multiply66_U0_start_full_n; +wire tdf10_l2_multiply66_U0_start_write; +wire tdf10_l2_writeOutputs_165_U0_start_full_n; +wire tdf10_l2_writeOutputs_165_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_sync_reg_tdf10_get_next_ijk_U0_ap_ready = 1'b0; +#0 ap_sync_reg_tdf10_readInputs69_U0_ap_ready = 1'b0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP38364_ifmap_vec #( + .DataWidth( 16 ), + .AddressRange( 576 ), + .AddressWidth( 10 )) +ifmap_vec_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf10_readInputs69_U0_ap_done), + .i_full_n(ifmap_vec_i_full_n), + .i_ce0(tdf10_readInputs69_U0_ifmap_vec_ce0), + .i_we0(tdf10_readInputs69_U0_ifmap_vec_we0), + .i_address0(tdf10_readInputs69_U0_ifmap_vec_address0), + .i_d0(tdf10_readInputs69_U0_ifmap_vec_d0), + .i_q0(ifmap_vec_i_q0), + .i_ce1(tdf10_readInputs69_U0_ifmap_vec_ce1), + .i_we1(tdf10_readInputs69_U0_ifmap_vec_we1), + .i_address1(tdf10_readInputs69_U0_ifmap_vec_address1), + .i_d1(tdf10_readInputs69_U0_ifmap_vec_d1), + .t_ce(1'b1), + .t_read(tdf10_dot_product_U0_ap_ready), + .t_empty_n(ifmap_vec_t_empty_n), + .t_ce0(tdf10_dot_product_U0_ifmap_vec_ce0), + .t_we0(1'b0), + .t_address0(tdf10_dot_product_U0_ifmap_vec_address0), + .t_d0(16'd0), + .t_q0(ifmap_vec_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(10'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP38364_ifmap_vec #( + .DataWidth( 16 ), + .AddressRange( 576 ), + .AddressWidth( 10 )) +weight_vecs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf10_readFilters68_U0_ap_done), + .i_full_n(weight_vecs_0_i_full_n), + .i_ce0(tdf10_readFilters68_U0_weight_vecs_0_ce0), + .i_we0(tdf10_readFilters68_U0_weight_vecs_0_we0), + .i_address0(tdf10_readFilters68_U0_weight_vecs_0_address0), + .i_d0(tdf10_readFilters68_U0_weight_vecs_0_d0), + .i_q0(weight_vecs_0_i_q0), + .i_ce1(tdf10_readFilters68_U0_weight_vecs_0_ce1), + .i_we1(tdf10_readFilters68_U0_weight_vecs_0_we1), + .i_address1(tdf10_readFilters68_U0_weight_vecs_0_address1), + .i_d1(tdf10_readFilters68_U0_weight_vecs_0_d1), + .t_ce(1'b1), + .t_read(tdf10_dot_product_U0_ap_ready), + .t_empty_n(weight_vecs_0_t_empty_n), + .t_ce0(tdf10_dot_product_U0_weight_vecs_0_ce0), + .t_we0(1'b0), + .t_address0(tdf10_dot_product_U0_weight_vecs_0_address0), + .t_d0(16'd0), + .t_q0(weight_vecs_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(10'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP38364_products_0 #( + .DataWidth( 16 ), + .AddressRange( 576 ), + .AddressWidth( 10 )) +products_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf10_dot_product_U0_ap_done), + .i_full_n(products_0_i_full_n), + .i_ce0(tdf10_dot_product_U0_products_0_ce0), + .i_we0(tdf10_dot_product_U0_products_0_we0), + .i_address0(tdf10_dot_product_U0_products_0_address0), + .i_d0(tdf10_dot_product_U0_products_0_d0), + .i_q0(products_0_i_q0), + .i_ce1(1'b0), + .i_address1(10'd0), + .i_q1(products_0_i_q1), + .t_ce(1'b1), + .t_read(tdf10_accum_1_U0_ap_ready), + .t_empty_n(products_0_t_empty_n), + .t_ce0(tdf10_accum_1_U0_accum_in_0_ce0), + .t_we0(1'b0), + .t_address0(tdf10_accum_1_U0_accum_in_0_address0), + .t_d0(16'd0), + .t_q0(products_0_t_q0), + .t_ce1(tdf10_accum_1_U0_accum_in_0_ce1), + .t_address1(tdf10_accum_1_U0_accum_in_0_address1), + .t_q1(products_0_t_q1) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP38364_accum1_out_0 #( + .DataWidth( 16 ), + .AddressRange( 8 ), + .AddressWidth( 3 )) +accum1_out_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf10_accum_1_U0_ap_done), + .i_full_n(accum1_out_0_i_full_n), + .i_ce0(tdf10_accum_1_U0_accum_out_ce0), + .i_we0(tdf10_accum_1_U0_accum_out_we0), + .i_address0(tdf10_accum_1_U0_accum_out_address0), + .i_d0(tdf10_accum_1_U0_accum_out_d0), + .i_q0(accum1_out_0_i_q0), + .i_ce1(tdf10_accum_1_U0_accum_out_ce1), + .i_we1(tdf10_accum_1_U0_accum_out_we1), + .i_address1(tdf10_accum_1_U0_accum_out_address1), + .i_d1(tdf10_accum_1_U0_accum_out_d1), + .t_ce(1'b1), + .t_read(tdf10_accum_2_U0_ap_ready), + .t_empty_n(accum1_out_0_t_empty_n), + .t_ce0(tdf10_accum_2_U0_accum_in_ce0), + .t_we0(1'b0), + .t_address0(tdf10_accum_2_U0_accum_in_address0), + .t_d0(16'd0), + .t_q0(accum1_out_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(3'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP38364_l2_products #( + .DataWidth( 16 ), + .AddressRange( 64 ), + .AddressWidth( 6 )) +l2_products_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf10_l2_multiply66_U0_ap_done), + .i_full_n(l2_products_i_full_n), + .i_ce0(tdf10_l2_multiply66_U0_l2_products_ce0), + .i_we0(tdf10_l2_multiply66_U0_l2_products_we0), + .i_address0(tdf10_l2_multiply66_U0_l2_products_address0), + .i_d0(tdf10_l2_multiply66_U0_l2_products_d0), + .i_q0(l2_products_i_q0), + .t_ce(1'b1), + .t_read(tdf10_l2_writeOutputs_165_U0_ap_ready), + .t_empty_n(l2_products_t_empty_n), + .t_ce0(tdf10_l2_writeOutputs_165_U0_l2_partial_sums_ce0), + .t_we0(1'b0), + .t_address0(tdf10_l2_writeOutputs_165_U0_l2_partial_sums_address0), + .t_d0(16'd0), + .t_q0(l2_products_t_q0) +); + +td_fused_top_tdf10_get_next_ijk tdf10_get_next_ijk_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf10_get_next_ijk_U0_ap_start), + .start_full_n(start_for_tdf10_readFilters68_U0_full_n), + .ap_done(tdf10_get_next_ijk_U0_ap_done), + .ap_continue(tdf10_get_next_ijk_U0_ap_continue), + .ap_idle(tdf10_get_next_ijk_U0_ap_idle), + .ap_ready(tdf10_get_next_ijk_U0_ap_ready), + .start_out(tdf10_get_next_ijk_U0_start_out), + .start_write(tdf10_get_next_ijk_U0_start_write), + .indices_0_din(tdf10_get_next_ijk_U0_indices_0_din), + .indices_0_full_n(indices_01_c_full_n), + .indices_0_write(tdf10_get_next_ijk_U0_indices_0_write), + .indices_1_din(tdf10_get_next_ijk_U0_indices_1_din), + .indices_1_full_n(indices_12_c_full_n), + .indices_1_write(tdf10_get_next_ijk_U0_indices_1_write), + .indices_2_out_din(tdf10_get_next_ijk_U0_indices_2_out_din), + .indices_2_out_full_n(indices_23_c_full_n), + .indices_2_out_write(tdf10_get_next_ijk_U0_indices_2_out_write), + .indices_2_out1_din(tdf10_get_next_ijk_U0_indices_2_out1_din), + .indices_2_out1_full_n(indices_23_c1_full_n), + .indices_2_out1_write(tdf10_get_next_ijk_U0_indices_2_out1_write), + .write_r_din(tdf10_get_next_ijk_U0_write_r_din), + .write_r_full_n(write4_c_full_n), + .write_r_write(tdf10_get_next_ijk_U0_write_r_write) +); + +td_fused_top_tdf10_readInputs69 tdf10_readInputs69_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf10_readInputs69_U0_ap_start), + .ap_done(tdf10_readInputs69_U0_ap_done), + .ap_continue(tdf10_readInputs69_U0_ap_continue), + .ap_idle(tdf10_readInputs69_U0_ap_idle), + .ap_ready(tdf10_readInputs69_U0_ap_ready), + .in_data_address0(tdf10_readInputs69_U0_in_data_address0), + .in_data_ce0(tdf10_readInputs69_U0_in_data_ce0), + .in_data_q0(in_data_q0), + .indices_01_dout(indices_01_c_dout), + .indices_01_empty_n(indices_01_c_empty_n), + .indices_01_read(tdf10_readInputs69_U0_indices_01_read), + .indices_12_dout(indices_12_c_dout), + .indices_12_empty_n(indices_12_c_empty_n), + .indices_12_read(tdf10_readInputs69_U0_indices_12_read), + .ifmap_vec_address0(tdf10_readInputs69_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf10_readInputs69_U0_ifmap_vec_ce0), + .ifmap_vec_we0(tdf10_readInputs69_U0_ifmap_vec_we0), + .ifmap_vec_d0(tdf10_readInputs69_U0_ifmap_vec_d0), + .ifmap_vec_address1(tdf10_readInputs69_U0_ifmap_vec_address1), + .ifmap_vec_ce1(tdf10_readInputs69_U0_ifmap_vec_ce1), + .ifmap_vec_we1(tdf10_readInputs69_U0_ifmap_vec_we1), + .ifmap_vec_d1(tdf10_readInputs69_U0_ifmap_vec_d1), + .indices_01_out_din(tdf10_readInputs69_U0_indices_01_out_din), + .indices_01_out_full_n(indices_01_c2_full_n), + .indices_01_out_write(tdf10_readInputs69_U0_indices_01_out_write), + .indices_12_out_din(tdf10_readInputs69_U0_indices_12_out_din), + .indices_12_out_full_n(indices_12_c3_full_n), + .indices_12_out_write(tdf10_readInputs69_U0_indices_12_out_write) +); + +td_fused_top_tdf10_readFilters68 tdf10_readFilters68_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf10_readFilters68_U0_ap_start), + .ap_done(tdf10_readFilters68_U0_ap_done), + .ap_continue(tdf10_readFilters68_U0_ap_continue), + .ap_idle(tdf10_readFilters68_U0_ap_idle), + .ap_ready(tdf10_readFilters68_U0_ap_ready), + .filter_data_address0(tdf10_readFilters68_U0_filter_data_address0), + .filter_data_ce0(tdf10_readFilters68_U0_filter_data_ce0), + .filter_data_q0(l1_filter_data_q0), + .indices_23_dout(indices_23_c_dout), + .indices_23_empty_n(indices_23_c_empty_n), + .indices_23_read(tdf10_readFilters68_U0_indices_23_read), + .weight_vecs_0_address0(tdf10_readFilters68_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf10_readFilters68_U0_weight_vecs_0_ce0), + .weight_vecs_0_we0(tdf10_readFilters68_U0_weight_vecs_0_we0), + .weight_vecs_0_d0(tdf10_readFilters68_U0_weight_vecs_0_d0), + .weight_vecs_0_address1(tdf10_readFilters68_U0_weight_vecs_0_address1), + .weight_vecs_0_ce1(tdf10_readFilters68_U0_weight_vecs_0_ce1), + .weight_vecs_0_we1(tdf10_readFilters68_U0_weight_vecs_0_we1), + .weight_vecs_0_d1(tdf10_readFilters68_U0_weight_vecs_0_d1) +); + +td_fused_top_tdf10_dot_product tdf10_dot_product_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf10_dot_product_U0_ap_start), + .ap_done(tdf10_dot_product_U0_ap_done), + .ap_continue(tdf10_dot_product_U0_ap_continue), + .ap_idle(tdf10_dot_product_U0_ap_idle), + .ap_ready(tdf10_dot_product_U0_ap_ready), + .ifmap_vec_address0(tdf10_dot_product_U0_ifmap_vec_address0), + .ifmap_vec_ce0(tdf10_dot_product_U0_ifmap_vec_ce0), + .ifmap_vec_q0(ifmap_vec_t_q0), + .weight_vecs_0_address0(tdf10_dot_product_U0_weight_vecs_0_address0), + .weight_vecs_0_ce0(tdf10_dot_product_U0_weight_vecs_0_ce0), + .weight_vecs_0_q0(weight_vecs_0_t_q0), + .products_0_address0(tdf10_dot_product_U0_products_0_address0), + .products_0_ce0(tdf10_dot_product_U0_products_0_ce0), + .products_0_we0(tdf10_dot_product_U0_products_0_we0), + .products_0_d0(tdf10_dot_product_U0_products_0_d0) +); + +td_fused_top_tdf10_accum_1 tdf10_accum_1_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf10_accum_1_U0_ap_start), + .ap_done(tdf10_accum_1_U0_ap_done), + .ap_continue(tdf10_accum_1_U0_ap_continue), + .ap_idle(tdf10_accum_1_U0_ap_idle), + .ap_ready(tdf10_accum_1_U0_ap_ready), + .accum_in_0_address0(tdf10_accum_1_U0_accum_in_0_address0), + .accum_in_0_ce0(tdf10_accum_1_U0_accum_in_0_ce0), + .accum_in_0_q0(products_0_t_q0), + .accum_in_0_address1(tdf10_accum_1_U0_accum_in_0_address1), + .accum_in_0_ce1(tdf10_accum_1_U0_accum_in_0_ce1), + .accum_in_0_q1(products_0_t_q1), + .accum_out_address0(tdf10_accum_1_U0_accum_out_address0), + .accum_out_ce0(tdf10_accum_1_U0_accum_out_ce0), + .accum_out_we0(tdf10_accum_1_U0_accum_out_we0), + .accum_out_d0(tdf10_accum_1_U0_accum_out_d0), + .accum_out_address1(tdf10_accum_1_U0_accum_out_address1), + .accum_out_ce1(tdf10_accum_1_U0_accum_out_ce1), + .accum_out_we1(tdf10_accum_1_U0_accum_out_we1), + .accum_out_d1(tdf10_accum_1_U0_accum_out_d1) +); + +td_fused_top_tdf10_accum_2 tdf10_accum_2_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf10_accum_2_U0_ap_start), + .ap_done(tdf10_accum_2_U0_ap_done), + .ap_continue(tdf10_accum_2_U0_ap_continue), + .ap_idle(tdf10_accum_2_U0_ap_idle), + .ap_ready(tdf10_accum_2_U0_ap_ready), + .accum_in_24(tdf10_accum_2_U0_accum_in_24), + .accum_in_24_ap_vld(tdf10_accum_2_U0_accum_in_24_ap_vld), + .accum_in_address0(tdf10_accum_2_U0_accum_in_address0), + .accum_in_ce0(tdf10_accum_2_U0_accum_in_ce0), + .accum_in_q0(accum1_out_0_t_q0) +); + +td_fused_top_Block_entry_proc_proc435 Block_entry_proc_proc435_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(Block_entry_proc_proc435_U0_ap_start), + .ap_done(Block_entry_proc_proc435_U0_ap_done), + .ap_continue(Block_entry_proc_proc435_U0_ap_continue), + .ap_idle(Block_entry_proc_proc435_U0_ap_idle), + .ap_ready(Block_entry_proc_proc435_U0_ap_ready), + .tmp(tmp_channel_dout), + .ap_return(Block_entry_proc_proc435_U0_ap_return) +); + +td_fused_top_tdf10_adjust tdf10_adjust_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf10_adjust_U0_ap_start), + .ap_done(tdf10_adjust_U0_ap_done), + .ap_continue(tdf10_adjust_U0_ap_continue), + .ap_idle(tdf10_adjust_U0_ap_idle), + .ap_ready(tdf10_adjust_U0_ap_ready), + .sums_read(sums_0_dout), + .adjustments_address0(tdf10_adjust_U0_adjustments_address0), + .adjustments_ce0(tdf10_adjust_U0_adjustments_ce0), + .adjustments_q0(l1_adjustments_q0), + .indices_23_dout(indices_23_c1_dout), + .indices_23_empty_n(indices_23_c1_empty_n), + .indices_23_read(tdf10_adjust_U0_indices_23_read), + .indices_23_out_din(tdf10_adjust_U0_indices_23_out_din), + .indices_23_out_full_n(indices_23_c4_full_n), + .indices_23_out_write(tdf10_adjust_U0_indices_23_out_write), + .ap_return(tdf10_adjust_U0_ap_return) +); + +td_fused_top_tdf10_l2_multiply66 tdf10_l2_multiply66_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf10_l2_multiply66_U0_ap_start), + .ap_done(tdf10_l2_multiply66_U0_ap_done), + .ap_continue(tdf10_l2_multiply66_U0_ap_continue), + .ap_idle(tdf10_l2_multiply66_U0_ap_idle), + .ap_ready(tdf10_l2_multiply66_U0_ap_ready), + .intermediate_fmaps_read(intermediate_fmaps_0_dout), + .l2_filter_data_address0(tdf10_l2_multiply66_U0_l2_filter_data_address0), + .l2_filter_data_ce0(tdf10_l2_multiply66_U0_l2_filter_data_ce0), + .l2_filter_data_q0(l2_filter_data_q0), + .l2_products_address0(tdf10_l2_multiply66_U0_l2_products_address0), + .l2_products_ce0(tdf10_l2_multiply66_U0_l2_products_ce0), + .l2_products_we0(tdf10_l2_multiply66_U0_l2_products_we0), + .l2_products_d0(tdf10_l2_multiply66_U0_l2_products_d0), + .indices_23_dout(indices_23_c4_dout), + .indices_23_empty_n(indices_23_c4_empty_n), + .indices_23_read(tdf10_l2_multiply66_U0_indices_23_read) +); + +td_fused_top_tdf10_l2_writeOutputs_165 tdf10_l2_writeOutputs_165_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf10_l2_writeOutputs_165_U0_ap_start), + .ap_done(tdf10_l2_writeOutputs_165_U0_ap_done), + .ap_continue(tdf10_l2_writeOutputs_165_U0_ap_continue), + .ap_idle(tdf10_l2_writeOutputs_165_U0_ap_idle), + .ap_ready(tdf10_l2_writeOutputs_165_U0_ap_ready), + .indices_01_dout(indices_01_c2_dout), + .indices_01_empty_n(indices_01_c2_empty_n), + .indices_01_read(tdf10_l2_writeOutputs_165_U0_indices_01_read), + .indices_12_dout(indices_12_c3_dout), + .indices_12_empty_n(indices_12_c3_empty_n), + .indices_12_read(tdf10_l2_writeOutputs_165_U0_indices_12_read), + .write4_dout(write4_c_dout), + .write4_empty_n(write4_c_empty_n), + .write4_read(tdf10_l2_writeOutputs_165_U0_write4_read), + .l2_partial_sums_address0(tdf10_l2_writeOutputs_165_U0_l2_partial_sums_address0), + .l2_partial_sums_ce0(tdf10_l2_writeOutputs_165_U0_l2_partial_sums_ce0), + .l2_partial_sums_q0(l2_products_t_q0), + .out_data_address1(tdf10_l2_writeOutputs_165_U0_out_data_address1), + .out_data_ce1(tdf10_l2_writeOutputs_165_U0_out_data_ce1), + .out_data_we1(tdf10_l2_writeOutputs_165_U0_out_data_we1), + .out_data_d1(tdf10_l2_writeOutputs_165_U0_out_data_d1), + .l2_adjustments_address0(tdf10_l2_writeOutputs_165_U0_l2_adjustments_address0), + .l2_adjustments_ce0(tdf10_l2_writeOutputs_165_U0_l2_adjustments_ce0), + .l2_adjustments_q0(l2_adjustments_q0) +); + +td_fused_top_fifo_w16_d2_S_x7 indices_01_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf10_readInputs69_U0_indices_01_read), + .if_dout(indices_01_c_dout), + .if_full_n(indices_01_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf10_get_next_ijk_U0_indices_0_write), + .if_din(tdf10_get_next_ijk_U0_indices_0_din) +); + +td_fused_top_fifo_w16_d2_S_x7 indices_12_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf10_readInputs69_U0_indices_12_read), + .if_dout(indices_12_c_dout), + .if_full_n(indices_12_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf10_get_next_ijk_U0_indices_1_write), + .if_din(tdf10_get_next_ijk_U0_indices_1_din) +); + +td_fused_top_fifo_w9_d2_S indices_23_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf10_readFilters68_U0_indices_23_read), + .if_dout(indices_23_c_dout), + .if_full_n(indices_23_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf10_get_next_ijk_U0_indices_2_out_write), + .if_din(tdf10_get_next_ijk_U0_indices_2_out_din) +); + +td_fused_top_fifo_w15_d7_S indices_23_c1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf10_adjust_U0_indices_23_read), + .if_dout(indices_23_c1_dout), + .if_full_n(indices_23_c1_full_n), + .if_write_ce(1'b1), + .if_write(tdf10_get_next_ijk_U0_indices_2_out1_write), + .if_din(tdf10_get_next_ijk_U0_indices_2_out1_din) +); + +td_fused_top_fifo_w1_d9_S_x1 write4_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(write4_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf10_l2_writeOutputs_165_U0_write4_read), + .if_dout(write4_c_dout), + .if_full_n(write4_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf10_get_next_ijk_U0_write_r_write), + .if_din(write4_c_din) +); + +td_fused_top_fifo_w4_d8_S_x0 indices_01_c2_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c2_empty_n), + .if_read_ce(1'b1), + .if_read(tdf10_l2_writeOutputs_165_U0_indices_01_read), + .if_dout(indices_01_c2_dout), + .if_full_n(indices_01_c2_full_n), + .if_write_ce(1'b1), + .if_write(tdf10_readInputs69_U0_indices_01_out_write), + .if_din(tdf10_readInputs69_U0_indices_01_out_din) +); + +td_fused_top_fifo_w8_d8_S_x indices_12_c3_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c3_empty_n), + .if_read_ce(1'b1), + .if_read(tdf10_l2_writeOutputs_165_U0_indices_12_read), + .if_dout(indices_12_c3_dout), + .if_full_n(indices_12_c3_full_n), + .if_write_ce(1'b1), + .if_write(tdf10_readInputs69_U0_indices_12_out_write), + .if_din(tdf10_readInputs69_U0_indices_12_out_din) +); + +td_fused_top_fifo_w16_d2_S_x7 tmp_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(tmp_channel_empty_n), + .if_read_ce(1'b1), + .if_read(Block_entry_proc_proc435_U0_ap_ready), + .if_dout(tmp_channel_dout), + .if_full_n(tmp_channel_full_n), + .if_write_ce(1'b1), + .if_write(tdf10_accum_2_U0_ap_done), + .if_din(tdf10_accum_2_U0_accum_in_24) +); + +td_fused_top_fifo_w16_d2_S_x7 sums_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(sums_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf10_adjust_U0_ap_ready), + .if_dout(sums_0_dout), + .if_full_n(sums_0_full_n), + .if_write_ce(1'b1), + .if_write(Block_entry_proc_proc435_U0_ap_done), + .if_din(Block_entry_proc_proc435_U0_ap_return) +); + +td_fused_top_fifo_w15_d2_S indices_23_c4_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c4_empty_n), + .if_read_ce(1'b1), + .if_read(tdf10_l2_multiply66_U0_indices_23_read), + .if_dout(indices_23_c4_dout), + .if_full_n(indices_23_c4_full_n), + .if_write_ce(1'b1), + .if_write(tdf10_adjust_U0_indices_23_out_write), + .if_din(tdf10_adjust_U0_indices_23_out_din) +); + +td_fused_top_fifo_w16_d2_S_x7 intermediate_fmaps_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(intermediate_fmaps_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf10_l2_multiply66_U0_ap_ready), + .if_dout(intermediate_fmaps_0_dout), + .if_full_n(intermediate_fmaps_0_full_n), + .if_write_ce(1'b1), + .if_write(tdf10_adjust_U0_ap_done), + .if_din(tdf10_adjust_U0_ap_return) +); + +td_fused_top_start_for_tdf10_readFilters68_U0 start_for_tdf10_readFilters68_U0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(start_for_tdf10_readFilters68_U0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf10_readFilters68_U0_ap_ready), + .if_dout(start_for_tdf10_readFilters68_U0_dout), + .if_full_n(start_for_tdf10_readFilters68_U0_full_n), + .if_write_ce(1'b1), + .if_write(tdf10_get_next_ijk_U0_start_write), + .if_din(start_for_tdf10_readFilters68_U0_din) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf10_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf10_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf10_get_next_ijk_U0_ap_ready <= ap_sync_tdf10_get_next_ijk_U0_ap_ready; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf10_readInputs69_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf10_readInputs69_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf10_readInputs69_U0_ap_ready <= ap_sync_tdf10_readInputs69_U0_ap_ready; + end + end +end + +assign Block_entry_proc_proc435_U0_ap_continue = sums_0_full_n; + +assign Block_entry_proc_proc435_U0_ap_start = tmp_channel_empty_n; + +assign Block_entry_proc_proc435_U0_start_full_n = 1'b1; + +assign Block_entry_proc_proc435_U0_start_write = 1'b0; + +assign ap_channel_done_accum1_out_0 = tdf10_accum_1_U0_ap_done; + +assign ap_channel_done_ifmap_vec = tdf10_readInputs69_U0_ap_done; + +assign ap_channel_done_intermediate_fmaps_0 = tdf10_adjust_U0_ap_done; + +assign ap_channel_done_l2_products = tdf10_l2_multiply66_U0_ap_done; + +assign ap_channel_done_products_0 = tdf10_dot_product_U0_ap_done; + +assign ap_channel_done_sums_0 = Block_entry_proc_proc435_U0_ap_done; + +assign ap_channel_done_tmp_channel = tdf10_accum_2_U0_ap_done; + +assign ap_channel_done_weight_vecs_0 = tdf10_readFilters68_U0_ap_done; + +assign ap_done = tdf10_l2_writeOutputs_165_U0_ap_done; + +assign ap_idle = (tdf10_readInputs69_U0_ap_idle & tdf10_readFilters68_U0_ap_idle & tdf10_l2_writeOutputs_165_U0_ap_idle & tdf10_l2_multiply66_U0_ap_idle & tdf10_get_next_ijk_U0_ap_idle & tdf10_dot_product_U0_ap_idle & tdf10_adjust_U0_ap_idle & tdf10_accum_2_U0_ap_idle & tdf10_accum_1_U0_ap_idle & (intermediate_fmaps_0_empty_n ^ 1'b1) & (sums_0_empty_n ^ 1'b1) & (tmp_channel_empty_n ^ 1'b1) & (l2_products_t_empty_n ^ 1'b1) & (products_0_t_empty_n ^ 1'b1) & (weight_vecs_0_t_empty_n ^ 1'b1) & (ifmap_vec_t_empty_n ^ 1'b1) & (1'b1 ^ accum1_out_0_t_empty_n) & Block_entry_proc_proc435_U0_ap_idle); + +assign ap_ready = ap_sync_ready; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = tdf10_l2_writeOutputs_165_U0_ap_done; + +assign ap_sync_ready = (ap_sync_tdf10_readInputs69_U0_ap_ready & ap_sync_tdf10_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf10_get_next_ijk_U0_ap_ready = (tdf10_get_next_ijk_U0_ap_ready | ap_sync_reg_tdf10_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf10_readInputs69_U0_ap_ready = (tdf10_readInputs69_U0_ap_ready | ap_sync_reg_tdf10_readInputs69_U0_ap_ready); + +assign in_data_address0 = tdf10_readInputs69_U0_in_data_address0; + +assign in_data_address1 = 12'd0; + +assign in_data_ce0 = tdf10_readInputs69_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = tdf10_readInputs69_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign l1_adjustments_address0 = tdf10_adjust_U0_adjustments_address0; + +assign l1_adjustments_address1 = 9'd0; + +assign l1_adjustments_ce0 = tdf10_adjust_U0_adjustments_ce0; + +assign l1_adjustments_ce1 = 1'b0; + +assign l1_adjustments_d0 = 48'd0; + +assign l1_adjustments_d1 = 48'd0; + +assign l1_adjustments_we0 = 1'b0; + +assign l1_adjustments_we1 = 1'b0; + +assign l1_filter_data_address0 = tdf10_readFilters68_U0_filter_data_address0; + +assign l1_filter_data_address1 = 17'd0; + +assign l1_filter_data_ce0 = tdf10_readFilters68_U0_filter_data_ce0; + +assign l1_filter_data_ce1 = 1'b0; + +assign l1_filter_data_d0 = 64'd0; + +assign l1_filter_data_d1 = 64'd0; + +assign l1_filter_data_we0 = 1'b0; + +assign l1_filter_data_we1 = 1'b0; + +assign l2_adjustments_address0 = tdf10_l2_writeOutputs_165_U0_l2_adjustments_address0; + +assign l2_adjustments_address1 = 6'd0; + +assign l2_adjustments_ce0 = tdf10_l2_writeOutputs_165_U0_l2_adjustments_ce0; + +assign l2_adjustments_ce1 = 1'b0; + +assign l2_adjustments_d0 = 48'd0; + +assign l2_adjustments_d1 = 48'd0; + +assign l2_adjustments_we0 = 1'b0; + +assign l2_adjustments_we1 = 1'b0; + +assign l2_filter_data_address0 = tdf10_l2_multiply66_U0_l2_filter_data_address0; + +assign l2_filter_data_address1 = 15'd0; + +assign l2_filter_data_ce0 = tdf10_l2_multiply66_U0_l2_filter_data_ce0; + +assign l2_filter_data_ce1 = 1'b0; + +assign l2_filter_data_d0 = 16'd0; + +assign l2_filter_data_d1 = 16'd0; + +assign l2_filter_data_we0 = 1'b0; + +assign l2_filter_data_we1 = 1'b0; + +assign out_data_address0 = 12'd0; + +assign out_data_address1 = tdf10_l2_writeOutputs_165_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = tdf10_l2_writeOutputs_165_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = tdf10_l2_writeOutputs_165_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = tdf10_l2_writeOutputs_165_U0_out_data_we1; + +assign out_data_write = tdf10_l2_writeOutputs_165_U0_out_data_write; + +assign products_0_t_d1 = 16'd0; + +assign products_0_t_we1 = 1'b0; + +assign start_for_tdf10_readFilters68_U0_din = 1'b1; + +assign tdf10_accum_1_U0_accum_out_full_n = accum1_out_0_i_full_n; + +assign tdf10_accum_1_U0_ap_continue = accum1_out_0_i_full_n; + +assign tdf10_accum_1_U0_ap_start = products_0_t_empty_n; + +assign tdf10_accum_1_U0_start_full_n = 1'b1; + +assign tdf10_accum_1_U0_start_write = 1'b0; + +assign tdf10_accum_2_U0_ap_continue = tmp_channel_full_n; + +assign tdf10_accum_2_U0_ap_start = accum1_out_0_t_empty_n; + +assign tdf10_accum_2_U0_start_full_n = 1'b1; + +assign tdf10_accum_2_U0_start_write = 1'b0; + +assign tdf10_adjust_U0_ap_continue = intermediate_fmaps_0_full_n; + +assign tdf10_adjust_U0_ap_start = sums_0_empty_n; + +assign tdf10_adjust_U0_start_full_n = 1'b1; + +assign tdf10_adjust_U0_start_write = 1'b0; + +assign tdf10_dot_product_U0_ap_continue = products_0_i_full_n; + +assign tdf10_dot_product_U0_ap_start = (weight_vecs_0_t_empty_n & ifmap_vec_t_empty_n); + +assign tdf10_dot_product_U0_products_0_full_n = products_0_i_full_n; + +assign tdf10_dot_product_U0_start_full_n = 1'b1; + +assign tdf10_dot_product_U0_start_write = 1'b0; + +assign tdf10_get_next_ijk_U0_ap_continue = 1'b1; + +assign tdf10_get_next_ijk_U0_ap_start = ((ap_sync_reg_tdf10_get_next_ijk_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf10_l2_multiply66_U0_ap_continue = l2_products_i_full_n; + +assign tdf10_l2_multiply66_U0_ap_start = intermediate_fmaps_0_empty_n; + +assign tdf10_l2_multiply66_U0_l2_products_full_n = l2_products_i_full_n; + +assign tdf10_l2_multiply66_U0_start_full_n = 1'b1; + +assign tdf10_l2_multiply66_U0_start_write = 1'b0; + +assign tdf10_l2_writeOutputs_165_U0_ap_continue = ap_continue; + +assign tdf10_l2_writeOutputs_165_U0_ap_start = l2_products_t_empty_n; + +assign tdf10_l2_writeOutputs_165_U0_out_data_full_n = out_data_full_n; + +assign tdf10_l2_writeOutputs_165_U0_out_data_write = 1'b0; + +assign tdf10_l2_writeOutputs_165_U0_start_full_n = 1'b1; + +assign tdf10_l2_writeOutputs_165_U0_start_write = 1'b0; + +assign tdf10_readFilters68_U0_ap_continue = weight_vecs_0_i_full_n; + +assign tdf10_readFilters68_U0_ap_start = start_for_tdf10_readFilters68_U0_empty_n; + +assign tdf10_readFilters68_U0_start_full_n = 1'b1; + +assign tdf10_readFilters68_U0_start_write = 1'b0; + +assign tdf10_readFilters68_U0_weight_vecs_0_full_n = weight_vecs_0_i_full_n; + +assign tdf10_readInputs69_U0_ap_continue = ifmap_vec_i_full_n; + +assign tdf10_readInputs69_U0_ap_start = ((ap_sync_reg_tdf10_readInputs69_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf10_readInputs69_U0_ifmap_vec_full_n = ifmap_vec_i_full_n; + +assign tdf10_readInputs69_U0_in_data_full_n = in_data_empty_n; + +assign tdf10_readInputs69_U0_in_data_write = 1'b0; + +assign tdf10_readInputs69_U0_start_full_n = 1'b1; + +assign tdf10_readInputs69_U0_start_write = 1'b0; + +assign write4_c_din = tdf10_get_next_ijk_U0_write_r_din; + +endmodule //td_fused_top_dataflow_in_loop_TOP_LOOP38364 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP76_accum1_out_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 3; +parameter MEM_SIZE = 8; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP76_accum1_out_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd8; +parameter AddressWidth = 32'd3; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP76_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP76_accum1_out_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP76_accum1_out_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 3, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP76_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP76_accum1_out_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP76_accum1_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP76_accum1_out_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP76_ifmap_vec_0_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 7; +parameter MEM_SIZE = 128; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP76_ifmap_vec_0_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd128; +parameter AddressWidth = 32'd7; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP76_ifmap_vec_0_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP76_ifmap_vec_0_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP76_ifmap_vec_0_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 7, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP76_ifmap_vec_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP76_ifmap_vec_0_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP76_ifmap_vec_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP76_ifmap_vec_0_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP76_products_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 7; +parameter MEM_SIZE = 128; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP76_products_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd128; +parameter AddressWidth = 32'd7; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP76_products_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP76_products_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP76_products_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 7, + BufferCount = 2, + MemLatency = 1, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire [AddressWidth-1:0] i_address1, + output wire [DataWidth-1:0] i_q1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire [AddressWidth-1:0] t_address1, + output wire [DataWidth-1:0] t_q1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [BufferCount-1:0] buf_we0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_d0_0, buf_d0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_q1_0, buf_q1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_dataflow_in_loop_TOP_LOOP76_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP76_products_0_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .we0 ( buf_we0[ 0 ] ), + .d0 ( buf_d0_0 ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .q1 ( buf_q1_0 ) + ); + td_fused_top_dataflow_in_loop_TOP_LOOP76_products_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP76_products_0_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .we0 ( buf_we0[ 1 ] ), + .d0 ( buf_d0_1 ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .q1 ( buf_q1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0 + : (iptr == 0 ) ? i_we0 : 1'b0; + assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0 + : (iptr == 1 ) ? i_we0 : 1'b0; + assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign i_q1 = (prev_iptr == 1'b1 ? buf_q1_1 : buf_q1_0); +assign t_q1 = reg_valid1 ? reg_q1 : (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// reg_q1 and reg_valid1 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q1 <= 1'b0; + reg_valid1 <= 1'b0; + end else if (!t_ce1 && !reg_valid1) begin + reg_q1 <= (prev_tptr == 1'b1 ? buf_q1_1 : buf_q1_0); + reg_valid1 <= 1'b1; + end else if (t_ce1) begin + reg_valid1 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP76 ( + ap_clk, + ap_rst, + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + ap_start, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +input ap_clk; +input ap_rst; +output [12:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [12:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [16:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [16:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [9:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [9:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +output [15:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [15:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +input ap_start; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +wire [15:0] ifmap_vec_0_0_i_q0; +wire [15:0] ifmap_vec_0_0_t_q0; +wire [15:0] weight_vecs_0_0_0_i_q0; +wire [15:0] weight_vecs_0_0_0_t_q0; +wire [15:0] products_0_i_q0; +wire [15:0] products_0_i_q1; +wire [15:0] products_0_t_q0; +wire [15:0] products_0_t_q1; +wire [15:0] accum1_out_0_i_q0; +wire [15:0] accum1_out_0_t_q0; +wire tdf12_get_next_ijk_U0_ap_start; +wire tdf12_get_next_ijk_U0_ap_done; +wire tdf12_get_next_ijk_U0_ap_continue; +wire tdf12_get_next_ijk_U0_ap_idle; +wire tdf12_get_next_ijk_U0_ap_ready; +wire tdf12_get_next_ijk_U0_start_out; +wire tdf12_get_next_ijk_U0_start_write; +wire [15:0] tdf12_get_next_ijk_U0_indices_0_din; +wire tdf12_get_next_ijk_U0_indices_0_write; +wire [15:0] tdf12_get_next_ijk_U0_indices_1_din; +wire tdf12_get_next_ijk_U0_indices_1_write; +wire [9:0] tdf12_get_next_ijk_U0_indices_2_out_din; +wire tdf12_get_next_ijk_U0_indices_2_out_write; +wire [9:0] tdf12_get_next_ijk_U0_indices_2_out1_din; +wire tdf12_get_next_ijk_U0_indices_2_out1_write; +wire tdf12_readInputs_U0_ap_start; +wire tdf12_readInputs_U0_ap_done; +wire tdf12_readInputs_U0_ap_continue; +wire tdf12_readInputs_U0_ap_idle; +wire tdf12_readInputs_U0_ap_ready; +wire [12:0] tdf12_readInputs_U0_in_data_address0; +wire tdf12_readInputs_U0_in_data_ce0; +wire tdf12_readInputs_U0_indices_01_read; +wire tdf12_readInputs_U0_indices_12_read; +wire [6:0] tdf12_readInputs_U0_ifmap_vec_0_0_address0; +wire tdf12_readInputs_U0_ifmap_vec_0_0_ce0; +wire tdf12_readInputs_U0_ifmap_vec_0_0_we0; +wire [15:0] tdf12_readInputs_U0_ifmap_vec_0_0_d0; +wire [6:0] tdf12_readInputs_U0_ifmap_vec_0_0_address1; +wire tdf12_readInputs_U0_ifmap_vec_0_0_ce1; +wire tdf12_readInputs_U0_ifmap_vec_0_0_we1; +wire [15:0] tdf12_readInputs_U0_ifmap_vec_0_0_d1; +wire [3:0] tdf12_readInputs_U0_indices_01_out_din; +wire tdf12_readInputs_U0_indices_01_out_write; +wire [7:0] tdf12_readInputs_U0_indices_12_out_din; +wire tdf12_readInputs_U0_indices_12_out_write; +wire tdf12_readInputs_U0_in_data_full_n; +wire tdf12_readInputs_U0_in_data_write; +wire ap_channel_done_ifmap_vec_0_0; +wire tdf12_readInputs_U0_ifmap_vec_0_0_full_n; +wire tdf12_readFilters78_U0_ap_start; +wire tdf12_readFilters78_U0_ap_done; +wire tdf12_readFilters78_U0_ap_continue; +wire tdf12_readFilters78_U0_ap_idle; +wire tdf12_readFilters78_U0_ap_ready; +wire [16:0] tdf12_readFilters78_U0_filter_data_address0; +wire tdf12_readFilters78_U0_filter_data_ce0; +wire tdf12_readFilters78_U0_indices_23_read; +wire [6:0] tdf12_readFilters78_U0_weight_vecs_0_0_0_address0; +wire tdf12_readFilters78_U0_weight_vecs_0_0_0_ce0; +wire tdf12_readFilters78_U0_weight_vecs_0_0_0_we0; +wire [15:0] tdf12_readFilters78_U0_weight_vecs_0_0_0_d0; +wire ap_channel_done_weight_vecs_0_0_0; +wire tdf12_readFilters78_U0_weight_vecs_0_0_0_full_n; +wire tdf12_dot_product_U0_ap_start; +wire tdf12_dot_product_U0_ap_done; +wire tdf12_dot_product_U0_ap_continue; +wire tdf12_dot_product_U0_ap_idle; +wire tdf12_dot_product_U0_ap_ready; +wire [6:0] tdf12_dot_product_U0_ifmap_vec_0_0_address0; +wire tdf12_dot_product_U0_ifmap_vec_0_0_ce0; +wire [6:0] tdf12_dot_product_U0_weight_vecs_0_0_0_address0; +wire tdf12_dot_product_U0_weight_vecs_0_0_0_ce0; +wire [6:0] tdf12_dot_product_U0_products_0_address0; +wire tdf12_dot_product_U0_products_0_ce0; +wire tdf12_dot_product_U0_products_0_we0; +wire [15:0] tdf12_dot_product_U0_products_0_d0; +wire ap_channel_done_products_0; +wire tdf12_dot_product_U0_products_0_full_n; +wire tdf12_accum_1_U0_ap_start; +wire tdf12_accum_1_U0_ap_done; +wire tdf12_accum_1_U0_ap_continue; +wire tdf12_accum_1_U0_ap_idle; +wire tdf12_accum_1_U0_ap_ready; +wire [6:0] tdf12_accum_1_U0_accum_in_0_address0; +wire tdf12_accum_1_U0_accum_in_0_ce0; +wire [6:0] tdf12_accum_1_U0_accum_in_0_address1; +wire tdf12_accum_1_U0_accum_in_0_ce1; +wire [2:0] tdf12_accum_1_U0_accum_out_address0; +wire tdf12_accum_1_U0_accum_out_ce0; +wire tdf12_accum_1_U0_accum_out_we0; +wire [15:0] tdf12_accum_1_U0_accum_out_d0; +wire [2:0] tdf12_accum_1_U0_accum_out_address1; +wire tdf12_accum_1_U0_accum_out_ce1; +wire tdf12_accum_1_U0_accum_out_we1; +wire [15:0] tdf12_accum_1_U0_accum_out_d1; +wire ap_channel_done_accum1_out_0; +wire tdf12_accum_1_U0_accum_out_full_n; +wire tdf12_accum_2_U0_ap_start; +wire tdf12_accum_2_U0_ap_done; +wire tdf12_accum_2_U0_ap_continue; +wire tdf12_accum_2_U0_ap_idle; +wire tdf12_accum_2_U0_ap_ready; +wire [15:0] tdf12_accum_2_U0_accum_in_20; +wire tdf12_accum_2_U0_accum_in_20_ap_vld; +wire [2:0] tdf12_accum_2_U0_accum_in_address0; +wire tdf12_accum_2_U0_accum_in_ce0; +wire ap_channel_done_tmp_channel; +wire tmp_channel_full_n; +wire Block_entry_proc_proc446_U0_ap_start; +wire Block_entry_proc_proc446_U0_ap_done; +wire Block_entry_proc_proc446_U0_ap_continue; +wire Block_entry_proc_proc446_U0_ap_idle; +wire Block_entry_proc_proc446_U0_ap_ready; +wire [15:0] Block_entry_proc_proc446_U0_ap_return; +wire ap_channel_done_sums_0; +wire sums_0_full_n; +wire tdf12_adjust_U0_ap_start; +wire tdf12_adjust_U0_ap_done; +wire tdf12_adjust_U0_ap_continue; +wire tdf12_adjust_U0_ap_idle; +wire tdf12_adjust_U0_ap_ready; +wire [9:0] tdf12_adjust_U0_adjustments_address0; +wire tdf12_adjust_U0_adjustments_ce0; +wire tdf12_adjust_U0_indices_23_read; +wire [15:0] tdf12_adjust_U0_ap_return; +wire ap_channel_done_outputs_0; +wire outputs_0_full_n; +wire tdf12_writeOutputs_unaligned_U0_ap_start; +wire tdf12_writeOutputs_unaligned_U0_ap_done; +wire tdf12_writeOutputs_unaligned_U0_ap_continue; +wire tdf12_writeOutputs_unaligned_U0_ap_idle; +wire tdf12_writeOutputs_unaligned_U0_ap_ready; +wire tdf12_writeOutputs_unaligned_U0_indices_01_read; +wire tdf12_writeOutputs_unaligned_U0_indices_12_read; +wire [15:0] tdf12_writeOutputs_unaligned_U0_out_data_address1; +wire tdf12_writeOutputs_unaligned_U0_out_data_ce1; +wire tdf12_writeOutputs_unaligned_U0_out_data_we1; +wire [63:0] tdf12_writeOutputs_unaligned_U0_out_data_d1; +wire tdf12_writeOutputs_unaligned_U0_out_data_full_n; +wire tdf12_writeOutputs_unaligned_U0_out_data_write; +wire ap_sync_continue; +wire ifmap_vec_0_0_i_full_n; +wire ifmap_vec_0_0_t_empty_n; +wire weight_vecs_0_0_0_i_full_n; +wire weight_vecs_0_0_0_t_empty_n; +wire products_0_i_full_n; +wire products_0_t_empty_n; +wire [15:0] products_0_t_d1; +wire products_0_t_we1; +wire accum1_out_0_i_full_n; +wire accum1_out_0_t_empty_n; +wire indices_01_c_full_n; +wire [15:0] indices_01_c_dout; +wire indices_01_c_empty_n; +wire indices_12_c_full_n; +wire [15:0] indices_12_c_dout; +wire indices_12_c_empty_n; +wire indices_23_c_full_n; +wire [9:0] indices_23_c_dout; +wire indices_23_c_empty_n; +wire indices_23_c1_full_n; +wire [9:0] indices_23_c1_dout; +wire indices_23_c1_empty_n; +wire indices_01_c2_full_n; +wire [3:0] indices_01_c2_dout; +wire indices_01_c2_empty_n; +wire indices_12_c3_full_n; +wire [7:0] indices_12_c3_dout; +wire indices_12_c3_empty_n; +wire [15:0] tmp_channel_dout; +wire tmp_channel_empty_n; +wire [15:0] sums_0_dout; +wire sums_0_empty_n; +wire [15:0] outputs_0_dout; +wire outputs_0_empty_n; +wire ap_sync_done; +wire ap_sync_ready; +reg ap_sync_reg_tdf12_get_next_ijk_U0_ap_ready; +wire ap_sync_tdf12_get_next_ijk_U0_ap_ready; +reg ap_sync_reg_tdf12_readInputs_U0_ap_ready; +wire ap_sync_tdf12_readInputs_U0_ap_ready; +wire [0:0] start_for_tdf12_readFilters78_U0_din; +wire start_for_tdf12_readFilters78_U0_full_n; +wire [0:0] start_for_tdf12_readFilters78_U0_dout; +wire start_for_tdf12_readFilters78_U0_empty_n; +wire tdf12_readInputs_U0_start_full_n; +wire tdf12_readInputs_U0_start_write; +wire tdf12_readFilters78_U0_start_full_n; +wire tdf12_readFilters78_U0_start_write; +wire tdf12_dot_product_U0_start_full_n; +wire tdf12_dot_product_U0_start_write; +wire tdf12_accum_1_U0_start_full_n; +wire tdf12_accum_1_U0_start_write; +wire tdf12_accum_2_U0_start_full_n; +wire tdf12_accum_2_U0_start_write; +wire Block_entry_proc_proc446_U0_start_full_n; +wire Block_entry_proc_proc446_U0_start_write; +wire tdf12_adjust_U0_start_full_n; +wire tdf12_adjust_U0_start_write; +wire tdf12_writeOutputs_unaligned_U0_start_full_n; +wire tdf12_writeOutputs_unaligned_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_sync_reg_tdf12_get_next_ijk_U0_ap_ready = 1'b0; +#0 ap_sync_reg_tdf12_readInputs_U0_ap_ready = 1'b0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP76_ifmap_vec_0_0 #( + .DataWidth( 16 ), + .AddressRange( 128 ), + .AddressWidth( 7 )) +ifmap_vec_0_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf12_readInputs_U0_ap_done), + .i_full_n(ifmap_vec_0_0_i_full_n), + .i_ce0(tdf12_readInputs_U0_ifmap_vec_0_0_ce0), + .i_we0(tdf12_readInputs_U0_ifmap_vec_0_0_we0), + .i_address0(tdf12_readInputs_U0_ifmap_vec_0_0_address0), + .i_d0(tdf12_readInputs_U0_ifmap_vec_0_0_d0), + .i_q0(ifmap_vec_0_0_i_q0), + .i_ce1(tdf12_readInputs_U0_ifmap_vec_0_0_ce1), + .i_we1(tdf12_readInputs_U0_ifmap_vec_0_0_we1), + .i_address1(tdf12_readInputs_U0_ifmap_vec_0_0_address1), + .i_d1(tdf12_readInputs_U0_ifmap_vec_0_0_d1), + .t_ce(1'b1), + .t_read(tdf12_dot_product_U0_ap_ready), + .t_empty_n(ifmap_vec_0_0_t_empty_n), + .t_ce0(tdf12_dot_product_U0_ifmap_vec_0_0_ce0), + .t_we0(1'b0), + .t_address0(tdf12_dot_product_U0_ifmap_vec_0_0_address0), + .t_d0(16'd0), + .t_q0(ifmap_vec_0_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(7'd0), + .t_d1(16'd0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP76_weight_vecs_0_0_0 #( + .DataWidth( 16 ), + .AddressRange( 128 ), + .AddressWidth( 7 )) +weight_vecs_0_0_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf12_readFilters78_U0_ap_done), + .i_full_n(weight_vecs_0_0_0_i_full_n), + .i_ce0(tdf12_readFilters78_U0_weight_vecs_0_0_0_ce0), + .i_we0(tdf12_readFilters78_U0_weight_vecs_0_0_0_we0), + .i_address0(tdf12_readFilters78_U0_weight_vecs_0_0_0_address0), + .i_d0(tdf12_readFilters78_U0_weight_vecs_0_0_0_d0), + .i_q0(weight_vecs_0_0_0_i_q0), + .t_ce(1'b1), + .t_read(tdf12_dot_product_U0_ap_ready), + .t_empty_n(weight_vecs_0_0_0_t_empty_n), + .t_ce0(tdf12_dot_product_U0_weight_vecs_0_0_0_ce0), + .t_we0(1'b0), + .t_address0(tdf12_dot_product_U0_weight_vecs_0_0_0_address0), + .t_d0(16'd0), + .t_q0(weight_vecs_0_0_0_t_q0) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP76_products_0 #( + .DataWidth( 16 ), + .AddressRange( 128 ), + .AddressWidth( 7 )) +products_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf12_dot_product_U0_ap_done), + .i_full_n(products_0_i_full_n), + .i_ce0(tdf12_dot_product_U0_products_0_ce0), + .i_we0(tdf12_dot_product_U0_products_0_we0), + .i_address0(tdf12_dot_product_U0_products_0_address0), + .i_d0(tdf12_dot_product_U0_products_0_d0), + .i_q0(products_0_i_q0), + .i_ce1(1'b0), + .i_address1(7'd0), + .i_q1(products_0_i_q1), + .t_ce(1'b1), + .t_read(tdf12_accum_1_U0_ap_ready), + .t_empty_n(products_0_t_empty_n), + .t_ce0(tdf12_accum_1_U0_accum_in_0_ce0), + .t_we0(1'b0), + .t_address0(tdf12_accum_1_U0_accum_in_0_address0), + .t_d0(16'd0), + .t_q0(products_0_t_q0), + .t_ce1(tdf12_accum_1_U0_accum_in_0_ce1), + .t_address1(tdf12_accum_1_U0_accum_in_0_address1), + .t_q1(products_0_t_q1) +); + +td_fused_top_dataflow_in_loop_TOP_LOOP76_accum1_out_0 #( + .DataWidth( 16 ), + .AddressRange( 8 ), + .AddressWidth( 3 )) +accum1_out_0_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf12_accum_1_U0_ap_done), + .i_full_n(accum1_out_0_i_full_n), + .i_ce0(tdf12_accum_1_U0_accum_out_ce0), + .i_we0(tdf12_accum_1_U0_accum_out_we0), + .i_address0(tdf12_accum_1_U0_accum_out_address0), + .i_d0(tdf12_accum_1_U0_accum_out_d0), + .i_q0(accum1_out_0_i_q0), + .i_ce1(tdf12_accum_1_U0_accum_out_ce1), + .i_we1(tdf12_accum_1_U0_accum_out_we1), + .i_address1(tdf12_accum_1_U0_accum_out_address1), + .i_d1(tdf12_accum_1_U0_accum_out_d1), + .t_ce(1'b1), + .t_read(tdf12_accum_2_U0_ap_ready), + .t_empty_n(accum1_out_0_t_empty_n), + .t_ce0(tdf12_accum_2_U0_accum_in_ce0), + .t_we0(1'b0), + .t_address0(tdf12_accum_2_U0_accum_in_address0), + .t_d0(16'd0), + .t_q0(accum1_out_0_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(3'd0), + .t_d1(16'd0) +); + +td_fused_top_tdf12_get_next_ijk tdf12_get_next_ijk_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf12_get_next_ijk_U0_ap_start), + .start_full_n(start_for_tdf12_readFilters78_U0_full_n), + .ap_done(tdf12_get_next_ijk_U0_ap_done), + .ap_continue(tdf12_get_next_ijk_U0_ap_continue), + .ap_idle(tdf12_get_next_ijk_U0_ap_idle), + .ap_ready(tdf12_get_next_ijk_U0_ap_ready), + .start_out(tdf12_get_next_ijk_U0_start_out), + .start_write(tdf12_get_next_ijk_U0_start_write), + .indices_0_din(tdf12_get_next_ijk_U0_indices_0_din), + .indices_0_full_n(indices_01_c_full_n), + .indices_0_write(tdf12_get_next_ijk_U0_indices_0_write), + .indices_1_din(tdf12_get_next_ijk_U0_indices_1_din), + .indices_1_full_n(indices_12_c_full_n), + .indices_1_write(tdf12_get_next_ijk_U0_indices_1_write), + .indices_2_out_din(tdf12_get_next_ijk_U0_indices_2_out_din), + .indices_2_out_full_n(indices_23_c_full_n), + .indices_2_out_write(tdf12_get_next_ijk_U0_indices_2_out_write), + .indices_2_out1_din(tdf12_get_next_ijk_U0_indices_2_out1_din), + .indices_2_out1_full_n(indices_23_c1_full_n), + .indices_2_out1_write(tdf12_get_next_ijk_U0_indices_2_out1_write) +); + +td_fused_top_tdf12_readInputs tdf12_readInputs_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf12_readInputs_U0_ap_start), + .ap_done(tdf12_readInputs_U0_ap_done), + .ap_continue(tdf12_readInputs_U0_ap_continue), + .ap_idle(tdf12_readInputs_U0_ap_idle), + .ap_ready(tdf12_readInputs_U0_ap_ready), + .in_data_address0(tdf12_readInputs_U0_in_data_address0), + .in_data_ce0(tdf12_readInputs_U0_in_data_ce0), + .in_data_q0(in_data_q0), + .indices_01_dout(indices_01_c_dout), + .indices_01_empty_n(indices_01_c_empty_n), + .indices_01_read(tdf12_readInputs_U0_indices_01_read), + .indices_12_dout(indices_12_c_dout), + .indices_12_empty_n(indices_12_c_empty_n), + .indices_12_read(tdf12_readInputs_U0_indices_12_read), + .ifmap_vec_0_0_address0(tdf12_readInputs_U0_ifmap_vec_0_0_address0), + .ifmap_vec_0_0_ce0(tdf12_readInputs_U0_ifmap_vec_0_0_ce0), + .ifmap_vec_0_0_we0(tdf12_readInputs_U0_ifmap_vec_0_0_we0), + .ifmap_vec_0_0_d0(tdf12_readInputs_U0_ifmap_vec_0_0_d0), + .ifmap_vec_0_0_address1(tdf12_readInputs_U0_ifmap_vec_0_0_address1), + .ifmap_vec_0_0_ce1(tdf12_readInputs_U0_ifmap_vec_0_0_ce1), + .ifmap_vec_0_0_we1(tdf12_readInputs_U0_ifmap_vec_0_0_we1), + .ifmap_vec_0_0_d1(tdf12_readInputs_U0_ifmap_vec_0_0_d1), + .indices_01_out_din(tdf12_readInputs_U0_indices_01_out_din), + .indices_01_out_full_n(indices_01_c2_full_n), + .indices_01_out_write(tdf12_readInputs_U0_indices_01_out_write), + .indices_12_out_din(tdf12_readInputs_U0_indices_12_out_din), + .indices_12_out_full_n(indices_12_c3_full_n), + .indices_12_out_write(tdf12_readInputs_U0_indices_12_out_write) +); + +td_fused_top_tdf12_readFilters78 tdf12_readFilters78_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf12_readFilters78_U0_ap_start), + .ap_done(tdf12_readFilters78_U0_ap_done), + .ap_continue(tdf12_readFilters78_U0_ap_continue), + .ap_idle(tdf12_readFilters78_U0_ap_idle), + .ap_ready(tdf12_readFilters78_U0_ap_ready), + .filter_data_address0(tdf12_readFilters78_U0_filter_data_address0), + .filter_data_ce0(tdf12_readFilters78_U0_filter_data_ce0), + .filter_data_q0(filter_data_q0), + .indices_23_dout(indices_23_c_dout), + .indices_23_empty_n(indices_23_c_empty_n), + .indices_23_read(tdf12_readFilters78_U0_indices_23_read), + .weight_vecs_0_0_0_address0(tdf12_readFilters78_U0_weight_vecs_0_0_0_address0), + .weight_vecs_0_0_0_ce0(tdf12_readFilters78_U0_weight_vecs_0_0_0_ce0), + .weight_vecs_0_0_0_we0(tdf12_readFilters78_U0_weight_vecs_0_0_0_we0), + .weight_vecs_0_0_0_d0(tdf12_readFilters78_U0_weight_vecs_0_0_0_d0) +); + +td_fused_top_tdf12_dot_product tdf12_dot_product_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf12_dot_product_U0_ap_start), + .ap_done(tdf12_dot_product_U0_ap_done), + .ap_continue(tdf12_dot_product_U0_ap_continue), + .ap_idle(tdf12_dot_product_U0_ap_idle), + .ap_ready(tdf12_dot_product_U0_ap_ready), + .ifmap_vec_0_0_address0(tdf12_dot_product_U0_ifmap_vec_0_0_address0), + .ifmap_vec_0_0_ce0(tdf12_dot_product_U0_ifmap_vec_0_0_ce0), + .ifmap_vec_0_0_q0(ifmap_vec_0_0_t_q0), + .weight_vecs_0_0_0_address0(tdf12_dot_product_U0_weight_vecs_0_0_0_address0), + .weight_vecs_0_0_0_ce0(tdf12_dot_product_U0_weight_vecs_0_0_0_ce0), + .weight_vecs_0_0_0_q0(weight_vecs_0_0_0_t_q0), + .products_0_address0(tdf12_dot_product_U0_products_0_address0), + .products_0_ce0(tdf12_dot_product_U0_products_0_ce0), + .products_0_we0(tdf12_dot_product_U0_products_0_we0), + .products_0_d0(tdf12_dot_product_U0_products_0_d0) +); + +td_fused_top_tdf12_accum_1 tdf12_accum_1_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf12_accum_1_U0_ap_start), + .ap_done(tdf12_accum_1_U0_ap_done), + .ap_continue(tdf12_accum_1_U0_ap_continue), + .ap_idle(tdf12_accum_1_U0_ap_idle), + .ap_ready(tdf12_accum_1_U0_ap_ready), + .accum_in_0_address0(tdf12_accum_1_U0_accum_in_0_address0), + .accum_in_0_ce0(tdf12_accum_1_U0_accum_in_0_ce0), + .accum_in_0_q0(products_0_t_q0), + .accum_in_0_address1(tdf12_accum_1_U0_accum_in_0_address1), + .accum_in_0_ce1(tdf12_accum_1_U0_accum_in_0_ce1), + .accum_in_0_q1(products_0_t_q1), + .accum_out_address0(tdf12_accum_1_U0_accum_out_address0), + .accum_out_ce0(tdf12_accum_1_U0_accum_out_ce0), + .accum_out_we0(tdf12_accum_1_U0_accum_out_we0), + .accum_out_d0(tdf12_accum_1_U0_accum_out_d0), + .accum_out_address1(tdf12_accum_1_U0_accum_out_address1), + .accum_out_ce1(tdf12_accum_1_U0_accum_out_ce1), + .accum_out_we1(tdf12_accum_1_U0_accum_out_we1), + .accum_out_d1(tdf12_accum_1_U0_accum_out_d1) +); + +td_fused_top_tdf12_accum_2 tdf12_accum_2_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf12_accum_2_U0_ap_start), + .ap_done(tdf12_accum_2_U0_ap_done), + .ap_continue(tdf12_accum_2_U0_ap_continue), + .ap_idle(tdf12_accum_2_U0_ap_idle), + .ap_ready(tdf12_accum_2_U0_ap_ready), + .accum_in_20(tdf12_accum_2_U0_accum_in_20), + .accum_in_20_ap_vld(tdf12_accum_2_U0_accum_in_20_ap_vld), + .accum_in_address0(tdf12_accum_2_U0_accum_in_address0), + .accum_in_ce0(tdf12_accum_2_U0_accum_in_ce0), + .accum_in_q0(accum1_out_0_t_q0) +); + +td_fused_top_Block_entry_proc_proc446 Block_entry_proc_proc446_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(Block_entry_proc_proc446_U0_ap_start), + .ap_done(Block_entry_proc_proc446_U0_ap_done), + .ap_continue(Block_entry_proc_proc446_U0_ap_continue), + .ap_idle(Block_entry_proc_proc446_U0_ap_idle), + .ap_ready(Block_entry_proc_proc446_U0_ap_ready), + .tmp(tmp_channel_dout), + .ap_return(Block_entry_proc_proc446_U0_ap_return) +); + +td_fused_top_tdf12_adjust tdf12_adjust_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf12_adjust_U0_ap_start), + .ap_done(tdf12_adjust_U0_ap_done), + .ap_continue(tdf12_adjust_U0_ap_continue), + .ap_idle(tdf12_adjust_U0_ap_idle), + .ap_ready(tdf12_adjust_U0_ap_ready), + .sums_read(sums_0_dout), + .adjustments_address0(tdf12_adjust_U0_adjustments_address0), + .adjustments_ce0(tdf12_adjust_U0_adjustments_ce0), + .adjustments_q0(adjustments_q0), + .indices_23_dout(indices_23_c1_dout), + .indices_23_empty_n(indices_23_c1_empty_n), + .indices_23_read(tdf12_adjust_U0_indices_23_read), + .ap_return(tdf12_adjust_U0_ap_return) +); + +td_fused_top_tdf12_writeOutputs_unaligned tdf12_writeOutputs_unaligned_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(tdf12_writeOutputs_unaligned_U0_ap_start), + .ap_done(tdf12_writeOutputs_unaligned_U0_ap_done), + .ap_continue(tdf12_writeOutputs_unaligned_U0_ap_continue), + .ap_idle(tdf12_writeOutputs_unaligned_U0_ap_idle), + .ap_ready(tdf12_writeOutputs_unaligned_U0_ap_ready), + .indices_01_dout(indices_01_c2_dout), + .indices_01_empty_n(indices_01_c2_empty_n), + .indices_01_read(tdf12_writeOutputs_unaligned_U0_indices_01_read), + .indices_12_dout(indices_12_c3_dout), + .indices_12_empty_n(indices_12_c3_empty_n), + .indices_12_read(tdf12_writeOutputs_unaligned_U0_indices_12_read), + .p_read(outputs_0_dout), + .out_data_address1(tdf12_writeOutputs_unaligned_U0_out_data_address1), + .out_data_ce1(tdf12_writeOutputs_unaligned_U0_out_data_ce1), + .out_data_we1(tdf12_writeOutputs_unaligned_U0_out_data_we1), + .out_data_d1(tdf12_writeOutputs_unaligned_U0_out_data_d1) +); + +td_fused_top_fifo_w16_d2_S_x9 indices_01_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf12_readInputs_U0_indices_01_read), + .if_dout(indices_01_c_dout), + .if_full_n(indices_01_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf12_get_next_ijk_U0_indices_0_write), + .if_din(tdf12_get_next_ijk_U0_indices_0_din) +); + +td_fused_top_fifo_w16_d2_S_x9 indices_12_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf12_readInputs_U0_indices_12_read), + .if_dout(indices_12_c_dout), + .if_full_n(indices_12_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf12_get_next_ijk_U0_indices_1_write), + .if_din(tdf12_get_next_ijk_U0_indices_1_din) +); + +td_fused_top_fifo_w10_d2_S indices_23_c_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c_empty_n), + .if_read_ce(1'b1), + .if_read(tdf12_readFilters78_U0_indices_23_read), + .if_dout(indices_23_c_dout), + .if_full_n(indices_23_c_full_n), + .if_write_ce(1'b1), + .if_write(tdf12_get_next_ijk_U0_indices_2_out_write), + .if_din(tdf12_get_next_ijk_U0_indices_2_out_din) +); + +td_fused_top_fifo_w10_d7_S_x indices_23_c1_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_23_c1_empty_n), + .if_read_ce(1'b1), + .if_read(tdf12_adjust_U0_indices_23_read), + .if_dout(indices_23_c1_dout), + .if_full_n(indices_23_c1_full_n), + .if_write_ce(1'b1), + .if_write(tdf12_get_next_ijk_U0_indices_2_out1_write), + .if_din(tdf12_get_next_ijk_U0_indices_2_out1_din) +); + +td_fused_top_fifo_w4_d7_S_x0 indices_01_c2_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_01_c2_empty_n), + .if_read_ce(1'b1), + .if_read(tdf12_writeOutputs_unaligned_U0_indices_01_read), + .if_dout(indices_01_c2_dout), + .if_full_n(indices_01_c2_full_n), + .if_write_ce(1'b1), + .if_write(tdf12_readInputs_U0_indices_01_out_write), + .if_din(tdf12_readInputs_U0_indices_01_out_din) +); + +td_fused_top_fifo_w8_d7_S_x0 indices_12_c3_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(indices_12_c3_empty_n), + .if_read_ce(1'b1), + .if_read(tdf12_writeOutputs_unaligned_U0_indices_12_read), + .if_dout(indices_12_c3_dout), + .if_full_n(indices_12_c3_full_n), + .if_write_ce(1'b1), + .if_write(tdf12_readInputs_U0_indices_12_out_write), + .if_din(tdf12_readInputs_U0_indices_12_out_din) +); + +td_fused_top_fifo_w16_d2_S_x9 tmp_channel_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(tmp_channel_empty_n), + .if_read_ce(1'b1), + .if_read(Block_entry_proc_proc446_U0_ap_ready), + .if_dout(tmp_channel_dout), + .if_full_n(tmp_channel_full_n), + .if_write_ce(1'b1), + .if_write(tdf12_accum_2_U0_ap_done), + .if_din(tdf12_accum_2_U0_accum_in_20) +); + +td_fused_top_fifo_w16_d2_S_x9 sums_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(sums_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf12_adjust_U0_ap_ready), + .if_dout(sums_0_dout), + .if_full_n(sums_0_full_n), + .if_write_ce(1'b1), + .if_write(Block_entry_proc_proc446_U0_ap_done), + .if_din(Block_entry_proc_proc446_U0_ap_return) +); + +td_fused_top_fifo_w16_d2_S_x9 outputs_0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(outputs_0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf12_writeOutputs_unaligned_U0_ap_ready), + .if_dout(outputs_0_dout), + .if_full_n(outputs_0_full_n), + .if_write_ce(1'b1), + .if_write(tdf12_adjust_U0_ap_done), + .if_din(tdf12_adjust_U0_ap_return) +); + +td_fused_top_start_for_tdf12_readFilters78_U0 start_for_tdf12_readFilters78_U0_U( + .clk(ap_clk), + .reset(ap_rst), + .if_empty_n(start_for_tdf12_readFilters78_U0_empty_n), + .if_read_ce(1'b1), + .if_read(tdf12_readFilters78_U0_ap_ready), + .if_dout(start_for_tdf12_readFilters78_U0_dout), + .if_full_n(start_for_tdf12_readFilters78_U0_full_n), + .if_write_ce(1'b1), + .if_write(tdf12_get_next_ijk_U0_start_write), + .if_din(start_for_tdf12_readFilters78_U0_din) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf12_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf12_get_next_ijk_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf12_get_next_ijk_U0_ap_ready <= ap_sync_tdf12_get_next_ijk_U0_ap_ready; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_sync_reg_tdf12_readInputs_U0_ap_ready <= 1'b0; + end else begin + if (((ap_sync_ready & ap_start) == 1'b1)) begin + ap_sync_reg_tdf12_readInputs_U0_ap_ready <= 1'b0; + end else begin + ap_sync_reg_tdf12_readInputs_U0_ap_ready <= ap_sync_tdf12_readInputs_U0_ap_ready; + end + end +end + +assign Block_entry_proc_proc446_U0_ap_continue = sums_0_full_n; + +assign Block_entry_proc_proc446_U0_ap_start = tmp_channel_empty_n; + +assign Block_entry_proc_proc446_U0_start_full_n = 1'b1; + +assign Block_entry_proc_proc446_U0_start_write = 1'b0; + +assign adjustments_address0 = tdf12_adjust_U0_adjustments_address0; + +assign adjustments_address1 = 10'd0; + +assign adjustments_ce0 = tdf12_adjust_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_channel_done_accum1_out_0 = tdf12_accum_1_U0_ap_done; + +assign ap_channel_done_ifmap_vec_0_0 = tdf12_readInputs_U0_ap_done; + +assign ap_channel_done_outputs_0 = tdf12_adjust_U0_ap_done; + +assign ap_channel_done_products_0 = tdf12_dot_product_U0_ap_done; + +assign ap_channel_done_sums_0 = Block_entry_proc_proc446_U0_ap_done; + +assign ap_channel_done_tmp_channel = tdf12_accum_2_U0_ap_done; + +assign ap_channel_done_weight_vecs_0_0_0 = tdf12_readFilters78_U0_ap_done; + +assign ap_done = tdf12_writeOutputs_unaligned_U0_ap_done; + +assign ap_idle = (tdf12_writeOutputs_unaligned_U0_ap_idle & tdf12_readInputs_U0_ap_idle & tdf12_readFilters78_U0_ap_idle & tdf12_get_next_ijk_U0_ap_idle & tdf12_dot_product_U0_ap_idle & tdf12_adjust_U0_ap_idle & tdf12_accum_2_U0_ap_idle & tdf12_accum_1_U0_ap_idle & (outputs_0_empty_n ^ 1'b1) & (sums_0_empty_n ^ 1'b1) & (tmp_channel_empty_n ^ 1'b1) & (products_0_t_empty_n ^ 1'b1) & (weight_vecs_0_0_0_t_empty_n ^ 1'b1) & (ifmap_vec_0_0_t_empty_n ^ 1'b1) & (1'b1 ^ accum1_out_0_t_empty_n) & Block_entry_proc_proc446_U0_ap_idle); + +assign ap_ready = ap_sync_ready; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = tdf12_writeOutputs_unaligned_U0_ap_done; + +assign ap_sync_ready = (ap_sync_tdf12_readInputs_U0_ap_ready & ap_sync_tdf12_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf12_get_next_ijk_U0_ap_ready = (tdf12_get_next_ijk_U0_ap_ready | ap_sync_reg_tdf12_get_next_ijk_U0_ap_ready); + +assign ap_sync_tdf12_readInputs_U0_ap_ready = (tdf12_readInputs_U0_ap_ready | ap_sync_reg_tdf12_readInputs_U0_ap_ready); + +assign filter_data_address0 = tdf12_readFilters78_U0_filter_data_address0; + +assign filter_data_address1 = 17'd0; + +assign filter_data_ce0 = tdf12_readFilters78_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = tdf12_readInputs_U0_in_data_address0; + +assign in_data_address1 = 13'd0; + +assign in_data_ce0 = tdf12_readInputs_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = tdf12_readInputs_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 16'd0; + +assign out_data_address1 = tdf12_writeOutputs_unaligned_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = tdf12_writeOutputs_unaligned_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = tdf12_writeOutputs_unaligned_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = tdf12_writeOutputs_unaligned_U0_out_data_we1; + +assign out_data_write = tdf12_writeOutputs_unaligned_U0_out_data_write; + +assign products_0_t_d1 = 16'd0; + +assign products_0_t_we1 = 1'b0; + +assign start_for_tdf12_readFilters78_U0_din = 1'b1; + +assign tdf12_accum_1_U0_accum_out_full_n = accum1_out_0_i_full_n; + +assign tdf12_accum_1_U0_ap_continue = accum1_out_0_i_full_n; + +assign tdf12_accum_1_U0_ap_start = products_0_t_empty_n; + +assign tdf12_accum_1_U0_start_full_n = 1'b1; + +assign tdf12_accum_1_U0_start_write = 1'b0; + +assign tdf12_accum_2_U0_ap_continue = tmp_channel_full_n; + +assign tdf12_accum_2_U0_ap_start = accum1_out_0_t_empty_n; + +assign tdf12_accum_2_U0_start_full_n = 1'b1; + +assign tdf12_accum_2_U0_start_write = 1'b0; + +assign tdf12_adjust_U0_ap_continue = outputs_0_full_n; + +assign tdf12_adjust_U0_ap_start = sums_0_empty_n; + +assign tdf12_adjust_U0_start_full_n = 1'b1; + +assign tdf12_adjust_U0_start_write = 1'b0; + +assign tdf12_dot_product_U0_ap_continue = products_0_i_full_n; + +assign tdf12_dot_product_U0_ap_start = (weight_vecs_0_0_0_t_empty_n & ifmap_vec_0_0_t_empty_n); + +assign tdf12_dot_product_U0_products_0_full_n = products_0_i_full_n; + +assign tdf12_dot_product_U0_start_full_n = 1'b1; + +assign tdf12_dot_product_U0_start_write = 1'b0; + +assign tdf12_get_next_ijk_U0_ap_continue = 1'b1; + +assign tdf12_get_next_ijk_U0_ap_start = ((ap_sync_reg_tdf12_get_next_ijk_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf12_readFilters78_U0_ap_continue = weight_vecs_0_0_0_i_full_n; + +assign tdf12_readFilters78_U0_ap_start = start_for_tdf12_readFilters78_U0_empty_n; + +assign tdf12_readFilters78_U0_start_full_n = 1'b1; + +assign tdf12_readFilters78_U0_start_write = 1'b0; + +assign tdf12_readFilters78_U0_weight_vecs_0_0_0_full_n = weight_vecs_0_0_0_i_full_n; + +assign tdf12_readInputs_U0_ap_continue = ifmap_vec_0_0_i_full_n; + +assign tdf12_readInputs_U0_ap_start = ((ap_sync_reg_tdf12_readInputs_U0_ap_ready ^ 1'b1) & ap_start); + +assign tdf12_readInputs_U0_ifmap_vec_0_0_full_n = ifmap_vec_0_0_i_full_n; + +assign tdf12_readInputs_U0_in_data_full_n = in_data_empty_n; + +assign tdf12_readInputs_U0_in_data_write = 1'b0; + +assign tdf12_readInputs_U0_start_full_n = 1'b1; + +assign tdf12_readInputs_U0_start_write = 1'b0; + +assign tdf12_writeOutputs_unaligned_U0_ap_continue = ap_continue; + +assign tdf12_writeOutputs_unaligned_U0_ap_start = outputs_0_empty_n; + +assign tdf12_writeOutputs_unaligned_U0_out_data_full_n = out_data_full_n; + +assign tdf12_writeOutputs_unaligned_U0_out_data_write = 1'b0; + +assign tdf12_writeOutputs_unaligned_U0_start_full_n = 1'b1; + +assign tdf12_writeOutputs_unaligned_U0_start_write = 1'b0; + +endmodule //td_fused_top_dataflow_in_loop_TOP_LOOP76 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP76_weight_vecs_0_0_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 8; +parameter MEM_SIZE = 256; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +output reg[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +output reg[DWIDTH-1:0] q1; +input clk; + +reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + q0 <= ram[addr0]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1) + ram[addr1] <= d1; + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_dataflow_in_loop_TOP_LOOP76_weight_vecs_0_0_0_memcore( + reset, + clk, + address0, + ce0, + we0, + d0, + q0, + address1, + ce1, + we1, + d1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd256; +parameter AddressWidth = 32'd8; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_dataflow_in_loop_TOP_LOOP76_weight_vecs_0_0_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP76_weight_vecs_0_0_0_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_dataflow_in_loop_TOP_LOOP76_weight_vecs_0_0_0 +#(parameter + DataWidth = 16, + AddressRange = 32, + AddressWidth = 7, + BufferCount = 2, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire i_we0, + input wire [AddressWidth-1:0] i_address0, + input wire [DataWidth-1:0] i_d0, + output wire [DataWidth-1:0] i_q0, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire t_we0, + input wire [AddressWidth-1:0] t_address0, + input wire [DataWidth-1:0] t_d0, + output wire [DataWidth-1:0] t_q0 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +wire [AddressWidth+IndexWidth-1:0] memcore_iaddr; +wire [AddressWidth+IndexWidth-1:0] memcore_taddr; + +//------------------------Instantiation------------------ +assign memcore_iaddr = {i_address0, iptr}; +assign memcore_taddr = {t_address0, tptr}; +td_fused_top_dataflow_in_loop_TOP_LOOP76_weight_vecs_0_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP76_weight_vecs_0_0_0_memcore_U ( + .reset ( reset ), + .clk ( clk ), + .address0 ( memcore_iaddr ), + .ce0 ( i_ce0 ), + .we0 ( i_we0), + .d0 ( i_d0 ), + .q0 ( i_q0 ), + .address1 ( memcore_taddr ), + .ce1 ( t_ce0 ), + .we1 ( t_we0), + .d1 ( t_d0 ), + .q1 ( t_q0 ) + +); + +//------------------------Body--------------------------- + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w10_d2_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd10; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w10_d2_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd10; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w10_d2_S_shiftReg +U_td_fused_top_fifo_w10_d2_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w10_d7_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd10; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w10_d7_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd10; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w10_d7_S_shiftReg +U_td_fused_top_fifo_w10_d7_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w10_d7_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd10; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w10_d7_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd10; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w10_d7_S_x_shiftReg +U_td_fused_top_fifo_w10_d7_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w10_d8_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd10; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w10_d8_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd10; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w10_d8_S_shiftReg +U_td_fused_top_fifo_w10_d8_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w10_d8_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd10; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w10_d8_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd10; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w10_d8_S_x_shiftReg +U_td_fused_top_fifo_w10_d8_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w11_d2_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd11; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w11_d2_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd11; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w11_d2_S_shiftReg +U_td_fused_top_fifo_w11_d2_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w11_d7_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd11; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w11_d7_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd11; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w11_d7_S_shiftReg +U_td_fused_top_fifo_w11_d7_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w12_d7_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd12; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w12_d7_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd12; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w12_d7_S_shiftReg +U_td_fused_top_fifo_w12_d7_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w12_d8_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd12; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w12_d8_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd12; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w12_d8_S_shiftReg +U_td_fused_top_fifo_w12_d8_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w12_d8_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd12; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w12_d8_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd12; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w12_d8_S_x_shiftReg +U_td_fused_top_fifo_w12_d8_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w13_d2_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd13; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w13_d2_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd13; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w13_d2_S_shiftReg +U_td_fused_top_fifo_w13_d2_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w13_d7_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd13; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w13_d7_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd13; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w13_d7_S_shiftReg +U_td_fused_top_fifo_w13_d7_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w14_d9_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd14; +parameter ADDR_WIDTH = 32'd4; +parameter DEPTH = 5'd9; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + sr_8 <= sr_7; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, a) begin + case (a) + 4'd0: q = sr_0; + 4'd1: q = sr_1; + 4'd2: q = sr_2; + 4'd3: q = sr_3; + 4'd4: q = sr_4; + 4'd5: q = sr_5; + 4'd6: q = sr_6; + 4'd7: q = sr_7; + 4'd8: q = sr_8; + default: q = sr_8; + endcase +end + +endmodule + +module td_fused_top_fifo_w14_d9_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd14; +parameter ADDR_WIDTH = 32'd4; +parameter DEPTH = 5'd9; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 5'd1; + if (mOutPtr == 5'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 5'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 5'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w14_d9_S_shiftReg +U_td_fused_top_fifo_w14_d9_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w15_d2_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd15; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w15_d2_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd15; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w15_d2_S_shiftReg +U_td_fused_top_fifo_w15_d2_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w15_d7_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd15; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w15_d7_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd15; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w15_d7_S_shiftReg +U_td_fused_top_fifo_w15_d7_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w16_d2_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w16_d2_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w16_d2_S_shiftReg +U_td_fused_top_fifo_w16_d2_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w16_d2_S_x0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w16_d2_S_x0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w16_d2_S_x0_shiftReg +U_td_fused_top_fifo_w16_d2_S_x0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w16_d2_S_x1_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w16_d2_S_x1 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w16_d2_S_x1_shiftReg +U_td_fused_top_fifo_w16_d2_S_x1_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w16_d2_S_x2_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w16_d2_S_x2 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w16_d2_S_x2_shiftReg +U_td_fused_top_fifo_w16_d2_S_x2_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w16_d2_S_x3_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w16_d2_S_x3 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w16_d2_S_x3_shiftReg +U_td_fused_top_fifo_w16_d2_S_x3_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w16_d2_S_x4_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w16_d2_S_x4 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w16_d2_S_x4_shiftReg +U_td_fused_top_fifo_w16_d2_S_x4_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w16_d2_S_x5_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w16_d2_S_x5 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w16_d2_S_x5_shiftReg +U_td_fused_top_fifo_w16_d2_S_x5_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w16_d2_S_x6_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w16_d2_S_x6 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w16_d2_S_x6_shiftReg +U_td_fused_top_fifo_w16_d2_S_x6_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w16_d2_S_x7_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w16_d2_S_x7 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w16_d2_S_x7_shiftReg +U_td_fused_top_fifo_w16_d2_S_x7_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w16_d2_S_x8_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w16_d2_S_x8 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w16_d2_S_x8_shiftReg +U_td_fused_top_fifo_w16_d2_S_x8_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w16_d2_S_x9_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w16_d2_S_x9 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w16_d2_S_x9_shiftReg +U_td_fused_top_fifo_w16_d2_S_x9_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w16_d2_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w16_d2_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd16; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w16_d2_S_x_shiftReg +U_td_fused_top_fifo_w16_d2_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w1_d8_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w1_d8_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w1_d8_S_shiftReg +U_td_fused_top_fifo_w1_d8_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w1_d8_S_x0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w1_d8_S_x0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w1_d8_S_x0_shiftReg +U_td_fused_top_fifo_w1_d8_S_x0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w1_d8_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w1_d8_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w1_d8_S_x_shiftReg +U_td_fused_top_fifo_w1_d8_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w1_d9_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd4; +parameter DEPTH = 5'd9; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + sr_8 <= sr_7; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, a) begin + case (a) + 4'd0: q = sr_0; + 4'd1: q = sr_1; + 4'd2: q = sr_2; + 4'd3: q = sr_3; + 4'd4: q = sr_4; + 4'd5: q = sr_5; + 4'd6: q = sr_6; + 4'd7: q = sr_7; + 4'd8: q = sr_8; + default: q = sr_8; + endcase +end + +endmodule + +module td_fused_top_fifo_w1_d9_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd4; +parameter DEPTH = 5'd9; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 5'd1; + if (mOutPtr == 5'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 5'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 5'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w1_d9_S_shiftReg +U_td_fused_top_fifo_w1_d9_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w1_d9_S_x0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd4; +parameter DEPTH = 5'd9; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + sr_8 <= sr_7; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, a) begin + case (a) + 4'd0: q = sr_0; + 4'd1: q = sr_1; + 4'd2: q = sr_2; + 4'd3: q = sr_3; + 4'd4: q = sr_4; + 4'd5: q = sr_5; + 4'd6: q = sr_6; + 4'd7: q = sr_7; + 4'd8: q = sr_8; + default: q = sr_8; + endcase +end + +endmodule + +module td_fused_top_fifo_w1_d9_S_x0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd4; +parameter DEPTH = 5'd9; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 5'd1; + if (mOutPtr == 5'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 5'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 5'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w1_d9_S_x0_shiftReg +U_td_fused_top_fifo_w1_d9_S_x0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w1_d9_S_x1_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd4; +parameter DEPTH = 5'd9; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + sr_8 <= sr_7; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, a) begin + case (a) + 4'd0: q = sr_0; + 4'd1: q = sr_1; + 4'd2: q = sr_2; + 4'd3: q = sr_3; + 4'd4: q = sr_4; + 4'd5: q = sr_5; + 4'd6: q = sr_6; + 4'd7: q = sr_7; + 4'd8: q = sr_8; + default: q = sr_8; + endcase +end + +endmodule + +module td_fused_top_fifo_w1_d9_S_x1 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd4; +parameter DEPTH = 5'd9; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 5'd1; + if (mOutPtr == 5'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 5'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 5'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w1_d9_S_x1_shiftReg +U_td_fused_top_fifo_w1_d9_S_x1_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w1_d9_S_x2_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd4; +parameter DEPTH = 5'd9; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + sr_8 <= sr_7; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, a) begin + case (a) + 4'd0: q = sr_0; + 4'd1: q = sr_1; + 4'd2: q = sr_2; + 4'd3: q = sr_3; + 4'd4: q = sr_4; + 4'd5: q = sr_5; + 4'd6: q = sr_6; + 4'd7: q = sr_7; + 4'd8: q = sr_8; + default: q = sr_8; + endcase +end + +endmodule + +module td_fused_top_fifo_w1_d9_S_x2 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd4; +parameter DEPTH = 5'd9; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 5'd1; + if (mOutPtr == 5'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 5'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 5'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w1_d9_S_x2_shiftReg +U_td_fused_top_fifo_w1_d9_S_x2_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w1_d9_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd4; +parameter DEPTH = 5'd9; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + sr_8 <= sr_7; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, a) begin + case (a) + 4'd0: q = sr_0; + 4'd1: q = sr_1; + 4'd2: q = sr_2; + 4'd3: q = sr_3; + 4'd4: q = sr_4; + 4'd5: q = sr_5; + 4'd6: q = sr_6; + 4'd7: q = sr_7; + 4'd8: q = sr_8; + default: q = sr_8; + endcase +end + +endmodule + +module td_fused_top_fifo_w1_d9_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd4; +parameter DEPTH = 5'd9; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 5'd1; + if (mOutPtr == 5'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 5'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 5'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w1_d9_S_x_shiftReg +U_td_fused_top_fifo_w1_d9_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w4_d2_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w4_d2_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w4_d2_S_shiftReg +U_td_fused_top_fifo_w4_d2_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w4_d2_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w4_d2_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w4_d2_S_x_shiftReg +U_td_fused_top_fifo_w4_d2_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w4_d7_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w4_d7_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w4_d7_S_shiftReg +U_td_fused_top_fifo_w4_d7_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w4_d7_S_x0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w4_d7_S_x0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w4_d7_S_x0_shiftReg +U_td_fused_top_fifo_w4_d7_S_x0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w4_d7_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w4_d7_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w4_d7_S_x_shiftReg +U_td_fused_top_fifo_w4_d7_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w4_d8_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w4_d8_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w4_d8_S_shiftReg +U_td_fused_top_fifo_w4_d8_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w4_d8_S_x0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w4_d8_S_x0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w4_d8_S_x0_shiftReg +U_td_fused_top_fifo_w4_d8_S_x0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w4_d8_S_x1_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w4_d8_S_x1 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w4_d8_S_x1_shiftReg +U_td_fused_top_fifo_w4_d8_S_x1_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w4_d8_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w4_d8_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd4; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w4_d8_S_x_shiftReg +U_td_fused_top_fifo_w4_d8_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w5_d2_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd5; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w5_d2_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd5; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w5_d2_S_shiftReg +U_td_fused_top_fifo_w5_d2_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w5_d2_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd5; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w5_d2_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd5; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w5_d2_S_x_shiftReg +U_td_fused_top_fifo_w5_d2_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w5_d7_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd5; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w5_d7_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd5; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w5_d7_S_shiftReg +U_td_fused_top_fifo_w5_d7_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w5_d7_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd5; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w5_d7_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd5; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w5_d7_S_x_shiftReg +U_td_fused_top_fifo_w5_d7_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w5_d8_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd5; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w5_d8_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd5; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w5_d8_S_shiftReg +U_td_fused_top_fifo_w5_d8_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w5_d8_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd5; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w5_d8_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd5; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w5_d8_S_x_shiftReg +U_td_fused_top_fifo_w5_d8_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w6_d2_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd6; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w6_d2_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd6; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w6_d2_S_shiftReg +U_td_fused_top_fifo_w6_d2_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w6_d7_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd6; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w6_d7_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd6; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w6_d7_S_shiftReg +U_td_fused_top_fifo_w6_d7_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w6_d7_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd6; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w6_d7_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd6; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w6_d7_S_x_shiftReg +U_td_fused_top_fifo_w6_d7_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w6_d8_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd6; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w6_d8_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd6; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w6_d8_S_shiftReg +U_td_fused_top_fifo_w6_d8_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w6_d8_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd6; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w6_d8_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd6; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w6_d8_S_x_shiftReg +U_td_fused_top_fifo_w6_d8_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w7_d2_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd7; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w7_d2_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd7; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w7_d2_S_shiftReg +U_td_fused_top_fifo_w7_d2_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w7_d2_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd7; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w7_d2_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd7; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w7_d2_S_x_shiftReg +U_td_fused_top_fifo_w7_d2_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w7_d7_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd7; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w7_d7_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd7; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w7_d7_S_shiftReg +U_td_fused_top_fifo_w7_d7_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w7_d9_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd7; +parameter ADDR_WIDTH = 32'd4; +parameter DEPTH = 5'd9; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + sr_8 <= sr_7; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, a) begin + case (a) + 4'd0: q = sr_0; + 4'd1: q = sr_1; + 4'd2: q = sr_2; + 4'd3: q = sr_3; + 4'd4: q = sr_4; + 4'd5: q = sr_5; + 4'd6: q = sr_6; + 4'd7: q = sr_7; + 4'd8: q = sr_8; + default: q = sr_8; + endcase +end + +endmodule + +module td_fused_top_fifo_w7_d9_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd7; +parameter ADDR_WIDTH = 32'd4; +parameter DEPTH = 5'd9; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 5'd1; + if (mOutPtr == 5'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 5'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 5'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w7_d9_S_shiftReg +U_td_fused_top_fifo_w7_d9_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w8_d2_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w8_d2_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w8_d2_S_shiftReg +U_td_fused_top_fifo_w8_d2_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w8_d2_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w8_d2_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w8_d2_S_x_shiftReg +U_td_fused_top_fifo_w8_d2_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w8_d7_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w8_d7_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w8_d7_S_shiftReg +U_td_fused_top_fifo_w8_d7_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w8_d7_S_x0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w8_d7_S_x0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w8_d7_S_x0_shiftReg +U_td_fused_top_fifo_w8_d7_S_x0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w8_d7_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w8_d7_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w8_d7_S_x_shiftReg +U_td_fused_top_fifo_w8_d7_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w8_d8_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w8_d8_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w8_d8_S_shiftReg +U_td_fused_top_fifo_w8_d8_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w8_d8_S_x0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w8_d8_S_x0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w8_d8_S_x0_shiftReg +U_td_fused_top_fifo_w8_d8_S_x0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w8_d8_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + sr_7 <= sr_6; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + 3'd7: q = sr_7; + default: q = sr_7; + endcase +end + +endmodule + +module td_fused_top_fifo_w8_d8_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd8; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd8; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w8_d8_S_x_shiftReg +U_td_fused_top_fifo_w8_d8_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w9_d2_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd9; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w9_d2_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd9; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w9_d2_S_shiftReg +U_td_fused_top_fifo_w9_d2_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w9_d2_S_x_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd9; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_fifo_w9_d2_S_x ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd9; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w9_d2_S_x_shiftReg +U_td_fused_top_fifo_w9_d2_S_x_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_fifo_w9_d7_S_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd9; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + sr_2 <= sr_1; + sr_3 <= sr_2; + sr_4 <= sr_3; + sr_5 <= sr_4; + sr_6 <= sr_5; + + + end + end + +always @( sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin + case (a) + 3'd0: q = sr_0; + 3'd1: q = sr_1; + 3'd2: q = sr_2; + 3'd3: q = sr_3; + 3'd4: q = sr_4; + 3'd5: q = sr_5; + 3'd6: q = sr_6; + default: q = sr_6; + endcase +end + +endmodule + +module td_fused_top_fifo_w9_d7_S ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd9; +parameter ADDR_WIDTH = 32'd3; +parameter DEPTH = 4'd7; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 4'd1; + if (mOutPtr == 4'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 4'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 4'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_fifo_w9_d7_S_shiftReg +U_td_fused_top_fifo_w9_d7_S_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_ap_hadd_3_full_dsp_16 ( + input wire aclk, + input wire aclken, + input wire s_axis_a_tvalid, + input wire [15:0] s_axis_a_tdata, + input wire s_axis_b_tvalid, + input wire [15:0] s_axis_b_tdata, + output wire m_axis_result_tvalid, + output wire [15:0] m_axis_result_tdata +); + + reg [15:0] a_reg, b_reg, res_reg; + wire [15:0] res; + + always @(posedge aclk) begin + if (aclken) begin + a_reg <= s_axis_a_tdata; + b_reg <= s_axis_b_tdata; + res_reg <= res; + end + end + + +`ifdef complex_dsp + addition_fp_16 u_add_fp ( + .a(a_reg), + .b(b_reg), + .out(res) + ); +`else +FPAddSub u_FPAddSub (.clk(), .rst(1'b0), .a(a_reg), .b(b_reg), .operation(1'b0), .result(res), .flags()); +`endif + + + assign m_axis_result_tdata = res_reg; + +endmodule + + +module td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 +#(parameter + ID = 25, + NUM_STAGE = 5, + din0_WIDTH = 16, + din1_WIDTH = 16, + dout_WIDTH = 16 +)( + input wire clk, + input wire reset, + input wire ce, + input wire [din0_WIDTH-1:0] din0, + input wire [din1_WIDTH-1:0] din1, + output wire [dout_WIDTH-1:0] dout +); +//------------------------Local signal------------------- +wire aclk; +wire aclken; +wire a_tvalid; +wire [15:0] a_tdata; +wire b_tvalid; +wire [15:0] b_tdata; +wire r_tvalid; +wire [15:0] r_tdata; +reg [din0_WIDTH-1:0] din0_buf1; +reg [din1_WIDTH-1:0] din1_buf1; +reg ce_r; +wire [dout_WIDTH-1:0] dout_i; +reg [dout_WIDTH-1:0] dout_r; +//------------------------Instantiation------------------ +td_fused_top_ap_hadd_3_full_dsp_16 td_fused_top_ap_hadd_3_full_dsp_16_u ( + .aclk ( aclk ), + .aclken ( aclken ), + .s_axis_a_tvalid ( a_tvalid ), + .s_axis_a_tdata ( a_tdata ), + .s_axis_b_tvalid ( b_tvalid ), + .s_axis_b_tdata ( b_tdata ), + .m_axis_result_tvalid ( r_tvalid ), + .m_axis_result_tdata ( r_tdata ) +); +//------------------------Body--------------------------- +assign aclk = clk; +assign aclken = ce_r; +assign a_tvalid = 1'b1; +assign a_tdata = din0_buf1; +assign b_tvalid = 1'b1; +assign b_tdata = din1_buf1; +assign dout_i = r_tdata; + +always @(posedge clk) begin + if (ce) begin + din0_buf1 <= din0; + din1_buf1 <= din1; + end +end + +always @ (posedge clk) begin + ce_r <= ce; +end + +always @ (posedge clk) begin + if (ce_r) begin + dout_r <= dout_i; + end +end + +assign dout = ce_r?dout_i:dout_r; +endmodule +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_ap_hcmp_0_no_dsp_16 ( + input wire s_axis_a_tvalid, + input wire [15:0] s_axis_a_tdata, + input wire s_axis_b_tvalid, + input wire [15:0] s_axis_b_tdata, + input wire s_axis_operation_tvalid, + input wire [7:0] s_axis_operation_tdata, + output wire m_axis_result_tvalid, + output wire [7:0] m_axis_result_tdata +); + // TEMP - compare module not yet ready + // In the meantime, negate operand B, add them + // together, and return the sign bit of the result. + wire [15:0] b_negative; + wire [15:0] result; + assign b_negative = {~s_axis_b_tdata[15], s_axis_b_tdata[14:0]}; + +`ifdef complex_dsp +addition_fp_16 u_add_fp ( + .a(s_axis_a_tdata), + .b(b_negative), + .out(result) + ); +`else +FPAddSub u_FPAddSub_2 (.clk(), .rst(1'b0), .a(s_axis_a_tdata), .b(b_negative), .operation(1'b0), .result(result), .flags()); +`endif + + assign m_axis_result_tdata = {7'b0, result[15]}; +endmodule + +module td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 +#(parameter + ID = 47, + NUM_STAGE = 2, + din0_WIDTH = 16, + din1_WIDTH = 16, + dout_WIDTH = 1 +)( + input wire clk, + input wire reset, + input wire ce, + input wire [din0_WIDTH-1:0] din0, + input wire [din1_WIDTH-1:0] din1, + input wire [4:0] opcode, + output wire [dout_WIDTH-1:0] dout +); +//------------------------Parameter---------------------- +// AutoESL opcode +localparam [4:0] + AP_OEQ = 5'b00001, + AP_OGT = 5'b00010, + AP_OGE = 5'b00011, + AP_OLT = 5'b00100, + AP_OLE = 5'b00101, + AP_ONE = 5'b00110, + AP_UNO = 5'b01000; +// FPV6 opcode +localparam [7:0] + OP_EQ = 8'b00010100, + OP_GT = 8'b00100100, + OP_GE = 8'b00110100, + OP_LT = 8'b00001100, + OP_LE = 8'b00011100, + OP_NE = 8'b00101100, + OP_UO = 8'b00000100; +//------------------------Local signal------------------- +wire a_tvalid; +wire [15:0] a_tdata; +wire b_tvalid; +wire [15:0] b_tdata; +wire op_tvalid; +reg [7:0] op_tdata; +wire r_tvalid; +wire [7:0] r_tdata; +reg [din0_WIDTH-1:0] din0_buf1; +reg [din1_WIDTH-1:0] din1_buf1; +reg [4:0] opcode_buf1; +reg ce_r; +wire [dout_WIDTH-1:0] dout_i; +reg [dout_WIDTH-1:0] dout_r; +//------------------------Instantiation------------------ +td_fused_top_ap_hcmp_0_no_dsp_16 td_fused_top_ap_hcmp_0_no_dsp_16_u ( + .s_axis_a_tvalid ( a_tvalid ), + .s_axis_a_tdata ( a_tdata ), + .s_axis_b_tvalid ( b_tvalid ), + .s_axis_b_tdata ( b_tdata ), + .s_axis_operation_tvalid ( op_tvalid ), + .s_axis_operation_tdata ( op_tdata ), + .m_axis_result_tvalid ( r_tvalid ), + .m_axis_result_tdata ( r_tdata ) +); +//------------------------Body--------------------------- +assign a_tvalid = 1'b1; +assign a_tdata = din0_buf1; +assign b_tvalid = 1'b1; +assign b_tdata = din1_buf1; +assign op_tvalid = 1'b1; +assign dout_i = r_tdata[0]; + +always @(*) begin + case (opcode_buf1) + AP_OEQ : op_tdata = OP_EQ; + AP_OGT : op_tdata = OP_GT; + AP_OGE : op_tdata = OP_GE; + AP_OLT : op_tdata = OP_LT; + AP_OLE : op_tdata = OP_LE; + AP_ONE : op_tdata = OP_NE; + AP_UNO : op_tdata = OP_UO; + default : op_tdata = OP_EQ; + endcase +end + +always @(posedge clk) begin + if (ce) begin + din0_buf1 <= din0; + din1_buf1 <= din1; + opcode_buf1 <= opcode; + end +end + +always @ (posedge clk) begin + ce_r <= ce; +end + +always @ (posedge clk) begin + if (ce_r) begin + dout_r <= dout_i; + end +end + +assign dout = ce_r?dout_i:dout_r; +endmodule +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_ap_hmul_2_max_dsp_16 ( + input wire aclk, + input wire aclken, + input wire s_axis_a_tvalid, + input wire [15:0] s_axis_a_tdata, + input wire s_axis_b_tvalid, + input wire [15:0] s_axis_b_tdata, + output wire m_axis_result_tvalid, + output wire [15:0] m_axis_result_tdata +); + + reg [15:0] a_reg, b_reg, res_reg; + wire [15:0] res; + + always @(posedge aclk) begin + if (aclken) begin + a_reg <= s_axis_a_tdata; + b_reg <= s_axis_b_tdata; + res_reg <= res; + end + end + +`ifdef complex_dsp + mult_fp_16 u_mult_fp ( + .a(a_reg), + .b(b_reg), + .out(res) + ); +`else +FPMult_16 u_FPMult (.clk(), .rst(1'b0), .a(a_reg), .b(b_reg), .result(res), .flags()); +`endif + assign m_axis_result_tdata = res_reg; + +endmodule + + +module td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 +#(parameter + ID = 20, + NUM_STAGE = 4, + din0_WIDTH = 16, + din1_WIDTH = 16, + dout_WIDTH = 16 +)( + input wire clk, + input wire reset, + input wire ce, + input wire [din0_WIDTH-1:0] din0, + input wire [din1_WIDTH-1:0] din1, + output wire [dout_WIDTH-1:0] dout +); +//------------------------Local signal------------------- +wire aclk; +wire aclken; +wire a_tvalid; +wire [15:0] a_tdata; +wire b_tvalid; +wire [15:0] b_tdata; +wire r_tvalid; +wire [15:0] r_tdata; +reg [din0_WIDTH-1:0] din0_buf1; +reg [din1_WIDTH-1:0] din1_buf1; +reg ce_r; +wire [dout_WIDTH-1:0] dout_i; +reg [dout_WIDTH-1:0] dout_r; +//------------------------Instantiation------------------ +td_fused_top_ap_hmul_2_max_dsp_16 td_fused_top_ap_hmul_2_max_dsp_16_u ( + .aclk ( aclk ), + .aclken ( aclken ), + .s_axis_a_tvalid ( a_tvalid ), + .s_axis_a_tdata ( a_tdata ), + .s_axis_b_tvalid ( b_tvalid ), + .s_axis_b_tdata ( b_tdata ), + .m_axis_result_tvalid ( r_tvalid ), + .m_axis_result_tdata ( r_tdata ) +); +//------------------------Body--------------------------- +assign aclk = clk; +assign aclken = ce_r; +assign a_tvalid = 1'b1; +assign a_tdata = din0_buf1; +assign b_tvalid = 1'b1; +assign b_tdata = din1_buf1; +assign dout_i = r_tdata; + +always @(posedge clk) begin + if (ce) begin + din0_buf1 <= din0; + din1_buf1 <= din1; + end +end + +always @ (posedge clk) begin + ce_r <= ce; +end + +always @ (posedge clk) begin + if (ce_r) begin + dout_r <= dout_i; + end +end + +assign dout = ce_r?dout_i:dout_r; +endmodule +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 +#(parameter + ID = 37, + NUM_STAGE = 5, + din0_WIDTH = 16, + din1_WIDTH = 16, + dout_WIDTH = 16 +)( + input wire clk, + input wire reset, + input wire ce, + input wire [din0_WIDTH-1:0] din0, + input wire [din1_WIDTH-1:0] din1, + output wire [dout_WIDTH-1:0] dout +); +//------------------------Local signal------------------- +wire aclk; +wire aclken; +wire a_tvalid; +wire [15:0] a_tdata; +wire b_tvalid; +wire [15:0] b_tdata; +wire r_tvalid; +wire [15:0] r_tdata; +reg [din0_WIDTH-1:0] din0_buf1; +reg [din1_WIDTH-1:0] din1_buf1; +reg ce_r; +wire [dout_WIDTH-1:0] dout_i; +reg [dout_WIDTH-1:0] dout_r; +//------------------------Instantiation------------------ +// Just replace with the hadd, logic is similar enough. +//td_fused_top_ap_hsub_3_full_dsp_16 td_fused_top_ap_hsub_3_full_dsp_16_u ( +td_fused_top_ap_hadd_3_full_dsp_16 td_fused_top_ap_hsub_3_full_dsp_16_u ( + .aclk ( aclk ), + .aclken ( aclken ), + .s_axis_a_tvalid ( a_tvalid ), + .s_axis_a_tdata ( a_tdata ), + .s_axis_b_tvalid ( b_tvalid ), + .s_axis_b_tdata ( b_tdata ), + .m_axis_result_tvalid ( r_tvalid ), + .m_axis_result_tdata ( r_tdata ) +); +//------------------------Body--------------------------- +assign aclk = clk; +assign aclken = ce_r; +assign a_tvalid = 1'b1; +assign a_tdata = din0_buf1; +assign b_tvalid = 1'b1; +assign b_tdata = din1_buf1; +assign dout_i = r_tdata; + +always @(posedge clk) begin + if (ce) begin + din0_buf1 <= din0; + din1_buf1 <= din1; + end +end + +always @ (posedge clk) begin + ce_r <= ce; +end + +always @ (posedge clk) begin + if (ce_r) begin + dout_r <= dout_i; + end +end + +assign dout = ce_r?dout_i:dout_r; +endmodule +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps + + module td_fused_top_mac_muladd_10s_9ns_8ns_16_4_1_DSP48_0( + input clk, + input rst, + input ce, + input [10 - 1:0] in0, + input [9 - 1:0] in1, + input [8 - 1:0] in2, + output [16 - 1:0] dout); + +wire [27 - 1:0] a; +wire [18 - 1:0] b; +wire [48 - 1:0] c; +wire [45 - 1:0] m; +wire [48 - 1:0] p; +reg [45 - 1:0] m_reg; +reg [27 - 1:0] a_reg; +reg [18 - 1:0] b_reg; +reg [48 - 1:0] p_reg; + +assign a = (in0); +assign b = (in1); +assign c = (in2); + +assign m = a_reg * b_reg; +assign p = m_reg + c; + +always @(posedge clk) begin + if (ce) begin + m_reg <= m; + a_reg <= a; + b_reg <= b; + p_reg <= p; + end +end + +assign dout = p_reg; + +endmodule +`timescale 1 ns / 1 ps +module td_fused_top_mac_muladd_10s_9ns_8ns_16_4_1( + clk, + reset, + ce, + din0, + din1, + din2, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter din2_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input clk; +input reset; +input ce; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +input[din2_WIDTH - 1:0] din2; +output[dout_WIDTH - 1:0] dout; + + + +td_fused_top_mac_muladd_10s_9ns_8ns_16_4_1_DSP48_0 td_fused_top_mac_muladd_10s_9ns_8ns_16_4_1_DSP48_0_U( + .clk( clk ), + .rst( reset ), + .ce( ce ), + .in0( din0 ), + .in1( din1 ), + .in2( din2 ), + .dout( dout ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_mul_10s_9ns_16_1_1_Multiplier_0(a, b, p); +input[10 - 1 : 0] a; +input[9 - 1 : 0] b; +output[16 - 1 : 0] p; + +assign p = (a) * ({1'b0, b}); +endmodule +`timescale 1 ns / 1 ps +module td_fused_top_mul_10s_9ns_16_1_1( + din0, + din1, + dout); + +parameter ID = 32'd1; +parameter NUM_STAGE = 32'd1; +parameter din0_WIDTH = 32'd1; +parameter din1_WIDTH = 32'd1; +parameter dout_WIDTH = 32'd1; +input[din0_WIDTH - 1:0] din0; +input[din1_WIDTH - 1:0] din1; +output[dout_WIDTH - 1:0] dout; + + + +td_fused_top_mul_10s_9ns_16_1_1_Multiplier_0 td_fused_top_mul_10s_9ns_16_1_1_Multiplier_0_U( + .a( din0 ), + .b( din1 ), + .p( dout ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_regslice_both +#(parameter + DataWidth=32 +)( + input ap_clk , + input ap_rst, + + input [DataWidth-1:0] data_in , + input vld_in , + output ack_in , + output [DataWidth-1:0] data_out, + output vld_out, + input ack_out, + output apdone_blk +); + + +reg [1:0] B_V_data_1_state; +wire [DataWidth-1:0] B_V_data_1_data_in; +reg [DataWidth-1:0] B_V_data_1_data_out; +wire B_V_data_1_vld_reg; +wire B_V_data_1_vld_in; +wire B_V_data_1_vld_out; +reg [DataWidth-1:0] B_V_data_1_payload_A; +reg [DataWidth-1:0] B_V_data_1_payload_B; +reg B_V_data_1_sel_rd; +reg B_V_data_1_sel_wr; +wire B_V_data_1_sel; +wire B_V_data_1_load_A; +wire B_V_data_1_load_B; +wire B_V_data_1_state_cmp_full; +wire B_V_data_1_ack_in; +wire B_V_data_1_ack_out; + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + B_V_data_1_sel_rd <= 1'b0; + end else begin + if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin + B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd; + end else begin + B_V_data_1_sel_rd <= B_V_data_1_sel_rd; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + B_V_data_1_sel_wr <= 1'b0; + end else begin + if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin + B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr; + end else begin + B_V_data_1_sel_wr <= B_V_data_1_sel_wr; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + B_V_data_1_state <= 2'd0; + end else begin + if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin + B_V_data_1_state <= 2'd2; + end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin + B_V_data_1_state <= 2'd1; + end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin + B_V_data_1_state <= 2'd3; + end else begin + B_V_data_1_state <= 2'd2; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == B_V_data_1_load_A)) begin + B_V_data_1_payload_A <= B_V_data_1_data_in; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == B_V_data_1_load_B)) begin + B_V_data_1_payload_B <= B_V_data_1_data_in; + end +end + +always @ (*) begin + if ((1'b1 == B_V_data_1_sel)) begin + B_V_data_1_data_out = B_V_data_1_payload_B; + end else begin + B_V_data_1_data_out = B_V_data_1_payload_A; + end +end + +assign B_V_data_1_ack_in = B_V_data_1_state[1'd1]; +assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full); +assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr); +assign B_V_data_1_sel = B_V_data_1_sel_rd; +assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0); +assign B_V_data_1_vld_out = B_V_data_1_state[1'd0]; + +assign ack_in = B_V_data_1_ack_in; +assign B_V_data_1_data_in = data_in; +assign B_V_data_1_vld_in = vld_in; + +assign vld_out = B_V_data_1_vld_out; +assign data_out = B_V_data_1_data_out; +assign B_V_data_1_ack_out = ack_out; + +assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1)); + +endmodule // both + + + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_start_for_tdf10_readFilters68_U0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_start_for_tdf10_readFilters68_U0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_start_for_tdf10_readFilters68_U0_shiftReg +U_td_fused_top_start_for_tdf10_readFilters68_U0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_start_for_tdf11_readFilters74_U0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_start_for_tdf11_readFilters74_U0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_start_for_tdf11_readFilters74_U0_shiftReg +U_td_fused_top_start_for_tdf11_readFilters74_U0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_start_for_tdf12_readFilters78_U0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_start_for_tdf12_readFilters78_U0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_start_for_tdf12_readFilters78_U0_shiftReg +U_td_fused_top_start_for_tdf12_readFilters78_U0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_start_for_tdf1_readFilters18_U0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_start_for_tdf1_readFilters18_U0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_start_for_tdf1_readFilters18_U0_shiftReg +U_td_fused_top_start_for_tdf1_readFilters18_U0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_start_for_tdf2_readFilters24_U0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_start_for_tdf2_readFilters24_U0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_start_for_tdf2_readFilters24_U0_shiftReg +U_td_fused_top_start_for_tdf2_readFilters24_U0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_start_for_tdf3_readFilters30_U0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_start_for_tdf3_readFilters30_U0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_start_for_tdf3_readFilters30_U0_shiftReg +U_td_fused_top_start_for_tdf3_readFilters30_U0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_start_for_tdf4_readFilters36_U0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_start_for_tdf4_readFilters36_U0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_start_for_tdf4_readFilters36_U0_shiftReg +U_td_fused_top_start_for_tdf4_readFilters36_U0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_start_for_tdf5_readFilters40_U0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_start_for_tdf5_readFilters40_U0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_start_for_tdf5_readFilters40_U0_shiftReg +U_td_fused_top_start_for_tdf5_readFilters40_U0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_start_for_tdf6_readFilters46_U0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_start_for_tdf6_readFilters46_U0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_start_for_tdf6_readFilters46_U0_shiftReg +U_td_fused_top_start_for_tdf6_readFilters46_U0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_start_for_tdf7_readFilters52_U0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_start_for_tdf7_readFilters52_U0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_start_for_tdf7_readFilters52_U0_shiftReg +U_td_fused_top_start_for_tdf7_readFilters52_U0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_start_for_tdf8_readFilters56_U0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_start_for_tdf8_readFilters56_U0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_start_for_tdf8_readFilters56_U0_shiftReg +U_td_fused_top_start_for_tdf8_readFilters56_U0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_start_for_tdf9_readFilters62_U0_shiftReg ( + clk, + data, + ce, + a, + q); + +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input [DATA_WIDTH-1:0] data; +input ce; +input [ADDR_WIDTH-1:0] a; +output reg [DATA_WIDTH-1:0] q; + +reg[DATA_WIDTH-1:0] sr_0, sr_1; +integer i; + +always @ (posedge clk) + begin + if (ce) + begin + sr_0 <= data; + sr_1 <= sr_0; + + + end + end + +always @( sr_0, sr_1, a) begin + case (a) + 1'd0: q = sr_0; + 1'd1: q = sr_1; + default: q = sr_1; + endcase +end + +endmodule + +module td_fused_top_start_for_tdf9_readFilters62_U0 ( + clk, + reset, + if_empty_n, + if_read_ce, + if_read, + if_dout, + if_full_n, + if_write_ce, + if_write, + if_din); + +parameter MEM_STYLE = "shiftreg"; +parameter DATA_WIDTH = 32'd1; +parameter ADDR_WIDTH = 32'd1; +parameter DEPTH = 2'd2; + +input clk; +input reset; +output if_empty_n; +input if_read_ce; +input if_read; +output[DATA_WIDTH - 1:0] if_dout; +output if_full_n; +input if_write_ce; +input if_write; +input[DATA_WIDTH - 1:0] if_din; + +wire[ADDR_WIDTH - 1:0] shiftReg_addr ; +wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q; +wire shiftReg_ce; +reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}}; +reg internal_empty_n = 0; +reg internal_full_n = 1; + +assign if_full_n = internal_full_n; +assign if_empty_n = internal_empty_n; +assign shiftReg_data = if_din; +assign if_dout = shiftReg_q; + +always @ (posedge clk) begin + if (reset == 1'b1) + begin + mOutPtr <= ~{ADDR_WIDTH+1{1'b0}}; + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else begin + if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) && + ((if_write & if_write_ce) == 0 | internal_full_n == 0)) + begin + mOutPtr <= mOutPtr - 2'd1; + if (mOutPtr == 2'd0) + internal_empty_n <= 1'b0; + internal_full_n <= 1'b1; + end + else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) && + ((if_write & if_write_ce) == 1 & internal_full_n == 1)) + begin + mOutPtr <= mOutPtr + 2'd1; + internal_empty_n <= 1'b1; + if (mOutPtr == DEPTH - 2'd2) + internal_full_n <= 1'b0; + end + end +end + +assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}}; +assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n; + +td_fused_top_start_for_tdf9_readFilters62_U0_shiftReg +U_td_fused_top_start_for_tdf9_readFilters62_U0_ram ( + .clk(clk), + .data(shiftReg_data), + .ce(shiftReg_ce), + .a(shiftReg_addr), + .q(shiftReg_q) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf10_15 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + l1_filter_data_address0, + l1_filter_data_ce0, + l1_filter_data_d0, + l1_filter_data_q0, + l1_filter_data_we0, + l1_filter_data_address1, + l1_filter_data_ce1, + l1_filter_data_d1, + l1_filter_data_q1, + l1_filter_data_we1, + l2_filter_data_address0, + l2_filter_data_ce0, + l2_filter_data_d0, + l2_filter_data_q0, + l2_filter_data_we0, + l2_filter_data_address1, + l2_filter_data_ce1, + l2_filter_data_d1, + l2_filter_data_q1, + l2_filter_data_we1, + l1_adjustments_address0, + l1_adjustments_ce0, + l1_adjustments_d0, + l1_adjustments_q0, + l1_adjustments_we0, + l1_adjustments_address1, + l1_adjustments_ce1, + l1_adjustments_d1, + l1_adjustments_q1, + l1_adjustments_we1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_d0, + l2_adjustments_q0, + l2_adjustments_we0, + l2_adjustments_address1, + l2_adjustments_ce1, + l2_adjustments_d1, + l2_adjustments_q1, + l2_adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [11:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [11:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [11:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [11:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [16:0] l1_filter_data_address0; +output l1_filter_data_ce0; +output [63:0] l1_filter_data_d0; +input [63:0] l1_filter_data_q0; +output l1_filter_data_we0; +output [16:0] l1_filter_data_address1; +output l1_filter_data_ce1; +output [63:0] l1_filter_data_d1; +input [63:0] l1_filter_data_q1; +output l1_filter_data_we1; +output [14:0] l2_filter_data_address0; +output l2_filter_data_ce0; +output [15:0] l2_filter_data_d0; +input [15:0] l2_filter_data_q0; +output l2_filter_data_we0; +output [14:0] l2_filter_data_address1; +output l2_filter_data_ce1; +output [15:0] l2_filter_data_d1; +input [15:0] l2_filter_data_q1; +output l2_filter_data_we1; +output [8:0] l1_adjustments_address0; +output l1_adjustments_ce0; +output [47:0] l1_adjustments_d0; +input [47:0] l1_adjustments_q0; +output l1_adjustments_we0; +output [8:0] l1_adjustments_address1; +output l1_adjustments_ce1; +output [47:0] l1_adjustments_d1; +input [47:0] l1_adjustments_q1; +output l1_adjustments_we1; +output [5:0] l2_adjustments_address0; +output l2_adjustments_ce0; +output [47:0] l2_adjustments_d0; +input [47:0] l2_adjustments_q0; +output l2_adjustments_we0; +output [5:0] l2_adjustments_address1; +output l2_adjustments_ce1; +output [47:0] l2_adjustments_d1; +input [47:0] l2_adjustments_q1; +output l2_adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [11:0] dataflow_in_loop_TOP_LOOP38364_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP38364_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP38364_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP38364_U0_in_data_we0; +wire [11:0] dataflow_in_loop_TOP_LOOP38364_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP38364_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP38364_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP38364_U0_in_data_we1; +wire [16:0] dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_we0; +wire [16:0] dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_we1; +wire [8:0] dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_we0; +wire [8:0] dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_we1; +wire [14:0] dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_we1; +wire [11:0] dataflow_in_loop_TOP_LOOP38364_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP38364_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP38364_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP38364_U0_out_data_we0; +wire [11:0] dataflow_in_loop_TOP_LOOP38364_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP38364_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP38364_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP38364_U0_out_data_we1; +wire [5:0] dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_we0; +wire [5:0] dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_we1; +wire dataflow_in_loop_TOP_LOOP38364_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP38364_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP38364_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP38364_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP38364_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP38364_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP38364_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP38364_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP38364_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [16:0] loop_dataflow_input_count; +reg [16:0] loop_dataflow_output_count; +wire [16:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP38364_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP38364_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 17'd0; +#0 loop_dataflow_output_count = 17'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP38364 dataflow_in_loop_TOP_LOOP38364_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP38364_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP38364_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP38364_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP38364_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP38364_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP38364_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP38364_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP38364_U0_in_data_we1), + .l1_filter_data_address0(dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_address0), + .l1_filter_data_ce0(dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_ce0), + .l1_filter_data_d0(dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_d0), + .l1_filter_data_q0(l1_filter_data_q0), + .l1_filter_data_we0(dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_we0), + .l1_filter_data_address1(dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_address1), + .l1_filter_data_ce1(dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_ce1), + .l1_filter_data_d1(dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_d1), + .l1_filter_data_q1(64'd0), + .l1_filter_data_we1(dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_we1), + .l1_adjustments_address0(dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_address0), + .l1_adjustments_ce0(dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_ce0), + .l1_adjustments_d0(dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_d0), + .l1_adjustments_q0(l1_adjustments_q0), + .l1_adjustments_we0(dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_we0), + .l1_adjustments_address1(dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_address1), + .l1_adjustments_ce1(dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_ce1), + .l1_adjustments_d1(dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_d1), + .l1_adjustments_q1(48'd0), + .l1_adjustments_we1(dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_we1), + .l2_filter_data_address0(dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_address0), + .l2_filter_data_ce0(dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_ce0), + .l2_filter_data_d0(dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_d0), + .l2_filter_data_q0(l2_filter_data_q0), + .l2_filter_data_we0(dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_we0), + .l2_filter_data_address1(dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_address1), + .l2_filter_data_ce1(dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_ce1), + .l2_filter_data_d1(dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_d1), + .l2_filter_data_q1(16'd0), + .l2_filter_data_we1(dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP38364_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP38364_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP38364_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP38364_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP38364_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP38364_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP38364_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP38364_U0_out_data_we1), + .l2_adjustments_address0(dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_address0), + .l2_adjustments_ce0(dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_ce0), + .l2_adjustments_d0(dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_d0), + .l2_adjustments_q0(l2_adjustments_q0), + .l2_adjustments_we0(dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_we0), + .l2_adjustments_address1(dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_address1), + .l2_adjustments_ce1(dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_ce1), + .l2_adjustments_d1(dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_d1), + .l2_adjustments_q1(48'd0), + .l2_adjustments_we1(dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_we1), + .ap_start(dataflow_in_loop_TOP_LOOP38364_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP38364_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP38364_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP38364_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP38364_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP38364_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP38364_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 17'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP38364_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 17'd1); + end else if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP38364_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= 17'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 17'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP38364_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP38364_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 17'd1); + end else if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP38364_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP38364_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= 17'd0; + end + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP38364_U0_ap_done == 1'b1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == 17'd0) & (ap_start == 1'b0) & (dataflow_in_loop_TOP_LOOP38364_U0_ap_idle == 1'b1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP38364_U0_ap_ready == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP38364_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP38364_U0_ap_continue = 1'b0; + end +end + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP38364_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP38364_U0_ap_ready; + +assign bound_minus_1 = (17'd100352 - 17'd1); + +assign dataflow_in_loop_TOP_LOOP38364_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP38364_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP38364_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP38364_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP38364_U0_start_write = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP38364_U0_in_data_address0; + +assign in_data_address1 = 12'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP38364_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP38364_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign l1_adjustments_address0 = dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_address0; + +assign l1_adjustments_address1 = 9'd0; + +assign l1_adjustments_ce0 = dataflow_in_loop_TOP_LOOP38364_U0_l1_adjustments_ce0; + +assign l1_adjustments_ce1 = 1'b0; + +assign l1_adjustments_d0 = 48'd0; + +assign l1_adjustments_d1 = 48'd0; + +assign l1_adjustments_we0 = 1'b0; + +assign l1_adjustments_we1 = 1'b0; + +assign l1_filter_data_address0 = dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_address0; + +assign l1_filter_data_address1 = 17'd0; + +assign l1_filter_data_ce0 = dataflow_in_loop_TOP_LOOP38364_U0_l1_filter_data_ce0; + +assign l1_filter_data_ce1 = 1'b0; + +assign l1_filter_data_d0 = 64'd0; + +assign l1_filter_data_d1 = 64'd0; + +assign l1_filter_data_we0 = 1'b0; + +assign l1_filter_data_we1 = 1'b0; + +assign l2_adjustments_address0 = dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_address0; + +assign l2_adjustments_address1 = 6'd0; + +assign l2_adjustments_ce0 = dataflow_in_loop_TOP_LOOP38364_U0_l2_adjustments_ce0; + +assign l2_adjustments_ce1 = 1'b0; + +assign l2_adjustments_d0 = 48'd0; + +assign l2_adjustments_d1 = 48'd0; + +assign l2_adjustments_we0 = 1'b0; + +assign l2_adjustments_we1 = 1'b0; + +assign l2_filter_data_address0 = dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_address0; + +assign l2_filter_data_address1 = 15'd0; + +assign l2_filter_data_ce0 = dataflow_in_loop_TOP_LOOP38364_U0_l2_filter_data_ce0; + +assign l2_filter_data_ce1 = 1'b0; + +assign l2_filter_data_d0 = 16'd0; + +assign l2_filter_data_d1 = 16'd0; + +assign l2_filter_data_we0 = 1'b0; + +assign l2_filter_data_we1 = 1'b0; + +assign out_data_address0 = 12'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP38364_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP38364_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP38364_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP38364_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP38364_U0_out_data_write; + +endmodule //td_fused_top_tdf10_15 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf10_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 8'd1; +parameter ap_ST_fsm_pp0_stage0 = 8'd2; +parameter ap_ST_fsm_pp0_stage1 = 8'd4; +parameter ap_ST_fsm_pp0_stage2 = 8'd8; +parameter ap_ST_fsm_pp0_stage3 = 8'd16; +parameter ap_ST_fsm_state12 = 8'd32; +parameter ap_ST_fsm_state13 = 8'd64; +parameter ap_ST_fsm_state14 = 8'd128; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [9:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [9:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[9:0] accum_in_0_address0; +reg accum_in_0_ce0; +reg[9:0] accum_in_0_address1; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [7:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [9:0] x_reg_168; +reg [15:0] psum_7_08_reg_180; +reg [15:0] psum_6_07_reg_192; +reg [15:0] psum_5_06_reg_204; +reg [15:0] psum_4_05_reg_216; +reg [15:0] psum_3_04_reg_228; +reg [15:0] psum_2_03_reg_240; +reg [15:0] psum_1_02_reg_252; +reg [15:0] psum_0_01_reg_264; +wire [0:0] icmp_ln132_fu_321_p2; +reg [0:0] icmp_ln132_reg_492; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state6_pp0_stage0_iter1; +wire ap_block_state10_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln132_reg_492_pp0_iter1_reg; +reg [0:0] icmp_ln132_reg_492_pp0_iter2_reg; +reg [15:0] accum_in_0_load_reg_506; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state7_pp0_stage1_iter1; +wire ap_block_state11_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_0_load_72_reg_511; +reg [15:0] accum_in_0_load_73_reg_526; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state8_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_0_load_74_reg_531; +wire [9:0] add_ln132_fu_387_p2; +reg [9:0] add_ln132_reg_546; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state9_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_0_load_75_reg_551; +reg [15:0] accum_in_0_load_76_reg_556; +reg [15:0] accum_in_0_load_77_reg_571; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_0_load_78_reg_576; +wire [15:0] grp_fu_305_p2; +wire [15:0] grp_fu_310_p2; +reg ap_enable_reg_pp0_iter2; +wire [3:0] add_ln140_fu_432_p2; +wire ap_CS_fsm_state13; +wire [0:0] tmp_fu_415_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage1_subdone; +reg [9:0] ap_phi_mux_x_phi_fu_172_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_184_p4; +wire ap_block_pp0_stage1; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_196_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_208_p4; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_220_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_232_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_03_phi_fu_244_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_276; +wire ap_CS_fsm_state12; +reg [15:0] ap_phi_mux_phi_ln152_phi_fu_290_p8; +wire [2:0] trunc_ln140_fu_428_p1; +wire [63:0] zext_ln132_fu_327_p1; +wire [63:0] zext_ln136_fu_338_p1; +wire [63:0] zext_ln136_19_fu_349_p1; +wire [63:0] zext_ln136_20_fu_360_p1; +wire [63:0] zext_ln136_21_fu_371_p1; +wire [63:0] zext_ln136_22_fu_382_p1; +wire [63:0] zext_ln136_23_fu_399_p1; +wire [63:0] zext_ln136_24_fu_410_p1; +wire [63:0] zext_ln140_fu_423_p1; +wire [63:0] zext_ln140_4_fu_444_p1; +reg [15:0] grp_fu_305_p0; +reg [15:0] grp_fu_305_p1; +reg [15:0] grp_fu_310_p0; +reg [15:0] grp_fu_310_p1; +wire [9:0] or_ln136_fu_332_p2; +wire [9:0] or_ln136_19_fu_343_p2; +wire [9:0] or_ln136_20_fu_354_p2; +wire [9:0] or_ln136_21_fu_365_p2; +wire [9:0] or_ln136_22_fu_376_p2; +wire [9:0] or_ln136_23_fu_393_p2; +wire [9:0] or_ln136_24_fu_404_p2; +wire [2:0] or_ln140_fu_438_p2; +wire [0:0] icmp_ln152_fu_449_p2; +wire [0:0] icmp_ln152_7_fu_463_p2; +wire [15:0] select_ln152_fu_455_p3; +wire [0:0] icmp_ln152_8_fu_477_p2; +wire [15:0] select_ln152_7_fu_469_p3; +wire ap_CS_fsm_state14; +reg [7:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_514; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 8'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U622( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_305_p0), + .din1(grp_fu_305_p1), + .dout(grp_fu_305_p2) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U623( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_310_p0), + .din1(grp_fu_310_p1), + .dout(grp_fu_310_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + q_reg_276 <= 4'd0; + end else if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + q_reg_276 <= add_ln140_fu_432_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + x_reg_168 <= add_ln132_reg_546; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_168 <= 10'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_load_72_reg_511 <= accum_in_0_q0; + accum_in_0_load_reg_506 <= accum_in_0_q1; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_load_73_reg_526 <= accum_in_0_q1; + accum_in_0_load_74_reg_531 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_load_75_reg_551 <= accum_in_0_q1; + accum_in_0_load_76_reg_556 <= accum_in_0_q0; + add_ln132_reg_546 <= add_ln132_fu_387_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_0_load_77_reg_571 <= accum_in_0_q1; + accum_in_0_load_78_reg_576 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln132_reg_492 <= icmp_ln132_fu_321_p2; + icmp_ln132_reg_492_pp0_iter1_reg <= icmp_ln132_reg_492; + icmp_ln132_reg_492_pp0_iter2_reg <= icmp_ln132_reg_492_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_0_01_reg_264 <= grp_fu_305_p2; + psum_1_02_reg_252 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_2_03_reg_240 <= grp_fu_305_p2; + psum_3_04_reg_228 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + psum_4_05_reg_216 <= grp_fu_305_p2; + psum_5_06_reg_204 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter2_reg == 1'd1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + psum_6_07_reg_192 <= grp_fu_305_p2; + psum_7_08_reg_180 <= grp_fu_310_p2; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address0 = zext_ln136_24_fu_410_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address0 = zext_ln136_22_fu_382_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address0 = zext_ln136_20_fu_360_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address0 = zext_ln136_fu_338_p1; + end else begin + accum_in_0_address0 = 'bx; + end + end else begin + accum_in_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address1 = zext_ln136_23_fu_399_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address1 = zext_ln136_21_fu_371_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address1 = zext_ln136_19_fu_349_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address1 = zext_ln132_fu_327_p1; + end else begin + accum_in_0_address1 = 'bx; + end + end else begin + accum_in_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln132_reg_492 == 1'd0)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + if ((trunc_ln140_fu_428_p1 == 3'd0)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_0_01_reg_264; + end else if ((1'b1 == ap_condition_514)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_6_07_reg_192; + end else if ((trunc_ln140_fu_428_p1 == 3'd4)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_4_05_reg_216; + end else if ((trunc_ln140_fu_428_p1 == 3'd2)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_2_03_reg_240; + end else begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_x_phi_fu_172_p4 = add_ln132_reg_546; + end else begin + ap_phi_mux_x_phi_fu_172_p4 = x_reg_168; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_6_07_phi_fu_196_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_4_05_phi_fu_220_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p0 = ap_phi_mux_psum_2_03_phi_fu_244_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p0 = grp_fu_305_p2; + end else begin + grp_fu_305_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p1 = accum_in_0_load_77_reg_571; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p1 = accum_in_0_load_75_reg_551; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p1 = accum_in_0_load_73_reg_526; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p1 = accum_in_0_load_reg_506; + end else begin + grp_fu_305_p1 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p0 = ap_phi_mux_psum_7_08_phi_fu_184_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p0 = ap_phi_mux_psum_5_06_phi_fu_208_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p0 = ap_phi_mux_psum_3_04_phi_fu_232_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p0 = grp_fu_310_p2; + end else begin + grp_fu_310_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p1 = accum_in_0_load_78_reg_576; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p1 = accum_in_0_load_76_reg_556; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p1 = accum_in_0_load_74_reg_531; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p1 = accum_in_0_load_72_reg_511; + end else begin + grp_fu_310_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (icmp_ln132_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (icmp_ln132_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_state14; + end + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln140_4_fu_444_p1; + +assign accum_out_address1 = zext_ln140_fu_423_p1; + +assign accum_out_d0 = ((icmp_ln152_8_fu_477_p2[0:0] == 1'b1) ? psum_5_06_reg_204 : select_ln152_7_fu_469_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln152_phi_fu_290_p8; + +assign add_ln132_fu_387_p2 = (x_reg_168 + 10'd8); + +assign add_ln140_fu_432_p2 = (q_reg_276 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_state14 = ap_CS_fsm[32'd7]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_514 = (~(trunc_ln140_fu_428_p1 == 3'd0) & ~(trunc_ln140_fu_428_p1 == 3'd4) & ~(trunc_ln140_fu_428_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_03_phi_fu_244_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_232_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_220_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_208_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_196_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_184_p4 = grp_fu_310_p2; + +assign icmp_ln132_fu_321_p2 = ((ap_phi_mux_x_phi_fu_172_p4 < 10'd576) ? 1'b1 : 1'b0); + +assign icmp_ln152_7_fu_463_p2 = ((or_ln140_fu_438_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln152_8_fu_477_p2 = ((or_ln140_fu_438_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln152_fu_449_p2 = ((or_ln140_fu_438_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln136_19_fu_343_p2 = (x_reg_168 | 10'd2); + +assign or_ln136_20_fu_354_p2 = (x_reg_168 | 10'd3); + +assign or_ln136_21_fu_365_p2 = (x_reg_168 | 10'd4); + +assign or_ln136_22_fu_376_p2 = (x_reg_168 | 10'd5); + +assign or_ln136_23_fu_393_p2 = (x_reg_168 | 10'd6); + +assign or_ln136_24_fu_404_p2 = (x_reg_168 | 10'd7); + +assign or_ln136_fu_332_p2 = (ap_phi_mux_x_phi_fu_172_p4 | 10'd1); + +assign or_ln140_fu_438_p2 = (trunc_ln140_fu_428_p1 | 3'd1); + +assign select_ln152_7_fu_469_p3 = ((icmp_ln152_7_fu_463_p2[0:0] == 1'b1) ? psum_3_04_reg_228 : select_ln152_fu_455_p3); + +assign select_ln152_fu_455_p3 = ((icmp_ln152_fu_449_p2[0:0] == 1'b1) ? psum_1_02_reg_252 : psum_7_08_reg_180); + +assign tmp_fu_415_p3 = q_reg_276[32'd3]; + +assign trunc_ln140_fu_428_p1 = q_reg_276[2:0]; + +assign zext_ln132_fu_327_p1 = ap_phi_mux_x_phi_fu_172_p4; + +assign zext_ln136_19_fu_349_p1 = or_ln136_19_fu_343_p2; + +assign zext_ln136_20_fu_360_p1 = or_ln136_20_fu_354_p2; + +assign zext_ln136_21_fu_371_p1 = or_ln136_21_fu_365_p2; + +assign zext_ln136_22_fu_382_p1 = or_ln136_22_fu_376_p2; + +assign zext_ln136_23_fu_399_p1 = or_ln136_23_fu_393_p2; + +assign zext_ln136_24_fu_410_p1 = or_ln136_24_fu_404_p2; + +assign zext_ln136_fu_338_p1 = or_ln136_fu_332_p2; + +assign zext_ln140_4_fu_444_p1 = or_ln140_fu_438_p2; + +assign zext_ln140_fu_423_p1 = q_reg_276; + +endmodule //td_fused_top_tdf10_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf10_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_24, + accum_in_24_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 7'd1; +parameter ap_ST_fsm_state2 = 7'd2; +parameter ap_ST_fsm_state3 = 7'd4; +parameter ap_ST_fsm_state4 = 7'd8; +parameter ap_ST_fsm_state5 = 7'd16; +parameter ap_ST_fsm_state6 = 7'd32; +parameter ap_ST_fsm_state7 = 7'd64; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_24; +output accum_in_24_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_24; +reg accum_in_24_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [6:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln164_fu_74_p2; +reg [3:0] add_ln164_reg_91; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln164_fu_85_p2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state7; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln164_fu_80_p1; +reg [15:0] accum_in_24_preg; +reg [6:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 7'd1; +#0 accum_in_24_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U626( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_q0), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_24_preg <= 16'd0; + end else begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_24_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + i_1_1_reg_44 <= add_ln164_reg_91; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln164_reg_91 <= add_ln164_fu_74_p2; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_24 = sum_01_reg_55; + end else begin + accum_in_24 = accum_in_24_preg; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_24_ap_vld = 1'b1; + end else begin + accum_in_24_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln164_fu_80_p1; + +assign add_ln164_fu_74_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln164_fu_85_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln164_fu_80_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf10_accum_2 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf10_adjustments_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 48; +parameter AWIDTH = 9; +parameter MEM_SIZE = 512; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf10_adjustments( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd48; +parameter AddressRange = 32'd512; +parameter AddressWidth = 32'd9; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf10_adjustments_ram td_fused_top_tdf10_adjustments_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf10_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + indices_23_out_din, + indices_23_out_full_n, + indices_23_out_write, + ap_return +); + +parameter ap_ST_fsm_state1 = 17'd1; +parameter ap_ST_fsm_state2 = 17'd2; +parameter ap_ST_fsm_state3 = 17'd4; +parameter ap_ST_fsm_state4 = 17'd8; +parameter ap_ST_fsm_state5 = 17'd16; +parameter ap_ST_fsm_state6 = 17'd32; +parameter ap_ST_fsm_state7 = 17'd64; +parameter ap_ST_fsm_state8 = 17'd128; +parameter ap_ST_fsm_state9 = 17'd256; +parameter ap_ST_fsm_state10 = 17'd512; +parameter ap_ST_fsm_state11 = 17'd1024; +parameter ap_ST_fsm_state12 = 17'd2048; +parameter ap_ST_fsm_state13 = 17'd4096; +parameter ap_ST_fsm_state14 = 17'd8192; +parameter ap_ST_fsm_state15 = 17'd16384; +parameter ap_ST_fsm_state16 = 17'd32768; +parameter ap_ST_fsm_state17 = 17'd65536; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_read; +output [8:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [14:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [14:0] indices_23_out_din; +input indices_23_out_full_n; +output indices_23_out_write; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg indices_23_read; +reg indices_23_out_write; + +reg ap_done_reg; + reg [16:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg indices_23_out_blk_n; +wire ap_CS_fsm_state4; +reg [15:0] tmp_110_i_i_reg_183; +reg [15:0] tmp_111_i_i_reg_188; +wire [15:0] grp_fu_93_p2; +reg [15:0] sub_i_i_i_reg_193; +wire ap_CS_fsm_state8; +wire ap_CS_fsm_state9; +wire [15:0] grp_fu_98_p2; +reg [15:0] mul_i_i_i_reg_203; +wire ap_CS_fsm_state12; +wire ap_CS_fsm_state13; +wire [63:0] zext_ln220_fu_106_p1; +reg ap_block_state1; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_89_p1; +wire [15:0] grp_fu_93_p1; +wire [15:0] grp_fu_98_p1; +wire [8:0] trunc_ln251_fu_102_p1; +wire [15:0] trunc_ln220_fu_111_p1; +wire [15:0] grp_fu_89_p2; +wire ap_CS_fsm_state17; +wire [15:0] bitcast_ln648_fu_148_p1; +wire [0:0] tmp_fu_152_p3; +reg [16:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 17'd1; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U630( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(mul_i_i_i_reg_203), + .din1(grp_fu_89_p1), + .dout(grp_fu_89_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U631( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sums_read), + .din1(grp_fu_93_p1), + .dout(grp_fu_93_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U632( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_193), + .din1(grp_fu_98_p1), + .dout(grp_fu_98_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + mul_i_i_i_reg_203 <= grp_fu_98_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sub_i_i_i_reg_193 <= grp_fu_93_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tmp_110_i_i_reg_183 <= {{adjustments_q0[31:16]}}; + tmp_111_i_i_reg_188 <= {{adjustments_q0[47:32]}}; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_out_blk_n = indices_23_out_full_n; + end else begin + indices_23_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_out_write = 1'b1; + end else begin + indices_23_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign adjustments_address0 = zext_ln220_fu_106_p1; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_return = ((tmp_fu_152_p3[0:0] == 1'b1) ? 16'd0 : grp_fu_89_p2); + +assign bitcast_ln648_fu_148_p1 = grp_fu_89_p2; + +assign grp_fu_89_p1 = tmp_111_i_i_reg_188; + +assign grp_fu_93_p1 = trunc_ln220_fu_111_p1; + +assign grp_fu_98_p1 = tmp_110_i_i_reg_183; + +assign indices_23_out_din = indices_23_dout; + +assign tmp_fu_152_p3 = bitcast_ln648_fu_148_p1[32'd15]; + +assign trunc_ln220_fu_111_p1 = adjustments_q0[15:0]; + +assign trunc_ln251_fu_102_p1 = indices_23_dout[8:0]; + +assign zext_ln220_fu_106_p1 = trunc_ln251_fu_102_p1; + +endmodule //td_fused_top_tdf10_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf10_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_q0, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [9:0] ifmap_vec_address0; +output ifmap_vec_ce0; +input [15:0] ifmap_vec_q0; +output [9:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +input [15:0] weight_vecs_0_q0; +output [9:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_ce0; +reg weight_vecs_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [9:0] indvar_flatten17_reg_97; +reg [8:0] indvar_flatten_reg_108; +reg [1:0] jj_reg_119; +reg [6:0] ic_reg_131; +reg [1:0] ii_reg_142; +wire [9:0] add_ln147_8_fu_157_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln147_fu_163_p2; +reg [0:0] icmp_ln147_reg_408; +reg [0:0] icmp_ln147_reg_408_pp0_iter1_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter2_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter3_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter4_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter5_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter6_reg; +wire [0:0] icmp_ln148_fu_169_p2; +reg [0:0] icmp_ln148_reg_412; +wire [0:0] and_ln147_fu_195_p2; +reg [0:0] and_ln147_reg_419; +wire [1:0] add_ln148_fu_201_p2; +reg [1:0] add_ln148_reg_424; +wire [6:0] select_ln148_fu_213_p3; +reg [6:0] select_ln148_reg_429; +wire [1:0] select_ln148_22_fu_221_p3; +reg [1:0] select_ln148_22_reg_434; +wire [5:0] trunc_ln150_fu_229_p1; +reg [5:0] trunc_ln150_reg_440; +reg [5:0] trunc_ln150_reg_440_pp0_iter1_reg; +reg [5:0] trunc_ln150_reg_440_pp0_iter2_reg; +reg [5:0] trunc_ln150_reg_440_pp0_iter3_reg; +reg [5:0] trunc_ln150_reg_440_pp0_iter4_reg; +reg [5:0] trunc_ln150_reg_440_pp0_iter5_reg; +reg [5:0] trunc_ln150_reg_440_pp0_iter6_reg; +wire [6:0] add_ln149_fu_233_p2; +wire [8:0] select_ln148_24_fu_245_p3; +wire [1:0] select_ln147_23_fu_287_p3; +reg [1:0] select_ln147_23_reg_455; +reg ap_enable_reg_pp0_iter1; +wire [3:0] select_ln148_23_fu_370_p3; +reg [3:0] select_ln148_23_reg_460; +reg [3:0] select_ln148_23_reg_460_pp0_iter2_reg; +reg [3:0] select_ln148_23_reg_460_pp0_iter3_reg; +reg [3:0] select_ln148_23_reg_460_pp0_iter4_reg; +reg [3:0] select_ln148_23_reg_460_pp0_iter5_reg; +reg [3:0] select_ln148_23_reg_460_pp0_iter6_reg; +reg [15:0] ifmap_vec_load_reg_475; +reg [15:0] weight_vecs_0_load_reg_480; +wire [15:0] grp_fu_153_p2; +reg [15:0] mul_reg_485; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg [1:0] ap_phi_mux_jj_phi_fu_123_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_146_p4; +wire [63:0] p_cast25_fu_386_p1; +wire [63:0] idxprom30_fu_398_p1; +wire [0:0] icmp_ln149_fu_189_p2; +wire [0:0] xor_ln147_fu_183_p2; +wire [1:0] select_ln147_fu_175_p3; +wire [0:0] or_ln148_fu_207_p2; +wire [8:0] add_ln148_8_fu_239_p2; +wire [3:0] shl_ln_fu_257_p3; +wire [3:0] zext_ln150_fu_253_p1; +wire [3:0] sub_ln150_fu_265_p2; +wire [3:0] zext_ln150_11_fu_271_p1; +wire [1:0] add_ln147_fu_281_p2; +wire [3:0] tmp_fu_298_p3; +wire [3:0] select_ln147_30_cast_fu_294_p1; +wire [3:0] shl_ln150_mid1_fu_316_p3; +wire [3:0] zext_ln150_17_fu_312_p1; +wire [3:0] sub_ln150_10_fu_324_p2; +wire [3:0] add_ln150_fu_275_p2; +wire [3:0] empty_150_fu_306_p2; +wire [3:0] select_ln148_29_cast_fu_344_p1; +wire [3:0] empty_151_fu_347_p2; +wire [3:0] select_ln147_24_fu_330_p3; +wire [3:0] zext_ln150_18_fu_361_p1; +wire [3:0] add_ln150_9_fu_364_p2; +wire [3:0] select_ln147_25_fu_337_p3; +wire [9:0] tmp_203_cast_fu_353_p3; +wire [9:0] select_ln148_cast_fu_377_p1; +wire [9:0] empty_152_fu_380_p2; +wire [9:0] p_fu_392_p3; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U618( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_load_reg_475), + .din1(weight_vecs_0_load_reg_480), + .dout(grp_fu_153_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_reg_131 <= add_ln149_fu_233_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_reg_131 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ii_reg_142 <= select_ln147_23_reg_455; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_142 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten17_reg_97 <= add_ln147_8_fu_157_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten17_reg_97 <= 10'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_108 <= select_ln148_24_fu_245_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_108 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_119 <= select_ln148_22_reg_434; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_119 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln148_reg_424 <= add_ln148_fu_201_p2; + and_ln147_reg_419 <= and_ln147_fu_195_p2; + icmp_ln148_reg_412 <= icmp_ln148_fu_169_p2; + select_ln148_reg_429 <= select_ln148_fu_213_p3; + trunc_ln150_reg_440 <= trunc_ln150_fu_229_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln147_reg_408 <= icmp_ln147_fu_163_p2; + icmp_ln147_reg_408_pp0_iter1_reg <= icmp_ln147_reg_408; + trunc_ln150_reg_440_pp0_iter1_reg <= trunc_ln150_reg_440; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln147_reg_408_pp0_iter2_reg <= icmp_ln147_reg_408_pp0_iter1_reg; + icmp_ln147_reg_408_pp0_iter3_reg <= icmp_ln147_reg_408_pp0_iter2_reg; + icmp_ln147_reg_408_pp0_iter4_reg <= icmp_ln147_reg_408_pp0_iter3_reg; + icmp_ln147_reg_408_pp0_iter5_reg <= icmp_ln147_reg_408_pp0_iter4_reg; + icmp_ln147_reg_408_pp0_iter6_reg <= icmp_ln147_reg_408_pp0_iter5_reg; + select_ln148_23_reg_460_pp0_iter2_reg <= select_ln148_23_reg_460; + select_ln148_23_reg_460_pp0_iter3_reg <= select_ln148_23_reg_460_pp0_iter2_reg; + select_ln148_23_reg_460_pp0_iter4_reg <= select_ln148_23_reg_460_pp0_iter3_reg; + select_ln148_23_reg_460_pp0_iter5_reg <= select_ln148_23_reg_460_pp0_iter4_reg; + select_ln148_23_reg_460_pp0_iter6_reg <= select_ln148_23_reg_460_pp0_iter5_reg; + trunc_ln150_reg_440_pp0_iter2_reg <= trunc_ln150_reg_440_pp0_iter1_reg; + trunc_ln150_reg_440_pp0_iter3_reg <= trunc_ln150_reg_440_pp0_iter2_reg; + trunc_ln150_reg_440_pp0_iter4_reg <= trunc_ln150_reg_440_pp0_iter3_reg; + trunc_ln150_reg_440_pp0_iter5_reg <= trunc_ln150_reg_440_pp0_iter4_reg; + trunc_ln150_reg_440_pp0_iter6_reg <= trunc_ln150_reg_440_pp0_iter5_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_load_reg_475 <= ifmap_vec_q0; + weight_vecs_0_load_reg_480 <= weight_vecs_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_reg_485 <= grp_fu_153_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + select_ln147_23_reg_455 <= select_ln147_23_fu_287_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_22_reg_434 <= select_ln148_22_fu_221_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_23_reg_460 <= select_ln148_23_fu_370_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_fu_163_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_146_p4 = select_ln147_23_reg_455; + end else begin + ap_phi_mux_ii_phi_fu_146_p4 = ii_reg_142; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_123_p4 = select_ln148_22_reg_434; + end else begin + ap_phi_mux_jj_phi_fu_123_p4 = jj_reg_119; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_8_fu_157_p2 = (indvar_flatten17_reg_97 + 10'd1); + +assign add_ln147_fu_281_p2 = (ap_phi_mux_ii_phi_fu_146_p4 + 2'd1); + +assign add_ln148_8_fu_239_p2 = (indvar_flatten_reg_108 + 9'd1); + +assign add_ln148_fu_201_p2 = (select_ln147_fu_175_p3 + 2'd1); + +assign add_ln149_fu_233_p2 = (select_ln148_fu_213_p3 + 7'd1); + +assign add_ln150_9_fu_364_p2 = (select_ln147_24_fu_330_p3 + zext_ln150_18_fu_361_p1); + +assign add_ln150_fu_275_p2 = (sub_ln150_fu_265_p2 + zext_ln150_11_fu_271_p1); + +assign and_ln147_fu_195_p2 = (xor_ln147_fu_183_p2 & icmp_ln149_fu_189_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign empty_150_fu_306_p2 = (tmp_fu_298_p3 - select_ln147_30_cast_fu_294_p1); + +assign empty_151_fu_347_p2 = (empty_150_fu_306_p2 + select_ln148_29_cast_fu_344_p1); + +assign empty_152_fu_380_p2 = (tmp_203_cast_fu_353_p3 + select_ln148_cast_fu_377_p1); + +assign icmp_ln147_fu_163_p2 = ((indvar_flatten17_reg_97 == 10'd576) ? 1'b1 : 1'b0); + +assign icmp_ln148_fu_169_p2 = ((indvar_flatten_reg_108 == 9'd192) ? 1'b1 : 1'b0); + +assign icmp_ln149_fu_189_p2 = ((ic_reg_131 == 7'd64) ? 1'b1 : 1'b0); + +assign idxprom30_fu_398_p1 = p_fu_392_p3; + +assign ifmap_vec_address0 = p_cast25_fu_386_p1; + +assign or_ln148_fu_207_p2 = (icmp_ln148_fu_169_p2 | and_ln147_fu_195_p2); + +assign p_cast25_fu_386_p1 = empty_152_fu_380_p2; + +assign p_fu_392_p3 = {{select_ln148_23_reg_460_pp0_iter6_reg}, {trunc_ln150_reg_440_pp0_iter6_reg}}; + +assign products_0_address0 = idxprom30_fu_398_p1; + +assign products_0_d0 = mul_reg_485; + +assign select_ln147_23_fu_287_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? add_ln147_fu_281_p2 : ap_phi_mux_ii_phi_fu_146_p4); + +assign select_ln147_24_fu_330_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? sub_ln150_10_fu_324_p2 : sub_ln150_fu_265_p2); + +assign select_ln147_25_fu_337_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? sub_ln150_10_fu_324_p2 : add_ln150_fu_275_p2); + +assign select_ln147_30_cast_fu_294_p1 = select_ln147_23_fu_287_p3; + +assign select_ln147_fu_175_p3 = ((icmp_ln148_fu_169_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_123_p4); + +assign select_ln148_22_fu_221_p3 = ((and_ln147_fu_195_p2[0:0] == 1'b1) ? add_ln148_fu_201_p2 : select_ln147_fu_175_p3); + +assign select_ln148_23_fu_370_p3 = ((and_ln147_reg_419[0:0] == 1'b1) ? add_ln150_9_fu_364_p2 : select_ln147_25_fu_337_p3); + +assign select_ln148_24_fu_245_p3 = ((icmp_ln148_fu_169_p2[0:0] == 1'b1) ? 9'd1 : add_ln148_8_fu_239_p2); + +assign select_ln148_29_cast_fu_344_p1 = select_ln148_22_reg_434; + +assign select_ln148_cast_fu_377_p1 = select_ln148_reg_429; + +assign select_ln148_fu_213_p3 = ((or_ln148_fu_207_p2[0:0] == 1'b1) ? 7'd0 : ic_reg_131); + +assign shl_ln150_mid1_fu_316_p3 = {{add_ln147_fu_281_p2}, {2'd0}}; + +assign shl_ln_fu_257_p3 = {{ap_phi_mux_ii_phi_fu_146_p4}, {2'd0}}; + +assign sub_ln150_10_fu_324_p2 = (shl_ln150_mid1_fu_316_p3 - zext_ln150_17_fu_312_p1); + +assign sub_ln150_fu_265_p2 = (shl_ln_fu_257_p3 - zext_ln150_fu_253_p1); + +assign tmp_203_cast_fu_353_p3 = {{empty_151_fu_347_p2}, {6'd0}}; + +assign tmp_fu_298_p3 = {{select_ln147_23_fu_287_p3}, {2'd0}}; + +assign trunc_ln150_fu_229_p1 = select_ln148_fu_213_p3[5:0]; + +assign weight_vecs_0_address0 = p_cast25_fu_386_p1; + +assign xor_ln147_fu_183_p2 = (icmp_ln148_fu_169_p2 ^ 1'd1); + +assign zext_ln150_11_fu_271_p1 = jj_reg_119; + +assign zext_ln150_17_fu_312_p1 = add_ln147_fu_281_p2; + +assign zext_ln150_18_fu_361_p1 = add_ln148_reg_424; + +assign zext_ln150_fu_253_p1 = ap_phi_mux_ii_phi_fu_146_p4; + +endmodule //td_fused_top_tdf10_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf10_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 17; +parameter MEM_SIZE = 73728; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; + reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf10_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd73728; +parameter AddressWidth = 32'd17; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf10_filters_ram td_fused_top_tdf10_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf10_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + indices_2_out_din, + indices_2_out_full_n, + indices_2_out_write, + indices_2_out1_din, + indices_2_out1_full_n, + indices_2_out1_write, + write_r_din, + write_r_full_n, + write_r_write +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [8:0] indices_2_out_din; +input indices_2_out_full_n; +output indices_2_out_write; +output [14:0] indices_2_out1_din; +input indices_2_out1_full_n; +output indices_2_out1_write; +output write_r_din; +input write_r_full_n; +output write_r_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg indices_0_write; +reg indices_1_write; +reg indices_2_out_write; +reg indices_2_out1_write; +reg write_r_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [15:0] i_10; +reg [15:0] j_10; +reg [15:0] k_10; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg indices_2_out_blk_n; +reg indices_2_out1_blk_n; +reg write_r_blk_n; +reg [0:0] ap_phi_mux_j_19_flag_0_i_phi_fu_92_p6; +reg ap_block_state1; +wire [0:0] icmp_ln188_fu_167_p2; +wire [0:0] icmp_ln191_fu_180_p2; +reg [15:0] ap_phi_mux_j_19_new_0_i_phi_fu_106_p6; +wire [15:0] add_ln190_fu_173_p2; +reg [15:0] ap_phi_mux_k_19_new_0_i_phi_fu_119_p6; +wire [15:0] add_ln187_fu_160_p2; +wire [15:0] select_ln194_fu_198_p3; +wire [15:0] add_ln193_fu_186_p2; +wire [0:0] icmp_ln194_fu_192_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_10 = 16'd0; +#0 j_10 = 16'd0; +#0 k_10 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln191_fu_180_p2 == 1'd1) & (icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_10 <= select_ln194_fu_198_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_19_flag_0_i_phi_fu_92_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j_10 <= ap_phi_mux_j_19_new_0_i_phi_fu_106_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k_10 <= ap_phi_mux_k_19_new_0_i_phi_fu_119_p6; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln188_fu_167_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_19_flag_0_i_phi_fu_92_p6 = 1'd0; + end else if ((((icmp_ln191_fu_180_p2 == 1'd0) & (icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln191_fu_180_p2 == 1'd1) & (icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_19_flag_0_i_phi_fu_92_p6 = 1'd1; + end else begin + ap_phi_mux_j_19_flag_0_i_phi_fu_92_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln191_fu_180_p2 == 1'd0)) begin + ap_phi_mux_j_19_new_0_i_phi_fu_106_p6 = add_ln190_fu_173_p2; + end else if ((icmp_ln191_fu_180_p2 == 1'd1)) begin + ap_phi_mux_j_19_new_0_i_phi_fu_106_p6 = 16'd0; + end else begin + ap_phi_mux_j_19_new_0_i_phi_fu_106_p6 = 'bx; + end + end else begin + ap_phi_mux_j_19_new_0_i_phi_fu_106_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln188_fu_167_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_19_new_0_i_phi_fu_119_p6 = add_ln187_fu_160_p2; + end else if ((((icmp_ln191_fu_180_p2 == 1'd0) & (icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln191_fu_180_p2 == 1'd1) & (icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_19_new_0_i_phi_fu_119_p6 = 16'd0; + end else begin + ap_phi_mux_k_19_new_0_i_phi_fu_119_p6 = 'bx; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_blk_n = indices_2_out1_full_n; + end else begin + indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_write = 1'b1; + end else begin + indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_blk_n = indices_2_out_full_n; + end else begin + indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_write = 1'b1; + end else begin + indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_r_blk_n = write_r_full_n; + end else begin + write_r_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_r_write = 1'b1; + end else begin + write_r_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln187_fu_160_p2 = (k_10 + 16'd1); + +assign add_ln190_fu_173_p2 = (j_10 + 16'd1); + +assign add_ln193_fu_186_p2 = (i_10 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign icmp_ln188_fu_167_p2 = ((add_ln187_fu_160_p2 == 16'd512) ? 1'b1 : 1'b0); + +assign icmp_ln191_fu_180_p2 = ((add_ln190_fu_173_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign icmp_ln194_fu_192_p2 = ((add_ln193_fu_186_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign indices_0_din = i_10; + +assign indices_1_din = j_10; + +assign indices_2_out1_din = k_10[14:0]; + +assign indices_2_out_din = k_10[8:0]; + +assign select_ln194_fu_198_p3 = ((icmp_ln194_fu_192_p2[0:0] == 1'b1) ? 16'd0 : add_ln193_fu_186_p2); + +assign start_out = real_start; + +assign write_r_din = ((k_10 == 16'd511) ? 1'b1 : 1'b0); + +endmodule //td_fused_top_tdf10_get_next_ijk +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf10_l2_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 15; +parameter MEM_SIZE = 32768; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf10_l2_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd32768; +parameter AddressWidth = 32'd15; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf10_l2_filters_ram td_fused_top_tdf10_l2_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf10_l2_multiply66 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + intermediate_fmaps_read, + l2_filter_data_address0, + l2_filter_data_ce0, + l2_filter_data_q0, + l2_products_address0, + l2_products_ce0, + l2_products_we0, + l2_products_d0, + indices_23_dout, + indices_23_empty_n, + indices_23_read +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] intermediate_fmaps_read; +output [14:0] l2_filter_data_address0; +output l2_filter_data_ce0; +input [15:0] l2_filter_data_q0; +output [5:0] l2_products_address0; +output l2_products_ce0; +output l2_products_we0; +output [15:0] l2_products_d0; +input [14:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg l2_filter_data_ce0; +reg l2_products_ce0; +reg l2_products_we0; +reg indices_23_read; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [6:0] i_1_1_reg_106; +reg [14:0] l2_ichan_reg_165; +wire [6:0] add_ln20_fu_122_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln20_fu_128_p2; +reg [0:0] icmp_ln20_reg_175; +reg [0:0] icmp_ln20_reg_175_pp0_iter1_reg; +reg [0:0] icmp_ln20_reg_175_pp0_iter2_reg; +reg [0:0] icmp_ln20_reg_175_pp0_iter3_reg; +reg [0:0] icmp_ln20_reg_175_pp0_iter4_reg; +reg [0:0] icmp_ln20_reg_175_pp0_iter5_reg; +reg [0:0] icmp_ln20_reg_175_pp0_iter6_reg; +wire [5:0] l2_o_fu_134_p1; +reg [5:0] l2_o_reg_179; +reg [5:0] l2_o_reg_179_pp0_iter1_reg; +reg [5:0] l2_o_reg_179_pp0_iter2_reg; +reg [5:0] l2_o_reg_179_pp0_iter3_reg; +reg [5:0] l2_o_reg_179_pp0_iter4_reg; +reg [5:0] l2_o_reg_179_pp0_iter5_reg; +reg [5:0] l2_o_reg_179_pp0_iter6_reg; +wire [15:0] grp_fu_117_p2; +reg [15:0] mul_i_i_reg_194; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +wire [63:0] zext_ln29_26_fu_151_p1; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln29_fu_156_p1; +wire [14:0] tmp_s_fu_138_p3; +wire [14:0] add_ln29_fu_146_p2; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U637( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(l2_filter_data_q0), + .din1(intermediate_fmaps_read), + .dout(grp_fu_117_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_106 <= 7'd0; + end else if (((icmp_ln20_fu_128_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + i_1_1_reg_106 <= add_ln20_fu_122_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln20_reg_175 <= icmp_ln20_fu_128_p2; + icmp_ln20_reg_175_pp0_iter1_reg <= icmp_ln20_reg_175; + l2_o_reg_179_pp0_iter1_reg <= l2_o_reg_179; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln20_reg_175_pp0_iter2_reg <= icmp_ln20_reg_175_pp0_iter1_reg; + icmp_ln20_reg_175_pp0_iter3_reg <= icmp_ln20_reg_175_pp0_iter2_reg; + icmp_ln20_reg_175_pp0_iter4_reg <= icmp_ln20_reg_175_pp0_iter3_reg; + icmp_ln20_reg_175_pp0_iter5_reg <= icmp_ln20_reg_175_pp0_iter4_reg; + icmp_ln20_reg_175_pp0_iter6_reg <= icmp_ln20_reg_175_pp0_iter5_reg; + l2_o_reg_179_pp0_iter2_reg <= l2_o_reg_179_pp0_iter1_reg; + l2_o_reg_179_pp0_iter3_reg <= l2_o_reg_179_pp0_iter2_reg; + l2_o_reg_179_pp0_iter4_reg <= l2_o_reg_179_pp0_iter3_reg; + l2_o_reg_179_pp0_iter5_reg <= l2_o_reg_179_pp0_iter4_reg; + l2_o_reg_179_pp0_iter6_reg <= l2_o_reg_179_pp0_iter5_reg; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + l2_ichan_reg_165 <= indices_23_dout; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln20_fu_128_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + l2_o_reg_179 <= l2_o_fu_134_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln20_reg_175_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_i_i_reg_194 <= grp_fu_117_p2; + end +end + +always @ (*) begin + if ((icmp_ln20_fu_128_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + l2_filter_data_ce0 = 1'b1; + end else begin + l2_filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + l2_products_ce0 = 1'b1; + end else begin + l2_products_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln20_reg_175_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + l2_products_we0 = 1'b1; + end else begin + l2_products_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln20_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln20_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln20_fu_122_p2 = (i_1_1_reg_106 + 7'd1); + +assign add_ln29_fu_146_p2 = (tmp_s_fu_138_p3 + l2_ichan_reg_165); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign icmp_ln20_fu_128_p2 = ((i_1_1_reg_106 == 7'd64) ? 1'b1 : 1'b0); + +assign l2_filter_data_address0 = zext_ln29_26_fu_151_p1; + +assign l2_o_fu_134_p1 = i_1_1_reg_106[5:0]; + +assign l2_products_address0 = zext_ln29_fu_156_p1; + +assign l2_products_d0 = mul_i_i_reg_194; + +assign tmp_s_fu_138_p3 = {{l2_o_fu_134_p1}, {9'd0}}; + +assign zext_ln29_26_fu_151_p1 = add_ln29_fu_146_p2; + +assign zext_ln29_fu_156_p1 = l2_o_reg_179_pp0_iter6_reg; + +endmodule //td_fused_top_tdf10_l2_multiply66 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf10_l2_writeOutputs_165_running_sums_3_ram (addr0, ce0, d0, we0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 6; +parameter MEM_SIZE = 64; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf10_l2_writeOutputs_165_running_sums_3_ram.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf10_l2_writeOutputs_165_running_sums_3( + reset, + clk, + address0, + ce0, + we0, + d0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd64; +parameter AddressWidth = 32'd6; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_tdf10_l2_writeOutputs_165_running_sums_3_ram td_fused_top_tdf10_l2_writeOutputs_165_running_sums_3_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf10_l2_writeOutputs_165 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + write4_dout, + write4_empty_n, + write4_read, + l2_partial_sums_address0, + l2_partial_sums_ce0, + l2_partial_sums_q0, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_q0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state25 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [3:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [7:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [0:0] write4_dout; +input write4_empty_n; +output write4_read; +output [5:0] l2_partial_sums_address0; +output l2_partial_sums_ce0; +input [15:0] l2_partial_sums_q0; +output [11:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; +output [5:0] l2_adjustments_address0; +output l2_adjustments_ce0; +input [47:0] l2_adjustments_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg write4_read; +reg l2_partial_sums_ce0; +reg out_data_ce1; +reg out_data_we1; +reg l2_adjustments_ce0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg running_sums_3_ce0; +reg running_sums_3_we0; +wire [15:0] running_sums_3_d0; +wire [5:0] running_sums_3_address1; +reg running_sums_3_ce1; +wire [15:0] running_sums_3_q1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg write4_blk_n; +reg [6:0] ochan_reg_208; +reg [0:0] write4_read_reg_567; +wire [9:0] add_ln109_fu_273_p2; +reg [9:0] add_ln109_reg_573; +wire [6:0] add_ln86_fu_279_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_state13_pp0_stage0_iter11; +wire ap_block_state14_pp0_stage0_iter12; +wire ap_block_state15_pp0_stage0_iter13; +wire ap_block_state16_pp0_stage0_iter14; +wire ap_block_state17_pp0_stage0_iter15; +wire ap_block_state18_pp0_stage0_iter16; +wire ap_block_state19_pp0_stage0_iter17; +wire ap_block_state20_pp0_stage0_iter18; +wire ap_block_state21_pp0_stage0_iter19; +wire ap_block_state22_pp0_stage0_iter20; +wire ap_block_state23_pp0_stage0_iter21; +wire ap_block_state24_pp0_stage0_iter22; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln86_fu_285_p2; +wire [63:0] zext_ln86_fu_291_p1; +reg [63:0] zext_ln86_reg_587; +reg [63:0] zext_ln86_reg_587_pp0_iter1_reg; +reg [63:0] zext_ln86_reg_587_pp0_iter2_reg; +reg [63:0] zext_ln86_reg_587_pp0_iter3_reg; +reg [5:0] running_sums_3_addr_reg_597; +reg [5:0] running_sums_3_addr_reg_597_pp0_iter1_reg; +reg [5:0] running_sums_3_addr_reg_597_pp0_iter2_reg; +reg [5:0] running_sums_3_addr_reg_597_pp0_iter3_reg; +reg [5:0] running_sums_3_addr_reg_597_pp0_iter4_reg; +reg [5:0] running_sums_3_addr_reg_597_pp0_iter5_reg; +reg [5:0] running_sums_3_addr_reg_597_pp0_iter6_reg; +wire [1:0] trunc_ln99_fu_297_p1; +reg [1:0] trunc_ln99_reg_603; +reg [1:0] trunc_ln99_reg_603_pp0_iter1_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter2_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter3_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter4_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter5_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter6_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter7_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter8_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter9_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter10_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter11_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter12_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter13_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter14_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter15_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter16_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter17_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter18_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter19_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter20_reg; +wire [0:0] and_ln103_fu_307_p2; +reg [0:0] and_ln103_reg_610; +reg [0:0] and_ln103_reg_610_pp0_iter1_reg; +reg [0:0] and_ln103_reg_610_pp0_iter2_reg; +reg [0:0] and_ln103_reg_610_pp0_iter3_reg; +reg [0:0] and_ln103_reg_610_pp0_iter4_reg; +reg [0:0] and_ln103_reg_610_pp0_iter5_reg; +reg [0:0] and_ln103_reg_610_pp0_iter6_reg; +reg [0:0] and_ln103_reg_610_pp0_iter7_reg; +reg [0:0] and_ln103_reg_610_pp0_iter8_reg; +reg [0:0] and_ln103_reg_610_pp0_iter9_reg; +reg [0:0] and_ln103_reg_610_pp0_iter10_reg; +reg [0:0] and_ln103_reg_610_pp0_iter11_reg; +reg [0:0] and_ln103_reg_610_pp0_iter12_reg; +reg [0:0] and_ln103_reg_610_pp0_iter13_reg; +reg [0:0] and_ln103_reg_610_pp0_iter14_reg; +reg [0:0] and_ln103_reg_610_pp0_iter15_reg; +reg [0:0] and_ln103_reg_610_pp0_iter16_reg; +reg [0:0] and_ln103_reg_610_pp0_iter17_reg; +reg [0:0] and_ln103_reg_610_pp0_iter18_reg; +reg [0:0] and_ln103_reg_610_pp0_iter19_reg; +reg [0:0] and_ln103_reg_610_pp0_iter20_reg; +reg [3:0] lshr_ln_reg_614; +reg [3:0] lshr_ln_reg_614_pp0_iter1_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter2_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter3_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter4_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter5_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter6_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter7_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter8_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter9_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter10_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter11_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter12_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter13_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter14_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter15_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter16_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter17_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter18_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter19_reg; +reg [3:0] lshr_ln_reg_614_pp0_iter20_reg; +reg [15:0] val_reg_619; +reg [15:0] running_sums_3_load_reg_624; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_219_p2; +reg [15:0] sum_reg_634; +reg [15:0] tmp_104_i_i_reg_645; +reg [15:0] tmp_104_i_i_reg_645_pp0_iter8_reg; +reg [15:0] tmp_104_i_i_reg_645_pp0_iter9_reg; +reg [15:0] tmp_104_i_i_reg_645_pp0_iter10_reg; +reg [15:0] tmp_104_i_i_reg_645_pp0_iter11_reg; +reg [15:0] tmp_105_i_i_reg_650; +reg [15:0] tmp_105_i_i_reg_650_pp0_iter8_reg; +reg [15:0] tmp_105_i_i_reg_650_pp0_iter9_reg; +reg [15:0] tmp_105_i_i_reg_650_pp0_iter10_reg; +reg [15:0] tmp_105_i_i_reg_650_pp0_iter11_reg; +reg [15:0] tmp_105_i_i_reg_650_pp0_iter12_reg; +reg [15:0] tmp_105_i_i_reg_650_pp0_iter13_reg; +reg [15:0] tmp_105_i_i_reg_650_pp0_iter14_reg; +reg [15:0] tmp_105_i_i_reg_650_pp0_iter15_reg; +wire [15:0] grp_fu_227_p2; +reg [15:0] sub_i_i_i_reg_655; +wire [15:0] grp_fu_231_p2; +reg [15:0] normalized_reg_665; +wire [15:0] grp_fu_223_p2; +reg [15:0] biased_reg_675; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_enable_reg_pp0_iter22; +wire ap_block_pp0_stage0; +wire [63:0] sext_ln109_fu_509_p1; +reg [15:0] quad_3_39_fu_114; +wire [15:0] quad_3_58_fu_475_p3; +reg [15:0] quad_3_36_fu_118; +wire [15:0] quad_3_57_fu_467_p3; +reg [15:0] quad_3_40_fu_122; +wire [15:0] quad_3_55_fu_451_p3; +reg [15:0] quad_3_41_fu_126; +wire [15:0] quad_3_52_fu_427_p3; +wire [15:0] grp_fu_223_p1; +wire [15:0] grp_fu_227_p1; +wire [15:0] grp_fu_231_p1; +wire [7:0] tmp_fu_235_p3; +wire [4:0] tmp_s_fu_247_p3; +wire [8:0] zext_ln109_fu_243_p1; +wire [8:0] zext_ln109_7_fu_255_p1; +wire [8:0] sub_ln109_fu_259_p2; +wire [9:0] sub_ln109_cast_fu_265_p1; +wire [9:0] zext_ln109_8_fu_269_p1; +wire [0:0] icmp_ln103_fu_301_p2; +wire [15:0] trunc_ln95_fu_329_p1; +wire [15:0] data_V_fu_378_p1; +wire [0:0] p_Result_s_fu_381_p3; +wire [0:0] icmp_ln99_fu_396_p2; +wire [15:0] quad_0_fu_389_p3; +wire [0:0] icmp_ln99_7_fu_409_p2; +wire [15:0] quad_3_fu_401_p3; +wire [0:0] icmp_ln99_8_fu_422_p2; +wire [15:0] quad_3_51_fu_414_p3; +wire [15:0] quad_3_53_fu_435_p3; +wire [15:0] quad_3_54_fu_443_p3; +wire [15:0] quad_3_56_fu_459_p3; +wire [13:0] tmp_74_fu_503_p3; +wire [15:0] bitcast_ln109_12_fu_526_p1; +wire [15:0] bitcast_ln109_11_fu_522_p1; +wire [15:0] bitcast_ln109_10_fu_518_p1; +wire [15:0] bitcast_ln109_fu_514_p1; +wire ap_CS_fsm_state25; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +end + +td_fused_top_tdf10_l2_writeOutputs_165_running_sums_3 #( + .DataWidth( 16 ), + .AddressRange( 64 ), + .AddressWidth( 6 )) +running_sums_3_U( + .reset(ap_rst), + .clk(ap_clk), + .address0(running_sums_3_addr_reg_597_pp0_iter6_reg), + .ce0(running_sums_3_ce0), + .we0(running_sums_3_we0), + .d0(running_sums_3_d0), + .address1(running_sums_3_address1), + .ce1(running_sums_3_ce1), + .q1(running_sums_3_q1) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U642( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(running_sums_3_load_reg_624), + .din1(val_reg_619), + .dout(grp_fu_219_p2) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U643( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(normalized_reg_665), + .din1(grp_fu_223_p1), + .dout(grp_fu_223_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U644( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_reg_634), + .din1(grp_fu_227_p1), + .dout(grp_fu_227_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U645( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_655), + .din1(grp_fu_231_p1), + .dout(grp_fu_231_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end else if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_285_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ochan_reg_208 <= add_ln86_fu_279_p2; + end else if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ochan_reg_208 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + add_ln109_reg_573 <= add_ln109_fu_273_p2; + write4_read_reg_567 <= write4_dout; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_285_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + and_ln103_reg_610 <= and_ln103_fu_307_p2; + running_sums_3_addr_reg_597 <= zext_ln86_fu_291_p1; + trunc_ln99_reg_603 <= trunc_ln99_fu_297_p1; + zext_ln86_reg_587[6 : 0] <= zext_ln86_fu_291_p1[6 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + and_ln103_reg_610_pp0_iter10_reg <= and_ln103_reg_610_pp0_iter9_reg; + and_ln103_reg_610_pp0_iter11_reg <= and_ln103_reg_610_pp0_iter10_reg; + and_ln103_reg_610_pp0_iter12_reg <= and_ln103_reg_610_pp0_iter11_reg; + and_ln103_reg_610_pp0_iter13_reg <= and_ln103_reg_610_pp0_iter12_reg; + and_ln103_reg_610_pp0_iter14_reg <= and_ln103_reg_610_pp0_iter13_reg; + and_ln103_reg_610_pp0_iter15_reg <= and_ln103_reg_610_pp0_iter14_reg; + and_ln103_reg_610_pp0_iter16_reg <= and_ln103_reg_610_pp0_iter15_reg; + and_ln103_reg_610_pp0_iter17_reg <= and_ln103_reg_610_pp0_iter16_reg; + and_ln103_reg_610_pp0_iter18_reg <= and_ln103_reg_610_pp0_iter17_reg; + and_ln103_reg_610_pp0_iter19_reg <= and_ln103_reg_610_pp0_iter18_reg; + and_ln103_reg_610_pp0_iter20_reg <= and_ln103_reg_610_pp0_iter19_reg; + and_ln103_reg_610_pp0_iter2_reg <= and_ln103_reg_610_pp0_iter1_reg; + and_ln103_reg_610_pp0_iter3_reg <= and_ln103_reg_610_pp0_iter2_reg; + and_ln103_reg_610_pp0_iter4_reg <= and_ln103_reg_610_pp0_iter3_reg; + and_ln103_reg_610_pp0_iter5_reg <= and_ln103_reg_610_pp0_iter4_reg; + and_ln103_reg_610_pp0_iter6_reg <= and_ln103_reg_610_pp0_iter5_reg; + and_ln103_reg_610_pp0_iter7_reg <= and_ln103_reg_610_pp0_iter6_reg; + and_ln103_reg_610_pp0_iter8_reg <= and_ln103_reg_610_pp0_iter7_reg; + and_ln103_reg_610_pp0_iter9_reg <= and_ln103_reg_610_pp0_iter8_reg; + biased_reg_675 <= grp_fu_223_p2; + lshr_ln_reg_614_pp0_iter10_reg <= lshr_ln_reg_614_pp0_iter9_reg; + lshr_ln_reg_614_pp0_iter11_reg <= lshr_ln_reg_614_pp0_iter10_reg; + lshr_ln_reg_614_pp0_iter12_reg <= lshr_ln_reg_614_pp0_iter11_reg; + lshr_ln_reg_614_pp0_iter13_reg <= lshr_ln_reg_614_pp0_iter12_reg; + lshr_ln_reg_614_pp0_iter14_reg <= lshr_ln_reg_614_pp0_iter13_reg; + lshr_ln_reg_614_pp0_iter15_reg <= lshr_ln_reg_614_pp0_iter14_reg; + lshr_ln_reg_614_pp0_iter16_reg <= lshr_ln_reg_614_pp0_iter15_reg; + lshr_ln_reg_614_pp0_iter17_reg <= lshr_ln_reg_614_pp0_iter16_reg; + lshr_ln_reg_614_pp0_iter18_reg <= lshr_ln_reg_614_pp0_iter17_reg; + lshr_ln_reg_614_pp0_iter19_reg <= lshr_ln_reg_614_pp0_iter18_reg; + lshr_ln_reg_614_pp0_iter20_reg <= lshr_ln_reg_614_pp0_iter19_reg; + lshr_ln_reg_614_pp0_iter2_reg <= lshr_ln_reg_614_pp0_iter1_reg; + lshr_ln_reg_614_pp0_iter3_reg <= lshr_ln_reg_614_pp0_iter2_reg; + lshr_ln_reg_614_pp0_iter4_reg <= lshr_ln_reg_614_pp0_iter3_reg; + lshr_ln_reg_614_pp0_iter5_reg <= lshr_ln_reg_614_pp0_iter4_reg; + lshr_ln_reg_614_pp0_iter6_reg <= lshr_ln_reg_614_pp0_iter5_reg; + lshr_ln_reg_614_pp0_iter7_reg <= lshr_ln_reg_614_pp0_iter6_reg; + lshr_ln_reg_614_pp0_iter8_reg <= lshr_ln_reg_614_pp0_iter7_reg; + lshr_ln_reg_614_pp0_iter9_reg <= lshr_ln_reg_614_pp0_iter8_reg; + normalized_reg_665 <= grp_fu_231_p2; + running_sums_3_addr_reg_597_pp0_iter2_reg <= running_sums_3_addr_reg_597_pp0_iter1_reg; + running_sums_3_addr_reg_597_pp0_iter3_reg <= running_sums_3_addr_reg_597_pp0_iter2_reg; + running_sums_3_addr_reg_597_pp0_iter4_reg <= running_sums_3_addr_reg_597_pp0_iter3_reg; + running_sums_3_addr_reg_597_pp0_iter5_reg <= running_sums_3_addr_reg_597_pp0_iter4_reg; + running_sums_3_addr_reg_597_pp0_iter6_reg <= running_sums_3_addr_reg_597_pp0_iter5_reg; + sub_i_i_i_reg_655 <= grp_fu_227_p2; + sum_reg_634 <= grp_fu_219_p2; + tmp_104_i_i_reg_645 <= {{l2_adjustments_q0[31:16]}}; + tmp_104_i_i_reg_645_pp0_iter10_reg <= tmp_104_i_i_reg_645_pp0_iter9_reg; + tmp_104_i_i_reg_645_pp0_iter11_reg <= tmp_104_i_i_reg_645_pp0_iter10_reg; + tmp_104_i_i_reg_645_pp0_iter8_reg <= tmp_104_i_i_reg_645; + tmp_104_i_i_reg_645_pp0_iter9_reg <= tmp_104_i_i_reg_645_pp0_iter8_reg; + tmp_105_i_i_reg_650 <= {{l2_adjustments_q0[47:32]}}; + tmp_105_i_i_reg_650_pp0_iter10_reg <= tmp_105_i_i_reg_650_pp0_iter9_reg; + tmp_105_i_i_reg_650_pp0_iter11_reg <= tmp_105_i_i_reg_650_pp0_iter10_reg; + tmp_105_i_i_reg_650_pp0_iter12_reg <= tmp_105_i_i_reg_650_pp0_iter11_reg; + tmp_105_i_i_reg_650_pp0_iter13_reg <= tmp_105_i_i_reg_650_pp0_iter12_reg; + tmp_105_i_i_reg_650_pp0_iter14_reg <= tmp_105_i_i_reg_650_pp0_iter13_reg; + tmp_105_i_i_reg_650_pp0_iter15_reg <= tmp_105_i_i_reg_650_pp0_iter14_reg; + tmp_105_i_i_reg_650_pp0_iter8_reg <= tmp_105_i_i_reg_650; + tmp_105_i_i_reg_650_pp0_iter9_reg <= tmp_105_i_i_reg_650_pp0_iter8_reg; + trunc_ln99_reg_603_pp0_iter10_reg <= trunc_ln99_reg_603_pp0_iter9_reg; + trunc_ln99_reg_603_pp0_iter11_reg <= trunc_ln99_reg_603_pp0_iter10_reg; + trunc_ln99_reg_603_pp0_iter12_reg <= trunc_ln99_reg_603_pp0_iter11_reg; + trunc_ln99_reg_603_pp0_iter13_reg <= trunc_ln99_reg_603_pp0_iter12_reg; + trunc_ln99_reg_603_pp0_iter14_reg <= trunc_ln99_reg_603_pp0_iter13_reg; + trunc_ln99_reg_603_pp0_iter15_reg <= trunc_ln99_reg_603_pp0_iter14_reg; + trunc_ln99_reg_603_pp0_iter16_reg <= trunc_ln99_reg_603_pp0_iter15_reg; + trunc_ln99_reg_603_pp0_iter17_reg <= trunc_ln99_reg_603_pp0_iter16_reg; + trunc_ln99_reg_603_pp0_iter18_reg <= trunc_ln99_reg_603_pp0_iter17_reg; + trunc_ln99_reg_603_pp0_iter19_reg <= trunc_ln99_reg_603_pp0_iter18_reg; + trunc_ln99_reg_603_pp0_iter20_reg <= trunc_ln99_reg_603_pp0_iter19_reg; + trunc_ln99_reg_603_pp0_iter2_reg <= trunc_ln99_reg_603_pp0_iter1_reg; + trunc_ln99_reg_603_pp0_iter3_reg <= trunc_ln99_reg_603_pp0_iter2_reg; + trunc_ln99_reg_603_pp0_iter4_reg <= trunc_ln99_reg_603_pp0_iter3_reg; + trunc_ln99_reg_603_pp0_iter5_reg <= trunc_ln99_reg_603_pp0_iter4_reg; + trunc_ln99_reg_603_pp0_iter6_reg <= trunc_ln99_reg_603_pp0_iter5_reg; + trunc_ln99_reg_603_pp0_iter7_reg <= trunc_ln99_reg_603_pp0_iter6_reg; + trunc_ln99_reg_603_pp0_iter8_reg <= trunc_ln99_reg_603_pp0_iter7_reg; + trunc_ln99_reg_603_pp0_iter9_reg <= trunc_ln99_reg_603_pp0_iter8_reg; + zext_ln86_reg_587_pp0_iter2_reg[6 : 0] <= zext_ln86_reg_587_pp0_iter1_reg[6 : 0]; + zext_ln86_reg_587_pp0_iter3_reg[6 : 0] <= zext_ln86_reg_587_pp0_iter2_reg[6 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + and_ln103_reg_610_pp0_iter1_reg <= and_ln103_reg_610; + lshr_ln_reg_614_pp0_iter1_reg <= lshr_ln_reg_614; + running_sums_3_addr_reg_597_pp0_iter1_reg <= running_sums_3_addr_reg_597; + trunc_ln99_reg_603_pp0_iter1_reg <= trunc_ln99_reg_603; + val_reg_619 <= l2_partial_sums_q0; + zext_ln86_reg_587_pp0_iter1_reg[6 : 0] <= zext_ln86_reg_587[6 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((1'd1 == and_ln103_fu_307_p2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_285_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + lshr_ln_reg_614 <= {{ochan_reg_208[5:2]}}; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + quad_3_36_fu_118 <= quad_3_57_fu_467_p3; + quad_3_39_fu_114 <= quad_3_58_fu_475_p3; + quad_3_40_fu_122 <= quad_3_55_fu_451_p3; + quad_3_41_fu_126 <= quad_3_52_fu_427_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_3_load_reg_624 <= running_sums_3_q1; + end +end + +always @ (*) begin + if ((icmp_ln86_fu_285_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter6 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter5 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter4 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + l2_adjustments_ce0 = 1'b1; + end else begin + l2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_partial_sums_ce0 = 1'b1; + end else begin + l2_partial_sums_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter22 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter21 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (1'd1 == and_ln103_reg_610_pp0_iter20_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_3_ce0 = 1'b1; + end else begin + running_sums_3_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_3_ce1 = 1'b1; + end else begin + running_sums_3_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_3_we0 = 1'b1; + end else begin + running_sums_3_we0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write4_blk_n = write4_empty_n; + end else begin + write4_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write4_read = 1'b1; + end else begin + write4_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln86_fu_285_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((ap_enable_reg_pp0_iter22 == 1'b1) & (ap_enable_reg_pp0_iter21 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln86_fu_285_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter22 == 1'b1) & (ap_enable_reg_pp0_iter21 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_state25; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state25 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln109_fu_273_p2 = ((sub_ln109_cast_fu_265_p1) + (zext_ln109_8_fu_269_p1)); + +assign add_ln86_fu_279_p2 = (ochan_reg_208 + 7'd1); + +assign and_ln103_fu_307_p2 = (write4_read_reg_567 & icmp_ln103_fu_301_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state25 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln109_10_fu_518_p1 = quad_3_57_fu_467_p3; + +assign bitcast_ln109_11_fu_522_p1 = quad_3_55_fu_451_p3; + +assign bitcast_ln109_12_fu_526_p1 = quad_3_52_fu_427_p3; + +assign bitcast_ln109_fu_514_p1 = quad_3_58_fu_475_p3; + +assign data_V_fu_378_p1 = biased_reg_675; + +assign grp_fu_223_p1 = tmp_105_i_i_reg_650_pp0_iter15_reg; + +assign grp_fu_227_p1 = trunc_ln95_fu_329_p1; + +assign grp_fu_231_p1 = tmp_104_i_i_reg_645_pp0_iter11_reg; + +assign icmp_ln103_fu_301_p2 = ((trunc_ln99_fu_297_p1 == 2'd3) ? 1'b1 : 1'b0); + +assign icmp_ln86_fu_285_p2 = ((ochan_reg_208 == 7'd64) ? 1'b1 : 1'b0); + +assign icmp_ln99_7_fu_409_p2 = ((trunc_ln99_reg_603_pp0_iter20_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln99_8_fu_422_p2 = ((trunc_ln99_reg_603_pp0_iter20_reg == 2'd0) ? 1'b1 : 1'b0); + +assign icmp_ln99_fu_396_p2 = ((trunc_ln99_reg_603_pp0_iter20_reg == 2'd2) ? 1'b1 : 1'b0); + +assign l2_adjustments_address0 = zext_ln86_reg_587_pp0_iter3_reg; + +assign l2_partial_sums_address0 = zext_ln86_fu_291_p1; + +assign out_data_address1 = sext_ln109_fu_509_p1; + +assign out_data_d1 = {{{{bitcast_ln109_12_fu_526_p1}, {bitcast_ln109_11_fu_522_p1}}, {bitcast_ln109_10_fu_518_p1}}, {bitcast_ln109_fu_514_p1}}; + +assign p_Result_s_fu_381_p3 = data_V_fu_378_p1[32'd15]; + +assign quad_0_fu_389_p3 = ((p_Result_s_fu_381_p3[0:0] == 1'b1) ? 16'd0 : biased_reg_675); + +assign quad_3_51_fu_414_p3 = ((icmp_ln99_7_fu_409_p2[0:0] == 1'b1) ? quad_3_41_fu_126 : quad_3_fu_401_p3); + +assign quad_3_52_fu_427_p3 = ((icmp_ln99_8_fu_422_p2[0:0] == 1'b1) ? quad_3_41_fu_126 : quad_3_51_fu_414_p3); + +assign quad_3_53_fu_435_p3 = ((icmp_ln99_fu_396_p2[0:0] == 1'b1) ? quad_0_fu_389_p3 : quad_3_40_fu_122); + +assign quad_3_54_fu_443_p3 = ((icmp_ln99_7_fu_409_p2[0:0] == 1'b1) ? quad_3_40_fu_122 : quad_3_53_fu_435_p3); + +assign quad_3_55_fu_451_p3 = ((icmp_ln99_8_fu_422_p2[0:0] == 1'b1) ? quad_3_40_fu_122 : quad_3_54_fu_443_p3); + +assign quad_3_56_fu_459_p3 = ((icmp_ln99_7_fu_409_p2[0:0] == 1'b1) ? quad_0_fu_389_p3 : quad_3_36_fu_118); + +assign quad_3_57_fu_467_p3 = ((icmp_ln99_8_fu_422_p2[0:0] == 1'b1) ? quad_3_36_fu_118 : quad_3_56_fu_459_p3); + +assign quad_3_58_fu_475_p3 = ((icmp_ln99_8_fu_422_p2[0:0] == 1'b1) ? quad_0_fu_389_p3 : quad_3_39_fu_114); + +assign quad_3_fu_401_p3 = ((icmp_ln99_fu_396_p2[0:0] == 1'b1) ? quad_3_41_fu_126 : quad_0_fu_389_p3); + +assign running_sums_3_address1 = zext_ln86_fu_291_p1; + +assign running_sums_3_d0 = ((write4_read_reg_567[0:0] == 1'b1) ? 16'd0 : sum_reg_634); + +assign sext_ln109_fu_509_p1 = (tmp_74_fu_503_p3); + +assign sub_ln109_cast_fu_265_p1 = (sub_ln109_fu_259_p2); + +assign sub_ln109_fu_259_p2 = (zext_ln109_fu_243_p1 - zext_ln109_7_fu_255_p1); + +assign tmp_74_fu_503_p3 = {{add_ln109_reg_573}, {lshr_ln_reg_614_pp0_iter20_reg}}; + +assign tmp_fu_235_p3 = {{indices_01_dout}, {4'd0}}; + +assign tmp_s_fu_247_p3 = {{indices_01_dout}, {1'd0}}; + +assign trunc_ln95_fu_329_p1 = l2_adjustments_q0[15:0]; + +assign trunc_ln99_fu_297_p1 = ochan_reg_208[1:0]; + +assign zext_ln109_7_fu_255_p1 = tmp_s_fu_247_p3; + +assign zext_ln109_8_fu_269_p1 = indices_12_dout; + +assign zext_ln109_fu_243_p1 = tmp_fu_235_p3; + +assign zext_ln86_fu_291_p1 = ochan_reg_208; + +always @ (posedge ap_clk) begin + zext_ln86_reg_587[63:7] <= 57'b000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_587_pp0_iter1_reg[63:7] <= 57'b000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_587_pp0_iter2_reg[63:7] <= 57'b000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_587_pp0_iter3_reg[63:7] <= 57'b000000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf10_l2_writeOutputs_165 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf10_readFilters68 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_we0, + weight_vecs_0_d0, + weight_vecs_0_address1, + weight_vecs_0_ce1, + weight_vecs_0_we1, + weight_vecs_0_d1 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_pp0_stage0 = 4'd2; +parameter ap_ST_fsm_pp0_stage1 = 4'd4; +parameter ap_ST_fsm_state7 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [16:0] filter_data_address0; +output filter_data_ce0; +input [63:0] filter_data_q0; +input [8:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [9:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +output weight_vecs_0_we0; +output [15:0] weight_vecs_0_d0; +output [9:0] weight_vecs_0_address1; +output weight_vecs_0_ce1; +output weight_vecs_0_we1; +output [15:0] weight_vecs_0_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg indices_23_read; +reg[9:0] weight_vecs_0_address0; +reg weight_vecs_0_ce0; +reg weight_vecs_0_we0; +reg[15:0] weight_vecs_0_d0; +reg[9:0] weight_vecs_0_address1; +reg weight_vecs_0_ce1; +reg weight_vecs_0_we1; +reg[15:0] weight_vecs_0_d1; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [7:0] indvar_flatten13_reg_174; +reg [1:0] ii_reg_185; +reg [6:0] indvar_flatten_reg_196; +reg [1:0] jj_reg_207; +reg [6:0] kk_0_i_i_reg_218; +wire [12:0] sext_ln47_fu_251_p1; +reg [12:0] sext_ln47_reg_583; +wire [7:0] add_ln47_8_fu_255_p2; +reg [7:0] add_ln47_8_reg_588; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state4_pp0_stage0_iter1; +wire ap_block_state6_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln47_fu_261_p2; +reg [0:0] icmp_ln47_reg_593; +reg [0:0] icmp_ln47_reg_593_pp0_iter1_reg; +wire [0:0] icmp_ln48_fu_273_p2; +reg [0:0] icmp_ln48_reg_597; +wire [1:0] select_ln47_8_fu_287_p3; +reg [1:0] select_ln47_8_reg_602; +wire [6:0] select_ln48_fu_356_p3; +reg [6:0] select_ln48_reg_609; +wire [1:0] select_ln48_15_fu_364_p3; +reg [1:0] select_ln48_15_reg_615; +wire [5:0] empty_149_fu_382_p1; +reg [5:0] empty_149_reg_621; +reg [5:0] empty_149_reg_621_pp0_iter1_reg; +wire [6:0] add_ln48_8_fu_405_p2; +reg [6:0] add_ln48_8_reg_633; +wire [6:0] add_ln49_fu_411_p2; +reg [6:0] add_ln49_reg_638; +wire ap_CS_fsm_pp0_stage1; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state5_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +wire [6:0] select_ln48_16_fu_416_p3; +reg [6:0] select_ln48_16_reg_643; +wire [5:0] add_ln55_29_fu_449_p2; +reg [5:0] add_ln55_29_reg_648; +wire [9:0] add_ln55_30_fu_470_p2; +reg [9:0] add_ln55_30_reg_655; +reg [15:0] tmp_102_i_i_reg_660; +reg [15:0] tmp_103_i_i_reg_665; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +wire ap_block_pp0_stage1_subdone; +reg ap_enable_reg_pp0_iter2; +reg [7:0] ap_phi_mux_indvar_flatten13_phi_fu_178_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_189_p4; +reg [6:0] ap_phi_mux_indvar_flatten_phi_fu_200_p4; +reg [1:0] ap_phi_mux_jj_phi_fu_211_p4; +reg [6:0] ap_phi_mux_kk_0_i_i_phi_fu_222_p4; +wire [63:0] tmp_19_fu_396_p3; +wire [63:0] zext_ln55_75_fu_476_p1; +wire ap_block_pp0_stage1; +wire [63:0] sext_ln55_7_fu_501_p1; +wire [63:0] sext_ln55_8_fu_553_p1; +wire [63:0] sext_ln55_9_fu_574_p1; +wire [15:0] bitcast_ln55_fu_484_p1; +wire [15:0] bitcast_ln55_4_fu_516_p1; +wire [15:0] bitcast_ln55_5_fu_558_p1; +wire [15:0] bitcast_ln55_6_fu_579_p1; +wire [10:0] tmp_fu_233_p3; +wire [11:0] zext_ln55_68_fu_241_p1; +wire [11:0] zext_ln55_fu_229_p1; +wire [11:0] sub_ln55_fu_245_p2; +wire [1:0] add_ln47_fu_267_p2; +wire [12:0] zext_ln55_70_fu_295_p1; +wire [12:0] add_ln55_fu_299_p2; +wire [14:0] tmp_69_fu_308_p3; +wire [59:0] sext_ln55_6_fu_316_p1; +wire [59:0] sext_ln55_fu_304_p1; +wire [0:0] icmp_ln49_fu_332_p2; +wire [0:0] xor_ln47_fu_326_p2; +wire [1:0] select_ln47_fu_279_p3; +wire [0:0] and_ln47_fu_338_p2; +wire [0:0] or_ln48_fu_350_p2; +wire [1:0] add_ln48_fu_344_p2; +wire [59:0] sub_ln55_17_fu_320_p2; +wire [59:0] zext_ln55_73_fu_372_p1; +wire [59:0] add_ln55_28_fu_376_p2; +wire [3:0] lshr_ln_fu_386_p4; +wire [3:0] tmp_s_fu_425_p3; +wire [4:0] zext_ln55_71_fu_432_p1; +wire [4:0] zext_ln55_69_fu_422_p1; +wire [4:0] sub_ln55_18_fu_436_p2; +wire [5:0] sext_ln48_fu_442_p1; +wire [5:0] zext_ln55_72_fu_446_p1; +wire [3:0] trunc_ln55_fu_455_p1; +wire [9:0] tmp_191_cast_fu_459_p3; +wire [9:0] zext_ln55_74_fu_467_p1; +wire [15:0] trunc_ln55_5_fu_480_p1; +wire [5:0] or_ln49_fu_489_p2; +wire [11:0] tmp_70_fu_494_p3; +wire [15:0] tmp_101_i_i_fu_506_p4; +wire [5:0] or_ln49_3_fu_541_p2; +wire [11:0] tmp_71_fu_546_p3; +wire [5:0] or_ln49_4_fu_562_p2; +wire [11:0] tmp_72_fu_567_p3; +wire ap_CS_fsm_state7; +reg [3:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ii_reg_185 <= select_ln47_8_reg_602; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_185 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + indvar_flatten13_reg_174 <= add_ln47_8_reg_588; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_174 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + indvar_flatten_reg_196 <= select_ln48_16_reg_643; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_196 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_207 <= select_ln48_15_reg_615; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_207 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_i_i_reg_218 <= add_ln49_reg_638; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_0_i_i_reg_218 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln47_8_reg_588 <= add_ln47_8_fu_255_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_261_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln48_8_reg_633 <= add_ln48_8_fu_405_p2; + empty_149_reg_621 <= empty_149_fu_382_p1; + icmp_ln48_reg_597 <= icmp_ln48_fu_273_p2; + select_ln48_reg_609 <= select_ln48_fu_356_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + add_ln49_reg_638 <= add_ln49_fu_411_p2; + select_ln48_16_reg_643 <= select_ln48_16_fu_416_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln55_29_reg_648 <= add_ln55_29_fu_449_p2; + add_ln55_30_reg_655 <= add_ln55_30_fu_470_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + empty_149_reg_621_pp0_iter1_reg <= empty_149_reg_621; + icmp_ln47_reg_593 <= icmp_ln47_fu_261_p2; + icmp_ln47_reg_593_pp0_iter1_reg <= icmp_ln47_reg_593; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_261_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln47_8_reg_602 <= select_ln47_8_fu_287_p3; + select_ln48_15_reg_615 <= select_ln48_15_fu_364_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sext_ln47_reg_583 <= sext_ln47_fu_251_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + tmp_102_i_i_reg_660 <= {{filter_data_q0[47:32]}}; + tmp_103_i_i_reg_665 <= {{filter_data_q0[63:48]}}; + end +end + +always @ (*) begin + if ((icmp_ln47_fu_261_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_189_p4 = select_ln47_8_reg_602; + end else begin + ap_phi_mux_ii_phi_fu_189_p4 = ii_reg_185; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_indvar_flatten13_phi_fu_178_p4 = add_ln47_8_reg_588; + end else begin + ap_phi_mux_indvar_flatten13_phi_fu_178_p4 = indvar_flatten13_reg_174; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_indvar_flatten_phi_fu_200_p4 = select_ln48_16_reg_643; + end else begin + ap_phi_mux_indvar_flatten_phi_fu_200_p4 = indvar_flatten_reg_196; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_211_p4 = select_ln48_15_reg_615; + end else begin + ap_phi_mux_jj_phi_fu_211_p4 = jj_reg_207; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_i_i_phi_fu_222_p4 = add_ln49_reg_638; + end else begin + ap_phi_mux_kk_0_i_i_phi_fu_222_p4 = kk_0_i_i_reg_218; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + weight_vecs_0_address0 = sext_ln55_9_fu_574_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_address0 = sext_ln55_7_fu_501_p1; + end else begin + weight_vecs_0_address0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + weight_vecs_0_address1 = sext_ln55_8_fu_553_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_address1 = zext_ln55_75_fu_476_p1; + end else begin + weight_vecs_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + weight_vecs_0_ce1 = 1'b1; + end else begin + weight_vecs_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + weight_vecs_0_d0 = bitcast_ln55_6_fu_579_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_d0 = bitcast_ln55_4_fu_516_p1; + end else begin + weight_vecs_0_d0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + weight_vecs_0_d1 = bitcast_ln55_5_fu_558_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_d1 = bitcast_ln55_fu_484_p1; + end else begin + weight_vecs_0_d1 = 'bx; + end +end + +always @ (*) begin + if ((((icmp_ln47_reg_593_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((icmp_ln47_reg_593_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + weight_vecs_0_we0 = 1'b1; + end else begin + weight_vecs_0_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((icmp_ln47_reg_593_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((icmp_ln47_reg_593_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + weight_vecs_0_we1 = 1'b1; + end else begin + weight_vecs_0_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln47_fu_261_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if ((((icmp_ln47_fu_261_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln47_8_fu_255_p2 = (ap_phi_mux_indvar_flatten13_phi_fu_178_p4 + 8'd1); + +assign add_ln47_fu_267_p2 = (ap_phi_mux_ii_phi_fu_189_p4 + 2'd1); + +assign add_ln48_8_fu_405_p2 = (ap_phi_mux_indvar_flatten_phi_fu_200_p4 + 7'd1); + +assign add_ln48_fu_344_p2 = (select_ln47_fu_279_p3 + 2'd1); + +assign add_ln49_fu_411_p2 = (select_ln48_reg_609 + 7'd4); + +assign add_ln55_28_fu_376_p2 = (sub_ln55_17_fu_320_p2 + zext_ln55_73_fu_372_p1); + +assign add_ln55_29_fu_449_p2 = ((sext_ln48_fu_442_p1) + (zext_ln55_72_fu_446_p1)); + +assign add_ln55_30_fu_470_p2 = (tmp_191_cast_fu_459_p3 + zext_ln55_74_fu_467_p1); + +assign add_ln55_fu_299_p2 = ((sext_ln47_reg_583) + (zext_ln55_70_fu_295_p1)); + +assign and_ln47_fu_338_p2 = (xor_ln47_fu_326_p2 & icmp_ln49_fu_332_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd3]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln55_4_fu_516_p1 = tmp_101_i_i_fu_506_p4; + +assign bitcast_ln55_5_fu_558_p1 = tmp_102_i_i_reg_660; + +assign bitcast_ln55_6_fu_579_p1 = tmp_103_i_i_reg_665; + +assign bitcast_ln55_fu_484_p1 = trunc_ln55_5_fu_480_p1; + +assign empty_149_fu_382_p1 = select_ln48_fu_356_p3[5:0]; + +assign filter_data_address0 = tmp_19_fu_396_p3; + +assign icmp_ln47_fu_261_p2 = ((ap_phi_mux_indvar_flatten13_phi_fu_178_p4 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln48_fu_273_p2 = ((ap_phi_mux_indvar_flatten_phi_fu_200_p4 == 7'd48) ? 1'b1 : 1'b0); + +assign icmp_ln49_fu_332_p2 = ((ap_phi_mux_kk_0_i_i_phi_fu_222_p4 == 7'd64) ? 1'b1 : 1'b0); + +assign lshr_ln_fu_386_p4 = {{select_ln48_fu_356_p3[5:2]}}; + +assign or_ln48_fu_350_p2 = (icmp_ln48_fu_273_p2 | and_ln47_fu_338_p2); + +assign or_ln49_3_fu_541_p2 = (empty_149_reg_621_pp0_iter1_reg | 6'd2); + +assign or_ln49_4_fu_562_p2 = (empty_149_reg_621_pp0_iter1_reg | 6'd3); + +assign or_ln49_fu_489_p2 = (empty_149_reg_621_pp0_iter1_reg | 6'd1); + +assign select_ln47_8_fu_287_p3 = ((icmp_ln48_fu_273_p2[0:0] == 1'b1) ? add_ln47_fu_267_p2 : ap_phi_mux_ii_phi_fu_189_p4); + +assign select_ln47_fu_279_p3 = ((icmp_ln48_fu_273_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_211_p4); + +assign select_ln48_15_fu_364_p3 = ((and_ln47_fu_338_p2[0:0] == 1'b1) ? add_ln48_fu_344_p2 : select_ln47_fu_279_p3); + +assign select_ln48_16_fu_416_p3 = ((icmp_ln48_reg_597[0:0] == 1'b1) ? 7'd1 : add_ln48_8_reg_633); + +assign select_ln48_fu_356_p3 = ((or_ln48_fu_350_p2[0:0] == 1'b1) ? 7'd0 : ap_phi_mux_kk_0_i_i_phi_fu_222_p4); + +assign sext_ln47_fu_251_p1 = (sub_ln55_fu_245_p2); + +assign sext_ln48_fu_442_p1 = (sub_ln55_18_fu_436_p2); + +assign sext_ln55_6_fu_316_p1 = (tmp_69_fu_308_p3); + +assign sext_ln55_7_fu_501_p1 = (tmp_70_fu_494_p3); + +assign sext_ln55_8_fu_553_p1 = (tmp_71_fu_546_p3); + +assign sext_ln55_9_fu_574_p1 = (tmp_72_fu_567_p3); + +assign sext_ln55_fu_304_p1 = add_ln55_fu_299_p2; + +assign sub_ln55_17_fu_320_p2 = ((sext_ln55_6_fu_316_p1) - (sext_ln55_fu_304_p1)); + +assign sub_ln55_18_fu_436_p2 = (zext_ln55_71_fu_432_p1 - zext_ln55_69_fu_422_p1); + +assign sub_ln55_fu_245_p2 = (zext_ln55_68_fu_241_p1 - zext_ln55_fu_229_p1); + +assign tmp_101_i_i_fu_506_p4 = {{filter_data_q0[31:16]}}; + +assign tmp_191_cast_fu_459_p3 = {{trunc_ln55_fu_455_p1}, {6'd0}}; + +assign tmp_19_fu_396_p3 = {{add_ln55_28_fu_376_p2}, {lshr_ln_fu_386_p4}}; + +assign tmp_69_fu_308_p3 = {{add_ln55_fu_299_p2}, {2'd0}}; + +assign tmp_70_fu_494_p3 = {{add_ln55_29_reg_648}, {or_ln49_fu_489_p2}}; + +assign tmp_71_fu_546_p3 = {{add_ln55_29_reg_648}, {or_ln49_3_fu_541_p2}}; + +assign tmp_72_fu_567_p3 = {{add_ln55_29_reg_648}, {or_ln49_4_fu_562_p2}}; + +assign tmp_fu_233_p3 = {{indices_23_dout}, {2'd0}}; + +assign tmp_s_fu_425_p3 = {{select_ln47_8_reg_602}, {2'd0}}; + +assign trunc_ln55_5_fu_480_p1 = filter_data_q0[15:0]; + +assign trunc_ln55_fu_455_p1 = add_ln55_29_fu_449_p2[3:0]; + +assign xor_ln47_fu_326_p2 = (icmp_ln48_fu_273_p2 ^ 1'd1); + +assign zext_ln55_68_fu_241_p1 = tmp_fu_233_p3; + +assign zext_ln55_69_fu_422_p1 = select_ln47_8_reg_602; + +assign zext_ln55_70_fu_295_p1 = select_ln47_8_fu_287_p3; + +assign zext_ln55_71_fu_432_p1 = tmp_s_fu_425_p3; + +assign zext_ln55_72_fu_446_p1 = select_ln48_15_reg_615; + +assign zext_ln55_73_fu_372_p1 = select_ln48_15_fu_364_p3; + +assign zext_ln55_74_fu_467_p1 = select_ln48_reg_609; + +assign zext_ln55_75_fu_476_p1 = add_ln55_30_reg_655; + +assign zext_ln55_fu_229_p1 = indices_23_dout; + +endmodule //td_fused_top_tdf10_readFilters68 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf10_readInputs69 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_we0, + ifmap_vec_d0, + ifmap_vec_address1, + ifmap_vec_ce1, + ifmap_vec_we1, + ifmap_vec_d1, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 5'd1; +parameter ap_ST_fsm_state2 = 5'd2; +parameter ap_ST_fsm_pp0_stage0 = 5'd4; +parameter ap_ST_fsm_pp0_stage1 = 5'd8; +parameter ap_ST_fsm_state9 = 5'd16; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [11:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [9:0] ifmap_vec_address0; +output ifmap_vec_ce0; +output ifmap_vec_we0; +output [15:0] ifmap_vec_d0; +output [9:0] ifmap_vec_address1; +output ifmap_vec_ce1; +output ifmap_vec_we1; +output [15:0] ifmap_vec_d1; +output [3:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [7:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg[9:0] ifmap_vec_address0; +reg ifmap_vec_ce0; +reg ifmap_vec_we0; +reg[15:0] ifmap_vec_d0; +reg[9:0] ifmap_vec_address1; +reg ifmap_vec_ce1; +reg ifmap_vec_we1; +reg[15:0] ifmap_vec_d1; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [4:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [7:0] indvar_flatten47_reg_224; +reg [1:0] ii_reg_236; +reg [6:0] indvar_flatten_reg_248; +reg [1:0] jj_reg_259; +reg [6:0] kk_0_i_i_reg_271; +reg [15:0] indices_01_read_reg_960; +wire [3:0] trunc_ln250_fu_282_p1; +reg [3:0] trunc_ln250_reg_965; +reg [15:0] indices_12_read_reg_970; +wire [7:0] empty_fu_287_p1; +reg [7:0] empty_reg_975; +wire [17:0] p_cast_i_i_fu_304_p1; +reg [17:0] p_cast_i_i_reg_982; +wire ap_CS_fsm_state2; +wire [17:0] sext_ln22_fu_314_p1; +reg [17:0] sext_ln22_reg_988; +wire [3:0] p_cast_fu_318_p2; +reg [3:0] p_cast_reg_994; +wire [0:0] or_ln23_36_fu_337_p2; +reg [0:0] or_ln23_36_reg_1000; +wire [7:0] p_mid137_fu_343_p2; +reg [7:0] p_mid137_reg_1005; +wire [3:0] p_cast5_i_i_fu_361_p2; +reg [3:0] p_cast5_i_i_reg_1010; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state5_pp0_stage0_iter1; +wire ap_block_state7_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [0:0] is_padding_fu_401_p2; +reg [0:0] is_padding_reg_1016; +wire [0:0] icmp_ln19_fu_407_p2; +reg [0:0] icmp_ln19_reg_1023; +reg [0:0] icmp_ln19_reg_1023_pp0_iter1_reg; +reg [0:0] icmp_ln19_reg_1023_pp0_iter2_reg; +wire [1:0] add_ln19_fu_413_p2; +reg [1:0] add_ln19_reg_1027; +wire [0:0] icmp_ln20_fu_419_p2; +reg [0:0] icmp_ln20_reg_1033; +wire [1:0] select_ln19_fu_425_p3; +reg [1:0] select_ln19_reg_1045; +wire [0:0] or_ln23_38_fu_456_p2; +reg [0:0] or_ln23_38_reg_1050; +wire [1:0] add_ln20_fu_461_p2; +reg [1:0] add_ln20_reg_1057; +wire [0:0] or_ln23_40_fu_496_p2; +reg [0:0] or_ln23_40_reg_1063; +wire [6:0] add_ln20_8_fu_502_p2; +reg [6:0] add_ln20_8_reg_1070; +wire [7:0] add_ln19_8_fu_508_p2; +reg [7:0] add_ln19_8_reg_1075; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state4_pp0_stage1_iter0; +wire ap_block_state6_pp0_stage1_iter1; +wire ap_block_state8_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +wire [1:0] select_ln19_42_fu_546_p3; +reg [1:0] select_ln19_42_reg_1080; +wire [6:0] select_ln20_fu_620_p3; +reg [6:0] select_ln20_reg_1087; +wire [1:0] select_ln20_35_fu_628_p3; +reg [1:0] select_ln20_35_reg_1093; +wire [0:0] select_ln20_36_fu_637_p3; +reg [0:0] select_ln20_36_reg_1099; +reg [0:0] select_ln20_36_reg_1099_pp0_iter1_reg; +wire [5:0] empty_148_fu_733_p1; +reg [5:0] empty_148_reg_1107; +reg [5:0] empty_148_reg_1107_pp0_iter1_reg; +wire [6:0] select_ln20_39_fu_760_p3; +reg [6:0] select_ln20_39_reg_1119; +wire [6:0] add_ln25_fu_766_p2; +reg [6:0] add_ln25_reg_1124; +reg ap_enable_reg_pp0_iter1; +wire [5:0] add_ln33_fu_798_p2; +reg [5:0] add_ln33_reg_1129; +wire [9:0] add_ln33_8_fu_819_p2; +reg [9:0] add_ln33_8_reg_1136; +wire [15:0] select_ln33_32_fu_898_p3; +reg [15:0] select_ln33_32_reg_1141; +wire [15:0] select_ln33_33_fu_919_p3; +reg [15:0] select_ln33_33_reg_1146; +wire ap_block_pp0_stage1_subdone; +reg ap_condition_pp0_exit_iter0_state4; +reg ap_enable_reg_pp0_iter2; +reg [7:0] ap_phi_mux_indvar_flatten47_phi_fu_228_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_240_p4; +reg [6:0] ap_phi_mux_indvar_flatten_phi_fu_252_p4; +reg [1:0] ap_phi_mux_jj_phi_fu_263_p4; +reg [6:0] ap_phi_mux_kk_0_i_i_phi_fu_275_p4; +wire ap_block_pp0_stage1; +wire [63:0] sext_ln32_fu_755_p1; +wire [63:0] zext_ln33_33_fu_825_p1; +wire [63:0] sext_ln33_fu_857_p1; +wire [63:0] sext_ln33_13_fu_938_p1; +wire [63:0] sext_ln33_14_fu_955_p1; +reg ap_block_state1; +wire [15:0] select_ln33_fu_837_p3; +wire [15:0] select_ln33_31_fu_876_p3; +wire [16:0] zext_ln19_fu_295_p1; +wire [16:0] empty_143_fu_298_p2; +wire [16:0] j_cast_i_i_fu_292_p1; +wire [16:0] add_ln22_fu_308_p2; +wire [0:0] tmp_62_fu_323_p3; +wire [0:0] icmp_ln24_fu_331_p2; +wire [17:0] ii_cast_i_i_fu_348_p1; +wire [3:0] ii_cast_fu_352_p1; +wire [17:0] empty_144_fu_356_p2; +wire [17:0] zext_ln20_fu_372_p1; +wire [17:0] add_ln22_8_fu_376_p2; +wire [0:0] tmp_63_fu_381_p3; +wire [0:0] icmp_ln24_8_fu_389_p2; +wire [0:0] or_ln23_fu_395_p2; +wire [0:0] empty_145_fu_366_p2; +wire [17:0] ii_cast_i_i_mid1_fu_433_p1; +wire [17:0] p_mid111_fu_437_p2; +wire [0:0] p_mid113_fu_442_p2; +wire [17:0] zext_ln20_8_fu_467_p1; +wire [17:0] add_ln22_9_fu_471_p2; +wire [0:0] tmp_64_fu_476_p3; +wire [0:0] icmp_ln24_9_fu_484_p2; +wire [0:0] or_ln23_39_fu_490_p2; +wire [0:0] select_ln19_44_fu_448_p3; +wire [2:0] zext_ln22_fu_514_p1; +wire [2:0] tmp1_fu_524_p2; +wire [7:0] tmp1_cast_fu_530_p1; +wire [7:0] empty_146_fu_534_p2; +wire [3:0] ii_cast_mid1_fu_552_p1; +wire [3:0] p_cast5_i_i_mid1_fu_555_p2; +wire [3:0] row_coord_int_mid131_fu_571_p3; +wire [3:0] row_coord_int_fu_518_p3; +wire [7:0] col_coord_int_mid139_fu_578_p3; +wire [7:0] col_coord_int_fu_539_p3; +wire [0:0] icmp_ln25_fu_603_p2; +wire [0:0] xor_ln19_fu_598_p2; +wire [0:0] and_ln19_fu_609_p2; +wire [0:0] or_ln20_fu_615_p2; +wire [0:0] select_ln19_45_fu_566_p3; +wire [3:0] select_ln19_43_fu_560_p3; +wire [2:0] zext_ln22_8_fu_634_p1; +wire [2:0] tmp1_mid1_fu_651_p2; +wire [7:0] tmp1_cast_mid1_fu_657_p1; +wire [7:0] p_mid1_fu_661_p2; +wire [3:0] row_coord_int_mid1_fu_644_p3; +wire [3:0] select_ln19_46_fu_584_p3; +wire [3:0] select_ln20_37_fu_673_p3; +wire [7:0] tmp_s_fu_681_p3; +wire [4:0] tmp_18_fu_693_p3; +wire [8:0] zext_ln32_fu_689_p1; +wire [8:0] zext_ln32_36_fu_701_p1; +wire [8:0] sub_ln32_fu_705_p2; +wire [7:0] col_coord_int_mid1_fu_666_p3; +wire [7:0] select_ln19_47_fu_591_p3; +wire [7:0] select_ln20_38_fu_715_p3; +wire [9:0] sext_ln20_fu_711_p1; +wire [9:0] zext_ln32_37_fu_723_p1; +wire [9:0] add_ln32_fu_727_p2; +wire [3:0] lshr_ln_fu_737_p4; +wire [13:0] tmp_65_fu_747_p3; +wire [3:0] tmp_fu_774_p3; +wire [4:0] zext_ln33_30_fu_781_p1; +wire [4:0] zext_ln33_fu_771_p1; +wire [4:0] sub_ln33_fu_785_p2; +wire [5:0] sub_ln33_cast_fu_791_p1; +wire [5:0] zext_ln33_31_fu_795_p1; +wire [3:0] trunc_ln33_fu_804_p1; +wire [9:0] tmp_180_cast_fu_808_p3; +wire [9:0] zext_ln33_32_fu_816_p1; +wire [15:0] trunc_ln32_fu_829_p1; +wire [15:0] bitcast_ln32_fu_833_p1; +wire [5:0] or_ln25_fu_845_p2; +wire [11:0] tmp_66_fu_850_p3; +wire [15:0] tmp_98_i_i_fu_862_p4; +wire [15:0] bitcast_ln32_31_fu_872_p1; +wire [15:0] tmp_99_i_i_fu_884_p4; +wire [15:0] bitcast_ln32_32_fu_894_p1; +wire [15:0] tmp_100_i_i_fu_905_p4; +wire [15:0] bitcast_ln32_33_fu_915_p1; +wire [5:0] or_ln25_21_fu_926_p2; +wire [11:0] tmp_67_fu_931_p3; +wire [5:0] or_ln25_22_fu_943_p2; +wire [11:0] tmp_68_fu_948_p3; +wire ap_CS_fsm_state9; +reg [4:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 5'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state4)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state4); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_236 <= select_ln19_42_reg_1080; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ii_reg_236 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + indvar_flatten47_reg_224 <= add_ln19_8_reg_1075; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + indvar_flatten47_reg_224 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + indvar_flatten_reg_248 <= select_ln20_39_reg_1119; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + indvar_flatten_reg_248 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_259 <= select_ln20_35_reg_1093; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + jj_reg_259 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + kk_0_i_i_reg_271 <= add_ln25_reg_1124; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + kk_0_i_i_reg_271 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + add_ln19_8_reg_1075 <= add_ln19_8_fu_508_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_407_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln19_reg_1027 <= add_ln19_fu_413_p2; + add_ln20_8_reg_1070 <= add_ln20_8_fu_502_p2; + add_ln20_reg_1057 <= add_ln20_fu_461_p2; + icmp_ln20_reg_1033 <= icmp_ln20_fu_419_p2; + or_ln23_38_reg_1050 <= or_ln23_38_fu_456_p2; + or_ln23_40_reg_1063 <= or_ln23_40_fu_496_p2; + select_ln19_reg_1045 <= select_ln19_fu_425_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln25_reg_1124 <= add_ln25_fu_766_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1023_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + add_ln33_8_reg_1136 <= add_ln33_8_fu_819_p2; + add_ln33_reg_1129 <= add_ln33_fu_798_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + empty_148_reg_1107 <= empty_148_fu_733_p1; + select_ln20_36_reg_1099 <= select_ln20_36_fu_637_p3; + select_ln20_reg_1087 <= select_ln20_fu_620_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + empty_148_reg_1107_pp0_iter1_reg <= empty_148_reg_1107; + select_ln20_36_reg_1099_pp0_iter1_reg <= select_ln20_36_reg_1099; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + empty_reg_975 <= empty_fu_287_p1; + indices_01_read_reg_960 <= indices_01_dout; + indices_12_read_reg_970 <= indices_12_dout; + trunc_ln250_reg_965 <= trunc_ln250_fu_282_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln19_reg_1023 <= icmp_ln19_fu_407_p2; + icmp_ln19_reg_1023_pp0_iter1_reg <= icmp_ln19_reg_1023; + icmp_ln19_reg_1023_pp0_iter2_reg <= icmp_ln19_reg_1023_pp0_iter1_reg; + is_padding_reg_1016 <= is_padding_fu_401_p2; + p_cast5_i_i_reg_1010 <= p_cast5_i_i_fu_361_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + or_ln23_36_reg_1000 <= or_ln23_36_fu_337_p2; + p_cast_i_i_reg_982 <= p_cast_i_i_fu_304_p1; + p_cast_reg_994 <= p_cast_fu_318_p2; + p_mid137_reg_1005 <= p_mid137_fu_343_p2; + sext_ln22_reg_988 <= sext_ln22_fu_314_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + select_ln19_42_reg_1080 <= select_ln19_42_fu_546_p3; + select_ln20_35_reg_1093 <= select_ln20_35_fu_628_p3; + select_ln20_39_reg_1119 <= select_ln20_39_fu_760_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_1023_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + select_ln33_32_reg_1141 <= select_ln33_32_fu_898_p3; + select_ln33_33_reg_1146 <= select_ln33_33_fu_919_p3; + end +end + +always @ (*) begin + if ((icmp_ln19_reg_1023 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_240_p4 = select_ln19_42_reg_1080; + end else begin + ap_phi_mux_ii_phi_fu_240_p4 = ii_reg_236; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_indvar_flatten47_phi_fu_228_p4 = add_ln19_8_reg_1075; + end else begin + ap_phi_mux_indvar_flatten47_phi_fu_228_p4 = indvar_flatten47_reg_224; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_indvar_flatten_phi_fu_252_p4 = select_ln20_39_reg_1119; + end else begin + ap_phi_mux_indvar_flatten_phi_fu_252_p4 = indvar_flatten_reg_248; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_263_p4 = select_ln20_35_reg_1093; + end else begin + ap_phi_mux_jj_phi_fu_263_p4 = jj_reg_259; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1))) begin + ap_phi_mux_kk_0_i_i_phi_fu_275_p4 = add_ln25_reg_1124; + end else begin + ap_phi_mux_kk_0_i_i_phi_fu_275_p4 = kk_0_i_i_reg_271; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_address0 = sext_ln33_14_fu_955_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_address0 = sext_ln33_fu_857_p1; + end else begin + ifmap_vec_address0 = 'bx; + end + end else begin + ifmap_vec_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_address1 = sext_ln33_13_fu_938_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_address1 = zext_ln33_33_fu_825_p1; + end else begin + ifmap_vec_address1 = 'bx; + end + end else begin + ifmap_vec_address1 = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_ce1 = 1'b1; + end else begin + ifmap_vec_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_d0 = select_ln33_33_reg_1146; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_d0 = select_ln33_31_fu_876_p3; + end else begin + ifmap_vec_d0 = 'bx; + end + end else begin + ifmap_vec_d0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_d1 = select_ln33_32_reg_1141; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_d1 = select_ln33_fu_837_p3; + end else begin + ifmap_vec_d1 = 'bx; + end + end else begin + ifmap_vec_d1 = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1023_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_1023_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_we0 = 1'b1; + end else begin + ifmap_vec_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1023_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_1023_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_we1 = 1'b1; + end else begin + ifmap_vec_we1 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln19_reg_1023 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone)) & ~((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage1_subdone)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage1_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln19_reg_1023 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_state9; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln19_8_fu_508_p2 = (indvar_flatten47_reg_224 + 8'd1); + +assign add_ln19_fu_413_p2 = (ap_phi_mux_ii_phi_fu_240_p4 + 2'd1); + +assign add_ln20_8_fu_502_p2 = (ap_phi_mux_indvar_flatten_phi_fu_252_p4 + 7'd1); + +assign add_ln20_fu_461_p2 = (select_ln19_fu_425_p3 + 2'd1); + +assign add_ln22_8_fu_376_p2 = ((sext_ln22_reg_988) + (zext_ln20_fu_372_p1)); + +assign add_ln22_9_fu_471_p2 = ((sext_ln22_reg_988) + (zext_ln20_8_fu_467_p1)); + +assign add_ln22_fu_308_p2 = ((j_cast_i_i_fu_292_p1) + (17'd131071)); + +assign add_ln25_fu_766_p2 = (select_ln20_reg_1087 + 7'd4); + +assign add_ln32_fu_727_p2 = ((sext_ln20_fu_711_p1) + (zext_ln32_37_fu_723_p1)); + +assign add_ln33_8_fu_819_p2 = (tmp_180_cast_fu_808_p3 + zext_ln33_32_fu_816_p1); + +assign add_ln33_fu_798_p2 = ((sub_ln33_cast_fu_791_p1) + (zext_ln33_31_fu_795_p1)); + +assign and_ln19_fu_609_p2 = (xor_ln19_fu_598_p2 & icmp_ln25_fu_603_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd4]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln32_31_fu_872_p1 = tmp_98_i_i_fu_862_p4; + +assign bitcast_ln32_32_fu_894_p1 = tmp_99_i_i_fu_884_p4; + +assign bitcast_ln32_33_fu_915_p1 = tmp_100_i_i_fu_905_p4; + +assign bitcast_ln32_fu_833_p1 = trunc_ln32_fu_829_p1; + +assign col_coord_int_fu_539_p3 = ((is_padding_reg_1016[0:0] == 1'b1) ? 8'd0 : empty_146_fu_534_p2); + +assign col_coord_int_mid139_fu_578_p3 = ((or_ln23_38_reg_1050[0:0] == 1'b1) ? 8'd0 : p_mid137_reg_1005); + +assign col_coord_int_mid1_fu_666_p3 = ((or_ln23_40_reg_1063[0:0] == 1'b1) ? 8'd0 : p_mid1_fu_661_p2); + +assign empty_143_fu_298_p2 = ((zext_ln19_fu_295_p1) + (17'd131071)); + +assign empty_144_fu_356_p2 = ((p_cast_i_i_reg_982) + (ii_cast_i_i_fu_348_p1)); + +assign empty_145_fu_366_p2 = ((empty_144_fu_356_p2 > 18'd13) ? 1'b1 : 1'b0); + +assign empty_146_fu_534_p2 = ((tmp1_cast_fu_530_p1) + (empty_reg_975)); + +assign empty_148_fu_733_p1 = select_ln20_fu_620_p3[5:0]; + +assign empty_fu_287_p1 = indices_12_dout[7:0]; + +assign icmp_ln19_fu_407_p2 = ((ap_phi_mux_indvar_flatten47_phi_fu_228_p4 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_419_p2 = ((ap_phi_mux_indvar_flatten_phi_fu_252_p4 == 7'd48) ? 1'b1 : 1'b0); + +assign icmp_ln24_8_fu_389_p2 = (((add_ln22_8_fu_376_p2) > (18'd13)) ? 1'b1 : 1'b0); + +assign icmp_ln24_9_fu_484_p2 = (((add_ln22_9_fu_471_p2) > (18'd13)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_331_p2 = (((add_ln22_fu_308_p2) > (17'd13)) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_603_p2 = ((ap_phi_mux_kk_0_i_i_phi_fu_275_p4 == 7'd64) ? 1'b1 : 1'b0); + +assign ii_cast_fu_352_p1 = ap_phi_mux_ii_phi_fu_240_p4; + +assign ii_cast_i_i_fu_348_p1 = ap_phi_mux_ii_phi_fu_240_p4; + +assign ii_cast_i_i_mid1_fu_433_p1 = add_ln19_fu_413_p2; + +assign ii_cast_mid1_fu_552_p1 = add_ln19_reg_1027; + +assign in_data_address0 = sext_ln32_fu_755_p1; + +assign indices_01_out_din = indices_01_dout[3:0]; + +assign indices_12_out_din = indices_12_dout[7:0]; + +assign is_padding_fu_401_p2 = (or_ln23_fu_395_p2 | empty_145_fu_366_p2); + +assign j_cast_i_i_fu_292_p1 = indices_12_read_reg_970; + +assign lshr_ln_fu_737_p4 = {{select_ln20_fu_620_p3[5:2]}}; + +assign or_ln20_fu_615_p2 = (icmp_ln20_reg_1033 | and_ln19_fu_609_p2); + +assign or_ln23_36_fu_337_p2 = (tmp_62_fu_323_p3 | icmp_ln24_fu_331_p2); + +assign or_ln23_38_fu_456_p2 = (p_mid113_fu_442_p2 | or_ln23_36_reg_1000); + +assign or_ln23_39_fu_490_p2 = (tmp_64_fu_476_p3 | icmp_ln24_9_fu_484_p2); + +assign or_ln23_40_fu_496_p2 = (select_ln19_44_fu_448_p3 | or_ln23_39_fu_490_p2); + +assign or_ln23_fu_395_p2 = (tmp_63_fu_381_p3 | icmp_ln24_8_fu_389_p2); + +assign or_ln25_21_fu_926_p2 = (empty_148_reg_1107_pp0_iter1_reg | 6'd2); + +assign or_ln25_22_fu_943_p2 = (empty_148_reg_1107_pp0_iter1_reg | 6'd3); + +assign or_ln25_fu_845_p2 = (empty_148_reg_1107_pp0_iter1_reg | 6'd1); + +assign p_cast5_i_i_fu_361_p2 = (p_cast_reg_994 + ii_cast_fu_352_p1); + +assign p_cast5_i_i_mid1_fu_555_p2 = (p_cast_reg_994 + ii_cast_mid1_fu_552_p1); + +assign p_cast_fu_318_p2 = ((trunc_ln250_reg_965) + (4'd15)); + +assign p_cast_i_i_fu_304_p1 = (empty_143_fu_298_p2); + +assign p_mid111_fu_437_p2 = ((p_cast_i_i_reg_982) + (ii_cast_i_i_mid1_fu_433_p1)); + +assign p_mid113_fu_442_p2 = ((p_mid111_fu_437_p2 > 18'd13) ? 1'b1 : 1'b0); + +assign p_mid137_fu_343_p2 = ((empty_reg_975) + (8'd255)); + +assign p_mid1_fu_661_p2 = ((tmp1_cast_mid1_fu_657_p1) + (empty_reg_975)); + +assign row_coord_int_fu_518_p3 = ((is_padding_reg_1016[0:0] == 1'b1) ? 4'd0 : p_cast5_i_i_reg_1010); + +assign row_coord_int_mid131_fu_571_p3 = ((or_ln23_38_reg_1050[0:0] == 1'b1) ? 4'd0 : p_cast5_i_i_mid1_fu_555_p2); + +assign row_coord_int_mid1_fu_644_p3 = ((or_ln23_40_reg_1063[0:0] == 1'b1) ? 4'd0 : select_ln19_43_fu_560_p3); + +assign select_ln19_42_fu_546_p3 = ((icmp_ln20_reg_1033[0:0] == 1'b1) ? add_ln19_reg_1027 : ii_reg_236); + +assign select_ln19_43_fu_560_p3 = ((icmp_ln20_reg_1033[0:0] == 1'b1) ? p_cast5_i_i_mid1_fu_555_p2 : p_cast5_i_i_reg_1010); + +assign select_ln19_44_fu_448_p3 = ((icmp_ln20_fu_419_p2[0:0] == 1'b1) ? p_mid113_fu_442_p2 : empty_145_fu_366_p2); + +assign select_ln19_45_fu_566_p3 = ((icmp_ln20_reg_1033[0:0] == 1'b1) ? or_ln23_38_reg_1050 : is_padding_reg_1016); + +assign select_ln19_46_fu_584_p3 = ((icmp_ln20_reg_1033[0:0] == 1'b1) ? row_coord_int_mid131_fu_571_p3 : row_coord_int_fu_518_p3); + +assign select_ln19_47_fu_591_p3 = ((icmp_ln20_reg_1033[0:0] == 1'b1) ? col_coord_int_mid139_fu_578_p3 : col_coord_int_fu_539_p3); + +assign select_ln19_fu_425_p3 = ((icmp_ln20_fu_419_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_263_p4); + +assign select_ln20_35_fu_628_p3 = ((and_ln19_fu_609_p2[0:0] == 1'b1) ? add_ln20_reg_1057 : select_ln19_reg_1045); + +assign select_ln20_36_fu_637_p3 = ((and_ln19_fu_609_p2[0:0] == 1'b1) ? or_ln23_40_reg_1063 : select_ln19_45_fu_566_p3); + +assign select_ln20_37_fu_673_p3 = ((and_ln19_fu_609_p2[0:0] == 1'b1) ? row_coord_int_mid1_fu_644_p3 : select_ln19_46_fu_584_p3); + +assign select_ln20_38_fu_715_p3 = ((and_ln19_fu_609_p2[0:0] == 1'b1) ? col_coord_int_mid1_fu_666_p3 : select_ln19_47_fu_591_p3); + +assign select_ln20_39_fu_760_p3 = ((icmp_ln20_reg_1033[0:0] == 1'b1) ? 7'd1 : add_ln20_8_reg_1070); + +assign select_ln20_fu_620_p3 = ((or_ln20_fu_615_p2[0:0] == 1'b1) ? 7'd0 : ap_phi_mux_kk_0_i_i_phi_fu_275_p4); + +assign select_ln33_31_fu_876_p3 = ((select_ln20_36_reg_1099_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_31_fu_872_p1); + +assign select_ln33_32_fu_898_p3 = ((select_ln20_36_reg_1099_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_32_fu_894_p1); + +assign select_ln33_33_fu_919_p3 = ((select_ln20_36_reg_1099_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_33_fu_915_p1); + +assign select_ln33_fu_837_p3 = ((select_ln20_36_reg_1099_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_fu_833_p1); + +assign sext_ln20_fu_711_p1 = (sub_ln32_fu_705_p2); + +assign sext_ln22_fu_314_p1 = add_ln22_fu_308_p2; + +assign sext_ln32_fu_755_p1 = (tmp_65_fu_747_p3); + +assign sext_ln33_13_fu_938_p1 = (tmp_67_fu_931_p3); + +assign sext_ln33_14_fu_955_p1 = (tmp_68_fu_948_p3); + +assign sext_ln33_fu_857_p1 = (tmp_66_fu_850_p3); + +assign sub_ln32_fu_705_p2 = (zext_ln32_fu_689_p1 - zext_ln32_36_fu_701_p1); + +assign sub_ln33_cast_fu_791_p1 = (sub_ln33_fu_785_p2); + +assign sub_ln33_fu_785_p2 = (zext_ln33_30_fu_781_p1 - zext_ln33_fu_771_p1); + +assign tmp1_cast_fu_530_p1 = (tmp1_fu_524_p2); + +assign tmp1_cast_mid1_fu_657_p1 = (tmp1_mid1_fu_651_p2); + +assign tmp1_fu_524_p2 = ((zext_ln22_fu_514_p1) + (3'd7)); + +assign tmp1_mid1_fu_651_p2 = ((zext_ln22_8_fu_634_p1) + (3'd7)); + +assign tmp_100_i_i_fu_905_p4 = {{in_data_q0[63:48]}}; + +assign tmp_180_cast_fu_808_p3 = {{trunc_ln33_fu_804_p1}, {6'd0}}; + +assign tmp_18_fu_693_p3 = {{select_ln20_37_fu_673_p3}, {1'd0}}; + +assign tmp_62_fu_323_p3 = add_ln22_fu_308_p2[32'd16]; + +assign tmp_63_fu_381_p3 = add_ln22_8_fu_376_p2[32'd17]; + +assign tmp_64_fu_476_p3 = add_ln22_9_fu_471_p2[32'd17]; + +assign tmp_65_fu_747_p3 = {{add_ln32_fu_727_p2}, {lshr_ln_fu_737_p4}}; + +assign tmp_66_fu_850_p3 = {{add_ln33_reg_1129}, {or_ln25_fu_845_p2}}; + +assign tmp_67_fu_931_p3 = {{add_ln33_reg_1129}, {or_ln25_21_fu_926_p2}}; + +assign tmp_68_fu_948_p3 = {{add_ln33_reg_1129}, {or_ln25_22_fu_943_p2}}; + +assign tmp_98_i_i_fu_862_p4 = {{in_data_q0[31:16]}}; + +assign tmp_99_i_i_fu_884_p4 = {{in_data_q0[47:32]}}; + +assign tmp_fu_774_p3 = {{select_ln19_42_reg_1080}, {2'd0}}; + +assign tmp_s_fu_681_p3 = {{select_ln20_37_fu_673_p3}, {4'd0}}; + +assign trunc_ln250_fu_282_p1 = indices_01_dout[3:0]; + +assign trunc_ln32_fu_829_p1 = in_data_q0[15:0]; + +assign trunc_ln33_fu_804_p1 = add_ln33_fu_798_p2[3:0]; + +assign xor_ln19_fu_598_p2 = (icmp_ln20_reg_1033 ^ 1'd1); + +assign zext_ln19_fu_295_p1 = indices_01_read_reg_960; + +assign zext_ln20_8_fu_467_p1 = add_ln20_fu_461_p2; + +assign zext_ln20_fu_372_p1 = ap_phi_mux_jj_phi_fu_263_p4; + +assign zext_ln22_8_fu_634_p1 = add_ln20_reg_1057; + +assign zext_ln22_fu_514_p1 = jj_reg_259; + +assign zext_ln32_36_fu_701_p1 = tmp_18_fu_693_p3; + +assign zext_ln32_37_fu_723_p1 = select_ln20_38_fu_715_p3; + +assign zext_ln32_fu_689_p1 = tmp_s_fu_681_p3; + +assign zext_ln33_30_fu_781_p1 = tmp_fu_774_p3; + +assign zext_ln33_31_fu_795_p1 = select_ln20_35_reg_1093; + +assign zext_ln33_32_fu_816_p1 = select_ln20_reg_1087; + +assign zext_ln33_33_fu_825_p1 = add_ln33_8_reg_1136; + +assign zext_ln33_fu_771_p1 = select_ln19_42_reg_1080; + +endmodule //td_fused_top_tdf10_readInputs69 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_114 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [15:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [15:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [15:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [15:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [8:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [8:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [3:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [3:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [15:0] dataflow_in_loop_TOP_LOOP38116_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP38116_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP38116_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP38116_U0_in_data_we0; +wire [15:0] dataflow_in_loop_TOP_LOOP38116_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP38116_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP38116_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP38116_U0_in_data_we1; +wire [8:0] dataflow_in_loop_TOP_LOOP38116_U0_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP38116_U0_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP38116_U0_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP38116_U0_filter_data_we0; +wire [8:0] dataflow_in_loop_TOP_LOOP38116_U0_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP38116_U0_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP38116_U0_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP38116_U0_filter_data_we1; +wire [3:0] dataflow_in_loop_TOP_LOOP38116_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP38116_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP38116_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP38116_U0_adjustments_we0; +wire [3:0] dataflow_in_loop_TOP_LOOP38116_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP38116_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP38116_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP38116_U0_adjustments_we1; +wire [15:0] dataflow_in_loop_TOP_LOOP38116_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP38116_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP38116_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP38116_U0_out_data_we0; +wire [15:0] dataflow_in_loop_TOP_LOOP38116_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP38116_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP38116_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP38116_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP38116_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP38116_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP38116_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP38116_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP38116_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP38116_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP38116_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP38116_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP38116_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [19:0] loop_dataflow_input_count; +reg [19:0] loop_dataflow_output_count; +wire [19:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP38116_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP38116_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 20'd0; +#0 loop_dataflow_output_count = 20'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP38116 dataflow_in_loop_TOP_LOOP38116_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP38116_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP38116_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP38116_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP38116_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP38116_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP38116_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP38116_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP38116_U0_in_data_we1), + .filter_data_address0(dataflow_in_loop_TOP_LOOP38116_U0_filter_data_address0), + .filter_data_ce0(dataflow_in_loop_TOP_LOOP38116_U0_filter_data_ce0), + .filter_data_d0(dataflow_in_loop_TOP_LOOP38116_U0_filter_data_d0), + .filter_data_q0(filter_data_q0), + .filter_data_we0(dataflow_in_loop_TOP_LOOP38116_U0_filter_data_we0), + .filter_data_address1(dataflow_in_loop_TOP_LOOP38116_U0_filter_data_address1), + .filter_data_ce1(dataflow_in_loop_TOP_LOOP38116_U0_filter_data_ce1), + .filter_data_d1(dataflow_in_loop_TOP_LOOP38116_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(dataflow_in_loop_TOP_LOOP38116_U0_filter_data_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP38116_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP38116_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP38116_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP38116_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP38116_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP38116_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP38116_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP38116_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP38116_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP38116_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP38116_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP38116_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP38116_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP38116_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP38116_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP38116_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP38116_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP38116_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP38116_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP38116_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP38116_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP38116_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP38116_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 20'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP38116_U0_ap_ready == 1'b1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 20'd1); + end else if (((dataflow_in_loop_TOP_LOOP38116_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= 20'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 20'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP38116_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP38116_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 20'd1); + end else if (((dataflow_in_loop_TOP_LOOP38116_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP38116_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + loop_dataflow_output_count <= 20'd0; + end + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP38116_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP38116_U0_ap_idle == 1'b1) & (loop_dataflow_output_count == 20'd0) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP38116_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP38116_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP38116_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP38116_U0_adjustments_address0; + +assign adjustments_address1 = 4'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP38116_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP38116_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP38116_U0_ap_ready; + +assign bound_minus_1 = (20'd802816 - 20'd1); + +assign dataflow_in_loop_TOP_LOOP38116_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP38116_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP38116_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP38116_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP38116_U0_start_write = 1'b0; + +assign filter_data_address0 = dataflow_in_loop_TOP_LOOP38116_U0_filter_data_address0; + +assign filter_data_address1 = 9'd0; + +assign filter_data_ce0 = dataflow_in_loop_TOP_LOOP38116_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP38116_U0_in_data_address0; + +assign in_data_address1 = 16'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP38116_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP38116_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 16'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP38116_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP38116_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP38116_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP38116_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP38116_U0_out_data_write; + +endmodule //td_fused_top_tdf1_114 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_14 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + l1_filter_data_address0, + l1_filter_data_ce0, + l1_filter_data_d0, + l1_filter_data_q0, + l1_filter_data_we0, + l1_filter_data_address1, + l1_filter_data_ce1, + l1_filter_data_d1, + l1_filter_data_q1, + l1_filter_data_we1, + l2_filter_data_address0, + l2_filter_data_ce0, + l2_filter_data_d0, + l2_filter_data_q0, + l2_filter_data_we0, + l2_filter_data_address1, + l2_filter_data_ce1, + l2_filter_data_d1, + l2_filter_data_q1, + l2_filter_data_we1, + l1_adjustments_address0, + l1_adjustments_ce0, + l1_adjustments_d0, + l1_adjustments_q0, + l1_adjustments_we0, + l1_adjustments_address1, + l1_adjustments_ce1, + l1_adjustments_d1, + l1_adjustments_q1, + l1_adjustments_we1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_d0, + l2_adjustments_q0, + l2_adjustments_we0, + l2_adjustments_address1, + l2_adjustments_ce1, + l2_adjustments_d1, + l2_adjustments_q1, + l2_adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [11:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [11:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [12:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [12:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [16:0] l1_filter_data_address0; +output l1_filter_data_ce0; +output [63:0] l1_filter_data_d0; +input [63:0] l1_filter_data_q0; +output l1_filter_data_we0; +output [16:0] l1_filter_data_address1; +output l1_filter_data_ce1; +output [63:0] l1_filter_data_d1; +input [63:0] l1_filter_data_q1; +output l1_filter_data_we1; +output [15:0] l2_filter_data_address0; +output l2_filter_data_ce0; +output [15:0] l2_filter_data_d0; +input [15:0] l2_filter_data_q0; +output l2_filter_data_we0; +output [15:0] l2_filter_data_address1; +output l2_filter_data_ce1; +output [15:0] l2_filter_data_d1; +input [15:0] l2_filter_data_q1; +output l2_filter_data_we1; +output [8:0] l1_adjustments_address0; +output l1_adjustments_ce0; +output [47:0] l1_adjustments_d0; +input [47:0] l1_adjustments_q0; +output l1_adjustments_we0; +output [8:0] l1_adjustments_address1; +output l1_adjustments_ce1; +output [47:0] l1_adjustments_d1; +input [47:0] l1_adjustments_q1; +output l1_adjustments_we1; +output [6:0] l2_adjustments_address0; +output l2_adjustments_ce0; +output [47:0] l2_adjustments_d0; +input [47:0] l2_adjustments_q0; +output l2_adjustments_we0; +output [6:0] l2_adjustments_address1; +output l2_adjustments_ce1; +output [47:0] l2_adjustments_d1; +input [47:0] l2_adjustments_q1; +output l2_adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [11:0] dataflow_in_loop_TOP_LOOP38270_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP38270_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP38270_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP38270_U0_in_data_we0; +wire [11:0] dataflow_in_loop_TOP_LOOP38270_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP38270_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP38270_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP38270_U0_in_data_we1; +wire [16:0] dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_we0; +wire [16:0] dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_we1; +wire [8:0] dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_we0; +wire [8:0] dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_we1; +wire [15:0] dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_we0; +wire [15:0] dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_we1; +wire [12:0] dataflow_in_loop_TOP_LOOP38270_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP38270_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP38270_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP38270_U0_out_data_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP38270_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP38270_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP38270_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP38270_U0_out_data_we1; +wire [6:0] dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_we0; +wire [6:0] dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_we1; +wire dataflow_in_loop_TOP_LOOP38270_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP38270_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP38270_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP38270_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP38270_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP38270_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP38270_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP38270_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP38270_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [16:0] loop_dataflow_input_count; +reg [16:0] loop_dataflow_output_count; +wire [16:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP38270_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP38270_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 17'd0; +#0 loop_dataflow_output_count = 17'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP38270 dataflow_in_loop_TOP_LOOP38270_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP38270_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP38270_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP38270_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP38270_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP38270_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP38270_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP38270_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP38270_U0_in_data_we1), + .l1_filter_data_address0(dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_address0), + .l1_filter_data_ce0(dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_ce0), + .l1_filter_data_d0(dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_d0), + .l1_filter_data_q0(l1_filter_data_q0), + .l1_filter_data_we0(dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_we0), + .l1_filter_data_address1(dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_address1), + .l1_filter_data_ce1(dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_ce1), + .l1_filter_data_d1(dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_d1), + .l1_filter_data_q1(64'd0), + .l1_filter_data_we1(dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_we1), + .l1_adjustments_address0(dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_address0), + .l1_adjustments_ce0(dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_ce0), + .l1_adjustments_d0(dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_d0), + .l1_adjustments_q0(l1_adjustments_q0), + .l1_adjustments_we0(dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_we0), + .l1_adjustments_address1(dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_address1), + .l1_adjustments_ce1(dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_ce1), + .l1_adjustments_d1(dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_d1), + .l1_adjustments_q1(48'd0), + .l1_adjustments_we1(dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_we1), + .l2_filter_data_address0(dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_address0), + .l2_filter_data_ce0(dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_ce0), + .l2_filter_data_d0(dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_d0), + .l2_filter_data_q0(l2_filter_data_q0), + .l2_filter_data_we0(dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_we0), + .l2_filter_data_address1(dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_address1), + .l2_filter_data_ce1(dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_ce1), + .l2_filter_data_d1(dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_d1), + .l2_filter_data_q1(16'd0), + .l2_filter_data_we1(dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP38270_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP38270_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP38270_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP38270_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP38270_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP38270_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP38270_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP38270_U0_out_data_we1), + .l2_adjustments_address0(dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_address0), + .l2_adjustments_ce0(dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_ce0), + .l2_adjustments_d0(dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_d0), + .l2_adjustments_q0(l2_adjustments_q0), + .l2_adjustments_we0(dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_we0), + .l2_adjustments_address1(dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_address1), + .l2_adjustments_ce1(dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_ce1), + .l2_adjustments_d1(dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_d1), + .l2_adjustments_q1(48'd0), + .l2_adjustments_we1(dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_we1), + .ap_start(dataflow_in_loop_TOP_LOOP38270_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP38270_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP38270_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP38270_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP38270_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP38270_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP38270_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 17'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP38270_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 17'd1); + end else if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP38270_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= 17'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 17'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP38270_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP38270_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 17'd1); + end else if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP38270_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP38270_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= 17'd0; + end + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP38270_U0_ap_done == 1'b1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == 17'd0) & (ap_start == 1'b0) & (dataflow_in_loop_TOP_LOOP38270_U0_ap_idle == 1'b1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP38270_U0_ap_ready == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP38270_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP38270_U0_ap_continue = 1'b0; + end +end + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP38270_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP38270_U0_ap_ready; + +assign bound_minus_1 = (17'd100352 - 17'd1); + +assign dataflow_in_loop_TOP_LOOP38270_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP38270_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP38270_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP38270_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP38270_U0_start_write = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP38270_U0_in_data_address0; + +assign in_data_address1 = 12'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP38270_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP38270_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign l1_adjustments_address0 = dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_address0; + +assign l1_adjustments_address1 = 9'd0; + +assign l1_adjustments_ce0 = dataflow_in_loop_TOP_LOOP38270_U0_l1_adjustments_ce0; + +assign l1_adjustments_ce1 = 1'b0; + +assign l1_adjustments_d0 = 48'd0; + +assign l1_adjustments_d1 = 48'd0; + +assign l1_adjustments_we0 = 1'b0; + +assign l1_adjustments_we1 = 1'b0; + +assign l1_filter_data_address0 = dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_address0; + +assign l1_filter_data_address1 = 17'd0; + +assign l1_filter_data_ce0 = dataflow_in_loop_TOP_LOOP38270_U0_l1_filter_data_ce0; + +assign l1_filter_data_ce1 = 1'b0; + +assign l1_filter_data_d0 = 64'd0; + +assign l1_filter_data_d1 = 64'd0; + +assign l1_filter_data_we0 = 1'b0; + +assign l1_filter_data_we1 = 1'b0; + +assign l2_adjustments_address0 = dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_address0; + +assign l2_adjustments_address1 = 7'd0; + +assign l2_adjustments_ce0 = dataflow_in_loop_TOP_LOOP38270_U0_l2_adjustments_ce0; + +assign l2_adjustments_ce1 = 1'b0; + +assign l2_adjustments_d0 = 48'd0; + +assign l2_adjustments_d1 = 48'd0; + +assign l2_adjustments_we0 = 1'b0; + +assign l2_adjustments_we1 = 1'b0; + +assign l2_filter_data_address0 = dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_address0; + +assign l2_filter_data_address1 = 16'd0; + +assign l2_filter_data_ce0 = dataflow_in_loop_TOP_LOOP38270_U0_l2_filter_data_ce0; + +assign l2_filter_data_ce1 = 1'b0; + +assign l2_filter_data_d0 = 16'd0; + +assign l2_filter_data_d1 = 16'd0; + +assign l2_filter_data_we0 = 1'b0; + +assign l2_filter_data_we1 = 1'b0; + +assign out_data_address0 = 13'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP38270_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP38270_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP38270_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP38270_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP38270_U0_out_data_write; + +endmodule //td_fused_top_tdf11_14 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 8'd1; +parameter ap_ST_fsm_pp0_stage0 = 8'd2; +parameter ap_ST_fsm_pp0_stage1 = 8'd4; +parameter ap_ST_fsm_pp0_stage2 = 8'd8; +parameter ap_ST_fsm_pp0_stage3 = 8'd16; +parameter ap_ST_fsm_state12 = 8'd32; +parameter ap_ST_fsm_state13 = 8'd64; +parameter ap_ST_fsm_state14 = 8'd128; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [9:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [9:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[9:0] accum_in_0_address0; +reg accum_in_0_ce0; +reg[9:0] accum_in_0_address1; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [7:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [9:0] x_reg_168; +reg [15:0] psum_7_08_reg_180; +reg [15:0] psum_6_07_reg_192; +reg [15:0] psum_5_06_reg_204; +reg [15:0] psum_4_05_reg_216; +reg [15:0] psum_3_04_reg_228; +reg [15:0] psum_2_03_reg_240; +reg [15:0] psum_1_02_reg_252; +reg [15:0] psum_0_01_reg_264; +wire [0:0] icmp_ln132_fu_321_p2; +reg [0:0] icmp_ln132_reg_492; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state6_pp0_stage0_iter1; +wire ap_block_state10_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln132_reg_492_pp0_iter1_reg; +reg [0:0] icmp_ln132_reg_492_pp0_iter2_reg; +reg [15:0] accum_in_0_load_reg_506; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state7_pp0_stage1_iter1; +wire ap_block_state11_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_0_load_65_reg_511; +reg [15:0] accum_in_0_load_66_reg_526; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state8_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_0_load_67_reg_531; +wire [9:0] add_ln132_fu_387_p2; +reg [9:0] add_ln132_reg_546; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state9_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_0_load_68_reg_551; +reg [15:0] accum_in_0_load_69_reg_556; +reg [15:0] accum_in_0_load_70_reg_571; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_0_load_71_reg_576; +wire [15:0] grp_fu_305_p2; +wire [15:0] grp_fu_310_p2; +reg ap_enable_reg_pp0_iter2; +wire [3:0] add_ln140_fu_432_p2; +wire ap_CS_fsm_state13; +wire [0:0] tmp_fu_415_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage1_subdone; +reg [9:0] ap_phi_mux_x_phi_fu_172_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_184_p4; +wire ap_block_pp0_stage1; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_196_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_208_p4; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_220_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_232_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_03_phi_fu_244_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_276; +wire ap_CS_fsm_state12; +reg [15:0] ap_phi_mux_phi_ln152_phi_fu_290_p8; +wire [2:0] trunc_ln140_fu_428_p1; +wire [63:0] zext_ln132_fu_327_p1; +wire [63:0] zext_ln136_fu_338_p1; +wire [63:0] zext_ln136_13_fu_349_p1; +wire [63:0] zext_ln136_14_fu_360_p1; +wire [63:0] zext_ln136_15_fu_371_p1; +wire [63:0] zext_ln136_16_fu_382_p1; +wire [63:0] zext_ln136_17_fu_399_p1; +wire [63:0] zext_ln136_18_fu_410_p1; +wire [63:0] zext_ln140_fu_423_p1; +wire [63:0] zext_ln140_3_fu_444_p1; +reg [15:0] grp_fu_305_p0; +reg [15:0] grp_fu_305_p1; +reg [15:0] grp_fu_310_p0; +reg [15:0] grp_fu_310_p1; +wire [9:0] or_ln136_fu_332_p2; +wire [9:0] or_ln136_13_fu_343_p2; +wire [9:0] or_ln136_14_fu_354_p2; +wire [9:0] or_ln136_15_fu_365_p2; +wire [9:0] or_ln136_16_fu_376_p2; +wire [9:0] or_ln136_17_fu_393_p2; +wire [9:0] or_ln136_18_fu_404_p2; +wire [2:0] or_ln140_fu_438_p2; +wire [0:0] icmp_ln152_fu_449_p2; +wire [0:0] icmp_ln152_5_fu_463_p2; +wire [15:0] select_ln152_fu_455_p3; +wire [0:0] icmp_ln152_6_fu_477_p2; +wire [15:0] select_ln152_5_fu_469_p3; +wire ap_CS_fsm_state14; +reg [7:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_514; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 8'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U699( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_305_p0), + .din1(grp_fu_305_p1), + .dout(grp_fu_305_p2) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U700( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_310_p0), + .din1(grp_fu_310_p1), + .dout(grp_fu_310_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + q_reg_276 <= 4'd0; + end else if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + q_reg_276 <= add_ln140_fu_432_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + x_reg_168 <= add_ln132_reg_546; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_168 <= 10'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_load_65_reg_511 <= accum_in_0_q0; + accum_in_0_load_reg_506 <= accum_in_0_q1; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_load_66_reg_526 <= accum_in_0_q1; + accum_in_0_load_67_reg_531 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_load_68_reg_551 <= accum_in_0_q1; + accum_in_0_load_69_reg_556 <= accum_in_0_q0; + add_ln132_reg_546 <= add_ln132_fu_387_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_0_load_70_reg_571 <= accum_in_0_q1; + accum_in_0_load_71_reg_576 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln132_reg_492 <= icmp_ln132_fu_321_p2; + icmp_ln132_reg_492_pp0_iter1_reg <= icmp_ln132_reg_492; + icmp_ln132_reg_492_pp0_iter2_reg <= icmp_ln132_reg_492_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_0_01_reg_264 <= grp_fu_305_p2; + psum_1_02_reg_252 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_2_03_reg_240 <= grp_fu_305_p2; + psum_3_04_reg_228 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + psum_4_05_reg_216 <= grp_fu_305_p2; + psum_5_06_reg_204 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter2_reg == 1'd1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + psum_6_07_reg_192 <= grp_fu_305_p2; + psum_7_08_reg_180 <= grp_fu_310_p2; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address0 = zext_ln136_18_fu_410_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address0 = zext_ln136_16_fu_382_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address0 = zext_ln136_14_fu_360_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address0 = zext_ln136_fu_338_p1; + end else begin + accum_in_0_address0 = 'bx; + end + end else begin + accum_in_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address1 = zext_ln136_17_fu_399_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address1 = zext_ln136_15_fu_371_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address1 = zext_ln136_13_fu_349_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address1 = zext_ln132_fu_327_p1; + end else begin + accum_in_0_address1 = 'bx; + end + end else begin + accum_in_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln132_reg_492 == 1'd0)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + if ((trunc_ln140_fu_428_p1 == 3'd0)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_0_01_reg_264; + end else if ((1'b1 == ap_condition_514)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_6_07_reg_192; + end else if ((trunc_ln140_fu_428_p1 == 3'd4)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_4_05_reg_216; + end else if ((trunc_ln140_fu_428_p1 == 3'd2)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_2_03_reg_240; + end else begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_x_phi_fu_172_p4 = add_ln132_reg_546; + end else begin + ap_phi_mux_x_phi_fu_172_p4 = x_reg_168; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_6_07_phi_fu_196_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_4_05_phi_fu_220_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p0 = ap_phi_mux_psum_2_03_phi_fu_244_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p0 = grp_fu_305_p2; + end else begin + grp_fu_305_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p1 = accum_in_0_load_70_reg_571; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p1 = accum_in_0_load_68_reg_551; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p1 = accum_in_0_load_66_reg_526; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p1 = accum_in_0_load_reg_506; + end else begin + grp_fu_305_p1 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p0 = ap_phi_mux_psum_7_08_phi_fu_184_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p0 = ap_phi_mux_psum_5_06_phi_fu_208_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p0 = ap_phi_mux_psum_3_04_phi_fu_232_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p0 = grp_fu_310_p2; + end else begin + grp_fu_310_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p1 = accum_in_0_load_71_reg_576; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p1 = accum_in_0_load_69_reg_556; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p1 = accum_in_0_load_67_reg_531; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p1 = accum_in_0_load_65_reg_511; + end else begin + grp_fu_310_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (icmp_ln132_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (icmp_ln132_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_state14; + end + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln140_3_fu_444_p1; + +assign accum_out_address1 = zext_ln140_fu_423_p1; + +assign accum_out_d0 = ((icmp_ln152_6_fu_477_p2[0:0] == 1'b1) ? psum_5_06_reg_204 : select_ln152_5_fu_469_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln152_phi_fu_290_p8; + +assign add_ln132_fu_387_p2 = (x_reg_168 + 10'd8); + +assign add_ln140_fu_432_p2 = (q_reg_276 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_state14 = ap_CS_fsm[32'd7]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_514 = (~(trunc_ln140_fu_428_p1 == 3'd0) & ~(trunc_ln140_fu_428_p1 == 3'd4) & ~(trunc_ln140_fu_428_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_03_phi_fu_244_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_232_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_220_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_208_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_196_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_184_p4 = grp_fu_310_p2; + +assign icmp_ln132_fu_321_p2 = ((ap_phi_mux_x_phi_fu_172_p4 < 10'd576) ? 1'b1 : 1'b0); + +assign icmp_ln152_5_fu_463_p2 = ((or_ln140_fu_438_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln152_6_fu_477_p2 = ((or_ln140_fu_438_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln152_fu_449_p2 = ((or_ln140_fu_438_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln136_13_fu_343_p2 = (x_reg_168 | 10'd2); + +assign or_ln136_14_fu_354_p2 = (x_reg_168 | 10'd3); + +assign or_ln136_15_fu_365_p2 = (x_reg_168 | 10'd4); + +assign or_ln136_16_fu_376_p2 = (x_reg_168 | 10'd5); + +assign or_ln136_17_fu_393_p2 = (x_reg_168 | 10'd6); + +assign or_ln136_18_fu_404_p2 = (x_reg_168 | 10'd7); + +assign or_ln136_fu_332_p2 = (ap_phi_mux_x_phi_fu_172_p4 | 10'd1); + +assign or_ln140_fu_438_p2 = (trunc_ln140_fu_428_p1 | 3'd1); + +assign select_ln152_5_fu_469_p3 = ((icmp_ln152_5_fu_463_p2[0:0] == 1'b1) ? psum_3_04_reg_228 : select_ln152_fu_455_p3); + +assign select_ln152_fu_455_p3 = ((icmp_ln152_fu_449_p2[0:0] == 1'b1) ? psum_1_02_reg_252 : psum_7_08_reg_180); + +assign tmp_fu_415_p3 = q_reg_276[32'd3]; + +assign trunc_ln140_fu_428_p1 = q_reg_276[2:0]; + +assign zext_ln132_fu_327_p1 = ap_phi_mux_x_phi_fu_172_p4; + +assign zext_ln136_13_fu_349_p1 = or_ln136_13_fu_343_p2; + +assign zext_ln136_14_fu_360_p1 = or_ln136_14_fu_354_p2; + +assign zext_ln136_15_fu_371_p1 = or_ln136_15_fu_365_p2; + +assign zext_ln136_16_fu_382_p1 = or_ln136_16_fu_376_p2; + +assign zext_ln136_17_fu_399_p1 = or_ln136_17_fu_393_p2; + +assign zext_ln136_18_fu_410_p1 = or_ln136_18_fu_404_p2; + +assign zext_ln136_fu_338_p1 = or_ln136_fu_332_p2; + +assign zext_ln140_3_fu_444_p1 = or_ln140_fu_438_p2; + +assign zext_ln140_fu_423_p1 = q_reg_276; + +endmodule //td_fused_top_tdf11_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_22, + accum_in_22_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 7'd1; +parameter ap_ST_fsm_state2 = 7'd2; +parameter ap_ST_fsm_state3 = 7'd4; +parameter ap_ST_fsm_state4 = 7'd8; +parameter ap_ST_fsm_state5 = 7'd16; +parameter ap_ST_fsm_state6 = 7'd32; +parameter ap_ST_fsm_state7 = 7'd64; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_22; +output accum_in_22_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_22; +reg accum_in_22_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [6:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln164_fu_74_p2; +reg [3:0] add_ln164_reg_91; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln164_fu_85_p2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state7; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln164_fu_80_p1; +reg [15:0] accum_in_22_preg; +reg [6:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 7'd1; +#0 accum_in_22_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U703( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_q0), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_22_preg <= 16'd0; + end else begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_22_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + i_1_1_reg_44 <= add_ln164_reg_91; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln164_reg_91 <= add_ln164_fu_74_p2; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_22 = sum_01_reg_55; + end else begin + accum_in_22 = accum_in_22_preg; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_22_ap_vld = 1'b1; + end else begin + accum_in_22_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln164_fu_80_p1; + +assign add_ln164_fu_74_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln164_fu_85_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln164_fu_80_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf11_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + indices_23_out_din, + indices_23_out_full_n, + indices_23_out_write, + ap_return +); + +parameter ap_ST_fsm_state1 = 17'd1; +parameter ap_ST_fsm_state2 = 17'd2; +parameter ap_ST_fsm_state3 = 17'd4; +parameter ap_ST_fsm_state4 = 17'd8; +parameter ap_ST_fsm_state5 = 17'd16; +parameter ap_ST_fsm_state6 = 17'd32; +parameter ap_ST_fsm_state7 = 17'd64; +parameter ap_ST_fsm_state8 = 17'd128; +parameter ap_ST_fsm_state9 = 17'd256; +parameter ap_ST_fsm_state10 = 17'd512; +parameter ap_ST_fsm_state11 = 17'd1024; +parameter ap_ST_fsm_state12 = 17'd2048; +parameter ap_ST_fsm_state13 = 17'd4096; +parameter ap_ST_fsm_state14 = 17'd8192; +parameter ap_ST_fsm_state15 = 17'd16384; +parameter ap_ST_fsm_state16 = 17'd32768; +parameter ap_ST_fsm_state17 = 17'd65536; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_read; +output [8:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [8:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [8:0] indices_23_out_din; +input indices_23_out_full_n; +output indices_23_out_write; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg indices_23_read; +reg indices_23_out_write; + +reg ap_done_reg; + reg [16:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg indices_23_out_blk_n; +wire ap_CS_fsm_state4; +reg [15:0] tmp_96_i_i_reg_179; +reg [15:0] tmp_97_i_i_reg_184; +wire [15:0] grp_fu_93_p2; +reg [15:0] sub_i_i_i_reg_189; +wire ap_CS_fsm_state8; +wire ap_CS_fsm_state9; +wire [15:0] grp_fu_98_p2; +reg [15:0] mul_i_i_i_reg_199; +wire ap_CS_fsm_state12; +wire ap_CS_fsm_state13; +wire [63:0] zext_ln220_fu_102_p1; +reg ap_block_state1; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_89_p1; +wire [15:0] grp_fu_93_p1; +wire [15:0] grp_fu_98_p1; +wire [15:0] trunc_ln220_fu_107_p1; +wire [15:0] grp_fu_89_p2; +wire ap_CS_fsm_state17; +wire [15:0] bitcast_ln648_fu_144_p1; +wire [0:0] tmp_fu_148_p3; +reg [16:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 17'd1; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U707( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(mul_i_i_i_reg_199), + .din1(grp_fu_89_p1), + .dout(grp_fu_89_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U708( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sums_read), + .din1(grp_fu_93_p1), + .dout(grp_fu_93_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U709( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_189), + .din1(grp_fu_98_p1), + .dout(grp_fu_98_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + mul_i_i_i_reg_199 <= grp_fu_98_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sub_i_i_i_reg_189 <= grp_fu_93_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tmp_96_i_i_reg_179 <= {{adjustments_q0[31:16]}}; + tmp_97_i_i_reg_184 <= {{adjustments_q0[47:32]}}; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_out_blk_n = indices_23_out_full_n; + end else begin + indices_23_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_out_write = 1'b1; + end else begin + indices_23_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign adjustments_address0 = zext_ln220_fu_102_p1; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_return = ((tmp_fu_148_p3[0:0] == 1'b1) ? 16'd0 : grp_fu_89_p2); + +assign bitcast_ln648_fu_144_p1 = grp_fu_89_p2; + +assign grp_fu_89_p1 = tmp_97_i_i_reg_184; + +assign grp_fu_93_p1 = trunc_ln220_fu_107_p1; + +assign grp_fu_98_p1 = tmp_96_i_i_reg_179; + +assign indices_23_out_din = indices_23_dout; + +assign tmp_fu_148_p3 = bitcast_ln648_fu_144_p1[32'd15]; + +assign trunc_ln220_fu_107_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_102_p1 = indices_23_dout; + +endmodule //td_fused_top_tdf11_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_q0, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [9:0] ifmap_vec_address0; +output ifmap_vec_ce0; +input [15:0] ifmap_vec_q0; +output [9:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +input [15:0] weight_vecs_0_q0; +output [9:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_ce0; +reg weight_vecs_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [9:0] indvar_flatten17_reg_97; +reg [8:0] indvar_flatten_reg_108; +reg [1:0] jj_reg_119; +reg [6:0] ic_reg_131; +reg [1:0] ii_reg_142; +wire [9:0] add_ln147_7_fu_157_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln147_fu_163_p2; +reg [0:0] icmp_ln147_reg_408; +reg [0:0] icmp_ln147_reg_408_pp0_iter1_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter2_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter3_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter4_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter5_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter6_reg; +wire [0:0] icmp_ln148_fu_169_p2; +reg [0:0] icmp_ln148_reg_412; +wire [0:0] and_ln147_fu_195_p2; +reg [0:0] and_ln147_reg_419; +wire [1:0] add_ln148_fu_201_p2; +reg [1:0] add_ln148_reg_424; +wire [6:0] select_ln148_fu_213_p3; +reg [6:0] select_ln148_reg_429; +wire [1:0] select_ln148_19_fu_221_p3; +reg [1:0] select_ln148_19_reg_434; +wire [5:0] trunc_ln150_fu_229_p1; +reg [5:0] trunc_ln150_reg_440; +reg [5:0] trunc_ln150_reg_440_pp0_iter1_reg; +reg [5:0] trunc_ln150_reg_440_pp0_iter2_reg; +reg [5:0] trunc_ln150_reg_440_pp0_iter3_reg; +reg [5:0] trunc_ln150_reg_440_pp0_iter4_reg; +reg [5:0] trunc_ln150_reg_440_pp0_iter5_reg; +reg [5:0] trunc_ln150_reg_440_pp0_iter6_reg; +wire [6:0] add_ln149_fu_233_p2; +wire [8:0] select_ln148_21_fu_245_p3; +wire [1:0] select_ln147_20_fu_287_p3; +reg [1:0] select_ln147_20_reg_455; +reg ap_enable_reg_pp0_iter1; +wire [3:0] select_ln148_20_fu_370_p3; +reg [3:0] select_ln148_20_reg_460; +reg [3:0] select_ln148_20_reg_460_pp0_iter2_reg; +reg [3:0] select_ln148_20_reg_460_pp0_iter3_reg; +reg [3:0] select_ln148_20_reg_460_pp0_iter4_reg; +reg [3:0] select_ln148_20_reg_460_pp0_iter5_reg; +reg [3:0] select_ln148_20_reg_460_pp0_iter6_reg; +reg [15:0] ifmap_vec_load_reg_475; +reg [15:0] weight_vecs_0_load_reg_480; +wire [15:0] grp_fu_153_p2; +reg [15:0] mul_reg_485; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg [1:0] ap_phi_mux_jj_phi_fu_123_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_146_p4; +wire [63:0] p_cast25_fu_386_p1; +wire [63:0] idxprom30_fu_398_p1; +wire [0:0] icmp_ln149_fu_189_p2; +wire [0:0] xor_ln147_fu_183_p2; +wire [1:0] select_ln147_fu_175_p3; +wire [0:0] or_ln148_fu_207_p2; +wire [8:0] add_ln148_7_fu_239_p2; +wire [3:0] shl_ln_fu_257_p3; +wire [3:0] zext_ln150_fu_253_p1; +wire [3:0] sub_ln150_fu_265_p2; +wire [3:0] zext_ln150_10_fu_271_p1; +wire [1:0] add_ln147_fu_281_p2; +wire [3:0] tmp_fu_298_p3; +wire [3:0] select_ln147_26_cast_fu_294_p1; +wire [3:0] shl_ln150_mid1_fu_316_p3; +wire [3:0] zext_ln150_15_fu_312_p1; +wire [3:0] sub_ln150_9_fu_324_p2; +wire [3:0] add_ln150_fu_275_p2; +wire [3:0] empty_139_fu_306_p2; +wire [3:0] select_ln148_25_cast_fu_344_p1; +wire [3:0] empty_140_fu_347_p2; +wire [3:0] select_ln147_21_fu_330_p3; +wire [3:0] zext_ln150_16_fu_361_p1; +wire [3:0] add_ln150_8_fu_364_p2; +wire [3:0] select_ln147_22_fu_337_p3; +wire [9:0] tmp_178_cast_fu_353_p3; +wire [9:0] select_ln148_cast_fu_377_p1; +wire [9:0] empty_141_fu_380_p2; +wire [9:0] p_fu_392_p3; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U695( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_load_reg_475), + .din1(weight_vecs_0_load_reg_480), + .dout(grp_fu_153_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_reg_131 <= add_ln149_fu_233_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_reg_131 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ii_reg_142 <= select_ln147_20_reg_455; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_142 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten17_reg_97 <= add_ln147_7_fu_157_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten17_reg_97 <= 10'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_108 <= select_ln148_21_fu_245_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_108 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_119 <= select_ln148_19_reg_434; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_119 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln148_reg_424 <= add_ln148_fu_201_p2; + and_ln147_reg_419 <= and_ln147_fu_195_p2; + icmp_ln148_reg_412 <= icmp_ln148_fu_169_p2; + select_ln148_reg_429 <= select_ln148_fu_213_p3; + trunc_ln150_reg_440 <= trunc_ln150_fu_229_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln147_reg_408 <= icmp_ln147_fu_163_p2; + icmp_ln147_reg_408_pp0_iter1_reg <= icmp_ln147_reg_408; + trunc_ln150_reg_440_pp0_iter1_reg <= trunc_ln150_reg_440; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln147_reg_408_pp0_iter2_reg <= icmp_ln147_reg_408_pp0_iter1_reg; + icmp_ln147_reg_408_pp0_iter3_reg <= icmp_ln147_reg_408_pp0_iter2_reg; + icmp_ln147_reg_408_pp0_iter4_reg <= icmp_ln147_reg_408_pp0_iter3_reg; + icmp_ln147_reg_408_pp0_iter5_reg <= icmp_ln147_reg_408_pp0_iter4_reg; + icmp_ln147_reg_408_pp0_iter6_reg <= icmp_ln147_reg_408_pp0_iter5_reg; + select_ln148_20_reg_460_pp0_iter2_reg <= select_ln148_20_reg_460; + select_ln148_20_reg_460_pp0_iter3_reg <= select_ln148_20_reg_460_pp0_iter2_reg; + select_ln148_20_reg_460_pp0_iter4_reg <= select_ln148_20_reg_460_pp0_iter3_reg; + select_ln148_20_reg_460_pp0_iter5_reg <= select_ln148_20_reg_460_pp0_iter4_reg; + select_ln148_20_reg_460_pp0_iter6_reg <= select_ln148_20_reg_460_pp0_iter5_reg; + trunc_ln150_reg_440_pp0_iter2_reg <= trunc_ln150_reg_440_pp0_iter1_reg; + trunc_ln150_reg_440_pp0_iter3_reg <= trunc_ln150_reg_440_pp0_iter2_reg; + trunc_ln150_reg_440_pp0_iter4_reg <= trunc_ln150_reg_440_pp0_iter3_reg; + trunc_ln150_reg_440_pp0_iter5_reg <= trunc_ln150_reg_440_pp0_iter4_reg; + trunc_ln150_reg_440_pp0_iter6_reg <= trunc_ln150_reg_440_pp0_iter5_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_load_reg_475 <= ifmap_vec_q0; + weight_vecs_0_load_reg_480 <= weight_vecs_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_reg_485 <= grp_fu_153_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + select_ln147_20_reg_455 <= select_ln147_20_fu_287_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_19_reg_434 <= select_ln148_19_fu_221_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_20_reg_460 <= select_ln148_20_fu_370_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_fu_163_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_146_p4 = select_ln147_20_reg_455; + end else begin + ap_phi_mux_ii_phi_fu_146_p4 = ii_reg_142; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_123_p4 = select_ln148_19_reg_434; + end else begin + ap_phi_mux_jj_phi_fu_123_p4 = jj_reg_119; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_7_fu_157_p2 = (indvar_flatten17_reg_97 + 10'd1); + +assign add_ln147_fu_281_p2 = (ap_phi_mux_ii_phi_fu_146_p4 + 2'd1); + +assign add_ln148_7_fu_239_p2 = (indvar_flatten_reg_108 + 9'd1); + +assign add_ln148_fu_201_p2 = (select_ln147_fu_175_p3 + 2'd1); + +assign add_ln149_fu_233_p2 = (select_ln148_fu_213_p3 + 7'd1); + +assign add_ln150_8_fu_364_p2 = (select_ln147_21_fu_330_p3 + zext_ln150_16_fu_361_p1); + +assign add_ln150_fu_275_p2 = (sub_ln150_fu_265_p2 + zext_ln150_10_fu_271_p1); + +assign and_ln147_fu_195_p2 = (xor_ln147_fu_183_p2 & icmp_ln149_fu_189_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign empty_139_fu_306_p2 = (tmp_fu_298_p3 - select_ln147_26_cast_fu_294_p1); + +assign empty_140_fu_347_p2 = (empty_139_fu_306_p2 + select_ln148_25_cast_fu_344_p1); + +assign empty_141_fu_380_p2 = (tmp_178_cast_fu_353_p3 + select_ln148_cast_fu_377_p1); + +assign icmp_ln147_fu_163_p2 = ((indvar_flatten17_reg_97 == 10'd576) ? 1'b1 : 1'b0); + +assign icmp_ln148_fu_169_p2 = ((indvar_flatten_reg_108 == 9'd192) ? 1'b1 : 1'b0); + +assign icmp_ln149_fu_189_p2 = ((ic_reg_131 == 7'd64) ? 1'b1 : 1'b0); + +assign idxprom30_fu_398_p1 = p_fu_392_p3; + +assign ifmap_vec_address0 = p_cast25_fu_386_p1; + +assign or_ln148_fu_207_p2 = (icmp_ln148_fu_169_p2 | and_ln147_fu_195_p2); + +assign p_cast25_fu_386_p1 = empty_141_fu_380_p2; + +assign p_fu_392_p3 = {{select_ln148_20_reg_460_pp0_iter6_reg}, {trunc_ln150_reg_440_pp0_iter6_reg}}; + +assign products_0_address0 = idxprom30_fu_398_p1; + +assign products_0_d0 = mul_reg_485; + +assign select_ln147_20_fu_287_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? add_ln147_fu_281_p2 : ap_phi_mux_ii_phi_fu_146_p4); + +assign select_ln147_21_fu_330_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? sub_ln150_9_fu_324_p2 : sub_ln150_fu_265_p2); + +assign select_ln147_22_fu_337_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? sub_ln150_9_fu_324_p2 : add_ln150_fu_275_p2); + +assign select_ln147_26_cast_fu_294_p1 = select_ln147_20_fu_287_p3; + +assign select_ln147_fu_175_p3 = ((icmp_ln148_fu_169_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_123_p4); + +assign select_ln148_19_fu_221_p3 = ((and_ln147_fu_195_p2[0:0] == 1'b1) ? add_ln148_fu_201_p2 : select_ln147_fu_175_p3); + +assign select_ln148_20_fu_370_p3 = ((and_ln147_reg_419[0:0] == 1'b1) ? add_ln150_8_fu_364_p2 : select_ln147_22_fu_337_p3); + +assign select_ln148_21_fu_245_p3 = ((icmp_ln148_fu_169_p2[0:0] == 1'b1) ? 9'd1 : add_ln148_7_fu_239_p2); + +assign select_ln148_25_cast_fu_344_p1 = select_ln148_19_reg_434; + +assign select_ln148_cast_fu_377_p1 = select_ln148_reg_429; + +assign select_ln148_fu_213_p3 = ((or_ln148_fu_207_p2[0:0] == 1'b1) ? 7'd0 : ic_reg_131); + +assign shl_ln150_mid1_fu_316_p3 = {{add_ln147_fu_281_p2}, {2'd0}}; + +assign shl_ln_fu_257_p3 = {{ap_phi_mux_ii_phi_fu_146_p4}, {2'd0}}; + +assign sub_ln150_9_fu_324_p2 = (shl_ln150_mid1_fu_316_p3 - zext_ln150_15_fu_312_p1); + +assign sub_ln150_fu_265_p2 = (shl_ln_fu_257_p3 - zext_ln150_fu_253_p1); + +assign tmp_178_cast_fu_353_p3 = {{empty_140_fu_347_p2}, {6'd0}}; + +assign tmp_fu_298_p3 = {{select_ln147_20_fu_287_p3}, {2'd0}}; + +assign trunc_ln150_fu_229_p1 = select_ln148_fu_213_p3[5:0]; + +assign weight_vecs_0_address0 = p_cast25_fu_386_p1; + +assign xor_ln147_fu_183_p2 = (icmp_ln148_fu_169_p2 ^ 1'd1); + +assign zext_ln150_10_fu_271_p1 = jj_reg_119; + +assign zext_ln150_15_fu_312_p1 = add_ln147_fu_281_p2; + +assign zext_ln150_16_fu_361_p1 = add_ln148_reg_424; + +assign zext_ln150_fu_253_p1 = ap_phi_mux_ii_phi_fu_146_p4; + +endmodule //td_fused_top_tdf11_dot_product +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + indices_2_out_din, + indices_2_out_full_n, + indices_2_out_write, + indices_2_out1_din, + indices_2_out1_full_n, + indices_2_out1_write, + write_r_din, + write_r_full_n, + write_r_write +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [8:0] indices_2_out_din; +input indices_2_out_full_n; +output indices_2_out_write; +output [8:0] indices_2_out1_din; +input indices_2_out1_full_n; +output indices_2_out1_write; +output write_r_din; +input write_r_full_n; +output write_r_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg indices_0_write; +reg indices_1_write; +reg indices_2_out_write; +reg indices_2_out1_write; +reg write_r_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [15:0] i_9; +reg [15:0] j_9; +reg [15:0] k_9; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg indices_2_out_blk_n; +reg indices_2_out1_blk_n; +reg write_r_blk_n; +reg [0:0] ap_phi_mux_j_20_flag_0_i_phi_fu_90_p6; +reg ap_block_state1; +wire [0:0] icmp_ln188_fu_161_p2; +wire [0:0] icmp_ln191_fu_174_p2; +reg [15:0] ap_phi_mux_j_20_new_0_i_phi_fu_104_p6; +wire [15:0] add_ln190_fu_167_p2; +reg [15:0] ap_phi_mux_k_20_new_0_i_phi_fu_117_p6; +wire [15:0] add_ln187_fu_154_p2; +wire [15:0] select_ln194_fu_192_p3; +wire [8:0] trunc_ln185_fu_141_p1; +wire [15:0] add_ln193_fu_180_p2; +wire [0:0] icmp_ln194_fu_186_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_9 = 16'd0; +#0 j_9 = 16'd0; +#0 k_9 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln191_fu_174_p2 == 1'd1) & (icmp_ln188_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_9 <= select_ln194_fu_192_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_20_flag_0_i_phi_fu_90_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j_9 <= ap_phi_mux_j_20_new_0_i_phi_fu_104_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k_9 <= ap_phi_mux_k_20_new_0_i_phi_fu_117_p6; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln188_fu_161_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_20_flag_0_i_phi_fu_90_p6 = 1'd0; + end else if ((((icmp_ln191_fu_174_p2 == 1'd0) & (icmp_ln188_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln191_fu_174_p2 == 1'd1) & (icmp_ln188_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_20_flag_0_i_phi_fu_90_p6 = 1'd1; + end else begin + ap_phi_mux_j_20_flag_0_i_phi_fu_90_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln188_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln191_fu_174_p2 == 1'd0)) begin + ap_phi_mux_j_20_new_0_i_phi_fu_104_p6 = add_ln190_fu_167_p2; + end else if ((icmp_ln191_fu_174_p2 == 1'd1)) begin + ap_phi_mux_j_20_new_0_i_phi_fu_104_p6 = 16'd0; + end else begin + ap_phi_mux_j_20_new_0_i_phi_fu_104_p6 = 'bx; + end + end else begin + ap_phi_mux_j_20_new_0_i_phi_fu_104_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln188_fu_161_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_20_new_0_i_phi_fu_117_p6 = add_ln187_fu_154_p2; + end else if ((((icmp_ln191_fu_174_p2 == 1'd0) & (icmp_ln188_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln191_fu_174_p2 == 1'd1) & (icmp_ln188_fu_161_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_20_new_0_i_phi_fu_117_p6 = 16'd0; + end else begin + ap_phi_mux_k_20_new_0_i_phi_fu_117_p6 = 'bx; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_blk_n = indices_2_out1_full_n; + end else begin + indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_write = 1'b1; + end else begin + indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_blk_n = indices_2_out_full_n; + end else begin + indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_write = 1'b1; + end else begin + indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_r_blk_n = write_r_full_n; + end else begin + write_r_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_r_write = 1'b1; + end else begin + write_r_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln187_fu_154_p2 = (k_9 + 16'd1); + +assign add_ln190_fu_167_p2 = (j_9 + 16'd1); + +assign add_ln193_fu_180_p2 = (i_9 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign icmp_ln188_fu_161_p2 = ((add_ln187_fu_154_p2 == 16'd512) ? 1'b1 : 1'b0); + +assign icmp_ln191_fu_174_p2 = ((add_ln190_fu_167_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign icmp_ln194_fu_186_p2 = ((add_ln193_fu_180_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign indices_0_din = i_9; + +assign indices_1_din = j_9; + +assign indices_2_out1_din = trunc_ln185_fu_141_p1; + +assign indices_2_out_din = trunc_ln185_fu_141_p1; + +assign select_ln194_fu_192_p3 = ((icmp_ln194_fu_186_p2[0:0] == 1'b1) ? 16'd0 : add_ln193_fu_180_p2); + +assign start_out = real_start; + +assign trunc_ln185_fu_141_p1 = k_9[8:0]; + +assign write_r_din = ((k_9 == 16'd511) ? 1'b1 : 1'b0); + +endmodule //td_fused_top_tdf11_get_next_ijk +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf11_l2_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 16; +parameter MEM_SIZE = 65536; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf11_l2_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd65536; +parameter AddressWidth = 32'd16; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf11_l2_filters_ram td_fused_top_tdf11_l2_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_l2_multiply72 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + intermediate_fmaps_read, + l2_filter_data_address0, + l2_filter_data_ce0, + l2_filter_data_q0, + l2_products_address0, + l2_products_ce0, + l2_products_we0, + l2_products_d0, + indices_23_dout, + indices_23_empty_n, + indices_23_read +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] intermediate_fmaps_read; +output [15:0] l2_filter_data_address0; +output l2_filter_data_ce0; +input [15:0] l2_filter_data_q0; +output [6:0] l2_products_address0; +output l2_products_ce0; +output l2_products_we0; +output [15:0] l2_products_d0; +input [8:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg l2_filter_data_ce0; +reg l2_products_ce0; +reg l2_products_we0; +reg indices_23_read; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [7:0] i_1_1_reg_106; +reg [7:0] i_1_1_reg_106_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +reg [7:0] i_1_1_reg_106_pp0_iter2_reg; +reg [7:0] i_1_1_reg_106_pp0_iter3_reg; +reg [7:0] i_1_1_reg_106_pp0_iter4_reg; +reg [7:0] i_1_1_reg_106_pp0_iter5_reg; +reg [7:0] i_1_1_reg_106_pp0_iter6_reg; +reg [8:0] indices_23_read_reg_167; +wire [7:0] i_12_fu_123_p2; +reg [7:0] i_12_reg_172; +reg ap_enable_reg_pp0_iter0; +wire [0:0] icmp_ln20_fu_129_p2; +reg [0:0] icmp_ln20_reg_177; +reg [0:0] icmp_ln20_reg_177_pp0_iter1_reg; +reg [0:0] icmp_ln20_reg_177_pp0_iter2_reg; +reg [0:0] icmp_ln20_reg_177_pp0_iter3_reg; +reg [0:0] icmp_ln20_reg_177_pp0_iter4_reg; +reg [0:0] icmp_ln20_reg_177_pp0_iter5_reg; +reg [0:0] icmp_ln20_reg_177_pp0_iter6_reg; +wire [15:0] grp_fu_118_p2; +reg [15:0] mul_i_i_reg_191; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg [7:0] ap_phi_mux_i_1_1_phi_fu_110_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln29_25_fu_152_p1; +wire [63:0] zext_ln29_fu_157_p1; +wire [6:0] trunc_ln29_fu_140_p1; +wire [8:0] l2_ichan_fu_135_p2; +wire [15:0] tmp_s_fu_144_p3; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U714( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(l2_filter_data_q0), + .din1(intermediate_fmaps_read), + .dout(grp_fu_118_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln20_reg_177 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + i_1_1_reg_106 <= i_12_reg_172; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_106 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + i_12_reg_172 <= i_12_fu_123_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + i_1_1_reg_106_pp0_iter1_reg <= i_1_1_reg_106; + icmp_ln20_reg_177 <= icmp_ln20_fu_129_p2; + icmp_ln20_reg_177_pp0_iter1_reg <= icmp_ln20_reg_177; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + i_1_1_reg_106_pp0_iter2_reg <= i_1_1_reg_106_pp0_iter1_reg; + i_1_1_reg_106_pp0_iter3_reg <= i_1_1_reg_106_pp0_iter2_reg; + i_1_1_reg_106_pp0_iter4_reg <= i_1_1_reg_106_pp0_iter3_reg; + i_1_1_reg_106_pp0_iter5_reg <= i_1_1_reg_106_pp0_iter4_reg; + i_1_1_reg_106_pp0_iter6_reg <= i_1_1_reg_106_pp0_iter5_reg; + icmp_ln20_reg_177_pp0_iter2_reg <= icmp_ln20_reg_177_pp0_iter1_reg; + icmp_ln20_reg_177_pp0_iter3_reg <= icmp_ln20_reg_177_pp0_iter2_reg; + icmp_ln20_reg_177_pp0_iter4_reg <= icmp_ln20_reg_177_pp0_iter3_reg; + icmp_ln20_reg_177_pp0_iter5_reg <= icmp_ln20_reg_177_pp0_iter4_reg; + icmp_ln20_reg_177_pp0_iter6_reg <= icmp_ln20_reg_177_pp0_iter5_reg; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + indices_23_read_reg_167 <= indices_23_dout; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln20_reg_177_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_i_i_reg_191 <= grp_fu_118_p2; + end +end + +always @ (*) begin + if ((icmp_ln20_fu_129_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln20_reg_177 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_i_1_1_phi_fu_110_p4 = i_12_reg_172; + end else begin + ap_phi_mux_i_1_1_phi_fu_110_p4 = i_1_1_reg_106; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + l2_filter_data_ce0 = 1'b1; + end else begin + l2_filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + l2_products_ce0 = 1'b1; + end else begin + l2_products_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln20_reg_177_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + l2_products_we0 = 1'b1; + end else begin + l2_products_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln20_fu_129_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln20_fu_129_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign i_12_fu_123_p2 = (ap_phi_mux_i_1_1_phi_fu_110_p4 + 8'd1); + +assign icmp_ln20_fu_129_p2 = ((ap_phi_mux_i_1_1_phi_fu_110_p4 == 8'd128) ? 1'b1 : 1'b0); + +assign l2_filter_data_address0 = zext_ln29_25_fu_152_p1; + +assign l2_ichan_fu_135_p2 = (indices_23_read_reg_167 + 9'd0); + +assign l2_products_address0 = zext_ln29_fu_157_p1; + +assign l2_products_d0 = mul_i_i_reg_191; + +assign tmp_s_fu_144_p3 = {{trunc_ln29_fu_140_p1}, {l2_ichan_fu_135_p2}}; + +assign trunc_ln29_fu_140_p1 = ap_phi_mux_i_1_1_phi_fu_110_p4[6:0]; + +assign zext_ln29_25_fu_152_p1 = tmp_s_fu_144_p3; + +assign zext_ln29_fu_157_p1 = i_1_1_reg_106_pp0_iter6_reg; + +endmodule //td_fused_top_tdf11_l2_multiply72 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2_ram (addr0, ce0, d0, we0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 7; +parameter MEM_SIZE = 128; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2_ram.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2( + reset, + clk, + address0, + ce0, + we0, + d0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd128; +parameter AddressWidth = 32'd7; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2_ram td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_l2_writeOutputs_171 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + write4_dout, + write4_empty_n, + write4_read, + l2_partial_sums_address0, + l2_partial_sums_ce0, + l2_partial_sums_q0, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_q0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state25 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [3:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [7:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [0:0] write4_dout; +input write4_empty_n; +output write4_read; +output [6:0] l2_partial_sums_address0; +output l2_partial_sums_ce0; +input [15:0] l2_partial_sums_q0; +output [12:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; +output [6:0] l2_adjustments_address0; +output l2_adjustments_ce0; +input [47:0] l2_adjustments_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg write4_read; +reg l2_partial_sums_ce0; +reg out_data_ce1; +reg out_data_we1; +reg l2_adjustments_ce0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg running_sums_2_ce0; +reg running_sums_2_we0; +wire [15:0] running_sums_2_d0; +wire [6:0] running_sums_2_address1; +reg running_sums_2_ce1; +wire [15:0] running_sums_2_q1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg write4_blk_n; +reg [7:0] ochan_reg_208; +reg [0:0] write4_read_reg_567; +wire [9:0] add_ln109_fu_273_p2; +reg [9:0] add_ln109_reg_573; +wire [7:0] ochan_1_fu_279_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_state13_pp0_stage0_iter11; +wire ap_block_state14_pp0_stage0_iter12; +wire ap_block_state15_pp0_stage0_iter13; +wire ap_block_state16_pp0_stage0_iter14; +wire ap_block_state17_pp0_stage0_iter15; +wire ap_block_state18_pp0_stage0_iter16; +wire ap_block_state19_pp0_stage0_iter17; +wire ap_block_state20_pp0_stage0_iter18; +wire ap_block_state21_pp0_stage0_iter19; +wire ap_block_state22_pp0_stage0_iter20; +wire ap_block_state23_pp0_stage0_iter21; +wire ap_block_state24_pp0_stage0_iter22; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln86_fu_285_p2; +wire [1:0] trunc_ln86_fu_291_p1; +reg [1:0] trunc_ln86_reg_587; +reg [1:0] trunc_ln86_reg_587_pp0_iter1_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter2_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter3_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter4_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter5_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter6_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter7_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter8_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter9_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter10_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter11_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter12_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter13_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter14_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter15_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter16_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter17_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter18_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter19_reg; +reg [1:0] trunc_ln86_reg_587_pp0_iter20_reg; +wire [63:0] zext_ln89_fu_295_p1; +reg [63:0] zext_ln89_reg_594; +reg [63:0] zext_ln89_reg_594_pp0_iter1_reg; +reg [63:0] zext_ln89_reg_594_pp0_iter2_reg; +reg [63:0] zext_ln89_reg_594_pp0_iter3_reg; +reg [6:0] running_sums_2_addr_reg_604; +reg [6:0] running_sums_2_addr_reg_604_pp0_iter1_reg; +reg [6:0] running_sums_2_addr_reg_604_pp0_iter2_reg; +reg [6:0] running_sums_2_addr_reg_604_pp0_iter3_reg; +reg [6:0] running_sums_2_addr_reg_604_pp0_iter4_reg; +reg [6:0] running_sums_2_addr_reg_604_pp0_iter5_reg; +reg [6:0] running_sums_2_addr_reg_604_pp0_iter6_reg; +wire [0:0] and_ln103_fu_307_p2; +reg [0:0] and_ln103_reg_610; +reg [0:0] and_ln103_reg_610_pp0_iter1_reg; +reg [0:0] and_ln103_reg_610_pp0_iter2_reg; +reg [0:0] and_ln103_reg_610_pp0_iter3_reg; +reg [0:0] and_ln103_reg_610_pp0_iter4_reg; +reg [0:0] and_ln103_reg_610_pp0_iter5_reg; +reg [0:0] and_ln103_reg_610_pp0_iter6_reg; +reg [0:0] and_ln103_reg_610_pp0_iter7_reg; +reg [0:0] and_ln103_reg_610_pp0_iter8_reg; +reg [0:0] and_ln103_reg_610_pp0_iter9_reg; +reg [0:0] and_ln103_reg_610_pp0_iter10_reg; +reg [0:0] and_ln103_reg_610_pp0_iter11_reg; +reg [0:0] and_ln103_reg_610_pp0_iter12_reg; +reg [0:0] and_ln103_reg_610_pp0_iter13_reg; +reg [0:0] and_ln103_reg_610_pp0_iter14_reg; +reg [0:0] and_ln103_reg_610_pp0_iter15_reg; +reg [0:0] and_ln103_reg_610_pp0_iter16_reg; +reg [0:0] and_ln103_reg_610_pp0_iter17_reg; +reg [0:0] and_ln103_reg_610_pp0_iter18_reg; +reg [0:0] and_ln103_reg_610_pp0_iter19_reg; +reg [0:0] and_ln103_reg_610_pp0_iter20_reg; +reg [4:0] lshr_ln_reg_614; +reg [4:0] lshr_ln_reg_614_pp0_iter1_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter2_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter3_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter4_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter5_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter6_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter7_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter8_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter9_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter10_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter11_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter12_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter13_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter14_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter15_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter16_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter17_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter18_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter19_reg; +reg [4:0] lshr_ln_reg_614_pp0_iter20_reg; +reg [15:0] val_reg_619; +reg [15:0] running_sums_2_load_reg_624; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_219_p2; +reg [15:0] sum_reg_634; +reg [15:0] tmp_90_i_i_reg_645; +reg [15:0] tmp_90_i_i_reg_645_pp0_iter8_reg; +reg [15:0] tmp_90_i_i_reg_645_pp0_iter9_reg; +reg [15:0] tmp_90_i_i_reg_645_pp0_iter10_reg; +reg [15:0] tmp_90_i_i_reg_645_pp0_iter11_reg; +reg [15:0] tmp_91_i_i_reg_650; +reg [15:0] tmp_91_i_i_reg_650_pp0_iter8_reg; +reg [15:0] tmp_91_i_i_reg_650_pp0_iter9_reg; +reg [15:0] tmp_91_i_i_reg_650_pp0_iter10_reg; +reg [15:0] tmp_91_i_i_reg_650_pp0_iter11_reg; +reg [15:0] tmp_91_i_i_reg_650_pp0_iter12_reg; +reg [15:0] tmp_91_i_i_reg_650_pp0_iter13_reg; +reg [15:0] tmp_91_i_i_reg_650_pp0_iter14_reg; +reg [15:0] tmp_91_i_i_reg_650_pp0_iter15_reg; +wire [15:0] grp_fu_227_p2; +reg [15:0] sub_i_i_i_reg_655; +wire [15:0] grp_fu_231_p2; +reg [15:0] normalized_reg_665; +wire [15:0] grp_fu_223_p2; +reg [15:0] biased_reg_675; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_enable_reg_pp0_iter22; +wire ap_block_pp0_stage0; +wire [63:0] sext_ln109_fu_509_p1; +reg [15:0] quad_3_27_fu_114; +wire [15:0] quad_3_38_fu_475_p3; +reg [15:0] quad_3_26_fu_118; +wire [15:0] quad_3_37_fu_467_p3; +reg [15:0] quad_3_28_fu_122; +wire [15:0] quad_3_35_fu_451_p3; +reg [15:0] quad_3_29_fu_126; +wire [15:0] quad_3_32_fu_427_p3; +wire [15:0] grp_fu_223_p1; +wire [15:0] grp_fu_227_p1; +wire [15:0] grp_fu_231_p1; +wire [7:0] tmp_fu_235_p3; +wire [4:0] tmp_s_fu_247_p3; +wire [8:0] zext_ln109_fu_243_p1; +wire [8:0] zext_ln109_5_fu_255_p1; +wire [8:0] sub_ln109_fu_259_p2; +wire [9:0] sub_ln109_cast_fu_265_p1; +wire [9:0] zext_ln109_6_fu_269_p1; +wire [0:0] icmp_ln103_fu_301_p2; +wire [15:0] trunc_ln95_fu_329_p1; +wire [15:0] data_V_fu_378_p1; +wire [0:0] p_Result_s_fu_381_p3; +wire [0:0] icmp_ln99_fu_396_p2; +wire [15:0] quad_0_fu_389_p3; +wire [0:0] icmp_ln99_5_fu_409_p2; +wire [15:0] quad_3_fu_401_p3; +wire [0:0] icmp_ln99_6_fu_422_p2; +wire [15:0] quad_3_31_fu_414_p3; +wire [15:0] quad_3_33_fu_435_p3; +wire [15:0] quad_3_34_fu_443_p3; +wire [15:0] quad_3_36_fu_459_p3; +wire [14:0] tmp_61_fu_503_p3; +wire [15:0] bitcast_ln109_9_fu_526_p1; +wire [15:0] bitcast_ln109_8_fu_522_p1; +wire [15:0] bitcast_ln109_7_fu_518_p1; +wire [15:0] bitcast_ln109_fu_514_p1; +wire ap_CS_fsm_state25; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +end + +td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2 #( + .DataWidth( 16 ), + .AddressRange( 128 ), + .AddressWidth( 7 )) +running_sums_2_U( + .reset(ap_rst), + .clk(ap_clk), + .address0(running_sums_2_addr_reg_604_pp0_iter6_reg), + .ce0(running_sums_2_ce0), + .we0(running_sums_2_we0), + .d0(running_sums_2_d0), + .address1(running_sums_2_address1), + .ce1(running_sums_2_ce1), + .q1(running_sums_2_q1) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U719( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(running_sums_2_load_reg_624), + .din1(val_reg_619), + .dout(grp_fu_219_p2) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U720( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(normalized_reg_665), + .din1(grp_fu_223_p1), + .dout(grp_fu_223_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U721( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_reg_634), + .din1(grp_fu_227_p1), + .dout(grp_fu_227_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U722( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_655), + .din1(grp_fu_231_p1), + .dout(grp_fu_231_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end else if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_285_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ochan_reg_208 <= ochan_1_fu_279_p2; + end else if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ochan_reg_208 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + add_ln109_reg_573 <= add_ln109_fu_273_p2; + write4_read_reg_567 <= write4_dout; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_285_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + and_ln103_reg_610 <= and_ln103_fu_307_p2; + running_sums_2_addr_reg_604 <= zext_ln89_fu_295_p1; + trunc_ln86_reg_587 <= trunc_ln86_fu_291_p1; + zext_ln89_reg_594[7 : 0] <= zext_ln89_fu_295_p1[7 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + and_ln103_reg_610_pp0_iter10_reg <= and_ln103_reg_610_pp0_iter9_reg; + and_ln103_reg_610_pp0_iter11_reg <= and_ln103_reg_610_pp0_iter10_reg; + and_ln103_reg_610_pp0_iter12_reg <= and_ln103_reg_610_pp0_iter11_reg; + and_ln103_reg_610_pp0_iter13_reg <= and_ln103_reg_610_pp0_iter12_reg; + and_ln103_reg_610_pp0_iter14_reg <= and_ln103_reg_610_pp0_iter13_reg; + and_ln103_reg_610_pp0_iter15_reg <= and_ln103_reg_610_pp0_iter14_reg; + and_ln103_reg_610_pp0_iter16_reg <= and_ln103_reg_610_pp0_iter15_reg; + and_ln103_reg_610_pp0_iter17_reg <= and_ln103_reg_610_pp0_iter16_reg; + and_ln103_reg_610_pp0_iter18_reg <= and_ln103_reg_610_pp0_iter17_reg; + and_ln103_reg_610_pp0_iter19_reg <= and_ln103_reg_610_pp0_iter18_reg; + and_ln103_reg_610_pp0_iter20_reg <= and_ln103_reg_610_pp0_iter19_reg; + and_ln103_reg_610_pp0_iter2_reg <= and_ln103_reg_610_pp0_iter1_reg; + and_ln103_reg_610_pp0_iter3_reg <= and_ln103_reg_610_pp0_iter2_reg; + and_ln103_reg_610_pp0_iter4_reg <= and_ln103_reg_610_pp0_iter3_reg; + and_ln103_reg_610_pp0_iter5_reg <= and_ln103_reg_610_pp0_iter4_reg; + and_ln103_reg_610_pp0_iter6_reg <= and_ln103_reg_610_pp0_iter5_reg; + and_ln103_reg_610_pp0_iter7_reg <= and_ln103_reg_610_pp0_iter6_reg; + and_ln103_reg_610_pp0_iter8_reg <= and_ln103_reg_610_pp0_iter7_reg; + and_ln103_reg_610_pp0_iter9_reg <= and_ln103_reg_610_pp0_iter8_reg; + biased_reg_675 <= grp_fu_223_p2; + lshr_ln_reg_614_pp0_iter10_reg <= lshr_ln_reg_614_pp0_iter9_reg; + lshr_ln_reg_614_pp0_iter11_reg <= lshr_ln_reg_614_pp0_iter10_reg; + lshr_ln_reg_614_pp0_iter12_reg <= lshr_ln_reg_614_pp0_iter11_reg; + lshr_ln_reg_614_pp0_iter13_reg <= lshr_ln_reg_614_pp0_iter12_reg; + lshr_ln_reg_614_pp0_iter14_reg <= lshr_ln_reg_614_pp0_iter13_reg; + lshr_ln_reg_614_pp0_iter15_reg <= lshr_ln_reg_614_pp0_iter14_reg; + lshr_ln_reg_614_pp0_iter16_reg <= lshr_ln_reg_614_pp0_iter15_reg; + lshr_ln_reg_614_pp0_iter17_reg <= lshr_ln_reg_614_pp0_iter16_reg; + lshr_ln_reg_614_pp0_iter18_reg <= lshr_ln_reg_614_pp0_iter17_reg; + lshr_ln_reg_614_pp0_iter19_reg <= lshr_ln_reg_614_pp0_iter18_reg; + lshr_ln_reg_614_pp0_iter20_reg <= lshr_ln_reg_614_pp0_iter19_reg; + lshr_ln_reg_614_pp0_iter2_reg <= lshr_ln_reg_614_pp0_iter1_reg; + lshr_ln_reg_614_pp0_iter3_reg <= lshr_ln_reg_614_pp0_iter2_reg; + lshr_ln_reg_614_pp0_iter4_reg <= lshr_ln_reg_614_pp0_iter3_reg; + lshr_ln_reg_614_pp0_iter5_reg <= lshr_ln_reg_614_pp0_iter4_reg; + lshr_ln_reg_614_pp0_iter6_reg <= lshr_ln_reg_614_pp0_iter5_reg; + lshr_ln_reg_614_pp0_iter7_reg <= lshr_ln_reg_614_pp0_iter6_reg; + lshr_ln_reg_614_pp0_iter8_reg <= lshr_ln_reg_614_pp0_iter7_reg; + lshr_ln_reg_614_pp0_iter9_reg <= lshr_ln_reg_614_pp0_iter8_reg; + normalized_reg_665 <= grp_fu_231_p2; + running_sums_2_addr_reg_604_pp0_iter2_reg <= running_sums_2_addr_reg_604_pp0_iter1_reg; + running_sums_2_addr_reg_604_pp0_iter3_reg <= running_sums_2_addr_reg_604_pp0_iter2_reg; + running_sums_2_addr_reg_604_pp0_iter4_reg <= running_sums_2_addr_reg_604_pp0_iter3_reg; + running_sums_2_addr_reg_604_pp0_iter5_reg <= running_sums_2_addr_reg_604_pp0_iter4_reg; + running_sums_2_addr_reg_604_pp0_iter6_reg <= running_sums_2_addr_reg_604_pp0_iter5_reg; + sub_i_i_i_reg_655 <= grp_fu_227_p2; + sum_reg_634 <= grp_fu_219_p2; + tmp_90_i_i_reg_645 <= {{l2_adjustments_q0[31:16]}}; + tmp_90_i_i_reg_645_pp0_iter10_reg <= tmp_90_i_i_reg_645_pp0_iter9_reg; + tmp_90_i_i_reg_645_pp0_iter11_reg <= tmp_90_i_i_reg_645_pp0_iter10_reg; + tmp_90_i_i_reg_645_pp0_iter8_reg <= tmp_90_i_i_reg_645; + tmp_90_i_i_reg_645_pp0_iter9_reg <= tmp_90_i_i_reg_645_pp0_iter8_reg; + tmp_91_i_i_reg_650 <= {{l2_adjustments_q0[47:32]}}; + tmp_91_i_i_reg_650_pp0_iter10_reg <= tmp_91_i_i_reg_650_pp0_iter9_reg; + tmp_91_i_i_reg_650_pp0_iter11_reg <= tmp_91_i_i_reg_650_pp0_iter10_reg; + tmp_91_i_i_reg_650_pp0_iter12_reg <= tmp_91_i_i_reg_650_pp0_iter11_reg; + tmp_91_i_i_reg_650_pp0_iter13_reg <= tmp_91_i_i_reg_650_pp0_iter12_reg; + tmp_91_i_i_reg_650_pp0_iter14_reg <= tmp_91_i_i_reg_650_pp0_iter13_reg; + tmp_91_i_i_reg_650_pp0_iter15_reg <= tmp_91_i_i_reg_650_pp0_iter14_reg; + tmp_91_i_i_reg_650_pp0_iter8_reg <= tmp_91_i_i_reg_650; + tmp_91_i_i_reg_650_pp0_iter9_reg <= tmp_91_i_i_reg_650_pp0_iter8_reg; + trunc_ln86_reg_587_pp0_iter10_reg <= trunc_ln86_reg_587_pp0_iter9_reg; + trunc_ln86_reg_587_pp0_iter11_reg <= trunc_ln86_reg_587_pp0_iter10_reg; + trunc_ln86_reg_587_pp0_iter12_reg <= trunc_ln86_reg_587_pp0_iter11_reg; + trunc_ln86_reg_587_pp0_iter13_reg <= trunc_ln86_reg_587_pp0_iter12_reg; + trunc_ln86_reg_587_pp0_iter14_reg <= trunc_ln86_reg_587_pp0_iter13_reg; + trunc_ln86_reg_587_pp0_iter15_reg <= trunc_ln86_reg_587_pp0_iter14_reg; + trunc_ln86_reg_587_pp0_iter16_reg <= trunc_ln86_reg_587_pp0_iter15_reg; + trunc_ln86_reg_587_pp0_iter17_reg <= trunc_ln86_reg_587_pp0_iter16_reg; + trunc_ln86_reg_587_pp0_iter18_reg <= trunc_ln86_reg_587_pp0_iter17_reg; + trunc_ln86_reg_587_pp0_iter19_reg <= trunc_ln86_reg_587_pp0_iter18_reg; + trunc_ln86_reg_587_pp0_iter20_reg <= trunc_ln86_reg_587_pp0_iter19_reg; + trunc_ln86_reg_587_pp0_iter2_reg <= trunc_ln86_reg_587_pp0_iter1_reg; + trunc_ln86_reg_587_pp0_iter3_reg <= trunc_ln86_reg_587_pp0_iter2_reg; + trunc_ln86_reg_587_pp0_iter4_reg <= trunc_ln86_reg_587_pp0_iter3_reg; + trunc_ln86_reg_587_pp0_iter5_reg <= trunc_ln86_reg_587_pp0_iter4_reg; + trunc_ln86_reg_587_pp0_iter6_reg <= trunc_ln86_reg_587_pp0_iter5_reg; + trunc_ln86_reg_587_pp0_iter7_reg <= trunc_ln86_reg_587_pp0_iter6_reg; + trunc_ln86_reg_587_pp0_iter8_reg <= trunc_ln86_reg_587_pp0_iter7_reg; + trunc_ln86_reg_587_pp0_iter9_reg <= trunc_ln86_reg_587_pp0_iter8_reg; + zext_ln89_reg_594_pp0_iter2_reg[7 : 0] <= zext_ln89_reg_594_pp0_iter1_reg[7 : 0]; + zext_ln89_reg_594_pp0_iter3_reg[7 : 0] <= zext_ln89_reg_594_pp0_iter2_reg[7 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + and_ln103_reg_610_pp0_iter1_reg <= and_ln103_reg_610; + lshr_ln_reg_614_pp0_iter1_reg <= lshr_ln_reg_614; + running_sums_2_addr_reg_604_pp0_iter1_reg <= running_sums_2_addr_reg_604; + trunc_ln86_reg_587_pp0_iter1_reg <= trunc_ln86_reg_587; + val_reg_619 <= l2_partial_sums_q0; + zext_ln89_reg_594_pp0_iter1_reg[7 : 0] <= zext_ln89_reg_594[7 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((1'd1 == and_ln103_fu_307_p2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_285_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + lshr_ln_reg_614 <= {{ochan_reg_208[6:2]}}; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + quad_3_26_fu_118 <= quad_3_37_fu_467_p3; + quad_3_27_fu_114 <= quad_3_38_fu_475_p3; + quad_3_28_fu_122 <= quad_3_35_fu_451_p3; + quad_3_29_fu_126 <= quad_3_32_fu_427_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_2_load_reg_624 <= running_sums_2_q1; + end +end + +always @ (*) begin + if ((icmp_ln86_fu_285_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter6 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter5 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter4 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + l2_adjustments_ce0 = 1'b1; + end else begin + l2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_partial_sums_ce0 = 1'b1; + end else begin + l2_partial_sums_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter22 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter21 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (1'd1 == and_ln103_reg_610_pp0_iter20_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_2_ce0 = 1'b1; + end else begin + running_sums_2_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_2_ce1 = 1'b1; + end else begin + running_sums_2_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_2_we0 = 1'b1; + end else begin + running_sums_2_we0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write4_blk_n = write4_empty_n; + end else begin + write4_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write4_read = 1'b1; + end else begin + write4_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln86_fu_285_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((ap_enable_reg_pp0_iter22 == 1'b1) & (ap_enable_reg_pp0_iter21 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln86_fu_285_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter22 == 1'b1) & (ap_enable_reg_pp0_iter21 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_state25; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state25 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln109_fu_273_p2 = ((sub_ln109_cast_fu_265_p1) + (zext_ln109_6_fu_269_p1)); + +assign and_ln103_fu_307_p2 = (write4_read_reg_567 & icmp_ln103_fu_301_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state25 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln109_7_fu_518_p1 = quad_3_37_fu_467_p3; + +assign bitcast_ln109_8_fu_522_p1 = quad_3_35_fu_451_p3; + +assign bitcast_ln109_9_fu_526_p1 = quad_3_32_fu_427_p3; + +assign bitcast_ln109_fu_514_p1 = quad_3_38_fu_475_p3; + +assign data_V_fu_378_p1 = biased_reg_675; + +assign grp_fu_223_p1 = tmp_91_i_i_reg_650_pp0_iter15_reg; + +assign grp_fu_227_p1 = trunc_ln95_fu_329_p1; + +assign grp_fu_231_p1 = tmp_90_i_i_reg_645_pp0_iter11_reg; + +assign icmp_ln103_fu_301_p2 = ((trunc_ln86_fu_291_p1 == 2'd3) ? 1'b1 : 1'b0); + +assign icmp_ln86_fu_285_p2 = ((ochan_reg_208 == 8'd128) ? 1'b1 : 1'b0); + +assign icmp_ln99_5_fu_409_p2 = ((trunc_ln86_reg_587_pp0_iter20_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln99_6_fu_422_p2 = ((trunc_ln86_reg_587_pp0_iter20_reg == 2'd0) ? 1'b1 : 1'b0); + +assign icmp_ln99_fu_396_p2 = ((trunc_ln86_reg_587_pp0_iter20_reg == 2'd2) ? 1'b1 : 1'b0); + +assign l2_adjustments_address0 = zext_ln89_reg_594_pp0_iter3_reg; + +assign l2_partial_sums_address0 = zext_ln89_fu_295_p1; + +assign ochan_1_fu_279_p2 = (ochan_reg_208 + 8'd1); + +assign out_data_address1 = sext_ln109_fu_509_p1; + +assign out_data_d1 = {{{{bitcast_ln109_9_fu_526_p1}, {bitcast_ln109_8_fu_522_p1}}, {bitcast_ln109_7_fu_518_p1}}, {bitcast_ln109_fu_514_p1}}; + +assign p_Result_s_fu_381_p3 = data_V_fu_378_p1[32'd15]; + +assign quad_0_fu_389_p3 = ((p_Result_s_fu_381_p3[0:0] == 1'b1) ? 16'd0 : biased_reg_675); + +assign quad_3_31_fu_414_p3 = ((icmp_ln99_5_fu_409_p2[0:0] == 1'b1) ? quad_3_29_fu_126 : quad_3_fu_401_p3); + +assign quad_3_32_fu_427_p3 = ((icmp_ln99_6_fu_422_p2[0:0] == 1'b1) ? quad_3_29_fu_126 : quad_3_31_fu_414_p3); + +assign quad_3_33_fu_435_p3 = ((icmp_ln99_fu_396_p2[0:0] == 1'b1) ? quad_0_fu_389_p3 : quad_3_28_fu_122); + +assign quad_3_34_fu_443_p3 = ((icmp_ln99_5_fu_409_p2[0:0] == 1'b1) ? quad_3_28_fu_122 : quad_3_33_fu_435_p3); + +assign quad_3_35_fu_451_p3 = ((icmp_ln99_6_fu_422_p2[0:0] == 1'b1) ? quad_3_28_fu_122 : quad_3_34_fu_443_p3); + +assign quad_3_36_fu_459_p3 = ((icmp_ln99_5_fu_409_p2[0:0] == 1'b1) ? quad_0_fu_389_p3 : quad_3_26_fu_118); + +assign quad_3_37_fu_467_p3 = ((icmp_ln99_6_fu_422_p2[0:0] == 1'b1) ? quad_3_26_fu_118 : quad_3_36_fu_459_p3); + +assign quad_3_38_fu_475_p3 = ((icmp_ln99_6_fu_422_p2[0:0] == 1'b1) ? quad_0_fu_389_p3 : quad_3_27_fu_114); + +assign quad_3_fu_401_p3 = ((icmp_ln99_fu_396_p2[0:0] == 1'b1) ? quad_3_29_fu_126 : quad_0_fu_389_p3); + +assign running_sums_2_address1 = zext_ln89_fu_295_p1; + +assign running_sums_2_d0 = ((write4_read_reg_567[0:0] == 1'b1) ? 16'd0 : sum_reg_634); + +assign sext_ln109_fu_509_p1 = (tmp_61_fu_503_p3); + +assign sub_ln109_cast_fu_265_p1 = (sub_ln109_fu_259_p2); + +assign sub_ln109_fu_259_p2 = (zext_ln109_fu_243_p1 - zext_ln109_5_fu_255_p1); + +assign tmp_61_fu_503_p3 = {{add_ln109_reg_573}, {lshr_ln_reg_614_pp0_iter20_reg}}; + +assign tmp_fu_235_p3 = {{indices_01_dout}, {4'd0}}; + +assign tmp_s_fu_247_p3 = {{indices_01_dout}, {1'd0}}; + +assign trunc_ln86_fu_291_p1 = ochan_reg_208[1:0]; + +assign trunc_ln95_fu_329_p1 = l2_adjustments_q0[15:0]; + +assign zext_ln109_5_fu_255_p1 = tmp_s_fu_247_p3; + +assign zext_ln109_6_fu_269_p1 = indices_12_dout; + +assign zext_ln109_fu_243_p1 = tmp_fu_235_p3; + +assign zext_ln89_fu_295_p1 = ochan_reg_208; + +always @ (posedge ap_clk) begin + zext_ln89_reg_594[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + zext_ln89_reg_594_pp0_iter1_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + zext_ln89_reg_594_pp0_iter2_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + zext_ln89_reg_594_pp0_iter3_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf11_l2_writeOutputs_171 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_readFilters74 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_we0, + weight_vecs_0_d0, + weight_vecs_0_address1, + weight_vecs_0_ce1, + weight_vecs_0_we1, + weight_vecs_0_d1 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_pp0_stage0 = 4'd2; +parameter ap_ST_fsm_pp0_stage1 = 4'd4; +parameter ap_ST_fsm_state7 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [16:0] filter_data_address0; +output filter_data_ce0; +input [63:0] filter_data_q0; +input [8:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [9:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +output weight_vecs_0_we0; +output [15:0] weight_vecs_0_d0; +output [9:0] weight_vecs_0_address1; +output weight_vecs_0_ce1; +output weight_vecs_0_we1; +output [15:0] weight_vecs_0_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg indices_23_read; +reg[9:0] weight_vecs_0_address0; +reg weight_vecs_0_ce0; +reg weight_vecs_0_we0; +reg[15:0] weight_vecs_0_d0; +reg[9:0] weight_vecs_0_address1; +reg weight_vecs_0_ce1; +reg weight_vecs_0_we1; +reg[15:0] weight_vecs_0_d1; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [7:0] indvar_flatten13_reg_174; +reg [1:0] ii_reg_185; +reg [6:0] indvar_flatten_reg_196; +reg [1:0] jj_reg_207; +reg [6:0] kk_0_i_i_reg_218; +wire [12:0] sext_ln47_fu_251_p1; +reg [12:0] sext_ln47_reg_583; +wire [7:0] add_ln47_7_fu_255_p2; +reg [7:0] add_ln47_7_reg_588; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state4_pp0_stage0_iter1; +wire ap_block_state6_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln47_fu_261_p2; +reg [0:0] icmp_ln47_reg_593; +reg [0:0] icmp_ln47_reg_593_pp0_iter1_reg; +wire [0:0] icmp_ln48_fu_273_p2; +reg [0:0] icmp_ln48_reg_597; +wire [1:0] select_ln47_7_fu_287_p3; +reg [1:0] select_ln47_7_reg_602; +wire [6:0] select_ln48_fu_356_p3; +reg [6:0] select_ln48_reg_609; +wire [1:0] select_ln48_13_fu_364_p3; +reg [1:0] select_ln48_13_reg_615; +wire [5:0] empty_138_fu_382_p1; +reg [5:0] empty_138_reg_621; +reg [5:0] empty_138_reg_621_pp0_iter1_reg; +wire [6:0] add_ln48_7_fu_405_p2; +reg [6:0] add_ln48_7_reg_633; +wire [6:0] add_ln49_fu_411_p2; +reg [6:0] add_ln49_reg_638; +wire ap_CS_fsm_pp0_stage1; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state5_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +wire [6:0] select_ln48_14_fu_416_p3; +reg [6:0] select_ln48_14_reg_643; +wire [5:0] add_ln55_26_fu_449_p2; +reg [5:0] add_ln55_26_reg_648; +wire [9:0] add_ln55_27_fu_470_p2; +reg [9:0] add_ln55_27_reg_655; +reg [15:0] tmp_88_i_i_reg_660; +reg [15:0] tmp_89_i_i_reg_665; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +wire ap_block_pp0_stage1_subdone; +reg ap_enable_reg_pp0_iter2; +reg [7:0] ap_phi_mux_indvar_flatten13_phi_fu_178_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_189_p4; +reg [6:0] ap_phi_mux_indvar_flatten_phi_fu_200_p4; +reg [1:0] ap_phi_mux_jj_phi_fu_211_p4; +reg [6:0] ap_phi_mux_kk_0_i_i_phi_fu_222_p4; +wire [63:0] tmp_17_fu_396_p3; +wire [63:0] zext_ln55_67_fu_476_p1; +wire ap_block_pp0_stage1; +wire [63:0] sext_ln55_3_fu_501_p1; +wire [63:0] sext_ln55_4_fu_553_p1; +wire [63:0] sext_ln55_5_fu_574_p1; +wire [15:0] bitcast_ln55_fu_484_p1; +wire [15:0] bitcast_ln55_1_fu_516_p1; +wire [15:0] bitcast_ln55_2_fu_558_p1; +wire [15:0] bitcast_ln55_3_fu_579_p1; +wire [10:0] tmp_fu_233_p3; +wire [11:0] zext_ln55_60_fu_241_p1; +wire [11:0] zext_ln55_fu_229_p1; +wire [11:0] sub_ln55_fu_245_p2; +wire [1:0] add_ln47_fu_267_p2; +wire [12:0] zext_ln55_62_fu_295_p1; +wire [12:0] add_ln55_fu_299_p2; +wire [14:0] tmp_56_fu_308_p3; +wire [59:0] sext_ln55_2_fu_316_p1; +wire [59:0] sext_ln55_fu_304_p1; +wire [0:0] icmp_ln49_fu_332_p2; +wire [0:0] xor_ln47_fu_326_p2; +wire [1:0] select_ln47_fu_279_p3; +wire [0:0] and_ln47_fu_338_p2; +wire [0:0] or_ln48_fu_350_p2; +wire [1:0] add_ln48_fu_344_p2; +wire [59:0] sub_ln55_15_fu_320_p2; +wire [59:0] zext_ln55_65_fu_372_p1; +wire [59:0] add_ln55_25_fu_376_p2; +wire [3:0] lshr_ln_fu_386_p4; +wire [3:0] tmp_s_fu_425_p3; +wire [4:0] zext_ln55_63_fu_432_p1; +wire [4:0] zext_ln55_61_fu_422_p1; +wire [4:0] sub_ln55_16_fu_436_p2; +wire [5:0] sext_ln48_fu_442_p1; +wire [5:0] zext_ln55_64_fu_446_p1; +wire [3:0] trunc_ln55_fu_455_p1; +wire [9:0] tmp_166_cast_fu_459_p3; +wire [9:0] zext_ln55_66_fu_467_p1; +wire [15:0] trunc_ln55_4_fu_480_p1; +wire [5:0] or_ln49_fu_489_p2; +wire [11:0] tmp_57_fu_494_p3; +wire [15:0] tmp_87_i_i_fu_506_p4; +wire [5:0] or_ln49_1_fu_541_p2; +wire [11:0] tmp_58_fu_546_p3; +wire [5:0] or_ln49_2_fu_562_p2; +wire [11:0] tmp_59_fu_567_p3; +wire ap_CS_fsm_state7; +reg [3:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ii_reg_185 <= select_ln47_7_reg_602; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_185 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + indvar_flatten13_reg_174 <= add_ln47_7_reg_588; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_174 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + indvar_flatten_reg_196 <= select_ln48_14_reg_643; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_196 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_207 <= select_ln48_13_reg_615; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_207 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_i_i_reg_218 <= add_ln49_reg_638; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_0_i_i_reg_218 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln47_7_reg_588 <= add_ln47_7_fu_255_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_261_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln48_7_reg_633 <= add_ln48_7_fu_405_p2; + empty_138_reg_621 <= empty_138_fu_382_p1; + icmp_ln48_reg_597 <= icmp_ln48_fu_273_p2; + select_ln48_reg_609 <= select_ln48_fu_356_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + add_ln49_reg_638 <= add_ln49_fu_411_p2; + select_ln48_14_reg_643 <= select_ln48_14_fu_416_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln55_26_reg_648 <= add_ln55_26_fu_449_p2; + add_ln55_27_reg_655 <= add_ln55_27_fu_470_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + empty_138_reg_621_pp0_iter1_reg <= empty_138_reg_621; + icmp_ln47_reg_593 <= icmp_ln47_fu_261_p2; + icmp_ln47_reg_593_pp0_iter1_reg <= icmp_ln47_reg_593; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_261_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln47_7_reg_602 <= select_ln47_7_fu_287_p3; + select_ln48_13_reg_615 <= select_ln48_13_fu_364_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sext_ln47_reg_583 <= sext_ln47_fu_251_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_593_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + tmp_88_i_i_reg_660 <= {{filter_data_q0[47:32]}}; + tmp_89_i_i_reg_665 <= {{filter_data_q0[63:48]}}; + end +end + +always @ (*) begin + if ((icmp_ln47_fu_261_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_189_p4 = select_ln47_7_reg_602; + end else begin + ap_phi_mux_ii_phi_fu_189_p4 = ii_reg_185; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_indvar_flatten13_phi_fu_178_p4 = add_ln47_7_reg_588; + end else begin + ap_phi_mux_indvar_flatten13_phi_fu_178_p4 = indvar_flatten13_reg_174; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_indvar_flatten_phi_fu_200_p4 = select_ln48_14_reg_643; + end else begin + ap_phi_mux_indvar_flatten_phi_fu_200_p4 = indvar_flatten_reg_196; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_211_p4 = select_ln48_13_reg_615; + end else begin + ap_phi_mux_jj_phi_fu_211_p4 = jj_reg_207; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_593 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_i_i_phi_fu_222_p4 = add_ln49_reg_638; + end else begin + ap_phi_mux_kk_0_i_i_phi_fu_222_p4 = kk_0_i_i_reg_218; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + weight_vecs_0_address0 = sext_ln55_5_fu_574_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_address0 = sext_ln55_3_fu_501_p1; + end else begin + weight_vecs_0_address0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + weight_vecs_0_address1 = sext_ln55_4_fu_553_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_address1 = zext_ln55_67_fu_476_p1; + end else begin + weight_vecs_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + weight_vecs_0_ce1 = 1'b1; + end else begin + weight_vecs_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + weight_vecs_0_d0 = bitcast_ln55_3_fu_579_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_d0 = bitcast_ln55_1_fu_516_p1; + end else begin + weight_vecs_0_d0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + weight_vecs_0_d1 = bitcast_ln55_2_fu_558_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_d1 = bitcast_ln55_fu_484_p1; + end else begin + weight_vecs_0_d1 = 'bx; + end +end + +always @ (*) begin + if ((((icmp_ln47_reg_593_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((icmp_ln47_reg_593_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + weight_vecs_0_we0 = 1'b1; + end else begin + weight_vecs_0_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((icmp_ln47_reg_593_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((icmp_ln47_reg_593_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + weight_vecs_0_we1 = 1'b1; + end else begin + weight_vecs_0_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln47_fu_261_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if ((((icmp_ln47_fu_261_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln47_7_fu_255_p2 = (ap_phi_mux_indvar_flatten13_phi_fu_178_p4 + 8'd1); + +assign add_ln47_fu_267_p2 = (ap_phi_mux_ii_phi_fu_189_p4 + 2'd1); + +assign add_ln48_7_fu_405_p2 = (ap_phi_mux_indvar_flatten_phi_fu_200_p4 + 7'd1); + +assign add_ln48_fu_344_p2 = (select_ln47_fu_279_p3 + 2'd1); + +assign add_ln49_fu_411_p2 = (select_ln48_reg_609 + 7'd4); + +assign add_ln55_25_fu_376_p2 = (sub_ln55_15_fu_320_p2 + zext_ln55_65_fu_372_p1); + +assign add_ln55_26_fu_449_p2 = ((sext_ln48_fu_442_p1) + (zext_ln55_64_fu_446_p1)); + +assign add_ln55_27_fu_470_p2 = (tmp_166_cast_fu_459_p3 + zext_ln55_66_fu_467_p1); + +assign add_ln55_fu_299_p2 = ((sext_ln47_reg_583) + (zext_ln55_62_fu_295_p1)); + +assign and_ln47_fu_338_p2 = (xor_ln47_fu_326_p2 & icmp_ln49_fu_332_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd3]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln55_1_fu_516_p1 = tmp_87_i_i_fu_506_p4; + +assign bitcast_ln55_2_fu_558_p1 = tmp_88_i_i_reg_660; + +assign bitcast_ln55_3_fu_579_p1 = tmp_89_i_i_reg_665; + +assign bitcast_ln55_fu_484_p1 = trunc_ln55_4_fu_480_p1; + +assign empty_138_fu_382_p1 = select_ln48_fu_356_p3[5:0]; + +assign filter_data_address0 = tmp_17_fu_396_p3; + +assign icmp_ln47_fu_261_p2 = ((ap_phi_mux_indvar_flatten13_phi_fu_178_p4 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln48_fu_273_p2 = ((ap_phi_mux_indvar_flatten_phi_fu_200_p4 == 7'd48) ? 1'b1 : 1'b0); + +assign icmp_ln49_fu_332_p2 = ((ap_phi_mux_kk_0_i_i_phi_fu_222_p4 == 7'd64) ? 1'b1 : 1'b0); + +assign lshr_ln_fu_386_p4 = {{select_ln48_fu_356_p3[5:2]}}; + +assign or_ln48_fu_350_p2 = (icmp_ln48_fu_273_p2 | and_ln47_fu_338_p2); + +assign or_ln49_1_fu_541_p2 = (empty_138_reg_621_pp0_iter1_reg | 6'd2); + +assign or_ln49_2_fu_562_p2 = (empty_138_reg_621_pp0_iter1_reg | 6'd3); + +assign or_ln49_fu_489_p2 = (empty_138_reg_621_pp0_iter1_reg | 6'd1); + +assign select_ln47_7_fu_287_p3 = ((icmp_ln48_fu_273_p2[0:0] == 1'b1) ? add_ln47_fu_267_p2 : ap_phi_mux_ii_phi_fu_189_p4); + +assign select_ln47_fu_279_p3 = ((icmp_ln48_fu_273_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_211_p4); + +assign select_ln48_13_fu_364_p3 = ((and_ln47_fu_338_p2[0:0] == 1'b1) ? add_ln48_fu_344_p2 : select_ln47_fu_279_p3); + +assign select_ln48_14_fu_416_p3 = ((icmp_ln48_reg_597[0:0] == 1'b1) ? 7'd1 : add_ln48_7_reg_633); + +assign select_ln48_fu_356_p3 = ((or_ln48_fu_350_p2[0:0] == 1'b1) ? 7'd0 : ap_phi_mux_kk_0_i_i_phi_fu_222_p4); + +assign sext_ln47_fu_251_p1 = (sub_ln55_fu_245_p2); + +assign sext_ln48_fu_442_p1 = (sub_ln55_16_fu_436_p2); + +assign sext_ln55_2_fu_316_p1 = (tmp_56_fu_308_p3); + +assign sext_ln55_3_fu_501_p1 = (tmp_57_fu_494_p3); + +assign sext_ln55_4_fu_553_p1 = (tmp_58_fu_546_p3); + +assign sext_ln55_5_fu_574_p1 = (tmp_59_fu_567_p3); + +assign sext_ln55_fu_304_p1 = add_ln55_fu_299_p2; + +assign sub_ln55_15_fu_320_p2 = ((sext_ln55_2_fu_316_p1) - (sext_ln55_fu_304_p1)); + +assign sub_ln55_16_fu_436_p2 = (zext_ln55_63_fu_432_p1 - zext_ln55_61_fu_422_p1); + +assign sub_ln55_fu_245_p2 = (zext_ln55_60_fu_241_p1 - zext_ln55_fu_229_p1); + +assign tmp_166_cast_fu_459_p3 = {{trunc_ln55_fu_455_p1}, {6'd0}}; + +assign tmp_17_fu_396_p3 = {{add_ln55_25_fu_376_p2}, {lshr_ln_fu_386_p4}}; + +assign tmp_56_fu_308_p3 = {{add_ln55_fu_299_p2}, {2'd0}}; + +assign tmp_57_fu_494_p3 = {{add_ln55_26_reg_648}, {or_ln49_fu_489_p2}}; + +assign tmp_58_fu_546_p3 = {{add_ln55_26_reg_648}, {or_ln49_1_fu_541_p2}}; + +assign tmp_59_fu_567_p3 = {{add_ln55_26_reg_648}, {or_ln49_2_fu_562_p2}}; + +assign tmp_87_i_i_fu_506_p4 = {{filter_data_q0[31:16]}}; + +assign tmp_fu_233_p3 = {{indices_23_dout}, {2'd0}}; + +assign tmp_s_fu_425_p3 = {{select_ln47_7_reg_602}, {2'd0}}; + +assign trunc_ln55_4_fu_480_p1 = filter_data_q0[15:0]; + +assign trunc_ln55_fu_455_p1 = add_ln55_26_fu_449_p2[3:0]; + +assign xor_ln47_fu_326_p2 = (icmp_ln48_fu_273_p2 ^ 1'd1); + +assign zext_ln55_60_fu_241_p1 = tmp_fu_233_p3; + +assign zext_ln55_61_fu_422_p1 = select_ln47_7_reg_602; + +assign zext_ln55_62_fu_295_p1 = select_ln47_7_fu_287_p3; + +assign zext_ln55_63_fu_432_p1 = tmp_s_fu_425_p3; + +assign zext_ln55_64_fu_446_p1 = select_ln48_13_reg_615; + +assign zext_ln55_65_fu_372_p1 = select_ln48_13_fu_364_p3; + +assign zext_ln55_66_fu_467_p1 = select_ln48_reg_609; + +assign zext_ln55_67_fu_476_p1 = add_ln55_27_reg_655; + +assign zext_ln55_fu_229_p1 = indices_23_dout; + +endmodule //td_fused_top_tdf11_readFilters74 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf11_readInputs75 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_we0, + ifmap_vec_d0, + ifmap_vec_address1, + ifmap_vec_ce1, + ifmap_vec_we1, + ifmap_vec_d1, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 5'd1; +parameter ap_ST_fsm_state2 = 5'd2; +parameter ap_ST_fsm_pp0_stage0 = 5'd4; +parameter ap_ST_fsm_pp0_stage1 = 5'd8; +parameter ap_ST_fsm_state9 = 5'd16; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [11:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [9:0] ifmap_vec_address0; +output ifmap_vec_ce0; +output ifmap_vec_we0; +output [15:0] ifmap_vec_d0; +output [9:0] ifmap_vec_address1; +output ifmap_vec_ce1; +output ifmap_vec_we1; +output [15:0] ifmap_vec_d1; +output [3:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [7:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg[9:0] ifmap_vec_address0; +reg ifmap_vec_ce0; +reg ifmap_vec_we0; +reg[15:0] ifmap_vec_d0; +reg[9:0] ifmap_vec_address1; +reg ifmap_vec_ce1; +reg ifmap_vec_we1; +reg[15:0] ifmap_vec_d1; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [4:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [7:0] indvar_flatten47_reg_224; +reg [1:0] ii_reg_236; +reg [6:0] indvar_flatten_reg_248; +reg [1:0] jj_reg_259; +reg [6:0] kk_0_i_i_reg_271; +reg [15:0] indices_01_read_reg_960; +wire [3:0] trunc_ln250_fu_282_p1; +reg [3:0] trunc_ln250_reg_965; +reg [15:0] indices_12_read_reg_970; +wire [7:0] empty_fu_287_p1; +reg [7:0] empty_reg_975; +wire [17:0] p_cast_i_i_fu_304_p1; +reg [17:0] p_cast_i_i_reg_982; +wire ap_CS_fsm_state2; +wire [17:0] sext_ln22_fu_314_p1; +reg [17:0] sext_ln22_reg_988; +wire [3:0] p_cast_fu_318_p2; +reg [3:0] p_cast_reg_994; +wire [0:0] or_ln23_31_fu_337_p2; +reg [0:0] or_ln23_31_reg_1000; +wire [7:0] p_mid137_fu_343_p2; +reg [7:0] p_mid137_reg_1005; +wire [3:0] p_cast5_i_i_fu_361_p2; +reg [3:0] p_cast5_i_i_reg_1010; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state5_pp0_stage0_iter1; +wire ap_block_state7_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [0:0] is_padding_fu_401_p2; +reg [0:0] is_padding_reg_1016; +wire [0:0] icmp_ln19_fu_407_p2; +reg [0:0] icmp_ln19_reg_1023; +reg [0:0] icmp_ln19_reg_1023_pp0_iter1_reg; +reg [0:0] icmp_ln19_reg_1023_pp0_iter2_reg; +wire [1:0] add_ln19_fu_413_p2; +reg [1:0] add_ln19_reg_1027; +wire [0:0] icmp_ln20_fu_419_p2; +reg [0:0] icmp_ln20_reg_1033; +wire [1:0] select_ln19_fu_425_p3; +reg [1:0] select_ln19_reg_1045; +wire [0:0] or_ln23_33_fu_456_p2; +reg [0:0] or_ln23_33_reg_1050; +wire [1:0] add_ln20_fu_461_p2; +reg [1:0] add_ln20_reg_1057; +wire [0:0] or_ln23_35_fu_496_p2; +reg [0:0] or_ln23_35_reg_1063; +wire [6:0] add_ln20_7_fu_502_p2; +reg [6:0] add_ln20_7_reg_1070; +wire [7:0] add_ln19_7_fu_508_p2; +reg [7:0] add_ln19_7_reg_1075; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state4_pp0_stage1_iter0; +wire ap_block_state6_pp0_stage1_iter1; +wire ap_block_state8_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +wire [1:0] select_ln19_36_fu_546_p3; +reg [1:0] select_ln19_36_reg_1080; +wire [6:0] select_ln20_fu_620_p3; +reg [6:0] select_ln20_reg_1087; +wire [1:0] select_ln20_30_fu_628_p3; +reg [1:0] select_ln20_30_reg_1093; +wire [0:0] select_ln20_31_fu_637_p3; +reg [0:0] select_ln20_31_reg_1099; +reg [0:0] select_ln20_31_reg_1099_pp0_iter1_reg; +wire [5:0] empty_137_fu_733_p1; +reg [5:0] empty_137_reg_1107; +reg [5:0] empty_137_reg_1107_pp0_iter1_reg; +wire [6:0] select_ln20_34_fu_760_p3; +reg [6:0] select_ln20_34_reg_1119; +wire [6:0] add_ln25_fu_766_p2; +reg [6:0] add_ln25_reg_1124; +reg ap_enable_reg_pp0_iter1; +wire [5:0] add_ln33_fu_798_p2; +reg [5:0] add_ln33_reg_1129; +wire [9:0] add_ln33_7_fu_819_p2; +reg [9:0] add_ln33_7_reg_1136; +wire [15:0] select_ln33_29_fu_898_p3; +reg [15:0] select_ln33_29_reg_1141; +wire [15:0] select_ln33_30_fu_919_p3; +reg [15:0] select_ln33_30_reg_1146; +wire ap_block_pp0_stage1_subdone; +reg ap_condition_pp0_exit_iter0_state4; +reg ap_enable_reg_pp0_iter2; +reg [7:0] ap_phi_mux_indvar_flatten47_phi_fu_228_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_240_p4; +reg [6:0] ap_phi_mux_indvar_flatten_phi_fu_252_p4; +reg [1:0] ap_phi_mux_jj_phi_fu_263_p4; +reg [6:0] ap_phi_mux_kk_0_i_i_phi_fu_275_p4; +wire ap_block_pp0_stage1; +wire [63:0] sext_ln32_fu_755_p1; +wire [63:0] zext_ln33_29_fu_825_p1; +wire [63:0] sext_ln33_fu_857_p1; +wire [63:0] sext_ln33_11_fu_938_p1; +wire [63:0] sext_ln33_12_fu_955_p1; +reg ap_block_state1; +wire [15:0] select_ln33_fu_837_p3; +wire [15:0] select_ln33_28_fu_876_p3; +wire [16:0] zext_ln19_fu_295_p1; +wire [16:0] empty_132_fu_298_p2; +wire [16:0] j_cast_i_i_fu_292_p1; +wire [16:0] add_ln22_fu_308_p2; +wire [0:0] tmp_49_fu_323_p3; +wire [0:0] icmp_ln24_fu_331_p2; +wire [17:0] ii_cast_i_i_fu_348_p1; +wire [3:0] ii_cast_fu_352_p1; +wire [17:0] empty_133_fu_356_p2; +wire [17:0] zext_ln20_fu_372_p1; +wire [17:0] add_ln22_7_fu_376_p2; +wire [0:0] tmp_50_fu_381_p3; +wire [0:0] icmp_ln24_7_fu_389_p2; +wire [0:0] or_ln23_fu_395_p2; +wire [0:0] empty_134_fu_366_p2; +wire [17:0] ii_cast_i_i_mid1_fu_433_p1; +wire [17:0] p_mid111_fu_437_p2; +wire [0:0] p_mid113_fu_442_p2; +wire [17:0] zext_ln20_7_fu_467_p1; +wire [17:0] add_ln22_8_fu_471_p2; +wire [0:0] tmp_51_fu_476_p3; +wire [0:0] icmp_ln24_8_fu_484_p2; +wire [0:0] or_ln23_34_fu_490_p2; +wire [0:0] select_ln19_38_fu_448_p3; +wire [2:0] zext_ln22_fu_514_p1; +wire [2:0] tmp1_fu_524_p2; +wire [7:0] tmp1_cast_fu_530_p1; +wire [7:0] empty_135_fu_534_p2; +wire [3:0] ii_cast_mid1_fu_552_p1; +wire [3:0] p_cast5_i_i_mid1_fu_555_p2; +wire [3:0] row_coord_int_mid131_fu_571_p3; +wire [3:0] row_coord_int_fu_518_p3; +wire [7:0] col_coord_int_mid139_fu_578_p3; +wire [7:0] col_coord_int_fu_539_p3; +wire [0:0] icmp_ln25_fu_603_p2; +wire [0:0] xor_ln19_fu_598_p2; +wire [0:0] and_ln19_fu_609_p2; +wire [0:0] or_ln20_fu_615_p2; +wire [0:0] select_ln19_39_fu_566_p3; +wire [3:0] select_ln19_37_fu_560_p3; +wire [2:0] zext_ln22_7_fu_634_p1; +wire [2:0] tmp1_mid1_fu_651_p2; +wire [7:0] tmp1_cast_mid1_fu_657_p1; +wire [7:0] p_mid1_fu_661_p2; +wire [3:0] row_coord_int_mid1_fu_644_p3; +wire [3:0] select_ln19_40_fu_584_p3; +wire [3:0] select_ln20_32_fu_673_p3; +wire [7:0] tmp_s_fu_681_p3; +wire [4:0] tmp_16_fu_693_p3; +wire [8:0] zext_ln32_fu_689_p1; +wire [8:0] zext_ln32_34_fu_701_p1; +wire [8:0] sub_ln32_fu_705_p2; +wire [7:0] col_coord_int_mid1_fu_666_p3; +wire [7:0] select_ln19_41_fu_591_p3; +wire [7:0] select_ln20_33_fu_715_p3; +wire [9:0] sext_ln20_fu_711_p1; +wire [9:0] zext_ln32_35_fu_723_p1; +wire [9:0] add_ln32_fu_727_p2; +wire [3:0] lshr_ln_fu_737_p4; +wire [13:0] tmp_52_fu_747_p3; +wire [3:0] tmp_fu_774_p3; +wire [4:0] zext_ln33_26_fu_781_p1; +wire [4:0] zext_ln33_fu_771_p1; +wire [4:0] sub_ln33_fu_785_p2; +wire [5:0] sub_ln33_cast_fu_791_p1; +wire [5:0] zext_ln33_27_fu_795_p1; +wire [3:0] trunc_ln33_fu_804_p1; +wire [9:0] tmp_155_cast_fu_808_p3; +wire [9:0] zext_ln33_28_fu_816_p1; +wire [15:0] trunc_ln32_fu_829_p1; +wire [15:0] bitcast_ln32_fu_833_p1; +wire [5:0] or_ln25_fu_845_p2; +wire [11:0] tmp_53_fu_850_p3; +wire [15:0] tmp_84_i_i_fu_862_p4; +wire [15:0] bitcast_ln32_28_fu_872_p1; +wire [15:0] tmp_85_i_i_fu_884_p4; +wire [15:0] bitcast_ln32_29_fu_894_p1; +wire [15:0] tmp_86_i_i_fu_905_p4; +wire [15:0] bitcast_ln32_30_fu_915_p1; +wire [5:0] or_ln25_19_fu_926_p2; +wire [11:0] tmp_54_fu_931_p3; +wire [5:0] or_ln25_20_fu_943_p2; +wire [11:0] tmp_55_fu_948_p3; +wire ap_CS_fsm_state9; +reg [4:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 5'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state4)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state4); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_236 <= select_ln19_36_reg_1080; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ii_reg_236 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + indvar_flatten47_reg_224 <= add_ln19_7_reg_1075; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + indvar_flatten47_reg_224 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + indvar_flatten_reg_248 <= select_ln20_34_reg_1119; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + indvar_flatten_reg_248 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_259 <= select_ln20_30_reg_1093; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + jj_reg_259 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + kk_0_i_i_reg_271 <= add_ln25_reg_1124; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + kk_0_i_i_reg_271 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + add_ln19_7_reg_1075 <= add_ln19_7_fu_508_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_407_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln19_reg_1027 <= add_ln19_fu_413_p2; + add_ln20_7_reg_1070 <= add_ln20_7_fu_502_p2; + add_ln20_reg_1057 <= add_ln20_fu_461_p2; + icmp_ln20_reg_1033 <= icmp_ln20_fu_419_p2; + or_ln23_33_reg_1050 <= or_ln23_33_fu_456_p2; + or_ln23_35_reg_1063 <= or_ln23_35_fu_496_p2; + select_ln19_reg_1045 <= select_ln19_fu_425_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln25_reg_1124 <= add_ln25_fu_766_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1023_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + add_ln33_7_reg_1136 <= add_ln33_7_fu_819_p2; + add_ln33_reg_1129 <= add_ln33_fu_798_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + empty_137_reg_1107 <= empty_137_fu_733_p1; + select_ln20_31_reg_1099 <= select_ln20_31_fu_637_p3; + select_ln20_reg_1087 <= select_ln20_fu_620_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + empty_137_reg_1107_pp0_iter1_reg <= empty_137_reg_1107; + select_ln20_31_reg_1099_pp0_iter1_reg <= select_ln20_31_reg_1099; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + empty_reg_975 <= empty_fu_287_p1; + indices_01_read_reg_960 <= indices_01_dout; + indices_12_read_reg_970 <= indices_12_dout; + trunc_ln250_reg_965 <= trunc_ln250_fu_282_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln19_reg_1023 <= icmp_ln19_fu_407_p2; + icmp_ln19_reg_1023_pp0_iter1_reg <= icmp_ln19_reg_1023; + icmp_ln19_reg_1023_pp0_iter2_reg <= icmp_ln19_reg_1023_pp0_iter1_reg; + is_padding_reg_1016 <= is_padding_fu_401_p2; + p_cast5_i_i_reg_1010 <= p_cast5_i_i_fu_361_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + or_ln23_31_reg_1000 <= or_ln23_31_fu_337_p2; + p_cast_i_i_reg_982 <= p_cast_i_i_fu_304_p1; + p_cast_reg_994 <= p_cast_fu_318_p2; + p_mid137_reg_1005 <= p_mid137_fu_343_p2; + sext_ln22_reg_988 <= sext_ln22_fu_314_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + select_ln19_36_reg_1080 <= select_ln19_36_fu_546_p3; + select_ln20_30_reg_1093 <= select_ln20_30_fu_628_p3; + select_ln20_34_reg_1119 <= select_ln20_34_fu_760_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_1023_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + select_ln33_29_reg_1141 <= select_ln33_29_fu_898_p3; + select_ln33_30_reg_1146 <= select_ln33_30_fu_919_p3; + end +end + +always @ (*) begin + if ((icmp_ln19_reg_1023 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_240_p4 = select_ln19_36_reg_1080; + end else begin + ap_phi_mux_ii_phi_fu_240_p4 = ii_reg_236; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_indvar_flatten47_phi_fu_228_p4 = add_ln19_7_reg_1075; + end else begin + ap_phi_mux_indvar_flatten47_phi_fu_228_p4 = indvar_flatten47_reg_224; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_indvar_flatten_phi_fu_252_p4 = select_ln20_34_reg_1119; + end else begin + ap_phi_mux_indvar_flatten_phi_fu_252_p4 = indvar_flatten_reg_248; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_263_p4 = select_ln20_30_reg_1093; + end else begin + ap_phi_mux_jj_phi_fu_263_p4 = jj_reg_259; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1023_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1))) begin + ap_phi_mux_kk_0_i_i_phi_fu_275_p4 = add_ln25_reg_1124; + end else begin + ap_phi_mux_kk_0_i_i_phi_fu_275_p4 = kk_0_i_i_reg_271; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_address0 = sext_ln33_12_fu_955_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_address0 = sext_ln33_fu_857_p1; + end else begin + ifmap_vec_address0 = 'bx; + end + end else begin + ifmap_vec_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_address1 = sext_ln33_11_fu_938_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_address1 = zext_ln33_29_fu_825_p1; + end else begin + ifmap_vec_address1 = 'bx; + end + end else begin + ifmap_vec_address1 = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_ce1 = 1'b1; + end else begin + ifmap_vec_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_d0 = select_ln33_30_reg_1146; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_d0 = select_ln33_28_fu_876_p3; + end else begin + ifmap_vec_d0 = 'bx; + end + end else begin + ifmap_vec_d0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_d1 = select_ln33_29_reg_1141; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_d1 = select_ln33_fu_837_p3; + end else begin + ifmap_vec_d1 = 'bx; + end + end else begin + ifmap_vec_d1 = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1023_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_1023_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_we0 = 1'b1; + end else begin + ifmap_vec_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1023_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_1023_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_we1 = 1'b1; + end else begin + ifmap_vec_we1 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln19_reg_1023 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone)) & ~((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage1_subdone)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage1_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln19_reg_1023 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_state9; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln19_7_fu_508_p2 = (indvar_flatten47_reg_224 + 8'd1); + +assign add_ln19_fu_413_p2 = (ap_phi_mux_ii_phi_fu_240_p4 + 2'd1); + +assign add_ln20_7_fu_502_p2 = (ap_phi_mux_indvar_flatten_phi_fu_252_p4 + 7'd1); + +assign add_ln20_fu_461_p2 = (select_ln19_fu_425_p3 + 2'd1); + +assign add_ln22_7_fu_376_p2 = ((sext_ln22_reg_988) + (zext_ln20_fu_372_p1)); + +assign add_ln22_8_fu_471_p2 = ((sext_ln22_reg_988) + (zext_ln20_7_fu_467_p1)); + +assign add_ln22_fu_308_p2 = ((j_cast_i_i_fu_292_p1) + (17'd131071)); + +assign add_ln25_fu_766_p2 = (select_ln20_reg_1087 + 7'd4); + +assign add_ln32_fu_727_p2 = ((sext_ln20_fu_711_p1) + (zext_ln32_35_fu_723_p1)); + +assign add_ln33_7_fu_819_p2 = (tmp_155_cast_fu_808_p3 + zext_ln33_28_fu_816_p1); + +assign add_ln33_fu_798_p2 = ((sub_ln33_cast_fu_791_p1) + (zext_ln33_27_fu_795_p1)); + +assign and_ln19_fu_609_p2 = (xor_ln19_fu_598_p2 & icmp_ln25_fu_603_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd4]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln32_28_fu_872_p1 = tmp_84_i_i_fu_862_p4; + +assign bitcast_ln32_29_fu_894_p1 = tmp_85_i_i_fu_884_p4; + +assign bitcast_ln32_30_fu_915_p1 = tmp_86_i_i_fu_905_p4; + +assign bitcast_ln32_fu_833_p1 = trunc_ln32_fu_829_p1; + +assign col_coord_int_fu_539_p3 = ((is_padding_reg_1016[0:0] == 1'b1) ? 8'd0 : empty_135_fu_534_p2); + +assign col_coord_int_mid139_fu_578_p3 = ((or_ln23_33_reg_1050[0:0] == 1'b1) ? 8'd0 : p_mid137_reg_1005); + +assign col_coord_int_mid1_fu_666_p3 = ((or_ln23_35_reg_1063[0:0] == 1'b1) ? 8'd0 : p_mid1_fu_661_p2); + +assign empty_132_fu_298_p2 = ((zext_ln19_fu_295_p1) + (17'd131071)); + +assign empty_133_fu_356_p2 = ((p_cast_i_i_reg_982) + (ii_cast_i_i_fu_348_p1)); + +assign empty_134_fu_366_p2 = ((empty_133_fu_356_p2 > 18'd13) ? 1'b1 : 1'b0); + +assign empty_135_fu_534_p2 = ((tmp1_cast_fu_530_p1) + (empty_reg_975)); + +assign empty_137_fu_733_p1 = select_ln20_fu_620_p3[5:0]; + +assign empty_fu_287_p1 = indices_12_dout[7:0]; + +assign icmp_ln19_fu_407_p2 = ((ap_phi_mux_indvar_flatten47_phi_fu_228_p4 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_419_p2 = ((ap_phi_mux_indvar_flatten_phi_fu_252_p4 == 7'd48) ? 1'b1 : 1'b0); + +assign icmp_ln24_7_fu_389_p2 = (((add_ln22_7_fu_376_p2) > (18'd13)) ? 1'b1 : 1'b0); + +assign icmp_ln24_8_fu_484_p2 = (((add_ln22_8_fu_471_p2) > (18'd13)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_331_p2 = (((add_ln22_fu_308_p2) > (17'd13)) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_603_p2 = ((ap_phi_mux_kk_0_i_i_phi_fu_275_p4 == 7'd64) ? 1'b1 : 1'b0); + +assign ii_cast_fu_352_p1 = ap_phi_mux_ii_phi_fu_240_p4; + +assign ii_cast_i_i_fu_348_p1 = ap_phi_mux_ii_phi_fu_240_p4; + +assign ii_cast_i_i_mid1_fu_433_p1 = add_ln19_fu_413_p2; + +assign ii_cast_mid1_fu_552_p1 = add_ln19_reg_1027; + +assign in_data_address0 = sext_ln32_fu_755_p1; + +assign indices_01_out_din = indices_01_dout[3:0]; + +assign indices_12_out_din = indices_12_dout[7:0]; + +assign is_padding_fu_401_p2 = (or_ln23_fu_395_p2 | empty_134_fu_366_p2); + +assign j_cast_i_i_fu_292_p1 = indices_12_read_reg_970; + +assign lshr_ln_fu_737_p4 = {{select_ln20_fu_620_p3[5:2]}}; + +assign or_ln20_fu_615_p2 = (icmp_ln20_reg_1033 | and_ln19_fu_609_p2); + +assign or_ln23_31_fu_337_p2 = (tmp_49_fu_323_p3 | icmp_ln24_fu_331_p2); + +assign or_ln23_33_fu_456_p2 = (p_mid113_fu_442_p2 | or_ln23_31_reg_1000); + +assign or_ln23_34_fu_490_p2 = (tmp_51_fu_476_p3 | icmp_ln24_8_fu_484_p2); + +assign or_ln23_35_fu_496_p2 = (select_ln19_38_fu_448_p3 | or_ln23_34_fu_490_p2); + +assign or_ln23_fu_395_p2 = (tmp_50_fu_381_p3 | icmp_ln24_7_fu_389_p2); + +assign or_ln25_19_fu_926_p2 = (empty_137_reg_1107_pp0_iter1_reg | 6'd2); + +assign or_ln25_20_fu_943_p2 = (empty_137_reg_1107_pp0_iter1_reg | 6'd3); + +assign or_ln25_fu_845_p2 = (empty_137_reg_1107_pp0_iter1_reg | 6'd1); + +assign p_cast5_i_i_fu_361_p2 = (p_cast_reg_994 + ii_cast_fu_352_p1); + +assign p_cast5_i_i_mid1_fu_555_p2 = (p_cast_reg_994 + ii_cast_mid1_fu_552_p1); + +assign p_cast_fu_318_p2 = ((trunc_ln250_reg_965) + (4'd15)); + +assign p_cast_i_i_fu_304_p1 = (empty_132_fu_298_p2); + +assign p_mid111_fu_437_p2 = ((p_cast_i_i_reg_982) + (ii_cast_i_i_mid1_fu_433_p1)); + +assign p_mid113_fu_442_p2 = ((p_mid111_fu_437_p2 > 18'd13) ? 1'b1 : 1'b0); + +assign p_mid137_fu_343_p2 = ((empty_reg_975) + (8'd255)); + +assign p_mid1_fu_661_p2 = ((tmp1_cast_mid1_fu_657_p1) + (empty_reg_975)); + +assign row_coord_int_fu_518_p3 = ((is_padding_reg_1016[0:0] == 1'b1) ? 4'd0 : p_cast5_i_i_reg_1010); + +assign row_coord_int_mid131_fu_571_p3 = ((or_ln23_33_reg_1050[0:0] == 1'b1) ? 4'd0 : p_cast5_i_i_mid1_fu_555_p2); + +assign row_coord_int_mid1_fu_644_p3 = ((or_ln23_35_reg_1063[0:0] == 1'b1) ? 4'd0 : select_ln19_37_fu_560_p3); + +assign select_ln19_36_fu_546_p3 = ((icmp_ln20_reg_1033[0:0] == 1'b1) ? add_ln19_reg_1027 : ii_reg_236); + +assign select_ln19_37_fu_560_p3 = ((icmp_ln20_reg_1033[0:0] == 1'b1) ? p_cast5_i_i_mid1_fu_555_p2 : p_cast5_i_i_reg_1010); + +assign select_ln19_38_fu_448_p3 = ((icmp_ln20_fu_419_p2[0:0] == 1'b1) ? p_mid113_fu_442_p2 : empty_134_fu_366_p2); + +assign select_ln19_39_fu_566_p3 = ((icmp_ln20_reg_1033[0:0] == 1'b1) ? or_ln23_33_reg_1050 : is_padding_reg_1016); + +assign select_ln19_40_fu_584_p3 = ((icmp_ln20_reg_1033[0:0] == 1'b1) ? row_coord_int_mid131_fu_571_p3 : row_coord_int_fu_518_p3); + +assign select_ln19_41_fu_591_p3 = ((icmp_ln20_reg_1033[0:0] == 1'b1) ? col_coord_int_mid139_fu_578_p3 : col_coord_int_fu_539_p3); + +assign select_ln19_fu_425_p3 = ((icmp_ln20_fu_419_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_263_p4); + +assign select_ln20_30_fu_628_p3 = ((and_ln19_fu_609_p2[0:0] == 1'b1) ? add_ln20_reg_1057 : select_ln19_reg_1045); + +assign select_ln20_31_fu_637_p3 = ((and_ln19_fu_609_p2[0:0] == 1'b1) ? or_ln23_35_reg_1063 : select_ln19_39_fu_566_p3); + +assign select_ln20_32_fu_673_p3 = ((and_ln19_fu_609_p2[0:0] == 1'b1) ? row_coord_int_mid1_fu_644_p3 : select_ln19_40_fu_584_p3); + +assign select_ln20_33_fu_715_p3 = ((and_ln19_fu_609_p2[0:0] == 1'b1) ? col_coord_int_mid1_fu_666_p3 : select_ln19_41_fu_591_p3); + +assign select_ln20_34_fu_760_p3 = ((icmp_ln20_reg_1033[0:0] == 1'b1) ? 7'd1 : add_ln20_7_reg_1070); + +assign select_ln20_fu_620_p3 = ((or_ln20_fu_615_p2[0:0] == 1'b1) ? 7'd0 : ap_phi_mux_kk_0_i_i_phi_fu_275_p4); + +assign select_ln33_28_fu_876_p3 = ((select_ln20_31_reg_1099_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_28_fu_872_p1); + +assign select_ln33_29_fu_898_p3 = ((select_ln20_31_reg_1099_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_29_fu_894_p1); + +assign select_ln33_30_fu_919_p3 = ((select_ln20_31_reg_1099_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_30_fu_915_p1); + +assign select_ln33_fu_837_p3 = ((select_ln20_31_reg_1099_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_fu_833_p1); + +assign sext_ln20_fu_711_p1 = (sub_ln32_fu_705_p2); + +assign sext_ln22_fu_314_p1 = add_ln22_fu_308_p2; + +assign sext_ln32_fu_755_p1 = (tmp_52_fu_747_p3); + +assign sext_ln33_11_fu_938_p1 = (tmp_54_fu_931_p3); + +assign sext_ln33_12_fu_955_p1 = (tmp_55_fu_948_p3); + +assign sext_ln33_fu_857_p1 = (tmp_53_fu_850_p3); + +assign sub_ln32_fu_705_p2 = (zext_ln32_fu_689_p1 - zext_ln32_34_fu_701_p1); + +assign sub_ln33_cast_fu_791_p1 = (sub_ln33_fu_785_p2); + +assign sub_ln33_fu_785_p2 = (zext_ln33_26_fu_781_p1 - zext_ln33_fu_771_p1); + +assign tmp1_cast_fu_530_p1 = (tmp1_fu_524_p2); + +assign tmp1_cast_mid1_fu_657_p1 = (tmp1_mid1_fu_651_p2); + +assign tmp1_fu_524_p2 = ((zext_ln22_fu_514_p1) + (3'd7)); + +assign tmp1_mid1_fu_651_p2 = ((zext_ln22_7_fu_634_p1) + (3'd7)); + +assign tmp_155_cast_fu_808_p3 = {{trunc_ln33_fu_804_p1}, {6'd0}}; + +assign tmp_16_fu_693_p3 = {{select_ln20_32_fu_673_p3}, {1'd0}}; + +assign tmp_49_fu_323_p3 = add_ln22_fu_308_p2[32'd16]; + +assign tmp_50_fu_381_p3 = add_ln22_7_fu_376_p2[32'd17]; + +assign tmp_51_fu_476_p3 = add_ln22_8_fu_471_p2[32'd17]; + +assign tmp_52_fu_747_p3 = {{add_ln32_fu_727_p2}, {lshr_ln_fu_737_p4}}; + +assign tmp_53_fu_850_p3 = {{add_ln33_reg_1129}, {or_ln25_fu_845_p2}}; + +assign tmp_54_fu_931_p3 = {{add_ln33_reg_1129}, {or_ln25_19_fu_926_p2}}; + +assign tmp_55_fu_948_p3 = {{add_ln33_reg_1129}, {or_ln25_20_fu_943_p2}}; + +assign tmp_84_i_i_fu_862_p4 = {{in_data_q0[31:16]}}; + +assign tmp_85_i_i_fu_884_p4 = {{in_data_q0[47:32]}}; + +assign tmp_86_i_i_fu_905_p4 = {{in_data_q0[63:48]}}; + +assign tmp_fu_774_p3 = {{select_ln19_36_reg_1080}, {2'd0}}; + +assign tmp_s_fu_681_p3 = {{select_ln20_32_fu_673_p3}, {4'd0}}; + +assign trunc_ln250_fu_282_p1 = indices_01_dout[3:0]; + +assign trunc_ln32_fu_829_p1 = in_data_q0[15:0]; + +assign trunc_ln33_fu_804_p1 = add_ln33_fu_798_p2[3:0]; + +assign xor_ln19_fu_598_p2 = (icmp_ln20_reg_1033 ^ 1'd1); + +assign zext_ln19_fu_295_p1 = indices_01_read_reg_960; + +assign zext_ln20_7_fu_467_p1 = add_ln20_fu_461_p2; + +assign zext_ln20_fu_372_p1 = ap_phi_mux_jj_phi_fu_263_p4; + +assign zext_ln22_7_fu_634_p1 = add_ln20_reg_1057; + +assign zext_ln22_fu_514_p1 = jj_reg_259; + +assign zext_ln32_34_fu_701_p1 = tmp_16_fu_693_p3; + +assign zext_ln32_35_fu_723_p1 = select_ln20_33_fu_715_p3; + +assign zext_ln32_fu_689_p1 = tmp_s_fu_681_p3; + +assign zext_ln33_26_fu_781_p1 = tmp_fu_774_p3; + +assign zext_ln33_27_fu_795_p1 = select_ln20_30_reg_1093; + +assign zext_ln33_28_fu_816_p1 = select_ln20_reg_1087; + +assign zext_ln33_29_fu_825_p1 = add_ln33_7_reg_1136; + +assign zext_ln33_fu_771_p1 = select_ln19_36_reg_1080; + +endmodule //td_fused_top_tdf11_readInputs75 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_13 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [12:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [12:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [15:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [15:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [16:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [16:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [9:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [9:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [12:0] dataflow_in_loop_TOP_LOOP76_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP76_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP76_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP76_U0_in_data_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP76_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP76_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP76_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP76_U0_in_data_we1; +wire [16:0] dataflow_in_loop_TOP_LOOP76_U0_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP76_U0_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP76_U0_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP76_U0_filter_data_we0; +wire [16:0] dataflow_in_loop_TOP_LOOP76_U0_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP76_U0_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP76_U0_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP76_U0_filter_data_we1; +wire [9:0] dataflow_in_loop_TOP_LOOP76_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP76_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP76_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP76_U0_adjustments_we0; +wire [9:0] dataflow_in_loop_TOP_LOOP76_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP76_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP76_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP76_U0_adjustments_we1; +wire [15:0] dataflow_in_loop_TOP_LOOP76_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP76_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP76_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP76_U0_out_data_we0; +wire [15:0] dataflow_in_loop_TOP_LOOP76_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP76_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP76_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP76_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP76_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP76_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP76_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP76_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP76_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP76_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP76_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP76_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP76_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [17:0] loop_dataflow_input_count; +reg [17:0] loop_dataflow_output_count; +wire [17:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP76_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP76_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 18'd0; +#0 loop_dataflow_output_count = 18'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP76 dataflow_in_loop_TOP_LOOP76_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP76_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP76_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP76_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP76_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP76_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP76_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP76_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP76_U0_in_data_we1), + .filter_data_address0(dataflow_in_loop_TOP_LOOP76_U0_filter_data_address0), + .filter_data_ce0(dataflow_in_loop_TOP_LOOP76_U0_filter_data_ce0), + .filter_data_d0(dataflow_in_loop_TOP_LOOP76_U0_filter_data_d0), + .filter_data_q0(filter_data_q0), + .filter_data_we0(dataflow_in_loop_TOP_LOOP76_U0_filter_data_we0), + .filter_data_address1(dataflow_in_loop_TOP_LOOP76_U0_filter_data_address1), + .filter_data_ce1(dataflow_in_loop_TOP_LOOP76_U0_filter_data_ce1), + .filter_data_d1(dataflow_in_loop_TOP_LOOP76_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(dataflow_in_loop_TOP_LOOP76_U0_filter_data_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP76_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP76_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP76_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP76_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP76_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP76_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP76_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP76_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP76_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP76_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP76_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP76_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP76_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP76_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP76_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP76_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP76_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP76_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP76_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP76_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP76_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP76_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP76_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 18'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP76_U0_ap_ready == 1'b1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 18'd1); + end else if (((dataflow_in_loop_TOP_LOOP76_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= 18'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 18'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP76_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP76_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 18'd1); + end else if (((dataflow_in_loop_TOP_LOOP76_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP76_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + loop_dataflow_output_count <= 18'd0; + end + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP76_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP76_U0_ap_idle == 1'b1) & (loop_dataflow_output_count == 18'd0) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP76_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP76_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP76_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP76_U0_adjustments_address0; + +assign adjustments_address1 = 10'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP76_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP76_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP76_U0_ap_ready; + +assign bound_minus_1 = (18'd196000 - 18'd1); + +assign dataflow_in_loop_TOP_LOOP76_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP76_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP76_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP76_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP76_U0_start_write = 1'b0; + +assign filter_data_address0 = dataflow_in_loop_TOP_LOOP76_U0_filter_data_address0; + +assign filter_data_address1 = 17'd0; + +assign filter_data_ce0 = dataflow_in_loop_TOP_LOOP76_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP76_U0_in_data_address0; + +assign in_data_address1 = 13'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP76_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP76_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 16'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP76_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP76_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP76_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP76_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP76_U0_out_data_write; + +endmodule //td_fused_top_tdf12_13 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 8'd1; +parameter ap_ST_fsm_pp0_stage0 = 8'd2; +parameter ap_ST_fsm_pp0_stage1 = 8'd4; +parameter ap_ST_fsm_pp0_stage2 = 8'd8; +parameter ap_ST_fsm_pp0_stage3 = 8'd16; +parameter ap_ST_fsm_state12 = 8'd32; +parameter ap_ST_fsm_state13 = 8'd64; +parameter ap_ST_fsm_state14 = 8'd128; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [6:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [6:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[6:0] accum_in_0_address0; +reg accum_in_0_ce0; +reg[6:0] accum_in_0_address1; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [7:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] x_reg_170; +reg [15:0] psum_7_08_reg_182; +reg [15:0] psum_6_07_reg_194; +reg [15:0] psum_5_06_reg_206; +reg [15:0] psum_4_05_reg_218; +reg [15:0] psum_3_04_reg_230; +reg [15:0] psum_2_03_reg_242; +reg [15:0] psum_1_02_reg_254; +reg [15:0] psum_0_01_reg_266; +wire [0:0] tmp_fu_323_p3; +reg [0:0] tmp_reg_494; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state6_pp0_stage0_iter1; +wire ap_block_state10_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] tmp_reg_494_pp0_iter1_reg; +reg [0:0] tmp_reg_494_pp0_iter2_reg; +wire [6:0] trunc_ln25_fu_336_p1; +reg [6:0] trunc_ln25_reg_498; +reg [15:0] accum_in_0_load_reg_518; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state7_pp0_stage1_iter1; +wire ap_block_state11_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_0_load_58_reg_523; +reg [15:0] accum_in_0_load_59_reg_538; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state8_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_0_load_60_reg_543; +wire [7:0] add_ln25_fu_391_p2; +reg [7:0] add_ln25_reg_558; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state9_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_0_load_61_reg_563; +reg [15:0] accum_in_0_load_62_reg_568; +reg [15:0] accum_in_0_load_63_reg_583; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_0_load_64_reg_588; +wire [15:0] grp_fu_307_p2; +wire [15:0] grp_fu_312_p2; +reg ap_enable_reg_pp0_iter2; +wire [3:0] add_ln33_fu_434_p2; +wire ap_CS_fsm_state13; +wire [0:0] tmp_48_fu_417_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage1_subdone; +reg [7:0] ap_phi_mux_x_phi_fu_174_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_186_p4; +wire ap_block_pp0_stage1; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_198_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_210_p4; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_222_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_234_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_03_phi_fu_246_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_278; +wire ap_CS_fsm_state12; +reg [15:0] ap_phi_mux_phi_ln45_phi_fu_292_p8; +wire [2:0] trunc_ln33_fu_430_p1; +wire [63:0] zext_ln25_fu_331_p1; +wire [63:0] zext_ln29_fu_346_p1; +wire [63:0] zext_ln29_19_fu_356_p1; +wire [63:0] zext_ln29_20_fu_366_p1; +wire [63:0] zext_ln29_21_fu_376_p1; +wire [63:0] zext_ln29_22_fu_386_p1; +wire [63:0] zext_ln29_23_fu_402_p1; +wire [63:0] zext_ln29_24_fu_412_p1; +wire [63:0] zext_ln33_fu_425_p1; +wire [63:0] zext_ln33_4_fu_446_p1; +reg [15:0] grp_fu_307_p0; +reg [15:0] grp_fu_307_p1; +reg [15:0] grp_fu_312_p0; +reg [15:0] grp_fu_312_p1; +wire [6:0] or_ln29_fu_340_p2; +wire [6:0] or_ln29_19_fu_351_p2; +wire [6:0] or_ln29_20_fu_361_p2; +wire [6:0] or_ln29_21_fu_371_p2; +wire [6:0] or_ln29_22_fu_381_p2; +wire [6:0] or_ln29_23_fu_397_p2; +wire [6:0] or_ln29_24_fu_407_p2; +wire [2:0] or_ln33_fu_440_p2; +wire [0:0] icmp_ln45_fu_451_p2; +wire [0:0] icmp_ln45_7_fu_465_p2; +wire [15:0] select_ln45_fu_457_p3; +wire [0:0] icmp_ln45_8_fu_479_p2; +wire [15:0] select_ln45_7_fu_471_p3; +wire ap_CS_fsm_state14; +reg [7:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_517; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 8'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U775( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_307_p0), + .din1(grp_fu_307_p1), + .dout(grp_fu_307_p2) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U776( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_312_p0), + .din1(grp_fu_312_p1), + .dout(grp_fu_312_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + q_reg_278 <= 4'd0; + end else if (((tmp_48_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + q_reg_278 <= add_ln33_fu_434_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + x_reg_170 <= add_ln25_reg_558; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_170 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_58_reg_523 <= accum_in_0_q0; + accum_in_0_load_reg_518 <= accum_in_0_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage2_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_59_reg_538 <= accum_in_0_q1; + accum_in_0_load_60_reg_543 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage3_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_61_reg_563 <= accum_in_0_q1; + accum_in_0_load_62_reg_568 <= accum_in_0_q0; + add_ln25_reg_558 <= add_ln25_fu_391_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_0_load_63_reg_583 <= accum_in_0_q1; + accum_in_0_load_64_reg_588 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_0_01_reg_266 <= grp_fu_307_p2; + psum_1_02_reg_254 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_2_03_reg_242 <= grp_fu_307_p2; + psum_3_04_reg_230 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + psum_4_05_reg_218 <= grp_fu_307_p2; + psum_5_06_reg_206 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + psum_6_07_reg_194 <= grp_fu_307_p2; + psum_7_08_reg_182 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + tmp_reg_494 <= ap_phi_mux_x_phi_fu_174_p4[32'd7]; + tmp_reg_494_pp0_iter1_reg <= tmp_reg_494; + tmp_reg_494_pp0_iter2_reg <= tmp_reg_494_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_fu_323_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln25_reg_498 <= trunc_ln25_fu_336_p1; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address0 = zext_ln29_24_fu_412_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address0 = zext_ln29_22_fu_386_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address0 = zext_ln29_20_fu_366_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address0 = zext_ln29_fu_346_p1; + end else begin + accum_in_0_address0 = 'bx; + end + end else begin + accum_in_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address1 = zext_ln29_23_fu_402_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address1 = zext_ln29_21_fu_376_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address1 = zext_ln29_19_fu_356_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address1 = zext_ln25_fu_331_p1; + end else begin + accum_in_0_address1 = 'bx; + end + end else begin + accum_in_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_48_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_48_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_reg_494 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_48_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + if ((trunc_ln33_fu_430_p1 == 3'd0)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_0_01_reg_266; + end else if ((1'b1 == ap_condition_517)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_6_07_reg_194; + end else if ((trunc_ln33_fu_430_p1 == 3'd4)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_4_05_reg_218; + end else if ((trunc_ln33_fu_430_p1 == 3'd2)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_2_03_reg_242; + end else begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_x_phi_fu_174_p4 = add_ln25_reg_558; + end else begin + ap_phi_mux_x_phi_fu_174_p4 = x_reg_170; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_307_p0 = ap_phi_mux_psum_6_07_phi_fu_198_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_307_p0 = ap_phi_mux_psum_4_05_phi_fu_222_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_307_p0 = ap_phi_mux_psum_2_03_phi_fu_246_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_307_p0 = grp_fu_307_p2; + end else begin + grp_fu_307_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_307_p1 = accum_in_0_load_63_reg_583; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_307_p1 = accum_in_0_load_61_reg_563; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_307_p1 = accum_in_0_load_59_reg_538; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_307_p1 = accum_in_0_load_reg_518; + end else begin + grp_fu_307_p1 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_312_p0 = ap_phi_mux_psum_7_08_phi_fu_186_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_312_p0 = ap_phi_mux_psum_5_06_phi_fu_210_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_312_p0 = ap_phi_mux_psum_3_04_phi_fu_234_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_312_p0 = grp_fu_312_p2; + end else begin + grp_fu_312_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_312_p1 = accum_in_0_load_64_reg_588; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_312_p1 = accum_in_0_load_62_reg_568; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_312_p1 = accum_in_0_load_60_reg_543; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_312_p1 = accum_in_0_load_58_reg_523; + end else begin + grp_fu_312_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_494 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_494 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + if (((tmp_48_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_state14; + end + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln33_4_fu_446_p1; + +assign accum_out_address1 = zext_ln33_fu_425_p1; + +assign accum_out_d0 = ((icmp_ln45_8_fu_479_p2[0:0] == 1'b1) ? psum_5_06_reg_206 : select_ln45_7_fu_471_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln45_phi_fu_292_p8; + +assign add_ln25_fu_391_p2 = (x_reg_170 + 8'd8); + +assign add_ln33_fu_434_p2 = (q_reg_278 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_state14 = ap_CS_fsm[32'd7]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_517 = (~(trunc_ln33_fu_430_p1 == 3'd0) & ~(trunc_ln33_fu_430_p1 == 3'd4) & ~(trunc_ln33_fu_430_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_03_phi_fu_246_p4 = grp_fu_307_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_234_p4 = grp_fu_312_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_222_p4 = grp_fu_307_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_210_p4 = grp_fu_312_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_198_p4 = grp_fu_307_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_186_p4 = grp_fu_312_p2; + +assign icmp_ln45_7_fu_465_p2 = ((or_ln33_fu_440_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln45_8_fu_479_p2 = ((or_ln33_fu_440_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln45_fu_451_p2 = ((or_ln33_fu_440_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln29_19_fu_351_p2 = (trunc_ln25_reg_498 | 7'd2); + +assign or_ln29_20_fu_361_p2 = (trunc_ln25_reg_498 | 7'd3); + +assign or_ln29_21_fu_371_p2 = (trunc_ln25_reg_498 | 7'd4); + +assign or_ln29_22_fu_381_p2 = (trunc_ln25_reg_498 | 7'd5); + +assign or_ln29_23_fu_397_p2 = (trunc_ln25_reg_498 | 7'd6); + +assign or_ln29_24_fu_407_p2 = (trunc_ln25_reg_498 | 7'd7); + +assign or_ln29_fu_340_p2 = (trunc_ln25_fu_336_p1 | 7'd1); + +assign or_ln33_fu_440_p2 = (trunc_ln33_fu_430_p1 | 3'd1); + +assign select_ln45_7_fu_471_p3 = ((icmp_ln45_7_fu_465_p2[0:0] == 1'b1) ? psum_3_04_reg_230 : select_ln45_fu_457_p3); + +assign select_ln45_fu_457_p3 = ((icmp_ln45_fu_451_p2[0:0] == 1'b1) ? psum_1_02_reg_254 : psum_7_08_reg_182); + +assign tmp_48_fu_417_p3 = q_reg_278[32'd3]; + +assign tmp_fu_323_p3 = ap_phi_mux_x_phi_fu_174_p4[32'd7]; + +assign trunc_ln25_fu_336_p1 = ap_phi_mux_x_phi_fu_174_p4[6:0]; + +assign trunc_ln33_fu_430_p1 = q_reg_278[2:0]; + +assign zext_ln25_fu_331_p1 = ap_phi_mux_x_phi_fu_174_p4; + +assign zext_ln29_19_fu_356_p1 = or_ln29_19_fu_351_p2; + +assign zext_ln29_20_fu_366_p1 = or_ln29_20_fu_361_p2; + +assign zext_ln29_21_fu_376_p1 = or_ln29_21_fu_371_p2; + +assign zext_ln29_22_fu_386_p1 = or_ln29_22_fu_381_p2; + +assign zext_ln29_23_fu_402_p1 = or_ln29_23_fu_397_p2; + +assign zext_ln29_24_fu_412_p1 = or_ln29_24_fu_407_p2; + +assign zext_ln29_fu_346_p1 = or_ln29_fu_340_p2; + +assign zext_ln33_4_fu_446_p1 = or_ln33_fu_440_p2; + +assign zext_ln33_fu_425_p1 = q_reg_278; + +endmodule //td_fused_top_tdf12_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_20, + accum_in_20_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 7'd1; +parameter ap_ST_fsm_state2 = 7'd2; +parameter ap_ST_fsm_state3 = 7'd4; +parameter ap_ST_fsm_state4 = 7'd8; +parameter ap_ST_fsm_state5 = 7'd16; +parameter ap_ST_fsm_state6 = 7'd32; +parameter ap_ST_fsm_state7 = 7'd64; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_20; +output accum_in_20_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_20; +reg accum_in_20_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [6:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln57_fu_74_p2; +reg [3:0] add_ln57_reg_91; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln57_fu_85_p2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state7; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln57_fu_80_p1; +reg [15:0] accum_in_20_preg; +reg [6:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 7'd1; +#0 accum_in_20_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U779( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_q0), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_20_preg <= 16'd0; + end else begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_20_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + i_1_1_reg_44 <= add_ln57_reg_91; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln57_reg_91 <= add_ln57_fu_74_p2; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_20 = sum_01_reg_55; + end else begin + accum_in_20 = accum_in_20_preg; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_20_ap_vld = 1'b1; + end else begin + accum_in_20_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln57_fu_80_p1; + +assign add_ln57_fu_74_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln57_fu_85_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln57_fu_80_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf12_accum_2 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf12_adjustments_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 48; +parameter AWIDTH = 10; +parameter MEM_SIZE = 1000; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf12_adjustments( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd48; +parameter AddressRange = 32'd1000; +parameter AddressWidth = 32'd10; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf12_adjustments_ram td_fused_top_tdf12_adjustments_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 17'd1; +parameter ap_ST_fsm_state2 = 17'd2; +parameter ap_ST_fsm_state3 = 17'd4; +parameter ap_ST_fsm_state4 = 17'd8; +parameter ap_ST_fsm_state5 = 17'd16; +parameter ap_ST_fsm_state6 = 17'd32; +parameter ap_ST_fsm_state7 = 17'd64; +parameter ap_ST_fsm_state8 = 17'd128; +parameter ap_ST_fsm_state9 = 17'd256; +parameter ap_ST_fsm_state10 = 17'd512; +parameter ap_ST_fsm_state11 = 17'd1024; +parameter ap_ST_fsm_state12 = 17'd2048; +parameter ap_ST_fsm_state13 = 17'd4096; +parameter ap_ST_fsm_state14 = 17'd8192; +parameter ap_ST_fsm_state15 = 17'd16384; +parameter ap_ST_fsm_state16 = 17'd32768; +parameter ap_ST_fsm_state17 = 17'd65536; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_read; +output [9:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [9:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg indices_23_read; + +reg ap_done_reg; + reg [16:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +wire ap_CS_fsm_state4; +reg [15:0] tmp_82_i_i_reg_167; +reg [15:0] tmp_83_i_i_reg_172; +wire [15:0] grp_fu_81_p2; +reg [15:0] sub_i_i_i_reg_177; +wire ap_CS_fsm_state8; +wire ap_CS_fsm_state9; +wire [15:0] grp_fu_86_p2; +reg [15:0] mul_i_i_i_reg_187; +wire ap_CS_fsm_state12; +wire ap_CS_fsm_state13; +wire [63:0] zext_ln220_fu_90_p1; +reg ap_block_state1; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_77_p1; +wire [15:0] grp_fu_81_p1; +wire [15:0] grp_fu_86_p1; +wire [15:0] trunc_ln220_fu_95_p1; +wire [15:0] grp_fu_77_p2; +wire ap_CS_fsm_state17; +wire [15:0] bitcast_ln648_fu_132_p1; +wire [0:0] tmp_fu_136_p3; +reg [16:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 17'd1; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U783( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(mul_i_i_i_reg_187), + .din1(grp_fu_77_p1), + .dout(grp_fu_77_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U784( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sums_read), + .din1(grp_fu_81_p1), + .dout(grp_fu_81_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U785( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_177), + .din1(grp_fu_86_p1), + .dout(grp_fu_86_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + mul_i_i_i_reg_187 <= grp_fu_86_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sub_i_i_i_reg_177 <= grp_fu_81_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tmp_82_i_i_reg_167 <= {{adjustments_q0[31:16]}}; + tmp_83_i_i_reg_172 <= {{adjustments_q0[47:32]}}; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign adjustments_address0 = zext_ln220_fu_90_p1; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_return = ((tmp_fu_136_p3[0:0] == 1'b1) ? 16'd0 : grp_fu_77_p2); + +assign bitcast_ln648_fu_132_p1 = grp_fu_77_p2; + +assign grp_fu_77_p1 = tmp_83_i_i_reg_172; + +assign grp_fu_81_p1 = trunc_ln220_fu_95_p1; + +assign grp_fu_86_p1 = tmp_82_i_i_reg_167; + +assign tmp_fu_136_p3 = bitcast_ln648_fu_132_p1[32'd15]; + +assign trunc_ln220_fu_95_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_90_p1 = indices_23_dout; + +endmodule //td_fused_top_tdf12_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_q0, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state9 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [6:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +input [15:0] ifmap_vec_0_0_q0; +output [6:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +input [15:0] weight_vecs_0_0_0_q0; +output [6:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_0_0_ce0; +reg weight_vecs_0_0_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] ic_0_0_reg_69; +wire [7:0] add_ln149_fu_84_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln149_fu_90_p2; +reg [0:0] icmp_ln149_reg_107; +reg [0:0] icmp_ln149_reg_107_pp0_iter1_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter2_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter3_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter4_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter5_reg; +wire [63:0] idxprom17_0_0_fu_96_p1; +reg [63:0] idxprom17_0_0_reg_111; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter1_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter2_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter3_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter4_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter5_reg; +reg [15:0] ifmap_vec_0_0_load_reg_126; +reg [15:0] weight_vecs_0_0_0_load_reg_131; +wire [15:0] grp_fu_80_p2; +reg [15:0] mul_reg_136; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +wire ap_block_pp0_stage0; +wire ap_CS_fsm_state9; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U771( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_0_load_reg_126), + .din1(weight_vecs_0_0_0_load_reg_131), + .dout(grp_fu_80_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_fu_90_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_0_0_reg_69 <= add_ln149_fu_84_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_0_0_reg_69 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln149_reg_107 <= icmp_ln149_fu_90_p2; + icmp_ln149_reg_107_pp0_iter1_reg <= icmp_ln149_reg_107; + idxprom17_0_0_reg_111_pp0_iter1_reg[7 : 0] <= idxprom17_0_0_reg_111[7 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln149_reg_107_pp0_iter2_reg <= icmp_ln149_reg_107_pp0_iter1_reg; + icmp_ln149_reg_107_pp0_iter3_reg <= icmp_ln149_reg_107_pp0_iter2_reg; + icmp_ln149_reg_107_pp0_iter4_reg <= icmp_ln149_reg_107_pp0_iter3_reg; + icmp_ln149_reg_107_pp0_iter5_reg <= icmp_ln149_reg_107_pp0_iter4_reg; + idxprom17_0_0_reg_111_pp0_iter2_reg[7 : 0] <= idxprom17_0_0_reg_111_pp0_iter1_reg[7 : 0]; + idxprom17_0_0_reg_111_pp0_iter3_reg[7 : 0] <= idxprom17_0_0_reg_111_pp0_iter2_reg[7 : 0]; + idxprom17_0_0_reg_111_pp0_iter4_reg[7 : 0] <= idxprom17_0_0_reg_111_pp0_iter3_reg[7 : 0]; + idxprom17_0_0_reg_111_pp0_iter5_reg[7 : 0] <= idxprom17_0_0_reg_111_pp0_iter4_reg[7 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_fu_90_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + idxprom17_0_0_reg_111[7 : 0] <= idxprom17_0_0_fu_96_p1[7 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_reg_107 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_load_reg_126 <= ifmap_vec_0_0_q0; + weight_vecs_0_0_0_load_reg_131 <= weight_vecs_0_0_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_reg_107_pp0_iter4_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_reg_136 <= grp_fu_80_p2; + end +end + +always @ (*) begin + if ((icmp_ln149_fu_90_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter6 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln149_reg_107_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter6 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln149_fu_90_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter6 == 1'b1) & (ap_enable_reg_pp0_iter5 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln149_fu_90_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter6 == 1'b1) & (ap_enable_reg_pp0_iter5 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state9; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln149_fu_84_p2 = (ic_0_0_reg_69 + 8'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign icmp_ln149_fu_90_p2 = ((ic_0_0_reg_69 == 8'd128) ? 1'b1 : 1'b0); + +assign idxprom17_0_0_fu_96_p1 = ic_0_0_reg_69; + +assign ifmap_vec_0_0_address0 = idxprom17_0_0_fu_96_p1; + +assign products_0_address0 = idxprom17_0_0_reg_111_pp0_iter5_reg; + +assign products_0_d0 = mul_reg_136; + +assign weight_vecs_0_0_0_address0 = idxprom17_0_0_fu_96_p1; + +always @ (posedge ap_clk) begin + idxprom17_0_0_reg_111[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter1_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter2_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter3_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter4_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter5_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf12_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf12_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 17; +parameter MEM_SIZE = 128000; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf12_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd128000; +parameter AddressWidth = 32'd17; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf12_filters_ram td_fused_top_tdf12_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + indices_2_out_din, + indices_2_out_full_n, + indices_2_out_write, + indices_2_out1_din, + indices_2_out1_full_n, + indices_2_out1_write +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [9:0] indices_2_out_din; +input indices_2_out_full_n; +output indices_2_out_write; +output [9:0] indices_2_out1_din; +input indices_2_out1_full_n; +output indices_2_out1_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg indices_0_write; +reg indices_1_write; +reg indices_2_out_write; +reg indices_2_out1_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [15:0] i_5; +reg [15:0] j_5; +reg [15:0] k_5; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg indices_2_out_blk_n; +reg indices_2_out1_blk_n; +reg [0:0] ap_phi_mux_j_9_flag_0_i_phi_fu_77_p6; +reg ap_block_state1; +wire [0:0] icmp_ln78_fu_141_p2; +wire [0:0] icmp_ln81_fu_154_p2; +reg [15:0] ap_phi_mux_j_9_new_0_i_phi_fu_91_p6; +wire [15:0] add_ln80_fu_147_p2; +reg [15:0] ap_phi_mux_k_9_new_0_i_phi_fu_104_p6; +wire [15:0] add_ln77_fu_134_p2; +wire [15:0] select_ln84_fu_172_p3; +wire [9:0] trunc_ln76_fu_128_p1; +wire [15:0] add_ln83_fu_160_p2; +wire [0:0] icmp_ln84_fu_166_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_5 = 16'd0; +#0 j_5 = 16'd0; +#0 k_5 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_5 <= select_ln84_fu_172_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_9_flag_0_i_phi_fu_77_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j_5 <= ap_phi_mux_j_9_new_0_i_phi_fu_91_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k_5 <= ap_phi_mux_k_9_new_0_i_phi_fu_104_p6; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_9_flag_0_i_phi_fu_77_p6 = 1'd0; + end else if ((((icmp_ln81_fu_154_p2 == 1'd0) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_9_flag_0_i_phi_fu_77_p6 = 1'd1; + end else begin + ap_phi_mux_j_9_flag_0_i_phi_fu_77_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln81_fu_154_p2 == 1'd0)) begin + ap_phi_mux_j_9_new_0_i_phi_fu_91_p6 = add_ln80_fu_147_p2; + end else if ((icmp_ln81_fu_154_p2 == 1'd1)) begin + ap_phi_mux_j_9_new_0_i_phi_fu_91_p6 = 16'd0; + end else begin + ap_phi_mux_j_9_new_0_i_phi_fu_91_p6 = 'bx; + end + end else begin + ap_phi_mux_j_9_new_0_i_phi_fu_91_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_9_new_0_i_phi_fu_104_p6 = add_ln77_fu_134_p2; + end else if ((((icmp_ln81_fu_154_p2 == 1'd0) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_9_new_0_i_phi_fu_104_p6 = 16'd0; + end else begin + ap_phi_mux_k_9_new_0_i_phi_fu_104_p6 = 'bx; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_blk_n = indices_2_out1_full_n; + end else begin + indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_write = 1'b1; + end else begin + indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_blk_n = indices_2_out_full_n; + end else begin + indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_write = 1'b1; + end else begin + indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln77_fu_134_p2 = (k_5 + 16'd1); + +assign add_ln80_fu_147_p2 = (j_5 + 16'd1); + +assign add_ln83_fu_160_p2 = (i_5 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign icmp_ln78_fu_141_p2 = ((add_ln77_fu_134_p2 == 16'd1000) ? 1'b1 : 1'b0); + +assign icmp_ln81_fu_154_p2 = ((add_ln80_fu_147_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign icmp_ln84_fu_166_p2 = ((add_ln83_fu_160_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign indices_0_din = i_5; + +assign indices_1_din = j_5; + +assign indices_2_out1_din = trunc_ln76_fu_128_p1; + +assign indices_2_out_din = trunc_ln76_fu_128_p1; + +assign select_ln84_fu_172_p3 = ((icmp_ln84_fu_166_p2[0:0] == 1'b1) ? 16'd0 : add_ln83_fu_160_p2); + +assign start_out = real_start; + +assign trunc_ln76_fu_128_p1 = k_5[9:0]; + +endmodule //td_fused_top_tdf12_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_readFilters78 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_we0, + weight_vecs_0_0_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state6 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [16:0] filter_data_address0; +output filter_data_ce0; +input [15:0] filter_data_q0; +input [9:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [6:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +output weight_vecs_0_0_0_we0; +output [15:0] weight_vecs_0_0_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg indices_23_read; +reg weight_vecs_0_0_0_ce0; +reg weight_vecs_0_0_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [7:0] kk_0_0_i_i_reg_93; +reg [7:0] kk_0_0_i_i_reg_93_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_pp0_stage0_11001; +reg [7:0] kk_0_0_i_i_reg_93_pp0_iter2_reg; +wire [16:0] tmp_fu_105_p3; +reg [16:0] tmp_reg_144; +wire [7:0] add_ln49_fu_113_p2; +reg [7:0] add_ln49_reg_149; +reg ap_enable_reg_pp0_iter0; +wire [0:0] icmp_ln49_fu_119_p2; +reg [0:0] icmp_ln49_reg_154; +reg [0:0] icmp_ln49_reg_154_pp0_iter1_reg; +reg [0:0] icmp_ln49_reg_154_pp0_iter2_reg; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg [7:0] ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln55_59_fu_134_p1; +wire [63:0] idxprom16_0_0_i_i_fu_139_p1; +wire [16:0] zext_ln55_fu_125_p1; +wire [16:0] add_ln55_fu_129_p2; +wire ap_CS_fsm_state6; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_0_i_i_reg_93 <= add_ln49_reg_149; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_0_0_i_i_reg_93 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln49_reg_149 <= add_ln49_fu_113_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln49_reg_154 <= icmp_ln49_fu_119_p2; + icmp_ln49_reg_154_pp0_iter1_reg <= icmp_ln49_reg_154; + kk_0_0_i_i_reg_93_pp0_iter1_reg <= kk_0_0_i_i_reg_93; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln49_reg_154_pp0_iter2_reg <= icmp_ln49_reg_154_pp0_iter1_reg; + kk_0_0_i_i_reg_93_pp0_iter2_reg <= kk_0_0_i_i_reg_93_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + tmp_reg_144[16 : 7] <= tmp_fu_105_p3[16 : 7]; + end +end + +always @ (*) begin + if ((icmp_ln49_fu_119_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 = add_ln49_reg_149; + end else begin + ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 = kk_0_0_i_i_reg_93; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln49_reg_154_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1))) begin + weight_vecs_0_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln49_fu_119_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln49_fu_119_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln49_fu_113_p2 = (ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 + 8'd1); + +assign add_ln55_fu_129_p2 = (tmp_reg_144 + zext_ln55_fu_125_p1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_address0 = zext_ln55_59_fu_134_p1; + +assign icmp_ln49_fu_119_p2 = ((ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 == 8'd128) ? 1'b1 : 1'b0); + +assign idxprom16_0_0_i_i_fu_139_p1 = kk_0_0_i_i_reg_93_pp0_iter2_reg; + +assign tmp_fu_105_p3 = {{indices_23_dout}, {7'd0}}; + +assign weight_vecs_0_0_0_address0 = idxprom16_0_0_i_i_fu_139_p1; + +assign weight_vecs_0_0_0_d0 = filter_data_q0; + +assign zext_ln55_59_fu_134_p1 = add_ln55_fu_129_p2; + +assign zext_ln55_fu_125_p1 = ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4; + +always @ (posedge ap_clk) begin + tmp_reg_144[6:0] <= 7'b0000000; +end + +endmodule //td_fused_top_tdf12_readFilters78 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_readInputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_we0, + ifmap_vec_0_0_d0, + ifmap_vec_0_0_address1, + ifmap_vec_0_0_ce1, + ifmap_vec_0_0_we1, + ifmap_vec_0_0_d1, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 5'd1; +parameter ap_ST_fsm_state2 = 5'd2; +parameter ap_ST_fsm_pp0_stage0 = 5'd4; +parameter ap_ST_fsm_pp0_stage1 = 5'd8; +parameter ap_ST_fsm_state8 = 5'd16; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [12:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [6:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +output ifmap_vec_0_0_we0; +output [15:0] ifmap_vec_0_0_d0; +output [6:0] ifmap_vec_0_0_address1; +output ifmap_vec_0_0_ce1; +output ifmap_vec_0_0_we1; +output [15:0] ifmap_vec_0_0_d1; +output [3:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [7:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg[6:0] ifmap_vec_0_0_address0; +reg ifmap_vec_0_0_ce0; +reg ifmap_vec_0_0_we0; +reg[15:0] ifmap_vec_0_0_d0; +reg[6:0] ifmap_vec_0_0_address1; +reg ifmap_vec_0_0_ce1; +reg ifmap_vec_0_0_we1; +reg[15:0] ifmap_vec_0_0_d1; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [4:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [7:0] kk_0_i_i_reg_180; +reg [7:0] kk_0_i_i_reg_180_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state5_pp0_stage0_iter1; +wire ap_block_state7_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [3:0] trunc_ln135_fu_192_p1; +reg [3:0] trunc_ln135_reg_434; +reg [15:0] col_coord_reg_439; +wire [0:0] is_padding_fu_214_p2; +reg [0:0] is_padding_reg_444; +wire [9:0] add_ln32_fu_274_p2; +reg [9:0] add_ln32_reg_454; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln25_fu_280_p2; +reg [0:0] icmp_ln25_reg_459; +reg [0:0] icmp_ln25_reg_459_pp0_iter1_reg; +wire [7:0] add_ln25_fu_308_p2; +reg [7:0] add_ln25_reg_468; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state4_pp0_stage1_iter0; +wire ap_block_state6_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +wire [6:0] empty_130_fu_314_p1; +reg [6:0] empty_130_reg_473; +wire [15:0] select_ln33_26_fu_386_p3; +reg [15:0] select_ln33_26_reg_479; +wire [15:0] select_ln33_27_fu_407_p3; +reg [15:0] select_ln33_27_reg_484; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state3; +reg ap_enable_reg_pp0_iter1; +wire ap_block_pp0_stage1_subdone; +reg ap_enable_reg_pp0_iter2; +reg [7:0] ap_phi_mux_kk_0_i_i_phi_fu_184_p4; +wire ap_block_pp0_stage0; +wire [63:0] sext_ln32_fu_303_p1; +wire [63:0] zext_ln32_fu_318_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln32_28_fu_345_p1; +wire [63:0] zext_ln32_29_fu_419_p1; +wire [63:0] zext_ln32_30_fu_429_p1; +reg ap_block_state1; +wire [15:0] select_ln33_fu_331_p3; +wire [15:0] select_ln33_25_fu_364_p3; +wire [0:0] cmp7_i_i_fu_202_p2; +wire [0:0] icmp_ln24_fu_208_p2; +wire [3:0] empty_128_fu_220_p1; +wire [3:0] row_coord_int_fu_223_p3; +wire [7:0] tmp_fu_236_p3; +wire [4:0] tmp_s_fu_248_p3; +wire [8:0] zext_ln32_31_fu_244_p1; +wire [8:0] zext_ln32_32_fu_256_p1; +wire [8:0] sub_ln32_fu_260_p2; +wire [3:0] col_coord_int_fu_229_p3; +wire [9:0] sub_ln32_cast_fu_266_p1; +wire [9:0] zext_ln32_33_fu_270_p1; +wire [4:0] lshr_ln_fu_286_p4; +wire [14:0] tmp_47_fu_296_p3; +wire [15:0] trunc_ln32_fu_323_p1; +wire [15:0] bitcast_ln32_fu_327_p1; +wire [6:0] or_ln25_fu_339_p2; +wire [15:0] tmp_79_i_i_fu_350_p4; +wire [15:0] bitcast_ln32_25_fu_360_p1; +wire [15:0] tmp_80_i_i_fu_372_p4; +wire [15:0] bitcast_ln32_26_fu_382_p1; +wire [15:0] tmp_81_i_i_fu_393_p4; +wire [15:0] bitcast_ln32_27_fu_403_p1; +wire [6:0] or_ln25_17_fu_414_p2; +wire [6:0] or_ln25_18_fu_424_p2; +wire ap_CS_fsm_state8; +reg [4:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 5'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln25_reg_459 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_i_i_reg_180 <= add_ln25_reg_468; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + kk_0_i_i_reg_180 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln25_reg_459 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln25_reg_468 <= add_ln25_fu_308_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln32_reg_454 <= add_ln32_fu_274_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + col_coord_reg_439 <= indices_12_dout; + is_padding_reg_444 <= is_padding_fu_214_p2; + trunc_ln135_reg_434 <= trunc_ln135_fu_192_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln25_reg_459_pp0_iter1_reg == 1'd0))) begin + empty_130_reg_473 <= empty_130_fu_314_p1; + select_ln33_26_reg_479 <= select_ln33_26_fu_386_p3; + select_ln33_27_reg_484 <= select_ln33_27_fu_407_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln25_reg_459 <= icmp_ln25_fu_280_p2; + icmp_ln25_reg_459_pp0_iter1_reg <= icmp_ln25_reg_459; + kk_0_i_i_reg_180_pp0_iter1_reg <= kk_0_i_i_reg_180; + end +end + +always @ (*) begin + if ((icmp_ln25_fu_280_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln25_reg_459 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_i_i_phi_fu_184_p4 = add_ln25_reg_468; + end else begin + ap_phi_mux_kk_0_i_i_phi_fu_184_p4 = kk_0_i_i_reg_180; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_address0 = zext_ln32_30_fu_429_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_address0 = zext_ln32_28_fu_345_p1; + end else begin + ifmap_vec_0_0_address0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_address1 = zext_ln32_29_fu_419_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_address1 = zext_ln32_fu_318_p1; + end else begin + ifmap_vec_0_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_ce1 = 1'b1; + end else begin + ifmap_vec_0_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_d0 = select_ln33_27_reg_484; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_d0 = select_ln33_25_fu_364_p3; + end else begin + ifmap_vec_0_0_d0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_d1 = select_ln33_26_reg_479; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_d1 = select_ln33_fu_331_p3; + end else begin + ifmap_vec_0_0_d1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln25_reg_459_pp0_iter1_reg == 1'd0)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln25_reg_459_pp0_iter1_reg == 1'd0)))) begin + ifmap_vec_0_0_we0 = 1'b1; + end else begin + ifmap_vec_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln25_reg_459_pp0_iter1_reg == 1'd0)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln25_reg_459_pp0_iter1_reg == 1'd0)))) begin + ifmap_vec_0_0_we1 = 1'b1; + end else begin + ifmap_vec_0_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln25_fu_280_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if ((((icmp_ln25_fu_280_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state8; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln25_fu_308_p2 = (kk_0_i_i_reg_180 + 8'd4); + +assign add_ln32_fu_274_p2 = ((sub_ln32_cast_fu_266_p1) + (zext_ln32_33_fu_270_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd4]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln32_25_fu_360_p1 = tmp_79_i_i_fu_350_p4; + +assign bitcast_ln32_26_fu_382_p1 = tmp_80_i_i_fu_372_p4; + +assign bitcast_ln32_27_fu_403_p1 = tmp_81_i_i_fu_393_p4; + +assign bitcast_ln32_fu_327_p1 = trunc_ln32_fu_323_p1; + +assign cmp7_i_i_fu_202_p2 = ((indices_01_dout > 16'd13) ? 1'b1 : 1'b0); + +assign col_coord_int_fu_229_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 4'd0 : empty_128_fu_220_p1); + +assign empty_128_fu_220_p1 = col_coord_reg_439[3:0]; + +assign empty_130_fu_314_p1 = kk_0_i_i_reg_180_pp0_iter1_reg[6:0]; + +assign icmp_ln24_fu_208_p2 = ((indices_12_dout > 16'd13) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_280_p2 = ((ap_phi_mux_kk_0_i_i_phi_fu_184_p4 == 8'd128) ? 1'b1 : 1'b0); + +assign in_data_address0 = sext_ln32_fu_303_p1; + +assign indices_01_out_din = indices_01_dout[3:0]; + +assign indices_12_out_din = indices_12_dout[7:0]; + +assign is_padding_fu_214_p2 = (icmp_ln24_fu_208_p2 | cmp7_i_i_fu_202_p2); + +assign lshr_ln_fu_286_p4 = {{ap_phi_mux_kk_0_i_i_phi_fu_184_p4[6:2]}}; + +assign or_ln25_17_fu_414_p2 = (empty_130_reg_473 | 7'd2); + +assign or_ln25_18_fu_424_p2 = (empty_130_reg_473 | 7'd3); + +assign or_ln25_fu_339_p2 = (empty_130_fu_314_p1 | 7'd1); + +assign row_coord_int_fu_223_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 4'd0 : trunc_ln135_reg_434); + +assign select_ln33_25_fu_364_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_25_fu_360_p1); + +assign select_ln33_26_fu_386_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_26_fu_382_p1); + +assign select_ln33_27_fu_407_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_27_fu_403_p1); + +assign select_ln33_fu_331_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_fu_327_p1); + +assign sext_ln32_fu_303_p1 = (tmp_47_fu_296_p3); + +assign sub_ln32_cast_fu_266_p1 = (sub_ln32_fu_260_p2); + +assign sub_ln32_fu_260_p2 = (zext_ln32_31_fu_244_p1 - zext_ln32_32_fu_256_p1); + +assign tmp_47_fu_296_p3 = {{add_ln32_reg_454}, {lshr_ln_fu_286_p4}}; + +assign tmp_79_i_i_fu_350_p4 = {{in_data_q0[31:16]}}; + +assign tmp_80_i_i_fu_372_p4 = {{in_data_q0[47:32]}}; + +assign tmp_81_i_i_fu_393_p4 = {{in_data_q0[63:48]}}; + +assign tmp_fu_236_p3 = {{row_coord_int_fu_223_p3}, {4'd0}}; + +assign tmp_s_fu_248_p3 = {{row_coord_int_fu_223_p3}, {1'd0}}; + +assign trunc_ln135_fu_192_p1 = indices_01_dout[3:0]; + +assign trunc_ln32_fu_323_p1 = in_data_q0[15:0]; + +assign zext_ln32_28_fu_345_p1 = or_ln25_fu_339_p2; + +assign zext_ln32_29_fu_419_p1 = or_ln25_17_fu_414_p2; + +assign zext_ln32_30_fu_429_p1 = or_ln25_18_fu_424_p2; + +assign zext_ln32_31_fu_244_p1 = tmp_fu_236_p3; + +assign zext_ln32_32_fu_256_p1 = tmp_s_fu_248_p3; + +assign zext_ln32_33_fu_270_p1 = col_coord_int_fu_229_p3; + +assign zext_ln32_fu_318_p1 = kk_0_i_i_reg_180_pp0_iter1_reg; + +endmodule //td_fused_top_tdf12_readInputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf12_writeOutputs_unaligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + p_read, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_state3 = 4'd4; +parameter ap_ST_fsm_state4 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [3:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [7:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [15:0] p_read; +output [15:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg out_data_ce1; +reg out_data_we1; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] outputCount_2; +reg [15:0] outputChanIdx_2; +reg [15:0] outputRow_7_0; +reg [15:0] outputRow_7_1; +reg [15:0] outputRow_7_2; +reg [15:0] outputRow_7_3; +reg indices_01_blk_n; +reg indices_12_blk_n; +wire [9:0] add_ln94_fu_157_p2; +reg [9:0] add_ln94_reg_315; +wire [15:0] mul_ln89_fu_166_p2; +reg [15:0] mul_ln89_reg_320; +wire ap_CS_fsm_state2; +wire [15:0] add_ln87_fu_204_p2; +wire ap_CS_fsm_state3; +wire [0:0] icmp_ln88_fu_210_p2; +reg [0:0] icmp_ln88_reg_333; +reg [15:0] ap_phi_mux_empty_phi_fu_112_p4; +reg [15:0] empty_reg_109; +wire ap_CS_fsm_state4; +wire [63:0] zext_ln94_22_fu_237_p1; +wire [15:0] select_ln97_fu_295_p3; +wire [1:0] trunc_ln86_fu_176_p1; +reg [15:0] ap_sig_allocacmp_outputRow_7_0_load; +reg [15:0] ap_sig_allocacmp_outputRow_7_1_load; +reg [15:0] ap_sig_allocacmp_outputRow_7_2_load; +reg [15:0] ap_sig_allocacmp_outputRow_7_3_load; +reg ap_block_state1; +wire [7:0] tmp_fu_119_p3; +wire [4:0] tmp_s_fu_131_p3; +wire [8:0] zext_ln94_fu_127_p1; +wire [8:0] zext_ln94_19_fu_139_p1; +wire [8:0] sub_ln94_fu_143_p2; +wire [9:0] sub_ln94_cast_fu_149_p1; +wire [9:0] zext_ln94_20_fu_153_p1; +wire [8:0] mul_ln89_fu_166_p1; +wire [8:0] trunc_ln94_fu_224_p1; +wire [15:0] zext_ln94_21_fu_228_p1; +wire [15:0] add_ln94_8_fu_232_p2; +wire [15:0] bitcast_ln94_24_fu_266_p1; +wire [15:0] bitcast_ln94_23_fu_258_p1; +wire [15:0] bitcast_ln94_22_fu_250_p1; +wire [15:0] bitcast_ln94_fu_242_p1; +wire [15:0] add_ln96_fu_283_p2; +wire [0:0] icmp_ln97_fu_289_p2; +reg [3:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 outputCount_2 = 16'd0; +#0 outputChanIdx_2 = 16'd0; +#0 outputRow_7_0 = 16'd0; +#0 outputRow_7_1 = 16'd0; +#0 outputRow_7_2 = 16'd0; +#0 outputRow_7_3 = 16'd0; +end + +td_fused_top_mul_10s_9ns_16_1_1 #( + .ID( 1 ), + .NUM_STAGE( 1 ), + .din0_WIDTH( 10 ), + .din1_WIDTH( 9 ), + .dout_WIDTH( 16 )) +mul_10s_9ns_16_1_1_U789( + .din0(add_ln94_reg_315), + .din1(mul_ln89_fu_166_p1), + .dout(mul_ln89_fu_166_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state4)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_reg_333 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin + empty_reg_109 <= 16'd0; + end else if (((icmp_ln88_fu_210_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state3))) begin + empty_reg_109 <= add_ln87_fu_204_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + add_ln94_reg_315 <= add_ln94_fu_157_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + icmp_ln88_reg_333 <= icmp_ln88_fu_210_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + mul_ln89_reg_320 <= mul_ln89_fu_166_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_fu_210_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + outputChanIdx_2 <= select_ln97_fu_295_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + outputCount_2 <= ap_phi_mux_empty_phi_fu_112_p4; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_176_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state3))) begin + outputRow_7_0 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_176_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state3))) begin + outputRow_7_1 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_176_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state3))) begin + outputRow_7_2 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_176_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state3))) begin + outputRow_7_3 <= p_read; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_reg_333 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin + ap_phi_mux_empty_phi_fu_112_p4 = 16'd0; + end else begin + ap_phi_mux_empty_phi_fu_112_p4 = empty_reg_109; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_176_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state3))) begin + ap_sig_allocacmp_outputRow_7_0_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_7_0_load = outputRow_7_0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_176_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state3))) begin + ap_sig_allocacmp_outputRow_7_1_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_7_1_load = outputRow_7_1; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_176_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state3))) begin + ap_sig_allocacmp_outputRow_7_2_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_7_2_load = outputRow_7_2; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_176_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state3))) begin + ap_sig_allocacmp_outputRow_7_3_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_7_3_load = outputRow_7_3; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3))) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_fu_210_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln87_fu_204_p2 = (outputCount_2 + 16'd1); + +assign add_ln94_8_fu_232_p2 = (mul_ln89_reg_320 + zext_ln94_21_fu_228_p1); + +assign add_ln94_fu_157_p2 = ((sub_ln94_cast_fu_149_p1) + (zext_ln94_20_fu_153_p1)); + +assign add_ln96_fu_283_p2 = (outputChanIdx_2 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign bitcast_ln94_22_fu_250_p1 = ap_sig_allocacmp_outputRow_7_1_load; + +assign bitcast_ln94_23_fu_258_p1 = ap_sig_allocacmp_outputRow_7_2_load; + +assign bitcast_ln94_24_fu_266_p1 = ap_sig_allocacmp_outputRow_7_3_load; + +assign bitcast_ln94_fu_242_p1 = ap_sig_allocacmp_outputRow_7_0_load; + +assign icmp_ln88_fu_210_p2 = ((add_ln87_fu_204_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign icmp_ln97_fu_289_p2 = ((add_ln96_fu_283_p2 == 16'd250) ? 1'b1 : 1'b0); + +assign mul_ln89_fu_166_p1 = 16'd250; + +assign out_data_address1 = zext_ln94_22_fu_237_p1; + +assign out_data_d1 = {{{{bitcast_ln94_24_fu_266_p1}, {bitcast_ln94_23_fu_258_p1}}, {bitcast_ln94_22_fu_250_p1}}, {bitcast_ln94_fu_242_p1}}; + +assign select_ln97_fu_295_p3 = ((icmp_ln97_fu_289_p2[0:0] == 1'b1) ? 16'd0 : add_ln96_fu_283_p2); + +assign sub_ln94_cast_fu_149_p1 = (sub_ln94_fu_143_p2); + +assign sub_ln94_fu_143_p2 = (zext_ln94_fu_127_p1 - zext_ln94_19_fu_139_p1); + +assign tmp_fu_119_p3 = {{indices_01_dout}, {4'd0}}; + +assign tmp_s_fu_131_p3 = {{indices_01_dout}, {1'd0}}; + +assign trunc_ln86_fu_176_p1 = outputCount_2[1:0]; + +assign trunc_ln94_fu_224_p1 = outputChanIdx_2[8:0]; + +assign zext_ln94_19_fu_139_p1 = tmp_s_fu_131_p3; + +assign zext_ln94_20_fu_153_p1 = indices_12_dout; + +assign zext_ln94_21_fu_228_p1 = trunc_ln94_fu_224_p1; + +assign zext_ln94_22_fu_237_p1 = add_ln94_8_fu_232_p2; + +assign zext_ln94_fu_127_p1 = tmp_fu_119_p3; + +endmodule //td_fused_top_tdf12_writeOutputs_unaligned +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state9 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [4:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [4:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [3:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_0_ce0; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [3:0] out_idx_reg_76; +reg [3:0] out_idx_reg_76_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_pp0_stage0_11001; +reg [3:0] out_idx_reg_76_pp0_iter2_reg; +reg [3:0] out_idx_reg_76_pp0_iter3_reg; +reg [3:0] out_idx_reg_76_pp0_iter4_reg; +reg [3:0] out_idx_reg_76_pp0_iter5_reg; +wire [3:0] add_ln59_fu_94_p2; +reg [3:0] add_ln59_reg_147; +reg ap_enable_reg_pp0_iter0; +wire [0:0] icmp_ln45_fu_100_p2; +reg [0:0] icmp_ln45_reg_152; +reg [0:0] icmp_ln45_reg_152_pp0_iter1_reg; +reg [0:0] icmp_ln45_reg_152_pp0_iter2_reg; +reg [0:0] icmp_ln45_reg_152_pp0_iter3_reg; +reg [0:0] icmp_ln45_reg_152_pp0_iter4_reg; +reg [0:0] icmp_ln45_reg_152_pp0_iter5_reg; +wire [4:0] i_1_1_fu_106_p3; +reg [4:0] i_1_1_reg_156; +wire [0:0] icmp_ln55_fu_120_p2; +reg [0:0] icmp_ln55_reg_161; +wire [15:0] select_ln55_fu_135_p3; +reg [15:0] select_ln55_reg_176; +reg ap_enable_reg_pp0_iter2; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg [3:0] ap_phi_mux_out_idx_phi_fu_80_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln55_1_fu_126_p1; +wire [63:0] zext_ln55_fu_131_p1; +wire [63:0] zext_ln45_fu_142_p1; +wire [15:0] grp_fu_88_p2; +wire [4:0] or_ln55_fu_114_p2; +wire ap_CS_fsm_state9; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U25( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(select_ln55_reg_176), + .din1(accum_in_0_q0), + .dout(grp_fu_88_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_76 <= 4'd0; + end else if (((icmp_ln45_reg_152 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + out_idx_reg_76 <= add_ln59_reg_147; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln59_reg_147 <= add_ln59_fu_94_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln45_fu_100_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + i_1_1_reg_156[4 : 1] <= i_1_1_fu_106_p3[4 : 1]; + icmp_ln55_reg_161 <= icmp_ln55_fu_120_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln45_reg_152 <= icmp_ln45_fu_100_p2; + icmp_ln45_reg_152_pp0_iter1_reg <= icmp_ln45_reg_152; + out_idx_reg_76_pp0_iter1_reg <= out_idx_reg_76; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln45_reg_152_pp0_iter2_reg <= icmp_ln45_reg_152_pp0_iter1_reg; + icmp_ln45_reg_152_pp0_iter3_reg <= icmp_ln45_reg_152_pp0_iter2_reg; + icmp_ln45_reg_152_pp0_iter4_reg <= icmp_ln45_reg_152_pp0_iter3_reg; + icmp_ln45_reg_152_pp0_iter5_reg <= icmp_ln45_reg_152_pp0_iter4_reg; + out_idx_reg_76_pp0_iter2_reg <= out_idx_reg_76_pp0_iter1_reg; + out_idx_reg_76_pp0_iter3_reg <= out_idx_reg_76_pp0_iter2_reg; + out_idx_reg_76_pp0_iter4_reg <= out_idx_reg_76_pp0_iter3_reg; + out_idx_reg_76_pp0_iter5_reg <= out_idx_reg_76_pp0_iter4_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln45_reg_152 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln55_reg_176 <= select_ln55_fu_135_p3; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter6 == 1'b1))) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_reg_152_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter6 == 1'b1))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln45_fu_100_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln45_reg_152 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_out_idx_phi_fu_80_p4 = add_ln59_reg_147; + end else begin + ap_phi_mux_out_idx_phi_fu_80_p4 = out_idx_reg_76; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln45_fu_100_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter6 == 1'b1) & (ap_enable_reg_pp0_iter5 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln45_fu_100_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter6 == 1'b1) & (ap_enable_reg_pp0_iter5 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state9; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_0_address0 = zext_ln55_fu_131_p1; + +assign accum_in_0_address1 = zext_ln55_1_fu_126_p1; + +assign accum_out_address0 = zext_ln45_fu_142_p1; + +assign accum_out_d0 = grp_fu_88_p2; + +assign add_ln59_fu_94_p2 = (ap_phi_mux_out_idx_phi_fu_80_p4 + 4'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign i_1_1_fu_106_p3 = {{ap_phi_mux_out_idx_phi_fu_80_p4}, {1'd0}}; + +assign icmp_ln45_fu_100_p2 = ((ap_phi_mux_out_idx_phi_fu_80_p4 == 4'd14) ? 1'b1 : 1'b0); + +assign icmp_ln55_fu_120_p2 = ((or_ln55_fu_114_p2 < 5'd27) ? 1'b1 : 1'b0); + +assign or_ln55_fu_114_p2 = (i_1_1_fu_106_p3 | 5'd1); + +assign select_ln55_fu_135_p3 = ((icmp_ln55_reg_161[0:0] == 1'b1) ? accum_in_0_q1 : 16'd0); + +assign zext_ln45_fu_142_p1 = out_idx_reg_76_pp0_iter5_reg; + +assign zext_ln55_1_fu_126_p1 = or_ln55_fu_114_p2; + +assign zext_ln55_fu_131_p1 = i_1_1_reg_156; + +always @ (posedge ap_clk) begin + i_1_1_reg_156[0] <= 1'b0; +end + +endmodule //td_fused_top_tdf1_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_address0, + accum_in_ce0, + accum_in_q0, + accum_in_address1, + accum_in_ce1, + accum_in_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state8 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [3:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; +output [3:0] accum_in_address1; +output accum_in_ce1; +input [15:0] accum_in_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg accum_in_ce0; +reg accum_in_ce1; +reg accum_out_ce0; +reg accum_out_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [2:0] out_idx_reg_72; +reg [2:0] out_idx_reg_72_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_pp0_stage0_11001; +reg [2:0] out_idx_reg_72_pp0_iter2_reg; +reg [2:0] out_idx_reg_72_pp0_iter3_reg; +reg [2:0] out_idx_reg_72_pp0_iter4_reg; +wire [2:0] add_ln89_fu_91_p2; +reg [2:0] add_ln89_reg_132; +reg ap_enable_reg_pp0_iter0; +wire [0:0] icmp_ln75_fu_97_p2; +reg [0:0] icmp_ln75_reg_137; +reg [0:0] icmp_ln75_reg_137_pp0_iter1_reg; +reg [0:0] icmp_ln75_reg_137_pp0_iter2_reg; +reg [0:0] icmp_ln75_reg_137_pp0_iter3_reg; +reg [0:0] icmp_ln75_reg_137_pp0_iter4_reg; +reg ap_enable_reg_pp0_iter1; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg [2:0] ap_phi_mux_out_idx_phi_fu_76_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln85_fu_111_p1; +wire [63:0] zext_ln85_1_fu_122_p1; +wire [63:0] zext_ln75_fu_127_p1; +wire [15:0] grp_fu_84_p2; +wire [3:0] i_1_1_fu_103_p3; +wire [3:0] or_ln85_fu_116_p2; +wire ap_CS_fsm_state8; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U29( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(accum_in_q0), + .din1(accum_in_q1), + .dout(grp_fu_84_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + out_idx_reg_72 <= 3'd0; + end else if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln75_reg_137 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + out_idx_reg_72 <= add_ln89_reg_132; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln89_reg_132 <= add_ln89_fu_91_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln75_reg_137 <= icmp_ln75_fu_97_p2; + icmp_ln75_reg_137_pp0_iter1_reg <= icmp_ln75_reg_137; + out_idx_reg_72_pp0_iter1_reg <= out_idx_reg_72; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln75_reg_137_pp0_iter2_reg <= icmp_ln75_reg_137_pp0_iter1_reg; + icmp_ln75_reg_137_pp0_iter3_reg <= icmp_ln75_reg_137_pp0_iter2_reg; + icmp_ln75_reg_137_pp0_iter4_reg <= icmp_ln75_reg_137_pp0_iter3_reg; + out_idx_reg_72_pp0_iter2_reg <= out_idx_reg_72_pp0_iter1_reg; + out_idx_reg_72_pp0_iter3_reg <= out_idx_reg_72_pp0_iter2_reg; + out_idx_reg_72_pp0_iter4_reg <= out_idx_reg_72_pp0_iter3_reg; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_ce1 = 1'b1; + end else begin + accum_in_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln75_reg_137_pp0_iter4_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln75_fu_97_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln75_reg_137 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_out_idx_phi_fu_76_p4 = add_ln89_reg_132; + end else begin + ap_phi_mux_out_idx_phi_fu_76_p4 = out_idx_reg_72; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln75_fu_97_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter5 == 1'b1) & (ap_enable_reg_pp0_iter4 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln75_fu_97_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter5 == 1'b1) & (ap_enable_reg_pp0_iter4 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state8; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln85_1_fu_122_p1; + +assign accum_in_address1 = zext_ln85_fu_111_p1; + +assign accum_out_address0 = zext_ln75_fu_127_p1; + +assign accum_out_d0 = grp_fu_84_p2; + +assign add_ln89_fu_91_p2 = (ap_phi_mux_out_idx_phi_fu_76_p4 + 3'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign i_1_1_fu_103_p3 = {{ap_phi_mux_out_idx_phi_fu_76_p4}, {1'd0}}; + +assign icmp_ln75_fu_97_p2 = ((ap_phi_mux_out_idx_phi_fu_76_p4 == 3'd7) ? 1'b1 : 1'b0); + +assign or_ln85_fu_116_p2 = (i_1_1_fu_103_p3 | 4'd1); + +assign zext_ln75_fu_127_p1 = out_idx_reg_72_pp0_iter4_reg; + +assign zext_ln85_1_fu_122_p1 = or_ln85_fu_116_p2; + +assign zext_ln85_fu_111_p1 = i_1_1_fu_103_p3; + +endmodule //td_fused_top_tdf1_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_accum_3 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_18, + accum_in_18_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 7'd1; +parameter ap_ST_fsm_state2 = 7'd2; +parameter ap_ST_fsm_state3 = 7'd4; +parameter ap_ST_fsm_state4 = 7'd8; +parameter ap_ST_fsm_state5 = 7'd16; +parameter ap_ST_fsm_state6 = 7'd32; +parameter ap_ST_fsm_state7 = 7'd64; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_18; +output accum_in_18_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_18; +reg accum_in_18_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [6:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [2:0] add_ln102_fu_74_p2; +reg [2:0] add_ln102_reg_91; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln102_fu_85_p2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state7; +reg [2:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln102_fu_80_p1; +reg [15:0] accum_in_18_preg; +reg [6:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 7'd1; +#0 accum_in_18_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U32( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_q0), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_18_preg <= 16'd0; + end else begin + if (((icmp_ln102_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_18_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln102_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 3'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + i_1_1_reg_44 <= add_ln102_reg_91; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln102_reg_91 <= add_ln102_fu_74_p2; + end +end + +always @ (*) begin + if (((icmp_ln102_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_18 = sum_01_reg_55; + end else begin + accum_in_18 = accum_in_18_preg; + end +end + +always @ (*) begin + if (((icmp_ln102_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_18_ap_vld = 1'b1; + end else begin + accum_in_18_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln102_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln102_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln102_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln102_fu_80_p1; + +assign add_ln102_fu_74_p2 = (i_1_1_reg_44 + 3'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln102_fu_85_p2 = ((i_1_1_reg_44 == 3'd7) ? 1'b1 : 1'b0); + +assign zext_ln102_fu_80_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf1_accum_3 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf1_adjustments_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 48; +parameter AWIDTH = 4; +parameter MEM_SIZE = 16; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf1_adjustments( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd48; +parameter AddressRange = 32'd16; +parameter AddressWidth = 32'd4; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf1_adjustments_ram td_fused_top_tdf1_adjustments_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 17'd1; +parameter ap_ST_fsm_state2 = 17'd2; +parameter ap_ST_fsm_state3 = 17'd4; +parameter ap_ST_fsm_state4 = 17'd8; +parameter ap_ST_fsm_state5 = 17'd16; +parameter ap_ST_fsm_state6 = 17'd32; +parameter ap_ST_fsm_state7 = 17'd64; +parameter ap_ST_fsm_state8 = 17'd128; +parameter ap_ST_fsm_state9 = 17'd256; +parameter ap_ST_fsm_state10 = 17'd512; +parameter ap_ST_fsm_state11 = 17'd1024; +parameter ap_ST_fsm_state12 = 17'd2048; +parameter ap_ST_fsm_state13 = 17'd4096; +parameter ap_ST_fsm_state14 = 17'd8192; +parameter ap_ST_fsm_state15 = 17'd16384; +parameter ap_ST_fsm_state16 = 17'd32768; +parameter ap_ST_fsm_state17 = 17'd65536; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_read; +output [3:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [3:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg input_indices_23_read; + +reg ap_done_reg; + reg [16:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +wire ap_CS_fsm_state4; +reg [15:0] tmp_74_i_i_reg_167; +reg [15:0] tmp_75_i_i_reg_172; +wire [15:0] grp_fu_81_p2; +reg [15:0] sub_i_i_i_reg_177; +wire ap_CS_fsm_state8; +wire ap_CS_fsm_state9; +wire [15:0] grp_fu_86_p2; +reg [15:0] mul_i_i_i_reg_187; +wire ap_CS_fsm_state12; +wire ap_CS_fsm_state13; +wire [63:0] zext_ln220_fu_90_p1; +reg ap_block_state1; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_77_p1; +wire [15:0] grp_fu_81_p1; +wire [15:0] grp_fu_86_p1; +wire [15:0] trunc_ln220_fu_95_p1; +wire [15:0] grp_fu_77_p2; +wire ap_CS_fsm_state17; +wire [15:0] bitcast_ln648_fu_132_p1; +wire [0:0] tmp_fu_136_p3; +reg [16:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 17'd1; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U36( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(mul_i_i_i_reg_187), + .din1(grp_fu_77_p1), + .dout(grp_fu_77_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U37( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sums_read), + .din1(grp_fu_81_p1), + .dout(grp_fu_81_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U38( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_177), + .din1(grp_fu_86_p1), + .dout(grp_fu_86_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + mul_i_i_i_reg_187 <= grp_fu_86_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sub_i_i_i_reg_177 <= grp_fu_81_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tmp_74_i_i_reg_167 <= {{adjustments_q0[31:16]}}; + tmp_75_i_i_reg_172 <= {{adjustments_q0[47:32]}}; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (~((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign adjustments_address0 = zext_ln220_fu_90_p1; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_return = ((tmp_fu_136_p3[0:0] == 1'b1) ? 16'd0 : grp_fu_77_p2); + +assign bitcast_ln648_fu_132_p1 = grp_fu_77_p2; + +assign grp_fu_77_p1 = tmp_75_i_i_reg_172; + +assign grp_fu_81_p1 = trunc_ln220_fu_95_p1; + +assign grp_fu_86_p1 = tmp_74_i_i_reg_167; + +assign tmp_fu_136_p3 = bitcast_ln648_fu_132_p1[32'd15]; + +assign trunc_ln220_fu_95_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_90_p1 = input_indices_23_dout; + +endmodule //td_fused_top_tdf1_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_q0, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state8 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [4:0] ifmap_vec_address0; +output ifmap_vec_ce0; +input [15:0] ifmap_vec_q0; +output [4:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +input [15:0] weight_vecs_0_q0; +output [4:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_ce0; +reg weight_vecs_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [4:0] indvar_flatten21_reg_93; +reg [1:0] ii_reg_104; +reg [3:0] indvar_flatten_reg_116; +reg [1:0] jj_reg_127; +reg [1:0] ic_reg_138; +wire [4:0] add_ln147_6_fu_156_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln147_fu_162_p2; +reg [0:0] icmp_ln147_reg_466; +reg [0:0] icmp_ln147_reg_466_pp0_iter1_reg; +reg [0:0] icmp_ln147_reg_466_pp0_iter2_reg; +reg [0:0] icmp_ln147_reg_466_pp0_iter3_reg; +reg [0:0] icmp_ln147_reg_466_pp0_iter4_reg; +wire [1:0] add_ln147_fu_168_p2; +reg [1:0] add_ln147_reg_470; +wire [0:0] icmp_ln148_fu_174_p2; +reg [0:0] icmp_ln148_reg_476; +wire [1:0] select_ln147_17_fu_180_p3; +reg [1:0] select_ln147_17_reg_485; +wire [3:0] select_ln148_18_fu_194_p3; +wire [1:0] select_ln148_16_fu_359_p3; +reg [1:0] select_ln148_16_reg_497; +reg ap_enable_reg_pp0_iter1; +wire [4:0] p_fu_445_p2; +reg [4:0] p_reg_512; +reg [4:0] p_reg_512_pp0_iter2_reg; +reg [4:0] p_reg_512_pp0_iter3_reg; +reg [4:0] p_reg_512_pp0_iter4_reg; +wire [1:0] add_ln149_fu_451_p2; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg [1:0] ap_phi_mux_ii_phi_fu_108_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_131_p4; +wire [63:0] p_cast27_fu_439_p1; +wire [63:0] idxprom30_fu_457_p1; +wire [15:0] grp_fu_149_p2; +wire [3:0] add_ln148_6_fu_188_p2; +wire [3:0] shl_ln_fu_206_p3; +wire [4:0] zext_ln150_7_fu_214_p1; +wire [4:0] zext_ln150_fu_202_p1; +wire [4:0] sub_ln150_fu_218_p2; +wire [4:0] zext_ln150_8_fu_224_p1; +wire [4:0] add_ln150_fu_228_p2; +wire [4:0] shl_ln150_fu_234_p2; +wire [3:0] tmp_s_fu_256_p3; +wire [4:0] tmp_145_cast_fu_263_p1; +wire [4:0] select_ln147_22_cast_fu_253_p1; +wire [4:0] empty_122_fu_267_p2; +wire [3:0] shl_ln150_mid1_fu_280_p3; +wire [4:0] zext_ln150_13_fu_287_p1; +wire [4:0] zext_ln150_12_fu_277_p1; +wire [4:0] sub_ln150_6_fu_291_p2; +wire [4:0] shl_ln150_1_fu_304_p2; +wire [4:0] sub_ln150_7_fu_310_p2; +wire [4:0] sub_ln150_1_fu_240_p2; +wire [0:0] icmp_ln149_fu_328_p2; +wire [0:0] xor_ln147_fu_323_p2; +wire [1:0] select_ln147_fu_246_p3; +wire [0:0] and_ln147_fu_334_p2; +wire [0:0] or_ln148_fu_346_p2; +wire [1:0] add_ln148_fu_340_p2; +wire [5:0] sext_ln150_fu_273_p1; +wire [5:0] select_ln148_21_cast_fu_367_p1; +wire [5:0] empty_123_fu_371_p2; +wire [2:0] empty_125_fu_381_p1; +wire [4:0] p_shl_cast_fu_385_p3; +wire [4:0] empty_124_fu_377_p1; +wire [4:0] select_ln147_18_fu_297_p3; +wire [4:0] zext_ln150_14_fu_399_p1; +wire [4:0] add_ln150_6_fu_403_p2; +wire [4:0] shl_ln150_2_fu_409_p2; +wire [4:0] sub_ln150_8_fu_415_p2; +wire [4:0] select_ln147_19_fu_316_p3; +wire [1:0] select_ln148_fu_351_p3; +wire [4:0] empty_126_fu_393_p2; +wire [4:0] select_ln148_cast_fu_429_p1; +wire [4:0] empty_127_fu_433_p2; +wire [4:0] select_ln148_17_fu_421_p3; +wire ap_CS_fsm_state8; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U20( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_q0), + .din1(weight_vecs_0_q0), + .dout(grp_fu_149_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_466 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_reg_138 <= add_ln149_fu_451_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_reg_138 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_466 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ii_reg_104 <= select_ln147_17_reg_485; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_104 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_162_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten21_reg_93 <= add_ln147_6_fu_156_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten21_reg_93 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_162_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_116 <= select_ln148_18_fu_194_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_116 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_466_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + jj_reg_127 <= select_ln148_16_reg_497; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_127 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_162_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln147_reg_470 <= add_ln147_fu_168_p2; + icmp_ln148_reg_476 <= icmp_ln148_fu_174_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln147_reg_466 <= icmp_ln147_fu_162_p2; + icmp_ln147_reg_466_pp0_iter1_reg <= icmp_ln147_reg_466; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln147_reg_466_pp0_iter2_reg <= icmp_ln147_reg_466_pp0_iter1_reg; + icmp_ln147_reg_466_pp0_iter3_reg <= icmp_ln147_reg_466_pp0_iter2_reg; + icmp_ln147_reg_466_pp0_iter4_reg <= icmp_ln147_reg_466_pp0_iter3_reg; + p_reg_512_pp0_iter2_reg <= p_reg_512; + p_reg_512_pp0_iter3_reg <= p_reg_512_pp0_iter2_reg; + p_reg_512_pp0_iter4_reg <= p_reg_512_pp0_iter3_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_466 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + p_reg_512 <= p_fu_445_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_162_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln147_17_reg_485 <= select_ln147_17_fu_180_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_466 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_16_reg_497 <= select_ln148_16_fu_359_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_fu_162_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln147_reg_466 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_108_p4 = select_ln147_17_reg_485; + end else begin + ap_phi_mux_ii_phi_fu_108_p4 = ii_reg_104; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_466_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_131_p4 = select_ln148_16_reg_497; + end else begin + ap_phi_mux_jj_phi_fu_131_p4 = jj_reg_127; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_466_pp0_iter4_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter5 == 1'b1) & (ap_enable_reg_pp0_iter4 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter5 == 1'b1) & (ap_enable_reg_pp0_iter4 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state8; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_6_fu_156_p2 = (indvar_flatten21_reg_93 + 5'd1); + +assign add_ln147_fu_168_p2 = (ap_phi_mux_ii_phi_fu_108_p4 + 2'd1); + +assign add_ln148_6_fu_188_p2 = (indvar_flatten_reg_116 + 4'd1); + +assign add_ln148_fu_340_p2 = (select_ln147_fu_246_p3 + 2'd1); + +assign add_ln149_fu_451_p2 = (select_ln148_fu_351_p3 + 2'd1); + +assign add_ln150_6_fu_403_p2 = (select_ln147_18_fu_297_p3 + zext_ln150_14_fu_399_p1); + +assign add_ln150_fu_228_p2 = (sub_ln150_fu_218_p2 + zext_ln150_8_fu_224_p1); + +assign and_ln147_fu_334_p2 = (xor_ln147_fu_323_p2 & icmp_ln149_fu_328_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign empty_122_fu_267_p2 = (tmp_145_cast_fu_263_p1 - select_ln147_22_cast_fu_253_p1); + +assign empty_123_fu_371_p2 = ((sext_ln150_fu_273_p1) + (select_ln148_21_cast_fu_367_p1)); + +assign empty_124_fu_377_p1 = empty_123_fu_371_p2[4:0]; + +assign empty_125_fu_381_p1 = empty_123_fu_371_p2[2:0]; + +assign empty_126_fu_393_p2 = (p_shl_cast_fu_385_p3 - empty_124_fu_377_p1); + +assign empty_127_fu_433_p2 = (empty_126_fu_393_p2 + select_ln148_cast_fu_429_p1); + +assign icmp_ln147_fu_162_p2 = ((indvar_flatten21_reg_93 == 5'd27) ? 1'b1 : 1'b0); + +assign icmp_ln148_fu_174_p2 = ((indvar_flatten_reg_116 == 4'd9) ? 1'b1 : 1'b0); + +assign icmp_ln149_fu_328_p2 = ((ic_reg_138 == 2'd3) ? 1'b1 : 1'b0); + +assign idxprom30_fu_457_p1 = p_reg_512_pp0_iter4_reg; + +assign ifmap_vec_address0 = p_cast27_fu_439_p1; + +assign or_ln148_fu_346_p2 = (icmp_ln148_reg_476 | and_ln147_fu_334_p2); + +assign p_cast27_fu_439_p1 = empty_127_fu_433_p2; + +assign p_fu_445_p2 = (select_ln148_17_fu_421_p3 + select_ln148_cast_fu_429_p1); + +assign p_shl_cast_fu_385_p3 = {{empty_125_fu_381_p1}, {2'd0}}; + +assign products_0_address0 = idxprom30_fu_457_p1; + +assign products_0_d0 = grp_fu_149_p2; + +assign select_ln147_17_fu_180_p3 = ((icmp_ln148_fu_174_p2[0:0] == 1'b1) ? add_ln147_fu_168_p2 : ap_phi_mux_ii_phi_fu_108_p4); + +assign select_ln147_18_fu_297_p3 = ((icmp_ln148_reg_476[0:0] == 1'b1) ? sub_ln150_6_fu_291_p2 : sub_ln150_fu_218_p2); + +assign select_ln147_19_fu_316_p3 = ((icmp_ln148_reg_476[0:0] == 1'b1) ? sub_ln150_7_fu_310_p2 : sub_ln150_1_fu_240_p2); + +assign select_ln147_22_cast_fu_253_p1 = select_ln147_17_reg_485; + +assign select_ln147_fu_246_p3 = ((icmp_ln148_reg_476[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_131_p4); + +assign select_ln148_16_fu_359_p3 = ((and_ln147_fu_334_p2[0:0] == 1'b1) ? add_ln148_fu_340_p2 : select_ln147_fu_246_p3); + +assign select_ln148_17_fu_421_p3 = ((and_ln147_fu_334_p2[0:0] == 1'b1) ? sub_ln150_8_fu_415_p2 : select_ln147_19_fu_316_p3); + +assign select_ln148_18_fu_194_p3 = ((icmp_ln148_fu_174_p2[0:0] == 1'b1) ? 4'd1 : add_ln148_6_fu_188_p2); + +assign select_ln148_21_cast_fu_367_p1 = select_ln148_16_fu_359_p3; + +assign select_ln148_cast_fu_429_p1 = select_ln148_fu_351_p3; + +assign select_ln148_fu_351_p3 = ((or_ln148_fu_346_p2[0:0] == 1'b1) ? 2'd0 : ic_reg_138); + +assign sext_ln150_fu_273_p1 = (empty_122_fu_267_p2); + +assign shl_ln150_1_fu_304_p2 = sub_ln150_6_fu_291_p2 << 5'd2; + +assign shl_ln150_2_fu_409_p2 = add_ln150_6_fu_403_p2 << 5'd2; + +assign shl_ln150_fu_234_p2 = add_ln150_fu_228_p2 << 5'd2; + +assign shl_ln150_mid1_fu_280_p3 = {{add_ln147_reg_470}, {2'd0}}; + +assign shl_ln_fu_206_p3 = {{ii_reg_104}, {2'd0}}; + +assign sub_ln150_1_fu_240_p2 = (shl_ln150_fu_234_p2 - add_ln150_fu_228_p2); + +assign sub_ln150_6_fu_291_p2 = (zext_ln150_13_fu_287_p1 - zext_ln150_12_fu_277_p1); + +assign sub_ln150_7_fu_310_p2 = (shl_ln150_1_fu_304_p2 - sub_ln150_6_fu_291_p2); + +assign sub_ln150_8_fu_415_p2 = (shl_ln150_2_fu_409_p2 - add_ln150_6_fu_403_p2); + +assign sub_ln150_fu_218_p2 = (zext_ln150_7_fu_214_p1 - zext_ln150_fu_202_p1); + +assign tmp_145_cast_fu_263_p1 = tmp_s_fu_256_p3; + +assign tmp_s_fu_256_p3 = {{select_ln147_17_reg_485}, {2'd0}}; + +assign weight_vecs_0_address0 = p_cast27_fu_439_p1; + +assign xor_ln147_fu_323_p2 = (icmp_ln148_reg_476 ^ 1'd1); + +assign zext_ln150_12_fu_277_p1 = add_ln147_reg_470; + +assign zext_ln150_13_fu_287_p1 = shl_ln150_mid1_fu_280_p3; + +assign zext_ln150_14_fu_399_p1 = add_ln148_fu_340_p2; + +assign zext_ln150_7_fu_214_p1 = shl_ln_fu_206_p3; + +assign zext_ln150_8_fu_224_p1 = ap_phi_mux_jj_phi_fu_131_p4; + +assign zext_ln150_fu_202_p1 = ii_reg_104; + +endmodule //td_fused_top_tdf1_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf1_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 9; +parameter MEM_SIZE = 432; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf1_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd432; +parameter AddressWidth = 32'd9; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf1_filters_ram td_fused_top_tdf1_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + input_indices_2_out_din, + input_indices_2_out_full_n, + input_indices_2_out_write, + input_indices_2_out1_din, + input_indices_2_out1_full_n, + input_indices_2_out1_write, + output_indices_0_din, + output_indices_0_full_n, + output_indices_0_write, + output_indices_1_din, + output_indices_1_full_n, + output_indices_1_write, + resetMaximum_din, + resetMaximum_full_n, + resetMaximum_write, + storeOutput_din, + storeOutput_full_n, + storeOutput_write, + ap_return_0, + ap_return_1 +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [3:0] input_indices_2_out_din; +input input_indices_2_out_full_n; +output input_indices_2_out_write; +output [3:0] input_indices_2_out1_din; +input input_indices_2_out1_full_n; +output input_indices_2_out1_write; +output [6:0] output_indices_0_din; +input output_indices_0_full_n; +output output_indices_0_write; +output [13:0] output_indices_1_din; +input output_indices_1_full_n; +output output_indices_1_write; +output resetMaximum_din; +input resetMaximum_full_n; +output resetMaximum_write; +output storeOutput_din; +input storeOutput_full_n; +output storeOutput_write; +output [15:0] ap_return_0; +output [15:0] ap_return_1; + +reg ap_done; +reg ap_idle; +reg start_write; +reg input_indices_2_out_write; +reg input_indices_2_out1_write; +reg output_indices_0_write; +reg output_indices_1_write; +reg resetMaximum_write; +reg storeOutput_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [1:0] i_p_3; +reg [1:0] j_p_3; +reg [15:0] i_7; +reg [15:0] j_7; +reg [15:0] k_7; +reg [15:0] i_out_3; +reg [15:0] j_out_3; +reg input_indices_2_out_blk_n; +reg input_indices_2_out1_blk_n; +reg output_indices_0_blk_n; +reg output_indices_1_blk_n; +reg resetMaximum_blk_n; +reg storeOutput_blk_n; +wire [1:0] select_ln163_fu_338_p3; +reg ap_block_state1; +wire [0:0] or_ln163_fu_312_p2; +wire [1:0] select_ln163_1_fu_346_p3; +wire [15:0] select_ln168_fu_278_p3; +wire [0:0] and_ln163_1_fu_306_p2; +wire [15:0] select_ln163_2_fu_360_p3; +wire [0:0] and_ln153_fu_354_p2; +wire [15:0] select_ln163_3_fu_388_p3; +wire [0:0] and_ln156_fu_294_p2; +wire [15:0] select_ln168_1_fu_286_p3; +wire [15:0] select_ln163_4_fu_396_p3; +wire [3:0] trunc_ln149_fu_182_p1; +wire [1:0] or_ln145_fu_126_p2; +wire [0:0] icmp_ln146_fu_139_p2; +wire [0:0] icmp_ln146_1_fu_145_p2; +wire [15:0] zext_ln147_fu_114_p1; +wire [15:0] zext_ln148_fu_122_p1; +wire [1:0] add_ln152_fu_206_p2; +wire [1:0] add_ln155_fu_218_p2; +wire [15:0] add_ln158_fu_230_p2; +wire [15:0] add_ln162_fu_248_p2; +wire [15:0] add_ln167_fu_266_p2; +wire [0:0] icmp_ln168_fu_272_p2; +wire [15:0] add_ln166_fu_260_p2; +wire [0:0] icmp_ln153_fu_212_p2; +wire [0:0] icmp_ln156_fu_224_p2; +wire [0:0] icmp_ln159_fu_236_p2; +wire [0:0] icmp_ln163_fu_254_p2; +wire [0:0] and_ln163_fu_300_p2; +wire [0:0] xor_ln156_fu_318_p2; +wire [0:0] and_ln156_1_fu_324_p2; +wire [1:0] select_ln156_fu_330_p3; +wire [15:0] add_ln161_fu_242_p2; +wire [0:0] xor_ln159_fu_368_p2; +wire [0:0] and_ln159_fu_374_p2; +wire [15:0] select_ln159_fu_380_p3; +wire [15:0] add_ln147_fu_162_p2; +wire [15:0] add_ln148_fu_172_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_p_3 = 2'd0; +#0 j_p_3 = 2'd0; +#0 i_7 = 16'd0; +#0 j_7 = 16'd0; +#0 k_7 = 16'd0; +#0 i_out_3 = 16'd0; +#0 j_out_3 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln163_1_fu_306_p2))) begin + i_7 <= select_ln168_fu_278_p3; + i_out_3 <= select_ln168_1_fu_286_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (or_ln163_fu_312_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_p_3 <= select_ln163_fu_338_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln153_fu_354_p2))) begin + j_7 <= select_ln163_2_fu_360_p3; + j_out_3 <= select_ln163_4_fu_396_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + j_p_3 <= select_ln163_1_fu_346_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln156_fu_294_p2))) begin + k_7 <= select_ln163_3_fu_388_p3; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_blk_n = input_indices_2_out1_full_n; + end else begin + input_indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_write = 1'b1; + end else begin + input_indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_blk_n = input_indices_2_out_full_n; + end else begin + input_indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_write = 1'b1; + end else begin + input_indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_blk_n = output_indices_0_full_n; + end else begin + output_indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_write = 1'b1; + end else begin + output_indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_blk_n = output_indices_1_full_n; + end else begin + output_indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_write = 1'b1; + end else begin + output_indices_1_write = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_blk_n = resetMaximum_full_n; + end else begin + resetMaximum_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_write = 1'b1; + end else begin + resetMaximum_write = 1'b0; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_blk_n = storeOutput_full_n; + end else begin + storeOutput_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_write = 1'b1; + end else begin + storeOutput_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_fu_162_p2 = (i_7 + zext_ln147_fu_114_p1); + +assign add_ln148_fu_172_p2 = (j_7 + zext_ln148_fu_122_p1); + +assign add_ln152_fu_206_p2 = (j_p_3 + 2'd1); + +assign add_ln155_fu_218_p2 = (i_p_3 + 2'd1); + +assign add_ln158_fu_230_p2 = (k_7 + 16'd1); + +assign add_ln161_fu_242_p2 = (j_7 + 16'd2); + +assign add_ln162_fu_248_p2 = (j_out_3 + 16'd1); + +assign add_ln166_fu_260_p2 = (i_7 + 16'd2); + +assign add_ln167_fu_266_p2 = (i_out_3 + 16'd1); + +assign and_ln153_fu_354_p2 = (icmp_ln159_fu_236_p2 & and_ln156_fu_294_p2); + +assign and_ln156_1_fu_324_p2 = (xor_ln156_fu_318_p2 & icmp_ln153_fu_212_p2); + +assign and_ln156_fu_294_p2 = (icmp_ln156_fu_224_p2 & icmp_ln153_fu_212_p2); + +assign and_ln159_fu_374_p2 = (xor_ln159_fu_368_p2 & and_ln156_fu_294_p2); + +assign and_ln163_1_fu_306_p2 = (and_ln163_fu_300_p2 & and_ln156_fu_294_p2); + +assign and_ln163_fu_300_p2 = (icmp_ln163_fu_254_p2 & icmp_ln159_fu_236_p2); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign ap_return_0 = add_ln147_fu_162_p2; + +assign ap_return_1 = add_ln148_fu_172_p2; + +assign icmp_ln146_1_fu_145_p2 = ((j_p_3 == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln146_fu_139_p2 = ((i_p_3 == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln153_fu_212_p2 = ((add_ln152_fu_206_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln156_fu_224_p2 = ((add_ln155_fu_218_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln159_fu_236_p2 = ((add_ln158_fu_230_p2 == 16'd16) ? 1'b1 : 1'b0); + +assign icmp_ln163_fu_254_p2 = ((add_ln162_fu_248_p2 == 16'd112) ? 1'b1 : 1'b0); + +assign icmp_ln168_fu_272_p2 = ((add_ln167_fu_266_p2 == 16'd112) ? 1'b1 : 1'b0); + +assign input_indices_2_out1_din = trunc_ln149_fu_182_p1; + +assign input_indices_2_out_din = trunc_ln149_fu_182_p1; + +assign or_ln145_fu_126_p2 = (j_p_3 | i_p_3); + +assign or_ln163_fu_312_p2 = (icmp_ln153_fu_212_p2 | and_ln163_1_fu_306_p2); + +assign output_indices_0_din = i_out_3[6:0]; + +assign output_indices_1_din = j_out_3[13:0]; + +assign resetMaximum_din = ((or_ln145_fu_126_p2 == 2'd0) ? 1'b1 : 1'b0); + +assign select_ln156_fu_330_p3 = ((and_ln156_1_fu_324_p2[0:0] == 1'b1) ? add_ln155_fu_218_p2 : 2'd0); + +assign select_ln159_fu_380_p3 = ((and_ln159_fu_374_p2[0:0] == 1'b1) ? add_ln158_fu_230_p2 : 16'd0); + +assign select_ln163_1_fu_346_p3 = ((or_ln163_fu_312_p2[0:0] == 1'b1) ? 2'd0 : add_ln152_fu_206_p2); + +assign select_ln163_2_fu_360_p3 = ((and_ln163_1_fu_306_p2[0:0] == 1'b1) ? 16'd0 : add_ln161_fu_242_p2); + +assign select_ln163_3_fu_388_p3 = ((and_ln163_1_fu_306_p2[0:0] == 1'b1) ? 16'd0 : select_ln159_fu_380_p3); + +assign select_ln163_4_fu_396_p3 = ((and_ln163_1_fu_306_p2[0:0] == 1'b1) ? 16'd0 : add_ln162_fu_248_p2); + +assign select_ln163_fu_338_p3 = ((and_ln163_1_fu_306_p2[0:0] == 1'b1) ? 2'd0 : select_ln156_fu_330_p3); + +assign select_ln168_1_fu_286_p3 = ((icmp_ln168_fu_272_p2[0:0] == 1'b1) ? 16'd0 : add_ln167_fu_266_p2); + +assign select_ln168_fu_278_p3 = ((icmp_ln168_fu_272_p2[0:0] == 1'b1) ? 16'd0 : add_ln166_fu_260_p2); + +assign start_out = real_start; + +assign storeOutput_din = (icmp_ln146_fu_139_p2 & icmp_ln146_1_fu_145_p2); + +assign trunc_ln149_fu_182_p1 = k_7[3:0]; + +assign xor_ln156_fu_318_p2 = (icmp_ln156_fu_224_p2 ^ 1'd1); + +assign xor_ln159_fu_368_p2 = (icmp_ln159_fu_236_p2 ^ 1'd1); + +assign zext_ln147_fu_114_p1 = i_p_3; + +assign zext_ln148_fu_122_p1 = j_p_3; + +endmodule //td_fused_top_tdf1_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_poolOutputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + output_indices_04_dout, + output_indices_04_empty_n, + output_indices_04_read, + output_indices_15_dout, + output_indices_15_empty_n, + output_indices_15_read, + resetMaximum6_dout, + resetMaximum6_empty_n, + resetMaximum6_read, + storeOutput7_dout, + storeOutput7_empty_n, + storeOutput7_read, + p_read, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_state3 = 4'd4; +parameter ap_ST_fsm_state4 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [6:0] output_indices_04_dout; +input output_indices_04_empty_n; +output output_indices_04_read; +input [13:0] output_indices_15_dout; +input output_indices_15_empty_n; +output output_indices_15_read; +input [0:0] resetMaximum6_dout; +input resetMaximum6_empty_n; +output resetMaximum6_read; +input [0:0] storeOutput7_dout; +input storeOutput7_empty_n; +output storeOutput7_read; +input [15:0] p_read; +output [15:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg output_indices_04_read; +reg output_indices_15_read; +reg resetMaximum6_read; +reg storeOutput7_read; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] max_vals_3_0; +reg output_indices_04_blk_n; +wire ap_CS_fsm_state2; +reg output_indices_15_blk_n; +reg resetMaximum6_blk_n; +reg storeOutput7_blk_n; +reg [6:0] output_indices_04_read_reg_147; +reg [13:0] output_indices_15_read_reg_152; +wire [0:0] storeOutput7_read_read_fu_82_p2; +reg [0:0] storeOutput7_read_reg_157; +wire grp_tdf1_writeOutputs_unaligned_fu_88_ap_start; +wire grp_tdf1_writeOutputs_unaligned_fu_88_ap_done; +wire grp_tdf1_writeOutputs_unaligned_fu_88_ap_idle; +wire grp_tdf1_writeOutputs_unaligned_fu_88_ap_ready; +wire [15:0] grp_tdf1_writeOutputs_unaligned_fu_88_out_data_address1; +wire grp_tdf1_writeOutputs_unaligned_fu_88_out_data_ce1; +wire grp_tdf1_writeOutputs_unaligned_fu_88_out_data_we1; +wire [63:0] grp_tdf1_writeOutputs_unaligned_fu_88_out_data_d1; +reg grp_tdf1_writeOutputs_unaligned_fu_88_ap_start_reg; +wire ap_CS_fsm_state3; +wire ap_CS_fsm_state4; +reg ap_block_state4_on_subcall_done; +wire [15:0] select_ln24_fu_126_p3; +reg ap_block_state2; +reg ap_block_state1; +wire [0:0] grp_fu_110_p2; +wire [0:0] or_ln24_fu_120_p2; +reg grp_fu_110_ce; +reg [3:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 max_vals_3_0 = 16'd0; +#0 grp_tdf1_writeOutputs_unaligned_fu_88_ap_start_reg = 1'b0; +end + +td_fused_top_tdf1_writeOutputs_unaligned grp_tdf1_writeOutputs_unaligned_fu_88( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(grp_tdf1_writeOutputs_unaligned_fu_88_ap_start), + .ap_done(grp_tdf1_writeOutputs_unaligned_fu_88_ap_done), + .ap_idle(grp_tdf1_writeOutputs_unaligned_fu_88_ap_idle), + .ap_ready(grp_tdf1_writeOutputs_unaligned_fu_88_ap_ready), + .i(output_indices_04_read_reg_147), + .j(output_indices_15_read_reg_152), + .out_data_address1(grp_tdf1_writeOutputs_unaligned_fu_88_out_data_address1), + .out_data_ce1(grp_tdf1_writeOutputs_unaligned_fu_88_out_data_ce1), + .out_data_we1(grp_tdf1_writeOutputs_unaligned_fu_88_out_data_we1), + .out_data_d1(grp_tdf1_writeOutputs_unaligned_fu_88_out_data_d1), + .max_vals_3_0(max_vals_3_0) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U47( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_110_ce), + .din0(max_vals_3_0), + .din1(p_read), + .opcode(5'd4), + .dout(grp_fu_110_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + grp_tdf1_writeOutputs_unaligned_fu_88_ap_start_reg <= 1'b0; + end else begin + if ((1'b1 == ap_CS_fsm_state3)) begin + grp_tdf1_writeOutputs_unaligned_fu_88_ap_start_reg <= 1'b1; + end else if ((grp_tdf1_writeOutputs_unaligned_fu_88_ap_ready == 1'b1)) begin + grp_tdf1_writeOutputs_unaligned_fu_88_ap_start_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + max_vals_3_0 <= select_ln24_fu_126_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_04_read_reg_147 <= output_indices_04_dout; + output_indices_15_read_reg_152 <= output_indices_15_dout; + storeOutput7_read_reg_157 <= storeOutput7_dout; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_110_ce = 1'b1; + end else begin + grp_fu_110_ce = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_04_blk_n = output_indices_04_empty_n; + end else begin + output_indices_04_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_04_read = 1'b1; + end else begin + output_indices_04_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_15_blk_n = output_indices_15_empty_n; + end else begin + output_indices_15_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_15_read = 1'b1; + end else begin + output_indices_15_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + resetMaximum6_blk_n = resetMaximum6_empty_n; + end else begin + resetMaximum6_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + resetMaximum6_read = 1'b1; + end else begin + resetMaximum6_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + storeOutput7_blk_n = storeOutput7_empty_n; + end else begin + storeOutput7_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + storeOutput7_read = 1'b1; + end else begin + storeOutput7_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_82_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_82_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state3; + end else begin + ap_NS_fsm = ap_ST_fsm_state2; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +always @ (*) begin + ap_block_state2 = ((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)); +end + +always @ (*) begin + ap_block_state4_on_subcall_done = ((grp_tdf1_writeOutputs_unaligned_fu_88_ap_done == 1'b0) & (storeOutput7_read_reg_157 == 1'd1)); +end + +assign grp_tdf1_writeOutputs_unaligned_fu_88_ap_start = grp_tdf1_writeOutputs_unaligned_fu_88_ap_start_reg; + +assign or_ln24_fu_120_p2 = (resetMaximum6_dout | grp_fu_110_p2); + +assign out_data_address1 = grp_tdf1_writeOutputs_unaligned_fu_88_out_data_address1; + +assign out_data_ce1 = grp_tdf1_writeOutputs_unaligned_fu_88_out_data_ce1; + +assign out_data_d1 = grp_tdf1_writeOutputs_unaligned_fu_88_out_data_d1; + +assign out_data_we1 = grp_tdf1_writeOutputs_unaligned_fu_88_out_data_we1; + +assign select_ln24_fu_126_p3 = ((or_ln24_fu_120_p2[0:0] == 1'b1) ? p_read : max_vals_3_0); + +assign storeOutput7_read_read_fu_82_p2 = storeOutput7_dout; + +endmodule //td_fused_top_tdf1_poolOutputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_readFilters18 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_we0, + weight_vecs_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state7 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [8:0] filter_data_address0; +output filter_data_ce0; +input [15:0] filter_data_q0; +input [3:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [4:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +output weight_vecs_0_we0; +output [15:0] weight_vecs_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg input_indices_23_read; +reg weight_vecs_0_ce0; +reg weight_vecs_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +reg [4:0] indvar_flatten13_reg_117; +reg [1:0] ii_reg_128; +reg [3:0] indvar_flatten_reg_139; +reg [1:0] jj_reg_150; +reg [1:0] kk_reg_161; +wire [7:0] sext_ln47_fu_194_p1; +reg [7:0] sext_ln47_reg_448; +wire [4:0] add_ln47_6_fu_198_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln47_fu_204_p2; +reg [0:0] icmp_ln47_reg_458; +reg [0:0] icmp_ln47_reg_458_pp0_iter1_reg; +reg [0:0] icmp_ln47_reg_458_pp0_iter2_reg; +reg [0:0] icmp_ln47_reg_458_pp0_iter3_reg; +wire [0:0] icmp_ln48_fu_216_p2; +reg [0:0] icmp_ln48_reg_462; +wire [1:0] select_ln47_6_fu_222_p3; +reg [1:0] select_ln47_6_reg_469; +wire [3:0] select_ln48_12_fu_236_p3; +wire [1:0] select_ln48_11_fu_341_p3; +reg [1:0] select_ln48_11_reg_482; +reg ap_enable_reg_pp0_iter1; +wire [4:0] add_ln55_24_fu_432_p2; +reg [4:0] add_ln55_24_reg_492; +reg [4:0] add_ln55_24_reg_492_pp0_iter2_reg; +reg [4:0] add_ln55_24_reg_492_pp0_iter3_reg; +wire [1:0] add_ln49_fu_438_p2; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg [1:0] ap_phi_mux_ii_phi_fu_132_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_154_p4; +wire [63:0] zext_ln55_57_fu_427_p1; +wire [63:0] zext_ln55_58_fu_444_p1; +wire [5:0] tmp_fu_176_p3; +wire [6:0] zext_ln55_49_fu_184_p1; +wire [6:0] zext_ln55_fu_172_p1; +wire [6:0] sub_ln55_fu_188_p2; +wire [1:0] add_ln47_fu_210_p2; +wire [3:0] add_ln48_6_fu_230_p2; +wire [7:0] zext_ln55_51_fu_254_p1; +wire [7:0] add_ln55_fu_257_p2; +wire [9:0] tmp_46_fu_266_p3; +wire [61:0] sext_ln55_1_fu_274_p1; +wire [61:0] sext_ln55_fu_262_p1; +wire [3:0] tmp_s_fu_284_p3; +wire [4:0] zext_ln55_52_fu_291_p1; +wire [4:0] zext_ln55_50_fu_251_p1; +wire [4:0] sub_ln55_12_fu_295_p2; +wire [0:0] icmp_ln49_fu_310_p2; +wire [0:0] xor_ln47_fu_305_p2; +wire [1:0] select_ln47_fu_244_p3; +wire [0:0] and_ln47_fu_316_p2; +wire [0:0] or_ln48_fu_328_p2; +wire [1:0] add_ln48_fu_322_p2; +wire [61:0] sub_ln55_11_fu_278_p2; +wire [61:0] zext_ln55_54_fu_353_p1; +wire [61:0] add_ln55_21_fu_357_p2; +wire [6:0] trunc_ln55_1_fu_367_p1; +wire [8:0] p_shl2_cast_fu_371_p3; +wire [8:0] trunc_ln55_fu_363_p1; +wire [5:0] sext_ln48_fu_301_p1; +wire [5:0] zext_ln55_53_fu_349_p1; +wire [5:0] add_ln55_22_fu_385_p2; +wire [2:0] trunc_ln55_3_fu_395_p1; +wire [4:0] p_shl1_cast_fu_399_p3; +wire [4:0] trunc_ln55_2_fu_391_p1; +wire [1:0] select_ln48_fu_333_p3; +wire [8:0] sub_ln55_13_fu_379_p2; +wire [8:0] zext_ln55_56_fu_417_p1; +wire [8:0] add_ln55_23_fu_421_p2; +wire [4:0] sub_ln55_14_fu_407_p2; +wire [4:0] zext_ln55_55_fu_413_p1; +wire ap_CS_fsm_state7; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_458 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ii_reg_128 <= select_ln47_6_reg_469; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_128 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_204_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten13_reg_117 <= add_ln47_6_fu_198_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_117 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_204_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_139 <= select_ln48_12_fu_236_p3; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_139 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_458_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + jj_reg_150 <= select_ln48_11_reg_482; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_150 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_458 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_reg_161 <= add_ln49_fu_438_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_161 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_458 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln55_24_reg_492 <= add_ln55_24_fu_432_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln55_24_reg_492_pp0_iter2_reg <= add_ln55_24_reg_492; + add_ln55_24_reg_492_pp0_iter3_reg <= add_ln55_24_reg_492_pp0_iter2_reg; + icmp_ln47_reg_458_pp0_iter2_reg <= icmp_ln47_reg_458_pp0_iter1_reg; + icmp_ln47_reg_458_pp0_iter3_reg <= icmp_ln47_reg_458_pp0_iter2_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln47_reg_458 <= icmp_ln47_fu_204_p2; + icmp_ln47_reg_458_pp0_iter1_reg <= icmp_ln47_reg_458; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_204_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln48_reg_462 <= icmp_ln48_fu_216_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_204_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln47_6_reg_469 <= select_ln47_6_fu_222_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_458 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln48_11_reg_482 <= select_ln48_11_fu_341_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sext_ln47_reg_448 <= sext_ln47_fu_194_p1; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln47_fu_204_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_458 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_132_p4 = select_ln47_6_reg_469; + end else begin + ap_phi_mux_ii_phi_fu_132_p4 = ii_reg_128; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_458_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_154_p4 = select_ln48_11_reg_482; + end else begin + ap_phi_mux_jj_phi_fu_154_p4 = jj_reg_150; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_458_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + weight_vecs_0_we0 = 1'b1; + end else begin + weight_vecs_0_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln47_6_fu_198_p2 = (indvar_flatten13_reg_117 + 5'd1); + +assign add_ln47_fu_210_p2 = (ap_phi_mux_ii_phi_fu_132_p4 + 2'd1); + +assign add_ln48_6_fu_230_p2 = (indvar_flatten_reg_139 + 4'd1); + +assign add_ln48_fu_322_p2 = (select_ln47_fu_244_p3 + 2'd1); + +assign add_ln49_fu_438_p2 = (select_ln48_fu_333_p3 + 2'd1); + +assign add_ln55_21_fu_357_p2 = (sub_ln55_11_fu_278_p2 + zext_ln55_54_fu_353_p1); + +assign add_ln55_22_fu_385_p2 = ((sext_ln48_fu_301_p1) + (zext_ln55_53_fu_349_p1)); + +assign add_ln55_23_fu_421_p2 = (sub_ln55_13_fu_379_p2 + zext_ln55_56_fu_417_p1); + +assign add_ln55_24_fu_432_p2 = (sub_ln55_14_fu_407_p2 + zext_ln55_55_fu_413_p1); + +assign add_ln55_fu_257_p2 = ((sext_ln47_reg_448) + (zext_ln55_51_fu_254_p1)); + +assign and_ln47_fu_316_p2 = (xor_ln47_fu_305_p2 & icmp_ln49_fu_310_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_address0 = zext_ln55_57_fu_427_p1; + +assign icmp_ln47_fu_204_p2 = ((indvar_flatten13_reg_117 == 5'd27) ? 1'b1 : 1'b0); + +assign icmp_ln48_fu_216_p2 = ((indvar_flatten_reg_139 == 4'd9) ? 1'b1 : 1'b0); + +assign icmp_ln49_fu_310_p2 = ((kk_reg_161 == 2'd3) ? 1'b1 : 1'b0); + +assign or_ln48_fu_328_p2 = (icmp_ln48_reg_462 | and_ln47_fu_316_p2); + +assign p_shl1_cast_fu_399_p3 = {{trunc_ln55_3_fu_395_p1}, {2'd0}}; + +assign p_shl2_cast_fu_371_p3 = {{trunc_ln55_1_fu_367_p1}, {2'd0}}; + +assign select_ln47_6_fu_222_p3 = ((icmp_ln48_fu_216_p2[0:0] == 1'b1) ? add_ln47_fu_210_p2 : ap_phi_mux_ii_phi_fu_132_p4); + +assign select_ln47_fu_244_p3 = ((icmp_ln48_reg_462[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_154_p4); + +assign select_ln48_11_fu_341_p3 = ((and_ln47_fu_316_p2[0:0] == 1'b1) ? add_ln48_fu_322_p2 : select_ln47_fu_244_p3); + +assign select_ln48_12_fu_236_p3 = ((icmp_ln48_fu_216_p2[0:0] == 1'b1) ? 4'd1 : add_ln48_6_fu_230_p2); + +assign select_ln48_fu_333_p3 = ((or_ln48_fu_328_p2[0:0] == 1'b1) ? 2'd0 : kk_reg_161); + +assign sext_ln47_fu_194_p1 = (sub_ln55_fu_188_p2); + +assign sext_ln48_fu_301_p1 = (sub_ln55_12_fu_295_p2); + +assign sext_ln55_1_fu_274_p1 = (tmp_46_fu_266_p3); + +assign sext_ln55_fu_262_p1 = add_ln55_fu_257_p2; + +assign sub_ln55_11_fu_278_p2 = ((sext_ln55_1_fu_274_p1) - (sext_ln55_fu_262_p1)); + +assign sub_ln55_12_fu_295_p2 = (zext_ln55_52_fu_291_p1 - zext_ln55_50_fu_251_p1); + +assign sub_ln55_13_fu_379_p2 = (p_shl2_cast_fu_371_p3 - trunc_ln55_fu_363_p1); + +assign sub_ln55_14_fu_407_p2 = (p_shl1_cast_fu_399_p3 - trunc_ln55_2_fu_391_p1); + +assign sub_ln55_fu_188_p2 = (zext_ln55_49_fu_184_p1 - zext_ln55_fu_172_p1); + +assign tmp_46_fu_266_p3 = {{add_ln55_fu_257_p2}, {2'd0}}; + +assign tmp_fu_176_p3 = {{input_indices_23_dout}, {2'd0}}; + +assign tmp_s_fu_284_p3 = {{select_ln47_6_reg_469}, {2'd0}}; + +assign trunc_ln55_1_fu_367_p1 = add_ln55_21_fu_357_p2[6:0]; + +assign trunc_ln55_2_fu_391_p1 = add_ln55_22_fu_385_p2[4:0]; + +assign trunc_ln55_3_fu_395_p1 = add_ln55_22_fu_385_p2[2:0]; + +assign trunc_ln55_fu_363_p1 = add_ln55_21_fu_357_p2[8:0]; + +assign weight_vecs_0_address0 = zext_ln55_58_fu_444_p1; + +assign weight_vecs_0_d0 = filter_data_q0; + +assign xor_ln47_fu_305_p2 = (icmp_ln48_reg_462 ^ 1'd1); + +assign zext_ln55_49_fu_184_p1 = tmp_fu_176_p3; + +assign zext_ln55_50_fu_251_p1 = select_ln47_6_reg_469; + +assign zext_ln55_51_fu_254_p1 = select_ln47_6_reg_469; + +assign zext_ln55_52_fu_291_p1 = tmp_s_fu_284_p3; + +assign zext_ln55_53_fu_349_p1 = select_ln48_11_fu_341_p3; + +assign zext_ln55_54_fu_353_p1 = select_ln48_11_fu_341_p3; + +assign zext_ln55_55_fu_413_p1 = select_ln48_fu_333_p3; + +assign zext_ln55_56_fu_417_p1 = select_ln48_fu_333_p3; + +assign zext_ln55_57_fu_427_p1 = add_ln55_23_fu_421_p2; + +assign zext_ln55_58_fu_444_p1 = add_ln55_24_reg_492_pp0_iter3_reg; + +assign zext_ln55_fu_172_p1 = input_indices_23_dout; + +endmodule //td_fused_top_tdf1_readFilters18 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_readInputs19 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + i_19, + j_19, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_we0, + ifmap_vec_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state7 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] i_19; +input [15:0] j_19; +output [4:0] ifmap_vec_address0; +output ifmap_vec_ce0; +output ifmap_vec_we0; +output [15:0] ifmap_vec_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg ifmap_vec_ce0; +reg ifmap_vec_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [4:0] indvar_flatten52_reg_144; +reg [1:0] ii_reg_155; +reg [3:0] indvar_flatten_reg_167; +reg [1:0] jj_reg_178; +reg [1:0] kk_reg_190; +wire [17:0] p_cast_i_fu_219_p1; +reg [17:0] p_cast_i_reg_910; +wire [17:0] sext_ln22_fu_229_p1; +reg [17:0] sext_ln22_reg_916; +wire [7:0] p_cast_fu_233_p2; +reg [7:0] p_cast_reg_922; +wire [0:0] or_ln23_26_fu_253_p2; +reg [0:0] or_ln23_26_reg_928; +wire [15:0] p_mid140_fu_259_p2; +reg [15:0] p_mid140_reg_933; +wire [4:0] add_ln19_6_fu_265_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_pp0_stage0_11001; +wire [0:0] is_padding_fu_315_p2; +reg [0:0] is_padding_reg_943; +reg [0:0] is_padding_reg_943_pp0_iter1_reg; +reg [0:0] is_padding_reg_943_pp0_iter2_reg; +reg [0:0] is_padding_reg_943_pp0_iter3_reg; +wire [0:0] icmp_ln19_fu_321_p2; +reg [0:0] icmp_ln19_reg_950; +reg [0:0] icmp_ln19_reg_950_pp0_iter1_reg; +reg [0:0] icmp_ln19_reg_950_pp0_iter2_reg; +reg [0:0] icmp_ln19_reg_950_pp0_iter3_reg; +wire [1:0] add_ln19_fu_327_p2; +reg [1:0] add_ln19_reg_954; +wire [0:0] icmp_ln20_fu_333_p2; +reg [0:0] icmp_ln20_reg_959; +reg [0:0] icmp_ln20_reg_959_pp0_iter1_reg; +reg [0:0] icmp_ln20_reg_959_pp0_iter2_reg; +reg [0:0] icmp_ln20_reg_959_pp0_iter3_reg; +wire [1:0] select_ln19_31_fu_347_p3; +reg [1:0] select_ln19_31_reg_966; +reg [1:0] select_ln19_31_reg_966_pp0_iter1_reg; +reg [1:0] select_ln19_31_reg_966_pp0_iter2_reg; +reg [1:0] select_ln19_31_reg_966_pp0_iter3_reg; +wire [0:0] or_ln23_28_fu_378_p2; +reg [0:0] or_ln23_28_reg_973; +reg [0:0] or_ln23_28_reg_973_pp0_iter1_reg; +reg [0:0] or_ln23_28_reg_973_pp0_iter2_reg; +reg [0:0] or_ln23_28_reg_973_pp0_iter3_reg; +wire [0:0] and_ln19_fu_395_p2; +reg [0:0] and_ln19_reg_980; +reg [0:0] and_ln19_reg_980_pp0_iter1_reg; +reg [0:0] and_ln19_reg_980_pp0_iter2_reg; +reg [0:0] and_ln19_reg_980_pp0_iter3_reg; +wire [1:0] add_ln20_fu_401_p2; +reg [1:0] add_ln20_reg_986; +wire [1:0] select_ln20_fu_413_p3; +reg [1:0] select_ln20_reg_991; +reg [1:0] select_ln20_reg_991_pp0_iter1_reg; +reg [1:0] select_ln20_reg_991_pp0_iter2_reg; +reg [1:0] select_ln20_reg_991_pp0_iter3_reg; +wire [1:0] select_ln20_26_fu_421_p3; +reg [1:0] select_ln20_26_reg_997; +reg [1:0] select_ln20_26_reg_997_pp0_iter1_reg; +reg [1:0] select_ln20_26_reg_997_pp0_iter2_reg; +reg [1:0] select_ln20_26_reg_997_pp0_iter3_reg; +wire [0:0] or_ln23_30_fu_458_p2; +reg [0:0] or_ln23_30_reg_1003; +reg [0:0] or_ln23_30_reg_1003_pp0_iter1_reg; +reg [0:0] or_ln23_30_reg_1003_pp0_iter2_reg; +reg [0:0] or_ln23_30_reg_1003_pp0_iter3_reg; +wire [1:0] add_ln25_fu_464_p2; +wire [3:0] select_ln20_29_fu_476_p3; +wire [5:0] tmp_15_fu_701_p3; +reg [5:0] tmp_15_reg_1025; +wire [5:0] empty_121_fu_708_p2; +reg [5:0] empty_121_reg_1030; +wire [0:0] icmp_ln32_fu_714_p2; +reg [0:0] icmp_ln32_reg_1035; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg [1:0] ap_phi_mux_ii_phi_fu_159_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_182_p4; +wire [63:0] zext_ln32_26_fu_696_p1; +wire [63:0] zext_ln33_25_fu_795_p1; +wire [16:0] zext_ln19_fu_205_p1; +wire [16:0] empty_116_fu_213_p2; +wire [16:0] j_cast_i_fu_201_p1; +wire [16:0] add_ln22_fu_223_p2; +wire [7:0] empty_fu_209_p1; +wire [0:0] tmp_fu_239_p3; +wire [0:0] icmp_ln24_fu_247_p2; +wire [17:0] ii_cast_i_fu_271_p1; +wire [17:0] empty_117_fu_275_p2; +wire [17:0] zext_ln20_fu_286_p1; +wire [17:0] add_ln22_6_fu_290_p2; +wire [0:0] tmp_43_fu_295_p3; +wire [0:0] icmp_ln24_6_fu_303_p2; +wire [0:0] or_ln23_fu_309_p2; +wire [0:0] empty_118_fu_280_p2; +wire [17:0] ii_cast_i_mid1_fu_355_p1; +wire [17:0] p_mid114_fu_359_p2; +wire [0:0] p_mid116_fu_364_p2; +wire [0:0] icmp_ln25_fu_389_p2; +wire [0:0] xor_ln19_fu_383_p2; +wire [1:0] select_ln19_fu_339_p3; +wire [0:0] or_ln20_fu_407_p2; +wire [17:0] zext_ln20_6_fu_429_p1; +wire [17:0] add_ln22_7_fu_433_p2; +wire [0:0] tmp_44_fu_438_p3; +wire [0:0] icmp_ln24_7_fu_446_p2; +wire [0:0] or_ln23_29_fu_452_p2; +wire [0:0] select_ln19_33_fu_370_p3; +wire [3:0] add_ln20_6_fu_470_p2; +wire [7:0] ii_cast_fu_484_p1; +wire [7:0] p_cast1_i_fu_488_p2; +wire [2:0] zext_ln22_fu_493_p1; +wire [2:0] tmp2_fu_504_p2; +wire [15:0] tmp2_cast_fu_510_p1; +wire [15:0] empty_119_fu_514_p2; +wire [7:0] row_coord_int_fu_497_p3; +wire [12:0] tmp_9_fu_534_p3; +wire [15:0] tmp_s_fu_526_p3; +wire [15:0] zext_ln32_fu_542_p1; +wire [15:0] sub_ln32_fu_546_p2; +wire [15:0] col_coord_int_fu_519_p3; +wire [7:0] ii_cast_mid1_fu_558_p1; +wire [7:0] p_cast1_i_mid1_fu_561_p2; +wire [7:0] row_coord_int_mid134_fu_573_p3; +wire [12:0] tmp_12_fu_594_p3; +wire [15:0] tmp_11_fu_586_p3; +wire [15:0] zext_ln32_24_fu_602_p1; +wire [15:0] sub_ln32_1_fu_606_p2; +wire [15:0] col_coord_int_mid142_fu_580_p3; +wire [15:0] add_ln32_1_fu_612_p2; +wire [15:0] add_ln32_fu_552_p2; +wire [7:0] select_ln19_32_fu_566_p3; +wire [2:0] zext_ln22_6_fu_625_p1; +wire [2:0] tmp2_mid1_fu_635_p2; +wire [15:0] tmp2_cast_mid1_fu_641_p1; +wire [15:0] p_mid1_fu_645_p2; +wire [7:0] row_coord_int_mid1_fu_628_p3; +wire [12:0] tmp_14_fu_665_p3; +wire [15:0] tmp_13_fu_657_p3; +wire [15:0] zext_ln32_25_fu_673_p1; +wire [15:0] sub_ln32_2_fu_677_p2; +wire [15:0] col_coord_int_mid1_fu_650_p3; +wire [15:0] add_ln32_2_fu_683_p2; +wire [15:0] select_ln19_35_fu_618_p3; +wire [15:0] select_ln20_28_fu_689_p3; +wire [3:0] tmp_10_fu_723_p3; +wire [4:0] zext_ln33_22_fu_730_p1; +wire [4:0] zext_ln33_fu_720_p1; +wire [4:0] sub_ln33_fu_734_p2; +wire [5:0] sub_ln33_cast_fu_740_p1; +wire [5:0] zext_ln33_23_fu_749_p1; +wire [5:0] add_ln33_fu_752_p2; +wire [2:0] trunc_ln33_1_fu_762_p1; +wire [4:0] p_shl4_cast_fu_766_p3; +wire [4:0] trunc_ln33_fu_758_p1; +wire [0:0] select_ln19_34_fu_744_p3; +wire [4:0] sub_ln33_1_fu_774_p2; +wire [4:0] zext_ln33_24_fu_786_p1; +wire [4:0] add_ln33_6_fu_789_p2; +wire [6:0] zext_ln32_27_fu_800_p1; +wire [6:0] zext_ln32_28_fu_803_p1; +wire [6:0] sub_ln32_3_fu_816_p2; +wire [6:0] sub_ln32_4_fu_828_p2; +reg [63:0] tmp_45_fu_806_p4; +wire [6:0] xor_ln32_fu_822_p2; +wire [6:0] select_ln32_fu_834_p3; +wire [6:0] select_ln32_2_fu_848_p3; +wire [6:0] sub_ln32_5_fu_855_p2; +wire [63:0] select_ln32_1_fu_841_p3; +wire [63:0] zext_ln32_29_fu_861_p1; +wire [63:0] zext_ln32_30_fu_865_p1; +wire [63:0] lshr_ln32_fu_869_p2; +wire [63:0] lshr_ln32_1_fu_875_p2; +wire [63:0] and_ln32_fu_881_p2; +wire [15:0] trunc_ln32_fu_887_p1; +wire [0:0] select_ln20_27_fu_780_p3; +wire [15:0] in_data_elem_fu_891_p1; +wire ap_CS_fsm_state7; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_950 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ii_reg_155 <= select_ln19_31_reg_966; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_155 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_321_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten52_reg_144 <= add_ln19_6_fu_265_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten52_reg_144 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_321_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_167 <= select_ln20_29_fu_476_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_167 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_950 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_178 <= select_ln20_26_reg_997; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_178 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_321_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_reg_190 <= add_ln25_fu_464_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_190 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_321_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln19_reg_954 <= add_ln19_fu_327_p2; + add_ln20_reg_986 <= add_ln20_fu_401_p2; + and_ln19_reg_980 <= and_ln19_fu_395_p2; + icmp_ln20_reg_959 <= icmp_ln20_fu_333_p2; + or_ln23_28_reg_973 <= or_ln23_28_fu_378_p2; + or_ln23_30_reg_1003 <= or_ln23_30_fu_458_p2; + select_ln20_reg_991 <= select_ln20_fu_413_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + and_ln19_reg_980_pp0_iter1_reg <= and_ln19_reg_980; + icmp_ln19_reg_950 <= icmp_ln19_fu_321_p2; + icmp_ln19_reg_950_pp0_iter1_reg <= icmp_ln19_reg_950; + icmp_ln20_reg_959_pp0_iter1_reg <= icmp_ln20_reg_959; + is_padding_reg_943 <= is_padding_fu_315_p2; + is_padding_reg_943_pp0_iter1_reg <= is_padding_reg_943; + or_ln23_28_reg_973_pp0_iter1_reg <= or_ln23_28_reg_973; + or_ln23_30_reg_1003_pp0_iter1_reg <= or_ln23_30_reg_1003; + select_ln19_31_reg_966_pp0_iter1_reg <= select_ln19_31_reg_966; + select_ln20_26_reg_997_pp0_iter1_reg <= select_ln20_26_reg_997; + select_ln20_reg_991_pp0_iter1_reg <= select_ln20_reg_991; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + and_ln19_reg_980_pp0_iter2_reg <= and_ln19_reg_980_pp0_iter1_reg; + and_ln19_reg_980_pp0_iter3_reg <= and_ln19_reg_980_pp0_iter2_reg; + icmp_ln19_reg_950_pp0_iter2_reg <= icmp_ln19_reg_950_pp0_iter1_reg; + icmp_ln19_reg_950_pp0_iter3_reg <= icmp_ln19_reg_950_pp0_iter2_reg; + icmp_ln20_reg_959_pp0_iter2_reg <= icmp_ln20_reg_959_pp0_iter1_reg; + icmp_ln20_reg_959_pp0_iter3_reg <= icmp_ln20_reg_959_pp0_iter2_reg; + is_padding_reg_943_pp0_iter2_reg <= is_padding_reg_943_pp0_iter1_reg; + is_padding_reg_943_pp0_iter3_reg <= is_padding_reg_943_pp0_iter2_reg; + or_ln23_28_reg_973_pp0_iter2_reg <= or_ln23_28_reg_973_pp0_iter1_reg; + or_ln23_28_reg_973_pp0_iter3_reg <= or_ln23_28_reg_973_pp0_iter2_reg; + or_ln23_30_reg_1003_pp0_iter2_reg <= or_ln23_30_reg_1003_pp0_iter1_reg; + or_ln23_30_reg_1003_pp0_iter3_reg <= or_ln23_30_reg_1003_pp0_iter2_reg; + select_ln19_31_reg_966_pp0_iter2_reg <= select_ln19_31_reg_966_pp0_iter1_reg; + select_ln19_31_reg_966_pp0_iter3_reg <= select_ln19_31_reg_966_pp0_iter2_reg; + select_ln20_26_reg_997_pp0_iter2_reg <= select_ln20_26_reg_997_pp0_iter1_reg; + select_ln20_26_reg_997_pp0_iter3_reg <= select_ln20_26_reg_997_pp0_iter2_reg; + select_ln20_reg_991_pp0_iter2_reg <= select_ln20_reg_991_pp0_iter1_reg; + select_ln20_reg_991_pp0_iter3_reg <= select_ln20_reg_991_pp0_iter2_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_950_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + empty_121_reg_1030[5 : 4] <= empty_121_fu_708_p2[5 : 4]; + icmp_ln32_reg_1035 <= icmp_ln32_fu_714_p2; + tmp_15_reg_1025[5 : 4] <= tmp_15_fu_701_p3[5 : 4]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + or_ln23_26_reg_928 <= or_ln23_26_fu_253_p2; + p_cast_i_reg_910 <= p_cast_i_fu_219_p1; + p_cast_reg_922 <= p_cast_fu_233_p2; + p_mid140_reg_933 <= p_mid140_fu_259_p2; + sext_ln22_reg_916 <= sext_ln22_fu_229_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_321_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln19_31_reg_966 <= select_ln19_31_fu_347_p3; + select_ln20_26_reg_997 <= select_ln20_26_fu_421_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_fu_321_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_950 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_159_p4 = select_ln19_31_reg_966; + end else begin + ap_phi_mux_ii_phi_fu_159_p4 = ii_reg_155; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_950 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_182_p4 = select_ln20_26_reg_997; + end else begin + ap_phi_mux_jj_phi_fu_182_p4 = jj_reg_178; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_950_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + ifmap_vec_we0 = 1'b1; + end else begin + ifmap_vec_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1)))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln19_6_fu_265_p2 = (indvar_flatten52_reg_144 + 5'd1); + +assign add_ln19_fu_327_p2 = (ap_phi_mux_ii_phi_fu_159_p4 + 2'd1); + +assign add_ln20_6_fu_470_p2 = (indvar_flatten_reg_167 + 4'd1); + +assign add_ln20_fu_401_p2 = (select_ln19_fu_339_p3 + 2'd1); + +assign add_ln22_6_fu_290_p2 = ((sext_ln22_reg_916) + (zext_ln20_fu_286_p1)); + +assign add_ln22_7_fu_433_p2 = ((sext_ln22_reg_916) + (zext_ln20_6_fu_429_p1)); + +assign add_ln22_fu_223_p2 = ((j_cast_i_fu_201_p1) + (17'd131071)); + +assign add_ln25_fu_464_p2 = (select_ln20_fu_413_p3 + 2'd1); + +assign add_ln32_1_fu_612_p2 = (sub_ln32_1_fu_606_p2 + col_coord_int_mid142_fu_580_p3); + +assign add_ln32_2_fu_683_p2 = (sub_ln32_2_fu_677_p2 + col_coord_int_mid1_fu_650_p3); + +assign add_ln32_fu_552_p2 = (sub_ln32_fu_546_p2 + col_coord_int_fu_519_p3); + +assign add_ln33_6_fu_789_p2 = (sub_ln33_1_fu_774_p2 + zext_ln33_24_fu_786_p1); + +assign add_ln33_fu_752_p2 = ((sub_ln33_cast_fu_740_p1) + (zext_ln33_23_fu_749_p1)); + +assign and_ln19_fu_395_p2 = (xor_ln19_fu_383_p2 & icmp_ln25_fu_389_p2); + +assign and_ln32_fu_881_p2 = (lshr_ln32_fu_869_p2 & lshr_ln32_1_fu_875_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign col_coord_int_fu_519_p3 = ((is_padding_reg_943[0:0] == 1'b1) ? 16'd0 : empty_119_fu_514_p2); + +assign col_coord_int_mid142_fu_580_p3 = ((or_ln23_28_reg_973[0:0] == 1'b1) ? 16'd0 : p_mid140_reg_933); + +assign col_coord_int_mid1_fu_650_p3 = ((or_ln23_30_reg_1003[0:0] == 1'b1) ? 16'd0 : p_mid1_fu_645_p2); + +assign empty_116_fu_213_p2 = ((zext_ln19_fu_205_p1) + (17'd131071)); + +assign empty_117_fu_275_p2 = ((p_cast_i_reg_910) + (ii_cast_i_fu_271_p1)); + +assign empty_118_fu_280_p2 = ((empty_117_fu_275_p2 > 18'd223) ? 1'b1 : 1'b0); + +assign empty_119_fu_514_p2 = ((tmp2_cast_fu_510_p1) + (j_19)); + +assign empty_121_fu_708_p2 = (tmp_15_fu_701_p3 | 6'd15); + +assign empty_fu_209_p1 = i_19[7:0]; + +assign icmp_ln19_fu_321_p2 = ((indvar_flatten52_reg_144 == 5'd27) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_333_p2 = ((indvar_flatten_reg_167 == 4'd9) ? 1'b1 : 1'b0); + +assign icmp_ln24_6_fu_303_p2 = (((add_ln22_6_fu_290_p2) > (18'd223)) ? 1'b1 : 1'b0); + +assign icmp_ln24_7_fu_446_p2 = (((add_ln22_7_fu_433_p2) > (18'd223)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_247_p2 = (((add_ln22_fu_223_p2) > (17'd223)) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_389_p2 = ((kk_reg_190 == 2'd3) ? 1'b1 : 1'b0); + +assign icmp_ln32_fu_714_p2 = ((tmp_15_fu_701_p3 > empty_121_fu_708_p2) ? 1'b1 : 1'b0); + +assign ifmap_vec_address0 = zext_ln33_25_fu_795_p1; + +assign ifmap_vec_d0 = ((select_ln20_27_fu_780_p3[0:0] == 1'b1) ? 16'd0 : in_data_elem_fu_891_p1); + +assign ii_cast_fu_484_p1 = ii_reg_155; + +assign ii_cast_i_fu_271_p1 = ap_phi_mux_ii_phi_fu_159_p4; + +assign ii_cast_i_mid1_fu_355_p1 = add_ln19_fu_327_p2; + +assign ii_cast_mid1_fu_558_p1 = add_ln19_reg_954; + +assign in_data_address0 = zext_ln32_26_fu_696_p1; + +assign in_data_elem_fu_891_p1 = trunc_ln32_fu_887_p1; + +assign is_padding_fu_315_p2 = (or_ln23_fu_309_p2 | empty_118_fu_280_p2); + +assign j_cast_i_fu_201_p1 = j_19; + +assign lshr_ln32_1_fu_875_p2 = 64'd18446744073709551615 >> zext_ln32_30_fu_865_p1; + +assign lshr_ln32_fu_869_p2 = select_ln32_1_fu_841_p3 >> zext_ln32_29_fu_861_p1; + +assign or_ln20_fu_407_p2 = (icmp_ln20_fu_333_p2 | and_ln19_fu_395_p2); + +assign or_ln23_26_fu_253_p2 = (tmp_fu_239_p3 | icmp_ln24_fu_247_p2); + +assign or_ln23_28_fu_378_p2 = (p_mid116_fu_364_p2 | or_ln23_26_reg_928); + +assign or_ln23_29_fu_452_p2 = (tmp_44_fu_438_p3 | icmp_ln24_7_fu_446_p2); + +assign or_ln23_30_fu_458_p2 = (select_ln19_33_fu_370_p3 | or_ln23_29_fu_452_p2); + +assign or_ln23_fu_309_p2 = (tmp_43_fu_295_p3 | icmp_ln24_6_fu_303_p2); + +assign p_cast1_i_fu_488_p2 = (p_cast_reg_922 + ii_cast_fu_484_p1); + +assign p_cast1_i_mid1_fu_561_p2 = (p_cast_reg_922 + ii_cast_mid1_fu_558_p1); + +assign p_cast_fu_233_p2 = ((empty_fu_209_p1) + (8'd255)); + +assign p_cast_i_fu_219_p1 = (empty_116_fu_213_p2); + +assign p_mid114_fu_359_p2 = ((p_cast_i_reg_910) + (ii_cast_i_mid1_fu_355_p1)); + +assign p_mid116_fu_364_p2 = ((p_mid114_fu_359_p2 > 18'd223) ? 1'b1 : 1'b0); + +assign p_mid140_fu_259_p2 = ((j_19) + (16'd65535)); + +assign p_mid1_fu_645_p2 = ((tmp2_cast_mid1_fu_641_p1) + (j_19)); + +assign p_shl4_cast_fu_766_p3 = {{trunc_ln33_1_fu_762_p1}, {2'd0}}; + +assign row_coord_int_fu_497_p3 = ((is_padding_reg_943[0:0] == 1'b1) ? 8'd0 : p_cast1_i_fu_488_p2); + +assign row_coord_int_mid134_fu_573_p3 = ((or_ln23_28_reg_973[0:0] == 1'b1) ? 8'd0 : p_cast1_i_mid1_fu_561_p2); + +assign row_coord_int_mid1_fu_628_p3 = ((or_ln23_30_reg_1003[0:0] == 1'b1) ? 8'd0 : select_ln19_32_fu_566_p3); + +assign select_ln19_31_fu_347_p3 = ((icmp_ln20_fu_333_p2[0:0] == 1'b1) ? add_ln19_fu_327_p2 : ap_phi_mux_ii_phi_fu_159_p4); + +assign select_ln19_32_fu_566_p3 = ((icmp_ln20_reg_959[0:0] == 1'b1) ? p_cast1_i_mid1_fu_561_p2 : p_cast1_i_fu_488_p2); + +assign select_ln19_33_fu_370_p3 = ((icmp_ln20_fu_333_p2[0:0] == 1'b1) ? p_mid116_fu_364_p2 : empty_118_fu_280_p2); + +assign select_ln19_34_fu_744_p3 = ((icmp_ln20_reg_959_pp0_iter3_reg[0:0] == 1'b1) ? or_ln23_28_reg_973_pp0_iter3_reg : is_padding_reg_943_pp0_iter3_reg); + +assign select_ln19_35_fu_618_p3 = ((icmp_ln20_reg_959[0:0] == 1'b1) ? add_ln32_1_fu_612_p2 : add_ln32_fu_552_p2); + +assign select_ln19_fu_339_p3 = ((icmp_ln20_fu_333_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_182_p4); + +assign select_ln20_26_fu_421_p3 = ((and_ln19_fu_395_p2[0:0] == 1'b1) ? add_ln20_fu_401_p2 : select_ln19_fu_339_p3); + +assign select_ln20_27_fu_780_p3 = ((and_ln19_reg_980_pp0_iter3_reg[0:0] == 1'b1) ? or_ln23_30_reg_1003_pp0_iter3_reg : select_ln19_34_fu_744_p3); + +assign select_ln20_28_fu_689_p3 = ((and_ln19_reg_980[0:0] == 1'b1) ? add_ln32_2_fu_683_p2 : select_ln19_35_fu_618_p3); + +assign select_ln20_29_fu_476_p3 = ((icmp_ln20_fu_333_p2[0:0] == 1'b1) ? 4'd1 : add_ln20_6_fu_470_p2); + +assign select_ln20_fu_413_p3 = ((or_ln20_fu_407_p2[0:0] == 1'b1) ? 2'd0 : kk_reg_190); + +assign select_ln32_1_fu_841_p3 = ((icmp_ln32_reg_1035[0:0] == 1'b1) ? tmp_45_fu_806_p4 : in_data_q0); + +assign select_ln32_2_fu_848_p3 = ((icmp_ln32_reg_1035[0:0] == 1'b1) ? xor_ln32_fu_822_p2 : zext_ln32_27_fu_800_p1); + +assign select_ln32_fu_834_p3 = ((icmp_ln32_reg_1035[0:0] == 1'b1) ? sub_ln32_3_fu_816_p2 : sub_ln32_4_fu_828_p2); + +assign sext_ln22_fu_229_p1 = add_ln22_fu_223_p2; + +assign sub_ln32_1_fu_606_p2 = (tmp_11_fu_586_p3 - zext_ln32_24_fu_602_p1); + +assign sub_ln32_2_fu_677_p2 = (tmp_13_fu_657_p3 - zext_ln32_25_fu_673_p1); + +assign sub_ln32_3_fu_816_p2 = (zext_ln32_27_fu_800_p1 - zext_ln32_28_fu_803_p1); + +assign sub_ln32_4_fu_828_p2 = (zext_ln32_28_fu_803_p1 - zext_ln32_27_fu_800_p1); + +assign sub_ln32_5_fu_855_p2 = (7'd63 - select_ln32_fu_834_p3); + +assign sub_ln32_fu_546_p2 = (tmp_s_fu_526_p3 - zext_ln32_fu_542_p1); + +assign sub_ln33_1_fu_774_p2 = (p_shl4_cast_fu_766_p3 - trunc_ln33_fu_758_p1); + +assign sub_ln33_cast_fu_740_p1 = (sub_ln33_fu_734_p2); + +assign sub_ln33_fu_734_p2 = (zext_ln33_22_fu_730_p1 - zext_ln33_fu_720_p1); + +assign tmp2_cast_fu_510_p1 = (tmp2_fu_504_p2); + +assign tmp2_cast_mid1_fu_641_p1 = (tmp2_mid1_fu_635_p2); + +assign tmp2_fu_504_p2 = ((zext_ln22_fu_493_p1) + (3'd7)); + +assign tmp2_mid1_fu_635_p2 = ((zext_ln22_6_fu_625_p1) + (3'd7)); + +assign tmp_10_fu_723_p3 = {{select_ln19_31_reg_966_pp0_iter3_reg}, {2'd0}}; + +assign tmp_11_fu_586_p3 = {{row_coord_int_mid134_fu_573_p3}, {8'd0}}; + +assign tmp_12_fu_594_p3 = {{row_coord_int_mid134_fu_573_p3}, {5'd0}}; + +assign tmp_13_fu_657_p3 = {{row_coord_int_mid1_fu_628_p3}, {8'd0}}; + +assign tmp_14_fu_665_p3 = {{row_coord_int_mid1_fu_628_p3}, {5'd0}}; + +assign tmp_15_fu_701_p3 = {{select_ln20_reg_991_pp0_iter2_reg}, {4'd0}}; + +assign tmp_43_fu_295_p3 = add_ln22_6_fu_290_p2[32'd17]; + +assign tmp_44_fu_438_p3 = add_ln22_7_fu_433_p2[32'd17]; + +integer ap_tvar_int_0; + +always @ (in_data_q0) begin + //for (ap_tvar_int_0 = 64 - 1; ap_tvar_int_0 >= 0; ap_tvar_int_0 = ap_tvar_int_0 - 1) begin + for (ap_tvar_int_0 = 0; ap_tvar_int_0 < 64; ap_tvar_int_0 = ap_tvar_int_0 + 1) begin + if (ap_tvar_int_0 > 63 - 0) begin + tmp_45_fu_806_p4[ap_tvar_int_0] = 1'b0; + end else begin + tmp_45_fu_806_p4[ap_tvar_int_0] = in_data_q0[63 - ap_tvar_int_0]; + end + end +end + +assign tmp_9_fu_534_p3 = {{row_coord_int_fu_497_p3}, {5'd0}}; + +assign tmp_fu_239_p3 = add_ln22_fu_223_p2[32'd16]; + +assign tmp_s_fu_526_p3 = {{row_coord_int_fu_497_p3}, {8'd0}}; + +assign trunc_ln32_fu_887_p1 = and_ln32_fu_881_p2[15:0]; + +assign trunc_ln33_1_fu_762_p1 = add_ln33_fu_752_p2[2:0]; + +assign trunc_ln33_fu_758_p1 = add_ln33_fu_752_p2[4:0]; + +assign xor_ln19_fu_383_p2 = (icmp_ln20_fu_333_p2 ^ 1'd1); + +assign xor_ln32_fu_822_p2 = (zext_ln32_27_fu_800_p1 ^ 7'd63); + +assign zext_ln19_fu_205_p1 = i_19; + +assign zext_ln20_6_fu_429_p1 = add_ln20_fu_401_p2; + +assign zext_ln20_fu_286_p1 = ap_phi_mux_jj_phi_fu_182_p4; + +assign zext_ln22_6_fu_625_p1 = add_ln20_reg_986; + +assign zext_ln22_fu_493_p1 = jj_reg_178; + +assign zext_ln32_24_fu_602_p1 = tmp_12_fu_594_p3; + +assign zext_ln32_25_fu_673_p1 = tmp_14_fu_665_p3; + +assign zext_ln32_26_fu_696_p1 = select_ln20_28_fu_689_p3; + +assign zext_ln32_27_fu_800_p1 = tmp_15_reg_1025; + +assign zext_ln32_28_fu_803_p1 = empty_121_reg_1030; + +assign zext_ln32_29_fu_861_p1 = select_ln32_2_fu_848_p3; + +assign zext_ln32_30_fu_865_p1 = sub_ln32_5_fu_855_p2; + +assign zext_ln32_fu_542_p1 = tmp_9_fu_534_p3; + +assign zext_ln33_22_fu_730_p1 = tmp_10_fu_723_p3; + +assign zext_ln33_23_fu_749_p1 = select_ln20_26_reg_997_pp0_iter3_reg; + +assign zext_ln33_24_fu_786_p1 = select_ln20_reg_991_pp0_iter3_reg; + +assign zext_ln33_25_fu_795_p1 = add_ln33_6_fu_789_p2; + +assign zext_ln33_fu_720_p1 = select_ln19_31_reg_966_pp0_iter3_reg; + +always @ (posedge ap_clk) begin + tmp_15_reg_1025[3:0] <= 4'b0000; + empty_121_reg_1030[3:0] <= 4'b1111; +end + +endmodule //td_fused_top_tdf1_readInputs19 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf1_writeOutputs_unaligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_idle, + ap_ready, + i, + j, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1, + max_vals_3_0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_state2 = 3'd2; +parameter ap_ST_fsm_state3 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +input [6:0] i; +input [13:0] j; +output [15:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; +input [15:0] max_vals_3_0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg out_data_ce1; +reg out_data_we1; + + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] outputCount_1; +reg [15:0] outputChanIdx_1; +reg [15:0] outputRow_8_0; +reg [15:0] outputRow_8_1; +reg [15:0] outputRow_8_2; +reg [15:0] outputRow_8_3; +wire [14:0] sub_ln94_fu_121_p2; +reg [14:0] sub_ln94_reg_294; +wire [15:0] add_ln87_fu_182_p2; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln88_fu_188_p2; +reg [0:0] icmp_ln88_reg_307; +reg [15:0] ap_phi_mux_empty_phi_fu_90_p4; +reg [15:0] empty_reg_87; +wire ap_CS_fsm_state3; +wire [63:0] zext_ln94_18_fu_216_p1; +wire [15:0] select_ln97_fu_274_p3; +wire [1:0] trunc_ln86_fu_154_p1; +reg [15:0] ap_sig_allocacmp_outputRow_8_0_load; +reg [15:0] ap_sig_allocacmp_outputRow_8_1_load; +reg [15:0] ap_sig_allocacmp_outputRow_8_2_load; +reg [15:0] ap_sig_allocacmp_outputRow_8_3_load; +wire [13:0] tmp_fu_97_p3; +wire [10:0] tmp_s_fu_109_p3; +wire [14:0] zext_ln94_fu_105_p1; +wire [14:0] zext_ln94_15_fu_117_p1; +wire [15:0] sub_ln94_cast14_fu_127_p1; +wire [15:0] zext_ln94_16_fu_130_p1; +wire [15:0] add_ln94_fu_134_p2; +wire [3:0] trunc_ln94_fu_202_p1; +wire [15:0] shl_ln89_fu_140_p2; +wire [15:0] zext_ln94_17_fu_206_p1; +wire [15:0] add_ln94_7_fu_210_p2; +wire [15:0] bitcast_ln94_21_fu_245_p1; +wire [15:0] bitcast_ln94_20_fu_237_p1; +wire [15:0] bitcast_ln94_19_fu_229_p1; +wire [15:0] bitcast_ln94_fu_221_p1; +wire [15:0] add_ln96_fu_262_p2; +wire [0:0] icmp_ln97_fu_268_p2; +reg [2:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 3'd1; +#0 outputCount_1 = 16'd0; +#0 outputChanIdx_1 = 16'd0; +#0 outputRow_8_0 = 16'd0; +#0 outputRow_8_1 = 16'd0; +#0 outputRow_8_2 = 16'd0; +#0 outputRow_8_3 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_reg_307 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + empty_reg_87 <= 16'd0; + end else if (((icmp_ln88_fu_188_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + empty_reg_87 <= add_ln87_fu_182_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + icmp_ln88_reg_307 <= icmp_ln88_fu_188_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_fu_188_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + outputChanIdx_1 <= select_ln97_fu_274_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + outputCount_1 <= ap_phi_mux_empty_phi_fu_90_p4; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_154_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_8_0 <= max_vals_3_0; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_154_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_8_1 <= max_vals_3_0; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_154_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_8_2 <= max_vals_3_0; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_154_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_8_3 <= max_vals_3_0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sub_ln94_reg_294[14 : 4] <= sub_ln94_fu_121_p2[14 : 4]; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) | ((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_reg_307 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + ap_phi_mux_empty_phi_fu_90_p4 = 16'd0; + end else begin + ap_phi_mux_empty_phi_fu_90_p4 = empty_reg_87; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_154_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_8_0_load = max_vals_3_0; + end else begin + ap_sig_allocacmp_outputRow_8_0_load = outputRow_8_0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_154_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_8_1_load = max_vals_3_0; + end else begin + ap_sig_allocacmp_outputRow_8_1_load = outputRow_8_1; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_154_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_8_2_load = max_vals_3_0; + end else begin + ap_sig_allocacmp_outputRow_8_2_load = outputRow_8_2; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_154_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_8_3_load = max_vals_3_0; + end else begin + ap_sig_allocacmp_outputRow_8_3_load = outputRow_8_3; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2))) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_fu_188_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln87_fu_182_p2 = (outputCount_1 + 16'd1); + +assign add_ln94_7_fu_210_p2 = (shl_ln89_fu_140_p2 + zext_ln94_17_fu_206_p1); + +assign add_ln94_fu_134_p2 = (sub_ln94_cast14_fu_127_p1 + zext_ln94_16_fu_130_p1); + +assign add_ln96_fu_262_p2 = (outputChanIdx_1 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign bitcast_ln94_19_fu_229_p1 = ap_sig_allocacmp_outputRow_8_1_load; + +assign bitcast_ln94_20_fu_237_p1 = ap_sig_allocacmp_outputRow_8_2_load; + +assign bitcast_ln94_21_fu_245_p1 = ap_sig_allocacmp_outputRow_8_3_load; + +assign bitcast_ln94_fu_221_p1 = ap_sig_allocacmp_outputRow_8_0_load; + +assign icmp_ln88_fu_188_p2 = ((add_ln87_fu_182_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign icmp_ln97_fu_268_p2 = ((add_ln96_fu_262_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign out_data_address1 = zext_ln94_18_fu_216_p1; + +assign out_data_d1 = {{{{bitcast_ln94_21_fu_245_p1}, {bitcast_ln94_20_fu_237_p1}}, {bitcast_ln94_19_fu_229_p1}}, {bitcast_ln94_fu_221_p1}}; + +assign select_ln97_fu_274_p3 = ((icmp_ln97_fu_268_p2[0:0] == 1'b1) ? 16'd0 : add_ln96_fu_262_p2); + +assign shl_ln89_fu_140_p2 = add_ln94_fu_134_p2 << 16'd2; + +assign sub_ln94_cast14_fu_127_p1 = sub_ln94_reg_294; + +assign sub_ln94_fu_121_p2 = (zext_ln94_fu_105_p1 - zext_ln94_15_fu_117_p1); + +assign tmp_fu_97_p3 = {{i}, {7'd0}}; + +assign tmp_s_fu_109_p3 = {{i}, {4'd0}}; + +assign trunc_ln86_fu_154_p1 = outputCount_1[1:0]; + +assign trunc_ln94_fu_202_p1 = outputChanIdx_1[3:0]; + +assign zext_ln94_15_fu_117_p1 = tmp_s_fu_109_p3; + +assign zext_ln94_16_fu_130_p1 = j; + +assign zext_ln94_17_fu_206_p1 = trunc_ln94_fu_202_p1; + +assign zext_ln94_18_fu_216_p1 = add_ln94_7_fu_210_p2; + +assign zext_ln94_fu_105_p1 = tmp_fu_97_p3; + +always @ (posedge ap_clk) begin + sub_ln94_reg_294[3:0] <= 4'b0000; +end + +endmodule //td_fused_top_tdf1_writeOutputs_unaligned +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_113 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [15:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [15:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [14:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [14:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [12:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [12:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [4:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [4:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [15:0] dataflow_in_loop_TOP_LOOP38022_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP38022_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP38022_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP38022_U0_in_data_we0; +wire [15:0] dataflow_in_loop_TOP_LOOP38022_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP38022_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP38022_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP38022_U0_in_data_we1; +wire [12:0] dataflow_in_loop_TOP_LOOP38022_U0_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP38022_U0_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP38022_U0_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP38022_U0_filter_data_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP38022_U0_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP38022_U0_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP38022_U0_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP38022_U0_filter_data_we1; +wire [4:0] dataflow_in_loop_TOP_LOOP38022_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP38022_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP38022_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP38022_U0_adjustments_we0; +wire [4:0] dataflow_in_loop_TOP_LOOP38022_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP38022_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP38022_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP38022_U0_adjustments_we1; +wire [14:0] dataflow_in_loop_TOP_LOOP38022_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP38022_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP38022_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP38022_U0_out_data_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP38022_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP38022_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP38022_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP38022_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP38022_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP38022_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP38022_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP38022_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP38022_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP38022_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP38022_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP38022_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP38022_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [18:0] loop_dataflow_input_count; +reg [18:0] loop_dataflow_output_count; +wire [18:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP38022_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP38022_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 19'd0; +#0 loop_dataflow_output_count = 19'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP38022 dataflow_in_loop_TOP_LOOP38022_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP38022_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP38022_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP38022_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP38022_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP38022_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP38022_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP38022_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP38022_U0_in_data_we1), + .filter_data_address0(dataflow_in_loop_TOP_LOOP38022_U0_filter_data_address0), + .filter_data_ce0(dataflow_in_loop_TOP_LOOP38022_U0_filter_data_ce0), + .filter_data_d0(dataflow_in_loop_TOP_LOOP38022_U0_filter_data_d0), + .filter_data_q0(filter_data_q0), + .filter_data_we0(dataflow_in_loop_TOP_LOOP38022_U0_filter_data_we0), + .filter_data_address1(dataflow_in_loop_TOP_LOOP38022_U0_filter_data_address1), + .filter_data_ce1(dataflow_in_loop_TOP_LOOP38022_U0_filter_data_ce1), + .filter_data_d1(dataflow_in_loop_TOP_LOOP38022_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(dataflow_in_loop_TOP_LOOP38022_U0_filter_data_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP38022_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP38022_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP38022_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP38022_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP38022_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP38022_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP38022_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP38022_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP38022_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP38022_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP38022_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP38022_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP38022_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP38022_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP38022_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP38022_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP38022_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP38022_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP38022_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP38022_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP38022_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP38022_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP38022_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 19'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP38022_U0_ap_ready == 1'b1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 19'd1); + end else if (((dataflow_in_loop_TOP_LOOP38022_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= 19'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 19'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP38022_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP38022_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 19'd1); + end else if (((dataflow_in_loop_TOP_LOOP38022_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP38022_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + loop_dataflow_output_count <= 19'd0; + end + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP38022_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP38022_U0_ap_idle == 1'b1) & (loop_dataflow_output_count == 19'd0) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP38022_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP38022_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP38022_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP38022_U0_adjustments_address0; + +assign adjustments_address1 = 5'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP38022_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP38022_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP38022_U0_ap_ready; + +assign bound_minus_1 = (19'd401408 - 19'd1); + +assign dataflow_in_loop_TOP_LOOP38022_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP38022_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP38022_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP38022_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP38022_U0_start_write = 1'b0; + +assign filter_data_address0 = dataflow_in_loop_TOP_LOOP38022_U0_filter_data_address0; + +assign filter_data_address1 = 13'd0; + +assign filter_data_ce0 = dataflow_in_loop_TOP_LOOP38022_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP38022_U0_in_data_address0; + +assign in_data_address1 = 16'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP38022_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP38022_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 15'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP38022_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP38022_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP38022_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP38022_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP38022_U0_out_data_write; + +endmodule //td_fused_top_tdf2_113 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 8'd1; +parameter ap_ST_fsm_pp0_stage0 = 8'd2; +parameter ap_ST_fsm_pp0_stage1 = 8'd4; +parameter ap_ST_fsm_pp0_stage2 = 8'd8; +parameter ap_ST_fsm_pp0_stage3 = 8'd16; +parameter ap_ST_fsm_state12 = 8'd32; +parameter ap_ST_fsm_state13 = 8'd64; +parameter ap_ST_fsm_state14 = 8'd128; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [7:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [7:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[7:0] accum_in_0_address0; +reg accum_in_0_ce0; +reg[7:0] accum_in_0_address1; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [7:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] x_reg_168; +reg [15:0] psum_7_08_reg_180; +reg [15:0] psum_6_07_reg_192; +reg [15:0] psum_5_06_reg_204; +reg [15:0] psum_4_05_reg_216; +reg [15:0] psum_3_04_reg_228; +reg [15:0] psum_2_03_reg_240; +reg [15:0] psum_1_02_reg_252; +reg [15:0] psum_0_01_reg_264; +wire [0:0] icmp_ln49_fu_321_p2; +reg [0:0] icmp_ln49_reg_492; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state6_pp0_stage0_iter1; +wire ap_block_state10_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln49_reg_492_pp0_iter1_reg; +reg [0:0] icmp_ln49_reg_492_pp0_iter2_reg; +reg [15:0] accum_in_0_load_reg_506; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state7_pp0_stage1_iter1; +wire ap_block_state11_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_0_load_50_reg_511; +reg [15:0] accum_in_0_load_51_reg_526; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state8_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_0_load_52_reg_531; +wire [7:0] add_ln49_fu_387_p2; +reg [7:0] add_ln49_reg_546; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state9_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_0_load_53_reg_551; +reg [15:0] accum_in_0_load_54_reg_556; +reg [15:0] accum_in_0_load_55_reg_571; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_0_load_56_reg_576; +wire [15:0] grp_fu_305_p2; +wire [15:0] grp_fu_310_p2; +reg ap_enable_reg_pp0_iter2; +wire [3:0] add_ln57_fu_432_p2; +wire ap_CS_fsm_state13; +wire [0:0] tmp_fu_415_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage1_subdone; +reg [7:0] ap_phi_mux_x_phi_fu_172_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_184_p4; +wire ap_block_pp0_stage1; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_196_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_208_p4; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_220_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_232_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_03_phi_fu_244_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_276; +wire ap_CS_fsm_state12; +reg [15:0] ap_phi_mux_phi_ln69_phi_fu_290_p8; +wire [2:0] trunc_ln57_fu_428_p1; +wire [63:0] zext_ln49_fu_327_p1; +wire [63:0] zext_ln53_fu_338_p1; +wire [63:0] zext_ln53_13_fu_349_p1; +wire [63:0] zext_ln53_14_fu_360_p1; +wire [63:0] zext_ln53_15_fu_371_p1; +wire [63:0] zext_ln53_16_fu_382_p1; +wire [63:0] zext_ln53_17_fu_399_p1; +wire [63:0] zext_ln53_18_fu_410_p1; +wire [63:0] zext_ln57_fu_423_p1; +wire [63:0] zext_ln57_3_fu_444_p1; +reg [15:0] grp_fu_305_p0; +reg [15:0] grp_fu_305_p1; +reg [15:0] grp_fu_310_p0; +reg [15:0] grp_fu_310_p1; +wire [7:0] or_ln53_fu_332_p2; +wire [7:0] or_ln53_13_fu_343_p2; +wire [7:0] or_ln53_14_fu_354_p2; +wire [7:0] or_ln53_15_fu_365_p2; +wire [7:0] or_ln53_16_fu_376_p2; +wire [7:0] or_ln53_17_fu_393_p2; +wire [7:0] or_ln53_18_fu_404_p2; +wire [2:0] or_ln57_fu_438_p2; +wire [0:0] icmp_ln69_fu_449_p2; +wire [0:0] icmp_ln69_5_fu_463_p2; +wire [15:0] select_ln69_fu_455_p3; +wire [0:0] icmp_ln69_6_fu_477_p2; +wire [15:0] select_ln69_5_fu_469_p3; +wire ap_CS_fsm_state14; +reg [7:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_514; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 8'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U96( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_305_p0), + .din1(grp_fu_305_p1), + .dout(grp_fu_305_p2) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U97( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_310_p0), + .din1(grp_fu_310_p1), + .dout(grp_fu_310_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + q_reg_276 <= 4'd0; + end else if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + q_reg_276 <= add_ln57_fu_432_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + x_reg_168 <= add_ln49_reg_546; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_168 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_load_50_reg_511 <= accum_in_0_q0; + accum_in_0_load_reg_506 <= accum_in_0_q1; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_load_51_reg_526 <= accum_in_0_q1; + accum_in_0_load_52_reg_531 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_load_53_reg_551 <= accum_in_0_q1; + accum_in_0_load_54_reg_556 <= accum_in_0_q0; + add_ln49_reg_546 <= add_ln49_fu_387_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_0_load_55_reg_571 <= accum_in_0_q1; + accum_in_0_load_56_reg_576 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln49_reg_492 <= icmp_ln49_fu_321_p2; + icmp_ln49_reg_492_pp0_iter1_reg <= icmp_ln49_reg_492; + icmp_ln49_reg_492_pp0_iter2_reg <= icmp_ln49_reg_492_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_0_01_reg_264 <= grp_fu_305_p2; + psum_1_02_reg_252 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_2_03_reg_240 <= grp_fu_305_p2; + psum_3_04_reg_228 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + psum_4_05_reg_216 <= grp_fu_305_p2; + psum_5_06_reg_204 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_492_pp0_iter2_reg == 1'd1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + psum_6_07_reg_192 <= grp_fu_305_p2; + psum_7_08_reg_180 <= grp_fu_310_p2; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address0 = zext_ln53_18_fu_410_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address0 = zext_ln53_16_fu_382_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address0 = zext_ln53_14_fu_360_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address0 = zext_ln53_fu_338_p1; + end else begin + accum_in_0_address0 = 'bx; + end + end else begin + accum_in_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address1 = zext_ln53_17_fu_399_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address1 = zext_ln53_15_fu_371_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address1 = zext_ln53_13_fu_349_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address1 = zext_ln49_fu_327_p1; + end else begin + accum_in_0_address1 = 'bx; + end + end else begin + accum_in_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln49_reg_492 == 1'd0)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + if ((trunc_ln57_fu_428_p1 == 3'd0)) begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = psum_0_01_reg_264; + end else if ((1'b1 == ap_condition_514)) begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = psum_6_07_reg_192; + end else if ((trunc_ln57_fu_428_p1 == 3'd4)) begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = psum_4_05_reg_216; + end else if ((trunc_ln57_fu_428_p1 == 3'd2)) begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = psum_2_03_reg_240; + end else begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_x_phi_fu_172_p4 = add_ln49_reg_546; + end else begin + ap_phi_mux_x_phi_fu_172_p4 = x_reg_168; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_6_07_phi_fu_196_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_4_05_phi_fu_220_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p0 = ap_phi_mux_psum_2_03_phi_fu_244_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p0 = grp_fu_305_p2; + end else begin + grp_fu_305_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p1 = accum_in_0_load_55_reg_571; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p1 = accum_in_0_load_53_reg_551; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p1 = accum_in_0_load_51_reg_526; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p1 = accum_in_0_load_reg_506; + end else begin + grp_fu_305_p1 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p0 = ap_phi_mux_psum_7_08_phi_fu_184_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p0 = ap_phi_mux_psum_5_06_phi_fu_208_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p0 = ap_phi_mux_psum_3_04_phi_fu_232_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p0 = grp_fu_310_p2; + end else begin + grp_fu_310_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p1 = accum_in_0_load_56_reg_576; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p1 = accum_in_0_load_54_reg_556; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p1 = accum_in_0_load_52_reg_531; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p1 = accum_in_0_load_50_reg_511; + end else begin + grp_fu_310_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (icmp_ln49_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (icmp_ln49_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_state14; + end + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln57_3_fu_444_p1; + +assign accum_out_address1 = zext_ln57_fu_423_p1; + +assign accum_out_d0 = ((icmp_ln69_6_fu_477_p2[0:0] == 1'b1) ? psum_5_06_reg_204 : select_ln69_5_fu_469_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln69_phi_fu_290_p8; + +assign add_ln49_fu_387_p2 = (x_reg_168 + 8'd8); + +assign add_ln57_fu_432_p2 = (q_reg_276 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_state14 = ap_CS_fsm[32'd7]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_514 = (~(trunc_ln57_fu_428_p1 == 3'd0) & ~(trunc_ln57_fu_428_p1 == 3'd4) & ~(trunc_ln57_fu_428_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_03_phi_fu_244_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_232_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_220_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_208_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_196_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_184_p4 = grp_fu_310_p2; + +assign icmp_ln49_fu_321_p2 = ((ap_phi_mux_x_phi_fu_172_p4 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln69_5_fu_463_p2 = ((or_ln57_fu_438_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln69_6_fu_477_p2 = ((or_ln57_fu_438_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln69_fu_449_p2 = ((or_ln57_fu_438_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln53_13_fu_343_p2 = (x_reg_168 | 8'd2); + +assign or_ln53_14_fu_354_p2 = (x_reg_168 | 8'd3); + +assign or_ln53_15_fu_365_p2 = (x_reg_168 | 8'd4); + +assign or_ln53_16_fu_376_p2 = (x_reg_168 | 8'd5); + +assign or_ln53_17_fu_393_p2 = (x_reg_168 | 8'd6); + +assign or_ln53_18_fu_404_p2 = (x_reg_168 | 8'd7); + +assign or_ln53_fu_332_p2 = (ap_phi_mux_x_phi_fu_172_p4 | 8'd1); + +assign or_ln57_fu_438_p2 = (trunc_ln57_fu_428_p1 | 3'd1); + +assign select_ln69_5_fu_469_p3 = ((icmp_ln69_5_fu_463_p2[0:0] == 1'b1) ? psum_3_04_reg_228 : select_ln69_fu_455_p3); + +assign select_ln69_fu_455_p3 = ((icmp_ln69_fu_449_p2[0:0] == 1'b1) ? psum_1_02_reg_252 : psum_7_08_reg_180); + +assign tmp_fu_415_p3 = q_reg_276[32'd3]; + +assign trunc_ln57_fu_428_p1 = q_reg_276[2:0]; + +assign zext_ln49_fu_327_p1 = ap_phi_mux_x_phi_fu_172_p4; + +assign zext_ln53_13_fu_349_p1 = or_ln53_13_fu_343_p2; + +assign zext_ln53_14_fu_360_p1 = or_ln53_14_fu_354_p2; + +assign zext_ln53_15_fu_371_p1 = or_ln53_15_fu_365_p2; + +assign zext_ln53_16_fu_382_p1 = or_ln53_16_fu_376_p2; + +assign zext_ln53_17_fu_399_p1 = or_ln53_17_fu_393_p2; + +assign zext_ln53_18_fu_410_p1 = or_ln53_18_fu_404_p2; + +assign zext_ln53_fu_338_p1 = or_ln53_fu_332_p2; + +assign zext_ln57_3_fu_444_p1 = or_ln57_fu_438_p2; + +assign zext_ln57_fu_423_p1 = q_reg_276; + +endmodule //td_fused_top_tdf2_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_16, + accum_in_16_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 7'd1; +parameter ap_ST_fsm_state2 = 7'd2; +parameter ap_ST_fsm_state3 = 7'd4; +parameter ap_ST_fsm_state4 = 7'd8; +parameter ap_ST_fsm_state5 = 7'd16; +parameter ap_ST_fsm_state6 = 7'd32; +parameter ap_ST_fsm_state7 = 7'd64; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_16; +output accum_in_16_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_16; +reg accum_in_16_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [6:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln81_fu_74_p2; +reg [3:0] add_ln81_reg_91; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln81_fu_85_p2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state7; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln81_fu_80_p1; +reg [15:0] accum_in_16_preg; +reg [6:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 7'd1; +#0 accum_in_16_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U100( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_q0), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_16_preg <= 16'd0; + end else begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_16_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + i_1_1_reg_44 <= add_ln81_reg_91; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln81_reg_91 <= add_ln81_fu_74_p2; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_16 = sum_01_reg_55; + end else begin + accum_in_16 = accum_in_16_preg; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_16_ap_vld = 1'b1; + end else begin + accum_in_16_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln81_fu_80_p1; + +assign add_ln81_fu_74_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln81_fu_85_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln81_fu_80_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf2_accum_2 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf2_adjustments_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 48; +parameter AWIDTH = 5; +parameter MEM_SIZE = 32; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf2_adjustments( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd48; +parameter AddressRange = 32'd32; +parameter AddressWidth = 32'd5; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf2_adjustments_ram td_fused_top_tdf2_adjustments_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 17'd1; +parameter ap_ST_fsm_state2 = 17'd2; +parameter ap_ST_fsm_state3 = 17'd4; +parameter ap_ST_fsm_state4 = 17'd8; +parameter ap_ST_fsm_state5 = 17'd16; +parameter ap_ST_fsm_state6 = 17'd32; +parameter ap_ST_fsm_state7 = 17'd64; +parameter ap_ST_fsm_state8 = 17'd128; +parameter ap_ST_fsm_state9 = 17'd256; +parameter ap_ST_fsm_state10 = 17'd512; +parameter ap_ST_fsm_state11 = 17'd1024; +parameter ap_ST_fsm_state12 = 17'd2048; +parameter ap_ST_fsm_state13 = 17'd4096; +parameter ap_ST_fsm_state14 = 17'd8192; +parameter ap_ST_fsm_state15 = 17'd16384; +parameter ap_ST_fsm_state16 = 17'd32768; +parameter ap_ST_fsm_state17 = 17'd65536; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_read; +output [4:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [4:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg input_indices_23_read; + +reg ap_done_reg; + reg [16:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +wire ap_CS_fsm_state4; +reg [15:0] tmp_69_i_i_reg_167; +reg [15:0] tmp_70_i_i_reg_172; +wire [15:0] grp_fu_81_p2; +reg [15:0] sub_i_i_i_reg_177; +wire ap_CS_fsm_state8; +wire ap_CS_fsm_state9; +wire [15:0] grp_fu_86_p2; +reg [15:0] mul_i_i_i_reg_187; +wire ap_CS_fsm_state12; +wire ap_CS_fsm_state13; +wire [63:0] zext_ln220_fu_90_p1; +reg ap_block_state1; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_77_p1; +wire [15:0] grp_fu_81_p1; +wire [15:0] grp_fu_86_p1; +wire [15:0] trunc_ln220_fu_95_p1; +wire [15:0] grp_fu_77_p2; +wire ap_CS_fsm_state17; +wire [15:0] bitcast_ln648_fu_132_p1; +wire [0:0] tmp_fu_136_p3; +reg [16:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 17'd1; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U104( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(mul_i_i_i_reg_187), + .din1(grp_fu_77_p1), + .dout(grp_fu_77_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U105( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sums_read), + .din1(grp_fu_81_p1), + .dout(grp_fu_81_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U106( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_177), + .din1(grp_fu_86_p1), + .dout(grp_fu_86_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + mul_i_i_i_reg_187 <= grp_fu_86_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sub_i_i_i_reg_177 <= grp_fu_81_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tmp_69_i_i_reg_167 <= {{adjustments_q0[31:16]}}; + tmp_70_i_i_reg_172 <= {{adjustments_q0[47:32]}}; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (~((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign adjustments_address0 = zext_ln220_fu_90_p1; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_return = ((tmp_fu_136_p3[0:0] == 1'b1) ? 16'd0 : grp_fu_77_p2); + +assign bitcast_ln648_fu_132_p1 = grp_fu_77_p2; + +assign grp_fu_77_p1 = tmp_70_i_i_reg_172; + +assign grp_fu_81_p1 = trunc_ln220_fu_95_p1; + +assign grp_fu_86_p1 = tmp_69_i_i_reg_167; + +assign tmp_fu_136_p3 = bitcast_ln648_fu_132_p1[32'd15]; + +assign trunc_ln220_fu_95_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_90_p1 = input_indices_23_dout; + +endmodule //td_fused_top_tdf2_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_q0, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [7:0] ifmap_vec_address0; +output ifmap_vec_ce0; +input [15:0] ifmap_vec_q0; +output [7:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +input [15:0] weight_vecs_0_q0; +output [7:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_ce0; +reg weight_vecs_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] indvar_flatten17_reg_97; +reg [6:0] indvar_flatten_reg_108; +reg [1:0] jj_reg_119; +reg [4:0] ic_reg_131; +reg [1:0] ii_reg_142; +wire [7:0] add_ln147_5_fu_157_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln147_fu_163_p2; +reg [0:0] icmp_ln147_reg_408; +reg [0:0] icmp_ln147_reg_408_pp0_iter1_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter2_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter3_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter4_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter5_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter6_reg; +wire [0:0] icmp_ln148_fu_169_p2; +reg [0:0] icmp_ln148_reg_412; +wire [0:0] and_ln147_fu_195_p2; +reg [0:0] and_ln147_reg_419; +wire [1:0] add_ln148_fu_201_p2; +reg [1:0] add_ln148_reg_424; +wire [4:0] select_ln148_fu_213_p3; +reg [4:0] select_ln148_reg_429; +wire [1:0] select_ln148_13_fu_221_p3; +reg [1:0] select_ln148_13_reg_434; +wire [3:0] trunc_ln150_fu_229_p1; +reg [3:0] trunc_ln150_reg_440; +reg [3:0] trunc_ln150_reg_440_pp0_iter1_reg; +reg [3:0] trunc_ln150_reg_440_pp0_iter2_reg; +reg [3:0] trunc_ln150_reg_440_pp0_iter3_reg; +reg [3:0] trunc_ln150_reg_440_pp0_iter4_reg; +reg [3:0] trunc_ln150_reg_440_pp0_iter5_reg; +reg [3:0] trunc_ln150_reg_440_pp0_iter6_reg; +wire [4:0] add_ln149_fu_233_p2; +wire [6:0] select_ln148_15_fu_245_p3; +wire [1:0] select_ln147_14_fu_287_p3; +reg [1:0] select_ln147_14_reg_455; +reg ap_enable_reg_pp0_iter1; +wire [3:0] select_ln148_14_fu_370_p3; +reg [3:0] select_ln148_14_reg_460; +reg [3:0] select_ln148_14_reg_460_pp0_iter2_reg; +reg [3:0] select_ln148_14_reg_460_pp0_iter3_reg; +reg [3:0] select_ln148_14_reg_460_pp0_iter4_reg; +reg [3:0] select_ln148_14_reg_460_pp0_iter5_reg; +reg [3:0] select_ln148_14_reg_460_pp0_iter6_reg; +reg [15:0] ifmap_vec_load_reg_475; +reg [15:0] weight_vecs_0_load_reg_480; +wire [15:0] grp_fu_153_p2; +reg [15:0] mul_reg_485; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg [1:0] ap_phi_mux_jj_phi_fu_123_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_146_p4; +wire [63:0] p_cast25_fu_386_p1; +wire [63:0] idxprom30_fu_398_p1; +wire [0:0] icmp_ln149_fu_189_p2; +wire [0:0] xor_ln147_fu_183_p2; +wire [1:0] select_ln147_fu_175_p3; +wire [0:0] or_ln148_fu_207_p2; +wire [6:0] add_ln148_5_fu_239_p2; +wire [3:0] shl_ln_fu_257_p3; +wire [3:0] zext_ln150_fu_253_p1; +wire [3:0] sub_ln150_fu_265_p2; +wire [3:0] zext_ln150_5_fu_271_p1; +wire [1:0] add_ln147_fu_281_p2; +wire [3:0] tmp_fu_298_p3; +wire [3:0] select_ln147_18_cast_fu_294_p1; +wire [3:0] shl_ln150_mid1_fu_316_p3; +wire [3:0] zext_ln150_10_fu_312_p1; +wire [3:0] sub_ln150_5_fu_324_p2; +wire [3:0] add_ln150_fu_275_p2; +wire [3:0] empty_112_fu_306_p2; +wire [3:0] select_ln148_17_cast_fu_344_p1; +wire [3:0] empty_113_fu_347_p2; +wire [3:0] select_ln147_15_fu_330_p3; +wire [3:0] zext_ln150_11_fu_361_p1; +wire [3:0] add_ln150_5_fu_364_p2; +wire [3:0] select_ln147_16_fu_337_p3; +wire [7:0] tmp_128_cast_fu_353_p3; +wire [7:0] select_ln148_cast_fu_377_p1; +wire [7:0] empty_114_fu_380_p2; +wire [7:0] p_fu_392_p3; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U92( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_load_reg_475), + .din1(weight_vecs_0_load_reg_480), + .dout(grp_fu_153_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_reg_131 <= add_ln149_fu_233_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_reg_131 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ii_reg_142 <= select_ln147_14_reg_455; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_142 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten17_reg_97 <= add_ln147_5_fu_157_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten17_reg_97 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_108 <= select_ln148_15_fu_245_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_108 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_119 <= select_ln148_13_reg_434; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_119 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln148_reg_424 <= add_ln148_fu_201_p2; + and_ln147_reg_419 <= and_ln147_fu_195_p2; + icmp_ln148_reg_412 <= icmp_ln148_fu_169_p2; + select_ln148_reg_429 <= select_ln148_fu_213_p3; + trunc_ln150_reg_440 <= trunc_ln150_fu_229_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln147_reg_408 <= icmp_ln147_fu_163_p2; + icmp_ln147_reg_408_pp0_iter1_reg <= icmp_ln147_reg_408; + trunc_ln150_reg_440_pp0_iter1_reg <= trunc_ln150_reg_440; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln147_reg_408_pp0_iter2_reg <= icmp_ln147_reg_408_pp0_iter1_reg; + icmp_ln147_reg_408_pp0_iter3_reg <= icmp_ln147_reg_408_pp0_iter2_reg; + icmp_ln147_reg_408_pp0_iter4_reg <= icmp_ln147_reg_408_pp0_iter3_reg; + icmp_ln147_reg_408_pp0_iter5_reg <= icmp_ln147_reg_408_pp0_iter4_reg; + icmp_ln147_reg_408_pp0_iter6_reg <= icmp_ln147_reg_408_pp0_iter5_reg; + select_ln148_14_reg_460_pp0_iter2_reg <= select_ln148_14_reg_460; + select_ln148_14_reg_460_pp0_iter3_reg <= select_ln148_14_reg_460_pp0_iter2_reg; + select_ln148_14_reg_460_pp0_iter4_reg <= select_ln148_14_reg_460_pp0_iter3_reg; + select_ln148_14_reg_460_pp0_iter5_reg <= select_ln148_14_reg_460_pp0_iter4_reg; + select_ln148_14_reg_460_pp0_iter6_reg <= select_ln148_14_reg_460_pp0_iter5_reg; + trunc_ln150_reg_440_pp0_iter2_reg <= trunc_ln150_reg_440_pp0_iter1_reg; + trunc_ln150_reg_440_pp0_iter3_reg <= trunc_ln150_reg_440_pp0_iter2_reg; + trunc_ln150_reg_440_pp0_iter4_reg <= trunc_ln150_reg_440_pp0_iter3_reg; + trunc_ln150_reg_440_pp0_iter5_reg <= trunc_ln150_reg_440_pp0_iter4_reg; + trunc_ln150_reg_440_pp0_iter6_reg <= trunc_ln150_reg_440_pp0_iter5_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_load_reg_475 <= ifmap_vec_q0; + weight_vecs_0_load_reg_480 <= weight_vecs_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_reg_485 <= grp_fu_153_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + select_ln147_14_reg_455 <= select_ln147_14_fu_287_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_13_reg_434 <= select_ln148_13_fu_221_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_14_reg_460 <= select_ln148_14_fu_370_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_fu_163_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_146_p4 = select_ln147_14_reg_455; + end else begin + ap_phi_mux_ii_phi_fu_146_p4 = ii_reg_142; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_123_p4 = select_ln148_13_reg_434; + end else begin + ap_phi_mux_jj_phi_fu_123_p4 = jj_reg_119; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_5_fu_157_p2 = (indvar_flatten17_reg_97 + 8'd1); + +assign add_ln147_fu_281_p2 = (ap_phi_mux_ii_phi_fu_146_p4 + 2'd1); + +assign add_ln148_5_fu_239_p2 = (indvar_flatten_reg_108 + 7'd1); + +assign add_ln148_fu_201_p2 = (select_ln147_fu_175_p3 + 2'd1); + +assign add_ln149_fu_233_p2 = (select_ln148_fu_213_p3 + 5'd1); + +assign add_ln150_5_fu_364_p2 = (select_ln147_15_fu_330_p3 + zext_ln150_11_fu_361_p1); + +assign add_ln150_fu_275_p2 = (sub_ln150_fu_265_p2 + zext_ln150_5_fu_271_p1); + +assign and_ln147_fu_195_p2 = (xor_ln147_fu_183_p2 & icmp_ln149_fu_189_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign empty_112_fu_306_p2 = (tmp_fu_298_p3 - select_ln147_18_cast_fu_294_p1); + +assign empty_113_fu_347_p2 = (empty_112_fu_306_p2 + select_ln148_17_cast_fu_344_p1); + +assign empty_114_fu_380_p2 = (tmp_128_cast_fu_353_p3 + select_ln148_cast_fu_377_p1); + +assign icmp_ln147_fu_163_p2 = ((indvar_flatten17_reg_97 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln148_fu_169_p2 = ((indvar_flatten_reg_108 == 7'd48) ? 1'b1 : 1'b0); + +assign icmp_ln149_fu_189_p2 = ((ic_reg_131 == 5'd16) ? 1'b1 : 1'b0); + +assign idxprom30_fu_398_p1 = p_fu_392_p3; + +assign ifmap_vec_address0 = p_cast25_fu_386_p1; + +assign or_ln148_fu_207_p2 = (icmp_ln148_fu_169_p2 | and_ln147_fu_195_p2); + +assign p_cast25_fu_386_p1 = empty_114_fu_380_p2; + +assign p_fu_392_p3 = {{select_ln148_14_reg_460_pp0_iter6_reg}, {trunc_ln150_reg_440_pp0_iter6_reg}}; + +assign products_0_address0 = idxprom30_fu_398_p1; + +assign products_0_d0 = mul_reg_485; + +assign select_ln147_14_fu_287_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? add_ln147_fu_281_p2 : ap_phi_mux_ii_phi_fu_146_p4); + +assign select_ln147_15_fu_330_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? sub_ln150_5_fu_324_p2 : sub_ln150_fu_265_p2); + +assign select_ln147_16_fu_337_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? sub_ln150_5_fu_324_p2 : add_ln150_fu_275_p2); + +assign select_ln147_18_cast_fu_294_p1 = select_ln147_14_fu_287_p3; + +assign select_ln147_fu_175_p3 = ((icmp_ln148_fu_169_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_123_p4); + +assign select_ln148_13_fu_221_p3 = ((and_ln147_fu_195_p2[0:0] == 1'b1) ? add_ln148_fu_201_p2 : select_ln147_fu_175_p3); + +assign select_ln148_14_fu_370_p3 = ((and_ln147_reg_419[0:0] == 1'b1) ? add_ln150_5_fu_364_p2 : select_ln147_16_fu_337_p3); + +assign select_ln148_15_fu_245_p3 = ((icmp_ln148_fu_169_p2[0:0] == 1'b1) ? 7'd1 : add_ln148_5_fu_239_p2); + +assign select_ln148_17_cast_fu_344_p1 = select_ln148_13_reg_434; + +assign select_ln148_cast_fu_377_p1 = select_ln148_reg_429; + +assign select_ln148_fu_213_p3 = ((or_ln148_fu_207_p2[0:0] == 1'b1) ? 5'd0 : ic_reg_131); + +assign shl_ln150_mid1_fu_316_p3 = {{add_ln147_fu_281_p2}, {2'd0}}; + +assign shl_ln_fu_257_p3 = {{ap_phi_mux_ii_phi_fu_146_p4}, {2'd0}}; + +assign sub_ln150_5_fu_324_p2 = (shl_ln150_mid1_fu_316_p3 - zext_ln150_10_fu_312_p1); + +assign sub_ln150_fu_265_p2 = (shl_ln_fu_257_p3 - zext_ln150_fu_253_p1); + +assign tmp_128_cast_fu_353_p3 = {{empty_113_fu_347_p2}, {4'd0}}; + +assign tmp_fu_298_p3 = {{select_ln147_14_fu_287_p3}, {2'd0}}; + +assign trunc_ln150_fu_229_p1 = select_ln148_fu_213_p3[3:0]; + +assign weight_vecs_0_address0 = p_cast25_fu_386_p1; + +assign xor_ln147_fu_183_p2 = (icmp_ln148_fu_169_p2 ^ 1'd1); + +assign zext_ln150_10_fu_312_p1 = add_ln147_fu_281_p2; + +assign zext_ln150_11_fu_361_p1 = add_ln148_reg_424; + +assign zext_ln150_5_fu_271_p1 = jj_reg_119; + +assign zext_ln150_fu_253_p1 = ap_phi_mux_ii_phi_fu_146_p4; + +endmodule //td_fused_top_tdf2_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf2_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 13; +parameter MEM_SIZE = 4608; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf2_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd4608; +parameter AddressWidth = 32'd13; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf2_filters_ram td_fused_top_tdf2_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + input_indices_2_out_din, + input_indices_2_out_full_n, + input_indices_2_out_write, + input_indices_2_out1_din, + input_indices_2_out1_full_n, + input_indices_2_out1_write, + output_indices_0_din, + output_indices_0_full_n, + output_indices_0_write, + output_indices_1_din, + output_indices_1_full_n, + output_indices_1_write, + resetMaximum_din, + resetMaximum_full_n, + resetMaximum_write, + storeOutput_din, + storeOutput_full_n, + storeOutput_write, + ap_return_0, + ap_return_1 +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [4:0] input_indices_2_out_din; +input input_indices_2_out_full_n; +output input_indices_2_out_write; +output [4:0] input_indices_2_out1_din; +input input_indices_2_out1_full_n; +output input_indices_2_out1_write; +output [5:0] output_indices_0_din; +input output_indices_0_full_n; +output output_indices_0_write; +output [11:0] output_indices_1_din; +input output_indices_1_full_n; +output output_indices_1_write; +output resetMaximum_din; +input resetMaximum_full_n; +output resetMaximum_write; +output storeOutput_din; +input storeOutput_full_n; +output storeOutput_write; +output [15:0] ap_return_0; +output [15:0] ap_return_1; + +reg ap_done; +reg ap_idle; +reg start_write; +reg input_indices_2_out_write; +reg input_indices_2_out1_write; +reg output_indices_0_write; +reg output_indices_1_write; +reg resetMaximum_write; +reg storeOutput_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [1:0] i_p_2; +reg [1:0] j_p_2; +reg [15:0] i_6; +reg [15:0] j_6; +reg [15:0] k_6; +reg [15:0] i_out_2; +reg [15:0] j_out_2; +reg input_indices_2_out_blk_n; +reg input_indices_2_out1_blk_n; +reg output_indices_0_blk_n; +reg output_indices_1_blk_n; +reg resetMaximum_blk_n; +reg storeOutput_blk_n; +wire [1:0] select_ln142_fu_338_p3; +reg ap_block_state1; +wire [0:0] or_ln142_fu_312_p2; +wire [1:0] select_ln142_9_fu_346_p3; +wire [15:0] select_ln147_fu_278_p3; +wire [0:0] and_ln142_3_fu_306_p2; +wire [15:0] select_ln142_10_fu_360_p3; +wire [0:0] and_ln132_fu_354_p2; +wire [15:0] select_ln142_11_fu_388_p3; +wire [0:0] and_ln135_fu_294_p2; +wire [15:0] select_ln147_3_fu_286_p3; +wire [15:0] select_ln142_12_fu_396_p3; +wire [4:0] trunc_ln128_fu_182_p1; +wire [1:0] or_ln124_fu_126_p2; +wire [0:0] icmp_ln125_fu_139_p2; +wire [0:0] icmp_ln125_3_fu_145_p2; +wire [15:0] zext_ln126_fu_114_p1; +wire [15:0] zext_ln127_fu_122_p1; +wire [1:0] add_ln131_fu_206_p2; +wire [1:0] add_ln134_fu_218_p2; +wire [15:0] add_ln137_fu_230_p2; +wire [15:0] add_ln141_fu_248_p2; +wire [15:0] add_ln146_fu_266_p2; +wire [0:0] icmp_ln147_fu_272_p2; +wire [15:0] add_ln145_fu_260_p2; +wire [0:0] icmp_ln132_fu_212_p2; +wire [0:0] icmp_ln135_fu_224_p2; +wire [0:0] icmp_ln138_fu_236_p2; +wire [0:0] icmp_ln142_fu_254_p2; +wire [0:0] and_ln142_fu_300_p2; +wire [0:0] xor_ln135_fu_318_p2; +wire [0:0] and_ln135_3_fu_324_p2; +wire [1:0] select_ln135_fu_330_p3; +wire [15:0] add_ln140_fu_242_p2; +wire [0:0] xor_ln138_fu_368_p2; +wire [0:0] and_ln138_fu_374_p2; +wire [15:0] select_ln138_fu_380_p3; +wire [15:0] add_ln126_fu_162_p2; +wire [15:0] add_ln127_fu_172_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_p_2 = 2'd0; +#0 j_p_2 = 2'd0; +#0 i_6 = 16'd0; +#0 j_6 = 16'd0; +#0 k_6 = 16'd0; +#0 i_out_2 = 16'd0; +#0 j_out_2 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln142_3_fu_306_p2))) begin + i_6 <= select_ln147_fu_278_p3; + i_out_2 <= select_ln147_3_fu_286_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (or_ln142_fu_312_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_p_2 <= select_ln142_fu_338_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln132_fu_354_p2))) begin + j_6 <= select_ln142_10_fu_360_p3; + j_out_2 <= select_ln142_12_fu_396_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + j_p_2 <= select_ln142_9_fu_346_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln135_fu_294_p2))) begin + k_6 <= select_ln142_11_fu_388_p3; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_blk_n = input_indices_2_out1_full_n; + end else begin + input_indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_write = 1'b1; + end else begin + input_indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_blk_n = input_indices_2_out_full_n; + end else begin + input_indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_write = 1'b1; + end else begin + input_indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_blk_n = output_indices_0_full_n; + end else begin + output_indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_write = 1'b1; + end else begin + output_indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_blk_n = output_indices_1_full_n; + end else begin + output_indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_write = 1'b1; + end else begin + output_indices_1_write = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_blk_n = resetMaximum_full_n; + end else begin + resetMaximum_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_write = 1'b1; + end else begin + resetMaximum_write = 1'b0; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_blk_n = storeOutput_full_n; + end else begin + storeOutput_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_write = 1'b1; + end else begin + storeOutput_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln126_fu_162_p2 = (i_6 + zext_ln126_fu_114_p1); + +assign add_ln127_fu_172_p2 = (j_6 + zext_ln127_fu_122_p1); + +assign add_ln131_fu_206_p2 = (j_p_2 + 2'd1); + +assign add_ln134_fu_218_p2 = (i_p_2 + 2'd1); + +assign add_ln137_fu_230_p2 = (k_6 + 16'd1); + +assign add_ln140_fu_242_p2 = (j_6 + 16'd2); + +assign add_ln141_fu_248_p2 = (j_out_2 + 16'd1); + +assign add_ln145_fu_260_p2 = (i_6 + 16'd2); + +assign add_ln146_fu_266_p2 = (i_out_2 + 16'd1); + +assign and_ln132_fu_354_p2 = (icmp_ln138_fu_236_p2 & and_ln135_fu_294_p2); + +assign and_ln135_3_fu_324_p2 = (xor_ln135_fu_318_p2 & icmp_ln132_fu_212_p2); + +assign and_ln135_fu_294_p2 = (icmp_ln135_fu_224_p2 & icmp_ln132_fu_212_p2); + +assign and_ln138_fu_374_p2 = (xor_ln138_fu_368_p2 & and_ln135_fu_294_p2); + +assign and_ln142_3_fu_306_p2 = (and_ln142_fu_300_p2 & and_ln135_fu_294_p2); + +assign and_ln142_fu_300_p2 = (icmp_ln142_fu_254_p2 & icmp_ln138_fu_236_p2); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign ap_return_0 = add_ln126_fu_162_p2; + +assign ap_return_1 = add_ln127_fu_172_p2; + +assign icmp_ln125_3_fu_145_p2 = ((j_p_2 == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln125_fu_139_p2 = ((i_p_2 == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln132_fu_212_p2 = ((add_ln131_fu_206_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln135_fu_224_p2 = ((add_ln134_fu_218_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln138_fu_236_p2 = ((add_ln137_fu_230_p2 == 16'd32) ? 1'b1 : 1'b0); + +assign icmp_ln142_fu_254_p2 = ((add_ln141_fu_248_p2 == 16'd56) ? 1'b1 : 1'b0); + +assign icmp_ln147_fu_272_p2 = ((add_ln146_fu_266_p2 == 16'd56) ? 1'b1 : 1'b0); + +assign input_indices_2_out1_din = trunc_ln128_fu_182_p1; + +assign input_indices_2_out_din = trunc_ln128_fu_182_p1; + +assign or_ln124_fu_126_p2 = (j_p_2 | i_p_2); + +assign or_ln142_fu_312_p2 = (icmp_ln132_fu_212_p2 | and_ln142_3_fu_306_p2); + +assign output_indices_0_din = i_out_2[5:0]; + +assign output_indices_1_din = j_out_2[11:0]; + +assign resetMaximum_din = ((or_ln124_fu_126_p2 == 2'd0) ? 1'b1 : 1'b0); + +assign select_ln135_fu_330_p3 = ((and_ln135_3_fu_324_p2[0:0] == 1'b1) ? add_ln134_fu_218_p2 : 2'd0); + +assign select_ln138_fu_380_p3 = ((and_ln138_fu_374_p2[0:0] == 1'b1) ? add_ln137_fu_230_p2 : 16'd0); + +assign select_ln142_10_fu_360_p3 = ((and_ln142_3_fu_306_p2[0:0] == 1'b1) ? 16'd0 : add_ln140_fu_242_p2); + +assign select_ln142_11_fu_388_p3 = ((and_ln142_3_fu_306_p2[0:0] == 1'b1) ? 16'd0 : select_ln138_fu_380_p3); + +assign select_ln142_12_fu_396_p3 = ((and_ln142_3_fu_306_p2[0:0] == 1'b1) ? 16'd0 : add_ln141_fu_248_p2); + +assign select_ln142_9_fu_346_p3 = ((or_ln142_fu_312_p2[0:0] == 1'b1) ? 2'd0 : add_ln131_fu_206_p2); + +assign select_ln142_fu_338_p3 = ((and_ln142_3_fu_306_p2[0:0] == 1'b1) ? 2'd0 : select_ln135_fu_330_p3); + +assign select_ln147_3_fu_286_p3 = ((icmp_ln147_fu_272_p2[0:0] == 1'b1) ? 16'd0 : add_ln146_fu_266_p2); + +assign select_ln147_fu_278_p3 = ((icmp_ln147_fu_272_p2[0:0] == 1'b1) ? 16'd0 : add_ln145_fu_260_p2); + +assign start_out = real_start; + +assign storeOutput_din = (icmp_ln125_fu_139_p2 & icmp_ln125_3_fu_145_p2); + +assign trunc_ln128_fu_182_p1 = k_6[4:0]; + +assign xor_ln135_fu_318_p2 = (icmp_ln135_fu_224_p2 ^ 1'd1); + +assign xor_ln138_fu_368_p2 = (icmp_ln138_fu_236_p2 ^ 1'd1); + +assign zext_ln126_fu_114_p1 = i_p_2; + +assign zext_ln127_fu_122_p1 = j_p_2; + +endmodule //td_fused_top_tdf2_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_poolOutputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + output_indices_04_dout, + output_indices_04_empty_n, + output_indices_04_read, + output_indices_15_dout, + output_indices_15_empty_n, + output_indices_15_read, + resetMaximum6_dout, + resetMaximum6_empty_n, + resetMaximum6_read, + storeOutput7_dout, + storeOutput7_empty_n, + storeOutput7_read, + p_read, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_state3 = 4'd4; +parameter ap_ST_fsm_state4 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [5:0] output_indices_04_dout; +input output_indices_04_empty_n; +output output_indices_04_read; +input [11:0] output_indices_15_dout; +input output_indices_15_empty_n; +output output_indices_15_read; +input [0:0] resetMaximum6_dout; +input resetMaximum6_empty_n; +output resetMaximum6_read; +input [0:0] storeOutput7_dout; +input storeOutput7_empty_n; +output storeOutput7_read; +input [15:0] p_read; +output [14:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg output_indices_04_read; +reg output_indices_15_read; +reg resetMaximum6_read; +reg storeOutput7_read; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] max_vals_4_0; +reg output_indices_04_blk_n; +wire ap_CS_fsm_state2; +reg output_indices_15_blk_n; +reg resetMaximum6_blk_n; +reg storeOutput7_blk_n; +reg [5:0] output_indices_04_read_reg_147; +reg [11:0] output_indices_15_read_reg_152; +wire [0:0] storeOutput7_read_read_fu_82_p2; +reg [0:0] storeOutput7_read_reg_157; +wire grp_tdf2_writeOutputs_unaligned_fu_88_ap_start; +wire grp_tdf2_writeOutputs_unaligned_fu_88_ap_done; +wire grp_tdf2_writeOutputs_unaligned_fu_88_ap_idle; +wire grp_tdf2_writeOutputs_unaligned_fu_88_ap_ready; +wire [14:0] grp_tdf2_writeOutputs_unaligned_fu_88_out_data_address1; +wire grp_tdf2_writeOutputs_unaligned_fu_88_out_data_ce1; +wire grp_tdf2_writeOutputs_unaligned_fu_88_out_data_we1; +wire [63:0] grp_tdf2_writeOutputs_unaligned_fu_88_out_data_d1; +reg grp_tdf2_writeOutputs_unaligned_fu_88_ap_start_reg; +wire ap_CS_fsm_state3; +wire ap_CS_fsm_state4; +reg ap_block_state4_on_subcall_done; +wire [15:0] select_ln24_fu_126_p3; +reg ap_block_state2; +reg ap_block_state1; +wire [0:0] grp_fu_110_p2; +wire [0:0] or_ln24_fu_120_p2; +reg grp_fu_110_ce; +reg [3:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 max_vals_4_0 = 16'd0; +#0 grp_tdf2_writeOutputs_unaligned_fu_88_ap_start_reg = 1'b0; +end + +td_fused_top_tdf2_writeOutputs_unaligned grp_tdf2_writeOutputs_unaligned_fu_88( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(grp_tdf2_writeOutputs_unaligned_fu_88_ap_start), + .ap_done(grp_tdf2_writeOutputs_unaligned_fu_88_ap_done), + .ap_idle(grp_tdf2_writeOutputs_unaligned_fu_88_ap_idle), + .ap_ready(grp_tdf2_writeOutputs_unaligned_fu_88_ap_ready), + .i(output_indices_04_read_reg_147), + .j(output_indices_15_read_reg_152), + .out_data_address1(grp_tdf2_writeOutputs_unaligned_fu_88_out_data_address1), + .out_data_ce1(grp_tdf2_writeOutputs_unaligned_fu_88_out_data_ce1), + .out_data_we1(grp_tdf2_writeOutputs_unaligned_fu_88_out_data_we1), + .out_data_d1(grp_tdf2_writeOutputs_unaligned_fu_88_out_data_d1), + .max_vals_4_0(max_vals_4_0) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U114( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_110_ce), + .din0(max_vals_4_0), + .din1(p_read), + .opcode(5'd4), + .dout(grp_fu_110_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + grp_tdf2_writeOutputs_unaligned_fu_88_ap_start_reg <= 1'b0; + end else begin + if ((1'b1 == ap_CS_fsm_state3)) begin + grp_tdf2_writeOutputs_unaligned_fu_88_ap_start_reg <= 1'b1; + end else if ((grp_tdf2_writeOutputs_unaligned_fu_88_ap_ready == 1'b1)) begin + grp_tdf2_writeOutputs_unaligned_fu_88_ap_start_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + max_vals_4_0 <= select_ln24_fu_126_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_04_read_reg_147 <= output_indices_04_dout; + output_indices_15_read_reg_152 <= output_indices_15_dout; + storeOutput7_read_reg_157 <= storeOutput7_dout; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_110_ce = 1'b1; + end else begin + grp_fu_110_ce = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_04_blk_n = output_indices_04_empty_n; + end else begin + output_indices_04_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_04_read = 1'b1; + end else begin + output_indices_04_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_15_blk_n = output_indices_15_empty_n; + end else begin + output_indices_15_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_15_read = 1'b1; + end else begin + output_indices_15_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + resetMaximum6_blk_n = resetMaximum6_empty_n; + end else begin + resetMaximum6_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + resetMaximum6_read = 1'b1; + end else begin + resetMaximum6_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + storeOutput7_blk_n = storeOutput7_empty_n; + end else begin + storeOutput7_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + storeOutput7_read = 1'b1; + end else begin + storeOutput7_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_82_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_82_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state3; + end else begin + ap_NS_fsm = ap_ST_fsm_state2; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +always @ (*) begin + ap_block_state2 = ((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)); +end + +always @ (*) begin + ap_block_state4_on_subcall_done = ((grp_tdf2_writeOutputs_unaligned_fu_88_ap_done == 1'b0) & (storeOutput7_read_reg_157 == 1'd1)); +end + +assign grp_tdf2_writeOutputs_unaligned_fu_88_ap_start = grp_tdf2_writeOutputs_unaligned_fu_88_ap_start_reg; + +assign or_ln24_fu_120_p2 = (resetMaximum6_dout | grp_fu_110_p2); + +assign out_data_address1 = grp_tdf2_writeOutputs_unaligned_fu_88_out_data_address1; + +assign out_data_ce1 = grp_tdf2_writeOutputs_unaligned_fu_88_out_data_ce1; + +assign out_data_d1 = grp_tdf2_writeOutputs_unaligned_fu_88_out_data_d1; + +assign out_data_we1 = grp_tdf2_writeOutputs_unaligned_fu_88_out_data_we1; + +assign select_ln24_fu_126_p3 = ((or_ln24_fu_120_p2[0:0] == 1'b1) ? p_read : max_vals_4_0); + +assign storeOutput7_read_read_fu_82_p2 = storeOutput7_dout; + +endmodule //td_fused_top_tdf2_poolOutputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_readFilters24 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_we0, + weight_vecs_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state7 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [12:0] filter_data_address0; +output filter_data_ce0; +input [15:0] filter_data_q0; +input [4:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [7:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +output weight_vecs_0_we0; +output [15:0] weight_vecs_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg input_indices_23_read; +reg weight_vecs_0_ce0; +reg weight_vecs_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +reg [7:0] indvar_flatten13_reg_123; +reg [1:0] ii_reg_134; +reg [6:0] indvar_flatten_reg_145; +reg [1:0] jj_reg_156; +reg [4:0] kk_reg_167; +wire [8:0] sext_ln47_fu_200_p1; +reg [8:0] sext_ln47_reg_408; +wire [7:0] add_ln47_5_fu_204_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln47_fu_210_p2; +reg [0:0] icmp_ln47_reg_418; +reg [0:0] icmp_ln47_reg_418_pp0_iter1_reg; +reg [0:0] icmp_ln47_reg_418_pp0_iter2_reg; +reg [0:0] icmp_ln47_reg_418_pp0_iter3_reg; +wire [0:0] icmp_ln48_fu_222_p2; +reg [0:0] icmp_ln48_reg_422; +wire [1:0] select_ln47_5_fu_228_p3; +reg [1:0] select_ln47_5_reg_429; +wire [6:0] select_ln48_10_fu_242_p3; +wire [1:0] select_ln48_9_fu_329_p3; +reg [1:0] select_ln48_9_reg_442; +reg ap_enable_reg_pp0_iter1; +wire [7:0] add_ln55_20_fu_392_p2; +reg [7:0] add_ln55_20_reg_452; +reg [7:0] add_ln55_20_reg_452_pp0_iter2_reg; +reg [7:0] add_ln55_20_reg_452_pp0_iter3_reg; +wire [4:0] add_ln49_fu_398_p2; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg [1:0] ap_phi_mux_ii_phi_fu_138_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_160_p4; +wire [63:0] zext_ln55_47_fu_387_p1; +wire [63:0] zext_ln55_48_fu_404_p1; +wire [6:0] tmp_fu_182_p3; +wire [7:0] zext_ln55_40_fu_190_p1; +wire [7:0] zext_ln55_fu_178_p1; +wire [7:0] sub_ln55_fu_194_p2; +wire [1:0] add_ln47_fu_216_p2; +wire [6:0] add_ln48_5_fu_236_p2; +wire [8:0] zext_ln55_42_fu_260_p1; +wire [8:0] add_ln55_fu_263_p2; +wire [8:0] shl_ln55_fu_268_p2; +wire [3:0] tmp_s_fu_280_p3; +wire [3:0] zext_ln55_41_fu_257_p1; +wire [0:0] icmp_ln49_fu_298_p2; +wire [0:0] xor_ln47_fu_293_p2; +wire [1:0] select_ln47_fu_250_p3; +wire [0:0] and_ln47_fu_304_p2; +wire [0:0] or_ln48_fu_316_p2; +wire [1:0] add_ln48_fu_310_p2; +wire [8:0] sub_ln55_9_fu_274_p2; +wire [8:0] zext_ln55_44_fu_341_p1; +wire [8:0] add_ln55_17_fu_345_p2; +wire [3:0] sub_ln55_10_fu_287_p2; +wire [3:0] zext_ln55_43_fu_337_p1; +wire [3:0] add_ln55_18_fu_359_p2; +wire [4:0] select_ln48_fu_321_p3; +wire [12:0] tmp_124_cast_fu_351_p3; +wire [12:0] zext_ln55_46_fu_377_p1; +wire [12:0] add_ln55_19_fu_381_p2; +wire [7:0] tmp_126_cast_fu_365_p3; +wire [7:0] zext_ln55_45_fu_373_p1; +wire ap_CS_fsm_state7; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ii_reg_134 <= select_ln47_5_reg_429; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_134 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten13_reg_123 <= add_ln47_5_fu_204_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_123 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_145 <= select_ln48_10_fu_242_p3; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_145 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_418_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + jj_reg_156 <= select_ln48_9_reg_442; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_156 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_reg_167 <= add_ln49_fu_398_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_167 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln55_20_reg_452 <= add_ln55_20_fu_392_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln55_20_reg_452_pp0_iter2_reg <= add_ln55_20_reg_452; + add_ln55_20_reg_452_pp0_iter3_reg <= add_ln55_20_reg_452_pp0_iter2_reg; + icmp_ln47_reg_418_pp0_iter2_reg <= icmp_ln47_reg_418_pp0_iter1_reg; + icmp_ln47_reg_418_pp0_iter3_reg <= icmp_ln47_reg_418_pp0_iter2_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln47_reg_418 <= icmp_ln47_fu_210_p2; + icmp_ln47_reg_418_pp0_iter1_reg <= icmp_ln47_reg_418; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln48_reg_422 <= icmp_ln48_fu_222_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln47_5_reg_429 <= select_ln47_5_fu_228_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln48_9_reg_442 <= select_ln48_9_fu_329_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sext_ln47_reg_408 <= sext_ln47_fu_200_p1; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln47_fu_210_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_138_p4 = select_ln47_5_reg_429; + end else begin + ap_phi_mux_ii_phi_fu_138_p4 = ii_reg_134; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_418_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_160_p4 = select_ln48_9_reg_442; + end else begin + ap_phi_mux_jj_phi_fu_160_p4 = jj_reg_156; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_418_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + weight_vecs_0_we0 = 1'b1; + end else begin + weight_vecs_0_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln47_5_fu_204_p2 = (indvar_flatten13_reg_123 + 8'd1); + +assign add_ln47_fu_216_p2 = (ap_phi_mux_ii_phi_fu_138_p4 + 2'd1); + +assign add_ln48_5_fu_236_p2 = (indvar_flatten_reg_145 + 7'd1); + +assign add_ln48_fu_310_p2 = (select_ln47_fu_250_p3 + 2'd1); + +assign add_ln49_fu_398_p2 = (select_ln48_fu_321_p3 + 5'd1); + +assign add_ln55_17_fu_345_p2 = (sub_ln55_9_fu_274_p2 + zext_ln55_44_fu_341_p1); + +assign add_ln55_18_fu_359_p2 = (sub_ln55_10_fu_287_p2 + zext_ln55_43_fu_337_p1); + +assign add_ln55_19_fu_381_p2 = (tmp_124_cast_fu_351_p3 + zext_ln55_46_fu_377_p1); + +assign add_ln55_20_fu_392_p2 = (tmp_126_cast_fu_365_p3 + zext_ln55_45_fu_373_p1); + +assign add_ln55_fu_263_p2 = ((sext_ln47_reg_408) + (zext_ln55_42_fu_260_p1)); + +assign and_ln47_fu_304_p2 = (xor_ln47_fu_293_p2 & icmp_ln49_fu_298_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_address0 = zext_ln55_47_fu_387_p1; + +assign icmp_ln47_fu_210_p2 = ((indvar_flatten13_reg_123 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln48_fu_222_p2 = ((indvar_flatten_reg_145 == 7'd48) ? 1'b1 : 1'b0); + +assign icmp_ln49_fu_298_p2 = ((kk_reg_167 == 5'd16) ? 1'b1 : 1'b0); + +assign or_ln48_fu_316_p2 = (icmp_ln48_reg_422 | and_ln47_fu_304_p2); + +assign select_ln47_5_fu_228_p3 = ((icmp_ln48_fu_222_p2[0:0] == 1'b1) ? add_ln47_fu_216_p2 : ap_phi_mux_ii_phi_fu_138_p4); + +assign select_ln47_fu_250_p3 = ((icmp_ln48_reg_422[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_160_p4); + +assign select_ln48_10_fu_242_p3 = ((icmp_ln48_fu_222_p2[0:0] == 1'b1) ? 7'd1 : add_ln48_5_fu_236_p2); + +assign select_ln48_9_fu_329_p3 = ((and_ln47_fu_304_p2[0:0] == 1'b1) ? add_ln48_fu_310_p2 : select_ln47_fu_250_p3); + +assign select_ln48_fu_321_p3 = ((or_ln48_fu_316_p2[0:0] == 1'b1) ? 5'd0 : kk_reg_167); + +assign sext_ln47_fu_200_p1 = (sub_ln55_fu_194_p2); + +assign shl_ln55_fu_268_p2 = add_ln55_fu_263_p2 << 9'd2; + +assign sub_ln55_10_fu_287_p2 = (tmp_s_fu_280_p3 - zext_ln55_41_fu_257_p1); + +assign sub_ln55_9_fu_274_p2 = (shl_ln55_fu_268_p2 - add_ln55_fu_263_p2); + +assign sub_ln55_fu_194_p2 = (zext_ln55_40_fu_190_p1 - zext_ln55_fu_178_p1); + +assign tmp_124_cast_fu_351_p3 = {{add_ln55_17_fu_345_p2}, {4'd0}}; + +assign tmp_126_cast_fu_365_p3 = {{add_ln55_18_fu_359_p2}, {4'd0}}; + +assign tmp_fu_182_p3 = {{input_indices_23_dout}, {2'd0}}; + +assign tmp_s_fu_280_p3 = {{select_ln47_5_reg_429}, {2'd0}}; + +assign weight_vecs_0_address0 = zext_ln55_48_fu_404_p1; + +assign weight_vecs_0_d0 = filter_data_q0; + +assign xor_ln47_fu_293_p2 = (icmp_ln48_reg_422 ^ 1'd1); + +assign zext_ln55_40_fu_190_p1 = tmp_fu_182_p3; + +assign zext_ln55_41_fu_257_p1 = select_ln47_5_reg_429; + +assign zext_ln55_42_fu_260_p1 = select_ln47_5_reg_429; + +assign zext_ln55_43_fu_337_p1 = select_ln48_9_fu_329_p3; + +assign zext_ln55_44_fu_341_p1 = select_ln48_9_fu_329_p3; + +assign zext_ln55_45_fu_373_p1 = select_ln48_fu_321_p3; + +assign zext_ln55_46_fu_377_p1 = select_ln48_fu_321_p3; + +assign zext_ln55_47_fu_387_p1 = add_ln55_19_fu_381_p2; + +assign zext_ln55_48_fu_404_p1 = add_ln55_20_reg_452_pp0_iter3_reg; + +assign zext_ln55_fu_178_p1 = input_indices_23_dout; + +endmodule //td_fused_top_tdf2_readFilters24 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_readInputs25 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + i_17, + j_17, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_we0, + ifmap_vec_d0, + ifmap_vec_address1, + ifmap_vec_ce1, + ifmap_vec_we1, + ifmap_vec_d1 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_pp0_stage0 = 4'd2; +parameter ap_ST_fsm_pp0_stage1 = 4'd4; +parameter ap_ST_fsm_state8 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] i_17; +input [15:0] j_17; +output [7:0] ifmap_vec_address0; +output ifmap_vec_ce0; +output ifmap_vec_we0; +output [15:0] ifmap_vec_d0; +output [7:0] ifmap_vec_address1; +output ifmap_vec_ce1; +output ifmap_vec_we1; +output [15:0] ifmap_vec_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg[7:0] ifmap_vec_address0; +reg ifmap_vec_ce0; +reg ifmap_vec_we0; +reg[15:0] ifmap_vec_d0; +reg[7:0] ifmap_vec_address1; +reg ifmap_vec_ce1; +reg ifmap_vec_we1; +reg[15:0] ifmap_vec_d1; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [5:0] indvar_flatten47_reg_194; +reg [1:0] ii_reg_206; +reg [4:0] indvar_flatten_reg_218; +reg [1:0] jj_reg_229; +reg [4:0] kk_0_i_reg_241; +wire [17:0] p_cast_i_fu_270_p1; +reg [17:0] p_cast_i_reg_931; +wire [13:0] trunc_ln22_fu_274_p1; +reg [13:0] trunc_ln22_reg_937; +wire [17:0] sext_ln22_fu_284_p1; +reg [17:0] sext_ln22_reg_943; +wire [6:0] p_cast_fu_288_p2; +reg [6:0] p_cast_reg_949; +wire [0:0] or_ln23_21_fu_308_p2; +reg [0:0] or_ln23_21_reg_955; +wire [13:0] p_mid137_fu_314_p2; +reg [13:0] p_mid137_reg_960; +wire [6:0] p_cast5_i_fu_333_p2; +reg [6:0] p_cast5_i_reg_965; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state4_pp0_stage0_iter1; +wire ap_block_state6_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [0:0] is_padding_fu_373_p2; +reg [0:0] is_padding_reg_971; +wire [0:0] icmp_ln19_fu_379_p2; +reg [0:0] icmp_ln19_reg_978; +reg [0:0] icmp_ln19_reg_978_pp0_iter1_reg; +reg [0:0] icmp_ln19_reg_978_pp0_iter2_reg; +wire [1:0] add_ln19_fu_385_p2; +reg [1:0] add_ln19_reg_982; +wire [0:0] icmp_ln20_fu_391_p2; +reg [0:0] icmp_ln20_reg_987; +wire [1:0] select_ln19_fu_397_p3; +reg [1:0] select_ln19_reg_999; +wire [6:0] p_cast5_i_mid1_fu_418_p2; +reg [6:0] p_cast5_i_mid1_reg_1004; +wire [0:0] or_ln23_23_fu_437_p2; +reg [0:0] or_ln23_23_reg_1010; +wire [1:0] add_ln20_fu_442_p2; +reg [1:0] add_ln20_reg_1017; +wire [0:0] or_ln23_25_fu_477_p2; +reg [0:0] or_ln23_25_reg_1023; +wire [4:0] add_ln20_5_fu_483_p2; +reg [4:0] add_ln20_5_reg_1030; +wire [5:0] add_ln19_5_fu_489_p2; +reg [5:0] add_ln19_5_reg_1035; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state5_pp0_stage1_iter1; +wire ap_block_state7_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +wire [1:0] select_ln19_25_fu_527_p3; +reg [1:0] select_ln19_25_reg_1040; +wire [4:0] select_ln20_fu_591_p3; +reg [4:0] select_ln20_reg_1047; +wire [1:0] select_ln20_21_fu_599_p3; +reg [1:0] select_ln20_21_reg_1053; +wire [0:0] select_ln20_22_fu_608_p3; +reg [0:0] select_ln20_22_reg_1059; +reg [0:0] select_ln20_22_reg_1059_pp0_iter1_reg; +wire [3:0] empty_111_fu_704_p1; +reg [3:0] empty_111_reg_1067; +reg [3:0] empty_111_reg_1067_pp0_iter1_reg; +wire [4:0] select_ln20_25_fu_731_p3; +reg [4:0] select_ln20_25_reg_1079; +wire [4:0] add_ln25_fu_737_p2; +reg [4:0] add_ln25_reg_1084; +reg ap_enable_reg_pp0_iter1; +wire [5:0] add_ln33_fu_769_p2; +reg [5:0] add_ln33_reg_1089; +wire [7:0] add_ln33_5_fu_790_p2; +reg [7:0] add_ln33_5_reg_1096; +wire [15:0] select_ln33_23_fu_869_p3; +reg [15:0] select_ln33_23_reg_1101; +wire [15:0] select_ln33_24_fu_890_p3; +reg [15:0] select_ln33_24_reg_1106; +reg ap_block_state1; +wire ap_block_pp0_stage1_subdone; +reg ap_condition_pp0_exit_iter0_state3; +reg ap_enable_reg_pp0_iter2; +reg [5:0] ap_phi_mux_indvar_flatten47_phi_fu_198_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_210_p4; +reg [4:0] ap_phi_mux_indvar_flatten_phi_fu_222_p4; +reg [1:0] ap_phi_mux_jj_phi_fu_233_p4; +reg [4:0] ap_phi_mux_kk_0_i_phi_fu_245_p4; +wire ap_block_pp0_stage1; +wire [63:0] sext_ln32_fu_726_p1; +wire [63:0] zext_ln33_21_fu_796_p1; +wire [63:0] sext_ln33_fu_828_p1; +wire [63:0] sext_ln33_9_fu_909_p1; +wire [63:0] sext_ln33_10_fu_926_p1; +wire [15:0] select_ln33_fu_808_p3; +wire [15:0] select_ln33_22_fu_847_p3; +wire [16:0] zext_ln19_fu_256_p1; +wire [16:0] empty_106_fu_264_p2; +wire [16:0] j_cast_i_fu_252_p1; +wire [16:0] add_ln22_fu_278_p2; +wire [6:0] empty_fu_260_p1; +wire [0:0] tmp_fu_294_p3; +wire [0:0] icmp_ln24_fu_302_p2; +wire [17:0] ii_cast_i_fu_320_p1; +wire [6:0] ii_cast_fu_324_p1; +wire [17:0] empty_107_fu_328_p2; +wire [17:0] zext_ln20_fu_344_p1; +wire [17:0] add_ln22_5_fu_348_p2; +wire [0:0] tmp_37_fu_353_p3; +wire [0:0] icmp_ln24_5_fu_361_p2; +wire [0:0] or_ln23_fu_367_p2; +wire [0:0] empty_108_fu_338_p2; +wire [17:0] ii_cast_i_mid1_fu_405_p1; +wire [6:0] ii_cast_mid1_fu_409_p1; +wire [17:0] p_mid111_fu_413_p2; +wire [0:0] p_mid113_fu_423_p2; +wire [17:0] zext_ln20_5_fu_448_p1; +wire [17:0] add_ln22_6_fu_452_p2; +wire [0:0] tmp_38_fu_457_p3; +wire [0:0] icmp_ln24_6_fu_465_p2; +wire [0:0] or_ln23_24_fu_471_p2; +wire [0:0] select_ln19_27_fu_429_p3; +wire [2:0] zext_ln22_fu_495_p1; +wire [2:0] tmp2_fu_505_p2; +wire [13:0] tmp2_cast_fu_511_p1; +wire [13:0] empty_109_fu_515_p2; +wire [6:0] row_coord_int_mid131_fu_543_p3; +wire [6:0] row_coord_int_fu_499_p3; +wire [13:0] col_coord_int_mid139_fu_549_p3; +wire [13:0] col_coord_int_fu_520_p3; +wire [0:0] icmp_ln25_fu_574_p2; +wire [0:0] xor_ln19_fu_569_p2; +wire [0:0] and_ln19_fu_580_p2; +wire [0:0] or_ln20_fu_586_p2; +wire [0:0] select_ln19_28_fu_538_p3; +wire [6:0] select_ln19_26_fu_533_p3; +wire [2:0] zext_ln22_5_fu_605_p1; +wire [2:0] tmp2_mid1_fu_622_p2; +wire [13:0] tmp2_cast_mid1_fu_628_p1; +wire [13:0] p_mid1_fu_632_p2; +wire [6:0] row_coord_int_mid1_fu_615_p3; +wire [6:0] select_ln19_29_fu_555_p3; +wire [6:0] select_ln20_23_fu_644_p3; +wire [13:0] tmp_7_fu_652_p3; +wire [10:0] tmp_8_fu_664_p3; +wire [14:0] zext_ln32_fu_660_p1; +wire [14:0] zext_ln32_22_fu_672_p1; +wire [14:0] sub_ln32_fu_676_p2; +wire [13:0] col_coord_int_mid1_fu_637_p3; +wire [13:0] select_ln19_30_fu_562_p3; +wire [13:0] select_ln20_24_fu_686_p3; +wire [15:0] sext_ln20_fu_682_p1; +wire [15:0] zext_ln32_23_fu_694_p1; +wire [15:0] add_ln32_fu_698_p2; +wire [1:0] lshr_ln_fu_708_p4; +wire [17:0] tmp_39_fu_718_p3; +wire [3:0] tmp_s_fu_745_p3; +wire [4:0] zext_ln33_18_fu_752_p1; +wire [4:0] zext_ln33_fu_742_p1; +wire [4:0] sub_ln33_fu_756_p2; +wire [5:0] sub_ln33_cast_fu_762_p1; +wire [5:0] zext_ln33_19_fu_766_p1; +wire [3:0] trunc_ln33_fu_775_p1; +wire [7:0] tmp_113_cast_fu_779_p3; +wire [7:0] zext_ln33_20_fu_787_p1; +wire [15:0] trunc_ln32_fu_800_p1; +wire [15:0] bitcast_ln32_fu_804_p1; +wire [3:0] or_ln25_fu_816_p2; +wire [9:0] tmp_40_fu_821_p3; +wire [15:0] tmp_66_i_fu_833_p4; +wire [15:0] bitcast_ln32_22_fu_843_p1; +wire [15:0] tmp_67_i_fu_855_p4; +wire [15:0] bitcast_ln32_23_fu_865_p1; +wire [15:0] tmp_68_i_fu_876_p4; +wire [15:0] bitcast_ln32_24_fu_886_p1; +wire [3:0] or_ln25_15_fu_897_p2; +wire [9:0] tmp_41_fu_902_p3; +wire [3:0] or_ln25_16_fu_914_p2; +wire [9:0] tmp_42_fu_919_p3; +wire ap_CS_fsm_state8; +reg [3:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state3) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state3)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state3); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ii_reg_206 <= select_ln19_25_reg_1040; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_206 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + indvar_flatten47_reg_194 <= add_ln19_5_reg_1035; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten47_reg_194 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + indvar_flatten_reg_218 <= select_ln20_25_reg_1079; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_218 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_229 <= select_ln20_21_reg_1053; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_229 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_i_reg_241 <= add_ln25_reg_1084; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_0_i_reg_241 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln19_5_reg_1035 <= add_ln19_5_fu_489_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_379_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln19_reg_982 <= add_ln19_fu_385_p2; + add_ln20_5_reg_1030 <= add_ln20_5_fu_483_p2; + add_ln20_reg_1017 <= add_ln20_fu_442_p2; + icmp_ln20_reg_987 <= icmp_ln20_fu_391_p2; + or_ln23_23_reg_1010 <= or_ln23_23_fu_437_p2; + or_ln23_25_reg_1023 <= or_ln23_25_fu_477_p2; + p_cast5_i_mid1_reg_1004 <= p_cast5_i_mid1_fu_418_p2; + select_ln19_reg_999 <= select_ln19_fu_397_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + add_ln25_reg_1084 <= add_ln25_fu_737_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + add_ln33_5_reg_1096 <= add_ln33_5_fu_790_p2; + add_ln33_reg_1089 <= add_ln33_fu_769_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + empty_111_reg_1067 <= empty_111_fu_704_p1; + select_ln20_22_reg_1059 <= select_ln20_22_fu_608_p3; + select_ln20_reg_1047 <= select_ln20_fu_591_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + empty_111_reg_1067_pp0_iter1_reg <= empty_111_reg_1067; + select_ln20_22_reg_1059_pp0_iter1_reg <= select_ln20_22_reg_1059; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln19_reg_978 <= icmp_ln19_fu_379_p2; + icmp_ln19_reg_978_pp0_iter1_reg <= icmp_ln19_reg_978; + icmp_ln19_reg_978_pp0_iter2_reg <= icmp_ln19_reg_978_pp0_iter1_reg; + is_padding_reg_971 <= is_padding_fu_373_p2; + p_cast5_i_reg_965 <= p_cast5_i_fu_333_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + or_ln23_21_reg_955 <= or_ln23_21_fu_308_p2; + p_cast_i_reg_931 <= p_cast_i_fu_270_p1; + p_cast_reg_949 <= p_cast_fu_288_p2; + p_mid137_reg_960 <= p_mid137_fu_314_p2; + sext_ln22_reg_943 <= sext_ln22_fu_284_p1; + trunc_ln22_reg_937 <= trunc_ln22_fu_274_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln19_25_reg_1040 <= select_ln19_25_fu_527_p3; + select_ln20_21_reg_1053 <= select_ln20_21_fu_599_p3; + select_ln20_25_reg_1079 <= select_ln20_25_fu_731_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln33_23_reg_1101 <= select_ln33_23_fu_869_p3; + select_ln33_24_reg_1106 <= select_ln33_24_fu_890_p3; + end +end + +always @ (*) begin + if ((icmp_ln19_reg_978 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_210_p4 = select_ln19_25_reg_1040; + end else begin + ap_phi_mux_ii_phi_fu_210_p4 = ii_reg_206; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_indvar_flatten47_phi_fu_198_p4 = add_ln19_5_reg_1035; + end else begin + ap_phi_mux_indvar_flatten47_phi_fu_198_p4 = indvar_flatten47_reg_194; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_indvar_flatten_phi_fu_222_p4 = select_ln20_25_reg_1079; + end else begin + ap_phi_mux_indvar_flatten_phi_fu_222_p4 = indvar_flatten_reg_218; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_233_p4 = select_ln20_21_reg_1053; + end else begin + ap_phi_mux_jj_phi_fu_233_p4 = jj_reg_229; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_978_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_i_phi_fu_245_p4 = add_ln25_reg_1084; + end else begin + ap_phi_mux_kk_0_i_phi_fu_245_p4 = kk_0_i_reg_241; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_address0 = sext_ln33_10_fu_926_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_address0 = sext_ln33_fu_828_p1; + end else begin + ifmap_vec_address0 = 'bx; + end + end else begin + ifmap_vec_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_address1 = sext_ln33_9_fu_909_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_address1 = zext_ln33_21_fu_796_p1; + end else begin + ifmap_vec_address1 = 'bx; + end + end else begin + ifmap_vec_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + ifmap_vec_ce1 = 1'b1; + end else begin + ifmap_vec_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_d0 = select_ln33_24_reg_1106; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_d0 = select_ln33_22_fu_847_p3; + end else begin + ifmap_vec_d0 = 'bx; + end + end else begin + ifmap_vec_d0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_d1 = select_ln33_23_reg_1101; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_d1 = select_ln33_fu_808_p3; + end else begin + ifmap_vec_d1 = 'bx; + end + end else begin + ifmap_vec_d1 = 'bx; + end +end + +always @ (*) begin + if ((((icmp_ln19_reg_978_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((icmp_ln19_reg_978_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + ifmap_vec_we0 = 1'b1; + end else begin + ifmap_vec_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((icmp_ln19_reg_978_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((icmp_ln19_reg_978_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + ifmap_vec_we1 = 1'b1; + end else begin + ifmap_vec_we1 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((icmp_ln19_reg_978 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln19_reg_978 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state8; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln19_5_fu_489_p2 = (indvar_flatten47_reg_194 + 6'd1); + +assign add_ln19_fu_385_p2 = (ap_phi_mux_ii_phi_fu_210_p4 + 2'd1); + +assign add_ln20_5_fu_483_p2 = (ap_phi_mux_indvar_flatten_phi_fu_222_p4 + 5'd1); + +assign add_ln20_fu_442_p2 = (select_ln19_fu_397_p3 + 2'd1); + +assign add_ln22_5_fu_348_p2 = ((sext_ln22_reg_943) + (zext_ln20_fu_344_p1)); + +assign add_ln22_6_fu_452_p2 = ((sext_ln22_reg_943) + (zext_ln20_5_fu_448_p1)); + +assign add_ln22_fu_278_p2 = ((j_cast_i_fu_252_p1) + (17'd131071)); + +assign add_ln25_fu_737_p2 = (select_ln20_reg_1047 + 5'd4); + +assign add_ln32_fu_698_p2 = ((sext_ln20_fu_682_p1) + (zext_ln32_23_fu_694_p1)); + +assign add_ln33_5_fu_790_p2 = (tmp_113_cast_fu_779_p3 + zext_ln33_20_fu_787_p1); + +assign add_ln33_fu_769_p2 = ((sub_ln33_cast_fu_762_p1) + (zext_ln33_19_fu_766_p1)); + +assign and_ln19_fu_580_p2 = (xor_ln19_fu_569_p2 & icmp_ln25_fu_574_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd3]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln32_22_fu_843_p1 = tmp_66_i_fu_833_p4; + +assign bitcast_ln32_23_fu_865_p1 = tmp_67_i_fu_855_p4; + +assign bitcast_ln32_24_fu_886_p1 = tmp_68_i_fu_876_p4; + +assign bitcast_ln32_fu_804_p1 = trunc_ln32_fu_800_p1; + +assign col_coord_int_fu_520_p3 = ((is_padding_reg_971[0:0] == 1'b1) ? 14'd0 : empty_109_fu_515_p2); + +assign col_coord_int_mid139_fu_549_p3 = ((or_ln23_23_reg_1010[0:0] == 1'b1) ? 14'd0 : p_mid137_reg_960); + +assign col_coord_int_mid1_fu_637_p3 = ((or_ln23_25_reg_1023[0:0] == 1'b1) ? 14'd0 : p_mid1_fu_632_p2); + +assign empty_106_fu_264_p2 = ((zext_ln19_fu_256_p1) + (17'd131071)); + +assign empty_107_fu_328_p2 = ((p_cast_i_reg_931) + (ii_cast_i_fu_320_p1)); + +assign empty_108_fu_338_p2 = ((empty_107_fu_328_p2 > 18'd111) ? 1'b1 : 1'b0); + +assign empty_109_fu_515_p2 = ((tmp2_cast_fu_511_p1) + (trunc_ln22_reg_937)); + +assign empty_111_fu_704_p1 = select_ln20_fu_591_p3[3:0]; + +assign empty_fu_260_p1 = i_17[6:0]; + +assign icmp_ln19_fu_379_p2 = ((ap_phi_mux_indvar_flatten47_phi_fu_198_p4 == 6'd36) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_391_p2 = ((ap_phi_mux_indvar_flatten_phi_fu_222_p4 == 5'd12) ? 1'b1 : 1'b0); + +assign icmp_ln24_5_fu_361_p2 = (((add_ln22_5_fu_348_p2) > (18'd111)) ? 1'b1 : 1'b0); + +assign icmp_ln24_6_fu_465_p2 = (((add_ln22_6_fu_452_p2) > (18'd111)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_302_p2 = (((add_ln22_fu_278_p2) > (17'd111)) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_574_p2 = ((ap_phi_mux_kk_0_i_phi_fu_245_p4 == 5'd16) ? 1'b1 : 1'b0); + +assign ii_cast_fu_324_p1 = ap_phi_mux_ii_phi_fu_210_p4; + +assign ii_cast_i_fu_320_p1 = ap_phi_mux_ii_phi_fu_210_p4; + +assign ii_cast_i_mid1_fu_405_p1 = add_ln19_fu_385_p2; + +assign ii_cast_mid1_fu_409_p1 = add_ln19_fu_385_p2; + +assign in_data_address0 = sext_ln32_fu_726_p1; + +assign is_padding_fu_373_p2 = (or_ln23_fu_367_p2 | empty_108_fu_338_p2); + +assign j_cast_i_fu_252_p1 = j_17; + +assign lshr_ln_fu_708_p4 = {{select_ln20_fu_591_p3[3:2]}}; + +assign or_ln20_fu_586_p2 = (icmp_ln20_reg_987 | and_ln19_fu_580_p2); + +assign or_ln23_21_fu_308_p2 = (tmp_fu_294_p3 | icmp_ln24_fu_302_p2); + +assign or_ln23_23_fu_437_p2 = (p_mid113_fu_423_p2 | or_ln23_21_reg_955); + +assign or_ln23_24_fu_471_p2 = (tmp_38_fu_457_p3 | icmp_ln24_6_fu_465_p2); + +assign or_ln23_25_fu_477_p2 = (select_ln19_27_fu_429_p3 | or_ln23_24_fu_471_p2); + +assign or_ln23_fu_367_p2 = (tmp_37_fu_353_p3 | icmp_ln24_5_fu_361_p2); + +assign or_ln25_15_fu_897_p2 = (empty_111_reg_1067_pp0_iter1_reg | 4'd2); + +assign or_ln25_16_fu_914_p2 = (empty_111_reg_1067_pp0_iter1_reg | 4'd3); + +assign or_ln25_fu_816_p2 = (empty_111_reg_1067_pp0_iter1_reg | 4'd1); + +assign p_cast5_i_fu_333_p2 = (p_cast_reg_949 + ii_cast_fu_324_p1); + +assign p_cast5_i_mid1_fu_418_p2 = (p_cast_reg_949 + ii_cast_mid1_fu_409_p1); + +assign p_cast_fu_288_p2 = ((empty_fu_260_p1) + (7'd127)); + +assign p_cast_i_fu_270_p1 = (empty_106_fu_264_p2); + +assign p_mid111_fu_413_p2 = ((p_cast_i_reg_931) + (ii_cast_i_mid1_fu_405_p1)); + +assign p_mid113_fu_423_p2 = ((p_mid111_fu_413_p2 > 18'd111) ? 1'b1 : 1'b0); + +assign p_mid137_fu_314_p2 = ((trunc_ln22_fu_274_p1) + (14'd16383)); + +assign p_mid1_fu_632_p2 = ((tmp2_cast_mid1_fu_628_p1) + (trunc_ln22_reg_937)); + +assign row_coord_int_fu_499_p3 = ((is_padding_reg_971[0:0] == 1'b1) ? 7'd0 : p_cast5_i_reg_965); + +assign row_coord_int_mid131_fu_543_p3 = ((or_ln23_23_reg_1010[0:0] == 1'b1) ? 7'd0 : p_cast5_i_mid1_reg_1004); + +assign row_coord_int_mid1_fu_615_p3 = ((or_ln23_25_reg_1023[0:0] == 1'b1) ? 7'd0 : select_ln19_26_fu_533_p3); + +assign select_ln19_25_fu_527_p3 = ((icmp_ln20_reg_987[0:0] == 1'b1) ? add_ln19_reg_982 : ii_reg_206); + +assign select_ln19_26_fu_533_p3 = ((icmp_ln20_reg_987[0:0] == 1'b1) ? p_cast5_i_mid1_reg_1004 : p_cast5_i_reg_965); + +assign select_ln19_27_fu_429_p3 = ((icmp_ln20_fu_391_p2[0:0] == 1'b1) ? p_mid113_fu_423_p2 : empty_108_fu_338_p2); + +assign select_ln19_28_fu_538_p3 = ((icmp_ln20_reg_987[0:0] == 1'b1) ? or_ln23_23_reg_1010 : is_padding_reg_971); + +assign select_ln19_29_fu_555_p3 = ((icmp_ln20_reg_987[0:0] == 1'b1) ? row_coord_int_mid131_fu_543_p3 : row_coord_int_fu_499_p3); + +assign select_ln19_30_fu_562_p3 = ((icmp_ln20_reg_987[0:0] == 1'b1) ? col_coord_int_mid139_fu_549_p3 : col_coord_int_fu_520_p3); + +assign select_ln19_fu_397_p3 = ((icmp_ln20_fu_391_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_233_p4); + +assign select_ln20_21_fu_599_p3 = ((and_ln19_fu_580_p2[0:0] == 1'b1) ? add_ln20_reg_1017 : select_ln19_reg_999); + +assign select_ln20_22_fu_608_p3 = ((and_ln19_fu_580_p2[0:0] == 1'b1) ? or_ln23_25_reg_1023 : select_ln19_28_fu_538_p3); + +assign select_ln20_23_fu_644_p3 = ((and_ln19_fu_580_p2[0:0] == 1'b1) ? row_coord_int_mid1_fu_615_p3 : select_ln19_29_fu_555_p3); + +assign select_ln20_24_fu_686_p3 = ((and_ln19_fu_580_p2[0:0] == 1'b1) ? col_coord_int_mid1_fu_637_p3 : select_ln19_30_fu_562_p3); + +assign select_ln20_25_fu_731_p3 = ((icmp_ln20_reg_987[0:0] == 1'b1) ? 5'd1 : add_ln20_5_reg_1030); + +assign select_ln20_fu_591_p3 = ((or_ln20_fu_586_p2[0:0] == 1'b1) ? 5'd0 : ap_phi_mux_kk_0_i_phi_fu_245_p4); + +assign select_ln33_22_fu_847_p3 = ((select_ln20_22_reg_1059_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_22_fu_843_p1); + +assign select_ln33_23_fu_869_p3 = ((select_ln20_22_reg_1059_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_23_fu_865_p1); + +assign select_ln33_24_fu_890_p3 = ((select_ln20_22_reg_1059_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_24_fu_886_p1); + +assign select_ln33_fu_808_p3 = ((select_ln20_22_reg_1059_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_fu_804_p1); + +assign sext_ln20_fu_682_p1 = (sub_ln32_fu_676_p2); + +assign sext_ln22_fu_284_p1 = add_ln22_fu_278_p2; + +assign sext_ln32_fu_726_p1 = (tmp_39_fu_718_p3); + +assign sext_ln33_10_fu_926_p1 = (tmp_42_fu_919_p3); + +assign sext_ln33_9_fu_909_p1 = (tmp_41_fu_902_p3); + +assign sext_ln33_fu_828_p1 = (tmp_40_fu_821_p3); + +assign sub_ln32_fu_676_p2 = (zext_ln32_fu_660_p1 - zext_ln32_22_fu_672_p1); + +assign sub_ln33_cast_fu_762_p1 = (sub_ln33_fu_756_p2); + +assign sub_ln33_fu_756_p2 = (zext_ln33_18_fu_752_p1 - zext_ln33_fu_742_p1); + +assign tmp2_cast_fu_511_p1 = (tmp2_fu_505_p2); + +assign tmp2_cast_mid1_fu_628_p1 = (tmp2_mid1_fu_622_p2); + +assign tmp2_fu_505_p2 = ((zext_ln22_fu_495_p1) + (3'd7)); + +assign tmp2_mid1_fu_622_p2 = ((zext_ln22_5_fu_605_p1) + (3'd7)); + +assign tmp_113_cast_fu_779_p3 = {{trunc_ln33_fu_775_p1}, {4'd0}}; + +assign tmp_37_fu_353_p3 = add_ln22_5_fu_348_p2[32'd17]; + +assign tmp_38_fu_457_p3 = add_ln22_6_fu_452_p2[32'd17]; + +assign tmp_39_fu_718_p3 = {{add_ln32_fu_698_p2}, {lshr_ln_fu_708_p4}}; + +assign tmp_40_fu_821_p3 = {{add_ln33_reg_1089}, {or_ln25_fu_816_p2}}; + +assign tmp_41_fu_902_p3 = {{add_ln33_reg_1089}, {or_ln25_15_fu_897_p2}}; + +assign tmp_42_fu_919_p3 = {{add_ln33_reg_1089}, {or_ln25_16_fu_914_p2}}; + +assign tmp_66_i_fu_833_p4 = {{in_data_q0[31:16]}}; + +assign tmp_67_i_fu_855_p4 = {{in_data_q0[47:32]}}; + +assign tmp_68_i_fu_876_p4 = {{in_data_q0[63:48]}}; + +assign tmp_7_fu_652_p3 = {{select_ln20_23_fu_644_p3}, {7'd0}}; + +assign tmp_8_fu_664_p3 = {{select_ln20_23_fu_644_p3}, {4'd0}}; + +assign tmp_fu_294_p3 = add_ln22_fu_278_p2[32'd16]; + +assign tmp_s_fu_745_p3 = {{select_ln19_25_reg_1040}, {2'd0}}; + +assign trunc_ln22_fu_274_p1 = j_17[13:0]; + +assign trunc_ln32_fu_800_p1 = in_data_q0[15:0]; + +assign trunc_ln33_fu_775_p1 = add_ln33_fu_769_p2[3:0]; + +assign xor_ln19_fu_569_p2 = (icmp_ln20_reg_987 ^ 1'd1); + +assign zext_ln19_fu_256_p1 = i_17; + +assign zext_ln20_5_fu_448_p1 = add_ln20_fu_442_p2; + +assign zext_ln20_fu_344_p1 = ap_phi_mux_jj_phi_fu_233_p4; + +assign zext_ln22_5_fu_605_p1 = add_ln20_reg_1017; + +assign zext_ln22_fu_495_p1 = jj_reg_229; + +assign zext_ln32_22_fu_672_p1 = tmp_8_fu_664_p3; + +assign zext_ln32_23_fu_694_p1 = select_ln20_24_fu_686_p3; + +assign zext_ln32_fu_660_p1 = tmp_7_fu_652_p3; + +assign zext_ln33_18_fu_752_p1 = tmp_s_fu_745_p3; + +assign zext_ln33_19_fu_766_p1 = select_ln20_21_reg_1053; + +assign zext_ln33_20_fu_787_p1 = select_ln20_reg_1047; + +assign zext_ln33_21_fu_796_p1 = add_ln33_5_reg_1096; + +assign zext_ln33_fu_742_p1 = select_ln19_25_reg_1040; + +endmodule //td_fused_top_tdf2_readInputs25 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf2_writeOutputs_unaligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_idle, + ap_ready, + i, + j, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1, + max_vals_4_0 +); + +parameter ap_ST_fsm_state1 = 2'd1; +parameter ap_ST_fsm_state2 = 2'd2; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +input [5:0] i; +input [11:0] j; +output [14:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; +input [15:0] max_vals_4_0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg out_data_ce1; +reg out_data_we1; + + reg [1:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] outputCount_7; +reg [15:0] outputChanIdx_7; +reg [15:0] outputRow_9_0; +reg [15:0] outputRow_9_1; +reg [15:0] outputRow_9_2; +reg [15:0] outputRow_9_3; +wire [15:0] add_ln87_fu_175_p2; +wire [0:0] icmp_ln88_fu_181_p2; +reg [0:0] icmp_ln88_reg_295; +reg [15:0] ap_phi_mux_empty_phi_fu_92_p4; +reg [15:0] empty_reg_89; +wire ap_CS_fsm_state2; +wire [63:0] zext_ln94_14_fu_209_p1; +wire [15:0] select_ln97_fu_267_p3; +wire [1:0] trunc_ln86_fu_147_p1; +reg [15:0] ap_sig_allocacmp_outputRow_9_0_load; +reg [15:0] ap_sig_allocacmp_outputRow_9_1_load; +reg [15:0] ap_sig_allocacmp_outputRow_9_2_load; +reg [15:0] ap_sig_allocacmp_outputRow_9_3_load; +wire [8:0] tmp_s_fu_107_p3; +wire [11:0] tmp_fu_99_p3; +wire [11:0] zext_ln94_fu_115_p1; +wire [11:0] sub_ln94_fu_119_p2; +wire [11:0] add_ln94_fu_125_p2; +wire [4:0] trunc_ln94_fu_195_p1; +wire [14:0] tmp_110_cast_fu_131_p3; +wire [14:0] zext_ln94_13_fu_199_p1; +wire [14:0] add_ln94_6_fu_203_p2; +wire [15:0] bitcast_ln94_18_fu_238_p1; +wire [15:0] bitcast_ln94_17_fu_230_p1; +wire [15:0] bitcast_ln94_16_fu_222_p1; +wire [15:0] bitcast_ln94_fu_214_p1; +wire [15:0] add_ln96_fu_255_p2; +wire [0:0] icmp_ln97_fu_261_p2; +reg [1:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 2'd1; +#0 outputCount_7 = 16'd0; +#0 outputChanIdx_7 = 16'd0; +#0 outputRow_9_0 = 16'd0; +#0 outputRow_9_1 = 16'd0; +#0 outputRow_9_2 = 16'd0; +#0 outputRow_9_3 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_reg_295 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + empty_reg_89 <= 16'd0; + end else if (((ap_start == 1'b1) & (icmp_ln88_fu_181_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + empty_reg_89 <= add_ln87_fu_175_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + icmp_ln88_reg_295 <= icmp_ln88_fu_181_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_start == 1'b1) & (icmp_ln88_fu_181_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + outputChanIdx_7 <= select_ln97_fu_267_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + outputCount_7 <= ap_phi_mux_empty_phi_fu_92_p4; + end +end + +always @ (posedge ap_clk) begin + if (((ap_start == 1'b1) & (trunc_ln86_fu_147_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_9_0 <= max_vals_4_0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_start == 1'b1) & (trunc_ln86_fu_147_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_9_1 <= max_vals_4_0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_start == 1'b1) & (trunc_ln86_fu_147_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_9_2 <= max_vals_4_0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_start == 1'b1) & (trunc_ln86_fu_147_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_9_3 <= max_vals_4_0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_reg_295 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_phi_mux_empty_phi_fu_92_p4 = 16'd0; + end else begin + ap_phi_mux_empty_phi_fu_92_p4 = empty_reg_89; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_147_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_sig_allocacmp_outputRow_9_0_load = max_vals_4_0; + end else begin + ap_sig_allocacmp_outputRow_9_0_load = outputRow_9_0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_147_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state1))) begin + ap_sig_allocacmp_outputRow_9_1_load = max_vals_4_0; + end else begin + ap_sig_allocacmp_outputRow_9_1_load = outputRow_9_1; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_147_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state1))) begin + ap_sig_allocacmp_outputRow_9_2_load = max_vals_4_0; + end else begin + ap_sig_allocacmp_outputRow_9_2_load = outputRow_9_2; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_147_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state1))) begin + ap_sig_allocacmp_outputRow_9_3_load = max_vals_4_0; + end else begin + ap_sig_allocacmp_outputRow_9_3_load = outputRow_9_3; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1)))) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_start == 1'b1) & (icmp_ln88_fu_181_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln87_fu_175_p2 = (outputCount_7 + 16'd1); + +assign add_ln94_6_fu_203_p2 = (tmp_110_cast_fu_131_p3 + zext_ln94_13_fu_199_p1); + +assign add_ln94_fu_125_p2 = (sub_ln94_fu_119_p2 + j); + +assign add_ln96_fu_255_p2 = (outputChanIdx_7 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign bitcast_ln94_16_fu_222_p1 = ap_sig_allocacmp_outputRow_9_1_load; + +assign bitcast_ln94_17_fu_230_p1 = ap_sig_allocacmp_outputRow_9_2_load; + +assign bitcast_ln94_18_fu_238_p1 = ap_sig_allocacmp_outputRow_9_3_load; + +assign bitcast_ln94_fu_214_p1 = ap_sig_allocacmp_outputRow_9_0_load; + +assign icmp_ln88_fu_181_p2 = ((add_ln87_fu_175_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign icmp_ln97_fu_261_p2 = ((add_ln96_fu_255_p2 == 16'd8) ? 1'b1 : 1'b0); + +assign out_data_address1 = zext_ln94_14_fu_209_p1; + +assign out_data_d1 = {{{{bitcast_ln94_18_fu_238_p1}, {bitcast_ln94_17_fu_230_p1}}, {bitcast_ln94_16_fu_222_p1}}, {bitcast_ln94_fu_214_p1}}; + +assign select_ln97_fu_267_p3 = ((icmp_ln97_fu_261_p2[0:0] == 1'b1) ? 16'd0 : add_ln96_fu_255_p2); + +assign sub_ln94_fu_119_p2 = (tmp_fu_99_p3 - zext_ln94_fu_115_p1); + +assign tmp_110_cast_fu_131_p3 = {{add_ln94_fu_125_p2}, {3'd0}}; + +assign tmp_fu_99_p3 = {{i}, {6'd0}}; + +assign tmp_s_fu_107_p3 = {{i}, {3'd0}}; + +assign trunc_ln86_fu_147_p1 = outputCount_7[1:0]; + +assign trunc_ln94_fu_195_p1 = outputChanIdx_7[4:0]; + +assign zext_ln94_13_fu_199_p1 = trunc_ln94_fu_195_p1; + +assign zext_ln94_14_fu_209_p1 = add_ln94_6_fu_203_p2; + +assign zext_ln94_fu_115_p1 = tmp_s_fu_107_p3; + +endmodule //td_fused_top_tdf2_writeOutputs_unaligned +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_112 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [14:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [14:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [13:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [13:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [8:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [8:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [3:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [3:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [14:0] dataflow_in_loop_TOP_LOOP37928_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP37928_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP37928_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP37928_U0_in_data_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP37928_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP37928_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP37928_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP37928_U0_in_data_we1; +wire [8:0] dataflow_in_loop_TOP_LOOP37928_U0_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP37928_U0_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP37928_U0_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP37928_U0_filter_data_we0; +wire [8:0] dataflow_in_loop_TOP_LOOP37928_U0_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP37928_U0_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP37928_U0_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP37928_U0_filter_data_we1; +wire [3:0] dataflow_in_loop_TOP_LOOP37928_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP37928_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP37928_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP37928_U0_adjustments_we0; +wire [3:0] dataflow_in_loop_TOP_LOOP37928_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP37928_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP37928_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP37928_U0_adjustments_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP37928_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP37928_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP37928_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP37928_U0_out_data_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP37928_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP37928_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP37928_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP37928_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP37928_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP37928_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP37928_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP37928_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP37928_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP37928_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP37928_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP37928_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP37928_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [15:0] loop_dataflow_input_count; +reg [15:0] loop_dataflow_output_count; +wire [15:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP37928_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP37928_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 16'd0; +#0 loop_dataflow_output_count = 16'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP37928 dataflow_in_loop_TOP_LOOP37928_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP37928_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP37928_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP37928_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP37928_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP37928_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP37928_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP37928_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP37928_U0_in_data_we1), + .filter_data_address0(dataflow_in_loop_TOP_LOOP37928_U0_filter_data_address0), + .filter_data_ce0(dataflow_in_loop_TOP_LOOP37928_U0_filter_data_ce0), + .filter_data_d0(dataflow_in_loop_TOP_LOOP37928_U0_filter_data_d0), + .filter_data_q0(filter_data_q0), + .filter_data_we0(dataflow_in_loop_TOP_LOOP37928_U0_filter_data_we0), + .filter_data_address1(dataflow_in_loop_TOP_LOOP37928_U0_filter_data_address1), + .filter_data_ce1(dataflow_in_loop_TOP_LOOP37928_U0_filter_data_ce1), + .filter_data_d1(dataflow_in_loop_TOP_LOOP37928_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(dataflow_in_loop_TOP_LOOP37928_U0_filter_data_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP37928_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP37928_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP37928_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP37928_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP37928_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP37928_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP37928_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP37928_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP37928_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP37928_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP37928_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP37928_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP37928_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP37928_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP37928_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP37928_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP37928_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP37928_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP37928_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP37928_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP37928_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP37928_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP37928_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 16'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37928_U0_ap_ready == 1'b1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 16'd1); + end else if (((dataflow_in_loop_TOP_LOOP37928_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= 16'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 16'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37928_U0_ap_done == 1'b1) & (dataflow_in_loop_TOP_LOOP37928_U0_ap_continue == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 16'd1); + end else if (((dataflow_in_loop_TOP_LOOP37928_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37928_U0_ap_continue == 1'b1))) begin + loop_dataflow_output_count <= 16'd0; + end + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP37928_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP37928_U0_ap_idle == 1'b1) & (loop_dataflow_output_count == 16'd0) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP37928_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP37928_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP37928_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP37928_U0_adjustments_address0; + +assign adjustments_address1 = 4'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP37928_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP37928_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP37928_U0_ap_ready; + +assign bound_minus_1 = (16'd50176 - 16'd1); + +assign dataflow_in_loop_TOP_LOOP37928_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP37928_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP37928_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP37928_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP37928_U0_start_write = 1'b0; + +assign filter_data_address0 = dataflow_in_loop_TOP_LOOP37928_U0_filter_data_address0; + +assign filter_data_address1 = 9'd0; + +assign filter_data_ce0 = dataflow_in_loop_TOP_LOOP37928_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP37928_U0_in_data_address0; + +assign in_data_address1 = 15'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP37928_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP37928_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 14'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP37928_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP37928_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP37928_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP37928_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP37928_U0_out_data_write; + +endmodule //td_fused_top_tdf3_112 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 8'd1; +parameter ap_ST_fsm_pp0_stage0 = 8'd2; +parameter ap_ST_fsm_pp0_stage1 = 8'd4; +parameter ap_ST_fsm_pp0_stage2 = 8'd8; +parameter ap_ST_fsm_pp0_stage3 = 8'd16; +parameter ap_ST_fsm_state11 = 8'd32; +parameter ap_ST_fsm_state12 = 8'd64; +parameter ap_ST_fsm_state13 = 8'd128; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [4:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [4:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[4:0] accum_in_0_address0; +reg accum_in_0_ce0; +reg[4:0] accum_in_0_address1; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [7:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [5:0] x_reg_168; +reg [15:0] psum_7_08_reg_180; +reg [15:0] psum_6_07_reg_192; +reg [15:0] psum_5_06_reg_204; +reg [15:0] psum_4_05_reg_216; +reg [15:0] psum_3_04_reg_228; +reg [15:0] psum_2_03_reg_240; +reg [15:0] psum_1_02_reg_252; +reg [15:0] psum_0_01_reg_264; +wire [0:0] tmp_fu_323_p3; +reg [0:0] tmp_reg_494; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state6_pp0_stage0_iter1; +wire ap_block_state10_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] tmp_reg_494_pp0_iter1_reg; +wire [4:0] trunc_ln25_fu_336_p1; +reg [4:0] trunc_ln25_reg_498; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state7_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state8_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +wire [5:0] add_ln25_fu_391_p2; +reg [5:0] add_ln25_reg_558; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state9_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_305_p2; +wire [15:0] grp_fu_311_p2; +reg ap_enable_reg_pp0_iter2; +wire [3:0] add_ln33_fu_434_p2; +wire ap_CS_fsm_state12; +wire [0:0] tmp_36_fu_417_p3; +reg ap_block_state1; +wire ap_block_pp0_stage1_subdone; +reg ap_condition_pp0_exit_iter0_state3; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage0_subdone; +reg [5:0] ap_phi_mux_x_phi_fu_172_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_184_p4; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_196_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_208_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_220_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_232_p4; +wire ap_block_pp0_stage2; +wire [15:0] ap_phi_mux_psum_2_03_phi_fu_244_p4; +wire ap_block_pp0_stage1; +reg [3:0] q_reg_276; +wire ap_CS_fsm_state11; +reg [15:0] ap_phi_mux_phi_ln45_phi_fu_290_p8; +wire [2:0] trunc_ln33_fu_430_p1; +wire [63:0] zext_ln25_fu_331_p1; +wire [63:0] zext_ln29_fu_346_p1; +wire [63:0] zext_ln29_13_fu_356_p1; +wire [63:0] zext_ln29_14_fu_366_p1; +wire [63:0] zext_ln29_15_fu_376_p1; +wire [63:0] zext_ln29_16_fu_386_p1; +wire [63:0] zext_ln29_17_fu_402_p1; +wire [63:0] zext_ln29_18_fu_412_p1; +wire [63:0] zext_ln33_fu_425_p1; +wire [63:0] zext_ln33_3_fu_446_p1; +reg [15:0] grp_fu_305_p0; +reg [15:0] grp_fu_311_p0; +wire [4:0] or_ln29_fu_340_p2; +wire [4:0] or_ln29_13_fu_351_p2; +wire [4:0] or_ln29_14_fu_361_p2; +wire [4:0] or_ln29_15_fu_371_p2; +wire [4:0] or_ln29_16_fu_381_p2; +wire [4:0] or_ln29_17_fu_397_p2; +wire [4:0] or_ln29_18_fu_407_p2; +wire [2:0] or_ln33_fu_440_p2; +wire [0:0] icmp_ln45_fu_451_p2; +wire [0:0] icmp_ln45_5_fu_465_p2; +wire [15:0] select_ln45_fu_457_p3; +wire [0:0] icmp_ln45_6_fu_479_p2; +wire [15:0] select_ln45_5_fu_471_p3; +wire ap_CS_fsm_state13; +reg [7:0] ap_NS_fsm; +wire ap_block_pp0_stage2_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_499; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 8'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U162( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_305_p0), + .din1(accum_in_0_q1), + .dout(grp_fu_305_p2) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U163( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_311_p0), + .din1(accum_in_0_q0), + .dout(grp_fu_311_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state11)) begin + q_reg_276 <= 4'd0; + end else if (((tmp_36_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state12))) begin + q_reg_276 <= add_ln33_fu_434_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + x_reg_168 <= add_ln25_reg_558; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_168 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage3_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln25_reg_558 <= add_ln25_fu_391_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_0_01_reg_264 <= grp_fu_305_p2; + psum_1_02_reg_252 <= grp_fu_311_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_2_03_reg_240 <= grp_fu_305_p2; + psum_3_04_reg_228 <= grp_fu_311_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_4_05_reg_216 <= grp_fu_305_p2; + psum_5_06_reg_204 <= grp_fu_311_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + psum_6_07_reg_192 <= grp_fu_305_p2; + psum_7_08_reg_180 <= grp_fu_311_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + tmp_reg_494 <= ap_phi_mux_x_phi_fu_172_p4[32'd5]; + tmp_reg_494_pp0_iter1_reg <= tmp_reg_494; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_fu_323_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln25_reg_498 <= trunc_ln25_fu_336_p1; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address0 = zext_ln29_18_fu_412_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address0 = zext_ln29_16_fu_386_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address0 = zext_ln29_14_fu_366_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address0 = zext_ln29_fu_346_p1; + end else begin + accum_in_0_address0 = 'bx; + end + end else begin + accum_in_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address1 = zext_ln29_17_fu_402_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address1 = zext_ln29_15_fu_376_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address1 = zext_ln29_13_fu_356_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address1 = zext_ln25_fu_331_p1; + end else begin + accum_in_0_address1 = 'bx; + end + end else begin + accum_in_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_36_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state12))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_36_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state12))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_reg_494 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_36_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state12))) begin + if ((trunc_ln33_fu_430_p1 == 3'd0)) begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = psum_0_01_reg_264; + end else if ((1'b1 == ap_condition_499)) begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = psum_6_07_reg_192; + end else if ((trunc_ln33_fu_430_p1 == 3'd4)) begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = psum_4_05_reg_216; + end else if ((trunc_ln33_fu_430_p1 == 3'd2)) begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = psum_2_03_reg_240; + end else begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln45_phi_fu_290_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_x_phi_fu_172_p4 = add_ln25_reg_558; + end else begin + ap_phi_mux_x_phi_fu_172_p4 = x_reg_168; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_6_07_phi_fu_196_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_4_05_phi_fu_220_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_2_03_phi_fu_244_p4; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_305_p0 = grp_fu_305_p2; + end else begin + grp_fu_305_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_311_p0 = ap_phi_mux_psum_7_08_phi_fu_184_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_311_p0 = ap_phi_mux_psum_5_06_phi_fu_208_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_311_p0 = ap_phi_mux_psum_3_04_phi_fu_232_p4; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_311_p0 = grp_fu_311_p2; + end else begin + grp_fu_311_p0 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state11; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((1'b0 == ap_block_pp0_stage1_subdone) & (tmp_reg_494 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((1'b0 == ap_block_pp0_stage1_subdone) & (tmp_reg_494 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state11; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((1'b0 == ap_block_pp0_stage2_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + if (((tmp_36_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state12))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_state13; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln33_3_fu_446_p1; + +assign accum_out_address1 = zext_ln33_fu_425_p1; + +assign accum_out_d0 = ((icmp_ln45_6_fu_479_p2[0:0] == 1'b1) ? psum_5_06_reg_204 : select_ln45_5_fu_471_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln45_phi_fu_290_p8; + +assign add_ln25_fu_391_p2 = (x_reg_168 + 6'd8); + +assign add_ln33_fu_434_p2 = (q_reg_276 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state11 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd7]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_499 = (~(trunc_ln33_fu_430_p1 == 3'd0) & ~(trunc_ln33_fu_430_p1 == 3'd4) & ~(trunc_ln33_fu_430_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_03_phi_fu_244_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_232_p4 = grp_fu_311_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_220_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_208_p4 = grp_fu_311_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_196_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_184_p4 = grp_fu_311_p2; + +assign icmp_ln45_5_fu_465_p2 = ((or_ln33_fu_440_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln45_6_fu_479_p2 = ((or_ln33_fu_440_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln45_fu_451_p2 = ((or_ln33_fu_440_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln29_13_fu_351_p2 = (trunc_ln25_reg_498 | 5'd2); + +assign or_ln29_14_fu_361_p2 = (trunc_ln25_reg_498 | 5'd3); + +assign or_ln29_15_fu_371_p2 = (trunc_ln25_reg_498 | 5'd4); + +assign or_ln29_16_fu_381_p2 = (trunc_ln25_reg_498 | 5'd5); + +assign or_ln29_17_fu_397_p2 = (trunc_ln25_reg_498 | 5'd6); + +assign or_ln29_18_fu_407_p2 = (trunc_ln25_reg_498 | 5'd7); + +assign or_ln29_fu_340_p2 = (trunc_ln25_fu_336_p1 | 5'd1); + +assign or_ln33_fu_440_p2 = (trunc_ln33_fu_430_p1 | 3'd1); + +assign select_ln45_5_fu_471_p3 = ((icmp_ln45_5_fu_465_p2[0:0] == 1'b1) ? psum_3_04_reg_228 : select_ln45_fu_457_p3); + +assign select_ln45_fu_457_p3 = ((icmp_ln45_fu_451_p2[0:0] == 1'b1) ? psum_1_02_reg_252 : psum_7_08_reg_180); + +assign tmp_36_fu_417_p3 = q_reg_276[32'd3]; + +assign tmp_fu_323_p3 = ap_phi_mux_x_phi_fu_172_p4[32'd5]; + +assign trunc_ln25_fu_336_p1 = ap_phi_mux_x_phi_fu_172_p4[4:0]; + +assign trunc_ln33_fu_430_p1 = q_reg_276[2:0]; + +assign zext_ln25_fu_331_p1 = ap_phi_mux_x_phi_fu_172_p4; + +assign zext_ln29_13_fu_356_p1 = or_ln29_13_fu_351_p2; + +assign zext_ln29_14_fu_366_p1 = or_ln29_14_fu_361_p2; + +assign zext_ln29_15_fu_376_p1 = or_ln29_15_fu_371_p2; + +assign zext_ln29_16_fu_386_p1 = or_ln29_16_fu_381_p2; + +assign zext_ln29_17_fu_402_p1 = or_ln29_17_fu_397_p2; + +assign zext_ln29_18_fu_412_p1 = or_ln29_18_fu_407_p2; + +assign zext_ln29_fu_346_p1 = or_ln29_fu_340_p2; + +assign zext_ln33_3_fu_446_p1 = or_ln33_fu_440_p2; + +assign zext_ln33_fu_425_p1 = q_reg_276; + +endmodule //td_fused_top_tdf3_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_14, + accum_in_14_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 7'd1; +parameter ap_ST_fsm_state2 = 7'd2; +parameter ap_ST_fsm_state3 = 7'd4; +parameter ap_ST_fsm_state4 = 7'd8; +parameter ap_ST_fsm_state5 = 7'd16; +parameter ap_ST_fsm_state6 = 7'd32; +parameter ap_ST_fsm_state7 = 7'd64; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_14; +output accum_in_14_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_14; +reg accum_in_14_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [6:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln57_fu_74_p2; +reg [3:0] add_ln57_reg_91; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln57_fu_85_p2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state7; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln57_fu_80_p1; +reg [15:0] accum_in_14_preg; +reg [6:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 7'd1; +#0 accum_in_14_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U166( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_q0), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_14_preg <= 16'd0; + end else begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_14_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + i_1_1_reg_44 <= add_ln57_reg_91; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln57_reg_91 <= add_ln57_fu_74_p2; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_14 = sum_01_reg_55; + end else begin + accum_in_14 = accum_in_14_preg; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_14_ap_vld = 1'b1; + end else begin + accum_in_14_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln57_fu_80_p1; + +assign add_ln57_fu_74_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln57_fu_85_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln57_fu_80_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf3_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 17'd1; +parameter ap_ST_fsm_state2 = 17'd2; +parameter ap_ST_fsm_state3 = 17'd4; +parameter ap_ST_fsm_state4 = 17'd8; +parameter ap_ST_fsm_state5 = 17'd16; +parameter ap_ST_fsm_state6 = 17'd32; +parameter ap_ST_fsm_state7 = 17'd64; +parameter ap_ST_fsm_state8 = 17'd128; +parameter ap_ST_fsm_state9 = 17'd256; +parameter ap_ST_fsm_state10 = 17'd512; +parameter ap_ST_fsm_state11 = 17'd1024; +parameter ap_ST_fsm_state12 = 17'd2048; +parameter ap_ST_fsm_state13 = 17'd4096; +parameter ap_ST_fsm_state14 = 17'd8192; +parameter ap_ST_fsm_state15 = 17'd16384; +parameter ap_ST_fsm_state16 = 17'd32768; +parameter ap_ST_fsm_state17 = 17'd65536; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_read; +output [3:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [3:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg indices_23_read; + +reg ap_done_reg; + reg [16:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +wire ap_CS_fsm_state4; +reg [15:0] tmp_61_i_i_reg_167; +reg [15:0] tmp_62_i_i_reg_172; +wire [15:0] grp_fu_81_p2; +reg [15:0] sub_i_i_i_reg_177; +wire ap_CS_fsm_state8; +wire ap_CS_fsm_state9; +wire [15:0] grp_fu_86_p2; +reg [15:0] mul_i_i_i_reg_187; +wire ap_CS_fsm_state12; +wire ap_CS_fsm_state13; +wire [63:0] zext_ln220_fu_90_p1; +reg ap_block_state1; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_77_p1; +wire [15:0] grp_fu_81_p1; +wire [15:0] grp_fu_86_p1; +wire [15:0] trunc_ln220_fu_95_p1; +wire [15:0] grp_fu_77_p2; +wire ap_CS_fsm_state17; +wire [15:0] bitcast_ln648_fu_132_p1; +wire [0:0] tmp_fu_136_p3; +reg [16:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 17'd1; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U170( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(mul_i_i_i_reg_187), + .din1(grp_fu_77_p1), + .dout(grp_fu_77_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U171( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sums_read), + .din1(grp_fu_81_p1), + .dout(grp_fu_81_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U172( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_177), + .din1(grp_fu_86_p1), + .dout(grp_fu_86_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + mul_i_i_i_reg_187 <= grp_fu_86_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sub_i_i_i_reg_177 <= grp_fu_81_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tmp_61_i_i_reg_167 <= {{adjustments_q0[31:16]}}; + tmp_62_i_i_reg_172 <= {{adjustments_q0[47:32]}}; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign adjustments_address0 = zext_ln220_fu_90_p1; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_return = ((tmp_fu_136_p3[0:0] == 1'b1) ? 16'd0 : grp_fu_77_p2); + +assign bitcast_ln648_fu_132_p1 = grp_fu_77_p2; + +assign grp_fu_77_p1 = tmp_62_i_i_reg_172; + +assign grp_fu_81_p1 = trunc_ln220_fu_95_p1; + +assign grp_fu_86_p1 = tmp_61_i_i_reg_167; + +assign tmp_fu_136_p3 = bitcast_ln648_fu_132_p1[32'd15]; + +assign trunc_ln220_fu_95_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_90_p1 = indices_23_dout; + +endmodule //td_fused_top_tdf3_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_q0, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state7 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [4:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +input [15:0] ifmap_vec_0_0_q0; +output [4:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +input [15:0] weight_vecs_0_0_0_q0; +output [4:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_0_0_ce0; +reg weight_vecs_0_0_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [5:0] ic_0_0_reg_69; +wire [5:0] add_ln149_fu_87_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln149_fu_93_p2; +reg [0:0] icmp_ln149_reg_118; +reg [0:0] icmp_ln149_reg_118_pp0_iter1_reg; +reg [0:0] icmp_ln149_reg_118_pp0_iter2_reg; +reg [0:0] icmp_ln149_reg_118_pp0_iter3_reg; +wire [4:0] trunc_ln150_fu_105_p1; +reg [4:0] trunc_ln150_reg_122; +reg [4:0] trunc_ln150_reg_122_pp0_iter1_reg; +reg [4:0] trunc_ln150_reg_122_pp0_iter2_reg; +reg [4:0] trunc_ln150_reg_122_pp0_iter3_reg; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +wire [63:0] zext_ln149_fu_99_p1; +wire ap_block_pp0_stage0; +wire [63:0] idxprom30_0_0_fu_109_p1; +wire [15:0] grp_fu_80_p2; +wire ap_CS_fsm_state7; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U158( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_0_q0), + .din1(weight_vecs_0_0_0_q0), + .dout(grp_fu_80_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_0_0_reg_69 <= 6'd0; + end else if (((icmp_ln149_fu_93_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_0_0_reg_69 <= add_ln149_fu_87_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln149_reg_118 <= icmp_ln149_fu_93_p2; + icmp_ln149_reg_118_pp0_iter1_reg <= icmp_ln149_reg_118; + trunc_ln150_reg_122_pp0_iter1_reg <= trunc_ln150_reg_122; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln149_reg_118_pp0_iter2_reg <= icmp_ln149_reg_118_pp0_iter1_reg; + icmp_ln149_reg_118_pp0_iter3_reg <= icmp_ln149_reg_118_pp0_iter2_reg; + trunc_ln150_reg_122_pp0_iter2_reg <= trunc_ln150_reg_122_pp0_iter1_reg; + trunc_ln150_reg_122_pp0_iter3_reg <= trunc_ln150_reg_122_pp0_iter2_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_fu_93_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln150_reg_122 <= trunc_ln150_fu_105_p1; + end +end + +always @ (*) begin + if ((icmp_ln149_fu_93_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln149_reg_118_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln149_fu_93_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln149_fu_93_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln149_fu_87_p2 = (ic_0_0_reg_69 + 6'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign icmp_ln149_fu_93_p2 = ((ic_0_0_reg_69 == 6'd32) ? 1'b1 : 1'b0); + +assign idxprom30_0_0_fu_109_p1 = trunc_ln150_reg_122_pp0_iter3_reg; + +assign ifmap_vec_0_0_address0 = zext_ln149_fu_99_p1; + +assign products_0_address0 = idxprom30_0_0_fu_109_p1; + +assign products_0_d0 = grp_fu_80_p2; + +assign trunc_ln150_fu_105_p1 = ic_0_0_reg_69[4:0]; + +assign weight_vecs_0_0_0_address0 = zext_ln149_fu_99_p1; + +assign zext_ln149_fu_99_p1 = ic_0_0_reg_69; + +endmodule //td_fused_top_tdf3_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf3_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 9; +parameter MEM_SIZE = 512; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf3_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd512; +parameter AddressWidth = 32'd9; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf3_filters_ram td_fused_top_tdf3_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + indices_2_out_din, + indices_2_out_full_n, + indices_2_out_write, + indices_2_out1_din, + indices_2_out1_full_n, + indices_2_out1_write +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [3:0] indices_2_out_din; +input indices_2_out_full_n; +output indices_2_out_write; +output [3:0] indices_2_out1_din; +input indices_2_out1_full_n; +output indices_2_out1_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg indices_0_write; +reg indices_1_write; +reg indices_2_out_write; +reg indices_2_out1_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [15:0] i_2; +reg [15:0] j_2; +reg [15:0] k_2; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg indices_2_out_blk_n; +reg indices_2_out1_blk_n; +reg [0:0] ap_phi_mux_j_14_flag_0_i_phi_fu_77_p6; +reg ap_block_state1; +wire [0:0] icmp_ln78_fu_141_p2; +wire [0:0] icmp_ln81_fu_154_p2; +reg [15:0] ap_phi_mux_j_14_new_0_i_phi_fu_91_p6; +wire [15:0] add_ln80_fu_147_p2; +reg [15:0] ap_phi_mux_k_14_new_0_i_phi_fu_104_p6; +wire [15:0] add_ln77_fu_134_p2; +wire [15:0] select_ln84_fu_172_p3; +wire [3:0] trunc_ln76_fu_128_p1; +wire [15:0] add_ln83_fu_160_p2; +wire [0:0] icmp_ln84_fu_166_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_2 = 16'd0; +#0 j_2 = 16'd0; +#0 k_2 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_2 <= select_ln84_fu_172_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_14_flag_0_i_phi_fu_77_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j_2 <= ap_phi_mux_j_14_new_0_i_phi_fu_91_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k_2 <= ap_phi_mux_k_14_new_0_i_phi_fu_104_p6; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_14_flag_0_i_phi_fu_77_p6 = 1'd0; + end else if ((((icmp_ln81_fu_154_p2 == 1'd0) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_14_flag_0_i_phi_fu_77_p6 = 1'd1; + end else begin + ap_phi_mux_j_14_flag_0_i_phi_fu_77_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln81_fu_154_p2 == 1'd0)) begin + ap_phi_mux_j_14_new_0_i_phi_fu_91_p6 = add_ln80_fu_147_p2; + end else if ((icmp_ln81_fu_154_p2 == 1'd1)) begin + ap_phi_mux_j_14_new_0_i_phi_fu_91_p6 = 16'd0; + end else begin + ap_phi_mux_j_14_new_0_i_phi_fu_91_p6 = 'bx; + end + end else begin + ap_phi_mux_j_14_new_0_i_phi_fu_91_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_14_new_0_i_phi_fu_104_p6 = add_ln77_fu_134_p2; + end else if ((((icmp_ln81_fu_154_p2 == 1'd0) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_14_new_0_i_phi_fu_104_p6 = 16'd0; + end else begin + ap_phi_mux_k_14_new_0_i_phi_fu_104_p6 = 'bx; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_blk_n = indices_2_out1_full_n; + end else begin + indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_write = 1'b1; + end else begin + indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_blk_n = indices_2_out_full_n; + end else begin + indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_write = 1'b1; + end else begin + indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln77_fu_134_p2 = (k_2 + 16'd1); + +assign add_ln80_fu_147_p2 = (j_2 + 16'd1); + +assign add_ln83_fu_160_p2 = (i_2 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign icmp_ln78_fu_141_p2 = ((add_ln77_fu_134_p2 == 16'd16) ? 1'b1 : 1'b0); + +assign icmp_ln81_fu_154_p2 = ((add_ln80_fu_147_p2 == 16'd56) ? 1'b1 : 1'b0); + +assign icmp_ln84_fu_166_p2 = ((add_ln83_fu_160_p2 == 16'd56) ? 1'b1 : 1'b0); + +assign indices_0_din = i_2; + +assign indices_1_din = j_2; + +assign indices_2_out1_din = trunc_ln76_fu_128_p1; + +assign indices_2_out_din = trunc_ln76_fu_128_p1; + +assign select_ln84_fu_172_p3 = ((icmp_ln84_fu_166_p2[0:0] == 1'b1) ? 16'd0 : add_ln83_fu_160_p2); + +assign start_out = real_start; + +assign trunc_ln76_fu_128_p1 = k_2[3:0]; + +endmodule //td_fused_top_tdf3_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_readFilters30 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_we0, + weight_vecs_0_0_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state6 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [8:0] filter_data_address0; +output filter_data_ce0; +input [15:0] filter_data_q0; +input [3:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [4:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +output weight_vecs_0_0_0_we0; +output [15:0] weight_vecs_0_0_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg indices_23_read; +reg weight_vecs_0_0_0_ce0; +reg weight_vecs_0_0_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [5:0] kk_0_0_i_i_reg_93; +reg [5:0] kk_0_0_i_i_reg_93_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_pp0_stage0_11001; +reg [5:0] kk_0_0_i_i_reg_93_pp0_iter2_reg; +wire [8:0] tmp_fu_105_p3; +reg [8:0] tmp_reg_144; +wire [5:0] add_ln49_fu_113_p2; +reg [5:0] add_ln49_reg_149; +reg ap_enable_reg_pp0_iter0; +wire [0:0] icmp_ln49_fu_119_p2; +reg [0:0] icmp_ln49_reg_154; +reg [0:0] icmp_ln49_reg_154_pp0_iter1_reg; +reg [0:0] icmp_ln49_reg_154_pp0_iter2_reg; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg [5:0] ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln55_39_fu_134_p1; +wire [63:0] zext_ln49_fu_139_p1; +wire [8:0] zext_ln55_fu_125_p1; +wire [8:0] add_ln55_fu_129_p2; +wire ap_CS_fsm_state6; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_0_i_i_reg_93 <= add_ln49_reg_149; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_0_0_i_i_reg_93 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln49_reg_149 <= add_ln49_fu_113_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln49_reg_154 <= icmp_ln49_fu_119_p2; + icmp_ln49_reg_154_pp0_iter1_reg <= icmp_ln49_reg_154; + kk_0_0_i_i_reg_93_pp0_iter1_reg <= kk_0_0_i_i_reg_93; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln49_reg_154_pp0_iter2_reg <= icmp_ln49_reg_154_pp0_iter1_reg; + kk_0_0_i_i_reg_93_pp0_iter2_reg <= kk_0_0_i_i_reg_93_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + tmp_reg_144[8 : 5] <= tmp_fu_105_p3[8 : 5]; + end +end + +always @ (*) begin + if ((icmp_ln49_fu_119_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 = add_ln49_reg_149; + end else begin + ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 = kk_0_0_i_i_reg_93; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln49_reg_154_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1))) begin + weight_vecs_0_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln49_fu_119_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln49_fu_119_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln49_fu_113_p2 = (ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 + 6'd1); + +assign add_ln55_fu_129_p2 = (tmp_reg_144 + zext_ln55_fu_125_p1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_address0 = zext_ln55_39_fu_134_p1; + +assign icmp_ln49_fu_119_p2 = ((ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 == 6'd32) ? 1'b1 : 1'b0); + +assign tmp_fu_105_p3 = {{indices_23_dout}, {5'd0}}; + +assign weight_vecs_0_0_0_address0 = zext_ln49_fu_139_p1; + +assign weight_vecs_0_0_0_d0 = filter_data_q0; + +assign zext_ln49_fu_139_p1 = kk_0_0_i_i_reg_93_pp0_iter2_reg; + +assign zext_ln55_39_fu_134_p1 = add_ln55_fu_129_p2; + +assign zext_ln55_fu_125_p1 = ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4; + +always @ (posedge ap_clk) begin + tmp_reg_144[4:0] <= 5'b00000; +end + +endmodule //td_fused_top_tdf3_readFilters30 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_readInputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_we0, + ifmap_vec_0_0_d0, + ifmap_vec_0_0_address1, + ifmap_vec_0_0_ce1, + ifmap_vec_0_0_we1, + ifmap_vec_0_0_d1, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 5'd1; +parameter ap_ST_fsm_state2 = 5'd2; +parameter ap_ST_fsm_pp0_stage0 = 5'd4; +parameter ap_ST_fsm_pp0_stage1 = 5'd8; +parameter ap_ST_fsm_state8 = 5'd16; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [14:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [4:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +output ifmap_vec_0_0_we0; +output [15:0] ifmap_vec_0_0_d0; +output [4:0] ifmap_vec_0_0_address1; +output ifmap_vec_0_0_ce1; +output ifmap_vec_0_0_we1; +output [15:0] ifmap_vec_0_0_d1; +output [5:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [11:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg[4:0] ifmap_vec_0_0_address0; +reg ifmap_vec_0_0_ce0; +reg ifmap_vec_0_0_we0; +reg[15:0] ifmap_vec_0_0_d0; +reg[4:0] ifmap_vec_0_0_address1; +reg ifmap_vec_0_0_ce1; +reg ifmap_vec_0_0_we1; +reg[15:0] ifmap_vec_0_0_d1; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [4:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [5:0] kk_0_i_i_reg_178; +reg [5:0] kk_0_i_i_reg_178_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state5_pp0_stage0_iter1; +wire ap_block_state7_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [5:0] trunc_ln135_fu_190_p1; +reg [5:0] trunc_ln135_reg_432; +reg [15:0] col_coord_reg_437; +wire [0:0] is_padding_fu_212_p2; +reg [0:0] is_padding_reg_442; +wire [13:0] add_ln32_fu_272_p2; +reg [13:0] add_ln32_reg_452; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln25_fu_278_p2; +reg [0:0] icmp_ln25_reg_457; +reg [0:0] icmp_ln25_reg_457_pp0_iter1_reg; +wire [5:0] add_ln25_fu_306_p2; +reg [5:0] add_ln25_reg_466; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state4_pp0_stage1_iter0; +wire ap_block_state6_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +wire [4:0] empty_104_fu_317_p1; +reg [4:0] empty_104_reg_471; +wire [15:0] select_ln33_20_fu_384_p3; +reg [15:0] select_ln33_20_reg_477; +wire [15:0] select_ln33_21_fu_405_p3; +reg [15:0] select_ln33_21_reg_482; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state3; +reg ap_enable_reg_pp0_iter1; +wire ap_block_pp0_stage1_subdone; +reg ap_enable_reg_pp0_iter2; +reg [5:0] ap_phi_mux_kk_0_i_i_phi_fu_182_p4; +wire ap_block_pp0_stage0; +wire [63:0] sext_ln32_fu_301_p1; +wire [63:0] kk_0_cast4_i_i_fu_312_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln32_16_fu_343_p1; +wire [63:0] zext_ln32_17_fu_417_p1; +wire [63:0] zext_ln32_18_fu_427_p1; +reg ap_block_state1; +wire [15:0] select_ln33_fu_329_p3; +wire [15:0] select_ln33_19_fu_362_p3; +wire [0:0] cmp7_i_i_fu_200_p2; +wire [0:0] icmp_ln24_fu_206_p2; +wire [5:0] empty_102_fu_218_p1; +wire [5:0] row_coord_int_fu_221_p3; +wire [11:0] tmp_fu_234_p3; +wire [8:0] tmp_s_fu_246_p3; +wire [12:0] zext_ln32_fu_242_p1; +wire [12:0] zext_ln32_20_fu_254_p1; +wire [12:0] sub_ln32_fu_258_p2; +wire [5:0] col_coord_int_fu_227_p3; +wire [13:0] sub_ln32_cast_fu_264_p1; +wire [13:0] zext_ln32_21_fu_268_p1; +wire [2:0] lshr_ln_fu_284_p4; +wire [16:0] tmp_35_fu_294_p3; +wire [15:0] trunc_ln32_fu_321_p1; +wire [15:0] bitcast_ln32_fu_325_p1; +wire [4:0] or_ln25_fu_337_p2; +wire [15:0] tmp_58_i_i_fu_348_p4; +wire [15:0] bitcast_ln32_19_fu_358_p1; +wire [15:0] tmp_59_i_i_fu_370_p4; +wire [15:0] bitcast_ln32_20_fu_380_p1; +wire [15:0] tmp_60_i_i_fu_391_p4; +wire [15:0] bitcast_ln32_21_fu_401_p1; +wire [4:0] or_ln25_13_fu_412_p2; +wire [4:0] or_ln25_14_fu_422_p2; +wire ap_CS_fsm_state8; +reg [4:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 5'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln25_reg_457 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_i_i_reg_178 <= add_ln25_reg_466; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + kk_0_i_i_reg_178 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln25_reg_457 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln25_reg_466 <= add_ln25_fu_306_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln32_reg_452 <= add_ln32_fu_272_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + col_coord_reg_437 <= indices_12_dout; + is_padding_reg_442 <= is_padding_fu_212_p2; + trunc_ln135_reg_432 <= trunc_ln135_fu_190_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln25_reg_457_pp0_iter1_reg == 1'd0))) begin + empty_104_reg_471 <= empty_104_fu_317_p1; + select_ln33_20_reg_477 <= select_ln33_20_fu_384_p3; + select_ln33_21_reg_482 <= select_ln33_21_fu_405_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln25_reg_457 <= icmp_ln25_fu_278_p2; + icmp_ln25_reg_457_pp0_iter1_reg <= icmp_ln25_reg_457; + kk_0_i_i_reg_178_pp0_iter1_reg <= kk_0_i_i_reg_178; + end +end + +always @ (*) begin + if ((icmp_ln25_fu_278_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln25_reg_457 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_i_i_phi_fu_182_p4 = add_ln25_reg_466; + end else begin + ap_phi_mux_kk_0_i_i_phi_fu_182_p4 = kk_0_i_i_reg_178; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_address0 = zext_ln32_18_fu_427_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_address0 = zext_ln32_16_fu_343_p1; + end else begin + ifmap_vec_0_0_address0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_address1 = zext_ln32_17_fu_417_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_address1 = kk_0_cast4_i_i_fu_312_p1; + end else begin + ifmap_vec_0_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_ce1 = 1'b1; + end else begin + ifmap_vec_0_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_d0 = select_ln33_21_reg_482; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_d0 = select_ln33_19_fu_362_p3; + end else begin + ifmap_vec_0_0_d0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_d1 = select_ln33_20_reg_477; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_d1 = select_ln33_fu_329_p3; + end else begin + ifmap_vec_0_0_d1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln25_reg_457_pp0_iter1_reg == 1'd0)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln25_reg_457_pp0_iter1_reg == 1'd0)))) begin + ifmap_vec_0_0_we0 = 1'b1; + end else begin + ifmap_vec_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln25_reg_457_pp0_iter1_reg == 1'd0)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln25_reg_457_pp0_iter1_reg == 1'd0)))) begin + ifmap_vec_0_0_we1 = 1'b1; + end else begin + ifmap_vec_0_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln25_fu_278_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if ((((icmp_ln25_fu_278_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state8; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln25_fu_306_p2 = (kk_0_i_i_reg_178 + 6'd4); + +assign add_ln32_fu_272_p2 = ((sub_ln32_cast_fu_264_p1) + (zext_ln32_21_fu_268_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd4]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln32_19_fu_358_p1 = tmp_58_i_i_fu_348_p4; + +assign bitcast_ln32_20_fu_380_p1 = tmp_59_i_i_fu_370_p4; + +assign bitcast_ln32_21_fu_401_p1 = tmp_60_i_i_fu_391_p4; + +assign bitcast_ln32_fu_325_p1 = trunc_ln32_fu_321_p1; + +assign cmp7_i_i_fu_200_p2 = ((indices_01_dout > 16'd55) ? 1'b1 : 1'b0); + +assign col_coord_int_fu_227_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 6'd0 : empty_102_fu_218_p1); + +assign empty_102_fu_218_p1 = col_coord_reg_437[5:0]; + +assign empty_104_fu_317_p1 = kk_0_i_i_reg_178_pp0_iter1_reg[4:0]; + +assign icmp_ln24_fu_206_p2 = ((indices_12_dout > 16'd55) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_278_p2 = ((ap_phi_mux_kk_0_i_i_phi_fu_182_p4 == 6'd32) ? 1'b1 : 1'b0); + +assign in_data_address0 = sext_ln32_fu_301_p1; + +assign indices_01_out_din = indices_01_dout[5:0]; + +assign indices_12_out_din = indices_12_dout[11:0]; + +assign is_padding_fu_212_p2 = (icmp_ln24_fu_206_p2 | cmp7_i_i_fu_200_p2); + +assign kk_0_cast4_i_i_fu_312_p1 = kk_0_i_i_reg_178_pp0_iter1_reg; + +assign lshr_ln_fu_284_p4 = {{ap_phi_mux_kk_0_i_i_phi_fu_182_p4[4:2]}}; + +assign or_ln25_13_fu_412_p2 = (empty_104_reg_471 | 5'd2); + +assign or_ln25_14_fu_422_p2 = (empty_104_reg_471 | 5'd3); + +assign or_ln25_fu_337_p2 = (empty_104_fu_317_p1 | 5'd1); + +assign row_coord_int_fu_221_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 6'd0 : trunc_ln135_reg_432); + +assign select_ln33_19_fu_362_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_19_fu_358_p1); + +assign select_ln33_20_fu_384_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_20_fu_380_p1); + +assign select_ln33_21_fu_405_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_21_fu_401_p1); + +assign select_ln33_fu_329_p3 = ((is_padding_reg_442[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_fu_325_p1); + +assign sext_ln32_fu_301_p1 = (tmp_35_fu_294_p3); + +assign sub_ln32_cast_fu_264_p1 = (sub_ln32_fu_258_p2); + +assign sub_ln32_fu_258_p2 = (zext_ln32_fu_242_p1 - zext_ln32_20_fu_254_p1); + +assign tmp_35_fu_294_p3 = {{add_ln32_reg_452}, {lshr_ln_fu_284_p4}}; + +assign tmp_58_i_i_fu_348_p4 = {{in_data_q0[31:16]}}; + +assign tmp_59_i_i_fu_370_p4 = {{in_data_q0[47:32]}}; + +assign tmp_60_i_i_fu_391_p4 = {{in_data_q0[63:48]}}; + +assign tmp_fu_234_p3 = {{row_coord_int_fu_221_p3}, {6'd0}}; + +assign tmp_s_fu_246_p3 = {{row_coord_int_fu_221_p3}, {3'd0}}; + +assign trunc_ln135_fu_190_p1 = indices_01_dout[5:0]; + +assign trunc_ln32_fu_321_p1 = in_data_q0[15:0]; + +assign zext_ln32_16_fu_343_p1 = or_ln25_fu_337_p2; + +assign zext_ln32_17_fu_417_p1 = or_ln25_13_fu_412_p2; + +assign zext_ln32_18_fu_427_p1 = or_ln25_14_fu_422_p2; + +assign zext_ln32_20_fu_254_p1 = tmp_s_fu_246_p3; + +assign zext_ln32_21_fu_268_p1 = col_coord_int_fu_227_p3; + +assign zext_ln32_fu_242_p1 = tmp_fu_234_p3; + +endmodule //td_fused_top_tdf3_readInputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf3_writeOutputs_unaligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + p_read, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_state2 = 3'd2; +parameter ap_ST_fsm_state3 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [5:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [11:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [15:0] p_read; +output [13:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg out_data_ce1; +reg out_data_we1; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] outputCount_6; +reg [15:0] outputChanIdx_6; +reg [15:0] outputRow_10_0; +reg [15:0] outputRow_10_1; +reg [15:0] outputRow_10_2; +reg [15:0] outputRow_10_3; +reg indices_01_blk_n; +reg indices_12_blk_n; +wire [13:0] shl_ln89_fu_163_p2; +reg [13:0] shl_ln89_reg_312; +wire [15:0] add_ln87_fu_201_p2; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln88_fu_207_p2; +reg [0:0] icmp_ln88_reg_325; +reg [15:0] ap_phi_mux_empty_phi_fu_112_p4; +reg [15:0] empty_reg_109; +wire ap_CS_fsm_state3; +wire [63:0] zext_ln94_12_fu_234_p1; +wire [15:0] select_ln97_fu_292_p3; +wire [1:0] trunc_ln86_fu_173_p1; +reg [15:0] ap_sig_allocacmp_outputRow_10_0_load; +reg [15:0] ap_sig_allocacmp_outputRow_10_1_load; +reg [15:0] ap_sig_allocacmp_outputRow_10_2_load; +reg [15:0] ap_sig_allocacmp_outputRow_10_3_load; +reg ap_block_state1; +wire [11:0] tmp_fu_119_p3; +wire [8:0] tmp_s_fu_131_p3; +wire [12:0] zext_ln94_fu_127_p1; +wire [12:0] zext_ln94_9_fu_139_p1; +wire [12:0] sub_ln94_fu_143_p2; +wire [13:0] sub_ln94_cast13_fu_149_p1; +wire [13:0] zext_ln94_10_fu_153_p1; +wire [13:0] add_ln94_fu_157_p2; +wire [3:0] trunc_ln94_fu_221_p1; +wire [13:0] zext_ln94_11_fu_225_p1; +wire [13:0] add_ln94_5_fu_229_p2; +wire [15:0] bitcast_ln94_15_fu_263_p1; +wire [15:0] bitcast_ln94_14_fu_255_p1; +wire [15:0] bitcast_ln94_13_fu_247_p1; +wire [15:0] bitcast_ln94_fu_239_p1; +wire [15:0] add_ln96_fu_280_p2; +wire [0:0] icmp_ln97_fu_286_p2; +reg [2:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 outputCount_6 = 16'd0; +#0 outputChanIdx_6 = 16'd0; +#0 outputRow_10_0 = 16'd0; +#0 outputRow_10_1 = 16'd0; +#0 outputRow_10_2 = 16'd0; +#0 outputRow_10_3 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state3)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_reg_325 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + empty_reg_109 <= 16'd0; + end else if (((icmp_ln88_fu_207_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + empty_reg_109 <= add_ln87_fu_201_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + icmp_ln88_reg_325 <= icmp_ln88_fu_207_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_fu_207_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + outputChanIdx_6 <= select_ln97_fu_292_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + outputCount_6 <= ap_phi_mux_empty_phi_fu_112_p4; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_173_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_10_0 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_173_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_10_1 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_173_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_10_2 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_173_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_10_3 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + shl_ln89_reg_312[13 : 2] <= shl_ln89_fu_163_p2[13 : 2]; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_reg_325 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + ap_phi_mux_empty_phi_fu_112_p4 = 16'd0; + end else begin + ap_phi_mux_empty_phi_fu_112_p4 = empty_reg_109; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_173_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_10_0_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_10_0_load = outputRow_10_0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_173_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_10_1_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_10_1_load = outputRow_10_1; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_173_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_10_2_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_10_2_load = outputRow_10_2; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_173_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_10_3_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_10_3_load = outputRow_10_3; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2))) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_fu_207_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln87_fu_201_p2 = (outputCount_6 + 16'd1); + +assign add_ln94_5_fu_229_p2 = (shl_ln89_reg_312 + zext_ln94_11_fu_225_p1); + +assign add_ln94_fu_157_p2 = (sub_ln94_cast13_fu_149_p1 + zext_ln94_10_fu_153_p1); + +assign add_ln96_fu_280_p2 = (outputChanIdx_6 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign bitcast_ln94_13_fu_247_p1 = ap_sig_allocacmp_outputRow_10_1_load; + +assign bitcast_ln94_14_fu_255_p1 = ap_sig_allocacmp_outputRow_10_2_load; + +assign bitcast_ln94_15_fu_263_p1 = ap_sig_allocacmp_outputRow_10_3_load; + +assign bitcast_ln94_fu_239_p1 = ap_sig_allocacmp_outputRow_10_0_load; + +assign icmp_ln88_fu_207_p2 = ((add_ln87_fu_201_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign icmp_ln97_fu_286_p2 = ((add_ln96_fu_280_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign out_data_address1 = zext_ln94_12_fu_234_p1; + +assign out_data_d1 = {{{{bitcast_ln94_15_fu_263_p1}, {bitcast_ln94_14_fu_255_p1}}, {bitcast_ln94_13_fu_247_p1}}, {bitcast_ln94_fu_239_p1}}; + +assign select_ln97_fu_292_p3 = ((icmp_ln97_fu_286_p2[0:0] == 1'b1) ? 16'd0 : add_ln96_fu_280_p2); + +assign shl_ln89_fu_163_p2 = add_ln94_fu_157_p2 << 14'd2; + +assign sub_ln94_cast13_fu_149_p1 = sub_ln94_fu_143_p2; + +assign sub_ln94_fu_143_p2 = (zext_ln94_fu_127_p1 - zext_ln94_9_fu_139_p1); + +assign tmp_fu_119_p3 = {{indices_01_dout}, {6'd0}}; + +assign tmp_s_fu_131_p3 = {{indices_01_dout}, {3'd0}}; + +assign trunc_ln86_fu_173_p1 = outputCount_6[1:0]; + +assign trunc_ln94_fu_221_p1 = outputChanIdx_6[3:0]; + +assign zext_ln94_10_fu_153_p1 = indices_12_dout; + +assign zext_ln94_11_fu_225_p1 = trunc_ln94_fu_221_p1; + +assign zext_ln94_12_fu_234_p1 = add_ln94_5_fu_229_p2; + +assign zext_ln94_9_fu_139_p1 = tmp_s_fu_131_p3; + +assign zext_ln94_fu_127_p1 = tmp_fu_119_p3; + +always @ (posedge ap_clk) begin + shl_ln89_reg_312[1:0] <= 2'b00; +end + +endmodule //td_fused_top_tdf3_writeOutputs_unaligned +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_111 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + l1_filter_data_address0, + l1_filter_data_ce0, + l1_filter_data_d0, + l1_filter_data_q0, + l1_filter_data_we0, + l1_filter_data_address1, + l1_filter_data_ce1, + l1_filter_data_d1, + l1_filter_data_q1, + l1_filter_data_we1, + l2_filter_data_address0, + l2_filter_data_ce0, + l2_filter_data_d0, + l2_filter_data_q0, + l2_filter_data_we0, + l2_filter_data_address1, + l2_filter_data_ce1, + l2_filter_data_d1, + l2_filter_data_q1, + l2_filter_data_we1, + l1_adjustments_address0, + l1_adjustments_ce0, + l1_adjustments_d0, + l1_adjustments_q0, + l1_adjustments_we0, + l1_adjustments_address1, + l1_adjustments_ce1, + l1_adjustments_d1, + l1_adjustments_q1, + l1_adjustments_we1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_d0, + l2_adjustments_q0, + l2_adjustments_we0, + l2_adjustments_address1, + l2_adjustments_ce1, + l2_adjustments_d1, + l2_adjustments_q1, + l2_adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [13:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [13:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [13:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [13:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [14:0] l1_filter_data_address0; +output l1_filter_data_ce0; +output [15:0] l1_filter_data_d0; +input [15:0] l1_filter_data_q0; +output l1_filter_data_we0; +output [14:0] l1_filter_data_address1; +output l1_filter_data_ce1; +output [15:0] l1_filter_data_d1; +input [15:0] l1_filter_data_q1; +output l1_filter_data_we1; +output [10:0] l2_filter_data_address0; +output l2_filter_data_ce0; +output [15:0] l2_filter_data_d0; +input [15:0] l2_filter_data_q0; +output l2_filter_data_we0; +output [10:0] l2_filter_data_address1; +output l2_filter_data_ce1; +output [15:0] l2_filter_data_d1; +input [15:0] l2_filter_data_q1; +output l2_filter_data_we1; +output [6:0] l1_adjustments_address0; +output l1_adjustments_ce0; +output [47:0] l1_adjustments_d0; +input [47:0] l1_adjustments_q0; +output l1_adjustments_we0; +output [6:0] l1_adjustments_address1; +output l1_adjustments_ce1; +output [47:0] l1_adjustments_d1; +input [47:0] l1_adjustments_q1; +output l1_adjustments_we1; +output [3:0] l2_adjustments_address0; +output l2_adjustments_ce0; +output [47:0] l2_adjustments_d0; +input [47:0] l2_adjustments_q0; +output l2_adjustments_we0; +output [3:0] l2_adjustments_address1; +output l2_adjustments_ce1; +output [47:0] l2_adjustments_d1; +input [47:0] l2_adjustments_q1; +output l2_adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [13:0] dataflow_in_loop_TOP_LOOP37832_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP37832_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP37832_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP37832_U0_in_data_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP37832_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP37832_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP37832_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP37832_U0_in_data_we1; +wire [14:0] dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_we1; +wire [6:0] dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_we0; +wire [6:0] dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_we1; +wire [10:0] dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_we0; +wire [10:0] dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP37832_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP37832_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP37832_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP37832_U0_out_data_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP37832_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP37832_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP37832_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP37832_U0_out_data_we1; +wire [3:0] dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_we0; +wire [3:0] dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_we1; +wire dataflow_in_loop_TOP_LOOP37832_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP37832_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP37832_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP37832_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP37832_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP37832_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP37832_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP37832_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP37832_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [18:0] loop_dataflow_input_count; +reg [18:0] loop_dataflow_output_count; +wire [18:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP37832_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP37832_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 19'd0; +#0 loop_dataflow_output_count = 19'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP37832 dataflow_in_loop_TOP_LOOP37832_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP37832_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP37832_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP37832_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP37832_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP37832_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP37832_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP37832_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP37832_U0_in_data_we1), + .l1_filter_data_address0(dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_address0), + .l1_filter_data_ce0(dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_ce0), + .l1_filter_data_d0(dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_d0), + .l1_filter_data_q0(l1_filter_data_q0), + .l1_filter_data_we0(dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_we0), + .l1_filter_data_address1(dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_address1), + .l1_filter_data_ce1(dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_ce1), + .l1_filter_data_d1(dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_d1), + .l1_filter_data_q1(16'd0), + .l1_filter_data_we1(dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_we1), + .l1_adjustments_address0(dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_address0), + .l1_adjustments_ce0(dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_ce0), + .l1_adjustments_d0(dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_d0), + .l1_adjustments_q0(l1_adjustments_q0), + .l1_adjustments_we0(dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_we0), + .l1_adjustments_address1(dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_address1), + .l1_adjustments_ce1(dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_ce1), + .l1_adjustments_d1(dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_d1), + .l1_adjustments_q1(48'd0), + .l1_adjustments_we1(dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_we1), + .l2_filter_data_address0(dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_address0), + .l2_filter_data_ce0(dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_ce0), + .l2_filter_data_d0(dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_d0), + .l2_filter_data_q0(l2_filter_data_q0), + .l2_filter_data_we0(dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_we0), + .l2_filter_data_address1(dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_address1), + .l2_filter_data_ce1(dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_ce1), + .l2_filter_data_d1(dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_d1), + .l2_filter_data_q1(16'd0), + .l2_filter_data_we1(dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP37832_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP37832_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP37832_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP37832_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP37832_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP37832_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP37832_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP37832_U0_out_data_we1), + .l2_adjustments_address0(dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_address0), + .l2_adjustments_ce0(dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_ce0), + .l2_adjustments_d0(dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_d0), + .l2_adjustments_q0(l2_adjustments_q0), + .l2_adjustments_we0(dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_we0), + .l2_adjustments_address1(dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_address1), + .l2_adjustments_ce1(dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_ce1), + .l2_adjustments_d1(dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_d1), + .l2_adjustments_q1(48'd0), + .l2_adjustments_we1(dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_we1), + .ap_start(dataflow_in_loop_TOP_LOOP37832_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP37832_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP37832_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP37832_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP37832_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP37832_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP37832_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 19'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP37832_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 19'd1); + end else if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP37832_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= 19'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 19'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37832_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP37832_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 19'd1); + end else if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37832_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP37832_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= 19'd0; + end + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37832_U0_ap_done == 1'b1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == 19'd0) & (ap_start == 1'b0) & (dataflow_in_loop_TOP_LOOP37832_U0_ap_idle == 1'b1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP37832_U0_ap_ready == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP37832_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP37832_U0_ap_continue = 1'b0; + end +end + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP37832_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP37832_U0_ap_ready; + +assign bound_minus_1 = (19'd401408 - 19'd1); + +assign dataflow_in_loop_TOP_LOOP37832_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP37832_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP37832_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP37832_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP37832_U0_start_write = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP37832_U0_in_data_address0; + +assign in_data_address1 = 14'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP37832_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP37832_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign l1_adjustments_address0 = dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_address0; + +assign l1_adjustments_address1 = 7'd0; + +assign l1_adjustments_ce0 = dataflow_in_loop_TOP_LOOP37832_U0_l1_adjustments_ce0; + +assign l1_adjustments_ce1 = 1'b0; + +assign l1_adjustments_d0 = 48'd0; + +assign l1_adjustments_d1 = 48'd0; + +assign l1_adjustments_we0 = 1'b0; + +assign l1_adjustments_we1 = 1'b0; + +assign l1_filter_data_address0 = dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_address0; + +assign l1_filter_data_address1 = 15'd0; + +assign l1_filter_data_ce0 = dataflow_in_loop_TOP_LOOP37832_U0_l1_filter_data_ce0; + +assign l1_filter_data_ce1 = 1'b0; + +assign l1_filter_data_d0 = 16'd0; + +assign l1_filter_data_d1 = 16'd0; + +assign l1_filter_data_we0 = 1'b0; + +assign l1_filter_data_we1 = 1'b0; + +assign l2_adjustments_address0 = dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_address0; + +assign l2_adjustments_address1 = 4'd0; + +assign l2_adjustments_ce0 = dataflow_in_loop_TOP_LOOP37832_U0_l2_adjustments_ce0; + +assign l2_adjustments_ce1 = 1'b0; + +assign l2_adjustments_d0 = 48'd0; + +assign l2_adjustments_d1 = 48'd0; + +assign l2_adjustments_we0 = 1'b0; + +assign l2_adjustments_we1 = 1'b0; + +assign l2_filter_data_address0 = dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_address0; + +assign l2_filter_data_address1 = 11'd0; + +assign l2_filter_data_ce0 = dataflow_in_loop_TOP_LOOP37832_U0_l2_filter_data_ce0; + +assign l2_filter_data_ce1 = 1'b0; + +assign l2_filter_data_d0 = 16'd0; + +assign l2_filter_data_d1 = 16'd0; + +assign l2_filter_data_we0 = 1'b0; + +assign l2_filter_data_we1 = 1'b0; + +assign out_data_address0 = 14'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP37832_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP37832_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP37832_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP37832_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP37832_U0_out_data_write; + +endmodule //td_fused_top_tdf4_111 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 8'd1; +parameter ap_ST_fsm_pp0_stage0 = 8'd2; +parameter ap_ST_fsm_pp0_stage1 = 8'd4; +parameter ap_ST_fsm_pp0_stage2 = 8'd8; +parameter ap_ST_fsm_pp0_stage3 = 8'd16; +parameter ap_ST_fsm_state12 = 8'd32; +parameter ap_ST_fsm_state13 = 8'd64; +parameter ap_ST_fsm_state14 = 8'd128; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [7:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [7:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[7:0] accum_in_0_address0; +reg accum_in_0_ce0; +reg[7:0] accum_in_0_address1; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [7:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] x_reg_168; +reg [15:0] psum_7_08_reg_180; +reg [15:0] psum_6_07_reg_192; +reg [15:0] psum_5_06_reg_204; +reg [15:0] psum_4_05_reg_216; +reg [15:0] psum_3_04_reg_228; +reg [15:0] psum_2_03_reg_240; +reg [15:0] psum_1_02_reg_252; +reg [15:0] psum_0_01_reg_264; +wire [0:0] icmp_ln132_fu_321_p2; +reg [0:0] icmp_ln132_reg_492; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state6_pp0_stage0_iter1; +wire ap_block_state10_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln132_reg_492_pp0_iter1_reg; +reg [0:0] icmp_ln132_reg_492_pp0_iter2_reg; +reg [15:0] accum_in_0_load_reg_506; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state7_pp0_stage1_iter1; +wire ap_block_state11_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_0_load_36_reg_511; +reg [15:0] accum_in_0_load_37_reg_526; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state8_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_0_load_38_reg_531; +wire [7:0] add_ln132_fu_387_p2; +reg [7:0] add_ln132_reg_546; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state9_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_0_load_39_reg_551; +reg [15:0] accum_in_0_load_40_reg_556; +reg [15:0] accum_in_0_load_41_reg_571; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_0_load_42_reg_576; +wire [15:0] grp_fu_305_p2; +wire [15:0] grp_fu_310_p2; +reg ap_enable_reg_pp0_iter2; +wire [3:0] add_ln140_fu_432_p2; +wire ap_CS_fsm_state13; +wire [0:0] tmp_fu_415_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage1_subdone; +reg [7:0] ap_phi_mux_x_phi_fu_172_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_184_p4; +wire ap_block_pp0_stage1; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_196_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_208_p4; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_220_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_232_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_03_phi_fu_244_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_276; +wire ap_CS_fsm_state12; +reg [15:0] ap_phi_mux_phi_ln152_phi_fu_290_p8; +wire [2:0] trunc_ln140_fu_428_p1; +wire [63:0] zext_ln132_fu_327_p1; +wire [63:0] zext_ln136_fu_338_p1; +wire [63:0] zext_ln136_7_fu_349_p1; +wire [63:0] zext_ln136_8_fu_360_p1; +wire [63:0] zext_ln136_9_fu_371_p1; +wire [63:0] zext_ln136_10_fu_382_p1; +wire [63:0] zext_ln136_11_fu_399_p1; +wire [63:0] zext_ln136_12_fu_410_p1; +wire [63:0] zext_ln140_fu_423_p1; +wire [63:0] zext_ln140_2_fu_444_p1; +reg [15:0] grp_fu_305_p0; +reg [15:0] grp_fu_305_p1; +reg [15:0] grp_fu_310_p0; +reg [15:0] grp_fu_310_p1; +wire [7:0] or_ln136_fu_332_p2; +wire [7:0] or_ln136_7_fu_343_p2; +wire [7:0] or_ln136_8_fu_354_p2; +wire [7:0] or_ln136_9_fu_365_p2; +wire [7:0] or_ln136_10_fu_376_p2; +wire [7:0] or_ln136_11_fu_393_p2; +wire [7:0] or_ln136_12_fu_404_p2; +wire [2:0] or_ln140_fu_438_p2; +wire [0:0] icmp_ln152_fu_449_p2; +wire [0:0] icmp_ln152_3_fu_463_p2; +wire [15:0] select_ln152_fu_455_p3; +wire [0:0] icmp_ln152_4_fu_477_p2; +wire [15:0] select_ln152_3_fu_469_p3; +wire ap_CS_fsm_state14; +reg [7:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_514; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 8'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U220( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_305_p0), + .din1(grp_fu_305_p1), + .dout(grp_fu_305_p2) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U221( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_310_p0), + .din1(grp_fu_310_p1), + .dout(grp_fu_310_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + q_reg_276 <= 4'd0; + end else if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + q_reg_276 <= add_ln140_fu_432_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + x_reg_168 <= add_ln132_reg_546; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_168 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_load_36_reg_511 <= accum_in_0_q0; + accum_in_0_load_reg_506 <= accum_in_0_q1; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_load_37_reg_526 <= accum_in_0_q1; + accum_in_0_load_38_reg_531 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_load_39_reg_551 <= accum_in_0_q1; + accum_in_0_load_40_reg_556 <= accum_in_0_q0; + add_ln132_reg_546 <= add_ln132_fu_387_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_0_load_41_reg_571 <= accum_in_0_q1; + accum_in_0_load_42_reg_576 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln132_reg_492 <= icmp_ln132_fu_321_p2; + icmp_ln132_reg_492_pp0_iter1_reg <= icmp_ln132_reg_492; + icmp_ln132_reg_492_pp0_iter2_reg <= icmp_ln132_reg_492_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_0_01_reg_264 <= grp_fu_305_p2; + psum_1_02_reg_252 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_2_03_reg_240 <= grp_fu_305_p2; + psum_3_04_reg_228 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + psum_4_05_reg_216 <= grp_fu_305_p2; + psum_5_06_reg_204 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter2_reg == 1'd1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + psum_6_07_reg_192 <= grp_fu_305_p2; + psum_7_08_reg_180 <= grp_fu_310_p2; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address0 = zext_ln136_12_fu_410_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address0 = zext_ln136_10_fu_382_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address0 = zext_ln136_8_fu_360_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address0 = zext_ln136_fu_338_p1; + end else begin + accum_in_0_address0 = 'bx; + end + end else begin + accum_in_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address1 = zext_ln136_11_fu_399_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address1 = zext_ln136_9_fu_371_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address1 = zext_ln136_7_fu_349_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address1 = zext_ln132_fu_327_p1; + end else begin + accum_in_0_address1 = 'bx; + end + end else begin + accum_in_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln132_reg_492 == 1'd0)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + if ((trunc_ln140_fu_428_p1 == 3'd0)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_0_01_reg_264; + end else if ((1'b1 == ap_condition_514)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_6_07_reg_192; + end else if ((trunc_ln140_fu_428_p1 == 3'd4)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_4_05_reg_216; + end else if ((trunc_ln140_fu_428_p1 == 3'd2)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_2_03_reg_240; + end else begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_x_phi_fu_172_p4 = add_ln132_reg_546; + end else begin + ap_phi_mux_x_phi_fu_172_p4 = x_reg_168; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_6_07_phi_fu_196_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_4_05_phi_fu_220_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p0 = ap_phi_mux_psum_2_03_phi_fu_244_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p0 = grp_fu_305_p2; + end else begin + grp_fu_305_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p1 = accum_in_0_load_41_reg_571; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p1 = accum_in_0_load_39_reg_551; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p1 = accum_in_0_load_37_reg_526; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p1 = accum_in_0_load_reg_506; + end else begin + grp_fu_305_p1 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p0 = ap_phi_mux_psum_7_08_phi_fu_184_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p0 = ap_phi_mux_psum_5_06_phi_fu_208_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p0 = ap_phi_mux_psum_3_04_phi_fu_232_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p0 = grp_fu_310_p2; + end else begin + grp_fu_310_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p1 = accum_in_0_load_42_reg_576; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p1 = accum_in_0_load_40_reg_556; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p1 = accum_in_0_load_38_reg_531; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p1 = accum_in_0_load_36_reg_511; + end else begin + grp_fu_310_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (icmp_ln132_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (icmp_ln132_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_state14; + end + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln140_2_fu_444_p1; + +assign accum_out_address1 = zext_ln140_fu_423_p1; + +assign accum_out_d0 = ((icmp_ln152_4_fu_477_p2[0:0] == 1'b1) ? psum_5_06_reg_204 : select_ln152_3_fu_469_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln152_phi_fu_290_p8; + +assign add_ln132_fu_387_p2 = (x_reg_168 + 8'd8); + +assign add_ln140_fu_432_p2 = (q_reg_276 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_state14 = ap_CS_fsm[32'd7]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_514 = (~(trunc_ln140_fu_428_p1 == 3'd0) & ~(trunc_ln140_fu_428_p1 == 3'd4) & ~(trunc_ln140_fu_428_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_03_phi_fu_244_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_232_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_220_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_208_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_196_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_184_p4 = grp_fu_310_p2; + +assign icmp_ln132_fu_321_p2 = ((ap_phi_mux_x_phi_fu_172_p4 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln152_3_fu_463_p2 = ((or_ln140_fu_438_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln152_4_fu_477_p2 = ((or_ln140_fu_438_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln152_fu_449_p2 = ((or_ln140_fu_438_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln136_10_fu_376_p2 = (x_reg_168 | 8'd5); + +assign or_ln136_11_fu_393_p2 = (x_reg_168 | 8'd6); + +assign or_ln136_12_fu_404_p2 = (x_reg_168 | 8'd7); + +assign or_ln136_7_fu_343_p2 = (x_reg_168 | 8'd2); + +assign or_ln136_8_fu_354_p2 = (x_reg_168 | 8'd3); + +assign or_ln136_9_fu_365_p2 = (x_reg_168 | 8'd4); + +assign or_ln136_fu_332_p2 = (ap_phi_mux_x_phi_fu_172_p4 | 8'd1); + +assign or_ln140_fu_438_p2 = (trunc_ln140_fu_428_p1 | 3'd1); + +assign select_ln152_3_fu_469_p3 = ((icmp_ln152_3_fu_463_p2[0:0] == 1'b1) ? psum_3_04_reg_228 : select_ln152_fu_455_p3); + +assign select_ln152_fu_455_p3 = ((icmp_ln152_fu_449_p2[0:0] == 1'b1) ? psum_1_02_reg_252 : psum_7_08_reg_180); + +assign tmp_fu_415_p3 = q_reg_276[32'd3]; + +assign trunc_ln140_fu_428_p1 = q_reg_276[2:0]; + +assign zext_ln132_fu_327_p1 = ap_phi_mux_x_phi_fu_172_p4; + +assign zext_ln136_10_fu_382_p1 = or_ln136_10_fu_376_p2; + +assign zext_ln136_11_fu_399_p1 = or_ln136_11_fu_393_p2; + +assign zext_ln136_12_fu_410_p1 = or_ln136_12_fu_404_p2; + +assign zext_ln136_7_fu_349_p1 = or_ln136_7_fu_343_p2; + +assign zext_ln136_8_fu_360_p1 = or_ln136_8_fu_354_p2; + +assign zext_ln136_9_fu_371_p1 = or_ln136_9_fu_365_p2; + +assign zext_ln136_fu_338_p1 = or_ln136_fu_332_p2; + +assign zext_ln140_2_fu_444_p1 = or_ln140_fu_438_p2; + +assign zext_ln140_fu_423_p1 = q_reg_276; + +endmodule //td_fused_top_tdf4_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_12, + accum_in_12_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 7'd1; +parameter ap_ST_fsm_state2 = 7'd2; +parameter ap_ST_fsm_state3 = 7'd4; +parameter ap_ST_fsm_state4 = 7'd8; +parameter ap_ST_fsm_state5 = 7'd16; +parameter ap_ST_fsm_state6 = 7'd32; +parameter ap_ST_fsm_state7 = 7'd64; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_12; +output accum_in_12_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_12; +reg accum_in_12_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [6:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln164_fu_74_p2; +reg [3:0] add_ln164_reg_91; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln164_fu_85_p2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state7; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln164_fu_80_p1; +reg [15:0] accum_in_12_preg; +reg [6:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 7'd1; +#0 accum_in_12_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U224( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_q0), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_12_preg <= 16'd0; + end else begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_12_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + i_1_1_reg_44 <= add_ln164_reg_91; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln164_reg_91 <= add_ln164_fu_74_p2; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_12 = sum_01_reg_55; + end else begin + accum_in_12 = accum_in_12_preg; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_12_ap_vld = 1'b1; + end else begin + accum_in_12_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln164_fu_80_p1; + +assign add_ln164_fu_74_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln164_fu_85_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln164_fu_80_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf4_accum_2 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_adjustments_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 48; +parameter AWIDTH = 7; +parameter MEM_SIZE = 128; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_adjustments( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd48; +parameter AddressRange = 32'd128; +parameter AddressWidth = 32'd7; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf4_adjustments_ram td_fused_top_tdf4_adjustments_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + indices_23_out_din, + indices_23_out_full_n, + indices_23_out_write, + ap_return +); + +parameter ap_ST_fsm_state1 = 17'd1; +parameter ap_ST_fsm_state2 = 17'd2; +parameter ap_ST_fsm_state3 = 17'd4; +parameter ap_ST_fsm_state4 = 17'd8; +parameter ap_ST_fsm_state5 = 17'd16; +parameter ap_ST_fsm_state6 = 17'd32; +parameter ap_ST_fsm_state7 = 17'd64; +parameter ap_ST_fsm_state8 = 17'd128; +parameter ap_ST_fsm_state9 = 17'd256; +parameter ap_ST_fsm_state10 = 17'd512; +parameter ap_ST_fsm_state11 = 17'd1024; +parameter ap_ST_fsm_state12 = 17'd2048; +parameter ap_ST_fsm_state13 = 17'd4096; +parameter ap_ST_fsm_state14 = 17'd8192; +parameter ap_ST_fsm_state15 = 17'd16384; +parameter ap_ST_fsm_state16 = 17'd32768; +parameter ap_ST_fsm_state17 = 17'd65536; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_read; +output [6:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [10:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [10:0] indices_23_out_din; +input indices_23_out_full_n; +output indices_23_out_write; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg indices_23_read; +reg indices_23_out_write; + +reg ap_done_reg; + reg [16:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg indices_23_out_blk_n; +wire ap_CS_fsm_state4; +reg [15:0] tmp_53_i_i_reg_183; +reg [15:0] tmp_54_i_i_reg_188; +wire [15:0] grp_fu_93_p2; +reg [15:0] sub_i_i_i_reg_193; +wire ap_CS_fsm_state8; +wire ap_CS_fsm_state9; +wire [15:0] grp_fu_98_p2; +reg [15:0] mul_i_i_i_reg_203; +wire ap_CS_fsm_state12; +wire ap_CS_fsm_state13; +wire [63:0] zext_ln220_fu_106_p1; +reg ap_block_state1; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_89_p1; +wire [15:0] grp_fu_93_p1; +wire [15:0] grp_fu_98_p1; +wire [6:0] trunc_ln251_fu_102_p1; +wire [15:0] trunc_ln220_fu_111_p1; +wire [15:0] grp_fu_89_p2; +wire ap_CS_fsm_state17; +wire [15:0] bitcast_ln648_fu_148_p1; +wire [0:0] tmp_fu_152_p3; +reg [16:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 17'd1; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U228( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(mul_i_i_i_reg_203), + .din1(grp_fu_89_p1), + .dout(grp_fu_89_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U229( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sums_read), + .din1(grp_fu_93_p1), + .dout(grp_fu_93_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U230( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_193), + .din1(grp_fu_98_p1), + .dout(grp_fu_98_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + mul_i_i_i_reg_203 <= grp_fu_98_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sub_i_i_i_reg_193 <= grp_fu_93_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tmp_53_i_i_reg_183 <= {{adjustments_q0[31:16]}}; + tmp_54_i_i_reg_188 <= {{adjustments_q0[47:32]}}; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_out_blk_n = indices_23_out_full_n; + end else begin + indices_23_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_out_write = 1'b1; + end else begin + indices_23_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign adjustments_address0 = zext_ln220_fu_106_p1; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_return = ((tmp_fu_152_p3[0:0] == 1'b1) ? 16'd0 : grp_fu_89_p2); + +assign bitcast_ln648_fu_148_p1 = grp_fu_89_p2; + +assign grp_fu_89_p1 = tmp_54_i_i_reg_188; + +assign grp_fu_93_p1 = trunc_ln220_fu_111_p1; + +assign grp_fu_98_p1 = tmp_53_i_i_reg_183; + +assign indices_23_out_din = indices_23_dout; + +assign tmp_fu_152_p3 = bitcast_ln648_fu_148_p1[32'd15]; + +assign trunc_ln220_fu_111_p1 = adjustments_q0[15:0]; + +assign trunc_ln251_fu_102_p1 = indices_23_dout[6:0]; + +assign zext_ln220_fu_106_p1 = trunc_ln251_fu_102_p1; + +endmodule //td_fused_top_tdf4_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_q0, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [7:0] ifmap_vec_address0; +output ifmap_vec_ce0; +input [15:0] ifmap_vec_q0; +output [7:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +input [15:0] weight_vecs_0_q0; +output [7:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_ce0; +reg weight_vecs_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] indvar_flatten17_reg_97; +reg [6:0] indvar_flatten_reg_108; +reg [1:0] jj_reg_119; +reg [4:0] ic_reg_131; +reg [1:0] ii_reg_142; +wire [7:0] add_ln147_4_fu_157_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln147_fu_163_p2; +reg [0:0] icmp_ln147_reg_408; +reg [0:0] icmp_ln147_reg_408_pp0_iter1_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter2_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter3_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter4_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter5_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter6_reg; +wire [0:0] icmp_ln148_fu_169_p2; +reg [0:0] icmp_ln148_reg_412; +wire [0:0] and_ln147_fu_195_p2; +reg [0:0] and_ln147_reg_419; +wire [1:0] add_ln148_fu_201_p2; +reg [1:0] add_ln148_reg_424; +wire [4:0] select_ln148_fu_213_p3; +reg [4:0] select_ln148_reg_429; +wire [1:0] select_ln148_10_fu_221_p3; +reg [1:0] select_ln148_10_reg_434; +wire [3:0] trunc_ln150_fu_229_p1; +reg [3:0] trunc_ln150_reg_440; +reg [3:0] trunc_ln150_reg_440_pp0_iter1_reg; +reg [3:0] trunc_ln150_reg_440_pp0_iter2_reg; +reg [3:0] trunc_ln150_reg_440_pp0_iter3_reg; +reg [3:0] trunc_ln150_reg_440_pp0_iter4_reg; +reg [3:0] trunc_ln150_reg_440_pp0_iter5_reg; +reg [3:0] trunc_ln150_reg_440_pp0_iter6_reg; +wire [4:0] add_ln149_fu_233_p2; +wire [6:0] select_ln148_12_fu_245_p3; +wire [1:0] select_ln147_11_fu_287_p3; +reg [1:0] select_ln147_11_reg_455; +reg ap_enable_reg_pp0_iter1; +wire [3:0] select_ln148_11_fu_370_p3; +reg [3:0] select_ln148_11_reg_460; +reg [3:0] select_ln148_11_reg_460_pp0_iter2_reg; +reg [3:0] select_ln148_11_reg_460_pp0_iter3_reg; +reg [3:0] select_ln148_11_reg_460_pp0_iter4_reg; +reg [3:0] select_ln148_11_reg_460_pp0_iter5_reg; +reg [3:0] select_ln148_11_reg_460_pp0_iter6_reg; +reg [15:0] ifmap_vec_load_reg_475; +reg [15:0] weight_vecs_0_load_reg_480; +wire [15:0] grp_fu_153_p2; +reg [15:0] mul_reg_485; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg [1:0] ap_phi_mux_jj_phi_fu_123_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_146_p4; +wire [63:0] p_cast25_fu_386_p1; +wire [63:0] idxprom30_fu_398_p1; +wire [0:0] icmp_ln149_fu_189_p2; +wire [0:0] xor_ln147_fu_183_p2; +wire [1:0] select_ln147_fu_175_p3; +wire [0:0] or_ln148_fu_207_p2; +wire [6:0] add_ln148_4_fu_239_p2; +wire [3:0] shl_ln_fu_257_p3; +wire [3:0] zext_ln150_fu_253_p1; +wire [3:0] sub_ln150_fu_265_p2; +wire [3:0] zext_ln150_4_fu_271_p1; +wire [1:0] add_ln147_fu_281_p2; +wire [3:0] tmp_fu_298_p3; +wire [3:0] select_ln147_14_cast_fu_294_p1; +wire [3:0] shl_ln150_mid1_fu_316_p3; +wire [3:0] zext_ln150_8_fu_312_p1; +wire [3:0] sub_ln150_4_fu_324_p2; +wire [3:0] add_ln150_fu_275_p2; +wire [3:0] empty_98_fu_306_p2; +wire [3:0] select_ln148_13_cast_fu_344_p1; +wire [3:0] empty_99_fu_347_p2; +wire [3:0] select_ln147_12_fu_330_p3; +wire [3:0] zext_ln150_9_fu_361_p1; +wire [3:0] add_ln150_4_fu_364_p2; +wire [3:0] select_ln147_13_fu_337_p3; +wire [7:0] tmp_100_cast_fu_353_p3; +wire [7:0] select_ln148_cast_fu_377_p1; +wire [7:0] empty_100_fu_380_p2; +wire [7:0] p_fu_392_p3; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U216( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_load_reg_475), + .din1(weight_vecs_0_load_reg_480), + .dout(grp_fu_153_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_reg_131 <= add_ln149_fu_233_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_reg_131 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ii_reg_142 <= select_ln147_11_reg_455; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_142 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten17_reg_97 <= add_ln147_4_fu_157_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten17_reg_97 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_108 <= select_ln148_12_fu_245_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_108 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_119 <= select_ln148_10_reg_434; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_119 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln148_reg_424 <= add_ln148_fu_201_p2; + and_ln147_reg_419 <= and_ln147_fu_195_p2; + icmp_ln148_reg_412 <= icmp_ln148_fu_169_p2; + select_ln148_reg_429 <= select_ln148_fu_213_p3; + trunc_ln150_reg_440 <= trunc_ln150_fu_229_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln147_reg_408 <= icmp_ln147_fu_163_p2; + icmp_ln147_reg_408_pp0_iter1_reg <= icmp_ln147_reg_408; + trunc_ln150_reg_440_pp0_iter1_reg <= trunc_ln150_reg_440; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln147_reg_408_pp0_iter2_reg <= icmp_ln147_reg_408_pp0_iter1_reg; + icmp_ln147_reg_408_pp0_iter3_reg <= icmp_ln147_reg_408_pp0_iter2_reg; + icmp_ln147_reg_408_pp0_iter4_reg <= icmp_ln147_reg_408_pp0_iter3_reg; + icmp_ln147_reg_408_pp0_iter5_reg <= icmp_ln147_reg_408_pp0_iter4_reg; + icmp_ln147_reg_408_pp0_iter6_reg <= icmp_ln147_reg_408_pp0_iter5_reg; + select_ln148_11_reg_460_pp0_iter2_reg <= select_ln148_11_reg_460; + select_ln148_11_reg_460_pp0_iter3_reg <= select_ln148_11_reg_460_pp0_iter2_reg; + select_ln148_11_reg_460_pp0_iter4_reg <= select_ln148_11_reg_460_pp0_iter3_reg; + select_ln148_11_reg_460_pp0_iter5_reg <= select_ln148_11_reg_460_pp0_iter4_reg; + select_ln148_11_reg_460_pp0_iter6_reg <= select_ln148_11_reg_460_pp0_iter5_reg; + trunc_ln150_reg_440_pp0_iter2_reg <= trunc_ln150_reg_440_pp0_iter1_reg; + trunc_ln150_reg_440_pp0_iter3_reg <= trunc_ln150_reg_440_pp0_iter2_reg; + trunc_ln150_reg_440_pp0_iter4_reg <= trunc_ln150_reg_440_pp0_iter3_reg; + trunc_ln150_reg_440_pp0_iter5_reg <= trunc_ln150_reg_440_pp0_iter4_reg; + trunc_ln150_reg_440_pp0_iter6_reg <= trunc_ln150_reg_440_pp0_iter5_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_load_reg_475 <= ifmap_vec_q0; + weight_vecs_0_load_reg_480 <= weight_vecs_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_reg_485 <= grp_fu_153_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + select_ln147_11_reg_455 <= select_ln147_11_fu_287_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_10_reg_434 <= select_ln148_10_fu_221_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_11_reg_460 <= select_ln148_11_fu_370_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_fu_163_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_146_p4 = select_ln147_11_reg_455; + end else begin + ap_phi_mux_ii_phi_fu_146_p4 = ii_reg_142; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_123_p4 = select_ln148_10_reg_434; + end else begin + ap_phi_mux_jj_phi_fu_123_p4 = jj_reg_119; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_4_fu_157_p2 = (indvar_flatten17_reg_97 + 8'd1); + +assign add_ln147_fu_281_p2 = (ap_phi_mux_ii_phi_fu_146_p4 + 2'd1); + +assign add_ln148_4_fu_239_p2 = (indvar_flatten_reg_108 + 7'd1); + +assign add_ln148_fu_201_p2 = (select_ln147_fu_175_p3 + 2'd1); + +assign add_ln149_fu_233_p2 = (select_ln148_fu_213_p3 + 5'd1); + +assign add_ln150_4_fu_364_p2 = (select_ln147_12_fu_330_p3 + zext_ln150_9_fu_361_p1); + +assign add_ln150_fu_275_p2 = (sub_ln150_fu_265_p2 + zext_ln150_4_fu_271_p1); + +assign and_ln147_fu_195_p2 = (xor_ln147_fu_183_p2 & icmp_ln149_fu_189_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign empty_100_fu_380_p2 = (tmp_100_cast_fu_353_p3 + select_ln148_cast_fu_377_p1); + +assign empty_98_fu_306_p2 = (tmp_fu_298_p3 - select_ln147_14_cast_fu_294_p1); + +assign empty_99_fu_347_p2 = (empty_98_fu_306_p2 + select_ln148_13_cast_fu_344_p1); + +assign icmp_ln147_fu_163_p2 = ((indvar_flatten17_reg_97 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln148_fu_169_p2 = ((indvar_flatten_reg_108 == 7'd48) ? 1'b1 : 1'b0); + +assign icmp_ln149_fu_189_p2 = ((ic_reg_131 == 5'd16) ? 1'b1 : 1'b0); + +assign idxprom30_fu_398_p1 = p_fu_392_p3; + +assign ifmap_vec_address0 = p_cast25_fu_386_p1; + +assign or_ln148_fu_207_p2 = (icmp_ln148_fu_169_p2 | and_ln147_fu_195_p2); + +assign p_cast25_fu_386_p1 = empty_100_fu_380_p2; + +assign p_fu_392_p3 = {{select_ln148_11_reg_460_pp0_iter6_reg}, {trunc_ln150_reg_440_pp0_iter6_reg}}; + +assign products_0_address0 = idxprom30_fu_398_p1; + +assign products_0_d0 = mul_reg_485; + +assign select_ln147_11_fu_287_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? add_ln147_fu_281_p2 : ap_phi_mux_ii_phi_fu_146_p4); + +assign select_ln147_12_fu_330_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? sub_ln150_4_fu_324_p2 : sub_ln150_fu_265_p2); + +assign select_ln147_13_fu_337_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? sub_ln150_4_fu_324_p2 : add_ln150_fu_275_p2); + +assign select_ln147_14_cast_fu_294_p1 = select_ln147_11_fu_287_p3; + +assign select_ln147_fu_175_p3 = ((icmp_ln148_fu_169_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_123_p4); + +assign select_ln148_10_fu_221_p3 = ((and_ln147_fu_195_p2[0:0] == 1'b1) ? add_ln148_fu_201_p2 : select_ln147_fu_175_p3); + +assign select_ln148_11_fu_370_p3 = ((and_ln147_reg_419[0:0] == 1'b1) ? add_ln150_4_fu_364_p2 : select_ln147_13_fu_337_p3); + +assign select_ln148_12_fu_245_p3 = ((icmp_ln148_fu_169_p2[0:0] == 1'b1) ? 7'd1 : add_ln148_4_fu_239_p2); + +assign select_ln148_13_cast_fu_344_p1 = select_ln148_10_reg_434; + +assign select_ln148_cast_fu_377_p1 = select_ln148_reg_429; + +assign select_ln148_fu_213_p3 = ((or_ln148_fu_207_p2[0:0] == 1'b1) ? 5'd0 : ic_reg_131); + +assign shl_ln150_mid1_fu_316_p3 = {{add_ln147_fu_281_p2}, {2'd0}}; + +assign shl_ln_fu_257_p3 = {{ap_phi_mux_ii_phi_fu_146_p4}, {2'd0}}; + +assign sub_ln150_4_fu_324_p2 = (shl_ln150_mid1_fu_316_p3 - zext_ln150_8_fu_312_p1); + +assign sub_ln150_fu_265_p2 = (shl_ln_fu_257_p3 - zext_ln150_fu_253_p1); + +assign tmp_100_cast_fu_353_p3 = {{empty_99_fu_347_p2}, {4'd0}}; + +assign tmp_fu_298_p3 = {{select_ln147_11_fu_287_p3}, {2'd0}}; + +assign trunc_ln150_fu_229_p1 = select_ln148_fu_213_p3[3:0]; + +assign weight_vecs_0_address0 = p_cast25_fu_386_p1; + +assign xor_ln147_fu_183_p2 = (icmp_ln148_fu_169_p2 ^ 1'd1); + +assign zext_ln150_4_fu_271_p1 = jj_reg_119; + +assign zext_ln150_8_fu_312_p1 = add_ln147_fu_281_p2; + +assign zext_ln150_9_fu_361_p1 = add_ln148_reg_424; + +assign zext_ln150_fu_253_p1 = ap_phi_mux_ii_phi_fu_146_p4; + +endmodule //td_fused_top_tdf4_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 15; +parameter MEM_SIZE = 18432; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd18432; +parameter AddressWidth = 32'd15; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf4_filters_ram td_fused_top_tdf4_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + indices_2_out_din, + indices_2_out_full_n, + indices_2_out_write, + indices_2_out1_din, + indices_2_out1_full_n, + indices_2_out1_write, + write_r_din, + write_r_full_n, + write_r_write +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [6:0] indices_2_out_din; +input indices_2_out_full_n; +output indices_2_out_write; +output [10:0] indices_2_out1_din; +input indices_2_out1_full_n; +output indices_2_out1_write; +output write_r_din; +input write_r_full_n; +output write_r_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg indices_0_write; +reg indices_1_write; +reg indices_2_out_write; +reg indices_2_out1_write; +reg write_r_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [15:0] i_4; +reg [15:0] j_4; +reg [15:0] k_4; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg indices_2_out_blk_n; +reg indices_2_out1_blk_n; +reg write_r_blk_n; +reg [0:0] ap_phi_mux_j_15_flag_0_i_phi_fu_92_p6; +reg ap_block_state1; +wire [0:0] icmp_ln188_fu_167_p2; +wire [0:0] icmp_ln191_fu_180_p2; +reg [15:0] ap_phi_mux_j_15_new_0_i_phi_fu_106_p6; +wire [15:0] add_ln190_fu_173_p2; +reg [15:0] ap_phi_mux_k_15_new_0_i_phi_fu_119_p6; +wire [15:0] add_ln187_fu_160_p2; +wire [15:0] select_ln194_fu_198_p3; +wire [15:0] add_ln193_fu_186_p2; +wire [0:0] icmp_ln194_fu_192_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_4 = 16'd0; +#0 j_4 = 16'd0; +#0 k_4 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln191_fu_180_p2 == 1'd1) & (icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_4 <= select_ln194_fu_198_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_15_flag_0_i_phi_fu_92_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j_4 <= ap_phi_mux_j_15_new_0_i_phi_fu_106_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k_4 <= ap_phi_mux_k_15_new_0_i_phi_fu_119_p6; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln188_fu_167_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_15_flag_0_i_phi_fu_92_p6 = 1'd0; + end else if ((((icmp_ln191_fu_180_p2 == 1'd0) & (icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln191_fu_180_p2 == 1'd1) & (icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_15_flag_0_i_phi_fu_92_p6 = 1'd1; + end else begin + ap_phi_mux_j_15_flag_0_i_phi_fu_92_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln191_fu_180_p2 == 1'd0)) begin + ap_phi_mux_j_15_new_0_i_phi_fu_106_p6 = add_ln190_fu_173_p2; + end else if ((icmp_ln191_fu_180_p2 == 1'd1)) begin + ap_phi_mux_j_15_new_0_i_phi_fu_106_p6 = 16'd0; + end else begin + ap_phi_mux_j_15_new_0_i_phi_fu_106_p6 = 'bx; + end + end else begin + ap_phi_mux_j_15_new_0_i_phi_fu_106_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln188_fu_167_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_15_new_0_i_phi_fu_119_p6 = add_ln187_fu_160_p2; + end else if ((((icmp_ln191_fu_180_p2 == 1'd0) & (icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln191_fu_180_p2 == 1'd1) & (icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_15_new_0_i_phi_fu_119_p6 = 16'd0; + end else begin + ap_phi_mux_k_15_new_0_i_phi_fu_119_p6 = 'bx; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_blk_n = indices_2_out1_full_n; + end else begin + indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_write = 1'b1; + end else begin + indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_blk_n = indices_2_out_full_n; + end else begin + indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_write = 1'b1; + end else begin + indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_r_blk_n = write_r_full_n; + end else begin + write_r_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_r_write = 1'b1; + end else begin + write_r_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln187_fu_160_p2 = (k_4 + 16'd1); + +assign add_ln190_fu_173_p2 = (j_4 + 16'd1); + +assign add_ln193_fu_186_p2 = (i_4 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign icmp_ln188_fu_167_p2 = ((add_ln187_fu_160_p2 == 16'd128) ? 1'b1 : 1'b0); + +assign icmp_ln191_fu_180_p2 = ((add_ln190_fu_173_p2 == 16'd56) ? 1'b1 : 1'b0); + +assign icmp_ln194_fu_192_p2 = ((add_ln193_fu_186_p2 == 16'd56) ? 1'b1 : 1'b0); + +assign indices_0_din = i_4; + +assign indices_1_din = j_4; + +assign indices_2_out1_din = k_4[10:0]; + +assign indices_2_out_din = k_4[6:0]; + +assign select_ln194_fu_198_p3 = ((icmp_ln194_fu_192_p2[0:0] == 1'b1) ? 16'd0 : add_ln193_fu_186_p2); + +assign start_out = real_start; + +assign write_r_din = ((k_4 == 16'd127) ? 1'b1 : 1'b0); + +endmodule //td_fused_top_tdf4_get_next_ijk +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_l2_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 11; +parameter MEM_SIZE = 2048; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_l2_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd2048; +parameter AddressWidth = 32'd11; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf4_l2_filters_ram td_fused_top_tdf4_l2_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_l2_multiply34 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + intermediate_fmaps_read, + l2_filter_data_address0, + l2_filter_data_ce0, + l2_filter_data_q0, + l2_products_address0, + l2_products_ce0, + l2_products_we0, + l2_products_d0, + indices_23_dout, + indices_23_empty_n, + indices_23_read +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] intermediate_fmaps_read; +output [10:0] l2_filter_data_address0; +output l2_filter_data_ce0; +input [15:0] l2_filter_data_q0; +output [3:0] l2_products_address0; +output l2_products_ce0; +output l2_products_we0; +output [15:0] l2_products_d0; +input [10:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg l2_filter_data_ce0; +reg l2_products_ce0; +reg l2_products_we0; +reg indices_23_read; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [4:0] i_1_1_reg_106; +reg [10:0] l2_ichan_reg_165; +wire [4:0] add_ln20_fu_122_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln20_fu_128_p2; +reg [0:0] icmp_ln20_reg_175; +reg [0:0] icmp_ln20_reg_175_pp0_iter1_reg; +reg [0:0] icmp_ln20_reg_175_pp0_iter2_reg; +reg [0:0] icmp_ln20_reg_175_pp0_iter3_reg; +reg [0:0] icmp_ln20_reg_175_pp0_iter4_reg; +reg [0:0] icmp_ln20_reg_175_pp0_iter5_reg; +reg [0:0] icmp_ln20_reg_175_pp0_iter6_reg; +wire [3:0] l2_o_fu_134_p1; +reg [3:0] l2_o_reg_179; +reg [3:0] l2_o_reg_179_pp0_iter1_reg; +reg [3:0] l2_o_reg_179_pp0_iter2_reg; +reg [3:0] l2_o_reg_179_pp0_iter3_reg; +reg [3:0] l2_o_reg_179_pp0_iter4_reg; +reg [3:0] l2_o_reg_179_pp0_iter5_reg; +reg [3:0] l2_o_reg_179_pp0_iter6_reg; +wire [15:0] grp_fu_117_p2; +reg [15:0] mul_i_i_reg_194; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +wire [63:0] zext_ln29_13_fu_151_p1; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln29_fu_156_p1; +wire [10:0] tmp_s_fu_138_p3; +wire [10:0] add_ln29_fu_146_p2; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U235( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(l2_filter_data_q0), + .din1(intermediate_fmaps_read), + .dout(grp_fu_117_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_106 <= 5'd0; + end else if (((icmp_ln20_fu_128_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + i_1_1_reg_106 <= add_ln20_fu_122_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln20_reg_175 <= icmp_ln20_fu_128_p2; + icmp_ln20_reg_175_pp0_iter1_reg <= icmp_ln20_reg_175; + l2_o_reg_179_pp0_iter1_reg <= l2_o_reg_179; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln20_reg_175_pp0_iter2_reg <= icmp_ln20_reg_175_pp0_iter1_reg; + icmp_ln20_reg_175_pp0_iter3_reg <= icmp_ln20_reg_175_pp0_iter2_reg; + icmp_ln20_reg_175_pp0_iter4_reg <= icmp_ln20_reg_175_pp0_iter3_reg; + icmp_ln20_reg_175_pp0_iter5_reg <= icmp_ln20_reg_175_pp0_iter4_reg; + icmp_ln20_reg_175_pp0_iter6_reg <= icmp_ln20_reg_175_pp0_iter5_reg; + l2_o_reg_179_pp0_iter2_reg <= l2_o_reg_179_pp0_iter1_reg; + l2_o_reg_179_pp0_iter3_reg <= l2_o_reg_179_pp0_iter2_reg; + l2_o_reg_179_pp0_iter4_reg <= l2_o_reg_179_pp0_iter3_reg; + l2_o_reg_179_pp0_iter5_reg <= l2_o_reg_179_pp0_iter4_reg; + l2_o_reg_179_pp0_iter6_reg <= l2_o_reg_179_pp0_iter5_reg; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + l2_ichan_reg_165 <= indices_23_dout; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln20_fu_128_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + l2_o_reg_179 <= l2_o_fu_134_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln20_reg_175_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_i_i_reg_194 <= grp_fu_117_p2; + end +end + +always @ (*) begin + if ((icmp_ln20_fu_128_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + l2_filter_data_ce0 = 1'b1; + end else begin + l2_filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + l2_products_ce0 = 1'b1; + end else begin + l2_products_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln20_reg_175_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + l2_products_we0 = 1'b1; + end else begin + l2_products_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln20_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln20_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln20_fu_122_p2 = (i_1_1_reg_106 + 5'd1); + +assign add_ln29_fu_146_p2 = (tmp_s_fu_138_p3 + l2_ichan_reg_165); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign icmp_ln20_fu_128_p2 = ((i_1_1_reg_106 == 5'd16) ? 1'b1 : 1'b0); + +assign l2_filter_data_address0 = zext_ln29_13_fu_151_p1; + +assign l2_o_fu_134_p1 = i_1_1_reg_106[3:0]; + +assign l2_products_address0 = zext_ln29_fu_156_p1; + +assign l2_products_d0 = mul_i_i_reg_194; + +assign tmp_s_fu_138_p3 = {{l2_o_fu_134_p1}, {7'd0}}; + +assign zext_ln29_13_fu_151_p1 = add_ln29_fu_146_p2; + +assign zext_ln29_fu_156_p1 = l2_o_reg_179_pp0_iter6_reg; + +endmodule //td_fused_top_tdf4_l2_multiply34 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_l2_writeOutputs_133_running_sums_1_ram (addr0, ce0, d0, we0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 4; +parameter MEM_SIZE = 16; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf4_l2_writeOutputs_133_running_sums_1_ram.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf4_l2_writeOutputs_133_running_sums_1( + reset, + clk, + address0, + ce0, + we0, + d0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd16; +parameter AddressWidth = 32'd4; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_tdf4_l2_writeOutputs_133_running_sums_1_ram td_fused_top_tdf4_l2_writeOutputs_133_running_sums_1_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_l2_writeOutputs_133 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + write4_dout, + write4_empty_n, + write4_read, + l2_partial_sums_address0, + l2_partial_sums_ce0, + l2_partial_sums_q0, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_q0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state25 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [5:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [11:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [0:0] write4_dout; +input write4_empty_n; +output write4_read; +output [3:0] l2_partial_sums_address0; +output l2_partial_sums_ce0; +input [15:0] l2_partial_sums_q0; +output [13:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; +output [3:0] l2_adjustments_address0; +output l2_adjustments_ce0; +input [47:0] l2_adjustments_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg write4_read; +reg l2_partial_sums_ce0; +reg out_data_ce1; +reg out_data_we1; +reg l2_adjustments_ce0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg running_sums_1_ce0; +reg running_sums_1_we0; +wire [15:0] running_sums_1_d0; +wire [3:0] running_sums_1_address1; +reg running_sums_1_ce1; +wire [15:0] running_sums_1_q1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg write4_blk_n; +reg [4:0] ochan_reg_208; +reg [0:0] write4_read_reg_567; +wire [13:0] add_ln109_fu_273_p2; +reg [13:0] add_ln109_reg_573; +wire [4:0] add_ln86_fu_279_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_state13_pp0_stage0_iter11; +wire ap_block_state14_pp0_stage0_iter12; +wire ap_block_state15_pp0_stage0_iter13; +wire ap_block_state16_pp0_stage0_iter14; +wire ap_block_state17_pp0_stage0_iter15; +wire ap_block_state18_pp0_stage0_iter16; +wire ap_block_state19_pp0_stage0_iter17; +wire ap_block_state20_pp0_stage0_iter18; +wire ap_block_state21_pp0_stage0_iter19; +wire ap_block_state22_pp0_stage0_iter20; +wire ap_block_state23_pp0_stage0_iter21; +wire ap_block_state24_pp0_stage0_iter22; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln86_fu_285_p2; +wire [63:0] zext_ln86_fu_291_p1; +reg [63:0] zext_ln86_reg_587; +reg [63:0] zext_ln86_reg_587_pp0_iter1_reg; +reg [63:0] zext_ln86_reg_587_pp0_iter2_reg; +reg [63:0] zext_ln86_reg_587_pp0_iter3_reg; +reg [3:0] running_sums_1_addr_reg_597; +reg [3:0] running_sums_1_addr_reg_597_pp0_iter1_reg; +reg [3:0] running_sums_1_addr_reg_597_pp0_iter2_reg; +reg [3:0] running_sums_1_addr_reg_597_pp0_iter3_reg; +reg [3:0] running_sums_1_addr_reg_597_pp0_iter4_reg; +reg [3:0] running_sums_1_addr_reg_597_pp0_iter5_reg; +reg [3:0] running_sums_1_addr_reg_597_pp0_iter6_reg; +wire [1:0] trunc_ln99_fu_297_p1; +reg [1:0] trunc_ln99_reg_603; +reg [1:0] trunc_ln99_reg_603_pp0_iter1_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter2_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter3_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter4_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter5_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter6_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter7_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter8_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter9_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter10_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter11_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter12_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter13_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter14_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter15_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter16_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter17_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter18_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter19_reg; +reg [1:0] trunc_ln99_reg_603_pp0_iter20_reg; +wire [0:0] and_ln103_fu_307_p2; +reg [0:0] and_ln103_reg_610; +reg [0:0] and_ln103_reg_610_pp0_iter1_reg; +reg [0:0] and_ln103_reg_610_pp0_iter2_reg; +reg [0:0] and_ln103_reg_610_pp0_iter3_reg; +reg [0:0] and_ln103_reg_610_pp0_iter4_reg; +reg [0:0] and_ln103_reg_610_pp0_iter5_reg; +reg [0:0] and_ln103_reg_610_pp0_iter6_reg; +reg [0:0] and_ln103_reg_610_pp0_iter7_reg; +reg [0:0] and_ln103_reg_610_pp0_iter8_reg; +reg [0:0] and_ln103_reg_610_pp0_iter9_reg; +reg [0:0] and_ln103_reg_610_pp0_iter10_reg; +reg [0:0] and_ln103_reg_610_pp0_iter11_reg; +reg [0:0] and_ln103_reg_610_pp0_iter12_reg; +reg [0:0] and_ln103_reg_610_pp0_iter13_reg; +reg [0:0] and_ln103_reg_610_pp0_iter14_reg; +reg [0:0] and_ln103_reg_610_pp0_iter15_reg; +reg [0:0] and_ln103_reg_610_pp0_iter16_reg; +reg [0:0] and_ln103_reg_610_pp0_iter17_reg; +reg [0:0] and_ln103_reg_610_pp0_iter18_reg; +reg [0:0] and_ln103_reg_610_pp0_iter19_reg; +reg [0:0] and_ln103_reg_610_pp0_iter20_reg; +reg [1:0] lshr_ln_reg_614; +reg [1:0] lshr_ln_reg_614_pp0_iter1_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter2_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter3_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter4_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter5_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter6_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter7_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter8_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter9_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter10_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter11_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter12_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter13_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter14_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter15_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter16_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter17_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter18_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter19_reg; +reg [1:0] lshr_ln_reg_614_pp0_iter20_reg; +reg [15:0] val_reg_619; +reg [15:0] running_sums_1_load_reg_624; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_219_p2; +reg [15:0] sum_reg_634; +reg [15:0] tmp_47_i_i_reg_645; +reg [15:0] tmp_47_i_i_reg_645_pp0_iter8_reg; +reg [15:0] tmp_47_i_i_reg_645_pp0_iter9_reg; +reg [15:0] tmp_47_i_i_reg_645_pp0_iter10_reg; +reg [15:0] tmp_47_i_i_reg_645_pp0_iter11_reg; +reg [15:0] tmp_48_i_i_reg_650; +reg [15:0] tmp_48_i_i_reg_650_pp0_iter8_reg; +reg [15:0] tmp_48_i_i_reg_650_pp0_iter9_reg; +reg [15:0] tmp_48_i_i_reg_650_pp0_iter10_reg; +reg [15:0] tmp_48_i_i_reg_650_pp0_iter11_reg; +reg [15:0] tmp_48_i_i_reg_650_pp0_iter12_reg; +reg [15:0] tmp_48_i_i_reg_650_pp0_iter13_reg; +reg [15:0] tmp_48_i_i_reg_650_pp0_iter14_reg; +reg [15:0] tmp_48_i_i_reg_650_pp0_iter15_reg; +wire [15:0] grp_fu_227_p2; +reg [15:0] sub_i_i_i_reg_655; +wire [15:0] grp_fu_231_p2; +reg [15:0] normalized_reg_665; +wire [15:0] grp_fu_223_p2; +reg [15:0] biased_reg_675; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_enable_reg_pp0_iter22; +wire ap_block_pp0_stage0; +wire [63:0] sext_ln109_fu_509_p1; +reg [15:0] quad_3_14_fu_114; +wire [15:0] quad_3_26_fu_475_p3; +reg [15:0] quad_3_15_fu_118; +wire [15:0] quad_3_25_fu_467_p3; +reg [15:0] quad_3_16_fu_122; +wire [15:0] quad_3_23_fu_451_p3; +reg [15:0] quad_3_17_fu_126; +wire [15:0] quad_3_20_fu_427_p3; +wire [15:0] grp_fu_223_p1; +wire [15:0] grp_fu_227_p1; +wire [15:0] grp_fu_231_p1; +wire [11:0] tmp_fu_235_p3; +wire [8:0] tmp_s_fu_247_p3; +wire [12:0] zext_ln109_fu_243_p1; +wire [12:0] zext_ln109_3_fu_255_p1; +wire [12:0] sub_ln109_fu_259_p2; +wire [13:0] sub_ln109_cast_fu_265_p1; +wire [13:0] zext_ln109_4_fu_269_p1; +wire [0:0] icmp_ln103_fu_301_p2; +wire [15:0] trunc_ln95_fu_329_p1; +wire [15:0] data_V_fu_378_p1; +wire [0:0] p_Result_s_fu_381_p3; +wire [0:0] icmp_ln99_fu_396_p2; +wire [15:0] quad_0_fu_389_p3; +wire [0:0] icmp_ln99_3_fu_409_p2; +wire [15:0] quad_3_fu_401_p3; +wire [0:0] icmp_ln99_4_fu_422_p2; +wire [15:0] quad_3_19_fu_414_p3; +wire [15:0] quad_3_21_fu_435_p3; +wire [15:0] quad_3_22_fu_443_p3; +wire [15:0] quad_3_24_fu_459_p3; +wire [15:0] tmp_34_fu_503_p3; +wire [15:0] bitcast_ln109_6_fu_526_p1; +wire [15:0] bitcast_ln109_5_fu_522_p1; +wire [15:0] bitcast_ln109_4_fu_518_p1; +wire [15:0] bitcast_ln109_fu_514_p1; +wire ap_CS_fsm_state25; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +end + +td_fused_top_tdf4_l2_writeOutputs_133_running_sums_1 #( + .DataWidth( 16 ), + .AddressRange( 16 ), + .AddressWidth( 4 )) +running_sums_1_U( + .reset(ap_rst), + .clk(ap_clk), + .address0(running_sums_1_addr_reg_597_pp0_iter6_reg), + .ce0(running_sums_1_ce0), + .we0(running_sums_1_we0), + .d0(running_sums_1_d0), + .address1(running_sums_1_address1), + .ce1(running_sums_1_ce1), + .q1(running_sums_1_q1) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U240( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(running_sums_1_load_reg_624), + .din1(val_reg_619), + .dout(grp_fu_219_p2) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U241( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(normalized_reg_665), + .din1(grp_fu_223_p1), + .dout(grp_fu_223_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U242( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_reg_634), + .din1(grp_fu_227_p1), + .dout(grp_fu_227_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U243( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_655), + .din1(grp_fu_231_p1), + .dout(grp_fu_231_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end else if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_285_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ochan_reg_208 <= add_ln86_fu_279_p2; + end else if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ochan_reg_208 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + add_ln109_reg_573 <= add_ln109_fu_273_p2; + write4_read_reg_567 <= write4_dout; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_285_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + and_ln103_reg_610 <= and_ln103_fu_307_p2; + running_sums_1_addr_reg_597 <= zext_ln86_fu_291_p1; + trunc_ln99_reg_603 <= trunc_ln99_fu_297_p1; + zext_ln86_reg_587[4 : 0] <= zext_ln86_fu_291_p1[4 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + and_ln103_reg_610_pp0_iter10_reg <= and_ln103_reg_610_pp0_iter9_reg; + and_ln103_reg_610_pp0_iter11_reg <= and_ln103_reg_610_pp0_iter10_reg; + and_ln103_reg_610_pp0_iter12_reg <= and_ln103_reg_610_pp0_iter11_reg; + and_ln103_reg_610_pp0_iter13_reg <= and_ln103_reg_610_pp0_iter12_reg; + and_ln103_reg_610_pp0_iter14_reg <= and_ln103_reg_610_pp0_iter13_reg; + and_ln103_reg_610_pp0_iter15_reg <= and_ln103_reg_610_pp0_iter14_reg; + and_ln103_reg_610_pp0_iter16_reg <= and_ln103_reg_610_pp0_iter15_reg; + and_ln103_reg_610_pp0_iter17_reg <= and_ln103_reg_610_pp0_iter16_reg; + and_ln103_reg_610_pp0_iter18_reg <= and_ln103_reg_610_pp0_iter17_reg; + and_ln103_reg_610_pp0_iter19_reg <= and_ln103_reg_610_pp0_iter18_reg; + and_ln103_reg_610_pp0_iter20_reg <= and_ln103_reg_610_pp0_iter19_reg; + and_ln103_reg_610_pp0_iter2_reg <= and_ln103_reg_610_pp0_iter1_reg; + and_ln103_reg_610_pp0_iter3_reg <= and_ln103_reg_610_pp0_iter2_reg; + and_ln103_reg_610_pp0_iter4_reg <= and_ln103_reg_610_pp0_iter3_reg; + and_ln103_reg_610_pp0_iter5_reg <= and_ln103_reg_610_pp0_iter4_reg; + and_ln103_reg_610_pp0_iter6_reg <= and_ln103_reg_610_pp0_iter5_reg; + and_ln103_reg_610_pp0_iter7_reg <= and_ln103_reg_610_pp0_iter6_reg; + and_ln103_reg_610_pp0_iter8_reg <= and_ln103_reg_610_pp0_iter7_reg; + and_ln103_reg_610_pp0_iter9_reg <= and_ln103_reg_610_pp0_iter8_reg; + biased_reg_675 <= grp_fu_223_p2; + lshr_ln_reg_614_pp0_iter10_reg <= lshr_ln_reg_614_pp0_iter9_reg; + lshr_ln_reg_614_pp0_iter11_reg <= lshr_ln_reg_614_pp0_iter10_reg; + lshr_ln_reg_614_pp0_iter12_reg <= lshr_ln_reg_614_pp0_iter11_reg; + lshr_ln_reg_614_pp0_iter13_reg <= lshr_ln_reg_614_pp0_iter12_reg; + lshr_ln_reg_614_pp0_iter14_reg <= lshr_ln_reg_614_pp0_iter13_reg; + lshr_ln_reg_614_pp0_iter15_reg <= lshr_ln_reg_614_pp0_iter14_reg; + lshr_ln_reg_614_pp0_iter16_reg <= lshr_ln_reg_614_pp0_iter15_reg; + lshr_ln_reg_614_pp0_iter17_reg <= lshr_ln_reg_614_pp0_iter16_reg; + lshr_ln_reg_614_pp0_iter18_reg <= lshr_ln_reg_614_pp0_iter17_reg; + lshr_ln_reg_614_pp0_iter19_reg <= lshr_ln_reg_614_pp0_iter18_reg; + lshr_ln_reg_614_pp0_iter20_reg <= lshr_ln_reg_614_pp0_iter19_reg; + lshr_ln_reg_614_pp0_iter2_reg <= lshr_ln_reg_614_pp0_iter1_reg; + lshr_ln_reg_614_pp0_iter3_reg <= lshr_ln_reg_614_pp0_iter2_reg; + lshr_ln_reg_614_pp0_iter4_reg <= lshr_ln_reg_614_pp0_iter3_reg; + lshr_ln_reg_614_pp0_iter5_reg <= lshr_ln_reg_614_pp0_iter4_reg; + lshr_ln_reg_614_pp0_iter6_reg <= lshr_ln_reg_614_pp0_iter5_reg; + lshr_ln_reg_614_pp0_iter7_reg <= lshr_ln_reg_614_pp0_iter6_reg; + lshr_ln_reg_614_pp0_iter8_reg <= lshr_ln_reg_614_pp0_iter7_reg; + lshr_ln_reg_614_pp0_iter9_reg <= lshr_ln_reg_614_pp0_iter8_reg; + normalized_reg_665 <= grp_fu_231_p2; + running_sums_1_addr_reg_597_pp0_iter2_reg <= running_sums_1_addr_reg_597_pp0_iter1_reg; + running_sums_1_addr_reg_597_pp0_iter3_reg <= running_sums_1_addr_reg_597_pp0_iter2_reg; + running_sums_1_addr_reg_597_pp0_iter4_reg <= running_sums_1_addr_reg_597_pp0_iter3_reg; + running_sums_1_addr_reg_597_pp0_iter5_reg <= running_sums_1_addr_reg_597_pp0_iter4_reg; + running_sums_1_addr_reg_597_pp0_iter6_reg <= running_sums_1_addr_reg_597_pp0_iter5_reg; + sub_i_i_i_reg_655 <= grp_fu_227_p2; + sum_reg_634 <= grp_fu_219_p2; + tmp_47_i_i_reg_645 <= {{l2_adjustments_q0[31:16]}}; + tmp_47_i_i_reg_645_pp0_iter10_reg <= tmp_47_i_i_reg_645_pp0_iter9_reg; + tmp_47_i_i_reg_645_pp0_iter11_reg <= tmp_47_i_i_reg_645_pp0_iter10_reg; + tmp_47_i_i_reg_645_pp0_iter8_reg <= tmp_47_i_i_reg_645; + tmp_47_i_i_reg_645_pp0_iter9_reg <= tmp_47_i_i_reg_645_pp0_iter8_reg; + tmp_48_i_i_reg_650 <= {{l2_adjustments_q0[47:32]}}; + tmp_48_i_i_reg_650_pp0_iter10_reg <= tmp_48_i_i_reg_650_pp0_iter9_reg; + tmp_48_i_i_reg_650_pp0_iter11_reg <= tmp_48_i_i_reg_650_pp0_iter10_reg; + tmp_48_i_i_reg_650_pp0_iter12_reg <= tmp_48_i_i_reg_650_pp0_iter11_reg; + tmp_48_i_i_reg_650_pp0_iter13_reg <= tmp_48_i_i_reg_650_pp0_iter12_reg; + tmp_48_i_i_reg_650_pp0_iter14_reg <= tmp_48_i_i_reg_650_pp0_iter13_reg; + tmp_48_i_i_reg_650_pp0_iter15_reg <= tmp_48_i_i_reg_650_pp0_iter14_reg; + tmp_48_i_i_reg_650_pp0_iter8_reg <= tmp_48_i_i_reg_650; + tmp_48_i_i_reg_650_pp0_iter9_reg <= tmp_48_i_i_reg_650_pp0_iter8_reg; + trunc_ln99_reg_603_pp0_iter10_reg <= trunc_ln99_reg_603_pp0_iter9_reg; + trunc_ln99_reg_603_pp0_iter11_reg <= trunc_ln99_reg_603_pp0_iter10_reg; + trunc_ln99_reg_603_pp0_iter12_reg <= trunc_ln99_reg_603_pp0_iter11_reg; + trunc_ln99_reg_603_pp0_iter13_reg <= trunc_ln99_reg_603_pp0_iter12_reg; + trunc_ln99_reg_603_pp0_iter14_reg <= trunc_ln99_reg_603_pp0_iter13_reg; + trunc_ln99_reg_603_pp0_iter15_reg <= trunc_ln99_reg_603_pp0_iter14_reg; + trunc_ln99_reg_603_pp0_iter16_reg <= trunc_ln99_reg_603_pp0_iter15_reg; + trunc_ln99_reg_603_pp0_iter17_reg <= trunc_ln99_reg_603_pp0_iter16_reg; + trunc_ln99_reg_603_pp0_iter18_reg <= trunc_ln99_reg_603_pp0_iter17_reg; + trunc_ln99_reg_603_pp0_iter19_reg <= trunc_ln99_reg_603_pp0_iter18_reg; + trunc_ln99_reg_603_pp0_iter20_reg <= trunc_ln99_reg_603_pp0_iter19_reg; + trunc_ln99_reg_603_pp0_iter2_reg <= trunc_ln99_reg_603_pp0_iter1_reg; + trunc_ln99_reg_603_pp0_iter3_reg <= trunc_ln99_reg_603_pp0_iter2_reg; + trunc_ln99_reg_603_pp0_iter4_reg <= trunc_ln99_reg_603_pp0_iter3_reg; + trunc_ln99_reg_603_pp0_iter5_reg <= trunc_ln99_reg_603_pp0_iter4_reg; + trunc_ln99_reg_603_pp0_iter6_reg <= trunc_ln99_reg_603_pp0_iter5_reg; + trunc_ln99_reg_603_pp0_iter7_reg <= trunc_ln99_reg_603_pp0_iter6_reg; + trunc_ln99_reg_603_pp0_iter8_reg <= trunc_ln99_reg_603_pp0_iter7_reg; + trunc_ln99_reg_603_pp0_iter9_reg <= trunc_ln99_reg_603_pp0_iter8_reg; + zext_ln86_reg_587_pp0_iter2_reg[4 : 0] <= zext_ln86_reg_587_pp0_iter1_reg[4 : 0]; + zext_ln86_reg_587_pp0_iter3_reg[4 : 0] <= zext_ln86_reg_587_pp0_iter2_reg[4 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + and_ln103_reg_610_pp0_iter1_reg <= and_ln103_reg_610; + lshr_ln_reg_614_pp0_iter1_reg <= lshr_ln_reg_614; + running_sums_1_addr_reg_597_pp0_iter1_reg <= running_sums_1_addr_reg_597; + trunc_ln99_reg_603_pp0_iter1_reg <= trunc_ln99_reg_603; + val_reg_619 <= l2_partial_sums_q0; + zext_ln86_reg_587_pp0_iter1_reg[4 : 0] <= zext_ln86_reg_587[4 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((1'd1 == and_ln103_fu_307_p2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_285_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + lshr_ln_reg_614 <= {{ochan_reg_208[3:2]}}; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + quad_3_14_fu_114 <= quad_3_26_fu_475_p3; + quad_3_15_fu_118 <= quad_3_25_fu_467_p3; + quad_3_16_fu_122 <= quad_3_23_fu_451_p3; + quad_3_17_fu_126 <= quad_3_20_fu_427_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_1_load_reg_624 <= running_sums_1_q1; + end +end + +always @ (*) begin + if ((icmp_ln86_fu_285_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter6 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter5 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter4 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + l2_adjustments_ce0 = 1'b1; + end else begin + l2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_partial_sums_ce0 = 1'b1; + end else begin + l2_partial_sums_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter22 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter21 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (1'd1 == and_ln103_reg_610_pp0_iter20_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_1_ce0 = 1'b1; + end else begin + running_sums_1_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_1_ce1 = 1'b1; + end else begin + running_sums_1_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_1_we0 = 1'b1; + end else begin + running_sums_1_we0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write4_blk_n = write4_empty_n; + end else begin + write4_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write4_read = 1'b1; + end else begin + write4_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln86_fu_285_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((ap_enable_reg_pp0_iter22 == 1'b1) & (ap_enable_reg_pp0_iter21 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln86_fu_285_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter22 == 1'b1) & (ap_enable_reg_pp0_iter21 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_state25; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state25 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln109_fu_273_p2 = ((sub_ln109_cast_fu_265_p1) + (zext_ln109_4_fu_269_p1)); + +assign add_ln86_fu_279_p2 = (ochan_reg_208 + 5'd1); + +assign and_ln103_fu_307_p2 = (write4_read_reg_567 & icmp_ln103_fu_301_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state25 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln109_4_fu_518_p1 = quad_3_25_fu_467_p3; + +assign bitcast_ln109_5_fu_522_p1 = quad_3_23_fu_451_p3; + +assign bitcast_ln109_6_fu_526_p1 = quad_3_20_fu_427_p3; + +assign bitcast_ln109_fu_514_p1 = quad_3_26_fu_475_p3; + +assign data_V_fu_378_p1 = biased_reg_675; + +assign grp_fu_223_p1 = tmp_48_i_i_reg_650_pp0_iter15_reg; + +assign grp_fu_227_p1 = trunc_ln95_fu_329_p1; + +assign grp_fu_231_p1 = tmp_47_i_i_reg_645_pp0_iter11_reg; + +assign icmp_ln103_fu_301_p2 = ((trunc_ln99_fu_297_p1 == 2'd3) ? 1'b1 : 1'b0); + +assign icmp_ln86_fu_285_p2 = ((ochan_reg_208 == 5'd16) ? 1'b1 : 1'b0); + +assign icmp_ln99_3_fu_409_p2 = ((trunc_ln99_reg_603_pp0_iter20_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln99_4_fu_422_p2 = ((trunc_ln99_reg_603_pp0_iter20_reg == 2'd0) ? 1'b1 : 1'b0); + +assign icmp_ln99_fu_396_p2 = ((trunc_ln99_reg_603_pp0_iter20_reg == 2'd2) ? 1'b1 : 1'b0); + +assign l2_adjustments_address0 = zext_ln86_reg_587_pp0_iter3_reg; + +assign l2_partial_sums_address0 = zext_ln86_fu_291_p1; + +assign out_data_address1 = sext_ln109_fu_509_p1; + +assign out_data_d1 = {{{{bitcast_ln109_6_fu_526_p1}, {bitcast_ln109_5_fu_522_p1}}, {bitcast_ln109_4_fu_518_p1}}, {bitcast_ln109_fu_514_p1}}; + +assign p_Result_s_fu_381_p3 = data_V_fu_378_p1[32'd15]; + +assign quad_0_fu_389_p3 = ((p_Result_s_fu_381_p3[0:0] == 1'b1) ? 16'd0 : biased_reg_675); + +assign quad_3_19_fu_414_p3 = ((icmp_ln99_3_fu_409_p2[0:0] == 1'b1) ? quad_3_17_fu_126 : quad_3_fu_401_p3); + +assign quad_3_20_fu_427_p3 = ((icmp_ln99_4_fu_422_p2[0:0] == 1'b1) ? quad_3_17_fu_126 : quad_3_19_fu_414_p3); + +assign quad_3_21_fu_435_p3 = ((icmp_ln99_fu_396_p2[0:0] == 1'b1) ? quad_0_fu_389_p3 : quad_3_16_fu_122); + +assign quad_3_22_fu_443_p3 = ((icmp_ln99_3_fu_409_p2[0:0] == 1'b1) ? quad_3_16_fu_122 : quad_3_21_fu_435_p3); + +assign quad_3_23_fu_451_p3 = ((icmp_ln99_4_fu_422_p2[0:0] == 1'b1) ? quad_3_16_fu_122 : quad_3_22_fu_443_p3); + +assign quad_3_24_fu_459_p3 = ((icmp_ln99_3_fu_409_p2[0:0] == 1'b1) ? quad_0_fu_389_p3 : quad_3_15_fu_118); + +assign quad_3_25_fu_467_p3 = ((icmp_ln99_4_fu_422_p2[0:0] == 1'b1) ? quad_3_15_fu_118 : quad_3_24_fu_459_p3); + +assign quad_3_26_fu_475_p3 = ((icmp_ln99_4_fu_422_p2[0:0] == 1'b1) ? quad_0_fu_389_p3 : quad_3_14_fu_114); + +assign quad_3_fu_401_p3 = ((icmp_ln99_fu_396_p2[0:0] == 1'b1) ? quad_3_17_fu_126 : quad_0_fu_389_p3); + +assign running_sums_1_address1 = zext_ln86_fu_291_p1; + +assign running_sums_1_d0 = ((write4_read_reg_567[0:0] == 1'b1) ? 16'd0 : sum_reg_634); + +assign sext_ln109_fu_509_p1 = (tmp_34_fu_503_p3); + +assign sub_ln109_cast_fu_265_p1 = (sub_ln109_fu_259_p2); + +assign sub_ln109_fu_259_p2 = (zext_ln109_fu_243_p1 - zext_ln109_3_fu_255_p1); + +assign tmp_34_fu_503_p3 = {{add_ln109_reg_573}, {lshr_ln_reg_614_pp0_iter20_reg}}; + +assign tmp_fu_235_p3 = {{indices_01_dout}, {6'd0}}; + +assign tmp_s_fu_247_p3 = {{indices_01_dout}, {3'd0}}; + +assign trunc_ln95_fu_329_p1 = l2_adjustments_q0[15:0]; + +assign trunc_ln99_fu_297_p1 = ochan_reg_208[1:0]; + +assign zext_ln109_3_fu_255_p1 = tmp_s_fu_247_p3; + +assign zext_ln109_4_fu_269_p1 = indices_12_dout; + +assign zext_ln109_fu_243_p1 = tmp_fu_235_p3; + +assign zext_ln86_fu_291_p1 = ochan_reg_208; + +always @ (posedge ap_clk) begin + zext_ln86_reg_587[63:5] <= 59'b00000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_587_pp0_iter1_reg[63:5] <= 59'b00000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_587_pp0_iter2_reg[63:5] <= 59'b00000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_587_pp0_iter3_reg[63:5] <= 59'b00000000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf4_l2_writeOutputs_133 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_readFilters36 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_we0, + weight_vecs_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state7 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [14:0] filter_data_address0; +output filter_data_ce0; +input [15:0] filter_data_q0; +input [6:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [7:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +output weight_vecs_0_we0; +output [15:0] weight_vecs_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg indices_23_read; +reg weight_vecs_0_ce0; +reg weight_vecs_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [7:0] indvar_flatten13_reg_123; +reg [1:0] ii_reg_134; +reg [6:0] indvar_flatten_reg_145; +reg [1:0] jj_reg_156; +reg [4:0] kk_reg_167; +wire [10:0] sext_ln47_fu_200_p1; +reg [10:0] sext_ln47_reg_408; +wire [7:0] add_ln47_4_fu_204_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln47_fu_210_p2; +reg [0:0] icmp_ln47_reg_418; +reg [0:0] icmp_ln47_reg_418_pp0_iter1_reg; +reg [0:0] icmp_ln47_reg_418_pp0_iter2_reg; +reg [0:0] icmp_ln47_reg_418_pp0_iter3_reg; +wire [0:0] icmp_ln48_fu_222_p2; +reg [0:0] icmp_ln48_reg_422; +wire [1:0] select_ln47_4_fu_228_p3; +reg [1:0] select_ln47_4_reg_429; +wire [6:0] select_ln48_8_fu_242_p3; +wire [1:0] select_ln48_7_fu_329_p3; +reg [1:0] select_ln48_7_reg_442; +reg ap_enable_reg_pp0_iter1; +wire [7:0] add_ln55_16_fu_392_p2; +reg [7:0] add_ln55_16_reg_452; +reg [7:0] add_ln55_16_reg_452_pp0_iter2_reg; +reg [7:0] add_ln55_16_reg_452_pp0_iter3_reg; +wire [4:0] add_ln49_fu_398_p2; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg [1:0] ap_phi_mux_ii_phi_fu_138_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_160_p4; +wire [63:0] zext_ln55_37_fu_387_p1; +wire [63:0] zext_ln55_38_fu_404_p1; +wire [8:0] tmp_fu_182_p3; +wire [9:0] zext_ln55_30_fu_190_p1; +wire [9:0] zext_ln55_fu_178_p1; +wire [9:0] sub_ln55_fu_194_p2; +wire [1:0] add_ln47_fu_216_p2; +wire [6:0] add_ln48_4_fu_236_p2; +wire [10:0] zext_ln55_32_fu_260_p1; +wire [10:0] add_ln55_fu_263_p2; +wire [10:0] shl_ln55_fu_268_p2; +wire [3:0] tmp_s_fu_280_p3; +wire [3:0] zext_ln55_31_fu_257_p1; +wire [0:0] icmp_ln49_fu_298_p2; +wire [0:0] xor_ln47_fu_293_p2; +wire [1:0] select_ln47_fu_250_p3; +wire [0:0] and_ln47_fu_304_p2; +wire [0:0] or_ln48_fu_316_p2; +wire [1:0] add_ln48_fu_310_p2; +wire [10:0] sub_ln55_7_fu_274_p2; +wire [10:0] zext_ln55_34_fu_341_p1; +wire [10:0] add_ln55_13_fu_345_p2; +wire [3:0] sub_ln55_8_fu_287_p2; +wire [3:0] zext_ln55_33_fu_337_p1; +wire [3:0] add_ln55_14_fu_359_p2; +wire [4:0] select_ln48_fu_321_p3; +wire [14:0] tmp_91_cast_fu_351_p3; +wire [14:0] zext_ln55_36_fu_377_p1; +wire [14:0] add_ln55_15_fu_381_p2; +wire [7:0] tmp_93_cast_fu_365_p3; +wire [7:0] zext_ln55_35_fu_373_p1; +wire ap_CS_fsm_state7; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ii_reg_134 <= select_ln47_4_reg_429; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_134 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten13_reg_123 <= add_ln47_4_fu_204_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_123 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_145 <= select_ln48_8_fu_242_p3; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_145 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_418_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + jj_reg_156 <= select_ln48_7_reg_442; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_156 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_reg_167 <= add_ln49_fu_398_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_167 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln55_16_reg_452 <= add_ln55_16_fu_392_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln55_16_reg_452_pp0_iter2_reg <= add_ln55_16_reg_452; + add_ln55_16_reg_452_pp0_iter3_reg <= add_ln55_16_reg_452_pp0_iter2_reg; + icmp_ln47_reg_418_pp0_iter2_reg <= icmp_ln47_reg_418_pp0_iter1_reg; + icmp_ln47_reg_418_pp0_iter3_reg <= icmp_ln47_reg_418_pp0_iter2_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln47_reg_418 <= icmp_ln47_fu_210_p2; + icmp_ln47_reg_418_pp0_iter1_reg <= icmp_ln47_reg_418; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln48_reg_422 <= icmp_ln48_fu_222_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln47_4_reg_429 <= select_ln47_4_fu_228_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln48_7_reg_442 <= select_ln48_7_fu_329_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sext_ln47_reg_408 <= sext_ln47_fu_200_p1; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln47_fu_210_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_138_p4 = select_ln47_4_reg_429; + end else begin + ap_phi_mux_ii_phi_fu_138_p4 = ii_reg_134; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_418_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_160_p4 = select_ln48_7_reg_442; + end else begin + ap_phi_mux_jj_phi_fu_160_p4 = jj_reg_156; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_418_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + weight_vecs_0_we0 = 1'b1; + end else begin + weight_vecs_0_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln47_4_fu_204_p2 = (indvar_flatten13_reg_123 + 8'd1); + +assign add_ln47_fu_216_p2 = (ap_phi_mux_ii_phi_fu_138_p4 + 2'd1); + +assign add_ln48_4_fu_236_p2 = (indvar_flatten_reg_145 + 7'd1); + +assign add_ln48_fu_310_p2 = (select_ln47_fu_250_p3 + 2'd1); + +assign add_ln49_fu_398_p2 = (select_ln48_fu_321_p3 + 5'd1); + +assign add_ln55_13_fu_345_p2 = (sub_ln55_7_fu_274_p2 + zext_ln55_34_fu_341_p1); + +assign add_ln55_14_fu_359_p2 = (sub_ln55_8_fu_287_p2 + zext_ln55_33_fu_337_p1); + +assign add_ln55_15_fu_381_p2 = (tmp_91_cast_fu_351_p3 + zext_ln55_36_fu_377_p1); + +assign add_ln55_16_fu_392_p2 = (tmp_93_cast_fu_365_p3 + zext_ln55_35_fu_373_p1); + +assign add_ln55_fu_263_p2 = ((sext_ln47_reg_408) + (zext_ln55_32_fu_260_p1)); + +assign and_ln47_fu_304_p2 = (xor_ln47_fu_293_p2 & icmp_ln49_fu_298_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_address0 = zext_ln55_37_fu_387_p1; + +assign icmp_ln47_fu_210_p2 = ((indvar_flatten13_reg_123 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln48_fu_222_p2 = ((indvar_flatten_reg_145 == 7'd48) ? 1'b1 : 1'b0); + +assign icmp_ln49_fu_298_p2 = ((kk_reg_167 == 5'd16) ? 1'b1 : 1'b0); + +assign or_ln48_fu_316_p2 = (icmp_ln48_reg_422 | and_ln47_fu_304_p2); + +assign select_ln47_4_fu_228_p3 = ((icmp_ln48_fu_222_p2[0:0] == 1'b1) ? add_ln47_fu_216_p2 : ap_phi_mux_ii_phi_fu_138_p4); + +assign select_ln47_fu_250_p3 = ((icmp_ln48_reg_422[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_160_p4); + +assign select_ln48_7_fu_329_p3 = ((and_ln47_fu_304_p2[0:0] == 1'b1) ? add_ln48_fu_310_p2 : select_ln47_fu_250_p3); + +assign select_ln48_8_fu_242_p3 = ((icmp_ln48_fu_222_p2[0:0] == 1'b1) ? 7'd1 : add_ln48_4_fu_236_p2); + +assign select_ln48_fu_321_p3 = ((or_ln48_fu_316_p2[0:0] == 1'b1) ? 5'd0 : kk_reg_167); + +assign sext_ln47_fu_200_p1 = (sub_ln55_fu_194_p2); + +assign shl_ln55_fu_268_p2 = add_ln55_fu_263_p2 << 11'd2; + +assign sub_ln55_7_fu_274_p2 = (shl_ln55_fu_268_p2 - add_ln55_fu_263_p2); + +assign sub_ln55_8_fu_287_p2 = (tmp_s_fu_280_p3 - zext_ln55_31_fu_257_p1); + +assign sub_ln55_fu_194_p2 = (zext_ln55_30_fu_190_p1 - zext_ln55_fu_178_p1); + +assign tmp_91_cast_fu_351_p3 = {{add_ln55_13_fu_345_p2}, {4'd0}}; + +assign tmp_93_cast_fu_365_p3 = {{add_ln55_14_fu_359_p2}, {4'd0}}; + +assign tmp_fu_182_p3 = {{indices_23_dout}, {2'd0}}; + +assign tmp_s_fu_280_p3 = {{select_ln47_4_reg_429}, {2'd0}}; + +assign weight_vecs_0_address0 = zext_ln55_38_fu_404_p1; + +assign weight_vecs_0_d0 = filter_data_q0; + +assign xor_ln47_fu_293_p2 = (icmp_ln48_reg_422 ^ 1'd1); + +assign zext_ln55_30_fu_190_p1 = tmp_fu_182_p3; + +assign zext_ln55_31_fu_257_p1 = select_ln47_4_reg_429; + +assign zext_ln55_32_fu_260_p1 = select_ln47_4_reg_429; + +assign zext_ln55_33_fu_337_p1 = select_ln48_7_fu_329_p3; + +assign zext_ln55_34_fu_341_p1 = select_ln48_7_fu_329_p3; + +assign zext_ln55_35_fu_373_p1 = select_ln48_fu_321_p3; + +assign zext_ln55_36_fu_377_p1 = select_ln48_fu_321_p3; + +assign zext_ln55_37_fu_387_p1 = add_ln55_15_fu_381_p2; + +assign zext_ln55_38_fu_404_p1 = add_ln55_16_reg_452_pp0_iter3_reg; + +assign zext_ln55_fu_178_p1 = indices_23_dout; + +endmodule //td_fused_top_tdf4_readFilters36 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf4_readInputs37 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_we0, + ifmap_vec_d0, + ifmap_vec_address1, + ifmap_vec_ce1, + ifmap_vec_we1, + ifmap_vec_d1, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 5'd1; +parameter ap_ST_fsm_state2 = 5'd2; +parameter ap_ST_fsm_pp0_stage0 = 5'd4; +parameter ap_ST_fsm_pp0_stage1 = 5'd8; +parameter ap_ST_fsm_state9 = 5'd16; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [13:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [7:0] ifmap_vec_address0; +output ifmap_vec_ce0; +output ifmap_vec_we0; +output [15:0] ifmap_vec_d0; +output [7:0] ifmap_vec_address1; +output ifmap_vec_ce1; +output ifmap_vec_we1; +output [15:0] ifmap_vec_d1; +output [5:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [11:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg[7:0] ifmap_vec_address0; +reg ifmap_vec_ce0; +reg ifmap_vec_we0; +reg[15:0] ifmap_vec_d0; +reg[7:0] ifmap_vec_address1; +reg ifmap_vec_ce1; +reg ifmap_vec_we1; +reg[15:0] ifmap_vec_d1; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [4:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [5:0] indvar_flatten47_reg_224; +reg [1:0] ii_reg_236; +reg [4:0] indvar_flatten_reg_248; +reg [1:0] jj_reg_259; +reg [4:0] kk_0_i_i_reg_271; +reg [15:0] indices_01_read_reg_959; +wire [5:0] trunc_ln250_fu_282_p1; +reg [5:0] trunc_ln250_reg_964; +reg [15:0] indices_12_read_reg_969; +wire [11:0] empty_fu_287_p1; +reg [11:0] empty_reg_974; +wire [17:0] p_cast_i_i_fu_304_p1; +reg [17:0] p_cast_i_i_reg_981; +wire ap_CS_fsm_state2; +wire [17:0] sext_ln22_fu_314_p1; +reg [17:0] sext_ln22_reg_987; +wire [5:0] p_cast_fu_318_p2; +reg [5:0] p_cast_reg_993; +wire [0:0] or_ln23_16_fu_337_p2; +reg [0:0] or_ln23_16_reg_999; +wire [11:0] p_mid137_fu_343_p2; +reg [11:0] p_mid137_reg_1004; +wire [5:0] p_cast5_i_i_fu_361_p2; +reg [5:0] p_cast5_i_i_reg_1009; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state5_pp0_stage0_iter1; +wire ap_block_state7_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [0:0] is_padding_fu_401_p2; +reg [0:0] is_padding_reg_1015; +wire [0:0] icmp_ln19_fu_407_p2; +reg [0:0] icmp_ln19_reg_1022; +reg [0:0] icmp_ln19_reg_1022_pp0_iter1_reg; +reg [0:0] icmp_ln19_reg_1022_pp0_iter2_reg; +wire [1:0] add_ln19_fu_413_p2; +reg [1:0] add_ln19_reg_1026; +wire [0:0] icmp_ln20_fu_419_p2; +reg [0:0] icmp_ln20_reg_1031; +wire [1:0] select_ln19_fu_425_p3; +reg [1:0] select_ln19_reg_1043; +wire [5:0] p_cast5_i_i_mid1_fu_446_p2; +reg [5:0] p_cast5_i_i_mid1_reg_1048; +wire [0:0] or_ln23_18_fu_465_p2; +reg [0:0] or_ln23_18_reg_1054; +wire [1:0] add_ln20_fu_470_p2; +reg [1:0] add_ln20_reg_1061; +wire [0:0] or_ln23_20_fu_505_p2; +reg [0:0] or_ln23_20_reg_1067; +wire [4:0] add_ln20_4_fu_511_p2; +reg [4:0] add_ln20_4_reg_1074; +wire [5:0] add_ln19_4_fu_517_p2; +reg [5:0] add_ln19_4_reg_1079; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state4_pp0_stage1_iter0; +wire ap_block_state6_pp0_stage1_iter1; +wire ap_block_state8_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +wire [1:0] select_ln19_19_fu_555_p3; +reg [1:0] select_ln19_19_reg_1084; +wire [4:0] select_ln20_fu_619_p3; +reg [4:0] select_ln20_reg_1091; +wire [1:0] select_ln20_16_fu_627_p3; +reg [1:0] select_ln20_16_reg_1097; +wire [0:0] select_ln20_17_fu_636_p3; +reg [0:0] select_ln20_17_reg_1103; +reg [0:0] select_ln20_17_reg_1103_pp0_iter1_reg; +wire [3:0] empty_97_fu_732_p1; +reg [3:0] empty_97_reg_1111; +reg [3:0] empty_97_reg_1111_pp0_iter1_reg; +wire [4:0] select_ln20_20_fu_759_p3; +reg [4:0] select_ln20_20_reg_1123; +wire [4:0] add_ln25_fu_765_p2; +reg [4:0] add_ln25_reg_1128; +reg ap_enable_reg_pp0_iter1; +wire [5:0] add_ln33_fu_797_p2; +reg [5:0] add_ln33_reg_1133; +wire [7:0] add_ln33_4_fu_818_p2; +reg [7:0] add_ln33_4_reg_1140; +wire [15:0] select_ln33_17_fu_897_p3; +reg [15:0] select_ln33_17_reg_1145; +wire [15:0] select_ln33_18_fu_918_p3; +reg [15:0] select_ln33_18_reg_1150; +wire ap_block_pp0_stage1_subdone; +reg ap_condition_pp0_exit_iter0_state4; +reg ap_enable_reg_pp0_iter2; +reg [5:0] ap_phi_mux_indvar_flatten47_phi_fu_228_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_240_p4; +reg [4:0] ap_phi_mux_indvar_flatten_phi_fu_252_p4; +reg [1:0] ap_phi_mux_jj_phi_fu_263_p4; +reg [4:0] ap_phi_mux_kk_0_i_i_phi_fu_275_p4; +wire ap_block_pp0_stage1; +wire [63:0] sext_ln32_fu_754_p1; +wire [63:0] zext_ln33_17_fu_824_p1; +wire [63:0] sext_ln33_fu_856_p1; +wire [63:0] sext_ln33_7_fu_937_p1; +wire [63:0] sext_ln33_8_fu_954_p1; +reg ap_block_state1; +wire [15:0] select_ln33_fu_836_p3; +wire [15:0] select_ln33_16_fu_875_p3; +wire [16:0] zext_ln19_fu_295_p1; +wire [16:0] empty_92_fu_298_p2; +wire [16:0] j_cast_i_i_fu_292_p1; +wire [16:0] add_ln22_fu_308_p2; +wire [0:0] tmp_26_fu_323_p3; +wire [0:0] icmp_ln24_fu_331_p2; +wire [17:0] ii_cast_i_i_fu_348_p1; +wire [5:0] ii_cast_fu_352_p1; +wire [17:0] empty_93_fu_356_p2; +wire [17:0] zext_ln20_fu_372_p1; +wire [17:0] add_ln22_4_fu_376_p2; +wire [0:0] tmp_27_fu_381_p3; +wire [0:0] icmp_ln24_4_fu_389_p2; +wire [0:0] or_ln23_fu_395_p2; +wire [0:0] empty_94_fu_366_p2; +wire [17:0] ii_cast_i_i_mid1_fu_433_p1; +wire [5:0] ii_cast_mid1_fu_437_p1; +wire [17:0] p_mid111_fu_441_p2; +wire [0:0] p_mid113_fu_451_p2; +wire [17:0] zext_ln20_4_fu_476_p1; +wire [17:0] add_ln22_5_fu_480_p2; +wire [0:0] tmp_28_fu_485_p3; +wire [0:0] icmp_ln24_5_fu_493_p2; +wire [0:0] or_ln23_19_fu_499_p2; +wire [0:0] select_ln19_21_fu_457_p3; +wire [2:0] zext_ln22_fu_523_p1; +wire [2:0] tmp1_fu_533_p2; +wire [11:0] tmp1_cast_fu_539_p1; +wire [11:0] empty_95_fu_543_p2; +wire [5:0] row_coord_int_mid131_fu_571_p3; +wire [5:0] row_coord_int_fu_527_p3; +wire [11:0] col_coord_int_mid139_fu_577_p3; +wire [11:0] col_coord_int_fu_548_p3; +wire [0:0] icmp_ln25_fu_602_p2; +wire [0:0] xor_ln19_fu_597_p2; +wire [0:0] and_ln19_fu_608_p2; +wire [0:0] or_ln20_fu_614_p2; +wire [0:0] select_ln19_22_fu_566_p3; +wire [5:0] select_ln19_20_fu_561_p3; +wire [2:0] zext_ln22_4_fu_633_p1; +wire [2:0] tmp1_mid1_fu_650_p2; +wire [11:0] tmp1_cast_mid1_fu_656_p1; +wire [11:0] p_mid1_fu_660_p2; +wire [5:0] row_coord_int_mid1_fu_643_p3; +wire [5:0] select_ln19_23_fu_583_p3; +wire [5:0] select_ln20_18_fu_672_p3; +wire [11:0] tmp_s_fu_680_p3; +wire [8:0] tmp_6_fu_692_p3; +wire [12:0] zext_ln32_fu_688_p1; +wire [12:0] zext_ln32_18_fu_700_p1; +wire [12:0] sub_ln32_fu_704_p2; +wire [11:0] col_coord_int_mid1_fu_665_p3; +wire [11:0] select_ln19_24_fu_590_p3; +wire [11:0] select_ln20_19_fu_714_p3; +wire [13:0] sext_ln20_fu_710_p1; +wire [13:0] zext_ln32_19_fu_722_p1; +wire [13:0] add_ln32_fu_726_p2; +wire [1:0] lshr_ln_fu_736_p4; +wire [15:0] tmp_29_fu_746_p3; +wire [3:0] tmp_fu_773_p3; +wire [4:0] zext_ln33_14_fu_780_p1; +wire [4:0] zext_ln33_fu_770_p1; +wire [4:0] sub_ln33_fu_784_p2; +wire [5:0] sub_ln33_cast_fu_790_p1; +wire [5:0] zext_ln33_15_fu_794_p1; +wire [3:0] trunc_ln33_fu_803_p1; +wire [7:0] tmp_80_cast_fu_807_p3; +wire [7:0] zext_ln33_16_fu_815_p1; +wire [15:0] trunc_ln32_fu_828_p1; +wire [15:0] bitcast_ln32_fu_832_p1; +wire [3:0] or_ln25_fu_844_p2; +wire [9:0] tmp_30_fu_849_p3; +wire [15:0] tmp_44_i_i_fu_861_p4; +wire [15:0] bitcast_ln32_16_fu_871_p1; +wire [15:0] tmp_45_i_i_fu_883_p4; +wire [15:0] bitcast_ln32_17_fu_893_p1; +wire [15:0] tmp_46_i_i_fu_904_p4; +wire [15:0] bitcast_ln32_18_fu_914_p1; +wire [3:0] or_ln25_11_fu_925_p2; +wire [9:0] tmp_31_fu_930_p3; +wire [3:0] or_ln25_12_fu_942_p2; +wire [9:0] tmp_32_fu_947_p3; +wire ap_CS_fsm_state9; +reg [4:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 5'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state4)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state4); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1022 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_236 <= select_ln19_19_reg_1084; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ii_reg_236 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1022 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + indvar_flatten47_reg_224 <= add_ln19_4_reg_1079; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + indvar_flatten47_reg_224 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1022 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + indvar_flatten_reg_248 <= select_ln20_20_reg_1123; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + indvar_flatten_reg_248 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1022 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_259 <= select_ln20_16_reg_1097; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + jj_reg_259 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1022_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + kk_0_i_i_reg_271 <= add_ln25_reg_1128; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + kk_0_i_i_reg_271 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + add_ln19_4_reg_1079 <= add_ln19_4_fu_517_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_407_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln19_reg_1026 <= add_ln19_fu_413_p2; + add_ln20_4_reg_1074 <= add_ln20_4_fu_511_p2; + add_ln20_reg_1061 <= add_ln20_fu_470_p2; + icmp_ln20_reg_1031 <= icmp_ln20_fu_419_p2; + or_ln23_18_reg_1054 <= or_ln23_18_fu_465_p2; + or_ln23_20_reg_1067 <= or_ln23_20_fu_505_p2; + p_cast5_i_i_mid1_reg_1048 <= p_cast5_i_i_mid1_fu_446_p2; + select_ln19_reg_1043 <= select_ln19_fu_425_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1022 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln25_reg_1128 <= add_ln25_fu_765_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1022_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + add_ln33_4_reg_1140 <= add_ln33_4_fu_818_p2; + add_ln33_reg_1133 <= add_ln33_fu_797_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1022 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + empty_97_reg_1111 <= empty_97_fu_732_p1; + select_ln20_17_reg_1103 <= select_ln20_17_fu_636_p3; + select_ln20_reg_1091 <= select_ln20_fu_619_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + empty_97_reg_1111_pp0_iter1_reg <= empty_97_reg_1111; + select_ln20_17_reg_1103_pp0_iter1_reg <= select_ln20_17_reg_1103; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + empty_reg_974 <= empty_fu_287_p1; + indices_01_read_reg_959 <= indices_01_dout; + indices_12_read_reg_969 <= indices_12_dout; + trunc_ln250_reg_964 <= trunc_ln250_fu_282_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln19_reg_1022 <= icmp_ln19_fu_407_p2; + icmp_ln19_reg_1022_pp0_iter1_reg <= icmp_ln19_reg_1022; + icmp_ln19_reg_1022_pp0_iter2_reg <= icmp_ln19_reg_1022_pp0_iter1_reg; + is_padding_reg_1015 <= is_padding_fu_401_p2; + p_cast5_i_i_reg_1009 <= p_cast5_i_i_fu_361_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + or_ln23_16_reg_999 <= or_ln23_16_fu_337_p2; + p_cast_i_i_reg_981 <= p_cast_i_i_fu_304_p1; + p_cast_reg_993 <= p_cast_fu_318_p2; + p_mid137_reg_1004 <= p_mid137_fu_343_p2; + sext_ln22_reg_987 <= sext_ln22_fu_314_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln19_reg_1022 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + select_ln19_19_reg_1084 <= select_ln19_19_fu_555_p3; + select_ln20_16_reg_1097 <= select_ln20_16_fu_627_p3; + select_ln20_20_reg_1123 <= select_ln20_20_fu_759_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_1022_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + select_ln33_17_reg_1145 <= select_ln33_17_fu_897_p3; + select_ln33_18_reg_1150 <= select_ln33_18_fu_918_p3; + end +end + +always @ (*) begin + if ((icmp_ln19_reg_1022 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1022 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_240_p4 = select_ln19_19_reg_1084; + end else begin + ap_phi_mux_ii_phi_fu_240_p4 = ii_reg_236; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1022 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_indvar_flatten47_phi_fu_228_p4 = add_ln19_4_reg_1079; + end else begin + ap_phi_mux_indvar_flatten47_phi_fu_228_p4 = indvar_flatten47_reg_224; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1022 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_indvar_flatten_phi_fu_252_p4 = select_ln20_20_reg_1123; + end else begin + ap_phi_mux_indvar_flatten_phi_fu_252_p4 = indvar_flatten_reg_248; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1022 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_263_p4 = select_ln20_16_reg_1097; + end else begin + ap_phi_mux_jj_phi_fu_263_p4 = jj_reg_259; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1022_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1))) begin + ap_phi_mux_kk_0_i_i_phi_fu_275_p4 = add_ln25_reg_1128; + end else begin + ap_phi_mux_kk_0_i_i_phi_fu_275_p4 = kk_0_i_i_reg_271; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_address0 = sext_ln33_8_fu_954_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_address0 = sext_ln33_fu_856_p1; + end else begin + ifmap_vec_address0 = 'bx; + end + end else begin + ifmap_vec_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_address1 = sext_ln33_7_fu_937_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_address1 = zext_ln33_17_fu_824_p1; + end else begin + ifmap_vec_address1 = 'bx; + end + end else begin + ifmap_vec_address1 = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_ce1 = 1'b1; + end else begin + ifmap_vec_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_d0 = select_ln33_18_reg_1150; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_d0 = select_ln33_16_fu_875_p3; + end else begin + ifmap_vec_d0 = 'bx; + end + end else begin + ifmap_vec_d0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_d1 = select_ln33_17_reg_1145; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_d1 = select_ln33_fu_836_p3; + end else begin + ifmap_vec_d1 = 'bx; + end + end else begin + ifmap_vec_d1 = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1022_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_1022_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_we0 = 1'b1; + end else begin + ifmap_vec_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1022_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_1022_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_we1 = 1'b1; + end else begin + ifmap_vec_we1 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln19_reg_1022 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone)) & ~((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage1_subdone)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage1_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln19_reg_1022 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_state9; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln19_4_fu_517_p2 = (indvar_flatten47_reg_224 + 6'd1); + +assign add_ln19_fu_413_p2 = (ap_phi_mux_ii_phi_fu_240_p4 + 2'd1); + +assign add_ln20_4_fu_511_p2 = (ap_phi_mux_indvar_flatten_phi_fu_252_p4 + 5'd1); + +assign add_ln20_fu_470_p2 = (select_ln19_fu_425_p3 + 2'd1); + +assign add_ln22_4_fu_376_p2 = ((sext_ln22_reg_987) + (zext_ln20_fu_372_p1)); + +assign add_ln22_5_fu_480_p2 = ((sext_ln22_reg_987) + (zext_ln20_4_fu_476_p1)); + +assign add_ln22_fu_308_p2 = ((j_cast_i_i_fu_292_p1) + (17'd131071)); + +assign add_ln25_fu_765_p2 = (select_ln20_reg_1091 + 5'd4); + +assign add_ln32_fu_726_p2 = ((sext_ln20_fu_710_p1) + (zext_ln32_19_fu_722_p1)); + +assign add_ln33_4_fu_818_p2 = (tmp_80_cast_fu_807_p3 + zext_ln33_16_fu_815_p1); + +assign add_ln33_fu_797_p2 = ((sub_ln33_cast_fu_790_p1) + (zext_ln33_15_fu_794_p1)); + +assign and_ln19_fu_608_p2 = (xor_ln19_fu_597_p2 & icmp_ln25_fu_602_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd4]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln32_16_fu_871_p1 = tmp_44_i_i_fu_861_p4; + +assign bitcast_ln32_17_fu_893_p1 = tmp_45_i_i_fu_883_p4; + +assign bitcast_ln32_18_fu_914_p1 = tmp_46_i_i_fu_904_p4; + +assign bitcast_ln32_fu_832_p1 = trunc_ln32_fu_828_p1; + +assign col_coord_int_fu_548_p3 = ((is_padding_reg_1015[0:0] == 1'b1) ? 12'd0 : empty_95_fu_543_p2); + +assign col_coord_int_mid139_fu_577_p3 = ((or_ln23_18_reg_1054[0:0] == 1'b1) ? 12'd0 : p_mid137_reg_1004); + +assign col_coord_int_mid1_fu_665_p3 = ((or_ln23_20_reg_1067[0:0] == 1'b1) ? 12'd0 : p_mid1_fu_660_p2); + +assign empty_92_fu_298_p2 = ((zext_ln19_fu_295_p1) + (17'd131071)); + +assign empty_93_fu_356_p2 = ((p_cast_i_i_reg_981) + (ii_cast_i_i_fu_348_p1)); + +assign empty_94_fu_366_p2 = ((empty_93_fu_356_p2 > 18'd55) ? 1'b1 : 1'b0); + +assign empty_95_fu_543_p2 = ((tmp1_cast_fu_539_p1) + (empty_reg_974)); + +assign empty_97_fu_732_p1 = select_ln20_fu_619_p3[3:0]; + +assign empty_fu_287_p1 = indices_12_dout[11:0]; + +assign icmp_ln19_fu_407_p2 = ((ap_phi_mux_indvar_flatten47_phi_fu_228_p4 == 6'd36) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_419_p2 = ((ap_phi_mux_indvar_flatten_phi_fu_252_p4 == 5'd12) ? 1'b1 : 1'b0); + +assign icmp_ln24_4_fu_389_p2 = (((add_ln22_4_fu_376_p2) > (18'd55)) ? 1'b1 : 1'b0); + +assign icmp_ln24_5_fu_493_p2 = (((add_ln22_5_fu_480_p2) > (18'd55)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_331_p2 = (((add_ln22_fu_308_p2) > (17'd55)) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_602_p2 = ((ap_phi_mux_kk_0_i_i_phi_fu_275_p4 == 5'd16) ? 1'b1 : 1'b0); + +assign ii_cast_fu_352_p1 = ap_phi_mux_ii_phi_fu_240_p4; + +assign ii_cast_i_i_fu_348_p1 = ap_phi_mux_ii_phi_fu_240_p4; + +assign ii_cast_i_i_mid1_fu_433_p1 = add_ln19_fu_413_p2; + +assign ii_cast_mid1_fu_437_p1 = add_ln19_fu_413_p2; + +assign in_data_address0 = sext_ln32_fu_754_p1; + +assign indices_01_out_din = indices_01_dout[5:0]; + +assign indices_12_out_din = indices_12_dout[11:0]; + +assign is_padding_fu_401_p2 = (or_ln23_fu_395_p2 | empty_94_fu_366_p2); + +assign j_cast_i_i_fu_292_p1 = indices_12_read_reg_969; + +assign lshr_ln_fu_736_p4 = {{select_ln20_fu_619_p3[3:2]}}; + +assign or_ln20_fu_614_p2 = (icmp_ln20_reg_1031 | and_ln19_fu_608_p2); + +assign or_ln23_16_fu_337_p2 = (tmp_26_fu_323_p3 | icmp_ln24_fu_331_p2); + +assign or_ln23_18_fu_465_p2 = (p_mid113_fu_451_p2 | or_ln23_16_reg_999); + +assign or_ln23_19_fu_499_p2 = (tmp_28_fu_485_p3 | icmp_ln24_5_fu_493_p2); + +assign or_ln23_20_fu_505_p2 = (select_ln19_21_fu_457_p3 | or_ln23_19_fu_499_p2); + +assign or_ln23_fu_395_p2 = (tmp_27_fu_381_p3 | icmp_ln24_4_fu_389_p2); + +assign or_ln25_11_fu_925_p2 = (empty_97_reg_1111_pp0_iter1_reg | 4'd2); + +assign or_ln25_12_fu_942_p2 = (empty_97_reg_1111_pp0_iter1_reg | 4'd3); + +assign or_ln25_fu_844_p2 = (empty_97_reg_1111_pp0_iter1_reg | 4'd1); + +assign p_cast5_i_i_fu_361_p2 = (p_cast_reg_993 + ii_cast_fu_352_p1); + +assign p_cast5_i_i_mid1_fu_446_p2 = (p_cast_reg_993 + ii_cast_mid1_fu_437_p1); + +assign p_cast_fu_318_p2 = ((trunc_ln250_reg_964) + (6'd63)); + +assign p_cast_i_i_fu_304_p1 = (empty_92_fu_298_p2); + +assign p_mid111_fu_441_p2 = ((p_cast_i_i_reg_981) + (ii_cast_i_i_mid1_fu_433_p1)); + +assign p_mid113_fu_451_p2 = ((p_mid111_fu_441_p2 > 18'd55) ? 1'b1 : 1'b0); + +assign p_mid137_fu_343_p2 = ((empty_reg_974) + (12'd4095)); + +assign p_mid1_fu_660_p2 = ((tmp1_cast_mid1_fu_656_p1) + (empty_reg_974)); + +assign row_coord_int_fu_527_p3 = ((is_padding_reg_1015[0:0] == 1'b1) ? 6'd0 : p_cast5_i_i_reg_1009); + +assign row_coord_int_mid131_fu_571_p3 = ((or_ln23_18_reg_1054[0:0] == 1'b1) ? 6'd0 : p_cast5_i_i_mid1_reg_1048); + +assign row_coord_int_mid1_fu_643_p3 = ((or_ln23_20_reg_1067[0:0] == 1'b1) ? 6'd0 : select_ln19_20_fu_561_p3); + +assign select_ln19_19_fu_555_p3 = ((icmp_ln20_reg_1031[0:0] == 1'b1) ? add_ln19_reg_1026 : ii_reg_236); + +assign select_ln19_20_fu_561_p3 = ((icmp_ln20_reg_1031[0:0] == 1'b1) ? p_cast5_i_i_mid1_reg_1048 : p_cast5_i_i_reg_1009); + +assign select_ln19_21_fu_457_p3 = ((icmp_ln20_fu_419_p2[0:0] == 1'b1) ? p_mid113_fu_451_p2 : empty_94_fu_366_p2); + +assign select_ln19_22_fu_566_p3 = ((icmp_ln20_reg_1031[0:0] == 1'b1) ? or_ln23_18_reg_1054 : is_padding_reg_1015); + +assign select_ln19_23_fu_583_p3 = ((icmp_ln20_reg_1031[0:0] == 1'b1) ? row_coord_int_mid131_fu_571_p3 : row_coord_int_fu_527_p3); + +assign select_ln19_24_fu_590_p3 = ((icmp_ln20_reg_1031[0:0] == 1'b1) ? col_coord_int_mid139_fu_577_p3 : col_coord_int_fu_548_p3); + +assign select_ln19_fu_425_p3 = ((icmp_ln20_fu_419_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_263_p4); + +assign select_ln20_16_fu_627_p3 = ((and_ln19_fu_608_p2[0:0] == 1'b1) ? add_ln20_reg_1061 : select_ln19_reg_1043); + +assign select_ln20_17_fu_636_p3 = ((and_ln19_fu_608_p2[0:0] == 1'b1) ? or_ln23_20_reg_1067 : select_ln19_22_fu_566_p3); + +assign select_ln20_18_fu_672_p3 = ((and_ln19_fu_608_p2[0:0] == 1'b1) ? row_coord_int_mid1_fu_643_p3 : select_ln19_23_fu_583_p3); + +assign select_ln20_19_fu_714_p3 = ((and_ln19_fu_608_p2[0:0] == 1'b1) ? col_coord_int_mid1_fu_665_p3 : select_ln19_24_fu_590_p3); + +assign select_ln20_20_fu_759_p3 = ((icmp_ln20_reg_1031[0:0] == 1'b1) ? 5'd1 : add_ln20_4_reg_1074); + +assign select_ln20_fu_619_p3 = ((or_ln20_fu_614_p2[0:0] == 1'b1) ? 5'd0 : ap_phi_mux_kk_0_i_i_phi_fu_275_p4); + +assign select_ln33_16_fu_875_p3 = ((select_ln20_17_reg_1103_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_16_fu_871_p1); + +assign select_ln33_17_fu_897_p3 = ((select_ln20_17_reg_1103_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_17_fu_893_p1); + +assign select_ln33_18_fu_918_p3 = ((select_ln20_17_reg_1103_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_18_fu_914_p1); + +assign select_ln33_fu_836_p3 = ((select_ln20_17_reg_1103_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_fu_832_p1); + +assign sext_ln20_fu_710_p1 = (sub_ln32_fu_704_p2); + +assign sext_ln22_fu_314_p1 = add_ln22_fu_308_p2; + +assign sext_ln32_fu_754_p1 = (tmp_29_fu_746_p3); + +assign sext_ln33_7_fu_937_p1 = (tmp_31_fu_930_p3); + +assign sext_ln33_8_fu_954_p1 = (tmp_32_fu_947_p3); + +assign sext_ln33_fu_856_p1 = (tmp_30_fu_849_p3); + +assign sub_ln32_fu_704_p2 = (zext_ln32_fu_688_p1 - zext_ln32_18_fu_700_p1); + +assign sub_ln33_cast_fu_790_p1 = (sub_ln33_fu_784_p2); + +assign sub_ln33_fu_784_p2 = (zext_ln33_14_fu_780_p1 - zext_ln33_fu_770_p1); + +assign tmp1_cast_fu_539_p1 = (tmp1_fu_533_p2); + +assign tmp1_cast_mid1_fu_656_p1 = (tmp1_mid1_fu_650_p2); + +assign tmp1_fu_533_p2 = ((zext_ln22_fu_523_p1) + (3'd7)); + +assign tmp1_mid1_fu_650_p2 = ((zext_ln22_4_fu_633_p1) + (3'd7)); + +assign tmp_26_fu_323_p3 = add_ln22_fu_308_p2[32'd16]; + +assign tmp_27_fu_381_p3 = add_ln22_4_fu_376_p2[32'd17]; + +assign tmp_28_fu_485_p3 = add_ln22_5_fu_480_p2[32'd17]; + +assign tmp_29_fu_746_p3 = {{add_ln32_fu_726_p2}, {lshr_ln_fu_736_p4}}; + +assign tmp_30_fu_849_p3 = {{add_ln33_reg_1133}, {or_ln25_fu_844_p2}}; + +assign tmp_31_fu_930_p3 = {{add_ln33_reg_1133}, {or_ln25_11_fu_925_p2}}; + +assign tmp_32_fu_947_p3 = {{add_ln33_reg_1133}, {or_ln25_12_fu_942_p2}}; + +assign tmp_44_i_i_fu_861_p4 = {{in_data_q0[31:16]}}; + +assign tmp_45_i_i_fu_883_p4 = {{in_data_q0[47:32]}}; + +assign tmp_46_i_i_fu_904_p4 = {{in_data_q0[63:48]}}; + +assign tmp_6_fu_692_p3 = {{select_ln20_18_fu_672_p3}, {3'd0}}; + +assign tmp_80_cast_fu_807_p3 = {{trunc_ln33_fu_803_p1}, {4'd0}}; + +assign tmp_fu_773_p3 = {{select_ln19_19_reg_1084}, {2'd0}}; + +assign tmp_s_fu_680_p3 = {{select_ln20_18_fu_672_p3}, {6'd0}}; + +assign trunc_ln250_fu_282_p1 = indices_01_dout[5:0]; + +assign trunc_ln32_fu_828_p1 = in_data_q0[15:0]; + +assign trunc_ln33_fu_803_p1 = add_ln33_fu_797_p2[3:0]; + +assign xor_ln19_fu_597_p2 = (icmp_ln20_reg_1031 ^ 1'd1); + +assign zext_ln19_fu_295_p1 = indices_01_read_reg_959; + +assign zext_ln20_4_fu_476_p1 = add_ln20_fu_470_p2; + +assign zext_ln20_fu_372_p1 = ap_phi_mux_jj_phi_fu_263_p4; + +assign zext_ln22_4_fu_633_p1 = add_ln20_reg_1061; + +assign zext_ln22_fu_523_p1 = jj_reg_259; + +assign zext_ln32_18_fu_700_p1 = tmp_6_fu_692_p3; + +assign zext_ln32_19_fu_722_p1 = select_ln20_19_fu_714_p3; + +assign zext_ln32_fu_688_p1 = tmp_s_fu_680_p3; + +assign zext_ln33_14_fu_780_p1 = tmp_fu_773_p3; + +assign zext_ln33_15_fu_794_p1 = select_ln20_16_reg_1097; + +assign zext_ln33_16_fu_815_p1 = select_ln20_reg_1091; + +assign zext_ln33_17_fu_824_p1 = add_ln33_4_reg_1140; + +assign zext_ln33_fu_770_p1 = select_ln19_19_reg_1084; + +endmodule //td_fused_top_tdf4_readInputs37 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_110 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [13:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [13:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [14:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [14:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [14:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [14:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [6:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [6:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [13:0] dataflow_in_loop_TOP_LOOP37738_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP37738_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP37738_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP37738_U0_in_data_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP37738_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP37738_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP37738_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP37738_U0_in_data_we1; +wire [14:0] dataflow_in_loop_TOP_LOOP37738_U0_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP37738_U0_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP37738_U0_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP37738_U0_filter_data_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP37738_U0_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP37738_U0_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP37738_U0_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP37738_U0_filter_data_we1; +wire [6:0] dataflow_in_loop_TOP_LOOP37738_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP37738_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP37738_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP37738_U0_adjustments_we0; +wire [6:0] dataflow_in_loop_TOP_LOOP37738_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP37738_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP37738_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP37738_U0_adjustments_we1; +wire [14:0] dataflow_in_loop_TOP_LOOP37738_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP37738_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP37738_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP37738_U0_out_data_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP37738_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP37738_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP37738_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP37738_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP37738_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP37738_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP37738_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP37738_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP37738_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP37738_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP37738_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP37738_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP37738_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [18:0] loop_dataflow_input_count; +reg [18:0] loop_dataflow_output_count; +wire [18:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP37738_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP37738_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 19'd0; +#0 loop_dataflow_output_count = 19'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP37738 dataflow_in_loop_TOP_LOOP37738_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP37738_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP37738_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP37738_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP37738_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP37738_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP37738_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP37738_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP37738_U0_in_data_we1), + .filter_data_address0(dataflow_in_loop_TOP_LOOP37738_U0_filter_data_address0), + .filter_data_ce0(dataflow_in_loop_TOP_LOOP37738_U0_filter_data_ce0), + .filter_data_d0(dataflow_in_loop_TOP_LOOP37738_U0_filter_data_d0), + .filter_data_q0(filter_data_q0), + .filter_data_we0(dataflow_in_loop_TOP_LOOP37738_U0_filter_data_we0), + .filter_data_address1(dataflow_in_loop_TOP_LOOP37738_U0_filter_data_address1), + .filter_data_ce1(dataflow_in_loop_TOP_LOOP37738_U0_filter_data_ce1), + .filter_data_d1(dataflow_in_loop_TOP_LOOP37738_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(dataflow_in_loop_TOP_LOOP37738_U0_filter_data_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP37738_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP37738_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP37738_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP37738_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP37738_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP37738_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP37738_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP37738_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP37738_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP37738_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP37738_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP37738_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP37738_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP37738_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP37738_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP37738_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP37738_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP37738_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP37738_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP37738_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP37738_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP37738_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP37738_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 19'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37738_U0_ap_ready == 1'b1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 19'd1); + end else if (((dataflow_in_loop_TOP_LOOP37738_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= 19'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 19'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37738_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP37738_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 19'd1); + end else if (((dataflow_in_loop_TOP_LOOP37738_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP37738_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + loop_dataflow_output_count <= 19'd0; + end + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP37738_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP37738_U0_ap_idle == 1'b1) & (loop_dataflow_output_count == 19'd0) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP37738_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP37738_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP37738_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP37738_U0_adjustments_address0; + +assign adjustments_address1 = 7'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP37738_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP37738_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP37738_U0_ap_ready; + +assign bound_minus_1 = (19'd401408 - 19'd1); + +assign dataflow_in_loop_TOP_LOOP37738_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP37738_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP37738_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP37738_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP37738_U0_start_write = 1'b0; + +assign filter_data_address0 = dataflow_in_loop_TOP_LOOP37738_U0_filter_data_address0; + +assign filter_data_address1 = 15'd0; + +assign filter_data_ce0 = dataflow_in_loop_TOP_LOOP37738_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP37738_U0_in_data_address0; + +assign in_data_address1 = 14'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP37738_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP37738_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 15'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP37738_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP37738_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP37738_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP37738_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP37738_U0_out_data_write; + +endmodule //td_fused_top_tdf5_110 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 8'd1; +parameter ap_ST_fsm_pp0_stage0 = 8'd2; +parameter ap_ST_fsm_pp0_stage1 = 8'd4; +parameter ap_ST_fsm_pp0_stage2 = 8'd8; +parameter ap_ST_fsm_pp0_stage3 = 8'd16; +parameter ap_ST_fsm_state12 = 8'd32; +parameter ap_ST_fsm_state13 = 8'd64; +parameter ap_ST_fsm_state14 = 8'd128; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [7:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [7:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[7:0] accum_in_0_address0; +reg accum_in_0_ce0; +reg[7:0] accum_in_0_address1; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [7:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] x_reg_168; +reg [15:0] psum_7_08_reg_180; +reg [15:0] psum_6_07_reg_192; +reg [15:0] psum_5_06_reg_204; +reg [15:0] psum_4_05_reg_216; +reg [15:0] psum_3_04_reg_228; +reg [15:0] psum_2_03_reg_240; +reg [15:0] psum_1_02_reg_252; +reg [15:0] psum_0_01_reg_264; +wire [0:0] icmp_ln49_fu_321_p2; +reg [0:0] icmp_ln49_reg_492; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state6_pp0_stage0_iter1; +wire ap_block_state10_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln49_reg_492_pp0_iter1_reg; +reg [0:0] icmp_ln49_reg_492_pp0_iter2_reg; +reg [15:0] accum_in_0_load_reg_506; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state7_pp0_stage1_iter1; +wire ap_block_state11_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_0_load_29_reg_511; +reg [15:0] accum_in_0_load_30_reg_526; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state8_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_0_load_31_reg_531; +wire [7:0] add_ln49_fu_387_p2; +reg [7:0] add_ln49_reg_546; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state9_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_0_load_32_reg_551; +reg [15:0] accum_in_0_load_33_reg_556; +reg [15:0] accum_in_0_load_34_reg_571; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_0_load_35_reg_576; +wire [15:0] grp_fu_305_p2; +wire [15:0] grp_fu_310_p2; +reg ap_enable_reg_pp0_iter2; +wire [3:0] add_ln57_fu_432_p2; +wire ap_CS_fsm_state13; +wire [0:0] tmp_fu_415_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage1_subdone; +reg [7:0] ap_phi_mux_x_phi_fu_172_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_184_p4; +wire ap_block_pp0_stage1; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_196_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_208_p4; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_220_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_232_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_03_phi_fu_244_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_276; +wire ap_CS_fsm_state12; +reg [15:0] ap_phi_mux_phi_ln69_phi_fu_290_p8; +wire [2:0] trunc_ln57_fu_428_p1; +wire [63:0] zext_ln49_fu_327_p1; +wire [63:0] zext_ln53_fu_338_p1; +wire [63:0] zext_ln53_7_fu_349_p1; +wire [63:0] zext_ln53_8_fu_360_p1; +wire [63:0] zext_ln53_9_fu_371_p1; +wire [63:0] zext_ln53_10_fu_382_p1; +wire [63:0] zext_ln53_11_fu_399_p1; +wire [63:0] zext_ln53_12_fu_410_p1; +wire [63:0] zext_ln57_fu_423_p1; +wire [63:0] zext_ln57_2_fu_444_p1; +reg [15:0] grp_fu_305_p0; +reg [15:0] grp_fu_305_p1; +reg [15:0] grp_fu_310_p0; +reg [15:0] grp_fu_310_p1; +wire [7:0] or_ln53_fu_332_p2; +wire [7:0] or_ln53_7_fu_343_p2; +wire [7:0] or_ln53_8_fu_354_p2; +wire [7:0] or_ln53_9_fu_365_p2; +wire [7:0] or_ln53_10_fu_376_p2; +wire [7:0] or_ln53_11_fu_393_p2; +wire [7:0] or_ln53_12_fu_404_p2; +wire [2:0] or_ln57_fu_438_p2; +wire [0:0] icmp_ln69_fu_449_p2; +wire [0:0] icmp_ln69_3_fu_463_p2; +wire [15:0] select_ln69_fu_455_p3; +wire [0:0] icmp_ln69_4_fu_477_p2; +wire [15:0] select_ln69_3_fu_469_p3; +wire ap_CS_fsm_state14; +reg [7:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_514; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 8'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U297( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_305_p0), + .din1(grp_fu_305_p1), + .dout(grp_fu_305_p2) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U298( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_310_p0), + .din1(grp_fu_310_p1), + .dout(grp_fu_310_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + q_reg_276 <= 4'd0; + end else if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + q_reg_276 <= add_ln57_fu_432_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + x_reg_168 <= add_ln49_reg_546; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_168 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_load_29_reg_511 <= accum_in_0_q0; + accum_in_0_load_reg_506 <= accum_in_0_q1; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_load_30_reg_526 <= accum_in_0_q1; + accum_in_0_load_31_reg_531 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_load_32_reg_551 <= accum_in_0_q1; + accum_in_0_load_33_reg_556 <= accum_in_0_q0; + add_ln49_reg_546 <= add_ln49_fu_387_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_0_load_34_reg_571 <= accum_in_0_q1; + accum_in_0_load_35_reg_576 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln49_reg_492 <= icmp_ln49_fu_321_p2; + icmp_ln49_reg_492_pp0_iter1_reg <= icmp_ln49_reg_492; + icmp_ln49_reg_492_pp0_iter2_reg <= icmp_ln49_reg_492_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_0_01_reg_264 <= grp_fu_305_p2; + psum_1_02_reg_252 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_2_03_reg_240 <= grp_fu_305_p2; + psum_3_04_reg_228 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + psum_4_05_reg_216 <= grp_fu_305_p2; + psum_5_06_reg_204 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_492_pp0_iter2_reg == 1'd1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + psum_6_07_reg_192 <= grp_fu_305_p2; + psum_7_08_reg_180 <= grp_fu_310_p2; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address0 = zext_ln53_12_fu_410_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address0 = zext_ln53_10_fu_382_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address0 = zext_ln53_8_fu_360_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address0 = zext_ln53_fu_338_p1; + end else begin + accum_in_0_address0 = 'bx; + end + end else begin + accum_in_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address1 = zext_ln53_11_fu_399_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address1 = zext_ln53_9_fu_371_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address1 = zext_ln53_7_fu_349_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address1 = zext_ln49_fu_327_p1; + end else begin + accum_in_0_address1 = 'bx; + end + end else begin + accum_in_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln49_reg_492 == 1'd0)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + if ((trunc_ln57_fu_428_p1 == 3'd0)) begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = psum_0_01_reg_264; + end else if ((1'b1 == ap_condition_514)) begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = psum_6_07_reg_192; + end else if ((trunc_ln57_fu_428_p1 == 3'd4)) begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = psum_4_05_reg_216; + end else if ((trunc_ln57_fu_428_p1 == 3'd2)) begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = psum_2_03_reg_240; + end else begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_x_phi_fu_172_p4 = add_ln49_reg_546; + end else begin + ap_phi_mux_x_phi_fu_172_p4 = x_reg_168; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_6_07_phi_fu_196_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_4_05_phi_fu_220_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p0 = ap_phi_mux_psum_2_03_phi_fu_244_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p0 = grp_fu_305_p2; + end else begin + grp_fu_305_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p1 = accum_in_0_load_34_reg_571; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p1 = accum_in_0_load_32_reg_551; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p1 = accum_in_0_load_30_reg_526; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p1 = accum_in_0_load_reg_506; + end else begin + grp_fu_305_p1 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p0 = ap_phi_mux_psum_7_08_phi_fu_184_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p0 = ap_phi_mux_psum_5_06_phi_fu_208_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p0 = ap_phi_mux_psum_3_04_phi_fu_232_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p0 = grp_fu_310_p2; + end else begin + grp_fu_310_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p1 = accum_in_0_load_35_reg_576; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p1 = accum_in_0_load_33_reg_556; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p1 = accum_in_0_load_31_reg_531; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p1 = accum_in_0_load_29_reg_511; + end else begin + grp_fu_310_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (icmp_ln49_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (icmp_ln49_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_state14; + end + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln57_2_fu_444_p1; + +assign accum_out_address1 = zext_ln57_fu_423_p1; + +assign accum_out_d0 = ((icmp_ln69_4_fu_477_p2[0:0] == 1'b1) ? psum_5_06_reg_204 : select_ln69_3_fu_469_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln69_phi_fu_290_p8; + +assign add_ln49_fu_387_p2 = (x_reg_168 + 8'd8); + +assign add_ln57_fu_432_p2 = (q_reg_276 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_state14 = ap_CS_fsm[32'd7]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_514 = (~(trunc_ln57_fu_428_p1 == 3'd0) & ~(trunc_ln57_fu_428_p1 == 3'd4) & ~(trunc_ln57_fu_428_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_03_phi_fu_244_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_232_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_220_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_208_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_196_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_184_p4 = grp_fu_310_p2; + +assign icmp_ln49_fu_321_p2 = ((ap_phi_mux_x_phi_fu_172_p4 < 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln69_3_fu_463_p2 = ((or_ln57_fu_438_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln69_4_fu_477_p2 = ((or_ln57_fu_438_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln69_fu_449_p2 = ((or_ln57_fu_438_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln53_10_fu_376_p2 = (x_reg_168 | 8'd5); + +assign or_ln53_11_fu_393_p2 = (x_reg_168 | 8'd6); + +assign or_ln53_12_fu_404_p2 = (x_reg_168 | 8'd7); + +assign or_ln53_7_fu_343_p2 = (x_reg_168 | 8'd2); + +assign or_ln53_8_fu_354_p2 = (x_reg_168 | 8'd3); + +assign or_ln53_9_fu_365_p2 = (x_reg_168 | 8'd4); + +assign or_ln53_fu_332_p2 = (ap_phi_mux_x_phi_fu_172_p4 | 8'd1); + +assign or_ln57_fu_438_p2 = (trunc_ln57_fu_428_p1 | 3'd1); + +assign select_ln69_3_fu_469_p3 = ((icmp_ln69_3_fu_463_p2[0:0] == 1'b1) ? psum_3_04_reg_228 : select_ln69_fu_455_p3); + +assign select_ln69_fu_455_p3 = ((icmp_ln69_fu_449_p2[0:0] == 1'b1) ? psum_1_02_reg_252 : psum_7_08_reg_180); + +assign tmp_fu_415_p3 = q_reg_276[32'd3]; + +assign trunc_ln57_fu_428_p1 = q_reg_276[2:0]; + +assign zext_ln49_fu_327_p1 = ap_phi_mux_x_phi_fu_172_p4; + +assign zext_ln53_10_fu_382_p1 = or_ln53_10_fu_376_p2; + +assign zext_ln53_11_fu_399_p1 = or_ln53_11_fu_393_p2; + +assign zext_ln53_12_fu_410_p1 = or_ln53_12_fu_404_p2; + +assign zext_ln53_7_fu_349_p1 = or_ln53_7_fu_343_p2; + +assign zext_ln53_8_fu_360_p1 = or_ln53_8_fu_354_p2; + +assign zext_ln53_9_fu_371_p1 = or_ln53_9_fu_365_p2; + +assign zext_ln53_fu_338_p1 = or_ln53_fu_332_p2; + +assign zext_ln57_2_fu_444_p1 = or_ln57_fu_438_p2; + +assign zext_ln57_fu_423_p1 = q_reg_276; + +endmodule //td_fused_top_tdf5_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_10, + accum_in_10_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 7'd1; +parameter ap_ST_fsm_state2 = 7'd2; +parameter ap_ST_fsm_state3 = 7'd4; +parameter ap_ST_fsm_state4 = 7'd8; +parameter ap_ST_fsm_state5 = 7'd16; +parameter ap_ST_fsm_state6 = 7'd32; +parameter ap_ST_fsm_state7 = 7'd64; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_10; +output accum_in_10_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_10; +reg accum_in_10_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [6:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln81_fu_74_p2; +reg [3:0] add_ln81_reg_91; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln81_fu_85_p2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state7; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln81_fu_80_p1; +reg [15:0] accum_in_10_preg; +reg [6:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 7'd1; +#0 accum_in_10_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U301( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_q0), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_10_preg <= 16'd0; + end else begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_10_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + i_1_1_reg_44 <= add_ln81_reg_91; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln81_reg_91 <= add_ln81_fu_74_p2; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_10 = sum_01_reg_55; + end else begin + accum_in_10 = accum_in_10_preg; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_10_ap_vld = 1'b1; + end else begin + accum_in_10_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln81_fu_80_p1; + +assign add_ln81_fu_74_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln81_fu_85_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln81_fu_80_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf5_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 17'd1; +parameter ap_ST_fsm_state2 = 17'd2; +parameter ap_ST_fsm_state3 = 17'd4; +parameter ap_ST_fsm_state4 = 17'd8; +parameter ap_ST_fsm_state5 = 17'd16; +parameter ap_ST_fsm_state6 = 17'd32; +parameter ap_ST_fsm_state7 = 17'd64; +parameter ap_ST_fsm_state8 = 17'd128; +parameter ap_ST_fsm_state9 = 17'd256; +parameter ap_ST_fsm_state10 = 17'd512; +parameter ap_ST_fsm_state11 = 17'd1024; +parameter ap_ST_fsm_state12 = 17'd2048; +parameter ap_ST_fsm_state13 = 17'd4096; +parameter ap_ST_fsm_state14 = 17'd8192; +parameter ap_ST_fsm_state15 = 17'd16384; +parameter ap_ST_fsm_state16 = 17'd32768; +parameter ap_ST_fsm_state17 = 17'd65536; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_read; +output [6:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [6:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg input_indices_23_read; + +reg ap_done_reg; + reg [16:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +wire ap_CS_fsm_state4; +reg [15:0] tmp_42_i_i_reg_167; +reg [15:0] tmp_43_i_i_reg_172; +wire [15:0] grp_fu_81_p2; +reg [15:0] sub_i_i_i_reg_177; +wire ap_CS_fsm_state8; +wire ap_CS_fsm_state9; +wire [15:0] grp_fu_86_p2; +reg [15:0] mul_i_i_i_reg_187; +wire ap_CS_fsm_state12; +wire ap_CS_fsm_state13; +wire [63:0] zext_ln220_fu_90_p1; +reg ap_block_state1; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_77_p1; +wire [15:0] grp_fu_81_p1; +wire [15:0] grp_fu_86_p1; +wire [15:0] trunc_ln220_fu_95_p1; +wire [15:0] grp_fu_77_p2; +wire ap_CS_fsm_state17; +wire [15:0] bitcast_ln648_fu_132_p1; +wire [0:0] tmp_fu_136_p3; +reg [16:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 17'd1; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U305( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(mul_i_i_i_reg_187), + .din1(grp_fu_77_p1), + .dout(grp_fu_77_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U306( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sums_read), + .din1(grp_fu_81_p1), + .dout(grp_fu_81_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U307( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_177), + .din1(grp_fu_86_p1), + .dout(grp_fu_86_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + mul_i_i_i_reg_187 <= grp_fu_86_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sub_i_i_i_reg_177 <= grp_fu_81_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tmp_42_i_i_reg_167 <= {{adjustments_q0[31:16]}}; + tmp_43_i_i_reg_172 <= {{adjustments_q0[47:32]}}; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (~((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign adjustments_address0 = zext_ln220_fu_90_p1; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_return = ((tmp_fu_136_p3[0:0] == 1'b1) ? 16'd0 : grp_fu_77_p2); + +assign bitcast_ln648_fu_132_p1 = grp_fu_77_p2; + +assign grp_fu_77_p1 = tmp_43_i_i_reg_172; + +assign grp_fu_81_p1 = trunc_ln220_fu_95_p1; + +assign grp_fu_86_p1 = tmp_42_i_i_reg_167; + +assign tmp_fu_136_p3 = bitcast_ln648_fu_132_p1[32'd15]; + +assign trunc_ln220_fu_95_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_90_p1 = input_indices_23_dout; + +endmodule //td_fused_top_tdf5_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_q0, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [7:0] ifmap_vec_address0; +output ifmap_vec_ce0; +input [15:0] ifmap_vec_q0; +output [7:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +input [15:0] weight_vecs_0_q0; +output [7:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_ce0; +reg weight_vecs_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] indvar_flatten17_reg_97; +reg [6:0] indvar_flatten_reg_108; +reg [1:0] jj_reg_119; +reg [4:0] ic_reg_131; +reg [1:0] ii_reg_142; +wire [7:0] add_ln147_3_fu_157_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln147_fu_163_p2; +reg [0:0] icmp_ln147_reg_408; +reg [0:0] icmp_ln147_reg_408_pp0_iter1_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter2_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter3_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter4_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter5_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter6_reg; +wire [0:0] icmp_ln148_fu_169_p2; +reg [0:0] icmp_ln148_reg_412; +wire [0:0] and_ln147_fu_195_p2; +reg [0:0] and_ln147_reg_419; +wire [1:0] add_ln148_fu_201_p2; +reg [1:0] add_ln148_reg_424; +wire [4:0] select_ln148_fu_213_p3; +reg [4:0] select_ln148_reg_429; +wire [1:0] select_ln148_7_fu_221_p3; +reg [1:0] select_ln148_7_reg_434; +wire [3:0] trunc_ln150_fu_229_p1; +reg [3:0] trunc_ln150_reg_440; +reg [3:0] trunc_ln150_reg_440_pp0_iter1_reg; +reg [3:0] trunc_ln150_reg_440_pp0_iter2_reg; +reg [3:0] trunc_ln150_reg_440_pp0_iter3_reg; +reg [3:0] trunc_ln150_reg_440_pp0_iter4_reg; +reg [3:0] trunc_ln150_reg_440_pp0_iter5_reg; +reg [3:0] trunc_ln150_reg_440_pp0_iter6_reg; +wire [4:0] add_ln149_fu_233_p2; +wire [6:0] select_ln148_9_fu_245_p3; +wire [1:0] select_ln147_8_fu_287_p3; +reg [1:0] select_ln147_8_reg_455; +reg ap_enable_reg_pp0_iter1; +wire [3:0] select_ln148_8_fu_370_p3; +reg [3:0] select_ln148_8_reg_460; +reg [3:0] select_ln148_8_reg_460_pp0_iter2_reg; +reg [3:0] select_ln148_8_reg_460_pp0_iter3_reg; +reg [3:0] select_ln148_8_reg_460_pp0_iter4_reg; +reg [3:0] select_ln148_8_reg_460_pp0_iter5_reg; +reg [3:0] select_ln148_8_reg_460_pp0_iter6_reg; +reg [15:0] ifmap_vec_load_reg_475; +reg [15:0] weight_vecs_0_load_reg_480; +wire [15:0] grp_fu_153_p2; +reg [15:0] mul_reg_485; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg [1:0] ap_phi_mux_jj_phi_fu_123_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_146_p4; +wire [63:0] p_cast25_fu_386_p1; +wire [63:0] idxprom30_fu_398_p1; +wire [0:0] icmp_ln149_fu_189_p2; +wire [0:0] xor_ln147_fu_183_p2; +wire [1:0] select_ln147_fu_175_p3; +wire [0:0] or_ln148_fu_207_p2; +wire [6:0] add_ln148_3_fu_239_p2; +wire [3:0] shl_ln_fu_257_p3; +wire [3:0] zext_ln150_fu_253_p1; +wire [3:0] sub_ln150_fu_265_p2; +wire [3:0] zext_ln150_3_fu_271_p1; +wire [1:0] add_ln147_fu_281_p2; +wire [3:0] tmp_fu_298_p3; +wire [3:0] select_ln147_10_cast_fu_294_p1; +wire [3:0] shl_ln150_mid1_fu_316_p3; +wire [3:0] zext_ln150_6_fu_312_p1; +wire [3:0] sub_ln150_3_fu_324_p2; +wire [3:0] add_ln150_fu_275_p2; +wire [3:0] empty_88_fu_306_p2; +wire [3:0] select_ln148_9_cast_fu_344_p1; +wire [3:0] empty_89_fu_347_p2; +wire [3:0] select_ln147_9_fu_330_p3; +wire [3:0] zext_ln150_7_fu_361_p1; +wire [3:0] add_ln150_3_fu_364_p2; +wire [3:0] select_ln147_10_fu_337_p3; +wire [7:0] tmp_78_cast_fu_353_p3; +wire [7:0] select_ln148_cast_fu_377_p1; +wire [7:0] empty_90_fu_380_p2; +wire [7:0] p_fu_392_p3; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U293( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_load_reg_475), + .din1(weight_vecs_0_load_reg_480), + .dout(grp_fu_153_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_reg_131 <= add_ln149_fu_233_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_reg_131 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ii_reg_142 <= select_ln147_8_reg_455; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_142 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten17_reg_97 <= add_ln147_3_fu_157_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten17_reg_97 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_108 <= select_ln148_9_fu_245_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_108 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_119 <= select_ln148_7_reg_434; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_119 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln148_reg_424 <= add_ln148_fu_201_p2; + and_ln147_reg_419 <= and_ln147_fu_195_p2; + icmp_ln148_reg_412 <= icmp_ln148_fu_169_p2; + select_ln148_reg_429 <= select_ln148_fu_213_p3; + trunc_ln150_reg_440 <= trunc_ln150_fu_229_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln147_reg_408 <= icmp_ln147_fu_163_p2; + icmp_ln147_reg_408_pp0_iter1_reg <= icmp_ln147_reg_408; + trunc_ln150_reg_440_pp0_iter1_reg <= trunc_ln150_reg_440; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln147_reg_408_pp0_iter2_reg <= icmp_ln147_reg_408_pp0_iter1_reg; + icmp_ln147_reg_408_pp0_iter3_reg <= icmp_ln147_reg_408_pp0_iter2_reg; + icmp_ln147_reg_408_pp0_iter4_reg <= icmp_ln147_reg_408_pp0_iter3_reg; + icmp_ln147_reg_408_pp0_iter5_reg <= icmp_ln147_reg_408_pp0_iter4_reg; + icmp_ln147_reg_408_pp0_iter6_reg <= icmp_ln147_reg_408_pp0_iter5_reg; + select_ln148_8_reg_460_pp0_iter2_reg <= select_ln148_8_reg_460; + select_ln148_8_reg_460_pp0_iter3_reg <= select_ln148_8_reg_460_pp0_iter2_reg; + select_ln148_8_reg_460_pp0_iter4_reg <= select_ln148_8_reg_460_pp0_iter3_reg; + select_ln148_8_reg_460_pp0_iter5_reg <= select_ln148_8_reg_460_pp0_iter4_reg; + select_ln148_8_reg_460_pp0_iter6_reg <= select_ln148_8_reg_460_pp0_iter5_reg; + trunc_ln150_reg_440_pp0_iter2_reg <= trunc_ln150_reg_440_pp0_iter1_reg; + trunc_ln150_reg_440_pp0_iter3_reg <= trunc_ln150_reg_440_pp0_iter2_reg; + trunc_ln150_reg_440_pp0_iter4_reg <= trunc_ln150_reg_440_pp0_iter3_reg; + trunc_ln150_reg_440_pp0_iter5_reg <= trunc_ln150_reg_440_pp0_iter4_reg; + trunc_ln150_reg_440_pp0_iter6_reg <= trunc_ln150_reg_440_pp0_iter5_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_load_reg_475 <= ifmap_vec_q0; + weight_vecs_0_load_reg_480 <= weight_vecs_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_reg_485 <= grp_fu_153_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + select_ln147_8_reg_455 <= select_ln147_8_fu_287_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_7_reg_434 <= select_ln148_7_fu_221_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_8_reg_460 <= select_ln148_8_fu_370_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_fu_163_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_146_p4 = select_ln147_8_reg_455; + end else begin + ap_phi_mux_ii_phi_fu_146_p4 = ii_reg_142; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_123_p4 = select_ln148_7_reg_434; + end else begin + ap_phi_mux_jj_phi_fu_123_p4 = jj_reg_119; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_3_fu_157_p2 = (indvar_flatten17_reg_97 + 8'd1); + +assign add_ln147_fu_281_p2 = (ap_phi_mux_ii_phi_fu_146_p4 + 2'd1); + +assign add_ln148_3_fu_239_p2 = (indvar_flatten_reg_108 + 7'd1); + +assign add_ln148_fu_201_p2 = (select_ln147_fu_175_p3 + 2'd1); + +assign add_ln149_fu_233_p2 = (select_ln148_fu_213_p3 + 5'd1); + +assign add_ln150_3_fu_364_p2 = (select_ln147_9_fu_330_p3 + zext_ln150_7_fu_361_p1); + +assign add_ln150_fu_275_p2 = (sub_ln150_fu_265_p2 + zext_ln150_3_fu_271_p1); + +assign and_ln147_fu_195_p2 = (xor_ln147_fu_183_p2 & icmp_ln149_fu_189_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign empty_88_fu_306_p2 = (tmp_fu_298_p3 - select_ln147_10_cast_fu_294_p1); + +assign empty_89_fu_347_p2 = (empty_88_fu_306_p2 + select_ln148_9_cast_fu_344_p1); + +assign empty_90_fu_380_p2 = (tmp_78_cast_fu_353_p3 + select_ln148_cast_fu_377_p1); + +assign icmp_ln147_fu_163_p2 = ((indvar_flatten17_reg_97 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln148_fu_169_p2 = ((indvar_flatten_reg_108 == 7'd48) ? 1'b1 : 1'b0); + +assign icmp_ln149_fu_189_p2 = ((ic_reg_131 == 5'd16) ? 1'b1 : 1'b0); + +assign idxprom30_fu_398_p1 = p_fu_392_p3; + +assign ifmap_vec_address0 = p_cast25_fu_386_p1; + +assign or_ln148_fu_207_p2 = (icmp_ln148_fu_169_p2 | and_ln147_fu_195_p2); + +assign p_cast25_fu_386_p1 = empty_90_fu_380_p2; + +assign p_fu_392_p3 = {{select_ln148_8_reg_460_pp0_iter6_reg}, {trunc_ln150_reg_440_pp0_iter6_reg}}; + +assign products_0_address0 = idxprom30_fu_398_p1; + +assign products_0_d0 = mul_reg_485; + +assign select_ln147_10_cast_fu_294_p1 = select_ln147_8_fu_287_p3; + +assign select_ln147_10_fu_337_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? sub_ln150_3_fu_324_p2 : add_ln150_fu_275_p2); + +assign select_ln147_8_fu_287_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? add_ln147_fu_281_p2 : ap_phi_mux_ii_phi_fu_146_p4); + +assign select_ln147_9_fu_330_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? sub_ln150_3_fu_324_p2 : sub_ln150_fu_265_p2); + +assign select_ln147_fu_175_p3 = ((icmp_ln148_fu_169_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_123_p4); + +assign select_ln148_7_fu_221_p3 = ((and_ln147_fu_195_p2[0:0] == 1'b1) ? add_ln148_fu_201_p2 : select_ln147_fu_175_p3); + +assign select_ln148_8_fu_370_p3 = ((and_ln147_reg_419[0:0] == 1'b1) ? add_ln150_3_fu_364_p2 : select_ln147_10_fu_337_p3); + +assign select_ln148_9_cast_fu_344_p1 = select_ln148_7_reg_434; + +assign select_ln148_9_fu_245_p3 = ((icmp_ln148_fu_169_p2[0:0] == 1'b1) ? 7'd1 : add_ln148_3_fu_239_p2); + +assign select_ln148_cast_fu_377_p1 = select_ln148_reg_429; + +assign select_ln148_fu_213_p3 = ((or_ln148_fu_207_p2[0:0] == 1'b1) ? 5'd0 : ic_reg_131); + +assign shl_ln150_mid1_fu_316_p3 = {{add_ln147_fu_281_p2}, {2'd0}}; + +assign shl_ln_fu_257_p3 = {{ap_phi_mux_ii_phi_fu_146_p4}, {2'd0}}; + +assign sub_ln150_3_fu_324_p2 = (shl_ln150_mid1_fu_316_p3 - zext_ln150_6_fu_312_p1); + +assign sub_ln150_fu_265_p2 = (shl_ln_fu_257_p3 - zext_ln150_fu_253_p1); + +assign tmp_78_cast_fu_353_p3 = {{empty_89_fu_347_p2}, {4'd0}}; + +assign tmp_fu_298_p3 = {{select_ln147_8_fu_287_p3}, {2'd0}}; + +assign trunc_ln150_fu_229_p1 = select_ln148_fu_213_p3[3:0]; + +assign weight_vecs_0_address0 = p_cast25_fu_386_p1; + +assign xor_ln147_fu_183_p2 = (icmp_ln148_fu_169_p2 ^ 1'd1); + +assign zext_ln150_3_fu_271_p1 = jj_reg_119; + +assign zext_ln150_6_fu_312_p1 = add_ln147_fu_281_p2; + +assign zext_ln150_7_fu_361_p1 = add_ln148_reg_424; + +assign zext_ln150_fu_253_p1 = ap_phi_mux_ii_phi_fu_146_p4; + +endmodule //td_fused_top_tdf5_dot_product +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + input_indices_2_out_din, + input_indices_2_out_full_n, + input_indices_2_out_write, + input_indices_2_out1_din, + input_indices_2_out1_full_n, + input_indices_2_out1_write, + output_indices_0_din, + output_indices_0_full_n, + output_indices_0_write, + output_indices_1_din, + output_indices_1_full_n, + output_indices_1_write, + resetMaximum_din, + resetMaximum_full_n, + resetMaximum_write, + storeOutput_din, + storeOutput_full_n, + storeOutput_write, + ap_return_0, + ap_return_1 +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [6:0] input_indices_2_out_din; +input input_indices_2_out_full_n; +output input_indices_2_out_write; +output [6:0] input_indices_2_out1_din; +input input_indices_2_out1_full_n; +output input_indices_2_out1_write; +output [4:0] output_indices_0_din; +input output_indices_0_full_n; +output output_indices_0_write; +output [9:0] output_indices_1_din; +input output_indices_1_full_n; +output output_indices_1_write; +output resetMaximum_din; +input resetMaximum_full_n; +output resetMaximum_write; +output storeOutput_din; +input storeOutput_full_n; +output storeOutput_write; +output [15:0] ap_return_0; +output [15:0] ap_return_1; + +reg ap_done; +reg ap_idle; +reg start_write; +reg input_indices_2_out_write; +reg input_indices_2_out1_write; +reg output_indices_0_write; +reg output_indices_1_write; +reg resetMaximum_write; +reg storeOutput_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [1:0] i_p_1; +reg [1:0] j_p_1; +reg [15:0] i_3; +reg [15:0] j_3; +reg [15:0] k_3; +reg [15:0] i_out_1; +reg [15:0] j_out_1; +reg input_indices_2_out_blk_n; +reg input_indices_2_out1_blk_n; +reg output_indices_0_blk_n; +reg output_indices_1_blk_n; +reg resetMaximum_blk_n; +reg storeOutput_blk_n; +wire [1:0] select_ln142_fu_338_p3; +reg ap_block_state1; +wire [0:0] or_ln142_fu_312_p2; +wire [1:0] select_ln142_5_fu_346_p3; +wire [15:0] select_ln147_fu_278_p3; +wire [0:0] and_ln142_2_fu_306_p2; +wire [15:0] select_ln142_6_fu_360_p3; +wire [0:0] and_ln132_fu_354_p2; +wire [15:0] select_ln142_7_fu_388_p3; +wire [0:0] and_ln135_fu_294_p2; +wire [15:0] select_ln147_2_fu_286_p3; +wire [15:0] select_ln142_8_fu_396_p3; +wire [6:0] trunc_ln128_fu_182_p1; +wire [1:0] or_ln124_fu_126_p2; +wire [0:0] icmp_ln125_fu_139_p2; +wire [0:0] icmp_ln125_2_fu_145_p2; +wire [15:0] zext_ln126_fu_114_p1; +wire [15:0] zext_ln127_fu_122_p1; +wire [1:0] add_ln131_fu_206_p2; +wire [1:0] add_ln134_fu_218_p2; +wire [15:0] add_ln137_fu_230_p2; +wire [15:0] add_ln141_fu_248_p2; +wire [15:0] add_ln146_fu_266_p2; +wire [0:0] icmp_ln147_fu_272_p2; +wire [15:0] add_ln145_fu_260_p2; +wire [0:0] icmp_ln132_fu_212_p2; +wire [0:0] icmp_ln135_fu_224_p2; +wire [0:0] icmp_ln138_fu_236_p2; +wire [0:0] icmp_ln142_fu_254_p2; +wire [0:0] and_ln142_fu_300_p2; +wire [0:0] xor_ln135_fu_318_p2; +wire [0:0] and_ln135_2_fu_324_p2; +wire [1:0] select_ln135_fu_330_p3; +wire [15:0] add_ln140_fu_242_p2; +wire [0:0] xor_ln138_fu_368_p2; +wire [0:0] and_ln138_fu_374_p2; +wire [15:0] select_ln138_fu_380_p3; +wire [15:0] add_ln126_fu_162_p2; +wire [15:0] add_ln127_fu_172_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_p_1 = 2'd0; +#0 j_p_1 = 2'd0; +#0 i_3 = 16'd0; +#0 j_3 = 16'd0; +#0 k_3 = 16'd0; +#0 i_out_1 = 16'd0; +#0 j_out_1 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln142_2_fu_306_p2))) begin + i_3 <= select_ln147_fu_278_p3; + i_out_1 <= select_ln147_2_fu_286_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (or_ln142_fu_312_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_p_1 <= select_ln142_fu_338_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln132_fu_354_p2))) begin + j_3 <= select_ln142_6_fu_360_p3; + j_out_1 <= select_ln142_8_fu_396_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + j_p_1 <= select_ln142_5_fu_346_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln135_fu_294_p2))) begin + k_3 <= select_ln142_7_fu_388_p3; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_blk_n = input_indices_2_out1_full_n; + end else begin + input_indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_write = 1'b1; + end else begin + input_indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_blk_n = input_indices_2_out_full_n; + end else begin + input_indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_write = 1'b1; + end else begin + input_indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_blk_n = output_indices_0_full_n; + end else begin + output_indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_write = 1'b1; + end else begin + output_indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_blk_n = output_indices_1_full_n; + end else begin + output_indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_write = 1'b1; + end else begin + output_indices_1_write = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_blk_n = resetMaximum_full_n; + end else begin + resetMaximum_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_write = 1'b1; + end else begin + resetMaximum_write = 1'b0; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_blk_n = storeOutput_full_n; + end else begin + storeOutput_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_write = 1'b1; + end else begin + storeOutput_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln126_fu_162_p2 = (i_3 + zext_ln126_fu_114_p1); + +assign add_ln127_fu_172_p2 = (j_3 + zext_ln127_fu_122_p1); + +assign add_ln131_fu_206_p2 = (j_p_1 + 2'd1); + +assign add_ln134_fu_218_p2 = (i_p_1 + 2'd1); + +assign add_ln137_fu_230_p2 = (k_3 + 16'd1); + +assign add_ln140_fu_242_p2 = (j_3 + 16'd2); + +assign add_ln141_fu_248_p2 = (j_out_1 + 16'd1); + +assign add_ln145_fu_260_p2 = (i_3 + 16'd2); + +assign add_ln146_fu_266_p2 = (i_out_1 + 16'd1); + +assign and_ln132_fu_354_p2 = (icmp_ln138_fu_236_p2 & and_ln135_fu_294_p2); + +assign and_ln135_2_fu_324_p2 = (xor_ln135_fu_318_p2 & icmp_ln132_fu_212_p2); + +assign and_ln135_fu_294_p2 = (icmp_ln135_fu_224_p2 & icmp_ln132_fu_212_p2); + +assign and_ln138_fu_374_p2 = (xor_ln138_fu_368_p2 & and_ln135_fu_294_p2); + +assign and_ln142_2_fu_306_p2 = (and_ln142_fu_300_p2 & and_ln135_fu_294_p2); + +assign and_ln142_fu_300_p2 = (icmp_ln142_fu_254_p2 & icmp_ln138_fu_236_p2); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign ap_return_0 = add_ln126_fu_162_p2; + +assign ap_return_1 = add_ln127_fu_172_p2; + +assign icmp_ln125_2_fu_145_p2 = ((j_p_1 == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln125_fu_139_p2 = ((i_p_1 == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln132_fu_212_p2 = ((add_ln131_fu_206_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln135_fu_224_p2 = ((add_ln134_fu_218_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln138_fu_236_p2 = ((add_ln137_fu_230_p2 == 16'd128) ? 1'b1 : 1'b0); + +assign icmp_ln142_fu_254_p2 = ((add_ln141_fu_248_p2 == 16'd28) ? 1'b1 : 1'b0); + +assign icmp_ln147_fu_272_p2 = ((add_ln146_fu_266_p2 == 16'd28) ? 1'b1 : 1'b0); + +assign input_indices_2_out1_din = trunc_ln128_fu_182_p1; + +assign input_indices_2_out_din = trunc_ln128_fu_182_p1; + +assign or_ln124_fu_126_p2 = (j_p_1 | i_p_1); + +assign or_ln142_fu_312_p2 = (icmp_ln132_fu_212_p2 | and_ln142_2_fu_306_p2); + +assign output_indices_0_din = i_out_1[4:0]; + +assign output_indices_1_din = j_out_1[9:0]; + +assign resetMaximum_din = ((or_ln124_fu_126_p2 == 2'd0) ? 1'b1 : 1'b0); + +assign select_ln135_fu_330_p3 = ((and_ln135_2_fu_324_p2[0:0] == 1'b1) ? add_ln134_fu_218_p2 : 2'd0); + +assign select_ln138_fu_380_p3 = ((and_ln138_fu_374_p2[0:0] == 1'b1) ? add_ln137_fu_230_p2 : 16'd0); + +assign select_ln142_5_fu_346_p3 = ((or_ln142_fu_312_p2[0:0] == 1'b1) ? 2'd0 : add_ln131_fu_206_p2); + +assign select_ln142_6_fu_360_p3 = ((and_ln142_2_fu_306_p2[0:0] == 1'b1) ? 16'd0 : add_ln140_fu_242_p2); + +assign select_ln142_7_fu_388_p3 = ((and_ln142_2_fu_306_p2[0:0] == 1'b1) ? 16'd0 : select_ln138_fu_380_p3); + +assign select_ln142_8_fu_396_p3 = ((and_ln142_2_fu_306_p2[0:0] == 1'b1) ? 16'd0 : add_ln141_fu_248_p2); + +assign select_ln142_fu_338_p3 = ((and_ln142_2_fu_306_p2[0:0] == 1'b1) ? 2'd0 : select_ln135_fu_330_p3); + +assign select_ln147_2_fu_286_p3 = ((icmp_ln147_fu_272_p2[0:0] == 1'b1) ? 16'd0 : add_ln146_fu_266_p2); + +assign select_ln147_fu_278_p3 = ((icmp_ln147_fu_272_p2[0:0] == 1'b1) ? 16'd0 : add_ln145_fu_260_p2); + +assign start_out = real_start; + +assign storeOutput_din = (icmp_ln125_fu_139_p2 & icmp_ln125_2_fu_145_p2); + +assign trunc_ln128_fu_182_p1 = k_3[6:0]; + +assign xor_ln135_fu_318_p2 = (icmp_ln135_fu_224_p2 ^ 1'd1); + +assign xor_ln138_fu_368_p2 = (icmp_ln138_fu_236_p2 ^ 1'd1); + +assign zext_ln126_fu_114_p1 = i_p_1; + +assign zext_ln127_fu_122_p1 = j_p_1; + +endmodule //td_fused_top_tdf5_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_poolOutputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + output_indices_04_dout, + output_indices_04_empty_n, + output_indices_04_read, + output_indices_15_dout, + output_indices_15_empty_n, + output_indices_15_read, + resetMaximum6_dout, + resetMaximum6_empty_n, + resetMaximum6_read, + storeOutput7_dout, + storeOutput7_empty_n, + storeOutput7_read, + p_read, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_state3 = 4'd4; +parameter ap_ST_fsm_state4 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [4:0] output_indices_04_dout; +input output_indices_04_empty_n; +output output_indices_04_read; +input [9:0] output_indices_15_dout; +input output_indices_15_empty_n; +output output_indices_15_read; +input [0:0] resetMaximum6_dout; +input resetMaximum6_empty_n; +output resetMaximum6_read; +input [0:0] storeOutput7_dout; +input storeOutput7_empty_n; +output storeOutput7_read; +input [15:0] p_read; +output [14:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg output_indices_04_read; +reg output_indices_15_read; +reg resetMaximum6_read; +reg storeOutput7_read; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] max_vals_5_0; +reg output_indices_04_blk_n; +wire ap_CS_fsm_state2; +reg output_indices_15_blk_n; +reg resetMaximum6_blk_n; +reg storeOutput7_blk_n; +reg [4:0] output_indices_04_read_reg_147; +reg [9:0] output_indices_15_read_reg_152; +wire [0:0] storeOutput7_read_read_fu_82_p2; +reg [0:0] storeOutput7_read_reg_157; +wire grp_tdf5_writeOutputs_unaligned_fu_88_ap_start; +wire grp_tdf5_writeOutputs_unaligned_fu_88_ap_done; +wire grp_tdf5_writeOutputs_unaligned_fu_88_ap_idle; +wire grp_tdf5_writeOutputs_unaligned_fu_88_ap_ready; +wire [14:0] grp_tdf5_writeOutputs_unaligned_fu_88_out_data_address1; +wire grp_tdf5_writeOutputs_unaligned_fu_88_out_data_ce1; +wire grp_tdf5_writeOutputs_unaligned_fu_88_out_data_we1; +wire [63:0] grp_tdf5_writeOutputs_unaligned_fu_88_out_data_d1; +reg grp_tdf5_writeOutputs_unaligned_fu_88_ap_start_reg; +wire ap_CS_fsm_state3; +wire ap_CS_fsm_state4; +reg ap_block_state4_on_subcall_done; +wire [15:0] select_ln24_fu_126_p3; +reg ap_block_state2; +reg ap_block_state1; +wire [0:0] grp_fu_110_p2; +wire [0:0] or_ln24_fu_120_p2; +reg grp_fu_110_ce; +reg [3:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 max_vals_5_0 = 16'd0; +#0 grp_tdf5_writeOutputs_unaligned_fu_88_ap_start_reg = 1'b0; +end + +td_fused_top_tdf5_writeOutputs_unaligned grp_tdf5_writeOutputs_unaligned_fu_88( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(grp_tdf5_writeOutputs_unaligned_fu_88_ap_start), + .ap_done(grp_tdf5_writeOutputs_unaligned_fu_88_ap_done), + .ap_idle(grp_tdf5_writeOutputs_unaligned_fu_88_ap_idle), + .ap_ready(grp_tdf5_writeOutputs_unaligned_fu_88_ap_ready), + .i(output_indices_04_read_reg_147), + .j(output_indices_15_read_reg_152), + .out_data_address1(grp_tdf5_writeOutputs_unaligned_fu_88_out_data_address1), + .out_data_ce1(grp_tdf5_writeOutputs_unaligned_fu_88_out_data_ce1), + .out_data_we1(grp_tdf5_writeOutputs_unaligned_fu_88_out_data_we1), + .out_data_d1(grp_tdf5_writeOutputs_unaligned_fu_88_out_data_d1), + .max_vals_5_0(max_vals_5_0) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U315( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_110_ce), + .din0(max_vals_5_0), + .din1(p_read), + .opcode(5'd4), + .dout(grp_fu_110_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + grp_tdf5_writeOutputs_unaligned_fu_88_ap_start_reg <= 1'b0; + end else begin + if ((1'b1 == ap_CS_fsm_state3)) begin + grp_tdf5_writeOutputs_unaligned_fu_88_ap_start_reg <= 1'b1; + end else if ((grp_tdf5_writeOutputs_unaligned_fu_88_ap_ready == 1'b1)) begin + grp_tdf5_writeOutputs_unaligned_fu_88_ap_start_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + max_vals_5_0 <= select_ln24_fu_126_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_04_read_reg_147 <= output_indices_04_dout; + output_indices_15_read_reg_152 <= output_indices_15_dout; + storeOutput7_read_reg_157 <= storeOutput7_dout; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_110_ce = 1'b1; + end else begin + grp_fu_110_ce = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_04_blk_n = output_indices_04_empty_n; + end else begin + output_indices_04_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_04_read = 1'b1; + end else begin + output_indices_04_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_15_blk_n = output_indices_15_empty_n; + end else begin + output_indices_15_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_15_read = 1'b1; + end else begin + output_indices_15_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + resetMaximum6_blk_n = resetMaximum6_empty_n; + end else begin + resetMaximum6_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + resetMaximum6_read = 1'b1; + end else begin + resetMaximum6_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + storeOutput7_blk_n = storeOutput7_empty_n; + end else begin + storeOutput7_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + storeOutput7_read = 1'b1; + end else begin + storeOutput7_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_82_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_82_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state3; + end else begin + ap_NS_fsm = ap_ST_fsm_state2; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +always @ (*) begin + ap_block_state2 = ((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)); +end + +always @ (*) begin + ap_block_state4_on_subcall_done = ((grp_tdf5_writeOutputs_unaligned_fu_88_ap_done == 1'b0) & (storeOutput7_read_reg_157 == 1'd1)); +end + +assign grp_tdf5_writeOutputs_unaligned_fu_88_ap_start = grp_tdf5_writeOutputs_unaligned_fu_88_ap_start_reg; + +assign or_ln24_fu_120_p2 = (resetMaximum6_dout | grp_fu_110_p2); + +assign out_data_address1 = grp_tdf5_writeOutputs_unaligned_fu_88_out_data_address1; + +assign out_data_ce1 = grp_tdf5_writeOutputs_unaligned_fu_88_out_data_ce1; + +assign out_data_d1 = grp_tdf5_writeOutputs_unaligned_fu_88_out_data_d1; + +assign out_data_we1 = grp_tdf5_writeOutputs_unaligned_fu_88_out_data_we1; + +assign select_ln24_fu_126_p3 = ((or_ln24_fu_120_p2[0:0] == 1'b1) ? p_read : max_vals_5_0); + +assign storeOutput7_read_read_fu_82_p2 = storeOutput7_dout; + +endmodule //td_fused_top_tdf5_poolOutputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_readFilters40 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_we0, + weight_vecs_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state7 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [14:0] filter_data_address0; +output filter_data_ce0; +input [15:0] filter_data_q0; +input [6:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [7:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +output weight_vecs_0_we0; +output [15:0] weight_vecs_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg input_indices_23_read; +reg weight_vecs_0_ce0; +reg weight_vecs_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +reg [7:0] indvar_flatten13_reg_123; +reg [1:0] ii_reg_134; +reg [6:0] indvar_flatten_reg_145; +reg [1:0] jj_reg_156; +reg [4:0] kk_reg_167; +wire [10:0] sext_ln47_fu_200_p1; +reg [10:0] sext_ln47_reg_408; +wire [7:0] add_ln47_3_fu_204_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln47_fu_210_p2; +reg [0:0] icmp_ln47_reg_418; +reg [0:0] icmp_ln47_reg_418_pp0_iter1_reg; +reg [0:0] icmp_ln47_reg_418_pp0_iter2_reg; +reg [0:0] icmp_ln47_reg_418_pp0_iter3_reg; +wire [0:0] icmp_ln48_fu_222_p2; +reg [0:0] icmp_ln48_reg_422; +wire [1:0] select_ln47_3_fu_228_p3; +reg [1:0] select_ln47_3_reg_429; +wire [6:0] select_ln48_6_fu_242_p3; +wire [1:0] select_ln48_5_fu_329_p3; +reg [1:0] select_ln48_5_reg_442; +reg ap_enable_reg_pp0_iter1; +wire [7:0] add_ln55_12_fu_392_p2; +reg [7:0] add_ln55_12_reg_452; +reg [7:0] add_ln55_12_reg_452_pp0_iter2_reg; +reg [7:0] add_ln55_12_reg_452_pp0_iter3_reg; +wire [4:0] add_ln49_fu_398_p2; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg [1:0] ap_phi_mux_ii_phi_fu_138_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_160_p4; +wire [63:0] zext_ln55_28_fu_387_p1; +wire [63:0] zext_ln55_29_fu_404_p1; +wire [8:0] tmp_fu_182_p3; +wire [9:0] zext_ln55_21_fu_190_p1; +wire [9:0] zext_ln55_fu_178_p1; +wire [9:0] sub_ln55_fu_194_p2; +wire [1:0] add_ln47_fu_216_p2; +wire [6:0] add_ln48_3_fu_236_p2; +wire [10:0] zext_ln55_23_fu_260_p1; +wire [10:0] add_ln55_fu_263_p2; +wire [10:0] shl_ln55_fu_268_p2; +wire [3:0] tmp_s_fu_280_p3; +wire [3:0] zext_ln55_22_fu_257_p1; +wire [0:0] icmp_ln49_fu_298_p2; +wire [0:0] xor_ln47_fu_293_p2; +wire [1:0] select_ln47_fu_250_p3; +wire [0:0] and_ln47_fu_304_p2; +wire [0:0] or_ln48_fu_316_p2; +wire [1:0] add_ln48_fu_310_p2; +wire [10:0] sub_ln55_5_fu_274_p2; +wire [10:0] zext_ln55_25_fu_341_p1; +wire [10:0] add_ln55_9_fu_345_p2; +wire [3:0] sub_ln55_6_fu_287_p2; +wire [3:0] zext_ln55_24_fu_337_p1; +wire [3:0] add_ln55_10_fu_359_p2; +wire [4:0] select_ln48_fu_321_p3; +wire [14:0] tmp_74_cast_fu_351_p3; +wire [14:0] zext_ln55_27_fu_377_p1; +wire [14:0] add_ln55_11_fu_381_p2; +wire [7:0] tmp_76_cast_fu_365_p3; +wire [7:0] zext_ln55_26_fu_373_p1; +wire ap_CS_fsm_state7; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ii_reg_134 <= select_ln47_3_reg_429; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_134 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten13_reg_123 <= add_ln47_3_fu_204_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_123 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_145 <= select_ln48_6_fu_242_p3; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_145 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_418_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + jj_reg_156 <= select_ln48_5_reg_442; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_156 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_reg_167 <= add_ln49_fu_398_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_167 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln55_12_reg_452 <= add_ln55_12_fu_392_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln55_12_reg_452_pp0_iter2_reg <= add_ln55_12_reg_452; + add_ln55_12_reg_452_pp0_iter3_reg <= add_ln55_12_reg_452_pp0_iter2_reg; + icmp_ln47_reg_418_pp0_iter2_reg <= icmp_ln47_reg_418_pp0_iter1_reg; + icmp_ln47_reg_418_pp0_iter3_reg <= icmp_ln47_reg_418_pp0_iter2_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln47_reg_418 <= icmp_ln47_fu_210_p2; + icmp_ln47_reg_418_pp0_iter1_reg <= icmp_ln47_reg_418; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln48_reg_422 <= icmp_ln48_fu_222_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln47_3_reg_429 <= select_ln47_3_fu_228_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln48_5_reg_442 <= select_ln48_5_fu_329_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sext_ln47_reg_408 <= sext_ln47_fu_200_p1; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln47_fu_210_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_138_p4 = select_ln47_3_reg_429; + end else begin + ap_phi_mux_ii_phi_fu_138_p4 = ii_reg_134; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_418_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_160_p4 = select_ln48_5_reg_442; + end else begin + ap_phi_mux_jj_phi_fu_160_p4 = jj_reg_156; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_418_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + weight_vecs_0_we0 = 1'b1; + end else begin + weight_vecs_0_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln47_3_fu_204_p2 = (indvar_flatten13_reg_123 + 8'd1); + +assign add_ln47_fu_216_p2 = (ap_phi_mux_ii_phi_fu_138_p4 + 2'd1); + +assign add_ln48_3_fu_236_p2 = (indvar_flatten_reg_145 + 7'd1); + +assign add_ln48_fu_310_p2 = (select_ln47_fu_250_p3 + 2'd1); + +assign add_ln49_fu_398_p2 = (select_ln48_fu_321_p3 + 5'd1); + +assign add_ln55_10_fu_359_p2 = (sub_ln55_6_fu_287_p2 + zext_ln55_24_fu_337_p1); + +assign add_ln55_11_fu_381_p2 = (tmp_74_cast_fu_351_p3 + zext_ln55_27_fu_377_p1); + +assign add_ln55_12_fu_392_p2 = (tmp_76_cast_fu_365_p3 + zext_ln55_26_fu_373_p1); + +assign add_ln55_9_fu_345_p2 = (sub_ln55_5_fu_274_p2 + zext_ln55_25_fu_341_p1); + +assign add_ln55_fu_263_p2 = ((sext_ln47_reg_408) + (zext_ln55_23_fu_260_p1)); + +assign and_ln47_fu_304_p2 = (xor_ln47_fu_293_p2 & icmp_ln49_fu_298_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_address0 = zext_ln55_28_fu_387_p1; + +assign icmp_ln47_fu_210_p2 = ((indvar_flatten13_reg_123 == 8'd144) ? 1'b1 : 1'b0); + +assign icmp_ln48_fu_222_p2 = ((indvar_flatten_reg_145 == 7'd48) ? 1'b1 : 1'b0); + +assign icmp_ln49_fu_298_p2 = ((kk_reg_167 == 5'd16) ? 1'b1 : 1'b0); + +assign or_ln48_fu_316_p2 = (icmp_ln48_reg_422 | and_ln47_fu_304_p2); + +assign select_ln47_3_fu_228_p3 = ((icmp_ln48_fu_222_p2[0:0] == 1'b1) ? add_ln47_fu_216_p2 : ap_phi_mux_ii_phi_fu_138_p4); + +assign select_ln47_fu_250_p3 = ((icmp_ln48_reg_422[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_160_p4); + +assign select_ln48_5_fu_329_p3 = ((and_ln47_fu_304_p2[0:0] == 1'b1) ? add_ln48_fu_310_p2 : select_ln47_fu_250_p3); + +assign select_ln48_6_fu_242_p3 = ((icmp_ln48_fu_222_p2[0:0] == 1'b1) ? 7'd1 : add_ln48_3_fu_236_p2); + +assign select_ln48_fu_321_p3 = ((or_ln48_fu_316_p2[0:0] == 1'b1) ? 5'd0 : kk_reg_167); + +assign sext_ln47_fu_200_p1 = (sub_ln55_fu_194_p2); + +assign shl_ln55_fu_268_p2 = add_ln55_fu_263_p2 << 11'd2; + +assign sub_ln55_5_fu_274_p2 = (shl_ln55_fu_268_p2 - add_ln55_fu_263_p2); + +assign sub_ln55_6_fu_287_p2 = (tmp_s_fu_280_p3 - zext_ln55_22_fu_257_p1); + +assign sub_ln55_fu_194_p2 = (zext_ln55_21_fu_190_p1 - zext_ln55_fu_178_p1); + +assign tmp_74_cast_fu_351_p3 = {{add_ln55_9_fu_345_p2}, {4'd0}}; + +assign tmp_76_cast_fu_365_p3 = {{add_ln55_10_fu_359_p2}, {4'd0}}; + +assign tmp_fu_182_p3 = {{input_indices_23_dout}, {2'd0}}; + +assign tmp_s_fu_280_p3 = {{select_ln47_3_reg_429}, {2'd0}}; + +assign weight_vecs_0_address0 = zext_ln55_29_fu_404_p1; + +assign weight_vecs_0_d0 = filter_data_q0; + +assign xor_ln47_fu_293_p2 = (icmp_ln48_reg_422 ^ 1'd1); + +assign zext_ln55_21_fu_190_p1 = tmp_fu_182_p3; + +assign zext_ln55_22_fu_257_p1 = select_ln47_3_reg_429; + +assign zext_ln55_23_fu_260_p1 = select_ln47_3_reg_429; + +assign zext_ln55_24_fu_337_p1 = select_ln48_5_fu_329_p3; + +assign zext_ln55_25_fu_341_p1 = select_ln48_5_fu_329_p3; + +assign zext_ln55_26_fu_373_p1 = select_ln48_fu_321_p3; + +assign zext_ln55_27_fu_377_p1 = select_ln48_fu_321_p3; + +assign zext_ln55_28_fu_387_p1 = add_ln55_11_fu_381_p2; + +assign zext_ln55_29_fu_404_p1 = add_ln55_12_reg_452_pp0_iter3_reg; + +assign zext_ln55_fu_178_p1 = input_indices_23_dout; + +endmodule //td_fused_top_tdf5_readFilters40 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_readInputs41 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + i_15, + j_15, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_we0, + ifmap_vec_d0, + ifmap_vec_address1, + ifmap_vec_ce1, + ifmap_vec_we1, + ifmap_vec_d1 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_pp0_stage0 = 4'd2; +parameter ap_ST_fsm_pp0_stage1 = 4'd4; +parameter ap_ST_fsm_state8 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [13:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] i_15; +input [15:0] j_15; +output [7:0] ifmap_vec_address0; +output ifmap_vec_ce0; +output ifmap_vec_we0; +output [15:0] ifmap_vec_d0; +output [7:0] ifmap_vec_address1; +output ifmap_vec_ce1; +output ifmap_vec_we1; +output [15:0] ifmap_vec_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg[7:0] ifmap_vec_address0; +reg ifmap_vec_ce0; +reg ifmap_vec_we0; +reg[15:0] ifmap_vec_d0; +reg[7:0] ifmap_vec_address1; +reg ifmap_vec_ce1; +reg ifmap_vec_we1; +reg[15:0] ifmap_vec_d1; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [5:0] indvar_flatten47_reg_194; +reg [1:0] ii_reg_206; +reg [4:0] indvar_flatten_reg_218; +reg [1:0] jj_reg_229; +reg [4:0] kk_0_i_reg_241; +wire [17:0] p_cast_i_fu_270_p1; +reg [17:0] p_cast_i_reg_931; +wire [11:0] trunc_ln22_fu_274_p1; +reg [11:0] trunc_ln22_reg_937; +wire [17:0] sext_ln22_fu_284_p1; +reg [17:0] sext_ln22_reg_943; +wire [5:0] p_cast_fu_288_p2; +reg [5:0] p_cast_reg_949; +wire [0:0] or_ln23_11_fu_308_p2; +reg [0:0] or_ln23_11_reg_955; +wire [11:0] p_mid137_fu_314_p2; +reg [11:0] p_mid137_reg_960; +wire [5:0] p_cast5_i_fu_333_p2; +reg [5:0] p_cast5_i_reg_965; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state4_pp0_stage0_iter1; +wire ap_block_state6_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [0:0] is_padding_fu_373_p2; +reg [0:0] is_padding_reg_971; +wire [0:0] icmp_ln19_fu_379_p2; +reg [0:0] icmp_ln19_reg_978; +reg [0:0] icmp_ln19_reg_978_pp0_iter1_reg; +reg [0:0] icmp_ln19_reg_978_pp0_iter2_reg; +wire [1:0] add_ln19_fu_385_p2; +reg [1:0] add_ln19_reg_982; +wire [0:0] icmp_ln20_fu_391_p2; +reg [0:0] icmp_ln20_reg_987; +wire [1:0] select_ln19_fu_397_p3; +reg [1:0] select_ln19_reg_999; +wire [5:0] p_cast5_i_mid1_fu_418_p2; +reg [5:0] p_cast5_i_mid1_reg_1004; +wire [0:0] or_ln23_13_fu_437_p2; +reg [0:0] or_ln23_13_reg_1010; +wire [1:0] add_ln20_fu_442_p2; +reg [1:0] add_ln20_reg_1017; +wire [0:0] or_ln23_15_fu_477_p2; +reg [0:0] or_ln23_15_reg_1023; +wire [4:0] add_ln20_3_fu_483_p2; +reg [4:0] add_ln20_3_reg_1030; +wire [5:0] add_ln19_3_fu_489_p2; +reg [5:0] add_ln19_3_reg_1035; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state5_pp0_stage1_iter1; +wire ap_block_state7_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +wire [1:0] select_ln19_13_fu_527_p3; +reg [1:0] select_ln19_13_reg_1040; +wire [4:0] select_ln20_fu_591_p3; +reg [4:0] select_ln20_reg_1047; +wire [1:0] select_ln20_11_fu_599_p3; +reg [1:0] select_ln20_11_reg_1053; +wire [0:0] select_ln20_12_fu_608_p3; +reg [0:0] select_ln20_12_reg_1059; +reg [0:0] select_ln20_12_reg_1059_pp0_iter1_reg; +wire [3:0] empty_87_fu_704_p1; +reg [3:0] empty_87_reg_1067; +reg [3:0] empty_87_reg_1067_pp0_iter1_reg; +wire [4:0] select_ln20_15_fu_731_p3; +reg [4:0] select_ln20_15_reg_1079; +wire [4:0] add_ln25_fu_737_p2; +reg [4:0] add_ln25_reg_1084; +reg ap_enable_reg_pp0_iter1; +wire [5:0] add_ln33_fu_769_p2; +reg [5:0] add_ln33_reg_1089; +wire [7:0] add_ln33_3_fu_790_p2; +reg [7:0] add_ln33_3_reg_1096; +wire [15:0] select_ln33_14_fu_869_p3; +reg [15:0] select_ln33_14_reg_1101; +wire [15:0] select_ln33_15_fu_890_p3; +reg [15:0] select_ln33_15_reg_1106; +reg ap_block_state1; +wire ap_block_pp0_stage1_subdone; +reg ap_condition_pp0_exit_iter0_state3; +reg ap_enable_reg_pp0_iter2; +reg [5:0] ap_phi_mux_indvar_flatten47_phi_fu_198_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_210_p4; +reg [4:0] ap_phi_mux_indvar_flatten_phi_fu_222_p4; +reg [1:0] ap_phi_mux_jj_phi_fu_233_p4; +reg [4:0] ap_phi_mux_kk_0_i_phi_fu_245_p4; +wire ap_block_pp0_stage1; +wire [63:0] sext_ln32_fu_726_p1; +wire [63:0] zext_ln33_13_fu_796_p1; +wire [63:0] sext_ln33_fu_828_p1; +wire [63:0] sext_ln33_5_fu_909_p1; +wire [63:0] sext_ln33_6_fu_926_p1; +wire [15:0] select_ln33_fu_808_p3; +wire [15:0] select_ln33_13_fu_847_p3; +wire [16:0] zext_ln19_fu_256_p1; +wire [16:0] empty_82_fu_264_p2; +wire [16:0] j_cast_i_fu_252_p1; +wire [16:0] add_ln22_fu_278_p2; +wire [5:0] empty_fu_260_p1; +wire [0:0] tmp_fu_294_p3; +wire [0:0] icmp_ln24_fu_302_p2; +wire [17:0] ii_cast_i_fu_320_p1; +wire [5:0] ii_cast_fu_324_p1; +wire [17:0] empty_83_fu_328_p2; +wire [17:0] zext_ln20_fu_344_p1; +wire [17:0] add_ln22_3_fu_348_p2; +wire [0:0] tmp_20_fu_353_p3; +wire [0:0] icmp_ln24_3_fu_361_p2; +wire [0:0] or_ln23_fu_367_p2; +wire [0:0] empty_84_fu_338_p2; +wire [17:0] ii_cast_i_mid1_fu_405_p1; +wire [5:0] ii_cast_mid1_fu_409_p1; +wire [17:0] p_mid111_fu_413_p2; +wire [0:0] p_mid113_fu_423_p2; +wire [17:0] zext_ln20_3_fu_448_p1; +wire [17:0] add_ln22_4_fu_452_p2; +wire [0:0] tmp_21_fu_457_p3; +wire [0:0] icmp_ln24_4_fu_465_p2; +wire [0:0] or_ln23_14_fu_471_p2; +wire [0:0] select_ln19_15_fu_429_p3; +wire [2:0] zext_ln22_fu_495_p1; +wire [2:0] tmp2_fu_505_p2; +wire [11:0] tmp2_cast_fu_511_p1; +wire [11:0] empty_85_fu_515_p2; +wire [5:0] row_coord_int_mid131_fu_543_p3; +wire [5:0] row_coord_int_fu_499_p3; +wire [11:0] col_coord_int_mid139_fu_549_p3; +wire [11:0] col_coord_int_fu_520_p3; +wire [0:0] icmp_ln25_fu_574_p2; +wire [0:0] xor_ln19_fu_569_p2; +wire [0:0] and_ln19_fu_580_p2; +wire [0:0] or_ln20_fu_586_p2; +wire [0:0] select_ln19_16_fu_538_p3; +wire [5:0] select_ln19_14_fu_533_p3; +wire [2:0] zext_ln22_3_fu_605_p1; +wire [2:0] tmp2_mid1_fu_622_p2; +wire [11:0] tmp2_cast_mid1_fu_628_p1; +wire [11:0] p_mid1_fu_632_p2; +wire [5:0] row_coord_int_mid1_fu_615_p3; +wire [5:0] select_ln19_17_fu_555_p3; +wire [5:0] select_ln20_13_fu_644_p3; +wire [11:0] tmp_4_fu_652_p3; +wire [8:0] tmp_5_fu_664_p3; +wire [12:0] zext_ln32_fu_660_p1; +wire [12:0] zext_ln32_16_fu_672_p1; +wire [12:0] sub_ln32_fu_676_p2; +wire [11:0] col_coord_int_mid1_fu_637_p3; +wire [11:0] select_ln19_18_fu_562_p3; +wire [11:0] select_ln20_14_fu_686_p3; +wire [13:0] sext_ln20_fu_682_p1; +wire [13:0] zext_ln32_17_fu_694_p1; +wire [13:0] add_ln32_fu_698_p2; +wire [1:0] lshr_ln_fu_708_p4; +wire [15:0] tmp_22_fu_718_p3; +wire [3:0] tmp_s_fu_745_p3; +wire [4:0] zext_ln33_10_fu_752_p1; +wire [4:0] zext_ln33_fu_742_p1; +wire [4:0] sub_ln33_fu_756_p2; +wire [5:0] sub_ln33_cast_fu_762_p1; +wire [5:0] zext_ln33_11_fu_766_p1; +wire [3:0] trunc_ln33_fu_775_p1; +wire [7:0] tmp_63_cast_fu_779_p3; +wire [7:0] zext_ln33_12_fu_787_p1; +wire [15:0] trunc_ln32_fu_800_p1; +wire [15:0] bitcast_ln32_fu_804_p1; +wire [3:0] or_ln25_fu_816_p2; +wire [9:0] tmp_23_fu_821_p3; +wire [15:0] tmp_39_i_fu_833_p4; +wire [15:0] bitcast_ln32_13_fu_843_p1; +wire [15:0] tmp_40_i_fu_855_p4; +wire [15:0] bitcast_ln32_14_fu_865_p1; +wire [15:0] tmp_41_i_fu_876_p4; +wire [15:0] bitcast_ln32_15_fu_886_p1; +wire [3:0] or_ln25_9_fu_897_p2; +wire [9:0] tmp_24_fu_902_p3; +wire [3:0] or_ln25_10_fu_914_p2; +wire [9:0] tmp_25_fu_919_p3; +wire ap_CS_fsm_state8; +reg [3:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state3) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state3)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state3); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ii_reg_206 <= select_ln19_13_reg_1040; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_206 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + indvar_flatten47_reg_194 <= add_ln19_3_reg_1035; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten47_reg_194 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + indvar_flatten_reg_218 <= select_ln20_15_reg_1079; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_218 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_229 <= select_ln20_11_reg_1053; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_229 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_i_reg_241 <= add_ln25_reg_1084; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_0_i_reg_241 <= 5'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln19_3_reg_1035 <= add_ln19_3_fu_489_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_379_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln19_reg_982 <= add_ln19_fu_385_p2; + add_ln20_3_reg_1030 <= add_ln20_3_fu_483_p2; + add_ln20_reg_1017 <= add_ln20_fu_442_p2; + icmp_ln20_reg_987 <= icmp_ln20_fu_391_p2; + or_ln23_13_reg_1010 <= or_ln23_13_fu_437_p2; + or_ln23_15_reg_1023 <= or_ln23_15_fu_477_p2; + p_cast5_i_mid1_reg_1004 <= p_cast5_i_mid1_fu_418_p2; + select_ln19_reg_999 <= select_ln19_fu_397_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + add_ln25_reg_1084 <= add_ln25_fu_737_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + add_ln33_3_reg_1096 <= add_ln33_3_fu_790_p2; + add_ln33_reg_1089 <= add_ln33_fu_769_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + empty_87_reg_1067 <= empty_87_fu_704_p1; + select_ln20_12_reg_1059 <= select_ln20_12_fu_608_p3; + select_ln20_reg_1047 <= select_ln20_fu_591_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + empty_87_reg_1067_pp0_iter1_reg <= empty_87_reg_1067; + select_ln20_12_reg_1059_pp0_iter1_reg <= select_ln20_12_reg_1059; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln19_reg_978 <= icmp_ln19_fu_379_p2; + icmp_ln19_reg_978_pp0_iter1_reg <= icmp_ln19_reg_978; + icmp_ln19_reg_978_pp0_iter2_reg <= icmp_ln19_reg_978_pp0_iter1_reg; + is_padding_reg_971 <= is_padding_fu_373_p2; + p_cast5_i_reg_965 <= p_cast5_i_fu_333_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + or_ln23_11_reg_955 <= or_ln23_11_fu_308_p2; + p_cast_i_reg_931 <= p_cast_i_fu_270_p1; + p_cast_reg_949 <= p_cast_fu_288_p2; + p_mid137_reg_960 <= p_mid137_fu_314_p2; + sext_ln22_reg_943 <= sext_ln22_fu_284_p1; + trunc_ln22_reg_937 <= trunc_ln22_fu_274_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln19_13_reg_1040 <= select_ln19_13_fu_527_p3; + select_ln20_11_reg_1053 <= select_ln20_11_fu_599_p3; + select_ln20_15_reg_1079 <= select_ln20_15_fu_731_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_978_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln33_14_reg_1101 <= select_ln33_14_fu_869_p3; + select_ln33_15_reg_1106 <= select_ln33_15_fu_890_p3; + end +end + +always @ (*) begin + if ((icmp_ln19_reg_978 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_210_p4 = select_ln19_13_reg_1040; + end else begin + ap_phi_mux_ii_phi_fu_210_p4 = ii_reg_206; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_indvar_flatten47_phi_fu_198_p4 = add_ln19_3_reg_1035; + end else begin + ap_phi_mux_indvar_flatten47_phi_fu_198_p4 = indvar_flatten47_reg_194; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_indvar_flatten_phi_fu_222_p4 = select_ln20_15_reg_1079; + end else begin + ap_phi_mux_indvar_flatten_phi_fu_222_p4 = indvar_flatten_reg_218; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_978 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_233_p4 = select_ln20_11_reg_1053; + end else begin + ap_phi_mux_jj_phi_fu_233_p4 = jj_reg_229; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_978_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_i_phi_fu_245_p4 = add_ln25_reg_1084; + end else begin + ap_phi_mux_kk_0_i_phi_fu_245_p4 = kk_0_i_reg_241; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_address0 = sext_ln33_6_fu_926_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_address0 = sext_ln33_fu_828_p1; + end else begin + ifmap_vec_address0 = 'bx; + end + end else begin + ifmap_vec_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_address1 = sext_ln33_5_fu_909_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_address1 = zext_ln33_13_fu_796_p1; + end else begin + ifmap_vec_address1 = 'bx; + end + end else begin + ifmap_vec_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + ifmap_vec_ce1 = 1'b1; + end else begin + ifmap_vec_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_d0 = select_ln33_15_reg_1106; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_d0 = select_ln33_13_fu_847_p3; + end else begin + ifmap_vec_d0 = 'bx; + end + end else begin + ifmap_vec_d0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_d1 = select_ln33_14_reg_1101; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_d1 = select_ln33_fu_808_p3; + end else begin + ifmap_vec_d1 = 'bx; + end + end else begin + ifmap_vec_d1 = 'bx; + end +end + +always @ (*) begin + if ((((icmp_ln19_reg_978_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((icmp_ln19_reg_978_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + ifmap_vec_we0 = 1'b1; + end else begin + ifmap_vec_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((icmp_ln19_reg_978_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((icmp_ln19_reg_978_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + ifmap_vec_we1 = 1'b1; + end else begin + ifmap_vec_we1 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((icmp_ln19_reg_978 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln19_reg_978 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state8; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln19_3_fu_489_p2 = (indvar_flatten47_reg_194 + 6'd1); + +assign add_ln19_fu_385_p2 = (ap_phi_mux_ii_phi_fu_210_p4 + 2'd1); + +assign add_ln20_3_fu_483_p2 = (ap_phi_mux_indvar_flatten_phi_fu_222_p4 + 5'd1); + +assign add_ln20_fu_442_p2 = (select_ln19_fu_397_p3 + 2'd1); + +assign add_ln22_3_fu_348_p2 = ((sext_ln22_reg_943) + (zext_ln20_fu_344_p1)); + +assign add_ln22_4_fu_452_p2 = ((sext_ln22_reg_943) + (zext_ln20_3_fu_448_p1)); + +assign add_ln22_fu_278_p2 = ((j_cast_i_fu_252_p1) + (17'd131071)); + +assign add_ln25_fu_737_p2 = (select_ln20_reg_1047 + 5'd4); + +assign add_ln32_fu_698_p2 = ((sext_ln20_fu_682_p1) + (zext_ln32_17_fu_694_p1)); + +assign add_ln33_3_fu_790_p2 = (tmp_63_cast_fu_779_p3 + zext_ln33_12_fu_787_p1); + +assign add_ln33_fu_769_p2 = ((sub_ln33_cast_fu_762_p1) + (zext_ln33_11_fu_766_p1)); + +assign and_ln19_fu_580_p2 = (xor_ln19_fu_569_p2 & icmp_ln25_fu_574_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd3]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln32_13_fu_843_p1 = tmp_39_i_fu_833_p4; + +assign bitcast_ln32_14_fu_865_p1 = tmp_40_i_fu_855_p4; + +assign bitcast_ln32_15_fu_886_p1 = tmp_41_i_fu_876_p4; + +assign bitcast_ln32_fu_804_p1 = trunc_ln32_fu_800_p1; + +assign col_coord_int_fu_520_p3 = ((is_padding_reg_971[0:0] == 1'b1) ? 12'd0 : empty_85_fu_515_p2); + +assign col_coord_int_mid139_fu_549_p3 = ((or_ln23_13_reg_1010[0:0] == 1'b1) ? 12'd0 : p_mid137_reg_960); + +assign col_coord_int_mid1_fu_637_p3 = ((or_ln23_15_reg_1023[0:0] == 1'b1) ? 12'd0 : p_mid1_fu_632_p2); + +assign empty_82_fu_264_p2 = ((zext_ln19_fu_256_p1) + (17'd131071)); + +assign empty_83_fu_328_p2 = ((p_cast_i_reg_931) + (ii_cast_i_fu_320_p1)); + +assign empty_84_fu_338_p2 = ((empty_83_fu_328_p2 > 18'd55) ? 1'b1 : 1'b0); + +assign empty_85_fu_515_p2 = ((tmp2_cast_fu_511_p1) + (trunc_ln22_reg_937)); + +assign empty_87_fu_704_p1 = select_ln20_fu_591_p3[3:0]; + +assign empty_fu_260_p1 = i_15[5:0]; + +assign icmp_ln19_fu_379_p2 = ((ap_phi_mux_indvar_flatten47_phi_fu_198_p4 == 6'd36) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_391_p2 = ((ap_phi_mux_indvar_flatten_phi_fu_222_p4 == 5'd12) ? 1'b1 : 1'b0); + +assign icmp_ln24_3_fu_361_p2 = (((add_ln22_3_fu_348_p2) > (18'd55)) ? 1'b1 : 1'b0); + +assign icmp_ln24_4_fu_465_p2 = (((add_ln22_4_fu_452_p2) > (18'd55)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_302_p2 = (((add_ln22_fu_278_p2) > (17'd55)) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_574_p2 = ((ap_phi_mux_kk_0_i_phi_fu_245_p4 == 5'd16) ? 1'b1 : 1'b0); + +assign ii_cast_fu_324_p1 = ap_phi_mux_ii_phi_fu_210_p4; + +assign ii_cast_i_fu_320_p1 = ap_phi_mux_ii_phi_fu_210_p4; + +assign ii_cast_i_mid1_fu_405_p1 = add_ln19_fu_385_p2; + +assign ii_cast_mid1_fu_409_p1 = add_ln19_fu_385_p2; + +assign in_data_address0 = sext_ln32_fu_726_p1; + +assign is_padding_fu_373_p2 = (or_ln23_fu_367_p2 | empty_84_fu_338_p2); + +assign j_cast_i_fu_252_p1 = j_15; + +assign lshr_ln_fu_708_p4 = {{select_ln20_fu_591_p3[3:2]}}; + +assign or_ln20_fu_586_p2 = (icmp_ln20_reg_987 | and_ln19_fu_580_p2); + +assign or_ln23_11_fu_308_p2 = (tmp_fu_294_p3 | icmp_ln24_fu_302_p2); + +assign or_ln23_13_fu_437_p2 = (p_mid113_fu_423_p2 | or_ln23_11_reg_955); + +assign or_ln23_14_fu_471_p2 = (tmp_21_fu_457_p3 | icmp_ln24_4_fu_465_p2); + +assign or_ln23_15_fu_477_p2 = (select_ln19_15_fu_429_p3 | or_ln23_14_fu_471_p2); + +assign or_ln23_fu_367_p2 = (tmp_20_fu_353_p3 | icmp_ln24_3_fu_361_p2); + +assign or_ln25_10_fu_914_p2 = (empty_87_reg_1067_pp0_iter1_reg | 4'd3); + +assign or_ln25_9_fu_897_p2 = (empty_87_reg_1067_pp0_iter1_reg | 4'd2); + +assign or_ln25_fu_816_p2 = (empty_87_reg_1067_pp0_iter1_reg | 4'd1); + +assign p_cast5_i_fu_333_p2 = (p_cast_reg_949 + ii_cast_fu_324_p1); + +assign p_cast5_i_mid1_fu_418_p2 = (p_cast_reg_949 + ii_cast_mid1_fu_409_p1); + +assign p_cast_fu_288_p2 = ((empty_fu_260_p1) + (6'd63)); + +assign p_cast_i_fu_270_p1 = (empty_82_fu_264_p2); + +assign p_mid111_fu_413_p2 = ((p_cast_i_reg_931) + (ii_cast_i_mid1_fu_405_p1)); + +assign p_mid113_fu_423_p2 = ((p_mid111_fu_413_p2 > 18'd55) ? 1'b1 : 1'b0); + +assign p_mid137_fu_314_p2 = ((trunc_ln22_fu_274_p1) + (12'd4095)); + +assign p_mid1_fu_632_p2 = ((tmp2_cast_mid1_fu_628_p1) + (trunc_ln22_reg_937)); + +assign row_coord_int_fu_499_p3 = ((is_padding_reg_971[0:0] == 1'b1) ? 6'd0 : p_cast5_i_reg_965); + +assign row_coord_int_mid131_fu_543_p3 = ((or_ln23_13_reg_1010[0:0] == 1'b1) ? 6'd0 : p_cast5_i_mid1_reg_1004); + +assign row_coord_int_mid1_fu_615_p3 = ((or_ln23_15_reg_1023[0:0] == 1'b1) ? 6'd0 : select_ln19_14_fu_533_p3); + +assign select_ln19_13_fu_527_p3 = ((icmp_ln20_reg_987[0:0] == 1'b1) ? add_ln19_reg_982 : ii_reg_206); + +assign select_ln19_14_fu_533_p3 = ((icmp_ln20_reg_987[0:0] == 1'b1) ? p_cast5_i_mid1_reg_1004 : p_cast5_i_reg_965); + +assign select_ln19_15_fu_429_p3 = ((icmp_ln20_fu_391_p2[0:0] == 1'b1) ? p_mid113_fu_423_p2 : empty_84_fu_338_p2); + +assign select_ln19_16_fu_538_p3 = ((icmp_ln20_reg_987[0:0] == 1'b1) ? or_ln23_13_reg_1010 : is_padding_reg_971); + +assign select_ln19_17_fu_555_p3 = ((icmp_ln20_reg_987[0:0] == 1'b1) ? row_coord_int_mid131_fu_543_p3 : row_coord_int_fu_499_p3); + +assign select_ln19_18_fu_562_p3 = ((icmp_ln20_reg_987[0:0] == 1'b1) ? col_coord_int_mid139_fu_549_p3 : col_coord_int_fu_520_p3); + +assign select_ln19_fu_397_p3 = ((icmp_ln20_fu_391_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_233_p4); + +assign select_ln20_11_fu_599_p3 = ((and_ln19_fu_580_p2[0:0] == 1'b1) ? add_ln20_reg_1017 : select_ln19_reg_999); + +assign select_ln20_12_fu_608_p3 = ((and_ln19_fu_580_p2[0:0] == 1'b1) ? or_ln23_15_reg_1023 : select_ln19_16_fu_538_p3); + +assign select_ln20_13_fu_644_p3 = ((and_ln19_fu_580_p2[0:0] == 1'b1) ? row_coord_int_mid1_fu_615_p3 : select_ln19_17_fu_555_p3); + +assign select_ln20_14_fu_686_p3 = ((and_ln19_fu_580_p2[0:0] == 1'b1) ? col_coord_int_mid1_fu_637_p3 : select_ln19_18_fu_562_p3); + +assign select_ln20_15_fu_731_p3 = ((icmp_ln20_reg_987[0:0] == 1'b1) ? 5'd1 : add_ln20_3_reg_1030); + +assign select_ln20_fu_591_p3 = ((or_ln20_fu_586_p2[0:0] == 1'b1) ? 5'd0 : ap_phi_mux_kk_0_i_phi_fu_245_p4); + +assign select_ln33_13_fu_847_p3 = ((select_ln20_12_reg_1059_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_13_fu_843_p1); + +assign select_ln33_14_fu_869_p3 = ((select_ln20_12_reg_1059_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_14_fu_865_p1); + +assign select_ln33_15_fu_890_p3 = ((select_ln20_12_reg_1059_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_15_fu_886_p1); + +assign select_ln33_fu_808_p3 = ((select_ln20_12_reg_1059_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_fu_804_p1); + +assign sext_ln20_fu_682_p1 = (sub_ln32_fu_676_p2); + +assign sext_ln22_fu_284_p1 = add_ln22_fu_278_p2; + +assign sext_ln32_fu_726_p1 = (tmp_22_fu_718_p3); + +assign sext_ln33_5_fu_909_p1 = (tmp_24_fu_902_p3); + +assign sext_ln33_6_fu_926_p1 = (tmp_25_fu_919_p3); + +assign sext_ln33_fu_828_p1 = (tmp_23_fu_821_p3); + +assign sub_ln32_fu_676_p2 = (zext_ln32_fu_660_p1 - zext_ln32_16_fu_672_p1); + +assign sub_ln33_cast_fu_762_p1 = (sub_ln33_fu_756_p2); + +assign sub_ln33_fu_756_p2 = (zext_ln33_10_fu_752_p1 - zext_ln33_fu_742_p1); + +assign tmp2_cast_fu_511_p1 = (tmp2_fu_505_p2); + +assign tmp2_cast_mid1_fu_628_p1 = (tmp2_mid1_fu_622_p2); + +assign tmp2_fu_505_p2 = ((zext_ln22_fu_495_p1) + (3'd7)); + +assign tmp2_mid1_fu_622_p2 = ((zext_ln22_3_fu_605_p1) + (3'd7)); + +assign tmp_20_fu_353_p3 = add_ln22_3_fu_348_p2[32'd17]; + +assign tmp_21_fu_457_p3 = add_ln22_4_fu_452_p2[32'd17]; + +assign tmp_22_fu_718_p3 = {{add_ln32_fu_698_p2}, {lshr_ln_fu_708_p4}}; + +assign tmp_23_fu_821_p3 = {{add_ln33_reg_1089}, {or_ln25_fu_816_p2}}; + +assign tmp_24_fu_902_p3 = {{add_ln33_reg_1089}, {or_ln25_9_fu_897_p2}}; + +assign tmp_25_fu_919_p3 = {{add_ln33_reg_1089}, {or_ln25_10_fu_914_p2}}; + +assign tmp_39_i_fu_833_p4 = {{in_data_q0[31:16]}}; + +assign tmp_40_i_fu_855_p4 = {{in_data_q0[47:32]}}; + +assign tmp_41_i_fu_876_p4 = {{in_data_q0[63:48]}}; + +assign tmp_4_fu_652_p3 = {{select_ln20_13_fu_644_p3}, {6'd0}}; + +assign tmp_5_fu_664_p3 = {{select_ln20_13_fu_644_p3}, {3'd0}}; + +assign tmp_63_cast_fu_779_p3 = {{trunc_ln33_fu_775_p1}, {4'd0}}; + +assign tmp_fu_294_p3 = add_ln22_fu_278_p2[32'd16]; + +assign tmp_s_fu_745_p3 = {{select_ln19_13_reg_1040}, {2'd0}}; + +assign trunc_ln22_fu_274_p1 = j_15[11:0]; + +assign trunc_ln32_fu_800_p1 = in_data_q0[15:0]; + +assign trunc_ln33_fu_775_p1 = add_ln33_fu_769_p2[3:0]; + +assign xor_ln19_fu_569_p2 = (icmp_ln20_reg_987 ^ 1'd1); + +assign zext_ln19_fu_256_p1 = i_15; + +assign zext_ln20_3_fu_448_p1 = add_ln20_fu_442_p2; + +assign zext_ln20_fu_344_p1 = ap_phi_mux_jj_phi_fu_233_p4; + +assign zext_ln22_3_fu_605_p1 = add_ln20_reg_1017; + +assign zext_ln22_fu_495_p1 = jj_reg_229; + +assign zext_ln32_16_fu_672_p1 = tmp_5_fu_664_p3; + +assign zext_ln32_17_fu_694_p1 = select_ln20_14_fu_686_p3; + +assign zext_ln32_fu_660_p1 = tmp_4_fu_652_p3; + +assign zext_ln33_10_fu_752_p1 = tmp_s_fu_745_p3; + +assign zext_ln33_11_fu_766_p1 = select_ln20_11_reg_1053; + +assign zext_ln33_12_fu_787_p1 = select_ln20_reg_1047; + +assign zext_ln33_13_fu_796_p1 = add_ln33_3_reg_1096; + +assign zext_ln33_fu_742_p1 = select_ln19_13_reg_1040; + +endmodule //td_fused_top_tdf5_readInputs41 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf5_writeOutputs_unaligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_idle, + ap_ready, + i, + j, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1, + max_vals_5_0 +); + +parameter ap_ST_fsm_state1 = 2'd1; +parameter ap_ST_fsm_state2 = 2'd2; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +input [4:0] i; +input [9:0] j; +output [14:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; +input [15:0] max_vals_5_0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg out_data_ce1; +reg out_data_we1; + + reg [1:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] outputCount_5; +reg [15:0] outputChanIdx_5; +reg [15:0] outputRow_11_0; +reg [15:0] outputRow_11_1; +reg [15:0] outputRow_11_2; +reg [15:0] outputRow_11_3; +wire [15:0] add_ln87_fu_173_p2; +wire [0:0] icmp_ln88_fu_179_p2; +reg [0:0] icmp_ln88_reg_293; +reg [15:0] ap_phi_mux_empty_phi_fu_90_p4; +reg [15:0] empty_reg_87; +wire ap_CS_fsm_state2; +wire [63:0] zext_ln94_8_fu_207_p1; +wire [15:0] select_ln97_fu_265_p3; +wire [1:0] trunc_ln86_fu_145_p1; +reg [15:0] ap_sig_allocacmp_outputRow_11_0_load; +reg [15:0] ap_sig_allocacmp_outputRow_11_1_load; +reg [15:0] ap_sig_allocacmp_outputRow_11_2_load; +reg [15:0] ap_sig_allocacmp_outputRow_11_3_load; +wire [6:0] tmp_s_fu_105_p3; +wire [9:0] tmp_fu_97_p3; +wire [9:0] zext_ln94_fu_113_p1; +wire [9:0] sub_ln94_fu_117_p2; +wire [9:0] add_ln94_fu_123_p2; +wire [6:0] trunc_ln94_fu_193_p1; +wire [14:0] tmp_60_cast_fu_129_p3; +wire [14:0] zext_ln94_7_fu_197_p1; +wire [14:0] add_ln94_4_fu_201_p2; +wire [15:0] bitcast_ln94_12_fu_236_p1; +wire [15:0] bitcast_ln94_11_fu_228_p1; +wire [15:0] bitcast_ln94_10_fu_220_p1; +wire [15:0] bitcast_ln94_fu_212_p1; +wire [15:0] add_ln96_fu_253_p2; +wire [0:0] icmp_ln97_fu_259_p2; +reg [1:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 2'd1; +#0 outputCount_5 = 16'd0; +#0 outputChanIdx_5 = 16'd0; +#0 outputRow_11_0 = 16'd0; +#0 outputRow_11_1 = 16'd0; +#0 outputRow_11_2 = 16'd0; +#0 outputRow_11_3 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_reg_293 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + empty_reg_87 <= 16'd0; + end else if (((ap_start == 1'b1) & (icmp_ln88_fu_179_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + empty_reg_87 <= add_ln87_fu_173_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + icmp_ln88_reg_293 <= icmp_ln88_fu_179_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_start == 1'b1) & (icmp_ln88_fu_179_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + outputChanIdx_5 <= select_ln97_fu_265_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + outputCount_5 <= ap_phi_mux_empty_phi_fu_90_p4; + end +end + +always @ (posedge ap_clk) begin + if (((ap_start == 1'b1) & (trunc_ln86_fu_145_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_11_0 <= max_vals_5_0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_start == 1'b1) & (trunc_ln86_fu_145_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_11_1 <= max_vals_5_0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_start == 1'b1) & (trunc_ln86_fu_145_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_11_2 <= max_vals_5_0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_start == 1'b1) & (trunc_ln86_fu_145_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_11_3 <= max_vals_5_0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_reg_293 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_phi_mux_empty_phi_fu_90_p4 = 16'd0; + end else begin + ap_phi_mux_empty_phi_fu_90_p4 = empty_reg_87; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_145_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_sig_allocacmp_outputRow_11_0_load = max_vals_5_0; + end else begin + ap_sig_allocacmp_outputRow_11_0_load = outputRow_11_0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_145_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state1))) begin + ap_sig_allocacmp_outputRow_11_1_load = max_vals_5_0; + end else begin + ap_sig_allocacmp_outputRow_11_1_load = outputRow_11_1; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_145_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state1))) begin + ap_sig_allocacmp_outputRow_11_2_load = max_vals_5_0; + end else begin + ap_sig_allocacmp_outputRow_11_2_load = outputRow_11_2; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_145_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state1))) begin + ap_sig_allocacmp_outputRow_11_3_load = max_vals_5_0; + end else begin + ap_sig_allocacmp_outputRow_11_3_load = outputRow_11_3; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1)))) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_start == 1'b1) & (icmp_ln88_fu_179_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln87_fu_173_p2 = (outputCount_5 + 16'd1); + +assign add_ln94_4_fu_201_p2 = (tmp_60_cast_fu_129_p3 + zext_ln94_7_fu_197_p1); + +assign add_ln94_fu_123_p2 = (sub_ln94_fu_117_p2 + j); + +assign add_ln96_fu_253_p2 = (outputChanIdx_5 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign bitcast_ln94_10_fu_220_p1 = ap_sig_allocacmp_outputRow_11_1_load; + +assign bitcast_ln94_11_fu_228_p1 = ap_sig_allocacmp_outputRow_11_2_load; + +assign bitcast_ln94_12_fu_236_p1 = ap_sig_allocacmp_outputRow_11_3_load; + +assign bitcast_ln94_fu_212_p1 = ap_sig_allocacmp_outputRow_11_0_load; + +assign icmp_ln88_fu_179_p2 = ((add_ln87_fu_173_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign icmp_ln97_fu_259_p2 = ((add_ln96_fu_253_p2 == 16'd32) ? 1'b1 : 1'b0); + +assign out_data_address1 = zext_ln94_8_fu_207_p1; + +assign out_data_d1 = {{{{bitcast_ln94_12_fu_236_p1}, {bitcast_ln94_11_fu_228_p1}}, {bitcast_ln94_10_fu_220_p1}}, {bitcast_ln94_fu_212_p1}}; + +assign select_ln97_fu_265_p3 = ((icmp_ln97_fu_259_p2[0:0] == 1'b1) ? 16'd0 : add_ln96_fu_253_p2); + +assign sub_ln94_fu_117_p2 = (tmp_fu_97_p3 - zext_ln94_fu_113_p1); + +assign tmp_60_cast_fu_129_p3 = {{add_ln94_fu_123_p2}, {5'd0}}; + +assign tmp_fu_97_p3 = {{i}, {5'd0}}; + +assign tmp_s_fu_105_p3 = {{i}, {2'd0}}; + +assign trunc_ln86_fu_145_p1 = outputCount_5[1:0]; + +assign trunc_ln94_fu_193_p1 = outputChanIdx_5[6:0]; + +assign zext_ln94_7_fu_197_p1 = trunc_ln94_fu_193_p1; + +assign zext_ln94_8_fu_207_p1 = add_ln94_4_fu_201_p2; + +assign zext_ln94_fu_113_p1 = tmp_s_fu_105_p3; + +endmodule //td_fused_top_tdf5_writeOutputs_unaligned +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_19 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [14:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [14:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [12:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [12:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [11:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [11:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [4:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [4:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [14:0] dataflow_in_loop_TOP_LOOP37644_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP37644_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP37644_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP37644_U0_in_data_we0; +wire [14:0] dataflow_in_loop_TOP_LOOP37644_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP37644_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP37644_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP37644_U0_in_data_we1; +wire [11:0] dataflow_in_loop_TOP_LOOP37644_U0_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP37644_U0_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP37644_U0_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP37644_U0_filter_data_we0; +wire [11:0] dataflow_in_loop_TOP_LOOP37644_U0_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP37644_U0_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP37644_U0_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP37644_U0_filter_data_we1; +wire [4:0] dataflow_in_loop_TOP_LOOP37644_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP37644_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP37644_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP37644_U0_adjustments_we0; +wire [4:0] dataflow_in_loop_TOP_LOOP37644_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP37644_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP37644_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP37644_U0_adjustments_we1; +wire [12:0] dataflow_in_loop_TOP_LOOP37644_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP37644_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP37644_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP37644_U0_out_data_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP37644_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP37644_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP37644_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP37644_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP37644_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP37644_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP37644_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP37644_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP37644_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP37644_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP37644_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP37644_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP37644_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [14:0] loop_dataflow_input_count; +reg [14:0] loop_dataflow_output_count; +wire [14:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP37644_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP37644_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 15'd0; +#0 loop_dataflow_output_count = 15'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP37644 dataflow_in_loop_TOP_LOOP37644_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP37644_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP37644_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP37644_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP37644_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP37644_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP37644_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP37644_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP37644_U0_in_data_we1), + .filter_data_address0(dataflow_in_loop_TOP_LOOP37644_U0_filter_data_address0), + .filter_data_ce0(dataflow_in_loop_TOP_LOOP37644_U0_filter_data_ce0), + .filter_data_d0(dataflow_in_loop_TOP_LOOP37644_U0_filter_data_d0), + .filter_data_q0(filter_data_q0), + .filter_data_we0(dataflow_in_loop_TOP_LOOP37644_U0_filter_data_we0), + .filter_data_address1(dataflow_in_loop_TOP_LOOP37644_U0_filter_data_address1), + .filter_data_ce1(dataflow_in_loop_TOP_LOOP37644_U0_filter_data_ce1), + .filter_data_d1(dataflow_in_loop_TOP_LOOP37644_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(dataflow_in_loop_TOP_LOOP37644_U0_filter_data_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP37644_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP37644_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP37644_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP37644_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP37644_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP37644_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP37644_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP37644_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP37644_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP37644_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP37644_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP37644_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP37644_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP37644_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP37644_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP37644_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP37644_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP37644_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP37644_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP37644_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP37644_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP37644_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP37644_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 15'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37644_U0_ap_ready == 1'b1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 15'd1); + end else if (((dataflow_in_loop_TOP_LOOP37644_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= 15'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 15'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37644_U0_ap_done == 1'b1) & (dataflow_in_loop_TOP_LOOP37644_U0_ap_continue == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 15'd1); + end else if (((dataflow_in_loop_TOP_LOOP37644_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37644_U0_ap_continue == 1'b1))) begin + loop_dataflow_output_count <= 15'd0; + end + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP37644_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP37644_U0_ap_idle == 1'b1) & (loop_dataflow_output_count == 15'd0) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP37644_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP37644_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP37644_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP37644_U0_adjustments_address0; + +assign adjustments_address1 = 5'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP37644_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP37644_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP37644_U0_ap_ready; + +assign bound_minus_1 = (15'd25088 - 15'd1); + +assign dataflow_in_loop_TOP_LOOP37644_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP37644_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP37644_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP37644_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP37644_U0_start_write = 1'b0; + +assign filter_data_address0 = dataflow_in_loop_TOP_LOOP37644_U0_filter_data_address0; + +assign filter_data_address1 = 12'd0; + +assign filter_data_ce0 = dataflow_in_loop_TOP_LOOP37644_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP37644_U0_in_data_address0; + +assign in_data_address1 = 15'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP37644_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP37644_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 13'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP37644_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP37644_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP37644_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP37644_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP37644_U0_out_data_write; + +endmodule //td_fused_top_tdf6_19 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 8'd1; +parameter ap_ST_fsm_pp0_stage0 = 8'd2; +parameter ap_ST_fsm_pp0_stage1 = 8'd4; +parameter ap_ST_fsm_pp0_stage2 = 8'd8; +parameter ap_ST_fsm_pp0_stage3 = 8'd16; +parameter ap_ST_fsm_state12 = 8'd32; +parameter ap_ST_fsm_state13 = 8'd64; +parameter ap_ST_fsm_state14 = 8'd128; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [6:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [6:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[6:0] accum_in_0_address0; +reg accum_in_0_ce0; +reg[6:0] accum_in_0_address1; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [7:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] x_reg_170; +reg [15:0] psum_7_08_reg_182; +reg [15:0] psum_6_07_reg_194; +reg [15:0] psum_5_06_reg_206; +reg [15:0] psum_4_05_reg_218; +reg [15:0] psum_3_04_reg_230; +reg [15:0] psum_2_03_reg_242; +reg [15:0] psum_1_02_reg_254; +reg [15:0] psum_0_01_reg_266; +wire [0:0] tmp_fu_323_p3; +reg [0:0] tmp_reg_494; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state6_pp0_stage0_iter1; +wire ap_block_state10_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] tmp_reg_494_pp0_iter1_reg; +reg [0:0] tmp_reg_494_pp0_iter2_reg; +wire [6:0] trunc_ln25_fu_336_p1; +reg [6:0] trunc_ln25_reg_498; +reg [15:0] accum_in_0_load_reg_518; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state7_pp0_stage1_iter1; +wire ap_block_state11_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_0_load_22_reg_523; +reg [15:0] accum_in_0_load_23_reg_538; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state8_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_0_load_24_reg_543; +wire [7:0] add_ln25_fu_391_p2; +reg [7:0] add_ln25_reg_558; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state9_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_0_load_25_reg_563; +reg [15:0] accum_in_0_load_26_reg_568; +reg [15:0] accum_in_0_load_27_reg_583; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_0_load_28_reg_588; +wire [15:0] grp_fu_307_p2; +wire [15:0] grp_fu_312_p2; +reg ap_enable_reg_pp0_iter2; +wire [3:0] add_ln33_fu_434_p2; +wire ap_CS_fsm_state13; +wire [0:0] tmp_19_fu_417_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage1_subdone; +reg [7:0] ap_phi_mux_x_phi_fu_174_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_186_p4; +wire ap_block_pp0_stage1; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_198_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_210_p4; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_222_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_234_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_03_phi_fu_246_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_278; +wire ap_CS_fsm_state12; +reg [15:0] ap_phi_mux_phi_ln45_phi_fu_292_p8; +wire [2:0] trunc_ln33_fu_430_p1; +wire [63:0] zext_ln25_fu_331_p1; +wire [63:0] zext_ln29_fu_346_p1; +wire [63:0] zext_ln29_7_fu_356_p1; +wire [63:0] zext_ln29_8_fu_366_p1; +wire [63:0] zext_ln29_9_fu_376_p1; +wire [63:0] zext_ln29_10_fu_386_p1; +wire [63:0] zext_ln29_11_fu_402_p1; +wire [63:0] zext_ln29_12_fu_412_p1; +wire [63:0] zext_ln33_fu_425_p1; +wire [63:0] zext_ln33_2_fu_446_p1; +reg [15:0] grp_fu_307_p0; +reg [15:0] grp_fu_307_p1; +reg [15:0] grp_fu_312_p0; +reg [15:0] grp_fu_312_p1; +wire [6:0] or_ln29_fu_340_p2; +wire [6:0] or_ln29_7_fu_351_p2; +wire [6:0] or_ln29_8_fu_361_p2; +wire [6:0] or_ln29_9_fu_371_p2; +wire [6:0] or_ln29_10_fu_381_p2; +wire [6:0] or_ln29_11_fu_397_p2; +wire [6:0] or_ln29_12_fu_407_p2; +wire [2:0] or_ln33_fu_440_p2; +wire [0:0] icmp_ln45_fu_451_p2; +wire [0:0] icmp_ln45_3_fu_465_p2; +wire [15:0] select_ln45_fu_457_p3; +wire [0:0] icmp_ln45_4_fu_479_p2; +wire [15:0] select_ln45_3_fu_471_p3; +wire ap_CS_fsm_state14; +reg [7:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_517; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 8'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U363( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_307_p0), + .din1(grp_fu_307_p1), + .dout(grp_fu_307_p2) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U364( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_312_p0), + .din1(grp_fu_312_p1), + .dout(grp_fu_312_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + q_reg_278 <= 4'd0; + end else if (((tmp_19_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + q_reg_278 <= add_ln33_fu_434_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + x_reg_170 <= add_ln25_reg_558; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_170 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_22_reg_523 <= accum_in_0_q0; + accum_in_0_load_reg_518 <= accum_in_0_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage2_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_23_reg_538 <= accum_in_0_q1; + accum_in_0_load_24_reg_543 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage3_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_25_reg_563 <= accum_in_0_q1; + accum_in_0_load_26_reg_568 <= accum_in_0_q0; + add_ln25_reg_558 <= add_ln25_fu_391_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_0_load_27_reg_583 <= accum_in_0_q1; + accum_in_0_load_28_reg_588 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_0_01_reg_266 <= grp_fu_307_p2; + psum_1_02_reg_254 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_2_03_reg_242 <= grp_fu_307_p2; + psum_3_04_reg_230 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + psum_4_05_reg_218 <= grp_fu_307_p2; + psum_5_06_reg_206 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + psum_6_07_reg_194 <= grp_fu_307_p2; + psum_7_08_reg_182 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + tmp_reg_494 <= ap_phi_mux_x_phi_fu_174_p4[32'd7]; + tmp_reg_494_pp0_iter1_reg <= tmp_reg_494; + tmp_reg_494_pp0_iter2_reg <= tmp_reg_494_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_fu_323_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln25_reg_498 <= trunc_ln25_fu_336_p1; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address0 = zext_ln29_12_fu_412_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address0 = zext_ln29_10_fu_386_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address0 = zext_ln29_8_fu_366_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address0 = zext_ln29_fu_346_p1; + end else begin + accum_in_0_address0 = 'bx; + end + end else begin + accum_in_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address1 = zext_ln29_11_fu_402_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address1 = zext_ln29_9_fu_376_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address1 = zext_ln29_7_fu_356_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address1 = zext_ln25_fu_331_p1; + end else begin + accum_in_0_address1 = 'bx; + end + end else begin + accum_in_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_19_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_19_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_reg_494 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_19_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + if ((trunc_ln33_fu_430_p1 == 3'd0)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_0_01_reg_266; + end else if ((1'b1 == ap_condition_517)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_6_07_reg_194; + end else if ((trunc_ln33_fu_430_p1 == 3'd4)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_4_05_reg_218; + end else if ((trunc_ln33_fu_430_p1 == 3'd2)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_2_03_reg_242; + end else begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_x_phi_fu_174_p4 = add_ln25_reg_558; + end else begin + ap_phi_mux_x_phi_fu_174_p4 = x_reg_170; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_307_p0 = ap_phi_mux_psum_6_07_phi_fu_198_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_307_p0 = ap_phi_mux_psum_4_05_phi_fu_222_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_307_p0 = ap_phi_mux_psum_2_03_phi_fu_246_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_307_p0 = grp_fu_307_p2; + end else begin + grp_fu_307_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_307_p1 = accum_in_0_load_27_reg_583; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_307_p1 = accum_in_0_load_25_reg_563; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_307_p1 = accum_in_0_load_23_reg_538; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_307_p1 = accum_in_0_load_reg_518; + end else begin + grp_fu_307_p1 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_312_p0 = ap_phi_mux_psum_7_08_phi_fu_186_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_312_p0 = ap_phi_mux_psum_5_06_phi_fu_210_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_312_p0 = ap_phi_mux_psum_3_04_phi_fu_234_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_312_p0 = grp_fu_312_p2; + end else begin + grp_fu_312_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_312_p1 = accum_in_0_load_28_reg_588; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_312_p1 = accum_in_0_load_26_reg_568; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_312_p1 = accum_in_0_load_24_reg_543; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_312_p1 = accum_in_0_load_22_reg_523; + end else begin + grp_fu_312_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_494 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_494 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + if (((tmp_19_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_state14; + end + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln33_2_fu_446_p1; + +assign accum_out_address1 = zext_ln33_fu_425_p1; + +assign accum_out_d0 = ((icmp_ln45_4_fu_479_p2[0:0] == 1'b1) ? psum_5_06_reg_206 : select_ln45_3_fu_471_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln45_phi_fu_292_p8; + +assign add_ln25_fu_391_p2 = (x_reg_170 + 8'd8); + +assign add_ln33_fu_434_p2 = (q_reg_278 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_state14 = ap_CS_fsm[32'd7]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_517 = (~(trunc_ln33_fu_430_p1 == 3'd0) & ~(trunc_ln33_fu_430_p1 == 3'd4) & ~(trunc_ln33_fu_430_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_03_phi_fu_246_p4 = grp_fu_307_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_234_p4 = grp_fu_312_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_222_p4 = grp_fu_307_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_210_p4 = grp_fu_312_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_198_p4 = grp_fu_307_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_186_p4 = grp_fu_312_p2; + +assign icmp_ln45_3_fu_465_p2 = ((or_ln33_fu_440_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln45_4_fu_479_p2 = ((or_ln33_fu_440_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln45_fu_451_p2 = ((or_ln33_fu_440_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln29_10_fu_381_p2 = (trunc_ln25_reg_498 | 7'd5); + +assign or_ln29_11_fu_397_p2 = (trunc_ln25_reg_498 | 7'd6); + +assign or_ln29_12_fu_407_p2 = (trunc_ln25_reg_498 | 7'd7); + +assign or_ln29_7_fu_351_p2 = (trunc_ln25_reg_498 | 7'd2); + +assign or_ln29_8_fu_361_p2 = (trunc_ln25_reg_498 | 7'd3); + +assign or_ln29_9_fu_371_p2 = (trunc_ln25_reg_498 | 7'd4); + +assign or_ln29_fu_340_p2 = (trunc_ln25_fu_336_p1 | 7'd1); + +assign or_ln33_fu_440_p2 = (trunc_ln33_fu_430_p1 | 3'd1); + +assign select_ln45_3_fu_471_p3 = ((icmp_ln45_3_fu_465_p2[0:0] == 1'b1) ? psum_3_04_reg_230 : select_ln45_fu_457_p3); + +assign select_ln45_fu_457_p3 = ((icmp_ln45_fu_451_p2[0:0] == 1'b1) ? psum_1_02_reg_254 : psum_7_08_reg_182); + +assign tmp_19_fu_417_p3 = q_reg_278[32'd3]; + +assign tmp_fu_323_p3 = ap_phi_mux_x_phi_fu_174_p4[32'd7]; + +assign trunc_ln25_fu_336_p1 = ap_phi_mux_x_phi_fu_174_p4[6:0]; + +assign trunc_ln33_fu_430_p1 = q_reg_278[2:0]; + +assign zext_ln25_fu_331_p1 = ap_phi_mux_x_phi_fu_174_p4; + +assign zext_ln29_10_fu_386_p1 = or_ln29_10_fu_381_p2; + +assign zext_ln29_11_fu_402_p1 = or_ln29_11_fu_397_p2; + +assign zext_ln29_12_fu_412_p1 = or_ln29_12_fu_407_p2; + +assign zext_ln29_7_fu_356_p1 = or_ln29_7_fu_351_p2; + +assign zext_ln29_8_fu_366_p1 = or_ln29_8_fu_361_p2; + +assign zext_ln29_9_fu_376_p1 = or_ln29_9_fu_371_p2; + +assign zext_ln29_fu_346_p1 = or_ln29_fu_340_p2; + +assign zext_ln33_2_fu_446_p1 = or_ln33_fu_440_p2; + +assign zext_ln33_fu_425_p1 = q_reg_278; + +endmodule //td_fused_top_tdf6_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_8, + accum_in_8_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 7'd1; +parameter ap_ST_fsm_state2 = 7'd2; +parameter ap_ST_fsm_state3 = 7'd4; +parameter ap_ST_fsm_state4 = 7'd8; +parameter ap_ST_fsm_state5 = 7'd16; +parameter ap_ST_fsm_state6 = 7'd32; +parameter ap_ST_fsm_state7 = 7'd64; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_8; +output accum_in_8_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_8; +reg accum_in_8_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [6:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln57_fu_74_p2; +reg [3:0] add_ln57_reg_91; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln57_fu_85_p2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state7; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln57_fu_80_p1; +reg [15:0] accum_in_8_preg; +reg [6:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 7'd1; +#0 accum_in_8_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U367( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_q0), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_8_preg <= 16'd0; + end else begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_8_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + i_1_1_reg_44 <= add_ln57_reg_91; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln57_reg_91 <= add_ln57_fu_74_p2; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_8 = sum_01_reg_55; + end else begin + accum_in_8 = accum_in_8_preg; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_8_ap_vld = 1'b1; + end else begin + accum_in_8_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln57_fu_80_p1; + +assign add_ln57_fu_74_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln57_fu_85_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln57_fu_80_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf6_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 17'd1; +parameter ap_ST_fsm_state2 = 17'd2; +parameter ap_ST_fsm_state3 = 17'd4; +parameter ap_ST_fsm_state4 = 17'd8; +parameter ap_ST_fsm_state5 = 17'd16; +parameter ap_ST_fsm_state6 = 17'd32; +parameter ap_ST_fsm_state7 = 17'd64; +parameter ap_ST_fsm_state8 = 17'd128; +parameter ap_ST_fsm_state9 = 17'd256; +parameter ap_ST_fsm_state10 = 17'd512; +parameter ap_ST_fsm_state11 = 17'd1024; +parameter ap_ST_fsm_state12 = 17'd2048; +parameter ap_ST_fsm_state13 = 17'd4096; +parameter ap_ST_fsm_state14 = 17'd8192; +parameter ap_ST_fsm_state15 = 17'd16384; +parameter ap_ST_fsm_state16 = 17'd32768; +parameter ap_ST_fsm_state17 = 17'd65536; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_read; +output [4:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [4:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg indices_23_read; + +reg ap_done_reg; + reg [16:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +wire ap_CS_fsm_state4; +reg [15:0] tmp_34_i_i_reg_167; +reg [15:0] tmp_35_i_i_reg_172; +wire [15:0] grp_fu_81_p2; +reg [15:0] sub_i_i_i_reg_177; +wire ap_CS_fsm_state8; +wire ap_CS_fsm_state9; +wire [15:0] grp_fu_86_p2; +reg [15:0] mul_i_i_i_reg_187; +wire ap_CS_fsm_state12; +wire ap_CS_fsm_state13; +wire [63:0] zext_ln220_fu_90_p1; +reg ap_block_state1; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_77_p1; +wire [15:0] grp_fu_81_p1; +wire [15:0] grp_fu_86_p1; +wire [15:0] trunc_ln220_fu_95_p1; +wire [15:0] grp_fu_77_p2; +wire ap_CS_fsm_state17; +wire [15:0] bitcast_ln648_fu_132_p1; +wire [0:0] tmp_fu_136_p3; +reg [16:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 17'd1; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U371( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(mul_i_i_i_reg_187), + .din1(grp_fu_77_p1), + .dout(grp_fu_77_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U372( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sums_read), + .din1(grp_fu_81_p1), + .dout(grp_fu_81_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U373( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_177), + .din1(grp_fu_86_p1), + .dout(grp_fu_86_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + mul_i_i_i_reg_187 <= grp_fu_86_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sub_i_i_i_reg_177 <= grp_fu_81_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tmp_34_i_i_reg_167 <= {{adjustments_q0[31:16]}}; + tmp_35_i_i_reg_172 <= {{adjustments_q0[47:32]}}; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign adjustments_address0 = zext_ln220_fu_90_p1; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_return = ((tmp_fu_136_p3[0:0] == 1'b1) ? 16'd0 : grp_fu_77_p2); + +assign bitcast_ln648_fu_132_p1 = grp_fu_77_p2; + +assign grp_fu_77_p1 = tmp_35_i_i_reg_172; + +assign grp_fu_81_p1 = trunc_ln220_fu_95_p1; + +assign grp_fu_86_p1 = tmp_34_i_i_reg_167; + +assign tmp_fu_136_p3 = bitcast_ln648_fu_132_p1[32'd15]; + +assign trunc_ln220_fu_95_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_90_p1 = indices_23_dout; + +endmodule //td_fused_top_tdf6_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_q0, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state9 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [6:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +input [15:0] ifmap_vec_0_0_q0; +output [6:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +input [15:0] weight_vecs_0_0_0_q0; +output [6:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_0_0_ce0; +reg weight_vecs_0_0_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [7:0] ic_0_0_reg_69; +wire [7:0] add_ln149_fu_84_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln149_fu_90_p2; +reg [0:0] icmp_ln149_reg_107; +reg [0:0] icmp_ln149_reg_107_pp0_iter1_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter2_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter3_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter4_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter5_reg; +wire [63:0] idxprom17_0_0_fu_96_p1; +reg [63:0] idxprom17_0_0_reg_111; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter1_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter2_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter3_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter4_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter5_reg; +reg [15:0] ifmap_vec_0_0_load_reg_126; +reg [15:0] weight_vecs_0_0_0_load_reg_131; +wire [15:0] grp_fu_80_p2; +reg [15:0] mul_reg_136; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +wire ap_block_pp0_stage0; +wire ap_CS_fsm_state9; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U359( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_0_load_reg_126), + .din1(weight_vecs_0_0_0_load_reg_131), + .dout(grp_fu_80_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_fu_90_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_0_0_reg_69 <= add_ln149_fu_84_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_0_0_reg_69 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln149_reg_107 <= icmp_ln149_fu_90_p2; + icmp_ln149_reg_107_pp0_iter1_reg <= icmp_ln149_reg_107; + idxprom17_0_0_reg_111_pp0_iter1_reg[7 : 0] <= idxprom17_0_0_reg_111[7 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln149_reg_107_pp0_iter2_reg <= icmp_ln149_reg_107_pp0_iter1_reg; + icmp_ln149_reg_107_pp0_iter3_reg <= icmp_ln149_reg_107_pp0_iter2_reg; + icmp_ln149_reg_107_pp0_iter4_reg <= icmp_ln149_reg_107_pp0_iter3_reg; + icmp_ln149_reg_107_pp0_iter5_reg <= icmp_ln149_reg_107_pp0_iter4_reg; + idxprom17_0_0_reg_111_pp0_iter2_reg[7 : 0] <= idxprom17_0_0_reg_111_pp0_iter1_reg[7 : 0]; + idxprom17_0_0_reg_111_pp0_iter3_reg[7 : 0] <= idxprom17_0_0_reg_111_pp0_iter2_reg[7 : 0]; + idxprom17_0_0_reg_111_pp0_iter4_reg[7 : 0] <= idxprom17_0_0_reg_111_pp0_iter3_reg[7 : 0]; + idxprom17_0_0_reg_111_pp0_iter5_reg[7 : 0] <= idxprom17_0_0_reg_111_pp0_iter4_reg[7 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_fu_90_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + idxprom17_0_0_reg_111[7 : 0] <= idxprom17_0_0_fu_96_p1[7 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_reg_107 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_load_reg_126 <= ifmap_vec_0_0_q0; + weight_vecs_0_0_0_load_reg_131 <= weight_vecs_0_0_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_reg_107_pp0_iter4_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_reg_136 <= grp_fu_80_p2; + end +end + +always @ (*) begin + if ((icmp_ln149_fu_90_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter6 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln149_reg_107_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter6 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln149_fu_90_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter6 == 1'b1) & (ap_enable_reg_pp0_iter5 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln149_fu_90_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter6 == 1'b1) & (ap_enable_reg_pp0_iter5 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state9; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln149_fu_84_p2 = (ic_0_0_reg_69 + 8'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign icmp_ln149_fu_90_p2 = ((ic_0_0_reg_69 == 8'd128) ? 1'b1 : 1'b0); + +assign idxprom17_0_0_fu_96_p1 = ic_0_0_reg_69; + +assign ifmap_vec_0_0_address0 = idxprom17_0_0_fu_96_p1; + +assign products_0_address0 = idxprom17_0_0_reg_111_pp0_iter5_reg; + +assign products_0_d0 = mul_reg_136; + +assign weight_vecs_0_0_0_address0 = idxprom17_0_0_fu_96_p1; + +always @ (posedge ap_clk) begin + idxprom17_0_0_reg_111[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter1_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter2_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter3_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter4_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter5_reg[63:8] <= 56'b00000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf6_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf6_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 12; +parameter MEM_SIZE = 4096; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf6_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd4096; +parameter AddressWidth = 32'd12; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf6_filters_ram td_fused_top_tdf6_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + indices_2_out_din, + indices_2_out_full_n, + indices_2_out_write, + indices_2_out1_din, + indices_2_out1_full_n, + indices_2_out1_write +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [4:0] indices_2_out_din; +input indices_2_out_full_n; +output indices_2_out_write; +output [4:0] indices_2_out1_din; +input indices_2_out1_full_n; +output indices_2_out1_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg indices_0_write; +reg indices_1_write; +reg indices_2_out_write; +reg indices_2_out1_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [15:0] i_1; +reg [15:0] j_1; +reg [15:0] k_1; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg indices_2_out_blk_n; +reg indices_2_out1_blk_n; +reg [0:0] ap_phi_mux_j_17_flag_0_i_phi_fu_77_p6; +reg ap_block_state1; +wire [0:0] icmp_ln78_fu_141_p2; +wire [0:0] icmp_ln81_fu_154_p2; +reg [15:0] ap_phi_mux_j_17_new_0_i_phi_fu_91_p6; +wire [15:0] add_ln80_fu_147_p2; +reg [15:0] ap_phi_mux_k_17_new_0_i_phi_fu_104_p6; +wire [15:0] add_ln77_fu_134_p2; +wire [15:0] select_ln84_fu_172_p3; +wire [4:0] trunc_ln76_fu_128_p1; +wire [15:0] add_ln83_fu_160_p2; +wire [0:0] icmp_ln84_fu_166_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_1 = 16'd0; +#0 j_1 = 16'd0; +#0 k_1 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_1 <= select_ln84_fu_172_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_17_flag_0_i_phi_fu_77_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j_1 <= ap_phi_mux_j_17_new_0_i_phi_fu_91_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k_1 <= ap_phi_mux_k_17_new_0_i_phi_fu_104_p6; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_17_flag_0_i_phi_fu_77_p6 = 1'd0; + end else if ((((icmp_ln81_fu_154_p2 == 1'd0) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_17_flag_0_i_phi_fu_77_p6 = 1'd1; + end else begin + ap_phi_mux_j_17_flag_0_i_phi_fu_77_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln81_fu_154_p2 == 1'd0)) begin + ap_phi_mux_j_17_new_0_i_phi_fu_91_p6 = add_ln80_fu_147_p2; + end else if ((icmp_ln81_fu_154_p2 == 1'd1)) begin + ap_phi_mux_j_17_new_0_i_phi_fu_91_p6 = 16'd0; + end else begin + ap_phi_mux_j_17_new_0_i_phi_fu_91_p6 = 'bx; + end + end else begin + ap_phi_mux_j_17_new_0_i_phi_fu_91_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_17_new_0_i_phi_fu_104_p6 = add_ln77_fu_134_p2; + end else if ((((icmp_ln81_fu_154_p2 == 1'd0) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_17_new_0_i_phi_fu_104_p6 = 16'd0; + end else begin + ap_phi_mux_k_17_new_0_i_phi_fu_104_p6 = 'bx; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_blk_n = indices_2_out1_full_n; + end else begin + indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_write = 1'b1; + end else begin + indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_blk_n = indices_2_out_full_n; + end else begin + indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_write = 1'b1; + end else begin + indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln77_fu_134_p2 = (k_1 + 16'd1); + +assign add_ln80_fu_147_p2 = (j_1 + 16'd1); + +assign add_ln83_fu_160_p2 = (i_1 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign icmp_ln78_fu_141_p2 = ((add_ln77_fu_134_p2 == 16'd32) ? 1'b1 : 1'b0); + +assign icmp_ln81_fu_154_p2 = ((add_ln80_fu_147_p2 == 16'd28) ? 1'b1 : 1'b0); + +assign icmp_ln84_fu_166_p2 = ((add_ln83_fu_160_p2 == 16'd28) ? 1'b1 : 1'b0); + +assign indices_0_din = i_1; + +assign indices_1_din = j_1; + +assign indices_2_out1_din = trunc_ln76_fu_128_p1; + +assign indices_2_out_din = trunc_ln76_fu_128_p1; + +assign select_ln84_fu_172_p3 = ((icmp_ln84_fu_166_p2[0:0] == 1'b1) ? 16'd0 : add_ln83_fu_160_p2); + +assign start_out = real_start; + +assign trunc_ln76_fu_128_p1 = k_1[4:0]; + +endmodule //td_fused_top_tdf6_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_readFilters46 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_we0, + weight_vecs_0_0_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state6 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [11:0] filter_data_address0; +output filter_data_ce0; +input [15:0] filter_data_q0; +input [4:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [6:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +output weight_vecs_0_0_0_we0; +output [15:0] weight_vecs_0_0_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg indices_23_read; +reg weight_vecs_0_0_0_ce0; +reg weight_vecs_0_0_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [7:0] kk_0_0_i_i_reg_93; +reg [7:0] kk_0_0_i_i_reg_93_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_pp0_stage0_11001; +reg [7:0] kk_0_0_i_i_reg_93_pp0_iter2_reg; +wire [11:0] tmp_fu_105_p3; +reg [11:0] tmp_reg_144; +wire [7:0] add_ln49_fu_113_p2; +reg [7:0] add_ln49_reg_149; +reg ap_enable_reg_pp0_iter0; +wire [0:0] icmp_ln49_fu_119_p2; +reg [0:0] icmp_ln49_reg_154; +reg [0:0] icmp_ln49_reg_154_pp0_iter1_reg; +reg [0:0] icmp_ln49_reg_154_pp0_iter2_reg; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg [7:0] ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln55_20_fu_134_p1; +wire [63:0] idxprom16_0_0_i_i_fu_139_p1; +wire [11:0] zext_ln55_fu_125_p1; +wire [11:0] add_ln55_fu_129_p2; +wire ap_CS_fsm_state6; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_0_i_i_reg_93 <= add_ln49_reg_149; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_0_0_i_i_reg_93 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln49_reg_149 <= add_ln49_fu_113_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln49_reg_154 <= icmp_ln49_fu_119_p2; + icmp_ln49_reg_154_pp0_iter1_reg <= icmp_ln49_reg_154; + kk_0_0_i_i_reg_93_pp0_iter1_reg <= kk_0_0_i_i_reg_93; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln49_reg_154_pp0_iter2_reg <= icmp_ln49_reg_154_pp0_iter1_reg; + kk_0_0_i_i_reg_93_pp0_iter2_reg <= kk_0_0_i_i_reg_93_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + tmp_reg_144[11 : 7] <= tmp_fu_105_p3[11 : 7]; + end +end + +always @ (*) begin + if ((icmp_ln49_fu_119_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 = add_ln49_reg_149; + end else begin + ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 = kk_0_0_i_i_reg_93; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln49_reg_154_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1))) begin + weight_vecs_0_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln49_fu_119_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln49_fu_119_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln49_fu_113_p2 = (ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 + 8'd1); + +assign add_ln55_fu_129_p2 = (tmp_reg_144 + zext_ln55_fu_125_p1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_address0 = zext_ln55_20_fu_134_p1; + +assign icmp_ln49_fu_119_p2 = ((ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 == 8'd128) ? 1'b1 : 1'b0); + +assign idxprom16_0_0_i_i_fu_139_p1 = kk_0_0_i_i_reg_93_pp0_iter2_reg; + +assign tmp_fu_105_p3 = {{indices_23_dout}, {7'd0}}; + +assign weight_vecs_0_0_0_address0 = idxprom16_0_0_i_i_fu_139_p1; + +assign weight_vecs_0_0_0_d0 = filter_data_q0; + +assign zext_ln55_20_fu_134_p1 = add_ln55_fu_129_p2; + +assign zext_ln55_fu_125_p1 = ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4; + +always @ (posedge ap_clk) begin + tmp_reg_144[6:0] <= 7'b0000000; +end + +endmodule //td_fused_top_tdf6_readFilters46 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_readInputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_we0, + ifmap_vec_0_0_d0, + ifmap_vec_0_0_address1, + ifmap_vec_0_0_ce1, + ifmap_vec_0_0_we1, + ifmap_vec_0_0_d1, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 5'd1; +parameter ap_ST_fsm_state2 = 5'd2; +parameter ap_ST_fsm_pp0_stage0 = 5'd4; +parameter ap_ST_fsm_pp0_stage1 = 5'd8; +parameter ap_ST_fsm_state8 = 5'd16; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [14:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [6:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +output ifmap_vec_0_0_we0; +output [15:0] ifmap_vec_0_0_d0; +output [6:0] ifmap_vec_0_0_address1; +output ifmap_vec_0_0_ce1; +output ifmap_vec_0_0_we1; +output [15:0] ifmap_vec_0_0_d1; +output [4:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [9:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg[6:0] ifmap_vec_0_0_address0; +reg ifmap_vec_0_0_ce0; +reg ifmap_vec_0_0_we0; +reg[15:0] ifmap_vec_0_0_d0; +reg[6:0] ifmap_vec_0_0_address1; +reg ifmap_vec_0_0_ce1; +reg ifmap_vec_0_0_we1; +reg[15:0] ifmap_vec_0_0_d1; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [4:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [7:0] kk_0_i_i_reg_180; +reg [7:0] kk_0_i_i_reg_180_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state5_pp0_stage0_iter1; +wire ap_block_state7_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [4:0] trunc_ln135_fu_192_p1; +reg [4:0] trunc_ln135_reg_434; +reg [15:0] col_coord_reg_439; +wire [0:0] is_padding_fu_214_p2; +reg [0:0] is_padding_reg_444; +wire [11:0] add_ln32_fu_274_p2; +reg [11:0] add_ln32_reg_454; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln25_fu_280_p2; +reg [0:0] icmp_ln25_reg_459; +reg [0:0] icmp_ln25_reg_459_pp0_iter1_reg; +wire [7:0] add_ln25_fu_308_p2; +reg [7:0] add_ln25_reg_468; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state4_pp0_stage1_iter0; +wire ap_block_state6_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +wire [6:0] empty_80_fu_314_p1; +reg [6:0] empty_80_reg_473; +wire [15:0] select_ln33_11_fu_386_p3; +reg [15:0] select_ln33_11_reg_479; +wire [15:0] select_ln33_12_fu_407_p3; +reg [15:0] select_ln33_12_reg_484; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state3; +reg ap_enable_reg_pp0_iter1; +wire ap_block_pp0_stage1_subdone; +reg ap_enable_reg_pp0_iter2; +reg [7:0] ap_phi_mux_kk_0_i_i_phi_fu_184_p4; +wire ap_block_pp0_stage0; +wire [63:0] sext_ln32_fu_303_p1; +wire [63:0] zext_ln32_fu_318_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln32_10_fu_345_p1; +wire [63:0] zext_ln32_11_fu_419_p1; +wire [63:0] zext_ln32_12_fu_429_p1; +reg ap_block_state1; +wire [15:0] select_ln33_fu_331_p3; +wire [15:0] select_ln33_10_fu_364_p3; +wire [0:0] cmp7_i_i_fu_202_p2; +wire [0:0] icmp_ln24_fu_208_p2; +wire [4:0] empty_78_fu_220_p1; +wire [4:0] row_coord_int_fu_223_p3; +wire [9:0] tmp_fu_236_p3; +wire [6:0] tmp_s_fu_248_p3; +wire [10:0] zext_ln32_13_fu_244_p1; +wire [10:0] zext_ln32_14_fu_256_p1; +wire [10:0] sub_ln32_fu_260_p2; +wire [4:0] col_coord_int_fu_229_p3; +wire [11:0] sub_ln32_cast_fu_266_p1; +wire [11:0] zext_ln32_15_fu_270_p1; +wire [4:0] lshr_ln_fu_286_p4; +wire [16:0] tmp_18_fu_296_p3; +wire [15:0] trunc_ln32_fu_323_p1; +wire [15:0] bitcast_ln32_fu_327_p1; +wire [6:0] or_ln25_fu_339_p2; +wire [15:0] tmp_31_i_i_fu_350_p4; +wire [15:0] bitcast_ln32_10_fu_360_p1; +wire [15:0] tmp_32_i_i_fu_372_p4; +wire [15:0] bitcast_ln32_11_fu_382_p1; +wire [15:0] tmp_33_i_i_fu_393_p4; +wire [15:0] bitcast_ln32_12_fu_403_p1; +wire [6:0] or_ln25_7_fu_414_p2; +wire [6:0] or_ln25_8_fu_424_p2; +wire ap_CS_fsm_state8; +reg [4:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 5'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln25_reg_459 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_i_i_reg_180 <= add_ln25_reg_468; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + kk_0_i_i_reg_180 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln25_reg_459 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln25_reg_468 <= add_ln25_fu_308_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln32_reg_454 <= add_ln32_fu_274_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + col_coord_reg_439 <= indices_12_dout; + is_padding_reg_444 <= is_padding_fu_214_p2; + trunc_ln135_reg_434 <= trunc_ln135_fu_192_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln25_reg_459_pp0_iter1_reg == 1'd0))) begin + empty_80_reg_473 <= empty_80_fu_314_p1; + select_ln33_11_reg_479 <= select_ln33_11_fu_386_p3; + select_ln33_12_reg_484 <= select_ln33_12_fu_407_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln25_reg_459 <= icmp_ln25_fu_280_p2; + icmp_ln25_reg_459_pp0_iter1_reg <= icmp_ln25_reg_459; + kk_0_i_i_reg_180_pp0_iter1_reg <= kk_0_i_i_reg_180; + end +end + +always @ (*) begin + if ((icmp_ln25_fu_280_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln25_reg_459 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_i_i_phi_fu_184_p4 = add_ln25_reg_468; + end else begin + ap_phi_mux_kk_0_i_i_phi_fu_184_p4 = kk_0_i_i_reg_180; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_address0 = zext_ln32_12_fu_429_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_address0 = zext_ln32_10_fu_345_p1; + end else begin + ifmap_vec_0_0_address0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_address1 = zext_ln32_11_fu_419_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_address1 = zext_ln32_fu_318_p1; + end else begin + ifmap_vec_0_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_ce1 = 1'b1; + end else begin + ifmap_vec_0_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_d0 = select_ln33_12_reg_484; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_d0 = select_ln33_10_fu_364_p3; + end else begin + ifmap_vec_0_0_d0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_d1 = select_ln33_11_reg_479; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_d1 = select_ln33_fu_331_p3; + end else begin + ifmap_vec_0_0_d1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln25_reg_459_pp0_iter1_reg == 1'd0)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln25_reg_459_pp0_iter1_reg == 1'd0)))) begin + ifmap_vec_0_0_we0 = 1'b1; + end else begin + ifmap_vec_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln25_reg_459_pp0_iter1_reg == 1'd0)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln25_reg_459_pp0_iter1_reg == 1'd0)))) begin + ifmap_vec_0_0_we1 = 1'b1; + end else begin + ifmap_vec_0_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln25_fu_280_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if ((((icmp_ln25_fu_280_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state8; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln25_fu_308_p2 = (kk_0_i_i_reg_180 + 8'd4); + +assign add_ln32_fu_274_p2 = ((sub_ln32_cast_fu_266_p1) + (zext_ln32_15_fu_270_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd4]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln32_10_fu_360_p1 = tmp_31_i_i_fu_350_p4; + +assign bitcast_ln32_11_fu_382_p1 = tmp_32_i_i_fu_372_p4; + +assign bitcast_ln32_12_fu_403_p1 = tmp_33_i_i_fu_393_p4; + +assign bitcast_ln32_fu_327_p1 = trunc_ln32_fu_323_p1; + +assign cmp7_i_i_fu_202_p2 = ((indices_01_dout > 16'd27) ? 1'b1 : 1'b0); + +assign col_coord_int_fu_229_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 5'd0 : empty_78_fu_220_p1); + +assign empty_78_fu_220_p1 = col_coord_reg_439[4:0]; + +assign empty_80_fu_314_p1 = kk_0_i_i_reg_180_pp0_iter1_reg[6:0]; + +assign icmp_ln24_fu_208_p2 = ((indices_12_dout > 16'd27) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_280_p2 = ((ap_phi_mux_kk_0_i_i_phi_fu_184_p4 == 8'd128) ? 1'b1 : 1'b0); + +assign in_data_address0 = sext_ln32_fu_303_p1; + +assign indices_01_out_din = indices_01_dout[4:0]; + +assign indices_12_out_din = indices_12_dout[9:0]; + +assign is_padding_fu_214_p2 = (icmp_ln24_fu_208_p2 | cmp7_i_i_fu_202_p2); + +assign lshr_ln_fu_286_p4 = {{ap_phi_mux_kk_0_i_i_phi_fu_184_p4[6:2]}}; + +assign or_ln25_7_fu_414_p2 = (empty_80_reg_473 | 7'd2); + +assign or_ln25_8_fu_424_p2 = (empty_80_reg_473 | 7'd3); + +assign or_ln25_fu_339_p2 = (empty_80_fu_314_p1 | 7'd1); + +assign row_coord_int_fu_223_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 5'd0 : trunc_ln135_reg_434); + +assign select_ln33_10_fu_364_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_10_fu_360_p1); + +assign select_ln33_11_fu_386_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_11_fu_382_p1); + +assign select_ln33_12_fu_407_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_12_fu_403_p1); + +assign select_ln33_fu_331_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_fu_327_p1); + +assign sext_ln32_fu_303_p1 = (tmp_18_fu_296_p3); + +assign sub_ln32_cast_fu_266_p1 = (sub_ln32_fu_260_p2); + +assign sub_ln32_fu_260_p2 = (zext_ln32_13_fu_244_p1 - zext_ln32_14_fu_256_p1); + +assign tmp_18_fu_296_p3 = {{add_ln32_reg_454}, {lshr_ln_fu_286_p4}}; + +assign tmp_31_i_i_fu_350_p4 = {{in_data_q0[31:16]}}; + +assign tmp_32_i_i_fu_372_p4 = {{in_data_q0[47:32]}}; + +assign tmp_33_i_i_fu_393_p4 = {{in_data_q0[63:48]}}; + +assign tmp_fu_236_p3 = {{row_coord_int_fu_223_p3}, {5'd0}}; + +assign tmp_s_fu_248_p3 = {{row_coord_int_fu_223_p3}, {2'd0}}; + +assign trunc_ln135_fu_192_p1 = indices_01_dout[4:0]; + +assign trunc_ln32_fu_323_p1 = in_data_q0[15:0]; + +assign zext_ln32_10_fu_345_p1 = or_ln25_fu_339_p2; + +assign zext_ln32_11_fu_419_p1 = or_ln25_7_fu_414_p2; + +assign zext_ln32_12_fu_429_p1 = or_ln25_8_fu_424_p2; + +assign zext_ln32_13_fu_244_p1 = tmp_fu_236_p3; + +assign zext_ln32_14_fu_256_p1 = tmp_s_fu_248_p3; + +assign zext_ln32_15_fu_270_p1 = col_coord_int_fu_229_p3; + +assign zext_ln32_fu_318_p1 = kk_0_i_i_reg_180_pp0_iter1_reg; + +endmodule //td_fused_top_tdf6_readInputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf6_writeOutputs_unaligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + p_read, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_state2 = 3'd2; +parameter ap_ST_fsm_state3 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [4:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [9:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [15:0] p_read; +output [12:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg out_data_ce1; +reg out_data_we1; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] outputCount_4; +reg [15:0] outputChanIdx_4; +reg [15:0] outputRow_12_0; +reg [15:0] outputRow_12_1; +reg [15:0] outputRow_12_2; +reg [15:0] outputRow_12_3; +reg indices_01_blk_n; +reg indices_12_blk_n; +wire [9:0] add_ln94_fu_147_p2; +reg [9:0] add_ln94_reg_304; +wire [15:0] add_ln87_fu_192_p2; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln88_fu_198_p2; +reg [0:0] icmp_ln88_reg_317; +reg [15:0] ap_phi_mux_empty_phi_fu_114_p4; +reg [15:0] empty_reg_111; +wire ap_CS_fsm_state3; +wire [63:0] zext_ln94_6_fu_226_p1; +wire [15:0] select_ln97_fu_284_p3; +wire [1:0] trunc_ln86_fu_164_p1; +reg [15:0] ap_sig_allocacmp_outputRow_12_0_load; +reg [15:0] ap_sig_allocacmp_outputRow_12_1_load; +reg [15:0] ap_sig_allocacmp_outputRow_12_2_load; +reg [15:0] ap_sig_allocacmp_outputRow_12_3_load; +reg ap_block_state1; +wire [6:0] tmp_s_fu_129_p3; +wire [9:0] tmp_fu_121_p3; +wire [9:0] zext_ln94_fu_137_p1; +wire [9:0] sub_ln94_fu_141_p2; +wire [4:0] trunc_ln94_fu_212_p1; +wire [12:0] tmp_53_cast_fu_153_p3; +wire [12:0] zext_ln94_5_fu_216_p1; +wire [12:0] add_ln94_3_fu_220_p2; +wire [15:0] bitcast_ln94_9_fu_255_p1; +wire [15:0] bitcast_ln94_8_fu_247_p1; +wire [15:0] bitcast_ln94_7_fu_239_p1; +wire [15:0] bitcast_ln94_fu_231_p1; +wire [15:0] add_ln96_fu_272_p2; +wire [0:0] icmp_ln97_fu_278_p2; +reg [2:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 outputCount_4 = 16'd0; +#0 outputChanIdx_4 = 16'd0; +#0 outputRow_12_0 = 16'd0; +#0 outputRow_12_1 = 16'd0; +#0 outputRow_12_2 = 16'd0; +#0 outputRow_12_3 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state3)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_reg_317 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + empty_reg_111 <= 16'd0; + end else if (((icmp_ln88_fu_198_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + empty_reg_111 <= add_ln87_fu_192_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + add_ln94_reg_304 <= add_ln94_fu_147_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + icmp_ln88_reg_317 <= icmp_ln88_fu_198_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_fu_198_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + outputChanIdx_4 <= select_ln97_fu_284_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + outputCount_4 <= ap_phi_mux_empty_phi_fu_114_p4; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_164_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_12_0 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_164_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_12_1 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_164_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_12_2 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_164_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_12_3 <= p_read; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_reg_317 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + ap_phi_mux_empty_phi_fu_114_p4 = 16'd0; + end else begin + ap_phi_mux_empty_phi_fu_114_p4 = empty_reg_111; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_164_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_12_0_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_12_0_load = outputRow_12_0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_164_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_12_1_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_12_1_load = outputRow_12_1; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_164_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_12_2_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_12_2_load = outputRow_12_2; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_164_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_12_3_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_12_3_load = outputRow_12_3; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2))) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_fu_198_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln87_fu_192_p2 = (outputCount_4 + 16'd1); + +assign add_ln94_3_fu_220_p2 = (tmp_53_cast_fu_153_p3 + zext_ln94_5_fu_216_p1); + +assign add_ln94_fu_147_p2 = (sub_ln94_fu_141_p2 + indices_12_dout); + +assign add_ln96_fu_272_p2 = (outputChanIdx_4 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign bitcast_ln94_7_fu_239_p1 = ap_sig_allocacmp_outputRow_12_1_load; + +assign bitcast_ln94_8_fu_247_p1 = ap_sig_allocacmp_outputRow_12_2_load; + +assign bitcast_ln94_9_fu_255_p1 = ap_sig_allocacmp_outputRow_12_3_load; + +assign bitcast_ln94_fu_231_p1 = ap_sig_allocacmp_outputRow_12_0_load; + +assign icmp_ln88_fu_198_p2 = ((add_ln87_fu_192_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign icmp_ln97_fu_278_p2 = ((add_ln96_fu_272_p2 == 16'd8) ? 1'b1 : 1'b0); + +assign out_data_address1 = zext_ln94_6_fu_226_p1; + +assign out_data_d1 = {{{{bitcast_ln94_9_fu_255_p1}, {bitcast_ln94_8_fu_247_p1}}, {bitcast_ln94_7_fu_239_p1}}, {bitcast_ln94_fu_231_p1}}; + +assign select_ln97_fu_284_p3 = ((icmp_ln97_fu_278_p2[0:0] == 1'b1) ? 16'd0 : add_ln96_fu_272_p2); + +assign sub_ln94_fu_141_p2 = (tmp_fu_121_p3 - zext_ln94_fu_137_p1); + +assign tmp_53_cast_fu_153_p3 = {{add_ln94_reg_304}, {3'd0}}; + +assign tmp_fu_121_p3 = {{indices_01_dout}, {5'd0}}; + +assign tmp_s_fu_129_p3 = {{indices_01_dout}, {2'd0}}; + +assign trunc_ln86_fu_164_p1 = outputCount_4[1:0]; + +assign trunc_ln94_fu_212_p1 = outputChanIdx_4[4:0]; + +assign zext_ln94_5_fu_216_p1 = trunc_ln94_fu_212_p1; + +assign zext_ln94_6_fu_226_p1 = add_ln94_3_fu_220_p2; + +assign zext_ln94_fu_137_p1 = tmp_s_fu_129_p3; + +endmodule //td_fused_top_tdf6_writeOutputs_unaligned +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_18 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + l1_filter_data_address0, + l1_filter_data_ce0, + l1_filter_data_d0, + l1_filter_data_q0, + l1_filter_data_we0, + l1_filter_data_address1, + l1_filter_data_ce1, + l1_filter_data_d1, + l1_filter_data_q1, + l1_filter_data_we1, + l2_filter_data_address0, + l2_filter_data_ce0, + l2_filter_data_d0, + l2_filter_data_q0, + l2_filter_data_we0, + l2_filter_data_address1, + l2_filter_data_ce1, + l2_filter_data_d1, + l2_filter_data_q1, + l2_filter_data_we1, + l1_adjustments_address0, + l1_adjustments_ce0, + l1_adjustments_d0, + l1_adjustments_q0, + l1_adjustments_we0, + l1_adjustments_address1, + l1_adjustments_ce1, + l1_adjustments_d1, + l1_adjustments_q1, + l1_adjustments_we1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_d0, + l2_adjustments_q0, + l2_adjustments_we0, + l2_adjustments_address1, + l2_adjustments_ce1, + l2_adjustments_d1, + l2_adjustments_q1, + l2_adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [12:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [12:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [12:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [12:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [16:0] l1_filter_data_address0; +output l1_filter_data_ce0; +output [15:0] l1_filter_data_d0; +input [15:0] l1_filter_data_q0; +output l1_filter_data_we0; +output [16:0] l1_filter_data_address1; +output l1_filter_data_ce1; +output [15:0] l1_filter_data_d1; +input [15:0] l1_filter_data_q1; +output l1_filter_data_we1; +output [12:0] l2_filter_data_address0; +output l2_filter_data_ce0; +output [15:0] l2_filter_data_d0; +input [15:0] l2_filter_data_q0; +output l2_filter_data_we0; +output [12:0] l2_filter_data_address1; +output l2_filter_data_ce1; +output [15:0] l2_filter_data_d1; +input [15:0] l2_filter_data_q1; +output l2_filter_data_we1; +output [7:0] l1_adjustments_address0; +output l1_adjustments_ce0; +output [47:0] l1_adjustments_d0; +input [47:0] l1_adjustments_q0; +output l1_adjustments_we0; +output [7:0] l1_adjustments_address1; +output l1_adjustments_ce1; +output [47:0] l1_adjustments_d1; +input [47:0] l1_adjustments_q1; +output l1_adjustments_we1; +output [4:0] l2_adjustments_address0; +output l2_adjustments_ce0; +output [47:0] l2_adjustments_d0; +input [47:0] l2_adjustments_q0; +output l2_adjustments_we0; +output [4:0] l2_adjustments_address1; +output l2_adjustments_ce1; +output [47:0] l2_adjustments_d1; +input [47:0] l2_adjustments_q1; +output l2_adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [12:0] dataflow_in_loop_TOP_LOOP37548_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP37548_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP37548_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP37548_U0_in_data_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP37548_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP37548_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP37548_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP37548_U0_in_data_we1; +wire [16:0] dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_we0; +wire [16:0] dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_we1; +wire [7:0] dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_we0; +wire [7:0] dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_we1; +wire [12:0] dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_we1; +wire [12:0] dataflow_in_loop_TOP_LOOP37548_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP37548_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP37548_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP37548_U0_out_data_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP37548_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP37548_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP37548_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP37548_U0_out_data_we1; +wire [4:0] dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_we0; +wire [4:0] dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_we1; +wire dataflow_in_loop_TOP_LOOP37548_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP37548_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP37548_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP37548_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP37548_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP37548_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP37548_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP37548_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP37548_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [17:0] loop_dataflow_input_count; +reg [17:0] loop_dataflow_output_count; +wire [17:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP37548_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP37548_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 18'd0; +#0 loop_dataflow_output_count = 18'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP37548 dataflow_in_loop_TOP_LOOP37548_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP37548_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP37548_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP37548_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP37548_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP37548_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP37548_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP37548_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP37548_U0_in_data_we1), + .l1_filter_data_address0(dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_address0), + .l1_filter_data_ce0(dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_ce0), + .l1_filter_data_d0(dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_d0), + .l1_filter_data_q0(l1_filter_data_q0), + .l1_filter_data_we0(dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_we0), + .l1_filter_data_address1(dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_address1), + .l1_filter_data_ce1(dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_ce1), + .l1_filter_data_d1(dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_d1), + .l1_filter_data_q1(16'd0), + .l1_filter_data_we1(dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_we1), + .l1_adjustments_address0(dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_address0), + .l1_adjustments_ce0(dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_ce0), + .l1_adjustments_d0(dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_d0), + .l1_adjustments_q0(l1_adjustments_q0), + .l1_adjustments_we0(dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_we0), + .l1_adjustments_address1(dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_address1), + .l1_adjustments_ce1(dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_ce1), + .l1_adjustments_d1(dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_d1), + .l1_adjustments_q1(48'd0), + .l1_adjustments_we1(dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_we1), + .l2_filter_data_address0(dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_address0), + .l2_filter_data_ce0(dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_ce0), + .l2_filter_data_d0(dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_d0), + .l2_filter_data_q0(l2_filter_data_q0), + .l2_filter_data_we0(dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_we0), + .l2_filter_data_address1(dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_address1), + .l2_filter_data_ce1(dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_ce1), + .l2_filter_data_d1(dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_d1), + .l2_filter_data_q1(16'd0), + .l2_filter_data_we1(dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP37548_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP37548_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP37548_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP37548_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP37548_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP37548_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP37548_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP37548_U0_out_data_we1), + .l2_adjustments_address0(dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_address0), + .l2_adjustments_ce0(dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_ce0), + .l2_adjustments_d0(dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_d0), + .l2_adjustments_q0(l2_adjustments_q0), + .l2_adjustments_we0(dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_we0), + .l2_adjustments_address1(dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_address1), + .l2_adjustments_ce1(dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_ce1), + .l2_adjustments_d1(dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_d1), + .l2_adjustments_q1(48'd0), + .l2_adjustments_we1(dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_we1), + .ap_start(dataflow_in_loop_TOP_LOOP37548_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP37548_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP37548_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP37548_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP37548_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP37548_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP37548_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 18'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP37548_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 18'd1); + end else if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP37548_U0_ap_ready == 1'b1))) begin + loop_dataflow_input_count <= 18'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 18'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37548_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP37548_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 18'd1); + end else if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37548_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP37548_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= 18'd0; + end + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37548_U0_ap_done == 1'b1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_output_count == 18'd0) & (ap_start == 1'b0) & (dataflow_in_loop_TOP_LOOP37548_U0_ap_idle == 1'b1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1) & (dataflow_in_loop_TOP_LOOP37548_U0_ap_ready == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP37548_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP37548_U0_ap_continue = 1'b0; + end +end + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP37548_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP37548_U0_ap_ready; + +assign bound_minus_1 = (18'd200704 - 18'd1); + +assign dataflow_in_loop_TOP_LOOP37548_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP37548_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP37548_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP37548_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP37548_U0_start_write = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP37548_U0_in_data_address0; + +assign in_data_address1 = 13'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP37548_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP37548_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign l1_adjustments_address0 = dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_address0; + +assign l1_adjustments_address1 = 8'd0; + +assign l1_adjustments_ce0 = dataflow_in_loop_TOP_LOOP37548_U0_l1_adjustments_ce0; + +assign l1_adjustments_ce1 = 1'b0; + +assign l1_adjustments_d0 = 48'd0; + +assign l1_adjustments_d1 = 48'd0; + +assign l1_adjustments_we0 = 1'b0; + +assign l1_adjustments_we1 = 1'b0; + +assign l1_filter_data_address0 = dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_address0; + +assign l1_filter_data_address1 = 17'd0; + +assign l1_filter_data_ce0 = dataflow_in_loop_TOP_LOOP37548_U0_l1_filter_data_ce0; + +assign l1_filter_data_ce1 = 1'b0; + +assign l1_filter_data_d0 = 16'd0; + +assign l1_filter_data_d1 = 16'd0; + +assign l1_filter_data_we0 = 1'b0; + +assign l1_filter_data_we1 = 1'b0; + +assign l2_adjustments_address0 = dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_address0; + +assign l2_adjustments_address1 = 5'd0; + +assign l2_adjustments_ce0 = dataflow_in_loop_TOP_LOOP37548_U0_l2_adjustments_ce0; + +assign l2_adjustments_ce1 = 1'b0; + +assign l2_adjustments_d0 = 48'd0; + +assign l2_adjustments_d1 = 48'd0; + +assign l2_adjustments_we0 = 1'b0; + +assign l2_adjustments_we1 = 1'b0; + +assign l2_filter_data_address0 = dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_address0; + +assign l2_filter_data_address1 = 13'd0; + +assign l2_filter_data_ce0 = dataflow_in_loop_TOP_LOOP37548_U0_l2_filter_data_ce0; + +assign l2_filter_data_ce1 = 1'b0; + +assign l2_filter_data_d0 = 16'd0; + +assign l2_filter_data_d1 = 16'd0; + +assign l2_filter_data_we0 = 1'b0; + +assign l2_filter_data_we1 = 1'b0; + +assign out_data_address0 = 13'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP37548_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP37548_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP37548_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP37548_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP37548_U0_out_data_write; + +endmodule //td_fused_top_tdf7_18 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 8'd1; +parameter ap_ST_fsm_pp0_stage0 = 8'd2; +parameter ap_ST_fsm_pp0_stage1 = 8'd4; +parameter ap_ST_fsm_pp0_stage2 = 8'd8; +parameter ap_ST_fsm_pp0_stage3 = 8'd16; +parameter ap_ST_fsm_state12 = 8'd32; +parameter ap_ST_fsm_state13 = 8'd64; +parameter ap_ST_fsm_state14 = 8'd128; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [8:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [8:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[8:0] accum_in_0_address0; +reg accum_in_0_ce0; +reg[8:0] accum_in_0_address1; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [7:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [8:0] x_reg_168; +reg [15:0] psum_7_08_reg_180; +reg [15:0] psum_6_07_reg_192; +reg [15:0] psum_5_06_reg_204; +reg [15:0] psum_4_05_reg_216; +reg [15:0] psum_3_04_reg_228; +reg [15:0] psum_2_03_reg_240; +reg [15:0] psum_1_02_reg_252; +reg [15:0] psum_0_01_reg_264; +wire [0:0] icmp_ln132_fu_321_p2; +reg [0:0] icmp_ln132_reg_492; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state6_pp0_stage0_iter1; +wire ap_block_state10_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln132_reg_492_pp0_iter1_reg; +reg [0:0] icmp_ln132_reg_492_pp0_iter2_reg; +reg [15:0] accum_in_0_load_reg_506; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state7_pp0_stage1_iter1; +wire ap_block_state11_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_0_load_15_reg_511; +reg [15:0] accum_in_0_load_16_reg_526; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state8_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_0_load_17_reg_531; +wire [8:0] add_ln132_fu_387_p2; +reg [8:0] add_ln132_reg_546; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state9_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_0_load_18_reg_551; +reg [15:0] accum_in_0_load_19_reg_556; +reg [15:0] accum_in_0_load_20_reg_571; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_0_load_21_reg_576; +wire [15:0] grp_fu_305_p2; +wire [15:0] grp_fu_310_p2; +reg ap_enable_reg_pp0_iter2; +wire [3:0] add_ln140_fu_432_p2; +wire ap_CS_fsm_state13; +wire [0:0] tmp_fu_415_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage1_subdone; +reg [8:0] ap_phi_mux_x_phi_fu_172_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_184_p4; +wire ap_block_pp0_stage1; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_196_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_208_p4; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_220_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_232_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_03_phi_fu_244_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_276; +wire ap_CS_fsm_state12; +reg [15:0] ap_phi_mux_phi_ln152_phi_fu_290_p8; +wire [2:0] trunc_ln140_fu_428_p1; +wire [63:0] zext_ln132_fu_327_p1; +wire [63:0] zext_ln136_fu_338_p1; +wire [63:0] zext_ln136_1_fu_349_p1; +wire [63:0] zext_ln136_2_fu_360_p1; +wire [63:0] zext_ln136_3_fu_371_p1; +wire [63:0] zext_ln136_4_fu_382_p1; +wire [63:0] zext_ln136_5_fu_399_p1; +wire [63:0] zext_ln136_6_fu_410_p1; +wire [63:0] zext_ln140_fu_423_p1; +wire [63:0] zext_ln140_1_fu_444_p1; +reg [15:0] grp_fu_305_p0; +reg [15:0] grp_fu_305_p1; +reg [15:0] grp_fu_310_p0; +reg [15:0] grp_fu_310_p1; +wire [8:0] or_ln136_fu_332_p2; +wire [8:0] or_ln136_1_fu_343_p2; +wire [8:0] or_ln136_2_fu_354_p2; +wire [8:0] or_ln136_3_fu_365_p2; +wire [8:0] or_ln136_4_fu_376_p2; +wire [8:0] or_ln136_5_fu_393_p2; +wire [8:0] or_ln136_6_fu_404_p2; +wire [2:0] or_ln140_fu_438_p2; +wire [0:0] icmp_ln152_fu_449_p2; +wire [0:0] icmp_ln152_1_fu_463_p2; +wire [15:0] select_ln152_fu_455_p3; +wire [0:0] icmp_ln152_2_fu_477_p2; +wire [15:0] select_ln152_1_fu_469_p3; +wire ap_CS_fsm_state14; +reg [7:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_514; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 8'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U421( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_305_p0), + .din1(grp_fu_305_p1), + .dout(grp_fu_305_p2) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U422( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_310_p0), + .din1(grp_fu_310_p1), + .dout(grp_fu_310_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + q_reg_276 <= 4'd0; + end else if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + q_reg_276 <= add_ln140_fu_432_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + x_reg_168 <= add_ln132_reg_546; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_168 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_load_15_reg_511 <= accum_in_0_q0; + accum_in_0_load_reg_506 <= accum_in_0_q1; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_load_16_reg_526 <= accum_in_0_q1; + accum_in_0_load_17_reg_531 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_load_18_reg_551 <= accum_in_0_q1; + accum_in_0_load_19_reg_556 <= accum_in_0_q0; + add_ln132_reg_546 <= add_ln132_fu_387_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_0_load_20_reg_571 <= accum_in_0_q1; + accum_in_0_load_21_reg_576 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln132_reg_492 <= icmp_ln132_fu_321_p2; + icmp_ln132_reg_492_pp0_iter1_reg <= icmp_ln132_reg_492; + icmp_ln132_reg_492_pp0_iter2_reg <= icmp_ln132_reg_492_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_0_01_reg_264 <= grp_fu_305_p2; + psum_1_02_reg_252 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_2_03_reg_240 <= grp_fu_305_p2; + psum_3_04_reg_228 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + psum_4_05_reg_216 <= grp_fu_305_p2; + psum_5_06_reg_204 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln132_reg_492_pp0_iter2_reg == 1'd1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + psum_6_07_reg_192 <= grp_fu_305_p2; + psum_7_08_reg_180 <= grp_fu_310_p2; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address0 = zext_ln136_6_fu_410_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address0 = zext_ln136_4_fu_382_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address0 = zext_ln136_2_fu_360_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address0 = zext_ln136_fu_338_p1; + end else begin + accum_in_0_address0 = 'bx; + end + end else begin + accum_in_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address1 = zext_ln136_5_fu_399_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address1 = zext_ln136_3_fu_371_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address1 = zext_ln136_1_fu_349_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address1 = zext_ln132_fu_327_p1; + end else begin + accum_in_0_address1 = 'bx; + end + end else begin + accum_in_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln132_reg_492 == 1'd0)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + if ((trunc_ln140_fu_428_p1 == 3'd0)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_0_01_reg_264; + end else if ((1'b1 == ap_condition_514)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_6_07_reg_192; + end else if ((trunc_ln140_fu_428_p1 == 3'd4)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_4_05_reg_216; + end else if ((trunc_ln140_fu_428_p1 == 3'd2)) begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = psum_2_03_reg_240; + end else begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln152_phi_fu_290_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (icmp_ln132_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_x_phi_fu_172_p4 = add_ln132_reg_546; + end else begin + ap_phi_mux_x_phi_fu_172_p4 = x_reg_168; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_6_07_phi_fu_196_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_4_05_phi_fu_220_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p0 = ap_phi_mux_psum_2_03_phi_fu_244_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p0 = grp_fu_305_p2; + end else begin + grp_fu_305_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p1 = accum_in_0_load_20_reg_571; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p1 = accum_in_0_load_18_reg_551; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p1 = accum_in_0_load_16_reg_526; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p1 = accum_in_0_load_reg_506; + end else begin + grp_fu_305_p1 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p0 = ap_phi_mux_psum_7_08_phi_fu_184_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p0 = ap_phi_mux_psum_5_06_phi_fu_208_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p0 = ap_phi_mux_psum_3_04_phi_fu_232_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p0 = grp_fu_310_p2; + end else begin + grp_fu_310_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p1 = accum_in_0_load_21_reg_576; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p1 = accum_in_0_load_19_reg_556; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p1 = accum_in_0_load_17_reg_531; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p1 = accum_in_0_load_15_reg_511; + end else begin + grp_fu_310_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (icmp_ln132_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (icmp_ln132_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_state14; + end + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln140_1_fu_444_p1; + +assign accum_out_address1 = zext_ln140_fu_423_p1; + +assign accum_out_d0 = ((icmp_ln152_2_fu_477_p2[0:0] == 1'b1) ? psum_5_06_reg_204 : select_ln152_1_fu_469_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln152_phi_fu_290_p8; + +assign add_ln132_fu_387_p2 = (x_reg_168 + 9'd8); + +assign add_ln140_fu_432_p2 = (q_reg_276 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_state14 = ap_CS_fsm[32'd7]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_514 = (~(trunc_ln140_fu_428_p1 == 3'd0) & ~(trunc_ln140_fu_428_p1 == 3'd4) & ~(trunc_ln140_fu_428_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_03_phi_fu_244_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_232_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_220_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_208_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_196_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_184_p4 = grp_fu_310_p2; + +assign icmp_ln132_fu_321_p2 = ((ap_phi_mux_x_phi_fu_172_p4 < 9'd288) ? 1'b1 : 1'b0); + +assign icmp_ln152_1_fu_463_p2 = ((or_ln140_fu_438_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln152_2_fu_477_p2 = ((or_ln140_fu_438_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln152_fu_449_p2 = ((or_ln140_fu_438_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln136_1_fu_343_p2 = (x_reg_168 | 9'd2); + +assign or_ln136_2_fu_354_p2 = (x_reg_168 | 9'd3); + +assign or_ln136_3_fu_365_p2 = (x_reg_168 | 9'd4); + +assign or_ln136_4_fu_376_p2 = (x_reg_168 | 9'd5); + +assign or_ln136_5_fu_393_p2 = (x_reg_168 | 9'd6); + +assign or_ln136_6_fu_404_p2 = (x_reg_168 | 9'd7); + +assign or_ln136_fu_332_p2 = (ap_phi_mux_x_phi_fu_172_p4 | 9'd1); + +assign or_ln140_fu_438_p2 = (trunc_ln140_fu_428_p1 | 3'd1); + +assign select_ln152_1_fu_469_p3 = ((icmp_ln152_1_fu_463_p2[0:0] == 1'b1) ? psum_3_04_reg_228 : select_ln152_fu_455_p3); + +assign select_ln152_fu_455_p3 = ((icmp_ln152_fu_449_p2[0:0] == 1'b1) ? psum_1_02_reg_252 : psum_7_08_reg_180); + +assign tmp_fu_415_p3 = q_reg_276[32'd3]; + +assign trunc_ln140_fu_428_p1 = q_reg_276[2:0]; + +assign zext_ln132_fu_327_p1 = ap_phi_mux_x_phi_fu_172_p4; + +assign zext_ln136_1_fu_349_p1 = or_ln136_1_fu_343_p2; + +assign zext_ln136_2_fu_360_p1 = or_ln136_2_fu_354_p2; + +assign zext_ln136_3_fu_371_p1 = or_ln136_3_fu_365_p2; + +assign zext_ln136_4_fu_382_p1 = or_ln136_4_fu_376_p2; + +assign zext_ln136_5_fu_399_p1 = or_ln136_5_fu_393_p2; + +assign zext_ln136_6_fu_410_p1 = or_ln136_6_fu_404_p2; + +assign zext_ln136_fu_338_p1 = or_ln136_fu_332_p2; + +assign zext_ln140_1_fu_444_p1 = or_ln140_fu_438_p2; + +assign zext_ln140_fu_423_p1 = q_reg_276; + +endmodule //td_fused_top_tdf7_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_6, + accum_in_6_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 7'd1; +parameter ap_ST_fsm_state2 = 7'd2; +parameter ap_ST_fsm_state3 = 7'd4; +parameter ap_ST_fsm_state4 = 7'd8; +parameter ap_ST_fsm_state5 = 7'd16; +parameter ap_ST_fsm_state6 = 7'd32; +parameter ap_ST_fsm_state7 = 7'd64; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_6; +output accum_in_6_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_6; +reg accum_in_6_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [6:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln164_fu_74_p2; +reg [3:0] add_ln164_reg_91; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln164_fu_85_p2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state7; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln164_fu_80_p1; +reg [15:0] accum_in_6_preg; +reg [6:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 7'd1; +#0 accum_in_6_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U425( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_q0), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_6_preg <= 16'd0; + end else begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_6_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + i_1_1_reg_44 <= add_ln164_reg_91; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln164_reg_91 <= add_ln164_fu_74_p2; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_6 = sum_01_reg_55; + end else begin + accum_in_6 = accum_in_6_preg; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_6_ap_vld = 1'b1; + end else begin + accum_in_6_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln164_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln164_fu_80_p1; + +assign add_ln164_fu_74_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln164_fu_85_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln164_fu_80_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf7_accum_2 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_adjustments_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 48; +parameter AWIDTH = 8; +parameter MEM_SIZE = 256; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_adjustments( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd48; +parameter AddressRange = 32'd256; +parameter AddressWidth = 32'd8; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf7_adjustments_ram td_fused_top_tdf7_adjustments_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + indices_23_out_din, + indices_23_out_full_n, + indices_23_out_write, + ap_return +); + +parameter ap_ST_fsm_state1 = 17'd1; +parameter ap_ST_fsm_state2 = 17'd2; +parameter ap_ST_fsm_state3 = 17'd4; +parameter ap_ST_fsm_state4 = 17'd8; +parameter ap_ST_fsm_state5 = 17'd16; +parameter ap_ST_fsm_state6 = 17'd32; +parameter ap_ST_fsm_state7 = 17'd64; +parameter ap_ST_fsm_state8 = 17'd128; +parameter ap_ST_fsm_state9 = 17'd256; +parameter ap_ST_fsm_state10 = 17'd512; +parameter ap_ST_fsm_state11 = 17'd1024; +parameter ap_ST_fsm_state12 = 17'd2048; +parameter ap_ST_fsm_state13 = 17'd4096; +parameter ap_ST_fsm_state14 = 17'd8192; +parameter ap_ST_fsm_state15 = 17'd16384; +parameter ap_ST_fsm_state16 = 17'd32768; +parameter ap_ST_fsm_state17 = 17'd65536; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_read; +output [7:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [12:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [12:0] indices_23_out_din; +input indices_23_out_full_n; +output indices_23_out_write; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg indices_23_read; +reg indices_23_out_write; + +reg ap_done_reg; + reg [16:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg indices_23_out_blk_n; +wire ap_CS_fsm_state4; +reg [15:0] tmp_26_i_i_reg_183; +reg [15:0] tmp_27_i_i_reg_188; +wire [15:0] grp_fu_93_p2; +reg [15:0] sub_i_i_i_reg_193; +wire ap_CS_fsm_state8; +wire ap_CS_fsm_state9; +wire [15:0] grp_fu_98_p2; +reg [15:0] mul_i_i_i_reg_203; +wire ap_CS_fsm_state12; +wire ap_CS_fsm_state13; +wire [63:0] zext_ln220_fu_106_p1; +reg ap_block_state1; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_89_p1; +wire [15:0] grp_fu_93_p1; +wire [15:0] grp_fu_98_p1; +wire [7:0] trunc_ln251_fu_102_p1; +wire [15:0] trunc_ln220_fu_111_p1; +wire [15:0] grp_fu_89_p2; +wire ap_CS_fsm_state17; +wire [15:0] bitcast_ln648_fu_148_p1; +wire [0:0] tmp_fu_152_p3; +reg [16:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 17'd1; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U429( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(mul_i_i_i_reg_203), + .din1(grp_fu_89_p1), + .dout(grp_fu_89_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U430( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sums_read), + .din1(grp_fu_93_p1), + .dout(grp_fu_93_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U431( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_193), + .din1(grp_fu_98_p1), + .dout(grp_fu_98_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + mul_i_i_i_reg_203 <= grp_fu_98_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sub_i_i_i_reg_193 <= grp_fu_93_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tmp_26_i_i_reg_183 <= {{adjustments_q0[31:16]}}; + tmp_27_i_i_reg_188 <= {{adjustments_q0[47:32]}}; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_out_blk_n = indices_23_out_full_n; + end else begin + indices_23_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_out_write = 1'b1; + end else begin + indices_23_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign adjustments_address0 = zext_ln220_fu_106_p1; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((indices_23_out_full_n == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_return = ((tmp_fu_152_p3[0:0] == 1'b1) ? 16'd0 : grp_fu_89_p2); + +assign bitcast_ln648_fu_148_p1 = grp_fu_89_p2; + +assign grp_fu_89_p1 = tmp_27_i_i_reg_188; + +assign grp_fu_93_p1 = trunc_ln220_fu_111_p1; + +assign grp_fu_98_p1 = tmp_26_i_i_reg_183; + +assign indices_23_out_din = indices_23_dout; + +assign tmp_fu_152_p3 = bitcast_ln648_fu_148_p1[32'd15]; + +assign trunc_ln220_fu_111_p1 = adjustments_q0[15:0]; + +assign trunc_ln251_fu_102_p1 = indices_23_dout[7:0]; + +assign zext_ln220_fu_106_p1 = trunc_ln251_fu_102_p1; + +endmodule //td_fused_top_tdf7_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_q0, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [8:0] ifmap_vec_address0; +output ifmap_vec_ce0; +input [15:0] ifmap_vec_q0; +output [8:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +input [15:0] weight_vecs_0_q0; +output [8:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_ce0; +reg weight_vecs_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [8:0] indvar_flatten17_reg_97; +reg [7:0] indvar_flatten_reg_108; +reg [1:0] jj_reg_119; +reg [5:0] ic_reg_131; +reg [1:0] ii_reg_142; +wire [8:0] add_ln147_2_fu_157_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln147_fu_163_p2; +reg [0:0] icmp_ln147_reg_408; +reg [0:0] icmp_ln147_reg_408_pp0_iter1_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter2_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter3_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter4_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter5_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter6_reg; +wire [0:0] icmp_ln148_fu_169_p2; +reg [0:0] icmp_ln148_reg_412; +wire [0:0] and_ln147_fu_195_p2; +reg [0:0] and_ln147_reg_419; +wire [1:0] add_ln148_fu_201_p2; +reg [1:0] add_ln148_reg_424; +wire [5:0] select_ln148_fu_213_p3; +reg [5:0] select_ln148_reg_429; +wire [1:0] select_ln148_4_fu_221_p3; +reg [1:0] select_ln148_4_reg_434; +wire [4:0] trunc_ln150_fu_229_p1; +reg [4:0] trunc_ln150_reg_440; +reg [4:0] trunc_ln150_reg_440_pp0_iter1_reg; +reg [4:0] trunc_ln150_reg_440_pp0_iter2_reg; +reg [4:0] trunc_ln150_reg_440_pp0_iter3_reg; +reg [4:0] trunc_ln150_reg_440_pp0_iter4_reg; +reg [4:0] trunc_ln150_reg_440_pp0_iter5_reg; +reg [4:0] trunc_ln150_reg_440_pp0_iter6_reg; +wire [5:0] add_ln149_fu_233_p2; +wire [7:0] select_ln148_6_fu_245_p3; +wire [1:0] select_ln147_5_fu_287_p3; +reg [1:0] select_ln147_5_reg_455; +reg ap_enable_reg_pp0_iter1; +wire [3:0] select_ln148_5_fu_370_p3; +reg [3:0] select_ln148_5_reg_460; +reg [3:0] select_ln148_5_reg_460_pp0_iter2_reg; +reg [3:0] select_ln148_5_reg_460_pp0_iter3_reg; +reg [3:0] select_ln148_5_reg_460_pp0_iter4_reg; +reg [3:0] select_ln148_5_reg_460_pp0_iter5_reg; +reg [3:0] select_ln148_5_reg_460_pp0_iter6_reg; +reg [15:0] ifmap_vec_load_reg_475; +reg [15:0] weight_vecs_0_load_reg_480; +wire [15:0] grp_fu_153_p2; +reg [15:0] mul_reg_485; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg [1:0] ap_phi_mux_jj_phi_fu_123_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_146_p4; +wire [63:0] p_cast25_fu_386_p1; +wire [63:0] idxprom30_fu_398_p1; +wire [0:0] icmp_ln149_fu_189_p2; +wire [0:0] xor_ln147_fu_183_p2; +wire [1:0] select_ln147_fu_175_p3; +wire [0:0] or_ln148_fu_207_p2; +wire [7:0] add_ln148_2_fu_239_p2; +wire [3:0] shl_ln_fu_257_p3; +wire [3:0] zext_ln150_fu_253_p1; +wire [3:0] sub_ln150_fu_265_p2; +wire [3:0] zext_ln150_2_fu_271_p1; +wire [1:0] add_ln147_fu_281_p2; +wire [3:0] tmp_fu_298_p3; +wire [3:0] select_ln147_6_cast_fu_294_p1; +wire [3:0] shl_ln150_mid1_fu_316_p3; +wire [3:0] zext_ln150_4_fu_312_p1; +wire [3:0] sub_ln150_2_fu_324_p2; +wire [3:0] add_ln150_fu_275_p2; +wire [3:0] empty_74_fu_306_p2; +wire [3:0] select_ln148_5_cast_fu_344_p1; +wire [3:0] empty_75_fu_347_p2; +wire [3:0] select_ln147_6_fu_330_p3; +wire [3:0] zext_ln150_5_fu_361_p1; +wire [3:0] add_ln150_2_fu_364_p2; +wire [3:0] select_ln147_7_fu_337_p3; +wire [8:0] tmp_50_cast_fu_353_p3; +wire [8:0] select_ln148_cast_fu_377_p1; +wire [8:0] empty_76_fu_380_p2; +wire [8:0] p_fu_392_p3; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U417( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_load_reg_475), + .din1(weight_vecs_0_load_reg_480), + .dout(grp_fu_153_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_reg_131 <= add_ln149_fu_233_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_reg_131 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ii_reg_142 <= select_ln147_5_reg_455; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_142 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten17_reg_97 <= add_ln147_2_fu_157_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten17_reg_97 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_108 <= select_ln148_6_fu_245_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_108 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_119 <= select_ln148_4_reg_434; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_119 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln148_reg_424 <= add_ln148_fu_201_p2; + and_ln147_reg_419 <= and_ln147_fu_195_p2; + icmp_ln148_reg_412 <= icmp_ln148_fu_169_p2; + select_ln148_reg_429 <= select_ln148_fu_213_p3; + trunc_ln150_reg_440 <= trunc_ln150_fu_229_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln147_reg_408 <= icmp_ln147_fu_163_p2; + icmp_ln147_reg_408_pp0_iter1_reg <= icmp_ln147_reg_408; + trunc_ln150_reg_440_pp0_iter1_reg <= trunc_ln150_reg_440; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln147_reg_408_pp0_iter2_reg <= icmp_ln147_reg_408_pp0_iter1_reg; + icmp_ln147_reg_408_pp0_iter3_reg <= icmp_ln147_reg_408_pp0_iter2_reg; + icmp_ln147_reg_408_pp0_iter4_reg <= icmp_ln147_reg_408_pp0_iter3_reg; + icmp_ln147_reg_408_pp0_iter5_reg <= icmp_ln147_reg_408_pp0_iter4_reg; + icmp_ln147_reg_408_pp0_iter6_reg <= icmp_ln147_reg_408_pp0_iter5_reg; + select_ln148_5_reg_460_pp0_iter2_reg <= select_ln148_5_reg_460; + select_ln148_5_reg_460_pp0_iter3_reg <= select_ln148_5_reg_460_pp0_iter2_reg; + select_ln148_5_reg_460_pp0_iter4_reg <= select_ln148_5_reg_460_pp0_iter3_reg; + select_ln148_5_reg_460_pp0_iter5_reg <= select_ln148_5_reg_460_pp0_iter4_reg; + select_ln148_5_reg_460_pp0_iter6_reg <= select_ln148_5_reg_460_pp0_iter5_reg; + trunc_ln150_reg_440_pp0_iter2_reg <= trunc_ln150_reg_440_pp0_iter1_reg; + trunc_ln150_reg_440_pp0_iter3_reg <= trunc_ln150_reg_440_pp0_iter2_reg; + trunc_ln150_reg_440_pp0_iter4_reg <= trunc_ln150_reg_440_pp0_iter3_reg; + trunc_ln150_reg_440_pp0_iter5_reg <= trunc_ln150_reg_440_pp0_iter4_reg; + trunc_ln150_reg_440_pp0_iter6_reg <= trunc_ln150_reg_440_pp0_iter5_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_load_reg_475 <= ifmap_vec_q0; + weight_vecs_0_load_reg_480 <= weight_vecs_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_reg_485 <= grp_fu_153_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + select_ln147_5_reg_455 <= select_ln147_5_fu_287_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_4_reg_434 <= select_ln148_4_fu_221_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_5_reg_460 <= select_ln148_5_fu_370_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_fu_163_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_146_p4 = select_ln147_5_reg_455; + end else begin + ap_phi_mux_ii_phi_fu_146_p4 = ii_reg_142; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_123_p4 = select_ln148_4_reg_434; + end else begin + ap_phi_mux_jj_phi_fu_123_p4 = jj_reg_119; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_2_fu_157_p2 = (indvar_flatten17_reg_97 + 9'd1); + +assign add_ln147_fu_281_p2 = (ap_phi_mux_ii_phi_fu_146_p4 + 2'd1); + +assign add_ln148_2_fu_239_p2 = (indvar_flatten_reg_108 + 8'd1); + +assign add_ln148_fu_201_p2 = (select_ln147_fu_175_p3 + 2'd1); + +assign add_ln149_fu_233_p2 = (select_ln148_fu_213_p3 + 6'd1); + +assign add_ln150_2_fu_364_p2 = (select_ln147_6_fu_330_p3 + zext_ln150_5_fu_361_p1); + +assign add_ln150_fu_275_p2 = (sub_ln150_fu_265_p2 + zext_ln150_2_fu_271_p1); + +assign and_ln147_fu_195_p2 = (xor_ln147_fu_183_p2 & icmp_ln149_fu_189_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign empty_74_fu_306_p2 = (tmp_fu_298_p3 - select_ln147_6_cast_fu_294_p1); + +assign empty_75_fu_347_p2 = (empty_74_fu_306_p2 + select_ln148_5_cast_fu_344_p1); + +assign empty_76_fu_380_p2 = (tmp_50_cast_fu_353_p3 + select_ln148_cast_fu_377_p1); + +assign icmp_ln147_fu_163_p2 = ((indvar_flatten17_reg_97 == 9'd288) ? 1'b1 : 1'b0); + +assign icmp_ln148_fu_169_p2 = ((indvar_flatten_reg_108 == 8'd96) ? 1'b1 : 1'b0); + +assign icmp_ln149_fu_189_p2 = ((ic_reg_131 == 6'd32) ? 1'b1 : 1'b0); + +assign idxprom30_fu_398_p1 = p_fu_392_p3; + +assign ifmap_vec_address0 = p_cast25_fu_386_p1; + +assign or_ln148_fu_207_p2 = (icmp_ln148_fu_169_p2 | and_ln147_fu_195_p2); + +assign p_cast25_fu_386_p1 = empty_76_fu_380_p2; + +assign p_fu_392_p3 = {{select_ln148_5_reg_460_pp0_iter6_reg}, {trunc_ln150_reg_440_pp0_iter6_reg}}; + +assign products_0_address0 = idxprom30_fu_398_p1; + +assign products_0_d0 = mul_reg_485; + +assign select_ln147_5_fu_287_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? add_ln147_fu_281_p2 : ap_phi_mux_ii_phi_fu_146_p4); + +assign select_ln147_6_cast_fu_294_p1 = select_ln147_5_fu_287_p3; + +assign select_ln147_6_fu_330_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? sub_ln150_2_fu_324_p2 : sub_ln150_fu_265_p2); + +assign select_ln147_7_fu_337_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? sub_ln150_2_fu_324_p2 : add_ln150_fu_275_p2); + +assign select_ln147_fu_175_p3 = ((icmp_ln148_fu_169_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_123_p4); + +assign select_ln148_4_fu_221_p3 = ((and_ln147_fu_195_p2[0:0] == 1'b1) ? add_ln148_fu_201_p2 : select_ln147_fu_175_p3); + +assign select_ln148_5_cast_fu_344_p1 = select_ln148_4_reg_434; + +assign select_ln148_5_fu_370_p3 = ((and_ln147_reg_419[0:0] == 1'b1) ? add_ln150_2_fu_364_p2 : select_ln147_7_fu_337_p3); + +assign select_ln148_6_fu_245_p3 = ((icmp_ln148_fu_169_p2[0:0] == 1'b1) ? 8'd1 : add_ln148_2_fu_239_p2); + +assign select_ln148_cast_fu_377_p1 = select_ln148_reg_429; + +assign select_ln148_fu_213_p3 = ((or_ln148_fu_207_p2[0:0] == 1'b1) ? 6'd0 : ic_reg_131); + +assign shl_ln150_mid1_fu_316_p3 = {{add_ln147_fu_281_p2}, {2'd0}}; + +assign shl_ln_fu_257_p3 = {{ap_phi_mux_ii_phi_fu_146_p4}, {2'd0}}; + +assign sub_ln150_2_fu_324_p2 = (shl_ln150_mid1_fu_316_p3 - zext_ln150_4_fu_312_p1); + +assign sub_ln150_fu_265_p2 = (shl_ln_fu_257_p3 - zext_ln150_fu_253_p1); + +assign tmp_50_cast_fu_353_p3 = {{empty_75_fu_347_p2}, {5'd0}}; + +assign tmp_fu_298_p3 = {{select_ln147_5_fu_287_p3}, {2'd0}}; + +assign trunc_ln150_fu_229_p1 = select_ln148_fu_213_p3[4:0]; + +assign weight_vecs_0_address0 = p_cast25_fu_386_p1; + +assign xor_ln147_fu_183_p2 = (icmp_ln148_fu_169_p2 ^ 1'd1); + +assign zext_ln150_2_fu_271_p1 = jj_reg_119; + +assign zext_ln150_4_fu_312_p1 = add_ln147_fu_281_p2; + +assign zext_ln150_5_fu_361_p1 = add_ln148_reg_424; + +assign zext_ln150_fu_253_p1 = ap_phi_mux_ii_phi_fu_146_p4; + +endmodule //td_fused_top_tdf7_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 17; +parameter MEM_SIZE = 73728; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd73728; +parameter AddressWidth = 32'd17; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf7_filters_ram td_fused_top_tdf7_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + indices_2_out_din, + indices_2_out_full_n, + indices_2_out_write, + indices_2_out1_din, + indices_2_out1_full_n, + indices_2_out1_write, + write_r_din, + write_r_full_n, + write_r_write +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [7:0] indices_2_out_din; +input indices_2_out_full_n; +output indices_2_out_write; +output [12:0] indices_2_out1_din; +input indices_2_out1_full_n; +output indices_2_out1_write; +output write_r_din; +input write_r_full_n; +output write_r_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg indices_0_write; +reg indices_1_write; +reg indices_2_out_write; +reg indices_2_out1_write; +reg write_r_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [15:0] i_11; +reg [15:0] j_11; +reg [15:0] k_11; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg indices_2_out_blk_n; +reg indices_2_out1_blk_n; +reg write_r_blk_n; +reg [0:0] ap_phi_mux_j_18_flag_0_i_phi_fu_92_p6; +reg ap_block_state1; +wire [0:0] icmp_ln188_fu_167_p2; +wire [0:0] icmp_ln191_fu_180_p2; +reg [15:0] ap_phi_mux_j_18_new_0_i_phi_fu_106_p6; +wire [15:0] add_ln190_fu_173_p2; +reg [15:0] ap_phi_mux_k_18_new_0_i_phi_fu_119_p6; +wire [15:0] add_ln187_fu_160_p2; +wire [15:0] select_ln194_fu_198_p3; +wire [15:0] add_ln193_fu_186_p2; +wire [0:0] icmp_ln194_fu_192_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_11 = 16'd0; +#0 j_11 = 16'd0; +#0 k_11 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln191_fu_180_p2 == 1'd1) & (icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_11 <= select_ln194_fu_198_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_18_flag_0_i_phi_fu_92_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j_11 <= ap_phi_mux_j_18_new_0_i_phi_fu_106_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k_11 <= ap_phi_mux_k_18_new_0_i_phi_fu_119_p6; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln188_fu_167_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_18_flag_0_i_phi_fu_92_p6 = 1'd0; + end else if ((((icmp_ln191_fu_180_p2 == 1'd0) & (icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln191_fu_180_p2 == 1'd1) & (icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_18_flag_0_i_phi_fu_92_p6 = 1'd1; + end else begin + ap_phi_mux_j_18_flag_0_i_phi_fu_92_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln191_fu_180_p2 == 1'd0)) begin + ap_phi_mux_j_18_new_0_i_phi_fu_106_p6 = add_ln190_fu_173_p2; + end else if ((icmp_ln191_fu_180_p2 == 1'd1)) begin + ap_phi_mux_j_18_new_0_i_phi_fu_106_p6 = 16'd0; + end else begin + ap_phi_mux_j_18_new_0_i_phi_fu_106_p6 = 'bx; + end + end else begin + ap_phi_mux_j_18_new_0_i_phi_fu_106_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln188_fu_167_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_18_new_0_i_phi_fu_119_p6 = add_ln187_fu_160_p2; + end else if ((((icmp_ln191_fu_180_p2 == 1'd0) & (icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln191_fu_180_p2 == 1'd1) & (icmp_ln188_fu_167_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_18_new_0_i_phi_fu_119_p6 = 16'd0; + end else begin + ap_phi_mux_k_18_new_0_i_phi_fu_119_p6 = 'bx; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_blk_n = indices_2_out1_full_n; + end else begin + indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_write = 1'b1; + end else begin + indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_blk_n = indices_2_out_full_n; + end else begin + indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_write = 1'b1; + end else begin + indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_r_blk_n = write_r_full_n; + end else begin + write_r_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write_r_write = 1'b1; + end else begin + write_r_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln187_fu_160_p2 = (k_11 + 16'd1); + +assign add_ln190_fu_173_p2 = (j_11 + 16'd1); + +assign add_ln193_fu_186_p2 = (i_11 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (write_r_full_n == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign icmp_ln188_fu_167_p2 = ((add_ln187_fu_160_p2 == 16'd256) ? 1'b1 : 1'b0); + +assign icmp_ln191_fu_180_p2 = ((add_ln190_fu_173_p2 == 16'd28) ? 1'b1 : 1'b0); + +assign icmp_ln194_fu_192_p2 = ((add_ln193_fu_186_p2 == 16'd28) ? 1'b1 : 1'b0); + +assign indices_0_din = i_11; + +assign indices_1_din = j_11; + +assign indices_2_out1_din = k_11[12:0]; + +assign indices_2_out_din = k_11[7:0]; + +assign select_ln194_fu_198_p3 = ((icmp_ln194_fu_192_p2[0:0] == 1'b1) ? 16'd0 : add_ln193_fu_186_p2); + +assign start_out = real_start; + +assign write_r_din = ((k_11 == 16'd255) ? 1'b1 : 1'b0); + +endmodule //td_fused_top_tdf7_get_next_ijk +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_l2_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 13; +parameter MEM_SIZE = 8192; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_l2_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd8192; +parameter AddressWidth = 32'd13; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf7_l2_filters_ram td_fused_top_tdf7_l2_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_l2_multiply50 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + intermediate_fmaps_read, + l2_filter_data_address0, + l2_filter_data_ce0, + l2_filter_data_q0, + l2_products_address0, + l2_products_ce0, + l2_products_we0, + l2_products_d0, + indices_23_dout, + indices_23_empty_n, + indices_23_read +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] intermediate_fmaps_read; +output [12:0] l2_filter_data_address0; +output l2_filter_data_ce0; +input [15:0] l2_filter_data_q0; +output [4:0] l2_products_address0; +output l2_products_ce0; +output l2_products_we0; +output [15:0] l2_products_d0; +input [12:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg l2_filter_data_ce0; +reg l2_products_ce0; +reg l2_products_we0; +reg indices_23_read; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [5:0] i_1_1_reg_106; +reg [12:0] l2_ichan_reg_165; +wire [5:0] add_ln20_fu_122_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln20_fu_128_p2; +reg [0:0] icmp_ln20_reg_175; +reg [0:0] icmp_ln20_reg_175_pp0_iter1_reg; +reg [0:0] icmp_ln20_reg_175_pp0_iter2_reg; +reg [0:0] icmp_ln20_reg_175_pp0_iter3_reg; +reg [0:0] icmp_ln20_reg_175_pp0_iter4_reg; +reg [0:0] icmp_ln20_reg_175_pp0_iter5_reg; +reg [0:0] icmp_ln20_reg_175_pp0_iter6_reg; +wire [4:0] l2_o_fu_134_p1; +reg [4:0] l2_o_reg_179; +reg [4:0] l2_o_reg_179_pp0_iter1_reg; +reg [4:0] l2_o_reg_179_pp0_iter2_reg; +reg [4:0] l2_o_reg_179_pp0_iter3_reg; +reg [4:0] l2_o_reg_179_pp0_iter4_reg; +reg [4:0] l2_o_reg_179_pp0_iter5_reg; +reg [4:0] l2_o_reg_179_pp0_iter6_reg; +wire [15:0] grp_fu_117_p2; +reg [15:0] mul_i_i_reg_194; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +wire [63:0] zext_ln29_7_fu_151_p1; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln29_fu_156_p1; +wire [12:0] tmp_s_fu_138_p3; +wire [12:0] add_ln29_fu_146_p2; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U436( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(l2_filter_data_q0), + .din1(intermediate_fmaps_read), + .dout(grp_fu_117_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_106 <= 6'd0; + end else if (((icmp_ln20_fu_128_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + i_1_1_reg_106 <= add_ln20_fu_122_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln20_reg_175 <= icmp_ln20_fu_128_p2; + icmp_ln20_reg_175_pp0_iter1_reg <= icmp_ln20_reg_175; + l2_o_reg_179_pp0_iter1_reg <= l2_o_reg_179; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln20_reg_175_pp0_iter2_reg <= icmp_ln20_reg_175_pp0_iter1_reg; + icmp_ln20_reg_175_pp0_iter3_reg <= icmp_ln20_reg_175_pp0_iter2_reg; + icmp_ln20_reg_175_pp0_iter4_reg <= icmp_ln20_reg_175_pp0_iter3_reg; + icmp_ln20_reg_175_pp0_iter5_reg <= icmp_ln20_reg_175_pp0_iter4_reg; + icmp_ln20_reg_175_pp0_iter6_reg <= icmp_ln20_reg_175_pp0_iter5_reg; + l2_o_reg_179_pp0_iter2_reg <= l2_o_reg_179_pp0_iter1_reg; + l2_o_reg_179_pp0_iter3_reg <= l2_o_reg_179_pp0_iter2_reg; + l2_o_reg_179_pp0_iter4_reg <= l2_o_reg_179_pp0_iter3_reg; + l2_o_reg_179_pp0_iter5_reg <= l2_o_reg_179_pp0_iter4_reg; + l2_o_reg_179_pp0_iter6_reg <= l2_o_reg_179_pp0_iter5_reg; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + l2_ichan_reg_165 <= indices_23_dout; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln20_fu_128_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + l2_o_reg_179 <= l2_o_fu_134_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln20_reg_175_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_i_i_reg_194 <= grp_fu_117_p2; + end +end + +always @ (*) begin + if ((icmp_ln20_fu_128_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + l2_filter_data_ce0 = 1'b1; + end else begin + l2_filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + l2_products_ce0 = 1'b1; + end else begin + l2_products_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln20_reg_175_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + l2_products_we0 = 1'b1; + end else begin + l2_products_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln20_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln20_fu_128_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln20_fu_122_p2 = (i_1_1_reg_106 + 6'd1); + +assign add_ln29_fu_146_p2 = (tmp_s_fu_138_p3 + l2_ichan_reg_165); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign icmp_ln20_fu_128_p2 = ((i_1_1_reg_106 == 6'd32) ? 1'b1 : 1'b0); + +assign l2_filter_data_address0 = zext_ln29_7_fu_151_p1; + +assign l2_o_fu_134_p1 = i_1_1_reg_106[4:0]; + +assign l2_products_address0 = zext_ln29_fu_156_p1; + +assign l2_products_d0 = mul_i_i_reg_194; + +assign tmp_s_fu_138_p3 = {{l2_o_fu_134_p1}, {8'd0}}; + +assign zext_ln29_7_fu_151_p1 = add_ln29_fu_146_p2; + +assign zext_ln29_fu_156_p1 = l2_o_reg_179_pp0_iter6_reg; + +endmodule //td_fused_top_tdf7_l2_multiply50 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_l2_writeOutputs_149_running_sums_ram (addr0, ce0, d0, we0, addr1, ce1, q1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 5; +parameter MEM_SIZE = 32; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; + +//initial begin +// $readmemh("./td_fused_top_tdf7_l2_writeOutputs_149_running_sums_ram.dat", ram); +//end + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram[addr0] <= d0; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram[addr1]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf7_l2_writeOutputs_149_running_sums( + reset, + clk, + address0, + ce0, + we0, + d0, + address1, + ce1, + q1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd32; +parameter AddressWidth = 32'd5; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; + + + +td_fused_top_tdf7_l2_writeOutputs_149_running_sums_ram td_fused_top_tdf7_l2_writeOutputs_149_running_sums_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_l2_writeOutputs_149 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + write4_dout, + write4_empty_n, + write4_read, + l2_partial_sums_address0, + l2_partial_sums_ce0, + l2_partial_sums_q0, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1, + l2_adjustments_address0, + l2_adjustments_ce0, + l2_adjustments_q0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state25 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [4:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [9:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [0:0] write4_dout; +input write4_empty_n; +output write4_read; +output [4:0] l2_partial_sums_address0; +output l2_partial_sums_ce0; +input [15:0] l2_partial_sums_q0; +output [12:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; +output [4:0] l2_adjustments_address0; +output l2_adjustments_ce0; +input [47:0] l2_adjustments_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg write4_read; +reg l2_partial_sums_ce0; +reg out_data_ce1; +reg out_data_we1; +reg l2_adjustments_ce0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg running_sums_ce0; +reg running_sums_we0; +wire [15:0] running_sums_d0; +wire [4:0] running_sums_address1; +reg running_sums_ce1; +wire [15:0] running_sums_q1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg write4_blk_n; +reg [5:0] ochan_reg_206; +reg [0:0] write4_read_reg_565; +wire [11:0] add_ln109_fu_271_p2; +reg [11:0] add_ln109_reg_571; +wire [5:0] add_ln86_fu_277_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_state10_pp0_stage0_iter8; +wire ap_block_state11_pp0_stage0_iter9; +wire ap_block_state12_pp0_stage0_iter10; +wire ap_block_state13_pp0_stage0_iter11; +wire ap_block_state14_pp0_stage0_iter12; +wire ap_block_state15_pp0_stage0_iter13; +wire ap_block_state16_pp0_stage0_iter14; +wire ap_block_state17_pp0_stage0_iter15; +wire ap_block_state18_pp0_stage0_iter16; +wire ap_block_state19_pp0_stage0_iter17; +wire ap_block_state20_pp0_stage0_iter18; +wire ap_block_state21_pp0_stage0_iter19; +wire ap_block_state22_pp0_stage0_iter20; +wire ap_block_state23_pp0_stage0_iter21; +wire ap_block_state24_pp0_stage0_iter22; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln86_fu_283_p2; +wire [63:0] zext_ln86_fu_289_p1; +reg [63:0] zext_ln86_reg_585; +reg [63:0] zext_ln86_reg_585_pp0_iter1_reg; +reg [63:0] zext_ln86_reg_585_pp0_iter2_reg; +reg [63:0] zext_ln86_reg_585_pp0_iter3_reg; +reg [4:0] running_sums_addr_reg_595; +reg [4:0] running_sums_addr_reg_595_pp0_iter1_reg; +reg [4:0] running_sums_addr_reg_595_pp0_iter2_reg; +reg [4:0] running_sums_addr_reg_595_pp0_iter3_reg; +reg [4:0] running_sums_addr_reg_595_pp0_iter4_reg; +reg [4:0] running_sums_addr_reg_595_pp0_iter5_reg; +reg [4:0] running_sums_addr_reg_595_pp0_iter6_reg; +wire [1:0] trunc_ln99_fu_295_p1; +reg [1:0] trunc_ln99_reg_601; +reg [1:0] trunc_ln99_reg_601_pp0_iter1_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter2_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter3_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter4_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter5_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter6_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter7_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter8_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter9_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter10_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter11_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter12_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter13_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter14_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter15_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter16_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter17_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter18_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter19_reg; +reg [1:0] trunc_ln99_reg_601_pp0_iter20_reg; +wire [0:0] and_ln103_fu_305_p2; +reg [0:0] and_ln103_reg_608; +reg [0:0] and_ln103_reg_608_pp0_iter1_reg; +reg [0:0] and_ln103_reg_608_pp0_iter2_reg; +reg [0:0] and_ln103_reg_608_pp0_iter3_reg; +reg [0:0] and_ln103_reg_608_pp0_iter4_reg; +reg [0:0] and_ln103_reg_608_pp0_iter5_reg; +reg [0:0] and_ln103_reg_608_pp0_iter6_reg; +reg [0:0] and_ln103_reg_608_pp0_iter7_reg; +reg [0:0] and_ln103_reg_608_pp0_iter8_reg; +reg [0:0] and_ln103_reg_608_pp0_iter9_reg; +reg [0:0] and_ln103_reg_608_pp0_iter10_reg; +reg [0:0] and_ln103_reg_608_pp0_iter11_reg; +reg [0:0] and_ln103_reg_608_pp0_iter12_reg; +reg [0:0] and_ln103_reg_608_pp0_iter13_reg; +reg [0:0] and_ln103_reg_608_pp0_iter14_reg; +reg [0:0] and_ln103_reg_608_pp0_iter15_reg; +reg [0:0] and_ln103_reg_608_pp0_iter16_reg; +reg [0:0] and_ln103_reg_608_pp0_iter17_reg; +reg [0:0] and_ln103_reg_608_pp0_iter18_reg; +reg [0:0] and_ln103_reg_608_pp0_iter19_reg; +reg [0:0] and_ln103_reg_608_pp0_iter20_reg; +reg [2:0] lshr_ln_reg_612; +reg [2:0] lshr_ln_reg_612_pp0_iter1_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter2_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter3_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter4_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter5_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter6_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter7_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter8_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter9_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter10_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter11_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter12_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter13_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter14_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter15_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter16_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter17_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter18_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter19_reg; +reg [2:0] lshr_ln_reg_612_pp0_iter20_reg; +reg [15:0] val_reg_617; +reg [15:0] running_sums_load_reg_622; +reg ap_enable_reg_pp0_iter1; +wire [15:0] grp_fu_217_p2; +reg [15:0] sum_reg_632; +reg [15:0] tmp_20_i_i_reg_643; +reg [15:0] tmp_20_i_i_reg_643_pp0_iter8_reg; +reg [15:0] tmp_20_i_i_reg_643_pp0_iter9_reg; +reg [15:0] tmp_20_i_i_reg_643_pp0_iter10_reg; +reg [15:0] tmp_20_i_i_reg_643_pp0_iter11_reg; +reg [15:0] tmp_21_i_i_reg_648; +reg [15:0] tmp_21_i_i_reg_648_pp0_iter8_reg; +reg [15:0] tmp_21_i_i_reg_648_pp0_iter9_reg; +reg [15:0] tmp_21_i_i_reg_648_pp0_iter10_reg; +reg [15:0] tmp_21_i_i_reg_648_pp0_iter11_reg; +reg [15:0] tmp_21_i_i_reg_648_pp0_iter12_reg; +reg [15:0] tmp_21_i_i_reg_648_pp0_iter13_reg; +reg [15:0] tmp_21_i_i_reg_648_pp0_iter14_reg; +reg [15:0] tmp_21_i_i_reg_648_pp0_iter15_reg; +wire [15:0] grp_fu_225_p2; +reg [15:0] sub_i_i_i_reg_653; +wire [15:0] grp_fu_229_p2; +reg [15:0] normalized_reg_663; +wire [15:0] grp_fu_221_p2; +reg [15:0] biased_reg_673; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg ap_enable_reg_pp0_iter8; +reg ap_enable_reg_pp0_iter9; +reg ap_enable_reg_pp0_iter10; +reg ap_enable_reg_pp0_iter11; +reg ap_enable_reg_pp0_iter12; +reg ap_enable_reg_pp0_iter13; +reg ap_enable_reg_pp0_iter14; +reg ap_enable_reg_pp0_iter15; +reg ap_enable_reg_pp0_iter16; +reg ap_enable_reg_pp0_iter17; +reg ap_enable_reg_pp0_iter18; +reg ap_enable_reg_pp0_iter19; +reg ap_enable_reg_pp0_iter20; +reg ap_enable_reg_pp0_iter21; +reg ap_enable_reg_pp0_iter22; +wire ap_block_pp0_stage0; +wire [63:0] sext_ln109_fu_507_p1; +reg [15:0] quad_3_1_fu_112; +wire [15:0] quad_3_13_fu_473_p3; +reg [15:0] quad_3_2_fu_116; +wire [15:0] quad_3_12_fu_465_p3; +reg [15:0] quad_3_3_fu_120; +wire [15:0] quad_3_10_fu_449_p3; +reg [15:0] quad_3_4_fu_124; +wire [15:0] quad_3_7_fu_425_p3; +wire [15:0] grp_fu_221_p1; +wire [15:0] grp_fu_225_p1; +wire [15:0] grp_fu_229_p1; +wire [9:0] tmp_fu_233_p3; +wire [6:0] tmp_s_fu_245_p3; +wire [10:0] zext_ln109_fu_241_p1; +wire [10:0] zext_ln109_1_fu_253_p1; +wire [10:0] sub_ln109_fu_257_p2; +wire [11:0] sub_ln109_cast_fu_263_p1; +wire [11:0] zext_ln109_2_fu_267_p1; +wire [0:0] icmp_ln103_fu_299_p2; +wire [15:0] trunc_ln95_fu_327_p1; +wire [15:0] data_V_fu_376_p1; +wire [0:0] p_Result_s_fu_379_p3; +wire [0:0] icmp_ln99_fu_394_p2; +wire [15:0] quad_0_fu_387_p3; +wire [0:0] icmp_ln99_1_fu_407_p2; +wire [15:0] quad_3_fu_399_p3; +wire [0:0] icmp_ln99_2_fu_420_p2; +wire [15:0] quad_3_6_fu_412_p3; +wire [15:0] quad_3_8_fu_433_p3; +wire [15:0] quad_3_9_fu_441_p3; +wire [15:0] quad_3_11_fu_457_p3; +wire [14:0] tmp_17_fu_501_p3; +wire [15:0] bitcast_ln109_3_fu_524_p1; +wire [15:0] bitcast_ln109_2_fu_520_p1; +wire [15:0] bitcast_ln109_1_fu_516_p1; +wire [15:0] bitcast_ln109_fu_512_p1; +wire ap_CS_fsm_state25; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +#0 ap_enable_reg_pp0_iter8 = 1'b0; +#0 ap_enable_reg_pp0_iter9 = 1'b0; +#0 ap_enable_reg_pp0_iter10 = 1'b0; +#0 ap_enable_reg_pp0_iter11 = 1'b0; +#0 ap_enable_reg_pp0_iter12 = 1'b0; +#0 ap_enable_reg_pp0_iter13 = 1'b0; +#0 ap_enable_reg_pp0_iter14 = 1'b0; +#0 ap_enable_reg_pp0_iter15 = 1'b0; +#0 ap_enable_reg_pp0_iter16 = 1'b0; +#0 ap_enable_reg_pp0_iter17 = 1'b0; +#0 ap_enable_reg_pp0_iter18 = 1'b0; +#0 ap_enable_reg_pp0_iter19 = 1'b0; +#0 ap_enable_reg_pp0_iter20 = 1'b0; +#0 ap_enable_reg_pp0_iter21 = 1'b0; +#0 ap_enable_reg_pp0_iter22 = 1'b0; +end + +td_fused_top_tdf7_l2_writeOutputs_149_running_sums #( + .DataWidth( 16 ), + .AddressRange( 32 ), + .AddressWidth( 5 )) +running_sums_U( + .reset(ap_rst), + .clk(ap_clk), + .address0(running_sums_addr_reg_595_pp0_iter6_reg), + .ce0(running_sums_ce0), + .we0(running_sums_we0), + .d0(running_sums_d0), + .address1(running_sums_address1), + .ce1(running_sums_ce1), + .q1(running_sums_q1) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U441( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(running_sums_load_reg_622), + .din1(val_reg_617), + .dout(grp_fu_217_p2) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U442( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(normalized_reg_663), + .din1(grp_fu_221_p1), + .dout(grp_fu_221_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U443( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_reg_632), + .din1(grp_fu_225_p1), + .dout(grp_fu_225_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U444( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_653), + .din1(grp_fu_229_p1), + .dout(grp_fu_229_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter10 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter11 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter12 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter13 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter14 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter15 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter16 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter17 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter18 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter19 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter20 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter21 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21; + end else if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter22 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter8 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter9 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_283_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ochan_reg_206 <= add_ln86_fu_277_p2; + end else if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ochan_reg_206 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + add_ln109_reg_571 <= add_ln109_fu_271_p2; + write4_read_reg_565 <= write4_dout; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_283_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + and_ln103_reg_608 <= and_ln103_fu_305_p2; + running_sums_addr_reg_595 <= zext_ln86_fu_289_p1; + trunc_ln99_reg_601 <= trunc_ln99_fu_295_p1; + zext_ln86_reg_585[5 : 0] <= zext_ln86_fu_289_p1[5 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + and_ln103_reg_608_pp0_iter10_reg <= and_ln103_reg_608_pp0_iter9_reg; + and_ln103_reg_608_pp0_iter11_reg <= and_ln103_reg_608_pp0_iter10_reg; + and_ln103_reg_608_pp0_iter12_reg <= and_ln103_reg_608_pp0_iter11_reg; + and_ln103_reg_608_pp0_iter13_reg <= and_ln103_reg_608_pp0_iter12_reg; + and_ln103_reg_608_pp0_iter14_reg <= and_ln103_reg_608_pp0_iter13_reg; + and_ln103_reg_608_pp0_iter15_reg <= and_ln103_reg_608_pp0_iter14_reg; + and_ln103_reg_608_pp0_iter16_reg <= and_ln103_reg_608_pp0_iter15_reg; + and_ln103_reg_608_pp0_iter17_reg <= and_ln103_reg_608_pp0_iter16_reg; + and_ln103_reg_608_pp0_iter18_reg <= and_ln103_reg_608_pp0_iter17_reg; + and_ln103_reg_608_pp0_iter19_reg <= and_ln103_reg_608_pp0_iter18_reg; + and_ln103_reg_608_pp0_iter20_reg <= and_ln103_reg_608_pp0_iter19_reg; + and_ln103_reg_608_pp0_iter2_reg <= and_ln103_reg_608_pp0_iter1_reg; + and_ln103_reg_608_pp0_iter3_reg <= and_ln103_reg_608_pp0_iter2_reg; + and_ln103_reg_608_pp0_iter4_reg <= and_ln103_reg_608_pp0_iter3_reg; + and_ln103_reg_608_pp0_iter5_reg <= and_ln103_reg_608_pp0_iter4_reg; + and_ln103_reg_608_pp0_iter6_reg <= and_ln103_reg_608_pp0_iter5_reg; + and_ln103_reg_608_pp0_iter7_reg <= and_ln103_reg_608_pp0_iter6_reg; + and_ln103_reg_608_pp0_iter8_reg <= and_ln103_reg_608_pp0_iter7_reg; + and_ln103_reg_608_pp0_iter9_reg <= and_ln103_reg_608_pp0_iter8_reg; + biased_reg_673 <= grp_fu_221_p2; + lshr_ln_reg_612_pp0_iter10_reg <= lshr_ln_reg_612_pp0_iter9_reg; + lshr_ln_reg_612_pp0_iter11_reg <= lshr_ln_reg_612_pp0_iter10_reg; + lshr_ln_reg_612_pp0_iter12_reg <= lshr_ln_reg_612_pp0_iter11_reg; + lshr_ln_reg_612_pp0_iter13_reg <= lshr_ln_reg_612_pp0_iter12_reg; + lshr_ln_reg_612_pp0_iter14_reg <= lshr_ln_reg_612_pp0_iter13_reg; + lshr_ln_reg_612_pp0_iter15_reg <= lshr_ln_reg_612_pp0_iter14_reg; + lshr_ln_reg_612_pp0_iter16_reg <= lshr_ln_reg_612_pp0_iter15_reg; + lshr_ln_reg_612_pp0_iter17_reg <= lshr_ln_reg_612_pp0_iter16_reg; + lshr_ln_reg_612_pp0_iter18_reg <= lshr_ln_reg_612_pp0_iter17_reg; + lshr_ln_reg_612_pp0_iter19_reg <= lshr_ln_reg_612_pp0_iter18_reg; + lshr_ln_reg_612_pp0_iter20_reg <= lshr_ln_reg_612_pp0_iter19_reg; + lshr_ln_reg_612_pp0_iter2_reg <= lshr_ln_reg_612_pp0_iter1_reg; + lshr_ln_reg_612_pp0_iter3_reg <= lshr_ln_reg_612_pp0_iter2_reg; + lshr_ln_reg_612_pp0_iter4_reg <= lshr_ln_reg_612_pp0_iter3_reg; + lshr_ln_reg_612_pp0_iter5_reg <= lshr_ln_reg_612_pp0_iter4_reg; + lshr_ln_reg_612_pp0_iter6_reg <= lshr_ln_reg_612_pp0_iter5_reg; + lshr_ln_reg_612_pp0_iter7_reg <= lshr_ln_reg_612_pp0_iter6_reg; + lshr_ln_reg_612_pp0_iter8_reg <= lshr_ln_reg_612_pp0_iter7_reg; + lshr_ln_reg_612_pp0_iter9_reg <= lshr_ln_reg_612_pp0_iter8_reg; + normalized_reg_663 <= grp_fu_229_p2; + running_sums_addr_reg_595_pp0_iter2_reg <= running_sums_addr_reg_595_pp0_iter1_reg; + running_sums_addr_reg_595_pp0_iter3_reg <= running_sums_addr_reg_595_pp0_iter2_reg; + running_sums_addr_reg_595_pp0_iter4_reg <= running_sums_addr_reg_595_pp0_iter3_reg; + running_sums_addr_reg_595_pp0_iter5_reg <= running_sums_addr_reg_595_pp0_iter4_reg; + running_sums_addr_reg_595_pp0_iter6_reg <= running_sums_addr_reg_595_pp0_iter5_reg; + sub_i_i_i_reg_653 <= grp_fu_225_p2; + sum_reg_632 <= grp_fu_217_p2; + tmp_20_i_i_reg_643 <= {{l2_adjustments_q0[31:16]}}; + tmp_20_i_i_reg_643_pp0_iter10_reg <= tmp_20_i_i_reg_643_pp0_iter9_reg; + tmp_20_i_i_reg_643_pp0_iter11_reg <= tmp_20_i_i_reg_643_pp0_iter10_reg; + tmp_20_i_i_reg_643_pp0_iter8_reg <= tmp_20_i_i_reg_643; + tmp_20_i_i_reg_643_pp0_iter9_reg <= tmp_20_i_i_reg_643_pp0_iter8_reg; + tmp_21_i_i_reg_648 <= {{l2_adjustments_q0[47:32]}}; + tmp_21_i_i_reg_648_pp0_iter10_reg <= tmp_21_i_i_reg_648_pp0_iter9_reg; + tmp_21_i_i_reg_648_pp0_iter11_reg <= tmp_21_i_i_reg_648_pp0_iter10_reg; + tmp_21_i_i_reg_648_pp0_iter12_reg <= tmp_21_i_i_reg_648_pp0_iter11_reg; + tmp_21_i_i_reg_648_pp0_iter13_reg <= tmp_21_i_i_reg_648_pp0_iter12_reg; + tmp_21_i_i_reg_648_pp0_iter14_reg <= tmp_21_i_i_reg_648_pp0_iter13_reg; + tmp_21_i_i_reg_648_pp0_iter15_reg <= tmp_21_i_i_reg_648_pp0_iter14_reg; + tmp_21_i_i_reg_648_pp0_iter8_reg <= tmp_21_i_i_reg_648; + tmp_21_i_i_reg_648_pp0_iter9_reg <= tmp_21_i_i_reg_648_pp0_iter8_reg; + trunc_ln99_reg_601_pp0_iter10_reg <= trunc_ln99_reg_601_pp0_iter9_reg; + trunc_ln99_reg_601_pp0_iter11_reg <= trunc_ln99_reg_601_pp0_iter10_reg; + trunc_ln99_reg_601_pp0_iter12_reg <= trunc_ln99_reg_601_pp0_iter11_reg; + trunc_ln99_reg_601_pp0_iter13_reg <= trunc_ln99_reg_601_pp0_iter12_reg; + trunc_ln99_reg_601_pp0_iter14_reg <= trunc_ln99_reg_601_pp0_iter13_reg; + trunc_ln99_reg_601_pp0_iter15_reg <= trunc_ln99_reg_601_pp0_iter14_reg; + trunc_ln99_reg_601_pp0_iter16_reg <= trunc_ln99_reg_601_pp0_iter15_reg; + trunc_ln99_reg_601_pp0_iter17_reg <= trunc_ln99_reg_601_pp0_iter16_reg; + trunc_ln99_reg_601_pp0_iter18_reg <= trunc_ln99_reg_601_pp0_iter17_reg; + trunc_ln99_reg_601_pp0_iter19_reg <= trunc_ln99_reg_601_pp0_iter18_reg; + trunc_ln99_reg_601_pp0_iter20_reg <= trunc_ln99_reg_601_pp0_iter19_reg; + trunc_ln99_reg_601_pp0_iter2_reg <= trunc_ln99_reg_601_pp0_iter1_reg; + trunc_ln99_reg_601_pp0_iter3_reg <= trunc_ln99_reg_601_pp0_iter2_reg; + trunc_ln99_reg_601_pp0_iter4_reg <= trunc_ln99_reg_601_pp0_iter3_reg; + trunc_ln99_reg_601_pp0_iter5_reg <= trunc_ln99_reg_601_pp0_iter4_reg; + trunc_ln99_reg_601_pp0_iter6_reg <= trunc_ln99_reg_601_pp0_iter5_reg; + trunc_ln99_reg_601_pp0_iter7_reg <= trunc_ln99_reg_601_pp0_iter6_reg; + trunc_ln99_reg_601_pp0_iter8_reg <= trunc_ln99_reg_601_pp0_iter7_reg; + trunc_ln99_reg_601_pp0_iter9_reg <= trunc_ln99_reg_601_pp0_iter8_reg; + zext_ln86_reg_585_pp0_iter2_reg[5 : 0] <= zext_ln86_reg_585_pp0_iter1_reg[5 : 0]; + zext_ln86_reg_585_pp0_iter3_reg[5 : 0] <= zext_ln86_reg_585_pp0_iter2_reg[5 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + and_ln103_reg_608_pp0_iter1_reg <= and_ln103_reg_608; + lshr_ln_reg_612_pp0_iter1_reg <= lshr_ln_reg_612; + running_sums_addr_reg_595_pp0_iter1_reg <= running_sums_addr_reg_595; + trunc_ln99_reg_601_pp0_iter1_reg <= trunc_ln99_reg_601; + val_reg_617 <= l2_partial_sums_q0; + zext_ln86_reg_585_pp0_iter1_reg[5 : 0] <= zext_ln86_reg_585[5 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((1'd1 == and_ln103_fu_305_p2) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln86_fu_283_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + lshr_ln_reg_612 <= {{ochan_reg_206[4:2]}}; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + quad_3_1_fu_112 <= quad_3_13_fu_473_p3; + quad_3_2_fu_116 <= quad_3_12_fu_465_p3; + quad_3_3_fu_120 <= quad_3_10_fu_449_p3; + quad_3_4_fu_124 <= quad_3_7_fu_425_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_load_reg_622 <= running_sums_q1; + end +end + +always @ (*) begin + if ((icmp_ln86_fu_283_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter22 == 1'b0) & (ap_enable_reg_pp0_iter21 == 1'b0) & (ap_enable_reg_pp0_iter20 == 1'b0) & (ap_enable_reg_pp0_iter19 == 1'b0) & (ap_enable_reg_pp0_iter18 == 1'b0) & (ap_enable_reg_pp0_iter17 == 1'b0) & (ap_enable_reg_pp0_iter16 == 1'b0) & (ap_enable_reg_pp0_iter15 == 1'b0) & (ap_enable_reg_pp0_iter14 == 1'b0) & (ap_enable_reg_pp0_iter13 == 1'b0) & (ap_enable_reg_pp0_iter12 == 1'b0) & (ap_enable_reg_pp0_iter11 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state25)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter6 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter5 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter4 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + l2_adjustments_ce0 = 1'b1; + end else begin + l2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + l2_partial_sums_ce0 = 1'b1; + end else begin + l2_partial_sums_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter22 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)) | ((ap_enable_reg_pp0_iter21 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter21 == 1'b1) & (1'd1 == and_ln103_reg_608_pp0_iter20_reg) & (1'b0 == ap_block_pp0_stage0_11001))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_ce0 = 1'b1; + end else begin + running_sums_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_ce1 = 1'b1; + end else begin + running_sums_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin + running_sums_we0 = 1'b1; + end else begin + running_sums_we0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write4_blk_n = write4_empty_n; + end else begin + write4_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + write4_read = 1'b1; + end else begin + write4_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln86_fu_283_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((ap_enable_reg_pp0_iter22 == 1'b1) & (ap_enable_reg_pp0_iter21 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln86_fu_283_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter22 == 1'b1) & (ap_enable_reg_pp0_iter21 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_state25; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state25 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln109_fu_271_p2 = ((sub_ln109_cast_fu_263_p1) + (zext_ln109_2_fu_267_p1)); + +assign add_ln86_fu_277_p2 = (ochan_reg_206 + 6'd1); + +assign and_ln103_fu_305_p2 = (write4_read_reg_565 & icmp_ln103_fu_299_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state25 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (write4_empty_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state10_pp0_stage0_iter8 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage0_iter9 = ~(1'b1 == 1'b1); + +assign ap_block_state12_pp0_stage0_iter10 = ~(1'b1 == 1'b1); + +assign ap_block_state13_pp0_stage0_iter11 = ~(1'b1 == 1'b1); + +assign ap_block_state14_pp0_stage0_iter12 = ~(1'b1 == 1'b1); + +assign ap_block_state15_pp0_stage0_iter13 = ~(1'b1 == 1'b1); + +assign ap_block_state16_pp0_stage0_iter14 = ~(1'b1 == 1'b1); + +assign ap_block_state17_pp0_stage0_iter15 = ~(1'b1 == 1'b1); + +assign ap_block_state18_pp0_stage0_iter16 = ~(1'b1 == 1'b1); + +assign ap_block_state19_pp0_stage0_iter17 = ~(1'b1 == 1'b1); + +assign ap_block_state20_pp0_stage0_iter18 = ~(1'b1 == 1'b1); + +assign ap_block_state21_pp0_stage0_iter19 = ~(1'b1 == 1'b1); + +assign ap_block_state22_pp0_stage0_iter20 = ~(1'b1 == 1'b1); + +assign ap_block_state23_pp0_stage0_iter21 = ~(1'b1 == 1'b1); + +assign ap_block_state24_pp0_stage0_iter22 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln109_1_fu_516_p1 = quad_3_12_fu_465_p3; + +assign bitcast_ln109_2_fu_520_p1 = quad_3_10_fu_449_p3; + +assign bitcast_ln109_3_fu_524_p1 = quad_3_7_fu_425_p3; + +assign bitcast_ln109_fu_512_p1 = quad_3_13_fu_473_p3; + +assign data_V_fu_376_p1 = biased_reg_673; + +assign grp_fu_221_p1 = tmp_21_i_i_reg_648_pp0_iter15_reg; + +assign grp_fu_225_p1 = trunc_ln95_fu_327_p1; + +assign grp_fu_229_p1 = tmp_20_i_i_reg_643_pp0_iter11_reg; + +assign icmp_ln103_fu_299_p2 = ((trunc_ln99_fu_295_p1 == 2'd3) ? 1'b1 : 1'b0); + +assign icmp_ln86_fu_283_p2 = ((ochan_reg_206 == 6'd32) ? 1'b1 : 1'b0); + +assign icmp_ln99_1_fu_407_p2 = ((trunc_ln99_reg_601_pp0_iter20_reg == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln99_2_fu_420_p2 = ((trunc_ln99_reg_601_pp0_iter20_reg == 2'd0) ? 1'b1 : 1'b0); + +assign icmp_ln99_fu_394_p2 = ((trunc_ln99_reg_601_pp0_iter20_reg == 2'd2) ? 1'b1 : 1'b0); + +assign l2_adjustments_address0 = zext_ln86_reg_585_pp0_iter3_reg; + +assign l2_partial_sums_address0 = zext_ln86_fu_289_p1; + +assign out_data_address1 = sext_ln109_fu_507_p1; + +assign out_data_d1 = {{{{bitcast_ln109_3_fu_524_p1}, {bitcast_ln109_2_fu_520_p1}}, {bitcast_ln109_1_fu_516_p1}}, {bitcast_ln109_fu_512_p1}}; + +assign p_Result_s_fu_379_p3 = data_V_fu_376_p1[32'd15]; + +assign quad_0_fu_387_p3 = ((p_Result_s_fu_379_p3[0:0] == 1'b1) ? 16'd0 : biased_reg_673); + +assign quad_3_10_fu_449_p3 = ((icmp_ln99_2_fu_420_p2[0:0] == 1'b1) ? quad_3_3_fu_120 : quad_3_9_fu_441_p3); + +assign quad_3_11_fu_457_p3 = ((icmp_ln99_1_fu_407_p2[0:0] == 1'b1) ? quad_0_fu_387_p3 : quad_3_2_fu_116); + +assign quad_3_12_fu_465_p3 = ((icmp_ln99_2_fu_420_p2[0:0] == 1'b1) ? quad_3_2_fu_116 : quad_3_11_fu_457_p3); + +assign quad_3_13_fu_473_p3 = ((icmp_ln99_2_fu_420_p2[0:0] == 1'b1) ? quad_0_fu_387_p3 : quad_3_1_fu_112); + +assign quad_3_6_fu_412_p3 = ((icmp_ln99_1_fu_407_p2[0:0] == 1'b1) ? quad_3_4_fu_124 : quad_3_fu_399_p3); + +assign quad_3_7_fu_425_p3 = ((icmp_ln99_2_fu_420_p2[0:0] == 1'b1) ? quad_3_4_fu_124 : quad_3_6_fu_412_p3); + +assign quad_3_8_fu_433_p3 = ((icmp_ln99_fu_394_p2[0:0] == 1'b1) ? quad_0_fu_387_p3 : quad_3_3_fu_120); + +assign quad_3_9_fu_441_p3 = ((icmp_ln99_1_fu_407_p2[0:0] == 1'b1) ? quad_3_3_fu_120 : quad_3_8_fu_433_p3); + +assign quad_3_fu_399_p3 = ((icmp_ln99_fu_394_p2[0:0] == 1'b1) ? quad_3_4_fu_124 : quad_0_fu_387_p3); + +assign running_sums_address1 = zext_ln86_fu_289_p1; + +assign running_sums_d0 = ((write4_read_reg_565[0:0] == 1'b1) ? 16'd0 : sum_reg_632); + +assign sext_ln109_fu_507_p1 = (tmp_17_fu_501_p3); + +assign sub_ln109_cast_fu_263_p1 = (sub_ln109_fu_257_p2); + +assign sub_ln109_fu_257_p2 = (zext_ln109_fu_241_p1 - zext_ln109_1_fu_253_p1); + +assign tmp_17_fu_501_p3 = {{add_ln109_reg_571}, {lshr_ln_reg_612_pp0_iter20_reg}}; + +assign tmp_fu_233_p3 = {{indices_01_dout}, {5'd0}}; + +assign tmp_s_fu_245_p3 = {{indices_01_dout}, {2'd0}}; + +assign trunc_ln95_fu_327_p1 = l2_adjustments_q0[15:0]; + +assign trunc_ln99_fu_295_p1 = ochan_reg_206[1:0]; + +assign zext_ln109_1_fu_253_p1 = tmp_s_fu_245_p3; + +assign zext_ln109_2_fu_267_p1 = indices_12_dout; + +assign zext_ln109_fu_241_p1 = tmp_fu_233_p3; + +assign zext_ln86_fu_289_p1 = ochan_reg_206; + +always @ (posedge ap_clk) begin + zext_ln86_reg_585[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_585_pp0_iter1_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_585_pp0_iter2_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; + zext_ln86_reg_585_pp0_iter3_reg[63:6] <= 58'b0000000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf7_l2_writeOutputs_149 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_readFilters52 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_we0, + weight_vecs_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state7 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [16:0] filter_data_address0; +output filter_data_ce0; +input [15:0] filter_data_q0; +input [7:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [8:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +output weight_vecs_0_we0; +output [15:0] weight_vecs_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg indices_23_read; +reg weight_vecs_0_ce0; +reg weight_vecs_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [8:0] indvar_flatten13_reg_123; +reg [1:0] ii_reg_134; +reg [7:0] indvar_flatten_reg_145; +reg [1:0] jj_reg_156; +reg [5:0] kk_reg_167; +wire [11:0] sext_ln47_fu_200_p1; +reg [11:0] sext_ln47_reg_408; +wire [8:0] add_ln47_2_fu_204_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln47_fu_210_p2; +reg [0:0] icmp_ln47_reg_418; +reg [0:0] icmp_ln47_reg_418_pp0_iter1_reg; +reg [0:0] icmp_ln47_reg_418_pp0_iter2_reg; +reg [0:0] icmp_ln47_reg_418_pp0_iter3_reg; +wire [0:0] icmp_ln48_fu_222_p2; +reg [0:0] icmp_ln48_reg_422; +wire [1:0] select_ln47_2_fu_228_p3; +reg [1:0] select_ln47_2_reg_429; +wire [7:0] select_ln48_4_fu_242_p3; +wire [1:0] select_ln48_3_fu_329_p3; +reg [1:0] select_ln48_3_reg_442; +reg ap_enable_reg_pp0_iter1; +wire [8:0] add_ln55_8_fu_392_p2; +reg [8:0] add_ln55_8_reg_452; +reg [8:0] add_ln55_8_reg_452_pp0_iter2_reg; +reg [8:0] add_ln55_8_reg_452_pp0_iter3_reg; +wire [5:0] add_ln49_fu_398_p2; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg [1:0] ap_phi_mux_ii_phi_fu_138_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_160_p4; +wire [63:0] zext_ln55_18_fu_387_p1; +wire [63:0] zext_ln55_19_fu_404_p1; +wire [9:0] tmp_fu_182_p3; +wire [10:0] zext_ln55_11_fu_190_p1; +wire [10:0] zext_ln55_fu_178_p1; +wire [10:0] sub_ln55_fu_194_p2; +wire [1:0] add_ln47_fu_216_p2; +wire [7:0] add_ln48_2_fu_236_p2; +wire [11:0] zext_ln55_13_fu_260_p1; +wire [11:0] add_ln55_fu_263_p2; +wire [11:0] shl_ln55_fu_268_p2; +wire [3:0] tmp_s_fu_280_p3; +wire [3:0] zext_ln55_12_fu_257_p1; +wire [0:0] icmp_ln49_fu_298_p2; +wire [0:0] xor_ln47_fu_293_p2; +wire [1:0] select_ln47_fu_250_p3; +wire [0:0] and_ln47_fu_304_p2; +wire [0:0] or_ln48_fu_316_p2; +wire [1:0] add_ln48_fu_310_p2; +wire [11:0] sub_ln55_3_fu_274_p2; +wire [11:0] zext_ln55_15_fu_341_p1; +wire [11:0] add_ln55_5_fu_345_p2; +wire [3:0] sub_ln55_4_fu_287_p2; +wire [3:0] zext_ln55_14_fu_337_p1; +wire [3:0] add_ln55_6_fu_359_p2; +wire [5:0] select_ln48_fu_321_p3; +wire [16:0] tmp_41_cast_fu_351_p3; +wire [16:0] zext_ln55_17_fu_377_p1; +wire [16:0] add_ln55_7_fu_381_p2; +wire [8:0] tmp_43_cast_fu_365_p3; +wire [8:0] zext_ln55_16_fu_373_p1; +wire ap_CS_fsm_state7; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ii_reg_134 <= select_ln47_2_reg_429; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_134 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten13_reg_123 <= add_ln47_2_fu_204_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_123 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_145 <= select_ln48_4_fu_242_p3; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_145 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_418_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + jj_reg_156 <= select_ln48_3_reg_442; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_156 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_reg_167 <= add_ln49_fu_398_p2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_167 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln55_8_reg_452 <= add_ln55_8_fu_392_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln55_8_reg_452_pp0_iter2_reg <= add_ln55_8_reg_452; + add_ln55_8_reg_452_pp0_iter3_reg <= add_ln55_8_reg_452_pp0_iter2_reg; + icmp_ln47_reg_418_pp0_iter2_reg <= icmp_ln47_reg_418_pp0_iter1_reg; + icmp_ln47_reg_418_pp0_iter3_reg <= icmp_ln47_reg_418_pp0_iter2_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln47_reg_418 <= icmp_ln47_fu_210_p2; + icmp_ln47_reg_418_pp0_iter1_reg <= icmp_ln47_reg_418; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln48_reg_422 <= icmp_ln48_fu_222_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln47_2_reg_429 <= select_ln47_2_fu_228_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln48_3_reg_442 <= select_ln48_3_fu_329_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sext_ln47_reg_408 <= sext_ln47_fu_200_p1; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln47_fu_210_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_138_p4 = select_ln47_2_reg_429; + end else begin + ap_phi_mux_ii_phi_fu_138_p4 = ii_reg_134; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_418_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_160_p4 = select_ln48_3_reg_442; + end else begin + ap_phi_mux_jj_phi_fu_160_p4 = jj_reg_156; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_418_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + weight_vecs_0_we0 = 1'b1; + end else begin + weight_vecs_0_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln47_2_fu_204_p2 = (indvar_flatten13_reg_123 + 9'd1); + +assign add_ln47_fu_216_p2 = (ap_phi_mux_ii_phi_fu_138_p4 + 2'd1); + +assign add_ln48_2_fu_236_p2 = (indvar_flatten_reg_145 + 8'd1); + +assign add_ln48_fu_310_p2 = (select_ln47_fu_250_p3 + 2'd1); + +assign add_ln49_fu_398_p2 = (select_ln48_fu_321_p3 + 6'd1); + +assign add_ln55_5_fu_345_p2 = (sub_ln55_3_fu_274_p2 + zext_ln55_15_fu_341_p1); + +assign add_ln55_6_fu_359_p2 = (sub_ln55_4_fu_287_p2 + zext_ln55_14_fu_337_p1); + +assign add_ln55_7_fu_381_p2 = (tmp_41_cast_fu_351_p3 + zext_ln55_17_fu_377_p1); + +assign add_ln55_8_fu_392_p2 = (tmp_43_cast_fu_365_p3 + zext_ln55_16_fu_373_p1); + +assign add_ln55_fu_263_p2 = ((sext_ln47_reg_408) + (zext_ln55_13_fu_260_p1)); + +assign and_ln47_fu_304_p2 = (xor_ln47_fu_293_p2 & icmp_ln49_fu_298_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_address0 = zext_ln55_18_fu_387_p1; + +assign icmp_ln47_fu_210_p2 = ((indvar_flatten13_reg_123 == 9'd288) ? 1'b1 : 1'b0); + +assign icmp_ln48_fu_222_p2 = ((indvar_flatten_reg_145 == 8'd96) ? 1'b1 : 1'b0); + +assign icmp_ln49_fu_298_p2 = ((kk_reg_167 == 6'd32) ? 1'b1 : 1'b0); + +assign or_ln48_fu_316_p2 = (icmp_ln48_reg_422 | and_ln47_fu_304_p2); + +assign select_ln47_2_fu_228_p3 = ((icmp_ln48_fu_222_p2[0:0] == 1'b1) ? add_ln47_fu_216_p2 : ap_phi_mux_ii_phi_fu_138_p4); + +assign select_ln47_fu_250_p3 = ((icmp_ln48_reg_422[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_160_p4); + +assign select_ln48_3_fu_329_p3 = ((and_ln47_fu_304_p2[0:0] == 1'b1) ? add_ln48_fu_310_p2 : select_ln47_fu_250_p3); + +assign select_ln48_4_fu_242_p3 = ((icmp_ln48_fu_222_p2[0:0] == 1'b1) ? 8'd1 : add_ln48_2_fu_236_p2); + +assign select_ln48_fu_321_p3 = ((or_ln48_fu_316_p2[0:0] == 1'b1) ? 6'd0 : kk_reg_167); + +assign sext_ln47_fu_200_p1 = (sub_ln55_fu_194_p2); + +assign shl_ln55_fu_268_p2 = add_ln55_fu_263_p2 << 12'd2; + +assign sub_ln55_3_fu_274_p2 = (shl_ln55_fu_268_p2 - add_ln55_fu_263_p2); + +assign sub_ln55_4_fu_287_p2 = (tmp_s_fu_280_p3 - zext_ln55_12_fu_257_p1); + +assign sub_ln55_fu_194_p2 = (zext_ln55_11_fu_190_p1 - zext_ln55_fu_178_p1); + +assign tmp_41_cast_fu_351_p3 = {{add_ln55_5_fu_345_p2}, {5'd0}}; + +assign tmp_43_cast_fu_365_p3 = {{add_ln55_6_fu_359_p2}, {5'd0}}; + +assign tmp_fu_182_p3 = {{indices_23_dout}, {2'd0}}; + +assign tmp_s_fu_280_p3 = {{select_ln47_2_reg_429}, {2'd0}}; + +assign weight_vecs_0_address0 = zext_ln55_19_fu_404_p1; + +assign weight_vecs_0_d0 = filter_data_q0; + +assign xor_ln47_fu_293_p2 = (icmp_ln48_reg_422 ^ 1'd1); + +assign zext_ln55_11_fu_190_p1 = tmp_fu_182_p3; + +assign zext_ln55_12_fu_257_p1 = select_ln47_2_reg_429; + +assign zext_ln55_13_fu_260_p1 = select_ln47_2_reg_429; + +assign zext_ln55_14_fu_337_p1 = select_ln48_3_fu_329_p3; + +assign zext_ln55_15_fu_341_p1 = select_ln48_3_fu_329_p3; + +assign zext_ln55_16_fu_373_p1 = select_ln48_fu_321_p3; + +assign zext_ln55_17_fu_377_p1 = select_ln48_fu_321_p3; + +assign zext_ln55_18_fu_387_p1 = add_ln55_7_fu_381_p2; + +assign zext_ln55_19_fu_404_p1 = add_ln55_8_reg_452_pp0_iter3_reg; + +assign zext_ln55_fu_178_p1 = indices_23_dout; + +endmodule //td_fused_top_tdf7_readFilters52 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf7_readInputs53 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_we0, + ifmap_vec_d0, + ifmap_vec_address1, + ifmap_vec_ce1, + ifmap_vec_we1, + ifmap_vec_d1, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 5'd1; +parameter ap_ST_fsm_state2 = 5'd2; +parameter ap_ST_fsm_pp0_stage0 = 5'd4; +parameter ap_ST_fsm_pp0_stage1 = 5'd8; +parameter ap_ST_fsm_state9 = 5'd16; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [12:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [8:0] ifmap_vec_address0; +output ifmap_vec_ce0; +output ifmap_vec_we0; +output [15:0] ifmap_vec_d0; +output [8:0] ifmap_vec_address1; +output ifmap_vec_ce1; +output ifmap_vec_we1; +output [15:0] ifmap_vec_d1; +output [4:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [9:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg[8:0] ifmap_vec_address0; +reg ifmap_vec_ce0; +reg ifmap_vec_we0; +reg[15:0] ifmap_vec_d0; +reg[8:0] ifmap_vec_address1; +reg ifmap_vec_ce1; +reg ifmap_vec_we1; +reg[15:0] ifmap_vec_d1; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [4:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [6:0] indvar_flatten47_reg_222; +reg [1:0] ii_reg_234; +reg [5:0] indvar_flatten_reg_246; +reg [1:0] jj_reg_257; +reg [5:0] kk_0_i_i_reg_269; +reg [15:0] indices_01_read_reg_957; +wire [4:0] trunc_ln250_fu_280_p1; +reg [4:0] trunc_ln250_reg_962; +reg [15:0] indices_12_read_reg_967; +wire [9:0] empty_fu_285_p1; +reg [9:0] empty_reg_972; +wire [17:0] p_cast_i_i_fu_302_p1; +reg [17:0] p_cast_i_i_reg_979; +wire ap_CS_fsm_state2; +wire [17:0] sext_ln22_fu_312_p1; +reg [17:0] sext_ln22_reg_985; +wire [4:0] p_cast_fu_316_p2; +reg [4:0] p_cast_reg_991; +wire [0:0] or_ln23_6_fu_335_p2; +reg [0:0] or_ln23_6_reg_997; +wire [9:0] p_mid137_fu_341_p2; +reg [9:0] p_mid137_reg_1002; +wire [4:0] p_cast5_i_i_fu_359_p2; +reg [4:0] p_cast5_i_i_reg_1007; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state5_pp0_stage0_iter1; +wire ap_block_state7_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [0:0] is_padding_fu_399_p2; +reg [0:0] is_padding_reg_1013; +wire [0:0] icmp_ln19_fu_405_p2; +reg [0:0] icmp_ln19_reg_1020; +reg [0:0] icmp_ln19_reg_1020_pp0_iter1_reg; +reg [0:0] icmp_ln19_reg_1020_pp0_iter2_reg; +wire [1:0] add_ln19_fu_411_p2; +reg [1:0] add_ln19_reg_1024; +wire [0:0] icmp_ln20_fu_417_p2; +reg [0:0] icmp_ln20_reg_1029; +wire [1:0] select_ln19_fu_423_p3; +reg [1:0] select_ln19_reg_1041; +wire [4:0] p_cast5_i_i_mid1_fu_444_p2; +reg [4:0] p_cast5_i_i_mid1_reg_1046; +wire [0:0] or_ln23_8_fu_463_p2; +reg [0:0] or_ln23_8_reg_1052; +wire [1:0] add_ln20_fu_468_p2; +reg [1:0] add_ln20_reg_1059; +wire [0:0] or_ln23_10_fu_503_p2; +reg [0:0] or_ln23_10_reg_1065; +wire [5:0] add_ln20_2_fu_509_p2; +reg [5:0] add_ln20_2_reg_1072; +wire [6:0] add_ln19_2_fu_515_p2; +reg [6:0] add_ln19_2_reg_1077; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state4_pp0_stage1_iter0; +wire ap_block_state6_pp0_stage1_iter1; +wire ap_block_state8_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +wire [1:0] select_ln19_7_fu_553_p3; +reg [1:0] select_ln19_7_reg_1082; +wire [5:0] select_ln20_fu_617_p3; +reg [5:0] select_ln20_reg_1089; +wire [1:0] select_ln20_6_fu_625_p3; +reg [1:0] select_ln20_6_reg_1095; +wire [0:0] select_ln20_7_fu_634_p3; +reg [0:0] select_ln20_7_reg_1101; +reg [0:0] select_ln20_7_reg_1101_pp0_iter1_reg; +wire [4:0] empty_73_fu_730_p1; +reg [4:0] empty_73_reg_1109; +reg [4:0] empty_73_reg_1109_pp0_iter1_reg; +wire [5:0] select_ln20_10_fu_757_p3; +reg [5:0] select_ln20_10_reg_1121; +wire [5:0] add_ln25_fu_763_p2; +reg [5:0] add_ln25_reg_1126; +reg ap_enable_reg_pp0_iter1; +wire [5:0] add_ln33_fu_795_p2; +reg [5:0] add_ln33_reg_1131; +wire [8:0] add_ln33_2_fu_816_p2; +reg [8:0] add_ln33_2_reg_1138; +wire [15:0] select_ln33_8_fu_895_p3; +reg [15:0] select_ln33_8_reg_1143; +wire [15:0] select_ln33_9_fu_916_p3; +reg [15:0] select_ln33_9_reg_1148; +wire ap_block_pp0_stage1_subdone; +reg ap_condition_pp0_exit_iter0_state4; +reg ap_enable_reg_pp0_iter2; +reg [6:0] ap_phi_mux_indvar_flatten47_phi_fu_226_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_238_p4; +reg [5:0] ap_phi_mux_indvar_flatten_phi_fu_250_p4; +reg [1:0] ap_phi_mux_jj_phi_fu_261_p4; +reg [5:0] ap_phi_mux_kk_0_i_i_phi_fu_273_p4; +wire ap_block_pp0_stage1; +wire [63:0] sext_ln32_fu_752_p1; +wire [63:0] zext_ln33_9_fu_822_p1; +wire [63:0] sext_ln33_fu_854_p1; +wire [63:0] sext_ln33_3_fu_935_p1; +wire [63:0] sext_ln33_4_fu_952_p1; +reg ap_block_state1; +wire [15:0] select_ln33_fu_834_p3; +wire [15:0] select_ln33_7_fu_873_p3; +wire [16:0] zext_ln19_fu_293_p1; +wire [16:0] empty_68_fu_296_p2; +wire [16:0] j_cast_i_i_fu_290_p1; +wire [16:0] add_ln22_fu_306_p2; +wire [0:0] tmp_9_fu_321_p3; +wire [0:0] icmp_ln24_fu_329_p2; +wire [17:0] ii_cast_i_i_fu_346_p1; +wire [4:0] ii_cast_fu_350_p1; +wire [17:0] empty_69_fu_354_p2; +wire [17:0] zext_ln20_fu_370_p1; +wire [17:0] add_ln22_2_fu_374_p2; +wire [0:0] tmp_10_fu_379_p3; +wire [0:0] icmp_ln24_2_fu_387_p2; +wire [0:0] or_ln23_fu_393_p2; +wire [0:0] empty_70_fu_364_p2; +wire [17:0] ii_cast_i_i_mid1_fu_431_p1; +wire [4:0] ii_cast_mid1_fu_435_p1; +wire [17:0] p_mid111_fu_439_p2; +wire [0:0] p_mid113_fu_449_p2; +wire [17:0] zext_ln20_2_fu_474_p1; +wire [17:0] add_ln22_3_fu_478_p2; +wire [0:0] tmp_11_fu_483_p3; +wire [0:0] icmp_ln24_3_fu_491_p2; +wire [0:0] or_ln23_9_fu_497_p2; +wire [0:0] select_ln19_9_fu_455_p3; +wire [2:0] zext_ln22_fu_521_p1; +wire [2:0] tmp1_fu_531_p2; +wire [9:0] tmp1_cast_fu_537_p1; +wire [9:0] empty_71_fu_541_p2; +wire [4:0] row_coord_int_mid131_fu_569_p3; +wire [4:0] row_coord_int_fu_525_p3; +wire [9:0] col_coord_int_mid139_fu_575_p3; +wire [9:0] col_coord_int_fu_546_p3; +wire [0:0] icmp_ln25_fu_600_p2; +wire [0:0] xor_ln19_fu_595_p2; +wire [0:0] and_ln19_fu_606_p2; +wire [0:0] or_ln20_fu_612_p2; +wire [0:0] select_ln19_10_fu_564_p3; +wire [4:0] select_ln19_8_fu_559_p3; +wire [2:0] zext_ln22_2_fu_631_p1; +wire [2:0] tmp1_mid1_fu_648_p2; +wire [9:0] tmp1_cast_mid1_fu_654_p1; +wire [9:0] p_mid1_fu_658_p2; +wire [4:0] row_coord_int_mid1_fu_641_p3; +wire [4:0] select_ln19_11_fu_581_p3; +wire [4:0] select_ln20_8_fu_670_p3; +wire [9:0] tmp_s_fu_678_p3; +wire [6:0] tmp_3_fu_690_p3; +wire [10:0] zext_ln32_fu_686_p1; +wire [10:0] zext_ln32_9_fu_698_p1; +wire [10:0] sub_ln32_fu_702_p2; +wire [9:0] col_coord_int_mid1_fu_663_p3; +wire [9:0] select_ln19_12_fu_588_p3; +wire [9:0] select_ln20_9_fu_712_p3; +wire [11:0] sext_ln20_fu_708_p1; +wire [11:0] zext_ln32_10_fu_720_p1; +wire [11:0] add_ln32_fu_724_p2; +wire [2:0] lshr_ln_fu_734_p4; +wire [14:0] tmp_12_fu_744_p3; +wire [3:0] tmp_fu_771_p3; +wire [4:0] zext_ln33_6_fu_778_p1; +wire [4:0] zext_ln33_fu_768_p1; +wire [4:0] sub_ln33_fu_782_p2; +wire [5:0] sub_ln33_cast_fu_788_p1; +wire [5:0] zext_ln33_7_fu_792_p1; +wire [3:0] trunc_ln33_fu_801_p1; +wire [8:0] tmp_30_cast_fu_805_p3; +wire [8:0] zext_ln33_8_fu_813_p1; +wire [15:0] trunc_ln32_fu_826_p1; +wire [15:0] bitcast_ln32_fu_830_p1; +wire [4:0] or_ln25_fu_842_p2; +wire [10:0] tmp_13_fu_847_p3; +wire [15:0] tmp_17_i_i_fu_859_p4; +wire [15:0] bitcast_ln32_7_fu_869_p1; +wire [15:0] tmp_18_i_i_fu_881_p4; +wire [15:0] bitcast_ln32_8_fu_891_p1; +wire [15:0] tmp_19_i_i_fu_902_p4; +wire [15:0] bitcast_ln32_9_fu_912_p1; +wire [4:0] or_ln25_5_fu_923_p2; +wire [10:0] tmp_14_fu_928_p3; +wire [4:0] or_ln25_6_fu_940_p2; +wire [10:0] tmp_15_fu_945_p3; +wire ap_CS_fsm_state9; +reg [4:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 5'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state4)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state4); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1020 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ii_reg_234 <= select_ln19_7_reg_1082; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ii_reg_234 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1020 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + indvar_flatten47_reg_222 <= add_ln19_2_reg_1077; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + indvar_flatten47_reg_222 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1020 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + indvar_flatten_reg_246 <= select_ln20_10_reg_1121; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + indvar_flatten_reg_246 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1020 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + jj_reg_257 <= select_ln20_6_reg_1095; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + jj_reg_257 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1020_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + kk_0_i_i_reg_269 <= add_ln25_reg_1126; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + kk_0_i_i_reg_269 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + add_ln19_2_reg_1077 <= add_ln19_2_fu_515_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_fu_405_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln19_reg_1024 <= add_ln19_fu_411_p2; + add_ln20_2_reg_1072 <= add_ln20_2_fu_509_p2; + add_ln20_reg_1059 <= add_ln20_fu_468_p2; + icmp_ln20_reg_1029 <= icmp_ln20_fu_417_p2; + or_ln23_10_reg_1065 <= or_ln23_10_fu_503_p2; + or_ln23_8_reg_1052 <= or_ln23_8_fu_463_p2; + p_cast5_i_i_mid1_reg_1046 <= p_cast5_i_i_mid1_fu_444_p2; + select_ln19_reg_1041 <= select_ln19_fu_423_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1020 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + add_ln25_reg_1126 <= add_ln25_fu_763_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1020_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + add_ln33_2_reg_1138 <= add_ln33_2_fu_816_p2; + add_ln33_reg_1131 <= add_ln33_fu_795_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1020 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + empty_73_reg_1109 <= empty_73_fu_730_p1; + select_ln20_7_reg_1101 <= select_ln20_7_fu_634_p3; + select_ln20_reg_1089 <= select_ln20_fu_617_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_11001))) begin + empty_73_reg_1109_pp0_iter1_reg <= empty_73_reg_1109; + select_ln20_7_reg_1101_pp0_iter1_reg <= select_ln20_7_reg_1101; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + empty_reg_972 <= empty_fu_285_p1; + indices_01_read_reg_957 <= indices_01_dout; + indices_12_read_reg_967 <= indices_12_dout; + trunc_ln250_reg_962 <= trunc_ln250_fu_280_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + icmp_ln19_reg_1020 <= icmp_ln19_fu_405_p2; + icmp_ln19_reg_1020_pp0_iter1_reg <= icmp_ln19_reg_1020; + icmp_ln19_reg_1020_pp0_iter2_reg <= icmp_ln19_reg_1020_pp0_iter1_reg; + is_padding_reg_1013 <= is_padding_fu_399_p2; + p_cast5_i_i_reg_1007 <= p_cast5_i_i_fu_359_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + or_ln23_6_reg_997 <= or_ln23_6_fu_335_p2; + p_cast_i_i_reg_979 <= p_cast_i_i_fu_302_p1; + p_cast_reg_991 <= p_cast_fu_316_p2; + p_mid137_reg_1002 <= p_mid137_fu_341_p2; + sext_ln22_reg_985 <= sext_ln22_fu_312_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln19_reg_1020 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001))) begin + select_ln19_7_reg_1082 <= select_ln19_7_fu_553_p3; + select_ln20_10_reg_1121 <= select_ln20_10_fu_757_p3; + select_ln20_6_reg_1095 <= select_ln20_6_fu_625_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_1020_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + select_ln33_8_reg_1143 <= select_ln33_8_fu_895_p3; + select_ln33_9_reg_1148 <= select_ln33_9_fu_916_p3; + end +end + +always @ (*) begin + if ((icmp_ln19_reg_1020 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1020 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_238_p4 = select_ln19_7_reg_1082; + end else begin + ap_phi_mux_ii_phi_fu_238_p4 = ii_reg_234; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1020 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_indvar_flatten47_phi_fu_226_p4 = add_ln19_2_reg_1077; + end else begin + ap_phi_mux_indvar_flatten47_phi_fu_226_p4 = indvar_flatten47_reg_222; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1020 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_indvar_flatten_phi_fu_250_p4 = select_ln20_10_reg_1121; + end else begin + ap_phi_mux_indvar_flatten_phi_fu_250_p4 = indvar_flatten_reg_246; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1020 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin + ap_phi_mux_jj_phi_fu_261_p4 = select_ln20_6_reg_1095; + end else begin + ap_phi_mux_jj_phi_fu_261_p4 = jj_reg_257; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln19_reg_1020_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1))) begin + ap_phi_mux_kk_0_i_i_phi_fu_273_p4 = add_ln25_reg_1126; + end else begin + ap_phi_mux_kk_0_i_i_phi_fu_273_p4 = kk_0_i_i_reg_269; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_address0 = sext_ln33_4_fu_952_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_address0 = sext_ln33_fu_854_p1; + end else begin + ifmap_vec_address0 = 'bx; + end + end else begin + ifmap_vec_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_address1 = sext_ln33_3_fu_935_p1; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_address1 = zext_ln33_9_fu_822_p1; + end else begin + ifmap_vec_address1 = 'bx; + end + end else begin + ifmap_vec_address1 = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_ce1 = 1'b1; + end else begin + ifmap_vec_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_d0 = select_ln33_9_reg_1148; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_d0 = select_ln33_7_fu_873_p3; + end else begin + ifmap_vec_d0 = 'bx; + end + end else begin + ifmap_vec_d0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b0 == ap_block_pp0_stage1))) begin + ifmap_vec_d1 = select_ln33_8_reg_1143; + end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0))) begin + ifmap_vec_d1 = select_ln33_fu_834_p3; + end else begin + ifmap_vec_d1 = 'bx; + end + end else begin + ifmap_vec_d1 = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1020_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_1020_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_we0 = 1'b1; + end else begin + ifmap_vec_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln19_reg_1020_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln19_reg_1020_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + ifmap_vec_we1 = 1'b1; + end else begin + ifmap_vec_we1 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001)))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln19_reg_1020 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone)) & ~((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage1_subdone)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage1_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln19_reg_1020 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone)))) begin + ap_NS_fsm = ap_ST_fsm_state9; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln19_2_fu_515_p2 = (indvar_flatten47_reg_222 + 7'd1); + +assign add_ln19_fu_411_p2 = (ap_phi_mux_ii_phi_fu_238_p4 + 2'd1); + +assign add_ln20_2_fu_509_p2 = (ap_phi_mux_indvar_flatten_phi_fu_250_p4 + 6'd1); + +assign add_ln20_fu_468_p2 = (select_ln19_fu_423_p3 + 2'd1); + +assign add_ln22_2_fu_374_p2 = ((sext_ln22_reg_985) + (zext_ln20_fu_370_p1)); + +assign add_ln22_3_fu_478_p2 = ((sext_ln22_reg_985) + (zext_ln20_2_fu_474_p1)); + +assign add_ln22_fu_306_p2 = ((j_cast_i_i_fu_290_p1) + (17'd131071)); + +assign add_ln25_fu_763_p2 = (select_ln20_reg_1089 + 6'd4); + +assign add_ln32_fu_724_p2 = ((sext_ln20_fu_708_p1) + (zext_ln32_10_fu_720_p1)); + +assign add_ln33_2_fu_816_p2 = (tmp_30_cast_fu_805_p3 + zext_ln33_8_fu_813_p1); + +assign add_ln33_fu_795_p2 = ((sub_ln33_cast_fu_788_p1) + (zext_ln33_7_fu_792_p1)); + +assign and_ln19_fu_606_p2 = (xor_ln19_fu_595_p2 & icmp_ln25_fu_600_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd4]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln32_7_fu_869_p1 = tmp_17_i_i_fu_859_p4; + +assign bitcast_ln32_8_fu_891_p1 = tmp_18_i_i_fu_881_p4; + +assign bitcast_ln32_9_fu_912_p1 = tmp_19_i_i_fu_902_p4; + +assign bitcast_ln32_fu_830_p1 = trunc_ln32_fu_826_p1; + +assign col_coord_int_fu_546_p3 = ((is_padding_reg_1013[0:0] == 1'b1) ? 10'd0 : empty_71_fu_541_p2); + +assign col_coord_int_mid139_fu_575_p3 = ((or_ln23_8_reg_1052[0:0] == 1'b1) ? 10'd0 : p_mid137_reg_1002); + +assign col_coord_int_mid1_fu_663_p3 = ((or_ln23_10_reg_1065[0:0] == 1'b1) ? 10'd0 : p_mid1_fu_658_p2); + +assign empty_68_fu_296_p2 = ((zext_ln19_fu_293_p1) + (17'd131071)); + +assign empty_69_fu_354_p2 = ((p_cast_i_i_reg_979) + (ii_cast_i_i_fu_346_p1)); + +assign empty_70_fu_364_p2 = ((empty_69_fu_354_p2 > 18'd27) ? 1'b1 : 1'b0); + +assign empty_71_fu_541_p2 = ((tmp1_cast_fu_537_p1) + (empty_reg_972)); + +assign empty_73_fu_730_p1 = select_ln20_fu_617_p3[4:0]; + +assign empty_fu_285_p1 = indices_12_dout[9:0]; + +assign icmp_ln19_fu_405_p2 = ((ap_phi_mux_indvar_flatten47_phi_fu_226_p4 == 7'd72) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_417_p2 = ((ap_phi_mux_indvar_flatten_phi_fu_250_p4 == 6'd24) ? 1'b1 : 1'b0); + +assign icmp_ln24_2_fu_387_p2 = (((add_ln22_2_fu_374_p2) > (18'd27)) ? 1'b1 : 1'b0); + +assign icmp_ln24_3_fu_491_p2 = (((add_ln22_3_fu_478_p2) > (18'd27)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_329_p2 = (((add_ln22_fu_306_p2) > (17'd27)) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_600_p2 = ((ap_phi_mux_kk_0_i_i_phi_fu_273_p4 == 6'd32) ? 1'b1 : 1'b0); + +assign ii_cast_fu_350_p1 = ap_phi_mux_ii_phi_fu_238_p4; + +assign ii_cast_i_i_fu_346_p1 = ap_phi_mux_ii_phi_fu_238_p4; + +assign ii_cast_i_i_mid1_fu_431_p1 = add_ln19_fu_411_p2; + +assign ii_cast_mid1_fu_435_p1 = add_ln19_fu_411_p2; + +assign in_data_address0 = sext_ln32_fu_752_p1; + +assign indices_01_out_din = indices_01_dout[4:0]; + +assign indices_12_out_din = indices_12_dout[9:0]; + +assign is_padding_fu_399_p2 = (or_ln23_fu_393_p2 | empty_70_fu_364_p2); + +assign j_cast_i_i_fu_290_p1 = indices_12_read_reg_967; + +assign lshr_ln_fu_734_p4 = {{select_ln20_fu_617_p3[4:2]}}; + +assign or_ln20_fu_612_p2 = (icmp_ln20_reg_1029 | and_ln19_fu_606_p2); + +assign or_ln23_10_fu_503_p2 = (select_ln19_9_fu_455_p3 | or_ln23_9_fu_497_p2); + +assign or_ln23_6_fu_335_p2 = (tmp_9_fu_321_p3 | icmp_ln24_fu_329_p2); + +assign or_ln23_8_fu_463_p2 = (p_mid113_fu_449_p2 | or_ln23_6_reg_997); + +assign or_ln23_9_fu_497_p2 = (tmp_11_fu_483_p3 | icmp_ln24_3_fu_491_p2); + +assign or_ln23_fu_393_p2 = (tmp_10_fu_379_p3 | icmp_ln24_2_fu_387_p2); + +assign or_ln25_5_fu_923_p2 = (empty_73_reg_1109_pp0_iter1_reg | 5'd2); + +assign or_ln25_6_fu_940_p2 = (empty_73_reg_1109_pp0_iter1_reg | 5'd3); + +assign or_ln25_fu_842_p2 = (empty_73_reg_1109_pp0_iter1_reg | 5'd1); + +assign p_cast5_i_i_fu_359_p2 = (p_cast_reg_991 + ii_cast_fu_350_p1); + +assign p_cast5_i_i_mid1_fu_444_p2 = (p_cast_reg_991 + ii_cast_mid1_fu_435_p1); + +assign p_cast_fu_316_p2 = ((trunc_ln250_reg_962) + (5'd31)); + +assign p_cast_i_i_fu_302_p1 = (empty_68_fu_296_p2); + +assign p_mid111_fu_439_p2 = ((p_cast_i_i_reg_979) + (ii_cast_i_i_mid1_fu_431_p1)); + +assign p_mid113_fu_449_p2 = ((p_mid111_fu_439_p2 > 18'd27) ? 1'b1 : 1'b0); + +assign p_mid137_fu_341_p2 = ((empty_reg_972) + (10'd1023)); + +assign p_mid1_fu_658_p2 = ((tmp1_cast_mid1_fu_654_p1) + (empty_reg_972)); + +assign row_coord_int_fu_525_p3 = ((is_padding_reg_1013[0:0] == 1'b1) ? 5'd0 : p_cast5_i_i_reg_1007); + +assign row_coord_int_mid131_fu_569_p3 = ((or_ln23_8_reg_1052[0:0] == 1'b1) ? 5'd0 : p_cast5_i_i_mid1_reg_1046); + +assign row_coord_int_mid1_fu_641_p3 = ((or_ln23_10_reg_1065[0:0] == 1'b1) ? 5'd0 : select_ln19_8_fu_559_p3); + +assign select_ln19_10_fu_564_p3 = ((icmp_ln20_reg_1029[0:0] == 1'b1) ? or_ln23_8_reg_1052 : is_padding_reg_1013); + +assign select_ln19_11_fu_581_p3 = ((icmp_ln20_reg_1029[0:0] == 1'b1) ? row_coord_int_mid131_fu_569_p3 : row_coord_int_fu_525_p3); + +assign select_ln19_12_fu_588_p3 = ((icmp_ln20_reg_1029[0:0] == 1'b1) ? col_coord_int_mid139_fu_575_p3 : col_coord_int_fu_546_p3); + +assign select_ln19_7_fu_553_p3 = ((icmp_ln20_reg_1029[0:0] == 1'b1) ? add_ln19_reg_1024 : ii_reg_234); + +assign select_ln19_8_fu_559_p3 = ((icmp_ln20_reg_1029[0:0] == 1'b1) ? p_cast5_i_i_mid1_reg_1046 : p_cast5_i_i_reg_1007); + +assign select_ln19_9_fu_455_p3 = ((icmp_ln20_fu_417_p2[0:0] == 1'b1) ? p_mid113_fu_449_p2 : empty_70_fu_364_p2); + +assign select_ln19_fu_423_p3 = ((icmp_ln20_fu_417_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_261_p4); + +assign select_ln20_10_fu_757_p3 = ((icmp_ln20_reg_1029[0:0] == 1'b1) ? 6'd1 : add_ln20_2_reg_1072); + +assign select_ln20_6_fu_625_p3 = ((and_ln19_fu_606_p2[0:0] == 1'b1) ? add_ln20_reg_1059 : select_ln19_reg_1041); + +assign select_ln20_7_fu_634_p3 = ((and_ln19_fu_606_p2[0:0] == 1'b1) ? or_ln23_10_reg_1065 : select_ln19_10_fu_564_p3); + +assign select_ln20_8_fu_670_p3 = ((and_ln19_fu_606_p2[0:0] == 1'b1) ? row_coord_int_mid1_fu_641_p3 : select_ln19_11_fu_581_p3); + +assign select_ln20_9_fu_712_p3 = ((and_ln19_fu_606_p2[0:0] == 1'b1) ? col_coord_int_mid1_fu_663_p3 : select_ln19_12_fu_588_p3); + +assign select_ln20_fu_617_p3 = ((or_ln20_fu_612_p2[0:0] == 1'b1) ? 6'd0 : ap_phi_mux_kk_0_i_i_phi_fu_273_p4); + +assign select_ln33_7_fu_873_p3 = ((select_ln20_7_reg_1101_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_7_fu_869_p1); + +assign select_ln33_8_fu_895_p3 = ((select_ln20_7_reg_1101_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_8_fu_891_p1); + +assign select_ln33_9_fu_916_p3 = ((select_ln20_7_reg_1101_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_9_fu_912_p1); + +assign select_ln33_fu_834_p3 = ((select_ln20_7_reg_1101_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_fu_830_p1); + +assign sext_ln20_fu_708_p1 = (sub_ln32_fu_702_p2); + +assign sext_ln22_fu_312_p1 = add_ln22_fu_306_p2; + +assign sext_ln32_fu_752_p1 = (tmp_12_fu_744_p3); + +assign sext_ln33_3_fu_935_p1 = (tmp_14_fu_928_p3); + +assign sext_ln33_4_fu_952_p1 = (tmp_15_fu_945_p3); + +assign sext_ln33_fu_854_p1 = (tmp_13_fu_847_p3); + +assign sub_ln32_fu_702_p2 = (zext_ln32_fu_686_p1 - zext_ln32_9_fu_698_p1); + +assign sub_ln33_cast_fu_788_p1 = (sub_ln33_fu_782_p2); + +assign sub_ln33_fu_782_p2 = (zext_ln33_6_fu_778_p1 - zext_ln33_fu_768_p1); + +assign tmp1_cast_fu_537_p1 = (tmp1_fu_531_p2); + +assign tmp1_cast_mid1_fu_654_p1 = (tmp1_mid1_fu_648_p2); + +assign tmp1_fu_531_p2 = ((zext_ln22_fu_521_p1) + (3'd7)); + +assign tmp1_mid1_fu_648_p2 = ((zext_ln22_2_fu_631_p1) + (3'd7)); + +assign tmp_10_fu_379_p3 = add_ln22_2_fu_374_p2[32'd17]; + +assign tmp_11_fu_483_p3 = add_ln22_3_fu_478_p2[32'd17]; + +assign tmp_12_fu_744_p3 = {{add_ln32_fu_724_p2}, {lshr_ln_fu_734_p4}}; + +assign tmp_13_fu_847_p3 = {{add_ln33_reg_1131}, {or_ln25_fu_842_p2}}; + +assign tmp_14_fu_928_p3 = {{add_ln33_reg_1131}, {or_ln25_5_fu_923_p2}}; + +assign tmp_15_fu_945_p3 = {{add_ln33_reg_1131}, {or_ln25_6_fu_940_p2}}; + +assign tmp_17_i_i_fu_859_p4 = {{in_data_q0[31:16]}}; + +assign tmp_18_i_i_fu_881_p4 = {{in_data_q0[47:32]}}; + +assign tmp_19_i_i_fu_902_p4 = {{in_data_q0[63:48]}}; + +assign tmp_30_cast_fu_805_p3 = {{trunc_ln33_fu_801_p1}, {5'd0}}; + +assign tmp_3_fu_690_p3 = {{select_ln20_8_fu_670_p3}, {2'd0}}; + +assign tmp_9_fu_321_p3 = add_ln22_fu_306_p2[32'd16]; + +assign tmp_fu_771_p3 = {{select_ln19_7_reg_1082}, {2'd0}}; + +assign tmp_s_fu_678_p3 = {{select_ln20_8_fu_670_p3}, {5'd0}}; + +assign trunc_ln250_fu_280_p1 = indices_01_dout[4:0]; + +assign trunc_ln32_fu_826_p1 = in_data_q0[15:0]; + +assign trunc_ln33_fu_801_p1 = add_ln33_fu_795_p2[3:0]; + +assign xor_ln19_fu_595_p2 = (icmp_ln20_reg_1029 ^ 1'd1); + +assign zext_ln19_fu_293_p1 = indices_01_read_reg_957; + +assign zext_ln20_2_fu_474_p1 = add_ln20_fu_468_p2; + +assign zext_ln20_fu_370_p1 = ap_phi_mux_jj_phi_fu_261_p4; + +assign zext_ln22_2_fu_631_p1 = add_ln20_reg_1059; + +assign zext_ln22_fu_521_p1 = jj_reg_257; + +assign zext_ln32_10_fu_720_p1 = select_ln20_9_fu_712_p3; + +assign zext_ln32_9_fu_698_p1 = tmp_3_fu_690_p3; + +assign zext_ln32_fu_686_p1 = tmp_s_fu_678_p3; + +assign zext_ln33_6_fu_778_p1 = tmp_fu_771_p3; + +assign zext_ln33_7_fu_792_p1 = select_ln20_6_reg_1095; + +assign zext_ln33_8_fu_813_p1 = select_ln20_reg_1089; + +assign zext_ln33_9_fu_822_p1 = add_ln33_2_reg_1138; + +assign zext_ln33_fu_768_p1 = select_ln19_7_reg_1082; + +endmodule //td_fused_top_tdf7_readInputs53 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_17 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [12:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [12:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [13:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [13:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [16:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [16:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [7:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [7:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [12:0] dataflow_in_loop_TOP_LOOP37454_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP37454_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP37454_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP37454_U0_in_data_we0; +wire [12:0] dataflow_in_loop_TOP_LOOP37454_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP37454_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP37454_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP37454_U0_in_data_we1; +wire [16:0] dataflow_in_loop_TOP_LOOP37454_U0_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP37454_U0_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP37454_U0_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP37454_U0_filter_data_we0; +wire [16:0] dataflow_in_loop_TOP_LOOP37454_U0_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP37454_U0_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP37454_U0_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP37454_U0_filter_data_we1; +wire [7:0] dataflow_in_loop_TOP_LOOP37454_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP37454_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP37454_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP37454_U0_adjustments_we0; +wire [7:0] dataflow_in_loop_TOP_LOOP37454_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP37454_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP37454_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP37454_U0_adjustments_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP37454_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP37454_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP37454_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP37454_U0_out_data_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP37454_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP37454_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP37454_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP37454_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP37454_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP37454_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP37454_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP37454_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP37454_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP37454_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP37454_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP37454_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP37454_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [17:0] loop_dataflow_input_count; +reg [17:0] loop_dataflow_output_count; +wire [17:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP37454_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP37454_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 18'd0; +#0 loop_dataflow_output_count = 18'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP37454 dataflow_in_loop_TOP_LOOP37454_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP37454_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP37454_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP37454_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP37454_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP37454_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP37454_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP37454_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP37454_U0_in_data_we1), + .filter_data_address0(dataflow_in_loop_TOP_LOOP37454_U0_filter_data_address0), + .filter_data_ce0(dataflow_in_loop_TOP_LOOP37454_U0_filter_data_ce0), + .filter_data_d0(dataflow_in_loop_TOP_LOOP37454_U0_filter_data_d0), + .filter_data_q0(filter_data_q0), + .filter_data_we0(dataflow_in_loop_TOP_LOOP37454_U0_filter_data_we0), + .filter_data_address1(dataflow_in_loop_TOP_LOOP37454_U0_filter_data_address1), + .filter_data_ce1(dataflow_in_loop_TOP_LOOP37454_U0_filter_data_ce1), + .filter_data_d1(dataflow_in_loop_TOP_LOOP37454_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(dataflow_in_loop_TOP_LOOP37454_U0_filter_data_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP37454_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP37454_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP37454_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP37454_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP37454_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP37454_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP37454_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP37454_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP37454_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP37454_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP37454_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP37454_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP37454_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP37454_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP37454_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP37454_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP37454_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP37454_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP37454_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP37454_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP37454_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP37454_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP37454_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 18'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37454_U0_ap_ready == 1'b1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 18'd1); + end else if (((dataflow_in_loop_TOP_LOOP37454_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= 18'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 18'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37454_U0_ap_done == 1'b1) & (dataflow_in_loop_TOP_LOOP37454_U0_ap_continue == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 18'd1); + end else if (((dataflow_in_loop_TOP_LOOP37454_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37454_U0_ap_continue == 1'b1))) begin + loop_dataflow_output_count <= 18'd0; + end + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP37454_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP37454_U0_ap_idle == 1'b1) & (loop_dataflow_output_count == 18'd0) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP37454_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP37454_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP37454_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP37454_U0_adjustments_address0; + +assign adjustments_address1 = 8'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP37454_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP37454_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP37454_U0_ap_ready; + +assign bound_minus_1 = (18'd200704 - 18'd1); + +assign dataflow_in_loop_TOP_LOOP37454_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP37454_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP37454_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP37454_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP37454_U0_start_write = 1'b0; + +assign filter_data_address0 = dataflow_in_loop_TOP_LOOP37454_U0_filter_data_address0; + +assign filter_data_address1 = 17'd0; + +assign filter_data_ce0 = dataflow_in_loop_TOP_LOOP37454_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP37454_U0_in_data_address0; + +assign in_data_address1 = 13'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP37454_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP37454_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 14'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP37454_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP37454_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP37454_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP37454_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP37454_U0_out_data_write; + +endmodule //td_fused_top_tdf8_17 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 8'd1; +parameter ap_ST_fsm_pp0_stage0 = 8'd2; +parameter ap_ST_fsm_pp0_stage1 = 8'd4; +parameter ap_ST_fsm_pp0_stage2 = 8'd8; +parameter ap_ST_fsm_pp0_stage3 = 8'd16; +parameter ap_ST_fsm_state12 = 8'd32; +parameter ap_ST_fsm_state13 = 8'd64; +parameter ap_ST_fsm_state14 = 8'd128; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [8:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [8:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[8:0] accum_in_0_address0; +reg accum_in_0_ce0; +reg[8:0] accum_in_0_address1; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [7:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [8:0] x_reg_168; +reg [15:0] psum_7_08_reg_180; +reg [15:0] psum_6_07_reg_192; +reg [15:0] psum_5_06_reg_204; +reg [15:0] psum_4_05_reg_216; +reg [15:0] psum_3_04_reg_228; +reg [15:0] psum_2_03_reg_240; +reg [15:0] psum_1_02_reg_252; +reg [15:0] psum_0_01_reg_264; +wire [0:0] icmp_ln49_fu_321_p2; +reg [0:0] icmp_ln49_reg_492; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state6_pp0_stage0_iter1; +wire ap_block_state10_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] icmp_ln49_reg_492_pp0_iter1_reg; +reg [0:0] icmp_ln49_reg_492_pp0_iter2_reg; +reg [15:0] accum_in_0_load_reg_506; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state7_pp0_stage1_iter1; +wire ap_block_state11_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_0_load_8_reg_511; +reg [15:0] accum_in_0_load_9_reg_526; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state8_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_0_load_10_reg_531; +wire [8:0] add_ln49_fu_387_p2; +reg [8:0] add_ln49_reg_546; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state9_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_0_load_11_reg_551; +reg [15:0] accum_in_0_load_12_reg_556; +reg [15:0] accum_in_0_load_13_reg_571; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_0_load_14_reg_576; +wire [15:0] grp_fu_305_p2; +wire [15:0] grp_fu_310_p2; +reg ap_enable_reg_pp0_iter2; +wire [3:0] add_ln57_fu_432_p2; +wire ap_CS_fsm_state13; +wire [0:0] tmp_fu_415_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage1_subdone; +reg [8:0] ap_phi_mux_x_phi_fu_172_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_184_p4; +wire ap_block_pp0_stage1; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_196_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_208_p4; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_220_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_232_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_03_phi_fu_244_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_276; +wire ap_CS_fsm_state12; +reg [15:0] ap_phi_mux_phi_ln69_phi_fu_290_p8; +wire [2:0] trunc_ln57_fu_428_p1; +wire [63:0] zext_ln49_fu_327_p1; +wire [63:0] zext_ln53_fu_338_p1; +wire [63:0] zext_ln53_1_fu_349_p1; +wire [63:0] zext_ln53_2_fu_360_p1; +wire [63:0] zext_ln53_3_fu_371_p1; +wire [63:0] zext_ln53_4_fu_382_p1; +wire [63:0] zext_ln53_5_fu_399_p1; +wire [63:0] zext_ln53_6_fu_410_p1; +wire [63:0] zext_ln57_fu_423_p1; +wire [63:0] zext_ln57_1_fu_444_p1; +reg [15:0] grp_fu_305_p0; +reg [15:0] grp_fu_305_p1; +reg [15:0] grp_fu_310_p0; +reg [15:0] grp_fu_310_p1; +wire [8:0] or_ln53_fu_332_p2; +wire [8:0] or_ln53_1_fu_343_p2; +wire [8:0] or_ln53_2_fu_354_p2; +wire [8:0] or_ln53_3_fu_365_p2; +wire [8:0] or_ln53_4_fu_376_p2; +wire [8:0] or_ln53_5_fu_393_p2; +wire [8:0] or_ln53_6_fu_404_p2; +wire [2:0] or_ln57_fu_438_p2; +wire [0:0] icmp_ln69_fu_449_p2; +wire [0:0] icmp_ln69_1_fu_463_p2; +wire [15:0] select_ln69_fu_455_p3; +wire [0:0] icmp_ln69_2_fu_477_p2; +wire [15:0] select_ln69_1_fu_469_p3; +wire ap_CS_fsm_state14; +reg [7:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_514; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 8'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U498( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_305_p0), + .din1(grp_fu_305_p1), + .dout(grp_fu_305_p2) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U499( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_310_p0), + .din1(grp_fu_310_p1), + .dout(grp_fu_310_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + q_reg_276 <= 4'd0; + end else if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + q_reg_276 <= add_ln57_fu_432_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + x_reg_168 <= add_ln49_reg_546; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_168 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_load_10_reg_531 <= accum_in_0_q0; + accum_in_0_load_9_reg_526 <= accum_in_0_q1; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_load_11_reg_551 <= accum_in_0_q1; + accum_in_0_load_12_reg_556 <= accum_in_0_q0; + add_ln49_reg_546 <= add_ln49_fu_387_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_0_load_13_reg_571 <= accum_in_0_q1; + accum_in_0_load_14_reg_576 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_load_8_reg_511 <= accum_in_0_q0; + accum_in_0_load_reg_506 <= accum_in_0_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln49_reg_492 <= icmp_ln49_fu_321_p2; + icmp_ln49_reg_492_pp0_iter1_reg <= icmp_ln49_reg_492; + icmp_ln49_reg_492_pp0_iter2_reg <= icmp_ln49_reg_492_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_0_01_reg_264 <= grp_fu_305_p2; + psum_1_02_reg_252 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_2_03_reg_240 <= grp_fu_305_p2; + psum_3_04_reg_228 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_492_pp0_iter1_reg == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + psum_4_05_reg_216 <= grp_fu_305_p2; + psum_5_06_reg_204 <= grp_fu_310_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_492_pp0_iter2_reg == 1'd1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + psum_6_07_reg_192 <= grp_fu_305_p2; + psum_7_08_reg_180 <= grp_fu_310_p2; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address0 = zext_ln53_6_fu_410_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address0 = zext_ln53_4_fu_382_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address0 = zext_ln53_2_fu_360_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address0 = zext_ln53_fu_338_p1; + end else begin + accum_in_0_address0 = 'bx; + end + end else begin + accum_in_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address1 = zext_ln53_5_fu_399_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address1 = zext_ln53_3_fu_371_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address1 = zext_ln53_1_fu_349_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address1 = zext_ln49_fu_327_p1; + end else begin + accum_in_0_address1 = 'bx; + end + end else begin + accum_in_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((icmp_ln49_reg_492 == 1'd0)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + if ((trunc_ln57_fu_428_p1 == 3'd0)) begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = psum_0_01_reg_264; + end else if ((1'b1 == ap_condition_514)) begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = psum_6_07_reg_192; + end else if ((trunc_ln57_fu_428_p1 == 3'd4)) begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = psum_4_05_reg_216; + end else if ((trunc_ln57_fu_428_p1 == 3'd2)) begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = psum_2_03_reg_240; + end else begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln69_phi_fu_290_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (icmp_ln49_reg_492 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_x_phi_fu_172_p4 = add_ln49_reg_546; + end else begin + ap_phi_mux_x_phi_fu_172_p4 = x_reg_168; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_6_07_phi_fu_196_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p0 = ap_phi_mux_psum_4_05_phi_fu_220_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p0 = ap_phi_mux_psum_2_03_phi_fu_244_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p0 = grp_fu_305_p2; + end else begin + grp_fu_305_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p1 = accum_in_0_load_13_reg_571; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_305_p1 = accum_in_0_load_11_reg_551; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_305_p1 = accum_in_0_load_9_reg_526; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_305_p1 = accum_in_0_load_reg_506; + end else begin + grp_fu_305_p1 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p0 = ap_phi_mux_psum_7_08_phi_fu_184_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p0 = ap_phi_mux_psum_5_06_phi_fu_208_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p0 = ap_phi_mux_psum_3_04_phi_fu_232_p4; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p0 = grp_fu_310_p2; + end else begin + grp_fu_310_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p1 = accum_in_0_load_14_reg_576; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_310_p1 = accum_in_0_load_12_reg_556; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + grp_fu_310_p1 = accum_in_0_load_10_reg_531; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + grp_fu_310_p1 = accum_in_0_load_8_reg_511; + end else begin + grp_fu_310_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (icmp_ln49_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (icmp_ln49_reg_492 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + if (((tmp_fu_415_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_state14; + end + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln57_1_fu_444_p1; + +assign accum_out_address1 = zext_ln57_fu_423_p1; + +assign accum_out_d0 = ((icmp_ln69_2_fu_477_p2[0:0] == 1'b1) ? psum_5_06_reg_204 : select_ln69_1_fu_469_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln69_phi_fu_290_p8; + +assign add_ln49_fu_387_p2 = (x_reg_168 + 9'd8); + +assign add_ln57_fu_432_p2 = (q_reg_276 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_state14 = ap_CS_fsm[32'd7]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_514 = (~(trunc_ln57_fu_428_p1 == 3'd0) & ~(trunc_ln57_fu_428_p1 == 3'd4) & ~(trunc_ln57_fu_428_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_03_phi_fu_244_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_232_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_220_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_208_p4 = grp_fu_310_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_196_p4 = grp_fu_305_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_184_p4 = grp_fu_310_p2; + +assign icmp_ln49_fu_321_p2 = ((ap_phi_mux_x_phi_fu_172_p4 < 9'd288) ? 1'b1 : 1'b0); + +assign icmp_ln69_1_fu_463_p2 = ((or_ln57_fu_438_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln69_2_fu_477_p2 = ((or_ln57_fu_438_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln69_fu_449_p2 = ((or_ln57_fu_438_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln53_1_fu_343_p2 = (x_reg_168 | 9'd2); + +assign or_ln53_2_fu_354_p2 = (x_reg_168 | 9'd3); + +assign or_ln53_3_fu_365_p2 = (x_reg_168 | 9'd4); + +assign or_ln53_4_fu_376_p2 = (x_reg_168 | 9'd5); + +assign or_ln53_5_fu_393_p2 = (x_reg_168 | 9'd6); + +assign or_ln53_6_fu_404_p2 = (x_reg_168 | 9'd7); + +assign or_ln53_fu_332_p2 = (ap_phi_mux_x_phi_fu_172_p4 | 9'd1); + +assign or_ln57_fu_438_p2 = (trunc_ln57_fu_428_p1 | 3'd1); + +assign select_ln69_1_fu_469_p3 = ((icmp_ln69_1_fu_463_p2[0:0] == 1'b1) ? psum_3_04_reg_228 : select_ln69_fu_455_p3); + +assign select_ln69_fu_455_p3 = ((icmp_ln69_fu_449_p2[0:0] == 1'b1) ? psum_1_02_reg_252 : psum_7_08_reg_180); + +assign tmp_fu_415_p3 = q_reg_276[32'd3]; + +assign trunc_ln57_fu_428_p1 = q_reg_276[2:0]; + +assign zext_ln49_fu_327_p1 = ap_phi_mux_x_phi_fu_172_p4; + +assign zext_ln53_1_fu_349_p1 = or_ln53_1_fu_343_p2; + +assign zext_ln53_2_fu_360_p1 = or_ln53_2_fu_354_p2; + +assign zext_ln53_3_fu_371_p1 = or_ln53_3_fu_365_p2; + +assign zext_ln53_4_fu_382_p1 = or_ln53_4_fu_376_p2; + +assign zext_ln53_5_fu_399_p1 = or_ln53_5_fu_393_p2; + +assign zext_ln53_6_fu_410_p1 = or_ln53_6_fu_404_p2; + +assign zext_ln53_fu_338_p1 = or_ln53_fu_332_p2; + +assign zext_ln57_1_fu_444_p1 = or_ln57_fu_438_p2; + +assign zext_ln57_fu_423_p1 = q_reg_276; + +endmodule //td_fused_top_tdf8_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_4, + accum_in_4_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 7'd1; +parameter ap_ST_fsm_state2 = 7'd2; +parameter ap_ST_fsm_state3 = 7'd4; +parameter ap_ST_fsm_state4 = 7'd8; +parameter ap_ST_fsm_state5 = 7'd16; +parameter ap_ST_fsm_state6 = 7'd32; +parameter ap_ST_fsm_state7 = 7'd64; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_4; +output accum_in_4_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_4; +reg accum_in_4_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [6:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln81_fu_74_p2; +reg [3:0] add_ln81_reg_91; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln81_fu_85_p2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state7; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_01_reg_55; +wire [63:0] zext_ln81_fu_80_p1; +reg [15:0] accum_in_4_preg; +reg [6:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 7'd1; +#0 accum_in_4_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U502( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_01_reg_55), + .din1(accum_in_q0), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_4_preg <= 16'd0; + end else begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_4_preg <= sum_01_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + i_1_1_reg_44 <= add_ln81_reg_91; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_01_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + sum_01_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln81_reg_91 <= add_ln81_fu_74_p2; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_4 = sum_01_reg_55; + end else begin + accum_in_4 = accum_in_4_preg; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_4_ap_vld = 1'b1; + end else begin + accum_in_4_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln81_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln81_fu_80_p1; + +assign add_ln81_fu_74_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln81_fu_85_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln81_fu_80_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf8_accum_2 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 17'd1; +parameter ap_ST_fsm_state2 = 17'd2; +parameter ap_ST_fsm_state3 = 17'd4; +parameter ap_ST_fsm_state4 = 17'd8; +parameter ap_ST_fsm_state5 = 17'd16; +parameter ap_ST_fsm_state6 = 17'd32; +parameter ap_ST_fsm_state7 = 17'd64; +parameter ap_ST_fsm_state8 = 17'd128; +parameter ap_ST_fsm_state9 = 17'd256; +parameter ap_ST_fsm_state10 = 17'd512; +parameter ap_ST_fsm_state11 = 17'd1024; +parameter ap_ST_fsm_state12 = 17'd2048; +parameter ap_ST_fsm_state13 = 17'd4096; +parameter ap_ST_fsm_state14 = 17'd8192; +parameter ap_ST_fsm_state15 = 17'd16384; +parameter ap_ST_fsm_state16 = 17'd32768; +parameter ap_ST_fsm_state17 = 17'd65536; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_read; +output [7:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [7:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg input_indices_23_read; + +reg ap_done_reg; + reg [16:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +wire ap_CS_fsm_state4; +reg [15:0] tmp_15_i_i_reg_167; +reg [15:0] tmp_16_i_i_reg_172; +wire [15:0] grp_fu_81_p2; +reg [15:0] sub_i_i_i_reg_177; +wire ap_CS_fsm_state8; +wire ap_CS_fsm_state9; +wire [15:0] grp_fu_86_p2; +reg [15:0] mul_i_i_i_reg_187; +wire ap_CS_fsm_state12; +wire ap_CS_fsm_state13; +wire [63:0] zext_ln220_fu_90_p1; +reg ap_block_state1; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_77_p1; +wire [15:0] grp_fu_81_p1; +wire [15:0] grp_fu_86_p1; +wire [15:0] trunc_ln220_fu_95_p1; +wire [15:0] grp_fu_77_p2; +wire ap_CS_fsm_state17; +wire [15:0] bitcast_ln648_fu_132_p1; +wire [0:0] tmp_fu_136_p3; +reg [16:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 17'd1; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U506( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(mul_i_i_i_reg_187), + .din1(grp_fu_77_p1), + .dout(grp_fu_77_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U507( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sums_read), + .din1(grp_fu_81_p1), + .dout(grp_fu_81_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U508( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_177), + .din1(grp_fu_86_p1), + .dout(grp_fu_86_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + mul_i_i_i_reg_187 <= grp_fu_86_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sub_i_i_i_reg_177 <= grp_fu_81_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tmp_15_i_i_reg_167 <= {{adjustments_q0[31:16]}}; + tmp_16_i_i_reg_172 <= {{adjustments_q0[47:32]}}; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (~((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign adjustments_address0 = zext_ln220_fu_90_p1; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_return = ((tmp_fu_136_p3[0:0] == 1'b1) ? 16'd0 : grp_fu_77_p2); + +assign bitcast_ln648_fu_132_p1 = grp_fu_77_p2; + +assign grp_fu_77_p1 = tmp_16_i_i_reg_172; + +assign grp_fu_81_p1 = trunc_ln220_fu_95_p1; + +assign grp_fu_86_p1 = tmp_15_i_i_reg_167; + +assign tmp_fu_136_p3 = bitcast_ln648_fu_132_p1[32'd15]; + +assign trunc_ln220_fu_95_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_90_p1 = input_indices_23_dout; + +endmodule //td_fused_top_tdf8_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_q0, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state10 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [8:0] ifmap_vec_address0; +output ifmap_vec_ce0; +input [15:0] ifmap_vec_q0; +output [8:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +input [15:0] weight_vecs_0_q0; +output [8:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_ce0; +reg weight_vecs_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [8:0] indvar_flatten17_reg_97; +reg [7:0] indvar_flatten_reg_108; +reg [1:0] jj_reg_119; +reg [5:0] ic_reg_131; +reg [1:0] ii_reg_142; +wire [8:0] add_ln147_1_fu_157_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_state9_pp0_stage0_iter7; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln147_fu_163_p2; +reg [0:0] icmp_ln147_reg_408; +reg [0:0] icmp_ln147_reg_408_pp0_iter1_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter2_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter3_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter4_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter5_reg; +reg [0:0] icmp_ln147_reg_408_pp0_iter6_reg; +wire [0:0] icmp_ln148_fu_169_p2; +reg [0:0] icmp_ln148_reg_412; +wire [0:0] and_ln147_fu_195_p2; +reg [0:0] and_ln147_reg_419; +wire [1:0] add_ln148_fu_201_p2; +reg [1:0] add_ln148_reg_424; +wire [5:0] select_ln148_fu_213_p3; +reg [5:0] select_ln148_reg_429; +wire [1:0] select_ln148_1_fu_221_p3; +reg [1:0] select_ln148_1_reg_434; +wire [4:0] trunc_ln150_fu_229_p1; +reg [4:0] trunc_ln150_reg_440; +reg [4:0] trunc_ln150_reg_440_pp0_iter1_reg; +reg [4:0] trunc_ln150_reg_440_pp0_iter2_reg; +reg [4:0] trunc_ln150_reg_440_pp0_iter3_reg; +reg [4:0] trunc_ln150_reg_440_pp0_iter4_reg; +reg [4:0] trunc_ln150_reg_440_pp0_iter5_reg; +reg [4:0] trunc_ln150_reg_440_pp0_iter6_reg; +wire [5:0] add_ln149_fu_233_p2; +wire [7:0] select_ln148_3_fu_245_p3; +wire [1:0] select_ln147_2_fu_287_p3; +reg [1:0] select_ln147_2_reg_455; +reg ap_enable_reg_pp0_iter1; +wire [3:0] select_ln148_2_fu_370_p3; +reg [3:0] select_ln148_2_reg_460; +reg [3:0] select_ln148_2_reg_460_pp0_iter2_reg; +reg [3:0] select_ln148_2_reg_460_pp0_iter3_reg; +reg [3:0] select_ln148_2_reg_460_pp0_iter4_reg; +reg [3:0] select_ln148_2_reg_460_pp0_iter5_reg; +reg [3:0] select_ln148_2_reg_460_pp0_iter6_reg; +reg [15:0] ifmap_vec_load_reg_475; +reg [15:0] weight_vecs_0_load_reg_480; +wire [15:0] grp_fu_153_p2; +reg [15:0] mul_reg_485; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +reg ap_enable_reg_pp0_iter7; +reg [1:0] ap_phi_mux_jj_phi_fu_123_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_146_p4; +wire [63:0] p_cast25_fu_386_p1; +wire [63:0] idxprom30_fu_398_p1; +wire [0:0] icmp_ln149_fu_189_p2; +wire [0:0] xor_ln147_fu_183_p2; +wire [1:0] select_ln147_fu_175_p3; +wire [0:0] or_ln148_fu_207_p2; +wire [7:0] add_ln148_1_fu_239_p2; +wire [3:0] shl_ln_fu_257_p3; +wire [3:0] zext_ln150_fu_253_p1; +wire [3:0] sub_ln150_fu_265_p2; +wire [3:0] zext_ln150_1_fu_271_p1; +wire [1:0] add_ln147_fu_281_p2; +wire [3:0] tmp_fu_298_p3; +wire [3:0] select_ln147_2_cast_fu_294_p1; +wire [3:0] shl_ln150_mid1_fu_316_p3; +wire [3:0] zext_ln150_2_fu_312_p1; +wire [3:0] sub_ln150_1_fu_324_p2; +wire [3:0] add_ln150_fu_275_p2; +wire [3:0] empty_64_fu_306_p2; +wire [3:0] select_ln148_1_cast_fu_344_p1; +wire [3:0] empty_65_fu_347_p2; +wire [3:0] select_ln147_3_fu_330_p3; +wire [3:0] zext_ln150_3_fu_361_p1; +wire [3:0] add_ln150_1_fu_364_p2; +wire [3:0] select_ln147_4_fu_337_p3; +wire [8:0] tmp_28_cast_fu_353_p3; +wire [8:0] select_ln148_cast_fu_377_p1; +wire [8:0] empty_66_fu_380_p2; +wire [8:0] p_fu_392_p3; +wire ap_CS_fsm_state10; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +#0 ap_enable_reg_pp0_iter7 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U494( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_load_reg_475), + .din1(weight_vecs_0_load_reg_480), + .dout(grp_fu_153_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter7 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_reg_131 <= add_ln149_fu_233_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_reg_131 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ii_reg_142 <= select_ln147_2_reg_455; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_142 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten17_reg_97 <= add_ln147_1_fu_157_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten17_reg_97 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_108 <= select_ln148_3_fu_245_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_108 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_119 <= select_ln148_1_reg_434; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_119 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln148_reg_424 <= add_ln148_fu_201_p2; + and_ln147_reg_419 <= and_ln147_fu_195_p2; + icmp_ln148_reg_412 <= icmp_ln148_fu_169_p2; + select_ln148_reg_429 <= select_ln148_fu_213_p3; + trunc_ln150_reg_440 <= trunc_ln150_fu_229_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln147_reg_408 <= icmp_ln147_fu_163_p2; + icmp_ln147_reg_408_pp0_iter1_reg <= icmp_ln147_reg_408; + trunc_ln150_reg_440_pp0_iter1_reg <= trunc_ln150_reg_440; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln147_reg_408_pp0_iter2_reg <= icmp_ln147_reg_408_pp0_iter1_reg; + icmp_ln147_reg_408_pp0_iter3_reg <= icmp_ln147_reg_408_pp0_iter2_reg; + icmp_ln147_reg_408_pp0_iter4_reg <= icmp_ln147_reg_408_pp0_iter3_reg; + icmp_ln147_reg_408_pp0_iter5_reg <= icmp_ln147_reg_408_pp0_iter4_reg; + icmp_ln147_reg_408_pp0_iter6_reg <= icmp_ln147_reg_408_pp0_iter5_reg; + select_ln148_2_reg_460_pp0_iter2_reg <= select_ln148_2_reg_460; + select_ln148_2_reg_460_pp0_iter3_reg <= select_ln148_2_reg_460_pp0_iter2_reg; + select_ln148_2_reg_460_pp0_iter4_reg <= select_ln148_2_reg_460_pp0_iter3_reg; + select_ln148_2_reg_460_pp0_iter5_reg <= select_ln148_2_reg_460_pp0_iter4_reg; + select_ln148_2_reg_460_pp0_iter6_reg <= select_ln148_2_reg_460_pp0_iter5_reg; + trunc_ln150_reg_440_pp0_iter2_reg <= trunc_ln150_reg_440_pp0_iter1_reg; + trunc_ln150_reg_440_pp0_iter3_reg <= trunc_ln150_reg_440_pp0_iter2_reg; + trunc_ln150_reg_440_pp0_iter4_reg <= trunc_ln150_reg_440_pp0_iter3_reg; + trunc_ln150_reg_440_pp0_iter5_reg <= trunc_ln150_reg_440_pp0_iter4_reg; + trunc_ln150_reg_440_pp0_iter6_reg <= trunc_ln150_reg_440_pp0_iter5_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + ifmap_vec_load_reg_475 <= ifmap_vec_q0; + weight_vecs_0_load_reg_480 <= weight_vecs_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_reg_485 <= grp_fu_153_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + select_ln147_2_reg_455 <= select_ln147_2_fu_287_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_fu_163_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_1_reg_434 <= select_ln148_1_fu_221_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln148_2_reg_460 <= select_ln148_2_fu_370_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_fu_163_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_146_p4 = select_ln147_2_reg_455; + end else begin + ap_phi_mux_ii_phi_fu_146_p4 = ii_reg_142; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_123_p4 = select_ln148_1_reg_434; + end else begin + ap_phi_mux_jj_phi_fu_123_p4 = jj_reg_119; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state10)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln147_reg_408_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter7 == 1'b1) & (ap_enable_reg_pp0_iter6 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ap_NS_fsm = ap_ST_fsm_state10; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln147_1_fu_157_p2 = (indvar_flatten17_reg_97 + 9'd1); + +assign add_ln147_fu_281_p2 = (ap_phi_mux_ii_phi_fu_146_p4 + 2'd1); + +assign add_ln148_1_fu_239_p2 = (indvar_flatten_reg_108 + 8'd1); + +assign add_ln148_fu_201_p2 = (select_ln147_fu_175_p3 + 2'd1); + +assign add_ln149_fu_233_p2 = (select_ln148_fu_213_p3 + 6'd1); + +assign add_ln150_1_fu_364_p2 = (select_ln147_3_fu_330_p3 + zext_ln150_3_fu_361_p1); + +assign add_ln150_fu_275_p2 = (sub_ln150_fu_265_p2 + zext_ln150_1_fu_271_p1); + +assign and_ln147_fu_195_p2 = (xor_ln147_fu_183_p2 & icmp_ln149_fu_189_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state10 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage0_iter7 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign empty_64_fu_306_p2 = (tmp_fu_298_p3 - select_ln147_2_cast_fu_294_p1); + +assign empty_65_fu_347_p2 = (empty_64_fu_306_p2 + select_ln148_1_cast_fu_344_p1); + +assign empty_66_fu_380_p2 = (tmp_28_cast_fu_353_p3 + select_ln148_cast_fu_377_p1); + +assign icmp_ln147_fu_163_p2 = ((indvar_flatten17_reg_97 == 9'd288) ? 1'b1 : 1'b0); + +assign icmp_ln148_fu_169_p2 = ((indvar_flatten_reg_108 == 8'd96) ? 1'b1 : 1'b0); + +assign icmp_ln149_fu_189_p2 = ((ic_reg_131 == 6'd32) ? 1'b1 : 1'b0); + +assign idxprom30_fu_398_p1 = p_fu_392_p3; + +assign ifmap_vec_address0 = p_cast25_fu_386_p1; + +assign or_ln148_fu_207_p2 = (icmp_ln148_fu_169_p2 | and_ln147_fu_195_p2); + +assign p_cast25_fu_386_p1 = empty_66_fu_380_p2; + +assign p_fu_392_p3 = {{select_ln148_2_reg_460_pp0_iter6_reg}, {trunc_ln150_reg_440_pp0_iter6_reg}}; + +assign products_0_address0 = idxprom30_fu_398_p1; + +assign products_0_d0 = mul_reg_485; + +assign select_ln147_2_cast_fu_294_p1 = select_ln147_2_fu_287_p3; + +assign select_ln147_2_fu_287_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? add_ln147_fu_281_p2 : ap_phi_mux_ii_phi_fu_146_p4); + +assign select_ln147_3_fu_330_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? sub_ln150_1_fu_324_p2 : sub_ln150_fu_265_p2); + +assign select_ln147_4_fu_337_p3 = ((icmp_ln148_reg_412[0:0] == 1'b1) ? sub_ln150_1_fu_324_p2 : add_ln150_fu_275_p2); + +assign select_ln147_fu_175_p3 = ((icmp_ln148_fu_169_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_123_p4); + +assign select_ln148_1_cast_fu_344_p1 = select_ln148_1_reg_434; + +assign select_ln148_1_fu_221_p3 = ((and_ln147_fu_195_p2[0:0] == 1'b1) ? add_ln148_fu_201_p2 : select_ln147_fu_175_p3); + +assign select_ln148_2_fu_370_p3 = ((and_ln147_reg_419[0:0] == 1'b1) ? add_ln150_1_fu_364_p2 : select_ln147_4_fu_337_p3); + +assign select_ln148_3_fu_245_p3 = ((icmp_ln148_fu_169_p2[0:0] == 1'b1) ? 8'd1 : add_ln148_1_fu_239_p2); + +assign select_ln148_cast_fu_377_p1 = select_ln148_reg_429; + +assign select_ln148_fu_213_p3 = ((or_ln148_fu_207_p2[0:0] == 1'b1) ? 6'd0 : ic_reg_131); + +assign shl_ln150_mid1_fu_316_p3 = {{add_ln147_fu_281_p2}, {2'd0}}; + +assign shl_ln_fu_257_p3 = {{ap_phi_mux_ii_phi_fu_146_p4}, {2'd0}}; + +assign sub_ln150_1_fu_324_p2 = (shl_ln150_mid1_fu_316_p3 - zext_ln150_2_fu_312_p1); + +assign sub_ln150_fu_265_p2 = (shl_ln_fu_257_p3 - zext_ln150_fu_253_p1); + +assign tmp_28_cast_fu_353_p3 = {{empty_65_fu_347_p2}, {5'd0}}; + +assign tmp_fu_298_p3 = {{select_ln147_2_fu_287_p3}, {2'd0}}; + +assign trunc_ln150_fu_229_p1 = select_ln148_fu_213_p3[4:0]; + +assign weight_vecs_0_address0 = p_cast25_fu_386_p1; + +assign xor_ln147_fu_183_p2 = (icmp_ln148_fu_169_p2 ^ 1'd1); + +assign zext_ln150_1_fu_271_p1 = jj_reg_119; + +assign zext_ln150_2_fu_312_p1 = add_ln147_fu_281_p2; + +assign zext_ln150_3_fu_361_p1 = add_ln148_reg_424; + +assign zext_ln150_fu_253_p1 = ap_phi_mux_ii_phi_fu_146_p4; + +endmodule //td_fused_top_tdf8_dot_product +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + input_indices_2_out_din, + input_indices_2_out_full_n, + input_indices_2_out_write, + input_indices_2_out1_din, + input_indices_2_out1_full_n, + input_indices_2_out1_write, + output_indices_0_din, + output_indices_0_full_n, + output_indices_0_write, + output_indices_1_din, + output_indices_1_full_n, + output_indices_1_write, + resetMaximum_din, + resetMaximum_full_n, + resetMaximum_write, + storeOutput_din, + storeOutput_full_n, + storeOutput_write, + ap_return_0, + ap_return_1 +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [7:0] input_indices_2_out_din; +input input_indices_2_out_full_n; +output input_indices_2_out_write; +output [7:0] input_indices_2_out1_din; +input input_indices_2_out1_full_n; +output input_indices_2_out1_write; +output [3:0] output_indices_0_din; +input output_indices_0_full_n; +output output_indices_0_write; +output [7:0] output_indices_1_din; +input output_indices_1_full_n; +output output_indices_1_write; +output resetMaximum_din; +input resetMaximum_full_n; +output resetMaximum_write; +output storeOutput_din; +input storeOutput_full_n; +output storeOutput_write; +output [15:0] ap_return_0; +output [15:0] ap_return_1; + +reg ap_done; +reg ap_idle; +reg start_write; +reg input_indices_2_out_write; +reg input_indices_2_out1_write; +reg output_indices_0_write; +reg output_indices_1_write; +reg resetMaximum_write; +reg storeOutput_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [1:0] i_p; +reg [1:0] j_p; +reg [15:0] i_8; +reg [15:0] j_8; +reg [15:0] k_8; +reg [15:0] i_out; +reg [15:0] j_out; +reg input_indices_2_out_blk_n; +reg input_indices_2_out1_blk_n; +reg output_indices_0_blk_n; +reg output_indices_1_blk_n; +reg resetMaximum_blk_n; +reg storeOutput_blk_n; +wire [1:0] select_ln142_fu_336_p3; +reg ap_block_state1; +wire [0:0] or_ln142_fu_310_p2; +wire [1:0] select_ln142_1_fu_344_p3; +wire [15:0] select_ln147_fu_276_p3; +wire [0:0] and_ln142_1_fu_304_p2; +wire [15:0] select_ln142_2_fu_358_p3; +wire [0:0] and_ln132_fu_352_p2; +wire [15:0] select_ln142_3_fu_386_p3; +wire [0:0] and_ln135_fu_292_p2; +wire [15:0] select_ln147_1_fu_284_p3; +wire [15:0] select_ln142_4_fu_394_p3; +wire [7:0] trunc_ln128_fu_180_p1; +wire [1:0] or_ln124_fu_124_p2; +wire [0:0] icmp_ln125_fu_137_p2; +wire [0:0] icmp_ln125_1_fu_143_p2; +wire [15:0] zext_ln126_fu_112_p1; +wire [15:0] zext_ln127_fu_120_p1; +wire [1:0] add_ln131_fu_204_p2; +wire [1:0] add_ln134_fu_216_p2; +wire [15:0] add_ln137_fu_228_p2; +wire [15:0] add_ln141_fu_246_p2; +wire [15:0] add_ln146_fu_264_p2; +wire [0:0] icmp_ln147_fu_270_p2; +wire [15:0] add_ln145_fu_258_p2; +wire [0:0] icmp_ln132_fu_210_p2; +wire [0:0] icmp_ln135_fu_222_p2; +wire [0:0] icmp_ln138_fu_234_p2; +wire [0:0] icmp_ln142_fu_252_p2; +wire [0:0] and_ln142_fu_298_p2; +wire [0:0] xor_ln135_fu_316_p2; +wire [0:0] and_ln135_1_fu_322_p2; +wire [1:0] select_ln135_fu_328_p3; +wire [15:0] add_ln140_fu_240_p2; +wire [0:0] xor_ln138_fu_366_p2; +wire [0:0] and_ln138_fu_372_p2; +wire [15:0] select_ln138_fu_378_p3; +wire [15:0] add_ln126_fu_160_p2; +wire [15:0] add_ln127_fu_170_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i_p = 2'd0; +#0 j_p = 2'd0; +#0 i_8 = 16'd0; +#0 j_8 = 16'd0; +#0 k_8 = 16'd0; +#0 i_out = 16'd0; +#0 j_out = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln142_1_fu_304_p2))) begin + i_8 <= select_ln147_fu_276_p3; + i_out <= select_ln147_1_fu_284_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (or_ln142_fu_310_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i_p <= select_ln142_fu_336_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln132_fu_352_p2))) begin + j_8 <= select_ln142_2_fu_358_p3; + j_out <= select_ln142_4_fu_394_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + j_p <= select_ln142_1_fu_344_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1) & (1'd1 == and_ln135_fu_292_p2))) begin + k_8 <= select_ln142_3_fu_386_p3; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_blk_n = input_indices_2_out1_full_n; + end else begin + input_indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out1_write = 1'b1; + end else begin + input_indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_blk_n = input_indices_2_out_full_n; + end else begin + input_indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_2_out_write = 1'b1; + end else begin + input_indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_blk_n = output_indices_0_full_n; + end else begin + output_indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_0_write = 1'b1; + end else begin + output_indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_blk_n = output_indices_1_full_n; + end else begin + output_indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + output_indices_1_write = 1'b1; + end else begin + output_indices_1_write = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_blk_n = resetMaximum_full_n; + end else begin + resetMaximum_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + resetMaximum_write = 1'b1; + end else begin + resetMaximum_write = 1'b0; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_blk_n = storeOutput_full_n; + end else begin + storeOutput_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + storeOutput_write = 1'b1; + end else begin + storeOutput_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln126_fu_160_p2 = (i_8 + zext_ln126_fu_112_p1); + +assign add_ln127_fu_170_p2 = (j_8 + zext_ln127_fu_120_p1); + +assign add_ln131_fu_204_p2 = (j_p + 2'd1); + +assign add_ln134_fu_216_p2 = (i_p + 2'd1); + +assign add_ln137_fu_228_p2 = (k_8 + 16'd1); + +assign add_ln140_fu_240_p2 = (j_8 + 16'd2); + +assign add_ln141_fu_246_p2 = (j_out + 16'd1); + +assign add_ln145_fu_258_p2 = (i_8 + 16'd2); + +assign add_ln146_fu_264_p2 = (i_out + 16'd1); + +assign and_ln132_fu_352_p2 = (icmp_ln138_fu_234_p2 & and_ln135_fu_292_p2); + +assign and_ln135_1_fu_322_p2 = (xor_ln135_fu_316_p2 & icmp_ln132_fu_210_p2); + +assign and_ln135_fu_292_p2 = (icmp_ln135_fu_222_p2 & icmp_ln132_fu_210_p2); + +assign and_ln138_fu_372_p2 = (xor_ln138_fu_366_p2 & and_ln135_fu_292_p2); + +assign and_ln142_1_fu_304_p2 = (and_ln142_fu_298_p2 & and_ln135_fu_292_p2); + +assign and_ln142_fu_298_p2 = (icmp_ln142_fu_252_p2 & icmp_ln138_fu_234_p2); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (storeOutput_full_n == 1'b0) | (resetMaximum_full_n == 1'b0) | (output_indices_1_full_n == 1'b0) | (output_indices_0_full_n == 1'b0) | (input_indices_2_out1_full_n == 1'b0) | (input_indices_2_out_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign ap_return_0 = add_ln126_fu_160_p2; + +assign ap_return_1 = add_ln127_fu_170_p2; + +assign icmp_ln125_1_fu_143_p2 = ((j_p == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln125_fu_137_p2 = ((i_p == 2'd1) ? 1'b1 : 1'b0); + +assign icmp_ln132_fu_210_p2 = ((add_ln131_fu_204_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln135_fu_222_p2 = ((add_ln134_fu_216_p2 == 2'd2) ? 1'b1 : 1'b0); + +assign icmp_ln138_fu_234_p2 = ((add_ln137_fu_228_p2 == 16'd256) ? 1'b1 : 1'b0); + +assign icmp_ln142_fu_252_p2 = ((add_ln141_fu_246_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign icmp_ln147_fu_270_p2 = ((add_ln146_fu_264_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign input_indices_2_out1_din = trunc_ln128_fu_180_p1; + +assign input_indices_2_out_din = trunc_ln128_fu_180_p1; + +assign or_ln124_fu_124_p2 = (j_p | i_p); + +assign or_ln142_fu_310_p2 = (icmp_ln132_fu_210_p2 | and_ln142_1_fu_304_p2); + +assign output_indices_0_din = i_out[3:0]; + +assign output_indices_1_din = j_out[7:0]; + +assign resetMaximum_din = ((or_ln124_fu_124_p2 == 2'd0) ? 1'b1 : 1'b0); + +assign select_ln135_fu_328_p3 = ((and_ln135_1_fu_322_p2[0:0] == 1'b1) ? add_ln134_fu_216_p2 : 2'd0); + +assign select_ln138_fu_378_p3 = ((and_ln138_fu_372_p2[0:0] == 1'b1) ? add_ln137_fu_228_p2 : 16'd0); + +assign select_ln142_1_fu_344_p3 = ((or_ln142_fu_310_p2[0:0] == 1'b1) ? 2'd0 : add_ln131_fu_204_p2); + +assign select_ln142_2_fu_358_p3 = ((and_ln142_1_fu_304_p2[0:0] == 1'b1) ? 16'd0 : add_ln140_fu_240_p2); + +assign select_ln142_3_fu_386_p3 = ((and_ln142_1_fu_304_p2[0:0] == 1'b1) ? 16'd0 : select_ln138_fu_378_p3); + +assign select_ln142_4_fu_394_p3 = ((and_ln142_1_fu_304_p2[0:0] == 1'b1) ? 16'd0 : add_ln141_fu_246_p2); + +assign select_ln142_fu_336_p3 = ((and_ln142_1_fu_304_p2[0:0] == 1'b1) ? 2'd0 : select_ln135_fu_328_p3); + +assign select_ln147_1_fu_284_p3 = ((icmp_ln147_fu_270_p2[0:0] == 1'b1) ? 16'd0 : add_ln146_fu_264_p2); + +assign select_ln147_fu_276_p3 = ((icmp_ln147_fu_270_p2[0:0] == 1'b1) ? 16'd0 : add_ln145_fu_258_p2); + +assign start_out = real_start; + +assign storeOutput_din = (icmp_ln125_fu_137_p2 & icmp_ln125_1_fu_143_p2); + +assign trunc_ln128_fu_180_p1 = k_8[7:0]; + +assign xor_ln135_fu_316_p2 = (icmp_ln135_fu_222_p2 ^ 1'd1); + +assign xor_ln138_fu_366_p2 = (icmp_ln138_fu_234_p2 ^ 1'd1); + +assign zext_ln126_fu_112_p1 = i_p; + +assign zext_ln127_fu_120_p1 = j_p; + +endmodule //td_fused_top_tdf8_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_poolOutputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + output_indices_04_dout, + output_indices_04_empty_n, + output_indices_04_read, + output_indices_15_dout, + output_indices_15_empty_n, + output_indices_15_read, + resetMaximum6_dout, + resetMaximum6_empty_n, + resetMaximum6_read, + storeOutput7_dout, + storeOutput7_empty_n, + storeOutput7_read, + p_read, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_state2 = 4'd2; +parameter ap_ST_fsm_state3 = 4'd4; +parameter ap_ST_fsm_state4 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [3:0] output_indices_04_dout; +input output_indices_04_empty_n; +output output_indices_04_read; +input [7:0] output_indices_15_dout; +input output_indices_15_empty_n; +output output_indices_15_read; +input [0:0] resetMaximum6_dout; +input resetMaximum6_empty_n; +output resetMaximum6_read; +input [0:0] storeOutput7_dout; +input storeOutput7_empty_n; +output storeOutput7_read; +input [15:0] p_read; +output [13:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg output_indices_04_read; +reg output_indices_15_read; +reg resetMaximum6_read; +reg storeOutput7_read; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] max_vals_0; +reg output_indices_04_blk_n; +wire ap_CS_fsm_state2; +reg output_indices_15_blk_n; +reg resetMaximum6_blk_n; +reg storeOutput7_blk_n; +reg [3:0] output_indices_04_read_reg_147; +reg [7:0] output_indices_15_read_reg_152; +wire [0:0] storeOutput7_read_read_fu_82_p2; +reg [0:0] storeOutput7_read_reg_157; +wire grp_tdf8_writeOutputs_unaligned_fu_88_ap_start; +wire grp_tdf8_writeOutputs_unaligned_fu_88_ap_done; +wire grp_tdf8_writeOutputs_unaligned_fu_88_ap_idle; +wire grp_tdf8_writeOutputs_unaligned_fu_88_ap_ready; +wire [13:0] grp_tdf8_writeOutputs_unaligned_fu_88_out_data_address1; +wire grp_tdf8_writeOutputs_unaligned_fu_88_out_data_ce1; +wire grp_tdf8_writeOutputs_unaligned_fu_88_out_data_we1; +wire [63:0] grp_tdf8_writeOutputs_unaligned_fu_88_out_data_d1; +reg grp_tdf8_writeOutputs_unaligned_fu_88_ap_start_reg; +wire ap_CS_fsm_state3; +wire ap_CS_fsm_state4; +reg ap_block_state4_on_subcall_done; +wire [15:0] select_ln24_fu_126_p3; +reg ap_block_state2; +reg ap_block_state1; +wire [0:0] grp_fu_110_p2; +wire [0:0] or_ln24_fu_120_p2; +reg grp_fu_110_ce; +reg [3:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 max_vals_0 = 16'd0; +#0 grp_tdf8_writeOutputs_unaligned_fu_88_ap_start_reg = 1'b0; +end + +td_fused_top_tdf8_writeOutputs_unaligned grp_tdf8_writeOutputs_unaligned_fu_88( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(grp_tdf8_writeOutputs_unaligned_fu_88_ap_start), + .ap_done(grp_tdf8_writeOutputs_unaligned_fu_88_ap_done), + .ap_idle(grp_tdf8_writeOutputs_unaligned_fu_88_ap_idle), + .ap_ready(grp_tdf8_writeOutputs_unaligned_fu_88_ap_ready), + .i(output_indices_04_read_reg_147), + .j(output_indices_15_read_reg_152), + .out_data_address1(grp_tdf8_writeOutputs_unaligned_fu_88_out_data_address1), + .out_data_ce1(grp_tdf8_writeOutputs_unaligned_fu_88_out_data_ce1), + .out_data_we1(grp_tdf8_writeOutputs_unaligned_fu_88_out_data_we1), + .out_data_d1(grp_tdf8_writeOutputs_unaligned_fu_88_out_data_d1), + .max_vals_0(max_vals_0) +); + +td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 2 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 1 )) +hcmp_16ns_16ns_1_2_no_dsp_1_U516( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_110_ce), + .din0(max_vals_0), + .din1(p_read), + .opcode(5'd4), + .dout(grp_fu_110_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + grp_tdf8_writeOutputs_unaligned_fu_88_ap_start_reg <= 1'b0; + end else begin + if ((1'b1 == ap_CS_fsm_state3)) begin + grp_tdf8_writeOutputs_unaligned_fu_88_ap_start_reg <= 1'b1; + end else if ((grp_tdf8_writeOutputs_unaligned_fu_88_ap_ready == 1'b1)) begin + grp_tdf8_writeOutputs_unaligned_fu_88_ap_start_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + max_vals_0 <= select_ln24_fu_126_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_04_read_reg_147 <= output_indices_04_dout; + output_indices_15_read_reg_152 <= output_indices_15_dout; + storeOutput7_read_reg_157 <= storeOutput7_dout; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)) | (~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2)))) begin + grp_fu_110_ce = 1'b1; + end else begin + grp_fu_110_ce = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_04_blk_n = output_indices_04_empty_n; + end else begin + output_indices_04_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_04_read = 1'b1; + end else begin + output_indices_04_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + output_indices_15_blk_n = output_indices_15_empty_n; + end else begin + output_indices_15_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + output_indices_15_read = 1'b1; + end else begin + output_indices_15_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + resetMaximum6_blk_n = resetMaximum6_empty_n; + end else begin + resetMaximum6_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + resetMaximum6_read = 1'b1; + end else begin + resetMaximum6_read = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + storeOutput7_blk_n = storeOutput7_empty_n; + end else begin + storeOutput7_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (1'b1 == ap_CS_fsm_state2))) begin + storeOutput7_read = 1'b1; + end else begin + storeOutput7_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_82_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state4; + end else if ((~((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)) & (storeOutput7_read_read_fu_82_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state3; + end else begin + ap_NS_fsm = ap_ST_fsm_state2; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + if (((1'b1 == ap_CS_fsm_state4) & (1'b0 == ap_block_state4_on_subcall_done))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +always @ (*) begin + ap_block_state2 = ((storeOutput7_empty_n == 1'b0) | (resetMaximum6_empty_n == 1'b0) | (output_indices_15_empty_n == 1'b0) | (output_indices_04_empty_n == 1'b0)); +end + +always @ (*) begin + ap_block_state4_on_subcall_done = ((grp_tdf8_writeOutputs_unaligned_fu_88_ap_done == 1'b0) & (storeOutput7_read_reg_157 == 1'd1)); +end + +assign grp_tdf8_writeOutputs_unaligned_fu_88_ap_start = grp_tdf8_writeOutputs_unaligned_fu_88_ap_start_reg; + +assign or_ln24_fu_120_p2 = (resetMaximum6_dout | grp_fu_110_p2); + +assign out_data_address1 = grp_tdf8_writeOutputs_unaligned_fu_88_out_data_address1; + +assign out_data_ce1 = grp_tdf8_writeOutputs_unaligned_fu_88_out_data_ce1; + +assign out_data_d1 = grp_tdf8_writeOutputs_unaligned_fu_88_out_data_d1; + +assign out_data_we1 = grp_tdf8_writeOutputs_unaligned_fu_88_out_data_we1; + +assign select_ln24_fu_126_p3 = ((or_ln24_fu_120_p2[0:0] == 1'b1) ? p_read : max_vals_0); + +assign storeOutput7_read_read_fu_82_p2 = storeOutput7_dout; + +endmodule //td_fused_top_tdf8_poolOutputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_readFilters56 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + input_indices_23_dout, + input_indices_23_empty_n, + input_indices_23_read, + weight_vecs_0_address0, + weight_vecs_0_ce0, + weight_vecs_0_we0, + weight_vecs_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state7 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [16:0] filter_data_address0; +output filter_data_ce0; +input [15:0] filter_data_q0; +input [7:0] input_indices_23_dout; +input input_indices_23_empty_n; +output input_indices_23_read; +output [8:0] weight_vecs_0_address0; +output weight_vecs_0_ce0; +output weight_vecs_0_we0; +output [15:0] weight_vecs_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg input_indices_23_read; +reg weight_vecs_0_ce0; +reg weight_vecs_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg input_indices_23_blk_n; +reg [8:0] indvar_flatten13_reg_123; +reg [1:0] ii_reg_134; +reg [7:0] indvar_flatten_reg_145; +reg [1:0] jj_reg_156; +reg [5:0] kk_reg_167; +wire [11:0] sext_ln47_fu_200_p1; +reg [11:0] sext_ln47_reg_408; +wire [8:0] add_ln47_1_fu_204_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln47_fu_210_p2; +reg [0:0] icmp_ln47_reg_418; +reg [0:0] icmp_ln47_reg_418_pp0_iter1_reg; +reg [0:0] icmp_ln47_reg_418_pp0_iter2_reg; +reg [0:0] icmp_ln47_reg_418_pp0_iter3_reg; +wire [0:0] icmp_ln48_fu_222_p2; +reg [0:0] icmp_ln48_reg_422; +wire [1:0] select_ln47_1_fu_228_p3; +reg [1:0] select_ln47_1_reg_429; +wire [7:0] select_ln48_2_fu_242_p3; +wire [1:0] select_ln48_1_fu_329_p3; +reg [1:0] select_ln48_1_reg_442; +reg ap_enable_reg_pp0_iter1; +wire [8:0] add_ln55_4_fu_392_p2; +reg [8:0] add_ln55_4_reg_452; +reg [8:0] add_ln55_4_reg_452_pp0_iter2_reg; +reg [8:0] add_ln55_4_reg_452_pp0_iter3_reg; +wire [5:0] add_ln49_fu_398_p2; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_enable_reg_pp0_iter2; +reg ap_condition_pp0_exit_iter1_state3; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg [1:0] ap_phi_mux_ii_phi_fu_138_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_jj_phi_fu_160_p4; +wire [63:0] zext_ln55_9_fu_387_p1; +wire [63:0] zext_ln55_10_fu_404_p1; +wire [9:0] tmp_fu_182_p3; +wire [10:0] zext_ln55_2_fu_190_p1; +wire [10:0] zext_ln55_fu_178_p1; +wire [10:0] sub_ln55_fu_194_p2; +wire [1:0] add_ln47_fu_216_p2; +wire [7:0] add_ln48_1_fu_236_p2; +wire [11:0] zext_ln55_4_fu_260_p1; +wire [11:0] add_ln55_fu_263_p2; +wire [11:0] shl_ln55_fu_268_p2; +wire [3:0] tmp_s_fu_280_p3; +wire [3:0] zext_ln55_3_fu_257_p1; +wire [0:0] icmp_ln49_fu_298_p2; +wire [0:0] xor_ln47_fu_293_p2; +wire [1:0] select_ln47_fu_250_p3; +wire [0:0] and_ln47_fu_304_p2; +wire [0:0] or_ln48_fu_316_p2; +wire [1:0] add_ln48_fu_310_p2; +wire [11:0] sub_ln55_1_fu_274_p2; +wire [11:0] zext_ln55_6_fu_341_p1; +wire [11:0] add_ln55_1_fu_345_p2; +wire [3:0] sub_ln55_2_fu_287_p2; +wire [3:0] zext_ln55_5_fu_337_p1; +wire [3:0] add_ln55_2_fu_359_p2; +wire [5:0] select_ln48_fu_321_p3; +wire [16:0] tmp_24_cast_fu_351_p3; +wire [16:0] zext_ln55_8_fu_377_p1; +wire [16:0] add_ln55_3_fu_381_p2; +wire [8:0] tmp_26_cast_fu_365_p3; +wire [8:0] zext_ln55_7_fu_373_p1; +wire ap_CS_fsm_state7; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter1_state3)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter0; + end else begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ii_reg_134 <= select_ln47_1_reg_429; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_134 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten13_reg_123 <= add_ln47_1_fu_204_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_123 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_145 <= select_ln48_2_fu_242_p3; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_145 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_418_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + jj_reg_156 <= select_ln48_1_reg_442; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_156 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + kk_reg_167 <= add_ln49_fu_398_p2; + end else if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_reg_167 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln55_4_reg_452 <= add_ln55_4_fu_392_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + add_ln55_4_reg_452_pp0_iter2_reg <= add_ln55_4_reg_452; + add_ln55_4_reg_452_pp0_iter3_reg <= add_ln55_4_reg_452_pp0_iter2_reg; + icmp_ln47_reg_418_pp0_iter2_reg <= icmp_ln47_reg_418_pp0_iter1_reg; + icmp_ln47_reg_418_pp0_iter3_reg <= icmp_ln47_reg_418_pp0_iter2_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln47_reg_418 <= icmp_ln47_fu_210_p2; + icmp_ln47_reg_418_pp0_iter1_reg <= icmp_ln47_reg_418; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln48_reg_422 <= icmp_ln48_fu_222_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln47_fu_210_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln47_1_reg_429 <= select_ln47_1_fu_228_p3; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln48_1_reg_442 <= select_ln48_1_fu_329_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + sext_ln47_reg_408 <= sext_ln47_fu_200_p1; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_condition_pp0_exit_iter1_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter1_state3 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln47_fu_210_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln47_reg_418 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_ii_phi_fu_138_p4 = select_ln47_1_reg_429; + end else begin + ap_phi_mux_ii_phi_fu_138_p4 = ii_reg_134; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_418_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_160_p4 = select_ln48_1_reg_442; + end else begin + ap_phi_mux_jj_phi_fu_160_p4 = jj_reg_156; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state7)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_blk_n = input_indices_23_empty_n; + end else begin + input_indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + input_indices_23_read = 1'b1; + end else begin + input_indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + weight_vecs_0_ce0 = 1'b1; + end else begin + weight_vecs_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln47_reg_418_pp0_iter3_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1))) begin + weight_vecs_0_we0 = 1'b1; + end else begin + weight_vecs_0_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_enable_reg_pp0_iter3 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state7; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln47_1_fu_204_p2 = (indvar_flatten13_reg_123 + 9'd1); + +assign add_ln47_fu_216_p2 = (ap_phi_mux_ii_phi_fu_138_p4 + 2'd1); + +assign add_ln48_1_fu_236_p2 = (indvar_flatten_reg_145 + 8'd1); + +assign add_ln48_fu_310_p2 = (select_ln47_fu_250_p3 + 2'd1); + +assign add_ln49_fu_398_p2 = (select_ln48_fu_321_p3 + 6'd1); + +assign add_ln55_1_fu_345_p2 = (sub_ln55_1_fu_274_p2 + zext_ln55_6_fu_341_p1); + +assign add_ln55_2_fu_359_p2 = (sub_ln55_2_fu_287_p2 + zext_ln55_5_fu_337_p1); + +assign add_ln55_3_fu_381_p2 = (tmp_24_cast_fu_351_p3 + zext_ln55_8_fu_377_p1); + +assign add_ln55_4_fu_392_p2 = (tmp_26_cast_fu_365_p3 + zext_ln55_7_fu_373_p1); + +assign add_ln55_fu_263_p2 = ((sext_ln47_reg_408) + (zext_ln55_4_fu_260_p1)); + +assign and_ln47_fu_304_p2 = (xor_ln47_fu_293_p2 & icmp_ln49_fu_298_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (input_indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_address0 = zext_ln55_9_fu_387_p1; + +assign icmp_ln47_fu_210_p2 = ((indvar_flatten13_reg_123 == 9'd288) ? 1'b1 : 1'b0); + +assign icmp_ln48_fu_222_p2 = ((indvar_flatten_reg_145 == 8'd96) ? 1'b1 : 1'b0); + +assign icmp_ln49_fu_298_p2 = ((kk_reg_167 == 6'd32) ? 1'b1 : 1'b0); + +assign or_ln48_fu_316_p2 = (icmp_ln48_reg_422 | and_ln47_fu_304_p2); + +assign select_ln47_1_fu_228_p3 = ((icmp_ln48_fu_222_p2[0:0] == 1'b1) ? add_ln47_fu_216_p2 : ap_phi_mux_ii_phi_fu_138_p4); + +assign select_ln47_fu_250_p3 = ((icmp_ln48_reg_422[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_160_p4); + +assign select_ln48_1_fu_329_p3 = ((and_ln47_fu_304_p2[0:0] == 1'b1) ? add_ln48_fu_310_p2 : select_ln47_fu_250_p3); + +assign select_ln48_2_fu_242_p3 = ((icmp_ln48_fu_222_p2[0:0] == 1'b1) ? 8'd1 : add_ln48_1_fu_236_p2); + +assign select_ln48_fu_321_p3 = ((or_ln48_fu_316_p2[0:0] == 1'b1) ? 6'd0 : kk_reg_167); + +assign sext_ln47_fu_200_p1 = (sub_ln55_fu_194_p2); + +assign shl_ln55_fu_268_p2 = add_ln55_fu_263_p2 << 12'd2; + +assign sub_ln55_1_fu_274_p2 = (shl_ln55_fu_268_p2 - add_ln55_fu_263_p2); + +assign sub_ln55_2_fu_287_p2 = (tmp_s_fu_280_p3 - zext_ln55_3_fu_257_p1); + +assign sub_ln55_fu_194_p2 = (zext_ln55_2_fu_190_p1 - zext_ln55_fu_178_p1); + +assign tmp_24_cast_fu_351_p3 = {{add_ln55_1_fu_345_p2}, {5'd0}}; + +assign tmp_26_cast_fu_365_p3 = {{add_ln55_2_fu_359_p2}, {5'd0}}; + +assign tmp_fu_182_p3 = {{input_indices_23_dout}, {2'd0}}; + +assign tmp_s_fu_280_p3 = {{select_ln47_1_reg_429}, {2'd0}}; + +assign weight_vecs_0_address0 = zext_ln55_10_fu_404_p1; + +assign weight_vecs_0_d0 = filter_data_q0; + +assign xor_ln47_fu_293_p2 = (icmp_ln48_reg_422 ^ 1'd1); + +assign zext_ln55_10_fu_404_p1 = add_ln55_4_reg_452_pp0_iter3_reg; + +assign zext_ln55_2_fu_190_p1 = tmp_fu_182_p3; + +assign zext_ln55_3_fu_257_p1 = select_ln47_1_reg_429; + +assign zext_ln55_4_fu_260_p1 = select_ln47_1_reg_429; + +assign zext_ln55_5_fu_337_p1 = select_ln48_1_fu_329_p3; + +assign zext_ln55_6_fu_341_p1 = select_ln48_1_fu_329_p3; + +assign zext_ln55_7_fu_373_p1 = select_ln48_fu_321_p3; + +assign zext_ln55_8_fu_377_p1 = select_ln48_fu_321_p3; + +assign zext_ln55_9_fu_387_p1 = add_ln55_3_fu_381_p2; + +assign zext_ln55_fu_178_p1 = input_indices_23_dout; + +endmodule //td_fused_top_tdf8_readFilters56 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_readInputs57 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + i_13, + j_13, + ifmap_vec_address0, + ifmap_vec_ce0, + ifmap_vec_we0, + ifmap_vec_d0, + ifmap_vec_address1, + ifmap_vec_ce1, + ifmap_vec_we1, + ifmap_vec_d1 +); + +parameter ap_ST_fsm_state1 = 4'd1; +parameter ap_ST_fsm_pp0_stage0 = 4'd2; +parameter ap_ST_fsm_pp0_stage1 = 4'd4; +parameter ap_ST_fsm_state8 = 4'd8; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [12:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] i_13; +input [15:0] j_13; +output [8:0] ifmap_vec_address0; +output ifmap_vec_ce0; +output ifmap_vec_we0; +output [15:0] ifmap_vec_d0; +output [8:0] ifmap_vec_address1; +output ifmap_vec_ce1; +output ifmap_vec_we1; +output [15:0] ifmap_vec_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg[8:0] ifmap_vec_address0; +reg ifmap_vec_ce0; +reg ifmap_vec_we0; +reg[15:0] ifmap_vec_d0; +reg[8:0] ifmap_vec_address1; +reg ifmap_vec_ce1; +reg ifmap_vec_we1; +reg[15:0] ifmap_vec_d1; + +reg ap_done_reg; + reg [3:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [6:0] indvar_flatten47_reg_192; +reg [1:0] ii_reg_204; +reg [5:0] indvar_flatten_reg_216; +reg [1:0] jj_reg_227; +reg [5:0] kk_0_i_reg_239; +wire [17:0] p_cast_i_fu_268_p1; +reg [17:0] p_cast_i_reg_929; +wire [9:0] trunc_ln22_fu_272_p1; +reg [9:0] trunc_ln22_reg_935; +wire [17:0] sext_ln22_fu_282_p1; +reg [17:0] sext_ln22_reg_941; +wire [4:0] p_cast_fu_286_p2; +reg [4:0] p_cast_reg_947; +wire [0:0] or_ln23_1_fu_306_p2; +reg [0:0] or_ln23_1_reg_953; +wire [9:0] p_mid137_fu_312_p2; +reg [9:0] p_mid137_reg_958; +wire [4:0] p_cast5_i_fu_331_p2; +reg [4:0] p_cast5_i_reg_963; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state4_pp0_stage0_iter1; +wire ap_block_state6_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [0:0] is_padding_fu_371_p2; +reg [0:0] is_padding_reg_969; +wire [0:0] icmp_ln19_fu_377_p2; +reg [0:0] icmp_ln19_reg_976; +reg [0:0] icmp_ln19_reg_976_pp0_iter1_reg; +reg [0:0] icmp_ln19_reg_976_pp0_iter2_reg; +wire [1:0] add_ln19_fu_383_p2; +reg [1:0] add_ln19_reg_980; +wire [0:0] icmp_ln20_fu_389_p2; +reg [0:0] icmp_ln20_reg_985; +wire [1:0] select_ln19_fu_395_p3; +reg [1:0] select_ln19_reg_997; +wire [4:0] p_cast5_i_mid1_fu_416_p2; +reg [4:0] p_cast5_i_mid1_reg_1002; +wire [0:0] or_ln23_3_fu_435_p2; +reg [0:0] or_ln23_3_reg_1008; +wire [1:0] add_ln20_fu_440_p2; +reg [1:0] add_ln20_reg_1015; +wire [0:0] or_ln23_5_fu_475_p2; +reg [0:0] or_ln23_5_reg_1021; +wire [5:0] add_ln20_1_fu_481_p2; +reg [5:0] add_ln20_1_reg_1028; +wire [6:0] add_ln19_1_fu_487_p2; +reg [6:0] add_ln19_1_reg_1033; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state5_pp0_stage1_iter1; +wire ap_block_state7_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +wire [1:0] select_ln19_1_fu_525_p3; +reg [1:0] select_ln19_1_reg_1038; +wire [5:0] select_ln20_fu_589_p3; +reg [5:0] select_ln20_reg_1045; +wire [1:0] select_ln20_1_fu_597_p3; +reg [1:0] select_ln20_1_reg_1051; +wire [0:0] select_ln20_2_fu_606_p3; +reg [0:0] select_ln20_2_reg_1057; +reg [0:0] select_ln20_2_reg_1057_pp0_iter1_reg; +wire [4:0] empty_63_fu_702_p1; +reg [4:0] empty_63_reg_1065; +reg [4:0] empty_63_reg_1065_pp0_iter1_reg; +wire [5:0] select_ln20_5_fu_729_p3; +reg [5:0] select_ln20_5_reg_1077; +wire [5:0] add_ln25_fu_735_p2; +reg [5:0] add_ln25_reg_1082; +reg ap_enable_reg_pp0_iter1; +wire [5:0] add_ln33_fu_767_p2; +reg [5:0] add_ln33_reg_1087; +wire [8:0] add_ln33_1_fu_788_p2; +reg [8:0] add_ln33_1_reg_1094; +wire [15:0] select_ln33_5_fu_867_p3; +reg [15:0] select_ln33_5_reg_1099; +wire [15:0] select_ln33_6_fu_888_p3; +reg [15:0] select_ln33_6_reg_1104; +reg ap_block_state1; +wire ap_block_pp0_stage1_subdone; +reg ap_condition_pp0_exit_iter0_state3; +reg ap_enable_reg_pp0_iter2; +reg [6:0] ap_phi_mux_indvar_flatten47_phi_fu_196_p4; +wire ap_block_pp0_stage0; +reg [1:0] ap_phi_mux_ii_phi_fu_208_p4; +reg [5:0] ap_phi_mux_indvar_flatten_phi_fu_220_p4; +reg [1:0] ap_phi_mux_jj_phi_fu_231_p4; +reg [5:0] ap_phi_mux_kk_0_i_phi_fu_243_p4; +wire ap_block_pp0_stage1; +wire [63:0] sext_ln32_fu_724_p1; +wire [63:0] zext_ln33_5_fu_794_p1; +wire [63:0] sext_ln33_fu_826_p1; +wire [63:0] sext_ln33_1_fu_907_p1; +wire [63:0] sext_ln33_2_fu_924_p1; +wire [15:0] select_ln33_fu_806_p3; +wire [15:0] select_ln33_4_fu_845_p3; +wire [16:0] zext_ln19_fu_254_p1; +wire [16:0] empty_58_fu_262_p2; +wire [16:0] j_cast_i_fu_250_p1; +wire [16:0] add_ln22_fu_276_p2; +wire [4:0] empty_fu_258_p1; +wire [0:0] tmp_fu_292_p3; +wire [0:0] icmp_ln24_fu_300_p2; +wire [17:0] ii_cast_i_fu_318_p1; +wire [4:0] ii_cast_fu_322_p1; +wire [17:0] empty_59_fu_326_p2; +wire [17:0] zext_ln20_fu_342_p1; +wire [17:0] add_ln22_1_fu_346_p2; +wire [0:0] tmp_3_fu_351_p3; +wire [0:0] icmp_ln24_1_fu_359_p2; +wire [0:0] or_ln23_fu_365_p2; +wire [0:0] empty_60_fu_336_p2; +wire [17:0] ii_cast_i_mid1_fu_403_p1; +wire [4:0] ii_cast_mid1_fu_407_p1; +wire [17:0] p_mid111_fu_411_p2; +wire [0:0] p_mid113_fu_421_p2; +wire [17:0] zext_ln20_1_fu_446_p1; +wire [17:0] add_ln22_2_fu_450_p2; +wire [0:0] tmp_4_fu_455_p3; +wire [0:0] icmp_ln24_2_fu_463_p2; +wire [0:0] or_ln23_4_fu_469_p2; +wire [0:0] select_ln19_3_fu_427_p3; +wire [2:0] zext_ln22_fu_493_p1; +wire [2:0] tmp2_fu_503_p2; +wire [9:0] tmp2_cast_fu_509_p1; +wire [9:0] empty_61_fu_513_p2; +wire [4:0] row_coord_int_mid131_fu_541_p3; +wire [4:0] row_coord_int_fu_497_p3; +wire [9:0] col_coord_int_mid139_fu_547_p3; +wire [9:0] col_coord_int_fu_518_p3; +wire [0:0] icmp_ln25_fu_572_p2; +wire [0:0] xor_ln19_fu_567_p2; +wire [0:0] and_ln19_fu_578_p2; +wire [0:0] or_ln20_fu_584_p2; +wire [0:0] select_ln19_4_fu_536_p3; +wire [4:0] select_ln19_2_fu_531_p3; +wire [2:0] zext_ln22_1_fu_603_p1; +wire [2:0] tmp2_mid1_fu_620_p2; +wire [9:0] tmp2_cast_mid1_fu_626_p1; +wire [9:0] p_mid1_fu_630_p2; +wire [4:0] row_coord_int_mid1_fu_613_p3; +wire [4:0] select_ln19_5_fu_553_p3; +wire [4:0] select_ln20_3_fu_642_p3; +wire [9:0] tmp_1_fu_650_p3; +wire [6:0] tmp_2_fu_662_p3; +wire [10:0] zext_ln32_fu_658_p1; +wire [10:0] zext_ln32_7_fu_670_p1; +wire [10:0] sub_ln32_fu_674_p2; +wire [9:0] col_coord_int_mid1_fu_635_p3; +wire [9:0] select_ln19_6_fu_560_p3; +wire [9:0] select_ln20_4_fu_684_p3; +wire [11:0] sext_ln20_fu_680_p1; +wire [11:0] zext_ln32_8_fu_692_p1; +wire [11:0] add_ln32_fu_696_p2; +wire [2:0] lshr_ln_fu_706_p4; +wire [14:0] tmp_5_fu_716_p3; +wire [3:0] tmp_s_fu_743_p3; +wire [4:0] zext_ln33_2_fu_750_p1; +wire [4:0] zext_ln33_fu_740_p1; +wire [4:0] sub_ln33_fu_754_p2; +wire [5:0] sub_ln33_cast_fu_760_p1; +wire [5:0] zext_ln33_3_fu_764_p1; +wire [3:0] trunc_ln33_fu_773_p1; +wire [8:0] tmp_13_cast_fu_777_p3; +wire [8:0] zext_ln33_4_fu_785_p1; +wire [15:0] trunc_ln32_fu_798_p1; +wire [15:0] bitcast_ln32_fu_802_p1; +wire [4:0] or_ln25_fu_814_p2; +wire [10:0] tmp_6_fu_819_p3; +wire [15:0] tmp_12_i_fu_831_p4; +wire [15:0] bitcast_ln32_4_fu_841_p1; +wire [15:0] tmp_13_i_fu_853_p4; +wire [15:0] bitcast_ln32_5_fu_863_p1; +wire [15:0] tmp_14_i_fu_874_p4; +wire [15:0] bitcast_ln32_6_fu_884_p1; +wire [4:0] or_ln25_3_fu_895_p2; +wire [10:0] tmp_7_fu_900_p3; +wire [4:0] or_ln25_4_fu_912_p2; +wire [10:0] tmp_8_fu_917_p3; +wire ap_CS_fsm_state8; +reg [3:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 4'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state3) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state3)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state3); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ii_reg_204 <= select_ln19_1_reg_1038; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ii_reg_204 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + indvar_flatten47_reg_192 <= add_ln19_1_reg_1033; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten47_reg_192 <= 7'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + indvar_flatten_reg_216 <= select_ln20_5_reg_1077; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_216 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + jj_reg_227 <= select_ln20_1_reg_1051; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + jj_reg_227 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_976_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_i_reg_239 <= add_ln25_reg_1082; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_0_i_reg_239 <= 6'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln19_1_reg_1033 <= add_ln19_1_fu_487_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_fu_377_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln19_reg_980 <= add_ln19_fu_383_p2; + add_ln20_1_reg_1028 <= add_ln20_1_fu_481_p2; + add_ln20_reg_1015 <= add_ln20_fu_440_p2; + icmp_ln20_reg_985 <= icmp_ln20_fu_389_p2; + or_ln23_3_reg_1008 <= or_ln23_3_fu_435_p2; + or_ln23_5_reg_1021 <= or_ln23_5_fu_475_p2; + p_cast5_i_mid1_reg_1002 <= p_cast5_i_mid1_fu_416_p2; + select_ln19_reg_997 <= select_ln19_fu_395_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + add_ln25_reg_1082 <= add_ln25_fu_735_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_976_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + add_ln33_1_reg_1094 <= add_ln33_1_fu_788_p2; + add_ln33_reg_1087 <= add_ln33_fu_767_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + empty_63_reg_1065 <= empty_63_fu_702_p1; + select_ln20_2_reg_1057 <= select_ln20_2_fu_606_p3; + select_ln20_reg_1045 <= select_ln20_fu_589_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + empty_63_reg_1065_pp0_iter1_reg <= empty_63_reg_1065; + select_ln20_2_reg_1057_pp0_iter1_reg <= select_ln20_2_reg_1057; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln19_reg_976 <= icmp_ln19_fu_377_p2; + icmp_ln19_reg_976_pp0_iter1_reg <= icmp_ln19_reg_976; + icmp_ln19_reg_976_pp0_iter2_reg <= icmp_ln19_reg_976_pp0_iter1_reg; + is_padding_reg_969 <= is_padding_fu_371_p2; + p_cast5_i_reg_963 <= p_cast5_i_fu_331_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + or_ln23_1_reg_953 <= or_ln23_1_fu_306_p2; + p_cast_i_reg_929 <= p_cast_i_fu_268_p1; + p_cast_reg_947 <= p_cast_fu_286_p2; + p_mid137_reg_958 <= p_mid137_fu_312_p2; + sext_ln22_reg_941 <= sext_ln22_fu_282_p1; + trunc_ln22_reg_935 <= trunc_ln22_fu_272_p1; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln19_1_reg_1038 <= select_ln19_1_fu_525_p3; + select_ln20_1_reg_1051 <= select_ln20_1_fu_597_p3; + select_ln20_5_reg_1077 <= select_ln20_5_fu_729_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln19_reg_976_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + select_ln33_5_reg_1099 <= select_ln33_5_fu_867_p3; + select_ln33_6_reg_1104 <= select_ln33_6_fu_888_p3; + end +end + +always @ (*) begin + if ((icmp_ln19_reg_976 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_ii_phi_fu_208_p4 = select_ln19_1_reg_1038; + end else begin + ap_phi_mux_ii_phi_fu_208_p4 = ii_reg_204; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_indvar_flatten47_phi_fu_196_p4 = add_ln19_1_reg_1033; + end else begin + ap_phi_mux_indvar_flatten47_phi_fu_196_p4 = indvar_flatten47_reg_192; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_indvar_flatten_phi_fu_220_p4 = select_ln20_5_reg_1077; + end else begin + ap_phi_mux_indvar_flatten_phi_fu_220_p4 = indvar_flatten_reg_216; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_976 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_jj_phi_fu_231_p4 = select_ln20_1_reg_1051; + end else begin + ap_phi_mux_jj_phi_fu_231_p4 = jj_reg_227; + end +end + +always @ (*) begin + if (((icmp_ln19_reg_976_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_i_phi_fu_243_p4 = add_ln25_reg_1082; + end else begin + ap_phi_mux_kk_0_i_phi_fu_243_p4 = kk_0_i_reg_239; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_address0 = sext_ln33_2_fu_924_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_address0 = sext_ln33_fu_826_p1; + end else begin + ifmap_vec_address0 = 'bx; + end + end else begin + ifmap_vec_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_address1 = sext_ln33_1_fu_907_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_address1 = zext_ln33_5_fu_794_p1; + end else begin + ifmap_vec_address1 = 'bx; + end + end else begin + ifmap_vec_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + ifmap_vec_ce0 = 1'b1; + end else begin + ifmap_vec_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + ifmap_vec_ce1 = 1'b1; + end else begin + ifmap_vec_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_d0 = select_ln33_6_reg_1104; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_d0 = select_ln33_4_fu_845_p3; + end else begin + ifmap_vec_d0 = 'bx; + end + end else begin + ifmap_vec_d0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter2 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ifmap_vec_d1 = select_ln33_5_reg_1099; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_d1 = select_ln33_fu_806_p3; + end else begin + ifmap_vec_d1 = 'bx; + end + end else begin + ifmap_vec_d1 = 'bx; + end +end + +always @ (*) begin + if ((((icmp_ln19_reg_976_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((icmp_ln19_reg_976_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + ifmap_vec_we0 = 1'b1; + end else begin + ifmap_vec_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((icmp_ln19_reg_976_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((icmp_ln19_reg_976_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + ifmap_vec_we1 = 1'b1; + end else begin + ifmap_vec_we1 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((icmp_ln19_reg_976 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln19_reg_976 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state8; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln19_1_fu_487_p2 = (indvar_flatten47_reg_192 + 7'd1); + +assign add_ln19_fu_383_p2 = (ap_phi_mux_ii_phi_fu_208_p4 + 2'd1); + +assign add_ln20_1_fu_481_p2 = (ap_phi_mux_indvar_flatten_phi_fu_220_p4 + 6'd1); + +assign add_ln20_fu_440_p2 = (select_ln19_fu_395_p3 + 2'd1); + +assign add_ln22_1_fu_346_p2 = ((sext_ln22_reg_941) + (zext_ln20_fu_342_p1)); + +assign add_ln22_2_fu_450_p2 = ((sext_ln22_reg_941) + (zext_ln20_1_fu_446_p1)); + +assign add_ln22_fu_276_p2 = ((j_cast_i_fu_250_p1) + (17'd131071)); + +assign add_ln25_fu_735_p2 = (select_ln20_reg_1045 + 6'd4); + +assign add_ln32_fu_696_p2 = ((sext_ln20_fu_680_p1) + (zext_ln32_8_fu_692_p1)); + +assign add_ln33_1_fu_788_p2 = (tmp_13_cast_fu_777_p3 + zext_ln33_4_fu_785_p1); + +assign add_ln33_fu_767_p2 = ((sub_ln33_cast_fu_760_p1) + (zext_ln33_3_fu_764_p1)); + +assign and_ln19_fu_578_p2 = (xor_ln19_fu_567_p2 & icmp_ln25_fu_572_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd3]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln32_4_fu_841_p1 = tmp_12_i_fu_831_p4; + +assign bitcast_ln32_5_fu_863_p1 = tmp_13_i_fu_853_p4; + +assign bitcast_ln32_6_fu_884_p1 = tmp_14_i_fu_874_p4; + +assign bitcast_ln32_fu_802_p1 = trunc_ln32_fu_798_p1; + +assign col_coord_int_fu_518_p3 = ((is_padding_reg_969[0:0] == 1'b1) ? 10'd0 : empty_61_fu_513_p2); + +assign col_coord_int_mid139_fu_547_p3 = ((or_ln23_3_reg_1008[0:0] == 1'b1) ? 10'd0 : p_mid137_reg_958); + +assign col_coord_int_mid1_fu_635_p3 = ((or_ln23_5_reg_1021[0:0] == 1'b1) ? 10'd0 : p_mid1_fu_630_p2); + +assign empty_58_fu_262_p2 = ((zext_ln19_fu_254_p1) + (17'd131071)); + +assign empty_59_fu_326_p2 = ((p_cast_i_reg_929) + (ii_cast_i_fu_318_p1)); + +assign empty_60_fu_336_p2 = ((empty_59_fu_326_p2 > 18'd27) ? 1'b1 : 1'b0); + +assign empty_61_fu_513_p2 = ((tmp2_cast_fu_509_p1) + (trunc_ln22_reg_935)); + +assign empty_63_fu_702_p1 = select_ln20_fu_589_p3[4:0]; + +assign empty_fu_258_p1 = i_13[4:0]; + +assign icmp_ln19_fu_377_p2 = ((ap_phi_mux_indvar_flatten47_phi_fu_196_p4 == 7'd72) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_389_p2 = ((ap_phi_mux_indvar_flatten_phi_fu_220_p4 == 6'd24) ? 1'b1 : 1'b0); + +assign icmp_ln24_1_fu_359_p2 = (((add_ln22_1_fu_346_p2) > (18'd27)) ? 1'b1 : 1'b0); + +assign icmp_ln24_2_fu_463_p2 = (((add_ln22_2_fu_450_p2) > (18'd27)) ? 1'b1 : 1'b0); + +assign icmp_ln24_fu_300_p2 = (((add_ln22_fu_276_p2) > (17'd27)) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_572_p2 = ((ap_phi_mux_kk_0_i_phi_fu_243_p4 == 6'd32) ? 1'b1 : 1'b0); + +assign ii_cast_fu_322_p1 = ap_phi_mux_ii_phi_fu_208_p4; + +assign ii_cast_i_fu_318_p1 = ap_phi_mux_ii_phi_fu_208_p4; + +assign ii_cast_i_mid1_fu_403_p1 = add_ln19_fu_383_p2; + +assign ii_cast_mid1_fu_407_p1 = add_ln19_fu_383_p2; + +assign in_data_address0 = sext_ln32_fu_724_p1; + +assign is_padding_fu_371_p2 = (or_ln23_fu_365_p2 | empty_60_fu_336_p2); + +assign j_cast_i_fu_250_p1 = j_13; + +assign lshr_ln_fu_706_p4 = {{select_ln20_fu_589_p3[4:2]}}; + +assign or_ln20_fu_584_p2 = (icmp_ln20_reg_985 | and_ln19_fu_578_p2); + +assign or_ln23_1_fu_306_p2 = (tmp_fu_292_p3 | icmp_ln24_fu_300_p2); + +assign or_ln23_3_fu_435_p2 = (p_mid113_fu_421_p2 | or_ln23_1_reg_953); + +assign or_ln23_4_fu_469_p2 = (tmp_4_fu_455_p3 | icmp_ln24_2_fu_463_p2); + +assign or_ln23_5_fu_475_p2 = (select_ln19_3_fu_427_p3 | or_ln23_4_fu_469_p2); + +assign or_ln23_fu_365_p2 = (tmp_3_fu_351_p3 | icmp_ln24_1_fu_359_p2); + +assign or_ln25_3_fu_895_p2 = (empty_63_reg_1065_pp0_iter1_reg | 5'd2); + +assign or_ln25_4_fu_912_p2 = (empty_63_reg_1065_pp0_iter1_reg | 5'd3); + +assign or_ln25_fu_814_p2 = (empty_63_reg_1065_pp0_iter1_reg | 5'd1); + +assign p_cast5_i_fu_331_p2 = (p_cast_reg_947 + ii_cast_fu_322_p1); + +assign p_cast5_i_mid1_fu_416_p2 = (p_cast_reg_947 + ii_cast_mid1_fu_407_p1); + +assign p_cast_fu_286_p2 = ((empty_fu_258_p1) + (5'd31)); + +assign p_cast_i_fu_268_p1 = (empty_58_fu_262_p2); + +assign p_mid111_fu_411_p2 = ((p_cast_i_reg_929) + (ii_cast_i_mid1_fu_403_p1)); + +assign p_mid113_fu_421_p2 = ((p_mid111_fu_411_p2 > 18'd27) ? 1'b1 : 1'b0); + +assign p_mid137_fu_312_p2 = ((trunc_ln22_fu_272_p1) + (10'd1023)); + +assign p_mid1_fu_630_p2 = ((tmp2_cast_mid1_fu_626_p1) + (trunc_ln22_reg_935)); + +assign row_coord_int_fu_497_p3 = ((is_padding_reg_969[0:0] == 1'b1) ? 5'd0 : p_cast5_i_reg_963); + +assign row_coord_int_mid131_fu_541_p3 = ((or_ln23_3_reg_1008[0:0] == 1'b1) ? 5'd0 : p_cast5_i_mid1_reg_1002); + +assign row_coord_int_mid1_fu_613_p3 = ((or_ln23_5_reg_1021[0:0] == 1'b1) ? 5'd0 : select_ln19_2_fu_531_p3); + +assign select_ln19_1_fu_525_p3 = ((icmp_ln20_reg_985[0:0] == 1'b1) ? add_ln19_reg_980 : ii_reg_204); + +assign select_ln19_2_fu_531_p3 = ((icmp_ln20_reg_985[0:0] == 1'b1) ? p_cast5_i_mid1_reg_1002 : p_cast5_i_reg_963); + +assign select_ln19_3_fu_427_p3 = ((icmp_ln20_fu_389_p2[0:0] == 1'b1) ? p_mid113_fu_421_p2 : empty_60_fu_336_p2); + +assign select_ln19_4_fu_536_p3 = ((icmp_ln20_reg_985[0:0] == 1'b1) ? or_ln23_3_reg_1008 : is_padding_reg_969); + +assign select_ln19_5_fu_553_p3 = ((icmp_ln20_reg_985[0:0] == 1'b1) ? row_coord_int_mid131_fu_541_p3 : row_coord_int_fu_497_p3); + +assign select_ln19_6_fu_560_p3 = ((icmp_ln20_reg_985[0:0] == 1'b1) ? col_coord_int_mid139_fu_547_p3 : col_coord_int_fu_518_p3); + +assign select_ln19_fu_395_p3 = ((icmp_ln20_fu_389_p2[0:0] == 1'b1) ? 2'd0 : ap_phi_mux_jj_phi_fu_231_p4); + +assign select_ln20_1_fu_597_p3 = ((and_ln19_fu_578_p2[0:0] == 1'b1) ? add_ln20_reg_1015 : select_ln19_reg_997); + +assign select_ln20_2_fu_606_p3 = ((and_ln19_fu_578_p2[0:0] == 1'b1) ? or_ln23_5_reg_1021 : select_ln19_4_fu_536_p3); + +assign select_ln20_3_fu_642_p3 = ((and_ln19_fu_578_p2[0:0] == 1'b1) ? row_coord_int_mid1_fu_613_p3 : select_ln19_5_fu_553_p3); + +assign select_ln20_4_fu_684_p3 = ((and_ln19_fu_578_p2[0:0] == 1'b1) ? col_coord_int_mid1_fu_635_p3 : select_ln19_6_fu_560_p3); + +assign select_ln20_5_fu_729_p3 = ((icmp_ln20_reg_985[0:0] == 1'b1) ? 6'd1 : add_ln20_1_reg_1028); + +assign select_ln20_fu_589_p3 = ((or_ln20_fu_584_p2[0:0] == 1'b1) ? 6'd0 : ap_phi_mux_kk_0_i_phi_fu_243_p4); + +assign select_ln33_4_fu_845_p3 = ((select_ln20_2_reg_1057_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_4_fu_841_p1); + +assign select_ln33_5_fu_867_p3 = ((select_ln20_2_reg_1057_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_5_fu_863_p1); + +assign select_ln33_6_fu_888_p3 = ((select_ln20_2_reg_1057_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_6_fu_884_p1); + +assign select_ln33_fu_806_p3 = ((select_ln20_2_reg_1057_pp0_iter1_reg[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_fu_802_p1); + +assign sext_ln20_fu_680_p1 = (sub_ln32_fu_674_p2); + +assign sext_ln22_fu_282_p1 = add_ln22_fu_276_p2; + +assign sext_ln32_fu_724_p1 = (tmp_5_fu_716_p3); + +assign sext_ln33_1_fu_907_p1 = (tmp_7_fu_900_p3); + +assign sext_ln33_2_fu_924_p1 = (tmp_8_fu_917_p3); + +assign sext_ln33_fu_826_p1 = (tmp_6_fu_819_p3); + +assign sub_ln32_fu_674_p2 = (zext_ln32_fu_658_p1 - zext_ln32_7_fu_670_p1); + +assign sub_ln33_cast_fu_760_p1 = (sub_ln33_fu_754_p2); + +assign sub_ln33_fu_754_p2 = (zext_ln33_2_fu_750_p1 - zext_ln33_fu_740_p1); + +assign tmp2_cast_fu_509_p1 = (tmp2_fu_503_p2); + +assign tmp2_cast_mid1_fu_626_p1 = (tmp2_mid1_fu_620_p2); + +assign tmp2_fu_503_p2 = ((zext_ln22_fu_493_p1) + (3'd7)); + +assign tmp2_mid1_fu_620_p2 = ((zext_ln22_1_fu_603_p1) + (3'd7)); + +assign tmp_12_i_fu_831_p4 = {{in_data_q0[31:16]}}; + +assign tmp_13_cast_fu_777_p3 = {{trunc_ln33_fu_773_p1}, {5'd0}}; + +assign tmp_13_i_fu_853_p4 = {{in_data_q0[47:32]}}; + +assign tmp_14_i_fu_874_p4 = {{in_data_q0[63:48]}}; + +assign tmp_1_fu_650_p3 = {{select_ln20_3_fu_642_p3}, {5'd0}}; + +assign tmp_2_fu_662_p3 = {{select_ln20_3_fu_642_p3}, {2'd0}}; + +assign tmp_3_fu_351_p3 = add_ln22_1_fu_346_p2[32'd17]; + +assign tmp_4_fu_455_p3 = add_ln22_2_fu_450_p2[32'd17]; + +assign tmp_5_fu_716_p3 = {{add_ln32_fu_696_p2}, {lshr_ln_fu_706_p4}}; + +assign tmp_6_fu_819_p3 = {{add_ln33_reg_1087}, {or_ln25_fu_814_p2}}; + +assign tmp_7_fu_900_p3 = {{add_ln33_reg_1087}, {or_ln25_3_fu_895_p2}}; + +assign tmp_8_fu_917_p3 = {{add_ln33_reg_1087}, {or_ln25_4_fu_912_p2}}; + +assign tmp_fu_292_p3 = add_ln22_fu_276_p2[32'd16]; + +assign tmp_s_fu_743_p3 = {{select_ln19_1_reg_1038}, {2'd0}}; + +assign trunc_ln22_fu_272_p1 = j_13[9:0]; + +assign trunc_ln32_fu_798_p1 = in_data_q0[15:0]; + +assign trunc_ln33_fu_773_p1 = add_ln33_fu_767_p2[3:0]; + +assign xor_ln19_fu_567_p2 = (icmp_ln20_reg_985 ^ 1'd1); + +assign zext_ln19_fu_254_p1 = i_13; + +assign zext_ln20_1_fu_446_p1 = add_ln20_fu_440_p2; + +assign zext_ln20_fu_342_p1 = ap_phi_mux_jj_phi_fu_231_p4; + +assign zext_ln22_1_fu_603_p1 = add_ln20_reg_1015; + +assign zext_ln22_fu_493_p1 = jj_reg_227; + +assign zext_ln32_7_fu_670_p1 = tmp_2_fu_662_p3; + +assign zext_ln32_8_fu_692_p1 = select_ln20_4_fu_684_p3; + +assign zext_ln32_fu_658_p1 = tmp_1_fu_650_p3; + +assign zext_ln33_2_fu_750_p1 = tmp_s_fu_743_p3; + +assign zext_ln33_3_fu_764_p1 = select_ln20_1_reg_1051; + +assign zext_ln33_4_fu_785_p1 = select_ln20_reg_1045; + +assign zext_ln33_5_fu_794_p1 = add_ln33_1_reg_1094; + +assign zext_ln33_fu_740_p1 = select_ln19_1_reg_1038; + +endmodule //td_fused_top_tdf8_readInputs57 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf8_writeOutputs_unaligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_idle, + ap_ready, + i, + j, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1, + max_vals_0 +); + +parameter ap_ST_fsm_state1 = 2'd1; +parameter ap_ST_fsm_state2 = 2'd2; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +input [3:0] i; +input [7:0] j; +output [13:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; +input [15:0] max_vals_0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg out_data_ce1; +reg out_data_we1; + + reg [1:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] outputCount_3; +reg [15:0] outputChanIdx_3; +reg [15:0] outputRow_13_0; +reg [15:0] outputRow_13_1; +reg [15:0] outputRow_13_2; +reg [15:0] outputRow_13_3; +wire [15:0] add_ln87_fu_177_p2; +wire [0:0] icmp_ln88_fu_183_p2; +reg [0:0] icmp_ln88_reg_297; +reg [15:0] ap_phi_mux_empty_phi_fu_94_p4; +reg [15:0] empty_reg_91; +wire ap_CS_fsm_state2; +wire [63:0] zext_ln94_4_fu_211_p1; +wire [15:0] select_ln97_fu_269_p3; +wire [1:0] trunc_ln86_fu_149_p1; +reg [15:0] ap_sig_allocacmp_outputRow_13_0_load; +reg [15:0] ap_sig_allocacmp_outputRow_13_1_load; +reg [15:0] ap_sig_allocacmp_outputRow_13_2_load; +reg [15:0] ap_sig_allocacmp_outputRow_13_3_load; +wire [4:0] tmp_8_fu_109_p3; +wire [7:0] tmp_fu_101_p3; +wire [7:0] zext_ln94_fu_117_p1; +wire [7:0] sub_ln94_fu_121_p2; +wire [7:0] add_ln94_fu_127_p2; +wire [7:0] trunc_ln94_fu_197_p1; +wire [13:0] tmp_10_cast_fu_133_p3; +wire [13:0] zext_ln94_3_fu_201_p1; +wire [13:0] add_ln94_2_fu_205_p2; +wire [15:0] bitcast_ln94_6_fu_240_p1; +wire [15:0] bitcast_ln94_5_fu_232_p1; +wire [15:0] bitcast_ln94_4_fu_224_p1; +wire [15:0] bitcast_ln94_fu_216_p1; +wire [15:0] add_ln96_fu_257_p2; +wire [0:0] icmp_ln97_fu_263_p2; +reg [1:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 2'd1; +#0 outputCount_3 = 16'd0; +#0 outputChanIdx_3 = 16'd0; +#0 outputRow_13_0 = 16'd0; +#0 outputRow_13_1 = 16'd0; +#0 outputRow_13_2 = 16'd0; +#0 outputRow_13_3 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_reg_297 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + empty_reg_91 <= 16'd0; + end else if (((ap_start == 1'b1) & (icmp_ln88_fu_183_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + empty_reg_91 <= add_ln87_fu_177_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + icmp_ln88_reg_297 <= icmp_ln88_fu_183_p2; + end +end + +always @ (posedge ap_clk) begin + if (((ap_start == 1'b1) & (icmp_ln88_fu_183_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + outputChanIdx_3 <= select_ln97_fu_269_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + outputCount_3 <= ap_phi_mux_empty_phi_fu_94_p4; + end +end + +always @ (posedge ap_clk) begin + if (((ap_start == 1'b1) & (trunc_ln86_fu_149_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_13_0 <= max_vals_0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_start == 1'b1) & (trunc_ln86_fu_149_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_13_1 <= max_vals_0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_start == 1'b1) & (trunc_ln86_fu_149_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_13_2 <= max_vals_0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_start == 1'b1) & (trunc_ln86_fu_149_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state1))) begin + outputRow_13_3 <= max_vals_0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_reg_297 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_phi_mux_empty_phi_fu_94_p4 = 16'd0; + end else begin + ap_phi_mux_empty_phi_fu_94_p4 = empty_reg_91; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_149_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_sig_allocacmp_outputRow_13_0_load = max_vals_0; + end else begin + ap_sig_allocacmp_outputRow_13_0_load = outputRow_13_0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_149_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state1))) begin + ap_sig_allocacmp_outputRow_13_1_load = max_vals_0; + end else begin + ap_sig_allocacmp_outputRow_13_1_load = outputRow_13_1; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_149_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state1))) begin + ap_sig_allocacmp_outputRow_13_2_load = max_vals_0; + end else begin + ap_sig_allocacmp_outputRow_13_2_load = outputRow_13_2; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_149_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state1))) begin + ap_sig_allocacmp_outputRow_13_3_load = max_vals_0; + end else begin + ap_sig_allocacmp_outputRow_13_3_load = outputRow_13_3; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1)))) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((ap_start == 1'b1) & (icmp_ln88_fu_183_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln87_fu_177_p2 = (outputCount_3 + 16'd1); + +assign add_ln94_2_fu_205_p2 = (tmp_10_cast_fu_133_p3 + zext_ln94_3_fu_201_p1); + +assign add_ln94_fu_127_p2 = (sub_ln94_fu_121_p2 + j); + +assign add_ln96_fu_257_p2 = (outputChanIdx_3 + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign bitcast_ln94_4_fu_224_p1 = ap_sig_allocacmp_outputRow_13_1_load; + +assign bitcast_ln94_5_fu_232_p1 = ap_sig_allocacmp_outputRow_13_2_load; + +assign bitcast_ln94_6_fu_240_p1 = ap_sig_allocacmp_outputRow_13_3_load; + +assign bitcast_ln94_fu_216_p1 = ap_sig_allocacmp_outputRow_13_0_load; + +assign icmp_ln88_fu_183_p2 = ((add_ln87_fu_177_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign icmp_ln97_fu_263_p2 = ((add_ln96_fu_257_p2 == 16'd64) ? 1'b1 : 1'b0); + +assign out_data_address1 = zext_ln94_4_fu_211_p1; + +assign out_data_d1 = {{{{bitcast_ln94_6_fu_240_p1}, {bitcast_ln94_5_fu_232_p1}}, {bitcast_ln94_4_fu_224_p1}}, {bitcast_ln94_fu_216_p1}}; + +assign select_ln97_fu_269_p3 = ((icmp_ln97_fu_263_p2[0:0] == 1'b1) ? 16'd0 : add_ln96_fu_257_p2); + +assign sub_ln94_fu_121_p2 = (tmp_fu_101_p3 - zext_ln94_fu_117_p1); + +assign tmp_10_cast_fu_133_p3 = {{add_ln94_fu_127_p2}, {6'd0}}; + +assign tmp_8_fu_109_p3 = {{i}, {1'd0}}; + +assign tmp_fu_101_p3 = {{i}, {4'd0}}; + +assign trunc_ln86_fu_149_p1 = outputCount_3[1:0]; + +assign trunc_ln94_fu_197_p1 = outputChanIdx_3[7:0]; + +assign zext_ln94_3_fu_201_p1 = trunc_ln94_fu_197_p1; + +assign zext_ln94_4_fu_211_p1 = add_ln94_2_fu_205_p2; + +assign zext_ln94_fu_117_p1 = tmp_8_fu_109_p3; + +endmodule //td_fused_top_tdf8_writeOutputs_unaligned +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_16 ( + in_data_address0, + in_data_ce0, + in_data_d0, + in_data_q0, + in_data_we0, + in_data_address1, + in_data_ce1, + in_data_d1, + in_data_q1, + in_data_we1, + out_data_address0, + out_data_ce0, + out_data_d0, + out_data_q0, + out_data_we0, + out_data_address1, + out_data_ce1, + out_data_d1, + out_data_q1, + out_data_we1, + filter_data_address0, + filter_data_ce0, + filter_data_d0, + filter_data_q0, + filter_data_we0, + filter_data_address1, + filter_data_ce1, + filter_data_d1, + filter_data_q1, + filter_data_we1, + adjustments_address0, + adjustments_ce0, + adjustments_d0, + adjustments_q0, + adjustments_we0, + adjustments_address1, + adjustments_ce1, + adjustments_d1, + adjustments_q1, + adjustments_we1, + ap_clk, + ap_rst, + in_data_empty_n, + in_data_read, + out_data_full_n, + out_data_write, + ap_start, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +output [13:0] in_data_address0; +output in_data_ce0; +output [63:0] in_data_d0; +input [63:0] in_data_q0; +output in_data_we0; +output [13:0] in_data_address1; +output in_data_ce1; +output [63:0] in_data_d1; +input [63:0] in_data_q1; +output in_data_we1; +output [11:0] out_data_address0; +output out_data_ce0; +output [63:0] out_data_d0; +input [63:0] out_data_q0; +output out_data_we0; +output [11:0] out_data_address1; +output out_data_ce1; +output [63:0] out_data_d1; +input [63:0] out_data_q1; +output out_data_we1; +output [13:0] filter_data_address0; +output filter_data_ce0; +output [15:0] filter_data_d0; +input [15:0] filter_data_q0; +output filter_data_we0; +output [13:0] filter_data_address1; +output filter_data_ce1; +output [15:0] filter_data_d1; +input [15:0] filter_data_q1; +output filter_data_we1; +output [5:0] adjustments_address0; +output adjustments_ce0; +output [47:0] adjustments_d0; +input [47:0] adjustments_q0; +output adjustments_we0; +output [5:0] adjustments_address1; +output adjustments_ce1; +output [47:0] adjustments_d1; +input [47:0] adjustments_q1; +output adjustments_we1; +input ap_clk; +input ap_rst; +input in_data_empty_n; +output in_data_read; +input out_data_full_n; +output out_data_write; +input ap_start; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +reg ap_done; +reg ap_ready; +reg ap_idle; + +wire [13:0] dataflow_in_loop_TOP_LOOP37360_U0_in_data_address0; +wire dataflow_in_loop_TOP_LOOP37360_U0_in_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP37360_U0_in_data_d0; +wire dataflow_in_loop_TOP_LOOP37360_U0_in_data_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP37360_U0_in_data_address1; +wire dataflow_in_loop_TOP_LOOP37360_U0_in_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP37360_U0_in_data_d1; +wire dataflow_in_loop_TOP_LOOP37360_U0_in_data_we1; +wire [13:0] dataflow_in_loop_TOP_LOOP37360_U0_filter_data_address0; +wire dataflow_in_loop_TOP_LOOP37360_U0_filter_data_ce0; +wire [15:0] dataflow_in_loop_TOP_LOOP37360_U0_filter_data_d0; +wire dataflow_in_loop_TOP_LOOP37360_U0_filter_data_we0; +wire [13:0] dataflow_in_loop_TOP_LOOP37360_U0_filter_data_address1; +wire dataflow_in_loop_TOP_LOOP37360_U0_filter_data_ce1; +wire [15:0] dataflow_in_loop_TOP_LOOP37360_U0_filter_data_d1; +wire dataflow_in_loop_TOP_LOOP37360_U0_filter_data_we1; +wire [5:0] dataflow_in_loop_TOP_LOOP37360_U0_adjustments_address0; +wire dataflow_in_loop_TOP_LOOP37360_U0_adjustments_ce0; +wire [47:0] dataflow_in_loop_TOP_LOOP37360_U0_adjustments_d0; +wire dataflow_in_loop_TOP_LOOP37360_U0_adjustments_we0; +wire [5:0] dataflow_in_loop_TOP_LOOP37360_U0_adjustments_address1; +wire dataflow_in_loop_TOP_LOOP37360_U0_adjustments_ce1; +wire [47:0] dataflow_in_loop_TOP_LOOP37360_U0_adjustments_d1; +wire dataflow_in_loop_TOP_LOOP37360_U0_adjustments_we1; +wire [11:0] dataflow_in_loop_TOP_LOOP37360_U0_out_data_address0; +wire dataflow_in_loop_TOP_LOOP37360_U0_out_data_ce0; +wire [63:0] dataflow_in_loop_TOP_LOOP37360_U0_out_data_d0; +wire dataflow_in_loop_TOP_LOOP37360_U0_out_data_we0; +wire [11:0] dataflow_in_loop_TOP_LOOP37360_U0_out_data_address1; +wire dataflow_in_loop_TOP_LOOP37360_U0_out_data_ce1; +wire [63:0] dataflow_in_loop_TOP_LOOP37360_U0_out_data_d1; +wire dataflow_in_loop_TOP_LOOP37360_U0_out_data_we1; +wire dataflow_in_loop_TOP_LOOP37360_U0_ap_start; +wire dataflow_in_loop_TOP_LOOP37360_U0_in_data_read; +wire dataflow_in_loop_TOP_LOOP37360_U0_out_data_write; +wire dataflow_in_loop_TOP_LOOP37360_U0_ap_done; +wire dataflow_in_loop_TOP_LOOP37360_U0_ap_ready; +wire dataflow_in_loop_TOP_LOOP37360_U0_ap_idle; +reg dataflow_in_loop_TOP_LOOP37360_U0_ap_continue; +wire dataflow_in_loop_TOP_LOOP37360_U0_in_data_full_n; +wire dataflow_in_loop_TOP_LOOP37360_U0_in_data_write; +wire ap_sync_continue; +wire ap_sync_done; +wire ap_sync_ready; +reg [13:0] loop_dataflow_input_count; +reg [13:0] loop_dataflow_output_count; +wire [13:0] bound_minus_1; +wire dataflow_in_loop_TOP_LOOP37360_U0_start_full_n; +wire dataflow_in_loop_TOP_LOOP37360_U0_start_write; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 loop_dataflow_input_count = 14'd0; +#0 loop_dataflow_output_count = 14'd0; +end + +td_fused_top_dataflow_in_loop_TOP_LOOP37360 dataflow_in_loop_TOP_LOOP37360_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_address0(dataflow_in_loop_TOP_LOOP37360_U0_in_data_address0), + .in_data_ce0(dataflow_in_loop_TOP_LOOP37360_U0_in_data_ce0), + .in_data_d0(dataflow_in_loop_TOP_LOOP37360_U0_in_data_d0), + .in_data_q0(in_data_q0), + .in_data_we0(dataflow_in_loop_TOP_LOOP37360_U0_in_data_we0), + .in_data_address1(dataflow_in_loop_TOP_LOOP37360_U0_in_data_address1), + .in_data_ce1(dataflow_in_loop_TOP_LOOP37360_U0_in_data_ce1), + .in_data_d1(dataflow_in_loop_TOP_LOOP37360_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(dataflow_in_loop_TOP_LOOP37360_U0_in_data_we1), + .filter_data_address0(dataflow_in_loop_TOP_LOOP37360_U0_filter_data_address0), + .filter_data_ce0(dataflow_in_loop_TOP_LOOP37360_U0_filter_data_ce0), + .filter_data_d0(dataflow_in_loop_TOP_LOOP37360_U0_filter_data_d0), + .filter_data_q0(filter_data_q0), + .filter_data_we0(dataflow_in_loop_TOP_LOOP37360_U0_filter_data_we0), + .filter_data_address1(dataflow_in_loop_TOP_LOOP37360_U0_filter_data_address1), + .filter_data_ce1(dataflow_in_loop_TOP_LOOP37360_U0_filter_data_ce1), + .filter_data_d1(dataflow_in_loop_TOP_LOOP37360_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(dataflow_in_loop_TOP_LOOP37360_U0_filter_data_we1), + .adjustments_address0(dataflow_in_loop_TOP_LOOP37360_U0_adjustments_address0), + .adjustments_ce0(dataflow_in_loop_TOP_LOOP37360_U0_adjustments_ce0), + .adjustments_d0(dataflow_in_loop_TOP_LOOP37360_U0_adjustments_d0), + .adjustments_q0(adjustments_q0), + .adjustments_we0(dataflow_in_loop_TOP_LOOP37360_U0_adjustments_we0), + .adjustments_address1(dataflow_in_loop_TOP_LOOP37360_U0_adjustments_address1), + .adjustments_ce1(dataflow_in_loop_TOP_LOOP37360_U0_adjustments_ce1), + .adjustments_d1(dataflow_in_loop_TOP_LOOP37360_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(dataflow_in_loop_TOP_LOOP37360_U0_adjustments_we1), + .out_data_address0(dataflow_in_loop_TOP_LOOP37360_U0_out_data_address0), + .out_data_ce0(dataflow_in_loop_TOP_LOOP37360_U0_out_data_ce0), + .out_data_d0(dataflow_in_loop_TOP_LOOP37360_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(dataflow_in_loop_TOP_LOOP37360_U0_out_data_we0), + .out_data_address1(dataflow_in_loop_TOP_LOOP37360_U0_out_data_address1), + .out_data_ce1(dataflow_in_loop_TOP_LOOP37360_U0_out_data_ce1), + .out_data_d1(dataflow_in_loop_TOP_LOOP37360_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(dataflow_in_loop_TOP_LOOP37360_U0_out_data_we1), + .ap_start(dataflow_in_loop_TOP_LOOP37360_U0_ap_start), + .in_data_empty_n(1'b0), + .in_data_read(dataflow_in_loop_TOP_LOOP37360_U0_in_data_read), + .out_data_full_n(out_data_full_n), + .out_data_write(dataflow_in_loop_TOP_LOOP37360_U0_out_data_write), + .ap_done(dataflow_in_loop_TOP_LOOP37360_U0_ap_done), + .ap_ready(dataflow_in_loop_TOP_LOOP37360_U0_ap_ready), + .ap_idle(dataflow_in_loop_TOP_LOOP37360_U0_ap_idle), + .ap_continue(dataflow_in_loop_TOP_LOOP37360_U0_ap_continue) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_input_count <= 14'd0; + end else begin + if ((~(loop_dataflow_input_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37360_U0_ap_ready == 1'b1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= (loop_dataflow_input_count + 14'd1); + end else if (((dataflow_in_loop_TOP_LOOP37360_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + loop_dataflow_input_count <= 14'd0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + loop_dataflow_output_count <= 14'd0; + end else begin + if ((~(loop_dataflow_output_count == bound_minus_1) & (dataflow_in_loop_TOP_LOOP37360_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP37360_U0_ap_done == 1'b1))) begin + loop_dataflow_output_count <= (loop_dataflow_output_count + 14'd1); + end else if (((dataflow_in_loop_TOP_LOOP37360_U0_ap_continue == 1'b1) & (dataflow_in_loop_TOP_LOOP37360_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + loop_dataflow_output_count <= 14'd0; + end + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP37360_U0_ap_done == 1'b1) & (loop_dataflow_output_count == bound_minus_1))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP37360_U0_ap_idle == 1'b1) & (loop_dataflow_output_count == 14'd0) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((dataflow_in_loop_TOP_LOOP37360_U0_ap_ready == 1'b1) & (loop_dataflow_input_count == bound_minus_1) & (ap_start == 1'b1))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~(loop_dataflow_output_count == bound_minus_1) | (ap_continue == 1'b1))) begin + dataflow_in_loop_TOP_LOOP37360_U0_ap_continue = 1'b1; + end else begin + dataflow_in_loop_TOP_LOOP37360_U0_ap_continue = 1'b0; + end +end + +assign adjustments_address0 = dataflow_in_loop_TOP_LOOP37360_U0_adjustments_address0; + +assign adjustments_address1 = 6'd0; + +assign adjustments_ce0 = dataflow_in_loop_TOP_LOOP37360_U0_adjustments_ce0; + +assign adjustments_ce1 = 1'b0; + +assign adjustments_d0 = 48'd0; + +assign adjustments_d1 = 48'd0; + +assign adjustments_we0 = 1'b0; + +assign adjustments_we1 = 1'b0; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = dataflow_in_loop_TOP_LOOP37360_U0_ap_done; + +assign ap_sync_ready = dataflow_in_loop_TOP_LOOP37360_U0_ap_ready; + +assign bound_minus_1 = (14'd12544 - 14'd1); + +assign dataflow_in_loop_TOP_LOOP37360_U0_ap_start = ap_start; + +assign dataflow_in_loop_TOP_LOOP37360_U0_in_data_full_n = in_data_empty_n; + +assign dataflow_in_loop_TOP_LOOP37360_U0_in_data_write = 1'b0; + +assign dataflow_in_loop_TOP_LOOP37360_U0_start_full_n = 1'b1; + +assign dataflow_in_loop_TOP_LOOP37360_U0_start_write = 1'b0; + +assign filter_data_address0 = dataflow_in_loop_TOP_LOOP37360_U0_filter_data_address0; + +assign filter_data_address1 = 14'd0; + +assign filter_data_ce0 = dataflow_in_loop_TOP_LOOP37360_U0_filter_data_ce0; + +assign filter_data_ce1 = 1'b0; + +assign filter_data_d0 = 16'd0; + +assign filter_data_d1 = 16'd0; + +assign filter_data_we0 = 1'b0; + +assign filter_data_we1 = 1'b0; + +assign in_data_address0 = dataflow_in_loop_TOP_LOOP37360_U0_in_data_address0; + +assign in_data_address1 = 14'd0; + +assign in_data_ce0 = dataflow_in_loop_TOP_LOOP37360_U0_in_data_ce0; + +assign in_data_ce1 = 1'b0; + +assign in_data_d0 = 64'd0; + +assign in_data_d1 = 64'd0; + +assign in_data_read = dataflow_in_loop_TOP_LOOP37360_U0_in_data_write; + +assign in_data_we0 = 1'b0; + +assign in_data_we1 = 1'b0; + +assign out_data_address0 = 12'd0; + +assign out_data_address1 = dataflow_in_loop_TOP_LOOP37360_U0_out_data_address1; + +assign out_data_ce0 = 1'b0; + +assign out_data_ce1 = dataflow_in_loop_TOP_LOOP37360_U0_out_data_ce1; + +assign out_data_d0 = 64'd0; + +assign out_data_d1 = dataflow_in_loop_TOP_LOOP37360_U0_out_data_d1; + +assign out_data_we0 = 1'b0; + +assign out_data_we1 = dataflow_in_loop_TOP_LOOP37360_U0_out_data_we1; + +assign out_data_write = dataflow_in_loop_TOP_LOOP37360_U0_out_data_write; + +endmodule //td_fused_top_tdf9_16 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_accum_1 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_0_address0, + accum_in_0_ce0, + accum_in_0_q0, + accum_in_0_address1, + accum_in_0_ce1, + accum_in_0_q1, + accum_out_address0, + accum_out_ce0, + accum_out_we0, + accum_out_d0, + accum_out_address1, + accum_out_ce1, + accum_out_we1, + accum_out_d1 +); + +parameter ap_ST_fsm_state1 = 8'd1; +parameter ap_ST_fsm_pp0_stage0 = 8'd2; +parameter ap_ST_fsm_pp0_stage1 = 8'd4; +parameter ap_ST_fsm_pp0_stage2 = 8'd8; +parameter ap_ST_fsm_pp0_stage3 = 8'd16; +parameter ap_ST_fsm_state12 = 8'd32; +parameter ap_ST_fsm_state13 = 8'd64; +parameter ap_ST_fsm_state14 = 8'd128; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [7:0] accum_in_0_address0; +output accum_in_0_ce0; +input [15:0] accum_in_0_q0; +output [7:0] accum_in_0_address1; +output accum_in_0_ce1; +input [15:0] accum_in_0_q1; +output [2:0] accum_out_address0; +output accum_out_ce0; +output accum_out_we0; +output [15:0] accum_out_d0; +output [2:0] accum_out_address1; +output accum_out_ce1; +output accum_out_we1; +output [15:0] accum_out_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[7:0] accum_in_0_address0; +reg accum_in_0_ce0; +reg[7:0] accum_in_0_address1; +reg accum_in_0_ce1; +reg accum_out_ce0; +reg accum_out_we0; +reg accum_out_ce1; +reg accum_out_we1; + +reg ap_done_reg; + reg [7:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [8:0] x_reg_170; +reg [15:0] psum_7_08_reg_182; +reg [15:0] psum_6_07_reg_194; +reg [15:0] psum_5_06_reg_206; +reg [15:0] psum_4_05_reg_218; +reg [15:0] psum_3_04_reg_230; +reg [15:0] psum_2_03_reg_242; +reg [15:0] psum_1_02_reg_254; +reg [15:0] psum_0_01_reg_266; +wire [0:0] tmp_fu_323_p3; +reg [0:0] tmp_reg_494; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state6_pp0_stage0_iter1; +wire ap_block_state10_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +reg [0:0] tmp_reg_494_pp0_iter1_reg; +reg [0:0] tmp_reg_494_pp0_iter2_reg; +wire [7:0] trunc_ln25_fu_336_p1; +reg [7:0] trunc_ln25_reg_498; +reg [15:0] accum_in_0_load_reg_518; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state7_pp0_stage1_iter1; +wire ap_block_state11_pp0_stage1_iter2; +wire ap_block_pp0_stage1_11001; +reg [15:0] accum_in_0_load_1_reg_523; +reg [15:0] accum_in_0_load_2_reg_538; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state8_pp0_stage2_iter1; +wire ap_block_pp0_stage2_11001; +reg [15:0] accum_in_0_load_3_reg_543; +wire [8:0] add_ln25_fu_391_p2; +reg [8:0] add_ln25_reg_558; +wire ap_CS_fsm_pp0_stage3; +wire ap_block_state5_pp0_stage3_iter0; +wire ap_block_state9_pp0_stage3_iter1; +wire ap_block_pp0_stage3_11001; +reg [15:0] accum_in_0_load_4_reg_563; +reg [15:0] accum_in_0_load_5_reg_568; +reg [15:0] accum_in_0_load_6_reg_583; +reg ap_enable_reg_pp0_iter1; +reg [15:0] accum_in_0_load_7_reg_588; +wire [15:0] grp_fu_307_p2; +wire [15:0] grp_fu_312_p2; +reg ap_enable_reg_pp0_iter2; +wire [3:0] add_ln33_fu_434_p2; +wire ap_CS_fsm_state13; +wire [0:0] tmp_2_fu_417_p3; +reg ap_block_state1; +wire ap_block_pp0_stage2_subdone; +reg ap_condition_pp0_exit_iter0_state4; +wire ap_block_pp0_stage3_subdone; +wire ap_block_pp0_stage1_subdone; +reg [8:0] ap_phi_mux_x_phi_fu_174_p4; +wire ap_block_pp0_stage0; +wire [15:0] ap_phi_mux_psum_7_08_phi_fu_186_p4; +wire ap_block_pp0_stage1; +wire [15:0] ap_phi_mux_psum_6_07_phi_fu_198_p4; +wire [15:0] ap_phi_mux_psum_5_06_phi_fu_210_p4; +wire [15:0] ap_phi_mux_psum_4_05_phi_fu_222_p4; +wire [15:0] ap_phi_mux_psum_3_04_phi_fu_234_p4; +wire ap_block_pp0_stage3; +wire [15:0] ap_phi_mux_psum_2_03_phi_fu_246_p4; +wire ap_block_pp0_stage2; +reg [3:0] q_reg_278; +wire ap_CS_fsm_state12; +reg [15:0] ap_phi_mux_phi_ln45_phi_fu_292_p8; +wire [2:0] trunc_ln33_fu_430_p1; +wire [63:0] zext_ln25_fu_331_p1; +wire [63:0] zext_ln29_fu_346_p1; +wire [63:0] zext_ln29_1_fu_356_p1; +wire [63:0] zext_ln29_2_fu_366_p1; +wire [63:0] zext_ln29_3_fu_376_p1; +wire [63:0] zext_ln29_4_fu_386_p1; +wire [63:0] zext_ln29_5_fu_402_p1; +wire [63:0] zext_ln29_6_fu_412_p1; +wire [63:0] zext_ln33_fu_425_p1; +wire [63:0] zext_ln33_1_fu_446_p1; +reg [15:0] grp_fu_307_p0; +reg [15:0] grp_fu_307_p1; +reg [15:0] grp_fu_312_p0; +reg [15:0] grp_fu_312_p1; +wire [7:0] or_ln29_fu_340_p2; +wire [7:0] or_ln29_1_fu_351_p2; +wire [7:0] or_ln29_2_fu_361_p2; +wire [7:0] or_ln29_3_fu_371_p2; +wire [7:0] or_ln29_4_fu_381_p2; +wire [7:0] or_ln29_5_fu_397_p2; +wire [7:0] or_ln29_6_fu_407_p2; +wire [2:0] or_ln33_fu_440_p2; +wire [0:0] icmp_ln45_fu_451_p2; +wire [0:0] icmp_ln45_1_fu_465_p2; +wire [15:0] select_ln45_fu_457_p3; +wire [0:0] icmp_ln45_2_fu_479_p2; +wire [15:0] select_ln45_1_fu_471_p3; +wire ap_CS_fsm_state14; +reg [7:0] ap_NS_fsm; +wire ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +reg ap_condition_518; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 8'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U564( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_307_p0), + .din1(grp_fu_307_p1), + .dout(grp_fu_307_p2) +); + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U565( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(grp_fu_312_p0), + .din1(grp_fu_312_p1), + .dout(grp_fu_312_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage2_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + q_reg_278 <= 4'd0; + end else if (((tmp_2_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + q_reg_278 <= add_ln33_fu_434_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + x_reg_170 <= add_ln25_reg_558; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + x_reg_170 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_1_reg_523 <= accum_in_0_q0; + accum_in_0_load_reg_518 <= accum_in_0_q1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage2_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_2_reg_538 <= accum_in_0_q1; + accum_in_0_load_3_reg_543 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage3_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + accum_in_0_load_4_reg_563 <= accum_in_0_q1; + accum_in_0_load_5_reg_568 <= accum_in_0_q0; + add_ln25_reg_558 <= add_ln25_fu_391_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + accum_in_0_load_6_reg_583 <= accum_in_0_q1; + accum_in_0_load_7_reg_588 <= accum_in_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_0_01_reg_266 <= grp_fu_307_p2; + psum_1_02_reg_254 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + psum_2_03_reg_242 <= grp_fu_307_p2; + psum_3_04_reg_230 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + psum_4_05_reg_218 <= grp_fu_307_p2; + psum_5_06_reg_206 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((tmp_reg_494_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + psum_6_07_reg_194 <= grp_fu_307_p2; + psum_7_08_reg_182 <= grp_fu_312_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + tmp_reg_494 <= ap_phi_mux_x_phi_fu_174_p4[32'd8]; + tmp_reg_494_pp0_iter1_reg <= tmp_reg_494; + tmp_reg_494_pp0_iter2_reg <= tmp_reg_494_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (tmp_fu_323_p3 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + trunc_ln25_reg_498 <= trunc_ln25_fu_336_p1; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address0 = zext_ln29_6_fu_412_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address0 = zext_ln29_4_fu_386_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address0 = zext_ln29_2_fu_366_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address0 = zext_ln29_fu_346_p1; + end else begin + accum_in_0_address0 = 'bx; + end + end else begin + accum_in_0_address0 = 'bx; + end +end + +always @ (*) begin + if ((ap_enable_reg_pp0_iter0 == 1'b1)) begin + if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + accum_in_0_address1 = zext_ln29_5_fu_402_p1; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + accum_in_0_address1 = zext_ln29_3_fu_376_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + accum_in_0_address1 = zext_ln29_1_fu_356_p1; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + accum_in_0_address1 = zext_ln25_fu_331_p1; + end else begin + accum_in_0_address1 = 'bx; + end + end else begin + accum_in_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_0_ce0 = 1'b1; + end else begin + accum_in_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + accum_in_0_ce1 = 1'b1; + end else begin + accum_in_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce0 = 1'b1; + end else begin + accum_out_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + accum_out_ce1 = 1'b1; + end else begin + accum_out_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_2_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we0 = 1'b1; + end else begin + accum_out_we0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_2_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + accum_out_we1 = 1'b1; + end else begin + accum_out_we1 = 1'b0; + end +end + +always @ (*) begin + if ((tmp_reg_494 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state4 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((tmp_2_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + if ((trunc_ln33_fu_430_p1 == 3'd0)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_0_01_reg_266; + end else if ((1'b1 == ap_condition_518)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_6_07_reg_194; + end else if ((trunc_ln33_fu_430_p1 == 3'd4)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_4_05_reg_218; + end else if ((trunc_ln33_fu_430_p1 == 3'd2)) begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = psum_2_03_reg_242; + end else begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = 'bx; + end + end else begin + ap_phi_mux_phi_ln45_phi_fu_292_p8 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (tmp_reg_494 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_x_phi_fu_174_p4 = add_ln25_reg_558; + end else begin + ap_phi_mux_x_phi_fu_174_p4 = x_reg_170; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state14)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_307_p0 = ap_phi_mux_psum_6_07_phi_fu_198_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_307_p0 = ap_phi_mux_psum_4_05_phi_fu_222_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_307_p0 = ap_phi_mux_psum_2_03_phi_fu_246_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_307_p0 = grp_fu_307_p2; + end else begin + grp_fu_307_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_307_p1 = accum_in_0_load_6_reg_583; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_307_p1 = accum_in_0_load_4_reg_563; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_307_p1 = accum_in_0_load_2_reg_538; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_307_p1 = accum_in_0_load_reg_518; + end else begin + grp_fu_307_p1 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_312_p0 = ap_phi_mux_psum_7_08_phi_fu_186_p4; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_312_p0 = ap_phi_mux_psum_5_06_phi_fu_210_p4; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_312_p0 = ap_phi_mux_psum_3_04_phi_fu_234_p4; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_312_p0 = grp_fu_312_p2; + end else begin + grp_fu_312_p0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_312_p1 = accum_in_0_load_7_reg_588; + end else if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + grp_fu_312_p1 = accum_in_0_load_5_reg_568; + end else if (((1'b0 == ap_block_pp0_stage3) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_312_p1 = accum_in_0_load_3_reg_543; + end else if (((1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + grp_fu_312_p1 = accum_in_0_load_1_reg_523; + end else begin + grp_fu_312_p1 = 'bx; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_494 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((1'b0 == ap_block_pp0_stage2_subdone) & (tmp_reg_494 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state12; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + if (((tmp_2_fu_417_p3 == 1'd0) & (1'b1 == ap_CS_fsm_state13))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_state14; + end + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_out_address0 = zext_ln33_1_fu_446_p1; + +assign accum_out_address1 = zext_ln33_fu_425_p1; + +assign accum_out_d0 = ((icmp_ln45_2_fu_479_p2[0:0] == 1'b1) ? psum_5_06_reg_206 : select_ln45_1_fu_471_p3); + +assign accum_out_d1 = ap_phi_mux_phi_ln45_phi_fu_292_p8; + +assign add_ln25_fu_391_p2 = (x_reg_170 + 9'd8); + +assign add_ln33_fu_434_p2 = (q_reg_278 + 4'd2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd5]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd6]; + +assign ap_CS_fsm_state14 = ap_CS_fsm[32'd7]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state10_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state11_pp0_stage1_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state9_pp0_stage3_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_condition_518 = (~(trunc_ln33_fu_430_p1 == 3'd0) & ~(trunc_ln33_fu_430_p1 == 3'd4) & ~(trunc_ln33_fu_430_p1 == 3'd2)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign ap_phi_mux_psum_2_03_phi_fu_246_p4 = grp_fu_307_p2; + +assign ap_phi_mux_psum_3_04_phi_fu_234_p4 = grp_fu_312_p2; + +assign ap_phi_mux_psum_4_05_phi_fu_222_p4 = grp_fu_307_p2; + +assign ap_phi_mux_psum_5_06_phi_fu_210_p4 = grp_fu_312_p2; + +assign ap_phi_mux_psum_6_07_phi_fu_198_p4 = grp_fu_307_p2; + +assign ap_phi_mux_psum_7_08_phi_fu_186_p4 = grp_fu_312_p2; + +assign icmp_ln45_1_fu_465_p2 = ((or_ln33_fu_440_p2 == 3'd3) ? 1'b1 : 1'b0); + +assign icmp_ln45_2_fu_479_p2 = ((or_ln33_fu_440_p2 == 3'd5) ? 1'b1 : 1'b0); + +assign icmp_ln45_fu_451_p2 = ((or_ln33_fu_440_p2 == 3'd1) ? 1'b1 : 1'b0); + +assign or_ln29_1_fu_351_p2 = (trunc_ln25_reg_498 | 8'd2); + +assign or_ln29_2_fu_361_p2 = (trunc_ln25_reg_498 | 8'd3); + +assign or_ln29_3_fu_371_p2 = (trunc_ln25_reg_498 | 8'd4); + +assign or_ln29_4_fu_381_p2 = (trunc_ln25_reg_498 | 8'd5); + +assign or_ln29_5_fu_397_p2 = (trunc_ln25_reg_498 | 8'd6); + +assign or_ln29_6_fu_407_p2 = (trunc_ln25_reg_498 | 8'd7); + +assign or_ln29_fu_340_p2 = (trunc_ln25_fu_336_p1 | 8'd1); + +assign or_ln33_fu_440_p2 = (trunc_ln33_fu_430_p1 | 3'd1); + +assign select_ln45_1_fu_471_p3 = ((icmp_ln45_1_fu_465_p2[0:0] == 1'b1) ? psum_3_04_reg_230 : select_ln45_fu_457_p3); + +assign select_ln45_fu_457_p3 = ((icmp_ln45_fu_451_p2[0:0] == 1'b1) ? psum_1_02_reg_254 : psum_7_08_reg_182); + +assign tmp_2_fu_417_p3 = q_reg_278[32'd3]; + +assign tmp_fu_323_p3 = ap_phi_mux_x_phi_fu_174_p4[32'd8]; + +assign trunc_ln25_fu_336_p1 = ap_phi_mux_x_phi_fu_174_p4[7:0]; + +assign trunc_ln33_fu_430_p1 = q_reg_278[2:0]; + +assign zext_ln25_fu_331_p1 = ap_phi_mux_x_phi_fu_174_p4; + +assign zext_ln29_1_fu_356_p1 = or_ln29_1_fu_351_p2; + +assign zext_ln29_2_fu_366_p1 = or_ln29_2_fu_361_p2; + +assign zext_ln29_3_fu_376_p1 = or_ln29_3_fu_371_p2; + +assign zext_ln29_4_fu_386_p1 = or_ln29_4_fu_381_p2; + +assign zext_ln29_5_fu_402_p1 = or_ln29_5_fu_397_p2; + +assign zext_ln29_6_fu_412_p1 = or_ln29_6_fu_407_p2; + +assign zext_ln29_fu_346_p1 = or_ln29_fu_340_p2; + +assign zext_ln33_1_fu_446_p1 = or_ln33_fu_440_p2; + +assign zext_ln33_fu_425_p1 = q_reg_278; + +endmodule //td_fused_top_tdf9_accum_1 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_accum_2 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + accum_in_2, + accum_in_2_ap_vld, + accum_in_address0, + accum_in_ce0, + accum_in_q0 +); + +parameter ap_ST_fsm_state1 = 7'd1; +parameter ap_ST_fsm_state2 = 7'd2; +parameter ap_ST_fsm_state3 = 7'd4; +parameter ap_ST_fsm_state4 = 7'd8; +parameter ap_ST_fsm_state5 = 7'd16; +parameter ap_ST_fsm_state6 = 7'd32; +parameter ap_ST_fsm_state7 = 7'd64; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] accum_in_2; +output accum_in_2_ap_vld; +output [2:0] accum_in_address0; +output accum_in_ce0; +input [15:0] accum_in_q0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg[15:0] accum_in_2; +reg accum_in_2_ap_vld; +reg accum_in_ce0; + +reg ap_done_reg; + reg [6:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [3:0] add_ln57_fu_74_p2; +reg [3:0] add_ln57_reg_91; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln57_fu_85_p2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_68_p2; +wire ap_CS_fsm_state7; +reg [3:0] i_1_1_reg_44; +reg ap_block_state1; +reg [15:0] sum_reg_55; +wire [63:0] zext_ln57_fu_80_p1; +reg [15:0] accum_in_2_preg; +reg [6:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 7'd1; +#0 accum_in_2_preg = 16'd0; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U568( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sum_reg_55), + .din1(accum_in_q0), + .dout(grp_fu_68_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + accum_in_2_preg <= 16'd0; + end else begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_2_preg <= sum_reg_55; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + i_1_1_reg_44 <= 4'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + i_1_1_reg_44 <= add_ln57_reg_91; + end +end + +always @ (posedge ap_clk) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + sum_reg_55 <= 16'd0; + end else if ((1'b1 == ap_CS_fsm_state7)) begin + sum_reg_55 <= grp_fu_68_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln57_reg_91 <= add_ln57_fu_74_p2; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_2 = sum_reg_55; + end else begin + accum_in_2 = accum_in_2_preg; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + accum_in_2_ap_vld = 1'b1; + end else begin + accum_in_2_ap_vld = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + accum_in_ce0 = 1'b1; + end else begin + accum_in_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + if (((icmp_ln57_fu_85_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state3; + end + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state2; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign accum_in_address0 = zext_ln57_fu_80_p1; + +assign add_ln57_fu_74_p2 = (i_1_1_reg_44 + 4'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6]; + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign icmp_ln57_fu_85_p2 = ((i_1_1_reg_44 == 4'd8) ? 1'b1 : 1'b0); + +assign zext_ln57_fu_80_p1 = i_1_1_reg_44; + +endmodule //td_fused_top_tdf9_accum_2 +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf9_adjustments_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 48; +parameter AWIDTH = 6; +parameter MEM_SIZE = 64; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf9_adjustments( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd48; +parameter AddressRange = 32'd64; +parameter AddressWidth = 32'd6; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf9_adjustments_ram td_fused_top_tdf9_adjustments_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_adjust ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + sums_read, + adjustments_address0, + adjustments_ce0, + adjustments_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + ap_return +); + +parameter ap_ST_fsm_state1 = 17'd1; +parameter ap_ST_fsm_state2 = 17'd2; +parameter ap_ST_fsm_state3 = 17'd4; +parameter ap_ST_fsm_state4 = 17'd8; +parameter ap_ST_fsm_state5 = 17'd16; +parameter ap_ST_fsm_state6 = 17'd32; +parameter ap_ST_fsm_state7 = 17'd64; +parameter ap_ST_fsm_state8 = 17'd128; +parameter ap_ST_fsm_state9 = 17'd256; +parameter ap_ST_fsm_state10 = 17'd512; +parameter ap_ST_fsm_state11 = 17'd1024; +parameter ap_ST_fsm_state12 = 17'd2048; +parameter ap_ST_fsm_state13 = 17'd4096; +parameter ap_ST_fsm_state14 = 17'd8192; +parameter ap_ST_fsm_state15 = 17'd16384; +parameter ap_ST_fsm_state16 = 17'd32768; +parameter ap_ST_fsm_state17 = 17'd65536; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] sums_read; +output [5:0] adjustments_address0; +output adjustments_ce0; +input [47:0] adjustments_q0; +input [5:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [15:0] ap_return; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg adjustments_ce0; +reg indices_23_read; + +reg ap_done_reg; + reg [16:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +wire ap_CS_fsm_state4; +reg [15:0] tmp_7_i_i_reg_167; +reg [15:0] tmp_8_i_i_reg_172; +wire [15:0] grp_fu_81_p2; +reg [15:0] sub_i_i_i_reg_177; +wire ap_CS_fsm_state8; +wire ap_CS_fsm_state9; +wire [15:0] grp_fu_86_p2; +reg [15:0] mul_i_i_i_reg_187; +wire ap_CS_fsm_state12; +wire ap_CS_fsm_state13; +wire [63:0] zext_ln220_fu_90_p1; +reg ap_block_state1; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state3; +wire [15:0] grp_fu_77_p1; +wire [15:0] grp_fu_81_p1; +wire [15:0] grp_fu_86_p1; +wire [15:0] trunc_ln220_fu_95_p1; +wire [15:0] grp_fu_77_p2; +wire ap_CS_fsm_state17; +wire [15:0] bitcast_ln648_fu_132_p1; +wire [0:0] tmp_fu_136_p3; +reg [16:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 17'd1; +end + +td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hadd_16ns_16ns_16_5_full_dsp_1_U572( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(mul_i_i_i_reg_187), + .din1(grp_fu_77_p1), + .dout(grp_fu_77_p2) +); + +td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 5 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hsub_16ns_16ns_16_5_full_dsp_1_U573( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sums_read), + .din1(grp_fu_81_p1), + .dout(grp_fu_81_p2) +); + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U574( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(sub_i_i_i_reg_177), + .din1(grp_fu_86_p1), + .dout(grp_fu_86_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state12)) begin + mul_i_i_i_reg_187 <= grp_fu_86_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + sub_i_i_i_reg_177 <= grp_fu_81_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tmp_7_i_i_reg_167 <= {{adjustments_q0[31:16]}}; + tmp_8_i_i_reg_172 <= {{adjustments_q0[47:32]}}; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2) | (~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1)))) begin + adjustments_ce0 = 1'b1; + end else begin + adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state17)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + ap_NS_fsm = ap_ST_fsm_state5; + end + ap_ST_fsm_state5 : begin + ap_NS_fsm = ap_ST_fsm_state6; + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state7; + end + ap_ST_fsm_state7 : begin + ap_NS_fsm = ap_ST_fsm_state8; + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state9; + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state10; + end + ap_ST_fsm_state10 : begin + ap_NS_fsm = ap_ST_fsm_state11; + end + ap_ST_fsm_state11 : begin + ap_NS_fsm = ap_ST_fsm_state12; + end + ap_ST_fsm_state12 : begin + ap_NS_fsm = ap_ST_fsm_state13; + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state14; + end + ap_ST_fsm_state14 : begin + ap_NS_fsm = ap_ST_fsm_state15; + end + ap_ST_fsm_state15 : begin + ap_NS_fsm = ap_ST_fsm_state16; + end + ap_ST_fsm_state16 : begin + ap_NS_fsm = ap_ST_fsm_state17; + end + ap_ST_fsm_state17 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign adjustments_address0 = zext_ln220_fu_90_p1; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12]; + +assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8]; + +always @ (*) begin + ap_block_state1 = ((indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_return = ((tmp_fu_136_p3[0:0] == 1'b1) ? 16'd0 : grp_fu_77_p2); + +assign bitcast_ln648_fu_132_p1 = grp_fu_77_p2; + +assign grp_fu_77_p1 = tmp_8_i_i_reg_172; + +assign grp_fu_81_p1 = trunc_ln220_fu_95_p1; + +assign grp_fu_86_p1 = tmp_7_i_i_reg_167; + +assign tmp_fu_136_p3 = bitcast_ln648_fu_132_p1[32'd15]; + +assign trunc_ln220_fu_95_p1 = adjustments_q0[15:0]; + +assign zext_ln220_fu_90_p1 = indices_23_dout; + +endmodule //td_fused_top_tdf9_adjust +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_dot_product ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_q0, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_q0, + products_0_address0, + products_0_ce0, + products_0_we0, + products_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state9 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [7:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +input [15:0] ifmap_vec_0_0_q0; +output [7:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +input [15:0] weight_vecs_0_0_0_q0; +output [7:0] products_0_address0; +output products_0_ce0; +output products_0_we0; +output [15:0] products_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg ifmap_vec_0_0_ce0; +reg weight_vecs_0_0_0_ce0; +reg products_0_ce0; +reg products_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [8:0] ic_0_0_reg_69; +wire [8:0] add_ln149_fu_84_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_state6_pp0_stage0_iter4; +wire ap_block_state7_pp0_stage0_iter5; +wire ap_block_state8_pp0_stage0_iter6; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln149_fu_90_p2; +reg [0:0] icmp_ln149_reg_107; +reg [0:0] icmp_ln149_reg_107_pp0_iter1_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter2_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter3_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter4_reg; +reg [0:0] icmp_ln149_reg_107_pp0_iter5_reg; +wire [63:0] idxprom17_0_0_fu_96_p1; +reg [63:0] idxprom17_0_0_reg_111; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter1_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter2_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter3_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter4_reg; +reg [63:0] idxprom17_0_0_reg_111_pp0_iter5_reg; +reg [15:0] ifmap_vec_0_0_load_reg_126; +reg [15:0] weight_vecs_0_0_0_load_reg_131; +wire [15:0] grp_fu_80_p2; +reg [15:0] mul_reg_136; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg ap_enable_reg_pp0_iter4; +reg ap_enable_reg_pp0_iter5; +reg ap_enable_reg_pp0_iter6; +wire ap_block_pp0_stage0; +wire ap_CS_fsm_state9; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +#0 ap_enable_reg_pp0_iter4 = 1'b0; +#0 ap_enable_reg_pp0_iter5 = 1'b0; +#0 ap_enable_reg_pp0_iter6 = 1'b0; +end + +td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 16 ), + .din1_WIDTH( 16 ), + .dout_WIDTH( 16 )) +hmul_16ns_16ns_16_4_max_dsp_1_U560( + .clk(ap_clk), + .reset(ap_rst), + .ce(1'b1), + .din0(ifmap_vec_0_0_load_reg_126), + .din1(weight_vecs_0_0_0_load_reg_131), + .dout(grp_fu_80_p2) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter4 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter5 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter6 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_fu_90_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ic_0_0_reg_69 <= add_ln149_fu_84_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ic_0_0_reg_69 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln149_reg_107 <= icmp_ln149_fu_90_p2; + icmp_ln149_reg_107_pp0_iter1_reg <= icmp_ln149_reg_107; + idxprom17_0_0_reg_111_pp0_iter1_reg[8 : 0] <= idxprom17_0_0_reg_111[8 : 0]; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln149_reg_107_pp0_iter2_reg <= icmp_ln149_reg_107_pp0_iter1_reg; + icmp_ln149_reg_107_pp0_iter3_reg <= icmp_ln149_reg_107_pp0_iter2_reg; + icmp_ln149_reg_107_pp0_iter4_reg <= icmp_ln149_reg_107_pp0_iter3_reg; + icmp_ln149_reg_107_pp0_iter5_reg <= icmp_ln149_reg_107_pp0_iter4_reg; + idxprom17_0_0_reg_111_pp0_iter2_reg[8 : 0] <= idxprom17_0_0_reg_111_pp0_iter1_reg[8 : 0]; + idxprom17_0_0_reg_111_pp0_iter3_reg[8 : 0] <= idxprom17_0_0_reg_111_pp0_iter2_reg[8 : 0]; + idxprom17_0_0_reg_111_pp0_iter4_reg[8 : 0] <= idxprom17_0_0_reg_111_pp0_iter3_reg[8 : 0]; + idxprom17_0_0_reg_111_pp0_iter5_reg[8 : 0] <= idxprom17_0_0_reg_111_pp0_iter4_reg[8 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_fu_90_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + idxprom17_0_0_reg_111[8 : 0] <= idxprom17_0_0_fu_96_p1[8 : 0]; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_reg_107 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_load_reg_126 <= ifmap_vec_0_0_q0; + weight_vecs_0_0_0_load_reg_131 <= weight_vecs_0_0_0_q0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln149_reg_107_pp0_iter4_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001))) begin + mul_reg_136 <= grp_fu_80_p2; + end +end + +always @ (*) begin + if ((icmp_ln149_fu_90_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state9)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter6 == 1'b1))) begin + products_0_ce0 = 1'b1; + end else begin + products_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln149_reg_107_pp0_iter5_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter6 == 1'b1))) begin + products_0_we0 = 1'b1; + end else begin + products_0_we0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln149_fu_90_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter6 == 1'b1) & (ap_enable_reg_pp0_iter5 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln149_fu_90_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter6 == 1'b1) & (ap_enable_reg_pp0_iter5 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state9; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state9 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln149_fu_84_p2 = (ic_0_0_reg_69 + 9'd1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state9 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter4 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter5 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage0_iter6 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign icmp_ln149_fu_90_p2 = ((ic_0_0_reg_69 == 9'd256) ? 1'b1 : 1'b0); + +assign idxprom17_0_0_fu_96_p1 = ic_0_0_reg_69; + +assign ifmap_vec_0_0_address0 = idxprom17_0_0_fu_96_p1; + +assign products_0_address0 = idxprom17_0_0_reg_111_pp0_iter5_reg; + +assign products_0_d0 = mul_reg_136; + +assign weight_vecs_0_0_0_address0 = idxprom17_0_0_fu_96_p1; + +always @ (posedge ap_clk) begin + idxprom17_0_0_reg_111[63:9] <= 55'b0000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter1_reg[63:9] <= 55'b0000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter2_reg[63:9] <= 55'b0000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter3_reg[63:9] <= 55'b0000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter4_reg[63:9] <= 55'b0000000000000000000000000000000000000000000000000000000; + idxprom17_0_0_reg_111_pp0_iter5_reg[63:9] <= 55'b0000000000000000000000000000000000000000000000000000000; +end + +endmodule //td_fused_top_tdf9_dot_product +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_tdf9_filters_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 14; +parameter MEM_SIZE = 16384; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; +reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_tdf9_filters( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd16384; +parameter AddressWidth = 32'd14; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_tdf9_filters_ram td_fused_top_tdf9_filters_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_get_next_ijk ( + ap_clk, + ap_rst, + ap_start, + start_full_n, + ap_done, + ap_continue, + ap_idle, + ap_ready, + start_out, + start_write, + indices_0_din, + indices_0_full_n, + indices_0_write, + indices_1_din, + indices_1_full_n, + indices_1_write, + indices_2_out_din, + indices_2_out_full_n, + indices_2_out_write, + indices_2_out1_din, + indices_2_out1_full_n, + indices_2_out1_write +); + +parameter ap_ST_fsm_state1 = 1'd1; + +input ap_clk; +input ap_rst; +input ap_start; +input start_full_n; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output start_out; +output start_write; +output [15:0] indices_0_din; +input indices_0_full_n; +output indices_0_write; +output [15:0] indices_1_din; +input indices_1_full_n; +output indices_1_write; +output [5:0] indices_2_out_din; +input indices_2_out_full_n; +output indices_2_out_write; +output [5:0] indices_2_out1_din; +input indices_2_out1_full_n; +output indices_2_out1_write; + +reg ap_done; +reg ap_idle; +reg start_write; +reg indices_0_write; +reg indices_1_write; +reg indices_2_out_write; +reg indices_2_out1_write; + +reg real_start; +reg start_once_reg; +reg ap_done_reg; + reg [0:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg internal_ap_ready; +reg [15:0] i; +reg [15:0] j; +reg [15:0] k; +reg indices_0_blk_n; +reg indices_1_blk_n; +reg indices_2_out_blk_n; +reg indices_2_out1_blk_n; +reg [0:0] ap_phi_mux_j_flag_0_i_phi_fu_77_p6; +reg ap_block_state1; +wire [0:0] icmp_ln78_fu_141_p2; +wire [0:0] icmp_ln81_fu_154_p2; +reg [15:0] ap_phi_mux_j_new_0_i_phi_fu_91_p6; +wire [15:0] add_ln80_fu_147_p2; +reg [15:0] ap_phi_mux_k_new_0_i_phi_fu_104_p6; +wire [15:0] add_ln77_fu_134_p2; +wire [15:0] select_ln84_fu_172_p3; +wire [5:0] trunc_ln76_fu_128_p1; +wire [15:0] add_ln83_fu_160_p2; +wire [0:0] icmp_ln84_fu_166_p2; +reg [0:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 start_once_reg = 1'b0; +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 1'd1; +#0 i = 16'd0; +#0 j = 16'd0; +#0 k = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + start_once_reg <= 1'b0; + end else begin + if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin + start_once_reg <= 1'b1; + end else if ((internal_ap_ready == 1'b1)) begin + start_once_reg <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + i <= select_ln84_fu_172_p3; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (ap_phi_mux_j_flag_0_i_phi_fu_77_p6 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + j <= ap_phi_mux_j_new_0_i_phi_fu_91_p6; + end +end + +always @ (posedge ap_clk) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + k <= ap_phi_mux_k_new_0_i_phi_fu_104_p6; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_j_flag_0_i_phi_fu_77_p6 = 1'd0; + end else if ((((icmp_ln81_fu_154_p2 == 1'd0) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_j_flag_0_i_phi_fu_77_p6 = 1'd1; + end else begin + ap_phi_mux_j_flag_0_i_phi_fu_77_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin + if ((icmp_ln81_fu_154_p2 == 1'd0)) begin + ap_phi_mux_j_new_0_i_phi_fu_91_p6 = add_ln80_fu_147_p2; + end else if ((icmp_ln81_fu_154_p2 == 1'd1)) begin + ap_phi_mux_j_new_0_i_phi_fu_91_p6 = 16'd0; + end else begin + ap_phi_mux_j_new_0_i_phi_fu_91_p6 = 'bx; + end + end else begin + ap_phi_mux_j_new_0_i_phi_fu_91_p6 = 'bx; + end +end + +always @ (*) begin + if (((icmp_ln78_fu_141_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_phi_mux_k_new_0_i_phi_fu_104_p6 = add_ln77_fu_134_p2; + end else if ((((icmp_ln81_fu_154_p2 == 1'd0) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)) | ((icmp_ln81_fu_154_p2 == 1'd1) & (icmp_ln78_fu_141_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_phi_mux_k_new_0_i_phi_fu_104_p6 = 16'd0; + end else begin + ap_phi_mux_k_new_0_i_phi_fu_104_p6 = 'bx; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_blk_n = indices_0_full_n; + end else begin + indices_0_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_0_write = 1'b1; + end else begin + indices_0_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_blk_n = indices_1_full_n; + end else begin + indices_1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_1_write = 1'b1; + end else begin + indices_1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_blk_n = indices_2_out1_full_n; + end else begin + indices_2_out1_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out1_write = 1'b1; + end else begin + indices_2_out1_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_blk_n = indices_2_out_full_n; + end else begin + indices_2_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_2_out_write = 1'b1; + end else begin + indices_2_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + internal_ap_ready = 1'b1; + end else begin + internal_ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin + real_start = 1'b0; + end else begin + real_start = ap_start; + end +end + +always @ (*) begin + if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin + start_write = 1'b1; + end else begin + start_write = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln77_fu_134_p2 = (k + 16'd1); + +assign add_ln80_fu_147_p2 = (j + 16'd1); + +assign add_ln83_fu_160_p2 = (i + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +always @ (*) begin + ap_block_state1 = ((real_start == 1'b0) | (indices_2_out1_full_n == 1'b0) | (indices_2_out_full_n == 1'b0) | (indices_1_full_n == 1'b0) | (indices_0_full_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_ready = internal_ap_ready; + +assign icmp_ln78_fu_141_p2 = ((add_ln77_fu_134_p2 == 16'd64) ? 1'b1 : 1'b0); + +assign icmp_ln81_fu_154_p2 = ((add_ln80_fu_147_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign icmp_ln84_fu_166_p2 = ((add_ln83_fu_160_p2 == 16'd14) ? 1'b1 : 1'b0); + +assign indices_0_din = i; + +assign indices_1_din = j; + +assign indices_2_out1_din = trunc_ln76_fu_128_p1; + +assign indices_2_out_din = trunc_ln76_fu_128_p1; + +assign select_ln84_fu_172_p3 = ((icmp_ln84_fu_166_p2[0:0] == 1'b1) ? 16'd0 : add_ln83_fu_160_p2); + +assign start_out = real_start; + +assign trunc_ln76_fu_128_p1 = k[5:0]; + +endmodule //td_fused_top_tdf9_get_next_ijk +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_readFilters62 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + filter_data_address0, + filter_data_ce0, + filter_data_q0, + indices_23_dout, + indices_23_empty_n, + indices_23_read, + weight_vecs_0_0_0_address0, + weight_vecs_0_0_0_ce0, + weight_vecs_0_0_0_we0, + weight_vecs_0_0_0_d0 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state6 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [13:0] filter_data_address0; +output filter_data_ce0; +input [15:0] filter_data_q0; +input [5:0] indices_23_dout; +input indices_23_empty_n; +output indices_23_read; +output [7:0] weight_vecs_0_0_0_address0; +output weight_vecs_0_0_0_ce0; +output weight_vecs_0_0_0_we0; +output [15:0] weight_vecs_0_0_0_d0; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg filter_data_ce0; +reg indices_23_read; +reg weight_vecs_0_0_0_ce0; +reg weight_vecs_0_0_0_we0; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_23_blk_n; +reg [8:0] kk_0_0_i_i_reg_93; +reg [8:0] kk_0_0_i_i_reg_93_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_pp0_stage0_11001; +reg [8:0] kk_0_0_i_i_reg_93_pp0_iter2_reg; +wire [13:0] tmp_fu_105_p3; +reg [13:0] tmp_reg_144; +wire [8:0] add_ln49_fu_113_p2; +reg [8:0] add_ln49_reg_149; +reg ap_enable_reg_pp0_iter0; +wire [0:0] icmp_ln49_fu_119_p2; +reg [0:0] icmp_ln49_reg_154; +reg [0:0] icmp_ln49_reg_154_pp0_iter1_reg; +reg [0:0] icmp_ln49_reg_154_pp0_iter2_reg; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state2; +reg ap_enable_reg_pp0_iter1; +reg ap_enable_reg_pp0_iter2; +reg ap_enable_reg_pp0_iter3; +reg [8:0] ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4; +wire ap_block_pp0_stage0; +wire [63:0] zext_ln55_1_fu_134_p1; +wire [63:0] idxprom16_0_0_i_i_fu_139_p1; +wire [13:0] zext_ln55_fu_125_p1; +wire [13:0] add_ln55_fu_129_p2; +wire ap_CS_fsm_state6; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin + ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state2); + end else begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_0_i_i_reg_93 <= add_ln49_reg_149; + end else if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + kk_0_0_i_i_reg_93 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln49_reg_149 <= add_ln49_fu_113_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln49_reg_154 <= icmp_ln49_fu_119_p2; + icmp_ln49_reg_154_pp0_iter1_reg <= icmp_ln49_reg_154; + kk_0_0_i_i_reg_93_pp0_iter1_reg <= kk_0_0_i_i_reg_93; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln49_reg_154_pp0_iter2_reg <= icmp_ln49_reg_154_pp0_iter1_reg; + kk_0_0_i_i_reg_93_pp0_iter2_reg <= kk_0_0_i_i_reg_93_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + tmp_reg_144[13 : 8] <= tmp_fu_105_p3[13 : 8]; + end +end + +always @ (*) begin + if ((icmp_ln49_fu_119_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state2 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state2 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln49_reg_154 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 = add_ln49_reg_149; + end else begin + ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 = kk_0_0_i_i_reg_93; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)))) begin + filter_data_ce0 = 1'b1; + end else begin + filter_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_blk_n = indices_23_empty_n; + end else begin + indices_23_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_23_read = 1'b1; + end else begin + indices_23_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1))) begin + weight_vecs_0_0_0_ce0 = 1'b1; + end else begin + weight_vecs_0_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln49_reg_154_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1))) begin + weight_vecs_0_0_0_we0 = 1'b1; + end else begin + weight_vecs_0_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln49_fu_119_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if ((((icmp_ln49_fu_119_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter3 == 1'b1) & (ap_enable_reg_pp0_iter2 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln49_fu_113_p2 = (ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 + 9'd1); + +assign add_ln55_fu_129_p2 = (tmp_reg_144 + zext_ln55_fu_125_p1); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_23_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign filter_data_address0 = zext_ln55_1_fu_134_p1; + +assign icmp_ln49_fu_119_p2 = ((ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4 == 9'd256) ? 1'b1 : 1'b0); + +assign idxprom16_0_0_i_i_fu_139_p1 = kk_0_0_i_i_reg_93_pp0_iter2_reg; + +assign tmp_fu_105_p3 = {{indices_23_dout}, {8'd0}}; + +assign weight_vecs_0_0_0_address0 = idxprom16_0_0_i_i_fu_139_p1; + +assign weight_vecs_0_0_0_d0 = filter_data_q0; + +assign zext_ln55_1_fu_134_p1 = add_ln55_fu_129_p2; + +assign zext_ln55_fu_125_p1 = ap_phi_mux_kk_0_0_i_i_phi_fu_97_p4; + +always @ (posedge ap_clk) begin + tmp_reg_144[7:0] <= 8'b00000000; +end + +endmodule //td_fused_top_tdf9_readFilters62 +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_readInputs ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + in_data_address0, + in_data_ce0, + in_data_q0, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + ifmap_vec_0_0_address0, + ifmap_vec_0_0_ce0, + ifmap_vec_0_0_we0, + ifmap_vec_0_0_d0, + ifmap_vec_0_0_address1, + ifmap_vec_0_0_ce1, + ifmap_vec_0_0_we1, + ifmap_vec_0_0_d1, + indices_01_out_din, + indices_01_out_full_n, + indices_01_out_write, + indices_12_out_din, + indices_12_out_full_n, + indices_12_out_write +); + +parameter ap_ST_fsm_state1 = 5'd1; +parameter ap_ST_fsm_state2 = 5'd2; +parameter ap_ST_fsm_pp0_stage0 = 5'd4; +parameter ap_ST_fsm_pp0_stage1 = 5'd8; +parameter ap_ST_fsm_state8 = 5'd16; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [13:0] in_data_address0; +output in_data_ce0; +input [63:0] in_data_q0; +input [15:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [15:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +output [7:0] ifmap_vec_0_0_address0; +output ifmap_vec_0_0_ce0; +output ifmap_vec_0_0_we0; +output [15:0] ifmap_vec_0_0_d0; +output [7:0] ifmap_vec_0_0_address1; +output ifmap_vec_0_0_ce1; +output ifmap_vec_0_0_we1; +output [15:0] ifmap_vec_0_0_d1; +output [3:0] indices_01_out_din; +input indices_01_out_full_n; +output indices_01_out_write; +output [7:0] indices_12_out_din; +input indices_12_out_full_n; +output indices_12_out_write; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg in_data_ce0; +reg indices_01_read; +reg indices_12_read; +reg[7:0] ifmap_vec_0_0_address0; +reg ifmap_vec_0_0_ce0; +reg ifmap_vec_0_0_we0; +reg[15:0] ifmap_vec_0_0_d0; +reg[7:0] ifmap_vec_0_0_address1; +reg ifmap_vec_0_0_ce1; +reg ifmap_vec_0_0_we1; +reg[15:0] ifmap_vec_0_0_d1; +reg indices_01_out_write; +reg indices_12_out_write; + +reg ap_done_reg; + reg [4:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg indices_01_blk_n; +reg indices_12_blk_n; +reg indices_01_out_blk_n; +reg indices_12_out_blk_n; +reg [8:0] kk_0_i_i_reg_180; +reg [8:0] kk_0_i_i_reg_180_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +wire ap_block_state3_pp0_stage0_iter0; +wire ap_block_state5_pp0_stage0_iter1; +wire ap_block_state7_pp0_stage0_iter2; +wire ap_block_pp0_stage0_11001; +wire [3:0] trunc_ln135_fu_192_p1; +reg [3:0] trunc_ln135_reg_434; +reg [15:0] col_coord_reg_439; +wire [0:0] is_padding_fu_214_p2; +reg [0:0] is_padding_reg_444; +wire [9:0] add_ln32_fu_274_p2; +reg [9:0] add_ln32_reg_454; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln25_fu_280_p2; +reg [0:0] icmp_ln25_reg_459; +reg [0:0] icmp_ln25_reg_459_pp0_iter1_reg; +wire [8:0] add_ln25_fu_308_p2; +reg [8:0] add_ln25_reg_468; +wire ap_CS_fsm_pp0_stage1; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state4_pp0_stage1_iter0; +wire ap_block_state6_pp0_stage1_iter1; +wire ap_block_pp0_stage1_11001; +wire [7:0] empty_56_fu_314_p1; +reg [7:0] empty_56_reg_473; +wire [15:0] select_ln33_2_fu_386_p3; +reg [15:0] select_ln33_2_reg_479; +wire [15:0] select_ln33_3_fu_407_p3; +reg [15:0] select_ln33_3_reg_484; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_exit_iter0_state3; +reg ap_enable_reg_pp0_iter1; +wire ap_block_pp0_stage1_subdone; +reg ap_enable_reg_pp0_iter2; +reg [8:0] ap_phi_mux_kk_0_i_i_phi_fu_184_p4; +wire ap_block_pp0_stage0; +wire [63:0] sext_ln32_fu_303_p1; +wire [63:0] zext_ln32_fu_318_p1; +wire ap_block_pp0_stage1; +wire [63:0] zext_ln32_2_fu_345_p1; +wire [63:0] zext_ln32_3_fu_419_p1; +wire [63:0] zext_ln32_4_fu_429_p1; +reg ap_block_state1; +wire [15:0] select_ln33_fu_331_p3; +wire [15:0] select_ln33_1_fu_364_p3; +wire [0:0] cmp7_i_i_fu_202_p2; +wire [0:0] icmp_ln24_fu_208_p2; +wire [3:0] empty_54_fu_220_p1; +wire [3:0] row_coord_int_fu_223_p3; +wire [7:0] tmp_fu_236_p3; +wire [4:0] tmp_4_fu_248_p3; +wire [8:0] zext_ln32_1_fu_244_p1; +wire [8:0] zext_ln32_5_fu_256_p1; +wire [8:0] sub_ln32_fu_260_p2; +wire [3:0] col_coord_int_fu_229_p3; +wire [9:0] sub_ln32_cast_fu_266_p1; +wire [9:0] zext_ln32_6_fu_270_p1; +wire [5:0] lshr_ln_fu_286_p4; +wire [15:0] tmp_1_fu_296_p3; +wire [15:0] trunc_ln32_fu_323_p1; +wire [15:0] bitcast_ln32_fu_327_p1; +wire [7:0] or_ln25_fu_339_p2; +wire [15:0] tmp_4_i_i_fu_350_p4; +wire [15:0] bitcast_ln32_1_fu_360_p1; +wire [15:0] tmp_5_i_i_fu_372_p4; +wire [15:0] bitcast_ln32_2_fu_382_p1; +wire [15:0] tmp_6_i_i_fu_393_p4; +wire [15:0] bitcast_ln32_3_fu_403_p1; +wire [7:0] or_ln25_1_fu_414_p2; +wire [7:0] or_ln25_2_fu_424_p2; +wire ap_CS_fsm_state8; +reg [4:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 5'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln25_reg_459 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + kk_0_i_i_reg_180 <= add_ln25_reg_468; + end else if ((1'b1 == ap_CS_fsm_state2)) begin + kk_0_i_i_reg_180 <= 9'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln25_reg_459 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln25_reg_468 <= add_ln25_fu_308_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + add_ln32_reg_454 <= add_ln32_fu_274_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + col_coord_reg_439 <= indices_12_dout; + is_padding_reg_444 <= is_padding_fu_214_p2; + trunc_ln135_reg_434 <= trunc_ln135_fu_192_p1; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (icmp_ln25_reg_459_pp0_iter1_reg == 1'd0))) begin + empty_56_reg_473 <= empty_56_fu_314_p1; + select_ln33_2_reg_479 <= select_ln33_2_fu_386_p3; + select_ln33_3_reg_484 <= select_ln33_3_fu_407_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln25_reg_459 <= icmp_ln25_fu_280_p2; + icmp_ln25_reg_459_pp0_iter1_reg <= icmp_ln25_reg_459; + kk_0_i_i_reg_180_pp0_iter1_reg <= kk_0_i_i_reg_180; + end +end + +always @ (*) begin + if ((icmp_ln25_fu_280_p2 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln25_reg_459 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ap_phi_mux_kk_0_i_i_phi_fu_184_p4 = add_ln25_reg_468; + end else begin + ap_phi_mux_kk_0_i_i_phi_fu_184_p4 = kk_0_i_i_reg_180; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state8)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_address0 = zext_ln32_4_fu_429_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_address0 = zext_ln32_2_fu_345_p1; + end else begin + ifmap_vec_0_0_address0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_address1 = zext_ln32_3_fu_419_p1; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_address1 = zext_ln32_fu_318_p1; + end else begin + ifmap_vec_0_0_address1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_ce0 = 1'b1; + end else begin + ifmap_vec_0_0_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)))) begin + ifmap_vec_0_0_ce1 = 1'b1; + end else begin + ifmap_vec_0_0_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_d0 = select_ln33_3_reg_484; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_d0 = select_ln33_1_fu_364_p3; + end else begin + ifmap_vec_0_0_d0 = 'bx; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + ifmap_vec_0_0_d1 = select_ln33_2_reg_479; + end else if (((1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + ifmap_vec_0_0_d1 = select_ln33_fu_331_p3; + end else begin + ifmap_vec_0_0_d1 = 'bx; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln25_reg_459_pp0_iter1_reg == 1'd0)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln25_reg_459_pp0_iter1_reg == 1'd0)))) begin + ifmap_vec_0_0_we0 = 1'b1; + end else begin + ifmap_vec_0_0_we0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln25_reg_459_pp0_iter1_reg == 1'd0)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (icmp_ln25_reg_459_pp0_iter1_reg == 1'd0)))) begin + ifmap_vec_0_0_we1 = 1'b1; + end else begin + ifmap_vec_0_0_we1 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin + in_data_ce0 = 1'b1; + end else begin + in_data_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_blk_n = indices_01_out_full_n; + end else begin + indices_01_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_out_write = 1'b1; + end else begin + indices_01_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_blk_n = indices_12_out_full_n; + end else begin + indices_12_out_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_out_write = 1'b1; + end else begin + indices_12_out_write = 1'b0; + end +end + +always @ (*) begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + ap_ST_fsm_pp0_stage0 : begin + if ((~((icmp_ln25_fu_280_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else if ((((icmp_ln25_fu_280_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin + ap_NS_fsm = ap_ST_fsm_state8; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((1'b0 == ap_block_pp0_stage1_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_state8 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln25_fu_308_p2 = (kk_0_i_i_reg_180 + 9'd4); + +assign add_ln32_fu_274_p2 = ((sub_ln32_cast_fu_266_p1) + (zext_ln32_6_fu_270_p1)); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state8 = ap_CS_fsm[32'd4]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((indices_12_out_full_n == 1'b0) | (indices_01_out_full_n == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln32_1_fu_360_p1 = tmp_4_i_i_fu_350_p4; + +assign bitcast_ln32_2_fu_382_p1 = tmp_5_i_i_fu_372_p4; + +assign bitcast_ln32_3_fu_403_p1 = tmp_6_i_i_fu_393_p4; + +assign bitcast_ln32_fu_327_p1 = trunc_ln32_fu_323_p1; + +assign cmp7_i_i_fu_202_p2 = ((indices_01_dout > 16'd13) ? 1'b1 : 1'b0); + +assign col_coord_int_fu_229_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 4'd0 : empty_54_fu_220_p1); + +assign empty_54_fu_220_p1 = col_coord_reg_439[3:0]; + +assign empty_56_fu_314_p1 = kk_0_i_i_reg_180_pp0_iter1_reg[7:0]; + +assign icmp_ln24_fu_208_p2 = ((indices_12_dout > 16'd13) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_280_p2 = ((ap_phi_mux_kk_0_i_i_phi_fu_184_p4 == 9'd256) ? 1'b1 : 1'b0); + +assign in_data_address0 = sext_ln32_fu_303_p1; + +assign indices_01_out_din = indices_01_dout[3:0]; + +assign indices_12_out_din = indices_12_dout[7:0]; + +assign is_padding_fu_214_p2 = (icmp_ln24_fu_208_p2 | cmp7_i_i_fu_202_p2); + +assign lshr_ln_fu_286_p4 = {{ap_phi_mux_kk_0_i_i_phi_fu_184_p4[7:2]}}; + +assign or_ln25_1_fu_414_p2 = (empty_56_reg_473 | 8'd2); + +assign or_ln25_2_fu_424_p2 = (empty_56_reg_473 | 8'd3); + +assign or_ln25_fu_339_p2 = (empty_56_fu_314_p1 | 8'd1); + +assign row_coord_int_fu_223_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 4'd0 : trunc_ln135_reg_434); + +assign select_ln33_1_fu_364_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_1_fu_360_p1); + +assign select_ln33_2_fu_386_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_2_fu_382_p1); + +assign select_ln33_3_fu_407_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_3_fu_403_p1); + +assign select_ln33_fu_331_p3 = ((is_padding_reg_444[0:0] == 1'b1) ? 16'd0 : bitcast_ln32_fu_327_p1); + +assign sext_ln32_fu_303_p1 = (tmp_1_fu_296_p3); + +assign sub_ln32_cast_fu_266_p1 = (sub_ln32_fu_260_p2); + +assign sub_ln32_fu_260_p2 = (zext_ln32_1_fu_244_p1 - zext_ln32_5_fu_256_p1); + +assign tmp_1_fu_296_p3 = {{add_ln32_reg_454}, {lshr_ln_fu_286_p4}}; + +assign tmp_4_fu_248_p3 = {{row_coord_int_fu_223_p3}, {1'd0}}; + +assign tmp_4_i_i_fu_350_p4 = {{in_data_q0[31:16]}}; + +assign tmp_5_i_i_fu_372_p4 = {{in_data_q0[47:32]}}; + +assign tmp_6_i_i_fu_393_p4 = {{in_data_q0[63:48]}}; + +assign tmp_fu_236_p3 = {{row_coord_int_fu_223_p3}, {4'd0}}; + +assign trunc_ln135_fu_192_p1 = indices_01_dout[3:0]; + +assign trunc_ln32_fu_323_p1 = in_data_q0[15:0]; + +assign zext_ln32_1_fu_244_p1 = tmp_fu_236_p3; + +assign zext_ln32_2_fu_345_p1 = or_ln25_fu_339_p2; + +assign zext_ln32_3_fu_419_p1 = or_ln25_1_fu_414_p2; + +assign zext_ln32_4_fu_429_p1 = or_ln25_2_fu_424_p2; + +assign zext_ln32_5_fu_256_p1 = tmp_4_fu_248_p3; + +assign zext_ln32_6_fu_270_p1 = col_coord_int_fu_229_p3; + +assign zext_ln32_fu_318_p1 = kk_0_i_i_reg_180_pp0_iter1_reg; + +endmodule //td_fused_top_tdf9_readInputs +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_tdf9_writeOutputs_unaligned ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + indices_01_dout, + indices_01_empty_n, + indices_01_read, + indices_12_dout, + indices_12_empty_n, + indices_12_read, + p_read, + out_data_address1, + out_data_ce1, + out_data_we1, + out_data_d1 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_state2 = 3'd2; +parameter ap_ST_fsm_state3 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [3:0] indices_01_dout; +input indices_01_empty_n; +output indices_01_read; +input [7:0] indices_12_dout; +input indices_12_empty_n; +output indices_12_read; +input [15:0] p_read; +output [11:0] out_data_address1; +output out_data_ce1; +output out_data_we1; +output [63:0] out_data_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg indices_01_read; +reg indices_12_read; +reg out_data_ce1; +reg out_data_we1; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [15:0] outputCount; +reg [15:0] outputChanIdx; +reg [15:0] outputRow_0; +reg [15:0] outputRow_1; +reg [15:0] outputRow_2; +reg [15:0] outputRow_3; +reg indices_01_blk_n; +reg indices_12_blk_n; +wire [7:0] add_ln94_fu_147_p2; +reg [7:0] add_ln94_reg_304; +wire [15:0] add_ln87_fu_192_p2; +wire ap_CS_fsm_state2; +wire [0:0] icmp_ln88_fu_198_p2; +reg [0:0] icmp_ln88_reg_317; +reg [15:0] ap_phi_mux_empty_phi_fu_114_p4; +reg [15:0] empty_reg_111; +wire ap_CS_fsm_state3; +wire [63:0] zext_ln94_2_fu_226_p1; +wire [15:0] select_ln97_fu_284_p3; +wire [1:0] trunc_ln86_fu_164_p1; +reg [15:0] ap_sig_allocacmp_outputRow_0_load; +reg [15:0] ap_sig_allocacmp_outputRow_1_load; +reg [15:0] ap_sig_allocacmp_outputRow_2_load; +reg [15:0] ap_sig_allocacmp_outputRow_3_load; +reg ap_block_state1; +wire [4:0] tmp_1_fu_129_p3; +wire [7:0] tmp_fu_121_p3; +wire [7:0] zext_ln94_fu_137_p1; +wire [7:0] sub_ln94_fu_141_p2; +wire [5:0] trunc_ln94_fu_212_p1; +wire [11:0] tmp_3_cast_fu_153_p3; +wire [11:0] zext_ln94_1_fu_216_p1; +wire [11:0] add_ln94_1_fu_220_p2; +wire [15:0] bitcast_ln94_3_fu_255_p1; +wire [15:0] bitcast_ln94_2_fu_247_p1; +wire [15:0] bitcast_ln94_1_fu_239_p1; +wire [15:0] bitcast_ln94_fu_231_p1; +wire [15:0] add_ln96_fu_272_p2; +wire [0:0] icmp_ln97_fu_278_p2; +reg [2:0] ap_NS_fsm; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 outputCount = 16'd0; +#0 outputChanIdx = 16'd0; +#0 outputRow_0 = 16'd0; +#0 outputRow_1 = 16'd0; +#0 outputRow_2 = 16'd0; +#0 outputRow_3 = 16'd0; +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state3)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_reg_317 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + empty_reg_111 <= 16'd0; + end else if (((icmp_ln88_fu_198_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin + empty_reg_111 <= add_ln87_fu_192_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state1)) begin + add_ln94_reg_304 <= add_ln94_fu_147_p2; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state2)) begin + icmp_ln88_reg_317 <= icmp_ln88_fu_198_p2; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln88_fu_198_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + outputChanIdx <= select_ln97_fu_284_p3; + end +end + +always @ (posedge ap_clk) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + outputCount <= ap_phi_mux_empty_phi_fu_114_p4; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_164_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_0 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_164_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_1 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_164_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_2 <= p_read; + end +end + +always @ (posedge ap_clk) begin + if (((trunc_ln86_fu_164_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state2))) begin + outputRow_3 <= p_read; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_reg_317 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin + ap_phi_mux_empty_phi_fu_114_p4 = 16'd0; + end else begin + ap_phi_mux_empty_phi_fu_114_p4 = empty_reg_111; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state3)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_164_p1 == 2'd0) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_0_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_0_load = outputRow_0; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_164_p1 == 2'd1) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_1_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_1_load = outputRow_1; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_164_p1 == 2'd2) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_2_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_2_load = outputRow_2; + end +end + +always @ (*) begin + if (((trunc_ln86_fu_164_p1 == 2'd3) & (1'b1 == ap_CS_fsm_state2))) begin + ap_sig_allocacmp_outputRow_3_load = p_read; + end else begin + ap_sig_allocacmp_outputRow_3_load = outputRow_3; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_blk_n = indices_01_empty_n; + end else begin + indices_01_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_01_read = 1'b1; + end else begin + indices_01_read = 1'b0; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_blk_n = indices_12_empty_n; + end else begin + indices_12_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indices_12_read = 1'b1; + end else begin + indices_12_read = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state2))) begin + out_data_ce1 = 1'b1; + end else begin + out_data_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln88_fu_198_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin + out_data_we1 = 1'b1; + end else begin + out_data_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln87_fu_192_p2 = (outputCount + 16'd1); + +assign add_ln94_1_fu_220_p2 = (tmp_3_cast_fu_153_p3 + zext_ln94_1_fu_216_p1); + +assign add_ln94_fu_147_p2 = (sub_ln94_fu_141_p2 + indices_12_dout); + +assign add_ln96_fu_272_p2 = (outputChanIdx + 16'd1); + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (indices_12_empty_n == 1'b0) | (indices_01_empty_n == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign bitcast_ln94_1_fu_239_p1 = ap_sig_allocacmp_outputRow_1_load; + +assign bitcast_ln94_2_fu_247_p1 = ap_sig_allocacmp_outputRow_2_load; + +assign bitcast_ln94_3_fu_255_p1 = ap_sig_allocacmp_outputRow_3_load; + +assign bitcast_ln94_fu_231_p1 = ap_sig_allocacmp_outputRow_0_load; + +assign icmp_ln88_fu_198_p2 = ((add_ln87_fu_192_p2 == 16'd4) ? 1'b1 : 1'b0); + +assign icmp_ln97_fu_278_p2 = ((add_ln96_fu_272_p2 == 16'd16) ? 1'b1 : 1'b0); + +assign out_data_address1 = zext_ln94_2_fu_226_p1; + +assign out_data_d1 = {{{{bitcast_ln94_3_fu_255_p1}, {bitcast_ln94_2_fu_247_p1}}, {bitcast_ln94_1_fu_239_p1}}, {bitcast_ln94_fu_231_p1}}; + +assign select_ln97_fu_284_p3 = ((icmp_ln97_fu_278_p2[0:0] == 1'b1) ? 16'd0 : add_ln96_fu_272_p2); + +assign sub_ln94_fu_141_p2 = (tmp_fu_121_p3 - zext_ln94_fu_137_p1); + +assign tmp_1_fu_129_p3 = {{indices_01_dout}, {1'd0}}; + +assign tmp_3_cast_fu_153_p3 = {{add_ln94_reg_304}, {4'd0}}; + +assign tmp_fu_121_p3 = {{indices_01_dout}, {4'd0}}; + +assign trunc_ln86_fu_164_p1 = outputCount[1:0]; + +assign trunc_ln94_fu_212_p1 = outputChanIdx[5:0]; + +assign zext_ln94_1_fu_216_p1 = trunc_ln94_fu_212_p1; + +assign zext_ln94_2_fu_226_p1 = add_ln94_1_fu_220_p2; + +assign zext_ln94_fu_137_p1 = tmp_1_fu_129_p3; + +endmodule //td_fused_top_tdf9_writeOutputs_unaligned +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_axi_in_p_ram (addr0, ce0, d0, we0, addr1, ce1, q1, addr2, ce2, q2, addr3, ce3, q3, addr4, ce4, q4, clk); + +parameter DWIDTH = 16; +parameter AWIDTH = 2; +parameter MEM_SIZE = 4; + +input[AWIDTH-1:0] addr0; +input ce0; +input[DWIDTH-1:0] d0; +input we0; +input[AWIDTH-1:0] addr1; +input ce1; +output reg[DWIDTH-1:0] q1; +input[AWIDTH-1:0] addr2; +input ce2; +output reg[DWIDTH-1:0] q2; +input[AWIDTH-1:0] addr3; +input ce3; +output reg[DWIDTH-1:0] q3; +input[AWIDTH-1:0] addr4; +input ce4; +output reg[DWIDTH-1:0] q4; +input clk; + +reg [DWIDTH-1:0] ram0[MEM_SIZE-1:0]; +reg [DWIDTH-1:0] ram1[MEM_SIZE-1:0]; +reg [DWIDTH-1:0] ram2[MEM_SIZE-1:0]; +reg [DWIDTH-1:0] ram3[MEM_SIZE-1:0]; + + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram0[addr0] <= d0; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + q1 <= ram0[addr1]; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram1[addr0] <= d0; + end +end + +always @(posedge clk) +begin + if (ce2) begin + q2 <= ram1[addr2]; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram2[addr0] <= d0; + end +end + +always @(posedge clk) +begin + if (ce3) begin + q3 <= ram2[addr3]; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + if (we0) + ram3[addr0] <= d0; + end +end + +always @(posedge clk) +begin + if (ce4) begin + q4 <= ram3[addr4]; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_axi_in_p( + reset, + clk, + address0, + ce0, + we0, + d0, + address1, + ce1, + q1, + address2, + ce2, + q2, + address3, + ce3, + q3, + address4, + ce4, + q4); + +parameter DataWidth = 32'd16; +parameter AddressRange = 32'd4; +parameter AddressWidth = 32'd2; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +input we0; +input[DataWidth - 1:0] d0; +input[AddressWidth - 1:0] address1; +input ce1; +output[DataWidth - 1:0] q1; +input[AddressWidth - 1:0] address2; +input ce2; +output[DataWidth - 1:0] q2; +input[AddressWidth - 1:0] address3; +input ce3; +output[DataWidth - 1:0] q3; +input[AddressWidth - 1:0] address4; +input ce4; +output[DataWidth - 1:0] q4; + + + +td_fused_top_td_fused_axi_in_p_ram td_fused_top_td_fused_axi_in_p_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .we0( we0 ), + .d0( d0 ), + .addr1( address1 ), + .ce1( ce1 ), + .q1( q1 ), + .addr2( address2 ), + .ce2( ce2 ), + .q2( q2 ), + .addr3( address3 ), + .ce3( ce3 ), + .q3( q3 ), + .addr4( address4 ), + .ce4( ce4 ), + .q4( q4 ) +); + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_td_fused_axi_in ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + stream_in_TDATA, + stream_in_TVALID, + stream_in_TREADY, + stream_in_TKEEP, + stream_in_TSTRB, + stream_in_TLAST, + fmaps_address1, + fmaps_ce1, + fmaps_we1, + fmaps_d1 +); + +parameter ap_ST_fsm_state1 = 3'd1; +parameter ap_ST_fsm_pp0_stage0 = 3'd2; +parameter ap_ST_fsm_state6 = 3'd4; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +input [15:0] stream_in_TDATA; +input stream_in_TVALID; +output stream_in_TREADY; +input [1:0] stream_in_TKEEP; +input [1:0] stream_in_TSTRB; +input [0:0] stream_in_TLAST; +output [15:0] fmaps_address1; +output fmaps_ce1; +output fmaps_we1; +output [63:0] fmaps_d1; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg stream_in_TREADY; +reg fmaps_ce1; +reg fmaps_we1; + +reg ap_done_reg; + reg [2:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg [17:0] indvar_flatten16_reg_185; +reg [9:0] indvar_flatten_reg_196; +reg [1:0] ch_reg_207; +reg [7:0] r_reg_218; +reg [7:0] c_reg_229; +wire [17:0] add_ln17_fu_240_p2; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state3_pp0_stage0_iter1; +wire ap_block_state4_pp0_stage0_iter2; +wire ap_block_state5_pp0_stage0_iter3; +wire ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln17_fu_246_p2; +reg [0:0] icmp_ln17_reg_483; +reg [0:0] icmp_ln17_reg_483_pp0_iter1_reg; +reg [0:0] icmp_ln17_reg_483_pp0_iter2_reg; +wire [0:0] icmp_ln18_fu_255_p2; +reg [0:0] icmp_ln18_reg_487; +reg [0:0] icmp_ln18_reg_487_pp0_iter1_reg; +wire [0:0] and_ln22_fu_273_p2; +reg [0:0] and_ln22_reg_493; +reg [0:0] and_ln22_reg_493_pp0_iter1_reg; +wire [0:0] icmp_ln25_fu_319_p2; +reg [0:0] icmp_ln25_reg_498; +reg [0:0] icmp_ln25_reg_498_pp0_iter1_reg; +wire [1:0] add_ln20_fu_330_p2; +wire [9:0] select_ln18_fu_342_p3; +wire [15:0] p_q4; +reg [15:0] p_load_3_reg_512; +reg ap_enable_reg_pp0_iter1; +wire [7:0] select_ln22_1_fu_363_p3; +reg [7:0] select_ln22_1_reg_517; +reg ap_enable_reg_pp0_iter2; +wire [7:0] select_ln19_48_fu_402_p3; +reg [7:0] select_ln19_48_reg_522; +reg ap_block_state1; +wire ap_block_pp0_stage0_subdone; +reg ap_condition_pp0_flush_enable; +reg ap_condition_pp0_exit_iter2_state4; +reg ap_enable_reg_pp0_iter3; +wire [1:0] p_address0; +reg p_ce0; +reg p_we0; +wire [15:0] p_d0; +wire [1:0] p_address1; +reg p_ce1; +wire [15:0] p_q1; +wire [1:0] p_address2; +reg p_ce2; +wire [15:0] p_q2; +wire [1:0] p_address3; +reg p_ce3; +wire [15:0] p_q3; +wire [1:0] p_address4; +reg p_ce4; +reg [7:0] ap_phi_mux_r_phi_fu_222_p4; +wire ap_block_pp0_stage0; +reg [7:0] ap_phi_mux_c_phi_fu_233_p4; +wire [63:0] zext_ln20_fu_293_p1; +wire [63:0] zext_ln27_2_fu_419_p1; +reg [15:0] tmp_data_1_fu_88; +wire [15:0] tmp_data_fu_310_p3; +wire [0:0] empty_154_nbread_fu_96_p5_0; +wire [0:0] icmp_ln20_fu_267_p2; +wire [0:0] xor_ln22_fu_261_p2; +wire [0:0] or_ln19_fu_279_p2; +wire [1:0] select_ln19_fu_285_p3; +wire [15:0] tmp_data_2_fu_306_p1; +wire [9:0] add_ln18_2_fu_336_p2; +wire [7:0] r_2_fu_350_p2; +wire [12:0] tmp_22_fu_378_p3; +wire [15:0] tmp_fu_370_p3; +wire [15:0] zext_ln27_fu_386_p1; +wire [7:0] select_ln22_fu_356_p3; +wire [7:0] c_2_fu_396_p2; +wire [15:0] sub_ln27_fu_390_p2; +wire [15:0] zext_ln27_1_fu_409_p1; +wire [15:0] add_ln27_fu_413_p2; +wire [15:0] bitcast_ln27_3_fu_436_p1; +wire [15:0] bitcast_ln27_2_fu_432_p1; +wire [15:0] bitcast_ln27_1_fu_428_p1; +wire [15:0] bitcast_ln27_fu_424_p1; +wire ap_CS_fsm_state6; +reg [2:0] ap_NS_fsm; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 3'd1; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter3 = 1'b0; +end + +td_fused_top_td_fused_axi_in_p #( + .DataWidth( 16 ), + .AddressRange( 4 ), + .AddressWidth( 2 )) +p_U( + .reset(ap_rst), + .clk(ap_clk), + .address0(p_address0), + .ce0(p_ce0), + .we0(p_we0), + .d0(p_d0), + .address1(p_address1), + .ce1(p_ce1), + .q1(p_q1), + .address2(p_address2), + .ce2(p_ce2), + .q2(p_q2), + .address3(p_address3), + .ce3(p_ce3), + .q3(p_q3), + .address4(p_address4), + .ce4(p_ce4), + .q4(p_q4) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if ((1'b1 == ap_condition_pp0_flush_enable)) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter2_state4) & (ap_enable_reg_pp0_iter1 == 1'b0)) | (~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1)))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter2_state4))) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter1; + end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter3 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_483_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1))) begin + c_reg_229 <= select_ln19_48_reg_522; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + c_reg_229 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_fu_246_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ch_reg_207 <= add_ln20_fu_330_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ch_reg_207 <= 2'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_fu_246_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten16_reg_185 <= add_ln17_fu_240_p2; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten16_reg_185 <= 18'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_fu_246_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_196 <= select_ln18_fu_342_p3; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_196 <= 10'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_483_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1))) begin + r_reg_218 <= select_ln22_1_reg_517; + end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + r_reg_218 <= 8'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_fu_246_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + and_ln22_reg_493 <= and_ln22_fu_273_p2; + icmp_ln18_reg_487 <= icmp_ln18_fu_255_p2; + icmp_ln25_reg_498 <= icmp_ln25_fu_319_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + and_ln22_reg_493_pp0_iter1_reg <= and_ln22_reg_493; + icmp_ln17_reg_483 <= icmp_ln17_fu_246_p2; + icmp_ln17_reg_483_pp0_iter1_reg <= icmp_ln17_reg_483; + icmp_ln18_reg_487_pp0_iter1_reg <= icmp_ln18_reg_487; + icmp_ln25_reg_498_pp0_iter1_reg <= icmp_ln25_reg_498; + end +end + +always @ (posedge ap_clk) begin + if ((1'b0 == ap_block_pp0_stage0_11001)) begin + icmp_ln17_reg_483_pp0_iter2_reg <= icmp_ln17_reg_483_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln25_reg_498 == 1'd1) & (icmp_ln17_reg_483 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + p_load_3_reg_512 <= p_q4; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_483_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + select_ln19_48_reg_522 <= select_ln19_48_fu_402_p3; + select_ln22_1_reg_517 <= select_ln22_1_fu_363_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_fu_246_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + tmp_data_1_fu_88 <= tmp_data_fu_310_p3; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_condition_pp0_exit_iter2_state4 = 1'b1; + end else begin + ap_condition_pp0_exit_iter2_state4 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln17_fu_246_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_condition_pp0_flush_enable = 1'b1; + end else begin + ap_condition_pp0_flush_enable = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln17_reg_483_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter3 == 1'b1))) begin + ap_phi_mux_c_phi_fu_233_p4 = select_ln19_48_reg_522; + end else begin + ap_phi_mux_c_phi_fu_233_p4 = c_reg_229; + end +end + +always @ (*) begin + if (((icmp_ln17_reg_483_pp0_iter2_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter3 == 1'b1))) begin + ap_phi_mux_r_phi_fu_222_p4 = select_ln22_1_reg_517; + end else begin + ap_phi_mux_r_phi_fu_222_p4 = r_reg_218; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state6)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter3 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin + fmaps_ce1 = 1'b1; + end else begin + fmaps_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln25_reg_498_pp0_iter1_reg == 1'd1) & (icmp_ln17_reg_483_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin + fmaps_we1 = 1'b1; + end else begin + fmaps_we1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + p_ce0 = 1'b1; + end else begin + p_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + p_ce1 = 1'b1; + end else begin + p_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + p_ce2 = 1'b1; + end else begin + p_ce2 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1))) begin + p_ce3 = 1'b1; + end else begin + p_ce3 = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + p_ce4 = 1'b1; + end else begin + p_ce4 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln17_fu_246_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + p_we0 = 1'b1; + end else begin + p_we0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln17_fu_246_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (stream_in_TVALID == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + stream_in_TREADY = 1'b1; + end else begin + stream_in_TREADY = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if (~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter2 == 1'b1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin + ap_NS_fsm = ap_ST_fsm_state6; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_state6 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln17_fu_240_p2 = (indvar_flatten16_reg_185 + 18'd1); + +assign add_ln18_2_fu_336_p2 = (indvar_flatten_reg_196 + 10'd1); + +assign add_ln20_fu_330_p2 = (select_ln19_fu_285_p3 + 2'd1); + +assign add_ln27_fu_413_p2 = (sub_ln27_fu_390_p2 + zext_ln27_1_fu_409_p1); + +assign and_ln22_fu_273_p2 = (xor_ln22_fu_261_p2 & icmp_ln20_fu_267_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state6 = ap_CS_fsm[32'd2]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1); + +assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage0_iter2 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage0_iter3 = ~(1'b1 == 1'b1); + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign bitcast_ln27_1_fu_428_p1 = p_q2; + +assign bitcast_ln27_2_fu_432_p1 = p_q1; + +assign bitcast_ln27_3_fu_436_p1 = p_load_3_reg_512; + +assign bitcast_ln27_fu_424_p1 = p_q3; + +assign c_2_fu_396_p2 = (select_ln22_fu_356_p3 + 8'd1); + +assign empty_154_nbread_fu_96_p5_0 = stream_in_TVALID; + +assign fmaps_address1 = zext_ln27_2_fu_419_p1; + +assign fmaps_d1 = {{{{bitcast_ln27_3_fu_436_p1}, {bitcast_ln27_2_fu_432_p1}}, {bitcast_ln27_1_fu_428_p1}}, {bitcast_ln27_fu_424_p1}}; + +assign icmp_ln17_fu_246_p2 = ((indvar_flatten16_reg_185 == 18'd150528) ? 1'b1 : 1'b0); + +assign icmp_ln18_fu_255_p2 = ((indvar_flatten_reg_196 == 10'd672) ? 1'b1 : 1'b0); + +assign icmp_ln20_fu_267_p2 = ((ch_reg_207 == 2'd3) ? 1'b1 : 1'b0); + +assign icmp_ln25_fu_319_p2 = ((select_ln19_fu_285_p3 == 2'd2) ? 1'b1 : 1'b0); + +assign or_ln19_fu_279_p2 = (icmp_ln18_fu_255_p2 | and_ln22_fu_273_p2); + +assign p_address0 = zext_ln20_fu_293_p1; + +assign p_address1 = 64'd2; + +assign p_address2 = 64'd1; + +assign p_address3 = 64'd0; + +assign p_address4 = 64'd3; + +assign p_d0 = ((empty_154_nbread_fu_96_p5_0[0:0] == 1'b1) ? tmp_data_2_fu_306_p1 : tmp_data_1_fu_88); + +assign r_2_fu_350_p2 = (ap_phi_mux_r_phi_fu_222_p4 + 8'd1); + +assign select_ln18_fu_342_p3 = ((icmp_ln18_fu_255_p2[0:0] == 1'b1) ? 10'd1 : add_ln18_2_fu_336_p2); + +assign select_ln19_48_fu_402_p3 = ((and_ln22_reg_493_pp0_iter1_reg[0:0] == 1'b1) ? c_2_fu_396_p2 : select_ln22_fu_356_p3); + +assign select_ln19_fu_285_p3 = ((or_ln19_fu_279_p2[0:0] == 1'b1) ? 2'd0 : ch_reg_207); + +assign select_ln22_1_fu_363_p3 = ((icmp_ln18_reg_487_pp0_iter1_reg[0:0] == 1'b1) ? r_2_fu_350_p2 : ap_phi_mux_r_phi_fu_222_p4); + +assign select_ln22_fu_356_p3 = ((icmp_ln18_reg_487_pp0_iter1_reg[0:0] == 1'b1) ? 8'd0 : ap_phi_mux_c_phi_fu_233_p4); + +assign sub_ln27_fu_390_p2 = (tmp_fu_370_p3 - zext_ln27_fu_386_p1); + +assign tmp_22_fu_378_p3 = {{select_ln22_1_fu_363_p3}, {5'd0}}; + +assign tmp_data_2_fu_306_p1 = stream_in_TDATA; + +assign tmp_data_fu_310_p3 = ((empty_154_nbread_fu_96_p5_0[0:0] == 1'b1) ? tmp_data_2_fu_306_p1 : tmp_data_1_fu_88); + +assign tmp_fu_370_p3 = {{select_ln22_1_fu_363_p3}, {8'd0}}; + +assign xor_ln22_fu_261_p2 = (icmp_ln18_fu_255_p2 ^ 1'd1); + +assign zext_ln20_fu_293_p1 = select_ln19_fu_285_p3; + +assign zext_ln27_1_fu_409_p1 = select_ln19_48_fu_402_p3; + +assign zext_ln27_2_fu_419_p1 = add_ln27_fu_413_p2; + +assign zext_ln27_fu_386_p1 = tmp_22_fu_378_p3; + +endmodule //td_fused_top_td_fused_axi_in +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_td_fused_axi_out ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + fmaps_address0, + fmaps_ce0, + fmaps_q0, + stream_out_TDATA, + stream_out_TVALID, + stream_out_TREADY, + stream_out_TKEEP, + stream_out_TSTRB, + stream_out_TLAST +); + +parameter ap_ST_fsm_state1 = 6'd1; +parameter ap_ST_fsm_pp0_stage0 = 6'd2; +parameter ap_ST_fsm_pp0_stage1 = 6'd4; +parameter ap_ST_fsm_pp0_stage2 = 6'd8; +parameter ap_ST_fsm_pp0_stage3 = 6'd16; +parameter ap_ST_fsm_state13 = 6'd32; + +input ap_clk; +input ap_rst; +input ap_start; +output ap_done; +input ap_continue; +output ap_idle; +output ap_ready; +output [15:0] fmaps_address0; +output fmaps_ce0; +input [63:0] fmaps_q0; +output [15:0] stream_out_TDATA; +output stream_out_TVALID; +input stream_out_TREADY; +output [1:0] stream_out_TKEEP; +output [1:0] stream_out_TSTRB; +output [0:0] stream_out_TLAST; + +reg ap_done; +reg ap_idle; +reg ap_ready; +reg fmaps_ce0; +reg[15:0] stream_out_TDATA; +reg stream_out_TVALID; + +reg ap_done_reg; + reg [5:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +reg stream_out_TDATA_blk_n; +wire ap_CS_fsm_pp0_stage3; +reg ap_enable_reg_pp0_iter1; +wire ap_block_pp0_stage3; +reg [0:0] icmp_ln17_reg_400; +reg [0:0] icmp_ln17_reg_400_pp0_iter1_reg; +wire ap_CS_fsm_pp0_stage0; +reg ap_enable_reg_pp0_iter2; +wire ap_block_pp0_stage0; +wire ap_CS_fsm_pp0_stage1; +wire ap_block_pp0_stage1; +reg [0:0] icmp_ln17_reg_400_pp0_iter2_reg; +wire ap_CS_fsm_pp0_stage2; +wire ap_block_pp0_stage2; +reg [15:0] indvar_flatten13_reg_134; +reg [3:0] r_reg_145; +reg [11:0] indvar_flatten_reg_156; +reg [3:0] c_reg_167; +reg [9:0] phi_ln25_reg_178; +wire [15:0] add_ln17_1_fu_189_p2; +reg [15:0] add_ln17_1_reg_395; +reg ap_enable_reg_pp0_iter0; +wire ap_block_state2_pp0_stage0_iter0; +wire ap_block_state6_pp0_stage0_iter1; +reg ap_block_state10_pp0_stage0_iter2; +reg ap_block_state10_io; +reg ap_block_pp0_stage0_11001; +wire [0:0] icmp_ln17_fu_195_p2; +wire [0:0] icmp_ln18_fu_207_p2; +reg [0:0] icmp_ln18_reg_404; +wire [3:0] select_ln17_fu_213_p3; +reg [3:0] select_ln17_reg_411; +wire [3:0] select_ln17_1_fu_221_p3; +reg [3:0] select_ln17_1_reg_417; +wire [11:0] add_ln18_1_fu_229_p2; +reg [11:0] add_ln18_1_reg_424; +wire [9:0] select_ln18_fu_294_p3; +reg [9:0] select_ln18_reg_429; +wire ap_block_state3_pp0_stage1_iter0; +wire ap_block_state7_pp0_stage1_iter1; +reg ap_block_state11_pp0_stage1_iter2; +reg ap_block_state11_io; +reg ap_block_pp0_stage1_11001; +wire [3:0] select_ln18_1_fu_302_p3; +reg [3:0] select_ln18_1_reg_434; +reg [7:0] lshr_ln_reg_444; +wire [11:0] select_ln18_2_fu_333_p3; +reg [11:0] select_ln18_2_reg_449; +wire ap_block_state5_pp0_stage3_iter0; +reg ap_block_state9_pp0_stage3_iter1; +reg ap_block_state9_io; +reg ap_block_pp0_stage3_11001; +wire [9:0] add_ln19_fu_346_p2; +reg [9:0] add_ln19_reg_464; +reg [15:0] tmp_s_reg_469; +reg [15:0] tmp_1_reg_474; +reg [15:0] tmp_2_reg_479; +reg ap_block_state1; +reg ap_block_pp0_stage1_subdone; +reg ap_condition_pp0_exit_iter0_state3; +reg ap_block_pp0_stage3_subdone; +wire ap_block_state4_pp0_stage2_iter0; +wire ap_block_state8_pp0_stage2_iter1; +reg ap_block_state12_pp0_stage2_iter2; +reg ap_block_state12_io; +reg ap_block_pp0_stage2_subdone; +reg [15:0] ap_phi_mux_indvar_flatten13_phi_fu_138_p4; +reg [3:0] ap_phi_mux_r_phi_fu_149_p4; +reg [11:0] ap_phi_mux_indvar_flatten_phi_fu_160_p4; +reg [3:0] ap_phi_mux_c_phi_fu_171_p4; +reg [9:0] ap_phi_mux_phi_ln25_phi_fu_182_p4; +wire [63:0] zext_ln25_4_fu_342_p1; +wire [15:0] trunc_ln25_fu_351_p1; +reg ap_block_pp0_stage3_01001; +reg ap_block_pp0_stage0_01001; +reg ap_block_pp0_stage1_01001; +reg ap_block_pp0_stage2_01001; +reg ap_block_pp0_stage2_11001; +wire [3:0] add_ln17_fu_201_p2; +wire [7:0] tmp_20_fu_235_p3; +wire [4:0] tmp_21_fu_246_p3; +wire [8:0] zext_ln25_fu_242_p1; +wire [8:0] zext_ln25_1_fu_253_p1; +wire [8:0] sub_ln25_fu_257_p2; +wire [0:0] icmp_ln19_fu_272_p2; +wire [0:0] xor_ln17_fu_267_p2; +wire [0:0] and_ln17_fu_278_p2; +wire [0:0] or_ln18_fu_289_p2; +wire [3:0] add_ln18_fu_284_p2; +wire [9:0] sext_ln18_fu_263_p1; +wire [9:0] zext_ln25_2_fu_309_p1; +wire [9:0] add_ln25_fu_313_p2; +wire [15:0] grp_fu_386_p3; +wire [8:0] grp_fu_386_p1; +wire [7:0] grp_fu_386_p2; +reg grp_fu_386_ce; +wire ap_CS_fsm_state13; +reg [5:0] ap_NS_fsm; +reg ap_block_pp0_stage0_subdone; +reg ap_idle_pp0; +wire ap_enable_pp0; +wire [15:0] grp_fu_386_p20; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_done_reg = 1'b0; +#0 ap_CS_fsm = 6'd1; +#0 ap_enable_reg_pp0_iter1 = 1'b0; +#0 ap_enable_reg_pp0_iter2 = 1'b0; +#0 ap_enable_reg_pp0_iter0 = 1'b0; +end + +td_fused_top_mac_muladd_10s_9ns_8ns_16_4_1 #( + .ID( 1 ), + .NUM_STAGE( 4 ), + .din0_WIDTH( 10 ), + .din1_WIDTH( 9 ), + .din2_WIDTH( 8 ), + .dout_WIDTH( 16 )) +mac_muladd_10s_9ns_8ns_16_4_1_U817( + .clk(ap_clk), + .reset(ap_rst), + .ce(grp_fu_386_ce), + .din0(add_ln25_fu_313_p2), + .din1(grp_fu_386_p1), + .din2(grp_fu_386_p2), + .dout(grp_fu_386_p3) +); + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_done_reg <= 1'b0; + end else begin + if ((ap_continue == 1'b1)) begin + ap_done_reg <= 1'b0; + end else if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done_reg <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage1_subdone) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin + ap_enable_reg_pp0_iter0 <= 1'b0; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter0 <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter1 <= 1'b0; + end else begin + if (((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst == 1'b1) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end else begin + if ((((1'b0 == ap_block_pp0_stage2_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((1'b0 == ap_block_pp0_stage3_subdone) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_enable_reg_pp0_iter2 <= 1'b0; + end + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_400 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + c_reg_167 <= select_ln18_1_reg_434; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + c_reg_167 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_400 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten13_reg_134 <= add_ln17_1_reg_395; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten13_reg_134 <= 16'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_400 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + indvar_flatten_reg_156 <= select_ln18_2_reg_449; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + indvar_flatten_reg_156 <= 12'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + phi_ln25_reg_178 <= add_ln19_reg_464; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + phi_ln25_reg_178 <= 10'd0; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_400 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + r_reg_145 <= select_ln17_1_reg_417; + end else if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + r_reg_145 <= 4'd0; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + add_ln17_1_reg_395 <= add_ln17_1_fu_189_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln17_fu_195_p2 == 1'd0))) begin + add_ln18_1_reg_424 <= add_ln18_1_fu_229_p2; + icmp_ln18_reg_404 <= icmp_ln18_fu_207_p2; + select_ln17_reg_411 <= select_ln17_fu_213_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_400 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + add_ln19_reg_464 <= add_ln19_fu_346_p2; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + icmp_ln17_reg_400 <= icmp_ln17_fu_195_p2; + icmp_ln17_reg_400_pp0_iter1_reg <= icmp_ln17_reg_400; + icmp_ln17_reg_400_pp0_iter2_reg <= icmp_ln17_reg_400_pp0_iter1_reg; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_400 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + lshr_ln_reg_444 <= {{select_ln18_fu_294_p3[9:2]}}; + select_ln18_reg_429 <= select_ln18_fu_294_p3; + end +end + +always @ (posedge ap_clk) begin + if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln17_fu_195_p2 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln17_1_reg_417 <= select_ln17_1_fu_221_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_400 == 1'd0) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + select_ln18_1_reg_434 <= select_ln18_1_fu_302_p3; + select_ln18_2_reg_449 <= select_ln18_2_fu_333_p3; + end +end + +always @ (posedge ap_clk) begin + if (((icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + tmp_1_reg_474 <= {{fmaps_q0[47:32]}}; + tmp_2_reg_479 <= {{fmaps_q0[63:48]}}; + tmp_s_reg_469 <= {{fmaps_q0[31:16]}}; + end +end + +always @ (*) begin + if ((icmp_ln17_reg_400 == 1'd1)) begin + ap_condition_pp0_exit_iter0_state3 = 1'b1; + end else begin + ap_condition_pp0_exit_iter0_state3 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_done = 1'b1; + end else begin + ap_done = ap_done_reg; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin + ap_idle_pp0 = 1'b1; + end else begin + ap_idle_pp0 = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln17_reg_400 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_c_phi_fu_171_p4 = select_ln18_1_reg_434; + end else begin + ap_phi_mux_c_phi_fu_171_p4 = c_reg_167; + end +end + +always @ (*) begin + if (((icmp_ln17_reg_400 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_indvar_flatten13_phi_fu_138_p4 = add_ln17_1_reg_395; + end else begin + ap_phi_mux_indvar_flatten13_phi_fu_138_p4 = indvar_flatten13_reg_134; + end +end + +always @ (*) begin + if (((icmp_ln17_reg_400 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_indvar_flatten_phi_fu_160_p4 = select_ln18_2_reg_449; + end else begin + ap_phi_mux_indvar_flatten_phi_fu_160_p4 = indvar_flatten_reg_156; + end +end + +always @ (*) begin + if (((icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + ap_phi_mux_phi_ln25_phi_fu_182_p4 = add_ln19_reg_464; + end else begin + ap_phi_mux_phi_ln25_phi_fu_182_p4 = phi_ln25_reg_178; + end +end + +always @ (*) begin + if (((icmp_ln17_reg_400 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + ap_phi_mux_r_phi_fu_149_p4 = select_ln17_1_reg_417; + end else begin + ap_phi_mux_r_phi_fu_149_p4 = r_reg_145; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state13)) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage2_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((1'b0 == ap_block_pp0_stage3_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((1'b0 == ap_block_pp0_stage1_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin + fmaps_ce0 = 1'b1; + end else begin + fmaps_ce0 = 1'b0; + end +end + +always @ (*) begin + if ((((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin + grp_fu_386_ce = 1'b1; + end else begin + grp_fu_386_ce = 1'b0; + end +end + +always @ (*) begin + if (((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage2_01001) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + stream_out_TDATA = tmp_2_reg_479; + end else if (((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage1_01001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin + stream_out_TDATA = tmp_1_reg_474; + end else if (((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_01001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin + stream_out_TDATA = tmp_s_reg_469; + end else if (((icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3_01001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin + stream_out_TDATA = trunc_ln25_fu_351_p1; + end else begin + stream_out_TDATA = 'bx; + end +end + +always @ (*) begin + if ((((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage2) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + stream_out_TDATA_blk_n = stream_out_TREADY; + end else begin + stream_out_TDATA_blk_n = 1'b1; + end +end + +always @ (*) begin + if ((((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (1'b0 == ap_block_pp0_stage3_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3)))) begin + stream_out_TVALID = 1'b1; + end else begin + stream_out_TVALID = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if ((~((ap_done_reg == 1'b1) | (ap_start == 1'b0)) & (1'b1 == ap_CS_fsm_state1))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_pp0_stage0 : begin + if ((1'b0 == ap_block_pp0_stage0_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end + end + ap_ST_fsm_pp0_stage1 : begin + if ((~((icmp_ln17_reg_400 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage1_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end else if (((icmp_ln17_reg_400 == 1'd1) & (1'b0 == ap_block_pp0_stage1_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage1; + end + end + ap_ST_fsm_pp0_stage2 : begin + if ((~((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2)) & (1'b0 == ap_block_pp0_stage2_subdone))) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end else if (((ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage2_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin + ap_NS_fsm = ap_ST_fsm_state13; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage2; + end + end + ap_ST_fsm_pp0_stage3 : begin + if ((1'b0 == ap_block_pp0_stage3_subdone)) begin + ap_NS_fsm = ap_ST_fsm_pp0_stage0; + end else begin + ap_NS_fsm = ap_ST_fsm_pp0_stage3; + end + end + ap_ST_fsm_state13 : begin + ap_NS_fsm = ap_ST_fsm_state1; + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign add_ln17_1_fu_189_p2 = (ap_phi_mux_indvar_flatten13_phi_fu_138_p4 + 16'd1); + +assign add_ln17_fu_201_p2 = (ap_phi_mux_r_phi_fu_149_p4 + 4'd1); + +assign add_ln18_1_fu_229_p2 = (ap_phi_mux_indvar_flatten_phi_fu_160_p4 + 12'd1); + +assign add_ln18_fu_284_p2 = (select_ln17_reg_411 + 4'd1); + +assign add_ln19_fu_346_p2 = (select_ln18_reg_429 + 10'd4); + +assign add_ln25_fu_313_p2 = ((sext_ln18_fu_263_p1) + (zext_ln25_2_fu_309_p1)); + +assign and_ln17_fu_278_p2 = (xor_ln17_fu_267_p2 & icmp_ln19_fu_272_p2); + +assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4]; + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state13 = ap_CS_fsm[32'd5]; + +assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_pp0_stage0_01001 = ((ap_enable_reg_pp0_iter2 == 1'b1) & (icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_pp0_stage0_11001 = ((ap_enable_reg_pp0_iter2 == 1'b1) & ((1'b1 == ap_block_state10_io) | ((icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +always @ (*) begin + ap_block_pp0_stage0_subdone = ((ap_enable_reg_pp0_iter2 == 1'b1) & ((1'b1 == ap_block_state10_io) | ((icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_pp0_stage1_01001 = ((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_pp0_stage1_11001 = ((ap_enable_reg_pp0_iter2 == 1'b1) & ((1'b1 == ap_block_state11_io) | ((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +always @ (*) begin + ap_block_pp0_stage1_subdone = ((ap_enable_reg_pp0_iter2 == 1'b1) & ((1'b1 == ap_block_state11_io) | ((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_pp0_stage2_01001 = ((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_pp0_stage2_11001 = ((ap_enable_reg_pp0_iter2 == 1'b1) & ((1'b1 == ap_block_state12_io) | ((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +always @ (*) begin + ap_block_pp0_stage2_subdone = ((ap_enable_reg_pp0_iter2 == 1'b1) & ((1'b1 == ap_block_state12_io) | ((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_pp0_stage3_01001 = ((icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_pp0_stage3_11001 = ((ap_enable_reg_pp0_iter1 == 1'b1) & ((1'b1 == ap_block_state9_io) | ((icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +always @ (*) begin + ap_block_pp0_stage3_subdone = ((ap_enable_reg_pp0_iter1 == 1'b1) & ((1'b1 == ap_block_state9_io) | ((icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)))); +end + +always @ (*) begin + ap_block_state1 = ((ap_done_reg == 1'b1) | (ap_start == 1'b0)); +end + +always @ (*) begin + ap_block_state10_io = ((icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_state10_pp0_stage0_iter2 = ((icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_state11_io = ((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_state11_pp0_stage1_iter2 = ((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_state12_io = ((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_state12_pp0_stage2_iter2 = ((icmp_ln17_reg_400_pp0_iter2_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1); + +assign ap_block_state6_pp0_stage0_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state7_pp0_stage1_iter1 = ~(1'b1 == 1'b1); + +assign ap_block_state8_pp0_stage2_iter1 = ~(1'b1 == 1'b1); + +always @ (*) begin + ap_block_state9_io = ((icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +always @ (*) begin + ap_block_state9_pp0_stage3_iter1 = ((icmp_ln17_reg_400_pp0_iter1_reg == 1'd0) & (stream_out_TREADY == 1'b0)); +end + +assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1); + +assign fmaps_address0 = zext_ln25_4_fu_342_p1; + +assign grp_fu_386_p1 = 16'd250; + +assign grp_fu_386_p2 = grp_fu_386_p20; + +assign grp_fu_386_p20 = lshr_ln_reg_444; + +assign icmp_ln17_fu_195_p2 = ((ap_phi_mux_indvar_flatten13_phi_fu_138_p4 == 16'd49000) ? 1'b1 : 1'b0); + +assign icmp_ln18_fu_207_p2 = ((ap_phi_mux_indvar_flatten_phi_fu_160_p4 == 12'd3500) ? 1'b1 : 1'b0); + +assign icmp_ln19_fu_272_p2 = ((ap_phi_mux_phi_ln25_phi_fu_182_p4 == 10'd1000) ? 1'b1 : 1'b0); + +assign or_ln18_fu_289_p2 = (icmp_ln18_reg_404 | and_ln17_fu_278_p2); + +assign select_ln17_1_fu_221_p3 = ((icmp_ln18_fu_207_p2[0:0] == 1'b1) ? add_ln17_fu_201_p2 : ap_phi_mux_r_phi_fu_149_p4); + +assign select_ln17_fu_213_p3 = ((icmp_ln18_fu_207_p2[0:0] == 1'b1) ? 4'd0 : ap_phi_mux_c_phi_fu_171_p4); + +assign select_ln18_1_fu_302_p3 = ((and_ln17_fu_278_p2[0:0] == 1'b1) ? add_ln18_fu_284_p2 : select_ln17_reg_411); + +assign select_ln18_2_fu_333_p3 = ((icmp_ln18_reg_404[0:0] == 1'b1) ? 12'd1 : add_ln18_1_reg_424); + +assign select_ln18_fu_294_p3 = ((or_ln18_fu_289_p2[0:0] == 1'b1) ? 10'd0 : ap_phi_mux_phi_ln25_phi_fu_182_p4); + +assign sext_ln18_fu_263_p1 = (sub_ln25_fu_257_p2); + +assign stream_out_TKEEP = 2'd0; + +assign stream_out_TLAST = 1'd0; + +assign stream_out_TSTRB = 2'd0; + +assign sub_ln25_fu_257_p2 = (zext_ln25_fu_242_p1 - zext_ln25_1_fu_253_p1); + +assign tmp_20_fu_235_p3 = {{select_ln17_1_reg_417}, {4'd0}}; + +assign tmp_21_fu_246_p3 = {{select_ln17_1_reg_417}, {1'd0}}; + +assign trunc_ln25_fu_351_p1 = fmaps_q0[15:0]; + +assign xor_ln17_fu_267_p2 = (icmp_ln18_reg_404 ^ 1'd1); + +assign zext_ln25_1_fu_253_p1 = tmp_21_fu_246_p3; + +assign zext_ln25_2_fu_309_p1 = select_ln18_1_fu_302_p3; + +assign zext_ln25_4_fu_342_p1 = (grp_fu_386_p3); + +assign zext_ln25_fu_242_p1 = tmp_20_fu_235_p3; + +endmodule //td_fused_top_td_fused_axi_out +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_final_fmaps_memcore_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 16; +parameter MEM_SIZE = 49000; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; + reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_final_fmaps_memcore( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd49000; +parameter AddressWidth = 32'd16; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_td_fused_final_fmaps_memcore_ram td_fused_top_td_fused_final_fmaps_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_td_fused_final_fmaps +#(parameter + DataWidth = 64, + AddressRange = 32, + AddressWidth = 16, + BufferCount = 2, + MemLatency = 3, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire [AddressWidth-1:0] i_address0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire [AddressWidth-1:0] t_address0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_td_fused_final_fmaps_memcore td_fused_top_td_fused_final_fmaps_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_td_fused_final_fmaps_memcore td_fused_top_td_fused_final_fmaps_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf10_fmaps_memcore_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 12; +parameter MEM_SIZE = 3136; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; + reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf10_fmaps_memcore( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd3136; +parameter AddressWidth = 32'd12; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_td_fused_tdf10_fmaps_memcore_ram td_fused_top_td_fused_tdf10_fmaps_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_td_fused_tdf10_fmaps +#(parameter + DataWidth = 64, + AddressRange = 32, + AddressWidth = 12, + BufferCount = 2, + MemLatency = 3, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire [AddressWidth-1:0] i_address0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire [AddressWidth-1:0] t_address0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_td_fused_tdf10_fmaps_memcore td_fused_top_td_fused_tdf10_fmaps_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_td_fused_tdf10_fmaps_memcore td_fused_top_td_fused_tdf10_fmaps_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf1_fmaps_memcore_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 16; +parameter MEM_SIZE = 50176; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; + reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf1_fmaps_memcore( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd50176; +parameter AddressWidth = 32'd16; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_td_fused_tdf1_fmaps_memcore_ram td_fused_top_td_fused_tdf1_fmaps_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_td_fused_tdf1_fmaps +#(parameter + DataWidth = 64, + AddressRange = 32, + AddressWidth = 16, + BufferCount = 2, + MemLatency = 3, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire [AddressWidth-1:0] i_address0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire [AddressWidth-1:0] t_address0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_td_fused_tdf1_fmaps_memcore td_fused_top_td_fused_tdf1_fmaps_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_td_fused_tdf1_fmaps_memcore td_fused_top_td_fused_tdf1_fmaps_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf3_fmaps_memcore_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 15; +parameter MEM_SIZE = 25088; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; + reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf3_fmaps_memcore( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd25088; +parameter AddressWidth = 32'd15; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_td_fused_tdf3_fmaps_memcore_ram td_fused_top_td_fused_tdf3_fmaps_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_td_fused_tdf3_fmaps +#(parameter + DataWidth = 64, + AddressRange = 32, + AddressWidth = 15, + BufferCount = 2, + MemLatency = 3, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire [AddressWidth-1:0] i_address0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire [AddressWidth-1:0] t_address0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_td_fused_tdf3_fmaps_memcore td_fused_top_td_fused_tdf3_fmaps_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_td_fused_tdf3_fmaps_memcore td_fused_top_td_fused_tdf3_fmaps_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf4_fmaps_memcore_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 14; +parameter MEM_SIZE = 12544; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; + reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf4_fmaps_memcore( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd12544; +parameter AddressWidth = 32'd14; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_td_fused_tdf4_fmaps_memcore_ram td_fused_top_td_fused_tdf4_fmaps_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_td_fused_tdf4_fmaps +#(parameter + DataWidth = 64, + AddressRange = 32, + AddressWidth = 14, + BufferCount = 2, + MemLatency = 3, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire [AddressWidth-1:0] i_address0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire [AddressWidth-1:0] t_address0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_td_fused_tdf4_fmaps_memcore td_fused_top_td_fused_tdf4_fmaps_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_td_fused_tdf4_fmaps_memcore td_fused_top_td_fused_tdf4_fmaps_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf7_fmaps_memcore_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); + +parameter DWIDTH = 64; +parameter AWIDTH = 13; +parameter MEM_SIZE = 6272; + +input[AWIDTH-1:0] addr0; +input ce0; +output wire[DWIDTH-1:0] q0; +input[AWIDTH-1:0] addr1; +input ce1; +input[DWIDTH-1:0] d1; +input we1; +input clk; + + reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; +wire [AWIDTH-1:0] addr0_t0; +reg [AWIDTH-1:0] addr0_t1; +reg [DWIDTH-1:0] q0_t0; + reg [DWIDTH-1:0] q0_t1; +wire [AWIDTH-1:0] addr1_t0; +reg [AWIDTH-1:0] addr1_t1; +wire [DWIDTH-1:0] d1_t0; +wire we1_t0; +reg [DWIDTH-1:0] d1_t1; +reg we1_t1; + + +assign addr0_t0 = addr0; +assign q0 = q0_t1; +assign addr1_t0 = addr1; +assign d1_t0 = d1; +assign we1_t0 = we1; + +always @(posedge clk) +begin + if (ce0) + begin + addr0_t1 <= addr0_t0; + q0_t1 <= q0_t0; + end + if (ce1) + begin + addr1_t1 <= addr1_t0; + d1_t1 <= d1_t0; + we1_t1 <= we1_t0; + end +end + + +always @(posedge clk) +begin + if (ce0) begin + q0_t0 <= ram[addr0_t1]; + end +end + + +always @(posedge clk) +begin + if (ce1) begin + if (we1_t1) + ram[addr1_t1] <= d1_t1; + end +end + + +endmodule + +`timescale 1 ns / 1 ps +module td_fused_top_td_fused_tdf7_fmaps_memcore( + reset, + clk, + address0, + ce0, + q0, + address1, + ce1, + we1, + d1); + +parameter DataWidth = 32'd64; +parameter AddressRange = 32'd6272; +parameter AddressWidth = 32'd13; +input reset; +input clk; +input[AddressWidth - 1:0] address0; +input ce0; +output[DataWidth - 1:0] q0; +input[AddressWidth - 1:0] address1; +input ce1; +input we1; +input[DataWidth - 1:0] d1; + + + +td_fused_top_td_fused_tdf7_fmaps_memcore_ram td_fused_top_td_fused_tdf7_fmaps_memcore_ram_U( + .clk( clk ), + .addr0( address0 ), + .ce0( ce0 ), + .q0( q0 ), + .addr1( address1 ), + .ce1( ce1 ), + .we1( we1 ), + .d1( d1 ) +); + +endmodule + +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// ============================================================== + +`timescale 1ns/1ps + +module td_fused_top_td_fused_tdf7_fmaps +#(parameter + DataWidth = 64, + AddressRange = 32, + AddressWidth = 13, + BufferCount = 2, + MemLatency = 3, + IndexWidth = 1 +) ( + // system signals + input wire clk, + input wire reset, + // initiator + input wire i_ce, + input wire i_write, + output wire i_full_n, + input wire i_ce0, + input wire [AddressWidth-1:0] i_address0, + output wire [DataWidth-1:0] i_q0, + input wire i_ce1, + input wire i_we1, + input wire [AddressWidth-1:0] i_address1, + input wire [DataWidth-1:0] i_d1, + // target + input wire t_ce, + input wire t_read, + output wire t_empty_n, + input wire t_ce0, + input wire [AddressWidth-1:0] t_address0, + output wire [DataWidth-1:0] t_q0, + input wire t_ce1, + input wire t_we1, + input wire [AddressWidth-1:0] t_address1, + input wire [DataWidth-1:0] t_d1 +); +//------------------------Local signal------------------- +// control/status +reg [IndexWidth-1:0] iptr = 1'b0; // initiator index +reg [IndexWidth-1:0] tptr = 1'b0; // target index +reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index +reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index +reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled +reg reg_valid0 = 1'b0; // buffer has valid data +reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled +reg reg_valid1 = 1'b0; // buffer has valid data +reg [IndexWidth:0] count = 1'b0; // count of written buffers +reg full_n = 1'b1; // whether all buffers are written +reg empty_n = 1'b0; // whether none of the buffers is written +wire push_buf; // finish writing a buffer +wire write_buf; // write a buffer +wire pop_buf; // finish reading a buffer +// buffer signals +wire [BufferCount-1:0] buf_ce0; +wire [AddressWidth-1:0] buf_a0_0, buf_a0_1; +wire [DataWidth-1:0] buf_q0_0, buf_q0_1; +wire [BufferCount-1:0] buf_ce1; +wire [BufferCount-1:0] buf_we1; +wire [AddressWidth-1:0] buf_a1_0, buf_a1_1; +wire [DataWidth-1:0] buf_d1_0, buf_d1_1; +//------------------------Instantiation------------------ +//genvar i; + td_fused_top_td_fused_tdf7_fmaps_memcore td_fused_top_td_fused_tdf7_fmaps_memcore_U_0 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_0 ), + .ce0 ( buf_ce0[ 0 ] ), + .q0 ( buf_q0_0 ), + .address1 ( buf_a1_0 ), + .ce1 ( buf_ce1[ 0 ] ), + .we1 ( buf_we1[ 0 ] ), + .d1 ( buf_d1_0 ) + ); + td_fused_top_td_fused_tdf7_fmaps_memcore td_fused_top_td_fused_tdf7_fmaps_memcore_U_1 ( + .reset ( reset ), + .clk ( clk ), + .address0 ( buf_a0_1 ), + .ce0 ( buf_ce0[ 1 ] ), + .q0 ( buf_q0_1 ), + .address1 ( buf_a1_1 ), + .ce1 ( buf_ce1[ 1 ] ), + .we1 ( buf_we1[ 1 ] ), + .d1 ( buf_d1_1 ) + ); + +//++++++++++++++++++++++++buffer signals+++++++++++++++++ + assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0 + : (iptr == 0 ) ? i_ce0 : 1'b0; + assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1 + : (iptr == 0 ) ? i_ce1 : 1'b0; + assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1 + : (iptr == 0 ) ? i_we1 : 1'b0; + assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1; + assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0 + : (iptr == 1 ) ? i_ce0 : 1'b0; + assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0; + assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1 + : (iptr == 1 ) ? i_ce1 : 1'b0; + assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1; + assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1 + : (iptr == 1 ) ? i_we1 : 1'b0; + assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//------------------------Body--------------------------- +assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0); +assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + +//++++++++++++++++++++++++output+++++++++++++++++++++++++ +assign i_full_n = full_n; +assign t_empty_n = empty_n; +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +//++++++++++++++++++++++++control/status+++++++++++++++++ +assign push_buf = i_ce & i_write & full_n; +assign write_buf = i_ce & i_write; +assign pop_buf = t_ce & t_read & empty_n; + +// iptr +always @(posedge clk) begin + if (reset == 1'b1) + iptr <= 1'b0; + else if (push_buf) begin + if (iptr == BufferCount - 1'b1) + iptr <= 1'b0; + else + iptr <= iptr + 1'b1; + end +end + +// tptr +always @(posedge clk) begin + if (reset == 1'b1) + tptr <= 1'b0; + else if (pop_buf) begin + if (tptr == BufferCount - 1'b1) + tptr <= 1'b0; + else + tptr <= tptr + 1'b1; + end +end + +// prev_iptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_iptr <= 1'b0; + else begin + prev_iptr <= iptr; + end +end + +// prev_tptr +always @(posedge clk) begin + if (reset == 1'b1) + prev_tptr <= 1'b0; + else begin + prev_tptr <= tptr; + end +end + +// reg_q0 and reg_valid0 +always @(posedge clk) begin + if (reset == 1'b1) begin + reg_q0 <= 1'b0; + reg_valid0 <= 1'b0; + end else if (!t_ce0 && !reg_valid0) begin + reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0); + reg_valid0 <= 1'b1; + end else if (t_ce0) begin + reg_valid0 <= 1'b0; + end +end + +// count +always @(posedge clk) begin + if (reset == 1'b1) + count <= 1'b0; + else if (push_buf && !pop_buf) + count <= count + 1'b1; + else if (!push_buf && pop_buf) + count <= count - 1'b1; +end + +// full_n +always @(posedge clk) begin + if (reset == 1'b1) + full_n <= 1'b1; + else if (push_buf && !pop_buf && count == BufferCount - 2'd2) + full_n <= 1'b0; + else if (!push_buf && pop_buf) + full_n <= 1'b1; +end + +// empty_n +always @(posedge clk) begin + if (reset == 1'b1) + empty_n <= 1'b0; + else if ((!write_buf && pop_buf && count == 1'b1) + || (pop_buf && count == 1'b0)) + empty_n <= 1'b0; + else if (write_buf && !pop_buf) + empty_n <= 1'b1; +end +//+++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +endmodule + +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + +module td_fused_top_td_fused ( + ap_clk, + ap_rst, + tdf1_filters_address0, + tdf1_filters_ce0, + tdf1_filters_d0, + tdf1_filters_q0, + tdf1_filters_we0, + tdf1_filters_address1, + tdf1_filters_ce1, + tdf1_filters_d1, + tdf1_filters_q1, + tdf1_filters_we1, + tdf2_filters_address0, + tdf2_filters_ce0, + tdf2_filters_d0, + tdf2_filters_q0, + tdf2_filters_we0, + tdf2_filters_address1, + tdf2_filters_ce1, + tdf2_filters_d1, + tdf2_filters_q1, + tdf2_filters_we1, + tdf3_filters_address0, + tdf3_filters_ce0, + tdf3_filters_d0, + tdf3_filters_q0, + tdf3_filters_we0, + tdf3_filters_address1, + tdf3_filters_ce1, + tdf3_filters_d1, + tdf3_filters_q1, + tdf3_filters_we1, + tdf4_filters_address0, + tdf4_filters_ce0, + tdf4_filters_d0, + tdf4_filters_q0, + tdf4_filters_we0, + tdf4_filters_address1, + tdf4_filters_ce1, + tdf4_filters_d1, + tdf4_filters_q1, + tdf4_filters_we1, + tdf4_l2_filters_address0, + tdf4_l2_filters_ce0, + tdf4_l2_filters_d0, + tdf4_l2_filters_q0, + tdf4_l2_filters_we0, + tdf4_l2_filters_address1, + tdf4_l2_filters_ce1, + tdf4_l2_filters_d1, + tdf4_l2_filters_q1, + tdf4_l2_filters_we1, + tdf5_filters_address0, + tdf5_filters_ce0, + tdf5_filters_d0, + tdf5_filters_q0, + tdf5_filters_we0, + tdf5_filters_address1, + tdf5_filters_ce1, + tdf5_filters_d1, + tdf5_filters_q1, + tdf5_filters_we1, + tdf6_filters_address0, + tdf6_filters_ce0, + tdf6_filters_d0, + tdf6_filters_q0, + tdf6_filters_we0, + tdf6_filters_address1, + tdf6_filters_ce1, + tdf6_filters_d1, + tdf6_filters_q1, + tdf6_filters_we1, + tdf7_filters_address0, + tdf7_filters_ce0, + tdf7_filters_d0, + tdf7_filters_q0, + tdf7_filters_we0, + tdf7_filters_address1, + tdf7_filters_ce1, + tdf7_filters_d1, + tdf7_filters_q1, + tdf7_filters_we1, + tdf7_l2_filters_address0, + tdf7_l2_filters_ce0, + tdf7_l2_filters_d0, + tdf7_l2_filters_q0, + tdf7_l2_filters_we0, + tdf7_l2_filters_address1, + tdf7_l2_filters_ce1, + tdf7_l2_filters_d1, + tdf7_l2_filters_q1, + tdf7_l2_filters_we1, + tdf8_filters_address0, + tdf8_filters_ce0, + tdf8_filters_d0, + tdf8_filters_q0, + tdf8_filters_we0, + tdf8_filters_address1, + tdf8_filters_ce1, + tdf8_filters_d1, + tdf8_filters_q1, + tdf8_filters_we1, + tdf9_filters_address0, + tdf9_filters_ce0, + tdf9_filters_d0, + tdf9_filters_q0, + tdf9_filters_we0, + tdf9_filters_address1, + tdf9_filters_ce1, + tdf9_filters_d1, + tdf9_filters_q1, + tdf9_filters_we1, + tdf10_filters_address0, + tdf10_filters_ce0, + tdf10_filters_d0, + tdf10_filters_q0, + tdf10_filters_we0, + tdf10_filters_address1, + tdf10_filters_ce1, + tdf10_filters_d1, + tdf10_filters_q1, + tdf10_filters_we1, + tdf10_l2_filters_address0, + tdf10_l2_filters_ce0, + tdf10_l2_filters_d0, + tdf10_l2_filters_q0, + tdf10_l2_filters_we0, + tdf10_l2_filters_address1, + tdf10_l2_filters_ce1, + tdf10_l2_filters_d1, + tdf10_l2_filters_q1, + tdf10_l2_filters_we1, + tdf11_filters_address0, + tdf11_filters_ce0, + tdf11_filters_d0, + tdf11_filters_q0, + tdf11_filters_we0, + tdf11_filters_address1, + tdf11_filters_ce1, + tdf11_filters_d1, + tdf11_filters_q1, + tdf11_filters_we1, + tdf11_l2_filters_address0, + tdf11_l2_filters_ce0, + tdf11_l2_filters_d0, + tdf11_l2_filters_q0, + tdf11_l2_filters_we0, + tdf11_l2_filters_address1, + tdf11_l2_filters_ce1, + tdf11_l2_filters_d1, + tdf11_l2_filters_q1, + tdf11_l2_filters_we1, + tdf12_filters_address0, + tdf12_filters_ce0, + tdf12_filters_d0, + tdf12_filters_q0, + tdf12_filters_we0, + tdf12_filters_address1, + tdf12_filters_ce1, + tdf12_filters_d1, + tdf12_filters_q1, + tdf12_filters_we1, + tdf1_adjustments_address0, + tdf1_adjustments_ce0, + tdf1_adjustments_d0, + tdf1_adjustments_q0, + tdf1_adjustments_we0, + tdf1_adjustments_address1, + tdf1_adjustments_ce1, + tdf1_adjustments_d1, + tdf1_adjustments_q1, + tdf1_adjustments_we1, + tdf2_adjustments_address0, + tdf2_adjustments_ce0, + tdf2_adjustments_d0, + tdf2_adjustments_q0, + tdf2_adjustments_we0, + tdf2_adjustments_address1, + tdf2_adjustments_ce1, + tdf2_adjustments_d1, + tdf2_adjustments_q1, + tdf2_adjustments_we1, + tdf3_adjustments_address0, + tdf3_adjustments_ce0, + tdf3_adjustments_d0, + tdf3_adjustments_q0, + tdf3_adjustments_we0, + tdf3_adjustments_address1, + tdf3_adjustments_ce1, + tdf3_adjustments_d1, + tdf3_adjustments_q1, + tdf3_adjustments_we1, + tdf4_adjustments_address0, + tdf4_adjustments_ce0, + tdf4_adjustments_d0, + tdf4_adjustments_q0, + tdf4_adjustments_we0, + tdf4_adjustments_address1, + tdf4_adjustments_ce1, + tdf4_adjustments_d1, + tdf4_adjustments_q1, + tdf4_adjustments_we1, + tdf4_l2_adjustments_address0, + tdf4_l2_adjustments_ce0, + tdf4_l2_adjustments_d0, + tdf4_l2_adjustments_q0, + tdf4_l2_adjustments_we0, + tdf4_l2_adjustments_address1, + tdf4_l2_adjustments_ce1, + tdf4_l2_adjustments_d1, + tdf4_l2_adjustments_q1, + tdf4_l2_adjustments_we1, + tdf5_adjustments_address0, + tdf5_adjustments_ce0, + tdf5_adjustments_d0, + tdf5_adjustments_q0, + tdf5_adjustments_we0, + tdf5_adjustments_address1, + tdf5_adjustments_ce1, + tdf5_adjustments_d1, + tdf5_adjustments_q1, + tdf5_adjustments_we1, + tdf6_adjustments_address0, + tdf6_adjustments_ce0, + tdf6_adjustments_d0, + tdf6_adjustments_q0, + tdf6_adjustments_we0, + tdf6_adjustments_address1, + tdf6_adjustments_ce1, + tdf6_adjustments_d1, + tdf6_adjustments_q1, + tdf6_adjustments_we1, + tdf7_adjustments_address0, + tdf7_adjustments_ce0, + tdf7_adjustments_d0, + tdf7_adjustments_q0, + tdf7_adjustments_we0, + tdf7_adjustments_address1, + tdf7_adjustments_ce1, + tdf7_adjustments_d1, + tdf7_adjustments_q1, + tdf7_adjustments_we1, + tdf7_l2_adjustments_address0, + tdf7_l2_adjustments_ce0, + tdf7_l2_adjustments_d0, + tdf7_l2_adjustments_q0, + tdf7_l2_adjustments_we0, + tdf7_l2_adjustments_address1, + tdf7_l2_adjustments_ce1, + tdf7_l2_adjustments_d1, + tdf7_l2_adjustments_q1, + tdf7_l2_adjustments_we1, + tdf8_adjustments_address0, + tdf8_adjustments_ce0, + tdf8_adjustments_d0, + tdf8_adjustments_q0, + tdf8_adjustments_we0, + tdf8_adjustments_address1, + tdf8_adjustments_ce1, + tdf8_adjustments_d1, + tdf8_adjustments_q1, + tdf8_adjustments_we1, + tdf9_adjustments_address0, + tdf9_adjustments_ce0, + tdf9_adjustments_d0, + tdf9_adjustments_q0, + tdf9_adjustments_we0, + tdf9_adjustments_address1, + tdf9_adjustments_ce1, + tdf9_adjustments_d1, + tdf9_adjustments_q1, + tdf9_adjustments_we1, + tdf10_adjustments_address0, + tdf10_adjustments_ce0, + tdf10_adjustments_d0, + tdf10_adjustments_q0, + tdf10_adjustments_we0, + tdf10_adjustments_address1, + tdf10_adjustments_ce1, + tdf10_adjustments_d1, + tdf10_adjustments_q1, + tdf10_adjustments_we1, + tdf10_l2_adjustments_address0, + tdf10_l2_adjustments_ce0, + tdf10_l2_adjustments_d0, + tdf10_l2_adjustments_q0, + tdf10_l2_adjustments_we0, + tdf10_l2_adjustments_address1, + tdf10_l2_adjustments_ce1, + tdf10_l2_adjustments_d1, + tdf10_l2_adjustments_q1, + tdf10_l2_adjustments_we1, + tdf11_adjustments_address0, + tdf11_adjustments_ce0, + tdf11_adjustments_d0, + tdf11_adjustments_q0, + tdf11_adjustments_we0, + tdf11_adjustments_address1, + tdf11_adjustments_ce1, + tdf11_adjustments_d1, + tdf11_adjustments_q1, + tdf11_adjustments_we1, + tdf11_l2_adjustments_address0, + tdf11_l2_adjustments_ce0, + tdf11_l2_adjustments_d0, + tdf11_l2_adjustments_q0, + tdf11_l2_adjustments_we0, + tdf11_l2_adjustments_address1, + tdf11_l2_adjustments_ce1, + tdf11_l2_adjustments_d1, + tdf11_l2_adjustments_q1, + tdf11_l2_adjustments_we1, + tdf12_adjustments_address0, + tdf12_adjustments_ce0, + tdf12_adjustments_d0, + tdf12_adjustments_q0, + tdf12_adjustments_we0, + tdf12_adjustments_address1, + tdf12_adjustments_ce1, + tdf12_adjustments_d1, + tdf12_adjustments_q1, + tdf12_adjustments_we1, + stream_in_TDATA, + stream_in_TKEEP, + stream_in_TSTRB, + stream_in_TLAST, + stream_out_TDATA, + stream_out_TKEEP, + stream_out_TSTRB, + stream_out_TLAST, + stream_in_TVALID, + stream_in_TREADY, + ap_start, + stream_out_TVALID, + stream_out_TREADY, + ap_done, + ap_ready, + ap_idle, + ap_continue +); + + +input ap_clk; +input ap_rst; +output [8:0] tdf1_filters_address0; +output tdf1_filters_ce0; +output [15:0] tdf1_filters_d0; +input [15:0] tdf1_filters_q0; +output tdf1_filters_we0; +output [8:0] tdf1_filters_address1; +output tdf1_filters_ce1; +output [15:0] tdf1_filters_d1; +input [15:0] tdf1_filters_q1; +output tdf1_filters_we1; +output [12:0] tdf2_filters_address0; +output tdf2_filters_ce0; +output [15:0] tdf2_filters_d0; +input [15:0] tdf2_filters_q0; +output tdf2_filters_we0; +output [12:0] tdf2_filters_address1; +output tdf2_filters_ce1; +output [15:0] tdf2_filters_d1; +input [15:0] tdf2_filters_q1; +output tdf2_filters_we1; +output [8:0] tdf3_filters_address0; +output tdf3_filters_ce0; +output [15:0] tdf3_filters_d0; +input [15:0] tdf3_filters_q0; +output tdf3_filters_we0; +output [8:0] tdf3_filters_address1; +output tdf3_filters_ce1; +output [15:0] tdf3_filters_d1; +input [15:0] tdf3_filters_q1; +output tdf3_filters_we1; +output [14:0] tdf4_filters_address0; +output tdf4_filters_ce0; +output [15:0] tdf4_filters_d0; +input [15:0] tdf4_filters_q0; +output tdf4_filters_we0; +output [14:0] tdf4_filters_address1; +output tdf4_filters_ce1; +output [15:0] tdf4_filters_d1; +input [15:0] tdf4_filters_q1; +output tdf4_filters_we1; +output [10:0] tdf4_l2_filters_address0; +output tdf4_l2_filters_ce0; +output [15:0] tdf4_l2_filters_d0; +input [15:0] tdf4_l2_filters_q0; +output tdf4_l2_filters_we0; +output [10:0] tdf4_l2_filters_address1; +output tdf4_l2_filters_ce1; +output [15:0] tdf4_l2_filters_d1; +input [15:0] tdf4_l2_filters_q1; +output tdf4_l2_filters_we1; +output [14:0] tdf5_filters_address0; +output tdf5_filters_ce0; +output [15:0] tdf5_filters_d0; +input [15:0] tdf5_filters_q0; +output tdf5_filters_we0; +output [14:0] tdf5_filters_address1; +output tdf5_filters_ce1; +output [15:0] tdf5_filters_d1; +input [15:0] tdf5_filters_q1; +output tdf5_filters_we1; +output [11:0] tdf6_filters_address0; +output tdf6_filters_ce0; +output [15:0] tdf6_filters_d0; +input [15:0] tdf6_filters_q0; +output tdf6_filters_we0; +output [11:0] tdf6_filters_address1; +output tdf6_filters_ce1; +output [15:0] tdf6_filters_d1; +input [15:0] tdf6_filters_q1; +output tdf6_filters_we1; +output [16:0] tdf7_filters_address0; +output tdf7_filters_ce0; +output [15:0] tdf7_filters_d0; +input [15:0] tdf7_filters_q0; +output tdf7_filters_we0; +output [16:0] tdf7_filters_address1; +output tdf7_filters_ce1; +output [15:0] tdf7_filters_d1; +input [15:0] tdf7_filters_q1; +output tdf7_filters_we1; +output [12:0] tdf7_l2_filters_address0; +output tdf7_l2_filters_ce0; +output [15:0] tdf7_l2_filters_d0; +input [15:0] tdf7_l2_filters_q0; +output tdf7_l2_filters_we0; +output [12:0] tdf7_l2_filters_address1; +output tdf7_l2_filters_ce1; +output [15:0] tdf7_l2_filters_d1; +input [15:0] tdf7_l2_filters_q1; +output tdf7_l2_filters_we1; +output [16:0] tdf8_filters_address0; +output tdf8_filters_ce0; +output [15:0] tdf8_filters_d0; +input [15:0] tdf8_filters_q0; +output tdf8_filters_we0; +output [16:0] tdf8_filters_address1; +output tdf8_filters_ce1; +output [15:0] tdf8_filters_d1; +input [15:0] tdf8_filters_q1; +output tdf8_filters_we1; +output [13:0] tdf9_filters_address0; +output tdf9_filters_ce0; +output [15:0] tdf9_filters_d0; +input [15:0] tdf9_filters_q0; +output tdf9_filters_we0; +output [13:0] tdf9_filters_address1; +output tdf9_filters_ce1; +output [15:0] tdf9_filters_d1; +input [15:0] tdf9_filters_q1; +output tdf9_filters_we1; +output [16:0] tdf10_filters_address0; +output tdf10_filters_ce0; +output [63:0] tdf10_filters_d0; +input [63:0] tdf10_filters_q0; +output tdf10_filters_we0; +output [16:0] tdf10_filters_address1; +output tdf10_filters_ce1; +output [63:0] tdf10_filters_d1; +input [63:0] tdf10_filters_q1; +output tdf10_filters_we1; +output [14:0] tdf10_l2_filters_address0; +output tdf10_l2_filters_ce0; +output [15:0] tdf10_l2_filters_d0; +input [15:0] tdf10_l2_filters_q0; +output tdf10_l2_filters_we0; +output [14:0] tdf10_l2_filters_address1; +output tdf10_l2_filters_ce1; +output [15:0] tdf10_l2_filters_d1; +input [15:0] tdf10_l2_filters_q1; +output tdf10_l2_filters_we1; +output [16:0] tdf11_filters_address0; +output tdf11_filters_ce0; +output [63:0] tdf11_filters_d0; +input [63:0] tdf11_filters_q0; +output tdf11_filters_we0; +output [16:0] tdf11_filters_address1; +output tdf11_filters_ce1; +output [63:0] tdf11_filters_d1; +input [63:0] tdf11_filters_q1; +output tdf11_filters_we1; +output [15:0] tdf11_l2_filters_address0; +output tdf11_l2_filters_ce0; +output [15:0] tdf11_l2_filters_d0; +input [15:0] tdf11_l2_filters_q0; +output tdf11_l2_filters_we0; +output [15:0] tdf11_l2_filters_address1; +output tdf11_l2_filters_ce1; +output [15:0] tdf11_l2_filters_d1; +input [15:0] tdf11_l2_filters_q1; +output tdf11_l2_filters_we1; +output [16:0] tdf12_filters_address0; +output tdf12_filters_ce0; +output [15:0] tdf12_filters_d0; +input [15:0] tdf12_filters_q0; +output tdf12_filters_we0; +output [16:0] tdf12_filters_address1; +output tdf12_filters_ce1; +output [15:0] tdf12_filters_d1; +input [15:0] tdf12_filters_q1; +output tdf12_filters_we1; +output [3:0] tdf1_adjustments_address0; +output tdf1_adjustments_ce0; +output [47:0] tdf1_adjustments_d0; +input [47:0] tdf1_adjustments_q0; +output tdf1_adjustments_we0; +output [3:0] tdf1_adjustments_address1; +output tdf1_adjustments_ce1; +output [47:0] tdf1_adjustments_d1; +input [47:0] tdf1_adjustments_q1; +output tdf1_adjustments_we1; +output [4:0] tdf2_adjustments_address0; +output tdf2_adjustments_ce0; +output [47:0] tdf2_adjustments_d0; +input [47:0] tdf2_adjustments_q0; +output tdf2_adjustments_we0; +output [4:0] tdf2_adjustments_address1; +output tdf2_adjustments_ce1; +output [47:0] tdf2_adjustments_d1; +input [47:0] tdf2_adjustments_q1; +output tdf2_adjustments_we1; +output [3:0] tdf3_adjustments_address0; +output tdf3_adjustments_ce0; +output [47:0] tdf3_adjustments_d0; +input [47:0] tdf3_adjustments_q0; +output tdf3_adjustments_we0; +output [3:0] tdf3_adjustments_address1; +output tdf3_adjustments_ce1; +output [47:0] tdf3_adjustments_d1; +input [47:0] tdf3_adjustments_q1; +output tdf3_adjustments_we1; +output [6:0] tdf4_adjustments_address0; +output tdf4_adjustments_ce0; +output [47:0] tdf4_adjustments_d0; +input [47:0] tdf4_adjustments_q0; +output tdf4_adjustments_we0; +output [6:0] tdf4_adjustments_address1; +output tdf4_adjustments_ce1; +output [47:0] tdf4_adjustments_d1; +input [47:0] tdf4_adjustments_q1; +output tdf4_adjustments_we1; +output [3:0] tdf4_l2_adjustments_address0; +output tdf4_l2_adjustments_ce0; +output [47:0] tdf4_l2_adjustments_d0; +input [47:0] tdf4_l2_adjustments_q0; +output tdf4_l2_adjustments_we0; +output [3:0] tdf4_l2_adjustments_address1; +output tdf4_l2_adjustments_ce1; +output [47:0] tdf4_l2_adjustments_d1; +input [47:0] tdf4_l2_adjustments_q1; +output tdf4_l2_adjustments_we1; +output [6:0] tdf5_adjustments_address0; +output tdf5_adjustments_ce0; +output [47:0] tdf5_adjustments_d0; +input [47:0] tdf5_adjustments_q0; +output tdf5_adjustments_we0; +output [6:0] tdf5_adjustments_address1; +output tdf5_adjustments_ce1; +output [47:0] tdf5_adjustments_d1; +input [47:0] tdf5_adjustments_q1; +output tdf5_adjustments_we1; +output [4:0] tdf6_adjustments_address0; +output tdf6_adjustments_ce0; +output [47:0] tdf6_adjustments_d0; +input [47:0] tdf6_adjustments_q0; +output tdf6_adjustments_we0; +output [4:0] tdf6_adjustments_address1; +output tdf6_adjustments_ce1; +output [47:0] tdf6_adjustments_d1; +input [47:0] tdf6_adjustments_q1; +output tdf6_adjustments_we1; +output [7:0] tdf7_adjustments_address0; +output tdf7_adjustments_ce0; +output [47:0] tdf7_adjustments_d0; +input [47:0] tdf7_adjustments_q0; +output tdf7_adjustments_we0; +output [7:0] tdf7_adjustments_address1; +output tdf7_adjustments_ce1; +output [47:0] tdf7_adjustments_d1; +input [47:0] tdf7_adjustments_q1; +output tdf7_adjustments_we1; +output [4:0] tdf7_l2_adjustments_address0; +output tdf7_l2_adjustments_ce0; +output [47:0] tdf7_l2_adjustments_d0; +input [47:0] tdf7_l2_adjustments_q0; +output tdf7_l2_adjustments_we0; +output [4:0] tdf7_l2_adjustments_address1; +output tdf7_l2_adjustments_ce1; +output [47:0] tdf7_l2_adjustments_d1; +input [47:0] tdf7_l2_adjustments_q1; +output tdf7_l2_adjustments_we1; +output [7:0] tdf8_adjustments_address0; +output tdf8_adjustments_ce0; +output [47:0] tdf8_adjustments_d0; +input [47:0] tdf8_adjustments_q0; +output tdf8_adjustments_we0; +output [7:0] tdf8_adjustments_address1; +output tdf8_adjustments_ce1; +output [47:0] tdf8_adjustments_d1; +input [47:0] tdf8_adjustments_q1; +output tdf8_adjustments_we1; +output [5:0] tdf9_adjustments_address0; +output tdf9_adjustments_ce0; +output [47:0] tdf9_adjustments_d0; +input [47:0] tdf9_adjustments_q0; +output tdf9_adjustments_we0; +output [5:0] tdf9_adjustments_address1; +output tdf9_adjustments_ce1; +output [47:0] tdf9_adjustments_d1; +input [47:0] tdf9_adjustments_q1; +output tdf9_adjustments_we1; +output [8:0] tdf10_adjustments_address0; +output tdf10_adjustments_ce0; +output [47:0] tdf10_adjustments_d0; +input [47:0] tdf10_adjustments_q0; +output tdf10_adjustments_we0; +output [8:0] tdf10_adjustments_address1; +output tdf10_adjustments_ce1; +output [47:0] tdf10_adjustments_d1; +input [47:0] tdf10_adjustments_q1; +output tdf10_adjustments_we1; +output [5:0] tdf10_l2_adjustments_address0; +output tdf10_l2_adjustments_ce0; +output [47:0] tdf10_l2_adjustments_d0; +input [47:0] tdf10_l2_adjustments_q0; +output tdf10_l2_adjustments_we0; +output [5:0] tdf10_l2_adjustments_address1; +output tdf10_l2_adjustments_ce1; +output [47:0] tdf10_l2_adjustments_d1; +input [47:0] tdf10_l2_adjustments_q1; +output tdf10_l2_adjustments_we1; +output [8:0] tdf11_adjustments_address0; +output tdf11_adjustments_ce0; +output [47:0] tdf11_adjustments_d0; +input [47:0] tdf11_adjustments_q0; +output tdf11_adjustments_we0; +output [8:0] tdf11_adjustments_address1; +output tdf11_adjustments_ce1; +output [47:0] tdf11_adjustments_d1; +input [47:0] tdf11_adjustments_q1; +output tdf11_adjustments_we1; +output [6:0] tdf11_l2_adjustments_address0; +output tdf11_l2_adjustments_ce0; +output [47:0] tdf11_l2_adjustments_d0; +input [47:0] tdf11_l2_adjustments_q0; +output tdf11_l2_adjustments_we0; +output [6:0] tdf11_l2_adjustments_address1; +output tdf11_l2_adjustments_ce1; +output [47:0] tdf11_l2_adjustments_d1; +input [47:0] tdf11_l2_adjustments_q1; +output tdf11_l2_adjustments_we1; +output [9:0] tdf12_adjustments_address0; +output tdf12_adjustments_ce0; +output [47:0] tdf12_adjustments_d0; +input [47:0] tdf12_adjustments_q0; +output tdf12_adjustments_we0; +output [9:0] tdf12_adjustments_address1; +output tdf12_adjustments_ce1; +output [47:0] tdf12_adjustments_d1; +input [47:0] tdf12_adjustments_q1; +output tdf12_adjustments_we1; +input [15:0] stream_in_TDATA; +input [1:0] stream_in_TKEEP; +input [1:0] stream_in_TSTRB; +input [0:0] stream_in_TLAST; +output [15:0] stream_out_TDATA; +output [1:0] stream_out_TKEEP; +output [1:0] stream_out_TSTRB; +output [0:0] stream_out_TLAST; +input stream_in_TVALID; +output stream_in_TREADY; +input ap_start; +output stream_out_TVALID; +input stream_out_TREADY; +output ap_done; +output ap_ready; +output ap_idle; +input ap_continue; + +wire [63:0] tdf1_fmaps_i_q0; +wire [63:0] tdf1_fmaps_t_q0; +wire [63:0] tdf2_fmaps_i_q0; +wire [63:0] tdf2_fmaps_t_q0; +wire [63:0] tdf3_fmaps_i_q0; +wire [63:0] tdf3_fmaps_t_q0; +wire [63:0] tdf4_fmaps_i_q0; +wire [63:0] tdf4_fmaps_t_q0; +wire [63:0] tdf5_fmaps_i_q0; +wire [63:0] tdf5_fmaps_t_q0; +wire [63:0] tdf6_fmaps_i_q0; +wire [63:0] tdf6_fmaps_t_q0; +wire [63:0] tdf7_fmaps_i_q0; +wire [63:0] tdf7_fmaps_t_q0; +wire [63:0] tdf8_fmaps_i_q0; +wire [63:0] tdf8_fmaps_t_q0; +wire [63:0] tdf9_fmaps_i_q0; +wire [63:0] tdf9_fmaps_t_q0; +wire [63:0] tdf10_fmaps_i_q0; +wire [63:0] tdf10_fmaps_t_q0; +wire [63:0] tdf11_fmaps_i_q0; +wire [63:0] tdf11_fmaps_t_q0; +wire [63:0] tdf12_fmaps_i_q0; +wire [63:0] tdf12_fmaps_t_q0; +wire [63:0] final_fmaps_i_q0; +wire [63:0] final_fmaps_t_q0; +wire td_fused_axi_in_U0_ap_start; +wire td_fused_axi_in_U0_ap_done; +wire td_fused_axi_in_U0_ap_continue; +wire td_fused_axi_in_U0_ap_idle; +wire td_fused_axi_in_U0_ap_ready; +wire td_fused_axi_in_U0_stream_in_TREADY; +wire [15:0] td_fused_axi_in_U0_fmaps_address1; +wire td_fused_axi_in_U0_fmaps_ce1; +wire td_fused_axi_in_U0_fmaps_we1; +wire [63:0] td_fused_axi_in_U0_fmaps_d1; +wire ap_channel_done_tdf1_fmaps; +wire td_fused_axi_in_U0_fmaps_full_n; +wire [15:0] tdf1_114_U0_in_data_address0; +wire tdf1_114_U0_in_data_ce0; +wire [63:0] tdf1_114_U0_in_data_d0; +wire tdf1_114_U0_in_data_we0; +wire [15:0] tdf1_114_U0_in_data_address1; +wire tdf1_114_U0_in_data_ce1; +wire [63:0] tdf1_114_U0_in_data_d1; +wire tdf1_114_U0_in_data_we1; +wire [15:0] tdf1_114_U0_out_data_address0; +wire tdf1_114_U0_out_data_ce0; +wire [63:0] tdf1_114_U0_out_data_d0; +wire tdf1_114_U0_out_data_we0; +wire [15:0] tdf1_114_U0_out_data_address1; +wire tdf1_114_U0_out_data_ce1; +wire [63:0] tdf1_114_U0_out_data_d1; +wire tdf1_114_U0_out_data_we1; +wire [8:0] tdf1_114_U0_filter_data_address0; +wire tdf1_114_U0_filter_data_ce0; +wire [15:0] tdf1_114_U0_filter_data_d0; +wire tdf1_114_U0_filter_data_we0; +wire [8:0] tdf1_114_U0_filter_data_address1; +wire tdf1_114_U0_filter_data_ce1; +wire [15:0] tdf1_114_U0_filter_data_d1; +wire tdf1_114_U0_filter_data_we1; +wire [3:0] tdf1_114_U0_adjustments_address0; +wire tdf1_114_U0_adjustments_ce0; +wire [47:0] tdf1_114_U0_adjustments_d0; +wire tdf1_114_U0_adjustments_we0; +wire [3:0] tdf1_114_U0_adjustments_address1; +wire tdf1_114_U0_adjustments_ce1; +wire [47:0] tdf1_114_U0_adjustments_d1; +wire tdf1_114_U0_adjustments_we1; +wire tdf1_114_U0_in_data_read; +wire tdf1_114_U0_out_data_full_n; +wire tdf1_114_U0_out_data_write; +wire tdf1_114_U0_ap_start; +wire tdf1_114_U0_ap_done; +wire tdf1_114_U0_ap_ready; +wire tdf1_114_U0_ap_idle; +wire tdf1_114_U0_ap_continue; +wire ap_channel_done_tdf2_fmaps; +wire [15:0] tdf2_113_U0_in_data_address0; +wire tdf2_113_U0_in_data_ce0; +wire [63:0] tdf2_113_U0_in_data_d0; +wire tdf2_113_U0_in_data_we0; +wire [15:0] tdf2_113_U0_in_data_address1; +wire tdf2_113_U0_in_data_ce1; +wire [63:0] tdf2_113_U0_in_data_d1; +wire tdf2_113_U0_in_data_we1; +wire [14:0] tdf2_113_U0_out_data_address0; +wire tdf2_113_U0_out_data_ce0; +wire [63:0] tdf2_113_U0_out_data_d0; +wire tdf2_113_U0_out_data_we0; +wire [14:0] tdf2_113_U0_out_data_address1; +wire tdf2_113_U0_out_data_ce1; +wire [63:0] tdf2_113_U0_out_data_d1; +wire tdf2_113_U0_out_data_we1; +wire [12:0] tdf2_113_U0_filter_data_address0; +wire tdf2_113_U0_filter_data_ce0; +wire [15:0] tdf2_113_U0_filter_data_d0; +wire tdf2_113_U0_filter_data_we0; +wire [12:0] tdf2_113_U0_filter_data_address1; +wire tdf2_113_U0_filter_data_ce1; +wire [15:0] tdf2_113_U0_filter_data_d1; +wire tdf2_113_U0_filter_data_we1; +wire [4:0] tdf2_113_U0_adjustments_address0; +wire tdf2_113_U0_adjustments_ce0; +wire [47:0] tdf2_113_U0_adjustments_d0; +wire tdf2_113_U0_adjustments_we0; +wire [4:0] tdf2_113_U0_adjustments_address1; +wire tdf2_113_U0_adjustments_ce1; +wire [47:0] tdf2_113_U0_adjustments_d1; +wire tdf2_113_U0_adjustments_we1; +wire tdf2_113_U0_in_data_read; +wire tdf2_113_U0_out_data_full_n; +wire tdf2_113_U0_out_data_write; +wire tdf2_113_U0_ap_start; +wire tdf2_113_U0_ap_done; +wire tdf2_113_U0_ap_ready; +wire tdf2_113_U0_ap_idle; +wire tdf2_113_U0_ap_continue; +wire ap_channel_done_tdf3_fmaps; +wire [14:0] tdf3_112_U0_in_data_address0; +wire tdf3_112_U0_in_data_ce0; +wire [63:0] tdf3_112_U0_in_data_d0; +wire tdf3_112_U0_in_data_we0; +wire [14:0] tdf3_112_U0_in_data_address1; +wire tdf3_112_U0_in_data_ce1; +wire [63:0] tdf3_112_U0_in_data_d1; +wire tdf3_112_U0_in_data_we1; +wire [13:0] tdf3_112_U0_out_data_address0; +wire tdf3_112_U0_out_data_ce0; +wire [63:0] tdf3_112_U0_out_data_d0; +wire tdf3_112_U0_out_data_we0; +wire [13:0] tdf3_112_U0_out_data_address1; +wire tdf3_112_U0_out_data_ce1; +wire [63:0] tdf3_112_U0_out_data_d1; +wire tdf3_112_U0_out_data_we1; +wire [8:0] tdf3_112_U0_filter_data_address0; +wire tdf3_112_U0_filter_data_ce0; +wire [15:0] tdf3_112_U0_filter_data_d0; +wire tdf3_112_U0_filter_data_we0; +wire [8:0] tdf3_112_U0_filter_data_address1; +wire tdf3_112_U0_filter_data_ce1; +wire [15:0] tdf3_112_U0_filter_data_d1; +wire tdf3_112_U0_filter_data_we1; +wire [3:0] tdf3_112_U0_adjustments_address0; +wire tdf3_112_U0_adjustments_ce0; +wire [47:0] tdf3_112_U0_adjustments_d0; +wire tdf3_112_U0_adjustments_we0; +wire [3:0] tdf3_112_U0_adjustments_address1; +wire tdf3_112_U0_adjustments_ce1; +wire [47:0] tdf3_112_U0_adjustments_d1; +wire tdf3_112_U0_adjustments_we1; +wire tdf3_112_U0_in_data_read; +wire tdf3_112_U0_out_data_full_n; +wire tdf3_112_U0_out_data_write; +wire tdf3_112_U0_ap_start; +wire tdf3_112_U0_ap_done; +wire tdf3_112_U0_ap_ready; +wire tdf3_112_U0_ap_idle; +wire tdf3_112_U0_ap_continue; +wire ap_channel_done_tdf4_fmaps; +wire [13:0] tdf4_111_U0_in_data_address0; +wire tdf4_111_U0_in_data_ce0; +wire [63:0] tdf4_111_U0_in_data_d0; +wire tdf4_111_U0_in_data_we0; +wire [13:0] tdf4_111_U0_in_data_address1; +wire tdf4_111_U0_in_data_ce1; +wire [63:0] tdf4_111_U0_in_data_d1; +wire tdf4_111_U0_in_data_we1; +wire [13:0] tdf4_111_U0_out_data_address0; +wire tdf4_111_U0_out_data_ce0; +wire [63:0] tdf4_111_U0_out_data_d0; +wire tdf4_111_U0_out_data_we0; +wire [13:0] tdf4_111_U0_out_data_address1; +wire tdf4_111_U0_out_data_ce1; +wire [63:0] tdf4_111_U0_out_data_d1; +wire tdf4_111_U0_out_data_we1; +wire [14:0] tdf4_111_U0_l1_filter_data_address0; +wire tdf4_111_U0_l1_filter_data_ce0; +wire [15:0] tdf4_111_U0_l1_filter_data_d0; +wire tdf4_111_U0_l1_filter_data_we0; +wire [14:0] tdf4_111_U0_l1_filter_data_address1; +wire tdf4_111_U0_l1_filter_data_ce1; +wire [15:0] tdf4_111_U0_l1_filter_data_d1; +wire tdf4_111_U0_l1_filter_data_we1; +wire [10:0] tdf4_111_U0_l2_filter_data_address0; +wire tdf4_111_U0_l2_filter_data_ce0; +wire [15:0] tdf4_111_U0_l2_filter_data_d0; +wire tdf4_111_U0_l2_filter_data_we0; +wire [10:0] tdf4_111_U0_l2_filter_data_address1; +wire tdf4_111_U0_l2_filter_data_ce1; +wire [15:0] tdf4_111_U0_l2_filter_data_d1; +wire tdf4_111_U0_l2_filter_data_we1; +wire [6:0] tdf4_111_U0_l1_adjustments_address0; +wire tdf4_111_U0_l1_adjustments_ce0; +wire [47:0] tdf4_111_U0_l1_adjustments_d0; +wire tdf4_111_U0_l1_adjustments_we0; +wire [6:0] tdf4_111_U0_l1_adjustments_address1; +wire tdf4_111_U0_l1_adjustments_ce1; +wire [47:0] tdf4_111_U0_l1_adjustments_d1; +wire tdf4_111_U0_l1_adjustments_we1; +wire [3:0] tdf4_111_U0_l2_adjustments_address0; +wire tdf4_111_U0_l2_adjustments_ce0; +wire [47:0] tdf4_111_U0_l2_adjustments_d0; +wire tdf4_111_U0_l2_adjustments_we0; +wire [3:0] tdf4_111_U0_l2_adjustments_address1; +wire tdf4_111_U0_l2_adjustments_ce1; +wire [47:0] tdf4_111_U0_l2_adjustments_d1; +wire tdf4_111_U0_l2_adjustments_we1; +wire tdf4_111_U0_in_data_read; +wire tdf4_111_U0_out_data_full_n; +wire tdf4_111_U0_out_data_write; +wire tdf4_111_U0_ap_start; +wire tdf4_111_U0_ap_done; +wire tdf4_111_U0_ap_ready; +wire tdf4_111_U0_ap_idle; +wire tdf4_111_U0_ap_continue; +wire ap_channel_done_tdf5_fmaps; +wire [13:0] tdf5_110_U0_in_data_address0; +wire tdf5_110_U0_in_data_ce0; +wire [63:0] tdf5_110_U0_in_data_d0; +wire tdf5_110_U0_in_data_we0; +wire [13:0] tdf5_110_U0_in_data_address1; +wire tdf5_110_U0_in_data_ce1; +wire [63:0] tdf5_110_U0_in_data_d1; +wire tdf5_110_U0_in_data_we1; +wire [14:0] tdf5_110_U0_out_data_address0; +wire tdf5_110_U0_out_data_ce0; +wire [63:0] tdf5_110_U0_out_data_d0; +wire tdf5_110_U0_out_data_we0; +wire [14:0] tdf5_110_U0_out_data_address1; +wire tdf5_110_U0_out_data_ce1; +wire [63:0] tdf5_110_U0_out_data_d1; +wire tdf5_110_U0_out_data_we1; +wire [14:0] tdf5_110_U0_filter_data_address0; +wire tdf5_110_U0_filter_data_ce0; +wire [15:0] tdf5_110_U0_filter_data_d0; +wire tdf5_110_U0_filter_data_we0; +wire [14:0] tdf5_110_U0_filter_data_address1; +wire tdf5_110_U0_filter_data_ce1; +wire [15:0] tdf5_110_U0_filter_data_d1; +wire tdf5_110_U0_filter_data_we1; +wire [6:0] tdf5_110_U0_adjustments_address0; +wire tdf5_110_U0_adjustments_ce0; +wire [47:0] tdf5_110_U0_adjustments_d0; +wire tdf5_110_U0_adjustments_we0; +wire [6:0] tdf5_110_U0_adjustments_address1; +wire tdf5_110_U0_adjustments_ce1; +wire [47:0] tdf5_110_U0_adjustments_d1; +wire tdf5_110_U0_adjustments_we1; +wire tdf5_110_U0_in_data_read; +wire tdf5_110_U0_out_data_full_n; +wire tdf5_110_U0_out_data_write; +wire tdf5_110_U0_ap_start; +wire tdf5_110_U0_ap_done; +wire tdf5_110_U0_ap_ready; +wire tdf5_110_U0_ap_idle; +wire tdf5_110_U0_ap_continue; +wire ap_channel_done_tdf6_fmaps; +wire [14:0] tdf6_19_U0_in_data_address0; +wire tdf6_19_U0_in_data_ce0; +wire [63:0] tdf6_19_U0_in_data_d0; +wire tdf6_19_U0_in_data_we0; +wire [14:0] tdf6_19_U0_in_data_address1; +wire tdf6_19_U0_in_data_ce1; +wire [63:0] tdf6_19_U0_in_data_d1; +wire tdf6_19_U0_in_data_we1; +wire [12:0] tdf6_19_U0_out_data_address0; +wire tdf6_19_U0_out_data_ce0; +wire [63:0] tdf6_19_U0_out_data_d0; +wire tdf6_19_U0_out_data_we0; +wire [12:0] tdf6_19_U0_out_data_address1; +wire tdf6_19_U0_out_data_ce1; +wire [63:0] tdf6_19_U0_out_data_d1; +wire tdf6_19_U0_out_data_we1; +wire [11:0] tdf6_19_U0_filter_data_address0; +wire tdf6_19_U0_filter_data_ce0; +wire [15:0] tdf6_19_U0_filter_data_d0; +wire tdf6_19_U0_filter_data_we0; +wire [11:0] tdf6_19_U0_filter_data_address1; +wire tdf6_19_U0_filter_data_ce1; +wire [15:0] tdf6_19_U0_filter_data_d1; +wire tdf6_19_U0_filter_data_we1; +wire [4:0] tdf6_19_U0_adjustments_address0; +wire tdf6_19_U0_adjustments_ce0; +wire [47:0] tdf6_19_U0_adjustments_d0; +wire tdf6_19_U0_adjustments_we0; +wire [4:0] tdf6_19_U0_adjustments_address1; +wire tdf6_19_U0_adjustments_ce1; +wire [47:0] tdf6_19_U0_adjustments_d1; +wire tdf6_19_U0_adjustments_we1; +wire tdf6_19_U0_in_data_read; +wire tdf6_19_U0_out_data_full_n; +wire tdf6_19_U0_out_data_write; +wire tdf6_19_U0_ap_start; +wire tdf6_19_U0_ap_done; +wire tdf6_19_U0_ap_ready; +wire tdf6_19_U0_ap_idle; +wire tdf6_19_U0_ap_continue; +wire ap_channel_done_tdf7_fmaps; +wire [12:0] tdf7_18_U0_in_data_address0; +wire tdf7_18_U0_in_data_ce0; +wire [63:0] tdf7_18_U0_in_data_d0; +wire tdf7_18_U0_in_data_we0; +wire [12:0] tdf7_18_U0_in_data_address1; +wire tdf7_18_U0_in_data_ce1; +wire [63:0] tdf7_18_U0_in_data_d1; +wire tdf7_18_U0_in_data_we1; +wire [12:0] tdf7_18_U0_out_data_address0; +wire tdf7_18_U0_out_data_ce0; +wire [63:0] tdf7_18_U0_out_data_d0; +wire tdf7_18_U0_out_data_we0; +wire [12:0] tdf7_18_U0_out_data_address1; +wire tdf7_18_U0_out_data_ce1; +wire [63:0] tdf7_18_U0_out_data_d1; +wire tdf7_18_U0_out_data_we1; +wire [16:0] tdf7_18_U0_l1_filter_data_address0; +wire tdf7_18_U0_l1_filter_data_ce0; +wire [15:0] tdf7_18_U0_l1_filter_data_d0; +wire tdf7_18_U0_l1_filter_data_we0; +wire [16:0] tdf7_18_U0_l1_filter_data_address1; +wire tdf7_18_U0_l1_filter_data_ce1; +wire [15:0] tdf7_18_U0_l1_filter_data_d1; +wire tdf7_18_U0_l1_filter_data_we1; +wire [12:0] tdf7_18_U0_l2_filter_data_address0; +wire tdf7_18_U0_l2_filter_data_ce0; +wire [15:0] tdf7_18_U0_l2_filter_data_d0; +wire tdf7_18_U0_l2_filter_data_we0; +wire [12:0] tdf7_18_U0_l2_filter_data_address1; +wire tdf7_18_U0_l2_filter_data_ce1; +wire [15:0] tdf7_18_U0_l2_filter_data_d1; +wire tdf7_18_U0_l2_filter_data_we1; +wire [7:0] tdf7_18_U0_l1_adjustments_address0; +wire tdf7_18_U0_l1_adjustments_ce0; +wire [47:0] tdf7_18_U0_l1_adjustments_d0; +wire tdf7_18_U0_l1_adjustments_we0; +wire [7:0] tdf7_18_U0_l1_adjustments_address1; +wire tdf7_18_U0_l1_adjustments_ce1; +wire [47:0] tdf7_18_U0_l1_adjustments_d1; +wire tdf7_18_U0_l1_adjustments_we1; +wire [4:0] tdf7_18_U0_l2_adjustments_address0; +wire tdf7_18_U0_l2_adjustments_ce0; +wire [47:0] tdf7_18_U0_l2_adjustments_d0; +wire tdf7_18_U0_l2_adjustments_we0; +wire [4:0] tdf7_18_U0_l2_adjustments_address1; +wire tdf7_18_U0_l2_adjustments_ce1; +wire [47:0] tdf7_18_U0_l2_adjustments_d1; +wire tdf7_18_U0_l2_adjustments_we1; +wire tdf7_18_U0_in_data_read; +wire tdf7_18_U0_out_data_full_n; +wire tdf7_18_U0_out_data_write; +wire tdf7_18_U0_ap_start; +wire tdf7_18_U0_ap_done; +wire tdf7_18_U0_ap_ready; +wire tdf7_18_U0_ap_idle; +wire tdf7_18_U0_ap_continue; +wire ap_channel_done_tdf8_fmaps; +wire [12:0] tdf8_17_U0_in_data_address0; +wire tdf8_17_U0_in_data_ce0; +wire [63:0] tdf8_17_U0_in_data_d0; +wire tdf8_17_U0_in_data_we0; +wire [12:0] tdf8_17_U0_in_data_address1; +wire tdf8_17_U0_in_data_ce1; +wire [63:0] tdf8_17_U0_in_data_d1; +wire tdf8_17_U0_in_data_we1; +wire [13:0] tdf8_17_U0_out_data_address0; +wire tdf8_17_U0_out_data_ce0; +wire [63:0] tdf8_17_U0_out_data_d0; +wire tdf8_17_U0_out_data_we0; +wire [13:0] tdf8_17_U0_out_data_address1; +wire tdf8_17_U0_out_data_ce1; +wire [63:0] tdf8_17_U0_out_data_d1; +wire tdf8_17_U0_out_data_we1; +wire [16:0] tdf8_17_U0_filter_data_address0; +wire tdf8_17_U0_filter_data_ce0; +wire [15:0] tdf8_17_U0_filter_data_d0; +wire tdf8_17_U0_filter_data_we0; +wire [16:0] tdf8_17_U0_filter_data_address1; +wire tdf8_17_U0_filter_data_ce1; +wire [15:0] tdf8_17_U0_filter_data_d1; +wire tdf8_17_U0_filter_data_we1; +wire [7:0] tdf8_17_U0_adjustments_address0; +wire tdf8_17_U0_adjustments_ce0; +wire [47:0] tdf8_17_U0_adjustments_d0; +wire tdf8_17_U0_adjustments_we0; +wire [7:0] tdf8_17_U0_adjustments_address1; +wire tdf8_17_U0_adjustments_ce1; +wire [47:0] tdf8_17_U0_adjustments_d1; +wire tdf8_17_U0_adjustments_we1; +wire tdf8_17_U0_in_data_read; +wire tdf8_17_U0_out_data_full_n; +wire tdf8_17_U0_out_data_write; +wire tdf8_17_U0_ap_start; +wire tdf8_17_U0_ap_done; +wire tdf8_17_U0_ap_ready; +wire tdf8_17_U0_ap_idle; +wire tdf8_17_U0_ap_continue; +wire ap_channel_done_tdf9_fmaps; +wire [13:0] tdf9_16_U0_in_data_address0; +wire tdf9_16_U0_in_data_ce0; +wire [63:0] tdf9_16_U0_in_data_d0; +wire tdf9_16_U0_in_data_we0; +wire [13:0] tdf9_16_U0_in_data_address1; +wire tdf9_16_U0_in_data_ce1; +wire [63:0] tdf9_16_U0_in_data_d1; +wire tdf9_16_U0_in_data_we1; +wire [11:0] tdf9_16_U0_out_data_address0; +wire tdf9_16_U0_out_data_ce0; +wire [63:0] tdf9_16_U0_out_data_d0; +wire tdf9_16_U0_out_data_we0; +wire [11:0] tdf9_16_U0_out_data_address1; +wire tdf9_16_U0_out_data_ce1; +wire [63:0] tdf9_16_U0_out_data_d1; +wire tdf9_16_U0_out_data_we1; +wire [13:0] tdf9_16_U0_filter_data_address0; +wire tdf9_16_U0_filter_data_ce0; +wire [15:0] tdf9_16_U0_filter_data_d0; +wire tdf9_16_U0_filter_data_we0; +wire [13:0] tdf9_16_U0_filter_data_address1; +wire tdf9_16_U0_filter_data_ce1; +wire [15:0] tdf9_16_U0_filter_data_d1; +wire tdf9_16_U0_filter_data_we1; +wire [5:0] tdf9_16_U0_adjustments_address0; +wire tdf9_16_U0_adjustments_ce0; +wire [47:0] tdf9_16_U0_adjustments_d0; +wire tdf9_16_U0_adjustments_we0; +wire [5:0] tdf9_16_U0_adjustments_address1; +wire tdf9_16_U0_adjustments_ce1; +wire [47:0] tdf9_16_U0_adjustments_d1; +wire tdf9_16_U0_adjustments_we1; +wire tdf9_16_U0_in_data_read; +wire tdf9_16_U0_out_data_full_n; +wire tdf9_16_U0_out_data_write; +wire tdf9_16_U0_ap_start; +wire tdf9_16_U0_ap_done; +wire tdf9_16_U0_ap_ready; +wire tdf9_16_U0_ap_idle; +wire tdf9_16_U0_ap_continue; +wire ap_channel_done_tdf10_fmaps; +wire [11:0] tdf10_15_U0_in_data_address0; +wire tdf10_15_U0_in_data_ce0; +wire [63:0] tdf10_15_U0_in_data_d0; +wire tdf10_15_U0_in_data_we0; +wire [11:0] tdf10_15_U0_in_data_address1; +wire tdf10_15_U0_in_data_ce1; +wire [63:0] tdf10_15_U0_in_data_d1; +wire tdf10_15_U0_in_data_we1; +wire [11:0] tdf10_15_U0_out_data_address0; +wire tdf10_15_U0_out_data_ce0; +wire [63:0] tdf10_15_U0_out_data_d0; +wire tdf10_15_U0_out_data_we0; +wire [11:0] tdf10_15_U0_out_data_address1; +wire tdf10_15_U0_out_data_ce1; +wire [63:0] tdf10_15_U0_out_data_d1; +wire tdf10_15_U0_out_data_we1; +wire [16:0] tdf10_15_U0_l1_filter_data_address0; +wire tdf10_15_U0_l1_filter_data_ce0; +wire [63:0] tdf10_15_U0_l1_filter_data_d0; +wire tdf10_15_U0_l1_filter_data_we0; +wire [16:0] tdf10_15_U0_l1_filter_data_address1; +wire tdf10_15_U0_l1_filter_data_ce1; +wire [63:0] tdf10_15_U0_l1_filter_data_d1; +wire tdf10_15_U0_l1_filter_data_we1; +wire [14:0] tdf10_15_U0_l2_filter_data_address0; +wire tdf10_15_U0_l2_filter_data_ce0; +wire [15:0] tdf10_15_U0_l2_filter_data_d0; +wire tdf10_15_U0_l2_filter_data_we0; +wire [14:0] tdf10_15_U0_l2_filter_data_address1; +wire tdf10_15_U0_l2_filter_data_ce1; +wire [15:0] tdf10_15_U0_l2_filter_data_d1; +wire tdf10_15_U0_l2_filter_data_we1; +wire [8:0] tdf10_15_U0_l1_adjustments_address0; +wire tdf10_15_U0_l1_adjustments_ce0; +wire [47:0] tdf10_15_U0_l1_adjustments_d0; +wire tdf10_15_U0_l1_adjustments_we0; +wire [8:0] tdf10_15_U0_l1_adjustments_address1; +wire tdf10_15_U0_l1_adjustments_ce1; +wire [47:0] tdf10_15_U0_l1_adjustments_d1; +wire tdf10_15_U0_l1_adjustments_we1; +wire [5:0] tdf10_15_U0_l2_adjustments_address0; +wire tdf10_15_U0_l2_adjustments_ce0; +wire [47:0] tdf10_15_U0_l2_adjustments_d0; +wire tdf10_15_U0_l2_adjustments_we0; +wire [5:0] tdf10_15_U0_l2_adjustments_address1; +wire tdf10_15_U0_l2_adjustments_ce1; +wire [47:0] tdf10_15_U0_l2_adjustments_d1; +wire tdf10_15_U0_l2_adjustments_we1; +wire tdf10_15_U0_in_data_read; +wire tdf10_15_U0_out_data_full_n; +wire tdf10_15_U0_out_data_write; +wire tdf10_15_U0_ap_start; +wire tdf10_15_U0_ap_done; +wire tdf10_15_U0_ap_ready; +wire tdf10_15_U0_ap_idle; +wire tdf10_15_U0_ap_continue; +wire ap_channel_done_tdf11_fmaps; +wire [11:0] tdf11_14_U0_in_data_address0; +wire tdf11_14_U0_in_data_ce0; +wire [63:0] tdf11_14_U0_in_data_d0; +wire tdf11_14_U0_in_data_we0; +wire [11:0] tdf11_14_U0_in_data_address1; +wire tdf11_14_U0_in_data_ce1; +wire [63:0] tdf11_14_U0_in_data_d1; +wire tdf11_14_U0_in_data_we1; +wire [12:0] tdf11_14_U0_out_data_address0; +wire tdf11_14_U0_out_data_ce0; +wire [63:0] tdf11_14_U0_out_data_d0; +wire tdf11_14_U0_out_data_we0; +wire [12:0] tdf11_14_U0_out_data_address1; +wire tdf11_14_U0_out_data_ce1; +wire [63:0] tdf11_14_U0_out_data_d1; +wire tdf11_14_U0_out_data_we1; +wire [16:0] tdf11_14_U0_l1_filter_data_address0; +wire tdf11_14_U0_l1_filter_data_ce0; +wire [63:0] tdf11_14_U0_l1_filter_data_d0; +wire tdf11_14_U0_l1_filter_data_we0; +wire [16:0] tdf11_14_U0_l1_filter_data_address1; +wire tdf11_14_U0_l1_filter_data_ce1; +wire [63:0] tdf11_14_U0_l1_filter_data_d1; +wire tdf11_14_U0_l1_filter_data_we1; +wire [15:0] tdf11_14_U0_l2_filter_data_address0; +wire tdf11_14_U0_l2_filter_data_ce0; +wire [15:0] tdf11_14_U0_l2_filter_data_d0; +wire tdf11_14_U0_l2_filter_data_we0; +wire [15:0] tdf11_14_U0_l2_filter_data_address1; +wire tdf11_14_U0_l2_filter_data_ce1; +wire [15:0] tdf11_14_U0_l2_filter_data_d1; +wire tdf11_14_U0_l2_filter_data_we1; +wire [8:0] tdf11_14_U0_l1_adjustments_address0; +wire tdf11_14_U0_l1_adjustments_ce0; +wire [47:0] tdf11_14_U0_l1_adjustments_d0; +wire tdf11_14_U0_l1_adjustments_we0; +wire [8:0] tdf11_14_U0_l1_adjustments_address1; +wire tdf11_14_U0_l1_adjustments_ce1; +wire [47:0] tdf11_14_U0_l1_adjustments_d1; +wire tdf11_14_U0_l1_adjustments_we1; +wire [6:0] tdf11_14_U0_l2_adjustments_address0; +wire tdf11_14_U0_l2_adjustments_ce0; +wire [47:0] tdf11_14_U0_l2_adjustments_d0; +wire tdf11_14_U0_l2_adjustments_we0; +wire [6:0] tdf11_14_U0_l2_adjustments_address1; +wire tdf11_14_U0_l2_adjustments_ce1; +wire [47:0] tdf11_14_U0_l2_adjustments_d1; +wire tdf11_14_U0_l2_adjustments_we1; +wire tdf11_14_U0_in_data_read; +wire tdf11_14_U0_out_data_full_n; +wire tdf11_14_U0_out_data_write; +wire tdf11_14_U0_ap_start; +wire tdf11_14_U0_ap_done; +wire tdf11_14_U0_ap_ready; +wire tdf11_14_U0_ap_idle; +wire tdf11_14_U0_ap_continue; +wire ap_channel_done_tdf12_fmaps; +wire [12:0] tdf12_13_U0_in_data_address0; +wire tdf12_13_U0_in_data_ce0; +wire [63:0] tdf12_13_U0_in_data_d0; +wire tdf12_13_U0_in_data_we0; +wire [12:0] tdf12_13_U0_in_data_address1; +wire tdf12_13_U0_in_data_ce1; +wire [63:0] tdf12_13_U0_in_data_d1; +wire tdf12_13_U0_in_data_we1; +wire [15:0] tdf12_13_U0_out_data_address0; +wire tdf12_13_U0_out_data_ce0; +wire [63:0] tdf12_13_U0_out_data_d0; +wire tdf12_13_U0_out_data_we0; +wire [15:0] tdf12_13_U0_out_data_address1; +wire tdf12_13_U0_out_data_ce1; +wire [63:0] tdf12_13_U0_out_data_d1; +wire tdf12_13_U0_out_data_we1; +wire [16:0] tdf12_13_U0_filter_data_address0; +wire tdf12_13_U0_filter_data_ce0; +wire [15:0] tdf12_13_U0_filter_data_d0; +wire tdf12_13_U0_filter_data_we0; +wire [16:0] tdf12_13_U0_filter_data_address1; +wire tdf12_13_U0_filter_data_ce1; +wire [15:0] tdf12_13_U0_filter_data_d1; +wire tdf12_13_U0_filter_data_we1; +wire [9:0] tdf12_13_U0_adjustments_address0; +wire tdf12_13_U0_adjustments_ce0; +wire [47:0] tdf12_13_U0_adjustments_d0; +wire tdf12_13_U0_adjustments_we0; +wire [9:0] tdf12_13_U0_adjustments_address1; +wire tdf12_13_U0_adjustments_ce1; +wire [47:0] tdf12_13_U0_adjustments_d1; +wire tdf12_13_U0_adjustments_we1; +wire tdf12_13_U0_in_data_read; +wire tdf12_13_U0_out_data_full_n; +wire tdf12_13_U0_out_data_write; +wire tdf12_13_U0_ap_start; +wire tdf12_13_U0_ap_done; +wire tdf12_13_U0_ap_ready; +wire tdf12_13_U0_ap_idle; +wire tdf12_13_U0_ap_continue; +wire ap_channel_done_final_fmaps; +wire td_fused_axi_out_U0_ap_start; +wire td_fused_axi_out_U0_ap_done; +wire td_fused_axi_out_U0_ap_continue; +wire td_fused_axi_out_U0_ap_idle; +wire td_fused_axi_out_U0_ap_ready; +wire [15:0] td_fused_axi_out_U0_fmaps_address0; +wire td_fused_axi_out_U0_fmaps_ce0; +wire [15:0] td_fused_axi_out_U0_stream_out_TDATA; +wire td_fused_axi_out_U0_stream_out_TVALID; +wire [1:0] td_fused_axi_out_U0_stream_out_TKEEP; +wire [1:0] td_fused_axi_out_U0_stream_out_TSTRB; +wire [0:0] td_fused_axi_out_U0_stream_out_TLAST; +wire ap_sync_continue; +wire tdf1_fmaps_i_full_n; +wire tdf1_fmaps_t_empty_n; +wire [63:0] tdf1_fmaps_t_d0; +wire tdf1_fmaps_t_we0; +wire tdf2_fmaps_i_full_n; +wire tdf2_fmaps_t_empty_n; +wire [63:0] tdf2_fmaps_t_d0; +wire tdf2_fmaps_t_we0; +wire tdf3_fmaps_i_full_n; +wire tdf3_fmaps_t_empty_n; +wire [63:0] tdf3_fmaps_t_d0; +wire tdf3_fmaps_t_we0; +wire tdf4_fmaps_i_full_n; +wire tdf4_fmaps_t_empty_n; +wire [63:0] tdf4_fmaps_t_d0; +wire tdf4_fmaps_t_we0; +wire tdf5_fmaps_i_full_n; +wire tdf5_fmaps_t_empty_n; +wire [63:0] tdf5_fmaps_t_d0; +wire tdf5_fmaps_t_we0; +wire tdf6_fmaps_i_full_n; +wire tdf6_fmaps_t_empty_n; +wire [63:0] tdf6_fmaps_t_d0; +wire tdf6_fmaps_t_we0; +wire tdf7_fmaps_i_full_n; +wire tdf7_fmaps_t_empty_n; +wire [63:0] tdf7_fmaps_t_d0; +wire tdf7_fmaps_t_we0; +wire tdf8_fmaps_i_full_n; +wire tdf8_fmaps_t_empty_n; +wire [63:0] tdf8_fmaps_t_d0; +wire tdf8_fmaps_t_we0; +wire tdf9_fmaps_i_full_n; +wire tdf9_fmaps_t_empty_n; +wire [63:0] tdf9_fmaps_t_d0; +wire tdf9_fmaps_t_we0; +wire tdf10_fmaps_i_full_n; +wire tdf10_fmaps_t_empty_n; +wire [63:0] tdf10_fmaps_t_d0; +wire tdf10_fmaps_t_we0; +wire tdf11_fmaps_i_full_n; +wire tdf11_fmaps_t_empty_n; +wire [63:0] tdf11_fmaps_t_d0; +wire tdf11_fmaps_t_we0; +wire tdf12_fmaps_i_full_n; +wire tdf12_fmaps_t_empty_n; +wire [63:0] tdf12_fmaps_t_d0; +wire tdf12_fmaps_t_we0; +wire final_fmaps_i_full_n; +wire final_fmaps_t_empty_n; +wire [63:0] final_fmaps_t_d0; +wire final_fmaps_t_we0; +wire ap_sync_done; +wire ap_sync_ready; +wire td_fused_axi_in_U0_start_full_n; +wire td_fused_axi_in_U0_start_write; +wire tdf1_114_U0_start_full_n; +wire tdf1_114_U0_start_write; +wire tdf2_113_U0_start_full_n; +wire tdf2_113_U0_start_write; +wire tdf3_112_U0_start_full_n; +wire tdf3_112_U0_start_write; +wire tdf4_111_U0_start_full_n; +wire tdf4_111_U0_start_write; +wire tdf5_110_U0_start_full_n; +wire tdf5_110_U0_start_write; +wire tdf6_19_U0_start_full_n; +wire tdf6_19_U0_start_write; +wire tdf7_18_U0_start_full_n; +wire tdf7_18_U0_start_write; +wire tdf8_17_U0_start_full_n; +wire tdf8_17_U0_start_write; +wire tdf9_16_U0_start_full_n; +wire tdf9_16_U0_start_write; +wire tdf10_15_U0_start_full_n; +wire tdf10_15_U0_start_write; +wire tdf11_14_U0_start_full_n; +wire tdf11_14_U0_start_write; +wire tdf12_13_U0_start_full_n; +wire tdf12_13_U0_start_write; +wire td_fused_axi_out_U0_start_full_n; +wire td_fused_axi_out_U0_start_write; + +td_fused_top_td_fused_tdf1_fmaps #( + .DataWidth( 64 ), + .AddressRange( 50176 ), + .AddressWidth( 16 )) +tdf1_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(td_fused_axi_in_U0_ap_done), + .i_full_n(tdf1_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(16'd0), + .i_q0(tdf1_fmaps_i_q0), + .i_ce1(td_fused_axi_in_U0_fmaps_ce1), + .i_we1(td_fused_axi_in_U0_fmaps_we1), + .i_address1(td_fused_axi_in_U0_fmaps_address1), + .i_d1(td_fused_axi_in_U0_fmaps_d1), + .t_ce(1'b1), + .t_read(tdf1_114_U0_ap_ready), + .t_empty_n(tdf1_fmaps_t_empty_n), + .t_ce0(tdf1_114_U0_in_data_ce0), + .t_address0(tdf1_114_U0_in_data_address0), + .t_q0(tdf1_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(16'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf1_fmaps #( + .DataWidth( 64 ), + .AddressRange( 50176 ), + .AddressWidth( 16 )) +tdf2_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf1_114_U0_ap_done), + .i_full_n(tdf2_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(16'd0), + .i_q0(tdf2_fmaps_i_q0), + .i_ce1(tdf1_114_U0_out_data_ce1), + .i_we1(tdf1_114_U0_out_data_we1), + .i_address1(tdf1_114_U0_out_data_address1), + .i_d1(tdf1_114_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf2_113_U0_ap_ready), + .t_empty_n(tdf2_fmaps_t_empty_n), + .t_ce0(tdf2_113_U0_in_data_ce0), + .t_address0(tdf2_113_U0_in_data_address0), + .t_q0(tdf2_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(16'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf3_fmaps #( + .DataWidth( 64 ), + .AddressRange( 25088 ), + .AddressWidth( 15 )) +tdf3_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf2_113_U0_ap_done), + .i_full_n(tdf3_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(15'd0), + .i_q0(tdf3_fmaps_i_q0), + .i_ce1(tdf2_113_U0_out_data_ce1), + .i_we1(tdf2_113_U0_out_data_we1), + .i_address1(tdf2_113_U0_out_data_address1), + .i_d1(tdf2_113_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf3_112_U0_ap_ready), + .t_empty_n(tdf3_fmaps_t_empty_n), + .t_ce0(tdf3_112_U0_in_data_ce0), + .t_address0(tdf3_112_U0_in_data_address0), + .t_q0(tdf3_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(15'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf4_fmaps #( + .DataWidth( 64 ), + .AddressRange( 12544 ), + .AddressWidth( 14 )) +tdf4_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf3_112_U0_ap_done), + .i_full_n(tdf4_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(14'd0), + .i_q0(tdf4_fmaps_i_q0), + .i_ce1(tdf3_112_U0_out_data_ce1), + .i_we1(tdf3_112_U0_out_data_we1), + .i_address1(tdf3_112_U0_out_data_address1), + .i_d1(tdf3_112_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf4_111_U0_ap_ready), + .t_empty_n(tdf4_fmaps_t_empty_n), + .t_ce0(tdf4_111_U0_in_data_ce0), + .t_address0(tdf4_111_U0_in_data_address0), + .t_q0(tdf4_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(14'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf4_fmaps #( + .DataWidth( 64 ), + .AddressRange( 12544 ), + .AddressWidth( 14 )) +tdf5_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf4_111_U0_ap_done), + .i_full_n(tdf5_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(14'd0), + .i_q0(tdf5_fmaps_i_q0), + .i_ce1(tdf4_111_U0_out_data_ce1), + .i_we1(tdf4_111_U0_out_data_we1), + .i_address1(tdf4_111_U0_out_data_address1), + .i_d1(tdf4_111_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf5_110_U0_ap_ready), + .t_empty_n(tdf5_fmaps_t_empty_n), + .t_ce0(tdf5_110_U0_in_data_ce0), + .t_address0(tdf5_110_U0_in_data_address0), + .t_q0(tdf5_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(14'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf3_fmaps #( + .DataWidth( 64 ), + .AddressRange( 25088 ), + .AddressWidth( 15 )) +tdf6_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf5_110_U0_ap_done), + .i_full_n(tdf6_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(15'd0), + .i_q0(tdf6_fmaps_i_q0), + .i_ce1(tdf5_110_U0_out_data_ce1), + .i_we1(tdf5_110_U0_out_data_we1), + .i_address1(tdf5_110_U0_out_data_address1), + .i_d1(tdf5_110_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf6_19_U0_ap_ready), + .t_empty_n(tdf6_fmaps_t_empty_n), + .t_ce0(tdf6_19_U0_in_data_ce0), + .t_address0(tdf6_19_U0_in_data_address0), + .t_q0(tdf6_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(15'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf7_fmaps #( + .DataWidth( 64 ), + .AddressRange( 6272 ), + .AddressWidth( 13 )) +tdf7_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf6_19_U0_ap_done), + .i_full_n(tdf7_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(13'd0), + .i_q0(tdf7_fmaps_i_q0), + .i_ce1(tdf6_19_U0_out_data_ce1), + .i_we1(tdf6_19_U0_out_data_we1), + .i_address1(tdf6_19_U0_out_data_address1), + .i_d1(tdf6_19_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf7_18_U0_ap_ready), + .t_empty_n(tdf7_fmaps_t_empty_n), + .t_ce0(tdf7_18_U0_in_data_ce0), + .t_address0(tdf7_18_U0_in_data_address0), + .t_q0(tdf7_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(13'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf7_fmaps #( + .DataWidth( 64 ), + .AddressRange( 6272 ), + .AddressWidth( 13 )) +tdf8_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf7_18_U0_ap_done), + .i_full_n(tdf8_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(13'd0), + .i_q0(tdf8_fmaps_i_q0), + .i_ce1(tdf7_18_U0_out_data_ce1), + .i_we1(tdf7_18_U0_out_data_we1), + .i_address1(tdf7_18_U0_out_data_address1), + .i_d1(tdf7_18_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf8_17_U0_ap_ready), + .t_empty_n(tdf8_fmaps_t_empty_n), + .t_ce0(tdf8_17_U0_in_data_ce0), + .t_address0(tdf8_17_U0_in_data_address0), + .t_q0(tdf8_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(13'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf4_fmaps #( + .DataWidth( 64 ), + .AddressRange( 12544 ), + .AddressWidth( 14 )) +tdf9_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf8_17_U0_ap_done), + .i_full_n(tdf9_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(14'd0), + .i_q0(tdf9_fmaps_i_q0), + .i_ce1(tdf8_17_U0_out_data_ce1), + .i_we1(tdf8_17_U0_out_data_we1), + .i_address1(tdf8_17_U0_out_data_address1), + .i_d1(tdf8_17_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf9_16_U0_ap_ready), + .t_empty_n(tdf9_fmaps_t_empty_n), + .t_ce0(tdf9_16_U0_in_data_ce0), + .t_address0(tdf9_16_U0_in_data_address0), + .t_q0(tdf9_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(14'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf10_fmaps #( + .DataWidth( 64 ), + .AddressRange( 3136 ), + .AddressWidth( 12 )) +tdf10_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf9_16_U0_ap_done), + .i_full_n(tdf10_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(12'd0), + .i_q0(tdf10_fmaps_i_q0), + .i_ce1(tdf9_16_U0_out_data_ce1), + .i_we1(tdf9_16_U0_out_data_we1), + .i_address1(tdf9_16_U0_out_data_address1), + .i_d1(tdf9_16_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf10_15_U0_ap_ready), + .t_empty_n(tdf10_fmaps_t_empty_n), + .t_ce0(tdf10_15_U0_in_data_ce0), + .t_address0(tdf10_15_U0_in_data_address0), + .t_q0(tdf10_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(12'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf10_fmaps #( + .DataWidth( 64 ), + .AddressRange( 3136 ), + .AddressWidth( 12 )) +tdf11_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf10_15_U0_ap_done), + .i_full_n(tdf11_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(12'd0), + .i_q0(tdf11_fmaps_i_q0), + .i_ce1(tdf10_15_U0_out_data_ce1), + .i_we1(tdf10_15_U0_out_data_we1), + .i_address1(tdf10_15_U0_out_data_address1), + .i_d1(tdf10_15_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf11_14_U0_ap_ready), + .t_empty_n(tdf11_fmaps_t_empty_n), + .t_ce0(tdf11_14_U0_in_data_ce0), + .t_address0(tdf11_14_U0_in_data_address0), + .t_q0(tdf11_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(12'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_tdf7_fmaps #( + .DataWidth( 64 ), + .AddressRange( 6272 ), + .AddressWidth( 13 )) +tdf12_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf11_14_U0_ap_done), + .i_full_n(tdf12_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(13'd0), + .i_q0(tdf12_fmaps_i_q0), + .i_ce1(tdf11_14_U0_out_data_ce1), + .i_we1(tdf11_14_U0_out_data_we1), + .i_address1(tdf11_14_U0_out_data_address1), + .i_d1(tdf11_14_U0_out_data_d1), + .t_ce(1'b1), + .t_read(tdf12_13_U0_ap_ready), + .t_empty_n(tdf12_fmaps_t_empty_n), + .t_ce0(tdf12_13_U0_in_data_ce0), + .t_address0(tdf12_13_U0_in_data_address0), + .t_q0(tdf12_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(13'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_final_fmaps #( + .DataWidth( 64 ), + .AddressRange( 49000 ), + .AddressWidth( 16 )) +final_fmaps_U( + .clk(ap_clk), + .reset(ap_rst), + .i_ce(1'b1), + .i_write(tdf12_13_U0_ap_done), + .i_full_n(final_fmaps_i_full_n), + .i_ce0(1'b0), + .i_address0(16'd0), + .i_q0(final_fmaps_i_q0), + .i_ce1(tdf12_13_U0_out_data_ce1), + .i_we1(tdf12_13_U0_out_data_we1), + .i_address1(tdf12_13_U0_out_data_address1), + .i_d1(tdf12_13_U0_out_data_d1), + .t_ce(1'b1), + .t_read(td_fused_axi_out_U0_ap_ready), + .t_empty_n(final_fmaps_t_empty_n), + .t_ce0(td_fused_axi_out_U0_fmaps_ce0), + .t_address0(td_fused_axi_out_U0_fmaps_address0), + .t_q0(final_fmaps_t_q0), + .t_ce1(1'b0), + .t_we1(1'b0), + .t_address1(16'd0), + .t_d1(64'd0) +); + +td_fused_top_td_fused_axi_in td_fused_axi_in_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(td_fused_axi_in_U0_ap_start), + .ap_done(td_fused_axi_in_U0_ap_done), + .ap_continue(td_fused_axi_in_U0_ap_continue), + .ap_idle(td_fused_axi_in_U0_ap_idle), + .ap_ready(td_fused_axi_in_U0_ap_ready), + .stream_in_TDATA(stream_in_TDATA), + .stream_in_TVALID(stream_in_TVALID), + .stream_in_TREADY(td_fused_axi_in_U0_stream_in_TREADY), + .stream_in_TKEEP(stream_in_TKEEP), + .stream_in_TSTRB(stream_in_TSTRB), + .stream_in_TLAST(stream_in_TLAST), + .fmaps_address1(td_fused_axi_in_U0_fmaps_address1), + .fmaps_ce1(td_fused_axi_in_U0_fmaps_ce1), + .fmaps_we1(td_fused_axi_in_U0_fmaps_we1), + .fmaps_d1(td_fused_axi_in_U0_fmaps_d1) +); + +td_fused_top_tdf1_114 tdf1_114_U0( + .in_data_address0(tdf1_114_U0_in_data_address0), + .in_data_ce0(tdf1_114_U0_in_data_ce0), + .in_data_d0(tdf1_114_U0_in_data_d0), + .in_data_q0(tdf1_fmaps_t_q0), + .in_data_we0(tdf1_114_U0_in_data_we0), + .in_data_address1(tdf1_114_U0_in_data_address1), + .in_data_ce1(tdf1_114_U0_in_data_ce1), + .in_data_d1(tdf1_114_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf1_114_U0_in_data_we1), + .out_data_address0(tdf1_114_U0_out_data_address0), + .out_data_ce0(tdf1_114_U0_out_data_ce0), + .out_data_d0(tdf1_114_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf1_114_U0_out_data_we0), + .out_data_address1(tdf1_114_U0_out_data_address1), + .out_data_ce1(tdf1_114_U0_out_data_ce1), + .out_data_d1(tdf1_114_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf1_114_U0_out_data_we1), + .filter_data_address0(tdf1_114_U0_filter_data_address0), + .filter_data_ce0(tdf1_114_U0_filter_data_ce0), + .filter_data_d0(tdf1_114_U0_filter_data_d0), + .filter_data_q0(tdf1_filters_q0), + .filter_data_we0(tdf1_114_U0_filter_data_we0), + .filter_data_address1(tdf1_114_U0_filter_data_address1), + .filter_data_ce1(tdf1_114_U0_filter_data_ce1), + .filter_data_d1(tdf1_114_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(tdf1_114_U0_filter_data_we1), + .adjustments_address0(tdf1_114_U0_adjustments_address0), + .adjustments_ce0(tdf1_114_U0_adjustments_ce0), + .adjustments_d0(tdf1_114_U0_adjustments_d0), + .adjustments_q0(tdf1_adjustments_q0), + .adjustments_we0(tdf1_114_U0_adjustments_we0), + .adjustments_address1(tdf1_114_U0_adjustments_address1), + .adjustments_ce1(tdf1_114_U0_adjustments_ce1), + .adjustments_d1(tdf1_114_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf1_114_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf1_114_U0_in_data_read), + .out_data_full_n(tdf2_fmaps_i_full_n), + .out_data_write(tdf1_114_U0_out_data_write), + .ap_start(tdf1_114_U0_ap_start), + .ap_done(tdf1_114_U0_ap_done), + .ap_ready(tdf1_114_U0_ap_ready), + .ap_idle(tdf1_114_U0_ap_idle), + .ap_continue(tdf1_114_U0_ap_continue) +); + +td_fused_top_tdf2_113 tdf2_113_U0( + .in_data_address0(tdf2_113_U0_in_data_address0), + .in_data_ce0(tdf2_113_U0_in_data_ce0), + .in_data_d0(tdf2_113_U0_in_data_d0), + .in_data_q0(tdf2_fmaps_t_q0), + .in_data_we0(tdf2_113_U0_in_data_we0), + .in_data_address1(tdf2_113_U0_in_data_address1), + .in_data_ce1(tdf2_113_U0_in_data_ce1), + .in_data_d1(tdf2_113_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf2_113_U0_in_data_we1), + .out_data_address0(tdf2_113_U0_out_data_address0), + .out_data_ce0(tdf2_113_U0_out_data_ce0), + .out_data_d0(tdf2_113_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf2_113_U0_out_data_we0), + .out_data_address1(tdf2_113_U0_out_data_address1), + .out_data_ce1(tdf2_113_U0_out_data_ce1), + .out_data_d1(tdf2_113_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf2_113_U0_out_data_we1), + .filter_data_address0(tdf2_113_U0_filter_data_address0), + .filter_data_ce0(tdf2_113_U0_filter_data_ce0), + .filter_data_d0(tdf2_113_U0_filter_data_d0), + .filter_data_q0(tdf2_filters_q0), + .filter_data_we0(tdf2_113_U0_filter_data_we0), + .filter_data_address1(tdf2_113_U0_filter_data_address1), + .filter_data_ce1(tdf2_113_U0_filter_data_ce1), + .filter_data_d1(tdf2_113_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(tdf2_113_U0_filter_data_we1), + .adjustments_address0(tdf2_113_U0_adjustments_address0), + .adjustments_ce0(tdf2_113_U0_adjustments_ce0), + .adjustments_d0(tdf2_113_U0_adjustments_d0), + .adjustments_q0(tdf2_adjustments_q0), + .adjustments_we0(tdf2_113_U0_adjustments_we0), + .adjustments_address1(tdf2_113_U0_adjustments_address1), + .adjustments_ce1(tdf2_113_U0_adjustments_ce1), + .adjustments_d1(tdf2_113_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf2_113_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf2_113_U0_in_data_read), + .out_data_full_n(tdf3_fmaps_i_full_n), + .out_data_write(tdf2_113_U0_out_data_write), + .ap_start(tdf2_113_U0_ap_start), + .ap_done(tdf2_113_U0_ap_done), + .ap_ready(tdf2_113_U0_ap_ready), + .ap_idle(tdf2_113_U0_ap_idle), + .ap_continue(tdf2_113_U0_ap_continue) +); + +td_fused_top_tdf3_112 tdf3_112_U0( + .in_data_address0(tdf3_112_U0_in_data_address0), + .in_data_ce0(tdf3_112_U0_in_data_ce0), + .in_data_d0(tdf3_112_U0_in_data_d0), + .in_data_q0(tdf3_fmaps_t_q0), + .in_data_we0(tdf3_112_U0_in_data_we0), + .in_data_address1(tdf3_112_U0_in_data_address1), + .in_data_ce1(tdf3_112_U0_in_data_ce1), + .in_data_d1(tdf3_112_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf3_112_U0_in_data_we1), + .out_data_address0(tdf3_112_U0_out_data_address0), + .out_data_ce0(tdf3_112_U0_out_data_ce0), + .out_data_d0(tdf3_112_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf3_112_U0_out_data_we0), + .out_data_address1(tdf3_112_U0_out_data_address1), + .out_data_ce1(tdf3_112_U0_out_data_ce1), + .out_data_d1(tdf3_112_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf3_112_U0_out_data_we1), + .filter_data_address0(tdf3_112_U0_filter_data_address0), + .filter_data_ce0(tdf3_112_U0_filter_data_ce0), + .filter_data_d0(tdf3_112_U0_filter_data_d0), + .filter_data_q0(tdf3_filters_q0), + .filter_data_we0(tdf3_112_U0_filter_data_we0), + .filter_data_address1(tdf3_112_U0_filter_data_address1), + .filter_data_ce1(tdf3_112_U0_filter_data_ce1), + .filter_data_d1(tdf3_112_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(tdf3_112_U0_filter_data_we1), + .adjustments_address0(tdf3_112_U0_adjustments_address0), + .adjustments_ce0(tdf3_112_U0_adjustments_ce0), + .adjustments_d0(tdf3_112_U0_adjustments_d0), + .adjustments_q0(tdf3_adjustments_q0), + .adjustments_we0(tdf3_112_U0_adjustments_we0), + .adjustments_address1(tdf3_112_U0_adjustments_address1), + .adjustments_ce1(tdf3_112_U0_adjustments_ce1), + .adjustments_d1(tdf3_112_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf3_112_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf3_112_U0_in_data_read), + .out_data_full_n(tdf4_fmaps_i_full_n), + .out_data_write(tdf3_112_U0_out_data_write), + .ap_start(tdf3_112_U0_ap_start), + .ap_done(tdf3_112_U0_ap_done), + .ap_ready(tdf3_112_U0_ap_ready), + .ap_idle(tdf3_112_U0_ap_idle), + .ap_continue(tdf3_112_U0_ap_continue) +); + +td_fused_top_tdf4_111 tdf4_111_U0( + .in_data_address0(tdf4_111_U0_in_data_address0), + .in_data_ce0(tdf4_111_U0_in_data_ce0), + .in_data_d0(tdf4_111_U0_in_data_d0), + .in_data_q0(tdf4_fmaps_t_q0), + .in_data_we0(tdf4_111_U0_in_data_we0), + .in_data_address1(tdf4_111_U0_in_data_address1), + .in_data_ce1(tdf4_111_U0_in_data_ce1), + .in_data_d1(tdf4_111_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf4_111_U0_in_data_we1), + .out_data_address0(tdf4_111_U0_out_data_address0), + .out_data_ce0(tdf4_111_U0_out_data_ce0), + .out_data_d0(tdf4_111_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf4_111_U0_out_data_we0), + .out_data_address1(tdf4_111_U0_out_data_address1), + .out_data_ce1(tdf4_111_U0_out_data_ce1), + .out_data_d1(tdf4_111_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf4_111_U0_out_data_we1), + .l1_filter_data_address0(tdf4_111_U0_l1_filter_data_address0), + .l1_filter_data_ce0(tdf4_111_U0_l1_filter_data_ce0), + .l1_filter_data_d0(tdf4_111_U0_l1_filter_data_d0), + .l1_filter_data_q0(tdf4_filters_q0), + .l1_filter_data_we0(tdf4_111_U0_l1_filter_data_we0), + .l1_filter_data_address1(tdf4_111_U0_l1_filter_data_address1), + .l1_filter_data_ce1(tdf4_111_U0_l1_filter_data_ce1), + .l1_filter_data_d1(tdf4_111_U0_l1_filter_data_d1), + .l1_filter_data_q1(16'd0), + .l1_filter_data_we1(tdf4_111_U0_l1_filter_data_we1), + .l2_filter_data_address0(tdf4_111_U0_l2_filter_data_address0), + .l2_filter_data_ce0(tdf4_111_U0_l2_filter_data_ce0), + .l2_filter_data_d0(tdf4_111_U0_l2_filter_data_d0), + .l2_filter_data_q0(tdf4_l2_filters_q0), + .l2_filter_data_we0(tdf4_111_U0_l2_filter_data_we0), + .l2_filter_data_address1(tdf4_111_U0_l2_filter_data_address1), + .l2_filter_data_ce1(tdf4_111_U0_l2_filter_data_ce1), + .l2_filter_data_d1(tdf4_111_U0_l2_filter_data_d1), + .l2_filter_data_q1(16'd0), + .l2_filter_data_we1(tdf4_111_U0_l2_filter_data_we1), + .l1_adjustments_address0(tdf4_111_U0_l1_adjustments_address0), + .l1_adjustments_ce0(tdf4_111_U0_l1_adjustments_ce0), + .l1_adjustments_d0(tdf4_111_U0_l1_adjustments_d0), + .l1_adjustments_q0(tdf4_adjustments_q0), + .l1_adjustments_we0(tdf4_111_U0_l1_adjustments_we0), + .l1_adjustments_address1(tdf4_111_U0_l1_adjustments_address1), + .l1_adjustments_ce1(tdf4_111_U0_l1_adjustments_ce1), + .l1_adjustments_d1(tdf4_111_U0_l1_adjustments_d1), + .l1_adjustments_q1(48'd0), + .l1_adjustments_we1(tdf4_111_U0_l1_adjustments_we1), + .l2_adjustments_address0(tdf4_111_U0_l2_adjustments_address0), + .l2_adjustments_ce0(tdf4_111_U0_l2_adjustments_ce0), + .l2_adjustments_d0(tdf4_111_U0_l2_adjustments_d0), + .l2_adjustments_q0(tdf4_l2_adjustments_q0), + .l2_adjustments_we0(tdf4_111_U0_l2_adjustments_we0), + .l2_adjustments_address1(tdf4_111_U0_l2_adjustments_address1), + .l2_adjustments_ce1(tdf4_111_U0_l2_adjustments_ce1), + .l2_adjustments_d1(tdf4_111_U0_l2_adjustments_d1), + .l2_adjustments_q1(48'd0), + .l2_adjustments_we1(tdf4_111_U0_l2_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf4_111_U0_in_data_read), + .out_data_full_n(tdf5_fmaps_i_full_n), + .out_data_write(tdf4_111_U0_out_data_write), + .ap_start(tdf4_111_U0_ap_start), + .ap_done(tdf4_111_U0_ap_done), + .ap_ready(tdf4_111_U0_ap_ready), + .ap_idle(tdf4_111_U0_ap_idle), + .ap_continue(tdf4_111_U0_ap_continue) +); + +td_fused_top_tdf5_110 tdf5_110_U0( + .in_data_address0(tdf5_110_U0_in_data_address0), + .in_data_ce0(tdf5_110_U0_in_data_ce0), + .in_data_d0(tdf5_110_U0_in_data_d0), + .in_data_q0(tdf5_fmaps_t_q0), + .in_data_we0(tdf5_110_U0_in_data_we0), + .in_data_address1(tdf5_110_U0_in_data_address1), + .in_data_ce1(tdf5_110_U0_in_data_ce1), + .in_data_d1(tdf5_110_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf5_110_U0_in_data_we1), + .out_data_address0(tdf5_110_U0_out_data_address0), + .out_data_ce0(tdf5_110_U0_out_data_ce0), + .out_data_d0(tdf5_110_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf5_110_U0_out_data_we0), + .out_data_address1(tdf5_110_U0_out_data_address1), + .out_data_ce1(tdf5_110_U0_out_data_ce1), + .out_data_d1(tdf5_110_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf5_110_U0_out_data_we1), + .filter_data_address0(tdf5_110_U0_filter_data_address0), + .filter_data_ce0(tdf5_110_U0_filter_data_ce0), + .filter_data_d0(tdf5_110_U0_filter_data_d0), + .filter_data_q0(tdf5_filters_q0), + .filter_data_we0(tdf5_110_U0_filter_data_we0), + .filter_data_address1(tdf5_110_U0_filter_data_address1), + .filter_data_ce1(tdf5_110_U0_filter_data_ce1), + .filter_data_d1(tdf5_110_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(tdf5_110_U0_filter_data_we1), + .adjustments_address0(tdf5_110_U0_adjustments_address0), + .adjustments_ce0(tdf5_110_U0_adjustments_ce0), + .adjustments_d0(tdf5_110_U0_adjustments_d0), + .adjustments_q0(tdf5_adjustments_q0), + .adjustments_we0(tdf5_110_U0_adjustments_we0), + .adjustments_address1(tdf5_110_U0_adjustments_address1), + .adjustments_ce1(tdf5_110_U0_adjustments_ce1), + .adjustments_d1(tdf5_110_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf5_110_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf5_110_U0_in_data_read), + .out_data_full_n(tdf6_fmaps_i_full_n), + .out_data_write(tdf5_110_U0_out_data_write), + .ap_start(tdf5_110_U0_ap_start), + .ap_done(tdf5_110_U0_ap_done), + .ap_ready(tdf5_110_U0_ap_ready), + .ap_idle(tdf5_110_U0_ap_idle), + .ap_continue(tdf5_110_U0_ap_continue) +); + +td_fused_top_tdf6_19 tdf6_19_U0( + .in_data_address0(tdf6_19_U0_in_data_address0), + .in_data_ce0(tdf6_19_U0_in_data_ce0), + .in_data_d0(tdf6_19_U0_in_data_d0), + .in_data_q0(tdf6_fmaps_t_q0), + .in_data_we0(tdf6_19_U0_in_data_we0), + .in_data_address1(tdf6_19_U0_in_data_address1), + .in_data_ce1(tdf6_19_U0_in_data_ce1), + .in_data_d1(tdf6_19_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf6_19_U0_in_data_we1), + .out_data_address0(tdf6_19_U0_out_data_address0), + .out_data_ce0(tdf6_19_U0_out_data_ce0), + .out_data_d0(tdf6_19_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf6_19_U0_out_data_we0), + .out_data_address1(tdf6_19_U0_out_data_address1), + .out_data_ce1(tdf6_19_U0_out_data_ce1), + .out_data_d1(tdf6_19_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf6_19_U0_out_data_we1), + .filter_data_address0(tdf6_19_U0_filter_data_address0), + .filter_data_ce0(tdf6_19_U0_filter_data_ce0), + .filter_data_d0(tdf6_19_U0_filter_data_d0), + .filter_data_q0(tdf6_filters_q0), + .filter_data_we0(tdf6_19_U0_filter_data_we0), + .filter_data_address1(tdf6_19_U0_filter_data_address1), + .filter_data_ce1(tdf6_19_U0_filter_data_ce1), + .filter_data_d1(tdf6_19_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(tdf6_19_U0_filter_data_we1), + .adjustments_address0(tdf6_19_U0_adjustments_address0), + .adjustments_ce0(tdf6_19_U0_adjustments_ce0), + .adjustments_d0(tdf6_19_U0_adjustments_d0), + .adjustments_q0(tdf6_adjustments_q0), + .adjustments_we0(tdf6_19_U0_adjustments_we0), + .adjustments_address1(tdf6_19_U0_adjustments_address1), + .adjustments_ce1(tdf6_19_U0_adjustments_ce1), + .adjustments_d1(tdf6_19_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf6_19_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf6_19_U0_in_data_read), + .out_data_full_n(tdf7_fmaps_i_full_n), + .out_data_write(tdf6_19_U0_out_data_write), + .ap_start(tdf6_19_U0_ap_start), + .ap_done(tdf6_19_U0_ap_done), + .ap_ready(tdf6_19_U0_ap_ready), + .ap_idle(tdf6_19_U0_ap_idle), + .ap_continue(tdf6_19_U0_ap_continue) +); + +td_fused_top_tdf7_18 tdf7_18_U0( + .in_data_address0(tdf7_18_U0_in_data_address0), + .in_data_ce0(tdf7_18_U0_in_data_ce0), + .in_data_d0(tdf7_18_U0_in_data_d0), + .in_data_q0(tdf7_fmaps_t_q0), + .in_data_we0(tdf7_18_U0_in_data_we0), + .in_data_address1(tdf7_18_U0_in_data_address1), + .in_data_ce1(tdf7_18_U0_in_data_ce1), + .in_data_d1(tdf7_18_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf7_18_U0_in_data_we1), + .out_data_address0(tdf7_18_U0_out_data_address0), + .out_data_ce0(tdf7_18_U0_out_data_ce0), + .out_data_d0(tdf7_18_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf7_18_U0_out_data_we0), + .out_data_address1(tdf7_18_U0_out_data_address1), + .out_data_ce1(tdf7_18_U0_out_data_ce1), + .out_data_d1(tdf7_18_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf7_18_U0_out_data_we1), + .l1_filter_data_address0(tdf7_18_U0_l1_filter_data_address0), + .l1_filter_data_ce0(tdf7_18_U0_l1_filter_data_ce0), + .l1_filter_data_d0(tdf7_18_U0_l1_filter_data_d0), + .l1_filter_data_q0(tdf7_filters_q0), + .l1_filter_data_we0(tdf7_18_U0_l1_filter_data_we0), + .l1_filter_data_address1(tdf7_18_U0_l1_filter_data_address1), + .l1_filter_data_ce1(tdf7_18_U0_l1_filter_data_ce1), + .l1_filter_data_d1(tdf7_18_U0_l1_filter_data_d1), + .l1_filter_data_q1(16'd0), + .l1_filter_data_we1(tdf7_18_U0_l1_filter_data_we1), + .l2_filter_data_address0(tdf7_18_U0_l2_filter_data_address0), + .l2_filter_data_ce0(tdf7_18_U0_l2_filter_data_ce0), + .l2_filter_data_d0(tdf7_18_U0_l2_filter_data_d0), + .l2_filter_data_q0(tdf7_l2_filters_q0), + .l2_filter_data_we0(tdf7_18_U0_l2_filter_data_we0), + .l2_filter_data_address1(tdf7_18_U0_l2_filter_data_address1), + .l2_filter_data_ce1(tdf7_18_U0_l2_filter_data_ce1), + .l2_filter_data_d1(tdf7_18_U0_l2_filter_data_d1), + .l2_filter_data_q1(16'd0), + .l2_filter_data_we1(tdf7_18_U0_l2_filter_data_we1), + .l1_adjustments_address0(tdf7_18_U0_l1_adjustments_address0), + .l1_adjustments_ce0(tdf7_18_U0_l1_adjustments_ce0), + .l1_adjustments_d0(tdf7_18_U0_l1_adjustments_d0), + .l1_adjustments_q0(tdf7_adjustments_q0), + .l1_adjustments_we0(tdf7_18_U0_l1_adjustments_we0), + .l1_adjustments_address1(tdf7_18_U0_l1_adjustments_address1), + .l1_adjustments_ce1(tdf7_18_U0_l1_adjustments_ce1), + .l1_adjustments_d1(tdf7_18_U0_l1_adjustments_d1), + .l1_adjustments_q1(48'd0), + .l1_adjustments_we1(tdf7_18_U0_l1_adjustments_we1), + .l2_adjustments_address0(tdf7_18_U0_l2_adjustments_address0), + .l2_adjustments_ce0(tdf7_18_U0_l2_adjustments_ce0), + .l2_adjustments_d0(tdf7_18_U0_l2_adjustments_d0), + .l2_adjustments_q0(tdf7_l2_adjustments_q0), + .l2_adjustments_we0(tdf7_18_U0_l2_adjustments_we0), + .l2_adjustments_address1(tdf7_18_U0_l2_adjustments_address1), + .l2_adjustments_ce1(tdf7_18_U0_l2_adjustments_ce1), + .l2_adjustments_d1(tdf7_18_U0_l2_adjustments_d1), + .l2_adjustments_q1(48'd0), + .l2_adjustments_we1(tdf7_18_U0_l2_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf7_18_U0_in_data_read), + .out_data_full_n(tdf8_fmaps_i_full_n), + .out_data_write(tdf7_18_U0_out_data_write), + .ap_start(tdf7_18_U0_ap_start), + .ap_done(tdf7_18_U0_ap_done), + .ap_ready(tdf7_18_U0_ap_ready), + .ap_idle(tdf7_18_U0_ap_idle), + .ap_continue(tdf7_18_U0_ap_continue) +); + +td_fused_top_tdf8_17 tdf8_17_U0( + .in_data_address0(tdf8_17_U0_in_data_address0), + .in_data_ce0(tdf8_17_U0_in_data_ce0), + .in_data_d0(tdf8_17_U0_in_data_d0), + .in_data_q0(tdf8_fmaps_t_q0), + .in_data_we0(tdf8_17_U0_in_data_we0), + .in_data_address1(tdf8_17_U0_in_data_address1), + .in_data_ce1(tdf8_17_U0_in_data_ce1), + .in_data_d1(tdf8_17_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf8_17_U0_in_data_we1), + .out_data_address0(tdf8_17_U0_out_data_address0), + .out_data_ce0(tdf8_17_U0_out_data_ce0), + .out_data_d0(tdf8_17_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf8_17_U0_out_data_we0), + .out_data_address1(tdf8_17_U0_out_data_address1), + .out_data_ce1(tdf8_17_U0_out_data_ce1), + .out_data_d1(tdf8_17_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf8_17_U0_out_data_we1), + .filter_data_address0(tdf8_17_U0_filter_data_address0), + .filter_data_ce0(tdf8_17_U0_filter_data_ce0), + .filter_data_d0(tdf8_17_U0_filter_data_d0), + .filter_data_q0(tdf8_filters_q0), + .filter_data_we0(tdf8_17_U0_filter_data_we0), + .filter_data_address1(tdf8_17_U0_filter_data_address1), + .filter_data_ce1(tdf8_17_U0_filter_data_ce1), + .filter_data_d1(tdf8_17_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(tdf8_17_U0_filter_data_we1), + .adjustments_address0(tdf8_17_U0_adjustments_address0), + .adjustments_ce0(tdf8_17_U0_adjustments_ce0), + .adjustments_d0(tdf8_17_U0_adjustments_d0), + .adjustments_q0(tdf8_adjustments_q0), + .adjustments_we0(tdf8_17_U0_adjustments_we0), + .adjustments_address1(tdf8_17_U0_adjustments_address1), + .adjustments_ce1(tdf8_17_U0_adjustments_ce1), + .adjustments_d1(tdf8_17_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf8_17_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf8_17_U0_in_data_read), + .out_data_full_n(tdf9_fmaps_i_full_n), + .out_data_write(tdf8_17_U0_out_data_write), + .ap_start(tdf8_17_U0_ap_start), + .ap_done(tdf8_17_U0_ap_done), + .ap_ready(tdf8_17_U0_ap_ready), + .ap_idle(tdf8_17_U0_ap_idle), + .ap_continue(tdf8_17_U0_ap_continue) +); + +td_fused_top_tdf9_16 tdf9_16_U0( + .in_data_address0(tdf9_16_U0_in_data_address0), + .in_data_ce0(tdf9_16_U0_in_data_ce0), + .in_data_d0(tdf9_16_U0_in_data_d0), + .in_data_q0(tdf9_fmaps_t_q0), + .in_data_we0(tdf9_16_U0_in_data_we0), + .in_data_address1(tdf9_16_U0_in_data_address1), + .in_data_ce1(tdf9_16_U0_in_data_ce1), + .in_data_d1(tdf9_16_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf9_16_U0_in_data_we1), + .out_data_address0(tdf9_16_U0_out_data_address0), + .out_data_ce0(tdf9_16_U0_out_data_ce0), + .out_data_d0(tdf9_16_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf9_16_U0_out_data_we0), + .out_data_address1(tdf9_16_U0_out_data_address1), + .out_data_ce1(tdf9_16_U0_out_data_ce1), + .out_data_d1(tdf9_16_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf9_16_U0_out_data_we1), + .filter_data_address0(tdf9_16_U0_filter_data_address0), + .filter_data_ce0(tdf9_16_U0_filter_data_ce0), + .filter_data_d0(tdf9_16_U0_filter_data_d0), + .filter_data_q0(tdf9_filters_q0), + .filter_data_we0(tdf9_16_U0_filter_data_we0), + .filter_data_address1(tdf9_16_U0_filter_data_address1), + .filter_data_ce1(tdf9_16_U0_filter_data_ce1), + .filter_data_d1(tdf9_16_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(tdf9_16_U0_filter_data_we1), + .adjustments_address0(tdf9_16_U0_adjustments_address0), + .adjustments_ce0(tdf9_16_U0_adjustments_ce0), + .adjustments_d0(tdf9_16_U0_adjustments_d0), + .adjustments_q0(tdf9_adjustments_q0), + .adjustments_we0(tdf9_16_U0_adjustments_we0), + .adjustments_address1(tdf9_16_U0_adjustments_address1), + .adjustments_ce1(tdf9_16_U0_adjustments_ce1), + .adjustments_d1(tdf9_16_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf9_16_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf9_16_U0_in_data_read), + .out_data_full_n(tdf10_fmaps_i_full_n), + .out_data_write(tdf9_16_U0_out_data_write), + .ap_start(tdf9_16_U0_ap_start), + .ap_done(tdf9_16_U0_ap_done), + .ap_ready(tdf9_16_U0_ap_ready), + .ap_idle(tdf9_16_U0_ap_idle), + .ap_continue(tdf9_16_U0_ap_continue) +); + +td_fused_top_tdf10_15 tdf10_15_U0( + .in_data_address0(tdf10_15_U0_in_data_address0), + .in_data_ce0(tdf10_15_U0_in_data_ce0), + .in_data_d0(tdf10_15_U0_in_data_d0), + .in_data_q0(tdf10_fmaps_t_q0), + .in_data_we0(tdf10_15_U0_in_data_we0), + .in_data_address1(tdf10_15_U0_in_data_address1), + .in_data_ce1(tdf10_15_U0_in_data_ce1), + .in_data_d1(tdf10_15_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf10_15_U0_in_data_we1), + .out_data_address0(tdf10_15_U0_out_data_address0), + .out_data_ce0(tdf10_15_U0_out_data_ce0), + .out_data_d0(tdf10_15_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf10_15_U0_out_data_we0), + .out_data_address1(tdf10_15_U0_out_data_address1), + .out_data_ce1(tdf10_15_U0_out_data_ce1), + .out_data_d1(tdf10_15_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf10_15_U0_out_data_we1), + .l1_filter_data_address0(tdf10_15_U0_l1_filter_data_address0), + .l1_filter_data_ce0(tdf10_15_U0_l1_filter_data_ce0), + .l1_filter_data_d0(tdf10_15_U0_l1_filter_data_d0), + .l1_filter_data_q0(tdf10_filters_q0), + .l1_filter_data_we0(tdf10_15_U0_l1_filter_data_we0), + .l1_filter_data_address1(tdf10_15_U0_l1_filter_data_address1), + .l1_filter_data_ce1(tdf10_15_U0_l1_filter_data_ce1), + .l1_filter_data_d1(tdf10_15_U0_l1_filter_data_d1), + .l1_filter_data_q1(64'd0), + .l1_filter_data_we1(tdf10_15_U0_l1_filter_data_we1), + .l2_filter_data_address0(tdf10_15_U0_l2_filter_data_address0), + .l2_filter_data_ce0(tdf10_15_U0_l2_filter_data_ce0), + .l2_filter_data_d0(tdf10_15_U0_l2_filter_data_d0), + .l2_filter_data_q0(tdf10_l2_filters_q0), + .l2_filter_data_we0(tdf10_15_U0_l2_filter_data_we0), + .l2_filter_data_address1(tdf10_15_U0_l2_filter_data_address1), + .l2_filter_data_ce1(tdf10_15_U0_l2_filter_data_ce1), + .l2_filter_data_d1(tdf10_15_U0_l2_filter_data_d1), + .l2_filter_data_q1(16'd0), + .l2_filter_data_we1(tdf10_15_U0_l2_filter_data_we1), + .l1_adjustments_address0(tdf10_15_U0_l1_adjustments_address0), + .l1_adjustments_ce0(tdf10_15_U0_l1_adjustments_ce0), + .l1_adjustments_d0(tdf10_15_U0_l1_adjustments_d0), + .l1_adjustments_q0(tdf10_adjustments_q0), + .l1_adjustments_we0(tdf10_15_U0_l1_adjustments_we0), + .l1_adjustments_address1(tdf10_15_U0_l1_adjustments_address1), + .l1_adjustments_ce1(tdf10_15_U0_l1_adjustments_ce1), + .l1_adjustments_d1(tdf10_15_U0_l1_adjustments_d1), + .l1_adjustments_q1(48'd0), + .l1_adjustments_we1(tdf10_15_U0_l1_adjustments_we1), + .l2_adjustments_address0(tdf10_15_U0_l2_adjustments_address0), + .l2_adjustments_ce0(tdf10_15_U0_l2_adjustments_ce0), + .l2_adjustments_d0(tdf10_15_U0_l2_adjustments_d0), + .l2_adjustments_q0(tdf10_l2_adjustments_q0), + .l2_adjustments_we0(tdf10_15_U0_l2_adjustments_we0), + .l2_adjustments_address1(tdf10_15_U0_l2_adjustments_address1), + .l2_adjustments_ce1(tdf10_15_U0_l2_adjustments_ce1), + .l2_adjustments_d1(tdf10_15_U0_l2_adjustments_d1), + .l2_adjustments_q1(48'd0), + .l2_adjustments_we1(tdf10_15_U0_l2_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf10_15_U0_in_data_read), + .out_data_full_n(tdf11_fmaps_i_full_n), + .out_data_write(tdf10_15_U0_out_data_write), + .ap_start(tdf10_15_U0_ap_start), + .ap_done(tdf10_15_U0_ap_done), + .ap_ready(tdf10_15_U0_ap_ready), + .ap_idle(tdf10_15_U0_ap_idle), + .ap_continue(tdf10_15_U0_ap_continue) +); + +td_fused_top_tdf11_14 tdf11_14_U0( + .in_data_address0(tdf11_14_U0_in_data_address0), + .in_data_ce0(tdf11_14_U0_in_data_ce0), + .in_data_d0(tdf11_14_U0_in_data_d0), + .in_data_q0(tdf11_fmaps_t_q0), + .in_data_we0(tdf11_14_U0_in_data_we0), + .in_data_address1(tdf11_14_U0_in_data_address1), + .in_data_ce1(tdf11_14_U0_in_data_ce1), + .in_data_d1(tdf11_14_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf11_14_U0_in_data_we1), + .out_data_address0(tdf11_14_U0_out_data_address0), + .out_data_ce0(tdf11_14_U0_out_data_ce0), + .out_data_d0(tdf11_14_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf11_14_U0_out_data_we0), + .out_data_address1(tdf11_14_U0_out_data_address1), + .out_data_ce1(tdf11_14_U0_out_data_ce1), + .out_data_d1(tdf11_14_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf11_14_U0_out_data_we1), + .l1_filter_data_address0(tdf11_14_U0_l1_filter_data_address0), + .l1_filter_data_ce0(tdf11_14_U0_l1_filter_data_ce0), + .l1_filter_data_d0(tdf11_14_U0_l1_filter_data_d0), + .l1_filter_data_q0(tdf11_filters_q0), + .l1_filter_data_we0(tdf11_14_U0_l1_filter_data_we0), + .l1_filter_data_address1(tdf11_14_U0_l1_filter_data_address1), + .l1_filter_data_ce1(tdf11_14_U0_l1_filter_data_ce1), + .l1_filter_data_d1(tdf11_14_U0_l1_filter_data_d1), + .l1_filter_data_q1(64'd0), + .l1_filter_data_we1(tdf11_14_U0_l1_filter_data_we1), + .l2_filter_data_address0(tdf11_14_U0_l2_filter_data_address0), + .l2_filter_data_ce0(tdf11_14_U0_l2_filter_data_ce0), + .l2_filter_data_d0(tdf11_14_U0_l2_filter_data_d0), + .l2_filter_data_q0(tdf11_l2_filters_q0), + .l2_filter_data_we0(tdf11_14_U0_l2_filter_data_we0), + .l2_filter_data_address1(tdf11_14_U0_l2_filter_data_address1), + .l2_filter_data_ce1(tdf11_14_U0_l2_filter_data_ce1), + .l2_filter_data_d1(tdf11_14_U0_l2_filter_data_d1), + .l2_filter_data_q1(16'd0), + .l2_filter_data_we1(tdf11_14_U0_l2_filter_data_we1), + .l1_adjustments_address0(tdf11_14_U0_l1_adjustments_address0), + .l1_adjustments_ce0(tdf11_14_U0_l1_adjustments_ce0), + .l1_adjustments_d0(tdf11_14_U0_l1_adjustments_d0), + .l1_adjustments_q0(tdf11_adjustments_q0), + .l1_adjustments_we0(tdf11_14_U0_l1_adjustments_we0), + .l1_adjustments_address1(tdf11_14_U0_l1_adjustments_address1), + .l1_adjustments_ce1(tdf11_14_U0_l1_adjustments_ce1), + .l1_adjustments_d1(tdf11_14_U0_l1_adjustments_d1), + .l1_adjustments_q1(48'd0), + .l1_adjustments_we1(tdf11_14_U0_l1_adjustments_we1), + .l2_adjustments_address0(tdf11_14_U0_l2_adjustments_address0), + .l2_adjustments_ce0(tdf11_14_U0_l2_adjustments_ce0), + .l2_adjustments_d0(tdf11_14_U0_l2_adjustments_d0), + .l2_adjustments_q0(tdf11_l2_adjustments_q0), + .l2_adjustments_we0(tdf11_14_U0_l2_adjustments_we0), + .l2_adjustments_address1(tdf11_14_U0_l2_adjustments_address1), + .l2_adjustments_ce1(tdf11_14_U0_l2_adjustments_ce1), + .l2_adjustments_d1(tdf11_14_U0_l2_adjustments_d1), + .l2_adjustments_q1(48'd0), + .l2_adjustments_we1(tdf11_14_U0_l2_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf11_14_U0_in_data_read), + .out_data_full_n(tdf12_fmaps_i_full_n), + .out_data_write(tdf11_14_U0_out_data_write), + .ap_start(tdf11_14_U0_ap_start), + .ap_done(tdf11_14_U0_ap_done), + .ap_ready(tdf11_14_U0_ap_ready), + .ap_idle(tdf11_14_U0_ap_idle), + .ap_continue(tdf11_14_U0_ap_continue) +); + +td_fused_top_tdf12_13 tdf12_13_U0( + .in_data_address0(tdf12_13_U0_in_data_address0), + .in_data_ce0(tdf12_13_U0_in_data_ce0), + .in_data_d0(tdf12_13_U0_in_data_d0), + .in_data_q0(tdf12_fmaps_t_q0), + .in_data_we0(tdf12_13_U0_in_data_we0), + .in_data_address1(tdf12_13_U0_in_data_address1), + .in_data_ce1(tdf12_13_U0_in_data_ce1), + .in_data_d1(tdf12_13_U0_in_data_d1), + .in_data_q1(64'd0), + .in_data_we1(tdf12_13_U0_in_data_we1), + .out_data_address0(tdf12_13_U0_out_data_address0), + .out_data_ce0(tdf12_13_U0_out_data_ce0), + .out_data_d0(tdf12_13_U0_out_data_d0), + .out_data_q0(64'd0), + .out_data_we0(tdf12_13_U0_out_data_we0), + .out_data_address1(tdf12_13_U0_out_data_address1), + .out_data_ce1(tdf12_13_U0_out_data_ce1), + .out_data_d1(tdf12_13_U0_out_data_d1), + .out_data_q1(64'd0), + .out_data_we1(tdf12_13_U0_out_data_we1), + .filter_data_address0(tdf12_13_U0_filter_data_address0), + .filter_data_ce0(tdf12_13_U0_filter_data_ce0), + .filter_data_d0(tdf12_13_U0_filter_data_d0), + .filter_data_q0(tdf12_filters_q0), + .filter_data_we0(tdf12_13_U0_filter_data_we0), + .filter_data_address1(tdf12_13_U0_filter_data_address1), + .filter_data_ce1(tdf12_13_U0_filter_data_ce1), + .filter_data_d1(tdf12_13_U0_filter_data_d1), + .filter_data_q1(16'd0), + .filter_data_we1(tdf12_13_U0_filter_data_we1), + .adjustments_address0(tdf12_13_U0_adjustments_address0), + .adjustments_ce0(tdf12_13_U0_adjustments_ce0), + .adjustments_d0(tdf12_13_U0_adjustments_d0), + .adjustments_q0(tdf12_adjustments_q0), + .adjustments_we0(tdf12_13_U0_adjustments_we0), + .adjustments_address1(tdf12_13_U0_adjustments_address1), + .adjustments_ce1(tdf12_13_U0_adjustments_ce1), + .adjustments_d1(tdf12_13_U0_adjustments_d1), + .adjustments_q1(48'd0), + .adjustments_we1(tdf12_13_U0_adjustments_we1), + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .in_data_empty_n(1'b0), + .in_data_read(tdf12_13_U0_in_data_read), + .out_data_full_n(final_fmaps_i_full_n), + .out_data_write(tdf12_13_U0_out_data_write), + .ap_start(tdf12_13_U0_ap_start), + .ap_done(tdf12_13_U0_ap_done), + .ap_ready(tdf12_13_U0_ap_ready), + .ap_idle(tdf12_13_U0_ap_idle), + .ap_continue(tdf12_13_U0_ap_continue) +); + +td_fused_top_td_fused_axi_out td_fused_axi_out_U0( + .ap_clk(ap_clk), + .ap_rst(ap_rst), + .ap_start(td_fused_axi_out_U0_ap_start), + .ap_done(td_fused_axi_out_U0_ap_done), + .ap_continue(td_fused_axi_out_U0_ap_continue), + .ap_idle(td_fused_axi_out_U0_ap_idle), + .ap_ready(td_fused_axi_out_U0_ap_ready), + .fmaps_address0(td_fused_axi_out_U0_fmaps_address0), + .fmaps_ce0(td_fused_axi_out_U0_fmaps_ce0), + .fmaps_q0(final_fmaps_t_q0), + .stream_out_TDATA(td_fused_axi_out_U0_stream_out_TDATA), + .stream_out_TVALID(td_fused_axi_out_U0_stream_out_TVALID), + .stream_out_TREADY(stream_out_TREADY), + .stream_out_TKEEP(td_fused_axi_out_U0_stream_out_TKEEP), + .stream_out_TSTRB(td_fused_axi_out_U0_stream_out_TSTRB), + .stream_out_TLAST(td_fused_axi_out_U0_stream_out_TLAST) +); + +assign ap_channel_done_final_fmaps = tdf12_13_U0_ap_done; + +assign ap_channel_done_tdf10_fmaps = tdf9_16_U0_ap_done; + +assign ap_channel_done_tdf11_fmaps = tdf10_15_U0_ap_done; + +assign ap_channel_done_tdf12_fmaps = tdf11_14_U0_ap_done; + +assign ap_channel_done_tdf1_fmaps = td_fused_axi_in_U0_ap_done; + +assign ap_channel_done_tdf2_fmaps = tdf1_114_U0_ap_done; + +assign ap_channel_done_tdf3_fmaps = tdf2_113_U0_ap_done; + +assign ap_channel_done_tdf4_fmaps = tdf3_112_U0_ap_done; + +assign ap_channel_done_tdf5_fmaps = tdf4_111_U0_ap_done; + +assign ap_channel_done_tdf6_fmaps = tdf5_110_U0_ap_done; + +assign ap_channel_done_tdf7_fmaps = tdf6_19_U0_ap_done; + +assign ap_channel_done_tdf8_fmaps = tdf7_18_U0_ap_done; + +assign ap_channel_done_tdf9_fmaps = tdf8_17_U0_ap_done; + +assign ap_done = td_fused_axi_out_U0_ap_done; + +assign ap_idle = (tdf9_16_U0_ap_idle & tdf8_17_U0_ap_idle & tdf7_18_U0_ap_idle & tdf6_19_U0_ap_idle & tdf5_110_U0_ap_idle & tdf4_111_U0_ap_idle & tdf3_112_U0_ap_idle & tdf2_113_U0_ap_idle & tdf1_114_U0_ap_idle & tdf12_13_U0_ap_idle & tdf11_14_U0_ap_idle & tdf10_15_U0_ap_idle & td_fused_axi_out_U0_ap_idle & td_fused_axi_in_U0_ap_idle & (final_fmaps_t_empty_n ^ 1'b1) & (tdf12_fmaps_t_empty_n ^ 1'b1) & (tdf11_fmaps_t_empty_n ^ 1'b1) & (tdf10_fmaps_t_empty_n ^ 1'b1) & (tdf9_fmaps_t_empty_n ^ 1'b1) & (tdf8_fmaps_t_empty_n ^ 1'b1) & (tdf7_fmaps_t_empty_n ^ 1'b1) & (tdf6_fmaps_t_empty_n ^ 1'b1) & (tdf5_fmaps_t_empty_n ^ 1'b1) & (tdf4_fmaps_t_empty_n ^ 1'b1) & (tdf3_fmaps_t_empty_n ^ 1'b1) & (tdf2_fmaps_t_empty_n ^ 1'b1) & (tdf1_fmaps_t_empty_n ^ 1'b1)); + +assign ap_ready = td_fused_axi_in_U0_ap_ready; + +assign ap_sync_continue = ap_continue; + +assign ap_sync_done = td_fused_axi_out_U0_ap_done; + +assign ap_sync_ready = td_fused_axi_in_U0_ap_ready; + +assign final_fmaps_t_d0 = 64'd0; + +assign final_fmaps_t_we0 = 1'b0; + +assign stream_in_TREADY = td_fused_axi_in_U0_stream_in_TREADY; + +assign stream_out_TDATA = td_fused_axi_out_U0_stream_out_TDATA; + +assign stream_out_TKEEP = td_fused_axi_out_U0_stream_out_TKEEP; + +assign stream_out_TLAST = td_fused_axi_out_U0_stream_out_TLAST; + +assign stream_out_TSTRB = td_fused_axi_out_U0_stream_out_TSTRB; + +assign stream_out_TVALID = td_fused_axi_out_U0_stream_out_TVALID; + +assign td_fused_axi_in_U0_ap_continue = tdf1_fmaps_i_full_n; + +assign td_fused_axi_in_U0_ap_start = ap_start; + +assign td_fused_axi_in_U0_fmaps_full_n = tdf1_fmaps_i_full_n; + +assign td_fused_axi_in_U0_start_full_n = 1'b1; + +assign td_fused_axi_in_U0_start_write = 1'b0; + +assign td_fused_axi_out_U0_ap_continue = ap_continue; + +assign td_fused_axi_out_U0_ap_start = final_fmaps_t_empty_n; + +assign td_fused_axi_out_U0_start_full_n = 1'b1; + +assign td_fused_axi_out_U0_start_write = 1'b0; + +assign tdf10_15_U0_ap_continue = tdf10_15_U0_out_data_full_n; + +assign tdf10_15_U0_ap_start = tdf10_fmaps_t_empty_n; + +assign tdf10_15_U0_out_data_full_n = tdf11_fmaps_i_full_n; + +assign tdf10_15_U0_start_full_n = 1'b1; + +assign tdf10_15_U0_start_write = 1'b0; + +assign tdf10_adjustments_address0 = tdf10_15_U0_l1_adjustments_address0; + +assign tdf10_adjustments_address1 = 9'd0; + +assign tdf10_adjustments_ce0 = tdf10_15_U0_l1_adjustments_ce0; + +assign tdf10_adjustments_ce1 = 1'b0; + +assign tdf10_adjustments_d0 = 48'd0; + +assign tdf10_adjustments_d1 = 48'd0; + +assign tdf10_adjustments_we0 = 1'b0; + +assign tdf10_adjustments_we1 = 1'b0; + +assign tdf10_filters_address0 = tdf10_15_U0_l1_filter_data_address0; + +assign tdf10_filters_address1 = 17'd0; + +assign tdf10_filters_ce0 = tdf10_15_U0_l1_filter_data_ce0; + +assign tdf10_filters_ce1 = 1'b0; + +assign tdf10_filters_d0 = 64'd0; + +assign tdf10_filters_d1 = 64'd0; + +assign tdf10_filters_we0 = 1'b0; + +assign tdf10_filters_we1 = 1'b0; + +assign tdf10_fmaps_t_d0 = 64'd0; + +assign tdf10_fmaps_t_we0 = 1'b0; + +assign tdf10_l2_adjustments_address0 = tdf10_15_U0_l2_adjustments_address0; + +assign tdf10_l2_adjustments_address1 = 6'd0; + +assign tdf10_l2_adjustments_ce0 = tdf10_15_U0_l2_adjustments_ce0; + +assign tdf10_l2_adjustments_ce1 = 1'b0; + +assign tdf10_l2_adjustments_d0 = 48'd0; + +assign tdf10_l2_adjustments_d1 = 48'd0; + +assign tdf10_l2_adjustments_we0 = 1'b0; + +assign tdf10_l2_adjustments_we1 = 1'b0; + +assign tdf10_l2_filters_address0 = tdf10_15_U0_l2_filter_data_address0; + +assign tdf10_l2_filters_address1 = 15'd0; + +assign tdf10_l2_filters_ce0 = tdf10_15_U0_l2_filter_data_ce0; + +assign tdf10_l2_filters_ce1 = 1'b0; + +assign tdf10_l2_filters_d0 = 16'd0; + +assign tdf10_l2_filters_d1 = 16'd0; + +assign tdf10_l2_filters_we0 = 1'b0; + +assign tdf10_l2_filters_we1 = 1'b0; + +assign tdf11_14_U0_ap_continue = tdf11_14_U0_out_data_full_n; + +assign tdf11_14_U0_ap_start = tdf11_fmaps_t_empty_n; + +assign tdf11_14_U0_out_data_full_n = tdf12_fmaps_i_full_n; + +assign tdf11_14_U0_start_full_n = 1'b1; + +assign tdf11_14_U0_start_write = 1'b0; + +assign tdf11_adjustments_address0 = tdf11_14_U0_l1_adjustments_address0; + +assign tdf11_adjustments_address1 = 9'd0; + +assign tdf11_adjustments_ce0 = tdf11_14_U0_l1_adjustments_ce0; + +assign tdf11_adjustments_ce1 = 1'b0; + +assign tdf11_adjustments_d0 = 48'd0; + +assign tdf11_adjustments_d1 = 48'd0; + +assign tdf11_adjustments_we0 = 1'b0; + +assign tdf11_adjustments_we1 = 1'b0; + +assign tdf11_filters_address0 = tdf11_14_U0_l1_filter_data_address0; + +assign tdf11_filters_address1 = 17'd0; + +assign tdf11_filters_ce0 = tdf11_14_U0_l1_filter_data_ce0; + +assign tdf11_filters_ce1 = 1'b0; + +assign tdf11_filters_d0 = 64'd0; + +assign tdf11_filters_d1 = 64'd0; + +assign tdf11_filters_we0 = 1'b0; + +assign tdf11_filters_we1 = 1'b0; + +assign tdf11_fmaps_t_d0 = 64'd0; + +assign tdf11_fmaps_t_we0 = 1'b0; + +assign tdf11_l2_adjustments_address0 = tdf11_14_U0_l2_adjustments_address0; + +assign tdf11_l2_adjustments_address1 = 7'd0; + +assign tdf11_l2_adjustments_ce0 = tdf11_14_U0_l2_adjustments_ce0; + +assign tdf11_l2_adjustments_ce1 = 1'b0; + +assign tdf11_l2_adjustments_d0 = 48'd0; + +assign tdf11_l2_adjustments_d1 = 48'd0; + +assign tdf11_l2_adjustments_we0 = 1'b0; + +assign tdf11_l2_adjustments_we1 = 1'b0; + +assign tdf11_l2_filters_address0 = tdf11_14_U0_l2_filter_data_address0; + +assign tdf11_l2_filters_address1 = 16'd0; + +assign tdf11_l2_filters_ce0 = tdf11_14_U0_l2_filter_data_ce0; + +assign tdf11_l2_filters_ce1 = 1'b0; + +assign tdf11_l2_filters_d0 = 16'd0; + +assign tdf11_l2_filters_d1 = 16'd0; + +assign tdf11_l2_filters_we0 = 1'b0; + +assign tdf11_l2_filters_we1 = 1'b0; + +assign tdf12_13_U0_ap_continue = tdf12_13_U0_out_data_full_n; + +assign tdf12_13_U0_ap_start = tdf12_fmaps_t_empty_n; + +assign tdf12_13_U0_out_data_full_n = final_fmaps_i_full_n; + +assign tdf12_13_U0_start_full_n = 1'b1; + +assign tdf12_13_U0_start_write = 1'b0; + +assign tdf12_adjustments_address0 = tdf12_13_U0_adjustments_address0; + +assign tdf12_adjustments_address1 = 10'd0; + +assign tdf12_adjustments_ce0 = tdf12_13_U0_adjustments_ce0; + +assign tdf12_adjustments_ce1 = 1'b0; + +assign tdf12_adjustments_d0 = 48'd0; + +assign tdf12_adjustments_d1 = 48'd0; + +assign tdf12_adjustments_we0 = 1'b0; + +assign tdf12_adjustments_we1 = 1'b0; + +assign tdf12_filters_address0 = tdf12_13_U0_filter_data_address0; + +assign tdf12_filters_address1 = 17'd0; + +assign tdf12_filters_ce0 = tdf12_13_U0_filter_data_ce0; + +assign tdf12_filters_ce1 = 1'b0; + +assign tdf12_filters_d0 = 16'd0; + +assign tdf12_filters_d1 = 16'd0; + +assign tdf12_filters_we0 = 1'b0; + +assign tdf12_filters_we1 = 1'b0; + +assign tdf12_fmaps_t_d0 = 64'd0; + +assign tdf12_fmaps_t_we0 = 1'b0; + +assign tdf1_114_U0_ap_continue = tdf1_114_U0_out_data_full_n; + +assign tdf1_114_U0_ap_start = tdf1_fmaps_t_empty_n; + +assign tdf1_114_U0_out_data_full_n = tdf2_fmaps_i_full_n; + +assign tdf1_114_U0_start_full_n = 1'b1; + +assign tdf1_114_U0_start_write = 1'b0; + +assign tdf1_adjustments_address0 = tdf1_114_U0_adjustments_address0; + +assign tdf1_adjustments_address1 = 4'd0; + +assign tdf1_adjustments_ce0 = tdf1_114_U0_adjustments_ce0; + +assign tdf1_adjustments_ce1 = 1'b0; + +assign tdf1_adjustments_d0 = 48'd0; + +assign tdf1_adjustments_d1 = 48'd0; + +assign tdf1_adjustments_we0 = 1'b0; + +assign tdf1_adjustments_we1 = 1'b0; + +assign tdf1_filters_address0 = tdf1_114_U0_filter_data_address0; + +assign tdf1_filters_address1 = 9'd0; + +assign tdf1_filters_ce0 = tdf1_114_U0_filter_data_ce0; + +assign tdf1_filters_ce1 = 1'b0; + +assign tdf1_filters_d0 = 16'd0; + +assign tdf1_filters_d1 = 16'd0; + +assign tdf1_filters_we0 = 1'b0; + +assign tdf1_filters_we1 = 1'b0; + +assign tdf1_fmaps_t_d0 = 64'd0; + +assign tdf1_fmaps_t_we0 = 1'b0; + +assign tdf2_113_U0_ap_continue = tdf2_113_U0_out_data_full_n; + +assign tdf2_113_U0_ap_start = tdf2_fmaps_t_empty_n; + +assign tdf2_113_U0_out_data_full_n = tdf3_fmaps_i_full_n; + +assign tdf2_113_U0_start_full_n = 1'b1; + +assign tdf2_113_U0_start_write = 1'b0; + +assign tdf2_adjustments_address0 = tdf2_113_U0_adjustments_address0; + +assign tdf2_adjustments_address1 = 5'd0; + +assign tdf2_adjustments_ce0 = tdf2_113_U0_adjustments_ce0; + +assign tdf2_adjustments_ce1 = 1'b0; + +assign tdf2_adjustments_d0 = 48'd0; + +assign tdf2_adjustments_d1 = 48'd0; + +assign tdf2_adjustments_we0 = 1'b0; + +assign tdf2_adjustments_we1 = 1'b0; + +assign tdf2_filters_address0 = tdf2_113_U0_filter_data_address0; + +assign tdf2_filters_address1 = 13'd0; + +assign tdf2_filters_ce0 = tdf2_113_U0_filter_data_ce0; + +assign tdf2_filters_ce1 = 1'b0; + +assign tdf2_filters_d0 = 16'd0; + +assign tdf2_filters_d1 = 16'd0; + +assign tdf2_filters_we0 = 1'b0; + +assign tdf2_filters_we1 = 1'b0; + +assign tdf2_fmaps_t_d0 = 64'd0; + +assign tdf2_fmaps_t_we0 = 1'b0; + +assign tdf3_112_U0_ap_continue = tdf3_112_U0_out_data_full_n; + +assign tdf3_112_U0_ap_start = tdf3_fmaps_t_empty_n; + +assign tdf3_112_U0_out_data_full_n = tdf4_fmaps_i_full_n; + +assign tdf3_112_U0_start_full_n = 1'b1; + +assign tdf3_112_U0_start_write = 1'b0; + +assign tdf3_adjustments_address0 = tdf3_112_U0_adjustments_address0; + +assign tdf3_adjustments_address1 = 4'd0; + +assign tdf3_adjustments_ce0 = tdf3_112_U0_adjustments_ce0; + +assign tdf3_adjustments_ce1 = 1'b0; + +assign tdf3_adjustments_d0 = 48'd0; + +assign tdf3_adjustments_d1 = 48'd0; + +assign tdf3_adjustments_we0 = 1'b0; + +assign tdf3_adjustments_we1 = 1'b0; + +assign tdf3_filters_address0 = tdf3_112_U0_filter_data_address0; + +assign tdf3_filters_address1 = 9'd0; + +assign tdf3_filters_ce0 = tdf3_112_U0_filter_data_ce0; + +assign tdf3_filters_ce1 = 1'b0; + +assign tdf3_filters_d0 = 16'd0; + +assign tdf3_filters_d1 = 16'd0; + +assign tdf3_filters_we0 = 1'b0; + +assign tdf3_filters_we1 = 1'b0; + +assign tdf3_fmaps_t_d0 = 64'd0; + +assign tdf3_fmaps_t_we0 = 1'b0; + +assign tdf4_111_U0_ap_continue = tdf4_111_U0_out_data_full_n; + +assign tdf4_111_U0_ap_start = tdf4_fmaps_t_empty_n; + +assign tdf4_111_U0_out_data_full_n = tdf5_fmaps_i_full_n; + +assign tdf4_111_U0_start_full_n = 1'b1; + +assign tdf4_111_U0_start_write = 1'b0; + +assign tdf4_adjustments_address0 = tdf4_111_U0_l1_adjustments_address0; + +assign tdf4_adjustments_address1 = 7'd0; + +assign tdf4_adjustments_ce0 = tdf4_111_U0_l1_adjustments_ce0; + +assign tdf4_adjustments_ce1 = 1'b0; + +assign tdf4_adjustments_d0 = 48'd0; + +assign tdf4_adjustments_d1 = 48'd0; + +assign tdf4_adjustments_we0 = 1'b0; + +assign tdf4_adjustments_we1 = 1'b0; + +assign tdf4_filters_address0 = tdf4_111_U0_l1_filter_data_address0; + +assign tdf4_filters_address1 = 15'd0; + +assign tdf4_filters_ce0 = tdf4_111_U0_l1_filter_data_ce0; + +assign tdf4_filters_ce1 = 1'b0; + +assign tdf4_filters_d0 = 16'd0; + +assign tdf4_filters_d1 = 16'd0; + +assign tdf4_filters_we0 = 1'b0; + +assign tdf4_filters_we1 = 1'b0; + +assign tdf4_fmaps_t_d0 = 64'd0; + +assign tdf4_fmaps_t_we0 = 1'b0; + +assign tdf4_l2_adjustments_address0 = tdf4_111_U0_l2_adjustments_address0; + +assign tdf4_l2_adjustments_address1 = 4'd0; + +assign tdf4_l2_adjustments_ce0 = tdf4_111_U0_l2_adjustments_ce0; + +assign tdf4_l2_adjustments_ce1 = 1'b0; + +assign tdf4_l2_adjustments_d0 = 48'd0; + +assign tdf4_l2_adjustments_d1 = 48'd0; + +assign tdf4_l2_adjustments_we0 = 1'b0; + +assign tdf4_l2_adjustments_we1 = 1'b0; + +assign tdf4_l2_filters_address0 = tdf4_111_U0_l2_filter_data_address0; + +assign tdf4_l2_filters_address1 = 11'd0; + +assign tdf4_l2_filters_ce0 = tdf4_111_U0_l2_filter_data_ce0; + +assign tdf4_l2_filters_ce1 = 1'b0; + +assign tdf4_l2_filters_d0 = 16'd0; + +assign tdf4_l2_filters_d1 = 16'd0; + +assign tdf4_l2_filters_we0 = 1'b0; + +assign tdf4_l2_filters_we1 = 1'b0; + +assign tdf5_110_U0_ap_continue = tdf5_110_U0_out_data_full_n; + +assign tdf5_110_U0_ap_start = tdf5_fmaps_t_empty_n; + +assign tdf5_110_U0_out_data_full_n = tdf6_fmaps_i_full_n; + +assign tdf5_110_U0_start_full_n = 1'b1; + +assign tdf5_110_U0_start_write = 1'b0; + +assign tdf5_adjustments_address0 = tdf5_110_U0_adjustments_address0; + +assign tdf5_adjustments_address1 = 7'd0; + +assign tdf5_adjustments_ce0 = tdf5_110_U0_adjustments_ce0; + +assign tdf5_adjustments_ce1 = 1'b0; + +assign tdf5_adjustments_d0 = 48'd0; + +assign tdf5_adjustments_d1 = 48'd0; + +assign tdf5_adjustments_we0 = 1'b0; + +assign tdf5_adjustments_we1 = 1'b0; + +assign tdf5_filters_address0 = tdf5_110_U0_filter_data_address0; + +assign tdf5_filters_address1 = 15'd0; + +assign tdf5_filters_ce0 = tdf5_110_U0_filter_data_ce0; + +assign tdf5_filters_ce1 = 1'b0; + +assign tdf5_filters_d0 = 16'd0; + +assign tdf5_filters_d1 = 16'd0; + +assign tdf5_filters_we0 = 1'b0; + +assign tdf5_filters_we1 = 1'b0; + +assign tdf5_fmaps_t_d0 = 64'd0; + +assign tdf5_fmaps_t_we0 = 1'b0; + +assign tdf6_19_U0_ap_continue = tdf6_19_U0_out_data_full_n; + +assign tdf6_19_U0_ap_start = tdf6_fmaps_t_empty_n; + +assign tdf6_19_U0_out_data_full_n = tdf7_fmaps_i_full_n; + +assign tdf6_19_U0_start_full_n = 1'b1; + +assign tdf6_19_U0_start_write = 1'b0; + +assign tdf6_adjustments_address0 = tdf6_19_U0_adjustments_address0; + +assign tdf6_adjustments_address1 = 5'd0; + +assign tdf6_adjustments_ce0 = tdf6_19_U0_adjustments_ce0; + +assign tdf6_adjustments_ce1 = 1'b0; + +assign tdf6_adjustments_d0 = 48'd0; + +assign tdf6_adjustments_d1 = 48'd0; + +assign tdf6_adjustments_we0 = 1'b0; + +assign tdf6_adjustments_we1 = 1'b0; + +assign tdf6_filters_address0 = tdf6_19_U0_filter_data_address0; + +assign tdf6_filters_address1 = 12'd0; + +assign tdf6_filters_ce0 = tdf6_19_U0_filter_data_ce0; + +assign tdf6_filters_ce1 = 1'b0; + +assign tdf6_filters_d0 = 16'd0; + +assign tdf6_filters_d1 = 16'd0; + +assign tdf6_filters_we0 = 1'b0; + +assign tdf6_filters_we1 = 1'b0; + +assign tdf6_fmaps_t_d0 = 64'd0; + +assign tdf6_fmaps_t_we0 = 1'b0; + +assign tdf7_18_U0_ap_continue = tdf7_18_U0_out_data_full_n; + +assign tdf7_18_U0_ap_start = tdf7_fmaps_t_empty_n; + +assign tdf7_18_U0_out_data_full_n = tdf8_fmaps_i_full_n; + +assign tdf7_18_U0_start_full_n = 1'b1; + +assign tdf7_18_U0_start_write = 1'b0; + +assign tdf7_adjustments_address0 = tdf7_18_U0_l1_adjustments_address0; + +assign tdf7_adjustments_address1 = 8'd0; + +assign tdf7_adjustments_ce0 = tdf7_18_U0_l1_adjustments_ce0; + +assign tdf7_adjustments_ce1 = 1'b0; + +assign tdf7_adjustments_d0 = 48'd0; + +assign tdf7_adjustments_d1 = 48'd0; + +assign tdf7_adjustments_we0 = 1'b0; + +assign tdf7_adjustments_we1 = 1'b0; + +assign tdf7_filters_address0 = tdf7_18_U0_l1_filter_data_address0; + +assign tdf7_filters_address1 = 17'd0; + +assign tdf7_filters_ce0 = tdf7_18_U0_l1_filter_data_ce0; + +assign tdf7_filters_ce1 = 1'b0; + +assign tdf7_filters_d0 = 16'd0; + +assign tdf7_filters_d1 = 16'd0; + +assign tdf7_filters_we0 = 1'b0; + +assign tdf7_filters_we1 = 1'b0; + +assign tdf7_fmaps_t_d0 = 64'd0; + +assign tdf7_fmaps_t_we0 = 1'b0; + +assign tdf7_l2_adjustments_address0 = tdf7_18_U0_l2_adjustments_address0; + +assign tdf7_l2_adjustments_address1 = 5'd0; + +assign tdf7_l2_adjustments_ce0 = tdf7_18_U0_l2_adjustments_ce0; + +assign tdf7_l2_adjustments_ce1 = 1'b0; + +assign tdf7_l2_adjustments_d0 = 48'd0; + +assign tdf7_l2_adjustments_d1 = 48'd0; + +assign tdf7_l2_adjustments_we0 = 1'b0; + +assign tdf7_l2_adjustments_we1 = 1'b0; + +assign tdf7_l2_filters_address0 = tdf7_18_U0_l2_filter_data_address0; + +assign tdf7_l2_filters_address1 = 13'd0; + +assign tdf7_l2_filters_ce0 = tdf7_18_U0_l2_filter_data_ce0; + +assign tdf7_l2_filters_ce1 = 1'b0; + +assign tdf7_l2_filters_d0 = 16'd0; + +assign tdf7_l2_filters_d1 = 16'd0; + +assign tdf7_l2_filters_we0 = 1'b0; + +assign tdf7_l2_filters_we1 = 1'b0; + +assign tdf8_17_U0_ap_continue = tdf8_17_U0_out_data_full_n; + +assign tdf8_17_U0_ap_start = tdf8_fmaps_t_empty_n; + +assign tdf8_17_U0_out_data_full_n = tdf9_fmaps_i_full_n; + +assign tdf8_17_U0_start_full_n = 1'b1; + +assign tdf8_17_U0_start_write = 1'b0; + +assign tdf8_adjustments_address0 = tdf8_17_U0_adjustments_address0; + +assign tdf8_adjustments_address1 = 8'd0; + +assign tdf8_adjustments_ce0 = tdf8_17_U0_adjustments_ce0; + +assign tdf8_adjustments_ce1 = 1'b0; + +assign tdf8_adjustments_d0 = 48'd0; + +assign tdf8_adjustments_d1 = 48'd0; + +assign tdf8_adjustments_we0 = 1'b0; + +assign tdf8_adjustments_we1 = 1'b0; + +assign tdf8_filters_address0 = tdf8_17_U0_filter_data_address0; + +assign tdf8_filters_address1 = 17'd0; + +assign tdf8_filters_ce0 = tdf8_17_U0_filter_data_ce0; + +assign tdf8_filters_ce1 = 1'b0; + +assign tdf8_filters_d0 = 16'd0; + +assign tdf8_filters_d1 = 16'd0; + +assign tdf8_filters_we0 = 1'b0; + +assign tdf8_filters_we1 = 1'b0; + +assign tdf8_fmaps_t_d0 = 64'd0; + +assign tdf8_fmaps_t_we0 = 1'b0; + +assign tdf9_16_U0_ap_continue = tdf9_16_U0_out_data_full_n; + +assign tdf9_16_U0_ap_start = tdf9_fmaps_t_empty_n; + +assign tdf9_16_U0_out_data_full_n = tdf10_fmaps_i_full_n; + +assign tdf9_16_U0_start_full_n = 1'b1; + +assign tdf9_16_U0_start_write = 1'b0; + +assign tdf9_adjustments_address0 = tdf9_16_U0_adjustments_address0; + +assign tdf9_adjustments_address1 = 6'd0; + +assign tdf9_adjustments_ce0 = tdf9_16_U0_adjustments_ce0; + +assign tdf9_adjustments_ce1 = 1'b0; + +assign tdf9_adjustments_d0 = 48'd0; + +assign tdf9_adjustments_d1 = 48'd0; + +assign tdf9_adjustments_we0 = 1'b0; + +assign tdf9_adjustments_we1 = 1'b0; + +assign tdf9_filters_address0 = tdf9_16_U0_filter_data_address0; + +assign tdf9_filters_address1 = 14'd0; + +assign tdf9_filters_ce0 = tdf9_16_U0_filter_data_ce0; + +assign tdf9_filters_ce1 = 1'b0; + +assign tdf9_filters_d0 = 16'd0; + +assign tdf9_filters_d1 = 16'd0; + +assign tdf9_filters_we0 = 1'b0; + +assign tdf9_filters_we1 = 1'b0; + +assign tdf9_fmaps_t_d0 = 64'd0; + +assign tdf9_fmaps_t_we0 = 1'b0; + +endmodule //td_fused_top_td_fused +// ============================================================== +// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) +// Version: 2020.2 +// Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// +// =========================================================== + +`timescale 1 ns / 1 ps + + + +module td_fused_top ( + ap_clk, + ap_rst_n, + ap_start, + ap_done, + ap_idle, + ap_ready, + stream_in_TDATA, + stream_in_TVALID, + stream_in_TREADY, + stream_in_TKEEP, + stream_in_TSTRB, + stream_in_TLAST, + stream_out_TDATA, + stream_out_TVALID, + stream_out_TREADY, + stream_out_TKEEP, + stream_out_TSTRB, + stream_out_TLAST +); + +parameter ap_ST_fsm_state1 = 5'd1; +parameter ap_ST_fsm_state2 = 5'd2; +parameter ap_ST_fsm_state3 = 5'd4; +parameter ap_ST_fsm_state4 = 5'd8; +parameter ap_ST_fsm_state5 = 5'd16; +parameter ap_const_lv64_0 = 64'd0; + +input ap_clk; +input ap_rst_n; +input ap_start; +output ap_done; +output ap_idle; +output ap_ready; +input [15:0] stream_in_TDATA; +input stream_in_TVALID; +output stream_in_TREADY; +input [1:0] stream_in_TKEEP; +input [1:0] stream_in_TSTRB; +input [0:0] stream_in_TLAST; +output [15:0] stream_out_TDATA; +output stream_out_TVALID; +input stream_out_TREADY; +output [1:0] stream_out_TKEEP; +output [1:0] stream_out_TSTRB; +output [0:0] stream_out_TLAST; + +reg ap_done; +reg ap_idle; +reg ap_ready; + + reg ap_rst_n_inv; + reg [4:0] ap_CS_fsm; +wire ap_CS_fsm_state1; +wire [15:0] tmp_data_fu_1262_p1; +wire [63:0] tmp_fu_1280_p5; +wire [47:0] trunc_ln151_fu_1294_p1; +reg tdf1_filters_ce0; +wire [15:0] tdf1_filters_q0; +wire [8:0] tdf1_filters_address1; +reg tdf1_filters_ce1; +reg tdf1_filters_we1; +reg tdf2_filters_ce0; +wire [15:0] tdf2_filters_q0; +wire [12:0] tdf2_filters_address1; +reg tdf2_filters_ce1; +reg tdf2_filters_we1; +reg tdf3_filters_ce0; +wire [15:0] tdf3_filters_q0; +wire [8:0] tdf3_filters_address1; +reg tdf3_filters_ce1; +reg tdf3_filters_we1; +reg tdf4_filters_ce0; +wire [15:0] tdf4_filters_q0; +wire [14:0] tdf4_filters_address1; +reg tdf4_filters_ce1; +reg tdf4_filters_we1; +reg tdf4_l2_filters_ce0; +wire [15:0] tdf4_l2_filters_q0; +wire [10:0] tdf4_l2_filters_address1; +reg tdf4_l2_filters_ce1; +reg tdf4_l2_filters_we1; +reg tdf5_filters_ce0; +wire [15:0] tdf5_filters_q0; +wire [14:0] tdf5_filters_address1; +reg tdf5_filters_ce1; +reg tdf5_filters_we1; +reg tdf6_filters_ce0; +wire [15:0] tdf6_filters_q0; +wire [11:0] tdf6_filters_address1; +reg tdf6_filters_ce1; +reg tdf6_filters_we1; +reg tdf7_filters_ce0; +wire [15:0] tdf7_filters_q0; +wire [16:0] tdf7_filters_address1; +reg tdf7_filters_ce1; +reg tdf7_filters_we1; +reg tdf7_l2_filters_ce0; +wire [15:0] tdf7_l2_filters_q0; +wire [12:0] tdf7_l2_filters_address1; +reg tdf7_l2_filters_ce1; +reg tdf7_l2_filters_we1; +reg tdf8_filters_ce0; +wire [15:0] tdf8_filters_q0; +wire [16:0] tdf8_filters_address1; +reg tdf8_filters_ce1; +reg tdf8_filters_we1; +reg tdf9_filters_ce0; +wire [15:0] tdf9_filters_q0; +wire [13:0] tdf9_filters_address1; +reg tdf9_filters_ce1; +reg tdf9_filters_we1; +reg tdf10_filters_ce0; +wire [63:0] tdf10_filters_q0; +wire [16:0] tdf10_filters_address1; +reg tdf10_filters_ce1; +reg tdf10_filters_we1; +reg tdf10_l2_filters_ce0; +wire [15:0] tdf10_l2_filters_q0; +wire [14:0] tdf10_l2_filters_address1; +reg tdf10_l2_filters_ce1; +reg tdf10_l2_filters_we1; +reg tdf11_filters_ce0; +wire [63:0] tdf11_filters_q0; +wire [16:0] tdf11_filters_address1; +reg tdf11_filters_ce1; +reg tdf11_filters_we1; +reg tdf11_l2_filters_ce0; +wire [15:0] tdf11_l2_filters_q0; +wire [15:0] tdf11_l2_filters_address1; +reg tdf11_l2_filters_ce1; +reg tdf11_l2_filters_we1; +reg tdf12_filters_ce0; +wire [15:0] tdf12_filters_q0; +wire [16:0] tdf12_filters_address1; +reg tdf12_filters_ce1; +reg tdf12_filters_we1; +reg tdf1_adjustments_ce0; +wire [47:0] tdf1_adjustments_q0; +wire [3:0] tdf1_adjustments_address1; +reg tdf1_adjustments_ce1; +reg tdf1_adjustments_we1; +reg tdf2_adjustments_ce0; +wire [47:0] tdf2_adjustments_q0; +wire [4:0] tdf2_adjustments_address1; +reg tdf2_adjustments_ce1; +reg tdf2_adjustments_we1; +reg tdf3_adjustments_ce0; +wire [47:0] tdf3_adjustments_q0; +wire [3:0] tdf3_adjustments_address1; +reg tdf3_adjustments_ce1; +reg tdf3_adjustments_we1; +reg tdf4_adjustments_ce0; +wire [47:0] tdf4_adjustments_q0; +wire [6:0] tdf4_adjustments_address1; +reg tdf4_adjustments_ce1; +reg tdf4_adjustments_we1; +reg tdf4_l2_adjustments_ce0; +wire [47:0] tdf4_l2_adjustments_q0; +wire [3:0] tdf4_l2_adjustments_address1; +reg tdf4_l2_adjustments_ce1; +reg tdf4_l2_adjustments_we1; +reg tdf5_adjustments_ce0; +wire [47:0] tdf5_adjustments_q0; +wire [6:0] tdf5_adjustments_address1; +reg tdf5_adjustments_ce1; +reg tdf5_adjustments_we1; +reg tdf6_adjustments_ce0; +wire [47:0] tdf6_adjustments_q0; +wire [4:0] tdf6_adjustments_address1; +reg tdf6_adjustments_ce1; +reg tdf6_adjustments_we1; +reg tdf7_adjustments_ce0; +wire [47:0] tdf7_adjustments_q0; +wire [7:0] tdf7_adjustments_address1; +reg tdf7_adjustments_ce1; +reg tdf7_adjustments_we1; +reg tdf7_l2_adjustments_ce0; +wire [47:0] tdf7_l2_adjustments_q0; +wire [4:0] tdf7_l2_adjustments_address1; +reg tdf7_l2_adjustments_ce1; +reg tdf7_l2_adjustments_we1; +reg tdf8_adjustments_ce0; +wire [47:0] tdf8_adjustments_q0; +wire [7:0] tdf8_adjustments_address1; +reg tdf8_adjustments_ce1; +reg tdf8_adjustments_we1; +reg tdf9_adjustments_ce0; +wire [47:0] tdf9_adjustments_q0; +wire [5:0] tdf9_adjustments_address1; +reg tdf9_adjustments_ce1; +reg tdf9_adjustments_we1; +reg tdf10_adjustments_ce0; +wire [47:0] tdf10_adjustments_q0; +wire [8:0] tdf10_adjustments_address1; +reg tdf10_adjustments_ce1; +reg tdf10_adjustments_we1; +reg tdf10_l2_adjustments_ce0; +wire [47:0] tdf10_l2_adjustments_q0; +wire [5:0] tdf10_l2_adjustments_address1; +reg tdf10_l2_adjustments_ce1; +reg tdf10_l2_adjustments_we1; +reg tdf11_adjustments_ce0; +wire [47:0] tdf11_adjustments_q0; +wire [8:0] tdf11_adjustments_address1; +reg tdf11_adjustments_ce1; +reg tdf11_adjustments_we1; +reg tdf11_l2_adjustments_ce0; +wire [47:0] tdf11_l2_adjustments_q0; +wire [6:0] tdf11_l2_adjustments_address1; +reg tdf11_l2_adjustments_ce1; +reg tdf11_l2_adjustments_we1; +reg tdf12_adjustments_ce0; +wire [47:0] tdf12_adjustments_q0; +wire [9:0] tdf12_adjustments_address1; +reg tdf12_adjustments_ce1; +reg tdf12_adjustments_we1; +wire [8:0] grp_td_fused_fu_990_tdf1_filters_address0; +wire grp_td_fused_fu_990_tdf1_filters_ce0; +wire [15:0] grp_td_fused_fu_990_tdf1_filters_d0; +wire grp_td_fused_fu_990_tdf1_filters_we0; +wire [8:0] grp_td_fused_fu_990_tdf1_filters_address1; +wire grp_td_fused_fu_990_tdf1_filters_ce1; +wire [15:0] grp_td_fused_fu_990_tdf1_filters_d1; +wire grp_td_fused_fu_990_tdf1_filters_we1; +wire [12:0] grp_td_fused_fu_990_tdf2_filters_address0; +wire grp_td_fused_fu_990_tdf2_filters_ce0; +wire [15:0] grp_td_fused_fu_990_tdf2_filters_d0; +wire grp_td_fused_fu_990_tdf2_filters_we0; +wire [12:0] grp_td_fused_fu_990_tdf2_filters_address1; +wire grp_td_fused_fu_990_tdf2_filters_ce1; +wire [15:0] grp_td_fused_fu_990_tdf2_filters_d1; +wire grp_td_fused_fu_990_tdf2_filters_we1; +wire [8:0] grp_td_fused_fu_990_tdf3_filters_address0; +wire grp_td_fused_fu_990_tdf3_filters_ce0; +wire [15:0] grp_td_fused_fu_990_tdf3_filters_d0; +wire grp_td_fused_fu_990_tdf3_filters_we0; +wire [8:0] grp_td_fused_fu_990_tdf3_filters_address1; +wire grp_td_fused_fu_990_tdf3_filters_ce1; +wire [15:0] grp_td_fused_fu_990_tdf3_filters_d1; +wire grp_td_fused_fu_990_tdf3_filters_we1; +wire [14:0] grp_td_fused_fu_990_tdf4_filters_address0; +wire grp_td_fused_fu_990_tdf4_filters_ce0; +wire [15:0] grp_td_fused_fu_990_tdf4_filters_d0; +wire grp_td_fused_fu_990_tdf4_filters_we0; +wire [14:0] grp_td_fused_fu_990_tdf4_filters_address1; +wire grp_td_fused_fu_990_tdf4_filters_ce1; +wire [15:0] grp_td_fused_fu_990_tdf4_filters_d1; +wire grp_td_fused_fu_990_tdf4_filters_we1; +wire [10:0] grp_td_fused_fu_990_tdf4_l2_filters_address0; +wire grp_td_fused_fu_990_tdf4_l2_filters_ce0; +wire [15:0] grp_td_fused_fu_990_tdf4_l2_filters_d0; +wire grp_td_fused_fu_990_tdf4_l2_filters_we0; +wire [10:0] grp_td_fused_fu_990_tdf4_l2_filters_address1; +wire grp_td_fused_fu_990_tdf4_l2_filters_ce1; +wire [15:0] grp_td_fused_fu_990_tdf4_l2_filters_d1; +wire grp_td_fused_fu_990_tdf4_l2_filters_we1; +wire [14:0] grp_td_fused_fu_990_tdf5_filters_address0; +wire grp_td_fused_fu_990_tdf5_filters_ce0; +wire [15:0] grp_td_fused_fu_990_tdf5_filters_d0; +wire grp_td_fused_fu_990_tdf5_filters_we0; +wire [14:0] grp_td_fused_fu_990_tdf5_filters_address1; +wire grp_td_fused_fu_990_tdf5_filters_ce1; +wire [15:0] grp_td_fused_fu_990_tdf5_filters_d1; +wire grp_td_fused_fu_990_tdf5_filters_we1; +wire [11:0] grp_td_fused_fu_990_tdf6_filters_address0; +wire grp_td_fused_fu_990_tdf6_filters_ce0; +wire [15:0] grp_td_fused_fu_990_tdf6_filters_d0; +wire grp_td_fused_fu_990_tdf6_filters_we0; +wire [11:0] grp_td_fused_fu_990_tdf6_filters_address1; +wire grp_td_fused_fu_990_tdf6_filters_ce1; +wire [15:0] grp_td_fused_fu_990_tdf6_filters_d1; +wire grp_td_fused_fu_990_tdf6_filters_we1; +wire [16:0] grp_td_fused_fu_990_tdf7_filters_address0; +wire grp_td_fused_fu_990_tdf7_filters_ce0; +wire [15:0] grp_td_fused_fu_990_tdf7_filters_d0; +wire grp_td_fused_fu_990_tdf7_filters_we0; +wire [16:0] grp_td_fused_fu_990_tdf7_filters_address1; +wire grp_td_fused_fu_990_tdf7_filters_ce1; +wire [15:0] grp_td_fused_fu_990_tdf7_filters_d1; +wire grp_td_fused_fu_990_tdf7_filters_we1; +wire [12:0] grp_td_fused_fu_990_tdf7_l2_filters_address0; +wire grp_td_fused_fu_990_tdf7_l2_filters_ce0; +wire [15:0] grp_td_fused_fu_990_tdf7_l2_filters_d0; +wire grp_td_fused_fu_990_tdf7_l2_filters_we0; +wire [12:0] grp_td_fused_fu_990_tdf7_l2_filters_address1; +wire grp_td_fused_fu_990_tdf7_l2_filters_ce1; +wire [15:0] grp_td_fused_fu_990_tdf7_l2_filters_d1; +wire grp_td_fused_fu_990_tdf7_l2_filters_we1; +wire [16:0] grp_td_fused_fu_990_tdf8_filters_address0; +wire grp_td_fused_fu_990_tdf8_filters_ce0; +wire [15:0] grp_td_fused_fu_990_tdf8_filters_d0; +wire grp_td_fused_fu_990_tdf8_filters_we0; +wire [16:0] grp_td_fused_fu_990_tdf8_filters_address1; +wire grp_td_fused_fu_990_tdf8_filters_ce1; +wire [15:0] grp_td_fused_fu_990_tdf8_filters_d1; +wire grp_td_fused_fu_990_tdf8_filters_we1; +wire [13:0] grp_td_fused_fu_990_tdf9_filters_address0; +wire grp_td_fused_fu_990_tdf9_filters_ce0; +wire [15:0] grp_td_fused_fu_990_tdf9_filters_d0; +wire grp_td_fused_fu_990_tdf9_filters_we0; +wire [13:0] grp_td_fused_fu_990_tdf9_filters_address1; +wire grp_td_fused_fu_990_tdf9_filters_ce1; +wire [15:0] grp_td_fused_fu_990_tdf9_filters_d1; +wire grp_td_fused_fu_990_tdf9_filters_we1; +wire [16:0] grp_td_fused_fu_990_tdf10_filters_address0; +wire grp_td_fused_fu_990_tdf10_filters_ce0; +wire [63:0] grp_td_fused_fu_990_tdf10_filters_d0; +wire grp_td_fused_fu_990_tdf10_filters_we0; +wire [16:0] grp_td_fused_fu_990_tdf10_filters_address1; +wire grp_td_fused_fu_990_tdf10_filters_ce1; +wire [63:0] grp_td_fused_fu_990_tdf10_filters_d1; +wire grp_td_fused_fu_990_tdf10_filters_we1; +wire [14:0] grp_td_fused_fu_990_tdf10_l2_filters_address0; +wire grp_td_fused_fu_990_tdf10_l2_filters_ce0; +wire [15:0] grp_td_fused_fu_990_tdf10_l2_filters_d0; +wire grp_td_fused_fu_990_tdf10_l2_filters_we0; +wire [14:0] grp_td_fused_fu_990_tdf10_l2_filters_address1; +wire grp_td_fused_fu_990_tdf10_l2_filters_ce1; +wire [15:0] grp_td_fused_fu_990_tdf10_l2_filters_d1; +wire grp_td_fused_fu_990_tdf10_l2_filters_we1; +wire [16:0] grp_td_fused_fu_990_tdf11_filters_address0; +wire grp_td_fused_fu_990_tdf11_filters_ce0; +wire [63:0] grp_td_fused_fu_990_tdf11_filters_d0; +wire grp_td_fused_fu_990_tdf11_filters_we0; +wire [16:0] grp_td_fused_fu_990_tdf11_filters_address1; +wire grp_td_fused_fu_990_tdf11_filters_ce1; +wire [63:0] grp_td_fused_fu_990_tdf11_filters_d1; +wire grp_td_fused_fu_990_tdf11_filters_we1; +wire [15:0] grp_td_fused_fu_990_tdf11_l2_filters_address0; +wire grp_td_fused_fu_990_tdf11_l2_filters_ce0; +wire [15:0] grp_td_fused_fu_990_tdf11_l2_filters_d0; +wire grp_td_fused_fu_990_tdf11_l2_filters_we0; +wire [15:0] grp_td_fused_fu_990_tdf11_l2_filters_address1; +wire grp_td_fused_fu_990_tdf11_l2_filters_ce1; +wire [15:0] grp_td_fused_fu_990_tdf11_l2_filters_d1; +wire grp_td_fused_fu_990_tdf11_l2_filters_we1; +wire [16:0] grp_td_fused_fu_990_tdf12_filters_address0; +wire grp_td_fused_fu_990_tdf12_filters_ce0; +wire [15:0] grp_td_fused_fu_990_tdf12_filters_d0; +wire grp_td_fused_fu_990_tdf12_filters_we0; +wire [16:0] grp_td_fused_fu_990_tdf12_filters_address1; +wire grp_td_fused_fu_990_tdf12_filters_ce1; +wire [15:0] grp_td_fused_fu_990_tdf12_filters_d1; +wire grp_td_fused_fu_990_tdf12_filters_we1; +wire [3:0] grp_td_fused_fu_990_tdf1_adjustments_address0; +wire grp_td_fused_fu_990_tdf1_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf1_adjustments_d0; +wire grp_td_fused_fu_990_tdf1_adjustments_we0; +wire [3:0] grp_td_fused_fu_990_tdf1_adjustments_address1; +wire grp_td_fused_fu_990_tdf1_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf1_adjustments_d1; +wire grp_td_fused_fu_990_tdf1_adjustments_we1; +wire [4:0] grp_td_fused_fu_990_tdf2_adjustments_address0; +wire grp_td_fused_fu_990_tdf2_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf2_adjustments_d0; +wire grp_td_fused_fu_990_tdf2_adjustments_we0; +wire [4:0] grp_td_fused_fu_990_tdf2_adjustments_address1; +wire grp_td_fused_fu_990_tdf2_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf2_adjustments_d1; +wire grp_td_fused_fu_990_tdf2_adjustments_we1; +wire [3:0] grp_td_fused_fu_990_tdf3_adjustments_address0; +wire grp_td_fused_fu_990_tdf3_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf3_adjustments_d0; +wire grp_td_fused_fu_990_tdf3_adjustments_we0; +wire [3:0] grp_td_fused_fu_990_tdf3_adjustments_address1; +wire grp_td_fused_fu_990_tdf3_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf3_adjustments_d1; +wire grp_td_fused_fu_990_tdf3_adjustments_we1; +wire [6:0] grp_td_fused_fu_990_tdf4_adjustments_address0; +wire grp_td_fused_fu_990_tdf4_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf4_adjustments_d0; +wire grp_td_fused_fu_990_tdf4_adjustments_we0; +wire [6:0] grp_td_fused_fu_990_tdf4_adjustments_address1; +wire grp_td_fused_fu_990_tdf4_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf4_adjustments_d1; +wire grp_td_fused_fu_990_tdf4_adjustments_we1; +wire [3:0] grp_td_fused_fu_990_tdf4_l2_adjustments_address0; +wire grp_td_fused_fu_990_tdf4_l2_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf4_l2_adjustments_d0; +wire grp_td_fused_fu_990_tdf4_l2_adjustments_we0; +wire [3:0] grp_td_fused_fu_990_tdf4_l2_adjustments_address1; +wire grp_td_fused_fu_990_tdf4_l2_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf4_l2_adjustments_d1; +wire grp_td_fused_fu_990_tdf4_l2_adjustments_we1; +wire [6:0] grp_td_fused_fu_990_tdf5_adjustments_address0; +wire grp_td_fused_fu_990_tdf5_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf5_adjustments_d0; +wire grp_td_fused_fu_990_tdf5_adjustments_we0; +wire [6:0] grp_td_fused_fu_990_tdf5_adjustments_address1; +wire grp_td_fused_fu_990_tdf5_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf5_adjustments_d1; +wire grp_td_fused_fu_990_tdf5_adjustments_we1; +wire [4:0] grp_td_fused_fu_990_tdf6_adjustments_address0; +wire grp_td_fused_fu_990_tdf6_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf6_adjustments_d0; +wire grp_td_fused_fu_990_tdf6_adjustments_we0; +wire [4:0] grp_td_fused_fu_990_tdf6_adjustments_address1; +wire grp_td_fused_fu_990_tdf6_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf6_adjustments_d1; +wire grp_td_fused_fu_990_tdf6_adjustments_we1; +wire [7:0] grp_td_fused_fu_990_tdf7_adjustments_address0; +wire grp_td_fused_fu_990_tdf7_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf7_adjustments_d0; +wire grp_td_fused_fu_990_tdf7_adjustments_we0; +wire [7:0] grp_td_fused_fu_990_tdf7_adjustments_address1; +wire grp_td_fused_fu_990_tdf7_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf7_adjustments_d1; +wire grp_td_fused_fu_990_tdf7_adjustments_we1; +wire [4:0] grp_td_fused_fu_990_tdf7_l2_adjustments_address0; +wire grp_td_fused_fu_990_tdf7_l2_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf7_l2_adjustments_d0; +wire grp_td_fused_fu_990_tdf7_l2_adjustments_we0; +wire [4:0] grp_td_fused_fu_990_tdf7_l2_adjustments_address1; +wire grp_td_fused_fu_990_tdf7_l2_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf7_l2_adjustments_d1; +wire grp_td_fused_fu_990_tdf7_l2_adjustments_we1; +wire [7:0] grp_td_fused_fu_990_tdf8_adjustments_address0; +wire grp_td_fused_fu_990_tdf8_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf8_adjustments_d0; +wire grp_td_fused_fu_990_tdf8_adjustments_we0; +wire [7:0] grp_td_fused_fu_990_tdf8_adjustments_address1; +wire grp_td_fused_fu_990_tdf8_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf8_adjustments_d1; +wire grp_td_fused_fu_990_tdf8_adjustments_we1; +wire [5:0] grp_td_fused_fu_990_tdf9_adjustments_address0; +wire grp_td_fused_fu_990_tdf9_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf9_adjustments_d0; +wire grp_td_fused_fu_990_tdf9_adjustments_we0; +wire [5:0] grp_td_fused_fu_990_tdf9_adjustments_address1; +wire grp_td_fused_fu_990_tdf9_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf9_adjustments_d1; +wire grp_td_fused_fu_990_tdf9_adjustments_we1; +wire [8:0] grp_td_fused_fu_990_tdf10_adjustments_address0; +wire grp_td_fused_fu_990_tdf10_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf10_adjustments_d0; +wire grp_td_fused_fu_990_tdf10_adjustments_we0; +wire [8:0] grp_td_fused_fu_990_tdf10_adjustments_address1; +wire grp_td_fused_fu_990_tdf10_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf10_adjustments_d1; +wire grp_td_fused_fu_990_tdf10_adjustments_we1; +wire [5:0] grp_td_fused_fu_990_tdf10_l2_adjustments_address0; +wire grp_td_fused_fu_990_tdf10_l2_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf10_l2_adjustments_d0; +wire grp_td_fused_fu_990_tdf10_l2_adjustments_we0; +wire [5:0] grp_td_fused_fu_990_tdf10_l2_adjustments_address1; +wire grp_td_fused_fu_990_tdf10_l2_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf10_l2_adjustments_d1; +wire grp_td_fused_fu_990_tdf10_l2_adjustments_we1; +wire [8:0] grp_td_fused_fu_990_tdf11_adjustments_address0; +wire grp_td_fused_fu_990_tdf11_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf11_adjustments_d0; +wire grp_td_fused_fu_990_tdf11_adjustments_we0; +wire [8:0] grp_td_fused_fu_990_tdf11_adjustments_address1; +wire grp_td_fused_fu_990_tdf11_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf11_adjustments_d1; +wire grp_td_fused_fu_990_tdf11_adjustments_we1; +wire [6:0] grp_td_fused_fu_990_tdf11_l2_adjustments_address0; +wire grp_td_fused_fu_990_tdf11_l2_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf11_l2_adjustments_d0; +wire grp_td_fused_fu_990_tdf11_l2_adjustments_we0; +wire [6:0] grp_td_fused_fu_990_tdf11_l2_adjustments_address1; +wire grp_td_fused_fu_990_tdf11_l2_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf11_l2_adjustments_d1; +wire grp_td_fused_fu_990_tdf11_l2_adjustments_we1; +wire [9:0] grp_td_fused_fu_990_tdf12_adjustments_address0; +wire grp_td_fused_fu_990_tdf12_adjustments_ce0; +wire [47:0] grp_td_fused_fu_990_tdf12_adjustments_d0; +wire grp_td_fused_fu_990_tdf12_adjustments_we0; +wire [9:0] grp_td_fused_fu_990_tdf12_adjustments_address1; +wire grp_td_fused_fu_990_tdf12_adjustments_ce1; +wire [47:0] grp_td_fused_fu_990_tdf12_adjustments_d1; +wire grp_td_fused_fu_990_tdf12_adjustments_we1; +wire [15:0] grp_td_fused_fu_990_stream_out_TDATA; +wire [1:0] grp_td_fused_fu_990_stream_out_TKEEP; +wire [1:0] grp_td_fused_fu_990_stream_out_TSTRB; +wire [0:0] grp_td_fused_fu_990_stream_out_TLAST; +wire grp_td_fused_fu_990_stream_in_TREADY; +wire grp_td_fused_fu_990_ap_start; +wire grp_td_fused_fu_990_stream_out_TVALID; +wire grp_td_fused_fu_990_stream_out_TREADY; +wire grp_td_fused_fu_990_ap_done; +wire grp_td_fused_fu_990_ap_ready; +wire grp_td_fused_fu_990_ap_idle; +reg grp_td_fused_fu_990_ap_continue; +reg grp_td_fused_fu_990_ap_start_reg; +wire ap_CS_fsm_state3; +wire ap_CS_fsm_state4; +wire ap_sync_grp_td_fused_fu_990_ap_ready; +wire ap_sync_grp_td_fused_fu_990_ap_done; +reg ap_block_state4_on_subcall_done; +reg ap_sync_reg_grp_td_fused_fu_990_ap_ready; +reg ap_sync_reg_grp_td_fused_fu_990_ap_done; +wire ap_CS_fsm_state2; +wire ap_CS_fsm_state5; +wire regslice_both_stream_out_V_data_V_U_apdone_blk; +reg [4:0] ap_NS_fsm; +wire regslice_both_stream_in_V_data_V_U_apdone_blk; +wire [15:0] stream_in_TDATA_int_regslice; +wire stream_in_TVALID_int_regslice; +reg stream_in_TREADY_int_regslice; +wire regslice_both_stream_in_V_data_V_U_ack_in; +wire regslice_both_stream_in_V_keep_V_U_apdone_blk; +wire [1:0] stream_in_TKEEP_int_regslice; +wire regslice_both_stream_in_V_keep_V_U_vld_out; +wire regslice_both_stream_in_V_keep_V_U_ack_in; +wire regslice_both_stream_in_V_strb_V_U_apdone_blk; +wire [1:0] stream_in_TSTRB_int_regslice; +wire regslice_both_stream_in_V_strb_V_U_vld_out; +wire regslice_both_stream_in_V_strb_V_U_ack_in; +wire regslice_both_stream_in_V_last_V_U_apdone_blk; +wire [0:0] stream_in_TLAST_int_regslice; +wire regslice_both_stream_in_V_last_V_U_vld_out; +wire regslice_both_stream_in_V_last_V_U_ack_in; +wire stream_out_TREADY_int_regslice; +wire regslice_both_stream_out_V_data_V_U_vld_out; +wire regslice_both_stream_out_V_keep_V_U_apdone_blk; +wire regslice_both_stream_out_V_keep_V_U_ack_in_dummy; +wire regslice_both_stream_out_V_keep_V_U_vld_out; +wire regslice_both_stream_out_V_strb_V_U_apdone_blk; +wire regslice_both_stream_out_V_strb_V_U_ack_in_dummy; +wire regslice_both_stream_out_V_strb_V_U_vld_out; +wire regslice_both_stream_out_V_last_V_U_apdone_blk; +wire regslice_both_stream_out_V_last_V_U_ack_in_dummy; +wire regslice_both_stream_out_V_last_V_U_vld_out; +wire ap_ce_reg; + +// power-on initialization +initial begin +#0 ap_CS_fsm = 5'd1; +#0 grp_td_fused_fu_990_ap_start_reg = 1'b0; +#0 ap_sync_reg_grp_td_fused_fu_990_ap_ready = 1'b0; +#0 ap_sync_reg_grp_td_fused_fu_990_ap_done = 1'b0; +end + +td_fused_top_tdf1_filters #( + .DataWidth( 16 ), + .AddressRange( 432 ), + .AddressWidth( 9 )) +tdf1_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf1_filters_address0), + .ce0(tdf1_filters_ce0), + .q0(tdf1_filters_q0), + .address1(tdf1_filters_address1), + .ce1(tdf1_filters_ce1), + .we1(tdf1_filters_we1), + .d1(tmp_data_fu_1262_p1) +); + +td_fused_top_tdf2_filters #( + .DataWidth( 16 ), + .AddressRange( 4608 ), + .AddressWidth( 13 )) +tdf2_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf2_filters_address0), + .ce0(tdf2_filters_ce0), + .q0(tdf2_filters_q0), + .address1(tdf2_filters_address1), + .ce1(tdf2_filters_ce1), + .we1(tdf2_filters_we1), + .d1(tmp_data_fu_1262_p1) +); + +td_fused_top_tdf3_filters #( + .DataWidth( 16 ), + .AddressRange( 512 ), + .AddressWidth( 9 )) +tdf3_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf3_filters_address0), + .ce0(tdf3_filters_ce0), + .q0(tdf3_filters_q0), + .address1(tdf3_filters_address1), + .ce1(tdf3_filters_ce1), + .we1(tdf3_filters_we1), + .d1(tmp_data_fu_1262_p1) +); + +td_fused_top_tdf4_filters #( + .DataWidth( 16 ), + .AddressRange( 18432 ), + .AddressWidth( 15 )) +tdf4_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf4_filters_address0), + .ce0(tdf4_filters_ce0), + .q0(tdf4_filters_q0), + .address1(tdf4_filters_address1), + .ce1(tdf4_filters_ce1), + .we1(tdf4_filters_we1), + .d1(tmp_data_fu_1262_p1) +); + +td_fused_top_tdf4_l2_filters #( + .DataWidth( 16 ), + .AddressRange( 2048 ), + .AddressWidth( 11 )) +tdf4_l2_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf4_l2_filters_address0), + .ce0(tdf4_l2_filters_ce0), + .q0(tdf4_l2_filters_q0), + .address1(tdf4_l2_filters_address1), + .ce1(tdf4_l2_filters_ce1), + .we1(tdf4_l2_filters_we1), + .d1(tmp_data_fu_1262_p1) +); + +td_fused_top_tdf4_filters #( + .DataWidth( 16 ), + .AddressRange( 18432 ), + .AddressWidth( 15 )) +tdf5_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf5_filters_address0), + .ce0(tdf5_filters_ce0), + .q0(tdf5_filters_q0), + .address1(tdf5_filters_address1), + .ce1(tdf5_filters_ce1), + .we1(tdf5_filters_we1), + .d1(tmp_data_fu_1262_p1) +); + +td_fused_top_tdf6_filters #( + .DataWidth( 16 ), + .AddressRange( 4096 ), + .AddressWidth( 12 )) +tdf6_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf6_filters_address0), + .ce0(tdf6_filters_ce0), + .q0(tdf6_filters_q0), + .address1(tdf6_filters_address1), + .ce1(tdf6_filters_ce1), + .we1(tdf6_filters_we1), + .d1(tmp_data_fu_1262_p1) +); + +td_fused_top_tdf7_filters #( + .DataWidth( 16 ), + .AddressRange( 73728 ), + .AddressWidth( 17 )) +tdf7_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf7_filters_address0), + .ce0(tdf7_filters_ce0), + .q0(tdf7_filters_q0), + .address1(tdf7_filters_address1), + .ce1(tdf7_filters_ce1), + .we1(tdf7_filters_we1), + .d1(tmp_data_fu_1262_p1) +); + +td_fused_top_tdf7_l2_filters #( + .DataWidth( 16 ), + .AddressRange( 8192 ), + .AddressWidth( 13 )) +tdf7_l2_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf7_l2_filters_address0), + .ce0(tdf7_l2_filters_ce0), + .q0(tdf7_l2_filters_q0), + .address1(tdf7_l2_filters_address1), + .ce1(tdf7_l2_filters_ce1), + .we1(tdf7_l2_filters_we1), + .d1(tmp_data_fu_1262_p1) +); + +td_fused_top_tdf7_filters #( + .DataWidth( 16 ), + .AddressRange( 73728 ), + .AddressWidth( 17 )) +tdf8_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf8_filters_address0), + .ce0(tdf8_filters_ce0), + .q0(tdf8_filters_q0), + .address1(tdf8_filters_address1), + .ce1(tdf8_filters_ce1), + .we1(tdf8_filters_we1), + .d1(tmp_data_fu_1262_p1) +); + +td_fused_top_tdf9_filters #( + .DataWidth( 16 ), + .AddressRange( 16384 ), + .AddressWidth( 14 )) +tdf9_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf9_filters_address0), + .ce0(tdf9_filters_ce0), + .q0(tdf9_filters_q0), + .address1(tdf9_filters_address1), + .ce1(tdf9_filters_ce1), + .we1(tdf9_filters_we1), + .d1(tmp_data_fu_1262_p1) +); + +td_fused_top_tdf10_filters #( + .DataWidth( 64 ), + .AddressRange( 73728 ), + .AddressWidth( 17 )) +tdf10_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf10_filters_address0), + .ce0(tdf10_filters_ce0), + .q0(tdf10_filters_q0), + .address1(tdf10_filters_address1), + .ce1(tdf10_filters_ce1), + .we1(tdf10_filters_we1), + .d1(tmp_fu_1280_p5) +); + +td_fused_top_tdf10_l2_filters #( + .DataWidth( 16 ), + .AddressRange( 32768 ), + .AddressWidth( 15 )) +tdf10_l2_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf10_l2_filters_address0), + .ce0(tdf10_l2_filters_ce0), + .q0(tdf10_l2_filters_q0), + .address1(tdf10_l2_filters_address1), + .ce1(tdf10_l2_filters_ce1), + .we1(tdf10_l2_filters_we1), + .d1(tmp_data_fu_1262_p1) +); + +td_fused_top_tdf10_filters #( + .DataWidth( 64 ), + .AddressRange( 73728 ), + .AddressWidth( 17 )) +tdf11_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf11_filters_address0), + .ce0(tdf11_filters_ce0), + .q0(tdf11_filters_q0), + .address1(tdf11_filters_address1), + .ce1(tdf11_filters_ce1), + .we1(tdf11_filters_we1), + .d1(tmp_fu_1280_p5) +); + +td_fused_top_tdf11_l2_filters #( + .DataWidth( 16 ), + .AddressRange( 65536 ), + .AddressWidth( 16 )) +tdf11_l2_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf11_l2_filters_address0), + .ce0(tdf11_l2_filters_ce0), + .q0(tdf11_l2_filters_q0), + .address1(tdf11_l2_filters_address1), + .ce1(tdf11_l2_filters_ce1), + .we1(tdf11_l2_filters_we1), + .d1(tmp_data_fu_1262_p1) +); + +td_fused_top_tdf12_filters #( + .DataWidth( 16 ), + .AddressRange( 128000 ), + .AddressWidth( 17 )) +tdf12_filters_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf12_filters_address0), + .ce0(tdf12_filters_ce0), + .q0(tdf12_filters_q0), + .address1(tdf12_filters_address1), + .ce1(tdf12_filters_ce1), + .we1(tdf12_filters_we1), + .d1(tmp_data_fu_1262_p1) +); + +td_fused_top_tdf1_adjustments #( + .DataWidth( 48 ), + .AddressRange( 16 ), + .AddressWidth( 4 )) +tdf1_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf1_adjustments_address0), + .ce0(tdf1_adjustments_ce0), + .q0(tdf1_adjustments_q0), + .address1(tdf1_adjustments_address1), + .ce1(tdf1_adjustments_ce1), + .we1(tdf1_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_tdf2_adjustments #( + .DataWidth( 48 ), + .AddressRange( 32 ), + .AddressWidth( 5 )) +tdf2_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf2_adjustments_address0), + .ce0(tdf2_adjustments_ce0), + .q0(tdf2_adjustments_q0), + .address1(tdf2_adjustments_address1), + .ce1(tdf2_adjustments_ce1), + .we1(tdf2_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_tdf1_adjustments #( + .DataWidth( 48 ), + .AddressRange( 16 ), + .AddressWidth( 4 )) +tdf3_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf3_adjustments_address0), + .ce0(tdf3_adjustments_ce0), + .q0(tdf3_adjustments_q0), + .address1(tdf3_adjustments_address1), + .ce1(tdf3_adjustments_ce1), + .we1(tdf3_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_tdf4_adjustments #( + .DataWidth( 48 ), + .AddressRange( 128 ), + .AddressWidth( 7 )) +tdf4_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf4_adjustments_address0), + .ce0(tdf4_adjustments_ce0), + .q0(tdf4_adjustments_q0), + .address1(tdf4_adjustments_address1), + .ce1(tdf4_adjustments_ce1), + .we1(tdf4_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_tdf1_adjustments #( + .DataWidth( 48 ), + .AddressRange( 16 ), + .AddressWidth( 4 )) +tdf4_l2_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf4_l2_adjustments_address0), + .ce0(tdf4_l2_adjustments_ce0), + .q0(tdf4_l2_adjustments_q0), + .address1(tdf4_l2_adjustments_address1), + .ce1(tdf4_l2_adjustments_ce1), + .we1(tdf4_l2_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_tdf4_adjustments #( + .DataWidth( 48 ), + .AddressRange( 128 ), + .AddressWidth( 7 )) +tdf5_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf5_adjustments_address0), + .ce0(tdf5_adjustments_ce0), + .q0(tdf5_adjustments_q0), + .address1(tdf5_adjustments_address1), + .ce1(tdf5_adjustments_ce1), + .we1(tdf5_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_tdf2_adjustments #( + .DataWidth( 48 ), + .AddressRange( 32 ), + .AddressWidth( 5 )) +tdf6_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf6_adjustments_address0), + .ce0(tdf6_adjustments_ce0), + .q0(tdf6_adjustments_q0), + .address1(tdf6_adjustments_address1), + .ce1(tdf6_adjustments_ce1), + .we1(tdf6_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_tdf7_adjustments #( + .DataWidth( 48 ), + .AddressRange( 256 ), + .AddressWidth( 8 )) +tdf7_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf7_adjustments_address0), + .ce0(tdf7_adjustments_ce0), + .q0(tdf7_adjustments_q0), + .address1(tdf7_adjustments_address1), + .ce1(tdf7_adjustments_ce1), + .we1(tdf7_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_tdf2_adjustments #( + .DataWidth( 48 ), + .AddressRange( 32 ), + .AddressWidth( 5 )) +tdf7_l2_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf7_l2_adjustments_address0), + .ce0(tdf7_l2_adjustments_ce0), + .q0(tdf7_l2_adjustments_q0), + .address1(tdf7_l2_adjustments_address1), + .ce1(tdf7_l2_adjustments_ce1), + .we1(tdf7_l2_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_tdf7_adjustments #( + .DataWidth( 48 ), + .AddressRange( 256 ), + .AddressWidth( 8 )) +tdf8_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf8_adjustments_address0), + .ce0(tdf8_adjustments_ce0), + .q0(tdf8_adjustments_q0), + .address1(tdf8_adjustments_address1), + .ce1(tdf8_adjustments_ce1), + .we1(tdf8_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_tdf9_adjustments #( + .DataWidth( 48 ), + .AddressRange( 64 ), + .AddressWidth( 6 )) +tdf9_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf9_adjustments_address0), + .ce0(tdf9_adjustments_ce0), + .q0(tdf9_adjustments_q0), + .address1(tdf9_adjustments_address1), + .ce1(tdf9_adjustments_ce1), + .we1(tdf9_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_tdf10_adjustments #( + .DataWidth( 48 ), + .AddressRange( 512 ), + .AddressWidth( 9 )) +tdf10_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf10_adjustments_address0), + .ce0(tdf10_adjustments_ce0), + .q0(tdf10_adjustments_q0), + .address1(tdf10_adjustments_address1), + .ce1(tdf10_adjustments_ce1), + .we1(tdf10_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_tdf9_adjustments #( + .DataWidth( 48 ), + .AddressRange( 64 ), + .AddressWidth( 6 )) +tdf10_l2_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf10_l2_adjustments_address0), + .ce0(tdf10_l2_adjustments_ce0), + .q0(tdf10_l2_adjustments_q0), + .address1(tdf10_l2_adjustments_address1), + .ce1(tdf10_l2_adjustments_ce1), + .we1(tdf10_l2_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_tdf10_adjustments #( + .DataWidth( 48 ), + .AddressRange( 512 ), + .AddressWidth( 9 )) +tdf11_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf11_adjustments_address0), + .ce0(tdf11_adjustments_ce0), + .q0(tdf11_adjustments_q0), + .address1(tdf11_adjustments_address1), + .ce1(tdf11_adjustments_ce1), + .we1(tdf11_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_tdf4_adjustments #( + .DataWidth( 48 ), + .AddressRange( 128 ), + .AddressWidth( 7 )) +tdf11_l2_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf11_l2_adjustments_address0), + .ce0(tdf11_l2_adjustments_ce0), + .q0(tdf11_l2_adjustments_q0), + .address1(tdf11_l2_adjustments_address1), + .ce1(tdf11_l2_adjustments_ce1), + .we1(tdf11_l2_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_tdf12_adjustments #( + .DataWidth( 48 ), + .AddressRange( 1000 ), + .AddressWidth( 10 )) +tdf12_adjustments_U( + .reset(ap_rst_n_inv), + .clk(ap_clk), + .address0(grp_td_fused_fu_990_tdf12_adjustments_address0), + .ce0(tdf12_adjustments_ce0), + .q0(tdf12_adjustments_q0), + .address1(tdf12_adjustments_address1), + .ce1(tdf12_adjustments_ce1), + .we1(tdf12_adjustments_we1), + .d1(trunc_ln151_fu_1294_p1) +); + +td_fused_top_td_fused grp_td_fused_fu_990( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .tdf1_filters_address0(grp_td_fused_fu_990_tdf1_filters_address0), + .tdf1_filters_ce0(grp_td_fused_fu_990_tdf1_filters_ce0), + .tdf1_filters_d0(grp_td_fused_fu_990_tdf1_filters_d0), + .tdf1_filters_q0(tdf1_filters_q0), + .tdf1_filters_we0(grp_td_fused_fu_990_tdf1_filters_we0), + .tdf1_filters_address1(grp_td_fused_fu_990_tdf1_filters_address1), + .tdf1_filters_ce1(grp_td_fused_fu_990_tdf1_filters_ce1), + .tdf1_filters_d1(grp_td_fused_fu_990_tdf1_filters_d1), + .tdf1_filters_q1(16'd0), + .tdf1_filters_we1(grp_td_fused_fu_990_tdf1_filters_we1), + .tdf2_filters_address0(grp_td_fused_fu_990_tdf2_filters_address0), + .tdf2_filters_ce0(grp_td_fused_fu_990_tdf2_filters_ce0), + .tdf2_filters_d0(grp_td_fused_fu_990_tdf2_filters_d0), + .tdf2_filters_q0(tdf2_filters_q0), + .tdf2_filters_we0(grp_td_fused_fu_990_tdf2_filters_we0), + .tdf2_filters_address1(grp_td_fused_fu_990_tdf2_filters_address1), + .tdf2_filters_ce1(grp_td_fused_fu_990_tdf2_filters_ce1), + .tdf2_filters_d1(grp_td_fused_fu_990_tdf2_filters_d1), + .tdf2_filters_q1(16'd0), + .tdf2_filters_we1(grp_td_fused_fu_990_tdf2_filters_we1), + .tdf3_filters_address0(grp_td_fused_fu_990_tdf3_filters_address0), + .tdf3_filters_ce0(grp_td_fused_fu_990_tdf3_filters_ce0), + .tdf3_filters_d0(grp_td_fused_fu_990_tdf3_filters_d0), + .tdf3_filters_q0(tdf3_filters_q0), + .tdf3_filters_we0(grp_td_fused_fu_990_tdf3_filters_we0), + .tdf3_filters_address1(grp_td_fused_fu_990_tdf3_filters_address1), + .tdf3_filters_ce1(grp_td_fused_fu_990_tdf3_filters_ce1), + .tdf3_filters_d1(grp_td_fused_fu_990_tdf3_filters_d1), + .tdf3_filters_q1(16'd0), + .tdf3_filters_we1(grp_td_fused_fu_990_tdf3_filters_we1), + .tdf4_filters_address0(grp_td_fused_fu_990_tdf4_filters_address0), + .tdf4_filters_ce0(grp_td_fused_fu_990_tdf4_filters_ce0), + .tdf4_filters_d0(grp_td_fused_fu_990_tdf4_filters_d0), + .tdf4_filters_q0(tdf4_filters_q0), + .tdf4_filters_we0(grp_td_fused_fu_990_tdf4_filters_we0), + .tdf4_filters_address1(grp_td_fused_fu_990_tdf4_filters_address1), + .tdf4_filters_ce1(grp_td_fused_fu_990_tdf4_filters_ce1), + .tdf4_filters_d1(grp_td_fused_fu_990_tdf4_filters_d1), + .tdf4_filters_q1(16'd0), + .tdf4_filters_we1(grp_td_fused_fu_990_tdf4_filters_we1), + .tdf4_l2_filters_address0(grp_td_fused_fu_990_tdf4_l2_filters_address0), + .tdf4_l2_filters_ce0(grp_td_fused_fu_990_tdf4_l2_filters_ce0), + .tdf4_l2_filters_d0(grp_td_fused_fu_990_tdf4_l2_filters_d0), + .tdf4_l2_filters_q0(tdf4_l2_filters_q0), + .tdf4_l2_filters_we0(grp_td_fused_fu_990_tdf4_l2_filters_we0), + .tdf4_l2_filters_address1(grp_td_fused_fu_990_tdf4_l2_filters_address1), + .tdf4_l2_filters_ce1(grp_td_fused_fu_990_tdf4_l2_filters_ce1), + .tdf4_l2_filters_d1(grp_td_fused_fu_990_tdf4_l2_filters_d1), + .tdf4_l2_filters_q1(16'd0), + .tdf4_l2_filters_we1(grp_td_fused_fu_990_tdf4_l2_filters_we1), + .tdf5_filters_address0(grp_td_fused_fu_990_tdf5_filters_address0), + .tdf5_filters_ce0(grp_td_fused_fu_990_tdf5_filters_ce0), + .tdf5_filters_d0(grp_td_fused_fu_990_tdf5_filters_d0), + .tdf5_filters_q0(tdf5_filters_q0), + .tdf5_filters_we0(grp_td_fused_fu_990_tdf5_filters_we0), + .tdf5_filters_address1(grp_td_fused_fu_990_tdf5_filters_address1), + .tdf5_filters_ce1(grp_td_fused_fu_990_tdf5_filters_ce1), + .tdf5_filters_d1(grp_td_fused_fu_990_tdf5_filters_d1), + .tdf5_filters_q1(16'd0), + .tdf5_filters_we1(grp_td_fused_fu_990_tdf5_filters_we1), + .tdf6_filters_address0(grp_td_fused_fu_990_tdf6_filters_address0), + .tdf6_filters_ce0(grp_td_fused_fu_990_tdf6_filters_ce0), + .tdf6_filters_d0(grp_td_fused_fu_990_tdf6_filters_d0), + .tdf6_filters_q0(tdf6_filters_q0), + .tdf6_filters_we0(grp_td_fused_fu_990_tdf6_filters_we0), + .tdf6_filters_address1(grp_td_fused_fu_990_tdf6_filters_address1), + .tdf6_filters_ce1(grp_td_fused_fu_990_tdf6_filters_ce1), + .tdf6_filters_d1(grp_td_fused_fu_990_tdf6_filters_d1), + .tdf6_filters_q1(16'd0), + .tdf6_filters_we1(grp_td_fused_fu_990_tdf6_filters_we1), + .tdf7_filters_address0(grp_td_fused_fu_990_tdf7_filters_address0), + .tdf7_filters_ce0(grp_td_fused_fu_990_tdf7_filters_ce0), + .tdf7_filters_d0(grp_td_fused_fu_990_tdf7_filters_d0), + .tdf7_filters_q0(tdf7_filters_q0), + .tdf7_filters_we0(grp_td_fused_fu_990_tdf7_filters_we0), + .tdf7_filters_address1(grp_td_fused_fu_990_tdf7_filters_address1), + .tdf7_filters_ce1(grp_td_fused_fu_990_tdf7_filters_ce1), + .tdf7_filters_d1(grp_td_fused_fu_990_tdf7_filters_d1), + .tdf7_filters_q1(16'd0), + .tdf7_filters_we1(grp_td_fused_fu_990_tdf7_filters_we1), + .tdf7_l2_filters_address0(grp_td_fused_fu_990_tdf7_l2_filters_address0), + .tdf7_l2_filters_ce0(grp_td_fused_fu_990_tdf7_l2_filters_ce0), + .tdf7_l2_filters_d0(grp_td_fused_fu_990_tdf7_l2_filters_d0), + .tdf7_l2_filters_q0(tdf7_l2_filters_q0), + .tdf7_l2_filters_we0(grp_td_fused_fu_990_tdf7_l2_filters_we0), + .tdf7_l2_filters_address1(grp_td_fused_fu_990_tdf7_l2_filters_address1), + .tdf7_l2_filters_ce1(grp_td_fused_fu_990_tdf7_l2_filters_ce1), + .tdf7_l2_filters_d1(grp_td_fused_fu_990_tdf7_l2_filters_d1), + .tdf7_l2_filters_q1(16'd0), + .tdf7_l2_filters_we1(grp_td_fused_fu_990_tdf7_l2_filters_we1), + .tdf8_filters_address0(grp_td_fused_fu_990_tdf8_filters_address0), + .tdf8_filters_ce0(grp_td_fused_fu_990_tdf8_filters_ce0), + .tdf8_filters_d0(grp_td_fused_fu_990_tdf8_filters_d0), + .tdf8_filters_q0(tdf8_filters_q0), + .tdf8_filters_we0(grp_td_fused_fu_990_tdf8_filters_we0), + .tdf8_filters_address1(grp_td_fused_fu_990_tdf8_filters_address1), + .tdf8_filters_ce1(grp_td_fused_fu_990_tdf8_filters_ce1), + .tdf8_filters_d1(grp_td_fused_fu_990_tdf8_filters_d1), + .tdf8_filters_q1(16'd0), + .tdf8_filters_we1(grp_td_fused_fu_990_tdf8_filters_we1), + .tdf9_filters_address0(grp_td_fused_fu_990_tdf9_filters_address0), + .tdf9_filters_ce0(grp_td_fused_fu_990_tdf9_filters_ce0), + .tdf9_filters_d0(grp_td_fused_fu_990_tdf9_filters_d0), + .tdf9_filters_q0(tdf9_filters_q0), + .tdf9_filters_we0(grp_td_fused_fu_990_tdf9_filters_we0), + .tdf9_filters_address1(grp_td_fused_fu_990_tdf9_filters_address1), + .tdf9_filters_ce1(grp_td_fused_fu_990_tdf9_filters_ce1), + .tdf9_filters_d1(grp_td_fused_fu_990_tdf9_filters_d1), + .tdf9_filters_q1(16'd0), + .tdf9_filters_we1(grp_td_fused_fu_990_tdf9_filters_we1), + .tdf10_filters_address0(grp_td_fused_fu_990_tdf10_filters_address0), + .tdf10_filters_ce0(grp_td_fused_fu_990_tdf10_filters_ce0), + .tdf10_filters_d0(grp_td_fused_fu_990_tdf10_filters_d0), + .tdf10_filters_q0(tdf10_filters_q0), + .tdf10_filters_we0(grp_td_fused_fu_990_tdf10_filters_we0), + .tdf10_filters_address1(grp_td_fused_fu_990_tdf10_filters_address1), + .tdf10_filters_ce1(grp_td_fused_fu_990_tdf10_filters_ce1), + .tdf10_filters_d1(grp_td_fused_fu_990_tdf10_filters_d1), + .tdf10_filters_q1(64'd0), + .tdf10_filters_we1(grp_td_fused_fu_990_tdf10_filters_we1), + .tdf10_l2_filters_address0(grp_td_fused_fu_990_tdf10_l2_filters_address0), + .tdf10_l2_filters_ce0(grp_td_fused_fu_990_tdf10_l2_filters_ce0), + .tdf10_l2_filters_d0(grp_td_fused_fu_990_tdf10_l2_filters_d0), + .tdf10_l2_filters_q0(tdf10_l2_filters_q0), + .tdf10_l2_filters_we0(grp_td_fused_fu_990_tdf10_l2_filters_we0), + .tdf10_l2_filters_address1(grp_td_fused_fu_990_tdf10_l2_filters_address1), + .tdf10_l2_filters_ce1(grp_td_fused_fu_990_tdf10_l2_filters_ce1), + .tdf10_l2_filters_d1(grp_td_fused_fu_990_tdf10_l2_filters_d1), + .tdf10_l2_filters_q1(16'd0), + .tdf10_l2_filters_we1(grp_td_fused_fu_990_tdf10_l2_filters_we1), + .tdf11_filters_address0(grp_td_fused_fu_990_tdf11_filters_address0), + .tdf11_filters_ce0(grp_td_fused_fu_990_tdf11_filters_ce0), + .tdf11_filters_d0(grp_td_fused_fu_990_tdf11_filters_d0), + .tdf11_filters_q0(tdf11_filters_q0), + .tdf11_filters_we0(grp_td_fused_fu_990_tdf11_filters_we0), + .tdf11_filters_address1(grp_td_fused_fu_990_tdf11_filters_address1), + .tdf11_filters_ce1(grp_td_fused_fu_990_tdf11_filters_ce1), + .tdf11_filters_d1(grp_td_fused_fu_990_tdf11_filters_d1), + .tdf11_filters_q1(64'd0), + .tdf11_filters_we1(grp_td_fused_fu_990_tdf11_filters_we1), + .tdf11_l2_filters_address0(grp_td_fused_fu_990_tdf11_l2_filters_address0), + .tdf11_l2_filters_ce0(grp_td_fused_fu_990_tdf11_l2_filters_ce0), + .tdf11_l2_filters_d0(grp_td_fused_fu_990_tdf11_l2_filters_d0), + .tdf11_l2_filters_q0(tdf11_l2_filters_q0), + .tdf11_l2_filters_we0(grp_td_fused_fu_990_tdf11_l2_filters_we0), + .tdf11_l2_filters_address1(grp_td_fused_fu_990_tdf11_l2_filters_address1), + .tdf11_l2_filters_ce1(grp_td_fused_fu_990_tdf11_l2_filters_ce1), + .tdf11_l2_filters_d1(grp_td_fused_fu_990_tdf11_l2_filters_d1), + .tdf11_l2_filters_q1(16'd0), + .tdf11_l2_filters_we1(grp_td_fused_fu_990_tdf11_l2_filters_we1), + .tdf12_filters_address0(grp_td_fused_fu_990_tdf12_filters_address0), + .tdf12_filters_ce0(grp_td_fused_fu_990_tdf12_filters_ce0), + .tdf12_filters_d0(grp_td_fused_fu_990_tdf12_filters_d0), + .tdf12_filters_q0(tdf12_filters_q0), + .tdf12_filters_we0(grp_td_fused_fu_990_tdf12_filters_we0), + .tdf12_filters_address1(grp_td_fused_fu_990_tdf12_filters_address1), + .tdf12_filters_ce1(grp_td_fused_fu_990_tdf12_filters_ce1), + .tdf12_filters_d1(grp_td_fused_fu_990_tdf12_filters_d1), + .tdf12_filters_q1(16'd0), + .tdf12_filters_we1(grp_td_fused_fu_990_tdf12_filters_we1), + .tdf1_adjustments_address0(grp_td_fused_fu_990_tdf1_adjustments_address0), + .tdf1_adjustments_ce0(grp_td_fused_fu_990_tdf1_adjustments_ce0), + .tdf1_adjustments_d0(grp_td_fused_fu_990_tdf1_adjustments_d0), + .tdf1_adjustments_q0(tdf1_adjustments_q0), + .tdf1_adjustments_we0(grp_td_fused_fu_990_tdf1_adjustments_we0), + .tdf1_adjustments_address1(grp_td_fused_fu_990_tdf1_adjustments_address1), + .tdf1_adjustments_ce1(grp_td_fused_fu_990_tdf1_adjustments_ce1), + .tdf1_adjustments_d1(grp_td_fused_fu_990_tdf1_adjustments_d1), + .tdf1_adjustments_q1(48'd0), + .tdf1_adjustments_we1(grp_td_fused_fu_990_tdf1_adjustments_we1), + .tdf2_adjustments_address0(grp_td_fused_fu_990_tdf2_adjustments_address0), + .tdf2_adjustments_ce0(grp_td_fused_fu_990_tdf2_adjustments_ce0), + .tdf2_adjustments_d0(grp_td_fused_fu_990_tdf2_adjustments_d0), + .tdf2_adjustments_q0(tdf2_adjustments_q0), + .tdf2_adjustments_we0(grp_td_fused_fu_990_tdf2_adjustments_we0), + .tdf2_adjustments_address1(grp_td_fused_fu_990_tdf2_adjustments_address1), + .tdf2_adjustments_ce1(grp_td_fused_fu_990_tdf2_adjustments_ce1), + .tdf2_adjustments_d1(grp_td_fused_fu_990_tdf2_adjustments_d1), + .tdf2_adjustments_q1(48'd0), + .tdf2_adjustments_we1(grp_td_fused_fu_990_tdf2_adjustments_we1), + .tdf3_adjustments_address0(grp_td_fused_fu_990_tdf3_adjustments_address0), + .tdf3_adjustments_ce0(grp_td_fused_fu_990_tdf3_adjustments_ce0), + .tdf3_adjustments_d0(grp_td_fused_fu_990_tdf3_adjustments_d0), + .tdf3_adjustments_q0(tdf3_adjustments_q0), + .tdf3_adjustments_we0(grp_td_fused_fu_990_tdf3_adjustments_we0), + .tdf3_adjustments_address1(grp_td_fused_fu_990_tdf3_adjustments_address1), + .tdf3_adjustments_ce1(grp_td_fused_fu_990_tdf3_adjustments_ce1), + .tdf3_adjustments_d1(grp_td_fused_fu_990_tdf3_adjustments_d1), + .tdf3_adjustments_q1(48'd0), + .tdf3_adjustments_we1(grp_td_fused_fu_990_tdf3_adjustments_we1), + .tdf4_adjustments_address0(grp_td_fused_fu_990_tdf4_adjustments_address0), + .tdf4_adjustments_ce0(grp_td_fused_fu_990_tdf4_adjustments_ce0), + .tdf4_adjustments_d0(grp_td_fused_fu_990_tdf4_adjustments_d0), + .tdf4_adjustments_q0(tdf4_adjustments_q0), + .tdf4_adjustments_we0(grp_td_fused_fu_990_tdf4_adjustments_we0), + .tdf4_adjustments_address1(grp_td_fused_fu_990_tdf4_adjustments_address1), + .tdf4_adjustments_ce1(grp_td_fused_fu_990_tdf4_adjustments_ce1), + .tdf4_adjustments_d1(grp_td_fused_fu_990_tdf4_adjustments_d1), + .tdf4_adjustments_q1(48'd0), + .tdf4_adjustments_we1(grp_td_fused_fu_990_tdf4_adjustments_we1), + .tdf4_l2_adjustments_address0(grp_td_fused_fu_990_tdf4_l2_adjustments_address0), + .tdf4_l2_adjustments_ce0(grp_td_fused_fu_990_tdf4_l2_adjustments_ce0), + .tdf4_l2_adjustments_d0(grp_td_fused_fu_990_tdf4_l2_adjustments_d0), + .tdf4_l2_adjustments_q0(tdf4_l2_adjustments_q0), + .tdf4_l2_adjustments_we0(grp_td_fused_fu_990_tdf4_l2_adjustments_we0), + .tdf4_l2_adjustments_address1(grp_td_fused_fu_990_tdf4_l2_adjustments_address1), + .tdf4_l2_adjustments_ce1(grp_td_fused_fu_990_tdf4_l2_adjustments_ce1), + .tdf4_l2_adjustments_d1(grp_td_fused_fu_990_tdf4_l2_adjustments_d1), + .tdf4_l2_adjustments_q1(48'd0), + .tdf4_l2_adjustments_we1(grp_td_fused_fu_990_tdf4_l2_adjustments_we1), + .tdf5_adjustments_address0(grp_td_fused_fu_990_tdf5_adjustments_address0), + .tdf5_adjustments_ce0(grp_td_fused_fu_990_tdf5_adjustments_ce0), + .tdf5_adjustments_d0(grp_td_fused_fu_990_tdf5_adjustments_d0), + .tdf5_adjustments_q0(tdf5_adjustments_q0), + .tdf5_adjustments_we0(grp_td_fused_fu_990_tdf5_adjustments_we0), + .tdf5_adjustments_address1(grp_td_fused_fu_990_tdf5_adjustments_address1), + .tdf5_adjustments_ce1(grp_td_fused_fu_990_tdf5_adjustments_ce1), + .tdf5_adjustments_d1(grp_td_fused_fu_990_tdf5_adjustments_d1), + .tdf5_adjustments_q1(48'd0), + .tdf5_adjustments_we1(grp_td_fused_fu_990_tdf5_adjustments_we1), + .tdf6_adjustments_address0(grp_td_fused_fu_990_tdf6_adjustments_address0), + .tdf6_adjustments_ce0(grp_td_fused_fu_990_tdf6_adjustments_ce0), + .tdf6_adjustments_d0(grp_td_fused_fu_990_tdf6_adjustments_d0), + .tdf6_adjustments_q0(tdf6_adjustments_q0), + .tdf6_adjustments_we0(grp_td_fused_fu_990_tdf6_adjustments_we0), + .tdf6_adjustments_address1(grp_td_fused_fu_990_tdf6_adjustments_address1), + .tdf6_adjustments_ce1(grp_td_fused_fu_990_tdf6_adjustments_ce1), + .tdf6_adjustments_d1(grp_td_fused_fu_990_tdf6_adjustments_d1), + .tdf6_adjustments_q1(48'd0), + .tdf6_adjustments_we1(grp_td_fused_fu_990_tdf6_adjustments_we1), + .tdf7_adjustments_address0(grp_td_fused_fu_990_tdf7_adjustments_address0), + .tdf7_adjustments_ce0(grp_td_fused_fu_990_tdf7_adjustments_ce0), + .tdf7_adjustments_d0(grp_td_fused_fu_990_tdf7_adjustments_d0), + .tdf7_adjustments_q0(tdf7_adjustments_q0), + .tdf7_adjustments_we0(grp_td_fused_fu_990_tdf7_adjustments_we0), + .tdf7_adjustments_address1(grp_td_fused_fu_990_tdf7_adjustments_address1), + .tdf7_adjustments_ce1(grp_td_fused_fu_990_tdf7_adjustments_ce1), + .tdf7_adjustments_d1(grp_td_fused_fu_990_tdf7_adjustments_d1), + .tdf7_adjustments_q1(48'd0), + .tdf7_adjustments_we1(grp_td_fused_fu_990_tdf7_adjustments_we1), + .tdf7_l2_adjustments_address0(grp_td_fused_fu_990_tdf7_l2_adjustments_address0), + .tdf7_l2_adjustments_ce0(grp_td_fused_fu_990_tdf7_l2_adjustments_ce0), + .tdf7_l2_adjustments_d0(grp_td_fused_fu_990_tdf7_l2_adjustments_d0), + .tdf7_l2_adjustments_q0(tdf7_l2_adjustments_q0), + .tdf7_l2_adjustments_we0(grp_td_fused_fu_990_tdf7_l2_adjustments_we0), + .tdf7_l2_adjustments_address1(grp_td_fused_fu_990_tdf7_l2_adjustments_address1), + .tdf7_l2_adjustments_ce1(grp_td_fused_fu_990_tdf7_l2_adjustments_ce1), + .tdf7_l2_adjustments_d1(grp_td_fused_fu_990_tdf7_l2_adjustments_d1), + .tdf7_l2_adjustments_q1(48'd0), + .tdf7_l2_adjustments_we1(grp_td_fused_fu_990_tdf7_l2_adjustments_we1), + .tdf8_adjustments_address0(grp_td_fused_fu_990_tdf8_adjustments_address0), + .tdf8_adjustments_ce0(grp_td_fused_fu_990_tdf8_adjustments_ce0), + .tdf8_adjustments_d0(grp_td_fused_fu_990_tdf8_adjustments_d0), + .tdf8_adjustments_q0(tdf8_adjustments_q0), + .tdf8_adjustments_we0(grp_td_fused_fu_990_tdf8_adjustments_we0), + .tdf8_adjustments_address1(grp_td_fused_fu_990_tdf8_adjustments_address1), + .tdf8_adjustments_ce1(grp_td_fused_fu_990_tdf8_adjustments_ce1), + .tdf8_adjustments_d1(grp_td_fused_fu_990_tdf8_adjustments_d1), + .tdf8_adjustments_q1(48'd0), + .tdf8_adjustments_we1(grp_td_fused_fu_990_tdf8_adjustments_we1), + .tdf9_adjustments_address0(grp_td_fused_fu_990_tdf9_adjustments_address0), + .tdf9_adjustments_ce0(grp_td_fused_fu_990_tdf9_adjustments_ce0), + .tdf9_adjustments_d0(grp_td_fused_fu_990_tdf9_adjustments_d0), + .tdf9_adjustments_q0(tdf9_adjustments_q0), + .tdf9_adjustments_we0(grp_td_fused_fu_990_tdf9_adjustments_we0), + .tdf9_adjustments_address1(grp_td_fused_fu_990_tdf9_adjustments_address1), + .tdf9_adjustments_ce1(grp_td_fused_fu_990_tdf9_adjustments_ce1), + .tdf9_adjustments_d1(grp_td_fused_fu_990_tdf9_adjustments_d1), + .tdf9_adjustments_q1(48'd0), + .tdf9_adjustments_we1(grp_td_fused_fu_990_tdf9_adjustments_we1), + .tdf10_adjustments_address0(grp_td_fused_fu_990_tdf10_adjustments_address0), + .tdf10_adjustments_ce0(grp_td_fused_fu_990_tdf10_adjustments_ce0), + .tdf10_adjustments_d0(grp_td_fused_fu_990_tdf10_adjustments_d0), + .tdf10_adjustments_q0(tdf10_adjustments_q0), + .tdf10_adjustments_we0(grp_td_fused_fu_990_tdf10_adjustments_we0), + .tdf10_adjustments_address1(grp_td_fused_fu_990_tdf10_adjustments_address1), + .tdf10_adjustments_ce1(grp_td_fused_fu_990_tdf10_adjustments_ce1), + .tdf10_adjustments_d1(grp_td_fused_fu_990_tdf10_adjustments_d1), + .tdf10_adjustments_q1(48'd0), + .tdf10_adjustments_we1(grp_td_fused_fu_990_tdf10_adjustments_we1), + .tdf10_l2_adjustments_address0(grp_td_fused_fu_990_tdf10_l2_adjustments_address0), + .tdf10_l2_adjustments_ce0(grp_td_fused_fu_990_tdf10_l2_adjustments_ce0), + .tdf10_l2_adjustments_d0(grp_td_fused_fu_990_tdf10_l2_adjustments_d0), + .tdf10_l2_adjustments_q0(tdf10_l2_adjustments_q0), + .tdf10_l2_adjustments_we0(grp_td_fused_fu_990_tdf10_l2_adjustments_we0), + .tdf10_l2_adjustments_address1(grp_td_fused_fu_990_tdf10_l2_adjustments_address1), + .tdf10_l2_adjustments_ce1(grp_td_fused_fu_990_tdf10_l2_adjustments_ce1), + .tdf10_l2_adjustments_d1(grp_td_fused_fu_990_tdf10_l2_adjustments_d1), + .tdf10_l2_adjustments_q1(48'd0), + .tdf10_l2_adjustments_we1(grp_td_fused_fu_990_tdf10_l2_adjustments_we1), + .tdf11_adjustments_address0(grp_td_fused_fu_990_tdf11_adjustments_address0), + .tdf11_adjustments_ce0(grp_td_fused_fu_990_tdf11_adjustments_ce0), + .tdf11_adjustments_d0(grp_td_fused_fu_990_tdf11_adjustments_d0), + .tdf11_adjustments_q0(tdf11_adjustments_q0), + .tdf11_adjustments_we0(grp_td_fused_fu_990_tdf11_adjustments_we0), + .tdf11_adjustments_address1(grp_td_fused_fu_990_tdf11_adjustments_address1), + .tdf11_adjustments_ce1(grp_td_fused_fu_990_tdf11_adjustments_ce1), + .tdf11_adjustments_d1(grp_td_fused_fu_990_tdf11_adjustments_d1), + .tdf11_adjustments_q1(48'd0), + .tdf11_adjustments_we1(grp_td_fused_fu_990_tdf11_adjustments_we1), + .tdf11_l2_adjustments_address0(grp_td_fused_fu_990_tdf11_l2_adjustments_address0), + .tdf11_l2_adjustments_ce0(grp_td_fused_fu_990_tdf11_l2_adjustments_ce0), + .tdf11_l2_adjustments_d0(grp_td_fused_fu_990_tdf11_l2_adjustments_d0), + .tdf11_l2_adjustments_q0(tdf11_l2_adjustments_q0), + .tdf11_l2_adjustments_we0(grp_td_fused_fu_990_tdf11_l2_adjustments_we0), + .tdf11_l2_adjustments_address1(grp_td_fused_fu_990_tdf11_l2_adjustments_address1), + .tdf11_l2_adjustments_ce1(grp_td_fused_fu_990_tdf11_l2_adjustments_ce1), + .tdf11_l2_adjustments_d1(grp_td_fused_fu_990_tdf11_l2_adjustments_d1), + .tdf11_l2_adjustments_q1(48'd0), + .tdf11_l2_adjustments_we1(grp_td_fused_fu_990_tdf11_l2_adjustments_we1), + .tdf12_adjustments_address0(grp_td_fused_fu_990_tdf12_adjustments_address0), + .tdf12_adjustments_ce0(grp_td_fused_fu_990_tdf12_adjustments_ce0), + .tdf12_adjustments_d0(grp_td_fused_fu_990_tdf12_adjustments_d0), + .tdf12_adjustments_q0(tdf12_adjustments_q0), + .tdf12_adjustments_we0(grp_td_fused_fu_990_tdf12_adjustments_we0), + .tdf12_adjustments_address1(grp_td_fused_fu_990_tdf12_adjustments_address1), + .tdf12_adjustments_ce1(grp_td_fused_fu_990_tdf12_adjustments_ce1), + .tdf12_adjustments_d1(grp_td_fused_fu_990_tdf12_adjustments_d1), + .tdf12_adjustments_q1(48'd0), + .tdf12_adjustments_we1(grp_td_fused_fu_990_tdf12_adjustments_we1), + .stream_in_TDATA(stream_in_TDATA_int_regslice), + .stream_in_TKEEP(stream_in_TKEEP_int_regslice), + .stream_in_TSTRB(stream_in_TSTRB_int_regslice), + .stream_in_TLAST(stream_in_TLAST_int_regslice), + .stream_out_TDATA(grp_td_fused_fu_990_stream_out_TDATA), + .stream_out_TKEEP(grp_td_fused_fu_990_stream_out_TKEEP), + .stream_out_TSTRB(grp_td_fused_fu_990_stream_out_TSTRB), + .stream_out_TLAST(grp_td_fused_fu_990_stream_out_TLAST), + .stream_in_TVALID(stream_in_TVALID_int_regslice), + .stream_in_TREADY(grp_td_fused_fu_990_stream_in_TREADY), + .ap_start(grp_td_fused_fu_990_ap_start), + .stream_out_TVALID(grp_td_fused_fu_990_stream_out_TVALID), + .stream_out_TREADY(grp_td_fused_fu_990_stream_out_TREADY), + .ap_done(grp_td_fused_fu_990_ap_done), + .ap_ready(grp_td_fused_fu_990_ap_ready), + .ap_idle(grp_td_fused_fu_990_ap_idle), + .ap_continue(grp_td_fused_fu_990_ap_continue) +); + +td_fused_top_regslice_both #( + .DataWidth( 16 )) +regslice_both_stream_in_V_data_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(stream_in_TDATA), + .vld_in(stream_in_TVALID), + .ack_in(regslice_both_stream_in_V_data_V_U_ack_in), + .data_out(stream_in_TDATA_int_regslice), + .vld_out(stream_in_TVALID_int_regslice), + .ack_out(stream_in_TREADY_int_regslice), + .apdone_blk(regslice_both_stream_in_V_data_V_U_apdone_blk) +); + +td_fused_top_regslice_both #( + .DataWidth( 2 )) +regslice_both_stream_in_V_keep_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(stream_in_TKEEP), + .vld_in(stream_in_TVALID), + .ack_in(regslice_both_stream_in_V_keep_V_U_ack_in), + .data_out(stream_in_TKEEP_int_regslice), + .vld_out(regslice_both_stream_in_V_keep_V_U_vld_out), + .ack_out(stream_in_TREADY_int_regslice), + .apdone_blk(regslice_both_stream_in_V_keep_V_U_apdone_blk) +); + +td_fused_top_regslice_both #( + .DataWidth( 2 )) +regslice_both_stream_in_V_strb_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(stream_in_TSTRB), + .vld_in(stream_in_TVALID), + .ack_in(regslice_both_stream_in_V_strb_V_U_ack_in), + .data_out(stream_in_TSTRB_int_regslice), + .vld_out(regslice_both_stream_in_V_strb_V_U_vld_out), + .ack_out(stream_in_TREADY_int_regslice), + .apdone_blk(regslice_both_stream_in_V_strb_V_U_apdone_blk) +); + +td_fused_top_regslice_both #( + .DataWidth( 1 )) +regslice_both_stream_in_V_last_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(stream_in_TLAST), + .vld_in(stream_in_TVALID), + .ack_in(regslice_both_stream_in_V_last_V_U_ack_in), + .data_out(stream_in_TLAST_int_regslice), + .vld_out(regslice_both_stream_in_V_last_V_U_vld_out), + .ack_out(stream_in_TREADY_int_regslice), + .apdone_blk(regslice_both_stream_in_V_last_V_U_apdone_blk) +); + +td_fused_top_regslice_both #( + .DataWidth( 16 )) +regslice_both_stream_out_V_data_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(grp_td_fused_fu_990_stream_out_TDATA), + .vld_in(grp_td_fused_fu_990_stream_out_TVALID), + .ack_in(stream_out_TREADY_int_regslice), + .data_out(stream_out_TDATA), + .vld_out(regslice_both_stream_out_V_data_V_U_vld_out), + .ack_out(stream_out_TREADY), + .apdone_blk(regslice_both_stream_out_V_data_V_U_apdone_blk) +); + +td_fused_top_regslice_both #( + .DataWidth( 2 )) +regslice_both_stream_out_V_keep_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(grp_td_fused_fu_990_stream_out_TKEEP), + .vld_in(grp_td_fused_fu_990_stream_out_TVALID), + .ack_in(regslice_both_stream_out_V_keep_V_U_ack_in_dummy), + .data_out(stream_out_TKEEP), + .vld_out(regslice_both_stream_out_V_keep_V_U_vld_out), + .ack_out(stream_out_TREADY), + .apdone_blk(regslice_both_stream_out_V_keep_V_U_apdone_blk) +); + +td_fused_top_regslice_both #( + .DataWidth( 2 )) +regslice_both_stream_out_V_strb_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(grp_td_fused_fu_990_stream_out_TSTRB), + .vld_in(grp_td_fused_fu_990_stream_out_TVALID), + .ack_in(regslice_both_stream_out_V_strb_V_U_ack_in_dummy), + .data_out(stream_out_TSTRB), + .vld_out(regslice_both_stream_out_V_strb_V_U_vld_out), + .ack_out(stream_out_TREADY), + .apdone_blk(regslice_both_stream_out_V_strb_V_U_apdone_blk) +); + +td_fused_top_regslice_both #( + .DataWidth( 1 )) +regslice_both_stream_out_V_last_V_U( + .ap_clk(ap_clk), + .ap_rst(ap_rst_n_inv), + .data_in(grp_td_fused_fu_990_stream_out_TLAST), + .vld_in(grp_td_fused_fu_990_stream_out_TVALID), + .ack_in(regslice_both_stream_out_V_last_V_U_ack_in_dummy), + .data_out(stream_out_TLAST), + .vld_out(regslice_both_stream_out_V_last_V_U_vld_out), + .ack_out(stream_out_TREADY), + .apdone_blk(regslice_both_stream_out_V_last_V_U_apdone_blk) +); + +always @ (posedge ap_clk) begin + if (ap_rst_n_inv == 1'b1) begin + ap_CS_fsm <= ap_ST_fsm_state1; + end else begin + ap_CS_fsm <= ap_NS_fsm; + end +end + +always @ (posedge ap_clk) begin + if (ap_rst_n_inv == 1'b1) begin + ap_sync_reg_grp_td_fused_fu_990_ap_done <= 1'b0; + end else begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_sync_reg_grp_td_fused_fu_990_ap_done <= 1'b0; + end else if ((grp_td_fused_fu_990_ap_done == 1'b1)) begin + ap_sync_reg_grp_td_fused_fu_990_ap_done <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst_n_inv == 1'b1) begin + ap_sync_reg_grp_td_fused_fu_990_ap_ready <= 1'b0; + end else begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_sync_reg_grp_td_fused_fu_990_ap_ready <= 1'b0; + end else if ((grp_td_fused_fu_990_ap_ready == 1'b1)) begin + ap_sync_reg_grp_td_fused_fu_990_ap_ready <= 1'b1; + end + end +end + +always @ (posedge ap_clk) begin + if (ap_rst_n_inv == 1'b1) begin + grp_td_fused_fu_990_ap_start_reg <= 1'b0; + end else begin + if (((1'b1 == ap_CS_fsm_state3) | ((ap_sync_grp_td_fused_fu_990_ap_ready == 1'b0) & (1'b1 == ap_CS_fsm_state4)))) begin + grp_td_fused_fu_990_ap_start_reg <= 1'b1; + end else if ((grp_td_fused_fu_990_ap_ready == 1'b1)) begin + grp_td_fused_fu_990_ap_start_reg <= 1'b0; + end + end +end + +always @ (*) begin + if (((regslice_both_stream_out_V_data_V_U_apdone_blk == 1'b0) & (1'b1 == ap_CS_fsm_state5))) begin + ap_done = 1'b1; + end else begin + ap_done = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b0))) begin + ap_idle = 1'b1; + end else begin + ap_idle = 1'b0; + end +end + +always @ (*) begin + if (((regslice_both_stream_out_V_data_V_U_apdone_blk == 1'b0) & (1'b1 == ap_CS_fsm_state5))) begin + ap_ready = 1'b1; + end else begin + ap_ready = 1'b0; + end +end + +always @ (*) begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + grp_td_fused_fu_990_ap_continue = 1'b1; + end else begin + grp_td_fused_fu_990_ap_continue = 1'b0; + end +end + +always @ (*) begin + if (((stream_in_TVALID_int_regslice == 1'b1) & (1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + stream_in_TREADY_int_regslice = 1'b1; + end else if ((1'b1 == ap_CS_fsm_state4)) begin + stream_in_TREADY_int_regslice = grp_td_fused_fu_990_stream_in_TREADY; + end else begin + stream_in_TREADY_int_regslice = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf10_adjustments_ce0 = grp_td_fused_fu_990_tdf10_adjustments_ce0; + end else begin + tdf10_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf10_adjustments_ce1 = 1'b1; + end else begin + tdf10_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf10_adjustments_we1 = 1'b1; + end else begin + tdf10_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf10_filters_ce0 = grp_td_fused_fu_990_tdf10_filters_ce0; + end else begin + tdf10_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf10_filters_ce1 = 1'b1; + end else begin + tdf10_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf10_filters_we1 = 1'b1; + end else begin + tdf10_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf10_l2_adjustments_ce0 = grp_td_fused_fu_990_tdf10_l2_adjustments_ce0; + end else begin + tdf10_l2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf10_l2_adjustments_ce1 = 1'b1; + end else begin + tdf10_l2_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf10_l2_adjustments_we1 = 1'b1; + end else begin + tdf10_l2_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf10_l2_filters_ce0 = grp_td_fused_fu_990_tdf10_l2_filters_ce0; + end else begin + tdf10_l2_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf10_l2_filters_ce1 = 1'b1; + end else begin + tdf10_l2_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf10_l2_filters_we1 = 1'b1; + end else begin + tdf10_l2_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf11_adjustments_ce0 = grp_td_fused_fu_990_tdf11_adjustments_ce0; + end else begin + tdf11_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf11_adjustments_ce1 = 1'b1; + end else begin + tdf11_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf11_adjustments_we1 = 1'b1; + end else begin + tdf11_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf11_filters_ce0 = grp_td_fused_fu_990_tdf11_filters_ce0; + end else begin + tdf11_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf11_filters_ce1 = 1'b1; + end else begin + tdf11_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf11_filters_we1 = 1'b1; + end else begin + tdf11_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf11_l2_adjustments_ce0 = grp_td_fused_fu_990_tdf11_l2_adjustments_ce0; + end else begin + tdf11_l2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf11_l2_adjustments_ce1 = 1'b1; + end else begin + tdf11_l2_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf11_l2_adjustments_we1 = 1'b1; + end else begin + tdf11_l2_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf11_l2_filters_ce0 = grp_td_fused_fu_990_tdf11_l2_filters_ce0; + end else begin + tdf11_l2_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf11_l2_filters_ce1 = 1'b1; + end else begin + tdf11_l2_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf11_l2_filters_we1 = 1'b1; + end else begin + tdf11_l2_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf12_adjustments_ce0 = grp_td_fused_fu_990_tdf12_adjustments_ce0; + end else begin + tdf12_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf12_adjustments_ce1 = 1'b1; + end else begin + tdf12_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf12_adjustments_we1 = 1'b1; + end else begin + tdf12_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf12_filters_ce0 = grp_td_fused_fu_990_tdf12_filters_ce0; + end else begin + tdf12_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf12_filters_ce1 = 1'b1; + end else begin + tdf12_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf12_filters_we1 = 1'b1; + end else begin + tdf12_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf1_adjustments_ce0 = grp_td_fused_fu_990_tdf1_adjustments_ce0; + end else begin + tdf1_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf1_adjustments_ce1 = 1'b1; + end else begin + tdf1_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf1_adjustments_we1 = 1'b1; + end else begin + tdf1_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf1_filters_ce0 = grp_td_fused_fu_990_tdf1_filters_ce0; + end else begin + tdf1_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf1_filters_ce1 = 1'b1; + end else begin + tdf1_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf1_filters_we1 = 1'b1; + end else begin + tdf1_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf2_adjustments_ce0 = grp_td_fused_fu_990_tdf2_adjustments_ce0; + end else begin + tdf2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf2_adjustments_ce1 = 1'b1; + end else begin + tdf2_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf2_adjustments_we1 = 1'b1; + end else begin + tdf2_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf2_filters_ce0 = grp_td_fused_fu_990_tdf2_filters_ce0; + end else begin + tdf2_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf2_filters_ce1 = 1'b1; + end else begin + tdf2_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf2_filters_we1 = 1'b1; + end else begin + tdf2_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf3_adjustments_ce0 = grp_td_fused_fu_990_tdf3_adjustments_ce0; + end else begin + tdf3_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf3_adjustments_ce1 = 1'b1; + end else begin + tdf3_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf3_adjustments_we1 = 1'b1; + end else begin + tdf3_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf3_filters_ce0 = grp_td_fused_fu_990_tdf3_filters_ce0; + end else begin + tdf3_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf3_filters_ce1 = 1'b1; + end else begin + tdf3_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf3_filters_we1 = 1'b1; + end else begin + tdf3_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf4_adjustments_ce0 = grp_td_fused_fu_990_tdf4_adjustments_ce0; + end else begin + tdf4_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf4_adjustments_ce1 = 1'b1; + end else begin + tdf4_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf4_adjustments_we1 = 1'b1; + end else begin + tdf4_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf4_filters_ce0 = grp_td_fused_fu_990_tdf4_filters_ce0; + end else begin + tdf4_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf4_filters_ce1 = 1'b1; + end else begin + tdf4_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf4_filters_we1 = 1'b1; + end else begin + tdf4_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf4_l2_adjustments_ce0 = grp_td_fused_fu_990_tdf4_l2_adjustments_ce0; + end else begin + tdf4_l2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf4_l2_adjustments_ce1 = 1'b1; + end else begin + tdf4_l2_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf4_l2_adjustments_we1 = 1'b1; + end else begin + tdf4_l2_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf4_l2_filters_ce0 = grp_td_fused_fu_990_tdf4_l2_filters_ce0; + end else begin + tdf4_l2_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf4_l2_filters_ce1 = 1'b1; + end else begin + tdf4_l2_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf4_l2_filters_we1 = 1'b1; + end else begin + tdf4_l2_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf5_adjustments_ce0 = grp_td_fused_fu_990_tdf5_adjustments_ce0; + end else begin + tdf5_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf5_adjustments_ce1 = 1'b1; + end else begin + tdf5_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf5_adjustments_we1 = 1'b1; + end else begin + tdf5_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf5_filters_ce0 = grp_td_fused_fu_990_tdf5_filters_ce0; + end else begin + tdf5_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf5_filters_ce1 = 1'b1; + end else begin + tdf5_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf5_filters_we1 = 1'b1; + end else begin + tdf5_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf6_adjustments_ce0 = grp_td_fused_fu_990_tdf6_adjustments_ce0; + end else begin + tdf6_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf6_adjustments_ce1 = 1'b1; + end else begin + tdf6_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf6_adjustments_we1 = 1'b1; + end else begin + tdf6_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf6_filters_ce0 = grp_td_fused_fu_990_tdf6_filters_ce0; + end else begin + tdf6_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf6_filters_ce1 = 1'b1; + end else begin + tdf6_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf6_filters_we1 = 1'b1; + end else begin + tdf6_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf7_adjustments_ce0 = grp_td_fused_fu_990_tdf7_adjustments_ce0; + end else begin + tdf7_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf7_adjustments_ce1 = 1'b1; + end else begin + tdf7_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf7_adjustments_we1 = 1'b1; + end else begin + tdf7_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf7_filters_ce0 = grp_td_fused_fu_990_tdf7_filters_ce0; + end else begin + tdf7_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf7_filters_ce1 = 1'b1; + end else begin + tdf7_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf7_filters_we1 = 1'b1; + end else begin + tdf7_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf7_l2_adjustments_ce0 = grp_td_fused_fu_990_tdf7_l2_adjustments_ce0; + end else begin + tdf7_l2_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf7_l2_adjustments_ce1 = 1'b1; + end else begin + tdf7_l2_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf7_l2_adjustments_we1 = 1'b1; + end else begin + tdf7_l2_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf7_l2_filters_ce0 = grp_td_fused_fu_990_tdf7_l2_filters_ce0; + end else begin + tdf7_l2_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf7_l2_filters_ce1 = 1'b1; + end else begin + tdf7_l2_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf7_l2_filters_we1 = 1'b1; + end else begin + tdf7_l2_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf8_adjustments_ce0 = grp_td_fused_fu_990_tdf8_adjustments_ce0; + end else begin + tdf8_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf8_adjustments_ce1 = 1'b1; + end else begin + tdf8_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf8_adjustments_we1 = 1'b1; + end else begin + tdf8_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf8_filters_ce0 = grp_td_fused_fu_990_tdf8_filters_ce0; + end else begin + tdf8_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf8_filters_ce1 = 1'b1; + end else begin + tdf8_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf8_filters_we1 = 1'b1; + end else begin + tdf8_filters_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf9_adjustments_ce0 = grp_td_fused_fu_990_tdf9_adjustments_ce0; + end else begin + tdf9_adjustments_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf9_adjustments_ce1 = 1'b1; + end else begin + tdf9_adjustments_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf9_adjustments_we1 = 1'b1; + end else begin + tdf9_adjustments_we1 = 1'b0; + end +end + +always @ (*) begin + if ((1'b1 == ap_CS_fsm_state4)) begin + tdf9_filters_ce0 = grp_td_fused_fu_990_tdf9_filters_ce0; + end else begin + tdf9_filters_ce0 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)))) begin + tdf9_filters_ce1 = 1'b1; + end else begin + tdf9_filters_ce1 = 1'b0; + end +end + +always @ (*) begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + tdf9_filters_we1 = 1'b1; + end else begin + tdf9_filters_we1 = 1'b0; + end +end + +always @ (*) begin + case (ap_CS_fsm) + ap_ST_fsm_state1 : begin + if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin + ap_NS_fsm = ap_ST_fsm_state2; + end else begin + ap_NS_fsm = ap_ST_fsm_state1; + end + end + ap_ST_fsm_state2 : begin + ap_NS_fsm = ap_ST_fsm_state3; + end + ap_ST_fsm_state3 : begin + ap_NS_fsm = ap_ST_fsm_state4; + end + ap_ST_fsm_state4 : begin + if (((1'b0 == ap_block_state4_on_subcall_done) & (1'b1 == ap_CS_fsm_state4))) begin + ap_NS_fsm = ap_ST_fsm_state5; + end else begin + ap_NS_fsm = ap_ST_fsm_state4; + end + end + ap_ST_fsm_state5 : begin + if (((regslice_both_stream_out_V_data_V_U_apdone_blk == 1'b0) & (1'b1 == ap_CS_fsm_state5))) begin + ap_NS_fsm = ap_ST_fsm_state1; + end else begin + ap_NS_fsm = ap_ST_fsm_state5; + end + end + default : begin + ap_NS_fsm = 'bx; + end + endcase +end + +assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0]; + +assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1]; + +assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2]; + +assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3]; + +assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4]; + +always @ (*) begin + ap_block_state4_on_subcall_done = ((ap_sync_grp_td_fused_fu_990_ap_ready & ap_sync_grp_td_fused_fu_990_ap_done) == 1'b0); +end + +always @ (*) begin + ap_rst_n_inv = ~ap_rst_n; +end + +assign ap_sync_grp_td_fused_fu_990_ap_done = (grp_td_fused_fu_990_ap_done | ap_sync_reg_grp_td_fused_fu_990_ap_done); + +assign ap_sync_grp_td_fused_fu_990_ap_ready = (grp_td_fused_fu_990_ap_ready | ap_sync_reg_grp_td_fused_fu_990_ap_ready); + +assign grp_td_fused_fu_990_ap_start = grp_td_fused_fu_990_ap_start_reg; + +assign grp_td_fused_fu_990_stream_out_TREADY = (stream_out_TREADY_int_regslice & ap_CS_fsm_state4); + +assign stream_in_TREADY = regslice_both_stream_in_V_data_V_U_ack_in; + +assign stream_out_TVALID = regslice_both_stream_out_V_data_V_U_vld_out; + +assign tdf10_adjustments_address1 = 64'd0; + +assign tdf10_filters_address1 = 64'd0; + +assign tdf10_l2_adjustments_address1 = 64'd0; + +assign tdf10_l2_filters_address1 = 64'd0; + +assign tdf11_adjustments_address1 = 64'd0; + +assign tdf11_filters_address1 = 64'd0; + +assign tdf11_l2_adjustments_address1 = 64'd0; + +assign tdf11_l2_filters_address1 = 64'd0; + +assign tdf12_adjustments_address1 = 64'd0; + +assign tdf12_filters_address1 = 64'd0; + +assign tdf1_adjustments_address1 = 64'd0; + +assign tdf1_filters_address1 = 64'd0; + +assign tdf2_adjustments_address1 = 64'd0; + +assign tdf2_filters_address1 = 64'd0; + +assign tdf3_adjustments_address1 = 64'd0; + +assign tdf3_filters_address1 = 64'd0; + +assign tdf4_adjustments_address1 = 64'd0; + +assign tdf4_filters_address1 = 64'd0; + +assign tdf4_l2_adjustments_address1 = 64'd0; + +assign tdf4_l2_filters_address1 = 64'd0; + +assign tdf5_adjustments_address1 = 64'd0; + +assign tdf5_filters_address1 = 64'd0; + +assign tdf6_adjustments_address1 = 64'd0; + +assign tdf6_filters_address1 = 64'd0; + +assign tdf7_adjustments_address1 = 64'd0; + +assign tdf7_filters_address1 = 64'd0; + +assign tdf7_l2_adjustments_address1 = 64'd0; + +assign tdf7_l2_filters_address1 = 64'd0; + +assign tdf8_adjustments_address1 = 64'd0; + +assign tdf8_filters_address1 = 64'd0; + +assign tdf9_adjustments_address1 = 64'd0; + +assign tdf9_filters_address1 = 64'd0; + +assign tmp_data_fu_1262_p1 = stream_in_TDATA_int_regslice; + +assign tmp_fu_1280_p5 = {{ap_const_lv64_0[63:16]}, {stream_in_TDATA_int_regslice}}; + +assign trunc_ln151_fu_1294_p1 = tmp_fu_1280_p5[47:0]; + +endmodule //td_fused_top + + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Floating point 16-bit multiplier +// This is a heavily modified version of: +// https://github.com/fbrosser/DSP48E1-FP/tree/master/src/FPMult +// Original author: Fredrik Brosser +// Abridged by: Samidh Mehta +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// + +`ifndef complex_dsp + +`define EXPONENT 5 +`define MANTISSA 10 +`define ACTUAL_MANTISSA 11 +`define EXPONENT_LSB 10 +`define EXPONENT_MSB 14 +`define MANTISSA_LSB 0 +`define MANTISSA_MSB 9 +`define MANTISSA_MUL_SPLIT_LSB 3 +`define MANTISSA_MUL_SPLIT_MSB 9 +`define SIGN 1 +`define SIGN_LOC 15 +`define DWIDTH (`SIGN+`EXPONENT+`MANTISSA) +`define IEEE_COMPLIANCE 1 + +module FPMult_16( + clk, + rst, + a, + b, + result, + flags + ); + + // Input Ports + input clk ; // Clock + input rst ; // Reset signal + input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number + + // Output ports + output [`DWIDTH-1:0] result ; // Product, result of the operation, 32-bit FP number + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Internal signals + wire [31:0] Z_int ; // Product, result of the operation, 32-bit FP number + wire [4:0] Flags_int ; // Flags indicating exceptions according to IEEE754 + + wire Sa ; // A's sign + wire Sb ; // B's sign + wire Sp ; // Product sign + wire [`EXPONENT-1:0] Ea ; // A's exponent + wire [`EXPONENT-1:0] Eb ; // B's exponent + wire [2*`MANTISSA+1:0] Mp ; // Product mantissa + wire [4:0] InputExc ; // Exceptions in inputs + wire [`MANTISSA-1:0] NormM ; // Normalized mantissa + wire [`EXPONENT:0] NormE ; // Normalized exponent + wire [`MANTISSA:0] RoundM ; // Normalized mantissa + wire [`EXPONENT:0] RoundE ; // Normalized exponent + wire [`MANTISSA:0] RoundMP ; // Normalized mantissa + wire [`EXPONENT:0] RoundEP ; // Normalized exponent + wire GRS ; + + //reg [63:0] pipe_0; // Pipeline register Input->Prep + reg [2*`DWIDTH-1:0] pipe_0; // Pipeline register Input->Prep + + //reg [92:0] pipe_1; // Pipeline register Prep->Execute + reg [3*`MANTISSA+2*`EXPONENT+7:0] pipe_1; // Pipeline register Prep->Execute + + //reg [38:0] pipe_2; // Pipeline register Execute->Normalize + reg [`MANTISSA+`EXPONENT+7:0] pipe_2; // Pipeline register Execute->Normalize + + //reg [72:0] pipe_3; // Pipeline register Normalize->Round + reg [2*`MANTISSA+2*`EXPONENT+10:0] pipe_3; // Pipeline register Normalize->Round + + //reg [36:0] pipe_4; // Pipeline register Round->Output + reg [`DWIDTH+4:0] pipe_4; // Pipeline register Round->Output + + assign result = pipe_4[`DWIDTH+4:5] ; + assign flags = pipe_4[4:0] ; + + // Prepare the operands for alignment and check for exceptions + FPMult_PrepModule PrepModule(clk, rst, pipe_0[2*`DWIDTH-1:`DWIDTH], pipe_0[`DWIDTH-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]) ; + + // Perform (unsigned) mantissa multiplication + FPMult_ExecuteModule ExecuteModule(pipe_1[3*`MANTISSA+`EXPONENT*2+7:2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7:2*`MANTISSA+7], pipe_1[2*`MANTISSA+6:5], pipe_1[2*`MANTISSA+2*`EXPONENT+6:2*`MANTISSA+`EXPONENT+7], pipe_1[2*`MANTISSA+`EXPONENT+6:2*`MANTISSA+7], pipe_1[2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7], Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0], GRS) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + FPMult_NormalizeModule NormalizeModule(pipe_2[`MANTISSA-1:0], pipe_2[`MANTISSA+`EXPONENT:`MANTISSA], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + //FPMult_RoundModule RoundModule(pipe_3[47:24], pipe_3[23:0], pipe_3[65:57], pipe_3[56:48], pipe_3[66], pipe_3[67], pipe_3[72:68], Z_int[31:0], Flags_int[4:0]) ; + FPMult_RoundModule RoundModule(pipe_3[2*`MANTISSA+1:`MANTISSA+1], pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+2*`EXPONENT+3:2*`MANTISSA+`EXPONENT+3], pipe_3[2*`MANTISSA+`EXPONENT+2:2*`MANTISSA+2], pipe_3[2*`MANTISSA+2*`EXPONENT+4], pipe_3[2*`MANTISSA+2*`EXPONENT+5], pipe_3[2*`MANTISSA+2*`EXPONENT+10:2*`MANTISSA+2*`EXPONENT+6], Z_int[`DWIDTH-1:0], Flags_int[4:0]) ; + + always @ (*) begin + if(rst) begin + pipe_0 = 0; + pipe_1 = 0; + pipe_2 = 0; + pipe_3 = 0; + pipe_4 = 0; + end + else begin + /* PIPE 0 + [63:32] A + [31:0] B + */ + pipe_0 = {a, b} ; + + /* PIPE 1 + [70] Sa + [69] Sb + [68:61] Ea + [60:53] Eb + [52:5] Mp + [4:0] InputExc + */ + //pipe_1 <= {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[`MANTISSA_MUL_SPLIT_LSB-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA-1:0], InputExc[4:0]} ; + pipe_1 = {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[8:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]} ; + /* PIPE 2 + [38:34] InputExc + [33] GRS + [32] Sp + [31:23] NormE + [22:0] NormM + */ + pipe_2 = {pipe_1[4:0], GRS, Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0]} ; + /* PIPE 3 + [72:68] InputExc + [67] GRS + [66] Sp + [65:57] RoundE + [56:48] RoundEP + [47:24] RoundM + [23:0] RoundMP + */ + pipe_3 = {pipe_2[`EXPONENT+`MANTISSA+7:`EXPONENT+`MANTISSA+1], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]} ; + /* PIPE 4 + [36:5] Z + [4:0] Flags + */ + pipe_4 = {Z_int[`DWIDTH-1:0], Flags_int[4:0]} ; + end + end + +endmodule + + +module FPMult_PrepModule ( + clk, + rst, + a, + b, + Sa, + Sb, + Ea, + Eb, + Mp, + InputExc + ); + + // Input ports + input clk ; + input rst ; + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [`EXPONENT-1:0] Ea ; // A's exponent + output [`EXPONENT-1:0] Eb ; // B's exponent + output [2*`MANTISSA+1:0] Mp ; // Mantissa product + output [4:0] InputExc ; // Input numbers are exceptions + + // Internal signals // If signal is high... + wire ANaN ; // A is a signalling NaN + wire BNaN ; // B is a signalling NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`MANTISSA-1:0] Ma; + wire [`MANTISSA-1:0] Mb; + + assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + + // Check for any exceptions and put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + //assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ; + + // Take input numbers apart + assign Sa = a[`DWIDTH-1] ; // A's sign + assign Sb = b[`DWIDTH-1] ; // B's sign + assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception + assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception +// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB]; + // assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB]; + + + + //assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ; + assign Mp = ({1'b1,a[`MANTISSA-1:0]}*{1'b1, b[`MANTISSA-1:0]}) ; + + + //We multiply part of the mantissa here + //Full mantissa of A + //Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B + // wire [`ACTUAL_MANTISSA-1:0] inp_A; + // wire [`ACTUAL_MANTISSA-1:0] inp_B; + // assign inp_A = {1'b1, Ma}; + // assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp)); +endmodule + + +module FPMult_ExecuteModule( + a, + b, + MpC, + Ea, + Eb, + Sa, + Sb, + Sp, + NormE, + NormM, + GRS + ); + + // Input ports + input [`MANTISSA-1:0] a ; + input [2*`EXPONENT:0] b ; + input [2*`MANTISSA+1:0] MpC ; + input [`EXPONENT-1:0] Ea ; // A's exponent + input [`EXPONENT-1:0] Eb ; // B's exponent + input Sa ; // A's sign + input Sb ; // B's sign + + // Output ports + output Sp ; // Product sign + output [`EXPONENT:0] NormE ; // Normalized exponent + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output GRS ; + + wire [2*`MANTISSA+1:0] Mp ; + + assign Sp = (Sa ^ Sb) ; // Equal signs give a positive product + + // wire [`ACTUAL_MANTISSA-1:0] inp_a; + // wire [`ACTUAL_MANTISSA-1:0] inp_b; + // assign inp_a = {1'b1, a}; + // assign inp_b = {{(`MANTISSA-`MANTISSA_MUL_SPLIT_LSB){1'b0}}, 1'b0, b}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_a), .B(inp_b), .TC(1'b0), .PRODUCT(Mp_temp)); + // DW01_add #(2*`ACTUAL_MANTISSA) u_add(.A(Mp_temp), .B(MpC<<`MANTISSA_MUL_SPLIT_LSB), .CI(1'b0), .SUM(Mp), .CO()); + + //assign Mp = (MpC<<(2*`EXPONENT+1)) + ({4'b0001, a[`MANTISSA-1:0]}*{1'b0, b[2*`EXPONENT:0]}) ; + assign Mp = MpC; + + + assign NormM = (Mp[2*`MANTISSA+1] ? Mp[2*`MANTISSA:`MANTISSA+1] : Mp[2*`MANTISSA-1:`MANTISSA]); // Check for overflow + assign NormE = (Ea + Eb + Mp[2*`MANTISSA+1]); // If so, increment exponent + + assign GRS = ((Mp[`MANTISSA]&(Mp[`MANTISSA+1]))|(|Mp[`MANTISSA-1:0])) ; + +endmodule + +module FPMult_NormalizeModule( + NormM, + NormE, + RoundE, + RoundEP, + RoundM, + RoundMP + ); + + // Input Ports + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input [`EXPONENT:0] NormE ; // Normalized exponent + + // Output Ports + output [`EXPONENT:0] RoundE ; + output [`EXPONENT:0] RoundEP ; + output [`MANTISSA:0] RoundM ; + output [`MANTISSA:0] RoundMP ; + + assign RoundE = NormE - 15 ; + assign RoundEP = NormE - 14 ; + assign RoundM = NormM ; + assign RoundMP = NormM ; + +endmodule + +module FPMult_RoundModule( + RoundM, + RoundMP, + RoundE, + RoundEP, + Sp, + GRS, + InputExc, + Z, + Flags + ); + + // Input Ports + input [`MANTISSA:0] RoundM ; // Normalized mantissa + input [`MANTISSA:0] RoundMP ; // Normalized exponent + input [`EXPONENT:0] RoundE ; // Normalized mantissa + 1 + input [`EXPONENT:0] RoundEP ; // Normalized exponent + 1 + input Sp ; // Product sign + input GRS ; + input [4:0] InputExc ; + + // Output Ports + output [`DWIDTH-1:0] Z ; // Final product + output [4:0] Flags ; + + // Internal Signals + wire [`EXPONENT:0] FinalE ; // Rounded exponent + wire [`MANTISSA:0] FinalM; + wire [`MANTISSA:0] PreShiftM; + + assign PreShiftM = GRS ? RoundMP : RoundM ; // Round up if R and (G or S) + + // Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow) + assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]) ; + + assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done + + assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]} ; // Putting the pieces together + assign Flags = InputExc[4:0]; + +endmodule + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Definition of a 16-bit floating point adder/subtractor +// This is a heavily modified version of: +// https://github.com/fbrosser/DSP48E1-FP/tree/master/src/FP_AddSub +// Original author: Fredrik Brosser +// Abridged by: Samidh Mehta +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// + +module FPAddSub( + clk, + rst, + a, + b, + operation, // 0 add, 1 sub + result, + flags + ); + + // Clock and reset + input clk ; // Clock signal + input rst ; // Reset (active high, resets pipeline registers) + + // Input ports + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + input operation ; // Operation select signal + + // Output ports + output [`DWIDTH-1:0] result ; // Result of the operation + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Pipeline Registers + //reg [79:0] pipe_1; // Pipeline register PreAlign->Align1 + reg [`DWIDTH*2+15:0] pipe_1; // Pipeline register PreAlign->Align1 + + //reg [67:0] pipe_2; // Pipeline register Align1->Align3 + reg [`MANTISSA*2+`EXPONENT+13:0] pipe_2; // Pipeline register Align1->Align3 + + //reg [76:0] pipe_3; 68 // Pipeline register Align1->Align3 + reg [`MANTISSA*2+`EXPONENT+14:0] pipe_3; // Pipeline register Align1->Align3 + + //reg [69:0] pipe_4; // Pipeline register Align3->Execute + reg [`MANTISSA*2+`EXPONENT+15:0] pipe_4; // Pipeline register Align3->Execute + + //reg [51:0] pipe_5; // Pipeline register Execute->Normalize + reg [`DWIDTH+`EXPONENT+11:0] pipe_5; // Pipeline register Execute->Normalize + + //reg [56:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + reg [`DWIDTH+`EXPONENT+16:0] pipe_6; // Pipeline register Nomalize->NormalizeShift1 + + //reg [56:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + reg [`DWIDTH+`EXPONENT+16:0] pipe_7; // Pipeline register NormalizeShift2->NormalizeShift3 + + //reg [54:0] pipe_8; // Pipeline register NormalizeShift3->Round + reg [`EXPONENT*2+`MANTISSA+15:0] pipe_8; // Pipeline register NormalizeShift3->Round + + //reg [40:0] pipe_9; // Pipeline register NormalizeShift3->Round + reg [`DWIDTH+8:0] pipe_9; // Pipeline register NormalizeShift3->Round + + // Internal wires between modules + wire [`DWIDTH-2:0] Aout_0 ; // A - sign + wire [`DWIDTH-2:0] Bout_0 ; // B - sign + wire Opout_0 ; // A's sign + wire Sa_0 ; // A's sign + wire Sb_0 ; // B's sign + wire MaxAB_1 ; // Indicates the larger of A and B(0/A, 1/B) + wire [`EXPONENT-1:0] CExp_1 ; // Common Exponent + wire [4:0] Shift_1 ; // Number of steps to smaller mantissa shift right (align) + wire [`MANTISSA-1:0] Mmax_1 ; // Larger mantissa + wire [4:0] InputExc_0 ; // Input numbers are exceptions + wire [9:0] ShiftDet_0 ; + wire [`MANTISSA-1:0] MminS_1 ; // Smaller mantissa after 0/16 shift + wire [`MANTISSA:0] MminS_2 ; // Smaller mantissa after 0/4/8/12 shift + wire [`MANTISSA:0] Mmin_3 ; // Smaller mantissa after 0/1/2/3 shift + wire [`DWIDTH:0] Sum_4 ; + wire PSgn_4 ; + wire Opr_4 ; + wire [4:0] Shift_5 ; // Number of steps to shift sum left (normalize) + wire [`DWIDTH:0] SumS_5 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_6 ; // Sum after 0/16 shift + wire [`DWIDTH:0] SumS_7 ; // Sum after 0/16 shift + wire [`MANTISSA-1:0] NormM_8 ; // Normalized mantissa + wire [`EXPONENT:0] NormE_8; // Adjusted exponent + wire ZeroSum_8 ; // Zero flag + wire NegE_8 ; // Flag indicating negative exponent + wire R_8 ; // Round bit + wire S_8 ; // Final sticky bit + wire FG_8 ; // Final sticky bit + wire [`DWIDTH-1:0] P_int ; + wire EOF ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_PrealignModule PrealignModule + ( // Inputs + a, b, operation, + // Outputs + Sa_0, Sb_0, ShiftDet_0[9:0], InputExc_0[4:0], Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Opout_0) ; + + // Prepare the operands for alignment and check for exceptions + FPAddSub_AlignModule AlignModule + ( // Inputs + pipe_1[14+2*`DWIDTH:16+`DWIDTH], pipe_1[15+`DWIDTH:17], pipe_1[14:5], + // Outputs + CExp_1[`EXPONENT-1:0], MaxAB_1, Shift_1[4:0], MminS_1[`MANTISSA-1:0], Mmax_1[`MANTISSA-1:0]) ; + + // Alignment Shift Stage 1 + FPAddSub_AlignShift1 AlignShift1 + ( // Inputs + pipe_2[`MANTISSA-1:0], pipe_2[2*`MANTISSA+9:2*`MANTISSA+7], + // Outputs + MminS_2[`MANTISSA:0]) ; + + // Alignment Shift Stage 3 and compution of guard and sticky bits + FPAddSub_AlignShift2 AlignShift2 + ( // Inputs + pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+7:2*`MANTISSA+6], + // Outputs + Mmin_3[`MANTISSA:0]) ; + + // Perform mantissa addition + FPAddSub_ExecutionModule ExecutionModule + ( // Inputs + pipe_4[`MANTISSA*2+5:`MANTISSA+6], pipe_4[`MANTISSA:0], pipe_4[`MANTISSA*2+`EXPONENT+13], pipe_4[`MANTISSA*2+`EXPONENT+12], pipe_4[`MANTISSA*2+`EXPONENT+11], pipe_4[`MANTISSA*2+`EXPONENT+14], + // Outputs + Sum_4[`DWIDTH:0], PSgn_4, Opr_4) ; + + // Prepare normalization of result + FPAddSub_NormalizeModule NormalizeModule + ( // Inputs + pipe_5[`DWIDTH:0], + // Outputs + SumS_5[`DWIDTH:0], Shift_5[4:0]) ; + + // Normalization Shift Stage 1 + FPAddSub_NormalizeShift1 NormalizeShift1 + ( // Inputs + pipe_6[`DWIDTH:0], pipe_6[`DWIDTH+`EXPONENT+14:`DWIDTH+`EXPONENT+11], + // Outputs + SumS_7[`DWIDTH:0]) ; + + // Normalization Shift Stage 3 and final guard, sticky and round bits + FPAddSub_NormalizeShift2 NormalizeShift2 + ( // Inputs + pipe_7[`DWIDTH:0], pipe_7[`DWIDTH+`EXPONENT+5:`DWIDTH+6], pipe_7[`DWIDTH+`EXPONENT+15:`DWIDTH+`EXPONENT+11], + // Outputs + NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8, FG_8) ; + + // Round and put result together + FPAddSub_RoundModule RoundModule + ( // Inputs + pipe_8[3], pipe_8[4+`EXPONENT:4], pipe_8[`EXPONENT+`MANTISSA+4:5+`EXPONENT], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT*2+`MANTISSA+15], pipe_8[`EXPONENT*2+`MANTISSA+12], pipe_8[`EXPONENT*2+`MANTISSA+11], pipe_8[`EXPONENT*2+`MANTISSA+14], pipe_8[`EXPONENT*2+`MANTISSA+10], + // Outputs + P_int[`DWIDTH-1:0], EOF) ; + + // Check for exceptions + FPAddSub_ExceptionModule Exceptionmodule + ( // Inputs + pipe_9[8+`DWIDTH:9], pipe_9[8], pipe_9[7], pipe_9[6], pipe_9[5:1], pipe_9[0], + // Outputs + result[`DWIDTH-1:0], flags[4:0]) ; + + always @ (*) begin + if(rst) begin + pipe_1 = 0; + pipe_2 = 0; + pipe_3 = 0; + pipe_4 = 0; + pipe_5 = 0; + pipe_6 = 0; + pipe_7 = 0; + pipe_8 = 0; + pipe_9 = 0; + end + else begin + + pipe_1 = {Opout_0, Aout_0[`DWIDTH-2:0], Bout_0[`DWIDTH-2:0], Sa_0, Sb_0, ShiftDet_0[9:0], InputExc_0[4:0]} ; + // PIPE_2 : + //[67] operation + //[66] Sa_0 + //[65] Sb_0 + //[64] MaxAB_0 + //[63:56] CExp_0 + //[55:51] Shift_0 + //[50:28] Mmax_0 + //[27:23] InputExc_0 + //[22:0] MminS_1 + // + pipe_2 = {pipe_1[`DWIDTH*2+15], pipe_1[16:15], MaxAB_1, CExp_1[`EXPONENT-1:0], Shift_1[4:0], Mmax_1[`MANTISSA-1:0], pipe_1[4:0], MminS_1[`MANTISSA-1:0]} ; + // PIPE_3 : + //[68] operation + //[67] Sa_0 + //[66] Sb_0 + //[65] MaxAB_0 + //[64:57] CExp_0 + //[56:52] Shift_0 + //[51:29] Mmax_0 + //[28:24] InputExc_0 + //[23:0] MminS_1 + // + pipe_3 = {pipe_2[`MANTISSA*2+`EXPONENT+13:`MANTISSA], MminS_2[`MANTISSA:0]} ; + // PIPE_4 : + //[68] operation + //[67] Sa_0 + //[66] Sb_0 + //[65] MaxAB_0 + //[64:57] CExp_0 + //[56:52] Shift_0 + //[51:29] Mmax_0 + //[28:24] InputExc_0 + //[23:0] Mmin_3 + // + pipe_4 = {pipe_3[`MANTISSA*2+`EXPONENT+14:`MANTISSA+1], Mmin_3[`MANTISSA:0]} ; + // PIPE_5 : + //[51] operation + //[50] PSgn_4 + //[49] Opr_4 + //[48] Sa_0 + //[47] Sb_0 + //[46] MaxAB_0 + //[45:38] CExp_0 + //[37:33] InputExc_0 + //[32:0] Sum_4 + // + pipe_5 = {pipe_4[2*`MANTISSA+`EXPONENT+14], PSgn_4, Opr_4, pipe_4[2*`MANTISSA+`EXPONENT+13:2*`MANTISSA+11], pipe_4[`MANTISSA+5:`MANTISSA+1], Sum_4[`DWIDTH:0]} ; + // PIPE_6 : + //[56] operation + //[55:51] Shift_5 + //[50] PSgn_4 + //[49] Opr_4 + //[48] Sa_0 + //[47] Sb_0 + //[46] MaxAB_0 + //[45:38] CExp_0 + //[37:33] InputExc_0 + //[32:0] Sum_4 + // + pipe_6 = {pipe_5[`EXPONENT+`EXPONENT+11], Shift_5[4:0], pipe_5[`DWIDTH+`EXPONENT+10:`DWIDTH+1], SumS_5[`DWIDTH:0]} ; + // pipe_7 : + //[56] operation + //[55:51] Shift_5 + //[50] PSgn_4 + //[49] Opr_4 + //[48] Sa_0 + //[47] Sb_0 + //[46] MaxAB_0 + //[45:38] CExp_0 + //[37:33] InputExc_0 + //[32:0] Sum_4 + // + pipe_7 = {pipe_6[`DWIDTH+`EXPONENT+16:`DWIDTH+1], SumS_7[`DWIDTH:0]} ; + // pipe_8: + //[54] FG_8 + //[53] operation + //[52] PSgn_4 + //[51] Sa_0 + //[50] Sb_0 + //[49] MaxAB_0 + //[48:41] CExp_0 + //[40:36] InputExc_8 + //[35:13] NormM_8 + //[12:4] NormE_8 + //[3] ZeroSum_8 + //[2] NegE_8 + //[1] R_8 + //[0] S_8 + // + pipe_8 = {FG_8, pipe_7[`DWIDTH+`EXPONENT+16], pipe_7[`DWIDTH+`EXPONENT+10], pipe_7[`DWIDTH+`EXPONENT+8:`DWIDTH+1], NormM_8[`MANTISSA-1:0], NormE_8[`EXPONENT:0], ZeroSum_8, NegE_8, R_8, S_8} ; + // pipe_9: + //[40:9] P_int + //[8] NegE_8 + //[7] R_8 + //[6] S_8 + //[5:1] InputExc_8 + //[0] EOF + // + pipe_9 = {P_int[`DWIDTH-1:0], pipe_8[2], pipe_8[1], pipe_8[0], pipe_8[`EXPONENT+`MANTISSA+9:`EXPONENT+`MANTISSA+5], EOF} ; + end + end + +endmodule + +// Description: The pre-alignment module is responsible for taking the inputs +// apart and checking the parts for exceptions. +// The exponent difference is also calculated in this module. + +module FPAddSub_PrealignModule( + A, + B, + operation, + Sa, + Sb, + ShiftDet, + InputExc, + Aout, + Bout, + Opout + ); + + // Input ports + input [`DWIDTH-1:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] B ; // Input B, a 32-bit floating point number + input operation ; + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [9:0] ShiftDet ; + output [4:0] InputExc ; // Input numbers are exceptions + output [`DWIDTH-2:0] Aout ; + output [`DWIDTH-2:0] Bout ; + output Opout ; + + // Internal signals // If signal is high... + wire ANaN ; // A is a NaN (Not-a-Number) + wire BNaN ; // B is a NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`EXPONENT-1:0] DAB ; // ExpA - ExpB + wire [`EXPONENT-1:0] DBA ; // ExpB - ExpA + + assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity + + // Put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + + //assign DAB = (A[30:23] - B[30:23]) ; + //assign DBA = (B[30:23] - A[30:23]) ; + assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1) ; + assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1) ; + + assign Sa = A[`DWIDTH-1] ; // A's sign bit + assign Sb = B[`DWIDTH-1] ; // B's sign bit + assign ShiftDet = {DBA[4:0], DAB[4:0]} ; // Shift data + assign Opout = operation ; + assign Aout = A[`DWIDTH-2:0] ; + assign Bout = B[`DWIDTH-2:0] ; + +endmodule + +// Description: The alignment module determines the larger input operand and +// sets the mantissas, shift and common exponent accordingly. + +module FPAddSub_AlignModule ( + A, + B, + ShiftDet, + CExp, + MaxAB, + Shift, + Mmin, + Mmax + ); + + // Input ports + input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number + input [`DWIDTH-2:0] B ; // Input B, a 32-bit floating point number + input [9:0] ShiftDet ; + + // Output ports + output [`EXPONENT-1:0] CExp ; // Common Exponent + output MaxAB ; // Incidates larger of A and B (0/A, 1/B) + output [4:0] Shift ; // Number of steps to smaller mantissa shift right + output [`MANTISSA-1:0] Mmin ; // Smaller mantissa + output [`MANTISSA-1:0] Mmax ; // Larger mantissa + + // Internal signals + //wire BOF ; // Check for shifting overflow if B is larger + //wire AOF ; // Check for shifting overflow if A is larger + + assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]) ; + //assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits + //assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits + + // Determine final shift value + //assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ; + + assign Shift = MaxAB ? ShiftDet[9:5] : ShiftDet[4:0] ; + + // Take out smaller mantissa and append shift space + assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0] ; + + // Take out larger mantissa + assign Mmax = MaxAB ? B[`MANTISSA-1:0]: A[`MANTISSA-1:0] ; + + // Common exponent + assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]) ; + +endmodule + +// Description: Alignment shift stage 1, performs 16|12|8|4 shift + +module FPAddSub_AlignShift1( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`MANTISSA-1:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [2:0] Shift ; // Shift amount + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + // Internal signals + reg [`MANTISSA:0] Lvl1; + reg [`MANTISSA:0] Lvl2; + wire [2*`MANTISSA+1:0] Stage1; + integer i; // Loop variable + + always @(*) begin + // Rotate by 16? + //Lvl1 <= Shift[2] ? {17'b00000000000000001, MminP[22:16]} : {1'b1, MminP}; + Lvl1 <= Shift[2] ? {11'b0000000000} : {1'b1, MminP}; + + end + + assign Stage1 = { Lvl1, Lvl1}; + + always @(*) begin // Rotate {0 | 4 | 8 | 12} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl2 <= Stage1[`MANTISSA:0]; + // Rotate by 4 + 2'b01: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+4]; end /*Lvl2[`MANTISSA:`MANTISSA-3] <= 0;*/ end + // Rotate by 8 + 2'b10: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+8]; end /*Lvl2[`MANTISSA:`MANTISSA-7] <= 0;*/ end + // Rotate by 12 + 2'b11: Lvl2[`MANTISSA: 0] <= 0; + //2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end + endcase + end + + // Assign output to next shift stage + assign Mmin = Lvl2; + +endmodule + +// Description: Alignment shift stage 2, performs 3|2|1 shift + +module FPAddSub_AlignShift2( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`MANTISSA:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [1:0] Shift ; // Shift amount + + // Output ports + output [`MANTISSA:0] Mmin ; // The smaller mantissa + + // Internal Signal + reg [`MANTISSA:0] Lvl3; + wire [2*`MANTISSA+1:0] Stage2; + integer j; // Loop variable + + assign Stage2 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: Lvl3 <= Stage2[`MANTISSA:0]; + // Rotate by 1 + 2'b01: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+1]; end /*Lvl3[`MANTISSA] <= 0; */end + // Rotate by 2 + 2'b10: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+2]; end /*Lvl3[`MANTISSA:`MANTISSA-1] <= 0;*/ end + // Rotate by 3 + 2'b11: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+3]; end /*Lvl3[`MANTISSA:`MANTISSA-2] <= 0;*/ end + endcase + end + + // Assign output + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + +// Description: Module that executes the addition or subtraction on mantissas. + +module FPAddSub_ExecutionModule( + Mmax, + Mmin, + Sa, + Sb, + MaxAB, + OpMode, + Sum, + PSgn, + Opr + ); + + // Input ports + input [`MANTISSA-1:0] Mmax ; // The larger mantissa + input [`MANTISSA:0] Mmin ; // The smaller mantissa + input Sa ; // Sign bit of larger number + input Sb ; // Sign bit of smaller number + input MaxAB ; // Indicates the larger number (0/A, 1/B) + input OpMode ; // Operation to be performed (0/Add, 1/Sub) + + // Output ports + output [`DWIDTH:0] Sum ; // The result of the operation + output PSgn ; // The sign for the result + output Opr ; // The effective (performed) operation + + assign Opr = (OpMode^Sa^Sb); // Resolve sign to determine operation + + // Perform effective operation + assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, 5'b00000} - {Mmin, 5'b00000}) : ({1'b1, Mmax, 5'b00000} + {Mmin, 5'b00000}) ; + + // Assign result sign + assign PSgn = (MaxAB ? Sb : Sa) ; + +endmodule + +// Description: Determine the normalization shift amount and perform 16-shift + +module FPAddSub_NormalizeModule( + Sum, + Mmin, + Shift + ); + + // Input ports + input [`DWIDTH:0] Sum ; // Mantissa sum including hidden 1 and GRS + + // Output ports + output [`DWIDTH:0] Mmin ; // Mantissa after 16|0 shift + output [4:0] Shift ; // Shift amount + + // Determine normalization shift amount by finding leading nought + assign Shift = ( + Sum[16] ? 5'b00000 : + Sum[15] ? 5'b00001 : + Sum[14] ? 5'b00010 : + Sum[13] ? 5'b00011 : + Sum[12] ? 5'b00100 : + Sum[11] ? 5'b00101 : + Sum[10] ? 5'b00110 : + Sum[9] ? 5'b00111 : + Sum[8] ? 5'b01000 : + Sum[7] ? 5'b01001 : + Sum[6] ? 5'b01010 : + Sum[5] ? 5'b01011 : + Sum[4] ? 5'b01100 : 5'b01101 + // Sum[19] ? 5'b01101 : + // Sum[18] ? 5'b01110 : + // Sum[17] ? 5'b01111 : + // Sum[16] ? 5'b10000 : + // Sum[15] ? 5'b10001 : + // Sum[14] ? 5'b10010 : + // Sum[13] ? 5'b10011 : + // Sum[12] ? 5'b10100 : + // Sum[11] ? 5'b10101 : + // Sum[10] ? 5'b10110 : + // Sum[9] ? 5'b10111 : + // Sum[8] ? 5'b11000 : + // Sum[7] ? 5'b11001 : 5'b11010 + ); + + reg [`DWIDTH:0] Lvl1; + + always @(*) begin + // Rotate by 16? + Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum; + end + + // Assign outputs + assign Mmin = Lvl1; // Take out smaller mantissa + +endmodule + +// Description: Normalization shift stage 1, performs 12|8|4|3|2|1|0 shift + +module FPAddSub_NormalizeShift1( + MminP, + Shift, + Mmin + ); + + // Input ports + input [`DWIDTH:0] MminP ; // Smaller mantissa after 16|12|8|4 shift + input [3:0] Shift ; // Shift amount + + // Output ports + output [`DWIDTH:0] Mmin ; // The smaller mantissa + + reg [`DWIDTH:0] Lvl2; + wire [2*`DWIDTH+1:0] Stage1; + reg [`DWIDTH:0] Lvl3; + wire [2*`DWIDTH+1:0] Stage2; + integer i; // Loop variable + + assign Stage1 = {MminP, MminP}; + + always @(*) begin // Rotate {0 | 4 | 8 | 12} bits + case (Shift[3:2]) + // Rotate by 0 + 2'b00: //Lvl2 <= Stage1[`DWIDTH:0]; + begin Lvl2 = Stage1[`DWIDTH:0]; end + // Rotate by 4 + 2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-4]; end Lvl2[3:0] <= 0; end + begin Lvl2[`DWIDTH: (`DWIDTH-4)] = Stage1[3:0]; Lvl2[`DWIDTH-4-1:0] = Stage1[`DWIDTH-4]; end + // Rotate by 8 + 2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-8]; end Lvl2[7:0] <= 0; end + begin Lvl2[`DWIDTH: (`DWIDTH-8)] = Stage1[3:0]; Lvl2[`DWIDTH-8-1:0] = Stage1[`DWIDTH-8]; end + // Rotate by 12 + 2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end + begin Lvl2[`DWIDTH: (`DWIDTH-12)] = Stage1[3:0]; Lvl2[`DWIDTH-12-1:0] = Stage1[`DWIDTH-12]; end + endcase + end + + assign Stage2 = {Lvl2, Lvl2}; + + always @(*) begin // Rotate {0 | 1 | 2 | 3} bits + case (Shift[1:0]) + // Rotate by 0 + 2'b00: //Lvl3 <= Stage2[`DWIDTH:0]; + begin Lvl3 = Stage2[`DWIDTH:0]; end + // Rotate by 1 + 2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-1]; end Lvl3[0] <= 0; end + begin Lvl3[`DWIDTH: (`DWIDTH-1)] = Stage2[3:0]; Lvl3[`DWIDTH-1-1:0] = Stage2[`DWIDTH-1]; end + // Rotate by 2 + 2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-2]; end Lvl3[1:0] <= 0; end + begin Lvl3[`DWIDTH: (`DWIDTH-2)] = Stage2[3:0]; Lvl3[`DWIDTH-2-1:0] = Stage2[`DWIDTH-2]; end + // Rotate by 3 + 2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end + begin Lvl3[`DWIDTH: (`DWIDTH-3)] = Stage2[3:0]; Lvl3[`DWIDTH-3-1:0] = Stage2[`DWIDTH-3]; end + endcase + end + + // Assign outputs + assign Mmin = Lvl3; // Take out smaller mantissa + +endmodule + +// Description: Normalization shift stage 2, calculates post-normalization +// mantissa and exponent, as well as the bits used in rounding + +module FPAddSub_NormalizeShift2( + PSSum, + CExp, + Shift, + NormM, + NormE, + ZeroSum, + NegE, + R, + S, + FG + ); + + // Input ports + input [`DWIDTH:0] PSSum ; // The Pre-Shift-Sum + input [`EXPONENT-1:0] CExp ; + input [4:0] Shift ; // Amount to be shifted + + // Output ports + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output [`EXPONENT:0] NormE ; // Adjusted exponent + output ZeroSum ; // Zero flag + output NegE ; // Flag indicating negative exponent + output R ; // Round bit + output S ; // Final sticky bit + output FG ; + + // Internal signals + wire MSBShift ; // Flag indicating that a second shift is needed + wire [`EXPONENT:0] ExpOF ; // MSB set in sum indicates overflow + wire [`EXPONENT:0] ExpOK ; // MSB not set, no adjustment + + // Calculate normalized exponent and mantissa, check for all-zero sum + assign MSBShift = PSSum[`DWIDTH] ; // Check MSB in unnormalized sum + assign ZeroSum = ~|PSSum ; // Check for all zero sum + assign ExpOK = CExp - Shift ; // Adjust exponent for new normalized mantissa + assign NegE = ExpOK[`EXPONENT] ; // Check for exponent overflow + assign ExpOF = CExp - Shift + 1'b1 ; // If MSB set, add one to exponent(x2) + assign NormE = MSBShift ? ExpOF : ExpOK ; // Check for exponent overflow + assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1] ; // The new, normalized mantissa + + // Also need to compute sticky and round bits for the rounding stage + assign FG = PSSum[`EXPONENT] ; + assign R = PSSum[`EXPONENT-1] ; + assign S = |PSSum[`EXPONENT-2:0] ; + +endmodule + +// Description: Performs 'Round to nearest, tie to even'-rounding on the +// normalized mantissa according to the G, R, S bits. Calculates +// final result and checks for exponent overflow. + +module FPAddSub_RoundModule( + ZeroSum, + NormE, + NormM, + R, + S, + G, + Sa, + Sb, + Ctrl, + MaxAB, + Z, + EOF + ); + + // Input ports + input ZeroSum ; // Sum is zero + input [`EXPONENT:0] NormE ; // Normalized exponent + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input R ; // Round bit + input S ; // Sticky bit + input G ; + input Sa ; // A's sign bit + input Sb ; // B's sign bit + input Ctrl ; // Control bit (operation) + input MaxAB ; + + // Output ports + output [`DWIDTH-1:0] Z ; // Final result + output EOF ; + + // Internal signals + wire [`MANTISSA:0] RoundUpM ; // Rounded up sum with room for overflow + wire [`MANTISSA-1:0] RoundM ; // The final rounded sum + wire [`EXPONENT:0] RoundE ; // Rounded exponent (note extra bit due to poential overflow ) + wire RoundUp ; // Flag indicating that the sum should be rounded up + wire FSgn; + wire ExpAdd ; // May have to add 1 to compensate for overflow + wire RoundOF ; // Rounding overflow + + // The cases where we need to round upwards (= adding one) in Round to nearest, tie to even + assign RoundUp = (G & ((R | S) | NormM[0])) ; + + // Note that in the other cases (rounding down), the sum is already 'rounded' + assign RoundUpM = (NormM + 1) ; // The sum, rounded up by 1 + assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM) ; // Compute final mantissa + assign RoundOF = RoundUp & RoundUpM[`MANTISSA] ; // Check for overflow when rounding up + + // Calculate post-rounding exponent + assign ExpAdd = (RoundOF ? 1'b1 : 1'b0) ; // Add 1 to exponent to compensate for overflow + assign RoundE = ZeroSum ? 5'b00000 : (NormE + ExpAdd) ; // Final exponent + + // If zero, need to determine sign according to rounding + assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ; + + // Assign final result + assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]} ; + + // Indicate exponent overflow + assign EOF = RoundE[`EXPONENT]; + +endmodule + +// Description: Check the final result for exception conditions and set +// flags accordingly. + +module FPAddSub_ExceptionModule( + Z, + NegE, + R, + S, + InputExc, + EOF, + P, + Flags + ); + + // Input ports + input [`DWIDTH-1:0] Z ; // Final product + input NegE ; // Negative exponent? + input R ; // Round bit + input S ; // Sticky bit + input [4:0] InputExc ; // Exceptions in inputs A and B + input EOF ; + + // Output ports + output [`DWIDTH-1:0] P ; // Final result + output [4:0] Flags ; // Exception flags + + // Internal signals + wire Overflow ; // Overflow flag + wire Underflow ; // Underflow flag + wire DivideByZero ; // Divide-by-Zero flag (always 0 in Add/Sub) + wire Invalid ; // Invalid inputs or result + wire Inexact ; // Result is inexact because of rounding + + // Exception flags + + // Result is too big to be represented + assign Overflow = EOF | InputExc[1] | InputExc[0] ; + + // Result is too small to be represented + assign Underflow = NegE & (R | S); + + // Infinite result computed exactly from finite operands + assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0]; + + // Invalid inputs or operation + assign Invalid = |(InputExc[4:2]) ; + + // Inexact answer due to rounding, overflow or underflow + assign Inexact = (R | S) | Overflow | Underflow; + + // Put pieces together to form final result + assign P = Z ; + + // Collect exception flags + assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact} ; + +endmodule +`endif + + diff --git a/designs/koios/test/design.yaml b/designs/koios/test/design.yaml new file mode 100644 index 000000000..c427bbebd --- /dev/null +++ b/designs/koios/test/design.yaml @@ -0,0 +1 @@ +top: top diff --git a/designs/koios/test/test.v b/designs/koios/test/test.v new file mode 100644 index 000000000..72f607396 --- /dev/null +++ b/designs/koios/test/test.v @@ -0,0 +1,608 @@ +///////////////////////////////////////////////////////// +// Author: Aman Arora +///////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////// +// This is a dummy design used for verifying some modes +// of the complex dsp slice used in the architecture: +// k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml. +// This design is meant for regression testing. +// The design just contains a few blocks copied from other +// designs. +///////////////////////////////////////////////////////// + + +`define BFLOAT16 + +// IEEE Half Precision => EXPONENT = 5, MANTISSA = 10 +// BFLOAT16 => EXPONENT = 8, MANTISSA = 7 + +`ifdef BFLOAT16 +`define EXPONENT 8 +`define MANTISSA 7 +`else // for ieee half precision fp16 +`define EXPONENT 5 +`define MANTISSA 10 +`endif + +`define SIGN 1 +`define DWIDTH (`SIGN+`EXPONENT+`MANTISSA) + +module top( + input reset, + input clk, + input [`DWIDTH-1:0] a, + input [`DWIDTH-1:0] b, + output [`DWIDTH-1:0] out, + input [15:0] i_features_0, + input [7:0] i_weights_0, + input [15:0] i_features_1, + input [7:0] i_weights_1, + input [15:0] i_features_2, + input [7:0] i_weights_2, + input [15:0] i_features_3, + input [7:0] i_weights_3, + output [23:0] o_result +); + +seq_mul u_mul(.a(a), .b(b), .out(out), .reset(reset), .clk(clk)); + +dot_product_16_8_30_4 u_dp( + .clk(clk), + .i_reset(reset), + .i_features_0(i_features_0), + .i_weights_0(i_weights_0), + .i_features_1(i_features_1), + .i_weights_1(i_weights_1), + .i_features_2(i_features_2), + .i_weights_2(i_weights_2), + .i_features_3(i_features_3), + .i_weights_3(i_weights_3), + .o_result(o_result) +); + +endmodule + +module seq_mul(a, b, out, reset, clk); +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +input reset; +input clk; +output [`DWIDTH-1:0] out; + +reg [`DWIDTH-1:0] a_flopped; +reg [`DWIDTH-1:0] b_flopped; + +wire [`DWIDTH-1:0] mul_out_temp; +reg [`DWIDTH-1:0] mul_out_temp_reg; + +always @(posedge clk) begin + if (reset) begin + a_flopped <= 0; + b_flopped <= 0; + end else begin + a_flopped <= a; + b_flopped <= b; + end +end + +//assign mul_out_temp = a * b; +`ifdef complex_dsp +mult_fp_clk_16 mul_u1(.clk(clk), .a(a_flopped), .b(b_flopped), .out(mul_out_temp)); +`else +FPMult_16 u_FPMult (.clk(clk), .rst(1'b0), .a(a_flopped), .b(b_flopped), .result(mul_out_temp), .flags()); +`endif + +always @(posedge clk) begin + if (reset) begin + mul_out_temp_reg <= 0; + end else begin + mul_out_temp_reg <= mul_out_temp; + end +end + +assign out = mul_out_temp_reg; + +endmodule + +module dot_product_16_8_30_4 ( + input clk, + input i_reset, + input [15:0] i_features_0, + input [7:0] i_weights_0, + input [15:0] i_features_1, + input [7:0] i_weights_1, + input [15:0] i_features_2, + input [7:0] i_weights_2, + input [15:0] i_features_3, + input [7:0] i_weights_3, + output [23:0] o_result +); + +wire [63:0] chains_0; +wire [63:0] chains_1; +wire [23:0] res; +reg [15:0] f_pipeline_0_0; +reg [7:0] w_pipeline_0_0; +reg [15:0] f_pipeline_0_1; +reg [7:0] w_pipeline_0_1; +reg [15:0] f_pipeline_1_0; +reg [7:0] w_pipeline_1_0; +reg [15:0] f_pipeline_1_1; +reg [7:0] w_pipeline_1_1; +reg [15:0] f_pipeline_2_0; +reg [7:0] w_pipeline_2_0; +reg [15:0] f_pipeline_2_1; +reg [7:0] w_pipeline_2_1; +reg [15:0] f_pipeline_3_0; +reg [7:0] w_pipeline_3_0; +reg [15:0] f_pipeline_3_1; +reg [7:0] w_pipeline_3_1; +reg r_pipeline_0; +reg r_pipeline_1; + +always @ (posedge clk) begin + r_pipeline_0 <= i_reset; + if(i_reset == 1'b1) begin + f_pipeline_0_0 <= 0; + w_pipeline_0_0 <= 0; + f_pipeline_1_0 <= 0; + w_pipeline_1_0 <= 0; + f_pipeline_2_0 <= 0; + w_pipeline_2_0 <= 0; + f_pipeline_3_0 <= 0; + w_pipeline_3_0 <= 0; + f_pipeline_0_1 <= 0; + w_pipeline_0_1 <= 0; + f_pipeline_1_1 <= 0; + w_pipeline_1_1 <= 0; + f_pipeline_2_1 <= 0; + w_pipeline_2_1 <= 0; + f_pipeline_3_1 <= 0; + w_pipeline_3_1 <= 0; + r_pipeline_1 <= 1'b1; + end else begin + f_pipeline_0_0 <= i_features_0; + w_pipeline_0_0 <= i_weights_0; + f_pipeline_1_0 <= i_features_1; + w_pipeline_1_0 <= i_weights_1; + f_pipeline_2_0 <= i_features_2; + w_pipeline_2_0 <= i_weights_2; + f_pipeline_3_0 <= i_features_3; + w_pipeline_3_0 <= i_weights_3; + r_pipeline_1 <= r_pipeline_0; + f_pipeline_0_1 <= f_pipeline_0_0; + w_pipeline_0_1 <= w_pipeline_0_0; + f_pipeline_1_1 <= f_pipeline_1_0; + w_pipeline_1_1 <= w_pipeline_1_0; + f_pipeline_2_1 <= f_pipeline_2_0; + w_pipeline_2_1 <= w_pipeline_2_0; + f_pipeline_3_1 <= f_pipeline_3_0; + w_pipeline_3_1 <= w_pipeline_3_0; + end +end + +wire [23:0] dummy_res_0; +dsp_block_16_8 dsp_block_16_8_false_inst_0 ( + .clk(clk), + .ena(1'b1), + .aclr(1'b0), + .ax(f_pipeline_0_0), + .ay(w_pipeline_0_0), + .bx(f_pipeline_1_0), + .by(w_pipeline_1_0), + .chainin(64'd0), + .chainout(chains_0), + .resulta(dummy_res_0) +); + +dsp_block_16_8 dsp_block_16_8_true_inst_2 ( + .clk(clk), + .ena(1'b1), + .aclr(r_pipeline_1), + .ax(f_pipeline_2_1), + .ay(w_pipeline_2_1), + .bx(f_pipeline_3_1), + .by(w_pipeline_3_1), + .chainin(chains_0), + .chainout(chains_1), + .resulta(res) +); + +assign o_result = res; + +endmodule + +module dsp_block_16_8 ( + input clk, + input ena, + input aclr, + input [15:0] ax, + input [7:0] ay, + input [15:0] bx, + input [7:0] by, + input [63:0] chainin, + output [63:0] chainout, + output [23:0] resulta +); + +wire [10:0] mode; +assign mode = 12'b1010_1010_0110; + +`ifdef complex_dsp +int_sop_2 mac_component ( + .mode_sigs(mode), + .clk(clk), + .reset(aclr), + .ax(ax), + .ay(ay), + .bx(bx), + .by(by), + .chainin(chainin), + .result(resulta), + .chainout(chainout) +); +`else +reg [15:0] ax_reg; +reg [7:0] ay_reg; +reg [15:0] bx_reg; +reg [7:0] by_reg; +reg [23:0] resulta; +always @(posedge clk) begin + if(aclr) begin + resulta <= 0; + ax_reg <= 0; + ay_reg <= 0; + bx_reg <= 0; + by_reg <= 0; + end + else begin + ax_reg <= ax; + ay_reg <= ay; + bx_reg <= bx; + by_reg <= by; + resulta <= ax_reg * ay_reg + bx_reg * by_reg + chainin; + end +end +assign chainout = {40'b0, resulta}; +`endif +endmodule + +`ifndef complex_dsp + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// Floating point 16-bit multiplier +// This is a heavily modified version of: +// https://github.com/fbrosser/DSP48E1-FP/tree/master/src/FPMult +// Original author: Fredrik Brosser +// Abridged by: Samidh Mehta +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// + +module FPMult_16( + clk, + rst, + a, + b, + result, + flags + ); + + // Input Ports + input clk ; // Clock + input rst ; // Reset signal + input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number + + // Output ports + output [`DWIDTH-1:0] result ; // Product, result of the operation, 32-bit FP number + output [4:0] flags ; // Flags indicating exceptions according to IEEE754 + + // Internal signals + wire [`DWIDTH-1:0] Z_int ; // Product, result of the operation, 32-bit FP number + wire [4:0] Flags_int ; // Flags indicating exceptions according to IEEE754 + + wire Sa ; // A's sign + wire Sb ; // B's sign + wire Sp ; // Product sign + wire [`EXPONENT-1:0] Ea ; // A's exponent + wire [`EXPONENT-1:0] Eb ; // B's exponent + wire [2*`MANTISSA+1:0] Mp ; // Product mantissa + wire [4:0] InputExc ; // Exceptions in inputs + wire [`MANTISSA-1:0] NormM ; // Normalized mantissa + wire [`EXPONENT:0] NormE ; // Normalized exponent + wire [`MANTISSA:0] RoundM ; // Normalized mantissa + wire [`EXPONENT:0] RoundE ; // Normalized exponent + wire [`MANTISSA:0] RoundMP ; // Normalized mantissa + wire [`EXPONENT:0] RoundEP ; // Normalized exponent + wire GRS ; + + //reg [63:0] pipe_0; // Pipeline register Input->Prep + reg [2*`DWIDTH-1:0] pipe_0; // Pipeline register Input->Prep + + //reg [92:0] pipe_1; // Pipeline register Prep->Execute + //reg [3*`MANTISSA+2*`EXPONENT+7:0] pipe_1; // Pipeline register Prep->Execute + reg [3*`MANTISSA+2*`EXPONENT+18:0] pipe_1; + + //reg [38:0] pipe_2; // Pipeline register Execute->Normalize + reg [`MANTISSA+`EXPONENT+7:0] pipe_2; // Pipeline register Execute->Normalize + + //reg [72:0] pipe_3; // Pipeline register Normalize->Round + reg [2*`MANTISSA+2*`EXPONENT+10:0] pipe_3; // Pipeline register Normalize->Round + + //reg [36:0] pipe_4; // Pipeline register Round->Output + reg [`DWIDTH+4:0] pipe_4; // Pipeline register Round->Output + + assign result = pipe_4[`DWIDTH+4:5] ; + assign flags = pipe_4[4:0] ; + + // Prepare the operands for alignment and check for exceptions + FPMult_PrepModule PrepModule(clk, rst, pipe_0[2*`DWIDTH-1:`DWIDTH], pipe_0[`DWIDTH-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]) ; + + // Perform (unsigned) mantissa multiplication + FPMult_ExecuteModule ExecuteModule(pipe_1[3*`MANTISSA+`EXPONENT*2+7:2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7:2*`MANTISSA+7], pipe_1[2*`MANTISSA+6:5], pipe_1[2*`MANTISSA+2*`EXPONENT+6:2*`MANTISSA+`EXPONENT+7], pipe_1[2*`MANTISSA+`EXPONENT+6:2*`MANTISSA+7], pipe_1[2*`MANTISSA+2*`EXPONENT+8], pipe_1[2*`MANTISSA+2*`EXPONENT+7], Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0], GRS) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + FPMult_NormalizeModule NormalizeModule(pipe_2[`MANTISSA-1:0], pipe_2[`MANTISSA+`EXPONENT:`MANTISSA], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]) ; + + // Round result and if necessary, perform a second (post-rounding) normalization step + //FPMult_RoundModule RoundModule(pipe_3[47:24], pipe_3[23:0], pipe_3[65:57], pipe_3[56:48], pipe_3[66], pipe_3[67], pipe_3[72:68], Z_int[31:0], Flags_int[4:0]) ; + FPMult_RoundModule RoundModule(pipe_3[2*`MANTISSA+1:`MANTISSA+1], pipe_3[`MANTISSA:0], pipe_3[2*`MANTISSA+2*`EXPONENT+3:2*`MANTISSA+`EXPONENT+3], pipe_3[2*`MANTISSA+`EXPONENT+2:2*`MANTISSA+2], pipe_3[2*`MANTISSA+2*`EXPONENT+4], pipe_3[2*`MANTISSA+2*`EXPONENT+5], pipe_3[2*`MANTISSA+2*`EXPONENT+10:2*`MANTISSA+2*`EXPONENT+6], Z_int[`DWIDTH-1:0], Flags_int[4:0]) ; + +//adding always@ (*) instead of posedge clock to make design combinational + always @ (posedge clk) begin + if(rst) begin + pipe_0 <= 0; + pipe_1 <= 0; + pipe_2 <= 0; + pipe_3 <= 0; + pipe_4 <= 0; + end + else begin + /* PIPE 0 + [2*`DWIDTH-1:`DWIDTH] A + [`DWIDTH-1:0] B + */ + pipe_0 <= {a, b} ; + + + /* PIPE 1 + [2*`EXPONENT+3*`MANTISSA + 18: 2*`EXPONENT+2*`MANTISSA + 18] //pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH] , mantissa of A + [2*`EXPONENT+2*`MANTISSA + 17 :2*`EXPONENT+2*`MANTISSA + 9] // pipe_0[8:0] + [2*`EXPONENT+2*`MANTISSA + 8] Sa + [2*`EXPONENT+2*`MANTISSA + 7] Sb + [2*`EXPONENT+2*`MANTISSA + 6:`EXPONENT+2*`MANTISSA+7] Ea + [`EXPONENT +2*`MANTISSA+6:2*`MANTISSA+7] Eb + [2*`MANTISSA+1+5:5] Mp + [4:0] InputExc + */ + //pipe_1 <= {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[`MANTISSA_MUL_SPLIT_LSB-1:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA-1:0], InputExc[4:0]} ; + pipe_1 <= {pipe_0[`DWIDTH+`MANTISSA-1:`DWIDTH], pipe_0[8:0], Sa, Sb, Ea[`EXPONENT-1:0], Eb[`EXPONENT-1:0], Mp[2*`MANTISSA+1:0], InputExc[4:0]} ; + + /* PIPE 2 + [`EXPONENT + `MANTISSA + 7:`EXPONENT + `MANTISSA + 3] InputExc + [`EXPONENT + `MANTISSA + 2] GRS + [`EXPONENT + `MANTISSA + 1] Sp + [`EXPONENT + `MANTISSA:`MANTISSA] NormE + [`MANTISSA-1:0] NormM + */ + pipe_2 <= {pipe_1[4:0], GRS, Sp, NormE[`EXPONENT:0], NormM[`MANTISSA-1:0]} ; + /* PIPE 3 + [2*`EXPONENT+2*`MANTISSA+10:2*`EXPONENT+2*`MANTISSA+6] InputExc + [2*`EXPONENT+2*`MANTISSA+5] GRS + [2*`EXPONENT+2*`MANTISSA+4] Sp + [2*`EXPONENT+2*`MANTISSA+3:`EXPONENT+2*`MANTISSA+3] RoundE + [`EXPONENT+2*`MANTISSA+2:2*`MANTISSA+2] RoundEP + [2*`MANTISSA+1:`MANTISSA+1] RoundM + [`MANTISSA:0] RoundMP + */ + pipe_3 <= {pipe_2[`EXPONENT+`MANTISSA+7:`EXPONENT+`MANTISSA+1], RoundE[`EXPONENT:0], RoundEP[`EXPONENT:0], RoundM[`MANTISSA:0], RoundMP[`MANTISSA:0]} ; + /* PIPE 4 + [`DWIDTH+4:5] Z + [4:0] Flags + */ + pipe_4 <= {Z_int[`DWIDTH-1:0], Flags_int[4:0]} ; + end + end + +endmodule + + + +module FPMult_PrepModule ( + clk, + rst, + a, + b, + Sa, + Sb, + Ea, + Eb, + Mp, + InputExc + ); + + // Input ports + input clk ; + input rst ; + input [`DWIDTH-1:0] a ; // Input A, a 32-bit floating point number + input [`DWIDTH-1:0] b ; // Input B, a 32-bit floating point number + + // Output ports + output Sa ; // A's sign + output Sb ; // B's sign + output [`EXPONENT-1:0] Ea ; // A's exponent + output [`EXPONENT-1:0] Eb ; // B's exponent + output [2*`MANTISSA+1:0] Mp ; // Mantissa product + output [4:0] InputExc ; // Input numbers are exceptions + + // Internal signals // If signal is high... + wire ANaN ; // A is a signalling NaN + wire BNaN ; // B is a signalling NaN + wire AInf ; // A is infinity + wire BInf ; // B is infinity + wire [`MANTISSA-1:0] Ma; + wire [`MANTISSA-1:0] Mb; + + assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN + assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN + assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity + + // Check for any exceptions and put all flags into exception vector + assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ; + //assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ; + + // Take input numbers apart + assign Sa = a[`DWIDTH-1] ; // A's sign + assign Sb = b[`DWIDTH-1] ; // B's sign + assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception + assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception +// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB]; + // assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB]; + + + + //assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ; + assign Mp = ({1'b1,a[`MANTISSA-1:0]}*{1'b1, b[`MANTISSA-1:0]}) ; + + + //We multiply part of the mantissa here + //Full mantissa of A + //Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B + // wire [`ACTUAL_MANTISSA-1:0] inp_A; + // wire [`ACTUAL_MANTISSA-1:0] inp_B; + // assign inp_A = {1'b1, Ma}; + // assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp)); +endmodule + + +module FPMult_ExecuteModule( + a, + b, + MpC, + Ea, + Eb, + Sa, + Sb, + Sp, + NormE, + NormM, + GRS + ); + + // Input ports + input [`MANTISSA-1:0] a ; + input [2*`EXPONENT:0] b ; + input [2*`MANTISSA+1:0] MpC ; + input [`EXPONENT-1:0] Ea ; // A's exponent + input [`EXPONENT-1:0] Eb ; // B's exponent + input Sa ; // A's sign + input Sb ; // B's sign + + // Output ports + output Sp ; // Product sign + output [`EXPONENT:0] NormE ; // Normalized exponent + output [`MANTISSA-1:0] NormM ; // Normalized mantissa + output GRS ; + + wire [2*`MANTISSA+1:0] Mp ; + + assign Sp = (Sa ^ Sb) ; // Equal signs give a positive product + + // wire [`ACTUAL_MANTISSA-1:0] inp_a; + // wire [`ACTUAL_MANTISSA-1:0] inp_b; + // assign inp_a = {1'b1, a}; + // assign inp_b = {{(`MANTISSA-`MANTISSA_MUL_SPLIT_LSB){1'b0}}, 1'b0, b}; + // DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_a), .B(inp_b), .TC(1'b0), .PRODUCT(Mp_temp)); + // DW01_add #(2*`ACTUAL_MANTISSA) u_add(.A(Mp_temp), .B(MpC<<`MANTISSA_MUL_SPLIT_LSB), .CI(1'b0), .SUM(Mp), .CO()); + + //assign Mp = (MpC<<(2*`EXPONENT+1)) + ({4'b0001, a[`MANTISSA-1:0]}*{1'b0, b[2*`EXPONENT:0]}) ; + assign Mp = MpC; + + + assign NormM = (Mp[2*`MANTISSA+1] ? Mp[2*`MANTISSA:`MANTISSA+1] : Mp[2*`MANTISSA-1:`MANTISSA]); // Check for overflow + assign NormE = (Ea + Eb + Mp[2*`MANTISSA+1]); // If so, increment exponent + + assign GRS = ((Mp[`MANTISSA]&(Mp[`MANTISSA+1]))|(|Mp[`MANTISSA-1:0])) ; + +endmodule + +module FPMult_NormalizeModule( + NormM, + NormE, + RoundE, + RoundEP, + RoundM, + RoundMP + ); + + // Input Ports + input [`MANTISSA-1:0] NormM ; // Normalized mantissa + input [`EXPONENT:0] NormE ; // Normalized exponent + + // Output Ports + output [`EXPONENT:0] RoundE ; + output [`EXPONENT:0] RoundEP ; + output [`MANTISSA:0] RoundM ; + output [`MANTISSA:0] RoundMP ; + +// EXPONENT = 5 +// EXPONENT -1 = 4 +// NEED to subtract 2^4 -1 = 15 + +wire [`EXPONENT-1 : 0] bias; + +assign bias = ((1<< (`EXPONENT -1)) -1); + + assign RoundE = NormE - bias ; + assign RoundEP = NormE - bias -1 ; + assign RoundM = NormM ; + assign RoundMP = NormM ; + +endmodule + +module FPMult_RoundModule( + RoundM, + RoundMP, + RoundE, + RoundEP, + Sp, + GRS, + InputExc, + Z, + Flags + ); + + // Input Ports + input [`MANTISSA:0] RoundM ; // Normalized mantissa + input [`MANTISSA:0] RoundMP ; // Normalized exponent + input [`EXPONENT:0] RoundE ; // Normalized mantissa + 1 + input [`EXPONENT:0] RoundEP ; // Normalized exponent + 1 + input Sp ; // Product sign + input GRS ; + input [4:0] InputExc ; + + // Output Ports + output [`DWIDTH-1:0] Z ; // Final product + output [4:0] Flags ; + + // Internal Signals + wire [`EXPONENT:0] FinalE ; // Rounded exponent + wire [`MANTISSA:0] FinalM; + wire [`MANTISSA:0] PreShiftM; + + assign PreShiftM = GRS ? RoundMP : RoundM ; // Round up if R and (G or S) + + // Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow) + assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]) ; + + assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done + + assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]} ; // Putting the pieces together + assign Flags = InputExc[4:0]; + +endmodule +`endif diff --git a/designs/koios/tpu_like.large.os/design.yaml b/designs/koios/tpu_like.large.os/design.yaml new file mode 100644 index 000000000..07777e95d --- /dev/null +++ b/designs/koios/tpu_like.large.os/design.yaml @@ -0,0 +1 @@ +top: tpu_random diff --git a/designs/koios/tpu_like.large.os/tpu_like.large.os.v b/designs/koios/tpu_like.large.os/tpu_like.large.os.v new file mode 100644 index 000000000..ad7f8f6e4 --- /dev/null +++ b/designs/koios/tpu_like.large.os/tpu_like.large.os.v @@ -0,0 +1,15691 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Aman Arora +////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +/////////////////////////////////// +// Overview +/////////////////////////////////// +//This design is based on the architecture from Google's TPU v1 [1]. At its heart, +//it uses a 32x32 matrix multiplication unit, instead of a 256x256 matrix multiplication +//unit used by the TPU. The design uses int8 precision. This systolic matrix multiplication +//unit is a output stationary unit, compared to weight stationary architecture used in the TPU. +//The activations are stored in RAM block A, whereas the weights are stored in RAM block B. +//Control and configuration are done through an APB interface, instead of a PCIe interface on +//the TPU. The normalization block applies the mean and variance values to the output of the +//matrix multiplication unit. Pooling unit supports 3 pooling windows - 1x1, 2x2 and 4x4. +//The activation unit supports two activation functions - rectified linear unit (ReLU) and +//the hyperbolic tangent (TanH). The activation unit is the last unit before the results +//are written back to RAM block A, from where they can be read again into the matrix +//multiplication unit for the next layer. +// +//[1] Jouppi et. al., In-Datacenter Performance Analysis of a Tensor Processing Unit, ISCA 2017 + +////////////////////////////////////// +// Module hierarchy +////////////////////////////////////// +// top (the top level design) +// |--- ram matrix_A (the RAM that stores matrix A (activations)) +// |--- ram matrix_B (the RAM that stores matrix B (weights)) +// |--- control u_control (the state machine that controls the operation) +// |--- cfg u_cfg (unit to configure/observe registers using an APB interface) +// |--- matmul_32x32_systolic u_matmul (systolic 32x32 matrix multiplication unit) +// | |--- output_logic (contains logic to shift out the outputs of matmul) +// | |--- systolic_data_setup (contains logic to shift in the inputs of the matmul) +// | |--- systolic_pe_matrix (32x32 matrix of processing elements) +// | |--- processing_element (one processing element) +// | |--- seq_mac (mac block inside each processing element) +// | |--- qmult (multiplier inside each mac) +// | |--- qadd (adder inside each mac) +// |--- norm u_norm (normalization block; applies mean and variance) +// |--- pool u_pool (block that performs pooling) +// |--- activation u_activation(block that applies activation - relu or tanh) + +////////////////////////////////////// +// Tested architectures +////////////////////////////////////// +// This design has been tested with: +// 1. The VTR flagship 40nm architecture. Example: arch/timing/k6_frac_N10_frac_chain_mem32K_40nm.xml +// Properties of this design on this architecture: +// Critical path delay: 11.79 ns +// Clock frequency: 84.76 MHz +// Critical path: Includes the multiplier in the MAC in a PE and inter-CLB routing +// Logic area (used): 7.07642e+08 MWTAs +// Resource usage: 5150 LBs, 16 RAMs, 1064 Multipliers +// Runtime (on Intel Xeon E5-2430 2.5GHz with single thread): 11500 sec +// 2. 22nm architectures generated from COFFE. Example: arch/COFFE_22nm/stratix10_arch.xml +// Properties of this design on this architecture: +// Critical path delay: 12.92 ns +// Clock frequency: 77.39 MHz +// Critical path: Includes the multiplier in the MAC in a PE and inter-CLB routing +// Logic area (used): 1.72408e+08 MWTAs +// Resource usage: 5033 LBs, 26 RAMs, 1072 Multipliers +// Runtime (on Intel Xeon E5-2430 2.5GHz with single thread): 12500 sec +// 3. 22nm architectures generated from COFFE. Example: arch/COFFE_22nm/k6n10LB_mem20K_complexDSP_customSB_22nm* + +////////////////////////////////////// +// Parameters +////////////////////////////////////// + +//The width of the data. This design uses int8 precision. So, DWIDTH is 8 +//To change to a floating point 16 version, change this to 16 and also +//change the datapath components (like adder and multiplier) to be floating point. +`define DWIDTH 8 + +//This is the size of the matrix multiplier unit. In this design, we have a systolic +//matrix multiplication unit that can multiply 32x32 matrix with a 32x32 matrix. +`define DESIGN_SIZE 32 +`define LOG2_DESIGN_SIZE 5 +`define MAT_MUL_SIZE 32 +`define MASK_WIDTH 32 +`define LOG2_MAT_MUL_SIZE 5 + +//This it the size of the address bus, or the depth of the RAM. Each location of +//the RAM is DWIDTH * MAT_MUL_SIZE wide. So, in this design, we use a total of +//1024 * 32 bytes of memory (i.e. 32 KB). +`define AWIDTH 10 + +//This is the number of clock cycles spent in the mac block +`define NUM_CYCLES_IN_MAC 3 + +//This defines the latency of accessing data from a block ram +`define MEM_ACCESS_LATENCY 1 + +//Data width and address width of the APB interface for registers +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 + +//Width of the stride for each column in the matrices (same as ram address width) +`define ADDR_STRIDE_WIDTH 16 + +//Number of bits to specify the pooling window. We support 3 sizes. +`define MAX_BITS_POOL 3 + +///////////////////////////////////////////////// +// Register specification +///////////////////////////////////////////////// + +//--------------------------------------- +//Addr 0 : Register with enables for various blocks. +//Includes mode of operation (convolution or fully_connected) +//--------------------------------------- +`define REG_ENABLES_ADDR 32'h0 +//Bit 0: enable_matmul +//Bit 1: enable_norm +//Bit 2: enable_pool +//Bit 3: enable_activation +//Bit 31: enable_conv_mode + +//--------------------------------------- +//Addr 4: Register that triggers the whole TPU +//--------------------------------------- +`define REG_STDN_TPU_ADDR 32'h4 +//Bit 0: start_tpu +//Bit 31: done_tpu + +//--------------------------------------- +//Addr 8: Register that stores the mean of the values +//--------------------------------------- +`define REG_MEAN_ADDR 32'h8 +//Bit 7:0: mean + +//--------------------------------------- +//Addr A: Register that stores the inverse variance of the values +//--------------------------------------- +`define REG_INV_VAR_ADDR 32'hA +//Bit 7:0: inv_var + +//--------------------------------------- +//Addr E: Register that stores the starting address of matrix A in BRAM A. +//In fully-connected mode, this register should be programmed with the +//address of the matrix being currently multiplied. That is, the +//address of the matrix of the matmul. So, this register will be +//programmed every time the matmul is kicked off during accumulation stages. +//Use the STRIDE registers to tell the matmul to increment addresses. +//In convolution mode, this register should be programmed with the +//address of the input activation matrix. No need to configure +//this every time the matmul is kicked off for accmulation. Just program it +//once it the beginning. Address increments are handled automatically . +//--------------------------------------- +`define REG_MATRIX_A_ADDR 32'he +//Bit `AWIDTH-1:0 address_mat_a + +//--------------------------------------- +//Addr 12: Register that stores the starting address of matrix B in BRAM B. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_B_ADDR 32'h12 +//Bit `AWIDTH-1:0 address_mat_b + +//--------------------------------------- +//Addr 16: Register that stores the starting address of matrix C in BRAM C. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_C_ADDR 32'h16 +//Bit `AWIDTH-1:0 address_mat_c + +//--------------------------------------- +//Addr 24: Register that controls the accumulation logic +//--------------------------------------- +`define REG_ACCUM_ACTIONS_ADDR 32'h24 +//Bit 0 save_output_to_accumulator +//Bit 1 add_accumulator_to_output + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 28: Register that stores the stride that should be taken to address +//elements in matrix A, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix A in the vertical +//direction. +//--------------------------------------- +`define REG_MATRIX_A_STRIDE_ADDR 32'h28 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_a + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 32: Register that stores the stride that should be taken to address +//elements in matrix B, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix B in the horizontal +//direction. +//--------------------------------------- +`define REG_MATRIX_B_STRIDE_ADDR 32'h32 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_b + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 36: Register that stores the stride that should be taken to address +//elements in matrix C, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix C in the vertical +//direction (this is generally same as address_stride_a). +//--------------------------------------- +`define REG_MATRIX_C_STRIDE_ADDR 32'h36 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_c + +//--------------------------------------- +//Addr 3A: Register that controls the activation block. Currently, the available +//settings are the selector of activation function that will be used. There are +//two options: ReLU and TanH. To use ReLU, clear the LSB of this register. To +//use TanH, set the LSB of this register. +//--------------------------------------- +`define REG_ACTIVATION_CSR_ADDR 32'h3A + +//--------------------------------------- +//Addr 3E: Register defining pooling window size +//--------------------------------------- +`define REG_POOL_WINDOW_ADDR 32'h3E +//Bit `MAX_BITS_POOL-1:0 pool window size + +//--------------------------------------- +//Addr 40: Register defining convolution parameters - 1 +//---------------------------------------- +`define REG_CONV_PARAMS_1_ADDR 32'h40 +//Bits filter_height (R) 3:0 +//Bits filter width (S) 7:4 +//Bits stride_horizontal 11:8 +//Bits stride_vertical 15:12 +//Bits pad_left 19:16 +//Bits pad_right 23:20 +//Bits pad_top 27:24 +//Bits pad_bottom 31:28 + +//--------------------------------------- +//Addr 44: Register defining convolution parameters - 2 +//---------------------------------------- +`define REG_CONV_PARAMS_2_ADDR 32'h44 +//Bits num_channels_input (C) 15:0 +//Bits num_channels_output (K) 31:16 + +//--------------------------------------- +//Addr 48: Register defining convolution parameters - 3 +//---------------------------------------- +`define REG_CONV_PARAMS_3_ADDR 32'h48 +//Bits input_image_height (H) 15:0 +//Bits input_image_width (W) 31:16 + +//--------------------------------------- +//Addr 4C: Register defining convolution parameters - 4 +//---------------------------------------- +`define REG_CONV_PARAMS_4_ADDR 32'h4C +//Bits output_image_height (P) 15:0 +//Bits output_image_width (Q) 31:16 + +//--------------------------------------- +//Addr 50: Register defining batch size +//---------------------------------------- +`define REG_BATCH_SIZE_ADDR 32'h50 +//Bits 31:0 batch_size (number of images, N) + +//--------------------------------------- +//Addresses 54,58,5C: Registers that stores the mask of which parts of the matrices are valid. +// +//Some examples where this is useful: +//1. Input matrix is smaller than the matmul. +// Say we want to multiply a 6x6 using an 8x8 matmul. +// The matmul still operates on the whole 8x8 part, so we need +// to ensure that there are 0s in the BRAMs in the invalid parts. +// But the mask is used by the blocks other than matmul. For ex, +// norm block will use the mask to avoid applying mean and variance +// to invalid parts (so tha they stay 0). +//2. When we start with large matrices, the size of the matrices can +// reduce to something less than the matmul size because of pooling. +// In that case for the next layer, we need to tell blocks like norm, +// what is valid and what is not. +// +//Note: This masks is applied to both x and y directions and also +//applied to both input matrices - A and B. +//--------------------------------------- +`define REG_VALID_MASK_A_ROWS_ADDR 32'h20 +`define REG_VALID_MASK_A_COLS_ADDR 32'h54 +`define REG_VALID_MASK_B_ROWS_ADDR 32'h5c +`define REG_VALID_MASK_B_COLS_ADDR 32'h58 +//Bit `MASK_WIDTH-1:0 validity_mask + +//This used to be a normal signal, but changing it to a `define. +//That's because it's not required to be a variable in this design. +//And ODIN doesn't seem to propagate constants properly. +`define final_mat_mul_size 32 + +///////////////////////////////////// +// Matrix multiplication unit +//////////////////////////////////// + +module matmul_32x32_systolic( + clk, + reset, + pe_reset, + start_mat_mul, + done_mat_mul, + address_mat_a, + address_mat_b, + address_mat_c, + address_stride_a, + address_stride_b, + address_stride_c, + a_data, + b_data, + a_data_in, //Data values coming in from previous matmul - systolic connections + b_data_in, + c_data_in, //Data values coming in from previous matmul - systolic shifting + c_data_out, //Data values going out to next matmul - systolic shifting + a_data_out, + b_data_out, + a_addr, + b_addr, + c_addr, + c_data_available, + + validity_mask_a_rows, + validity_mask_a_cols, + validity_mask_b_rows, + validity_mask_b_cols, + + final_mat_mul_size, + + a_loc, + b_loc +); + + input clk; + input reset; + input pe_reset; + input start_mat_mul; + output done_mat_mul; + input [`AWIDTH-1:0] address_mat_a; + input [`AWIDTH-1:0] address_mat_b; + input [`AWIDTH-1:0] address_mat_c; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + output [`AWIDTH-1:0] a_addr; + output [`AWIDTH-1:0] b_addr; + output [`AWIDTH-1:0] c_addr; + output c_data_available; + + input [`MASK_WIDTH-1:0] validity_mask_a_rows; + input [`MASK_WIDTH-1:0] validity_mask_a_cols; + input [`MASK_WIDTH-1:0] validity_mask_b_rows; + input [`MASK_WIDTH-1:0] validity_mask_b_cols; + +//7:0 is okay here. We aren't going to make a matmul larger than 128x128 +//In fact, these will get optimized out by the synthesis tool, because +//we hardcode them at the instantiation level. + input [7:0] final_mat_mul_size; + + input [7:0] a_loc; + input [7:0] b_loc; + +////////////////////////////////////////////////////////////////////////// +// Logic for clock counting and when to assert done +////////////////////////////////////////////////////////////////////////// + +reg done_mat_mul; +//This is 7 bits because the expectation is that clock count will be pretty +//small. For large matmuls, this will need to increased to have more bits. +//In general, a systolic multiplier takes 4*N-2+P cycles, where N is the size +//of the matmul and P is the number of pipleine stages in the MAC block. +reg [7:0] clk_cnt; + +//Finding out number of cycles to assert matmul done. +//When we have to save the outputs to accumulators, then we don't need to +//shift out data. So, we can assert done_mat_mul early. +//In the normal case, we have to include the time to shift out the results. +//Note: the count expression used to contain "4*final_mat_mul_size", but +//to avoid multiplication, we now use "final_mat_mul_size<<2" +wire [7:0] clk_cnt_for_done; + +assign clk_cnt_for_done = + ((`final_mat_mul_size<<2) - 2 + `NUM_CYCLES_IN_MAC); + +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + clk_cnt <= 0; + done_mat_mul <= 0; + end + else if (clk_cnt == clk_cnt_for_done) begin + done_mat_mul <= 1; + clk_cnt <= clk_cnt + 1; + + end + else if (done_mat_mul == 0) begin + clk_cnt <= clk_cnt + 1; + + end + else begin + done_mat_mul <= 0; + clk_cnt <= clk_cnt + 1; + end +end +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] a16_data; +wire [`DWIDTH-1:0] a17_data; +wire [`DWIDTH-1:0] a18_data; +wire [`DWIDTH-1:0] a19_data; +wire [`DWIDTH-1:0] a20_data; +wire [`DWIDTH-1:0] a21_data; +wire [`DWIDTH-1:0] a22_data; +wire [`DWIDTH-1:0] a23_data; +wire [`DWIDTH-1:0] a24_data; +wire [`DWIDTH-1:0] a25_data; +wire [`DWIDTH-1:0] a26_data; +wire [`DWIDTH-1:0] a27_data; +wire [`DWIDTH-1:0] a28_data; +wire [`DWIDTH-1:0] a29_data; +wire [`DWIDTH-1:0] a30_data; +wire [`DWIDTH-1:0] a31_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; +wire [`DWIDTH-1:0] b16_data; +wire [`DWIDTH-1:0] b17_data; +wire [`DWIDTH-1:0] b18_data; +wire [`DWIDTH-1:0] b19_data; +wire [`DWIDTH-1:0] b20_data; +wire [`DWIDTH-1:0] b21_data; +wire [`DWIDTH-1:0] b22_data; +wire [`DWIDTH-1:0] b23_data; +wire [`DWIDTH-1:0] b24_data; +wire [`DWIDTH-1:0] b25_data; +wire [`DWIDTH-1:0] b26_data; +wire [`DWIDTH-1:0] b27_data; +wire [`DWIDTH-1:0] b28_data; +wire [`DWIDTH-1:0] b29_data; +wire [`DWIDTH-1:0] b30_data; +wire [`DWIDTH-1:0] b31_data; +wire [`DWIDTH-1:0] a1_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_1; +wire [`DWIDTH-1:0] a3_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_1; +wire [`DWIDTH-1:0] a4_data_delayed_2; +wire [`DWIDTH-1:0] a4_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_1; +wire [`DWIDTH-1:0] a5_data_delayed_2; +wire [`DWIDTH-1:0] a5_data_delayed_3; +wire [`DWIDTH-1:0] a5_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_1; +wire [`DWIDTH-1:0] a6_data_delayed_2; +wire [`DWIDTH-1:0] a6_data_delayed_3; +wire [`DWIDTH-1:0] a6_data_delayed_4; +wire [`DWIDTH-1:0] a6_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_1; +wire [`DWIDTH-1:0] a7_data_delayed_2; +wire [`DWIDTH-1:0] a7_data_delayed_3; +wire [`DWIDTH-1:0] a7_data_delayed_4; +wire [`DWIDTH-1:0] a7_data_delayed_5; +wire [`DWIDTH-1:0] a7_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_1; +wire [`DWIDTH-1:0] a8_data_delayed_2; +wire [`DWIDTH-1:0] a8_data_delayed_3; +wire [`DWIDTH-1:0] a8_data_delayed_4; +wire [`DWIDTH-1:0] a8_data_delayed_5; +wire [`DWIDTH-1:0] a8_data_delayed_6; +wire [`DWIDTH-1:0] a8_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_1; +wire [`DWIDTH-1:0] a9_data_delayed_2; +wire [`DWIDTH-1:0] a9_data_delayed_3; +wire [`DWIDTH-1:0] a9_data_delayed_4; +wire [`DWIDTH-1:0] a9_data_delayed_5; +wire [`DWIDTH-1:0] a9_data_delayed_6; +wire [`DWIDTH-1:0] a9_data_delayed_7; +wire [`DWIDTH-1:0] a9_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_1; +wire [`DWIDTH-1:0] a10_data_delayed_2; +wire [`DWIDTH-1:0] a10_data_delayed_3; +wire [`DWIDTH-1:0] a10_data_delayed_4; +wire [`DWIDTH-1:0] a10_data_delayed_5; +wire [`DWIDTH-1:0] a10_data_delayed_6; +wire [`DWIDTH-1:0] a10_data_delayed_7; +wire [`DWIDTH-1:0] a10_data_delayed_8; +wire [`DWIDTH-1:0] a10_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_1; +wire [`DWIDTH-1:0] a11_data_delayed_2; +wire [`DWIDTH-1:0] a11_data_delayed_3; +wire [`DWIDTH-1:0] a11_data_delayed_4; +wire [`DWIDTH-1:0] a11_data_delayed_5; +wire [`DWIDTH-1:0] a11_data_delayed_6; +wire [`DWIDTH-1:0] a11_data_delayed_7; +wire [`DWIDTH-1:0] a11_data_delayed_8; +wire [`DWIDTH-1:0] a11_data_delayed_9; +wire [`DWIDTH-1:0] a11_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_1; +wire [`DWIDTH-1:0] a12_data_delayed_2; +wire [`DWIDTH-1:0] a12_data_delayed_3; +wire [`DWIDTH-1:0] a12_data_delayed_4; +wire [`DWIDTH-1:0] a12_data_delayed_5; +wire [`DWIDTH-1:0] a12_data_delayed_6; +wire [`DWIDTH-1:0] a12_data_delayed_7; +wire [`DWIDTH-1:0] a12_data_delayed_8; +wire [`DWIDTH-1:0] a12_data_delayed_9; +wire [`DWIDTH-1:0] a12_data_delayed_10; +wire [`DWIDTH-1:0] a12_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_1; +wire [`DWIDTH-1:0] a13_data_delayed_2; +wire [`DWIDTH-1:0] a13_data_delayed_3; +wire [`DWIDTH-1:0] a13_data_delayed_4; +wire [`DWIDTH-1:0] a13_data_delayed_5; +wire [`DWIDTH-1:0] a13_data_delayed_6; +wire [`DWIDTH-1:0] a13_data_delayed_7; +wire [`DWIDTH-1:0] a13_data_delayed_8; +wire [`DWIDTH-1:0] a13_data_delayed_9; +wire [`DWIDTH-1:0] a13_data_delayed_10; +wire [`DWIDTH-1:0] a13_data_delayed_11; +wire [`DWIDTH-1:0] a13_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_1; +wire [`DWIDTH-1:0] a14_data_delayed_2; +wire [`DWIDTH-1:0] a14_data_delayed_3; +wire [`DWIDTH-1:0] a14_data_delayed_4; +wire [`DWIDTH-1:0] a14_data_delayed_5; +wire [`DWIDTH-1:0] a14_data_delayed_6; +wire [`DWIDTH-1:0] a14_data_delayed_7; +wire [`DWIDTH-1:0] a14_data_delayed_8; +wire [`DWIDTH-1:0] a14_data_delayed_9; +wire [`DWIDTH-1:0] a14_data_delayed_10; +wire [`DWIDTH-1:0] a14_data_delayed_11; +wire [`DWIDTH-1:0] a14_data_delayed_12; +wire [`DWIDTH-1:0] a14_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_1; +wire [`DWIDTH-1:0] a15_data_delayed_2; +wire [`DWIDTH-1:0] a15_data_delayed_3; +wire [`DWIDTH-1:0] a15_data_delayed_4; +wire [`DWIDTH-1:0] a15_data_delayed_5; +wire [`DWIDTH-1:0] a15_data_delayed_6; +wire [`DWIDTH-1:0] a15_data_delayed_7; +wire [`DWIDTH-1:0] a15_data_delayed_8; +wire [`DWIDTH-1:0] a15_data_delayed_9; +wire [`DWIDTH-1:0] a15_data_delayed_10; +wire [`DWIDTH-1:0] a15_data_delayed_11; +wire [`DWIDTH-1:0] a15_data_delayed_12; +wire [`DWIDTH-1:0] a15_data_delayed_13; +wire [`DWIDTH-1:0] a15_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_15; +wire [`DWIDTH-1:0] a16_data_delayed_1; +wire [`DWIDTH-1:0] a16_data_delayed_2; +wire [`DWIDTH-1:0] a16_data_delayed_3; +wire [`DWIDTH-1:0] a16_data_delayed_4; +wire [`DWIDTH-1:0] a16_data_delayed_5; +wire [`DWIDTH-1:0] a16_data_delayed_6; +wire [`DWIDTH-1:0] a16_data_delayed_7; +wire [`DWIDTH-1:0] a16_data_delayed_8; +wire [`DWIDTH-1:0] a16_data_delayed_9; +wire [`DWIDTH-1:0] a16_data_delayed_10; +wire [`DWIDTH-1:0] a16_data_delayed_11; +wire [`DWIDTH-1:0] a16_data_delayed_12; +wire [`DWIDTH-1:0] a16_data_delayed_13; +wire [`DWIDTH-1:0] a16_data_delayed_14; +wire [`DWIDTH-1:0] a16_data_delayed_15; +wire [`DWIDTH-1:0] a16_data_delayed_16; +wire [`DWIDTH-1:0] a17_data_delayed_1; +wire [`DWIDTH-1:0] a17_data_delayed_2; +wire [`DWIDTH-1:0] a17_data_delayed_3; +wire [`DWIDTH-1:0] a17_data_delayed_4; +wire [`DWIDTH-1:0] a17_data_delayed_5; +wire [`DWIDTH-1:0] a17_data_delayed_6; +wire [`DWIDTH-1:0] a17_data_delayed_7; +wire [`DWIDTH-1:0] a17_data_delayed_8; +wire [`DWIDTH-1:0] a17_data_delayed_9; +wire [`DWIDTH-1:0] a17_data_delayed_10; +wire [`DWIDTH-1:0] a17_data_delayed_11; +wire [`DWIDTH-1:0] a17_data_delayed_12; +wire [`DWIDTH-1:0] a17_data_delayed_13; +wire [`DWIDTH-1:0] a17_data_delayed_14; +wire [`DWIDTH-1:0] a17_data_delayed_15; +wire [`DWIDTH-1:0] a17_data_delayed_16; +wire [`DWIDTH-1:0] a17_data_delayed_17; +wire [`DWIDTH-1:0] a18_data_delayed_1; +wire [`DWIDTH-1:0] a18_data_delayed_2; +wire [`DWIDTH-1:0] a18_data_delayed_3; +wire [`DWIDTH-1:0] a18_data_delayed_4; +wire [`DWIDTH-1:0] a18_data_delayed_5; +wire [`DWIDTH-1:0] a18_data_delayed_6; +wire [`DWIDTH-1:0] a18_data_delayed_7; +wire [`DWIDTH-1:0] a18_data_delayed_8; +wire [`DWIDTH-1:0] a18_data_delayed_9; +wire [`DWIDTH-1:0] a18_data_delayed_10; +wire [`DWIDTH-1:0] a18_data_delayed_11; +wire [`DWIDTH-1:0] a18_data_delayed_12; +wire [`DWIDTH-1:0] a18_data_delayed_13; +wire [`DWIDTH-1:0] a18_data_delayed_14; +wire [`DWIDTH-1:0] a18_data_delayed_15; +wire [`DWIDTH-1:0] a18_data_delayed_16; +wire [`DWIDTH-1:0] a18_data_delayed_17; +wire [`DWIDTH-1:0] a18_data_delayed_18; +wire [`DWIDTH-1:0] a19_data_delayed_1; +wire [`DWIDTH-1:0] a19_data_delayed_2; +wire [`DWIDTH-1:0] a19_data_delayed_3; +wire [`DWIDTH-1:0] a19_data_delayed_4; +wire [`DWIDTH-1:0] a19_data_delayed_5; +wire [`DWIDTH-1:0] a19_data_delayed_6; +wire [`DWIDTH-1:0] a19_data_delayed_7; +wire [`DWIDTH-1:0] a19_data_delayed_8; +wire [`DWIDTH-1:0] a19_data_delayed_9; +wire [`DWIDTH-1:0] a19_data_delayed_10; +wire [`DWIDTH-1:0] a19_data_delayed_11; +wire [`DWIDTH-1:0] a19_data_delayed_12; +wire [`DWIDTH-1:0] a19_data_delayed_13; +wire [`DWIDTH-1:0] a19_data_delayed_14; +wire [`DWIDTH-1:0] a19_data_delayed_15; +wire [`DWIDTH-1:0] a19_data_delayed_16; +wire [`DWIDTH-1:0] a19_data_delayed_17; +wire [`DWIDTH-1:0] a19_data_delayed_18; +wire [`DWIDTH-1:0] a19_data_delayed_19; +wire [`DWIDTH-1:0] a20_data_delayed_1; +wire [`DWIDTH-1:0] a20_data_delayed_2; +wire [`DWIDTH-1:0] a20_data_delayed_3; +wire [`DWIDTH-1:0] a20_data_delayed_4; +wire [`DWIDTH-1:0] a20_data_delayed_5; +wire [`DWIDTH-1:0] a20_data_delayed_6; +wire [`DWIDTH-1:0] a20_data_delayed_7; +wire [`DWIDTH-1:0] a20_data_delayed_8; +wire [`DWIDTH-1:0] a20_data_delayed_9; +wire [`DWIDTH-1:0] a20_data_delayed_10; +wire [`DWIDTH-1:0] a20_data_delayed_11; +wire [`DWIDTH-1:0] a20_data_delayed_12; +wire [`DWIDTH-1:0] a20_data_delayed_13; +wire [`DWIDTH-1:0] a20_data_delayed_14; +wire [`DWIDTH-1:0] a20_data_delayed_15; +wire [`DWIDTH-1:0] a20_data_delayed_16; +wire [`DWIDTH-1:0] a20_data_delayed_17; +wire [`DWIDTH-1:0] a20_data_delayed_18; +wire [`DWIDTH-1:0] a20_data_delayed_19; +wire [`DWIDTH-1:0] a20_data_delayed_20; +wire [`DWIDTH-1:0] a21_data_delayed_1; +wire [`DWIDTH-1:0] a21_data_delayed_2; +wire [`DWIDTH-1:0] a21_data_delayed_3; +wire [`DWIDTH-1:0] a21_data_delayed_4; +wire [`DWIDTH-1:0] a21_data_delayed_5; +wire [`DWIDTH-1:0] a21_data_delayed_6; +wire [`DWIDTH-1:0] a21_data_delayed_7; +wire [`DWIDTH-1:0] a21_data_delayed_8; +wire [`DWIDTH-1:0] a21_data_delayed_9; +wire [`DWIDTH-1:0] a21_data_delayed_10; +wire [`DWIDTH-1:0] a21_data_delayed_11; +wire [`DWIDTH-1:0] a21_data_delayed_12; +wire [`DWIDTH-1:0] a21_data_delayed_13; +wire [`DWIDTH-1:0] a21_data_delayed_14; +wire [`DWIDTH-1:0] a21_data_delayed_15; +wire [`DWIDTH-1:0] a21_data_delayed_16; +wire [`DWIDTH-1:0] a21_data_delayed_17; +wire [`DWIDTH-1:0] a21_data_delayed_18; +wire [`DWIDTH-1:0] a21_data_delayed_19; +wire [`DWIDTH-1:0] a21_data_delayed_20; +wire [`DWIDTH-1:0] a21_data_delayed_21; +wire [`DWIDTH-1:0] a22_data_delayed_1; +wire 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[`DWIDTH-1:0] b8_data_delayed_4; +wire [`DWIDTH-1:0] b8_data_delayed_5; +wire [`DWIDTH-1:0] b8_data_delayed_6; +wire [`DWIDTH-1:0] b8_data_delayed_7; +wire [`DWIDTH-1:0] b8_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_1; +wire [`DWIDTH-1:0] b9_data_delayed_2; +wire [`DWIDTH-1:0] b9_data_delayed_3; +wire [`DWIDTH-1:0] b9_data_delayed_4; +wire [`DWIDTH-1:0] b9_data_delayed_5; +wire [`DWIDTH-1:0] b9_data_delayed_6; +wire [`DWIDTH-1:0] b9_data_delayed_7; +wire [`DWIDTH-1:0] b9_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_1; +wire [`DWIDTH-1:0] b10_data_delayed_2; +wire [`DWIDTH-1:0] b10_data_delayed_3; +wire [`DWIDTH-1:0] b10_data_delayed_4; +wire [`DWIDTH-1:0] b10_data_delayed_5; +wire [`DWIDTH-1:0] b10_data_delayed_6; +wire [`DWIDTH-1:0] b10_data_delayed_7; +wire [`DWIDTH-1:0] b10_data_delayed_8; +wire [`DWIDTH-1:0] b10_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_1; +wire [`DWIDTH-1:0] b11_data_delayed_2; +wire [`DWIDTH-1:0] b11_data_delayed_3; +wire [`DWIDTH-1:0] b11_data_delayed_4; +wire [`DWIDTH-1:0] b11_data_delayed_5; +wire [`DWIDTH-1:0] b11_data_delayed_6; +wire [`DWIDTH-1:0] b11_data_delayed_7; +wire [`DWIDTH-1:0] b11_data_delayed_8; +wire [`DWIDTH-1:0] b11_data_delayed_9; +wire [`DWIDTH-1:0] b11_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_1; +wire [`DWIDTH-1:0] b12_data_delayed_2; +wire [`DWIDTH-1:0] b12_data_delayed_3; +wire [`DWIDTH-1:0] b12_data_delayed_4; +wire [`DWIDTH-1:0] b12_data_delayed_5; +wire [`DWIDTH-1:0] b12_data_delayed_6; +wire [`DWIDTH-1:0] b12_data_delayed_7; +wire [`DWIDTH-1:0] b12_data_delayed_8; +wire [`DWIDTH-1:0] b12_data_delayed_9; +wire [`DWIDTH-1:0] b12_data_delayed_10; +wire [`DWIDTH-1:0] b12_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_1; +wire [`DWIDTH-1:0] b13_data_delayed_2; +wire [`DWIDTH-1:0] b13_data_delayed_3; +wire [`DWIDTH-1:0] b13_data_delayed_4; +wire [`DWIDTH-1:0] b13_data_delayed_5; +wire [`DWIDTH-1:0] b13_data_delayed_6; +wire [`DWIDTH-1:0] b13_data_delayed_7; +wire [`DWIDTH-1:0] b13_data_delayed_8; +wire [`DWIDTH-1:0] b13_data_delayed_9; +wire [`DWIDTH-1:0] b13_data_delayed_10; +wire [`DWIDTH-1:0] b13_data_delayed_11; +wire [`DWIDTH-1:0] b13_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_1; +wire [`DWIDTH-1:0] b14_data_delayed_2; +wire [`DWIDTH-1:0] b14_data_delayed_3; +wire [`DWIDTH-1:0] b14_data_delayed_4; +wire [`DWIDTH-1:0] b14_data_delayed_5; +wire [`DWIDTH-1:0] b14_data_delayed_6; +wire [`DWIDTH-1:0] b14_data_delayed_7; +wire [`DWIDTH-1:0] b14_data_delayed_8; +wire [`DWIDTH-1:0] b14_data_delayed_9; +wire [`DWIDTH-1:0] b14_data_delayed_10; +wire [`DWIDTH-1:0] b14_data_delayed_11; +wire [`DWIDTH-1:0] b14_data_delayed_12; +wire [`DWIDTH-1:0] b14_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_1; +wire [`DWIDTH-1:0] b15_data_delayed_2; +wire [`DWIDTH-1:0] b15_data_delayed_3; +wire [`DWIDTH-1:0] b15_data_delayed_4; +wire [`DWIDTH-1:0] b15_data_delayed_5; +wire [`DWIDTH-1:0] b15_data_delayed_6; +wire [`DWIDTH-1:0] b15_data_delayed_7; +wire [`DWIDTH-1:0] b15_data_delayed_8; +wire [`DWIDTH-1:0] b15_data_delayed_9; +wire [`DWIDTH-1:0] b15_data_delayed_10; +wire [`DWIDTH-1:0] b15_data_delayed_11; +wire [`DWIDTH-1:0] b15_data_delayed_12; +wire [`DWIDTH-1:0] b15_data_delayed_13; +wire [`DWIDTH-1:0] b15_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_15; +wire [`DWIDTH-1:0] b16_data_delayed_1; +wire [`DWIDTH-1:0] b16_data_delayed_2; +wire [`DWIDTH-1:0] b16_data_delayed_3; +wire [`DWIDTH-1:0] b16_data_delayed_4; +wire [`DWIDTH-1:0] b16_data_delayed_5; +wire [`DWIDTH-1:0] b16_data_delayed_6; +wire [`DWIDTH-1:0] b16_data_delayed_7; +wire [`DWIDTH-1:0] b16_data_delayed_8; +wire [`DWIDTH-1:0] b16_data_delayed_9; +wire [`DWIDTH-1:0] b16_data_delayed_10; +wire [`DWIDTH-1:0] b16_data_delayed_11; +wire [`DWIDTH-1:0] b16_data_delayed_12; +wire [`DWIDTH-1:0] b16_data_delayed_13; +wire [`DWIDTH-1:0] b16_data_delayed_14; +wire [`DWIDTH-1:0] b16_data_delayed_15; +wire [`DWIDTH-1:0] b16_data_delayed_16; +wire [`DWIDTH-1:0] b17_data_delayed_1; +wire [`DWIDTH-1:0] b17_data_delayed_2; +wire [`DWIDTH-1:0] b17_data_delayed_3; +wire [`DWIDTH-1:0] b17_data_delayed_4; +wire [`DWIDTH-1:0] b17_data_delayed_5; +wire [`DWIDTH-1:0] b17_data_delayed_6; +wire [`DWIDTH-1:0] b17_data_delayed_7; +wire [`DWIDTH-1:0] b17_data_delayed_8; +wire [`DWIDTH-1:0] b17_data_delayed_9; +wire [`DWIDTH-1:0] b17_data_delayed_10; +wire [`DWIDTH-1:0] b17_data_delayed_11; +wire [`DWIDTH-1:0] b17_data_delayed_12; +wire [`DWIDTH-1:0] b17_data_delayed_13; +wire [`DWIDTH-1:0] b17_data_delayed_14; +wire [`DWIDTH-1:0] b17_data_delayed_15; +wire [`DWIDTH-1:0] b17_data_delayed_16; +wire [`DWIDTH-1:0] b17_data_delayed_17; +wire [`DWIDTH-1:0] b18_data_delayed_1; +wire [`DWIDTH-1:0] b18_data_delayed_2; +wire [`DWIDTH-1:0] b18_data_delayed_3; +wire [`DWIDTH-1:0] b18_data_delayed_4; +wire [`DWIDTH-1:0] b18_data_delayed_5; +wire [`DWIDTH-1:0] b18_data_delayed_6; +wire [`DWIDTH-1:0] b18_data_delayed_7; +wire [`DWIDTH-1:0] b18_data_delayed_8; +wire [`DWIDTH-1:0] b18_data_delayed_9; +wire [`DWIDTH-1:0] b18_data_delayed_10; +wire [`DWIDTH-1:0] b18_data_delayed_11; +wire [`DWIDTH-1:0] b18_data_delayed_12; +wire [`DWIDTH-1:0] b18_data_delayed_13; +wire [`DWIDTH-1:0] b18_data_delayed_14; +wire [`DWIDTH-1:0] b18_data_delayed_15; +wire [`DWIDTH-1:0] b18_data_delayed_16; +wire [`DWIDTH-1:0] b18_data_delayed_17; +wire [`DWIDTH-1:0] b18_data_delayed_18; +wire [`DWIDTH-1:0] b19_data_delayed_1; +wire [`DWIDTH-1:0] b19_data_delayed_2; +wire [`DWIDTH-1:0] b19_data_delayed_3; +wire [`DWIDTH-1:0] b19_data_delayed_4; +wire [`DWIDTH-1:0] b19_data_delayed_5; +wire [`DWIDTH-1:0] b19_data_delayed_6; +wire [`DWIDTH-1:0] b19_data_delayed_7; +wire [`DWIDTH-1:0] b19_data_delayed_8; +wire [`DWIDTH-1:0] b19_data_delayed_9; +wire [`DWIDTH-1:0] b19_data_delayed_10; +wire [`DWIDTH-1:0] b19_data_delayed_11; +wire [`DWIDTH-1:0] b19_data_delayed_12; +wire [`DWIDTH-1:0] b19_data_delayed_13; +wire [`DWIDTH-1:0] b19_data_delayed_14; +wire [`DWIDTH-1:0] b19_data_delayed_15; +wire [`DWIDTH-1:0] b19_data_delayed_16; +wire [`DWIDTH-1:0] b19_data_delayed_17; +wire [`DWIDTH-1:0] b19_data_delayed_18; +wire [`DWIDTH-1:0] b19_data_delayed_19; +wire [`DWIDTH-1:0] b20_data_delayed_1; +wire [`DWIDTH-1:0] b20_data_delayed_2; +wire [`DWIDTH-1:0] b20_data_delayed_3; +wire [`DWIDTH-1:0] b20_data_delayed_4; +wire [`DWIDTH-1:0] b20_data_delayed_5; +wire [`DWIDTH-1:0] b20_data_delayed_6; +wire [`DWIDTH-1:0] b20_data_delayed_7; +wire [`DWIDTH-1:0] b20_data_delayed_8; +wire [`DWIDTH-1:0] b20_data_delayed_9; +wire [`DWIDTH-1:0] b20_data_delayed_10; +wire [`DWIDTH-1:0] b20_data_delayed_11; +wire [`DWIDTH-1:0] b20_data_delayed_12; +wire [`DWIDTH-1:0] b20_data_delayed_13; +wire [`DWIDTH-1:0] b20_data_delayed_14; +wire [`DWIDTH-1:0] b20_data_delayed_15; +wire [`DWIDTH-1:0] b20_data_delayed_16; +wire [`DWIDTH-1:0] b20_data_delayed_17; +wire [`DWIDTH-1:0] b20_data_delayed_18; +wire [`DWIDTH-1:0] b20_data_delayed_19; +wire [`DWIDTH-1:0] b20_data_delayed_20; +wire [`DWIDTH-1:0] b21_data_delayed_1; +wire [`DWIDTH-1:0] b21_data_delayed_2; +wire [`DWIDTH-1:0] b21_data_delayed_3; +wire [`DWIDTH-1:0] b21_data_delayed_4; +wire [`DWIDTH-1:0] b21_data_delayed_5; +wire [`DWIDTH-1:0] b21_data_delayed_6; +wire [`DWIDTH-1:0] b21_data_delayed_7; +wire [`DWIDTH-1:0] b21_data_delayed_8; +wire [`DWIDTH-1:0] b21_data_delayed_9; +wire [`DWIDTH-1:0] b21_data_delayed_10; +wire [`DWIDTH-1:0] b21_data_delayed_11; +wire [`DWIDTH-1:0] b21_data_delayed_12; +wire [`DWIDTH-1:0] b21_data_delayed_13; +wire [`DWIDTH-1:0] b21_data_delayed_14; +wire [`DWIDTH-1:0] b21_data_delayed_15; +wire [`DWIDTH-1:0] b21_data_delayed_16; +wire [`DWIDTH-1:0] b21_data_delayed_17; +wire [`DWIDTH-1:0] b21_data_delayed_18; +wire [`DWIDTH-1:0] b21_data_delayed_19; +wire [`DWIDTH-1:0] b21_data_delayed_20; +wire [`DWIDTH-1:0] b21_data_delayed_21; +wire [`DWIDTH-1:0] b22_data_delayed_1; +wire [`DWIDTH-1:0] b22_data_delayed_2; +wire [`DWIDTH-1:0] b22_data_delayed_3; +wire [`DWIDTH-1:0] b22_data_delayed_4; +wire [`DWIDTH-1:0] b22_data_delayed_5; +wire [`DWIDTH-1:0] b22_data_delayed_6; +wire [`DWIDTH-1:0] b22_data_delayed_7; +wire [`DWIDTH-1:0] b22_data_delayed_8; +wire [`DWIDTH-1:0] b22_data_delayed_9; +wire [`DWIDTH-1:0] b22_data_delayed_10; +wire [`DWIDTH-1:0] b22_data_delayed_11; +wire [`DWIDTH-1:0] b22_data_delayed_12; +wire [`DWIDTH-1:0] b22_data_delayed_13; +wire [`DWIDTH-1:0] b22_data_delayed_14; +wire [`DWIDTH-1:0] b22_data_delayed_15; +wire [`DWIDTH-1:0] b22_data_delayed_16; +wire [`DWIDTH-1:0] b22_data_delayed_17; +wire [`DWIDTH-1:0] b22_data_delayed_18; +wire [`DWIDTH-1:0] b22_data_delayed_19; +wire [`DWIDTH-1:0] b22_data_delayed_20; +wire [`DWIDTH-1:0] b22_data_delayed_21; +wire [`DWIDTH-1:0] b22_data_delayed_22; +wire [`DWIDTH-1:0] b23_data_delayed_1; +wire [`DWIDTH-1:0] b23_data_delayed_2; +wire [`DWIDTH-1:0] b23_data_delayed_3; +wire [`DWIDTH-1:0] b23_data_delayed_4; +wire [`DWIDTH-1:0] b23_data_delayed_5; +wire [`DWIDTH-1:0] b23_data_delayed_6; +wire [`DWIDTH-1:0] b23_data_delayed_7; +wire [`DWIDTH-1:0] b23_data_delayed_8; +wire [`DWIDTH-1:0] b23_data_delayed_9; +wire [`DWIDTH-1:0] b23_data_delayed_10; +wire [`DWIDTH-1:0] b23_data_delayed_11; +wire [`DWIDTH-1:0] b23_data_delayed_12; +wire [`DWIDTH-1:0] b23_data_delayed_13; +wire [`DWIDTH-1:0] b23_data_delayed_14; +wire [`DWIDTH-1:0] b23_data_delayed_15; +wire [`DWIDTH-1:0] b23_data_delayed_16; +wire [`DWIDTH-1:0] b23_data_delayed_17; +wire [`DWIDTH-1:0] b23_data_delayed_18; +wire [`DWIDTH-1:0] b23_data_delayed_19; +wire [`DWIDTH-1:0] b23_data_delayed_20; +wire [`DWIDTH-1:0] b23_data_delayed_21; +wire [`DWIDTH-1:0] b23_data_delayed_22; +wire [`DWIDTH-1:0] b23_data_delayed_23; +wire [`DWIDTH-1:0] b24_data_delayed_1; +wire [`DWIDTH-1:0] b24_data_delayed_2; +wire [`DWIDTH-1:0] b24_data_delayed_3; +wire [`DWIDTH-1:0] b24_data_delayed_4; +wire [`DWIDTH-1:0] b24_data_delayed_5; +wire [`DWIDTH-1:0] b24_data_delayed_6; +wire [`DWIDTH-1:0] b24_data_delayed_7; +wire [`DWIDTH-1:0] b24_data_delayed_8; +wire [`DWIDTH-1:0] b24_data_delayed_9; +wire [`DWIDTH-1:0] b24_data_delayed_10; +wire [`DWIDTH-1:0] b24_data_delayed_11; +wire [`DWIDTH-1:0] b24_data_delayed_12; +wire [`DWIDTH-1:0] b24_data_delayed_13; +wire [`DWIDTH-1:0] b24_data_delayed_14; +wire [`DWIDTH-1:0] b24_data_delayed_15; +wire [`DWIDTH-1:0] b24_data_delayed_16; +wire [`DWIDTH-1:0] b24_data_delayed_17; +wire [`DWIDTH-1:0] b24_data_delayed_18; +wire [`DWIDTH-1:0] b24_data_delayed_19; +wire [`DWIDTH-1:0] b24_data_delayed_20; +wire [`DWIDTH-1:0] b24_data_delayed_21; +wire [`DWIDTH-1:0] b24_data_delayed_22; +wire [`DWIDTH-1:0] b24_data_delayed_23; +wire [`DWIDTH-1:0] b24_data_delayed_24; +wire [`DWIDTH-1:0] b25_data_delayed_1; +wire [`DWIDTH-1:0] b25_data_delayed_2; +wire [`DWIDTH-1:0] b25_data_delayed_3; +wire [`DWIDTH-1:0] b25_data_delayed_4; +wire [`DWIDTH-1:0] b25_data_delayed_5; +wire [`DWIDTH-1:0] b25_data_delayed_6; +wire [`DWIDTH-1:0] b25_data_delayed_7; +wire [`DWIDTH-1:0] b25_data_delayed_8; +wire [`DWIDTH-1:0] b25_data_delayed_9; +wire [`DWIDTH-1:0] b25_data_delayed_10; +wire [`DWIDTH-1:0] b25_data_delayed_11; +wire [`DWIDTH-1:0] b25_data_delayed_12; +wire [`DWIDTH-1:0] b25_data_delayed_13; +wire [`DWIDTH-1:0] b25_data_delayed_14; +wire [`DWIDTH-1:0] b25_data_delayed_15; +wire [`DWIDTH-1:0] b25_data_delayed_16; +wire [`DWIDTH-1:0] b25_data_delayed_17; +wire [`DWIDTH-1:0] b25_data_delayed_18; +wire [`DWIDTH-1:0] b25_data_delayed_19; +wire [`DWIDTH-1:0] b25_data_delayed_20; +wire [`DWIDTH-1:0] b25_data_delayed_21; +wire [`DWIDTH-1:0] b25_data_delayed_22; +wire [`DWIDTH-1:0] b25_data_delayed_23; +wire [`DWIDTH-1:0] b25_data_delayed_24; +wire [`DWIDTH-1:0] b25_data_delayed_25; +wire [`DWIDTH-1:0] b26_data_delayed_1; +wire [`DWIDTH-1:0] b26_data_delayed_2; +wire [`DWIDTH-1:0] b26_data_delayed_3; +wire [`DWIDTH-1:0] b26_data_delayed_4; +wire [`DWIDTH-1:0] b26_data_delayed_5; +wire [`DWIDTH-1:0] b26_data_delayed_6; +wire [`DWIDTH-1:0] b26_data_delayed_7; +wire [`DWIDTH-1:0] b26_data_delayed_8; +wire [`DWIDTH-1:0] b26_data_delayed_9; +wire [`DWIDTH-1:0] b26_data_delayed_10; +wire [`DWIDTH-1:0] b26_data_delayed_11; +wire [`DWIDTH-1:0] b26_data_delayed_12; +wire [`DWIDTH-1:0] b26_data_delayed_13; +wire [`DWIDTH-1:0] b26_data_delayed_14; +wire [`DWIDTH-1:0] b26_data_delayed_15; +wire [`DWIDTH-1:0] b26_data_delayed_16; +wire [`DWIDTH-1:0] b26_data_delayed_17; +wire [`DWIDTH-1:0] b26_data_delayed_18; +wire [`DWIDTH-1:0] b26_data_delayed_19; +wire [`DWIDTH-1:0] b26_data_delayed_20; +wire [`DWIDTH-1:0] b26_data_delayed_21; +wire [`DWIDTH-1:0] b26_data_delayed_22; +wire [`DWIDTH-1:0] b26_data_delayed_23; +wire [`DWIDTH-1:0] b26_data_delayed_24; +wire [`DWIDTH-1:0] b26_data_delayed_25; +wire [`DWIDTH-1:0] b26_data_delayed_26; +wire [`DWIDTH-1:0] b27_data_delayed_1; +wire [`DWIDTH-1:0] b27_data_delayed_2; +wire [`DWIDTH-1:0] b27_data_delayed_3; +wire [`DWIDTH-1:0] b27_data_delayed_4; +wire [`DWIDTH-1:0] b27_data_delayed_5; +wire [`DWIDTH-1:0] b27_data_delayed_6; +wire [`DWIDTH-1:0] b27_data_delayed_7; +wire [`DWIDTH-1:0] b27_data_delayed_8; +wire [`DWIDTH-1:0] b27_data_delayed_9; +wire [`DWIDTH-1:0] b27_data_delayed_10; +wire [`DWIDTH-1:0] b27_data_delayed_11; +wire [`DWIDTH-1:0] b27_data_delayed_12; +wire [`DWIDTH-1:0] b27_data_delayed_13; +wire [`DWIDTH-1:0] b27_data_delayed_14; +wire [`DWIDTH-1:0] b27_data_delayed_15; +wire [`DWIDTH-1:0] b27_data_delayed_16; +wire [`DWIDTH-1:0] b27_data_delayed_17; +wire [`DWIDTH-1:0] b27_data_delayed_18; +wire [`DWIDTH-1:0] b27_data_delayed_19; +wire [`DWIDTH-1:0] b27_data_delayed_20; +wire [`DWIDTH-1:0] b27_data_delayed_21; +wire [`DWIDTH-1:0] b27_data_delayed_22; +wire [`DWIDTH-1:0] b27_data_delayed_23; +wire [`DWIDTH-1:0] b27_data_delayed_24; +wire [`DWIDTH-1:0] b27_data_delayed_25; +wire [`DWIDTH-1:0] b27_data_delayed_26; +wire [`DWIDTH-1:0] b27_data_delayed_27; +wire [`DWIDTH-1:0] b28_data_delayed_1; +wire [`DWIDTH-1:0] b28_data_delayed_2; +wire [`DWIDTH-1:0] b28_data_delayed_3; +wire [`DWIDTH-1:0] b28_data_delayed_4; +wire [`DWIDTH-1:0] b28_data_delayed_5; +wire [`DWIDTH-1:0] b28_data_delayed_6; +wire [`DWIDTH-1:0] b28_data_delayed_7; +wire [`DWIDTH-1:0] b28_data_delayed_8; +wire [`DWIDTH-1:0] b28_data_delayed_9; +wire [`DWIDTH-1:0] b28_data_delayed_10; +wire [`DWIDTH-1:0] b28_data_delayed_11; +wire [`DWIDTH-1:0] b28_data_delayed_12; +wire [`DWIDTH-1:0] b28_data_delayed_13; +wire [`DWIDTH-1:0] b28_data_delayed_14; +wire [`DWIDTH-1:0] b28_data_delayed_15; +wire [`DWIDTH-1:0] b28_data_delayed_16; +wire [`DWIDTH-1:0] b28_data_delayed_17; +wire [`DWIDTH-1:0] b28_data_delayed_18; +wire [`DWIDTH-1:0] b28_data_delayed_19; +wire [`DWIDTH-1:0] b28_data_delayed_20; +wire [`DWIDTH-1:0] b28_data_delayed_21; +wire [`DWIDTH-1:0] b28_data_delayed_22; +wire [`DWIDTH-1:0] b28_data_delayed_23; +wire [`DWIDTH-1:0] b28_data_delayed_24; +wire [`DWIDTH-1:0] b28_data_delayed_25; +wire [`DWIDTH-1:0] b28_data_delayed_26; +wire [`DWIDTH-1:0] b28_data_delayed_27; +wire [`DWIDTH-1:0] b28_data_delayed_28; +wire [`DWIDTH-1:0] b29_data_delayed_1; +wire [`DWIDTH-1:0] b29_data_delayed_2; +wire [`DWIDTH-1:0] b29_data_delayed_3; +wire [`DWIDTH-1:0] b29_data_delayed_4; +wire [`DWIDTH-1:0] b29_data_delayed_5; +wire [`DWIDTH-1:0] b29_data_delayed_6; +wire [`DWIDTH-1:0] b29_data_delayed_7; +wire [`DWIDTH-1:0] b29_data_delayed_8; +wire [`DWIDTH-1:0] b29_data_delayed_9; +wire [`DWIDTH-1:0] b29_data_delayed_10; +wire [`DWIDTH-1:0] b29_data_delayed_11; +wire [`DWIDTH-1:0] b29_data_delayed_12; +wire [`DWIDTH-1:0] b29_data_delayed_13; +wire [`DWIDTH-1:0] b29_data_delayed_14; +wire [`DWIDTH-1:0] b29_data_delayed_15; +wire [`DWIDTH-1:0] b29_data_delayed_16; +wire [`DWIDTH-1:0] b29_data_delayed_17; +wire [`DWIDTH-1:0] b29_data_delayed_18; +wire [`DWIDTH-1:0] b29_data_delayed_19; +wire [`DWIDTH-1:0] b29_data_delayed_20; +wire [`DWIDTH-1:0] b29_data_delayed_21; +wire [`DWIDTH-1:0] b29_data_delayed_22; +wire [`DWIDTH-1:0] b29_data_delayed_23; +wire [`DWIDTH-1:0] b29_data_delayed_24; +wire [`DWIDTH-1:0] b29_data_delayed_25; +wire [`DWIDTH-1:0] b29_data_delayed_26; +wire [`DWIDTH-1:0] b29_data_delayed_27; +wire [`DWIDTH-1:0] b29_data_delayed_28; +wire [`DWIDTH-1:0] b29_data_delayed_29; +wire [`DWIDTH-1:0] b30_data_delayed_1; +wire [`DWIDTH-1:0] b30_data_delayed_2; +wire [`DWIDTH-1:0] b30_data_delayed_3; +wire [`DWIDTH-1:0] b30_data_delayed_4; +wire [`DWIDTH-1:0] b30_data_delayed_5; +wire [`DWIDTH-1:0] b30_data_delayed_6; +wire [`DWIDTH-1:0] b30_data_delayed_7; +wire [`DWIDTH-1:0] b30_data_delayed_8; +wire [`DWIDTH-1:0] b30_data_delayed_9; +wire [`DWIDTH-1:0] b30_data_delayed_10; +wire [`DWIDTH-1:0] b30_data_delayed_11; +wire [`DWIDTH-1:0] b30_data_delayed_12; +wire [`DWIDTH-1:0] b30_data_delayed_13; +wire [`DWIDTH-1:0] b30_data_delayed_14; +wire [`DWIDTH-1:0] b30_data_delayed_15; +wire [`DWIDTH-1:0] b30_data_delayed_16; +wire [`DWIDTH-1:0] b30_data_delayed_17; +wire [`DWIDTH-1:0] b30_data_delayed_18; +wire [`DWIDTH-1:0] b30_data_delayed_19; +wire [`DWIDTH-1:0] b30_data_delayed_20; +wire [`DWIDTH-1:0] b30_data_delayed_21; +wire [`DWIDTH-1:0] b30_data_delayed_22; +wire [`DWIDTH-1:0] b30_data_delayed_23; +wire [`DWIDTH-1:0] b30_data_delayed_24; +wire [`DWIDTH-1:0] b30_data_delayed_25; +wire [`DWIDTH-1:0] b30_data_delayed_26; +wire [`DWIDTH-1:0] b30_data_delayed_27; +wire [`DWIDTH-1:0] b30_data_delayed_28; +wire [`DWIDTH-1:0] b30_data_delayed_29; +wire [`DWIDTH-1:0] b30_data_delayed_30; +wire [`DWIDTH-1:0] b31_data_delayed_1; +wire [`DWIDTH-1:0] b31_data_delayed_2; +wire [`DWIDTH-1:0] b31_data_delayed_3; +wire [`DWIDTH-1:0] b31_data_delayed_4; +wire [`DWIDTH-1:0] b31_data_delayed_5; +wire [`DWIDTH-1:0] b31_data_delayed_6; +wire [`DWIDTH-1:0] b31_data_delayed_7; +wire [`DWIDTH-1:0] b31_data_delayed_8; +wire [`DWIDTH-1:0] b31_data_delayed_9; +wire [`DWIDTH-1:0] b31_data_delayed_10; +wire [`DWIDTH-1:0] b31_data_delayed_11; +wire [`DWIDTH-1:0] b31_data_delayed_12; +wire [`DWIDTH-1:0] b31_data_delayed_13; +wire [`DWIDTH-1:0] b31_data_delayed_14; +wire [`DWIDTH-1:0] b31_data_delayed_15; +wire [`DWIDTH-1:0] b31_data_delayed_16; +wire [`DWIDTH-1:0] b31_data_delayed_17; +wire [`DWIDTH-1:0] b31_data_delayed_18; +wire [`DWIDTH-1:0] b31_data_delayed_19; +wire [`DWIDTH-1:0] b31_data_delayed_20; +wire [`DWIDTH-1:0] b31_data_delayed_21; +wire [`DWIDTH-1:0] b31_data_delayed_22; +wire [`DWIDTH-1:0] b31_data_delayed_23; +wire [`DWIDTH-1:0] b31_data_delayed_24; +wire [`DWIDTH-1:0] b31_data_delayed_25; +wire [`DWIDTH-1:0] b31_data_delayed_26; +wire [`DWIDTH-1:0] b31_data_delayed_27; +wire [`DWIDTH-1:0] b31_data_delayed_28; +wire [`DWIDTH-1:0] b31_data_delayed_29; +wire [`DWIDTH-1:0] b31_data_delayed_30; +wire [`DWIDTH-1:0] b31_data_delayed_31; + + +////////////////////////////////////////////////////////////////////////// +// Instantiation of systolic data setup +////////////////////////////////////////////////////////////////////////// +systolic_data_setup u_systolic_data_setup( +.clk(clk), +.reset(reset), +.start_mat_mul(start_mat_mul), +.a_addr(a_addr), +.b_addr(b_addr), +.address_mat_a(address_mat_a), +.address_mat_b(address_mat_b), +.address_stride_a(address_stride_a), +.address_stride_b(address_stride_b), +.a_data(a_data), +.b_data(b_data), +.clk_cnt(clk_cnt), +.a0_data(a0_data), +.b0_data(b0_data), +.a1_data_delayed_1(a1_data_delayed_1), +.b1_data_delayed_1(b1_data_delayed_1), +.a2_data_delayed_2(a2_data_delayed_2), +.b2_data_delayed_2(b2_data_delayed_2), +.a3_data_delayed_3(a3_data_delayed_3), +.b3_data_delayed_3(b3_data_delayed_3), +.a4_data_delayed_4(a4_data_delayed_4), +.b4_data_delayed_4(b4_data_delayed_4), +.a5_data_delayed_5(a5_data_delayed_5), +.b5_data_delayed_5(b5_data_delayed_5), +.a6_data_delayed_6(a6_data_delayed_6), +.b6_data_delayed_6(b6_data_delayed_6), +.a7_data_delayed_7(a7_data_delayed_7), +.b7_data_delayed_7(b7_data_delayed_7), +.a8_data_delayed_8(a8_data_delayed_8), +.b8_data_delayed_8(b8_data_delayed_8), +.a9_data_delayed_9(a9_data_delayed_9), +.b9_data_delayed_9(b9_data_delayed_9), +.a10_data_delayed_10(a10_data_delayed_10), +.b10_data_delayed_10(b10_data_delayed_10), +.a11_data_delayed_11(a11_data_delayed_11), +.b11_data_delayed_11(b11_data_delayed_11), +.a12_data_delayed_12(a12_data_delayed_12), +.b12_data_delayed_12(b12_data_delayed_12), +.a13_data_delayed_13(a13_data_delayed_13), +.b13_data_delayed_13(b13_data_delayed_13), +.a14_data_delayed_14(a14_data_delayed_14), +.b14_data_delayed_14(b14_data_delayed_14), +.a15_data_delayed_15(a15_data_delayed_15), +.b15_data_delayed_15(b15_data_delayed_15), +.a16_data_delayed_16(a16_data_delayed_16), +.b16_data_delayed_16(b16_data_delayed_16), +.a17_data_delayed_17(a17_data_delayed_17), +.b17_data_delayed_17(b17_data_delayed_17), +.a18_data_delayed_18(a18_data_delayed_18), +.b18_data_delayed_18(b18_data_delayed_18), +.a19_data_delayed_19(a19_data_delayed_19), +.b19_data_delayed_19(b19_data_delayed_19), +.a20_data_delayed_20(a20_data_delayed_20), +.b20_data_delayed_20(b20_data_delayed_20), +.a21_data_delayed_21(a21_data_delayed_21), +.b21_data_delayed_21(b21_data_delayed_21), +.a22_data_delayed_22(a22_data_delayed_22), +.b22_data_delayed_22(b22_data_delayed_22), +.a23_data_delayed_23(a23_data_delayed_23), +.b23_data_delayed_23(b23_data_delayed_23), +.a24_data_delayed_24(a24_data_delayed_24), +.b24_data_delayed_24(b24_data_delayed_24), +.a25_data_delayed_25(a25_data_delayed_25), +.b25_data_delayed_25(b25_data_delayed_25), +.a26_data_delayed_26(a26_data_delayed_26), +.b26_data_delayed_26(b26_data_delayed_26), +.a27_data_delayed_27(a27_data_delayed_27), +.b27_data_delayed_27(b27_data_delayed_27), +.a28_data_delayed_28(a28_data_delayed_28), +.b28_data_delayed_28(b28_data_delayed_28), +.a29_data_delayed_29(a29_data_delayed_29), +.b29_data_delayed_29(b29_data_delayed_29), +.a30_data_delayed_30(a30_data_delayed_30), +.b30_data_delayed_30(b30_data_delayed_30), +.a31_data_delayed_31(a31_data_delayed_31), +.b31_data_delayed_31(b31_data_delayed_31), + +.validity_mask_a_rows(validity_mask_a_rows), +.validity_mask_a_cols(validity_mask_a_cols), +.validity_mask_b_rows(validity_mask_b_rows), +.validity_mask_b_cols(validity_mask_b_cols), + +.final_mat_mul_size(final_mat_mul_size), + +.a_loc(a_loc), +.b_loc(b_loc) +); + +////////////////////////////////////////////////////////////////////////// +// Logic to mux data_in coming from neighboring matmuls +////////////////////////////////////////////////////////////////////////// +wire [`DWIDTH-1:0] a0; +wire [`DWIDTH-1:0] a1; +wire [`DWIDTH-1:0] a2; +wire [`DWIDTH-1:0] a3; +wire [`DWIDTH-1:0] a4; +wire [`DWIDTH-1:0] a5; +wire [`DWIDTH-1:0] a6; +wire [`DWIDTH-1:0] a7; +wire [`DWIDTH-1:0] a8; +wire [`DWIDTH-1:0] a9; +wire [`DWIDTH-1:0] a10; +wire [`DWIDTH-1:0] a11; +wire [`DWIDTH-1:0] a12; +wire [`DWIDTH-1:0] a13; +wire [`DWIDTH-1:0] a14; +wire [`DWIDTH-1:0] a15; +wire [`DWIDTH-1:0] a16; +wire [`DWIDTH-1:0] a17; +wire [`DWIDTH-1:0] a18; +wire [`DWIDTH-1:0] a19; +wire [`DWIDTH-1:0] a20; +wire [`DWIDTH-1:0] a21; +wire [`DWIDTH-1:0] a22; +wire [`DWIDTH-1:0] a23; +wire [`DWIDTH-1:0] a24; +wire [`DWIDTH-1:0] a25; +wire [`DWIDTH-1:0] a26; +wire [`DWIDTH-1:0] a27; +wire [`DWIDTH-1:0] a28; +wire [`DWIDTH-1:0] a29; +wire [`DWIDTH-1:0] a30; +wire [`DWIDTH-1:0] a31; +wire [`DWIDTH-1:0] b0; +wire [`DWIDTH-1:0] b1; +wire [`DWIDTH-1:0] b2; +wire [`DWIDTH-1:0] b3; +wire [`DWIDTH-1:0] b4; +wire [`DWIDTH-1:0] b5; +wire [`DWIDTH-1:0] b6; +wire [`DWIDTH-1:0] b7; +wire [`DWIDTH-1:0] b8; +wire [`DWIDTH-1:0] b9; +wire [`DWIDTH-1:0] b10; +wire [`DWIDTH-1:0] b11; +wire [`DWIDTH-1:0] b12; +wire [`DWIDTH-1:0] b13; +wire [`DWIDTH-1:0] b14; +wire [`DWIDTH-1:0] b15; +wire [`DWIDTH-1:0] b16; +wire [`DWIDTH-1:0] b17; +wire [`DWIDTH-1:0] b18; +wire [`DWIDTH-1:0] b19; +wire [`DWIDTH-1:0] b20; +wire [`DWIDTH-1:0] b21; +wire [`DWIDTH-1:0] b22; +wire [`DWIDTH-1:0] b23; +wire [`DWIDTH-1:0] b24; +wire [`DWIDTH-1:0] b25; +wire [`DWIDTH-1:0] b26; +wire [`DWIDTH-1:0] b27; +wire [`DWIDTH-1:0] b28; +wire [`DWIDTH-1:0] b29; +wire [`DWIDTH-1:0] b30; +wire [`DWIDTH-1:0] b31; + +wire [`DWIDTH-1:0] a0_data_in; +wire [`DWIDTH-1:0] a1_data_in; +wire [`DWIDTH-1:0] a2_data_in; +wire [`DWIDTH-1:0] a3_data_in; +wire [`DWIDTH-1:0] a4_data_in; +wire [`DWIDTH-1:0] a5_data_in; +wire [`DWIDTH-1:0] a6_data_in; +wire [`DWIDTH-1:0] a7_data_in; +wire [`DWIDTH-1:0] a8_data_in; +wire [`DWIDTH-1:0] a9_data_in; +wire [`DWIDTH-1:0] a10_data_in; +wire [`DWIDTH-1:0] a11_data_in; +wire [`DWIDTH-1:0] a12_data_in; +wire [`DWIDTH-1:0] a13_data_in; +wire [`DWIDTH-1:0] a14_data_in; +wire [`DWIDTH-1:0] a15_data_in; +wire [`DWIDTH-1:0] a16_data_in; +wire [`DWIDTH-1:0] a17_data_in; +wire [`DWIDTH-1:0] a18_data_in; +wire [`DWIDTH-1:0] a19_data_in; +wire [`DWIDTH-1:0] a20_data_in; +wire [`DWIDTH-1:0] a21_data_in; +wire [`DWIDTH-1:0] a22_data_in; +wire [`DWIDTH-1:0] a23_data_in; +wire [`DWIDTH-1:0] a24_data_in; +wire [`DWIDTH-1:0] a25_data_in; +wire [`DWIDTH-1:0] a26_data_in; +wire [`DWIDTH-1:0] a27_data_in; +wire [`DWIDTH-1:0] a28_data_in; +wire [`DWIDTH-1:0] a29_data_in; +wire [`DWIDTH-1:0] a30_data_in; +wire [`DWIDTH-1:0] a31_data_in; + +assign a0_data_in = a_data_in[1*`DWIDTH-1:0*`DWIDTH]; +assign a1_data_in = a_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign a2_data_in = a_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign a3_data_in = a_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign a4_data_in = a_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign a5_data_in = a_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign a6_data_in = a_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign a7_data_in = a_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign a8_data_in = a_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign a9_data_in = a_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign a10_data_in = a_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign a11_data_in = a_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign a12_data_in = a_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign a13_data_in = a_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign a14_data_in = a_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign a15_data_in = a_data_in[16*`DWIDTH-1:15*`DWIDTH]; +assign a16_data_in = a_data_in[17*`DWIDTH-1:16*`DWIDTH]; +assign a17_data_in = a_data_in[18*`DWIDTH-1:17*`DWIDTH]; +assign a18_data_in = a_data_in[19*`DWIDTH-1:18*`DWIDTH]; +assign a19_data_in = a_data_in[20*`DWIDTH-1:19*`DWIDTH]; +assign a20_data_in = a_data_in[21*`DWIDTH-1:20*`DWIDTH]; +assign a21_data_in = a_data_in[22*`DWIDTH-1:21*`DWIDTH]; +assign a22_data_in = a_data_in[23*`DWIDTH-1:22*`DWIDTH]; +assign a23_data_in = a_data_in[24*`DWIDTH-1:23*`DWIDTH]; +assign a24_data_in = a_data_in[25*`DWIDTH-1:24*`DWIDTH]; +assign a25_data_in = a_data_in[26*`DWIDTH-1:25*`DWIDTH]; +assign a26_data_in = a_data_in[27*`DWIDTH-1:26*`DWIDTH]; +assign a27_data_in = a_data_in[28*`DWIDTH-1:27*`DWIDTH]; +assign a28_data_in = a_data_in[29*`DWIDTH-1:28*`DWIDTH]; +assign a29_data_in = a_data_in[30*`DWIDTH-1:29*`DWIDTH]; +assign a30_data_in = a_data_in[31*`DWIDTH-1:30*`DWIDTH]; +assign a31_data_in = a_data_in[32*`DWIDTH-1:31*`DWIDTH]; + +wire [`DWIDTH-1:0] b0_data_in; +wire [`DWIDTH-1:0] b1_data_in; +wire [`DWIDTH-1:0] b2_data_in; +wire [`DWIDTH-1:0] b3_data_in; +wire [`DWIDTH-1:0] b4_data_in; +wire [`DWIDTH-1:0] b5_data_in; +wire [`DWIDTH-1:0] b6_data_in; +wire [`DWIDTH-1:0] b7_data_in; +wire [`DWIDTH-1:0] b8_data_in; +wire [`DWIDTH-1:0] b9_data_in; +wire [`DWIDTH-1:0] b10_data_in; +wire [`DWIDTH-1:0] b11_data_in; +wire [`DWIDTH-1:0] b12_data_in; +wire [`DWIDTH-1:0] b13_data_in; +wire [`DWIDTH-1:0] b14_data_in; +wire [`DWIDTH-1:0] b15_data_in; +wire [`DWIDTH-1:0] b16_data_in; +wire [`DWIDTH-1:0] b17_data_in; +wire [`DWIDTH-1:0] b18_data_in; +wire [`DWIDTH-1:0] b19_data_in; +wire [`DWIDTH-1:0] b20_data_in; +wire [`DWIDTH-1:0] b21_data_in; +wire [`DWIDTH-1:0] b22_data_in; +wire [`DWIDTH-1:0] b23_data_in; +wire [`DWIDTH-1:0] b24_data_in; +wire [`DWIDTH-1:0] b25_data_in; +wire [`DWIDTH-1:0] b26_data_in; +wire [`DWIDTH-1:0] b27_data_in; +wire [`DWIDTH-1:0] b28_data_in; +wire [`DWIDTH-1:0] b29_data_in; +wire [`DWIDTH-1:0] b30_data_in; +wire [`DWIDTH-1:0] b31_data_in; + +assign b0_data_in = b_data_in[1*`DWIDTH-1:0*`DWIDTH]; +assign b1_data_in = b_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign b2_data_in = b_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign b3_data_in = b_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign b4_data_in = b_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign b5_data_in = b_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign b6_data_in = b_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign b7_data_in = b_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign b8_data_in = b_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign b9_data_in = b_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign b10_data_in = b_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign b11_data_in = b_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign b12_data_in = b_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign b13_data_in = b_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign b14_data_in = b_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign b15_data_in = b_data_in[16*`DWIDTH-1:15*`DWIDTH]; +assign b16_data_in = b_data_in[17*`DWIDTH-1:16*`DWIDTH]; +assign b17_data_in = b_data_in[18*`DWIDTH-1:17*`DWIDTH]; +assign b18_data_in = b_data_in[19*`DWIDTH-1:18*`DWIDTH]; +assign b19_data_in = b_data_in[20*`DWIDTH-1:19*`DWIDTH]; +assign b20_data_in = b_data_in[21*`DWIDTH-1:20*`DWIDTH]; +assign b21_data_in = b_data_in[22*`DWIDTH-1:21*`DWIDTH]; +assign b22_data_in = b_data_in[23*`DWIDTH-1:22*`DWIDTH]; +assign b23_data_in = b_data_in[24*`DWIDTH-1:23*`DWIDTH]; +assign b24_data_in = b_data_in[25*`DWIDTH-1:24*`DWIDTH]; +assign b25_data_in = b_data_in[26*`DWIDTH-1:25*`DWIDTH]; +assign b26_data_in = b_data_in[27*`DWIDTH-1:26*`DWIDTH]; +assign b27_data_in = b_data_in[28*`DWIDTH-1:27*`DWIDTH]; +assign b28_data_in = b_data_in[29*`DWIDTH-1:28*`DWIDTH]; +assign b29_data_in = b_data_in[30*`DWIDTH-1:29*`DWIDTH]; +assign b30_data_in = b_data_in[31*`DWIDTH-1:30*`DWIDTH]; +assign b31_data_in = b_data_in[32*`DWIDTH-1:31*`DWIDTH]; + +assign a0 = (b_loc==0) ? a0_data : a0_data_in; +assign a1 = (b_loc==0) ? a1_data_delayed_1 : a1_data_in; +assign a2 = (b_loc==0) ? a2_data_delayed_2 : a2_data_in; +assign a3 = (b_loc==0) ? a3_data_delayed_3 : a3_data_in; +assign a4 = (b_loc==0) ? a4_data_delayed_4 : a4_data_in; +assign a5 = (b_loc==0) ? a5_data_delayed_5 : a5_data_in; +assign a6 = (b_loc==0) ? a6_data_delayed_6 : a6_data_in; +assign a7 = (b_loc==0) ? a7_data_delayed_7 : a7_data_in; +assign a8 = (b_loc==0) ? a8_data_delayed_8 : a8_data_in; +assign a9 = (b_loc==0) ? a9_data_delayed_9 : a9_data_in; +assign a10 = (b_loc==0) ? a10_data_delayed_10 : a10_data_in; +assign a11 = (b_loc==0) ? a11_data_delayed_11 : a11_data_in; +assign a12 = (b_loc==0) ? a12_data_delayed_12 : a12_data_in; +assign a13 = (b_loc==0) ? a13_data_delayed_13 : a13_data_in; +assign a14 = (b_loc==0) ? a14_data_delayed_14 : a14_data_in; +assign a15 = (b_loc==0) ? a15_data_delayed_15 : a15_data_in; +assign a16 = (b_loc==0) ? a16_data_delayed_16 : a16_data_in; +assign a17 = (b_loc==0) ? a17_data_delayed_17 : a17_data_in; +assign a18 = (b_loc==0) ? a18_data_delayed_18 : a18_data_in; +assign a19 = (b_loc==0) ? a19_data_delayed_19 : a19_data_in; +assign a20 = (b_loc==0) ? a20_data_delayed_20 : a20_data_in; +assign a21 = (b_loc==0) ? a21_data_delayed_21 : a21_data_in; +assign a22 = (b_loc==0) ? a22_data_delayed_22 : a22_data_in; +assign a23 = (b_loc==0) ? a23_data_delayed_23 : a23_data_in; +assign a24 = (b_loc==0) ? a24_data_delayed_24 : a24_data_in; +assign a25 = (b_loc==0) ? a25_data_delayed_25 : a25_data_in; +assign a26 = (b_loc==0) ? a26_data_delayed_26 : a26_data_in; +assign a27 = (b_loc==0) ? a27_data_delayed_27 : a27_data_in; +assign a28 = (b_loc==0) ? a28_data_delayed_28 : a28_data_in; +assign a29 = (b_loc==0) ? a29_data_delayed_29 : a29_data_in; +assign a30 = (b_loc==0) ? a30_data_delayed_30 : a30_data_in; +assign a31 = (b_loc==0) ? a31_data_delayed_31 : a31_data_in; + +assign b0 = (a_loc==0) ? b0_data : b0_data_in; +assign b1 = (a_loc==0) ? b1_data_delayed_1 : b1_data_in; +assign b2 = (a_loc==0) ? b2_data_delayed_2 : b2_data_in; +assign b3 = (a_loc==0) ? b3_data_delayed_3 : b3_data_in; +assign b4 = (a_loc==0) ? b4_data_delayed_4 : b4_data_in; +assign b5 = (a_loc==0) ? b5_data_delayed_5 : b5_data_in; +assign b6 = (a_loc==0) ? b6_data_delayed_6 : b6_data_in; +assign b7 = (a_loc==0) ? b7_data_delayed_7 : b7_data_in; +assign b8 = (a_loc==0) ? b8_data_delayed_8 : b8_data_in; +assign b9 = (a_loc==0) ? b9_data_delayed_9 : b9_data_in; +assign b10 = (a_loc==0) ? b10_data_delayed_10 : b10_data_in; +assign b11 = (a_loc==0) ? b11_data_delayed_11 : b11_data_in; +assign b12 = (a_loc==0) ? b12_data_delayed_12 : b12_data_in; +assign b13 = (a_loc==0) ? b13_data_delayed_13 : b13_data_in; +assign b14 = (a_loc==0) ? b14_data_delayed_14 : b14_data_in; +assign b15 = (a_loc==0) ? b15_data_delayed_15 : b15_data_in; +assign b16 = (a_loc==0) ? b16_data_delayed_16 : b16_data_in; +assign b17 = (a_loc==0) ? b17_data_delayed_17 : b17_data_in; +assign b18 = (a_loc==0) ? b18_data_delayed_18 : b18_data_in; +assign b19 = (a_loc==0) ? b19_data_delayed_19 : b19_data_in; +assign b20 = (a_loc==0) ? b20_data_delayed_20 : b20_data_in; +assign b21 = (a_loc==0) ? b21_data_delayed_21 : b21_data_in; +assign b22 = (a_loc==0) ? b22_data_delayed_22 : b22_data_in; +assign b23 = (a_loc==0) ? b23_data_delayed_23 : b23_data_in; +assign b24 = (a_loc==0) ? b24_data_delayed_24 : b24_data_in; +assign b25 = (a_loc==0) ? b25_data_delayed_25 : b25_data_in; +assign b26 = (a_loc==0) ? b26_data_delayed_26 : b26_data_in; +assign b27 = (a_loc==0) ? b27_data_delayed_27 : b27_data_in; +assign b28 = (a_loc==0) ? b28_data_delayed_28 : b28_data_in; +assign b29 = (a_loc==0) ? b29_data_delayed_29 : b29_data_in; +assign b30 = (a_loc==0) ? b30_data_delayed_30 : b30_data_in; +assign b31 = (a_loc==0) ? b31_data_delayed_31 : b31_data_in; + +wire [`DWIDTH-1:0] matrixC0_0; +wire [`DWIDTH-1:0] matrixC0_1; +wire [`DWIDTH-1:0] matrixC0_2; +wire [`DWIDTH-1:0] matrixC0_3; +wire [`DWIDTH-1:0] matrixC0_4; +wire [`DWIDTH-1:0] matrixC0_5; +wire [`DWIDTH-1:0] matrixC0_6; +wire [`DWIDTH-1:0] matrixC0_7; +wire [`DWIDTH-1:0] matrixC0_8; +wire [`DWIDTH-1:0] matrixC0_9; +wire [`DWIDTH-1:0] matrixC0_10; +wire [`DWIDTH-1:0] matrixC0_11; +wire [`DWIDTH-1:0] matrixC0_12; +wire [`DWIDTH-1:0] matrixC0_13; +wire [`DWIDTH-1:0] matrixC0_14; +wire [`DWIDTH-1:0] matrixC0_15; +wire [`DWIDTH-1:0] matrixC0_16; +wire [`DWIDTH-1:0] matrixC0_17; +wire [`DWIDTH-1:0] matrixC0_18; +wire [`DWIDTH-1:0] matrixC0_19; +wire [`DWIDTH-1:0] matrixC0_20; +wire [`DWIDTH-1:0] matrixC0_21; +wire [`DWIDTH-1:0] matrixC0_22; +wire [`DWIDTH-1:0] matrixC0_23; +wire [`DWIDTH-1:0] matrixC0_24; +wire [`DWIDTH-1:0] matrixC0_25; +wire [`DWIDTH-1:0] matrixC0_26; +wire [`DWIDTH-1:0] matrixC0_27; +wire [`DWIDTH-1:0] matrixC0_28; +wire [`DWIDTH-1:0] matrixC0_29; +wire [`DWIDTH-1:0] matrixC0_30; +wire [`DWIDTH-1:0] matrixC0_31; +wire [`DWIDTH-1:0] matrixC1_0; +wire [`DWIDTH-1:0] matrixC1_1; +wire [`DWIDTH-1:0] matrixC1_2; +wire [`DWIDTH-1:0] matrixC1_3; +wire [`DWIDTH-1:0] matrixC1_4; +wire [`DWIDTH-1:0] matrixC1_5; +wire [`DWIDTH-1:0] matrixC1_6; +wire [`DWIDTH-1:0] matrixC1_7; +wire [`DWIDTH-1:0] matrixC1_8; +wire [`DWIDTH-1:0] matrixC1_9; +wire [`DWIDTH-1:0] matrixC1_10; +wire [`DWIDTH-1:0] matrixC1_11; +wire [`DWIDTH-1:0] matrixC1_12; +wire [`DWIDTH-1:0] matrixC1_13; +wire [`DWIDTH-1:0] matrixC1_14; +wire [`DWIDTH-1:0] matrixC1_15; +wire [`DWIDTH-1:0] matrixC1_16; +wire [`DWIDTH-1:0] matrixC1_17; +wire [`DWIDTH-1:0] matrixC1_18; +wire [`DWIDTH-1:0] matrixC1_19; +wire [`DWIDTH-1:0] matrixC1_20; +wire [`DWIDTH-1:0] matrixC1_21; +wire [`DWIDTH-1:0] matrixC1_22; +wire [`DWIDTH-1:0] matrixC1_23; +wire [`DWIDTH-1:0] matrixC1_24; +wire [`DWIDTH-1:0] matrixC1_25; +wire [`DWIDTH-1:0] matrixC1_26; +wire [`DWIDTH-1:0] matrixC1_27; +wire [`DWIDTH-1:0] matrixC1_28; +wire [`DWIDTH-1:0] matrixC1_29; +wire [`DWIDTH-1:0] matrixC1_30; +wire [`DWIDTH-1:0] matrixC1_31; +wire [`DWIDTH-1:0] matrixC2_0; +wire [`DWIDTH-1:0] matrixC2_1; +wire [`DWIDTH-1:0] matrixC2_2; +wire [`DWIDTH-1:0] matrixC2_3; +wire [`DWIDTH-1:0] matrixC2_4; +wire [`DWIDTH-1:0] matrixC2_5; +wire [`DWIDTH-1:0] matrixC2_6; +wire [`DWIDTH-1:0] matrixC2_7; +wire [`DWIDTH-1:0] matrixC2_8; +wire [`DWIDTH-1:0] matrixC2_9; +wire [`DWIDTH-1:0] matrixC2_10; +wire [`DWIDTH-1:0] matrixC2_11; +wire [`DWIDTH-1:0] matrixC2_12; +wire [`DWIDTH-1:0] matrixC2_13; +wire [`DWIDTH-1:0] matrixC2_14; +wire [`DWIDTH-1:0] matrixC2_15; +wire [`DWIDTH-1:0] matrixC2_16; +wire [`DWIDTH-1:0] matrixC2_17; +wire [`DWIDTH-1:0] matrixC2_18; +wire [`DWIDTH-1:0] matrixC2_19; +wire [`DWIDTH-1:0] matrixC2_20; +wire [`DWIDTH-1:0] matrixC2_21; +wire [`DWIDTH-1:0] matrixC2_22; +wire [`DWIDTH-1:0] matrixC2_23; +wire [`DWIDTH-1:0] matrixC2_24; +wire [`DWIDTH-1:0] matrixC2_25; +wire [`DWIDTH-1:0] matrixC2_26; +wire [`DWIDTH-1:0] matrixC2_27; +wire [`DWIDTH-1:0] matrixC2_28; +wire [`DWIDTH-1:0] matrixC2_29; +wire [`DWIDTH-1:0] matrixC2_30; +wire [`DWIDTH-1:0] matrixC2_31; +wire [`DWIDTH-1:0] matrixC3_0; +wire [`DWIDTH-1:0] matrixC3_1; +wire [`DWIDTH-1:0] matrixC3_2; +wire [`DWIDTH-1:0] matrixC3_3; +wire [`DWIDTH-1:0] matrixC3_4; +wire [`DWIDTH-1:0] matrixC3_5; +wire [`DWIDTH-1:0] matrixC3_6; +wire [`DWIDTH-1:0] matrixC3_7; +wire [`DWIDTH-1:0] matrixC3_8; +wire [`DWIDTH-1:0] matrixC3_9; +wire [`DWIDTH-1:0] matrixC3_10; +wire [`DWIDTH-1:0] matrixC3_11; +wire [`DWIDTH-1:0] matrixC3_12; +wire [`DWIDTH-1:0] matrixC3_13; +wire [`DWIDTH-1:0] matrixC3_14; +wire [`DWIDTH-1:0] matrixC3_15; +wire [`DWIDTH-1:0] matrixC3_16; +wire [`DWIDTH-1:0] matrixC3_17; +wire [`DWIDTH-1:0] matrixC3_18; +wire [`DWIDTH-1:0] matrixC3_19; +wire [`DWIDTH-1:0] matrixC3_20; +wire [`DWIDTH-1:0] matrixC3_21; +wire [`DWIDTH-1:0] matrixC3_22; +wire [`DWIDTH-1:0] matrixC3_23; +wire [`DWIDTH-1:0] matrixC3_24; +wire [`DWIDTH-1:0] matrixC3_25; +wire [`DWIDTH-1:0] matrixC3_26; +wire [`DWIDTH-1:0] matrixC3_27; +wire [`DWIDTH-1:0] matrixC3_28; +wire [`DWIDTH-1:0] matrixC3_29; +wire [`DWIDTH-1:0] matrixC3_30; +wire [`DWIDTH-1:0] matrixC3_31; +wire [`DWIDTH-1:0] matrixC4_0; +wire [`DWIDTH-1:0] matrixC4_1; +wire [`DWIDTH-1:0] matrixC4_2; +wire [`DWIDTH-1:0] matrixC4_3; +wire [`DWIDTH-1:0] matrixC4_4; +wire [`DWIDTH-1:0] matrixC4_5; +wire [`DWIDTH-1:0] matrixC4_6; +wire [`DWIDTH-1:0] matrixC4_7; +wire [`DWIDTH-1:0] matrixC4_8; +wire [`DWIDTH-1:0] matrixC4_9; +wire [`DWIDTH-1:0] matrixC4_10; +wire [`DWIDTH-1:0] matrixC4_11; +wire [`DWIDTH-1:0] matrixC4_12; +wire [`DWIDTH-1:0] matrixC4_13; +wire [`DWIDTH-1:0] matrixC4_14; +wire [`DWIDTH-1:0] matrixC4_15; +wire [`DWIDTH-1:0] matrixC4_16; +wire [`DWIDTH-1:0] matrixC4_17; +wire [`DWIDTH-1:0] matrixC4_18; +wire [`DWIDTH-1:0] matrixC4_19; +wire [`DWIDTH-1:0] matrixC4_20; +wire [`DWIDTH-1:0] matrixC4_21; +wire [`DWIDTH-1:0] matrixC4_22; +wire [`DWIDTH-1:0] matrixC4_23; +wire [`DWIDTH-1:0] matrixC4_24; +wire [`DWIDTH-1:0] matrixC4_25; +wire [`DWIDTH-1:0] matrixC4_26; +wire [`DWIDTH-1:0] matrixC4_27; +wire [`DWIDTH-1:0] matrixC4_28; +wire [`DWIDTH-1:0] matrixC4_29; +wire [`DWIDTH-1:0] matrixC4_30; +wire [`DWIDTH-1:0] matrixC4_31; +wire [`DWIDTH-1:0] matrixC5_0; +wire [`DWIDTH-1:0] matrixC5_1; +wire [`DWIDTH-1:0] matrixC5_2; +wire [`DWIDTH-1:0] matrixC5_3; +wire [`DWIDTH-1:0] matrixC5_4; +wire [`DWIDTH-1:0] matrixC5_5; +wire [`DWIDTH-1:0] matrixC5_6; +wire [`DWIDTH-1:0] matrixC5_7; +wire [`DWIDTH-1:0] matrixC5_8; +wire [`DWIDTH-1:0] matrixC5_9; +wire [`DWIDTH-1:0] matrixC5_10; +wire [`DWIDTH-1:0] matrixC5_11; +wire [`DWIDTH-1:0] matrixC5_12; +wire [`DWIDTH-1:0] matrixC5_13; +wire [`DWIDTH-1:0] matrixC5_14; +wire [`DWIDTH-1:0] matrixC5_15; +wire [`DWIDTH-1:0] matrixC5_16; +wire [`DWIDTH-1:0] matrixC5_17; +wire [`DWIDTH-1:0] matrixC5_18; +wire [`DWIDTH-1:0] matrixC5_19; +wire [`DWIDTH-1:0] matrixC5_20; +wire [`DWIDTH-1:0] matrixC5_21; +wire [`DWIDTH-1:0] matrixC5_22; +wire [`DWIDTH-1:0] matrixC5_23; +wire [`DWIDTH-1:0] matrixC5_24; +wire [`DWIDTH-1:0] matrixC5_25; +wire [`DWIDTH-1:0] matrixC5_26; +wire [`DWIDTH-1:0] matrixC5_27; +wire [`DWIDTH-1:0] matrixC5_28; +wire [`DWIDTH-1:0] matrixC5_29; +wire [`DWIDTH-1:0] matrixC5_30; +wire [`DWIDTH-1:0] matrixC5_31; +wire [`DWIDTH-1:0] matrixC6_0; +wire [`DWIDTH-1:0] matrixC6_1; +wire [`DWIDTH-1:0] matrixC6_2; +wire [`DWIDTH-1:0] matrixC6_3; +wire [`DWIDTH-1:0] matrixC6_4; +wire [`DWIDTH-1:0] matrixC6_5; +wire [`DWIDTH-1:0] matrixC6_6; +wire [`DWIDTH-1:0] matrixC6_7; +wire [`DWIDTH-1:0] matrixC6_8; +wire [`DWIDTH-1:0] matrixC6_9; +wire [`DWIDTH-1:0] matrixC6_10; +wire [`DWIDTH-1:0] matrixC6_11; +wire [`DWIDTH-1:0] matrixC6_12; +wire [`DWIDTH-1:0] matrixC6_13; +wire [`DWIDTH-1:0] matrixC6_14; +wire [`DWIDTH-1:0] matrixC6_15; +wire [`DWIDTH-1:0] matrixC6_16; +wire [`DWIDTH-1:0] matrixC6_17; +wire [`DWIDTH-1:0] matrixC6_18; +wire [`DWIDTH-1:0] matrixC6_19; +wire [`DWIDTH-1:0] matrixC6_20; +wire [`DWIDTH-1:0] matrixC6_21; +wire [`DWIDTH-1:0] matrixC6_22; +wire [`DWIDTH-1:0] matrixC6_23; +wire [`DWIDTH-1:0] matrixC6_24; +wire [`DWIDTH-1:0] matrixC6_25; +wire [`DWIDTH-1:0] matrixC6_26; +wire [`DWIDTH-1:0] matrixC6_27; +wire [`DWIDTH-1:0] matrixC6_28; +wire [`DWIDTH-1:0] matrixC6_29; +wire [`DWIDTH-1:0] matrixC6_30; +wire [`DWIDTH-1:0] matrixC6_31; +wire [`DWIDTH-1:0] matrixC7_0; +wire [`DWIDTH-1:0] matrixC7_1; +wire [`DWIDTH-1:0] matrixC7_2; +wire [`DWIDTH-1:0] matrixC7_3; +wire [`DWIDTH-1:0] matrixC7_4; +wire [`DWIDTH-1:0] matrixC7_5; +wire [`DWIDTH-1:0] matrixC7_6; +wire [`DWIDTH-1:0] matrixC7_7; +wire [`DWIDTH-1:0] matrixC7_8; +wire [`DWIDTH-1:0] matrixC7_9; +wire [`DWIDTH-1:0] matrixC7_10; +wire [`DWIDTH-1:0] matrixC7_11; +wire [`DWIDTH-1:0] matrixC7_12; +wire [`DWIDTH-1:0] matrixC7_13; +wire [`DWIDTH-1:0] matrixC7_14; +wire [`DWIDTH-1:0] matrixC7_15; +wire [`DWIDTH-1:0] matrixC7_16; +wire [`DWIDTH-1:0] matrixC7_17; +wire [`DWIDTH-1:0] matrixC7_18; +wire [`DWIDTH-1:0] matrixC7_19; +wire [`DWIDTH-1:0] matrixC7_20; +wire [`DWIDTH-1:0] matrixC7_21; +wire [`DWIDTH-1:0] matrixC7_22; +wire [`DWIDTH-1:0] matrixC7_23; +wire [`DWIDTH-1:0] matrixC7_24; +wire [`DWIDTH-1:0] matrixC7_25; +wire [`DWIDTH-1:0] matrixC7_26; +wire [`DWIDTH-1:0] matrixC7_27; +wire [`DWIDTH-1:0] matrixC7_28; +wire [`DWIDTH-1:0] matrixC7_29; +wire [`DWIDTH-1:0] matrixC7_30; +wire [`DWIDTH-1:0] matrixC7_31; +wire [`DWIDTH-1:0] matrixC8_0; +wire [`DWIDTH-1:0] matrixC8_1; +wire [`DWIDTH-1:0] matrixC8_2; +wire [`DWIDTH-1:0] matrixC8_3; +wire [`DWIDTH-1:0] matrixC8_4; +wire [`DWIDTH-1:0] matrixC8_5; +wire [`DWIDTH-1:0] matrixC8_6; +wire [`DWIDTH-1:0] matrixC8_7; +wire [`DWIDTH-1:0] matrixC8_8; +wire [`DWIDTH-1:0] matrixC8_9; +wire [`DWIDTH-1:0] matrixC8_10; +wire [`DWIDTH-1:0] matrixC8_11; +wire [`DWIDTH-1:0] matrixC8_12; +wire [`DWIDTH-1:0] matrixC8_13; +wire [`DWIDTH-1:0] matrixC8_14; +wire [`DWIDTH-1:0] matrixC8_15; +wire [`DWIDTH-1:0] matrixC8_16; +wire [`DWIDTH-1:0] matrixC8_17; +wire [`DWIDTH-1:0] matrixC8_18; +wire [`DWIDTH-1:0] matrixC8_19; +wire [`DWIDTH-1:0] matrixC8_20; +wire [`DWIDTH-1:0] matrixC8_21; +wire [`DWIDTH-1:0] matrixC8_22; +wire [`DWIDTH-1:0] matrixC8_23; +wire [`DWIDTH-1:0] matrixC8_24; +wire [`DWIDTH-1:0] matrixC8_25; +wire [`DWIDTH-1:0] matrixC8_26; +wire [`DWIDTH-1:0] matrixC8_27; +wire [`DWIDTH-1:0] matrixC8_28; +wire [`DWIDTH-1:0] matrixC8_29; +wire [`DWIDTH-1:0] matrixC8_30; +wire [`DWIDTH-1:0] matrixC8_31; +wire [`DWIDTH-1:0] matrixC9_0; +wire [`DWIDTH-1:0] matrixC9_1; +wire [`DWIDTH-1:0] matrixC9_2; +wire [`DWIDTH-1:0] matrixC9_3; +wire [`DWIDTH-1:0] matrixC9_4; +wire [`DWIDTH-1:0] matrixC9_5; +wire [`DWIDTH-1:0] matrixC9_6; +wire [`DWIDTH-1:0] matrixC9_7; +wire [`DWIDTH-1:0] matrixC9_8; +wire [`DWIDTH-1:0] matrixC9_9; +wire [`DWIDTH-1:0] matrixC9_10; +wire [`DWIDTH-1:0] matrixC9_11; +wire [`DWIDTH-1:0] matrixC9_12; +wire [`DWIDTH-1:0] matrixC9_13; +wire [`DWIDTH-1:0] matrixC9_14; +wire [`DWIDTH-1:0] matrixC9_15; +wire [`DWIDTH-1:0] matrixC9_16; +wire [`DWIDTH-1:0] matrixC9_17; +wire [`DWIDTH-1:0] matrixC9_18; +wire [`DWIDTH-1:0] matrixC9_19; +wire [`DWIDTH-1:0] matrixC9_20; +wire [`DWIDTH-1:0] matrixC9_21; +wire [`DWIDTH-1:0] matrixC9_22; +wire [`DWIDTH-1:0] matrixC9_23; +wire [`DWIDTH-1:0] matrixC9_24; +wire [`DWIDTH-1:0] matrixC9_25; +wire [`DWIDTH-1:0] matrixC9_26; +wire [`DWIDTH-1:0] matrixC9_27; +wire [`DWIDTH-1:0] matrixC9_28; +wire [`DWIDTH-1:0] matrixC9_29; +wire [`DWIDTH-1:0] matrixC9_30; +wire [`DWIDTH-1:0] matrixC9_31; +wire [`DWIDTH-1:0] matrixC10_0; +wire [`DWIDTH-1:0] matrixC10_1; +wire [`DWIDTH-1:0] matrixC10_2; +wire [`DWIDTH-1:0] matrixC10_3; +wire [`DWIDTH-1:0] matrixC10_4; +wire [`DWIDTH-1:0] matrixC10_5; +wire [`DWIDTH-1:0] matrixC10_6; +wire [`DWIDTH-1:0] matrixC10_7; +wire [`DWIDTH-1:0] matrixC10_8; +wire [`DWIDTH-1:0] matrixC10_9; +wire [`DWIDTH-1:0] matrixC10_10; +wire [`DWIDTH-1:0] matrixC10_11; +wire [`DWIDTH-1:0] matrixC10_12; +wire [`DWIDTH-1:0] matrixC10_13; +wire [`DWIDTH-1:0] matrixC10_14; +wire [`DWIDTH-1:0] matrixC10_15; +wire [`DWIDTH-1:0] matrixC10_16; +wire [`DWIDTH-1:0] matrixC10_17; +wire [`DWIDTH-1:0] matrixC10_18; +wire [`DWIDTH-1:0] matrixC10_19; +wire [`DWIDTH-1:0] matrixC10_20; +wire [`DWIDTH-1:0] matrixC10_21; +wire [`DWIDTH-1:0] matrixC10_22; +wire [`DWIDTH-1:0] matrixC10_23; +wire [`DWIDTH-1:0] matrixC10_24; +wire [`DWIDTH-1:0] matrixC10_25; +wire [`DWIDTH-1:0] matrixC10_26; +wire [`DWIDTH-1:0] matrixC10_27; +wire [`DWIDTH-1:0] matrixC10_28; +wire [`DWIDTH-1:0] matrixC10_29; +wire [`DWIDTH-1:0] matrixC10_30; +wire [`DWIDTH-1:0] matrixC10_31; +wire [`DWIDTH-1:0] matrixC11_0; +wire [`DWIDTH-1:0] matrixC11_1; +wire [`DWIDTH-1:0] matrixC11_2; +wire [`DWIDTH-1:0] matrixC11_3; +wire [`DWIDTH-1:0] matrixC11_4; +wire [`DWIDTH-1:0] matrixC11_5; +wire [`DWIDTH-1:0] matrixC11_6; +wire [`DWIDTH-1:0] matrixC11_7; +wire [`DWIDTH-1:0] matrixC11_8; +wire [`DWIDTH-1:0] matrixC11_9; +wire [`DWIDTH-1:0] matrixC11_10; +wire [`DWIDTH-1:0] matrixC11_11; +wire [`DWIDTH-1:0] matrixC11_12; +wire [`DWIDTH-1:0] matrixC11_13; +wire [`DWIDTH-1:0] matrixC11_14; +wire [`DWIDTH-1:0] matrixC11_15; +wire [`DWIDTH-1:0] matrixC11_16; +wire [`DWIDTH-1:0] matrixC11_17; +wire [`DWIDTH-1:0] matrixC11_18; +wire [`DWIDTH-1:0] matrixC11_19; +wire [`DWIDTH-1:0] matrixC11_20; +wire [`DWIDTH-1:0] matrixC11_21; +wire [`DWIDTH-1:0] matrixC11_22; +wire [`DWIDTH-1:0] matrixC11_23; +wire [`DWIDTH-1:0] matrixC11_24; +wire [`DWIDTH-1:0] matrixC11_25; +wire [`DWIDTH-1:0] matrixC11_26; +wire [`DWIDTH-1:0] matrixC11_27; +wire [`DWIDTH-1:0] matrixC11_28; +wire [`DWIDTH-1:0] matrixC11_29; +wire [`DWIDTH-1:0] matrixC11_30; +wire [`DWIDTH-1:0] matrixC11_31; +wire [`DWIDTH-1:0] matrixC12_0; +wire [`DWIDTH-1:0] matrixC12_1; +wire [`DWIDTH-1:0] matrixC12_2; +wire [`DWIDTH-1:0] matrixC12_3; +wire [`DWIDTH-1:0] matrixC12_4; +wire [`DWIDTH-1:0] matrixC12_5; +wire [`DWIDTH-1:0] matrixC12_6; +wire [`DWIDTH-1:0] matrixC12_7; +wire [`DWIDTH-1:0] matrixC12_8; +wire [`DWIDTH-1:0] matrixC12_9; +wire [`DWIDTH-1:0] matrixC12_10; +wire [`DWIDTH-1:0] matrixC12_11; +wire [`DWIDTH-1:0] matrixC12_12; +wire [`DWIDTH-1:0] matrixC12_13; +wire [`DWIDTH-1:0] matrixC12_14; +wire [`DWIDTH-1:0] matrixC12_15; +wire [`DWIDTH-1:0] matrixC12_16; +wire [`DWIDTH-1:0] matrixC12_17; +wire [`DWIDTH-1:0] matrixC12_18; +wire [`DWIDTH-1:0] matrixC12_19; +wire [`DWIDTH-1:0] matrixC12_20; +wire [`DWIDTH-1:0] matrixC12_21; +wire [`DWIDTH-1:0] matrixC12_22; +wire [`DWIDTH-1:0] matrixC12_23; +wire [`DWIDTH-1:0] matrixC12_24; +wire [`DWIDTH-1:0] matrixC12_25; +wire [`DWIDTH-1:0] matrixC12_26; +wire [`DWIDTH-1:0] matrixC12_27; +wire [`DWIDTH-1:0] matrixC12_28; +wire [`DWIDTH-1:0] matrixC12_29; +wire [`DWIDTH-1:0] matrixC12_30; +wire [`DWIDTH-1:0] matrixC12_31; +wire [`DWIDTH-1:0] matrixC13_0; +wire [`DWIDTH-1:0] matrixC13_1; +wire [`DWIDTH-1:0] matrixC13_2; +wire [`DWIDTH-1:0] matrixC13_3; +wire [`DWIDTH-1:0] matrixC13_4; +wire [`DWIDTH-1:0] matrixC13_5; +wire [`DWIDTH-1:0] matrixC13_6; +wire [`DWIDTH-1:0] matrixC13_7; +wire [`DWIDTH-1:0] matrixC13_8; +wire [`DWIDTH-1:0] matrixC13_9; +wire [`DWIDTH-1:0] matrixC13_10; +wire [`DWIDTH-1:0] matrixC13_11; +wire [`DWIDTH-1:0] matrixC13_12; +wire [`DWIDTH-1:0] matrixC13_13; +wire [`DWIDTH-1:0] matrixC13_14; +wire [`DWIDTH-1:0] matrixC13_15; +wire [`DWIDTH-1:0] matrixC13_16; +wire [`DWIDTH-1:0] matrixC13_17; +wire [`DWIDTH-1:0] matrixC13_18; +wire [`DWIDTH-1:0] matrixC13_19; +wire [`DWIDTH-1:0] matrixC13_20; +wire [`DWIDTH-1:0] matrixC13_21; +wire [`DWIDTH-1:0] matrixC13_22; +wire [`DWIDTH-1:0] matrixC13_23; +wire [`DWIDTH-1:0] matrixC13_24; +wire [`DWIDTH-1:0] matrixC13_25; +wire [`DWIDTH-1:0] matrixC13_26; +wire [`DWIDTH-1:0] matrixC13_27; +wire [`DWIDTH-1:0] matrixC13_28; +wire [`DWIDTH-1:0] matrixC13_29; +wire [`DWIDTH-1:0] matrixC13_30; +wire [`DWIDTH-1:0] matrixC13_31; +wire [`DWIDTH-1:0] matrixC14_0; +wire [`DWIDTH-1:0] matrixC14_1; +wire [`DWIDTH-1:0] matrixC14_2; +wire [`DWIDTH-1:0] matrixC14_3; +wire [`DWIDTH-1:0] matrixC14_4; +wire [`DWIDTH-1:0] matrixC14_5; +wire [`DWIDTH-1:0] matrixC14_6; +wire [`DWIDTH-1:0] matrixC14_7; +wire [`DWIDTH-1:0] matrixC14_8; +wire [`DWIDTH-1:0] matrixC14_9; +wire [`DWIDTH-1:0] matrixC14_10; +wire [`DWIDTH-1:0] matrixC14_11; +wire [`DWIDTH-1:0] matrixC14_12; +wire [`DWIDTH-1:0] matrixC14_13; +wire [`DWIDTH-1:0] matrixC14_14; +wire [`DWIDTH-1:0] matrixC14_15; +wire [`DWIDTH-1:0] matrixC14_16; +wire [`DWIDTH-1:0] matrixC14_17; +wire [`DWIDTH-1:0] matrixC14_18; +wire [`DWIDTH-1:0] matrixC14_19; +wire [`DWIDTH-1:0] matrixC14_20; +wire [`DWIDTH-1:0] matrixC14_21; +wire [`DWIDTH-1:0] matrixC14_22; +wire [`DWIDTH-1:0] matrixC14_23; +wire [`DWIDTH-1:0] matrixC14_24; +wire [`DWIDTH-1:0] matrixC14_25; +wire [`DWIDTH-1:0] matrixC14_26; +wire [`DWIDTH-1:0] matrixC14_27; +wire [`DWIDTH-1:0] matrixC14_28; +wire [`DWIDTH-1:0] matrixC14_29; +wire [`DWIDTH-1:0] matrixC14_30; +wire [`DWIDTH-1:0] matrixC14_31; +wire [`DWIDTH-1:0] matrixC15_0; +wire [`DWIDTH-1:0] matrixC15_1; +wire [`DWIDTH-1:0] matrixC15_2; +wire [`DWIDTH-1:0] matrixC15_3; +wire [`DWIDTH-1:0] matrixC15_4; +wire [`DWIDTH-1:0] matrixC15_5; +wire [`DWIDTH-1:0] matrixC15_6; +wire [`DWIDTH-1:0] matrixC15_7; +wire [`DWIDTH-1:0] matrixC15_8; +wire [`DWIDTH-1:0] matrixC15_9; +wire [`DWIDTH-1:0] matrixC15_10; +wire [`DWIDTH-1:0] matrixC15_11; +wire [`DWIDTH-1:0] matrixC15_12; +wire [`DWIDTH-1:0] matrixC15_13; +wire [`DWIDTH-1:0] matrixC15_14; +wire [`DWIDTH-1:0] matrixC15_15; +wire [`DWIDTH-1:0] matrixC15_16; +wire [`DWIDTH-1:0] matrixC15_17; +wire [`DWIDTH-1:0] matrixC15_18; +wire [`DWIDTH-1:0] matrixC15_19; +wire [`DWIDTH-1:0] matrixC15_20; +wire [`DWIDTH-1:0] matrixC15_21; +wire [`DWIDTH-1:0] matrixC15_22; +wire [`DWIDTH-1:0] matrixC15_23; +wire [`DWIDTH-1:0] matrixC15_24; +wire [`DWIDTH-1:0] matrixC15_25; +wire [`DWIDTH-1:0] matrixC15_26; +wire [`DWIDTH-1:0] matrixC15_27; +wire [`DWIDTH-1:0] matrixC15_28; +wire [`DWIDTH-1:0] matrixC15_29; +wire [`DWIDTH-1:0] matrixC15_30; +wire [`DWIDTH-1:0] matrixC15_31; +wire [`DWIDTH-1:0] matrixC16_0; +wire [`DWIDTH-1:0] matrixC16_1; +wire [`DWIDTH-1:0] matrixC16_2; +wire [`DWIDTH-1:0] matrixC16_3; +wire [`DWIDTH-1:0] matrixC16_4; +wire [`DWIDTH-1:0] matrixC16_5; +wire [`DWIDTH-1:0] matrixC16_6; +wire [`DWIDTH-1:0] matrixC16_7; +wire [`DWIDTH-1:0] matrixC16_8; +wire [`DWIDTH-1:0] matrixC16_9; +wire [`DWIDTH-1:0] matrixC16_10; +wire [`DWIDTH-1:0] matrixC16_11; +wire [`DWIDTH-1:0] matrixC16_12; +wire [`DWIDTH-1:0] matrixC16_13; +wire [`DWIDTH-1:0] matrixC16_14; +wire [`DWIDTH-1:0] matrixC16_15; +wire [`DWIDTH-1:0] matrixC16_16; +wire [`DWIDTH-1:0] matrixC16_17; +wire [`DWIDTH-1:0] matrixC16_18; +wire [`DWIDTH-1:0] matrixC16_19; +wire [`DWIDTH-1:0] matrixC16_20; +wire [`DWIDTH-1:0] matrixC16_21; +wire [`DWIDTH-1:0] matrixC16_22; +wire [`DWIDTH-1:0] matrixC16_23; +wire [`DWIDTH-1:0] matrixC16_24; +wire [`DWIDTH-1:0] matrixC16_25; +wire [`DWIDTH-1:0] matrixC16_26; +wire [`DWIDTH-1:0] matrixC16_27; +wire [`DWIDTH-1:0] matrixC16_28; +wire [`DWIDTH-1:0] matrixC16_29; +wire [`DWIDTH-1:0] matrixC16_30; +wire [`DWIDTH-1:0] matrixC16_31; +wire [`DWIDTH-1:0] matrixC17_0; +wire [`DWIDTH-1:0] matrixC17_1; +wire [`DWIDTH-1:0] matrixC17_2; +wire [`DWIDTH-1:0] matrixC17_3; +wire [`DWIDTH-1:0] matrixC17_4; +wire [`DWIDTH-1:0] matrixC17_5; +wire [`DWIDTH-1:0] matrixC17_6; +wire [`DWIDTH-1:0] matrixC17_7; +wire [`DWIDTH-1:0] matrixC17_8; +wire [`DWIDTH-1:0] matrixC17_9; +wire [`DWIDTH-1:0] matrixC17_10; +wire [`DWIDTH-1:0] matrixC17_11; +wire [`DWIDTH-1:0] matrixC17_12; +wire [`DWIDTH-1:0] matrixC17_13; +wire [`DWIDTH-1:0] matrixC17_14; +wire [`DWIDTH-1:0] matrixC17_15; +wire [`DWIDTH-1:0] matrixC17_16; +wire [`DWIDTH-1:0] matrixC17_17; +wire [`DWIDTH-1:0] matrixC17_18; +wire [`DWIDTH-1:0] matrixC17_19; +wire [`DWIDTH-1:0] matrixC17_20; +wire [`DWIDTH-1:0] matrixC17_21; +wire [`DWIDTH-1:0] matrixC17_22; +wire [`DWIDTH-1:0] matrixC17_23; +wire [`DWIDTH-1:0] matrixC17_24; +wire [`DWIDTH-1:0] matrixC17_25; +wire [`DWIDTH-1:0] matrixC17_26; +wire [`DWIDTH-1:0] matrixC17_27; +wire [`DWIDTH-1:0] matrixC17_28; +wire [`DWIDTH-1:0] matrixC17_29; +wire [`DWIDTH-1:0] matrixC17_30; +wire [`DWIDTH-1:0] matrixC17_31; +wire [`DWIDTH-1:0] matrixC18_0; +wire [`DWIDTH-1:0] matrixC18_1; +wire [`DWIDTH-1:0] matrixC18_2; +wire [`DWIDTH-1:0] matrixC18_3; +wire [`DWIDTH-1:0] matrixC18_4; +wire [`DWIDTH-1:0] matrixC18_5; +wire [`DWIDTH-1:0] matrixC18_6; +wire [`DWIDTH-1:0] matrixC18_7; +wire [`DWIDTH-1:0] matrixC18_8; +wire [`DWIDTH-1:0] matrixC18_9; +wire [`DWIDTH-1:0] matrixC18_10; +wire [`DWIDTH-1:0] matrixC18_11; +wire [`DWIDTH-1:0] matrixC18_12; +wire [`DWIDTH-1:0] matrixC18_13; +wire [`DWIDTH-1:0] matrixC18_14; +wire [`DWIDTH-1:0] matrixC18_15; +wire [`DWIDTH-1:0] matrixC18_16; +wire [`DWIDTH-1:0] matrixC18_17; +wire [`DWIDTH-1:0] matrixC18_18; +wire [`DWIDTH-1:0] matrixC18_19; +wire [`DWIDTH-1:0] matrixC18_20; +wire [`DWIDTH-1:0] matrixC18_21; +wire [`DWIDTH-1:0] matrixC18_22; +wire [`DWIDTH-1:0] matrixC18_23; +wire [`DWIDTH-1:0] matrixC18_24; +wire [`DWIDTH-1:0] matrixC18_25; +wire [`DWIDTH-1:0] matrixC18_26; +wire [`DWIDTH-1:0] matrixC18_27; +wire [`DWIDTH-1:0] matrixC18_28; +wire [`DWIDTH-1:0] matrixC18_29; +wire [`DWIDTH-1:0] matrixC18_30; +wire [`DWIDTH-1:0] matrixC18_31; +wire [`DWIDTH-1:0] matrixC19_0; +wire [`DWIDTH-1:0] matrixC19_1; +wire [`DWIDTH-1:0] matrixC19_2; +wire [`DWIDTH-1:0] matrixC19_3; +wire [`DWIDTH-1:0] matrixC19_4; +wire [`DWIDTH-1:0] matrixC19_5; +wire [`DWIDTH-1:0] matrixC19_6; +wire [`DWIDTH-1:0] matrixC19_7; +wire [`DWIDTH-1:0] matrixC19_8; +wire [`DWIDTH-1:0] matrixC19_9; +wire [`DWIDTH-1:0] matrixC19_10; +wire [`DWIDTH-1:0] matrixC19_11; +wire [`DWIDTH-1:0] matrixC19_12; +wire [`DWIDTH-1:0] matrixC19_13; +wire [`DWIDTH-1:0] matrixC19_14; +wire [`DWIDTH-1:0] matrixC19_15; +wire [`DWIDTH-1:0] matrixC19_16; +wire [`DWIDTH-1:0] matrixC19_17; +wire [`DWIDTH-1:0] matrixC19_18; +wire [`DWIDTH-1:0] matrixC19_19; +wire [`DWIDTH-1:0] matrixC19_20; +wire [`DWIDTH-1:0] matrixC19_21; +wire [`DWIDTH-1:0] matrixC19_22; +wire [`DWIDTH-1:0] matrixC19_23; +wire [`DWIDTH-1:0] matrixC19_24; +wire [`DWIDTH-1:0] matrixC19_25; +wire [`DWIDTH-1:0] matrixC19_26; +wire [`DWIDTH-1:0] matrixC19_27; +wire [`DWIDTH-1:0] matrixC19_28; +wire [`DWIDTH-1:0] matrixC19_29; +wire [`DWIDTH-1:0] matrixC19_30; +wire [`DWIDTH-1:0] matrixC19_31; +wire [`DWIDTH-1:0] matrixC20_0; +wire [`DWIDTH-1:0] matrixC20_1; +wire [`DWIDTH-1:0] matrixC20_2; +wire [`DWIDTH-1:0] matrixC20_3; +wire [`DWIDTH-1:0] matrixC20_4; +wire [`DWIDTH-1:0] matrixC20_5; +wire [`DWIDTH-1:0] matrixC20_6; +wire [`DWIDTH-1:0] matrixC20_7; +wire [`DWIDTH-1:0] matrixC20_8; +wire [`DWIDTH-1:0] matrixC20_9; +wire [`DWIDTH-1:0] matrixC20_10; +wire [`DWIDTH-1:0] matrixC20_11; +wire [`DWIDTH-1:0] matrixC20_12; +wire [`DWIDTH-1:0] matrixC20_13; +wire [`DWIDTH-1:0] matrixC20_14; +wire [`DWIDTH-1:0] matrixC20_15; +wire [`DWIDTH-1:0] matrixC20_16; +wire [`DWIDTH-1:0] matrixC20_17; +wire [`DWIDTH-1:0] matrixC20_18; +wire [`DWIDTH-1:0] matrixC20_19; +wire [`DWIDTH-1:0] matrixC20_20; +wire [`DWIDTH-1:0] matrixC20_21; +wire [`DWIDTH-1:0] matrixC20_22; +wire [`DWIDTH-1:0] matrixC20_23; +wire [`DWIDTH-1:0] matrixC20_24; +wire [`DWIDTH-1:0] matrixC20_25; +wire [`DWIDTH-1:0] matrixC20_26; +wire [`DWIDTH-1:0] matrixC20_27; +wire [`DWIDTH-1:0] matrixC20_28; +wire [`DWIDTH-1:0] matrixC20_29; +wire [`DWIDTH-1:0] matrixC20_30; +wire [`DWIDTH-1:0] matrixC20_31; +wire [`DWIDTH-1:0] matrixC21_0; +wire [`DWIDTH-1:0] matrixC21_1; +wire [`DWIDTH-1:0] matrixC21_2; +wire [`DWIDTH-1:0] matrixC21_3; +wire [`DWIDTH-1:0] matrixC21_4; +wire [`DWIDTH-1:0] matrixC21_5; +wire [`DWIDTH-1:0] matrixC21_6; +wire [`DWIDTH-1:0] matrixC21_7; +wire [`DWIDTH-1:0] matrixC21_8; +wire [`DWIDTH-1:0] matrixC21_9; +wire [`DWIDTH-1:0] matrixC21_10; +wire [`DWIDTH-1:0] matrixC21_11; +wire [`DWIDTH-1:0] matrixC21_12; +wire [`DWIDTH-1:0] matrixC21_13; +wire [`DWIDTH-1:0] matrixC21_14; +wire [`DWIDTH-1:0] matrixC21_15; +wire [`DWIDTH-1:0] matrixC21_16; +wire [`DWIDTH-1:0] matrixC21_17; +wire [`DWIDTH-1:0] matrixC21_18; +wire [`DWIDTH-1:0] matrixC21_19; +wire [`DWIDTH-1:0] matrixC21_20; +wire [`DWIDTH-1:0] matrixC21_21; +wire [`DWIDTH-1:0] matrixC21_22; +wire [`DWIDTH-1:0] matrixC21_23; +wire [`DWIDTH-1:0] matrixC21_24; +wire [`DWIDTH-1:0] matrixC21_25; +wire [`DWIDTH-1:0] matrixC21_26; +wire [`DWIDTH-1:0] matrixC21_27; +wire [`DWIDTH-1:0] matrixC21_28; +wire [`DWIDTH-1:0] matrixC21_29; +wire [`DWIDTH-1:0] matrixC21_30; +wire [`DWIDTH-1:0] matrixC21_31; +wire [`DWIDTH-1:0] matrixC22_0; +wire [`DWIDTH-1:0] matrixC22_1; +wire [`DWIDTH-1:0] matrixC22_2; +wire [`DWIDTH-1:0] matrixC22_3; +wire [`DWIDTH-1:0] matrixC22_4; +wire [`DWIDTH-1:0] matrixC22_5; +wire [`DWIDTH-1:0] matrixC22_6; +wire [`DWIDTH-1:0] matrixC22_7; +wire [`DWIDTH-1:0] matrixC22_8; +wire [`DWIDTH-1:0] matrixC22_9; +wire [`DWIDTH-1:0] matrixC22_10; +wire [`DWIDTH-1:0] matrixC22_11; +wire [`DWIDTH-1:0] matrixC22_12; +wire [`DWIDTH-1:0] matrixC22_13; +wire [`DWIDTH-1:0] matrixC22_14; +wire [`DWIDTH-1:0] matrixC22_15; +wire [`DWIDTH-1:0] matrixC22_16; +wire [`DWIDTH-1:0] matrixC22_17; +wire [`DWIDTH-1:0] matrixC22_18; +wire [`DWIDTH-1:0] matrixC22_19; +wire [`DWIDTH-1:0] matrixC22_20; +wire [`DWIDTH-1:0] matrixC22_21; +wire [`DWIDTH-1:0] matrixC22_22; +wire [`DWIDTH-1:0] matrixC22_23; +wire [`DWIDTH-1:0] matrixC22_24; +wire [`DWIDTH-1:0] matrixC22_25; +wire [`DWIDTH-1:0] matrixC22_26; +wire [`DWIDTH-1:0] matrixC22_27; +wire [`DWIDTH-1:0] matrixC22_28; +wire [`DWIDTH-1:0] matrixC22_29; +wire [`DWIDTH-1:0] matrixC22_30; +wire [`DWIDTH-1:0] matrixC22_31; +wire [`DWIDTH-1:0] matrixC23_0; +wire [`DWIDTH-1:0] matrixC23_1; +wire [`DWIDTH-1:0] matrixC23_2; +wire [`DWIDTH-1:0] matrixC23_3; +wire [`DWIDTH-1:0] matrixC23_4; +wire [`DWIDTH-1:0] matrixC23_5; +wire [`DWIDTH-1:0] matrixC23_6; +wire [`DWIDTH-1:0] matrixC23_7; +wire [`DWIDTH-1:0] matrixC23_8; +wire [`DWIDTH-1:0] matrixC23_9; +wire [`DWIDTH-1:0] matrixC23_10; +wire [`DWIDTH-1:0] matrixC23_11; +wire [`DWIDTH-1:0] matrixC23_12; +wire [`DWIDTH-1:0] matrixC23_13; +wire [`DWIDTH-1:0] matrixC23_14; +wire [`DWIDTH-1:0] matrixC23_15; +wire [`DWIDTH-1:0] matrixC23_16; +wire [`DWIDTH-1:0] matrixC23_17; +wire [`DWIDTH-1:0] matrixC23_18; +wire [`DWIDTH-1:0] matrixC23_19; +wire [`DWIDTH-1:0] matrixC23_20; +wire [`DWIDTH-1:0] matrixC23_21; +wire [`DWIDTH-1:0] matrixC23_22; +wire [`DWIDTH-1:0] matrixC23_23; +wire [`DWIDTH-1:0] matrixC23_24; +wire [`DWIDTH-1:0] matrixC23_25; +wire [`DWIDTH-1:0] matrixC23_26; +wire [`DWIDTH-1:0] matrixC23_27; +wire [`DWIDTH-1:0] matrixC23_28; +wire [`DWIDTH-1:0] matrixC23_29; +wire [`DWIDTH-1:0] matrixC23_30; +wire [`DWIDTH-1:0] matrixC23_31; +wire [`DWIDTH-1:0] matrixC24_0; +wire [`DWIDTH-1:0] matrixC24_1; +wire [`DWIDTH-1:0] matrixC24_2; +wire [`DWIDTH-1:0] matrixC24_3; +wire [`DWIDTH-1:0] matrixC24_4; +wire [`DWIDTH-1:0] matrixC24_5; +wire [`DWIDTH-1:0] matrixC24_6; +wire [`DWIDTH-1:0] matrixC24_7; +wire [`DWIDTH-1:0] matrixC24_8; +wire [`DWIDTH-1:0] matrixC24_9; +wire [`DWIDTH-1:0] matrixC24_10; +wire [`DWIDTH-1:0] matrixC24_11; +wire [`DWIDTH-1:0] matrixC24_12; +wire [`DWIDTH-1:0] matrixC24_13; +wire [`DWIDTH-1:0] matrixC24_14; +wire [`DWIDTH-1:0] matrixC24_15; +wire [`DWIDTH-1:0] matrixC24_16; +wire [`DWIDTH-1:0] matrixC24_17; +wire [`DWIDTH-1:0] matrixC24_18; +wire [`DWIDTH-1:0] matrixC24_19; +wire [`DWIDTH-1:0] matrixC24_20; +wire [`DWIDTH-1:0] matrixC24_21; +wire [`DWIDTH-1:0] matrixC24_22; +wire [`DWIDTH-1:0] matrixC24_23; +wire [`DWIDTH-1:0] matrixC24_24; +wire [`DWIDTH-1:0] matrixC24_25; +wire [`DWIDTH-1:0] matrixC24_26; +wire [`DWIDTH-1:0] matrixC24_27; +wire [`DWIDTH-1:0] matrixC24_28; +wire [`DWIDTH-1:0] matrixC24_29; +wire [`DWIDTH-1:0] matrixC24_30; +wire [`DWIDTH-1:0] matrixC24_31; +wire [`DWIDTH-1:0] matrixC25_0; +wire [`DWIDTH-1:0] matrixC25_1; +wire [`DWIDTH-1:0] matrixC25_2; +wire [`DWIDTH-1:0] matrixC25_3; +wire [`DWIDTH-1:0] matrixC25_4; +wire [`DWIDTH-1:0] matrixC25_5; +wire [`DWIDTH-1:0] matrixC25_6; +wire [`DWIDTH-1:0] matrixC25_7; +wire [`DWIDTH-1:0] matrixC25_8; +wire [`DWIDTH-1:0] matrixC25_9; +wire [`DWIDTH-1:0] matrixC25_10; +wire [`DWIDTH-1:0] matrixC25_11; +wire [`DWIDTH-1:0] matrixC25_12; +wire [`DWIDTH-1:0] matrixC25_13; +wire [`DWIDTH-1:0] matrixC25_14; +wire [`DWIDTH-1:0] matrixC25_15; +wire [`DWIDTH-1:0] matrixC25_16; +wire [`DWIDTH-1:0] matrixC25_17; +wire [`DWIDTH-1:0] matrixC25_18; +wire [`DWIDTH-1:0] matrixC25_19; +wire [`DWIDTH-1:0] matrixC25_20; +wire [`DWIDTH-1:0] matrixC25_21; +wire [`DWIDTH-1:0] matrixC25_22; +wire [`DWIDTH-1:0] matrixC25_23; +wire [`DWIDTH-1:0] matrixC25_24; +wire [`DWIDTH-1:0] matrixC25_25; +wire [`DWIDTH-1:0] matrixC25_26; +wire [`DWIDTH-1:0] matrixC25_27; +wire [`DWIDTH-1:0] matrixC25_28; +wire [`DWIDTH-1:0] matrixC25_29; +wire [`DWIDTH-1:0] matrixC25_30; +wire [`DWIDTH-1:0] matrixC25_31; +wire [`DWIDTH-1:0] matrixC26_0; +wire [`DWIDTH-1:0] matrixC26_1; +wire [`DWIDTH-1:0] matrixC26_2; +wire [`DWIDTH-1:0] matrixC26_3; +wire [`DWIDTH-1:0] matrixC26_4; +wire [`DWIDTH-1:0] matrixC26_5; +wire [`DWIDTH-1:0] matrixC26_6; +wire [`DWIDTH-1:0] matrixC26_7; +wire [`DWIDTH-1:0] matrixC26_8; +wire [`DWIDTH-1:0] matrixC26_9; +wire [`DWIDTH-1:0] matrixC26_10; +wire [`DWIDTH-1:0] matrixC26_11; +wire [`DWIDTH-1:0] matrixC26_12; +wire [`DWIDTH-1:0] matrixC26_13; +wire [`DWIDTH-1:0] matrixC26_14; +wire [`DWIDTH-1:0] matrixC26_15; +wire [`DWIDTH-1:0] matrixC26_16; +wire [`DWIDTH-1:0] matrixC26_17; +wire [`DWIDTH-1:0] matrixC26_18; +wire [`DWIDTH-1:0] matrixC26_19; +wire [`DWIDTH-1:0] matrixC26_20; +wire [`DWIDTH-1:0] matrixC26_21; +wire [`DWIDTH-1:0] matrixC26_22; +wire [`DWIDTH-1:0] matrixC26_23; +wire [`DWIDTH-1:0] matrixC26_24; +wire [`DWIDTH-1:0] matrixC26_25; +wire [`DWIDTH-1:0] matrixC26_26; +wire [`DWIDTH-1:0] matrixC26_27; +wire [`DWIDTH-1:0] matrixC26_28; +wire [`DWIDTH-1:0] matrixC26_29; +wire [`DWIDTH-1:0] matrixC26_30; +wire [`DWIDTH-1:0] matrixC26_31; +wire [`DWIDTH-1:0] matrixC27_0; +wire [`DWIDTH-1:0] matrixC27_1; +wire [`DWIDTH-1:0] matrixC27_2; +wire [`DWIDTH-1:0] matrixC27_3; +wire [`DWIDTH-1:0] matrixC27_4; +wire [`DWIDTH-1:0] matrixC27_5; +wire [`DWIDTH-1:0] matrixC27_6; +wire [`DWIDTH-1:0] matrixC27_7; +wire [`DWIDTH-1:0] matrixC27_8; +wire [`DWIDTH-1:0] matrixC27_9; +wire [`DWIDTH-1:0] matrixC27_10; +wire [`DWIDTH-1:0] matrixC27_11; +wire [`DWIDTH-1:0] matrixC27_12; +wire [`DWIDTH-1:0] matrixC27_13; +wire [`DWIDTH-1:0] matrixC27_14; +wire [`DWIDTH-1:0] matrixC27_15; +wire [`DWIDTH-1:0] matrixC27_16; +wire [`DWIDTH-1:0] matrixC27_17; +wire [`DWIDTH-1:0] matrixC27_18; +wire [`DWIDTH-1:0] matrixC27_19; +wire [`DWIDTH-1:0] matrixC27_20; +wire [`DWIDTH-1:0] matrixC27_21; +wire [`DWIDTH-1:0] matrixC27_22; +wire [`DWIDTH-1:0] matrixC27_23; +wire [`DWIDTH-1:0] matrixC27_24; +wire [`DWIDTH-1:0] matrixC27_25; +wire [`DWIDTH-1:0] matrixC27_26; +wire [`DWIDTH-1:0] matrixC27_27; +wire [`DWIDTH-1:0] matrixC27_28; +wire [`DWIDTH-1:0] matrixC27_29; +wire [`DWIDTH-1:0] matrixC27_30; +wire [`DWIDTH-1:0] matrixC27_31; +wire [`DWIDTH-1:0] matrixC28_0; +wire [`DWIDTH-1:0] matrixC28_1; +wire [`DWIDTH-1:0] matrixC28_2; +wire [`DWIDTH-1:0] matrixC28_3; +wire [`DWIDTH-1:0] matrixC28_4; +wire [`DWIDTH-1:0] matrixC28_5; +wire [`DWIDTH-1:0] matrixC28_6; +wire [`DWIDTH-1:0] matrixC28_7; +wire [`DWIDTH-1:0] matrixC28_8; +wire [`DWIDTH-1:0] matrixC28_9; +wire [`DWIDTH-1:0] matrixC28_10; +wire [`DWIDTH-1:0] matrixC28_11; +wire [`DWIDTH-1:0] matrixC28_12; +wire [`DWIDTH-1:0] matrixC28_13; +wire [`DWIDTH-1:0] matrixC28_14; +wire [`DWIDTH-1:0] matrixC28_15; +wire [`DWIDTH-1:0] matrixC28_16; +wire [`DWIDTH-1:0] matrixC28_17; +wire [`DWIDTH-1:0] matrixC28_18; +wire [`DWIDTH-1:0] matrixC28_19; +wire [`DWIDTH-1:0] matrixC28_20; +wire [`DWIDTH-1:0] matrixC28_21; +wire [`DWIDTH-1:0] matrixC28_22; +wire [`DWIDTH-1:0] matrixC28_23; +wire [`DWIDTH-1:0] matrixC28_24; +wire [`DWIDTH-1:0] matrixC28_25; +wire [`DWIDTH-1:0] matrixC28_26; +wire [`DWIDTH-1:0] matrixC28_27; +wire [`DWIDTH-1:0] matrixC28_28; +wire [`DWIDTH-1:0] matrixC28_29; +wire [`DWIDTH-1:0] matrixC28_30; +wire [`DWIDTH-1:0] matrixC28_31; +wire [`DWIDTH-1:0] matrixC29_0; +wire [`DWIDTH-1:0] matrixC29_1; +wire [`DWIDTH-1:0] matrixC29_2; +wire [`DWIDTH-1:0] matrixC29_3; +wire [`DWIDTH-1:0] matrixC29_4; +wire [`DWIDTH-1:0] matrixC29_5; +wire [`DWIDTH-1:0] matrixC29_6; +wire [`DWIDTH-1:0] matrixC29_7; +wire [`DWIDTH-1:0] matrixC29_8; +wire [`DWIDTH-1:0] matrixC29_9; +wire [`DWIDTH-1:0] matrixC29_10; +wire [`DWIDTH-1:0] matrixC29_11; +wire [`DWIDTH-1:0] matrixC29_12; +wire [`DWIDTH-1:0] matrixC29_13; +wire [`DWIDTH-1:0] matrixC29_14; +wire [`DWIDTH-1:0] matrixC29_15; +wire [`DWIDTH-1:0] matrixC29_16; +wire [`DWIDTH-1:0] matrixC29_17; +wire [`DWIDTH-1:0] matrixC29_18; +wire [`DWIDTH-1:0] matrixC29_19; +wire [`DWIDTH-1:0] matrixC29_20; +wire [`DWIDTH-1:0] matrixC29_21; +wire [`DWIDTH-1:0] matrixC29_22; +wire [`DWIDTH-1:0] matrixC29_23; +wire [`DWIDTH-1:0] matrixC29_24; +wire [`DWIDTH-1:0] matrixC29_25; +wire [`DWIDTH-1:0] matrixC29_26; +wire [`DWIDTH-1:0] matrixC29_27; +wire [`DWIDTH-1:0] matrixC29_28; +wire [`DWIDTH-1:0] matrixC29_29; +wire [`DWIDTH-1:0] matrixC29_30; +wire [`DWIDTH-1:0] matrixC29_31; +wire [`DWIDTH-1:0] matrixC30_0; +wire [`DWIDTH-1:0] matrixC30_1; +wire [`DWIDTH-1:0] matrixC30_2; +wire [`DWIDTH-1:0] matrixC30_3; +wire [`DWIDTH-1:0] matrixC30_4; +wire [`DWIDTH-1:0] matrixC30_5; +wire [`DWIDTH-1:0] matrixC30_6; +wire [`DWIDTH-1:0] matrixC30_7; +wire [`DWIDTH-1:0] matrixC30_8; +wire [`DWIDTH-1:0] matrixC30_9; +wire [`DWIDTH-1:0] matrixC30_10; +wire [`DWIDTH-1:0] matrixC30_11; +wire [`DWIDTH-1:0] matrixC30_12; +wire [`DWIDTH-1:0] matrixC30_13; +wire [`DWIDTH-1:0] matrixC30_14; +wire [`DWIDTH-1:0] matrixC30_15; +wire [`DWIDTH-1:0] matrixC30_16; +wire [`DWIDTH-1:0] matrixC30_17; +wire [`DWIDTH-1:0] matrixC30_18; +wire [`DWIDTH-1:0] matrixC30_19; +wire [`DWIDTH-1:0] matrixC30_20; +wire [`DWIDTH-1:0] matrixC30_21; +wire [`DWIDTH-1:0] matrixC30_22; +wire [`DWIDTH-1:0] matrixC30_23; +wire [`DWIDTH-1:0] matrixC30_24; +wire [`DWIDTH-1:0] matrixC30_25; +wire [`DWIDTH-1:0] matrixC30_26; +wire [`DWIDTH-1:0] matrixC30_27; +wire [`DWIDTH-1:0] matrixC30_28; +wire [`DWIDTH-1:0] matrixC30_29; +wire [`DWIDTH-1:0] matrixC30_30; +wire [`DWIDTH-1:0] matrixC30_31; +wire [`DWIDTH-1:0] matrixC31_0; +wire [`DWIDTH-1:0] matrixC31_1; +wire [`DWIDTH-1:0] matrixC31_2; +wire [`DWIDTH-1:0] matrixC31_3; +wire [`DWIDTH-1:0] matrixC31_4; +wire [`DWIDTH-1:0] matrixC31_5; +wire [`DWIDTH-1:0] matrixC31_6; +wire [`DWIDTH-1:0] matrixC31_7; +wire [`DWIDTH-1:0] matrixC31_8; +wire [`DWIDTH-1:0] matrixC31_9; +wire [`DWIDTH-1:0] matrixC31_10; +wire [`DWIDTH-1:0] matrixC31_11; +wire [`DWIDTH-1:0] matrixC31_12; +wire [`DWIDTH-1:0] matrixC31_13; +wire [`DWIDTH-1:0] matrixC31_14; +wire [`DWIDTH-1:0] matrixC31_15; +wire [`DWIDTH-1:0] matrixC31_16; +wire [`DWIDTH-1:0] matrixC31_17; +wire [`DWIDTH-1:0] matrixC31_18; +wire [`DWIDTH-1:0] matrixC31_19; +wire [`DWIDTH-1:0] matrixC31_20; +wire [`DWIDTH-1:0] matrixC31_21; +wire [`DWIDTH-1:0] matrixC31_22; +wire [`DWIDTH-1:0] matrixC31_23; +wire [`DWIDTH-1:0] matrixC31_24; +wire [`DWIDTH-1:0] matrixC31_25; +wire [`DWIDTH-1:0] matrixC31_26; +wire [`DWIDTH-1:0] matrixC31_27; +wire [`DWIDTH-1:0] matrixC31_28; +wire [`DWIDTH-1:0] matrixC31_29; +wire [`DWIDTH-1:0] matrixC31_30; +wire [`DWIDTH-1:0] matrixC31_31; + +wire row_latch_en; +////////////////////////////////////////////////////////////////////////// +// Instantiation of the output logic +////////////////////////////////////////////////////////////////////////// +output_logic u_output_logic( +.start_mat_mul(start_mat_mul), +.done_mat_mul(done_mat_mul), +.address_mat_c(address_mat_c), +.address_stride_c(address_stride_c), +.c_data_out(c_data_out), +.c_data_in(c_data_in), +.c_addr(c_addr), +.c_data_available(c_data_available), +.clk_cnt(clk_cnt), +.row_latch_en(row_latch_en), +.final_mat_mul_size(final_mat_mul_size), +.matrixC0_0(matrixC0_0), +.matrixC0_1(matrixC0_1), +.matrixC0_2(matrixC0_2), +.matrixC0_3(matrixC0_3), +.matrixC0_4(matrixC0_4), +.matrixC0_5(matrixC0_5), +.matrixC0_6(matrixC0_6), +.matrixC0_7(matrixC0_7), +.matrixC0_8(matrixC0_8), +.matrixC0_9(matrixC0_9), +.matrixC0_10(matrixC0_10), +.matrixC0_11(matrixC0_11), +.matrixC0_12(matrixC0_12), +.matrixC0_13(matrixC0_13), +.matrixC0_14(matrixC0_14), +.matrixC0_15(matrixC0_15), +.matrixC0_16(matrixC0_16), +.matrixC0_17(matrixC0_17), +.matrixC0_18(matrixC0_18), +.matrixC0_19(matrixC0_19), +.matrixC0_20(matrixC0_20), +.matrixC0_21(matrixC0_21), +.matrixC0_22(matrixC0_22), +.matrixC0_23(matrixC0_23), +.matrixC0_24(matrixC0_24), +.matrixC0_25(matrixC0_25), +.matrixC0_26(matrixC0_26), +.matrixC0_27(matrixC0_27), +.matrixC0_28(matrixC0_28), +.matrixC0_29(matrixC0_29), +.matrixC0_30(matrixC0_30), +.matrixC0_31(matrixC0_31), +.matrixC1_0(matrixC1_0), +.matrixC1_1(matrixC1_1), +.matrixC1_2(matrixC1_2), +.matrixC1_3(matrixC1_3), +.matrixC1_4(matrixC1_4), +.matrixC1_5(matrixC1_5), +.matrixC1_6(matrixC1_6), +.matrixC1_7(matrixC1_7), +.matrixC1_8(matrixC1_8), +.matrixC1_9(matrixC1_9), +.matrixC1_10(matrixC1_10), +.matrixC1_11(matrixC1_11), +.matrixC1_12(matrixC1_12), +.matrixC1_13(matrixC1_13), +.matrixC1_14(matrixC1_14), +.matrixC1_15(matrixC1_15), +.matrixC1_16(matrixC1_16), +.matrixC1_17(matrixC1_17), +.matrixC1_18(matrixC1_18), +.matrixC1_19(matrixC1_19), +.matrixC1_20(matrixC1_20), +.matrixC1_21(matrixC1_21), +.matrixC1_22(matrixC1_22), +.matrixC1_23(matrixC1_23), +.matrixC1_24(matrixC1_24), +.matrixC1_25(matrixC1_25), +.matrixC1_26(matrixC1_26), +.matrixC1_27(matrixC1_27), +.matrixC1_28(matrixC1_28), +.matrixC1_29(matrixC1_29), +.matrixC1_30(matrixC1_30), +.matrixC1_31(matrixC1_31), +.matrixC2_0(matrixC2_0), +.matrixC2_1(matrixC2_1), +.matrixC2_2(matrixC2_2), +.matrixC2_3(matrixC2_3), +.matrixC2_4(matrixC2_4), +.matrixC2_5(matrixC2_5), +.matrixC2_6(matrixC2_6), +.matrixC2_7(matrixC2_7), +.matrixC2_8(matrixC2_8), +.matrixC2_9(matrixC2_9), +.matrixC2_10(matrixC2_10), +.matrixC2_11(matrixC2_11), +.matrixC2_12(matrixC2_12), +.matrixC2_13(matrixC2_13), +.matrixC2_14(matrixC2_14), +.matrixC2_15(matrixC2_15), +.matrixC2_16(matrixC2_16), +.matrixC2_17(matrixC2_17), +.matrixC2_18(matrixC2_18), +.matrixC2_19(matrixC2_19), +.matrixC2_20(matrixC2_20), +.matrixC2_21(matrixC2_21), +.matrixC2_22(matrixC2_22), +.matrixC2_23(matrixC2_23), +.matrixC2_24(matrixC2_24), +.matrixC2_25(matrixC2_25), +.matrixC2_26(matrixC2_26), +.matrixC2_27(matrixC2_27), +.matrixC2_28(matrixC2_28), +.matrixC2_29(matrixC2_29), +.matrixC2_30(matrixC2_30), +.matrixC2_31(matrixC2_31), +.matrixC3_0(matrixC3_0), +.matrixC3_1(matrixC3_1), +.matrixC3_2(matrixC3_2), +.matrixC3_3(matrixC3_3), +.matrixC3_4(matrixC3_4), +.matrixC3_5(matrixC3_5), +.matrixC3_6(matrixC3_6), +.matrixC3_7(matrixC3_7), +.matrixC3_8(matrixC3_8), +.matrixC3_9(matrixC3_9), +.matrixC3_10(matrixC3_10), +.matrixC3_11(matrixC3_11), +.matrixC3_12(matrixC3_12), +.matrixC3_13(matrixC3_13), +.matrixC3_14(matrixC3_14), +.matrixC3_15(matrixC3_15), +.matrixC3_16(matrixC3_16), +.matrixC3_17(matrixC3_17), +.matrixC3_18(matrixC3_18), +.matrixC3_19(matrixC3_19), +.matrixC3_20(matrixC3_20), +.matrixC3_21(matrixC3_21), +.matrixC3_22(matrixC3_22), +.matrixC3_23(matrixC3_23), +.matrixC3_24(matrixC3_24), +.matrixC3_25(matrixC3_25), +.matrixC3_26(matrixC3_26), +.matrixC3_27(matrixC3_27), +.matrixC3_28(matrixC3_28), +.matrixC3_29(matrixC3_29), +.matrixC3_30(matrixC3_30), +.matrixC3_31(matrixC3_31), +.matrixC4_0(matrixC4_0), +.matrixC4_1(matrixC4_1), +.matrixC4_2(matrixC4_2), +.matrixC4_3(matrixC4_3), +.matrixC4_4(matrixC4_4), +.matrixC4_5(matrixC4_5), +.matrixC4_6(matrixC4_6), +.matrixC4_7(matrixC4_7), +.matrixC4_8(matrixC4_8), +.matrixC4_9(matrixC4_9), +.matrixC4_10(matrixC4_10), +.matrixC4_11(matrixC4_11), +.matrixC4_12(matrixC4_12), +.matrixC4_13(matrixC4_13), +.matrixC4_14(matrixC4_14), +.matrixC4_15(matrixC4_15), +.matrixC4_16(matrixC4_16), +.matrixC4_17(matrixC4_17), +.matrixC4_18(matrixC4_18), +.matrixC4_19(matrixC4_19), +.matrixC4_20(matrixC4_20), +.matrixC4_21(matrixC4_21), +.matrixC4_22(matrixC4_22), +.matrixC4_23(matrixC4_23), +.matrixC4_24(matrixC4_24), +.matrixC4_25(matrixC4_25), +.matrixC4_26(matrixC4_26), +.matrixC4_27(matrixC4_27), +.matrixC4_28(matrixC4_28), +.matrixC4_29(matrixC4_29), +.matrixC4_30(matrixC4_30), +.matrixC4_31(matrixC4_31), +.matrixC5_0(matrixC5_0), +.matrixC5_1(matrixC5_1), +.matrixC5_2(matrixC5_2), +.matrixC5_3(matrixC5_3), +.matrixC5_4(matrixC5_4), +.matrixC5_5(matrixC5_5), +.matrixC5_6(matrixC5_6), +.matrixC5_7(matrixC5_7), +.matrixC5_8(matrixC5_8), +.matrixC5_9(matrixC5_9), +.matrixC5_10(matrixC5_10), +.matrixC5_11(matrixC5_11), +.matrixC5_12(matrixC5_12), +.matrixC5_13(matrixC5_13), +.matrixC5_14(matrixC5_14), +.matrixC5_15(matrixC5_15), +.matrixC5_16(matrixC5_16), +.matrixC5_17(matrixC5_17), +.matrixC5_18(matrixC5_18), +.matrixC5_19(matrixC5_19), +.matrixC5_20(matrixC5_20), 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+.matrixC20_25(matrixC20_25), +.matrixC20_26(matrixC20_26), +.matrixC20_27(matrixC20_27), +.matrixC20_28(matrixC20_28), +.matrixC20_29(matrixC20_29), +.matrixC20_30(matrixC20_30), +.matrixC20_31(matrixC20_31), +.matrixC21_0(matrixC21_0), +.matrixC21_1(matrixC21_1), +.matrixC21_2(matrixC21_2), +.matrixC21_3(matrixC21_3), +.matrixC21_4(matrixC21_4), +.matrixC21_5(matrixC21_5), +.matrixC21_6(matrixC21_6), +.matrixC21_7(matrixC21_7), +.matrixC21_8(matrixC21_8), +.matrixC21_9(matrixC21_9), +.matrixC21_10(matrixC21_10), +.matrixC21_11(matrixC21_11), +.matrixC21_12(matrixC21_12), +.matrixC21_13(matrixC21_13), +.matrixC21_14(matrixC21_14), +.matrixC21_15(matrixC21_15), +.matrixC21_16(matrixC21_16), +.matrixC21_17(matrixC21_17), +.matrixC21_18(matrixC21_18), +.matrixC21_19(matrixC21_19), +.matrixC21_20(matrixC21_20), +.matrixC21_21(matrixC21_21), +.matrixC21_22(matrixC21_22), +.matrixC21_23(matrixC21_23), +.matrixC21_24(matrixC21_24), +.matrixC21_25(matrixC21_25), +.matrixC21_26(matrixC21_26), +.matrixC21_27(matrixC21_27), +.matrixC21_28(matrixC21_28), +.matrixC21_29(matrixC21_29), +.matrixC21_30(matrixC21_30), +.matrixC21_31(matrixC21_31), +.matrixC22_0(matrixC22_0), +.matrixC22_1(matrixC22_1), +.matrixC22_2(matrixC22_2), +.matrixC22_3(matrixC22_3), +.matrixC22_4(matrixC22_4), +.matrixC22_5(matrixC22_5), +.matrixC22_6(matrixC22_6), +.matrixC22_7(matrixC22_7), +.matrixC22_8(matrixC22_8), +.matrixC22_9(matrixC22_9), +.matrixC22_10(matrixC22_10), +.matrixC22_11(matrixC22_11), +.matrixC22_12(matrixC22_12), +.matrixC22_13(matrixC22_13), +.matrixC22_14(matrixC22_14), +.matrixC22_15(matrixC22_15), +.matrixC22_16(matrixC22_16), +.matrixC22_17(matrixC22_17), +.matrixC22_18(matrixC22_18), +.matrixC22_19(matrixC22_19), +.matrixC22_20(matrixC22_20), +.matrixC22_21(matrixC22_21), +.matrixC22_22(matrixC22_22), +.matrixC22_23(matrixC22_23), +.matrixC22_24(matrixC22_24), +.matrixC22_25(matrixC22_25), +.matrixC22_26(matrixC22_26), +.matrixC22_27(matrixC22_27), +.matrixC22_28(matrixC22_28), +.matrixC22_29(matrixC22_29), +.matrixC22_30(matrixC22_30), +.matrixC22_31(matrixC22_31), +.matrixC23_0(matrixC23_0), +.matrixC23_1(matrixC23_1), +.matrixC23_2(matrixC23_2), +.matrixC23_3(matrixC23_3), +.matrixC23_4(matrixC23_4), +.matrixC23_5(matrixC23_5), +.matrixC23_6(matrixC23_6), +.matrixC23_7(matrixC23_7), +.matrixC23_8(matrixC23_8), +.matrixC23_9(matrixC23_9), +.matrixC23_10(matrixC23_10), +.matrixC23_11(matrixC23_11), +.matrixC23_12(matrixC23_12), +.matrixC23_13(matrixC23_13), +.matrixC23_14(matrixC23_14), +.matrixC23_15(matrixC23_15), +.matrixC23_16(matrixC23_16), +.matrixC23_17(matrixC23_17), +.matrixC23_18(matrixC23_18), +.matrixC23_19(matrixC23_19), +.matrixC23_20(matrixC23_20), +.matrixC23_21(matrixC23_21), +.matrixC23_22(matrixC23_22), +.matrixC23_23(matrixC23_23), +.matrixC23_24(matrixC23_24), +.matrixC23_25(matrixC23_25), +.matrixC23_26(matrixC23_26), +.matrixC23_27(matrixC23_27), +.matrixC23_28(matrixC23_28), +.matrixC23_29(matrixC23_29), +.matrixC23_30(matrixC23_30), +.matrixC23_31(matrixC23_31), +.matrixC24_0(matrixC24_0), +.matrixC24_1(matrixC24_1), +.matrixC24_2(matrixC24_2), +.matrixC24_3(matrixC24_3), +.matrixC24_4(matrixC24_4), +.matrixC24_5(matrixC24_5), +.matrixC24_6(matrixC24_6), +.matrixC24_7(matrixC24_7), +.matrixC24_8(matrixC24_8), +.matrixC24_9(matrixC24_9), +.matrixC24_10(matrixC24_10), +.matrixC24_11(matrixC24_11), +.matrixC24_12(matrixC24_12), +.matrixC24_13(matrixC24_13), +.matrixC24_14(matrixC24_14), +.matrixC24_15(matrixC24_15), +.matrixC24_16(matrixC24_16), +.matrixC24_17(matrixC24_17), +.matrixC24_18(matrixC24_18), +.matrixC24_19(matrixC24_19), +.matrixC24_20(matrixC24_20), +.matrixC24_21(matrixC24_21), +.matrixC24_22(matrixC24_22), +.matrixC24_23(matrixC24_23), +.matrixC24_24(matrixC24_24), +.matrixC24_25(matrixC24_25), +.matrixC24_26(matrixC24_26), +.matrixC24_27(matrixC24_27), +.matrixC24_28(matrixC24_28), +.matrixC24_29(matrixC24_29), +.matrixC24_30(matrixC24_30), +.matrixC24_31(matrixC24_31), +.matrixC25_0(matrixC25_0), +.matrixC25_1(matrixC25_1), +.matrixC25_2(matrixC25_2), +.matrixC25_3(matrixC25_3), +.matrixC25_4(matrixC25_4), +.matrixC25_5(matrixC25_5), +.matrixC25_6(matrixC25_6), +.matrixC25_7(matrixC25_7), +.matrixC25_8(matrixC25_8), +.matrixC25_9(matrixC25_9), +.matrixC25_10(matrixC25_10), +.matrixC25_11(matrixC25_11), +.matrixC25_12(matrixC25_12), +.matrixC25_13(matrixC25_13), +.matrixC25_14(matrixC25_14), +.matrixC25_15(matrixC25_15), +.matrixC25_16(matrixC25_16), +.matrixC25_17(matrixC25_17), +.matrixC25_18(matrixC25_18), +.matrixC25_19(matrixC25_19), +.matrixC25_20(matrixC25_20), +.matrixC25_21(matrixC25_21), +.matrixC25_22(matrixC25_22), +.matrixC25_23(matrixC25_23), +.matrixC25_24(matrixC25_24), +.matrixC25_25(matrixC25_25), +.matrixC25_26(matrixC25_26), +.matrixC25_27(matrixC25_27), +.matrixC25_28(matrixC25_28), +.matrixC25_29(matrixC25_29), +.matrixC25_30(matrixC25_30), +.matrixC25_31(matrixC25_31), +.matrixC26_0(matrixC26_0), +.matrixC26_1(matrixC26_1), +.matrixC26_2(matrixC26_2), +.matrixC26_3(matrixC26_3), +.matrixC26_4(matrixC26_4), +.matrixC26_5(matrixC26_5), +.matrixC26_6(matrixC26_6), +.matrixC26_7(matrixC26_7), +.matrixC26_8(matrixC26_8), +.matrixC26_9(matrixC26_9), +.matrixC26_10(matrixC26_10), +.matrixC26_11(matrixC26_11), +.matrixC26_12(matrixC26_12), +.matrixC26_13(matrixC26_13), +.matrixC26_14(matrixC26_14), +.matrixC26_15(matrixC26_15), +.matrixC26_16(matrixC26_16), +.matrixC26_17(matrixC26_17), +.matrixC26_18(matrixC26_18), +.matrixC26_19(matrixC26_19), +.matrixC26_20(matrixC26_20), +.matrixC26_21(matrixC26_21), +.matrixC26_22(matrixC26_22), +.matrixC26_23(matrixC26_23), +.matrixC26_24(matrixC26_24), +.matrixC26_25(matrixC26_25), +.matrixC26_26(matrixC26_26), +.matrixC26_27(matrixC26_27), +.matrixC26_28(matrixC26_28), +.matrixC26_29(matrixC26_29), +.matrixC26_30(matrixC26_30), +.matrixC26_31(matrixC26_31), +.matrixC27_0(matrixC27_0), +.matrixC27_1(matrixC27_1), +.matrixC27_2(matrixC27_2), +.matrixC27_3(matrixC27_3), +.matrixC27_4(matrixC27_4), +.matrixC27_5(matrixC27_5), +.matrixC27_6(matrixC27_6), +.matrixC27_7(matrixC27_7), +.matrixC27_8(matrixC27_8), +.matrixC27_9(matrixC27_9), +.matrixC27_10(matrixC27_10), +.matrixC27_11(matrixC27_11), +.matrixC27_12(matrixC27_12), +.matrixC27_13(matrixC27_13), +.matrixC27_14(matrixC27_14), +.matrixC27_15(matrixC27_15), +.matrixC27_16(matrixC27_16), +.matrixC27_17(matrixC27_17), +.matrixC27_18(matrixC27_18), +.matrixC27_19(matrixC27_19), +.matrixC27_20(matrixC27_20), +.matrixC27_21(matrixC27_21), +.matrixC27_22(matrixC27_22), +.matrixC27_23(matrixC27_23), +.matrixC27_24(matrixC27_24), +.matrixC27_25(matrixC27_25), +.matrixC27_26(matrixC27_26), +.matrixC27_27(matrixC27_27), +.matrixC27_28(matrixC27_28), +.matrixC27_29(matrixC27_29), +.matrixC27_30(matrixC27_30), +.matrixC27_31(matrixC27_31), +.matrixC28_0(matrixC28_0), +.matrixC28_1(matrixC28_1), +.matrixC28_2(matrixC28_2), +.matrixC28_3(matrixC28_3), +.matrixC28_4(matrixC28_4), +.matrixC28_5(matrixC28_5), +.matrixC28_6(matrixC28_6), +.matrixC28_7(matrixC28_7), +.matrixC28_8(matrixC28_8), +.matrixC28_9(matrixC28_9), +.matrixC28_10(matrixC28_10), +.matrixC28_11(matrixC28_11), +.matrixC28_12(matrixC28_12), +.matrixC28_13(matrixC28_13), +.matrixC28_14(matrixC28_14), +.matrixC28_15(matrixC28_15), +.matrixC28_16(matrixC28_16), +.matrixC28_17(matrixC28_17), +.matrixC28_18(matrixC28_18), +.matrixC28_19(matrixC28_19), +.matrixC28_20(matrixC28_20), +.matrixC28_21(matrixC28_21), +.matrixC28_22(matrixC28_22), +.matrixC28_23(matrixC28_23), +.matrixC28_24(matrixC28_24), +.matrixC28_25(matrixC28_25), +.matrixC28_26(matrixC28_26), +.matrixC28_27(matrixC28_27), +.matrixC28_28(matrixC28_28), +.matrixC28_29(matrixC28_29), +.matrixC28_30(matrixC28_30), +.matrixC28_31(matrixC28_31), +.matrixC29_0(matrixC29_0), +.matrixC29_1(matrixC29_1), +.matrixC29_2(matrixC29_2), +.matrixC29_3(matrixC29_3), +.matrixC29_4(matrixC29_4), +.matrixC29_5(matrixC29_5), +.matrixC29_6(matrixC29_6), +.matrixC29_7(matrixC29_7), +.matrixC29_8(matrixC29_8), +.matrixC29_9(matrixC29_9), +.matrixC29_10(matrixC29_10), +.matrixC29_11(matrixC29_11), +.matrixC29_12(matrixC29_12), +.matrixC29_13(matrixC29_13), +.matrixC29_14(matrixC29_14), +.matrixC29_15(matrixC29_15), +.matrixC29_16(matrixC29_16), +.matrixC29_17(matrixC29_17), +.matrixC29_18(matrixC29_18), +.matrixC29_19(matrixC29_19), +.matrixC29_20(matrixC29_20), +.matrixC29_21(matrixC29_21), +.matrixC29_22(matrixC29_22), +.matrixC29_23(matrixC29_23), +.matrixC29_24(matrixC29_24), +.matrixC29_25(matrixC29_25), +.matrixC29_26(matrixC29_26), +.matrixC29_27(matrixC29_27), +.matrixC29_28(matrixC29_28), +.matrixC29_29(matrixC29_29), +.matrixC29_30(matrixC29_30), +.matrixC29_31(matrixC29_31), +.matrixC30_0(matrixC30_0), +.matrixC30_1(matrixC30_1), +.matrixC30_2(matrixC30_2), +.matrixC30_3(matrixC30_3), +.matrixC30_4(matrixC30_4), +.matrixC30_5(matrixC30_5), +.matrixC30_6(matrixC30_6), +.matrixC30_7(matrixC30_7), +.matrixC30_8(matrixC30_8), +.matrixC30_9(matrixC30_9), +.matrixC30_10(matrixC30_10), +.matrixC30_11(matrixC30_11), +.matrixC30_12(matrixC30_12), +.matrixC30_13(matrixC30_13), +.matrixC30_14(matrixC30_14), +.matrixC30_15(matrixC30_15), +.matrixC30_16(matrixC30_16), +.matrixC30_17(matrixC30_17), +.matrixC30_18(matrixC30_18), +.matrixC30_19(matrixC30_19), +.matrixC30_20(matrixC30_20), +.matrixC30_21(matrixC30_21), +.matrixC30_22(matrixC30_22), +.matrixC30_23(matrixC30_23), +.matrixC30_24(matrixC30_24), +.matrixC30_25(matrixC30_25), +.matrixC30_26(matrixC30_26), +.matrixC30_27(matrixC30_27), +.matrixC30_28(matrixC30_28), +.matrixC30_29(matrixC30_29), +.matrixC30_30(matrixC30_30), +.matrixC30_31(matrixC30_31), +.matrixC31_0(matrixC31_0), +.matrixC31_1(matrixC31_1), +.matrixC31_2(matrixC31_2), +.matrixC31_3(matrixC31_3), +.matrixC31_4(matrixC31_4), +.matrixC31_5(matrixC31_5), +.matrixC31_6(matrixC31_6), +.matrixC31_7(matrixC31_7), +.matrixC31_8(matrixC31_8), +.matrixC31_9(matrixC31_9), +.matrixC31_10(matrixC31_10), +.matrixC31_11(matrixC31_11), +.matrixC31_12(matrixC31_12), +.matrixC31_13(matrixC31_13), +.matrixC31_14(matrixC31_14), +.matrixC31_15(matrixC31_15), +.matrixC31_16(matrixC31_16), +.matrixC31_17(matrixC31_17), +.matrixC31_18(matrixC31_18), +.matrixC31_19(matrixC31_19), +.matrixC31_20(matrixC31_20), +.matrixC31_21(matrixC31_21), +.matrixC31_22(matrixC31_22), +.matrixC31_23(matrixC31_23), +.matrixC31_24(matrixC31_24), +.matrixC31_25(matrixC31_25), +.matrixC31_26(matrixC31_26), +.matrixC31_27(matrixC31_27), +.matrixC31_28(matrixC31_28), +.matrixC31_29(matrixC31_29), +.matrixC31_30(matrixC31_30), +.matrixC31_31(matrixC31_31), + +.clk(clk), +.reset(reset) +); + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +systolic_pe_matrix u_systolic_pe_matrix( +.clk(clk), +.reset(reset), +.pe_reset(pe_reset), +.a0(a0), +.a1(a1), +.a2(a2), +.a3(a3), +.a4(a4), +.a5(a5), +.a6(a6), +.a7(a7), +.a8(a8), +.a9(a9), +.a10(a10), +.a11(a11), +.a12(a12), +.a13(a13), +.a14(a14), +.a15(a15), +.a16(a16), +.a17(a17), +.a18(a18), +.a19(a19), +.a20(a20), +.a21(a21), +.a22(a22), +.a23(a23), +.a24(a24), +.a25(a25), +.a26(a26), +.a27(a27), +.a28(a28), +.a29(a29), +.a30(a30), +.a31(a31), +.b0(b0), +.b1(b1), +.b2(b2), +.b3(b3), +.b4(b4), +.b5(b5), +.b6(b6), +.b7(b7), +.b8(b8), +.b9(b9), +.b10(b10), +.b11(b11), +.b12(b12), +.b13(b13), +.b14(b14), +.b15(b15), +.b16(b16), +.b17(b17), +.b18(b18), +.b19(b19), +.b20(b20), +.b21(b21), +.b22(b22), +.b23(b23), +.b24(b24), +.b25(b25), +.b26(b26), +.b27(b27), +.b28(b28), +.b29(b29), +.b30(b30), +.b31(b31), +.matrixC0_0(matrixC0_0), +.matrixC0_1(matrixC0_1), +.matrixC0_2(matrixC0_2), +.matrixC0_3(matrixC0_3), +.matrixC0_4(matrixC0_4), +.matrixC0_5(matrixC0_5), +.matrixC0_6(matrixC0_6), +.matrixC0_7(matrixC0_7), +.matrixC0_8(matrixC0_8), +.matrixC0_9(matrixC0_9), +.matrixC0_10(matrixC0_10), +.matrixC0_11(matrixC0_11), +.matrixC0_12(matrixC0_12), +.matrixC0_13(matrixC0_13), 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+.matrixC17_31(matrixC17_31), +.matrixC18_0(matrixC18_0), +.matrixC18_1(matrixC18_1), +.matrixC18_2(matrixC18_2), +.matrixC18_3(matrixC18_3), +.matrixC18_4(matrixC18_4), +.matrixC18_5(matrixC18_5), +.matrixC18_6(matrixC18_6), +.matrixC18_7(matrixC18_7), +.matrixC18_8(matrixC18_8), +.matrixC18_9(matrixC18_9), +.matrixC18_10(matrixC18_10), +.matrixC18_11(matrixC18_11), +.matrixC18_12(matrixC18_12), +.matrixC18_13(matrixC18_13), +.matrixC18_14(matrixC18_14), +.matrixC18_15(matrixC18_15), +.matrixC18_16(matrixC18_16), +.matrixC18_17(matrixC18_17), +.matrixC18_18(matrixC18_18), +.matrixC18_19(matrixC18_19), +.matrixC18_20(matrixC18_20), +.matrixC18_21(matrixC18_21), +.matrixC18_22(matrixC18_22), +.matrixC18_23(matrixC18_23), +.matrixC18_24(matrixC18_24), +.matrixC18_25(matrixC18_25), +.matrixC18_26(matrixC18_26), +.matrixC18_27(matrixC18_27), +.matrixC18_28(matrixC18_28), +.matrixC18_29(matrixC18_29), +.matrixC18_30(matrixC18_30), +.matrixC18_31(matrixC18_31), +.matrixC19_0(matrixC19_0), +.matrixC19_1(matrixC19_1), +.matrixC19_2(matrixC19_2), +.matrixC19_3(matrixC19_3), +.matrixC19_4(matrixC19_4), +.matrixC19_5(matrixC19_5), +.matrixC19_6(matrixC19_6), +.matrixC19_7(matrixC19_7), +.matrixC19_8(matrixC19_8), +.matrixC19_9(matrixC19_9), +.matrixC19_10(matrixC19_10), +.matrixC19_11(matrixC19_11), +.matrixC19_12(matrixC19_12), +.matrixC19_13(matrixC19_13), +.matrixC19_14(matrixC19_14), +.matrixC19_15(matrixC19_15), +.matrixC19_16(matrixC19_16), +.matrixC19_17(matrixC19_17), +.matrixC19_18(matrixC19_18), +.matrixC19_19(matrixC19_19), +.matrixC19_20(matrixC19_20), +.matrixC19_21(matrixC19_21), +.matrixC19_22(matrixC19_22), +.matrixC19_23(matrixC19_23), +.matrixC19_24(matrixC19_24), +.matrixC19_25(matrixC19_25), +.matrixC19_26(matrixC19_26), +.matrixC19_27(matrixC19_27), +.matrixC19_28(matrixC19_28), +.matrixC19_29(matrixC19_29), +.matrixC19_30(matrixC19_30), +.matrixC19_31(matrixC19_31), +.matrixC20_0(matrixC20_0), +.matrixC20_1(matrixC20_1), +.matrixC20_2(matrixC20_2), +.matrixC20_3(matrixC20_3), +.matrixC20_4(matrixC20_4), +.matrixC20_5(matrixC20_5), +.matrixC20_6(matrixC20_6), +.matrixC20_7(matrixC20_7), +.matrixC20_8(matrixC20_8), +.matrixC20_9(matrixC20_9), +.matrixC20_10(matrixC20_10), +.matrixC20_11(matrixC20_11), +.matrixC20_12(matrixC20_12), +.matrixC20_13(matrixC20_13), +.matrixC20_14(matrixC20_14), +.matrixC20_15(matrixC20_15), +.matrixC20_16(matrixC20_16), +.matrixC20_17(matrixC20_17), +.matrixC20_18(matrixC20_18), +.matrixC20_19(matrixC20_19), +.matrixC20_20(matrixC20_20), +.matrixC20_21(matrixC20_21), +.matrixC20_22(matrixC20_22), +.matrixC20_23(matrixC20_23), +.matrixC20_24(matrixC20_24), +.matrixC20_25(matrixC20_25), +.matrixC20_26(matrixC20_26), +.matrixC20_27(matrixC20_27), +.matrixC20_28(matrixC20_28), +.matrixC20_29(matrixC20_29), +.matrixC20_30(matrixC20_30), +.matrixC20_31(matrixC20_31), +.matrixC21_0(matrixC21_0), +.matrixC21_1(matrixC21_1), +.matrixC21_2(matrixC21_2), +.matrixC21_3(matrixC21_3), +.matrixC21_4(matrixC21_4), +.matrixC21_5(matrixC21_5), +.matrixC21_6(matrixC21_6), +.matrixC21_7(matrixC21_7), +.matrixC21_8(matrixC21_8), +.matrixC21_9(matrixC21_9), +.matrixC21_10(matrixC21_10), +.matrixC21_11(matrixC21_11), +.matrixC21_12(matrixC21_12), +.matrixC21_13(matrixC21_13), +.matrixC21_14(matrixC21_14), +.matrixC21_15(matrixC21_15), +.matrixC21_16(matrixC21_16), +.matrixC21_17(matrixC21_17), +.matrixC21_18(matrixC21_18), +.matrixC21_19(matrixC21_19), +.matrixC21_20(matrixC21_20), +.matrixC21_21(matrixC21_21), +.matrixC21_22(matrixC21_22), +.matrixC21_23(matrixC21_23), +.matrixC21_24(matrixC21_24), +.matrixC21_25(matrixC21_25), +.matrixC21_26(matrixC21_26), +.matrixC21_27(matrixC21_27), +.matrixC21_28(matrixC21_28), +.matrixC21_29(matrixC21_29), +.matrixC21_30(matrixC21_30), +.matrixC21_31(matrixC21_31), +.matrixC22_0(matrixC22_0), +.matrixC22_1(matrixC22_1), +.matrixC22_2(matrixC22_2), +.matrixC22_3(matrixC22_3), +.matrixC22_4(matrixC22_4), +.matrixC22_5(matrixC22_5), +.matrixC22_6(matrixC22_6), +.matrixC22_7(matrixC22_7), +.matrixC22_8(matrixC22_8), +.matrixC22_9(matrixC22_9), +.matrixC22_10(matrixC22_10), +.matrixC22_11(matrixC22_11), +.matrixC22_12(matrixC22_12), +.matrixC22_13(matrixC22_13), +.matrixC22_14(matrixC22_14), +.matrixC22_15(matrixC22_15), +.matrixC22_16(matrixC22_16), +.matrixC22_17(matrixC22_17), +.matrixC22_18(matrixC22_18), +.matrixC22_19(matrixC22_19), +.matrixC22_20(matrixC22_20), +.matrixC22_21(matrixC22_21), +.matrixC22_22(matrixC22_22), +.matrixC22_23(matrixC22_23), +.matrixC22_24(matrixC22_24), +.matrixC22_25(matrixC22_25), +.matrixC22_26(matrixC22_26), +.matrixC22_27(matrixC22_27), +.matrixC22_28(matrixC22_28), +.matrixC22_29(matrixC22_29), +.matrixC22_30(matrixC22_30), +.matrixC22_31(matrixC22_31), +.matrixC23_0(matrixC23_0), +.matrixC23_1(matrixC23_1), +.matrixC23_2(matrixC23_2), +.matrixC23_3(matrixC23_3), +.matrixC23_4(matrixC23_4), +.matrixC23_5(matrixC23_5), +.matrixC23_6(matrixC23_6), +.matrixC23_7(matrixC23_7), +.matrixC23_8(matrixC23_8), +.matrixC23_9(matrixC23_9), +.matrixC23_10(matrixC23_10), +.matrixC23_11(matrixC23_11), +.matrixC23_12(matrixC23_12), +.matrixC23_13(matrixC23_13), +.matrixC23_14(matrixC23_14), +.matrixC23_15(matrixC23_15), +.matrixC23_16(matrixC23_16), +.matrixC23_17(matrixC23_17), +.matrixC23_18(matrixC23_18), +.matrixC23_19(matrixC23_19), +.matrixC23_20(matrixC23_20), +.matrixC23_21(matrixC23_21), +.matrixC23_22(matrixC23_22), +.matrixC23_23(matrixC23_23), +.matrixC23_24(matrixC23_24), +.matrixC23_25(matrixC23_25), +.matrixC23_26(matrixC23_26), +.matrixC23_27(matrixC23_27), +.matrixC23_28(matrixC23_28), +.matrixC23_29(matrixC23_29), +.matrixC23_30(matrixC23_30), +.matrixC23_31(matrixC23_31), +.matrixC24_0(matrixC24_0), +.matrixC24_1(matrixC24_1), +.matrixC24_2(matrixC24_2), +.matrixC24_3(matrixC24_3), +.matrixC24_4(matrixC24_4), +.matrixC24_5(matrixC24_5), +.matrixC24_6(matrixC24_6), +.matrixC24_7(matrixC24_7), +.matrixC24_8(matrixC24_8), +.matrixC24_9(matrixC24_9), +.matrixC24_10(matrixC24_10), +.matrixC24_11(matrixC24_11), +.matrixC24_12(matrixC24_12), +.matrixC24_13(matrixC24_13), +.matrixC24_14(matrixC24_14), +.matrixC24_15(matrixC24_15), +.matrixC24_16(matrixC24_16), +.matrixC24_17(matrixC24_17), +.matrixC24_18(matrixC24_18), +.matrixC24_19(matrixC24_19), +.matrixC24_20(matrixC24_20), +.matrixC24_21(matrixC24_21), +.matrixC24_22(matrixC24_22), +.matrixC24_23(matrixC24_23), +.matrixC24_24(matrixC24_24), +.matrixC24_25(matrixC24_25), +.matrixC24_26(matrixC24_26), +.matrixC24_27(matrixC24_27), +.matrixC24_28(matrixC24_28), +.matrixC24_29(matrixC24_29), +.matrixC24_30(matrixC24_30), +.matrixC24_31(matrixC24_31), +.matrixC25_0(matrixC25_0), +.matrixC25_1(matrixC25_1), +.matrixC25_2(matrixC25_2), +.matrixC25_3(matrixC25_3), +.matrixC25_4(matrixC25_4), +.matrixC25_5(matrixC25_5), +.matrixC25_6(matrixC25_6), +.matrixC25_7(matrixC25_7), +.matrixC25_8(matrixC25_8), +.matrixC25_9(matrixC25_9), +.matrixC25_10(matrixC25_10), +.matrixC25_11(matrixC25_11), +.matrixC25_12(matrixC25_12), +.matrixC25_13(matrixC25_13), +.matrixC25_14(matrixC25_14), +.matrixC25_15(matrixC25_15), +.matrixC25_16(matrixC25_16), +.matrixC25_17(matrixC25_17), +.matrixC25_18(matrixC25_18), +.matrixC25_19(matrixC25_19), +.matrixC25_20(matrixC25_20), +.matrixC25_21(matrixC25_21), +.matrixC25_22(matrixC25_22), +.matrixC25_23(matrixC25_23), +.matrixC25_24(matrixC25_24), +.matrixC25_25(matrixC25_25), +.matrixC25_26(matrixC25_26), +.matrixC25_27(matrixC25_27), +.matrixC25_28(matrixC25_28), +.matrixC25_29(matrixC25_29), +.matrixC25_30(matrixC25_30), +.matrixC25_31(matrixC25_31), +.matrixC26_0(matrixC26_0), +.matrixC26_1(matrixC26_1), +.matrixC26_2(matrixC26_2), +.matrixC26_3(matrixC26_3), +.matrixC26_4(matrixC26_4), +.matrixC26_5(matrixC26_5), +.matrixC26_6(matrixC26_6), +.matrixC26_7(matrixC26_7), +.matrixC26_8(matrixC26_8), +.matrixC26_9(matrixC26_9), +.matrixC26_10(matrixC26_10), +.matrixC26_11(matrixC26_11), +.matrixC26_12(matrixC26_12), +.matrixC26_13(matrixC26_13), +.matrixC26_14(matrixC26_14), +.matrixC26_15(matrixC26_15), +.matrixC26_16(matrixC26_16), +.matrixC26_17(matrixC26_17), +.matrixC26_18(matrixC26_18), +.matrixC26_19(matrixC26_19), +.matrixC26_20(matrixC26_20), +.matrixC26_21(matrixC26_21), +.matrixC26_22(matrixC26_22), +.matrixC26_23(matrixC26_23), +.matrixC26_24(matrixC26_24), +.matrixC26_25(matrixC26_25), +.matrixC26_26(matrixC26_26), +.matrixC26_27(matrixC26_27), +.matrixC26_28(matrixC26_28), +.matrixC26_29(matrixC26_29), +.matrixC26_30(matrixC26_30), +.matrixC26_31(matrixC26_31), +.matrixC27_0(matrixC27_0), +.matrixC27_1(matrixC27_1), +.matrixC27_2(matrixC27_2), +.matrixC27_3(matrixC27_3), +.matrixC27_4(matrixC27_4), +.matrixC27_5(matrixC27_5), +.matrixC27_6(matrixC27_6), +.matrixC27_7(matrixC27_7), +.matrixC27_8(matrixC27_8), +.matrixC27_9(matrixC27_9), +.matrixC27_10(matrixC27_10), +.matrixC27_11(matrixC27_11), +.matrixC27_12(matrixC27_12), +.matrixC27_13(matrixC27_13), +.matrixC27_14(matrixC27_14), +.matrixC27_15(matrixC27_15), +.matrixC27_16(matrixC27_16), +.matrixC27_17(matrixC27_17), +.matrixC27_18(matrixC27_18), +.matrixC27_19(matrixC27_19), +.matrixC27_20(matrixC27_20), +.matrixC27_21(matrixC27_21), +.matrixC27_22(matrixC27_22), +.matrixC27_23(matrixC27_23), +.matrixC27_24(matrixC27_24), +.matrixC27_25(matrixC27_25), +.matrixC27_26(matrixC27_26), +.matrixC27_27(matrixC27_27), +.matrixC27_28(matrixC27_28), +.matrixC27_29(matrixC27_29), +.matrixC27_30(matrixC27_30), +.matrixC27_31(matrixC27_31), +.matrixC28_0(matrixC28_0), +.matrixC28_1(matrixC28_1), +.matrixC28_2(matrixC28_2), +.matrixC28_3(matrixC28_3), +.matrixC28_4(matrixC28_4), +.matrixC28_5(matrixC28_5), +.matrixC28_6(matrixC28_6), +.matrixC28_7(matrixC28_7), +.matrixC28_8(matrixC28_8), +.matrixC28_9(matrixC28_9), +.matrixC28_10(matrixC28_10), +.matrixC28_11(matrixC28_11), +.matrixC28_12(matrixC28_12), +.matrixC28_13(matrixC28_13), +.matrixC28_14(matrixC28_14), +.matrixC28_15(matrixC28_15), +.matrixC28_16(matrixC28_16), +.matrixC28_17(matrixC28_17), +.matrixC28_18(matrixC28_18), +.matrixC28_19(matrixC28_19), +.matrixC28_20(matrixC28_20), +.matrixC28_21(matrixC28_21), +.matrixC28_22(matrixC28_22), +.matrixC28_23(matrixC28_23), +.matrixC28_24(matrixC28_24), +.matrixC28_25(matrixC28_25), +.matrixC28_26(matrixC28_26), +.matrixC28_27(matrixC28_27), +.matrixC28_28(matrixC28_28), +.matrixC28_29(matrixC28_29), +.matrixC28_30(matrixC28_30), +.matrixC28_31(matrixC28_31), +.matrixC29_0(matrixC29_0), +.matrixC29_1(matrixC29_1), +.matrixC29_2(matrixC29_2), +.matrixC29_3(matrixC29_3), +.matrixC29_4(matrixC29_4), +.matrixC29_5(matrixC29_5), +.matrixC29_6(matrixC29_6), +.matrixC29_7(matrixC29_7), +.matrixC29_8(matrixC29_8), +.matrixC29_9(matrixC29_9), +.matrixC29_10(matrixC29_10), +.matrixC29_11(matrixC29_11), +.matrixC29_12(matrixC29_12), +.matrixC29_13(matrixC29_13), +.matrixC29_14(matrixC29_14), +.matrixC29_15(matrixC29_15), +.matrixC29_16(matrixC29_16), +.matrixC29_17(matrixC29_17), +.matrixC29_18(matrixC29_18), +.matrixC29_19(matrixC29_19), +.matrixC29_20(matrixC29_20), +.matrixC29_21(matrixC29_21), +.matrixC29_22(matrixC29_22), +.matrixC29_23(matrixC29_23), +.matrixC29_24(matrixC29_24), +.matrixC29_25(matrixC29_25), +.matrixC29_26(matrixC29_26), +.matrixC29_27(matrixC29_27), +.matrixC29_28(matrixC29_28), +.matrixC29_29(matrixC29_29), +.matrixC29_30(matrixC29_30), +.matrixC29_31(matrixC29_31), +.matrixC30_0(matrixC30_0), +.matrixC30_1(matrixC30_1), +.matrixC30_2(matrixC30_2), +.matrixC30_3(matrixC30_3), +.matrixC30_4(matrixC30_4), +.matrixC30_5(matrixC30_5), +.matrixC30_6(matrixC30_6), +.matrixC30_7(matrixC30_7), +.matrixC30_8(matrixC30_8), +.matrixC30_9(matrixC30_9), +.matrixC30_10(matrixC30_10), +.matrixC30_11(matrixC30_11), +.matrixC30_12(matrixC30_12), +.matrixC30_13(matrixC30_13), +.matrixC30_14(matrixC30_14), +.matrixC30_15(matrixC30_15), +.matrixC30_16(matrixC30_16), +.matrixC30_17(matrixC30_17), +.matrixC30_18(matrixC30_18), +.matrixC30_19(matrixC30_19), +.matrixC30_20(matrixC30_20), +.matrixC30_21(matrixC30_21), +.matrixC30_22(matrixC30_22), +.matrixC30_23(matrixC30_23), +.matrixC30_24(matrixC30_24), +.matrixC30_25(matrixC30_25), +.matrixC30_26(matrixC30_26), +.matrixC30_27(matrixC30_27), +.matrixC30_28(matrixC30_28), +.matrixC30_29(matrixC30_29), +.matrixC30_30(matrixC30_30), +.matrixC30_31(matrixC30_31), +.matrixC31_0(matrixC31_0), +.matrixC31_1(matrixC31_1), +.matrixC31_2(matrixC31_2), +.matrixC31_3(matrixC31_3), +.matrixC31_4(matrixC31_4), +.matrixC31_5(matrixC31_5), +.matrixC31_6(matrixC31_6), +.matrixC31_7(matrixC31_7), +.matrixC31_8(matrixC31_8), +.matrixC31_9(matrixC31_9), +.matrixC31_10(matrixC31_10), +.matrixC31_11(matrixC31_11), +.matrixC31_12(matrixC31_12), +.matrixC31_13(matrixC31_13), +.matrixC31_14(matrixC31_14), +.matrixC31_15(matrixC31_15), +.matrixC31_16(matrixC31_16), +.matrixC31_17(matrixC31_17), +.matrixC31_18(matrixC31_18), +.matrixC31_19(matrixC31_19), +.matrixC31_20(matrixC31_20), +.matrixC31_21(matrixC31_21), +.matrixC31_22(matrixC31_22), +.matrixC31_23(matrixC31_23), +.matrixC31_24(matrixC31_24), +.matrixC31_25(matrixC31_25), +.matrixC31_26(matrixC31_26), +.matrixC31_27(matrixC31_27), +.matrixC31_28(matrixC31_28), +.matrixC31_29(matrixC31_29), +.matrixC31_30(matrixC31_30), +.matrixC31_31(matrixC31_31), + +.a_data_out(a_data_out), +.b_data_out(b_data_out) +); + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Output logic +////////////////////////////////////////////////////////////////////////// +module output_logic( +start_mat_mul, +done_mat_mul, +address_mat_c, +address_stride_c, +c_data_in, +c_data_out, //Data values going out to next matmul - systolic shifting +c_addr, +c_data_available, +clk_cnt, +row_latch_en, +final_mat_mul_size, +matrixC0_0, +matrixC0_1, +matrixC0_2, +matrixC0_3, +matrixC0_4, +matrixC0_5, +matrixC0_6, +matrixC0_7, +matrixC0_8, +matrixC0_9, +matrixC0_10, +matrixC0_11, +matrixC0_12, +matrixC0_13, +matrixC0_14, +matrixC0_15, +matrixC0_16, +matrixC0_17, +matrixC0_18, +matrixC0_19, +matrixC0_20, +matrixC0_21, +matrixC0_22, +matrixC0_23, +matrixC0_24, +matrixC0_25, +matrixC0_26, +matrixC0_27, +matrixC0_28, +matrixC0_29, +matrixC0_30, +matrixC0_31, +matrixC1_0, +matrixC1_1, +matrixC1_2, +matrixC1_3, +matrixC1_4, +matrixC1_5, +matrixC1_6, +matrixC1_7, +matrixC1_8, +matrixC1_9, +matrixC1_10, +matrixC1_11, +matrixC1_12, +matrixC1_13, +matrixC1_14, +matrixC1_15, +matrixC1_16, +matrixC1_17, +matrixC1_18, +matrixC1_19, +matrixC1_20, +matrixC1_21, +matrixC1_22, +matrixC1_23, +matrixC1_24, +matrixC1_25, +matrixC1_26, +matrixC1_27, +matrixC1_28, +matrixC1_29, +matrixC1_30, +matrixC1_31, +matrixC2_0, +matrixC2_1, +matrixC2_2, +matrixC2_3, +matrixC2_4, +matrixC2_5, +matrixC2_6, +matrixC2_7, +matrixC2_8, +matrixC2_9, +matrixC2_10, +matrixC2_11, +matrixC2_12, +matrixC2_13, +matrixC2_14, +matrixC2_15, +matrixC2_16, +matrixC2_17, +matrixC2_18, +matrixC2_19, +matrixC2_20, +matrixC2_21, +matrixC2_22, +matrixC2_23, +matrixC2_24, +matrixC2_25, +matrixC2_26, +matrixC2_27, +matrixC2_28, +matrixC2_29, +matrixC2_30, +matrixC2_31, +matrixC3_0, +matrixC3_1, +matrixC3_2, +matrixC3_3, +matrixC3_4, +matrixC3_5, +matrixC3_6, +matrixC3_7, +matrixC3_8, +matrixC3_9, +matrixC3_10, +matrixC3_11, +matrixC3_12, +matrixC3_13, +matrixC3_14, +matrixC3_15, +matrixC3_16, +matrixC3_17, +matrixC3_18, +matrixC3_19, +matrixC3_20, +matrixC3_21, +matrixC3_22, +matrixC3_23, +matrixC3_24, +matrixC3_25, +matrixC3_26, +matrixC3_27, +matrixC3_28, +matrixC3_29, +matrixC3_30, +matrixC3_31, +matrixC4_0, +matrixC4_1, +matrixC4_2, +matrixC4_3, +matrixC4_4, +matrixC4_5, +matrixC4_6, +matrixC4_7, +matrixC4_8, +matrixC4_9, +matrixC4_10, +matrixC4_11, +matrixC4_12, +matrixC4_13, +matrixC4_14, +matrixC4_15, +matrixC4_16, +matrixC4_17, +matrixC4_18, +matrixC4_19, +matrixC4_20, +matrixC4_21, +matrixC4_22, +matrixC4_23, +matrixC4_24, +matrixC4_25, +matrixC4_26, +matrixC4_27, +matrixC4_28, +matrixC4_29, +matrixC4_30, +matrixC4_31, +matrixC5_0, +matrixC5_1, +matrixC5_2, +matrixC5_3, +matrixC5_4, +matrixC5_5, +matrixC5_6, +matrixC5_7, +matrixC5_8, +matrixC5_9, +matrixC5_10, +matrixC5_11, +matrixC5_12, +matrixC5_13, +matrixC5_14, +matrixC5_15, +matrixC5_16, +matrixC5_17, +matrixC5_18, +matrixC5_19, +matrixC5_20, +matrixC5_21, +matrixC5_22, +matrixC5_23, +matrixC5_24, +matrixC5_25, +matrixC5_26, +matrixC5_27, +matrixC5_28, +matrixC5_29, +matrixC5_30, +matrixC5_31, +matrixC6_0, +matrixC6_1, +matrixC6_2, +matrixC6_3, +matrixC6_4, +matrixC6_5, +matrixC6_6, +matrixC6_7, +matrixC6_8, +matrixC6_9, +matrixC6_10, +matrixC6_11, +matrixC6_12, +matrixC6_13, +matrixC6_14, +matrixC6_15, +matrixC6_16, +matrixC6_17, +matrixC6_18, +matrixC6_19, +matrixC6_20, +matrixC6_21, +matrixC6_22, +matrixC6_23, +matrixC6_24, +matrixC6_25, +matrixC6_26, +matrixC6_27, +matrixC6_28, +matrixC6_29, +matrixC6_30, +matrixC6_31, +matrixC7_0, +matrixC7_1, +matrixC7_2, +matrixC7_3, +matrixC7_4, +matrixC7_5, +matrixC7_6, +matrixC7_7, +matrixC7_8, +matrixC7_9, +matrixC7_10, +matrixC7_11, +matrixC7_12, +matrixC7_13, +matrixC7_14, +matrixC7_15, +matrixC7_16, +matrixC7_17, +matrixC7_18, +matrixC7_19, +matrixC7_20, +matrixC7_21, +matrixC7_22, +matrixC7_23, +matrixC7_24, +matrixC7_25, +matrixC7_26, +matrixC7_27, +matrixC7_28, +matrixC7_29, +matrixC7_30, +matrixC7_31, +matrixC8_0, +matrixC8_1, +matrixC8_2, +matrixC8_3, +matrixC8_4, +matrixC8_5, +matrixC8_6, +matrixC8_7, +matrixC8_8, +matrixC8_9, +matrixC8_10, +matrixC8_11, +matrixC8_12, +matrixC8_13, +matrixC8_14, +matrixC8_15, +matrixC8_16, +matrixC8_17, +matrixC8_18, +matrixC8_19, +matrixC8_20, +matrixC8_21, +matrixC8_22, +matrixC8_23, +matrixC8_24, +matrixC8_25, +matrixC8_26, +matrixC8_27, +matrixC8_28, +matrixC8_29, +matrixC8_30, +matrixC8_31, +matrixC9_0, +matrixC9_1, +matrixC9_2, +matrixC9_3, +matrixC9_4, +matrixC9_5, +matrixC9_6, +matrixC9_7, +matrixC9_8, +matrixC9_9, +matrixC9_10, +matrixC9_11, +matrixC9_12, +matrixC9_13, +matrixC9_14, +matrixC9_15, +matrixC9_16, +matrixC9_17, +matrixC9_18, +matrixC9_19, +matrixC9_20, +matrixC9_21, +matrixC9_22, +matrixC9_23, +matrixC9_24, +matrixC9_25, +matrixC9_26, +matrixC9_27, +matrixC9_28, +matrixC9_29, +matrixC9_30, +matrixC9_31, +matrixC10_0, +matrixC10_1, +matrixC10_2, +matrixC10_3, +matrixC10_4, +matrixC10_5, +matrixC10_6, +matrixC10_7, +matrixC10_8, +matrixC10_9, +matrixC10_10, +matrixC10_11, +matrixC10_12, +matrixC10_13, +matrixC10_14, +matrixC10_15, +matrixC10_16, +matrixC10_17, +matrixC10_18, +matrixC10_19, +matrixC10_20, +matrixC10_21, +matrixC10_22, +matrixC10_23, +matrixC10_24, +matrixC10_25, +matrixC10_26, +matrixC10_27, +matrixC10_28, +matrixC10_29, +matrixC10_30, +matrixC10_31, +matrixC11_0, +matrixC11_1, +matrixC11_2, +matrixC11_3, +matrixC11_4, +matrixC11_5, +matrixC11_6, +matrixC11_7, +matrixC11_8, +matrixC11_9, +matrixC11_10, +matrixC11_11, +matrixC11_12, +matrixC11_13, +matrixC11_14, +matrixC11_15, +matrixC11_16, +matrixC11_17, +matrixC11_18, +matrixC11_19, +matrixC11_20, +matrixC11_21, +matrixC11_22, +matrixC11_23, +matrixC11_24, +matrixC11_25, +matrixC11_26, +matrixC11_27, +matrixC11_28, +matrixC11_29, +matrixC11_30, +matrixC11_31, +matrixC12_0, +matrixC12_1, +matrixC12_2, +matrixC12_3, +matrixC12_4, +matrixC12_5, +matrixC12_6, +matrixC12_7, +matrixC12_8, +matrixC12_9, +matrixC12_10, +matrixC12_11, +matrixC12_12, +matrixC12_13, +matrixC12_14, +matrixC12_15, +matrixC12_16, +matrixC12_17, +matrixC12_18, +matrixC12_19, +matrixC12_20, +matrixC12_21, +matrixC12_22, +matrixC12_23, +matrixC12_24, +matrixC12_25, +matrixC12_26, +matrixC12_27, +matrixC12_28, +matrixC12_29, +matrixC12_30, +matrixC12_31, +matrixC13_0, +matrixC13_1, +matrixC13_2, +matrixC13_3, +matrixC13_4, +matrixC13_5, +matrixC13_6, +matrixC13_7, +matrixC13_8, +matrixC13_9, +matrixC13_10, +matrixC13_11, +matrixC13_12, +matrixC13_13, +matrixC13_14, +matrixC13_15, +matrixC13_16, +matrixC13_17, +matrixC13_18, +matrixC13_19, +matrixC13_20, +matrixC13_21, +matrixC13_22, +matrixC13_23, +matrixC13_24, +matrixC13_25, +matrixC13_26, +matrixC13_27, +matrixC13_28, +matrixC13_29, +matrixC13_30, +matrixC13_31, +matrixC14_0, +matrixC14_1, +matrixC14_2, +matrixC14_3, +matrixC14_4, +matrixC14_5, +matrixC14_6, +matrixC14_7, +matrixC14_8, +matrixC14_9, +matrixC14_10, +matrixC14_11, +matrixC14_12, +matrixC14_13, +matrixC14_14, +matrixC14_15, +matrixC14_16, +matrixC14_17, +matrixC14_18, +matrixC14_19, +matrixC14_20, +matrixC14_21, +matrixC14_22, +matrixC14_23, +matrixC14_24, +matrixC14_25, +matrixC14_26, +matrixC14_27, +matrixC14_28, +matrixC14_29, +matrixC14_30, +matrixC14_31, +matrixC15_0, +matrixC15_1, +matrixC15_2, +matrixC15_3, +matrixC15_4, +matrixC15_5, +matrixC15_6, +matrixC15_7, +matrixC15_8, +matrixC15_9, +matrixC15_10, +matrixC15_11, +matrixC15_12, +matrixC15_13, +matrixC15_14, +matrixC15_15, +matrixC15_16, +matrixC15_17, +matrixC15_18, +matrixC15_19, +matrixC15_20, +matrixC15_21, +matrixC15_22, +matrixC15_23, +matrixC15_24, +matrixC15_25, +matrixC15_26, +matrixC15_27, +matrixC15_28, +matrixC15_29, +matrixC15_30, +matrixC15_31, +matrixC16_0, +matrixC16_1, +matrixC16_2, +matrixC16_3, +matrixC16_4, +matrixC16_5, +matrixC16_6, +matrixC16_7, +matrixC16_8, +matrixC16_9, +matrixC16_10, +matrixC16_11, +matrixC16_12, +matrixC16_13, +matrixC16_14, +matrixC16_15, +matrixC16_16, +matrixC16_17, +matrixC16_18, +matrixC16_19, +matrixC16_20, +matrixC16_21, +matrixC16_22, +matrixC16_23, +matrixC16_24, +matrixC16_25, +matrixC16_26, +matrixC16_27, +matrixC16_28, +matrixC16_29, +matrixC16_30, +matrixC16_31, +matrixC17_0, +matrixC17_1, +matrixC17_2, +matrixC17_3, +matrixC17_4, +matrixC17_5, +matrixC17_6, +matrixC17_7, +matrixC17_8, +matrixC17_9, +matrixC17_10, +matrixC17_11, +matrixC17_12, +matrixC17_13, +matrixC17_14, +matrixC17_15, +matrixC17_16, +matrixC17_17, +matrixC17_18, +matrixC17_19, +matrixC17_20, +matrixC17_21, +matrixC17_22, +matrixC17_23, +matrixC17_24, +matrixC17_25, +matrixC17_26, +matrixC17_27, +matrixC17_28, +matrixC17_29, +matrixC17_30, +matrixC17_31, +matrixC18_0, +matrixC18_1, +matrixC18_2, +matrixC18_3, +matrixC18_4, +matrixC18_5, +matrixC18_6, +matrixC18_7, +matrixC18_8, +matrixC18_9, +matrixC18_10, +matrixC18_11, +matrixC18_12, +matrixC18_13, +matrixC18_14, +matrixC18_15, +matrixC18_16, +matrixC18_17, +matrixC18_18, +matrixC18_19, +matrixC18_20, +matrixC18_21, +matrixC18_22, +matrixC18_23, +matrixC18_24, +matrixC18_25, +matrixC18_26, +matrixC18_27, +matrixC18_28, +matrixC18_29, +matrixC18_30, +matrixC18_31, +matrixC19_0, +matrixC19_1, +matrixC19_2, +matrixC19_3, +matrixC19_4, +matrixC19_5, +matrixC19_6, +matrixC19_7, +matrixC19_8, +matrixC19_9, +matrixC19_10, +matrixC19_11, +matrixC19_12, +matrixC19_13, +matrixC19_14, +matrixC19_15, +matrixC19_16, +matrixC19_17, +matrixC19_18, +matrixC19_19, +matrixC19_20, +matrixC19_21, +matrixC19_22, +matrixC19_23, +matrixC19_24, +matrixC19_25, +matrixC19_26, +matrixC19_27, +matrixC19_28, +matrixC19_29, +matrixC19_30, +matrixC19_31, +matrixC20_0, +matrixC20_1, +matrixC20_2, +matrixC20_3, +matrixC20_4, +matrixC20_5, +matrixC20_6, +matrixC20_7, +matrixC20_8, +matrixC20_9, +matrixC20_10, +matrixC20_11, +matrixC20_12, +matrixC20_13, +matrixC20_14, +matrixC20_15, +matrixC20_16, +matrixC20_17, +matrixC20_18, +matrixC20_19, +matrixC20_20, +matrixC20_21, +matrixC20_22, +matrixC20_23, +matrixC20_24, +matrixC20_25, +matrixC20_26, +matrixC20_27, +matrixC20_28, +matrixC20_29, +matrixC20_30, +matrixC20_31, +matrixC21_0, +matrixC21_1, +matrixC21_2, +matrixC21_3, +matrixC21_4, +matrixC21_5, +matrixC21_6, +matrixC21_7, +matrixC21_8, +matrixC21_9, +matrixC21_10, +matrixC21_11, +matrixC21_12, +matrixC21_13, +matrixC21_14, +matrixC21_15, +matrixC21_16, +matrixC21_17, +matrixC21_18, +matrixC21_19, +matrixC21_20, +matrixC21_21, +matrixC21_22, +matrixC21_23, +matrixC21_24, +matrixC21_25, +matrixC21_26, +matrixC21_27, +matrixC21_28, +matrixC21_29, +matrixC21_30, +matrixC21_31, +matrixC22_0, +matrixC22_1, +matrixC22_2, +matrixC22_3, +matrixC22_4, +matrixC22_5, +matrixC22_6, +matrixC22_7, +matrixC22_8, +matrixC22_9, +matrixC22_10, +matrixC22_11, +matrixC22_12, +matrixC22_13, +matrixC22_14, +matrixC22_15, +matrixC22_16, +matrixC22_17, +matrixC22_18, +matrixC22_19, +matrixC22_20, +matrixC22_21, +matrixC22_22, +matrixC22_23, +matrixC22_24, +matrixC22_25, +matrixC22_26, +matrixC22_27, +matrixC22_28, +matrixC22_29, +matrixC22_30, +matrixC22_31, +matrixC23_0, +matrixC23_1, +matrixC23_2, +matrixC23_3, +matrixC23_4, +matrixC23_5, +matrixC23_6, +matrixC23_7, +matrixC23_8, +matrixC23_9, +matrixC23_10, +matrixC23_11, +matrixC23_12, +matrixC23_13, +matrixC23_14, +matrixC23_15, +matrixC23_16, +matrixC23_17, +matrixC23_18, +matrixC23_19, +matrixC23_20, +matrixC23_21, +matrixC23_22, +matrixC23_23, +matrixC23_24, +matrixC23_25, +matrixC23_26, +matrixC23_27, +matrixC23_28, +matrixC23_29, +matrixC23_30, +matrixC23_31, +matrixC24_0, +matrixC24_1, +matrixC24_2, +matrixC24_3, +matrixC24_4, +matrixC24_5, +matrixC24_6, +matrixC24_7, +matrixC24_8, +matrixC24_9, +matrixC24_10, +matrixC24_11, +matrixC24_12, +matrixC24_13, +matrixC24_14, +matrixC24_15, +matrixC24_16, +matrixC24_17, +matrixC24_18, +matrixC24_19, +matrixC24_20, +matrixC24_21, +matrixC24_22, +matrixC24_23, +matrixC24_24, +matrixC24_25, +matrixC24_26, +matrixC24_27, +matrixC24_28, +matrixC24_29, +matrixC24_30, +matrixC24_31, +matrixC25_0, +matrixC25_1, +matrixC25_2, +matrixC25_3, +matrixC25_4, +matrixC25_5, +matrixC25_6, +matrixC25_7, +matrixC25_8, +matrixC25_9, +matrixC25_10, +matrixC25_11, +matrixC25_12, +matrixC25_13, +matrixC25_14, +matrixC25_15, +matrixC25_16, +matrixC25_17, +matrixC25_18, +matrixC25_19, +matrixC25_20, +matrixC25_21, +matrixC25_22, +matrixC25_23, +matrixC25_24, +matrixC25_25, +matrixC25_26, +matrixC25_27, +matrixC25_28, +matrixC25_29, +matrixC25_30, +matrixC25_31, +matrixC26_0, +matrixC26_1, +matrixC26_2, +matrixC26_3, +matrixC26_4, +matrixC26_5, +matrixC26_6, +matrixC26_7, +matrixC26_8, +matrixC26_9, +matrixC26_10, +matrixC26_11, +matrixC26_12, +matrixC26_13, +matrixC26_14, +matrixC26_15, +matrixC26_16, +matrixC26_17, +matrixC26_18, +matrixC26_19, +matrixC26_20, +matrixC26_21, +matrixC26_22, +matrixC26_23, +matrixC26_24, +matrixC26_25, +matrixC26_26, +matrixC26_27, +matrixC26_28, +matrixC26_29, +matrixC26_30, +matrixC26_31, +matrixC27_0, +matrixC27_1, +matrixC27_2, +matrixC27_3, +matrixC27_4, +matrixC27_5, +matrixC27_6, +matrixC27_7, +matrixC27_8, +matrixC27_9, +matrixC27_10, +matrixC27_11, +matrixC27_12, +matrixC27_13, +matrixC27_14, +matrixC27_15, +matrixC27_16, +matrixC27_17, +matrixC27_18, +matrixC27_19, +matrixC27_20, +matrixC27_21, +matrixC27_22, +matrixC27_23, +matrixC27_24, +matrixC27_25, +matrixC27_26, +matrixC27_27, +matrixC27_28, +matrixC27_29, +matrixC27_30, +matrixC27_31, +matrixC28_0, +matrixC28_1, +matrixC28_2, +matrixC28_3, +matrixC28_4, +matrixC28_5, +matrixC28_6, +matrixC28_7, +matrixC28_8, +matrixC28_9, +matrixC28_10, +matrixC28_11, +matrixC28_12, +matrixC28_13, +matrixC28_14, +matrixC28_15, +matrixC28_16, +matrixC28_17, +matrixC28_18, +matrixC28_19, +matrixC28_20, +matrixC28_21, +matrixC28_22, +matrixC28_23, +matrixC28_24, +matrixC28_25, +matrixC28_26, +matrixC28_27, +matrixC28_28, +matrixC28_29, +matrixC28_30, +matrixC28_31, +matrixC29_0, +matrixC29_1, +matrixC29_2, +matrixC29_3, +matrixC29_4, +matrixC29_5, +matrixC29_6, +matrixC29_7, +matrixC29_8, +matrixC29_9, +matrixC29_10, +matrixC29_11, +matrixC29_12, +matrixC29_13, +matrixC29_14, +matrixC29_15, +matrixC29_16, +matrixC29_17, +matrixC29_18, +matrixC29_19, +matrixC29_20, +matrixC29_21, +matrixC29_22, +matrixC29_23, +matrixC29_24, +matrixC29_25, +matrixC29_26, +matrixC29_27, +matrixC29_28, +matrixC29_29, +matrixC29_30, +matrixC29_31, +matrixC30_0, +matrixC30_1, +matrixC30_2, +matrixC30_3, +matrixC30_4, +matrixC30_5, +matrixC30_6, +matrixC30_7, +matrixC30_8, +matrixC30_9, +matrixC30_10, +matrixC30_11, +matrixC30_12, +matrixC30_13, +matrixC30_14, +matrixC30_15, +matrixC30_16, +matrixC30_17, +matrixC30_18, +matrixC30_19, +matrixC30_20, +matrixC30_21, +matrixC30_22, +matrixC30_23, +matrixC30_24, +matrixC30_25, +matrixC30_26, +matrixC30_27, +matrixC30_28, +matrixC30_29, +matrixC30_30, +matrixC30_31, +matrixC31_0, +matrixC31_1, +matrixC31_2, +matrixC31_3, +matrixC31_4, +matrixC31_5, +matrixC31_6, +matrixC31_7, +matrixC31_8, +matrixC31_9, +matrixC31_10, +matrixC31_11, +matrixC31_12, +matrixC31_13, +matrixC31_14, +matrixC31_15, +matrixC31_16, +matrixC31_17, +matrixC31_18, +matrixC31_19, +matrixC31_20, +matrixC31_21, +matrixC31_22, +matrixC31_23, +matrixC31_24, +matrixC31_25, +matrixC31_26, +matrixC31_27, +matrixC31_28, +matrixC31_29, +matrixC31_30, +matrixC31_31, + +clk, +reset +); + +input clk; +input reset; +input start_mat_mul; +input done_mat_mul; +input [`AWIDTH-1:0] address_mat_c; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; +output [`AWIDTH-1:0] c_addr; +output c_data_available; +input [7:0] clk_cnt; +output row_latch_en; + +input [7:0] final_mat_mul_size; +input [`DWIDTH-1:0] matrixC0_0; +input [`DWIDTH-1:0] matrixC0_1; +input [`DWIDTH-1:0] matrixC0_2; +input [`DWIDTH-1:0] matrixC0_3; +input [`DWIDTH-1:0] matrixC0_4; +input [`DWIDTH-1:0] matrixC0_5; +input [`DWIDTH-1:0] matrixC0_6; +input [`DWIDTH-1:0] matrixC0_7; +input [`DWIDTH-1:0] matrixC0_8; +input [`DWIDTH-1:0] matrixC0_9; +input [`DWIDTH-1:0] matrixC0_10; +input [`DWIDTH-1:0] matrixC0_11; +input [`DWIDTH-1:0] matrixC0_12; +input [`DWIDTH-1:0] matrixC0_13; +input [`DWIDTH-1:0] matrixC0_14; +input [`DWIDTH-1:0] matrixC0_15; +input [`DWIDTH-1:0] matrixC0_16; +input [`DWIDTH-1:0] matrixC0_17; +input [`DWIDTH-1:0] matrixC0_18; +input [`DWIDTH-1:0] matrixC0_19; +input [`DWIDTH-1:0] matrixC0_20; +input [`DWIDTH-1:0] matrixC0_21; +input [`DWIDTH-1:0] matrixC0_22; +input [`DWIDTH-1:0] matrixC0_23; +input [`DWIDTH-1:0] matrixC0_24; +input [`DWIDTH-1:0] matrixC0_25; +input [`DWIDTH-1:0] matrixC0_26; +input [`DWIDTH-1:0] matrixC0_27; +input [`DWIDTH-1:0] matrixC0_28; +input [`DWIDTH-1:0] matrixC0_29; +input [`DWIDTH-1:0] matrixC0_30; +input [`DWIDTH-1:0] matrixC0_31; +input [`DWIDTH-1:0] matrixC1_0; +input [`DWIDTH-1:0] matrixC1_1; +input [`DWIDTH-1:0] matrixC1_2; +input [`DWIDTH-1:0] matrixC1_3; +input [`DWIDTH-1:0] matrixC1_4; +input [`DWIDTH-1:0] matrixC1_5; +input [`DWIDTH-1:0] matrixC1_6; +input [`DWIDTH-1:0] matrixC1_7; +input [`DWIDTH-1:0] matrixC1_8; +input [`DWIDTH-1:0] matrixC1_9; +input [`DWIDTH-1:0] matrixC1_10; +input [`DWIDTH-1:0] matrixC1_11; +input [`DWIDTH-1:0] matrixC1_12; +input [`DWIDTH-1:0] matrixC1_13; +input [`DWIDTH-1:0] matrixC1_14; +input [`DWIDTH-1:0] matrixC1_15; +input [`DWIDTH-1:0] matrixC1_16; +input [`DWIDTH-1:0] matrixC1_17; +input [`DWIDTH-1:0] matrixC1_18; +input [`DWIDTH-1:0] matrixC1_19; +input [`DWIDTH-1:0] matrixC1_20; +input [`DWIDTH-1:0] matrixC1_21; +input [`DWIDTH-1:0] matrixC1_22; +input [`DWIDTH-1:0] matrixC1_23; +input [`DWIDTH-1:0] matrixC1_24; +input [`DWIDTH-1:0] matrixC1_25; +input [`DWIDTH-1:0] matrixC1_26; +input [`DWIDTH-1:0] matrixC1_27; +input [`DWIDTH-1:0] matrixC1_28; +input [`DWIDTH-1:0] matrixC1_29; +input [`DWIDTH-1:0] matrixC1_30; +input [`DWIDTH-1:0] matrixC1_31; +input [`DWIDTH-1:0] matrixC2_0; +input [`DWIDTH-1:0] matrixC2_1; +input [`DWIDTH-1:0] matrixC2_2; +input [`DWIDTH-1:0] matrixC2_3; +input [`DWIDTH-1:0] matrixC2_4; +input [`DWIDTH-1:0] matrixC2_5; +input [`DWIDTH-1:0] matrixC2_6; +input [`DWIDTH-1:0] matrixC2_7; +input [`DWIDTH-1:0] matrixC2_8; +input [`DWIDTH-1:0] matrixC2_9; +input [`DWIDTH-1:0] matrixC2_10; +input [`DWIDTH-1:0] matrixC2_11; +input [`DWIDTH-1:0] matrixC2_12; +input [`DWIDTH-1:0] matrixC2_13; +input [`DWIDTH-1:0] matrixC2_14; +input [`DWIDTH-1:0] matrixC2_15; +input [`DWIDTH-1:0] matrixC2_16; +input [`DWIDTH-1:0] matrixC2_17; +input [`DWIDTH-1:0] matrixC2_18; +input [`DWIDTH-1:0] matrixC2_19; +input [`DWIDTH-1:0] matrixC2_20; +input [`DWIDTH-1:0] matrixC2_21; +input [`DWIDTH-1:0] matrixC2_22; +input [`DWIDTH-1:0] matrixC2_23; +input [`DWIDTH-1:0] matrixC2_24; +input [`DWIDTH-1:0] matrixC2_25; +input [`DWIDTH-1:0] matrixC2_26; +input [`DWIDTH-1:0] matrixC2_27; +input [`DWIDTH-1:0] matrixC2_28; +input [`DWIDTH-1:0] matrixC2_29; +input [`DWIDTH-1:0] matrixC2_30; +input [`DWIDTH-1:0] matrixC2_31; +input [`DWIDTH-1:0] matrixC3_0; +input [`DWIDTH-1:0] matrixC3_1; +input [`DWIDTH-1:0] matrixC3_2; +input [`DWIDTH-1:0] matrixC3_3; +input [`DWIDTH-1:0] matrixC3_4; +input [`DWIDTH-1:0] matrixC3_5; +input [`DWIDTH-1:0] matrixC3_6; +input [`DWIDTH-1:0] matrixC3_7; +input [`DWIDTH-1:0] matrixC3_8; +input [`DWIDTH-1:0] matrixC3_9; +input [`DWIDTH-1:0] matrixC3_10; +input [`DWIDTH-1:0] matrixC3_11; +input [`DWIDTH-1:0] matrixC3_12; +input [`DWIDTH-1:0] matrixC3_13; +input [`DWIDTH-1:0] matrixC3_14; +input [`DWIDTH-1:0] matrixC3_15; +input [`DWIDTH-1:0] matrixC3_16; +input [`DWIDTH-1:0] matrixC3_17; +input [`DWIDTH-1:0] matrixC3_18; +input [`DWIDTH-1:0] matrixC3_19; +input [`DWIDTH-1:0] matrixC3_20; +input [`DWIDTH-1:0] matrixC3_21; +input [`DWIDTH-1:0] matrixC3_22; +input [`DWIDTH-1:0] matrixC3_23; +input [`DWIDTH-1:0] matrixC3_24; +input [`DWIDTH-1:0] matrixC3_25; +input [`DWIDTH-1:0] matrixC3_26; +input [`DWIDTH-1:0] matrixC3_27; +input [`DWIDTH-1:0] matrixC3_28; +input [`DWIDTH-1:0] matrixC3_29; +input [`DWIDTH-1:0] matrixC3_30; +input [`DWIDTH-1:0] matrixC3_31; +input [`DWIDTH-1:0] matrixC4_0; +input [`DWIDTH-1:0] matrixC4_1; +input [`DWIDTH-1:0] matrixC4_2; +input [`DWIDTH-1:0] matrixC4_3; +input [`DWIDTH-1:0] matrixC4_4; +input [`DWIDTH-1:0] matrixC4_5; +input [`DWIDTH-1:0] matrixC4_6; +input [`DWIDTH-1:0] matrixC4_7; +input [`DWIDTH-1:0] matrixC4_8; +input [`DWIDTH-1:0] matrixC4_9; +input [`DWIDTH-1:0] matrixC4_10; +input [`DWIDTH-1:0] matrixC4_11; +input [`DWIDTH-1:0] matrixC4_12; +input [`DWIDTH-1:0] matrixC4_13; +input [`DWIDTH-1:0] matrixC4_14; +input [`DWIDTH-1:0] matrixC4_15; +input [`DWIDTH-1:0] matrixC4_16; +input [`DWIDTH-1:0] matrixC4_17; +input [`DWIDTH-1:0] matrixC4_18; +input [`DWIDTH-1:0] matrixC4_19; +input [`DWIDTH-1:0] matrixC4_20; +input [`DWIDTH-1:0] matrixC4_21; +input [`DWIDTH-1:0] matrixC4_22; +input [`DWIDTH-1:0] matrixC4_23; +input [`DWIDTH-1:0] matrixC4_24; +input [`DWIDTH-1:0] matrixC4_25; +input [`DWIDTH-1:0] matrixC4_26; +input [`DWIDTH-1:0] matrixC4_27; +input [`DWIDTH-1:0] matrixC4_28; +input [`DWIDTH-1:0] matrixC4_29; +input [`DWIDTH-1:0] matrixC4_30; +input [`DWIDTH-1:0] matrixC4_31; +input [`DWIDTH-1:0] matrixC5_0; +input [`DWIDTH-1:0] matrixC5_1; +input [`DWIDTH-1:0] matrixC5_2; +input [`DWIDTH-1:0] matrixC5_3; +input [`DWIDTH-1:0] matrixC5_4; +input [`DWIDTH-1:0] matrixC5_5; +input [`DWIDTH-1:0] matrixC5_6; +input [`DWIDTH-1:0] matrixC5_7; +input [`DWIDTH-1:0] matrixC5_8; +input [`DWIDTH-1:0] matrixC5_9; +input [`DWIDTH-1:0] matrixC5_10; +input [`DWIDTH-1:0] matrixC5_11; +input [`DWIDTH-1:0] matrixC5_12; +input [`DWIDTH-1:0] matrixC5_13; +input [`DWIDTH-1:0] matrixC5_14; +input [`DWIDTH-1:0] matrixC5_15; +input [`DWIDTH-1:0] matrixC5_16; +input [`DWIDTH-1:0] matrixC5_17; +input [`DWIDTH-1:0] matrixC5_18; +input [`DWIDTH-1:0] matrixC5_19; +input [`DWIDTH-1:0] matrixC5_20; +input [`DWIDTH-1:0] matrixC5_21; +input [`DWIDTH-1:0] matrixC5_22; +input [`DWIDTH-1:0] matrixC5_23; +input [`DWIDTH-1:0] matrixC5_24; +input [`DWIDTH-1:0] matrixC5_25; +input [`DWIDTH-1:0] matrixC5_26; +input [`DWIDTH-1:0] matrixC5_27; +input [`DWIDTH-1:0] matrixC5_28; +input [`DWIDTH-1:0] matrixC5_29; +input [`DWIDTH-1:0] matrixC5_30; +input [`DWIDTH-1:0] matrixC5_31; +input [`DWIDTH-1:0] matrixC6_0; +input [`DWIDTH-1:0] matrixC6_1; +input [`DWIDTH-1:0] matrixC6_2; +input [`DWIDTH-1:0] matrixC6_3; +input [`DWIDTH-1:0] matrixC6_4; +input [`DWIDTH-1:0] matrixC6_5; +input [`DWIDTH-1:0] matrixC6_6; +input [`DWIDTH-1:0] matrixC6_7; +input [`DWIDTH-1:0] matrixC6_8; +input [`DWIDTH-1:0] matrixC6_9; +input [`DWIDTH-1:0] matrixC6_10; +input [`DWIDTH-1:0] matrixC6_11; +input [`DWIDTH-1:0] matrixC6_12; +input [`DWIDTH-1:0] matrixC6_13; +input [`DWIDTH-1:0] matrixC6_14; +input [`DWIDTH-1:0] matrixC6_15; +input [`DWIDTH-1:0] matrixC6_16; +input [`DWIDTH-1:0] matrixC6_17; +input [`DWIDTH-1:0] matrixC6_18; +input [`DWIDTH-1:0] matrixC6_19; +input [`DWIDTH-1:0] matrixC6_20; +input [`DWIDTH-1:0] matrixC6_21; +input [`DWIDTH-1:0] matrixC6_22; +input [`DWIDTH-1:0] matrixC6_23; +input [`DWIDTH-1:0] matrixC6_24; +input [`DWIDTH-1:0] matrixC6_25; +input [`DWIDTH-1:0] matrixC6_26; +input [`DWIDTH-1:0] matrixC6_27; +input [`DWIDTH-1:0] matrixC6_28; +input [`DWIDTH-1:0] matrixC6_29; +input [`DWIDTH-1:0] matrixC6_30; +input [`DWIDTH-1:0] matrixC6_31; +input [`DWIDTH-1:0] matrixC7_0; +input [`DWIDTH-1:0] matrixC7_1; +input [`DWIDTH-1:0] matrixC7_2; +input [`DWIDTH-1:0] matrixC7_3; +input [`DWIDTH-1:0] matrixC7_4; +input [`DWIDTH-1:0] matrixC7_5; +input [`DWIDTH-1:0] matrixC7_6; +input [`DWIDTH-1:0] matrixC7_7; +input [`DWIDTH-1:0] matrixC7_8; +input [`DWIDTH-1:0] matrixC7_9; +input [`DWIDTH-1:0] matrixC7_10; +input [`DWIDTH-1:0] matrixC7_11; +input [`DWIDTH-1:0] matrixC7_12; +input [`DWIDTH-1:0] matrixC7_13; +input [`DWIDTH-1:0] matrixC7_14; +input [`DWIDTH-1:0] matrixC7_15; +input [`DWIDTH-1:0] matrixC7_16; +input [`DWIDTH-1:0] matrixC7_17; +input [`DWIDTH-1:0] matrixC7_18; +input [`DWIDTH-1:0] matrixC7_19; +input [`DWIDTH-1:0] matrixC7_20; +input [`DWIDTH-1:0] matrixC7_21; +input [`DWIDTH-1:0] matrixC7_22; +input [`DWIDTH-1:0] matrixC7_23; +input [`DWIDTH-1:0] matrixC7_24; +input [`DWIDTH-1:0] matrixC7_25; +input [`DWIDTH-1:0] matrixC7_26; +input [`DWIDTH-1:0] matrixC7_27; +input [`DWIDTH-1:0] matrixC7_28; +input [`DWIDTH-1:0] matrixC7_29; +input [`DWIDTH-1:0] matrixC7_30; +input [`DWIDTH-1:0] matrixC7_31; +input [`DWIDTH-1:0] matrixC8_0; +input [`DWIDTH-1:0] matrixC8_1; +input [`DWIDTH-1:0] matrixC8_2; +input [`DWIDTH-1:0] matrixC8_3; +input [`DWIDTH-1:0] matrixC8_4; +input [`DWIDTH-1:0] matrixC8_5; +input [`DWIDTH-1:0] matrixC8_6; +input [`DWIDTH-1:0] matrixC8_7; +input [`DWIDTH-1:0] matrixC8_8; +input [`DWIDTH-1:0] matrixC8_9; +input [`DWIDTH-1:0] matrixC8_10; +input [`DWIDTH-1:0] matrixC8_11; +input [`DWIDTH-1:0] matrixC8_12; +input [`DWIDTH-1:0] matrixC8_13; +input [`DWIDTH-1:0] matrixC8_14; +input [`DWIDTH-1:0] matrixC8_15; +input [`DWIDTH-1:0] matrixC8_16; +input [`DWIDTH-1:0] matrixC8_17; +input [`DWIDTH-1:0] matrixC8_18; +input [`DWIDTH-1:0] matrixC8_19; +input [`DWIDTH-1:0] matrixC8_20; +input [`DWIDTH-1:0] matrixC8_21; +input [`DWIDTH-1:0] matrixC8_22; +input [`DWIDTH-1:0] matrixC8_23; +input [`DWIDTH-1:0] matrixC8_24; +input [`DWIDTH-1:0] matrixC8_25; +input [`DWIDTH-1:0] matrixC8_26; +input [`DWIDTH-1:0] matrixC8_27; +input [`DWIDTH-1:0] matrixC8_28; +input [`DWIDTH-1:0] matrixC8_29; +input [`DWIDTH-1:0] matrixC8_30; +input [`DWIDTH-1:0] matrixC8_31; +input [`DWIDTH-1:0] matrixC9_0; +input [`DWIDTH-1:0] matrixC9_1; +input [`DWIDTH-1:0] matrixC9_2; +input [`DWIDTH-1:0] matrixC9_3; +input [`DWIDTH-1:0] matrixC9_4; +input [`DWIDTH-1:0] matrixC9_5; +input [`DWIDTH-1:0] matrixC9_6; +input [`DWIDTH-1:0] matrixC9_7; +input [`DWIDTH-1:0] matrixC9_8; +input [`DWIDTH-1:0] matrixC9_9; +input [`DWIDTH-1:0] matrixC9_10; +input [`DWIDTH-1:0] matrixC9_11; +input [`DWIDTH-1:0] matrixC9_12; +input [`DWIDTH-1:0] matrixC9_13; +input [`DWIDTH-1:0] matrixC9_14; +input [`DWIDTH-1:0] matrixC9_15; +input [`DWIDTH-1:0] matrixC9_16; +input [`DWIDTH-1:0] matrixC9_17; +input [`DWIDTH-1:0] matrixC9_18; +input [`DWIDTH-1:0] matrixC9_19; +input [`DWIDTH-1:0] matrixC9_20; +input [`DWIDTH-1:0] matrixC9_21; +input [`DWIDTH-1:0] matrixC9_22; +input [`DWIDTH-1:0] matrixC9_23; +input [`DWIDTH-1:0] matrixC9_24; +input [`DWIDTH-1:0] matrixC9_25; +input [`DWIDTH-1:0] matrixC9_26; +input [`DWIDTH-1:0] matrixC9_27; +input [`DWIDTH-1:0] matrixC9_28; +input [`DWIDTH-1:0] matrixC9_29; +input [`DWIDTH-1:0] matrixC9_30; +input [`DWIDTH-1:0] matrixC9_31; +input [`DWIDTH-1:0] matrixC10_0; +input [`DWIDTH-1:0] matrixC10_1; +input [`DWIDTH-1:0] matrixC10_2; +input [`DWIDTH-1:0] matrixC10_3; +input [`DWIDTH-1:0] matrixC10_4; +input [`DWIDTH-1:0] matrixC10_5; +input [`DWIDTH-1:0] matrixC10_6; +input [`DWIDTH-1:0] matrixC10_7; +input [`DWIDTH-1:0] matrixC10_8; +input [`DWIDTH-1:0] matrixC10_9; +input [`DWIDTH-1:0] matrixC10_10; +input [`DWIDTH-1:0] matrixC10_11; +input [`DWIDTH-1:0] matrixC10_12; +input [`DWIDTH-1:0] matrixC10_13; +input [`DWIDTH-1:0] matrixC10_14; +input [`DWIDTH-1:0] matrixC10_15; +input [`DWIDTH-1:0] matrixC10_16; +input [`DWIDTH-1:0] matrixC10_17; +input [`DWIDTH-1:0] matrixC10_18; +input [`DWIDTH-1:0] matrixC10_19; +input [`DWIDTH-1:0] matrixC10_20; +input [`DWIDTH-1:0] matrixC10_21; +input [`DWIDTH-1:0] matrixC10_22; +input [`DWIDTH-1:0] matrixC10_23; +input [`DWIDTH-1:0] matrixC10_24; +input [`DWIDTH-1:0] matrixC10_25; +input [`DWIDTH-1:0] matrixC10_26; +input [`DWIDTH-1:0] matrixC10_27; +input [`DWIDTH-1:0] matrixC10_28; +input [`DWIDTH-1:0] matrixC10_29; +input [`DWIDTH-1:0] matrixC10_30; +input [`DWIDTH-1:0] matrixC10_31; +input [`DWIDTH-1:0] matrixC11_0; +input [`DWIDTH-1:0] matrixC11_1; +input [`DWIDTH-1:0] matrixC11_2; +input [`DWIDTH-1:0] matrixC11_3; +input [`DWIDTH-1:0] matrixC11_4; +input [`DWIDTH-1:0] matrixC11_5; +input [`DWIDTH-1:0] matrixC11_6; +input [`DWIDTH-1:0] matrixC11_7; +input [`DWIDTH-1:0] matrixC11_8; +input [`DWIDTH-1:0] matrixC11_9; +input [`DWIDTH-1:0] matrixC11_10; +input [`DWIDTH-1:0] matrixC11_11; +input [`DWIDTH-1:0] matrixC11_12; +input [`DWIDTH-1:0] matrixC11_13; +input [`DWIDTH-1:0] matrixC11_14; +input [`DWIDTH-1:0] matrixC11_15; +input [`DWIDTH-1:0] matrixC11_16; +input [`DWIDTH-1:0] matrixC11_17; +input [`DWIDTH-1:0] matrixC11_18; +input [`DWIDTH-1:0] matrixC11_19; +input [`DWIDTH-1:0] matrixC11_20; +input [`DWIDTH-1:0] matrixC11_21; +input [`DWIDTH-1:0] matrixC11_22; +input [`DWIDTH-1:0] matrixC11_23; +input [`DWIDTH-1:0] matrixC11_24; +input [`DWIDTH-1:0] matrixC11_25; +input [`DWIDTH-1:0] matrixC11_26; +input [`DWIDTH-1:0] matrixC11_27; +input [`DWIDTH-1:0] matrixC11_28; +input [`DWIDTH-1:0] matrixC11_29; +input [`DWIDTH-1:0] matrixC11_30; +input [`DWIDTH-1:0] matrixC11_31; +input [`DWIDTH-1:0] matrixC12_0; +input [`DWIDTH-1:0] matrixC12_1; +input [`DWIDTH-1:0] matrixC12_2; +input [`DWIDTH-1:0] matrixC12_3; +input [`DWIDTH-1:0] matrixC12_4; +input [`DWIDTH-1:0] matrixC12_5; +input [`DWIDTH-1:0] matrixC12_6; +input [`DWIDTH-1:0] matrixC12_7; +input [`DWIDTH-1:0] matrixC12_8; +input [`DWIDTH-1:0] matrixC12_9; +input [`DWIDTH-1:0] matrixC12_10; +input [`DWIDTH-1:0] matrixC12_11; +input [`DWIDTH-1:0] matrixC12_12; +input [`DWIDTH-1:0] matrixC12_13; +input [`DWIDTH-1:0] matrixC12_14; +input [`DWIDTH-1:0] matrixC12_15; +input [`DWIDTH-1:0] matrixC12_16; +input [`DWIDTH-1:0] matrixC12_17; +input [`DWIDTH-1:0] matrixC12_18; +input [`DWIDTH-1:0] matrixC12_19; +input [`DWIDTH-1:0] matrixC12_20; +input [`DWIDTH-1:0] matrixC12_21; +input [`DWIDTH-1:0] matrixC12_22; +input [`DWIDTH-1:0] matrixC12_23; +input [`DWIDTH-1:0] matrixC12_24; +input [`DWIDTH-1:0] matrixC12_25; +input [`DWIDTH-1:0] matrixC12_26; +input [`DWIDTH-1:0] matrixC12_27; +input [`DWIDTH-1:0] matrixC12_28; +input [`DWIDTH-1:0] matrixC12_29; +input [`DWIDTH-1:0] matrixC12_30; +input [`DWIDTH-1:0] matrixC12_31; +input [`DWIDTH-1:0] matrixC13_0; +input [`DWIDTH-1:0] matrixC13_1; +input [`DWIDTH-1:0] matrixC13_2; +input [`DWIDTH-1:0] matrixC13_3; +input [`DWIDTH-1:0] matrixC13_4; +input [`DWIDTH-1:0] matrixC13_5; +input [`DWIDTH-1:0] matrixC13_6; +input [`DWIDTH-1:0] matrixC13_7; +input [`DWIDTH-1:0] matrixC13_8; +input [`DWIDTH-1:0] matrixC13_9; +input [`DWIDTH-1:0] matrixC13_10; +input [`DWIDTH-1:0] matrixC13_11; +input [`DWIDTH-1:0] matrixC13_12; +input [`DWIDTH-1:0] matrixC13_13; +input [`DWIDTH-1:0] matrixC13_14; +input [`DWIDTH-1:0] matrixC13_15; +input [`DWIDTH-1:0] matrixC13_16; +input [`DWIDTH-1:0] matrixC13_17; +input [`DWIDTH-1:0] matrixC13_18; +input [`DWIDTH-1:0] matrixC13_19; +input [`DWIDTH-1:0] matrixC13_20; +input [`DWIDTH-1:0] matrixC13_21; +input [`DWIDTH-1:0] matrixC13_22; +input [`DWIDTH-1:0] matrixC13_23; +input [`DWIDTH-1:0] matrixC13_24; +input [`DWIDTH-1:0] matrixC13_25; +input [`DWIDTH-1:0] matrixC13_26; +input [`DWIDTH-1:0] matrixC13_27; +input [`DWIDTH-1:0] matrixC13_28; +input [`DWIDTH-1:0] matrixC13_29; +input [`DWIDTH-1:0] matrixC13_30; +input [`DWIDTH-1:0] matrixC13_31; +input [`DWIDTH-1:0] matrixC14_0; +input [`DWIDTH-1:0] matrixC14_1; +input [`DWIDTH-1:0] matrixC14_2; +input [`DWIDTH-1:0] matrixC14_3; +input [`DWIDTH-1:0] matrixC14_4; +input [`DWIDTH-1:0] matrixC14_5; +input [`DWIDTH-1:0] matrixC14_6; +input [`DWIDTH-1:0] matrixC14_7; +input [`DWIDTH-1:0] matrixC14_8; +input [`DWIDTH-1:0] matrixC14_9; +input [`DWIDTH-1:0] matrixC14_10; +input [`DWIDTH-1:0] matrixC14_11; +input [`DWIDTH-1:0] matrixC14_12; +input [`DWIDTH-1:0] matrixC14_13; +input [`DWIDTH-1:0] matrixC14_14; +input [`DWIDTH-1:0] matrixC14_15; +input [`DWIDTH-1:0] matrixC14_16; +input [`DWIDTH-1:0] matrixC14_17; +input [`DWIDTH-1:0] matrixC14_18; +input [`DWIDTH-1:0] matrixC14_19; +input [`DWIDTH-1:0] matrixC14_20; +input [`DWIDTH-1:0] matrixC14_21; +input [`DWIDTH-1:0] matrixC14_22; +input [`DWIDTH-1:0] matrixC14_23; +input [`DWIDTH-1:0] matrixC14_24; +input [`DWIDTH-1:0] matrixC14_25; +input [`DWIDTH-1:0] matrixC14_26; +input [`DWIDTH-1:0] matrixC14_27; +input [`DWIDTH-1:0] matrixC14_28; +input [`DWIDTH-1:0] matrixC14_29; +input [`DWIDTH-1:0] matrixC14_30; +input [`DWIDTH-1:0] matrixC14_31; +input [`DWIDTH-1:0] matrixC15_0; +input [`DWIDTH-1:0] matrixC15_1; +input [`DWIDTH-1:0] matrixC15_2; +input [`DWIDTH-1:0] matrixC15_3; +input [`DWIDTH-1:0] matrixC15_4; +input [`DWIDTH-1:0] matrixC15_5; +input [`DWIDTH-1:0] matrixC15_6; +input [`DWIDTH-1:0] matrixC15_7; +input [`DWIDTH-1:0] matrixC15_8; +input [`DWIDTH-1:0] matrixC15_9; +input [`DWIDTH-1:0] matrixC15_10; +input [`DWIDTH-1:0] matrixC15_11; +input [`DWIDTH-1:0] matrixC15_12; +input [`DWIDTH-1:0] matrixC15_13; +input [`DWIDTH-1:0] matrixC15_14; +input [`DWIDTH-1:0] matrixC15_15; +input [`DWIDTH-1:0] matrixC15_16; +input [`DWIDTH-1:0] matrixC15_17; +input [`DWIDTH-1:0] matrixC15_18; +input [`DWIDTH-1:0] matrixC15_19; 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+input [`DWIDTH-1:0] matrixC26_12; +input [`DWIDTH-1:0] matrixC26_13; +input [`DWIDTH-1:0] matrixC26_14; +input [`DWIDTH-1:0] matrixC26_15; +input [`DWIDTH-1:0] matrixC26_16; +input [`DWIDTH-1:0] matrixC26_17; +input [`DWIDTH-1:0] matrixC26_18; +input [`DWIDTH-1:0] matrixC26_19; +input [`DWIDTH-1:0] matrixC26_20; +input [`DWIDTH-1:0] matrixC26_21; +input [`DWIDTH-1:0] matrixC26_22; +input [`DWIDTH-1:0] matrixC26_23; +input [`DWIDTH-1:0] matrixC26_24; +input [`DWIDTH-1:0] matrixC26_25; +input [`DWIDTH-1:0] matrixC26_26; +input [`DWIDTH-1:0] matrixC26_27; +input [`DWIDTH-1:0] matrixC26_28; +input [`DWIDTH-1:0] matrixC26_29; +input [`DWIDTH-1:0] matrixC26_30; +input [`DWIDTH-1:0] matrixC26_31; +input [`DWIDTH-1:0] matrixC27_0; +input [`DWIDTH-1:0] matrixC27_1; +input [`DWIDTH-1:0] matrixC27_2; +input [`DWIDTH-1:0] matrixC27_3; +input [`DWIDTH-1:0] matrixC27_4; +input [`DWIDTH-1:0] matrixC27_5; +input [`DWIDTH-1:0] matrixC27_6; +input [`DWIDTH-1:0] matrixC27_7; +input [`DWIDTH-1:0] matrixC27_8; +input [`DWIDTH-1:0] matrixC27_9; +input [`DWIDTH-1:0] matrixC27_10; +input [`DWIDTH-1:0] matrixC27_11; +input [`DWIDTH-1:0] matrixC27_12; +input [`DWIDTH-1:0] matrixC27_13; +input [`DWIDTH-1:0] matrixC27_14; +input [`DWIDTH-1:0] matrixC27_15; +input [`DWIDTH-1:0] matrixC27_16; +input [`DWIDTH-1:0] matrixC27_17; +input [`DWIDTH-1:0] matrixC27_18; +input [`DWIDTH-1:0] matrixC27_19; +input [`DWIDTH-1:0] matrixC27_20; +input [`DWIDTH-1:0] matrixC27_21; +input [`DWIDTH-1:0] matrixC27_22; +input [`DWIDTH-1:0] matrixC27_23; +input [`DWIDTH-1:0] matrixC27_24; +input [`DWIDTH-1:0] matrixC27_25; +input [`DWIDTH-1:0] matrixC27_26; +input [`DWIDTH-1:0] matrixC27_27; +input [`DWIDTH-1:0] matrixC27_28; +input [`DWIDTH-1:0] matrixC27_29; +input [`DWIDTH-1:0] matrixC27_30; +input [`DWIDTH-1:0] matrixC27_31; +input [`DWIDTH-1:0] matrixC28_0; +input [`DWIDTH-1:0] matrixC28_1; +input [`DWIDTH-1:0] matrixC28_2; +input [`DWIDTH-1:0] matrixC28_3; +input [`DWIDTH-1:0] matrixC28_4; +input [`DWIDTH-1:0] matrixC28_5; +input [`DWIDTH-1:0] matrixC28_6; +input [`DWIDTH-1:0] matrixC28_7; +input [`DWIDTH-1:0] matrixC28_8; +input [`DWIDTH-1:0] matrixC28_9; +input [`DWIDTH-1:0] matrixC28_10; +input [`DWIDTH-1:0] matrixC28_11; +input [`DWIDTH-1:0] matrixC28_12; +input [`DWIDTH-1:0] matrixC28_13; +input [`DWIDTH-1:0] matrixC28_14; +input [`DWIDTH-1:0] matrixC28_15; +input [`DWIDTH-1:0] matrixC28_16; +input [`DWIDTH-1:0] matrixC28_17; +input [`DWIDTH-1:0] matrixC28_18; +input [`DWIDTH-1:0] matrixC28_19; +input [`DWIDTH-1:0] matrixC28_20; +input [`DWIDTH-1:0] matrixC28_21; +input [`DWIDTH-1:0] matrixC28_22; +input [`DWIDTH-1:0] matrixC28_23; +input [`DWIDTH-1:0] matrixC28_24; +input [`DWIDTH-1:0] matrixC28_25; +input [`DWIDTH-1:0] matrixC28_26; +input [`DWIDTH-1:0] matrixC28_27; +input [`DWIDTH-1:0] matrixC28_28; +input [`DWIDTH-1:0] matrixC28_29; +input [`DWIDTH-1:0] matrixC28_30; +input [`DWIDTH-1:0] matrixC28_31; +input [`DWIDTH-1:0] matrixC29_0; +input [`DWIDTH-1:0] matrixC29_1; +input [`DWIDTH-1:0] matrixC29_2; +input [`DWIDTH-1:0] matrixC29_3; +input [`DWIDTH-1:0] matrixC29_4; +input [`DWIDTH-1:0] matrixC29_5; +input [`DWIDTH-1:0] matrixC29_6; +input [`DWIDTH-1:0] matrixC29_7; +input [`DWIDTH-1:0] matrixC29_8; +input [`DWIDTH-1:0] matrixC29_9; +input [`DWIDTH-1:0] matrixC29_10; +input [`DWIDTH-1:0] matrixC29_11; +input [`DWIDTH-1:0] matrixC29_12; +input [`DWIDTH-1:0] matrixC29_13; +input [`DWIDTH-1:0] matrixC29_14; +input [`DWIDTH-1:0] matrixC29_15; +input [`DWIDTH-1:0] matrixC29_16; +input [`DWIDTH-1:0] matrixC29_17; +input [`DWIDTH-1:0] matrixC29_18; +input [`DWIDTH-1:0] matrixC29_19; +input [`DWIDTH-1:0] matrixC29_20; +input [`DWIDTH-1:0] matrixC29_21; +input [`DWIDTH-1:0] matrixC29_22; +input [`DWIDTH-1:0] matrixC29_23; +input [`DWIDTH-1:0] matrixC29_24; +input [`DWIDTH-1:0] matrixC29_25; +input [`DWIDTH-1:0] matrixC29_26; +input [`DWIDTH-1:0] matrixC29_27; +input [`DWIDTH-1:0] matrixC29_28; +input [`DWIDTH-1:0] matrixC29_29; +input [`DWIDTH-1:0] matrixC29_30; +input [`DWIDTH-1:0] matrixC29_31; +input [`DWIDTH-1:0] matrixC30_0; +input [`DWIDTH-1:0] matrixC30_1; +input [`DWIDTH-1:0] matrixC30_2; +input [`DWIDTH-1:0] matrixC30_3; +input [`DWIDTH-1:0] matrixC30_4; +input [`DWIDTH-1:0] matrixC30_5; +input [`DWIDTH-1:0] matrixC30_6; +input [`DWIDTH-1:0] matrixC30_7; +input [`DWIDTH-1:0] matrixC30_8; +input [`DWIDTH-1:0] matrixC30_9; +input [`DWIDTH-1:0] matrixC30_10; +input [`DWIDTH-1:0] matrixC30_11; +input [`DWIDTH-1:0] matrixC30_12; +input [`DWIDTH-1:0] matrixC30_13; +input [`DWIDTH-1:0] matrixC30_14; +input [`DWIDTH-1:0] matrixC30_15; +input [`DWIDTH-1:0] matrixC30_16; +input [`DWIDTH-1:0] matrixC30_17; +input [`DWIDTH-1:0] matrixC30_18; +input [`DWIDTH-1:0] matrixC30_19; +input [`DWIDTH-1:0] matrixC30_20; +input [`DWIDTH-1:0] matrixC30_21; +input [`DWIDTH-1:0] matrixC30_22; +input [`DWIDTH-1:0] matrixC30_23; +input [`DWIDTH-1:0] matrixC30_24; +input [`DWIDTH-1:0] matrixC30_25; +input [`DWIDTH-1:0] matrixC30_26; +input [`DWIDTH-1:0] matrixC30_27; +input [`DWIDTH-1:0] matrixC30_28; +input [`DWIDTH-1:0] matrixC30_29; +input [`DWIDTH-1:0] matrixC30_30; +input [`DWIDTH-1:0] matrixC30_31; +input [`DWIDTH-1:0] matrixC31_0; +input [`DWIDTH-1:0] matrixC31_1; +input [`DWIDTH-1:0] matrixC31_2; +input [`DWIDTH-1:0] matrixC31_3; +input [`DWIDTH-1:0] matrixC31_4; +input [`DWIDTH-1:0] matrixC31_5; +input [`DWIDTH-1:0] matrixC31_6; +input [`DWIDTH-1:0] matrixC31_7; +input [`DWIDTH-1:0] matrixC31_8; +input [`DWIDTH-1:0] matrixC31_9; +input [`DWIDTH-1:0] matrixC31_10; +input [`DWIDTH-1:0] matrixC31_11; +input [`DWIDTH-1:0] matrixC31_12; +input [`DWIDTH-1:0] matrixC31_13; +input [`DWIDTH-1:0] matrixC31_14; +input [`DWIDTH-1:0] matrixC31_15; +input [`DWIDTH-1:0] matrixC31_16; +input [`DWIDTH-1:0] matrixC31_17; +input [`DWIDTH-1:0] matrixC31_18; +input [`DWIDTH-1:0] matrixC31_19; +input [`DWIDTH-1:0] matrixC31_20; +input [`DWIDTH-1:0] matrixC31_21; +input [`DWIDTH-1:0] matrixC31_22; +input [`DWIDTH-1:0] matrixC31_23; +input [`DWIDTH-1:0] matrixC31_24; +input [`DWIDTH-1:0] matrixC31_25; +input [`DWIDTH-1:0] matrixC31_26; +input [`DWIDTH-1:0] matrixC31_27; +input [`DWIDTH-1:0] matrixC31_28; +input [`DWIDTH-1:0] matrixC31_29; +input [`DWIDTH-1:0] matrixC31_30; +input [`DWIDTH-1:0] matrixC31_31; +wire row_latch_en; + + +////////////////////////////////////////////////////////////////////////// +// Logic to capture matrix C data from the PEs and shift it out +////////////////////////////////////////////////////////////////////////// +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + (a_loc+b_loc) * `BB_MAT_MUL_SIZE + 10 + `NUM_CYCLES_IN_MAC - 1)); +//Writing the line above to avoid multiplication: +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + ((a_loc+b_loc) << `LOG2_MAT_MUL_SIZE) + 10 + `NUM_CYCLES_IN_MAC - 1)); + +assign row_latch_en = + ((clk_cnt == ((`final_mat_mul_size<<2) - `final_mat_mul_size - 1 +`NUM_CYCLES_IN_MAC))); + +reg c_data_available; +reg [`AWIDTH-1:0] c_addr; +reg start_capturing_c_data; +reg [31:0] counter; +reg [32*`DWIDTH-1:0] c_data_out; +reg [32*`DWIDTH-1:0] c_data_out_1; +reg [32*`DWIDTH-1:0] c_data_out_2; +reg [32*`DWIDTH-1:0] c_data_out_3; +reg [32*`DWIDTH-1:0] c_data_out_4; +reg [32*`DWIDTH-1:0] c_data_out_5; +reg [32*`DWIDTH-1:0] c_data_out_6; +reg [32*`DWIDTH-1:0] c_data_out_7; +reg [32*`DWIDTH-1:0] c_data_out_8; +reg [32*`DWIDTH-1:0] c_data_out_9; +reg [32*`DWIDTH-1:0] c_data_out_10; +reg [32*`DWIDTH-1:0] c_data_out_11; +reg [32*`DWIDTH-1:0] c_data_out_12; +reg [32*`DWIDTH-1:0] c_data_out_13; +reg [32*`DWIDTH-1:0] c_data_out_14; +reg [32*`DWIDTH-1:0] c_data_out_15; +reg [32*`DWIDTH-1:0] c_data_out_16; +reg [32*`DWIDTH-1:0] c_data_out_17; +reg [32*`DWIDTH-1:0] c_data_out_18; +reg [32*`DWIDTH-1:0] c_data_out_19; +reg [32*`DWIDTH-1:0] c_data_out_20; +reg [32*`DWIDTH-1:0] c_data_out_21; +reg [32*`DWIDTH-1:0] c_data_out_22; +reg [32*`DWIDTH-1:0] c_data_out_23; +reg [32*`DWIDTH-1:0] c_data_out_24; +reg [32*`DWIDTH-1:0] c_data_out_25; +reg [32*`DWIDTH-1:0] c_data_out_26; +reg [32*`DWIDTH-1:0] c_data_out_27; +reg [32*`DWIDTH-1:0] c_data_out_28; +reg [32*`DWIDTH-1:0] c_data_out_29; +reg [32*`DWIDTH-1:0] c_data_out_30; +reg [32*`DWIDTH-1:0] c_data_out_31; +wire condition_to_start_shifting_output; +assign condition_to_start_shifting_output = + row_latch_en ; + + +//For larger matmuls, this logic will have more entries in the case statement +always @(posedge clk) begin + if (reset | ~start_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c + address_stride_c; + c_data_out <= 0; + counter <= 0; + + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + c_data_out_4 <= 0; + c_data_out_5 <= 0; + c_data_out_6 <= 0; + c_data_out_7 <= 0; + c_data_out_8 <= 0; + c_data_out_9 <= 0; + c_data_out_10 <= 0; + c_data_out_11 <= 0; + c_data_out_12 <= 0; + c_data_out_13 <= 0; + c_data_out_14 <= 0; + c_data_out_15 <= 0; + c_data_out_16 <= 0; + c_data_out_17 <= 0; + c_data_out_18 <= 0; + c_data_out_19 <= 0; + c_data_out_20 <= 0; + c_data_out_21 <= 0; + c_data_out_22 <= 0; + c_data_out_23 <= 0; + c_data_out_24 <= 0; + c_data_out_25 <= 0; + c_data_out_26 <= 0; + c_data_out_27 <= 0; + c_data_out_28 <= 0; + c_data_out_29 <= 0; + c_data_out_30 <= 0; + c_data_out_31 <= 0; + end else if (condition_to_start_shifting_output) begin + start_capturing_c_data <= 1'b1; + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + c_data_out <= {matrixC31_31, matrixC30_31, matrixC29_31, matrixC28_31, matrixC27_31, matrixC26_31, matrixC25_31, matrixC24_31, matrixC23_31, matrixC22_31, matrixC21_31, matrixC20_31, matrixC19_31, matrixC18_31, matrixC17_31, matrixC16_31, matrixC15_31, matrixC14_31, matrixC13_31, matrixC12_31, matrixC11_31, matrixC10_31, matrixC9_31, matrixC8_31, matrixC7_31, matrixC6_31, matrixC5_31, matrixC4_31, matrixC3_31, matrixC2_31, matrixC1_31, matrixC0_31}; + c_data_out_1 <= {matrixC31_30, matrixC30_30, matrixC29_30, matrixC28_30, matrixC27_30, matrixC26_30, matrixC25_30, matrixC24_30, matrixC23_30, matrixC22_30, matrixC21_30, matrixC20_30, matrixC19_30, matrixC18_30, matrixC17_30, matrixC16_30, matrixC15_30, matrixC14_30, matrixC13_30, matrixC12_30, matrixC11_30, matrixC10_30, matrixC9_30, matrixC8_30, matrixC7_30, matrixC6_30, matrixC5_30, matrixC4_30, matrixC3_30, matrixC2_30, matrixC1_30, matrixC0_30}; + c_data_out_2 <= {matrixC31_29, matrixC30_29, matrixC29_29, matrixC28_29, matrixC27_29, matrixC26_29, matrixC25_29, matrixC24_29, matrixC23_29, matrixC22_29, matrixC21_29, matrixC20_29, matrixC19_29, matrixC18_29, matrixC17_29, matrixC16_29, matrixC15_29, matrixC14_29, matrixC13_29, matrixC12_29, matrixC11_29, matrixC10_29, matrixC9_29, matrixC8_29, matrixC7_29, matrixC6_29, matrixC5_29, matrixC4_29, matrixC3_29, matrixC2_29, matrixC1_29, matrixC0_29}; + c_data_out_3 <= {matrixC31_28, matrixC30_28, matrixC29_28, matrixC28_28, matrixC27_28, matrixC26_28, matrixC25_28, matrixC24_28, matrixC23_28, matrixC22_28, matrixC21_28, matrixC20_28, matrixC19_28, matrixC18_28, matrixC17_28, matrixC16_28, matrixC15_28, matrixC14_28, matrixC13_28, matrixC12_28, matrixC11_28, matrixC10_28, matrixC9_28, matrixC8_28, matrixC7_28, matrixC6_28, matrixC5_28, matrixC4_28, matrixC3_28, matrixC2_28, matrixC1_28, matrixC0_28}; + c_data_out_4 <= {matrixC31_27, matrixC30_27, matrixC29_27, matrixC28_27, matrixC27_27, matrixC26_27, matrixC25_27, matrixC24_27, matrixC23_27, matrixC22_27, matrixC21_27, matrixC20_27, matrixC19_27, matrixC18_27, matrixC17_27, matrixC16_27, matrixC15_27, matrixC14_27, matrixC13_27, matrixC12_27, matrixC11_27, matrixC10_27, matrixC9_27, matrixC8_27, matrixC7_27, matrixC6_27, matrixC5_27, matrixC4_27, matrixC3_27, matrixC2_27, matrixC1_27, matrixC0_27}; + c_data_out_5 <= {matrixC31_26, matrixC30_26, matrixC29_26, matrixC28_26, matrixC27_26, matrixC26_26, matrixC25_26, matrixC24_26, matrixC23_26, matrixC22_26, matrixC21_26, matrixC20_26, matrixC19_26, matrixC18_26, matrixC17_26, matrixC16_26, matrixC15_26, matrixC14_26, matrixC13_26, matrixC12_26, matrixC11_26, matrixC10_26, matrixC9_26, matrixC8_26, matrixC7_26, matrixC6_26, matrixC5_26, matrixC4_26, matrixC3_26, matrixC2_26, matrixC1_26, matrixC0_26}; + c_data_out_6 <= {matrixC31_25, matrixC30_25, matrixC29_25, matrixC28_25, matrixC27_25, matrixC26_25, matrixC25_25, matrixC24_25, matrixC23_25, matrixC22_25, matrixC21_25, matrixC20_25, matrixC19_25, matrixC18_25, matrixC17_25, matrixC16_25, matrixC15_25, matrixC14_25, matrixC13_25, matrixC12_25, matrixC11_25, matrixC10_25, matrixC9_25, matrixC8_25, matrixC7_25, matrixC6_25, matrixC5_25, matrixC4_25, matrixC3_25, matrixC2_25, matrixC1_25, matrixC0_25}; + c_data_out_7 <= {matrixC31_24, matrixC30_24, matrixC29_24, matrixC28_24, matrixC27_24, matrixC26_24, matrixC25_24, matrixC24_24, matrixC23_24, matrixC22_24, matrixC21_24, matrixC20_24, matrixC19_24, matrixC18_24, matrixC17_24, matrixC16_24, matrixC15_24, matrixC14_24, matrixC13_24, matrixC12_24, matrixC11_24, matrixC10_24, matrixC9_24, matrixC8_24, matrixC7_24, matrixC6_24, matrixC5_24, matrixC4_24, matrixC3_24, matrixC2_24, matrixC1_24, matrixC0_24}; + c_data_out_8 <= {matrixC31_23, matrixC30_23, matrixC29_23, matrixC28_23, matrixC27_23, matrixC26_23, matrixC25_23, matrixC24_23, matrixC23_23, matrixC22_23, matrixC21_23, matrixC20_23, matrixC19_23, matrixC18_23, matrixC17_23, matrixC16_23, matrixC15_23, matrixC14_23, matrixC13_23, matrixC12_23, matrixC11_23, matrixC10_23, matrixC9_23, matrixC8_23, matrixC7_23, matrixC6_23, matrixC5_23, matrixC4_23, matrixC3_23, matrixC2_23, matrixC1_23, matrixC0_23}; + c_data_out_9 <= {matrixC31_22, matrixC30_22, matrixC29_22, matrixC28_22, matrixC27_22, matrixC26_22, matrixC25_22, matrixC24_22, matrixC23_22, matrixC22_22, matrixC21_22, matrixC20_22, matrixC19_22, matrixC18_22, matrixC17_22, matrixC16_22, matrixC15_22, matrixC14_22, matrixC13_22, matrixC12_22, matrixC11_22, matrixC10_22, matrixC9_22, matrixC8_22, matrixC7_22, matrixC6_22, matrixC5_22, matrixC4_22, matrixC3_22, matrixC2_22, matrixC1_22, matrixC0_22}; + c_data_out_10 <= {matrixC31_21, matrixC30_21, matrixC29_21, matrixC28_21, matrixC27_21, matrixC26_21, matrixC25_21, matrixC24_21, matrixC23_21, matrixC22_21, matrixC21_21, matrixC20_21, matrixC19_21, matrixC18_21, matrixC17_21, matrixC16_21, matrixC15_21, matrixC14_21, matrixC13_21, matrixC12_21, matrixC11_21, matrixC10_21, matrixC9_21, matrixC8_21, matrixC7_21, matrixC6_21, matrixC5_21, matrixC4_21, matrixC3_21, matrixC2_21, matrixC1_21, matrixC0_21}; + c_data_out_11 <= {matrixC31_20, matrixC30_20, matrixC29_20, matrixC28_20, matrixC27_20, matrixC26_20, matrixC25_20, matrixC24_20, matrixC23_20, matrixC22_20, matrixC21_20, matrixC20_20, matrixC19_20, matrixC18_20, matrixC17_20, matrixC16_20, matrixC15_20, matrixC14_20, matrixC13_20, matrixC12_20, matrixC11_20, matrixC10_20, matrixC9_20, matrixC8_20, matrixC7_20, matrixC6_20, matrixC5_20, matrixC4_20, matrixC3_20, matrixC2_20, matrixC1_20, matrixC0_20}; + c_data_out_12 <= {matrixC31_19, matrixC30_19, matrixC29_19, matrixC28_19, matrixC27_19, matrixC26_19, matrixC25_19, matrixC24_19, matrixC23_19, matrixC22_19, matrixC21_19, matrixC20_19, matrixC19_19, matrixC18_19, matrixC17_19, matrixC16_19, matrixC15_19, matrixC14_19, matrixC13_19, matrixC12_19, matrixC11_19, matrixC10_19, matrixC9_19, matrixC8_19, matrixC7_19, matrixC6_19, matrixC5_19, matrixC4_19, matrixC3_19, matrixC2_19, matrixC1_19, matrixC0_19}; + c_data_out_13 <= {matrixC31_18, matrixC30_18, matrixC29_18, matrixC28_18, matrixC27_18, matrixC26_18, matrixC25_18, matrixC24_18, matrixC23_18, matrixC22_18, matrixC21_18, matrixC20_18, matrixC19_18, matrixC18_18, matrixC17_18, matrixC16_18, matrixC15_18, matrixC14_18, matrixC13_18, matrixC12_18, matrixC11_18, matrixC10_18, matrixC9_18, matrixC8_18, matrixC7_18, matrixC6_18, matrixC5_18, matrixC4_18, matrixC3_18, matrixC2_18, matrixC1_18, matrixC0_18}; + c_data_out_14 <= {matrixC31_17, matrixC30_17, matrixC29_17, matrixC28_17, matrixC27_17, matrixC26_17, matrixC25_17, matrixC24_17, matrixC23_17, matrixC22_17, matrixC21_17, matrixC20_17, matrixC19_17, matrixC18_17, matrixC17_17, matrixC16_17, matrixC15_17, matrixC14_17, matrixC13_17, matrixC12_17, matrixC11_17, matrixC10_17, matrixC9_17, matrixC8_17, matrixC7_17, matrixC6_17, matrixC5_17, matrixC4_17, matrixC3_17, matrixC2_17, matrixC1_17, matrixC0_17}; + c_data_out_15 <= {matrixC31_16, matrixC30_16, matrixC29_16, matrixC28_16, matrixC27_16, matrixC26_16, matrixC25_16, matrixC24_16, matrixC23_16, matrixC22_16, matrixC21_16, matrixC20_16, matrixC19_16, matrixC18_16, matrixC17_16, matrixC16_16, matrixC15_16, matrixC14_16, matrixC13_16, matrixC12_16, matrixC11_16, matrixC10_16, matrixC9_16, matrixC8_16, matrixC7_16, matrixC6_16, matrixC5_16, matrixC4_16, matrixC3_16, matrixC2_16, matrixC1_16, matrixC0_16}; + c_data_out_16 <= {matrixC31_15, matrixC30_15, matrixC29_15, matrixC28_15, matrixC27_15, matrixC26_15, matrixC25_15, matrixC24_15, matrixC23_15, matrixC22_15, matrixC21_15, matrixC20_15, matrixC19_15, matrixC18_15, matrixC17_15, matrixC16_15, matrixC15_15, matrixC14_15, matrixC13_15, matrixC12_15, matrixC11_15, matrixC10_15, matrixC9_15, matrixC8_15, matrixC7_15, matrixC6_15, matrixC5_15, matrixC4_15, matrixC3_15, matrixC2_15, matrixC1_15, matrixC0_15}; + c_data_out_17 <= {matrixC31_14, matrixC30_14, matrixC29_14, matrixC28_14, matrixC27_14, matrixC26_14, matrixC25_14, matrixC24_14, matrixC23_14, matrixC22_14, matrixC21_14, matrixC20_14, matrixC19_14, matrixC18_14, matrixC17_14, matrixC16_14, matrixC15_14, matrixC14_14, matrixC13_14, matrixC12_14, matrixC11_14, matrixC10_14, matrixC9_14, matrixC8_14, matrixC7_14, matrixC6_14, matrixC5_14, matrixC4_14, matrixC3_14, matrixC2_14, matrixC1_14, matrixC0_14}; + c_data_out_18 <= {matrixC31_13, matrixC30_13, matrixC29_13, matrixC28_13, matrixC27_13, matrixC26_13, matrixC25_13, matrixC24_13, matrixC23_13, matrixC22_13, matrixC21_13, matrixC20_13, matrixC19_13, matrixC18_13, matrixC17_13, matrixC16_13, matrixC15_13, matrixC14_13, matrixC13_13, matrixC12_13, matrixC11_13, matrixC10_13, matrixC9_13, matrixC8_13, matrixC7_13, matrixC6_13, matrixC5_13, matrixC4_13, matrixC3_13, matrixC2_13, matrixC1_13, matrixC0_13}; + c_data_out_19 <= {matrixC31_12, matrixC30_12, matrixC29_12, matrixC28_12, matrixC27_12, matrixC26_12, matrixC25_12, matrixC24_12, matrixC23_12, matrixC22_12, matrixC21_12, matrixC20_12, matrixC19_12, matrixC18_12, matrixC17_12, matrixC16_12, matrixC15_12, matrixC14_12, matrixC13_12, matrixC12_12, matrixC11_12, matrixC10_12, matrixC9_12, matrixC8_12, matrixC7_12, matrixC6_12, matrixC5_12, matrixC4_12, matrixC3_12, matrixC2_12, matrixC1_12, matrixC0_12}; + c_data_out_20 <= {matrixC31_11, matrixC30_11, matrixC29_11, matrixC28_11, matrixC27_11, matrixC26_11, matrixC25_11, matrixC24_11, matrixC23_11, matrixC22_11, matrixC21_11, matrixC20_11, matrixC19_11, matrixC18_11, matrixC17_11, matrixC16_11, matrixC15_11, matrixC14_11, matrixC13_11, matrixC12_11, matrixC11_11, matrixC10_11, matrixC9_11, matrixC8_11, matrixC7_11, matrixC6_11, matrixC5_11, matrixC4_11, matrixC3_11, matrixC2_11, matrixC1_11, matrixC0_11}; + c_data_out_21 <= {matrixC31_10, matrixC30_10, matrixC29_10, matrixC28_10, matrixC27_10, matrixC26_10, matrixC25_10, matrixC24_10, matrixC23_10, matrixC22_10, matrixC21_10, matrixC20_10, matrixC19_10, matrixC18_10, matrixC17_10, matrixC16_10, matrixC15_10, matrixC14_10, matrixC13_10, matrixC12_10, matrixC11_10, matrixC10_10, matrixC9_10, matrixC8_10, matrixC7_10, matrixC6_10, matrixC5_10, matrixC4_10, matrixC3_10, matrixC2_10, matrixC1_10, matrixC0_10}; + c_data_out_22 <= {matrixC31_9, matrixC30_9, matrixC29_9, matrixC28_9, matrixC27_9, matrixC26_9, matrixC25_9, matrixC24_9, matrixC23_9, matrixC22_9, matrixC21_9, matrixC20_9, matrixC19_9, matrixC18_9, matrixC17_9, matrixC16_9, matrixC15_9, matrixC14_9, matrixC13_9, matrixC12_9, matrixC11_9, matrixC10_9, matrixC9_9, matrixC8_9, matrixC7_9, matrixC6_9, matrixC5_9, matrixC4_9, matrixC3_9, matrixC2_9, matrixC1_9, matrixC0_9}; + c_data_out_23 <= {matrixC31_8, matrixC30_8, matrixC29_8, matrixC28_8, matrixC27_8, matrixC26_8, matrixC25_8, matrixC24_8, matrixC23_8, matrixC22_8, matrixC21_8, matrixC20_8, matrixC19_8, matrixC18_8, matrixC17_8, matrixC16_8, matrixC15_8, matrixC14_8, matrixC13_8, matrixC12_8, matrixC11_8, matrixC10_8, matrixC9_8, matrixC8_8, matrixC7_8, matrixC6_8, matrixC5_8, matrixC4_8, matrixC3_8, matrixC2_8, matrixC1_8, matrixC0_8}; + c_data_out_24 <= {matrixC31_7, matrixC30_7, matrixC29_7, matrixC28_7, matrixC27_7, matrixC26_7, matrixC25_7, matrixC24_7, matrixC23_7, matrixC22_7, matrixC21_7, matrixC20_7, matrixC19_7, matrixC18_7, matrixC17_7, matrixC16_7, matrixC15_7, matrixC14_7, matrixC13_7, matrixC12_7, matrixC11_7, matrixC10_7, matrixC9_7, matrixC8_7, matrixC7_7, matrixC6_7, matrixC5_7, matrixC4_7, matrixC3_7, matrixC2_7, matrixC1_7, matrixC0_7}; + c_data_out_25 <= {matrixC31_6, matrixC30_6, matrixC29_6, matrixC28_6, matrixC27_6, matrixC26_6, matrixC25_6, matrixC24_6, matrixC23_6, matrixC22_6, matrixC21_6, matrixC20_6, matrixC19_6, matrixC18_6, matrixC17_6, matrixC16_6, matrixC15_6, matrixC14_6, matrixC13_6, matrixC12_6, matrixC11_6, matrixC10_6, matrixC9_6, matrixC8_6, matrixC7_6, matrixC6_6, matrixC5_6, matrixC4_6, matrixC3_6, matrixC2_6, matrixC1_6, matrixC0_6}; + c_data_out_26 <= {matrixC31_5, matrixC30_5, matrixC29_5, matrixC28_5, matrixC27_5, matrixC26_5, matrixC25_5, matrixC24_5, matrixC23_5, matrixC22_5, matrixC21_5, matrixC20_5, matrixC19_5, matrixC18_5, matrixC17_5, matrixC16_5, matrixC15_5, matrixC14_5, matrixC13_5, matrixC12_5, matrixC11_5, matrixC10_5, matrixC9_5, matrixC8_5, matrixC7_5, matrixC6_5, matrixC5_5, matrixC4_5, matrixC3_5, matrixC2_5, matrixC1_5, matrixC0_5}; + c_data_out_27 <= {matrixC31_4, matrixC30_4, matrixC29_4, matrixC28_4, matrixC27_4, matrixC26_4, matrixC25_4, matrixC24_4, matrixC23_4, matrixC22_4, matrixC21_4, matrixC20_4, matrixC19_4, matrixC18_4, matrixC17_4, matrixC16_4, matrixC15_4, matrixC14_4, matrixC13_4, matrixC12_4, matrixC11_4, matrixC10_4, matrixC9_4, matrixC8_4, matrixC7_4, matrixC6_4, matrixC5_4, matrixC4_4, matrixC3_4, matrixC2_4, matrixC1_4, matrixC0_4}; + c_data_out_28 <= {matrixC31_3, matrixC30_3, matrixC29_3, matrixC28_3, matrixC27_3, matrixC26_3, matrixC25_3, matrixC24_3, matrixC23_3, matrixC22_3, matrixC21_3, matrixC20_3, matrixC19_3, matrixC18_3, matrixC17_3, matrixC16_3, matrixC15_3, matrixC14_3, matrixC13_3, matrixC12_3, matrixC11_3, matrixC10_3, matrixC9_3, matrixC8_3, matrixC7_3, matrixC6_3, matrixC5_3, matrixC4_3, matrixC3_3, matrixC2_3, matrixC1_3, matrixC0_3}; + c_data_out_29 <= {matrixC31_2, matrixC30_2, matrixC29_2, matrixC28_2, matrixC27_2, matrixC26_2, matrixC25_2, matrixC24_2, matrixC23_2, matrixC22_2, matrixC21_2, matrixC20_2, matrixC19_2, matrixC18_2, matrixC17_2, matrixC16_2, matrixC15_2, matrixC14_2, matrixC13_2, matrixC12_2, matrixC11_2, matrixC10_2, matrixC9_2, matrixC8_2, matrixC7_2, matrixC6_2, matrixC5_2, matrixC4_2, matrixC3_2, matrixC2_2, matrixC1_2, matrixC0_2}; + c_data_out_30 <= {matrixC31_1, matrixC30_1, matrixC29_1, matrixC28_1, matrixC27_1, matrixC26_1, matrixC25_1, matrixC24_1, matrixC23_1, matrixC22_1, matrixC21_1, matrixC20_1, matrixC19_1, matrixC18_1, matrixC17_1, matrixC16_1, matrixC15_1, matrixC14_1, matrixC13_1, matrixC12_1, matrixC11_1, matrixC10_1, matrixC9_1, matrixC8_1, matrixC7_1, matrixC6_1, matrixC5_1, matrixC4_1, matrixC3_1, matrixC2_1, matrixC1_1, matrixC0_1}; + c_data_out_31 <= {matrixC31_0, matrixC30_0, matrixC29_0, matrixC28_0, matrixC27_0, matrixC26_0, matrixC25_0, matrixC24_0, matrixC23_0, matrixC22_0, matrixC21_0, matrixC20_0, matrixC19_0, matrixC18_0, matrixC17_0, matrixC16_0, matrixC15_0, matrixC14_0, matrixC13_0, matrixC12_0, matrixC11_0, matrixC10_0, matrixC9_0, matrixC8_0, matrixC7_0, matrixC6_0, matrixC5_0, matrixC4_0, matrixC3_0, matrixC2_0, matrixC1_0, matrixC0_0}; + + counter <= counter + 1; + end else if (done_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c + address_stride_c; + c_data_out <= 0; + + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + c_data_out_4 <= 0; + c_data_out_5 <= 0; + c_data_out_6 <= 0; + c_data_out_7 <= 0; + c_data_out_8 <= 0; + c_data_out_9 <= 0; + c_data_out_10 <= 0; + c_data_out_11 <= 0; + c_data_out_12 <= 0; + c_data_out_13 <= 0; + c_data_out_14 <= 0; + c_data_out_15 <= 0; + c_data_out_16 <= 0; + c_data_out_17 <= 0; + c_data_out_18 <= 0; + c_data_out_19 <= 0; + c_data_out_20 <= 0; + c_data_out_21 <= 0; + c_data_out_22 <= 0; + c_data_out_23 <= 0; + c_data_out_24 <= 0; + c_data_out_25 <= 0; + c_data_out_26 <= 0; + c_data_out_27 <= 0; + c_data_out_28 <= 0; + c_data_out_29 <= 0; + c_data_out_30 <= 0; + c_data_out_31 <= 0; + end + else if (counter >= `MAT_MUL_SIZE) begin + c_data_out <= c_data_out_1; + c_addr <= c_addr - address_stride_c; + + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_out_4; + c_data_out_4 <= c_data_out_5; + c_data_out_5 <= c_data_out_6; + c_data_out_6 <= c_data_out_7; + c_data_out_7 <= c_data_out_8; + c_data_out_8 <= c_data_out_9; + c_data_out_9 <= c_data_out_10; + c_data_out_10 <= c_data_out_11; + c_data_out_11 <= c_data_out_12; + c_data_out_12 <= c_data_out_13; + c_data_out_13 <= c_data_out_14; + c_data_out_14 <= c_data_out_15; + c_data_out_15 <= c_data_out_16; + c_data_out_16 <= c_data_out_17; + c_data_out_17 <= c_data_out_18; + c_data_out_18 <= c_data_out_19; + c_data_out_19 <= c_data_out_20; + c_data_out_20 <= c_data_out_21; + c_data_out_21 <= c_data_out_22; + c_data_out_22 <= c_data_out_23; + c_data_out_23 <= c_data_out_24; + c_data_out_24 <= c_data_out_25; + c_data_out_25 <= c_data_out_26; + c_data_out_26 <= c_data_out_27; + c_data_out_27 <= c_data_out_28; + c_data_out_28 <= c_data_out_29; + c_data_out_29 <= c_data_out_30; + c_data_out_30 <= c_data_out_31; + c_data_out_31 <= c_data_in; + end + else if (start_capturing_c_data) begin + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + counter <= counter + 1; + c_data_out <= c_data_out_1; + + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_out_4; + c_data_out_4 <= c_data_out_5; + c_data_out_5 <= c_data_out_6; + c_data_out_6 <= c_data_out_7; + c_data_out_7 <= c_data_out_8; + c_data_out_8 <= c_data_out_9; + c_data_out_9 <= c_data_out_10; + c_data_out_10 <= c_data_out_11; + c_data_out_11 <= c_data_out_12; + c_data_out_12 <= c_data_out_13; + c_data_out_13 <= c_data_out_14; + c_data_out_14 <= c_data_out_15; + c_data_out_15 <= c_data_out_16; + c_data_out_16 <= c_data_out_17; + c_data_out_17 <= c_data_out_18; + c_data_out_18 <= c_data_out_19; + c_data_out_19 <= c_data_out_20; + c_data_out_20 <= c_data_out_21; + c_data_out_21 <= c_data_out_22; + c_data_out_22 <= c_data_out_23; + c_data_out_23 <= c_data_out_24; + c_data_out_24 <= c_data_out_25; + c_data_out_25 <= c_data_out_26; + c_data_out_26 <= c_data_out_27; + c_data_out_27 <= c_data_out_28; + c_data_out_28 <= c_data_out_29; + c_data_out_29 <= c_data_out_30; + c_data_out_30 <= c_data_out_31; + c_data_out_31 <= c_data_in; + end +end + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolic data setup +////////////////////////////////////////////////////////////////////////// +module systolic_data_setup( +clk, +reset, +start_mat_mul, +a_addr, +b_addr, +address_mat_a, +address_mat_b, +address_stride_a, +address_stride_b, +a_data, +b_data, +clk_cnt, +a0_data, +b0_data, +a1_data_delayed_1, +b1_data_delayed_1, +a2_data_delayed_2, +b2_data_delayed_2, +a3_data_delayed_3, +b3_data_delayed_3, +a4_data_delayed_4, +b4_data_delayed_4, +a5_data_delayed_5, +b5_data_delayed_5, +a6_data_delayed_6, +b6_data_delayed_6, +a7_data_delayed_7, +b7_data_delayed_7, +a8_data_delayed_8, +b8_data_delayed_8, +a9_data_delayed_9, +b9_data_delayed_9, +a10_data_delayed_10, +b10_data_delayed_10, +a11_data_delayed_11, +b11_data_delayed_11, +a12_data_delayed_12, +b12_data_delayed_12, +a13_data_delayed_13, +b13_data_delayed_13, +a14_data_delayed_14, +b14_data_delayed_14, +a15_data_delayed_15, +b15_data_delayed_15, +a16_data_delayed_16, +b16_data_delayed_16, +a17_data_delayed_17, +b17_data_delayed_17, +a18_data_delayed_18, +b18_data_delayed_18, +a19_data_delayed_19, +b19_data_delayed_19, +a20_data_delayed_20, +b20_data_delayed_20, +a21_data_delayed_21, +b21_data_delayed_21, +a22_data_delayed_22, +b22_data_delayed_22, +a23_data_delayed_23, +b23_data_delayed_23, +a24_data_delayed_24, +b24_data_delayed_24, +a25_data_delayed_25, +b25_data_delayed_25, +a26_data_delayed_26, +b26_data_delayed_26, +a27_data_delayed_27, +b27_data_delayed_27, +a28_data_delayed_28, +b28_data_delayed_28, +a29_data_delayed_29, +b29_data_delayed_29, +a30_data_delayed_30, +b30_data_delayed_30, +a31_data_delayed_31, +b31_data_delayed_31, + +validity_mask_a_rows, +validity_mask_a_cols, +validity_mask_b_rows, +validity_mask_b_cols, + +final_mat_mul_size, + +a_loc, +b_loc +); + +input clk; +input reset; +input start_mat_mul; +output [`AWIDTH-1:0] a_addr; +output [`AWIDTH-1:0] b_addr; +input [`AWIDTH-1:0] address_mat_a; +input [`AWIDTH-1:0] address_mat_b; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; +input [7:0] clk_cnt; +output [`DWIDTH-1:0] a0_data; +output [`DWIDTH-1:0] b0_data; +output [`DWIDTH-1:0] a1_data_delayed_1; +output [`DWIDTH-1:0] b1_data_delayed_1; +output [`DWIDTH-1:0] a2_data_delayed_2; +output [`DWIDTH-1:0] b2_data_delayed_2; +output [`DWIDTH-1:0] a3_data_delayed_3; +output [`DWIDTH-1:0] b3_data_delayed_3; +output [`DWIDTH-1:0] a4_data_delayed_4; +output [`DWIDTH-1:0] b4_data_delayed_4; +output [`DWIDTH-1:0] a5_data_delayed_5; +output [`DWIDTH-1:0] b5_data_delayed_5; +output [`DWIDTH-1:0] a6_data_delayed_6; +output [`DWIDTH-1:0] b6_data_delayed_6; +output [`DWIDTH-1:0] a7_data_delayed_7; +output [`DWIDTH-1:0] b7_data_delayed_7; +output [`DWIDTH-1:0] a8_data_delayed_8; +output [`DWIDTH-1:0] b8_data_delayed_8; +output [`DWIDTH-1:0] a9_data_delayed_9; +output [`DWIDTH-1:0] b9_data_delayed_9; +output [`DWIDTH-1:0] a10_data_delayed_10; +output [`DWIDTH-1:0] b10_data_delayed_10; +output [`DWIDTH-1:0] a11_data_delayed_11; +output [`DWIDTH-1:0] b11_data_delayed_11; +output [`DWIDTH-1:0] a12_data_delayed_12; +output [`DWIDTH-1:0] b12_data_delayed_12; +output [`DWIDTH-1:0] a13_data_delayed_13; +output [`DWIDTH-1:0] b13_data_delayed_13; +output [`DWIDTH-1:0] a14_data_delayed_14; +output [`DWIDTH-1:0] b14_data_delayed_14; +output [`DWIDTH-1:0] a15_data_delayed_15; +output [`DWIDTH-1:0] b15_data_delayed_15; +output [`DWIDTH-1:0] a16_data_delayed_16; +output [`DWIDTH-1:0] b16_data_delayed_16; +output [`DWIDTH-1:0] a17_data_delayed_17; +output [`DWIDTH-1:0] b17_data_delayed_17; +output [`DWIDTH-1:0] a18_data_delayed_18; +output [`DWIDTH-1:0] b18_data_delayed_18; +output [`DWIDTH-1:0] a19_data_delayed_19; +output [`DWIDTH-1:0] b19_data_delayed_19; +output [`DWIDTH-1:0] a20_data_delayed_20; +output [`DWIDTH-1:0] b20_data_delayed_20; +output [`DWIDTH-1:0] a21_data_delayed_21; +output [`DWIDTH-1:0] b21_data_delayed_21; +output [`DWIDTH-1:0] a22_data_delayed_22; +output [`DWIDTH-1:0] b22_data_delayed_22; +output [`DWIDTH-1:0] a23_data_delayed_23; +output [`DWIDTH-1:0] b23_data_delayed_23; +output [`DWIDTH-1:0] a24_data_delayed_24; +output [`DWIDTH-1:0] b24_data_delayed_24; +output [`DWIDTH-1:0] a25_data_delayed_25; +output [`DWIDTH-1:0] b25_data_delayed_25; +output [`DWIDTH-1:0] a26_data_delayed_26; +output [`DWIDTH-1:0] b26_data_delayed_26; +output [`DWIDTH-1:0] a27_data_delayed_27; +output [`DWIDTH-1:0] b27_data_delayed_27; +output [`DWIDTH-1:0] a28_data_delayed_28; +output [`DWIDTH-1:0] b28_data_delayed_28; +output [`DWIDTH-1:0] a29_data_delayed_29; +output [`DWIDTH-1:0] b29_data_delayed_29; +output [`DWIDTH-1:0] a30_data_delayed_30; +output [`DWIDTH-1:0] b30_data_delayed_30; +output [`DWIDTH-1:0] a31_data_delayed_31; +output [`DWIDTH-1:0] b31_data_delayed_31; + +input [`MASK_WIDTH-1:0] validity_mask_a_rows; +input [`MASK_WIDTH-1:0] validity_mask_a_cols; +input [`MASK_WIDTH-1:0] validity_mask_b_rows; +input [`MASK_WIDTH-1:0] validity_mask_b_cols; + +input [7:0] final_mat_mul_size; + +input [7:0] a_loc; +input [7:0] b_loc; +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] a16_data; +wire [`DWIDTH-1:0] a17_data; +wire [`DWIDTH-1:0] a18_data; +wire [`DWIDTH-1:0] a19_data; +wire [`DWIDTH-1:0] a20_data; +wire [`DWIDTH-1:0] a21_data; +wire [`DWIDTH-1:0] a22_data; +wire [`DWIDTH-1:0] a23_data; +wire [`DWIDTH-1:0] a24_data; +wire [`DWIDTH-1:0] a25_data; +wire [`DWIDTH-1:0] a26_data; +wire [`DWIDTH-1:0] a27_data; +wire [`DWIDTH-1:0] a28_data; +wire [`DWIDTH-1:0] a29_data; +wire [`DWIDTH-1:0] a30_data; +wire [`DWIDTH-1:0] a31_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; +wire [`DWIDTH-1:0] b16_data; +wire [`DWIDTH-1:0] b17_data; +wire [`DWIDTH-1:0] b18_data; +wire [`DWIDTH-1:0] b19_data; +wire [`DWIDTH-1:0] b20_data; +wire [`DWIDTH-1:0] b21_data; +wire [`DWIDTH-1:0] b22_data; +wire [`DWIDTH-1:0] b23_data; +wire [`DWIDTH-1:0] b24_data; +wire [`DWIDTH-1:0] b25_data; +wire [`DWIDTH-1:0] b26_data; +wire [`DWIDTH-1:0] b27_data; +wire [`DWIDTH-1:0] b28_data; +wire [`DWIDTH-1:0] b29_data; +wire [`DWIDTH-1:0] b30_data; +wire [`DWIDTH-1:0] b31_data; + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM A +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] a_addr; +reg a_mem_access; //flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin + //(clk_cnt >= a_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + + if (reset || ~start_mat_mul || (clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + a_addr <= address_mat_a-address_stride_a; + + a_mem_access <= 0; + end + //else if ((clk_cnt >= a_loc*`MAT_MUL_SIZE) && (clk_cnt < a_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + + else if ((clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (a_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + a_addr <= a_addr + address_stride_a; + + a_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM A +////////////////////////////////////////////////////////////////////////// +reg [7:0] a_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + a_mem_access_counter <= 0; + end + else if (a_mem_access == 1) begin + a_mem_access_counter <= a_mem_access_counter + 1; + end + else begin + a_mem_access_counter <= 0; + end +end + +wire a_data_valid; //flag that tells whether the data from memory is valid +assign a_data_valid = + ((validity_mask_a_cols[0]==1'b0 && a_mem_access_counter==1) || + (validity_mask_a_cols[1]==1'b0 && a_mem_access_counter==2) || + (validity_mask_a_cols[2]==1'b0 && a_mem_access_counter==3) || + (validity_mask_a_cols[3]==1'b0 && a_mem_access_counter==4) || + (validity_mask_a_cols[4]==1'b0 && a_mem_access_counter==5) || + (validity_mask_a_cols[5]==1'b0 && a_mem_access_counter==6) || + (validity_mask_a_cols[6]==1'b0 && a_mem_access_counter==7) || + (validity_mask_a_cols[7]==1'b0 && a_mem_access_counter==8) || + (validity_mask_a_cols[8]==1'b0 && a_mem_access_counter==9) || + (validity_mask_a_cols[9]==1'b0 && a_mem_access_counter==10) || + (validity_mask_a_cols[10]==1'b0 && a_mem_access_counter==11) || + (validity_mask_a_cols[11]==1'b0 && a_mem_access_counter==12) || + (validity_mask_a_cols[12]==1'b0 && a_mem_access_counter==13) || + (validity_mask_a_cols[13]==1'b0 && a_mem_access_counter==14) || + (validity_mask_a_cols[14]==1'b0 && a_mem_access_counter==15) || + (validity_mask_a_cols[15]==1'b0 && a_mem_access_counter==16) || + (validity_mask_a_cols[16]==1'b0 && a_mem_access_counter==17) || + (validity_mask_a_cols[17]==1'b0 && a_mem_access_counter==18) || + (validity_mask_a_cols[18]==1'b0 && a_mem_access_counter==19) || + (validity_mask_a_cols[19]==1'b0 && a_mem_access_counter==20) || + (validity_mask_a_cols[20]==1'b0 && a_mem_access_counter==21) || + (validity_mask_a_cols[21]==1'b0 && a_mem_access_counter==22) || + (validity_mask_a_cols[22]==1'b0 && a_mem_access_counter==23) || + (validity_mask_a_cols[23]==1'b0 && a_mem_access_counter==24) || + (validity_mask_a_cols[24]==1'b0 && a_mem_access_counter==25) || + (validity_mask_a_cols[25]==1'b0 && a_mem_access_counter==26) || + (validity_mask_a_cols[26]==1'b0 && a_mem_access_counter==27) || + (validity_mask_a_cols[27]==1'b0 && a_mem_access_counter==28) || + (validity_mask_a_cols[28]==1'b0 && a_mem_access_counter==29) || + (validity_mask_a_cols[29]==1'b0 && a_mem_access_counter==30) || + (validity_mask_a_cols[30]==1'b0 && a_mem_access_counter==31) || + (validity_mask_a_cols[31]==1'b0 && a_mem_access_counter==32)) ? + + 1'b0 : (a_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM A (systolic data setup) +////////////////////////////////////////////////////////////////////////// +assign a0_data = a_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[0]}}; +assign a1_data = a_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[1]}}; +assign a2_data = a_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[2]}}; +assign a3_data = a_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[3]}}; +assign a4_data = a_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[4]}}; +assign a5_data = a_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[5]}}; +assign a6_data = a_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[6]}}; +assign a7_data = a_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[7]}}; +assign a8_data = a_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[8]}}; +assign a9_data = a_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[9]}}; +assign a10_data = a_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[10]}}; +assign a11_data = a_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[11]}}; +assign a12_data = a_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[12]}}; +assign a13_data = a_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[13]}}; +assign a14_data = a_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[14]}}; +assign a15_data = a_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[15]}}; +assign a16_data = a_data[17*`DWIDTH-1:16*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[16]}}; +assign a17_data = a_data[18*`DWIDTH-1:17*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[17]}}; +assign a18_data = a_data[19*`DWIDTH-1:18*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[18]}}; +assign a19_data = a_data[20*`DWIDTH-1:19*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[19]}}; +assign a20_data = a_data[21*`DWIDTH-1:20*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[20]}}; +assign a21_data = a_data[22*`DWIDTH-1:21*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[21]}}; +assign a22_data = a_data[23*`DWIDTH-1:22*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[22]}}; +assign a23_data = a_data[24*`DWIDTH-1:23*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[23]}}; +assign a24_data = a_data[25*`DWIDTH-1:24*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[24]}}; +assign a25_data = a_data[26*`DWIDTH-1:25*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[25]}}; +assign a26_data = a_data[27*`DWIDTH-1:26*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[26]}}; +assign a27_data = a_data[28*`DWIDTH-1:27*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[27]}}; +assign a28_data = a_data[29*`DWIDTH-1:28*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[28]}}; +assign a29_data = a_data[30*`DWIDTH-1:29*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[29]}}; +assign a30_data = a_data[31*`DWIDTH-1:30*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[30]}}; +assign a31_data = a_data[32*`DWIDTH-1:31*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[31]}}; + +reg [`DWIDTH-1:0] a1_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_1; +reg [`DWIDTH-1:0] a3_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_1; +reg [`DWIDTH-1:0] a4_data_delayed_2; +reg [`DWIDTH-1:0] a4_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_1; +reg [`DWIDTH-1:0] a5_data_delayed_2; +reg [`DWIDTH-1:0] a5_data_delayed_3; +reg [`DWIDTH-1:0] a5_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_1; +reg [`DWIDTH-1:0] a6_data_delayed_2; +reg [`DWIDTH-1:0] a6_data_delayed_3; +reg [`DWIDTH-1:0] a6_data_delayed_4; +reg [`DWIDTH-1:0] a6_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_1; +reg [`DWIDTH-1:0] a7_data_delayed_2; +reg [`DWIDTH-1:0] a7_data_delayed_3; +reg [`DWIDTH-1:0] a7_data_delayed_4; +reg [`DWIDTH-1:0] a7_data_delayed_5; +reg [`DWIDTH-1:0] a7_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_1; +reg [`DWIDTH-1:0] a8_data_delayed_2; +reg [`DWIDTH-1:0] a8_data_delayed_3; +reg [`DWIDTH-1:0] a8_data_delayed_4; +reg [`DWIDTH-1:0] a8_data_delayed_5; +reg [`DWIDTH-1:0] a8_data_delayed_6; +reg [`DWIDTH-1:0] a8_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_1; +reg [`DWIDTH-1:0] a9_data_delayed_2; +reg [`DWIDTH-1:0] a9_data_delayed_3; +reg [`DWIDTH-1:0] a9_data_delayed_4; +reg [`DWIDTH-1:0] a9_data_delayed_5; +reg [`DWIDTH-1:0] a9_data_delayed_6; +reg [`DWIDTH-1:0] a9_data_delayed_7; +reg [`DWIDTH-1:0] a9_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_1; +reg [`DWIDTH-1:0] a10_data_delayed_2; +reg [`DWIDTH-1:0] a10_data_delayed_3; +reg [`DWIDTH-1:0] a10_data_delayed_4; +reg [`DWIDTH-1:0] a10_data_delayed_5; +reg [`DWIDTH-1:0] a10_data_delayed_6; +reg [`DWIDTH-1:0] a10_data_delayed_7; +reg [`DWIDTH-1:0] a10_data_delayed_8; +reg [`DWIDTH-1:0] a10_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_1; +reg [`DWIDTH-1:0] a11_data_delayed_2; +reg [`DWIDTH-1:0] a11_data_delayed_3; +reg [`DWIDTH-1:0] a11_data_delayed_4; +reg [`DWIDTH-1:0] a11_data_delayed_5; +reg [`DWIDTH-1:0] a11_data_delayed_6; +reg [`DWIDTH-1:0] a11_data_delayed_7; +reg [`DWIDTH-1:0] a11_data_delayed_8; +reg [`DWIDTH-1:0] a11_data_delayed_9; +reg [`DWIDTH-1:0] a11_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_1; +reg [`DWIDTH-1:0] a12_data_delayed_2; +reg [`DWIDTH-1:0] a12_data_delayed_3; +reg [`DWIDTH-1:0] a12_data_delayed_4; +reg [`DWIDTH-1:0] a12_data_delayed_5; +reg [`DWIDTH-1:0] a12_data_delayed_6; +reg [`DWIDTH-1:0] a12_data_delayed_7; +reg [`DWIDTH-1:0] a12_data_delayed_8; +reg [`DWIDTH-1:0] a12_data_delayed_9; +reg [`DWIDTH-1:0] a12_data_delayed_10; +reg [`DWIDTH-1:0] a12_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_1; +reg [`DWIDTH-1:0] a13_data_delayed_2; +reg [`DWIDTH-1:0] a13_data_delayed_3; +reg [`DWIDTH-1:0] a13_data_delayed_4; +reg [`DWIDTH-1:0] a13_data_delayed_5; +reg [`DWIDTH-1:0] a13_data_delayed_6; +reg [`DWIDTH-1:0] a13_data_delayed_7; +reg [`DWIDTH-1:0] a13_data_delayed_8; +reg [`DWIDTH-1:0] a13_data_delayed_9; +reg [`DWIDTH-1:0] a13_data_delayed_10; +reg [`DWIDTH-1:0] a13_data_delayed_11; +reg [`DWIDTH-1:0] a13_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_1; +reg [`DWIDTH-1:0] a14_data_delayed_2; +reg [`DWIDTH-1:0] a14_data_delayed_3; +reg [`DWIDTH-1:0] a14_data_delayed_4; +reg [`DWIDTH-1:0] a14_data_delayed_5; +reg [`DWIDTH-1:0] a14_data_delayed_6; +reg [`DWIDTH-1:0] a14_data_delayed_7; +reg [`DWIDTH-1:0] a14_data_delayed_8; +reg [`DWIDTH-1:0] a14_data_delayed_9; +reg [`DWIDTH-1:0] a14_data_delayed_10; +reg [`DWIDTH-1:0] a14_data_delayed_11; +reg [`DWIDTH-1:0] a14_data_delayed_12; +reg [`DWIDTH-1:0] a14_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_1; +reg [`DWIDTH-1:0] a15_data_delayed_2; +reg [`DWIDTH-1:0] a15_data_delayed_3; +reg [`DWIDTH-1:0] a15_data_delayed_4; +reg [`DWIDTH-1:0] a15_data_delayed_5; +reg [`DWIDTH-1:0] a15_data_delayed_6; +reg [`DWIDTH-1:0] a15_data_delayed_7; +reg [`DWIDTH-1:0] a15_data_delayed_8; +reg [`DWIDTH-1:0] a15_data_delayed_9; +reg [`DWIDTH-1:0] a15_data_delayed_10; +reg [`DWIDTH-1:0] a15_data_delayed_11; +reg [`DWIDTH-1:0] a15_data_delayed_12; +reg [`DWIDTH-1:0] a15_data_delayed_13; +reg [`DWIDTH-1:0] a15_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_15; +reg [`DWIDTH-1:0] a16_data_delayed_1; +reg [`DWIDTH-1:0] a16_data_delayed_2; +reg [`DWIDTH-1:0] a16_data_delayed_3; +reg [`DWIDTH-1:0] a16_data_delayed_4; +reg [`DWIDTH-1:0] a16_data_delayed_5; +reg [`DWIDTH-1:0] a16_data_delayed_6; +reg [`DWIDTH-1:0] a16_data_delayed_7; +reg [`DWIDTH-1:0] a16_data_delayed_8; +reg [`DWIDTH-1:0] a16_data_delayed_9; +reg [`DWIDTH-1:0] a16_data_delayed_10; +reg [`DWIDTH-1:0] a16_data_delayed_11; +reg [`DWIDTH-1:0] a16_data_delayed_12; +reg [`DWIDTH-1:0] a16_data_delayed_13; +reg [`DWIDTH-1:0] a16_data_delayed_14; +reg [`DWIDTH-1:0] a16_data_delayed_15; +reg [`DWIDTH-1:0] a16_data_delayed_16; +reg [`DWIDTH-1:0] a17_data_delayed_1; +reg [`DWIDTH-1:0] a17_data_delayed_2; +reg [`DWIDTH-1:0] a17_data_delayed_3; +reg [`DWIDTH-1:0] a17_data_delayed_4; +reg [`DWIDTH-1:0] a17_data_delayed_5; +reg [`DWIDTH-1:0] a17_data_delayed_6; +reg [`DWIDTH-1:0] a17_data_delayed_7; +reg [`DWIDTH-1:0] a17_data_delayed_8; +reg [`DWIDTH-1:0] a17_data_delayed_9; +reg [`DWIDTH-1:0] a17_data_delayed_10; +reg [`DWIDTH-1:0] a17_data_delayed_11; +reg [`DWIDTH-1:0] a17_data_delayed_12; +reg [`DWIDTH-1:0] a17_data_delayed_13; +reg [`DWIDTH-1:0] a17_data_delayed_14; +reg [`DWIDTH-1:0] a17_data_delayed_15; +reg [`DWIDTH-1:0] a17_data_delayed_16; +reg [`DWIDTH-1:0] a17_data_delayed_17; +reg [`DWIDTH-1:0] a18_data_delayed_1; +reg [`DWIDTH-1:0] a18_data_delayed_2; +reg [`DWIDTH-1:0] a18_data_delayed_3; +reg [`DWIDTH-1:0] a18_data_delayed_4; +reg [`DWIDTH-1:0] a18_data_delayed_5; +reg [`DWIDTH-1:0] a18_data_delayed_6; +reg [`DWIDTH-1:0] a18_data_delayed_7; +reg [`DWIDTH-1:0] a18_data_delayed_8; +reg [`DWIDTH-1:0] a18_data_delayed_9; +reg [`DWIDTH-1:0] a18_data_delayed_10; +reg [`DWIDTH-1:0] a18_data_delayed_11; +reg [`DWIDTH-1:0] a18_data_delayed_12; +reg [`DWIDTH-1:0] a18_data_delayed_13; +reg [`DWIDTH-1:0] a18_data_delayed_14; +reg [`DWIDTH-1:0] a18_data_delayed_15; +reg [`DWIDTH-1:0] a18_data_delayed_16; +reg [`DWIDTH-1:0] a18_data_delayed_17; +reg [`DWIDTH-1:0] a18_data_delayed_18; +reg [`DWIDTH-1:0] a19_data_delayed_1; +reg [`DWIDTH-1:0] a19_data_delayed_2; +reg [`DWIDTH-1:0] a19_data_delayed_3; +reg [`DWIDTH-1:0] a19_data_delayed_4; +reg [`DWIDTH-1:0] a19_data_delayed_5; +reg [`DWIDTH-1:0] a19_data_delayed_6; +reg [`DWIDTH-1:0] a19_data_delayed_7; +reg [`DWIDTH-1:0] a19_data_delayed_8; +reg [`DWIDTH-1:0] a19_data_delayed_9; +reg [`DWIDTH-1:0] a19_data_delayed_10; +reg [`DWIDTH-1:0] a19_data_delayed_11; +reg [`DWIDTH-1:0] a19_data_delayed_12; +reg [`DWIDTH-1:0] a19_data_delayed_13; +reg [`DWIDTH-1:0] a19_data_delayed_14; +reg [`DWIDTH-1:0] a19_data_delayed_15; +reg [`DWIDTH-1:0] a19_data_delayed_16; +reg [`DWIDTH-1:0] a19_data_delayed_17; +reg [`DWIDTH-1:0] a19_data_delayed_18; +reg [`DWIDTH-1:0] a19_data_delayed_19; +reg [`DWIDTH-1:0] a20_data_delayed_1; +reg [`DWIDTH-1:0] a20_data_delayed_2; +reg [`DWIDTH-1:0] a20_data_delayed_3; +reg [`DWIDTH-1:0] a20_data_delayed_4; +reg [`DWIDTH-1:0] a20_data_delayed_5; +reg [`DWIDTH-1:0] a20_data_delayed_6; +reg [`DWIDTH-1:0] a20_data_delayed_7; +reg [`DWIDTH-1:0] a20_data_delayed_8; +reg [`DWIDTH-1:0] a20_data_delayed_9; +reg [`DWIDTH-1:0] a20_data_delayed_10; +reg [`DWIDTH-1:0] a20_data_delayed_11; +reg [`DWIDTH-1:0] a20_data_delayed_12; +reg [`DWIDTH-1:0] a20_data_delayed_13; +reg [`DWIDTH-1:0] a20_data_delayed_14; +reg [`DWIDTH-1:0] a20_data_delayed_15; +reg [`DWIDTH-1:0] a20_data_delayed_16; +reg [`DWIDTH-1:0] a20_data_delayed_17; +reg [`DWIDTH-1:0] a20_data_delayed_18; +reg [`DWIDTH-1:0] a20_data_delayed_19; +reg [`DWIDTH-1:0] a20_data_delayed_20; +reg [`DWIDTH-1:0] a21_data_delayed_1; +reg [`DWIDTH-1:0] a21_data_delayed_2; +reg [`DWIDTH-1:0] a21_data_delayed_3; +reg [`DWIDTH-1:0] a21_data_delayed_4; +reg [`DWIDTH-1:0] a21_data_delayed_5; +reg [`DWIDTH-1:0] a21_data_delayed_6; +reg [`DWIDTH-1:0] a21_data_delayed_7; +reg [`DWIDTH-1:0] a21_data_delayed_8; +reg [`DWIDTH-1:0] a21_data_delayed_9; +reg [`DWIDTH-1:0] a21_data_delayed_10; +reg [`DWIDTH-1:0] a21_data_delayed_11; +reg [`DWIDTH-1:0] a21_data_delayed_12; +reg [`DWIDTH-1:0] a21_data_delayed_13; +reg [`DWIDTH-1:0] a21_data_delayed_14; +reg [`DWIDTH-1:0] a21_data_delayed_15; +reg [`DWIDTH-1:0] a21_data_delayed_16; +reg [`DWIDTH-1:0] a21_data_delayed_17; +reg [`DWIDTH-1:0] a21_data_delayed_18; +reg [`DWIDTH-1:0] a21_data_delayed_19; +reg [`DWIDTH-1:0] a21_data_delayed_20; +reg [`DWIDTH-1:0] a21_data_delayed_21; +reg [`DWIDTH-1:0] a22_data_delayed_1; +reg [`DWIDTH-1:0] a22_data_delayed_2; +reg [`DWIDTH-1:0] a22_data_delayed_3; +reg [`DWIDTH-1:0] a22_data_delayed_4; +reg [`DWIDTH-1:0] a22_data_delayed_5; +reg [`DWIDTH-1:0] a22_data_delayed_6; +reg [`DWIDTH-1:0] a22_data_delayed_7; +reg [`DWIDTH-1:0] a22_data_delayed_8; +reg [`DWIDTH-1:0] a22_data_delayed_9; +reg [`DWIDTH-1:0] a22_data_delayed_10; +reg [`DWIDTH-1:0] a22_data_delayed_11; +reg [`DWIDTH-1:0] a22_data_delayed_12; +reg [`DWIDTH-1:0] a22_data_delayed_13; +reg [`DWIDTH-1:0] a22_data_delayed_14; +reg [`DWIDTH-1:0] a22_data_delayed_15; +reg [`DWIDTH-1:0] a22_data_delayed_16; +reg [`DWIDTH-1:0] a22_data_delayed_17; +reg [`DWIDTH-1:0] a22_data_delayed_18; +reg [`DWIDTH-1:0] a22_data_delayed_19; +reg [`DWIDTH-1:0] a22_data_delayed_20; +reg [`DWIDTH-1:0] a22_data_delayed_21; +reg [`DWIDTH-1:0] a22_data_delayed_22; +reg [`DWIDTH-1:0] a23_data_delayed_1; +reg [`DWIDTH-1:0] a23_data_delayed_2; +reg [`DWIDTH-1:0] a23_data_delayed_3; +reg [`DWIDTH-1:0] a23_data_delayed_4; +reg [`DWIDTH-1:0] a23_data_delayed_5; +reg [`DWIDTH-1:0] a23_data_delayed_6; +reg [`DWIDTH-1:0] a23_data_delayed_7; +reg [`DWIDTH-1:0] a23_data_delayed_8; +reg [`DWIDTH-1:0] a23_data_delayed_9; +reg [`DWIDTH-1:0] a23_data_delayed_10; +reg [`DWIDTH-1:0] a23_data_delayed_11; +reg [`DWIDTH-1:0] a23_data_delayed_12; +reg [`DWIDTH-1:0] a23_data_delayed_13; +reg [`DWIDTH-1:0] a23_data_delayed_14; +reg [`DWIDTH-1:0] a23_data_delayed_15; +reg [`DWIDTH-1:0] a23_data_delayed_16; +reg [`DWIDTH-1:0] a23_data_delayed_17; +reg [`DWIDTH-1:0] a23_data_delayed_18; +reg [`DWIDTH-1:0] a23_data_delayed_19; +reg [`DWIDTH-1:0] a23_data_delayed_20; +reg [`DWIDTH-1:0] a23_data_delayed_21; +reg [`DWIDTH-1:0] a23_data_delayed_22; +reg [`DWIDTH-1:0] a23_data_delayed_23; +reg [`DWIDTH-1:0] a24_data_delayed_1; +reg [`DWIDTH-1:0] a24_data_delayed_2; +reg [`DWIDTH-1:0] a24_data_delayed_3; +reg [`DWIDTH-1:0] a24_data_delayed_4; +reg [`DWIDTH-1:0] a24_data_delayed_5; +reg [`DWIDTH-1:0] a24_data_delayed_6; +reg [`DWIDTH-1:0] a24_data_delayed_7; +reg [`DWIDTH-1:0] a24_data_delayed_8; +reg [`DWIDTH-1:0] a24_data_delayed_9; +reg [`DWIDTH-1:0] a24_data_delayed_10; +reg [`DWIDTH-1:0] a24_data_delayed_11; +reg [`DWIDTH-1:0] a24_data_delayed_12; +reg [`DWIDTH-1:0] a24_data_delayed_13; +reg [`DWIDTH-1:0] a24_data_delayed_14; +reg [`DWIDTH-1:0] a24_data_delayed_15; +reg [`DWIDTH-1:0] a24_data_delayed_16; +reg [`DWIDTH-1:0] a24_data_delayed_17; +reg [`DWIDTH-1:0] a24_data_delayed_18; +reg [`DWIDTH-1:0] a24_data_delayed_19; +reg [`DWIDTH-1:0] a24_data_delayed_20; +reg [`DWIDTH-1:0] a24_data_delayed_21; +reg [`DWIDTH-1:0] a24_data_delayed_22; +reg [`DWIDTH-1:0] a24_data_delayed_23; +reg [`DWIDTH-1:0] a24_data_delayed_24; +reg [`DWIDTH-1:0] a25_data_delayed_1; +reg [`DWIDTH-1:0] a25_data_delayed_2; +reg [`DWIDTH-1:0] a25_data_delayed_3; +reg [`DWIDTH-1:0] a25_data_delayed_4; +reg [`DWIDTH-1:0] a25_data_delayed_5; +reg [`DWIDTH-1:0] a25_data_delayed_6; +reg [`DWIDTH-1:0] a25_data_delayed_7; +reg [`DWIDTH-1:0] a25_data_delayed_8; +reg [`DWIDTH-1:0] a25_data_delayed_9; +reg [`DWIDTH-1:0] a25_data_delayed_10; +reg [`DWIDTH-1:0] a25_data_delayed_11; +reg [`DWIDTH-1:0] a25_data_delayed_12; +reg [`DWIDTH-1:0] a25_data_delayed_13; +reg [`DWIDTH-1:0] a25_data_delayed_14; +reg [`DWIDTH-1:0] a25_data_delayed_15; +reg [`DWIDTH-1:0] a25_data_delayed_16; +reg [`DWIDTH-1:0] a25_data_delayed_17; +reg [`DWIDTH-1:0] a25_data_delayed_18; +reg [`DWIDTH-1:0] a25_data_delayed_19; +reg [`DWIDTH-1:0] a25_data_delayed_20; +reg [`DWIDTH-1:0] a25_data_delayed_21; +reg [`DWIDTH-1:0] a25_data_delayed_22; +reg [`DWIDTH-1:0] a25_data_delayed_23; +reg [`DWIDTH-1:0] a25_data_delayed_24; +reg [`DWIDTH-1:0] a25_data_delayed_25; +reg [`DWIDTH-1:0] a26_data_delayed_1; +reg [`DWIDTH-1:0] a26_data_delayed_2; +reg [`DWIDTH-1:0] a26_data_delayed_3; +reg [`DWIDTH-1:0] a26_data_delayed_4; +reg [`DWIDTH-1:0] a26_data_delayed_5; +reg [`DWIDTH-1:0] a26_data_delayed_6; +reg [`DWIDTH-1:0] a26_data_delayed_7; +reg [`DWIDTH-1:0] a26_data_delayed_8; +reg [`DWIDTH-1:0] a26_data_delayed_9; +reg [`DWIDTH-1:0] a26_data_delayed_10; +reg [`DWIDTH-1:0] a26_data_delayed_11; +reg [`DWIDTH-1:0] a26_data_delayed_12; +reg [`DWIDTH-1:0] a26_data_delayed_13; +reg [`DWIDTH-1:0] a26_data_delayed_14; +reg [`DWIDTH-1:0] a26_data_delayed_15; +reg [`DWIDTH-1:0] a26_data_delayed_16; +reg [`DWIDTH-1:0] a26_data_delayed_17; +reg [`DWIDTH-1:0] a26_data_delayed_18; +reg [`DWIDTH-1:0] a26_data_delayed_19; +reg [`DWIDTH-1:0] a26_data_delayed_20; +reg [`DWIDTH-1:0] a26_data_delayed_21; +reg [`DWIDTH-1:0] a26_data_delayed_22; +reg [`DWIDTH-1:0] a26_data_delayed_23; +reg [`DWIDTH-1:0] a26_data_delayed_24; +reg [`DWIDTH-1:0] a26_data_delayed_25; +reg [`DWIDTH-1:0] a26_data_delayed_26; +reg [`DWIDTH-1:0] a27_data_delayed_1; +reg [`DWIDTH-1:0] a27_data_delayed_2; +reg [`DWIDTH-1:0] a27_data_delayed_3; +reg [`DWIDTH-1:0] a27_data_delayed_4; +reg [`DWIDTH-1:0] a27_data_delayed_5; +reg [`DWIDTH-1:0] a27_data_delayed_6; +reg [`DWIDTH-1:0] a27_data_delayed_7; +reg [`DWIDTH-1:0] a27_data_delayed_8; +reg [`DWIDTH-1:0] a27_data_delayed_9; +reg [`DWIDTH-1:0] a27_data_delayed_10; +reg [`DWIDTH-1:0] a27_data_delayed_11; +reg [`DWIDTH-1:0] a27_data_delayed_12; +reg [`DWIDTH-1:0] a27_data_delayed_13; +reg [`DWIDTH-1:0] a27_data_delayed_14; +reg [`DWIDTH-1:0] a27_data_delayed_15; +reg [`DWIDTH-1:0] a27_data_delayed_16; +reg [`DWIDTH-1:0] a27_data_delayed_17; +reg [`DWIDTH-1:0] a27_data_delayed_18; +reg [`DWIDTH-1:0] a27_data_delayed_19; +reg [`DWIDTH-1:0] a27_data_delayed_20; +reg [`DWIDTH-1:0] a27_data_delayed_21; +reg [`DWIDTH-1:0] a27_data_delayed_22; +reg [`DWIDTH-1:0] a27_data_delayed_23; +reg [`DWIDTH-1:0] a27_data_delayed_24; +reg [`DWIDTH-1:0] a27_data_delayed_25; +reg [`DWIDTH-1:0] a27_data_delayed_26; +reg [`DWIDTH-1:0] a27_data_delayed_27; +reg [`DWIDTH-1:0] a28_data_delayed_1; +reg [`DWIDTH-1:0] a28_data_delayed_2; +reg [`DWIDTH-1:0] a28_data_delayed_3; +reg [`DWIDTH-1:0] a28_data_delayed_4; +reg [`DWIDTH-1:0] a28_data_delayed_5; +reg [`DWIDTH-1:0] a28_data_delayed_6; +reg [`DWIDTH-1:0] a28_data_delayed_7; +reg [`DWIDTH-1:0] a28_data_delayed_8; +reg [`DWIDTH-1:0] a28_data_delayed_9; +reg [`DWIDTH-1:0] a28_data_delayed_10; +reg [`DWIDTH-1:0] a28_data_delayed_11; +reg [`DWIDTH-1:0] a28_data_delayed_12; +reg [`DWIDTH-1:0] a28_data_delayed_13; +reg [`DWIDTH-1:0] a28_data_delayed_14; +reg [`DWIDTH-1:0] a28_data_delayed_15; +reg [`DWIDTH-1:0] a28_data_delayed_16; +reg [`DWIDTH-1:0] a28_data_delayed_17; +reg [`DWIDTH-1:0] a28_data_delayed_18; +reg [`DWIDTH-1:0] a28_data_delayed_19; +reg [`DWIDTH-1:0] a28_data_delayed_20; +reg [`DWIDTH-1:0] a28_data_delayed_21; +reg [`DWIDTH-1:0] a28_data_delayed_22; +reg [`DWIDTH-1:0] a28_data_delayed_23; +reg [`DWIDTH-1:0] a28_data_delayed_24; +reg [`DWIDTH-1:0] a28_data_delayed_25; +reg [`DWIDTH-1:0] a28_data_delayed_26; +reg [`DWIDTH-1:0] a28_data_delayed_27; +reg [`DWIDTH-1:0] a28_data_delayed_28; +reg [`DWIDTH-1:0] a29_data_delayed_1; +reg [`DWIDTH-1:0] a29_data_delayed_2; +reg [`DWIDTH-1:0] a29_data_delayed_3; +reg [`DWIDTH-1:0] a29_data_delayed_4; +reg [`DWIDTH-1:0] a29_data_delayed_5; +reg [`DWIDTH-1:0] a29_data_delayed_6; +reg [`DWIDTH-1:0] a29_data_delayed_7; +reg [`DWIDTH-1:0] a29_data_delayed_8; +reg [`DWIDTH-1:0] a29_data_delayed_9; +reg [`DWIDTH-1:0] a29_data_delayed_10; +reg [`DWIDTH-1:0] a29_data_delayed_11; +reg [`DWIDTH-1:0] a29_data_delayed_12; +reg [`DWIDTH-1:0] a29_data_delayed_13; +reg [`DWIDTH-1:0] a29_data_delayed_14; +reg [`DWIDTH-1:0] a29_data_delayed_15; +reg [`DWIDTH-1:0] a29_data_delayed_16; +reg [`DWIDTH-1:0] a29_data_delayed_17; +reg [`DWIDTH-1:0] a29_data_delayed_18; +reg [`DWIDTH-1:0] a29_data_delayed_19; +reg [`DWIDTH-1:0] a29_data_delayed_20; +reg [`DWIDTH-1:0] a29_data_delayed_21; +reg [`DWIDTH-1:0] a29_data_delayed_22; +reg [`DWIDTH-1:0] a29_data_delayed_23; +reg [`DWIDTH-1:0] a29_data_delayed_24; +reg [`DWIDTH-1:0] a29_data_delayed_25; +reg [`DWIDTH-1:0] a29_data_delayed_26; +reg [`DWIDTH-1:0] a29_data_delayed_27; +reg [`DWIDTH-1:0] a29_data_delayed_28; +reg [`DWIDTH-1:0] a29_data_delayed_29; +reg [`DWIDTH-1:0] a30_data_delayed_1; +reg [`DWIDTH-1:0] a30_data_delayed_2; +reg [`DWIDTH-1:0] a30_data_delayed_3; +reg [`DWIDTH-1:0] a30_data_delayed_4; +reg [`DWIDTH-1:0] a30_data_delayed_5; +reg [`DWIDTH-1:0] a30_data_delayed_6; +reg [`DWIDTH-1:0] a30_data_delayed_7; +reg [`DWIDTH-1:0] a30_data_delayed_8; +reg [`DWIDTH-1:0] a30_data_delayed_9; +reg [`DWIDTH-1:0] a30_data_delayed_10; +reg [`DWIDTH-1:0] a30_data_delayed_11; +reg [`DWIDTH-1:0] a30_data_delayed_12; +reg [`DWIDTH-1:0] a30_data_delayed_13; +reg [`DWIDTH-1:0] a30_data_delayed_14; +reg [`DWIDTH-1:0] a30_data_delayed_15; +reg [`DWIDTH-1:0] a30_data_delayed_16; +reg [`DWIDTH-1:0] a30_data_delayed_17; +reg [`DWIDTH-1:0] a30_data_delayed_18; +reg [`DWIDTH-1:0] a30_data_delayed_19; +reg [`DWIDTH-1:0] a30_data_delayed_20; +reg [`DWIDTH-1:0] a30_data_delayed_21; +reg [`DWIDTH-1:0] a30_data_delayed_22; +reg [`DWIDTH-1:0] a30_data_delayed_23; +reg [`DWIDTH-1:0] a30_data_delayed_24; +reg [`DWIDTH-1:0] a30_data_delayed_25; +reg [`DWIDTH-1:0] a30_data_delayed_26; +reg [`DWIDTH-1:0] a30_data_delayed_27; +reg [`DWIDTH-1:0] a30_data_delayed_28; +reg [`DWIDTH-1:0] a30_data_delayed_29; +reg [`DWIDTH-1:0] a30_data_delayed_30; +reg [`DWIDTH-1:0] a31_data_delayed_1; +reg [`DWIDTH-1:0] a31_data_delayed_2; +reg [`DWIDTH-1:0] a31_data_delayed_3; +reg [`DWIDTH-1:0] a31_data_delayed_4; +reg [`DWIDTH-1:0] a31_data_delayed_5; +reg [`DWIDTH-1:0] a31_data_delayed_6; +reg [`DWIDTH-1:0] a31_data_delayed_7; +reg [`DWIDTH-1:0] a31_data_delayed_8; +reg [`DWIDTH-1:0] a31_data_delayed_9; +reg [`DWIDTH-1:0] a31_data_delayed_10; +reg [`DWIDTH-1:0] a31_data_delayed_11; +reg [`DWIDTH-1:0] a31_data_delayed_12; +reg [`DWIDTH-1:0] a31_data_delayed_13; +reg [`DWIDTH-1:0] a31_data_delayed_14; +reg [`DWIDTH-1:0] a31_data_delayed_15; +reg [`DWIDTH-1:0] a31_data_delayed_16; +reg [`DWIDTH-1:0] a31_data_delayed_17; +reg [`DWIDTH-1:0] a31_data_delayed_18; +reg [`DWIDTH-1:0] a31_data_delayed_19; +reg [`DWIDTH-1:0] a31_data_delayed_20; +reg [`DWIDTH-1:0] a31_data_delayed_21; +reg [`DWIDTH-1:0] a31_data_delayed_22; +reg [`DWIDTH-1:0] a31_data_delayed_23; +reg [`DWIDTH-1:0] a31_data_delayed_24; +reg [`DWIDTH-1:0] a31_data_delayed_25; +reg [`DWIDTH-1:0] a31_data_delayed_26; +reg [`DWIDTH-1:0] a31_data_delayed_27; +reg [`DWIDTH-1:0] a31_data_delayed_28; +reg [`DWIDTH-1:0] a31_data_delayed_29; +reg [`DWIDTH-1:0] a31_data_delayed_30; +reg [`DWIDTH-1:0] a31_data_delayed_31; + + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + a1_data_delayed_1 <= 0; + a2_data_delayed_1 <= 0; + a2_data_delayed_2 <= 0; + a3_data_delayed_1 <= 0; + a3_data_delayed_2 <= 0; + a3_data_delayed_3 <= 0; + a4_data_delayed_1 <= 0; + a4_data_delayed_2 <= 0; + a4_data_delayed_3 <= 0; + a4_data_delayed_4 <= 0; + a5_data_delayed_1 <= 0; + a5_data_delayed_2 <= 0; + a5_data_delayed_3 <= 0; + a5_data_delayed_4 <= 0; + a5_data_delayed_5 <= 0; + a6_data_delayed_1 <= 0; + a6_data_delayed_2 <= 0; + a6_data_delayed_3 <= 0; + a6_data_delayed_4 <= 0; + a6_data_delayed_5 <= 0; + a6_data_delayed_6 <= 0; + a7_data_delayed_1 <= 0; + a7_data_delayed_2 <= 0; + a7_data_delayed_3 <= 0; + a7_data_delayed_4 <= 0; + a7_data_delayed_5 <= 0; + a7_data_delayed_6 <= 0; + a7_data_delayed_7 <= 0; + a8_data_delayed_1 <= 0; + a8_data_delayed_2 <= 0; + a8_data_delayed_3 <= 0; + a8_data_delayed_4 <= 0; + a8_data_delayed_5 <= 0; + a8_data_delayed_6 <= 0; + a8_data_delayed_7 <= 0; + a8_data_delayed_8 <= 0; + a9_data_delayed_1 <= 0; + a9_data_delayed_2 <= 0; + a9_data_delayed_3 <= 0; + a9_data_delayed_4 <= 0; + a9_data_delayed_5 <= 0; + a9_data_delayed_6 <= 0; + a9_data_delayed_7 <= 0; + a9_data_delayed_8 <= 0; + a9_data_delayed_9 <= 0; + a10_data_delayed_1 <= 0; + a10_data_delayed_2 <= 0; + a10_data_delayed_3 <= 0; + a10_data_delayed_4 <= 0; + a10_data_delayed_5 <= 0; + a10_data_delayed_6 <= 0; + a10_data_delayed_7 <= 0; + a10_data_delayed_8 <= 0; + a10_data_delayed_9 <= 0; + a10_data_delayed_10 <= 0; + a11_data_delayed_1 <= 0; + a11_data_delayed_2 <= 0; + a11_data_delayed_3 <= 0; + a11_data_delayed_4 <= 0; + a11_data_delayed_5 <= 0; + a11_data_delayed_6 <= 0; + a11_data_delayed_7 <= 0; + a11_data_delayed_8 <= 0; + a11_data_delayed_9 <= 0; + a11_data_delayed_10 <= 0; + a11_data_delayed_11 <= 0; + a12_data_delayed_1 <= 0; + a12_data_delayed_2 <= 0; + a12_data_delayed_3 <= 0; + a12_data_delayed_4 <= 0; + a12_data_delayed_5 <= 0; + a12_data_delayed_6 <= 0; + a12_data_delayed_7 <= 0; + a12_data_delayed_8 <= 0; + a12_data_delayed_9 <= 0; + a12_data_delayed_10 <= 0; + a12_data_delayed_11 <= 0; + a12_data_delayed_12 <= 0; + a13_data_delayed_1 <= 0; + a13_data_delayed_2 <= 0; + a13_data_delayed_3 <= 0; + a13_data_delayed_4 <= 0; + a13_data_delayed_5 <= 0; + a13_data_delayed_6 <= 0; + a13_data_delayed_7 <= 0; + a13_data_delayed_8 <= 0; + a13_data_delayed_9 <= 0; + a13_data_delayed_10 <= 0; + a13_data_delayed_11 <= 0; + a13_data_delayed_12 <= 0; + a13_data_delayed_13 <= 0; + a14_data_delayed_1 <= 0; + a14_data_delayed_2 <= 0; + a14_data_delayed_3 <= 0; + a14_data_delayed_4 <= 0; + a14_data_delayed_5 <= 0; + a14_data_delayed_6 <= 0; + a14_data_delayed_7 <= 0; + a14_data_delayed_8 <= 0; + a14_data_delayed_9 <= 0; + a14_data_delayed_10 <= 0; + a14_data_delayed_11 <= 0; + a14_data_delayed_12 <= 0; + a14_data_delayed_13 <= 0; + a14_data_delayed_14 <= 0; + a15_data_delayed_1 <= 0; + a15_data_delayed_2 <= 0; + a15_data_delayed_3 <= 0; + a15_data_delayed_4 <= 0; + a15_data_delayed_5 <= 0; + a15_data_delayed_6 <= 0; + a15_data_delayed_7 <= 0; + a15_data_delayed_8 <= 0; + a15_data_delayed_9 <= 0; + a15_data_delayed_10 <= 0; + a15_data_delayed_11 <= 0; + a15_data_delayed_12 <= 0; + a15_data_delayed_13 <= 0; + a15_data_delayed_14 <= 0; + a15_data_delayed_15 <= 0; + a16_data_delayed_1 <= 0; + a16_data_delayed_2 <= 0; + a16_data_delayed_3 <= 0; + a16_data_delayed_4 <= 0; + a16_data_delayed_5 <= 0; + a16_data_delayed_6 <= 0; + a16_data_delayed_7 <= 0; + a16_data_delayed_8 <= 0; + a16_data_delayed_9 <= 0; + a16_data_delayed_10 <= 0; + a16_data_delayed_11 <= 0; + a16_data_delayed_12 <= 0; + a16_data_delayed_13 <= 0; + a16_data_delayed_14 <= 0; + a16_data_delayed_15 <= 0; + a16_data_delayed_16 <= 0; + a17_data_delayed_1 <= 0; + a17_data_delayed_2 <= 0; + a17_data_delayed_3 <= 0; + a17_data_delayed_4 <= 0; + a17_data_delayed_5 <= 0; + a17_data_delayed_6 <= 0; + a17_data_delayed_7 <= 0; + a17_data_delayed_8 <= 0; + a17_data_delayed_9 <= 0; + a17_data_delayed_10 <= 0; + a17_data_delayed_11 <= 0; + a17_data_delayed_12 <= 0; + a17_data_delayed_13 <= 0; + a17_data_delayed_14 <= 0; + a17_data_delayed_15 <= 0; + a17_data_delayed_16 <= 0; + a17_data_delayed_17 <= 0; + a18_data_delayed_1 <= 0; + a18_data_delayed_2 <= 0; + a18_data_delayed_3 <= 0; + a18_data_delayed_4 <= 0; + a18_data_delayed_5 <= 0; + a18_data_delayed_6 <= 0; + a18_data_delayed_7 <= 0; + a18_data_delayed_8 <= 0; + a18_data_delayed_9 <= 0; + a18_data_delayed_10 <= 0; + a18_data_delayed_11 <= 0; + a18_data_delayed_12 <= 0; + a18_data_delayed_13 <= 0; + a18_data_delayed_14 <= 0; + a18_data_delayed_15 <= 0; + a18_data_delayed_16 <= 0; + a18_data_delayed_17 <= 0; + a18_data_delayed_18 <= 0; + a19_data_delayed_1 <= 0; + a19_data_delayed_2 <= 0; + a19_data_delayed_3 <= 0; + a19_data_delayed_4 <= 0; + a19_data_delayed_5 <= 0; + a19_data_delayed_6 <= 0; + a19_data_delayed_7 <= 0; + a19_data_delayed_8 <= 0; + a19_data_delayed_9 <= 0; + a19_data_delayed_10 <= 0; + a19_data_delayed_11 <= 0; + a19_data_delayed_12 <= 0; + a19_data_delayed_13 <= 0; + a19_data_delayed_14 <= 0; + a19_data_delayed_15 <= 0; + a19_data_delayed_16 <= 0; + a19_data_delayed_17 <= 0; + a19_data_delayed_18 <= 0; + a19_data_delayed_19 <= 0; + a20_data_delayed_1 <= 0; + a20_data_delayed_2 <= 0; + a20_data_delayed_3 <= 0; + a20_data_delayed_4 <= 0; + a20_data_delayed_5 <= 0; + a20_data_delayed_6 <= 0; + a20_data_delayed_7 <= 0; + a20_data_delayed_8 <= 0; + a20_data_delayed_9 <= 0; + a20_data_delayed_10 <= 0; + a20_data_delayed_11 <= 0; + a20_data_delayed_12 <= 0; + a20_data_delayed_13 <= 0; + a20_data_delayed_14 <= 0; + a20_data_delayed_15 <= 0; + a20_data_delayed_16 <= 0; + a20_data_delayed_17 <= 0; + a20_data_delayed_18 <= 0; + a20_data_delayed_19 <= 0; + a20_data_delayed_20 <= 0; + a21_data_delayed_1 <= 0; + a21_data_delayed_2 <= 0; + a21_data_delayed_3 <= 0; + a21_data_delayed_4 <= 0; + a21_data_delayed_5 <= 0; + a21_data_delayed_6 <= 0; + a21_data_delayed_7 <= 0; + a21_data_delayed_8 <= 0; + a21_data_delayed_9 <= 0; + a21_data_delayed_10 <= 0; + a21_data_delayed_11 <= 0; + a21_data_delayed_12 <= 0; + a21_data_delayed_13 <= 0; + a21_data_delayed_14 <= 0; + a21_data_delayed_15 <= 0; + a21_data_delayed_16 <= 0; + a21_data_delayed_17 <= 0; + a21_data_delayed_18 <= 0; + a21_data_delayed_19 <= 0; + a21_data_delayed_20 <= 0; + a21_data_delayed_21 <= 0; + a22_data_delayed_1 <= 0; + a22_data_delayed_2 <= 0; + a22_data_delayed_3 <= 0; + a22_data_delayed_4 <= 0; + a22_data_delayed_5 <= 0; + a22_data_delayed_6 <= 0; + a22_data_delayed_7 <= 0; + a22_data_delayed_8 <= 0; + a22_data_delayed_9 <= 0; + a22_data_delayed_10 <= 0; + a22_data_delayed_11 <= 0; + a22_data_delayed_12 <= 0; + a22_data_delayed_13 <= 0; + a22_data_delayed_14 <= 0; + a22_data_delayed_15 <= 0; + a22_data_delayed_16 <= 0; + a22_data_delayed_17 <= 0; + a22_data_delayed_18 <= 0; + a22_data_delayed_19 <= 0; + a22_data_delayed_20 <= 0; + a22_data_delayed_21 <= 0; + a22_data_delayed_22 <= 0; + a23_data_delayed_1 <= 0; + a23_data_delayed_2 <= 0; + a23_data_delayed_3 <= 0; + a23_data_delayed_4 <= 0; + a23_data_delayed_5 <= 0; + a23_data_delayed_6 <= 0; + a23_data_delayed_7 <= 0; + a23_data_delayed_8 <= 0; + a23_data_delayed_9 <= 0; + a23_data_delayed_10 <= 0; + a23_data_delayed_11 <= 0; + a23_data_delayed_12 <= 0; + a23_data_delayed_13 <= 0; + a23_data_delayed_14 <= 0; + a23_data_delayed_15 <= 0; + a23_data_delayed_16 <= 0; + a23_data_delayed_17 <= 0; + a23_data_delayed_18 <= 0; + a23_data_delayed_19 <= 0; + a23_data_delayed_20 <= 0; + a23_data_delayed_21 <= 0; + a23_data_delayed_22 <= 0; + a23_data_delayed_23 <= 0; + a24_data_delayed_1 <= 0; + a24_data_delayed_2 <= 0; + a24_data_delayed_3 <= 0; + a24_data_delayed_4 <= 0; + a24_data_delayed_5 <= 0; + a24_data_delayed_6 <= 0; + a24_data_delayed_7 <= 0; + a24_data_delayed_8 <= 0; + a24_data_delayed_9 <= 0; + a24_data_delayed_10 <= 0; + a24_data_delayed_11 <= 0; + a24_data_delayed_12 <= 0; + a24_data_delayed_13 <= 0; + a24_data_delayed_14 <= 0; + a24_data_delayed_15 <= 0; + a24_data_delayed_16 <= 0; + a24_data_delayed_17 <= 0; + a24_data_delayed_18 <= 0; + a24_data_delayed_19 <= 0; + a24_data_delayed_20 <= 0; + a24_data_delayed_21 <= 0; + a24_data_delayed_22 <= 0; + a24_data_delayed_23 <= 0; + a24_data_delayed_24 <= 0; + a25_data_delayed_1 <= 0; + a25_data_delayed_2 <= 0; + a25_data_delayed_3 <= 0; + a25_data_delayed_4 <= 0; + a25_data_delayed_5 <= 0; + a25_data_delayed_6 <= 0; + a25_data_delayed_7 <= 0; + a25_data_delayed_8 <= 0; + a25_data_delayed_9 <= 0; + a25_data_delayed_10 <= 0; + a25_data_delayed_11 <= 0; + a25_data_delayed_12 <= 0; + a25_data_delayed_13 <= 0; + a25_data_delayed_14 <= 0; + a25_data_delayed_15 <= 0; + a25_data_delayed_16 <= 0; + a25_data_delayed_17 <= 0; + a25_data_delayed_18 <= 0; + a25_data_delayed_19 <= 0; + a25_data_delayed_20 <= 0; + a25_data_delayed_21 <= 0; + a25_data_delayed_22 <= 0; + a25_data_delayed_23 <= 0; + a25_data_delayed_24 <= 0; + a25_data_delayed_25 <= 0; + a26_data_delayed_1 <= 0; + a26_data_delayed_2 <= 0; + a26_data_delayed_3 <= 0; + a26_data_delayed_4 <= 0; + a26_data_delayed_5 <= 0; + a26_data_delayed_6 <= 0; + a26_data_delayed_7 <= 0; + a26_data_delayed_8 <= 0; + a26_data_delayed_9 <= 0; + a26_data_delayed_10 <= 0; + a26_data_delayed_11 <= 0; + a26_data_delayed_12 <= 0; + a26_data_delayed_13 <= 0; + a26_data_delayed_14 <= 0; + a26_data_delayed_15 <= 0; + a26_data_delayed_16 <= 0; + a26_data_delayed_17 <= 0; + a26_data_delayed_18 <= 0; + a26_data_delayed_19 <= 0; + a26_data_delayed_20 <= 0; + a26_data_delayed_21 <= 0; + a26_data_delayed_22 <= 0; + a26_data_delayed_23 <= 0; + a26_data_delayed_24 <= 0; + a26_data_delayed_25 <= 0; + a26_data_delayed_26 <= 0; + a27_data_delayed_1 <= 0; + a27_data_delayed_2 <= 0; + a27_data_delayed_3 <= 0; + a27_data_delayed_4 <= 0; + a27_data_delayed_5 <= 0; + a27_data_delayed_6 <= 0; + a27_data_delayed_7 <= 0; + a27_data_delayed_8 <= 0; + a27_data_delayed_9 <= 0; + a27_data_delayed_10 <= 0; + a27_data_delayed_11 <= 0; + a27_data_delayed_12 <= 0; + a27_data_delayed_13 <= 0; + a27_data_delayed_14 <= 0; + a27_data_delayed_15 <= 0; + a27_data_delayed_16 <= 0; + a27_data_delayed_17 <= 0; + a27_data_delayed_18 <= 0; + a27_data_delayed_19 <= 0; + a27_data_delayed_20 <= 0; + a27_data_delayed_21 <= 0; + a27_data_delayed_22 <= 0; + a27_data_delayed_23 <= 0; + a27_data_delayed_24 <= 0; + a27_data_delayed_25 <= 0; + a27_data_delayed_26 <= 0; + a27_data_delayed_27 <= 0; + a28_data_delayed_1 <= 0; + a28_data_delayed_2 <= 0; + a28_data_delayed_3 <= 0; + a28_data_delayed_4 <= 0; + a28_data_delayed_5 <= 0; + a28_data_delayed_6 <= 0; + a28_data_delayed_7 <= 0; + a28_data_delayed_8 <= 0; + a28_data_delayed_9 <= 0; + a28_data_delayed_10 <= 0; + a28_data_delayed_11 <= 0; + a28_data_delayed_12 <= 0; + a28_data_delayed_13 <= 0; + a28_data_delayed_14 <= 0; + a28_data_delayed_15 <= 0; + a28_data_delayed_16 <= 0; + a28_data_delayed_17 <= 0; + a28_data_delayed_18 <= 0; + a28_data_delayed_19 <= 0; + a28_data_delayed_20 <= 0; + a28_data_delayed_21 <= 0; + a28_data_delayed_22 <= 0; + a28_data_delayed_23 <= 0; + a28_data_delayed_24 <= 0; + a28_data_delayed_25 <= 0; + a28_data_delayed_26 <= 0; + a28_data_delayed_27 <= 0; + a28_data_delayed_28 <= 0; + a29_data_delayed_1 <= 0; + a29_data_delayed_2 <= 0; + a29_data_delayed_3 <= 0; + a29_data_delayed_4 <= 0; + a29_data_delayed_5 <= 0; + a29_data_delayed_6 <= 0; + a29_data_delayed_7 <= 0; + a29_data_delayed_8 <= 0; + a29_data_delayed_9 <= 0; + a29_data_delayed_10 <= 0; + a29_data_delayed_11 <= 0; + a29_data_delayed_12 <= 0; + a29_data_delayed_13 <= 0; + a29_data_delayed_14 <= 0; + a29_data_delayed_15 <= 0; + a29_data_delayed_16 <= 0; + a29_data_delayed_17 <= 0; + a29_data_delayed_18 <= 0; + a29_data_delayed_19 <= 0; + a29_data_delayed_20 <= 0; + a29_data_delayed_21 <= 0; + a29_data_delayed_22 <= 0; + a29_data_delayed_23 <= 0; + a29_data_delayed_24 <= 0; + a29_data_delayed_25 <= 0; + a29_data_delayed_26 <= 0; + a29_data_delayed_27 <= 0; + a29_data_delayed_28 <= 0; + a29_data_delayed_29 <= 0; + a30_data_delayed_1 <= 0; + a30_data_delayed_2 <= 0; + a30_data_delayed_3 <= 0; + a30_data_delayed_4 <= 0; + a30_data_delayed_5 <= 0; + a30_data_delayed_6 <= 0; + a30_data_delayed_7 <= 0; + a30_data_delayed_8 <= 0; + a30_data_delayed_9 <= 0; + a30_data_delayed_10 <= 0; + a30_data_delayed_11 <= 0; + a30_data_delayed_12 <= 0; + a30_data_delayed_13 <= 0; + a30_data_delayed_14 <= 0; + a30_data_delayed_15 <= 0; + a30_data_delayed_16 <= 0; + a30_data_delayed_17 <= 0; + a30_data_delayed_18 <= 0; + a30_data_delayed_19 <= 0; + a30_data_delayed_20 <= 0; + a30_data_delayed_21 <= 0; + a30_data_delayed_22 <= 0; + a30_data_delayed_23 <= 0; + a30_data_delayed_24 <= 0; + a30_data_delayed_25 <= 0; + a30_data_delayed_26 <= 0; + a30_data_delayed_27 <= 0; + a30_data_delayed_28 <= 0; + a30_data_delayed_29 <= 0; + a30_data_delayed_30 <= 0; + a31_data_delayed_1 <= 0; + a31_data_delayed_2 <= 0; + a31_data_delayed_3 <= 0; + a31_data_delayed_4 <= 0; + a31_data_delayed_5 <= 0; + a31_data_delayed_6 <= 0; + a31_data_delayed_7 <= 0; + a31_data_delayed_8 <= 0; + a31_data_delayed_9 <= 0; + a31_data_delayed_10 <= 0; + a31_data_delayed_11 <= 0; + a31_data_delayed_12 <= 0; + a31_data_delayed_13 <= 0; + a31_data_delayed_14 <= 0; + a31_data_delayed_15 <= 0; + a31_data_delayed_16 <= 0; + a31_data_delayed_17 <= 0; + a31_data_delayed_18 <= 0; + a31_data_delayed_19 <= 0; + a31_data_delayed_20 <= 0; + a31_data_delayed_21 <= 0; + a31_data_delayed_22 <= 0; + a31_data_delayed_23 <= 0; + a31_data_delayed_24 <= 0; + a31_data_delayed_25 <= 0; + a31_data_delayed_26 <= 0; + a31_data_delayed_27 <= 0; + a31_data_delayed_28 <= 0; + a31_data_delayed_29 <= 0; + a31_data_delayed_30 <= 0; + a31_data_delayed_31 <= 0; + + end + else begin + a1_data_delayed_1 <= a1_data; + a2_data_delayed_1 <= a2_data; + a3_data_delayed_1 <= a3_data; + a4_data_delayed_1 <= a4_data; + a5_data_delayed_1 <= a5_data; + a6_data_delayed_1 <= a6_data; + a7_data_delayed_1 <= a7_data; + a8_data_delayed_1 <= a8_data; + a9_data_delayed_1 <= a9_data; + a10_data_delayed_1 <= a10_data; + a11_data_delayed_1 <= a11_data; + a12_data_delayed_1 <= a12_data; + a13_data_delayed_1 <= a13_data; + a14_data_delayed_1 <= a14_data; + a15_data_delayed_1 <= a15_data; + a16_data_delayed_1 <= a16_data; + a17_data_delayed_1 <= a17_data; + a18_data_delayed_1 <= a18_data; + a19_data_delayed_1 <= a19_data; + a20_data_delayed_1 <= a20_data; + a21_data_delayed_1 <= a21_data; + a22_data_delayed_1 <= a22_data; + a23_data_delayed_1 <= a23_data; + a24_data_delayed_1 <= a24_data; + a25_data_delayed_1 <= a25_data; + a26_data_delayed_1 <= a26_data; + a27_data_delayed_1 <= a27_data; + a28_data_delayed_1 <= a28_data; + a29_data_delayed_1 <= a29_data; + a30_data_delayed_1 <= a30_data; + a31_data_delayed_1 <= a31_data; + a2_data_delayed_2 <= a2_data_delayed_1; + a3_data_delayed_2 <= a3_data_delayed_1; + a3_data_delayed_3 <= a3_data_delayed_2; + a4_data_delayed_2 <= a4_data_delayed_1; + a4_data_delayed_3 <= a4_data_delayed_2; + a4_data_delayed_4 <= a4_data_delayed_3; + a5_data_delayed_2 <= a5_data_delayed_1; + a5_data_delayed_3 <= a5_data_delayed_2; + a5_data_delayed_4 <= a5_data_delayed_3; + a5_data_delayed_5 <= a5_data_delayed_4; + a6_data_delayed_2 <= a6_data_delayed_1; + a6_data_delayed_3 <= a6_data_delayed_2; + a6_data_delayed_4 <= a6_data_delayed_3; + a6_data_delayed_5 <= a6_data_delayed_4; + a6_data_delayed_6 <= a6_data_delayed_5; + a7_data_delayed_2 <= a7_data_delayed_1; + a7_data_delayed_3 <= a7_data_delayed_2; + a7_data_delayed_4 <= a7_data_delayed_3; + a7_data_delayed_5 <= a7_data_delayed_4; + a7_data_delayed_6 <= a7_data_delayed_5; + a7_data_delayed_7 <= a7_data_delayed_6; + a8_data_delayed_2 <= a8_data_delayed_1; + a8_data_delayed_3 <= a8_data_delayed_2; + a8_data_delayed_4 <= a8_data_delayed_3; + a8_data_delayed_5 <= a8_data_delayed_4; + a8_data_delayed_6 <= a8_data_delayed_5; + a8_data_delayed_7 <= a8_data_delayed_6; + a8_data_delayed_8 <= a8_data_delayed_7; + a9_data_delayed_2 <= a9_data_delayed_1; + a9_data_delayed_3 <= a9_data_delayed_2; + a9_data_delayed_4 <= a9_data_delayed_3; + a9_data_delayed_5 <= a9_data_delayed_4; + a9_data_delayed_6 <= a9_data_delayed_5; + a9_data_delayed_7 <= a9_data_delayed_6; + a9_data_delayed_8 <= a9_data_delayed_7; + a9_data_delayed_9 <= a9_data_delayed_8; + a10_data_delayed_2 <= a10_data_delayed_1; + a10_data_delayed_3 <= a10_data_delayed_2; + a10_data_delayed_4 <= a10_data_delayed_3; + a10_data_delayed_5 <= a10_data_delayed_4; + a10_data_delayed_6 <= a10_data_delayed_5; + a10_data_delayed_7 <= a10_data_delayed_6; + a10_data_delayed_8 <= a10_data_delayed_7; + a10_data_delayed_9 <= a10_data_delayed_8; + a10_data_delayed_10 <= a10_data_delayed_9; + a11_data_delayed_2 <= a11_data_delayed_1; + a11_data_delayed_3 <= a11_data_delayed_2; + a11_data_delayed_4 <= a11_data_delayed_3; + a11_data_delayed_5 <= a11_data_delayed_4; + a11_data_delayed_6 <= a11_data_delayed_5; + a11_data_delayed_7 <= a11_data_delayed_6; + a11_data_delayed_8 <= a11_data_delayed_7; + a11_data_delayed_9 <= a11_data_delayed_8; + a11_data_delayed_10 <= a11_data_delayed_9; + a11_data_delayed_11 <= a11_data_delayed_10; + a12_data_delayed_2 <= a12_data_delayed_1; + a12_data_delayed_3 <= a12_data_delayed_2; + a12_data_delayed_4 <= a12_data_delayed_3; + a12_data_delayed_5 <= a12_data_delayed_4; + a12_data_delayed_6 <= a12_data_delayed_5; + a12_data_delayed_7 <= a12_data_delayed_6; + a12_data_delayed_8 <= a12_data_delayed_7; + a12_data_delayed_9 <= a12_data_delayed_8; + a12_data_delayed_10 <= a12_data_delayed_9; + a12_data_delayed_11 <= a12_data_delayed_10; + a12_data_delayed_12 <= a12_data_delayed_11; + a13_data_delayed_2 <= a13_data_delayed_1; + a13_data_delayed_3 <= a13_data_delayed_2; + a13_data_delayed_4 <= a13_data_delayed_3; + a13_data_delayed_5 <= a13_data_delayed_4; + a13_data_delayed_6 <= a13_data_delayed_5; + a13_data_delayed_7 <= a13_data_delayed_6; + a13_data_delayed_8 <= a13_data_delayed_7; + a13_data_delayed_9 <= a13_data_delayed_8; + a13_data_delayed_10 <= a13_data_delayed_9; + a13_data_delayed_11 <= a13_data_delayed_10; + a13_data_delayed_12 <= a13_data_delayed_11; + a13_data_delayed_13 <= a13_data_delayed_12; + a14_data_delayed_2 <= a14_data_delayed_1; + a14_data_delayed_3 <= a14_data_delayed_2; + a14_data_delayed_4 <= a14_data_delayed_3; + a14_data_delayed_5 <= a14_data_delayed_4; + a14_data_delayed_6 <= a14_data_delayed_5; + a14_data_delayed_7 <= a14_data_delayed_6; + a14_data_delayed_8 <= a14_data_delayed_7; + a14_data_delayed_9 <= a14_data_delayed_8; + a14_data_delayed_10 <= a14_data_delayed_9; + a14_data_delayed_11 <= a14_data_delayed_10; + a14_data_delayed_12 <= a14_data_delayed_11; + a14_data_delayed_13 <= a14_data_delayed_12; + a14_data_delayed_14 <= a14_data_delayed_13; + a15_data_delayed_2 <= a15_data_delayed_1; + a15_data_delayed_3 <= a15_data_delayed_2; + a15_data_delayed_4 <= a15_data_delayed_3; + a15_data_delayed_5 <= a15_data_delayed_4; + a15_data_delayed_6 <= a15_data_delayed_5; + a15_data_delayed_7 <= a15_data_delayed_6; + a15_data_delayed_8 <= a15_data_delayed_7; + a15_data_delayed_9 <= a15_data_delayed_8; + a15_data_delayed_10 <= a15_data_delayed_9; + a15_data_delayed_11 <= a15_data_delayed_10; + a15_data_delayed_12 <= a15_data_delayed_11; + a15_data_delayed_13 <= a15_data_delayed_12; + a15_data_delayed_14 <= a15_data_delayed_13; + a15_data_delayed_15 <= a15_data_delayed_14; + a16_data_delayed_2 <= a16_data_delayed_1; + a16_data_delayed_3 <= a16_data_delayed_2; + a16_data_delayed_4 <= a16_data_delayed_3; + a16_data_delayed_5 <= a16_data_delayed_4; + a16_data_delayed_6 <= a16_data_delayed_5; + a16_data_delayed_7 <= a16_data_delayed_6; + a16_data_delayed_8 <= a16_data_delayed_7; + a16_data_delayed_9 <= a16_data_delayed_8; + a16_data_delayed_10 <= a16_data_delayed_9; + a16_data_delayed_11 <= a16_data_delayed_10; + a16_data_delayed_12 <= a16_data_delayed_11; + a16_data_delayed_13 <= a16_data_delayed_12; + a16_data_delayed_14 <= a16_data_delayed_13; + a16_data_delayed_15 <= a16_data_delayed_14; + a16_data_delayed_16 <= a16_data_delayed_15; + a17_data_delayed_2 <= a17_data_delayed_1; + a17_data_delayed_3 <= a17_data_delayed_2; + a17_data_delayed_4 <= a17_data_delayed_3; + a17_data_delayed_5 <= a17_data_delayed_4; + a17_data_delayed_6 <= a17_data_delayed_5; + a17_data_delayed_7 <= a17_data_delayed_6; + a17_data_delayed_8 <= a17_data_delayed_7; + a17_data_delayed_9 <= a17_data_delayed_8; + a17_data_delayed_10 <= a17_data_delayed_9; + a17_data_delayed_11 <= a17_data_delayed_10; + a17_data_delayed_12 <= a17_data_delayed_11; + a17_data_delayed_13 <= a17_data_delayed_12; + a17_data_delayed_14 <= a17_data_delayed_13; + a17_data_delayed_15 <= a17_data_delayed_14; + a17_data_delayed_16 <= a17_data_delayed_15; + a17_data_delayed_17 <= a17_data_delayed_16; + a18_data_delayed_2 <= a18_data_delayed_1; + a18_data_delayed_3 <= a18_data_delayed_2; + a18_data_delayed_4 <= a18_data_delayed_3; + a18_data_delayed_5 <= a18_data_delayed_4; + a18_data_delayed_6 <= a18_data_delayed_5; + a18_data_delayed_7 <= a18_data_delayed_6; + a18_data_delayed_8 <= a18_data_delayed_7; + a18_data_delayed_9 <= a18_data_delayed_8; + a18_data_delayed_10 <= a18_data_delayed_9; + a18_data_delayed_11 <= a18_data_delayed_10; + a18_data_delayed_12 <= a18_data_delayed_11; + a18_data_delayed_13 <= a18_data_delayed_12; + a18_data_delayed_14 <= a18_data_delayed_13; + a18_data_delayed_15 <= a18_data_delayed_14; + a18_data_delayed_16 <= a18_data_delayed_15; + a18_data_delayed_17 <= a18_data_delayed_16; + a18_data_delayed_18 <= a18_data_delayed_17; + a19_data_delayed_2 <= a19_data_delayed_1; + a19_data_delayed_3 <= a19_data_delayed_2; + a19_data_delayed_4 <= a19_data_delayed_3; + a19_data_delayed_5 <= a19_data_delayed_4; + a19_data_delayed_6 <= a19_data_delayed_5; + a19_data_delayed_7 <= a19_data_delayed_6; + a19_data_delayed_8 <= a19_data_delayed_7; + a19_data_delayed_9 <= a19_data_delayed_8; + a19_data_delayed_10 <= a19_data_delayed_9; + a19_data_delayed_11 <= a19_data_delayed_10; + a19_data_delayed_12 <= a19_data_delayed_11; + a19_data_delayed_13 <= a19_data_delayed_12; + a19_data_delayed_14 <= a19_data_delayed_13; + a19_data_delayed_15 <= a19_data_delayed_14; + a19_data_delayed_16 <= a19_data_delayed_15; + a19_data_delayed_17 <= a19_data_delayed_16; + a19_data_delayed_18 <= a19_data_delayed_17; + a19_data_delayed_19 <= a19_data_delayed_18; + a20_data_delayed_2 <= a20_data_delayed_1; + a20_data_delayed_3 <= a20_data_delayed_2; + a20_data_delayed_4 <= a20_data_delayed_3; + a20_data_delayed_5 <= a20_data_delayed_4; + a20_data_delayed_6 <= a20_data_delayed_5; + a20_data_delayed_7 <= a20_data_delayed_6; + a20_data_delayed_8 <= a20_data_delayed_7; + a20_data_delayed_9 <= a20_data_delayed_8; + a20_data_delayed_10 <= a20_data_delayed_9; + a20_data_delayed_11 <= a20_data_delayed_10; + a20_data_delayed_12 <= a20_data_delayed_11; + a20_data_delayed_13 <= a20_data_delayed_12; + a20_data_delayed_14 <= a20_data_delayed_13; + a20_data_delayed_15 <= a20_data_delayed_14; + a20_data_delayed_16 <= a20_data_delayed_15; + a20_data_delayed_17 <= a20_data_delayed_16; + a20_data_delayed_18 <= a20_data_delayed_17; + a20_data_delayed_19 <= a20_data_delayed_18; + a20_data_delayed_20 <= a20_data_delayed_19; + a21_data_delayed_2 <= a21_data_delayed_1; + a21_data_delayed_3 <= a21_data_delayed_2; + a21_data_delayed_4 <= a21_data_delayed_3; + a21_data_delayed_5 <= a21_data_delayed_4; + a21_data_delayed_6 <= a21_data_delayed_5; + a21_data_delayed_7 <= a21_data_delayed_6; + a21_data_delayed_8 <= a21_data_delayed_7; + a21_data_delayed_9 <= a21_data_delayed_8; + a21_data_delayed_10 <= a21_data_delayed_9; + a21_data_delayed_11 <= a21_data_delayed_10; + a21_data_delayed_12 <= a21_data_delayed_11; + a21_data_delayed_13 <= a21_data_delayed_12; + a21_data_delayed_14 <= a21_data_delayed_13; + a21_data_delayed_15 <= a21_data_delayed_14; + a21_data_delayed_16 <= a21_data_delayed_15; + a21_data_delayed_17 <= a21_data_delayed_16; + a21_data_delayed_18 <= a21_data_delayed_17; + a21_data_delayed_19 <= a21_data_delayed_18; + a21_data_delayed_20 <= a21_data_delayed_19; + a21_data_delayed_21 <= a21_data_delayed_20; + a22_data_delayed_2 <= a22_data_delayed_1; + a22_data_delayed_3 <= a22_data_delayed_2; + a22_data_delayed_4 <= a22_data_delayed_3; + a22_data_delayed_5 <= a22_data_delayed_4; + a22_data_delayed_6 <= a22_data_delayed_5; + a22_data_delayed_7 <= a22_data_delayed_6; + a22_data_delayed_8 <= a22_data_delayed_7; + a22_data_delayed_9 <= a22_data_delayed_8; + a22_data_delayed_10 <= a22_data_delayed_9; + a22_data_delayed_11 <= a22_data_delayed_10; + a22_data_delayed_12 <= a22_data_delayed_11; + a22_data_delayed_13 <= a22_data_delayed_12; + a22_data_delayed_14 <= a22_data_delayed_13; + a22_data_delayed_15 <= a22_data_delayed_14; + a22_data_delayed_16 <= a22_data_delayed_15; + a22_data_delayed_17 <= a22_data_delayed_16; + a22_data_delayed_18 <= a22_data_delayed_17; + a22_data_delayed_19 <= a22_data_delayed_18; + a22_data_delayed_20 <= a22_data_delayed_19; + a22_data_delayed_21 <= a22_data_delayed_20; + a22_data_delayed_22 <= a22_data_delayed_21; + a23_data_delayed_2 <= a23_data_delayed_1; + a23_data_delayed_3 <= a23_data_delayed_2; + a23_data_delayed_4 <= a23_data_delayed_3; + a23_data_delayed_5 <= a23_data_delayed_4; + a23_data_delayed_6 <= a23_data_delayed_5; + a23_data_delayed_7 <= a23_data_delayed_6; + a23_data_delayed_8 <= a23_data_delayed_7; + a23_data_delayed_9 <= a23_data_delayed_8; + a23_data_delayed_10 <= a23_data_delayed_9; + a23_data_delayed_11 <= a23_data_delayed_10; + a23_data_delayed_12 <= a23_data_delayed_11; + a23_data_delayed_13 <= a23_data_delayed_12; + a23_data_delayed_14 <= a23_data_delayed_13; + a23_data_delayed_15 <= a23_data_delayed_14; + a23_data_delayed_16 <= a23_data_delayed_15; + a23_data_delayed_17 <= a23_data_delayed_16; + a23_data_delayed_18 <= a23_data_delayed_17; + a23_data_delayed_19 <= a23_data_delayed_18; + a23_data_delayed_20 <= a23_data_delayed_19; + a23_data_delayed_21 <= a23_data_delayed_20; + a23_data_delayed_22 <= a23_data_delayed_21; + a23_data_delayed_23 <= a23_data_delayed_22; + a24_data_delayed_2 <= a24_data_delayed_1; + a24_data_delayed_3 <= a24_data_delayed_2; + a24_data_delayed_4 <= a24_data_delayed_3; + a24_data_delayed_5 <= a24_data_delayed_4; + a24_data_delayed_6 <= a24_data_delayed_5; + a24_data_delayed_7 <= a24_data_delayed_6; + a24_data_delayed_8 <= a24_data_delayed_7; + a24_data_delayed_9 <= a24_data_delayed_8; + a24_data_delayed_10 <= a24_data_delayed_9; + a24_data_delayed_11 <= a24_data_delayed_10; + a24_data_delayed_12 <= a24_data_delayed_11; + a24_data_delayed_13 <= a24_data_delayed_12; + a24_data_delayed_14 <= a24_data_delayed_13; + a24_data_delayed_15 <= a24_data_delayed_14; + a24_data_delayed_16 <= a24_data_delayed_15; + a24_data_delayed_17 <= a24_data_delayed_16; + a24_data_delayed_18 <= a24_data_delayed_17; + a24_data_delayed_19 <= a24_data_delayed_18; + a24_data_delayed_20 <= a24_data_delayed_19; + a24_data_delayed_21 <= a24_data_delayed_20; + a24_data_delayed_22 <= a24_data_delayed_21; + a24_data_delayed_23 <= a24_data_delayed_22; + a24_data_delayed_24 <= a24_data_delayed_23; + a25_data_delayed_2 <= a25_data_delayed_1; + a25_data_delayed_3 <= a25_data_delayed_2; + a25_data_delayed_4 <= a25_data_delayed_3; + a25_data_delayed_5 <= a25_data_delayed_4; + a25_data_delayed_6 <= a25_data_delayed_5; + a25_data_delayed_7 <= a25_data_delayed_6; + a25_data_delayed_8 <= a25_data_delayed_7; + a25_data_delayed_9 <= a25_data_delayed_8; + a25_data_delayed_10 <= a25_data_delayed_9; + a25_data_delayed_11 <= a25_data_delayed_10; + a25_data_delayed_12 <= a25_data_delayed_11; + a25_data_delayed_13 <= a25_data_delayed_12; + a25_data_delayed_14 <= a25_data_delayed_13; + a25_data_delayed_15 <= a25_data_delayed_14; + a25_data_delayed_16 <= a25_data_delayed_15; + a25_data_delayed_17 <= a25_data_delayed_16; + a25_data_delayed_18 <= a25_data_delayed_17; + a25_data_delayed_19 <= a25_data_delayed_18; + a25_data_delayed_20 <= a25_data_delayed_19; + a25_data_delayed_21 <= a25_data_delayed_20; + a25_data_delayed_22 <= a25_data_delayed_21; + a25_data_delayed_23 <= a25_data_delayed_22; + a25_data_delayed_24 <= a25_data_delayed_23; + a25_data_delayed_25 <= a25_data_delayed_24; + a26_data_delayed_2 <= a26_data_delayed_1; + a26_data_delayed_3 <= a26_data_delayed_2; + a26_data_delayed_4 <= a26_data_delayed_3; + a26_data_delayed_5 <= a26_data_delayed_4; + a26_data_delayed_6 <= a26_data_delayed_5; + a26_data_delayed_7 <= a26_data_delayed_6; + a26_data_delayed_8 <= a26_data_delayed_7; + a26_data_delayed_9 <= a26_data_delayed_8; + a26_data_delayed_10 <= a26_data_delayed_9; + a26_data_delayed_11 <= a26_data_delayed_10; + a26_data_delayed_12 <= a26_data_delayed_11; + a26_data_delayed_13 <= a26_data_delayed_12; + a26_data_delayed_14 <= a26_data_delayed_13; + a26_data_delayed_15 <= a26_data_delayed_14; + a26_data_delayed_16 <= a26_data_delayed_15; + a26_data_delayed_17 <= a26_data_delayed_16; + a26_data_delayed_18 <= a26_data_delayed_17; + a26_data_delayed_19 <= a26_data_delayed_18; + a26_data_delayed_20 <= a26_data_delayed_19; + a26_data_delayed_21 <= a26_data_delayed_20; + a26_data_delayed_22 <= a26_data_delayed_21; + a26_data_delayed_23 <= a26_data_delayed_22; + a26_data_delayed_24 <= a26_data_delayed_23; + a26_data_delayed_25 <= a26_data_delayed_24; + a26_data_delayed_26 <= a26_data_delayed_25; + a27_data_delayed_2 <= a27_data_delayed_1; + a27_data_delayed_3 <= a27_data_delayed_2; + a27_data_delayed_4 <= a27_data_delayed_3; + a27_data_delayed_5 <= a27_data_delayed_4; + a27_data_delayed_6 <= a27_data_delayed_5; + a27_data_delayed_7 <= a27_data_delayed_6; + a27_data_delayed_8 <= a27_data_delayed_7; + a27_data_delayed_9 <= a27_data_delayed_8; + a27_data_delayed_10 <= a27_data_delayed_9; + a27_data_delayed_11 <= a27_data_delayed_10; + a27_data_delayed_12 <= a27_data_delayed_11; + a27_data_delayed_13 <= a27_data_delayed_12; + a27_data_delayed_14 <= a27_data_delayed_13; + a27_data_delayed_15 <= a27_data_delayed_14; + a27_data_delayed_16 <= a27_data_delayed_15; + a27_data_delayed_17 <= a27_data_delayed_16; + a27_data_delayed_18 <= a27_data_delayed_17; + a27_data_delayed_19 <= a27_data_delayed_18; + a27_data_delayed_20 <= a27_data_delayed_19; + a27_data_delayed_21 <= a27_data_delayed_20; + a27_data_delayed_22 <= a27_data_delayed_21; + a27_data_delayed_23 <= a27_data_delayed_22; + a27_data_delayed_24 <= a27_data_delayed_23; + a27_data_delayed_25 <= a27_data_delayed_24; + a27_data_delayed_26 <= a27_data_delayed_25; + a27_data_delayed_27 <= a27_data_delayed_26; + a28_data_delayed_2 <= a28_data_delayed_1; + a28_data_delayed_3 <= a28_data_delayed_2; + a28_data_delayed_4 <= a28_data_delayed_3; + a28_data_delayed_5 <= a28_data_delayed_4; + a28_data_delayed_6 <= a28_data_delayed_5; + a28_data_delayed_7 <= a28_data_delayed_6; + a28_data_delayed_8 <= a28_data_delayed_7; + a28_data_delayed_9 <= a28_data_delayed_8; + a28_data_delayed_10 <= a28_data_delayed_9; + a28_data_delayed_11 <= a28_data_delayed_10; + a28_data_delayed_12 <= a28_data_delayed_11; + a28_data_delayed_13 <= a28_data_delayed_12; + a28_data_delayed_14 <= a28_data_delayed_13; + a28_data_delayed_15 <= a28_data_delayed_14; + a28_data_delayed_16 <= a28_data_delayed_15; + a28_data_delayed_17 <= a28_data_delayed_16; + a28_data_delayed_18 <= a28_data_delayed_17; + a28_data_delayed_19 <= a28_data_delayed_18; + a28_data_delayed_20 <= a28_data_delayed_19; + a28_data_delayed_21 <= a28_data_delayed_20; + a28_data_delayed_22 <= a28_data_delayed_21; + a28_data_delayed_23 <= a28_data_delayed_22; + a28_data_delayed_24 <= a28_data_delayed_23; + a28_data_delayed_25 <= a28_data_delayed_24; + a28_data_delayed_26 <= a28_data_delayed_25; + a28_data_delayed_27 <= a28_data_delayed_26; + a28_data_delayed_28 <= a28_data_delayed_27; + a29_data_delayed_2 <= a29_data_delayed_1; + a29_data_delayed_3 <= a29_data_delayed_2; + a29_data_delayed_4 <= a29_data_delayed_3; + a29_data_delayed_5 <= a29_data_delayed_4; + a29_data_delayed_6 <= a29_data_delayed_5; + a29_data_delayed_7 <= a29_data_delayed_6; + a29_data_delayed_8 <= a29_data_delayed_7; + a29_data_delayed_9 <= a29_data_delayed_8; + a29_data_delayed_10 <= a29_data_delayed_9; + a29_data_delayed_11 <= a29_data_delayed_10; + a29_data_delayed_12 <= a29_data_delayed_11; + a29_data_delayed_13 <= a29_data_delayed_12; + a29_data_delayed_14 <= a29_data_delayed_13; + a29_data_delayed_15 <= a29_data_delayed_14; + a29_data_delayed_16 <= a29_data_delayed_15; + a29_data_delayed_17 <= a29_data_delayed_16; + a29_data_delayed_18 <= a29_data_delayed_17; + a29_data_delayed_19 <= a29_data_delayed_18; + a29_data_delayed_20 <= a29_data_delayed_19; + a29_data_delayed_21 <= a29_data_delayed_20; + a29_data_delayed_22 <= a29_data_delayed_21; + a29_data_delayed_23 <= a29_data_delayed_22; + a29_data_delayed_24 <= a29_data_delayed_23; + a29_data_delayed_25 <= a29_data_delayed_24; + a29_data_delayed_26 <= a29_data_delayed_25; + a29_data_delayed_27 <= a29_data_delayed_26; + a29_data_delayed_28 <= a29_data_delayed_27; + a29_data_delayed_29 <= a29_data_delayed_28; + a30_data_delayed_2 <= a30_data_delayed_1; + a30_data_delayed_3 <= a30_data_delayed_2; + a30_data_delayed_4 <= a30_data_delayed_3; + a30_data_delayed_5 <= a30_data_delayed_4; + a30_data_delayed_6 <= a30_data_delayed_5; + a30_data_delayed_7 <= a30_data_delayed_6; + a30_data_delayed_8 <= a30_data_delayed_7; + a30_data_delayed_9 <= a30_data_delayed_8; + a30_data_delayed_10 <= a30_data_delayed_9; + a30_data_delayed_11 <= a30_data_delayed_10; + a30_data_delayed_12 <= a30_data_delayed_11; + a30_data_delayed_13 <= a30_data_delayed_12; + a30_data_delayed_14 <= a30_data_delayed_13; + a30_data_delayed_15 <= a30_data_delayed_14; + a30_data_delayed_16 <= a30_data_delayed_15; + a30_data_delayed_17 <= a30_data_delayed_16; + a30_data_delayed_18 <= a30_data_delayed_17; + a30_data_delayed_19 <= a30_data_delayed_18; + a30_data_delayed_20 <= a30_data_delayed_19; + a30_data_delayed_21 <= a30_data_delayed_20; + a30_data_delayed_22 <= a30_data_delayed_21; + a30_data_delayed_23 <= a30_data_delayed_22; + a30_data_delayed_24 <= a30_data_delayed_23; + a30_data_delayed_25 <= a30_data_delayed_24; + a30_data_delayed_26 <= a30_data_delayed_25; + a30_data_delayed_27 <= a30_data_delayed_26; + a30_data_delayed_28 <= a30_data_delayed_27; + a30_data_delayed_29 <= a30_data_delayed_28; + a30_data_delayed_30 <= a30_data_delayed_29; + a31_data_delayed_2 <= a31_data_delayed_1; + a31_data_delayed_3 <= a31_data_delayed_2; + a31_data_delayed_4 <= a31_data_delayed_3; + a31_data_delayed_5 <= a31_data_delayed_4; + a31_data_delayed_6 <= a31_data_delayed_5; + a31_data_delayed_7 <= a31_data_delayed_6; + a31_data_delayed_8 <= a31_data_delayed_7; + a31_data_delayed_9 <= a31_data_delayed_8; + a31_data_delayed_10 <= a31_data_delayed_9; + a31_data_delayed_11 <= a31_data_delayed_10; + a31_data_delayed_12 <= a31_data_delayed_11; + a31_data_delayed_13 <= a31_data_delayed_12; + a31_data_delayed_14 <= a31_data_delayed_13; + a31_data_delayed_15 <= a31_data_delayed_14; + a31_data_delayed_16 <= a31_data_delayed_15; + a31_data_delayed_17 <= a31_data_delayed_16; + a31_data_delayed_18 <= a31_data_delayed_17; + a31_data_delayed_19 <= a31_data_delayed_18; + a31_data_delayed_20 <= a31_data_delayed_19; + a31_data_delayed_21 <= a31_data_delayed_20; + a31_data_delayed_22 <= a31_data_delayed_21; + a31_data_delayed_23 <= a31_data_delayed_22; + a31_data_delayed_24 <= a31_data_delayed_23; + a31_data_delayed_25 <= a31_data_delayed_24; + a31_data_delayed_26 <= a31_data_delayed_25; + a31_data_delayed_27 <= a31_data_delayed_26; + a31_data_delayed_28 <= a31_data_delayed_27; + a31_data_delayed_29 <= a31_data_delayed_28; + a31_data_delayed_30 <= a31_data_delayed_29; + a31_data_delayed_31 <= a31_data_delayed_30; + + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM B +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] b_addr; +reg b_mem_access; //flag that tells whether the matmul is trying to access memory or not +always @(posedge clk) begin + //else if (clk_cnt >= b_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + + if ((reset || ~start_mat_mul) || (clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + b_addr <= address_mat_b - address_stride_b; + + b_mem_access <= 0; + end + //else if ((clk_cnt >= b_loc*`MAT_MUL_SIZE) && (clk_cnt < b_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + + else if ((clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (b_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + b_addr <= b_addr + address_stride_b; + + b_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM B +////////////////////////////////////////////////////////////////////////// +reg [7:0] b_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + b_mem_access_counter <= 0; + end + else if (b_mem_access == 1) begin + b_mem_access_counter <= b_mem_access_counter + 1; + end + else begin + b_mem_access_counter <= 0; + end +end + +wire b_data_valid; //flag that tells whether the data from memory is valid +assign b_data_valid = + ((validity_mask_b_rows[0]==1'b0 && b_mem_access_counter==1) || + (validity_mask_b_rows[1]==1'b0 && b_mem_access_counter==2) || + (validity_mask_b_rows[2]==1'b0 && b_mem_access_counter==3) || + (validity_mask_b_rows[3]==1'b0 && b_mem_access_counter==4) || + (validity_mask_b_rows[4]==1'b0 && b_mem_access_counter==5) || + (validity_mask_b_rows[5]==1'b0 && b_mem_access_counter==6) || + (validity_mask_b_rows[6]==1'b0 && b_mem_access_counter==7) || + (validity_mask_b_rows[7]==1'b0 && b_mem_access_counter==8) || + (validity_mask_b_rows[8]==1'b0 && b_mem_access_counter==9) || + (validity_mask_b_rows[9]==1'b0 && b_mem_access_counter==10) || + (validity_mask_b_rows[10]==1'b0 && b_mem_access_counter==11) || + (validity_mask_b_rows[11]==1'b0 && b_mem_access_counter==12) || + (validity_mask_b_rows[12]==1'b0 && b_mem_access_counter==13) || + (validity_mask_b_rows[13]==1'b0 && b_mem_access_counter==14) || + (validity_mask_b_rows[14]==1'b0 && b_mem_access_counter==15) || + (validity_mask_b_rows[15]==1'b0 && b_mem_access_counter==16) || + (validity_mask_b_rows[16]==1'b0 && b_mem_access_counter==17) || + (validity_mask_b_rows[17]==1'b0 && b_mem_access_counter==18) || + (validity_mask_b_rows[18]==1'b0 && b_mem_access_counter==19) || + (validity_mask_b_rows[19]==1'b0 && b_mem_access_counter==20) || + (validity_mask_b_rows[20]==1'b0 && b_mem_access_counter==21) || + (validity_mask_b_rows[21]==1'b0 && b_mem_access_counter==22) || + (validity_mask_b_rows[22]==1'b0 && b_mem_access_counter==23) || + (validity_mask_b_rows[23]==1'b0 && b_mem_access_counter==24) || + (validity_mask_b_rows[24]==1'b0 && b_mem_access_counter==25) || + (validity_mask_b_rows[25]==1'b0 && b_mem_access_counter==26) || + (validity_mask_b_rows[26]==1'b0 && b_mem_access_counter==27) || + (validity_mask_b_rows[27]==1'b0 && b_mem_access_counter==28) || + (validity_mask_b_rows[28]==1'b0 && b_mem_access_counter==29) || + (validity_mask_b_rows[29]==1'b0 && b_mem_access_counter==30) || + (validity_mask_b_rows[30]==1'b0 && b_mem_access_counter==31) || + (validity_mask_b_rows[31]==1'b0 && b_mem_access_counter==32)) ? + + 1'b0 : (b_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM B (systolic data setup) +////////////////////////////////////////////////////////////////////////// +assign b0_data = b_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[0]}}; +assign b1_data = b_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[1]}}; +assign b2_data = b_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[2]}}; +assign b3_data = b_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[3]}}; +assign b4_data = b_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[4]}}; +assign b5_data = b_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[5]}}; +assign b6_data = b_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[6]}}; +assign b7_data = b_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[7]}}; +assign b8_data = b_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[8]}}; +assign b9_data = b_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[9]}}; +assign b10_data = b_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[10]}}; +assign b11_data = b_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[11]}}; +assign b12_data = b_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[12]}}; +assign b13_data = b_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[13]}}; +assign b14_data = b_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[14]}}; +assign b15_data = b_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[15]}}; +assign b16_data = b_data[17*`DWIDTH-1:16*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[16]}}; +assign b17_data = b_data[18*`DWIDTH-1:17*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[17]}}; +assign b18_data = b_data[19*`DWIDTH-1:18*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[18]}}; +assign b19_data = b_data[20*`DWIDTH-1:19*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[19]}}; +assign b20_data = b_data[21*`DWIDTH-1:20*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[20]}}; +assign b21_data = b_data[22*`DWIDTH-1:21*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[21]}}; +assign b22_data = b_data[23*`DWIDTH-1:22*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[22]}}; +assign b23_data = b_data[24*`DWIDTH-1:23*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[23]}}; +assign b24_data = b_data[25*`DWIDTH-1:24*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[24]}}; +assign b25_data = b_data[26*`DWIDTH-1:25*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[25]}}; +assign b26_data = b_data[27*`DWIDTH-1:26*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[26]}}; +assign b27_data = b_data[28*`DWIDTH-1:27*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[27]}}; +assign b28_data = b_data[29*`DWIDTH-1:28*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[28]}}; +assign b29_data = b_data[30*`DWIDTH-1:29*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[29]}}; +assign b30_data = b_data[31*`DWIDTH-1:30*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[30]}}; +assign b31_data = b_data[32*`DWIDTH-1:31*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[31]}}; + +reg [`DWIDTH-1:0] b1_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_1; +reg [`DWIDTH-1:0] b3_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_1; +reg [`DWIDTH-1:0] b4_data_delayed_2; +reg [`DWIDTH-1:0] b4_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_1; +reg [`DWIDTH-1:0] b5_data_delayed_2; +reg [`DWIDTH-1:0] b5_data_delayed_3; +reg [`DWIDTH-1:0] b5_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_1; +reg [`DWIDTH-1:0] b6_data_delayed_2; +reg [`DWIDTH-1:0] b6_data_delayed_3; +reg [`DWIDTH-1:0] b6_data_delayed_4; +reg [`DWIDTH-1:0] b6_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_1; +reg [`DWIDTH-1:0] b7_data_delayed_2; +reg [`DWIDTH-1:0] b7_data_delayed_3; +reg [`DWIDTH-1:0] b7_data_delayed_4; +reg [`DWIDTH-1:0] b7_data_delayed_5; +reg [`DWIDTH-1:0] b7_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_1; +reg [`DWIDTH-1:0] b8_data_delayed_2; +reg [`DWIDTH-1:0] b8_data_delayed_3; +reg [`DWIDTH-1:0] b8_data_delayed_4; +reg [`DWIDTH-1:0] b8_data_delayed_5; +reg [`DWIDTH-1:0] b8_data_delayed_6; +reg [`DWIDTH-1:0] b8_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_1; +reg [`DWIDTH-1:0] b9_data_delayed_2; +reg [`DWIDTH-1:0] b9_data_delayed_3; +reg [`DWIDTH-1:0] b9_data_delayed_4; +reg [`DWIDTH-1:0] b9_data_delayed_5; +reg [`DWIDTH-1:0] b9_data_delayed_6; +reg [`DWIDTH-1:0] b9_data_delayed_7; +reg [`DWIDTH-1:0] b9_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_1; +reg [`DWIDTH-1:0] b10_data_delayed_2; +reg [`DWIDTH-1:0] b10_data_delayed_3; +reg [`DWIDTH-1:0] b10_data_delayed_4; +reg [`DWIDTH-1:0] b10_data_delayed_5; +reg [`DWIDTH-1:0] b10_data_delayed_6; +reg [`DWIDTH-1:0] b10_data_delayed_7; +reg [`DWIDTH-1:0] b10_data_delayed_8; +reg [`DWIDTH-1:0] b10_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_1; +reg [`DWIDTH-1:0] b11_data_delayed_2; +reg [`DWIDTH-1:0] b11_data_delayed_3; +reg [`DWIDTH-1:0] b11_data_delayed_4; +reg [`DWIDTH-1:0] b11_data_delayed_5; +reg [`DWIDTH-1:0] b11_data_delayed_6; +reg [`DWIDTH-1:0] b11_data_delayed_7; +reg [`DWIDTH-1:0] b11_data_delayed_8; +reg [`DWIDTH-1:0] b11_data_delayed_9; +reg [`DWIDTH-1:0] b11_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_1; +reg [`DWIDTH-1:0] b12_data_delayed_2; +reg [`DWIDTH-1:0] b12_data_delayed_3; +reg [`DWIDTH-1:0] b12_data_delayed_4; +reg [`DWIDTH-1:0] b12_data_delayed_5; +reg [`DWIDTH-1:0] b12_data_delayed_6; +reg [`DWIDTH-1:0] b12_data_delayed_7; +reg [`DWIDTH-1:0] b12_data_delayed_8; +reg [`DWIDTH-1:0] b12_data_delayed_9; +reg [`DWIDTH-1:0] b12_data_delayed_10; +reg [`DWIDTH-1:0] b12_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_1; +reg [`DWIDTH-1:0] b13_data_delayed_2; +reg [`DWIDTH-1:0] b13_data_delayed_3; +reg [`DWIDTH-1:0] b13_data_delayed_4; +reg [`DWIDTH-1:0] b13_data_delayed_5; +reg [`DWIDTH-1:0] b13_data_delayed_6; +reg [`DWIDTH-1:0] b13_data_delayed_7; +reg [`DWIDTH-1:0] b13_data_delayed_8; +reg [`DWIDTH-1:0] b13_data_delayed_9; +reg [`DWIDTH-1:0] b13_data_delayed_10; +reg [`DWIDTH-1:0] b13_data_delayed_11; +reg [`DWIDTH-1:0] b13_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_1; +reg [`DWIDTH-1:0] b14_data_delayed_2; +reg [`DWIDTH-1:0] b14_data_delayed_3; +reg [`DWIDTH-1:0] b14_data_delayed_4; +reg [`DWIDTH-1:0] b14_data_delayed_5; +reg [`DWIDTH-1:0] b14_data_delayed_6; +reg [`DWIDTH-1:0] b14_data_delayed_7; +reg [`DWIDTH-1:0] b14_data_delayed_8; +reg [`DWIDTH-1:0] b14_data_delayed_9; +reg [`DWIDTH-1:0] b14_data_delayed_10; +reg [`DWIDTH-1:0] b14_data_delayed_11; +reg [`DWIDTH-1:0] b14_data_delayed_12; +reg [`DWIDTH-1:0] b14_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_1; +reg [`DWIDTH-1:0] b15_data_delayed_2; +reg [`DWIDTH-1:0] b15_data_delayed_3; +reg [`DWIDTH-1:0] b15_data_delayed_4; +reg [`DWIDTH-1:0] b15_data_delayed_5; +reg [`DWIDTH-1:0] b15_data_delayed_6; +reg [`DWIDTH-1:0] b15_data_delayed_7; +reg [`DWIDTH-1:0] b15_data_delayed_8; +reg [`DWIDTH-1:0] b15_data_delayed_9; +reg [`DWIDTH-1:0] b15_data_delayed_10; +reg [`DWIDTH-1:0] b15_data_delayed_11; +reg [`DWIDTH-1:0] b15_data_delayed_12; +reg [`DWIDTH-1:0] b15_data_delayed_13; +reg [`DWIDTH-1:0] b15_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_15; +reg [`DWIDTH-1:0] b16_data_delayed_1; +reg [`DWIDTH-1:0] b16_data_delayed_2; +reg [`DWIDTH-1:0] b16_data_delayed_3; +reg [`DWIDTH-1:0] b16_data_delayed_4; +reg [`DWIDTH-1:0] b16_data_delayed_5; +reg [`DWIDTH-1:0] b16_data_delayed_6; +reg [`DWIDTH-1:0] b16_data_delayed_7; +reg [`DWIDTH-1:0] b16_data_delayed_8; +reg [`DWIDTH-1:0] b16_data_delayed_9; +reg [`DWIDTH-1:0] b16_data_delayed_10; +reg [`DWIDTH-1:0] b16_data_delayed_11; +reg [`DWIDTH-1:0] b16_data_delayed_12; +reg [`DWIDTH-1:0] b16_data_delayed_13; +reg [`DWIDTH-1:0] b16_data_delayed_14; +reg [`DWIDTH-1:0] b16_data_delayed_15; +reg [`DWIDTH-1:0] b16_data_delayed_16; +reg [`DWIDTH-1:0] b17_data_delayed_1; +reg [`DWIDTH-1:0] b17_data_delayed_2; +reg [`DWIDTH-1:0] b17_data_delayed_3; +reg [`DWIDTH-1:0] b17_data_delayed_4; +reg [`DWIDTH-1:0] b17_data_delayed_5; +reg [`DWIDTH-1:0] b17_data_delayed_6; +reg [`DWIDTH-1:0] b17_data_delayed_7; +reg [`DWIDTH-1:0] b17_data_delayed_8; +reg [`DWIDTH-1:0] b17_data_delayed_9; +reg [`DWIDTH-1:0] b17_data_delayed_10; +reg [`DWIDTH-1:0] b17_data_delayed_11; +reg [`DWIDTH-1:0] b17_data_delayed_12; +reg [`DWIDTH-1:0] b17_data_delayed_13; +reg [`DWIDTH-1:0] b17_data_delayed_14; +reg [`DWIDTH-1:0] b17_data_delayed_15; +reg [`DWIDTH-1:0] b17_data_delayed_16; +reg [`DWIDTH-1:0] b17_data_delayed_17; +reg [`DWIDTH-1:0] b18_data_delayed_1; +reg [`DWIDTH-1:0] b18_data_delayed_2; +reg [`DWIDTH-1:0] b18_data_delayed_3; +reg [`DWIDTH-1:0] b18_data_delayed_4; +reg [`DWIDTH-1:0] b18_data_delayed_5; +reg [`DWIDTH-1:0] b18_data_delayed_6; +reg [`DWIDTH-1:0] b18_data_delayed_7; +reg [`DWIDTH-1:0] b18_data_delayed_8; +reg [`DWIDTH-1:0] b18_data_delayed_9; +reg [`DWIDTH-1:0] b18_data_delayed_10; +reg [`DWIDTH-1:0] b18_data_delayed_11; +reg [`DWIDTH-1:0] b18_data_delayed_12; +reg [`DWIDTH-1:0] b18_data_delayed_13; +reg [`DWIDTH-1:0] b18_data_delayed_14; +reg [`DWIDTH-1:0] b18_data_delayed_15; +reg [`DWIDTH-1:0] b18_data_delayed_16; +reg [`DWIDTH-1:0] b18_data_delayed_17; +reg [`DWIDTH-1:0] b18_data_delayed_18; +reg [`DWIDTH-1:0] b19_data_delayed_1; +reg [`DWIDTH-1:0] b19_data_delayed_2; +reg [`DWIDTH-1:0] b19_data_delayed_3; +reg [`DWIDTH-1:0] b19_data_delayed_4; +reg [`DWIDTH-1:0] b19_data_delayed_5; +reg [`DWIDTH-1:0] b19_data_delayed_6; +reg [`DWIDTH-1:0] b19_data_delayed_7; +reg [`DWIDTH-1:0] b19_data_delayed_8; +reg [`DWIDTH-1:0] b19_data_delayed_9; +reg [`DWIDTH-1:0] b19_data_delayed_10; +reg [`DWIDTH-1:0] b19_data_delayed_11; +reg [`DWIDTH-1:0] b19_data_delayed_12; +reg [`DWIDTH-1:0] b19_data_delayed_13; +reg [`DWIDTH-1:0] b19_data_delayed_14; +reg [`DWIDTH-1:0] b19_data_delayed_15; +reg [`DWIDTH-1:0] b19_data_delayed_16; +reg [`DWIDTH-1:0] b19_data_delayed_17; +reg [`DWIDTH-1:0] b19_data_delayed_18; +reg [`DWIDTH-1:0] b19_data_delayed_19; +reg [`DWIDTH-1:0] b20_data_delayed_1; +reg [`DWIDTH-1:0] b20_data_delayed_2; +reg [`DWIDTH-1:0] b20_data_delayed_3; +reg [`DWIDTH-1:0] b20_data_delayed_4; +reg [`DWIDTH-1:0] b20_data_delayed_5; +reg [`DWIDTH-1:0] b20_data_delayed_6; +reg [`DWIDTH-1:0] b20_data_delayed_7; +reg [`DWIDTH-1:0] b20_data_delayed_8; +reg [`DWIDTH-1:0] b20_data_delayed_9; +reg [`DWIDTH-1:0] b20_data_delayed_10; +reg [`DWIDTH-1:0] b20_data_delayed_11; +reg [`DWIDTH-1:0] b20_data_delayed_12; +reg [`DWIDTH-1:0] b20_data_delayed_13; +reg [`DWIDTH-1:0] b20_data_delayed_14; +reg [`DWIDTH-1:0] b20_data_delayed_15; +reg [`DWIDTH-1:0] b20_data_delayed_16; +reg [`DWIDTH-1:0] b20_data_delayed_17; +reg [`DWIDTH-1:0] b20_data_delayed_18; +reg [`DWIDTH-1:0] b20_data_delayed_19; +reg [`DWIDTH-1:0] b20_data_delayed_20; +reg [`DWIDTH-1:0] b21_data_delayed_1; +reg [`DWIDTH-1:0] b21_data_delayed_2; +reg [`DWIDTH-1:0] b21_data_delayed_3; +reg [`DWIDTH-1:0] b21_data_delayed_4; +reg [`DWIDTH-1:0] b21_data_delayed_5; +reg [`DWIDTH-1:0] b21_data_delayed_6; +reg [`DWIDTH-1:0] b21_data_delayed_7; +reg [`DWIDTH-1:0] b21_data_delayed_8; +reg [`DWIDTH-1:0] b21_data_delayed_9; +reg [`DWIDTH-1:0] b21_data_delayed_10; +reg [`DWIDTH-1:0] b21_data_delayed_11; +reg [`DWIDTH-1:0] b21_data_delayed_12; +reg [`DWIDTH-1:0] b21_data_delayed_13; +reg [`DWIDTH-1:0] b21_data_delayed_14; +reg [`DWIDTH-1:0] b21_data_delayed_15; +reg [`DWIDTH-1:0] b21_data_delayed_16; +reg [`DWIDTH-1:0] b21_data_delayed_17; +reg [`DWIDTH-1:0] b21_data_delayed_18; +reg [`DWIDTH-1:0] b21_data_delayed_19; +reg [`DWIDTH-1:0] b21_data_delayed_20; +reg [`DWIDTH-1:0] b21_data_delayed_21; +reg [`DWIDTH-1:0] b22_data_delayed_1; +reg [`DWIDTH-1:0] b22_data_delayed_2; +reg [`DWIDTH-1:0] b22_data_delayed_3; +reg [`DWIDTH-1:0] b22_data_delayed_4; +reg [`DWIDTH-1:0] b22_data_delayed_5; +reg [`DWIDTH-1:0] b22_data_delayed_6; +reg [`DWIDTH-1:0] b22_data_delayed_7; +reg [`DWIDTH-1:0] b22_data_delayed_8; +reg [`DWIDTH-1:0] b22_data_delayed_9; +reg [`DWIDTH-1:0] b22_data_delayed_10; +reg [`DWIDTH-1:0] b22_data_delayed_11; +reg [`DWIDTH-1:0] b22_data_delayed_12; +reg [`DWIDTH-1:0] b22_data_delayed_13; +reg [`DWIDTH-1:0] b22_data_delayed_14; +reg [`DWIDTH-1:0] b22_data_delayed_15; +reg [`DWIDTH-1:0] b22_data_delayed_16; +reg [`DWIDTH-1:0] b22_data_delayed_17; +reg [`DWIDTH-1:0] b22_data_delayed_18; +reg [`DWIDTH-1:0] b22_data_delayed_19; +reg [`DWIDTH-1:0] b22_data_delayed_20; +reg [`DWIDTH-1:0] b22_data_delayed_21; +reg [`DWIDTH-1:0] b22_data_delayed_22; +reg [`DWIDTH-1:0] b23_data_delayed_1; +reg [`DWIDTH-1:0] b23_data_delayed_2; +reg [`DWIDTH-1:0] b23_data_delayed_3; +reg [`DWIDTH-1:0] b23_data_delayed_4; +reg [`DWIDTH-1:0] b23_data_delayed_5; +reg [`DWIDTH-1:0] b23_data_delayed_6; +reg [`DWIDTH-1:0] b23_data_delayed_7; +reg [`DWIDTH-1:0] b23_data_delayed_8; +reg [`DWIDTH-1:0] b23_data_delayed_9; +reg [`DWIDTH-1:0] b23_data_delayed_10; +reg [`DWIDTH-1:0] b23_data_delayed_11; +reg [`DWIDTH-1:0] b23_data_delayed_12; +reg [`DWIDTH-1:0] b23_data_delayed_13; +reg [`DWIDTH-1:0] b23_data_delayed_14; +reg [`DWIDTH-1:0] b23_data_delayed_15; +reg [`DWIDTH-1:0] b23_data_delayed_16; +reg [`DWIDTH-1:0] b23_data_delayed_17; +reg [`DWIDTH-1:0] b23_data_delayed_18; +reg [`DWIDTH-1:0] b23_data_delayed_19; +reg [`DWIDTH-1:0] b23_data_delayed_20; +reg [`DWIDTH-1:0] b23_data_delayed_21; +reg [`DWIDTH-1:0] b23_data_delayed_22; +reg [`DWIDTH-1:0] b23_data_delayed_23; +reg [`DWIDTH-1:0] b24_data_delayed_1; +reg [`DWIDTH-1:0] b24_data_delayed_2; +reg [`DWIDTH-1:0] b24_data_delayed_3; +reg [`DWIDTH-1:0] b24_data_delayed_4; +reg [`DWIDTH-1:0] b24_data_delayed_5; +reg [`DWIDTH-1:0] b24_data_delayed_6; +reg [`DWIDTH-1:0] b24_data_delayed_7; +reg [`DWIDTH-1:0] b24_data_delayed_8; +reg [`DWIDTH-1:0] b24_data_delayed_9; +reg [`DWIDTH-1:0] b24_data_delayed_10; +reg [`DWIDTH-1:0] b24_data_delayed_11; +reg [`DWIDTH-1:0] b24_data_delayed_12; +reg [`DWIDTH-1:0] b24_data_delayed_13; +reg [`DWIDTH-1:0] b24_data_delayed_14; +reg [`DWIDTH-1:0] b24_data_delayed_15; +reg [`DWIDTH-1:0] b24_data_delayed_16; +reg [`DWIDTH-1:0] b24_data_delayed_17; +reg [`DWIDTH-1:0] b24_data_delayed_18; +reg [`DWIDTH-1:0] b24_data_delayed_19; +reg [`DWIDTH-1:0] b24_data_delayed_20; +reg [`DWIDTH-1:0] b24_data_delayed_21; +reg [`DWIDTH-1:0] b24_data_delayed_22; +reg [`DWIDTH-1:0] b24_data_delayed_23; +reg [`DWIDTH-1:0] b24_data_delayed_24; +reg [`DWIDTH-1:0] b25_data_delayed_1; +reg [`DWIDTH-1:0] b25_data_delayed_2; +reg [`DWIDTH-1:0] b25_data_delayed_3; +reg [`DWIDTH-1:0] b25_data_delayed_4; +reg [`DWIDTH-1:0] b25_data_delayed_5; +reg [`DWIDTH-1:0] b25_data_delayed_6; +reg [`DWIDTH-1:0] b25_data_delayed_7; +reg [`DWIDTH-1:0] b25_data_delayed_8; +reg [`DWIDTH-1:0] b25_data_delayed_9; +reg [`DWIDTH-1:0] b25_data_delayed_10; +reg [`DWIDTH-1:0] b25_data_delayed_11; +reg [`DWIDTH-1:0] b25_data_delayed_12; +reg [`DWIDTH-1:0] b25_data_delayed_13; +reg [`DWIDTH-1:0] b25_data_delayed_14; +reg [`DWIDTH-1:0] b25_data_delayed_15; +reg [`DWIDTH-1:0] b25_data_delayed_16; +reg [`DWIDTH-1:0] b25_data_delayed_17; +reg [`DWIDTH-1:0] b25_data_delayed_18; +reg [`DWIDTH-1:0] b25_data_delayed_19; +reg [`DWIDTH-1:0] b25_data_delayed_20; +reg [`DWIDTH-1:0] b25_data_delayed_21; +reg [`DWIDTH-1:0] b25_data_delayed_22; +reg [`DWIDTH-1:0] b25_data_delayed_23; +reg [`DWIDTH-1:0] b25_data_delayed_24; +reg [`DWIDTH-1:0] b25_data_delayed_25; +reg [`DWIDTH-1:0] b26_data_delayed_1; +reg [`DWIDTH-1:0] b26_data_delayed_2; +reg [`DWIDTH-1:0] b26_data_delayed_3; +reg [`DWIDTH-1:0] b26_data_delayed_4; +reg [`DWIDTH-1:0] b26_data_delayed_5; +reg [`DWIDTH-1:0] b26_data_delayed_6; +reg [`DWIDTH-1:0] b26_data_delayed_7; +reg [`DWIDTH-1:0] b26_data_delayed_8; +reg [`DWIDTH-1:0] b26_data_delayed_9; +reg [`DWIDTH-1:0] b26_data_delayed_10; +reg [`DWIDTH-1:0] b26_data_delayed_11; +reg [`DWIDTH-1:0] b26_data_delayed_12; +reg [`DWIDTH-1:0] b26_data_delayed_13; +reg [`DWIDTH-1:0] b26_data_delayed_14; +reg [`DWIDTH-1:0] b26_data_delayed_15; +reg [`DWIDTH-1:0] b26_data_delayed_16; +reg [`DWIDTH-1:0] b26_data_delayed_17; +reg [`DWIDTH-1:0] b26_data_delayed_18; +reg [`DWIDTH-1:0] b26_data_delayed_19; +reg [`DWIDTH-1:0] b26_data_delayed_20; +reg [`DWIDTH-1:0] b26_data_delayed_21; +reg [`DWIDTH-1:0] b26_data_delayed_22; +reg [`DWIDTH-1:0] b26_data_delayed_23; +reg [`DWIDTH-1:0] b26_data_delayed_24; +reg [`DWIDTH-1:0] b26_data_delayed_25; +reg [`DWIDTH-1:0] b26_data_delayed_26; +reg [`DWIDTH-1:0] b27_data_delayed_1; +reg [`DWIDTH-1:0] b27_data_delayed_2; +reg [`DWIDTH-1:0] b27_data_delayed_3; +reg [`DWIDTH-1:0] b27_data_delayed_4; +reg [`DWIDTH-1:0] b27_data_delayed_5; +reg [`DWIDTH-1:0] b27_data_delayed_6; +reg [`DWIDTH-1:0] b27_data_delayed_7; +reg [`DWIDTH-1:0] b27_data_delayed_8; +reg [`DWIDTH-1:0] b27_data_delayed_9; +reg [`DWIDTH-1:0] b27_data_delayed_10; +reg [`DWIDTH-1:0] b27_data_delayed_11; +reg [`DWIDTH-1:0] b27_data_delayed_12; +reg [`DWIDTH-1:0] b27_data_delayed_13; +reg [`DWIDTH-1:0] b27_data_delayed_14; +reg [`DWIDTH-1:0] b27_data_delayed_15; +reg [`DWIDTH-1:0] b27_data_delayed_16; +reg [`DWIDTH-1:0] b27_data_delayed_17; +reg [`DWIDTH-1:0] b27_data_delayed_18; +reg [`DWIDTH-1:0] b27_data_delayed_19; +reg [`DWIDTH-1:0] b27_data_delayed_20; +reg [`DWIDTH-1:0] b27_data_delayed_21; +reg [`DWIDTH-1:0] b27_data_delayed_22; +reg [`DWIDTH-1:0] b27_data_delayed_23; +reg [`DWIDTH-1:0] b27_data_delayed_24; +reg [`DWIDTH-1:0] b27_data_delayed_25; +reg [`DWIDTH-1:0] b27_data_delayed_26; +reg [`DWIDTH-1:0] b27_data_delayed_27; +reg [`DWIDTH-1:0] b28_data_delayed_1; +reg [`DWIDTH-1:0] b28_data_delayed_2; +reg [`DWIDTH-1:0] b28_data_delayed_3; +reg [`DWIDTH-1:0] b28_data_delayed_4; +reg [`DWIDTH-1:0] b28_data_delayed_5; +reg [`DWIDTH-1:0] b28_data_delayed_6; +reg [`DWIDTH-1:0] b28_data_delayed_7; +reg [`DWIDTH-1:0] b28_data_delayed_8; +reg [`DWIDTH-1:0] b28_data_delayed_9; +reg [`DWIDTH-1:0] b28_data_delayed_10; +reg [`DWIDTH-1:0] b28_data_delayed_11; +reg [`DWIDTH-1:0] b28_data_delayed_12; +reg [`DWIDTH-1:0] b28_data_delayed_13; +reg [`DWIDTH-1:0] b28_data_delayed_14; +reg [`DWIDTH-1:0] b28_data_delayed_15; +reg [`DWIDTH-1:0] b28_data_delayed_16; +reg [`DWIDTH-1:0] b28_data_delayed_17; +reg [`DWIDTH-1:0] b28_data_delayed_18; +reg [`DWIDTH-1:0] b28_data_delayed_19; +reg [`DWIDTH-1:0] b28_data_delayed_20; +reg [`DWIDTH-1:0] b28_data_delayed_21; +reg [`DWIDTH-1:0] b28_data_delayed_22; +reg [`DWIDTH-1:0] b28_data_delayed_23; +reg [`DWIDTH-1:0] b28_data_delayed_24; +reg [`DWIDTH-1:0] b28_data_delayed_25; +reg [`DWIDTH-1:0] b28_data_delayed_26; +reg [`DWIDTH-1:0] b28_data_delayed_27; +reg [`DWIDTH-1:0] b28_data_delayed_28; +reg [`DWIDTH-1:0] b29_data_delayed_1; +reg [`DWIDTH-1:0] b29_data_delayed_2; +reg [`DWIDTH-1:0] b29_data_delayed_3; +reg [`DWIDTH-1:0] b29_data_delayed_4; +reg [`DWIDTH-1:0] b29_data_delayed_5; +reg [`DWIDTH-1:0] b29_data_delayed_6; +reg [`DWIDTH-1:0] b29_data_delayed_7; +reg [`DWIDTH-1:0] b29_data_delayed_8; +reg [`DWIDTH-1:0] b29_data_delayed_9; +reg [`DWIDTH-1:0] b29_data_delayed_10; +reg [`DWIDTH-1:0] b29_data_delayed_11; +reg [`DWIDTH-1:0] b29_data_delayed_12; +reg [`DWIDTH-1:0] b29_data_delayed_13; +reg [`DWIDTH-1:0] b29_data_delayed_14; +reg [`DWIDTH-1:0] b29_data_delayed_15; +reg [`DWIDTH-1:0] b29_data_delayed_16; +reg [`DWIDTH-1:0] b29_data_delayed_17; +reg [`DWIDTH-1:0] b29_data_delayed_18; +reg [`DWIDTH-1:0] b29_data_delayed_19; +reg [`DWIDTH-1:0] b29_data_delayed_20; +reg [`DWIDTH-1:0] b29_data_delayed_21; +reg [`DWIDTH-1:0] b29_data_delayed_22; +reg [`DWIDTH-1:0] b29_data_delayed_23; +reg [`DWIDTH-1:0] b29_data_delayed_24; +reg [`DWIDTH-1:0] b29_data_delayed_25; +reg [`DWIDTH-1:0] b29_data_delayed_26; +reg [`DWIDTH-1:0] b29_data_delayed_27; +reg [`DWIDTH-1:0] b29_data_delayed_28; +reg [`DWIDTH-1:0] b29_data_delayed_29; +reg [`DWIDTH-1:0] b30_data_delayed_1; +reg [`DWIDTH-1:0] b30_data_delayed_2; +reg [`DWIDTH-1:0] b30_data_delayed_3; +reg [`DWIDTH-1:0] b30_data_delayed_4; +reg [`DWIDTH-1:0] b30_data_delayed_5; +reg [`DWIDTH-1:0] b30_data_delayed_6; +reg [`DWIDTH-1:0] b30_data_delayed_7; +reg [`DWIDTH-1:0] b30_data_delayed_8; +reg [`DWIDTH-1:0] b30_data_delayed_9; +reg [`DWIDTH-1:0] b30_data_delayed_10; +reg [`DWIDTH-1:0] b30_data_delayed_11; +reg [`DWIDTH-1:0] b30_data_delayed_12; +reg [`DWIDTH-1:0] b30_data_delayed_13; +reg [`DWIDTH-1:0] b30_data_delayed_14; +reg [`DWIDTH-1:0] b30_data_delayed_15; +reg [`DWIDTH-1:0] b30_data_delayed_16; +reg [`DWIDTH-1:0] b30_data_delayed_17; +reg [`DWIDTH-1:0] b30_data_delayed_18; +reg [`DWIDTH-1:0] b30_data_delayed_19; +reg [`DWIDTH-1:0] b30_data_delayed_20; +reg [`DWIDTH-1:0] b30_data_delayed_21; +reg [`DWIDTH-1:0] b30_data_delayed_22; +reg [`DWIDTH-1:0] b30_data_delayed_23; +reg [`DWIDTH-1:0] b30_data_delayed_24; +reg [`DWIDTH-1:0] b30_data_delayed_25; +reg [`DWIDTH-1:0] b30_data_delayed_26; +reg [`DWIDTH-1:0] b30_data_delayed_27; +reg [`DWIDTH-1:0] b30_data_delayed_28; +reg [`DWIDTH-1:0] b30_data_delayed_29; +reg [`DWIDTH-1:0] b30_data_delayed_30; +reg [`DWIDTH-1:0] b31_data_delayed_1; +reg [`DWIDTH-1:0] b31_data_delayed_2; +reg [`DWIDTH-1:0] b31_data_delayed_3; +reg [`DWIDTH-1:0] b31_data_delayed_4; +reg [`DWIDTH-1:0] b31_data_delayed_5; +reg [`DWIDTH-1:0] b31_data_delayed_6; +reg [`DWIDTH-1:0] b31_data_delayed_7; +reg [`DWIDTH-1:0] b31_data_delayed_8; +reg [`DWIDTH-1:0] b31_data_delayed_9; +reg [`DWIDTH-1:0] b31_data_delayed_10; +reg [`DWIDTH-1:0] b31_data_delayed_11; +reg [`DWIDTH-1:0] b31_data_delayed_12; +reg [`DWIDTH-1:0] b31_data_delayed_13; +reg [`DWIDTH-1:0] b31_data_delayed_14; +reg [`DWIDTH-1:0] b31_data_delayed_15; +reg [`DWIDTH-1:0] b31_data_delayed_16; +reg [`DWIDTH-1:0] b31_data_delayed_17; +reg [`DWIDTH-1:0] b31_data_delayed_18; +reg [`DWIDTH-1:0] b31_data_delayed_19; +reg [`DWIDTH-1:0] b31_data_delayed_20; +reg [`DWIDTH-1:0] b31_data_delayed_21; +reg [`DWIDTH-1:0] b31_data_delayed_22; +reg [`DWIDTH-1:0] b31_data_delayed_23; +reg [`DWIDTH-1:0] b31_data_delayed_24; +reg [`DWIDTH-1:0] b31_data_delayed_25; +reg [`DWIDTH-1:0] b31_data_delayed_26; +reg [`DWIDTH-1:0] b31_data_delayed_27; +reg [`DWIDTH-1:0] b31_data_delayed_28; +reg [`DWIDTH-1:0] b31_data_delayed_29; +reg [`DWIDTH-1:0] b31_data_delayed_30; +reg [`DWIDTH-1:0] b31_data_delayed_31; + + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + b1_data_delayed_1 <= 0; + b2_data_delayed_1 <= 0; + b2_data_delayed_2 <= 0; + b3_data_delayed_1 <= 0; + b3_data_delayed_2 <= 0; + b3_data_delayed_3 <= 0; + b4_data_delayed_1 <= 0; + b4_data_delayed_2 <= 0; + b4_data_delayed_3 <= 0; + b4_data_delayed_4 <= 0; + b5_data_delayed_1 <= 0; + b5_data_delayed_2 <= 0; + b5_data_delayed_3 <= 0; + b5_data_delayed_4 <= 0; + b5_data_delayed_5 <= 0; + b6_data_delayed_1 <= 0; + b6_data_delayed_2 <= 0; + b6_data_delayed_3 <= 0; + b6_data_delayed_4 <= 0; + b6_data_delayed_5 <= 0; + b6_data_delayed_6 <= 0; + b7_data_delayed_1 <= 0; + b7_data_delayed_2 <= 0; + b7_data_delayed_3 <= 0; + b7_data_delayed_4 <= 0; + b7_data_delayed_5 <= 0; + b7_data_delayed_6 <= 0; + b7_data_delayed_7 <= 0; + b8_data_delayed_1 <= 0; + b8_data_delayed_2 <= 0; + b8_data_delayed_3 <= 0; + b8_data_delayed_4 <= 0; + b8_data_delayed_5 <= 0; + b8_data_delayed_6 <= 0; + b8_data_delayed_7 <= 0; + b8_data_delayed_8 <= 0; + b9_data_delayed_1 <= 0; + b9_data_delayed_2 <= 0; + b9_data_delayed_3 <= 0; + b9_data_delayed_4 <= 0; + b9_data_delayed_5 <= 0; + b9_data_delayed_6 <= 0; + b9_data_delayed_7 <= 0; + b9_data_delayed_8 <= 0; + b9_data_delayed_9 <= 0; + b10_data_delayed_1 <= 0; + b10_data_delayed_2 <= 0; + b10_data_delayed_3 <= 0; + b10_data_delayed_4 <= 0; + b10_data_delayed_5 <= 0; + b10_data_delayed_6 <= 0; + b10_data_delayed_7 <= 0; + b10_data_delayed_8 <= 0; + b10_data_delayed_9 <= 0; + b10_data_delayed_10 <= 0; + b11_data_delayed_1 <= 0; + b11_data_delayed_2 <= 0; + b11_data_delayed_3 <= 0; + b11_data_delayed_4 <= 0; + b11_data_delayed_5 <= 0; + b11_data_delayed_6 <= 0; + b11_data_delayed_7 <= 0; + b11_data_delayed_8 <= 0; + b11_data_delayed_9 <= 0; + b11_data_delayed_10 <= 0; + b11_data_delayed_11 <= 0; + b12_data_delayed_1 <= 0; + b12_data_delayed_2 <= 0; + b12_data_delayed_3 <= 0; + b12_data_delayed_4 <= 0; + b12_data_delayed_5 <= 0; + b12_data_delayed_6 <= 0; + b12_data_delayed_7 <= 0; + b12_data_delayed_8 <= 0; + b12_data_delayed_9 <= 0; + b12_data_delayed_10 <= 0; + b12_data_delayed_11 <= 0; + b12_data_delayed_12 <= 0; + b13_data_delayed_1 <= 0; + b13_data_delayed_2 <= 0; + b13_data_delayed_3 <= 0; + b13_data_delayed_4 <= 0; + b13_data_delayed_5 <= 0; + b13_data_delayed_6 <= 0; + b13_data_delayed_7 <= 0; + b13_data_delayed_8 <= 0; + b13_data_delayed_9 <= 0; + b13_data_delayed_10 <= 0; + b13_data_delayed_11 <= 0; + b13_data_delayed_12 <= 0; + b13_data_delayed_13 <= 0; + b14_data_delayed_1 <= 0; + b14_data_delayed_2 <= 0; + b14_data_delayed_3 <= 0; + b14_data_delayed_4 <= 0; + b14_data_delayed_5 <= 0; + b14_data_delayed_6 <= 0; + b14_data_delayed_7 <= 0; + b14_data_delayed_8 <= 0; + b14_data_delayed_9 <= 0; + b14_data_delayed_10 <= 0; + b14_data_delayed_11 <= 0; + b14_data_delayed_12 <= 0; + b14_data_delayed_13 <= 0; + b14_data_delayed_14 <= 0; + b15_data_delayed_1 <= 0; + b15_data_delayed_2 <= 0; + b15_data_delayed_3 <= 0; + b15_data_delayed_4 <= 0; + b15_data_delayed_5 <= 0; + b15_data_delayed_6 <= 0; + b15_data_delayed_7 <= 0; + b15_data_delayed_8 <= 0; + b15_data_delayed_9 <= 0; + b15_data_delayed_10 <= 0; + b15_data_delayed_11 <= 0; + b15_data_delayed_12 <= 0; + b15_data_delayed_13 <= 0; + b15_data_delayed_14 <= 0; + b15_data_delayed_15 <= 0; + b16_data_delayed_1 <= 0; + b16_data_delayed_2 <= 0; + b16_data_delayed_3 <= 0; + b16_data_delayed_4 <= 0; + b16_data_delayed_5 <= 0; + b16_data_delayed_6 <= 0; + b16_data_delayed_7 <= 0; + b16_data_delayed_8 <= 0; + b16_data_delayed_9 <= 0; + b16_data_delayed_10 <= 0; + b16_data_delayed_11 <= 0; + b16_data_delayed_12 <= 0; + b16_data_delayed_13 <= 0; + b16_data_delayed_14 <= 0; + b16_data_delayed_15 <= 0; + b16_data_delayed_16 <= 0; + b17_data_delayed_1 <= 0; + b17_data_delayed_2 <= 0; + b17_data_delayed_3 <= 0; + b17_data_delayed_4 <= 0; + b17_data_delayed_5 <= 0; + b17_data_delayed_6 <= 0; + b17_data_delayed_7 <= 0; + b17_data_delayed_8 <= 0; + b17_data_delayed_9 <= 0; + b17_data_delayed_10 <= 0; + b17_data_delayed_11 <= 0; + b17_data_delayed_12 <= 0; + b17_data_delayed_13 <= 0; + b17_data_delayed_14 <= 0; + b17_data_delayed_15 <= 0; + b17_data_delayed_16 <= 0; + b17_data_delayed_17 <= 0; + b18_data_delayed_1 <= 0; + b18_data_delayed_2 <= 0; + b18_data_delayed_3 <= 0; + b18_data_delayed_4 <= 0; + b18_data_delayed_5 <= 0; + b18_data_delayed_6 <= 0; + b18_data_delayed_7 <= 0; + b18_data_delayed_8 <= 0; + b18_data_delayed_9 <= 0; + b18_data_delayed_10 <= 0; + b18_data_delayed_11 <= 0; + b18_data_delayed_12 <= 0; + b18_data_delayed_13 <= 0; + b18_data_delayed_14 <= 0; + b18_data_delayed_15 <= 0; + b18_data_delayed_16 <= 0; + b18_data_delayed_17 <= 0; + b18_data_delayed_18 <= 0; + b19_data_delayed_1 <= 0; + b19_data_delayed_2 <= 0; + b19_data_delayed_3 <= 0; + b19_data_delayed_4 <= 0; + b19_data_delayed_5 <= 0; + b19_data_delayed_6 <= 0; + b19_data_delayed_7 <= 0; + b19_data_delayed_8 <= 0; + b19_data_delayed_9 <= 0; + b19_data_delayed_10 <= 0; + b19_data_delayed_11 <= 0; + b19_data_delayed_12 <= 0; + b19_data_delayed_13 <= 0; + b19_data_delayed_14 <= 0; + b19_data_delayed_15 <= 0; + b19_data_delayed_16 <= 0; + b19_data_delayed_17 <= 0; + b19_data_delayed_18 <= 0; + b19_data_delayed_19 <= 0; + b20_data_delayed_1 <= 0; + b20_data_delayed_2 <= 0; + b20_data_delayed_3 <= 0; + b20_data_delayed_4 <= 0; + b20_data_delayed_5 <= 0; + b20_data_delayed_6 <= 0; + b20_data_delayed_7 <= 0; + b20_data_delayed_8 <= 0; + b20_data_delayed_9 <= 0; + b20_data_delayed_10 <= 0; + b20_data_delayed_11 <= 0; + b20_data_delayed_12 <= 0; + b20_data_delayed_13 <= 0; + b20_data_delayed_14 <= 0; + b20_data_delayed_15 <= 0; + b20_data_delayed_16 <= 0; + b20_data_delayed_17 <= 0; + b20_data_delayed_18 <= 0; + b20_data_delayed_19 <= 0; + b20_data_delayed_20 <= 0; + b21_data_delayed_1 <= 0; + b21_data_delayed_2 <= 0; + b21_data_delayed_3 <= 0; + b21_data_delayed_4 <= 0; + b21_data_delayed_5 <= 0; + b21_data_delayed_6 <= 0; + b21_data_delayed_7 <= 0; + b21_data_delayed_8 <= 0; + b21_data_delayed_9 <= 0; + b21_data_delayed_10 <= 0; + b21_data_delayed_11 <= 0; + b21_data_delayed_12 <= 0; + b21_data_delayed_13 <= 0; + b21_data_delayed_14 <= 0; + b21_data_delayed_15 <= 0; + b21_data_delayed_16 <= 0; + b21_data_delayed_17 <= 0; + b21_data_delayed_18 <= 0; + b21_data_delayed_19 <= 0; + b21_data_delayed_20 <= 0; + b21_data_delayed_21 <= 0; + b22_data_delayed_1 <= 0; + b22_data_delayed_2 <= 0; + b22_data_delayed_3 <= 0; + b22_data_delayed_4 <= 0; + b22_data_delayed_5 <= 0; + b22_data_delayed_6 <= 0; + b22_data_delayed_7 <= 0; + b22_data_delayed_8 <= 0; + b22_data_delayed_9 <= 0; + b22_data_delayed_10 <= 0; + b22_data_delayed_11 <= 0; + b22_data_delayed_12 <= 0; + b22_data_delayed_13 <= 0; + b22_data_delayed_14 <= 0; + b22_data_delayed_15 <= 0; + b22_data_delayed_16 <= 0; + b22_data_delayed_17 <= 0; + b22_data_delayed_18 <= 0; + b22_data_delayed_19 <= 0; + b22_data_delayed_20 <= 0; + b22_data_delayed_21 <= 0; + b22_data_delayed_22 <= 0; + b23_data_delayed_1 <= 0; + b23_data_delayed_2 <= 0; + b23_data_delayed_3 <= 0; + b23_data_delayed_4 <= 0; + b23_data_delayed_5 <= 0; + b23_data_delayed_6 <= 0; + b23_data_delayed_7 <= 0; + b23_data_delayed_8 <= 0; + b23_data_delayed_9 <= 0; + b23_data_delayed_10 <= 0; + b23_data_delayed_11 <= 0; + b23_data_delayed_12 <= 0; + b23_data_delayed_13 <= 0; + b23_data_delayed_14 <= 0; + b23_data_delayed_15 <= 0; + b23_data_delayed_16 <= 0; + b23_data_delayed_17 <= 0; + b23_data_delayed_18 <= 0; + b23_data_delayed_19 <= 0; + b23_data_delayed_20 <= 0; + b23_data_delayed_21 <= 0; + b23_data_delayed_22 <= 0; + b23_data_delayed_23 <= 0; + b24_data_delayed_1 <= 0; + b24_data_delayed_2 <= 0; + b24_data_delayed_3 <= 0; + b24_data_delayed_4 <= 0; + b24_data_delayed_5 <= 0; + b24_data_delayed_6 <= 0; + b24_data_delayed_7 <= 0; + b24_data_delayed_8 <= 0; + b24_data_delayed_9 <= 0; + b24_data_delayed_10 <= 0; + b24_data_delayed_11 <= 0; + b24_data_delayed_12 <= 0; + b24_data_delayed_13 <= 0; + b24_data_delayed_14 <= 0; + b24_data_delayed_15 <= 0; + b24_data_delayed_16 <= 0; + b24_data_delayed_17 <= 0; + b24_data_delayed_18 <= 0; + b24_data_delayed_19 <= 0; + b24_data_delayed_20 <= 0; + b24_data_delayed_21 <= 0; + b24_data_delayed_22 <= 0; + b24_data_delayed_23 <= 0; + b24_data_delayed_24 <= 0; + b25_data_delayed_1 <= 0; + b25_data_delayed_2 <= 0; + b25_data_delayed_3 <= 0; + b25_data_delayed_4 <= 0; + b25_data_delayed_5 <= 0; + b25_data_delayed_6 <= 0; + b25_data_delayed_7 <= 0; + b25_data_delayed_8 <= 0; + b25_data_delayed_9 <= 0; + b25_data_delayed_10 <= 0; + b25_data_delayed_11 <= 0; + b25_data_delayed_12 <= 0; + b25_data_delayed_13 <= 0; + b25_data_delayed_14 <= 0; + b25_data_delayed_15 <= 0; + b25_data_delayed_16 <= 0; + b25_data_delayed_17 <= 0; + b25_data_delayed_18 <= 0; + b25_data_delayed_19 <= 0; + b25_data_delayed_20 <= 0; + b25_data_delayed_21 <= 0; + b25_data_delayed_22 <= 0; + b25_data_delayed_23 <= 0; + b25_data_delayed_24 <= 0; + b25_data_delayed_25 <= 0; + b26_data_delayed_1 <= 0; + b26_data_delayed_2 <= 0; + b26_data_delayed_3 <= 0; + b26_data_delayed_4 <= 0; + b26_data_delayed_5 <= 0; + b26_data_delayed_6 <= 0; + b26_data_delayed_7 <= 0; + b26_data_delayed_8 <= 0; + b26_data_delayed_9 <= 0; + b26_data_delayed_10 <= 0; + b26_data_delayed_11 <= 0; + b26_data_delayed_12 <= 0; + b26_data_delayed_13 <= 0; + b26_data_delayed_14 <= 0; + b26_data_delayed_15 <= 0; + b26_data_delayed_16 <= 0; + b26_data_delayed_17 <= 0; + b26_data_delayed_18 <= 0; + b26_data_delayed_19 <= 0; + b26_data_delayed_20 <= 0; + b26_data_delayed_21 <= 0; + b26_data_delayed_22 <= 0; + b26_data_delayed_23 <= 0; + b26_data_delayed_24 <= 0; + b26_data_delayed_25 <= 0; + b26_data_delayed_26 <= 0; + b27_data_delayed_1 <= 0; + b27_data_delayed_2 <= 0; + b27_data_delayed_3 <= 0; + b27_data_delayed_4 <= 0; + b27_data_delayed_5 <= 0; + b27_data_delayed_6 <= 0; + b27_data_delayed_7 <= 0; + b27_data_delayed_8 <= 0; + b27_data_delayed_9 <= 0; + b27_data_delayed_10 <= 0; + b27_data_delayed_11 <= 0; + b27_data_delayed_12 <= 0; + b27_data_delayed_13 <= 0; + b27_data_delayed_14 <= 0; + b27_data_delayed_15 <= 0; + b27_data_delayed_16 <= 0; + b27_data_delayed_17 <= 0; + b27_data_delayed_18 <= 0; + b27_data_delayed_19 <= 0; + b27_data_delayed_20 <= 0; + b27_data_delayed_21 <= 0; + b27_data_delayed_22 <= 0; + b27_data_delayed_23 <= 0; + b27_data_delayed_24 <= 0; + b27_data_delayed_25 <= 0; + b27_data_delayed_26 <= 0; + b27_data_delayed_27 <= 0; + b28_data_delayed_1 <= 0; + b28_data_delayed_2 <= 0; + b28_data_delayed_3 <= 0; + b28_data_delayed_4 <= 0; + b28_data_delayed_5 <= 0; + b28_data_delayed_6 <= 0; + b28_data_delayed_7 <= 0; + b28_data_delayed_8 <= 0; + b28_data_delayed_9 <= 0; + b28_data_delayed_10 <= 0; + b28_data_delayed_11 <= 0; + b28_data_delayed_12 <= 0; + b28_data_delayed_13 <= 0; + b28_data_delayed_14 <= 0; + b28_data_delayed_15 <= 0; + b28_data_delayed_16 <= 0; + b28_data_delayed_17 <= 0; + b28_data_delayed_18 <= 0; + b28_data_delayed_19 <= 0; + b28_data_delayed_20 <= 0; + b28_data_delayed_21 <= 0; + b28_data_delayed_22 <= 0; + b28_data_delayed_23 <= 0; + b28_data_delayed_24 <= 0; + b28_data_delayed_25 <= 0; + b28_data_delayed_26 <= 0; + b28_data_delayed_27 <= 0; + b28_data_delayed_28 <= 0; + b29_data_delayed_1 <= 0; + b29_data_delayed_2 <= 0; + b29_data_delayed_3 <= 0; + b29_data_delayed_4 <= 0; + b29_data_delayed_5 <= 0; + b29_data_delayed_6 <= 0; + b29_data_delayed_7 <= 0; + b29_data_delayed_8 <= 0; + b29_data_delayed_9 <= 0; + b29_data_delayed_10 <= 0; + b29_data_delayed_11 <= 0; + b29_data_delayed_12 <= 0; + b29_data_delayed_13 <= 0; + b29_data_delayed_14 <= 0; + b29_data_delayed_15 <= 0; + b29_data_delayed_16 <= 0; + b29_data_delayed_17 <= 0; + b29_data_delayed_18 <= 0; + b29_data_delayed_19 <= 0; + b29_data_delayed_20 <= 0; + b29_data_delayed_21 <= 0; + b29_data_delayed_22 <= 0; + b29_data_delayed_23 <= 0; + b29_data_delayed_24 <= 0; + b29_data_delayed_25 <= 0; + b29_data_delayed_26 <= 0; + b29_data_delayed_27 <= 0; + b29_data_delayed_28 <= 0; + b29_data_delayed_29 <= 0; + b30_data_delayed_1 <= 0; + b30_data_delayed_2 <= 0; + b30_data_delayed_3 <= 0; + b30_data_delayed_4 <= 0; + b30_data_delayed_5 <= 0; + b30_data_delayed_6 <= 0; + b30_data_delayed_7 <= 0; + b30_data_delayed_8 <= 0; + b30_data_delayed_9 <= 0; + b30_data_delayed_10 <= 0; + b30_data_delayed_11 <= 0; + b30_data_delayed_12 <= 0; + b30_data_delayed_13 <= 0; + b30_data_delayed_14 <= 0; + b30_data_delayed_15 <= 0; + b30_data_delayed_16 <= 0; + b30_data_delayed_17 <= 0; + b30_data_delayed_18 <= 0; + b30_data_delayed_19 <= 0; + b30_data_delayed_20 <= 0; + b30_data_delayed_21 <= 0; + b30_data_delayed_22 <= 0; + b30_data_delayed_23 <= 0; + b30_data_delayed_24 <= 0; + b30_data_delayed_25 <= 0; + b30_data_delayed_26 <= 0; + b30_data_delayed_27 <= 0; + b30_data_delayed_28 <= 0; + b30_data_delayed_29 <= 0; + b30_data_delayed_30 <= 0; + b31_data_delayed_1 <= 0; + b31_data_delayed_2 <= 0; + b31_data_delayed_3 <= 0; + b31_data_delayed_4 <= 0; + b31_data_delayed_5 <= 0; + b31_data_delayed_6 <= 0; + b31_data_delayed_7 <= 0; + b31_data_delayed_8 <= 0; + b31_data_delayed_9 <= 0; + b31_data_delayed_10 <= 0; + b31_data_delayed_11 <= 0; + b31_data_delayed_12 <= 0; + b31_data_delayed_13 <= 0; + b31_data_delayed_14 <= 0; + b31_data_delayed_15 <= 0; + b31_data_delayed_16 <= 0; + b31_data_delayed_17 <= 0; + b31_data_delayed_18 <= 0; + b31_data_delayed_19 <= 0; + b31_data_delayed_20 <= 0; + b31_data_delayed_21 <= 0; + b31_data_delayed_22 <= 0; + b31_data_delayed_23 <= 0; + b31_data_delayed_24 <= 0; + b31_data_delayed_25 <= 0; + b31_data_delayed_26 <= 0; + b31_data_delayed_27 <= 0; + b31_data_delayed_28 <= 0; + b31_data_delayed_29 <= 0; + b31_data_delayed_30 <= 0; + b31_data_delayed_31 <= 0; + + end + else begin + b1_data_delayed_1 <= b1_data; + b2_data_delayed_1 <= b2_data; + b3_data_delayed_1 <= b3_data; + b4_data_delayed_1 <= b4_data; + b5_data_delayed_1 <= b5_data; + b6_data_delayed_1 <= b6_data; + b7_data_delayed_1 <= b7_data; + b8_data_delayed_1 <= b8_data; + b9_data_delayed_1 <= b9_data; + b10_data_delayed_1 <= b10_data; + b11_data_delayed_1 <= b11_data; + b12_data_delayed_1 <= b12_data; + b13_data_delayed_1 <= b13_data; + b14_data_delayed_1 <= b14_data; + b15_data_delayed_1 <= b15_data; + b16_data_delayed_1 <= b16_data; + b17_data_delayed_1 <= b17_data; + b18_data_delayed_1 <= b18_data; + b19_data_delayed_1 <= b19_data; + b20_data_delayed_1 <= b20_data; + b21_data_delayed_1 <= b21_data; + b22_data_delayed_1 <= b22_data; + b23_data_delayed_1 <= b23_data; + b24_data_delayed_1 <= b24_data; + b25_data_delayed_1 <= b25_data; + b26_data_delayed_1 <= b26_data; + b27_data_delayed_1 <= b27_data; + b28_data_delayed_1 <= b28_data; + b29_data_delayed_1 <= b29_data; + b30_data_delayed_1 <= b30_data; + b31_data_delayed_1 <= b31_data; + b2_data_delayed_2 <= b2_data_delayed_1; + b3_data_delayed_2 <= b3_data_delayed_1; + b3_data_delayed_3 <= b3_data_delayed_2; + b4_data_delayed_2 <= b4_data_delayed_1; + b4_data_delayed_3 <= b4_data_delayed_2; + b4_data_delayed_4 <= b4_data_delayed_3; + b5_data_delayed_2 <= b5_data_delayed_1; + b5_data_delayed_3 <= b5_data_delayed_2; + b5_data_delayed_4 <= b5_data_delayed_3; + b5_data_delayed_5 <= b5_data_delayed_4; + b6_data_delayed_2 <= b6_data_delayed_1; + b6_data_delayed_3 <= b6_data_delayed_2; + b6_data_delayed_4 <= b6_data_delayed_3; + b6_data_delayed_5 <= b6_data_delayed_4; + b6_data_delayed_6 <= b6_data_delayed_5; + b7_data_delayed_2 <= b7_data_delayed_1; + b7_data_delayed_3 <= b7_data_delayed_2; + b7_data_delayed_4 <= b7_data_delayed_3; + b7_data_delayed_5 <= b7_data_delayed_4; + b7_data_delayed_6 <= b7_data_delayed_5; + b7_data_delayed_7 <= b7_data_delayed_6; + b8_data_delayed_2 <= b8_data_delayed_1; + b8_data_delayed_3 <= b8_data_delayed_2; + b8_data_delayed_4 <= b8_data_delayed_3; + b8_data_delayed_5 <= b8_data_delayed_4; + b8_data_delayed_6 <= b8_data_delayed_5; + b8_data_delayed_7 <= b8_data_delayed_6; + b8_data_delayed_8 <= b8_data_delayed_7; + b9_data_delayed_2 <= b9_data_delayed_1; + b9_data_delayed_3 <= b9_data_delayed_2; + b9_data_delayed_4 <= b9_data_delayed_3; + b9_data_delayed_5 <= b9_data_delayed_4; + b9_data_delayed_6 <= b9_data_delayed_5; + b9_data_delayed_7 <= b9_data_delayed_6; + b9_data_delayed_8 <= b9_data_delayed_7; + b9_data_delayed_9 <= b9_data_delayed_8; + b10_data_delayed_2 <= b10_data_delayed_1; + b10_data_delayed_3 <= b10_data_delayed_2; + b10_data_delayed_4 <= b10_data_delayed_3; + b10_data_delayed_5 <= b10_data_delayed_4; + b10_data_delayed_6 <= b10_data_delayed_5; + b10_data_delayed_7 <= b10_data_delayed_6; + b10_data_delayed_8 <= b10_data_delayed_7; + b10_data_delayed_9 <= b10_data_delayed_8; + b10_data_delayed_10 <= b10_data_delayed_9; + b11_data_delayed_2 <= b11_data_delayed_1; + b11_data_delayed_3 <= b11_data_delayed_2; + b11_data_delayed_4 <= b11_data_delayed_3; + b11_data_delayed_5 <= b11_data_delayed_4; + b11_data_delayed_6 <= b11_data_delayed_5; + b11_data_delayed_7 <= b11_data_delayed_6; + b11_data_delayed_8 <= b11_data_delayed_7; + b11_data_delayed_9 <= b11_data_delayed_8; + b11_data_delayed_10 <= b11_data_delayed_9; + b11_data_delayed_11 <= b11_data_delayed_10; + b12_data_delayed_2 <= b12_data_delayed_1; + b12_data_delayed_3 <= b12_data_delayed_2; + b12_data_delayed_4 <= b12_data_delayed_3; + b12_data_delayed_5 <= b12_data_delayed_4; + b12_data_delayed_6 <= b12_data_delayed_5; + b12_data_delayed_7 <= b12_data_delayed_6; + b12_data_delayed_8 <= b12_data_delayed_7; + b12_data_delayed_9 <= b12_data_delayed_8; + b12_data_delayed_10 <= b12_data_delayed_9; + b12_data_delayed_11 <= b12_data_delayed_10; + b12_data_delayed_12 <= b12_data_delayed_11; + b13_data_delayed_2 <= b13_data_delayed_1; + b13_data_delayed_3 <= b13_data_delayed_2; + b13_data_delayed_4 <= b13_data_delayed_3; + b13_data_delayed_5 <= b13_data_delayed_4; + b13_data_delayed_6 <= b13_data_delayed_5; + b13_data_delayed_7 <= b13_data_delayed_6; + b13_data_delayed_8 <= b13_data_delayed_7; + b13_data_delayed_9 <= b13_data_delayed_8; + b13_data_delayed_10 <= b13_data_delayed_9; + b13_data_delayed_11 <= b13_data_delayed_10; + b13_data_delayed_12 <= b13_data_delayed_11; + b13_data_delayed_13 <= b13_data_delayed_12; + b14_data_delayed_2 <= b14_data_delayed_1; + b14_data_delayed_3 <= b14_data_delayed_2; + b14_data_delayed_4 <= b14_data_delayed_3; + b14_data_delayed_5 <= b14_data_delayed_4; + b14_data_delayed_6 <= b14_data_delayed_5; + b14_data_delayed_7 <= b14_data_delayed_6; + b14_data_delayed_8 <= b14_data_delayed_7; + b14_data_delayed_9 <= b14_data_delayed_8; + b14_data_delayed_10 <= b14_data_delayed_9; + b14_data_delayed_11 <= b14_data_delayed_10; + b14_data_delayed_12 <= b14_data_delayed_11; + b14_data_delayed_13 <= b14_data_delayed_12; + b14_data_delayed_14 <= b14_data_delayed_13; + b15_data_delayed_2 <= b15_data_delayed_1; + b15_data_delayed_3 <= b15_data_delayed_2; + b15_data_delayed_4 <= b15_data_delayed_3; + b15_data_delayed_5 <= b15_data_delayed_4; + b15_data_delayed_6 <= b15_data_delayed_5; + b15_data_delayed_7 <= b15_data_delayed_6; + b15_data_delayed_8 <= b15_data_delayed_7; + b15_data_delayed_9 <= b15_data_delayed_8; + b15_data_delayed_10 <= b15_data_delayed_9; + b15_data_delayed_11 <= b15_data_delayed_10; + b15_data_delayed_12 <= b15_data_delayed_11; + b15_data_delayed_13 <= b15_data_delayed_12; + b15_data_delayed_14 <= b15_data_delayed_13; + b15_data_delayed_15 <= b15_data_delayed_14; + b16_data_delayed_2 <= b16_data_delayed_1; + b16_data_delayed_3 <= b16_data_delayed_2; + b16_data_delayed_4 <= b16_data_delayed_3; + b16_data_delayed_5 <= b16_data_delayed_4; + b16_data_delayed_6 <= b16_data_delayed_5; + b16_data_delayed_7 <= b16_data_delayed_6; + b16_data_delayed_8 <= b16_data_delayed_7; + b16_data_delayed_9 <= b16_data_delayed_8; + b16_data_delayed_10 <= b16_data_delayed_9; + b16_data_delayed_11 <= b16_data_delayed_10; + b16_data_delayed_12 <= b16_data_delayed_11; + b16_data_delayed_13 <= b16_data_delayed_12; + b16_data_delayed_14 <= b16_data_delayed_13; + b16_data_delayed_15 <= b16_data_delayed_14; + b16_data_delayed_16 <= b16_data_delayed_15; + b17_data_delayed_2 <= b17_data_delayed_1; + b17_data_delayed_3 <= b17_data_delayed_2; + b17_data_delayed_4 <= b17_data_delayed_3; + b17_data_delayed_5 <= b17_data_delayed_4; + b17_data_delayed_6 <= b17_data_delayed_5; + b17_data_delayed_7 <= b17_data_delayed_6; + b17_data_delayed_8 <= b17_data_delayed_7; + b17_data_delayed_9 <= b17_data_delayed_8; + b17_data_delayed_10 <= b17_data_delayed_9; + b17_data_delayed_11 <= b17_data_delayed_10; + b17_data_delayed_12 <= b17_data_delayed_11; + b17_data_delayed_13 <= b17_data_delayed_12; + b17_data_delayed_14 <= b17_data_delayed_13; + b17_data_delayed_15 <= b17_data_delayed_14; + b17_data_delayed_16 <= b17_data_delayed_15; + b17_data_delayed_17 <= b17_data_delayed_16; + b18_data_delayed_2 <= b18_data_delayed_1; + b18_data_delayed_3 <= b18_data_delayed_2; + b18_data_delayed_4 <= b18_data_delayed_3; + b18_data_delayed_5 <= b18_data_delayed_4; + b18_data_delayed_6 <= b18_data_delayed_5; + b18_data_delayed_7 <= b18_data_delayed_6; + b18_data_delayed_8 <= b18_data_delayed_7; + b18_data_delayed_9 <= b18_data_delayed_8; + b18_data_delayed_10 <= b18_data_delayed_9; + b18_data_delayed_11 <= b18_data_delayed_10; + b18_data_delayed_12 <= b18_data_delayed_11; + b18_data_delayed_13 <= b18_data_delayed_12; + b18_data_delayed_14 <= b18_data_delayed_13; + b18_data_delayed_15 <= b18_data_delayed_14; + b18_data_delayed_16 <= b18_data_delayed_15; + b18_data_delayed_17 <= b18_data_delayed_16; + b18_data_delayed_18 <= b18_data_delayed_17; + b19_data_delayed_2 <= b19_data_delayed_1; + b19_data_delayed_3 <= b19_data_delayed_2; + b19_data_delayed_4 <= b19_data_delayed_3; + b19_data_delayed_5 <= b19_data_delayed_4; + b19_data_delayed_6 <= b19_data_delayed_5; + b19_data_delayed_7 <= b19_data_delayed_6; + b19_data_delayed_8 <= b19_data_delayed_7; + b19_data_delayed_9 <= b19_data_delayed_8; + b19_data_delayed_10 <= b19_data_delayed_9; + b19_data_delayed_11 <= b19_data_delayed_10; + b19_data_delayed_12 <= b19_data_delayed_11; + b19_data_delayed_13 <= b19_data_delayed_12; + b19_data_delayed_14 <= b19_data_delayed_13; + b19_data_delayed_15 <= b19_data_delayed_14; + b19_data_delayed_16 <= b19_data_delayed_15; + b19_data_delayed_17 <= b19_data_delayed_16; + b19_data_delayed_18 <= b19_data_delayed_17; + b19_data_delayed_19 <= b19_data_delayed_18; + b20_data_delayed_2 <= b20_data_delayed_1; + b20_data_delayed_3 <= b20_data_delayed_2; + b20_data_delayed_4 <= b20_data_delayed_3; + b20_data_delayed_5 <= b20_data_delayed_4; + b20_data_delayed_6 <= b20_data_delayed_5; + b20_data_delayed_7 <= b20_data_delayed_6; + b20_data_delayed_8 <= b20_data_delayed_7; + b20_data_delayed_9 <= b20_data_delayed_8; + b20_data_delayed_10 <= b20_data_delayed_9; + b20_data_delayed_11 <= b20_data_delayed_10; + b20_data_delayed_12 <= b20_data_delayed_11; + b20_data_delayed_13 <= b20_data_delayed_12; + b20_data_delayed_14 <= b20_data_delayed_13; + b20_data_delayed_15 <= b20_data_delayed_14; + b20_data_delayed_16 <= b20_data_delayed_15; + b20_data_delayed_17 <= b20_data_delayed_16; + b20_data_delayed_18 <= b20_data_delayed_17; + b20_data_delayed_19 <= b20_data_delayed_18; + b20_data_delayed_20 <= b20_data_delayed_19; + b21_data_delayed_2 <= b21_data_delayed_1; + b21_data_delayed_3 <= b21_data_delayed_2; + b21_data_delayed_4 <= b21_data_delayed_3; + b21_data_delayed_5 <= b21_data_delayed_4; + b21_data_delayed_6 <= b21_data_delayed_5; + b21_data_delayed_7 <= b21_data_delayed_6; + b21_data_delayed_8 <= b21_data_delayed_7; + b21_data_delayed_9 <= b21_data_delayed_8; + b21_data_delayed_10 <= b21_data_delayed_9; + b21_data_delayed_11 <= b21_data_delayed_10; + b21_data_delayed_12 <= b21_data_delayed_11; + b21_data_delayed_13 <= b21_data_delayed_12; + b21_data_delayed_14 <= b21_data_delayed_13; + b21_data_delayed_15 <= b21_data_delayed_14; + b21_data_delayed_16 <= b21_data_delayed_15; + b21_data_delayed_17 <= b21_data_delayed_16; + b21_data_delayed_18 <= b21_data_delayed_17; + b21_data_delayed_19 <= b21_data_delayed_18; + b21_data_delayed_20 <= b21_data_delayed_19; + b21_data_delayed_21 <= b21_data_delayed_20; + b22_data_delayed_2 <= b22_data_delayed_1; + b22_data_delayed_3 <= b22_data_delayed_2; + b22_data_delayed_4 <= b22_data_delayed_3; + b22_data_delayed_5 <= b22_data_delayed_4; + b22_data_delayed_6 <= b22_data_delayed_5; + b22_data_delayed_7 <= b22_data_delayed_6; + b22_data_delayed_8 <= b22_data_delayed_7; + b22_data_delayed_9 <= b22_data_delayed_8; + b22_data_delayed_10 <= b22_data_delayed_9; + b22_data_delayed_11 <= b22_data_delayed_10; + b22_data_delayed_12 <= b22_data_delayed_11; + b22_data_delayed_13 <= b22_data_delayed_12; + b22_data_delayed_14 <= b22_data_delayed_13; + b22_data_delayed_15 <= b22_data_delayed_14; + b22_data_delayed_16 <= b22_data_delayed_15; + b22_data_delayed_17 <= b22_data_delayed_16; + b22_data_delayed_18 <= b22_data_delayed_17; + b22_data_delayed_19 <= b22_data_delayed_18; + b22_data_delayed_20 <= b22_data_delayed_19; + b22_data_delayed_21 <= b22_data_delayed_20; + b22_data_delayed_22 <= b22_data_delayed_21; + b23_data_delayed_2 <= b23_data_delayed_1; + b23_data_delayed_3 <= b23_data_delayed_2; + b23_data_delayed_4 <= b23_data_delayed_3; + b23_data_delayed_5 <= b23_data_delayed_4; + b23_data_delayed_6 <= b23_data_delayed_5; + b23_data_delayed_7 <= b23_data_delayed_6; + b23_data_delayed_8 <= b23_data_delayed_7; + b23_data_delayed_9 <= b23_data_delayed_8; + b23_data_delayed_10 <= b23_data_delayed_9; + b23_data_delayed_11 <= b23_data_delayed_10; + b23_data_delayed_12 <= b23_data_delayed_11; + b23_data_delayed_13 <= b23_data_delayed_12; + b23_data_delayed_14 <= b23_data_delayed_13; + b23_data_delayed_15 <= b23_data_delayed_14; + b23_data_delayed_16 <= b23_data_delayed_15; + b23_data_delayed_17 <= b23_data_delayed_16; + b23_data_delayed_18 <= b23_data_delayed_17; + b23_data_delayed_19 <= b23_data_delayed_18; + b23_data_delayed_20 <= b23_data_delayed_19; + b23_data_delayed_21 <= b23_data_delayed_20; + b23_data_delayed_22 <= b23_data_delayed_21; + b23_data_delayed_23 <= b23_data_delayed_22; + b24_data_delayed_2 <= b24_data_delayed_1; + b24_data_delayed_3 <= b24_data_delayed_2; + b24_data_delayed_4 <= b24_data_delayed_3; + b24_data_delayed_5 <= b24_data_delayed_4; + b24_data_delayed_6 <= b24_data_delayed_5; + b24_data_delayed_7 <= b24_data_delayed_6; + b24_data_delayed_8 <= b24_data_delayed_7; + b24_data_delayed_9 <= b24_data_delayed_8; + b24_data_delayed_10 <= b24_data_delayed_9; + b24_data_delayed_11 <= b24_data_delayed_10; + b24_data_delayed_12 <= b24_data_delayed_11; + b24_data_delayed_13 <= b24_data_delayed_12; + b24_data_delayed_14 <= b24_data_delayed_13; + b24_data_delayed_15 <= b24_data_delayed_14; + b24_data_delayed_16 <= b24_data_delayed_15; + b24_data_delayed_17 <= b24_data_delayed_16; + b24_data_delayed_18 <= b24_data_delayed_17; + b24_data_delayed_19 <= b24_data_delayed_18; + b24_data_delayed_20 <= b24_data_delayed_19; + b24_data_delayed_21 <= b24_data_delayed_20; + b24_data_delayed_22 <= b24_data_delayed_21; + b24_data_delayed_23 <= b24_data_delayed_22; + b24_data_delayed_24 <= b24_data_delayed_23; + b25_data_delayed_2 <= b25_data_delayed_1; + b25_data_delayed_3 <= b25_data_delayed_2; + b25_data_delayed_4 <= b25_data_delayed_3; + b25_data_delayed_5 <= b25_data_delayed_4; + b25_data_delayed_6 <= b25_data_delayed_5; + b25_data_delayed_7 <= b25_data_delayed_6; + b25_data_delayed_8 <= b25_data_delayed_7; + b25_data_delayed_9 <= b25_data_delayed_8; + b25_data_delayed_10 <= b25_data_delayed_9; + b25_data_delayed_11 <= b25_data_delayed_10; + b25_data_delayed_12 <= b25_data_delayed_11; + b25_data_delayed_13 <= b25_data_delayed_12; + b25_data_delayed_14 <= b25_data_delayed_13; + b25_data_delayed_15 <= b25_data_delayed_14; + b25_data_delayed_16 <= b25_data_delayed_15; + b25_data_delayed_17 <= b25_data_delayed_16; + b25_data_delayed_18 <= b25_data_delayed_17; + b25_data_delayed_19 <= b25_data_delayed_18; + b25_data_delayed_20 <= b25_data_delayed_19; + b25_data_delayed_21 <= b25_data_delayed_20; + b25_data_delayed_22 <= b25_data_delayed_21; + b25_data_delayed_23 <= b25_data_delayed_22; + b25_data_delayed_24 <= b25_data_delayed_23; + b25_data_delayed_25 <= b25_data_delayed_24; + b26_data_delayed_2 <= b26_data_delayed_1; + b26_data_delayed_3 <= b26_data_delayed_2; + b26_data_delayed_4 <= b26_data_delayed_3; + b26_data_delayed_5 <= b26_data_delayed_4; + b26_data_delayed_6 <= b26_data_delayed_5; + b26_data_delayed_7 <= b26_data_delayed_6; + b26_data_delayed_8 <= b26_data_delayed_7; + b26_data_delayed_9 <= b26_data_delayed_8; + b26_data_delayed_10 <= b26_data_delayed_9; + b26_data_delayed_11 <= b26_data_delayed_10; + b26_data_delayed_12 <= b26_data_delayed_11; + b26_data_delayed_13 <= b26_data_delayed_12; + b26_data_delayed_14 <= b26_data_delayed_13; + b26_data_delayed_15 <= b26_data_delayed_14; + b26_data_delayed_16 <= b26_data_delayed_15; + b26_data_delayed_17 <= b26_data_delayed_16; + b26_data_delayed_18 <= b26_data_delayed_17; + b26_data_delayed_19 <= b26_data_delayed_18; + b26_data_delayed_20 <= b26_data_delayed_19; + b26_data_delayed_21 <= b26_data_delayed_20; + b26_data_delayed_22 <= b26_data_delayed_21; + b26_data_delayed_23 <= b26_data_delayed_22; + b26_data_delayed_24 <= b26_data_delayed_23; + b26_data_delayed_25 <= b26_data_delayed_24; + b26_data_delayed_26 <= b26_data_delayed_25; + b27_data_delayed_2 <= b27_data_delayed_1; + b27_data_delayed_3 <= b27_data_delayed_2; + b27_data_delayed_4 <= b27_data_delayed_3; + b27_data_delayed_5 <= b27_data_delayed_4; + b27_data_delayed_6 <= b27_data_delayed_5; + b27_data_delayed_7 <= b27_data_delayed_6; + b27_data_delayed_8 <= b27_data_delayed_7; + b27_data_delayed_9 <= b27_data_delayed_8; + b27_data_delayed_10 <= b27_data_delayed_9; + b27_data_delayed_11 <= b27_data_delayed_10; + b27_data_delayed_12 <= b27_data_delayed_11; + b27_data_delayed_13 <= b27_data_delayed_12; + b27_data_delayed_14 <= b27_data_delayed_13; + b27_data_delayed_15 <= b27_data_delayed_14; + b27_data_delayed_16 <= b27_data_delayed_15; + b27_data_delayed_17 <= b27_data_delayed_16; + b27_data_delayed_18 <= b27_data_delayed_17; + b27_data_delayed_19 <= b27_data_delayed_18; + b27_data_delayed_20 <= b27_data_delayed_19; + b27_data_delayed_21 <= b27_data_delayed_20; + b27_data_delayed_22 <= b27_data_delayed_21; + b27_data_delayed_23 <= b27_data_delayed_22; + b27_data_delayed_24 <= b27_data_delayed_23; + b27_data_delayed_25 <= b27_data_delayed_24; + b27_data_delayed_26 <= b27_data_delayed_25; + b27_data_delayed_27 <= b27_data_delayed_26; + b28_data_delayed_2 <= b28_data_delayed_1; + b28_data_delayed_3 <= b28_data_delayed_2; + b28_data_delayed_4 <= b28_data_delayed_3; + b28_data_delayed_5 <= b28_data_delayed_4; + b28_data_delayed_6 <= b28_data_delayed_5; + b28_data_delayed_7 <= b28_data_delayed_6; + b28_data_delayed_8 <= b28_data_delayed_7; + b28_data_delayed_9 <= b28_data_delayed_8; + b28_data_delayed_10 <= b28_data_delayed_9; + b28_data_delayed_11 <= b28_data_delayed_10; + b28_data_delayed_12 <= b28_data_delayed_11; + b28_data_delayed_13 <= b28_data_delayed_12; + b28_data_delayed_14 <= b28_data_delayed_13; + b28_data_delayed_15 <= b28_data_delayed_14; + b28_data_delayed_16 <= b28_data_delayed_15; + b28_data_delayed_17 <= b28_data_delayed_16; + b28_data_delayed_18 <= b28_data_delayed_17; + b28_data_delayed_19 <= b28_data_delayed_18; + b28_data_delayed_20 <= b28_data_delayed_19; + b28_data_delayed_21 <= b28_data_delayed_20; + b28_data_delayed_22 <= b28_data_delayed_21; + b28_data_delayed_23 <= b28_data_delayed_22; + b28_data_delayed_24 <= b28_data_delayed_23; + b28_data_delayed_25 <= b28_data_delayed_24; + b28_data_delayed_26 <= b28_data_delayed_25; + b28_data_delayed_27 <= b28_data_delayed_26; + b28_data_delayed_28 <= b28_data_delayed_27; + b29_data_delayed_2 <= b29_data_delayed_1; + b29_data_delayed_3 <= b29_data_delayed_2; + b29_data_delayed_4 <= b29_data_delayed_3; + b29_data_delayed_5 <= b29_data_delayed_4; + b29_data_delayed_6 <= b29_data_delayed_5; + b29_data_delayed_7 <= b29_data_delayed_6; + b29_data_delayed_8 <= b29_data_delayed_7; + b29_data_delayed_9 <= b29_data_delayed_8; + b29_data_delayed_10 <= b29_data_delayed_9; + b29_data_delayed_11 <= b29_data_delayed_10; + b29_data_delayed_12 <= b29_data_delayed_11; + b29_data_delayed_13 <= b29_data_delayed_12; + b29_data_delayed_14 <= b29_data_delayed_13; + b29_data_delayed_15 <= b29_data_delayed_14; + b29_data_delayed_16 <= b29_data_delayed_15; + b29_data_delayed_17 <= b29_data_delayed_16; + b29_data_delayed_18 <= b29_data_delayed_17; + b29_data_delayed_19 <= b29_data_delayed_18; + b29_data_delayed_20 <= b29_data_delayed_19; + b29_data_delayed_21 <= b29_data_delayed_20; + b29_data_delayed_22 <= b29_data_delayed_21; + b29_data_delayed_23 <= b29_data_delayed_22; + b29_data_delayed_24 <= b29_data_delayed_23; + b29_data_delayed_25 <= b29_data_delayed_24; + b29_data_delayed_26 <= b29_data_delayed_25; + b29_data_delayed_27 <= b29_data_delayed_26; + b29_data_delayed_28 <= b29_data_delayed_27; + b29_data_delayed_29 <= b29_data_delayed_28; + b30_data_delayed_2 <= b30_data_delayed_1; + b30_data_delayed_3 <= b30_data_delayed_2; + b30_data_delayed_4 <= b30_data_delayed_3; + b30_data_delayed_5 <= b30_data_delayed_4; + b30_data_delayed_6 <= b30_data_delayed_5; + b30_data_delayed_7 <= b30_data_delayed_6; + b30_data_delayed_8 <= b30_data_delayed_7; + b30_data_delayed_9 <= b30_data_delayed_8; + b30_data_delayed_10 <= b30_data_delayed_9; + b30_data_delayed_11 <= b30_data_delayed_10; + b30_data_delayed_12 <= b30_data_delayed_11; + b30_data_delayed_13 <= b30_data_delayed_12; + b30_data_delayed_14 <= b30_data_delayed_13; + b30_data_delayed_15 <= b30_data_delayed_14; + b30_data_delayed_16 <= b30_data_delayed_15; + b30_data_delayed_17 <= b30_data_delayed_16; + b30_data_delayed_18 <= b30_data_delayed_17; + b30_data_delayed_19 <= b30_data_delayed_18; + b30_data_delayed_20 <= b30_data_delayed_19; + b30_data_delayed_21 <= b30_data_delayed_20; + b30_data_delayed_22 <= b30_data_delayed_21; + b30_data_delayed_23 <= b30_data_delayed_22; + b30_data_delayed_24 <= b30_data_delayed_23; + b30_data_delayed_25 <= b30_data_delayed_24; + b30_data_delayed_26 <= b30_data_delayed_25; + b30_data_delayed_27 <= b30_data_delayed_26; + b30_data_delayed_28 <= b30_data_delayed_27; + b30_data_delayed_29 <= b30_data_delayed_28; + b30_data_delayed_30 <= b30_data_delayed_29; + b31_data_delayed_2 <= b31_data_delayed_1; + b31_data_delayed_3 <= b31_data_delayed_2; + b31_data_delayed_4 <= b31_data_delayed_3; + b31_data_delayed_5 <= b31_data_delayed_4; + b31_data_delayed_6 <= b31_data_delayed_5; + b31_data_delayed_7 <= b31_data_delayed_6; + b31_data_delayed_8 <= b31_data_delayed_7; + b31_data_delayed_9 <= b31_data_delayed_8; + b31_data_delayed_10 <= b31_data_delayed_9; + b31_data_delayed_11 <= b31_data_delayed_10; + b31_data_delayed_12 <= b31_data_delayed_11; + b31_data_delayed_13 <= b31_data_delayed_12; + b31_data_delayed_14 <= b31_data_delayed_13; + b31_data_delayed_15 <= b31_data_delayed_14; + b31_data_delayed_16 <= b31_data_delayed_15; + b31_data_delayed_17 <= b31_data_delayed_16; + b31_data_delayed_18 <= b31_data_delayed_17; + b31_data_delayed_19 <= b31_data_delayed_18; + b31_data_delayed_20 <= b31_data_delayed_19; + b31_data_delayed_21 <= b31_data_delayed_20; + b31_data_delayed_22 <= b31_data_delayed_21; + b31_data_delayed_23 <= b31_data_delayed_22; + b31_data_delayed_24 <= b31_data_delayed_23; + b31_data_delayed_25 <= b31_data_delayed_24; + b31_data_delayed_26 <= b31_data_delayed_25; + b31_data_delayed_27 <= b31_data_delayed_26; + b31_data_delayed_28 <= b31_data_delayed_27; + b31_data_delayed_29 <= b31_data_delayed_28; + b31_data_delayed_30 <= b31_data_delayed_29; + b31_data_delayed_31 <= b31_data_delayed_30; + + end +end +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolically connected PEs +////////////////////////////////////////////////////////////////////////// +module systolic_pe_matrix( +clk, +reset, +pe_reset, +a0, +a1, +a2, +a3, +a4, +a5, +a6, +a7, +a8, +a9, +a10, +a11, +a12, +a13, +a14, +a15, +a16, +a17, +a18, +a19, +a20, +a21, +a22, +a23, +a24, +a25, +a26, +a27, +a28, +a29, +a30, +a31, +b0, +b1, +b2, +b3, +b4, +b5, +b6, +b7, +b8, +b9, +b10, +b11, +b12, +b13, +b14, +b15, +b16, +b17, +b18, +b19, +b20, +b21, +b22, +b23, +b24, +b25, +b26, +b27, +b28, +b29, +b30, +b31, +matrixC0_0, +matrixC0_1, +matrixC0_2, +matrixC0_3, +matrixC0_4, +matrixC0_5, +matrixC0_6, +matrixC0_7, +matrixC0_8, +matrixC0_9, +matrixC0_10, +matrixC0_11, +matrixC0_12, +matrixC0_13, +matrixC0_14, +matrixC0_15, +matrixC0_16, +matrixC0_17, +matrixC0_18, +matrixC0_19, +matrixC0_20, +matrixC0_21, +matrixC0_22, +matrixC0_23, +matrixC0_24, +matrixC0_25, +matrixC0_26, +matrixC0_27, +matrixC0_28, +matrixC0_29, +matrixC0_30, +matrixC0_31, +matrixC1_0, +matrixC1_1, +matrixC1_2, +matrixC1_3, +matrixC1_4, +matrixC1_5, +matrixC1_6, +matrixC1_7, +matrixC1_8, +matrixC1_9, +matrixC1_10, +matrixC1_11, +matrixC1_12, +matrixC1_13, +matrixC1_14, +matrixC1_15, +matrixC1_16, +matrixC1_17, +matrixC1_18, +matrixC1_19, +matrixC1_20, +matrixC1_21, +matrixC1_22, +matrixC1_23, +matrixC1_24, +matrixC1_25, +matrixC1_26, +matrixC1_27, +matrixC1_28, +matrixC1_29, +matrixC1_30, +matrixC1_31, +matrixC2_0, +matrixC2_1, +matrixC2_2, +matrixC2_3, +matrixC2_4, +matrixC2_5, +matrixC2_6, +matrixC2_7, +matrixC2_8, +matrixC2_9, +matrixC2_10, +matrixC2_11, +matrixC2_12, +matrixC2_13, +matrixC2_14, +matrixC2_15, +matrixC2_16, +matrixC2_17, +matrixC2_18, +matrixC2_19, +matrixC2_20, +matrixC2_21, +matrixC2_22, +matrixC2_23, +matrixC2_24, +matrixC2_25, +matrixC2_26, +matrixC2_27, +matrixC2_28, +matrixC2_29, +matrixC2_30, +matrixC2_31, +matrixC3_0, +matrixC3_1, +matrixC3_2, +matrixC3_3, +matrixC3_4, +matrixC3_5, +matrixC3_6, +matrixC3_7, +matrixC3_8, +matrixC3_9, +matrixC3_10, +matrixC3_11, +matrixC3_12, +matrixC3_13, +matrixC3_14, +matrixC3_15, +matrixC3_16, +matrixC3_17, +matrixC3_18, +matrixC3_19, +matrixC3_20, +matrixC3_21, +matrixC3_22, +matrixC3_23, +matrixC3_24, +matrixC3_25, +matrixC3_26, +matrixC3_27, +matrixC3_28, +matrixC3_29, +matrixC3_30, +matrixC3_31, +matrixC4_0, +matrixC4_1, +matrixC4_2, +matrixC4_3, +matrixC4_4, +matrixC4_5, +matrixC4_6, +matrixC4_7, +matrixC4_8, +matrixC4_9, +matrixC4_10, +matrixC4_11, +matrixC4_12, +matrixC4_13, +matrixC4_14, +matrixC4_15, +matrixC4_16, +matrixC4_17, +matrixC4_18, +matrixC4_19, +matrixC4_20, +matrixC4_21, +matrixC4_22, +matrixC4_23, +matrixC4_24, +matrixC4_25, +matrixC4_26, +matrixC4_27, +matrixC4_28, +matrixC4_29, +matrixC4_30, +matrixC4_31, +matrixC5_0, +matrixC5_1, +matrixC5_2, +matrixC5_3, +matrixC5_4, +matrixC5_5, +matrixC5_6, +matrixC5_7, +matrixC5_8, +matrixC5_9, +matrixC5_10, +matrixC5_11, +matrixC5_12, +matrixC5_13, +matrixC5_14, +matrixC5_15, +matrixC5_16, +matrixC5_17, +matrixC5_18, +matrixC5_19, +matrixC5_20, +matrixC5_21, +matrixC5_22, +matrixC5_23, +matrixC5_24, +matrixC5_25, +matrixC5_26, +matrixC5_27, +matrixC5_28, +matrixC5_29, +matrixC5_30, +matrixC5_31, +matrixC6_0, +matrixC6_1, +matrixC6_2, +matrixC6_3, +matrixC6_4, +matrixC6_5, +matrixC6_6, +matrixC6_7, +matrixC6_8, +matrixC6_9, +matrixC6_10, +matrixC6_11, +matrixC6_12, +matrixC6_13, +matrixC6_14, +matrixC6_15, +matrixC6_16, +matrixC6_17, +matrixC6_18, +matrixC6_19, +matrixC6_20, +matrixC6_21, +matrixC6_22, +matrixC6_23, +matrixC6_24, +matrixC6_25, +matrixC6_26, +matrixC6_27, +matrixC6_28, +matrixC6_29, +matrixC6_30, +matrixC6_31, +matrixC7_0, +matrixC7_1, +matrixC7_2, +matrixC7_3, +matrixC7_4, +matrixC7_5, +matrixC7_6, +matrixC7_7, +matrixC7_8, +matrixC7_9, +matrixC7_10, +matrixC7_11, +matrixC7_12, +matrixC7_13, +matrixC7_14, +matrixC7_15, +matrixC7_16, +matrixC7_17, +matrixC7_18, +matrixC7_19, +matrixC7_20, +matrixC7_21, +matrixC7_22, +matrixC7_23, +matrixC7_24, +matrixC7_25, +matrixC7_26, +matrixC7_27, +matrixC7_28, +matrixC7_29, +matrixC7_30, +matrixC7_31, +matrixC8_0, +matrixC8_1, +matrixC8_2, +matrixC8_3, +matrixC8_4, +matrixC8_5, +matrixC8_6, +matrixC8_7, +matrixC8_8, +matrixC8_9, +matrixC8_10, +matrixC8_11, +matrixC8_12, +matrixC8_13, +matrixC8_14, +matrixC8_15, +matrixC8_16, +matrixC8_17, +matrixC8_18, +matrixC8_19, +matrixC8_20, +matrixC8_21, +matrixC8_22, +matrixC8_23, +matrixC8_24, +matrixC8_25, +matrixC8_26, +matrixC8_27, +matrixC8_28, +matrixC8_29, +matrixC8_30, +matrixC8_31, +matrixC9_0, +matrixC9_1, +matrixC9_2, +matrixC9_3, +matrixC9_4, +matrixC9_5, +matrixC9_6, +matrixC9_7, +matrixC9_8, +matrixC9_9, +matrixC9_10, +matrixC9_11, +matrixC9_12, +matrixC9_13, +matrixC9_14, +matrixC9_15, +matrixC9_16, +matrixC9_17, +matrixC9_18, +matrixC9_19, +matrixC9_20, +matrixC9_21, +matrixC9_22, +matrixC9_23, +matrixC9_24, +matrixC9_25, +matrixC9_26, +matrixC9_27, +matrixC9_28, +matrixC9_29, +matrixC9_30, +matrixC9_31, +matrixC10_0, +matrixC10_1, +matrixC10_2, +matrixC10_3, +matrixC10_4, +matrixC10_5, +matrixC10_6, +matrixC10_7, +matrixC10_8, +matrixC10_9, +matrixC10_10, +matrixC10_11, +matrixC10_12, +matrixC10_13, +matrixC10_14, +matrixC10_15, +matrixC10_16, +matrixC10_17, +matrixC10_18, +matrixC10_19, +matrixC10_20, +matrixC10_21, +matrixC10_22, +matrixC10_23, +matrixC10_24, +matrixC10_25, +matrixC10_26, +matrixC10_27, +matrixC10_28, +matrixC10_29, +matrixC10_30, +matrixC10_31, +matrixC11_0, +matrixC11_1, +matrixC11_2, +matrixC11_3, +matrixC11_4, +matrixC11_5, +matrixC11_6, +matrixC11_7, +matrixC11_8, +matrixC11_9, +matrixC11_10, +matrixC11_11, +matrixC11_12, +matrixC11_13, +matrixC11_14, +matrixC11_15, +matrixC11_16, +matrixC11_17, +matrixC11_18, +matrixC11_19, +matrixC11_20, +matrixC11_21, +matrixC11_22, +matrixC11_23, +matrixC11_24, +matrixC11_25, +matrixC11_26, +matrixC11_27, +matrixC11_28, +matrixC11_29, +matrixC11_30, +matrixC11_31, +matrixC12_0, +matrixC12_1, +matrixC12_2, +matrixC12_3, +matrixC12_4, +matrixC12_5, +matrixC12_6, +matrixC12_7, +matrixC12_8, +matrixC12_9, +matrixC12_10, +matrixC12_11, +matrixC12_12, +matrixC12_13, +matrixC12_14, +matrixC12_15, +matrixC12_16, +matrixC12_17, +matrixC12_18, +matrixC12_19, +matrixC12_20, +matrixC12_21, +matrixC12_22, +matrixC12_23, +matrixC12_24, +matrixC12_25, +matrixC12_26, +matrixC12_27, +matrixC12_28, +matrixC12_29, +matrixC12_30, +matrixC12_31, +matrixC13_0, +matrixC13_1, +matrixC13_2, +matrixC13_3, +matrixC13_4, +matrixC13_5, +matrixC13_6, +matrixC13_7, +matrixC13_8, +matrixC13_9, +matrixC13_10, +matrixC13_11, +matrixC13_12, +matrixC13_13, +matrixC13_14, +matrixC13_15, +matrixC13_16, +matrixC13_17, +matrixC13_18, +matrixC13_19, +matrixC13_20, +matrixC13_21, +matrixC13_22, +matrixC13_23, +matrixC13_24, +matrixC13_25, +matrixC13_26, +matrixC13_27, +matrixC13_28, +matrixC13_29, +matrixC13_30, +matrixC13_31, +matrixC14_0, +matrixC14_1, +matrixC14_2, +matrixC14_3, +matrixC14_4, +matrixC14_5, +matrixC14_6, +matrixC14_7, +matrixC14_8, +matrixC14_9, +matrixC14_10, +matrixC14_11, +matrixC14_12, +matrixC14_13, +matrixC14_14, +matrixC14_15, +matrixC14_16, +matrixC14_17, +matrixC14_18, +matrixC14_19, +matrixC14_20, +matrixC14_21, +matrixC14_22, +matrixC14_23, +matrixC14_24, +matrixC14_25, +matrixC14_26, +matrixC14_27, +matrixC14_28, +matrixC14_29, +matrixC14_30, +matrixC14_31, +matrixC15_0, +matrixC15_1, +matrixC15_2, +matrixC15_3, +matrixC15_4, +matrixC15_5, +matrixC15_6, +matrixC15_7, +matrixC15_8, +matrixC15_9, +matrixC15_10, +matrixC15_11, +matrixC15_12, +matrixC15_13, +matrixC15_14, +matrixC15_15, +matrixC15_16, +matrixC15_17, +matrixC15_18, +matrixC15_19, +matrixC15_20, +matrixC15_21, +matrixC15_22, +matrixC15_23, +matrixC15_24, +matrixC15_25, +matrixC15_26, +matrixC15_27, +matrixC15_28, +matrixC15_29, +matrixC15_30, +matrixC15_31, +matrixC16_0, +matrixC16_1, +matrixC16_2, +matrixC16_3, +matrixC16_4, +matrixC16_5, +matrixC16_6, +matrixC16_7, +matrixC16_8, +matrixC16_9, +matrixC16_10, +matrixC16_11, +matrixC16_12, +matrixC16_13, +matrixC16_14, +matrixC16_15, +matrixC16_16, +matrixC16_17, +matrixC16_18, +matrixC16_19, +matrixC16_20, +matrixC16_21, +matrixC16_22, +matrixC16_23, +matrixC16_24, +matrixC16_25, +matrixC16_26, +matrixC16_27, +matrixC16_28, +matrixC16_29, +matrixC16_30, +matrixC16_31, +matrixC17_0, +matrixC17_1, +matrixC17_2, +matrixC17_3, +matrixC17_4, +matrixC17_5, +matrixC17_6, +matrixC17_7, +matrixC17_8, +matrixC17_9, +matrixC17_10, +matrixC17_11, +matrixC17_12, +matrixC17_13, +matrixC17_14, +matrixC17_15, +matrixC17_16, +matrixC17_17, +matrixC17_18, +matrixC17_19, +matrixC17_20, +matrixC17_21, +matrixC17_22, +matrixC17_23, +matrixC17_24, +matrixC17_25, +matrixC17_26, +matrixC17_27, +matrixC17_28, +matrixC17_29, +matrixC17_30, +matrixC17_31, +matrixC18_0, +matrixC18_1, +matrixC18_2, +matrixC18_3, +matrixC18_4, +matrixC18_5, +matrixC18_6, +matrixC18_7, +matrixC18_8, +matrixC18_9, +matrixC18_10, +matrixC18_11, +matrixC18_12, +matrixC18_13, +matrixC18_14, +matrixC18_15, +matrixC18_16, +matrixC18_17, +matrixC18_18, +matrixC18_19, +matrixC18_20, +matrixC18_21, +matrixC18_22, +matrixC18_23, +matrixC18_24, +matrixC18_25, +matrixC18_26, +matrixC18_27, +matrixC18_28, +matrixC18_29, +matrixC18_30, +matrixC18_31, +matrixC19_0, +matrixC19_1, +matrixC19_2, +matrixC19_3, +matrixC19_4, +matrixC19_5, +matrixC19_6, +matrixC19_7, +matrixC19_8, +matrixC19_9, +matrixC19_10, +matrixC19_11, +matrixC19_12, +matrixC19_13, +matrixC19_14, +matrixC19_15, +matrixC19_16, +matrixC19_17, +matrixC19_18, +matrixC19_19, +matrixC19_20, +matrixC19_21, +matrixC19_22, +matrixC19_23, +matrixC19_24, +matrixC19_25, +matrixC19_26, +matrixC19_27, +matrixC19_28, +matrixC19_29, +matrixC19_30, +matrixC19_31, +matrixC20_0, +matrixC20_1, +matrixC20_2, +matrixC20_3, +matrixC20_4, +matrixC20_5, +matrixC20_6, +matrixC20_7, +matrixC20_8, +matrixC20_9, +matrixC20_10, +matrixC20_11, +matrixC20_12, +matrixC20_13, +matrixC20_14, +matrixC20_15, +matrixC20_16, +matrixC20_17, +matrixC20_18, +matrixC20_19, +matrixC20_20, +matrixC20_21, +matrixC20_22, +matrixC20_23, +matrixC20_24, +matrixC20_25, +matrixC20_26, +matrixC20_27, +matrixC20_28, +matrixC20_29, +matrixC20_30, +matrixC20_31, +matrixC21_0, +matrixC21_1, +matrixC21_2, +matrixC21_3, +matrixC21_4, +matrixC21_5, +matrixC21_6, +matrixC21_7, +matrixC21_8, +matrixC21_9, +matrixC21_10, +matrixC21_11, +matrixC21_12, +matrixC21_13, +matrixC21_14, +matrixC21_15, +matrixC21_16, +matrixC21_17, +matrixC21_18, +matrixC21_19, +matrixC21_20, +matrixC21_21, +matrixC21_22, +matrixC21_23, +matrixC21_24, +matrixC21_25, +matrixC21_26, +matrixC21_27, +matrixC21_28, +matrixC21_29, +matrixC21_30, +matrixC21_31, +matrixC22_0, +matrixC22_1, +matrixC22_2, +matrixC22_3, +matrixC22_4, +matrixC22_5, +matrixC22_6, +matrixC22_7, +matrixC22_8, +matrixC22_9, +matrixC22_10, +matrixC22_11, +matrixC22_12, +matrixC22_13, +matrixC22_14, +matrixC22_15, +matrixC22_16, +matrixC22_17, +matrixC22_18, +matrixC22_19, +matrixC22_20, +matrixC22_21, +matrixC22_22, +matrixC22_23, +matrixC22_24, +matrixC22_25, +matrixC22_26, +matrixC22_27, +matrixC22_28, +matrixC22_29, +matrixC22_30, +matrixC22_31, +matrixC23_0, +matrixC23_1, +matrixC23_2, +matrixC23_3, +matrixC23_4, +matrixC23_5, +matrixC23_6, +matrixC23_7, +matrixC23_8, +matrixC23_9, +matrixC23_10, +matrixC23_11, +matrixC23_12, +matrixC23_13, +matrixC23_14, +matrixC23_15, +matrixC23_16, +matrixC23_17, +matrixC23_18, +matrixC23_19, +matrixC23_20, +matrixC23_21, +matrixC23_22, +matrixC23_23, +matrixC23_24, +matrixC23_25, +matrixC23_26, +matrixC23_27, +matrixC23_28, +matrixC23_29, +matrixC23_30, +matrixC23_31, +matrixC24_0, +matrixC24_1, +matrixC24_2, +matrixC24_3, +matrixC24_4, +matrixC24_5, +matrixC24_6, +matrixC24_7, +matrixC24_8, +matrixC24_9, +matrixC24_10, +matrixC24_11, +matrixC24_12, +matrixC24_13, +matrixC24_14, +matrixC24_15, +matrixC24_16, +matrixC24_17, +matrixC24_18, +matrixC24_19, +matrixC24_20, +matrixC24_21, +matrixC24_22, +matrixC24_23, +matrixC24_24, +matrixC24_25, +matrixC24_26, +matrixC24_27, +matrixC24_28, +matrixC24_29, +matrixC24_30, +matrixC24_31, +matrixC25_0, +matrixC25_1, +matrixC25_2, +matrixC25_3, +matrixC25_4, +matrixC25_5, +matrixC25_6, +matrixC25_7, +matrixC25_8, +matrixC25_9, +matrixC25_10, +matrixC25_11, +matrixC25_12, +matrixC25_13, +matrixC25_14, +matrixC25_15, +matrixC25_16, +matrixC25_17, +matrixC25_18, +matrixC25_19, +matrixC25_20, +matrixC25_21, +matrixC25_22, +matrixC25_23, +matrixC25_24, +matrixC25_25, +matrixC25_26, +matrixC25_27, +matrixC25_28, +matrixC25_29, +matrixC25_30, +matrixC25_31, +matrixC26_0, +matrixC26_1, +matrixC26_2, +matrixC26_3, +matrixC26_4, +matrixC26_5, +matrixC26_6, +matrixC26_7, +matrixC26_8, +matrixC26_9, +matrixC26_10, +matrixC26_11, +matrixC26_12, +matrixC26_13, +matrixC26_14, +matrixC26_15, +matrixC26_16, +matrixC26_17, +matrixC26_18, +matrixC26_19, +matrixC26_20, +matrixC26_21, +matrixC26_22, +matrixC26_23, +matrixC26_24, +matrixC26_25, +matrixC26_26, +matrixC26_27, +matrixC26_28, +matrixC26_29, +matrixC26_30, +matrixC26_31, +matrixC27_0, +matrixC27_1, +matrixC27_2, +matrixC27_3, +matrixC27_4, +matrixC27_5, +matrixC27_6, +matrixC27_7, +matrixC27_8, +matrixC27_9, +matrixC27_10, +matrixC27_11, +matrixC27_12, +matrixC27_13, +matrixC27_14, +matrixC27_15, +matrixC27_16, +matrixC27_17, +matrixC27_18, +matrixC27_19, +matrixC27_20, +matrixC27_21, +matrixC27_22, +matrixC27_23, +matrixC27_24, +matrixC27_25, +matrixC27_26, +matrixC27_27, +matrixC27_28, +matrixC27_29, +matrixC27_30, +matrixC27_31, +matrixC28_0, +matrixC28_1, +matrixC28_2, +matrixC28_3, +matrixC28_4, +matrixC28_5, +matrixC28_6, +matrixC28_7, +matrixC28_8, +matrixC28_9, +matrixC28_10, +matrixC28_11, +matrixC28_12, +matrixC28_13, +matrixC28_14, +matrixC28_15, +matrixC28_16, +matrixC28_17, +matrixC28_18, +matrixC28_19, +matrixC28_20, +matrixC28_21, +matrixC28_22, +matrixC28_23, +matrixC28_24, +matrixC28_25, +matrixC28_26, +matrixC28_27, +matrixC28_28, +matrixC28_29, +matrixC28_30, +matrixC28_31, +matrixC29_0, +matrixC29_1, +matrixC29_2, +matrixC29_3, +matrixC29_4, +matrixC29_5, +matrixC29_6, +matrixC29_7, +matrixC29_8, +matrixC29_9, +matrixC29_10, +matrixC29_11, +matrixC29_12, +matrixC29_13, +matrixC29_14, +matrixC29_15, +matrixC29_16, +matrixC29_17, +matrixC29_18, +matrixC29_19, +matrixC29_20, +matrixC29_21, +matrixC29_22, +matrixC29_23, +matrixC29_24, +matrixC29_25, +matrixC29_26, +matrixC29_27, +matrixC29_28, +matrixC29_29, +matrixC29_30, +matrixC29_31, +matrixC30_0, +matrixC30_1, +matrixC30_2, +matrixC30_3, +matrixC30_4, +matrixC30_5, +matrixC30_6, +matrixC30_7, +matrixC30_8, +matrixC30_9, +matrixC30_10, +matrixC30_11, +matrixC30_12, +matrixC30_13, +matrixC30_14, +matrixC30_15, +matrixC30_16, +matrixC30_17, +matrixC30_18, +matrixC30_19, +matrixC30_20, +matrixC30_21, +matrixC30_22, +matrixC30_23, +matrixC30_24, +matrixC30_25, +matrixC30_26, +matrixC30_27, +matrixC30_28, +matrixC30_29, +matrixC30_30, +matrixC30_31, +matrixC31_0, +matrixC31_1, +matrixC31_2, +matrixC31_3, +matrixC31_4, +matrixC31_5, +matrixC31_6, +matrixC31_7, +matrixC31_8, +matrixC31_9, +matrixC31_10, +matrixC31_11, +matrixC31_12, +matrixC31_13, +matrixC31_14, +matrixC31_15, +matrixC31_16, +matrixC31_17, +matrixC31_18, +matrixC31_19, +matrixC31_20, +matrixC31_21, +matrixC31_22, +matrixC31_23, +matrixC31_24, +matrixC31_25, +matrixC31_26, +matrixC31_27, +matrixC31_28, +matrixC31_29, +matrixC31_30, +matrixC31_31, + +a_data_out, +b_data_out +); + +input clk; +input reset; +input pe_reset; +input [`DWIDTH-1:0] a0; +input [`DWIDTH-1:0] a1; +input [`DWIDTH-1:0] a2; +input [`DWIDTH-1:0] a3; +input [`DWIDTH-1:0] a4; +input [`DWIDTH-1:0] a5; +input [`DWIDTH-1:0] a6; +input [`DWIDTH-1:0] a7; +input [`DWIDTH-1:0] a8; +input [`DWIDTH-1:0] a9; +input [`DWIDTH-1:0] a10; +input [`DWIDTH-1:0] a11; +input [`DWIDTH-1:0] a12; +input [`DWIDTH-1:0] a13; +input [`DWIDTH-1:0] a14; +input [`DWIDTH-1:0] a15; +input [`DWIDTH-1:0] a16; +input [`DWIDTH-1:0] a17; +input [`DWIDTH-1:0] a18; +input [`DWIDTH-1:0] a19; +input [`DWIDTH-1:0] a20; +input [`DWIDTH-1:0] a21; +input [`DWIDTH-1:0] a22; +input [`DWIDTH-1:0] a23; +input [`DWIDTH-1:0] a24; +input [`DWIDTH-1:0] a25; +input [`DWIDTH-1:0] a26; +input [`DWIDTH-1:0] a27; +input [`DWIDTH-1:0] a28; +input [`DWIDTH-1:0] a29; +input [`DWIDTH-1:0] a30; +input [`DWIDTH-1:0] a31; +input [`DWIDTH-1:0] b0; +input [`DWIDTH-1:0] b1; +input [`DWIDTH-1:0] b2; +input [`DWIDTH-1:0] b3; +input [`DWIDTH-1:0] b4; +input [`DWIDTH-1:0] b5; +input [`DWIDTH-1:0] b6; +input [`DWIDTH-1:0] b7; +input [`DWIDTH-1:0] b8; +input [`DWIDTH-1:0] b9; +input [`DWIDTH-1:0] b10; +input [`DWIDTH-1:0] b11; +input [`DWIDTH-1:0] b12; +input [`DWIDTH-1:0] b13; +input [`DWIDTH-1:0] b14; +input [`DWIDTH-1:0] b15; +input [`DWIDTH-1:0] b16; +input [`DWIDTH-1:0] b17; +input [`DWIDTH-1:0] b18; +input [`DWIDTH-1:0] b19; +input [`DWIDTH-1:0] b20; +input [`DWIDTH-1:0] b21; +input [`DWIDTH-1:0] b22; +input [`DWIDTH-1:0] b23; +input [`DWIDTH-1:0] b24; +input [`DWIDTH-1:0] b25; +input [`DWIDTH-1:0] b26; +input [`DWIDTH-1:0] b27; +input [`DWIDTH-1:0] b28; +input [`DWIDTH-1:0] b29; +input [`DWIDTH-1:0] b30; +input [`DWIDTH-1:0] b31; +output [`DWIDTH-1:0] matrixC0_0; +output [`DWIDTH-1:0] matrixC0_1; +output [`DWIDTH-1:0] matrixC0_2; +output [`DWIDTH-1:0] matrixC0_3; +output [`DWIDTH-1:0] matrixC0_4; +output [`DWIDTH-1:0] matrixC0_5; +output [`DWIDTH-1:0] matrixC0_6; +output [`DWIDTH-1:0] matrixC0_7; +output [`DWIDTH-1:0] matrixC0_8; +output [`DWIDTH-1:0] matrixC0_9; +output [`DWIDTH-1:0] matrixC0_10; +output [`DWIDTH-1:0] matrixC0_11; +output [`DWIDTH-1:0] matrixC0_12; +output [`DWIDTH-1:0] matrixC0_13; +output [`DWIDTH-1:0] matrixC0_14; +output [`DWIDTH-1:0] matrixC0_15; +output [`DWIDTH-1:0] matrixC0_16; +output [`DWIDTH-1:0] matrixC0_17; +output [`DWIDTH-1:0] matrixC0_18; +output [`DWIDTH-1:0] matrixC0_19; +output [`DWIDTH-1:0] matrixC0_20; +output [`DWIDTH-1:0] matrixC0_21; +output [`DWIDTH-1:0] matrixC0_22; +output [`DWIDTH-1:0] matrixC0_23; +output [`DWIDTH-1:0] matrixC0_24; +output [`DWIDTH-1:0] matrixC0_25; +output [`DWIDTH-1:0] matrixC0_26; +output [`DWIDTH-1:0] matrixC0_27; +output [`DWIDTH-1:0] matrixC0_28; +output [`DWIDTH-1:0] matrixC0_29; +output [`DWIDTH-1:0] matrixC0_30; +output [`DWIDTH-1:0] matrixC0_31; +output [`DWIDTH-1:0] matrixC1_0; +output [`DWIDTH-1:0] matrixC1_1; +output [`DWIDTH-1:0] matrixC1_2; +output [`DWIDTH-1:0] matrixC1_3; +output [`DWIDTH-1:0] matrixC1_4; +output [`DWIDTH-1:0] matrixC1_5; +output [`DWIDTH-1:0] matrixC1_6; +output [`DWIDTH-1:0] matrixC1_7; +output [`DWIDTH-1:0] matrixC1_8; +output [`DWIDTH-1:0] matrixC1_9; +output [`DWIDTH-1:0] matrixC1_10; +output [`DWIDTH-1:0] matrixC1_11; +output [`DWIDTH-1:0] matrixC1_12; +output [`DWIDTH-1:0] matrixC1_13; +output [`DWIDTH-1:0] matrixC1_14; +output [`DWIDTH-1:0] matrixC1_15; +output [`DWIDTH-1:0] matrixC1_16; +output [`DWIDTH-1:0] matrixC1_17; +output [`DWIDTH-1:0] matrixC1_18; +output [`DWIDTH-1:0] matrixC1_19; +output [`DWIDTH-1:0] matrixC1_20; +output [`DWIDTH-1:0] matrixC1_21; +output [`DWIDTH-1:0] matrixC1_22; +output [`DWIDTH-1:0] matrixC1_23; +output [`DWIDTH-1:0] matrixC1_24; +output [`DWIDTH-1:0] matrixC1_25; +output [`DWIDTH-1:0] matrixC1_26; +output [`DWIDTH-1:0] matrixC1_27; +output [`DWIDTH-1:0] matrixC1_28; +output [`DWIDTH-1:0] matrixC1_29; +output [`DWIDTH-1:0] matrixC1_30; +output [`DWIDTH-1:0] matrixC1_31; +output [`DWIDTH-1:0] matrixC2_0; +output [`DWIDTH-1:0] matrixC2_1; +output [`DWIDTH-1:0] matrixC2_2; +output [`DWIDTH-1:0] matrixC2_3; +output [`DWIDTH-1:0] matrixC2_4; +output [`DWIDTH-1:0] matrixC2_5; +output [`DWIDTH-1:0] matrixC2_6; +output [`DWIDTH-1:0] matrixC2_7; +output [`DWIDTH-1:0] matrixC2_8; +output [`DWIDTH-1:0] matrixC2_9; +output [`DWIDTH-1:0] matrixC2_10; +output [`DWIDTH-1:0] matrixC2_11; +output [`DWIDTH-1:0] matrixC2_12; +output [`DWIDTH-1:0] matrixC2_13; +output [`DWIDTH-1:0] matrixC2_14; +output [`DWIDTH-1:0] matrixC2_15; +output [`DWIDTH-1:0] matrixC2_16; +output [`DWIDTH-1:0] matrixC2_17; +output [`DWIDTH-1:0] matrixC2_18; +output [`DWIDTH-1:0] matrixC2_19; +output [`DWIDTH-1:0] matrixC2_20; +output [`DWIDTH-1:0] matrixC2_21; +output [`DWIDTH-1:0] matrixC2_22; +output [`DWIDTH-1:0] matrixC2_23; +output [`DWIDTH-1:0] matrixC2_24; +output [`DWIDTH-1:0] matrixC2_25; +output [`DWIDTH-1:0] matrixC2_26; +output [`DWIDTH-1:0] matrixC2_27; +output [`DWIDTH-1:0] matrixC2_28; +output [`DWIDTH-1:0] matrixC2_29; +output [`DWIDTH-1:0] matrixC2_30; +output [`DWIDTH-1:0] matrixC2_31; +output [`DWIDTH-1:0] matrixC3_0; +output [`DWIDTH-1:0] matrixC3_1; +output [`DWIDTH-1:0] matrixC3_2; +output [`DWIDTH-1:0] matrixC3_3; +output [`DWIDTH-1:0] matrixC3_4; +output [`DWIDTH-1:0] matrixC3_5; +output [`DWIDTH-1:0] matrixC3_6; +output [`DWIDTH-1:0] matrixC3_7; +output [`DWIDTH-1:0] matrixC3_8; +output [`DWIDTH-1:0] matrixC3_9; +output [`DWIDTH-1:0] matrixC3_10; +output [`DWIDTH-1:0] matrixC3_11; +output [`DWIDTH-1:0] matrixC3_12; +output [`DWIDTH-1:0] matrixC3_13; +output [`DWIDTH-1:0] matrixC3_14; +output [`DWIDTH-1:0] matrixC3_15; +output [`DWIDTH-1:0] matrixC3_16; +output [`DWIDTH-1:0] matrixC3_17; +output [`DWIDTH-1:0] matrixC3_18; +output [`DWIDTH-1:0] matrixC3_19; +output [`DWIDTH-1:0] matrixC3_20; +output [`DWIDTH-1:0] matrixC3_21; +output [`DWIDTH-1:0] matrixC3_22; +output [`DWIDTH-1:0] matrixC3_23; +output [`DWIDTH-1:0] matrixC3_24; +output [`DWIDTH-1:0] matrixC3_25; +output [`DWIDTH-1:0] matrixC3_26; +output [`DWIDTH-1:0] matrixC3_27; +output [`DWIDTH-1:0] matrixC3_28; +output [`DWIDTH-1:0] matrixC3_29; +output [`DWIDTH-1:0] matrixC3_30; +output [`DWIDTH-1:0] matrixC3_31; +output [`DWIDTH-1:0] matrixC4_0; +output [`DWIDTH-1:0] matrixC4_1; +output [`DWIDTH-1:0] matrixC4_2; +output [`DWIDTH-1:0] matrixC4_3; +output [`DWIDTH-1:0] matrixC4_4; +output [`DWIDTH-1:0] matrixC4_5; +output [`DWIDTH-1:0] matrixC4_6; +output [`DWIDTH-1:0] matrixC4_7; +output [`DWIDTH-1:0] matrixC4_8; +output [`DWIDTH-1:0] matrixC4_9; +output [`DWIDTH-1:0] matrixC4_10; +output [`DWIDTH-1:0] matrixC4_11; +output [`DWIDTH-1:0] matrixC4_12; +output [`DWIDTH-1:0] matrixC4_13; +output [`DWIDTH-1:0] matrixC4_14; +output [`DWIDTH-1:0] matrixC4_15; +output [`DWIDTH-1:0] matrixC4_16; +output [`DWIDTH-1:0] matrixC4_17; +output [`DWIDTH-1:0] matrixC4_18; +output [`DWIDTH-1:0] matrixC4_19; +output [`DWIDTH-1:0] matrixC4_20; +output [`DWIDTH-1:0] matrixC4_21; +output [`DWIDTH-1:0] matrixC4_22; +output [`DWIDTH-1:0] matrixC4_23; +output [`DWIDTH-1:0] matrixC4_24; +output [`DWIDTH-1:0] matrixC4_25; +output [`DWIDTH-1:0] matrixC4_26; +output [`DWIDTH-1:0] matrixC4_27; +output [`DWIDTH-1:0] matrixC4_28; +output [`DWIDTH-1:0] matrixC4_29; +output [`DWIDTH-1:0] matrixC4_30; +output [`DWIDTH-1:0] matrixC4_31; +output [`DWIDTH-1:0] matrixC5_0; +output [`DWIDTH-1:0] matrixC5_1; +output [`DWIDTH-1:0] matrixC5_2; +output [`DWIDTH-1:0] matrixC5_3; +output [`DWIDTH-1:0] matrixC5_4; +output [`DWIDTH-1:0] matrixC5_5; +output [`DWIDTH-1:0] matrixC5_6; +output [`DWIDTH-1:0] matrixC5_7; +output [`DWIDTH-1:0] matrixC5_8; +output [`DWIDTH-1:0] matrixC5_9; +output [`DWIDTH-1:0] matrixC5_10; +output [`DWIDTH-1:0] matrixC5_11; +output [`DWIDTH-1:0] matrixC5_12; +output [`DWIDTH-1:0] matrixC5_13; +output [`DWIDTH-1:0] matrixC5_14; +output [`DWIDTH-1:0] matrixC5_15; +output [`DWIDTH-1:0] matrixC5_16; +output [`DWIDTH-1:0] matrixC5_17; +output [`DWIDTH-1:0] matrixC5_18; +output [`DWIDTH-1:0] matrixC5_19; +output [`DWIDTH-1:0] matrixC5_20; +output [`DWIDTH-1:0] matrixC5_21; +output [`DWIDTH-1:0] matrixC5_22; +output [`DWIDTH-1:0] matrixC5_23; +output [`DWIDTH-1:0] matrixC5_24; +output [`DWIDTH-1:0] matrixC5_25; +output [`DWIDTH-1:0] matrixC5_26; +output [`DWIDTH-1:0] matrixC5_27; +output [`DWIDTH-1:0] matrixC5_28; +output [`DWIDTH-1:0] matrixC5_29; +output [`DWIDTH-1:0] matrixC5_30; +output [`DWIDTH-1:0] matrixC5_31; +output [`DWIDTH-1:0] matrixC6_0; +output [`DWIDTH-1:0] matrixC6_1; +output [`DWIDTH-1:0] matrixC6_2; +output [`DWIDTH-1:0] matrixC6_3; +output [`DWIDTH-1:0] matrixC6_4; +output [`DWIDTH-1:0] matrixC6_5; +output [`DWIDTH-1:0] matrixC6_6; +output [`DWIDTH-1:0] matrixC6_7; +output [`DWIDTH-1:0] matrixC6_8; +output [`DWIDTH-1:0] matrixC6_9; +output [`DWIDTH-1:0] matrixC6_10; +output [`DWIDTH-1:0] matrixC6_11; +output [`DWIDTH-1:0] matrixC6_12; +output [`DWIDTH-1:0] matrixC6_13; +output [`DWIDTH-1:0] matrixC6_14; +output [`DWIDTH-1:0] matrixC6_15; +output [`DWIDTH-1:0] matrixC6_16; +output [`DWIDTH-1:0] matrixC6_17; +output [`DWIDTH-1:0] matrixC6_18; +output [`DWIDTH-1:0] matrixC6_19; +output [`DWIDTH-1:0] matrixC6_20; +output [`DWIDTH-1:0] matrixC6_21; +output [`DWIDTH-1:0] matrixC6_22; +output [`DWIDTH-1:0] matrixC6_23; +output [`DWIDTH-1:0] matrixC6_24; +output [`DWIDTH-1:0] matrixC6_25; +output [`DWIDTH-1:0] matrixC6_26; +output [`DWIDTH-1:0] matrixC6_27; +output [`DWIDTH-1:0] matrixC6_28; +output [`DWIDTH-1:0] matrixC6_29; +output [`DWIDTH-1:0] matrixC6_30; +output [`DWIDTH-1:0] matrixC6_31; +output [`DWIDTH-1:0] matrixC7_0; +output [`DWIDTH-1:0] matrixC7_1; +output [`DWIDTH-1:0] matrixC7_2; +output [`DWIDTH-1:0] matrixC7_3; +output [`DWIDTH-1:0] matrixC7_4; +output [`DWIDTH-1:0] matrixC7_5; +output [`DWIDTH-1:0] matrixC7_6; +output [`DWIDTH-1:0] matrixC7_7; +output [`DWIDTH-1:0] matrixC7_8; +output [`DWIDTH-1:0] matrixC7_9; +output [`DWIDTH-1:0] matrixC7_10; +output [`DWIDTH-1:0] matrixC7_11; +output [`DWIDTH-1:0] matrixC7_12; +output [`DWIDTH-1:0] matrixC7_13; +output [`DWIDTH-1:0] matrixC7_14; +output [`DWIDTH-1:0] matrixC7_15; +output [`DWIDTH-1:0] matrixC7_16; +output [`DWIDTH-1:0] matrixC7_17; +output [`DWIDTH-1:0] matrixC7_18; +output [`DWIDTH-1:0] matrixC7_19; +output [`DWIDTH-1:0] matrixC7_20; +output [`DWIDTH-1:0] matrixC7_21; +output [`DWIDTH-1:0] matrixC7_22; +output [`DWIDTH-1:0] matrixC7_23; +output [`DWIDTH-1:0] matrixC7_24; +output [`DWIDTH-1:0] matrixC7_25; +output [`DWIDTH-1:0] matrixC7_26; +output [`DWIDTH-1:0] matrixC7_27; +output [`DWIDTH-1:0] matrixC7_28; +output [`DWIDTH-1:0] matrixC7_29; +output [`DWIDTH-1:0] matrixC7_30; +output [`DWIDTH-1:0] matrixC7_31; +output [`DWIDTH-1:0] matrixC8_0; +output [`DWIDTH-1:0] matrixC8_1; +output [`DWIDTH-1:0] matrixC8_2; +output [`DWIDTH-1:0] matrixC8_3; +output [`DWIDTH-1:0] matrixC8_4; +output [`DWIDTH-1:0] matrixC8_5; +output [`DWIDTH-1:0] matrixC8_6; +output [`DWIDTH-1:0] matrixC8_7; +output [`DWIDTH-1:0] matrixC8_8; +output [`DWIDTH-1:0] matrixC8_9; +output [`DWIDTH-1:0] matrixC8_10; +output [`DWIDTH-1:0] matrixC8_11; +output [`DWIDTH-1:0] matrixC8_12; +output [`DWIDTH-1:0] matrixC8_13; +output [`DWIDTH-1:0] matrixC8_14; +output [`DWIDTH-1:0] matrixC8_15; +output [`DWIDTH-1:0] matrixC8_16; +output [`DWIDTH-1:0] matrixC8_17; +output [`DWIDTH-1:0] matrixC8_18; +output [`DWIDTH-1:0] matrixC8_19; +output [`DWIDTH-1:0] matrixC8_20; +output [`DWIDTH-1:0] matrixC8_21; +output [`DWIDTH-1:0] matrixC8_22; +output [`DWIDTH-1:0] matrixC8_23; +output [`DWIDTH-1:0] matrixC8_24; +output [`DWIDTH-1:0] matrixC8_25; +output [`DWIDTH-1:0] matrixC8_26; +output [`DWIDTH-1:0] matrixC8_27; +output [`DWIDTH-1:0] matrixC8_28; +output [`DWIDTH-1:0] matrixC8_29; +output [`DWIDTH-1:0] matrixC8_30; +output [`DWIDTH-1:0] matrixC8_31; +output [`DWIDTH-1:0] matrixC9_0; +output [`DWIDTH-1:0] matrixC9_1; +output [`DWIDTH-1:0] matrixC9_2; +output [`DWIDTH-1:0] matrixC9_3; +output [`DWIDTH-1:0] matrixC9_4; +output [`DWIDTH-1:0] matrixC9_5; +output [`DWIDTH-1:0] matrixC9_6; +output [`DWIDTH-1:0] matrixC9_7; +output [`DWIDTH-1:0] matrixC9_8; +output [`DWIDTH-1:0] matrixC9_9; +output [`DWIDTH-1:0] matrixC9_10; +output [`DWIDTH-1:0] matrixC9_11; +output [`DWIDTH-1:0] matrixC9_12; +output [`DWIDTH-1:0] matrixC9_13; +output [`DWIDTH-1:0] matrixC9_14; +output [`DWIDTH-1:0] matrixC9_15; +output [`DWIDTH-1:0] matrixC9_16; +output [`DWIDTH-1:0] matrixC9_17; +output [`DWIDTH-1:0] matrixC9_18; +output [`DWIDTH-1:0] matrixC9_19; +output [`DWIDTH-1:0] matrixC9_20; +output [`DWIDTH-1:0] matrixC9_21; +output [`DWIDTH-1:0] matrixC9_22; +output [`DWIDTH-1:0] matrixC9_23; +output [`DWIDTH-1:0] matrixC9_24; +output [`DWIDTH-1:0] matrixC9_25; +output [`DWIDTH-1:0] matrixC9_26; +output [`DWIDTH-1:0] matrixC9_27; +output [`DWIDTH-1:0] matrixC9_28; +output [`DWIDTH-1:0] matrixC9_29; +output [`DWIDTH-1:0] matrixC9_30; +output [`DWIDTH-1:0] matrixC9_31; +output [`DWIDTH-1:0] matrixC10_0; +output [`DWIDTH-1:0] matrixC10_1; +output [`DWIDTH-1:0] matrixC10_2; +output [`DWIDTH-1:0] matrixC10_3; +output [`DWIDTH-1:0] matrixC10_4; +output [`DWIDTH-1:0] matrixC10_5; +output [`DWIDTH-1:0] matrixC10_6; +output [`DWIDTH-1:0] matrixC10_7; +output [`DWIDTH-1:0] matrixC10_8; +output [`DWIDTH-1:0] matrixC10_9; +output [`DWIDTH-1:0] matrixC10_10; +output [`DWIDTH-1:0] matrixC10_11; +output [`DWIDTH-1:0] matrixC10_12; +output [`DWIDTH-1:0] matrixC10_13; +output [`DWIDTH-1:0] matrixC10_14; +output [`DWIDTH-1:0] matrixC10_15; +output [`DWIDTH-1:0] matrixC10_16; +output [`DWIDTH-1:0] matrixC10_17; +output [`DWIDTH-1:0] matrixC10_18; +output [`DWIDTH-1:0] matrixC10_19; +output [`DWIDTH-1:0] matrixC10_20; +output [`DWIDTH-1:0] matrixC10_21; +output [`DWIDTH-1:0] matrixC10_22; +output [`DWIDTH-1:0] matrixC10_23; +output [`DWIDTH-1:0] matrixC10_24; +output [`DWIDTH-1:0] matrixC10_25; +output [`DWIDTH-1:0] matrixC10_26; +output [`DWIDTH-1:0] matrixC10_27; +output [`DWIDTH-1:0] matrixC10_28; +output [`DWIDTH-1:0] matrixC10_29; +output [`DWIDTH-1:0] matrixC10_30; +output [`DWIDTH-1:0] matrixC10_31; +output [`DWIDTH-1:0] matrixC11_0; +output [`DWIDTH-1:0] matrixC11_1; +output [`DWIDTH-1:0] matrixC11_2; +output [`DWIDTH-1:0] matrixC11_3; +output [`DWIDTH-1:0] matrixC11_4; +output [`DWIDTH-1:0] matrixC11_5; +output [`DWIDTH-1:0] matrixC11_6; +output [`DWIDTH-1:0] matrixC11_7; +output [`DWIDTH-1:0] matrixC11_8; +output [`DWIDTH-1:0] matrixC11_9; +output [`DWIDTH-1:0] matrixC11_10; +output [`DWIDTH-1:0] matrixC11_11; +output [`DWIDTH-1:0] matrixC11_12; +output [`DWIDTH-1:0] matrixC11_13; +output [`DWIDTH-1:0] matrixC11_14; +output [`DWIDTH-1:0] matrixC11_15; +output [`DWIDTH-1:0] matrixC11_16; +output [`DWIDTH-1:0] matrixC11_17; +output [`DWIDTH-1:0] matrixC11_18; +output [`DWIDTH-1:0] matrixC11_19; +output [`DWIDTH-1:0] matrixC11_20; +output [`DWIDTH-1:0] matrixC11_21; +output [`DWIDTH-1:0] matrixC11_22; +output [`DWIDTH-1:0] matrixC11_23; +output [`DWIDTH-1:0] matrixC11_24; +output [`DWIDTH-1:0] matrixC11_25; +output [`DWIDTH-1:0] matrixC11_26; +output [`DWIDTH-1:0] matrixC11_27; +output [`DWIDTH-1:0] matrixC11_28; +output [`DWIDTH-1:0] matrixC11_29; +output [`DWIDTH-1:0] matrixC11_30; +output [`DWIDTH-1:0] matrixC11_31; +output [`DWIDTH-1:0] matrixC12_0; +output [`DWIDTH-1:0] matrixC12_1; +output [`DWIDTH-1:0] matrixC12_2; +output [`DWIDTH-1:0] matrixC12_3; +output [`DWIDTH-1:0] matrixC12_4; +output [`DWIDTH-1:0] matrixC12_5; +output [`DWIDTH-1:0] matrixC12_6; +output [`DWIDTH-1:0] matrixC12_7; +output [`DWIDTH-1:0] matrixC12_8; +output [`DWIDTH-1:0] matrixC12_9; +output [`DWIDTH-1:0] matrixC12_10; +output [`DWIDTH-1:0] matrixC12_11; +output [`DWIDTH-1:0] matrixC12_12; +output [`DWIDTH-1:0] matrixC12_13; +output [`DWIDTH-1:0] matrixC12_14; +output [`DWIDTH-1:0] matrixC12_15; +output [`DWIDTH-1:0] matrixC12_16; +output [`DWIDTH-1:0] matrixC12_17; +output [`DWIDTH-1:0] matrixC12_18; +output [`DWIDTH-1:0] matrixC12_19; +output [`DWIDTH-1:0] matrixC12_20; +output [`DWIDTH-1:0] matrixC12_21; +output [`DWIDTH-1:0] matrixC12_22; +output [`DWIDTH-1:0] matrixC12_23; +output [`DWIDTH-1:0] matrixC12_24; +output [`DWIDTH-1:0] matrixC12_25; +output [`DWIDTH-1:0] matrixC12_26; +output [`DWIDTH-1:0] matrixC12_27; +output [`DWIDTH-1:0] matrixC12_28; +output [`DWIDTH-1:0] matrixC12_29; +output [`DWIDTH-1:0] matrixC12_30; +output [`DWIDTH-1:0] matrixC12_31; +output [`DWIDTH-1:0] matrixC13_0; +output [`DWIDTH-1:0] matrixC13_1; +output [`DWIDTH-1:0] matrixC13_2; +output [`DWIDTH-1:0] matrixC13_3; +output [`DWIDTH-1:0] matrixC13_4; +output [`DWIDTH-1:0] matrixC13_5; +output [`DWIDTH-1:0] matrixC13_6; +output [`DWIDTH-1:0] matrixC13_7; +output [`DWIDTH-1:0] matrixC13_8; +output [`DWIDTH-1:0] matrixC13_9; +output [`DWIDTH-1:0] matrixC13_10; +output [`DWIDTH-1:0] matrixC13_11; +output [`DWIDTH-1:0] matrixC13_12; +output [`DWIDTH-1:0] matrixC13_13; +output [`DWIDTH-1:0] matrixC13_14; +output [`DWIDTH-1:0] matrixC13_15; +output [`DWIDTH-1:0] matrixC13_16; +output [`DWIDTH-1:0] matrixC13_17; +output [`DWIDTH-1:0] matrixC13_18; +output [`DWIDTH-1:0] matrixC13_19; +output [`DWIDTH-1:0] matrixC13_20; +output [`DWIDTH-1:0] matrixC13_21; +output [`DWIDTH-1:0] matrixC13_22; +output [`DWIDTH-1:0] matrixC13_23; +output [`DWIDTH-1:0] matrixC13_24; +output [`DWIDTH-1:0] matrixC13_25; +output [`DWIDTH-1:0] matrixC13_26; +output [`DWIDTH-1:0] matrixC13_27; +output [`DWIDTH-1:0] matrixC13_28; +output [`DWIDTH-1:0] matrixC13_29; +output [`DWIDTH-1:0] matrixC13_30; +output [`DWIDTH-1:0] matrixC13_31; +output [`DWIDTH-1:0] matrixC14_0; +output [`DWIDTH-1:0] matrixC14_1; +output [`DWIDTH-1:0] matrixC14_2; +output [`DWIDTH-1:0] matrixC14_3; +output [`DWIDTH-1:0] matrixC14_4; +output [`DWIDTH-1:0] matrixC14_5; +output [`DWIDTH-1:0] matrixC14_6; +output [`DWIDTH-1:0] matrixC14_7; +output [`DWIDTH-1:0] matrixC14_8; +output [`DWIDTH-1:0] matrixC14_9; +output [`DWIDTH-1:0] matrixC14_10; +output [`DWIDTH-1:0] matrixC14_11; +output [`DWIDTH-1:0] matrixC14_12; +output [`DWIDTH-1:0] matrixC14_13; +output [`DWIDTH-1:0] matrixC14_14; +output [`DWIDTH-1:0] matrixC14_15; +output [`DWIDTH-1:0] matrixC14_16; +output [`DWIDTH-1:0] matrixC14_17; +output [`DWIDTH-1:0] matrixC14_18; +output [`DWIDTH-1:0] matrixC14_19; +output [`DWIDTH-1:0] matrixC14_20; +output [`DWIDTH-1:0] matrixC14_21; +output [`DWIDTH-1:0] matrixC14_22; +output [`DWIDTH-1:0] matrixC14_23; +output [`DWIDTH-1:0] matrixC14_24; +output [`DWIDTH-1:0] matrixC14_25; +output [`DWIDTH-1:0] matrixC14_26; +output [`DWIDTH-1:0] matrixC14_27; +output [`DWIDTH-1:0] matrixC14_28; +output [`DWIDTH-1:0] matrixC14_29; +output [`DWIDTH-1:0] matrixC14_30; +output [`DWIDTH-1:0] matrixC14_31; +output [`DWIDTH-1:0] matrixC15_0; +output [`DWIDTH-1:0] matrixC15_1; +output [`DWIDTH-1:0] matrixC15_2; +output [`DWIDTH-1:0] matrixC15_3; +output [`DWIDTH-1:0] matrixC15_4; +output [`DWIDTH-1:0] matrixC15_5; +output [`DWIDTH-1:0] matrixC15_6; +output [`DWIDTH-1:0] matrixC15_7; +output [`DWIDTH-1:0] matrixC15_8; +output [`DWIDTH-1:0] matrixC15_9; +output [`DWIDTH-1:0] matrixC15_10; +output [`DWIDTH-1:0] matrixC15_11; +output [`DWIDTH-1:0] matrixC15_12; +output [`DWIDTH-1:0] matrixC15_13; +output [`DWIDTH-1:0] matrixC15_14; +output [`DWIDTH-1:0] matrixC15_15; +output [`DWIDTH-1:0] matrixC15_16; +output [`DWIDTH-1:0] matrixC15_17; +output [`DWIDTH-1:0] matrixC15_18; +output [`DWIDTH-1:0] matrixC15_19; +output [`DWIDTH-1:0] matrixC15_20; +output [`DWIDTH-1:0] matrixC15_21; +output [`DWIDTH-1:0] matrixC15_22; +output [`DWIDTH-1:0] matrixC15_23; +output [`DWIDTH-1:0] matrixC15_24; +output [`DWIDTH-1:0] matrixC15_25; +output [`DWIDTH-1:0] matrixC15_26; +output [`DWIDTH-1:0] matrixC15_27; +output [`DWIDTH-1:0] matrixC15_28; +output [`DWIDTH-1:0] matrixC15_29; +output [`DWIDTH-1:0] matrixC15_30; +output [`DWIDTH-1:0] matrixC15_31; +output [`DWIDTH-1:0] matrixC16_0; +output [`DWIDTH-1:0] matrixC16_1; +output [`DWIDTH-1:0] matrixC16_2; +output [`DWIDTH-1:0] matrixC16_3; +output [`DWIDTH-1:0] matrixC16_4; +output [`DWIDTH-1:0] matrixC16_5; +output [`DWIDTH-1:0] matrixC16_6; +output [`DWIDTH-1:0] matrixC16_7; +output [`DWIDTH-1:0] matrixC16_8; +output [`DWIDTH-1:0] matrixC16_9; +output [`DWIDTH-1:0] matrixC16_10; +output [`DWIDTH-1:0] matrixC16_11; +output [`DWIDTH-1:0] matrixC16_12; +output [`DWIDTH-1:0] matrixC16_13; +output [`DWIDTH-1:0] matrixC16_14; +output [`DWIDTH-1:0] matrixC16_15; +output [`DWIDTH-1:0] matrixC16_16; +output [`DWIDTH-1:0] matrixC16_17; +output [`DWIDTH-1:0] matrixC16_18; +output [`DWIDTH-1:0] matrixC16_19; +output [`DWIDTH-1:0] matrixC16_20; +output [`DWIDTH-1:0] matrixC16_21; +output [`DWIDTH-1:0] matrixC16_22; +output [`DWIDTH-1:0] matrixC16_23; +output [`DWIDTH-1:0] matrixC16_24; +output [`DWIDTH-1:0] matrixC16_25; +output [`DWIDTH-1:0] matrixC16_26; +output [`DWIDTH-1:0] matrixC16_27; +output [`DWIDTH-1:0] matrixC16_28; +output [`DWIDTH-1:0] matrixC16_29; +output [`DWIDTH-1:0] matrixC16_30; +output [`DWIDTH-1:0] matrixC16_31; +output [`DWIDTH-1:0] matrixC17_0; +output [`DWIDTH-1:0] matrixC17_1; +output [`DWIDTH-1:0] matrixC17_2; +output [`DWIDTH-1:0] matrixC17_3; +output [`DWIDTH-1:0] matrixC17_4; +output [`DWIDTH-1:0] matrixC17_5; +output [`DWIDTH-1:0] matrixC17_6; +output [`DWIDTH-1:0] matrixC17_7; +output [`DWIDTH-1:0] matrixC17_8; +output [`DWIDTH-1:0] matrixC17_9; +output [`DWIDTH-1:0] matrixC17_10; +output [`DWIDTH-1:0] matrixC17_11; +output [`DWIDTH-1:0] matrixC17_12; +output [`DWIDTH-1:0] matrixC17_13; +output [`DWIDTH-1:0] matrixC17_14; +output [`DWIDTH-1:0] matrixC17_15; +output [`DWIDTH-1:0] matrixC17_16; +output [`DWIDTH-1:0] matrixC17_17; +output [`DWIDTH-1:0] matrixC17_18; +output [`DWIDTH-1:0] matrixC17_19; +output [`DWIDTH-1:0] matrixC17_20; +output [`DWIDTH-1:0] matrixC17_21; +output [`DWIDTH-1:0] matrixC17_22; +output [`DWIDTH-1:0] matrixC17_23; +output [`DWIDTH-1:0] matrixC17_24; +output [`DWIDTH-1:0] matrixC17_25; +output [`DWIDTH-1:0] matrixC17_26; +output [`DWIDTH-1:0] matrixC17_27; +output [`DWIDTH-1:0] matrixC17_28; +output [`DWIDTH-1:0] matrixC17_29; +output [`DWIDTH-1:0] matrixC17_30; +output [`DWIDTH-1:0] matrixC17_31; +output [`DWIDTH-1:0] matrixC18_0; +output [`DWIDTH-1:0] matrixC18_1; +output [`DWIDTH-1:0] matrixC18_2; +output [`DWIDTH-1:0] matrixC18_3; +output [`DWIDTH-1:0] matrixC18_4; +output [`DWIDTH-1:0] matrixC18_5; +output [`DWIDTH-1:0] matrixC18_6; +output [`DWIDTH-1:0] matrixC18_7; +output [`DWIDTH-1:0] matrixC18_8; +output [`DWIDTH-1:0] matrixC18_9; +output [`DWIDTH-1:0] matrixC18_10; +output [`DWIDTH-1:0] matrixC18_11; +output [`DWIDTH-1:0] matrixC18_12; +output [`DWIDTH-1:0] matrixC18_13; +output [`DWIDTH-1:0] matrixC18_14; +output [`DWIDTH-1:0] matrixC18_15; +output [`DWIDTH-1:0] matrixC18_16; +output [`DWIDTH-1:0] matrixC18_17; +output [`DWIDTH-1:0] matrixC18_18; +output [`DWIDTH-1:0] matrixC18_19; +output [`DWIDTH-1:0] matrixC18_20; +output [`DWIDTH-1:0] matrixC18_21; +output [`DWIDTH-1:0] matrixC18_22; +output [`DWIDTH-1:0] matrixC18_23; +output [`DWIDTH-1:0] matrixC18_24; +output [`DWIDTH-1:0] matrixC18_25; +output [`DWIDTH-1:0] matrixC18_26; +output [`DWIDTH-1:0] matrixC18_27; +output [`DWIDTH-1:0] matrixC18_28; +output [`DWIDTH-1:0] matrixC18_29; +output [`DWIDTH-1:0] matrixC18_30; +output [`DWIDTH-1:0] matrixC18_31; +output [`DWIDTH-1:0] matrixC19_0; +output [`DWIDTH-1:0] matrixC19_1; +output [`DWIDTH-1:0] matrixC19_2; +output [`DWIDTH-1:0] matrixC19_3; +output [`DWIDTH-1:0] matrixC19_4; +output [`DWIDTH-1:0] matrixC19_5; +output [`DWIDTH-1:0] matrixC19_6; +output [`DWIDTH-1:0] matrixC19_7; +output [`DWIDTH-1:0] matrixC19_8; +output [`DWIDTH-1:0] matrixC19_9; +output [`DWIDTH-1:0] matrixC19_10; +output [`DWIDTH-1:0] matrixC19_11; +output [`DWIDTH-1:0] matrixC19_12; +output [`DWIDTH-1:0] matrixC19_13; +output [`DWIDTH-1:0] matrixC19_14; +output [`DWIDTH-1:0] matrixC19_15; +output [`DWIDTH-1:0] matrixC19_16; +output [`DWIDTH-1:0] matrixC19_17; +output [`DWIDTH-1:0] matrixC19_18; +output [`DWIDTH-1:0] matrixC19_19; +output [`DWIDTH-1:0] matrixC19_20; +output [`DWIDTH-1:0] matrixC19_21; +output [`DWIDTH-1:0] matrixC19_22; +output [`DWIDTH-1:0] matrixC19_23; +output [`DWIDTH-1:0] matrixC19_24; +output [`DWIDTH-1:0] matrixC19_25; +output [`DWIDTH-1:0] matrixC19_26; +output [`DWIDTH-1:0] matrixC19_27; +output [`DWIDTH-1:0] matrixC19_28; +output [`DWIDTH-1:0] matrixC19_29; +output [`DWIDTH-1:0] matrixC19_30; +output [`DWIDTH-1:0] matrixC19_31; +output [`DWIDTH-1:0] matrixC20_0; +output [`DWIDTH-1:0] matrixC20_1; +output [`DWIDTH-1:0] matrixC20_2; +output [`DWIDTH-1:0] matrixC20_3; +output [`DWIDTH-1:0] matrixC20_4; +output [`DWIDTH-1:0] matrixC20_5; +output [`DWIDTH-1:0] matrixC20_6; +output [`DWIDTH-1:0] matrixC20_7; +output [`DWIDTH-1:0] matrixC20_8; +output [`DWIDTH-1:0] matrixC20_9; +output [`DWIDTH-1:0] matrixC20_10; +output [`DWIDTH-1:0] matrixC20_11; +output [`DWIDTH-1:0] matrixC20_12; +output [`DWIDTH-1:0] matrixC20_13; +output [`DWIDTH-1:0] matrixC20_14; +output [`DWIDTH-1:0] matrixC20_15; +output [`DWIDTH-1:0] matrixC20_16; +output [`DWIDTH-1:0] matrixC20_17; +output [`DWIDTH-1:0] matrixC20_18; +output [`DWIDTH-1:0] matrixC20_19; +output [`DWIDTH-1:0] matrixC20_20; +output [`DWIDTH-1:0] matrixC20_21; +output [`DWIDTH-1:0] matrixC20_22; +output [`DWIDTH-1:0] matrixC20_23; +output [`DWIDTH-1:0] matrixC20_24; +output [`DWIDTH-1:0] matrixC20_25; +output [`DWIDTH-1:0] matrixC20_26; +output [`DWIDTH-1:0] matrixC20_27; +output [`DWIDTH-1:0] matrixC20_28; +output [`DWIDTH-1:0] matrixC20_29; +output [`DWIDTH-1:0] matrixC20_30; +output [`DWIDTH-1:0] matrixC20_31; +output [`DWIDTH-1:0] matrixC21_0; +output [`DWIDTH-1:0] matrixC21_1; +output [`DWIDTH-1:0] matrixC21_2; +output [`DWIDTH-1:0] matrixC21_3; +output [`DWIDTH-1:0] matrixC21_4; +output [`DWIDTH-1:0] matrixC21_5; +output [`DWIDTH-1:0] matrixC21_6; +output [`DWIDTH-1:0] matrixC21_7; +output [`DWIDTH-1:0] matrixC21_8; +output [`DWIDTH-1:0] matrixC21_9; +output [`DWIDTH-1:0] matrixC21_10; +output [`DWIDTH-1:0] matrixC21_11; +output [`DWIDTH-1:0] matrixC21_12; +output [`DWIDTH-1:0] matrixC21_13; +output [`DWIDTH-1:0] matrixC21_14; +output [`DWIDTH-1:0] matrixC21_15; +output [`DWIDTH-1:0] matrixC21_16; +output [`DWIDTH-1:0] matrixC21_17; +output [`DWIDTH-1:0] matrixC21_18; +output [`DWIDTH-1:0] matrixC21_19; +output [`DWIDTH-1:0] matrixC21_20; +output [`DWIDTH-1:0] matrixC21_21; +output [`DWIDTH-1:0] matrixC21_22; +output [`DWIDTH-1:0] matrixC21_23; +output [`DWIDTH-1:0] matrixC21_24; +output [`DWIDTH-1:0] matrixC21_25; +output [`DWIDTH-1:0] matrixC21_26; +output [`DWIDTH-1:0] matrixC21_27; +output [`DWIDTH-1:0] matrixC21_28; +output [`DWIDTH-1:0] matrixC21_29; +output [`DWIDTH-1:0] matrixC21_30; +output [`DWIDTH-1:0] matrixC21_31; +output [`DWIDTH-1:0] matrixC22_0; +output [`DWIDTH-1:0] matrixC22_1; +output [`DWIDTH-1:0] matrixC22_2; +output [`DWIDTH-1:0] matrixC22_3; +output [`DWIDTH-1:0] matrixC22_4; +output [`DWIDTH-1:0] matrixC22_5; +output [`DWIDTH-1:0] matrixC22_6; +output [`DWIDTH-1:0] matrixC22_7; +output [`DWIDTH-1:0] matrixC22_8; +output [`DWIDTH-1:0] matrixC22_9; +output [`DWIDTH-1:0] matrixC22_10; +output [`DWIDTH-1:0] matrixC22_11; +output [`DWIDTH-1:0] matrixC22_12; +output [`DWIDTH-1:0] matrixC22_13; +output [`DWIDTH-1:0] matrixC22_14; +output [`DWIDTH-1:0] matrixC22_15; +output [`DWIDTH-1:0] matrixC22_16; +output [`DWIDTH-1:0] matrixC22_17; +output [`DWIDTH-1:0] matrixC22_18; +output [`DWIDTH-1:0] matrixC22_19; +output [`DWIDTH-1:0] matrixC22_20; +output [`DWIDTH-1:0] matrixC22_21; +output [`DWIDTH-1:0] matrixC22_22; +output [`DWIDTH-1:0] matrixC22_23; +output [`DWIDTH-1:0] matrixC22_24; +output [`DWIDTH-1:0] matrixC22_25; +output [`DWIDTH-1:0] matrixC22_26; +output [`DWIDTH-1:0] matrixC22_27; +output [`DWIDTH-1:0] matrixC22_28; +output [`DWIDTH-1:0] matrixC22_29; +output [`DWIDTH-1:0] matrixC22_30; +output [`DWIDTH-1:0] matrixC22_31; +output [`DWIDTH-1:0] matrixC23_0; +output [`DWIDTH-1:0] matrixC23_1; +output [`DWIDTH-1:0] matrixC23_2; +output [`DWIDTH-1:0] matrixC23_3; +output [`DWIDTH-1:0] matrixC23_4; +output [`DWIDTH-1:0] matrixC23_5; +output [`DWIDTH-1:0] matrixC23_6; +output [`DWIDTH-1:0] matrixC23_7; +output [`DWIDTH-1:0] matrixC23_8; +output [`DWIDTH-1:0] matrixC23_9; +output [`DWIDTH-1:0] matrixC23_10; +output [`DWIDTH-1:0] matrixC23_11; +output [`DWIDTH-1:0] matrixC23_12; +output [`DWIDTH-1:0] matrixC23_13; +output [`DWIDTH-1:0] matrixC23_14; +output [`DWIDTH-1:0] matrixC23_15; +output [`DWIDTH-1:0] matrixC23_16; +output [`DWIDTH-1:0] matrixC23_17; +output [`DWIDTH-1:0] matrixC23_18; +output [`DWIDTH-1:0] matrixC23_19; +output [`DWIDTH-1:0] matrixC23_20; +output [`DWIDTH-1:0] matrixC23_21; +output [`DWIDTH-1:0] matrixC23_22; +output [`DWIDTH-1:0] matrixC23_23; +output [`DWIDTH-1:0] matrixC23_24; +output [`DWIDTH-1:0] matrixC23_25; +output [`DWIDTH-1:0] matrixC23_26; +output [`DWIDTH-1:0] matrixC23_27; +output [`DWIDTH-1:0] matrixC23_28; +output [`DWIDTH-1:0] matrixC23_29; +output [`DWIDTH-1:0] matrixC23_30; +output [`DWIDTH-1:0] matrixC23_31; +output [`DWIDTH-1:0] matrixC24_0; +output [`DWIDTH-1:0] matrixC24_1; +output [`DWIDTH-1:0] matrixC24_2; +output [`DWIDTH-1:0] matrixC24_3; +output [`DWIDTH-1:0] matrixC24_4; +output [`DWIDTH-1:0] matrixC24_5; +output [`DWIDTH-1:0] matrixC24_6; +output [`DWIDTH-1:0] matrixC24_7; +output [`DWIDTH-1:0] matrixC24_8; +output [`DWIDTH-1:0] matrixC24_9; +output [`DWIDTH-1:0] matrixC24_10; +output [`DWIDTH-1:0] matrixC24_11; +output [`DWIDTH-1:0] matrixC24_12; +output [`DWIDTH-1:0] matrixC24_13; +output [`DWIDTH-1:0] matrixC24_14; +output [`DWIDTH-1:0] matrixC24_15; +output [`DWIDTH-1:0] matrixC24_16; +output [`DWIDTH-1:0] matrixC24_17; +output [`DWIDTH-1:0] matrixC24_18; +output [`DWIDTH-1:0] matrixC24_19; +output [`DWIDTH-1:0] matrixC24_20; +output [`DWIDTH-1:0] matrixC24_21; +output [`DWIDTH-1:0] matrixC24_22; +output [`DWIDTH-1:0] matrixC24_23; +output [`DWIDTH-1:0] matrixC24_24; +output [`DWIDTH-1:0] matrixC24_25; +output [`DWIDTH-1:0] matrixC24_26; +output [`DWIDTH-1:0] matrixC24_27; +output [`DWIDTH-1:0] matrixC24_28; +output [`DWIDTH-1:0] matrixC24_29; +output [`DWIDTH-1:0] matrixC24_30; +output [`DWIDTH-1:0] matrixC24_31; +output [`DWIDTH-1:0] matrixC25_0; +output [`DWIDTH-1:0] matrixC25_1; +output [`DWIDTH-1:0] matrixC25_2; +output [`DWIDTH-1:0] matrixC25_3; +output [`DWIDTH-1:0] matrixC25_4; +output [`DWIDTH-1:0] matrixC25_5; +output [`DWIDTH-1:0] matrixC25_6; +output [`DWIDTH-1:0] matrixC25_7; +output [`DWIDTH-1:0] matrixC25_8; +output [`DWIDTH-1:0] matrixC25_9; +output [`DWIDTH-1:0] matrixC25_10; +output [`DWIDTH-1:0] matrixC25_11; +output [`DWIDTH-1:0] matrixC25_12; +output [`DWIDTH-1:0] matrixC25_13; +output [`DWIDTH-1:0] matrixC25_14; +output [`DWIDTH-1:0] matrixC25_15; +output [`DWIDTH-1:0] matrixC25_16; +output [`DWIDTH-1:0] matrixC25_17; +output [`DWIDTH-1:0] matrixC25_18; +output [`DWIDTH-1:0] matrixC25_19; +output [`DWIDTH-1:0] matrixC25_20; +output [`DWIDTH-1:0] matrixC25_21; +output [`DWIDTH-1:0] matrixC25_22; +output [`DWIDTH-1:0] matrixC25_23; +output [`DWIDTH-1:0] matrixC25_24; +output [`DWIDTH-1:0] matrixC25_25; +output [`DWIDTH-1:0] matrixC25_26; +output [`DWIDTH-1:0] matrixC25_27; +output [`DWIDTH-1:0] matrixC25_28; +output [`DWIDTH-1:0] matrixC25_29; +output [`DWIDTH-1:0] matrixC25_30; +output [`DWIDTH-1:0] matrixC25_31; +output [`DWIDTH-1:0] matrixC26_0; +output [`DWIDTH-1:0] matrixC26_1; +output [`DWIDTH-1:0] matrixC26_2; +output [`DWIDTH-1:0] matrixC26_3; +output [`DWIDTH-1:0] matrixC26_4; +output [`DWIDTH-1:0] matrixC26_5; +output [`DWIDTH-1:0] matrixC26_6; +output [`DWIDTH-1:0] matrixC26_7; +output [`DWIDTH-1:0] matrixC26_8; +output [`DWIDTH-1:0] matrixC26_9; +output [`DWIDTH-1:0] matrixC26_10; +output [`DWIDTH-1:0] matrixC26_11; +output [`DWIDTH-1:0] matrixC26_12; +output [`DWIDTH-1:0] matrixC26_13; +output [`DWIDTH-1:0] matrixC26_14; +output [`DWIDTH-1:0] matrixC26_15; +output [`DWIDTH-1:0] matrixC26_16; +output [`DWIDTH-1:0] matrixC26_17; +output [`DWIDTH-1:0] matrixC26_18; +output [`DWIDTH-1:0] matrixC26_19; +output [`DWIDTH-1:0] matrixC26_20; +output [`DWIDTH-1:0] matrixC26_21; +output [`DWIDTH-1:0] matrixC26_22; +output [`DWIDTH-1:0] matrixC26_23; +output [`DWIDTH-1:0] matrixC26_24; +output [`DWIDTH-1:0] matrixC26_25; +output [`DWIDTH-1:0] matrixC26_26; +output [`DWIDTH-1:0] matrixC26_27; +output [`DWIDTH-1:0] matrixC26_28; +output [`DWIDTH-1:0] matrixC26_29; +output [`DWIDTH-1:0] matrixC26_30; +output [`DWIDTH-1:0] matrixC26_31; +output [`DWIDTH-1:0] matrixC27_0; +output [`DWIDTH-1:0] matrixC27_1; +output [`DWIDTH-1:0] matrixC27_2; +output [`DWIDTH-1:0] matrixC27_3; +output [`DWIDTH-1:0] matrixC27_4; +output [`DWIDTH-1:0] matrixC27_5; +output [`DWIDTH-1:0] matrixC27_6; +output [`DWIDTH-1:0] matrixC27_7; +output [`DWIDTH-1:0] matrixC27_8; +output [`DWIDTH-1:0] matrixC27_9; +output [`DWIDTH-1:0] matrixC27_10; +output [`DWIDTH-1:0] matrixC27_11; +output [`DWIDTH-1:0] matrixC27_12; +output [`DWIDTH-1:0] matrixC27_13; +output [`DWIDTH-1:0] matrixC27_14; +output [`DWIDTH-1:0] matrixC27_15; +output [`DWIDTH-1:0] matrixC27_16; +output [`DWIDTH-1:0] matrixC27_17; +output [`DWIDTH-1:0] matrixC27_18; +output [`DWIDTH-1:0] matrixC27_19; +output [`DWIDTH-1:0] matrixC27_20; +output [`DWIDTH-1:0] matrixC27_21; +output [`DWIDTH-1:0] matrixC27_22; +output [`DWIDTH-1:0] matrixC27_23; +output [`DWIDTH-1:0] matrixC27_24; +output [`DWIDTH-1:0] matrixC27_25; +output [`DWIDTH-1:0] matrixC27_26; +output [`DWIDTH-1:0] matrixC27_27; +output [`DWIDTH-1:0] matrixC27_28; +output [`DWIDTH-1:0] matrixC27_29; +output [`DWIDTH-1:0] matrixC27_30; +output [`DWIDTH-1:0] matrixC27_31; +output [`DWIDTH-1:0] matrixC28_0; +output [`DWIDTH-1:0] matrixC28_1; +output [`DWIDTH-1:0] matrixC28_2; +output [`DWIDTH-1:0] matrixC28_3; +output [`DWIDTH-1:0] matrixC28_4; +output [`DWIDTH-1:0] matrixC28_5; +output [`DWIDTH-1:0] matrixC28_6; +output [`DWIDTH-1:0] matrixC28_7; +output [`DWIDTH-1:0] matrixC28_8; +output [`DWIDTH-1:0] matrixC28_9; +output [`DWIDTH-1:0] matrixC28_10; +output [`DWIDTH-1:0] matrixC28_11; +output [`DWIDTH-1:0] matrixC28_12; +output [`DWIDTH-1:0] matrixC28_13; +output [`DWIDTH-1:0] matrixC28_14; +output [`DWIDTH-1:0] matrixC28_15; +output [`DWIDTH-1:0] matrixC28_16; +output [`DWIDTH-1:0] matrixC28_17; +output [`DWIDTH-1:0] matrixC28_18; +output [`DWIDTH-1:0] matrixC28_19; +output [`DWIDTH-1:0] matrixC28_20; +output [`DWIDTH-1:0] matrixC28_21; +output [`DWIDTH-1:0] matrixC28_22; +output [`DWIDTH-1:0] matrixC28_23; +output [`DWIDTH-1:0] matrixC28_24; +output [`DWIDTH-1:0] matrixC28_25; +output [`DWIDTH-1:0] matrixC28_26; +output [`DWIDTH-1:0] matrixC28_27; +output [`DWIDTH-1:0] matrixC28_28; +output [`DWIDTH-1:0] matrixC28_29; +output [`DWIDTH-1:0] matrixC28_30; +output [`DWIDTH-1:0] matrixC28_31; +output [`DWIDTH-1:0] matrixC29_0; +output [`DWIDTH-1:0] matrixC29_1; +output [`DWIDTH-1:0] matrixC29_2; +output [`DWIDTH-1:0] matrixC29_3; +output [`DWIDTH-1:0] matrixC29_4; +output [`DWIDTH-1:0] matrixC29_5; +output [`DWIDTH-1:0] matrixC29_6; +output [`DWIDTH-1:0] matrixC29_7; +output [`DWIDTH-1:0] matrixC29_8; +output [`DWIDTH-1:0] matrixC29_9; +output [`DWIDTH-1:0] matrixC29_10; +output [`DWIDTH-1:0] matrixC29_11; +output [`DWIDTH-1:0] matrixC29_12; +output [`DWIDTH-1:0] matrixC29_13; +output [`DWIDTH-1:0] matrixC29_14; +output [`DWIDTH-1:0] matrixC29_15; +output [`DWIDTH-1:0] matrixC29_16; +output [`DWIDTH-1:0] matrixC29_17; +output [`DWIDTH-1:0] matrixC29_18; +output [`DWIDTH-1:0] matrixC29_19; +output [`DWIDTH-1:0] matrixC29_20; +output [`DWIDTH-1:0] matrixC29_21; +output [`DWIDTH-1:0] matrixC29_22; +output [`DWIDTH-1:0] matrixC29_23; +output [`DWIDTH-1:0] matrixC29_24; +output [`DWIDTH-1:0] matrixC29_25; +output [`DWIDTH-1:0] matrixC29_26; +output [`DWIDTH-1:0] matrixC29_27; +output [`DWIDTH-1:0] matrixC29_28; +output [`DWIDTH-1:0] matrixC29_29; +output [`DWIDTH-1:0] matrixC29_30; +output [`DWIDTH-1:0] matrixC29_31; +output [`DWIDTH-1:0] matrixC30_0; +output [`DWIDTH-1:0] matrixC30_1; +output [`DWIDTH-1:0] matrixC30_2; +output [`DWIDTH-1:0] matrixC30_3; +output [`DWIDTH-1:0] matrixC30_4; +output [`DWIDTH-1:0] matrixC30_5; +output [`DWIDTH-1:0] matrixC30_6; +output [`DWIDTH-1:0] matrixC30_7; +output [`DWIDTH-1:0] matrixC30_8; +output [`DWIDTH-1:0] matrixC30_9; +output [`DWIDTH-1:0] matrixC30_10; +output [`DWIDTH-1:0] matrixC30_11; +output [`DWIDTH-1:0] matrixC30_12; +output [`DWIDTH-1:0] matrixC30_13; +output [`DWIDTH-1:0] matrixC30_14; +output [`DWIDTH-1:0] matrixC30_15; +output [`DWIDTH-1:0] matrixC30_16; +output [`DWIDTH-1:0] matrixC30_17; +output [`DWIDTH-1:0] matrixC30_18; +output [`DWIDTH-1:0] matrixC30_19; +output [`DWIDTH-1:0] matrixC30_20; +output [`DWIDTH-1:0] matrixC30_21; +output [`DWIDTH-1:0] matrixC30_22; +output [`DWIDTH-1:0] matrixC30_23; +output [`DWIDTH-1:0] matrixC30_24; +output [`DWIDTH-1:0] matrixC30_25; +output [`DWIDTH-1:0] matrixC30_26; +output [`DWIDTH-1:0] matrixC30_27; +output [`DWIDTH-1:0] matrixC30_28; +output [`DWIDTH-1:0] matrixC30_29; +output [`DWIDTH-1:0] matrixC30_30; +output [`DWIDTH-1:0] matrixC30_31; +output [`DWIDTH-1:0] matrixC31_0; +output [`DWIDTH-1:0] matrixC31_1; +output [`DWIDTH-1:0] matrixC31_2; +output [`DWIDTH-1:0] matrixC31_3; +output [`DWIDTH-1:0] matrixC31_4; +output [`DWIDTH-1:0] matrixC31_5; +output [`DWIDTH-1:0] matrixC31_6; +output [`DWIDTH-1:0] matrixC31_7; +output [`DWIDTH-1:0] matrixC31_8; +output [`DWIDTH-1:0] matrixC31_9; +output [`DWIDTH-1:0] matrixC31_10; +output [`DWIDTH-1:0] matrixC31_11; +output [`DWIDTH-1:0] matrixC31_12; +output [`DWIDTH-1:0] matrixC31_13; +output [`DWIDTH-1:0] matrixC31_14; +output [`DWIDTH-1:0] matrixC31_15; +output [`DWIDTH-1:0] matrixC31_16; +output [`DWIDTH-1:0] matrixC31_17; +output [`DWIDTH-1:0] matrixC31_18; +output [`DWIDTH-1:0] matrixC31_19; +output [`DWIDTH-1:0] matrixC31_20; +output [`DWIDTH-1:0] matrixC31_21; +output [`DWIDTH-1:0] matrixC31_22; +output [`DWIDTH-1:0] matrixC31_23; +output [`DWIDTH-1:0] matrixC31_24; +output [`DWIDTH-1:0] matrixC31_25; +output [`DWIDTH-1:0] matrixC31_26; +output [`DWIDTH-1:0] matrixC31_27; +output [`DWIDTH-1:0] matrixC31_28; +output [`DWIDTH-1:0] matrixC31_29; +output [`DWIDTH-1:0] matrixC31_30; +output [`DWIDTH-1:0] matrixC31_31; + +output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + +wire [`DWIDTH-1:0] a0_0to0_1, a0_1to0_2, a0_2to0_3, a0_3to0_4, a0_4to0_5, a0_5to0_6, a0_6to0_7, a0_7to0_8, a0_8to0_9, a0_9to0_10, a0_10to0_11, a0_11to0_12, a0_12to0_13, a0_13to0_14, a0_14to0_15, a0_15to0_16, a0_16to0_17, a0_17to0_18, a0_18to0_19, a0_19to0_20, a0_20to0_21, a0_21to0_22, a0_22to0_23, a0_23to0_24, a0_24to0_25, a0_25to0_26, a0_26to0_27, a0_27to0_28, a0_28to0_29, a0_29to0_30, a0_30to0_31, a0_31to0_32; +wire [`DWIDTH-1:0] a1_0to1_1, a1_1to1_2, a1_2to1_3, a1_3to1_4, a1_4to1_5, a1_5to1_6, a1_6to1_7, a1_7to1_8, a1_8to1_9, a1_9to1_10, a1_10to1_11, a1_11to1_12, a1_12to1_13, a1_13to1_14, a1_14to1_15, a1_15to1_16, a1_16to1_17, a1_17to1_18, a1_18to1_19, a1_19to1_20, a1_20to1_21, a1_21to1_22, a1_22to1_23, a1_23to1_24, a1_24to1_25, a1_25to1_26, a1_26to1_27, a1_27to1_28, a1_28to1_29, a1_29to1_30, a1_30to1_31, a1_31to1_32; +wire [`DWIDTH-1:0] a2_0to2_1, a2_1to2_2, a2_2to2_3, a2_3to2_4, a2_4to2_5, a2_5to2_6, a2_6to2_7, a2_7to2_8, a2_8to2_9, a2_9to2_10, a2_10to2_11, a2_11to2_12, a2_12to2_13, a2_13to2_14, a2_14to2_15, a2_15to2_16, a2_16to2_17, a2_17to2_18, a2_18to2_19, a2_19to2_20, a2_20to2_21, a2_21to2_22, a2_22to2_23, a2_23to2_24, a2_24to2_25, a2_25to2_26, a2_26to2_27, a2_27to2_28, a2_28to2_29, a2_29to2_30, a2_30to2_31, a2_31to2_32; +wire [`DWIDTH-1:0] a3_0to3_1, a3_1to3_2, a3_2to3_3, a3_3to3_4, a3_4to3_5, a3_5to3_6, a3_6to3_7, a3_7to3_8, a3_8to3_9, a3_9to3_10, a3_10to3_11, a3_11to3_12, a3_12to3_13, a3_13to3_14, a3_14to3_15, a3_15to3_16, a3_16to3_17, a3_17to3_18, a3_18to3_19, a3_19to3_20, a3_20to3_21, a3_21to3_22, a3_22to3_23, a3_23to3_24, a3_24to3_25, a3_25to3_26, a3_26to3_27, a3_27to3_28, a3_28to3_29, a3_29to3_30, a3_30to3_31, a3_31to3_32; +wire [`DWIDTH-1:0] a4_0to4_1, a4_1to4_2, a4_2to4_3, a4_3to4_4, a4_4to4_5, a4_5to4_6, a4_6to4_7, a4_7to4_8, a4_8to4_9, a4_9to4_10, a4_10to4_11, a4_11to4_12, a4_12to4_13, a4_13to4_14, a4_14to4_15, a4_15to4_16, a4_16to4_17, a4_17to4_18, a4_18to4_19, a4_19to4_20, a4_20to4_21, a4_21to4_22, a4_22to4_23, a4_23to4_24, a4_24to4_25, a4_25to4_26, a4_26to4_27, a4_27to4_28, a4_28to4_29, a4_29to4_30, a4_30to4_31, a4_31to4_32; +wire [`DWIDTH-1:0] a5_0to5_1, a5_1to5_2, a5_2to5_3, a5_3to5_4, a5_4to5_5, a5_5to5_6, a5_6to5_7, a5_7to5_8, a5_8to5_9, a5_9to5_10, a5_10to5_11, a5_11to5_12, a5_12to5_13, a5_13to5_14, a5_14to5_15, a5_15to5_16, a5_16to5_17, a5_17to5_18, a5_18to5_19, a5_19to5_20, a5_20to5_21, a5_21to5_22, a5_22to5_23, a5_23to5_24, a5_24to5_25, a5_25to5_26, a5_26to5_27, a5_27to5_28, a5_28to5_29, a5_29to5_30, a5_30to5_31, a5_31to5_32; +wire [`DWIDTH-1:0] a6_0to6_1, a6_1to6_2, a6_2to6_3, a6_3to6_4, a6_4to6_5, a6_5to6_6, a6_6to6_7, a6_7to6_8, a6_8to6_9, a6_9to6_10, a6_10to6_11, a6_11to6_12, a6_12to6_13, a6_13to6_14, a6_14to6_15, a6_15to6_16, a6_16to6_17, a6_17to6_18, a6_18to6_19, a6_19to6_20, a6_20to6_21, a6_21to6_22, a6_22to6_23, a6_23to6_24, a6_24to6_25, a6_25to6_26, a6_26to6_27, a6_27to6_28, a6_28to6_29, a6_29to6_30, a6_30to6_31, a6_31to6_32; +wire [`DWIDTH-1:0] a7_0to7_1, a7_1to7_2, a7_2to7_3, a7_3to7_4, a7_4to7_5, a7_5to7_6, a7_6to7_7, a7_7to7_8, a7_8to7_9, a7_9to7_10, a7_10to7_11, a7_11to7_12, a7_12to7_13, a7_13to7_14, a7_14to7_15, a7_15to7_16, a7_16to7_17, a7_17to7_18, a7_18to7_19, a7_19to7_20, a7_20to7_21, a7_21to7_22, a7_22to7_23, a7_23to7_24, a7_24to7_25, a7_25to7_26, a7_26to7_27, a7_27to7_28, a7_28to7_29, a7_29to7_30, a7_30to7_31, a7_31to7_32; +wire [`DWIDTH-1:0] a8_0to8_1, a8_1to8_2, a8_2to8_3, a8_3to8_4, a8_4to8_5, a8_5to8_6, a8_6to8_7, a8_7to8_8, a8_8to8_9, a8_9to8_10, a8_10to8_11, a8_11to8_12, a8_12to8_13, a8_13to8_14, a8_14to8_15, a8_15to8_16, a8_16to8_17, a8_17to8_18, a8_18to8_19, a8_19to8_20, a8_20to8_21, a8_21to8_22, a8_22to8_23, a8_23to8_24, a8_24to8_25, a8_25to8_26, a8_26to8_27, a8_27to8_28, a8_28to8_29, a8_29to8_30, a8_30to8_31, a8_31to8_32; +wire [`DWIDTH-1:0] a9_0to9_1, a9_1to9_2, a9_2to9_3, a9_3to9_4, a9_4to9_5, a9_5to9_6, a9_6to9_7, a9_7to9_8, a9_8to9_9, a9_9to9_10, a9_10to9_11, a9_11to9_12, a9_12to9_13, a9_13to9_14, a9_14to9_15, a9_15to9_16, a9_16to9_17, a9_17to9_18, a9_18to9_19, a9_19to9_20, a9_20to9_21, a9_21to9_22, a9_22to9_23, a9_23to9_24, a9_24to9_25, a9_25to9_26, a9_26to9_27, a9_27to9_28, a9_28to9_29, a9_29to9_30, a9_30to9_31, a9_31to9_32; +wire [`DWIDTH-1:0] a10_0to10_1, a10_1to10_2, a10_2to10_3, a10_3to10_4, a10_4to10_5, a10_5to10_6, a10_6to10_7, a10_7to10_8, a10_8to10_9, a10_9to10_10, a10_10to10_11, a10_11to10_12, a10_12to10_13, a10_13to10_14, a10_14to10_15, a10_15to10_16, a10_16to10_17, a10_17to10_18, a10_18to10_19, a10_19to10_20, a10_20to10_21, a10_21to10_22, a10_22to10_23, a10_23to10_24, a10_24to10_25, a10_25to10_26, a10_26to10_27, a10_27to10_28, a10_28to10_29, a10_29to10_30, a10_30to10_31, a10_31to10_32; +wire [`DWIDTH-1:0] a11_0to11_1, a11_1to11_2, a11_2to11_3, a11_3to11_4, a11_4to11_5, a11_5to11_6, a11_6to11_7, a11_7to11_8, a11_8to11_9, a11_9to11_10, a11_10to11_11, a11_11to11_12, a11_12to11_13, a11_13to11_14, a11_14to11_15, a11_15to11_16, a11_16to11_17, a11_17to11_18, a11_18to11_19, a11_19to11_20, a11_20to11_21, a11_21to11_22, a11_22to11_23, a11_23to11_24, a11_24to11_25, a11_25to11_26, a11_26to11_27, a11_27to11_28, a11_28to11_29, a11_29to11_30, a11_30to11_31, a11_31to11_32; +wire [`DWIDTH-1:0] a12_0to12_1, a12_1to12_2, a12_2to12_3, a12_3to12_4, a12_4to12_5, a12_5to12_6, a12_6to12_7, a12_7to12_8, a12_8to12_9, a12_9to12_10, a12_10to12_11, a12_11to12_12, a12_12to12_13, a12_13to12_14, a12_14to12_15, a12_15to12_16, a12_16to12_17, a12_17to12_18, a12_18to12_19, a12_19to12_20, a12_20to12_21, a12_21to12_22, a12_22to12_23, a12_23to12_24, a12_24to12_25, a12_25to12_26, a12_26to12_27, a12_27to12_28, a12_28to12_29, a12_29to12_30, a12_30to12_31, a12_31to12_32; +wire [`DWIDTH-1:0] a13_0to13_1, a13_1to13_2, a13_2to13_3, a13_3to13_4, a13_4to13_5, a13_5to13_6, a13_6to13_7, a13_7to13_8, a13_8to13_9, a13_9to13_10, a13_10to13_11, a13_11to13_12, a13_12to13_13, a13_13to13_14, a13_14to13_15, a13_15to13_16, a13_16to13_17, a13_17to13_18, a13_18to13_19, a13_19to13_20, a13_20to13_21, a13_21to13_22, a13_22to13_23, a13_23to13_24, a13_24to13_25, a13_25to13_26, a13_26to13_27, a13_27to13_28, a13_28to13_29, a13_29to13_30, a13_30to13_31, a13_31to13_32; +wire [`DWIDTH-1:0] a14_0to14_1, a14_1to14_2, a14_2to14_3, a14_3to14_4, a14_4to14_5, a14_5to14_6, a14_6to14_7, a14_7to14_8, a14_8to14_9, a14_9to14_10, a14_10to14_11, a14_11to14_12, a14_12to14_13, a14_13to14_14, a14_14to14_15, a14_15to14_16, a14_16to14_17, a14_17to14_18, a14_18to14_19, a14_19to14_20, a14_20to14_21, a14_21to14_22, a14_22to14_23, a14_23to14_24, a14_24to14_25, a14_25to14_26, a14_26to14_27, a14_27to14_28, a14_28to14_29, a14_29to14_30, a14_30to14_31, a14_31to14_32; +wire [`DWIDTH-1:0] a15_0to15_1, a15_1to15_2, a15_2to15_3, a15_3to15_4, a15_4to15_5, a15_5to15_6, a15_6to15_7, a15_7to15_8, a15_8to15_9, a15_9to15_10, a15_10to15_11, a15_11to15_12, a15_12to15_13, a15_13to15_14, a15_14to15_15, a15_15to15_16, a15_16to15_17, a15_17to15_18, a15_18to15_19, a15_19to15_20, a15_20to15_21, a15_21to15_22, a15_22to15_23, a15_23to15_24, a15_24to15_25, a15_25to15_26, a15_26to15_27, a15_27to15_28, a15_28to15_29, a15_29to15_30, a15_30to15_31, a15_31to15_32; +wire [`DWIDTH-1:0] a16_0to16_1, a16_1to16_2, a16_2to16_3, a16_3to16_4, a16_4to16_5, a16_5to16_6, a16_6to16_7, a16_7to16_8, a16_8to16_9, a16_9to16_10, a16_10to16_11, a16_11to16_12, a16_12to16_13, a16_13to16_14, a16_14to16_15, a16_15to16_16, a16_16to16_17, a16_17to16_18, a16_18to16_19, a16_19to16_20, a16_20to16_21, a16_21to16_22, a16_22to16_23, a16_23to16_24, a16_24to16_25, a16_25to16_26, a16_26to16_27, a16_27to16_28, a16_28to16_29, a16_29to16_30, a16_30to16_31, a16_31to16_32; +wire [`DWIDTH-1:0] a17_0to17_1, a17_1to17_2, a17_2to17_3, a17_3to17_4, a17_4to17_5, a17_5to17_6, a17_6to17_7, a17_7to17_8, a17_8to17_9, a17_9to17_10, a17_10to17_11, a17_11to17_12, a17_12to17_13, a17_13to17_14, a17_14to17_15, a17_15to17_16, a17_16to17_17, a17_17to17_18, a17_18to17_19, a17_19to17_20, a17_20to17_21, a17_21to17_22, a17_22to17_23, a17_23to17_24, a17_24to17_25, a17_25to17_26, a17_26to17_27, a17_27to17_28, a17_28to17_29, a17_29to17_30, a17_30to17_31, a17_31to17_32; +wire [`DWIDTH-1:0] a18_0to18_1, a18_1to18_2, a18_2to18_3, a18_3to18_4, a18_4to18_5, a18_5to18_6, a18_6to18_7, a18_7to18_8, a18_8to18_9, a18_9to18_10, a18_10to18_11, a18_11to18_12, a18_12to18_13, a18_13to18_14, a18_14to18_15, a18_15to18_16, a18_16to18_17, a18_17to18_18, a18_18to18_19, a18_19to18_20, a18_20to18_21, a18_21to18_22, a18_22to18_23, a18_23to18_24, a18_24to18_25, a18_25to18_26, a18_26to18_27, a18_27to18_28, a18_28to18_29, a18_29to18_30, a18_30to18_31, a18_31to18_32; +wire [`DWIDTH-1:0] a19_0to19_1, a19_1to19_2, a19_2to19_3, a19_3to19_4, a19_4to19_5, a19_5to19_6, a19_6to19_7, a19_7to19_8, a19_8to19_9, a19_9to19_10, a19_10to19_11, a19_11to19_12, a19_12to19_13, a19_13to19_14, a19_14to19_15, a19_15to19_16, a19_16to19_17, a19_17to19_18, a19_18to19_19, a19_19to19_20, a19_20to19_21, a19_21to19_22, a19_22to19_23, a19_23to19_24, a19_24to19_25, a19_25to19_26, a19_26to19_27, a19_27to19_28, a19_28to19_29, a19_29to19_30, a19_30to19_31, a19_31to19_32; +wire [`DWIDTH-1:0] a20_0to20_1, a20_1to20_2, a20_2to20_3, a20_3to20_4, a20_4to20_5, a20_5to20_6, a20_6to20_7, a20_7to20_8, a20_8to20_9, a20_9to20_10, a20_10to20_11, a20_11to20_12, a20_12to20_13, a20_13to20_14, a20_14to20_15, a20_15to20_16, a20_16to20_17, a20_17to20_18, a20_18to20_19, a20_19to20_20, a20_20to20_21, a20_21to20_22, a20_22to20_23, a20_23to20_24, a20_24to20_25, a20_25to20_26, a20_26to20_27, a20_27to20_28, a20_28to20_29, a20_29to20_30, a20_30to20_31, a20_31to20_32; +wire [`DWIDTH-1:0] a21_0to21_1, a21_1to21_2, a21_2to21_3, a21_3to21_4, a21_4to21_5, a21_5to21_6, a21_6to21_7, a21_7to21_8, a21_8to21_9, a21_9to21_10, a21_10to21_11, a21_11to21_12, a21_12to21_13, a21_13to21_14, a21_14to21_15, a21_15to21_16, a21_16to21_17, a21_17to21_18, a21_18to21_19, a21_19to21_20, a21_20to21_21, a21_21to21_22, a21_22to21_23, a21_23to21_24, a21_24to21_25, a21_25to21_26, a21_26to21_27, a21_27to21_28, a21_28to21_29, a21_29to21_30, a21_30to21_31, a21_31to21_32; +wire [`DWIDTH-1:0] a22_0to22_1, a22_1to22_2, a22_2to22_3, a22_3to22_4, a22_4to22_5, a22_5to22_6, a22_6to22_7, a22_7to22_8, a22_8to22_9, a22_9to22_10, a22_10to22_11, a22_11to22_12, a22_12to22_13, a22_13to22_14, a22_14to22_15, a22_15to22_16, a22_16to22_17, a22_17to22_18, a22_18to22_19, a22_19to22_20, a22_20to22_21, a22_21to22_22, a22_22to22_23, a22_23to22_24, a22_24to22_25, a22_25to22_26, a22_26to22_27, a22_27to22_28, a22_28to22_29, a22_29to22_30, a22_30to22_31, a22_31to22_32; +wire [`DWIDTH-1:0] a23_0to23_1, a23_1to23_2, a23_2to23_3, a23_3to23_4, a23_4to23_5, a23_5to23_6, a23_6to23_7, a23_7to23_8, a23_8to23_9, a23_9to23_10, a23_10to23_11, a23_11to23_12, a23_12to23_13, a23_13to23_14, a23_14to23_15, a23_15to23_16, a23_16to23_17, a23_17to23_18, a23_18to23_19, a23_19to23_20, a23_20to23_21, a23_21to23_22, a23_22to23_23, a23_23to23_24, a23_24to23_25, a23_25to23_26, a23_26to23_27, a23_27to23_28, a23_28to23_29, a23_29to23_30, a23_30to23_31, a23_31to23_32; +wire [`DWIDTH-1:0] a24_0to24_1, a24_1to24_2, a24_2to24_3, a24_3to24_4, a24_4to24_5, a24_5to24_6, a24_6to24_7, a24_7to24_8, a24_8to24_9, a24_9to24_10, a24_10to24_11, a24_11to24_12, a24_12to24_13, a24_13to24_14, a24_14to24_15, a24_15to24_16, a24_16to24_17, a24_17to24_18, a24_18to24_19, a24_19to24_20, a24_20to24_21, a24_21to24_22, a24_22to24_23, a24_23to24_24, a24_24to24_25, a24_25to24_26, a24_26to24_27, a24_27to24_28, a24_28to24_29, a24_29to24_30, a24_30to24_31, a24_31to24_32; +wire [`DWIDTH-1:0] a25_0to25_1, a25_1to25_2, a25_2to25_3, a25_3to25_4, a25_4to25_5, a25_5to25_6, a25_6to25_7, a25_7to25_8, a25_8to25_9, a25_9to25_10, a25_10to25_11, a25_11to25_12, a25_12to25_13, a25_13to25_14, a25_14to25_15, a25_15to25_16, a25_16to25_17, a25_17to25_18, a25_18to25_19, a25_19to25_20, a25_20to25_21, a25_21to25_22, a25_22to25_23, a25_23to25_24, a25_24to25_25, a25_25to25_26, a25_26to25_27, a25_27to25_28, a25_28to25_29, a25_29to25_30, a25_30to25_31, a25_31to25_32; +wire [`DWIDTH-1:0] a26_0to26_1, a26_1to26_2, a26_2to26_3, a26_3to26_4, a26_4to26_5, a26_5to26_6, a26_6to26_7, a26_7to26_8, a26_8to26_9, a26_9to26_10, a26_10to26_11, a26_11to26_12, a26_12to26_13, a26_13to26_14, a26_14to26_15, a26_15to26_16, a26_16to26_17, a26_17to26_18, a26_18to26_19, a26_19to26_20, a26_20to26_21, a26_21to26_22, a26_22to26_23, a26_23to26_24, a26_24to26_25, a26_25to26_26, a26_26to26_27, a26_27to26_28, a26_28to26_29, a26_29to26_30, a26_30to26_31, a26_31to26_32; +wire [`DWIDTH-1:0] a27_0to27_1, a27_1to27_2, a27_2to27_3, a27_3to27_4, a27_4to27_5, a27_5to27_6, a27_6to27_7, a27_7to27_8, a27_8to27_9, a27_9to27_10, a27_10to27_11, a27_11to27_12, a27_12to27_13, a27_13to27_14, a27_14to27_15, a27_15to27_16, a27_16to27_17, a27_17to27_18, a27_18to27_19, a27_19to27_20, a27_20to27_21, a27_21to27_22, a27_22to27_23, a27_23to27_24, a27_24to27_25, a27_25to27_26, a27_26to27_27, a27_27to27_28, a27_28to27_29, a27_29to27_30, a27_30to27_31, a27_31to27_32; +wire [`DWIDTH-1:0] a28_0to28_1, a28_1to28_2, a28_2to28_3, a28_3to28_4, a28_4to28_5, a28_5to28_6, a28_6to28_7, a28_7to28_8, a28_8to28_9, a28_9to28_10, a28_10to28_11, a28_11to28_12, a28_12to28_13, a28_13to28_14, a28_14to28_15, a28_15to28_16, a28_16to28_17, a28_17to28_18, a28_18to28_19, a28_19to28_20, a28_20to28_21, a28_21to28_22, a28_22to28_23, a28_23to28_24, a28_24to28_25, a28_25to28_26, a28_26to28_27, a28_27to28_28, a28_28to28_29, a28_29to28_30, a28_30to28_31, a28_31to28_32; +wire [`DWIDTH-1:0] a29_0to29_1, a29_1to29_2, a29_2to29_3, a29_3to29_4, a29_4to29_5, a29_5to29_6, a29_6to29_7, a29_7to29_8, a29_8to29_9, a29_9to29_10, a29_10to29_11, a29_11to29_12, a29_12to29_13, a29_13to29_14, a29_14to29_15, a29_15to29_16, a29_16to29_17, a29_17to29_18, a29_18to29_19, a29_19to29_20, a29_20to29_21, a29_21to29_22, a29_22to29_23, a29_23to29_24, a29_24to29_25, a29_25to29_26, a29_26to29_27, a29_27to29_28, a29_28to29_29, a29_29to29_30, a29_30to29_31, a29_31to29_32; +wire [`DWIDTH-1:0] a30_0to30_1, a30_1to30_2, a30_2to30_3, a30_3to30_4, a30_4to30_5, a30_5to30_6, a30_6to30_7, a30_7to30_8, a30_8to30_9, a30_9to30_10, a30_10to30_11, a30_11to30_12, a30_12to30_13, a30_13to30_14, a30_14to30_15, a30_15to30_16, a30_16to30_17, a30_17to30_18, a30_18to30_19, a30_19to30_20, a30_20to30_21, a30_21to30_22, a30_22to30_23, a30_23to30_24, a30_24to30_25, a30_25to30_26, a30_26to30_27, a30_27to30_28, a30_28to30_29, a30_29to30_30, a30_30to30_31, a30_31to30_32; +wire [`DWIDTH-1:0] a31_0to31_1, a31_1to31_2, a31_2to31_3, a31_3to31_4, a31_4to31_5, a31_5to31_6, a31_6to31_7, a31_7to31_8, a31_8to31_9, a31_9to31_10, a31_10to31_11, a31_11to31_12, a31_12to31_13, a31_13to31_14, a31_14to31_15, a31_15to31_16, a31_16to31_17, a31_17to31_18, a31_18to31_19, a31_19to31_20, a31_20to31_21, a31_21to31_22, a31_22to31_23, a31_23to31_24, a31_24to31_25, a31_25to31_26, a31_26to31_27, a31_27to31_28, a31_28to31_29, a31_29to31_30, a31_30to31_31, a31_31to31_32; + +wire [18:0] b0_0to1_0, b1_0to2_0, b2_0to3_0, b3_0to4_0, b4_0to5_0, b5_0to6_0, b6_0to7_0, b7_0to8_0, b8_0to9_0, b9_0to10_0, b10_0to11_0, b11_0to12_0, b12_0to13_0, b13_0to14_0, b14_0to15_0, b15_0to16_0, b16_0to17_0, b17_0to18_0, b18_0to19_0, b19_0to20_0, b20_0to21_0, b21_0to22_0, b22_0to23_0, b23_0to24_0, b24_0to25_0, b25_0to26_0, b26_0to27_0, b27_0to28_0, b28_0to29_0, b29_0to30_0, b30_0to31_0, b31_0to32_0; +wire [18:0] b0_1to1_1, b1_1to2_1, b2_1to3_1, b3_1to4_1, b4_1to5_1, b5_1to6_1, b6_1to7_1, b7_1to8_1, b8_1to9_1, b9_1to10_1, b10_1to11_1, b11_1to12_1, b12_1to13_1, b13_1to14_1, b14_1to15_1, b15_1to16_1, b16_1to17_1, b17_1to18_1, b18_1to19_1, b19_1to20_1, b20_1to21_1, b21_1to22_1, b22_1to23_1, b23_1to24_1, b24_1to25_1, b25_1to26_1, b26_1to27_1, b27_1to28_1, b28_1to29_1, b29_1to30_1, b30_1to31_1, b31_1to32_1; +wire [18:0] b0_2to1_2, b1_2to2_2, b2_2to3_2, b3_2to4_2, b4_2to5_2, b5_2to6_2, b6_2to7_2, b7_2to8_2, b8_2to9_2, b9_2to10_2, b10_2to11_2, b11_2to12_2, b12_2to13_2, b13_2to14_2, b14_2to15_2, b15_2to16_2, b16_2to17_2, b17_2to18_2, b18_2to19_2, b19_2to20_2, b20_2to21_2, b21_2to22_2, b22_2to23_2, b23_2to24_2, b24_2to25_2, b25_2to26_2, b26_2to27_2, b27_2to28_2, b28_2to29_2, b29_2to30_2, b30_2to31_2, b31_2to32_2; +wire [18:0] b0_3to1_3, b1_3to2_3, b2_3to3_3, b3_3to4_3, b4_3to5_3, b5_3to6_3, b6_3to7_3, b7_3to8_3, b8_3to9_3, b9_3to10_3, b10_3to11_3, b11_3to12_3, b12_3to13_3, b13_3to14_3, b14_3to15_3, b15_3to16_3, b16_3to17_3, b17_3to18_3, b18_3to19_3, b19_3to20_3, b20_3to21_3, b21_3to22_3, b22_3to23_3, b23_3to24_3, b24_3to25_3, b25_3to26_3, b26_3to27_3, b27_3to28_3, b28_3to29_3, b29_3to30_3, b30_3to31_3, b31_3to32_3; +wire [18:0] b0_4to1_4, b1_4to2_4, b2_4to3_4, b3_4to4_4, b4_4to5_4, b5_4to6_4, b6_4to7_4, b7_4to8_4, b8_4to9_4, b9_4to10_4, b10_4to11_4, b11_4to12_4, b12_4to13_4, b13_4to14_4, b14_4to15_4, b15_4to16_4, b16_4to17_4, b17_4to18_4, b18_4to19_4, b19_4to20_4, b20_4to21_4, b21_4to22_4, b22_4to23_4, b23_4to24_4, b24_4to25_4, b25_4to26_4, b26_4to27_4, b27_4to28_4, b28_4to29_4, b29_4to30_4, b30_4to31_4, b31_4to32_4; +wire [18:0] b0_5to1_5, b1_5to2_5, b2_5to3_5, b3_5to4_5, b4_5to5_5, b5_5to6_5, b6_5to7_5, b7_5to8_5, b8_5to9_5, b9_5to10_5, b10_5to11_5, b11_5to12_5, b12_5to13_5, b13_5to14_5, b14_5to15_5, b15_5to16_5, b16_5to17_5, b17_5to18_5, b18_5to19_5, b19_5to20_5, b20_5to21_5, b21_5to22_5, b22_5to23_5, b23_5to24_5, b24_5to25_5, b25_5to26_5, b26_5to27_5, b27_5to28_5, b28_5to29_5, b29_5to30_5, b30_5to31_5, b31_5to32_5; +wire [18:0] b0_6to1_6, b1_6to2_6, b2_6to3_6, b3_6to4_6, b4_6to5_6, b5_6to6_6, b6_6to7_6, b7_6to8_6, b8_6to9_6, b9_6to10_6, b10_6to11_6, b11_6to12_6, b12_6to13_6, b13_6to14_6, b14_6to15_6, b15_6to16_6, b16_6to17_6, b17_6to18_6, b18_6to19_6, b19_6to20_6, b20_6to21_6, b21_6to22_6, b22_6to23_6, b23_6to24_6, b24_6to25_6, b25_6to26_6, b26_6to27_6, b27_6to28_6, b28_6to29_6, b29_6to30_6, b30_6to31_6, b31_6to32_6; +wire [18:0] b0_7to1_7, b1_7to2_7, b2_7to3_7, b3_7to4_7, b4_7to5_7, b5_7to6_7, b6_7to7_7, b7_7to8_7, b8_7to9_7, b9_7to10_7, b10_7to11_7, b11_7to12_7, b12_7to13_7, b13_7to14_7, b14_7to15_7, b15_7to16_7, b16_7to17_7, b17_7to18_7, b18_7to19_7, b19_7to20_7, b20_7to21_7, b21_7to22_7, b22_7to23_7, b23_7to24_7, b24_7to25_7, b25_7to26_7, b26_7to27_7, b27_7to28_7, b28_7to29_7, b29_7to30_7, b30_7to31_7, b31_7to32_7; +wire [18:0] b0_8to1_8, b1_8to2_8, b2_8to3_8, b3_8to4_8, b4_8to5_8, b5_8to6_8, b6_8to7_8, b7_8to8_8, b8_8to9_8, b9_8to10_8, b10_8to11_8, b11_8to12_8, b12_8to13_8, b13_8to14_8, b14_8to15_8, b15_8to16_8, b16_8to17_8, b17_8to18_8, b18_8to19_8, b19_8to20_8, b20_8to21_8, b21_8to22_8, b22_8to23_8, b23_8to24_8, b24_8to25_8, b25_8to26_8, b26_8to27_8, b27_8to28_8, b28_8to29_8, b29_8to30_8, b30_8to31_8, b31_8to32_8; +wire [18:0] b0_9to1_9, b1_9to2_9, b2_9to3_9, b3_9to4_9, b4_9to5_9, b5_9to6_9, b6_9to7_9, b7_9to8_9, b8_9to9_9, b9_9to10_9, b10_9to11_9, b11_9to12_9, b12_9to13_9, b13_9to14_9, b14_9to15_9, b15_9to16_9, b16_9to17_9, b17_9to18_9, b18_9to19_9, b19_9to20_9, b20_9to21_9, b21_9to22_9, b22_9to23_9, b23_9to24_9, b24_9to25_9, b25_9to26_9, b26_9to27_9, b27_9to28_9, b28_9to29_9, b29_9to30_9, b30_9to31_9, b31_9to32_9; +wire [18:0] b0_10to1_10, b1_10to2_10, b2_10to3_10, b3_10to4_10, b4_10to5_10, b5_10to6_10, b6_10to7_10, b7_10to8_10, b8_10to9_10, b9_10to10_10, b10_10to11_10, b11_10to12_10, b12_10to13_10, b13_10to14_10, b14_10to15_10, b15_10to16_10, b16_10to17_10, b17_10to18_10, b18_10to19_10, b19_10to20_10, b20_10to21_10, b21_10to22_10, b22_10to23_10, b23_10to24_10, b24_10to25_10, b25_10to26_10, b26_10to27_10, b27_10to28_10, b28_10to29_10, b29_10to30_10, b30_10to31_10, b31_10to32_10; +wire [18:0] b0_11to1_11, b1_11to2_11, b2_11to3_11, b3_11to4_11, b4_11to5_11, b5_11to6_11, b6_11to7_11, b7_11to8_11, b8_11to9_11, b9_11to10_11, b10_11to11_11, b11_11to12_11, b12_11to13_11, b13_11to14_11, b14_11to15_11, b15_11to16_11, b16_11to17_11, b17_11to18_11, b18_11to19_11, b19_11to20_11, b20_11to21_11, b21_11to22_11, b22_11to23_11, b23_11to24_11, b24_11to25_11, b25_11to26_11, b26_11to27_11, b27_11to28_11, b28_11to29_11, b29_11to30_11, b30_11to31_11, b31_11to32_11; +wire [18:0] b0_12to1_12, b1_12to2_12, b2_12to3_12, b3_12to4_12, b4_12to5_12, b5_12to6_12, b6_12to7_12, b7_12to8_12, b8_12to9_12, b9_12to10_12, b10_12to11_12, b11_12to12_12, b12_12to13_12, b13_12to14_12, b14_12to15_12, b15_12to16_12, b16_12to17_12, b17_12to18_12, b18_12to19_12, b19_12to20_12, b20_12to21_12, b21_12to22_12, b22_12to23_12, b23_12to24_12, b24_12to25_12, b25_12to26_12, b26_12to27_12, b27_12to28_12, b28_12to29_12, b29_12to30_12, b30_12to31_12, b31_12to32_12; +wire [18:0] b0_13to1_13, b1_13to2_13, b2_13to3_13, b3_13to4_13, b4_13to5_13, b5_13to6_13, b6_13to7_13, b7_13to8_13, b8_13to9_13, b9_13to10_13, b10_13to11_13, b11_13to12_13, b12_13to13_13, b13_13to14_13, b14_13to15_13, b15_13to16_13, b16_13to17_13, b17_13to18_13, b18_13to19_13, b19_13to20_13, b20_13to21_13, b21_13to22_13, b22_13to23_13, b23_13to24_13, b24_13to25_13, b25_13to26_13, b26_13to27_13, b27_13to28_13, b28_13to29_13, b29_13to30_13, b30_13to31_13, b31_13to32_13; +wire [18:0] b0_14to1_14, b1_14to2_14, b2_14to3_14, b3_14to4_14, b4_14to5_14, b5_14to6_14, b6_14to7_14, b7_14to8_14, b8_14to9_14, b9_14to10_14, b10_14to11_14, b11_14to12_14, b12_14to13_14, b13_14to14_14, b14_14to15_14, b15_14to16_14, b16_14to17_14, b17_14to18_14, b18_14to19_14, b19_14to20_14, b20_14to21_14, b21_14to22_14, b22_14to23_14, b23_14to24_14, b24_14to25_14, b25_14to26_14, b26_14to27_14, b27_14to28_14, b28_14to29_14, b29_14to30_14, b30_14to31_14, b31_14to32_14; +wire [18:0] b0_15to1_15, b1_15to2_15, b2_15to3_15, b3_15to4_15, b4_15to5_15, b5_15to6_15, b6_15to7_15, b7_15to8_15, b8_15to9_15, b9_15to10_15, b10_15to11_15, b11_15to12_15, b12_15to13_15, b13_15to14_15, b14_15to15_15, b15_15to16_15, b16_15to17_15, b17_15to18_15, b18_15to19_15, b19_15to20_15, b20_15to21_15, b21_15to22_15, b22_15to23_15, b23_15to24_15, b24_15to25_15, b25_15to26_15, b26_15to27_15, b27_15to28_15, b28_15to29_15, b29_15to30_15, b30_15to31_15, b31_15to32_15; +wire [18:0] b0_16to1_16, b1_16to2_16, b2_16to3_16, b3_16to4_16, b4_16to5_16, b5_16to6_16, b6_16to7_16, b7_16to8_16, b8_16to9_16, b9_16to10_16, b10_16to11_16, b11_16to12_16, b12_16to13_16, b13_16to14_16, b14_16to15_16, b15_16to16_16, b16_16to17_16, b17_16to18_16, b18_16to19_16, b19_16to20_16, b20_16to21_16, b21_16to22_16, b22_16to23_16, b23_16to24_16, b24_16to25_16, b25_16to26_16, b26_16to27_16, b27_16to28_16, b28_16to29_16, b29_16to30_16, b30_16to31_16, b31_16to32_16; +wire [18:0] b0_17to1_17, b1_17to2_17, b2_17to3_17, b3_17to4_17, b4_17to5_17, b5_17to6_17, b6_17to7_17, b7_17to8_17, b8_17to9_17, b9_17to10_17, b10_17to11_17, b11_17to12_17, b12_17to13_17, b13_17to14_17, b14_17to15_17, b15_17to16_17, b16_17to17_17, b17_17to18_17, b18_17to19_17, b19_17to20_17, b20_17to21_17, b21_17to22_17, b22_17to23_17, b23_17to24_17, b24_17to25_17, b25_17to26_17, b26_17to27_17, b27_17to28_17, b28_17to29_17, b29_17to30_17, b30_17to31_17, b31_17to32_17; +wire [18:0] b0_18to1_18, b1_18to2_18, b2_18to3_18, b3_18to4_18, b4_18to5_18, b5_18to6_18, b6_18to7_18, b7_18to8_18, b8_18to9_18, b9_18to10_18, b10_18to11_18, b11_18to12_18, b12_18to13_18, b13_18to14_18, b14_18to15_18, b15_18to16_18, b16_18to17_18, b17_18to18_18, b18_18to19_18, b19_18to20_18, b20_18to21_18, b21_18to22_18, b22_18to23_18, b23_18to24_18, b24_18to25_18, b25_18to26_18, b26_18to27_18, b27_18to28_18, b28_18to29_18, b29_18to30_18, b30_18to31_18, b31_18to32_18; +wire [18:0] b0_19to1_19, b1_19to2_19, b2_19to3_19, b3_19to4_19, b4_19to5_19, b5_19to6_19, b6_19to7_19, b7_19to8_19, b8_19to9_19, b9_19to10_19, b10_19to11_19, b11_19to12_19, b12_19to13_19, b13_19to14_19, b14_19to15_19, b15_19to16_19, b16_19to17_19, b17_19to18_19, b18_19to19_19, b19_19to20_19, b20_19to21_19, b21_19to22_19, b22_19to23_19, b23_19to24_19, b24_19to25_19, b25_19to26_19, b26_19to27_19, b27_19to28_19, b28_19to29_19, b29_19to30_19, b30_19to31_19, b31_19to32_19; +wire [18:0] b0_20to1_20, b1_20to2_20, b2_20to3_20, b3_20to4_20, b4_20to5_20, b5_20to6_20, b6_20to7_20, b7_20to8_20, b8_20to9_20, b9_20to10_20, b10_20to11_20, b11_20to12_20, b12_20to13_20, b13_20to14_20, b14_20to15_20, b15_20to16_20, b16_20to17_20, b17_20to18_20, b18_20to19_20, b19_20to20_20, b20_20to21_20, b21_20to22_20, b22_20to23_20, b23_20to24_20, b24_20to25_20, b25_20to26_20, b26_20to27_20, b27_20to28_20, b28_20to29_20, b29_20to30_20, b30_20to31_20, b31_20to32_20; +wire [18:0] b0_21to1_21, b1_21to2_21, b2_21to3_21, b3_21to4_21, b4_21to5_21, b5_21to6_21, b6_21to7_21, b7_21to8_21, b8_21to9_21, b9_21to10_21, b10_21to11_21, b11_21to12_21, b12_21to13_21, b13_21to14_21, b14_21to15_21, b15_21to16_21, b16_21to17_21, b17_21to18_21, b18_21to19_21, b19_21to20_21, b20_21to21_21, b21_21to22_21, b22_21to23_21, b23_21to24_21, b24_21to25_21, b25_21to26_21, b26_21to27_21, b27_21to28_21, b28_21to29_21, b29_21to30_21, b30_21to31_21, b31_21to32_21; +wire [18:0] b0_22to1_22, b1_22to2_22, b2_22to3_22, b3_22to4_22, b4_22to5_22, b5_22to6_22, b6_22to7_22, b7_22to8_22, b8_22to9_22, b9_22to10_22, b10_22to11_22, b11_22to12_22, b12_22to13_22, b13_22to14_22, b14_22to15_22, b15_22to16_22, b16_22to17_22, b17_22to18_22, b18_22to19_22, b19_22to20_22, b20_22to21_22, b21_22to22_22, b22_22to23_22, b23_22to24_22, b24_22to25_22, b25_22to26_22, b26_22to27_22, b27_22to28_22, b28_22to29_22, b29_22to30_22, b30_22to31_22, b31_22to32_22; +wire [18:0] b0_23to1_23, b1_23to2_23, b2_23to3_23, b3_23to4_23, b4_23to5_23, b5_23to6_23, b6_23to7_23, b7_23to8_23, b8_23to9_23, b9_23to10_23, b10_23to11_23, b11_23to12_23, b12_23to13_23, b13_23to14_23, b14_23to15_23, b15_23to16_23, b16_23to17_23, b17_23to18_23, b18_23to19_23, b19_23to20_23, b20_23to21_23, b21_23to22_23, b22_23to23_23, b23_23to24_23, b24_23to25_23, b25_23to26_23, b26_23to27_23, b27_23to28_23, b28_23to29_23, b29_23to30_23, b30_23to31_23, b31_23to32_23; +wire [18:0] b0_24to1_24, b1_24to2_24, b2_24to3_24, b3_24to4_24, b4_24to5_24, b5_24to6_24, b6_24to7_24, b7_24to8_24, b8_24to9_24, b9_24to10_24, b10_24to11_24, b11_24to12_24, b12_24to13_24, b13_24to14_24, b14_24to15_24, b15_24to16_24, b16_24to17_24, b17_24to18_24, b18_24to19_24, b19_24to20_24, b20_24to21_24, b21_24to22_24, b22_24to23_24, b23_24to24_24, b24_24to25_24, b25_24to26_24, b26_24to27_24, b27_24to28_24, b28_24to29_24, b29_24to30_24, b30_24to31_24, b31_24to32_24; +wire [18:0] b0_25to1_25, b1_25to2_25, b2_25to3_25, b3_25to4_25, b4_25to5_25, b5_25to6_25, b6_25to7_25, b7_25to8_25, b8_25to9_25, b9_25to10_25, b10_25to11_25, b11_25to12_25, b12_25to13_25, b13_25to14_25, b14_25to15_25, b15_25to16_25, b16_25to17_25, b17_25to18_25, b18_25to19_25, b19_25to20_25, b20_25to21_25, b21_25to22_25, b22_25to23_25, b23_25to24_25, b24_25to25_25, b25_25to26_25, b26_25to27_25, b27_25to28_25, b28_25to29_25, b29_25to30_25, b30_25to31_25, b31_25to32_25; +wire [18:0] b0_26to1_26, b1_26to2_26, b2_26to3_26, b3_26to4_26, b4_26to5_26, b5_26to6_26, b6_26to7_26, b7_26to8_26, b8_26to9_26, b9_26to10_26, b10_26to11_26, b11_26to12_26, b12_26to13_26, b13_26to14_26, b14_26to15_26, b15_26to16_26, b16_26to17_26, b17_26to18_26, b18_26to19_26, b19_26to20_26, b20_26to21_26, b21_26to22_26, b22_26to23_26, b23_26to24_26, b24_26to25_26, b25_26to26_26, b26_26to27_26, b27_26to28_26, b28_26to29_26, b29_26to30_26, b30_26to31_26, b31_26to32_26; +wire [18:0] b0_27to1_27, b1_27to2_27, b2_27to3_27, b3_27to4_27, b4_27to5_27, b5_27to6_27, b6_27to7_27, b7_27to8_27, b8_27to9_27, b9_27to10_27, b10_27to11_27, b11_27to12_27, b12_27to13_27, b13_27to14_27, b14_27to15_27, b15_27to16_27, b16_27to17_27, b17_27to18_27, b18_27to19_27, b19_27to20_27, b20_27to21_27, b21_27to22_27, b22_27to23_27, b23_27to24_27, b24_27to25_27, b25_27to26_27, b26_27to27_27, b27_27to28_27, b28_27to29_27, b29_27to30_27, b30_27to31_27, b31_27to32_27; +wire [18:0] b0_28to1_28, b1_28to2_28, b2_28to3_28, b3_28to4_28, b4_28to5_28, b5_28to6_28, b6_28to7_28, b7_28to8_28, b8_28to9_28, b9_28to10_28, b10_28to11_28, b11_28to12_28, b12_28to13_28, b13_28to14_28, b14_28to15_28, b15_28to16_28, b16_28to17_28, b17_28to18_28, b18_28to19_28, b19_28to20_28, b20_28to21_28, b21_28to22_28, b22_28to23_28, b23_28to24_28, b24_28to25_28, b25_28to26_28, b26_28to27_28, b27_28to28_28, b28_28to29_28, b29_28to30_28, b30_28to31_28, b31_28to32_28; +wire [18:0] b0_29to1_29, b1_29to2_29, b2_29to3_29, b3_29to4_29, b4_29to5_29, b5_29to6_29, b6_29to7_29, b7_29to8_29, b8_29to9_29, b9_29to10_29, b10_29to11_29, b11_29to12_29, b12_29to13_29, b13_29to14_29, b14_29to15_29, b15_29to16_29, b16_29to17_29, b17_29to18_29, b18_29to19_29, b19_29to20_29, b20_29to21_29, b21_29to22_29, b22_29to23_29, b23_29to24_29, b24_29to25_29, b25_29to26_29, b26_29to27_29, b27_29to28_29, b28_29to29_29, b29_29to30_29, b30_29to31_29, b31_29to32_29; +wire [18:0] b0_30to1_30, b1_30to2_30, b2_30to3_30, b3_30to4_30, b4_30to5_30, b5_30to6_30, b6_30to7_30, b7_30to8_30, b8_30to9_30, b9_30to10_30, b10_30to11_30, b11_30to12_30, b12_30to13_30, b13_30to14_30, b14_30to15_30, b15_30to16_30, b16_30to17_30, b17_30to18_30, b18_30to19_30, b19_30to20_30, b20_30to21_30, b21_30to22_30, b22_30to23_30, b23_30to24_30, b24_30to25_30, b25_30to26_30, b26_30to27_30, b27_30to28_30, b28_30to29_30, b29_30to30_30, b30_30to31_30, b31_30to32_30; +wire [18:0] b0_31to1_31, b1_31to2_31, b2_31to3_31, b3_31to4_31, b4_31to5_31, b5_31to6_31, b6_31to7_31, b7_31to8_31, b8_31to9_31, b9_31to10_31, b10_31to11_31, b11_31to12_31, b12_31to13_31, b13_31to14_31, b14_31to15_31, b15_31to16_31, b16_31to17_31, b17_31to18_31, b18_31to19_31, b19_31to20_31, b20_31to21_31, b21_31to22_31, b22_31to23_31, b23_31to24_31, b24_31to25_31, b25_31to26_31, b26_31to27_31, b27_31to28_31, b28_31to29_31, b29_31to30_31, b30_31to31_31, b31_31to32_31; + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +//For larger matmul, more PEs will be needed +wire effective_rst; +assign effective_rst = reset | pe_reset; + +processing_element_top_edge pe0_0(.reset(effective_rst), .clk(clk), .in_a(a0), .in_b(b0), .out_a(a0_0to0_1), .out_b(b0_0to1_0), .out_c(matrixC0_0)); +processing_element_top_edge pe0_1(.reset(effective_rst), .clk(clk), .in_a(a0_0to0_1), .in_b(b1), .out_a(a0_1to0_2), .out_b(b0_1to1_1), .out_c(matrixC0_1)); +processing_element_top_edge pe0_2(.reset(effective_rst), .clk(clk), .in_a(a0_1to0_2), .in_b(b2), .out_a(a0_2to0_3), .out_b(b0_2to1_2), .out_c(matrixC0_2)); +processing_element_top_edge pe0_3(.reset(effective_rst), .clk(clk), .in_a(a0_2to0_3), .in_b(b3), .out_a(a0_3to0_4), .out_b(b0_3to1_3), .out_c(matrixC0_3)); +processing_element_top_edge pe0_4(.reset(effective_rst), .clk(clk), .in_a(a0_3to0_4), .in_b(b4), .out_a(a0_4to0_5), .out_b(b0_4to1_4), .out_c(matrixC0_4)); +processing_element_top_edge pe0_5(.reset(effective_rst), .clk(clk), .in_a(a0_4to0_5), .in_b(b5), .out_a(a0_5to0_6), .out_b(b0_5to1_5), .out_c(matrixC0_5)); +processing_element_top_edge pe0_6(.reset(effective_rst), .clk(clk), .in_a(a0_5to0_6), .in_b(b6), .out_a(a0_6to0_7), .out_b(b0_6to1_6), .out_c(matrixC0_6)); +processing_element_top_edge pe0_7(.reset(effective_rst), .clk(clk), .in_a(a0_6to0_7), .in_b(b7), .out_a(a0_7to0_8), .out_b(b0_7to1_7), .out_c(matrixC0_7)); +processing_element_top_edge pe0_8(.reset(effective_rst), .clk(clk), .in_a(a0_7to0_8), .in_b(b8), .out_a(a0_8to0_9), .out_b(b0_8to1_8), .out_c(matrixC0_8)); +processing_element_top_edge pe0_9(.reset(effective_rst), .clk(clk), .in_a(a0_8to0_9), .in_b(b9), .out_a(a0_9to0_10), .out_b(b0_9to1_9), .out_c(matrixC0_9)); +processing_element_top_edge pe0_10(.reset(effective_rst), .clk(clk), .in_a(a0_9to0_10), .in_b(b10), .out_a(a0_10to0_11), .out_b(b0_10to1_10), .out_c(matrixC0_10)); +processing_element_top_edge pe0_11(.reset(effective_rst), .clk(clk), .in_a(a0_10to0_11), .in_b(b11), .out_a(a0_11to0_12), .out_b(b0_11to1_11), .out_c(matrixC0_11)); +processing_element_top_edge pe0_12(.reset(effective_rst), .clk(clk), .in_a(a0_11to0_12), .in_b(b12), .out_a(a0_12to0_13), .out_b(b0_12to1_12), .out_c(matrixC0_12)); +processing_element_top_edge pe0_13(.reset(effective_rst), .clk(clk), .in_a(a0_12to0_13), .in_b(b13), .out_a(a0_13to0_14), .out_b(b0_13to1_13), .out_c(matrixC0_13)); +processing_element_top_edge pe0_14(.reset(effective_rst), .clk(clk), .in_a(a0_13to0_14), .in_b(b14), .out_a(a0_14to0_15), .out_b(b0_14to1_14), .out_c(matrixC0_14)); +processing_element_top_edge pe0_15(.reset(effective_rst), .clk(clk), .in_a(a0_14to0_15), .in_b(b15), .out_a(a0_15to0_16), .out_b(b0_15to1_15), .out_c(matrixC0_15)); +processing_element_top_edge pe0_16(.reset(effective_rst), .clk(clk), .in_a(a0_15to0_16), .in_b(b16), .out_a(a0_16to0_17), .out_b(b0_16to1_16), .out_c(matrixC0_16)); +processing_element_top_edge pe0_17(.reset(effective_rst), .clk(clk), .in_a(a0_16to0_17), .in_b(b17), .out_a(a0_17to0_18), .out_b(b0_17to1_17), .out_c(matrixC0_17)); +processing_element_top_edge pe0_18(.reset(effective_rst), .clk(clk), .in_a(a0_17to0_18), .in_b(b18), .out_a(a0_18to0_19), .out_b(b0_18to1_18), .out_c(matrixC0_18)); +processing_element_top_edge pe0_19(.reset(effective_rst), .clk(clk), .in_a(a0_18to0_19), .in_b(b19), .out_a(a0_19to0_20), .out_b(b0_19to1_19), .out_c(matrixC0_19)); +processing_element_top_edge pe0_20(.reset(effective_rst), .clk(clk), .in_a(a0_19to0_20), .in_b(b20), .out_a(a0_20to0_21), .out_b(b0_20to1_20), .out_c(matrixC0_20)); +processing_element_top_edge pe0_21(.reset(effective_rst), .clk(clk), .in_a(a0_20to0_21), .in_b(b21), .out_a(a0_21to0_22), .out_b(b0_21to1_21), .out_c(matrixC0_21)); +processing_element_top_edge pe0_22(.reset(effective_rst), .clk(clk), .in_a(a0_21to0_22), .in_b(b22), .out_a(a0_22to0_23), .out_b(b0_22to1_22), .out_c(matrixC0_22)); +processing_element_top_edge pe0_23(.reset(effective_rst), .clk(clk), .in_a(a0_22to0_23), .in_b(b23), .out_a(a0_23to0_24), .out_b(b0_23to1_23), .out_c(matrixC0_23)); +processing_element_top_edge pe0_24(.reset(effective_rst), .clk(clk), .in_a(a0_23to0_24), .in_b(b24), .out_a(a0_24to0_25), .out_b(b0_24to1_24), .out_c(matrixC0_24)); +processing_element_top_edge pe0_25(.reset(effective_rst), .clk(clk), .in_a(a0_24to0_25), .in_b(b25), .out_a(a0_25to0_26), .out_b(b0_25to1_25), .out_c(matrixC0_25)); +processing_element_top_edge pe0_26(.reset(effective_rst), .clk(clk), .in_a(a0_25to0_26), .in_b(b26), .out_a(a0_26to0_27), .out_b(b0_26to1_26), .out_c(matrixC0_26)); +processing_element_top_edge pe0_27(.reset(effective_rst), .clk(clk), .in_a(a0_26to0_27), .in_b(b27), .out_a(a0_27to0_28), .out_b(b0_27to1_27), .out_c(matrixC0_27)); +processing_element_top_edge pe0_28(.reset(effective_rst), .clk(clk), .in_a(a0_27to0_28), .in_b(b28), .out_a(a0_28to0_29), .out_b(b0_28to1_28), .out_c(matrixC0_28)); +processing_element_top_edge pe0_29(.reset(effective_rst), .clk(clk), .in_a(a0_28to0_29), .in_b(b29), .out_a(a0_29to0_30), .out_b(b0_29to1_29), .out_c(matrixC0_29)); +processing_element_top_edge pe0_30(.reset(effective_rst), .clk(clk), .in_a(a0_29to0_30), .in_b(b30), .out_a(a0_30to0_31), .out_b(b0_30to1_30), .out_c(matrixC0_30)); +processing_element_top_edge pe0_31(.reset(effective_rst), .clk(clk), .in_a(a0_30to0_31), .in_b(b31), .out_a(a0_31to0_32), .out_b(b0_31to1_31), .out_c(matrixC0_31)); + +processing_element pe1_0(.reset(effective_rst), .clk(clk), .in_a(a1), .in_b(b0_0to1_0), .out_a(a1_0to1_1), .out_b(b1_0to2_0), .out_c(matrixC1_0)); +processing_element pe2_0(.reset(effective_rst), .clk(clk), .in_a(a2), .in_b(b1_0to2_0), .out_a(a2_0to2_1), .out_b(b2_0to3_0), .out_c(matrixC2_0)); +processing_element pe3_0(.reset(effective_rst), .clk(clk), .in_a(a3), .in_b(b2_0to3_0), .out_a(a3_0to3_1), .out_b(b3_0to4_0), .out_c(matrixC3_0)); +processing_element pe4_0(.reset(effective_rst), .clk(clk), .in_a(a4), .in_b(b3_0to4_0), .out_a(a4_0to4_1), .out_b(b4_0to5_0), .out_c(matrixC4_0)); +processing_element pe5_0(.reset(effective_rst), .clk(clk), .in_a(a5), .in_b(b4_0to5_0), .out_a(a5_0to5_1), .out_b(b5_0to6_0), .out_c(matrixC5_0)); +processing_element pe6_0(.reset(effective_rst), .clk(clk), .in_a(a6), .in_b(b5_0to6_0), .out_a(a6_0to6_1), .out_b(b6_0to7_0), .out_c(matrixC6_0)); +processing_element pe7_0(.reset(effective_rst), .clk(clk), .in_a(a7), .in_b(b6_0to7_0), .out_a(a7_0to7_1), .out_b(b7_0to8_0), .out_c(matrixC7_0)); +processing_element pe8_0(.reset(effective_rst), .clk(clk), .in_a(a8), .in_b(b7_0to8_0), .out_a(a8_0to8_1), .out_b(b8_0to9_0), .out_c(matrixC8_0)); +processing_element pe9_0(.reset(effective_rst), .clk(clk), .in_a(a9), .in_b(b8_0to9_0), .out_a(a9_0to9_1), .out_b(b9_0to10_0), .out_c(matrixC9_0)); +processing_element pe10_0(.reset(effective_rst), .clk(clk), .in_a(a10), .in_b(b9_0to10_0), .out_a(a10_0to10_1), .out_b(b10_0to11_0), .out_c(matrixC10_0)); +processing_element pe11_0(.reset(effective_rst), .clk(clk), .in_a(a11), .in_b(b10_0to11_0), .out_a(a11_0to11_1), .out_b(b11_0to12_0), .out_c(matrixC11_0)); +processing_element pe12_0(.reset(effective_rst), .clk(clk), .in_a(a12), .in_b(b11_0to12_0), .out_a(a12_0to12_1), .out_b(b12_0to13_0), .out_c(matrixC12_0)); +processing_element pe13_0(.reset(effective_rst), .clk(clk), .in_a(a13), .in_b(b12_0to13_0), .out_a(a13_0to13_1), .out_b(b13_0to14_0), .out_c(matrixC13_0)); +processing_element pe14_0(.reset(effective_rst), .clk(clk), .in_a(a14), .in_b(b13_0to14_0), .out_a(a14_0to14_1), .out_b(b14_0to15_0), .out_c(matrixC14_0)); +processing_element pe15_0(.reset(effective_rst), .clk(clk), .in_a(a15), .in_b(b14_0to15_0), .out_a(a15_0to15_1), .out_b(b15_0to16_0), .out_c(matrixC15_0)); +processing_element pe16_0(.reset(effective_rst), .clk(clk), .in_a(a16), .in_b(b15_0to16_0), .out_a(a16_0to16_1), .out_b(b16_0to17_0), .out_c(matrixC16_0)); +processing_element pe17_0(.reset(effective_rst), .clk(clk), .in_a(a17), .in_b(b16_0to17_0), .out_a(a17_0to17_1), .out_b(b17_0to18_0), .out_c(matrixC17_0)); +processing_element pe18_0(.reset(effective_rst), .clk(clk), .in_a(a18), .in_b(b17_0to18_0), .out_a(a18_0to18_1), .out_b(b18_0to19_0), .out_c(matrixC18_0)); +processing_element pe19_0(.reset(effective_rst), .clk(clk), .in_a(a19), .in_b(b18_0to19_0), .out_a(a19_0to19_1), .out_b(b19_0to20_0), .out_c(matrixC19_0)); +processing_element pe20_0(.reset(effective_rst), .clk(clk), .in_a(a20), .in_b(b19_0to20_0), .out_a(a20_0to20_1), .out_b(b20_0to21_0), .out_c(matrixC20_0)); +processing_element pe21_0(.reset(effective_rst), .clk(clk), .in_a(a21), .in_b(b20_0to21_0), .out_a(a21_0to21_1), .out_b(b21_0to22_0), .out_c(matrixC21_0)); +processing_element pe22_0(.reset(effective_rst), .clk(clk), .in_a(a22), .in_b(b21_0to22_0), .out_a(a22_0to22_1), .out_b(b22_0to23_0), .out_c(matrixC22_0)); +processing_element pe23_0(.reset(effective_rst), .clk(clk), .in_a(a23), .in_b(b22_0to23_0), .out_a(a23_0to23_1), .out_b(b23_0to24_0), .out_c(matrixC23_0)); +processing_element pe24_0(.reset(effective_rst), .clk(clk), .in_a(a24), .in_b(b23_0to24_0), .out_a(a24_0to24_1), .out_b(b24_0to25_0), .out_c(matrixC24_0)); +processing_element pe25_0(.reset(effective_rst), .clk(clk), .in_a(a25), .in_b(b24_0to25_0), .out_a(a25_0to25_1), .out_b(b25_0to26_0), .out_c(matrixC25_0)); +processing_element pe26_0(.reset(effective_rst), .clk(clk), .in_a(a26), .in_b(b25_0to26_0), .out_a(a26_0to26_1), .out_b(b26_0to27_0), .out_c(matrixC26_0)); +processing_element pe27_0(.reset(effective_rst), .clk(clk), .in_a(a27), .in_b(b26_0to27_0), .out_a(a27_0to27_1), .out_b(b27_0to28_0), .out_c(matrixC27_0)); +processing_element pe28_0(.reset(effective_rst), .clk(clk), .in_a(a28), .in_b(b27_0to28_0), .out_a(a28_0to28_1), .out_b(b28_0to29_0), .out_c(matrixC28_0)); +processing_element pe29_0(.reset(effective_rst), .clk(clk), .in_a(a29), .in_b(b28_0to29_0), .out_a(a29_0to29_1), .out_b(b29_0to30_0), .out_c(matrixC29_0)); +processing_element pe30_0(.reset(effective_rst), .clk(clk), .in_a(a30), .in_b(b29_0to30_0), .out_a(a30_0to30_1), .out_b(b30_0to31_0), .out_c(matrixC30_0)); +processing_element_bottom_edge pe31_0(.reset(effective_rst), .clk(clk), .in_a(a31), .in_b(b30_0to31_0), .out_a(a31_0to31_1), .out_b(b31_0to32_0), .out_c(matrixC31_0)); + +processing_element pe1_1(.reset(effective_rst), .clk(clk), .in_a(a1_0to1_1), .in_b(b0_1to1_1), .out_a(a1_1to1_2), .out_b(b1_1to2_1), .out_c(matrixC1_1)); +processing_element pe1_2(.reset(effective_rst), .clk(clk), .in_a(a1_1to1_2), .in_b(b0_2to1_2), .out_a(a1_2to1_3), .out_b(b1_2to2_2), .out_c(matrixC1_2)); +processing_element pe1_3(.reset(effective_rst), .clk(clk), .in_a(a1_2to1_3), .in_b(b0_3to1_3), .out_a(a1_3to1_4), .out_b(b1_3to2_3), .out_c(matrixC1_3)); +processing_element pe1_4(.reset(effective_rst), .clk(clk), .in_a(a1_3to1_4), .in_b(b0_4to1_4), .out_a(a1_4to1_5), .out_b(b1_4to2_4), .out_c(matrixC1_4)); +processing_element pe1_5(.reset(effective_rst), .clk(clk), .in_a(a1_4to1_5), .in_b(b0_5to1_5), .out_a(a1_5to1_6), .out_b(b1_5to2_5), .out_c(matrixC1_5)); +processing_element pe1_6(.reset(effective_rst), .clk(clk), .in_a(a1_5to1_6), .in_b(b0_6to1_6), .out_a(a1_6to1_7), .out_b(b1_6to2_6), .out_c(matrixC1_6)); +processing_element pe1_7(.reset(effective_rst), .clk(clk), .in_a(a1_6to1_7), .in_b(b0_7to1_7), .out_a(a1_7to1_8), .out_b(b1_7to2_7), .out_c(matrixC1_7)); +processing_element pe1_8(.reset(effective_rst), .clk(clk), .in_a(a1_7to1_8), .in_b(b0_8to1_8), .out_a(a1_8to1_9), .out_b(b1_8to2_8), .out_c(matrixC1_8)); +processing_element pe1_9(.reset(effective_rst), .clk(clk), .in_a(a1_8to1_9), .in_b(b0_9to1_9), .out_a(a1_9to1_10), .out_b(b1_9to2_9), .out_c(matrixC1_9)); +processing_element pe1_10(.reset(effective_rst), .clk(clk), .in_a(a1_9to1_10), .in_b(b0_10to1_10), .out_a(a1_10to1_11), .out_b(b1_10to2_10), .out_c(matrixC1_10)); +processing_element pe1_11(.reset(effective_rst), .clk(clk), .in_a(a1_10to1_11), .in_b(b0_11to1_11), .out_a(a1_11to1_12), .out_b(b1_11to2_11), .out_c(matrixC1_11)); +processing_element pe1_12(.reset(effective_rst), .clk(clk), .in_a(a1_11to1_12), .in_b(b0_12to1_12), .out_a(a1_12to1_13), .out_b(b1_12to2_12), .out_c(matrixC1_12)); +processing_element pe1_13(.reset(effective_rst), .clk(clk), .in_a(a1_12to1_13), .in_b(b0_13to1_13), .out_a(a1_13to1_14), .out_b(b1_13to2_13), .out_c(matrixC1_13)); +processing_element pe1_14(.reset(effective_rst), .clk(clk), .in_a(a1_13to1_14), .in_b(b0_14to1_14), .out_a(a1_14to1_15), .out_b(b1_14to2_14), .out_c(matrixC1_14)); +processing_element pe1_15(.reset(effective_rst), .clk(clk), .in_a(a1_14to1_15), .in_b(b0_15to1_15), .out_a(a1_15to1_16), .out_b(b1_15to2_15), .out_c(matrixC1_15)); +processing_element pe1_16(.reset(effective_rst), .clk(clk), .in_a(a1_15to1_16), .in_b(b0_16to1_16), .out_a(a1_16to1_17), .out_b(b1_16to2_16), .out_c(matrixC1_16)); +processing_element pe1_17(.reset(effective_rst), .clk(clk), .in_a(a1_16to1_17), .in_b(b0_17to1_17), .out_a(a1_17to1_18), .out_b(b1_17to2_17), .out_c(matrixC1_17)); +processing_element pe1_18(.reset(effective_rst), .clk(clk), .in_a(a1_17to1_18), .in_b(b0_18to1_18), .out_a(a1_18to1_19), .out_b(b1_18to2_18), .out_c(matrixC1_18)); +processing_element pe1_19(.reset(effective_rst), .clk(clk), .in_a(a1_18to1_19), .in_b(b0_19to1_19), .out_a(a1_19to1_20), .out_b(b1_19to2_19), .out_c(matrixC1_19)); +processing_element pe1_20(.reset(effective_rst), .clk(clk), .in_a(a1_19to1_20), .in_b(b0_20to1_20), .out_a(a1_20to1_21), .out_b(b1_20to2_20), .out_c(matrixC1_20)); +processing_element pe1_21(.reset(effective_rst), .clk(clk), .in_a(a1_20to1_21), .in_b(b0_21to1_21), .out_a(a1_21to1_22), .out_b(b1_21to2_21), .out_c(matrixC1_21)); +processing_element pe1_22(.reset(effective_rst), .clk(clk), .in_a(a1_21to1_22), .in_b(b0_22to1_22), .out_a(a1_22to1_23), .out_b(b1_22to2_22), .out_c(matrixC1_22)); +processing_element pe1_23(.reset(effective_rst), .clk(clk), .in_a(a1_22to1_23), .in_b(b0_23to1_23), .out_a(a1_23to1_24), .out_b(b1_23to2_23), .out_c(matrixC1_23)); +processing_element pe1_24(.reset(effective_rst), .clk(clk), .in_a(a1_23to1_24), .in_b(b0_24to1_24), .out_a(a1_24to1_25), .out_b(b1_24to2_24), .out_c(matrixC1_24)); +processing_element pe1_25(.reset(effective_rst), .clk(clk), .in_a(a1_24to1_25), .in_b(b0_25to1_25), .out_a(a1_25to1_26), .out_b(b1_25to2_25), .out_c(matrixC1_25)); +processing_element pe1_26(.reset(effective_rst), .clk(clk), .in_a(a1_25to1_26), .in_b(b0_26to1_26), .out_a(a1_26to1_27), .out_b(b1_26to2_26), .out_c(matrixC1_26)); +processing_element pe1_27(.reset(effective_rst), .clk(clk), .in_a(a1_26to1_27), .in_b(b0_27to1_27), .out_a(a1_27to1_28), .out_b(b1_27to2_27), .out_c(matrixC1_27)); +processing_element pe1_28(.reset(effective_rst), .clk(clk), .in_a(a1_27to1_28), .in_b(b0_28to1_28), .out_a(a1_28to1_29), .out_b(b1_28to2_28), .out_c(matrixC1_28)); +processing_element pe1_29(.reset(effective_rst), .clk(clk), .in_a(a1_28to1_29), .in_b(b0_29to1_29), .out_a(a1_29to1_30), .out_b(b1_29to2_29), .out_c(matrixC1_29)); +processing_element pe1_30(.reset(effective_rst), .clk(clk), .in_a(a1_29to1_30), .in_b(b0_30to1_30), .out_a(a1_30to1_31), .out_b(b1_30to2_30), .out_c(matrixC1_30)); +processing_element pe1_31(.reset(effective_rst), .clk(clk), .in_a(a1_30to1_31), .in_b(b0_31to1_31), .out_a(a1_31to1_32), .out_b(b1_31to2_31), .out_c(matrixC1_31)); +processing_element pe2_1(.reset(effective_rst), .clk(clk), .in_a(a2_0to2_1), .in_b(b1_1to2_1), .out_a(a2_1to2_2), .out_b(b2_1to3_1), .out_c(matrixC2_1)); +processing_element pe2_2(.reset(effective_rst), .clk(clk), .in_a(a2_1to2_2), .in_b(b1_2to2_2), .out_a(a2_2to2_3), .out_b(b2_2to3_2), .out_c(matrixC2_2)); +processing_element pe2_3(.reset(effective_rst), .clk(clk), .in_a(a2_2to2_3), .in_b(b1_3to2_3), .out_a(a2_3to2_4), .out_b(b2_3to3_3), .out_c(matrixC2_3)); +processing_element pe2_4(.reset(effective_rst), .clk(clk), .in_a(a2_3to2_4), .in_b(b1_4to2_4), .out_a(a2_4to2_5), .out_b(b2_4to3_4), .out_c(matrixC2_4)); +processing_element pe2_5(.reset(effective_rst), .clk(clk), .in_a(a2_4to2_5), .in_b(b1_5to2_5), .out_a(a2_5to2_6), .out_b(b2_5to3_5), .out_c(matrixC2_5)); +processing_element pe2_6(.reset(effective_rst), .clk(clk), .in_a(a2_5to2_6), .in_b(b1_6to2_6), .out_a(a2_6to2_7), .out_b(b2_6to3_6), .out_c(matrixC2_6)); +processing_element pe2_7(.reset(effective_rst), .clk(clk), .in_a(a2_6to2_7), .in_b(b1_7to2_7), .out_a(a2_7to2_8), .out_b(b2_7to3_7), .out_c(matrixC2_7)); +processing_element pe2_8(.reset(effective_rst), .clk(clk), .in_a(a2_7to2_8), .in_b(b1_8to2_8), .out_a(a2_8to2_9), .out_b(b2_8to3_8), .out_c(matrixC2_8)); +processing_element pe2_9(.reset(effective_rst), .clk(clk), .in_a(a2_8to2_9), .in_b(b1_9to2_9), .out_a(a2_9to2_10), .out_b(b2_9to3_9), .out_c(matrixC2_9)); +processing_element pe2_10(.reset(effective_rst), .clk(clk), .in_a(a2_9to2_10), .in_b(b1_10to2_10), .out_a(a2_10to2_11), .out_b(b2_10to3_10), .out_c(matrixC2_10)); +processing_element pe2_11(.reset(effective_rst), .clk(clk), .in_a(a2_10to2_11), .in_b(b1_11to2_11), .out_a(a2_11to2_12), .out_b(b2_11to3_11), .out_c(matrixC2_11)); +processing_element pe2_12(.reset(effective_rst), .clk(clk), .in_a(a2_11to2_12), .in_b(b1_12to2_12), .out_a(a2_12to2_13), .out_b(b2_12to3_12), .out_c(matrixC2_12)); +processing_element pe2_13(.reset(effective_rst), .clk(clk), .in_a(a2_12to2_13), .in_b(b1_13to2_13), .out_a(a2_13to2_14), .out_b(b2_13to3_13), .out_c(matrixC2_13)); +processing_element pe2_14(.reset(effective_rst), .clk(clk), .in_a(a2_13to2_14), .in_b(b1_14to2_14), .out_a(a2_14to2_15), .out_b(b2_14to3_14), .out_c(matrixC2_14)); +processing_element pe2_15(.reset(effective_rst), .clk(clk), .in_a(a2_14to2_15), .in_b(b1_15to2_15), .out_a(a2_15to2_16), .out_b(b2_15to3_15), .out_c(matrixC2_15)); +processing_element pe2_16(.reset(effective_rst), .clk(clk), .in_a(a2_15to2_16), .in_b(b1_16to2_16), .out_a(a2_16to2_17), .out_b(b2_16to3_16), .out_c(matrixC2_16)); +processing_element pe2_17(.reset(effective_rst), .clk(clk), .in_a(a2_16to2_17), .in_b(b1_17to2_17), .out_a(a2_17to2_18), .out_b(b2_17to3_17), .out_c(matrixC2_17)); +processing_element pe2_18(.reset(effective_rst), .clk(clk), .in_a(a2_17to2_18), .in_b(b1_18to2_18), .out_a(a2_18to2_19), .out_b(b2_18to3_18), .out_c(matrixC2_18)); +processing_element pe2_19(.reset(effective_rst), .clk(clk), .in_a(a2_18to2_19), .in_b(b1_19to2_19), .out_a(a2_19to2_20), .out_b(b2_19to3_19), .out_c(matrixC2_19)); +processing_element pe2_20(.reset(effective_rst), .clk(clk), .in_a(a2_19to2_20), .in_b(b1_20to2_20), .out_a(a2_20to2_21), .out_b(b2_20to3_20), .out_c(matrixC2_20)); +processing_element pe2_21(.reset(effective_rst), .clk(clk), .in_a(a2_20to2_21), .in_b(b1_21to2_21), .out_a(a2_21to2_22), .out_b(b2_21to3_21), .out_c(matrixC2_21)); +processing_element pe2_22(.reset(effective_rst), .clk(clk), .in_a(a2_21to2_22), .in_b(b1_22to2_22), .out_a(a2_22to2_23), .out_b(b2_22to3_22), .out_c(matrixC2_22)); +processing_element pe2_23(.reset(effective_rst), .clk(clk), .in_a(a2_22to2_23), .in_b(b1_23to2_23), .out_a(a2_23to2_24), .out_b(b2_23to3_23), .out_c(matrixC2_23)); +processing_element pe2_24(.reset(effective_rst), .clk(clk), .in_a(a2_23to2_24), .in_b(b1_24to2_24), .out_a(a2_24to2_25), .out_b(b2_24to3_24), .out_c(matrixC2_24)); +processing_element pe2_25(.reset(effective_rst), .clk(clk), .in_a(a2_24to2_25), .in_b(b1_25to2_25), .out_a(a2_25to2_26), .out_b(b2_25to3_25), .out_c(matrixC2_25)); +processing_element pe2_26(.reset(effective_rst), .clk(clk), .in_a(a2_25to2_26), .in_b(b1_26to2_26), .out_a(a2_26to2_27), .out_b(b2_26to3_26), .out_c(matrixC2_26)); +processing_element pe2_27(.reset(effective_rst), .clk(clk), .in_a(a2_26to2_27), .in_b(b1_27to2_27), .out_a(a2_27to2_28), .out_b(b2_27to3_27), .out_c(matrixC2_27)); +processing_element pe2_28(.reset(effective_rst), .clk(clk), .in_a(a2_27to2_28), .in_b(b1_28to2_28), .out_a(a2_28to2_29), .out_b(b2_28to3_28), .out_c(matrixC2_28)); +processing_element pe2_29(.reset(effective_rst), .clk(clk), .in_a(a2_28to2_29), .in_b(b1_29to2_29), .out_a(a2_29to2_30), .out_b(b2_29to3_29), .out_c(matrixC2_29)); +processing_element pe2_30(.reset(effective_rst), .clk(clk), .in_a(a2_29to2_30), .in_b(b1_30to2_30), .out_a(a2_30to2_31), .out_b(b2_30to3_30), .out_c(matrixC2_30)); +processing_element pe2_31(.reset(effective_rst), .clk(clk), .in_a(a2_30to2_31), .in_b(b1_31to2_31), .out_a(a2_31to2_32), .out_b(b2_31to3_31), .out_c(matrixC2_31)); +processing_element pe3_1(.reset(effective_rst), .clk(clk), .in_a(a3_0to3_1), .in_b(b2_1to3_1), .out_a(a3_1to3_2), .out_b(b3_1to4_1), .out_c(matrixC3_1)); +processing_element pe3_2(.reset(effective_rst), .clk(clk), .in_a(a3_1to3_2), .in_b(b2_2to3_2), .out_a(a3_2to3_3), .out_b(b3_2to4_2), .out_c(matrixC3_2)); +processing_element pe3_3(.reset(effective_rst), .clk(clk), .in_a(a3_2to3_3), .in_b(b2_3to3_3), .out_a(a3_3to3_4), .out_b(b3_3to4_3), .out_c(matrixC3_3)); +processing_element pe3_4(.reset(effective_rst), .clk(clk), .in_a(a3_3to3_4), .in_b(b2_4to3_4), .out_a(a3_4to3_5), .out_b(b3_4to4_4), .out_c(matrixC3_4)); +processing_element pe3_5(.reset(effective_rst), .clk(clk), .in_a(a3_4to3_5), .in_b(b2_5to3_5), .out_a(a3_5to3_6), .out_b(b3_5to4_5), .out_c(matrixC3_5)); +processing_element pe3_6(.reset(effective_rst), .clk(clk), .in_a(a3_5to3_6), .in_b(b2_6to3_6), .out_a(a3_6to3_7), .out_b(b3_6to4_6), .out_c(matrixC3_6)); +processing_element pe3_7(.reset(effective_rst), .clk(clk), .in_a(a3_6to3_7), .in_b(b2_7to3_7), .out_a(a3_7to3_8), .out_b(b3_7to4_7), .out_c(matrixC3_7)); +processing_element pe3_8(.reset(effective_rst), .clk(clk), .in_a(a3_7to3_8), .in_b(b2_8to3_8), .out_a(a3_8to3_9), .out_b(b3_8to4_8), .out_c(matrixC3_8)); +processing_element pe3_9(.reset(effective_rst), .clk(clk), .in_a(a3_8to3_9), .in_b(b2_9to3_9), .out_a(a3_9to3_10), .out_b(b3_9to4_9), .out_c(matrixC3_9)); +processing_element pe3_10(.reset(effective_rst), .clk(clk), .in_a(a3_9to3_10), .in_b(b2_10to3_10), .out_a(a3_10to3_11), .out_b(b3_10to4_10), .out_c(matrixC3_10)); +processing_element pe3_11(.reset(effective_rst), .clk(clk), .in_a(a3_10to3_11), .in_b(b2_11to3_11), .out_a(a3_11to3_12), .out_b(b3_11to4_11), .out_c(matrixC3_11)); +processing_element pe3_12(.reset(effective_rst), .clk(clk), .in_a(a3_11to3_12), .in_b(b2_12to3_12), .out_a(a3_12to3_13), .out_b(b3_12to4_12), .out_c(matrixC3_12)); +processing_element pe3_13(.reset(effective_rst), .clk(clk), .in_a(a3_12to3_13), .in_b(b2_13to3_13), .out_a(a3_13to3_14), .out_b(b3_13to4_13), .out_c(matrixC3_13)); +processing_element pe3_14(.reset(effective_rst), .clk(clk), .in_a(a3_13to3_14), .in_b(b2_14to3_14), .out_a(a3_14to3_15), .out_b(b3_14to4_14), .out_c(matrixC3_14)); +processing_element pe3_15(.reset(effective_rst), .clk(clk), .in_a(a3_14to3_15), .in_b(b2_15to3_15), .out_a(a3_15to3_16), .out_b(b3_15to4_15), .out_c(matrixC3_15)); +processing_element pe3_16(.reset(effective_rst), .clk(clk), .in_a(a3_15to3_16), .in_b(b2_16to3_16), .out_a(a3_16to3_17), .out_b(b3_16to4_16), .out_c(matrixC3_16)); +processing_element pe3_17(.reset(effective_rst), .clk(clk), .in_a(a3_16to3_17), .in_b(b2_17to3_17), .out_a(a3_17to3_18), .out_b(b3_17to4_17), .out_c(matrixC3_17)); +processing_element pe3_18(.reset(effective_rst), .clk(clk), .in_a(a3_17to3_18), .in_b(b2_18to3_18), .out_a(a3_18to3_19), .out_b(b3_18to4_18), .out_c(matrixC3_18)); +processing_element pe3_19(.reset(effective_rst), .clk(clk), .in_a(a3_18to3_19), .in_b(b2_19to3_19), .out_a(a3_19to3_20), .out_b(b3_19to4_19), .out_c(matrixC3_19)); +processing_element pe3_20(.reset(effective_rst), .clk(clk), .in_a(a3_19to3_20), .in_b(b2_20to3_20), .out_a(a3_20to3_21), .out_b(b3_20to4_20), .out_c(matrixC3_20)); +processing_element pe3_21(.reset(effective_rst), .clk(clk), .in_a(a3_20to3_21), .in_b(b2_21to3_21), .out_a(a3_21to3_22), .out_b(b3_21to4_21), .out_c(matrixC3_21)); +processing_element pe3_22(.reset(effective_rst), .clk(clk), .in_a(a3_21to3_22), .in_b(b2_22to3_22), .out_a(a3_22to3_23), .out_b(b3_22to4_22), .out_c(matrixC3_22)); +processing_element pe3_23(.reset(effective_rst), .clk(clk), .in_a(a3_22to3_23), .in_b(b2_23to3_23), .out_a(a3_23to3_24), .out_b(b3_23to4_23), .out_c(matrixC3_23)); +processing_element pe3_24(.reset(effective_rst), .clk(clk), .in_a(a3_23to3_24), .in_b(b2_24to3_24), .out_a(a3_24to3_25), .out_b(b3_24to4_24), .out_c(matrixC3_24)); +processing_element pe3_25(.reset(effective_rst), .clk(clk), .in_a(a3_24to3_25), .in_b(b2_25to3_25), .out_a(a3_25to3_26), .out_b(b3_25to4_25), .out_c(matrixC3_25)); +processing_element pe3_26(.reset(effective_rst), .clk(clk), .in_a(a3_25to3_26), .in_b(b2_26to3_26), .out_a(a3_26to3_27), .out_b(b3_26to4_26), .out_c(matrixC3_26)); +processing_element pe3_27(.reset(effective_rst), .clk(clk), .in_a(a3_26to3_27), .in_b(b2_27to3_27), .out_a(a3_27to3_28), .out_b(b3_27to4_27), .out_c(matrixC3_27)); +processing_element pe3_28(.reset(effective_rst), .clk(clk), .in_a(a3_27to3_28), .in_b(b2_28to3_28), .out_a(a3_28to3_29), .out_b(b3_28to4_28), .out_c(matrixC3_28)); +processing_element pe3_29(.reset(effective_rst), .clk(clk), .in_a(a3_28to3_29), .in_b(b2_29to3_29), .out_a(a3_29to3_30), .out_b(b3_29to4_29), .out_c(matrixC3_29)); +processing_element pe3_30(.reset(effective_rst), .clk(clk), .in_a(a3_29to3_30), .in_b(b2_30to3_30), .out_a(a3_30to3_31), .out_b(b3_30to4_30), .out_c(matrixC3_30)); +processing_element pe3_31(.reset(effective_rst), .clk(clk), .in_a(a3_30to3_31), .in_b(b2_31to3_31), .out_a(a3_31to3_32), .out_b(b3_31to4_31), .out_c(matrixC3_31)); +processing_element pe4_1(.reset(effective_rst), .clk(clk), .in_a(a4_0to4_1), .in_b(b3_1to4_1), .out_a(a4_1to4_2), .out_b(b4_1to5_1), .out_c(matrixC4_1)); +processing_element pe4_2(.reset(effective_rst), .clk(clk), .in_a(a4_1to4_2), .in_b(b3_2to4_2), .out_a(a4_2to4_3), .out_b(b4_2to5_2), .out_c(matrixC4_2)); +processing_element pe4_3(.reset(effective_rst), .clk(clk), .in_a(a4_2to4_3), .in_b(b3_3to4_3), .out_a(a4_3to4_4), .out_b(b4_3to5_3), .out_c(matrixC4_3)); +processing_element pe4_4(.reset(effective_rst), .clk(clk), .in_a(a4_3to4_4), .in_b(b3_4to4_4), .out_a(a4_4to4_5), .out_b(b4_4to5_4), .out_c(matrixC4_4)); +processing_element pe4_5(.reset(effective_rst), .clk(clk), .in_a(a4_4to4_5), .in_b(b3_5to4_5), .out_a(a4_5to4_6), .out_b(b4_5to5_5), .out_c(matrixC4_5)); +processing_element pe4_6(.reset(effective_rst), .clk(clk), .in_a(a4_5to4_6), .in_b(b3_6to4_6), .out_a(a4_6to4_7), .out_b(b4_6to5_6), .out_c(matrixC4_6)); +processing_element pe4_7(.reset(effective_rst), .clk(clk), .in_a(a4_6to4_7), .in_b(b3_7to4_7), .out_a(a4_7to4_8), .out_b(b4_7to5_7), .out_c(matrixC4_7)); +processing_element pe4_8(.reset(effective_rst), .clk(clk), .in_a(a4_7to4_8), .in_b(b3_8to4_8), .out_a(a4_8to4_9), .out_b(b4_8to5_8), .out_c(matrixC4_8)); +processing_element pe4_9(.reset(effective_rst), .clk(clk), .in_a(a4_8to4_9), .in_b(b3_9to4_9), .out_a(a4_9to4_10), .out_b(b4_9to5_9), .out_c(matrixC4_9)); +processing_element pe4_10(.reset(effective_rst), .clk(clk), .in_a(a4_9to4_10), .in_b(b3_10to4_10), .out_a(a4_10to4_11), .out_b(b4_10to5_10), .out_c(matrixC4_10)); +processing_element pe4_11(.reset(effective_rst), .clk(clk), .in_a(a4_10to4_11), .in_b(b3_11to4_11), .out_a(a4_11to4_12), .out_b(b4_11to5_11), .out_c(matrixC4_11)); +processing_element pe4_12(.reset(effective_rst), .clk(clk), .in_a(a4_11to4_12), .in_b(b3_12to4_12), .out_a(a4_12to4_13), .out_b(b4_12to5_12), .out_c(matrixC4_12)); +processing_element pe4_13(.reset(effective_rst), .clk(clk), .in_a(a4_12to4_13), .in_b(b3_13to4_13), .out_a(a4_13to4_14), .out_b(b4_13to5_13), .out_c(matrixC4_13)); +processing_element pe4_14(.reset(effective_rst), .clk(clk), .in_a(a4_13to4_14), .in_b(b3_14to4_14), .out_a(a4_14to4_15), .out_b(b4_14to5_14), .out_c(matrixC4_14)); +processing_element pe4_15(.reset(effective_rst), .clk(clk), .in_a(a4_14to4_15), .in_b(b3_15to4_15), .out_a(a4_15to4_16), .out_b(b4_15to5_15), .out_c(matrixC4_15)); +processing_element pe4_16(.reset(effective_rst), .clk(clk), .in_a(a4_15to4_16), .in_b(b3_16to4_16), .out_a(a4_16to4_17), .out_b(b4_16to5_16), .out_c(matrixC4_16)); +processing_element pe4_17(.reset(effective_rst), .clk(clk), .in_a(a4_16to4_17), .in_b(b3_17to4_17), .out_a(a4_17to4_18), .out_b(b4_17to5_17), .out_c(matrixC4_17)); +processing_element pe4_18(.reset(effective_rst), .clk(clk), .in_a(a4_17to4_18), .in_b(b3_18to4_18), .out_a(a4_18to4_19), .out_b(b4_18to5_18), .out_c(matrixC4_18)); +processing_element pe4_19(.reset(effective_rst), .clk(clk), .in_a(a4_18to4_19), .in_b(b3_19to4_19), .out_a(a4_19to4_20), .out_b(b4_19to5_19), .out_c(matrixC4_19)); +processing_element pe4_20(.reset(effective_rst), .clk(clk), .in_a(a4_19to4_20), .in_b(b3_20to4_20), .out_a(a4_20to4_21), .out_b(b4_20to5_20), .out_c(matrixC4_20)); +processing_element pe4_21(.reset(effective_rst), .clk(clk), .in_a(a4_20to4_21), .in_b(b3_21to4_21), .out_a(a4_21to4_22), .out_b(b4_21to5_21), .out_c(matrixC4_21)); +processing_element pe4_22(.reset(effective_rst), .clk(clk), .in_a(a4_21to4_22), .in_b(b3_22to4_22), .out_a(a4_22to4_23), .out_b(b4_22to5_22), .out_c(matrixC4_22)); +processing_element pe4_23(.reset(effective_rst), .clk(clk), .in_a(a4_22to4_23), .in_b(b3_23to4_23), .out_a(a4_23to4_24), .out_b(b4_23to5_23), .out_c(matrixC4_23)); +processing_element pe4_24(.reset(effective_rst), .clk(clk), .in_a(a4_23to4_24), .in_b(b3_24to4_24), .out_a(a4_24to4_25), .out_b(b4_24to5_24), .out_c(matrixC4_24)); +processing_element pe4_25(.reset(effective_rst), .clk(clk), .in_a(a4_24to4_25), .in_b(b3_25to4_25), .out_a(a4_25to4_26), .out_b(b4_25to5_25), .out_c(matrixC4_25)); +processing_element pe4_26(.reset(effective_rst), .clk(clk), .in_a(a4_25to4_26), .in_b(b3_26to4_26), .out_a(a4_26to4_27), .out_b(b4_26to5_26), .out_c(matrixC4_26)); +processing_element pe4_27(.reset(effective_rst), .clk(clk), .in_a(a4_26to4_27), .in_b(b3_27to4_27), .out_a(a4_27to4_28), .out_b(b4_27to5_27), .out_c(matrixC4_27)); +processing_element pe4_28(.reset(effective_rst), .clk(clk), .in_a(a4_27to4_28), .in_b(b3_28to4_28), .out_a(a4_28to4_29), .out_b(b4_28to5_28), .out_c(matrixC4_28)); +processing_element pe4_29(.reset(effective_rst), .clk(clk), .in_a(a4_28to4_29), .in_b(b3_29to4_29), .out_a(a4_29to4_30), .out_b(b4_29to5_29), .out_c(matrixC4_29)); +processing_element pe4_30(.reset(effective_rst), .clk(clk), .in_a(a4_29to4_30), .in_b(b3_30to4_30), .out_a(a4_30to4_31), .out_b(b4_30to5_30), .out_c(matrixC4_30)); +processing_element pe4_31(.reset(effective_rst), .clk(clk), .in_a(a4_30to4_31), .in_b(b3_31to4_31), .out_a(a4_31to4_32), .out_b(b4_31to5_31), .out_c(matrixC4_31)); +processing_element pe5_1(.reset(effective_rst), .clk(clk), .in_a(a5_0to5_1), .in_b(b4_1to5_1), .out_a(a5_1to5_2), .out_b(b5_1to6_1), .out_c(matrixC5_1)); +processing_element pe5_2(.reset(effective_rst), .clk(clk), .in_a(a5_1to5_2), .in_b(b4_2to5_2), .out_a(a5_2to5_3), .out_b(b5_2to6_2), .out_c(matrixC5_2)); +processing_element pe5_3(.reset(effective_rst), .clk(clk), .in_a(a5_2to5_3), .in_b(b4_3to5_3), .out_a(a5_3to5_4), .out_b(b5_3to6_3), .out_c(matrixC5_3)); +processing_element pe5_4(.reset(effective_rst), .clk(clk), .in_a(a5_3to5_4), .in_b(b4_4to5_4), .out_a(a5_4to5_5), .out_b(b5_4to6_4), .out_c(matrixC5_4)); +processing_element pe5_5(.reset(effective_rst), .clk(clk), .in_a(a5_4to5_5), .in_b(b4_5to5_5), .out_a(a5_5to5_6), .out_b(b5_5to6_5), .out_c(matrixC5_5)); +processing_element pe5_6(.reset(effective_rst), .clk(clk), .in_a(a5_5to5_6), .in_b(b4_6to5_6), .out_a(a5_6to5_7), .out_b(b5_6to6_6), .out_c(matrixC5_6)); +processing_element pe5_7(.reset(effective_rst), .clk(clk), .in_a(a5_6to5_7), .in_b(b4_7to5_7), .out_a(a5_7to5_8), .out_b(b5_7to6_7), .out_c(matrixC5_7)); +processing_element pe5_8(.reset(effective_rst), .clk(clk), .in_a(a5_7to5_8), .in_b(b4_8to5_8), .out_a(a5_8to5_9), .out_b(b5_8to6_8), .out_c(matrixC5_8)); +processing_element pe5_9(.reset(effective_rst), .clk(clk), .in_a(a5_8to5_9), .in_b(b4_9to5_9), .out_a(a5_9to5_10), .out_b(b5_9to6_9), .out_c(matrixC5_9)); +processing_element pe5_10(.reset(effective_rst), .clk(clk), .in_a(a5_9to5_10), .in_b(b4_10to5_10), .out_a(a5_10to5_11), .out_b(b5_10to6_10), .out_c(matrixC5_10)); +processing_element pe5_11(.reset(effective_rst), .clk(clk), .in_a(a5_10to5_11), .in_b(b4_11to5_11), .out_a(a5_11to5_12), .out_b(b5_11to6_11), .out_c(matrixC5_11)); +processing_element pe5_12(.reset(effective_rst), .clk(clk), .in_a(a5_11to5_12), .in_b(b4_12to5_12), .out_a(a5_12to5_13), .out_b(b5_12to6_12), .out_c(matrixC5_12)); +processing_element pe5_13(.reset(effective_rst), .clk(clk), .in_a(a5_12to5_13), .in_b(b4_13to5_13), .out_a(a5_13to5_14), .out_b(b5_13to6_13), .out_c(matrixC5_13)); +processing_element pe5_14(.reset(effective_rst), .clk(clk), .in_a(a5_13to5_14), .in_b(b4_14to5_14), .out_a(a5_14to5_15), .out_b(b5_14to6_14), .out_c(matrixC5_14)); +processing_element pe5_15(.reset(effective_rst), .clk(clk), .in_a(a5_14to5_15), .in_b(b4_15to5_15), .out_a(a5_15to5_16), .out_b(b5_15to6_15), .out_c(matrixC5_15)); +processing_element pe5_16(.reset(effective_rst), .clk(clk), .in_a(a5_15to5_16), .in_b(b4_16to5_16), .out_a(a5_16to5_17), .out_b(b5_16to6_16), .out_c(matrixC5_16)); +processing_element pe5_17(.reset(effective_rst), .clk(clk), .in_a(a5_16to5_17), .in_b(b4_17to5_17), .out_a(a5_17to5_18), .out_b(b5_17to6_17), .out_c(matrixC5_17)); +processing_element pe5_18(.reset(effective_rst), .clk(clk), .in_a(a5_17to5_18), .in_b(b4_18to5_18), .out_a(a5_18to5_19), .out_b(b5_18to6_18), .out_c(matrixC5_18)); +processing_element pe5_19(.reset(effective_rst), .clk(clk), .in_a(a5_18to5_19), .in_b(b4_19to5_19), .out_a(a5_19to5_20), .out_b(b5_19to6_19), .out_c(matrixC5_19)); +processing_element pe5_20(.reset(effective_rst), .clk(clk), .in_a(a5_19to5_20), .in_b(b4_20to5_20), .out_a(a5_20to5_21), .out_b(b5_20to6_20), .out_c(matrixC5_20)); +processing_element pe5_21(.reset(effective_rst), .clk(clk), .in_a(a5_20to5_21), .in_b(b4_21to5_21), .out_a(a5_21to5_22), .out_b(b5_21to6_21), .out_c(matrixC5_21)); +processing_element pe5_22(.reset(effective_rst), .clk(clk), .in_a(a5_21to5_22), .in_b(b4_22to5_22), .out_a(a5_22to5_23), .out_b(b5_22to6_22), .out_c(matrixC5_22)); +processing_element pe5_23(.reset(effective_rst), .clk(clk), .in_a(a5_22to5_23), .in_b(b4_23to5_23), .out_a(a5_23to5_24), .out_b(b5_23to6_23), .out_c(matrixC5_23)); +processing_element pe5_24(.reset(effective_rst), .clk(clk), .in_a(a5_23to5_24), .in_b(b4_24to5_24), .out_a(a5_24to5_25), .out_b(b5_24to6_24), .out_c(matrixC5_24)); +processing_element pe5_25(.reset(effective_rst), .clk(clk), .in_a(a5_24to5_25), .in_b(b4_25to5_25), .out_a(a5_25to5_26), .out_b(b5_25to6_25), .out_c(matrixC5_25)); +processing_element pe5_26(.reset(effective_rst), .clk(clk), .in_a(a5_25to5_26), .in_b(b4_26to5_26), .out_a(a5_26to5_27), .out_b(b5_26to6_26), .out_c(matrixC5_26)); +processing_element pe5_27(.reset(effective_rst), .clk(clk), .in_a(a5_26to5_27), .in_b(b4_27to5_27), .out_a(a5_27to5_28), .out_b(b5_27to6_27), .out_c(matrixC5_27)); +processing_element pe5_28(.reset(effective_rst), .clk(clk), .in_a(a5_27to5_28), .in_b(b4_28to5_28), .out_a(a5_28to5_29), .out_b(b5_28to6_28), .out_c(matrixC5_28)); +processing_element pe5_29(.reset(effective_rst), .clk(clk), .in_a(a5_28to5_29), .in_b(b4_29to5_29), .out_a(a5_29to5_30), .out_b(b5_29to6_29), .out_c(matrixC5_29)); +processing_element pe5_30(.reset(effective_rst), .clk(clk), .in_a(a5_29to5_30), .in_b(b4_30to5_30), .out_a(a5_30to5_31), .out_b(b5_30to6_30), .out_c(matrixC5_30)); +processing_element pe5_31(.reset(effective_rst), .clk(clk), .in_a(a5_30to5_31), .in_b(b4_31to5_31), .out_a(a5_31to5_32), .out_b(b5_31to6_31), .out_c(matrixC5_31)); +processing_element pe6_1(.reset(effective_rst), .clk(clk), .in_a(a6_0to6_1), .in_b(b5_1to6_1), .out_a(a6_1to6_2), .out_b(b6_1to7_1), .out_c(matrixC6_1)); +processing_element pe6_2(.reset(effective_rst), .clk(clk), .in_a(a6_1to6_2), .in_b(b5_2to6_2), .out_a(a6_2to6_3), .out_b(b6_2to7_2), .out_c(matrixC6_2)); +processing_element pe6_3(.reset(effective_rst), .clk(clk), .in_a(a6_2to6_3), .in_b(b5_3to6_3), .out_a(a6_3to6_4), .out_b(b6_3to7_3), .out_c(matrixC6_3)); +processing_element pe6_4(.reset(effective_rst), .clk(clk), .in_a(a6_3to6_4), .in_b(b5_4to6_4), .out_a(a6_4to6_5), .out_b(b6_4to7_4), .out_c(matrixC6_4)); +processing_element pe6_5(.reset(effective_rst), .clk(clk), .in_a(a6_4to6_5), .in_b(b5_5to6_5), .out_a(a6_5to6_6), .out_b(b6_5to7_5), .out_c(matrixC6_5)); +processing_element pe6_6(.reset(effective_rst), .clk(clk), .in_a(a6_5to6_6), .in_b(b5_6to6_6), .out_a(a6_6to6_7), .out_b(b6_6to7_6), .out_c(matrixC6_6)); +processing_element pe6_7(.reset(effective_rst), .clk(clk), .in_a(a6_6to6_7), .in_b(b5_7to6_7), .out_a(a6_7to6_8), .out_b(b6_7to7_7), .out_c(matrixC6_7)); +processing_element pe6_8(.reset(effective_rst), .clk(clk), .in_a(a6_7to6_8), .in_b(b5_8to6_8), .out_a(a6_8to6_9), .out_b(b6_8to7_8), .out_c(matrixC6_8)); +processing_element pe6_9(.reset(effective_rst), .clk(clk), .in_a(a6_8to6_9), .in_b(b5_9to6_9), .out_a(a6_9to6_10), .out_b(b6_9to7_9), .out_c(matrixC6_9)); +processing_element pe6_10(.reset(effective_rst), .clk(clk), .in_a(a6_9to6_10), .in_b(b5_10to6_10), .out_a(a6_10to6_11), .out_b(b6_10to7_10), .out_c(matrixC6_10)); +processing_element pe6_11(.reset(effective_rst), .clk(clk), .in_a(a6_10to6_11), .in_b(b5_11to6_11), .out_a(a6_11to6_12), .out_b(b6_11to7_11), .out_c(matrixC6_11)); +processing_element pe6_12(.reset(effective_rst), .clk(clk), .in_a(a6_11to6_12), .in_b(b5_12to6_12), .out_a(a6_12to6_13), .out_b(b6_12to7_12), .out_c(matrixC6_12)); +processing_element pe6_13(.reset(effective_rst), .clk(clk), .in_a(a6_12to6_13), .in_b(b5_13to6_13), .out_a(a6_13to6_14), .out_b(b6_13to7_13), .out_c(matrixC6_13)); +processing_element pe6_14(.reset(effective_rst), .clk(clk), .in_a(a6_13to6_14), .in_b(b5_14to6_14), .out_a(a6_14to6_15), .out_b(b6_14to7_14), .out_c(matrixC6_14)); +processing_element pe6_15(.reset(effective_rst), .clk(clk), .in_a(a6_14to6_15), .in_b(b5_15to6_15), .out_a(a6_15to6_16), .out_b(b6_15to7_15), .out_c(matrixC6_15)); +processing_element pe6_16(.reset(effective_rst), .clk(clk), .in_a(a6_15to6_16), .in_b(b5_16to6_16), .out_a(a6_16to6_17), .out_b(b6_16to7_16), .out_c(matrixC6_16)); +processing_element pe6_17(.reset(effective_rst), .clk(clk), .in_a(a6_16to6_17), .in_b(b5_17to6_17), .out_a(a6_17to6_18), .out_b(b6_17to7_17), .out_c(matrixC6_17)); +processing_element pe6_18(.reset(effective_rst), .clk(clk), .in_a(a6_17to6_18), .in_b(b5_18to6_18), .out_a(a6_18to6_19), .out_b(b6_18to7_18), .out_c(matrixC6_18)); +processing_element pe6_19(.reset(effective_rst), .clk(clk), .in_a(a6_18to6_19), .in_b(b5_19to6_19), .out_a(a6_19to6_20), .out_b(b6_19to7_19), .out_c(matrixC6_19)); +processing_element pe6_20(.reset(effective_rst), .clk(clk), .in_a(a6_19to6_20), .in_b(b5_20to6_20), .out_a(a6_20to6_21), .out_b(b6_20to7_20), .out_c(matrixC6_20)); +processing_element pe6_21(.reset(effective_rst), .clk(clk), .in_a(a6_20to6_21), .in_b(b5_21to6_21), .out_a(a6_21to6_22), .out_b(b6_21to7_21), .out_c(matrixC6_21)); +processing_element pe6_22(.reset(effective_rst), .clk(clk), .in_a(a6_21to6_22), .in_b(b5_22to6_22), .out_a(a6_22to6_23), .out_b(b6_22to7_22), .out_c(matrixC6_22)); +processing_element pe6_23(.reset(effective_rst), .clk(clk), .in_a(a6_22to6_23), .in_b(b5_23to6_23), .out_a(a6_23to6_24), .out_b(b6_23to7_23), .out_c(matrixC6_23)); +processing_element pe6_24(.reset(effective_rst), .clk(clk), .in_a(a6_23to6_24), .in_b(b5_24to6_24), .out_a(a6_24to6_25), .out_b(b6_24to7_24), .out_c(matrixC6_24)); +processing_element pe6_25(.reset(effective_rst), .clk(clk), .in_a(a6_24to6_25), .in_b(b5_25to6_25), .out_a(a6_25to6_26), .out_b(b6_25to7_25), .out_c(matrixC6_25)); +processing_element pe6_26(.reset(effective_rst), .clk(clk), .in_a(a6_25to6_26), .in_b(b5_26to6_26), .out_a(a6_26to6_27), .out_b(b6_26to7_26), .out_c(matrixC6_26)); +processing_element pe6_27(.reset(effective_rst), .clk(clk), .in_a(a6_26to6_27), .in_b(b5_27to6_27), .out_a(a6_27to6_28), .out_b(b6_27to7_27), .out_c(matrixC6_27)); +processing_element pe6_28(.reset(effective_rst), .clk(clk), .in_a(a6_27to6_28), .in_b(b5_28to6_28), .out_a(a6_28to6_29), .out_b(b6_28to7_28), .out_c(matrixC6_28)); +processing_element pe6_29(.reset(effective_rst), .clk(clk), .in_a(a6_28to6_29), .in_b(b5_29to6_29), .out_a(a6_29to6_30), .out_b(b6_29to7_29), .out_c(matrixC6_29)); +processing_element pe6_30(.reset(effective_rst), .clk(clk), .in_a(a6_29to6_30), .in_b(b5_30to6_30), .out_a(a6_30to6_31), .out_b(b6_30to7_30), .out_c(matrixC6_30)); +processing_element pe6_31(.reset(effective_rst), .clk(clk), .in_a(a6_30to6_31), .in_b(b5_31to6_31), .out_a(a6_31to6_32), .out_b(b6_31to7_31), .out_c(matrixC6_31)); +processing_element pe7_1(.reset(effective_rst), .clk(clk), .in_a(a7_0to7_1), .in_b(b6_1to7_1), .out_a(a7_1to7_2), .out_b(b7_1to8_1), .out_c(matrixC7_1)); +processing_element pe7_2(.reset(effective_rst), .clk(clk), .in_a(a7_1to7_2), .in_b(b6_2to7_2), .out_a(a7_2to7_3), .out_b(b7_2to8_2), .out_c(matrixC7_2)); +processing_element pe7_3(.reset(effective_rst), .clk(clk), .in_a(a7_2to7_3), .in_b(b6_3to7_3), .out_a(a7_3to7_4), .out_b(b7_3to8_3), .out_c(matrixC7_3)); +processing_element pe7_4(.reset(effective_rst), .clk(clk), .in_a(a7_3to7_4), .in_b(b6_4to7_4), .out_a(a7_4to7_5), .out_b(b7_4to8_4), .out_c(matrixC7_4)); +processing_element pe7_5(.reset(effective_rst), .clk(clk), .in_a(a7_4to7_5), .in_b(b6_5to7_5), .out_a(a7_5to7_6), .out_b(b7_5to8_5), .out_c(matrixC7_5)); +processing_element pe7_6(.reset(effective_rst), .clk(clk), .in_a(a7_5to7_6), .in_b(b6_6to7_6), .out_a(a7_6to7_7), .out_b(b7_6to8_6), .out_c(matrixC7_6)); +processing_element pe7_7(.reset(effective_rst), .clk(clk), .in_a(a7_6to7_7), .in_b(b6_7to7_7), .out_a(a7_7to7_8), .out_b(b7_7to8_7), .out_c(matrixC7_7)); +processing_element pe7_8(.reset(effective_rst), .clk(clk), .in_a(a7_7to7_8), .in_b(b6_8to7_8), .out_a(a7_8to7_9), .out_b(b7_8to8_8), .out_c(matrixC7_8)); +processing_element pe7_9(.reset(effective_rst), .clk(clk), .in_a(a7_8to7_9), .in_b(b6_9to7_9), .out_a(a7_9to7_10), .out_b(b7_9to8_9), .out_c(matrixC7_9)); +processing_element pe7_10(.reset(effective_rst), .clk(clk), .in_a(a7_9to7_10), .in_b(b6_10to7_10), .out_a(a7_10to7_11), .out_b(b7_10to8_10), .out_c(matrixC7_10)); +processing_element pe7_11(.reset(effective_rst), .clk(clk), .in_a(a7_10to7_11), .in_b(b6_11to7_11), .out_a(a7_11to7_12), .out_b(b7_11to8_11), .out_c(matrixC7_11)); +processing_element pe7_12(.reset(effective_rst), .clk(clk), .in_a(a7_11to7_12), .in_b(b6_12to7_12), .out_a(a7_12to7_13), .out_b(b7_12to8_12), .out_c(matrixC7_12)); +processing_element pe7_13(.reset(effective_rst), .clk(clk), .in_a(a7_12to7_13), .in_b(b6_13to7_13), .out_a(a7_13to7_14), .out_b(b7_13to8_13), .out_c(matrixC7_13)); +processing_element pe7_14(.reset(effective_rst), .clk(clk), .in_a(a7_13to7_14), .in_b(b6_14to7_14), .out_a(a7_14to7_15), .out_b(b7_14to8_14), .out_c(matrixC7_14)); +processing_element pe7_15(.reset(effective_rst), .clk(clk), .in_a(a7_14to7_15), .in_b(b6_15to7_15), .out_a(a7_15to7_16), .out_b(b7_15to8_15), .out_c(matrixC7_15)); +processing_element pe7_16(.reset(effective_rst), .clk(clk), .in_a(a7_15to7_16), .in_b(b6_16to7_16), .out_a(a7_16to7_17), .out_b(b7_16to8_16), .out_c(matrixC7_16)); +processing_element pe7_17(.reset(effective_rst), .clk(clk), .in_a(a7_16to7_17), .in_b(b6_17to7_17), .out_a(a7_17to7_18), .out_b(b7_17to8_17), .out_c(matrixC7_17)); +processing_element pe7_18(.reset(effective_rst), .clk(clk), .in_a(a7_17to7_18), .in_b(b6_18to7_18), .out_a(a7_18to7_19), .out_b(b7_18to8_18), .out_c(matrixC7_18)); +processing_element pe7_19(.reset(effective_rst), .clk(clk), .in_a(a7_18to7_19), .in_b(b6_19to7_19), .out_a(a7_19to7_20), .out_b(b7_19to8_19), .out_c(matrixC7_19)); +processing_element pe7_20(.reset(effective_rst), .clk(clk), .in_a(a7_19to7_20), .in_b(b6_20to7_20), .out_a(a7_20to7_21), .out_b(b7_20to8_20), .out_c(matrixC7_20)); +processing_element pe7_21(.reset(effective_rst), .clk(clk), .in_a(a7_20to7_21), .in_b(b6_21to7_21), .out_a(a7_21to7_22), .out_b(b7_21to8_21), .out_c(matrixC7_21)); +processing_element pe7_22(.reset(effective_rst), .clk(clk), .in_a(a7_21to7_22), .in_b(b6_22to7_22), .out_a(a7_22to7_23), .out_b(b7_22to8_22), .out_c(matrixC7_22)); +processing_element pe7_23(.reset(effective_rst), .clk(clk), .in_a(a7_22to7_23), .in_b(b6_23to7_23), .out_a(a7_23to7_24), .out_b(b7_23to8_23), .out_c(matrixC7_23)); +processing_element pe7_24(.reset(effective_rst), .clk(clk), .in_a(a7_23to7_24), .in_b(b6_24to7_24), .out_a(a7_24to7_25), .out_b(b7_24to8_24), .out_c(matrixC7_24)); +processing_element pe7_25(.reset(effective_rst), .clk(clk), .in_a(a7_24to7_25), .in_b(b6_25to7_25), .out_a(a7_25to7_26), .out_b(b7_25to8_25), .out_c(matrixC7_25)); +processing_element pe7_26(.reset(effective_rst), .clk(clk), .in_a(a7_25to7_26), .in_b(b6_26to7_26), .out_a(a7_26to7_27), .out_b(b7_26to8_26), .out_c(matrixC7_26)); +processing_element pe7_27(.reset(effective_rst), .clk(clk), .in_a(a7_26to7_27), .in_b(b6_27to7_27), .out_a(a7_27to7_28), .out_b(b7_27to8_27), .out_c(matrixC7_27)); +processing_element pe7_28(.reset(effective_rst), .clk(clk), .in_a(a7_27to7_28), .in_b(b6_28to7_28), .out_a(a7_28to7_29), .out_b(b7_28to8_28), .out_c(matrixC7_28)); +processing_element pe7_29(.reset(effective_rst), .clk(clk), .in_a(a7_28to7_29), .in_b(b6_29to7_29), .out_a(a7_29to7_30), .out_b(b7_29to8_29), .out_c(matrixC7_29)); +processing_element pe7_30(.reset(effective_rst), .clk(clk), .in_a(a7_29to7_30), .in_b(b6_30to7_30), .out_a(a7_30to7_31), .out_b(b7_30to8_30), .out_c(matrixC7_30)); +processing_element pe7_31(.reset(effective_rst), .clk(clk), .in_a(a7_30to7_31), .in_b(b6_31to7_31), .out_a(a7_31to7_32), .out_b(b7_31to8_31), .out_c(matrixC7_31)); +processing_element pe8_1(.reset(effective_rst), .clk(clk), .in_a(a8_0to8_1), .in_b(b7_1to8_1), .out_a(a8_1to8_2), .out_b(b8_1to9_1), .out_c(matrixC8_1)); +processing_element pe8_2(.reset(effective_rst), .clk(clk), .in_a(a8_1to8_2), .in_b(b7_2to8_2), .out_a(a8_2to8_3), .out_b(b8_2to9_2), .out_c(matrixC8_2)); +processing_element pe8_3(.reset(effective_rst), .clk(clk), .in_a(a8_2to8_3), .in_b(b7_3to8_3), .out_a(a8_3to8_4), .out_b(b8_3to9_3), .out_c(matrixC8_3)); +processing_element pe8_4(.reset(effective_rst), .clk(clk), .in_a(a8_3to8_4), .in_b(b7_4to8_4), .out_a(a8_4to8_5), .out_b(b8_4to9_4), .out_c(matrixC8_4)); +processing_element pe8_5(.reset(effective_rst), .clk(clk), .in_a(a8_4to8_5), .in_b(b7_5to8_5), .out_a(a8_5to8_6), .out_b(b8_5to9_5), .out_c(matrixC8_5)); +processing_element pe8_6(.reset(effective_rst), .clk(clk), .in_a(a8_5to8_6), .in_b(b7_6to8_6), .out_a(a8_6to8_7), .out_b(b8_6to9_6), .out_c(matrixC8_6)); +processing_element pe8_7(.reset(effective_rst), .clk(clk), .in_a(a8_6to8_7), .in_b(b7_7to8_7), .out_a(a8_7to8_8), .out_b(b8_7to9_7), .out_c(matrixC8_7)); +processing_element pe8_8(.reset(effective_rst), .clk(clk), .in_a(a8_7to8_8), .in_b(b7_8to8_8), .out_a(a8_8to8_9), .out_b(b8_8to9_8), .out_c(matrixC8_8)); +processing_element pe8_9(.reset(effective_rst), .clk(clk), .in_a(a8_8to8_9), .in_b(b7_9to8_9), .out_a(a8_9to8_10), .out_b(b8_9to9_9), .out_c(matrixC8_9)); +processing_element pe8_10(.reset(effective_rst), .clk(clk), .in_a(a8_9to8_10), .in_b(b7_10to8_10), .out_a(a8_10to8_11), .out_b(b8_10to9_10), .out_c(matrixC8_10)); +processing_element pe8_11(.reset(effective_rst), .clk(clk), .in_a(a8_10to8_11), .in_b(b7_11to8_11), .out_a(a8_11to8_12), .out_b(b8_11to9_11), .out_c(matrixC8_11)); +processing_element pe8_12(.reset(effective_rst), .clk(clk), .in_a(a8_11to8_12), .in_b(b7_12to8_12), .out_a(a8_12to8_13), .out_b(b8_12to9_12), .out_c(matrixC8_12)); +processing_element pe8_13(.reset(effective_rst), .clk(clk), .in_a(a8_12to8_13), .in_b(b7_13to8_13), .out_a(a8_13to8_14), .out_b(b8_13to9_13), .out_c(matrixC8_13)); +processing_element pe8_14(.reset(effective_rst), .clk(clk), .in_a(a8_13to8_14), .in_b(b7_14to8_14), .out_a(a8_14to8_15), .out_b(b8_14to9_14), .out_c(matrixC8_14)); +processing_element pe8_15(.reset(effective_rst), .clk(clk), .in_a(a8_14to8_15), .in_b(b7_15to8_15), .out_a(a8_15to8_16), .out_b(b8_15to9_15), .out_c(matrixC8_15)); +processing_element pe8_16(.reset(effective_rst), .clk(clk), .in_a(a8_15to8_16), .in_b(b7_16to8_16), .out_a(a8_16to8_17), .out_b(b8_16to9_16), .out_c(matrixC8_16)); +processing_element pe8_17(.reset(effective_rst), .clk(clk), .in_a(a8_16to8_17), .in_b(b7_17to8_17), .out_a(a8_17to8_18), .out_b(b8_17to9_17), .out_c(matrixC8_17)); +processing_element pe8_18(.reset(effective_rst), .clk(clk), .in_a(a8_17to8_18), .in_b(b7_18to8_18), .out_a(a8_18to8_19), .out_b(b8_18to9_18), .out_c(matrixC8_18)); +processing_element pe8_19(.reset(effective_rst), .clk(clk), .in_a(a8_18to8_19), .in_b(b7_19to8_19), .out_a(a8_19to8_20), .out_b(b8_19to9_19), .out_c(matrixC8_19)); +processing_element pe8_20(.reset(effective_rst), .clk(clk), .in_a(a8_19to8_20), .in_b(b7_20to8_20), .out_a(a8_20to8_21), .out_b(b8_20to9_20), .out_c(matrixC8_20)); +processing_element pe8_21(.reset(effective_rst), .clk(clk), .in_a(a8_20to8_21), .in_b(b7_21to8_21), .out_a(a8_21to8_22), .out_b(b8_21to9_21), .out_c(matrixC8_21)); +processing_element pe8_22(.reset(effective_rst), .clk(clk), .in_a(a8_21to8_22), .in_b(b7_22to8_22), .out_a(a8_22to8_23), .out_b(b8_22to9_22), .out_c(matrixC8_22)); +processing_element pe8_23(.reset(effective_rst), .clk(clk), .in_a(a8_22to8_23), .in_b(b7_23to8_23), .out_a(a8_23to8_24), .out_b(b8_23to9_23), .out_c(matrixC8_23)); +processing_element pe8_24(.reset(effective_rst), .clk(clk), .in_a(a8_23to8_24), .in_b(b7_24to8_24), .out_a(a8_24to8_25), .out_b(b8_24to9_24), .out_c(matrixC8_24)); +processing_element pe8_25(.reset(effective_rst), .clk(clk), .in_a(a8_24to8_25), .in_b(b7_25to8_25), .out_a(a8_25to8_26), .out_b(b8_25to9_25), .out_c(matrixC8_25)); +processing_element pe8_26(.reset(effective_rst), .clk(clk), .in_a(a8_25to8_26), .in_b(b7_26to8_26), .out_a(a8_26to8_27), .out_b(b8_26to9_26), .out_c(matrixC8_26)); +processing_element pe8_27(.reset(effective_rst), .clk(clk), .in_a(a8_26to8_27), .in_b(b7_27to8_27), .out_a(a8_27to8_28), .out_b(b8_27to9_27), .out_c(matrixC8_27)); +processing_element pe8_28(.reset(effective_rst), .clk(clk), .in_a(a8_27to8_28), .in_b(b7_28to8_28), .out_a(a8_28to8_29), .out_b(b8_28to9_28), .out_c(matrixC8_28)); +processing_element pe8_29(.reset(effective_rst), .clk(clk), .in_a(a8_28to8_29), .in_b(b7_29to8_29), .out_a(a8_29to8_30), .out_b(b8_29to9_29), .out_c(matrixC8_29)); +processing_element pe8_30(.reset(effective_rst), .clk(clk), .in_a(a8_29to8_30), .in_b(b7_30to8_30), .out_a(a8_30to8_31), .out_b(b8_30to9_30), .out_c(matrixC8_30)); +processing_element pe8_31(.reset(effective_rst), .clk(clk), .in_a(a8_30to8_31), .in_b(b7_31to8_31), .out_a(a8_31to8_32), .out_b(b8_31to9_31), .out_c(matrixC8_31)); +processing_element pe9_1(.reset(effective_rst), .clk(clk), .in_a(a9_0to9_1), .in_b(b8_1to9_1), .out_a(a9_1to9_2), .out_b(b9_1to10_1), .out_c(matrixC9_1)); +processing_element pe9_2(.reset(effective_rst), .clk(clk), .in_a(a9_1to9_2), .in_b(b8_2to9_2), .out_a(a9_2to9_3), .out_b(b9_2to10_2), .out_c(matrixC9_2)); +processing_element pe9_3(.reset(effective_rst), .clk(clk), .in_a(a9_2to9_3), .in_b(b8_3to9_3), .out_a(a9_3to9_4), .out_b(b9_3to10_3), .out_c(matrixC9_3)); +processing_element pe9_4(.reset(effective_rst), .clk(clk), .in_a(a9_3to9_4), .in_b(b8_4to9_4), .out_a(a9_4to9_5), .out_b(b9_4to10_4), .out_c(matrixC9_4)); +processing_element pe9_5(.reset(effective_rst), .clk(clk), .in_a(a9_4to9_5), .in_b(b8_5to9_5), .out_a(a9_5to9_6), .out_b(b9_5to10_5), .out_c(matrixC9_5)); +processing_element pe9_6(.reset(effective_rst), .clk(clk), .in_a(a9_5to9_6), .in_b(b8_6to9_6), .out_a(a9_6to9_7), .out_b(b9_6to10_6), .out_c(matrixC9_6)); +processing_element pe9_7(.reset(effective_rst), .clk(clk), .in_a(a9_6to9_7), .in_b(b8_7to9_7), .out_a(a9_7to9_8), .out_b(b9_7to10_7), .out_c(matrixC9_7)); +processing_element pe9_8(.reset(effective_rst), .clk(clk), .in_a(a9_7to9_8), .in_b(b8_8to9_8), .out_a(a9_8to9_9), .out_b(b9_8to10_8), .out_c(matrixC9_8)); +processing_element pe9_9(.reset(effective_rst), .clk(clk), .in_a(a9_8to9_9), .in_b(b8_9to9_9), .out_a(a9_9to9_10), .out_b(b9_9to10_9), .out_c(matrixC9_9)); +processing_element pe9_10(.reset(effective_rst), .clk(clk), .in_a(a9_9to9_10), .in_b(b8_10to9_10), .out_a(a9_10to9_11), .out_b(b9_10to10_10), .out_c(matrixC9_10)); +processing_element pe9_11(.reset(effective_rst), .clk(clk), .in_a(a9_10to9_11), .in_b(b8_11to9_11), .out_a(a9_11to9_12), .out_b(b9_11to10_11), .out_c(matrixC9_11)); +processing_element pe9_12(.reset(effective_rst), .clk(clk), .in_a(a9_11to9_12), .in_b(b8_12to9_12), .out_a(a9_12to9_13), .out_b(b9_12to10_12), .out_c(matrixC9_12)); +processing_element pe9_13(.reset(effective_rst), .clk(clk), .in_a(a9_12to9_13), .in_b(b8_13to9_13), .out_a(a9_13to9_14), .out_b(b9_13to10_13), .out_c(matrixC9_13)); +processing_element pe9_14(.reset(effective_rst), .clk(clk), .in_a(a9_13to9_14), .in_b(b8_14to9_14), .out_a(a9_14to9_15), .out_b(b9_14to10_14), .out_c(matrixC9_14)); +processing_element pe9_15(.reset(effective_rst), .clk(clk), .in_a(a9_14to9_15), .in_b(b8_15to9_15), .out_a(a9_15to9_16), .out_b(b9_15to10_15), .out_c(matrixC9_15)); +processing_element pe9_16(.reset(effective_rst), .clk(clk), .in_a(a9_15to9_16), .in_b(b8_16to9_16), .out_a(a9_16to9_17), .out_b(b9_16to10_16), .out_c(matrixC9_16)); +processing_element pe9_17(.reset(effective_rst), .clk(clk), .in_a(a9_16to9_17), .in_b(b8_17to9_17), .out_a(a9_17to9_18), .out_b(b9_17to10_17), .out_c(matrixC9_17)); +processing_element pe9_18(.reset(effective_rst), .clk(clk), .in_a(a9_17to9_18), .in_b(b8_18to9_18), .out_a(a9_18to9_19), .out_b(b9_18to10_18), .out_c(matrixC9_18)); +processing_element pe9_19(.reset(effective_rst), .clk(clk), .in_a(a9_18to9_19), .in_b(b8_19to9_19), .out_a(a9_19to9_20), .out_b(b9_19to10_19), .out_c(matrixC9_19)); +processing_element pe9_20(.reset(effective_rst), .clk(clk), .in_a(a9_19to9_20), .in_b(b8_20to9_20), .out_a(a9_20to9_21), .out_b(b9_20to10_20), .out_c(matrixC9_20)); +processing_element pe9_21(.reset(effective_rst), .clk(clk), .in_a(a9_20to9_21), .in_b(b8_21to9_21), .out_a(a9_21to9_22), .out_b(b9_21to10_21), .out_c(matrixC9_21)); +processing_element pe9_22(.reset(effective_rst), .clk(clk), .in_a(a9_21to9_22), .in_b(b8_22to9_22), .out_a(a9_22to9_23), .out_b(b9_22to10_22), .out_c(matrixC9_22)); +processing_element pe9_23(.reset(effective_rst), .clk(clk), .in_a(a9_22to9_23), .in_b(b8_23to9_23), .out_a(a9_23to9_24), .out_b(b9_23to10_23), .out_c(matrixC9_23)); +processing_element pe9_24(.reset(effective_rst), .clk(clk), .in_a(a9_23to9_24), .in_b(b8_24to9_24), .out_a(a9_24to9_25), .out_b(b9_24to10_24), .out_c(matrixC9_24)); +processing_element pe9_25(.reset(effective_rst), .clk(clk), .in_a(a9_24to9_25), .in_b(b8_25to9_25), .out_a(a9_25to9_26), .out_b(b9_25to10_25), .out_c(matrixC9_25)); +processing_element pe9_26(.reset(effective_rst), .clk(clk), .in_a(a9_25to9_26), .in_b(b8_26to9_26), .out_a(a9_26to9_27), .out_b(b9_26to10_26), .out_c(matrixC9_26)); +processing_element pe9_27(.reset(effective_rst), .clk(clk), .in_a(a9_26to9_27), .in_b(b8_27to9_27), .out_a(a9_27to9_28), .out_b(b9_27to10_27), .out_c(matrixC9_27)); +processing_element pe9_28(.reset(effective_rst), .clk(clk), .in_a(a9_27to9_28), .in_b(b8_28to9_28), .out_a(a9_28to9_29), .out_b(b9_28to10_28), .out_c(matrixC9_28)); +processing_element pe9_29(.reset(effective_rst), .clk(clk), .in_a(a9_28to9_29), .in_b(b8_29to9_29), .out_a(a9_29to9_30), .out_b(b9_29to10_29), .out_c(matrixC9_29)); +processing_element pe9_30(.reset(effective_rst), .clk(clk), .in_a(a9_29to9_30), .in_b(b8_30to9_30), .out_a(a9_30to9_31), .out_b(b9_30to10_30), .out_c(matrixC9_30)); +processing_element pe9_31(.reset(effective_rst), .clk(clk), .in_a(a9_30to9_31), .in_b(b8_31to9_31), .out_a(a9_31to9_32), .out_b(b9_31to10_31), .out_c(matrixC9_31)); +processing_element pe10_1(.reset(effective_rst), .clk(clk), .in_a(a10_0to10_1), .in_b(b9_1to10_1), .out_a(a10_1to10_2), .out_b(b10_1to11_1), .out_c(matrixC10_1)); +processing_element pe10_2(.reset(effective_rst), .clk(clk), .in_a(a10_1to10_2), .in_b(b9_2to10_2), .out_a(a10_2to10_3), .out_b(b10_2to11_2), .out_c(matrixC10_2)); +processing_element pe10_3(.reset(effective_rst), .clk(clk), .in_a(a10_2to10_3), .in_b(b9_3to10_3), .out_a(a10_3to10_4), .out_b(b10_3to11_3), .out_c(matrixC10_3)); +processing_element pe10_4(.reset(effective_rst), .clk(clk), .in_a(a10_3to10_4), .in_b(b9_4to10_4), .out_a(a10_4to10_5), .out_b(b10_4to11_4), .out_c(matrixC10_4)); +processing_element pe10_5(.reset(effective_rst), .clk(clk), .in_a(a10_4to10_5), .in_b(b9_5to10_5), .out_a(a10_5to10_6), .out_b(b10_5to11_5), .out_c(matrixC10_5)); +processing_element pe10_6(.reset(effective_rst), .clk(clk), .in_a(a10_5to10_6), .in_b(b9_6to10_6), .out_a(a10_6to10_7), .out_b(b10_6to11_6), .out_c(matrixC10_6)); +processing_element pe10_7(.reset(effective_rst), .clk(clk), .in_a(a10_6to10_7), .in_b(b9_7to10_7), .out_a(a10_7to10_8), .out_b(b10_7to11_7), .out_c(matrixC10_7)); +processing_element pe10_8(.reset(effective_rst), .clk(clk), .in_a(a10_7to10_8), .in_b(b9_8to10_8), .out_a(a10_8to10_9), .out_b(b10_8to11_8), .out_c(matrixC10_8)); +processing_element pe10_9(.reset(effective_rst), .clk(clk), .in_a(a10_8to10_9), .in_b(b9_9to10_9), .out_a(a10_9to10_10), .out_b(b10_9to11_9), .out_c(matrixC10_9)); +processing_element pe10_10(.reset(effective_rst), .clk(clk), .in_a(a10_9to10_10), .in_b(b9_10to10_10), .out_a(a10_10to10_11), .out_b(b10_10to11_10), .out_c(matrixC10_10)); +processing_element pe10_11(.reset(effective_rst), .clk(clk), .in_a(a10_10to10_11), .in_b(b9_11to10_11), .out_a(a10_11to10_12), .out_b(b10_11to11_11), .out_c(matrixC10_11)); +processing_element pe10_12(.reset(effective_rst), .clk(clk), .in_a(a10_11to10_12), .in_b(b9_12to10_12), .out_a(a10_12to10_13), .out_b(b10_12to11_12), .out_c(matrixC10_12)); +processing_element pe10_13(.reset(effective_rst), .clk(clk), .in_a(a10_12to10_13), .in_b(b9_13to10_13), .out_a(a10_13to10_14), .out_b(b10_13to11_13), .out_c(matrixC10_13)); +processing_element pe10_14(.reset(effective_rst), .clk(clk), .in_a(a10_13to10_14), .in_b(b9_14to10_14), .out_a(a10_14to10_15), .out_b(b10_14to11_14), .out_c(matrixC10_14)); +processing_element pe10_15(.reset(effective_rst), .clk(clk), .in_a(a10_14to10_15), .in_b(b9_15to10_15), .out_a(a10_15to10_16), .out_b(b10_15to11_15), .out_c(matrixC10_15)); +processing_element pe10_16(.reset(effective_rst), .clk(clk), .in_a(a10_15to10_16), .in_b(b9_16to10_16), .out_a(a10_16to10_17), .out_b(b10_16to11_16), .out_c(matrixC10_16)); +processing_element pe10_17(.reset(effective_rst), .clk(clk), .in_a(a10_16to10_17), .in_b(b9_17to10_17), .out_a(a10_17to10_18), .out_b(b10_17to11_17), .out_c(matrixC10_17)); +processing_element pe10_18(.reset(effective_rst), .clk(clk), .in_a(a10_17to10_18), .in_b(b9_18to10_18), .out_a(a10_18to10_19), .out_b(b10_18to11_18), .out_c(matrixC10_18)); +processing_element pe10_19(.reset(effective_rst), .clk(clk), .in_a(a10_18to10_19), .in_b(b9_19to10_19), .out_a(a10_19to10_20), .out_b(b10_19to11_19), .out_c(matrixC10_19)); +processing_element pe10_20(.reset(effective_rst), .clk(clk), .in_a(a10_19to10_20), .in_b(b9_20to10_20), .out_a(a10_20to10_21), .out_b(b10_20to11_20), .out_c(matrixC10_20)); +processing_element pe10_21(.reset(effective_rst), .clk(clk), .in_a(a10_20to10_21), .in_b(b9_21to10_21), .out_a(a10_21to10_22), .out_b(b10_21to11_21), .out_c(matrixC10_21)); +processing_element pe10_22(.reset(effective_rst), .clk(clk), .in_a(a10_21to10_22), .in_b(b9_22to10_22), .out_a(a10_22to10_23), .out_b(b10_22to11_22), .out_c(matrixC10_22)); +processing_element pe10_23(.reset(effective_rst), .clk(clk), .in_a(a10_22to10_23), .in_b(b9_23to10_23), .out_a(a10_23to10_24), .out_b(b10_23to11_23), .out_c(matrixC10_23)); +processing_element pe10_24(.reset(effective_rst), .clk(clk), .in_a(a10_23to10_24), .in_b(b9_24to10_24), .out_a(a10_24to10_25), .out_b(b10_24to11_24), .out_c(matrixC10_24)); +processing_element pe10_25(.reset(effective_rst), .clk(clk), .in_a(a10_24to10_25), .in_b(b9_25to10_25), .out_a(a10_25to10_26), .out_b(b10_25to11_25), .out_c(matrixC10_25)); +processing_element pe10_26(.reset(effective_rst), .clk(clk), .in_a(a10_25to10_26), .in_b(b9_26to10_26), .out_a(a10_26to10_27), .out_b(b10_26to11_26), .out_c(matrixC10_26)); +processing_element pe10_27(.reset(effective_rst), .clk(clk), .in_a(a10_26to10_27), .in_b(b9_27to10_27), .out_a(a10_27to10_28), .out_b(b10_27to11_27), .out_c(matrixC10_27)); +processing_element pe10_28(.reset(effective_rst), .clk(clk), .in_a(a10_27to10_28), .in_b(b9_28to10_28), .out_a(a10_28to10_29), .out_b(b10_28to11_28), .out_c(matrixC10_28)); +processing_element pe10_29(.reset(effective_rst), .clk(clk), .in_a(a10_28to10_29), .in_b(b9_29to10_29), .out_a(a10_29to10_30), .out_b(b10_29to11_29), .out_c(matrixC10_29)); +processing_element pe10_30(.reset(effective_rst), .clk(clk), .in_a(a10_29to10_30), .in_b(b9_30to10_30), .out_a(a10_30to10_31), .out_b(b10_30to11_30), .out_c(matrixC10_30)); +processing_element pe10_31(.reset(effective_rst), .clk(clk), .in_a(a10_30to10_31), .in_b(b9_31to10_31), .out_a(a10_31to10_32), .out_b(b10_31to11_31), .out_c(matrixC10_31)); +processing_element pe11_1(.reset(effective_rst), .clk(clk), .in_a(a11_0to11_1), .in_b(b10_1to11_1), .out_a(a11_1to11_2), .out_b(b11_1to12_1), .out_c(matrixC11_1)); +processing_element pe11_2(.reset(effective_rst), .clk(clk), .in_a(a11_1to11_2), .in_b(b10_2to11_2), .out_a(a11_2to11_3), .out_b(b11_2to12_2), .out_c(matrixC11_2)); +processing_element pe11_3(.reset(effective_rst), .clk(clk), .in_a(a11_2to11_3), .in_b(b10_3to11_3), .out_a(a11_3to11_4), .out_b(b11_3to12_3), .out_c(matrixC11_3)); +processing_element pe11_4(.reset(effective_rst), .clk(clk), .in_a(a11_3to11_4), .in_b(b10_4to11_4), .out_a(a11_4to11_5), .out_b(b11_4to12_4), .out_c(matrixC11_4)); +processing_element pe11_5(.reset(effective_rst), .clk(clk), .in_a(a11_4to11_5), .in_b(b10_5to11_5), .out_a(a11_5to11_6), .out_b(b11_5to12_5), .out_c(matrixC11_5)); +processing_element pe11_6(.reset(effective_rst), .clk(clk), .in_a(a11_5to11_6), .in_b(b10_6to11_6), .out_a(a11_6to11_7), .out_b(b11_6to12_6), .out_c(matrixC11_6)); +processing_element pe11_7(.reset(effective_rst), .clk(clk), .in_a(a11_6to11_7), .in_b(b10_7to11_7), .out_a(a11_7to11_8), .out_b(b11_7to12_7), .out_c(matrixC11_7)); +processing_element pe11_8(.reset(effective_rst), .clk(clk), .in_a(a11_7to11_8), .in_b(b10_8to11_8), .out_a(a11_8to11_9), .out_b(b11_8to12_8), .out_c(matrixC11_8)); +processing_element pe11_9(.reset(effective_rst), .clk(clk), .in_a(a11_8to11_9), .in_b(b10_9to11_9), .out_a(a11_9to11_10), .out_b(b11_9to12_9), .out_c(matrixC11_9)); +processing_element pe11_10(.reset(effective_rst), .clk(clk), .in_a(a11_9to11_10), .in_b(b10_10to11_10), .out_a(a11_10to11_11), .out_b(b11_10to12_10), .out_c(matrixC11_10)); +processing_element pe11_11(.reset(effective_rst), .clk(clk), .in_a(a11_10to11_11), .in_b(b10_11to11_11), .out_a(a11_11to11_12), .out_b(b11_11to12_11), .out_c(matrixC11_11)); +processing_element pe11_12(.reset(effective_rst), .clk(clk), .in_a(a11_11to11_12), .in_b(b10_12to11_12), .out_a(a11_12to11_13), .out_b(b11_12to12_12), .out_c(matrixC11_12)); +processing_element pe11_13(.reset(effective_rst), .clk(clk), .in_a(a11_12to11_13), .in_b(b10_13to11_13), .out_a(a11_13to11_14), .out_b(b11_13to12_13), .out_c(matrixC11_13)); +processing_element pe11_14(.reset(effective_rst), .clk(clk), .in_a(a11_13to11_14), .in_b(b10_14to11_14), .out_a(a11_14to11_15), .out_b(b11_14to12_14), .out_c(matrixC11_14)); +processing_element pe11_15(.reset(effective_rst), .clk(clk), .in_a(a11_14to11_15), .in_b(b10_15to11_15), .out_a(a11_15to11_16), .out_b(b11_15to12_15), .out_c(matrixC11_15)); +processing_element pe11_16(.reset(effective_rst), .clk(clk), .in_a(a11_15to11_16), .in_b(b10_16to11_16), .out_a(a11_16to11_17), .out_b(b11_16to12_16), .out_c(matrixC11_16)); +processing_element pe11_17(.reset(effective_rst), .clk(clk), .in_a(a11_16to11_17), .in_b(b10_17to11_17), .out_a(a11_17to11_18), .out_b(b11_17to12_17), .out_c(matrixC11_17)); +processing_element pe11_18(.reset(effective_rst), .clk(clk), .in_a(a11_17to11_18), .in_b(b10_18to11_18), .out_a(a11_18to11_19), .out_b(b11_18to12_18), .out_c(matrixC11_18)); +processing_element pe11_19(.reset(effective_rst), .clk(clk), .in_a(a11_18to11_19), .in_b(b10_19to11_19), .out_a(a11_19to11_20), .out_b(b11_19to12_19), .out_c(matrixC11_19)); +processing_element pe11_20(.reset(effective_rst), .clk(clk), .in_a(a11_19to11_20), .in_b(b10_20to11_20), .out_a(a11_20to11_21), .out_b(b11_20to12_20), .out_c(matrixC11_20)); +processing_element pe11_21(.reset(effective_rst), .clk(clk), .in_a(a11_20to11_21), .in_b(b10_21to11_21), .out_a(a11_21to11_22), .out_b(b11_21to12_21), .out_c(matrixC11_21)); +processing_element pe11_22(.reset(effective_rst), .clk(clk), .in_a(a11_21to11_22), .in_b(b10_22to11_22), .out_a(a11_22to11_23), .out_b(b11_22to12_22), .out_c(matrixC11_22)); +processing_element pe11_23(.reset(effective_rst), .clk(clk), .in_a(a11_22to11_23), .in_b(b10_23to11_23), .out_a(a11_23to11_24), .out_b(b11_23to12_23), .out_c(matrixC11_23)); +processing_element pe11_24(.reset(effective_rst), .clk(clk), .in_a(a11_23to11_24), .in_b(b10_24to11_24), .out_a(a11_24to11_25), .out_b(b11_24to12_24), .out_c(matrixC11_24)); +processing_element pe11_25(.reset(effective_rst), .clk(clk), .in_a(a11_24to11_25), .in_b(b10_25to11_25), .out_a(a11_25to11_26), .out_b(b11_25to12_25), .out_c(matrixC11_25)); +processing_element pe11_26(.reset(effective_rst), .clk(clk), .in_a(a11_25to11_26), .in_b(b10_26to11_26), .out_a(a11_26to11_27), .out_b(b11_26to12_26), .out_c(matrixC11_26)); +processing_element pe11_27(.reset(effective_rst), .clk(clk), .in_a(a11_26to11_27), .in_b(b10_27to11_27), .out_a(a11_27to11_28), .out_b(b11_27to12_27), .out_c(matrixC11_27)); +processing_element pe11_28(.reset(effective_rst), .clk(clk), .in_a(a11_27to11_28), .in_b(b10_28to11_28), .out_a(a11_28to11_29), .out_b(b11_28to12_28), .out_c(matrixC11_28)); +processing_element pe11_29(.reset(effective_rst), .clk(clk), .in_a(a11_28to11_29), .in_b(b10_29to11_29), .out_a(a11_29to11_30), .out_b(b11_29to12_29), .out_c(matrixC11_29)); +processing_element pe11_30(.reset(effective_rst), .clk(clk), .in_a(a11_29to11_30), .in_b(b10_30to11_30), .out_a(a11_30to11_31), .out_b(b11_30to12_30), .out_c(matrixC11_30)); +processing_element pe11_31(.reset(effective_rst), .clk(clk), .in_a(a11_30to11_31), .in_b(b10_31to11_31), .out_a(a11_31to11_32), .out_b(b11_31to12_31), .out_c(matrixC11_31)); +processing_element pe12_1(.reset(effective_rst), .clk(clk), .in_a(a12_0to12_1), .in_b(b11_1to12_1), .out_a(a12_1to12_2), .out_b(b12_1to13_1), .out_c(matrixC12_1)); +processing_element pe12_2(.reset(effective_rst), .clk(clk), .in_a(a12_1to12_2), .in_b(b11_2to12_2), .out_a(a12_2to12_3), .out_b(b12_2to13_2), .out_c(matrixC12_2)); +processing_element pe12_3(.reset(effective_rst), .clk(clk), .in_a(a12_2to12_3), .in_b(b11_3to12_3), .out_a(a12_3to12_4), .out_b(b12_3to13_3), .out_c(matrixC12_3)); +processing_element pe12_4(.reset(effective_rst), .clk(clk), .in_a(a12_3to12_4), .in_b(b11_4to12_4), .out_a(a12_4to12_5), .out_b(b12_4to13_4), .out_c(matrixC12_4)); +processing_element pe12_5(.reset(effective_rst), .clk(clk), .in_a(a12_4to12_5), .in_b(b11_5to12_5), .out_a(a12_5to12_6), .out_b(b12_5to13_5), .out_c(matrixC12_5)); +processing_element pe12_6(.reset(effective_rst), .clk(clk), .in_a(a12_5to12_6), .in_b(b11_6to12_6), .out_a(a12_6to12_7), .out_b(b12_6to13_6), .out_c(matrixC12_6)); +processing_element pe12_7(.reset(effective_rst), .clk(clk), .in_a(a12_6to12_7), .in_b(b11_7to12_7), .out_a(a12_7to12_8), .out_b(b12_7to13_7), .out_c(matrixC12_7)); +processing_element pe12_8(.reset(effective_rst), .clk(clk), .in_a(a12_7to12_8), .in_b(b11_8to12_8), .out_a(a12_8to12_9), .out_b(b12_8to13_8), .out_c(matrixC12_8)); +processing_element pe12_9(.reset(effective_rst), .clk(clk), .in_a(a12_8to12_9), .in_b(b11_9to12_9), .out_a(a12_9to12_10), .out_b(b12_9to13_9), .out_c(matrixC12_9)); +processing_element pe12_10(.reset(effective_rst), .clk(clk), .in_a(a12_9to12_10), .in_b(b11_10to12_10), .out_a(a12_10to12_11), .out_b(b12_10to13_10), .out_c(matrixC12_10)); +processing_element pe12_11(.reset(effective_rst), .clk(clk), .in_a(a12_10to12_11), .in_b(b11_11to12_11), .out_a(a12_11to12_12), .out_b(b12_11to13_11), .out_c(matrixC12_11)); +processing_element pe12_12(.reset(effective_rst), .clk(clk), .in_a(a12_11to12_12), .in_b(b11_12to12_12), .out_a(a12_12to12_13), .out_b(b12_12to13_12), .out_c(matrixC12_12)); +processing_element pe12_13(.reset(effective_rst), .clk(clk), .in_a(a12_12to12_13), .in_b(b11_13to12_13), .out_a(a12_13to12_14), .out_b(b12_13to13_13), .out_c(matrixC12_13)); +processing_element pe12_14(.reset(effective_rst), .clk(clk), .in_a(a12_13to12_14), .in_b(b11_14to12_14), .out_a(a12_14to12_15), .out_b(b12_14to13_14), .out_c(matrixC12_14)); +processing_element pe12_15(.reset(effective_rst), .clk(clk), .in_a(a12_14to12_15), .in_b(b11_15to12_15), .out_a(a12_15to12_16), .out_b(b12_15to13_15), .out_c(matrixC12_15)); +processing_element pe12_16(.reset(effective_rst), .clk(clk), .in_a(a12_15to12_16), .in_b(b11_16to12_16), .out_a(a12_16to12_17), .out_b(b12_16to13_16), .out_c(matrixC12_16)); +processing_element pe12_17(.reset(effective_rst), .clk(clk), .in_a(a12_16to12_17), .in_b(b11_17to12_17), .out_a(a12_17to12_18), .out_b(b12_17to13_17), .out_c(matrixC12_17)); +processing_element pe12_18(.reset(effective_rst), .clk(clk), .in_a(a12_17to12_18), .in_b(b11_18to12_18), .out_a(a12_18to12_19), .out_b(b12_18to13_18), .out_c(matrixC12_18)); +processing_element pe12_19(.reset(effective_rst), .clk(clk), .in_a(a12_18to12_19), .in_b(b11_19to12_19), .out_a(a12_19to12_20), .out_b(b12_19to13_19), .out_c(matrixC12_19)); +processing_element pe12_20(.reset(effective_rst), .clk(clk), .in_a(a12_19to12_20), .in_b(b11_20to12_20), .out_a(a12_20to12_21), .out_b(b12_20to13_20), .out_c(matrixC12_20)); +processing_element pe12_21(.reset(effective_rst), .clk(clk), .in_a(a12_20to12_21), .in_b(b11_21to12_21), .out_a(a12_21to12_22), .out_b(b12_21to13_21), .out_c(matrixC12_21)); +processing_element pe12_22(.reset(effective_rst), .clk(clk), .in_a(a12_21to12_22), .in_b(b11_22to12_22), .out_a(a12_22to12_23), .out_b(b12_22to13_22), .out_c(matrixC12_22)); +processing_element pe12_23(.reset(effective_rst), .clk(clk), .in_a(a12_22to12_23), .in_b(b11_23to12_23), .out_a(a12_23to12_24), .out_b(b12_23to13_23), .out_c(matrixC12_23)); +processing_element pe12_24(.reset(effective_rst), .clk(clk), .in_a(a12_23to12_24), .in_b(b11_24to12_24), .out_a(a12_24to12_25), .out_b(b12_24to13_24), .out_c(matrixC12_24)); +processing_element pe12_25(.reset(effective_rst), .clk(clk), .in_a(a12_24to12_25), .in_b(b11_25to12_25), .out_a(a12_25to12_26), .out_b(b12_25to13_25), .out_c(matrixC12_25)); +processing_element pe12_26(.reset(effective_rst), .clk(clk), .in_a(a12_25to12_26), .in_b(b11_26to12_26), .out_a(a12_26to12_27), .out_b(b12_26to13_26), .out_c(matrixC12_26)); +processing_element pe12_27(.reset(effective_rst), .clk(clk), .in_a(a12_26to12_27), .in_b(b11_27to12_27), .out_a(a12_27to12_28), .out_b(b12_27to13_27), .out_c(matrixC12_27)); +processing_element pe12_28(.reset(effective_rst), .clk(clk), .in_a(a12_27to12_28), .in_b(b11_28to12_28), .out_a(a12_28to12_29), .out_b(b12_28to13_28), .out_c(matrixC12_28)); +processing_element pe12_29(.reset(effective_rst), .clk(clk), .in_a(a12_28to12_29), .in_b(b11_29to12_29), .out_a(a12_29to12_30), .out_b(b12_29to13_29), .out_c(matrixC12_29)); +processing_element pe12_30(.reset(effective_rst), .clk(clk), .in_a(a12_29to12_30), .in_b(b11_30to12_30), .out_a(a12_30to12_31), .out_b(b12_30to13_30), .out_c(matrixC12_30)); +processing_element pe12_31(.reset(effective_rst), .clk(clk), .in_a(a12_30to12_31), .in_b(b11_31to12_31), .out_a(a12_31to12_32), .out_b(b12_31to13_31), .out_c(matrixC12_31)); +processing_element pe13_1(.reset(effective_rst), .clk(clk), .in_a(a13_0to13_1), .in_b(b12_1to13_1), .out_a(a13_1to13_2), .out_b(b13_1to14_1), .out_c(matrixC13_1)); +processing_element pe13_2(.reset(effective_rst), .clk(clk), .in_a(a13_1to13_2), .in_b(b12_2to13_2), .out_a(a13_2to13_3), .out_b(b13_2to14_2), .out_c(matrixC13_2)); +processing_element pe13_3(.reset(effective_rst), .clk(clk), .in_a(a13_2to13_3), .in_b(b12_3to13_3), .out_a(a13_3to13_4), .out_b(b13_3to14_3), .out_c(matrixC13_3)); +processing_element pe13_4(.reset(effective_rst), .clk(clk), .in_a(a13_3to13_4), .in_b(b12_4to13_4), .out_a(a13_4to13_5), .out_b(b13_4to14_4), .out_c(matrixC13_4)); +processing_element pe13_5(.reset(effective_rst), .clk(clk), .in_a(a13_4to13_5), .in_b(b12_5to13_5), .out_a(a13_5to13_6), .out_b(b13_5to14_5), .out_c(matrixC13_5)); +processing_element pe13_6(.reset(effective_rst), .clk(clk), .in_a(a13_5to13_6), .in_b(b12_6to13_6), .out_a(a13_6to13_7), .out_b(b13_6to14_6), .out_c(matrixC13_6)); +processing_element pe13_7(.reset(effective_rst), .clk(clk), .in_a(a13_6to13_7), .in_b(b12_7to13_7), .out_a(a13_7to13_8), .out_b(b13_7to14_7), .out_c(matrixC13_7)); +processing_element pe13_8(.reset(effective_rst), .clk(clk), .in_a(a13_7to13_8), .in_b(b12_8to13_8), .out_a(a13_8to13_9), .out_b(b13_8to14_8), .out_c(matrixC13_8)); +processing_element pe13_9(.reset(effective_rst), .clk(clk), .in_a(a13_8to13_9), .in_b(b12_9to13_9), .out_a(a13_9to13_10), .out_b(b13_9to14_9), .out_c(matrixC13_9)); +processing_element pe13_10(.reset(effective_rst), .clk(clk), .in_a(a13_9to13_10), .in_b(b12_10to13_10), .out_a(a13_10to13_11), .out_b(b13_10to14_10), .out_c(matrixC13_10)); +processing_element pe13_11(.reset(effective_rst), .clk(clk), .in_a(a13_10to13_11), .in_b(b12_11to13_11), .out_a(a13_11to13_12), .out_b(b13_11to14_11), .out_c(matrixC13_11)); +processing_element pe13_12(.reset(effective_rst), .clk(clk), .in_a(a13_11to13_12), .in_b(b12_12to13_12), .out_a(a13_12to13_13), .out_b(b13_12to14_12), .out_c(matrixC13_12)); +processing_element pe13_13(.reset(effective_rst), .clk(clk), .in_a(a13_12to13_13), .in_b(b12_13to13_13), .out_a(a13_13to13_14), .out_b(b13_13to14_13), .out_c(matrixC13_13)); +processing_element pe13_14(.reset(effective_rst), .clk(clk), .in_a(a13_13to13_14), .in_b(b12_14to13_14), .out_a(a13_14to13_15), .out_b(b13_14to14_14), .out_c(matrixC13_14)); +processing_element pe13_15(.reset(effective_rst), .clk(clk), .in_a(a13_14to13_15), .in_b(b12_15to13_15), .out_a(a13_15to13_16), .out_b(b13_15to14_15), .out_c(matrixC13_15)); +processing_element pe13_16(.reset(effective_rst), .clk(clk), .in_a(a13_15to13_16), .in_b(b12_16to13_16), .out_a(a13_16to13_17), .out_b(b13_16to14_16), .out_c(matrixC13_16)); +processing_element pe13_17(.reset(effective_rst), .clk(clk), .in_a(a13_16to13_17), .in_b(b12_17to13_17), .out_a(a13_17to13_18), .out_b(b13_17to14_17), .out_c(matrixC13_17)); +processing_element pe13_18(.reset(effective_rst), .clk(clk), .in_a(a13_17to13_18), .in_b(b12_18to13_18), .out_a(a13_18to13_19), .out_b(b13_18to14_18), .out_c(matrixC13_18)); +processing_element pe13_19(.reset(effective_rst), .clk(clk), .in_a(a13_18to13_19), .in_b(b12_19to13_19), .out_a(a13_19to13_20), .out_b(b13_19to14_19), .out_c(matrixC13_19)); +processing_element pe13_20(.reset(effective_rst), .clk(clk), .in_a(a13_19to13_20), .in_b(b12_20to13_20), .out_a(a13_20to13_21), .out_b(b13_20to14_20), .out_c(matrixC13_20)); +processing_element pe13_21(.reset(effective_rst), .clk(clk), .in_a(a13_20to13_21), .in_b(b12_21to13_21), .out_a(a13_21to13_22), .out_b(b13_21to14_21), .out_c(matrixC13_21)); +processing_element pe13_22(.reset(effective_rst), .clk(clk), .in_a(a13_21to13_22), .in_b(b12_22to13_22), .out_a(a13_22to13_23), .out_b(b13_22to14_22), .out_c(matrixC13_22)); +processing_element pe13_23(.reset(effective_rst), .clk(clk), .in_a(a13_22to13_23), .in_b(b12_23to13_23), .out_a(a13_23to13_24), .out_b(b13_23to14_23), .out_c(matrixC13_23)); +processing_element pe13_24(.reset(effective_rst), .clk(clk), .in_a(a13_23to13_24), .in_b(b12_24to13_24), .out_a(a13_24to13_25), .out_b(b13_24to14_24), .out_c(matrixC13_24)); +processing_element pe13_25(.reset(effective_rst), .clk(clk), .in_a(a13_24to13_25), .in_b(b12_25to13_25), .out_a(a13_25to13_26), .out_b(b13_25to14_25), .out_c(matrixC13_25)); +processing_element pe13_26(.reset(effective_rst), .clk(clk), .in_a(a13_25to13_26), .in_b(b12_26to13_26), .out_a(a13_26to13_27), .out_b(b13_26to14_26), .out_c(matrixC13_26)); +processing_element pe13_27(.reset(effective_rst), .clk(clk), .in_a(a13_26to13_27), .in_b(b12_27to13_27), .out_a(a13_27to13_28), .out_b(b13_27to14_27), .out_c(matrixC13_27)); +processing_element pe13_28(.reset(effective_rst), .clk(clk), .in_a(a13_27to13_28), .in_b(b12_28to13_28), .out_a(a13_28to13_29), .out_b(b13_28to14_28), .out_c(matrixC13_28)); +processing_element pe13_29(.reset(effective_rst), .clk(clk), .in_a(a13_28to13_29), .in_b(b12_29to13_29), .out_a(a13_29to13_30), .out_b(b13_29to14_29), .out_c(matrixC13_29)); +processing_element pe13_30(.reset(effective_rst), .clk(clk), .in_a(a13_29to13_30), .in_b(b12_30to13_30), .out_a(a13_30to13_31), .out_b(b13_30to14_30), .out_c(matrixC13_30)); +processing_element pe13_31(.reset(effective_rst), .clk(clk), .in_a(a13_30to13_31), .in_b(b12_31to13_31), .out_a(a13_31to13_32), .out_b(b13_31to14_31), .out_c(matrixC13_31)); +processing_element pe14_1(.reset(effective_rst), .clk(clk), .in_a(a14_0to14_1), .in_b(b13_1to14_1), .out_a(a14_1to14_2), .out_b(b14_1to15_1), .out_c(matrixC14_1)); +processing_element pe14_2(.reset(effective_rst), .clk(clk), .in_a(a14_1to14_2), .in_b(b13_2to14_2), .out_a(a14_2to14_3), .out_b(b14_2to15_2), .out_c(matrixC14_2)); +processing_element pe14_3(.reset(effective_rst), .clk(clk), .in_a(a14_2to14_3), .in_b(b13_3to14_3), .out_a(a14_3to14_4), .out_b(b14_3to15_3), .out_c(matrixC14_3)); +processing_element pe14_4(.reset(effective_rst), .clk(clk), .in_a(a14_3to14_4), .in_b(b13_4to14_4), .out_a(a14_4to14_5), .out_b(b14_4to15_4), .out_c(matrixC14_4)); +processing_element pe14_5(.reset(effective_rst), .clk(clk), .in_a(a14_4to14_5), .in_b(b13_5to14_5), .out_a(a14_5to14_6), .out_b(b14_5to15_5), .out_c(matrixC14_5)); +processing_element pe14_6(.reset(effective_rst), .clk(clk), .in_a(a14_5to14_6), .in_b(b13_6to14_6), .out_a(a14_6to14_7), .out_b(b14_6to15_6), .out_c(matrixC14_6)); +processing_element pe14_7(.reset(effective_rst), .clk(clk), .in_a(a14_6to14_7), .in_b(b13_7to14_7), .out_a(a14_7to14_8), .out_b(b14_7to15_7), .out_c(matrixC14_7)); +processing_element pe14_8(.reset(effective_rst), .clk(clk), .in_a(a14_7to14_8), .in_b(b13_8to14_8), .out_a(a14_8to14_9), .out_b(b14_8to15_8), .out_c(matrixC14_8)); +processing_element pe14_9(.reset(effective_rst), .clk(clk), .in_a(a14_8to14_9), .in_b(b13_9to14_9), .out_a(a14_9to14_10), .out_b(b14_9to15_9), .out_c(matrixC14_9)); +processing_element pe14_10(.reset(effective_rst), .clk(clk), .in_a(a14_9to14_10), .in_b(b13_10to14_10), .out_a(a14_10to14_11), .out_b(b14_10to15_10), .out_c(matrixC14_10)); +processing_element pe14_11(.reset(effective_rst), .clk(clk), .in_a(a14_10to14_11), .in_b(b13_11to14_11), .out_a(a14_11to14_12), .out_b(b14_11to15_11), .out_c(matrixC14_11)); +processing_element pe14_12(.reset(effective_rst), .clk(clk), .in_a(a14_11to14_12), .in_b(b13_12to14_12), .out_a(a14_12to14_13), .out_b(b14_12to15_12), .out_c(matrixC14_12)); +processing_element pe14_13(.reset(effective_rst), .clk(clk), .in_a(a14_12to14_13), .in_b(b13_13to14_13), .out_a(a14_13to14_14), .out_b(b14_13to15_13), .out_c(matrixC14_13)); +processing_element pe14_14(.reset(effective_rst), .clk(clk), .in_a(a14_13to14_14), .in_b(b13_14to14_14), .out_a(a14_14to14_15), .out_b(b14_14to15_14), .out_c(matrixC14_14)); +processing_element pe14_15(.reset(effective_rst), .clk(clk), .in_a(a14_14to14_15), .in_b(b13_15to14_15), .out_a(a14_15to14_16), .out_b(b14_15to15_15), .out_c(matrixC14_15)); +processing_element pe14_16(.reset(effective_rst), .clk(clk), .in_a(a14_15to14_16), .in_b(b13_16to14_16), .out_a(a14_16to14_17), .out_b(b14_16to15_16), .out_c(matrixC14_16)); +processing_element pe14_17(.reset(effective_rst), .clk(clk), .in_a(a14_16to14_17), .in_b(b13_17to14_17), .out_a(a14_17to14_18), .out_b(b14_17to15_17), .out_c(matrixC14_17)); +processing_element pe14_18(.reset(effective_rst), .clk(clk), .in_a(a14_17to14_18), .in_b(b13_18to14_18), .out_a(a14_18to14_19), .out_b(b14_18to15_18), .out_c(matrixC14_18)); +processing_element pe14_19(.reset(effective_rst), .clk(clk), .in_a(a14_18to14_19), .in_b(b13_19to14_19), .out_a(a14_19to14_20), .out_b(b14_19to15_19), .out_c(matrixC14_19)); +processing_element pe14_20(.reset(effective_rst), .clk(clk), .in_a(a14_19to14_20), .in_b(b13_20to14_20), .out_a(a14_20to14_21), .out_b(b14_20to15_20), .out_c(matrixC14_20)); +processing_element pe14_21(.reset(effective_rst), .clk(clk), .in_a(a14_20to14_21), .in_b(b13_21to14_21), .out_a(a14_21to14_22), .out_b(b14_21to15_21), .out_c(matrixC14_21)); +processing_element pe14_22(.reset(effective_rst), .clk(clk), .in_a(a14_21to14_22), .in_b(b13_22to14_22), .out_a(a14_22to14_23), .out_b(b14_22to15_22), .out_c(matrixC14_22)); +processing_element pe14_23(.reset(effective_rst), .clk(clk), .in_a(a14_22to14_23), .in_b(b13_23to14_23), .out_a(a14_23to14_24), .out_b(b14_23to15_23), .out_c(matrixC14_23)); +processing_element pe14_24(.reset(effective_rst), .clk(clk), .in_a(a14_23to14_24), .in_b(b13_24to14_24), .out_a(a14_24to14_25), .out_b(b14_24to15_24), .out_c(matrixC14_24)); +processing_element pe14_25(.reset(effective_rst), .clk(clk), .in_a(a14_24to14_25), .in_b(b13_25to14_25), .out_a(a14_25to14_26), .out_b(b14_25to15_25), .out_c(matrixC14_25)); +processing_element pe14_26(.reset(effective_rst), .clk(clk), .in_a(a14_25to14_26), .in_b(b13_26to14_26), .out_a(a14_26to14_27), .out_b(b14_26to15_26), .out_c(matrixC14_26)); +processing_element pe14_27(.reset(effective_rst), .clk(clk), .in_a(a14_26to14_27), .in_b(b13_27to14_27), .out_a(a14_27to14_28), .out_b(b14_27to15_27), .out_c(matrixC14_27)); +processing_element pe14_28(.reset(effective_rst), .clk(clk), .in_a(a14_27to14_28), .in_b(b13_28to14_28), .out_a(a14_28to14_29), .out_b(b14_28to15_28), .out_c(matrixC14_28)); +processing_element pe14_29(.reset(effective_rst), .clk(clk), .in_a(a14_28to14_29), .in_b(b13_29to14_29), .out_a(a14_29to14_30), .out_b(b14_29to15_29), .out_c(matrixC14_29)); +processing_element pe14_30(.reset(effective_rst), .clk(clk), .in_a(a14_29to14_30), .in_b(b13_30to14_30), .out_a(a14_30to14_31), .out_b(b14_30to15_30), .out_c(matrixC14_30)); +processing_element pe14_31(.reset(effective_rst), .clk(clk), .in_a(a14_30to14_31), .in_b(b13_31to14_31), .out_a(a14_31to14_32), .out_b(b14_31to15_31), .out_c(matrixC14_31)); +processing_element pe15_1(.reset(effective_rst), .clk(clk), .in_a(a15_0to15_1), .in_b(b14_1to15_1), .out_a(a15_1to15_2), .out_b(b15_1to16_1), .out_c(matrixC15_1)); +processing_element pe15_2(.reset(effective_rst), .clk(clk), .in_a(a15_1to15_2), .in_b(b14_2to15_2), .out_a(a15_2to15_3), .out_b(b15_2to16_2), .out_c(matrixC15_2)); +processing_element pe15_3(.reset(effective_rst), .clk(clk), .in_a(a15_2to15_3), .in_b(b14_3to15_3), .out_a(a15_3to15_4), .out_b(b15_3to16_3), .out_c(matrixC15_3)); +processing_element pe15_4(.reset(effective_rst), .clk(clk), .in_a(a15_3to15_4), .in_b(b14_4to15_4), .out_a(a15_4to15_5), .out_b(b15_4to16_4), .out_c(matrixC15_4)); +processing_element pe15_5(.reset(effective_rst), .clk(clk), .in_a(a15_4to15_5), .in_b(b14_5to15_5), .out_a(a15_5to15_6), .out_b(b15_5to16_5), .out_c(matrixC15_5)); +processing_element pe15_6(.reset(effective_rst), .clk(clk), .in_a(a15_5to15_6), .in_b(b14_6to15_6), .out_a(a15_6to15_7), .out_b(b15_6to16_6), .out_c(matrixC15_6)); +processing_element pe15_7(.reset(effective_rst), .clk(clk), .in_a(a15_6to15_7), .in_b(b14_7to15_7), .out_a(a15_7to15_8), .out_b(b15_7to16_7), .out_c(matrixC15_7)); +processing_element pe15_8(.reset(effective_rst), .clk(clk), .in_a(a15_7to15_8), .in_b(b14_8to15_8), .out_a(a15_8to15_9), .out_b(b15_8to16_8), .out_c(matrixC15_8)); +processing_element pe15_9(.reset(effective_rst), .clk(clk), .in_a(a15_8to15_9), .in_b(b14_9to15_9), .out_a(a15_9to15_10), .out_b(b15_9to16_9), .out_c(matrixC15_9)); +processing_element pe15_10(.reset(effective_rst), .clk(clk), .in_a(a15_9to15_10), .in_b(b14_10to15_10), .out_a(a15_10to15_11), .out_b(b15_10to16_10), .out_c(matrixC15_10)); +processing_element pe15_11(.reset(effective_rst), .clk(clk), .in_a(a15_10to15_11), .in_b(b14_11to15_11), .out_a(a15_11to15_12), .out_b(b15_11to16_11), .out_c(matrixC15_11)); +processing_element pe15_12(.reset(effective_rst), .clk(clk), .in_a(a15_11to15_12), .in_b(b14_12to15_12), .out_a(a15_12to15_13), .out_b(b15_12to16_12), .out_c(matrixC15_12)); +processing_element pe15_13(.reset(effective_rst), .clk(clk), .in_a(a15_12to15_13), .in_b(b14_13to15_13), .out_a(a15_13to15_14), .out_b(b15_13to16_13), .out_c(matrixC15_13)); +processing_element pe15_14(.reset(effective_rst), .clk(clk), .in_a(a15_13to15_14), .in_b(b14_14to15_14), .out_a(a15_14to15_15), .out_b(b15_14to16_14), .out_c(matrixC15_14)); +processing_element pe15_15(.reset(effective_rst), .clk(clk), .in_a(a15_14to15_15), .in_b(b14_15to15_15), .out_a(a15_15to15_16), .out_b(b15_15to16_15), .out_c(matrixC15_15)); +processing_element pe15_16(.reset(effective_rst), .clk(clk), .in_a(a15_15to15_16), .in_b(b14_16to15_16), .out_a(a15_16to15_17), .out_b(b15_16to16_16), .out_c(matrixC15_16)); +processing_element pe15_17(.reset(effective_rst), .clk(clk), .in_a(a15_16to15_17), .in_b(b14_17to15_17), .out_a(a15_17to15_18), .out_b(b15_17to16_17), .out_c(matrixC15_17)); +processing_element pe15_18(.reset(effective_rst), .clk(clk), .in_a(a15_17to15_18), .in_b(b14_18to15_18), .out_a(a15_18to15_19), .out_b(b15_18to16_18), .out_c(matrixC15_18)); +processing_element pe15_19(.reset(effective_rst), .clk(clk), .in_a(a15_18to15_19), .in_b(b14_19to15_19), .out_a(a15_19to15_20), .out_b(b15_19to16_19), .out_c(matrixC15_19)); +processing_element pe15_20(.reset(effective_rst), .clk(clk), .in_a(a15_19to15_20), .in_b(b14_20to15_20), .out_a(a15_20to15_21), .out_b(b15_20to16_20), .out_c(matrixC15_20)); +processing_element pe15_21(.reset(effective_rst), .clk(clk), .in_a(a15_20to15_21), .in_b(b14_21to15_21), .out_a(a15_21to15_22), .out_b(b15_21to16_21), .out_c(matrixC15_21)); +processing_element pe15_22(.reset(effective_rst), .clk(clk), .in_a(a15_21to15_22), .in_b(b14_22to15_22), .out_a(a15_22to15_23), .out_b(b15_22to16_22), .out_c(matrixC15_22)); +processing_element pe15_23(.reset(effective_rst), .clk(clk), .in_a(a15_22to15_23), .in_b(b14_23to15_23), .out_a(a15_23to15_24), .out_b(b15_23to16_23), .out_c(matrixC15_23)); +processing_element pe15_24(.reset(effective_rst), .clk(clk), .in_a(a15_23to15_24), .in_b(b14_24to15_24), .out_a(a15_24to15_25), .out_b(b15_24to16_24), .out_c(matrixC15_24)); +processing_element pe15_25(.reset(effective_rst), .clk(clk), .in_a(a15_24to15_25), .in_b(b14_25to15_25), .out_a(a15_25to15_26), .out_b(b15_25to16_25), .out_c(matrixC15_25)); +processing_element pe15_26(.reset(effective_rst), .clk(clk), .in_a(a15_25to15_26), .in_b(b14_26to15_26), .out_a(a15_26to15_27), .out_b(b15_26to16_26), .out_c(matrixC15_26)); +processing_element pe15_27(.reset(effective_rst), .clk(clk), .in_a(a15_26to15_27), .in_b(b14_27to15_27), .out_a(a15_27to15_28), .out_b(b15_27to16_27), .out_c(matrixC15_27)); +processing_element pe15_28(.reset(effective_rst), .clk(clk), .in_a(a15_27to15_28), .in_b(b14_28to15_28), .out_a(a15_28to15_29), .out_b(b15_28to16_28), .out_c(matrixC15_28)); +processing_element pe15_29(.reset(effective_rst), .clk(clk), .in_a(a15_28to15_29), .in_b(b14_29to15_29), .out_a(a15_29to15_30), .out_b(b15_29to16_29), .out_c(matrixC15_29)); +processing_element pe15_30(.reset(effective_rst), .clk(clk), .in_a(a15_29to15_30), .in_b(b14_30to15_30), .out_a(a15_30to15_31), .out_b(b15_30to16_30), .out_c(matrixC15_30)); +processing_element pe15_31(.reset(effective_rst), .clk(clk), .in_a(a15_30to15_31), .in_b(b14_31to15_31), .out_a(a15_31to15_32), .out_b(b15_31to16_31), .out_c(matrixC15_31)); +processing_element pe16_1(.reset(effective_rst), .clk(clk), .in_a(a16_0to16_1), .in_b(b15_1to16_1), .out_a(a16_1to16_2), .out_b(b16_1to17_1), .out_c(matrixC16_1)); +processing_element pe16_2(.reset(effective_rst), .clk(clk), .in_a(a16_1to16_2), .in_b(b15_2to16_2), .out_a(a16_2to16_3), .out_b(b16_2to17_2), .out_c(matrixC16_2)); +processing_element pe16_3(.reset(effective_rst), .clk(clk), .in_a(a16_2to16_3), .in_b(b15_3to16_3), .out_a(a16_3to16_4), .out_b(b16_3to17_3), .out_c(matrixC16_3)); +processing_element pe16_4(.reset(effective_rst), .clk(clk), .in_a(a16_3to16_4), .in_b(b15_4to16_4), .out_a(a16_4to16_5), .out_b(b16_4to17_4), .out_c(matrixC16_4)); +processing_element pe16_5(.reset(effective_rst), .clk(clk), .in_a(a16_4to16_5), .in_b(b15_5to16_5), .out_a(a16_5to16_6), .out_b(b16_5to17_5), .out_c(matrixC16_5)); +processing_element pe16_6(.reset(effective_rst), .clk(clk), .in_a(a16_5to16_6), .in_b(b15_6to16_6), .out_a(a16_6to16_7), .out_b(b16_6to17_6), .out_c(matrixC16_6)); +processing_element pe16_7(.reset(effective_rst), .clk(clk), .in_a(a16_6to16_7), .in_b(b15_7to16_7), .out_a(a16_7to16_8), .out_b(b16_7to17_7), .out_c(matrixC16_7)); +processing_element pe16_8(.reset(effective_rst), .clk(clk), .in_a(a16_7to16_8), .in_b(b15_8to16_8), .out_a(a16_8to16_9), .out_b(b16_8to17_8), .out_c(matrixC16_8)); +processing_element pe16_9(.reset(effective_rst), .clk(clk), .in_a(a16_8to16_9), .in_b(b15_9to16_9), .out_a(a16_9to16_10), .out_b(b16_9to17_9), .out_c(matrixC16_9)); +processing_element pe16_10(.reset(effective_rst), .clk(clk), .in_a(a16_9to16_10), .in_b(b15_10to16_10), .out_a(a16_10to16_11), .out_b(b16_10to17_10), .out_c(matrixC16_10)); +processing_element pe16_11(.reset(effective_rst), .clk(clk), .in_a(a16_10to16_11), .in_b(b15_11to16_11), .out_a(a16_11to16_12), .out_b(b16_11to17_11), .out_c(matrixC16_11)); +processing_element pe16_12(.reset(effective_rst), .clk(clk), .in_a(a16_11to16_12), .in_b(b15_12to16_12), .out_a(a16_12to16_13), .out_b(b16_12to17_12), .out_c(matrixC16_12)); +processing_element pe16_13(.reset(effective_rst), .clk(clk), .in_a(a16_12to16_13), .in_b(b15_13to16_13), .out_a(a16_13to16_14), .out_b(b16_13to17_13), .out_c(matrixC16_13)); +processing_element pe16_14(.reset(effective_rst), .clk(clk), .in_a(a16_13to16_14), .in_b(b15_14to16_14), .out_a(a16_14to16_15), .out_b(b16_14to17_14), .out_c(matrixC16_14)); +processing_element pe16_15(.reset(effective_rst), .clk(clk), .in_a(a16_14to16_15), .in_b(b15_15to16_15), .out_a(a16_15to16_16), .out_b(b16_15to17_15), .out_c(matrixC16_15)); +processing_element pe16_16(.reset(effective_rst), .clk(clk), .in_a(a16_15to16_16), .in_b(b15_16to16_16), .out_a(a16_16to16_17), .out_b(b16_16to17_16), .out_c(matrixC16_16)); +processing_element pe16_17(.reset(effective_rst), .clk(clk), .in_a(a16_16to16_17), .in_b(b15_17to16_17), .out_a(a16_17to16_18), .out_b(b16_17to17_17), .out_c(matrixC16_17)); +processing_element pe16_18(.reset(effective_rst), .clk(clk), .in_a(a16_17to16_18), .in_b(b15_18to16_18), .out_a(a16_18to16_19), .out_b(b16_18to17_18), .out_c(matrixC16_18)); +processing_element pe16_19(.reset(effective_rst), .clk(clk), .in_a(a16_18to16_19), .in_b(b15_19to16_19), .out_a(a16_19to16_20), .out_b(b16_19to17_19), .out_c(matrixC16_19)); +processing_element pe16_20(.reset(effective_rst), .clk(clk), .in_a(a16_19to16_20), .in_b(b15_20to16_20), .out_a(a16_20to16_21), .out_b(b16_20to17_20), .out_c(matrixC16_20)); +processing_element pe16_21(.reset(effective_rst), .clk(clk), .in_a(a16_20to16_21), .in_b(b15_21to16_21), .out_a(a16_21to16_22), .out_b(b16_21to17_21), .out_c(matrixC16_21)); +processing_element pe16_22(.reset(effective_rst), .clk(clk), .in_a(a16_21to16_22), .in_b(b15_22to16_22), .out_a(a16_22to16_23), .out_b(b16_22to17_22), .out_c(matrixC16_22)); +processing_element pe16_23(.reset(effective_rst), .clk(clk), .in_a(a16_22to16_23), .in_b(b15_23to16_23), .out_a(a16_23to16_24), .out_b(b16_23to17_23), .out_c(matrixC16_23)); +processing_element pe16_24(.reset(effective_rst), .clk(clk), .in_a(a16_23to16_24), .in_b(b15_24to16_24), .out_a(a16_24to16_25), .out_b(b16_24to17_24), .out_c(matrixC16_24)); +processing_element pe16_25(.reset(effective_rst), .clk(clk), .in_a(a16_24to16_25), .in_b(b15_25to16_25), .out_a(a16_25to16_26), .out_b(b16_25to17_25), .out_c(matrixC16_25)); +processing_element pe16_26(.reset(effective_rst), .clk(clk), .in_a(a16_25to16_26), .in_b(b15_26to16_26), .out_a(a16_26to16_27), .out_b(b16_26to17_26), .out_c(matrixC16_26)); +processing_element pe16_27(.reset(effective_rst), .clk(clk), .in_a(a16_26to16_27), .in_b(b15_27to16_27), .out_a(a16_27to16_28), .out_b(b16_27to17_27), .out_c(matrixC16_27)); +processing_element pe16_28(.reset(effective_rst), .clk(clk), .in_a(a16_27to16_28), .in_b(b15_28to16_28), .out_a(a16_28to16_29), .out_b(b16_28to17_28), .out_c(matrixC16_28)); +processing_element pe16_29(.reset(effective_rst), .clk(clk), .in_a(a16_28to16_29), .in_b(b15_29to16_29), .out_a(a16_29to16_30), .out_b(b16_29to17_29), .out_c(matrixC16_29)); +processing_element pe16_30(.reset(effective_rst), .clk(clk), .in_a(a16_29to16_30), .in_b(b15_30to16_30), .out_a(a16_30to16_31), .out_b(b16_30to17_30), .out_c(matrixC16_30)); +processing_element pe16_31(.reset(effective_rst), .clk(clk), .in_a(a16_30to16_31), .in_b(b15_31to16_31), .out_a(a16_31to16_32), .out_b(b16_31to17_31), .out_c(matrixC16_31)); +processing_element pe17_1(.reset(effective_rst), .clk(clk), .in_a(a17_0to17_1), .in_b(b16_1to17_1), .out_a(a17_1to17_2), .out_b(b17_1to18_1), .out_c(matrixC17_1)); +processing_element pe17_2(.reset(effective_rst), .clk(clk), .in_a(a17_1to17_2), .in_b(b16_2to17_2), .out_a(a17_2to17_3), .out_b(b17_2to18_2), .out_c(matrixC17_2)); +processing_element pe17_3(.reset(effective_rst), .clk(clk), .in_a(a17_2to17_3), .in_b(b16_3to17_3), .out_a(a17_3to17_4), .out_b(b17_3to18_3), .out_c(matrixC17_3)); +processing_element pe17_4(.reset(effective_rst), .clk(clk), .in_a(a17_3to17_4), .in_b(b16_4to17_4), .out_a(a17_4to17_5), .out_b(b17_4to18_4), .out_c(matrixC17_4)); +processing_element pe17_5(.reset(effective_rst), .clk(clk), .in_a(a17_4to17_5), .in_b(b16_5to17_5), .out_a(a17_5to17_6), .out_b(b17_5to18_5), .out_c(matrixC17_5)); +processing_element pe17_6(.reset(effective_rst), .clk(clk), .in_a(a17_5to17_6), .in_b(b16_6to17_6), .out_a(a17_6to17_7), .out_b(b17_6to18_6), .out_c(matrixC17_6)); +processing_element pe17_7(.reset(effective_rst), .clk(clk), .in_a(a17_6to17_7), .in_b(b16_7to17_7), .out_a(a17_7to17_8), .out_b(b17_7to18_7), .out_c(matrixC17_7)); +processing_element pe17_8(.reset(effective_rst), .clk(clk), .in_a(a17_7to17_8), .in_b(b16_8to17_8), .out_a(a17_8to17_9), .out_b(b17_8to18_8), .out_c(matrixC17_8)); +processing_element pe17_9(.reset(effective_rst), .clk(clk), .in_a(a17_8to17_9), .in_b(b16_9to17_9), .out_a(a17_9to17_10), .out_b(b17_9to18_9), .out_c(matrixC17_9)); +processing_element pe17_10(.reset(effective_rst), .clk(clk), .in_a(a17_9to17_10), .in_b(b16_10to17_10), .out_a(a17_10to17_11), .out_b(b17_10to18_10), .out_c(matrixC17_10)); +processing_element pe17_11(.reset(effective_rst), .clk(clk), .in_a(a17_10to17_11), .in_b(b16_11to17_11), .out_a(a17_11to17_12), .out_b(b17_11to18_11), .out_c(matrixC17_11)); +processing_element pe17_12(.reset(effective_rst), .clk(clk), .in_a(a17_11to17_12), .in_b(b16_12to17_12), .out_a(a17_12to17_13), .out_b(b17_12to18_12), .out_c(matrixC17_12)); +processing_element pe17_13(.reset(effective_rst), .clk(clk), .in_a(a17_12to17_13), .in_b(b16_13to17_13), .out_a(a17_13to17_14), .out_b(b17_13to18_13), .out_c(matrixC17_13)); +processing_element pe17_14(.reset(effective_rst), .clk(clk), .in_a(a17_13to17_14), .in_b(b16_14to17_14), .out_a(a17_14to17_15), .out_b(b17_14to18_14), .out_c(matrixC17_14)); +processing_element pe17_15(.reset(effective_rst), .clk(clk), .in_a(a17_14to17_15), .in_b(b16_15to17_15), .out_a(a17_15to17_16), .out_b(b17_15to18_15), .out_c(matrixC17_15)); +processing_element pe17_16(.reset(effective_rst), .clk(clk), .in_a(a17_15to17_16), .in_b(b16_16to17_16), .out_a(a17_16to17_17), .out_b(b17_16to18_16), .out_c(matrixC17_16)); +processing_element pe17_17(.reset(effective_rst), .clk(clk), .in_a(a17_16to17_17), .in_b(b16_17to17_17), .out_a(a17_17to17_18), .out_b(b17_17to18_17), .out_c(matrixC17_17)); +processing_element pe17_18(.reset(effective_rst), .clk(clk), .in_a(a17_17to17_18), .in_b(b16_18to17_18), .out_a(a17_18to17_19), .out_b(b17_18to18_18), .out_c(matrixC17_18)); +processing_element pe17_19(.reset(effective_rst), .clk(clk), .in_a(a17_18to17_19), .in_b(b16_19to17_19), .out_a(a17_19to17_20), .out_b(b17_19to18_19), .out_c(matrixC17_19)); +processing_element pe17_20(.reset(effective_rst), .clk(clk), .in_a(a17_19to17_20), .in_b(b16_20to17_20), .out_a(a17_20to17_21), .out_b(b17_20to18_20), .out_c(matrixC17_20)); +processing_element pe17_21(.reset(effective_rst), .clk(clk), .in_a(a17_20to17_21), .in_b(b16_21to17_21), .out_a(a17_21to17_22), .out_b(b17_21to18_21), .out_c(matrixC17_21)); +processing_element pe17_22(.reset(effective_rst), .clk(clk), .in_a(a17_21to17_22), .in_b(b16_22to17_22), .out_a(a17_22to17_23), .out_b(b17_22to18_22), .out_c(matrixC17_22)); +processing_element pe17_23(.reset(effective_rst), .clk(clk), .in_a(a17_22to17_23), .in_b(b16_23to17_23), .out_a(a17_23to17_24), .out_b(b17_23to18_23), .out_c(matrixC17_23)); +processing_element pe17_24(.reset(effective_rst), .clk(clk), .in_a(a17_23to17_24), .in_b(b16_24to17_24), .out_a(a17_24to17_25), .out_b(b17_24to18_24), .out_c(matrixC17_24)); +processing_element pe17_25(.reset(effective_rst), .clk(clk), .in_a(a17_24to17_25), .in_b(b16_25to17_25), .out_a(a17_25to17_26), .out_b(b17_25to18_25), .out_c(matrixC17_25)); +processing_element pe17_26(.reset(effective_rst), .clk(clk), .in_a(a17_25to17_26), .in_b(b16_26to17_26), .out_a(a17_26to17_27), .out_b(b17_26to18_26), .out_c(matrixC17_26)); +processing_element pe17_27(.reset(effective_rst), .clk(clk), .in_a(a17_26to17_27), .in_b(b16_27to17_27), .out_a(a17_27to17_28), .out_b(b17_27to18_27), .out_c(matrixC17_27)); +processing_element pe17_28(.reset(effective_rst), .clk(clk), .in_a(a17_27to17_28), .in_b(b16_28to17_28), .out_a(a17_28to17_29), .out_b(b17_28to18_28), .out_c(matrixC17_28)); +processing_element pe17_29(.reset(effective_rst), .clk(clk), .in_a(a17_28to17_29), .in_b(b16_29to17_29), .out_a(a17_29to17_30), .out_b(b17_29to18_29), .out_c(matrixC17_29)); +processing_element pe17_30(.reset(effective_rst), .clk(clk), .in_a(a17_29to17_30), .in_b(b16_30to17_30), .out_a(a17_30to17_31), .out_b(b17_30to18_30), .out_c(matrixC17_30)); +processing_element pe17_31(.reset(effective_rst), .clk(clk), .in_a(a17_30to17_31), .in_b(b16_31to17_31), .out_a(a17_31to17_32), .out_b(b17_31to18_31), .out_c(matrixC17_31)); +processing_element pe18_1(.reset(effective_rst), .clk(clk), .in_a(a18_0to18_1), .in_b(b17_1to18_1), .out_a(a18_1to18_2), .out_b(b18_1to19_1), .out_c(matrixC18_1)); +processing_element pe18_2(.reset(effective_rst), .clk(clk), .in_a(a18_1to18_2), .in_b(b17_2to18_2), .out_a(a18_2to18_3), .out_b(b18_2to19_2), .out_c(matrixC18_2)); +processing_element pe18_3(.reset(effective_rst), .clk(clk), .in_a(a18_2to18_3), .in_b(b17_3to18_3), .out_a(a18_3to18_4), .out_b(b18_3to19_3), .out_c(matrixC18_3)); +processing_element pe18_4(.reset(effective_rst), .clk(clk), .in_a(a18_3to18_4), .in_b(b17_4to18_4), .out_a(a18_4to18_5), .out_b(b18_4to19_4), .out_c(matrixC18_4)); +processing_element pe18_5(.reset(effective_rst), .clk(clk), .in_a(a18_4to18_5), .in_b(b17_5to18_5), .out_a(a18_5to18_6), .out_b(b18_5to19_5), .out_c(matrixC18_5)); +processing_element pe18_6(.reset(effective_rst), .clk(clk), .in_a(a18_5to18_6), .in_b(b17_6to18_6), .out_a(a18_6to18_7), .out_b(b18_6to19_6), .out_c(matrixC18_6)); +processing_element pe18_7(.reset(effective_rst), .clk(clk), .in_a(a18_6to18_7), .in_b(b17_7to18_7), .out_a(a18_7to18_8), .out_b(b18_7to19_7), .out_c(matrixC18_7)); +processing_element pe18_8(.reset(effective_rst), .clk(clk), .in_a(a18_7to18_8), .in_b(b17_8to18_8), .out_a(a18_8to18_9), .out_b(b18_8to19_8), .out_c(matrixC18_8)); +processing_element pe18_9(.reset(effective_rst), .clk(clk), .in_a(a18_8to18_9), .in_b(b17_9to18_9), .out_a(a18_9to18_10), .out_b(b18_9to19_9), .out_c(matrixC18_9)); +processing_element pe18_10(.reset(effective_rst), .clk(clk), .in_a(a18_9to18_10), .in_b(b17_10to18_10), .out_a(a18_10to18_11), .out_b(b18_10to19_10), .out_c(matrixC18_10)); +processing_element pe18_11(.reset(effective_rst), .clk(clk), .in_a(a18_10to18_11), .in_b(b17_11to18_11), .out_a(a18_11to18_12), .out_b(b18_11to19_11), .out_c(matrixC18_11)); +processing_element pe18_12(.reset(effective_rst), .clk(clk), .in_a(a18_11to18_12), .in_b(b17_12to18_12), .out_a(a18_12to18_13), .out_b(b18_12to19_12), .out_c(matrixC18_12)); +processing_element pe18_13(.reset(effective_rst), .clk(clk), .in_a(a18_12to18_13), .in_b(b17_13to18_13), .out_a(a18_13to18_14), .out_b(b18_13to19_13), .out_c(matrixC18_13)); +processing_element pe18_14(.reset(effective_rst), .clk(clk), .in_a(a18_13to18_14), .in_b(b17_14to18_14), .out_a(a18_14to18_15), .out_b(b18_14to19_14), .out_c(matrixC18_14)); +processing_element pe18_15(.reset(effective_rst), .clk(clk), .in_a(a18_14to18_15), .in_b(b17_15to18_15), .out_a(a18_15to18_16), .out_b(b18_15to19_15), .out_c(matrixC18_15)); +processing_element pe18_16(.reset(effective_rst), .clk(clk), .in_a(a18_15to18_16), .in_b(b17_16to18_16), .out_a(a18_16to18_17), .out_b(b18_16to19_16), .out_c(matrixC18_16)); +processing_element pe18_17(.reset(effective_rst), .clk(clk), .in_a(a18_16to18_17), .in_b(b17_17to18_17), .out_a(a18_17to18_18), .out_b(b18_17to19_17), .out_c(matrixC18_17)); +processing_element pe18_18(.reset(effective_rst), .clk(clk), .in_a(a18_17to18_18), .in_b(b17_18to18_18), .out_a(a18_18to18_19), .out_b(b18_18to19_18), .out_c(matrixC18_18)); +processing_element pe18_19(.reset(effective_rst), .clk(clk), .in_a(a18_18to18_19), .in_b(b17_19to18_19), .out_a(a18_19to18_20), .out_b(b18_19to19_19), .out_c(matrixC18_19)); +processing_element pe18_20(.reset(effective_rst), .clk(clk), .in_a(a18_19to18_20), .in_b(b17_20to18_20), .out_a(a18_20to18_21), .out_b(b18_20to19_20), .out_c(matrixC18_20)); +processing_element pe18_21(.reset(effective_rst), .clk(clk), .in_a(a18_20to18_21), .in_b(b17_21to18_21), .out_a(a18_21to18_22), .out_b(b18_21to19_21), .out_c(matrixC18_21)); +processing_element pe18_22(.reset(effective_rst), .clk(clk), .in_a(a18_21to18_22), .in_b(b17_22to18_22), .out_a(a18_22to18_23), .out_b(b18_22to19_22), .out_c(matrixC18_22)); +processing_element pe18_23(.reset(effective_rst), .clk(clk), .in_a(a18_22to18_23), .in_b(b17_23to18_23), .out_a(a18_23to18_24), .out_b(b18_23to19_23), .out_c(matrixC18_23)); +processing_element pe18_24(.reset(effective_rst), .clk(clk), .in_a(a18_23to18_24), .in_b(b17_24to18_24), .out_a(a18_24to18_25), .out_b(b18_24to19_24), .out_c(matrixC18_24)); +processing_element pe18_25(.reset(effective_rst), .clk(clk), .in_a(a18_24to18_25), .in_b(b17_25to18_25), .out_a(a18_25to18_26), .out_b(b18_25to19_25), .out_c(matrixC18_25)); +processing_element pe18_26(.reset(effective_rst), .clk(clk), .in_a(a18_25to18_26), .in_b(b17_26to18_26), .out_a(a18_26to18_27), .out_b(b18_26to19_26), .out_c(matrixC18_26)); +processing_element pe18_27(.reset(effective_rst), .clk(clk), .in_a(a18_26to18_27), .in_b(b17_27to18_27), .out_a(a18_27to18_28), .out_b(b18_27to19_27), .out_c(matrixC18_27)); +processing_element pe18_28(.reset(effective_rst), .clk(clk), .in_a(a18_27to18_28), .in_b(b17_28to18_28), .out_a(a18_28to18_29), .out_b(b18_28to19_28), .out_c(matrixC18_28)); +processing_element pe18_29(.reset(effective_rst), .clk(clk), .in_a(a18_28to18_29), .in_b(b17_29to18_29), .out_a(a18_29to18_30), .out_b(b18_29to19_29), .out_c(matrixC18_29)); +processing_element pe18_30(.reset(effective_rst), .clk(clk), .in_a(a18_29to18_30), .in_b(b17_30to18_30), .out_a(a18_30to18_31), .out_b(b18_30to19_30), .out_c(matrixC18_30)); +processing_element pe18_31(.reset(effective_rst), .clk(clk), .in_a(a18_30to18_31), .in_b(b17_31to18_31), .out_a(a18_31to18_32), .out_b(b18_31to19_31), .out_c(matrixC18_31)); +processing_element pe19_1(.reset(effective_rst), .clk(clk), .in_a(a19_0to19_1), .in_b(b18_1to19_1), .out_a(a19_1to19_2), .out_b(b19_1to20_1), .out_c(matrixC19_1)); +processing_element pe19_2(.reset(effective_rst), .clk(clk), .in_a(a19_1to19_2), .in_b(b18_2to19_2), .out_a(a19_2to19_3), .out_b(b19_2to20_2), .out_c(matrixC19_2)); +processing_element pe19_3(.reset(effective_rst), .clk(clk), .in_a(a19_2to19_3), .in_b(b18_3to19_3), .out_a(a19_3to19_4), .out_b(b19_3to20_3), .out_c(matrixC19_3)); +processing_element pe19_4(.reset(effective_rst), .clk(clk), .in_a(a19_3to19_4), .in_b(b18_4to19_4), .out_a(a19_4to19_5), .out_b(b19_4to20_4), .out_c(matrixC19_4)); +processing_element pe19_5(.reset(effective_rst), .clk(clk), .in_a(a19_4to19_5), .in_b(b18_5to19_5), .out_a(a19_5to19_6), .out_b(b19_5to20_5), .out_c(matrixC19_5)); +processing_element pe19_6(.reset(effective_rst), .clk(clk), .in_a(a19_5to19_6), .in_b(b18_6to19_6), .out_a(a19_6to19_7), .out_b(b19_6to20_6), .out_c(matrixC19_6)); +processing_element pe19_7(.reset(effective_rst), .clk(clk), .in_a(a19_6to19_7), .in_b(b18_7to19_7), .out_a(a19_7to19_8), .out_b(b19_7to20_7), .out_c(matrixC19_7)); +processing_element pe19_8(.reset(effective_rst), .clk(clk), .in_a(a19_7to19_8), .in_b(b18_8to19_8), .out_a(a19_8to19_9), .out_b(b19_8to20_8), .out_c(matrixC19_8)); +processing_element pe19_9(.reset(effective_rst), .clk(clk), .in_a(a19_8to19_9), .in_b(b18_9to19_9), .out_a(a19_9to19_10), .out_b(b19_9to20_9), .out_c(matrixC19_9)); +processing_element pe19_10(.reset(effective_rst), .clk(clk), .in_a(a19_9to19_10), .in_b(b18_10to19_10), .out_a(a19_10to19_11), .out_b(b19_10to20_10), .out_c(matrixC19_10)); +processing_element pe19_11(.reset(effective_rst), .clk(clk), .in_a(a19_10to19_11), .in_b(b18_11to19_11), .out_a(a19_11to19_12), .out_b(b19_11to20_11), .out_c(matrixC19_11)); +processing_element pe19_12(.reset(effective_rst), .clk(clk), .in_a(a19_11to19_12), .in_b(b18_12to19_12), .out_a(a19_12to19_13), .out_b(b19_12to20_12), .out_c(matrixC19_12)); +processing_element pe19_13(.reset(effective_rst), .clk(clk), .in_a(a19_12to19_13), .in_b(b18_13to19_13), .out_a(a19_13to19_14), .out_b(b19_13to20_13), .out_c(matrixC19_13)); +processing_element pe19_14(.reset(effective_rst), .clk(clk), .in_a(a19_13to19_14), .in_b(b18_14to19_14), .out_a(a19_14to19_15), .out_b(b19_14to20_14), .out_c(matrixC19_14)); +processing_element pe19_15(.reset(effective_rst), .clk(clk), .in_a(a19_14to19_15), .in_b(b18_15to19_15), .out_a(a19_15to19_16), .out_b(b19_15to20_15), .out_c(matrixC19_15)); +processing_element pe19_16(.reset(effective_rst), .clk(clk), .in_a(a19_15to19_16), .in_b(b18_16to19_16), .out_a(a19_16to19_17), .out_b(b19_16to20_16), .out_c(matrixC19_16)); +processing_element pe19_17(.reset(effective_rst), .clk(clk), .in_a(a19_16to19_17), .in_b(b18_17to19_17), .out_a(a19_17to19_18), .out_b(b19_17to20_17), .out_c(matrixC19_17)); +processing_element pe19_18(.reset(effective_rst), .clk(clk), .in_a(a19_17to19_18), .in_b(b18_18to19_18), .out_a(a19_18to19_19), .out_b(b19_18to20_18), .out_c(matrixC19_18)); +processing_element pe19_19(.reset(effective_rst), .clk(clk), .in_a(a19_18to19_19), .in_b(b18_19to19_19), .out_a(a19_19to19_20), .out_b(b19_19to20_19), .out_c(matrixC19_19)); +processing_element pe19_20(.reset(effective_rst), .clk(clk), .in_a(a19_19to19_20), .in_b(b18_20to19_20), .out_a(a19_20to19_21), .out_b(b19_20to20_20), .out_c(matrixC19_20)); +processing_element pe19_21(.reset(effective_rst), .clk(clk), .in_a(a19_20to19_21), .in_b(b18_21to19_21), .out_a(a19_21to19_22), .out_b(b19_21to20_21), .out_c(matrixC19_21)); +processing_element pe19_22(.reset(effective_rst), .clk(clk), .in_a(a19_21to19_22), .in_b(b18_22to19_22), .out_a(a19_22to19_23), .out_b(b19_22to20_22), .out_c(matrixC19_22)); +processing_element pe19_23(.reset(effective_rst), .clk(clk), .in_a(a19_22to19_23), .in_b(b18_23to19_23), .out_a(a19_23to19_24), .out_b(b19_23to20_23), .out_c(matrixC19_23)); +processing_element pe19_24(.reset(effective_rst), .clk(clk), .in_a(a19_23to19_24), .in_b(b18_24to19_24), .out_a(a19_24to19_25), .out_b(b19_24to20_24), .out_c(matrixC19_24)); +processing_element pe19_25(.reset(effective_rst), .clk(clk), .in_a(a19_24to19_25), .in_b(b18_25to19_25), .out_a(a19_25to19_26), .out_b(b19_25to20_25), .out_c(matrixC19_25)); +processing_element pe19_26(.reset(effective_rst), .clk(clk), .in_a(a19_25to19_26), .in_b(b18_26to19_26), .out_a(a19_26to19_27), .out_b(b19_26to20_26), .out_c(matrixC19_26)); +processing_element pe19_27(.reset(effective_rst), .clk(clk), .in_a(a19_26to19_27), .in_b(b18_27to19_27), .out_a(a19_27to19_28), .out_b(b19_27to20_27), .out_c(matrixC19_27)); +processing_element pe19_28(.reset(effective_rst), .clk(clk), .in_a(a19_27to19_28), .in_b(b18_28to19_28), .out_a(a19_28to19_29), .out_b(b19_28to20_28), .out_c(matrixC19_28)); +processing_element pe19_29(.reset(effective_rst), .clk(clk), .in_a(a19_28to19_29), .in_b(b18_29to19_29), .out_a(a19_29to19_30), .out_b(b19_29to20_29), .out_c(matrixC19_29)); +processing_element pe19_30(.reset(effective_rst), .clk(clk), .in_a(a19_29to19_30), .in_b(b18_30to19_30), .out_a(a19_30to19_31), .out_b(b19_30to20_30), .out_c(matrixC19_30)); +processing_element pe19_31(.reset(effective_rst), .clk(clk), .in_a(a19_30to19_31), .in_b(b18_31to19_31), .out_a(a19_31to19_32), .out_b(b19_31to20_31), .out_c(matrixC19_31)); +processing_element pe20_1(.reset(effective_rst), .clk(clk), .in_a(a20_0to20_1), .in_b(b19_1to20_1), .out_a(a20_1to20_2), .out_b(b20_1to21_1), .out_c(matrixC20_1)); +processing_element pe20_2(.reset(effective_rst), .clk(clk), .in_a(a20_1to20_2), .in_b(b19_2to20_2), .out_a(a20_2to20_3), .out_b(b20_2to21_2), .out_c(matrixC20_2)); +processing_element pe20_3(.reset(effective_rst), .clk(clk), .in_a(a20_2to20_3), .in_b(b19_3to20_3), .out_a(a20_3to20_4), .out_b(b20_3to21_3), .out_c(matrixC20_3)); +processing_element pe20_4(.reset(effective_rst), .clk(clk), .in_a(a20_3to20_4), .in_b(b19_4to20_4), .out_a(a20_4to20_5), .out_b(b20_4to21_4), .out_c(matrixC20_4)); +processing_element pe20_5(.reset(effective_rst), .clk(clk), .in_a(a20_4to20_5), .in_b(b19_5to20_5), .out_a(a20_5to20_6), .out_b(b20_5to21_5), .out_c(matrixC20_5)); +processing_element pe20_6(.reset(effective_rst), .clk(clk), .in_a(a20_5to20_6), .in_b(b19_6to20_6), .out_a(a20_6to20_7), .out_b(b20_6to21_6), .out_c(matrixC20_6)); +processing_element pe20_7(.reset(effective_rst), .clk(clk), .in_a(a20_6to20_7), .in_b(b19_7to20_7), .out_a(a20_7to20_8), .out_b(b20_7to21_7), .out_c(matrixC20_7)); +processing_element pe20_8(.reset(effective_rst), .clk(clk), .in_a(a20_7to20_8), .in_b(b19_8to20_8), .out_a(a20_8to20_9), .out_b(b20_8to21_8), .out_c(matrixC20_8)); +processing_element pe20_9(.reset(effective_rst), .clk(clk), .in_a(a20_8to20_9), .in_b(b19_9to20_9), .out_a(a20_9to20_10), .out_b(b20_9to21_9), .out_c(matrixC20_9)); +processing_element pe20_10(.reset(effective_rst), .clk(clk), .in_a(a20_9to20_10), .in_b(b19_10to20_10), .out_a(a20_10to20_11), .out_b(b20_10to21_10), .out_c(matrixC20_10)); +processing_element pe20_11(.reset(effective_rst), .clk(clk), .in_a(a20_10to20_11), .in_b(b19_11to20_11), .out_a(a20_11to20_12), .out_b(b20_11to21_11), .out_c(matrixC20_11)); +processing_element pe20_12(.reset(effective_rst), .clk(clk), .in_a(a20_11to20_12), .in_b(b19_12to20_12), .out_a(a20_12to20_13), .out_b(b20_12to21_12), .out_c(matrixC20_12)); +processing_element pe20_13(.reset(effective_rst), .clk(clk), .in_a(a20_12to20_13), .in_b(b19_13to20_13), .out_a(a20_13to20_14), .out_b(b20_13to21_13), .out_c(matrixC20_13)); +processing_element pe20_14(.reset(effective_rst), .clk(clk), .in_a(a20_13to20_14), .in_b(b19_14to20_14), .out_a(a20_14to20_15), .out_b(b20_14to21_14), .out_c(matrixC20_14)); +processing_element pe20_15(.reset(effective_rst), .clk(clk), .in_a(a20_14to20_15), .in_b(b19_15to20_15), .out_a(a20_15to20_16), .out_b(b20_15to21_15), .out_c(matrixC20_15)); +processing_element pe20_16(.reset(effective_rst), .clk(clk), .in_a(a20_15to20_16), .in_b(b19_16to20_16), .out_a(a20_16to20_17), .out_b(b20_16to21_16), .out_c(matrixC20_16)); +processing_element pe20_17(.reset(effective_rst), .clk(clk), .in_a(a20_16to20_17), .in_b(b19_17to20_17), .out_a(a20_17to20_18), .out_b(b20_17to21_17), .out_c(matrixC20_17)); +processing_element pe20_18(.reset(effective_rst), .clk(clk), .in_a(a20_17to20_18), .in_b(b19_18to20_18), .out_a(a20_18to20_19), .out_b(b20_18to21_18), .out_c(matrixC20_18)); +processing_element pe20_19(.reset(effective_rst), .clk(clk), .in_a(a20_18to20_19), .in_b(b19_19to20_19), .out_a(a20_19to20_20), .out_b(b20_19to21_19), .out_c(matrixC20_19)); +processing_element pe20_20(.reset(effective_rst), .clk(clk), .in_a(a20_19to20_20), .in_b(b19_20to20_20), .out_a(a20_20to20_21), .out_b(b20_20to21_20), .out_c(matrixC20_20)); +processing_element pe20_21(.reset(effective_rst), .clk(clk), .in_a(a20_20to20_21), .in_b(b19_21to20_21), .out_a(a20_21to20_22), .out_b(b20_21to21_21), .out_c(matrixC20_21)); +processing_element pe20_22(.reset(effective_rst), .clk(clk), .in_a(a20_21to20_22), .in_b(b19_22to20_22), .out_a(a20_22to20_23), .out_b(b20_22to21_22), .out_c(matrixC20_22)); +processing_element pe20_23(.reset(effective_rst), .clk(clk), .in_a(a20_22to20_23), .in_b(b19_23to20_23), .out_a(a20_23to20_24), .out_b(b20_23to21_23), .out_c(matrixC20_23)); +processing_element pe20_24(.reset(effective_rst), .clk(clk), .in_a(a20_23to20_24), .in_b(b19_24to20_24), .out_a(a20_24to20_25), .out_b(b20_24to21_24), .out_c(matrixC20_24)); +processing_element pe20_25(.reset(effective_rst), .clk(clk), .in_a(a20_24to20_25), .in_b(b19_25to20_25), .out_a(a20_25to20_26), .out_b(b20_25to21_25), .out_c(matrixC20_25)); +processing_element pe20_26(.reset(effective_rst), .clk(clk), .in_a(a20_25to20_26), .in_b(b19_26to20_26), .out_a(a20_26to20_27), .out_b(b20_26to21_26), .out_c(matrixC20_26)); +processing_element pe20_27(.reset(effective_rst), .clk(clk), .in_a(a20_26to20_27), .in_b(b19_27to20_27), .out_a(a20_27to20_28), .out_b(b20_27to21_27), .out_c(matrixC20_27)); +processing_element pe20_28(.reset(effective_rst), .clk(clk), .in_a(a20_27to20_28), .in_b(b19_28to20_28), .out_a(a20_28to20_29), .out_b(b20_28to21_28), .out_c(matrixC20_28)); +processing_element pe20_29(.reset(effective_rst), .clk(clk), .in_a(a20_28to20_29), .in_b(b19_29to20_29), .out_a(a20_29to20_30), .out_b(b20_29to21_29), .out_c(matrixC20_29)); +processing_element pe20_30(.reset(effective_rst), .clk(clk), .in_a(a20_29to20_30), .in_b(b19_30to20_30), .out_a(a20_30to20_31), .out_b(b20_30to21_30), .out_c(matrixC20_30)); +processing_element pe20_31(.reset(effective_rst), .clk(clk), .in_a(a20_30to20_31), .in_b(b19_31to20_31), .out_a(a20_31to20_32), .out_b(b20_31to21_31), .out_c(matrixC20_31)); +processing_element pe21_1(.reset(effective_rst), .clk(clk), .in_a(a21_0to21_1), .in_b(b20_1to21_1), .out_a(a21_1to21_2), .out_b(b21_1to22_1), .out_c(matrixC21_1)); +processing_element pe21_2(.reset(effective_rst), .clk(clk), .in_a(a21_1to21_2), .in_b(b20_2to21_2), .out_a(a21_2to21_3), .out_b(b21_2to22_2), .out_c(matrixC21_2)); +processing_element pe21_3(.reset(effective_rst), .clk(clk), .in_a(a21_2to21_3), .in_b(b20_3to21_3), .out_a(a21_3to21_4), .out_b(b21_3to22_3), .out_c(matrixC21_3)); +processing_element pe21_4(.reset(effective_rst), .clk(clk), .in_a(a21_3to21_4), .in_b(b20_4to21_4), .out_a(a21_4to21_5), .out_b(b21_4to22_4), .out_c(matrixC21_4)); +processing_element pe21_5(.reset(effective_rst), .clk(clk), .in_a(a21_4to21_5), .in_b(b20_5to21_5), .out_a(a21_5to21_6), .out_b(b21_5to22_5), .out_c(matrixC21_5)); +processing_element pe21_6(.reset(effective_rst), .clk(clk), .in_a(a21_5to21_6), .in_b(b20_6to21_6), .out_a(a21_6to21_7), .out_b(b21_6to22_6), .out_c(matrixC21_6)); +processing_element pe21_7(.reset(effective_rst), .clk(clk), .in_a(a21_6to21_7), .in_b(b20_7to21_7), .out_a(a21_7to21_8), .out_b(b21_7to22_7), .out_c(matrixC21_7)); +processing_element pe21_8(.reset(effective_rst), .clk(clk), .in_a(a21_7to21_8), .in_b(b20_8to21_8), .out_a(a21_8to21_9), .out_b(b21_8to22_8), .out_c(matrixC21_8)); +processing_element pe21_9(.reset(effective_rst), .clk(clk), .in_a(a21_8to21_9), .in_b(b20_9to21_9), .out_a(a21_9to21_10), .out_b(b21_9to22_9), .out_c(matrixC21_9)); +processing_element pe21_10(.reset(effective_rst), .clk(clk), .in_a(a21_9to21_10), .in_b(b20_10to21_10), .out_a(a21_10to21_11), .out_b(b21_10to22_10), .out_c(matrixC21_10)); +processing_element pe21_11(.reset(effective_rst), .clk(clk), .in_a(a21_10to21_11), .in_b(b20_11to21_11), .out_a(a21_11to21_12), .out_b(b21_11to22_11), .out_c(matrixC21_11)); +processing_element pe21_12(.reset(effective_rst), .clk(clk), .in_a(a21_11to21_12), .in_b(b20_12to21_12), .out_a(a21_12to21_13), .out_b(b21_12to22_12), .out_c(matrixC21_12)); +processing_element pe21_13(.reset(effective_rst), .clk(clk), .in_a(a21_12to21_13), .in_b(b20_13to21_13), .out_a(a21_13to21_14), .out_b(b21_13to22_13), .out_c(matrixC21_13)); +processing_element pe21_14(.reset(effective_rst), .clk(clk), .in_a(a21_13to21_14), .in_b(b20_14to21_14), .out_a(a21_14to21_15), .out_b(b21_14to22_14), .out_c(matrixC21_14)); +processing_element pe21_15(.reset(effective_rst), .clk(clk), .in_a(a21_14to21_15), .in_b(b20_15to21_15), .out_a(a21_15to21_16), .out_b(b21_15to22_15), .out_c(matrixC21_15)); +processing_element pe21_16(.reset(effective_rst), .clk(clk), .in_a(a21_15to21_16), .in_b(b20_16to21_16), .out_a(a21_16to21_17), .out_b(b21_16to22_16), .out_c(matrixC21_16)); +processing_element pe21_17(.reset(effective_rst), .clk(clk), .in_a(a21_16to21_17), .in_b(b20_17to21_17), .out_a(a21_17to21_18), .out_b(b21_17to22_17), .out_c(matrixC21_17)); +processing_element pe21_18(.reset(effective_rst), .clk(clk), .in_a(a21_17to21_18), .in_b(b20_18to21_18), .out_a(a21_18to21_19), .out_b(b21_18to22_18), .out_c(matrixC21_18)); +processing_element pe21_19(.reset(effective_rst), .clk(clk), .in_a(a21_18to21_19), .in_b(b20_19to21_19), .out_a(a21_19to21_20), .out_b(b21_19to22_19), .out_c(matrixC21_19)); +processing_element pe21_20(.reset(effective_rst), .clk(clk), .in_a(a21_19to21_20), .in_b(b20_20to21_20), .out_a(a21_20to21_21), .out_b(b21_20to22_20), .out_c(matrixC21_20)); +processing_element pe21_21(.reset(effective_rst), .clk(clk), .in_a(a21_20to21_21), .in_b(b20_21to21_21), .out_a(a21_21to21_22), .out_b(b21_21to22_21), .out_c(matrixC21_21)); +processing_element pe21_22(.reset(effective_rst), .clk(clk), .in_a(a21_21to21_22), .in_b(b20_22to21_22), .out_a(a21_22to21_23), .out_b(b21_22to22_22), .out_c(matrixC21_22)); +processing_element pe21_23(.reset(effective_rst), .clk(clk), .in_a(a21_22to21_23), .in_b(b20_23to21_23), .out_a(a21_23to21_24), .out_b(b21_23to22_23), .out_c(matrixC21_23)); +processing_element pe21_24(.reset(effective_rst), .clk(clk), .in_a(a21_23to21_24), .in_b(b20_24to21_24), .out_a(a21_24to21_25), .out_b(b21_24to22_24), .out_c(matrixC21_24)); +processing_element pe21_25(.reset(effective_rst), .clk(clk), .in_a(a21_24to21_25), .in_b(b20_25to21_25), .out_a(a21_25to21_26), .out_b(b21_25to22_25), .out_c(matrixC21_25)); +processing_element pe21_26(.reset(effective_rst), .clk(clk), .in_a(a21_25to21_26), .in_b(b20_26to21_26), .out_a(a21_26to21_27), .out_b(b21_26to22_26), .out_c(matrixC21_26)); +processing_element pe21_27(.reset(effective_rst), .clk(clk), .in_a(a21_26to21_27), .in_b(b20_27to21_27), .out_a(a21_27to21_28), .out_b(b21_27to22_27), .out_c(matrixC21_27)); +processing_element pe21_28(.reset(effective_rst), .clk(clk), .in_a(a21_27to21_28), .in_b(b20_28to21_28), .out_a(a21_28to21_29), .out_b(b21_28to22_28), .out_c(matrixC21_28)); +processing_element pe21_29(.reset(effective_rst), .clk(clk), .in_a(a21_28to21_29), .in_b(b20_29to21_29), .out_a(a21_29to21_30), .out_b(b21_29to22_29), .out_c(matrixC21_29)); +processing_element pe21_30(.reset(effective_rst), .clk(clk), .in_a(a21_29to21_30), .in_b(b20_30to21_30), .out_a(a21_30to21_31), .out_b(b21_30to22_30), .out_c(matrixC21_30)); +processing_element pe21_31(.reset(effective_rst), .clk(clk), .in_a(a21_30to21_31), .in_b(b20_31to21_31), .out_a(a21_31to21_32), .out_b(b21_31to22_31), .out_c(matrixC21_31)); +processing_element pe22_1(.reset(effective_rst), .clk(clk), .in_a(a22_0to22_1), .in_b(b21_1to22_1), .out_a(a22_1to22_2), .out_b(b22_1to23_1), .out_c(matrixC22_1)); +processing_element pe22_2(.reset(effective_rst), .clk(clk), .in_a(a22_1to22_2), .in_b(b21_2to22_2), .out_a(a22_2to22_3), .out_b(b22_2to23_2), .out_c(matrixC22_2)); +processing_element pe22_3(.reset(effective_rst), .clk(clk), .in_a(a22_2to22_3), .in_b(b21_3to22_3), .out_a(a22_3to22_4), .out_b(b22_3to23_3), .out_c(matrixC22_3)); +processing_element pe22_4(.reset(effective_rst), .clk(clk), .in_a(a22_3to22_4), .in_b(b21_4to22_4), .out_a(a22_4to22_5), .out_b(b22_4to23_4), .out_c(matrixC22_4)); +processing_element pe22_5(.reset(effective_rst), .clk(clk), .in_a(a22_4to22_5), .in_b(b21_5to22_5), .out_a(a22_5to22_6), .out_b(b22_5to23_5), .out_c(matrixC22_5)); +processing_element pe22_6(.reset(effective_rst), .clk(clk), .in_a(a22_5to22_6), .in_b(b21_6to22_6), .out_a(a22_6to22_7), .out_b(b22_6to23_6), .out_c(matrixC22_6)); +processing_element pe22_7(.reset(effective_rst), .clk(clk), .in_a(a22_6to22_7), .in_b(b21_7to22_7), .out_a(a22_7to22_8), .out_b(b22_7to23_7), .out_c(matrixC22_7)); +processing_element pe22_8(.reset(effective_rst), .clk(clk), .in_a(a22_7to22_8), .in_b(b21_8to22_8), .out_a(a22_8to22_9), .out_b(b22_8to23_8), .out_c(matrixC22_8)); +processing_element pe22_9(.reset(effective_rst), .clk(clk), .in_a(a22_8to22_9), .in_b(b21_9to22_9), .out_a(a22_9to22_10), .out_b(b22_9to23_9), .out_c(matrixC22_9)); +processing_element pe22_10(.reset(effective_rst), .clk(clk), .in_a(a22_9to22_10), .in_b(b21_10to22_10), .out_a(a22_10to22_11), .out_b(b22_10to23_10), .out_c(matrixC22_10)); +processing_element pe22_11(.reset(effective_rst), .clk(clk), .in_a(a22_10to22_11), .in_b(b21_11to22_11), .out_a(a22_11to22_12), .out_b(b22_11to23_11), .out_c(matrixC22_11)); +processing_element pe22_12(.reset(effective_rst), .clk(clk), .in_a(a22_11to22_12), .in_b(b21_12to22_12), .out_a(a22_12to22_13), .out_b(b22_12to23_12), .out_c(matrixC22_12)); +processing_element pe22_13(.reset(effective_rst), .clk(clk), .in_a(a22_12to22_13), .in_b(b21_13to22_13), .out_a(a22_13to22_14), .out_b(b22_13to23_13), .out_c(matrixC22_13)); +processing_element pe22_14(.reset(effective_rst), .clk(clk), .in_a(a22_13to22_14), .in_b(b21_14to22_14), .out_a(a22_14to22_15), .out_b(b22_14to23_14), .out_c(matrixC22_14)); +processing_element pe22_15(.reset(effective_rst), .clk(clk), .in_a(a22_14to22_15), .in_b(b21_15to22_15), .out_a(a22_15to22_16), .out_b(b22_15to23_15), .out_c(matrixC22_15)); +processing_element pe22_16(.reset(effective_rst), .clk(clk), .in_a(a22_15to22_16), .in_b(b21_16to22_16), .out_a(a22_16to22_17), .out_b(b22_16to23_16), .out_c(matrixC22_16)); +processing_element pe22_17(.reset(effective_rst), .clk(clk), .in_a(a22_16to22_17), .in_b(b21_17to22_17), .out_a(a22_17to22_18), .out_b(b22_17to23_17), .out_c(matrixC22_17)); +processing_element pe22_18(.reset(effective_rst), .clk(clk), .in_a(a22_17to22_18), .in_b(b21_18to22_18), .out_a(a22_18to22_19), .out_b(b22_18to23_18), .out_c(matrixC22_18)); +processing_element pe22_19(.reset(effective_rst), .clk(clk), .in_a(a22_18to22_19), .in_b(b21_19to22_19), .out_a(a22_19to22_20), .out_b(b22_19to23_19), .out_c(matrixC22_19)); +processing_element pe22_20(.reset(effective_rst), .clk(clk), .in_a(a22_19to22_20), .in_b(b21_20to22_20), .out_a(a22_20to22_21), .out_b(b22_20to23_20), .out_c(matrixC22_20)); +processing_element pe22_21(.reset(effective_rst), .clk(clk), .in_a(a22_20to22_21), .in_b(b21_21to22_21), .out_a(a22_21to22_22), .out_b(b22_21to23_21), .out_c(matrixC22_21)); +processing_element pe22_22(.reset(effective_rst), .clk(clk), .in_a(a22_21to22_22), .in_b(b21_22to22_22), .out_a(a22_22to22_23), .out_b(b22_22to23_22), .out_c(matrixC22_22)); +processing_element pe22_23(.reset(effective_rst), .clk(clk), .in_a(a22_22to22_23), .in_b(b21_23to22_23), .out_a(a22_23to22_24), .out_b(b22_23to23_23), .out_c(matrixC22_23)); +processing_element pe22_24(.reset(effective_rst), .clk(clk), .in_a(a22_23to22_24), .in_b(b21_24to22_24), .out_a(a22_24to22_25), .out_b(b22_24to23_24), .out_c(matrixC22_24)); +processing_element pe22_25(.reset(effective_rst), .clk(clk), .in_a(a22_24to22_25), .in_b(b21_25to22_25), .out_a(a22_25to22_26), .out_b(b22_25to23_25), .out_c(matrixC22_25)); +processing_element pe22_26(.reset(effective_rst), .clk(clk), .in_a(a22_25to22_26), .in_b(b21_26to22_26), .out_a(a22_26to22_27), .out_b(b22_26to23_26), .out_c(matrixC22_26)); +processing_element pe22_27(.reset(effective_rst), .clk(clk), .in_a(a22_26to22_27), .in_b(b21_27to22_27), .out_a(a22_27to22_28), .out_b(b22_27to23_27), .out_c(matrixC22_27)); +processing_element pe22_28(.reset(effective_rst), .clk(clk), .in_a(a22_27to22_28), .in_b(b21_28to22_28), .out_a(a22_28to22_29), .out_b(b22_28to23_28), .out_c(matrixC22_28)); +processing_element pe22_29(.reset(effective_rst), .clk(clk), .in_a(a22_28to22_29), .in_b(b21_29to22_29), .out_a(a22_29to22_30), .out_b(b22_29to23_29), .out_c(matrixC22_29)); +processing_element pe22_30(.reset(effective_rst), .clk(clk), .in_a(a22_29to22_30), .in_b(b21_30to22_30), .out_a(a22_30to22_31), .out_b(b22_30to23_30), .out_c(matrixC22_30)); +processing_element pe22_31(.reset(effective_rst), .clk(clk), .in_a(a22_30to22_31), .in_b(b21_31to22_31), .out_a(a22_31to22_32), .out_b(b22_31to23_31), .out_c(matrixC22_31)); +processing_element pe23_1(.reset(effective_rst), .clk(clk), .in_a(a23_0to23_1), .in_b(b22_1to23_1), .out_a(a23_1to23_2), .out_b(b23_1to24_1), .out_c(matrixC23_1)); +processing_element pe23_2(.reset(effective_rst), .clk(clk), .in_a(a23_1to23_2), .in_b(b22_2to23_2), .out_a(a23_2to23_3), .out_b(b23_2to24_2), .out_c(matrixC23_2)); +processing_element pe23_3(.reset(effective_rst), .clk(clk), .in_a(a23_2to23_3), .in_b(b22_3to23_3), .out_a(a23_3to23_4), .out_b(b23_3to24_3), .out_c(matrixC23_3)); +processing_element pe23_4(.reset(effective_rst), .clk(clk), .in_a(a23_3to23_4), .in_b(b22_4to23_4), .out_a(a23_4to23_5), .out_b(b23_4to24_4), .out_c(matrixC23_4)); +processing_element pe23_5(.reset(effective_rst), .clk(clk), .in_a(a23_4to23_5), .in_b(b22_5to23_5), .out_a(a23_5to23_6), .out_b(b23_5to24_5), .out_c(matrixC23_5)); +processing_element pe23_6(.reset(effective_rst), .clk(clk), .in_a(a23_5to23_6), .in_b(b22_6to23_6), .out_a(a23_6to23_7), .out_b(b23_6to24_6), .out_c(matrixC23_6)); +processing_element pe23_7(.reset(effective_rst), .clk(clk), .in_a(a23_6to23_7), .in_b(b22_7to23_7), .out_a(a23_7to23_8), .out_b(b23_7to24_7), .out_c(matrixC23_7)); +processing_element pe23_8(.reset(effective_rst), .clk(clk), .in_a(a23_7to23_8), .in_b(b22_8to23_8), .out_a(a23_8to23_9), .out_b(b23_8to24_8), .out_c(matrixC23_8)); +processing_element pe23_9(.reset(effective_rst), .clk(clk), .in_a(a23_8to23_9), .in_b(b22_9to23_9), .out_a(a23_9to23_10), .out_b(b23_9to24_9), .out_c(matrixC23_9)); +processing_element pe23_10(.reset(effective_rst), .clk(clk), .in_a(a23_9to23_10), .in_b(b22_10to23_10), .out_a(a23_10to23_11), .out_b(b23_10to24_10), .out_c(matrixC23_10)); +processing_element pe23_11(.reset(effective_rst), .clk(clk), .in_a(a23_10to23_11), .in_b(b22_11to23_11), .out_a(a23_11to23_12), .out_b(b23_11to24_11), .out_c(matrixC23_11)); +processing_element pe23_12(.reset(effective_rst), .clk(clk), .in_a(a23_11to23_12), .in_b(b22_12to23_12), .out_a(a23_12to23_13), .out_b(b23_12to24_12), .out_c(matrixC23_12)); +processing_element pe23_13(.reset(effective_rst), .clk(clk), .in_a(a23_12to23_13), .in_b(b22_13to23_13), .out_a(a23_13to23_14), .out_b(b23_13to24_13), .out_c(matrixC23_13)); +processing_element pe23_14(.reset(effective_rst), .clk(clk), .in_a(a23_13to23_14), .in_b(b22_14to23_14), .out_a(a23_14to23_15), .out_b(b23_14to24_14), .out_c(matrixC23_14)); +processing_element pe23_15(.reset(effective_rst), .clk(clk), .in_a(a23_14to23_15), .in_b(b22_15to23_15), .out_a(a23_15to23_16), .out_b(b23_15to24_15), .out_c(matrixC23_15)); +processing_element pe23_16(.reset(effective_rst), .clk(clk), .in_a(a23_15to23_16), .in_b(b22_16to23_16), .out_a(a23_16to23_17), .out_b(b23_16to24_16), .out_c(matrixC23_16)); +processing_element pe23_17(.reset(effective_rst), .clk(clk), .in_a(a23_16to23_17), .in_b(b22_17to23_17), .out_a(a23_17to23_18), .out_b(b23_17to24_17), .out_c(matrixC23_17)); +processing_element pe23_18(.reset(effective_rst), .clk(clk), .in_a(a23_17to23_18), .in_b(b22_18to23_18), .out_a(a23_18to23_19), .out_b(b23_18to24_18), .out_c(matrixC23_18)); +processing_element pe23_19(.reset(effective_rst), .clk(clk), .in_a(a23_18to23_19), .in_b(b22_19to23_19), .out_a(a23_19to23_20), .out_b(b23_19to24_19), .out_c(matrixC23_19)); +processing_element pe23_20(.reset(effective_rst), .clk(clk), .in_a(a23_19to23_20), .in_b(b22_20to23_20), .out_a(a23_20to23_21), .out_b(b23_20to24_20), .out_c(matrixC23_20)); +processing_element pe23_21(.reset(effective_rst), .clk(clk), .in_a(a23_20to23_21), .in_b(b22_21to23_21), .out_a(a23_21to23_22), .out_b(b23_21to24_21), .out_c(matrixC23_21)); +processing_element pe23_22(.reset(effective_rst), .clk(clk), .in_a(a23_21to23_22), .in_b(b22_22to23_22), .out_a(a23_22to23_23), .out_b(b23_22to24_22), .out_c(matrixC23_22)); +processing_element pe23_23(.reset(effective_rst), .clk(clk), .in_a(a23_22to23_23), .in_b(b22_23to23_23), .out_a(a23_23to23_24), .out_b(b23_23to24_23), .out_c(matrixC23_23)); +processing_element pe23_24(.reset(effective_rst), .clk(clk), .in_a(a23_23to23_24), .in_b(b22_24to23_24), .out_a(a23_24to23_25), .out_b(b23_24to24_24), .out_c(matrixC23_24)); +processing_element pe23_25(.reset(effective_rst), .clk(clk), .in_a(a23_24to23_25), .in_b(b22_25to23_25), .out_a(a23_25to23_26), .out_b(b23_25to24_25), .out_c(matrixC23_25)); +processing_element pe23_26(.reset(effective_rst), .clk(clk), .in_a(a23_25to23_26), .in_b(b22_26to23_26), .out_a(a23_26to23_27), .out_b(b23_26to24_26), .out_c(matrixC23_26)); +processing_element pe23_27(.reset(effective_rst), .clk(clk), .in_a(a23_26to23_27), .in_b(b22_27to23_27), .out_a(a23_27to23_28), .out_b(b23_27to24_27), .out_c(matrixC23_27)); +processing_element pe23_28(.reset(effective_rst), .clk(clk), .in_a(a23_27to23_28), .in_b(b22_28to23_28), .out_a(a23_28to23_29), .out_b(b23_28to24_28), .out_c(matrixC23_28)); +processing_element pe23_29(.reset(effective_rst), .clk(clk), .in_a(a23_28to23_29), .in_b(b22_29to23_29), .out_a(a23_29to23_30), .out_b(b23_29to24_29), .out_c(matrixC23_29)); +processing_element pe23_30(.reset(effective_rst), .clk(clk), .in_a(a23_29to23_30), .in_b(b22_30to23_30), .out_a(a23_30to23_31), .out_b(b23_30to24_30), .out_c(matrixC23_30)); +processing_element pe23_31(.reset(effective_rst), .clk(clk), .in_a(a23_30to23_31), .in_b(b22_31to23_31), .out_a(a23_31to23_32), .out_b(b23_31to24_31), .out_c(matrixC23_31)); +processing_element pe24_1(.reset(effective_rst), .clk(clk), .in_a(a24_0to24_1), .in_b(b23_1to24_1), .out_a(a24_1to24_2), .out_b(b24_1to25_1), .out_c(matrixC24_1)); +processing_element pe24_2(.reset(effective_rst), .clk(clk), .in_a(a24_1to24_2), .in_b(b23_2to24_2), .out_a(a24_2to24_3), .out_b(b24_2to25_2), .out_c(matrixC24_2)); +processing_element pe24_3(.reset(effective_rst), .clk(clk), .in_a(a24_2to24_3), .in_b(b23_3to24_3), .out_a(a24_3to24_4), .out_b(b24_3to25_3), .out_c(matrixC24_3)); +processing_element pe24_4(.reset(effective_rst), .clk(clk), .in_a(a24_3to24_4), .in_b(b23_4to24_4), .out_a(a24_4to24_5), .out_b(b24_4to25_4), .out_c(matrixC24_4)); +processing_element pe24_5(.reset(effective_rst), .clk(clk), .in_a(a24_4to24_5), .in_b(b23_5to24_5), .out_a(a24_5to24_6), .out_b(b24_5to25_5), .out_c(matrixC24_5)); +processing_element pe24_6(.reset(effective_rst), .clk(clk), .in_a(a24_5to24_6), .in_b(b23_6to24_6), .out_a(a24_6to24_7), .out_b(b24_6to25_6), .out_c(matrixC24_6)); +processing_element pe24_7(.reset(effective_rst), .clk(clk), .in_a(a24_6to24_7), .in_b(b23_7to24_7), .out_a(a24_7to24_8), .out_b(b24_7to25_7), .out_c(matrixC24_7)); +processing_element pe24_8(.reset(effective_rst), .clk(clk), .in_a(a24_7to24_8), .in_b(b23_8to24_8), .out_a(a24_8to24_9), .out_b(b24_8to25_8), .out_c(matrixC24_8)); +processing_element pe24_9(.reset(effective_rst), .clk(clk), .in_a(a24_8to24_9), .in_b(b23_9to24_9), .out_a(a24_9to24_10), .out_b(b24_9to25_9), .out_c(matrixC24_9)); +processing_element pe24_10(.reset(effective_rst), .clk(clk), .in_a(a24_9to24_10), .in_b(b23_10to24_10), .out_a(a24_10to24_11), .out_b(b24_10to25_10), .out_c(matrixC24_10)); +processing_element pe24_11(.reset(effective_rst), .clk(clk), .in_a(a24_10to24_11), .in_b(b23_11to24_11), .out_a(a24_11to24_12), .out_b(b24_11to25_11), .out_c(matrixC24_11)); +processing_element pe24_12(.reset(effective_rst), .clk(clk), .in_a(a24_11to24_12), .in_b(b23_12to24_12), .out_a(a24_12to24_13), .out_b(b24_12to25_12), .out_c(matrixC24_12)); +processing_element pe24_13(.reset(effective_rst), .clk(clk), .in_a(a24_12to24_13), .in_b(b23_13to24_13), .out_a(a24_13to24_14), .out_b(b24_13to25_13), .out_c(matrixC24_13)); +processing_element pe24_14(.reset(effective_rst), .clk(clk), .in_a(a24_13to24_14), .in_b(b23_14to24_14), .out_a(a24_14to24_15), .out_b(b24_14to25_14), .out_c(matrixC24_14)); +processing_element pe24_15(.reset(effective_rst), .clk(clk), .in_a(a24_14to24_15), .in_b(b23_15to24_15), .out_a(a24_15to24_16), .out_b(b24_15to25_15), .out_c(matrixC24_15)); +processing_element pe24_16(.reset(effective_rst), .clk(clk), .in_a(a24_15to24_16), .in_b(b23_16to24_16), .out_a(a24_16to24_17), .out_b(b24_16to25_16), .out_c(matrixC24_16)); +processing_element pe24_17(.reset(effective_rst), .clk(clk), .in_a(a24_16to24_17), .in_b(b23_17to24_17), .out_a(a24_17to24_18), .out_b(b24_17to25_17), .out_c(matrixC24_17)); +processing_element pe24_18(.reset(effective_rst), .clk(clk), .in_a(a24_17to24_18), .in_b(b23_18to24_18), .out_a(a24_18to24_19), .out_b(b24_18to25_18), .out_c(matrixC24_18)); +processing_element pe24_19(.reset(effective_rst), .clk(clk), .in_a(a24_18to24_19), .in_b(b23_19to24_19), .out_a(a24_19to24_20), .out_b(b24_19to25_19), .out_c(matrixC24_19)); +processing_element pe24_20(.reset(effective_rst), .clk(clk), .in_a(a24_19to24_20), .in_b(b23_20to24_20), .out_a(a24_20to24_21), .out_b(b24_20to25_20), .out_c(matrixC24_20)); +processing_element pe24_21(.reset(effective_rst), .clk(clk), .in_a(a24_20to24_21), .in_b(b23_21to24_21), .out_a(a24_21to24_22), .out_b(b24_21to25_21), .out_c(matrixC24_21)); +processing_element pe24_22(.reset(effective_rst), .clk(clk), .in_a(a24_21to24_22), .in_b(b23_22to24_22), .out_a(a24_22to24_23), .out_b(b24_22to25_22), .out_c(matrixC24_22)); +processing_element pe24_23(.reset(effective_rst), .clk(clk), .in_a(a24_22to24_23), .in_b(b23_23to24_23), .out_a(a24_23to24_24), .out_b(b24_23to25_23), .out_c(matrixC24_23)); +processing_element pe24_24(.reset(effective_rst), .clk(clk), .in_a(a24_23to24_24), .in_b(b23_24to24_24), .out_a(a24_24to24_25), .out_b(b24_24to25_24), .out_c(matrixC24_24)); +processing_element pe24_25(.reset(effective_rst), .clk(clk), .in_a(a24_24to24_25), .in_b(b23_25to24_25), .out_a(a24_25to24_26), .out_b(b24_25to25_25), .out_c(matrixC24_25)); +processing_element pe24_26(.reset(effective_rst), .clk(clk), .in_a(a24_25to24_26), .in_b(b23_26to24_26), .out_a(a24_26to24_27), .out_b(b24_26to25_26), .out_c(matrixC24_26)); +processing_element pe24_27(.reset(effective_rst), .clk(clk), .in_a(a24_26to24_27), .in_b(b23_27to24_27), .out_a(a24_27to24_28), .out_b(b24_27to25_27), .out_c(matrixC24_27)); +processing_element pe24_28(.reset(effective_rst), .clk(clk), .in_a(a24_27to24_28), .in_b(b23_28to24_28), .out_a(a24_28to24_29), .out_b(b24_28to25_28), .out_c(matrixC24_28)); +processing_element pe24_29(.reset(effective_rst), .clk(clk), .in_a(a24_28to24_29), .in_b(b23_29to24_29), .out_a(a24_29to24_30), .out_b(b24_29to25_29), .out_c(matrixC24_29)); +processing_element pe24_30(.reset(effective_rst), .clk(clk), .in_a(a24_29to24_30), .in_b(b23_30to24_30), .out_a(a24_30to24_31), .out_b(b24_30to25_30), .out_c(matrixC24_30)); +processing_element pe24_31(.reset(effective_rst), .clk(clk), .in_a(a24_30to24_31), .in_b(b23_31to24_31), .out_a(a24_31to24_32), .out_b(b24_31to25_31), .out_c(matrixC24_31)); +processing_element pe25_1(.reset(effective_rst), .clk(clk), .in_a(a25_0to25_1), .in_b(b24_1to25_1), .out_a(a25_1to25_2), .out_b(b25_1to26_1), .out_c(matrixC25_1)); +processing_element pe25_2(.reset(effective_rst), .clk(clk), .in_a(a25_1to25_2), .in_b(b24_2to25_2), .out_a(a25_2to25_3), .out_b(b25_2to26_2), .out_c(matrixC25_2)); +processing_element pe25_3(.reset(effective_rst), .clk(clk), .in_a(a25_2to25_3), .in_b(b24_3to25_3), .out_a(a25_3to25_4), .out_b(b25_3to26_3), .out_c(matrixC25_3)); +processing_element pe25_4(.reset(effective_rst), .clk(clk), .in_a(a25_3to25_4), .in_b(b24_4to25_4), .out_a(a25_4to25_5), .out_b(b25_4to26_4), .out_c(matrixC25_4)); +processing_element pe25_5(.reset(effective_rst), .clk(clk), .in_a(a25_4to25_5), .in_b(b24_5to25_5), .out_a(a25_5to25_6), .out_b(b25_5to26_5), .out_c(matrixC25_5)); +processing_element pe25_6(.reset(effective_rst), .clk(clk), .in_a(a25_5to25_6), .in_b(b24_6to25_6), .out_a(a25_6to25_7), .out_b(b25_6to26_6), .out_c(matrixC25_6)); +processing_element pe25_7(.reset(effective_rst), .clk(clk), .in_a(a25_6to25_7), .in_b(b24_7to25_7), .out_a(a25_7to25_8), .out_b(b25_7to26_7), .out_c(matrixC25_7)); +processing_element pe25_8(.reset(effective_rst), .clk(clk), .in_a(a25_7to25_8), .in_b(b24_8to25_8), .out_a(a25_8to25_9), .out_b(b25_8to26_8), .out_c(matrixC25_8)); +processing_element pe25_9(.reset(effective_rst), .clk(clk), .in_a(a25_8to25_9), .in_b(b24_9to25_9), .out_a(a25_9to25_10), .out_b(b25_9to26_9), .out_c(matrixC25_9)); +processing_element pe25_10(.reset(effective_rst), .clk(clk), .in_a(a25_9to25_10), .in_b(b24_10to25_10), .out_a(a25_10to25_11), .out_b(b25_10to26_10), .out_c(matrixC25_10)); +processing_element pe25_11(.reset(effective_rst), .clk(clk), .in_a(a25_10to25_11), .in_b(b24_11to25_11), .out_a(a25_11to25_12), .out_b(b25_11to26_11), .out_c(matrixC25_11)); +processing_element pe25_12(.reset(effective_rst), .clk(clk), .in_a(a25_11to25_12), .in_b(b24_12to25_12), .out_a(a25_12to25_13), .out_b(b25_12to26_12), .out_c(matrixC25_12)); +processing_element pe25_13(.reset(effective_rst), .clk(clk), .in_a(a25_12to25_13), .in_b(b24_13to25_13), .out_a(a25_13to25_14), .out_b(b25_13to26_13), .out_c(matrixC25_13)); +processing_element pe25_14(.reset(effective_rst), .clk(clk), .in_a(a25_13to25_14), .in_b(b24_14to25_14), .out_a(a25_14to25_15), .out_b(b25_14to26_14), .out_c(matrixC25_14)); +processing_element pe25_15(.reset(effective_rst), .clk(clk), .in_a(a25_14to25_15), .in_b(b24_15to25_15), .out_a(a25_15to25_16), .out_b(b25_15to26_15), .out_c(matrixC25_15)); +processing_element pe25_16(.reset(effective_rst), .clk(clk), .in_a(a25_15to25_16), .in_b(b24_16to25_16), .out_a(a25_16to25_17), .out_b(b25_16to26_16), .out_c(matrixC25_16)); +processing_element pe25_17(.reset(effective_rst), .clk(clk), .in_a(a25_16to25_17), .in_b(b24_17to25_17), .out_a(a25_17to25_18), .out_b(b25_17to26_17), .out_c(matrixC25_17)); +processing_element pe25_18(.reset(effective_rst), .clk(clk), .in_a(a25_17to25_18), .in_b(b24_18to25_18), .out_a(a25_18to25_19), .out_b(b25_18to26_18), .out_c(matrixC25_18)); +processing_element pe25_19(.reset(effective_rst), .clk(clk), .in_a(a25_18to25_19), .in_b(b24_19to25_19), .out_a(a25_19to25_20), .out_b(b25_19to26_19), .out_c(matrixC25_19)); +processing_element pe25_20(.reset(effective_rst), .clk(clk), .in_a(a25_19to25_20), .in_b(b24_20to25_20), .out_a(a25_20to25_21), .out_b(b25_20to26_20), .out_c(matrixC25_20)); +processing_element pe25_21(.reset(effective_rst), .clk(clk), .in_a(a25_20to25_21), .in_b(b24_21to25_21), .out_a(a25_21to25_22), .out_b(b25_21to26_21), .out_c(matrixC25_21)); +processing_element pe25_22(.reset(effective_rst), .clk(clk), .in_a(a25_21to25_22), .in_b(b24_22to25_22), .out_a(a25_22to25_23), .out_b(b25_22to26_22), .out_c(matrixC25_22)); +processing_element pe25_23(.reset(effective_rst), .clk(clk), .in_a(a25_22to25_23), .in_b(b24_23to25_23), .out_a(a25_23to25_24), .out_b(b25_23to26_23), .out_c(matrixC25_23)); +processing_element pe25_24(.reset(effective_rst), .clk(clk), .in_a(a25_23to25_24), .in_b(b24_24to25_24), .out_a(a25_24to25_25), .out_b(b25_24to26_24), .out_c(matrixC25_24)); +processing_element pe25_25(.reset(effective_rst), .clk(clk), .in_a(a25_24to25_25), .in_b(b24_25to25_25), .out_a(a25_25to25_26), .out_b(b25_25to26_25), .out_c(matrixC25_25)); +processing_element pe25_26(.reset(effective_rst), .clk(clk), .in_a(a25_25to25_26), .in_b(b24_26to25_26), .out_a(a25_26to25_27), .out_b(b25_26to26_26), .out_c(matrixC25_26)); +processing_element pe25_27(.reset(effective_rst), .clk(clk), .in_a(a25_26to25_27), .in_b(b24_27to25_27), .out_a(a25_27to25_28), .out_b(b25_27to26_27), .out_c(matrixC25_27)); +processing_element pe25_28(.reset(effective_rst), .clk(clk), .in_a(a25_27to25_28), .in_b(b24_28to25_28), .out_a(a25_28to25_29), .out_b(b25_28to26_28), .out_c(matrixC25_28)); +processing_element pe25_29(.reset(effective_rst), .clk(clk), .in_a(a25_28to25_29), .in_b(b24_29to25_29), .out_a(a25_29to25_30), .out_b(b25_29to26_29), .out_c(matrixC25_29)); +processing_element pe25_30(.reset(effective_rst), .clk(clk), .in_a(a25_29to25_30), .in_b(b24_30to25_30), .out_a(a25_30to25_31), .out_b(b25_30to26_30), .out_c(matrixC25_30)); +processing_element pe25_31(.reset(effective_rst), .clk(clk), .in_a(a25_30to25_31), .in_b(b24_31to25_31), .out_a(a25_31to25_32), .out_b(b25_31to26_31), .out_c(matrixC25_31)); +processing_element pe26_1(.reset(effective_rst), .clk(clk), .in_a(a26_0to26_1), .in_b(b25_1to26_1), .out_a(a26_1to26_2), .out_b(b26_1to27_1), .out_c(matrixC26_1)); +processing_element pe26_2(.reset(effective_rst), .clk(clk), .in_a(a26_1to26_2), .in_b(b25_2to26_2), .out_a(a26_2to26_3), .out_b(b26_2to27_2), .out_c(matrixC26_2)); +processing_element pe26_3(.reset(effective_rst), .clk(clk), .in_a(a26_2to26_3), .in_b(b25_3to26_3), .out_a(a26_3to26_4), .out_b(b26_3to27_3), .out_c(matrixC26_3)); +processing_element pe26_4(.reset(effective_rst), .clk(clk), .in_a(a26_3to26_4), .in_b(b25_4to26_4), .out_a(a26_4to26_5), .out_b(b26_4to27_4), .out_c(matrixC26_4)); +processing_element pe26_5(.reset(effective_rst), .clk(clk), .in_a(a26_4to26_5), .in_b(b25_5to26_5), .out_a(a26_5to26_6), .out_b(b26_5to27_5), .out_c(matrixC26_5)); +processing_element pe26_6(.reset(effective_rst), .clk(clk), .in_a(a26_5to26_6), .in_b(b25_6to26_6), .out_a(a26_6to26_7), .out_b(b26_6to27_6), .out_c(matrixC26_6)); +processing_element pe26_7(.reset(effective_rst), .clk(clk), .in_a(a26_6to26_7), .in_b(b25_7to26_7), .out_a(a26_7to26_8), .out_b(b26_7to27_7), .out_c(matrixC26_7)); +processing_element pe26_8(.reset(effective_rst), .clk(clk), .in_a(a26_7to26_8), .in_b(b25_8to26_8), .out_a(a26_8to26_9), .out_b(b26_8to27_8), .out_c(matrixC26_8)); +processing_element pe26_9(.reset(effective_rst), .clk(clk), .in_a(a26_8to26_9), .in_b(b25_9to26_9), .out_a(a26_9to26_10), .out_b(b26_9to27_9), .out_c(matrixC26_9)); +processing_element pe26_10(.reset(effective_rst), .clk(clk), .in_a(a26_9to26_10), .in_b(b25_10to26_10), .out_a(a26_10to26_11), .out_b(b26_10to27_10), .out_c(matrixC26_10)); +processing_element pe26_11(.reset(effective_rst), .clk(clk), .in_a(a26_10to26_11), .in_b(b25_11to26_11), .out_a(a26_11to26_12), .out_b(b26_11to27_11), .out_c(matrixC26_11)); +processing_element pe26_12(.reset(effective_rst), .clk(clk), .in_a(a26_11to26_12), .in_b(b25_12to26_12), .out_a(a26_12to26_13), .out_b(b26_12to27_12), .out_c(matrixC26_12)); +processing_element pe26_13(.reset(effective_rst), .clk(clk), .in_a(a26_12to26_13), .in_b(b25_13to26_13), .out_a(a26_13to26_14), .out_b(b26_13to27_13), .out_c(matrixC26_13)); +processing_element pe26_14(.reset(effective_rst), .clk(clk), .in_a(a26_13to26_14), .in_b(b25_14to26_14), .out_a(a26_14to26_15), .out_b(b26_14to27_14), .out_c(matrixC26_14)); +processing_element pe26_15(.reset(effective_rst), .clk(clk), .in_a(a26_14to26_15), .in_b(b25_15to26_15), .out_a(a26_15to26_16), .out_b(b26_15to27_15), .out_c(matrixC26_15)); +processing_element pe26_16(.reset(effective_rst), .clk(clk), .in_a(a26_15to26_16), .in_b(b25_16to26_16), .out_a(a26_16to26_17), .out_b(b26_16to27_16), .out_c(matrixC26_16)); +processing_element pe26_17(.reset(effective_rst), .clk(clk), .in_a(a26_16to26_17), .in_b(b25_17to26_17), .out_a(a26_17to26_18), .out_b(b26_17to27_17), .out_c(matrixC26_17)); +processing_element pe26_18(.reset(effective_rst), .clk(clk), .in_a(a26_17to26_18), .in_b(b25_18to26_18), .out_a(a26_18to26_19), .out_b(b26_18to27_18), .out_c(matrixC26_18)); +processing_element pe26_19(.reset(effective_rst), .clk(clk), .in_a(a26_18to26_19), .in_b(b25_19to26_19), .out_a(a26_19to26_20), .out_b(b26_19to27_19), .out_c(matrixC26_19)); +processing_element pe26_20(.reset(effective_rst), .clk(clk), .in_a(a26_19to26_20), .in_b(b25_20to26_20), .out_a(a26_20to26_21), .out_b(b26_20to27_20), .out_c(matrixC26_20)); +processing_element pe26_21(.reset(effective_rst), .clk(clk), .in_a(a26_20to26_21), .in_b(b25_21to26_21), .out_a(a26_21to26_22), .out_b(b26_21to27_21), .out_c(matrixC26_21)); +processing_element pe26_22(.reset(effective_rst), .clk(clk), .in_a(a26_21to26_22), .in_b(b25_22to26_22), .out_a(a26_22to26_23), .out_b(b26_22to27_22), .out_c(matrixC26_22)); +processing_element pe26_23(.reset(effective_rst), .clk(clk), .in_a(a26_22to26_23), .in_b(b25_23to26_23), .out_a(a26_23to26_24), .out_b(b26_23to27_23), .out_c(matrixC26_23)); +processing_element pe26_24(.reset(effective_rst), .clk(clk), .in_a(a26_23to26_24), .in_b(b25_24to26_24), .out_a(a26_24to26_25), .out_b(b26_24to27_24), .out_c(matrixC26_24)); +processing_element pe26_25(.reset(effective_rst), .clk(clk), .in_a(a26_24to26_25), .in_b(b25_25to26_25), .out_a(a26_25to26_26), .out_b(b26_25to27_25), .out_c(matrixC26_25)); +processing_element pe26_26(.reset(effective_rst), .clk(clk), .in_a(a26_25to26_26), .in_b(b25_26to26_26), .out_a(a26_26to26_27), .out_b(b26_26to27_26), .out_c(matrixC26_26)); +processing_element pe26_27(.reset(effective_rst), .clk(clk), .in_a(a26_26to26_27), .in_b(b25_27to26_27), .out_a(a26_27to26_28), .out_b(b26_27to27_27), .out_c(matrixC26_27)); +processing_element pe26_28(.reset(effective_rst), .clk(clk), .in_a(a26_27to26_28), .in_b(b25_28to26_28), .out_a(a26_28to26_29), .out_b(b26_28to27_28), .out_c(matrixC26_28)); +processing_element pe26_29(.reset(effective_rst), .clk(clk), .in_a(a26_28to26_29), .in_b(b25_29to26_29), .out_a(a26_29to26_30), .out_b(b26_29to27_29), .out_c(matrixC26_29)); +processing_element pe26_30(.reset(effective_rst), .clk(clk), .in_a(a26_29to26_30), .in_b(b25_30to26_30), .out_a(a26_30to26_31), .out_b(b26_30to27_30), .out_c(matrixC26_30)); +processing_element pe26_31(.reset(effective_rst), .clk(clk), .in_a(a26_30to26_31), .in_b(b25_31to26_31), .out_a(a26_31to26_32), .out_b(b26_31to27_31), .out_c(matrixC26_31)); +processing_element pe27_1(.reset(effective_rst), .clk(clk), .in_a(a27_0to27_1), .in_b(b26_1to27_1), .out_a(a27_1to27_2), .out_b(b27_1to28_1), .out_c(matrixC27_1)); +processing_element pe27_2(.reset(effective_rst), .clk(clk), .in_a(a27_1to27_2), .in_b(b26_2to27_2), .out_a(a27_2to27_3), .out_b(b27_2to28_2), .out_c(matrixC27_2)); +processing_element pe27_3(.reset(effective_rst), .clk(clk), .in_a(a27_2to27_3), .in_b(b26_3to27_3), .out_a(a27_3to27_4), .out_b(b27_3to28_3), .out_c(matrixC27_3)); +processing_element pe27_4(.reset(effective_rst), .clk(clk), .in_a(a27_3to27_4), .in_b(b26_4to27_4), .out_a(a27_4to27_5), .out_b(b27_4to28_4), .out_c(matrixC27_4)); +processing_element pe27_5(.reset(effective_rst), .clk(clk), .in_a(a27_4to27_5), .in_b(b26_5to27_5), .out_a(a27_5to27_6), .out_b(b27_5to28_5), .out_c(matrixC27_5)); +processing_element pe27_6(.reset(effective_rst), .clk(clk), .in_a(a27_5to27_6), .in_b(b26_6to27_6), .out_a(a27_6to27_7), .out_b(b27_6to28_6), .out_c(matrixC27_6)); +processing_element pe27_7(.reset(effective_rst), .clk(clk), .in_a(a27_6to27_7), .in_b(b26_7to27_7), .out_a(a27_7to27_8), .out_b(b27_7to28_7), .out_c(matrixC27_7)); +processing_element pe27_8(.reset(effective_rst), .clk(clk), .in_a(a27_7to27_8), .in_b(b26_8to27_8), .out_a(a27_8to27_9), .out_b(b27_8to28_8), .out_c(matrixC27_8)); +processing_element pe27_9(.reset(effective_rst), .clk(clk), .in_a(a27_8to27_9), .in_b(b26_9to27_9), .out_a(a27_9to27_10), .out_b(b27_9to28_9), .out_c(matrixC27_9)); +processing_element pe27_10(.reset(effective_rst), .clk(clk), .in_a(a27_9to27_10), .in_b(b26_10to27_10), .out_a(a27_10to27_11), .out_b(b27_10to28_10), .out_c(matrixC27_10)); +processing_element pe27_11(.reset(effective_rst), .clk(clk), .in_a(a27_10to27_11), .in_b(b26_11to27_11), .out_a(a27_11to27_12), .out_b(b27_11to28_11), .out_c(matrixC27_11)); +processing_element pe27_12(.reset(effective_rst), .clk(clk), .in_a(a27_11to27_12), .in_b(b26_12to27_12), .out_a(a27_12to27_13), .out_b(b27_12to28_12), .out_c(matrixC27_12)); +processing_element pe27_13(.reset(effective_rst), .clk(clk), .in_a(a27_12to27_13), .in_b(b26_13to27_13), .out_a(a27_13to27_14), .out_b(b27_13to28_13), .out_c(matrixC27_13)); +processing_element pe27_14(.reset(effective_rst), .clk(clk), .in_a(a27_13to27_14), .in_b(b26_14to27_14), .out_a(a27_14to27_15), .out_b(b27_14to28_14), .out_c(matrixC27_14)); +processing_element pe27_15(.reset(effective_rst), .clk(clk), .in_a(a27_14to27_15), .in_b(b26_15to27_15), .out_a(a27_15to27_16), .out_b(b27_15to28_15), .out_c(matrixC27_15)); +processing_element pe27_16(.reset(effective_rst), .clk(clk), .in_a(a27_15to27_16), .in_b(b26_16to27_16), .out_a(a27_16to27_17), .out_b(b27_16to28_16), .out_c(matrixC27_16)); +processing_element pe27_17(.reset(effective_rst), .clk(clk), .in_a(a27_16to27_17), .in_b(b26_17to27_17), .out_a(a27_17to27_18), .out_b(b27_17to28_17), .out_c(matrixC27_17)); +processing_element pe27_18(.reset(effective_rst), .clk(clk), .in_a(a27_17to27_18), .in_b(b26_18to27_18), .out_a(a27_18to27_19), .out_b(b27_18to28_18), .out_c(matrixC27_18)); +processing_element pe27_19(.reset(effective_rst), .clk(clk), .in_a(a27_18to27_19), .in_b(b26_19to27_19), .out_a(a27_19to27_20), .out_b(b27_19to28_19), .out_c(matrixC27_19)); +processing_element pe27_20(.reset(effective_rst), .clk(clk), .in_a(a27_19to27_20), .in_b(b26_20to27_20), .out_a(a27_20to27_21), .out_b(b27_20to28_20), .out_c(matrixC27_20)); +processing_element pe27_21(.reset(effective_rst), .clk(clk), .in_a(a27_20to27_21), .in_b(b26_21to27_21), .out_a(a27_21to27_22), .out_b(b27_21to28_21), .out_c(matrixC27_21)); +processing_element pe27_22(.reset(effective_rst), .clk(clk), .in_a(a27_21to27_22), .in_b(b26_22to27_22), .out_a(a27_22to27_23), .out_b(b27_22to28_22), .out_c(matrixC27_22)); +processing_element pe27_23(.reset(effective_rst), .clk(clk), .in_a(a27_22to27_23), .in_b(b26_23to27_23), .out_a(a27_23to27_24), .out_b(b27_23to28_23), .out_c(matrixC27_23)); +processing_element pe27_24(.reset(effective_rst), .clk(clk), .in_a(a27_23to27_24), .in_b(b26_24to27_24), .out_a(a27_24to27_25), .out_b(b27_24to28_24), .out_c(matrixC27_24)); +processing_element pe27_25(.reset(effective_rst), .clk(clk), .in_a(a27_24to27_25), .in_b(b26_25to27_25), .out_a(a27_25to27_26), .out_b(b27_25to28_25), .out_c(matrixC27_25)); +processing_element pe27_26(.reset(effective_rst), .clk(clk), .in_a(a27_25to27_26), .in_b(b26_26to27_26), .out_a(a27_26to27_27), .out_b(b27_26to28_26), .out_c(matrixC27_26)); +processing_element pe27_27(.reset(effective_rst), .clk(clk), .in_a(a27_26to27_27), .in_b(b26_27to27_27), .out_a(a27_27to27_28), .out_b(b27_27to28_27), .out_c(matrixC27_27)); +processing_element pe27_28(.reset(effective_rst), .clk(clk), .in_a(a27_27to27_28), .in_b(b26_28to27_28), .out_a(a27_28to27_29), .out_b(b27_28to28_28), .out_c(matrixC27_28)); +processing_element pe27_29(.reset(effective_rst), .clk(clk), .in_a(a27_28to27_29), .in_b(b26_29to27_29), .out_a(a27_29to27_30), .out_b(b27_29to28_29), .out_c(matrixC27_29)); +processing_element pe27_30(.reset(effective_rst), .clk(clk), .in_a(a27_29to27_30), .in_b(b26_30to27_30), .out_a(a27_30to27_31), .out_b(b27_30to28_30), .out_c(matrixC27_30)); +processing_element pe27_31(.reset(effective_rst), .clk(clk), .in_a(a27_30to27_31), .in_b(b26_31to27_31), .out_a(a27_31to27_32), .out_b(b27_31to28_31), .out_c(matrixC27_31)); +processing_element pe28_1(.reset(effective_rst), .clk(clk), .in_a(a28_0to28_1), .in_b(b27_1to28_1), .out_a(a28_1to28_2), .out_b(b28_1to29_1), .out_c(matrixC28_1)); +processing_element pe28_2(.reset(effective_rst), .clk(clk), .in_a(a28_1to28_2), .in_b(b27_2to28_2), .out_a(a28_2to28_3), .out_b(b28_2to29_2), .out_c(matrixC28_2)); +processing_element pe28_3(.reset(effective_rst), .clk(clk), .in_a(a28_2to28_3), .in_b(b27_3to28_3), .out_a(a28_3to28_4), .out_b(b28_3to29_3), .out_c(matrixC28_3)); +processing_element pe28_4(.reset(effective_rst), .clk(clk), .in_a(a28_3to28_4), .in_b(b27_4to28_4), .out_a(a28_4to28_5), .out_b(b28_4to29_4), .out_c(matrixC28_4)); +processing_element pe28_5(.reset(effective_rst), .clk(clk), .in_a(a28_4to28_5), .in_b(b27_5to28_5), .out_a(a28_5to28_6), .out_b(b28_5to29_5), .out_c(matrixC28_5)); +processing_element pe28_6(.reset(effective_rst), .clk(clk), .in_a(a28_5to28_6), .in_b(b27_6to28_6), .out_a(a28_6to28_7), .out_b(b28_6to29_6), .out_c(matrixC28_6)); +processing_element pe28_7(.reset(effective_rst), .clk(clk), .in_a(a28_6to28_7), .in_b(b27_7to28_7), .out_a(a28_7to28_8), .out_b(b28_7to29_7), .out_c(matrixC28_7)); +processing_element pe28_8(.reset(effective_rst), .clk(clk), .in_a(a28_7to28_8), .in_b(b27_8to28_8), .out_a(a28_8to28_9), .out_b(b28_8to29_8), .out_c(matrixC28_8)); +processing_element pe28_9(.reset(effective_rst), .clk(clk), .in_a(a28_8to28_9), .in_b(b27_9to28_9), .out_a(a28_9to28_10), .out_b(b28_9to29_9), .out_c(matrixC28_9)); +processing_element pe28_10(.reset(effective_rst), .clk(clk), .in_a(a28_9to28_10), .in_b(b27_10to28_10), .out_a(a28_10to28_11), .out_b(b28_10to29_10), .out_c(matrixC28_10)); +processing_element pe28_11(.reset(effective_rst), .clk(clk), .in_a(a28_10to28_11), .in_b(b27_11to28_11), .out_a(a28_11to28_12), .out_b(b28_11to29_11), .out_c(matrixC28_11)); +processing_element pe28_12(.reset(effective_rst), .clk(clk), .in_a(a28_11to28_12), .in_b(b27_12to28_12), .out_a(a28_12to28_13), .out_b(b28_12to29_12), .out_c(matrixC28_12)); +processing_element pe28_13(.reset(effective_rst), .clk(clk), .in_a(a28_12to28_13), .in_b(b27_13to28_13), .out_a(a28_13to28_14), .out_b(b28_13to29_13), .out_c(matrixC28_13)); +processing_element pe28_14(.reset(effective_rst), .clk(clk), .in_a(a28_13to28_14), .in_b(b27_14to28_14), .out_a(a28_14to28_15), .out_b(b28_14to29_14), .out_c(matrixC28_14)); +processing_element pe28_15(.reset(effective_rst), .clk(clk), .in_a(a28_14to28_15), .in_b(b27_15to28_15), .out_a(a28_15to28_16), .out_b(b28_15to29_15), .out_c(matrixC28_15)); +processing_element pe28_16(.reset(effective_rst), .clk(clk), .in_a(a28_15to28_16), .in_b(b27_16to28_16), .out_a(a28_16to28_17), .out_b(b28_16to29_16), .out_c(matrixC28_16)); +processing_element pe28_17(.reset(effective_rst), .clk(clk), .in_a(a28_16to28_17), .in_b(b27_17to28_17), .out_a(a28_17to28_18), .out_b(b28_17to29_17), .out_c(matrixC28_17)); +processing_element pe28_18(.reset(effective_rst), .clk(clk), .in_a(a28_17to28_18), .in_b(b27_18to28_18), .out_a(a28_18to28_19), .out_b(b28_18to29_18), .out_c(matrixC28_18)); +processing_element pe28_19(.reset(effective_rst), .clk(clk), .in_a(a28_18to28_19), .in_b(b27_19to28_19), .out_a(a28_19to28_20), .out_b(b28_19to29_19), .out_c(matrixC28_19)); +processing_element pe28_20(.reset(effective_rst), .clk(clk), .in_a(a28_19to28_20), .in_b(b27_20to28_20), .out_a(a28_20to28_21), .out_b(b28_20to29_20), .out_c(matrixC28_20)); +processing_element pe28_21(.reset(effective_rst), .clk(clk), .in_a(a28_20to28_21), .in_b(b27_21to28_21), .out_a(a28_21to28_22), .out_b(b28_21to29_21), .out_c(matrixC28_21)); +processing_element pe28_22(.reset(effective_rst), .clk(clk), .in_a(a28_21to28_22), .in_b(b27_22to28_22), .out_a(a28_22to28_23), .out_b(b28_22to29_22), .out_c(matrixC28_22)); +processing_element pe28_23(.reset(effective_rst), .clk(clk), .in_a(a28_22to28_23), .in_b(b27_23to28_23), .out_a(a28_23to28_24), .out_b(b28_23to29_23), .out_c(matrixC28_23)); +processing_element pe28_24(.reset(effective_rst), .clk(clk), .in_a(a28_23to28_24), .in_b(b27_24to28_24), .out_a(a28_24to28_25), .out_b(b28_24to29_24), .out_c(matrixC28_24)); +processing_element pe28_25(.reset(effective_rst), .clk(clk), .in_a(a28_24to28_25), .in_b(b27_25to28_25), .out_a(a28_25to28_26), .out_b(b28_25to29_25), .out_c(matrixC28_25)); +processing_element pe28_26(.reset(effective_rst), .clk(clk), .in_a(a28_25to28_26), .in_b(b27_26to28_26), .out_a(a28_26to28_27), .out_b(b28_26to29_26), .out_c(matrixC28_26)); +processing_element pe28_27(.reset(effective_rst), .clk(clk), .in_a(a28_26to28_27), .in_b(b27_27to28_27), .out_a(a28_27to28_28), .out_b(b28_27to29_27), .out_c(matrixC28_27)); +processing_element pe28_28(.reset(effective_rst), .clk(clk), .in_a(a28_27to28_28), .in_b(b27_28to28_28), .out_a(a28_28to28_29), .out_b(b28_28to29_28), .out_c(matrixC28_28)); +processing_element pe28_29(.reset(effective_rst), .clk(clk), .in_a(a28_28to28_29), .in_b(b27_29to28_29), .out_a(a28_29to28_30), .out_b(b28_29to29_29), .out_c(matrixC28_29)); +processing_element pe28_30(.reset(effective_rst), .clk(clk), .in_a(a28_29to28_30), .in_b(b27_30to28_30), .out_a(a28_30to28_31), .out_b(b28_30to29_30), .out_c(matrixC28_30)); +processing_element pe28_31(.reset(effective_rst), .clk(clk), .in_a(a28_30to28_31), .in_b(b27_31to28_31), .out_a(a28_31to28_32), .out_b(b28_31to29_31), .out_c(matrixC28_31)); +processing_element pe29_1(.reset(effective_rst), .clk(clk), .in_a(a29_0to29_1), .in_b(b28_1to29_1), .out_a(a29_1to29_2), .out_b(b29_1to30_1), .out_c(matrixC29_1)); +processing_element pe29_2(.reset(effective_rst), .clk(clk), .in_a(a29_1to29_2), .in_b(b28_2to29_2), .out_a(a29_2to29_3), .out_b(b29_2to30_2), .out_c(matrixC29_2)); +processing_element pe29_3(.reset(effective_rst), .clk(clk), .in_a(a29_2to29_3), .in_b(b28_3to29_3), .out_a(a29_3to29_4), .out_b(b29_3to30_3), .out_c(matrixC29_3)); +processing_element pe29_4(.reset(effective_rst), .clk(clk), .in_a(a29_3to29_4), .in_b(b28_4to29_4), .out_a(a29_4to29_5), .out_b(b29_4to30_4), .out_c(matrixC29_4)); +processing_element pe29_5(.reset(effective_rst), .clk(clk), .in_a(a29_4to29_5), .in_b(b28_5to29_5), .out_a(a29_5to29_6), .out_b(b29_5to30_5), .out_c(matrixC29_5)); +processing_element pe29_6(.reset(effective_rst), .clk(clk), .in_a(a29_5to29_6), .in_b(b28_6to29_6), .out_a(a29_6to29_7), .out_b(b29_6to30_6), .out_c(matrixC29_6)); +processing_element pe29_7(.reset(effective_rst), .clk(clk), .in_a(a29_6to29_7), .in_b(b28_7to29_7), .out_a(a29_7to29_8), .out_b(b29_7to30_7), .out_c(matrixC29_7)); +processing_element pe29_8(.reset(effective_rst), .clk(clk), .in_a(a29_7to29_8), .in_b(b28_8to29_8), .out_a(a29_8to29_9), .out_b(b29_8to30_8), .out_c(matrixC29_8)); +processing_element pe29_9(.reset(effective_rst), .clk(clk), .in_a(a29_8to29_9), .in_b(b28_9to29_9), .out_a(a29_9to29_10), .out_b(b29_9to30_9), .out_c(matrixC29_9)); +processing_element pe29_10(.reset(effective_rst), .clk(clk), .in_a(a29_9to29_10), .in_b(b28_10to29_10), .out_a(a29_10to29_11), .out_b(b29_10to30_10), .out_c(matrixC29_10)); +processing_element pe29_11(.reset(effective_rst), .clk(clk), .in_a(a29_10to29_11), .in_b(b28_11to29_11), .out_a(a29_11to29_12), .out_b(b29_11to30_11), .out_c(matrixC29_11)); +processing_element pe29_12(.reset(effective_rst), .clk(clk), .in_a(a29_11to29_12), .in_b(b28_12to29_12), .out_a(a29_12to29_13), .out_b(b29_12to30_12), .out_c(matrixC29_12)); +processing_element pe29_13(.reset(effective_rst), .clk(clk), .in_a(a29_12to29_13), .in_b(b28_13to29_13), .out_a(a29_13to29_14), .out_b(b29_13to30_13), .out_c(matrixC29_13)); +processing_element pe29_14(.reset(effective_rst), .clk(clk), .in_a(a29_13to29_14), .in_b(b28_14to29_14), .out_a(a29_14to29_15), .out_b(b29_14to30_14), .out_c(matrixC29_14)); +processing_element pe29_15(.reset(effective_rst), .clk(clk), .in_a(a29_14to29_15), .in_b(b28_15to29_15), .out_a(a29_15to29_16), .out_b(b29_15to30_15), .out_c(matrixC29_15)); +processing_element pe29_16(.reset(effective_rst), .clk(clk), .in_a(a29_15to29_16), .in_b(b28_16to29_16), .out_a(a29_16to29_17), .out_b(b29_16to30_16), .out_c(matrixC29_16)); +processing_element pe29_17(.reset(effective_rst), .clk(clk), .in_a(a29_16to29_17), .in_b(b28_17to29_17), .out_a(a29_17to29_18), .out_b(b29_17to30_17), .out_c(matrixC29_17)); +processing_element pe29_18(.reset(effective_rst), .clk(clk), .in_a(a29_17to29_18), .in_b(b28_18to29_18), .out_a(a29_18to29_19), .out_b(b29_18to30_18), .out_c(matrixC29_18)); +processing_element pe29_19(.reset(effective_rst), .clk(clk), .in_a(a29_18to29_19), .in_b(b28_19to29_19), .out_a(a29_19to29_20), .out_b(b29_19to30_19), .out_c(matrixC29_19)); +processing_element pe29_20(.reset(effective_rst), .clk(clk), .in_a(a29_19to29_20), .in_b(b28_20to29_20), .out_a(a29_20to29_21), .out_b(b29_20to30_20), .out_c(matrixC29_20)); +processing_element pe29_21(.reset(effective_rst), .clk(clk), .in_a(a29_20to29_21), .in_b(b28_21to29_21), .out_a(a29_21to29_22), .out_b(b29_21to30_21), .out_c(matrixC29_21)); +processing_element pe29_22(.reset(effective_rst), .clk(clk), .in_a(a29_21to29_22), .in_b(b28_22to29_22), .out_a(a29_22to29_23), .out_b(b29_22to30_22), .out_c(matrixC29_22)); +processing_element pe29_23(.reset(effective_rst), .clk(clk), .in_a(a29_22to29_23), .in_b(b28_23to29_23), .out_a(a29_23to29_24), .out_b(b29_23to30_23), .out_c(matrixC29_23)); +processing_element pe29_24(.reset(effective_rst), .clk(clk), .in_a(a29_23to29_24), .in_b(b28_24to29_24), .out_a(a29_24to29_25), .out_b(b29_24to30_24), .out_c(matrixC29_24)); +processing_element pe29_25(.reset(effective_rst), .clk(clk), .in_a(a29_24to29_25), .in_b(b28_25to29_25), .out_a(a29_25to29_26), .out_b(b29_25to30_25), .out_c(matrixC29_25)); +processing_element pe29_26(.reset(effective_rst), .clk(clk), .in_a(a29_25to29_26), .in_b(b28_26to29_26), .out_a(a29_26to29_27), .out_b(b29_26to30_26), .out_c(matrixC29_26)); +processing_element pe29_27(.reset(effective_rst), .clk(clk), .in_a(a29_26to29_27), .in_b(b28_27to29_27), .out_a(a29_27to29_28), .out_b(b29_27to30_27), .out_c(matrixC29_27)); +processing_element pe29_28(.reset(effective_rst), .clk(clk), .in_a(a29_27to29_28), .in_b(b28_28to29_28), .out_a(a29_28to29_29), .out_b(b29_28to30_28), .out_c(matrixC29_28)); +processing_element pe29_29(.reset(effective_rst), .clk(clk), .in_a(a29_28to29_29), .in_b(b28_29to29_29), .out_a(a29_29to29_30), .out_b(b29_29to30_29), .out_c(matrixC29_29)); +processing_element pe29_30(.reset(effective_rst), .clk(clk), .in_a(a29_29to29_30), .in_b(b28_30to29_30), .out_a(a29_30to29_31), .out_b(b29_30to30_30), .out_c(matrixC29_30)); +processing_element pe29_31(.reset(effective_rst), .clk(clk), .in_a(a29_30to29_31), .in_b(b28_31to29_31), .out_a(a29_31to29_32), .out_b(b29_31to30_31), .out_c(matrixC29_31)); +processing_element pe30_1(.reset(effective_rst), .clk(clk), .in_a(a30_0to30_1), .in_b(b29_1to30_1), .out_a(a30_1to30_2), .out_b(b30_1to31_1), .out_c(matrixC30_1)); +processing_element pe30_2(.reset(effective_rst), .clk(clk), .in_a(a30_1to30_2), .in_b(b29_2to30_2), .out_a(a30_2to30_3), .out_b(b30_2to31_2), .out_c(matrixC30_2)); +processing_element pe30_3(.reset(effective_rst), .clk(clk), .in_a(a30_2to30_3), .in_b(b29_3to30_3), .out_a(a30_3to30_4), .out_b(b30_3to31_3), .out_c(matrixC30_3)); +processing_element pe30_4(.reset(effective_rst), .clk(clk), .in_a(a30_3to30_4), .in_b(b29_4to30_4), .out_a(a30_4to30_5), .out_b(b30_4to31_4), .out_c(matrixC30_4)); +processing_element pe30_5(.reset(effective_rst), .clk(clk), .in_a(a30_4to30_5), .in_b(b29_5to30_5), .out_a(a30_5to30_6), .out_b(b30_5to31_5), .out_c(matrixC30_5)); +processing_element pe30_6(.reset(effective_rst), .clk(clk), .in_a(a30_5to30_6), .in_b(b29_6to30_6), .out_a(a30_6to30_7), .out_b(b30_6to31_6), .out_c(matrixC30_6)); +processing_element pe30_7(.reset(effective_rst), .clk(clk), .in_a(a30_6to30_7), .in_b(b29_7to30_7), .out_a(a30_7to30_8), .out_b(b30_7to31_7), .out_c(matrixC30_7)); +processing_element pe30_8(.reset(effective_rst), .clk(clk), .in_a(a30_7to30_8), .in_b(b29_8to30_8), .out_a(a30_8to30_9), .out_b(b30_8to31_8), .out_c(matrixC30_8)); +processing_element pe30_9(.reset(effective_rst), .clk(clk), .in_a(a30_8to30_9), .in_b(b29_9to30_9), .out_a(a30_9to30_10), .out_b(b30_9to31_9), .out_c(matrixC30_9)); +processing_element pe30_10(.reset(effective_rst), .clk(clk), .in_a(a30_9to30_10), .in_b(b29_10to30_10), .out_a(a30_10to30_11), .out_b(b30_10to31_10), .out_c(matrixC30_10)); +processing_element pe30_11(.reset(effective_rst), .clk(clk), .in_a(a30_10to30_11), .in_b(b29_11to30_11), .out_a(a30_11to30_12), .out_b(b30_11to31_11), .out_c(matrixC30_11)); +processing_element pe30_12(.reset(effective_rst), .clk(clk), .in_a(a30_11to30_12), .in_b(b29_12to30_12), .out_a(a30_12to30_13), .out_b(b30_12to31_12), .out_c(matrixC30_12)); +processing_element pe30_13(.reset(effective_rst), .clk(clk), .in_a(a30_12to30_13), .in_b(b29_13to30_13), .out_a(a30_13to30_14), .out_b(b30_13to31_13), .out_c(matrixC30_13)); +processing_element pe30_14(.reset(effective_rst), .clk(clk), .in_a(a30_13to30_14), .in_b(b29_14to30_14), .out_a(a30_14to30_15), .out_b(b30_14to31_14), .out_c(matrixC30_14)); +processing_element pe30_15(.reset(effective_rst), .clk(clk), .in_a(a30_14to30_15), .in_b(b29_15to30_15), .out_a(a30_15to30_16), .out_b(b30_15to31_15), .out_c(matrixC30_15)); +processing_element pe30_16(.reset(effective_rst), .clk(clk), .in_a(a30_15to30_16), .in_b(b29_16to30_16), .out_a(a30_16to30_17), .out_b(b30_16to31_16), .out_c(matrixC30_16)); +processing_element pe30_17(.reset(effective_rst), .clk(clk), .in_a(a30_16to30_17), .in_b(b29_17to30_17), .out_a(a30_17to30_18), .out_b(b30_17to31_17), .out_c(matrixC30_17)); +processing_element pe30_18(.reset(effective_rst), .clk(clk), .in_a(a30_17to30_18), .in_b(b29_18to30_18), .out_a(a30_18to30_19), .out_b(b30_18to31_18), .out_c(matrixC30_18)); +processing_element pe30_19(.reset(effective_rst), .clk(clk), .in_a(a30_18to30_19), .in_b(b29_19to30_19), .out_a(a30_19to30_20), .out_b(b30_19to31_19), .out_c(matrixC30_19)); +processing_element pe30_20(.reset(effective_rst), .clk(clk), .in_a(a30_19to30_20), .in_b(b29_20to30_20), .out_a(a30_20to30_21), .out_b(b30_20to31_20), .out_c(matrixC30_20)); +processing_element pe30_21(.reset(effective_rst), .clk(clk), .in_a(a30_20to30_21), .in_b(b29_21to30_21), .out_a(a30_21to30_22), .out_b(b30_21to31_21), .out_c(matrixC30_21)); +processing_element pe30_22(.reset(effective_rst), .clk(clk), .in_a(a30_21to30_22), .in_b(b29_22to30_22), .out_a(a30_22to30_23), .out_b(b30_22to31_22), .out_c(matrixC30_22)); +processing_element pe30_23(.reset(effective_rst), .clk(clk), .in_a(a30_22to30_23), .in_b(b29_23to30_23), .out_a(a30_23to30_24), .out_b(b30_23to31_23), .out_c(matrixC30_23)); +processing_element pe30_24(.reset(effective_rst), .clk(clk), .in_a(a30_23to30_24), .in_b(b29_24to30_24), .out_a(a30_24to30_25), .out_b(b30_24to31_24), .out_c(matrixC30_24)); +processing_element pe30_25(.reset(effective_rst), .clk(clk), .in_a(a30_24to30_25), .in_b(b29_25to30_25), .out_a(a30_25to30_26), .out_b(b30_25to31_25), .out_c(matrixC30_25)); +processing_element pe30_26(.reset(effective_rst), .clk(clk), .in_a(a30_25to30_26), .in_b(b29_26to30_26), .out_a(a30_26to30_27), .out_b(b30_26to31_26), .out_c(matrixC30_26)); +processing_element pe30_27(.reset(effective_rst), .clk(clk), .in_a(a30_26to30_27), .in_b(b29_27to30_27), .out_a(a30_27to30_28), .out_b(b30_27to31_27), .out_c(matrixC30_27)); +processing_element pe30_28(.reset(effective_rst), .clk(clk), .in_a(a30_27to30_28), .in_b(b29_28to30_28), .out_a(a30_28to30_29), .out_b(b30_28to31_28), .out_c(matrixC30_28)); +processing_element pe30_29(.reset(effective_rst), .clk(clk), .in_a(a30_28to30_29), .in_b(b29_29to30_29), .out_a(a30_29to30_30), .out_b(b30_29to31_29), .out_c(matrixC30_29)); +processing_element pe30_30(.reset(effective_rst), .clk(clk), .in_a(a30_29to30_30), .in_b(b29_30to30_30), .out_a(a30_30to30_31), .out_b(b30_30to31_30), .out_c(matrixC30_30)); +processing_element pe30_31(.reset(effective_rst), .clk(clk), .in_a(a30_30to30_31), .in_b(b29_31to30_31), .out_a(a30_31to30_32), .out_b(b30_31to31_31), .out_c(matrixC30_31)); +processing_element_bottom_edge pe31_1(.reset(effective_rst), .clk(clk), .in_a(a31_0to31_1), .in_b(b30_1to31_1), .out_a(a31_1to31_2), .out_b(b31_1to32_1), .out_c(matrixC31_1)); +processing_element_bottom_edge pe31_2(.reset(effective_rst), .clk(clk), .in_a(a31_1to31_2), .in_b(b30_2to31_2), .out_a(a31_2to31_3), .out_b(b31_2to32_2), .out_c(matrixC31_2)); +processing_element_bottom_edge pe31_3(.reset(effective_rst), .clk(clk), .in_a(a31_2to31_3), .in_b(b30_3to31_3), .out_a(a31_3to31_4), .out_b(b31_3to32_3), .out_c(matrixC31_3)); +processing_element_bottom_edge pe31_4(.reset(effective_rst), .clk(clk), .in_a(a31_3to31_4), .in_b(b30_4to31_4), .out_a(a31_4to31_5), .out_b(b31_4to32_4), .out_c(matrixC31_4)); +processing_element_bottom_edge pe31_5(.reset(effective_rst), .clk(clk), .in_a(a31_4to31_5), .in_b(b30_5to31_5), .out_a(a31_5to31_6), .out_b(b31_5to32_5), .out_c(matrixC31_5)); +processing_element_bottom_edge pe31_6(.reset(effective_rst), .clk(clk), .in_a(a31_5to31_6), .in_b(b30_6to31_6), .out_a(a31_6to31_7), .out_b(b31_6to32_6), .out_c(matrixC31_6)); +processing_element_bottom_edge pe31_7(.reset(effective_rst), .clk(clk), .in_a(a31_6to31_7), .in_b(b30_7to31_7), .out_a(a31_7to31_8), .out_b(b31_7to32_7), .out_c(matrixC31_7)); +processing_element_bottom_edge pe31_8(.reset(effective_rst), .clk(clk), .in_a(a31_7to31_8), .in_b(b30_8to31_8), .out_a(a31_8to31_9), .out_b(b31_8to32_8), .out_c(matrixC31_8)); +processing_element_bottom_edge pe31_9(.reset(effective_rst), .clk(clk), .in_a(a31_8to31_9), .in_b(b30_9to31_9), .out_a(a31_9to31_10), .out_b(b31_9to32_9), .out_c(matrixC31_9)); +processing_element_bottom_edge pe31_10(.reset(effective_rst), .clk(clk), .in_a(a31_9to31_10), .in_b(b30_10to31_10), .out_a(a31_10to31_11), .out_b(b31_10to32_10), .out_c(matrixC31_10)); +processing_element_bottom_edge pe31_11(.reset(effective_rst), .clk(clk), .in_a(a31_10to31_11), .in_b(b30_11to31_11), .out_a(a31_11to31_12), .out_b(b31_11to32_11), .out_c(matrixC31_11)); +processing_element_bottom_edge pe31_12(.reset(effective_rst), .clk(clk), .in_a(a31_11to31_12), .in_b(b30_12to31_12), .out_a(a31_12to31_13), .out_b(b31_12to32_12), .out_c(matrixC31_12)); +processing_element_bottom_edge pe31_13(.reset(effective_rst), .clk(clk), .in_a(a31_12to31_13), .in_b(b30_13to31_13), .out_a(a31_13to31_14), .out_b(b31_13to32_13), .out_c(matrixC31_13)); +processing_element_bottom_edge pe31_14(.reset(effective_rst), .clk(clk), .in_a(a31_13to31_14), .in_b(b30_14to31_14), .out_a(a31_14to31_15), .out_b(b31_14to32_14), .out_c(matrixC31_14)); +processing_element_bottom_edge pe31_15(.reset(effective_rst), .clk(clk), .in_a(a31_14to31_15), .in_b(b30_15to31_15), .out_a(a31_15to31_16), .out_b(b31_15to32_15), .out_c(matrixC31_15)); +processing_element_bottom_edge pe31_16(.reset(effective_rst), .clk(clk), .in_a(a31_15to31_16), .in_b(b30_16to31_16), .out_a(a31_16to31_17), .out_b(b31_16to32_16), .out_c(matrixC31_16)); +processing_element_bottom_edge pe31_17(.reset(effective_rst), .clk(clk), .in_a(a31_16to31_17), .in_b(b30_17to31_17), .out_a(a31_17to31_18), .out_b(b31_17to32_17), .out_c(matrixC31_17)); +processing_element_bottom_edge pe31_18(.reset(effective_rst), .clk(clk), .in_a(a31_17to31_18), .in_b(b30_18to31_18), .out_a(a31_18to31_19), .out_b(b31_18to32_18), .out_c(matrixC31_18)); +processing_element_bottom_edge pe31_19(.reset(effective_rst), .clk(clk), .in_a(a31_18to31_19), .in_b(b30_19to31_19), .out_a(a31_19to31_20), .out_b(b31_19to32_19), .out_c(matrixC31_19)); +processing_element_bottom_edge pe31_20(.reset(effective_rst), .clk(clk), .in_a(a31_19to31_20), .in_b(b30_20to31_20), .out_a(a31_20to31_21), .out_b(b31_20to32_20), .out_c(matrixC31_20)); +processing_element_bottom_edge pe31_21(.reset(effective_rst), .clk(clk), .in_a(a31_20to31_21), .in_b(b30_21to31_21), .out_a(a31_21to31_22), .out_b(b31_21to32_21), .out_c(matrixC31_21)); +processing_element_bottom_edge pe31_22(.reset(effective_rst), .clk(clk), .in_a(a31_21to31_22), .in_b(b30_22to31_22), .out_a(a31_22to31_23), .out_b(b31_22to32_22), .out_c(matrixC31_22)); +processing_element_bottom_edge pe31_23(.reset(effective_rst), .clk(clk), .in_a(a31_22to31_23), .in_b(b30_23to31_23), .out_a(a31_23to31_24), .out_b(b31_23to32_23), .out_c(matrixC31_23)); +processing_element_bottom_edge pe31_24(.reset(effective_rst), .clk(clk), .in_a(a31_23to31_24), .in_b(b30_24to31_24), .out_a(a31_24to31_25), .out_b(b31_24to32_24), .out_c(matrixC31_24)); +processing_element_bottom_edge pe31_25(.reset(effective_rst), .clk(clk), .in_a(a31_24to31_25), .in_b(b30_25to31_25), .out_a(a31_25to31_26), .out_b(b31_25to32_25), .out_c(matrixC31_25)); +processing_element_bottom_edge pe31_26(.reset(effective_rst), .clk(clk), .in_a(a31_25to31_26), .in_b(b30_26to31_26), .out_a(a31_26to31_27), .out_b(b31_26to32_26), .out_c(matrixC31_26)); +processing_element_bottom_edge pe31_27(.reset(effective_rst), .clk(clk), .in_a(a31_26to31_27), .in_b(b30_27to31_27), .out_a(a31_27to31_28), .out_b(b31_27to32_27), .out_c(matrixC31_27)); +processing_element_bottom_edge pe31_28(.reset(effective_rst), .clk(clk), .in_a(a31_27to31_28), .in_b(b30_28to31_28), .out_a(a31_28to31_29), .out_b(b31_28to32_28), .out_c(matrixC31_28)); +processing_element_bottom_edge pe31_29(.reset(effective_rst), .clk(clk), .in_a(a31_28to31_29), .in_b(b30_29to31_29), .out_a(a31_29to31_30), .out_b(b31_29to32_29), .out_c(matrixC31_29)); +processing_element_bottom_edge pe31_30(.reset(effective_rst), .clk(clk), .in_a(a31_29to31_30), .in_b(b30_30to31_30), .out_a(a31_30to31_31), .out_b(b31_30to32_30), .out_c(matrixC31_30)); +processing_element_bottom_edge pe31_31(.reset(effective_rst), .clk(clk), .in_a(a31_30to31_31), .in_b(b30_31to31_31), .out_a(a31_31to31_32), .out_b(b31_31to32_31), .out_c(matrixC31_31)); +//assign a_data_out = {a31_31to31_32,a30_31to30_32,a29_31to29_32,a28_31to28_32,a27_31to27_32,a26_31to26_32,a25_31to25_32,a24_31to24_32,a23_31to23_32,a22_31to22_32,a21_31to21_32,a20_31to20_32,a19_31to19_32,a18_31to18_32,a17_31to17_32,a16_31to16_32,a15_31to15_32,a14_31to14_32,a13_31to13_32,a12_31to12_32,a11_31to11_32,a10_31to10_32,a9_31to9_32,a8_31to8_32,a7_31to7_32,a6_31to6_32,a5_31to5_32,a4_31to4_32,a3_31to3_32,a2_31to2_32,a1_31to1_32,a0_31to0_32}; +//assign b_data_out = {b31_31to32_31,b31_30to32_30,b31_29to32_29,b31_28to32_28,b31_27to32_27,b31_26to32_26,b31_25to32_25,b31_24to32_24,b31_23to32_23,b31_22to32_22,b31_21to32_21,b31_20to32_20,b31_19to32_19,b31_18to32_18,b31_17to32_17,b31_16to32_16,b31_15to32_15,b31_14to32_14,b31_13to32_13,b31_12to32_12,b31_11to32_11,b31_10to32_10,b31_9to32_9,b31_8to32_8,b31_7to32_7,b31_6to32_6,b31_5to32_5,b31_4to32_4,b31_3to32_3,b31_2to32_2,b31_1to32_1,b31_0to32_0}; + +endmodule + +module processing_element( + reset, + clk, + in_a, + in_b, + out_a, + out_b, + out_c + ); + +`ifdef complex_dsp + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [18:0] in_b; + output reg [`DWIDTH-1:0] out_a; + output [18:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + wire [18:0] scanout; + wire [63:0] chainout; //unconnected + wire [63:0] result; + wire [17:0] ax; + wire [18:0] ay; //unconnected + wire [35:0] bx; + wire [63:0] chainin; //unconnected + wire [18:0] scanin; + wire [11:0] mode_sigs; + + assign mode_sigs = 12'b010101010101; //Any value of mode_sigs (structural, not functional, correctness) + assign ax = {{(18-`DWIDTH){1'b0}}, in_a}; + //assign ay = {{(19-`DWIDTH){1'b0}}, in_b}; + assign bx = 36'b0; + assign scanin = in_b; + + //We will instantiate DSP slices with input chaining. + //Input chaining is only supported in the 18x19 mode or the 27x27 mode. + //We will use the input chain provided by the DSP for the B input. For A, the chain will be manual. + + mult_add_int_18x19 u_pe( + .clk(clk), + .reset(reset), + .mode_sigs(mode_sigs), + .ax(ax), + .ay(ay), + .bx(bx), + .chainin(chainin), + .scanin(scanin), + .result(result), + .chainout(chainout), + .scanout(scanout) + ); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + end + else begin + out_a<=in_a; + end + end + + assign out_b = scanout; + assign out_c = result[`DWIDTH-1:0]; + +`else + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [18:0] in_b; + output reg [`DWIDTH-1:0] out_a; + output reg [18:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + wire [`DWIDTH-1:0] out_mac; + + assign out_c = out_mac; + + seq_mac u_mac(.a(in_a), .b(in_b), .out(out_mac), .reset(reset), .clk(clk)); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + out_b<=0; + end + else begin + out_a<=in_a; + out_b<=in_b; + end + end + +`endif + +endmodule + +module processing_element_top_edge( + reset, + clk, + in_a, + in_b, + out_a, + out_b, + out_c + ); + +`ifdef complex_dsp + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [18:0] in_b; + output reg [`DWIDTH-1:0] out_a; + output [18:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + wire [18:0] scanout; + wire [63:0] chainout; //unconnected + wire [63:0] result; + wire [17:0] ax; + wire [18:0] ay; + wire [35:0] bx; + wire [63:0] chainin; //unconnected + wire [18:0] scanin; //unconnected + wire [11:0] mode_sigs; + + assign mode_sigs = 12'b010101010101; //Any value of mode_sigs (structural, not functional, correctness) + assign ax = {{(18-`DWIDTH){1'b0}}, in_a}; + assign ay = {{(19-`DWIDTH){1'b0}}, in_b}; + assign bx = 36'b0; + + //We will instantiate DSP slices with input chaining. + //Input chaining is only supported in the 18x19 mode or the 27x27 mode. + //We will use the input chain provided by the DSP for the B input. For A, the chain will be manual. + + mult_add_int_18x19 u_pe( + .clk(clk), + .reset(reset), + .mode_sigs(mode_sigs), + .ax(ax), + .ay(ay), + .bx(bx), + .chainin(chainin), + .scanin(scanin), + .result(result), + .chainout(chainout), + .scanout(scanout) + ); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + end + else begin + out_a<=in_a; + end + end + + assign out_b = scanout; + assign out_c = result[`DWIDTH-1:0]; + +`else + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [18:0] in_b; + output reg [`DWIDTH-1:0] out_a; + output reg [18:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + wire [`DWIDTH-1:0] out_mac; + + assign out_c = out_mac; + + seq_mac u_mac(.a(in_a), .b(in_b), .out(out_mac), .reset(reset), .clk(clk)); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + out_b<=0; + end + else begin + out_a<=in_a; + out_b<=in_b; + end + end + +`endif + +endmodule + +module processing_element_bottom_edge( + reset, + clk, + in_a, + in_b, + out_a, + out_b, + out_c + ); + +`ifdef complex_dsp + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [18:0] in_b; + output reg [`DWIDTH-1:0] out_a; + output [18:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + wire [18:0] scanout; //unconnected + wire [63:0] chainout; //unconnected + wire [63:0] result; + wire [17:0] ax; + wire [18:0] ay; //unconnected + wire [35:0] bx; + wire [63:0] chainin; //unconnected + wire [18:0] scanin; + wire [11:0] mode_sigs; + + assign mode_sigs = 12'b010101010101; //Any value of mode_sigs (structural, not functional, correctness) + assign ax = {{(18-`DWIDTH){1'b0}}, in_a}; + //assign ay = {{(19-`DWIDTH){1'b0}}, in_b}; + assign bx = 36'b0; + assign scanin = in_b; + + //We will instantiate DSP slices with input chaining. + //Input chaining is only supported in the 18x19 mode or the 27x27 mode. + //We will use the input chain provided by the DSP for the B input. For A, the chain will be manual. + + mult_add_int_18x19 u_pe( + .clk(clk), + .reset(reset), + .mode_sigs(mode_sigs), + .ax(ax), + .ay(ay), + .bx(bx), + .chainin(chainin), + .scanin(scanin), + .result(result), + .chainout(chainout), + .scanout(scanout) + ); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + end + else begin + out_a<=in_a; + end + end + + //assign out_b = scanout; + assign out_c = result[`DWIDTH-1:0]; + +`else + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [18:0] in_b; + output reg [`DWIDTH-1:0] out_a; + output reg [18:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + wire [`DWIDTH-1:0] out_mac; + + assign out_c = out_mac; + + seq_mac u_mac(.a(in_a), .b(in_b), .out(out_mac), .reset(reset), .clk(clk)); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + out_b<=0; + end + else begin + out_a<=in_a; + out_b<=in_b; + end + end + +`endif + +endmodule + +`ifndef complex_dsp +module seq_mac(a, b, out, reset, clk); +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +input reset; +input clk; +output [`DWIDTH-1:0] out; + +reg [2*`DWIDTH-1:0] out_temp; +wire [`DWIDTH-1:0] mul_out; +wire [2*`DWIDTH-1:0] add_out; + +reg [`DWIDTH-1:0] a_flopped; +reg [`DWIDTH-1:0] b_flopped; + +wire [2*`DWIDTH-1:0] mul_out_temp; +reg [2*`DWIDTH-1:0] mul_out_temp_reg; + +always @(posedge clk) begin + a_flopped <= a; + b_flopped <= b; +end + +//assign mul_out = a * b; +qmult mult_u1(.i_multiplicand(a_flopped), .i_multiplier(b_flopped), .o_result(mul_out_temp)); + +always @(posedge clk) begin + mul_out_temp_reg <= mul_out_temp; +end + +//we just truncate the higher bits of the product +//assign add_out = mul_out + out; +qadd add_u1(.a(out_temp), .b(mul_out_temp_reg), .c(add_out)); + +always @(posedge clk) begin + out_temp <= add_out; +end + +//down cast the result +assign out = + (out_temp[2*`DWIDTH-1] == 0) ? //positive number + ( + (|(out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 1, that means overlfow + {out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b1}}} : //sign bit and then all 1s + {out_temp[2*`DWIDTH-1] , out_temp[`DWIDTH-2:0]} + ) + : //negative number + ( + (|(out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 0, that means overlfow + {out_temp[2*`DWIDTH-1] , out_temp[`DWIDTH-2:0]} : + {out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b0}}} //sign bit and then all 0s + ); + +endmodule + +module qmult(i_multiplicand,i_multiplier,o_result); +input [`DWIDTH-1:0] i_multiplicand; +input [`DWIDTH-1:0] i_multiplier; +output [2*`DWIDTH-1:0] o_result; + +assign o_result = i_multiplicand * i_multiplier; +//DW02_mult #(`DWIDTH,`DWIDTH) u_mult(.A(i_multiplicand), .B(i_multiplier), .TC(1'b1), .PRODUCT(o_result)); + +endmodule + +module qadd(a,b,c); +input [2*`DWIDTH-1:0] a; +input [2*`DWIDTH-1:0] b; +output [2*`DWIDTH-1:0] c; + +assign c = a + b; +//DW01_add #(`DWIDTH) u_add(.A(a), .B(b), .CI(1'b0), .SUM(c), .CO()); +endmodule +`endif + +////////////////////////////////////////////// +// Configuration block +////////////////////////////////////////////// + +module cfg( + input PCLK, + input PRESETn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output reg [`REG_DATAWIDTH-1:0] PRDATA, + output reg PREADY, + output reg start_tpu, + output reg enable_matmul, + output reg enable_norm, + output reg enable_pool, + output reg enable_activation, + output reg enable_conv_mode, + output reg [`DWIDTH-1:0] mean, + output reg [`DWIDTH-1:0] inv_var, + output reg [`MAX_BITS_POOL-1:0] pool_window_size, + output reg [`AWIDTH-1:0] address_mat_a, + output reg [`AWIDTH-1:0] address_mat_b, + output reg [`AWIDTH-1:0] address_mat_c, + output reg [`MASK_WIDTH-1:0] validity_mask_a_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_a_cols, + output reg [`MASK_WIDTH-1:0] validity_mask_b_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_b_cols, + output reg save_output_to_accum, + output reg add_accum_to_output, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c, + output reg activation_type, + output reg [3:0] conv_filter_height, + output reg [3:0] conv_filter_width, + output reg [3:0] conv_stride_horiz, + output reg [3:0] conv_stride_verti, + output reg [3:0] conv_padding_left, + output reg [3:0] conv_padding_right, + output reg [3:0] conv_padding_top, + output reg [3:0] conv_padding_bottom, + output reg [15:0] num_channels_inp, + output reg [15:0] num_channels_out, + output reg [15:0] inp_img_height, + output reg [15:0] inp_img_width, + output reg [15:0] out_img_height, + output reg [15:0] out_img_width, + output reg [31:0] batch_size, + output reg pe_reset, + input done_tpu +); + +//Dummy register to sync all other invalid/unimplemented addresses +reg [`REG_DATAWIDTH-1:0] reg_dummy; + + +////////////////////////////////////////////////////// +//Using a simple APB interface. Taken from: +// https://github.com/maomran/APB-Slave +// https://research.ijcaonline.org/volume95/number21/pxc3897047.pdf + +reg [1:0] State; +`define IDLE 2'b00 +`define W_ENABLE 2'b01 +`define R_ENABLE 2'b10 + +always @(posedge PCLK) begin + if (PRESETn == 0) begin + State <= `IDLE; + PRDATA <= 0; + PREADY <= 0; + start_tpu <= 0; + enable_matmul <= 0; + enable_norm <= 0; + enable_pool <= 0; + enable_activation <= 0; + mean <= 0; + inv_var <= 0; + pool_window_size <= 1; + reg_dummy <= 0; + address_mat_a <= 0; + address_mat_b <= 0; + address_mat_c <= 0; + validity_mask_a_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_a_cols <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_cols <= {`MASK_WIDTH{1'b1}}; + save_output_to_accum <= 0; + add_accum_to_output <= 0; + address_stride_a <= `DESIGN_SIZE; + address_stride_b <= `DESIGN_SIZE; + address_stride_c <= `DESIGN_SIZE; + activation_type <= 1; + conv_filter_height <= 2; + conv_filter_width <= 2; + conv_stride_horiz <= 1; + conv_stride_verti <= 1; + conv_padding_left <= 0; + conv_padding_right <= 0; + conv_padding_top <= 0; + conv_padding_bottom<= 0; + num_channels_inp <= 4; + num_channels_out <= 4; + inp_img_height <= 8; + inp_img_width <= 8; + out_img_height <= 7; + out_img_width <= 7; + batch_size <= 2; + enable_conv_mode <= 0; + pe_reset <= 0; + end + + else begin + case (State) + `IDLE : begin + PRDATA <= 0; + if (PSEL) begin + if (PWRITE) begin + State <= `W_ENABLE; + end + else begin + State <= `R_ENABLE; + end + end + PREADY <= 0; + pe_reset <= 0; //this register bit auto resets itself + end + + `W_ENABLE : begin + if (PSEL && PWRITE && PENABLE) begin + case (PADDR) + `REG_ENABLES_ADDR : begin + enable_conv_mode <= PWDATA[31]; + enable_activation <= PWDATA[3]; + enable_pool <= PWDATA[2]; + enable_norm <= PWDATA[1]; + enable_matmul <= PWDATA[0]; + end + `REG_STDN_TPU_ADDR : begin + start_tpu <= PWDATA[0]; + pe_reset <= PWDATA[15]; + end + `REG_MEAN_ADDR : mean <= PWDATA[`DWIDTH-1:0]; + `REG_INV_VAR_ADDR : inv_var <= PWDATA[`DWIDTH-1:0]; + `REG_MATRIX_A_ADDR : address_mat_a <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_B_ADDR : address_mat_b <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_C_ADDR : address_mat_c <= PWDATA[`AWIDTH-1:0]; + `REG_VALID_MASK_A_ROWS_ADDR: begin + validity_mask_a_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_A_COLS_ADDR: begin + validity_mask_a_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_ROWS_ADDR: begin + validity_mask_b_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_COLS_ADDR: begin + validity_mask_b_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_POOL_WINDOW_ADDR: pool_window_size <= PWDATA[`MAX_BITS_POOL-1:0]; + `REG_ACCUM_ACTIONS_ADDR: begin + add_accum_to_output <= PWDATA[1]; + save_output_to_accum <= PWDATA[0]; + end + `REG_MATRIX_A_STRIDE_ADDR : address_stride_a <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_B_STRIDE_ADDR : address_stride_b <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_C_STRIDE_ADDR : address_stride_c <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_ACTIVATION_CSR_ADDR : activation_type <= PWDATA[0]; + `REG_CONV_PARAMS_1_ADDR : begin + conv_filter_height <= PWDATA[3:0]; + conv_filter_width <= PWDATA[7:4]; + conv_stride_horiz <= PWDATA[11:8]; + conv_stride_verti <= PWDATA[15:12]; + conv_padding_left <= PWDATA[19:16]; + conv_padding_right <= PWDATA[23:20]; + conv_padding_top <= PWDATA[27:24]; + conv_padding_bottom<= PWDATA[31:28]; + end + `REG_CONV_PARAMS_2_ADDR : begin + num_channels_inp <= PWDATA[15:0]; + num_channels_out <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_3_ADDR : begin + inp_img_height <= PWDATA[15:0]; + inp_img_width <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_4_ADDR : begin + out_img_height <= PWDATA[15:0]; + out_img_width <= PWDATA[31:16]; + end + `REG_BATCH_SIZE_ADDR : batch_size <= PWDATA[31:0]; + default: reg_dummy <= PWDATA; //sink writes to a dummy register + endcase + PREADY <=1; + end + State <= `IDLE; + end + + `R_ENABLE : begin + if (PSEL && !PWRITE && PENABLE) begin + PREADY <= 1; + case (PADDR) + `REG_ENABLES_ADDR : PRDATA <= {28'b0, enable_activation, enable_pool, enable_norm, enable_matmul}; + `REG_STDN_TPU_ADDR : PRDATA <= {done_tpu, 30'b0, start_tpu}; + `REG_MEAN_ADDR : PRDATA <= mean; + `REG_INV_VAR_ADDR : PRDATA <= inv_var; + `REG_MATRIX_A_ADDR : PRDATA <= address_mat_a; + `REG_MATRIX_B_ADDR : PRDATA <= address_mat_b; + `REG_MATRIX_C_ADDR : PRDATA <= address_mat_c; + `REG_VALID_MASK_A_ROWS_ADDR: PRDATA <= validity_mask_a_rows; + `REG_VALID_MASK_A_COLS_ADDR: PRDATA <= validity_mask_a_cols; + `REG_VALID_MASK_B_ROWS_ADDR: PRDATA <= validity_mask_b_rows; + `REG_VALID_MASK_B_COLS_ADDR: PRDATA <= validity_mask_b_cols; + `REG_POOL_WINDOW_ADDR : PRDATA <= pool_window_size; + `REG_ACCUM_ACTIONS_ADDR: PRDATA <= {30'b0, add_accum_to_output, save_output_to_accum}; + `REG_MATRIX_A_STRIDE_ADDR : PRDATA <= address_stride_a; + `REG_MATRIX_B_STRIDE_ADDR : PRDATA <= address_stride_b; + `REG_MATRIX_C_STRIDE_ADDR : PRDATA <= address_stride_c; + `REG_ACTIVATION_CSR_ADDR : PRDATA <= {31'b0, activation_type}; + `REG_CONV_PARAMS_1_ADDR : PRDATA <= { + conv_filter_height, + conv_filter_width, + conv_stride_horiz, + conv_stride_verti, + conv_padding_left, + conv_padding_right, + conv_padding_top, + conv_padding_bottom + }; + `REG_CONV_PARAMS_2_ADDR : PRDATA <= { + num_channels_inp, + num_channels_out + }; + `REG_CONV_PARAMS_3_ADDR : PRDATA <= { + inp_img_height, + inp_img_width + }; + `REG_CONV_PARAMS_4_ADDR : PRDATA <= { + out_img_height, + out_img_width + }; + `REG_BATCH_SIZE_ADDR : PRDATA <= batch_size; + default : PRDATA <= reg_dummy; //read the dummy register for undefined addresses + endcase + end + State <= `IDLE; + end + default: begin + State <= `IDLE; + end + endcase + end +end + +endmodule + + +//////////////////////////////////////////////// +// Normalization block +//////////////////////////////////////////////// + +module norm( + input enable_norm, + input [`DWIDTH-1:0] mean, + input [`DWIDTH-1:0] inv_var, + input in_data_available, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_norm, + input clk, + input reset +); + +reg out_data_available_internal; +wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] mean_applied_data; +reg [`DESIGN_SIZE*`DWIDTH-1:0] variance_applied_data; +reg done_norm_internal; +reg norm_in_progress; +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +//Muxing logic to handle the case when this block is disabled +assign out_data_available = (enable_norm) ? out_data_available_internal : in_data_available_flopped; +assign out_data = (enable_norm) ? out_data_internal : inp_data_flopped; +assign done_norm = (enable_norm) ? done_norm_internal : 1'b1; + +//inp_data will have multiple elements in it. the number of elements is the same as size of the matmul. +//on each clock edge, if in_data_available is 1, then we will normalize the inputs. + +//the code uses the funky part-select syntax. example: +//wire [7:0] byteN = word[byte_num*8 +: 8]; +//byte_num*8 is the starting point. 8 is the width is the part-select (has to be constant).in_data_available +//+: indicates the part-select increases from the starting point +//-: indicates the part-select decreases from the starting point +//another example: +//loc = 3; +//PA[loc -:4] = PA[loc+1 +:4]; // equivalent to PA[3:0] = PA[7:4]; + +reg [31:0] cycle_count; +reg [31:0] i; +always @(posedge clk) begin + if ((reset || ~enable_norm)) begin + mean_applied_data <= 0; + variance_applied_data <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + done_norm_internal <= 0; + norm_in_progress <= 0; + in_data_available_flopped <= in_data_available; + inp_data_flopped <= inp_data; + end else if (in_data_available || norm_in_progress) begin + cycle_count <= cycle_count + 1; + //Let's apply mean and variance as the input data comes in. + //We have a pipeline here. First stage does the add (to apply the mean) + //and second stage does the multiplication (to apply the variance). + //Note: the following loop is not a loop across multiple columns of data. + //This loop will run in 2 cycle on the same column of data that comes into + //this module in 1 clock. + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if (validity_mask[i] == 1'b1) begin + mean_applied_data[i*`DWIDTH +: `DWIDTH] <= (inp_data[i*`DWIDTH +: `DWIDTH] - mean); + variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH] * inv_var); + end + else begin + mean_applied_data[i*`DWIDTH +: `DWIDTH] <= (inp_data[i*`DWIDTH +: `DWIDTH]); + variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH]); + end + end + + //Out data is available starting with the second clock cycle because + //in the first cycle, we only apply the mean. + if(cycle_count==2) begin + out_data_available_internal <= 1; + end + + //When we've normalized values N times, where N is the matmul + //size, that means we're done. But there is one additional cycle + //that is taken in the beginning (when we are applying the mean to the first + //column of data). We can call this the Initiation Interval of the pipeline. + //So, for a 4x4 matmul, this block takes 5 cycles. + if(cycle_count==(`DESIGN_SIZE+1)) begin + done_norm_internal <= 1'b1; + norm_in_progress <= 0; + end + else begin + norm_in_progress <= 1; + end + end + else begin + mean_applied_data <= 0; + variance_applied_data <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + done_norm_internal <= 0; + norm_in_progress <= 0; + end +end + +assign out_data_internal = variance_applied_data; + +endmodule + +////////////////////////////////// +// Dual port RAM +////////////////////////////////// + +module ram ( + addr0, + d0, + we0, + q0, + addr1, + d1, + we1, + q1, + clk); + +input [`AWIDTH-1:0] addr0; +input [`AWIDTH-1:0] addr1; +input [`DESIGN_SIZE*`DWIDTH-1:0] d0; +input [`DESIGN_SIZE*`DWIDTH-1:0] d1; +input [`DESIGN_SIZE-1:0] we0; +input [`DESIGN_SIZE-1:0] we1; +output [`DESIGN_SIZE*`DWIDTH-1:0] q0; +output [`DESIGN_SIZE*`DWIDTH-1:0] q1; +input clk; + +genvar i; + +generate +`ifdef QUARTUS + for (i=0;i<`DESIGN_SIZE;i=i+1) begin: gen_dp1 +`else + for (i=0;i<`DESIGN_SIZE;i=i+1) begin +`endif + dpram_original #(.AWIDTH(`AWIDTH),.DWIDTH(`DWIDTH),.NUM_WORDS(1<<`AWIDTH)) dp1 (.clk(clk),.address_a(addr0),.address_b(addr1),.wren_a(we0[i]),.wren_b(we1[i]),.data_a(d0[i*`DWIDTH +: `DWIDTH]),.data_b(d1[i*`DWIDTH +: `DWIDTH]),.out_a(q0[i*`DWIDTH +: `DWIDTH]),.out_b(q1[i*`DWIDTH +: `DWIDTH])); + end +endgenerate + + +endmodule + +module dpram_original ( + clk, + address_a, + address_b, + wren_a, + wren_b, + data_a, + data_b, + out_a, + out_b +); +parameter AWIDTH=10; +parameter NUM_WORDS=1024; +parameter DWIDTH=32; +input clk; +input [(AWIDTH-1):0] address_a; +input [(AWIDTH-1):0] address_b; +input wren_a; +input wren_b; +input [(DWIDTH-1):0] data_a; +input [(DWIDTH-1):0] data_b; +output reg [(DWIDTH-1):0] out_a; +output reg [(DWIDTH-1):0] out_b; + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram[NUM_WORDS-1:0]; +always @ (posedge clk) begin + if (wren_a) begin + ram[address_a] <= data_a; + end + else begin + out_a <= ram[address_a]; + end +end + +always @ (posedge clk) begin + if (wren_b) begin + ram[address_b] <= data_b; + end + else begin + out_b <= ram[address_b]; + end +end + +`else + +defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; +defparam u_dual_port_ram.DATA_WIDTH = DWIDTH; + +dual_port_ram u_dual_port_ram( +.addr1(address_a), +.we1(wren_a), +.data1(data_a), +.out1(out_a), +.addr2(address_b), +.we2(wren_b), +.data2(data_b), +.out2(out_b), +.clk(clk) +); + +`endif +endmodule + + +//////////////////////////////////////////////// +// Control unit +//////////////////////////////////////////////// + +module control( + input clk, + input reset, + input start_tpu, + input enable_matmul, + input enable_norm, + input enable_activation, + input enable_pool, + output reg start_mat_mul, + input done_mat_mul, + input done_norm, + input done_pool, + input done_activation, + input save_output_to_accum, + output reg done_tpu +); + +reg [3:0] state; + +`define STATE_INIT 4'b0000 +`define STATE_MATMUL 4'b0001 +`define STATE_NORM 4'b0010 +`define STATE_POOL 4'b0011 +`define STATE_ACTIVATION 4'b0100 +`define STATE_DONE 4'b0101 + +////////////////////////////////////////////////////// +// Assumption: We will always run matmul first. That is, matmul is not optional. +// The other blocks - norm, act, pool - are optional. +// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation +////////////////////////////////////////////////////// + +always @( posedge clk) begin + if (reset) begin + state <= `STATE_INIT; + start_mat_mul <= 1'b0; + done_tpu <= 1'b0; + end else begin + case (state) + `STATE_INIT: begin + if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin + if (enable_matmul == 1'b1) begin + start_mat_mul <= 1'b1; + state <= `STATE_MATMUL; + end + end + end + + //start_mat_mul is kinda used as a reset in some logic + //inside the matmul unit. So, we can't make it 0 right away after + //asserting it. + `STATE_MATMUL: begin + if (done_mat_mul == 1'b1) begin + start_mat_mul <= 1'b0; + if(save_output_to_accum) begin + state <= `STATE_DONE; + end + else if (enable_norm) begin + state <= `STATE_NORM; + end + else if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + else begin + start_mat_mul <= 1'b1; + end + end + + `STATE_NORM: begin + if (done_norm == 1'b1) begin + if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_POOL: begin + if (done_pool == 1'b1) begin + if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_ACTIVATION: begin + if (done_activation == 1'b1) begin + state <= `STATE_DONE; + end + end + + `STATE_DONE: begin + //We need to write start_tpu to 0 in the CFG block to get out of this state + if (start_tpu == 1'b0) begin + state <= `STATE_INIT; + done_tpu <= 0; + end + else begin + done_tpu <= 1; + end + end + endcase + end +end +endmodule + +//////////////////////////////////////////////// +// Pooling block +//////////////////////////////////////////////// + +module pool( + input enable_pool, + input in_data_available, + input [`MAX_BITS_POOL-1:0] pool_window_size, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_pool, + input clk, + input reset +); + +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +reg [`DESIGN_SIZE*`DWIDTH-1:0] out_data_temp; +reg done_pool_temp; +reg out_data_available_temp; +reg [31:0] i,j; +reg [31:0] cycle_count; + +always @(posedge clk) begin + if (reset || ~enable_pool || ~in_data_available) begin + out_data_temp <= 0; + done_pool_temp <= 0; + out_data_available_temp <= 0; + cycle_count <= 0; + in_data_available_flopped <= in_data_available; + inp_data_flopped <= inp_data; + end + + else if (in_data_available) begin + cycle_count <= cycle_count + 1; + out_data_available_temp <= 1; + + case (pool_window_size) + 1: begin + out_data_temp <= inp_data; + end + 2: begin + for (i = 0; i < `DESIGN_SIZE/2; i = i + 8) begin + out_data_temp[ i +: 8] <= (inp_data[i*2 +: 8] + inp_data[i*2 + 8 +: 8]) >> 1; + end + end + 4: begin + for (i = 0; i < `DESIGN_SIZE/4; i = i + 8) begin + //TODO: If 3 adders are the critical path, break into 2 cycles + out_data_temp[ i +: 8] <= (inp_data[i*4 +: 8] + inp_data[i*4 + 8 +: 8] + inp_data[i*4 + 16 +: 8] + inp_data[i*4 + 24 +: 8]) >> 2; + end + end + endcase + + if(cycle_count==`DESIGN_SIZE) begin + done_pool_temp <= 1'b1; + end + end +end + +assign out_data = enable_pool ? out_data_temp : inp_data_flopped; +assign out_data_available = enable_pool ? out_data_available_temp : in_data_available_flopped; +assign done_pool = enable_pool ? done_pool_temp : 1'b1; + +//Adding a dummy signal to use validity_mask input, to make ODIN happy +wire [`MASK_WIDTH-1:0] dummy; +assign dummy = validity_mask; + +endmodule + +//////////////////////////////////////////////// +// Activation block +//////////////////////////////////////////////// + +module activation( + input activation_type, + input enable_activation, + input in_data_available, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_activation, + input clk, + input reset +); + +reg done_activation_internal; +reg out_data_available_internal; +wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] slope_applied_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] intercept_applied_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] relu_applied_data_internal; +reg [31:0] i; +reg [31:0] cycle_count; +reg activation_in_progress; + +reg [(`DESIGN_SIZE*4)-1:0] address; +reg [(`DESIGN_SIZE*8)-1:0] data_slope; +reg [(`DESIGN_SIZE*8)-1:0] data_slope_flopped; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept_delayed; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept_flopped; + +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +always @(posedge clk) begin + if (reset) begin + inp_data_flopped <= 0; + data_slope_flopped <= 0; + end else begin + inp_data_flopped <= inp_data; + data_slope_flopped <= data_slope; + end +end + +// If the activation block is not enabled, just forward the input data +assign out_data = enable_activation ? out_data_internal : inp_data_flopped; +assign done_activation = enable_activation ? done_activation_internal : 1'b1; +assign out_data_available = enable_activation ? out_data_available_internal : in_data_available_flopped; + +always @(posedge clk) begin + if (reset || ~enable_activation) begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + data_intercept_flopped <= 0; + done_activation_internal <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + in_data_available_flopped <= in_data_available; + end else if(in_data_available || activation_in_progress) begin + cycle_count <= cycle_count + 1; + + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if(activation_type==1'b1) begin // tanH + slope_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= data_slope_flopped[i*8 +: 8] * inp_data_flopped[i*`DWIDTH +:`DWIDTH]; + data_intercept_flopped[i*8 +: 8] <= data_intercept[i*8 +: 8]; + data_intercept_delayed[i*8 +: 8] <= data_intercept_flopped[i*8 +: 8]; + intercept_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= slope_applied_data_internal[i*`DWIDTH +:`DWIDTH] + data_intercept_delayed[i*8 +: 8]; + end else begin // ReLU + relu_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= inp_data[i*`DWIDTH] ? {`DWIDTH{1'b0}} : inp_data[i*`DWIDTH +:`DWIDTH]; + end + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if (cycle_count==3) begin + out_data_available_internal <= 1; + end + end else begin + if (cycle_count==2) begin + out_data_available_internal <= 1; + end + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if(cycle_count==(`DESIGN_SIZE+2)) begin + done_activation_internal <= 1'b1; + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end else begin + if(cycle_count==(`DESIGN_SIZE+1)) begin + done_activation_internal <= 1'b1; + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end + end + else begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + data_intercept_flopped <= 0; + done_activation_internal <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + end +end + +assign out_data_internal = (activation_type) ? intercept_applied_data_internal : relu_applied_data_internal; + +//Our equation of tanh is Y=AX+B +//A is the slope and B is the intercept. +//We store A in one LUT and B in another. +//LUT for the slope +always @(address) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + case (address[i*4+:4]) + 4'b0000: data_slope[i*8+:8] = 8'd0; + 4'b0001: data_slope[i*8+:8] = 8'd0; + 4'b0010: data_slope[i*8+:8] = 8'd2; + 4'b0011: data_slope[i*8+:8] = 8'd3; + 4'b0100: data_slope[i*8+:8] = 8'd4; + 4'b0101: data_slope[i*8+:8] = 8'd0; + 4'b0110: data_slope[i*8+:8] = 8'd4; + 4'b0111: data_slope[i*8+:8] = 8'd3; + 4'b1000: data_slope[i*8+:8] = 8'd2; + 4'b1001: data_slope[i*8+:8] = 8'd0; + 4'b1010: data_slope[i*8+:8] = 8'd0; + default: data_slope[i*8+:8] = 8'd0; + endcase + end +end + +//LUT for the intercept +always @(address) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + case (address[i*4+:4]) + 4'b0000: data_intercept[i*8+:8] = 8'd127; + 4'b0001: data_intercept[i*8+:8] = 8'd99; + 4'b0010: data_intercept[i*8+:8] = 8'd46; + 4'b0011: data_intercept[i*8+:8] = 8'd18; + 4'b0100: data_intercept[i*8+:8] = 8'd0; + 4'b0101: data_intercept[i*8+:8] = 8'd0; + 4'b0110: data_intercept[i*8+:8] = 8'd0; + 4'b0111: data_intercept[i*8+:8] = -8'd18; + 4'b1000: data_intercept[i*8+:8] = -8'd46; + 4'b1001: data_intercept[i*8+:8] = -8'd99; + 4'b1010: data_intercept[i*8+:8] = -8'd127; + default: data_intercept[i*8+:8] = 8'd0; + endcase + end +end + +//Logic to find address +always @(inp_data) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if((inp_data[i*`DWIDTH +:`DWIDTH])>=90) begin + address[i*4+:4] = 4'b0000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=39 && (inp_data[i*`DWIDTH +:`DWIDTH])<90) begin + address[i*4+:4] = 4'b0001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=28 && (inp_data[i*`DWIDTH +:`DWIDTH])<39) begin + address[i*4+:4] = 4'b0010; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=16 && (inp_data[i*`DWIDTH +:`DWIDTH])<28) begin + address[i*4+:4] = 4'b0011; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=1 && (inp_data[i*`DWIDTH +:`DWIDTH])<16) begin + address[i*4+:4] = 4'b0100; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])==0) begin + address[i*4+:4] = 4'b0101; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-16 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-1) begin + address[i*4+:4] = 4'b0110; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-28 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-16) begin + address[i*4+:4] = 4'b0111; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-39 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-28) begin + address[i*4+:4] = 4'b1000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-90 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-39) begin + address[i*4+:4] = 4'b1001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])<=-90) begin + address[i*4+:4] = 4'b1010; + end + else begin + address[i*4+:4] = 4'b0101; + end + end +end + +//Adding a dummy signal to use validity_mask input, to make ODIN happy +//TODO: Need to correctly use validity_mask +wire [`MASK_WIDTH-1:0] dummy; +assign dummy = validity_mask; + +endmodule + + +////////////////////////////////////////////////////// +// Top module +////////////////////////////////////////////////////// + +module top( + input clk, + input clk_mem, + input reset, + input resetn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output [`REG_DATAWIDTH-1:0] PRDATA, + output PREADY, + input [`AWIDTH-1:0] bram_addr_a_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a_ext, + input [`DESIGN_SIZE-1:0] bram_we_a_ext, + input [`AWIDTH-1:0] bram_addr_b_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b_ext, + input [`DESIGN_SIZE-1:0] bram_we_b_ext +); + +wire [`AWIDTH-1:0] bram_addr_a; +wire [`AWIDTH-1:0] bram_addr_a_for_reading; +reg [`AWIDTH-1:0] bram_addr_a_for_writing; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a; +reg [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a; +wire [`DESIGN_SIZE-1:0] bram_we_a; +wire bram_en_a; +wire [`AWIDTH-1:0] bram_addr_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b; +wire [`DESIGN_SIZE-1:0] bram_we_b; +wire bram_en_b; +reg bram_a_wdata_available; +wire [`AWIDTH-1:0] bram_addr_c_NC; +wire start_tpu; +wire done_tpu; +wire start_mat_mul; +wire done_mat_mul; +wire norm_out_data_available; +wire done_norm; +wire pool_out_data_available; +wire done_pool; +wire activation_out_data_available; +wire done_activation; +wire enable_matmul; +wire enable_norm; +wire enable_activation; +wire enable_pool; +wire [`DESIGN_SIZE*`DWIDTH-1:0] matmul_c_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] norm_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] pool_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] activation_data_out; +wire matmul_c_data_available; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_in_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_in_NC; +wire [`DWIDTH-1:0] mean; +wire [`DWIDTH-1:0] inv_var; +wire [`AWIDTH-1:0] address_mat_a; +wire [`AWIDTH-1:0] address_mat_b; +wire [`AWIDTH-1:0] address_mat_c; +wire [`MASK_WIDTH-1:0] validity_mask_a_rows; +wire [`MASK_WIDTH-1:0] validity_mask_a_cols; +wire [`MASK_WIDTH-1:0] validity_mask_b_rows; +wire [`MASK_WIDTH-1:0] validity_mask_b_cols; +wire save_output_to_accum; +wire add_accum_to_output; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +wire [`MAX_BITS_POOL-1:0] pool_window_size; +wire activation_type; +wire [3:0] conv_filter_height; +wire [3:0] conv_filter_width; +wire [3:0] conv_stride_horiz; +wire [3:0] conv_stride_verti; +wire [3:0] conv_padding_left; +wire [3:0] conv_padding_right; +wire [3:0] conv_padding_top; +wire [3:0] conv_padding_bottom; +wire [15:0] num_channels_inp; +wire [15:0] num_channels_out; +wire [15:0] inp_img_height; +wire [15:0] inp_img_width; +wire [15:0] out_img_height; +wire [15:0] out_img_width; +wire [31:0] batch_size; +wire enable_conv_mode; +wire pe_reset; + +//Connections for bram a (activation/input matrix) +//bram_addr_a -> connected to u_matmul_4x4 +//bram_rdata_a -> connected to u_matmul_4x4 +//bram_wdata_a -> will come from the last block that is enabled +//bram_we_a -> will be 1 when the last block's data is available +//bram_en_a -> hardcoded to 1 +assign bram_addr_a = (bram_a_wdata_available) ? bram_addr_a_for_writing : bram_addr_a_for_reading; +assign bram_en_a = 1'b1; +assign bram_we_a = (bram_a_wdata_available) ? {`DESIGN_SIZE{1'b1}} : {`DESIGN_SIZE{1'b0}}; + +//Connections for bram b (weights matrix) +//bram_addr_b -> connected to u_matmul_4x4 +//bram_rdata_b -> connected to u_matmul_4x4 +//bram_wdata_b -> hardcoded to 0 (this block only reads from bram b) +//bram_we_b -> hardcoded to 0 (this block only reads from bram b) +//bram_en_b -> hardcoded to 1 +assign bram_wdata_b = {`DESIGN_SIZE*`DWIDTH{1'b0}}; +assign bram_en_b = 1'b1; +assign bram_we_b = {`DESIGN_SIZE{1'b0}}; + +//////////////////////////////////////////////////////////////// +// BRAM matrix A (inputs/activations) +//////////////////////////////////////////////////////////////// +ram matrix_A ( + .addr0(bram_addr_a), + .d0(bram_wdata_a), + .we0(bram_we_a), + .q0(bram_rdata_a), + .addr1(bram_addr_a_ext), + .d1(bram_wdata_a_ext), + .we1(bram_we_a_ext), + .q1(bram_rdata_a_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// BRAM matrix B (weights) +//////////////////////////////////////////////////////////////// +ram matrix_B ( + .addr0(bram_addr_b), + .d0(bram_wdata_b), + .we0(bram_we_b), + .q0(bram_rdata_b), + .addr1(bram_addr_b_ext), + .d1(bram_wdata_b_ext), + .we1(bram_we_b_ext), + .q1(bram_rdata_b_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// Control logic that directs all the operation +//////////////////////////////////////////////////////////////// +control u_control( + .clk(clk), + .reset(reset), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_activation(enable_activation), + .enable_pool(enable_pool), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .done_norm(done_norm), + .done_pool(done_pool), + .done_activation(done_activation), + .save_output_to_accum(save_output_to_accum), + .done_tpu(done_tpu) +); + +//////////////////////////////////////////////////////////////// +// Configuration (register) block +//////////////////////////////////////////////////////////////// +cfg u_cfg( + .PCLK(clk), + .PRESETn(resetn), + .PADDR(PADDR), + .PWRITE(PWRITE), + .PSEL(PSEL), + .PENABLE(PENABLE), + .PWDATA(PWDATA), + .PRDATA(PRDATA), + .PREADY(PREADY), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_pool(enable_pool), + .enable_activation(enable_activation), + .enable_conv_mode(enable_conv_mode), + .mean(mean), + .inv_var(inv_var), + .pool_window_size(pool_window_size), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols(validity_mask_a_cols), + .validity_mask_b_rows(validity_mask_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .save_output_to_accum(save_output_to_accum), + .add_accum_to_output(add_accum_to_output), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .activation_type(activation_type), + .conv_filter_height(conv_filter_height), + .conv_filter_width(conv_filter_width), + .conv_stride_horiz(conv_stride_horiz), + .conv_stride_verti(conv_stride_verti), + .conv_padding_left(conv_padding_left), + .conv_padding_right(conv_padding_right), + .conv_padding_top(conv_padding_top), + .conv_padding_bottom(conv_padding_bottom), + .num_channels_inp(num_channels_inp), + .num_channels_out(num_channels_out), + .inp_img_height(inp_img_height), + .inp_img_width(inp_img_width), + .out_img_height(out_img_height), + .out_img_width(out_img_width), + .batch_size(batch_size), + .pe_reset(pe_reset), + .done_tpu(done_tpu) +); + +//TODO: We want to move the data setup part +//and the interface to BRAM_A and BRAM_B outside +//into its own modules. For now, it is all inside +//the matmul block + +//////////////////////////////////////////////////////////////// +//Matrix multiplier +//Note: the ports on this module to write data to bram c +//are not used in this top module. +//////////////////////////////////////////////////////////////// +matmul_32x32_systolic u_matmul( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .a_data(bram_rdata_a), + .b_data(bram_rdata_b), + .a_data_in(a_data_in_NC), + .b_data_in(b_data_in_NC), + .c_data_in({`DESIGN_SIZE*`DWIDTH{1'b0}}), + .c_data_out(matmul_c_data_out), + .a_data_out(a_data_out_NC), + .b_data_out(b_data_out_NC), + .a_addr(bram_addr_a_for_reading), + .b_addr(bram_addr_b), + .c_addr(bram_addr_c_NC), + .c_data_available(matmul_c_data_available), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols(validity_mask_a_cols), + .validity_mask_b_rows(validity_mask_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .final_mat_mul_size(8'd32), + .a_loc(8'd0), + .b_loc(8'd0) +); + +//////////////////////////////////////////////////////////////// +// Normalization module +//////////////////////////////////////////////////////////////// +norm u_norm( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(matmul_c_data_available), + .inp_data(matmul_c_data_out), + .out_data(norm_data_out), + .out_data_available(norm_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_norm(done_norm), + .clk(clk), + .reset(reset) +); + +//////////////////////////////////////////////////////////////// +// Pooling module +//////////////////////////////////////////////////////////////// +pool u_pool( + .enable_pool(enable_pool), + .in_data_available(norm_out_data_available), + .pool_window_size(pool_window_size), + .inp_data(norm_data_out), + .out_data(pool_data_out), + .out_data_available(pool_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_pool(done_pool), + .clk(clk), + .reset(reset) +); + +//////////////////////////////////////////////////////////////// +// Activation module +//////////////////////////////////////////////////////////////// +activation u_activation( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(pool_out_data_available), + .inp_data(pool_data_out), + .out_data(activation_data_out), + .out_data_available(activation_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_activation(done_activation), + .clk(clk), + .reset(reset) +); + +//Interface to BRAM to write the output. +//Ideally, we could remove this flop stage. But then we'd +//have to generate the address for the output BRAM in each +//block that could potentially write the output. +always @(posedge clk) begin + if (reset) begin + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end + else if (activation_out_data_available) begin + bram_wdata_a <= activation_data_out; + bram_addr_a_for_writing <= bram_addr_a_for_writing - address_stride_c; + bram_a_wdata_available <= activation_out_data_available; + end + else begin + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end +end + +endmodule + + diff --git a/designs/koios/tpu_like.large.os/tpu_random.sv b/designs/koios/tpu_like.large.os/tpu_random.sv new file mode 100644 index 000000000..eaba760a0 --- /dev/null +++ b/designs/koios/tpu_like.large.os/tpu_random.sv @@ -0,0 +1,143 @@ +/* +Random I/Os for TPU +*/ + +`include "../../random_number_generator.sv" + +`define DWIDTH 8 + +//This is the size of the matrix multiplier unit. In this design, we have a systolic +//matrix multiplication unit that can multiply 32x32 matrix with a 32x32 matrix. +`define DESIGN_SIZE 32 +`define LOG2_DESIGN_SIZE 5 +`define MAT_MUL_SIZE 32 +`define MASK_WIDTH 32 +`define LOG2_MAT_MUL_SIZE 5 + +//This it the size of the address bus, or the depth of the RAM. Each location of +//the RAM is DWIDTH * MAT_MUL_SIZE wide. So, in this design, we use a total of +//1024 * 32 bytes of memory (i.e. 32 KB). +`define AWIDTH 10 + +//This is the number of clock cycles spent in the mac block +`define NUM_CYCLES_IN_MAC 3 + +//This defines the latency of accessing data from a block ram +`define MEM_ACCESS_LATENCY 1 + +//Data width and address width of the APB interface for registers +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 + +//Width of the stride for each column in the matrices (same as ram address width) +`define ADDR_STRIDE_WIDTH 16 + +//Number of bits to specify the pooling window. We support 3 sizes. +`define MAX_BITS_POOL 3 + +module tpu_random( + input wire logic clk, + input wire logic clk_mem, + input wire logic reset, + input wire logic resetn, + input wire logic [`REG_ADDRWIDTH-1:0] PADDR, + input wire logic PWRITE, + input wire logic PSEL, + input wire logic PENABLE, + input wire logic [`REG_DATAWIDTH-1:0] PWDATA, + output logic [`REG_DATAWIDTH-1:0] PRDATA, + output logic PREADY, + input wire logic [`AWIDTH-1:0] bram_addr_a_ext, + input wire logic [`DESIGN_SIZE-1:0] bram_we_a_ext, + input wire logic [`AWIDTH-1:0] bram_addr_b_ext, + input wire logic [`DESIGN_SIZE-1:0] bram_we_b_ext, + input wire logic [5:0] o_sel, + output logic [7:0] o_data +); + +logic [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a_ext; +logic [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b_ext; + +RandomNumberGenerator #( + .RANDOM_WIDTH(`DESIGN_SIZE*`DWIDTH), + .SEED(0) +) rng ( + .clk(clk), + .reset(reset), + .random_number(bram_wdata_a_ext) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(`DESIGN_SIZE*`DWIDTH), + .SEED(0) +) rng2 ( + .clk(clk), + .reset(reset), + .random_number(bram_wdata_b_ext) +); + +logic [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata[1:0]; + +always_comb begin + case(o_sel[5:1]) + 5'd0: o_data = bram_rdata[o_sel[0]][7:0]; + 5'd1: o_data = bram_rdata[o_sel[0]][15:8]; + 5'd2: o_data = bram_rdata[o_sel[0]][23:16]; + 5'd3: o_data = bram_rdata[o_sel[0]][31:24]; + 5'd4: o_data = bram_rdata[o_sel[0]][39:32]; + 5'd5: o_data = bram_rdata[o_sel[0]][47:40]; + 5'd6: o_data = bram_rdata[o_sel[0]][55:48]; + 5'd7: o_data = bram_rdata[o_sel[0]][63:56]; + 5'd8: o_data = bram_rdata[o_sel[0]][71:64]; + 5'd9: o_data = bram_rdata[o_sel[0]][79:72]; + 5'd10: o_data = bram_rdata[o_sel[0]][87:80]; + 5'd11: o_data = bram_rdata[o_sel[0]][95:88]; + 5'd12: o_data = bram_rdata[o_sel[0]][103:96]; + 5'd13: o_data = bram_rdata[o_sel[0]][111:104]; + 5'd14: o_data = bram_rdata[o_sel[0]][119:112]; + 5'd15: o_data = bram_rdata[o_sel[0]][127:120]; + 5'd16: o_data = bram_rdata[o_sel[0]][135:128]; + 5'd17: o_data = bram_rdata[o_sel[0]][143:136]; + 5'd18: o_data = bram_rdata[o_sel[0]][151:144]; + 5'd19: o_data = bram_rdata[o_sel[0]][159:152]; + 5'd20: o_data = bram_rdata[o_sel[0]][167:160]; + 5'd21: o_data = bram_rdata[o_sel[0]][175:168]; + 5'd22: o_data = bram_rdata[o_sel[0]][183:176]; + 5'd23: o_data = bram_rdata[o_sel[0]][191:184]; + 5'd24: o_data = bram_rdata[o_sel[0]][199:192]; + 5'd25: o_data = bram_rdata[o_sel[0]][207:200]; + 5'd26: o_data = bram_rdata[o_sel[0]][215:208]; + 5'd27: o_data = bram_rdata[o_sel[0]][223:216]; + 5'd28: o_data = bram_rdata[o_sel[0]][231:224]; + 5'd29: o_data = bram_rdata[o_sel[0]][239:232]; + 5'd30: o_data = bram_rdata[o_sel[0]][247:240]; + 5'd31: o_data = bram_rdata[o_sel[0]][255:248]; + default: o_data = 8'b0; + endcase +end + + + +top tpu0( + clk, + clk_mem, + reset, + resetn, + PADDR, + PWRITE, + PSEL, + PENABLE, + PWDATA, + PRDATA, + PREADY, + bram_addr_a_ext, + bram_rdata[0], + bram_wdata_a_ext, + bram_we_a_ext, + bram_addr_b_ext, + bram_rdata[1], + bram_wdata_b_ext, + bram_we_b_ext +); + +endmodule \ No newline at end of file diff --git a/designs/koios/tpu_like.large.ws/design.yaml b/designs/koios/tpu_like.large.ws/design.yaml new file mode 100644 index 000000000..fd07addb7 --- /dev/null +++ b/designs/koios/tpu_like.large.ws/design.yaml @@ -0,0 +1 @@ +top: tpu_random \ No newline at end of file diff --git a/designs/koios/tpu_like.large.ws/tpu_like.large.ws.v b/designs/koios/tpu_like.large.ws/tpu_like.large.ws.v new file mode 100644 index 000000000..54d0ada9a --- /dev/null +++ b/designs/koios/tpu_like.large.ws/tpu_like.large.ws.v @@ -0,0 +1,23768 @@ +`timescale 1ns/1ns +`define VCS +`define MATMUL_SIZE_32 +`define MORE_TESTS +`define DESIGN_SIZE_32 +`define SIMULATION +`define layer_test + +`define DWIDTH 8 +`define AWIDTH 11 +`define MEM_SIZE 2048 + +`ifdef MATMUL_SIZE_4 +`define MAT_MUL_SIZE 4 +`define MASK_WIDTH 4 +`define LOG2_MAT_MUL_SIZE 2 +`endif + +`ifdef MATMUL_SIZE_8 +`define MAT_MUL_SIZE 8 +`define MASK_WIDTH 8 +`define LOG2_MAT_MUL_SIZE 3 +`endif + +`ifdef MATMUL_SIZE_16 +`define MAT_MUL_SIZE 16 +`define MASK_WIDTH 16 +`define LOG2_MAT_MUL_SIZE 4 +`endif + +`ifdef MATMUL_SIZE_32 +`define MAT_MUL_SIZE 32 +`define MASK_WIDTH 32 +`define LOG2_MAT_MUL_SIZE 5 +`endif + +`ifdef DESIGN_SIZE_4 +`define DESIGN_SIZE 4 +`define LOG2_DESIGN_SIZE 2 +`endif + +`ifdef DESIGN_SIZE_8 +`define DESIGN_SIZE 8 +`define LOG2_DESIGN_SIZE 3 +`endif + +`ifdef DESIGN_SIZE_16 +`define DESIGN_SIZE 16 +`define LOG2_DESIGN_SIZE 4 +`endif + +`ifdef DESIGN_SIZE_32 +`define DESIGN_SIZE 32 +`define LOG2_DESIGN_SIZE 5 +`endif + +`define BB_MAT_MUL_SIZE `MAT_MUL_SIZE +`define NUM_CYCLES_IN_MAC 3 +`define MEM_ACCESS_LATENCY 1 +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 +`define ADDR_STRIDE_WIDTH 8 +`define MAX_BITS_POOL 3 + +///////////////////////////////////////////////// +//How to use fully-connected mode? +///////////////////////////////////////////////// +//TODO: See layer test and accum test and write documentation + +///////////////////////////////////////////////// +//How to use convolution mode? +///////////////////////////////////////////////// + +//Matrix A (input activation matrix) +//---------------------------------- +//* This matrix is the non-expanded matrix (ie. this contains +// the same number of elements as the input activation tensor). +// It doesn't contain the expanded GEMM M matrix corresponding +// to this convolution. +//* This matrix is expected to have been padded though. That is, +// if there are any padding rows/columns to be added, the software +// should do that and store the padded matrix in the BRAM. +//* Initial address of matrix A is to be programmed once in the +// beginning of calculation of each output tile. We don't have +// to reprogram the address of A every time during accumulation. +//* The register containing stride of the matrix A is not used +// in convolution mode. Address strides for each read are determined +// on the basis of C,R,S values internally in the RTL. This is because +// strides are not fixed. They vary for every read. +//* This matrix is laid out in NCHW format. + +//Matrix B (weight matrix) +//---------------------------------- +//* This matrix is the non-expanded matrix (ie. this contains +// the same number of elements as the weight tensor). +// It doesn't contain the expanded GEMM N matrix corresponding +// to this convolution. +//* There is no concept of padding for this matrix. +//* Initial address of matrix B is to be programmed once in the +// beginning of calculation of each output tile. We don't have +// to reprogram the address of B every time during accumulation. +//* The register containing stride of the matrix B is not used +// in the RTL. Address strides for each read are determined +// on the basis of C,R,S values internally in the RTL. +//* This matrix is laid out in NCHW format, but it is transposed. +// So technically, the format is WHCN. + +//Matrix C (output activation matrix) +//---------------------------------- +//* This matrix is the non-expanded matrix (ie. this contains +// the same number of elements as the output activation tensor). +// It contains the GEMM matrix corresponding +// to this convolution. +//* There is no concept of padding for this matrix. +//* Initial address of matrix C is to be programmed in the +// beginning of calculation of each output tile. +// There is no concept of programming the address of C for +// accumulation. We write the matrix C only after all accumulations +// have finished. +//* The register containing stride of the matrix C is not used +// in the RTL. That is because the stride is known and is equal to +// out_img_width * out_img_height, and RTL just uses that directly. +//* This matrix is laid out in NCHW format. + +///////////////////////////////////////////////// +//Register specification +///////////////////////////////////////////////// +//--------------------------------------- +//Addr 0 : Register with enables for various blocks. +//Includes mode of operation (convolution or fully_connected) +//--------------------------------------- +`define REG_ENABLES_ADDR 32'h0 +//Bit 0: enable_matmul +//Bit 1: enable_norm +//Bit 2: enable_pool +//Bit 3: enable_activation +//Bit 31: enable_conv_mode + +//--------------------------------------- +//Addr 4: Register that triggers the whole TPU +//--------------------------------------- +`define REG_STDN_TPU_ADDR 32'h4 +//Bit 0: start_tpu +//Bit 31: done_tpu + +//--------------------------------------- +//Addr 8: Register that stores the mean of the values +//--------------------------------------- +`define REG_MEAN_ADDR 32'h8 +//Bit 7:0: mean + +//--------------------------------------- +//Addr A: Register that stores the inverse variance of the values +//--------------------------------------- +`define REG_INV_VAR_ADDR 32'hA +//Bit 7:0: inv_var + +//--------------------------------------- +//Addr E: Register that stores the starting address of matrix A in BRAM A. +//In fully-connected mode, this register should be programmed with the +//address of the matrix being currently multiplied. That is, the +//address of the matrix of the matmul. So, this register will be +//programmed every time the matmul is kicked off during accumulation stages. +//Use the STRIDE registers to tell the matmul to increment addresses. +//In convolution mode, this register should be programmed with the +//address of the input activation matrix. No need to configure +//this every time the matmul is kicked off for accmulation. Just program it +//once it the beginning. Address increments are handled automatically . +//--------------------------------------- +`define REG_MATRIX_A_ADDR 32'he +//Bit `AWIDTH-1:0 address_mat_a + +//--------------------------------------- +//Addr 12: Register that stores the starting address of matrix B in BRAM B. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_B_ADDR 32'h12 +//Bit `AWIDTH-1:0 address_mat_b + +//--------------------------------------- +//Addr 16: Register that stores the starting address of matrix C in BRAM C. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_C_ADDR 32'h16 +//Bit `AWIDTH-1:0 address_mat_c + + + +//--------------------------------------- +//Addr 24: Register that controls the accumulation logic +//--------------------------------------- +`define REG_ACCUM_ACTIONS_ADDR 32'h24 +//Bit 0 save_output_to_accumulator +//Bit 1 add_accumulator_to_output + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 28: Register that stores the stride that should be taken to address +//elements in matrix A, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix A in the vertical +//direction. +//--------------------------------------- +`define REG_MATRIX_A_STRIDE_ADDR 32'h28 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_a + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 32: Register that stores the stride that should be taken to address +//elements in matrix B, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix B in the horizontal +//direction. +//--------------------------------------- +`define REG_MATRIX_B_STRIDE_ADDR 32'h32 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_b + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 36: Register that stores the stride that should be taken to address +//elements in matrix C, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix C in the vertical +//direction (this is generally same as address_stride_a). +//--------------------------------------- +`define REG_MATRIX_C_STRIDE_ADDR 32'h36 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_c + +//--------------------------------------- +//Addr 3A: Register that controls the activation block. Currently, the available +//settings are the selector of activation function that will be used. There are +//two options: ReLU and TanH. To use ReLU, clear the LSB of this register. To +//use TanH, set the LSB of this register. +//--------------------------------------- +`define REG_ACTIVATION_CSR_ADDR 32'h3A + +//--------------------------------------- +//Addr 3E: Register defining pooling window size +//--------------------------------------- +`define REG_POOL_WINDOW_ADDR 32'h3E +//Bit `MAX_BITS_POOL-1:0 pool window size + +//--------------------------------------- +//Addr 40: Register defining convolution parameters - 1 +//---------------------------------------- +`define REG_CONV_PARAMS_1_ADDR 32'h40 +//Bits filter_height (R) 3:0 +//Bits filter width (S) 7:4 +//Bits stride_horizontal 11:8 +//Bits stride_vertical 15:12 +//Bits pad_left 19:16 +//Bits pad_right 23:20 +//Bits pad_top 27:24 +//Bits pad_bottom 31:28 + +//--------------------------------------- +//Addr 44: Register defining convolution parameters - 2 +//---------------------------------------- +`define REG_CONV_PARAMS_2_ADDR 32'h44 +//Bits num_channels_input (C) 15:0 +//Bits num_channels_output (K) 31:16 + +//--------------------------------------- +//Addr 48: Register defining convolution parameters - 3 +//---------------------------------------- +`define REG_CONV_PARAMS_3_ADDR 32'h48 +//Bits input_image_height (H) 15:0 +//Bits input_image_width (W) 31:16 + +//--------------------------------------- +//Addr 4C: Register defining convolution parameters - 4 +//---------------------------------------- +`define REG_CONV_PARAMS_4_ADDR 32'h4C +//Bits output_image_height (P) 15:0 +//Bits output_image_width (Q) 31:16 + +//--------------------------------------- +//Addr 50: Register defining batch size +//---------------------------------------- +`define REG_BATCH_SIZE_ADDR 32'h50 +//Bits 31:0 batch_size (number of images, N) + +//--------------------------------------- +//Addresses 54,58,5C: Registers that stores the mask of which parts of the matrices are valid. +// +//Some examples where this is useful: +//1. Input matrix is smaller than the matmul. +// Say we want to multiply a 6x6 using an 8x8 matmul. +// The matmul still operates on the whole 8x8 part, so we need +// to ensure that there are 0s in the BRAMs in the invalid parts. +// But the mask is used by the blocks other than matmul. For ex, +// norm block will use the mask to avoid applying mean and variance +// to invalid parts (so tha they stay 0). +//2. When we start with large matrices, the size of the matrices can +// reduce to something less than the matmul size because of pooling. +// In that case for the next layer, we need to tell blocks like norm, +// what is valid and what is not. +// +//Note: This masks is applied to both x and y directions and also +//applied to both input matrices - A and B. +//--------------------------------------- +`define REG_VALID_MASK_A_ROWS_ADDR 32'h20 +`define REG_VALID_MASK_A_COLS_B_ROWS_ADDR 32'h54 +`define REG_VALID_MASK_B_COLS_ADDR 32'h58 +//Bit `MASK_WIDTH-1:0 validity_mask + +//--------------------------------------- +//Addr 60-64: Register defining number of design sized matrices +//that the input matrices can be divided into. +//---------------------------------------- +`define REG_NUM_MATRICES_A_ADDR 32'h60 +`define REG_NUM_MATRICES_B_ADDR 32'h64 + +//--------------------------------------- +//Addr 68: Register defining the pooling constants +//---------------------------------------- +`define REG_POOLING_ACCUM_ADDR 32'h68 + +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM generate_matmul.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + +module matmul_32x32_systolic( + clk, + reset, + pe_reset, + start_mat_mul, + done_mat_mul, + num_matrices_A, + num_matrices_B, + address_mat_a, + address_mat_b, + address_stride_a, + address_stride_b, + a_data, + b_data, + a_data_in, // Data values coming in from previous matmul - systolic connections + b_data_in, // Data values coming in from previous matmul - weight matrix + c_data_in, // Data values coming in from previous matmul - systolic shifting + c_data_out, // Data values going out to next matmul - systolic shifting + a_data_out, + b_data_out, + a_addr, + b_addr, + c_addr, + c_data_available, + matrixC31_0, + matrixC31_1, + matrixC31_2, + matrixC31_3, + matrixC31_4, + matrixC31_5, + matrixC31_6, + matrixC31_7, + matrixC31_8, + matrixC31_9, + matrixC31_10, + matrixC31_11, + matrixC31_12, + matrixC31_13, + matrixC31_14, + matrixC31_15, + matrixC31_16, + matrixC31_17, + matrixC31_18, + matrixC31_19, + matrixC31_20, + matrixC31_21, + matrixC31_22, + matrixC31_23, + matrixC31_24, + matrixC31_25, + matrixC31_26, + matrixC31_27, + matrixC31_28, + matrixC31_29, + matrixC31_30, + matrixC31_31, + validity_mask_a_rows, + validity_mask_a_cols_b_rows, + validity_mask_b_cols, + a_loc, + b_loc +); + +input clk; +input reset; +input pe_reset; +input start_mat_mul; +output done_mat_mul; +input [31:0] num_matrices_A; // Number of 32x32 matrices the input matrix can be divided into +input [31:0] num_matrices_B; // Number of 32x32 matrices the weight matrix can be divided into +input [`AWIDTH-1:0] address_mat_a; +input [`AWIDTH-1:0] address_mat_b; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; +output [`AWIDTH-1:0] a_addr; +output [`AWIDTH-1:0] b_addr; +output [`AWIDTH-1:0] c_addr; +output c_data_available; +output [`DWIDTH-1:0] matrixC31_0; +output [`DWIDTH-1:0] matrixC31_1; +output [`DWIDTH-1:0] matrixC31_2; +output [`DWIDTH-1:0] matrixC31_3; +output [`DWIDTH-1:0] matrixC31_4; +output [`DWIDTH-1:0] matrixC31_5; +output [`DWIDTH-1:0] matrixC31_6; +output [`DWIDTH-1:0] matrixC31_7; +output [`DWIDTH-1:0] matrixC31_8; +output [`DWIDTH-1:0] matrixC31_9; +output [`DWIDTH-1:0] matrixC31_10; +output [`DWIDTH-1:0] matrixC31_11; +output [`DWIDTH-1:0] matrixC31_12; +output [`DWIDTH-1:0] matrixC31_13; +output [`DWIDTH-1:0] matrixC31_14; +output [`DWIDTH-1:0] matrixC31_15; +output [`DWIDTH-1:0] matrixC31_16; +output [`DWIDTH-1:0] matrixC31_17; +output [`DWIDTH-1:0] matrixC31_18; +output [`DWIDTH-1:0] matrixC31_19; +output [`DWIDTH-1:0] matrixC31_20; +output [`DWIDTH-1:0] matrixC31_21; +output [`DWIDTH-1:0] matrixC31_22; +output [`DWIDTH-1:0] matrixC31_23; +output [`DWIDTH-1:0] matrixC31_24; +output [`DWIDTH-1:0] matrixC31_25; +output [`DWIDTH-1:0] matrixC31_26; +output [`DWIDTH-1:0] matrixC31_27; +output [`DWIDTH-1:0] matrixC31_28; +output [`DWIDTH-1:0] matrixC31_29; +output [`DWIDTH-1:0] matrixC31_30; +output [`DWIDTH-1:0] matrixC31_31; +input [`MASK_WIDTH-1:0] validity_mask_a_rows; +input [`MASK_WIDTH-1:0] validity_mask_a_cols_b_rows; +input [`MASK_WIDTH-1:0] validity_mask_b_cols; +input [63:0] a_loc; +input [63:0] b_loc; + +////////////////////////////////////////////////////////////////////////// +// Logic for clock counting and when to assert done +////////////////////////////////////////////////////////////////////////// + +reg done_mat_mul; +// This is set to 63 bits in accordance with the previous simulations. +// In general, a systolic multiplier takes 4*N-2+P cycles, where N is the size +// of the matmul and P is the number of pipeline stages in the MAC block. +reg [63:0] clk_cnt; + +// Finding out number of cycles to assert matmul done. +// When we have to save the outputs to accumulators, then we don't need to +// shift out data. So, we can assert done_mat_mul early. +// Note: the count expression used to contain "num_matrices_32x32*8", but +// to avoid multiplication, we now use "num_matrices_32x32 << 3" +wire [63:0] clk_cnt_for_done; +assign clk_cnt_for_done = +((num_matrices_A << (2*`LOG2_MAT_MUL_SIZE -1)) + 1 + `NUM_CYCLES_IN_MAC) ; + +always @(posedge clk) begin +if (reset || ~start_mat_mul) begin + clk_cnt <= 0; + done_mat_mul <= 0; +end +else if (clk_cnt == clk_cnt_for_done) begin + done_mat_mul <= 1; + clk_cnt <= clk_cnt + 1; +end +else if (done_mat_mul == 0) begin + clk_cnt <= clk_cnt + 1; +end +else begin + done_mat_mul <= 0; + clk_cnt <= clk_cnt + 1; +end +end + +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] a16_data; +wire [`DWIDTH-1:0] a17_data; +wire [`DWIDTH-1:0] a18_data; +wire [`DWIDTH-1:0] a19_data; +wire [`DWIDTH-1:0] a20_data; +wire [`DWIDTH-1:0] a21_data; +wire [`DWIDTH-1:0] a22_data; +wire [`DWIDTH-1:0] a23_data; +wire [`DWIDTH-1:0] a24_data; +wire [`DWIDTH-1:0] a25_data; +wire [`DWIDTH-1:0] a26_data; +wire [`DWIDTH-1:0] a27_data; +wire [`DWIDTH-1:0] a28_data; +wire [`DWIDTH-1:0] a29_data; +wire [`DWIDTH-1:0] a30_data; +wire [`DWIDTH-1:0] a31_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; +wire [`DWIDTH-1:0] b16_data; +wire [`DWIDTH-1:0] b17_data; +wire [`DWIDTH-1:0] b18_data; +wire [`DWIDTH-1:0] b19_data; +wire [`DWIDTH-1:0] b20_data; +wire [`DWIDTH-1:0] b21_data; +wire [`DWIDTH-1:0] b22_data; +wire [`DWIDTH-1:0] b23_data; +wire [`DWIDTH-1:0] b24_data; +wire [`DWIDTH-1:0] b25_data; +wire [`DWIDTH-1:0] b26_data; +wire [`DWIDTH-1:0] b27_data; +wire [`DWIDTH-1:0] b28_data; +wire [`DWIDTH-1:0] b29_data; +wire [`DWIDTH-1:0] b30_data; +wire [`DWIDTH-1:0] b31_data; +wire [`DWIDTH-1:0] a1_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_1; +wire [`DWIDTH-1:0] a3_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_1; +wire [`DWIDTH-1:0] a4_data_delayed_2; +wire [`DWIDTH-1:0] a4_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_1; +wire [`DWIDTH-1:0] a5_data_delayed_2; +wire [`DWIDTH-1:0] a5_data_delayed_3; +wire [`DWIDTH-1:0] a5_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_1; +wire [`DWIDTH-1:0] a6_data_delayed_2; +wire [`DWIDTH-1:0] a6_data_delayed_3; +wire [`DWIDTH-1:0] a6_data_delayed_4; +wire [`DWIDTH-1:0] a6_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_1; +wire [`DWIDTH-1:0] a7_data_delayed_2; +wire [`DWIDTH-1:0] a7_data_delayed_3; +wire [`DWIDTH-1:0] a7_data_delayed_4; +wire [`DWIDTH-1:0] a7_data_delayed_5; +wire [`DWIDTH-1:0] a7_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_1; +wire [`DWIDTH-1:0] a8_data_delayed_2; +wire [`DWIDTH-1:0] a8_data_delayed_3; +wire [`DWIDTH-1:0] a8_data_delayed_4; +wire [`DWIDTH-1:0] a8_data_delayed_5; +wire [`DWIDTH-1:0] a8_data_delayed_6; +wire [`DWIDTH-1:0] a8_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_1; +wire [`DWIDTH-1:0] a9_data_delayed_2; +wire [`DWIDTH-1:0] a9_data_delayed_3; +wire [`DWIDTH-1:0] a9_data_delayed_4; +wire [`DWIDTH-1:0] a9_data_delayed_5; +wire [`DWIDTH-1:0] a9_data_delayed_6; +wire [`DWIDTH-1:0] a9_data_delayed_7; +wire [`DWIDTH-1:0] a9_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_1; +wire [`DWIDTH-1:0] a10_data_delayed_2; +wire [`DWIDTH-1:0] a10_data_delayed_3; +wire [`DWIDTH-1:0] a10_data_delayed_4; +wire [`DWIDTH-1:0] a10_data_delayed_5; +wire [`DWIDTH-1:0] a10_data_delayed_6; +wire [`DWIDTH-1:0] a10_data_delayed_7; +wire [`DWIDTH-1:0] a10_data_delayed_8; +wire [`DWIDTH-1:0] a10_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_1; +wire [`DWIDTH-1:0] a11_data_delayed_2; +wire [`DWIDTH-1:0] a11_data_delayed_3; +wire [`DWIDTH-1:0] a11_data_delayed_4; +wire [`DWIDTH-1:0] a11_data_delayed_5; +wire [`DWIDTH-1:0] a11_data_delayed_6; +wire [`DWIDTH-1:0] a11_data_delayed_7; +wire [`DWIDTH-1:0] a11_data_delayed_8; +wire [`DWIDTH-1:0] a11_data_delayed_9; +wire [`DWIDTH-1:0] a11_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_1; +wire [`DWIDTH-1:0] a12_data_delayed_2; +wire [`DWIDTH-1:0] a12_data_delayed_3; +wire [`DWIDTH-1:0] a12_data_delayed_4; +wire [`DWIDTH-1:0] a12_data_delayed_5; +wire [`DWIDTH-1:0] a12_data_delayed_6; +wire [`DWIDTH-1:0] a12_data_delayed_7; +wire [`DWIDTH-1:0] a12_data_delayed_8; +wire [`DWIDTH-1:0] a12_data_delayed_9; +wire [`DWIDTH-1:0] a12_data_delayed_10; +wire [`DWIDTH-1:0] a12_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_1; +wire [`DWIDTH-1:0] a13_data_delayed_2; +wire [`DWIDTH-1:0] a13_data_delayed_3; +wire [`DWIDTH-1:0] a13_data_delayed_4; +wire [`DWIDTH-1:0] a13_data_delayed_5; +wire [`DWIDTH-1:0] a13_data_delayed_6; +wire [`DWIDTH-1:0] a13_data_delayed_7; +wire [`DWIDTH-1:0] a13_data_delayed_8; +wire [`DWIDTH-1:0] a13_data_delayed_9; +wire [`DWIDTH-1:0] a13_data_delayed_10; +wire [`DWIDTH-1:0] a13_data_delayed_11; +wire [`DWIDTH-1:0] a13_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_1; +wire [`DWIDTH-1:0] a14_data_delayed_2; +wire [`DWIDTH-1:0] a14_data_delayed_3; +wire [`DWIDTH-1:0] a14_data_delayed_4; +wire [`DWIDTH-1:0] a14_data_delayed_5; +wire [`DWIDTH-1:0] a14_data_delayed_6; +wire [`DWIDTH-1:0] a14_data_delayed_7; +wire [`DWIDTH-1:0] a14_data_delayed_8; +wire [`DWIDTH-1:0] a14_data_delayed_9; +wire [`DWIDTH-1:0] a14_data_delayed_10; +wire [`DWIDTH-1:0] a14_data_delayed_11; +wire [`DWIDTH-1:0] a14_data_delayed_12; +wire [`DWIDTH-1:0] a14_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_1; +wire [`DWIDTH-1:0] a15_data_delayed_2; +wire [`DWIDTH-1:0] a15_data_delayed_3; +wire [`DWIDTH-1:0] a15_data_delayed_4; +wire [`DWIDTH-1:0] a15_data_delayed_5; +wire [`DWIDTH-1:0] a15_data_delayed_6; +wire [`DWIDTH-1:0] a15_data_delayed_7; +wire [`DWIDTH-1:0] a15_data_delayed_8; +wire [`DWIDTH-1:0] a15_data_delayed_9; +wire [`DWIDTH-1:0] a15_data_delayed_10; +wire [`DWIDTH-1:0] a15_data_delayed_11; +wire [`DWIDTH-1:0] a15_data_delayed_12; +wire [`DWIDTH-1:0] a15_data_delayed_13; +wire [`DWIDTH-1:0] a15_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_15; +wire [`DWIDTH-1:0] a16_data_delayed_1; +wire [`DWIDTH-1:0] a16_data_delayed_2; +wire [`DWIDTH-1:0] a16_data_delayed_3; +wire [`DWIDTH-1:0] a16_data_delayed_4; +wire [`DWIDTH-1:0] a16_data_delayed_5; +wire [`DWIDTH-1:0] a16_data_delayed_6; +wire [`DWIDTH-1:0] a16_data_delayed_7; +wire [`DWIDTH-1:0] a16_data_delayed_8; +wire [`DWIDTH-1:0] a16_data_delayed_9; +wire [`DWIDTH-1:0] a16_data_delayed_10; +wire [`DWIDTH-1:0] a16_data_delayed_11; +wire [`DWIDTH-1:0] a16_data_delayed_12; +wire [`DWIDTH-1:0] a16_data_delayed_13; +wire [`DWIDTH-1:0] a16_data_delayed_14; +wire [`DWIDTH-1:0] a16_data_delayed_15; +wire [`DWIDTH-1:0] a16_data_delayed_16; +wire [`DWIDTH-1:0] a17_data_delayed_1; +wire [`DWIDTH-1:0] a17_data_delayed_2; +wire [`DWIDTH-1:0] a17_data_delayed_3; +wire [`DWIDTH-1:0] a17_data_delayed_4; +wire [`DWIDTH-1:0] a17_data_delayed_5; +wire [`DWIDTH-1:0] a17_data_delayed_6; +wire [`DWIDTH-1:0] a17_data_delayed_7; +wire [`DWIDTH-1:0] a17_data_delayed_8; +wire [`DWIDTH-1:0] a17_data_delayed_9; +wire [`DWIDTH-1:0] a17_data_delayed_10; +wire [`DWIDTH-1:0] a17_data_delayed_11; +wire [`DWIDTH-1:0] a17_data_delayed_12; +wire [`DWIDTH-1:0] a17_data_delayed_13; +wire [`DWIDTH-1:0] a17_data_delayed_14; +wire [`DWIDTH-1:0] a17_data_delayed_15; +wire [`DWIDTH-1:0] a17_data_delayed_16; +wire [`DWIDTH-1:0] a17_data_delayed_17; +wire [`DWIDTH-1:0] a18_data_delayed_1; +wire [`DWIDTH-1:0] a18_data_delayed_2; +wire [`DWIDTH-1:0] a18_data_delayed_3; +wire [`DWIDTH-1:0] a18_data_delayed_4; +wire [`DWIDTH-1:0] a18_data_delayed_5; +wire [`DWIDTH-1:0] a18_data_delayed_6; +wire [`DWIDTH-1:0] a18_data_delayed_7; +wire [`DWIDTH-1:0] a18_data_delayed_8; +wire [`DWIDTH-1:0] a18_data_delayed_9; +wire [`DWIDTH-1:0] a18_data_delayed_10; +wire [`DWIDTH-1:0] a18_data_delayed_11; +wire [`DWIDTH-1:0] a18_data_delayed_12; +wire [`DWIDTH-1:0] a18_data_delayed_13; +wire [`DWIDTH-1:0] a18_data_delayed_14; +wire [`DWIDTH-1:0] a18_data_delayed_15; +wire [`DWIDTH-1:0] a18_data_delayed_16; +wire [`DWIDTH-1:0] a18_data_delayed_17; +wire [`DWIDTH-1:0] a18_data_delayed_18; +wire [`DWIDTH-1:0] a19_data_delayed_1; +wire [`DWIDTH-1:0] a19_data_delayed_2; +wire [`DWIDTH-1:0] a19_data_delayed_3; +wire [`DWIDTH-1:0] a19_data_delayed_4; +wire [`DWIDTH-1:0] a19_data_delayed_5; +wire [`DWIDTH-1:0] a19_data_delayed_6; +wire [`DWIDTH-1:0] a19_data_delayed_7; +wire [`DWIDTH-1:0] a19_data_delayed_8; +wire [`DWIDTH-1:0] a19_data_delayed_9; +wire [`DWIDTH-1:0] a19_data_delayed_10; +wire [`DWIDTH-1:0] a19_data_delayed_11; +wire [`DWIDTH-1:0] a19_data_delayed_12; +wire [`DWIDTH-1:0] a19_data_delayed_13; +wire [`DWIDTH-1:0] a19_data_delayed_14; +wire [`DWIDTH-1:0] a19_data_delayed_15; +wire [`DWIDTH-1:0] a19_data_delayed_16; +wire [`DWIDTH-1:0] a19_data_delayed_17; +wire [`DWIDTH-1:0] a19_data_delayed_18; +wire [`DWIDTH-1:0] a19_data_delayed_19; +wire [`DWIDTH-1:0] a20_data_delayed_1; +wire [`DWIDTH-1:0] a20_data_delayed_2; +wire [`DWIDTH-1:0] a20_data_delayed_3; +wire [`DWIDTH-1:0] a20_data_delayed_4; +wire [`DWIDTH-1:0] a20_data_delayed_5; +wire [`DWIDTH-1:0] a20_data_delayed_6; +wire [`DWIDTH-1:0] a20_data_delayed_7; +wire [`DWIDTH-1:0] a20_data_delayed_8; +wire [`DWIDTH-1:0] a20_data_delayed_9; +wire [`DWIDTH-1:0] a20_data_delayed_10; +wire [`DWIDTH-1:0] a20_data_delayed_11; +wire [`DWIDTH-1:0] a20_data_delayed_12; +wire [`DWIDTH-1:0] a20_data_delayed_13; +wire [`DWIDTH-1:0] a20_data_delayed_14; +wire [`DWIDTH-1:0] a20_data_delayed_15; +wire [`DWIDTH-1:0] a20_data_delayed_16; +wire [`DWIDTH-1:0] a20_data_delayed_17; +wire [`DWIDTH-1:0] a20_data_delayed_18; +wire [`DWIDTH-1:0] a20_data_delayed_19; +wire [`DWIDTH-1:0] a20_data_delayed_20; +wire [`DWIDTH-1:0] a21_data_delayed_1; +wire [`DWIDTH-1:0] a21_data_delayed_2; +wire [`DWIDTH-1:0] a21_data_delayed_3; +wire [`DWIDTH-1:0] a21_data_delayed_4; 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+wire [`DWIDTH-1:0] b6_data_delayed_5; +wire [`DWIDTH-1:0] b6_data_delayed_6; +wire [`DWIDTH-1:0] b7_data_delayed_1; +wire [`DWIDTH-1:0] b7_data_delayed_2; +wire [`DWIDTH-1:0] b7_data_delayed_3; +wire [`DWIDTH-1:0] b7_data_delayed_4; +wire [`DWIDTH-1:0] b7_data_delayed_5; +wire [`DWIDTH-1:0] b7_data_delayed_6; +wire [`DWIDTH-1:0] b7_data_delayed_7; +wire [`DWIDTH-1:0] b8_data_delayed_1; +wire [`DWIDTH-1:0] b8_data_delayed_2; +wire [`DWIDTH-1:0] b8_data_delayed_3; +wire [`DWIDTH-1:0] b8_data_delayed_4; +wire [`DWIDTH-1:0] b8_data_delayed_5; +wire [`DWIDTH-1:0] b8_data_delayed_6; +wire [`DWIDTH-1:0] b8_data_delayed_7; +wire [`DWIDTH-1:0] b8_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_1; +wire [`DWIDTH-1:0] b9_data_delayed_2; +wire [`DWIDTH-1:0] b9_data_delayed_3; +wire [`DWIDTH-1:0] b9_data_delayed_4; +wire [`DWIDTH-1:0] b9_data_delayed_5; +wire [`DWIDTH-1:0] b9_data_delayed_6; +wire [`DWIDTH-1:0] b9_data_delayed_7; +wire [`DWIDTH-1:0] b9_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_1; +wire [`DWIDTH-1:0] b10_data_delayed_2; +wire [`DWIDTH-1:0] b10_data_delayed_3; +wire [`DWIDTH-1:0] b10_data_delayed_4; +wire [`DWIDTH-1:0] b10_data_delayed_5; +wire [`DWIDTH-1:0] b10_data_delayed_6; +wire [`DWIDTH-1:0] b10_data_delayed_7; +wire [`DWIDTH-1:0] b10_data_delayed_8; +wire [`DWIDTH-1:0] b10_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_1; +wire [`DWIDTH-1:0] b11_data_delayed_2; +wire [`DWIDTH-1:0] b11_data_delayed_3; +wire [`DWIDTH-1:0] b11_data_delayed_4; +wire [`DWIDTH-1:0] b11_data_delayed_5; +wire [`DWIDTH-1:0] b11_data_delayed_6; +wire [`DWIDTH-1:0] b11_data_delayed_7; +wire [`DWIDTH-1:0] b11_data_delayed_8; +wire [`DWIDTH-1:0] b11_data_delayed_9; +wire [`DWIDTH-1:0] b11_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_1; +wire [`DWIDTH-1:0] b12_data_delayed_2; +wire [`DWIDTH-1:0] b12_data_delayed_3; +wire [`DWIDTH-1:0] b12_data_delayed_4; +wire [`DWIDTH-1:0] b12_data_delayed_5; +wire [`DWIDTH-1:0] b12_data_delayed_6; +wire [`DWIDTH-1:0] b12_data_delayed_7; +wire [`DWIDTH-1:0] b12_data_delayed_8; +wire [`DWIDTH-1:0] b12_data_delayed_9; +wire [`DWIDTH-1:0] b12_data_delayed_10; +wire [`DWIDTH-1:0] b12_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_1; +wire [`DWIDTH-1:0] b13_data_delayed_2; +wire [`DWIDTH-1:0] b13_data_delayed_3; +wire [`DWIDTH-1:0] b13_data_delayed_4; +wire [`DWIDTH-1:0] b13_data_delayed_5; +wire [`DWIDTH-1:0] b13_data_delayed_6; +wire [`DWIDTH-1:0] b13_data_delayed_7; +wire [`DWIDTH-1:0] b13_data_delayed_8; +wire [`DWIDTH-1:0] b13_data_delayed_9; +wire [`DWIDTH-1:0] b13_data_delayed_10; +wire [`DWIDTH-1:0] b13_data_delayed_11; +wire [`DWIDTH-1:0] b13_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_1; +wire [`DWIDTH-1:0] b14_data_delayed_2; +wire [`DWIDTH-1:0] b14_data_delayed_3; +wire [`DWIDTH-1:0] b14_data_delayed_4; +wire [`DWIDTH-1:0] b14_data_delayed_5; +wire [`DWIDTH-1:0] b14_data_delayed_6; +wire [`DWIDTH-1:0] b14_data_delayed_7; +wire [`DWIDTH-1:0] b14_data_delayed_8; +wire [`DWIDTH-1:0] b14_data_delayed_9; +wire [`DWIDTH-1:0] b14_data_delayed_10; +wire [`DWIDTH-1:0] b14_data_delayed_11; +wire [`DWIDTH-1:0] b14_data_delayed_12; +wire [`DWIDTH-1:0] b14_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_1; +wire [`DWIDTH-1:0] b15_data_delayed_2; +wire [`DWIDTH-1:0] b15_data_delayed_3; +wire [`DWIDTH-1:0] b15_data_delayed_4; +wire [`DWIDTH-1:0] b15_data_delayed_5; +wire [`DWIDTH-1:0] b15_data_delayed_6; +wire [`DWIDTH-1:0] b15_data_delayed_7; +wire [`DWIDTH-1:0] b15_data_delayed_8; +wire [`DWIDTH-1:0] b15_data_delayed_9; +wire [`DWIDTH-1:0] b15_data_delayed_10; +wire [`DWIDTH-1:0] b15_data_delayed_11; +wire [`DWIDTH-1:0] b15_data_delayed_12; +wire [`DWIDTH-1:0] b15_data_delayed_13; +wire [`DWIDTH-1:0] b15_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_15; +wire [`DWIDTH-1:0] b16_data_delayed_1; +wire [`DWIDTH-1:0] b16_data_delayed_2; +wire [`DWIDTH-1:0] b16_data_delayed_3; +wire [`DWIDTH-1:0] b16_data_delayed_4; +wire [`DWIDTH-1:0] b16_data_delayed_5; +wire [`DWIDTH-1:0] b16_data_delayed_6; +wire [`DWIDTH-1:0] b16_data_delayed_7; +wire [`DWIDTH-1:0] b16_data_delayed_8; +wire [`DWIDTH-1:0] b16_data_delayed_9; +wire [`DWIDTH-1:0] b16_data_delayed_10; +wire [`DWIDTH-1:0] b16_data_delayed_11; +wire [`DWIDTH-1:0] b16_data_delayed_12; +wire [`DWIDTH-1:0] b16_data_delayed_13; +wire [`DWIDTH-1:0] b16_data_delayed_14; +wire [`DWIDTH-1:0] b16_data_delayed_15; +wire [`DWIDTH-1:0] b16_data_delayed_16; +wire [`DWIDTH-1:0] b17_data_delayed_1; +wire [`DWIDTH-1:0] b17_data_delayed_2; +wire [`DWIDTH-1:0] b17_data_delayed_3; +wire [`DWIDTH-1:0] b17_data_delayed_4; +wire [`DWIDTH-1:0] b17_data_delayed_5; +wire [`DWIDTH-1:0] b17_data_delayed_6; +wire [`DWIDTH-1:0] b17_data_delayed_7; +wire [`DWIDTH-1:0] b17_data_delayed_8; +wire [`DWIDTH-1:0] b17_data_delayed_9; +wire [`DWIDTH-1:0] b17_data_delayed_10; +wire [`DWIDTH-1:0] b17_data_delayed_11; +wire [`DWIDTH-1:0] b17_data_delayed_12; +wire [`DWIDTH-1:0] b17_data_delayed_13; +wire [`DWIDTH-1:0] b17_data_delayed_14; +wire [`DWIDTH-1:0] b17_data_delayed_15; +wire [`DWIDTH-1:0] b17_data_delayed_16; +wire [`DWIDTH-1:0] b17_data_delayed_17; +wire [`DWIDTH-1:0] b18_data_delayed_1; +wire [`DWIDTH-1:0] b18_data_delayed_2; +wire [`DWIDTH-1:0] b18_data_delayed_3; +wire [`DWIDTH-1:0] b18_data_delayed_4; +wire [`DWIDTH-1:0] b18_data_delayed_5; +wire [`DWIDTH-1:0] b18_data_delayed_6; +wire [`DWIDTH-1:0] b18_data_delayed_7; +wire [`DWIDTH-1:0] b18_data_delayed_8; +wire [`DWIDTH-1:0] b18_data_delayed_9; +wire [`DWIDTH-1:0] b18_data_delayed_10; +wire [`DWIDTH-1:0] b18_data_delayed_11; +wire [`DWIDTH-1:0] b18_data_delayed_12; +wire [`DWIDTH-1:0] b18_data_delayed_13; +wire [`DWIDTH-1:0] b18_data_delayed_14; +wire [`DWIDTH-1:0] b18_data_delayed_15; +wire [`DWIDTH-1:0] b18_data_delayed_16; +wire [`DWIDTH-1:0] b18_data_delayed_17; +wire [`DWIDTH-1:0] b18_data_delayed_18; +wire [`DWIDTH-1:0] b19_data_delayed_1; +wire [`DWIDTH-1:0] b19_data_delayed_2; +wire [`DWIDTH-1:0] b19_data_delayed_3; +wire [`DWIDTH-1:0] b19_data_delayed_4; +wire [`DWIDTH-1:0] b19_data_delayed_5; +wire [`DWIDTH-1:0] b19_data_delayed_6; +wire [`DWIDTH-1:0] b19_data_delayed_7; +wire [`DWIDTH-1:0] b19_data_delayed_8; +wire [`DWIDTH-1:0] b19_data_delayed_9; +wire [`DWIDTH-1:0] b19_data_delayed_10; +wire [`DWIDTH-1:0] b19_data_delayed_11; +wire [`DWIDTH-1:0] b19_data_delayed_12; +wire [`DWIDTH-1:0] b19_data_delayed_13; +wire [`DWIDTH-1:0] b19_data_delayed_14; +wire [`DWIDTH-1:0] b19_data_delayed_15; +wire [`DWIDTH-1:0] b19_data_delayed_16; +wire [`DWIDTH-1:0] b19_data_delayed_17; +wire [`DWIDTH-1:0] b19_data_delayed_18; +wire [`DWIDTH-1:0] b19_data_delayed_19; +wire [`DWIDTH-1:0] b20_data_delayed_1; +wire [`DWIDTH-1:0] b20_data_delayed_2; +wire [`DWIDTH-1:0] b20_data_delayed_3; +wire [`DWIDTH-1:0] b20_data_delayed_4; +wire [`DWIDTH-1:0] b20_data_delayed_5; +wire [`DWIDTH-1:0] b20_data_delayed_6; +wire [`DWIDTH-1:0] b20_data_delayed_7; +wire [`DWIDTH-1:0] b20_data_delayed_8; +wire [`DWIDTH-1:0] b20_data_delayed_9; +wire [`DWIDTH-1:0] b20_data_delayed_10; +wire [`DWIDTH-1:0] b20_data_delayed_11; +wire [`DWIDTH-1:0] b20_data_delayed_12; +wire [`DWIDTH-1:0] b20_data_delayed_13; +wire [`DWIDTH-1:0] b20_data_delayed_14; +wire [`DWIDTH-1:0] b20_data_delayed_15; +wire [`DWIDTH-1:0] b20_data_delayed_16; +wire [`DWIDTH-1:0] b20_data_delayed_17; +wire [`DWIDTH-1:0] b20_data_delayed_18; +wire [`DWIDTH-1:0] b20_data_delayed_19; +wire [`DWIDTH-1:0] b20_data_delayed_20; +wire [`DWIDTH-1:0] b21_data_delayed_1; +wire [`DWIDTH-1:0] b21_data_delayed_2; +wire [`DWIDTH-1:0] b21_data_delayed_3; +wire [`DWIDTH-1:0] b21_data_delayed_4; +wire [`DWIDTH-1:0] b21_data_delayed_5; +wire [`DWIDTH-1:0] b21_data_delayed_6; +wire [`DWIDTH-1:0] b21_data_delayed_7; +wire [`DWIDTH-1:0] b21_data_delayed_8; +wire [`DWIDTH-1:0] b21_data_delayed_9; +wire [`DWIDTH-1:0] b21_data_delayed_10; +wire [`DWIDTH-1:0] b21_data_delayed_11; +wire [`DWIDTH-1:0] b21_data_delayed_12; +wire [`DWIDTH-1:0] b21_data_delayed_13; +wire [`DWIDTH-1:0] b21_data_delayed_14; +wire [`DWIDTH-1:0] b21_data_delayed_15; +wire [`DWIDTH-1:0] b21_data_delayed_16; +wire [`DWIDTH-1:0] b21_data_delayed_17; +wire [`DWIDTH-1:0] b21_data_delayed_18; +wire [`DWIDTH-1:0] b21_data_delayed_19; +wire [`DWIDTH-1:0] b21_data_delayed_20; +wire [`DWIDTH-1:0] b21_data_delayed_21; +wire [`DWIDTH-1:0] b22_data_delayed_1; +wire [`DWIDTH-1:0] b22_data_delayed_2; +wire [`DWIDTH-1:0] b22_data_delayed_3; +wire [`DWIDTH-1:0] b22_data_delayed_4; +wire [`DWIDTH-1:0] b22_data_delayed_5; +wire [`DWIDTH-1:0] b22_data_delayed_6; +wire [`DWIDTH-1:0] b22_data_delayed_7; +wire [`DWIDTH-1:0] b22_data_delayed_8; +wire [`DWIDTH-1:0] b22_data_delayed_9; +wire [`DWIDTH-1:0] b22_data_delayed_10; +wire [`DWIDTH-1:0] b22_data_delayed_11; +wire [`DWIDTH-1:0] b22_data_delayed_12; +wire [`DWIDTH-1:0] b22_data_delayed_13; +wire [`DWIDTH-1:0] b22_data_delayed_14; +wire [`DWIDTH-1:0] b22_data_delayed_15; +wire [`DWIDTH-1:0] b22_data_delayed_16; +wire [`DWIDTH-1:0] b22_data_delayed_17; +wire [`DWIDTH-1:0] b22_data_delayed_18; +wire [`DWIDTH-1:0] b22_data_delayed_19; +wire [`DWIDTH-1:0] b22_data_delayed_20; +wire [`DWIDTH-1:0] b22_data_delayed_21; +wire [`DWIDTH-1:0] b22_data_delayed_22; +wire [`DWIDTH-1:0] b23_data_delayed_1; +wire [`DWIDTH-1:0] b23_data_delayed_2; +wire [`DWIDTH-1:0] b23_data_delayed_3; +wire [`DWIDTH-1:0] b23_data_delayed_4; +wire [`DWIDTH-1:0] b23_data_delayed_5; +wire [`DWIDTH-1:0] b23_data_delayed_6; +wire [`DWIDTH-1:0] b23_data_delayed_7; +wire [`DWIDTH-1:0] b23_data_delayed_8; +wire [`DWIDTH-1:0] b23_data_delayed_9; +wire [`DWIDTH-1:0] b23_data_delayed_10; +wire [`DWIDTH-1:0] b23_data_delayed_11; +wire [`DWIDTH-1:0] b23_data_delayed_12; +wire [`DWIDTH-1:0] b23_data_delayed_13; +wire [`DWIDTH-1:0] b23_data_delayed_14; +wire [`DWIDTH-1:0] b23_data_delayed_15; +wire [`DWIDTH-1:0] b23_data_delayed_16; +wire [`DWIDTH-1:0] b23_data_delayed_17; +wire [`DWIDTH-1:0] b23_data_delayed_18; +wire [`DWIDTH-1:0] b23_data_delayed_19; +wire [`DWIDTH-1:0] b23_data_delayed_20; +wire [`DWIDTH-1:0] b23_data_delayed_21; +wire [`DWIDTH-1:0] b23_data_delayed_22; +wire [`DWIDTH-1:0] b23_data_delayed_23; +wire [`DWIDTH-1:0] b24_data_delayed_1; +wire [`DWIDTH-1:0] b24_data_delayed_2; +wire [`DWIDTH-1:0] b24_data_delayed_3; +wire [`DWIDTH-1:0] b24_data_delayed_4; +wire [`DWIDTH-1:0] b24_data_delayed_5; +wire [`DWIDTH-1:0] b24_data_delayed_6; +wire [`DWIDTH-1:0] b24_data_delayed_7; +wire [`DWIDTH-1:0] b24_data_delayed_8; +wire [`DWIDTH-1:0] b24_data_delayed_9; +wire [`DWIDTH-1:0] b24_data_delayed_10; +wire [`DWIDTH-1:0] b24_data_delayed_11; +wire [`DWIDTH-1:0] b24_data_delayed_12; +wire [`DWIDTH-1:0] b24_data_delayed_13; +wire [`DWIDTH-1:0] b24_data_delayed_14; +wire [`DWIDTH-1:0] b24_data_delayed_15; +wire [`DWIDTH-1:0] b24_data_delayed_16; +wire [`DWIDTH-1:0] b24_data_delayed_17; +wire [`DWIDTH-1:0] b24_data_delayed_18; +wire [`DWIDTH-1:0] b24_data_delayed_19; +wire [`DWIDTH-1:0] b24_data_delayed_20; +wire [`DWIDTH-1:0] b24_data_delayed_21; +wire [`DWIDTH-1:0] b24_data_delayed_22; +wire [`DWIDTH-1:0] b24_data_delayed_23; +wire [`DWIDTH-1:0] b24_data_delayed_24; +wire [`DWIDTH-1:0] b25_data_delayed_1; +wire [`DWIDTH-1:0] b25_data_delayed_2; +wire [`DWIDTH-1:0] b25_data_delayed_3; +wire [`DWIDTH-1:0] b25_data_delayed_4; +wire [`DWIDTH-1:0] b25_data_delayed_5; +wire [`DWIDTH-1:0] b25_data_delayed_6; +wire [`DWIDTH-1:0] b25_data_delayed_7; +wire [`DWIDTH-1:0] b25_data_delayed_8; +wire [`DWIDTH-1:0] b25_data_delayed_9; +wire [`DWIDTH-1:0] b25_data_delayed_10; +wire [`DWIDTH-1:0] b25_data_delayed_11; +wire [`DWIDTH-1:0] b25_data_delayed_12; +wire [`DWIDTH-1:0] b25_data_delayed_13; +wire [`DWIDTH-1:0] b25_data_delayed_14; +wire [`DWIDTH-1:0] b25_data_delayed_15; +wire [`DWIDTH-1:0] b25_data_delayed_16; +wire [`DWIDTH-1:0] b25_data_delayed_17; +wire [`DWIDTH-1:0] b25_data_delayed_18; +wire [`DWIDTH-1:0] b25_data_delayed_19; +wire [`DWIDTH-1:0] b25_data_delayed_20; +wire [`DWIDTH-1:0] b25_data_delayed_21; +wire [`DWIDTH-1:0] b25_data_delayed_22; +wire [`DWIDTH-1:0] b25_data_delayed_23; +wire [`DWIDTH-1:0] b25_data_delayed_24; +wire [`DWIDTH-1:0] b25_data_delayed_25; +wire [`DWIDTH-1:0] b26_data_delayed_1; +wire [`DWIDTH-1:0] b26_data_delayed_2; +wire [`DWIDTH-1:0] b26_data_delayed_3; +wire [`DWIDTH-1:0] b26_data_delayed_4; +wire [`DWIDTH-1:0] b26_data_delayed_5; +wire [`DWIDTH-1:0] b26_data_delayed_6; +wire [`DWIDTH-1:0] b26_data_delayed_7; +wire [`DWIDTH-1:0] b26_data_delayed_8; +wire [`DWIDTH-1:0] b26_data_delayed_9; +wire [`DWIDTH-1:0] b26_data_delayed_10; +wire [`DWIDTH-1:0] b26_data_delayed_11; +wire [`DWIDTH-1:0] b26_data_delayed_12; +wire [`DWIDTH-1:0] b26_data_delayed_13; +wire [`DWIDTH-1:0] b26_data_delayed_14; +wire [`DWIDTH-1:0] b26_data_delayed_15; +wire [`DWIDTH-1:0] b26_data_delayed_16; +wire [`DWIDTH-1:0] b26_data_delayed_17; +wire [`DWIDTH-1:0] b26_data_delayed_18; +wire [`DWIDTH-1:0] b26_data_delayed_19; +wire [`DWIDTH-1:0] b26_data_delayed_20; +wire [`DWIDTH-1:0] b26_data_delayed_21; +wire [`DWIDTH-1:0] b26_data_delayed_22; +wire [`DWIDTH-1:0] b26_data_delayed_23; +wire [`DWIDTH-1:0] b26_data_delayed_24; +wire [`DWIDTH-1:0] b26_data_delayed_25; +wire [`DWIDTH-1:0] b26_data_delayed_26; +wire [`DWIDTH-1:0] b27_data_delayed_1; +wire [`DWIDTH-1:0] b27_data_delayed_2; +wire [`DWIDTH-1:0] b27_data_delayed_3; +wire [`DWIDTH-1:0] b27_data_delayed_4; +wire [`DWIDTH-1:0] b27_data_delayed_5; +wire [`DWIDTH-1:0] b27_data_delayed_6; +wire [`DWIDTH-1:0] b27_data_delayed_7; +wire [`DWIDTH-1:0] b27_data_delayed_8; +wire [`DWIDTH-1:0] b27_data_delayed_9; +wire [`DWIDTH-1:0] b27_data_delayed_10; +wire [`DWIDTH-1:0] b27_data_delayed_11; +wire [`DWIDTH-1:0] b27_data_delayed_12; +wire [`DWIDTH-1:0] b27_data_delayed_13; +wire [`DWIDTH-1:0] b27_data_delayed_14; +wire [`DWIDTH-1:0] b27_data_delayed_15; +wire [`DWIDTH-1:0] b27_data_delayed_16; +wire [`DWIDTH-1:0] b27_data_delayed_17; +wire [`DWIDTH-1:0] b27_data_delayed_18; +wire [`DWIDTH-1:0] b27_data_delayed_19; +wire [`DWIDTH-1:0] b27_data_delayed_20; +wire [`DWIDTH-1:0] b27_data_delayed_21; +wire [`DWIDTH-1:0] b27_data_delayed_22; +wire [`DWIDTH-1:0] b27_data_delayed_23; +wire [`DWIDTH-1:0] b27_data_delayed_24; +wire [`DWIDTH-1:0] b27_data_delayed_25; +wire [`DWIDTH-1:0] b27_data_delayed_26; +wire [`DWIDTH-1:0] b27_data_delayed_27; +wire [`DWIDTH-1:0] b28_data_delayed_1; +wire [`DWIDTH-1:0] b28_data_delayed_2; +wire [`DWIDTH-1:0] b28_data_delayed_3; +wire [`DWIDTH-1:0] b28_data_delayed_4; +wire [`DWIDTH-1:0] b28_data_delayed_5; +wire [`DWIDTH-1:0] b28_data_delayed_6; +wire [`DWIDTH-1:0] b28_data_delayed_7; +wire [`DWIDTH-1:0] b28_data_delayed_8; +wire [`DWIDTH-1:0] b28_data_delayed_9; +wire [`DWIDTH-1:0] b28_data_delayed_10; +wire [`DWIDTH-1:0] b28_data_delayed_11; +wire [`DWIDTH-1:0] b28_data_delayed_12; +wire [`DWIDTH-1:0] b28_data_delayed_13; +wire [`DWIDTH-1:0] b28_data_delayed_14; +wire [`DWIDTH-1:0] b28_data_delayed_15; +wire [`DWIDTH-1:0] b28_data_delayed_16; +wire [`DWIDTH-1:0] b28_data_delayed_17; +wire [`DWIDTH-1:0] b28_data_delayed_18; +wire [`DWIDTH-1:0] b28_data_delayed_19; +wire [`DWIDTH-1:0] b28_data_delayed_20; +wire [`DWIDTH-1:0] b28_data_delayed_21; +wire [`DWIDTH-1:0] b28_data_delayed_22; +wire [`DWIDTH-1:0] b28_data_delayed_23; +wire [`DWIDTH-1:0] b28_data_delayed_24; +wire [`DWIDTH-1:0] b28_data_delayed_25; +wire [`DWIDTH-1:0] b28_data_delayed_26; +wire [`DWIDTH-1:0] b28_data_delayed_27; +wire [`DWIDTH-1:0] b28_data_delayed_28; +wire [`DWIDTH-1:0] b29_data_delayed_1; +wire [`DWIDTH-1:0] b29_data_delayed_2; +wire [`DWIDTH-1:0] b29_data_delayed_3; +wire [`DWIDTH-1:0] b29_data_delayed_4; +wire [`DWIDTH-1:0] b29_data_delayed_5; +wire [`DWIDTH-1:0] b29_data_delayed_6; +wire [`DWIDTH-1:0] b29_data_delayed_7; +wire [`DWIDTH-1:0] b29_data_delayed_8; +wire [`DWIDTH-1:0] b29_data_delayed_9; +wire [`DWIDTH-1:0] b29_data_delayed_10; +wire [`DWIDTH-1:0] b29_data_delayed_11; +wire [`DWIDTH-1:0] b29_data_delayed_12; +wire [`DWIDTH-1:0] b29_data_delayed_13; +wire [`DWIDTH-1:0] b29_data_delayed_14; +wire [`DWIDTH-1:0] b29_data_delayed_15; +wire [`DWIDTH-1:0] b29_data_delayed_16; +wire [`DWIDTH-1:0] b29_data_delayed_17; +wire [`DWIDTH-1:0] b29_data_delayed_18; +wire [`DWIDTH-1:0] b29_data_delayed_19; +wire [`DWIDTH-1:0] b29_data_delayed_20; +wire [`DWIDTH-1:0] b29_data_delayed_21; +wire [`DWIDTH-1:0] b29_data_delayed_22; +wire [`DWIDTH-1:0] b29_data_delayed_23; +wire [`DWIDTH-1:0] b29_data_delayed_24; +wire [`DWIDTH-1:0] b29_data_delayed_25; +wire [`DWIDTH-1:0] b29_data_delayed_26; +wire [`DWIDTH-1:0] b29_data_delayed_27; +wire [`DWIDTH-1:0] b29_data_delayed_28; +wire [`DWIDTH-1:0] b29_data_delayed_29; +wire [`DWIDTH-1:0] b30_data_delayed_1; +wire [`DWIDTH-1:0] b30_data_delayed_2; +wire [`DWIDTH-1:0] b30_data_delayed_3; +wire [`DWIDTH-1:0] b30_data_delayed_4; +wire [`DWIDTH-1:0] b30_data_delayed_5; +wire [`DWIDTH-1:0] b30_data_delayed_6; +wire [`DWIDTH-1:0] b30_data_delayed_7; +wire [`DWIDTH-1:0] b30_data_delayed_8; +wire [`DWIDTH-1:0] b30_data_delayed_9; +wire [`DWIDTH-1:0] b30_data_delayed_10; +wire [`DWIDTH-1:0] b30_data_delayed_11; +wire [`DWIDTH-1:0] b30_data_delayed_12; +wire [`DWIDTH-1:0] b30_data_delayed_13; +wire [`DWIDTH-1:0] b30_data_delayed_14; +wire [`DWIDTH-1:0] b30_data_delayed_15; +wire [`DWIDTH-1:0] b30_data_delayed_16; +wire [`DWIDTH-1:0] b30_data_delayed_17; +wire [`DWIDTH-1:0] b30_data_delayed_18; +wire [`DWIDTH-1:0] b30_data_delayed_19; +wire [`DWIDTH-1:0] b30_data_delayed_20; +wire [`DWIDTH-1:0] b30_data_delayed_21; +wire [`DWIDTH-1:0] b30_data_delayed_22; +wire [`DWIDTH-1:0] b30_data_delayed_23; +wire [`DWIDTH-1:0] b30_data_delayed_24; +wire [`DWIDTH-1:0] b30_data_delayed_25; +wire [`DWIDTH-1:0] b30_data_delayed_26; +wire [`DWIDTH-1:0] b30_data_delayed_27; +wire [`DWIDTH-1:0] b30_data_delayed_28; +wire [`DWIDTH-1:0] b30_data_delayed_29; +wire [`DWIDTH-1:0] b30_data_delayed_30; +wire [`DWIDTH-1:0] b31_data_delayed_1; +wire [`DWIDTH-1:0] b31_data_delayed_2; +wire [`DWIDTH-1:0] b31_data_delayed_3; +wire [`DWIDTH-1:0] b31_data_delayed_4; +wire [`DWIDTH-1:0] b31_data_delayed_5; +wire [`DWIDTH-1:0] b31_data_delayed_6; +wire [`DWIDTH-1:0] b31_data_delayed_7; +wire [`DWIDTH-1:0] b31_data_delayed_8; +wire [`DWIDTH-1:0] b31_data_delayed_9; +wire [`DWIDTH-1:0] b31_data_delayed_10; +wire [`DWIDTH-1:0] b31_data_delayed_11; +wire [`DWIDTH-1:0] b31_data_delayed_12; +wire [`DWIDTH-1:0] b31_data_delayed_13; +wire [`DWIDTH-1:0] b31_data_delayed_14; +wire [`DWIDTH-1:0] b31_data_delayed_15; +wire [`DWIDTH-1:0] b31_data_delayed_16; +wire [`DWIDTH-1:0] b31_data_delayed_17; +wire [`DWIDTH-1:0] b31_data_delayed_18; +wire [`DWIDTH-1:0] b31_data_delayed_19; +wire [`DWIDTH-1:0] b31_data_delayed_20; +wire [`DWIDTH-1:0] b31_data_delayed_21; +wire [`DWIDTH-1:0] b31_data_delayed_22; +wire [`DWIDTH-1:0] b31_data_delayed_23; +wire [`DWIDTH-1:0] b31_data_delayed_24; +wire [`DWIDTH-1:0] b31_data_delayed_25; +wire [`DWIDTH-1:0] b31_data_delayed_26; +wire [`DWIDTH-1:0] b31_data_delayed_27; +wire [`DWIDTH-1:0] b31_data_delayed_28; +wire [`DWIDTH-1:0] b31_data_delayed_29; +wire [`DWIDTH-1:0] b31_data_delayed_30; +wire [`DWIDTH-1:0] b31_data_delayed_31; + +reg b_data_sel; // MUX select for Ping-Pong buffers containing the weights in the matmul +reg b_data_valid_ping; +reg b_data_valid_pong; + +always @ (posedge clk) begin + if ((clk_cnt >= 16'd1 && clk_cnt <= 16'd8)||(clk_cnt >= 16'd17 && clk_cnt <= 16'd24)) + b_data_valid_pong <= 1'b1; + else + b_data_valid_pong <= 1'b0; +end + +always @ (posedge clk) begin + if ((clk_cnt >= 16'd9 && clk_cnt <= 16'd16)) + b_data_valid_ping <= 1'b1; + else + b_data_valid_ping <= 1'b0; +end + +always @ (posedge clk) begin + if ((clk_cnt >= 16'd10 && clk_cnt <= 16'd17)||(clk_cnt >= 16'd26 && clk_cnt <= 16'd33)) + b_data_sel <= 1'b1; + else + b_data_sel <= 1'b0; +end + +////////////////////////////////////////////////////////////////////////// +// Instantiation of systolic data setup +////////////////////////////////////////////////////////////////////////// +systolic_data_setup u_systolic_data_setup( + .clk(clk), + .reset(reset), + .start_mat_mul(start_mat_mul), + .a_addr(a_addr), + .b_addr(b_addr), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .a_data(a_data), + .b_data(b_data), + .clk_cnt(clk_cnt), + .a0_data(a0_data), + .a1_data_delayed_1(a1_data_delayed_1), + .a2_data_delayed_2(a2_data_delayed_2), + .a3_data_delayed_3(a3_data_delayed_3), + .a4_data_delayed_4(a4_data_delayed_4), + .a5_data_delayed_5(a5_data_delayed_5), + .a6_data_delayed_6(a6_data_delayed_6), + .a7_data_delayed_7(a7_data_delayed_7), + .a8_data_delayed_8(a8_data_delayed_8), + .a9_data_delayed_9(a9_data_delayed_9), + .a10_data_delayed_10(a10_data_delayed_10), + .a11_data_delayed_11(a11_data_delayed_11), + .a12_data_delayed_12(a12_data_delayed_12), + .a13_data_delayed_13(a13_data_delayed_13), + .a14_data_delayed_14(a14_data_delayed_14), + .a15_data_delayed_15(a15_data_delayed_15), + .a16_data_delayed_16(a16_data_delayed_16), + .a17_data_delayed_17(a17_data_delayed_17), + .a18_data_delayed_18(a18_data_delayed_18), + .a19_data_delayed_19(a19_data_delayed_19), + .a20_data_delayed_20(a20_data_delayed_20), + .a21_data_delayed_21(a21_data_delayed_21), + .a22_data_delayed_22(a22_data_delayed_22), + .a23_data_delayed_23(a23_data_delayed_23), + .a24_data_delayed_24(a24_data_delayed_24), + .a25_data_delayed_25(a25_data_delayed_25), + .a26_data_delayed_26(a26_data_delayed_26), + .a27_data_delayed_27(a27_data_delayed_27), + .a28_data_delayed_28(a28_data_delayed_28), + .a29_data_delayed_29(a29_data_delayed_29), + .a30_data_delayed_30(a30_data_delayed_30), + .a31_data_delayed_31(a31_data_delayed_31), + .b0_data(b0_data), + .b1_data_delayed_1(b1_data_delayed_1), + .b2_data_delayed_2(b2_data_delayed_2), + .b3_data_delayed_3(b3_data_delayed_3), + .b4_data_delayed_4(b4_data_delayed_4), + .b5_data_delayed_5(b5_data_delayed_5), + .b6_data_delayed_6(b6_data_delayed_6), + .b7_data_delayed_7(b7_data_delayed_7), + .b8_data_delayed_8(b8_data_delayed_8), + .b9_data_delayed_9(b9_data_delayed_9), + .b10_data_delayed_10(b10_data_delayed_10), + .b11_data_delayed_11(b11_data_delayed_11), + .b12_data_delayed_12(b12_data_delayed_12), + .b13_data_delayed_13(b13_data_delayed_13), + .b14_data_delayed_14(b14_data_delayed_14), + .b15_data_delayed_15(b15_data_delayed_15), + .b16_data_delayed_16(b16_data_delayed_16), + .b17_data_delayed_17(b17_data_delayed_17), + .b18_data_delayed_18(b18_data_delayed_18), + .b19_data_delayed_19(b19_data_delayed_19), + .b20_data_delayed_20(b20_data_delayed_20), + .b21_data_delayed_21(b21_data_delayed_21), + .b22_data_delayed_22(b22_data_delayed_22), + .b23_data_delayed_23(b23_data_delayed_23), + .b24_data_delayed_24(b24_data_delayed_24), + .b25_data_delayed_25(b25_data_delayed_25), + .b26_data_delayed_26(b26_data_delayed_26), + .b27_data_delayed_27(b27_data_delayed_27), + .b28_data_delayed_28(b28_data_delayed_28), + .b29_data_delayed_29(b29_data_delayed_29), + .b30_data_delayed_30(b30_data_delayed_30), + .b31_data_delayed_31(b31_data_delayed_31), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols_b_rows(validity_mask_a_cols_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .num_matrices_A(num_matrices_A), + .num_matrices_B(num_matrices_B), + .a_loc(a_loc), + .b_loc(b_loc) +); + +////////////////////////////////////////////////////////////////////////// +// Logic to mux data_in coming from neighboring matmuls +////////////////////////////////////////////////////////////////////////// +wire [`DWIDTH-1:0] a0; +wire [`DWIDTH-1:0] a1; +wire [`DWIDTH-1:0] a2; +wire [`DWIDTH-1:0] a3; +wire [`DWIDTH-1:0] a4; +wire [`DWIDTH-1:0] a5; +wire [`DWIDTH-1:0] a6; +wire [`DWIDTH-1:0] a7; +wire [`DWIDTH-1:0] a8; +wire [`DWIDTH-1:0] a9; +wire [`DWIDTH-1:0] a10; +wire [`DWIDTH-1:0] a11; +wire [`DWIDTH-1:0] a12; +wire [`DWIDTH-1:0] a13; +wire [`DWIDTH-1:0] a14; +wire [`DWIDTH-1:0] a15; +wire [`DWIDTH-1:0] a16; +wire [`DWIDTH-1:0] a17; +wire [`DWIDTH-1:0] a18; +wire [`DWIDTH-1:0] a19; +wire [`DWIDTH-1:0] a20; +wire [`DWIDTH-1:0] a21; +wire [`DWIDTH-1:0] a22; +wire [`DWIDTH-1:0] a23; +wire [`DWIDTH-1:0] a24; +wire [`DWIDTH-1:0] a25; +wire [`DWIDTH-1:0] a26; +wire [`DWIDTH-1:0] a27; +wire [`DWIDTH-1:0] a28; +wire [`DWIDTH-1:0] a29; +wire [`DWIDTH-1:0] a30; +wire [`DWIDTH-1:0] a31; +wire [`DWIDTH-1:0] b0; +wire [`DWIDTH-1:0] b1; +wire [`DWIDTH-1:0] b2; +wire [`DWIDTH-1:0] b3; +wire [`DWIDTH-1:0] b4; +wire [`DWIDTH-1:0] b5; +wire [`DWIDTH-1:0] b6; +wire [`DWIDTH-1:0] b7; +wire [`DWIDTH-1:0] b8; +wire [`DWIDTH-1:0] b9; +wire [`DWIDTH-1:0] b10; +wire [`DWIDTH-1:0] b11; +wire [`DWIDTH-1:0] b12; +wire [`DWIDTH-1:0] b13; +wire [`DWIDTH-1:0] b14; +wire [`DWIDTH-1:0] b15; +wire [`DWIDTH-1:0] b16; +wire [`DWIDTH-1:0] b17; +wire [`DWIDTH-1:0] b18; +wire [`DWIDTH-1:0] b19; +wire [`DWIDTH-1:0] b20; +wire [`DWIDTH-1:0] b21; +wire [`DWIDTH-1:0] b22; +wire [`DWIDTH-1:0] b23; +wire [`DWIDTH-1:0] b24; +wire [`DWIDTH-1:0] b25; +wire [`DWIDTH-1:0] b26; +wire [`DWIDTH-1:0] b27; +wire [`DWIDTH-1:0] b28; +wire [`DWIDTH-1:0] b29; +wire [`DWIDTH-1:0] b30; +wire [`DWIDTH-1:0] b31; +wire [`DWIDTH-1:0] c0; +wire [`DWIDTH-1:0] c1; +wire [`DWIDTH-1:0] c2; +wire [`DWIDTH-1:0] c3; +wire [`DWIDTH-1:0] c4; +wire [`DWIDTH-1:0] c5; +wire [`DWIDTH-1:0] c6; +wire [`DWIDTH-1:0] c7; +wire [`DWIDTH-1:0] c8; +wire [`DWIDTH-1:0] c9; +wire [`DWIDTH-1:0] c10; +wire [`DWIDTH-1:0] c11; +wire [`DWIDTH-1:0] c12; +wire [`DWIDTH-1:0] c13; +wire [`DWIDTH-1:0] c14; +wire [`DWIDTH-1:0] c15; +wire [`DWIDTH-1:0] c16; +wire [`DWIDTH-1:0] c17; +wire [`DWIDTH-1:0] c18; +wire [`DWIDTH-1:0] c19; +wire [`DWIDTH-1:0] c20; +wire [`DWIDTH-1:0] c21; +wire [`DWIDTH-1:0] c22; +wire [`DWIDTH-1:0] c23; +wire [`DWIDTH-1:0] c24; +wire [`DWIDTH-1:0] c25; +wire [`DWIDTH-1:0] c26; +wire [`DWIDTH-1:0] c27; +wire [`DWIDTH-1:0] c28; +wire [`DWIDTH-1:0] c29; +wire [`DWIDTH-1:0] c30; +wire [`DWIDTH-1:0] c31; + +wire [`DWIDTH-1:0] a0_data_in; +wire [`DWIDTH-1:0] a1_data_in; +wire [`DWIDTH-1:0] a2_data_in; +wire [`DWIDTH-1:0] a3_data_in; +wire [`DWIDTH-1:0] a4_data_in; +wire [`DWIDTH-1:0] a5_data_in; +wire [`DWIDTH-1:0] a6_data_in; +wire [`DWIDTH-1:0] a7_data_in; +wire [`DWIDTH-1:0] a8_data_in; +wire [`DWIDTH-1:0] a9_data_in; +wire [`DWIDTH-1:0] a10_data_in; +wire [`DWIDTH-1:0] a11_data_in; +wire [`DWIDTH-1:0] a12_data_in; +wire [`DWIDTH-1:0] a13_data_in; +wire [`DWIDTH-1:0] a14_data_in; +wire [`DWIDTH-1:0] a15_data_in; +wire [`DWIDTH-1:0] a16_data_in; +wire [`DWIDTH-1:0] a17_data_in; +wire [`DWIDTH-1:0] a18_data_in; +wire [`DWIDTH-1:0] a19_data_in; +wire [`DWIDTH-1:0] a20_data_in; +wire [`DWIDTH-1:0] a21_data_in; +wire [`DWIDTH-1:0] a22_data_in; +wire [`DWIDTH-1:0] a23_data_in; +wire [`DWIDTH-1:0] a24_data_in; +wire [`DWIDTH-1:0] a25_data_in; +wire [`DWIDTH-1:0] a26_data_in; +wire [`DWIDTH-1:0] a27_data_in; +wire [`DWIDTH-1:0] a28_data_in; +wire [`DWIDTH-1:0] a29_data_in; +wire [`DWIDTH-1:0] a30_data_in; +wire [`DWIDTH-1:0] a31_data_in; +assign a0_data_in = a_data_in[`DWIDTH-1:0]; +assign a1_data_in = a_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign a2_data_in = a_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign a3_data_in = a_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign a4_data_in = a_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign a5_data_in = a_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign a6_data_in = a_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign a7_data_in = a_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign a8_data_in = a_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign a9_data_in = a_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign a10_data_in = a_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign a11_data_in = a_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign a12_data_in = a_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign a13_data_in = a_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign a14_data_in = a_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign a15_data_in = a_data_in[16*`DWIDTH-1:15*`DWIDTH]; +assign a16_data_in = a_data_in[17*`DWIDTH-1:16*`DWIDTH]; +assign a17_data_in = a_data_in[18*`DWIDTH-1:17*`DWIDTH]; +assign a18_data_in = a_data_in[19*`DWIDTH-1:18*`DWIDTH]; +assign a19_data_in = a_data_in[20*`DWIDTH-1:19*`DWIDTH]; +assign a20_data_in = a_data_in[21*`DWIDTH-1:20*`DWIDTH]; +assign a21_data_in = a_data_in[22*`DWIDTH-1:21*`DWIDTH]; +assign a22_data_in = a_data_in[23*`DWIDTH-1:22*`DWIDTH]; +assign a23_data_in = a_data_in[24*`DWIDTH-1:23*`DWIDTH]; +assign a24_data_in = a_data_in[25*`DWIDTH-1:24*`DWIDTH]; +assign a25_data_in = a_data_in[26*`DWIDTH-1:25*`DWIDTH]; +assign a26_data_in = a_data_in[27*`DWIDTH-1:26*`DWIDTH]; +assign a27_data_in = a_data_in[28*`DWIDTH-1:27*`DWIDTH]; +assign a28_data_in = a_data_in[29*`DWIDTH-1:28*`DWIDTH]; +assign a29_data_in = a_data_in[30*`DWIDTH-1:29*`DWIDTH]; +assign a30_data_in = a_data_in[31*`DWIDTH-1:30*`DWIDTH]; +assign a31_data_in = a_data_in[32*`DWIDTH-1:31*`DWIDTH]; + +wire [`DWIDTH-1:0] b0_data_in; +wire [`DWIDTH-1:0] b1_data_in; +wire [`DWIDTH-1:0] b2_data_in; +wire [`DWIDTH-1:0] b3_data_in; +wire [`DWIDTH-1:0] b4_data_in; +wire [`DWIDTH-1:0] b5_data_in; +wire [`DWIDTH-1:0] b6_data_in; +wire [`DWIDTH-1:0] b7_data_in; +wire [`DWIDTH-1:0] b8_data_in; +wire [`DWIDTH-1:0] b9_data_in; +wire [`DWIDTH-1:0] b10_data_in; +wire [`DWIDTH-1:0] b11_data_in; +wire [`DWIDTH-1:0] b12_data_in; +wire [`DWIDTH-1:0] b13_data_in; +wire [`DWIDTH-1:0] b14_data_in; +wire [`DWIDTH-1:0] b15_data_in; +wire [`DWIDTH-1:0] b16_data_in; +wire [`DWIDTH-1:0] b17_data_in; +wire [`DWIDTH-1:0] b18_data_in; +wire [`DWIDTH-1:0] b19_data_in; +wire [`DWIDTH-1:0] b20_data_in; +wire [`DWIDTH-1:0] b21_data_in; +wire [`DWIDTH-1:0] b22_data_in; +wire [`DWIDTH-1:0] b23_data_in; +wire [`DWIDTH-1:0] b24_data_in; +wire [`DWIDTH-1:0] b25_data_in; +wire [`DWIDTH-1:0] b26_data_in; +wire [`DWIDTH-1:0] b27_data_in; +wire [`DWIDTH-1:0] b28_data_in; +wire [`DWIDTH-1:0] b29_data_in; +wire [`DWIDTH-1:0] b30_data_in; +wire [`DWIDTH-1:0] b31_data_in; +assign b0_data_in = b_data_in[`DWIDTH-1:0]; +assign b1_data_in = b_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign b2_data_in = b_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign b3_data_in = b_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign b4_data_in = b_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign b5_data_in = b_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign b6_data_in = b_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign b7_data_in = b_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign b8_data_in = b_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign b9_data_in = b_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign b10_data_in = b_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign b11_data_in = b_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign b12_data_in = b_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign b13_data_in = b_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign b14_data_in = b_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign b15_data_in = b_data_in[16*`DWIDTH-1:15*`DWIDTH]; +assign b16_data_in = b_data_in[17*`DWIDTH-1:16*`DWIDTH]; +assign b17_data_in = b_data_in[18*`DWIDTH-1:17*`DWIDTH]; +assign b18_data_in = b_data_in[19*`DWIDTH-1:18*`DWIDTH]; +assign b19_data_in = b_data_in[20*`DWIDTH-1:19*`DWIDTH]; +assign b20_data_in = b_data_in[21*`DWIDTH-1:20*`DWIDTH]; +assign b21_data_in = b_data_in[22*`DWIDTH-1:21*`DWIDTH]; +assign b22_data_in = b_data_in[23*`DWIDTH-1:22*`DWIDTH]; +assign b23_data_in = b_data_in[24*`DWIDTH-1:23*`DWIDTH]; +assign b24_data_in = b_data_in[25*`DWIDTH-1:24*`DWIDTH]; +assign b25_data_in = b_data_in[26*`DWIDTH-1:25*`DWIDTH]; +assign b26_data_in = b_data_in[27*`DWIDTH-1:26*`DWIDTH]; +assign b27_data_in = b_data_in[28*`DWIDTH-1:27*`DWIDTH]; +assign b28_data_in = b_data_in[29*`DWIDTH-1:28*`DWIDTH]; +assign b29_data_in = b_data_in[30*`DWIDTH-1:29*`DWIDTH]; +assign b30_data_in = b_data_in[31*`DWIDTH-1:30*`DWIDTH]; +assign b31_data_in = b_data_in[32*`DWIDTH-1:31*`DWIDTH]; + +// If b_loc is 0, that means this matmul block is on the top-row of the +// final large matmul. In that case, b will take inputs from mem. +// If b_loc != 0, that means this matmul block is not on the top-row of the +// final large matmul. In that case, b will take inputs from the matmul on top +// of this one. +assign a0 = (b_loc==0) ? a0_data : a0_data_in; +assign a1 = (b_loc==0) ? a1_data_delayed_1 : a1_data_in; +assign a2 = (b_loc==0) ? a2_data_delayed_2 : a2_data_in; +assign a3 = (b_loc==0) ? a3_data_delayed_3 : a3_data_in; +assign a4 = (b_loc==0) ? a4_data_delayed_4 : a4_data_in; +assign a5 = (b_loc==0) ? a5_data_delayed_5 : a5_data_in; +assign a6 = (b_loc==0) ? a6_data_delayed_6 : a6_data_in; +assign a7 = (b_loc==0) ? a7_data_delayed_7 : a7_data_in; +assign a8 = (b_loc==0) ? a8_data_delayed_8 : a8_data_in; +assign a9 = (b_loc==0) ? a9_data_delayed_9 : a9_data_in; +assign a10 = (b_loc==0) ? a10_data_delayed_10 : a10_data_in; +assign a11 = (b_loc==0) ? a11_data_delayed_11 : a11_data_in; +assign a12 = (b_loc==0) ? a12_data_delayed_12 : a12_data_in; +assign a13 = (b_loc==0) ? a13_data_delayed_13 : a13_data_in; +assign a14 = (b_loc==0) ? a14_data_delayed_14 : a14_data_in; +assign a15 = (b_loc==0) ? a15_data_delayed_15 : a15_data_in; +assign a16 = (b_loc==0) ? a16_data_delayed_16 : a16_data_in; +assign a17 = (b_loc==0) ? a17_data_delayed_17 : a17_data_in; +assign a18 = (b_loc==0) ? a18_data_delayed_18 : a18_data_in; +assign a19 = (b_loc==0) ? a19_data_delayed_19 : a19_data_in; +assign a20 = (b_loc==0) ? a20_data_delayed_20 : a20_data_in; +assign a21 = (b_loc==0) ? a21_data_delayed_21 : a21_data_in; +assign a22 = (b_loc==0) ? a22_data_delayed_22 : a22_data_in; +assign a23 = (b_loc==0) ? a23_data_delayed_23 : a23_data_in; +assign a24 = (b_loc==0) ? a24_data_delayed_24 : a24_data_in; +assign a25 = (b_loc==0) ? a25_data_delayed_25 : a25_data_in; +assign a26 = (b_loc==0) ? a26_data_delayed_26 : a26_data_in; +assign a27 = (b_loc==0) ? a27_data_delayed_27 : a27_data_in; +assign a28 = (b_loc==0) ? a28_data_delayed_28 : a28_data_in; +assign a29 = (b_loc==0) ? a29_data_delayed_29 : a29_data_in; +assign a30 = (b_loc==0) ? a30_data_delayed_30 : a30_data_in; +assign a31 = (b_loc==0) ? a31_data_delayed_31 : a31_data_in; + +/// If a_loc is 0, that means this matmul block is on the left-col of the +// final large matmul. In that case, a will take inputs from mem. +// If a_loc != 0, that means this matmul block is not on the left-col of the +// final large matmul. In that case, a will take inputs from the matmul on left +// of this one. +assign b0 = (a_loc==0) ? b0_data : b0_data_in; +assign b1 = (a_loc==0) ? b1_data_delayed_1 : b1_data_in; +assign b2 = (a_loc==0) ? b2_data_delayed_2 : b2_data_in; +assign b3 = (a_loc==0) ? b3_data_delayed_3 : b3_data_in; +assign b4 = (a_loc==0) ? b4_data_delayed_4 : b4_data_in; +assign b5 = (a_loc==0) ? b5_data_delayed_5 : b5_data_in; +assign b6 = (a_loc==0) ? b6_data_delayed_6 : b6_data_in; +assign b7 = (a_loc==0) ? b7_data_delayed_7 : b7_data_in; +assign b8 = (a_loc==0) ? b8_data_delayed_8 : b8_data_in; +assign b9 = (a_loc==0) ? b9_data_delayed_9 : b9_data_in; +assign b10 = (a_loc==0) ? b10_data_delayed_10 : b10_data_in; +assign b11 = (a_loc==0) ? b11_data_delayed_11 : b11_data_in; +assign b12 = (a_loc==0) ? b12_data_delayed_12 : b12_data_in; +assign b13 = (a_loc==0) ? b13_data_delayed_13 : b13_data_in; +assign b14 = (a_loc==0) ? b14_data_delayed_14 : b14_data_in; +assign b15 = (a_loc==0) ? b15_data_delayed_15 : b15_data_in; +assign b16 = (a_loc==0) ? b16_data_delayed_16 : b16_data_in; +assign b17 = (a_loc==0) ? b17_data_delayed_17 : b17_data_in; +assign b18 = (a_loc==0) ? b18_data_delayed_18 : b18_data_in; +assign b19 = (a_loc==0) ? b19_data_delayed_19 : b19_data_in; +assign b20 = (a_loc==0) ? b20_data_delayed_20 : b20_data_in; +assign b21 = (a_loc==0) ? b21_data_delayed_21 : b21_data_in; +assign b22 = (a_loc==0) ? b22_data_delayed_22 : b22_data_in; +assign b23 = (a_loc==0) ? b23_data_delayed_23 : b23_data_in; +assign b24 = (a_loc==0) ? b24_data_delayed_24 : b24_data_in; +assign b25 = (a_loc==0) ? b25_data_delayed_25 : b25_data_in; +assign b26 = (a_loc==0) ? b26_data_delayed_26 : b26_data_in; +assign b27 = (a_loc==0) ? b27_data_delayed_27 : b27_data_in; +assign b28 = (a_loc==0) ? b28_data_delayed_28 : b28_data_in; +assign b29 = (a_loc==0) ? b29_data_delayed_29 : b29_data_in; +assign b30 = (a_loc==0) ? b30_data_delayed_30 : b30_data_in; +assign b31 = (a_loc==0) ? b31_data_delayed_31 : b31_data_in; + +assign c0 = c_data_in[`DWIDTH-1:0]; +assign c1 = c_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign c2 = c_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign c3 = c_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign c4 = c_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign c5 = c_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign c6 = c_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign c7 = c_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign c8 = c_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign c9 = c_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign c10 = c_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign c11 = c_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign c12 = c_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign c13 = c_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign c14 = c_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign c15 = c_data_in[16*`DWIDTH-1:15*`DWIDTH]; +assign c16 = c_data_in[17*`DWIDTH-1:16*`DWIDTH]; +assign c17 = c_data_in[18*`DWIDTH-1:17*`DWIDTH]; +assign c18 = c_data_in[19*`DWIDTH-1:18*`DWIDTH]; +assign c19 = c_data_in[20*`DWIDTH-1:19*`DWIDTH]; +assign c20 = c_data_in[21*`DWIDTH-1:20*`DWIDTH]; +assign c21 = c_data_in[22*`DWIDTH-1:21*`DWIDTH]; +assign c22 = c_data_in[23*`DWIDTH-1:22*`DWIDTH]; +assign c23 = c_data_in[24*`DWIDTH-1:23*`DWIDTH]; +assign c24 = c_data_in[25*`DWIDTH-1:24*`DWIDTH]; +assign c25 = c_data_in[26*`DWIDTH-1:25*`DWIDTH]; +assign c26 = c_data_in[27*`DWIDTH-1:26*`DWIDTH]; +assign c27 = c_data_in[28*`DWIDTH-1:27*`DWIDTH]; +assign c28 = c_data_in[29*`DWIDTH-1:28*`DWIDTH]; +assign c29 = c_data_in[30*`DWIDTH-1:29*`DWIDTH]; +assign c30 = c_data_in[31*`DWIDTH-1:30*`DWIDTH]; +assign c31 = c_data_in[32*`DWIDTH-1:31*`DWIDTH]; + +wire [`DWIDTH-1:0] matrixC0_0; +wire [`DWIDTH-1:0] matrixC0_1; +wire [`DWIDTH-1:0] matrixC0_2; +wire [`DWIDTH-1:0] matrixC0_3; +wire [`DWIDTH-1:0] matrixC0_4; +wire [`DWIDTH-1:0] matrixC0_5; +wire [`DWIDTH-1:0] matrixC0_6; +wire [`DWIDTH-1:0] matrixC0_7; +wire [`DWIDTH-1:0] matrixC0_8; +wire [`DWIDTH-1:0] matrixC0_9; +wire [`DWIDTH-1:0] matrixC0_10; +wire [`DWIDTH-1:0] matrixC0_11; +wire [`DWIDTH-1:0] matrixC0_12; +wire [`DWIDTH-1:0] matrixC0_13; +wire [`DWIDTH-1:0] matrixC0_14; +wire [`DWIDTH-1:0] matrixC0_15; +wire [`DWIDTH-1:0] matrixC0_16; +wire [`DWIDTH-1:0] matrixC0_17; +wire [`DWIDTH-1:0] matrixC0_18; +wire [`DWIDTH-1:0] matrixC0_19; +wire [`DWIDTH-1:0] matrixC0_20; +wire [`DWIDTH-1:0] matrixC0_21; +wire [`DWIDTH-1:0] matrixC0_22; +wire [`DWIDTH-1:0] matrixC0_23; +wire [`DWIDTH-1:0] matrixC0_24; +wire [`DWIDTH-1:0] matrixC0_25; +wire [`DWIDTH-1:0] matrixC0_26; +wire [`DWIDTH-1:0] matrixC0_27; +wire [`DWIDTH-1:0] matrixC0_28; +wire [`DWIDTH-1:0] matrixC0_29; +wire [`DWIDTH-1:0] matrixC0_30; +wire [`DWIDTH-1:0] matrixC0_31; +wire [`DWIDTH-1:0] matrixC1_0; +wire [`DWIDTH-1:0] matrixC1_1; +wire [`DWIDTH-1:0] matrixC1_2; +wire [`DWIDTH-1:0] matrixC1_3; +wire [`DWIDTH-1:0] matrixC1_4; +wire [`DWIDTH-1:0] matrixC1_5; +wire [`DWIDTH-1:0] matrixC1_6; +wire [`DWIDTH-1:0] matrixC1_7; +wire [`DWIDTH-1:0] matrixC1_8; +wire [`DWIDTH-1:0] matrixC1_9; +wire [`DWIDTH-1:0] matrixC1_10; +wire [`DWIDTH-1:0] matrixC1_11; +wire [`DWIDTH-1:0] matrixC1_12; +wire [`DWIDTH-1:0] matrixC1_13; +wire [`DWIDTH-1:0] matrixC1_14; +wire [`DWIDTH-1:0] matrixC1_15; +wire [`DWIDTH-1:0] matrixC1_16; +wire [`DWIDTH-1:0] matrixC1_17; +wire [`DWIDTH-1:0] matrixC1_18; +wire [`DWIDTH-1:0] matrixC1_19; +wire [`DWIDTH-1:0] matrixC1_20; +wire [`DWIDTH-1:0] matrixC1_21; +wire [`DWIDTH-1:0] matrixC1_22; +wire [`DWIDTH-1:0] matrixC1_23; +wire [`DWIDTH-1:0] matrixC1_24; +wire [`DWIDTH-1:0] matrixC1_25; +wire [`DWIDTH-1:0] matrixC1_26; +wire [`DWIDTH-1:0] matrixC1_27; +wire [`DWIDTH-1:0] matrixC1_28; +wire [`DWIDTH-1:0] matrixC1_29; +wire [`DWIDTH-1:0] matrixC1_30; +wire [`DWIDTH-1:0] matrixC1_31; +wire [`DWIDTH-1:0] matrixC2_0; +wire [`DWIDTH-1:0] matrixC2_1; +wire [`DWIDTH-1:0] matrixC2_2; +wire [`DWIDTH-1:0] matrixC2_3; +wire [`DWIDTH-1:0] matrixC2_4; +wire [`DWIDTH-1:0] matrixC2_5; +wire [`DWIDTH-1:0] matrixC2_6; +wire [`DWIDTH-1:0] matrixC2_7; +wire [`DWIDTH-1:0] matrixC2_8; +wire [`DWIDTH-1:0] matrixC2_9; +wire [`DWIDTH-1:0] matrixC2_10; +wire [`DWIDTH-1:0] matrixC2_11; +wire [`DWIDTH-1:0] matrixC2_12; +wire [`DWIDTH-1:0] matrixC2_13; +wire [`DWIDTH-1:0] matrixC2_14; +wire [`DWIDTH-1:0] matrixC2_15; +wire [`DWIDTH-1:0] matrixC2_16; +wire [`DWIDTH-1:0] matrixC2_17; +wire [`DWIDTH-1:0] matrixC2_18; +wire [`DWIDTH-1:0] matrixC2_19; +wire [`DWIDTH-1:0] matrixC2_20; +wire [`DWIDTH-1:0] matrixC2_21; +wire [`DWIDTH-1:0] matrixC2_22; +wire [`DWIDTH-1:0] matrixC2_23; +wire [`DWIDTH-1:0] matrixC2_24; +wire [`DWIDTH-1:0] matrixC2_25; +wire [`DWIDTH-1:0] matrixC2_26; +wire [`DWIDTH-1:0] matrixC2_27; +wire [`DWIDTH-1:0] matrixC2_28; +wire [`DWIDTH-1:0] matrixC2_29; +wire [`DWIDTH-1:0] matrixC2_30; +wire [`DWIDTH-1:0] matrixC2_31; +wire [`DWIDTH-1:0] matrixC3_0; +wire [`DWIDTH-1:0] matrixC3_1; +wire [`DWIDTH-1:0] matrixC3_2; +wire [`DWIDTH-1:0] matrixC3_3; +wire [`DWIDTH-1:0] matrixC3_4; +wire [`DWIDTH-1:0] matrixC3_5; +wire [`DWIDTH-1:0] matrixC3_6; +wire [`DWIDTH-1:0] matrixC3_7; +wire [`DWIDTH-1:0] matrixC3_8; +wire [`DWIDTH-1:0] matrixC3_9; +wire [`DWIDTH-1:0] matrixC3_10; +wire [`DWIDTH-1:0] matrixC3_11; +wire [`DWIDTH-1:0] matrixC3_12; +wire [`DWIDTH-1:0] matrixC3_13; +wire [`DWIDTH-1:0] matrixC3_14; +wire [`DWIDTH-1:0] matrixC3_15; +wire [`DWIDTH-1:0] matrixC3_16; +wire [`DWIDTH-1:0] matrixC3_17; +wire [`DWIDTH-1:0] matrixC3_18; +wire [`DWIDTH-1:0] matrixC3_19; +wire [`DWIDTH-1:0] matrixC3_20; +wire [`DWIDTH-1:0] matrixC3_21; +wire [`DWIDTH-1:0] matrixC3_22; +wire [`DWIDTH-1:0] matrixC3_23; +wire [`DWIDTH-1:0] matrixC3_24; +wire [`DWIDTH-1:0] matrixC3_25; +wire [`DWIDTH-1:0] matrixC3_26; +wire [`DWIDTH-1:0] matrixC3_27; +wire [`DWIDTH-1:0] matrixC3_28; +wire [`DWIDTH-1:0] matrixC3_29; +wire [`DWIDTH-1:0] matrixC3_30; +wire [`DWIDTH-1:0] matrixC3_31; +wire [`DWIDTH-1:0] matrixC4_0; +wire [`DWIDTH-1:0] matrixC4_1; +wire [`DWIDTH-1:0] matrixC4_2; +wire [`DWIDTH-1:0] matrixC4_3; +wire [`DWIDTH-1:0] matrixC4_4; +wire [`DWIDTH-1:0] matrixC4_5; +wire [`DWIDTH-1:0] matrixC4_6; +wire [`DWIDTH-1:0] matrixC4_7; +wire [`DWIDTH-1:0] matrixC4_8; +wire [`DWIDTH-1:0] matrixC4_9; +wire [`DWIDTH-1:0] matrixC4_10; +wire [`DWIDTH-1:0] matrixC4_11; +wire [`DWIDTH-1:0] matrixC4_12; +wire [`DWIDTH-1:0] matrixC4_13; +wire [`DWIDTH-1:0] matrixC4_14; +wire [`DWIDTH-1:0] matrixC4_15; +wire [`DWIDTH-1:0] matrixC4_16; +wire [`DWIDTH-1:0] matrixC4_17; +wire [`DWIDTH-1:0] matrixC4_18; +wire [`DWIDTH-1:0] matrixC4_19; +wire [`DWIDTH-1:0] matrixC4_20; +wire [`DWIDTH-1:0] matrixC4_21; +wire [`DWIDTH-1:0] matrixC4_22; +wire [`DWIDTH-1:0] matrixC4_23; +wire [`DWIDTH-1:0] matrixC4_24; +wire [`DWIDTH-1:0] matrixC4_25; +wire [`DWIDTH-1:0] matrixC4_26; +wire [`DWIDTH-1:0] matrixC4_27; +wire [`DWIDTH-1:0] matrixC4_28; +wire [`DWIDTH-1:0] matrixC4_29; +wire [`DWIDTH-1:0] matrixC4_30; +wire [`DWIDTH-1:0] matrixC4_31; +wire [`DWIDTH-1:0] matrixC5_0; +wire [`DWIDTH-1:0] matrixC5_1; +wire [`DWIDTH-1:0] matrixC5_2; +wire [`DWIDTH-1:0] matrixC5_3; +wire [`DWIDTH-1:0] matrixC5_4; +wire [`DWIDTH-1:0] matrixC5_5; +wire [`DWIDTH-1:0] matrixC5_6; +wire [`DWIDTH-1:0] matrixC5_7; +wire [`DWIDTH-1:0] matrixC5_8; +wire [`DWIDTH-1:0] matrixC5_9; +wire [`DWIDTH-1:0] matrixC5_10; +wire [`DWIDTH-1:0] matrixC5_11; +wire [`DWIDTH-1:0] matrixC5_12; +wire [`DWIDTH-1:0] matrixC5_13; +wire [`DWIDTH-1:0] matrixC5_14; +wire [`DWIDTH-1:0] matrixC5_15; +wire [`DWIDTH-1:0] matrixC5_16; +wire [`DWIDTH-1:0] matrixC5_17; +wire [`DWIDTH-1:0] matrixC5_18; +wire [`DWIDTH-1:0] matrixC5_19; +wire [`DWIDTH-1:0] matrixC5_20; +wire [`DWIDTH-1:0] matrixC5_21; +wire [`DWIDTH-1:0] matrixC5_22; +wire [`DWIDTH-1:0] matrixC5_23; +wire [`DWIDTH-1:0] matrixC5_24; +wire [`DWIDTH-1:0] matrixC5_25; +wire [`DWIDTH-1:0] matrixC5_26; +wire [`DWIDTH-1:0] matrixC5_27; +wire [`DWIDTH-1:0] matrixC5_28; +wire [`DWIDTH-1:0] matrixC5_29; +wire [`DWIDTH-1:0] matrixC5_30; +wire [`DWIDTH-1:0] matrixC5_31; +wire [`DWIDTH-1:0] matrixC6_0; +wire [`DWIDTH-1:0] matrixC6_1; +wire [`DWIDTH-1:0] matrixC6_2; +wire [`DWIDTH-1:0] matrixC6_3; +wire [`DWIDTH-1:0] matrixC6_4; +wire [`DWIDTH-1:0] matrixC6_5; +wire [`DWIDTH-1:0] matrixC6_6; +wire [`DWIDTH-1:0] matrixC6_7; +wire [`DWIDTH-1:0] matrixC6_8; +wire [`DWIDTH-1:0] matrixC6_9; +wire [`DWIDTH-1:0] matrixC6_10; +wire [`DWIDTH-1:0] matrixC6_11; +wire [`DWIDTH-1:0] matrixC6_12; +wire [`DWIDTH-1:0] matrixC6_13; +wire [`DWIDTH-1:0] matrixC6_14; +wire [`DWIDTH-1:0] matrixC6_15; +wire [`DWIDTH-1:0] matrixC6_16; +wire [`DWIDTH-1:0] matrixC6_17; +wire [`DWIDTH-1:0] matrixC6_18; +wire [`DWIDTH-1:0] matrixC6_19; +wire [`DWIDTH-1:0] matrixC6_20; +wire [`DWIDTH-1:0] matrixC6_21; +wire [`DWIDTH-1:0] matrixC6_22; +wire [`DWIDTH-1:0] matrixC6_23; +wire [`DWIDTH-1:0] matrixC6_24; +wire [`DWIDTH-1:0] matrixC6_25; +wire [`DWIDTH-1:0] matrixC6_26; +wire [`DWIDTH-1:0] matrixC6_27; +wire [`DWIDTH-1:0] matrixC6_28; +wire [`DWIDTH-1:0] matrixC6_29; +wire [`DWIDTH-1:0] matrixC6_30; +wire [`DWIDTH-1:0] matrixC6_31; +wire [`DWIDTH-1:0] matrixC7_0; +wire [`DWIDTH-1:0] matrixC7_1; +wire [`DWIDTH-1:0] matrixC7_2; +wire [`DWIDTH-1:0] matrixC7_3; +wire [`DWIDTH-1:0] matrixC7_4; +wire [`DWIDTH-1:0] matrixC7_5; +wire [`DWIDTH-1:0] matrixC7_6; +wire [`DWIDTH-1:0] matrixC7_7; +wire [`DWIDTH-1:0] matrixC7_8; +wire [`DWIDTH-1:0] matrixC7_9; +wire [`DWIDTH-1:0] matrixC7_10; +wire [`DWIDTH-1:0] matrixC7_11; +wire [`DWIDTH-1:0] matrixC7_12; +wire [`DWIDTH-1:0] matrixC7_13; +wire [`DWIDTH-1:0] matrixC7_14; +wire [`DWIDTH-1:0] matrixC7_15; +wire [`DWIDTH-1:0] matrixC7_16; +wire [`DWIDTH-1:0] matrixC7_17; +wire [`DWIDTH-1:0] matrixC7_18; +wire [`DWIDTH-1:0] matrixC7_19; +wire [`DWIDTH-1:0] matrixC7_20; +wire [`DWIDTH-1:0] matrixC7_21; +wire [`DWIDTH-1:0] matrixC7_22; +wire [`DWIDTH-1:0] matrixC7_23; +wire [`DWIDTH-1:0] matrixC7_24; +wire [`DWIDTH-1:0] matrixC7_25; +wire [`DWIDTH-1:0] matrixC7_26; +wire [`DWIDTH-1:0] matrixC7_27; +wire [`DWIDTH-1:0] matrixC7_28; +wire [`DWIDTH-1:0] matrixC7_29; +wire [`DWIDTH-1:0] matrixC7_30; +wire [`DWIDTH-1:0] matrixC7_31; +wire [`DWIDTH-1:0] matrixC8_0; +wire [`DWIDTH-1:0] matrixC8_1; +wire [`DWIDTH-1:0] matrixC8_2; +wire [`DWIDTH-1:0] matrixC8_3; +wire [`DWIDTH-1:0] matrixC8_4; +wire [`DWIDTH-1:0] matrixC8_5; +wire [`DWIDTH-1:0] matrixC8_6; +wire [`DWIDTH-1:0] matrixC8_7; +wire [`DWIDTH-1:0] matrixC8_8; +wire [`DWIDTH-1:0] matrixC8_9; +wire [`DWIDTH-1:0] matrixC8_10; +wire [`DWIDTH-1:0] matrixC8_11; +wire [`DWIDTH-1:0] matrixC8_12; +wire [`DWIDTH-1:0] matrixC8_13; +wire [`DWIDTH-1:0] matrixC8_14; +wire [`DWIDTH-1:0] matrixC8_15; +wire [`DWIDTH-1:0] matrixC8_16; +wire [`DWIDTH-1:0] matrixC8_17; +wire [`DWIDTH-1:0] matrixC8_18; +wire [`DWIDTH-1:0] matrixC8_19; +wire [`DWIDTH-1:0] matrixC8_20; +wire [`DWIDTH-1:0] matrixC8_21; +wire [`DWIDTH-1:0] matrixC8_22; +wire [`DWIDTH-1:0] matrixC8_23; +wire [`DWIDTH-1:0] matrixC8_24; +wire [`DWIDTH-1:0] matrixC8_25; +wire [`DWIDTH-1:0] matrixC8_26; +wire [`DWIDTH-1:0] matrixC8_27; +wire [`DWIDTH-1:0] matrixC8_28; +wire [`DWIDTH-1:0] matrixC8_29; +wire [`DWIDTH-1:0] matrixC8_30; +wire [`DWIDTH-1:0] matrixC8_31; +wire [`DWIDTH-1:0] matrixC9_0; +wire [`DWIDTH-1:0] matrixC9_1; +wire [`DWIDTH-1:0] matrixC9_2; +wire [`DWIDTH-1:0] matrixC9_3; +wire [`DWIDTH-1:0] matrixC9_4; +wire [`DWIDTH-1:0] matrixC9_5; +wire [`DWIDTH-1:0] matrixC9_6; +wire [`DWIDTH-1:0] matrixC9_7; +wire [`DWIDTH-1:0] matrixC9_8; +wire [`DWIDTH-1:0] matrixC9_9; +wire [`DWIDTH-1:0] matrixC9_10; +wire [`DWIDTH-1:0] matrixC9_11; +wire [`DWIDTH-1:0] matrixC9_12; +wire [`DWIDTH-1:0] matrixC9_13; +wire [`DWIDTH-1:0] matrixC9_14; +wire [`DWIDTH-1:0] matrixC9_15; +wire [`DWIDTH-1:0] matrixC9_16; +wire [`DWIDTH-1:0] matrixC9_17; +wire [`DWIDTH-1:0] matrixC9_18; +wire [`DWIDTH-1:0] matrixC9_19; +wire [`DWIDTH-1:0] matrixC9_20; +wire [`DWIDTH-1:0] matrixC9_21; +wire [`DWIDTH-1:0] matrixC9_22; +wire [`DWIDTH-1:0] matrixC9_23; +wire [`DWIDTH-1:0] matrixC9_24; +wire [`DWIDTH-1:0] matrixC9_25; +wire [`DWIDTH-1:0] matrixC9_26; +wire [`DWIDTH-1:0] matrixC9_27; +wire [`DWIDTH-1:0] matrixC9_28; +wire [`DWIDTH-1:0] matrixC9_29; +wire [`DWIDTH-1:0] matrixC9_30; +wire [`DWIDTH-1:0] matrixC9_31; +wire [`DWIDTH-1:0] matrixC10_0; +wire [`DWIDTH-1:0] matrixC10_1; +wire [`DWIDTH-1:0] matrixC10_2; +wire [`DWIDTH-1:0] matrixC10_3; +wire [`DWIDTH-1:0] matrixC10_4; +wire [`DWIDTH-1:0] matrixC10_5; +wire [`DWIDTH-1:0] matrixC10_6; +wire [`DWIDTH-1:0] matrixC10_7; +wire [`DWIDTH-1:0] matrixC10_8; +wire [`DWIDTH-1:0] matrixC10_9; +wire [`DWIDTH-1:0] matrixC10_10; +wire [`DWIDTH-1:0] matrixC10_11; +wire [`DWIDTH-1:0] matrixC10_12; +wire [`DWIDTH-1:0] matrixC10_13; +wire [`DWIDTH-1:0] matrixC10_14; +wire [`DWIDTH-1:0] matrixC10_15; +wire [`DWIDTH-1:0] matrixC10_16; +wire [`DWIDTH-1:0] matrixC10_17; +wire [`DWIDTH-1:0] matrixC10_18; +wire [`DWIDTH-1:0] matrixC10_19; +wire [`DWIDTH-1:0] matrixC10_20; +wire [`DWIDTH-1:0] matrixC10_21; +wire [`DWIDTH-1:0] matrixC10_22; +wire [`DWIDTH-1:0] matrixC10_23; +wire [`DWIDTH-1:0] matrixC10_24; +wire [`DWIDTH-1:0] matrixC10_25; +wire [`DWIDTH-1:0] matrixC10_26; +wire [`DWIDTH-1:0] matrixC10_27; +wire [`DWIDTH-1:0] matrixC10_28; +wire [`DWIDTH-1:0] matrixC10_29; +wire [`DWIDTH-1:0] matrixC10_30; +wire [`DWIDTH-1:0] matrixC10_31; +wire [`DWIDTH-1:0] matrixC11_0; +wire [`DWIDTH-1:0] matrixC11_1; +wire [`DWIDTH-1:0] matrixC11_2; +wire [`DWIDTH-1:0] matrixC11_3; +wire [`DWIDTH-1:0] matrixC11_4; +wire [`DWIDTH-1:0] matrixC11_5; +wire [`DWIDTH-1:0] matrixC11_6; +wire [`DWIDTH-1:0] matrixC11_7; +wire [`DWIDTH-1:0] matrixC11_8; +wire [`DWIDTH-1:0] matrixC11_9; +wire [`DWIDTH-1:0] matrixC11_10; +wire [`DWIDTH-1:0] matrixC11_11; +wire [`DWIDTH-1:0] matrixC11_12; +wire [`DWIDTH-1:0] matrixC11_13; +wire [`DWIDTH-1:0] matrixC11_14; +wire [`DWIDTH-1:0] matrixC11_15; +wire [`DWIDTH-1:0] matrixC11_16; +wire [`DWIDTH-1:0] matrixC11_17; +wire [`DWIDTH-1:0] matrixC11_18; +wire [`DWIDTH-1:0] matrixC11_19; +wire [`DWIDTH-1:0] matrixC11_20; +wire [`DWIDTH-1:0] matrixC11_21; +wire [`DWIDTH-1:0] matrixC11_22; +wire [`DWIDTH-1:0] matrixC11_23; +wire [`DWIDTH-1:0] matrixC11_24; +wire [`DWIDTH-1:0] matrixC11_25; +wire [`DWIDTH-1:0] matrixC11_26; +wire [`DWIDTH-1:0] matrixC11_27; +wire [`DWIDTH-1:0] matrixC11_28; +wire [`DWIDTH-1:0] matrixC11_29; +wire [`DWIDTH-1:0] matrixC11_30; +wire [`DWIDTH-1:0] matrixC11_31; +wire [`DWIDTH-1:0] matrixC12_0; +wire [`DWIDTH-1:0] matrixC12_1; +wire [`DWIDTH-1:0] matrixC12_2; +wire [`DWIDTH-1:0] matrixC12_3; +wire [`DWIDTH-1:0] matrixC12_4; +wire [`DWIDTH-1:0] matrixC12_5; +wire [`DWIDTH-1:0] matrixC12_6; +wire [`DWIDTH-1:0] matrixC12_7; +wire [`DWIDTH-1:0] matrixC12_8; +wire [`DWIDTH-1:0] matrixC12_9; +wire [`DWIDTH-1:0] matrixC12_10; +wire [`DWIDTH-1:0] matrixC12_11; +wire [`DWIDTH-1:0] matrixC12_12; +wire [`DWIDTH-1:0] matrixC12_13; +wire [`DWIDTH-1:0] matrixC12_14; +wire [`DWIDTH-1:0] matrixC12_15; +wire [`DWIDTH-1:0] matrixC12_16; +wire [`DWIDTH-1:0] matrixC12_17; +wire [`DWIDTH-1:0] matrixC12_18; +wire [`DWIDTH-1:0] matrixC12_19; +wire [`DWIDTH-1:0] matrixC12_20; +wire [`DWIDTH-1:0] matrixC12_21; +wire [`DWIDTH-1:0] matrixC12_22; +wire [`DWIDTH-1:0] matrixC12_23; +wire [`DWIDTH-1:0] matrixC12_24; +wire [`DWIDTH-1:0] matrixC12_25; +wire [`DWIDTH-1:0] matrixC12_26; +wire [`DWIDTH-1:0] matrixC12_27; +wire [`DWIDTH-1:0] matrixC12_28; +wire [`DWIDTH-1:0] matrixC12_29; +wire [`DWIDTH-1:0] matrixC12_30; +wire [`DWIDTH-1:0] matrixC12_31; +wire [`DWIDTH-1:0] matrixC13_0; +wire [`DWIDTH-1:0] matrixC13_1; +wire [`DWIDTH-1:0] matrixC13_2; +wire [`DWIDTH-1:0] matrixC13_3; +wire [`DWIDTH-1:0] matrixC13_4; +wire [`DWIDTH-1:0] matrixC13_5; +wire [`DWIDTH-1:0] matrixC13_6; +wire [`DWIDTH-1:0] matrixC13_7; +wire [`DWIDTH-1:0] matrixC13_8; +wire [`DWIDTH-1:0] matrixC13_9; +wire [`DWIDTH-1:0] matrixC13_10; +wire [`DWIDTH-1:0] matrixC13_11; +wire [`DWIDTH-1:0] matrixC13_12; +wire [`DWIDTH-1:0] matrixC13_13; +wire [`DWIDTH-1:0] matrixC13_14; +wire [`DWIDTH-1:0] matrixC13_15; +wire [`DWIDTH-1:0] matrixC13_16; +wire [`DWIDTH-1:0] matrixC13_17; +wire [`DWIDTH-1:0] matrixC13_18; +wire [`DWIDTH-1:0] matrixC13_19; +wire [`DWIDTH-1:0] matrixC13_20; +wire [`DWIDTH-1:0] matrixC13_21; +wire [`DWIDTH-1:0] matrixC13_22; +wire [`DWIDTH-1:0] matrixC13_23; +wire [`DWIDTH-1:0] matrixC13_24; +wire [`DWIDTH-1:0] matrixC13_25; +wire [`DWIDTH-1:0] matrixC13_26; +wire [`DWIDTH-1:0] matrixC13_27; +wire [`DWIDTH-1:0] matrixC13_28; +wire [`DWIDTH-1:0] matrixC13_29; +wire [`DWIDTH-1:0] matrixC13_30; +wire [`DWIDTH-1:0] matrixC13_31; +wire [`DWIDTH-1:0] matrixC14_0; +wire [`DWIDTH-1:0] matrixC14_1; +wire [`DWIDTH-1:0] matrixC14_2; +wire [`DWIDTH-1:0] matrixC14_3; +wire [`DWIDTH-1:0] matrixC14_4; +wire [`DWIDTH-1:0] matrixC14_5; +wire [`DWIDTH-1:0] matrixC14_6; +wire [`DWIDTH-1:0] matrixC14_7; +wire [`DWIDTH-1:0] matrixC14_8; +wire [`DWIDTH-1:0] matrixC14_9; +wire [`DWIDTH-1:0] matrixC14_10; +wire [`DWIDTH-1:0] matrixC14_11; +wire [`DWIDTH-1:0] matrixC14_12; +wire [`DWIDTH-1:0] matrixC14_13; +wire [`DWIDTH-1:0] matrixC14_14; +wire [`DWIDTH-1:0] matrixC14_15; +wire [`DWIDTH-1:0] matrixC14_16; +wire [`DWIDTH-1:0] matrixC14_17; +wire [`DWIDTH-1:0] matrixC14_18; +wire [`DWIDTH-1:0] matrixC14_19; +wire [`DWIDTH-1:0] matrixC14_20; +wire [`DWIDTH-1:0] matrixC14_21; +wire [`DWIDTH-1:0] matrixC14_22; +wire [`DWIDTH-1:0] matrixC14_23; +wire [`DWIDTH-1:0] matrixC14_24; +wire [`DWIDTH-1:0] matrixC14_25; +wire [`DWIDTH-1:0] matrixC14_26; +wire [`DWIDTH-1:0] matrixC14_27; +wire [`DWIDTH-1:0] matrixC14_28; +wire [`DWIDTH-1:0] matrixC14_29; +wire [`DWIDTH-1:0] matrixC14_30; +wire [`DWIDTH-1:0] matrixC14_31; +wire [`DWIDTH-1:0] matrixC15_0; +wire [`DWIDTH-1:0] matrixC15_1; +wire [`DWIDTH-1:0] matrixC15_2; +wire [`DWIDTH-1:0] matrixC15_3; +wire [`DWIDTH-1:0] matrixC15_4; +wire [`DWIDTH-1:0] matrixC15_5; +wire [`DWIDTH-1:0] matrixC15_6; +wire [`DWIDTH-1:0] matrixC15_7; +wire [`DWIDTH-1:0] matrixC15_8; +wire [`DWIDTH-1:0] matrixC15_9; +wire [`DWIDTH-1:0] matrixC15_10; +wire [`DWIDTH-1:0] matrixC15_11; +wire [`DWIDTH-1:0] matrixC15_12; +wire [`DWIDTH-1:0] matrixC15_13; +wire [`DWIDTH-1:0] matrixC15_14; +wire [`DWIDTH-1:0] matrixC15_15; +wire [`DWIDTH-1:0] matrixC15_16; +wire [`DWIDTH-1:0] matrixC15_17; +wire [`DWIDTH-1:0] matrixC15_18; +wire [`DWIDTH-1:0] matrixC15_19; +wire [`DWIDTH-1:0] matrixC15_20; +wire [`DWIDTH-1:0] matrixC15_21; +wire [`DWIDTH-1:0] matrixC15_22; +wire [`DWIDTH-1:0] matrixC15_23; +wire [`DWIDTH-1:0] matrixC15_24; +wire [`DWIDTH-1:0] matrixC15_25; +wire [`DWIDTH-1:0] matrixC15_26; +wire [`DWIDTH-1:0] matrixC15_27; +wire [`DWIDTH-1:0] matrixC15_28; +wire [`DWIDTH-1:0] matrixC15_29; +wire [`DWIDTH-1:0] matrixC15_30; +wire [`DWIDTH-1:0] matrixC15_31; +wire [`DWIDTH-1:0] matrixC16_0; +wire [`DWIDTH-1:0] matrixC16_1; +wire [`DWIDTH-1:0] matrixC16_2; +wire [`DWIDTH-1:0] matrixC16_3; +wire [`DWIDTH-1:0] matrixC16_4; +wire [`DWIDTH-1:0] matrixC16_5; +wire [`DWIDTH-1:0] matrixC16_6; +wire [`DWIDTH-1:0] matrixC16_7; +wire [`DWIDTH-1:0] matrixC16_8; +wire [`DWIDTH-1:0] matrixC16_9; +wire [`DWIDTH-1:0] matrixC16_10; +wire [`DWIDTH-1:0] matrixC16_11; +wire [`DWIDTH-1:0] matrixC16_12; +wire [`DWIDTH-1:0] matrixC16_13; +wire [`DWIDTH-1:0] matrixC16_14; +wire [`DWIDTH-1:0] matrixC16_15; +wire [`DWIDTH-1:0] matrixC16_16; +wire [`DWIDTH-1:0] matrixC16_17; +wire [`DWIDTH-1:0] matrixC16_18; +wire [`DWIDTH-1:0] matrixC16_19; +wire [`DWIDTH-1:0] matrixC16_20; +wire [`DWIDTH-1:0] matrixC16_21; +wire [`DWIDTH-1:0] matrixC16_22; +wire [`DWIDTH-1:0] matrixC16_23; +wire [`DWIDTH-1:0] matrixC16_24; +wire [`DWIDTH-1:0] matrixC16_25; +wire [`DWIDTH-1:0] matrixC16_26; +wire [`DWIDTH-1:0] matrixC16_27; +wire [`DWIDTH-1:0] matrixC16_28; +wire [`DWIDTH-1:0] matrixC16_29; +wire [`DWIDTH-1:0] matrixC16_30; +wire [`DWIDTH-1:0] matrixC16_31; +wire [`DWIDTH-1:0] matrixC17_0; +wire [`DWIDTH-1:0] matrixC17_1; +wire [`DWIDTH-1:0] matrixC17_2; +wire [`DWIDTH-1:0] matrixC17_3; +wire [`DWIDTH-1:0] matrixC17_4; +wire [`DWIDTH-1:0] matrixC17_5; +wire [`DWIDTH-1:0] matrixC17_6; +wire [`DWIDTH-1:0] matrixC17_7; +wire [`DWIDTH-1:0] matrixC17_8; +wire [`DWIDTH-1:0] matrixC17_9; +wire [`DWIDTH-1:0] matrixC17_10; +wire [`DWIDTH-1:0] matrixC17_11; +wire [`DWIDTH-1:0] matrixC17_12; +wire [`DWIDTH-1:0] matrixC17_13; +wire [`DWIDTH-1:0] matrixC17_14; +wire [`DWIDTH-1:0] matrixC17_15; +wire [`DWIDTH-1:0] matrixC17_16; +wire [`DWIDTH-1:0] matrixC17_17; +wire [`DWIDTH-1:0] matrixC17_18; +wire [`DWIDTH-1:0] matrixC17_19; +wire [`DWIDTH-1:0] matrixC17_20; +wire [`DWIDTH-1:0] matrixC17_21; +wire [`DWIDTH-1:0] matrixC17_22; +wire [`DWIDTH-1:0] matrixC17_23; +wire [`DWIDTH-1:0] matrixC17_24; +wire [`DWIDTH-1:0] matrixC17_25; +wire [`DWIDTH-1:0] matrixC17_26; +wire [`DWIDTH-1:0] matrixC17_27; +wire [`DWIDTH-1:0] matrixC17_28; +wire [`DWIDTH-1:0] matrixC17_29; +wire [`DWIDTH-1:0] matrixC17_30; +wire [`DWIDTH-1:0] matrixC17_31; +wire [`DWIDTH-1:0] matrixC18_0; +wire [`DWIDTH-1:0] matrixC18_1; +wire [`DWIDTH-1:0] matrixC18_2; +wire [`DWIDTH-1:0] matrixC18_3; +wire [`DWIDTH-1:0] matrixC18_4; +wire [`DWIDTH-1:0] matrixC18_5; +wire [`DWIDTH-1:0] matrixC18_6; +wire [`DWIDTH-1:0] matrixC18_7; +wire [`DWIDTH-1:0] matrixC18_8; +wire [`DWIDTH-1:0] matrixC18_9; +wire [`DWIDTH-1:0] matrixC18_10; +wire [`DWIDTH-1:0] matrixC18_11; +wire [`DWIDTH-1:0] matrixC18_12; +wire [`DWIDTH-1:0] matrixC18_13; +wire [`DWIDTH-1:0] matrixC18_14; +wire [`DWIDTH-1:0] matrixC18_15; +wire [`DWIDTH-1:0] matrixC18_16; +wire [`DWIDTH-1:0] matrixC18_17; +wire [`DWIDTH-1:0] matrixC18_18; +wire [`DWIDTH-1:0] matrixC18_19; +wire [`DWIDTH-1:0] matrixC18_20; +wire [`DWIDTH-1:0] matrixC18_21; +wire [`DWIDTH-1:0] matrixC18_22; +wire [`DWIDTH-1:0] matrixC18_23; +wire [`DWIDTH-1:0] matrixC18_24; +wire [`DWIDTH-1:0] matrixC18_25; +wire [`DWIDTH-1:0] matrixC18_26; +wire [`DWIDTH-1:0] matrixC18_27; +wire [`DWIDTH-1:0] matrixC18_28; +wire [`DWIDTH-1:0] matrixC18_29; +wire [`DWIDTH-1:0] matrixC18_30; +wire [`DWIDTH-1:0] matrixC18_31; +wire [`DWIDTH-1:0] matrixC19_0; +wire [`DWIDTH-1:0] matrixC19_1; +wire [`DWIDTH-1:0] matrixC19_2; +wire [`DWIDTH-1:0] matrixC19_3; +wire [`DWIDTH-1:0] matrixC19_4; +wire [`DWIDTH-1:0] matrixC19_5; +wire [`DWIDTH-1:0] matrixC19_6; +wire [`DWIDTH-1:0] matrixC19_7; +wire [`DWIDTH-1:0] matrixC19_8; +wire [`DWIDTH-1:0] matrixC19_9; +wire [`DWIDTH-1:0] matrixC19_10; +wire [`DWIDTH-1:0] matrixC19_11; +wire [`DWIDTH-1:0] matrixC19_12; +wire [`DWIDTH-1:0] matrixC19_13; +wire [`DWIDTH-1:0] matrixC19_14; +wire [`DWIDTH-1:0] matrixC19_15; +wire [`DWIDTH-1:0] matrixC19_16; +wire [`DWIDTH-1:0] matrixC19_17; +wire [`DWIDTH-1:0] matrixC19_18; +wire [`DWIDTH-1:0] matrixC19_19; +wire [`DWIDTH-1:0] matrixC19_20; +wire [`DWIDTH-1:0] matrixC19_21; +wire [`DWIDTH-1:0] matrixC19_22; +wire [`DWIDTH-1:0] matrixC19_23; +wire [`DWIDTH-1:0] matrixC19_24; +wire [`DWIDTH-1:0] matrixC19_25; +wire [`DWIDTH-1:0] matrixC19_26; +wire [`DWIDTH-1:0] matrixC19_27; +wire [`DWIDTH-1:0] matrixC19_28; +wire [`DWIDTH-1:0] matrixC19_29; +wire [`DWIDTH-1:0] matrixC19_30; +wire [`DWIDTH-1:0] matrixC19_31; +wire [`DWIDTH-1:0] matrixC20_0; +wire [`DWIDTH-1:0] matrixC20_1; +wire [`DWIDTH-1:0] matrixC20_2; +wire [`DWIDTH-1:0] matrixC20_3; +wire [`DWIDTH-1:0] matrixC20_4; +wire [`DWIDTH-1:0] matrixC20_5; +wire [`DWIDTH-1:0] matrixC20_6; +wire [`DWIDTH-1:0] matrixC20_7; +wire [`DWIDTH-1:0] matrixC20_8; +wire [`DWIDTH-1:0] matrixC20_9; +wire [`DWIDTH-1:0] matrixC20_10; +wire [`DWIDTH-1:0] matrixC20_11; +wire [`DWIDTH-1:0] matrixC20_12; +wire [`DWIDTH-1:0] matrixC20_13; +wire [`DWIDTH-1:0] matrixC20_14; +wire [`DWIDTH-1:0] matrixC20_15; +wire [`DWIDTH-1:0] matrixC20_16; +wire [`DWIDTH-1:0] matrixC20_17; +wire [`DWIDTH-1:0] matrixC20_18; +wire [`DWIDTH-1:0] matrixC20_19; +wire [`DWIDTH-1:0] matrixC20_20; +wire [`DWIDTH-1:0] matrixC20_21; +wire [`DWIDTH-1:0] matrixC20_22; +wire [`DWIDTH-1:0] matrixC20_23; +wire [`DWIDTH-1:0] matrixC20_24; +wire [`DWIDTH-1:0] matrixC20_25; +wire [`DWIDTH-1:0] matrixC20_26; +wire [`DWIDTH-1:0] matrixC20_27; +wire [`DWIDTH-1:0] matrixC20_28; +wire [`DWIDTH-1:0] matrixC20_29; +wire [`DWIDTH-1:0] matrixC20_30; +wire [`DWIDTH-1:0] matrixC20_31; +wire [`DWIDTH-1:0] matrixC21_0; +wire [`DWIDTH-1:0] matrixC21_1; +wire [`DWIDTH-1:0] matrixC21_2; +wire [`DWIDTH-1:0] matrixC21_3; +wire [`DWIDTH-1:0] matrixC21_4; +wire [`DWIDTH-1:0] matrixC21_5; +wire [`DWIDTH-1:0] matrixC21_6; +wire [`DWIDTH-1:0] matrixC21_7; +wire [`DWIDTH-1:0] matrixC21_8; +wire [`DWIDTH-1:0] matrixC21_9; +wire [`DWIDTH-1:0] matrixC21_10; +wire [`DWIDTH-1:0] matrixC21_11; +wire [`DWIDTH-1:0] matrixC21_12; +wire [`DWIDTH-1:0] matrixC21_13; +wire [`DWIDTH-1:0] matrixC21_14; +wire [`DWIDTH-1:0] matrixC21_15; +wire [`DWIDTH-1:0] matrixC21_16; +wire [`DWIDTH-1:0] matrixC21_17; +wire [`DWIDTH-1:0] matrixC21_18; +wire [`DWIDTH-1:0] matrixC21_19; +wire [`DWIDTH-1:0] matrixC21_20; +wire [`DWIDTH-1:0] matrixC21_21; +wire [`DWIDTH-1:0] matrixC21_22; +wire [`DWIDTH-1:0] matrixC21_23; +wire [`DWIDTH-1:0] matrixC21_24; +wire [`DWIDTH-1:0] matrixC21_25; +wire [`DWIDTH-1:0] matrixC21_26; +wire [`DWIDTH-1:0] matrixC21_27; +wire [`DWIDTH-1:0] matrixC21_28; +wire [`DWIDTH-1:0] matrixC21_29; +wire [`DWIDTH-1:0] matrixC21_30; +wire [`DWIDTH-1:0] matrixC21_31; +wire [`DWIDTH-1:0] matrixC22_0; +wire [`DWIDTH-1:0] matrixC22_1; +wire [`DWIDTH-1:0] matrixC22_2; +wire [`DWIDTH-1:0] matrixC22_3; +wire [`DWIDTH-1:0] matrixC22_4; +wire [`DWIDTH-1:0] matrixC22_5; +wire [`DWIDTH-1:0] matrixC22_6; +wire [`DWIDTH-1:0] matrixC22_7; +wire [`DWIDTH-1:0] matrixC22_8; +wire [`DWIDTH-1:0] matrixC22_9; +wire [`DWIDTH-1:0] matrixC22_10; +wire [`DWIDTH-1:0] matrixC22_11; +wire [`DWIDTH-1:0] matrixC22_12; +wire [`DWIDTH-1:0] matrixC22_13; +wire [`DWIDTH-1:0] matrixC22_14; +wire [`DWIDTH-1:0] matrixC22_15; +wire [`DWIDTH-1:0] matrixC22_16; +wire [`DWIDTH-1:0] matrixC22_17; +wire [`DWIDTH-1:0] matrixC22_18; +wire [`DWIDTH-1:0] matrixC22_19; +wire [`DWIDTH-1:0] matrixC22_20; +wire [`DWIDTH-1:0] matrixC22_21; +wire [`DWIDTH-1:0] matrixC22_22; +wire [`DWIDTH-1:0] matrixC22_23; +wire [`DWIDTH-1:0] matrixC22_24; +wire [`DWIDTH-1:0] matrixC22_25; +wire [`DWIDTH-1:0] matrixC22_26; +wire [`DWIDTH-1:0] matrixC22_27; +wire [`DWIDTH-1:0] matrixC22_28; +wire [`DWIDTH-1:0] matrixC22_29; +wire [`DWIDTH-1:0] matrixC22_30; +wire [`DWIDTH-1:0] matrixC22_31; +wire [`DWIDTH-1:0] matrixC23_0; +wire [`DWIDTH-1:0] matrixC23_1; +wire [`DWIDTH-1:0] matrixC23_2; +wire [`DWIDTH-1:0] matrixC23_3; +wire [`DWIDTH-1:0] matrixC23_4; +wire [`DWIDTH-1:0] matrixC23_5; +wire [`DWIDTH-1:0] matrixC23_6; +wire [`DWIDTH-1:0] matrixC23_7; +wire [`DWIDTH-1:0] matrixC23_8; +wire [`DWIDTH-1:0] matrixC23_9; +wire [`DWIDTH-1:0] matrixC23_10; +wire [`DWIDTH-1:0] matrixC23_11; +wire [`DWIDTH-1:0] matrixC23_12; +wire [`DWIDTH-1:0] matrixC23_13; +wire [`DWIDTH-1:0] matrixC23_14; +wire [`DWIDTH-1:0] matrixC23_15; +wire [`DWIDTH-1:0] matrixC23_16; +wire [`DWIDTH-1:0] matrixC23_17; +wire [`DWIDTH-1:0] matrixC23_18; +wire [`DWIDTH-1:0] matrixC23_19; +wire [`DWIDTH-1:0] matrixC23_20; +wire [`DWIDTH-1:0] matrixC23_21; +wire [`DWIDTH-1:0] matrixC23_22; +wire [`DWIDTH-1:0] matrixC23_23; +wire [`DWIDTH-1:0] matrixC23_24; +wire [`DWIDTH-1:0] matrixC23_25; +wire [`DWIDTH-1:0] matrixC23_26; +wire [`DWIDTH-1:0] matrixC23_27; +wire [`DWIDTH-1:0] matrixC23_28; +wire [`DWIDTH-1:0] matrixC23_29; +wire [`DWIDTH-1:0] matrixC23_30; +wire [`DWIDTH-1:0] matrixC23_31; +wire [`DWIDTH-1:0] matrixC24_0; +wire [`DWIDTH-1:0] matrixC24_1; +wire [`DWIDTH-1:0] matrixC24_2; +wire [`DWIDTH-1:0] matrixC24_3; +wire [`DWIDTH-1:0] matrixC24_4; +wire [`DWIDTH-1:0] matrixC24_5; +wire [`DWIDTH-1:0] matrixC24_6; +wire [`DWIDTH-1:0] matrixC24_7; +wire [`DWIDTH-1:0] matrixC24_8; +wire [`DWIDTH-1:0] matrixC24_9; +wire [`DWIDTH-1:0] matrixC24_10; +wire [`DWIDTH-1:0] matrixC24_11; +wire [`DWIDTH-1:0] matrixC24_12; +wire [`DWIDTH-1:0] matrixC24_13; +wire [`DWIDTH-1:0] matrixC24_14; +wire [`DWIDTH-1:0] matrixC24_15; +wire [`DWIDTH-1:0] matrixC24_16; +wire [`DWIDTH-1:0] matrixC24_17; +wire [`DWIDTH-1:0] matrixC24_18; +wire [`DWIDTH-1:0] matrixC24_19; +wire [`DWIDTH-1:0] matrixC24_20; +wire [`DWIDTH-1:0] matrixC24_21; +wire [`DWIDTH-1:0] matrixC24_22; +wire [`DWIDTH-1:0] matrixC24_23; +wire [`DWIDTH-1:0] matrixC24_24; +wire [`DWIDTH-1:0] matrixC24_25; +wire [`DWIDTH-1:0] matrixC24_26; +wire [`DWIDTH-1:0] matrixC24_27; +wire [`DWIDTH-1:0] matrixC24_28; +wire [`DWIDTH-1:0] matrixC24_29; +wire [`DWIDTH-1:0] matrixC24_30; +wire [`DWIDTH-1:0] matrixC24_31; +wire [`DWIDTH-1:0] matrixC25_0; +wire [`DWIDTH-1:0] matrixC25_1; +wire [`DWIDTH-1:0] matrixC25_2; +wire [`DWIDTH-1:0] matrixC25_3; +wire [`DWIDTH-1:0] matrixC25_4; +wire [`DWIDTH-1:0] matrixC25_5; +wire [`DWIDTH-1:0] matrixC25_6; +wire [`DWIDTH-1:0] matrixC25_7; +wire [`DWIDTH-1:0] matrixC25_8; +wire [`DWIDTH-1:0] matrixC25_9; +wire [`DWIDTH-1:0] matrixC25_10; +wire [`DWIDTH-1:0] matrixC25_11; +wire [`DWIDTH-1:0] matrixC25_12; +wire [`DWIDTH-1:0] matrixC25_13; +wire [`DWIDTH-1:0] matrixC25_14; +wire [`DWIDTH-1:0] matrixC25_15; +wire [`DWIDTH-1:0] matrixC25_16; +wire [`DWIDTH-1:0] matrixC25_17; +wire [`DWIDTH-1:0] matrixC25_18; +wire [`DWIDTH-1:0] matrixC25_19; +wire [`DWIDTH-1:0] matrixC25_20; +wire [`DWIDTH-1:0] matrixC25_21; +wire [`DWIDTH-1:0] matrixC25_22; +wire [`DWIDTH-1:0] matrixC25_23; +wire [`DWIDTH-1:0] matrixC25_24; +wire [`DWIDTH-1:0] matrixC25_25; +wire [`DWIDTH-1:0] matrixC25_26; +wire [`DWIDTH-1:0] matrixC25_27; +wire [`DWIDTH-1:0] matrixC25_28; +wire [`DWIDTH-1:0] matrixC25_29; +wire [`DWIDTH-1:0] matrixC25_30; +wire [`DWIDTH-1:0] matrixC25_31; +wire [`DWIDTH-1:0] matrixC26_0; +wire [`DWIDTH-1:0] matrixC26_1; +wire [`DWIDTH-1:0] matrixC26_2; +wire [`DWIDTH-1:0] matrixC26_3; +wire [`DWIDTH-1:0] matrixC26_4; +wire [`DWIDTH-1:0] matrixC26_5; +wire [`DWIDTH-1:0] matrixC26_6; +wire [`DWIDTH-1:0] matrixC26_7; +wire [`DWIDTH-1:0] matrixC26_8; +wire [`DWIDTH-1:0] matrixC26_9; +wire [`DWIDTH-1:0] matrixC26_10; +wire [`DWIDTH-1:0] matrixC26_11; +wire [`DWIDTH-1:0] matrixC26_12; +wire [`DWIDTH-1:0] matrixC26_13; +wire [`DWIDTH-1:0] matrixC26_14; +wire [`DWIDTH-1:0] matrixC26_15; +wire [`DWIDTH-1:0] matrixC26_16; +wire [`DWIDTH-1:0] matrixC26_17; +wire [`DWIDTH-1:0] matrixC26_18; +wire [`DWIDTH-1:0] matrixC26_19; +wire [`DWIDTH-1:0] matrixC26_20; +wire [`DWIDTH-1:0] matrixC26_21; +wire [`DWIDTH-1:0] matrixC26_22; +wire [`DWIDTH-1:0] matrixC26_23; +wire [`DWIDTH-1:0] matrixC26_24; +wire [`DWIDTH-1:0] matrixC26_25; +wire [`DWIDTH-1:0] matrixC26_26; +wire [`DWIDTH-1:0] matrixC26_27; +wire [`DWIDTH-1:0] matrixC26_28; +wire [`DWIDTH-1:0] matrixC26_29; +wire [`DWIDTH-1:0] matrixC26_30; +wire [`DWIDTH-1:0] matrixC26_31; +wire [`DWIDTH-1:0] matrixC27_0; +wire [`DWIDTH-1:0] matrixC27_1; +wire [`DWIDTH-1:0] matrixC27_2; +wire [`DWIDTH-1:0] matrixC27_3; +wire [`DWIDTH-1:0] matrixC27_4; +wire [`DWIDTH-1:0] matrixC27_5; +wire [`DWIDTH-1:0] matrixC27_6; +wire [`DWIDTH-1:0] matrixC27_7; +wire [`DWIDTH-1:0] matrixC27_8; +wire [`DWIDTH-1:0] matrixC27_9; +wire [`DWIDTH-1:0] matrixC27_10; +wire [`DWIDTH-1:0] matrixC27_11; +wire [`DWIDTH-1:0] matrixC27_12; +wire [`DWIDTH-1:0] matrixC27_13; +wire [`DWIDTH-1:0] matrixC27_14; +wire [`DWIDTH-1:0] matrixC27_15; +wire [`DWIDTH-1:0] matrixC27_16; +wire [`DWIDTH-1:0] matrixC27_17; +wire [`DWIDTH-1:0] matrixC27_18; +wire [`DWIDTH-1:0] matrixC27_19; +wire [`DWIDTH-1:0] matrixC27_20; +wire [`DWIDTH-1:0] matrixC27_21; +wire [`DWIDTH-1:0] matrixC27_22; +wire [`DWIDTH-1:0] matrixC27_23; +wire [`DWIDTH-1:0] matrixC27_24; +wire [`DWIDTH-1:0] matrixC27_25; +wire [`DWIDTH-1:0] matrixC27_26; +wire [`DWIDTH-1:0] matrixC27_27; +wire [`DWIDTH-1:0] matrixC27_28; +wire [`DWIDTH-1:0] matrixC27_29; +wire [`DWIDTH-1:0] matrixC27_30; +wire [`DWIDTH-1:0] matrixC27_31; +wire [`DWIDTH-1:0] matrixC28_0; +wire [`DWIDTH-1:0] matrixC28_1; +wire [`DWIDTH-1:0] matrixC28_2; +wire [`DWIDTH-1:0] matrixC28_3; +wire [`DWIDTH-1:0] matrixC28_4; +wire [`DWIDTH-1:0] matrixC28_5; +wire [`DWIDTH-1:0] matrixC28_6; +wire [`DWIDTH-1:0] matrixC28_7; +wire [`DWIDTH-1:0] matrixC28_8; +wire [`DWIDTH-1:0] matrixC28_9; +wire [`DWIDTH-1:0] matrixC28_10; +wire [`DWIDTH-1:0] matrixC28_11; +wire [`DWIDTH-1:0] matrixC28_12; +wire [`DWIDTH-1:0] matrixC28_13; +wire [`DWIDTH-1:0] matrixC28_14; +wire [`DWIDTH-1:0] matrixC28_15; +wire [`DWIDTH-1:0] matrixC28_16; +wire [`DWIDTH-1:0] matrixC28_17; +wire [`DWIDTH-1:0] matrixC28_18; +wire [`DWIDTH-1:0] matrixC28_19; +wire [`DWIDTH-1:0] matrixC28_20; +wire [`DWIDTH-1:0] matrixC28_21; +wire [`DWIDTH-1:0] matrixC28_22; +wire [`DWIDTH-1:0] matrixC28_23; +wire [`DWIDTH-1:0] matrixC28_24; +wire [`DWIDTH-1:0] matrixC28_25; +wire [`DWIDTH-1:0] matrixC28_26; +wire [`DWIDTH-1:0] matrixC28_27; +wire [`DWIDTH-1:0] matrixC28_28; +wire [`DWIDTH-1:0] matrixC28_29; +wire [`DWIDTH-1:0] matrixC28_30; +wire [`DWIDTH-1:0] matrixC28_31; +wire [`DWIDTH-1:0] matrixC29_0; +wire [`DWIDTH-1:0] matrixC29_1; +wire [`DWIDTH-1:0] matrixC29_2; +wire [`DWIDTH-1:0] matrixC29_3; +wire [`DWIDTH-1:0] matrixC29_4; +wire [`DWIDTH-1:0] matrixC29_5; +wire [`DWIDTH-1:0] matrixC29_6; +wire [`DWIDTH-1:0] matrixC29_7; +wire [`DWIDTH-1:0] matrixC29_8; +wire [`DWIDTH-1:0] matrixC29_9; +wire [`DWIDTH-1:0] matrixC29_10; +wire [`DWIDTH-1:0] matrixC29_11; +wire [`DWIDTH-1:0] matrixC29_12; +wire [`DWIDTH-1:0] matrixC29_13; +wire [`DWIDTH-1:0] matrixC29_14; +wire [`DWIDTH-1:0] matrixC29_15; +wire [`DWIDTH-1:0] matrixC29_16; +wire [`DWIDTH-1:0] matrixC29_17; +wire [`DWIDTH-1:0] matrixC29_18; +wire [`DWIDTH-1:0] matrixC29_19; +wire [`DWIDTH-1:0] matrixC29_20; +wire [`DWIDTH-1:0] matrixC29_21; +wire [`DWIDTH-1:0] matrixC29_22; +wire [`DWIDTH-1:0] matrixC29_23; +wire [`DWIDTH-1:0] matrixC29_24; +wire [`DWIDTH-1:0] matrixC29_25; +wire [`DWIDTH-1:0] matrixC29_26; +wire [`DWIDTH-1:0] matrixC29_27; +wire [`DWIDTH-1:0] matrixC29_28; +wire [`DWIDTH-1:0] matrixC29_29; +wire [`DWIDTH-1:0] matrixC29_30; +wire [`DWIDTH-1:0] matrixC29_31; +wire [`DWIDTH-1:0] matrixC30_0; +wire [`DWIDTH-1:0] matrixC30_1; +wire [`DWIDTH-1:0] matrixC30_2; +wire [`DWIDTH-1:0] matrixC30_3; +wire [`DWIDTH-1:0] matrixC30_4; +wire [`DWIDTH-1:0] matrixC30_5; +wire [`DWIDTH-1:0] matrixC30_6; +wire [`DWIDTH-1:0] matrixC30_7; +wire [`DWIDTH-1:0] matrixC30_8; +wire [`DWIDTH-1:0] matrixC30_9; +wire [`DWIDTH-1:0] matrixC30_10; +wire [`DWIDTH-1:0] matrixC30_11; +wire [`DWIDTH-1:0] matrixC30_12; +wire [`DWIDTH-1:0] matrixC30_13; +wire [`DWIDTH-1:0] matrixC30_14; +wire [`DWIDTH-1:0] matrixC30_15; +wire [`DWIDTH-1:0] matrixC30_16; +wire [`DWIDTH-1:0] matrixC30_17; +wire [`DWIDTH-1:0] matrixC30_18; +wire [`DWIDTH-1:0] matrixC30_19; +wire [`DWIDTH-1:0] matrixC30_20; +wire [`DWIDTH-1:0] matrixC30_21; +wire [`DWIDTH-1:0] matrixC30_22; +wire [`DWIDTH-1:0] matrixC30_23; +wire [`DWIDTH-1:0] matrixC30_24; +wire [`DWIDTH-1:0] matrixC30_25; +wire [`DWIDTH-1:0] matrixC30_26; +wire [`DWIDTH-1:0] matrixC30_27; +wire [`DWIDTH-1:0] matrixC30_28; +wire [`DWIDTH-1:0] matrixC30_29; +wire [`DWIDTH-1:0] matrixC30_30; +wire [`DWIDTH-1:0] matrixC30_31; +wire [`DWIDTH-1:0] matrixC31_0; +wire [`DWIDTH-1:0] matrixC31_1; +wire [`DWIDTH-1:0] matrixC31_2; +wire [`DWIDTH-1:0] matrixC31_3; +wire [`DWIDTH-1:0] matrixC31_4; +wire [`DWIDTH-1:0] matrixC31_5; +wire [`DWIDTH-1:0] matrixC31_6; +wire [`DWIDTH-1:0] matrixC31_7; +wire [`DWIDTH-1:0] matrixC31_8; +wire [`DWIDTH-1:0] matrixC31_9; +wire [`DWIDTH-1:0] matrixC31_10; +wire [`DWIDTH-1:0] matrixC31_11; +wire [`DWIDTH-1:0] matrixC31_12; +wire [`DWIDTH-1:0] matrixC31_13; +wire [`DWIDTH-1:0] matrixC31_14; +wire [`DWIDTH-1:0] matrixC31_15; +wire [`DWIDTH-1:0] matrixC31_16; +wire [`DWIDTH-1:0] matrixC31_17; +wire [`DWIDTH-1:0] matrixC31_18; +wire [`DWIDTH-1:0] matrixC31_19; +wire [`DWIDTH-1:0] matrixC31_20; +wire [`DWIDTH-1:0] matrixC31_21; +wire [`DWIDTH-1:0] matrixC31_22; +wire [`DWIDTH-1:0] matrixC31_23; +wire [`DWIDTH-1:0] matrixC31_24; +wire [`DWIDTH-1:0] matrixC31_25; +wire [`DWIDTH-1:0] matrixC31_26; +wire [`DWIDTH-1:0] matrixC31_27; +wire [`DWIDTH-1:0] matrixC31_28; +wire [`DWIDTH-1:0] matrixC31_29; +wire [`DWIDTH-1:0] matrixC31_30; +wire [`DWIDTH-1:0] matrixC31_31; + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +systolic_pe_matrix u_systolic_pe_matrix( + .reset(reset), + .clk(clk), + .pe_reset(pe_reset), + .b_data_sel(b_data_sel), + .b_data_valid_ping(b_data_valid_ping), + .b_data_valid_pong(b_data_valid_pong), + .a0(a0), + .a1(a1), + .a2(a2), + .a3(a3), + .a4(a4), + .a5(a5), + .a6(a6), + .a7(a7), + .a8(a8), + .a9(a9), + .a10(a10), + .a11(a11), + .a12(a12), + .a13(a13), + .a14(a14), + .a15(a15), + .a16(a16), + .a17(a17), + .a18(a18), + .a19(a19), + .a20(a20), + .a21(a21), + .a22(a22), + .a23(a23), + .a24(a24), + .a25(a25), + .a26(a26), + .a27(a27), + .a28(a28), + .a29(a29), + .a30(a30), + .a31(a31), + .b0(b0), + .b1(b1), + .b2(b2), + .b3(b3), + .b4(b4), + .b5(b5), + .b6(b6), + .b7(b7), + .b8(b8), + .b9(b9), + .b10(b10), + .b11(b11), + .b12(b12), + .b13(b13), + .b14(b14), + .b15(b15), + .b16(b16), + .b17(b17), + .b18(b18), + .b19(b19), + .b20(b20), + .b21(b21), + .b22(b22), + .b23(b23), + .b24(b24), + .b25(b25), + .b26(b26), + .b27(b27), + .b28(b28), + .b29(b29), + .b30(b30), + .b31(b31), + .c0(c0), + .c1(c1), + .c2(c2), + .c3(c3), + .c4(c4), + .c5(c5), + .c6(c6), + .c7(c7), + .c8(c8), + .c9(c9), + .c10(c10), + .c11(c11), + .c12(c12), + .c13(c13), + .c14(c14), + .c15(c15), + .c16(c16), + .c17(c17), + .c18(c18), + .c19(c19), + .c20(c20), + .c21(c21), + .c22(c22), + .c23(c23), + .c24(c24), + .c25(c25), + .c26(c26), + .c27(c27), + .c28(c28), + .c29(c29), + .c30(c30), + .c31(c31), + .matrixC0_0(matrixC0_0), + .matrixC0_1(matrixC0_1), + .matrixC0_2(matrixC0_2), + .matrixC0_3(matrixC0_3), + .matrixC0_4(matrixC0_4), + .matrixC0_5(matrixC0_5), + .matrixC0_6(matrixC0_6), + .matrixC0_7(matrixC0_7), + .matrixC0_8(matrixC0_8), + .matrixC0_9(matrixC0_9), + .matrixC0_10(matrixC0_10), + .matrixC0_11(matrixC0_11), + .matrixC0_12(matrixC0_12), + .matrixC0_13(matrixC0_13), + .matrixC0_14(matrixC0_14), + .matrixC0_15(matrixC0_15), + .matrixC0_16(matrixC0_16), + .matrixC0_17(matrixC0_17), + .matrixC0_18(matrixC0_18), + .matrixC0_19(matrixC0_19), + .matrixC0_20(matrixC0_20), + .matrixC0_21(matrixC0_21), + .matrixC0_22(matrixC0_22), + .matrixC0_23(matrixC0_23), + .matrixC0_24(matrixC0_24), + .matrixC0_25(matrixC0_25), + .matrixC0_26(matrixC0_26), + .matrixC0_27(matrixC0_27), + .matrixC0_28(matrixC0_28), + .matrixC0_29(matrixC0_29), + .matrixC0_30(matrixC0_30), + .matrixC0_31(matrixC0_31), + .matrixC1_0(matrixC1_0), + .matrixC1_1(matrixC1_1), + .matrixC1_2(matrixC1_2), + .matrixC1_3(matrixC1_3), + .matrixC1_4(matrixC1_4), + .matrixC1_5(matrixC1_5), + .matrixC1_6(matrixC1_6), + .matrixC1_7(matrixC1_7), + .matrixC1_8(matrixC1_8), + .matrixC1_9(matrixC1_9), + .matrixC1_10(matrixC1_10), + .matrixC1_11(matrixC1_11), + .matrixC1_12(matrixC1_12), + .matrixC1_13(matrixC1_13), + .matrixC1_14(matrixC1_14), + .matrixC1_15(matrixC1_15), + .matrixC1_16(matrixC1_16), + .matrixC1_17(matrixC1_17), + .matrixC1_18(matrixC1_18), + .matrixC1_19(matrixC1_19), + .matrixC1_20(matrixC1_20), + .matrixC1_21(matrixC1_21), + .matrixC1_22(matrixC1_22), + .matrixC1_23(matrixC1_23), + .matrixC1_24(matrixC1_24), + .matrixC1_25(matrixC1_25), + .matrixC1_26(matrixC1_26), + .matrixC1_27(matrixC1_27), + .matrixC1_28(matrixC1_28), + .matrixC1_29(matrixC1_29), + .matrixC1_30(matrixC1_30), + .matrixC1_31(matrixC1_31), + .matrixC2_0(matrixC2_0), + .matrixC2_1(matrixC2_1), + .matrixC2_2(matrixC2_2), + .matrixC2_3(matrixC2_3), + .matrixC2_4(matrixC2_4), + .matrixC2_5(matrixC2_5), + .matrixC2_6(matrixC2_6), + .matrixC2_7(matrixC2_7), + .matrixC2_8(matrixC2_8), + .matrixC2_9(matrixC2_9), + .matrixC2_10(matrixC2_10), + .matrixC2_11(matrixC2_11), + .matrixC2_12(matrixC2_12), + .matrixC2_13(matrixC2_13), + .matrixC2_14(matrixC2_14), + .matrixC2_15(matrixC2_15), + .matrixC2_16(matrixC2_16), + .matrixC2_17(matrixC2_17), + .matrixC2_18(matrixC2_18), + .matrixC2_19(matrixC2_19), + .matrixC2_20(matrixC2_20), + .matrixC2_21(matrixC2_21), + .matrixC2_22(matrixC2_22), + .matrixC2_23(matrixC2_23), + .matrixC2_24(matrixC2_24), + .matrixC2_25(matrixC2_25), + .matrixC2_26(matrixC2_26), + .matrixC2_27(matrixC2_27), + .matrixC2_28(matrixC2_28), + .matrixC2_29(matrixC2_29), + .matrixC2_30(matrixC2_30), + .matrixC2_31(matrixC2_31), + .matrixC3_0(matrixC3_0), + .matrixC3_1(matrixC3_1), + .matrixC3_2(matrixC3_2), + .matrixC3_3(matrixC3_3), + .matrixC3_4(matrixC3_4), + .matrixC3_5(matrixC3_5), + .matrixC3_6(matrixC3_6), + .matrixC3_7(matrixC3_7), + .matrixC3_8(matrixC3_8), + .matrixC3_9(matrixC3_9), + .matrixC3_10(matrixC3_10), + .matrixC3_11(matrixC3_11), + .matrixC3_12(matrixC3_12), + .matrixC3_13(matrixC3_13), + .matrixC3_14(matrixC3_14), + .matrixC3_15(matrixC3_15), + .matrixC3_16(matrixC3_16), + .matrixC3_17(matrixC3_17), + .matrixC3_18(matrixC3_18), + .matrixC3_19(matrixC3_19), + .matrixC3_20(matrixC3_20), + .matrixC3_21(matrixC3_21), + .matrixC3_22(matrixC3_22), + .matrixC3_23(matrixC3_23), + .matrixC3_24(matrixC3_24), + .matrixC3_25(matrixC3_25), + .matrixC3_26(matrixC3_26), + .matrixC3_27(matrixC3_27), + .matrixC3_28(matrixC3_28), + .matrixC3_29(matrixC3_29), + .matrixC3_30(matrixC3_30), + .matrixC3_31(matrixC3_31), + .matrixC4_0(matrixC4_0), + .matrixC4_1(matrixC4_1), + .matrixC4_2(matrixC4_2), + .matrixC4_3(matrixC4_3), + .matrixC4_4(matrixC4_4), + .matrixC4_5(matrixC4_5), + .matrixC4_6(matrixC4_6), + .matrixC4_7(matrixC4_7), + .matrixC4_8(matrixC4_8), + .matrixC4_9(matrixC4_9), + .matrixC4_10(matrixC4_10), + .matrixC4_11(matrixC4_11), + .matrixC4_12(matrixC4_12), + .matrixC4_13(matrixC4_13), + .matrixC4_14(matrixC4_14), + .matrixC4_15(matrixC4_15), + .matrixC4_16(matrixC4_16), + .matrixC4_17(matrixC4_17), + .matrixC4_18(matrixC4_18), + .matrixC4_19(matrixC4_19), + .matrixC4_20(matrixC4_20), + .matrixC4_21(matrixC4_21), + .matrixC4_22(matrixC4_22), + .matrixC4_23(matrixC4_23), + .matrixC4_24(matrixC4_24), + .matrixC4_25(matrixC4_25), + .matrixC4_26(matrixC4_26), + .matrixC4_27(matrixC4_27), + .matrixC4_28(matrixC4_28), + .matrixC4_29(matrixC4_29), + .matrixC4_30(matrixC4_30), + .matrixC4_31(matrixC4_31), + .matrixC5_0(matrixC5_0), + .matrixC5_1(matrixC5_1), + .matrixC5_2(matrixC5_2), + .matrixC5_3(matrixC5_3), + .matrixC5_4(matrixC5_4), + .matrixC5_5(matrixC5_5), + .matrixC5_6(matrixC5_6), + .matrixC5_7(matrixC5_7), + .matrixC5_8(matrixC5_8), + .matrixC5_9(matrixC5_9), + .matrixC5_10(matrixC5_10), + .matrixC5_11(matrixC5_11), + .matrixC5_12(matrixC5_12), + .matrixC5_13(matrixC5_13), + .matrixC5_14(matrixC5_14), + .matrixC5_15(matrixC5_15), + .matrixC5_16(matrixC5_16), + .matrixC5_17(matrixC5_17), + .matrixC5_18(matrixC5_18), + .matrixC5_19(matrixC5_19), + .matrixC5_20(matrixC5_20), + .matrixC5_21(matrixC5_21), + .matrixC5_22(matrixC5_22), + .matrixC5_23(matrixC5_23), + .matrixC5_24(matrixC5_24), + .matrixC5_25(matrixC5_25), + .matrixC5_26(matrixC5_26), + .matrixC5_27(matrixC5_27), + .matrixC5_28(matrixC5_28), + .matrixC5_29(matrixC5_29), + .matrixC5_30(matrixC5_30), + .matrixC5_31(matrixC5_31), + .matrixC6_0(matrixC6_0), + .matrixC6_1(matrixC6_1), + .matrixC6_2(matrixC6_2), + .matrixC6_3(matrixC6_3), + .matrixC6_4(matrixC6_4), + .matrixC6_5(matrixC6_5), + .matrixC6_6(matrixC6_6), + .matrixC6_7(matrixC6_7), + .matrixC6_8(matrixC6_8), + .matrixC6_9(matrixC6_9), + .matrixC6_10(matrixC6_10), + .matrixC6_11(matrixC6_11), + .matrixC6_12(matrixC6_12), + .matrixC6_13(matrixC6_13), + .matrixC6_14(matrixC6_14), + .matrixC6_15(matrixC6_15), + .matrixC6_16(matrixC6_16), + .matrixC6_17(matrixC6_17), + .matrixC6_18(matrixC6_18), + .matrixC6_19(matrixC6_19), + .matrixC6_20(matrixC6_20), + .matrixC6_21(matrixC6_21), + .matrixC6_22(matrixC6_22), + .matrixC6_23(matrixC6_23), + .matrixC6_24(matrixC6_24), + .matrixC6_25(matrixC6_25), + .matrixC6_26(matrixC6_26), + .matrixC6_27(matrixC6_27), + .matrixC6_28(matrixC6_28), + .matrixC6_29(matrixC6_29), + .matrixC6_30(matrixC6_30), + .matrixC6_31(matrixC6_31), + .matrixC7_0(matrixC7_0), + .matrixC7_1(matrixC7_1), + .matrixC7_2(matrixC7_2), + .matrixC7_3(matrixC7_3), + .matrixC7_4(matrixC7_4), + .matrixC7_5(matrixC7_5), + .matrixC7_6(matrixC7_6), + .matrixC7_7(matrixC7_7), + .matrixC7_8(matrixC7_8), + .matrixC7_9(matrixC7_9), + .matrixC7_10(matrixC7_10), + .matrixC7_11(matrixC7_11), + .matrixC7_12(matrixC7_12), + .matrixC7_13(matrixC7_13), + .matrixC7_14(matrixC7_14), + .matrixC7_15(matrixC7_15), + .matrixC7_16(matrixC7_16), + .matrixC7_17(matrixC7_17), + .matrixC7_18(matrixC7_18), + .matrixC7_19(matrixC7_19), + .matrixC7_20(matrixC7_20), + .matrixC7_21(matrixC7_21), + .matrixC7_22(matrixC7_22), + .matrixC7_23(matrixC7_23), + .matrixC7_24(matrixC7_24), + .matrixC7_25(matrixC7_25), + .matrixC7_26(matrixC7_26), + .matrixC7_27(matrixC7_27), + .matrixC7_28(matrixC7_28), + .matrixC7_29(matrixC7_29), + .matrixC7_30(matrixC7_30), + .matrixC7_31(matrixC7_31), + .matrixC8_0(matrixC8_0), + .matrixC8_1(matrixC8_1), + .matrixC8_2(matrixC8_2), + .matrixC8_3(matrixC8_3), + .matrixC8_4(matrixC8_4), + .matrixC8_5(matrixC8_5), + .matrixC8_6(matrixC8_6), + .matrixC8_7(matrixC8_7), + .matrixC8_8(matrixC8_8), + .matrixC8_9(matrixC8_9), + .matrixC8_10(matrixC8_10), + .matrixC8_11(matrixC8_11), + .matrixC8_12(matrixC8_12), + .matrixC8_13(matrixC8_13), + .matrixC8_14(matrixC8_14), + .matrixC8_15(matrixC8_15), + .matrixC8_16(matrixC8_16), + .matrixC8_17(matrixC8_17), + .matrixC8_18(matrixC8_18), + .matrixC8_19(matrixC8_19), + .matrixC8_20(matrixC8_20), + .matrixC8_21(matrixC8_21), + .matrixC8_22(matrixC8_22), + .matrixC8_23(matrixC8_23), + .matrixC8_24(matrixC8_24), + .matrixC8_25(matrixC8_25), + .matrixC8_26(matrixC8_26), + .matrixC8_27(matrixC8_27), + .matrixC8_28(matrixC8_28), + .matrixC8_29(matrixC8_29), + .matrixC8_30(matrixC8_30), + .matrixC8_31(matrixC8_31), + .matrixC9_0(matrixC9_0), + .matrixC9_1(matrixC9_1), + .matrixC9_2(matrixC9_2), + .matrixC9_3(matrixC9_3), + .matrixC9_4(matrixC9_4), + .matrixC9_5(matrixC9_5), + .matrixC9_6(matrixC9_6), + .matrixC9_7(matrixC9_7), + .matrixC9_8(matrixC9_8), + .matrixC9_9(matrixC9_9), + .matrixC9_10(matrixC9_10), + .matrixC9_11(matrixC9_11), + .matrixC9_12(matrixC9_12), + .matrixC9_13(matrixC9_13), + .matrixC9_14(matrixC9_14), + .matrixC9_15(matrixC9_15), + .matrixC9_16(matrixC9_16), + .matrixC9_17(matrixC9_17), + .matrixC9_18(matrixC9_18), + .matrixC9_19(matrixC9_19), + .matrixC9_20(matrixC9_20), + .matrixC9_21(matrixC9_21), + .matrixC9_22(matrixC9_22), + .matrixC9_23(matrixC9_23), + .matrixC9_24(matrixC9_24), + .matrixC9_25(matrixC9_25), + .matrixC9_26(matrixC9_26), + .matrixC9_27(matrixC9_27), + .matrixC9_28(matrixC9_28), + .matrixC9_29(matrixC9_29), + .matrixC9_30(matrixC9_30), + .matrixC9_31(matrixC9_31), + .matrixC10_0(matrixC10_0), + .matrixC10_1(matrixC10_1), + .matrixC10_2(matrixC10_2), + .matrixC10_3(matrixC10_3), + .matrixC10_4(matrixC10_4), + .matrixC10_5(matrixC10_5), + .matrixC10_6(matrixC10_6), + .matrixC10_7(matrixC10_7), + .matrixC10_8(matrixC10_8), + .matrixC10_9(matrixC10_9), + .matrixC10_10(matrixC10_10), + .matrixC10_11(matrixC10_11), + .matrixC10_12(matrixC10_12), + .matrixC10_13(matrixC10_13), + .matrixC10_14(matrixC10_14), + .matrixC10_15(matrixC10_15), + .matrixC10_16(matrixC10_16), + .matrixC10_17(matrixC10_17), + .matrixC10_18(matrixC10_18), + .matrixC10_19(matrixC10_19), + .matrixC10_20(matrixC10_20), + .matrixC10_21(matrixC10_21), + .matrixC10_22(matrixC10_22), + .matrixC10_23(matrixC10_23), + .matrixC10_24(matrixC10_24), + .matrixC10_25(matrixC10_25), + .matrixC10_26(matrixC10_26), + .matrixC10_27(matrixC10_27), + .matrixC10_28(matrixC10_28), + .matrixC10_29(matrixC10_29), + .matrixC10_30(matrixC10_30), + .matrixC10_31(matrixC10_31), + .matrixC11_0(matrixC11_0), + .matrixC11_1(matrixC11_1), + .matrixC11_2(matrixC11_2), + .matrixC11_3(matrixC11_3), + .matrixC11_4(matrixC11_4), + .matrixC11_5(matrixC11_5), + .matrixC11_6(matrixC11_6), + .matrixC11_7(matrixC11_7), + .matrixC11_8(matrixC11_8), + .matrixC11_9(matrixC11_9), + .matrixC11_10(matrixC11_10), + .matrixC11_11(matrixC11_11), + .matrixC11_12(matrixC11_12), + .matrixC11_13(matrixC11_13), + .matrixC11_14(matrixC11_14), + .matrixC11_15(matrixC11_15), + .matrixC11_16(matrixC11_16), + .matrixC11_17(matrixC11_17), + .matrixC11_18(matrixC11_18), + .matrixC11_19(matrixC11_19), + .matrixC11_20(matrixC11_20), + .matrixC11_21(matrixC11_21), + .matrixC11_22(matrixC11_22), + .matrixC11_23(matrixC11_23), + .matrixC11_24(matrixC11_24), + .matrixC11_25(matrixC11_25), + .matrixC11_26(matrixC11_26), + .matrixC11_27(matrixC11_27), + .matrixC11_28(matrixC11_28), + .matrixC11_29(matrixC11_29), + .matrixC11_30(matrixC11_30), + .matrixC11_31(matrixC11_31), + .matrixC12_0(matrixC12_0), + .matrixC12_1(matrixC12_1), + .matrixC12_2(matrixC12_2), + .matrixC12_3(matrixC12_3), + .matrixC12_4(matrixC12_4), + .matrixC12_5(matrixC12_5), + .matrixC12_6(matrixC12_6), + .matrixC12_7(matrixC12_7), + .matrixC12_8(matrixC12_8), + .matrixC12_9(matrixC12_9), + .matrixC12_10(matrixC12_10), + .matrixC12_11(matrixC12_11), + .matrixC12_12(matrixC12_12), + .matrixC12_13(matrixC12_13), + .matrixC12_14(matrixC12_14), + .matrixC12_15(matrixC12_15), + .matrixC12_16(matrixC12_16), + .matrixC12_17(matrixC12_17), + .matrixC12_18(matrixC12_18), + .matrixC12_19(matrixC12_19), + .matrixC12_20(matrixC12_20), + .matrixC12_21(matrixC12_21), + .matrixC12_22(matrixC12_22), + .matrixC12_23(matrixC12_23), + .matrixC12_24(matrixC12_24), + .matrixC12_25(matrixC12_25), + .matrixC12_26(matrixC12_26), + .matrixC12_27(matrixC12_27), + .matrixC12_28(matrixC12_28), + .matrixC12_29(matrixC12_29), + .matrixC12_30(matrixC12_30), + .matrixC12_31(matrixC12_31), + .matrixC13_0(matrixC13_0), + .matrixC13_1(matrixC13_1), + .matrixC13_2(matrixC13_2), + .matrixC13_3(matrixC13_3), + .matrixC13_4(matrixC13_4), + .matrixC13_5(matrixC13_5), + .matrixC13_6(matrixC13_6), + .matrixC13_7(matrixC13_7), + .matrixC13_8(matrixC13_8), + .matrixC13_9(matrixC13_9), + .matrixC13_10(matrixC13_10), + .matrixC13_11(matrixC13_11), + .matrixC13_12(matrixC13_12), + .matrixC13_13(matrixC13_13), + .matrixC13_14(matrixC13_14), + .matrixC13_15(matrixC13_15), + .matrixC13_16(matrixC13_16), + .matrixC13_17(matrixC13_17), + .matrixC13_18(matrixC13_18), + .matrixC13_19(matrixC13_19), + .matrixC13_20(matrixC13_20), + .matrixC13_21(matrixC13_21), + .matrixC13_22(matrixC13_22), + .matrixC13_23(matrixC13_23), + .matrixC13_24(matrixC13_24), + .matrixC13_25(matrixC13_25), + .matrixC13_26(matrixC13_26), + .matrixC13_27(matrixC13_27), + .matrixC13_28(matrixC13_28), + .matrixC13_29(matrixC13_29), + .matrixC13_30(matrixC13_30), + .matrixC13_31(matrixC13_31), + .matrixC14_0(matrixC14_0), + .matrixC14_1(matrixC14_1), + .matrixC14_2(matrixC14_2), + .matrixC14_3(matrixC14_3), + .matrixC14_4(matrixC14_4), + .matrixC14_5(matrixC14_5), + .matrixC14_6(matrixC14_6), + .matrixC14_7(matrixC14_7), + .matrixC14_8(matrixC14_8), + .matrixC14_9(matrixC14_9), + .matrixC14_10(matrixC14_10), + .matrixC14_11(matrixC14_11), + .matrixC14_12(matrixC14_12), + .matrixC14_13(matrixC14_13), + .matrixC14_14(matrixC14_14), + .matrixC14_15(matrixC14_15), + .matrixC14_16(matrixC14_16), + .matrixC14_17(matrixC14_17), + .matrixC14_18(matrixC14_18), + .matrixC14_19(matrixC14_19), + .matrixC14_20(matrixC14_20), + .matrixC14_21(matrixC14_21), + .matrixC14_22(matrixC14_22), + .matrixC14_23(matrixC14_23), + .matrixC14_24(matrixC14_24), + .matrixC14_25(matrixC14_25), + .matrixC14_26(matrixC14_26), + .matrixC14_27(matrixC14_27), + .matrixC14_28(matrixC14_28), + .matrixC14_29(matrixC14_29), + .matrixC14_30(matrixC14_30), + .matrixC14_31(matrixC14_31), + .matrixC15_0(matrixC15_0), + .matrixC15_1(matrixC15_1), + .matrixC15_2(matrixC15_2), + .matrixC15_3(matrixC15_3), + .matrixC15_4(matrixC15_4), + .matrixC15_5(matrixC15_5), + .matrixC15_6(matrixC15_6), + .matrixC15_7(matrixC15_7), + .matrixC15_8(matrixC15_8), + .matrixC15_9(matrixC15_9), + .matrixC15_10(matrixC15_10), + .matrixC15_11(matrixC15_11), + .matrixC15_12(matrixC15_12), + .matrixC15_13(matrixC15_13), + .matrixC15_14(matrixC15_14), + .matrixC15_15(matrixC15_15), + .matrixC15_16(matrixC15_16), + .matrixC15_17(matrixC15_17), + .matrixC15_18(matrixC15_18), + .matrixC15_19(matrixC15_19), + .matrixC15_20(matrixC15_20), + .matrixC15_21(matrixC15_21), + .matrixC15_22(matrixC15_22), + .matrixC15_23(matrixC15_23), + .matrixC15_24(matrixC15_24), + .matrixC15_25(matrixC15_25), + .matrixC15_26(matrixC15_26), + .matrixC15_27(matrixC15_27), + .matrixC15_28(matrixC15_28), + .matrixC15_29(matrixC15_29), + .matrixC15_30(matrixC15_30), + .matrixC15_31(matrixC15_31), + .matrixC16_0(matrixC16_0), + .matrixC16_1(matrixC16_1), + .matrixC16_2(matrixC16_2), + .matrixC16_3(matrixC16_3), + .matrixC16_4(matrixC16_4), + .matrixC16_5(matrixC16_5), + .matrixC16_6(matrixC16_6), + .matrixC16_7(matrixC16_7), + .matrixC16_8(matrixC16_8), + .matrixC16_9(matrixC16_9), + .matrixC16_10(matrixC16_10), + .matrixC16_11(matrixC16_11), + .matrixC16_12(matrixC16_12), + .matrixC16_13(matrixC16_13), + .matrixC16_14(matrixC16_14), + .matrixC16_15(matrixC16_15), + .matrixC16_16(matrixC16_16), + .matrixC16_17(matrixC16_17), + .matrixC16_18(matrixC16_18), + .matrixC16_19(matrixC16_19), + .matrixC16_20(matrixC16_20), + .matrixC16_21(matrixC16_21), + .matrixC16_22(matrixC16_22), + .matrixC16_23(matrixC16_23), + .matrixC16_24(matrixC16_24), + .matrixC16_25(matrixC16_25), + .matrixC16_26(matrixC16_26), + .matrixC16_27(matrixC16_27), + .matrixC16_28(matrixC16_28), + .matrixC16_29(matrixC16_29), + .matrixC16_30(matrixC16_30), + .matrixC16_31(matrixC16_31), + .matrixC17_0(matrixC17_0), + .matrixC17_1(matrixC17_1), + .matrixC17_2(matrixC17_2), + .matrixC17_3(matrixC17_3), + .matrixC17_4(matrixC17_4), + .matrixC17_5(matrixC17_5), + .matrixC17_6(matrixC17_6), + .matrixC17_7(matrixC17_7), + .matrixC17_8(matrixC17_8), + .matrixC17_9(matrixC17_9), + .matrixC17_10(matrixC17_10), + .matrixC17_11(matrixC17_11), + .matrixC17_12(matrixC17_12), + .matrixC17_13(matrixC17_13), + .matrixC17_14(matrixC17_14), + .matrixC17_15(matrixC17_15), + .matrixC17_16(matrixC17_16), + .matrixC17_17(matrixC17_17), + .matrixC17_18(matrixC17_18), + .matrixC17_19(matrixC17_19), + .matrixC17_20(matrixC17_20), + .matrixC17_21(matrixC17_21), + .matrixC17_22(matrixC17_22), + .matrixC17_23(matrixC17_23), + .matrixC17_24(matrixC17_24), + .matrixC17_25(matrixC17_25), + .matrixC17_26(matrixC17_26), + .matrixC17_27(matrixC17_27), + .matrixC17_28(matrixC17_28), + .matrixC17_29(matrixC17_29), + .matrixC17_30(matrixC17_30), + .matrixC17_31(matrixC17_31), + .matrixC18_0(matrixC18_0), + .matrixC18_1(matrixC18_1), + .matrixC18_2(matrixC18_2), + .matrixC18_3(matrixC18_3), + .matrixC18_4(matrixC18_4), + .matrixC18_5(matrixC18_5), + .matrixC18_6(matrixC18_6), + .matrixC18_7(matrixC18_7), + .matrixC18_8(matrixC18_8), + .matrixC18_9(matrixC18_9), + .matrixC18_10(matrixC18_10), + .matrixC18_11(matrixC18_11), + .matrixC18_12(matrixC18_12), + .matrixC18_13(matrixC18_13), + .matrixC18_14(matrixC18_14), + .matrixC18_15(matrixC18_15), + .matrixC18_16(matrixC18_16), + .matrixC18_17(matrixC18_17), + .matrixC18_18(matrixC18_18), + .matrixC18_19(matrixC18_19), + .matrixC18_20(matrixC18_20), + .matrixC18_21(matrixC18_21), + .matrixC18_22(matrixC18_22), + .matrixC18_23(matrixC18_23), + .matrixC18_24(matrixC18_24), + .matrixC18_25(matrixC18_25), + .matrixC18_26(matrixC18_26), + .matrixC18_27(matrixC18_27), + .matrixC18_28(matrixC18_28), + .matrixC18_29(matrixC18_29), + .matrixC18_30(matrixC18_30), + .matrixC18_31(matrixC18_31), + .matrixC19_0(matrixC19_0), + .matrixC19_1(matrixC19_1), + .matrixC19_2(matrixC19_2), + .matrixC19_3(matrixC19_3), + .matrixC19_4(matrixC19_4), + .matrixC19_5(matrixC19_5), + .matrixC19_6(matrixC19_6), + .matrixC19_7(matrixC19_7), + .matrixC19_8(matrixC19_8), + .matrixC19_9(matrixC19_9), + .matrixC19_10(matrixC19_10), + .matrixC19_11(matrixC19_11), + .matrixC19_12(matrixC19_12), + .matrixC19_13(matrixC19_13), + .matrixC19_14(matrixC19_14), + .matrixC19_15(matrixC19_15), + .matrixC19_16(matrixC19_16), + .matrixC19_17(matrixC19_17), + .matrixC19_18(matrixC19_18), + .matrixC19_19(matrixC19_19), + .matrixC19_20(matrixC19_20), + .matrixC19_21(matrixC19_21), + .matrixC19_22(matrixC19_22), + .matrixC19_23(matrixC19_23), + .matrixC19_24(matrixC19_24), + .matrixC19_25(matrixC19_25), + .matrixC19_26(matrixC19_26), + .matrixC19_27(matrixC19_27), + .matrixC19_28(matrixC19_28), + .matrixC19_29(matrixC19_29), + .matrixC19_30(matrixC19_30), + .matrixC19_31(matrixC19_31), + .matrixC20_0(matrixC20_0), + .matrixC20_1(matrixC20_1), + .matrixC20_2(matrixC20_2), + .matrixC20_3(matrixC20_3), + .matrixC20_4(matrixC20_4), + .matrixC20_5(matrixC20_5), + .matrixC20_6(matrixC20_6), + .matrixC20_7(matrixC20_7), + .matrixC20_8(matrixC20_8), + .matrixC20_9(matrixC20_9), + .matrixC20_10(matrixC20_10), + .matrixC20_11(matrixC20_11), + .matrixC20_12(matrixC20_12), + .matrixC20_13(matrixC20_13), + .matrixC20_14(matrixC20_14), + .matrixC20_15(matrixC20_15), + .matrixC20_16(matrixC20_16), + .matrixC20_17(matrixC20_17), + .matrixC20_18(matrixC20_18), + .matrixC20_19(matrixC20_19), + .matrixC20_20(matrixC20_20), + .matrixC20_21(matrixC20_21), + .matrixC20_22(matrixC20_22), + .matrixC20_23(matrixC20_23), + .matrixC20_24(matrixC20_24), + .matrixC20_25(matrixC20_25), + .matrixC20_26(matrixC20_26), + .matrixC20_27(matrixC20_27), + .matrixC20_28(matrixC20_28), + .matrixC20_29(matrixC20_29), + .matrixC20_30(matrixC20_30), + .matrixC20_31(matrixC20_31), + .matrixC21_0(matrixC21_0), + .matrixC21_1(matrixC21_1), + .matrixC21_2(matrixC21_2), + .matrixC21_3(matrixC21_3), + .matrixC21_4(matrixC21_4), + .matrixC21_5(matrixC21_5), + .matrixC21_6(matrixC21_6), + .matrixC21_7(matrixC21_7), + .matrixC21_8(matrixC21_8), + .matrixC21_9(matrixC21_9), + .matrixC21_10(matrixC21_10), + .matrixC21_11(matrixC21_11), + .matrixC21_12(matrixC21_12), + .matrixC21_13(matrixC21_13), + .matrixC21_14(matrixC21_14), + .matrixC21_15(matrixC21_15), + .matrixC21_16(matrixC21_16), + .matrixC21_17(matrixC21_17), + .matrixC21_18(matrixC21_18), + .matrixC21_19(matrixC21_19), + .matrixC21_20(matrixC21_20), + .matrixC21_21(matrixC21_21), + .matrixC21_22(matrixC21_22), + .matrixC21_23(matrixC21_23), + .matrixC21_24(matrixC21_24), + .matrixC21_25(matrixC21_25), + .matrixC21_26(matrixC21_26), + .matrixC21_27(matrixC21_27), + .matrixC21_28(matrixC21_28), + .matrixC21_29(matrixC21_29), + .matrixC21_30(matrixC21_30), + .matrixC21_31(matrixC21_31), + .matrixC22_0(matrixC22_0), + .matrixC22_1(matrixC22_1), + .matrixC22_2(matrixC22_2), + .matrixC22_3(matrixC22_3), + .matrixC22_4(matrixC22_4), + .matrixC22_5(matrixC22_5), + .matrixC22_6(matrixC22_6), + .matrixC22_7(matrixC22_7), + .matrixC22_8(matrixC22_8), + .matrixC22_9(matrixC22_9), + .matrixC22_10(matrixC22_10), + .matrixC22_11(matrixC22_11), + .matrixC22_12(matrixC22_12), + .matrixC22_13(matrixC22_13), + .matrixC22_14(matrixC22_14), + .matrixC22_15(matrixC22_15), + .matrixC22_16(matrixC22_16), + .matrixC22_17(matrixC22_17), + .matrixC22_18(matrixC22_18), + .matrixC22_19(matrixC22_19), + .matrixC22_20(matrixC22_20), + .matrixC22_21(matrixC22_21), + .matrixC22_22(matrixC22_22), + .matrixC22_23(matrixC22_23), + .matrixC22_24(matrixC22_24), + .matrixC22_25(matrixC22_25), + .matrixC22_26(matrixC22_26), + .matrixC22_27(matrixC22_27), + .matrixC22_28(matrixC22_28), + .matrixC22_29(matrixC22_29), + .matrixC22_30(matrixC22_30), + .matrixC22_31(matrixC22_31), + .matrixC23_0(matrixC23_0), + .matrixC23_1(matrixC23_1), + .matrixC23_2(matrixC23_2), + .matrixC23_3(matrixC23_3), + .matrixC23_4(matrixC23_4), + .matrixC23_5(matrixC23_5), + .matrixC23_6(matrixC23_6), + .matrixC23_7(matrixC23_7), + .matrixC23_8(matrixC23_8), + .matrixC23_9(matrixC23_9), + .matrixC23_10(matrixC23_10), + .matrixC23_11(matrixC23_11), + .matrixC23_12(matrixC23_12), + .matrixC23_13(matrixC23_13), + .matrixC23_14(matrixC23_14), + .matrixC23_15(matrixC23_15), + .matrixC23_16(matrixC23_16), + .matrixC23_17(matrixC23_17), + .matrixC23_18(matrixC23_18), + .matrixC23_19(matrixC23_19), + .matrixC23_20(matrixC23_20), + .matrixC23_21(matrixC23_21), + .matrixC23_22(matrixC23_22), + .matrixC23_23(matrixC23_23), + .matrixC23_24(matrixC23_24), + .matrixC23_25(matrixC23_25), + .matrixC23_26(matrixC23_26), + .matrixC23_27(matrixC23_27), + .matrixC23_28(matrixC23_28), + .matrixC23_29(matrixC23_29), + .matrixC23_30(matrixC23_30), + .matrixC23_31(matrixC23_31), + .matrixC24_0(matrixC24_0), + .matrixC24_1(matrixC24_1), + .matrixC24_2(matrixC24_2), + .matrixC24_3(matrixC24_3), + .matrixC24_4(matrixC24_4), + .matrixC24_5(matrixC24_5), + .matrixC24_6(matrixC24_6), + .matrixC24_7(matrixC24_7), + .matrixC24_8(matrixC24_8), + .matrixC24_9(matrixC24_9), + .matrixC24_10(matrixC24_10), + .matrixC24_11(matrixC24_11), + .matrixC24_12(matrixC24_12), + .matrixC24_13(matrixC24_13), + .matrixC24_14(matrixC24_14), + .matrixC24_15(matrixC24_15), + .matrixC24_16(matrixC24_16), + .matrixC24_17(matrixC24_17), + .matrixC24_18(matrixC24_18), + .matrixC24_19(matrixC24_19), + .matrixC24_20(matrixC24_20), + .matrixC24_21(matrixC24_21), + .matrixC24_22(matrixC24_22), + .matrixC24_23(matrixC24_23), + .matrixC24_24(matrixC24_24), + .matrixC24_25(matrixC24_25), + .matrixC24_26(matrixC24_26), + .matrixC24_27(matrixC24_27), + .matrixC24_28(matrixC24_28), + .matrixC24_29(matrixC24_29), + .matrixC24_30(matrixC24_30), + .matrixC24_31(matrixC24_31), + .matrixC25_0(matrixC25_0), + .matrixC25_1(matrixC25_1), + .matrixC25_2(matrixC25_2), + .matrixC25_3(matrixC25_3), + .matrixC25_4(matrixC25_4), + .matrixC25_5(matrixC25_5), + .matrixC25_6(matrixC25_6), + .matrixC25_7(matrixC25_7), + .matrixC25_8(matrixC25_8), + .matrixC25_9(matrixC25_9), + .matrixC25_10(matrixC25_10), + .matrixC25_11(matrixC25_11), + .matrixC25_12(matrixC25_12), + .matrixC25_13(matrixC25_13), + .matrixC25_14(matrixC25_14), + .matrixC25_15(matrixC25_15), + .matrixC25_16(matrixC25_16), + .matrixC25_17(matrixC25_17), + .matrixC25_18(matrixC25_18), + .matrixC25_19(matrixC25_19), + .matrixC25_20(matrixC25_20), + .matrixC25_21(matrixC25_21), + .matrixC25_22(matrixC25_22), + .matrixC25_23(matrixC25_23), + .matrixC25_24(matrixC25_24), + .matrixC25_25(matrixC25_25), + .matrixC25_26(matrixC25_26), + .matrixC25_27(matrixC25_27), + .matrixC25_28(matrixC25_28), + .matrixC25_29(matrixC25_29), + .matrixC25_30(matrixC25_30), + .matrixC25_31(matrixC25_31), + .matrixC26_0(matrixC26_0), + .matrixC26_1(matrixC26_1), + .matrixC26_2(matrixC26_2), + .matrixC26_3(matrixC26_3), + .matrixC26_4(matrixC26_4), + .matrixC26_5(matrixC26_5), + .matrixC26_6(matrixC26_6), + .matrixC26_7(matrixC26_7), + .matrixC26_8(matrixC26_8), + .matrixC26_9(matrixC26_9), + .matrixC26_10(matrixC26_10), + .matrixC26_11(matrixC26_11), + .matrixC26_12(matrixC26_12), + .matrixC26_13(matrixC26_13), + .matrixC26_14(matrixC26_14), + .matrixC26_15(matrixC26_15), + .matrixC26_16(matrixC26_16), + .matrixC26_17(matrixC26_17), + .matrixC26_18(matrixC26_18), + .matrixC26_19(matrixC26_19), + .matrixC26_20(matrixC26_20), + .matrixC26_21(matrixC26_21), + .matrixC26_22(matrixC26_22), + .matrixC26_23(matrixC26_23), + .matrixC26_24(matrixC26_24), + .matrixC26_25(matrixC26_25), + .matrixC26_26(matrixC26_26), + .matrixC26_27(matrixC26_27), + .matrixC26_28(matrixC26_28), + .matrixC26_29(matrixC26_29), + .matrixC26_30(matrixC26_30), + .matrixC26_31(matrixC26_31), + .matrixC27_0(matrixC27_0), + .matrixC27_1(matrixC27_1), + .matrixC27_2(matrixC27_2), + .matrixC27_3(matrixC27_3), + .matrixC27_4(matrixC27_4), + .matrixC27_5(matrixC27_5), + .matrixC27_6(matrixC27_6), + .matrixC27_7(matrixC27_7), + .matrixC27_8(matrixC27_8), + .matrixC27_9(matrixC27_9), + .matrixC27_10(matrixC27_10), + .matrixC27_11(matrixC27_11), + .matrixC27_12(matrixC27_12), + .matrixC27_13(matrixC27_13), + .matrixC27_14(matrixC27_14), + .matrixC27_15(matrixC27_15), + .matrixC27_16(matrixC27_16), + .matrixC27_17(matrixC27_17), + .matrixC27_18(matrixC27_18), + .matrixC27_19(matrixC27_19), + .matrixC27_20(matrixC27_20), + .matrixC27_21(matrixC27_21), + .matrixC27_22(matrixC27_22), + .matrixC27_23(matrixC27_23), + .matrixC27_24(matrixC27_24), + .matrixC27_25(matrixC27_25), + .matrixC27_26(matrixC27_26), + .matrixC27_27(matrixC27_27), + .matrixC27_28(matrixC27_28), + .matrixC27_29(matrixC27_29), + .matrixC27_30(matrixC27_30), + .matrixC27_31(matrixC27_31), + .matrixC28_0(matrixC28_0), + .matrixC28_1(matrixC28_1), + .matrixC28_2(matrixC28_2), + .matrixC28_3(matrixC28_3), + .matrixC28_4(matrixC28_4), + .matrixC28_5(matrixC28_5), + .matrixC28_6(matrixC28_6), + .matrixC28_7(matrixC28_7), + .matrixC28_8(matrixC28_8), + .matrixC28_9(matrixC28_9), + .matrixC28_10(matrixC28_10), + .matrixC28_11(matrixC28_11), + .matrixC28_12(matrixC28_12), + .matrixC28_13(matrixC28_13), + .matrixC28_14(matrixC28_14), + .matrixC28_15(matrixC28_15), + .matrixC28_16(matrixC28_16), + .matrixC28_17(matrixC28_17), + .matrixC28_18(matrixC28_18), + .matrixC28_19(matrixC28_19), + .matrixC28_20(matrixC28_20), + .matrixC28_21(matrixC28_21), + .matrixC28_22(matrixC28_22), + .matrixC28_23(matrixC28_23), + .matrixC28_24(matrixC28_24), + .matrixC28_25(matrixC28_25), + .matrixC28_26(matrixC28_26), + .matrixC28_27(matrixC28_27), + .matrixC28_28(matrixC28_28), + .matrixC28_29(matrixC28_29), + .matrixC28_30(matrixC28_30), + .matrixC28_31(matrixC28_31), + .matrixC29_0(matrixC29_0), + .matrixC29_1(matrixC29_1), + .matrixC29_2(matrixC29_2), + .matrixC29_3(matrixC29_3), + .matrixC29_4(matrixC29_4), + .matrixC29_5(matrixC29_5), + .matrixC29_6(matrixC29_6), + .matrixC29_7(matrixC29_7), + .matrixC29_8(matrixC29_8), + .matrixC29_9(matrixC29_9), + .matrixC29_10(matrixC29_10), + .matrixC29_11(matrixC29_11), + .matrixC29_12(matrixC29_12), + .matrixC29_13(matrixC29_13), + .matrixC29_14(matrixC29_14), + .matrixC29_15(matrixC29_15), + .matrixC29_16(matrixC29_16), + .matrixC29_17(matrixC29_17), + .matrixC29_18(matrixC29_18), + .matrixC29_19(matrixC29_19), + .matrixC29_20(matrixC29_20), + .matrixC29_21(matrixC29_21), + .matrixC29_22(matrixC29_22), + .matrixC29_23(matrixC29_23), + .matrixC29_24(matrixC29_24), + .matrixC29_25(matrixC29_25), + .matrixC29_26(matrixC29_26), + .matrixC29_27(matrixC29_27), + .matrixC29_28(matrixC29_28), + .matrixC29_29(matrixC29_29), + .matrixC29_30(matrixC29_30), + .matrixC29_31(matrixC29_31), + .matrixC30_0(matrixC30_0), + .matrixC30_1(matrixC30_1), + .matrixC30_2(matrixC30_2), + .matrixC30_3(matrixC30_3), + .matrixC30_4(matrixC30_4), + .matrixC30_5(matrixC30_5), + .matrixC30_6(matrixC30_6), + .matrixC30_7(matrixC30_7), + .matrixC30_8(matrixC30_8), + .matrixC30_9(matrixC30_9), + .matrixC30_10(matrixC30_10), + .matrixC30_11(matrixC30_11), + .matrixC30_12(matrixC30_12), + .matrixC30_13(matrixC30_13), + .matrixC30_14(matrixC30_14), + .matrixC30_15(matrixC30_15), + .matrixC30_16(matrixC30_16), + .matrixC30_17(matrixC30_17), + .matrixC30_18(matrixC30_18), + .matrixC30_19(matrixC30_19), + .matrixC30_20(matrixC30_20), + .matrixC30_21(matrixC30_21), + .matrixC30_22(matrixC30_22), + .matrixC30_23(matrixC30_23), + .matrixC30_24(matrixC30_24), + .matrixC30_25(matrixC30_25), + .matrixC30_26(matrixC30_26), + .matrixC30_27(matrixC30_27), + .matrixC30_28(matrixC30_28), + .matrixC30_29(matrixC30_29), + .matrixC30_30(matrixC30_30), + .matrixC30_31(matrixC30_31), + .matrixC31_0(matrixC31_0), + .matrixC31_1(matrixC31_1), + .matrixC31_2(matrixC31_2), + .matrixC31_3(matrixC31_3), + .matrixC31_4(matrixC31_4), + .matrixC31_5(matrixC31_5), + .matrixC31_6(matrixC31_6), + .matrixC31_7(matrixC31_7), + .matrixC31_8(matrixC31_8), + .matrixC31_9(matrixC31_9), + .matrixC31_10(matrixC31_10), + .matrixC31_11(matrixC31_11), + .matrixC31_12(matrixC31_12), + .matrixC31_13(matrixC31_13), + .matrixC31_14(matrixC31_14), + .matrixC31_15(matrixC31_15), + .matrixC31_16(matrixC31_16), + .matrixC31_17(matrixC31_17), + .matrixC31_18(matrixC31_18), + .matrixC31_19(matrixC31_19), + .matrixC31_20(matrixC31_20), + .matrixC31_21(matrixC31_21), + .matrixC31_22(matrixC31_22), + .matrixC31_23(matrixC31_23), + .matrixC31_24(matrixC31_24), + .matrixC31_25(matrixC31_25), + .matrixC31_26(matrixC31_26), + .matrixC31_27(matrixC31_27), + .matrixC31_28(matrixC31_28), + .matrixC31_29(matrixC31_29), + .matrixC31_30(matrixC31_30), + .matrixC31_31(matrixC31_31), + .a_data_out(a_data_out), + .b_data_out(b_data_out) +); + +wire c_data_available; + +assign c_data_available = (clk_cnt > (`LOG2_MAT_MUL_SIZE-1+(`MAT_MUL_SIZE << 1)) & clk_cnt <= ((`LOG2_MAT_MUL_SIZE+(`MAT_MUL_SIZE << 1)) + (num_matrices_A << `LOG2_MAT_MUL_SIZE)-1)); + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Systolic data setup +////////////////////////////////////////////////////////////////////////// +module systolic_data_setup( + clk, + reset, + start_mat_mul, + a_addr, + b_addr, + address_mat_a, + address_mat_b, + address_stride_a, + address_stride_b, + a_data, + b_data, + clk_cnt, + a0_data, + a1_data_delayed_1, + a2_data_delayed_2, + a3_data_delayed_3, + a4_data_delayed_4, + a5_data_delayed_5, + a6_data_delayed_6, + a7_data_delayed_7, + a8_data_delayed_8, + a9_data_delayed_9, + a10_data_delayed_10, + a11_data_delayed_11, + a12_data_delayed_12, + a13_data_delayed_13, + a14_data_delayed_14, + a15_data_delayed_15, + a16_data_delayed_16, + a17_data_delayed_17, + a18_data_delayed_18, + a19_data_delayed_19, + a20_data_delayed_20, + a21_data_delayed_21, + a22_data_delayed_22, + a23_data_delayed_23, + a24_data_delayed_24, + a25_data_delayed_25, + a26_data_delayed_26, + a27_data_delayed_27, + a28_data_delayed_28, + a29_data_delayed_29, + a30_data_delayed_30, + a31_data_delayed_31, + b0_data, + b1_data_delayed_1, + b2_data_delayed_2, + b3_data_delayed_3, + b4_data_delayed_4, + b5_data_delayed_5, + b6_data_delayed_6, + b7_data_delayed_7, + b8_data_delayed_8, + b9_data_delayed_9, + b10_data_delayed_10, + b11_data_delayed_11, + b12_data_delayed_12, + b13_data_delayed_13, + b14_data_delayed_14, + b15_data_delayed_15, + b16_data_delayed_16, + b17_data_delayed_17, + b18_data_delayed_18, + b19_data_delayed_19, + b20_data_delayed_20, + b21_data_delayed_21, + b22_data_delayed_22, + b23_data_delayed_23, + b24_data_delayed_24, + b25_data_delayed_25, + b26_data_delayed_26, + b27_data_delayed_27, + b28_data_delayed_28, + b29_data_delayed_29, + b30_data_delayed_30, + b31_data_delayed_31, + validity_mask_a_rows, + validity_mask_a_cols_b_rows, + validity_mask_b_cols, + num_matrices_A, + num_matrices_B, + a_loc, + b_loc +); + +input clk; +input reset; +input start_mat_mul; +output [`AWIDTH-1:0] a_addr; +output [`AWIDTH-1:0] b_addr; +input [`AWIDTH-1:0] address_mat_a; +input [`AWIDTH-1:0] address_mat_b; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; +input [63:0] clk_cnt; +output [`DWIDTH-1:0] a0_data; +output [`DWIDTH-1:0] a1_data_delayed_1; +output [`DWIDTH-1:0] a2_data_delayed_2; +output [`DWIDTH-1:0] a3_data_delayed_3; +output [`DWIDTH-1:0] a4_data_delayed_4; +output [`DWIDTH-1:0] a5_data_delayed_5; +output [`DWIDTH-1:0] a6_data_delayed_6; +output [`DWIDTH-1:0] a7_data_delayed_7; +output [`DWIDTH-1:0] a8_data_delayed_8; +output [`DWIDTH-1:0] a9_data_delayed_9; +output [`DWIDTH-1:0] a10_data_delayed_10; +output [`DWIDTH-1:0] a11_data_delayed_11; +output [`DWIDTH-1:0] a12_data_delayed_12; +output [`DWIDTH-1:0] a13_data_delayed_13; +output [`DWIDTH-1:0] a14_data_delayed_14; +output [`DWIDTH-1:0] a15_data_delayed_15; +output [`DWIDTH-1:0] a16_data_delayed_16; +output [`DWIDTH-1:0] a17_data_delayed_17; +output [`DWIDTH-1:0] a18_data_delayed_18; +output [`DWIDTH-1:0] a19_data_delayed_19; +output [`DWIDTH-1:0] a20_data_delayed_20; +output [`DWIDTH-1:0] a21_data_delayed_21; +output [`DWIDTH-1:0] a22_data_delayed_22; +output [`DWIDTH-1:0] a23_data_delayed_23; +output [`DWIDTH-1:0] a24_data_delayed_24; +output [`DWIDTH-1:0] a25_data_delayed_25; +output [`DWIDTH-1:0] a26_data_delayed_26; +output [`DWIDTH-1:0] a27_data_delayed_27; +output [`DWIDTH-1:0] a28_data_delayed_28; +output [`DWIDTH-1:0] a29_data_delayed_29; +output [`DWIDTH-1:0] a30_data_delayed_30; +output [`DWIDTH-1:0] a31_data_delayed_31; +output [`DWIDTH-1:0] b0_data; +output [`DWIDTH-1:0] b1_data_delayed_1; +output [`DWIDTH-1:0] b2_data_delayed_2; +output [`DWIDTH-1:0] b3_data_delayed_3; +output [`DWIDTH-1:0] b4_data_delayed_4; +output [`DWIDTH-1:0] b5_data_delayed_5; +output [`DWIDTH-1:0] b6_data_delayed_6; +output [`DWIDTH-1:0] b7_data_delayed_7; +output [`DWIDTH-1:0] b8_data_delayed_8; +output [`DWIDTH-1:0] b9_data_delayed_9; +output [`DWIDTH-1:0] b10_data_delayed_10; +output [`DWIDTH-1:0] b11_data_delayed_11; +output [`DWIDTH-1:0] b12_data_delayed_12; +output [`DWIDTH-1:0] b13_data_delayed_13; +output [`DWIDTH-1:0] b14_data_delayed_14; +output [`DWIDTH-1:0] b15_data_delayed_15; +output [`DWIDTH-1:0] b16_data_delayed_16; +output [`DWIDTH-1:0] b17_data_delayed_17; +output [`DWIDTH-1:0] b18_data_delayed_18; +output [`DWIDTH-1:0] b19_data_delayed_19; +output [`DWIDTH-1:0] b20_data_delayed_20; +output [`DWIDTH-1:0] b21_data_delayed_21; +output [`DWIDTH-1:0] b22_data_delayed_22; +output [`DWIDTH-1:0] b23_data_delayed_23; +output [`DWIDTH-1:0] b24_data_delayed_24; +output [`DWIDTH-1:0] b25_data_delayed_25; +output [`DWIDTH-1:0] b26_data_delayed_26; +output [`DWIDTH-1:0] b27_data_delayed_27; +output [`DWIDTH-1:0] b28_data_delayed_28; +output [`DWIDTH-1:0] b29_data_delayed_29; +output [`DWIDTH-1:0] b30_data_delayed_30; +output [`DWIDTH-1:0] b31_data_delayed_31; +input [`MASK_WIDTH-1:0] validity_mask_a_rows; +input [`MASK_WIDTH-1:0] validity_mask_a_cols_b_rows; +input [`MASK_WIDTH-1:0] validity_mask_b_cols; +input [31:0] num_matrices_A; +input [31:0] num_matrices_B; +input [63:0] a_loc; +input [63:0] b_loc; + +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] a16_data; +wire [`DWIDTH-1:0] a17_data; +wire [`DWIDTH-1:0] a18_data; +wire [`DWIDTH-1:0] a19_data; +wire [`DWIDTH-1:0] a20_data; +wire [`DWIDTH-1:0] a21_data; +wire [`DWIDTH-1:0] a22_data; +wire [`DWIDTH-1:0] a23_data; +wire [`DWIDTH-1:0] a24_data; +wire [`DWIDTH-1:0] a25_data; +wire [`DWIDTH-1:0] a26_data; +wire [`DWIDTH-1:0] a27_data; +wire [`DWIDTH-1:0] a28_data; +wire [`DWIDTH-1:0] a29_data; +wire [`DWIDTH-1:0] a30_data; +wire [`DWIDTH-1:0] a31_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; +wire [`DWIDTH-1:0] b16_data; +wire [`DWIDTH-1:0] b17_data; +wire [`DWIDTH-1:0] b18_data; +wire [`DWIDTH-1:0] b19_data; +wire [`DWIDTH-1:0] b20_data; +wire [`DWIDTH-1:0] b21_data; +wire [`DWIDTH-1:0] b22_data; +wire [`DWIDTH-1:0] b23_data; +wire [`DWIDTH-1:0] b24_data; +wire [`DWIDTH-1:0] b25_data; +wire [`DWIDTH-1:0] b26_data; +wire [`DWIDTH-1:0] b27_data; +wire [`DWIDTH-1:0] b28_data; +wire [`DWIDTH-1:0] b29_data; +wire [`DWIDTH-1:0] b30_data; +wire [`DWIDTH-1:0] b31_data; + +wire a_data_valid; // flag that tells whether the data from memory is valid +wire b_data_valid; // flag that tells whether the data from memory is valid + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM A +////////////////////////////////////////////////////////////////////////// + +reg [`AWIDTH-1:0] a_addr; +reg a_mem_access; // flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin +if ((reset || ~start_mat_mul) || (clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)+`MAT_MUL_SIZE+(num_matrices_A << `LOG2_MAT_MUL_SIZE))) begin + a_addr <= address_mat_a-address_stride_a; + a_mem_access <= 0; +end +else if ((clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)+`MAT_MUL_SIZE) && (clk_cnt < (a_loc<<`LOG2_MAT_MUL_SIZE)+`MAT_MUL_SIZE+(num_matrices_A << `LOG2_MAT_MUL_SIZE))) begin + a_addr <= a_addr + address_stride_a; + a_mem_access <= 1; +end +end + + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM A +////////////////////////////////////////////////////////////////////////// + +reg [63:0] a_mem_access_counter; + +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + a_mem_access_counter <= 0; + end + else if (a_mem_access == 1) begin + a_mem_access_counter <= a_mem_access_counter + 1; + end + else begin + a_mem_access_counter <= 0; + end +end + +assign a_data_valid = + ((validity_mask_a_cols_b_rows[0]==1'b0 && a_mem_access_counter==1) || + (validity_mask_a_cols_b_rows[1]==1'b0 && a_mem_access_counter==2) || + (validity_mask_a_cols_b_rows[2]==1'b0 && a_mem_access_counter==3) || + (validity_mask_a_cols_b_rows[3]==1'b0 && a_mem_access_counter==4) || + (validity_mask_a_cols_b_rows[4]==1'b0 && a_mem_access_counter==5) || + (validity_mask_a_cols_b_rows[5]==1'b0 && a_mem_access_counter==6) || + (validity_mask_a_cols_b_rows[6]==1'b0 && a_mem_access_counter==7) || + (validity_mask_a_cols_b_rows[7]==1'b0 && a_mem_access_counter==8) || + (validity_mask_a_cols_b_rows[8]==1'b0 && a_mem_access_counter==9) || + (validity_mask_a_cols_b_rows[9]==1'b0 && a_mem_access_counter==10) || + (validity_mask_a_cols_b_rows[10]==1'b0 && a_mem_access_counter==11) || + (validity_mask_a_cols_b_rows[11]==1'b0 && a_mem_access_counter==12) || + (validity_mask_a_cols_b_rows[12]==1'b0 && a_mem_access_counter==13) || + (validity_mask_a_cols_b_rows[13]==1'b0 && a_mem_access_counter==14) || + (validity_mask_a_cols_b_rows[14]==1'b0 && a_mem_access_counter==15) || + (validity_mask_a_cols_b_rows[15]==1'b0 && a_mem_access_counter==16) || + (validity_mask_a_cols_b_rows[16]==1'b0 && a_mem_access_counter==17) || + (validity_mask_a_cols_b_rows[17]==1'b0 && a_mem_access_counter==18) || + (validity_mask_a_cols_b_rows[18]==1'b0 && a_mem_access_counter==19) || + (validity_mask_a_cols_b_rows[19]==1'b0 && a_mem_access_counter==20) || + (validity_mask_a_cols_b_rows[20]==1'b0 && a_mem_access_counter==21) || + (validity_mask_a_cols_b_rows[21]==1'b0 && a_mem_access_counter==22) || + (validity_mask_a_cols_b_rows[22]==1'b0 && a_mem_access_counter==23) || + (validity_mask_a_cols_b_rows[23]==1'b0 && a_mem_access_counter==24) || + (validity_mask_a_cols_b_rows[24]==1'b0 && a_mem_access_counter==25) || + (validity_mask_a_cols_b_rows[25]==1'b0 && a_mem_access_counter==26) || + (validity_mask_a_cols_b_rows[26]==1'b0 && a_mem_access_counter==27) || + (validity_mask_a_cols_b_rows[27]==1'b0 && a_mem_access_counter==28) || + (validity_mask_a_cols_b_rows[28]==1'b0 && a_mem_access_counter==29) || + (validity_mask_a_cols_b_rows[29]==1'b0 && a_mem_access_counter==30) || + (validity_mask_a_cols_b_rows[30]==1'b0 && a_mem_access_counter==31) || + (validity_mask_a_cols_b_rows[31]==1'b0 && a_mem_access_counter==32)) ? + 1'b0 : (a_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM A (systolic data setup) +////////////////////////////////////////////////////////////////////////// + +// Slice data into chunks and qualify it with whether it is valid or not +assign a0_data = a_data[`DWIDTH-1:0] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[0]}}; +assign a1_data = a_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[1]}}; +assign a2_data = a_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[2]}}; +assign a3_data = a_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[3]}}; +assign a4_data = a_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[4]}}; +assign a5_data = a_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[5]}}; +assign a6_data = a_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[6]}}; +assign a7_data = a_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[7]}}; +assign a8_data = a_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[8]}}; +assign a9_data = a_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[9]}}; +assign a10_data = a_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[10]}}; +assign a11_data = a_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[11]}}; +assign a12_data = a_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[12]}}; +assign a13_data = a_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[13]}}; +assign a14_data = a_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[14]}}; +assign a15_data = a_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[15]}}; +assign a16_data = a_data[17*`DWIDTH-1:16*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[16]}}; +assign a17_data = a_data[18*`DWIDTH-1:17*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[17]}}; +assign a18_data = a_data[19*`DWIDTH-1:18*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[18]}}; +assign a19_data = a_data[20*`DWIDTH-1:19*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[19]}}; +assign a20_data = a_data[21*`DWIDTH-1:20*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[20]}}; +assign a21_data = a_data[22*`DWIDTH-1:21*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[21]}}; +assign a22_data = a_data[23*`DWIDTH-1:22*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[22]}}; +assign a23_data = a_data[24*`DWIDTH-1:23*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[23]}}; +assign a24_data = a_data[25*`DWIDTH-1:24*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[24]}}; +assign a25_data = a_data[26*`DWIDTH-1:25*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[25]}}; +assign a26_data = a_data[27*`DWIDTH-1:26*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[26]}}; +assign a27_data = a_data[28*`DWIDTH-1:27*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[27]}}; +assign a28_data = a_data[29*`DWIDTH-1:28*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[28]}}; +assign a29_data = a_data[30*`DWIDTH-1:29*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[29]}}; +assign a30_data = a_data[31*`DWIDTH-1:30*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[30]}}; +assign a31_data = a_data[32*`DWIDTH-1:31*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[31]}}; + +// For larger matmuls, more such delaying flops will be needed +reg [`DWIDTH-1:0] a1_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_1; +reg [`DWIDTH-1:0] a3_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_1; +reg [`DWIDTH-1:0] a4_data_delayed_2; +reg [`DWIDTH-1:0] a4_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_1; +reg [`DWIDTH-1:0] a5_data_delayed_2; +reg [`DWIDTH-1:0] a5_data_delayed_3; +reg [`DWIDTH-1:0] a5_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_1; +reg [`DWIDTH-1:0] a6_data_delayed_2; +reg [`DWIDTH-1:0] a6_data_delayed_3; +reg [`DWIDTH-1:0] a6_data_delayed_4; +reg [`DWIDTH-1:0] a6_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_1; +reg [`DWIDTH-1:0] a7_data_delayed_2; +reg [`DWIDTH-1:0] a7_data_delayed_3; +reg [`DWIDTH-1:0] a7_data_delayed_4; +reg [`DWIDTH-1:0] a7_data_delayed_5; +reg [`DWIDTH-1:0] a7_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_1; +reg [`DWIDTH-1:0] a8_data_delayed_2; +reg [`DWIDTH-1:0] a8_data_delayed_3; +reg [`DWIDTH-1:0] a8_data_delayed_4; +reg [`DWIDTH-1:0] a8_data_delayed_5; +reg [`DWIDTH-1:0] a8_data_delayed_6; +reg [`DWIDTH-1:0] a8_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_1; +reg [`DWIDTH-1:0] a9_data_delayed_2; +reg [`DWIDTH-1:0] a9_data_delayed_3; +reg [`DWIDTH-1:0] a9_data_delayed_4; +reg [`DWIDTH-1:0] a9_data_delayed_5; +reg [`DWIDTH-1:0] a9_data_delayed_6; +reg [`DWIDTH-1:0] a9_data_delayed_7; +reg [`DWIDTH-1:0] a9_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_1; +reg [`DWIDTH-1:0] a10_data_delayed_2; +reg [`DWIDTH-1:0] a10_data_delayed_3; +reg [`DWIDTH-1:0] a10_data_delayed_4; +reg [`DWIDTH-1:0] a10_data_delayed_5; +reg [`DWIDTH-1:0] a10_data_delayed_6; +reg [`DWIDTH-1:0] a10_data_delayed_7; +reg [`DWIDTH-1:0] a10_data_delayed_8; +reg [`DWIDTH-1:0] a10_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_1; +reg [`DWIDTH-1:0] a11_data_delayed_2; +reg [`DWIDTH-1:0] a11_data_delayed_3; +reg [`DWIDTH-1:0] a11_data_delayed_4; +reg [`DWIDTH-1:0] a11_data_delayed_5; +reg [`DWIDTH-1:0] a11_data_delayed_6; +reg [`DWIDTH-1:0] a11_data_delayed_7; +reg [`DWIDTH-1:0] a11_data_delayed_8; +reg [`DWIDTH-1:0] a11_data_delayed_9; +reg [`DWIDTH-1:0] a11_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_1; +reg [`DWIDTH-1:0] a12_data_delayed_2; +reg [`DWIDTH-1:0] a12_data_delayed_3; +reg [`DWIDTH-1:0] a12_data_delayed_4; +reg [`DWIDTH-1:0] a12_data_delayed_5; +reg [`DWIDTH-1:0] a12_data_delayed_6; +reg [`DWIDTH-1:0] a12_data_delayed_7; +reg [`DWIDTH-1:0] a12_data_delayed_8; +reg [`DWIDTH-1:0] a12_data_delayed_9; +reg [`DWIDTH-1:0] a12_data_delayed_10; +reg [`DWIDTH-1:0] a12_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_1; +reg [`DWIDTH-1:0] a13_data_delayed_2; +reg [`DWIDTH-1:0] a13_data_delayed_3; +reg [`DWIDTH-1:0] a13_data_delayed_4; +reg [`DWIDTH-1:0] a13_data_delayed_5; +reg [`DWIDTH-1:0] a13_data_delayed_6; +reg [`DWIDTH-1:0] a13_data_delayed_7; +reg [`DWIDTH-1:0] a13_data_delayed_8; +reg [`DWIDTH-1:0] a13_data_delayed_9; +reg [`DWIDTH-1:0] a13_data_delayed_10; +reg [`DWIDTH-1:0] a13_data_delayed_11; +reg [`DWIDTH-1:0] a13_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_1; +reg [`DWIDTH-1:0] a14_data_delayed_2; +reg [`DWIDTH-1:0] a14_data_delayed_3; +reg [`DWIDTH-1:0] a14_data_delayed_4; +reg [`DWIDTH-1:0] a14_data_delayed_5; +reg [`DWIDTH-1:0] a14_data_delayed_6; +reg [`DWIDTH-1:0] a14_data_delayed_7; +reg [`DWIDTH-1:0] a14_data_delayed_8; +reg [`DWIDTH-1:0] a14_data_delayed_9; +reg [`DWIDTH-1:0] a14_data_delayed_10; +reg [`DWIDTH-1:0] a14_data_delayed_11; +reg [`DWIDTH-1:0] a14_data_delayed_12; +reg [`DWIDTH-1:0] a14_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_1; +reg [`DWIDTH-1:0] a15_data_delayed_2; +reg [`DWIDTH-1:0] a15_data_delayed_3; +reg [`DWIDTH-1:0] a15_data_delayed_4; +reg [`DWIDTH-1:0] a15_data_delayed_5; +reg [`DWIDTH-1:0] a15_data_delayed_6; +reg [`DWIDTH-1:0] a15_data_delayed_7; +reg [`DWIDTH-1:0] a15_data_delayed_8; +reg [`DWIDTH-1:0] a15_data_delayed_9; +reg [`DWIDTH-1:0] a15_data_delayed_10; +reg [`DWIDTH-1:0] a15_data_delayed_11; +reg [`DWIDTH-1:0] a15_data_delayed_12; +reg [`DWIDTH-1:0] a15_data_delayed_13; +reg [`DWIDTH-1:0] a15_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_15; +reg [`DWIDTH-1:0] a16_data_delayed_1; +reg [`DWIDTH-1:0] a16_data_delayed_2; +reg [`DWIDTH-1:0] a16_data_delayed_3; +reg [`DWIDTH-1:0] a16_data_delayed_4; +reg [`DWIDTH-1:0] a16_data_delayed_5; +reg [`DWIDTH-1:0] a16_data_delayed_6; +reg [`DWIDTH-1:0] a16_data_delayed_7; +reg [`DWIDTH-1:0] a16_data_delayed_8; +reg [`DWIDTH-1:0] a16_data_delayed_9; +reg [`DWIDTH-1:0] a16_data_delayed_10; +reg [`DWIDTH-1:0] a16_data_delayed_11; +reg [`DWIDTH-1:0] a16_data_delayed_12; +reg [`DWIDTH-1:0] a16_data_delayed_13; +reg [`DWIDTH-1:0] a16_data_delayed_14; +reg [`DWIDTH-1:0] a16_data_delayed_15; +reg [`DWIDTH-1:0] a16_data_delayed_16; +reg [`DWIDTH-1:0] a17_data_delayed_1; +reg [`DWIDTH-1:0] a17_data_delayed_2; +reg [`DWIDTH-1:0] a17_data_delayed_3; +reg [`DWIDTH-1:0] a17_data_delayed_4; +reg [`DWIDTH-1:0] a17_data_delayed_5; +reg [`DWIDTH-1:0] a17_data_delayed_6; +reg [`DWIDTH-1:0] a17_data_delayed_7; +reg [`DWIDTH-1:0] a17_data_delayed_8; +reg [`DWIDTH-1:0] a17_data_delayed_9; +reg [`DWIDTH-1:0] a17_data_delayed_10; +reg [`DWIDTH-1:0] a17_data_delayed_11; +reg [`DWIDTH-1:0] a17_data_delayed_12; +reg [`DWIDTH-1:0] a17_data_delayed_13; +reg [`DWIDTH-1:0] a17_data_delayed_14; +reg [`DWIDTH-1:0] a17_data_delayed_15; +reg [`DWIDTH-1:0] a17_data_delayed_16; +reg [`DWIDTH-1:0] a17_data_delayed_17; +reg [`DWIDTH-1:0] a18_data_delayed_1; +reg [`DWIDTH-1:0] a18_data_delayed_2; +reg [`DWIDTH-1:0] a18_data_delayed_3; +reg [`DWIDTH-1:0] a18_data_delayed_4; +reg [`DWIDTH-1:0] a18_data_delayed_5; +reg [`DWIDTH-1:0] a18_data_delayed_6; +reg [`DWIDTH-1:0] a18_data_delayed_7; +reg [`DWIDTH-1:0] a18_data_delayed_8; +reg [`DWIDTH-1:0] a18_data_delayed_9; +reg [`DWIDTH-1:0] a18_data_delayed_10; +reg [`DWIDTH-1:0] a18_data_delayed_11; +reg [`DWIDTH-1:0] a18_data_delayed_12; +reg [`DWIDTH-1:0] a18_data_delayed_13; +reg [`DWIDTH-1:0] a18_data_delayed_14; +reg [`DWIDTH-1:0] a18_data_delayed_15; +reg [`DWIDTH-1:0] a18_data_delayed_16; +reg [`DWIDTH-1:0] a18_data_delayed_17; +reg [`DWIDTH-1:0] a18_data_delayed_18; +reg [`DWIDTH-1:0] a19_data_delayed_1; +reg [`DWIDTH-1:0] a19_data_delayed_2; +reg [`DWIDTH-1:0] a19_data_delayed_3; +reg [`DWIDTH-1:0] a19_data_delayed_4; +reg [`DWIDTH-1:0] a19_data_delayed_5; +reg [`DWIDTH-1:0] a19_data_delayed_6; +reg [`DWIDTH-1:0] a19_data_delayed_7; +reg [`DWIDTH-1:0] a19_data_delayed_8; +reg [`DWIDTH-1:0] a19_data_delayed_9; +reg [`DWIDTH-1:0] a19_data_delayed_10; +reg [`DWIDTH-1:0] a19_data_delayed_11; +reg [`DWIDTH-1:0] a19_data_delayed_12; +reg [`DWIDTH-1:0] a19_data_delayed_13; +reg [`DWIDTH-1:0] a19_data_delayed_14; +reg [`DWIDTH-1:0] a19_data_delayed_15; +reg [`DWIDTH-1:0] a19_data_delayed_16; +reg [`DWIDTH-1:0] a19_data_delayed_17; +reg [`DWIDTH-1:0] a19_data_delayed_18; +reg [`DWIDTH-1:0] a19_data_delayed_19; +reg [`DWIDTH-1:0] a20_data_delayed_1; +reg [`DWIDTH-1:0] a20_data_delayed_2; +reg [`DWIDTH-1:0] a20_data_delayed_3; +reg [`DWIDTH-1:0] a20_data_delayed_4; +reg [`DWIDTH-1:0] a20_data_delayed_5; +reg [`DWIDTH-1:0] a20_data_delayed_6; +reg [`DWIDTH-1:0] a20_data_delayed_7; +reg [`DWIDTH-1:0] a20_data_delayed_8; +reg [`DWIDTH-1:0] a20_data_delayed_9; +reg [`DWIDTH-1:0] a20_data_delayed_10; +reg [`DWIDTH-1:0] a20_data_delayed_11; +reg [`DWIDTH-1:0] a20_data_delayed_12; +reg [`DWIDTH-1:0] a20_data_delayed_13; +reg [`DWIDTH-1:0] a20_data_delayed_14; +reg [`DWIDTH-1:0] a20_data_delayed_15; +reg [`DWIDTH-1:0] a20_data_delayed_16; +reg [`DWIDTH-1:0] a20_data_delayed_17; +reg [`DWIDTH-1:0] a20_data_delayed_18; +reg [`DWIDTH-1:0] a20_data_delayed_19; +reg [`DWIDTH-1:0] a20_data_delayed_20; +reg [`DWIDTH-1:0] a21_data_delayed_1; +reg [`DWIDTH-1:0] a21_data_delayed_2; +reg [`DWIDTH-1:0] a21_data_delayed_3; +reg [`DWIDTH-1:0] a21_data_delayed_4; +reg [`DWIDTH-1:0] a21_data_delayed_5; +reg [`DWIDTH-1:0] a21_data_delayed_6; +reg [`DWIDTH-1:0] a21_data_delayed_7; +reg [`DWIDTH-1:0] a21_data_delayed_8; +reg [`DWIDTH-1:0] a21_data_delayed_9; +reg [`DWIDTH-1:0] a21_data_delayed_10; +reg [`DWIDTH-1:0] a21_data_delayed_11; +reg [`DWIDTH-1:0] a21_data_delayed_12; +reg [`DWIDTH-1:0] a21_data_delayed_13; +reg [`DWIDTH-1:0] a21_data_delayed_14; +reg [`DWIDTH-1:0] a21_data_delayed_15; +reg [`DWIDTH-1:0] a21_data_delayed_16; +reg [`DWIDTH-1:0] a21_data_delayed_17; +reg [`DWIDTH-1:0] a21_data_delayed_18; +reg [`DWIDTH-1:0] a21_data_delayed_19; +reg [`DWIDTH-1:0] a21_data_delayed_20; +reg [`DWIDTH-1:0] a21_data_delayed_21; +reg [`DWIDTH-1:0] a22_data_delayed_1; +reg [`DWIDTH-1:0] a22_data_delayed_2; +reg [`DWIDTH-1:0] a22_data_delayed_3; +reg [`DWIDTH-1:0] a22_data_delayed_4; +reg [`DWIDTH-1:0] a22_data_delayed_5; +reg [`DWIDTH-1:0] a22_data_delayed_6; +reg [`DWIDTH-1:0] a22_data_delayed_7; +reg [`DWIDTH-1:0] a22_data_delayed_8; +reg [`DWIDTH-1:0] a22_data_delayed_9; +reg [`DWIDTH-1:0] a22_data_delayed_10; +reg [`DWIDTH-1:0] a22_data_delayed_11; +reg [`DWIDTH-1:0] a22_data_delayed_12; +reg [`DWIDTH-1:0] a22_data_delayed_13; +reg [`DWIDTH-1:0] a22_data_delayed_14; +reg [`DWIDTH-1:0] a22_data_delayed_15; +reg [`DWIDTH-1:0] a22_data_delayed_16; +reg [`DWIDTH-1:0] a22_data_delayed_17; +reg [`DWIDTH-1:0] a22_data_delayed_18; +reg [`DWIDTH-1:0] a22_data_delayed_19; +reg [`DWIDTH-1:0] a22_data_delayed_20; +reg [`DWIDTH-1:0] a22_data_delayed_21; +reg [`DWIDTH-1:0] a22_data_delayed_22; +reg [`DWIDTH-1:0] a23_data_delayed_1; +reg [`DWIDTH-1:0] a23_data_delayed_2; +reg [`DWIDTH-1:0] a23_data_delayed_3; +reg [`DWIDTH-1:0] a23_data_delayed_4; +reg [`DWIDTH-1:0] a23_data_delayed_5; +reg [`DWIDTH-1:0] a23_data_delayed_6; +reg [`DWIDTH-1:0] a23_data_delayed_7; +reg [`DWIDTH-1:0] a23_data_delayed_8; +reg [`DWIDTH-1:0] a23_data_delayed_9; +reg [`DWIDTH-1:0] a23_data_delayed_10; +reg [`DWIDTH-1:0] a23_data_delayed_11; +reg [`DWIDTH-1:0] a23_data_delayed_12; +reg [`DWIDTH-1:0] a23_data_delayed_13; +reg [`DWIDTH-1:0] a23_data_delayed_14; +reg [`DWIDTH-1:0] a23_data_delayed_15; +reg [`DWIDTH-1:0] a23_data_delayed_16; +reg [`DWIDTH-1:0] a23_data_delayed_17; +reg [`DWIDTH-1:0] a23_data_delayed_18; +reg [`DWIDTH-1:0] a23_data_delayed_19; +reg [`DWIDTH-1:0] a23_data_delayed_20; +reg [`DWIDTH-1:0] a23_data_delayed_21; +reg [`DWIDTH-1:0] a23_data_delayed_22; +reg [`DWIDTH-1:0] a23_data_delayed_23; +reg [`DWIDTH-1:0] a24_data_delayed_1; +reg [`DWIDTH-1:0] a24_data_delayed_2; +reg [`DWIDTH-1:0] a24_data_delayed_3; +reg [`DWIDTH-1:0] a24_data_delayed_4; +reg [`DWIDTH-1:0] a24_data_delayed_5; +reg [`DWIDTH-1:0] a24_data_delayed_6; +reg [`DWIDTH-1:0] a24_data_delayed_7; +reg [`DWIDTH-1:0] a24_data_delayed_8; +reg [`DWIDTH-1:0] a24_data_delayed_9; +reg [`DWIDTH-1:0] a24_data_delayed_10; +reg [`DWIDTH-1:0] a24_data_delayed_11; +reg [`DWIDTH-1:0] a24_data_delayed_12; +reg [`DWIDTH-1:0] a24_data_delayed_13; +reg [`DWIDTH-1:0] a24_data_delayed_14; +reg [`DWIDTH-1:0] a24_data_delayed_15; +reg [`DWIDTH-1:0] a24_data_delayed_16; +reg [`DWIDTH-1:0] a24_data_delayed_17; +reg [`DWIDTH-1:0] a24_data_delayed_18; +reg [`DWIDTH-1:0] a24_data_delayed_19; +reg [`DWIDTH-1:0] a24_data_delayed_20; +reg [`DWIDTH-1:0] a24_data_delayed_21; +reg [`DWIDTH-1:0] a24_data_delayed_22; +reg [`DWIDTH-1:0] a24_data_delayed_23; +reg [`DWIDTH-1:0] a24_data_delayed_24; +reg [`DWIDTH-1:0] a25_data_delayed_1; +reg [`DWIDTH-1:0] a25_data_delayed_2; +reg [`DWIDTH-1:0] a25_data_delayed_3; +reg [`DWIDTH-1:0] a25_data_delayed_4; +reg [`DWIDTH-1:0] a25_data_delayed_5; +reg [`DWIDTH-1:0] a25_data_delayed_6; +reg [`DWIDTH-1:0] a25_data_delayed_7; +reg [`DWIDTH-1:0] a25_data_delayed_8; +reg [`DWIDTH-1:0] a25_data_delayed_9; +reg [`DWIDTH-1:0] a25_data_delayed_10; +reg [`DWIDTH-1:0] a25_data_delayed_11; +reg [`DWIDTH-1:0] a25_data_delayed_12; +reg [`DWIDTH-1:0] a25_data_delayed_13; +reg [`DWIDTH-1:0] a25_data_delayed_14; +reg [`DWIDTH-1:0] a25_data_delayed_15; +reg [`DWIDTH-1:0] a25_data_delayed_16; +reg [`DWIDTH-1:0] a25_data_delayed_17; +reg [`DWIDTH-1:0] a25_data_delayed_18; +reg [`DWIDTH-1:0] a25_data_delayed_19; +reg [`DWIDTH-1:0] a25_data_delayed_20; +reg [`DWIDTH-1:0] a25_data_delayed_21; +reg [`DWIDTH-1:0] a25_data_delayed_22; +reg [`DWIDTH-1:0] a25_data_delayed_23; +reg [`DWIDTH-1:0] a25_data_delayed_24; +reg [`DWIDTH-1:0] a25_data_delayed_25; +reg [`DWIDTH-1:0] a26_data_delayed_1; +reg [`DWIDTH-1:0] a26_data_delayed_2; +reg [`DWIDTH-1:0] a26_data_delayed_3; +reg [`DWIDTH-1:0] a26_data_delayed_4; +reg [`DWIDTH-1:0] a26_data_delayed_5; +reg [`DWIDTH-1:0] a26_data_delayed_6; +reg [`DWIDTH-1:0] a26_data_delayed_7; +reg [`DWIDTH-1:0] a26_data_delayed_8; +reg [`DWIDTH-1:0] a26_data_delayed_9; +reg [`DWIDTH-1:0] a26_data_delayed_10; +reg [`DWIDTH-1:0] a26_data_delayed_11; +reg [`DWIDTH-1:0] a26_data_delayed_12; +reg [`DWIDTH-1:0] a26_data_delayed_13; +reg [`DWIDTH-1:0] a26_data_delayed_14; +reg [`DWIDTH-1:0] a26_data_delayed_15; +reg [`DWIDTH-1:0] a26_data_delayed_16; +reg [`DWIDTH-1:0] a26_data_delayed_17; +reg [`DWIDTH-1:0] a26_data_delayed_18; +reg [`DWIDTH-1:0] a26_data_delayed_19; +reg [`DWIDTH-1:0] a26_data_delayed_20; +reg [`DWIDTH-1:0] a26_data_delayed_21; +reg [`DWIDTH-1:0] a26_data_delayed_22; +reg [`DWIDTH-1:0] a26_data_delayed_23; +reg [`DWIDTH-1:0] a26_data_delayed_24; +reg [`DWIDTH-1:0] a26_data_delayed_25; +reg [`DWIDTH-1:0] a26_data_delayed_26; +reg [`DWIDTH-1:0] a27_data_delayed_1; +reg [`DWIDTH-1:0] a27_data_delayed_2; +reg [`DWIDTH-1:0] a27_data_delayed_3; +reg [`DWIDTH-1:0] a27_data_delayed_4; +reg [`DWIDTH-1:0] a27_data_delayed_5; +reg [`DWIDTH-1:0] a27_data_delayed_6; +reg [`DWIDTH-1:0] a27_data_delayed_7; +reg [`DWIDTH-1:0] a27_data_delayed_8; +reg [`DWIDTH-1:0] a27_data_delayed_9; +reg [`DWIDTH-1:0] a27_data_delayed_10; +reg [`DWIDTH-1:0] a27_data_delayed_11; +reg [`DWIDTH-1:0] a27_data_delayed_12; +reg [`DWIDTH-1:0] a27_data_delayed_13; +reg [`DWIDTH-1:0] a27_data_delayed_14; +reg [`DWIDTH-1:0] a27_data_delayed_15; +reg [`DWIDTH-1:0] a27_data_delayed_16; +reg [`DWIDTH-1:0] a27_data_delayed_17; +reg [`DWIDTH-1:0] a27_data_delayed_18; +reg [`DWIDTH-1:0] a27_data_delayed_19; +reg [`DWIDTH-1:0] a27_data_delayed_20; +reg [`DWIDTH-1:0] a27_data_delayed_21; +reg [`DWIDTH-1:0] a27_data_delayed_22; +reg [`DWIDTH-1:0] a27_data_delayed_23; +reg [`DWIDTH-1:0] a27_data_delayed_24; +reg [`DWIDTH-1:0] a27_data_delayed_25; +reg [`DWIDTH-1:0] a27_data_delayed_26; +reg [`DWIDTH-1:0] a27_data_delayed_27; +reg [`DWIDTH-1:0] a28_data_delayed_1; +reg [`DWIDTH-1:0] a28_data_delayed_2; +reg [`DWIDTH-1:0] a28_data_delayed_3; +reg [`DWIDTH-1:0] a28_data_delayed_4; +reg [`DWIDTH-1:0] a28_data_delayed_5; +reg [`DWIDTH-1:0] a28_data_delayed_6; +reg [`DWIDTH-1:0] a28_data_delayed_7; +reg [`DWIDTH-1:0] a28_data_delayed_8; +reg [`DWIDTH-1:0] a28_data_delayed_9; +reg [`DWIDTH-1:0] a28_data_delayed_10; +reg [`DWIDTH-1:0] a28_data_delayed_11; +reg [`DWIDTH-1:0] a28_data_delayed_12; +reg [`DWIDTH-1:0] a28_data_delayed_13; +reg [`DWIDTH-1:0] a28_data_delayed_14; +reg [`DWIDTH-1:0] a28_data_delayed_15; +reg [`DWIDTH-1:0] a28_data_delayed_16; +reg [`DWIDTH-1:0] a28_data_delayed_17; +reg [`DWIDTH-1:0] a28_data_delayed_18; +reg [`DWIDTH-1:0] a28_data_delayed_19; +reg [`DWIDTH-1:0] a28_data_delayed_20; +reg [`DWIDTH-1:0] a28_data_delayed_21; +reg [`DWIDTH-1:0] a28_data_delayed_22; +reg [`DWIDTH-1:0] a28_data_delayed_23; +reg [`DWIDTH-1:0] a28_data_delayed_24; +reg [`DWIDTH-1:0] a28_data_delayed_25; +reg [`DWIDTH-1:0] a28_data_delayed_26; +reg [`DWIDTH-1:0] a28_data_delayed_27; +reg [`DWIDTH-1:0] a28_data_delayed_28; +reg [`DWIDTH-1:0] a29_data_delayed_1; +reg [`DWIDTH-1:0] a29_data_delayed_2; +reg [`DWIDTH-1:0] a29_data_delayed_3; +reg [`DWIDTH-1:0] a29_data_delayed_4; +reg [`DWIDTH-1:0] a29_data_delayed_5; +reg [`DWIDTH-1:0] a29_data_delayed_6; +reg [`DWIDTH-1:0] a29_data_delayed_7; +reg [`DWIDTH-1:0] a29_data_delayed_8; +reg [`DWIDTH-1:0] a29_data_delayed_9; +reg [`DWIDTH-1:0] a29_data_delayed_10; +reg [`DWIDTH-1:0] a29_data_delayed_11; +reg [`DWIDTH-1:0] a29_data_delayed_12; +reg [`DWIDTH-1:0] a29_data_delayed_13; +reg [`DWIDTH-1:0] a29_data_delayed_14; +reg [`DWIDTH-1:0] a29_data_delayed_15; +reg [`DWIDTH-1:0] a29_data_delayed_16; +reg [`DWIDTH-1:0] a29_data_delayed_17; +reg [`DWIDTH-1:0] a29_data_delayed_18; +reg [`DWIDTH-1:0] a29_data_delayed_19; +reg [`DWIDTH-1:0] a29_data_delayed_20; +reg [`DWIDTH-1:0] a29_data_delayed_21; +reg [`DWIDTH-1:0] a29_data_delayed_22; +reg [`DWIDTH-1:0] a29_data_delayed_23; +reg [`DWIDTH-1:0] a29_data_delayed_24; +reg [`DWIDTH-1:0] a29_data_delayed_25; +reg [`DWIDTH-1:0] a29_data_delayed_26; +reg [`DWIDTH-1:0] a29_data_delayed_27; +reg [`DWIDTH-1:0] a29_data_delayed_28; +reg [`DWIDTH-1:0] a29_data_delayed_29; +reg [`DWIDTH-1:0] a30_data_delayed_1; +reg [`DWIDTH-1:0] a30_data_delayed_2; +reg [`DWIDTH-1:0] a30_data_delayed_3; +reg [`DWIDTH-1:0] a30_data_delayed_4; +reg [`DWIDTH-1:0] a30_data_delayed_5; +reg [`DWIDTH-1:0] a30_data_delayed_6; +reg [`DWIDTH-1:0] a30_data_delayed_7; +reg [`DWIDTH-1:0] a30_data_delayed_8; +reg [`DWIDTH-1:0] a30_data_delayed_9; +reg [`DWIDTH-1:0] a30_data_delayed_10; +reg [`DWIDTH-1:0] a30_data_delayed_11; +reg [`DWIDTH-1:0] a30_data_delayed_12; +reg [`DWIDTH-1:0] a30_data_delayed_13; +reg [`DWIDTH-1:0] a30_data_delayed_14; +reg [`DWIDTH-1:0] a30_data_delayed_15; +reg [`DWIDTH-1:0] a30_data_delayed_16; +reg [`DWIDTH-1:0] a30_data_delayed_17; +reg [`DWIDTH-1:0] a30_data_delayed_18; +reg [`DWIDTH-1:0] a30_data_delayed_19; +reg [`DWIDTH-1:0] a30_data_delayed_20; +reg [`DWIDTH-1:0] a30_data_delayed_21; +reg [`DWIDTH-1:0] a30_data_delayed_22; +reg [`DWIDTH-1:0] a30_data_delayed_23; +reg [`DWIDTH-1:0] a30_data_delayed_24; +reg [`DWIDTH-1:0] a30_data_delayed_25; +reg [`DWIDTH-1:0] a30_data_delayed_26; +reg [`DWIDTH-1:0] a30_data_delayed_27; +reg [`DWIDTH-1:0] a30_data_delayed_28; +reg [`DWIDTH-1:0] a30_data_delayed_29; +reg [`DWIDTH-1:0] a30_data_delayed_30; +reg [`DWIDTH-1:0] a31_data_delayed_1; +reg [`DWIDTH-1:0] a31_data_delayed_2; +reg [`DWIDTH-1:0] a31_data_delayed_3; +reg [`DWIDTH-1:0] a31_data_delayed_4; +reg [`DWIDTH-1:0] a31_data_delayed_5; +reg [`DWIDTH-1:0] a31_data_delayed_6; +reg [`DWIDTH-1:0] a31_data_delayed_7; +reg [`DWIDTH-1:0] a31_data_delayed_8; +reg [`DWIDTH-1:0] a31_data_delayed_9; +reg [`DWIDTH-1:0] a31_data_delayed_10; +reg [`DWIDTH-1:0] a31_data_delayed_11; +reg [`DWIDTH-1:0] a31_data_delayed_12; +reg [`DWIDTH-1:0] a31_data_delayed_13; +reg [`DWIDTH-1:0] a31_data_delayed_14; +reg [`DWIDTH-1:0] a31_data_delayed_15; +reg [`DWIDTH-1:0] a31_data_delayed_16; +reg [`DWIDTH-1:0] a31_data_delayed_17; +reg [`DWIDTH-1:0] a31_data_delayed_18; +reg [`DWIDTH-1:0] a31_data_delayed_19; +reg [`DWIDTH-1:0] a31_data_delayed_20; +reg [`DWIDTH-1:0] a31_data_delayed_21; +reg [`DWIDTH-1:0] a31_data_delayed_22; +reg [`DWIDTH-1:0] a31_data_delayed_23; +reg [`DWIDTH-1:0] a31_data_delayed_24; +reg [`DWIDTH-1:0] a31_data_delayed_25; +reg [`DWIDTH-1:0] a31_data_delayed_26; +reg [`DWIDTH-1:0] a31_data_delayed_27; +reg [`DWIDTH-1:0] a31_data_delayed_28; +reg [`DWIDTH-1:0] a31_data_delayed_29; +reg [`DWIDTH-1:0] a31_data_delayed_30; +reg [`DWIDTH-1:0] a31_data_delayed_31; + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + a1_data_delayed_1 <= 0; + a2_data_delayed_1 <= 0; + a2_data_delayed_2 <= 0; + a3_data_delayed_1 <= 0; + a3_data_delayed_2 <= 0; + a3_data_delayed_3 <= 0; + a4_data_delayed_1 <= 0; + a4_data_delayed_2 <= 0; + a4_data_delayed_3 <= 0; + a4_data_delayed_4 <= 0; + a5_data_delayed_1 <= 0; + a5_data_delayed_2 <= 0; + a5_data_delayed_3 <= 0; + a5_data_delayed_4 <= 0; + a5_data_delayed_5 <= 0; + a6_data_delayed_1 <= 0; + a6_data_delayed_2 <= 0; + a6_data_delayed_3 <= 0; + a6_data_delayed_4 <= 0; + a6_data_delayed_5 <= 0; + a6_data_delayed_6 <= 0; + a7_data_delayed_1 <= 0; + a7_data_delayed_2 <= 0; + a7_data_delayed_3 <= 0; + a7_data_delayed_4 <= 0; + a7_data_delayed_5 <= 0; + a7_data_delayed_6 <= 0; + a7_data_delayed_7 <= 0; + a8_data_delayed_1 <= 0; + a8_data_delayed_2 <= 0; + a8_data_delayed_3 <= 0; + a8_data_delayed_4 <= 0; + a8_data_delayed_5 <= 0; + a8_data_delayed_6 <= 0; + a8_data_delayed_7 <= 0; + a8_data_delayed_8 <= 0; + a9_data_delayed_1 <= 0; + a9_data_delayed_2 <= 0; + a9_data_delayed_3 <= 0; + a9_data_delayed_4 <= 0; + a9_data_delayed_5 <= 0; + a9_data_delayed_6 <= 0; + a9_data_delayed_7 <= 0; + a9_data_delayed_8 <= 0; + a9_data_delayed_9 <= 0; + a10_data_delayed_1 <= 0; + a10_data_delayed_2 <= 0; + a10_data_delayed_3 <= 0; + a10_data_delayed_4 <= 0; + a10_data_delayed_5 <= 0; + a10_data_delayed_6 <= 0; + a10_data_delayed_7 <= 0; + a10_data_delayed_8 <= 0; + a10_data_delayed_9 <= 0; + a10_data_delayed_10 <= 0; + a11_data_delayed_1 <= 0; + a11_data_delayed_2 <= 0; + a11_data_delayed_3 <= 0; + a11_data_delayed_4 <= 0; + a11_data_delayed_5 <= 0; + a11_data_delayed_6 <= 0; + a11_data_delayed_7 <= 0; + a11_data_delayed_8 <= 0; + a11_data_delayed_9 <= 0; + a11_data_delayed_10 <= 0; + a11_data_delayed_11 <= 0; + a12_data_delayed_1 <= 0; + a12_data_delayed_2 <= 0; + a12_data_delayed_3 <= 0; + a12_data_delayed_4 <= 0; + a12_data_delayed_5 <= 0; + a12_data_delayed_6 <= 0; + a12_data_delayed_7 <= 0; + a12_data_delayed_8 <= 0; + a12_data_delayed_9 <= 0; + a12_data_delayed_10 <= 0; + a12_data_delayed_11 <= 0; + a12_data_delayed_12 <= 0; + a13_data_delayed_1 <= 0; + a13_data_delayed_2 <= 0; + a13_data_delayed_3 <= 0; + a13_data_delayed_4 <= 0; + a13_data_delayed_5 <= 0; + a13_data_delayed_6 <= 0; + a13_data_delayed_7 <= 0; + a13_data_delayed_8 <= 0; + a13_data_delayed_9 <= 0; + a13_data_delayed_10 <= 0; + a13_data_delayed_11 <= 0; + a13_data_delayed_12 <= 0; + a13_data_delayed_13 <= 0; + a14_data_delayed_1 <= 0; + a14_data_delayed_2 <= 0; + a14_data_delayed_3 <= 0; + a14_data_delayed_4 <= 0; + a14_data_delayed_5 <= 0; + a14_data_delayed_6 <= 0; + a14_data_delayed_7 <= 0; + a14_data_delayed_8 <= 0; + a14_data_delayed_9 <= 0; + a14_data_delayed_10 <= 0; + a14_data_delayed_11 <= 0; + a14_data_delayed_12 <= 0; + a14_data_delayed_13 <= 0; + a14_data_delayed_14 <= 0; + a15_data_delayed_1 <= 0; + a15_data_delayed_2 <= 0; + a15_data_delayed_3 <= 0; + a15_data_delayed_4 <= 0; + a15_data_delayed_5 <= 0; + a15_data_delayed_6 <= 0; + a15_data_delayed_7 <= 0; + a15_data_delayed_8 <= 0; + a15_data_delayed_9 <= 0; + a15_data_delayed_10 <= 0; + a15_data_delayed_11 <= 0; + a15_data_delayed_12 <= 0; + a15_data_delayed_13 <= 0; + a15_data_delayed_14 <= 0; + a15_data_delayed_15 <= 0; + a16_data_delayed_1 <= 0; + a16_data_delayed_2 <= 0; + a16_data_delayed_3 <= 0; + a16_data_delayed_4 <= 0; + a16_data_delayed_5 <= 0; + a16_data_delayed_6 <= 0; + a16_data_delayed_7 <= 0; + a16_data_delayed_8 <= 0; + a16_data_delayed_9 <= 0; + a16_data_delayed_10 <= 0; + a16_data_delayed_11 <= 0; + a16_data_delayed_12 <= 0; + a16_data_delayed_13 <= 0; + a16_data_delayed_14 <= 0; + a16_data_delayed_15 <= 0; + a16_data_delayed_16 <= 0; + a17_data_delayed_1 <= 0; + a17_data_delayed_2 <= 0; + a17_data_delayed_3 <= 0; + a17_data_delayed_4 <= 0; + a17_data_delayed_5 <= 0; + a17_data_delayed_6 <= 0; + a17_data_delayed_7 <= 0; + a17_data_delayed_8 <= 0; + a17_data_delayed_9 <= 0; + a17_data_delayed_10 <= 0; + a17_data_delayed_11 <= 0; + a17_data_delayed_12 <= 0; + a17_data_delayed_13 <= 0; + a17_data_delayed_14 <= 0; + a17_data_delayed_15 <= 0; + a17_data_delayed_16 <= 0; + a17_data_delayed_17 <= 0; + a18_data_delayed_1 <= 0; + a18_data_delayed_2 <= 0; + a18_data_delayed_3 <= 0; + a18_data_delayed_4 <= 0; + a18_data_delayed_5 <= 0; + a18_data_delayed_6 <= 0; + a18_data_delayed_7 <= 0; + a18_data_delayed_8 <= 0; + a18_data_delayed_9 <= 0; + a18_data_delayed_10 <= 0; + a18_data_delayed_11 <= 0; + a18_data_delayed_12 <= 0; + a18_data_delayed_13 <= 0; + a18_data_delayed_14 <= 0; + a18_data_delayed_15 <= 0; + a18_data_delayed_16 <= 0; + a18_data_delayed_17 <= 0; + a18_data_delayed_18 <= 0; + a19_data_delayed_1 <= 0; + a19_data_delayed_2 <= 0; + a19_data_delayed_3 <= 0; + a19_data_delayed_4 <= 0; + a19_data_delayed_5 <= 0; + a19_data_delayed_6 <= 0; + a19_data_delayed_7 <= 0; + a19_data_delayed_8 <= 0; + a19_data_delayed_9 <= 0; + a19_data_delayed_10 <= 0; + a19_data_delayed_11 <= 0; + a19_data_delayed_12 <= 0; + a19_data_delayed_13 <= 0; + a19_data_delayed_14 <= 0; + a19_data_delayed_15 <= 0; + a19_data_delayed_16 <= 0; + a19_data_delayed_17 <= 0; + a19_data_delayed_18 <= 0; + a19_data_delayed_19 <= 0; + a20_data_delayed_1 <= 0; + a20_data_delayed_2 <= 0; + a20_data_delayed_3 <= 0; + a20_data_delayed_4 <= 0; + a20_data_delayed_5 <= 0; + a20_data_delayed_6 <= 0; + a20_data_delayed_7 <= 0; + a20_data_delayed_8 <= 0; + a20_data_delayed_9 <= 0; + a20_data_delayed_10 <= 0; + a20_data_delayed_11 <= 0; + a20_data_delayed_12 <= 0; + a20_data_delayed_13 <= 0; + a20_data_delayed_14 <= 0; + a20_data_delayed_15 <= 0; + a20_data_delayed_16 <= 0; + a20_data_delayed_17 <= 0; + a20_data_delayed_18 <= 0; + a20_data_delayed_19 <= 0; + a20_data_delayed_20 <= 0; + a21_data_delayed_1 <= 0; + a21_data_delayed_2 <= 0; + a21_data_delayed_3 <= 0; + a21_data_delayed_4 <= 0; + a21_data_delayed_5 <= 0; + a21_data_delayed_6 <= 0; + a21_data_delayed_7 <= 0; + a21_data_delayed_8 <= 0; + a21_data_delayed_9 <= 0; + a21_data_delayed_10 <= 0; + a21_data_delayed_11 <= 0; + a21_data_delayed_12 <= 0; + a21_data_delayed_13 <= 0; + a21_data_delayed_14 <= 0; + a21_data_delayed_15 <= 0; + a21_data_delayed_16 <= 0; + a21_data_delayed_17 <= 0; + a21_data_delayed_18 <= 0; + a21_data_delayed_19 <= 0; + a21_data_delayed_20 <= 0; + a21_data_delayed_21 <= 0; + a22_data_delayed_1 <= 0; + a22_data_delayed_2 <= 0; + a22_data_delayed_3 <= 0; + a22_data_delayed_4 <= 0; + a22_data_delayed_5 <= 0; + a22_data_delayed_6 <= 0; + a22_data_delayed_7 <= 0; + a22_data_delayed_8 <= 0; + a22_data_delayed_9 <= 0; + a22_data_delayed_10 <= 0; + a22_data_delayed_11 <= 0; + a22_data_delayed_12 <= 0; + a22_data_delayed_13 <= 0; + a22_data_delayed_14 <= 0; + a22_data_delayed_15 <= 0; + a22_data_delayed_16 <= 0; + a22_data_delayed_17 <= 0; + a22_data_delayed_18 <= 0; + a22_data_delayed_19 <= 0; + a22_data_delayed_20 <= 0; + a22_data_delayed_21 <= 0; + a22_data_delayed_22 <= 0; + a23_data_delayed_1 <= 0; + a23_data_delayed_2 <= 0; + a23_data_delayed_3 <= 0; + a23_data_delayed_4 <= 0; + a23_data_delayed_5 <= 0; + a23_data_delayed_6 <= 0; + a23_data_delayed_7 <= 0; + a23_data_delayed_8 <= 0; + a23_data_delayed_9 <= 0; + a23_data_delayed_10 <= 0; + a23_data_delayed_11 <= 0; + a23_data_delayed_12 <= 0; + a23_data_delayed_13 <= 0; + a23_data_delayed_14 <= 0; + a23_data_delayed_15 <= 0; + a23_data_delayed_16 <= 0; + a23_data_delayed_17 <= 0; + a23_data_delayed_18 <= 0; + a23_data_delayed_19 <= 0; + a23_data_delayed_20 <= 0; + a23_data_delayed_21 <= 0; + a23_data_delayed_22 <= 0; + a23_data_delayed_23 <= 0; + a24_data_delayed_1 <= 0; + a24_data_delayed_2 <= 0; + a24_data_delayed_3 <= 0; + a24_data_delayed_4 <= 0; + a24_data_delayed_5 <= 0; + a24_data_delayed_6 <= 0; + a24_data_delayed_7 <= 0; + a24_data_delayed_8 <= 0; + a24_data_delayed_9 <= 0; + a24_data_delayed_10 <= 0; + a24_data_delayed_11 <= 0; + a24_data_delayed_12 <= 0; + a24_data_delayed_13 <= 0; + a24_data_delayed_14 <= 0; + a24_data_delayed_15 <= 0; + a24_data_delayed_16 <= 0; + a24_data_delayed_17 <= 0; + a24_data_delayed_18 <= 0; + a24_data_delayed_19 <= 0; + a24_data_delayed_20 <= 0; + a24_data_delayed_21 <= 0; + a24_data_delayed_22 <= 0; + a24_data_delayed_23 <= 0; + a24_data_delayed_24 <= 0; + a25_data_delayed_1 <= 0; + a25_data_delayed_2 <= 0; + a25_data_delayed_3 <= 0; + a25_data_delayed_4 <= 0; + a25_data_delayed_5 <= 0; + a25_data_delayed_6 <= 0; + a25_data_delayed_7 <= 0; + a25_data_delayed_8 <= 0; + a25_data_delayed_9 <= 0; + a25_data_delayed_10 <= 0; + a25_data_delayed_11 <= 0; + a25_data_delayed_12 <= 0; + a25_data_delayed_13 <= 0; + a25_data_delayed_14 <= 0; + a25_data_delayed_15 <= 0; + a25_data_delayed_16 <= 0; + a25_data_delayed_17 <= 0; + a25_data_delayed_18 <= 0; + a25_data_delayed_19 <= 0; + a25_data_delayed_20 <= 0; + a25_data_delayed_21 <= 0; + a25_data_delayed_22 <= 0; + a25_data_delayed_23 <= 0; + a25_data_delayed_24 <= 0; + a25_data_delayed_25 <= 0; + a26_data_delayed_1 <= 0; + a26_data_delayed_2 <= 0; + a26_data_delayed_3 <= 0; + a26_data_delayed_4 <= 0; + a26_data_delayed_5 <= 0; + a26_data_delayed_6 <= 0; + a26_data_delayed_7 <= 0; + a26_data_delayed_8 <= 0; + a26_data_delayed_9 <= 0; + a26_data_delayed_10 <= 0; + a26_data_delayed_11 <= 0; + a26_data_delayed_12 <= 0; + a26_data_delayed_13 <= 0; + a26_data_delayed_14 <= 0; + a26_data_delayed_15 <= 0; + a26_data_delayed_16 <= 0; + a26_data_delayed_17 <= 0; + a26_data_delayed_18 <= 0; + a26_data_delayed_19 <= 0; + a26_data_delayed_20 <= 0; + a26_data_delayed_21 <= 0; + a26_data_delayed_22 <= 0; + a26_data_delayed_23 <= 0; + a26_data_delayed_24 <= 0; + a26_data_delayed_25 <= 0; + a26_data_delayed_26 <= 0; + a27_data_delayed_1 <= 0; + a27_data_delayed_2 <= 0; + a27_data_delayed_3 <= 0; + a27_data_delayed_4 <= 0; + a27_data_delayed_5 <= 0; + a27_data_delayed_6 <= 0; + a27_data_delayed_7 <= 0; + a27_data_delayed_8 <= 0; + a27_data_delayed_9 <= 0; + a27_data_delayed_10 <= 0; + a27_data_delayed_11 <= 0; + a27_data_delayed_12 <= 0; + a27_data_delayed_13 <= 0; + a27_data_delayed_14 <= 0; + a27_data_delayed_15 <= 0; + a27_data_delayed_16 <= 0; + a27_data_delayed_17 <= 0; + a27_data_delayed_18 <= 0; + a27_data_delayed_19 <= 0; + a27_data_delayed_20 <= 0; + a27_data_delayed_21 <= 0; + a27_data_delayed_22 <= 0; + a27_data_delayed_23 <= 0; + a27_data_delayed_24 <= 0; + a27_data_delayed_25 <= 0; + a27_data_delayed_26 <= 0; + a27_data_delayed_27 <= 0; + a28_data_delayed_1 <= 0; + a28_data_delayed_2 <= 0; + a28_data_delayed_3 <= 0; + a28_data_delayed_4 <= 0; + a28_data_delayed_5 <= 0; + a28_data_delayed_6 <= 0; + a28_data_delayed_7 <= 0; + a28_data_delayed_8 <= 0; + a28_data_delayed_9 <= 0; + a28_data_delayed_10 <= 0; + a28_data_delayed_11 <= 0; + a28_data_delayed_12 <= 0; + a28_data_delayed_13 <= 0; + a28_data_delayed_14 <= 0; + a28_data_delayed_15 <= 0; + a28_data_delayed_16 <= 0; + a28_data_delayed_17 <= 0; + a28_data_delayed_18 <= 0; + a28_data_delayed_19 <= 0; + a28_data_delayed_20 <= 0; + a28_data_delayed_21 <= 0; + a28_data_delayed_22 <= 0; + a28_data_delayed_23 <= 0; + a28_data_delayed_24 <= 0; + a28_data_delayed_25 <= 0; + a28_data_delayed_26 <= 0; + a28_data_delayed_27 <= 0; + a28_data_delayed_28 <= 0; + a29_data_delayed_1 <= 0; + a29_data_delayed_2 <= 0; + a29_data_delayed_3 <= 0; + a29_data_delayed_4 <= 0; + a29_data_delayed_5 <= 0; + a29_data_delayed_6 <= 0; + a29_data_delayed_7 <= 0; + a29_data_delayed_8 <= 0; + a29_data_delayed_9 <= 0; + a29_data_delayed_10 <= 0; + a29_data_delayed_11 <= 0; + a29_data_delayed_12 <= 0; + a29_data_delayed_13 <= 0; + a29_data_delayed_14 <= 0; + a29_data_delayed_15 <= 0; + a29_data_delayed_16 <= 0; + a29_data_delayed_17 <= 0; + a29_data_delayed_18 <= 0; + a29_data_delayed_19 <= 0; + a29_data_delayed_20 <= 0; + a29_data_delayed_21 <= 0; + a29_data_delayed_22 <= 0; + a29_data_delayed_23 <= 0; + a29_data_delayed_24 <= 0; + a29_data_delayed_25 <= 0; + a29_data_delayed_26 <= 0; + a29_data_delayed_27 <= 0; + a29_data_delayed_28 <= 0; + a29_data_delayed_29 <= 0; + a30_data_delayed_1 <= 0; + a30_data_delayed_2 <= 0; + a30_data_delayed_3 <= 0; + a30_data_delayed_4 <= 0; + a30_data_delayed_5 <= 0; + a30_data_delayed_6 <= 0; + a30_data_delayed_7 <= 0; + a30_data_delayed_8 <= 0; + a30_data_delayed_9 <= 0; + a30_data_delayed_10 <= 0; + a30_data_delayed_11 <= 0; + a30_data_delayed_12 <= 0; + a30_data_delayed_13 <= 0; + a30_data_delayed_14 <= 0; + a30_data_delayed_15 <= 0; + a30_data_delayed_16 <= 0; + a30_data_delayed_17 <= 0; + a30_data_delayed_18 <= 0; + a30_data_delayed_19 <= 0; + a30_data_delayed_20 <= 0; + a30_data_delayed_21 <= 0; + a30_data_delayed_22 <= 0; + a30_data_delayed_23 <= 0; + a30_data_delayed_24 <= 0; + a30_data_delayed_25 <= 0; + a30_data_delayed_26 <= 0; + a30_data_delayed_27 <= 0; + a30_data_delayed_28 <= 0; + a30_data_delayed_29 <= 0; + a30_data_delayed_30 <= 0; + a31_data_delayed_1 <= 0; + a31_data_delayed_2 <= 0; + a31_data_delayed_3 <= 0; + a31_data_delayed_4 <= 0; + a31_data_delayed_5 <= 0; + a31_data_delayed_6 <= 0; + a31_data_delayed_7 <= 0; + a31_data_delayed_8 <= 0; + a31_data_delayed_9 <= 0; + a31_data_delayed_10 <= 0; + a31_data_delayed_11 <= 0; + a31_data_delayed_12 <= 0; + a31_data_delayed_13 <= 0; + a31_data_delayed_14 <= 0; + a31_data_delayed_15 <= 0; + a31_data_delayed_16 <= 0; + a31_data_delayed_17 <= 0; + a31_data_delayed_18 <= 0; + a31_data_delayed_19 <= 0; + a31_data_delayed_20 <= 0; + a31_data_delayed_21 <= 0; + a31_data_delayed_22 <= 0; + a31_data_delayed_23 <= 0; + a31_data_delayed_24 <= 0; + a31_data_delayed_25 <= 0; + a31_data_delayed_26 <= 0; + a31_data_delayed_27 <= 0; + a31_data_delayed_28 <= 0; + a31_data_delayed_29 <= 0; + a31_data_delayed_30 <= 0; + a31_data_delayed_31 <= 0; + end + else begin + a1_data_delayed_1 <= a1_data; + a2_data_delayed_1 <= a2_data; + a2_data_delayed_2 <= a2_data_delayed_1; + a3_data_delayed_1 <= a3_data; + a3_data_delayed_2 <= a3_data_delayed_1; + a3_data_delayed_3 <= a3_data_delayed_2; + a4_data_delayed_1 <= a4_data; + a4_data_delayed_2 <= a4_data_delayed_1; + a4_data_delayed_3 <= a4_data_delayed_2; + a4_data_delayed_4 <= a4_data_delayed_3; + a5_data_delayed_1 <= a5_data; + a5_data_delayed_2 <= a5_data_delayed_1; + a5_data_delayed_3 <= a5_data_delayed_2; + a5_data_delayed_4 <= a5_data_delayed_3; + a5_data_delayed_5 <= a5_data_delayed_4; + a6_data_delayed_1 <= a6_data; + a6_data_delayed_2 <= a6_data_delayed_1; + a6_data_delayed_3 <= a6_data_delayed_2; + a6_data_delayed_4 <= a6_data_delayed_3; + a6_data_delayed_5 <= a6_data_delayed_4; + a6_data_delayed_6 <= a6_data_delayed_5; + a7_data_delayed_1 <= a7_data; + a7_data_delayed_2 <= a7_data_delayed_1; + a7_data_delayed_3 <= a7_data_delayed_2; + a7_data_delayed_4 <= a7_data_delayed_3; + a7_data_delayed_5 <= a7_data_delayed_4; + a7_data_delayed_6 <= a7_data_delayed_5; + a7_data_delayed_7 <= a7_data_delayed_6; + a8_data_delayed_1 <= a8_data; + a8_data_delayed_2 <= a8_data_delayed_1; + a8_data_delayed_3 <= a8_data_delayed_2; + a8_data_delayed_4 <= a8_data_delayed_3; + a8_data_delayed_5 <= a8_data_delayed_4; + a8_data_delayed_6 <= a8_data_delayed_5; + a8_data_delayed_7 <= a8_data_delayed_6; + a8_data_delayed_8 <= a8_data_delayed_7; + a9_data_delayed_1 <= a9_data; + a9_data_delayed_2 <= a9_data_delayed_1; + a9_data_delayed_3 <= a9_data_delayed_2; + a9_data_delayed_4 <= a9_data_delayed_3; + a9_data_delayed_5 <= a9_data_delayed_4; + a9_data_delayed_6 <= a9_data_delayed_5; + a9_data_delayed_7 <= a9_data_delayed_6; + a9_data_delayed_8 <= a9_data_delayed_7; + a9_data_delayed_9 <= a9_data_delayed_8; + a10_data_delayed_1 <= a10_data; + a10_data_delayed_2 <= a10_data_delayed_1; + a10_data_delayed_3 <= a10_data_delayed_2; + a10_data_delayed_4 <= a10_data_delayed_3; + a10_data_delayed_5 <= a10_data_delayed_4; + a10_data_delayed_6 <= a10_data_delayed_5; + a10_data_delayed_7 <= a10_data_delayed_6; + a10_data_delayed_8 <= a10_data_delayed_7; + a10_data_delayed_9 <= a10_data_delayed_8; + a10_data_delayed_10 <= a10_data_delayed_9; + a11_data_delayed_1 <= a11_data; + a11_data_delayed_2 <= a11_data_delayed_1; + a11_data_delayed_3 <= a11_data_delayed_2; + a11_data_delayed_4 <= a11_data_delayed_3; + a11_data_delayed_5 <= a11_data_delayed_4; + a11_data_delayed_6 <= a11_data_delayed_5; + a11_data_delayed_7 <= a11_data_delayed_6; + a11_data_delayed_8 <= a11_data_delayed_7; + a11_data_delayed_9 <= a11_data_delayed_8; + a11_data_delayed_10 <= a11_data_delayed_9; + a11_data_delayed_11 <= a11_data_delayed_10; + a12_data_delayed_1 <= a12_data; + a12_data_delayed_2 <= a12_data_delayed_1; + a12_data_delayed_3 <= a12_data_delayed_2; + a12_data_delayed_4 <= a12_data_delayed_3; + a12_data_delayed_5 <= a12_data_delayed_4; + a12_data_delayed_6 <= a12_data_delayed_5; + a12_data_delayed_7 <= a12_data_delayed_6; + a12_data_delayed_8 <= a12_data_delayed_7; + a12_data_delayed_9 <= a12_data_delayed_8; + a12_data_delayed_10 <= a12_data_delayed_9; + a12_data_delayed_11 <= a12_data_delayed_10; + a12_data_delayed_12 <= a12_data_delayed_11; + a13_data_delayed_1 <= a13_data; + a13_data_delayed_2 <= a13_data_delayed_1; + a13_data_delayed_3 <= a13_data_delayed_2; + a13_data_delayed_4 <= a13_data_delayed_3; + a13_data_delayed_5 <= a13_data_delayed_4; + a13_data_delayed_6 <= a13_data_delayed_5; + a13_data_delayed_7 <= a13_data_delayed_6; + a13_data_delayed_8 <= a13_data_delayed_7; + a13_data_delayed_9 <= a13_data_delayed_8; + a13_data_delayed_10 <= a13_data_delayed_9; + a13_data_delayed_11 <= a13_data_delayed_10; + a13_data_delayed_12 <= a13_data_delayed_11; + a13_data_delayed_13 <= a13_data_delayed_12; + a14_data_delayed_1 <= a14_data; + a14_data_delayed_2 <= a14_data_delayed_1; + a14_data_delayed_3 <= a14_data_delayed_2; + a14_data_delayed_4 <= a14_data_delayed_3; + a14_data_delayed_5 <= a14_data_delayed_4; + a14_data_delayed_6 <= a14_data_delayed_5; + a14_data_delayed_7 <= a14_data_delayed_6; + a14_data_delayed_8 <= a14_data_delayed_7; + a14_data_delayed_9 <= a14_data_delayed_8; + a14_data_delayed_10 <= a14_data_delayed_9; + a14_data_delayed_11 <= a14_data_delayed_10; + a14_data_delayed_12 <= a14_data_delayed_11; + a14_data_delayed_13 <= a14_data_delayed_12; + a14_data_delayed_14 <= a14_data_delayed_13; + a15_data_delayed_1 <= a15_data; + a15_data_delayed_2 <= a15_data_delayed_1; + a15_data_delayed_3 <= a15_data_delayed_2; + a15_data_delayed_4 <= a15_data_delayed_3; + a15_data_delayed_5 <= a15_data_delayed_4; + a15_data_delayed_6 <= a15_data_delayed_5; + a15_data_delayed_7 <= a15_data_delayed_6; + a15_data_delayed_8 <= a15_data_delayed_7; + a15_data_delayed_9 <= a15_data_delayed_8; + a15_data_delayed_10 <= a15_data_delayed_9; + a15_data_delayed_11 <= a15_data_delayed_10; + a15_data_delayed_12 <= a15_data_delayed_11; + a15_data_delayed_13 <= a15_data_delayed_12; + a15_data_delayed_14 <= a15_data_delayed_13; + a15_data_delayed_15 <= a15_data_delayed_14; + a16_data_delayed_1 <= a16_data; + a16_data_delayed_2 <= a16_data_delayed_1; + a16_data_delayed_3 <= a16_data_delayed_2; + a16_data_delayed_4 <= a16_data_delayed_3; + a16_data_delayed_5 <= a16_data_delayed_4; + a16_data_delayed_6 <= a16_data_delayed_5; + a16_data_delayed_7 <= a16_data_delayed_6; + a16_data_delayed_8 <= a16_data_delayed_7; + a16_data_delayed_9 <= a16_data_delayed_8; + a16_data_delayed_10 <= a16_data_delayed_9; + a16_data_delayed_11 <= a16_data_delayed_10; + a16_data_delayed_12 <= a16_data_delayed_11; + a16_data_delayed_13 <= a16_data_delayed_12; + a16_data_delayed_14 <= a16_data_delayed_13; + a16_data_delayed_15 <= a16_data_delayed_14; + a16_data_delayed_16 <= a16_data_delayed_15; + a17_data_delayed_1 <= a17_data; + a17_data_delayed_2 <= a17_data_delayed_1; + a17_data_delayed_3 <= a17_data_delayed_2; + a17_data_delayed_4 <= a17_data_delayed_3; + a17_data_delayed_5 <= a17_data_delayed_4; + a17_data_delayed_6 <= a17_data_delayed_5; + a17_data_delayed_7 <= a17_data_delayed_6; + a17_data_delayed_8 <= a17_data_delayed_7; + a17_data_delayed_9 <= a17_data_delayed_8; + a17_data_delayed_10 <= a17_data_delayed_9; + a17_data_delayed_11 <= a17_data_delayed_10; + a17_data_delayed_12 <= a17_data_delayed_11; + a17_data_delayed_13 <= a17_data_delayed_12; + a17_data_delayed_14 <= a17_data_delayed_13; + a17_data_delayed_15 <= a17_data_delayed_14; + a17_data_delayed_16 <= a17_data_delayed_15; + a17_data_delayed_17 <= a17_data_delayed_16; + a18_data_delayed_1 <= a18_data; + a18_data_delayed_2 <= a18_data_delayed_1; + a18_data_delayed_3 <= a18_data_delayed_2; + a18_data_delayed_4 <= a18_data_delayed_3; + a18_data_delayed_5 <= a18_data_delayed_4; + a18_data_delayed_6 <= a18_data_delayed_5; + a18_data_delayed_7 <= a18_data_delayed_6; + a18_data_delayed_8 <= a18_data_delayed_7; + a18_data_delayed_9 <= a18_data_delayed_8; + a18_data_delayed_10 <= a18_data_delayed_9; + a18_data_delayed_11 <= a18_data_delayed_10; + a18_data_delayed_12 <= a18_data_delayed_11; + a18_data_delayed_13 <= a18_data_delayed_12; + a18_data_delayed_14 <= a18_data_delayed_13; + a18_data_delayed_15 <= a18_data_delayed_14; + a18_data_delayed_16 <= a18_data_delayed_15; + a18_data_delayed_17 <= a18_data_delayed_16; + a18_data_delayed_18 <= a18_data_delayed_17; + a19_data_delayed_1 <= a19_data; + a19_data_delayed_2 <= a19_data_delayed_1; + a19_data_delayed_3 <= a19_data_delayed_2; + a19_data_delayed_4 <= a19_data_delayed_3; + a19_data_delayed_5 <= a19_data_delayed_4; + a19_data_delayed_6 <= a19_data_delayed_5; + a19_data_delayed_7 <= a19_data_delayed_6; + a19_data_delayed_8 <= a19_data_delayed_7; + a19_data_delayed_9 <= a19_data_delayed_8; + a19_data_delayed_10 <= a19_data_delayed_9; + a19_data_delayed_11 <= a19_data_delayed_10; + a19_data_delayed_12 <= a19_data_delayed_11; + a19_data_delayed_13 <= a19_data_delayed_12; + a19_data_delayed_14 <= a19_data_delayed_13; + a19_data_delayed_15 <= a19_data_delayed_14; + a19_data_delayed_16 <= a19_data_delayed_15; + a19_data_delayed_17 <= a19_data_delayed_16; + a19_data_delayed_18 <= a19_data_delayed_17; + a19_data_delayed_19 <= a19_data_delayed_18; + a20_data_delayed_1 <= a20_data; + a20_data_delayed_2 <= a20_data_delayed_1; + a20_data_delayed_3 <= a20_data_delayed_2; + a20_data_delayed_4 <= a20_data_delayed_3; + a20_data_delayed_5 <= a20_data_delayed_4; + a20_data_delayed_6 <= a20_data_delayed_5; + a20_data_delayed_7 <= a20_data_delayed_6; + a20_data_delayed_8 <= a20_data_delayed_7; + a20_data_delayed_9 <= a20_data_delayed_8; + a20_data_delayed_10 <= a20_data_delayed_9; + a20_data_delayed_11 <= a20_data_delayed_10; + a20_data_delayed_12 <= a20_data_delayed_11; + a20_data_delayed_13 <= a20_data_delayed_12; + a20_data_delayed_14 <= a20_data_delayed_13; + a20_data_delayed_15 <= a20_data_delayed_14; + a20_data_delayed_16 <= a20_data_delayed_15; + a20_data_delayed_17 <= a20_data_delayed_16; + a20_data_delayed_18 <= a20_data_delayed_17; + a20_data_delayed_19 <= a20_data_delayed_18; + a20_data_delayed_20 <= a20_data_delayed_19; + a21_data_delayed_1 <= a21_data; + a21_data_delayed_2 <= a21_data_delayed_1; + a21_data_delayed_3 <= a21_data_delayed_2; + a21_data_delayed_4 <= a21_data_delayed_3; + a21_data_delayed_5 <= a21_data_delayed_4; + a21_data_delayed_6 <= a21_data_delayed_5; + a21_data_delayed_7 <= a21_data_delayed_6; + a21_data_delayed_8 <= a21_data_delayed_7; + a21_data_delayed_9 <= a21_data_delayed_8; + a21_data_delayed_10 <= a21_data_delayed_9; + a21_data_delayed_11 <= a21_data_delayed_10; + a21_data_delayed_12 <= a21_data_delayed_11; + a21_data_delayed_13 <= a21_data_delayed_12; + a21_data_delayed_14 <= a21_data_delayed_13; + a21_data_delayed_15 <= a21_data_delayed_14; + a21_data_delayed_16 <= a21_data_delayed_15; + a21_data_delayed_17 <= a21_data_delayed_16; + a21_data_delayed_18 <= a21_data_delayed_17; + a21_data_delayed_19 <= a21_data_delayed_18; + a21_data_delayed_20 <= a21_data_delayed_19; + a21_data_delayed_21 <= a21_data_delayed_20; + a22_data_delayed_1 <= a22_data; + a22_data_delayed_2 <= a22_data_delayed_1; + a22_data_delayed_3 <= a22_data_delayed_2; + a22_data_delayed_4 <= a22_data_delayed_3; + a22_data_delayed_5 <= a22_data_delayed_4; + a22_data_delayed_6 <= a22_data_delayed_5; + a22_data_delayed_7 <= a22_data_delayed_6; + a22_data_delayed_8 <= a22_data_delayed_7; + a22_data_delayed_9 <= a22_data_delayed_8; + a22_data_delayed_10 <= a22_data_delayed_9; + a22_data_delayed_11 <= a22_data_delayed_10; + a22_data_delayed_12 <= a22_data_delayed_11; + a22_data_delayed_13 <= a22_data_delayed_12; + a22_data_delayed_14 <= a22_data_delayed_13; + a22_data_delayed_15 <= a22_data_delayed_14; + a22_data_delayed_16 <= a22_data_delayed_15; + a22_data_delayed_17 <= a22_data_delayed_16; + a22_data_delayed_18 <= a22_data_delayed_17; + a22_data_delayed_19 <= a22_data_delayed_18; + a22_data_delayed_20 <= a22_data_delayed_19; + a22_data_delayed_21 <= a22_data_delayed_20; + a22_data_delayed_22 <= a22_data_delayed_21; + a23_data_delayed_1 <= a23_data; + a23_data_delayed_2 <= a23_data_delayed_1; + a23_data_delayed_3 <= a23_data_delayed_2; + a23_data_delayed_4 <= a23_data_delayed_3; + a23_data_delayed_5 <= a23_data_delayed_4; + a23_data_delayed_6 <= a23_data_delayed_5; + a23_data_delayed_7 <= a23_data_delayed_6; + a23_data_delayed_8 <= a23_data_delayed_7; + a23_data_delayed_9 <= a23_data_delayed_8; + a23_data_delayed_10 <= a23_data_delayed_9; + a23_data_delayed_11 <= a23_data_delayed_10; + a23_data_delayed_12 <= a23_data_delayed_11; + a23_data_delayed_13 <= a23_data_delayed_12; + a23_data_delayed_14 <= a23_data_delayed_13; + a23_data_delayed_15 <= a23_data_delayed_14; + a23_data_delayed_16 <= a23_data_delayed_15; + a23_data_delayed_17 <= a23_data_delayed_16; + a23_data_delayed_18 <= a23_data_delayed_17; + a23_data_delayed_19 <= a23_data_delayed_18; + a23_data_delayed_20 <= a23_data_delayed_19; + a23_data_delayed_21 <= a23_data_delayed_20; + a23_data_delayed_22 <= a23_data_delayed_21; + a23_data_delayed_23 <= a23_data_delayed_22; + a24_data_delayed_1 <= a24_data; + a24_data_delayed_2 <= a24_data_delayed_1; + a24_data_delayed_3 <= a24_data_delayed_2; + a24_data_delayed_4 <= a24_data_delayed_3; + a24_data_delayed_5 <= a24_data_delayed_4; + a24_data_delayed_6 <= a24_data_delayed_5; + a24_data_delayed_7 <= a24_data_delayed_6; + a24_data_delayed_8 <= a24_data_delayed_7; + a24_data_delayed_9 <= a24_data_delayed_8; + a24_data_delayed_10 <= a24_data_delayed_9; + a24_data_delayed_11 <= a24_data_delayed_10; + a24_data_delayed_12 <= a24_data_delayed_11; + a24_data_delayed_13 <= a24_data_delayed_12; + a24_data_delayed_14 <= a24_data_delayed_13; + a24_data_delayed_15 <= a24_data_delayed_14; + a24_data_delayed_16 <= a24_data_delayed_15; + a24_data_delayed_17 <= a24_data_delayed_16; + a24_data_delayed_18 <= a24_data_delayed_17; + a24_data_delayed_19 <= a24_data_delayed_18; + a24_data_delayed_20 <= a24_data_delayed_19; + a24_data_delayed_21 <= a24_data_delayed_20; + a24_data_delayed_22 <= a24_data_delayed_21; + a24_data_delayed_23 <= a24_data_delayed_22; + a24_data_delayed_24 <= a24_data_delayed_23; + a25_data_delayed_1 <= a25_data; + a25_data_delayed_2 <= a25_data_delayed_1; + a25_data_delayed_3 <= a25_data_delayed_2; + a25_data_delayed_4 <= a25_data_delayed_3; + a25_data_delayed_5 <= a25_data_delayed_4; + a25_data_delayed_6 <= a25_data_delayed_5; + a25_data_delayed_7 <= a25_data_delayed_6; + a25_data_delayed_8 <= a25_data_delayed_7; + a25_data_delayed_9 <= a25_data_delayed_8; + a25_data_delayed_10 <= a25_data_delayed_9; + a25_data_delayed_11 <= a25_data_delayed_10; + a25_data_delayed_12 <= a25_data_delayed_11; + a25_data_delayed_13 <= a25_data_delayed_12; + a25_data_delayed_14 <= a25_data_delayed_13; + a25_data_delayed_15 <= a25_data_delayed_14; + a25_data_delayed_16 <= a25_data_delayed_15; + a25_data_delayed_17 <= a25_data_delayed_16; + a25_data_delayed_18 <= a25_data_delayed_17; + a25_data_delayed_19 <= a25_data_delayed_18; + a25_data_delayed_20 <= a25_data_delayed_19; + a25_data_delayed_21 <= a25_data_delayed_20; + a25_data_delayed_22 <= a25_data_delayed_21; + a25_data_delayed_23 <= a25_data_delayed_22; + a25_data_delayed_24 <= a25_data_delayed_23; + a25_data_delayed_25 <= a25_data_delayed_24; + a26_data_delayed_1 <= a26_data; + a26_data_delayed_2 <= a26_data_delayed_1; + a26_data_delayed_3 <= a26_data_delayed_2; + a26_data_delayed_4 <= a26_data_delayed_3; + a26_data_delayed_5 <= a26_data_delayed_4; + a26_data_delayed_6 <= a26_data_delayed_5; + a26_data_delayed_7 <= a26_data_delayed_6; + a26_data_delayed_8 <= a26_data_delayed_7; + a26_data_delayed_9 <= a26_data_delayed_8; + a26_data_delayed_10 <= a26_data_delayed_9; + a26_data_delayed_11 <= a26_data_delayed_10; + a26_data_delayed_12 <= a26_data_delayed_11; + a26_data_delayed_13 <= a26_data_delayed_12; + a26_data_delayed_14 <= a26_data_delayed_13; + a26_data_delayed_15 <= a26_data_delayed_14; + a26_data_delayed_16 <= a26_data_delayed_15; + a26_data_delayed_17 <= a26_data_delayed_16; + a26_data_delayed_18 <= a26_data_delayed_17; + a26_data_delayed_19 <= a26_data_delayed_18; + a26_data_delayed_20 <= a26_data_delayed_19; + a26_data_delayed_21 <= a26_data_delayed_20; + a26_data_delayed_22 <= a26_data_delayed_21; + a26_data_delayed_23 <= a26_data_delayed_22; + a26_data_delayed_24 <= a26_data_delayed_23; + a26_data_delayed_25 <= a26_data_delayed_24; + a26_data_delayed_26 <= a26_data_delayed_25; + a27_data_delayed_1 <= a27_data; + a27_data_delayed_2 <= a27_data_delayed_1; + a27_data_delayed_3 <= a27_data_delayed_2; + a27_data_delayed_4 <= a27_data_delayed_3; + a27_data_delayed_5 <= a27_data_delayed_4; + a27_data_delayed_6 <= a27_data_delayed_5; + a27_data_delayed_7 <= a27_data_delayed_6; + a27_data_delayed_8 <= a27_data_delayed_7; + a27_data_delayed_9 <= a27_data_delayed_8; + a27_data_delayed_10 <= a27_data_delayed_9; + a27_data_delayed_11 <= a27_data_delayed_10; + a27_data_delayed_12 <= a27_data_delayed_11; + a27_data_delayed_13 <= a27_data_delayed_12; + a27_data_delayed_14 <= a27_data_delayed_13; + a27_data_delayed_15 <= a27_data_delayed_14; + a27_data_delayed_16 <= a27_data_delayed_15; + a27_data_delayed_17 <= a27_data_delayed_16; + a27_data_delayed_18 <= a27_data_delayed_17; + a27_data_delayed_19 <= a27_data_delayed_18; + a27_data_delayed_20 <= a27_data_delayed_19; + a27_data_delayed_21 <= a27_data_delayed_20; + a27_data_delayed_22 <= a27_data_delayed_21; + a27_data_delayed_23 <= a27_data_delayed_22; + a27_data_delayed_24 <= a27_data_delayed_23; + a27_data_delayed_25 <= a27_data_delayed_24; + a27_data_delayed_26 <= a27_data_delayed_25; + a27_data_delayed_27 <= a27_data_delayed_26; + a28_data_delayed_1 <= a28_data; + a28_data_delayed_2 <= a28_data_delayed_1; + a28_data_delayed_3 <= a28_data_delayed_2; + a28_data_delayed_4 <= a28_data_delayed_3; + a28_data_delayed_5 <= a28_data_delayed_4; + a28_data_delayed_6 <= a28_data_delayed_5; + a28_data_delayed_7 <= a28_data_delayed_6; + a28_data_delayed_8 <= a28_data_delayed_7; + a28_data_delayed_9 <= a28_data_delayed_8; + a28_data_delayed_10 <= a28_data_delayed_9; + a28_data_delayed_11 <= a28_data_delayed_10; + a28_data_delayed_12 <= a28_data_delayed_11; + a28_data_delayed_13 <= a28_data_delayed_12; + a28_data_delayed_14 <= a28_data_delayed_13; + a28_data_delayed_15 <= a28_data_delayed_14; + a28_data_delayed_16 <= a28_data_delayed_15; + a28_data_delayed_17 <= a28_data_delayed_16; + a28_data_delayed_18 <= a28_data_delayed_17; + a28_data_delayed_19 <= a28_data_delayed_18; + a28_data_delayed_20 <= a28_data_delayed_19; + a28_data_delayed_21 <= a28_data_delayed_20; + a28_data_delayed_22 <= a28_data_delayed_21; + a28_data_delayed_23 <= a28_data_delayed_22; + a28_data_delayed_24 <= a28_data_delayed_23; + a28_data_delayed_25 <= a28_data_delayed_24; + a28_data_delayed_26 <= a28_data_delayed_25; + a28_data_delayed_27 <= a28_data_delayed_26; + a28_data_delayed_28 <= a28_data_delayed_27; + a29_data_delayed_1 <= a29_data; + a29_data_delayed_2 <= a29_data_delayed_1; + a29_data_delayed_3 <= a29_data_delayed_2; + a29_data_delayed_4 <= a29_data_delayed_3; + a29_data_delayed_5 <= a29_data_delayed_4; + a29_data_delayed_6 <= a29_data_delayed_5; + a29_data_delayed_7 <= a29_data_delayed_6; + a29_data_delayed_8 <= a29_data_delayed_7; + a29_data_delayed_9 <= a29_data_delayed_8; + a29_data_delayed_10 <= a29_data_delayed_9; + a29_data_delayed_11 <= a29_data_delayed_10; + a29_data_delayed_12 <= a29_data_delayed_11; + a29_data_delayed_13 <= a29_data_delayed_12; + a29_data_delayed_14 <= a29_data_delayed_13; + a29_data_delayed_15 <= a29_data_delayed_14; + a29_data_delayed_16 <= a29_data_delayed_15; + a29_data_delayed_17 <= a29_data_delayed_16; + a29_data_delayed_18 <= a29_data_delayed_17; + a29_data_delayed_19 <= a29_data_delayed_18; + a29_data_delayed_20 <= a29_data_delayed_19; + a29_data_delayed_21 <= a29_data_delayed_20; + a29_data_delayed_22 <= a29_data_delayed_21; + a29_data_delayed_23 <= a29_data_delayed_22; + a29_data_delayed_24 <= a29_data_delayed_23; + a29_data_delayed_25 <= a29_data_delayed_24; + a29_data_delayed_26 <= a29_data_delayed_25; + a29_data_delayed_27 <= a29_data_delayed_26; + a29_data_delayed_28 <= a29_data_delayed_27; + a29_data_delayed_29 <= a29_data_delayed_28; + a30_data_delayed_1 <= a30_data; + a30_data_delayed_2 <= a30_data_delayed_1; + a30_data_delayed_3 <= a30_data_delayed_2; + a30_data_delayed_4 <= a30_data_delayed_3; + a30_data_delayed_5 <= a30_data_delayed_4; + a30_data_delayed_6 <= a30_data_delayed_5; + a30_data_delayed_7 <= a30_data_delayed_6; + a30_data_delayed_8 <= a30_data_delayed_7; + a30_data_delayed_9 <= a30_data_delayed_8; + a30_data_delayed_10 <= a30_data_delayed_9; + a30_data_delayed_11 <= a30_data_delayed_10; + a30_data_delayed_12 <= a30_data_delayed_11; + a30_data_delayed_13 <= a30_data_delayed_12; + a30_data_delayed_14 <= a30_data_delayed_13; + a30_data_delayed_15 <= a30_data_delayed_14; + a30_data_delayed_16 <= a30_data_delayed_15; + a30_data_delayed_17 <= a30_data_delayed_16; + a30_data_delayed_18 <= a30_data_delayed_17; + a30_data_delayed_19 <= a30_data_delayed_18; + a30_data_delayed_20 <= a30_data_delayed_19; + a30_data_delayed_21 <= a30_data_delayed_20; + a30_data_delayed_22 <= a30_data_delayed_21; + a30_data_delayed_23 <= a30_data_delayed_22; + a30_data_delayed_24 <= a30_data_delayed_23; + a30_data_delayed_25 <= a30_data_delayed_24; + a30_data_delayed_26 <= a30_data_delayed_25; + a30_data_delayed_27 <= a30_data_delayed_26; + a30_data_delayed_28 <= a30_data_delayed_27; + a30_data_delayed_29 <= a30_data_delayed_28; + a30_data_delayed_30 <= a30_data_delayed_29; + a31_data_delayed_1 <= a31_data; + a31_data_delayed_2 <= a31_data_delayed_1; + a31_data_delayed_3 <= a31_data_delayed_2; + a31_data_delayed_4 <= a31_data_delayed_3; + a31_data_delayed_5 <= a31_data_delayed_4; + a31_data_delayed_6 <= a31_data_delayed_5; + a31_data_delayed_7 <= a31_data_delayed_6; + a31_data_delayed_8 <= a31_data_delayed_7; + a31_data_delayed_9 <= a31_data_delayed_8; + a31_data_delayed_10 <= a31_data_delayed_9; + a31_data_delayed_11 <= a31_data_delayed_10; + a31_data_delayed_12 <= a31_data_delayed_11; + a31_data_delayed_13 <= a31_data_delayed_12; + a31_data_delayed_14 <= a31_data_delayed_13; + a31_data_delayed_15 <= a31_data_delayed_14; + a31_data_delayed_16 <= a31_data_delayed_15; + a31_data_delayed_17 <= a31_data_delayed_16; + a31_data_delayed_18 <= a31_data_delayed_17; + a31_data_delayed_19 <= a31_data_delayed_18; + a31_data_delayed_20 <= a31_data_delayed_19; + a31_data_delayed_21 <= a31_data_delayed_20; + a31_data_delayed_22 <= a31_data_delayed_21; + a31_data_delayed_23 <= a31_data_delayed_22; + a31_data_delayed_24 <= a31_data_delayed_23; + a31_data_delayed_25 <= a31_data_delayed_24; + a31_data_delayed_26 <= a31_data_delayed_25; + a31_data_delayed_27 <= a31_data_delayed_26; + a31_data_delayed_28 <= a31_data_delayed_27; + a31_data_delayed_29 <= a31_data_delayed_28; + a31_data_delayed_30 <= a31_data_delayed_29; + a31_data_delayed_31 <= a31_data_delayed_30; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM B +////////////////////////////////////////////////////////////////////////// + +reg [`AWIDTH-1:0] b_addr; +reg b_mem_access; // flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin + if ((reset || ~start_mat_mul) || (clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)+num_matrices_B << `LOG2_MAT_MUL_SIZE)) begin + b_addr <= address_mat_b - address_stride_b; + b_mem_access <= 0; + end + else if ((clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (b_loc<<`LOG2_MAT_MUL_SIZE)+num_matrices_B << `LOG2_MAT_MUL_SIZE)) begin + b_addr <= b_addr + address_stride_b; + b_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM B +////////////////////////////////////////////////////////////////////////// + +reg [7:0] b_mem_access_counter; + +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + b_mem_access_counter <= 0; + end + else if (b_mem_access == 1) begin + b_mem_access_counter <= b_mem_access_counter + 1; + end + else begin + b_mem_access_counter <= 0; + end +end + +assign b_data_valid = + ((validity_mask_a_cols_b_rows[0]==1'b0 && b_mem_access_counter==1) || + (validity_mask_a_cols_b_rows[1]==1'b0 && b_mem_access_counter==2) || + (validity_mask_a_cols_b_rows[2]==1'b0 && b_mem_access_counter==3) || + (validity_mask_a_cols_b_rows[3]==1'b0 && b_mem_access_counter==4) || + (validity_mask_a_cols_b_rows[4]==1'b0 && b_mem_access_counter==5) || + (validity_mask_a_cols_b_rows[5]==1'b0 && b_mem_access_counter==6) || + (validity_mask_a_cols_b_rows[6]==1'b0 && b_mem_access_counter==7) || + (validity_mask_a_cols_b_rows[7]==1'b0 && b_mem_access_counter==8) || + (validity_mask_a_cols_b_rows[8]==1'b0 && b_mem_access_counter==9) || + (validity_mask_a_cols_b_rows[9]==1'b0 && b_mem_access_counter==10) || + (validity_mask_a_cols_b_rows[10]==1'b0 && b_mem_access_counter==11) || + (validity_mask_a_cols_b_rows[11]==1'b0 && b_mem_access_counter==12) || + (validity_mask_a_cols_b_rows[12]==1'b0 && b_mem_access_counter==13) || + (validity_mask_a_cols_b_rows[13]==1'b0 && b_mem_access_counter==14) || + (validity_mask_a_cols_b_rows[14]==1'b0 && b_mem_access_counter==15) || + (validity_mask_a_cols_b_rows[15]==1'b0 && b_mem_access_counter==16) || + (validity_mask_a_cols_b_rows[16]==1'b0 && b_mem_access_counter==17) || + (validity_mask_a_cols_b_rows[17]==1'b0 && b_mem_access_counter==18) || + (validity_mask_a_cols_b_rows[18]==1'b0 && b_mem_access_counter==19) || + (validity_mask_a_cols_b_rows[19]==1'b0 && b_mem_access_counter==20) || + (validity_mask_a_cols_b_rows[20]==1'b0 && b_mem_access_counter==21) || + (validity_mask_a_cols_b_rows[21]==1'b0 && b_mem_access_counter==22) || + (validity_mask_a_cols_b_rows[22]==1'b0 && b_mem_access_counter==23) || + (validity_mask_a_cols_b_rows[23]==1'b0 && b_mem_access_counter==24) || + (validity_mask_a_cols_b_rows[24]==1'b0 && b_mem_access_counter==25) || + (validity_mask_a_cols_b_rows[25]==1'b0 && b_mem_access_counter==26) || + (validity_mask_a_cols_b_rows[26]==1'b0 && b_mem_access_counter==27) || + (validity_mask_a_cols_b_rows[27]==1'b0 && b_mem_access_counter==28) || + (validity_mask_a_cols_b_rows[28]==1'b0 && b_mem_access_counter==29) || + (validity_mask_a_cols_b_rows[29]==1'b0 && b_mem_access_counter==30) || + (validity_mask_a_cols_b_rows[30]==1'b0 && b_mem_access_counter==31) || + (validity_mask_a_cols_b_rows[31]==1'b0 && b_mem_access_counter==32)) ? + 1'b0 : (b_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM B (systolic data setup) +////////////////////////////////////////////////////////////////////////// + +// Slice data into chunks and qualify it with whether it is valid or not +assign b0_data = b_data[`DWIDTH-1:0] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[0]}}; +assign b1_data = b_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[1]}}; +assign b2_data = b_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[2]}}; +assign b3_data = b_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[3]}}; +assign b4_data = b_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[4]}}; +assign b5_data = b_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[5]}}; +assign b6_data = b_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[6]}}; +assign b7_data = b_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[7]}}; +assign b8_data = b_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[8]}}; +assign b9_data = b_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[9]}}; +assign b10_data = b_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[10]}}; +assign b11_data = b_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[11]}}; +assign b12_data = b_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[12]}}; +assign b13_data = b_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[13]}}; +assign b14_data = b_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[14]}}; +assign b15_data = b_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[15]}}; +assign b16_data = b_data[17*`DWIDTH-1:16*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[16]}}; +assign b17_data = b_data[18*`DWIDTH-1:17*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[17]}}; +assign b18_data = b_data[19*`DWIDTH-1:18*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[18]}}; +assign b19_data = b_data[20*`DWIDTH-1:19*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[19]}}; +assign b20_data = b_data[21*`DWIDTH-1:20*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[20]}}; +assign b21_data = b_data[22*`DWIDTH-1:21*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[21]}}; +assign b22_data = b_data[23*`DWIDTH-1:22*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[22]}}; +assign b23_data = b_data[24*`DWIDTH-1:23*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[23]}}; +assign b24_data = b_data[25*`DWIDTH-1:24*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[24]}}; +assign b25_data = b_data[26*`DWIDTH-1:25*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[25]}}; +assign b26_data = b_data[27*`DWIDTH-1:26*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[26]}}; +assign b27_data = b_data[28*`DWIDTH-1:27*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[27]}}; +assign b28_data = b_data[29*`DWIDTH-1:28*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[28]}}; +assign b29_data = b_data[30*`DWIDTH-1:29*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[29]}}; +assign b30_data = b_data[31*`DWIDTH-1:30*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[30]}}; +assign b31_data = b_data[32*`DWIDTH-1:31*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[31]}}; + +// For larger matmuls, more such delaying flops will be needed +reg [`DWIDTH-1:0] b1_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_1; +reg [`DWIDTH-1:0] b3_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_1; +reg [`DWIDTH-1:0] b4_data_delayed_2; +reg [`DWIDTH-1:0] b4_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_1; +reg [`DWIDTH-1:0] b5_data_delayed_2; +reg [`DWIDTH-1:0] b5_data_delayed_3; +reg [`DWIDTH-1:0] b5_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_1; +reg [`DWIDTH-1:0] b6_data_delayed_2; +reg [`DWIDTH-1:0] b6_data_delayed_3; +reg [`DWIDTH-1:0] b6_data_delayed_4; +reg [`DWIDTH-1:0] b6_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_1; +reg [`DWIDTH-1:0] b7_data_delayed_2; +reg [`DWIDTH-1:0] b7_data_delayed_3; +reg [`DWIDTH-1:0] b7_data_delayed_4; +reg [`DWIDTH-1:0] b7_data_delayed_5; +reg [`DWIDTH-1:0] b7_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_1; +reg [`DWIDTH-1:0] b8_data_delayed_2; +reg [`DWIDTH-1:0] b8_data_delayed_3; +reg [`DWIDTH-1:0] b8_data_delayed_4; +reg [`DWIDTH-1:0] b8_data_delayed_5; +reg [`DWIDTH-1:0] b8_data_delayed_6; +reg [`DWIDTH-1:0] b8_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_1; +reg [`DWIDTH-1:0] b9_data_delayed_2; +reg [`DWIDTH-1:0] b9_data_delayed_3; +reg [`DWIDTH-1:0] b9_data_delayed_4; +reg [`DWIDTH-1:0] b9_data_delayed_5; +reg [`DWIDTH-1:0] b9_data_delayed_6; +reg [`DWIDTH-1:0] b9_data_delayed_7; +reg [`DWIDTH-1:0] b9_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_1; +reg [`DWIDTH-1:0] b10_data_delayed_2; +reg [`DWIDTH-1:0] b10_data_delayed_3; +reg [`DWIDTH-1:0] b10_data_delayed_4; +reg [`DWIDTH-1:0] b10_data_delayed_5; +reg [`DWIDTH-1:0] b10_data_delayed_6; +reg [`DWIDTH-1:0] b10_data_delayed_7; +reg [`DWIDTH-1:0] b10_data_delayed_8; +reg [`DWIDTH-1:0] b10_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_1; +reg [`DWIDTH-1:0] b11_data_delayed_2; +reg [`DWIDTH-1:0] b11_data_delayed_3; +reg [`DWIDTH-1:0] b11_data_delayed_4; +reg [`DWIDTH-1:0] b11_data_delayed_5; +reg [`DWIDTH-1:0] b11_data_delayed_6; +reg [`DWIDTH-1:0] b11_data_delayed_7; +reg [`DWIDTH-1:0] b11_data_delayed_8; +reg [`DWIDTH-1:0] b11_data_delayed_9; +reg [`DWIDTH-1:0] b11_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_1; +reg [`DWIDTH-1:0] b12_data_delayed_2; +reg [`DWIDTH-1:0] b12_data_delayed_3; +reg [`DWIDTH-1:0] b12_data_delayed_4; +reg [`DWIDTH-1:0] b12_data_delayed_5; +reg [`DWIDTH-1:0] b12_data_delayed_6; +reg [`DWIDTH-1:0] b12_data_delayed_7; +reg [`DWIDTH-1:0] b12_data_delayed_8; +reg [`DWIDTH-1:0] b12_data_delayed_9; +reg [`DWIDTH-1:0] b12_data_delayed_10; +reg [`DWIDTH-1:0] b12_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_1; +reg [`DWIDTH-1:0] b13_data_delayed_2; +reg [`DWIDTH-1:0] b13_data_delayed_3; +reg [`DWIDTH-1:0] b13_data_delayed_4; +reg [`DWIDTH-1:0] b13_data_delayed_5; +reg [`DWIDTH-1:0] b13_data_delayed_6; +reg [`DWIDTH-1:0] b13_data_delayed_7; +reg [`DWIDTH-1:0] b13_data_delayed_8; +reg [`DWIDTH-1:0] b13_data_delayed_9; +reg [`DWIDTH-1:0] b13_data_delayed_10; +reg [`DWIDTH-1:0] b13_data_delayed_11; +reg [`DWIDTH-1:0] b13_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_1; +reg [`DWIDTH-1:0] b14_data_delayed_2; +reg [`DWIDTH-1:0] b14_data_delayed_3; +reg [`DWIDTH-1:0] b14_data_delayed_4; +reg [`DWIDTH-1:0] b14_data_delayed_5; +reg [`DWIDTH-1:0] b14_data_delayed_6; +reg [`DWIDTH-1:0] b14_data_delayed_7; +reg [`DWIDTH-1:0] b14_data_delayed_8; +reg [`DWIDTH-1:0] b14_data_delayed_9; +reg [`DWIDTH-1:0] b14_data_delayed_10; +reg [`DWIDTH-1:0] b14_data_delayed_11; +reg [`DWIDTH-1:0] b14_data_delayed_12; +reg [`DWIDTH-1:0] b14_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_1; +reg [`DWIDTH-1:0] b15_data_delayed_2; +reg [`DWIDTH-1:0] b15_data_delayed_3; +reg [`DWIDTH-1:0] b15_data_delayed_4; +reg [`DWIDTH-1:0] b15_data_delayed_5; +reg [`DWIDTH-1:0] b15_data_delayed_6; +reg [`DWIDTH-1:0] b15_data_delayed_7; +reg [`DWIDTH-1:0] b15_data_delayed_8; +reg [`DWIDTH-1:0] b15_data_delayed_9; +reg [`DWIDTH-1:0] b15_data_delayed_10; +reg [`DWIDTH-1:0] b15_data_delayed_11; +reg [`DWIDTH-1:0] b15_data_delayed_12; +reg [`DWIDTH-1:0] b15_data_delayed_13; +reg [`DWIDTH-1:0] b15_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_15; +reg [`DWIDTH-1:0] b16_data_delayed_1; +reg [`DWIDTH-1:0] b16_data_delayed_2; +reg [`DWIDTH-1:0] b16_data_delayed_3; +reg [`DWIDTH-1:0] b16_data_delayed_4; +reg [`DWIDTH-1:0] b16_data_delayed_5; +reg [`DWIDTH-1:0] b16_data_delayed_6; +reg [`DWIDTH-1:0] b16_data_delayed_7; +reg [`DWIDTH-1:0] b16_data_delayed_8; +reg [`DWIDTH-1:0] b16_data_delayed_9; +reg [`DWIDTH-1:0] b16_data_delayed_10; +reg [`DWIDTH-1:0] b16_data_delayed_11; +reg [`DWIDTH-1:0] b16_data_delayed_12; +reg [`DWIDTH-1:0] b16_data_delayed_13; +reg [`DWIDTH-1:0] b16_data_delayed_14; +reg [`DWIDTH-1:0] b16_data_delayed_15; +reg [`DWIDTH-1:0] b16_data_delayed_16; +reg [`DWIDTH-1:0] b17_data_delayed_1; +reg [`DWIDTH-1:0] b17_data_delayed_2; +reg [`DWIDTH-1:0] b17_data_delayed_3; +reg [`DWIDTH-1:0] b17_data_delayed_4; +reg [`DWIDTH-1:0] b17_data_delayed_5; +reg [`DWIDTH-1:0] b17_data_delayed_6; +reg [`DWIDTH-1:0] b17_data_delayed_7; +reg [`DWIDTH-1:0] b17_data_delayed_8; +reg [`DWIDTH-1:0] b17_data_delayed_9; +reg [`DWIDTH-1:0] b17_data_delayed_10; +reg [`DWIDTH-1:0] b17_data_delayed_11; +reg [`DWIDTH-1:0] b17_data_delayed_12; +reg [`DWIDTH-1:0] b17_data_delayed_13; +reg [`DWIDTH-1:0] b17_data_delayed_14; +reg [`DWIDTH-1:0] b17_data_delayed_15; +reg [`DWIDTH-1:0] b17_data_delayed_16; +reg [`DWIDTH-1:0] b17_data_delayed_17; +reg [`DWIDTH-1:0] b18_data_delayed_1; +reg [`DWIDTH-1:0] b18_data_delayed_2; +reg [`DWIDTH-1:0] b18_data_delayed_3; +reg [`DWIDTH-1:0] b18_data_delayed_4; +reg [`DWIDTH-1:0] b18_data_delayed_5; +reg [`DWIDTH-1:0] b18_data_delayed_6; +reg [`DWIDTH-1:0] b18_data_delayed_7; +reg [`DWIDTH-1:0] b18_data_delayed_8; +reg [`DWIDTH-1:0] b18_data_delayed_9; +reg [`DWIDTH-1:0] b18_data_delayed_10; +reg [`DWIDTH-1:0] b18_data_delayed_11; +reg [`DWIDTH-1:0] b18_data_delayed_12; +reg [`DWIDTH-1:0] b18_data_delayed_13; +reg [`DWIDTH-1:0] b18_data_delayed_14; +reg [`DWIDTH-1:0] b18_data_delayed_15; +reg [`DWIDTH-1:0] b18_data_delayed_16; +reg [`DWIDTH-1:0] b18_data_delayed_17; +reg [`DWIDTH-1:0] b18_data_delayed_18; +reg [`DWIDTH-1:0] b19_data_delayed_1; +reg [`DWIDTH-1:0] b19_data_delayed_2; +reg [`DWIDTH-1:0] b19_data_delayed_3; +reg [`DWIDTH-1:0] b19_data_delayed_4; +reg [`DWIDTH-1:0] b19_data_delayed_5; +reg [`DWIDTH-1:0] b19_data_delayed_6; +reg [`DWIDTH-1:0] b19_data_delayed_7; +reg [`DWIDTH-1:0] b19_data_delayed_8; +reg [`DWIDTH-1:0] b19_data_delayed_9; +reg [`DWIDTH-1:0] b19_data_delayed_10; +reg [`DWIDTH-1:0] b19_data_delayed_11; +reg [`DWIDTH-1:0] b19_data_delayed_12; +reg [`DWIDTH-1:0] b19_data_delayed_13; +reg [`DWIDTH-1:0] b19_data_delayed_14; +reg [`DWIDTH-1:0] b19_data_delayed_15; +reg [`DWIDTH-1:0] b19_data_delayed_16; +reg [`DWIDTH-1:0] b19_data_delayed_17; +reg [`DWIDTH-1:0] b19_data_delayed_18; +reg [`DWIDTH-1:0] b19_data_delayed_19; +reg [`DWIDTH-1:0] b20_data_delayed_1; +reg [`DWIDTH-1:0] b20_data_delayed_2; +reg [`DWIDTH-1:0] b20_data_delayed_3; +reg [`DWIDTH-1:0] b20_data_delayed_4; +reg [`DWIDTH-1:0] b20_data_delayed_5; +reg [`DWIDTH-1:0] b20_data_delayed_6; +reg [`DWIDTH-1:0] b20_data_delayed_7; +reg [`DWIDTH-1:0] b20_data_delayed_8; +reg [`DWIDTH-1:0] b20_data_delayed_9; +reg [`DWIDTH-1:0] b20_data_delayed_10; +reg [`DWIDTH-1:0] b20_data_delayed_11; +reg [`DWIDTH-1:0] b20_data_delayed_12; +reg [`DWIDTH-1:0] b20_data_delayed_13; +reg [`DWIDTH-1:0] b20_data_delayed_14; +reg [`DWIDTH-1:0] b20_data_delayed_15; +reg [`DWIDTH-1:0] b20_data_delayed_16; +reg [`DWIDTH-1:0] b20_data_delayed_17; +reg [`DWIDTH-1:0] b20_data_delayed_18; +reg [`DWIDTH-1:0] b20_data_delayed_19; +reg [`DWIDTH-1:0] b20_data_delayed_20; +reg [`DWIDTH-1:0] b21_data_delayed_1; +reg [`DWIDTH-1:0] b21_data_delayed_2; +reg [`DWIDTH-1:0] b21_data_delayed_3; +reg [`DWIDTH-1:0] b21_data_delayed_4; +reg [`DWIDTH-1:0] b21_data_delayed_5; +reg [`DWIDTH-1:0] b21_data_delayed_6; +reg [`DWIDTH-1:0] b21_data_delayed_7; +reg [`DWIDTH-1:0] b21_data_delayed_8; +reg [`DWIDTH-1:0] b21_data_delayed_9; +reg [`DWIDTH-1:0] b21_data_delayed_10; +reg [`DWIDTH-1:0] b21_data_delayed_11; +reg [`DWIDTH-1:0] b21_data_delayed_12; +reg [`DWIDTH-1:0] b21_data_delayed_13; +reg [`DWIDTH-1:0] b21_data_delayed_14; +reg [`DWIDTH-1:0] b21_data_delayed_15; +reg [`DWIDTH-1:0] b21_data_delayed_16; +reg [`DWIDTH-1:0] b21_data_delayed_17; +reg [`DWIDTH-1:0] b21_data_delayed_18; +reg [`DWIDTH-1:0] b21_data_delayed_19; +reg [`DWIDTH-1:0] b21_data_delayed_20; +reg [`DWIDTH-1:0] b21_data_delayed_21; +reg [`DWIDTH-1:0] b22_data_delayed_1; +reg [`DWIDTH-1:0] b22_data_delayed_2; +reg [`DWIDTH-1:0] b22_data_delayed_3; +reg [`DWIDTH-1:0] b22_data_delayed_4; +reg [`DWIDTH-1:0] b22_data_delayed_5; +reg [`DWIDTH-1:0] b22_data_delayed_6; +reg [`DWIDTH-1:0] b22_data_delayed_7; +reg [`DWIDTH-1:0] b22_data_delayed_8; +reg [`DWIDTH-1:0] b22_data_delayed_9; +reg [`DWIDTH-1:0] b22_data_delayed_10; +reg [`DWIDTH-1:0] b22_data_delayed_11; +reg [`DWIDTH-1:0] b22_data_delayed_12; +reg [`DWIDTH-1:0] b22_data_delayed_13; +reg [`DWIDTH-1:0] b22_data_delayed_14; +reg [`DWIDTH-1:0] b22_data_delayed_15; +reg [`DWIDTH-1:0] b22_data_delayed_16; +reg [`DWIDTH-1:0] b22_data_delayed_17; +reg [`DWIDTH-1:0] b22_data_delayed_18; +reg [`DWIDTH-1:0] b22_data_delayed_19; +reg [`DWIDTH-1:0] b22_data_delayed_20; +reg [`DWIDTH-1:0] b22_data_delayed_21; +reg [`DWIDTH-1:0] b22_data_delayed_22; +reg [`DWIDTH-1:0] b23_data_delayed_1; +reg [`DWIDTH-1:0] b23_data_delayed_2; +reg [`DWIDTH-1:0] b23_data_delayed_3; +reg [`DWIDTH-1:0] b23_data_delayed_4; +reg [`DWIDTH-1:0] b23_data_delayed_5; +reg [`DWIDTH-1:0] b23_data_delayed_6; +reg [`DWIDTH-1:0] b23_data_delayed_7; +reg [`DWIDTH-1:0] b23_data_delayed_8; +reg [`DWIDTH-1:0] b23_data_delayed_9; +reg [`DWIDTH-1:0] b23_data_delayed_10; +reg [`DWIDTH-1:0] b23_data_delayed_11; +reg [`DWIDTH-1:0] b23_data_delayed_12; +reg [`DWIDTH-1:0] b23_data_delayed_13; +reg [`DWIDTH-1:0] b23_data_delayed_14; +reg [`DWIDTH-1:0] b23_data_delayed_15; +reg [`DWIDTH-1:0] b23_data_delayed_16; +reg [`DWIDTH-1:0] b23_data_delayed_17; +reg [`DWIDTH-1:0] b23_data_delayed_18; +reg [`DWIDTH-1:0] b23_data_delayed_19; +reg [`DWIDTH-1:0] b23_data_delayed_20; +reg [`DWIDTH-1:0] b23_data_delayed_21; +reg [`DWIDTH-1:0] b23_data_delayed_22; +reg [`DWIDTH-1:0] b23_data_delayed_23; +reg [`DWIDTH-1:0] b24_data_delayed_1; +reg [`DWIDTH-1:0] b24_data_delayed_2; +reg [`DWIDTH-1:0] b24_data_delayed_3; +reg [`DWIDTH-1:0] b24_data_delayed_4; +reg [`DWIDTH-1:0] b24_data_delayed_5; +reg [`DWIDTH-1:0] b24_data_delayed_6; +reg [`DWIDTH-1:0] b24_data_delayed_7; +reg [`DWIDTH-1:0] b24_data_delayed_8; +reg [`DWIDTH-1:0] b24_data_delayed_9; +reg [`DWIDTH-1:0] b24_data_delayed_10; +reg [`DWIDTH-1:0] b24_data_delayed_11; +reg [`DWIDTH-1:0] b24_data_delayed_12; +reg [`DWIDTH-1:0] b24_data_delayed_13; +reg [`DWIDTH-1:0] b24_data_delayed_14; +reg [`DWIDTH-1:0] b24_data_delayed_15; +reg [`DWIDTH-1:0] b24_data_delayed_16; +reg [`DWIDTH-1:0] b24_data_delayed_17; +reg [`DWIDTH-1:0] b24_data_delayed_18; +reg [`DWIDTH-1:0] b24_data_delayed_19; +reg [`DWIDTH-1:0] b24_data_delayed_20; +reg [`DWIDTH-1:0] b24_data_delayed_21; +reg [`DWIDTH-1:0] b24_data_delayed_22; +reg [`DWIDTH-1:0] b24_data_delayed_23; +reg [`DWIDTH-1:0] b24_data_delayed_24; +reg [`DWIDTH-1:0] b25_data_delayed_1; +reg [`DWIDTH-1:0] b25_data_delayed_2; +reg [`DWIDTH-1:0] b25_data_delayed_3; +reg [`DWIDTH-1:0] b25_data_delayed_4; +reg [`DWIDTH-1:0] b25_data_delayed_5; +reg [`DWIDTH-1:0] b25_data_delayed_6; +reg [`DWIDTH-1:0] b25_data_delayed_7; +reg [`DWIDTH-1:0] b25_data_delayed_8; +reg [`DWIDTH-1:0] b25_data_delayed_9; +reg [`DWIDTH-1:0] b25_data_delayed_10; +reg [`DWIDTH-1:0] b25_data_delayed_11; +reg [`DWIDTH-1:0] b25_data_delayed_12; +reg [`DWIDTH-1:0] b25_data_delayed_13; +reg [`DWIDTH-1:0] b25_data_delayed_14; +reg [`DWIDTH-1:0] b25_data_delayed_15; +reg [`DWIDTH-1:0] b25_data_delayed_16; +reg [`DWIDTH-1:0] b25_data_delayed_17; +reg [`DWIDTH-1:0] b25_data_delayed_18; +reg [`DWIDTH-1:0] b25_data_delayed_19; +reg [`DWIDTH-1:0] b25_data_delayed_20; +reg [`DWIDTH-1:0] b25_data_delayed_21; +reg [`DWIDTH-1:0] b25_data_delayed_22; +reg [`DWIDTH-1:0] b25_data_delayed_23; +reg [`DWIDTH-1:0] b25_data_delayed_24; +reg [`DWIDTH-1:0] b25_data_delayed_25; +reg [`DWIDTH-1:0] b26_data_delayed_1; +reg [`DWIDTH-1:0] b26_data_delayed_2; +reg [`DWIDTH-1:0] b26_data_delayed_3; +reg [`DWIDTH-1:0] b26_data_delayed_4; +reg [`DWIDTH-1:0] b26_data_delayed_5; +reg [`DWIDTH-1:0] b26_data_delayed_6; +reg [`DWIDTH-1:0] b26_data_delayed_7; +reg [`DWIDTH-1:0] b26_data_delayed_8; +reg [`DWIDTH-1:0] b26_data_delayed_9; +reg [`DWIDTH-1:0] b26_data_delayed_10; +reg [`DWIDTH-1:0] b26_data_delayed_11; +reg [`DWIDTH-1:0] b26_data_delayed_12; +reg [`DWIDTH-1:0] b26_data_delayed_13; +reg [`DWIDTH-1:0] b26_data_delayed_14; +reg [`DWIDTH-1:0] b26_data_delayed_15; +reg [`DWIDTH-1:0] b26_data_delayed_16; +reg [`DWIDTH-1:0] b26_data_delayed_17; +reg [`DWIDTH-1:0] b26_data_delayed_18; +reg [`DWIDTH-1:0] b26_data_delayed_19; +reg [`DWIDTH-1:0] b26_data_delayed_20; +reg [`DWIDTH-1:0] b26_data_delayed_21; +reg [`DWIDTH-1:0] b26_data_delayed_22; +reg [`DWIDTH-1:0] b26_data_delayed_23; +reg [`DWIDTH-1:0] b26_data_delayed_24; +reg [`DWIDTH-1:0] b26_data_delayed_25; +reg [`DWIDTH-1:0] b26_data_delayed_26; +reg [`DWIDTH-1:0] b27_data_delayed_1; +reg [`DWIDTH-1:0] b27_data_delayed_2; +reg [`DWIDTH-1:0] b27_data_delayed_3; +reg [`DWIDTH-1:0] b27_data_delayed_4; +reg [`DWIDTH-1:0] b27_data_delayed_5; +reg [`DWIDTH-1:0] b27_data_delayed_6; +reg [`DWIDTH-1:0] b27_data_delayed_7; +reg [`DWIDTH-1:0] b27_data_delayed_8; +reg [`DWIDTH-1:0] b27_data_delayed_9; +reg [`DWIDTH-1:0] b27_data_delayed_10; +reg [`DWIDTH-1:0] b27_data_delayed_11; +reg [`DWIDTH-1:0] b27_data_delayed_12; +reg [`DWIDTH-1:0] b27_data_delayed_13; +reg [`DWIDTH-1:0] b27_data_delayed_14; +reg [`DWIDTH-1:0] b27_data_delayed_15; +reg [`DWIDTH-1:0] b27_data_delayed_16; +reg [`DWIDTH-1:0] b27_data_delayed_17; +reg [`DWIDTH-1:0] b27_data_delayed_18; +reg [`DWIDTH-1:0] b27_data_delayed_19; +reg [`DWIDTH-1:0] b27_data_delayed_20; +reg [`DWIDTH-1:0] b27_data_delayed_21; +reg [`DWIDTH-1:0] b27_data_delayed_22; +reg [`DWIDTH-1:0] b27_data_delayed_23; +reg [`DWIDTH-1:0] b27_data_delayed_24; +reg [`DWIDTH-1:0] b27_data_delayed_25; +reg [`DWIDTH-1:0] b27_data_delayed_26; +reg [`DWIDTH-1:0] b27_data_delayed_27; +reg [`DWIDTH-1:0] b28_data_delayed_1; +reg [`DWIDTH-1:0] b28_data_delayed_2; +reg [`DWIDTH-1:0] b28_data_delayed_3; +reg [`DWIDTH-1:0] b28_data_delayed_4; +reg [`DWIDTH-1:0] b28_data_delayed_5; +reg [`DWIDTH-1:0] b28_data_delayed_6; +reg [`DWIDTH-1:0] b28_data_delayed_7; +reg [`DWIDTH-1:0] b28_data_delayed_8; +reg [`DWIDTH-1:0] b28_data_delayed_9; +reg [`DWIDTH-1:0] b28_data_delayed_10; +reg [`DWIDTH-1:0] b28_data_delayed_11; +reg [`DWIDTH-1:0] b28_data_delayed_12; +reg [`DWIDTH-1:0] b28_data_delayed_13; +reg [`DWIDTH-1:0] b28_data_delayed_14; +reg [`DWIDTH-1:0] b28_data_delayed_15; +reg [`DWIDTH-1:0] b28_data_delayed_16; +reg [`DWIDTH-1:0] b28_data_delayed_17; +reg [`DWIDTH-1:0] b28_data_delayed_18; +reg [`DWIDTH-1:0] b28_data_delayed_19; +reg [`DWIDTH-1:0] b28_data_delayed_20; +reg [`DWIDTH-1:0] b28_data_delayed_21; +reg [`DWIDTH-1:0] b28_data_delayed_22; +reg [`DWIDTH-1:0] b28_data_delayed_23; +reg [`DWIDTH-1:0] b28_data_delayed_24; +reg [`DWIDTH-1:0] b28_data_delayed_25; +reg [`DWIDTH-1:0] b28_data_delayed_26; +reg [`DWIDTH-1:0] b28_data_delayed_27; +reg [`DWIDTH-1:0] b28_data_delayed_28; +reg [`DWIDTH-1:0] b29_data_delayed_1; +reg [`DWIDTH-1:0] b29_data_delayed_2; +reg [`DWIDTH-1:0] b29_data_delayed_3; +reg [`DWIDTH-1:0] b29_data_delayed_4; +reg [`DWIDTH-1:0] b29_data_delayed_5; +reg [`DWIDTH-1:0] b29_data_delayed_6; +reg [`DWIDTH-1:0] b29_data_delayed_7; +reg [`DWIDTH-1:0] b29_data_delayed_8; +reg [`DWIDTH-1:0] b29_data_delayed_9; +reg [`DWIDTH-1:0] b29_data_delayed_10; +reg [`DWIDTH-1:0] b29_data_delayed_11; +reg [`DWIDTH-1:0] b29_data_delayed_12; +reg [`DWIDTH-1:0] b29_data_delayed_13; +reg [`DWIDTH-1:0] b29_data_delayed_14; +reg [`DWIDTH-1:0] b29_data_delayed_15; +reg [`DWIDTH-1:0] b29_data_delayed_16; +reg [`DWIDTH-1:0] b29_data_delayed_17; +reg [`DWIDTH-1:0] b29_data_delayed_18; +reg [`DWIDTH-1:0] b29_data_delayed_19; +reg [`DWIDTH-1:0] b29_data_delayed_20; +reg [`DWIDTH-1:0] b29_data_delayed_21; +reg [`DWIDTH-1:0] b29_data_delayed_22; +reg [`DWIDTH-1:0] b29_data_delayed_23; +reg [`DWIDTH-1:0] b29_data_delayed_24; +reg [`DWIDTH-1:0] b29_data_delayed_25; +reg [`DWIDTH-1:0] b29_data_delayed_26; +reg [`DWIDTH-1:0] b29_data_delayed_27; +reg [`DWIDTH-1:0] b29_data_delayed_28; +reg [`DWIDTH-1:0] b29_data_delayed_29; +reg [`DWIDTH-1:0] b30_data_delayed_1; +reg [`DWIDTH-1:0] b30_data_delayed_2; +reg [`DWIDTH-1:0] b30_data_delayed_3; +reg [`DWIDTH-1:0] b30_data_delayed_4; +reg [`DWIDTH-1:0] b30_data_delayed_5; +reg [`DWIDTH-1:0] b30_data_delayed_6; +reg [`DWIDTH-1:0] b30_data_delayed_7; +reg [`DWIDTH-1:0] b30_data_delayed_8; +reg [`DWIDTH-1:0] b30_data_delayed_9; +reg [`DWIDTH-1:0] b30_data_delayed_10; +reg [`DWIDTH-1:0] b30_data_delayed_11; +reg [`DWIDTH-1:0] b30_data_delayed_12; +reg [`DWIDTH-1:0] b30_data_delayed_13; +reg [`DWIDTH-1:0] b30_data_delayed_14; +reg [`DWIDTH-1:0] b30_data_delayed_15; +reg [`DWIDTH-1:0] b30_data_delayed_16; +reg [`DWIDTH-1:0] b30_data_delayed_17; +reg [`DWIDTH-1:0] b30_data_delayed_18; +reg [`DWIDTH-1:0] b30_data_delayed_19; +reg [`DWIDTH-1:0] b30_data_delayed_20; +reg [`DWIDTH-1:0] b30_data_delayed_21; +reg [`DWIDTH-1:0] b30_data_delayed_22; +reg [`DWIDTH-1:0] b30_data_delayed_23; +reg [`DWIDTH-1:0] b30_data_delayed_24; +reg [`DWIDTH-1:0] b30_data_delayed_25; +reg [`DWIDTH-1:0] b30_data_delayed_26; +reg [`DWIDTH-1:0] b30_data_delayed_27; +reg [`DWIDTH-1:0] b30_data_delayed_28; +reg [`DWIDTH-1:0] b30_data_delayed_29; +reg [`DWIDTH-1:0] b30_data_delayed_30; +reg [`DWIDTH-1:0] b31_data_delayed_1; +reg [`DWIDTH-1:0] b31_data_delayed_2; +reg [`DWIDTH-1:0] b31_data_delayed_3; +reg [`DWIDTH-1:0] b31_data_delayed_4; +reg [`DWIDTH-1:0] b31_data_delayed_5; +reg [`DWIDTH-1:0] b31_data_delayed_6; +reg [`DWIDTH-1:0] b31_data_delayed_7; +reg [`DWIDTH-1:0] b31_data_delayed_8; +reg [`DWIDTH-1:0] b31_data_delayed_9; +reg [`DWIDTH-1:0] b31_data_delayed_10; +reg [`DWIDTH-1:0] b31_data_delayed_11; +reg [`DWIDTH-1:0] b31_data_delayed_12; +reg [`DWIDTH-1:0] b31_data_delayed_13; +reg [`DWIDTH-1:0] b31_data_delayed_14; +reg [`DWIDTH-1:0] b31_data_delayed_15; +reg [`DWIDTH-1:0] b31_data_delayed_16; +reg [`DWIDTH-1:0] b31_data_delayed_17; +reg [`DWIDTH-1:0] b31_data_delayed_18; +reg [`DWIDTH-1:0] b31_data_delayed_19; +reg [`DWIDTH-1:0] b31_data_delayed_20; +reg [`DWIDTH-1:0] b31_data_delayed_21; +reg [`DWIDTH-1:0] b31_data_delayed_22; +reg [`DWIDTH-1:0] b31_data_delayed_23; +reg [`DWIDTH-1:0] b31_data_delayed_24; +reg [`DWIDTH-1:0] b31_data_delayed_25; +reg [`DWIDTH-1:0] b31_data_delayed_26; +reg [`DWIDTH-1:0] b31_data_delayed_27; +reg [`DWIDTH-1:0] b31_data_delayed_28; +reg [`DWIDTH-1:0] b31_data_delayed_29; +reg [`DWIDTH-1:0] b31_data_delayed_30; +reg [`DWIDTH-1:0] b31_data_delayed_31; + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + b1_data_delayed_1 <= 0; + b2_data_delayed_1 <= 0; + b2_data_delayed_2 <= 0; + b3_data_delayed_1 <= 0; + b3_data_delayed_2 <= 0; + b3_data_delayed_3 <= 0; + b4_data_delayed_1 <= 0; + b4_data_delayed_2 <= 0; + b4_data_delayed_3 <= 0; + b4_data_delayed_4 <= 0; + b5_data_delayed_1 <= 0; + b5_data_delayed_2 <= 0; + b5_data_delayed_3 <= 0; + b5_data_delayed_4 <= 0; + b5_data_delayed_5 <= 0; + b6_data_delayed_1 <= 0; + b6_data_delayed_2 <= 0; + b6_data_delayed_3 <= 0; + b6_data_delayed_4 <= 0; + b6_data_delayed_5 <= 0; + b6_data_delayed_6 <= 0; + b7_data_delayed_1 <= 0; + b7_data_delayed_2 <= 0; + b7_data_delayed_3 <= 0; + b7_data_delayed_4 <= 0; + b7_data_delayed_5 <= 0; + b7_data_delayed_6 <= 0; + b7_data_delayed_7 <= 0; + b8_data_delayed_1 <= 0; + b8_data_delayed_2 <= 0; + b8_data_delayed_3 <= 0; + b8_data_delayed_4 <= 0; + b8_data_delayed_5 <= 0; + b8_data_delayed_6 <= 0; + b8_data_delayed_7 <= 0; + b8_data_delayed_8 <= 0; + b9_data_delayed_1 <= 0; + b9_data_delayed_2 <= 0; + b9_data_delayed_3 <= 0; + b9_data_delayed_4 <= 0; + b9_data_delayed_5 <= 0; + b9_data_delayed_6 <= 0; + b9_data_delayed_7 <= 0; + b9_data_delayed_8 <= 0; + b9_data_delayed_9 <= 0; + b10_data_delayed_1 <= 0; + b10_data_delayed_2 <= 0; + b10_data_delayed_3 <= 0; + b10_data_delayed_4 <= 0; + b10_data_delayed_5 <= 0; + b10_data_delayed_6 <= 0; + b10_data_delayed_7 <= 0; + b10_data_delayed_8 <= 0; + b10_data_delayed_9 <= 0; + b10_data_delayed_10 <= 0; + b11_data_delayed_1 <= 0; + b11_data_delayed_2 <= 0; + b11_data_delayed_3 <= 0; + b11_data_delayed_4 <= 0; + b11_data_delayed_5 <= 0; + b11_data_delayed_6 <= 0; + b11_data_delayed_7 <= 0; + b11_data_delayed_8 <= 0; + b11_data_delayed_9 <= 0; + b11_data_delayed_10 <= 0; + b11_data_delayed_11 <= 0; + b12_data_delayed_1 <= 0; + b12_data_delayed_2 <= 0; + b12_data_delayed_3 <= 0; + b12_data_delayed_4 <= 0; + b12_data_delayed_5 <= 0; + b12_data_delayed_6 <= 0; + b12_data_delayed_7 <= 0; + b12_data_delayed_8 <= 0; + b12_data_delayed_9 <= 0; + b12_data_delayed_10 <= 0; + b12_data_delayed_11 <= 0; + b12_data_delayed_12 <= 0; + b13_data_delayed_1 <= 0; + b13_data_delayed_2 <= 0; + b13_data_delayed_3 <= 0; + b13_data_delayed_4 <= 0; + b13_data_delayed_5 <= 0; + b13_data_delayed_6 <= 0; + b13_data_delayed_7 <= 0; + b13_data_delayed_8 <= 0; + b13_data_delayed_9 <= 0; + b13_data_delayed_10 <= 0; + b13_data_delayed_11 <= 0; + b13_data_delayed_12 <= 0; + b13_data_delayed_13 <= 0; + b14_data_delayed_1 <= 0; + b14_data_delayed_2 <= 0; + b14_data_delayed_3 <= 0; + b14_data_delayed_4 <= 0; + b14_data_delayed_5 <= 0; + b14_data_delayed_6 <= 0; + b14_data_delayed_7 <= 0; + b14_data_delayed_8 <= 0; + b14_data_delayed_9 <= 0; + b14_data_delayed_10 <= 0; + b14_data_delayed_11 <= 0; + b14_data_delayed_12 <= 0; + b14_data_delayed_13 <= 0; + b14_data_delayed_14 <= 0; + b15_data_delayed_1 <= 0; + b15_data_delayed_2 <= 0; + b15_data_delayed_3 <= 0; + b15_data_delayed_4 <= 0; + b15_data_delayed_5 <= 0; + b15_data_delayed_6 <= 0; + b15_data_delayed_7 <= 0; + b15_data_delayed_8 <= 0; + b15_data_delayed_9 <= 0; + b15_data_delayed_10 <= 0; + b15_data_delayed_11 <= 0; + b15_data_delayed_12 <= 0; + b15_data_delayed_13 <= 0; + b15_data_delayed_14 <= 0; + b15_data_delayed_15 <= 0; + b16_data_delayed_1 <= 0; + b16_data_delayed_2 <= 0; + b16_data_delayed_3 <= 0; + b16_data_delayed_4 <= 0; + b16_data_delayed_5 <= 0; + b16_data_delayed_6 <= 0; + b16_data_delayed_7 <= 0; + b16_data_delayed_8 <= 0; + b16_data_delayed_9 <= 0; + b16_data_delayed_10 <= 0; + b16_data_delayed_11 <= 0; + b16_data_delayed_12 <= 0; + b16_data_delayed_13 <= 0; + b16_data_delayed_14 <= 0; + b16_data_delayed_15 <= 0; + b16_data_delayed_16 <= 0; + b17_data_delayed_1 <= 0; + b17_data_delayed_2 <= 0; + b17_data_delayed_3 <= 0; + b17_data_delayed_4 <= 0; + b17_data_delayed_5 <= 0; + b17_data_delayed_6 <= 0; + b17_data_delayed_7 <= 0; + b17_data_delayed_8 <= 0; + b17_data_delayed_9 <= 0; + b17_data_delayed_10 <= 0; + b17_data_delayed_11 <= 0; + b17_data_delayed_12 <= 0; + b17_data_delayed_13 <= 0; + b17_data_delayed_14 <= 0; + b17_data_delayed_15 <= 0; + b17_data_delayed_16 <= 0; + b17_data_delayed_17 <= 0; + b18_data_delayed_1 <= 0; + b18_data_delayed_2 <= 0; + b18_data_delayed_3 <= 0; + b18_data_delayed_4 <= 0; + b18_data_delayed_5 <= 0; + b18_data_delayed_6 <= 0; + b18_data_delayed_7 <= 0; + b18_data_delayed_8 <= 0; + b18_data_delayed_9 <= 0; + b18_data_delayed_10 <= 0; + b18_data_delayed_11 <= 0; + b18_data_delayed_12 <= 0; + b18_data_delayed_13 <= 0; + b18_data_delayed_14 <= 0; + b18_data_delayed_15 <= 0; + b18_data_delayed_16 <= 0; + b18_data_delayed_17 <= 0; + b18_data_delayed_18 <= 0; + b19_data_delayed_1 <= 0; + b19_data_delayed_2 <= 0; + b19_data_delayed_3 <= 0; + b19_data_delayed_4 <= 0; + b19_data_delayed_5 <= 0; + b19_data_delayed_6 <= 0; + b19_data_delayed_7 <= 0; + b19_data_delayed_8 <= 0; + b19_data_delayed_9 <= 0; + b19_data_delayed_10 <= 0; + b19_data_delayed_11 <= 0; + b19_data_delayed_12 <= 0; + b19_data_delayed_13 <= 0; + b19_data_delayed_14 <= 0; + b19_data_delayed_15 <= 0; + b19_data_delayed_16 <= 0; + b19_data_delayed_17 <= 0; + b19_data_delayed_18 <= 0; + b19_data_delayed_19 <= 0; + b20_data_delayed_1 <= 0; + b20_data_delayed_2 <= 0; + b20_data_delayed_3 <= 0; + b20_data_delayed_4 <= 0; + b20_data_delayed_5 <= 0; + b20_data_delayed_6 <= 0; + b20_data_delayed_7 <= 0; + b20_data_delayed_8 <= 0; + b20_data_delayed_9 <= 0; + b20_data_delayed_10 <= 0; + b20_data_delayed_11 <= 0; + b20_data_delayed_12 <= 0; + b20_data_delayed_13 <= 0; + b20_data_delayed_14 <= 0; + b20_data_delayed_15 <= 0; + b20_data_delayed_16 <= 0; + b20_data_delayed_17 <= 0; + b20_data_delayed_18 <= 0; + b20_data_delayed_19 <= 0; + b20_data_delayed_20 <= 0; + b21_data_delayed_1 <= 0; + b21_data_delayed_2 <= 0; + b21_data_delayed_3 <= 0; + b21_data_delayed_4 <= 0; + b21_data_delayed_5 <= 0; + b21_data_delayed_6 <= 0; + b21_data_delayed_7 <= 0; + b21_data_delayed_8 <= 0; + b21_data_delayed_9 <= 0; + b21_data_delayed_10 <= 0; + b21_data_delayed_11 <= 0; + b21_data_delayed_12 <= 0; + b21_data_delayed_13 <= 0; + b21_data_delayed_14 <= 0; + b21_data_delayed_15 <= 0; + b21_data_delayed_16 <= 0; + b21_data_delayed_17 <= 0; + b21_data_delayed_18 <= 0; + b21_data_delayed_19 <= 0; + b21_data_delayed_20 <= 0; + b21_data_delayed_21 <= 0; + b22_data_delayed_1 <= 0; + b22_data_delayed_2 <= 0; + b22_data_delayed_3 <= 0; + b22_data_delayed_4 <= 0; + b22_data_delayed_5 <= 0; + b22_data_delayed_6 <= 0; + b22_data_delayed_7 <= 0; + b22_data_delayed_8 <= 0; + b22_data_delayed_9 <= 0; + b22_data_delayed_10 <= 0; + b22_data_delayed_11 <= 0; + b22_data_delayed_12 <= 0; + b22_data_delayed_13 <= 0; + b22_data_delayed_14 <= 0; + b22_data_delayed_15 <= 0; + b22_data_delayed_16 <= 0; + b22_data_delayed_17 <= 0; + b22_data_delayed_18 <= 0; + b22_data_delayed_19 <= 0; + b22_data_delayed_20 <= 0; + b22_data_delayed_21 <= 0; + b22_data_delayed_22 <= 0; + b23_data_delayed_1 <= 0; + b23_data_delayed_2 <= 0; + b23_data_delayed_3 <= 0; + b23_data_delayed_4 <= 0; + b23_data_delayed_5 <= 0; + b23_data_delayed_6 <= 0; + b23_data_delayed_7 <= 0; + b23_data_delayed_8 <= 0; + b23_data_delayed_9 <= 0; + b23_data_delayed_10 <= 0; + b23_data_delayed_11 <= 0; + b23_data_delayed_12 <= 0; + b23_data_delayed_13 <= 0; + b23_data_delayed_14 <= 0; + b23_data_delayed_15 <= 0; + b23_data_delayed_16 <= 0; + b23_data_delayed_17 <= 0; + b23_data_delayed_18 <= 0; + b23_data_delayed_19 <= 0; + b23_data_delayed_20 <= 0; + b23_data_delayed_21 <= 0; + b23_data_delayed_22 <= 0; + b23_data_delayed_23 <= 0; + b24_data_delayed_1 <= 0; + b24_data_delayed_2 <= 0; + b24_data_delayed_3 <= 0; + b24_data_delayed_4 <= 0; + b24_data_delayed_5 <= 0; + b24_data_delayed_6 <= 0; + b24_data_delayed_7 <= 0; + b24_data_delayed_8 <= 0; + b24_data_delayed_9 <= 0; + b24_data_delayed_10 <= 0; + b24_data_delayed_11 <= 0; + b24_data_delayed_12 <= 0; + b24_data_delayed_13 <= 0; + b24_data_delayed_14 <= 0; + b24_data_delayed_15 <= 0; + b24_data_delayed_16 <= 0; + b24_data_delayed_17 <= 0; + b24_data_delayed_18 <= 0; + b24_data_delayed_19 <= 0; + b24_data_delayed_20 <= 0; + b24_data_delayed_21 <= 0; + b24_data_delayed_22 <= 0; + b24_data_delayed_23 <= 0; + b24_data_delayed_24 <= 0; + b25_data_delayed_1 <= 0; + b25_data_delayed_2 <= 0; + b25_data_delayed_3 <= 0; + b25_data_delayed_4 <= 0; + b25_data_delayed_5 <= 0; + b25_data_delayed_6 <= 0; + b25_data_delayed_7 <= 0; + b25_data_delayed_8 <= 0; + b25_data_delayed_9 <= 0; + b25_data_delayed_10 <= 0; + b25_data_delayed_11 <= 0; + b25_data_delayed_12 <= 0; + b25_data_delayed_13 <= 0; + b25_data_delayed_14 <= 0; + b25_data_delayed_15 <= 0; + b25_data_delayed_16 <= 0; + b25_data_delayed_17 <= 0; + b25_data_delayed_18 <= 0; + b25_data_delayed_19 <= 0; + b25_data_delayed_20 <= 0; + b25_data_delayed_21 <= 0; + b25_data_delayed_22 <= 0; + b25_data_delayed_23 <= 0; + b25_data_delayed_24 <= 0; + b25_data_delayed_25 <= 0; + b26_data_delayed_1 <= 0; + b26_data_delayed_2 <= 0; + b26_data_delayed_3 <= 0; + b26_data_delayed_4 <= 0; + b26_data_delayed_5 <= 0; + b26_data_delayed_6 <= 0; + b26_data_delayed_7 <= 0; + b26_data_delayed_8 <= 0; + b26_data_delayed_9 <= 0; + b26_data_delayed_10 <= 0; + b26_data_delayed_11 <= 0; + b26_data_delayed_12 <= 0; + b26_data_delayed_13 <= 0; + b26_data_delayed_14 <= 0; + b26_data_delayed_15 <= 0; + b26_data_delayed_16 <= 0; + b26_data_delayed_17 <= 0; + b26_data_delayed_18 <= 0; + b26_data_delayed_19 <= 0; + b26_data_delayed_20 <= 0; + b26_data_delayed_21 <= 0; + b26_data_delayed_22 <= 0; + b26_data_delayed_23 <= 0; + b26_data_delayed_24 <= 0; + b26_data_delayed_25 <= 0; + b26_data_delayed_26 <= 0; + b27_data_delayed_1 <= 0; + b27_data_delayed_2 <= 0; + b27_data_delayed_3 <= 0; + b27_data_delayed_4 <= 0; + b27_data_delayed_5 <= 0; + b27_data_delayed_6 <= 0; + b27_data_delayed_7 <= 0; + b27_data_delayed_8 <= 0; + b27_data_delayed_9 <= 0; + b27_data_delayed_10 <= 0; + b27_data_delayed_11 <= 0; + b27_data_delayed_12 <= 0; + b27_data_delayed_13 <= 0; + b27_data_delayed_14 <= 0; + b27_data_delayed_15 <= 0; + b27_data_delayed_16 <= 0; + b27_data_delayed_17 <= 0; + b27_data_delayed_18 <= 0; + b27_data_delayed_19 <= 0; + b27_data_delayed_20 <= 0; + b27_data_delayed_21 <= 0; + b27_data_delayed_22 <= 0; + b27_data_delayed_23 <= 0; + b27_data_delayed_24 <= 0; + b27_data_delayed_25 <= 0; + b27_data_delayed_26 <= 0; + b27_data_delayed_27 <= 0; + b28_data_delayed_1 <= 0; + b28_data_delayed_2 <= 0; + b28_data_delayed_3 <= 0; + b28_data_delayed_4 <= 0; + b28_data_delayed_5 <= 0; + b28_data_delayed_6 <= 0; + b28_data_delayed_7 <= 0; + b28_data_delayed_8 <= 0; + b28_data_delayed_9 <= 0; + b28_data_delayed_10 <= 0; + b28_data_delayed_11 <= 0; + b28_data_delayed_12 <= 0; + b28_data_delayed_13 <= 0; + b28_data_delayed_14 <= 0; + b28_data_delayed_15 <= 0; + b28_data_delayed_16 <= 0; + b28_data_delayed_17 <= 0; + b28_data_delayed_18 <= 0; + b28_data_delayed_19 <= 0; + b28_data_delayed_20 <= 0; + b28_data_delayed_21 <= 0; + b28_data_delayed_22 <= 0; + b28_data_delayed_23 <= 0; + b28_data_delayed_24 <= 0; + b28_data_delayed_25 <= 0; + b28_data_delayed_26 <= 0; + b28_data_delayed_27 <= 0; + b28_data_delayed_28 <= 0; + b29_data_delayed_1 <= 0; + b29_data_delayed_2 <= 0; + b29_data_delayed_3 <= 0; + b29_data_delayed_4 <= 0; + b29_data_delayed_5 <= 0; + b29_data_delayed_6 <= 0; + b29_data_delayed_7 <= 0; + b29_data_delayed_8 <= 0; + b29_data_delayed_9 <= 0; + b29_data_delayed_10 <= 0; + b29_data_delayed_11 <= 0; + b29_data_delayed_12 <= 0; + b29_data_delayed_13 <= 0; + b29_data_delayed_14 <= 0; + b29_data_delayed_15 <= 0; + b29_data_delayed_16 <= 0; + b29_data_delayed_17 <= 0; + b29_data_delayed_18 <= 0; + b29_data_delayed_19 <= 0; + b29_data_delayed_20 <= 0; + b29_data_delayed_21 <= 0; + b29_data_delayed_22 <= 0; + b29_data_delayed_23 <= 0; + b29_data_delayed_24 <= 0; + b29_data_delayed_25 <= 0; + b29_data_delayed_26 <= 0; + b29_data_delayed_27 <= 0; + b29_data_delayed_28 <= 0; + b29_data_delayed_29 <= 0; + b30_data_delayed_1 <= 0; + b30_data_delayed_2 <= 0; + b30_data_delayed_3 <= 0; + b30_data_delayed_4 <= 0; + b30_data_delayed_5 <= 0; + b30_data_delayed_6 <= 0; + b30_data_delayed_7 <= 0; + b30_data_delayed_8 <= 0; + b30_data_delayed_9 <= 0; + b30_data_delayed_10 <= 0; + b30_data_delayed_11 <= 0; + b30_data_delayed_12 <= 0; + b30_data_delayed_13 <= 0; + b30_data_delayed_14 <= 0; + b30_data_delayed_15 <= 0; + b30_data_delayed_16 <= 0; + b30_data_delayed_17 <= 0; + b30_data_delayed_18 <= 0; + b30_data_delayed_19 <= 0; + b30_data_delayed_20 <= 0; + b30_data_delayed_21 <= 0; + b30_data_delayed_22 <= 0; + b30_data_delayed_23 <= 0; + b30_data_delayed_24 <= 0; + b30_data_delayed_25 <= 0; + b30_data_delayed_26 <= 0; + b30_data_delayed_27 <= 0; + b30_data_delayed_28 <= 0; + b30_data_delayed_29 <= 0; + b30_data_delayed_30 <= 0; + b31_data_delayed_1 <= 0; + b31_data_delayed_2 <= 0; + b31_data_delayed_3 <= 0; + b31_data_delayed_4 <= 0; + b31_data_delayed_5 <= 0; + b31_data_delayed_6 <= 0; + b31_data_delayed_7 <= 0; + b31_data_delayed_8 <= 0; + b31_data_delayed_9 <= 0; + b31_data_delayed_10 <= 0; + b31_data_delayed_11 <= 0; + b31_data_delayed_12 <= 0; + b31_data_delayed_13 <= 0; + b31_data_delayed_14 <= 0; + b31_data_delayed_15 <= 0; + b31_data_delayed_16 <= 0; + b31_data_delayed_17 <= 0; + b31_data_delayed_18 <= 0; + b31_data_delayed_19 <= 0; + b31_data_delayed_20 <= 0; + b31_data_delayed_21 <= 0; + b31_data_delayed_22 <= 0; + b31_data_delayed_23 <= 0; + b31_data_delayed_24 <= 0; + b31_data_delayed_25 <= 0; + b31_data_delayed_26 <= 0; + b31_data_delayed_27 <= 0; + b31_data_delayed_28 <= 0; + b31_data_delayed_29 <= 0; + b31_data_delayed_30 <= 0; + b31_data_delayed_31 <= 0; + end + else begin + b1_data_delayed_1 <= b1_data; + b2_data_delayed_1 <= b2_data; + b2_data_delayed_2 <= b2_data_delayed_1; + b3_data_delayed_1 <= b3_data; + b3_data_delayed_2 <= b3_data_delayed_1; + b3_data_delayed_3 <= b3_data_delayed_2; + b4_data_delayed_1 <= b4_data; + b4_data_delayed_2 <= b4_data_delayed_1; + b4_data_delayed_3 <= b4_data_delayed_2; + b4_data_delayed_4 <= b4_data_delayed_3; + b5_data_delayed_1 <= b5_data; + b5_data_delayed_2 <= b5_data_delayed_1; + b5_data_delayed_3 <= b5_data_delayed_2; + b5_data_delayed_4 <= b5_data_delayed_3; + b5_data_delayed_5 <= b5_data_delayed_4; + b6_data_delayed_1 <= b6_data; + b6_data_delayed_2 <= b6_data_delayed_1; + b6_data_delayed_3 <= b6_data_delayed_2; + b6_data_delayed_4 <= b6_data_delayed_3; + b6_data_delayed_5 <= b6_data_delayed_4; + b6_data_delayed_6 <= b6_data_delayed_5; + b7_data_delayed_1 <= b7_data; + b7_data_delayed_2 <= b7_data_delayed_1; + b7_data_delayed_3 <= b7_data_delayed_2; + b7_data_delayed_4 <= b7_data_delayed_3; + b7_data_delayed_5 <= b7_data_delayed_4; + b7_data_delayed_6 <= b7_data_delayed_5; + b7_data_delayed_7 <= b7_data_delayed_6; + b8_data_delayed_1 <= b8_data; + b8_data_delayed_2 <= b8_data_delayed_1; + b8_data_delayed_3 <= b8_data_delayed_2; + b8_data_delayed_4 <= b8_data_delayed_3; + b8_data_delayed_5 <= b8_data_delayed_4; + b8_data_delayed_6 <= b8_data_delayed_5; + b8_data_delayed_7 <= b8_data_delayed_6; + b8_data_delayed_8 <= b8_data_delayed_7; + b9_data_delayed_1 <= b9_data; + b9_data_delayed_2 <= b9_data_delayed_1; + b9_data_delayed_3 <= b9_data_delayed_2; + b9_data_delayed_4 <= b9_data_delayed_3; + b9_data_delayed_5 <= b9_data_delayed_4; + b9_data_delayed_6 <= b9_data_delayed_5; + b9_data_delayed_7 <= b9_data_delayed_6; + b9_data_delayed_8 <= b9_data_delayed_7; + b9_data_delayed_9 <= b9_data_delayed_8; + b10_data_delayed_1 <= b10_data; + b10_data_delayed_2 <= b10_data_delayed_1; + b10_data_delayed_3 <= b10_data_delayed_2; + b10_data_delayed_4 <= b10_data_delayed_3; + b10_data_delayed_5 <= b10_data_delayed_4; + b10_data_delayed_6 <= b10_data_delayed_5; + b10_data_delayed_7 <= b10_data_delayed_6; + b10_data_delayed_8 <= b10_data_delayed_7; + b10_data_delayed_9 <= b10_data_delayed_8; + b10_data_delayed_10 <= b10_data_delayed_9; + b11_data_delayed_1 <= b11_data; + b11_data_delayed_2 <= b11_data_delayed_1; + b11_data_delayed_3 <= b11_data_delayed_2; + b11_data_delayed_4 <= b11_data_delayed_3; + b11_data_delayed_5 <= b11_data_delayed_4; + b11_data_delayed_6 <= b11_data_delayed_5; + b11_data_delayed_7 <= b11_data_delayed_6; + b11_data_delayed_8 <= b11_data_delayed_7; + b11_data_delayed_9 <= b11_data_delayed_8; + b11_data_delayed_10 <= b11_data_delayed_9; + b11_data_delayed_11 <= b11_data_delayed_10; + b12_data_delayed_1 <= b12_data; + b12_data_delayed_2 <= b12_data_delayed_1; + b12_data_delayed_3 <= b12_data_delayed_2; + b12_data_delayed_4 <= b12_data_delayed_3; + b12_data_delayed_5 <= b12_data_delayed_4; + b12_data_delayed_6 <= b12_data_delayed_5; + b12_data_delayed_7 <= b12_data_delayed_6; + b12_data_delayed_8 <= b12_data_delayed_7; + b12_data_delayed_9 <= b12_data_delayed_8; + b12_data_delayed_10 <= b12_data_delayed_9; + b12_data_delayed_11 <= b12_data_delayed_10; + b12_data_delayed_12 <= b12_data_delayed_11; + b13_data_delayed_1 <= b13_data; + b13_data_delayed_2 <= b13_data_delayed_1; + b13_data_delayed_3 <= b13_data_delayed_2; + b13_data_delayed_4 <= b13_data_delayed_3; + b13_data_delayed_5 <= b13_data_delayed_4; + b13_data_delayed_6 <= b13_data_delayed_5; + b13_data_delayed_7 <= b13_data_delayed_6; + b13_data_delayed_8 <= b13_data_delayed_7; + b13_data_delayed_9 <= b13_data_delayed_8; + b13_data_delayed_10 <= b13_data_delayed_9; + b13_data_delayed_11 <= b13_data_delayed_10; + b13_data_delayed_12 <= b13_data_delayed_11; + b13_data_delayed_13 <= b13_data_delayed_12; + b14_data_delayed_1 <= b14_data; + b14_data_delayed_2 <= b14_data_delayed_1; + b14_data_delayed_3 <= b14_data_delayed_2; + b14_data_delayed_4 <= b14_data_delayed_3; + b14_data_delayed_5 <= b14_data_delayed_4; + b14_data_delayed_6 <= b14_data_delayed_5; + b14_data_delayed_7 <= b14_data_delayed_6; + b14_data_delayed_8 <= b14_data_delayed_7; + b14_data_delayed_9 <= b14_data_delayed_8; + b14_data_delayed_10 <= b14_data_delayed_9; + b14_data_delayed_11 <= b14_data_delayed_10; + b14_data_delayed_12 <= b14_data_delayed_11; + b14_data_delayed_13 <= b14_data_delayed_12; + b14_data_delayed_14 <= b14_data_delayed_13; + b15_data_delayed_1 <= b15_data; + b15_data_delayed_2 <= b15_data_delayed_1; + b15_data_delayed_3 <= b15_data_delayed_2; + b15_data_delayed_4 <= b15_data_delayed_3; + b15_data_delayed_5 <= b15_data_delayed_4; + b15_data_delayed_6 <= b15_data_delayed_5; + b15_data_delayed_7 <= b15_data_delayed_6; + b15_data_delayed_8 <= b15_data_delayed_7; + b15_data_delayed_9 <= b15_data_delayed_8; + b15_data_delayed_10 <= b15_data_delayed_9; + b15_data_delayed_11 <= b15_data_delayed_10; + b15_data_delayed_12 <= b15_data_delayed_11; + b15_data_delayed_13 <= b15_data_delayed_12; + b15_data_delayed_14 <= b15_data_delayed_13; + b15_data_delayed_15 <= b15_data_delayed_14; + b16_data_delayed_1 <= b16_data; + b16_data_delayed_2 <= b16_data_delayed_1; + b16_data_delayed_3 <= b16_data_delayed_2; + b16_data_delayed_4 <= b16_data_delayed_3; + b16_data_delayed_5 <= b16_data_delayed_4; + b16_data_delayed_6 <= b16_data_delayed_5; + b16_data_delayed_7 <= b16_data_delayed_6; + b16_data_delayed_8 <= b16_data_delayed_7; + b16_data_delayed_9 <= b16_data_delayed_8; + b16_data_delayed_10 <= b16_data_delayed_9; + b16_data_delayed_11 <= b16_data_delayed_10; + b16_data_delayed_12 <= b16_data_delayed_11; + b16_data_delayed_13 <= b16_data_delayed_12; + b16_data_delayed_14 <= b16_data_delayed_13; + b16_data_delayed_15 <= b16_data_delayed_14; + b16_data_delayed_16 <= b16_data_delayed_15; + b17_data_delayed_1 <= b17_data; + b17_data_delayed_2 <= b17_data_delayed_1; + b17_data_delayed_3 <= b17_data_delayed_2; + b17_data_delayed_4 <= b17_data_delayed_3; + b17_data_delayed_5 <= b17_data_delayed_4; + b17_data_delayed_6 <= b17_data_delayed_5; + b17_data_delayed_7 <= b17_data_delayed_6; + b17_data_delayed_8 <= b17_data_delayed_7; + b17_data_delayed_9 <= b17_data_delayed_8; + b17_data_delayed_10 <= b17_data_delayed_9; + b17_data_delayed_11 <= b17_data_delayed_10; + b17_data_delayed_12 <= b17_data_delayed_11; + b17_data_delayed_13 <= b17_data_delayed_12; + b17_data_delayed_14 <= b17_data_delayed_13; + b17_data_delayed_15 <= b17_data_delayed_14; + b17_data_delayed_16 <= b17_data_delayed_15; + b17_data_delayed_17 <= b17_data_delayed_16; + b18_data_delayed_1 <= b18_data; + b18_data_delayed_2 <= b18_data_delayed_1; + b18_data_delayed_3 <= b18_data_delayed_2; + b18_data_delayed_4 <= b18_data_delayed_3; + b18_data_delayed_5 <= b18_data_delayed_4; + b18_data_delayed_6 <= b18_data_delayed_5; + b18_data_delayed_7 <= b18_data_delayed_6; + b18_data_delayed_8 <= b18_data_delayed_7; + b18_data_delayed_9 <= b18_data_delayed_8; + b18_data_delayed_10 <= b18_data_delayed_9; + b18_data_delayed_11 <= b18_data_delayed_10; + b18_data_delayed_12 <= b18_data_delayed_11; + b18_data_delayed_13 <= b18_data_delayed_12; + b18_data_delayed_14 <= b18_data_delayed_13; + b18_data_delayed_15 <= b18_data_delayed_14; + b18_data_delayed_16 <= b18_data_delayed_15; + b18_data_delayed_17 <= b18_data_delayed_16; + b18_data_delayed_18 <= b18_data_delayed_17; + b19_data_delayed_1 <= b19_data; + b19_data_delayed_2 <= b19_data_delayed_1; + b19_data_delayed_3 <= b19_data_delayed_2; + b19_data_delayed_4 <= b19_data_delayed_3; + b19_data_delayed_5 <= b19_data_delayed_4; + b19_data_delayed_6 <= b19_data_delayed_5; + b19_data_delayed_7 <= b19_data_delayed_6; + b19_data_delayed_8 <= b19_data_delayed_7; + b19_data_delayed_9 <= b19_data_delayed_8; + b19_data_delayed_10 <= b19_data_delayed_9; + b19_data_delayed_11 <= b19_data_delayed_10; + b19_data_delayed_12 <= b19_data_delayed_11; + b19_data_delayed_13 <= b19_data_delayed_12; + b19_data_delayed_14 <= b19_data_delayed_13; + b19_data_delayed_15 <= b19_data_delayed_14; + b19_data_delayed_16 <= b19_data_delayed_15; + b19_data_delayed_17 <= b19_data_delayed_16; + b19_data_delayed_18 <= b19_data_delayed_17; + b19_data_delayed_19 <= b19_data_delayed_18; + b20_data_delayed_1 <= b20_data; + b20_data_delayed_2 <= b20_data_delayed_1; + b20_data_delayed_3 <= b20_data_delayed_2; + b20_data_delayed_4 <= b20_data_delayed_3; + b20_data_delayed_5 <= b20_data_delayed_4; + b20_data_delayed_6 <= b20_data_delayed_5; + b20_data_delayed_7 <= b20_data_delayed_6; + b20_data_delayed_8 <= b20_data_delayed_7; + b20_data_delayed_9 <= b20_data_delayed_8; + b20_data_delayed_10 <= b20_data_delayed_9; + b20_data_delayed_11 <= b20_data_delayed_10; + b20_data_delayed_12 <= b20_data_delayed_11; + b20_data_delayed_13 <= b20_data_delayed_12; + b20_data_delayed_14 <= b20_data_delayed_13; + b20_data_delayed_15 <= b20_data_delayed_14; + b20_data_delayed_16 <= b20_data_delayed_15; + b20_data_delayed_17 <= b20_data_delayed_16; + b20_data_delayed_18 <= b20_data_delayed_17; + b20_data_delayed_19 <= b20_data_delayed_18; + b20_data_delayed_20 <= b20_data_delayed_19; + b21_data_delayed_1 <= b21_data; + b21_data_delayed_2 <= b21_data_delayed_1; + b21_data_delayed_3 <= b21_data_delayed_2; + b21_data_delayed_4 <= b21_data_delayed_3; + b21_data_delayed_5 <= b21_data_delayed_4; + b21_data_delayed_6 <= b21_data_delayed_5; + b21_data_delayed_7 <= b21_data_delayed_6; + b21_data_delayed_8 <= b21_data_delayed_7; + b21_data_delayed_9 <= b21_data_delayed_8; + b21_data_delayed_10 <= b21_data_delayed_9; + b21_data_delayed_11 <= b21_data_delayed_10; + b21_data_delayed_12 <= b21_data_delayed_11; + b21_data_delayed_13 <= b21_data_delayed_12; + b21_data_delayed_14 <= b21_data_delayed_13; + b21_data_delayed_15 <= b21_data_delayed_14; + b21_data_delayed_16 <= b21_data_delayed_15; + b21_data_delayed_17 <= b21_data_delayed_16; + b21_data_delayed_18 <= b21_data_delayed_17; + b21_data_delayed_19 <= b21_data_delayed_18; + b21_data_delayed_20 <= b21_data_delayed_19; + b21_data_delayed_21 <= b21_data_delayed_20; + b22_data_delayed_1 <= b22_data; + b22_data_delayed_2 <= b22_data_delayed_1; + b22_data_delayed_3 <= b22_data_delayed_2; + b22_data_delayed_4 <= b22_data_delayed_3; + b22_data_delayed_5 <= b22_data_delayed_4; + b22_data_delayed_6 <= b22_data_delayed_5; + b22_data_delayed_7 <= b22_data_delayed_6; + b22_data_delayed_8 <= b22_data_delayed_7; + b22_data_delayed_9 <= b22_data_delayed_8; + b22_data_delayed_10 <= b22_data_delayed_9; + b22_data_delayed_11 <= b22_data_delayed_10; + b22_data_delayed_12 <= b22_data_delayed_11; + b22_data_delayed_13 <= b22_data_delayed_12; + b22_data_delayed_14 <= b22_data_delayed_13; + b22_data_delayed_15 <= b22_data_delayed_14; + b22_data_delayed_16 <= b22_data_delayed_15; + b22_data_delayed_17 <= b22_data_delayed_16; + b22_data_delayed_18 <= b22_data_delayed_17; + b22_data_delayed_19 <= b22_data_delayed_18; + b22_data_delayed_20 <= b22_data_delayed_19; + b22_data_delayed_21 <= b22_data_delayed_20; + b22_data_delayed_22 <= b22_data_delayed_21; + b23_data_delayed_1 <= b23_data; + b23_data_delayed_2 <= b23_data_delayed_1; + b23_data_delayed_3 <= b23_data_delayed_2; + b23_data_delayed_4 <= b23_data_delayed_3; + b23_data_delayed_5 <= b23_data_delayed_4; + b23_data_delayed_6 <= b23_data_delayed_5; + b23_data_delayed_7 <= b23_data_delayed_6; + b23_data_delayed_8 <= b23_data_delayed_7; + b23_data_delayed_9 <= b23_data_delayed_8; + b23_data_delayed_10 <= b23_data_delayed_9; + b23_data_delayed_11 <= b23_data_delayed_10; + b23_data_delayed_12 <= b23_data_delayed_11; + b23_data_delayed_13 <= b23_data_delayed_12; + b23_data_delayed_14 <= b23_data_delayed_13; + b23_data_delayed_15 <= b23_data_delayed_14; + b23_data_delayed_16 <= b23_data_delayed_15; + b23_data_delayed_17 <= b23_data_delayed_16; + b23_data_delayed_18 <= b23_data_delayed_17; + b23_data_delayed_19 <= b23_data_delayed_18; + b23_data_delayed_20 <= b23_data_delayed_19; + b23_data_delayed_21 <= b23_data_delayed_20; + b23_data_delayed_22 <= b23_data_delayed_21; + b23_data_delayed_23 <= b23_data_delayed_22; + b24_data_delayed_1 <= b24_data; + b24_data_delayed_2 <= b24_data_delayed_1; + b24_data_delayed_3 <= b24_data_delayed_2; + b24_data_delayed_4 <= b24_data_delayed_3; + b24_data_delayed_5 <= b24_data_delayed_4; + b24_data_delayed_6 <= b24_data_delayed_5; + b24_data_delayed_7 <= b24_data_delayed_6; + b24_data_delayed_8 <= b24_data_delayed_7; + b24_data_delayed_9 <= b24_data_delayed_8; + b24_data_delayed_10 <= b24_data_delayed_9; + b24_data_delayed_11 <= b24_data_delayed_10; + b24_data_delayed_12 <= b24_data_delayed_11; + b24_data_delayed_13 <= b24_data_delayed_12; + b24_data_delayed_14 <= b24_data_delayed_13; + b24_data_delayed_15 <= b24_data_delayed_14; + b24_data_delayed_16 <= b24_data_delayed_15; + b24_data_delayed_17 <= b24_data_delayed_16; + b24_data_delayed_18 <= b24_data_delayed_17; + b24_data_delayed_19 <= b24_data_delayed_18; + b24_data_delayed_20 <= b24_data_delayed_19; + b24_data_delayed_21 <= b24_data_delayed_20; + b24_data_delayed_22 <= b24_data_delayed_21; + b24_data_delayed_23 <= b24_data_delayed_22; + b24_data_delayed_24 <= b24_data_delayed_23; + b25_data_delayed_1 <= b25_data; + b25_data_delayed_2 <= b25_data_delayed_1; + b25_data_delayed_3 <= b25_data_delayed_2; + b25_data_delayed_4 <= b25_data_delayed_3; + b25_data_delayed_5 <= b25_data_delayed_4; + b25_data_delayed_6 <= b25_data_delayed_5; + b25_data_delayed_7 <= b25_data_delayed_6; + b25_data_delayed_8 <= b25_data_delayed_7; + b25_data_delayed_9 <= b25_data_delayed_8; + b25_data_delayed_10 <= b25_data_delayed_9; + b25_data_delayed_11 <= b25_data_delayed_10; + b25_data_delayed_12 <= b25_data_delayed_11; + b25_data_delayed_13 <= b25_data_delayed_12; + b25_data_delayed_14 <= b25_data_delayed_13; + b25_data_delayed_15 <= b25_data_delayed_14; + b25_data_delayed_16 <= b25_data_delayed_15; + b25_data_delayed_17 <= b25_data_delayed_16; + b25_data_delayed_18 <= b25_data_delayed_17; + b25_data_delayed_19 <= b25_data_delayed_18; + b25_data_delayed_20 <= b25_data_delayed_19; + b25_data_delayed_21 <= b25_data_delayed_20; + b25_data_delayed_22 <= b25_data_delayed_21; + b25_data_delayed_23 <= b25_data_delayed_22; + b25_data_delayed_24 <= b25_data_delayed_23; + b25_data_delayed_25 <= b25_data_delayed_24; + b26_data_delayed_1 <= b26_data; + b26_data_delayed_2 <= b26_data_delayed_1; + b26_data_delayed_3 <= b26_data_delayed_2; + b26_data_delayed_4 <= b26_data_delayed_3; + b26_data_delayed_5 <= b26_data_delayed_4; + b26_data_delayed_6 <= b26_data_delayed_5; + b26_data_delayed_7 <= b26_data_delayed_6; + b26_data_delayed_8 <= b26_data_delayed_7; + b26_data_delayed_9 <= b26_data_delayed_8; + b26_data_delayed_10 <= b26_data_delayed_9; + b26_data_delayed_11 <= b26_data_delayed_10; + b26_data_delayed_12 <= b26_data_delayed_11; + b26_data_delayed_13 <= b26_data_delayed_12; + b26_data_delayed_14 <= b26_data_delayed_13; + b26_data_delayed_15 <= b26_data_delayed_14; + b26_data_delayed_16 <= b26_data_delayed_15; + b26_data_delayed_17 <= b26_data_delayed_16; + b26_data_delayed_18 <= b26_data_delayed_17; + b26_data_delayed_19 <= b26_data_delayed_18; + b26_data_delayed_20 <= b26_data_delayed_19; + b26_data_delayed_21 <= b26_data_delayed_20; + b26_data_delayed_22 <= b26_data_delayed_21; + b26_data_delayed_23 <= b26_data_delayed_22; + b26_data_delayed_24 <= b26_data_delayed_23; + b26_data_delayed_25 <= b26_data_delayed_24; + b26_data_delayed_26 <= b26_data_delayed_25; + b27_data_delayed_1 <= b27_data; + b27_data_delayed_2 <= b27_data_delayed_1; + b27_data_delayed_3 <= b27_data_delayed_2; + b27_data_delayed_4 <= b27_data_delayed_3; + b27_data_delayed_5 <= b27_data_delayed_4; + b27_data_delayed_6 <= b27_data_delayed_5; + b27_data_delayed_7 <= b27_data_delayed_6; + b27_data_delayed_8 <= b27_data_delayed_7; + b27_data_delayed_9 <= b27_data_delayed_8; + b27_data_delayed_10 <= b27_data_delayed_9; + b27_data_delayed_11 <= b27_data_delayed_10; + b27_data_delayed_12 <= b27_data_delayed_11; + b27_data_delayed_13 <= b27_data_delayed_12; + b27_data_delayed_14 <= b27_data_delayed_13; + b27_data_delayed_15 <= b27_data_delayed_14; + b27_data_delayed_16 <= b27_data_delayed_15; + b27_data_delayed_17 <= b27_data_delayed_16; + b27_data_delayed_18 <= b27_data_delayed_17; + b27_data_delayed_19 <= b27_data_delayed_18; + b27_data_delayed_20 <= b27_data_delayed_19; + b27_data_delayed_21 <= b27_data_delayed_20; + b27_data_delayed_22 <= b27_data_delayed_21; + b27_data_delayed_23 <= b27_data_delayed_22; + b27_data_delayed_24 <= b27_data_delayed_23; + b27_data_delayed_25 <= b27_data_delayed_24; + b27_data_delayed_26 <= b27_data_delayed_25; + b27_data_delayed_27 <= b27_data_delayed_26; + b28_data_delayed_1 <= b28_data; + b28_data_delayed_2 <= b28_data_delayed_1; + b28_data_delayed_3 <= b28_data_delayed_2; + b28_data_delayed_4 <= b28_data_delayed_3; + b28_data_delayed_5 <= b28_data_delayed_4; + b28_data_delayed_6 <= b28_data_delayed_5; + b28_data_delayed_7 <= b28_data_delayed_6; + b28_data_delayed_8 <= b28_data_delayed_7; + b28_data_delayed_9 <= b28_data_delayed_8; + b28_data_delayed_10 <= b28_data_delayed_9; + b28_data_delayed_11 <= b28_data_delayed_10; + b28_data_delayed_12 <= b28_data_delayed_11; + b28_data_delayed_13 <= b28_data_delayed_12; + b28_data_delayed_14 <= b28_data_delayed_13; + b28_data_delayed_15 <= b28_data_delayed_14; + b28_data_delayed_16 <= b28_data_delayed_15; + b28_data_delayed_17 <= b28_data_delayed_16; + b28_data_delayed_18 <= b28_data_delayed_17; + b28_data_delayed_19 <= b28_data_delayed_18; + b28_data_delayed_20 <= b28_data_delayed_19; + b28_data_delayed_21 <= b28_data_delayed_20; + b28_data_delayed_22 <= b28_data_delayed_21; + b28_data_delayed_23 <= b28_data_delayed_22; + b28_data_delayed_24 <= b28_data_delayed_23; + b28_data_delayed_25 <= b28_data_delayed_24; + b28_data_delayed_26 <= b28_data_delayed_25; + b28_data_delayed_27 <= b28_data_delayed_26; + b28_data_delayed_28 <= b28_data_delayed_27; + b29_data_delayed_1 <= b29_data; + b29_data_delayed_2 <= b29_data_delayed_1; + b29_data_delayed_3 <= b29_data_delayed_2; + b29_data_delayed_4 <= b29_data_delayed_3; + b29_data_delayed_5 <= b29_data_delayed_4; + b29_data_delayed_6 <= b29_data_delayed_5; + b29_data_delayed_7 <= b29_data_delayed_6; + b29_data_delayed_8 <= b29_data_delayed_7; + b29_data_delayed_9 <= b29_data_delayed_8; + b29_data_delayed_10 <= b29_data_delayed_9; + b29_data_delayed_11 <= b29_data_delayed_10; + b29_data_delayed_12 <= b29_data_delayed_11; + b29_data_delayed_13 <= b29_data_delayed_12; + b29_data_delayed_14 <= b29_data_delayed_13; + b29_data_delayed_15 <= b29_data_delayed_14; + b29_data_delayed_16 <= b29_data_delayed_15; + b29_data_delayed_17 <= b29_data_delayed_16; + b29_data_delayed_18 <= b29_data_delayed_17; + b29_data_delayed_19 <= b29_data_delayed_18; + b29_data_delayed_20 <= b29_data_delayed_19; + b29_data_delayed_21 <= b29_data_delayed_20; + b29_data_delayed_22 <= b29_data_delayed_21; + b29_data_delayed_23 <= b29_data_delayed_22; + b29_data_delayed_24 <= b29_data_delayed_23; + b29_data_delayed_25 <= b29_data_delayed_24; + b29_data_delayed_26 <= b29_data_delayed_25; + b29_data_delayed_27 <= b29_data_delayed_26; + b29_data_delayed_28 <= b29_data_delayed_27; + b29_data_delayed_29 <= b29_data_delayed_28; + b30_data_delayed_1 <= b30_data; + b30_data_delayed_2 <= b30_data_delayed_1; + b30_data_delayed_3 <= b30_data_delayed_2; + b30_data_delayed_4 <= b30_data_delayed_3; + b30_data_delayed_5 <= b30_data_delayed_4; + b30_data_delayed_6 <= b30_data_delayed_5; + b30_data_delayed_7 <= b30_data_delayed_6; + b30_data_delayed_8 <= b30_data_delayed_7; + b30_data_delayed_9 <= b30_data_delayed_8; + b30_data_delayed_10 <= b30_data_delayed_9; + b30_data_delayed_11 <= b30_data_delayed_10; + b30_data_delayed_12 <= b30_data_delayed_11; + b30_data_delayed_13 <= b30_data_delayed_12; + b30_data_delayed_14 <= b30_data_delayed_13; + b30_data_delayed_15 <= b30_data_delayed_14; + b30_data_delayed_16 <= b30_data_delayed_15; + b30_data_delayed_17 <= b30_data_delayed_16; + b30_data_delayed_18 <= b30_data_delayed_17; + b30_data_delayed_19 <= b30_data_delayed_18; + b30_data_delayed_20 <= b30_data_delayed_19; + b30_data_delayed_21 <= b30_data_delayed_20; + b30_data_delayed_22 <= b30_data_delayed_21; + b30_data_delayed_23 <= b30_data_delayed_22; + b30_data_delayed_24 <= b30_data_delayed_23; + b30_data_delayed_25 <= b30_data_delayed_24; + b30_data_delayed_26 <= b30_data_delayed_25; + b30_data_delayed_27 <= b30_data_delayed_26; + b30_data_delayed_28 <= b30_data_delayed_27; + b30_data_delayed_29 <= b30_data_delayed_28; + b30_data_delayed_30 <= b30_data_delayed_29; + b31_data_delayed_1 <= b31_data; + b31_data_delayed_2 <= b31_data_delayed_1; + b31_data_delayed_3 <= b31_data_delayed_2; + b31_data_delayed_4 <= b31_data_delayed_3; + b31_data_delayed_5 <= b31_data_delayed_4; + b31_data_delayed_6 <= b31_data_delayed_5; + b31_data_delayed_7 <= b31_data_delayed_6; + b31_data_delayed_8 <= b31_data_delayed_7; + b31_data_delayed_9 <= b31_data_delayed_8; + b31_data_delayed_10 <= b31_data_delayed_9; + b31_data_delayed_11 <= b31_data_delayed_10; + b31_data_delayed_12 <= b31_data_delayed_11; + b31_data_delayed_13 <= b31_data_delayed_12; + b31_data_delayed_14 <= b31_data_delayed_13; + b31_data_delayed_15 <= b31_data_delayed_14; + b31_data_delayed_16 <= b31_data_delayed_15; + b31_data_delayed_17 <= b31_data_delayed_16; + b31_data_delayed_18 <= b31_data_delayed_17; + b31_data_delayed_19 <= b31_data_delayed_18; + b31_data_delayed_20 <= b31_data_delayed_19; + b31_data_delayed_21 <= b31_data_delayed_20; + b31_data_delayed_22 <= b31_data_delayed_21; + b31_data_delayed_23 <= b31_data_delayed_22; + b31_data_delayed_24 <= b31_data_delayed_23; + b31_data_delayed_25 <= b31_data_delayed_24; + b31_data_delayed_26 <= b31_data_delayed_25; + b31_data_delayed_27 <= b31_data_delayed_26; + b31_data_delayed_28 <= b31_data_delayed_27; + b31_data_delayed_29 <= b31_data_delayed_28; + b31_data_delayed_30 <= b31_data_delayed_29; + b31_data_delayed_31 <= b31_data_delayed_30; + end +end + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Systolically connected PEs +////////////////////////////////////////////////////////////////////////// + +module systolic_pe_matrix( + reset, + clk, + pe_reset, + b_data_sel, + a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26, a27, a28, a29, a30, a31, + b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15, b16, b17, b18, b19, b20, b21, b22, b23, b24, b25, b26, b27, b28, b29, b30, b31, + c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19, c20, c21, c22, c23, c24, c25, c26, c27, c28, c29, c30, c31, + matrixC0_0, + matrixC0_1, + matrixC0_2, + matrixC0_3, + matrixC0_4, + matrixC0_5, + matrixC0_6, + matrixC0_7, + matrixC0_8, + matrixC0_9, + matrixC0_10, + matrixC0_11, + matrixC0_12, + matrixC0_13, + matrixC0_14, + matrixC0_15, + matrixC0_16, + matrixC0_17, + matrixC0_18, + matrixC0_19, + matrixC0_20, + matrixC0_21, + matrixC0_22, + matrixC0_23, + matrixC0_24, + matrixC0_25, + matrixC0_26, + matrixC0_27, + matrixC0_28, + matrixC0_29, + matrixC0_30, + matrixC0_31, + matrixC1_0, + matrixC1_1, + matrixC1_2, + matrixC1_3, + matrixC1_4, + matrixC1_5, + matrixC1_6, + matrixC1_7, + matrixC1_8, + matrixC1_9, + matrixC1_10, + matrixC1_11, + matrixC1_12, + matrixC1_13, + matrixC1_14, + matrixC1_15, + matrixC1_16, + matrixC1_17, + matrixC1_18, + matrixC1_19, + matrixC1_20, + matrixC1_21, + matrixC1_22, + matrixC1_23, + matrixC1_24, + matrixC1_25, + matrixC1_26, + matrixC1_27, + matrixC1_28, + matrixC1_29, + matrixC1_30, + matrixC1_31, + matrixC2_0, + matrixC2_1, + matrixC2_2, + matrixC2_3, + matrixC2_4, + matrixC2_5, + matrixC2_6, + matrixC2_7, + matrixC2_8, + matrixC2_9, + matrixC2_10, + matrixC2_11, + matrixC2_12, + matrixC2_13, + matrixC2_14, + matrixC2_15, + matrixC2_16, + matrixC2_17, + matrixC2_18, + matrixC2_19, + matrixC2_20, + matrixC2_21, + matrixC2_22, + matrixC2_23, + matrixC2_24, + matrixC2_25, + matrixC2_26, + matrixC2_27, + matrixC2_28, + matrixC2_29, + matrixC2_30, + matrixC2_31, + matrixC3_0, + matrixC3_1, + matrixC3_2, + matrixC3_3, + matrixC3_4, + matrixC3_5, + matrixC3_6, + matrixC3_7, + matrixC3_8, + matrixC3_9, + matrixC3_10, + matrixC3_11, + matrixC3_12, + matrixC3_13, + matrixC3_14, + matrixC3_15, + matrixC3_16, + matrixC3_17, + matrixC3_18, + matrixC3_19, + matrixC3_20, + matrixC3_21, + matrixC3_22, + matrixC3_23, + matrixC3_24, + matrixC3_25, + matrixC3_26, + matrixC3_27, + matrixC3_28, + matrixC3_29, + matrixC3_30, + matrixC3_31, + matrixC4_0, + matrixC4_1, + matrixC4_2, + matrixC4_3, + matrixC4_4, + matrixC4_5, + matrixC4_6, + matrixC4_7, + matrixC4_8, + matrixC4_9, + matrixC4_10, + matrixC4_11, + matrixC4_12, + matrixC4_13, + matrixC4_14, + matrixC4_15, + matrixC4_16, + matrixC4_17, + matrixC4_18, + matrixC4_19, + matrixC4_20, + matrixC4_21, + matrixC4_22, + matrixC4_23, + matrixC4_24, + matrixC4_25, + matrixC4_26, + matrixC4_27, + matrixC4_28, + matrixC4_29, + matrixC4_30, + matrixC4_31, + matrixC5_0, + matrixC5_1, + matrixC5_2, + matrixC5_3, + matrixC5_4, + matrixC5_5, + matrixC5_6, + matrixC5_7, + matrixC5_8, + matrixC5_9, + matrixC5_10, + matrixC5_11, + matrixC5_12, + matrixC5_13, + matrixC5_14, + matrixC5_15, + matrixC5_16, + matrixC5_17, + matrixC5_18, + matrixC5_19, + matrixC5_20, + matrixC5_21, + matrixC5_22, + matrixC5_23, + matrixC5_24, + matrixC5_25, + matrixC5_26, + matrixC5_27, + matrixC5_28, + matrixC5_29, + matrixC5_30, + matrixC5_31, + matrixC6_0, + matrixC6_1, + matrixC6_2, + matrixC6_3, + matrixC6_4, + matrixC6_5, + matrixC6_6, + matrixC6_7, + matrixC6_8, + matrixC6_9, + matrixC6_10, + matrixC6_11, + matrixC6_12, + matrixC6_13, + matrixC6_14, + matrixC6_15, + matrixC6_16, + matrixC6_17, + matrixC6_18, + matrixC6_19, + matrixC6_20, + matrixC6_21, + matrixC6_22, + matrixC6_23, + matrixC6_24, + matrixC6_25, + matrixC6_26, + matrixC6_27, + matrixC6_28, + matrixC6_29, + matrixC6_30, + matrixC6_31, + matrixC7_0, + matrixC7_1, + matrixC7_2, + matrixC7_3, + matrixC7_4, + matrixC7_5, + matrixC7_6, + matrixC7_7, + matrixC7_8, + matrixC7_9, + matrixC7_10, + matrixC7_11, + matrixC7_12, + matrixC7_13, + matrixC7_14, + matrixC7_15, + matrixC7_16, + matrixC7_17, + matrixC7_18, + matrixC7_19, + matrixC7_20, + matrixC7_21, + matrixC7_22, + matrixC7_23, + matrixC7_24, + matrixC7_25, + matrixC7_26, + matrixC7_27, + matrixC7_28, + matrixC7_29, + matrixC7_30, + matrixC7_31, + matrixC8_0, + matrixC8_1, + matrixC8_2, + matrixC8_3, + matrixC8_4, + matrixC8_5, + matrixC8_6, + matrixC8_7, + matrixC8_8, + matrixC8_9, + matrixC8_10, + matrixC8_11, + matrixC8_12, + matrixC8_13, + matrixC8_14, + matrixC8_15, + matrixC8_16, + matrixC8_17, + matrixC8_18, + matrixC8_19, + matrixC8_20, + matrixC8_21, + matrixC8_22, + matrixC8_23, + matrixC8_24, + matrixC8_25, + matrixC8_26, + matrixC8_27, + matrixC8_28, + matrixC8_29, + matrixC8_30, + matrixC8_31, + matrixC9_0, + matrixC9_1, + matrixC9_2, + matrixC9_3, + matrixC9_4, + matrixC9_5, + matrixC9_6, + matrixC9_7, + matrixC9_8, + matrixC9_9, + matrixC9_10, + matrixC9_11, + matrixC9_12, + matrixC9_13, + matrixC9_14, + matrixC9_15, + matrixC9_16, + matrixC9_17, + matrixC9_18, + matrixC9_19, + matrixC9_20, + matrixC9_21, + matrixC9_22, + matrixC9_23, + matrixC9_24, + matrixC9_25, + matrixC9_26, + matrixC9_27, + matrixC9_28, + matrixC9_29, + matrixC9_30, + matrixC9_31, + matrixC10_0, + matrixC10_1, + matrixC10_2, + matrixC10_3, + matrixC10_4, + matrixC10_5, + matrixC10_6, + matrixC10_7, + matrixC10_8, + matrixC10_9, + matrixC10_10, + matrixC10_11, + matrixC10_12, + matrixC10_13, + matrixC10_14, + matrixC10_15, + matrixC10_16, + matrixC10_17, + matrixC10_18, + matrixC10_19, + matrixC10_20, + matrixC10_21, + matrixC10_22, + matrixC10_23, + matrixC10_24, + matrixC10_25, + matrixC10_26, + matrixC10_27, + matrixC10_28, + matrixC10_29, + matrixC10_30, + matrixC10_31, + matrixC11_0, + matrixC11_1, + matrixC11_2, + matrixC11_3, + matrixC11_4, + matrixC11_5, + matrixC11_6, + matrixC11_7, + matrixC11_8, + matrixC11_9, + matrixC11_10, + matrixC11_11, + matrixC11_12, + matrixC11_13, + matrixC11_14, + matrixC11_15, + matrixC11_16, + matrixC11_17, + matrixC11_18, + matrixC11_19, + matrixC11_20, + matrixC11_21, + matrixC11_22, + matrixC11_23, + matrixC11_24, + matrixC11_25, + matrixC11_26, + matrixC11_27, + matrixC11_28, + matrixC11_29, + matrixC11_30, + matrixC11_31, + matrixC12_0, + matrixC12_1, + matrixC12_2, + matrixC12_3, + matrixC12_4, + matrixC12_5, + matrixC12_6, + matrixC12_7, + matrixC12_8, + matrixC12_9, + matrixC12_10, + matrixC12_11, + matrixC12_12, + matrixC12_13, + matrixC12_14, + matrixC12_15, + matrixC12_16, + matrixC12_17, + matrixC12_18, + matrixC12_19, + matrixC12_20, + matrixC12_21, + matrixC12_22, + matrixC12_23, + matrixC12_24, + matrixC12_25, + matrixC12_26, + matrixC12_27, + matrixC12_28, + matrixC12_29, + matrixC12_30, + matrixC12_31, + matrixC13_0, + matrixC13_1, + matrixC13_2, + matrixC13_3, + matrixC13_4, + matrixC13_5, + matrixC13_6, + matrixC13_7, + matrixC13_8, + matrixC13_9, + matrixC13_10, + matrixC13_11, + matrixC13_12, + matrixC13_13, + matrixC13_14, + matrixC13_15, + matrixC13_16, + matrixC13_17, + matrixC13_18, + matrixC13_19, + matrixC13_20, + matrixC13_21, + matrixC13_22, + matrixC13_23, + matrixC13_24, + matrixC13_25, + matrixC13_26, + matrixC13_27, + matrixC13_28, + matrixC13_29, + matrixC13_30, + matrixC13_31, + matrixC14_0, + matrixC14_1, + matrixC14_2, + matrixC14_3, + matrixC14_4, + matrixC14_5, + matrixC14_6, + matrixC14_7, + matrixC14_8, + matrixC14_9, + matrixC14_10, + matrixC14_11, + matrixC14_12, + matrixC14_13, + matrixC14_14, + matrixC14_15, + matrixC14_16, + matrixC14_17, + matrixC14_18, + matrixC14_19, + matrixC14_20, + matrixC14_21, + matrixC14_22, + matrixC14_23, + matrixC14_24, + matrixC14_25, + matrixC14_26, + matrixC14_27, + matrixC14_28, + matrixC14_29, + matrixC14_30, + matrixC14_31, + matrixC15_0, + matrixC15_1, + matrixC15_2, + matrixC15_3, + matrixC15_4, + matrixC15_5, + matrixC15_6, + matrixC15_7, + matrixC15_8, + matrixC15_9, + matrixC15_10, + matrixC15_11, + matrixC15_12, + matrixC15_13, + matrixC15_14, + matrixC15_15, + matrixC15_16, + matrixC15_17, + matrixC15_18, + matrixC15_19, + matrixC15_20, + matrixC15_21, + matrixC15_22, + matrixC15_23, + matrixC15_24, + matrixC15_25, + matrixC15_26, + matrixC15_27, + matrixC15_28, + matrixC15_29, + matrixC15_30, + matrixC15_31, + matrixC16_0, + matrixC16_1, + matrixC16_2, + matrixC16_3, + matrixC16_4, + matrixC16_5, + matrixC16_6, + matrixC16_7, + matrixC16_8, + matrixC16_9, + matrixC16_10, + matrixC16_11, + matrixC16_12, + matrixC16_13, + matrixC16_14, + matrixC16_15, + matrixC16_16, + matrixC16_17, + matrixC16_18, + matrixC16_19, + matrixC16_20, + matrixC16_21, + matrixC16_22, + matrixC16_23, + matrixC16_24, + matrixC16_25, + matrixC16_26, + matrixC16_27, + matrixC16_28, + matrixC16_29, + matrixC16_30, + matrixC16_31, + matrixC17_0, + matrixC17_1, + matrixC17_2, + matrixC17_3, + matrixC17_4, + matrixC17_5, + matrixC17_6, + matrixC17_7, + matrixC17_8, + matrixC17_9, + matrixC17_10, + matrixC17_11, + matrixC17_12, + matrixC17_13, + matrixC17_14, + matrixC17_15, + matrixC17_16, + matrixC17_17, + matrixC17_18, + matrixC17_19, + matrixC17_20, + matrixC17_21, + matrixC17_22, + matrixC17_23, + matrixC17_24, + matrixC17_25, + matrixC17_26, + matrixC17_27, + matrixC17_28, + matrixC17_29, + matrixC17_30, + matrixC17_31, + matrixC18_0, + matrixC18_1, + matrixC18_2, + matrixC18_3, + matrixC18_4, + matrixC18_5, + matrixC18_6, + matrixC18_7, + matrixC18_8, + matrixC18_9, + matrixC18_10, + matrixC18_11, + matrixC18_12, + matrixC18_13, + matrixC18_14, + matrixC18_15, + matrixC18_16, + matrixC18_17, + matrixC18_18, + matrixC18_19, + matrixC18_20, + matrixC18_21, + matrixC18_22, + matrixC18_23, + matrixC18_24, + matrixC18_25, + matrixC18_26, + matrixC18_27, + matrixC18_28, + matrixC18_29, + matrixC18_30, + matrixC18_31, + matrixC19_0, + matrixC19_1, + matrixC19_2, + matrixC19_3, + matrixC19_4, + matrixC19_5, + matrixC19_6, + matrixC19_7, + matrixC19_8, + matrixC19_9, + matrixC19_10, + matrixC19_11, + matrixC19_12, + matrixC19_13, + matrixC19_14, + matrixC19_15, + matrixC19_16, + matrixC19_17, + matrixC19_18, + matrixC19_19, + matrixC19_20, + matrixC19_21, + matrixC19_22, + matrixC19_23, + matrixC19_24, + matrixC19_25, + matrixC19_26, + matrixC19_27, + matrixC19_28, + matrixC19_29, + matrixC19_30, + matrixC19_31, + matrixC20_0, + matrixC20_1, + matrixC20_2, + matrixC20_3, + matrixC20_4, + matrixC20_5, + matrixC20_6, + matrixC20_7, + matrixC20_8, + matrixC20_9, + matrixC20_10, + matrixC20_11, + matrixC20_12, + matrixC20_13, + matrixC20_14, + matrixC20_15, + matrixC20_16, + matrixC20_17, + matrixC20_18, + matrixC20_19, + matrixC20_20, + matrixC20_21, + matrixC20_22, + matrixC20_23, + matrixC20_24, + matrixC20_25, + matrixC20_26, + matrixC20_27, + matrixC20_28, + matrixC20_29, + matrixC20_30, + matrixC20_31, + matrixC21_0, + matrixC21_1, + matrixC21_2, + matrixC21_3, + matrixC21_4, + matrixC21_5, + matrixC21_6, + matrixC21_7, + matrixC21_8, + matrixC21_9, + matrixC21_10, + matrixC21_11, + matrixC21_12, + matrixC21_13, + matrixC21_14, + matrixC21_15, + matrixC21_16, + matrixC21_17, + matrixC21_18, + matrixC21_19, + matrixC21_20, + matrixC21_21, + matrixC21_22, + matrixC21_23, + matrixC21_24, + matrixC21_25, + matrixC21_26, + matrixC21_27, + matrixC21_28, + matrixC21_29, + matrixC21_30, + matrixC21_31, + matrixC22_0, + matrixC22_1, + matrixC22_2, + matrixC22_3, + matrixC22_4, + matrixC22_5, + matrixC22_6, + matrixC22_7, + matrixC22_8, + matrixC22_9, + matrixC22_10, + matrixC22_11, + matrixC22_12, + matrixC22_13, + matrixC22_14, + matrixC22_15, + matrixC22_16, + matrixC22_17, + matrixC22_18, + matrixC22_19, + matrixC22_20, + matrixC22_21, + matrixC22_22, + matrixC22_23, + matrixC22_24, + matrixC22_25, + matrixC22_26, + matrixC22_27, + matrixC22_28, + matrixC22_29, + matrixC22_30, + matrixC22_31, + matrixC23_0, + matrixC23_1, + matrixC23_2, + matrixC23_3, + matrixC23_4, + matrixC23_5, + matrixC23_6, + matrixC23_7, + matrixC23_8, + matrixC23_9, + matrixC23_10, + matrixC23_11, + matrixC23_12, + matrixC23_13, + matrixC23_14, + matrixC23_15, + matrixC23_16, + matrixC23_17, + matrixC23_18, + matrixC23_19, + matrixC23_20, + matrixC23_21, + matrixC23_22, + matrixC23_23, + matrixC23_24, + matrixC23_25, + matrixC23_26, + matrixC23_27, + matrixC23_28, + matrixC23_29, + matrixC23_30, + matrixC23_31, + matrixC24_0, + matrixC24_1, + matrixC24_2, + matrixC24_3, + matrixC24_4, + matrixC24_5, + matrixC24_6, + matrixC24_7, + matrixC24_8, + matrixC24_9, + matrixC24_10, + matrixC24_11, + matrixC24_12, + matrixC24_13, + matrixC24_14, + matrixC24_15, + matrixC24_16, + matrixC24_17, + matrixC24_18, + matrixC24_19, + matrixC24_20, + matrixC24_21, + matrixC24_22, + matrixC24_23, + matrixC24_24, + matrixC24_25, + matrixC24_26, + matrixC24_27, + matrixC24_28, + matrixC24_29, + matrixC24_30, + matrixC24_31, + matrixC25_0, + matrixC25_1, + matrixC25_2, + matrixC25_3, + matrixC25_4, + matrixC25_5, + matrixC25_6, + matrixC25_7, + matrixC25_8, + matrixC25_9, + matrixC25_10, + matrixC25_11, + matrixC25_12, + matrixC25_13, + matrixC25_14, + matrixC25_15, + matrixC25_16, + matrixC25_17, + matrixC25_18, + matrixC25_19, + matrixC25_20, + matrixC25_21, + matrixC25_22, + matrixC25_23, + matrixC25_24, + matrixC25_25, + matrixC25_26, + matrixC25_27, + matrixC25_28, + matrixC25_29, + matrixC25_30, + matrixC25_31, + matrixC26_0, + matrixC26_1, + matrixC26_2, + matrixC26_3, + matrixC26_4, + matrixC26_5, + matrixC26_6, + matrixC26_7, + matrixC26_8, + matrixC26_9, + matrixC26_10, + matrixC26_11, + matrixC26_12, + matrixC26_13, + matrixC26_14, + matrixC26_15, + matrixC26_16, + matrixC26_17, + matrixC26_18, + matrixC26_19, + matrixC26_20, + matrixC26_21, + matrixC26_22, + matrixC26_23, + matrixC26_24, + matrixC26_25, + matrixC26_26, + matrixC26_27, + matrixC26_28, + matrixC26_29, + matrixC26_30, + matrixC26_31, + matrixC27_0, + matrixC27_1, + matrixC27_2, + matrixC27_3, + matrixC27_4, + matrixC27_5, + matrixC27_6, + matrixC27_7, + matrixC27_8, + matrixC27_9, + matrixC27_10, + matrixC27_11, + matrixC27_12, + matrixC27_13, + matrixC27_14, + matrixC27_15, + matrixC27_16, + matrixC27_17, + matrixC27_18, + matrixC27_19, + matrixC27_20, + matrixC27_21, + matrixC27_22, + matrixC27_23, + matrixC27_24, + matrixC27_25, + matrixC27_26, + matrixC27_27, + matrixC27_28, + matrixC27_29, + matrixC27_30, + matrixC27_31, + matrixC28_0, + matrixC28_1, + matrixC28_2, + matrixC28_3, + matrixC28_4, + matrixC28_5, + matrixC28_6, + matrixC28_7, + matrixC28_8, + matrixC28_9, + matrixC28_10, + matrixC28_11, + matrixC28_12, + matrixC28_13, + matrixC28_14, + matrixC28_15, + matrixC28_16, + matrixC28_17, + matrixC28_18, + matrixC28_19, + matrixC28_20, + matrixC28_21, + matrixC28_22, + matrixC28_23, + matrixC28_24, + matrixC28_25, + matrixC28_26, + matrixC28_27, + matrixC28_28, + matrixC28_29, + matrixC28_30, + matrixC28_31, + matrixC29_0, + matrixC29_1, + matrixC29_2, + matrixC29_3, + matrixC29_4, + matrixC29_5, + matrixC29_6, + matrixC29_7, + matrixC29_8, + matrixC29_9, + matrixC29_10, + matrixC29_11, + matrixC29_12, + matrixC29_13, + matrixC29_14, + matrixC29_15, + matrixC29_16, + matrixC29_17, + matrixC29_18, + matrixC29_19, + matrixC29_20, + matrixC29_21, + matrixC29_22, + matrixC29_23, + matrixC29_24, + matrixC29_25, + matrixC29_26, + matrixC29_27, + matrixC29_28, + matrixC29_29, + matrixC29_30, + matrixC29_31, + matrixC30_0, + matrixC30_1, + matrixC30_2, + matrixC30_3, + matrixC30_4, + matrixC30_5, + matrixC30_6, + matrixC30_7, + matrixC30_8, + matrixC30_9, + matrixC30_10, + matrixC30_11, + matrixC30_12, + matrixC30_13, + matrixC30_14, + matrixC30_15, + matrixC30_16, + matrixC30_17, + matrixC30_18, + matrixC30_19, + matrixC30_20, + matrixC30_21, + matrixC30_22, + matrixC30_23, + matrixC30_24, + matrixC30_25, + matrixC30_26, + matrixC30_27, + matrixC30_28, + matrixC30_29, + matrixC30_30, + matrixC30_31, + matrixC31_0, + matrixC31_1, + matrixC31_2, + matrixC31_3, + matrixC31_4, + matrixC31_5, + matrixC31_6, + matrixC31_7, + matrixC31_8, + matrixC31_9, + matrixC31_10, + matrixC31_11, + matrixC31_12, + matrixC31_13, + matrixC31_14, + matrixC31_15, + matrixC31_16, + matrixC31_17, + matrixC31_18, + matrixC31_19, + matrixC31_20, + matrixC31_21, + matrixC31_22, + matrixC31_23, + matrixC31_24, + matrixC31_25, + matrixC31_26, + matrixC31_27, + matrixC31_28, + matrixC31_29, + matrixC31_30, + matrixC31_31, + a_data_out, + b_data_out, + b_data_valid_ping, + b_data_valid_pong +); + +input clk; +input reset; +input pe_reset; +input b_data_sel; +input b_data_valid_ping; +input b_data_valid_pong; +input [`DWIDTH-1:0] a0; +input [`DWIDTH-1:0] a1; +input [`DWIDTH-1:0] a2; +input [`DWIDTH-1:0] a3; +input [`DWIDTH-1:0] a4; +input [`DWIDTH-1:0] a5; +input [`DWIDTH-1:0] a6; +input [`DWIDTH-1:0] a7; +input [`DWIDTH-1:0] a8; +input [`DWIDTH-1:0] a9; +input [`DWIDTH-1:0] a10; +input [`DWIDTH-1:0] a11; +input [`DWIDTH-1:0] a12; +input [`DWIDTH-1:0] a13; +input [`DWIDTH-1:0] a14; +input [`DWIDTH-1:0] a15; +input [`DWIDTH-1:0] a16; +input [`DWIDTH-1:0] a17; +input [`DWIDTH-1:0] a18; +input [`DWIDTH-1:0] a19; +input [`DWIDTH-1:0] a20; +input [`DWIDTH-1:0] a21; +input [`DWIDTH-1:0] a22; +input [`DWIDTH-1:0] a23; +input [`DWIDTH-1:0] a24; +input [`DWIDTH-1:0] a25; +input [`DWIDTH-1:0] a26; +input [`DWIDTH-1:0] a27; +input [`DWIDTH-1:0] a28; +input [`DWIDTH-1:0] a29; +input [`DWIDTH-1:0] a30; +input [`DWIDTH-1:0] a31; +input [`DWIDTH-1:0] b0; +input [`DWIDTH-1:0] b1; +input [`DWIDTH-1:0] b2; +input [`DWIDTH-1:0] b3; +input [`DWIDTH-1:0] b4; +input [`DWIDTH-1:0] b5; +input [`DWIDTH-1:0] b6; +input [`DWIDTH-1:0] b7; +input [`DWIDTH-1:0] b8; +input [`DWIDTH-1:0] b9; +input [`DWIDTH-1:0] b10; +input [`DWIDTH-1:0] b11; +input [`DWIDTH-1:0] b12; +input [`DWIDTH-1:0] b13; +input [`DWIDTH-1:0] b14; +input [`DWIDTH-1:0] b15; +input [`DWIDTH-1:0] b16; +input [`DWIDTH-1:0] b17; +input [`DWIDTH-1:0] b18; +input [`DWIDTH-1:0] b19; +input [`DWIDTH-1:0] b20; +input [`DWIDTH-1:0] b21; +input [`DWIDTH-1:0] b22; +input [`DWIDTH-1:0] b23; +input [`DWIDTH-1:0] b24; +input [`DWIDTH-1:0] b25; +input [`DWIDTH-1:0] b26; +input [`DWIDTH-1:0] b27; +input [`DWIDTH-1:0] b28; +input [`DWIDTH-1:0] b29; +input [`DWIDTH-1:0] b30; +input [`DWIDTH-1:0] b31; +input [`DWIDTH-1:0] c0; +input [`DWIDTH-1:0] c1; +input [`DWIDTH-1:0] c2; +input [`DWIDTH-1:0] c3; +input [`DWIDTH-1:0] c4; +input [`DWIDTH-1:0] c5; +input [`DWIDTH-1:0] c6; +input [`DWIDTH-1:0] c7; +input [`DWIDTH-1:0] c8; +input [`DWIDTH-1:0] c9; +input [`DWIDTH-1:0] c10; +input [`DWIDTH-1:0] c11; +input [`DWIDTH-1:0] c12; +input [`DWIDTH-1:0] c13; +input [`DWIDTH-1:0] c14; +input [`DWIDTH-1:0] c15; +input [`DWIDTH-1:0] c16; +input [`DWIDTH-1:0] c17; +input [`DWIDTH-1:0] c18; +input [`DWIDTH-1:0] c19; +input [`DWIDTH-1:0] c20; +input [`DWIDTH-1:0] c21; +input [`DWIDTH-1:0] c22; +input [`DWIDTH-1:0] c23; +input [`DWIDTH-1:0] c24; +input [`DWIDTH-1:0] c25; +input [`DWIDTH-1:0] c26; +input [`DWIDTH-1:0] c27; +input [`DWIDTH-1:0] c28; +input [`DWIDTH-1:0] c29; +input [`DWIDTH-1:0] c30; +input [`DWIDTH-1:0] c31; +output [`DWIDTH-1:0] matrixC0_0; +output [`DWIDTH-1:0] matrixC0_1; +output [`DWIDTH-1:0] matrixC0_2; +output [`DWIDTH-1:0] matrixC0_3; +output [`DWIDTH-1:0] matrixC0_4; +output [`DWIDTH-1:0] matrixC0_5; +output [`DWIDTH-1:0] matrixC0_6; +output [`DWIDTH-1:0] matrixC0_7; +output [`DWIDTH-1:0] matrixC0_8; +output [`DWIDTH-1:0] matrixC0_9; +output [`DWIDTH-1:0] matrixC0_10; +output [`DWIDTH-1:0] matrixC0_11; +output [`DWIDTH-1:0] matrixC0_12; +output [`DWIDTH-1:0] matrixC0_13; +output [`DWIDTH-1:0] matrixC0_14; +output [`DWIDTH-1:0] matrixC0_15; +output [`DWIDTH-1:0] matrixC0_16; +output [`DWIDTH-1:0] matrixC0_17; +output [`DWIDTH-1:0] matrixC0_18; +output [`DWIDTH-1:0] matrixC0_19; +output [`DWIDTH-1:0] matrixC0_20; +output [`DWIDTH-1:0] matrixC0_21; +output [`DWIDTH-1:0] matrixC0_22; +output [`DWIDTH-1:0] matrixC0_23; +output [`DWIDTH-1:0] matrixC0_24; +output [`DWIDTH-1:0] matrixC0_25; +output [`DWIDTH-1:0] matrixC0_26; +output [`DWIDTH-1:0] matrixC0_27; +output [`DWIDTH-1:0] matrixC0_28; +output [`DWIDTH-1:0] matrixC0_29; +output [`DWIDTH-1:0] matrixC0_30; +output [`DWIDTH-1:0] matrixC0_31; +output [`DWIDTH-1:0] matrixC1_0; +output [`DWIDTH-1:0] matrixC1_1; +output [`DWIDTH-1:0] matrixC1_2; +output [`DWIDTH-1:0] matrixC1_3; +output [`DWIDTH-1:0] matrixC1_4; +output [`DWIDTH-1:0] matrixC1_5; +output [`DWIDTH-1:0] matrixC1_6; +output [`DWIDTH-1:0] matrixC1_7; +output [`DWIDTH-1:0] matrixC1_8; +output [`DWIDTH-1:0] matrixC1_9; +output [`DWIDTH-1:0] matrixC1_10; +output [`DWIDTH-1:0] matrixC1_11; +output [`DWIDTH-1:0] matrixC1_12; +output [`DWIDTH-1:0] matrixC1_13; +output [`DWIDTH-1:0] matrixC1_14; +output [`DWIDTH-1:0] matrixC1_15; +output [`DWIDTH-1:0] matrixC1_16; +output [`DWIDTH-1:0] matrixC1_17; +output [`DWIDTH-1:0] matrixC1_18; +output [`DWIDTH-1:0] matrixC1_19; +output [`DWIDTH-1:0] matrixC1_20; +output [`DWIDTH-1:0] matrixC1_21; +output [`DWIDTH-1:0] matrixC1_22; +output [`DWIDTH-1:0] matrixC1_23; +output [`DWIDTH-1:0] matrixC1_24; +output [`DWIDTH-1:0] matrixC1_25; +output [`DWIDTH-1:0] matrixC1_26; +output [`DWIDTH-1:0] matrixC1_27; +output [`DWIDTH-1:0] matrixC1_28; +output [`DWIDTH-1:0] matrixC1_29; +output [`DWIDTH-1:0] matrixC1_30; +output [`DWIDTH-1:0] matrixC1_31; +output [`DWIDTH-1:0] matrixC2_0; +output [`DWIDTH-1:0] matrixC2_1; +output [`DWIDTH-1:0] matrixC2_2; +output [`DWIDTH-1:0] matrixC2_3; +output [`DWIDTH-1:0] matrixC2_4; +output [`DWIDTH-1:0] matrixC2_5; +output [`DWIDTH-1:0] matrixC2_6; +output [`DWIDTH-1:0] matrixC2_7; +output [`DWIDTH-1:0] matrixC2_8; +output [`DWIDTH-1:0] matrixC2_9; +output [`DWIDTH-1:0] matrixC2_10; +output [`DWIDTH-1:0] matrixC2_11; +output [`DWIDTH-1:0] matrixC2_12; +output [`DWIDTH-1:0] matrixC2_13; +output [`DWIDTH-1:0] matrixC2_14; +output [`DWIDTH-1:0] matrixC2_15; +output [`DWIDTH-1:0] matrixC2_16; +output [`DWIDTH-1:0] matrixC2_17; +output [`DWIDTH-1:0] matrixC2_18; +output [`DWIDTH-1:0] matrixC2_19; +output [`DWIDTH-1:0] matrixC2_20; +output [`DWIDTH-1:0] matrixC2_21; +output [`DWIDTH-1:0] matrixC2_22; +output [`DWIDTH-1:0] matrixC2_23; +output [`DWIDTH-1:0] matrixC2_24; +output [`DWIDTH-1:0] matrixC2_25; +output [`DWIDTH-1:0] matrixC2_26; +output [`DWIDTH-1:0] matrixC2_27; +output [`DWIDTH-1:0] matrixC2_28; +output [`DWIDTH-1:0] matrixC2_29; +output [`DWIDTH-1:0] matrixC2_30; +output [`DWIDTH-1:0] matrixC2_31; +output [`DWIDTH-1:0] matrixC3_0; +output [`DWIDTH-1:0] matrixC3_1; +output [`DWIDTH-1:0] matrixC3_2; +output [`DWIDTH-1:0] matrixC3_3; +output [`DWIDTH-1:0] matrixC3_4; +output [`DWIDTH-1:0] matrixC3_5; +output [`DWIDTH-1:0] matrixC3_6; +output [`DWIDTH-1:0] matrixC3_7; +output [`DWIDTH-1:0] matrixC3_8; +output [`DWIDTH-1:0] matrixC3_9; +output [`DWIDTH-1:0] matrixC3_10; +output [`DWIDTH-1:0] matrixC3_11; +output [`DWIDTH-1:0] matrixC3_12; +output [`DWIDTH-1:0] matrixC3_13; +output [`DWIDTH-1:0] matrixC3_14; +output [`DWIDTH-1:0] matrixC3_15; +output [`DWIDTH-1:0] matrixC3_16; +output [`DWIDTH-1:0] matrixC3_17; +output [`DWIDTH-1:0] matrixC3_18; +output [`DWIDTH-1:0] matrixC3_19; +output [`DWIDTH-1:0] matrixC3_20; +output [`DWIDTH-1:0] matrixC3_21; +output [`DWIDTH-1:0] matrixC3_22; +output [`DWIDTH-1:0] matrixC3_23; +output [`DWIDTH-1:0] matrixC3_24; +output [`DWIDTH-1:0] matrixC3_25; +output [`DWIDTH-1:0] matrixC3_26; +output [`DWIDTH-1:0] matrixC3_27; +output [`DWIDTH-1:0] matrixC3_28; +output [`DWIDTH-1:0] matrixC3_29; +output [`DWIDTH-1:0] matrixC3_30; +output [`DWIDTH-1:0] matrixC3_31; +output [`DWIDTH-1:0] matrixC4_0; +output [`DWIDTH-1:0] matrixC4_1; +output [`DWIDTH-1:0] matrixC4_2; +output [`DWIDTH-1:0] matrixC4_3; +output [`DWIDTH-1:0] matrixC4_4; +output [`DWIDTH-1:0] matrixC4_5; +output [`DWIDTH-1:0] matrixC4_6; +output [`DWIDTH-1:0] matrixC4_7; +output [`DWIDTH-1:0] matrixC4_8; +output [`DWIDTH-1:0] matrixC4_9; +output [`DWIDTH-1:0] matrixC4_10; +output [`DWIDTH-1:0] matrixC4_11; +output [`DWIDTH-1:0] matrixC4_12; +output [`DWIDTH-1:0] matrixC4_13; +output [`DWIDTH-1:0] matrixC4_14; +output [`DWIDTH-1:0] matrixC4_15; +output [`DWIDTH-1:0] matrixC4_16; +output [`DWIDTH-1:0] matrixC4_17; +output [`DWIDTH-1:0] matrixC4_18; +output [`DWIDTH-1:0] matrixC4_19; +output [`DWIDTH-1:0] matrixC4_20; +output [`DWIDTH-1:0] matrixC4_21; +output [`DWIDTH-1:0] matrixC4_22; +output [`DWIDTH-1:0] matrixC4_23; +output [`DWIDTH-1:0] matrixC4_24; +output [`DWIDTH-1:0] matrixC4_25; +output [`DWIDTH-1:0] matrixC4_26; +output [`DWIDTH-1:0] matrixC4_27; +output [`DWIDTH-1:0] matrixC4_28; +output [`DWIDTH-1:0] matrixC4_29; +output [`DWIDTH-1:0] matrixC4_30; +output [`DWIDTH-1:0] matrixC4_31; +output [`DWIDTH-1:0] matrixC5_0; +output [`DWIDTH-1:0] matrixC5_1; +output [`DWIDTH-1:0] matrixC5_2; +output [`DWIDTH-1:0] matrixC5_3; +output [`DWIDTH-1:0] matrixC5_4; +output [`DWIDTH-1:0] matrixC5_5; +output [`DWIDTH-1:0] matrixC5_6; +output [`DWIDTH-1:0] matrixC5_7; +output [`DWIDTH-1:0] matrixC5_8; +output [`DWIDTH-1:0] matrixC5_9; +output [`DWIDTH-1:0] matrixC5_10; +output [`DWIDTH-1:0] matrixC5_11; +output [`DWIDTH-1:0] matrixC5_12; +output [`DWIDTH-1:0] matrixC5_13; +output [`DWIDTH-1:0] matrixC5_14; +output [`DWIDTH-1:0] matrixC5_15; +output [`DWIDTH-1:0] matrixC5_16; +output [`DWIDTH-1:0] matrixC5_17; +output [`DWIDTH-1:0] matrixC5_18; +output [`DWIDTH-1:0] matrixC5_19; +output [`DWIDTH-1:0] matrixC5_20; +output [`DWIDTH-1:0] matrixC5_21; +output [`DWIDTH-1:0] matrixC5_22; +output [`DWIDTH-1:0] matrixC5_23; +output [`DWIDTH-1:0] matrixC5_24; +output [`DWIDTH-1:0] matrixC5_25; +output [`DWIDTH-1:0] matrixC5_26; +output [`DWIDTH-1:0] matrixC5_27; +output [`DWIDTH-1:0] matrixC5_28; +output [`DWIDTH-1:0] matrixC5_29; +output [`DWIDTH-1:0] matrixC5_30; +output [`DWIDTH-1:0] matrixC5_31; +output [`DWIDTH-1:0] matrixC6_0; +output [`DWIDTH-1:0] matrixC6_1; +output [`DWIDTH-1:0] matrixC6_2; +output [`DWIDTH-1:0] matrixC6_3; +output [`DWIDTH-1:0] matrixC6_4; +output [`DWIDTH-1:0] matrixC6_5; +output [`DWIDTH-1:0] matrixC6_6; +output [`DWIDTH-1:0] matrixC6_7; +output [`DWIDTH-1:0] matrixC6_8; +output [`DWIDTH-1:0] matrixC6_9; +output [`DWIDTH-1:0] matrixC6_10; +output [`DWIDTH-1:0] matrixC6_11; +output [`DWIDTH-1:0] matrixC6_12; +output [`DWIDTH-1:0] matrixC6_13; +output [`DWIDTH-1:0] matrixC6_14; +output [`DWIDTH-1:0] matrixC6_15; +output [`DWIDTH-1:0] matrixC6_16; +output [`DWIDTH-1:0] matrixC6_17; +output [`DWIDTH-1:0] matrixC6_18; +output [`DWIDTH-1:0] matrixC6_19; +output [`DWIDTH-1:0] matrixC6_20; +output [`DWIDTH-1:0] matrixC6_21; +output [`DWIDTH-1:0] matrixC6_22; +output [`DWIDTH-1:0] matrixC6_23; +output [`DWIDTH-1:0] matrixC6_24; +output [`DWIDTH-1:0] matrixC6_25; +output [`DWIDTH-1:0] matrixC6_26; +output [`DWIDTH-1:0] matrixC6_27; +output [`DWIDTH-1:0] matrixC6_28; +output [`DWIDTH-1:0] matrixC6_29; +output [`DWIDTH-1:0] matrixC6_30; +output [`DWIDTH-1:0] matrixC6_31; +output [`DWIDTH-1:0] matrixC7_0; +output [`DWIDTH-1:0] matrixC7_1; +output [`DWIDTH-1:0] matrixC7_2; +output [`DWIDTH-1:0] matrixC7_3; +output [`DWIDTH-1:0] matrixC7_4; +output [`DWIDTH-1:0] matrixC7_5; +output [`DWIDTH-1:0] matrixC7_6; +output [`DWIDTH-1:0] matrixC7_7; +output [`DWIDTH-1:0] matrixC7_8; +output [`DWIDTH-1:0] matrixC7_9; +output [`DWIDTH-1:0] matrixC7_10; +output [`DWIDTH-1:0] matrixC7_11; +output [`DWIDTH-1:0] matrixC7_12; +output [`DWIDTH-1:0] matrixC7_13; +output [`DWIDTH-1:0] matrixC7_14; +output [`DWIDTH-1:0] matrixC7_15; +output [`DWIDTH-1:0] matrixC7_16; +output [`DWIDTH-1:0] matrixC7_17; +output [`DWIDTH-1:0] matrixC7_18; +output [`DWIDTH-1:0] matrixC7_19; +output [`DWIDTH-1:0] matrixC7_20; +output [`DWIDTH-1:0] matrixC7_21; +output [`DWIDTH-1:0] matrixC7_22; +output [`DWIDTH-1:0] matrixC7_23; +output [`DWIDTH-1:0] matrixC7_24; +output [`DWIDTH-1:0] matrixC7_25; +output [`DWIDTH-1:0] matrixC7_26; +output [`DWIDTH-1:0] matrixC7_27; +output [`DWIDTH-1:0] matrixC7_28; +output [`DWIDTH-1:0] matrixC7_29; +output [`DWIDTH-1:0] matrixC7_30; +output [`DWIDTH-1:0] matrixC7_31; +output [`DWIDTH-1:0] matrixC8_0; +output [`DWIDTH-1:0] matrixC8_1; +output [`DWIDTH-1:0] matrixC8_2; +output [`DWIDTH-1:0] matrixC8_3; +output [`DWIDTH-1:0] matrixC8_4; +output [`DWIDTH-1:0] matrixC8_5; +output [`DWIDTH-1:0] matrixC8_6; +output [`DWIDTH-1:0] matrixC8_7; +output [`DWIDTH-1:0] matrixC8_8; +output [`DWIDTH-1:0] matrixC8_9; +output [`DWIDTH-1:0] matrixC8_10; +output [`DWIDTH-1:0] matrixC8_11; +output [`DWIDTH-1:0] matrixC8_12; +output [`DWIDTH-1:0] matrixC8_13; +output [`DWIDTH-1:0] matrixC8_14; +output [`DWIDTH-1:0] matrixC8_15; +output [`DWIDTH-1:0] matrixC8_16; +output [`DWIDTH-1:0] matrixC8_17; +output [`DWIDTH-1:0] matrixC8_18; +output [`DWIDTH-1:0] matrixC8_19; +output [`DWIDTH-1:0] matrixC8_20; +output [`DWIDTH-1:0] matrixC8_21; +output [`DWIDTH-1:0] matrixC8_22; +output [`DWIDTH-1:0] matrixC8_23; +output [`DWIDTH-1:0] matrixC8_24; +output [`DWIDTH-1:0] matrixC8_25; +output [`DWIDTH-1:0] matrixC8_26; +output [`DWIDTH-1:0] matrixC8_27; +output [`DWIDTH-1:0] matrixC8_28; +output [`DWIDTH-1:0] matrixC8_29; +output [`DWIDTH-1:0] matrixC8_30; +output [`DWIDTH-1:0] matrixC8_31; +output [`DWIDTH-1:0] matrixC9_0; +output [`DWIDTH-1:0] matrixC9_1; +output [`DWIDTH-1:0] matrixC9_2; +output [`DWIDTH-1:0] matrixC9_3; +output [`DWIDTH-1:0] matrixC9_4; +output [`DWIDTH-1:0] matrixC9_5; +output [`DWIDTH-1:0] matrixC9_6; +output [`DWIDTH-1:0] matrixC9_7; +output [`DWIDTH-1:0] matrixC9_8; +output [`DWIDTH-1:0] matrixC9_9; +output [`DWIDTH-1:0] matrixC9_10; +output [`DWIDTH-1:0] matrixC9_11; +output [`DWIDTH-1:0] matrixC9_12; +output [`DWIDTH-1:0] matrixC9_13; +output [`DWIDTH-1:0] matrixC9_14; +output [`DWIDTH-1:0] matrixC9_15; +output [`DWIDTH-1:0] matrixC9_16; +output [`DWIDTH-1:0] matrixC9_17; +output [`DWIDTH-1:0] matrixC9_18; +output [`DWIDTH-1:0] matrixC9_19; +output [`DWIDTH-1:0] matrixC9_20; +output [`DWIDTH-1:0] matrixC9_21; +output [`DWIDTH-1:0] matrixC9_22; +output [`DWIDTH-1:0] matrixC9_23; +output [`DWIDTH-1:0] matrixC9_24; +output [`DWIDTH-1:0] matrixC9_25; +output [`DWIDTH-1:0] matrixC9_26; +output [`DWIDTH-1:0] matrixC9_27; +output [`DWIDTH-1:0] matrixC9_28; +output [`DWIDTH-1:0] matrixC9_29; +output [`DWIDTH-1:0] matrixC9_30; +output [`DWIDTH-1:0] matrixC9_31; +output [`DWIDTH-1:0] matrixC10_0; +output [`DWIDTH-1:0] matrixC10_1; +output [`DWIDTH-1:0] matrixC10_2; +output [`DWIDTH-1:0] matrixC10_3; +output [`DWIDTH-1:0] matrixC10_4; +output [`DWIDTH-1:0] matrixC10_5; +output [`DWIDTH-1:0] matrixC10_6; +output [`DWIDTH-1:0] matrixC10_7; +output [`DWIDTH-1:0] matrixC10_8; +output [`DWIDTH-1:0] matrixC10_9; +output [`DWIDTH-1:0] matrixC10_10; +output [`DWIDTH-1:0] matrixC10_11; +output [`DWIDTH-1:0] matrixC10_12; +output [`DWIDTH-1:0] matrixC10_13; +output [`DWIDTH-1:0] matrixC10_14; +output [`DWIDTH-1:0] matrixC10_15; +output [`DWIDTH-1:0] matrixC10_16; +output [`DWIDTH-1:0] matrixC10_17; +output [`DWIDTH-1:0] matrixC10_18; +output [`DWIDTH-1:0] matrixC10_19; +output [`DWIDTH-1:0] matrixC10_20; +output [`DWIDTH-1:0] matrixC10_21; +output [`DWIDTH-1:0] matrixC10_22; +output [`DWIDTH-1:0] matrixC10_23; +output [`DWIDTH-1:0] matrixC10_24; +output [`DWIDTH-1:0] matrixC10_25; +output [`DWIDTH-1:0] matrixC10_26; +output [`DWIDTH-1:0] matrixC10_27; +output [`DWIDTH-1:0] matrixC10_28; +output [`DWIDTH-1:0] matrixC10_29; +output [`DWIDTH-1:0] matrixC10_30; +output [`DWIDTH-1:0] matrixC10_31; +output [`DWIDTH-1:0] matrixC11_0; +output [`DWIDTH-1:0] matrixC11_1; +output [`DWIDTH-1:0] matrixC11_2; +output [`DWIDTH-1:0] matrixC11_3; +output [`DWIDTH-1:0] matrixC11_4; +output [`DWIDTH-1:0] matrixC11_5; +output [`DWIDTH-1:0] matrixC11_6; +output [`DWIDTH-1:0] matrixC11_7; +output [`DWIDTH-1:0] matrixC11_8; +output [`DWIDTH-1:0] matrixC11_9; +output [`DWIDTH-1:0] matrixC11_10; +output [`DWIDTH-1:0] matrixC11_11; +output [`DWIDTH-1:0] matrixC11_12; +output [`DWIDTH-1:0] matrixC11_13; +output [`DWIDTH-1:0] matrixC11_14; +output [`DWIDTH-1:0] matrixC11_15; +output [`DWIDTH-1:0] matrixC11_16; +output [`DWIDTH-1:0] matrixC11_17; +output [`DWIDTH-1:0] matrixC11_18; +output [`DWIDTH-1:0] matrixC11_19; +output [`DWIDTH-1:0] matrixC11_20; +output [`DWIDTH-1:0] matrixC11_21; +output [`DWIDTH-1:0] matrixC11_22; +output [`DWIDTH-1:0] matrixC11_23; +output [`DWIDTH-1:0] matrixC11_24; +output [`DWIDTH-1:0] matrixC11_25; +output [`DWIDTH-1:0] matrixC11_26; +output [`DWIDTH-1:0] matrixC11_27; +output [`DWIDTH-1:0] matrixC11_28; +output [`DWIDTH-1:0] matrixC11_29; +output [`DWIDTH-1:0] matrixC11_30; +output [`DWIDTH-1:0] matrixC11_31; +output [`DWIDTH-1:0] matrixC12_0; +output [`DWIDTH-1:0] matrixC12_1; +output [`DWIDTH-1:0] matrixC12_2; +output [`DWIDTH-1:0] matrixC12_3; +output [`DWIDTH-1:0] matrixC12_4; +output [`DWIDTH-1:0] matrixC12_5; +output [`DWIDTH-1:0] matrixC12_6; +output [`DWIDTH-1:0] matrixC12_7; +output [`DWIDTH-1:0] matrixC12_8; +output [`DWIDTH-1:0] matrixC12_9; +output [`DWIDTH-1:0] matrixC12_10; +output [`DWIDTH-1:0] matrixC12_11; +output [`DWIDTH-1:0] matrixC12_12; +output [`DWIDTH-1:0] matrixC12_13; +output [`DWIDTH-1:0] matrixC12_14; +output [`DWIDTH-1:0] matrixC12_15; +output [`DWIDTH-1:0] matrixC12_16; +output [`DWIDTH-1:0] matrixC12_17; +output [`DWIDTH-1:0] matrixC12_18; +output [`DWIDTH-1:0] matrixC12_19; +output [`DWIDTH-1:0] matrixC12_20; +output [`DWIDTH-1:0] matrixC12_21; +output [`DWIDTH-1:0] matrixC12_22; +output [`DWIDTH-1:0] matrixC12_23; +output [`DWIDTH-1:0] matrixC12_24; +output [`DWIDTH-1:0] matrixC12_25; +output [`DWIDTH-1:0] matrixC12_26; +output [`DWIDTH-1:0] matrixC12_27; +output [`DWIDTH-1:0] matrixC12_28; +output [`DWIDTH-1:0] matrixC12_29; +output [`DWIDTH-1:0] matrixC12_30; +output [`DWIDTH-1:0] matrixC12_31; +output [`DWIDTH-1:0] matrixC13_0; +output [`DWIDTH-1:0] matrixC13_1; +output [`DWIDTH-1:0] matrixC13_2; +output [`DWIDTH-1:0] matrixC13_3; +output [`DWIDTH-1:0] matrixC13_4; +output [`DWIDTH-1:0] matrixC13_5; +output [`DWIDTH-1:0] matrixC13_6; +output [`DWIDTH-1:0] matrixC13_7; +output [`DWIDTH-1:0] matrixC13_8; +output [`DWIDTH-1:0] matrixC13_9; +output [`DWIDTH-1:0] matrixC13_10; +output [`DWIDTH-1:0] matrixC13_11; +output [`DWIDTH-1:0] matrixC13_12; +output [`DWIDTH-1:0] matrixC13_13; +output [`DWIDTH-1:0] matrixC13_14; +output [`DWIDTH-1:0] matrixC13_15; +output [`DWIDTH-1:0] matrixC13_16; +output [`DWIDTH-1:0] matrixC13_17; +output [`DWIDTH-1:0] matrixC13_18; +output [`DWIDTH-1:0] matrixC13_19; +output [`DWIDTH-1:0] matrixC13_20; +output [`DWIDTH-1:0] matrixC13_21; +output [`DWIDTH-1:0] matrixC13_22; +output [`DWIDTH-1:0] matrixC13_23; +output [`DWIDTH-1:0] matrixC13_24; +output [`DWIDTH-1:0] matrixC13_25; +output [`DWIDTH-1:0] matrixC13_26; +output [`DWIDTH-1:0] matrixC13_27; +output [`DWIDTH-1:0] matrixC13_28; +output [`DWIDTH-1:0] matrixC13_29; +output [`DWIDTH-1:0] matrixC13_30; +output [`DWIDTH-1:0] matrixC13_31; +output [`DWIDTH-1:0] matrixC14_0; +output [`DWIDTH-1:0] matrixC14_1; +output [`DWIDTH-1:0] matrixC14_2; +output [`DWIDTH-1:0] matrixC14_3; +output [`DWIDTH-1:0] matrixC14_4; +output [`DWIDTH-1:0] matrixC14_5; +output [`DWIDTH-1:0] matrixC14_6; +output [`DWIDTH-1:0] matrixC14_7; +output [`DWIDTH-1:0] matrixC14_8; +output [`DWIDTH-1:0] matrixC14_9; +output [`DWIDTH-1:0] matrixC14_10; +output [`DWIDTH-1:0] matrixC14_11; +output [`DWIDTH-1:0] matrixC14_12; +output [`DWIDTH-1:0] matrixC14_13; +output [`DWIDTH-1:0] matrixC14_14; +output [`DWIDTH-1:0] matrixC14_15; +output [`DWIDTH-1:0] matrixC14_16; +output [`DWIDTH-1:0] matrixC14_17; +output [`DWIDTH-1:0] matrixC14_18; +output [`DWIDTH-1:0] matrixC14_19; +output [`DWIDTH-1:0] matrixC14_20; +output [`DWIDTH-1:0] matrixC14_21; +output [`DWIDTH-1:0] matrixC14_22; +output [`DWIDTH-1:0] matrixC14_23; +output [`DWIDTH-1:0] matrixC14_24; +output [`DWIDTH-1:0] matrixC14_25; +output [`DWIDTH-1:0] matrixC14_26; +output [`DWIDTH-1:0] matrixC14_27; +output [`DWIDTH-1:0] matrixC14_28; +output [`DWIDTH-1:0] matrixC14_29; +output [`DWIDTH-1:0] matrixC14_30; +output [`DWIDTH-1:0] matrixC14_31; +output [`DWIDTH-1:0] matrixC15_0; +output [`DWIDTH-1:0] matrixC15_1; +output [`DWIDTH-1:0] matrixC15_2; +output [`DWIDTH-1:0] matrixC15_3; +output [`DWIDTH-1:0] matrixC15_4; +output [`DWIDTH-1:0] matrixC15_5; +output [`DWIDTH-1:0] matrixC15_6; +output [`DWIDTH-1:0] matrixC15_7; +output [`DWIDTH-1:0] matrixC15_8; +output [`DWIDTH-1:0] matrixC15_9; +output [`DWIDTH-1:0] matrixC15_10; +output [`DWIDTH-1:0] matrixC15_11; +output [`DWIDTH-1:0] matrixC15_12; +output [`DWIDTH-1:0] matrixC15_13; +output [`DWIDTH-1:0] matrixC15_14; +output [`DWIDTH-1:0] matrixC15_15; +output [`DWIDTH-1:0] matrixC15_16; +output [`DWIDTH-1:0] matrixC15_17; +output [`DWIDTH-1:0] matrixC15_18; +output [`DWIDTH-1:0] matrixC15_19; +output [`DWIDTH-1:0] matrixC15_20; +output [`DWIDTH-1:0] matrixC15_21; +output [`DWIDTH-1:0] matrixC15_22; +output [`DWIDTH-1:0] matrixC15_23; +output [`DWIDTH-1:0] matrixC15_24; +output [`DWIDTH-1:0] matrixC15_25; +output [`DWIDTH-1:0] matrixC15_26; +output [`DWIDTH-1:0] matrixC15_27; +output [`DWIDTH-1:0] matrixC15_28; +output [`DWIDTH-1:0] matrixC15_29; +output [`DWIDTH-1:0] matrixC15_30; +output [`DWIDTH-1:0] matrixC15_31; +output [`DWIDTH-1:0] matrixC16_0; +output [`DWIDTH-1:0] matrixC16_1; +output [`DWIDTH-1:0] matrixC16_2; +output [`DWIDTH-1:0] matrixC16_3; +output [`DWIDTH-1:0] matrixC16_4; +output [`DWIDTH-1:0] matrixC16_5; +output [`DWIDTH-1:0] matrixC16_6; +output [`DWIDTH-1:0] matrixC16_7; +output [`DWIDTH-1:0] matrixC16_8; +output [`DWIDTH-1:0] matrixC16_9; +output [`DWIDTH-1:0] matrixC16_10; +output [`DWIDTH-1:0] matrixC16_11; +output [`DWIDTH-1:0] matrixC16_12; +output [`DWIDTH-1:0] matrixC16_13; +output [`DWIDTH-1:0] matrixC16_14; +output [`DWIDTH-1:0] matrixC16_15; +output [`DWIDTH-1:0] matrixC16_16; +output [`DWIDTH-1:0] matrixC16_17; +output [`DWIDTH-1:0] matrixC16_18; +output [`DWIDTH-1:0] matrixC16_19; +output [`DWIDTH-1:0] matrixC16_20; +output [`DWIDTH-1:0] matrixC16_21; +output [`DWIDTH-1:0] matrixC16_22; +output [`DWIDTH-1:0] matrixC16_23; +output [`DWIDTH-1:0] matrixC16_24; +output [`DWIDTH-1:0] matrixC16_25; +output [`DWIDTH-1:0] matrixC16_26; +output [`DWIDTH-1:0] matrixC16_27; +output [`DWIDTH-1:0] matrixC16_28; +output [`DWIDTH-1:0] matrixC16_29; +output [`DWIDTH-1:0] matrixC16_30; +output [`DWIDTH-1:0] matrixC16_31; +output [`DWIDTH-1:0] matrixC17_0; +output [`DWIDTH-1:0] matrixC17_1; +output [`DWIDTH-1:0] matrixC17_2; +output [`DWIDTH-1:0] matrixC17_3; +output [`DWIDTH-1:0] matrixC17_4; +output [`DWIDTH-1:0] matrixC17_5; +output [`DWIDTH-1:0] matrixC17_6; +output [`DWIDTH-1:0] matrixC17_7; +output [`DWIDTH-1:0] matrixC17_8; +output [`DWIDTH-1:0] matrixC17_9; +output [`DWIDTH-1:0] matrixC17_10; +output [`DWIDTH-1:0] matrixC17_11; +output [`DWIDTH-1:0] matrixC17_12; +output [`DWIDTH-1:0] matrixC17_13; +output [`DWIDTH-1:0] matrixC17_14; +output [`DWIDTH-1:0] matrixC17_15; +output [`DWIDTH-1:0] matrixC17_16; +output [`DWIDTH-1:0] matrixC17_17; +output [`DWIDTH-1:0] matrixC17_18; +output [`DWIDTH-1:0] matrixC17_19; +output [`DWIDTH-1:0] matrixC17_20; +output [`DWIDTH-1:0] matrixC17_21; +output [`DWIDTH-1:0] matrixC17_22; +output [`DWIDTH-1:0] matrixC17_23; +output [`DWIDTH-1:0] matrixC17_24; +output [`DWIDTH-1:0] matrixC17_25; +output [`DWIDTH-1:0] matrixC17_26; +output [`DWIDTH-1:0] matrixC17_27; +output [`DWIDTH-1:0] matrixC17_28; +output [`DWIDTH-1:0] matrixC17_29; +output [`DWIDTH-1:0] matrixC17_30; +output [`DWIDTH-1:0] matrixC17_31; +output [`DWIDTH-1:0] matrixC18_0; +output [`DWIDTH-1:0] matrixC18_1; +output [`DWIDTH-1:0] matrixC18_2; +output [`DWIDTH-1:0] matrixC18_3; +output [`DWIDTH-1:0] matrixC18_4; +output [`DWIDTH-1:0] matrixC18_5; +output [`DWIDTH-1:0] matrixC18_6; +output [`DWIDTH-1:0] matrixC18_7; +output [`DWIDTH-1:0] matrixC18_8; +output [`DWIDTH-1:0] matrixC18_9; +output [`DWIDTH-1:0] matrixC18_10; +output [`DWIDTH-1:0] matrixC18_11; +output [`DWIDTH-1:0] matrixC18_12; +output [`DWIDTH-1:0] matrixC18_13; +output [`DWIDTH-1:0] matrixC18_14; +output [`DWIDTH-1:0] matrixC18_15; +output [`DWIDTH-1:0] matrixC18_16; +output [`DWIDTH-1:0] matrixC18_17; +output [`DWIDTH-1:0] matrixC18_18; +output [`DWIDTH-1:0] matrixC18_19; +output [`DWIDTH-1:0] matrixC18_20; +output [`DWIDTH-1:0] matrixC18_21; +output [`DWIDTH-1:0] matrixC18_22; +output [`DWIDTH-1:0] matrixC18_23; +output [`DWIDTH-1:0] matrixC18_24; +output [`DWIDTH-1:0] matrixC18_25; +output [`DWIDTH-1:0] matrixC18_26; +output [`DWIDTH-1:0] matrixC18_27; +output [`DWIDTH-1:0] matrixC18_28; +output [`DWIDTH-1:0] matrixC18_29; +output [`DWIDTH-1:0] matrixC18_30; +output [`DWIDTH-1:0] matrixC18_31; +output [`DWIDTH-1:0] matrixC19_0; +output [`DWIDTH-1:0] matrixC19_1; +output [`DWIDTH-1:0] matrixC19_2; +output [`DWIDTH-1:0] matrixC19_3; +output [`DWIDTH-1:0] matrixC19_4; +output [`DWIDTH-1:0] matrixC19_5; +output [`DWIDTH-1:0] matrixC19_6; +output [`DWIDTH-1:0] matrixC19_7; +output [`DWIDTH-1:0] matrixC19_8; +output [`DWIDTH-1:0] matrixC19_9; +output [`DWIDTH-1:0] matrixC19_10; +output [`DWIDTH-1:0] matrixC19_11; +output [`DWIDTH-1:0] matrixC19_12; +output [`DWIDTH-1:0] matrixC19_13; +output [`DWIDTH-1:0] matrixC19_14; +output [`DWIDTH-1:0] matrixC19_15; +output [`DWIDTH-1:0] matrixC19_16; +output [`DWIDTH-1:0] matrixC19_17; +output [`DWIDTH-1:0] matrixC19_18; +output [`DWIDTH-1:0] matrixC19_19; +output [`DWIDTH-1:0] matrixC19_20; +output [`DWIDTH-1:0] matrixC19_21; +output [`DWIDTH-1:0] matrixC19_22; +output [`DWIDTH-1:0] matrixC19_23; +output [`DWIDTH-1:0] matrixC19_24; +output [`DWIDTH-1:0] matrixC19_25; +output [`DWIDTH-1:0] matrixC19_26; +output [`DWIDTH-1:0] matrixC19_27; +output [`DWIDTH-1:0] matrixC19_28; +output [`DWIDTH-1:0] matrixC19_29; +output [`DWIDTH-1:0] matrixC19_30; +output [`DWIDTH-1:0] matrixC19_31; +output [`DWIDTH-1:0] matrixC20_0; +output [`DWIDTH-1:0] matrixC20_1; +output [`DWIDTH-1:0] matrixC20_2; +output [`DWIDTH-1:0] matrixC20_3; +output [`DWIDTH-1:0] matrixC20_4; +output [`DWIDTH-1:0] matrixC20_5; +output [`DWIDTH-1:0] matrixC20_6; +output [`DWIDTH-1:0] matrixC20_7; +output [`DWIDTH-1:0] matrixC20_8; +output [`DWIDTH-1:0] matrixC20_9; +output [`DWIDTH-1:0] matrixC20_10; +output [`DWIDTH-1:0] matrixC20_11; +output [`DWIDTH-1:0] matrixC20_12; +output [`DWIDTH-1:0] matrixC20_13; +output [`DWIDTH-1:0] matrixC20_14; +output [`DWIDTH-1:0] matrixC20_15; +output [`DWIDTH-1:0] matrixC20_16; +output [`DWIDTH-1:0] matrixC20_17; +output [`DWIDTH-1:0] matrixC20_18; +output [`DWIDTH-1:0] matrixC20_19; +output [`DWIDTH-1:0] matrixC20_20; +output [`DWIDTH-1:0] matrixC20_21; +output [`DWIDTH-1:0] matrixC20_22; +output [`DWIDTH-1:0] matrixC20_23; +output [`DWIDTH-1:0] matrixC20_24; +output [`DWIDTH-1:0] matrixC20_25; +output [`DWIDTH-1:0] matrixC20_26; +output [`DWIDTH-1:0] matrixC20_27; +output [`DWIDTH-1:0] matrixC20_28; +output [`DWIDTH-1:0] matrixC20_29; +output [`DWIDTH-1:0] matrixC20_30; +output [`DWIDTH-1:0] matrixC20_31; +output [`DWIDTH-1:0] matrixC21_0; +output [`DWIDTH-1:0] matrixC21_1; +output [`DWIDTH-1:0] matrixC21_2; +output [`DWIDTH-1:0] matrixC21_3; +output [`DWIDTH-1:0] matrixC21_4; +output [`DWIDTH-1:0] matrixC21_5; +output [`DWIDTH-1:0] matrixC21_6; +output [`DWIDTH-1:0] matrixC21_7; +output [`DWIDTH-1:0] matrixC21_8; +output [`DWIDTH-1:0] matrixC21_9; +output [`DWIDTH-1:0] matrixC21_10; +output [`DWIDTH-1:0] matrixC21_11; +output [`DWIDTH-1:0] matrixC21_12; +output [`DWIDTH-1:0] matrixC21_13; +output [`DWIDTH-1:0] matrixC21_14; +output [`DWIDTH-1:0] matrixC21_15; +output [`DWIDTH-1:0] matrixC21_16; +output [`DWIDTH-1:0] matrixC21_17; +output [`DWIDTH-1:0] matrixC21_18; +output [`DWIDTH-1:0] matrixC21_19; +output [`DWIDTH-1:0] matrixC21_20; +output [`DWIDTH-1:0] matrixC21_21; +output [`DWIDTH-1:0] matrixC21_22; +output [`DWIDTH-1:0] matrixC21_23; +output [`DWIDTH-1:0] matrixC21_24; +output [`DWIDTH-1:0] matrixC21_25; +output [`DWIDTH-1:0] matrixC21_26; +output [`DWIDTH-1:0] matrixC21_27; +output [`DWIDTH-1:0] matrixC21_28; +output [`DWIDTH-1:0] matrixC21_29; +output [`DWIDTH-1:0] matrixC21_30; +output [`DWIDTH-1:0] matrixC21_31; +output [`DWIDTH-1:0] matrixC22_0; +output [`DWIDTH-1:0] matrixC22_1; +output [`DWIDTH-1:0] matrixC22_2; +output [`DWIDTH-1:0] matrixC22_3; +output [`DWIDTH-1:0] matrixC22_4; +output [`DWIDTH-1:0] matrixC22_5; +output [`DWIDTH-1:0] matrixC22_6; +output [`DWIDTH-1:0] matrixC22_7; +output [`DWIDTH-1:0] matrixC22_8; +output [`DWIDTH-1:0] matrixC22_9; +output [`DWIDTH-1:0] matrixC22_10; +output [`DWIDTH-1:0] matrixC22_11; +output [`DWIDTH-1:0] matrixC22_12; +output [`DWIDTH-1:0] matrixC22_13; +output [`DWIDTH-1:0] matrixC22_14; +output [`DWIDTH-1:0] matrixC22_15; +output [`DWIDTH-1:0] matrixC22_16; +output [`DWIDTH-1:0] matrixC22_17; +output [`DWIDTH-1:0] matrixC22_18; +output [`DWIDTH-1:0] matrixC22_19; +output [`DWIDTH-1:0] matrixC22_20; +output [`DWIDTH-1:0] matrixC22_21; +output [`DWIDTH-1:0] matrixC22_22; +output [`DWIDTH-1:0] matrixC22_23; +output [`DWIDTH-1:0] matrixC22_24; +output [`DWIDTH-1:0] matrixC22_25; +output [`DWIDTH-1:0] matrixC22_26; +output [`DWIDTH-1:0] matrixC22_27; +output [`DWIDTH-1:0] matrixC22_28; +output [`DWIDTH-1:0] matrixC22_29; +output [`DWIDTH-1:0] matrixC22_30; +output [`DWIDTH-1:0] matrixC22_31; +output [`DWIDTH-1:0] matrixC23_0; +output [`DWIDTH-1:0] matrixC23_1; +output [`DWIDTH-1:0] matrixC23_2; +output [`DWIDTH-1:0] matrixC23_3; +output [`DWIDTH-1:0] matrixC23_4; +output [`DWIDTH-1:0] matrixC23_5; +output [`DWIDTH-1:0] matrixC23_6; +output [`DWIDTH-1:0] matrixC23_7; +output [`DWIDTH-1:0] matrixC23_8; +output [`DWIDTH-1:0] matrixC23_9; +output [`DWIDTH-1:0] matrixC23_10; +output [`DWIDTH-1:0] matrixC23_11; +output [`DWIDTH-1:0] matrixC23_12; +output [`DWIDTH-1:0] matrixC23_13; +output [`DWIDTH-1:0] matrixC23_14; +output [`DWIDTH-1:0] matrixC23_15; +output [`DWIDTH-1:0] matrixC23_16; +output [`DWIDTH-1:0] matrixC23_17; +output [`DWIDTH-1:0] matrixC23_18; +output [`DWIDTH-1:0] matrixC23_19; +output [`DWIDTH-1:0] matrixC23_20; +output [`DWIDTH-1:0] matrixC23_21; +output [`DWIDTH-1:0] matrixC23_22; +output [`DWIDTH-1:0] matrixC23_23; +output [`DWIDTH-1:0] matrixC23_24; +output [`DWIDTH-1:0] matrixC23_25; +output [`DWIDTH-1:0] matrixC23_26; +output [`DWIDTH-1:0] matrixC23_27; +output [`DWIDTH-1:0] matrixC23_28; +output [`DWIDTH-1:0] matrixC23_29; +output [`DWIDTH-1:0] matrixC23_30; +output [`DWIDTH-1:0] matrixC23_31; +output [`DWIDTH-1:0] matrixC24_0; +output [`DWIDTH-1:0] matrixC24_1; +output [`DWIDTH-1:0] matrixC24_2; +output [`DWIDTH-1:0] matrixC24_3; +output [`DWIDTH-1:0] matrixC24_4; +output [`DWIDTH-1:0] matrixC24_5; +output [`DWIDTH-1:0] matrixC24_6; +output [`DWIDTH-1:0] matrixC24_7; +output [`DWIDTH-1:0] matrixC24_8; +output [`DWIDTH-1:0] matrixC24_9; +output [`DWIDTH-1:0] matrixC24_10; +output [`DWIDTH-1:0] matrixC24_11; +output [`DWIDTH-1:0] matrixC24_12; +output [`DWIDTH-1:0] matrixC24_13; +output [`DWIDTH-1:0] matrixC24_14; +output [`DWIDTH-1:0] matrixC24_15; +output [`DWIDTH-1:0] matrixC24_16; +output [`DWIDTH-1:0] matrixC24_17; +output [`DWIDTH-1:0] matrixC24_18; +output [`DWIDTH-1:0] matrixC24_19; +output [`DWIDTH-1:0] matrixC24_20; +output [`DWIDTH-1:0] matrixC24_21; +output [`DWIDTH-1:0] matrixC24_22; +output [`DWIDTH-1:0] matrixC24_23; +output [`DWIDTH-1:0] matrixC24_24; +output [`DWIDTH-1:0] matrixC24_25; +output [`DWIDTH-1:0] matrixC24_26; +output [`DWIDTH-1:0] matrixC24_27; +output [`DWIDTH-1:0] matrixC24_28; +output [`DWIDTH-1:0] matrixC24_29; +output [`DWIDTH-1:0] matrixC24_30; +output [`DWIDTH-1:0] matrixC24_31; +output [`DWIDTH-1:0] matrixC25_0; +output [`DWIDTH-1:0] matrixC25_1; +output [`DWIDTH-1:0] matrixC25_2; +output [`DWIDTH-1:0] matrixC25_3; +output [`DWIDTH-1:0] matrixC25_4; +output [`DWIDTH-1:0] matrixC25_5; +output [`DWIDTH-1:0] matrixC25_6; +output [`DWIDTH-1:0] matrixC25_7; +output [`DWIDTH-1:0] matrixC25_8; +output [`DWIDTH-1:0] matrixC25_9; +output [`DWIDTH-1:0] matrixC25_10; +output [`DWIDTH-1:0] matrixC25_11; +output [`DWIDTH-1:0] matrixC25_12; +output [`DWIDTH-1:0] matrixC25_13; +output [`DWIDTH-1:0] matrixC25_14; +output [`DWIDTH-1:0] matrixC25_15; +output [`DWIDTH-1:0] matrixC25_16; +output [`DWIDTH-1:0] matrixC25_17; +output [`DWIDTH-1:0] matrixC25_18; +output [`DWIDTH-1:0] matrixC25_19; +output [`DWIDTH-1:0] matrixC25_20; +output [`DWIDTH-1:0] matrixC25_21; +output [`DWIDTH-1:0] matrixC25_22; +output [`DWIDTH-1:0] matrixC25_23; +output [`DWIDTH-1:0] matrixC25_24; +output [`DWIDTH-1:0] matrixC25_25; +output [`DWIDTH-1:0] matrixC25_26; +output [`DWIDTH-1:0] matrixC25_27; +output [`DWIDTH-1:0] matrixC25_28; +output [`DWIDTH-1:0] matrixC25_29; +output [`DWIDTH-1:0] matrixC25_30; +output [`DWIDTH-1:0] matrixC25_31; +output [`DWIDTH-1:0] matrixC26_0; +output [`DWIDTH-1:0] matrixC26_1; +output [`DWIDTH-1:0] matrixC26_2; +output [`DWIDTH-1:0] matrixC26_3; +output [`DWIDTH-1:0] matrixC26_4; +output [`DWIDTH-1:0] matrixC26_5; +output [`DWIDTH-1:0] matrixC26_6; +output [`DWIDTH-1:0] matrixC26_7; +output [`DWIDTH-1:0] matrixC26_8; +output [`DWIDTH-1:0] matrixC26_9; +output [`DWIDTH-1:0] matrixC26_10; +output [`DWIDTH-1:0] matrixC26_11; +output [`DWIDTH-1:0] matrixC26_12; +output [`DWIDTH-1:0] matrixC26_13; +output [`DWIDTH-1:0] matrixC26_14; +output [`DWIDTH-1:0] matrixC26_15; +output [`DWIDTH-1:0] matrixC26_16; +output [`DWIDTH-1:0] matrixC26_17; +output [`DWIDTH-1:0] matrixC26_18; +output [`DWIDTH-1:0] matrixC26_19; +output [`DWIDTH-1:0] matrixC26_20; +output [`DWIDTH-1:0] matrixC26_21; +output [`DWIDTH-1:0] matrixC26_22; +output [`DWIDTH-1:0] matrixC26_23; +output [`DWIDTH-1:0] matrixC26_24; +output [`DWIDTH-1:0] matrixC26_25; +output [`DWIDTH-1:0] matrixC26_26; +output [`DWIDTH-1:0] matrixC26_27; +output [`DWIDTH-1:0] matrixC26_28; +output [`DWIDTH-1:0] matrixC26_29; +output [`DWIDTH-1:0] matrixC26_30; +output [`DWIDTH-1:0] matrixC26_31; +output [`DWIDTH-1:0] matrixC27_0; +output [`DWIDTH-1:0] matrixC27_1; +output [`DWIDTH-1:0] matrixC27_2; +output [`DWIDTH-1:0] matrixC27_3; +output [`DWIDTH-1:0] matrixC27_4; +output [`DWIDTH-1:0] matrixC27_5; +output [`DWIDTH-1:0] matrixC27_6; +output [`DWIDTH-1:0] matrixC27_7; +output [`DWIDTH-1:0] matrixC27_8; +output [`DWIDTH-1:0] matrixC27_9; +output [`DWIDTH-1:0] matrixC27_10; +output [`DWIDTH-1:0] matrixC27_11; +output [`DWIDTH-1:0] matrixC27_12; +output [`DWIDTH-1:0] matrixC27_13; +output [`DWIDTH-1:0] matrixC27_14; +output [`DWIDTH-1:0] matrixC27_15; +output [`DWIDTH-1:0] matrixC27_16; +output [`DWIDTH-1:0] matrixC27_17; +output [`DWIDTH-1:0] matrixC27_18; +output [`DWIDTH-1:0] matrixC27_19; +output [`DWIDTH-1:0] matrixC27_20; +output [`DWIDTH-1:0] matrixC27_21; +output [`DWIDTH-1:0] matrixC27_22; +output [`DWIDTH-1:0] matrixC27_23; +output [`DWIDTH-1:0] matrixC27_24; +output [`DWIDTH-1:0] matrixC27_25; +output [`DWIDTH-1:0] matrixC27_26; +output [`DWIDTH-1:0] matrixC27_27; +output [`DWIDTH-1:0] matrixC27_28; +output [`DWIDTH-1:0] matrixC27_29; +output [`DWIDTH-1:0] matrixC27_30; +output [`DWIDTH-1:0] matrixC27_31; +output [`DWIDTH-1:0] matrixC28_0; +output [`DWIDTH-1:0] matrixC28_1; +output [`DWIDTH-1:0] matrixC28_2; +output [`DWIDTH-1:0] matrixC28_3; +output [`DWIDTH-1:0] matrixC28_4; +output [`DWIDTH-1:0] matrixC28_5; +output [`DWIDTH-1:0] matrixC28_6; +output [`DWIDTH-1:0] matrixC28_7; +output [`DWIDTH-1:0] matrixC28_8; +output [`DWIDTH-1:0] matrixC28_9; +output [`DWIDTH-1:0] matrixC28_10; +output [`DWIDTH-1:0] matrixC28_11; +output [`DWIDTH-1:0] matrixC28_12; +output [`DWIDTH-1:0] matrixC28_13; +output [`DWIDTH-1:0] matrixC28_14; +output [`DWIDTH-1:0] matrixC28_15; +output [`DWIDTH-1:0] matrixC28_16; +output [`DWIDTH-1:0] matrixC28_17; +output [`DWIDTH-1:0] matrixC28_18; +output [`DWIDTH-1:0] matrixC28_19; +output [`DWIDTH-1:0] matrixC28_20; +output [`DWIDTH-1:0] matrixC28_21; +output [`DWIDTH-1:0] matrixC28_22; +output [`DWIDTH-1:0] matrixC28_23; +output [`DWIDTH-1:0] matrixC28_24; +output [`DWIDTH-1:0] matrixC28_25; +output [`DWIDTH-1:0] matrixC28_26; +output [`DWIDTH-1:0] matrixC28_27; +output [`DWIDTH-1:0] matrixC28_28; +output [`DWIDTH-1:0] matrixC28_29; +output [`DWIDTH-1:0] matrixC28_30; +output [`DWIDTH-1:0] matrixC28_31; +output [`DWIDTH-1:0] matrixC29_0; +output [`DWIDTH-1:0] matrixC29_1; +output [`DWIDTH-1:0] matrixC29_2; +output [`DWIDTH-1:0] matrixC29_3; +output [`DWIDTH-1:0] matrixC29_4; +output [`DWIDTH-1:0] matrixC29_5; +output [`DWIDTH-1:0] matrixC29_6; +output [`DWIDTH-1:0] matrixC29_7; +output [`DWIDTH-1:0] matrixC29_8; +output [`DWIDTH-1:0] matrixC29_9; +output [`DWIDTH-1:0] matrixC29_10; +output [`DWIDTH-1:0] matrixC29_11; +output [`DWIDTH-1:0] matrixC29_12; +output [`DWIDTH-1:0] matrixC29_13; +output [`DWIDTH-1:0] matrixC29_14; +output [`DWIDTH-1:0] matrixC29_15; +output [`DWIDTH-1:0] matrixC29_16; +output [`DWIDTH-1:0] matrixC29_17; +output [`DWIDTH-1:0] matrixC29_18; +output [`DWIDTH-1:0] matrixC29_19; +output [`DWIDTH-1:0] matrixC29_20; +output [`DWIDTH-1:0] matrixC29_21; +output [`DWIDTH-1:0] matrixC29_22; +output [`DWIDTH-1:0] matrixC29_23; +output [`DWIDTH-1:0] matrixC29_24; +output [`DWIDTH-1:0] matrixC29_25; +output [`DWIDTH-1:0] matrixC29_26; +output [`DWIDTH-1:0] matrixC29_27; +output [`DWIDTH-1:0] matrixC29_28; +output [`DWIDTH-1:0] matrixC29_29; +output [`DWIDTH-1:0] matrixC29_30; +output [`DWIDTH-1:0] matrixC29_31; +output [`DWIDTH-1:0] matrixC30_0; +output [`DWIDTH-1:0] matrixC30_1; +output [`DWIDTH-1:0] matrixC30_2; +output [`DWIDTH-1:0] matrixC30_3; +output [`DWIDTH-1:0] matrixC30_4; +output [`DWIDTH-1:0] matrixC30_5; +output [`DWIDTH-1:0] matrixC30_6; +output [`DWIDTH-1:0] matrixC30_7; +output [`DWIDTH-1:0] matrixC30_8; +output [`DWIDTH-1:0] matrixC30_9; +output [`DWIDTH-1:0] matrixC30_10; +output [`DWIDTH-1:0] matrixC30_11; +output [`DWIDTH-1:0] matrixC30_12; +output [`DWIDTH-1:0] matrixC30_13; +output [`DWIDTH-1:0] matrixC30_14; +output [`DWIDTH-1:0] matrixC30_15; +output [`DWIDTH-1:0] matrixC30_16; +output [`DWIDTH-1:0] matrixC30_17; +output [`DWIDTH-1:0] matrixC30_18; +output [`DWIDTH-1:0] matrixC30_19; +output [`DWIDTH-1:0] matrixC30_20; +output [`DWIDTH-1:0] matrixC30_21; +output [`DWIDTH-1:0] matrixC30_22; +output [`DWIDTH-1:0] matrixC30_23; +output [`DWIDTH-1:0] matrixC30_24; +output [`DWIDTH-1:0] matrixC30_25; +output [`DWIDTH-1:0] matrixC30_26; +output [`DWIDTH-1:0] matrixC30_27; +output [`DWIDTH-1:0] matrixC30_28; +output [`DWIDTH-1:0] matrixC30_29; +output [`DWIDTH-1:0] matrixC30_30; +output [`DWIDTH-1:0] matrixC30_31; +output [`DWIDTH-1:0] matrixC31_0; +output [`DWIDTH-1:0] matrixC31_1; +output [`DWIDTH-1:0] matrixC31_2; +output [`DWIDTH-1:0] matrixC31_3; +output [`DWIDTH-1:0] matrixC31_4; +output [`DWIDTH-1:0] matrixC31_5; +output [`DWIDTH-1:0] matrixC31_6; +output [`DWIDTH-1:0] matrixC31_7; +output [`DWIDTH-1:0] matrixC31_8; +output [`DWIDTH-1:0] matrixC31_9; +output [`DWIDTH-1:0] matrixC31_10; +output [`DWIDTH-1:0] matrixC31_11; +output [`DWIDTH-1:0] matrixC31_12; +output [`DWIDTH-1:0] matrixC31_13; +output [`DWIDTH-1:0] matrixC31_14; +output [`DWIDTH-1:0] matrixC31_15; +output [`DWIDTH-1:0] matrixC31_16; +output [`DWIDTH-1:0] matrixC31_17; +output [`DWIDTH-1:0] matrixC31_18; +output [`DWIDTH-1:0] matrixC31_19; +output [`DWIDTH-1:0] matrixC31_20; +output [`DWIDTH-1:0] matrixC31_21; +output [`DWIDTH-1:0] matrixC31_22; +output [`DWIDTH-1:0] matrixC31_23; +output [`DWIDTH-1:0] matrixC31_24; +output [`DWIDTH-1:0] matrixC31_25; +output [`DWIDTH-1:0] matrixC31_26; +output [`DWIDTH-1:0] matrixC31_27; +output [`DWIDTH-1:0] matrixC31_28; +output [`DWIDTH-1:0] matrixC31_29; +output [`DWIDTH-1:0] matrixC31_30; +output [`DWIDTH-1:0] matrixC31_31; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + + +wire [`DWIDTH-1:0] a0_0to0_1, a0_1to0_2, a0_2to0_3, a0_3to0_4, a0_4to0_5, a0_5to0_6, a0_6to0_7, a0_7to0_8, a0_8to0_9, a0_9to0_10, a0_10to0_11, a0_11to0_12, a0_12to0_13, a0_13to0_14, a0_14to0_15, a0_15to0_16, a0_16to0_17, a0_17to0_18, a0_18to0_19, a0_19to0_20, a0_20to0_21, a0_21to0_22, a0_22to0_23, a0_23to0_24, a0_24to0_25, a0_25to0_26, a0_26to0_27, a0_27to0_28, a0_28to0_29, a0_29to0_30, a0_30to0_31, a0_31to0_32; +wire [`DWIDTH-1:0] a1_0to1_1, a1_1to1_2, a1_2to1_3, a1_3to1_4, a1_4to1_5, a1_5to1_6, a1_6to1_7, a1_7to1_8, a1_8to1_9, a1_9to1_10, a1_10to1_11, a1_11to1_12, a1_12to1_13, a1_13to1_14, a1_14to1_15, a1_15to1_16, a1_16to1_17, a1_17to1_18, a1_18to1_19, a1_19to1_20, a1_20to1_21, a1_21to1_22, a1_22to1_23, a1_23to1_24, a1_24to1_25, a1_25to1_26, a1_26to1_27, a1_27to1_28, a1_28to1_29, a1_29to1_30, a1_30to1_31, a1_31to1_32; +wire [`DWIDTH-1:0] a2_0to2_1, a2_1to2_2, a2_2to2_3, a2_3to2_4, a2_4to2_5, a2_5to2_6, a2_6to2_7, a2_7to2_8, a2_8to2_9, a2_9to2_10, a2_10to2_11, a2_11to2_12, a2_12to2_13, a2_13to2_14, a2_14to2_15, a2_15to2_16, a2_16to2_17, a2_17to2_18, a2_18to2_19, a2_19to2_20, a2_20to2_21, a2_21to2_22, a2_22to2_23, a2_23to2_24, a2_24to2_25, a2_25to2_26, a2_26to2_27, a2_27to2_28, a2_28to2_29, a2_29to2_30, a2_30to2_31, a2_31to2_32; +wire [`DWIDTH-1:0] a3_0to3_1, a3_1to3_2, a3_2to3_3, a3_3to3_4, a3_4to3_5, a3_5to3_6, a3_6to3_7, a3_7to3_8, a3_8to3_9, a3_9to3_10, a3_10to3_11, a3_11to3_12, a3_12to3_13, a3_13to3_14, a3_14to3_15, a3_15to3_16, a3_16to3_17, a3_17to3_18, a3_18to3_19, a3_19to3_20, a3_20to3_21, a3_21to3_22, a3_22to3_23, a3_23to3_24, a3_24to3_25, a3_25to3_26, a3_26to3_27, a3_27to3_28, a3_28to3_29, a3_29to3_30, a3_30to3_31, a3_31to3_32; +wire [`DWIDTH-1:0] a4_0to4_1, a4_1to4_2, a4_2to4_3, a4_3to4_4, a4_4to4_5, a4_5to4_6, a4_6to4_7, a4_7to4_8, a4_8to4_9, a4_9to4_10, a4_10to4_11, a4_11to4_12, a4_12to4_13, a4_13to4_14, a4_14to4_15, a4_15to4_16, a4_16to4_17, a4_17to4_18, a4_18to4_19, a4_19to4_20, a4_20to4_21, a4_21to4_22, a4_22to4_23, a4_23to4_24, a4_24to4_25, a4_25to4_26, a4_26to4_27, a4_27to4_28, a4_28to4_29, a4_29to4_30, a4_30to4_31, a4_31to4_32; +wire [`DWIDTH-1:0] a5_0to5_1, a5_1to5_2, a5_2to5_3, a5_3to5_4, a5_4to5_5, a5_5to5_6, a5_6to5_7, a5_7to5_8, a5_8to5_9, a5_9to5_10, a5_10to5_11, a5_11to5_12, a5_12to5_13, a5_13to5_14, a5_14to5_15, a5_15to5_16, a5_16to5_17, a5_17to5_18, a5_18to5_19, a5_19to5_20, a5_20to5_21, a5_21to5_22, a5_22to5_23, a5_23to5_24, a5_24to5_25, a5_25to5_26, a5_26to5_27, a5_27to5_28, a5_28to5_29, a5_29to5_30, a5_30to5_31, a5_31to5_32; +wire [`DWIDTH-1:0] a6_0to6_1, a6_1to6_2, a6_2to6_3, a6_3to6_4, a6_4to6_5, a6_5to6_6, a6_6to6_7, a6_7to6_8, a6_8to6_9, a6_9to6_10, a6_10to6_11, a6_11to6_12, a6_12to6_13, a6_13to6_14, a6_14to6_15, a6_15to6_16, a6_16to6_17, a6_17to6_18, a6_18to6_19, a6_19to6_20, a6_20to6_21, a6_21to6_22, a6_22to6_23, a6_23to6_24, a6_24to6_25, a6_25to6_26, a6_26to6_27, a6_27to6_28, a6_28to6_29, a6_29to6_30, a6_30to6_31, a6_31to6_32; +wire [`DWIDTH-1:0] a7_0to7_1, a7_1to7_2, a7_2to7_3, a7_3to7_4, a7_4to7_5, a7_5to7_6, a7_6to7_7, a7_7to7_8, a7_8to7_9, a7_9to7_10, a7_10to7_11, a7_11to7_12, a7_12to7_13, a7_13to7_14, a7_14to7_15, a7_15to7_16, a7_16to7_17, a7_17to7_18, a7_18to7_19, a7_19to7_20, a7_20to7_21, a7_21to7_22, a7_22to7_23, a7_23to7_24, a7_24to7_25, a7_25to7_26, a7_26to7_27, a7_27to7_28, a7_28to7_29, a7_29to7_30, a7_30to7_31, a7_31to7_32; +wire [`DWIDTH-1:0] a8_0to8_1, a8_1to8_2, a8_2to8_3, a8_3to8_4, a8_4to8_5, a8_5to8_6, a8_6to8_7, a8_7to8_8, a8_8to8_9, a8_9to8_10, a8_10to8_11, a8_11to8_12, a8_12to8_13, a8_13to8_14, a8_14to8_15, a8_15to8_16, a8_16to8_17, a8_17to8_18, a8_18to8_19, a8_19to8_20, a8_20to8_21, a8_21to8_22, a8_22to8_23, a8_23to8_24, a8_24to8_25, a8_25to8_26, a8_26to8_27, a8_27to8_28, a8_28to8_29, a8_29to8_30, a8_30to8_31, a8_31to8_32; +wire [`DWIDTH-1:0] a9_0to9_1, a9_1to9_2, a9_2to9_3, a9_3to9_4, a9_4to9_5, a9_5to9_6, a9_6to9_7, a9_7to9_8, a9_8to9_9, a9_9to9_10, a9_10to9_11, a9_11to9_12, a9_12to9_13, a9_13to9_14, a9_14to9_15, a9_15to9_16, a9_16to9_17, a9_17to9_18, a9_18to9_19, a9_19to9_20, a9_20to9_21, a9_21to9_22, a9_22to9_23, a9_23to9_24, a9_24to9_25, a9_25to9_26, a9_26to9_27, a9_27to9_28, a9_28to9_29, a9_29to9_30, a9_30to9_31, a9_31to9_32; +wire [`DWIDTH-1:0] a10_0to10_1, a10_1to10_2, a10_2to10_3, a10_3to10_4, a10_4to10_5, a10_5to10_6, a10_6to10_7, a10_7to10_8, a10_8to10_9, a10_9to10_10, a10_10to10_11, a10_11to10_12, a10_12to10_13, a10_13to10_14, a10_14to10_15, a10_15to10_16, a10_16to10_17, a10_17to10_18, a10_18to10_19, a10_19to10_20, a10_20to10_21, a10_21to10_22, a10_22to10_23, a10_23to10_24, a10_24to10_25, a10_25to10_26, a10_26to10_27, a10_27to10_28, a10_28to10_29, a10_29to10_30, a10_30to10_31, a10_31to10_32; +wire [`DWIDTH-1:0] a11_0to11_1, a11_1to11_2, a11_2to11_3, a11_3to11_4, a11_4to11_5, a11_5to11_6, a11_6to11_7, a11_7to11_8, a11_8to11_9, a11_9to11_10, a11_10to11_11, a11_11to11_12, a11_12to11_13, a11_13to11_14, a11_14to11_15, a11_15to11_16, a11_16to11_17, a11_17to11_18, a11_18to11_19, a11_19to11_20, a11_20to11_21, a11_21to11_22, a11_22to11_23, a11_23to11_24, a11_24to11_25, a11_25to11_26, a11_26to11_27, a11_27to11_28, a11_28to11_29, a11_29to11_30, a11_30to11_31, a11_31to11_32; +wire [`DWIDTH-1:0] a12_0to12_1, a12_1to12_2, a12_2to12_3, a12_3to12_4, a12_4to12_5, a12_5to12_6, a12_6to12_7, a12_7to12_8, a12_8to12_9, a12_9to12_10, a12_10to12_11, a12_11to12_12, a12_12to12_13, a12_13to12_14, a12_14to12_15, a12_15to12_16, a12_16to12_17, a12_17to12_18, a12_18to12_19, a12_19to12_20, a12_20to12_21, a12_21to12_22, a12_22to12_23, a12_23to12_24, a12_24to12_25, a12_25to12_26, a12_26to12_27, a12_27to12_28, a12_28to12_29, a12_29to12_30, a12_30to12_31, a12_31to12_32; +wire [`DWIDTH-1:0] a13_0to13_1, a13_1to13_2, a13_2to13_3, a13_3to13_4, a13_4to13_5, a13_5to13_6, a13_6to13_7, a13_7to13_8, a13_8to13_9, a13_9to13_10, a13_10to13_11, a13_11to13_12, a13_12to13_13, a13_13to13_14, a13_14to13_15, a13_15to13_16, a13_16to13_17, a13_17to13_18, a13_18to13_19, a13_19to13_20, a13_20to13_21, a13_21to13_22, a13_22to13_23, a13_23to13_24, a13_24to13_25, a13_25to13_26, a13_26to13_27, a13_27to13_28, a13_28to13_29, a13_29to13_30, a13_30to13_31, a13_31to13_32; +wire [`DWIDTH-1:0] a14_0to14_1, a14_1to14_2, a14_2to14_3, a14_3to14_4, a14_4to14_5, a14_5to14_6, a14_6to14_7, a14_7to14_8, a14_8to14_9, a14_9to14_10, a14_10to14_11, a14_11to14_12, a14_12to14_13, a14_13to14_14, a14_14to14_15, a14_15to14_16, a14_16to14_17, a14_17to14_18, a14_18to14_19, a14_19to14_20, a14_20to14_21, a14_21to14_22, a14_22to14_23, a14_23to14_24, a14_24to14_25, a14_25to14_26, a14_26to14_27, a14_27to14_28, a14_28to14_29, a14_29to14_30, a14_30to14_31, a14_31to14_32; +wire [`DWIDTH-1:0] a15_0to15_1, a15_1to15_2, a15_2to15_3, a15_3to15_4, a15_4to15_5, a15_5to15_6, a15_6to15_7, a15_7to15_8, a15_8to15_9, a15_9to15_10, a15_10to15_11, a15_11to15_12, a15_12to15_13, a15_13to15_14, a15_14to15_15, a15_15to15_16, a15_16to15_17, a15_17to15_18, a15_18to15_19, a15_19to15_20, a15_20to15_21, a15_21to15_22, a15_22to15_23, a15_23to15_24, a15_24to15_25, a15_25to15_26, a15_26to15_27, a15_27to15_28, a15_28to15_29, a15_29to15_30, a15_30to15_31, a15_31to15_32; +wire [`DWIDTH-1:0] a16_0to16_1, a16_1to16_2, a16_2to16_3, a16_3to16_4, a16_4to16_5, a16_5to16_6, a16_6to16_7, a16_7to16_8, a16_8to16_9, a16_9to16_10, a16_10to16_11, a16_11to16_12, a16_12to16_13, a16_13to16_14, a16_14to16_15, a16_15to16_16, a16_16to16_17, a16_17to16_18, a16_18to16_19, a16_19to16_20, a16_20to16_21, a16_21to16_22, a16_22to16_23, a16_23to16_24, a16_24to16_25, a16_25to16_26, a16_26to16_27, a16_27to16_28, a16_28to16_29, a16_29to16_30, a16_30to16_31, a16_31to16_32; +wire [`DWIDTH-1:0] a17_0to17_1, a17_1to17_2, a17_2to17_3, a17_3to17_4, a17_4to17_5, a17_5to17_6, a17_6to17_7, a17_7to17_8, a17_8to17_9, a17_9to17_10, a17_10to17_11, a17_11to17_12, a17_12to17_13, a17_13to17_14, a17_14to17_15, a17_15to17_16, a17_16to17_17, a17_17to17_18, a17_18to17_19, a17_19to17_20, a17_20to17_21, a17_21to17_22, a17_22to17_23, a17_23to17_24, a17_24to17_25, a17_25to17_26, a17_26to17_27, a17_27to17_28, a17_28to17_29, a17_29to17_30, a17_30to17_31, a17_31to17_32; +wire [`DWIDTH-1:0] a18_0to18_1, a18_1to18_2, a18_2to18_3, a18_3to18_4, a18_4to18_5, a18_5to18_6, a18_6to18_7, a18_7to18_8, a18_8to18_9, a18_9to18_10, a18_10to18_11, a18_11to18_12, a18_12to18_13, a18_13to18_14, a18_14to18_15, a18_15to18_16, a18_16to18_17, a18_17to18_18, a18_18to18_19, a18_19to18_20, a18_20to18_21, a18_21to18_22, a18_22to18_23, a18_23to18_24, a18_24to18_25, a18_25to18_26, a18_26to18_27, a18_27to18_28, a18_28to18_29, a18_29to18_30, a18_30to18_31, a18_31to18_32; +wire [`DWIDTH-1:0] a19_0to19_1, a19_1to19_2, a19_2to19_3, a19_3to19_4, a19_4to19_5, a19_5to19_6, a19_6to19_7, a19_7to19_8, a19_8to19_9, a19_9to19_10, a19_10to19_11, a19_11to19_12, a19_12to19_13, a19_13to19_14, a19_14to19_15, a19_15to19_16, a19_16to19_17, a19_17to19_18, a19_18to19_19, a19_19to19_20, a19_20to19_21, a19_21to19_22, a19_22to19_23, a19_23to19_24, a19_24to19_25, a19_25to19_26, a19_26to19_27, a19_27to19_28, a19_28to19_29, a19_29to19_30, a19_30to19_31, a19_31to19_32; +wire [`DWIDTH-1:0] a20_0to20_1, a20_1to20_2, a20_2to20_3, a20_3to20_4, a20_4to20_5, a20_5to20_6, a20_6to20_7, a20_7to20_8, a20_8to20_9, a20_9to20_10, a20_10to20_11, a20_11to20_12, a20_12to20_13, a20_13to20_14, a20_14to20_15, a20_15to20_16, a20_16to20_17, a20_17to20_18, a20_18to20_19, a20_19to20_20, a20_20to20_21, a20_21to20_22, a20_22to20_23, a20_23to20_24, a20_24to20_25, a20_25to20_26, a20_26to20_27, a20_27to20_28, a20_28to20_29, a20_29to20_30, a20_30to20_31, a20_31to20_32; +wire [`DWIDTH-1:0] a21_0to21_1, a21_1to21_2, a21_2to21_3, a21_3to21_4, a21_4to21_5, a21_5to21_6, a21_6to21_7, a21_7to21_8, a21_8to21_9, a21_9to21_10, a21_10to21_11, a21_11to21_12, a21_12to21_13, a21_13to21_14, a21_14to21_15, a21_15to21_16, a21_16to21_17, a21_17to21_18, a21_18to21_19, a21_19to21_20, a21_20to21_21, a21_21to21_22, a21_22to21_23, a21_23to21_24, a21_24to21_25, a21_25to21_26, a21_26to21_27, a21_27to21_28, a21_28to21_29, a21_29to21_30, a21_30to21_31, a21_31to21_32; +wire [`DWIDTH-1:0] a22_0to22_1, a22_1to22_2, a22_2to22_3, a22_3to22_4, a22_4to22_5, a22_5to22_6, a22_6to22_7, a22_7to22_8, a22_8to22_9, a22_9to22_10, a22_10to22_11, a22_11to22_12, a22_12to22_13, a22_13to22_14, a22_14to22_15, a22_15to22_16, a22_16to22_17, a22_17to22_18, a22_18to22_19, a22_19to22_20, a22_20to22_21, a22_21to22_22, a22_22to22_23, a22_23to22_24, a22_24to22_25, a22_25to22_26, a22_26to22_27, a22_27to22_28, a22_28to22_29, a22_29to22_30, a22_30to22_31, a22_31to22_32; +wire [`DWIDTH-1:0] a23_0to23_1, a23_1to23_2, a23_2to23_3, a23_3to23_4, a23_4to23_5, a23_5to23_6, a23_6to23_7, a23_7to23_8, a23_8to23_9, a23_9to23_10, a23_10to23_11, a23_11to23_12, a23_12to23_13, a23_13to23_14, a23_14to23_15, a23_15to23_16, a23_16to23_17, a23_17to23_18, a23_18to23_19, a23_19to23_20, a23_20to23_21, a23_21to23_22, a23_22to23_23, a23_23to23_24, a23_24to23_25, a23_25to23_26, a23_26to23_27, a23_27to23_28, a23_28to23_29, a23_29to23_30, a23_30to23_31, a23_31to23_32; +wire [`DWIDTH-1:0] a24_0to24_1, a24_1to24_2, a24_2to24_3, a24_3to24_4, a24_4to24_5, a24_5to24_6, a24_6to24_7, a24_7to24_8, a24_8to24_9, a24_9to24_10, a24_10to24_11, a24_11to24_12, a24_12to24_13, a24_13to24_14, a24_14to24_15, a24_15to24_16, a24_16to24_17, a24_17to24_18, a24_18to24_19, a24_19to24_20, a24_20to24_21, a24_21to24_22, a24_22to24_23, a24_23to24_24, a24_24to24_25, a24_25to24_26, a24_26to24_27, a24_27to24_28, a24_28to24_29, a24_29to24_30, a24_30to24_31, a24_31to24_32; +wire [`DWIDTH-1:0] a25_0to25_1, a25_1to25_2, a25_2to25_3, a25_3to25_4, a25_4to25_5, a25_5to25_6, a25_6to25_7, a25_7to25_8, a25_8to25_9, a25_9to25_10, a25_10to25_11, a25_11to25_12, a25_12to25_13, a25_13to25_14, a25_14to25_15, a25_15to25_16, a25_16to25_17, a25_17to25_18, a25_18to25_19, a25_19to25_20, a25_20to25_21, a25_21to25_22, a25_22to25_23, a25_23to25_24, a25_24to25_25, a25_25to25_26, a25_26to25_27, a25_27to25_28, a25_28to25_29, a25_29to25_30, a25_30to25_31, a25_31to25_32; +wire [`DWIDTH-1:0] a26_0to26_1, a26_1to26_2, a26_2to26_3, a26_3to26_4, a26_4to26_5, a26_5to26_6, a26_6to26_7, a26_7to26_8, a26_8to26_9, a26_9to26_10, a26_10to26_11, a26_11to26_12, a26_12to26_13, a26_13to26_14, a26_14to26_15, a26_15to26_16, a26_16to26_17, a26_17to26_18, a26_18to26_19, a26_19to26_20, a26_20to26_21, a26_21to26_22, a26_22to26_23, a26_23to26_24, a26_24to26_25, a26_25to26_26, a26_26to26_27, a26_27to26_28, a26_28to26_29, a26_29to26_30, a26_30to26_31, a26_31to26_32; +wire [`DWIDTH-1:0] a27_0to27_1, a27_1to27_2, a27_2to27_3, a27_3to27_4, a27_4to27_5, a27_5to27_6, a27_6to27_7, a27_7to27_8, a27_8to27_9, a27_9to27_10, a27_10to27_11, a27_11to27_12, a27_12to27_13, a27_13to27_14, a27_14to27_15, a27_15to27_16, a27_16to27_17, a27_17to27_18, a27_18to27_19, a27_19to27_20, a27_20to27_21, a27_21to27_22, a27_22to27_23, a27_23to27_24, a27_24to27_25, a27_25to27_26, a27_26to27_27, a27_27to27_28, a27_28to27_29, a27_29to27_30, a27_30to27_31, a27_31to27_32; +wire [`DWIDTH-1:0] a28_0to28_1, a28_1to28_2, a28_2to28_3, a28_3to28_4, a28_4to28_5, a28_5to28_6, a28_6to28_7, a28_7to28_8, a28_8to28_9, a28_9to28_10, a28_10to28_11, a28_11to28_12, a28_12to28_13, a28_13to28_14, a28_14to28_15, a28_15to28_16, a28_16to28_17, a28_17to28_18, a28_18to28_19, a28_19to28_20, a28_20to28_21, a28_21to28_22, a28_22to28_23, a28_23to28_24, a28_24to28_25, a28_25to28_26, a28_26to28_27, a28_27to28_28, a28_28to28_29, a28_29to28_30, a28_30to28_31, a28_31to28_32; +wire [`DWIDTH-1:0] a29_0to29_1, a29_1to29_2, a29_2to29_3, a29_3to29_4, a29_4to29_5, a29_5to29_6, a29_6to29_7, a29_7to29_8, a29_8to29_9, a29_9to29_10, a29_10to29_11, a29_11to29_12, a29_12to29_13, a29_13to29_14, a29_14to29_15, a29_15to29_16, a29_16to29_17, a29_17to29_18, a29_18to29_19, a29_19to29_20, a29_20to29_21, a29_21to29_22, a29_22to29_23, a29_23to29_24, a29_24to29_25, a29_25to29_26, a29_26to29_27, a29_27to29_28, a29_28to29_29, a29_29to29_30, a29_30to29_31, a29_31to29_32; +wire [`DWIDTH-1:0] a30_0to30_1, a30_1to30_2, a30_2to30_3, a30_3to30_4, a30_4to30_5, a30_5to30_6, a30_6to30_7, a30_7to30_8, a30_8to30_9, a30_9to30_10, a30_10to30_11, a30_11to30_12, a30_12to30_13, a30_13to30_14, a30_14to30_15, a30_15to30_16, a30_16to30_17, a30_17to30_18, a30_18to30_19, a30_19to30_20, a30_20to30_21, a30_21to30_22, a30_22to30_23, a30_23to30_24, a30_24to30_25, a30_25to30_26, a30_26to30_27, a30_27to30_28, a30_28to30_29, a30_29to30_30, a30_30to30_31, a30_31to30_32; +wire [`DWIDTH-1:0] a31_0to31_1, a31_1to31_2, a31_2to31_3, a31_3to31_4, a31_4to31_5, a31_5to31_6, a31_6to31_7, a31_7to31_8, a31_8to31_9, a31_9to31_10, a31_10to31_11, a31_11to31_12, a31_12to31_13, a31_13to31_14, a31_14to31_15, a31_15to31_16, a31_16to31_17, a31_17to31_18, a31_18to31_19, a31_19to31_20, a31_20to31_21, a31_21to31_22, a31_22to31_23, a31_23to31_24, a31_24to31_25, a31_25to31_26, a31_26to31_27, a31_27to31_28, a31_28to31_29, a31_29to31_30, a31_30to31_31, a31_31to31_32; + +wire [`DWIDTH-1:0] b0_0to1_0, b1_0to2_0, b2_0to3_0, b3_0to4_0, b4_0to5_0, b5_0to6_0, b6_0to7_0, b7_0to8_0, b8_0to9_0, b9_0to10_0, b10_0to11_0, b11_0to12_0, b12_0to13_0, b13_0to14_0, b14_0to15_0, b15_0to16_0, b16_0to17_0, b17_0to18_0, b18_0to19_0, b19_0to20_0, b20_0to21_0, b21_0to22_0, b22_0to23_0, b23_0to24_0, b24_0to25_0, b25_0to26_0, b26_0to27_0, b27_0to28_0, b28_0to29_0, b29_0to30_0, b30_0to31_0, b31_0to32_0; +wire [`DWIDTH-1:0] b0_1to1_1, b1_1to2_1, b2_1to3_1, b3_1to4_1, b4_1to5_1, b5_1to6_1, b6_1to7_1, b7_1to8_1, b8_1to9_1, b9_1to10_1, b10_1to11_1, b11_1to12_1, b12_1to13_1, b13_1to14_1, b14_1to15_1, b15_1to16_1, b16_1to17_1, b17_1to18_1, b18_1to19_1, b19_1to20_1, b20_1to21_1, b21_1to22_1, b22_1to23_1, b23_1to24_1, b24_1to25_1, b25_1to26_1, b26_1to27_1, b27_1to28_1, b28_1to29_1, b29_1to30_1, b30_1to31_1, b31_1to32_1; +wire [`DWIDTH-1:0] b0_2to1_2, b1_2to2_2, b2_2to3_2, b3_2to4_2, b4_2to5_2, b5_2to6_2, b6_2to7_2, b7_2to8_2, b8_2to9_2, b9_2to10_2, b10_2to11_2, b11_2to12_2, b12_2to13_2, b13_2to14_2, b14_2to15_2, b15_2to16_2, b16_2to17_2, b17_2to18_2, b18_2to19_2, b19_2to20_2, b20_2to21_2, b21_2to22_2, b22_2to23_2, b23_2to24_2, b24_2to25_2, b25_2to26_2, b26_2to27_2, b27_2to28_2, b28_2to29_2, b29_2to30_2, b30_2to31_2, b31_2to32_2; +wire [`DWIDTH-1:0] b0_3to1_3, b1_3to2_3, b2_3to3_3, b3_3to4_3, b4_3to5_3, b5_3to6_3, b6_3to7_3, b7_3to8_3, b8_3to9_3, b9_3to10_3, b10_3to11_3, b11_3to12_3, b12_3to13_3, b13_3to14_3, b14_3to15_3, b15_3to16_3, b16_3to17_3, b17_3to18_3, b18_3to19_3, b19_3to20_3, b20_3to21_3, b21_3to22_3, b22_3to23_3, b23_3to24_3, b24_3to25_3, b25_3to26_3, b26_3to27_3, b27_3to28_3, b28_3to29_3, b29_3to30_3, b30_3to31_3, b31_3to32_3; +wire [`DWIDTH-1:0] b0_4to1_4, b1_4to2_4, b2_4to3_4, b3_4to4_4, b4_4to5_4, b5_4to6_4, b6_4to7_4, b7_4to8_4, b8_4to9_4, b9_4to10_4, b10_4to11_4, b11_4to12_4, b12_4to13_4, b13_4to14_4, b14_4to15_4, b15_4to16_4, b16_4to17_4, b17_4to18_4, b18_4to19_4, b19_4to20_4, b20_4to21_4, b21_4to22_4, b22_4to23_4, b23_4to24_4, b24_4to25_4, b25_4to26_4, b26_4to27_4, b27_4to28_4, b28_4to29_4, b29_4to30_4, b30_4to31_4, b31_4to32_4; +wire [`DWIDTH-1:0] b0_5to1_5, b1_5to2_5, b2_5to3_5, b3_5to4_5, b4_5to5_5, b5_5to6_5, b6_5to7_5, b7_5to8_5, b8_5to9_5, b9_5to10_5, b10_5to11_5, b11_5to12_5, b12_5to13_5, b13_5to14_5, b14_5to15_5, b15_5to16_5, b16_5to17_5, b17_5to18_5, b18_5to19_5, b19_5to20_5, b20_5to21_5, b21_5to22_5, b22_5to23_5, b23_5to24_5, b24_5to25_5, b25_5to26_5, b26_5to27_5, b27_5to28_5, b28_5to29_5, b29_5to30_5, b30_5to31_5, b31_5to32_5; +wire [`DWIDTH-1:0] b0_6to1_6, b1_6to2_6, b2_6to3_6, b3_6to4_6, b4_6to5_6, b5_6to6_6, b6_6to7_6, b7_6to8_6, b8_6to9_6, b9_6to10_6, b10_6to11_6, b11_6to12_6, b12_6to13_6, b13_6to14_6, b14_6to15_6, b15_6to16_6, b16_6to17_6, b17_6to18_6, b18_6to19_6, b19_6to20_6, b20_6to21_6, b21_6to22_6, b22_6to23_6, b23_6to24_6, b24_6to25_6, b25_6to26_6, b26_6to27_6, b27_6to28_6, b28_6to29_6, b29_6to30_6, b30_6to31_6, b31_6to32_6; +wire [`DWIDTH-1:0] b0_7to1_7, b1_7to2_7, b2_7to3_7, b3_7to4_7, b4_7to5_7, b5_7to6_7, b6_7to7_7, b7_7to8_7, b8_7to9_7, b9_7to10_7, b10_7to11_7, b11_7to12_7, b12_7to13_7, b13_7to14_7, b14_7to15_7, b15_7to16_7, b16_7to17_7, b17_7to18_7, b18_7to19_7, b19_7to20_7, b20_7to21_7, b21_7to22_7, b22_7to23_7, b23_7to24_7, b24_7to25_7, b25_7to26_7, b26_7to27_7, b27_7to28_7, b28_7to29_7, b29_7to30_7, b30_7to31_7, b31_7to32_7; +wire [`DWIDTH-1:0] b0_8to1_8, b1_8to2_8, b2_8to3_8, b3_8to4_8, b4_8to5_8, b5_8to6_8, b6_8to7_8, b7_8to8_8, b8_8to9_8, b9_8to10_8, b10_8to11_8, b11_8to12_8, b12_8to13_8, b13_8to14_8, b14_8to15_8, b15_8to16_8, b16_8to17_8, b17_8to18_8, b18_8to19_8, b19_8to20_8, b20_8to21_8, b21_8to22_8, b22_8to23_8, b23_8to24_8, b24_8to25_8, b25_8to26_8, b26_8to27_8, b27_8to28_8, b28_8to29_8, b29_8to30_8, b30_8to31_8, b31_8to32_8; +wire [`DWIDTH-1:0] b0_9to1_9, b1_9to2_9, b2_9to3_9, b3_9to4_9, b4_9to5_9, b5_9to6_9, b6_9to7_9, b7_9to8_9, b8_9to9_9, b9_9to10_9, b10_9to11_9, b11_9to12_9, b12_9to13_9, b13_9to14_9, b14_9to15_9, b15_9to16_9, b16_9to17_9, b17_9to18_9, b18_9to19_9, b19_9to20_9, b20_9to21_9, b21_9to22_9, b22_9to23_9, b23_9to24_9, b24_9to25_9, b25_9to26_9, b26_9to27_9, b27_9to28_9, b28_9to29_9, b29_9to30_9, b30_9to31_9, b31_9to32_9; +wire [`DWIDTH-1:0] b0_10to1_10, b1_10to2_10, b2_10to3_10, b3_10to4_10, b4_10to5_10, b5_10to6_10, b6_10to7_10, b7_10to8_10, b8_10to9_10, b9_10to10_10, b10_10to11_10, b11_10to12_10, b12_10to13_10, b13_10to14_10, b14_10to15_10, b15_10to16_10, b16_10to17_10, b17_10to18_10, b18_10to19_10, b19_10to20_10, b20_10to21_10, b21_10to22_10, b22_10to23_10, b23_10to24_10, b24_10to25_10, b25_10to26_10, b26_10to27_10, b27_10to28_10, b28_10to29_10, b29_10to30_10, b30_10to31_10, b31_10to32_10; +wire [`DWIDTH-1:0] b0_11to1_11, b1_11to2_11, b2_11to3_11, b3_11to4_11, b4_11to5_11, b5_11to6_11, b6_11to7_11, b7_11to8_11, b8_11to9_11, b9_11to10_11, b10_11to11_11, b11_11to12_11, b12_11to13_11, b13_11to14_11, b14_11to15_11, b15_11to16_11, b16_11to17_11, b17_11to18_11, b18_11to19_11, b19_11to20_11, b20_11to21_11, b21_11to22_11, b22_11to23_11, b23_11to24_11, b24_11to25_11, b25_11to26_11, b26_11to27_11, b27_11to28_11, b28_11to29_11, b29_11to30_11, b30_11to31_11, b31_11to32_11; +wire [`DWIDTH-1:0] b0_12to1_12, b1_12to2_12, b2_12to3_12, b3_12to4_12, b4_12to5_12, b5_12to6_12, b6_12to7_12, b7_12to8_12, b8_12to9_12, b9_12to10_12, b10_12to11_12, b11_12to12_12, b12_12to13_12, b13_12to14_12, b14_12to15_12, b15_12to16_12, b16_12to17_12, b17_12to18_12, b18_12to19_12, b19_12to20_12, b20_12to21_12, b21_12to22_12, b22_12to23_12, b23_12to24_12, b24_12to25_12, b25_12to26_12, b26_12to27_12, b27_12to28_12, b28_12to29_12, b29_12to30_12, b30_12to31_12, b31_12to32_12; +wire [`DWIDTH-1:0] b0_13to1_13, b1_13to2_13, b2_13to3_13, b3_13to4_13, b4_13to5_13, b5_13to6_13, b6_13to7_13, b7_13to8_13, b8_13to9_13, b9_13to10_13, b10_13to11_13, b11_13to12_13, b12_13to13_13, b13_13to14_13, b14_13to15_13, b15_13to16_13, b16_13to17_13, b17_13to18_13, b18_13to19_13, b19_13to20_13, b20_13to21_13, b21_13to22_13, b22_13to23_13, b23_13to24_13, b24_13to25_13, b25_13to26_13, b26_13to27_13, b27_13to28_13, b28_13to29_13, b29_13to30_13, b30_13to31_13, b31_13to32_13; +wire [`DWIDTH-1:0] b0_14to1_14, b1_14to2_14, b2_14to3_14, b3_14to4_14, b4_14to5_14, b5_14to6_14, b6_14to7_14, b7_14to8_14, b8_14to9_14, b9_14to10_14, b10_14to11_14, b11_14to12_14, b12_14to13_14, b13_14to14_14, b14_14to15_14, b15_14to16_14, b16_14to17_14, b17_14to18_14, b18_14to19_14, b19_14to20_14, b20_14to21_14, b21_14to22_14, b22_14to23_14, b23_14to24_14, b24_14to25_14, b25_14to26_14, b26_14to27_14, b27_14to28_14, b28_14to29_14, b29_14to30_14, b30_14to31_14, b31_14to32_14; +wire [`DWIDTH-1:0] b0_15to1_15, b1_15to2_15, b2_15to3_15, b3_15to4_15, b4_15to5_15, b5_15to6_15, b6_15to7_15, b7_15to8_15, b8_15to9_15, b9_15to10_15, b10_15to11_15, b11_15to12_15, b12_15to13_15, b13_15to14_15, b14_15to15_15, b15_15to16_15, b16_15to17_15, b17_15to18_15, b18_15to19_15, b19_15to20_15, b20_15to21_15, b21_15to22_15, b22_15to23_15, b23_15to24_15, b24_15to25_15, b25_15to26_15, b26_15to27_15, b27_15to28_15, b28_15to29_15, b29_15to30_15, b30_15to31_15, b31_15to32_15; +wire [`DWIDTH-1:0] b0_16to1_16, b1_16to2_16, b2_16to3_16, b3_16to4_16, b4_16to5_16, b5_16to6_16, b6_16to7_16, b7_16to8_16, b8_16to9_16, b9_16to10_16, b10_16to11_16, b11_16to12_16, b12_16to13_16, b13_16to14_16, b14_16to15_16, b15_16to16_16, b16_16to17_16, b17_16to18_16, b18_16to19_16, b19_16to20_16, b20_16to21_16, b21_16to22_16, b22_16to23_16, b23_16to24_16, b24_16to25_16, b25_16to26_16, b26_16to27_16, b27_16to28_16, b28_16to29_16, b29_16to30_16, b30_16to31_16, b31_16to32_16; +wire [`DWIDTH-1:0] b0_17to1_17, b1_17to2_17, b2_17to3_17, b3_17to4_17, b4_17to5_17, b5_17to6_17, b6_17to7_17, b7_17to8_17, b8_17to9_17, b9_17to10_17, b10_17to11_17, b11_17to12_17, b12_17to13_17, b13_17to14_17, b14_17to15_17, b15_17to16_17, b16_17to17_17, b17_17to18_17, b18_17to19_17, b19_17to20_17, b20_17to21_17, b21_17to22_17, b22_17to23_17, b23_17to24_17, b24_17to25_17, b25_17to26_17, b26_17to27_17, b27_17to28_17, b28_17to29_17, b29_17to30_17, b30_17to31_17, b31_17to32_17; +wire [`DWIDTH-1:0] b0_18to1_18, b1_18to2_18, b2_18to3_18, b3_18to4_18, b4_18to5_18, b5_18to6_18, b6_18to7_18, b7_18to8_18, b8_18to9_18, b9_18to10_18, b10_18to11_18, b11_18to12_18, b12_18to13_18, b13_18to14_18, b14_18to15_18, b15_18to16_18, b16_18to17_18, b17_18to18_18, b18_18to19_18, b19_18to20_18, b20_18to21_18, b21_18to22_18, b22_18to23_18, b23_18to24_18, b24_18to25_18, b25_18to26_18, b26_18to27_18, b27_18to28_18, b28_18to29_18, b29_18to30_18, b30_18to31_18, b31_18to32_18; +wire [`DWIDTH-1:0] b0_19to1_19, b1_19to2_19, b2_19to3_19, b3_19to4_19, b4_19to5_19, b5_19to6_19, b6_19to7_19, b7_19to8_19, b8_19to9_19, b9_19to10_19, b10_19to11_19, b11_19to12_19, b12_19to13_19, b13_19to14_19, b14_19to15_19, b15_19to16_19, b16_19to17_19, b17_19to18_19, b18_19to19_19, b19_19to20_19, b20_19to21_19, b21_19to22_19, b22_19to23_19, b23_19to24_19, b24_19to25_19, b25_19to26_19, b26_19to27_19, b27_19to28_19, b28_19to29_19, b29_19to30_19, b30_19to31_19, b31_19to32_19; +wire [`DWIDTH-1:0] b0_20to1_20, b1_20to2_20, b2_20to3_20, b3_20to4_20, b4_20to5_20, b5_20to6_20, b6_20to7_20, b7_20to8_20, b8_20to9_20, b9_20to10_20, b10_20to11_20, b11_20to12_20, b12_20to13_20, b13_20to14_20, b14_20to15_20, b15_20to16_20, b16_20to17_20, b17_20to18_20, b18_20to19_20, b19_20to20_20, b20_20to21_20, b21_20to22_20, b22_20to23_20, b23_20to24_20, b24_20to25_20, b25_20to26_20, b26_20to27_20, b27_20to28_20, b28_20to29_20, b29_20to30_20, b30_20to31_20, b31_20to32_20; +wire [`DWIDTH-1:0] b0_21to1_21, b1_21to2_21, b2_21to3_21, b3_21to4_21, b4_21to5_21, b5_21to6_21, b6_21to7_21, b7_21to8_21, b8_21to9_21, b9_21to10_21, b10_21to11_21, b11_21to12_21, b12_21to13_21, b13_21to14_21, b14_21to15_21, b15_21to16_21, b16_21to17_21, b17_21to18_21, b18_21to19_21, b19_21to20_21, b20_21to21_21, b21_21to22_21, b22_21to23_21, b23_21to24_21, b24_21to25_21, b25_21to26_21, b26_21to27_21, b27_21to28_21, b28_21to29_21, b29_21to30_21, b30_21to31_21, b31_21to32_21; +wire [`DWIDTH-1:0] b0_22to1_22, b1_22to2_22, b2_22to3_22, b3_22to4_22, b4_22to5_22, b5_22to6_22, b6_22to7_22, b7_22to8_22, b8_22to9_22, b9_22to10_22, b10_22to11_22, b11_22to12_22, b12_22to13_22, b13_22to14_22, b14_22to15_22, b15_22to16_22, b16_22to17_22, b17_22to18_22, b18_22to19_22, b19_22to20_22, b20_22to21_22, b21_22to22_22, b22_22to23_22, b23_22to24_22, b24_22to25_22, b25_22to26_22, b26_22to27_22, b27_22to28_22, b28_22to29_22, b29_22to30_22, b30_22to31_22, b31_22to32_22; +wire [`DWIDTH-1:0] b0_23to1_23, b1_23to2_23, b2_23to3_23, b3_23to4_23, b4_23to5_23, b5_23to6_23, b6_23to7_23, b7_23to8_23, b8_23to9_23, b9_23to10_23, b10_23to11_23, b11_23to12_23, b12_23to13_23, b13_23to14_23, b14_23to15_23, b15_23to16_23, b16_23to17_23, b17_23to18_23, b18_23to19_23, b19_23to20_23, b20_23to21_23, b21_23to22_23, b22_23to23_23, b23_23to24_23, b24_23to25_23, b25_23to26_23, b26_23to27_23, b27_23to28_23, b28_23to29_23, b29_23to30_23, b30_23to31_23, b31_23to32_23; +wire [`DWIDTH-1:0] b0_24to1_24, b1_24to2_24, b2_24to3_24, b3_24to4_24, b4_24to5_24, b5_24to6_24, b6_24to7_24, b7_24to8_24, b8_24to9_24, b9_24to10_24, b10_24to11_24, b11_24to12_24, b12_24to13_24, b13_24to14_24, b14_24to15_24, b15_24to16_24, b16_24to17_24, b17_24to18_24, b18_24to19_24, b19_24to20_24, b20_24to21_24, b21_24to22_24, b22_24to23_24, b23_24to24_24, b24_24to25_24, b25_24to26_24, b26_24to27_24, b27_24to28_24, b28_24to29_24, b29_24to30_24, b30_24to31_24, b31_24to32_24; +wire [`DWIDTH-1:0] b0_25to1_25, b1_25to2_25, b2_25to3_25, b3_25to4_25, b4_25to5_25, b5_25to6_25, b6_25to7_25, b7_25to8_25, b8_25to9_25, b9_25to10_25, b10_25to11_25, b11_25to12_25, b12_25to13_25, b13_25to14_25, b14_25to15_25, b15_25to16_25, b16_25to17_25, b17_25to18_25, b18_25to19_25, b19_25to20_25, b20_25to21_25, b21_25to22_25, b22_25to23_25, b23_25to24_25, b24_25to25_25, b25_25to26_25, b26_25to27_25, b27_25to28_25, b28_25to29_25, b29_25to30_25, b30_25to31_25, b31_25to32_25; +wire [`DWIDTH-1:0] b0_26to1_26, b1_26to2_26, b2_26to3_26, b3_26to4_26, b4_26to5_26, b5_26to6_26, b6_26to7_26, b7_26to8_26, b8_26to9_26, b9_26to10_26, b10_26to11_26, b11_26to12_26, b12_26to13_26, b13_26to14_26, b14_26to15_26, b15_26to16_26, b16_26to17_26, b17_26to18_26, b18_26to19_26, b19_26to20_26, b20_26to21_26, b21_26to22_26, b22_26to23_26, b23_26to24_26, b24_26to25_26, b25_26to26_26, b26_26to27_26, b27_26to28_26, b28_26to29_26, b29_26to30_26, b30_26to31_26, b31_26to32_26; +wire [`DWIDTH-1:0] b0_27to1_27, b1_27to2_27, b2_27to3_27, b3_27to4_27, b4_27to5_27, b5_27to6_27, b6_27to7_27, b7_27to8_27, b8_27to9_27, b9_27to10_27, b10_27to11_27, b11_27to12_27, b12_27to13_27, b13_27to14_27, b14_27to15_27, b15_27to16_27, b16_27to17_27, b17_27to18_27, b18_27to19_27, b19_27to20_27, b20_27to21_27, b21_27to22_27, b22_27to23_27, b23_27to24_27, b24_27to25_27, b25_27to26_27, b26_27to27_27, b27_27to28_27, b28_27to29_27, b29_27to30_27, b30_27to31_27, b31_27to32_27; +wire [`DWIDTH-1:0] b0_28to1_28, b1_28to2_28, b2_28to3_28, b3_28to4_28, b4_28to5_28, b5_28to6_28, b6_28to7_28, b7_28to8_28, b8_28to9_28, b9_28to10_28, b10_28to11_28, b11_28to12_28, b12_28to13_28, b13_28to14_28, b14_28to15_28, b15_28to16_28, b16_28to17_28, b17_28to18_28, b18_28to19_28, b19_28to20_28, b20_28to21_28, b21_28to22_28, b22_28to23_28, b23_28to24_28, b24_28to25_28, b25_28to26_28, b26_28to27_28, b27_28to28_28, b28_28to29_28, b29_28to30_28, b30_28to31_28, b31_28to32_28; +wire [`DWIDTH-1:0] b0_29to1_29, b1_29to2_29, b2_29to3_29, b3_29to4_29, b4_29to5_29, b5_29to6_29, b6_29to7_29, b7_29to8_29, b8_29to9_29, b9_29to10_29, b10_29to11_29, b11_29to12_29, b12_29to13_29, b13_29to14_29, b14_29to15_29, b15_29to16_29, b16_29to17_29, b17_29to18_29, b18_29to19_29, b19_29to20_29, b20_29to21_29, b21_29to22_29, b22_29to23_29, b23_29to24_29, b24_29to25_29, b25_29to26_29, b26_29to27_29, b27_29to28_29, b28_29to29_29, b29_29to30_29, b30_29to31_29, b31_29to32_29; +wire [`DWIDTH-1:0] b0_30to1_30, b1_30to2_30, b2_30to3_30, b3_30to4_30, b4_30to5_30, b5_30to6_30, b6_30to7_30, b7_30to8_30, b8_30to9_30, b9_30to10_30, b10_30to11_30, b11_30to12_30, b12_30to13_30, b13_30to14_30, b14_30to15_30, b15_30to16_30, b16_30to17_30, b17_30to18_30, b18_30to19_30, b19_30to20_30, b20_30to21_30, b21_30to22_30, b22_30to23_30, b23_30to24_30, b24_30to25_30, b25_30to26_30, b26_30to27_30, b27_30to28_30, b28_30to29_30, b29_30to30_30, b30_30to31_30, b31_30to32_30; +wire [`DWIDTH-1:0] b0_31to1_31, b1_31to2_31, b2_31to3_31, b3_31to4_31, b4_31to5_31, b5_31to6_31, b6_31to7_31, b7_31to8_31, b8_31to9_31, b9_31to10_31, b10_31to11_31, b11_31to12_31, b12_31to13_31, b13_31to14_31, b14_31to15_31, b15_31to16_31, b16_31to17_31, b17_31to18_31, b18_31to19_31, b19_31to20_31, b20_31to21_31, b21_31to22_31, b22_31to23_31, b23_31to24_31, b24_31to25_31, b25_31to26_31, b26_31to27_31, b27_31to28_31, b28_31to29_31, b29_31to30_31, b30_31to31_31, b31_31to32_31; + +wire [`DWIDTH-1:0] b0_0to1_0_ping, b1_0to2_0_ping, b2_0to3_0_ping, b3_0to4_0_ping, b4_0to5_0_ping, b5_0to6_0_ping, b6_0to7_0_ping, b7_0to8_0_ping, b8_0to9_0_ping, b9_0to10_0_ping, b10_0to11_0_ping, b11_0to12_0_ping, b12_0to13_0_ping, b13_0to14_0_ping, b14_0to15_0_ping, b15_0to16_0_ping, b16_0to17_0_ping, b17_0to18_0_ping, b18_0to19_0_ping, b19_0to20_0_ping, b20_0to21_0_ping, b21_0to22_0_ping, b22_0to23_0_ping, b23_0to24_0_ping, b24_0to25_0_ping, b25_0to26_0_ping, b26_0to27_0_ping, b27_0to28_0_ping, b28_0to29_0_ping, b29_0to30_0_ping, b30_0to31_0_ping, b31_0to32_0_ping; +wire [`DWIDTH-1:0] b0_1to1_1_ping, b1_1to2_1_ping, b2_1to3_1_ping, b3_1to4_1_ping, b4_1to5_1_ping, b5_1to6_1_ping, b6_1to7_1_ping, b7_1to8_1_ping, b8_1to9_1_ping, b9_1to10_1_ping, b10_1to11_1_ping, b11_1to12_1_ping, b12_1to13_1_ping, b13_1to14_1_ping, b14_1to15_1_ping, b15_1to16_1_ping, b16_1to17_1_ping, b17_1to18_1_ping, b18_1to19_1_ping, b19_1to20_1_ping, b20_1to21_1_ping, b21_1to22_1_ping, b22_1to23_1_ping, b23_1to24_1_ping, b24_1to25_1_ping, b25_1to26_1_ping, b26_1to27_1_ping, b27_1to28_1_ping, b28_1to29_1_ping, b29_1to30_1_ping, b30_1to31_1_ping, b31_1to32_1_ping; +wire [`DWIDTH-1:0] b0_2to1_2_ping, b1_2to2_2_ping, b2_2to3_2_ping, b3_2to4_2_ping, b4_2to5_2_ping, b5_2to6_2_ping, b6_2to7_2_ping, b7_2to8_2_ping, b8_2to9_2_ping, b9_2to10_2_ping, b10_2to11_2_ping, b11_2to12_2_ping, b12_2to13_2_ping, b13_2to14_2_ping, b14_2to15_2_ping, b15_2to16_2_ping, b16_2to17_2_ping, b17_2to18_2_ping, b18_2to19_2_ping, b19_2to20_2_ping, b20_2to21_2_ping, b21_2to22_2_ping, b22_2to23_2_ping, b23_2to24_2_ping, b24_2to25_2_ping, b25_2to26_2_ping, b26_2to27_2_ping, b27_2to28_2_ping, b28_2to29_2_ping, b29_2to30_2_ping, b30_2to31_2_ping, b31_2to32_2_ping; +wire [`DWIDTH-1:0] b0_3to1_3_ping, b1_3to2_3_ping, b2_3to3_3_ping, b3_3to4_3_ping, b4_3to5_3_ping, b5_3to6_3_ping, b6_3to7_3_ping, b7_3to8_3_ping, b8_3to9_3_ping, b9_3to10_3_ping, b10_3to11_3_ping, b11_3to12_3_ping, b12_3to13_3_ping, b13_3to14_3_ping, b14_3to15_3_ping, b15_3to16_3_ping, b16_3to17_3_ping, b17_3to18_3_ping, b18_3to19_3_ping, b19_3to20_3_ping, b20_3to21_3_ping, b21_3to22_3_ping, b22_3to23_3_ping, b23_3to24_3_ping, b24_3to25_3_ping, b25_3to26_3_ping, b26_3to27_3_ping, b27_3to28_3_ping, b28_3to29_3_ping, b29_3to30_3_ping, b30_3to31_3_ping, b31_3to32_3_ping; +wire [`DWIDTH-1:0] b0_4to1_4_ping, b1_4to2_4_ping, b2_4to3_4_ping, b3_4to4_4_ping, b4_4to5_4_ping, b5_4to6_4_ping, b6_4to7_4_ping, b7_4to8_4_ping, b8_4to9_4_ping, b9_4to10_4_ping, b10_4to11_4_ping, b11_4to12_4_ping, b12_4to13_4_ping, b13_4to14_4_ping, b14_4to15_4_ping, b15_4to16_4_ping, b16_4to17_4_ping, b17_4to18_4_ping, b18_4to19_4_ping, b19_4to20_4_ping, b20_4to21_4_ping, b21_4to22_4_ping, b22_4to23_4_ping, b23_4to24_4_ping, b24_4to25_4_ping, b25_4to26_4_ping, b26_4to27_4_ping, b27_4to28_4_ping, b28_4to29_4_ping, b29_4to30_4_ping, b30_4to31_4_ping, b31_4to32_4_ping; +wire [`DWIDTH-1:0] b0_5to1_5_ping, b1_5to2_5_ping, b2_5to3_5_ping, b3_5to4_5_ping, b4_5to5_5_ping, b5_5to6_5_ping, b6_5to7_5_ping, b7_5to8_5_ping, b8_5to9_5_ping, b9_5to10_5_ping, b10_5to11_5_ping, b11_5to12_5_ping, b12_5to13_5_ping, b13_5to14_5_ping, b14_5to15_5_ping, b15_5to16_5_ping, b16_5to17_5_ping, b17_5to18_5_ping, b18_5to19_5_ping, b19_5to20_5_ping, b20_5to21_5_ping, b21_5to22_5_ping, b22_5to23_5_ping, b23_5to24_5_ping, b24_5to25_5_ping, b25_5to26_5_ping, b26_5to27_5_ping, b27_5to28_5_ping, b28_5to29_5_ping, b29_5to30_5_ping, b30_5to31_5_ping, b31_5to32_5_ping; +wire [`DWIDTH-1:0] b0_6to1_6_ping, b1_6to2_6_ping, b2_6to3_6_ping, b3_6to4_6_ping, b4_6to5_6_ping, b5_6to6_6_ping, b6_6to7_6_ping, b7_6to8_6_ping, b8_6to9_6_ping, b9_6to10_6_ping, b10_6to11_6_ping, b11_6to12_6_ping, b12_6to13_6_ping, b13_6to14_6_ping, b14_6to15_6_ping, b15_6to16_6_ping, b16_6to17_6_ping, b17_6to18_6_ping, b18_6to19_6_ping, b19_6to20_6_ping, b20_6to21_6_ping, b21_6to22_6_ping, b22_6to23_6_ping, b23_6to24_6_ping, b24_6to25_6_ping, b25_6to26_6_ping, b26_6to27_6_ping, b27_6to28_6_ping, b28_6to29_6_ping, b29_6to30_6_ping, b30_6to31_6_ping, b31_6to32_6_ping; +wire [`DWIDTH-1:0] b0_7to1_7_ping, b1_7to2_7_ping, b2_7to3_7_ping, b3_7to4_7_ping, b4_7to5_7_ping, b5_7to6_7_ping, b6_7to7_7_ping, b7_7to8_7_ping, b8_7to9_7_ping, b9_7to10_7_ping, b10_7to11_7_ping, b11_7to12_7_ping, b12_7to13_7_ping, b13_7to14_7_ping, b14_7to15_7_ping, b15_7to16_7_ping, b16_7to17_7_ping, b17_7to18_7_ping, b18_7to19_7_ping, b19_7to20_7_ping, b20_7to21_7_ping, b21_7to22_7_ping, b22_7to23_7_ping, b23_7to24_7_ping, b24_7to25_7_ping, b25_7to26_7_ping, b26_7to27_7_ping, b27_7to28_7_ping, b28_7to29_7_ping, b29_7to30_7_ping, b30_7to31_7_ping, b31_7to32_7_ping; +wire [`DWIDTH-1:0] b0_8to1_8_ping, b1_8to2_8_ping, b2_8to3_8_ping, b3_8to4_8_ping, b4_8to5_8_ping, b5_8to6_8_ping, b6_8to7_8_ping, b7_8to8_8_ping, b8_8to9_8_ping, b9_8to10_8_ping, b10_8to11_8_ping, b11_8to12_8_ping, b12_8to13_8_ping, b13_8to14_8_ping, b14_8to15_8_ping, b15_8to16_8_ping, b16_8to17_8_ping, b17_8to18_8_ping, b18_8to19_8_ping, b19_8to20_8_ping, b20_8to21_8_ping, b21_8to22_8_ping, b22_8to23_8_ping, b23_8to24_8_ping, b24_8to25_8_ping, b25_8to26_8_ping, b26_8to27_8_ping, b27_8to28_8_ping, b28_8to29_8_ping, b29_8to30_8_ping, b30_8to31_8_ping, b31_8to32_8_ping; +wire [`DWIDTH-1:0] b0_9to1_9_ping, b1_9to2_9_ping, b2_9to3_9_ping, b3_9to4_9_ping, b4_9to5_9_ping, b5_9to6_9_ping, b6_9to7_9_ping, b7_9to8_9_ping, b8_9to9_9_ping, b9_9to10_9_ping, b10_9to11_9_ping, b11_9to12_9_ping, b12_9to13_9_ping, b13_9to14_9_ping, b14_9to15_9_ping, b15_9to16_9_ping, b16_9to17_9_ping, b17_9to18_9_ping, b18_9to19_9_ping, b19_9to20_9_ping, b20_9to21_9_ping, b21_9to22_9_ping, b22_9to23_9_ping, b23_9to24_9_ping, b24_9to25_9_ping, b25_9to26_9_ping, b26_9to27_9_ping, b27_9to28_9_ping, b28_9to29_9_ping, b29_9to30_9_ping, b30_9to31_9_ping, b31_9to32_9_ping; +wire [`DWIDTH-1:0] b0_10to1_10_ping, b1_10to2_10_ping, b2_10to3_10_ping, b3_10to4_10_ping, b4_10to5_10_ping, b5_10to6_10_ping, b6_10to7_10_ping, b7_10to8_10_ping, b8_10to9_10_ping, b9_10to10_10_ping, b10_10to11_10_ping, b11_10to12_10_ping, b12_10to13_10_ping, b13_10to14_10_ping, b14_10to15_10_ping, b15_10to16_10_ping, b16_10to17_10_ping, b17_10to18_10_ping, b18_10to19_10_ping, b19_10to20_10_ping, b20_10to21_10_ping, b21_10to22_10_ping, b22_10to23_10_ping, b23_10to24_10_ping, b24_10to25_10_ping, b25_10to26_10_ping, b26_10to27_10_ping, b27_10to28_10_ping, b28_10to29_10_ping, b29_10to30_10_ping, b30_10to31_10_ping, b31_10to32_10_ping; +wire [`DWIDTH-1:0] b0_11to1_11_ping, b1_11to2_11_ping, b2_11to3_11_ping, b3_11to4_11_ping, b4_11to5_11_ping, b5_11to6_11_ping, b6_11to7_11_ping, b7_11to8_11_ping, b8_11to9_11_ping, b9_11to10_11_ping, b10_11to11_11_ping, b11_11to12_11_ping, b12_11to13_11_ping, b13_11to14_11_ping, b14_11to15_11_ping, b15_11to16_11_ping, b16_11to17_11_ping, b17_11to18_11_ping, b18_11to19_11_ping, b19_11to20_11_ping, b20_11to21_11_ping, b21_11to22_11_ping, b22_11to23_11_ping, b23_11to24_11_ping, b24_11to25_11_ping, b25_11to26_11_ping, b26_11to27_11_ping, b27_11to28_11_ping, b28_11to29_11_ping, b29_11to30_11_ping, b30_11to31_11_ping, b31_11to32_11_ping; +wire [`DWIDTH-1:0] b0_12to1_12_ping, b1_12to2_12_ping, b2_12to3_12_ping, b3_12to4_12_ping, b4_12to5_12_ping, b5_12to6_12_ping, b6_12to7_12_ping, b7_12to8_12_ping, b8_12to9_12_ping, b9_12to10_12_ping, b10_12to11_12_ping, b11_12to12_12_ping, b12_12to13_12_ping, b13_12to14_12_ping, b14_12to15_12_ping, b15_12to16_12_ping, b16_12to17_12_ping, b17_12to18_12_ping, b18_12to19_12_ping, b19_12to20_12_ping, b20_12to21_12_ping, b21_12to22_12_ping, b22_12to23_12_ping, b23_12to24_12_ping, b24_12to25_12_ping, b25_12to26_12_ping, b26_12to27_12_ping, b27_12to28_12_ping, b28_12to29_12_ping, b29_12to30_12_ping, b30_12to31_12_ping, b31_12to32_12_ping; +wire [`DWIDTH-1:0] b0_13to1_13_ping, b1_13to2_13_ping, b2_13to3_13_ping, b3_13to4_13_ping, b4_13to5_13_ping, b5_13to6_13_ping, b6_13to7_13_ping, b7_13to8_13_ping, b8_13to9_13_ping, b9_13to10_13_ping, b10_13to11_13_ping, b11_13to12_13_ping, b12_13to13_13_ping, b13_13to14_13_ping, b14_13to15_13_ping, b15_13to16_13_ping, b16_13to17_13_ping, b17_13to18_13_ping, b18_13to19_13_ping, b19_13to20_13_ping, b20_13to21_13_ping, b21_13to22_13_ping, b22_13to23_13_ping, b23_13to24_13_ping, b24_13to25_13_ping, b25_13to26_13_ping, b26_13to27_13_ping, b27_13to28_13_ping, b28_13to29_13_ping, b29_13to30_13_ping, b30_13to31_13_ping, b31_13to32_13_ping; +wire [`DWIDTH-1:0] b0_14to1_14_ping, b1_14to2_14_ping, b2_14to3_14_ping, b3_14to4_14_ping, b4_14to5_14_ping, b5_14to6_14_ping, b6_14to7_14_ping, b7_14to8_14_ping, b8_14to9_14_ping, b9_14to10_14_ping, b10_14to11_14_ping, b11_14to12_14_ping, b12_14to13_14_ping, b13_14to14_14_ping, b14_14to15_14_ping, b15_14to16_14_ping, b16_14to17_14_ping, b17_14to18_14_ping, b18_14to19_14_ping, b19_14to20_14_ping, b20_14to21_14_ping, b21_14to22_14_ping, b22_14to23_14_ping, b23_14to24_14_ping, b24_14to25_14_ping, b25_14to26_14_ping, b26_14to27_14_ping, b27_14to28_14_ping, b28_14to29_14_ping, b29_14to30_14_ping, b30_14to31_14_ping, b31_14to32_14_ping; +wire [`DWIDTH-1:0] b0_15to1_15_ping, b1_15to2_15_ping, b2_15to3_15_ping, b3_15to4_15_ping, b4_15to5_15_ping, b5_15to6_15_ping, b6_15to7_15_ping, b7_15to8_15_ping, b8_15to9_15_ping, b9_15to10_15_ping, b10_15to11_15_ping, b11_15to12_15_ping, b12_15to13_15_ping, b13_15to14_15_ping, b14_15to15_15_ping, b15_15to16_15_ping, b16_15to17_15_ping, b17_15to18_15_ping, b18_15to19_15_ping, b19_15to20_15_ping, b20_15to21_15_ping, b21_15to22_15_ping, b22_15to23_15_ping, b23_15to24_15_ping, b24_15to25_15_ping, b25_15to26_15_ping, b26_15to27_15_ping, b27_15to28_15_ping, b28_15to29_15_ping, b29_15to30_15_ping, b30_15to31_15_ping, b31_15to32_15_ping; +wire [`DWIDTH-1:0] b0_16to1_16_ping, b1_16to2_16_ping, b2_16to3_16_ping, b3_16to4_16_ping, b4_16to5_16_ping, b5_16to6_16_ping, b6_16to7_16_ping, b7_16to8_16_ping, b8_16to9_16_ping, b9_16to10_16_ping, b10_16to11_16_ping, b11_16to12_16_ping, b12_16to13_16_ping, b13_16to14_16_ping, b14_16to15_16_ping, b15_16to16_16_ping, b16_16to17_16_ping, b17_16to18_16_ping, b18_16to19_16_ping, b19_16to20_16_ping, b20_16to21_16_ping, b21_16to22_16_ping, b22_16to23_16_ping, b23_16to24_16_ping, b24_16to25_16_ping, b25_16to26_16_ping, b26_16to27_16_ping, b27_16to28_16_ping, b28_16to29_16_ping, b29_16to30_16_ping, b30_16to31_16_ping, b31_16to32_16_ping; +wire [`DWIDTH-1:0] b0_17to1_17_ping, b1_17to2_17_ping, b2_17to3_17_ping, b3_17to4_17_ping, b4_17to5_17_ping, b5_17to6_17_ping, b6_17to7_17_ping, b7_17to8_17_ping, b8_17to9_17_ping, b9_17to10_17_ping, b10_17to11_17_ping, b11_17to12_17_ping, b12_17to13_17_ping, b13_17to14_17_ping, b14_17to15_17_ping, b15_17to16_17_ping, b16_17to17_17_ping, b17_17to18_17_ping, b18_17to19_17_ping, b19_17to20_17_ping, b20_17to21_17_ping, b21_17to22_17_ping, b22_17to23_17_ping, b23_17to24_17_ping, b24_17to25_17_ping, b25_17to26_17_ping, b26_17to27_17_ping, b27_17to28_17_ping, b28_17to29_17_ping, b29_17to30_17_ping, b30_17to31_17_ping, b31_17to32_17_ping; +wire [`DWIDTH-1:0] b0_18to1_18_ping, b1_18to2_18_ping, b2_18to3_18_ping, b3_18to4_18_ping, b4_18to5_18_ping, b5_18to6_18_ping, b6_18to7_18_ping, b7_18to8_18_ping, b8_18to9_18_ping, b9_18to10_18_ping, b10_18to11_18_ping, b11_18to12_18_ping, b12_18to13_18_ping, b13_18to14_18_ping, b14_18to15_18_ping, b15_18to16_18_ping, b16_18to17_18_ping, b17_18to18_18_ping, b18_18to19_18_ping, b19_18to20_18_ping, b20_18to21_18_ping, b21_18to22_18_ping, b22_18to23_18_ping, b23_18to24_18_ping, b24_18to25_18_ping, b25_18to26_18_ping, b26_18to27_18_ping, b27_18to28_18_ping, b28_18to29_18_ping, b29_18to30_18_ping, b30_18to31_18_ping, b31_18to32_18_ping; +wire [`DWIDTH-1:0] b0_19to1_19_ping, b1_19to2_19_ping, b2_19to3_19_ping, b3_19to4_19_ping, b4_19to5_19_ping, b5_19to6_19_ping, b6_19to7_19_ping, b7_19to8_19_ping, b8_19to9_19_ping, b9_19to10_19_ping, b10_19to11_19_ping, b11_19to12_19_ping, b12_19to13_19_ping, b13_19to14_19_ping, b14_19to15_19_ping, b15_19to16_19_ping, b16_19to17_19_ping, b17_19to18_19_ping, b18_19to19_19_ping, b19_19to20_19_ping, b20_19to21_19_ping, b21_19to22_19_ping, b22_19to23_19_ping, b23_19to24_19_ping, b24_19to25_19_ping, b25_19to26_19_ping, b26_19to27_19_ping, b27_19to28_19_ping, b28_19to29_19_ping, b29_19to30_19_ping, b30_19to31_19_ping, b31_19to32_19_ping; +wire [`DWIDTH-1:0] b0_20to1_20_ping, b1_20to2_20_ping, b2_20to3_20_ping, b3_20to4_20_ping, b4_20to5_20_ping, b5_20to6_20_ping, b6_20to7_20_ping, b7_20to8_20_ping, b8_20to9_20_ping, b9_20to10_20_ping, b10_20to11_20_ping, b11_20to12_20_ping, b12_20to13_20_ping, b13_20to14_20_ping, b14_20to15_20_ping, b15_20to16_20_ping, b16_20to17_20_ping, b17_20to18_20_ping, b18_20to19_20_ping, b19_20to20_20_ping, b20_20to21_20_ping, b21_20to22_20_ping, b22_20to23_20_ping, b23_20to24_20_ping, b24_20to25_20_ping, b25_20to26_20_ping, b26_20to27_20_ping, b27_20to28_20_ping, b28_20to29_20_ping, b29_20to30_20_ping, b30_20to31_20_ping, b31_20to32_20_ping; +wire [`DWIDTH-1:0] b0_21to1_21_ping, b1_21to2_21_ping, b2_21to3_21_ping, b3_21to4_21_ping, b4_21to5_21_ping, b5_21to6_21_ping, b6_21to7_21_ping, b7_21to8_21_ping, b8_21to9_21_ping, b9_21to10_21_ping, b10_21to11_21_ping, b11_21to12_21_ping, b12_21to13_21_ping, b13_21to14_21_ping, b14_21to15_21_ping, b15_21to16_21_ping, b16_21to17_21_ping, b17_21to18_21_ping, b18_21to19_21_ping, b19_21to20_21_ping, b20_21to21_21_ping, b21_21to22_21_ping, b22_21to23_21_ping, b23_21to24_21_ping, b24_21to25_21_ping, b25_21to26_21_ping, b26_21to27_21_ping, b27_21to28_21_ping, b28_21to29_21_ping, b29_21to30_21_ping, b30_21to31_21_ping, b31_21to32_21_ping; +wire [`DWIDTH-1:0] b0_22to1_22_ping, b1_22to2_22_ping, b2_22to3_22_ping, b3_22to4_22_ping, b4_22to5_22_ping, b5_22to6_22_ping, b6_22to7_22_ping, b7_22to8_22_ping, b8_22to9_22_ping, b9_22to10_22_ping, b10_22to11_22_ping, b11_22to12_22_ping, b12_22to13_22_ping, b13_22to14_22_ping, b14_22to15_22_ping, b15_22to16_22_ping, b16_22to17_22_ping, b17_22to18_22_ping, b18_22to19_22_ping, b19_22to20_22_ping, b20_22to21_22_ping, b21_22to22_22_ping, b22_22to23_22_ping, b23_22to24_22_ping, b24_22to25_22_ping, b25_22to26_22_ping, b26_22to27_22_ping, b27_22to28_22_ping, b28_22to29_22_ping, b29_22to30_22_ping, b30_22to31_22_ping, b31_22to32_22_ping; +wire [`DWIDTH-1:0] b0_23to1_23_ping, b1_23to2_23_ping, b2_23to3_23_ping, b3_23to4_23_ping, b4_23to5_23_ping, b5_23to6_23_ping, b6_23to7_23_ping, b7_23to8_23_ping, b8_23to9_23_ping, b9_23to10_23_ping, b10_23to11_23_ping, b11_23to12_23_ping, b12_23to13_23_ping, b13_23to14_23_ping, b14_23to15_23_ping, b15_23to16_23_ping, b16_23to17_23_ping, b17_23to18_23_ping, b18_23to19_23_ping, b19_23to20_23_ping, b20_23to21_23_ping, b21_23to22_23_ping, b22_23to23_23_ping, b23_23to24_23_ping, b24_23to25_23_ping, b25_23to26_23_ping, b26_23to27_23_ping, b27_23to28_23_ping, b28_23to29_23_ping, b29_23to30_23_ping, b30_23to31_23_ping, b31_23to32_23_ping; +wire [`DWIDTH-1:0] b0_24to1_24_ping, b1_24to2_24_ping, b2_24to3_24_ping, b3_24to4_24_ping, b4_24to5_24_ping, b5_24to6_24_ping, b6_24to7_24_ping, b7_24to8_24_ping, b8_24to9_24_ping, b9_24to10_24_ping, b10_24to11_24_ping, b11_24to12_24_ping, b12_24to13_24_ping, b13_24to14_24_ping, b14_24to15_24_ping, b15_24to16_24_ping, b16_24to17_24_ping, b17_24to18_24_ping, b18_24to19_24_ping, b19_24to20_24_ping, b20_24to21_24_ping, b21_24to22_24_ping, b22_24to23_24_ping, b23_24to24_24_ping, b24_24to25_24_ping, b25_24to26_24_ping, b26_24to27_24_ping, b27_24to28_24_ping, b28_24to29_24_ping, b29_24to30_24_ping, b30_24to31_24_ping, b31_24to32_24_ping; +wire [`DWIDTH-1:0] b0_25to1_25_ping, b1_25to2_25_ping, b2_25to3_25_ping, b3_25to4_25_ping, b4_25to5_25_ping, b5_25to6_25_ping, b6_25to7_25_ping, b7_25to8_25_ping, b8_25to9_25_ping, b9_25to10_25_ping, b10_25to11_25_ping, b11_25to12_25_ping, b12_25to13_25_ping, b13_25to14_25_ping, b14_25to15_25_ping, b15_25to16_25_ping, b16_25to17_25_ping, b17_25to18_25_ping, b18_25to19_25_ping, b19_25to20_25_ping, b20_25to21_25_ping, b21_25to22_25_ping, b22_25to23_25_ping, b23_25to24_25_ping, b24_25to25_25_ping, b25_25to26_25_ping, b26_25to27_25_ping, b27_25to28_25_ping, b28_25to29_25_ping, b29_25to30_25_ping, b30_25to31_25_ping, b31_25to32_25_ping; +wire [`DWIDTH-1:0] b0_26to1_26_ping, b1_26to2_26_ping, b2_26to3_26_ping, b3_26to4_26_ping, b4_26to5_26_ping, b5_26to6_26_ping, b6_26to7_26_ping, b7_26to8_26_ping, b8_26to9_26_ping, b9_26to10_26_ping, b10_26to11_26_ping, b11_26to12_26_ping, b12_26to13_26_ping, b13_26to14_26_ping, b14_26to15_26_ping, b15_26to16_26_ping, b16_26to17_26_ping, b17_26to18_26_ping, b18_26to19_26_ping, b19_26to20_26_ping, b20_26to21_26_ping, b21_26to22_26_ping, b22_26to23_26_ping, b23_26to24_26_ping, b24_26to25_26_ping, b25_26to26_26_ping, b26_26to27_26_ping, b27_26to28_26_ping, b28_26to29_26_ping, b29_26to30_26_ping, b30_26to31_26_ping, b31_26to32_26_ping; +wire [`DWIDTH-1:0] b0_27to1_27_ping, b1_27to2_27_ping, b2_27to3_27_ping, b3_27to4_27_ping, b4_27to5_27_ping, b5_27to6_27_ping, b6_27to7_27_ping, b7_27to8_27_ping, b8_27to9_27_ping, b9_27to10_27_ping, b10_27to11_27_ping, b11_27to12_27_ping, b12_27to13_27_ping, b13_27to14_27_ping, b14_27to15_27_ping, b15_27to16_27_ping, b16_27to17_27_ping, b17_27to18_27_ping, b18_27to19_27_ping, b19_27to20_27_ping, b20_27to21_27_ping, b21_27to22_27_ping, b22_27to23_27_ping, b23_27to24_27_ping, b24_27to25_27_ping, b25_27to26_27_ping, b26_27to27_27_ping, b27_27to28_27_ping, b28_27to29_27_ping, b29_27to30_27_ping, b30_27to31_27_ping, b31_27to32_27_ping; +wire [`DWIDTH-1:0] b0_28to1_28_ping, b1_28to2_28_ping, b2_28to3_28_ping, b3_28to4_28_ping, b4_28to5_28_ping, b5_28to6_28_ping, b6_28to7_28_ping, b7_28to8_28_ping, b8_28to9_28_ping, b9_28to10_28_ping, b10_28to11_28_ping, b11_28to12_28_ping, b12_28to13_28_ping, b13_28to14_28_ping, b14_28to15_28_ping, b15_28to16_28_ping, b16_28to17_28_ping, b17_28to18_28_ping, b18_28to19_28_ping, b19_28to20_28_ping, b20_28to21_28_ping, b21_28to22_28_ping, b22_28to23_28_ping, b23_28to24_28_ping, b24_28to25_28_ping, b25_28to26_28_ping, b26_28to27_28_ping, b27_28to28_28_ping, b28_28to29_28_ping, b29_28to30_28_ping, b30_28to31_28_ping, b31_28to32_28_ping; +wire [`DWIDTH-1:0] b0_29to1_29_ping, b1_29to2_29_ping, b2_29to3_29_ping, b3_29to4_29_ping, b4_29to5_29_ping, b5_29to6_29_ping, b6_29to7_29_ping, b7_29to8_29_ping, b8_29to9_29_ping, b9_29to10_29_ping, b10_29to11_29_ping, b11_29to12_29_ping, b12_29to13_29_ping, b13_29to14_29_ping, b14_29to15_29_ping, b15_29to16_29_ping, b16_29to17_29_ping, b17_29to18_29_ping, b18_29to19_29_ping, b19_29to20_29_ping, b20_29to21_29_ping, b21_29to22_29_ping, b22_29to23_29_ping, b23_29to24_29_ping, b24_29to25_29_ping, b25_29to26_29_ping, b26_29to27_29_ping, b27_29to28_29_ping, b28_29to29_29_ping, b29_29to30_29_ping, b30_29to31_29_ping, b31_29to32_29_ping; +wire [`DWIDTH-1:0] b0_30to1_30_ping, b1_30to2_30_ping, b2_30to3_30_ping, b3_30to4_30_ping, b4_30to5_30_ping, b5_30to6_30_ping, b6_30to7_30_ping, b7_30to8_30_ping, b8_30to9_30_ping, b9_30to10_30_ping, b10_30to11_30_ping, b11_30to12_30_ping, b12_30to13_30_ping, b13_30to14_30_ping, b14_30to15_30_ping, b15_30to16_30_ping, b16_30to17_30_ping, b17_30to18_30_ping, b18_30to19_30_ping, b19_30to20_30_ping, b20_30to21_30_ping, b21_30to22_30_ping, b22_30to23_30_ping, b23_30to24_30_ping, b24_30to25_30_ping, b25_30to26_30_ping, b26_30to27_30_ping, b27_30to28_30_ping, b28_30to29_30_ping, b29_30to30_30_ping, b30_30to31_30_ping, b31_30to32_30_ping; +wire [`DWIDTH-1:0] b0_31to1_31_ping, b1_31to2_31_ping, b2_31to3_31_ping, b3_31to4_31_ping, b4_31to5_31_ping, b5_31to6_31_ping, b6_31to7_31_ping, b7_31to8_31_ping, b8_31to9_31_ping, b9_31to10_31_ping, b10_31to11_31_ping, b11_31to12_31_ping, b12_31to13_31_ping, b13_31to14_31_ping, b14_31to15_31_ping, b15_31to16_31_ping, b16_31to17_31_ping, b17_31to18_31_ping, b18_31to19_31_ping, b19_31to20_31_ping, b20_31to21_31_ping, b21_31to22_31_ping, b22_31to23_31_ping, b23_31to24_31_ping, b24_31to25_31_ping, b25_31to26_31_ping, b26_31to27_31_ping, b27_31to28_31_ping, b28_31to29_31_ping, b29_31to30_31_ping, b30_31to31_31_ping, b31_31to32_31_ping; + +wire [`DWIDTH-1:0] b0_0to1_0_pong, b1_0to2_0_pong, b2_0to3_0_pong, b3_0to4_0_pong, b4_0to5_0_pong, b5_0to6_0_pong, b6_0to7_0_pong, b7_0to8_0_pong, b8_0to9_0_pong, b9_0to10_0_pong, b10_0to11_0_pong, b11_0to12_0_pong, b12_0to13_0_pong, b13_0to14_0_pong, b14_0to15_0_pong, b15_0to16_0_pong, b16_0to17_0_pong, b17_0to18_0_pong, b18_0to19_0_pong, b19_0to20_0_pong, b20_0to21_0_pong, b21_0to22_0_pong, b22_0to23_0_pong, b23_0to24_0_pong, b24_0to25_0_pong, b25_0to26_0_pong, b26_0to27_0_pong, b27_0to28_0_pong, b28_0to29_0_pong, b29_0to30_0_pong, b30_0to31_0_pong, b31_0to32_0_pong; +wire [`DWIDTH-1:0] b0_1to1_1_pong, b1_1to2_1_pong, b2_1to3_1_pong, b3_1to4_1_pong, b4_1to5_1_pong, b5_1to6_1_pong, b6_1to7_1_pong, b7_1to8_1_pong, b8_1to9_1_pong, b9_1to10_1_pong, b10_1to11_1_pong, b11_1to12_1_pong, b12_1to13_1_pong, b13_1to14_1_pong, b14_1to15_1_pong, b15_1to16_1_pong, b16_1to17_1_pong, b17_1to18_1_pong, b18_1to19_1_pong, b19_1to20_1_pong, b20_1to21_1_pong, b21_1to22_1_pong, b22_1to23_1_pong, b23_1to24_1_pong, b24_1to25_1_pong, b25_1to26_1_pong, b26_1to27_1_pong, b27_1to28_1_pong, b28_1to29_1_pong, b29_1to30_1_pong, b30_1to31_1_pong, b31_1to32_1_pong; +wire [`DWIDTH-1:0] b0_2to1_2_pong, b1_2to2_2_pong, b2_2to3_2_pong, b3_2to4_2_pong, b4_2to5_2_pong, b5_2to6_2_pong, b6_2to7_2_pong, b7_2to8_2_pong, b8_2to9_2_pong, b9_2to10_2_pong, b10_2to11_2_pong, b11_2to12_2_pong, b12_2to13_2_pong, b13_2to14_2_pong, b14_2to15_2_pong, b15_2to16_2_pong, b16_2to17_2_pong, b17_2to18_2_pong, b18_2to19_2_pong, b19_2to20_2_pong, b20_2to21_2_pong, b21_2to22_2_pong, b22_2to23_2_pong, b23_2to24_2_pong, b24_2to25_2_pong, b25_2to26_2_pong, b26_2to27_2_pong, b27_2to28_2_pong, b28_2to29_2_pong, b29_2to30_2_pong, b30_2to31_2_pong, b31_2to32_2_pong; +wire [`DWIDTH-1:0] b0_3to1_3_pong, b1_3to2_3_pong, b2_3to3_3_pong, b3_3to4_3_pong, b4_3to5_3_pong, b5_3to6_3_pong, b6_3to7_3_pong, b7_3to8_3_pong, b8_3to9_3_pong, b9_3to10_3_pong, b10_3to11_3_pong, b11_3to12_3_pong, b12_3to13_3_pong, b13_3to14_3_pong, b14_3to15_3_pong, b15_3to16_3_pong, b16_3to17_3_pong, b17_3to18_3_pong, b18_3to19_3_pong, b19_3to20_3_pong, b20_3to21_3_pong, b21_3to22_3_pong, b22_3to23_3_pong, b23_3to24_3_pong, b24_3to25_3_pong, b25_3to26_3_pong, b26_3to27_3_pong, b27_3to28_3_pong, b28_3to29_3_pong, b29_3to30_3_pong, b30_3to31_3_pong, b31_3to32_3_pong; +wire [`DWIDTH-1:0] b0_4to1_4_pong, b1_4to2_4_pong, b2_4to3_4_pong, b3_4to4_4_pong, b4_4to5_4_pong, b5_4to6_4_pong, b6_4to7_4_pong, b7_4to8_4_pong, b8_4to9_4_pong, b9_4to10_4_pong, b10_4to11_4_pong, b11_4to12_4_pong, b12_4to13_4_pong, b13_4to14_4_pong, b14_4to15_4_pong, b15_4to16_4_pong, b16_4to17_4_pong, b17_4to18_4_pong, b18_4to19_4_pong, b19_4to20_4_pong, b20_4to21_4_pong, b21_4to22_4_pong, b22_4to23_4_pong, b23_4to24_4_pong, b24_4to25_4_pong, b25_4to26_4_pong, b26_4to27_4_pong, b27_4to28_4_pong, b28_4to29_4_pong, b29_4to30_4_pong, b30_4to31_4_pong, b31_4to32_4_pong; +wire [`DWIDTH-1:0] b0_5to1_5_pong, b1_5to2_5_pong, b2_5to3_5_pong, b3_5to4_5_pong, b4_5to5_5_pong, b5_5to6_5_pong, b6_5to7_5_pong, b7_5to8_5_pong, b8_5to9_5_pong, b9_5to10_5_pong, b10_5to11_5_pong, b11_5to12_5_pong, b12_5to13_5_pong, b13_5to14_5_pong, b14_5to15_5_pong, b15_5to16_5_pong, b16_5to17_5_pong, b17_5to18_5_pong, b18_5to19_5_pong, b19_5to20_5_pong, b20_5to21_5_pong, b21_5to22_5_pong, b22_5to23_5_pong, b23_5to24_5_pong, b24_5to25_5_pong, b25_5to26_5_pong, b26_5to27_5_pong, b27_5to28_5_pong, b28_5to29_5_pong, b29_5to30_5_pong, b30_5to31_5_pong, b31_5to32_5_pong; +wire [`DWIDTH-1:0] b0_6to1_6_pong, b1_6to2_6_pong, b2_6to3_6_pong, b3_6to4_6_pong, b4_6to5_6_pong, b5_6to6_6_pong, b6_6to7_6_pong, b7_6to8_6_pong, b8_6to9_6_pong, b9_6to10_6_pong, b10_6to11_6_pong, b11_6to12_6_pong, b12_6to13_6_pong, b13_6to14_6_pong, b14_6to15_6_pong, b15_6to16_6_pong, b16_6to17_6_pong, b17_6to18_6_pong, b18_6to19_6_pong, b19_6to20_6_pong, b20_6to21_6_pong, b21_6to22_6_pong, b22_6to23_6_pong, b23_6to24_6_pong, b24_6to25_6_pong, b25_6to26_6_pong, b26_6to27_6_pong, b27_6to28_6_pong, b28_6to29_6_pong, b29_6to30_6_pong, b30_6to31_6_pong, b31_6to32_6_pong; +wire [`DWIDTH-1:0] b0_7to1_7_pong, b1_7to2_7_pong, b2_7to3_7_pong, b3_7to4_7_pong, b4_7to5_7_pong, b5_7to6_7_pong, b6_7to7_7_pong, b7_7to8_7_pong, b8_7to9_7_pong, b9_7to10_7_pong, b10_7to11_7_pong, b11_7to12_7_pong, b12_7to13_7_pong, b13_7to14_7_pong, b14_7to15_7_pong, b15_7to16_7_pong, b16_7to17_7_pong, b17_7to18_7_pong, b18_7to19_7_pong, b19_7to20_7_pong, b20_7to21_7_pong, b21_7to22_7_pong, b22_7to23_7_pong, b23_7to24_7_pong, b24_7to25_7_pong, b25_7to26_7_pong, b26_7to27_7_pong, b27_7to28_7_pong, b28_7to29_7_pong, b29_7to30_7_pong, b30_7to31_7_pong, b31_7to32_7_pong; +wire [`DWIDTH-1:0] b0_8to1_8_pong, b1_8to2_8_pong, b2_8to3_8_pong, b3_8to4_8_pong, b4_8to5_8_pong, b5_8to6_8_pong, b6_8to7_8_pong, b7_8to8_8_pong, b8_8to9_8_pong, b9_8to10_8_pong, b10_8to11_8_pong, b11_8to12_8_pong, b12_8to13_8_pong, b13_8to14_8_pong, b14_8to15_8_pong, b15_8to16_8_pong, b16_8to17_8_pong, b17_8to18_8_pong, b18_8to19_8_pong, b19_8to20_8_pong, b20_8to21_8_pong, b21_8to22_8_pong, b22_8to23_8_pong, b23_8to24_8_pong, b24_8to25_8_pong, b25_8to26_8_pong, b26_8to27_8_pong, b27_8to28_8_pong, b28_8to29_8_pong, b29_8to30_8_pong, b30_8to31_8_pong, b31_8to32_8_pong; +wire [`DWIDTH-1:0] b0_9to1_9_pong, b1_9to2_9_pong, b2_9to3_9_pong, b3_9to4_9_pong, b4_9to5_9_pong, b5_9to6_9_pong, b6_9to7_9_pong, b7_9to8_9_pong, b8_9to9_9_pong, b9_9to10_9_pong, b10_9to11_9_pong, b11_9to12_9_pong, b12_9to13_9_pong, b13_9to14_9_pong, b14_9to15_9_pong, b15_9to16_9_pong, b16_9to17_9_pong, b17_9to18_9_pong, b18_9to19_9_pong, b19_9to20_9_pong, b20_9to21_9_pong, b21_9to22_9_pong, b22_9to23_9_pong, b23_9to24_9_pong, b24_9to25_9_pong, b25_9to26_9_pong, b26_9to27_9_pong, b27_9to28_9_pong, b28_9to29_9_pong, b29_9to30_9_pong, b30_9to31_9_pong, b31_9to32_9_pong; +wire [`DWIDTH-1:0] b0_10to1_10_pong, b1_10to2_10_pong, b2_10to3_10_pong, b3_10to4_10_pong, b4_10to5_10_pong, b5_10to6_10_pong, b6_10to7_10_pong, b7_10to8_10_pong, b8_10to9_10_pong, b9_10to10_10_pong, b10_10to11_10_pong, b11_10to12_10_pong, b12_10to13_10_pong, b13_10to14_10_pong, b14_10to15_10_pong, b15_10to16_10_pong, b16_10to17_10_pong, b17_10to18_10_pong, b18_10to19_10_pong, b19_10to20_10_pong, b20_10to21_10_pong, b21_10to22_10_pong, b22_10to23_10_pong, b23_10to24_10_pong, b24_10to25_10_pong, b25_10to26_10_pong, b26_10to27_10_pong, b27_10to28_10_pong, b28_10to29_10_pong, b29_10to30_10_pong, b30_10to31_10_pong, b31_10to32_10_pong; +wire [`DWIDTH-1:0] b0_11to1_11_pong, b1_11to2_11_pong, b2_11to3_11_pong, b3_11to4_11_pong, b4_11to5_11_pong, b5_11to6_11_pong, b6_11to7_11_pong, b7_11to8_11_pong, b8_11to9_11_pong, b9_11to10_11_pong, b10_11to11_11_pong, b11_11to12_11_pong, b12_11to13_11_pong, b13_11to14_11_pong, b14_11to15_11_pong, b15_11to16_11_pong, b16_11to17_11_pong, b17_11to18_11_pong, b18_11to19_11_pong, b19_11to20_11_pong, b20_11to21_11_pong, b21_11to22_11_pong, b22_11to23_11_pong, b23_11to24_11_pong, b24_11to25_11_pong, b25_11to26_11_pong, b26_11to27_11_pong, b27_11to28_11_pong, b28_11to29_11_pong, b29_11to30_11_pong, b30_11to31_11_pong, b31_11to32_11_pong; +wire [`DWIDTH-1:0] b0_12to1_12_pong, b1_12to2_12_pong, b2_12to3_12_pong, b3_12to4_12_pong, b4_12to5_12_pong, b5_12to6_12_pong, b6_12to7_12_pong, b7_12to8_12_pong, b8_12to9_12_pong, b9_12to10_12_pong, b10_12to11_12_pong, b11_12to12_12_pong, b12_12to13_12_pong, b13_12to14_12_pong, b14_12to15_12_pong, b15_12to16_12_pong, b16_12to17_12_pong, b17_12to18_12_pong, b18_12to19_12_pong, b19_12to20_12_pong, b20_12to21_12_pong, b21_12to22_12_pong, b22_12to23_12_pong, b23_12to24_12_pong, b24_12to25_12_pong, b25_12to26_12_pong, b26_12to27_12_pong, b27_12to28_12_pong, b28_12to29_12_pong, b29_12to30_12_pong, b30_12to31_12_pong, b31_12to32_12_pong; +wire [`DWIDTH-1:0] b0_13to1_13_pong, b1_13to2_13_pong, b2_13to3_13_pong, b3_13to4_13_pong, b4_13to5_13_pong, b5_13to6_13_pong, b6_13to7_13_pong, b7_13to8_13_pong, b8_13to9_13_pong, b9_13to10_13_pong, b10_13to11_13_pong, b11_13to12_13_pong, b12_13to13_13_pong, b13_13to14_13_pong, b14_13to15_13_pong, b15_13to16_13_pong, b16_13to17_13_pong, b17_13to18_13_pong, b18_13to19_13_pong, b19_13to20_13_pong, b20_13to21_13_pong, b21_13to22_13_pong, b22_13to23_13_pong, b23_13to24_13_pong, b24_13to25_13_pong, b25_13to26_13_pong, b26_13to27_13_pong, b27_13to28_13_pong, b28_13to29_13_pong, b29_13to30_13_pong, b30_13to31_13_pong, b31_13to32_13_pong; +wire [`DWIDTH-1:0] b0_14to1_14_pong, b1_14to2_14_pong, b2_14to3_14_pong, b3_14to4_14_pong, b4_14to5_14_pong, b5_14to6_14_pong, b6_14to7_14_pong, b7_14to8_14_pong, b8_14to9_14_pong, b9_14to10_14_pong, b10_14to11_14_pong, b11_14to12_14_pong, b12_14to13_14_pong, b13_14to14_14_pong, b14_14to15_14_pong, b15_14to16_14_pong, b16_14to17_14_pong, b17_14to18_14_pong, b18_14to19_14_pong, b19_14to20_14_pong, b20_14to21_14_pong, b21_14to22_14_pong, b22_14to23_14_pong, b23_14to24_14_pong, b24_14to25_14_pong, b25_14to26_14_pong, b26_14to27_14_pong, b27_14to28_14_pong, b28_14to29_14_pong, b29_14to30_14_pong, b30_14to31_14_pong, b31_14to32_14_pong; +wire [`DWIDTH-1:0] b0_15to1_15_pong, b1_15to2_15_pong, b2_15to3_15_pong, b3_15to4_15_pong, b4_15to5_15_pong, b5_15to6_15_pong, b6_15to7_15_pong, b7_15to8_15_pong, b8_15to9_15_pong, b9_15to10_15_pong, b10_15to11_15_pong, b11_15to12_15_pong, b12_15to13_15_pong, b13_15to14_15_pong, b14_15to15_15_pong, b15_15to16_15_pong, b16_15to17_15_pong, b17_15to18_15_pong, b18_15to19_15_pong, b19_15to20_15_pong, b20_15to21_15_pong, b21_15to22_15_pong, b22_15to23_15_pong, b23_15to24_15_pong, b24_15to25_15_pong, b25_15to26_15_pong, b26_15to27_15_pong, b27_15to28_15_pong, b28_15to29_15_pong, b29_15to30_15_pong, b30_15to31_15_pong, b31_15to32_15_pong; +wire [`DWIDTH-1:0] b0_16to1_16_pong, b1_16to2_16_pong, b2_16to3_16_pong, b3_16to4_16_pong, b4_16to5_16_pong, b5_16to6_16_pong, b6_16to7_16_pong, b7_16to8_16_pong, b8_16to9_16_pong, b9_16to10_16_pong, b10_16to11_16_pong, b11_16to12_16_pong, b12_16to13_16_pong, b13_16to14_16_pong, b14_16to15_16_pong, b15_16to16_16_pong, b16_16to17_16_pong, b17_16to18_16_pong, b18_16to19_16_pong, b19_16to20_16_pong, b20_16to21_16_pong, b21_16to22_16_pong, b22_16to23_16_pong, b23_16to24_16_pong, b24_16to25_16_pong, b25_16to26_16_pong, b26_16to27_16_pong, b27_16to28_16_pong, b28_16to29_16_pong, b29_16to30_16_pong, b30_16to31_16_pong, b31_16to32_16_pong; +wire [`DWIDTH-1:0] b0_17to1_17_pong, b1_17to2_17_pong, b2_17to3_17_pong, b3_17to4_17_pong, b4_17to5_17_pong, b5_17to6_17_pong, b6_17to7_17_pong, b7_17to8_17_pong, b8_17to9_17_pong, b9_17to10_17_pong, b10_17to11_17_pong, b11_17to12_17_pong, b12_17to13_17_pong, b13_17to14_17_pong, b14_17to15_17_pong, b15_17to16_17_pong, b16_17to17_17_pong, b17_17to18_17_pong, b18_17to19_17_pong, b19_17to20_17_pong, b20_17to21_17_pong, b21_17to22_17_pong, b22_17to23_17_pong, b23_17to24_17_pong, b24_17to25_17_pong, b25_17to26_17_pong, b26_17to27_17_pong, b27_17to28_17_pong, b28_17to29_17_pong, b29_17to30_17_pong, b30_17to31_17_pong, b31_17to32_17_pong; +wire [`DWIDTH-1:0] b0_18to1_18_pong, b1_18to2_18_pong, b2_18to3_18_pong, b3_18to4_18_pong, b4_18to5_18_pong, b5_18to6_18_pong, b6_18to7_18_pong, b7_18to8_18_pong, b8_18to9_18_pong, b9_18to10_18_pong, b10_18to11_18_pong, b11_18to12_18_pong, b12_18to13_18_pong, b13_18to14_18_pong, b14_18to15_18_pong, b15_18to16_18_pong, b16_18to17_18_pong, b17_18to18_18_pong, b18_18to19_18_pong, b19_18to20_18_pong, b20_18to21_18_pong, b21_18to22_18_pong, b22_18to23_18_pong, b23_18to24_18_pong, b24_18to25_18_pong, b25_18to26_18_pong, b26_18to27_18_pong, b27_18to28_18_pong, b28_18to29_18_pong, b29_18to30_18_pong, b30_18to31_18_pong, b31_18to32_18_pong; +wire [`DWIDTH-1:0] b0_19to1_19_pong, b1_19to2_19_pong, b2_19to3_19_pong, b3_19to4_19_pong, b4_19to5_19_pong, b5_19to6_19_pong, b6_19to7_19_pong, b7_19to8_19_pong, b8_19to9_19_pong, b9_19to10_19_pong, b10_19to11_19_pong, b11_19to12_19_pong, b12_19to13_19_pong, b13_19to14_19_pong, b14_19to15_19_pong, b15_19to16_19_pong, b16_19to17_19_pong, b17_19to18_19_pong, b18_19to19_19_pong, b19_19to20_19_pong, b20_19to21_19_pong, b21_19to22_19_pong, b22_19to23_19_pong, b23_19to24_19_pong, b24_19to25_19_pong, b25_19to26_19_pong, b26_19to27_19_pong, b27_19to28_19_pong, b28_19to29_19_pong, b29_19to30_19_pong, b30_19to31_19_pong, b31_19to32_19_pong; +wire [`DWIDTH-1:0] b0_20to1_20_pong, b1_20to2_20_pong, b2_20to3_20_pong, b3_20to4_20_pong, b4_20to5_20_pong, b5_20to6_20_pong, b6_20to7_20_pong, b7_20to8_20_pong, b8_20to9_20_pong, b9_20to10_20_pong, b10_20to11_20_pong, b11_20to12_20_pong, b12_20to13_20_pong, b13_20to14_20_pong, b14_20to15_20_pong, b15_20to16_20_pong, b16_20to17_20_pong, b17_20to18_20_pong, b18_20to19_20_pong, b19_20to20_20_pong, b20_20to21_20_pong, b21_20to22_20_pong, b22_20to23_20_pong, b23_20to24_20_pong, b24_20to25_20_pong, b25_20to26_20_pong, b26_20to27_20_pong, b27_20to28_20_pong, b28_20to29_20_pong, b29_20to30_20_pong, b30_20to31_20_pong, b31_20to32_20_pong; +wire [`DWIDTH-1:0] b0_21to1_21_pong, b1_21to2_21_pong, b2_21to3_21_pong, b3_21to4_21_pong, b4_21to5_21_pong, b5_21to6_21_pong, b6_21to7_21_pong, b7_21to8_21_pong, b8_21to9_21_pong, b9_21to10_21_pong, b10_21to11_21_pong, b11_21to12_21_pong, b12_21to13_21_pong, b13_21to14_21_pong, b14_21to15_21_pong, b15_21to16_21_pong, b16_21to17_21_pong, b17_21to18_21_pong, b18_21to19_21_pong, b19_21to20_21_pong, b20_21to21_21_pong, b21_21to22_21_pong, b22_21to23_21_pong, b23_21to24_21_pong, b24_21to25_21_pong, b25_21to26_21_pong, b26_21to27_21_pong, b27_21to28_21_pong, b28_21to29_21_pong, b29_21to30_21_pong, b30_21to31_21_pong, b31_21to32_21_pong; +wire [`DWIDTH-1:0] b0_22to1_22_pong, b1_22to2_22_pong, b2_22to3_22_pong, b3_22to4_22_pong, b4_22to5_22_pong, b5_22to6_22_pong, b6_22to7_22_pong, b7_22to8_22_pong, b8_22to9_22_pong, b9_22to10_22_pong, b10_22to11_22_pong, b11_22to12_22_pong, b12_22to13_22_pong, b13_22to14_22_pong, b14_22to15_22_pong, b15_22to16_22_pong, b16_22to17_22_pong, b17_22to18_22_pong, b18_22to19_22_pong, b19_22to20_22_pong, b20_22to21_22_pong, b21_22to22_22_pong, b22_22to23_22_pong, b23_22to24_22_pong, b24_22to25_22_pong, b25_22to26_22_pong, b26_22to27_22_pong, b27_22to28_22_pong, b28_22to29_22_pong, b29_22to30_22_pong, b30_22to31_22_pong, b31_22to32_22_pong; +wire [`DWIDTH-1:0] b0_23to1_23_pong, b1_23to2_23_pong, b2_23to3_23_pong, b3_23to4_23_pong, b4_23to5_23_pong, b5_23to6_23_pong, b6_23to7_23_pong, b7_23to8_23_pong, b8_23to9_23_pong, b9_23to10_23_pong, b10_23to11_23_pong, b11_23to12_23_pong, b12_23to13_23_pong, b13_23to14_23_pong, b14_23to15_23_pong, b15_23to16_23_pong, b16_23to17_23_pong, b17_23to18_23_pong, b18_23to19_23_pong, b19_23to20_23_pong, b20_23to21_23_pong, b21_23to22_23_pong, b22_23to23_23_pong, b23_23to24_23_pong, b24_23to25_23_pong, b25_23to26_23_pong, b26_23to27_23_pong, b27_23to28_23_pong, b28_23to29_23_pong, b29_23to30_23_pong, b30_23to31_23_pong, b31_23to32_23_pong; +wire [`DWIDTH-1:0] b0_24to1_24_pong, b1_24to2_24_pong, b2_24to3_24_pong, b3_24to4_24_pong, b4_24to5_24_pong, b5_24to6_24_pong, b6_24to7_24_pong, b7_24to8_24_pong, b8_24to9_24_pong, b9_24to10_24_pong, b10_24to11_24_pong, b11_24to12_24_pong, b12_24to13_24_pong, b13_24to14_24_pong, b14_24to15_24_pong, b15_24to16_24_pong, b16_24to17_24_pong, b17_24to18_24_pong, b18_24to19_24_pong, b19_24to20_24_pong, b20_24to21_24_pong, b21_24to22_24_pong, b22_24to23_24_pong, b23_24to24_24_pong, b24_24to25_24_pong, b25_24to26_24_pong, b26_24to27_24_pong, b27_24to28_24_pong, b28_24to29_24_pong, b29_24to30_24_pong, b30_24to31_24_pong, b31_24to32_24_pong; +wire [`DWIDTH-1:0] b0_25to1_25_pong, b1_25to2_25_pong, b2_25to3_25_pong, b3_25to4_25_pong, b4_25to5_25_pong, b5_25to6_25_pong, b6_25to7_25_pong, b7_25to8_25_pong, b8_25to9_25_pong, b9_25to10_25_pong, b10_25to11_25_pong, b11_25to12_25_pong, b12_25to13_25_pong, b13_25to14_25_pong, b14_25to15_25_pong, b15_25to16_25_pong, b16_25to17_25_pong, b17_25to18_25_pong, b18_25to19_25_pong, b19_25to20_25_pong, b20_25to21_25_pong, b21_25to22_25_pong, b22_25to23_25_pong, b23_25to24_25_pong, b24_25to25_25_pong, b25_25to26_25_pong, b26_25to27_25_pong, b27_25to28_25_pong, b28_25to29_25_pong, b29_25to30_25_pong, b30_25to31_25_pong, b31_25to32_25_pong; +wire [`DWIDTH-1:0] b0_26to1_26_pong, b1_26to2_26_pong, b2_26to3_26_pong, b3_26to4_26_pong, b4_26to5_26_pong, b5_26to6_26_pong, b6_26to7_26_pong, b7_26to8_26_pong, b8_26to9_26_pong, b9_26to10_26_pong, b10_26to11_26_pong, b11_26to12_26_pong, b12_26to13_26_pong, b13_26to14_26_pong, b14_26to15_26_pong, b15_26to16_26_pong, b16_26to17_26_pong, b17_26to18_26_pong, b18_26to19_26_pong, b19_26to20_26_pong, b20_26to21_26_pong, b21_26to22_26_pong, b22_26to23_26_pong, b23_26to24_26_pong, b24_26to25_26_pong, b25_26to26_26_pong, b26_26to27_26_pong, b27_26to28_26_pong, b28_26to29_26_pong, b29_26to30_26_pong, b30_26to31_26_pong, b31_26to32_26_pong; +wire [`DWIDTH-1:0] b0_27to1_27_pong, b1_27to2_27_pong, b2_27to3_27_pong, b3_27to4_27_pong, b4_27to5_27_pong, b5_27to6_27_pong, b6_27to7_27_pong, b7_27to8_27_pong, b8_27to9_27_pong, b9_27to10_27_pong, b10_27to11_27_pong, b11_27to12_27_pong, b12_27to13_27_pong, b13_27to14_27_pong, b14_27to15_27_pong, b15_27to16_27_pong, b16_27to17_27_pong, b17_27to18_27_pong, b18_27to19_27_pong, b19_27to20_27_pong, b20_27to21_27_pong, b21_27to22_27_pong, b22_27to23_27_pong, b23_27to24_27_pong, b24_27to25_27_pong, b25_27to26_27_pong, b26_27to27_27_pong, b27_27to28_27_pong, b28_27to29_27_pong, b29_27to30_27_pong, b30_27to31_27_pong, b31_27to32_27_pong; +wire [`DWIDTH-1:0] b0_28to1_28_pong, b1_28to2_28_pong, b2_28to3_28_pong, b3_28to4_28_pong, b4_28to5_28_pong, b5_28to6_28_pong, b6_28to7_28_pong, b7_28to8_28_pong, b8_28to9_28_pong, b9_28to10_28_pong, b10_28to11_28_pong, b11_28to12_28_pong, b12_28to13_28_pong, b13_28to14_28_pong, b14_28to15_28_pong, b15_28to16_28_pong, b16_28to17_28_pong, b17_28to18_28_pong, b18_28to19_28_pong, b19_28to20_28_pong, b20_28to21_28_pong, b21_28to22_28_pong, b22_28to23_28_pong, b23_28to24_28_pong, b24_28to25_28_pong, b25_28to26_28_pong, b26_28to27_28_pong, b27_28to28_28_pong, b28_28to29_28_pong, b29_28to30_28_pong, b30_28to31_28_pong, b31_28to32_28_pong; +wire [`DWIDTH-1:0] b0_29to1_29_pong, b1_29to2_29_pong, b2_29to3_29_pong, b3_29to4_29_pong, b4_29to5_29_pong, b5_29to6_29_pong, b6_29to7_29_pong, b7_29to8_29_pong, b8_29to9_29_pong, b9_29to10_29_pong, b10_29to11_29_pong, b11_29to12_29_pong, b12_29to13_29_pong, b13_29to14_29_pong, b14_29to15_29_pong, b15_29to16_29_pong, b16_29to17_29_pong, b17_29to18_29_pong, b18_29to19_29_pong, b19_29to20_29_pong, b20_29to21_29_pong, b21_29to22_29_pong, b22_29to23_29_pong, b23_29to24_29_pong, b24_29to25_29_pong, b25_29to26_29_pong, b26_29to27_29_pong, b27_29to28_29_pong, b28_29to29_29_pong, b29_29to30_29_pong, b30_29to31_29_pong, b31_29to32_29_pong; +wire [`DWIDTH-1:0] b0_30to1_30_pong, b1_30to2_30_pong, b2_30to3_30_pong, b3_30to4_30_pong, b4_30to5_30_pong, b5_30to6_30_pong, b6_30to7_30_pong, b7_30to8_30_pong, b8_30to9_30_pong, b9_30to10_30_pong, b10_30to11_30_pong, b11_30to12_30_pong, b12_30to13_30_pong, b13_30to14_30_pong, b14_30to15_30_pong, b15_30to16_30_pong, b16_30to17_30_pong, b17_30to18_30_pong, b18_30to19_30_pong, b19_30to20_30_pong, b20_30to21_30_pong, b21_30to22_30_pong, b22_30to23_30_pong, b23_30to24_30_pong, b24_30to25_30_pong, b25_30to26_30_pong, b26_30to27_30_pong, b27_30to28_30_pong, b28_30to29_30_pong, b29_30to30_30_pong, b30_30to31_30_pong, b31_30to32_30_pong; +wire [`DWIDTH-1:0] b0_31to1_31_pong, b1_31to2_31_pong, b2_31to3_31_pong, b3_31to4_31_pong, b4_31to5_31_pong, b5_31to6_31_pong, b6_31to7_31_pong, b7_31to8_31_pong, b8_31to9_31_pong, b9_31to10_31_pong, b10_31to11_31_pong, b11_31to12_31_pong, b12_31to13_31_pong, b13_31to14_31_pong, b14_31to15_31_pong, b15_31to16_31_pong, b16_31to17_31_pong, b17_31to18_31_pong, b18_31to19_31_pong, b19_31to20_31_pong, b20_31to21_31_pong, b21_31to22_31_pong, b22_31to23_31_pong, b23_31to24_31_pong, b24_31to25_31_pong, b25_31to26_31_pong, b26_31to27_31_pong, b27_31to28_31_pong, b28_31to29_31_pong, b29_31to30_31_pong, b30_31to31_31_pong, b31_31to32_31_pong; + +reg [`DWIDTH-1:0] b0_data, b1_data, b2_data, b3_data, b4_data, b5_data, b6_data, b7_data, b8_data, b9_data, b10_data, b11_data, b12_data, b13_data, b14_data, b15_data, b16_data, b17_data, b18_data, b19_data, b20_data, b21_data, b22_data, b23_data, b24_data, b25_data, b26_data, b27_data, b28_data, b29_data, b30_data, b31_data; + +wire effective_rst; +assign effective_rst = reset | pe_reset; + +reg b_data_sel_delay1; +reg b_data_sel_delay2; +reg b_data_sel_delay3; +reg b_data_sel_delay4; +reg b_data_sel_delay5; +reg b_data_sel_delay6; +reg b_data_sel_delay7; +reg b_data_sel_delay8; +reg b_data_sel_delay9; +reg b_data_sel_delay10; +reg b_data_sel_delay11; +reg b_data_sel_delay12; +reg b_data_sel_delay13; +reg b_data_sel_delay14; +reg b_data_sel_delay15; +reg b_data_sel_delay16; +reg b_data_sel_delay17; +reg b_data_sel_delay18; +reg b_data_sel_delay19; +reg b_data_sel_delay20; +reg b_data_sel_delay21; +reg b_data_sel_delay22; +reg b_data_sel_delay23; +reg b_data_sel_delay24; +reg b_data_sel_delay25; +reg b_data_sel_delay26; +reg b_data_sel_delay27; +reg b_data_sel_delay28; +reg b_data_sel_delay29; +reg b_data_sel_delay30; +reg b_data_sel_delay31; +reg b_data_sel_delay32; +reg b_data_sel_delay33; +reg b_data_sel_delay34; +reg b_data_sel_delay35; +reg b_data_sel_delay36; +reg b_data_sel_delay37; +reg b_data_sel_delay38; +reg b_data_sel_delay39; +reg b_data_sel_delay40; +reg b_data_sel_delay41; +reg b_data_sel_delay42; +reg b_data_sel_delay43; +reg b_data_sel_delay44; +reg b_data_sel_delay45; +reg b_data_sel_delay46; +reg b_data_sel_delay47; +reg b_data_sel_delay48; +reg b_data_sel_delay49; +reg b_data_sel_delay50; +reg b_data_sel_delay51; +reg b_data_sel_delay52; +reg b_data_sel_delay53; +reg b_data_sel_delay54; +reg b_data_sel_delay55; +reg b_data_sel_delay56; +reg b_data_sel_delay57; +reg b_data_sel_delay58; +reg b_data_sel_delay59; +reg b_data_sel_delay60; +reg b_data_sel_delay61; +reg b_data_sel_delay62; + +always @ (posedge clk) begin + if (reset) begin + b_data_sel_delay1 <= 0; + b_data_sel_delay2 <= 0; + b_data_sel_delay3 <= 0; + b_data_sel_delay4 <= 0; + b_data_sel_delay5 <= 0; + b_data_sel_delay6 <= 0; + b_data_sel_delay7 <= 0; + b_data_sel_delay8 <= 0; + b_data_sel_delay9 <= 0; + b_data_sel_delay10 <= 0; + b_data_sel_delay11 <= 0; + b_data_sel_delay12 <= 0; + b_data_sel_delay13 <= 0; + b_data_sel_delay14 <= 0; + b_data_sel_delay15 <= 0; + b_data_sel_delay16 <= 0; + b_data_sel_delay17 <= 0; + b_data_sel_delay18 <= 0; + b_data_sel_delay19 <= 0; + b_data_sel_delay20 <= 0; + b_data_sel_delay21 <= 0; + b_data_sel_delay22 <= 0; + b_data_sel_delay23 <= 0; + b_data_sel_delay24 <= 0; + b_data_sel_delay25 <= 0; + b_data_sel_delay26 <= 0; + b_data_sel_delay27 <= 0; + b_data_sel_delay28 <= 0; + b_data_sel_delay29 <= 0; + b_data_sel_delay30 <= 0; + b_data_sel_delay31 <= 0; + b_data_sel_delay32 <= 0; + b_data_sel_delay33 <= 0; + b_data_sel_delay34 <= 0; + b_data_sel_delay35 <= 0; + b_data_sel_delay36 <= 0; + b_data_sel_delay37 <= 0; + b_data_sel_delay38 <= 0; + b_data_sel_delay39 <= 0; + b_data_sel_delay40 <= 0; + b_data_sel_delay41 <= 0; + b_data_sel_delay42 <= 0; + b_data_sel_delay43 <= 0; + b_data_sel_delay44 <= 0; + b_data_sel_delay45 <= 0; + b_data_sel_delay46 <= 0; + b_data_sel_delay47 <= 0; + b_data_sel_delay48 <= 0; + b_data_sel_delay49 <= 0; + b_data_sel_delay50 <= 0; + b_data_sel_delay51 <= 0; + b_data_sel_delay52 <= 0; + b_data_sel_delay53 <= 0; + b_data_sel_delay54 <= 0; + b_data_sel_delay55 <= 0; + b_data_sel_delay56 <= 0; + b_data_sel_delay57 <= 0; + b_data_sel_delay58 <= 0; + b_data_sel_delay59 <= 0; + b_data_sel_delay60 <= 0; + b_data_sel_delay61 <= 0; + b_data_sel_delay62 <= 0; + end + else begin + b_data_sel_delay1 <= b_data_sel; + b_data_sel_delay2 <= b_data_sel_delay1; + b_data_sel_delay3 <= b_data_sel_delay2; + b_data_sel_delay4 <= b_data_sel_delay3; + b_data_sel_delay5 <= b_data_sel_delay4; + b_data_sel_delay6 <= b_data_sel_delay5; + b_data_sel_delay7 <= b_data_sel_delay6; + b_data_sel_delay8 <= b_data_sel_delay7; + b_data_sel_delay9 <= b_data_sel_delay8; + b_data_sel_delay10 <= b_data_sel_delay9; + b_data_sel_delay11 <= b_data_sel_delay10; + b_data_sel_delay12 <= b_data_sel_delay11; + b_data_sel_delay13 <= b_data_sel_delay12; + b_data_sel_delay14 <= b_data_sel_delay13; + b_data_sel_delay15 <= b_data_sel_delay14; + b_data_sel_delay16 <= b_data_sel_delay15; + b_data_sel_delay17 <= b_data_sel_delay16; + b_data_sel_delay18 <= b_data_sel_delay17; + b_data_sel_delay19 <= b_data_sel_delay18; + b_data_sel_delay20 <= b_data_sel_delay19; + b_data_sel_delay21 <= b_data_sel_delay20; + b_data_sel_delay22 <= b_data_sel_delay21; + b_data_sel_delay23 <= b_data_sel_delay22; + b_data_sel_delay24 <= b_data_sel_delay23; + b_data_sel_delay25 <= b_data_sel_delay24; + b_data_sel_delay26 <= b_data_sel_delay25; + b_data_sel_delay27 <= b_data_sel_delay26; + b_data_sel_delay28 <= b_data_sel_delay27; + b_data_sel_delay29 <= b_data_sel_delay28; + b_data_sel_delay30 <= b_data_sel_delay29; + b_data_sel_delay31 <= b_data_sel_delay30; + b_data_sel_delay32 <= b_data_sel_delay31; + b_data_sel_delay33 <= b_data_sel_delay32; + b_data_sel_delay34 <= b_data_sel_delay33; + b_data_sel_delay35 <= b_data_sel_delay34; + b_data_sel_delay36 <= b_data_sel_delay35; + b_data_sel_delay37 <= b_data_sel_delay36; + b_data_sel_delay38 <= b_data_sel_delay37; + b_data_sel_delay39 <= b_data_sel_delay38; + b_data_sel_delay40 <= b_data_sel_delay39; + b_data_sel_delay41 <= b_data_sel_delay40; + b_data_sel_delay42 <= b_data_sel_delay41; + b_data_sel_delay43 <= b_data_sel_delay42; + b_data_sel_delay44 <= b_data_sel_delay43; + b_data_sel_delay45 <= b_data_sel_delay44; + b_data_sel_delay46 <= b_data_sel_delay45; + b_data_sel_delay47 <= b_data_sel_delay46; + b_data_sel_delay48 <= b_data_sel_delay47; + b_data_sel_delay49 <= b_data_sel_delay48; + b_data_sel_delay50 <= b_data_sel_delay49; + b_data_sel_delay51 <= b_data_sel_delay50; + b_data_sel_delay52 <= b_data_sel_delay51; + b_data_sel_delay53 <= b_data_sel_delay52; + b_data_sel_delay54 <= b_data_sel_delay53; + b_data_sel_delay55 <= b_data_sel_delay54; + b_data_sel_delay56 <= b_data_sel_delay55; + b_data_sel_delay57 <= b_data_sel_delay56; + b_data_sel_delay58 <= b_data_sel_delay57; + b_data_sel_delay59 <= b_data_sel_delay58; + b_data_sel_delay60 <= b_data_sel_delay59; + b_data_sel_delay61 <= b_data_sel_delay60; + b_data_sel_delay62 <= b_data_sel_delay61; + end +end + +// Signals for Each PONG buffer + +reg b_data_valid_pong_delay0_1; +reg b_data_valid_pong_delay0_2; +reg b_data_valid_pong_delay0_3; +reg b_data_valid_pong_delay0_4; +reg b_data_valid_pong_delay0_5; +reg b_data_valid_pong_delay0_6; +reg b_data_valid_pong_delay0_7; +reg b_data_valid_pong_delay0_8; +reg b_data_valid_pong_delay0_9; +reg b_data_valid_pong_delay0_10; +reg b_data_valid_pong_delay0_11; +reg b_data_valid_pong_delay0_12; +reg b_data_valid_pong_delay0_13; +reg b_data_valid_pong_delay0_14; +reg b_data_valid_pong_delay0_15; +reg b_data_valid_pong_delay0_16; +reg b_data_valid_pong_delay0_17; +reg b_data_valid_pong_delay0_18; +reg b_data_valid_pong_delay0_19; +reg b_data_valid_pong_delay0_20; +reg b_data_valid_pong_delay0_21; +reg b_data_valid_pong_delay0_22; +reg b_data_valid_pong_delay0_23; +reg b_data_valid_pong_delay0_24; +reg b_data_valid_pong_delay0_25; +reg b_data_valid_pong_delay0_26; +reg b_data_valid_pong_delay0_27; +reg b_data_valid_pong_delay0_28; +reg b_data_valid_pong_delay0_29; +reg b_data_valid_pong_delay0_30; +reg b_data_valid_pong_delay0_31; +reg b_data_valid_pong_delay0_32; +reg b_data_valid_pong_delay0_33; +reg b_data_valid_pong_delay0_34; +reg b_data_valid_pong_delay0_35; +reg b_data_valid_pong_delay0_36; +reg b_data_valid_pong_delay0_37; +reg b_data_valid_pong_delay0_38; +reg b_data_valid_pong_delay0_39; +reg b_data_valid_pong_delay0_40; +reg b_data_valid_pong_delay0_41; +reg b_data_valid_pong_delay0_42; +reg b_data_valid_pong_delay0_43; +reg b_data_valid_pong_delay0_44; +reg b_data_valid_pong_delay0_45; +reg b_data_valid_pong_delay0_46; +reg b_data_valid_pong_delay0_47; +reg b_data_valid_pong_delay0_48; +reg b_data_valid_pong_delay0_49; +reg b_data_valid_pong_delay0_50; +reg b_data_valid_pong_delay0_51; +reg b_data_valid_pong_delay0_52; +reg b_data_valid_pong_delay0_53; +reg b_data_valid_pong_delay0_54; +reg b_data_valid_pong_delay0_55; +reg b_data_valid_pong_delay0_56; +reg b_data_valid_pong_delay0_57; +reg b_data_valid_pong_delay0_58; +reg b_data_valid_pong_delay0_59; +reg b_data_valid_pong_delay0_60; +reg b_data_valid_pong_delay0_61; +reg b_data_valid_pong_delay0_62; +wire b_data_valid_pong_delay1_0; +wire b_data_valid_pong_delay2_0; +wire b_data_valid_pong_delay3_0; +wire b_data_valid_pong_delay4_0; +wire b_data_valid_pong_delay5_0; +wire b_data_valid_pong_delay6_0; +wire b_data_valid_pong_delay7_0; +wire b_data_valid_pong_delay8_0; +wire b_data_valid_pong_delay9_0; +wire b_data_valid_pong_delay10_0; +wire b_data_valid_pong_delay11_0; +wire b_data_valid_pong_delay12_0; +wire b_data_valid_pong_delay13_0; +wire b_data_valid_pong_delay14_0; +wire b_data_valid_pong_delay15_0; +wire b_data_valid_pong_delay16_0; +wire b_data_valid_pong_delay17_0; +wire b_data_valid_pong_delay18_0; +wire b_data_valid_pong_delay19_0; +wire b_data_valid_pong_delay20_0; +wire b_data_valid_pong_delay21_0; +wire b_data_valid_pong_delay22_0; +wire b_data_valid_pong_delay23_0; +wire b_data_valid_pong_delay24_0; +wire b_data_valid_pong_delay25_0; +wire b_data_valid_pong_delay26_0; +wire b_data_valid_pong_delay27_0; +wire b_data_valid_pong_delay28_0; +wire b_data_valid_pong_delay29_0; +wire b_data_valid_pong_delay30_0; +wire b_data_valid_pong_delay31_0; +wire b_data_valid_pong_delay1_1; +wire b_data_valid_pong_delay2_1; +wire b_data_valid_pong_delay3_1; +wire b_data_valid_pong_delay4_1; +wire b_data_valid_pong_delay5_1; +wire b_data_valid_pong_delay6_1; +wire b_data_valid_pong_delay7_1; +wire b_data_valid_pong_delay8_1; +wire b_data_valid_pong_delay9_1; +wire b_data_valid_pong_delay10_1; +wire b_data_valid_pong_delay11_1; +wire b_data_valid_pong_delay12_1; +wire b_data_valid_pong_delay13_1; +wire b_data_valid_pong_delay14_1; +wire b_data_valid_pong_delay15_1; +wire b_data_valid_pong_delay16_1; +wire b_data_valid_pong_delay17_1; +wire b_data_valid_pong_delay18_1; +wire b_data_valid_pong_delay19_1; +wire b_data_valid_pong_delay20_1; +wire b_data_valid_pong_delay21_1; +wire b_data_valid_pong_delay22_1; +wire b_data_valid_pong_delay23_1; +wire b_data_valid_pong_delay24_1; +wire b_data_valid_pong_delay25_1; +wire b_data_valid_pong_delay26_1; +wire b_data_valid_pong_delay27_1; +wire b_data_valid_pong_delay28_1; +wire b_data_valid_pong_delay29_1; +wire b_data_valid_pong_delay30_1; +wire b_data_valid_pong_delay31_1; +wire b_data_valid_pong_delay1_2; +wire b_data_valid_pong_delay2_2; +wire b_data_valid_pong_delay3_2; +wire b_data_valid_pong_delay4_2; +wire b_data_valid_pong_delay5_2; +wire b_data_valid_pong_delay6_2; +wire b_data_valid_pong_delay7_2; +wire b_data_valid_pong_delay8_2; +wire b_data_valid_pong_delay9_2; +wire b_data_valid_pong_delay10_2; +wire b_data_valid_pong_delay11_2; +wire b_data_valid_pong_delay12_2; +wire b_data_valid_pong_delay13_2; +wire b_data_valid_pong_delay14_2; +wire b_data_valid_pong_delay15_2; +wire b_data_valid_pong_delay16_2; +wire b_data_valid_pong_delay17_2; +wire b_data_valid_pong_delay18_2; +wire b_data_valid_pong_delay19_2; +wire b_data_valid_pong_delay20_2; +wire b_data_valid_pong_delay21_2; +wire b_data_valid_pong_delay22_2; +wire b_data_valid_pong_delay23_2; +wire b_data_valid_pong_delay24_2; +wire b_data_valid_pong_delay25_2; +wire b_data_valid_pong_delay26_2; +wire b_data_valid_pong_delay27_2; +wire b_data_valid_pong_delay28_2; +wire b_data_valid_pong_delay29_2; +wire b_data_valid_pong_delay30_2; +wire b_data_valid_pong_delay31_2; +wire b_data_valid_pong_delay1_3; +wire b_data_valid_pong_delay2_3; +wire b_data_valid_pong_delay3_3; +wire b_data_valid_pong_delay4_3; +wire b_data_valid_pong_delay5_3; +wire b_data_valid_pong_delay6_3; +wire b_data_valid_pong_delay7_3; +wire b_data_valid_pong_delay8_3; +wire b_data_valid_pong_delay9_3; +wire b_data_valid_pong_delay10_3; +wire b_data_valid_pong_delay11_3; +wire b_data_valid_pong_delay12_3; +wire b_data_valid_pong_delay13_3; +wire b_data_valid_pong_delay14_3; +wire b_data_valid_pong_delay15_3; +wire b_data_valid_pong_delay16_3; +wire b_data_valid_pong_delay17_3; +wire b_data_valid_pong_delay18_3; +wire b_data_valid_pong_delay19_3; +wire b_data_valid_pong_delay20_3; +wire b_data_valid_pong_delay21_3; +wire b_data_valid_pong_delay22_3; +wire b_data_valid_pong_delay23_3; +wire b_data_valid_pong_delay24_3; +wire b_data_valid_pong_delay25_3; +wire b_data_valid_pong_delay26_3; +wire b_data_valid_pong_delay27_3; +wire b_data_valid_pong_delay28_3; +wire b_data_valid_pong_delay29_3; +wire b_data_valid_pong_delay30_3; +wire b_data_valid_pong_delay31_3; +wire b_data_valid_pong_delay1_4; +wire b_data_valid_pong_delay2_4; +wire b_data_valid_pong_delay3_4; +wire b_data_valid_pong_delay4_4; +wire b_data_valid_pong_delay5_4; +wire b_data_valid_pong_delay6_4; +wire b_data_valid_pong_delay7_4; +wire b_data_valid_pong_delay8_4; +wire b_data_valid_pong_delay9_4; +wire b_data_valid_pong_delay10_4; +wire b_data_valid_pong_delay11_4; +wire b_data_valid_pong_delay12_4; +wire b_data_valid_pong_delay13_4; +wire b_data_valid_pong_delay14_4; +wire b_data_valid_pong_delay15_4; +wire b_data_valid_pong_delay16_4; +wire b_data_valid_pong_delay17_4; +wire b_data_valid_pong_delay18_4; +wire b_data_valid_pong_delay19_4; +wire b_data_valid_pong_delay20_4; +wire b_data_valid_pong_delay21_4; +wire b_data_valid_pong_delay22_4; +wire b_data_valid_pong_delay23_4; +wire b_data_valid_pong_delay24_4; +wire b_data_valid_pong_delay25_4; +wire b_data_valid_pong_delay26_4; +wire b_data_valid_pong_delay27_4; +wire b_data_valid_pong_delay28_4; +wire b_data_valid_pong_delay29_4; +wire b_data_valid_pong_delay30_4; +wire b_data_valid_pong_delay31_4; +wire b_data_valid_pong_delay1_5; +wire b_data_valid_pong_delay2_5; +wire b_data_valid_pong_delay3_5; +wire b_data_valid_pong_delay4_5; +wire b_data_valid_pong_delay5_5; +wire b_data_valid_pong_delay6_5; +wire b_data_valid_pong_delay7_5; +wire b_data_valid_pong_delay8_5; +wire b_data_valid_pong_delay9_5; +wire b_data_valid_pong_delay10_5; +wire b_data_valid_pong_delay11_5; +wire b_data_valid_pong_delay12_5; +wire b_data_valid_pong_delay13_5; +wire b_data_valid_pong_delay14_5; +wire b_data_valid_pong_delay15_5; +wire b_data_valid_pong_delay16_5; +wire b_data_valid_pong_delay17_5; +wire b_data_valid_pong_delay18_5; +wire b_data_valid_pong_delay19_5; +wire b_data_valid_pong_delay20_5; +wire b_data_valid_pong_delay21_5; +wire b_data_valid_pong_delay22_5; +wire b_data_valid_pong_delay23_5; +wire b_data_valid_pong_delay24_5; +wire b_data_valid_pong_delay25_5; +wire b_data_valid_pong_delay26_5; +wire b_data_valid_pong_delay27_5; +wire b_data_valid_pong_delay28_5; +wire b_data_valid_pong_delay29_5; +wire b_data_valid_pong_delay30_5; +wire b_data_valid_pong_delay31_5; +wire b_data_valid_pong_delay1_6; +wire b_data_valid_pong_delay2_6; +wire b_data_valid_pong_delay3_6; +wire b_data_valid_pong_delay4_6; +wire b_data_valid_pong_delay5_6; +wire b_data_valid_pong_delay6_6; +wire b_data_valid_pong_delay7_6; +wire b_data_valid_pong_delay8_6; +wire b_data_valid_pong_delay9_6; +wire b_data_valid_pong_delay10_6; +wire b_data_valid_pong_delay11_6; +wire b_data_valid_pong_delay12_6; +wire b_data_valid_pong_delay13_6; +wire b_data_valid_pong_delay14_6; +wire b_data_valid_pong_delay15_6; +wire b_data_valid_pong_delay16_6; +wire b_data_valid_pong_delay17_6; +wire b_data_valid_pong_delay18_6; +wire b_data_valid_pong_delay19_6; +wire b_data_valid_pong_delay20_6; +wire b_data_valid_pong_delay21_6; +wire b_data_valid_pong_delay22_6; +wire b_data_valid_pong_delay23_6; +wire b_data_valid_pong_delay24_6; +wire b_data_valid_pong_delay25_6; +wire b_data_valid_pong_delay26_6; +wire b_data_valid_pong_delay27_6; +wire b_data_valid_pong_delay28_6; +wire b_data_valid_pong_delay29_6; +wire b_data_valid_pong_delay30_6; +wire b_data_valid_pong_delay31_6; +wire b_data_valid_pong_delay1_7; +wire b_data_valid_pong_delay2_7; +wire b_data_valid_pong_delay3_7; +wire b_data_valid_pong_delay4_7; +wire b_data_valid_pong_delay5_7; +wire b_data_valid_pong_delay6_7; +wire b_data_valid_pong_delay7_7; +wire b_data_valid_pong_delay8_7; +wire b_data_valid_pong_delay9_7; +wire b_data_valid_pong_delay10_7; +wire b_data_valid_pong_delay11_7; +wire b_data_valid_pong_delay12_7; +wire b_data_valid_pong_delay13_7; +wire b_data_valid_pong_delay14_7; +wire b_data_valid_pong_delay15_7; +wire b_data_valid_pong_delay16_7; +wire b_data_valid_pong_delay17_7; +wire b_data_valid_pong_delay18_7; +wire b_data_valid_pong_delay19_7; +wire b_data_valid_pong_delay20_7; +wire b_data_valid_pong_delay21_7; +wire b_data_valid_pong_delay22_7; +wire b_data_valid_pong_delay23_7; +wire b_data_valid_pong_delay24_7; +wire b_data_valid_pong_delay25_7; +wire b_data_valid_pong_delay26_7; +wire b_data_valid_pong_delay27_7; +wire b_data_valid_pong_delay28_7; +wire b_data_valid_pong_delay29_7; +wire b_data_valid_pong_delay30_7; +wire b_data_valid_pong_delay31_7; +wire b_data_valid_pong_delay1_8; +wire b_data_valid_pong_delay2_8; +wire b_data_valid_pong_delay3_8; +wire b_data_valid_pong_delay4_8; +wire b_data_valid_pong_delay5_8; +wire b_data_valid_pong_delay6_8; +wire b_data_valid_pong_delay7_8; +wire b_data_valid_pong_delay8_8; +wire b_data_valid_pong_delay9_8; +wire b_data_valid_pong_delay10_8; +wire b_data_valid_pong_delay11_8; +wire b_data_valid_pong_delay12_8; +wire b_data_valid_pong_delay13_8; +wire b_data_valid_pong_delay14_8; +wire b_data_valid_pong_delay15_8; +wire b_data_valid_pong_delay16_8; +wire b_data_valid_pong_delay17_8; +wire b_data_valid_pong_delay18_8; +wire b_data_valid_pong_delay19_8; +wire b_data_valid_pong_delay20_8; +wire b_data_valid_pong_delay21_8; +wire b_data_valid_pong_delay22_8; +wire b_data_valid_pong_delay23_8; +wire b_data_valid_pong_delay24_8; +wire b_data_valid_pong_delay25_8; +wire b_data_valid_pong_delay26_8; +wire b_data_valid_pong_delay27_8; +wire b_data_valid_pong_delay28_8; +wire b_data_valid_pong_delay29_8; +wire b_data_valid_pong_delay30_8; +wire b_data_valid_pong_delay31_8; +wire b_data_valid_pong_delay1_9; +wire b_data_valid_pong_delay2_9; +wire b_data_valid_pong_delay3_9; +wire b_data_valid_pong_delay4_9; +wire b_data_valid_pong_delay5_9; +wire b_data_valid_pong_delay6_9; +wire b_data_valid_pong_delay7_9; +wire b_data_valid_pong_delay8_9; +wire b_data_valid_pong_delay9_9; +wire b_data_valid_pong_delay10_9; +wire b_data_valid_pong_delay11_9; +wire b_data_valid_pong_delay12_9; +wire b_data_valid_pong_delay13_9; +wire b_data_valid_pong_delay14_9; +wire b_data_valid_pong_delay15_9; +wire b_data_valid_pong_delay16_9; +wire b_data_valid_pong_delay17_9; +wire b_data_valid_pong_delay18_9; +wire b_data_valid_pong_delay19_9; +wire b_data_valid_pong_delay20_9; +wire b_data_valid_pong_delay21_9; +wire b_data_valid_pong_delay22_9; +wire b_data_valid_pong_delay23_9; +wire b_data_valid_pong_delay24_9; +wire b_data_valid_pong_delay25_9; +wire b_data_valid_pong_delay26_9; +wire b_data_valid_pong_delay27_9; +wire b_data_valid_pong_delay28_9; +wire b_data_valid_pong_delay29_9; +wire b_data_valid_pong_delay30_9; +wire b_data_valid_pong_delay31_9; +wire b_data_valid_pong_delay1_10; +wire b_data_valid_pong_delay2_10; +wire b_data_valid_pong_delay3_10; +wire b_data_valid_pong_delay4_10; +wire b_data_valid_pong_delay5_10; +wire b_data_valid_pong_delay6_10; +wire b_data_valid_pong_delay7_10; +wire b_data_valid_pong_delay8_10; +wire b_data_valid_pong_delay9_10; +wire b_data_valid_pong_delay10_10; +wire b_data_valid_pong_delay11_10; +wire b_data_valid_pong_delay12_10; +wire b_data_valid_pong_delay13_10; +wire b_data_valid_pong_delay14_10; +wire b_data_valid_pong_delay15_10; +wire b_data_valid_pong_delay16_10; +wire b_data_valid_pong_delay17_10; +wire b_data_valid_pong_delay18_10; +wire b_data_valid_pong_delay19_10; +wire b_data_valid_pong_delay20_10; +wire b_data_valid_pong_delay21_10; +wire b_data_valid_pong_delay22_10; +wire b_data_valid_pong_delay23_10; +wire b_data_valid_pong_delay24_10; +wire b_data_valid_pong_delay25_10; +wire b_data_valid_pong_delay26_10; +wire b_data_valid_pong_delay27_10; +wire b_data_valid_pong_delay28_10; +wire b_data_valid_pong_delay29_10; +wire b_data_valid_pong_delay30_10; +wire b_data_valid_pong_delay31_10; +wire b_data_valid_pong_delay1_11; +wire b_data_valid_pong_delay2_11; +wire b_data_valid_pong_delay3_11; +wire b_data_valid_pong_delay4_11; +wire b_data_valid_pong_delay5_11; +wire b_data_valid_pong_delay6_11; +wire b_data_valid_pong_delay7_11; +wire b_data_valid_pong_delay8_11; +wire b_data_valid_pong_delay9_11; +wire b_data_valid_pong_delay10_11; +wire b_data_valid_pong_delay11_11; +wire b_data_valid_pong_delay12_11; +wire b_data_valid_pong_delay13_11; +wire b_data_valid_pong_delay14_11; +wire b_data_valid_pong_delay15_11; +wire b_data_valid_pong_delay16_11; +wire b_data_valid_pong_delay17_11; +wire b_data_valid_pong_delay18_11; +wire b_data_valid_pong_delay19_11; +wire b_data_valid_pong_delay20_11; +wire b_data_valid_pong_delay21_11; +wire b_data_valid_pong_delay22_11; +wire b_data_valid_pong_delay23_11; +wire b_data_valid_pong_delay24_11; +wire b_data_valid_pong_delay25_11; +wire b_data_valid_pong_delay26_11; +wire b_data_valid_pong_delay27_11; +wire b_data_valid_pong_delay28_11; +wire b_data_valid_pong_delay29_11; +wire b_data_valid_pong_delay30_11; +wire b_data_valid_pong_delay31_11; +wire b_data_valid_pong_delay1_12; +wire b_data_valid_pong_delay2_12; +wire b_data_valid_pong_delay3_12; +wire b_data_valid_pong_delay4_12; +wire b_data_valid_pong_delay5_12; +wire b_data_valid_pong_delay6_12; +wire b_data_valid_pong_delay7_12; +wire b_data_valid_pong_delay8_12; +wire b_data_valid_pong_delay9_12; +wire b_data_valid_pong_delay10_12; +wire b_data_valid_pong_delay11_12; +wire b_data_valid_pong_delay12_12; +wire b_data_valid_pong_delay13_12; +wire b_data_valid_pong_delay14_12; +wire b_data_valid_pong_delay15_12; +wire b_data_valid_pong_delay16_12; +wire b_data_valid_pong_delay17_12; +wire b_data_valid_pong_delay18_12; +wire b_data_valid_pong_delay19_12; +wire b_data_valid_pong_delay20_12; +wire b_data_valid_pong_delay21_12; +wire b_data_valid_pong_delay22_12; +wire b_data_valid_pong_delay23_12; +wire b_data_valid_pong_delay24_12; +wire b_data_valid_pong_delay25_12; +wire b_data_valid_pong_delay26_12; +wire b_data_valid_pong_delay27_12; +wire b_data_valid_pong_delay28_12; +wire b_data_valid_pong_delay29_12; +wire b_data_valid_pong_delay30_12; +wire b_data_valid_pong_delay31_12; +wire b_data_valid_pong_delay1_13; +wire b_data_valid_pong_delay2_13; +wire b_data_valid_pong_delay3_13; +wire b_data_valid_pong_delay4_13; +wire b_data_valid_pong_delay5_13; +wire b_data_valid_pong_delay6_13; +wire b_data_valid_pong_delay7_13; +wire b_data_valid_pong_delay8_13; +wire b_data_valid_pong_delay9_13; +wire b_data_valid_pong_delay10_13; +wire b_data_valid_pong_delay11_13; +wire b_data_valid_pong_delay12_13; +wire b_data_valid_pong_delay13_13; +wire b_data_valid_pong_delay14_13; +wire b_data_valid_pong_delay15_13; +wire b_data_valid_pong_delay16_13; +wire b_data_valid_pong_delay17_13; +wire b_data_valid_pong_delay18_13; +wire b_data_valid_pong_delay19_13; +wire b_data_valid_pong_delay20_13; +wire b_data_valid_pong_delay21_13; +wire b_data_valid_pong_delay22_13; +wire b_data_valid_pong_delay23_13; +wire b_data_valid_pong_delay24_13; +wire b_data_valid_pong_delay25_13; +wire b_data_valid_pong_delay26_13; +wire b_data_valid_pong_delay27_13; +wire b_data_valid_pong_delay28_13; +wire b_data_valid_pong_delay29_13; +wire b_data_valid_pong_delay30_13; +wire b_data_valid_pong_delay31_13; +wire b_data_valid_pong_delay1_14; +wire b_data_valid_pong_delay2_14; +wire b_data_valid_pong_delay3_14; +wire b_data_valid_pong_delay4_14; +wire b_data_valid_pong_delay5_14; +wire b_data_valid_pong_delay6_14; +wire b_data_valid_pong_delay7_14; +wire b_data_valid_pong_delay8_14; +wire b_data_valid_pong_delay9_14; +wire b_data_valid_pong_delay10_14; +wire b_data_valid_pong_delay11_14; +wire b_data_valid_pong_delay12_14; +wire b_data_valid_pong_delay13_14; +wire b_data_valid_pong_delay14_14; +wire b_data_valid_pong_delay15_14; +wire b_data_valid_pong_delay16_14; +wire b_data_valid_pong_delay17_14; +wire b_data_valid_pong_delay18_14; +wire b_data_valid_pong_delay19_14; +wire b_data_valid_pong_delay20_14; +wire b_data_valid_pong_delay21_14; +wire b_data_valid_pong_delay22_14; +wire b_data_valid_pong_delay23_14; +wire b_data_valid_pong_delay24_14; +wire b_data_valid_pong_delay25_14; +wire b_data_valid_pong_delay26_14; +wire b_data_valid_pong_delay27_14; +wire b_data_valid_pong_delay28_14; +wire b_data_valid_pong_delay29_14; +wire b_data_valid_pong_delay30_14; +wire b_data_valid_pong_delay31_14; +wire b_data_valid_pong_delay1_15; +wire b_data_valid_pong_delay2_15; +wire b_data_valid_pong_delay3_15; +wire b_data_valid_pong_delay4_15; +wire b_data_valid_pong_delay5_15; +wire b_data_valid_pong_delay6_15; +wire b_data_valid_pong_delay7_15; +wire b_data_valid_pong_delay8_15; +wire b_data_valid_pong_delay9_15; +wire b_data_valid_pong_delay10_15; +wire b_data_valid_pong_delay11_15; +wire b_data_valid_pong_delay12_15; +wire b_data_valid_pong_delay13_15; +wire b_data_valid_pong_delay14_15; +wire b_data_valid_pong_delay15_15; +wire b_data_valid_pong_delay16_15; +wire b_data_valid_pong_delay17_15; +wire b_data_valid_pong_delay18_15; +wire b_data_valid_pong_delay19_15; +wire b_data_valid_pong_delay20_15; +wire b_data_valid_pong_delay21_15; +wire b_data_valid_pong_delay22_15; +wire b_data_valid_pong_delay23_15; +wire b_data_valid_pong_delay24_15; +wire b_data_valid_pong_delay25_15; +wire b_data_valid_pong_delay26_15; +wire b_data_valid_pong_delay27_15; +wire b_data_valid_pong_delay28_15; +wire b_data_valid_pong_delay29_15; +wire b_data_valid_pong_delay30_15; +wire b_data_valid_pong_delay31_15; +wire b_data_valid_pong_delay1_16; +wire b_data_valid_pong_delay2_16; +wire b_data_valid_pong_delay3_16; +wire b_data_valid_pong_delay4_16; +wire b_data_valid_pong_delay5_16; +wire b_data_valid_pong_delay6_16; +wire b_data_valid_pong_delay7_16; +wire b_data_valid_pong_delay8_16; +wire b_data_valid_pong_delay9_16; +wire b_data_valid_pong_delay10_16; +wire b_data_valid_pong_delay11_16; +wire b_data_valid_pong_delay12_16; +wire b_data_valid_pong_delay13_16; +wire b_data_valid_pong_delay14_16; +wire b_data_valid_pong_delay15_16; +wire b_data_valid_pong_delay16_16; +wire b_data_valid_pong_delay17_16; +wire b_data_valid_pong_delay18_16; +wire b_data_valid_pong_delay19_16; +wire b_data_valid_pong_delay20_16; +wire b_data_valid_pong_delay21_16; +wire b_data_valid_pong_delay22_16; +wire b_data_valid_pong_delay23_16; +wire b_data_valid_pong_delay24_16; +wire b_data_valid_pong_delay25_16; +wire b_data_valid_pong_delay26_16; +wire b_data_valid_pong_delay27_16; +wire b_data_valid_pong_delay28_16; +wire b_data_valid_pong_delay29_16; +wire b_data_valid_pong_delay30_16; +wire b_data_valid_pong_delay31_16; +wire b_data_valid_pong_delay1_17; +wire b_data_valid_pong_delay2_17; +wire b_data_valid_pong_delay3_17; +wire b_data_valid_pong_delay4_17; +wire b_data_valid_pong_delay5_17; +wire b_data_valid_pong_delay6_17; +wire b_data_valid_pong_delay7_17; +wire b_data_valid_pong_delay8_17; +wire b_data_valid_pong_delay9_17; +wire b_data_valid_pong_delay10_17; +wire b_data_valid_pong_delay11_17; +wire b_data_valid_pong_delay12_17; +wire b_data_valid_pong_delay13_17; +wire b_data_valid_pong_delay14_17; +wire b_data_valid_pong_delay15_17; +wire b_data_valid_pong_delay16_17; +wire b_data_valid_pong_delay17_17; +wire b_data_valid_pong_delay18_17; +wire b_data_valid_pong_delay19_17; +wire b_data_valid_pong_delay20_17; +wire b_data_valid_pong_delay21_17; +wire b_data_valid_pong_delay22_17; +wire b_data_valid_pong_delay23_17; +wire b_data_valid_pong_delay24_17; +wire b_data_valid_pong_delay25_17; +wire b_data_valid_pong_delay26_17; +wire b_data_valid_pong_delay27_17; +wire b_data_valid_pong_delay28_17; +wire b_data_valid_pong_delay29_17; +wire b_data_valid_pong_delay30_17; +wire b_data_valid_pong_delay31_17; +wire b_data_valid_pong_delay1_18; +wire b_data_valid_pong_delay2_18; +wire b_data_valid_pong_delay3_18; +wire b_data_valid_pong_delay4_18; +wire b_data_valid_pong_delay5_18; +wire b_data_valid_pong_delay6_18; +wire b_data_valid_pong_delay7_18; +wire b_data_valid_pong_delay8_18; +wire b_data_valid_pong_delay9_18; +wire b_data_valid_pong_delay10_18; +wire b_data_valid_pong_delay11_18; +wire b_data_valid_pong_delay12_18; +wire b_data_valid_pong_delay13_18; +wire b_data_valid_pong_delay14_18; +wire b_data_valid_pong_delay15_18; +wire b_data_valid_pong_delay16_18; +wire b_data_valid_pong_delay17_18; +wire b_data_valid_pong_delay18_18; +wire b_data_valid_pong_delay19_18; +wire b_data_valid_pong_delay20_18; +wire b_data_valid_pong_delay21_18; +wire b_data_valid_pong_delay22_18; +wire b_data_valid_pong_delay23_18; +wire b_data_valid_pong_delay24_18; +wire b_data_valid_pong_delay25_18; +wire b_data_valid_pong_delay26_18; +wire b_data_valid_pong_delay27_18; +wire b_data_valid_pong_delay28_18; +wire b_data_valid_pong_delay29_18; +wire b_data_valid_pong_delay30_18; +wire b_data_valid_pong_delay31_18; +wire b_data_valid_pong_delay1_19; +wire b_data_valid_pong_delay2_19; +wire b_data_valid_pong_delay3_19; +wire b_data_valid_pong_delay4_19; +wire b_data_valid_pong_delay5_19; +wire b_data_valid_pong_delay6_19; +wire b_data_valid_pong_delay7_19; +wire b_data_valid_pong_delay8_19; +wire b_data_valid_pong_delay9_19; +wire b_data_valid_pong_delay10_19; +wire b_data_valid_pong_delay11_19; +wire b_data_valid_pong_delay12_19; +wire b_data_valid_pong_delay13_19; +wire b_data_valid_pong_delay14_19; +wire b_data_valid_pong_delay15_19; +wire b_data_valid_pong_delay16_19; +wire b_data_valid_pong_delay17_19; +wire b_data_valid_pong_delay18_19; +wire b_data_valid_pong_delay19_19; +wire b_data_valid_pong_delay20_19; +wire b_data_valid_pong_delay21_19; +wire b_data_valid_pong_delay22_19; +wire b_data_valid_pong_delay23_19; +wire b_data_valid_pong_delay24_19; +wire b_data_valid_pong_delay25_19; +wire b_data_valid_pong_delay26_19; +wire b_data_valid_pong_delay27_19; +wire b_data_valid_pong_delay28_19; +wire b_data_valid_pong_delay29_19; +wire b_data_valid_pong_delay30_19; +wire b_data_valid_pong_delay31_19; +wire b_data_valid_pong_delay1_20; +wire b_data_valid_pong_delay2_20; +wire b_data_valid_pong_delay3_20; +wire b_data_valid_pong_delay4_20; +wire b_data_valid_pong_delay5_20; +wire b_data_valid_pong_delay6_20; +wire b_data_valid_pong_delay7_20; +wire b_data_valid_pong_delay8_20; +wire b_data_valid_pong_delay9_20; +wire b_data_valid_pong_delay10_20; +wire b_data_valid_pong_delay11_20; +wire b_data_valid_pong_delay12_20; +wire b_data_valid_pong_delay13_20; +wire b_data_valid_pong_delay14_20; +wire b_data_valid_pong_delay15_20; +wire b_data_valid_pong_delay16_20; +wire b_data_valid_pong_delay17_20; +wire b_data_valid_pong_delay18_20; +wire b_data_valid_pong_delay19_20; +wire b_data_valid_pong_delay20_20; +wire b_data_valid_pong_delay21_20; +wire b_data_valid_pong_delay22_20; +wire b_data_valid_pong_delay23_20; +wire b_data_valid_pong_delay24_20; +wire b_data_valid_pong_delay25_20; +wire b_data_valid_pong_delay26_20; +wire b_data_valid_pong_delay27_20; +wire b_data_valid_pong_delay28_20; +wire b_data_valid_pong_delay29_20; +wire b_data_valid_pong_delay30_20; +wire b_data_valid_pong_delay31_20; +wire b_data_valid_pong_delay1_21; +wire b_data_valid_pong_delay2_21; +wire b_data_valid_pong_delay3_21; +wire b_data_valid_pong_delay4_21; +wire b_data_valid_pong_delay5_21; +wire b_data_valid_pong_delay6_21; +wire b_data_valid_pong_delay7_21; +wire b_data_valid_pong_delay8_21; +wire b_data_valid_pong_delay9_21; +wire b_data_valid_pong_delay10_21; +wire b_data_valid_pong_delay11_21; +wire b_data_valid_pong_delay12_21; +wire b_data_valid_pong_delay13_21; +wire b_data_valid_pong_delay14_21; +wire b_data_valid_pong_delay15_21; +wire b_data_valid_pong_delay16_21; +wire b_data_valid_pong_delay17_21; +wire b_data_valid_pong_delay18_21; +wire b_data_valid_pong_delay19_21; +wire b_data_valid_pong_delay20_21; +wire b_data_valid_pong_delay21_21; +wire b_data_valid_pong_delay22_21; +wire b_data_valid_pong_delay23_21; +wire b_data_valid_pong_delay24_21; +wire b_data_valid_pong_delay25_21; +wire b_data_valid_pong_delay26_21; +wire b_data_valid_pong_delay27_21; +wire b_data_valid_pong_delay28_21; +wire b_data_valid_pong_delay29_21; +wire b_data_valid_pong_delay30_21; +wire b_data_valid_pong_delay31_21; +wire b_data_valid_pong_delay1_22; +wire b_data_valid_pong_delay2_22; +wire b_data_valid_pong_delay3_22; +wire b_data_valid_pong_delay4_22; +wire b_data_valid_pong_delay5_22; +wire b_data_valid_pong_delay6_22; +wire b_data_valid_pong_delay7_22; +wire b_data_valid_pong_delay8_22; +wire b_data_valid_pong_delay9_22; +wire b_data_valid_pong_delay10_22; +wire b_data_valid_pong_delay11_22; +wire b_data_valid_pong_delay12_22; +wire b_data_valid_pong_delay13_22; +wire b_data_valid_pong_delay14_22; +wire b_data_valid_pong_delay15_22; +wire b_data_valid_pong_delay16_22; +wire b_data_valid_pong_delay17_22; +wire b_data_valid_pong_delay18_22; +wire b_data_valid_pong_delay19_22; +wire b_data_valid_pong_delay20_22; +wire b_data_valid_pong_delay21_22; +wire b_data_valid_pong_delay22_22; +wire b_data_valid_pong_delay23_22; +wire b_data_valid_pong_delay24_22; +wire b_data_valid_pong_delay25_22; +wire b_data_valid_pong_delay26_22; +wire b_data_valid_pong_delay27_22; +wire b_data_valid_pong_delay28_22; +wire b_data_valid_pong_delay29_22; +wire b_data_valid_pong_delay30_22; +wire b_data_valid_pong_delay31_22; +wire b_data_valid_pong_delay1_23; +wire b_data_valid_pong_delay2_23; +wire b_data_valid_pong_delay3_23; +wire b_data_valid_pong_delay4_23; +wire b_data_valid_pong_delay5_23; +wire b_data_valid_pong_delay6_23; +wire b_data_valid_pong_delay7_23; +wire b_data_valid_pong_delay8_23; +wire b_data_valid_pong_delay9_23; +wire b_data_valid_pong_delay10_23; +wire b_data_valid_pong_delay11_23; +wire b_data_valid_pong_delay12_23; +wire b_data_valid_pong_delay13_23; +wire b_data_valid_pong_delay14_23; +wire b_data_valid_pong_delay15_23; +wire b_data_valid_pong_delay16_23; +wire b_data_valid_pong_delay17_23; +wire b_data_valid_pong_delay18_23; +wire b_data_valid_pong_delay19_23; +wire b_data_valid_pong_delay20_23; +wire b_data_valid_pong_delay21_23; +wire b_data_valid_pong_delay22_23; +wire b_data_valid_pong_delay23_23; +wire b_data_valid_pong_delay24_23; +wire b_data_valid_pong_delay25_23; +wire b_data_valid_pong_delay26_23; +wire b_data_valid_pong_delay27_23; +wire b_data_valid_pong_delay28_23; +wire b_data_valid_pong_delay29_23; +wire b_data_valid_pong_delay30_23; +wire b_data_valid_pong_delay31_23; +wire b_data_valid_pong_delay1_24; +wire b_data_valid_pong_delay2_24; +wire b_data_valid_pong_delay3_24; +wire b_data_valid_pong_delay4_24; +wire b_data_valid_pong_delay5_24; +wire b_data_valid_pong_delay6_24; +wire b_data_valid_pong_delay7_24; +wire b_data_valid_pong_delay8_24; +wire b_data_valid_pong_delay9_24; +wire b_data_valid_pong_delay10_24; +wire b_data_valid_pong_delay11_24; +wire b_data_valid_pong_delay12_24; +wire b_data_valid_pong_delay13_24; +wire b_data_valid_pong_delay14_24; +wire b_data_valid_pong_delay15_24; +wire b_data_valid_pong_delay16_24; +wire b_data_valid_pong_delay17_24; +wire b_data_valid_pong_delay18_24; +wire b_data_valid_pong_delay19_24; +wire b_data_valid_pong_delay20_24; +wire b_data_valid_pong_delay21_24; +wire b_data_valid_pong_delay22_24; +wire b_data_valid_pong_delay23_24; +wire b_data_valid_pong_delay24_24; +wire b_data_valid_pong_delay25_24; +wire b_data_valid_pong_delay26_24; +wire b_data_valid_pong_delay27_24; +wire b_data_valid_pong_delay28_24; +wire b_data_valid_pong_delay29_24; +wire b_data_valid_pong_delay30_24; +wire b_data_valid_pong_delay31_24; +wire b_data_valid_pong_delay1_25; +wire b_data_valid_pong_delay2_25; +wire b_data_valid_pong_delay3_25; +wire b_data_valid_pong_delay4_25; +wire b_data_valid_pong_delay5_25; +wire b_data_valid_pong_delay6_25; +wire b_data_valid_pong_delay7_25; +wire b_data_valid_pong_delay8_25; +wire b_data_valid_pong_delay9_25; +wire b_data_valid_pong_delay10_25; +wire b_data_valid_pong_delay11_25; +wire b_data_valid_pong_delay12_25; +wire b_data_valid_pong_delay13_25; +wire b_data_valid_pong_delay14_25; +wire b_data_valid_pong_delay15_25; +wire b_data_valid_pong_delay16_25; +wire b_data_valid_pong_delay17_25; +wire b_data_valid_pong_delay18_25; +wire b_data_valid_pong_delay19_25; +wire b_data_valid_pong_delay20_25; +wire b_data_valid_pong_delay21_25; +wire b_data_valid_pong_delay22_25; +wire b_data_valid_pong_delay23_25; +wire b_data_valid_pong_delay24_25; +wire b_data_valid_pong_delay25_25; +wire b_data_valid_pong_delay26_25; +wire b_data_valid_pong_delay27_25; +wire b_data_valid_pong_delay28_25; +wire b_data_valid_pong_delay29_25; +wire b_data_valid_pong_delay30_25; +wire b_data_valid_pong_delay31_25; +wire b_data_valid_pong_delay1_26; +wire b_data_valid_pong_delay2_26; +wire b_data_valid_pong_delay3_26; +wire b_data_valid_pong_delay4_26; +wire b_data_valid_pong_delay5_26; +wire b_data_valid_pong_delay6_26; +wire b_data_valid_pong_delay7_26; +wire b_data_valid_pong_delay8_26; +wire b_data_valid_pong_delay9_26; +wire b_data_valid_pong_delay10_26; +wire b_data_valid_pong_delay11_26; +wire b_data_valid_pong_delay12_26; +wire b_data_valid_pong_delay13_26; +wire b_data_valid_pong_delay14_26; +wire b_data_valid_pong_delay15_26; +wire b_data_valid_pong_delay16_26; +wire b_data_valid_pong_delay17_26; +wire b_data_valid_pong_delay18_26; +wire b_data_valid_pong_delay19_26; +wire b_data_valid_pong_delay20_26; +wire b_data_valid_pong_delay21_26; +wire b_data_valid_pong_delay22_26; +wire b_data_valid_pong_delay23_26; +wire b_data_valid_pong_delay24_26; +wire b_data_valid_pong_delay25_26; +wire b_data_valid_pong_delay26_26; +wire b_data_valid_pong_delay27_26; +wire b_data_valid_pong_delay28_26; +wire b_data_valid_pong_delay29_26; +wire b_data_valid_pong_delay30_26; +wire b_data_valid_pong_delay31_26; +wire b_data_valid_pong_delay1_27; +wire b_data_valid_pong_delay2_27; +wire b_data_valid_pong_delay3_27; +wire b_data_valid_pong_delay4_27; +wire b_data_valid_pong_delay5_27; +wire b_data_valid_pong_delay6_27; +wire b_data_valid_pong_delay7_27; +wire b_data_valid_pong_delay8_27; +wire b_data_valid_pong_delay9_27; +wire b_data_valid_pong_delay10_27; +wire b_data_valid_pong_delay11_27; +wire b_data_valid_pong_delay12_27; +wire b_data_valid_pong_delay13_27; +wire b_data_valid_pong_delay14_27; +wire b_data_valid_pong_delay15_27; +wire b_data_valid_pong_delay16_27; +wire b_data_valid_pong_delay17_27; +wire b_data_valid_pong_delay18_27; +wire b_data_valid_pong_delay19_27; +wire b_data_valid_pong_delay20_27; +wire b_data_valid_pong_delay21_27; +wire b_data_valid_pong_delay22_27; +wire b_data_valid_pong_delay23_27; +wire b_data_valid_pong_delay24_27; +wire b_data_valid_pong_delay25_27; +wire b_data_valid_pong_delay26_27; +wire b_data_valid_pong_delay27_27; +wire b_data_valid_pong_delay28_27; +wire b_data_valid_pong_delay29_27; +wire b_data_valid_pong_delay30_27; +wire b_data_valid_pong_delay31_27; +wire b_data_valid_pong_delay1_28; +wire b_data_valid_pong_delay2_28; +wire b_data_valid_pong_delay3_28; +wire b_data_valid_pong_delay4_28; +wire b_data_valid_pong_delay5_28; +wire b_data_valid_pong_delay6_28; +wire b_data_valid_pong_delay7_28; +wire b_data_valid_pong_delay8_28; +wire b_data_valid_pong_delay9_28; +wire b_data_valid_pong_delay10_28; +wire b_data_valid_pong_delay11_28; +wire b_data_valid_pong_delay12_28; +wire b_data_valid_pong_delay13_28; +wire b_data_valid_pong_delay14_28; +wire b_data_valid_pong_delay15_28; +wire b_data_valid_pong_delay16_28; +wire b_data_valid_pong_delay17_28; +wire b_data_valid_pong_delay18_28; +wire b_data_valid_pong_delay19_28; +wire b_data_valid_pong_delay20_28; +wire b_data_valid_pong_delay21_28; +wire b_data_valid_pong_delay22_28; +wire b_data_valid_pong_delay23_28; +wire b_data_valid_pong_delay24_28; +wire b_data_valid_pong_delay25_28; +wire b_data_valid_pong_delay26_28; +wire b_data_valid_pong_delay27_28; +wire b_data_valid_pong_delay28_28; +wire b_data_valid_pong_delay29_28; +wire b_data_valid_pong_delay30_28; +wire b_data_valid_pong_delay31_28; +wire b_data_valid_pong_delay1_29; +wire b_data_valid_pong_delay2_29; +wire b_data_valid_pong_delay3_29; +wire b_data_valid_pong_delay4_29; +wire b_data_valid_pong_delay5_29; +wire b_data_valid_pong_delay6_29; +wire b_data_valid_pong_delay7_29; +wire b_data_valid_pong_delay8_29; +wire b_data_valid_pong_delay9_29; +wire b_data_valid_pong_delay10_29; +wire b_data_valid_pong_delay11_29; +wire b_data_valid_pong_delay12_29; +wire b_data_valid_pong_delay13_29; +wire b_data_valid_pong_delay14_29; +wire b_data_valid_pong_delay15_29; +wire b_data_valid_pong_delay16_29; +wire b_data_valid_pong_delay17_29; +wire b_data_valid_pong_delay18_29; +wire b_data_valid_pong_delay19_29; +wire b_data_valid_pong_delay20_29; +wire b_data_valid_pong_delay21_29; +wire b_data_valid_pong_delay22_29; +wire b_data_valid_pong_delay23_29; +wire b_data_valid_pong_delay24_29; +wire b_data_valid_pong_delay25_29; +wire b_data_valid_pong_delay26_29; +wire b_data_valid_pong_delay27_29; +wire b_data_valid_pong_delay28_29; +wire b_data_valid_pong_delay29_29; +wire b_data_valid_pong_delay30_29; +wire b_data_valid_pong_delay31_29; +wire b_data_valid_pong_delay1_30; +wire b_data_valid_pong_delay2_30; +wire b_data_valid_pong_delay3_30; +wire b_data_valid_pong_delay4_30; +wire b_data_valid_pong_delay5_30; +wire b_data_valid_pong_delay6_30; +wire b_data_valid_pong_delay7_30; +wire b_data_valid_pong_delay8_30; +wire b_data_valid_pong_delay9_30; +wire b_data_valid_pong_delay10_30; +wire b_data_valid_pong_delay11_30; +wire b_data_valid_pong_delay12_30; +wire b_data_valid_pong_delay13_30; +wire b_data_valid_pong_delay14_30; +wire b_data_valid_pong_delay15_30; +wire b_data_valid_pong_delay16_30; +wire b_data_valid_pong_delay17_30; +wire b_data_valid_pong_delay18_30; +wire b_data_valid_pong_delay19_30; +wire b_data_valid_pong_delay20_30; +wire b_data_valid_pong_delay21_30; +wire b_data_valid_pong_delay22_30; +wire b_data_valid_pong_delay23_30; +wire b_data_valid_pong_delay24_30; +wire b_data_valid_pong_delay25_30; +wire b_data_valid_pong_delay26_30; +wire b_data_valid_pong_delay27_30; +wire b_data_valid_pong_delay28_30; +wire b_data_valid_pong_delay29_30; +wire b_data_valid_pong_delay30_30; +wire b_data_valid_pong_delay31_30; +wire b_data_valid_pong_delay1_31; +wire b_data_valid_pong_delay2_31; +wire b_data_valid_pong_delay3_31; +wire b_data_valid_pong_delay4_31; +wire b_data_valid_pong_delay5_31; +wire b_data_valid_pong_delay6_31; +wire b_data_valid_pong_delay7_31; +wire b_data_valid_pong_delay8_31; +wire b_data_valid_pong_delay9_31; +wire b_data_valid_pong_delay10_31; +wire b_data_valid_pong_delay11_31; +wire b_data_valid_pong_delay12_31; +wire b_data_valid_pong_delay13_31; +wire b_data_valid_pong_delay14_31; +wire b_data_valid_pong_delay15_31; +wire b_data_valid_pong_delay16_31; +wire b_data_valid_pong_delay17_31; +wire b_data_valid_pong_delay18_31; +wire b_data_valid_pong_delay19_31; +wire b_data_valid_pong_delay20_31; +wire b_data_valid_pong_delay21_31; +wire b_data_valid_pong_delay22_31; +wire b_data_valid_pong_delay23_31; +wire b_data_valid_pong_delay24_31; +wire b_data_valid_pong_delay25_31; +wire b_data_valid_pong_delay26_31; +wire b_data_valid_pong_delay27_31; +wire b_data_valid_pong_delay28_31; +wire b_data_valid_pong_delay29_31; +wire b_data_valid_pong_delay30_31; +wire b_data_valid_pong_delay31_31; + +always @ (posedge clk) begin + b_data_valid_pong_delay0_1 <= b_data_valid_pong; + b_data_valid_pong_delay0_2 <= b_data_valid_pong_delay0_1; + b_data_valid_pong_delay0_3 <= b_data_valid_pong_delay0_2; + b_data_valid_pong_delay0_4 <= b_data_valid_pong_delay0_3; + b_data_valid_pong_delay0_5 <= b_data_valid_pong_delay0_4; + b_data_valid_pong_delay0_6 <= b_data_valid_pong_delay0_5; + b_data_valid_pong_delay0_7 <= b_data_valid_pong_delay0_6; + b_data_valid_pong_delay0_8 <= b_data_valid_pong_delay0_7; + b_data_valid_pong_delay0_9 <= b_data_valid_pong_delay0_8; + b_data_valid_pong_delay0_10 <= b_data_valid_pong_delay0_9; + b_data_valid_pong_delay0_11 <= b_data_valid_pong_delay0_10; + b_data_valid_pong_delay0_12 <= b_data_valid_pong_delay0_11; + b_data_valid_pong_delay0_13 <= b_data_valid_pong_delay0_12; + b_data_valid_pong_delay0_14 <= b_data_valid_pong_delay0_13; + b_data_valid_pong_delay0_15 <= b_data_valid_pong_delay0_14; + b_data_valid_pong_delay0_16 <= b_data_valid_pong_delay0_15; + b_data_valid_pong_delay0_17 <= b_data_valid_pong_delay0_16; + b_data_valid_pong_delay0_18 <= b_data_valid_pong_delay0_17; + b_data_valid_pong_delay0_19 <= b_data_valid_pong_delay0_18; + b_data_valid_pong_delay0_20 <= b_data_valid_pong_delay0_19; + b_data_valid_pong_delay0_21 <= b_data_valid_pong_delay0_20; + b_data_valid_pong_delay0_22 <= b_data_valid_pong_delay0_21; + b_data_valid_pong_delay0_23 <= b_data_valid_pong_delay0_22; + b_data_valid_pong_delay0_24 <= b_data_valid_pong_delay0_23; + b_data_valid_pong_delay0_25 <= b_data_valid_pong_delay0_24; + b_data_valid_pong_delay0_26 <= b_data_valid_pong_delay0_25; + b_data_valid_pong_delay0_27 <= b_data_valid_pong_delay0_26; + b_data_valid_pong_delay0_28 <= b_data_valid_pong_delay0_27; + b_data_valid_pong_delay0_29 <= b_data_valid_pong_delay0_28; + b_data_valid_pong_delay0_30 <= b_data_valid_pong_delay0_29; + b_data_valid_pong_delay0_31 <= b_data_valid_pong_delay0_30; + b_data_valid_pong_delay0_32 <= b_data_valid_pong_delay0_31; + b_data_valid_pong_delay0_33 <= b_data_valid_pong_delay0_32; + b_data_valid_pong_delay0_34 <= b_data_valid_pong_delay0_33; + b_data_valid_pong_delay0_35 <= b_data_valid_pong_delay0_34; + b_data_valid_pong_delay0_36 <= b_data_valid_pong_delay0_35; + b_data_valid_pong_delay0_37 <= b_data_valid_pong_delay0_36; + b_data_valid_pong_delay0_38 <= b_data_valid_pong_delay0_37; + b_data_valid_pong_delay0_39 <= b_data_valid_pong_delay0_38; + b_data_valid_pong_delay0_40 <= b_data_valid_pong_delay0_39; + b_data_valid_pong_delay0_41 <= b_data_valid_pong_delay0_40; + b_data_valid_pong_delay0_42 <= b_data_valid_pong_delay0_41; + b_data_valid_pong_delay0_43 <= b_data_valid_pong_delay0_42; + b_data_valid_pong_delay0_44 <= b_data_valid_pong_delay0_43; + b_data_valid_pong_delay0_45 <= b_data_valid_pong_delay0_44; + b_data_valid_pong_delay0_46 <= b_data_valid_pong_delay0_45; + b_data_valid_pong_delay0_47 <= b_data_valid_pong_delay0_46; + b_data_valid_pong_delay0_48 <= b_data_valid_pong_delay0_47; + b_data_valid_pong_delay0_49 <= b_data_valid_pong_delay0_48; + b_data_valid_pong_delay0_50 <= b_data_valid_pong_delay0_49; + b_data_valid_pong_delay0_51 <= b_data_valid_pong_delay0_50; + b_data_valid_pong_delay0_52 <= b_data_valid_pong_delay0_51; + b_data_valid_pong_delay0_53 <= b_data_valid_pong_delay0_52; + b_data_valid_pong_delay0_54 <= b_data_valid_pong_delay0_53; + b_data_valid_pong_delay0_55 <= b_data_valid_pong_delay0_54; + b_data_valid_pong_delay0_56 <= b_data_valid_pong_delay0_55; + b_data_valid_pong_delay0_57 <= b_data_valid_pong_delay0_56; + b_data_valid_pong_delay0_58 <= b_data_valid_pong_delay0_57; + b_data_valid_pong_delay0_59 <= b_data_valid_pong_delay0_58; + b_data_valid_pong_delay0_60 <= b_data_valid_pong_delay0_59; + b_data_valid_pong_delay0_61 <= b_data_valid_pong_delay0_60; + b_data_valid_pong_delay0_62 <= b_data_valid_pong_delay0_61; +end + +assign b_data_valid_pong_delay1_0 = b_data_valid_pong & b_data_valid_pong_delay0_1; +assign b_data_valid_pong_delay2_0 = b_data_valid_pong & b_data_valid_pong_delay0_2; +assign b_data_valid_pong_delay3_0 = b_data_valid_pong & b_data_valid_pong_delay0_3; +assign b_data_valid_pong_delay4_0 = b_data_valid_pong & b_data_valid_pong_delay0_4; +assign b_data_valid_pong_delay5_0 = b_data_valid_pong & b_data_valid_pong_delay0_5; +assign b_data_valid_pong_delay6_0 = b_data_valid_pong & b_data_valid_pong_delay0_6; +assign b_data_valid_pong_delay7_0 = b_data_valid_pong & b_data_valid_pong_delay0_7; +assign b_data_valid_pong_delay8_0 = b_data_valid_pong & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay9_0 = b_data_valid_pong & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay10_0 = b_data_valid_pong & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay11_0 = b_data_valid_pong & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay12_0 = b_data_valid_pong & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay13_0 = b_data_valid_pong & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay14_0 = b_data_valid_pong & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay15_0 = b_data_valid_pong & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay16_0 = b_data_valid_pong & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay17_0 = b_data_valid_pong & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay18_0 = b_data_valid_pong & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay19_0 = b_data_valid_pong & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay20_0 = b_data_valid_pong & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay21_0 = b_data_valid_pong & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay22_0 = b_data_valid_pong & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay23_0 = b_data_valid_pong & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay24_0 = b_data_valid_pong & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay25_0 = b_data_valid_pong & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay26_0 = b_data_valid_pong & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay27_0 = b_data_valid_pong & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay28_0 = b_data_valid_pong & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay29_0 = b_data_valid_pong & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay30_0 = b_data_valid_pong & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay31_0 = b_data_valid_pong & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay1_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_2; +assign b_data_valid_pong_delay2_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_3; +assign b_data_valid_pong_delay3_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_4; +assign b_data_valid_pong_delay4_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_5; +assign b_data_valid_pong_delay5_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_6; +assign b_data_valid_pong_delay6_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_7; +assign b_data_valid_pong_delay7_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay8_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay9_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay10_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay11_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay12_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay13_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay14_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay15_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay16_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay17_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay18_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay19_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay20_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay21_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay22_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay23_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay24_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay25_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay26_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay27_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay28_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay29_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay30_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay31_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay1_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_3; +assign b_data_valid_pong_delay2_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_4; +assign b_data_valid_pong_delay3_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_5; +assign b_data_valid_pong_delay4_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_6; +assign b_data_valid_pong_delay5_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_7; +assign b_data_valid_pong_delay6_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay7_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay8_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay9_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay10_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay11_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay12_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay13_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay14_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay15_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay16_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay17_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay18_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay19_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay20_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay21_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay22_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay23_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay24_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay25_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay26_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay27_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay28_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay29_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay30_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay31_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay1_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_4; +assign b_data_valid_pong_delay2_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_5; +assign b_data_valid_pong_delay3_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_6; +assign b_data_valid_pong_delay4_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_7; +assign b_data_valid_pong_delay5_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay6_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay7_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay8_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay9_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay10_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay11_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay12_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay13_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay14_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay15_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay16_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay17_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay18_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay19_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay20_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay21_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay22_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay23_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay24_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay25_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay26_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay27_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay28_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay29_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay30_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay31_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay1_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_5; +assign b_data_valid_pong_delay2_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_6; +assign b_data_valid_pong_delay3_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_7; +assign b_data_valid_pong_delay4_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay5_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay6_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay7_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay8_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay9_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay10_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay11_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay12_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay13_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay14_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay15_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay16_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay17_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay18_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay19_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay20_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay21_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay22_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay23_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay24_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay25_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay26_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay27_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay28_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay29_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay30_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay31_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay1_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_6; +assign b_data_valid_pong_delay2_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_7; +assign b_data_valid_pong_delay3_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay4_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay5_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay6_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay7_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay8_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay9_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay10_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay11_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay12_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay13_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay14_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay15_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay16_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay17_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay18_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay19_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay20_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay21_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay22_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay23_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay24_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay25_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay26_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay27_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay28_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay29_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay30_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay31_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay1_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_7; +assign b_data_valid_pong_delay2_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay3_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay4_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay5_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay6_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay7_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay8_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay9_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay10_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay11_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay12_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay13_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay14_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay15_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay16_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay17_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay18_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay19_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay20_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay21_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay22_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay23_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay24_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay25_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay26_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay27_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay28_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay29_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay30_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay31_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay1_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay2_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay3_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay4_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay5_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay6_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay7_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay8_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay9_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay10_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay11_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay12_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay13_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay14_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay15_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay16_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay17_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay18_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay19_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay20_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay21_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay22_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay23_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay24_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay25_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay26_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay27_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay28_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay29_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay30_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay31_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay1_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay2_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay3_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay4_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay5_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay6_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay7_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay8_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay9_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay10_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay11_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay12_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay13_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay14_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay15_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay16_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay17_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay18_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay19_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay20_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay21_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay22_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay23_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay24_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay25_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay26_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay27_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay28_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay29_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay30_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay31_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay1_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay2_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay3_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay4_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay5_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay6_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay7_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay8_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay9_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay10_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay11_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay12_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay13_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay14_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay15_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay16_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay17_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay18_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay19_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay20_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay21_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay22_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay23_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay24_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay25_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay26_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay27_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay28_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay29_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay30_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay31_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay1_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay2_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay3_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay4_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay5_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay6_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay7_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay8_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay9_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay10_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay11_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay12_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay13_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay14_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay15_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay16_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay17_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay18_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay19_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay20_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay21_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay22_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay23_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay24_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay25_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay26_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay27_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay28_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay29_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay30_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay31_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay1_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay2_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay3_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay4_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay5_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay6_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay7_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay8_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay9_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay10_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay11_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay12_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay13_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay14_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay15_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay16_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay17_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay18_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay19_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay20_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay21_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay22_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay23_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay24_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay25_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay26_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay27_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay28_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay29_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay30_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay31_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay1_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay2_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay3_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay4_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay5_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay6_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay7_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay8_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay9_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay10_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay11_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay12_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay13_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay14_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay15_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay16_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay17_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay18_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay19_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay20_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay21_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay22_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay23_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay24_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay25_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay26_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay27_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay28_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay29_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay30_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay31_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay1_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay2_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay3_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay4_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay5_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay6_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay7_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay8_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay9_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay10_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay11_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay12_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay13_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay14_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay15_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay16_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay17_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay18_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay19_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay20_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay21_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay22_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay23_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay24_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay25_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay26_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay27_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay28_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay29_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay30_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay31_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay1_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay2_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay3_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay4_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay5_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay6_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay7_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay8_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay9_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay10_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay11_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay12_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay13_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay14_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay15_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay16_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay17_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay18_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay19_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay20_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay21_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay22_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay23_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay24_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay25_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay26_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay27_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay28_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay29_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay30_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay31_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay1_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay2_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay3_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay4_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay5_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay6_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay7_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay8_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay9_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay10_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay11_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay12_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay13_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay14_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay15_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay16_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay17_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay18_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay19_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay20_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay21_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay22_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay23_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay24_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay25_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay26_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay27_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay28_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay29_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay30_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay31_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay1_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay2_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay3_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay4_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay5_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay6_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay7_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay8_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay9_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay10_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay11_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay12_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay13_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay14_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay15_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay16_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay17_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay18_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay19_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay20_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay21_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay22_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay23_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay24_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay25_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay26_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay27_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay28_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay29_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay30_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay31_16 = b_data_valid_pong_delay0_16 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay1_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay2_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay3_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay4_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay5_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay6_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay7_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay8_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay9_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay10_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay11_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay12_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay13_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay14_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay15_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay16_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay17_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay18_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay19_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay20_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay21_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay22_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay23_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay24_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay25_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay26_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay27_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay28_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay29_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay30_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay31_17 = b_data_valid_pong_delay0_17 & b_data_valid_pong_delay0_48; +assign b_data_valid_pong_delay1_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay2_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay3_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay4_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay5_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay6_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay7_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay8_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay9_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay10_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay11_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay12_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay13_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay14_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay15_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay16_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay17_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay18_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay19_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay20_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay21_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay22_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay23_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay24_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay25_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay26_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay27_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay28_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay29_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay30_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_48; +assign b_data_valid_pong_delay31_18 = b_data_valid_pong_delay0_18 & b_data_valid_pong_delay0_49; +assign b_data_valid_pong_delay1_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay2_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay3_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay4_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay5_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay6_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay7_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay8_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay9_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay10_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay11_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay12_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay13_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay14_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay15_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay16_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay17_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay18_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay19_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay20_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay21_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay22_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay23_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay24_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay25_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay26_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay27_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay28_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay29_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_48; +assign b_data_valid_pong_delay30_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_49; +assign b_data_valid_pong_delay31_19 = b_data_valid_pong_delay0_19 & b_data_valid_pong_delay0_50; +assign b_data_valid_pong_delay1_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay2_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay3_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay4_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay5_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay6_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay7_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay8_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay9_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay10_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay11_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay12_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay13_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay14_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay15_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay16_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay17_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay18_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay19_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay20_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay21_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay22_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay23_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay24_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay25_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay26_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay27_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay28_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_48; +assign b_data_valid_pong_delay29_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_49; +assign b_data_valid_pong_delay30_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_50; +assign b_data_valid_pong_delay31_20 = b_data_valid_pong_delay0_20 & b_data_valid_pong_delay0_51; +assign b_data_valid_pong_delay1_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay2_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay3_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay4_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay5_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay6_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay7_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay8_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay9_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay10_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay11_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay12_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay13_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay14_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay15_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay16_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay17_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay18_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay19_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay20_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay21_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay22_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay23_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay24_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay25_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay26_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay27_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_48; +assign b_data_valid_pong_delay28_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_49; +assign b_data_valid_pong_delay29_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_50; +assign b_data_valid_pong_delay30_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_51; +assign b_data_valid_pong_delay31_21 = b_data_valid_pong_delay0_21 & b_data_valid_pong_delay0_52; +assign b_data_valid_pong_delay1_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay2_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay3_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay4_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay5_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay6_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay7_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay8_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay9_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay10_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay11_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay12_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay13_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay14_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay15_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay16_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay17_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay18_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay19_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay20_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay21_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay22_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay23_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay24_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay25_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay26_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_48; +assign b_data_valid_pong_delay27_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_49; +assign b_data_valid_pong_delay28_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_50; +assign b_data_valid_pong_delay29_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_51; +assign b_data_valid_pong_delay30_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_52; +assign b_data_valid_pong_delay31_22 = b_data_valid_pong_delay0_22 & b_data_valid_pong_delay0_53; +assign b_data_valid_pong_delay1_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay2_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay3_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay4_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay5_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay6_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay7_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay8_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay9_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay10_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay11_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay12_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay13_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay14_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay15_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay16_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay17_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay18_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay19_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay20_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay21_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay22_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay23_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay24_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay25_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_48; +assign b_data_valid_pong_delay26_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_49; +assign b_data_valid_pong_delay27_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_50; +assign b_data_valid_pong_delay28_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_51; +assign b_data_valid_pong_delay29_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_52; +assign b_data_valid_pong_delay30_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_53; +assign b_data_valid_pong_delay31_23 = b_data_valid_pong_delay0_23 & b_data_valid_pong_delay0_54; +assign b_data_valid_pong_delay1_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay2_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay3_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay4_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay5_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay6_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay7_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay8_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay9_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay10_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay11_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay12_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay13_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay14_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay15_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay16_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay17_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay18_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay19_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay20_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay21_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay22_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay23_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay24_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_48; +assign b_data_valid_pong_delay25_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_49; +assign b_data_valid_pong_delay26_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_50; +assign b_data_valid_pong_delay27_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_51; +assign b_data_valid_pong_delay28_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_52; +assign b_data_valid_pong_delay29_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_53; +assign b_data_valid_pong_delay30_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_54; +assign b_data_valid_pong_delay31_24 = b_data_valid_pong_delay0_24 & b_data_valid_pong_delay0_55; +assign b_data_valid_pong_delay1_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay2_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay3_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay4_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay5_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay6_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay7_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay8_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay9_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay10_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay11_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay12_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay13_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay14_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay15_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay16_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay17_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay18_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay19_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay20_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay21_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay22_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay23_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_48; +assign b_data_valid_pong_delay24_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_49; +assign b_data_valid_pong_delay25_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_50; +assign b_data_valid_pong_delay26_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_51; +assign b_data_valid_pong_delay27_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_52; +assign b_data_valid_pong_delay28_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_53; +assign b_data_valid_pong_delay29_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_54; +assign b_data_valid_pong_delay30_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_55; +assign b_data_valid_pong_delay31_25 = b_data_valid_pong_delay0_25 & b_data_valid_pong_delay0_56; +assign b_data_valid_pong_delay1_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay2_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay3_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay4_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay5_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay6_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay7_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay8_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay9_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay10_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay11_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay12_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay13_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay14_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay15_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay16_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay17_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay18_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay19_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay20_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay21_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay22_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_48; +assign b_data_valid_pong_delay23_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_49; +assign b_data_valid_pong_delay24_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_50; +assign b_data_valid_pong_delay25_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_51; +assign b_data_valid_pong_delay26_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_52; +assign b_data_valid_pong_delay27_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_53; +assign b_data_valid_pong_delay28_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_54; +assign b_data_valid_pong_delay29_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_55; +assign b_data_valid_pong_delay30_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_56; +assign b_data_valid_pong_delay31_26 = b_data_valid_pong_delay0_26 & b_data_valid_pong_delay0_57; +assign b_data_valid_pong_delay1_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay2_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay3_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay4_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay5_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay6_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay7_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay8_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay9_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay10_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay11_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay12_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay13_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay14_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay15_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay16_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay17_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay18_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay19_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay20_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay21_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_48; +assign b_data_valid_pong_delay22_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_49; +assign b_data_valid_pong_delay23_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_50; +assign b_data_valid_pong_delay24_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_51; +assign b_data_valid_pong_delay25_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_52; +assign b_data_valid_pong_delay26_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_53; +assign b_data_valid_pong_delay27_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_54; +assign b_data_valid_pong_delay28_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_55; +assign b_data_valid_pong_delay29_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_56; +assign b_data_valid_pong_delay30_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_57; +assign b_data_valid_pong_delay31_27 = b_data_valid_pong_delay0_27 & b_data_valid_pong_delay0_58; +assign b_data_valid_pong_delay1_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay2_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay3_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay4_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay5_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay6_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay7_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay8_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay9_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay10_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay11_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay12_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay13_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay14_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay15_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay16_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay17_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay18_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay19_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay20_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_48; +assign b_data_valid_pong_delay21_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_49; +assign b_data_valid_pong_delay22_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_50; +assign b_data_valid_pong_delay23_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_51; +assign b_data_valid_pong_delay24_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_52; +assign b_data_valid_pong_delay25_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_53; +assign b_data_valid_pong_delay26_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_54; +assign b_data_valid_pong_delay27_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_55; +assign b_data_valid_pong_delay28_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_56; +assign b_data_valid_pong_delay29_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_57; +assign b_data_valid_pong_delay30_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_58; +assign b_data_valid_pong_delay31_28 = b_data_valid_pong_delay0_28 & b_data_valid_pong_delay0_59; +assign b_data_valid_pong_delay1_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_30; +assign b_data_valid_pong_delay2_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay3_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay4_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay5_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay6_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay7_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay8_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay9_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay10_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay11_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay12_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay13_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay14_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay15_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay16_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay17_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay18_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay19_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_48; +assign b_data_valid_pong_delay20_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_49; +assign b_data_valid_pong_delay21_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_50; +assign b_data_valid_pong_delay22_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_51; +assign b_data_valid_pong_delay23_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_52; +assign b_data_valid_pong_delay24_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_53; +assign b_data_valid_pong_delay25_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_54; +assign b_data_valid_pong_delay26_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_55; +assign b_data_valid_pong_delay27_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_56; +assign b_data_valid_pong_delay28_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_57; +assign b_data_valid_pong_delay29_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_58; +assign b_data_valid_pong_delay30_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_59; +assign b_data_valid_pong_delay31_29 = b_data_valid_pong_delay0_29 & b_data_valid_pong_delay0_60; +assign b_data_valid_pong_delay1_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_31; +assign b_data_valid_pong_delay2_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay3_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay4_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay5_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay6_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay7_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay8_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay9_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay10_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay11_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay12_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay13_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay14_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay15_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay16_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay17_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay18_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_48; +assign b_data_valid_pong_delay19_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_49; +assign b_data_valid_pong_delay20_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_50; +assign b_data_valid_pong_delay21_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_51; +assign b_data_valid_pong_delay22_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_52; +assign b_data_valid_pong_delay23_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_53; +assign b_data_valid_pong_delay24_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_54; +assign b_data_valid_pong_delay25_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_55; +assign b_data_valid_pong_delay26_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_56; +assign b_data_valid_pong_delay27_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_57; +assign b_data_valid_pong_delay28_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_58; +assign b_data_valid_pong_delay29_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_59; +assign b_data_valid_pong_delay30_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_60; +assign b_data_valid_pong_delay31_30 = b_data_valid_pong_delay0_30 & b_data_valid_pong_delay0_61; +assign b_data_valid_pong_delay1_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_32; +assign b_data_valid_pong_delay2_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_33; +assign b_data_valid_pong_delay3_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_34; +assign b_data_valid_pong_delay4_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_35; +assign b_data_valid_pong_delay5_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_36; +assign b_data_valid_pong_delay6_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_37; +assign b_data_valid_pong_delay7_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_38; +assign b_data_valid_pong_delay8_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_39; +assign b_data_valid_pong_delay9_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_40; +assign b_data_valid_pong_delay10_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_41; +assign b_data_valid_pong_delay11_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_42; +assign b_data_valid_pong_delay12_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_43; +assign b_data_valid_pong_delay13_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_44; +assign b_data_valid_pong_delay14_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_45; +assign b_data_valid_pong_delay15_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_46; +assign b_data_valid_pong_delay16_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_47; +assign b_data_valid_pong_delay17_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_48; +assign b_data_valid_pong_delay18_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_49; +assign b_data_valid_pong_delay19_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_50; +assign b_data_valid_pong_delay20_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_51; +assign b_data_valid_pong_delay21_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_52; +assign b_data_valid_pong_delay22_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_53; +assign b_data_valid_pong_delay23_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_54; +assign b_data_valid_pong_delay24_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_55; +assign b_data_valid_pong_delay25_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_56; +assign b_data_valid_pong_delay26_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_57; +assign b_data_valid_pong_delay27_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_58; +assign b_data_valid_pong_delay28_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_59; +assign b_data_valid_pong_delay29_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_60; +assign b_data_valid_pong_delay30_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_61; +assign b_data_valid_pong_delay31_31 = b_data_valid_pong_delay0_31 & b_data_valid_pong_delay0_62; + +// Signals for Each PING buffer + +reg b_data_valid_ping_delay0_1; +reg b_data_valid_ping_delay0_2; +reg b_data_valid_ping_delay0_3; +reg b_data_valid_ping_delay0_4; +reg b_data_valid_ping_delay0_5; +reg b_data_valid_ping_delay0_6; +reg b_data_valid_ping_delay0_7; +reg b_data_valid_ping_delay0_8; +reg b_data_valid_ping_delay0_9; +reg b_data_valid_ping_delay0_10; +reg b_data_valid_ping_delay0_11; +reg b_data_valid_ping_delay0_12; +reg b_data_valid_ping_delay0_13; +reg b_data_valid_ping_delay0_14; +reg b_data_valid_ping_delay0_15; +reg b_data_valid_ping_delay0_16; +reg b_data_valid_ping_delay0_17; +reg b_data_valid_ping_delay0_18; +reg b_data_valid_ping_delay0_19; +reg b_data_valid_ping_delay0_20; +reg b_data_valid_ping_delay0_21; +reg b_data_valid_ping_delay0_22; +reg b_data_valid_ping_delay0_23; +reg b_data_valid_ping_delay0_24; +reg b_data_valid_ping_delay0_25; +reg b_data_valid_ping_delay0_26; +reg b_data_valid_ping_delay0_27; +reg b_data_valid_ping_delay0_28; +reg b_data_valid_ping_delay0_29; +reg b_data_valid_ping_delay0_30; +reg b_data_valid_ping_delay0_31; +reg b_data_valid_ping_delay0_32; +reg b_data_valid_ping_delay0_33; +reg b_data_valid_ping_delay0_34; +reg b_data_valid_ping_delay0_35; +reg b_data_valid_ping_delay0_36; +reg b_data_valid_ping_delay0_37; +reg b_data_valid_ping_delay0_38; +reg b_data_valid_ping_delay0_39; +reg b_data_valid_ping_delay0_40; +reg b_data_valid_ping_delay0_41; +reg b_data_valid_ping_delay0_42; +reg b_data_valid_ping_delay0_43; +reg b_data_valid_ping_delay0_44; +reg b_data_valid_ping_delay0_45; +reg b_data_valid_ping_delay0_46; +reg b_data_valid_ping_delay0_47; +reg b_data_valid_ping_delay0_48; +reg b_data_valid_ping_delay0_49; +reg b_data_valid_ping_delay0_50; +reg b_data_valid_ping_delay0_51; +reg b_data_valid_ping_delay0_52; +reg b_data_valid_ping_delay0_53; +reg b_data_valid_ping_delay0_54; +reg b_data_valid_ping_delay0_55; +reg b_data_valid_ping_delay0_56; +reg b_data_valid_ping_delay0_57; +reg b_data_valid_ping_delay0_58; +reg b_data_valid_ping_delay0_59; +reg b_data_valid_ping_delay0_60; +reg b_data_valid_ping_delay0_61; +reg b_data_valid_ping_delay0_62; +wire b_data_valid_ping_delay1_0; +wire b_data_valid_ping_delay2_0; +wire b_data_valid_ping_delay3_0; +wire b_data_valid_ping_delay4_0; +wire b_data_valid_ping_delay5_0; +wire b_data_valid_ping_delay6_0; +wire b_data_valid_ping_delay7_0; +wire b_data_valid_ping_delay8_0; +wire b_data_valid_ping_delay9_0; +wire b_data_valid_ping_delay10_0; +wire b_data_valid_ping_delay11_0; +wire b_data_valid_ping_delay12_0; +wire b_data_valid_ping_delay13_0; +wire b_data_valid_ping_delay14_0; +wire b_data_valid_ping_delay15_0; +wire b_data_valid_ping_delay16_0; +wire b_data_valid_ping_delay17_0; +wire b_data_valid_ping_delay18_0; +wire b_data_valid_ping_delay19_0; +wire b_data_valid_ping_delay20_0; +wire b_data_valid_ping_delay21_0; +wire b_data_valid_ping_delay22_0; +wire b_data_valid_ping_delay23_0; +wire b_data_valid_ping_delay24_0; +wire b_data_valid_ping_delay25_0; +wire b_data_valid_ping_delay26_0; +wire b_data_valid_ping_delay27_0; +wire b_data_valid_ping_delay28_0; +wire b_data_valid_ping_delay29_0; +wire b_data_valid_ping_delay30_0; +wire b_data_valid_ping_delay31_0; +wire b_data_valid_ping_delay1_1; +wire b_data_valid_ping_delay2_1; +wire b_data_valid_ping_delay3_1; +wire b_data_valid_ping_delay4_1; +wire b_data_valid_ping_delay5_1; +wire b_data_valid_ping_delay6_1; +wire b_data_valid_ping_delay7_1; +wire b_data_valid_ping_delay8_1; +wire b_data_valid_ping_delay9_1; +wire b_data_valid_ping_delay10_1; +wire b_data_valid_ping_delay11_1; +wire b_data_valid_ping_delay12_1; +wire b_data_valid_ping_delay13_1; +wire b_data_valid_ping_delay14_1; +wire b_data_valid_ping_delay15_1; +wire b_data_valid_ping_delay16_1; +wire b_data_valid_ping_delay17_1; +wire b_data_valid_ping_delay18_1; +wire b_data_valid_ping_delay19_1; +wire b_data_valid_ping_delay20_1; +wire b_data_valid_ping_delay21_1; +wire b_data_valid_ping_delay22_1; +wire b_data_valid_ping_delay23_1; +wire b_data_valid_ping_delay24_1; +wire b_data_valid_ping_delay25_1; +wire b_data_valid_ping_delay26_1; +wire b_data_valid_ping_delay27_1; +wire b_data_valid_ping_delay28_1; +wire b_data_valid_ping_delay29_1; +wire b_data_valid_ping_delay30_1; +wire b_data_valid_ping_delay31_1; +wire b_data_valid_ping_delay1_2; +wire b_data_valid_ping_delay2_2; +wire b_data_valid_ping_delay3_2; +wire b_data_valid_ping_delay4_2; +wire b_data_valid_ping_delay5_2; +wire b_data_valid_ping_delay6_2; +wire b_data_valid_ping_delay7_2; +wire b_data_valid_ping_delay8_2; +wire b_data_valid_ping_delay9_2; +wire b_data_valid_ping_delay10_2; +wire b_data_valid_ping_delay11_2; +wire b_data_valid_ping_delay12_2; +wire b_data_valid_ping_delay13_2; +wire b_data_valid_ping_delay14_2; +wire b_data_valid_ping_delay15_2; +wire b_data_valid_ping_delay16_2; +wire b_data_valid_ping_delay17_2; +wire b_data_valid_ping_delay18_2; +wire b_data_valid_ping_delay19_2; +wire b_data_valid_ping_delay20_2; +wire b_data_valid_ping_delay21_2; +wire b_data_valid_ping_delay22_2; +wire b_data_valid_ping_delay23_2; +wire b_data_valid_ping_delay24_2; +wire b_data_valid_ping_delay25_2; +wire b_data_valid_ping_delay26_2; +wire b_data_valid_ping_delay27_2; +wire b_data_valid_ping_delay28_2; +wire b_data_valid_ping_delay29_2; +wire b_data_valid_ping_delay30_2; +wire b_data_valid_ping_delay31_2; +wire b_data_valid_ping_delay1_3; +wire b_data_valid_ping_delay2_3; +wire b_data_valid_ping_delay3_3; +wire b_data_valid_ping_delay4_3; +wire b_data_valid_ping_delay5_3; +wire b_data_valid_ping_delay6_3; +wire b_data_valid_ping_delay7_3; +wire b_data_valid_ping_delay8_3; +wire b_data_valid_ping_delay9_3; +wire b_data_valid_ping_delay10_3; +wire b_data_valid_ping_delay11_3; +wire b_data_valid_ping_delay12_3; +wire b_data_valid_ping_delay13_3; +wire b_data_valid_ping_delay14_3; +wire b_data_valid_ping_delay15_3; +wire b_data_valid_ping_delay16_3; +wire b_data_valid_ping_delay17_3; +wire b_data_valid_ping_delay18_3; +wire b_data_valid_ping_delay19_3; +wire b_data_valid_ping_delay20_3; +wire b_data_valid_ping_delay21_3; +wire b_data_valid_ping_delay22_3; +wire b_data_valid_ping_delay23_3; +wire b_data_valid_ping_delay24_3; +wire b_data_valid_ping_delay25_3; +wire b_data_valid_ping_delay26_3; +wire b_data_valid_ping_delay27_3; +wire b_data_valid_ping_delay28_3; +wire b_data_valid_ping_delay29_3; +wire b_data_valid_ping_delay30_3; +wire b_data_valid_ping_delay31_3; +wire b_data_valid_ping_delay1_4; +wire b_data_valid_ping_delay2_4; +wire b_data_valid_ping_delay3_4; +wire b_data_valid_ping_delay4_4; +wire b_data_valid_ping_delay5_4; +wire b_data_valid_ping_delay6_4; +wire b_data_valid_ping_delay7_4; +wire b_data_valid_ping_delay8_4; +wire b_data_valid_ping_delay9_4; +wire b_data_valid_ping_delay10_4; +wire b_data_valid_ping_delay11_4; +wire b_data_valid_ping_delay12_4; +wire b_data_valid_ping_delay13_4; +wire b_data_valid_ping_delay14_4; +wire b_data_valid_ping_delay15_4; +wire b_data_valid_ping_delay16_4; +wire b_data_valid_ping_delay17_4; +wire b_data_valid_ping_delay18_4; +wire b_data_valid_ping_delay19_4; +wire b_data_valid_ping_delay20_4; +wire b_data_valid_ping_delay21_4; +wire b_data_valid_ping_delay22_4; +wire b_data_valid_ping_delay23_4; +wire b_data_valid_ping_delay24_4; +wire b_data_valid_ping_delay25_4; +wire b_data_valid_ping_delay26_4; +wire b_data_valid_ping_delay27_4; +wire b_data_valid_ping_delay28_4; +wire b_data_valid_ping_delay29_4; +wire b_data_valid_ping_delay30_4; +wire b_data_valid_ping_delay31_4; +wire b_data_valid_ping_delay1_5; +wire b_data_valid_ping_delay2_5; +wire b_data_valid_ping_delay3_5; +wire b_data_valid_ping_delay4_5; +wire b_data_valid_ping_delay5_5; +wire b_data_valid_ping_delay6_5; +wire b_data_valid_ping_delay7_5; +wire b_data_valid_ping_delay8_5; +wire b_data_valid_ping_delay9_5; +wire b_data_valid_ping_delay10_5; +wire b_data_valid_ping_delay11_5; +wire b_data_valid_ping_delay12_5; +wire b_data_valid_ping_delay13_5; +wire b_data_valid_ping_delay14_5; +wire b_data_valid_ping_delay15_5; +wire b_data_valid_ping_delay16_5; +wire b_data_valid_ping_delay17_5; +wire b_data_valid_ping_delay18_5; +wire b_data_valid_ping_delay19_5; +wire b_data_valid_ping_delay20_5; +wire b_data_valid_ping_delay21_5; +wire b_data_valid_ping_delay22_5; +wire b_data_valid_ping_delay23_5; +wire b_data_valid_ping_delay24_5; +wire b_data_valid_ping_delay25_5; +wire b_data_valid_ping_delay26_5; +wire b_data_valid_ping_delay27_5; +wire b_data_valid_ping_delay28_5; +wire b_data_valid_ping_delay29_5; +wire b_data_valid_ping_delay30_5; +wire b_data_valid_ping_delay31_5; +wire b_data_valid_ping_delay1_6; +wire b_data_valid_ping_delay2_6; +wire b_data_valid_ping_delay3_6; +wire b_data_valid_ping_delay4_6; +wire b_data_valid_ping_delay5_6; +wire b_data_valid_ping_delay6_6; +wire b_data_valid_ping_delay7_6; +wire b_data_valid_ping_delay8_6; +wire b_data_valid_ping_delay9_6; +wire b_data_valid_ping_delay10_6; +wire b_data_valid_ping_delay11_6; +wire b_data_valid_ping_delay12_6; +wire b_data_valid_ping_delay13_6; +wire b_data_valid_ping_delay14_6; +wire b_data_valid_ping_delay15_6; +wire b_data_valid_ping_delay16_6; +wire b_data_valid_ping_delay17_6; +wire b_data_valid_ping_delay18_6; +wire b_data_valid_ping_delay19_6; +wire b_data_valid_ping_delay20_6; +wire b_data_valid_ping_delay21_6; +wire b_data_valid_ping_delay22_6; +wire b_data_valid_ping_delay23_6; +wire b_data_valid_ping_delay24_6; +wire b_data_valid_ping_delay25_6; +wire b_data_valid_ping_delay26_6; +wire b_data_valid_ping_delay27_6; +wire b_data_valid_ping_delay28_6; +wire b_data_valid_ping_delay29_6; +wire b_data_valid_ping_delay30_6; +wire b_data_valid_ping_delay31_6; +wire b_data_valid_ping_delay1_7; +wire b_data_valid_ping_delay2_7; +wire b_data_valid_ping_delay3_7; +wire b_data_valid_ping_delay4_7; +wire b_data_valid_ping_delay5_7; +wire b_data_valid_ping_delay6_7; +wire b_data_valid_ping_delay7_7; +wire b_data_valid_ping_delay8_7; +wire b_data_valid_ping_delay9_7; +wire b_data_valid_ping_delay10_7; +wire b_data_valid_ping_delay11_7; +wire b_data_valid_ping_delay12_7; +wire b_data_valid_ping_delay13_7; +wire b_data_valid_ping_delay14_7; +wire b_data_valid_ping_delay15_7; +wire b_data_valid_ping_delay16_7; +wire b_data_valid_ping_delay17_7; +wire b_data_valid_ping_delay18_7; +wire b_data_valid_ping_delay19_7; +wire b_data_valid_ping_delay20_7; +wire b_data_valid_ping_delay21_7; +wire b_data_valid_ping_delay22_7; +wire b_data_valid_ping_delay23_7; +wire b_data_valid_ping_delay24_7; +wire b_data_valid_ping_delay25_7; +wire b_data_valid_ping_delay26_7; +wire b_data_valid_ping_delay27_7; +wire b_data_valid_ping_delay28_7; +wire b_data_valid_ping_delay29_7; +wire b_data_valid_ping_delay30_7; +wire b_data_valid_ping_delay31_7; +wire b_data_valid_ping_delay1_8; +wire b_data_valid_ping_delay2_8; +wire b_data_valid_ping_delay3_8; +wire b_data_valid_ping_delay4_8; +wire b_data_valid_ping_delay5_8; +wire b_data_valid_ping_delay6_8; +wire b_data_valid_ping_delay7_8; +wire b_data_valid_ping_delay8_8; +wire b_data_valid_ping_delay9_8; +wire b_data_valid_ping_delay10_8; +wire b_data_valid_ping_delay11_8; +wire b_data_valid_ping_delay12_8; +wire b_data_valid_ping_delay13_8; +wire b_data_valid_ping_delay14_8; +wire b_data_valid_ping_delay15_8; +wire b_data_valid_ping_delay16_8; +wire b_data_valid_ping_delay17_8; +wire b_data_valid_ping_delay18_8; +wire b_data_valid_ping_delay19_8; +wire b_data_valid_ping_delay20_8; +wire b_data_valid_ping_delay21_8; +wire b_data_valid_ping_delay22_8; +wire b_data_valid_ping_delay23_8; +wire b_data_valid_ping_delay24_8; +wire b_data_valid_ping_delay25_8; +wire b_data_valid_ping_delay26_8; +wire b_data_valid_ping_delay27_8; +wire b_data_valid_ping_delay28_8; +wire b_data_valid_ping_delay29_8; +wire b_data_valid_ping_delay30_8; +wire b_data_valid_ping_delay31_8; +wire b_data_valid_ping_delay1_9; +wire b_data_valid_ping_delay2_9; +wire b_data_valid_ping_delay3_9; +wire b_data_valid_ping_delay4_9; +wire b_data_valid_ping_delay5_9; +wire b_data_valid_ping_delay6_9; +wire b_data_valid_ping_delay7_9; +wire b_data_valid_ping_delay8_9; +wire b_data_valid_ping_delay9_9; +wire b_data_valid_ping_delay10_9; +wire b_data_valid_ping_delay11_9; +wire b_data_valid_ping_delay12_9; +wire b_data_valid_ping_delay13_9; +wire b_data_valid_ping_delay14_9; +wire b_data_valid_ping_delay15_9; +wire b_data_valid_ping_delay16_9; +wire b_data_valid_ping_delay17_9; +wire b_data_valid_ping_delay18_9; +wire b_data_valid_ping_delay19_9; +wire b_data_valid_ping_delay20_9; +wire b_data_valid_ping_delay21_9; +wire b_data_valid_ping_delay22_9; +wire b_data_valid_ping_delay23_9; +wire b_data_valid_ping_delay24_9; +wire b_data_valid_ping_delay25_9; +wire b_data_valid_ping_delay26_9; +wire b_data_valid_ping_delay27_9; +wire b_data_valid_ping_delay28_9; +wire b_data_valid_ping_delay29_9; +wire b_data_valid_ping_delay30_9; +wire b_data_valid_ping_delay31_9; +wire b_data_valid_ping_delay1_10; +wire b_data_valid_ping_delay2_10; +wire b_data_valid_ping_delay3_10; +wire b_data_valid_ping_delay4_10; +wire b_data_valid_ping_delay5_10; +wire b_data_valid_ping_delay6_10; +wire b_data_valid_ping_delay7_10; +wire b_data_valid_ping_delay8_10; +wire b_data_valid_ping_delay9_10; +wire b_data_valid_ping_delay10_10; +wire b_data_valid_ping_delay11_10; +wire b_data_valid_ping_delay12_10; +wire b_data_valid_ping_delay13_10; +wire b_data_valid_ping_delay14_10; +wire b_data_valid_ping_delay15_10; +wire b_data_valid_ping_delay16_10; +wire b_data_valid_ping_delay17_10; +wire b_data_valid_ping_delay18_10; +wire b_data_valid_ping_delay19_10; +wire b_data_valid_ping_delay20_10; +wire b_data_valid_ping_delay21_10; +wire b_data_valid_ping_delay22_10; +wire b_data_valid_ping_delay23_10; +wire b_data_valid_ping_delay24_10; +wire b_data_valid_ping_delay25_10; +wire b_data_valid_ping_delay26_10; +wire b_data_valid_ping_delay27_10; +wire b_data_valid_ping_delay28_10; +wire b_data_valid_ping_delay29_10; +wire b_data_valid_ping_delay30_10; +wire b_data_valid_ping_delay31_10; +wire b_data_valid_ping_delay1_11; +wire b_data_valid_ping_delay2_11; +wire b_data_valid_ping_delay3_11; +wire b_data_valid_ping_delay4_11; +wire b_data_valid_ping_delay5_11; +wire b_data_valid_ping_delay6_11; +wire b_data_valid_ping_delay7_11; +wire b_data_valid_ping_delay8_11; +wire b_data_valid_ping_delay9_11; +wire b_data_valid_ping_delay10_11; +wire b_data_valid_ping_delay11_11; +wire b_data_valid_ping_delay12_11; +wire b_data_valid_ping_delay13_11; +wire b_data_valid_ping_delay14_11; +wire b_data_valid_ping_delay15_11; +wire b_data_valid_ping_delay16_11; +wire b_data_valid_ping_delay17_11; +wire b_data_valid_ping_delay18_11; +wire b_data_valid_ping_delay19_11; +wire b_data_valid_ping_delay20_11; +wire b_data_valid_ping_delay21_11; +wire b_data_valid_ping_delay22_11; +wire b_data_valid_ping_delay23_11; +wire b_data_valid_ping_delay24_11; +wire b_data_valid_ping_delay25_11; +wire b_data_valid_ping_delay26_11; +wire b_data_valid_ping_delay27_11; +wire b_data_valid_ping_delay28_11; +wire b_data_valid_ping_delay29_11; +wire b_data_valid_ping_delay30_11; +wire b_data_valid_ping_delay31_11; +wire b_data_valid_ping_delay1_12; +wire b_data_valid_ping_delay2_12; +wire b_data_valid_ping_delay3_12; +wire b_data_valid_ping_delay4_12; +wire b_data_valid_ping_delay5_12; +wire b_data_valid_ping_delay6_12; +wire b_data_valid_ping_delay7_12; +wire b_data_valid_ping_delay8_12; +wire b_data_valid_ping_delay9_12; +wire b_data_valid_ping_delay10_12; +wire b_data_valid_ping_delay11_12; +wire b_data_valid_ping_delay12_12; +wire b_data_valid_ping_delay13_12; +wire b_data_valid_ping_delay14_12; +wire b_data_valid_ping_delay15_12; +wire b_data_valid_ping_delay16_12; +wire b_data_valid_ping_delay17_12; +wire b_data_valid_ping_delay18_12; +wire b_data_valid_ping_delay19_12; +wire b_data_valid_ping_delay20_12; +wire b_data_valid_ping_delay21_12; +wire b_data_valid_ping_delay22_12; +wire b_data_valid_ping_delay23_12; +wire b_data_valid_ping_delay24_12; +wire b_data_valid_ping_delay25_12; +wire b_data_valid_ping_delay26_12; +wire b_data_valid_ping_delay27_12; +wire b_data_valid_ping_delay28_12; +wire b_data_valid_ping_delay29_12; +wire b_data_valid_ping_delay30_12; +wire b_data_valid_ping_delay31_12; +wire b_data_valid_ping_delay1_13; +wire b_data_valid_ping_delay2_13; +wire b_data_valid_ping_delay3_13; +wire b_data_valid_ping_delay4_13; +wire b_data_valid_ping_delay5_13; +wire b_data_valid_ping_delay6_13; +wire b_data_valid_ping_delay7_13; +wire b_data_valid_ping_delay8_13; +wire b_data_valid_ping_delay9_13; +wire b_data_valid_ping_delay10_13; +wire b_data_valid_ping_delay11_13; +wire b_data_valid_ping_delay12_13; +wire b_data_valid_ping_delay13_13; +wire b_data_valid_ping_delay14_13; +wire b_data_valid_ping_delay15_13; +wire b_data_valid_ping_delay16_13; +wire b_data_valid_ping_delay17_13; +wire b_data_valid_ping_delay18_13; +wire b_data_valid_ping_delay19_13; +wire b_data_valid_ping_delay20_13; +wire b_data_valid_ping_delay21_13; +wire b_data_valid_ping_delay22_13; +wire b_data_valid_ping_delay23_13; +wire b_data_valid_ping_delay24_13; +wire b_data_valid_ping_delay25_13; +wire b_data_valid_ping_delay26_13; +wire b_data_valid_ping_delay27_13; +wire b_data_valid_ping_delay28_13; +wire b_data_valid_ping_delay29_13; +wire b_data_valid_ping_delay30_13; +wire b_data_valid_ping_delay31_13; +wire b_data_valid_ping_delay1_14; +wire b_data_valid_ping_delay2_14; +wire b_data_valid_ping_delay3_14; +wire b_data_valid_ping_delay4_14; +wire b_data_valid_ping_delay5_14; +wire b_data_valid_ping_delay6_14; +wire b_data_valid_ping_delay7_14; +wire b_data_valid_ping_delay8_14; +wire b_data_valid_ping_delay9_14; +wire b_data_valid_ping_delay10_14; +wire b_data_valid_ping_delay11_14; +wire b_data_valid_ping_delay12_14; +wire b_data_valid_ping_delay13_14; +wire b_data_valid_ping_delay14_14; +wire b_data_valid_ping_delay15_14; +wire b_data_valid_ping_delay16_14; +wire b_data_valid_ping_delay17_14; +wire b_data_valid_ping_delay18_14; +wire b_data_valid_ping_delay19_14; +wire b_data_valid_ping_delay20_14; +wire b_data_valid_ping_delay21_14; +wire b_data_valid_ping_delay22_14; +wire b_data_valid_ping_delay23_14; +wire b_data_valid_ping_delay24_14; +wire b_data_valid_ping_delay25_14; +wire b_data_valid_ping_delay26_14; +wire b_data_valid_ping_delay27_14; +wire b_data_valid_ping_delay28_14; +wire b_data_valid_ping_delay29_14; +wire b_data_valid_ping_delay30_14; +wire b_data_valid_ping_delay31_14; +wire b_data_valid_ping_delay1_15; +wire b_data_valid_ping_delay2_15; +wire b_data_valid_ping_delay3_15; +wire b_data_valid_ping_delay4_15; +wire b_data_valid_ping_delay5_15; +wire b_data_valid_ping_delay6_15; +wire b_data_valid_ping_delay7_15; +wire b_data_valid_ping_delay8_15; +wire b_data_valid_ping_delay9_15; +wire b_data_valid_ping_delay10_15; +wire b_data_valid_ping_delay11_15; +wire b_data_valid_ping_delay12_15; +wire b_data_valid_ping_delay13_15; +wire b_data_valid_ping_delay14_15; +wire b_data_valid_ping_delay15_15; +wire b_data_valid_ping_delay16_15; +wire b_data_valid_ping_delay17_15; +wire b_data_valid_ping_delay18_15; +wire b_data_valid_ping_delay19_15; +wire b_data_valid_ping_delay20_15; +wire b_data_valid_ping_delay21_15; +wire b_data_valid_ping_delay22_15; +wire b_data_valid_ping_delay23_15; +wire b_data_valid_ping_delay24_15; +wire b_data_valid_ping_delay25_15; +wire b_data_valid_ping_delay26_15; +wire b_data_valid_ping_delay27_15; +wire b_data_valid_ping_delay28_15; +wire b_data_valid_ping_delay29_15; +wire b_data_valid_ping_delay30_15; +wire b_data_valid_ping_delay31_15; +wire b_data_valid_ping_delay1_16; +wire b_data_valid_ping_delay2_16; +wire b_data_valid_ping_delay3_16; +wire b_data_valid_ping_delay4_16; +wire b_data_valid_ping_delay5_16; +wire b_data_valid_ping_delay6_16; +wire b_data_valid_ping_delay7_16; +wire b_data_valid_ping_delay8_16; +wire b_data_valid_ping_delay9_16; +wire b_data_valid_ping_delay10_16; +wire b_data_valid_ping_delay11_16; +wire b_data_valid_ping_delay12_16; +wire b_data_valid_ping_delay13_16; +wire b_data_valid_ping_delay14_16; +wire b_data_valid_ping_delay15_16; +wire b_data_valid_ping_delay16_16; +wire b_data_valid_ping_delay17_16; +wire b_data_valid_ping_delay18_16; +wire b_data_valid_ping_delay19_16; +wire b_data_valid_ping_delay20_16; +wire b_data_valid_ping_delay21_16; +wire b_data_valid_ping_delay22_16; +wire b_data_valid_ping_delay23_16; +wire b_data_valid_ping_delay24_16; +wire b_data_valid_ping_delay25_16; +wire b_data_valid_ping_delay26_16; +wire b_data_valid_ping_delay27_16; +wire b_data_valid_ping_delay28_16; +wire b_data_valid_ping_delay29_16; +wire b_data_valid_ping_delay30_16; +wire b_data_valid_ping_delay31_16; +wire b_data_valid_ping_delay1_17; +wire b_data_valid_ping_delay2_17; +wire b_data_valid_ping_delay3_17; +wire b_data_valid_ping_delay4_17; +wire b_data_valid_ping_delay5_17; +wire b_data_valid_ping_delay6_17; +wire b_data_valid_ping_delay7_17; +wire b_data_valid_ping_delay8_17; +wire b_data_valid_ping_delay9_17; +wire b_data_valid_ping_delay10_17; +wire b_data_valid_ping_delay11_17; +wire b_data_valid_ping_delay12_17; +wire b_data_valid_ping_delay13_17; +wire b_data_valid_ping_delay14_17; +wire b_data_valid_ping_delay15_17; +wire b_data_valid_ping_delay16_17; +wire b_data_valid_ping_delay17_17; +wire b_data_valid_ping_delay18_17; +wire b_data_valid_ping_delay19_17; +wire b_data_valid_ping_delay20_17; +wire b_data_valid_ping_delay21_17; +wire b_data_valid_ping_delay22_17; +wire b_data_valid_ping_delay23_17; +wire b_data_valid_ping_delay24_17; +wire b_data_valid_ping_delay25_17; +wire b_data_valid_ping_delay26_17; +wire b_data_valid_ping_delay27_17; +wire b_data_valid_ping_delay28_17; +wire b_data_valid_ping_delay29_17; +wire b_data_valid_ping_delay30_17; +wire b_data_valid_ping_delay31_17; +wire b_data_valid_ping_delay1_18; +wire b_data_valid_ping_delay2_18; +wire b_data_valid_ping_delay3_18; +wire b_data_valid_ping_delay4_18; +wire b_data_valid_ping_delay5_18; +wire b_data_valid_ping_delay6_18; +wire b_data_valid_ping_delay7_18; +wire b_data_valid_ping_delay8_18; +wire b_data_valid_ping_delay9_18; +wire b_data_valid_ping_delay10_18; +wire b_data_valid_ping_delay11_18; +wire b_data_valid_ping_delay12_18; +wire b_data_valid_ping_delay13_18; +wire b_data_valid_ping_delay14_18; +wire b_data_valid_ping_delay15_18; +wire b_data_valid_ping_delay16_18; +wire b_data_valid_ping_delay17_18; +wire b_data_valid_ping_delay18_18; +wire b_data_valid_ping_delay19_18; +wire b_data_valid_ping_delay20_18; +wire b_data_valid_ping_delay21_18; +wire b_data_valid_ping_delay22_18; +wire b_data_valid_ping_delay23_18; +wire b_data_valid_ping_delay24_18; +wire b_data_valid_ping_delay25_18; +wire b_data_valid_ping_delay26_18; +wire b_data_valid_ping_delay27_18; +wire b_data_valid_ping_delay28_18; +wire b_data_valid_ping_delay29_18; +wire b_data_valid_ping_delay30_18; +wire b_data_valid_ping_delay31_18; +wire b_data_valid_ping_delay1_19; +wire b_data_valid_ping_delay2_19; +wire b_data_valid_ping_delay3_19; +wire b_data_valid_ping_delay4_19; +wire b_data_valid_ping_delay5_19; +wire b_data_valid_ping_delay6_19; +wire b_data_valid_ping_delay7_19; +wire b_data_valid_ping_delay8_19; +wire b_data_valid_ping_delay9_19; +wire b_data_valid_ping_delay10_19; +wire b_data_valid_ping_delay11_19; +wire b_data_valid_ping_delay12_19; +wire b_data_valid_ping_delay13_19; +wire b_data_valid_ping_delay14_19; +wire b_data_valid_ping_delay15_19; +wire b_data_valid_ping_delay16_19; +wire b_data_valid_ping_delay17_19; +wire b_data_valid_ping_delay18_19; +wire b_data_valid_ping_delay19_19; +wire b_data_valid_ping_delay20_19; +wire b_data_valid_ping_delay21_19; +wire b_data_valid_ping_delay22_19; +wire b_data_valid_ping_delay23_19; +wire b_data_valid_ping_delay24_19; +wire b_data_valid_ping_delay25_19; +wire b_data_valid_ping_delay26_19; +wire b_data_valid_ping_delay27_19; +wire b_data_valid_ping_delay28_19; +wire b_data_valid_ping_delay29_19; +wire b_data_valid_ping_delay30_19; +wire b_data_valid_ping_delay31_19; +wire b_data_valid_ping_delay1_20; +wire b_data_valid_ping_delay2_20; +wire b_data_valid_ping_delay3_20; +wire b_data_valid_ping_delay4_20; +wire b_data_valid_ping_delay5_20; +wire b_data_valid_ping_delay6_20; +wire b_data_valid_ping_delay7_20; +wire b_data_valid_ping_delay8_20; +wire b_data_valid_ping_delay9_20; +wire b_data_valid_ping_delay10_20; +wire b_data_valid_ping_delay11_20; +wire b_data_valid_ping_delay12_20; +wire b_data_valid_ping_delay13_20; +wire b_data_valid_ping_delay14_20; +wire b_data_valid_ping_delay15_20; +wire b_data_valid_ping_delay16_20; +wire b_data_valid_ping_delay17_20; +wire b_data_valid_ping_delay18_20; +wire b_data_valid_ping_delay19_20; +wire b_data_valid_ping_delay20_20; +wire b_data_valid_ping_delay21_20; +wire b_data_valid_ping_delay22_20; +wire b_data_valid_ping_delay23_20; +wire b_data_valid_ping_delay24_20; +wire b_data_valid_ping_delay25_20; +wire b_data_valid_ping_delay26_20; +wire b_data_valid_ping_delay27_20; +wire b_data_valid_ping_delay28_20; +wire b_data_valid_ping_delay29_20; +wire b_data_valid_ping_delay30_20; +wire b_data_valid_ping_delay31_20; +wire b_data_valid_ping_delay1_21; +wire b_data_valid_ping_delay2_21; +wire b_data_valid_ping_delay3_21; +wire b_data_valid_ping_delay4_21; +wire b_data_valid_ping_delay5_21; +wire b_data_valid_ping_delay6_21; +wire b_data_valid_ping_delay7_21; +wire b_data_valid_ping_delay8_21; +wire b_data_valid_ping_delay9_21; +wire b_data_valid_ping_delay10_21; +wire b_data_valid_ping_delay11_21; +wire b_data_valid_ping_delay12_21; +wire b_data_valid_ping_delay13_21; +wire b_data_valid_ping_delay14_21; +wire b_data_valid_ping_delay15_21; +wire b_data_valid_ping_delay16_21; +wire b_data_valid_ping_delay17_21; +wire b_data_valid_ping_delay18_21; +wire b_data_valid_ping_delay19_21; +wire b_data_valid_ping_delay20_21; +wire b_data_valid_ping_delay21_21; +wire b_data_valid_ping_delay22_21; +wire b_data_valid_ping_delay23_21; +wire b_data_valid_ping_delay24_21; +wire b_data_valid_ping_delay25_21; +wire b_data_valid_ping_delay26_21; +wire b_data_valid_ping_delay27_21; +wire b_data_valid_ping_delay28_21; +wire b_data_valid_ping_delay29_21; +wire b_data_valid_ping_delay30_21; +wire b_data_valid_ping_delay31_21; +wire b_data_valid_ping_delay1_22; +wire b_data_valid_ping_delay2_22; +wire b_data_valid_ping_delay3_22; +wire b_data_valid_ping_delay4_22; +wire b_data_valid_ping_delay5_22; +wire b_data_valid_ping_delay6_22; +wire b_data_valid_ping_delay7_22; +wire b_data_valid_ping_delay8_22; +wire b_data_valid_ping_delay9_22; +wire b_data_valid_ping_delay10_22; +wire b_data_valid_ping_delay11_22; +wire b_data_valid_ping_delay12_22; +wire b_data_valid_ping_delay13_22; +wire b_data_valid_ping_delay14_22; +wire b_data_valid_ping_delay15_22; +wire b_data_valid_ping_delay16_22; +wire b_data_valid_ping_delay17_22; +wire b_data_valid_ping_delay18_22; +wire b_data_valid_ping_delay19_22; +wire b_data_valid_ping_delay20_22; +wire b_data_valid_ping_delay21_22; +wire b_data_valid_ping_delay22_22; +wire b_data_valid_ping_delay23_22; +wire b_data_valid_ping_delay24_22; +wire b_data_valid_ping_delay25_22; +wire b_data_valid_ping_delay26_22; +wire b_data_valid_ping_delay27_22; +wire b_data_valid_ping_delay28_22; +wire b_data_valid_ping_delay29_22; +wire b_data_valid_ping_delay30_22; +wire b_data_valid_ping_delay31_22; +wire b_data_valid_ping_delay1_23; +wire b_data_valid_ping_delay2_23; +wire b_data_valid_ping_delay3_23; +wire b_data_valid_ping_delay4_23; +wire b_data_valid_ping_delay5_23; +wire b_data_valid_ping_delay6_23; +wire b_data_valid_ping_delay7_23; +wire b_data_valid_ping_delay8_23; +wire b_data_valid_ping_delay9_23; +wire b_data_valid_ping_delay10_23; +wire b_data_valid_ping_delay11_23; +wire b_data_valid_ping_delay12_23; +wire b_data_valid_ping_delay13_23; +wire b_data_valid_ping_delay14_23; +wire b_data_valid_ping_delay15_23; +wire b_data_valid_ping_delay16_23; +wire b_data_valid_ping_delay17_23; +wire b_data_valid_ping_delay18_23; +wire b_data_valid_ping_delay19_23; +wire b_data_valid_ping_delay20_23; +wire b_data_valid_ping_delay21_23; +wire b_data_valid_ping_delay22_23; +wire b_data_valid_ping_delay23_23; +wire b_data_valid_ping_delay24_23; +wire b_data_valid_ping_delay25_23; +wire b_data_valid_ping_delay26_23; +wire b_data_valid_ping_delay27_23; +wire b_data_valid_ping_delay28_23; +wire b_data_valid_ping_delay29_23; +wire b_data_valid_ping_delay30_23; +wire b_data_valid_ping_delay31_23; +wire b_data_valid_ping_delay1_24; +wire b_data_valid_ping_delay2_24; +wire b_data_valid_ping_delay3_24; +wire b_data_valid_ping_delay4_24; +wire b_data_valid_ping_delay5_24; +wire b_data_valid_ping_delay6_24; +wire b_data_valid_ping_delay7_24; +wire b_data_valid_ping_delay8_24; +wire b_data_valid_ping_delay9_24; +wire b_data_valid_ping_delay10_24; +wire b_data_valid_ping_delay11_24; +wire b_data_valid_ping_delay12_24; +wire b_data_valid_ping_delay13_24; +wire b_data_valid_ping_delay14_24; +wire b_data_valid_ping_delay15_24; +wire b_data_valid_ping_delay16_24; +wire b_data_valid_ping_delay17_24; +wire b_data_valid_ping_delay18_24; +wire b_data_valid_ping_delay19_24; +wire b_data_valid_ping_delay20_24; +wire b_data_valid_ping_delay21_24; +wire b_data_valid_ping_delay22_24; +wire b_data_valid_ping_delay23_24; +wire b_data_valid_ping_delay24_24; +wire b_data_valid_ping_delay25_24; +wire b_data_valid_ping_delay26_24; +wire b_data_valid_ping_delay27_24; +wire b_data_valid_ping_delay28_24; +wire b_data_valid_ping_delay29_24; +wire b_data_valid_ping_delay30_24; +wire b_data_valid_ping_delay31_24; +wire b_data_valid_ping_delay1_25; +wire b_data_valid_ping_delay2_25; +wire b_data_valid_ping_delay3_25; +wire b_data_valid_ping_delay4_25; +wire b_data_valid_ping_delay5_25; +wire b_data_valid_ping_delay6_25; +wire b_data_valid_ping_delay7_25; +wire b_data_valid_ping_delay8_25; +wire b_data_valid_ping_delay9_25; +wire b_data_valid_ping_delay10_25; +wire b_data_valid_ping_delay11_25; +wire b_data_valid_ping_delay12_25; +wire b_data_valid_ping_delay13_25; +wire b_data_valid_ping_delay14_25; +wire b_data_valid_ping_delay15_25; +wire b_data_valid_ping_delay16_25; +wire b_data_valid_ping_delay17_25; +wire b_data_valid_ping_delay18_25; +wire b_data_valid_ping_delay19_25; +wire b_data_valid_ping_delay20_25; +wire b_data_valid_ping_delay21_25; +wire b_data_valid_ping_delay22_25; +wire b_data_valid_ping_delay23_25; +wire b_data_valid_ping_delay24_25; +wire b_data_valid_ping_delay25_25; +wire b_data_valid_ping_delay26_25; +wire b_data_valid_ping_delay27_25; +wire b_data_valid_ping_delay28_25; +wire b_data_valid_ping_delay29_25; +wire b_data_valid_ping_delay30_25; +wire b_data_valid_ping_delay31_25; +wire b_data_valid_ping_delay1_26; +wire b_data_valid_ping_delay2_26; +wire b_data_valid_ping_delay3_26; +wire b_data_valid_ping_delay4_26; +wire b_data_valid_ping_delay5_26; +wire b_data_valid_ping_delay6_26; +wire b_data_valid_ping_delay7_26; +wire b_data_valid_ping_delay8_26; +wire b_data_valid_ping_delay9_26; +wire b_data_valid_ping_delay10_26; +wire b_data_valid_ping_delay11_26; +wire b_data_valid_ping_delay12_26; +wire b_data_valid_ping_delay13_26; +wire b_data_valid_ping_delay14_26; +wire b_data_valid_ping_delay15_26; +wire b_data_valid_ping_delay16_26; +wire b_data_valid_ping_delay17_26; +wire b_data_valid_ping_delay18_26; +wire b_data_valid_ping_delay19_26; +wire b_data_valid_ping_delay20_26; +wire b_data_valid_ping_delay21_26; +wire b_data_valid_ping_delay22_26; +wire b_data_valid_ping_delay23_26; +wire b_data_valid_ping_delay24_26; +wire b_data_valid_ping_delay25_26; +wire b_data_valid_ping_delay26_26; +wire b_data_valid_ping_delay27_26; +wire b_data_valid_ping_delay28_26; +wire b_data_valid_ping_delay29_26; +wire b_data_valid_ping_delay30_26; +wire b_data_valid_ping_delay31_26; +wire b_data_valid_ping_delay1_27; +wire b_data_valid_ping_delay2_27; +wire b_data_valid_ping_delay3_27; +wire b_data_valid_ping_delay4_27; +wire b_data_valid_ping_delay5_27; +wire b_data_valid_ping_delay6_27; +wire b_data_valid_ping_delay7_27; +wire b_data_valid_ping_delay8_27; +wire b_data_valid_ping_delay9_27; +wire b_data_valid_ping_delay10_27; +wire b_data_valid_ping_delay11_27; +wire b_data_valid_ping_delay12_27; +wire b_data_valid_ping_delay13_27; +wire b_data_valid_ping_delay14_27; +wire b_data_valid_ping_delay15_27; +wire b_data_valid_ping_delay16_27; +wire b_data_valid_ping_delay17_27; +wire b_data_valid_ping_delay18_27; +wire b_data_valid_ping_delay19_27; +wire b_data_valid_ping_delay20_27; +wire b_data_valid_ping_delay21_27; +wire b_data_valid_ping_delay22_27; +wire b_data_valid_ping_delay23_27; +wire b_data_valid_ping_delay24_27; +wire b_data_valid_ping_delay25_27; +wire b_data_valid_ping_delay26_27; +wire b_data_valid_ping_delay27_27; +wire b_data_valid_ping_delay28_27; +wire b_data_valid_ping_delay29_27; +wire b_data_valid_ping_delay30_27; +wire b_data_valid_ping_delay31_27; +wire b_data_valid_ping_delay1_28; +wire b_data_valid_ping_delay2_28; +wire b_data_valid_ping_delay3_28; +wire b_data_valid_ping_delay4_28; +wire b_data_valid_ping_delay5_28; +wire b_data_valid_ping_delay6_28; +wire b_data_valid_ping_delay7_28; +wire b_data_valid_ping_delay8_28; +wire b_data_valid_ping_delay9_28; +wire b_data_valid_ping_delay10_28; +wire b_data_valid_ping_delay11_28; +wire b_data_valid_ping_delay12_28; +wire b_data_valid_ping_delay13_28; +wire b_data_valid_ping_delay14_28; +wire b_data_valid_ping_delay15_28; +wire b_data_valid_ping_delay16_28; +wire b_data_valid_ping_delay17_28; +wire b_data_valid_ping_delay18_28; +wire b_data_valid_ping_delay19_28; +wire b_data_valid_ping_delay20_28; +wire b_data_valid_ping_delay21_28; +wire b_data_valid_ping_delay22_28; +wire b_data_valid_ping_delay23_28; +wire b_data_valid_ping_delay24_28; +wire b_data_valid_ping_delay25_28; +wire b_data_valid_ping_delay26_28; +wire b_data_valid_ping_delay27_28; +wire b_data_valid_ping_delay28_28; +wire b_data_valid_ping_delay29_28; +wire b_data_valid_ping_delay30_28; +wire b_data_valid_ping_delay31_28; +wire b_data_valid_ping_delay1_29; +wire b_data_valid_ping_delay2_29; +wire b_data_valid_ping_delay3_29; +wire b_data_valid_ping_delay4_29; +wire b_data_valid_ping_delay5_29; +wire b_data_valid_ping_delay6_29; +wire b_data_valid_ping_delay7_29; +wire b_data_valid_ping_delay8_29; +wire b_data_valid_ping_delay9_29; +wire b_data_valid_ping_delay10_29; +wire b_data_valid_ping_delay11_29; +wire b_data_valid_ping_delay12_29; +wire b_data_valid_ping_delay13_29; +wire b_data_valid_ping_delay14_29; +wire b_data_valid_ping_delay15_29; +wire b_data_valid_ping_delay16_29; +wire b_data_valid_ping_delay17_29; +wire b_data_valid_ping_delay18_29; +wire b_data_valid_ping_delay19_29; +wire b_data_valid_ping_delay20_29; +wire b_data_valid_ping_delay21_29; +wire b_data_valid_ping_delay22_29; +wire b_data_valid_ping_delay23_29; +wire b_data_valid_ping_delay24_29; +wire b_data_valid_ping_delay25_29; +wire b_data_valid_ping_delay26_29; +wire b_data_valid_ping_delay27_29; +wire b_data_valid_ping_delay28_29; +wire b_data_valid_ping_delay29_29; +wire b_data_valid_ping_delay30_29; +wire b_data_valid_ping_delay31_29; +wire b_data_valid_ping_delay1_30; +wire b_data_valid_ping_delay2_30; +wire b_data_valid_ping_delay3_30; +wire b_data_valid_ping_delay4_30; +wire b_data_valid_ping_delay5_30; +wire b_data_valid_ping_delay6_30; +wire b_data_valid_ping_delay7_30; +wire b_data_valid_ping_delay8_30; +wire b_data_valid_ping_delay9_30; +wire b_data_valid_ping_delay10_30; +wire b_data_valid_ping_delay11_30; +wire b_data_valid_ping_delay12_30; +wire b_data_valid_ping_delay13_30; +wire b_data_valid_ping_delay14_30; +wire b_data_valid_ping_delay15_30; +wire b_data_valid_ping_delay16_30; +wire b_data_valid_ping_delay17_30; +wire b_data_valid_ping_delay18_30; +wire b_data_valid_ping_delay19_30; +wire b_data_valid_ping_delay20_30; +wire b_data_valid_ping_delay21_30; +wire b_data_valid_ping_delay22_30; +wire b_data_valid_ping_delay23_30; +wire b_data_valid_ping_delay24_30; +wire b_data_valid_ping_delay25_30; +wire b_data_valid_ping_delay26_30; +wire b_data_valid_ping_delay27_30; +wire b_data_valid_ping_delay28_30; +wire b_data_valid_ping_delay29_30; +wire b_data_valid_ping_delay30_30; +wire b_data_valid_ping_delay31_30; +wire b_data_valid_ping_delay1_31; +wire b_data_valid_ping_delay2_31; +wire b_data_valid_ping_delay3_31; +wire b_data_valid_ping_delay4_31; +wire b_data_valid_ping_delay5_31; +wire b_data_valid_ping_delay6_31; +wire b_data_valid_ping_delay7_31; +wire b_data_valid_ping_delay8_31; +wire b_data_valid_ping_delay9_31; +wire b_data_valid_ping_delay10_31; +wire b_data_valid_ping_delay11_31; +wire b_data_valid_ping_delay12_31; +wire b_data_valid_ping_delay13_31; +wire b_data_valid_ping_delay14_31; +wire b_data_valid_ping_delay15_31; +wire b_data_valid_ping_delay16_31; +wire b_data_valid_ping_delay17_31; +wire b_data_valid_ping_delay18_31; +wire b_data_valid_ping_delay19_31; +wire b_data_valid_ping_delay20_31; +wire b_data_valid_ping_delay21_31; +wire b_data_valid_ping_delay22_31; +wire b_data_valid_ping_delay23_31; +wire b_data_valid_ping_delay24_31; +wire b_data_valid_ping_delay25_31; +wire b_data_valid_ping_delay26_31; +wire b_data_valid_ping_delay27_31; +wire b_data_valid_ping_delay28_31; +wire b_data_valid_ping_delay29_31; +wire b_data_valid_ping_delay30_31; +wire b_data_valid_ping_delay31_31; + +always @ (posedge clk) begin + b_data_valid_ping_delay0_1 <= b_data_valid_ping; + b_data_valid_ping_delay0_2 <= b_data_valid_ping_delay0_1; + b_data_valid_ping_delay0_3 <= b_data_valid_ping_delay0_2; + b_data_valid_ping_delay0_4 <= b_data_valid_ping_delay0_3; + b_data_valid_ping_delay0_5 <= b_data_valid_ping_delay0_4; + b_data_valid_ping_delay0_6 <= b_data_valid_ping_delay0_5; + b_data_valid_ping_delay0_7 <= b_data_valid_ping_delay0_6; + b_data_valid_ping_delay0_8 <= b_data_valid_ping_delay0_7; + b_data_valid_ping_delay0_9 <= b_data_valid_ping_delay0_8; + b_data_valid_ping_delay0_10 <= b_data_valid_ping_delay0_9; + b_data_valid_ping_delay0_11 <= b_data_valid_ping_delay0_10; + b_data_valid_ping_delay0_12 <= b_data_valid_ping_delay0_11; + b_data_valid_ping_delay0_13 <= b_data_valid_ping_delay0_12; + b_data_valid_ping_delay0_14 <= b_data_valid_ping_delay0_13; + b_data_valid_ping_delay0_15 <= b_data_valid_ping_delay0_14; + b_data_valid_ping_delay0_16 <= b_data_valid_ping_delay0_15; + b_data_valid_ping_delay0_17 <= b_data_valid_ping_delay0_16; + b_data_valid_ping_delay0_18 <= b_data_valid_ping_delay0_17; + b_data_valid_ping_delay0_19 <= b_data_valid_ping_delay0_18; + b_data_valid_ping_delay0_20 <= b_data_valid_ping_delay0_19; + b_data_valid_ping_delay0_21 <= b_data_valid_ping_delay0_20; + b_data_valid_ping_delay0_22 <= b_data_valid_ping_delay0_21; + b_data_valid_ping_delay0_23 <= b_data_valid_ping_delay0_22; + b_data_valid_ping_delay0_24 <= b_data_valid_ping_delay0_23; + b_data_valid_ping_delay0_25 <= b_data_valid_ping_delay0_24; + b_data_valid_ping_delay0_26 <= b_data_valid_ping_delay0_25; + b_data_valid_ping_delay0_27 <= b_data_valid_ping_delay0_26; + b_data_valid_ping_delay0_28 <= b_data_valid_ping_delay0_27; + b_data_valid_ping_delay0_29 <= b_data_valid_ping_delay0_28; + b_data_valid_ping_delay0_30 <= b_data_valid_ping_delay0_29; + b_data_valid_ping_delay0_31 <= b_data_valid_ping_delay0_30; + b_data_valid_ping_delay0_32 <= b_data_valid_ping_delay0_31; + b_data_valid_ping_delay0_33 <= b_data_valid_ping_delay0_32; + b_data_valid_ping_delay0_34 <= b_data_valid_ping_delay0_33; + b_data_valid_ping_delay0_35 <= b_data_valid_ping_delay0_34; + b_data_valid_ping_delay0_36 <= b_data_valid_ping_delay0_35; + b_data_valid_ping_delay0_37 <= b_data_valid_ping_delay0_36; + b_data_valid_ping_delay0_38 <= b_data_valid_ping_delay0_37; + b_data_valid_ping_delay0_39 <= b_data_valid_ping_delay0_38; + b_data_valid_ping_delay0_40 <= b_data_valid_ping_delay0_39; + b_data_valid_ping_delay0_41 <= b_data_valid_ping_delay0_40; + b_data_valid_ping_delay0_42 <= b_data_valid_ping_delay0_41; + b_data_valid_ping_delay0_43 <= b_data_valid_ping_delay0_42; + b_data_valid_ping_delay0_44 <= b_data_valid_ping_delay0_43; + b_data_valid_ping_delay0_45 <= b_data_valid_ping_delay0_44; + b_data_valid_ping_delay0_46 <= b_data_valid_ping_delay0_45; + b_data_valid_ping_delay0_47 <= b_data_valid_ping_delay0_46; + b_data_valid_ping_delay0_48 <= b_data_valid_ping_delay0_47; + b_data_valid_ping_delay0_49 <= b_data_valid_ping_delay0_48; + b_data_valid_ping_delay0_50 <= b_data_valid_ping_delay0_49; + b_data_valid_ping_delay0_51 <= b_data_valid_ping_delay0_50; + b_data_valid_ping_delay0_52 <= b_data_valid_ping_delay0_51; + b_data_valid_ping_delay0_53 <= b_data_valid_ping_delay0_52; + b_data_valid_ping_delay0_54 <= b_data_valid_ping_delay0_53; + b_data_valid_ping_delay0_55 <= b_data_valid_ping_delay0_54; + b_data_valid_ping_delay0_56 <= b_data_valid_ping_delay0_55; + b_data_valid_ping_delay0_57 <= b_data_valid_ping_delay0_56; + b_data_valid_ping_delay0_58 <= b_data_valid_ping_delay0_57; + b_data_valid_ping_delay0_59 <= b_data_valid_ping_delay0_58; + b_data_valid_ping_delay0_60 <= b_data_valid_ping_delay0_59; + b_data_valid_ping_delay0_61 <= b_data_valid_ping_delay0_60; + b_data_valid_ping_delay0_62 <= b_data_valid_ping_delay0_61; +end + +assign b_data_valid_ping_delay1_0 = b_data_valid_ping & b_data_valid_ping_delay0_1; +assign b_data_valid_ping_delay2_0 = b_data_valid_ping & b_data_valid_ping_delay0_2; +assign b_data_valid_ping_delay3_0 = b_data_valid_ping & b_data_valid_ping_delay0_3; +assign b_data_valid_ping_delay4_0 = b_data_valid_ping & b_data_valid_ping_delay0_4; +assign b_data_valid_ping_delay5_0 = b_data_valid_ping & b_data_valid_ping_delay0_5; +assign b_data_valid_ping_delay6_0 = b_data_valid_ping & b_data_valid_ping_delay0_6; +assign b_data_valid_ping_delay7_0 = b_data_valid_ping & b_data_valid_ping_delay0_7; +assign b_data_valid_ping_delay8_0 = b_data_valid_ping & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay9_0 = b_data_valid_ping & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay10_0 = b_data_valid_ping & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay11_0 = b_data_valid_ping & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay12_0 = b_data_valid_ping & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay13_0 = b_data_valid_ping & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay14_0 = b_data_valid_ping & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay15_0 = b_data_valid_ping & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay16_0 = b_data_valid_ping & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay17_0 = b_data_valid_ping & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay18_0 = b_data_valid_ping & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay19_0 = b_data_valid_ping & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay20_0 = b_data_valid_ping & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay21_0 = b_data_valid_ping & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay22_0 = b_data_valid_ping & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay23_0 = b_data_valid_ping & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay24_0 = b_data_valid_ping & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay25_0 = b_data_valid_ping & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay26_0 = b_data_valid_ping & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay27_0 = b_data_valid_ping & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay28_0 = b_data_valid_ping & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay29_0 = b_data_valid_ping & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay30_0 = b_data_valid_ping & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay31_0 = b_data_valid_ping & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay1_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_2; +assign b_data_valid_ping_delay2_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_3; +assign b_data_valid_ping_delay3_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_4; +assign b_data_valid_ping_delay4_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_5; +assign b_data_valid_ping_delay5_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_6; +assign b_data_valid_ping_delay6_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_7; +assign b_data_valid_ping_delay7_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay8_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay9_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay10_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay11_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay12_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay13_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay14_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay15_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay16_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay17_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay18_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay19_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay20_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay21_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay22_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay23_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay24_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay25_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay26_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay27_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay28_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay29_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay30_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay31_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay1_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_3; +assign b_data_valid_ping_delay2_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_4; +assign b_data_valid_ping_delay3_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_5; +assign b_data_valid_ping_delay4_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_6; +assign b_data_valid_ping_delay5_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_7; +assign b_data_valid_ping_delay6_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay7_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay8_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay9_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay10_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay11_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay12_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay13_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay14_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay15_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay16_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay17_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay18_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay19_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay20_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay21_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay22_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay23_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay24_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay25_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay26_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay27_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay28_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay29_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay30_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay31_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay1_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_4; +assign b_data_valid_ping_delay2_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_5; +assign b_data_valid_ping_delay3_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_6; +assign b_data_valid_ping_delay4_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_7; +assign b_data_valid_ping_delay5_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay6_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay7_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay8_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay9_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay10_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay11_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay12_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay13_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay14_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay15_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay16_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay17_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay18_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay19_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay20_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay21_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay22_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay23_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay24_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay25_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay26_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay27_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay28_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay29_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay30_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay31_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay1_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_5; +assign b_data_valid_ping_delay2_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_6; +assign b_data_valid_ping_delay3_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_7; +assign b_data_valid_ping_delay4_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay5_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay6_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay7_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay8_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay9_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay10_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay11_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay12_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay13_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay14_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay15_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay16_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay17_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay18_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay19_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay20_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay21_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay22_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay23_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay24_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay25_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay26_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay27_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay28_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay29_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay30_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay31_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay1_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_6; +assign b_data_valid_ping_delay2_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_7; +assign b_data_valid_ping_delay3_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay4_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay5_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay6_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay7_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay8_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay9_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay10_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay11_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay12_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay13_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay14_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay15_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay16_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay17_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay18_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay19_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay20_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay21_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay22_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay23_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay24_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay25_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay26_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay27_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay28_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay29_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay30_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay31_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay1_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_7; +assign b_data_valid_ping_delay2_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay3_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay4_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay5_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay6_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay7_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay8_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay9_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay10_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay11_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay12_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay13_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay14_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay15_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay16_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay17_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay18_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay19_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay20_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay21_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay22_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay23_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay24_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay25_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay26_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay27_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay28_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay29_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay30_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay31_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay1_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay2_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay3_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay4_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay5_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay6_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay7_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay8_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay9_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay10_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay11_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay12_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay13_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay14_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay15_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay16_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay17_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay18_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay19_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay20_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay21_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay22_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay23_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay24_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay25_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay26_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay27_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay28_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay29_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay30_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay31_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay1_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay2_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay3_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay4_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay5_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay6_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay7_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay8_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay9_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay10_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay11_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay12_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay13_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay14_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay15_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay16_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay17_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay18_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay19_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay20_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay21_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay22_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay23_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay24_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay25_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay26_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay27_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay28_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay29_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay30_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay31_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay1_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay2_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay3_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay4_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay5_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay6_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay7_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay8_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay9_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay10_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay11_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay12_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay13_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay14_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay15_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay16_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay17_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay18_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay19_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay20_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay21_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay22_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay23_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay24_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay25_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay26_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay27_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay28_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay29_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay30_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay31_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay1_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay2_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay3_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay4_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay5_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay6_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay7_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay8_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay9_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay10_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay11_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay12_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay13_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay14_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay15_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay16_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay17_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay18_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay19_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay20_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay21_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay22_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay23_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay24_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay25_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay26_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay27_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay28_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay29_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay30_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay31_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay1_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay2_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay3_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay4_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay5_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay6_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay7_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay8_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay9_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay10_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay11_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay12_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay13_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay14_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay15_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay16_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay17_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay18_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay19_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay20_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay21_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay22_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay23_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay24_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay25_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay26_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay27_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay28_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay29_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay30_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay31_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay1_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay2_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay3_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay4_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay5_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay6_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay7_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay8_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay9_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay10_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay11_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay12_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay13_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay14_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay15_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay16_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay17_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay18_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay19_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay20_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay21_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay22_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay23_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay24_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay25_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay26_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay27_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay28_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay29_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay30_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay31_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay1_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay2_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay3_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay4_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay5_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay6_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay7_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay8_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay9_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay10_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay11_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay12_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay13_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay14_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay15_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay16_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay17_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay18_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay19_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay20_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay21_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay22_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay23_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay24_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay25_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay26_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay27_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay28_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay29_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay30_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay31_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay1_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay2_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay3_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay4_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay5_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay6_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay7_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay8_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay9_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay10_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay11_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay12_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay13_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay14_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay15_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay16_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay17_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay18_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay19_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay20_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay21_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay22_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay23_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay24_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay25_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay26_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay27_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay28_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay29_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay30_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay31_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay1_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay2_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay3_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay4_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay5_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay6_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay7_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay8_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay9_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay10_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay11_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay12_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay13_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay14_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay15_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay16_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay17_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay18_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay19_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay20_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay21_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay22_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay23_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay24_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay25_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay26_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay27_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay28_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay29_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay30_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay31_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay1_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay2_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay3_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay4_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay5_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay6_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay7_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay8_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay9_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay10_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay11_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay12_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay13_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay14_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay15_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay16_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay17_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay18_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay19_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay20_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay21_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay22_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay23_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay24_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay25_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay26_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay27_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay28_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay29_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay30_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay31_16 = b_data_valid_ping_delay0_16 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay1_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay2_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay3_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay4_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay5_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay6_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay7_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay8_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay9_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay10_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay11_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay12_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay13_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay14_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay15_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay16_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay17_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay18_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay19_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay20_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay21_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay22_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay23_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay24_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay25_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay26_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay27_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay28_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay29_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay30_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay31_17 = b_data_valid_ping_delay0_17 & b_data_valid_ping_delay0_48; +assign b_data_valid_ping_delay1_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay2_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay3_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay4_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay5_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay6_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay7_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay8_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay9_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay10_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay11_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay12_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay13_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay14_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay15_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay16_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay17_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay18_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay19_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay20_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay21_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay22_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay23_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay24_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay25_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay26_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay27_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay28_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay29_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay30_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_48; +assign b_data_valid_ping_delay31_18 = b_data_valid_ping_delay0_18 & b_data_valid_ping_delay0_49; +assign b_data_valid_ping_delay1_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay2_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay3_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay4_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay5_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay6_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay7_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay8_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay9_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay10_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay11_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay12_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay13_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay14_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay15_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay16_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay17_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay18_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay19_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay20_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay21_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay22_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay23_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay24_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay25_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay26_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay27_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay28_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay29_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_48; +assign b_data_valid_ping_delay30_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_49; +assign b_data_valid_ping_delay31_19 = b_data_valid_ping_delay0_19 & b_data_valid_ping_delay0_50; +assign b_data_valid_ping_delay1_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay2_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay3_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay4_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay5_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay6_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay7_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay8_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay9_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay10_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay11_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay12_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay13_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay14_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay15_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay16_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay17_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay18_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay19_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay20_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay21_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay22_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay23_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay24_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay25_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay26_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay27_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay28_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_48; +assign b_data_valid_ping_delay29_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_49; +assign b_data_valid_ping_delay30_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_50; +assign b_data_valid_ping_delay31_20 = b_data_valid_ping_delay0_20 & b_data_valid_ping_delay0_51; +assign b_data_valid_ping_delay1_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay2_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay3_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay4_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay5_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay6_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay7_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay8_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay9_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay10_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay11_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay12_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay13_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay14_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay15_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay16_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay17_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay18_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay19_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay20_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay21_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay22_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay23_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay24_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay25_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay26_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay27_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_48; +assign b_data_valid_ping_delay28_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_49; +assign b_data_valid_ping_delay29_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_50; +assign b_data_valid_ping_delay30_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_51; +assign b_data_valid_ping_delay31_21 = b_data_valid_ping_delay0_21 & b_data_valid_ping_delay0_52; +assign b_data_valid_ping_delay1_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay2_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay3_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay4_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay5_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay6_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay7_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay8_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay9_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay10_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay11_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay12_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay13_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay14_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay15_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay16_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay17_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay18_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay19_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay20_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay21_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay22_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay23_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay24_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay25_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay26_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_48; +assign b_data_valid_ping_delay27_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_49; +assign b_data_valid_ping_delay28_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_50; +assign b_data_valid_ping_delay29_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_51; +assign b_data_valid_ping_delay30_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_52; +assign b_data_valid_ping_delay31_22 = b_data_valid_ping_delay0_22 & b_data_valid_ping_delay0_53; +assign b_data_valid_ping_delay1_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay2_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay3_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay4_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay5_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay6_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay7_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay8_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay9_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay10_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay11_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay12_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay13_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay14_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay15_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay16_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay17_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay18_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay19_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay20_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay21_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay22_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay23_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay24_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay25_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_48; +assign b_data_valid_ping_delay26_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_49; +assign b_data_valid_ping_delay27_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_50; +assign b_data_valid_ping_delay28_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_51; +assign b_data_valid_ping_delay29_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_52; +assign b_data_valid_ping_delay30_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_53; +assign b_data_valid_ping_delay31_23 = b_data_valid_ping_delay0_23 & b_data_valid_ping_delay0_54; +assign b_data_valid_ping_delay1_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay2_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay3_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay4_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay5_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay6_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay7_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay8_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay9_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay10_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay11_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay12_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay13_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay14_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay15_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay16_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay17_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay18_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay19_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay20_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay21_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay22_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay23_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay24_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_48; +assign b_data_valid_ping_delay25_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_49; +assign b_data_valid_ping_delay26_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_50; +assign b_data_valid_ping_delay27_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_51; +assign b_data_valid_ping_delay28_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_52; +assign b_data_valid_ping_delay29_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_53; +assign b_data_valid_ping_delay30_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_54; +assign b_data_valid_ping_delay31_24 = b_data_valid_ping_delay0_24 & b_data_valid_ping_delay0_55; +assign b_data_valid_ping_delay1_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay2_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay3_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay4_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay5_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay6_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay7_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay8_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay9_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay10_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay11_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay12_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay13_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay14_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay15_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay16_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay17_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay18_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay19_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay20_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay21_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay22_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay23_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_48; +assign b_data_valid_ping_delay24_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_49; +assign b_data_valid_ping_delay25_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_50; +assign b_data_valid_ping_delay26_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_51; +assign b_data_valid_ping_delay27_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_52; +assign b_data_valid_ping_delay28_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_53; +assign b_data_valid_ping_delay29_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_54; +assign b_data_valid_ping_delay30_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_55; +assign b_data_valid_ping_delay31_25 = b_data_valid_ping_delay0_25 & b_data_valid_ping_delay0_56; +assign b_data_valid_ping_delay1_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay2_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay3_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay4_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay5_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay6_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay7_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay8_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay9_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay10_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay11_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay12_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay13_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay14_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay15_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay16_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay17_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay18_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay19_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay20_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay21_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay22_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_48; +assign b_data_valid_ping_delay23_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_49; +assign b_data_valid_ping_delay24_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_50; +assign b_data_valid_ping_delay25_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_51; +assign b_data_valid_ping_delay26_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_52; +assign b_data_valid_ping_delay27_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_53; +assign b_data_valid_ping_delay28_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_54; +assign b_data_valid_ping_delay29_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_55; +assign b_data_valid_ping_delay30_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_56; +assign b_data_valid_ping_delay31_26 = b_data_valid_ping_delay0_26 & b_data_valid_ping_delay0_57; +assign b_data_valid_ping_delay1_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay2_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay3_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay4_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay5_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay6_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay7_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay8_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay9_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay10_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay11_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay12_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay13_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay14_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay15_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay16_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay17_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay18_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay19_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay20_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay21_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_48; +assign b_data_valid_ping_delay22_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_49; +assign b_data_valid_ping_delay23_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_50; +assign b_data_valid_ping_delay24_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_51; +assign b_data_valid_ping_delay25_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_52; +assign b_data_valid_ping_delay26_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_53; +assign b_data_valid_ping_delay27_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_54; +assign b_data_valid_ping_delay28_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_55; +assign b_data_valid_ping_delay29_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_56; +assign b_data_valid_ping_delay30_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_57; +assign b_data_valid_ping_delay31_27 = b_data_valid_ping_delay0_27 & b_data_valid_ping_delay0_58; +assign b_data_valid_ping_delay1_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay2_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay3_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay4_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay5_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay6_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay7_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay8_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay9_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay10_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay11_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay12_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay13_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay14_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay15_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay16_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay17_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay18_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay19_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay20_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_48; +assign b_data_valid_ping_delay21_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_49; +assign b_data_valid_ping_delay22_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_50; +assign b_data_valid_ping_delay23_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_51; +assign b_data_valid_ping_delay24_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_52; +assign b_data_valid_ping_delay25_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_53; +assign b_data_valid_ping_delay26_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_54; +assign b_data_valid_ping_delay27_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_55; +assign b_data_valid_ping_delay28_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_56; +assign b_data_valid_ping_delay29_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_57; +assign b_data_valid_ping_delay30_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_58; +assign b_data_valid_ping_delay31_28 = b_data_valid_ping_delay0_28 & b_data_valid_ping_delay0_59; +assign b_data_valid_ping_delay1_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_30; +assign b_data_valid_ping_delay2_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay3_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay4_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay5_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay6_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay7_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay8_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay9_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay10_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay11_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay12_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay13_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay14_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay15_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay16_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay17_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay18_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay19_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_48; +assign b_data_valid_ping_delay20_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_49; +assign b_data_valid_ping_delay21_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_50; +assign b_data_valid_ping_delay22_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_51; +assign b_data_valid_ping_delay23_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_52; +assign b_data_valid_ping_delay24_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_53; +assign b_data_valid_ping_delay25_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_54; +assign b_data_valid_ping_delay26_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_55; +assign b_data_valid_ping_delay27_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_56; +assign b_data_valid_ping_delay28_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_57; +assign b_data_valid_ping_delay29_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_58; +assign b_data_valid_ping_delay30_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_59; +assign b_data_valid_ping_delay31_29 = b_data_valid_ping_delay0_29 & b_data_valid_ping_delay0_60; +assign b_data_valid_ping_delay1_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_31; +assign b_data_valid_ping_delay2_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay3_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay4_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay5_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay6_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay7_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay8_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay9_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay10_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay11_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay12_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay13_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay14_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay15_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay16_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay17_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay18_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_48; +assign b_data_valid_ping_delay19_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_49; +assign b_data_valid_ping_delay20_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_50; +assign b_data_valid_ping_delay21_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_51; +assign b_data_valid_ping_delay22_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_52; +assign b_data_valid_ping_delay23_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_53; +assign b_data_valid_ping_delay24_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_54; +assign b_data_valid_ping_delay25_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_55; +assign b_data_valid_ping_delay26_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_56; +assign b_data_valid_ping_delay27_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_57; +assign b_data_valid_ping_delay28_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_58; +assign b_data_valid_ping_delay29_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_59; +assign b_data_valid_ping_delay30_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_60; +assign b_data_valid_ping_delay31_30 = b_data_valid_ping_delay0_30 & b_data_valid_ping_delay0_61; +assign b_data_valid_ping_delay1_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_32; +assign b_data_valid_ping_delay2_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_33; +assign b_data_valid_ping_delay3_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_34; +assign b_data_valid_ping_delay4_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_35; +assign b_data_valid_ping_delay5_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_36; +assign b_data_valid_ping_delay6_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_37; +assign b_data_valid_ping_delay7_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_38; +assign b_data_valid_ping_delay8_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_39; +assign b_data_valid_ping_delay9_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_40; +assign b_data_valid_ping_delay10_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_41; +assign b_data_valid_ping_delay11_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_42; +assign b_data_valid_ping_delay12_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_43; +assign b_data_valid_ping_delay13_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_44; +assign b_data_valid_ping_delay14_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_45; +assign b_data_valid_ping_delay15_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_46; +assign b_data_valid_ping_delay16_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_47; +assign b_data_valid_ping_delay17_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_48; +assign b_data_valid_ping_delay18_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_49; +assign b_data_valid_ping_delay19_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_50; +assign b_data_valid_ping_delay20_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_51; +assign b_data_valid_ping_delay21_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_52; +assign b_data_valid_ping_delay22_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_53; +assign b_data_valid_ping_delay23_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_54; +assign b_data_valid_ping_delay24_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_55; +assign b_data_valid_ping_delay25_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_56; +assign b_data_valid_ping_delay26_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_57; +assign b_data_valid_ping_delay27_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_58; +assign b_data_valid_ping_delay28_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_59; +assign b_data_valid_ping_delay29_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_60; +assign b_data_valid_ping_delay30_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_61; +assign b_data_valid_ping_delay31_31 = b_data_valid_ping_delay0_31 & b_data_valid_ping_delay0_62; + +wire [`DWIDTH-1:0] in_a_0_0_NC, in_a_0_1_NC, in_a_0_2_NC, in_a_0_3_NC, in_a_0_4_NC, in_a_0_5_NC, in_a_0_6_NC, in_a_0_7_NC, in_a_0_8_NC, in_a_0_9_NC, in_a_0_10_NC, in_a_0_11_NC, in_a_0_12_NC, in_a_0_13_NC, in_a_0_14_NC, in_a_0_15_NC, in_a_0_16_NC, in_a_0_17_NC, in_a_0_18_NC, in_a_0_19_NC, in_a_0_20_NC, in_a_0_21_NC, in_a_0_22_NC, in_a_0_23_NC, in_a_0_24_NC, in_a_0_25_NC, in_a_0_26_NC, in_a_0_27_NC, in_a_0_28_NC, in_a_0_29_NC, in_a_0_30_NC, in_a_0_31_NC, in_a_1_0_NC, in_a_1_1_NC, in_a_1_2_NC, in_a_1_3_NC, in_a_1_4_NC, in_a_1_5_NC, in_a_1_6_NC, in_a_1_7_NC, in_a_1_8_NC, in_a_1_9_NC, in_a_1_10_NC, in_a_1_11_NC, in_a_1_12_NC, in_a_1_13_NC, in_a_1_14_NC, in_a_1_15_NC, in_a_1_16_NC, in_a_1_17_NC, in_a_1_18_NC, in_a_1_19_NC, in_a_1_20_NC, in_a_1_21_NC, in_a_1_22_NC, in_a_1_23_NC, in_a_1_24_NC, in_a_1_25_NC, in_a_1_26_NC, in_a_1_27_NC, in_a_1_28_NC, in_a_1_29_NC, in_a_1_30_NC, in_a_1_31_NC, in_a_2_0_NC, in_a_2_1_NC, in_a_2_2_NC, in_a_2_3_NC, in_a_2_4_NC, in_a_2_5_NC, in_a_2_6_NC, in_a_2_7_NC, in_a_2_8_NC, in_a_2_9_NC, in_a_2_10_NC, in_a_2_11_NC, in_a_2_12_NC, in_a_2_13_NC, in_a_2_14_NC, in_a_2_15_NC, in_a_2_16_NC, in_a_2_17_NC, in_a_2_18_NC, in_a_2_19_NC, in_a_2_20_NC, in_a_2_21_NC, in_a_2_22_NC, in_a_2_23_NC, in_a_2_24_NC, in_a_2_25_NC, in_a_2_26_NC, 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in_a_chain_31_6_NC, in_a_chain_31_7_NC, in_a_chain_31_8_NC, in_a_chain_31_9_NC, in_a_chain_31_10_NC, in_a_chain_31_11_NC, in_a_chain_31_12_NC, in_a_chain_31_13_NC, in_a_chain_31_14_NC, in_a_chain_31_15_NC, in_a_chain_31_16_NC, in_a_chain_31_17_NC, in_a_chain_31_18_NC, in_a_chain_31_19_NC, in_a_chain_31_20_NC, in_a_chain_31_21_NC, in_a_chain_31_22_NC, in_a_chain_31_23_NC, in_a_chain_31_24_NC, in_a_chain_31_25_NC, in_a_chain_31_26_NC, in_a_chain_31_27_NC, in_a_chain_31_28_NC, in_a_chain_31_29_NC, in_a_chain_31_30_NC, in_a_chain_31_31_NC; + +wire [`DWIDTH-1:0] out_a_0_0_NC, out_a_0_1_NC, out_a_0_2_NC, out_a_0_3_NC, out_a_0_4_NC, out_a_0_5_NC, out_a_0_6_NC, out_a_0_7_NC, out_a_0_8_NC, out_a_0_9_NC, out_a_0_10_NC, out_a_0_11_NC, out_a_0_12_NC, out_a_0_13_NC, out_a_0_14_NC, out_a_0_15_NC, out_a_0_16_NC, out_a_0_17_NC, out_a_0_18_NC, out_a_0_19_NC, out_a_0_20_NC, out_a_0_21_NC, out_a_0_22_NC, out_a_0_23_NC, out_a_0_24_NC, out_a_0_25_NC, out_a_0_26_NC, out_a_0_27_NC, out_a_0_28_NC, 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out_a_3_1_NC, out_a_3_2_NC, out_a_3_3_NC, out_a_3_4_NC, out_a_3_5_NC, out_a_3_6_NC, out_a_3_7_NC, out_a_3_8_NC, out_a_3_9_NC, out_a_3_10_NC, out_a_3_11_NC, out_a_3_12_NC, out_a_3_13_NC, out_a_3_14_NC, out_a_3_15_NC, out_a_3_16_NC, out_a_3_17_NC, out_a_3_18_NC, out_a_3_19_NC, out_a_3_20_NC, out_a_3_21_NC, out_a_3_22_NC, out_a_3_23_NC, out_a_3_24_NC, out_a_3_25_NC, out_a_3_26_NC, out_a_3_27_NC, out_a_3_28_NC, out_a_3_29_NC, out_a_3_30_NC, out_a_3_31_NC, out_a_4_0_NC, out_a_4_1_NC, out_a_4_2_NC, out_a_4_3_NC, out_a_4_4_NC, out_a_4_5_NC, out_a_4_6_NC, out_a_4_7_NC, out_a_4_8_NC, out_a_4_9_NC, out_a_4_10_NC, out_a_4_11_NC, out_a_4_12_NC, out_a_4_13_NC, out_a_4_14_NC, out_a_4_15_NC, out_a_4_16_NC, out_a_4_17_NC, out_a_4_18_NC, out_a_4_19_NC, out_a_4_20_NC, out_a_4_21_NC, out_a_4_22_NC, out_a_4_23_NC, out_a_4_24_NC, out_a_4_25_NC, out_a_4_26_NC, out_a_4_27_NC, out_a_4_28_NC, out_a_4_29_NC, out_a_4_30_NC, out_a_4_31_NC, out_a_5_0_NC, out_a_5_1_NC, out_a_5_2_NC, out_a_5_3_NC, out_a_5_4_NC, out_a_5_5_NC, out_a_5_6_NC, out_a_5_7_NC, out_a_5_8_NC, out_a_5_9_NC, out_a_5_10_NC, out_a_5_11_NC, out_a_5_12_NC, out_a_5_13_NC, out_a_5_14_NC, out_a_5_15_NC, out_a_5_16_NC, out_a_5_17_NC, out_a_5_18_NC, out_a_5_19_NC, out_a_5_20_NC, out_a_5_21_NC, out_a_5_22_NC, out_a_5_23_NC, out_a_5_24_NC, out_a_5_25_NC, out_a_5_26_NC, out_a_5_27_NC, out_a_5_28_NC, out_a_5_29_NC, out_a_5_30_NC, out_a_5_31_NC, out_a_6_0_NC, out_a_6_1_NC, out_a_6_2_NC, out_a_6_3_NC, out_a_6_4_NC, out_a_6_5_NC, out_a_6_6_NC, out_a_6_7_NC, out_a_6_8_NC, out_a_6_9_NC, out_a_6_10_NC, out_a_6_11_NC, out_a_6_12_NC, out_a_6_13_NC, out_a_6_14_NC, out_a_6_15_NC, out_a_6_16_NC, out_a_6_17_NC, out_a_6_18_NC, out_a_6_19_NC, out_a_6_20_NC, out_a_6_21_NC, out_a_6_22_NC, out_a_6_23_NC, out_a_6_24_NC, out_a_6_25_NC, out_a_6_26_NC, out_a_6_27_NC, out_a_6_28_NC, out_a_6_29_NC, out_a_6_30_NC, out_a_6_31_NC, out_a_7_0_NC, out_a_7_1_NC, out_a_7_2_NC, out_a_7_3_NC, out_a_7_4_NC, out_a_7_5_NC, out_a_7_6_NC, out_a_7_7_NC, out_a_7_8_NC, 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out_a_15_12_NC, out_a_15_13_NC, out_a_15_14_NC, out_a_15_15_NC, out_a_15_16_NC, out_a_15_17_NC, out_a_15_18_NC, out_a_15_19_NC, out_a_15_20_NC, out_a_15_21_NC, out_a_15_22_NC, out_a_15_23_NC, out_a_15_24_NC, out_a_15_25_NC, out_a_15_26_NC, out_a_15_27_NC, out_a_15_28_NC, out_a_15_29_NC, out_a_15_30_NC, out_a_15_31_NC, out_a_16_0_NC, out_a_16_1_NC, out_a_16_2_NC, out_a_16_3_NC, out_a_16_4_NC, out_a_16_5_NC, out_a_16_6_NC, out_a_16_7_NC, out_a_16_8_NC, out_a_16_9_NC, out_a_16_10_NC, out_a_16_11_NC, out_a_16_12_NC, out_a_16_13_NC, out_a_16_14_NC, out_a_16_15_NC, out_a_16_16_NC, out_a_16_17_NC, out_a_16_18_NC, out_a_16_19_NC, out_a_16_20_NC, out_a_16_21_NC, out_a_16_22_NC, out_a_16_23_NC, out_a_16_24_NC, out_a_16_25_NC, out_a_16_26_NC, out_a_16_27_NC, out_a_16_28_NC, out_a_16_29_NC, out_a_16_30_NC, out_a_16_31_NC, out_a_17_0_NC, out_a_17_1_NC, out_a_17_2_NC, out_a_17_3_NC, out_a_17_4_NC, out_a_17_5_NC, out_a_17_6_NC, out_a_17_7_NC, out_a_17_8_NC, out_a_17_9_NC, out_a_17_10_NC, out_a_17_11_NC, out_a_17_12_NC, out_a_17_13_NC, out_a_17_14_NC, out_a_17_15_NC, out_a_17_16_NC, out_a_17_17_NC, out_a_17_18_NC, out_a_17_19_NC, out_a_17_20_NC, out_a_17_21_NC, out_a_17_22_NC, out_a_17_23_NC, out_a_17_24_NC, out_a_17_25_NC, out_a_17_26_NC, out_a_17_27_NC, out_a_17_28_NC, out_a_17_29_NC, out_a_17_30_NC, out_a_17_31_NC, out_a_18_0_NC, out_a_18_1_NC, out_a_18_2_NC, out_a_18_3_NC, out_a_18_4_NC, out_a_18_5_NC, out_a_18_6_NC, out_a_18_7_NC, out_a_18_8_NC, out_a_18_9_NC, out_a_18_10_NC, out_a_18_11_NC, out_a_18_12_NC, out_a_18_13_NC, out_a_18_14_NC, out_a_18_15_NC, out_a_18_16_NC, out_a_18_17_NC, out_a_18_18_NC, out_a_18_19_NC, out_a_18_20_NC, out_a_18_21_NC, out_a_18_22_NC, out_a_18_23_NC, out_a_18_24_NC, out_a_18_25_NC, out_a_18_26_NC, out_a_18_27_NC, out_a_18_28_NC, out_a_18_29_NC, out_a_18_30_NC, out_a_18_31_NC, out_a_19_0_NC, out_a_19_1_NC, out_a_19_2_NC, out_a_19_3_NC, out_a_19_4_NC, out_a_19_5_NC, out_a_19_6_NC, out_a_19_7_NC, out_a_19_8_NC, out_a_19_9_NC, out_a_19_10_NC, out_a_19_11_NC, out_a_19_12_NC, out_a_19_13_NC, out_a_19_14_NC, out_a_19_15_NC, out_a_19_16_NC, out_a_19_17_NC, out_a_19_18_NC, out_a_19_19_NC, out_a_19_20_NC, out_a_19_21_NC, out_a_19_22_NC, out_a_19_23_NC, out_a_19_24_NC, out_a_19_25_NC, out_a_19_26_NC, out_a_19_27_NC, out_a_19_28_NC, out_a_19_29_NC, out_a_19_30_NC, out_a_19_31_NC, out_a_20_0_NC, out_a_20_1_NC, out_a_20_2_NC, out_a_20_3_NC, out_a_20_4_NC, out_a_20_5_NC, out_a_20_6_NC, out_a_20_7_NC, out_a_20_8_NC, out_a_20_9_NC, out_a_20_10_NC, out_a_20_11_NC, out_a_20_12_NC, out_a_20_13_NC, out_a_20_14_NC, out_a_20_15_NC, out_a_20_16_NC, out_a_20_17_NC, out_a_20_18_NC, out_a_20_19_NC, out_a_20_20_NC, out_a_20_21_NC, out_a_20_22_NC, out_a_20_23_NC, out_a_20_24_NC, out_a_20_25_NC, out_a_20_26_NC, out_a_20_27_NC, out_a_20_28_NC, out_a_20_29_NC, out_a_20_30_NC, out_a_20_31_NC, out_a_21_0_NC, out_a_21_1_NC, out_a_21_2_NC, out_a_21_3_NC, out_a_21_4_NC, out_a_21_5_NC, out_a_21_6_NC, out_a_21_7_NC, out_a_21_8_NC, out_a_21_9_NC, out_a_21_10_NC, out_a_21_11_NC, out_a_21_12_NC, out_a_21_13_NC, out_a_21_14_NC, out_a_21_15_NC, out_a_21_16_NC, out_a_21_17_NC, out_a_21_18_NC, out_a_21_19_NC, out_a_21_20_NC, out_a_21_21_NC, out_a_21_22_NC, out_a_21_23_NC, out_a_21_24_NC, out_a_21_25_NC, out_a_21_26_NC, out_a_21_27_NC, out_a_21_28_NC, out_a_21_29_NC, out_a_21_30_NC, out_a_21_31_NC, out_a_22_0_NC, out_a_22_1_NC, out_a_22_2_NC, out_a_22_3_NC, out_a_22_4_NC, out_a_22_5_NC, out_a_22_6_NC, out_a_22_7_NC, out_a_22_8_NC, out_a_22_9_NC, out_a_22_10_NC, out_a_22_11_NC, out_a_22_12_NC, out_a_22_13_NC, out_a_22_14_NC, out_a_22_15_NC, out_a_22_16_NC, out_a_22_17_NC, out_a_22_18_NC, out_a_22_19_NC, out_a_22_20_NC, out_a_22_21_NC, out_a_22_22_NC, out_a_22_23_NC, out_a_22_24_NC, out_a_22_25_NC, out_a_22_26_NC, out_a_22_27_NC, out_a_22_28_NC, out_a_22_29_NC, out_a_22_30_NC, out_a_22_31_NC, out_a_23_0_NC, out_a_23_1_NC, out_a_23_2_NC, out_a_23_3_NC, out_a_23_4_NC, out_a_23_5_NC, out_a_23_6_NC, out_a_23_7_NC, out_a_23_8_NC, out_a_23_9_NC, out_a_23_10_NC, out_a_23_11_NC, out_a_23_12_NC, out_a_23_13_NC, out_a_23_14_NC, out_a_23_15_NC, out_a_23_16_NC, out_a_23_17_NC, out_a_23_18_NC, out_a_23_19_NC, out_a_23_20_NC, out_a_23_21_NC, out_a_23_22_NC, out_a_23_23_NC, out_a_23_24_NC, out_a_23_25_NC, out_a_23_26_NC, out_a_23_27_NC, out_a_23_28_NC, out_a_23_29_NC, out_a_23_30_NC, out_a_23_31_NC, out_a_24_0_NC, out_a_24_1_NC, out_a_24_2_NC, out_a_24_3_NC, out_a_24_4_NC, out_a_24_5_NC, out_a_24_6_NC, out_a_24_7_NC, out_a_24_8_NC, out_a_24_9_NC, out_a_24_10_NC, out_a_24_11_NC, out_a_24_12_NC, out_a_24_13_NC, out_a_24_14_NC, out_a_24_15_NC, out_a_24_16_NC, out_a_24_17_NC, out_a_24_18_NC, out_a_24_19_NC, out_a_24_20_NC, out_a_24_21_NC, out_a_24_22_NC, out_a_24_23_NC, out_a_24_24_NC, out_a_24_25_NC, out_a_24_26_NC, out_a_24_27_NC, out_a_24_28_NC, out_a_24_29_NC, out_a_24_30_NC, out_a_24_31_NC, out_a_25_0_NC, out_a_25_1_NC, out_a_25_2_NC, out_a_25_3_NC, out_a_25_4_NC, out_a_25_5_NC, out_a_25_6_NC, out_a_25_7_NC, out_a_25_8_NC, out_a_25_9_NC, out_a_25_10_NC, out_a_25_11_NC, out_a_25_12_NC, out_a_25_13_NC, out_a_25_14_NC, out_a_25_15_NC, out_a_25_16_NC, out_a_25_17_NC, out_a_25_18_NC, out_a_25_19_NC, out_a_25_20_NC, out_a_25_21_NC, out_a_25_22_NC, out_a_25_23_NC, out_a_25_24_NC, out_a_25_25_NC, out_a_25_26_NC, out_a_25_27_NC, out_a_25_28_NC, out_a_25_29_NC, out_a_25_30_NC, out_a_25_31_NC, out_a_26_0_NC, out_a_26_1_NC, out_a_26_2_NC, out_a_26_3_NC, out_a_26_4_NC, out_a_26_5_NC, out_a_26_6_NC, out_a_26_7_NC, out_a_26_8_NC, out_a_26_9_NC, out_a_26_10_NC, out_a_26_11_NC, out_a_26_12_NC, out_a_26_13_NC, out_a_26_14_NC, out_a_26_15_NC, out_a_26_16_NC, out_a_26_17_NC, out_a_26_18_NC, out_a_26_19_NC, out_a_26_20_NC, out_a_26_21_NC, out_a_26_22_NC, out_a_26_23_NC, out_a_26_24_NC, out_a_26_25_NC, out_a_26_26_NC, out_a_26_27_NC, out_a_26_28_NC, out_a_26_29_NC, out_a_26_30_NC, out_a_26_31_NC, out_a_27_0_NC, out_a_27_1_NC, out_a_27_2_NC, out_a_27_3_NC, out_a_27_4_NC, out_a_27_5_NC, out_a_27_6_NC, out_a_27_7_NC, out_a_27_8_NC, out_a_27_9_NC, out_a_27_10_NC, out_a_27_11_NC, out_a_27_12_NC, out_a_27_13_NC, out_a_27_14_NC, out_a_27_15_NC, out_a_27_16_NC, out_a_27_17_NC, out_a_27_18_NC, out_a_27_19_NC, out_a_27_20_NC, out_a_27_21_NC, out_a_27_22_NC, out_a_27_23_NC, out_a_27_24_NC, out_a_27_25_NC, out_a_27_26_NC, out_a_27_27_NC, out_a_27_28_NC, out_a_27_29_NC, out_a_27_30_NC, out_a_27_31_NC, out_a_28_0_NC, out_a_28_1_NC, out_a_28_2_NC, out_a_28_3_NC, out_a_28_4_NC, out_a_28_5_NC, out_a_28_6_NC, out_a_28_7_NC, out_a_28_8_NC, out_a_28_9_NC, out_a_28_10_NC, out_a_28_11_NC, out_a_28_12_NC, out_a_28_13_NC, out_a_28_14_NC, out_a_28_15_NC, out_a_28_16_NC, out_a_28_17_NC, out_a_28_18_NC, out_a_28_19_NC, out_a_28_20_NC, out_a_28_21_NC, out_a_28_22_NC, out_a_28_23_NC, out_a_28_24_NC, out_a_28_25_NC, out_a_28_26_NC, out_a_28_27_NC, out_a_28_28_NC, out_a_28_29_NC, out_a_28_30_NC, out_a_28_31_NC, out_a_29_0_NC, out_a_29_1_NC, out_a_29_2_NC, out_a_29_3_NC, out_a_29_4_NC, out_a_29_5_NC, out_a_29_6_NC, out_a_29_7_NC, out_a_29_8_NC, out_a_29_9_NC, out_a_29_10_NC, out_a_29_11_NC, out_a_29_12_NC, out_a_29_13_NC, out_a_29_14_NC, out_a_29_15_NC, out_a_29_16_NC, out_a_29_17_NC, out_a_29_18_NC, out_a_29_19_NC, out_a_29_20_NC, out_a_29_21_NC, out_a_29_22_NC, out_a_29_23_NC, out_a_29_24_NC, out_a_29_25_NC, out_a_29_26_NC, out_a_29_27_NC, out_a_29_28_NC, out_a_29_29_NC, out_a_29_30_NC, out_a_29_31_NC, out_a_30_0_NC, out_a_30_1_NC, out_a_30_2_NC, out_a_30_3_NC, out_a_30_4_NC, out_a_30_5_NC, out_a_30_6_NC, out_a_30_7_NC, out_a_30_8_NC, out_a_30_9_NC, out_a_30_10_NC, out_a_30_11_NC, out_a_30_12_NC, out_a_30_13_NC, out_a_30_14_NC, out_a_30_15_NC, out_a_30_16_NC, out_a_30_17_NC, out_a_30_18_NC, out_a_30_19_NC, out_a_30_20_NC, out_a_30_21_NC, out_a_30_22_NC, out_a_30_23_NC, out_a_30_24_NC, out_a_30_25_NC, out_a_30_26_NC, out_a_30_27_NC, out_a_30_28_NC, out_a_30_29_NC, out_a_30_30_NC, out_a_30_31_NC, out_a_31_0_NC, out_a_31_1_NC, out_a_31_2_NC, out_a_31_3_NC, out_a_31_4_NC, out_a_31_5_NC, out_a_31_6_NC, out_a_31_7_NC, out_a_31_8_NC, out_a_31_9_NC, out_a_31_10_NC, out_a_31_11_NC, out_a_31_12_NC, out_a_31_13_NC, out_a_31_14_NC, out_a_31_15_NC, out_a_31_16_NC, out_a_31_17_NC, out_a_31_18_NC, out_a_31_19_NC, out_a_31_20_NC, out_a_31_21_NC, out_a_31_22_NC, out_a_31_23_NC, out_a_31_24_NC, out_a_31_25_NC, out_a_31_26_NC, out_a_31_27_NC, out_a_31_28_NC, out_a_31_29_NC, out_a_31_30_NC, out_a_31_31_NC; + +processing_element pe0_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel), .in_a(a0), .in_a_chain(in_a_chain_0_0_NC), .in_b(b0), .in_c(c0), .out_a(out_a_0_0_NC), .out_a_chain(a0_0to0_1), .out_b(b0_0to1_0), .out_b0(b0_0to1_0_ping), .out_b1(b0_0to1_0_pong), .out_c(matrixC0_0), .b_data_valid_ping(b_data_valid_ping), .b_data_valid_pong(b_data_valid_pong ), .mode(1'b1)); +processing_element pe0_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay1), .in_a(in_a_0_1_NC), .in_a_chain(a0_0to0_1), .in_b(b1), .in_c(c1), .out_a(out_a_0_1_NC), .out_a_chain(a0_1to0_2), .out_b(b0_1to1_1), .out_b0(b0_1to1_1_ping), .out_b1(b0_1to1_1_pong), .out_c(matrixC0_1), .b_data_valid_ping(b_data_valid_ping_delay0_1), .b_data_valid_pong(b_data_valid_pong_delay0_1), .mode(1'b0)); +processing_element pe0_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay2), .in_a(in_a_0_2_NC), .in_a_chain(a0_1to0_2), .in_b(b2), .in_c(c2), .out_a(out_a_0_2_NC), .out_a_chain(a0_2to0_3), .out_b(b0_2to1_2), .out_b0(b0_2to1_2_ping), .out_b1(b0_2to1_2_pong), .out_c(matrixC0_2), .b_data_valid_ping(b_data_valid_ping_delay0_2), .b_data_valid_pong(b_data_valid_pong_delay0_2), .mode(1'b0)); +processing_element pe0_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay3), .in_a(in_a_0_3_NC), .in_a_chain(a0_2to0_3), .in_b(b3), .in_c(c3), .out_a(out_a_0_3_NC), .out_a_chain(a0_3to0_4), .out_b(b0_3to1_3), .out_b0(b0_3to1_3_ping), .out_b1(b0_3to1_3_pong), .out_c(matrixC0_3), .b_data_valid_ping(b_data_valid_ping_delay0_3), .b_data_valid_pong(b_data_valid_pong_delay0_3), .mode(1'b0)); +processing_element pe0_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay4), .in_a(in_a_0_4_NC), .in_a_chain(a0_3to0_4), .in_b(b4), .in_c(c4), .out_a(out_a_0_4_NC), .out_a_chain(a0_4to0_5), .out_b(b0_4to1_4), .out_b0(b0_4to1_4_ping), .out_b1(b0_4to1_4_pong), .out_c(matrixC0_4), .b_data_valid_ping(b_data_valid_ping_delay0_4), .b_data_valid_pong(b_data_valid_pong_delay0_4), .mode(1'b0)); +processing_element pe0_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay5), .in_a(in_a_0_5_NC), .in_a_chain(a0_4to0_5), .in_b(b5), .in_c(c5), .out_a(out_a_0_5_NC), .out_a_chain(a0_5to0_6), .out_b(b0_5to1_5), .out_b0(b0_5to1_5_ping), .out_b1(b0_5to1_5_pong), .out_c(matrixC0_5), .b_data_valid_ping(b_data_valid_ping_delay0_5), .b_data_valid_pong(b_data_valid_pong_delay0_5), .mode(1'b0)); +processing_element pe0_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay6), .in_a(in_a_0_6_NC), .in_a_chain(a0_5to0_6), .in_b(b6), .in_c(c6), .out_a(out_a_0_6_NC), .out_a_chain(a0_6to0_7), .out_b(b0_6to1_6), .out_b0(b0_6to1_6_ping), .out_b1(b0_6to1_6_pong), .out_c(matrixC0_6), .b_data_valid_ping(b_data_valid_ping_delay0_6), .b_data_valid_pong(b_data_valid_pong_delay0_6), .mode(1'b0)); +processing_element pe0_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(in_a_0_7_NC), .in_a_chain(a0_6to0_7), .in_b(b7), .in_c(c7), .out_a(out_a_0_7_NC), .out_a_chain(a0_7to0_8), .out_b(b0_7to1_7), .out_b0(b0_7to1_7_ping), .out_b1(b0_7to1_7_pong), .out_c(matrixC0_7), .b_data_valid_ping(b_data_valid_ping_delay0_7), .b_data_valid_pong(b_data_valid_pong_delay0_7), .mode(1'b0)); +processing_element pe0_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_0_8_NC), .in_a_chain(a0_7to0_8), .in_b(b8), .in_c(c8), .out_a(out_a_0_8_NC), .out_a_chain(a0_8to0_9), .out_b(b0_8to1_8), .out_b0(b0_8to1_8_ping), .out_b1(b0_8to1_8_pong), .out_c(matrixC0_8), .b_data_valid_ping(b_data_valid_ping_delay0_8), .b_data_valid_pong(b_data_valid_pong_delay0_8), .mode(1'b0)); +processing_element pe0_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_0_9_NC), .in_a_chain(a0_8to0_9), .in_b(b9), .in_c(c9), .out_a(out_a_0_9_NC), .out_a_chain(a0_9to0_10), .out_b(b0_9to1_9), .out_b0(b0_9to1_9_ping), .out_b1(b0_9to1_9_pong), .out_c(matrixC0_9), .b_data_valid_ping(b_data_valid_ping_delay0_9), .b_data_valid_pong(b_data_valid_pong_delay0_9), .mode(1'b0)); +processing_element pe0_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_0_10_NC), .in_a_chain(a0_9to0_10), .in_b(b10), .in_c(c10), .out_a(out_a_0_10_NC), .out_a_chain(a0_10to0_11), .out_b(b0_10to1_10), .out_b0(b0_10to1_10_ping), .out_b1(b0_10to1_10_pong), .out_c(matrixC0_10), .b_data_valid_ping(b_data_valid_ping_delay0_10), .b_data_valid_pong(b_data_valid_pong_delay0_10), .mode(1'b0)); +processing_element pe0_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_0_11_NC), .in_a_chain(a0_10to0_11), .in_b(b11), .in_c(c11), .out_a(out_a_0_11_NC), .out_a_chain(a0_11to0_12), .out_b(b0_11to1_11), .out_b0(b0_11to1_11_ping), .out_b1(b0_11to1_11_pong), .out_c(matrixC0_11), .b_data_valid_ping(b_data_valid_ping_delay0_11), .b_data_valid_pong(b_data_valid_pong_delay0_11), .mode(1'b0)); +processing_element pe0_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_0_12_NC), .in_a_chain(a0_11to0_12), .in_b(b12), .in_c(c12), .out_a(out_a_0_12_NC), .out_a_chain(a0_12to0_13), .out_b(b0_12to1_12), .out_b0(b0_12to1_12_ping), .out_b1(b0_12to1_12_pong), .out_c(matrixC0_12), .b_data_valid_ping(b_data_valid_ping_delay0_12), .b_data_valid_pong(b_data_valid_pong_delay0_12), .mode(1'b0)); +processing_element pe0_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_0_13_NC), .in_a_chain(a0_12to0_13), .in_b(b13), .in_c(c13), .out_a(out_a_0_13_NC), .out_a_chain(a0_13to0_14), .out_b(b0_13to1_13), .out_b0(b0_13to1_13_ping), .out_b1(b0_13to1_13_pong), .out_c(matrixC0_13), .b_data_valid_ping(b_data_valid_ping_delay0_13), .b_data_valid_pong(b_data_valid_pong_delay0_13), .mode(1'b0)); +processing_element pe0_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_0_14_NC), .in_a_chain(a0_13to0_14), .in_b(b14), .in_c(c14), .out_a(out_a_0_14_NC), .out_a_chain(a0_14to0_15), .out_b(b0_14to1_14), .out_b0(b0_14to1_14_ping), .out_b1(b0_14to1_14_pong), .out_c(matrixC0_14), .b_data_valid_ping(b_data_valid_ping_delay0_14), .b_data_valid_pong(b_data_valid_pong_delay0_14), .mode(1'b0)); +processing_element pe0_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_0_15_NC), .in_a_chain(a0_14to0_15), .in_b(b15), .in_c(c15), .out_a(out_a_0_15_NC), .out_a_chain(a0_15to0_16), .out_b(b0_15to1_15), .out_b0(b0_15to1_15_ping), .out_b1(b0_15to1_15_pong), .out_c(matrixC0_15), .b_data_valid_ping(b_data_valid_ping_delay0_15), .b_data_valid_pong(b_data_valid_pong_delay0_15), .mode(1'b0)); +processing_element pe0_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_0_16_NC), .in_a_chain(a0_15to0_16), .in_b(b16), .in_c(c16), .out_a(out_a_0_16_NC), .out_a_chain(a0_16to0_17), .out_b(b0_16to1_16), .out_b0(b0_16to1_16_ping), .out_b1(b0_16to1_16_pong), .out_c(matrixC0_16), .b_data_valid_ping(b_data_valid_ping_delay0_16), .b_data_valid_pong(b_data_valid_pong_delay0_16), .mode(1'b0)); +processing_element pe0_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_0_17_NC), .in_a_chain(a0_16to0_17), .in_b(b17), .in_c(c17), .out_a(out_a_0_17_NC), .out_a_chain(a0_17to0_18), .out_b(b0_17to1_17), .out_b0(b0_17to1_17_ping), .out_b1(b0_17to1_17_pong), .out_c(matrixC0_17), .b_data_valid_ping(b_data_valid_ping_delay0_17), .b_data_valid_pong(b_data_valid_pong_delay0_17), .mode(1'b0)); +processing_element pe0_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_0_18_NC), .in_a_chain(a0_17to0_18), .in_b(b18), .in_c(c18), .out_a(out_a_0_18_NC), .out_a_chain(a0_18to0_19), .out_b(b0_18to1_18), .out_b0(b0_18to1_18_ping), .out_b1(b0_18to1_18_pong), .out_c(matrixC0_18), .b_data_valid_ping(b_data_valid_ping_delay0_18), .b_data_valid_pong(b_data_valid_pong_delay0_18), .mode(1'b0)); +processing_element pe0_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_0_19_NC), .in_a_chain(a0_18to0_19), .in_b(b19), .in_c(c19), .out_a(out_a_0_19_NC), .out_a_chain(a0_19to0_20), .out_b(b0_19to1_19), .out_b0(b0_19to1_19_ping), .out_b1(b0_19to1_19_pong), .out_c(matrixC0_19), .b_data_valid_ping(b_data_valid_ping_delay0_19), .b_data_valid_pong(b_data_valid_pong_delay0_19), .mode(1'b0)); +processing_element pe0_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_0_20_NC), .in_a_chain(a0_19to0_20), .in_b(b20), .in_c(c20), .out_a(out_a_0_20_NC), .out_a_chain(a0_20to0_21), .out_b(b0_20to1_20), .out_b0(b0_20to1_20_ping), .out_b1(b0_20to1_20_pong), .out_c(matrixC0_20), .b_data_valid_ping(b_data_valid_ping_delay0_20), .b_data_valid_pong(b_data_valid_pong_delay0_20), .mode(1'b0)); +processing_element pe0_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_0_21_NC), .in_a_chain(a0_20to0_21), .in_b(b21), .in_c(c21), .out_a(out_a_0_21_NC), .out_a_chain(a0_21to0_22), .out_b(b0_21to1_21), .out_b0(b0_21to1_21_ping), .out_b1(b0_21to1_21_pong), .out_c(matrixC0_21), .b_data_valid_ping(b_data_valid_ping_delay0_21), .b_data_valid_pong(b_data_valid_pong_delay0_21), .mode(1'b0)); +processing_element pe0_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_0_22_NC), .in_a_chain(a0_21to0_22), .in_b(b22), .in_c(c22), .out_a(out_a_0_22_NC), .out_a_chain(a0_22to0_23), .out_b(b0_22to1_22), .out_b0(b0_22to1_22_ping), .out_b1(b0_22to1_22_pong), .out_c(matrixC0_22), .b_data_valid_ping(b_data_valid_ping_delay0_22), .b_data_valid_pong(b_data_valid_pong_delay0_22), .mode(1'b0)); +processing_element pe0_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_0_23_NC), .in_a_chain(a0_22to0_23), .in_b(b23), .in_c(c23), .out_a(out_a_0_23_NC), .out_a_chain(a0_23to0_24), .out_b(b0_23to1_23), .out_b0(b0_23to1_23_ping), .out_b1(b0_23to1_23_pong), .out_c(matrixC0_23), .b_data_valid_ping(b_data_valid_ping_delay0_23), .b_data_valid_pong(b_data_valid_pong_delay0_23), .mode(1'b0)); +processing_element pe0_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_0_24_NC), .in_a_chain(a0_23to0_24), .in_b(b24), .in_c(c24), .out_a(out_a_0_24_NC), .out_a_chain(a0_24to0_25), .out_b(b0_24to1_24), .out_b0(b0_24to1_24_ping), .out_b1(b0_24to1_24_pong), .out_c(matrixC0_24), .b_data_valid_ping(b_data_valid_ping_delay0_24), .b_data_valid_pong(b_data_valid_pong_delay0_24), .mode(1'b0)); +processing_element pe0_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_0_25_NC), .in_a_chain(a0_24to0_25), .in_b(b25), .in_c(c25), .out_a(out_a_0_25_NC), .out_a_chain(a0_25to0_26), .out_b(b0_25to1_25), .out_b0(b0_25to1_25_ping), .out_b1(b0_25to1_25_pong), .out_c(matrixC0_25), .b_data_valid_ping(b_data_valid_ping_delay0_25), .b_data_valid_pong(b_data_valid_pong_delay0_25), .mode(1'b0)); +processing_element pe0_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_0_26_NC), .in_a_chain(a0_25to0_26), .in_b(b26), .in_c(c26), .out_a(out_a_0_26_NC), .out_a_chain(a0_26to0_27), .out_b(b0_26to1_26), .out_b0(b0_26to1_26_ping), .out_b1(b0_26to1_26_pong), .out_c(matrixC0_26), .b_data_valid_ping(b_data_valid_ping_delay0_26), .b_data_valid_pong(b_data_valid_pong_delay0_26), .mode(1'b0)); +processing_element pe0_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_0_27_NC), .in_a_chain(a0_26to0_27), .in_b(b27), .in_c(c27), .out_a(out_a_0_27_NC), .out_a_chain(a0_27to0_28), .out_b(b0_27to1_27), .out_b0(b0_27to1_27_ping), .out_b1(b0_27to1_27_pong), .out_c(matrixC0_27), .b_data_valid_ping(b_data_valid_ping_delay0_27), .b_data_valid_pong(b_data_valid_pong_delay0_27), .mode(1'b0)); +processing_element pe0_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_0_28_NC), .in_a_chain(a0_27to0_28), .in_b(b28), .in_c(c28), .out_a(out_a_0_28_NC), .out_a_chain(a0_28to0_29), .out_b(b0_28to1_28), .out_b0(b0_28to1_28_ping), .out_b1(b0_28to1_28_pong), .out_c(matrixC0_28), .b_data_valid_ping(b_data_valid_ping_delay0_28), .b_data_valid_pong(b_data_valid_pong_delay0_28), .mode(1'b0)); +processing_element pe0_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_0_29_NC), .in_a_chain(a0_28to0_29), .in_b(b29), .in_c(c29), .out_a(out_a_0_29_NC), .out_a_chain(a0_29to0_30), .out_b(b0_29to1_29), .out_b0(b0_29to1_29_ping), .out_b1(b0_29to1_29_pong), .out_c(matrixC0_29), .b_data_valid_ping(b_data_valid_ping_delay0_29), .b_data_valid_pong(b_data_valid_pong_delay0_29), .mode(1'b0)); +processing_element pe0_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_0_30_NC), .in_a_chain(a0_29to0_30), .in_b(b30), .in_c(c30), .out_a(out_a_0_30_NC), .out_a_chain(a0_30to0_31), .out_b(b0_30to1_30), .out_b0(b0_30to1_30_ping), .out_b1(b0_30to1_30_pong), .out_c(matrixC0_30), .b_data_valid_ping(b_data_valid_ping_delay0_30), .b_data_valid_pong(b_data_valid_pong_delay0_30), .mode(1'b0)); +processing_element pe0_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_0_31_NC), .in_a_chain(a0_30to0_31), .in_b(b31), .in_c(c31), .out_a(out_a_0_31_NC), .out_a_chain(a0_31to0_32), .out_b(b0_31to1_31), .out_b0(b0_31to1_31_ping), .out_b1(b0_31to1_31_pong), .out_c(matrixC0_31), .b_data_valid_ping(b_data_valid_ping_delay0_31), .b_data_valid_pong(b_data_valid_pong_delay0_31), .mode(1'b0)); +processing_element pe1_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay1), .in_a(a1), .in_a_chain(in_a_chain_1_0_NC), .in_b(b0_0to1_0), .in_c(matrixC0_0), .out_a(out_a_1_0_NC), .out_a_chain(a1_0to1_1), .out_b(b1_0to2_0), .out_b0(b1_0to2_0_ping), .out_b1(b1_0to2_0_pong), .out_c(matrixC1_0), .b_data_valid_ping(b_data_valid_ping_delay1_0), .b_data_valid_pong(b_data_valid_pong_delay1_0), .mode(1'b1)); +processing_element pe1_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay2), .in_a(in_a_1_1_NC), .in_a_chain(a1_0to1_1), .in_b(b0_1to1_1), .in_c(matrixC0_1), .out_a(out_a_1_1_NC), .out_a_chain(a1_1to1_2), .out_b(b1_1to2_1), .out_b0(b1_1to2_1_ping), .out_b1(b1_1to2_1_pong), .out_c(matrixC1_1), .b_data_valid_ping(b_data_valid_ping_delay1_1), .b_data_valid_pong(b_data_valid_pong_delay1_1), .mode(1'b0)); +processing_element pe1_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay3), .in_a(in_a_1_2_NC), .in_a_chain(a1_1to1_2), .in_b(b0_2to1_2), .in_c(matrixC0_2), .out_a(out_a_1_2_NC), .out_a_chain(a1_2to1_3), .out_b(b1_2to2_2), .out_b0(b1_2to2_2_ping), .out_b1(b1_2to2_2_pong), .out_c(matrixC1_2), .b_data_valid_ping(b_data_valid_ping_delay1_2), .b_data_valid_pong(b_data_valid_pong_delay1_2), .mode(1'b0)); +processing_element pe1_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay4), .in_a(in_a_1_3_NC), .in_a_chain(a1_2to1_3), .in_b(b0_3to1_3), .in_c(matrixC0_3), .out_a(out_a_1_3_NC), .out_a_chain(a1_3to1_4), .out_b(b1_3to2_3), .out_b0(b1_3to2_3_ping), .out_b1(b1_3to2_3_pong), .out_c(matrixC1_3), .b_data_valid_ping(b_data_valid_ping_delay1_3), .b_data_valid_pong(b_data_valid_pong_delay1_3), .mode(1'b0)); +processing_element pe1_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay5), .in_a(in_a_1_4_NC), .in_a_chain(a1_3to1_4), .in_b(b0_4to1_4), .in_c(matrixC0_4), .out_a(out_a_1_4_NC), .out_a_chain(a1_4to1_5), .out_b(b1_4to2_4), .out_b0(b1_4to2_4_ping), .out_b1(b1_4to2_4_pong), .out_c(matrixC1_4), .b_data_valid_ping(b_data_valid_ping_delay1_4), .b_data_valid_pong(b_data_valid_pong_delay1_4), .mode(1'b0)); +processing_element pe1_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay6), .in_a(in_a_1_5_NC), .in_a_chain(a1_4to1_5), .in_b(b0_5to1_5), .in_c(matrixC0_5), .out_a(out_a_1_5_NC), .out_a_chain(a1_5to1_6), .out_b(b1_5to2_5), .out_b0(b1_5to2_5_ping), .out_b1(b1_5to2_5_pong), .out_c(matrixC1_5), .b_data_valid_ping(b_data_valid_ping_delay1_5), .b_data_valid_pong(b_data_valid_pong_delay1_5), .mode(1'b0)); +processing_element pe1_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(in_a_1_6_NC), .in_a_chain(a1_5to1_6), .in_b(b0_6to1_6), .in_c(matrixC0_6), .out_a(out_a_1_6_NC), .out_a_chain(a1_6to1_7), .out_b(b1_6to2_6), .out_b0(b1_6to2_6_ping), .out_b1(b1_6to2_6_pong), .out_c(matrixC1_6), .b_data_valid_ping(b_data_valid_ping_delay1_6), .b_data_valid_pong(b_data_valid_pong_delay1_6), .mode(1'b0)); +processing_element pe1_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_1_7_NC), .in_a_chain(a1_6to1_7), .in_b(b0_7to1_7), .in_c(matrixC0_7), .out_a(out_a_1_7_NC), .out_a_chain(a1_7to1_8), .out_b(b1_7to2_7), .out_b0(b1_7to2_7_ping), .out_b1(b1_7to2_7_pong), .out_c(matrixC1_7), .b_data_valid_ping(b_data_valid_ping_delay1_7), .b_data_valid_pong(b_data_valid_pong_delay1_7), .mode(1'b0)); +processing_element pe1_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_1_8_NC), .in_a_chain(a1_7to1_8), .in_b(b0_8to1_8), .in_c(matrixC0_8), .out_a(out_a_1_8_NC), .out_a_chain(a1_8to1_9), .out_b(b1_8to2_8), .out_b0(b1_8to2_8_ping), .out_b1(b1_8to2_8_pong), .out_c(matrixC1_8), .b_data_valid_ping(b_data_valid_ping_delay1_8), .b_data_valid_pong(b_data_valid_pong_delay1_8), .mode(1'b0)); +processing_element pe1_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_1_9_NC), .in_a_chain(a1_8to1_9), .in_b(b0_9to1_9), .in_c(matrixC0_9), .out_a(out_a_1_9_NC), .out_a_chain(a1_9to1_10), .out_b(b1_9to2_9), .out_b0(b1_9to2_9_ping), .out_b1(b1_9to2_9_pong), .out_c(matrixC1_9), .b_data_valid_ping(b_data_valid_ping_delay1_9), .b_data_valid_pong(b_data_valid_pong_delay1_9), .mode(1'b0)); +processing_element pe1_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_1_10_NC), .in_a_chain(a1_9to1_10), .in_b(b0_10to1_10), .in_c(matrixC0_10), .out_a(out_a_1_10_NC), .out_a_chain(a1_10to1_11), .out_b(b1_10to2_10), .out_b0(b1_10to2_10_ping), .out_b1(b1_10to2_10_pong), .out_c(matrixC1_10), .b_data_valid_ping(b_data_valid_ping_delay1_10), .b_data_valid_pong(b_data_valid_pong_delay1_10), .mode(1'b0)); +processing_element pe1_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_1_11_NC), .in_a_chain(a1_10to1_11), .in_b(b0_11to1_11), .in_c(matrixC0_11), .out_a(out_a_1_11_NC), .out_a_chain(a1_11to1_12), .out_b(b1_11to2_11), .out_b0(b1_11to2_11_ping), .out_b1(b1_11to2_11_pong), .out_c(matrixC1_11), .b_data_valid_ping(b_data_valid_ping_delay1_11), .b_data_valid_pong(b_data_valid_pong_delay1_11), .mode(1'b0)); +processing_element pe1_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_1_12_NC), .in_a_chain(a1_11to1_12), .in_b(b0_12to1_12), .in_c(matrixC0_12), .out_a(out_a_1_12_NC), .out_a_chain(a1_12to1_13), .out_b(b1_12to2_12), .out_b0(b1_12to2_12_ping), .out_b1(b1_12to2_12_pong), .out_c(matrixC1_12), .b_data_valid_ping(b_data_valid_ping_delay1_12), .b_data_valid_pong(b_data_valid_pong_delay1_12), .mode(1'b0)); +processing_element pe1_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_1_13_NC), .in_a_chain(a1_12to1_13), .in_b(b0_13to1_13), .in_c(matrixC0_13), .out_a(out_a_1_13_NC), .out_a_chain(a1_13to1_14), .out_b(b1_13to2_13), .out_b0(b1_13to2_13_ping), .out_b1(b1_13to2_13_pong), .out_c(matrixC1_13), .b_data_valid_ping(b_data_valid_ping_delay1_13), .b_data_valid_pong(b_data_valid_pong_delay1_13), .mode(1'b0)); +processing_element pe1_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_1_14_NC), .in_a_chain(a1_13to1_14), .in_b(b0_14to1_14), .in_c(matrixC0_14), .out_a(out_a_1_14_NC), .out_a_chain(a1_14to1_15), .out_b(b1_14to2_14), .out_b0(b1_14to2_14_ping), .out_b1(b1_14to2_14_pong), .out_c(matrixC1_14), .b_data_valid_ping(b_data_valid_ping_delay1_14), .b_data_valid_pong(b_data_valid_pong_delay1_14), .mode(1'b0)); +processing_element pe1_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_1_15_NC), .in_a_chain(a1_14to1_15), .in_b(b0_15to1_15), .in_c(matrixC0_15), .out_a(out_a_1_15_NC), .out_a_chain(a1_15to1_16), .out_b(b1_15to2_15), .out_b0(b1_15to2_15_ping), .out_b1(b1_15to2_15_pong), .out_c(matrixC1_15), .b_data_valid_ping(b_data_valid_ping_delay1_15), .b_data_valid_pong(b_data_valid_pong_delay1_15), .mode(1'b0)); +processing_element pe1_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_1_16_NC), .in_a_chain(a1_15to1_16), .in_b(b0_16to1_16), .in_c(matrixC0_16), .out_a(out_a_1_16_NC), .out_a_chain(a1_16to1_17), .out_b(b1_16to2_16), .out_b0(b1_16to2_16_ping), .out_b1(b1_16to2_16_pong), .out_c(matrixC1_16), .b_data_valid_ping(b_data_valid_ping_delay1_16), .b_data_valid_pong(b_data_valid_pong_delay1_16), .mode(1'b0)); +processing_element pe1_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_1_17_NC), .in_a_chain(a1_16to1_17), .in_b(b0_17to1_17), .in_c(matrixC0_17), .out_a(out_a_1_17_NC), .out_a_chain(a1_17to1_18), .out_b(b1_17to2_17), .out_b0(b1_17to2_17_ping), .out_b1(b1_17to2_17_pong), .out_c(matrixC1_17), .b_data_valid_ping(b_data_valid_ping_delay1_17), .b_data_valid_pong(b_data_valid_pong_delay1_17), .mode(1'b0)); +processing_element pe1_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_1_18_NC), .in_a_chain(a1_17to1_18), .in_b(b0_18to1_18), .in_c(matrixC0_18), .out_a(out_a_1_18_NC), .out_a_chain(a1_18to1_19), .out_b(b1_18to2_18), .out_b0(b1_18to2_18_ping), .out_b1(b1_18to2_18_pong), .out_c(matrixC1_18), .b_data_valid_ping(b_data_valid_ping_delay1_18), .b_data_valid_pong(b_data_valid_pong_delay1_18), .mode(1'b0)); +processing_element pe1_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_1_19_NC), .in_a_chain(a1_18to1_19), .in_b(b0_19to1_19), .in_c(matrixC0_19), .out_a(out_a_1_19_NC), .out_a_chain(a1_19to1_20), .out_b(b1_19to2_19), .out_b0(b1_19to2_19_ping), .out_b1(b1_19to2_19_pong), .out_c(matrixC1_19), .b_data_valid_ping(b_data_valid_ping_delay1_19), .b_data_valid_pong(b_data_valid_pong_delay1_19), .mode(1'b0)); +processing_element pe1_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_1_20_NC), .in_a_chain(a1_19to1_20), .in_b(b0_20to1_20), .in_c(matrixC0_20), .out_a(out_a_1_20_NC), .out_a_chain(a1_20to1_21), .out_b(b1_20to2_20), .out_b0(b1_20to2_20_ping), .out_b1(b1_20to2_20_pong), .out_c(matrixC1_20), .b_data_valid_ping(b_data_valid_ping_delay1_20), .b_data_valid_pong(b_data_valid_pong_delay1_20), .mode(1'b0)); +processing_element pe1_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_1_21_NC), .in_a_chain(a1_20to1_21), .in_b(b0_21to1_21), .in_c(matrixC0_21), .out_a(out_a_1_21_NC), .out_a_chain(a1_21to1_22), .out_b(b1_21to2_21), .out_b0(b1_21to2_21_ping), .out_b1(b1_21to2_21_pong), .out_c(matrixC1_21), .b_data_valid_ping(b_data_valid_ping_delay1_21), .b_data_valid_pong(b_data_valid_pong_delay1_21), .mode(1'b0)); +processing_element pe1_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_1_22_NC), .in_a_chain(a1_21to1_22), .in_b(b0_22to1_22), .in_c(matrixC0_22), .out_a(out_a_1_22_NC), .out_a_chain(a1_22to1_23), .out_b(b1_22to2_22), .out_b0(b1_22to2_22_ping), .out_b1(b1_22to2_22_pong), .out_c(matrixC1_22), .b_data_valid_ping(b_data_valid_ping_delay1_22), .b_data_valid_pong(b_data_valid_pong_delay1_22), .mode(1'b0)); +processing_element pe1_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_1_23_NC), .in_a_chain(a1_22to1_23), .in_b(b0_23to1_23), .in_c(matrixC0_23), .out_a(out_a_1_23_NC), .out_a_chain(a1_23to1_24), .out_b(b1_23to2_23), .out_b0(b1_23to2_23_ping), .out_b1(b1_23to2_23_pong), .out_c(matrixC1_23), .b_data_valid_ping(b_data_valid_ping_delay1_23), .b_data_valid_pong(b_data_valid_pong_delay1_23), .mode(1'b0)); +processing_element pe1_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_1_24_NC), .in_a_chain(a1_23to1_24), .in_b(b0_24to1_24), .in_c(matrixC0_24), .out_a(out_a_1_24_NC), .out_a_chain(a1_24to1_25), .out_b(b1_24to2_24), .out_b0(b1_24to2_24_ping), .out_b1(b1_24to2_24_pong), .out_c(matrixC1_24), .b_data_valid_ping(b_data_valid_ping_delay1_24), .b_data_valid_pong(b_data_valid_pong_delay1_24), .mode(1'b0)); +processing_element pe1_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_1_25_NC), .in_a_chain(a1_24to1_25), .in_b(b0_25to1_25), .in_c(matrixC0_25), .out_a(out_a_1_25_NC), .out_a_chain(a1_25to1_26), .out_b(b1_25to2_25), .out_b0(b1_25to2_25_ping), .out_b1(b1_25to2_25_pong), .out_c(matrixC1_25), .b_data_valid_ping(b_data_valid_ping_delay1_25), .b_data_valid_pong(b_data_valid_pong_delay1_25), .mode(1'b0)); +processing_element pe1_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_1_26_NC), .in_a_chain(a1_25to1_26), .in_b(b0_26to1_26), .in_c(matrixC0_26), .out_a(out_a_1_26_NC), .out_a_chain(a1_26to1_27), .out_b(b1_26to2_26), .out_b0(b1_26to2_26_ping), .out_b1(b1_26to2_26_pong), .out_c(matrixC1_26), .b_data_valid_ping(b_data_valid_ping_delay1_26), .b_data_valid_pong(b_data_valid_pong_delay1_26), .mode(1'b0)); +processing_element pe1_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_1_27_NC), .in_a_chain(a1_26to1_27), .in_b(b0_27to1_27), .in_c(matrixC0_27), .out_a(out_a_1_27_NC), .out_a_chain(a1_27to1_28), .out_b(b1_27to2_27), .out_b0(b1_27to2_27_ping), .out_b1(b1_27to2_27_pong), .out_c(matrixC1_27), .b_data_valid_ping(b_data_valid_ping_delay1_27), .b_data_valid_pong(b_data_valid_pong_delay1_27), .mode(1'b0)); +processing_element pe1_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_1_28_NC), .in_a_chain(a1_27to1_28), .in_b(b0_28to1_28), .in_c(matrixC0_28), .out_a(out_a_1_28_NC), .out_a_chain(a1_28to1_29), .out_b(b1_28to2_28), .out_b0(b1_28to2_28_ping), .out_b1(b1_28to2_28_pong), .out_c(matrixC1_28), .b_data_valid_ping(b_data_valid_ping_delay1_28), .b_data_valid_pong(b_data_valid_pong_delay1_28), .mode(1'b0)); +processing_element pe1_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_1_29_NC), .in_a_chain(a1_28to1_29), .in_b(b0_29to1_29), .in_c(matrixC0_29), .out_a(out_a_1_29_NC), .out_a_chain(a1_29to1_30), .out_b(b1_29to2_29), .out_b0(b1_29to2_29_ping), .out_b1(b1_29to2_29_pong), .out_c(matrixC1_29), .b_data_valid_ping(b_data_valid_ping_delay1_29), .b_data_valid_pong(b_data_valid_pong_delay1_29), .mode(1'b0)); +processing_element pe1_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_1_30_NC), .in_a_chain(a1_29to1_30), .in_b(b0_30to1_30), .in_c(matrixC0_30), .out_a(out_a_1_30_NC), .out_a_chain(a1_30to1_31), .out_b(b1_30to2_30), .out_b0(b1_30to2_30_ping), .out_b1(b1_30to2_30_pong), .out_c(matrixC1_30), .b_data_valid_ping(b_data_valid_ping_delay1_30), .b_data_valid_pong(b_data_valid_pong_delay1_30), .mode(1'b0)); +processing_element pe1_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_1_31_NC), .in_a_chain(a1_30to1_31), .in_b(b0_31to1_31), .in_c(matrixC0_31), .out_a(out_a_1_31_NC), .out_a_chain(a1_31to1_32), .out_b(b1_31to2_31), .out_b0(b1_31to2_31_ping), .out_b1(b1_31to2_31_pong), .out_c(matrixC1_31), .b_data_valid_ping(b_data_valid_ping_delay1_31), .b_data_valid_pong(b_data_valid_pong_delay1_31), .mode(1'b0)); +processing_element pe2_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay2), .in_a(a2), .in_a_chain(in_a_chain_2_0_NC), .in_b(b1_0to2_0), .in_c(matrixC1_0), .out_a(out_a_2_0_NC), .out_a_chain(a2_0to2_1), .out_b(b2_0to3_0), .out_b0(b2_0to3_0_ping), .out_b1(b2_0to3_0_pong), .out_c(matrixC2_0), .b_data_valid_ping(b_data_valid_ping_delay2_0), .b_data_valid_pong(b_data_valid_pong_delay2_0), .mode(1'b1)); +processing_element pe2_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay3), .in_a(in_a_2_1_NC), .in_a_chain(a2_0to2_1), .in_b(b1_1to2_1), .in_c(matrixC1_1), .out_a(out_a_2_1_NC), .out_a_chain(a2_1to2_2), .out_b(b2_1to3_1), .out_b0(b2_1to3_1_ping), .out_b1(b2_1to3_1_pong), .out_c(matrixC2_1), .b_data_valid_ping(b_data_valid_ping_delay2_1), .b_data_valid_pong(b_data_valid_pong_delay2_1), .mode(1'b0)); +processing_element pe2_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay4), .in_a(in_a_2_2_NC), .in_a_chain(a2_1to2_2), .in_b(b1_2to2_2), .in_c(matrixC1_2), .out_a(out_a_2_2_NC), .out_a_chain(a2_2to2_3), .out_b(b2_2to3_2), .out_b0(b2_2to3_2_ping), .out_b1(b2_2to3_2_pong), .out_c(matrixC2_2), .b_data_valid_ping(b_data_valid_ping_delay2_2), .b_data_valid_pong(b_data_valid_pong_delay2_2), .mode(1'b0)); +processing_element pe2_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay5), .in_a(in_a_2_3_NC), .in_a_chain(a2_2to2_3), .in_b(b1_3to2_3), .in_c(matrixC1_3), .out_a(out_a_2_3_NC), .out_a_chain(a2_3to2_4), .out_b(b2_3to3_3), .out_b0(b2_3to3_3_ping), .out_b1(b2_3to3_3_pong), .out_c(matrixC2_3), .b_data_valid_ping(b_data_valid_ping_delay2_3), .b_data_valid_pong(b_data_valid_pong_delay2_3), .mode(1'b0)); +processing_element pe2_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay6), .in_a(in_a_2_4_NC), .in_a_chain(a2_3to2_4), .in_b(b1_4to2_4), .in_c(matrixC1_4), .out_a(out_a_2_4_NC), .out_a_chain(a2_4to2_5), .out_b(b2_4to3_4), .out_b0(b2_4to3_4_ping), .out_b1(b2_4to3_4_pong), .out_c(matrixC2_4), .b_data_valid_ping(b_data_valid_ping_delay2_4), .b_data_valid_pong(b_data_valid_pong_delay2_4), .mode(1'b0)); +processing_element pe2_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(in_a_2_5_NC), .in_a_chain(a2_4to2_5), .in_b(b1_5to2_5), .in_c(matrixC1_5), .out_a(out_a_2_5_NC), .out_a_chain(a2_5to2_6), .out_b(b2_5to3_5), .out_b0(b2_5to3_5_ping), .out_b1(b2_5to3_5_pong), .out_c(matrixC2_5), .b_data_valid_ping(b_data_valid_ping_delay2_5), .b_data_valid_pong(b_data_valid_pong_delay2_5), .mode(1'b0)); +processing_element pe2_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_2_6_NC), .in_a_chain(a2_5to2_6), .in_b(b1_6to2_6), .in_c(matrixC1_6), .out_a(out_a_2_6_NC), .out_a_chain(a2_6to2_7), .out_b(b2_6to3_6), .out_b0(b2_6to3_6_ping), .out_b1(b2_6to3_6_pong), .out_c(matrixC2_6), .b_data_valid_ping(b_data_valid_ping_delay2_6), .b_data_valid_pong(b_data_valid_pong_delay2_6), .mode(1'b0)); +processing_element pe2_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_2_7_NC), .in_a_chain(a2_6to2_7), .in_b(b1_7to2_7), .in_c(matrixC1_7), .out_a(out_a_2_7_NC), .out_a_chain(a2_7to2_8), .out_b(b2_7to3_7), .out_b0(b2_7to3_7_ping), .out_b1(b2_7to3_7_pong), .out_c(matrixC2_7), .b_data_valid_ping(b_data_valid_ping_delay2_7), .b_data_valid_pong(b_data_valid_pong_delay2_7), .mode(1'b0)); +processing_element pe2_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_2_8_NC), .in_a_chain(a2_7to2_8), .in_b(b1_8to2_8), .in_c(matrixC1_8), .out_a(out_a_2_8_NC), .out_a_chain(a2_8to2_9), .out_b(b2_8to3_8), .out_b0(b2_8to3_8_ping), .out_b1(b2_8to3_8_pong), .out_c(matrixC2_8), .b_data_valid_ping(b_data_valid_ping_delay2_8), .b_data_valid_pong(b_data_valid_pong_delay2_8), .mode(1'b0)); +processing_element pe2_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_2_9_NC), .in_a_chain(a2_8to2_9), .in_b(b1_9to2_9), .in_c(matrixC1_9), .out_a(out_a_2_9_NC), .out_a_chain(a2_9to2_10), .out_b(b2_9to3_9), .out_b0(b2_9to3_9_ping), .out_b1(b2_9to3_9_pong), .out_c(matrixC2_9), .b_data_valid_ping(b_data_valid_ping_delay2_9), .b_data_valid_pong(b_data_valid_pong_delay2_9), .mode(1'b0)); +processing_element pe2_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_2_10_NC), .in_a_chain(a2_9to2_10), .in_b(b1_10to2_10), .in_c(matrixC1_10), .out_a(out_a_2_10_NC), .out_a_chain(a2_10to2_11), .out_b(b2_10to3_10), .out_b0(b2_10to3_10_ping), .out_b1(b2_10to3_10_pong), .out_c(matrixC2_10), .b_data_valid_ping(b_data_valid_ping_delay2_10), .b_data_valid_pong(b_data_valid_pong_delay2_10), .mode(1'b0)); +processing_element pe2_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_2_11_NC), .in_a_chain(a2_10to2_11), .in_b(b1_11to2_11), .in_c(matrixC1_11), .out_a(out_a_2_11_NC), .out_a_chain(a2_11to2_12), .out_b(b2_11to3_11), .out_b0(b2_11to3_11_ping), .out_b1(b2_11to3_11_pong), .out_c(matrixC2_11), .b_data_valid_ping(b_data_valid_ping_delay2_11), .b_data_valid_pong(b_data_valid_pong_delay2_11), .mode(1'b0)); +processing_element pe2_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_2_12_NC), .in_a_chain(a2_11to2_12), .in_b(b1_12to2_12), .in_c(matrixC1_12), .out_a(out_a_2_12_NC), .out_a_chain(a2_12to2_13), .out_b(b2_12to3_12), .out_b0(b2_12to3_12_ping), .out_b1(b2_12to3_12_pong), .out_c(matrixC2_12), .b_data_valid_ping(b_data_valid_ping_delay2_12), .b_data_valid_pong(b_data_valid_pong_delay2_12), .mode(1'b0)); +processing_element pe2_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_2_13_NC), .in_a_chain(a2_12to2_13), .in_b(b1_13to2_13), .in_c(matrixC1_13), .out_a(out_a_2_13_NC), .out_a_chain(a2_13to2_14), .out_b(b2_13to3_13), .out_b0(b2_13to3_13_ping), .out_b1(b2_13to3_13_pong), .out_c(matrixC2_13), .b_data_valid_ping(b_data_valid_ping_delay2_13), .b_data_valid_pong(b_data_valid_pong_delay2_13), .mode(1'b0)); +processing_element pe2_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_2_14_NC), .in_a_chain(a2_13to2_14), .in_b(b1_14to2_14), .in_c(matrixC1_14), .out_a(out_a_2_14_NC), .out_a_chain(a2_14to2_15), .out_b(b2_14to3_14), .out_b0(b2_14to3_14_ping), .out_b1(b2_14to3_14_pong), .out_c(matrixC2_14), .b_data_valid_ping(b_data_valid_ping_delay2_14), .b_data_valid_pong(b_data_valid_pong_delay2_14), .mode(1'b0)); +processing_element pe2_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_2_15_NC), .in_a_chain(a2_14to2_15), .in_b(b1_15to2_15), .in_c(matrixC1_15), .out_a(out_a_2_15_NC), .out_a_chain(a2_15to2_16), .out_b(b2_15to3_15), .out_b0(b2_15to3_15_ping), .out_b1(b2_15to3_15_pong), .out_c(matrixC2_15), .b_data_valid_ping(b_data_valid_ping_delay2_15), .b_data_valid_pong(b_data_valid_pong_delay2_15), .mode(1'b0)); +processing_element pe2_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_2_16_NC), .in_a_chain(a2_15to2_16), .in_b(b1_16to2_16), .in_c(matrixC1_16), .out_a(out_a_2_16_NC), .out_a_chain(a2_16to2_17), .out_b(b2_16to3_16), .out_b0(b2_16to3_16_ping), .out_b1(b2_16to3_16_pong), .out_c(matrixC2_16), .b_data_valid_ping(b_data_valid_ping_delay2_16), .b_data_valid_pong(b_data_valid_pong_delay2_16), .mode(1'b0)); +processing_element pe2_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_2_17_NC), .in_a_chain(a2_16to2_17), .in_b(b1_17to2_17), .in_c(matrixC1_17), .out_a(out_a_2_17_NC), .out_a_chain(a2_17to2_18), .out_b(b2_17to3_17), .out_b0(b2_17to3_17_ping), .out_b1(b2_17to3_17_pong), .out_c(matrixC2_17), .b_data_valid_ping(b_data_valid_ping_delay2_17), .b_data_valid_pong(b_data_valid_pong_delay2_17), .mode(1'b0)); +processing_element pe2_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_2_18_NC), .in_a_chain(a2_17to2_18), .in_b(b1_18to2_18), .in_c(matrixC1_18), .out_a(out_a_2_18_NC), .out_a_chain(a2_18to2_19), .out_b(b2_18to3_18), .out_b0(b2_18to3_18_ping), .out_b1(b2_18to3_18_pong), .out_c(matrixC2_18), .b_data_valid_ping(b_data_valid_ping_delay2_18), .b_data_valid_pong(b_data_valid_pong_delay2_18), .mode(1'b0)); +processing_element pe2_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_2_19_NC), .in_a_chain(a2_18to2_19), .in_b(b1_19to2_19), .in_c(matrixC1_19), .out_a(out_a_2_19_NC), .out_a_chain(a2_19to2_20), .out_b(b2_19to3_19), .out_b0(b2_19to3_19_ping), .out_b1(b2_19to3_19_pong), .out_c(matrixC2_19), .b_data_valid_ping(b_data_valid_ping_delay2_19), .b_data_valid_pong(b_data_valid_pong_delay2_19), .mode(1'b0)); +processing_element pe2_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_2_20_NC), .in_a_chain(a2_19to2_20), .in_b(b1_20to2_20), .in_c(matrixC1_20), .out_a(out_a_2_20_NC), .out_a_chain(a2_20to2_21), .out_b(b2_20to3_20), .out_b0(b2_20to3_20_ping), .out_b1(b2_20to3_20_pong), .out_c(matrixC2_20), .b_data_valid_ping(b_data_valid_ping_delay2_20), .b_data_valid_pong(b_data_valid_pong_delay2_20), .mode(1'b0)); +processing_element pe2_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_2_21_NC), .in_a_chain(a2_20to2_21), .in_b(b1_21to2_21), .in_c(matrixC1_21), .out_a(out_a_2_21_NC), .out_a_chain(a2_21to2_22), .out_b(b2_21to3_21), .out_b0(b2_21to3_21_ping), .out_b1(b2_21to3_21_pong), .out_c(matrixC2_21), .b_data_valid_ping(b_data_valid_ping_delay2_21), .b_data_valid_pong(b_data_valid_pong_delay2_21), .mode(1'b0)); +processing_element pe2_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_2_22_NC), .in_a_chain(a2_21to2_22), .in_b(b1_22to2_22), .in_c(matrixC1_22), .out_a(out_a_2_22_NC), .out_a_chain(a2_22to2_23), .out_b(b2_22to3_22), .out_b0(b2_22to3_22_ping), .out_b1(b2_22to3_22_pong), .out_c(matrixC2_22), .b_data_valid_ping(b_data_valid_ping_delay2_22), .b_data_valid_pong(b_data_valid_pong_delay2_22), .mode(1'b0)); +processing_element pe2_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_2_23_NC), .in_a_chain(a2_22to2_23), .in_b(b1_23to2_23), .in_c(matrixC1_23), .out_a(out_a_2_23_NC), .out_a_chain(a2_23to2_24), .out_b(b2_23to3_23), .out_b0(b2_23to3_23_ping), .out_b1(b2_23to3_23_pong), .out_c(matrixC2_23), .b_data_valid_ping(b_data_valid_ping_delay2_23), .b_data_valid_pong(b_data_valid_pong_delay2_23), .mode(1'b0)); +processing_element pe2_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_2_24_NC), .in_a_chain(a2_23to2_24), .in_b(b1_24to2_24), .in_c(matrixC1_24), .out_a(out_a_2_24_NC), .out_a_chain(a2_24to2_25), .out_b(b2_24to3_24), .out_b0(b2_24to3_24_ping), .out_b1(b2_24to3_24_pong), .out_c(matrixC2_24), .b_data_valid_ping(b_data_valid_ping_delay2_24), .b_data_valid_pong(b_data_valid_pong_delay2_24), .mode(1'b0)); +processing_element pe2_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_2_25_NC), .in_a_chain(a2_24to2_25), .in_b(b1_25to2_25), .in_c(matrixC1_25), .out_a(out_a_2_25_NC), .out_a_chain(a2_25to2_26), .out_b(b2_25to3_25), .out_b0(b2_25to3_25_ping), .out_b1(b2_25to3_25_pong), .out_c(matrixC2_25), .b_data_valid_ping(b_data_valid_ping_delay2_25), .b_data_valid_pong(b_data_valid_pong_delay2_25), .mode(1'b0)); +processing_element pe2_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_2_26_NC), .in_a_chain(a2_25to2_26), .in_b(b1_26to2_26), .in_c(matrixC1_26), .out_a(out_a_2_26_NC), .out_a_chain(a2_26to2_27), .out_b(b2_26to3_26), .out_b0(b2_26to3_26_ping), .out_b1(b2_26to3_26_pong), .out_c(matrixC2_26), .b_data_valid_ping(b_data_valid_ping_delay2_26), .b_data_valid_pong(b_data_valid_pong_delay2_26), .mode(1'b0)); +processing_element pe2_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_2_27_NC), .in_a_chain(a2_26to2_27), .in_b(b1_27to2_27), .in_c(matrixC1_27), .out_a(out_a_2_27_NC), .out_a_chain(a2_27to2_28), .out_b(b2_27to3_27), .out_b0(b2_27to3_27_ping), .out_b1(b2_27to3_27_pong), .out_c(matrixC2_27), .b_data_valid_ping(b_data_valid_ping_delay2_27), .b_data_valid_pong(b_data_valid_pong_delay2_27), .mode(1'b0)); +processing_element pe2_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_2_28_NC), .in_a_chain(a2_27to2_28), .in_b(b1_28to2_28), .in_c(matrixC1_28), .out_a(out_a_2_28_NC), .out_a_chain(a2_28to2_29), .out_b(b2_28to3_28), .out_b0(b2_28to3_28_ping), .out_b1(b2_28to3_28_pong), .out_c(matrixC2_28), .b_data_valid_ping(b_data_valid_ping_delay2_28), .b_data_valid_pong(b_data_valid_pong_delay2_28), .mode(1'b0)); +processing_element pe2_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_2_29_NC), .in_a_chain(a2_28to2_29), .in_b(b1_29to2_29), .in_c(matrixC1_29), .out_a(out_a_2_29_NC), .out_a_chain(a2_29to2_30), .out_b(b2_29to3_29), .out_b0(b2_29to3_29_ping), .out_b1(b2_29to3_29_pong), .out_c(matrixC2_29), .b_data_valid_ping(b_data_valid_ping_delay2_29), .b_data_valid_pong(b_data_valid_pong_delay2_29), .mode(1'b0)); +processing_element pe2_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_2_30_NC), .in_a_chain(a2_29to2_30), .in_b(b1_30to2_30), .in_c(matrixC1_30), .out_a(out_a_2_30_NC), .out_a_chain(a2_30to2_31), .out_b(b2_30to3_30), .out_b0(b2_30to3_30_ping), .out_b1(b2_30to3_30_pong), .out_c(matrixC2_30), .b_data_valid_ping(b_data_valid_ping_delay2_30), .b_data_valid_pong(b_data_valid_pong_delay2_30), .mode(1'b0)); +processing_element pe2_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_2_31_NC), .in_a_chain(a2_30to2_31), .in_b(b1_31to2_31), .in_c(matrixC1_31), .out_a(out_a_2_31_NC), .out_a_chain(a2_31to2_32), .out_b(b2_31to3_31), .out_b0(b2_31to3_31_ping), .out_b1(b2_31to3_31_pong), .out_c(matrixC2_31), .b_data_valid_ping(b_data_valid_ping_delay2_31), .b_data_valid_pong(b_data_valid_pong_delay2_31), .mode(1'b0)); +processing_element pe3_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay3), .in_a(a3), .in_a_chain(in_a_chain_3_0_NC), .in_b(b2_0to3_0), .in_c(matrixC2_0), .out_a(out_a_3_0_NC), .out_a_chain(a3_0to3_1), .out_b(b3_0to4_0), .out_b0(b3_0to4_0_ping), .out_b1(b3_0to4_0_pong), .out_c(matrixC3_0), .b_data_valid_ping(b_data_valid_ping_delay3_0), .b_data_valid_pong(b_data_valid_pong_delay3_0), .mode(1'b1)); +processing_element pe3_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay4), .in_a(in_a_3_1_NC), .in_a_chain(a3_0to3_1), .in_b(b2_1to3_1), .in_c(matrixC2_1), .out_a(out_a_3_1_NC), .out_a_chain(a3_1to3_2), .out_b(b3_1to4_1), .out_b0(b3_1to4_1_ping), .out_b1(b3_1to4_1_pong), .out_c(matrixC3_1), .b_data_valid_ping(b_data_valid_ping_delay3_1), .b_data_valid_pong(b_data_valid_pong_delay3_1), .mode(1'b0)); +processing_element pe3_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay5), .in_a(in_a_3_2_NC), .in_a_chain(a3_1to3_2), .in_b(b2_2to3_2), .in_c(matrixC2_2), .out_a(out_a_3_2_NC), .out_a_chain(a3_2to3_3), .out_b(b3_2to4_2), .out_b0(b3_2to4_2_ping), .out_b1(b3_2to4_2_pong), .out_c(matrixC3_2), .b_data_valid_ping(b_data_valid_ping_delay3_2), .b_data_valid_pong(b_data_valid_pong_delay3_2), .mode(1'b0)); +processing_element pe3_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay6), .in_a(in_a_3_3_NC), .in_a_chain(a3_2to3_3), .in_b(b2_3to3_3), .in_c(matrixC2_3), .out_a(out_a_3_3_NC), .out_a_chain(a3_3to3_4), .out_b(b3_3to4_3), .out_b0(b3_3to4_3_ping), .out_b1(b3_3to4_3_pong), .out_c(matrixC3_3), .b_data_valid_ping(b_data_valid_ping_delay3_3), .b_data_valid_pong(b_data_valid_pong_delay3_3), .mode(1'b0)); +processing_element pe3_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(in_a_3_4_NC), .in_a_chain(a3_3to3_4), .in_b(b2_4to3_4), .in_c(matrixC2_4), .out_a(out_a_3_4_NC), .out_a_chain(a3_4to3_5), .out_b(b3_4to4_4), .out_b0(b3_4to4_4_ping), .out_b1(b3_4to4_4_pong), .out_c(matrixC3_4), .b_data_valid_ping(b_data_valid_ping_delay3_4), .b_data_valid_pong(b_data_valid_pong_delay3_4), .mode(1'b0)); +processing_element pe3_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_3_5_NC), .in_a_chain(a3_4to3_5), .in_b(b2_5to3_5), .in_c(matrixC2_5), .out_a(out_a_3_5_NC), .out_a_chain(a3_5to3_6), .out_b(b3_5to4_5), .out_b0(b3_5to4_5_ping), .out_b1(b3_5to4_5_pong), .out_c(matrixC3_5), .b_data_valid_ping(b_data_valid_ping_delay3_5), .b_data_valid_pong(b_data_valid_pong_delay3_5), .mode(1'b0)); +processing_element pe3_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_3_6_NC), .in_a_chain(a3_5to3_6), .in_b(b2_6to3_6), .in_c(matrixC2_6), .out_a(out_a_3_6_NC), .out_a_chain(a3_6to3_7), .out_b(b3_6to4_6), .out_b0(b3_6to4_6_ping), .out_b1(b3_6to4_6_pong), .out_c(matrixC3_6), .b_data_valid_ping(b_data_valid_ping_delay3_6), .b_data_valid_pong(b_data_valid_pong_delay3_6), .mode(1'b0)); +processing_element pe3_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_3_7_NC), .in_a_chain(a3_6to3_7), .in_b(b2_7to3_7), .in_c(matrixC2_7), .out_a(out_a_3_7_NC), .out_a_chain(a3_7to3_8), .out_b(b3_7to4_7), .out_b0(b3_7to4_7_ping), .out_b1(b3_7to4_7_pong), .out_c(matrixC3_7), .b_data_valid_ping(b_data_valid_ping_delay3_7), .b_data_valid_pong(b_data_valid_pong_delay3_7), .mode(1'b0)); +processing_element pe3_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_3_8_NC), .in_a_chain(a3_7to3_8), .in_b(b2_8to3_8), .in_c(matrixC2_8), .out_a(out_a_3_8_NC), .out_a_chain(a3_8to3_9), .out_b(b3_8to4_8), .out_b0(b3_8to4_8_ping), .out_b1(b3_8to4_8_pong), .out_c(matrixC3_8), .b_data_valid_ping(b_data_valid_ping_delay3_8), .b_data_valid_pong(b_data_valid_pong_delay3_8), .mode(1'b0)); +processing_element pe3_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_3_9_NC), .in_a_chain(a3_8to3_9), .in_b(b2_9to3_9), .in_c(matrixC2_9), .out_a(out_a_3_9_NC), .out_a_chain(a3_9to3_10), .out_b(b3_9to4_9), .out_b0(b3_9to4_9_ping), .out_b1(b3_9to4_9_pong), .out_c(matrixC3_9), .b_data_valid_ping(b_data_valid_ping_delay3_9), .b_data_valid_pong(b_data_valid_pong_delay3_9), .mode(1'b0)); +processing_element pe3_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_3_10_NC), .in_a_chain(a3_9to3_10), .in_b(b2_10to3_10), .in_c(matrixC2_10), .out_a(out_a_3_10_NC), .out_a_chain(a3_10to3_11), .out_b(b3_10to4_10), .out_b0(b3_10to4_10_ping), .out_b1(b3_10to4_10_pong), .out_c(matrixC3_10), .b_data_valid_ping(b_data_valid_ping_delay3_10), .b_data_valid_pong(b_data_valid_pong_delay3_10), .mode(1'b0)); +processing_element pe3_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_3_11_NC), .in_a_chain(a3_10to3_11), .in_b(b2_11to3_11), .in_c(matrixC2_11), .out_a(out_a_3_11_NC), .out_a_chain(a3_11to3_12), .out_b(b3_11to4_11), .out_b0(b3_11to4_11_ping), .out_b1(b3_11to4_11_pong), .out_c(matrixC3_11), .b_data_valid_ping(b_data_valid_ping_delay3_11), .b_data_valid_pong(b_data_valid_pong_delay3_11), .mode(1'b0)); +processing_element pe3_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_3_12_NC), .in_a_chain(a3_11to3_12), .in_b(b2_12to3_12), .in_c(matrixC2_12), .out_a(out_a_3_12_NC), .out_a_chain(a3_12to3_13), .out_b(b3_12to4_12), .out_b0(b3_12to4_12_ping), .out_b1(b3_12to4_12_pong), .out_c(matrixC3_12), .b_data_valid_ping(b_data_valid_ping_delay3_12), .b_data_valid_pong(b_data_valid_pong_delay3_12), .mode(1'b0)); +processing_element pe3_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_3_13_NC), .in_a_chain(a3_12to3_13), .in_b(b2_13to3_13), .in_c(matrixC2_13), .out_a(out_a_3_13_NC), .out_a_chain(a3_13to3_14), .out_b(b3_13to4_13), .out_b0(b3_13to4_13_ping), .out_b1(b3_13to4_13_pong), .out_c(matrixC3_13), .b_data_valid_ping(b_data_valid_ping_delay3_13), .b_data_valid_pong(b_data_valid_pong_delay3_13), .mode(1'b0)); +processing_element pe3_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_3_14_NC), .in_a_chain(a3_13to3_14), .in_b(b2_14to3_14), .in_c(matrixC2_14), .out_a(out_a_3_14_NC), .out_a_chain(a3_14to3_15), .out_b(b3_14to4_14), .out_b0(b3_14to4_14_ping), .out_b1(b3_14to4_14_pong), .out_c(matrixC3_14), .b_data_valid_ping(b_data_valid_ping_delay3_14), .b_data_valid_pong(b_data_valid_pong_delay3_14), .mode(1'b0)); +processing_element pe3_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_3_15_NC), .in_a_chain(a3_14to3_15), .in_b(b2_15to3_15), .in_c(matrixC2_15), .out_a(out_a_3_15_NC), .out_a_chain(a3_15to3_16), .out_b(b3_15to4_15), .out_b0(b3_15to4_15_ping), .out_b1(b3_15to4_15_pong), .out_c(matrixC3_15), .b_data_valid_ping(b_data_valid_ping_delay3_15), .b_data_valid_pong(b_data_valid_pong_delay3_15), .mode(1'b0)); +processing_element pe3_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_3_16_NC), .in_a_chain(a3_15to3_16), .in_b(b2_16to3_16), .in_c(matrixC2_16), .out_a(out_a_3_16_NC), .out_a_chain(a3_16to3_17), .out_b(b3_16to4_16), .out_b0(b3_16to4_16_ping), .out_b1(b3_16to4_16_pong), .out_c(matrixC3_16), .b_data_valid_ping(b_data_valid_ping_delay3_16), .b_data_valid_pong(b_data_valid_pong_delay3_16), .mode(1'b0)); +processing_element pe3_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_3_17_NC), .in_a_chain(a3_16to3_17), .in_b(b2_17to3_17), .in_c(matrixC2_17), .out_a(out_a_3_17_NC), .out_a_chain(a3_17to3_18), .out_b(b3_17to4_17), .out_b0(b3_17to4_17_ping), .out_b1(b3_17to4_17_pong), .out_c(matrixC3_17), .b_data_valid_ping(b_data_valid_ping_delay3_17), .b_data_valid_pong(b_data_valid_pong_delay3_17), .mode(1'b0)); +processing_element pe3_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_3_18_NC), .in_a_chain(a3_17to3_18), .in_b(b2_18to3_18), .in_c(matrixC2_18), .out_a(out_a_3_18_NC), .out_a_chain(a3_18to3_19), .out_b(b3_18to4_18), .out_b0(b3_18to4_18_ping), .out_b1(b3_18to4_18_pong), .out_c(matrixC3_18), .b_data_valid_ping(b_data_valid_ping_delay3_18), .b_data_valid_pong(b_data_valid_pong_delay3_18), .mode(1'b0)); +processing_element pe3_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_3_19_NC), .in_a_chain(a3_18to3_19), .in_b(b2_19to3_19), .in_c(matrixC2_19), .out_a(out_a_3_19_NC), .out_a_chain(a3_19to3_20), .out_b(b3_19to4_19), .out_b0(b3_19to4_19_ping), .out_b1(b3_19to4_19_pong), .out_c(matrixC3_19), .b_data_valid_ping(b_data_valid_ping_delay3_19), .b_data_valid_pong(b_data_valid_pong_delay3_19), .mode(1'b0)); +processing_element pe3_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_3_20_NC), .in_a_chain(a3_19to3_20), .in_b(b2_20to3_20), .in_c(matrixC2_20), .out_a(out_a_3_20_NC), .out_a_chain(a3_20to3_21), .out_b(b3_20to4_20), .out_b0(b3_20to4_20_ping), .out_b1(b3_20to4_20_pong), .out_c(matrixC3_20), .b_data_valid_ping(b_data_valid_ping_delay3_20), .b_data_valid_pong(b_data_valid_pong_delay3_20), .mode(1'b0)); +processing_element pe3_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_3_21_NC), .in_a_chain(a3_20to3_21), .in_b(b2_21to3_21), .in_c(matrixC2_21), .out_a(out_a_3_21_NC), .out_a_chain(a3_21to3_22), .out_b(b3_21to4_21), .out_b0(b3_21to4_21_ping), .out_b1(b3_21to4_21_pong), .out_c(matrixC3_21), .b_data_valid_ping(b_data_valid_ping_delay3_21), .b_data_valid_pong(b_data_valid_pong_delay3_21), .mode(1'b0)); +processing_element pe3_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_3_22_NC), .in_a_chain(a3_21to3_22), .in_b(b2_22to3_22), .in_c(matrixC2_22), .out_a(out_a_3_22_NC), .out_a_chain(a3_22to3_23), .out_b(b3_22to4_22), .out_b0(b3_22to4_22_ping), .out_b1(b3_22to4_22_pong), .out_c(matrixC3_22), .b_data_valid_ping(b_data_valid_ping_delay3_22), .b_data_valid_pong(b_data_valid_pong_delay3_22), .mode(1'b0)); +processing_element pe3_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_3_23_NC), .in_a_chain(a3_22to3_23), .in_b(b2_23to3_23), .in_c(matrixC2_23), .out_a(out_a_3_23_NC), .out_a_chain(a3_23to3_24), .out_b(b3_23to4_23), .out_b0(b3_23to4_23_ping), .out_b1(b3_23to4_23_pong), .out_c(matrixC3_23), .b_data_valid_ping(b_data_valid_ping_delay3_23), .b_data_valid_pong(b_data_valid_pong_delay3_23), .mode(1'b0)); +processing_element pe3_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_3_24_NC), .in_a_chain(a3_23to3_24), .in_b(b2_24to3_24), .in_c(matrixC2_24), .out_a(out_a_3_24_NC), .out_a_chain(a3_24to3_25), .out_b(b3_24to4_24), .out_b0(b3_24to4_24_ping), .out_b1(b3_24to4_24_pong), .out_c(matrixC3_24), .b_data_valid_ping(b_data_valid_ping_delay3_24), .b_data_valid_pong(b_data_valid_pong_delay3_24), .mode(1'b0)); +processing_element pe3_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_3_25_NC), .in_a_chain(a3_24to3_25), .in_b(b2_25to3_25), .in_c(matrixC2_25), .out_a(out_a_3_25_NC), .out_a_chain(a3_25to3_26), .out_b(b3_25to4_25), .out_b0(b3_25to4_25_ping), .out_b1(b3_25to4_25_pong), .out_c(matrixC3_25), .b_data_valid_ping(b_data_valid_ping_delay3_25), .b_data_valid_pong(b_data_valid_pong_delay3_25), .mode(1'b0)); +processing_element pe3_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_3_26_NC), .in_a_chain(a3_25to3_26), .in_b(b2_26to3_26), .in_c(matrixC2_26), .out_a(out_a_3_26_NC), .out_a_chain(a3_26to3_27), .out_b(b3_26to4_26), .out_b0(b3_26to4_26_ping), .out_b1(b3_26to4_26_pong), .out_c(matrixC3_26), .b_data_valid_ping(b_data_valid_ping_delay3_26), .b_data_valid_pong(b_data_valid_pong_delay3_26), .mode(1'b0)); +processing_element pe3_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_3_27_NC), .in_a_chain(a3_26to3_27), .in_b(b2_27to3_27), .in_c(matrixC2_27), .out_a(out_a_3_27_NC), .out_a_chain(a3_27to3_28), .out_b(b3_27to4_27), .out_b0(b3_27to4_27_ping), .out_b1(b3_27to4_27_pong), .out_c(matrixC3_27), .b_data_valid_ping(b_data_valid_ping_delay3_27), .b_data_valid_pong(b_data_valid_pong_delay3_27), .mode(1'b0)); +processing_element pe3_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_3_28_NC), .in_a_chain(a3_27to3_28), .in_b(b2_28to3_28), .in_c(matrixC2_28), .out_a(out_a_3_28_NC), .out_a_chain(a3_28to3_29), .out_b(b3_28to4_28), .out_b0(b3_28to4_28_ping), .out_b1(b3_28to4_28_pong), .out_c(matrixC3_28), .b_data_valid_ping(b_data_valid_ping_delay3_28), .b_data_valid_pong(b_data_valid_pong_delay3_28), .mode(1'b0)); +processing_element pe3_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_3_29_NC), .in_a_chain(a3_28to3_29), .in_b(b2_29to3_29), .in_c(matrixC2_29), .out_a(out_a_3_29_NC), .out_a_chain(a3_29to3_30), .out_b(b3_29to4_29), .out_b0(b3_29to4_29_ping), .out_b1(b3_29to4_29_pong), .out_c(matrixC3_29), .b_data_valid_ping(b_data_valid_ping_delay3_29), .b_data_valid_pong(b_data_valid_pong_delay3_29), .mode(1'b0)); +processing_element pe3_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_3_30_NC), .in_a_chain(a3_29to3_30), .in_b(b2_30to3_30), .in_c(matrixC2_30), .out_a(out_a_3_30_NC), .out_a_chain(a3_30to3_31), .out_b(b3_30to4_30), .out_b0(b3_30to4_30_ping), .out_b1(b3_30to4_30_pong), .out_c(matrixC3_30), .b_data_valid_ping(b_data_valid_ping_delay3_30), .b_data_valid_pong(b_data_valid_pong_delay3_30), .mode(1'b0)); +processing_element pe3_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_3_31_NC), .in_a_chain(a3_30to3_31), .in_b(b2_31to3_31), .in_c(matrixC2_31), .out_a(out_a_3_31_NC), .out_a_chain(a3_31to3_32), .out_b(b3_31to4_31), .out_b0(b3_31to4_31_ping), .out_b1(b3_31to4_31_pong), .out_c(matrixC3_31), .b_data_valid_ping(b_data_valid_ping_delay3_31), .b_data_valid_pong(b_data_valid_pong_delay3_31), .mode(1'b0)); +processing_element pe4_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay4), .in_a(a4), .in_a_chain(in_a_chain_4_0_NC), .in_b(b3_0to4_0), .in_c(matrixC3_0), .out_a(out_a_4_0_NC), .out_a_chain(a4_0to4_1), .out_b(b4_0to5_0), .out_b0(b4_0to5_0_ping), .out_b1(b4_0to5_0_pong), .out_c(matrixC4_0), .b_data_valid_ping(b_data_valid_ping_delay4_0), .b_data_valid_pong(b_data_valid_pong_delay4_0), .mode(1'b1)); +processing_element pe4_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay5), .in_a(in_a_4_1_NC), .in_a_chain(a4_0to4_1), .in_b(b3_1to4_1), .in_c(matrixC3_1), .out_a(out_a_4_1_NC), .out_a_chain(a4_1to4_2), .out_b(b4_1to5_1), .out_b0(b4_1to5_1_ping), .out_b1(b4_1to5_1_pong), .out_c(matrixC4_1), .b_data_valid_ping(b_data_valid_ping_delay4_1), .b_data_valid_pong(b_data_valid_pong_delay4_1), .mode(1'b0)); +processing_element pe4_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay6), .in_a(in_a_4_2_NC), .in_a_chain(a4_1to4_2), .in_b(b3_2to4_2), .in_c(matrixC3_2), .out_a(out_a_4_2_NC), .out_a_chain(a4_2to4_3), .out_b(b4_2to5_2), .out_b0(b4_2to5_2_ping), .out_b1(b4_2to5_2_pong), .out_c(matrixC4_2), .b_data_valid_ping(b_data_valid_ping_delay4_2), .b_data_valid_pong(b_data_valid_pong_delay4_2), .mode(1'b0)); +processing_element pe4_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(in_a_4_3_NC), .in_a_chain(a4_2to4_3), .in_b(b3_3to4_3), .in_c(matrixC3_3), .out_a(out_a_4_3_NC), .out_a_chain(a4_3to4_4), .out_b(b4_3to5_3), .out_b0(b4_3to5_3_ping), .out_b1(b4_3to5_3_pong), .out_c(matrixC4_3), .b_data_valid_ping(b_data_valid_ping_delay4_3), .b_data_valid_pong(b_data_valid_pong_delay4_3), .mode(1'b0)); +processing_element pe4_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_4_4_NC), .in_a_chain(a4_3to4_4), .in_b(b3_4to4_4), .in_c(matrixC3_4), .out_a(out_a_4_4_NC), .out_a_chain(a4_4to4_5), .out_b(b4_4to5_4), .out_b0(b4_4to5_4_ping), .out_b1(b4_4to5_4_pong), .out_c(matrixC4_4), .b_data_valid_ping(b_data_valid_ping_delay4_4), .b_data_valid_pong(b_data_valid_pong_delay4_4), .mode(1'b0)); +processing_element pe4_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_4_5_NC), .in_a_chain(a4_4to4_5), .in_b(b3_5to4_5), .in_c(matrixC3_5), .out_a(out_a_4_5_NC), .out_a_chain(a4_5to4_6), .out_b(b4_5to5_5), .out_b0(b4_5to5_5_ping), .out_b1(b4_5to5_5_pong), .out_c(matrixC4_5), .b_data_valid_ping(b_data_valid_ping_delay4_5), .b_data_valid_pong(b_data_valid_pong_delay4_5), .mode(1'b0)); +processing_element pe4_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_4_6_NC), .in_a_chain(a4_5to4_6), .in_b(b3_6to4_6), .in_c(matrixC3_6), .out_a(out_a_4_6_NC), .out_a_chain(a4_6to4_7), .out_b(b4_6to5_6), .out_b0(b4_6to5_6_ping), .out_b1(b4_6to5_6_pong), .out_c(matrixC4_6), .b_data_valid_ping(b_data_valid_ping_delay4_6), .b_data_valid_pong(b_data_valid_pong_delay4_6), .mode(1'b0)); +processing_element pe4_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_4_7_NC), .in_a_chain(a4_6to4_7), .in_b(b3_7to4_7), .in_c(matrixC3_7), .out_a(out_a_4_7_NC), .out_a_chain(a4_7to4_8), .out_b(b4_7to5_7), .out_b0(b4_7to5_7_ping), .out_b1(b4_7to5_7_pong), .out_c(matrixC4_7), .b_data_valid_ping(b_data_valid_ping_delay4_7), .b_data_valid_pong(b_data_valid_pong_delay4_7), .mode(1'b0)); +processing_element pe4_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_4_8_NC), .in_a_chain(a4_7to4_8), .in_b(b3_8to4_8), .in_c(matrixC3_8), .out_a(out_a_4_8_NC), .out_a_chain(a4_8to4_9), .out_b(b4_8to5_8), .out_b0(b4_8to5_8_ping), .out_b1(b4_8to5_8_pong), .out_c(matrixC4_8), .b_data_valid_ping(b_data_valid_ping_delay4_8), .b_data_valid_pong(b_data_valid_pong_delay4_8), .mode(1'b0)); +processing_element pe4_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_4_9_NC), .in_a_chain(a4_8to4_9), .in_b(b3_9to4_9), .in_c(matrixC3_9), .out_a(out_a_4_9_NC), .out_a_chain(a4_9to4_10), .out_b(b4_9to5_9), .out_b0(b4_9to5_9_ping), .out_b1(b4_9to5_9_pong), .out_c(matrixC4_9), .b_data_valid_ping(b_data_valid_ping_delay4_9), .b_data_valid_pong(b_data_valid_pong_delay4_9), .mode(1'b0)); +processing_element pe4_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_4_10_NC), .in_a_chain(a4_9to4_10), .in_b(b3_10to4_10), .in_c(matrixC3_10), .out_a(out_a_4_10_NC), .out_a_chain(a4_10to4_11), .out_b(b4_10to5_10), .out_b0(b4_10to5_10_ping), .out_b1(b4_10to5_10_pong), .out_c(matrixC4_10), .b_data_valid_ping(b_data_valid_ping_delay4_10), .b_data_valid_pong(b_data_valid_pong_delay4_10), .mode(1'b0)); +processing_element pe4_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_4_11_NC), .in_a_chain(a4_10to4_11), .in_b(b3_11to4_11), .in_c(matrixC3_11), .out_a(out_a_4_11_NC), .out_a_chain(a4_11to4_12), .out_b(b4_11to5_11), .out_b0(b4_11to5_11_ping), .out_b1(b4_11to5_11_pong), .out_c(matrixC4_11), .b_data_valid_ping(b_data_valid_ping_delay4_11), .b_data_valid_pong(b_data_valid_pong_delay4_11), .mode(1'b0)); +processing_element pe4_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_4_12_NC), .in_a_chain(a4_11to4_12), .in_b(b3_12to4_12), .in_c(matrixC3_12), .out_a(out_a_4_12_NC), .out_a_chain(a4_12to4_13), .out_b(b4_12to5_12), .out_b0(b4_12to5_12_ping), .out_b1(b4_12to5_12_pong), .out_c(matrixC4_12), .b_data_valid_ping(b_data_valid_ping_delay4_12), .b_data_valid_pong(b_data_valid_pong_delay4_12), .mode(1'b0)); +processing_element pe4_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_4_13_NC), .in_a_chain(a4_12to4_13), .in_b(b3_13to4_13), .in_c(matrixC3_13), .out_a(out_a_4_13_NC), .out_a_chain(a4_13to4_14), .out_b(b4_13to5_13), .out_b0(b4_13to5_13_ping), .out_b1(b4_13to5_13_pong), .out_c(matrixC4_13), .b_data_valid_ping(b_data_valid_ping_delay4_13), .b_data_valid_pong(b_data_valid_pong_delay4_13), .mode(1'b0)); +processing_element pe4_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_4_14_NC), .in_a_chain(a4_13to4_14), .in_b(b3_14to4_14), .in_c(matrixC3_14), .out_a(out_a_4_14_NC), .out_a_chain(a4_14to4_15), .out_b(b4_14to5_14), .out_b0(b4_14to5_14_ping), .out_b1(b4_14to5_14_pong), .out_c(matrixC4_14), .b_data_valid_ping(b_data_valid_ping_delay4_14), .b_data_valid_pong(b_data_valid_pong_delay4_14), .mode(1'b0)); +processing_element pe4_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_4_15_NC), .in_a_chain(a4_14to4_15), .in_b(b3_15to4_15), .in_c(matrixC3_15), .out_a(out_a_4_15_NC), .out_a_chain(a4_15to4_16), .out_b(b4_15to5_15), .out_b0(b4_15to5_15_ping), .out_b1(b4_15to5_15_pong), .out_c(matrixC4_15), .b_data_valid_ping(b_data_valid_ping_delay4_15), .b_data_valid_pong(b_data_valid_pong_delay4_15), .mode(1'b0)); +processing_element pe4_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_4_16_NC), .in_a_chain(a4_15to4_16), .in_b(b3_16to4_16), .in_c(matrixC3_16), .out_a(out_a_4_16_NC), .out_a_chain(a4_16to4_17), .out_b(b4_16to5_16), .out_b0(b4_16to5_16_ping), .out_b1(b4_16to5_16_pong), .out_c(matrixC4_16), .b_data_valid_ping(b_data_valid_ping_delay4_16), .b_data_valid_pong(b_data_valid_pong_delay4_16), .mode(1'b0)); +processing_element pe4_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_4_17_NC), .in_a_chain(a4_16to4_17), .in_b(b3_17to4_17), .in_c(matrixC3_17), .out_a(out_a_4_17_NC), .out_a_chain(a4_17to4_18), .out_b(b4_17to5_17), .out_b0(b4_17to5_17_ping), .out_b1(b4_17to5_17_pong), .out_c(matrixC4_17), .b_data_valid_ping(b_data_valid_ping_delay4_17), .b_data_valid_pong(b_data_valid_pong_delay4_17), .mode(1'b0)); +processing_element pe4_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_4_18_NC), .in_a_chain(a4_17to4_18), .in_b(b3_18to4_18), .in_c(matrixC3_18), .out_a(out_a_4_18_NC), .out_a_chain(a4_18to4_19), .out_b(b4_18to5_18), .out_b0(b4_18to5_18_ping), .out_b1(b4_18to5_18_pong), .out_c(matrixC4_18), .b_data_valid_ping(b_data_valid_ping_delay4_18), .b_data_valid_pong(b_data_valid_pong_delay4_18), .mode(1'b0)); +processing_element pe4_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_4_19_NC), .in_a_chain(a4_18to4_19), .in_b(b3_19to4_19), .in_c(matrixC3_19), .out_a(out_a_4_19_NC), .out_a_chain(a4_19to4_20), .out_b(b4_19to5_19), .out_b0(b4_19to5_19_ping), .out_b1(b4_19to5_19_pong), .out_c(matrixC4_19), .b_data_valid_ping(b_data_valid_ping_delay4_19), .b_data_valid_pong(b_data_valid_pong_delay4_19), .mode(1'b0)); +processing_element pe4_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_4_20_NC), .in_a_chain(a4_19to4_20), .in_b(b3_20to4_20), .in_c(matrixC3_20), .out_a(out_a_4_20_NC), .out_a_chain(a4_20to4_21), .out_b(b4_20to5_20), .out_b0(b4_20to5_20_ping), .out_b1(b4_20to5_20_pong), .out_c(matrixC4_20), .b_data_valid_ping(b_data_valid_ping_delay4_20), .b_data_valid_pong(b_data_valid_pong_delay4_20), .mode(1'b0)); +processing_element pe4_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_4_21_NC), .in_a_chain(a4_20to4_21), .in_b(b3_21to4_21), .in_c(matrixC3_21), .out_a(out_a_4_21_NC), .out_a_chain(a4_21to4_22), .out_b(b4_21to5_21), .out_b0(b4_21to5_21_ping), .out_b1(b4_21to5_21_pong), .out_c(matrixC4_21), .b_data_valid_ping(b_data_valid_ping_delay4_21), .b_data_valid_pong(b_data_valid_pong_delay4_21), .mode(1'b0)); +processing_element pe4_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_4_22_NC), .in_a_chain(a4_21to4_22), .in_b(b3_22to4_22), .in_c(matrixC3_22), .out_a(out_a_4_22_NC), .out_a_chain(a4_22to4_23), .out_b(b4_22to5_22), .out_b0(b4_22to5_22_ping), .out_b1(b4_22to5_22_pong), .out_c(matrixC4_22), .b_data_valid_ping(b_data_valid_ping_delay4_22), .b_data_valid_pong(b_data_valid_pong_delay4_22), .mode(1'b0)); +processing_element pe4_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_4_23_NC), .in_a_chain(a4_22to4_23), .in_b(b3_23to4_23), .in_c(matrixC3_23), .out_a(out_a_4_23_NC), .out_a_chain(a4_23to4_24), .out_b(b4_23to5_23), .out_b0(b4_23to5_23_ping), .out_b1(b4_23to5_23_pong), .out_c(matrixC4_23), .b_data_valid_ping(b_data_valid_ping_delay4_23), .b_data_valid_pong(b_data_valid_pong_delay4_23), .mode(1'b0)); +processing_element pe4_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_4_24_NC), .in_a_chain(a4_23to4_24), .in_b(b3_24to4_24), .in_c(matrixC3_24), .out_a(out_a_4_24_NC), .out_a_chain(a4_24to4_25), .out_b(b4_24to5_24), .out_b0(b4_24to5_24_ping), .out_b1(b4_24to5_24_pong), .out_c(matrixC4_24), .b_data_valid_ping(b_data_valid_ping_delay4_24), .b_data_valid_pong(b_data_valid_pong_delay4_24), .mode(1'b0)); +processing_element pe4_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_4_25_NC), .in_a_chain(a4_24to4_25), .in_b(b3_25to4_25), .in_c(matrixC3_25), .out_a(out_a_4_25_NC), .out_a_chain(a4_25to4_26), .out_b(b4_25to5_25), .out_b0(b4_25to5_25_ping), .out_b1(b4_25to5_25_pong), .out_c(matrixC4_25), .b_data_valid_ping(b_data_valid_ping_delay4_25), .b_data_valid_pong(b_data_valid_pong_delay4_25), .mode(1'b0)); +processing_element pe4_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_4_26_NC), .in_a_chain(a4_25to4_26), .in_b(b3_26to4_26), .in_c(matrixC3_26), .out_a(out_a_4_26_NC), .out_a_chain(a4_26to4_27), .out_b(b4_26to5_26), .out_b0(b4_26to5_26_ping), .out_b1(b4_26to5_26_pong), .out_c(matrixC4_26), .b_data_valid_ping(b_data_valid_ping_delay4_26), .b_data_valid_pong(b_data_valid_pong_delay4_26), .mode(1'b0)); +processing_element pe4_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_4_27_NC), .in_a_chain(a4_26to4_27), .in_b(b3_27to4_27), .in_c(matrixC3_27), .out_a(out_a_4_27_NC), .out_a_chain(a4_27to4_28), .out_b(b4_27to5_27), .out_b0(b4_27to5_27_ping), .out_b1(b4_27to5_27_pong), .out_c(matrixC4_27), .b_data_valid_ping(b_data_valid_ping_delay4_27), .b_data_valid_pong(b_data_valid_pong_delay4_27), .mode(1'b0)); +processing_element pe4_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_4_28_NC), .in_a_chain(a4_27to4_28), .in_b(b3_28to4_28), .in_c(matrixC3_28), .out_a(out_a_4_28_NC), .out_a_chain(a4_28to4_29), .out_b(b4_28to5_28), .out_b0(b4_28to5_28_ping), .out_b1(b4_28to5_28_pong), .out_c(matrixC4_28), .b_data_valid_ping(b_data_valid_ping_delay4_28), .b_data_valid_pong(b_data_valid_pong_delay4_28), .mode(1'b0)); +processing_element pe4_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_4_29_NC), .in_a_chain(a4_28to4_29), .in_b(b3_29to4_29), .in_c(matrixC3_29), .out_a(out_a_4_29_NC), .out_a_chain(a4_29to4_30), .out_b(b4_29to5_29), .out_b0(b4_29to5_29_ping), .out_b1(b4_29to5_29_pong), .out_c(matrixC4_29), .b_data_valid_ping(b_data_valid_ping_delay4_29), .b_data_valid_pong(b_data_valid_pong_delay4_29), .mode(1'b0)); +processing_element pe4_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_4_30_NC), .in_a_chain(a4_29to4_30), .in_b(b3_30to4_30), .in_c(matrixC3_30), .out_a(out_a_4_30_NC), .out_a_chain(a4_30to4_31), .out_b(b4_30to5_30), .out_b0(b4_30to5_30_ping), .out_b1(b4_30to5_30_pong), .out_c(matrixC4_30), .b_data_valid_ping(b_data_valid_ping_delay4_30), .b_data_valid_pong(b_data_valid_pong_delay4_30), .mode(1'b0)); +processing_element pe4_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_4_31_NC), .in_a_chain(a4_30to4_31), .in_b(b3_31to4_31), .in_c(matrixC3_31), .out_a(out_a_4_31_NC), .out_a_chain(a4_31to4_32), .out_b(b4_31to5_31), .out_b0(b4_31to5_31_ping), .out_b1(b4_31to5_31_pong), .out_c(matrixC4_31), .b_data_valid_ping(b_data_valid_ping_delay4_31), .b_data_valid_pong(b_data_valid_pong_delay4_31), .mode(1'b0)); +processing_element pe5_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay5), .in_a(a5), .in_a_chain(in_a_chain_5_0_NC), .in_b(b4_0to5_0), .in_c(matrixC4_0), .out_a(out_a_5_0_NC), .out_a_chain(a5_0to5_1), .out_b(b5_0to6_0), .out_b0(b5_0to6_0_ping), .out_b1(b5_0to6_0_pong), .out_c(matrixC5_0), .b_data_valid_ping(b_data_valid_ping_delay5_0), .b_data_valid_pong(b_data_valid_pong_delay5_0), .mode(1'b1)); +processing_element pe5_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay6), .in_a(in_a_5_1_NC), .in_a_chain(a5_0to5_1), .in_b(b4_1to5_1), .in_c(matrixC4_1), .out_a(out_a_5_1_NC), .out_a_chain(a5_1to5_2), .out_b(b5_1to6_1), .out_b0(b5_1to6_1_ping), .out_b1(b5_1to6_1_pong), .out_c(matrixC5_1), .b_data_valid_ping(b_data_valid_ping_delay5_1), .b_data_valid_pong(b_data_valid_pong_delay5_1), .mode(1'b0)); +processing_element pe5_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(in_a_5_2_NC), .in_a_chain(a5_1to5_2), .in_b(b4_2to5_2), .in_c(matrixC4_2), .out_a(out_a_5_2_NC), .out_a_chain(a5_2to5_3), .out_b(b5_2to6_2), .out_b0(b5_2to6_2_ping), .out_b1(b5_2to6_2_pong), .out_c(matrixC5_2), .b_data_valid_ping(b_data_valid_ping_delay5_2), .b_data_valid_pong(b_data_valid_pong_delay5_2), .mode(1'b0)); +processing_element pe5_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_5_3_NC), .in_a_chain(a5_2to5_3), .in_b(b4_3to5_3), .in_c(matrixC4_3), .out_a(out_a_5_3_NC), .out_a_chain(a5_3to5_4), .out_b(b5_3to6_3), .out_b0(b5_3to6_3_ping), .out_b1(b5_3to6_3_pong), .out_c(matrixC5_3), .b_data_valid_ping(b_data_valid_ping_delay5_3), .b_data_valid_pong(b_data_valid_pong_delay5_3), .mode(1'b0)); +processing_element pe5_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_5_4_NC), .in_a_chain(a5_3to5_4), .in_b(b4_4to5_4), .in_c(matrixC4_4), .out_a(out_a_5_4_NC), .out_a_chain(a5_4to5_5), .out_b(b5_4to6_4), .out_b0(b5_4to6_4_ping), .out_b1(b5_4to6_4_pong), .out_c(matrixC5_4), .b_data_valid_ping(b_data_valid_ping_delay5_4), .b_data_valid_pong(b_data_valid_pong_delay5_4), .mode(1'b0)); +processing_element pe5_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_5_5_NC), .in_a_chain(a5_4to5_5), .in_b(b4_5to5_5), .in_c(matrixC4_5), .out_a(out_a_5_5_NC), .out_a_chain(a5_5to5_6), .out_b(b5_5to6_5), .out_b0(b5_5to6_5_ping), .out_b1(b5_5to6_5_pong), .out_c(matrixC5_5), .b_data_valid_ping(b_data_valid_ping_delay5_5), .b_data_valid_pong(b_data_valid_pong_delay5_5), .mode(1'b0)); +processing_element pe5_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_5_6_NC), .in_a_chain(a5_5to5_6), .in_b(b4_6to5_6), .in_c(matrixC4_6), .out_a(out_a_5_6_NC), .out_a_chain(a5_6to5_7), .out_b(b5_6to6_6), .out_b0(b5_6to6_6_ping), .out_b1(b5_6to6_6_pong), .out_c(matrixC5_6), .b_data_valid_ping(b_data_valid_ping_delay5_6), .b_data_valid_pong(b_data_valid_pong_delay5_6), .mode(1'b0)); +processing_element pe5_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_5_7_NC), .in_a_chain(a5_6to5_7), .in_b(b4_7to5_7), .in_c(matrixC4_7), .out_a(out_a_5_7_NC), .out_a_chain(a5_7to5_8), .out_b(b5_7to6_7), .out_b0(b5_7to6_7_ping), .out_b1(b5_7to6_7_pong), .out_c(matrixC5_7), .b_data_valid_ping(b_data_valid_ping_delay5_7), .b_data_valid_pong(b_data_valid_pong_delay5_7), .mode(1'b0)); +processing_element pe5_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_5_8_NC), .in_a_chain(a5_7to5_8), .in_b(b4_8to5_8), .in_c(matrixC4_8), .out_a(out_a_5_8_NC), .out_a_chain(a5_8to5_9), .out_b(b5_8to6_8), .out_b0(b5_8to6_8_ping), .out_b1(b5_8to6_8_pong), .out_c(matrixC5_8), .b_data_valid_ping(b_data_valid_ping_delay5_8), .b_data_valid_pong(b_data_valid_pong_delay5_8), .mode(1'b0)); +processing_element pe5_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_5_9_NC), .in_a_chain(a5_8to5_9), .in_b(b4_9to5_9), .in_c(matrixC4_9), .out_a(out_a_5_9_NC), .out_a_chain(a5_9to5_10), .out_b(b5_9to6_9), .out_b0(b5_9to6_9_ping), .out_b1(b5_9to6_9_pong), .out_c(matrixC5_9), .b_data_valid_ping(b_data_valid_ping_delay5_9), .b_data_valid_pong(b_data_valid_pong_delay5_9), .mode(1'b0)); +processing_element pe5_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_5_10_NC), .in_a_chain(a5_9to5_10), .in_b(b4_10to5_10), .in_c(matrixC4_10), .out_a(out_a_5_10_NC), .out_a_chain(a5_10to5_11), .out_b(b5_10to6_10), .out_b0(b5_10to6_10_ping), .out_b1(b5_10to6_10_pong), .out_c(matrixC5_10), .b_data_valid_ping(b_data_valid_ping_delay5_10), .b_data_valid_pong(b_data_valid_pong_delay5_10), .mode(1'b0)); +processing_element pe5_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_5_11_NC), .in_a_chain(a5_10to5_11), .in_b(b4_11to5_11), .in_c(matrixC4_11), .out_a(out_a_5_11_NC), .out_a_chain(a5_11to5_12), .out_b(b5_11to6_11), .out_b0(b5_11to6_11_ping), .out_b1(b5_11to6_11_pong), .out_c(matrixC5_11), .b_data_valid_ping(b_data_valid_ping_delay5_11), .b_data_valid_pong(b_data_valid_pong_delay5_11), .mode(1'b0)); +processing_element pe5_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_5_12_NC), .in_a_chain(a5_11to5_12), .in_b(b4_12to5_12), .in_c(matrixC4_12), .out_a(out_a_5_12_NC), .out_a_chain(a5_12to5_13), .out_b(b5_12to6_12), .out_b0(b5_12to6_12_ping), .out_b1(b5_12to6_12_pong), .out_c(matrixC5_12), .b_data_valid_ping(b_data_valid_ping_delay5_12), .b_data_valid_pong(b_data_valid_pong_delay5_12), .mode(1'b0)); +processing_element pe5_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_5_13_NC), .in_a_chain(a5_12to5_13), .in_b(b4_13to5_13), .in_c(matrixC4_13), .out_a(out_a_5_13_NC), .out_a_chain(a5_13to5_14), .out_b(b5_13to6_13), .out_b0(b5_13to6_13_ping), .out_b1(b5_13to6_13_pong), .out_c(matrixC5_13), .b_data_valid_ping(b_data_valid_ping_delay5_13), .b_data_valid_pong(b_data_valid_pong_delay5_13), .mode(1'b0)); +processing_element pe5_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_5_14_NC), .in_a_chain(a5_13to5_14), .in_b(b4_14to5_14), .in_c(matrixC4_14), .out_a(out_a_5_14_NC), .out_a_chain(a5_14to5_15), .out_b(b5_14to6_14), .out_b0(b5_14to6_14_ping), .out_b1(b5_14to6_14_pong), .out_c(matrixC5_14), .b_data_valid_ping(b_data_valid_ping_delay5_14), .b_data_valid_pong(b_data_valid_pong_delay5_14), .mode(1'b0)); +processing_element pe5_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_5_15_NC), .in_a_chain(a5_14to5_15), .in_b(b4_15to5_15), .in_c(matrixC4_15), .out_a(out_a_5_15_NC), .out_a_chain(a5_15to5_16), .out_b(b5_15to6_15), .out_b0(b5_15to6_15_ping), .out_b1(b5_15to6_15_pong), .out_c(matrixC5_15), .b_data_valid_ping(b_data_valid_ping_delay5_15), .b_data_valid_pong(b_data_valid_pong_delay5_15), .mode(1'b0)); +processing_element pe5_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_5_16_NC), .in_a_chain(a5_15to5_16), .in_b(b4_16to5_16), .in_c(matrixC4_16), .out_a(out_a_5_16_NC), .out_a_chain(a5_16to5_17), .out_b(b5_16to6_16), .out_b0(b5_16to6_16_ping), .out_b1(b5_16to6_16_pong), .out_c(matrixC5_16), .b_data_valid_ping(b_data_valid_ping_delay5_16), .b_data_valid_pong(b_data_valid_pong_delay5_16), .mode(1'b0)); +processing_element pe5_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_5_17_NC), .in_a_chain(a5_16to5_17), .in_b(b4_17to5_17), .in_c(matrixC4_17), .out_a(out_a_5_17_NC), .out_a_chain(a5_17to5_18), .out_b(b5_17to6_17), .out_b0(b5_17to6_17_ping), .out_b1(b5_17to6_17_pong), .out_c(matrixC5_17), .b_data_valid_ping(b_data_valid_ping_delay5_17), .b_data_valid_pong(b_data_valid_pong_delay5_17), .mode(1'b0)); +processing_element pe5_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_5_18_NC), .in_a_chain(a5_17to5_18), .in_b(b4_18to5_18), .in_c(matrixC4_18), .out_a(out_a_5_18_NC), .out_a_chain(a5_18to5_19), .out_b(b5_18to6_18), .out_b0(b5_18to6_18_ping), .out_b1(b5_18to6_18_pong), .out_c(matrixC5_18), .b_data_valid_ping(b_data_valid_ping_delay5_18), .b_data_valid_pong(b_data_valid_pong_delay5_18), .mode(1'b0)); +processing_element pe5_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_5_19_NC), .in_a_chain(a5_18to5_19), .in_b(b4_19to5_19), .in_c(matrixC4_19), .out_a(out_a_5_19_NC), .out_a_chain(a5_19to5_20), .out_b(b5_19to6_19), .out_b0(b5_19to6_19_ping), .out_b1(b5_19to6_19_pong), .out_c(matrixC5_19), .b_data_valid_ping(b_data_valid_ping_delay5_19), .b_data_valid_pong(b_data_valid_pong_delay5_19), .mode(1'b0)); +processing_element pe5_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_5_20_NC), .in_a_chain(a5_19to5_20), .in_b(b4_20to5_20), .in_c(matrixC4_20), .out_a(out_a_5_20_NC), .out_a_chain(a5_20to5_21), .out_b(b5_20to6_20), .out_b0(b5_20to6_20_ping), .out_b1(b5_20to6_20_pong), .out_c(matrixC5_20), .b_data_valid_ping(b_data_valid_ping_delay5_20), .b_data_valid_pong(b_data_valid_pong_delay5_20), .mode(1'b0)); +processing_element pe5_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_5_21_NC), .in_a_chain(a5_20to5_21), .in_b(b4_21to5_21), .in_c(matrixC4_21), .out_a(out_a_5_21_NC), .out_a_chain(a5_21to5_22), .out_b(b5_21to6_21), .out_b0(b5_21to6_21_ping), .out_b1(b5_21to6_21_pong), .out_c(matrixC5_21), .b_data_valid_ping(b_data_valid_ping_delay5_21), .b_data_valid_pong(b_data_valid_pong_delay5_21), .mode(1'b0)); +processing_element pe5_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_5_22_NC), .in_a_chain(a5_21to5_22), .in_b(b4_22to5_22), .in_c(matrixC4_22), .out_a(out_a_5_22_NC), .out_a_chain(a5_22to5_23), .out_b(b5_22to6_22), .out_b0(b5_22to6_22_ping), .out_b1(b5_22to6_22_pong), .out_c(matrixC5_22), .b_data_valid_ping(b_data_valid_ping_delay5_22), .b_data_valid_pong(b_data_valid_pong_delay5_22), .mode(1'b0)); +processing_element pe5_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_5_23_NC), .in_a_chain(a5_22to5_23), .in_b(b4_23to5_23), .in_c(matrixC4_23), .out_a(out_a_5_23_NC), .out_a_chain(a5_23to5_24), .out_b(b5_23to6_23), .out_b0(b5_23to6_23_ping), .out_b1(b5_23to6_23_pong), .out_c(matrixC5_23), .b_data_valid_ping(b_data_valid_ping_delay5_23), .b_data_valid_pong(b_data_valid_pong_delay5_23), .mode(1'b0)); +processing_element pe5_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_5_24_NC), .in_a_chain(a5_23to5_24), .in_b(b4_24to5_24), .in_c(matrixC4_24), .out_a(out_a_5_24_NC), .out_a_chain(a5_24to5_25), .out_b(b5_24to6_24), .out_b0(b5_24to6_24_ping), .out_b1(b5_24to6_24_pong), .out_c(matrixC5_24), .b_data_valid_ping(b_data_valid_ping_delay5_24), .b_data_valid_pong(b_data_valid_pong_delay5_24), .mode(1'b0)); +processing_element pe5_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_5_25_NC), .in_a_chain(a5_24to5_25), .in_b(b4_25to5_25), .in_c(matrixC4_25), .out_a(out_a_5_25_NC), .out_a_chain(a5_25to5_26), .out_b(b5_25to6_25), .out_b0(b5_25to6_25_ping), .out_b1(b5_25to6_25_pong), .out_c(matrixC5_25), .b_data_valid_ping(b_data_valid_ping_delay5_25), .b_data_valid_pong(b_data_valid_pong_delay5_25), .mode(1'b0)); +processing_element pe5_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_5_26_NC), .in_a_chain(a5_25to5_26), .in_b(b4_26to5_26), .in_c(matrixC4_26), .out_a(out_a_5_26_NC), .out_a_chain(a5_26to5_27), .out_b(b5_26to6_26), .out_b0(b5_26to6_26_ping), .out_b1(b5_26to6_26_pong), .out_c(matrixC5_26), .b_data_valid_ping(b_data_valid_ping_delay5_26), .b_data_valid_pong(b_data_valid_pong_delay5_26), .mode(1'b0)); +processing_element pe5_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_5_27_NC), .in_a_chain(a5_26to5_27), .in_b(b4_27to5_27), .in_c(matrixC4_27), .out_a(out_a_5_27_NC), .out_a_chain(a5_27to5_28), .out_b(b5_27to6_27), .out_b0(b5_27to6_27_ping), .out_b1(b5_27to6_27_pong), .out_c(matrixC5_27), .b_data_valid_ping(b_data_valid_ping_delay5_27), .b_data_valid_pong(b_data_valid_pong_delay5_27), .mode(1'b0)); +processing_element pe5_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_5_28_NC), .in_a_chain(a5_27to5_28), .in_b(b4_28to5_28), .in_c(matrixC4_28), .out_a(out_a_5_28_NC), .out_a_chain(a5_28to5_29), .out_b(b5_28to6_28), .out_b0(b5_28to6_28_ping), .out_b1(b5_28to6_28_pong), .out_c(matrixC5_28), .b_data_valid_ping(b_data_valid_ping_delay5_28), .b_data_valid_pong(b_data_valid_pong_delay5_28), .mode(1'b0)); +processing_element pe5_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_5_29_NC), .in_a_chain(a5_28to5_29), .in_b(b4_29to5_29), .in_c(matrixC4_29), .out_a(out_a_5_29_NC), .out_a_chain(a5_29to5_30), .out_b(b5_29to6_29), .out_b0(b5_29to6_29_ping), .out_b1(b5_29to6_29_pong), .out_c(matrixC5_29), .b_data_valid_ping(b_data_valid_ping_delay5_29), .b_data_valid_pong(b_data_valid_pong_delay5_29), .mode(1'b0)); +processing_element pe5_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_5_30_NC), .in_a_chain(a5_29to5_30), .in_b(b4_30to5_30), .in_c(matrixC4_30), .out_a(out_a_5_30_NC), .out_a_chain(a5_30to5_31), .out_b(b5_30to6_30), .out_b0(b5_30to6_30_ping), .out_b1(b5_30to6_30_pong), .out_c(matrixC5_30), .b_data_valid_ping(b_data_valid_ping_delay5_30), .b_data_valid_pong(b_data_valid_pong_delay5_30), .mode(1'b0)); +processing_element pe5_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_5_31_NC), .in_a_chain(a5_30to5_31), .in_b(b4_31to5_31), .in_c(matrixC4_31), .out_a(out_a_5_31_NC), .out_a_chain(a5_31to5_32), .out_b(b5_31to6_31), .out_b0(b5_31to6_31_ping), .out_b1(b5_31to6_31_pong), .out_c(matrixC5_31), .b_data_valid_ping(b_data_valid_ping_delay5_31), .b_data_valid_pong(b_data_valid_pong_delay5_31), .mode(1'b0)); +processing_element pe6_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay6), .in_a(a6), .in_a_chain(in_a_chain_6_0_NC), .in_b(b5_0to6_0), .in_c(matrixC5_0), .out_a(out_a_6_0_NC), .out_a_chain(a6_0to6_1), .out_b(b6_0to7_0), .out_b0(b6_0to7_0_ping), .out_b1(b6_0to7_0_pong), .out_c(matrixC6_0), .b_data_valid_ping(b_data_valid_ping_delay6_0), .b_data_valid_pong(b_data_valid_pong_delay6_0), .mode(1'b1)); +processing_element pe6_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(in_a_6_1_NC), .in_a_chain(a6_0to6_1), .in_b(b5_1to6_1), .in_c(matrixC5_1), .out_a(out_a_6_1_NC), .out_a_chain(a6_1to6_2), .out_b(b6_1to7_1), .out_b0(b6_1to7_1_ping), .out_b1(b6_1to7_1_pong), .out_c(matrixC6_1), .b_data_valid_ping(b_data_valid_ping_delay6_1), .b_data_valid_pong(b_data_valid_pong_delay6_1), .mode(1'b0)); +processing_element pe6_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_6_2_NC), .in_a_chain(a6_1to6_2), .in_b(b5_2to6_2), .in_c(matrixC5_2), .out_a(out_a_6_2_NC), .out_a_chain(a6_2to6_3), .out_b(b6_2to7_2), .out_b0(b6_2to7_2_ping), .out_b1(b6_2to7_2_pong), .out_c(matrixC6_2), .b_data_valid_ping(b_data_valid_ping_delay6_2), .b_data_valid_pong(b_data_valid_pong_delay6_2), .mode(1'b0)); +processing_element pe6_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_6_3_NC), .in_a_chain(a6_2to6_3), .in_b(b5_3to6_3), .in_c(matrixC5_3), .out_a(out_a_6_3_NC), .out_a_chain(a6_3to6_4), .out_b(b6_3to7_3), .out_b0(b6_3to7_3_ping), .out_b1(b6_3to7_3_pong), .out_c(matrixC6_3), .b_data_valid_ping(b_data_valid_ping_delay6_3), .b_data_valid_pong(b_data_valid_pong_delay6_3), .mode(1'b0)); +processing_element pe6_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_6_4_NC), .in_a_chain(a6_3to6_4), .in_b(b5_4to6_4), .in_c(matrixC5_4), .out_a(out_a_6_4_NC), .out_a_chain(a6_4to6_5), .out_b(b6_4to7_4), .out_b0(b6_4to7_4_ping), .out_b1(b6_4to7_4_pong), .out_c(matrixC6_4), .b_data_valid_ping(b_data_valid_ping_delay6_4), .b_data_valid_pong(b_data_valid_pong_delay6_4), .mode(1'b0)); +processing_element pe6_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_6_5_NC), .in_a_chain(a6_4to6_5), .in_b(b5_5to6_5), .in_c(matrixC5_5), .out_a(out_a_6_5_NC), .out_a_chain(a6_5to6_6), .out_b(b6_5to7_5), .out_b0(b6_5to7_5_ping), .out_b1(b6_5to7_5_pong), .out_c(matrixC6_5), .b_data_valid_ping(b_data_valid_ping_delay6_5), .b_data_valid_pong(b_data_valid_pong_delay6_5), .mode(1'b0)); +processing_element pe6_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_6_6_NC), .in_a_chain(a6_5to6_6), .in_b(b5_6to6_6), .in_c(matrixC5_6), .out_a(out_a_6_6_NC), .out_a_chain(a6_6to6_7), .out_b(b6_6to7_6), .out_b0(b6_6to7_6_ping), .out_b1(b6_6to7_6_pong), .out_c(matrixC6_6), .b_data_valid_ping(b_data_valid_ping_delay6_6), .b_data_valid_pong(b_data_valid_pong_delay6_6), .mode(1'b0)); +processing_element pe6_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_6_7_NC), .in_a_chain(a6_6to6_7), .in_b(b5_7to6_7), .in_c(matrixC5_7), .out_a(out_a_6_7_NC), .out_a_chain(a6_7to6_8), .out_b(b6_7to7_7), .out_b0(b6_7to7_7_ping), .out_b1(b6_7to7_7_pong), .out_c(matrixC6_7), .b_data_valid_ping(b_data_valid_ping_delay6_7), .b_data_valid_pong(b_data_valid_pong_delay6_7), .mode(1'b0)); +processing_element pe6_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_6_8_NC), .in_a_chain(a6_7to6_8), .in_b(b5_8to6_8), .in_c(matrixC5_8), .out_a(out_a_6_8_NC), .out_a_chain(a6_8to6_9), .out_b(b6_8to7_8), .out_b0(b6_8to7_8_ping), .out_b1(b6_8to7_8_pong), .out_c(matrixC6_8), .b_data_valid_ping(b_data_valid_ping_delay6_8), .b_data_valid_pong(b_data_valid_pong_delay6_8), .mode(1'b0)); +processing_element pe6_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_6_9_NC), .in_a_chain(a6_8to6_9), .in_b(b5_9to6_9), .in_c(matrixC5_9), .out_a(out_a_6_9_NC), .out_a_chain(a6_9to6_10), .out_b(b6_9to7_9), .out_b0(b6_9to7_9_ping), .out_b1(b6_9to7_9_pong), .out_c(matrixC6_9), .b_data_valid_ping(b_data_valid_ping_delay6_9), .b_data_valid_pong(b_data_valid_pong_delay6_9), .mode(1'b0)); +processing_element pe6_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_6_10_NC), .in_a_chain(a6_9to6_10), .in_b(b5_10to6_10), .in_c(matrixC5_10), .out_a(out_a_6_10_NC), .out_a_chain(a6_10to6_11), .out_b(b6_10to7_10), .out_b0(b6_10to7_10_ping), .out_b1(b6_10to7_10_pong), .out_c(matrixC6_10), .b_data_valid_ping(b_data_valid_ping_delay6_10), .b_data_valid_pong(b_data_valid_pong_delay6_10), .mode(1'b0)); +processing_element pe6_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_6_11_NC), .in_a_chain(a6_10to6_11), .in_b(b5_11to6_11), .in_c(matrixC5_11), .out_a(out_a_6_11_NC), .out_a_chain(a6_11to6_12), .out_b(b6_11to7_11), .out_b0(b6_11to7_11_ping), .out_b1(b6_11to7_11_pong), .out_c(matrixC6_11), .b_data_valid_ping(b_data_valid_ping_delay6_11), .b_data_valid_pong(b_data_valid_pong_delay6_11), .mode(1'b0)); +processing_element pe6_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_6_12_NC), .in_a_chain(a6_11to6_12), .in_b(b5_12to6_12), .in_c(matrixC5_12), .out_a(out_a_6_12_NC), .out_a_chain(a6_12to6_13), .out_b(b6_12to7_12), .out_b0(b6_12to7_12_ping), .out_b1(b6_12to7_12_pong), .out_c(matrixC6_12), .b_data_valid_ping(b_data_valid_ping_delay6_12), .b_data_valid_pong(b_data_valid_pong_delay6_12), .mode(1'b0)); +processing_element pe6_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_6_13_NC), .in_a_chain(a6_12to6_13), .in_b(b5_13to6_13), .in_c(matrixC5_13), .out_a(out_a_6_13_NC), .out_a_chain(a6_13to6_14), .out_b(b6_13to7_13), .out_b0(b6_13to7_13_ping), .out_b1(b6_13to7_13_pong), .out_c(matrixC6_13), .b_data_valid_ping(b_data_valid_ping_delay6_13), .b_data_valid_pong(b_data_valid_pong_delay6_13), .mode(1'b0)); +processing_element pe6_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_6_14_NC), .in_a_chain(a6_13to6_14), .in_b(b5_14to6_14), .in_c(matrixC5_14), .out_a(out_a_6_14_NC), .out_a_chain(a6_14to6_15), .out_b(b6_14to7_14), .out_b0(b6_14to7_14_ping), .out_b1(b6_14to7_14_pong), .out_c(matrixC6_14), .b_data_valid_ping(b_data_valid_ping_delay6_14), .b_data_valid_pong(b_data_valid_pong_delay6_14), .mode(1'b0)); +processing_element pe6_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_6_15_NC), .in_a_chain(a6_14to6_15), .in_b(b5_15to6_15), .in_c(matrixC5_15), .out_a(out_a_6_15_NC), .out_a_chain(a6_15to6_16), .out_b(b6_15to7_15), .out_b0(b6_15to7_15_ping), .out_b1(b6_15to7_15_pong), .out_c(matrixC6_15), .b_data_valid_ping(b_data_valid_ping_delay6_15), .b_data_valid_pong(b_data_valid_pong_delay6_15), .mode(1'b0)); +processing_element pe6_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_6_16_NC), .in_a_chain(a6_15to6_16), .in_b(b5_16to6_16), .in_c(matrixC5_16), .out_a(out_a_6_16_NC), .out_a_chain(a6_16to6_17), .out_b(b6_16to7_16), .out_b0(b6_16to7_16_ping), .out_b1(b6_16to7_16_pong), .out_c(matrixC6_16), .b_data_valid_ping(b_data_valid_ping_delay6_16), .b_data_valid_pong(b_data_valid_pong_delay6_16), .mode(1'b0)); +processing_element pe6_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_6_17_NC), .in_a_chain(a6_16to6_17), .in_b(b5_17to6_17), .in_c(matrixC5_17), .out_a(out_a_6_17_NC), .out_a_chain(a6_17to6_18), .out_b(b6_17to7_17), .out_b0(b6_17to7_17_ping), .out_b1(b6_17to7_17_pong), .out_c(matrixC6_17), .b_data_valid_ping(b_data_valid_ping_delay6_17), .b_data_valid_pong(b_data_valid_pong_delay6_17), .mode(1'b0)); +processing_element pe6_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_6_18_NC), .in_a_chain(a6_17to6_18), .in_b(b5_18to6_18), .in_c(matrixC5_18), .out_a(out_a_6_18_NC), .out_a_chain(a6_18to6_19), .out_b(b6_18to7_18), .out_b0(b6_18to7_18_ping), .out_b1(b6_18to7_18_pong), .out_c(matrixC6_18), .b_data_valid_ping(b_data_valid_ping_delay6_18), .b_data_valid_pong(b_data_valid_pong_delay6_18), .mode(1'b0)); +processing_element pe6_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_6_19_NC), .in_a_chain(a6_18to6_19), .in_b(b5_19to6_19), .in_c(matrixC5_19), .out_a(out_a_6_19_NC), .out_a_chain(a6_19to6_20), .out_b(b6_19to7_19), .out_b0(b6_19to7_19_ping), .out_b1(b6_19to7_19_pong), .out_c(matrixC6_19), .b_data_valid_ping(b_data_valid_ping_delay6_19), .b_data_valid_pong(b_data_valid_pong_delay6_19), .mode(1'b0)); +processing_element pe6_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_6_20_NC), .in_a_chain(a6_19to6_20), .in_b(b5_20to6_20), .in_c(matrixC5_20), .out_a(out_a_6_20_NC), .out_a_chain(a6_20to6_21), .out_b(b6_20to7_20), .out_b0(b6_20to7_20_ping), .out_b1(b6_20to7_20_pong), .out_c(matrixC6_20), .b_data_valid_ping(b_data_valid_ping_delay6_20), .b_data_valid_pong(b_data_valid_pong_delay6_20), .mode(1'b0)); +processing_element pe6_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_6_21_NC), .in_a_chain(a6_20to6_21), .in_b(b5_21to6_21), .in_c(matrixC5_21), .out_a(out_a_6_21_NC), .out_a_chain(a6_21to6_22), .out_b(b6_21to7_21), .out_b0(b6_21to7_21_ping), .out_b1(b6_21to7_21_pong), .out_c(matrixC6_21), .b_data_valid_ping(b_data_valid_ping_delay6_21), .b_data_valid_pong(b_data_valid_pong_delay6_21), .mode(1'b0)); +processing_element pe6_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_6_22_NC), .in_a_chain(a6_21to6_22), .in_b(b5_22to6_22), .in_c(matrixC5_22), .out_a(out_a_6_22_NC), .out_a_chain(a6_22to6_23), .out_b(b6_22to7_22), .out_b0(b6_22to7_22_ping), .out_b1(b6_22to7_22_pong), .out_c(matrixC6_22), .b_data_valid_ping(b_data_valid_ping_delay6_22), .b_data_valid_pong(b_data_valid_pong_delay6_22), .mode(1'b0)); +processing_element pe6_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_6_23_NC), .in_a_chain(a6_22to6_23), .in_b(b5_23to6_23), .in_c(matrixC5_23), .out_a(out_a_6_23_NC), .out_a_chain(a6_23to6_24), .out_b(b6_23to7_23), .out_b0(b6_23to7_23_ping), .out_b1(b6_23to7_23_pong), .out_c(matrixC6_23), .b_data_valid_ping(b_data_valid_ping_delay6_23), .b_data_valid_pong(b_data_valid_pong_delay6_23), .mode(1'b0)); +processing_element pe6_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_6_24_NC), .in_a_chain(a6_23to6_24), .in_b(b5_24to6_24), .in_c(matrixC5_24), .out_a(out_a_6_24_NC), .out_a_chain(a6_24to6_25), .out_b(b6_24to7_24), .out_b0(b6_24to7_24_ping), .out_b1(b6_24to7_24_pong), .out_c(matrixC6_24), .b_data_valid_ping(b_data_valid_ping_delay6_24), .b_data_valid_pong(b_data_valid_pong_delay6_24), .mode(1'b0)); +processing_element pe6_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_6_25_NC), .in_a_chain(a6_24to6_25), .in_b(b5_25to6_25), .in_c(matrixC5_25), .out_a(out_a_6_25_NC), .out_a_chain(a6_25to6_26), .out_b(b6_25to7_25), .out_b0(b6_25to7_25_ping), .out_b1(b6_25to7_25_pong), .out_c(matrixC6_25), .b_data_valid_ping(b_data_valid_ping_delay6_25), .b_data_valid_pong(b_data_valid_pong_delay6_25), .mode(1'b0)); +processing_element pe6_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_6_26_NC), .in_a_chain(a6_25to6_26), .in_b(b5_26to6_26), .in_c(matrixC5_26), .out_a(out_a_6_26_NC), .out_a_chain(a6_26to6_27), .out_b(b6_26to7_26), .out_b0(b6_26to7_26_ping), .out_b1(b6_26to7_26_pong), .out_c(matrixC6_26), .b_data_valid_ping(b_data_valid_ping_delay6_26), .b_data_valid_pong(b_data_valid_pong_delay6_26), .mode(1'b0)); +processing_element pe6_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_6_27_NC), .in_a_chain(a6_26to6_27), .in_b(b5_27to6_27), .in_c(matrixC5_27), .out_a(out_a_6_27_NC), .out_a_chain(a6_27to6_28), .out_b(b6_27to7_27), .out_b0(b6_27to7_27_ping), .out_b1(b6_27to7_27_pong), .out_c(matrixC6_27), .b_data_valid_ping(b_data_valid_ping_delay6_27), .b_data_valid_pong(b_data_valid_pong_delay6_27), .mode(1'b0)); +processing_element pe6_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_6_28_NC), .in_a_chain(a6_27to6_28), .in_b(b5_28to6_28), .in_c(matrixC5_28), .out_a(out_a_6_28_NC), .out_a_chain(a6_28to6_29), .out_b(b6_28to7_28), .out_b0(b6_28to7_28_ping), .out_b1(b6_28to7_28_pong), .out_c(matrixC6_28), .b_data_valid_ping(b_data_valid_ping_delay6_28), .b_data_valid_pong(b_data_valid_pong_delay6_28), .mode(1'b0)); +processing_element pe6_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_6_29_NC), .in_a_chain(a6_28to6_29), .in_b(b5_29to6_29), .in_c(matrixC5_29), .out_a(out_a_6_29_NC), .out_a_chain(a6_29to6_30), .out_b(b6_29to7_29), .out_b0(b6_29to7_29_ping), .out_b1(b6_29to7_29_pong), .out_c(matrixC6_29), .b_data_valid_ping(b_data_valid_ping_delay6_29), .b_data_valid_pong(b_data_valid_pong_delay6_29), .mode(1'b0)); +processing_element pe6_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_6_30_NC), .in_a_chain(a6_29to6_30), .in_b(b5_30to6_30), .in_c(matrixC5_30), .out_a(out_a_6_30_NC), .out_a_chain(a6_30to6_31), .out_b(b6_30to7_30), .out_b0(b6_30to7_30_ping), .out_b1(b6_30to7_30_pong), .out_c(matrixC6_30), .b_data_valid_ping(b_data_valid_ping_delay6_30), .b_data_valid_pong(b_data_valid_pong_delay6_30), .mode(1'b0)); +processing_element pe6_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_6_31_NC), .in_a_chain(a6_30to6_31), .in_b(b5_31to6_31), .in_c(matrixC5_31), .out_a(out_a_6_31_NC), .out_a_chain(a6_31to6_32), .out_b(b6_31to7_31), .out_b0(b6_31to7_31_ping), .out_b1(b6_31to7_31_pong), .out_c(matrixC6_31), .b_data_valid_ping(b_data_valid_ping_delay6_31), .b_data_valid_pong(b_data_valid_pong_delay6_31), .mode(1'b0)); +processing_element pe7_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(a7), .in_a_chain(in_a_chain_7_0_NC), .in_b(b6_0to7_0), .in_c(matrixC6_0), .out_a(out_a_7_0_NC), .out_a_chain(a7_0to7_1), .out_b(b7_0to8_0), .out_b0(b7_0to8_0_ping), .out_b1(b7_0to8_0_pong), .out_c(matrixC7_0), .b_data_valid_ping(b_data_valid_ping_delay7_0), .b_data_valid_pong(b_data_valid_pong_delay7_0), .mode(1'b1)); +processing_element pe7_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_7_1_NC), .in_a_chain(a7_0to7_1), .in_b(b6_1to7_1), .in_c(matrixC6_1), .out_a(out_a_7_1_NC), .out_a_chain(a7_1to7_2), .out_b(b7_1to8_1), .out_b0(b7_1to8_1_ping), .out_b1(b7_1to8_1_pong), .out_c(matrixC7_1), .b_data_valid_ping(b_data_valid_ping_delay7_1), .b_data_valid_pong(b_data_valid_pong_delay7_1), .mode(1'b0)); +processing_element pe7_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_7_2_NC), .in_a_chain(a7_1to7_2), .in_b(b6_2to7_2), .in_c(matrixC6_2), .out_a(out_a_7_2_NC), .out_a_chain(a7_2to7_3), .out_b(b7_2to8_2), .out_b0(b7_2to8_2_ping), .out_b1(b7_2to8_2_pong), .out_c(matrixC7_2), .b_data_valid_ping(b_data_valid_ping_delay7_2), .b_data_valid_pong(b_data_valid_pong_delay7_2), .mode(1'b0)); +processing_element pe7_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_7_3_NC), .in_a_chain(a7_2to7_3), .in_b(b6_3to7_3), .in_c(matrixC6_3), .out_a(out_a_7_3_NC), .out_a_chain(a7_3to7_4), .out_b(b7_3to8_3), .out_b0(b7_3to8_3_ping), .out_b1(b7_3to8_3_pong), .out_c(matrixC7_3), .b_data_valid_ping(b_data_valid_ping_delay7_3), .b_data_valid_pong(b_data_valid_pong_delay7_3), .mode(1'b0)); +processing_element pe7_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_7_4_NC), .in_a_chain(a7_3to7_4), .in_b(b6_4to7_4), .in_c(matrixC6_4), .out_a(out_a_7_4_NC), .out_a_chain(a7_4to7_5), .out_b(b7_4to8_4), .out_b0(b7_4to8_4_ping), .out_b1(b7_4to8_4_pong), .out_c(matrixC7_4), .b_data_valid_ping(b_data_valid_ping_delay7_4), .b_data_valid_pong(b_data_valid_pong_delay7_4), .mode(1'b0)); +processing_element pe7_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_7_5_NC), .in_a_chain(a7_4to7_5), .in_b(b6_5to7_5), .in_c(matrixC6_5), .out_a(out_a_7_5_NC), .out_a_chain(a7_5to7_6), .out_b(b7_5to8_5), .out_b0(b7_5to8_5_ping), .out_b1(b7_5to8_5_pong), .out_c(matrixC7_5), .b_data_valid_ping(b_data_valid_ping_delay7_5), .b_data_valid_pong(b_data_valid_pong_delay7_5), .mode(1'b0)); +processing_element pe7_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_7_6_NC), .in_a_chain(a7_5to7_6), .in_b(b6_6to7_6), .in_c(matrixC6_6), .out_a(out_a_7_6_NC), .out_a_chain(a7_6to7_7), .out_b(b7_6to8_6), .out_b0(b7_6to8_6_ping), .out_b1(b7_6to8_6_pong), .out_c(matrixC7_6), .b_data_valid_ping(b_data_valid_ping_delay7_6), .b_data_valid_pong(b_data_valid_pong_delay7_6), .mode(1'b0)); +processing_element pe7_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_7_7_NC), .in_a_chain(a7_6to7_7), .in_b(b6_7to7_7), .in_c(matrixC6_7), .out_a(out_a_7_7_NC), .out_a_chain(a7_7to7_8), .out_b(b7_7to8_7), .out_b0(b7_7to8_7_ping), .out_b1(b7_7to8_7_pong), .out_c(matrixC7_7), .b_data_valid_ping(b_data_valid_ping_delay7_7), .b_data_valid_pong(b_data_valid_pong_delay7_7), .mode(1'b0)); +processing_element pe7_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_7_8_NC), .in_a_chain(a7_7to7_8), .in_b(b6_8to7_8), .in_c(matrixC6_8), .out_a(out_a_7_8_NC), .out_a_chain(a7_8to7_9), .out_b(b7_8to8_8), .out_b0(b7_8to8_8_ping), .out_b1(b7_8to8_8_pong), .out_c(matrixC7_8), .b_data_valid_ping(b_data_valid_ping_delay7_8), .b_data_valid_pong(b_data_valid_pong_delay7_8), .mode(1'b0)); +processing_element pe7_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_7_9_NC), .in_a_chain(a7_8to7_9), .in_b(b6_9to7_9), .in_c(matrixC6_9), .out_a(out_a_7_9_NC), .out_a_chain(a7_9to7_10), .out_b(b7_9to8_9), .out_b0(b7_9to8_9_ping), .out_b1(b7_9to8_9_pong), .out_c(matrixC7_9), .b_data_valid_ping(b_data_valid_ping_delay7_9), .b_data_valid_pong(b_data_valid_pong_delay7_9), .mode(1'b0)); +processing_element pe7_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_7_10_NC), .in_a_chain(a7_9to7_10), .in_b(b6_10to7_10), .in_c(matrixC6_10), .out_a(out_a_7_10_NC), .out_a_chain(a7_10to7_11), .out_b(b7_10to8_10), .out_b0(b7_10to8_10_ping), .out_b1(b7_10to8_10_pong), .out_c(matrixC7_10), .b_data_valid_ping(b_data_valid_ping_delay7_10), .b_data_valid_pong(b_data_valid_pong_delay7_10), .mode(1'b0)); +processing_element pe7_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_7_11_NC), .in_a_chain(a7_10to7_11), .in_b(b6_11to7_11), .in_c(matrixC6_11), .out_a(out_a_7_11_NC), .out_a_chain(a7_11to7_12), .out_b(b7_11to8_11), .out_b0(b7_11to8_11_ping), .out_b1(b7_11to8_11_pong), .out_c(matrixC7_11), .b_data_valid_ping(b_data_valid_ping_delay7_11), .b_data_valid_pong(b_data_valid_pong_delay7_11), .mode(1'b0)); +processing_element pe7_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_7_12_NC), .in_a_chain(a7_11to7_12), .in_b(b6_12to7_12), .in_c(matrixC6_12), .out_a(out_a_7_12_NC), .out_a_chain(a7_12to7_13), .out_b(b7_12to8_12), .out_b0(b7_12to8_12_ping), .out_b1(b7_12to8_12_pong), .out_c(matrixC7_12), .b_data_valid_ping(b_data_valid_ping_delay7_12), .b_data_valid_pong(b_data_valid_pong_delay7_12), .mode(1'b0)); +processing_element pe7_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_7_13_NC), .in_a_chain(a7_12to7_13), .in_b(b6_13to7_13), .in_c(matrixC6_13), .out_a(out_a_7_13_NC), .out_a_chain(a7_13to7_14), .out_b(b7_13to8_13), .out_b0(b7_13to8_13_ping), .out_b1(b7_13to8_13_pong), .out_c(matrixC7_13), .b_data_valid_ping(b_data_valid_ping_delay7_13), .b_data_valid_pong(b_data_valid_pong_delay7_13), .mode(1'b0)); +processing_element pe7_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_7_14_NC), .in_a_chain(a7_13to7_14), .in_b(b6_14to7_14), .in_c(matrixC6_14), .out_a(out_a_7_14_NC), .out_a_chain(a7_14to7_15), .out_b(b7_14to8_14), .out_b0(b7_14to8_14_ping), .out_b1(b7_14to8_14_pong), .out_c(matrixC7_14), .b_data_valid_ping(b_data_valid_ping_delay7_14), .b_data_valid_pong(b_data_valid_pong_delay7_14), .mode(1'b0)); +processing_element pe7_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_7_15_NC), .in_a_chain(a7_14to7_15), .in_b(b6_15to7_15), .in_c(matrixC6_15), .out_a(out_a_7_15_NC), .out_a_chain(a7_15to7_16), .out_b(b7_15to8_15), .out_b0(b7_15to8_15_ping), .out_b1(b7_15to8_15_pong), .out_c(matrixC7_15), .b_data_valid_ping(b_data_valid_ping_delay7_15), .b_data_valid_pong(b_data_valid_pong_delay7_15), .mode(1'b0)); +processing_element pe7_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_7_16_NC), .in_a_chain(a7_15to7_16), .in_b(b6_16to7_16), .in_c(matrixC6_16), .out_a(out_a_7_16_NC), .out_a_chain(a7_16to7_17), .out_b(b7_16to8_16), .out_b0(b7_16to8_16_ping), .out_b1(b7_16to8_16_pong), .out_c(matrixC7_16), .b_data_valid_ping(b_data_valid_ping_delay7_16), .b_data_valid_pong(b_data_valid_pong_delay7_16), .mode(1'b0)); +processing_element pe7_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_7_17_NC), .in_a_chain(a7_16to7_17), .in_b(b6_17to7_17), .in_c(matrixC6_17), .out_a(out_a_7_17_NC), .out_a_chain(a7_17to7_18), .out_b(b7_17to8_17), .out_b0(b7_17to8_17_ping), .out_b1(b7_17to8_17_pong), .out_c(matrixC7_17), .b_data_valid_ping(b_data_valid_ping_delay7_17), .b_data_valid_pong(b_data_valid_pong_delay7_17), .mode(1'b0)); +processing_element pe7_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_7_18_NC), .in_a_chain(a7_17to7_18), .in_b(b6_18to7_18), .in_c(matrixC6_18), .out_a(out_a_7_18_NC), .out_a_chain(a7_18to7_19), .out_b(b7_18to8_18), .out_b0(b7_18to8_18_ping), .out_b1(b7_18to8_18_pong), .out_c(matrixC7_18), .b_data_valid_ping(b_data_valid_ping_delay7_18), .b_data_valid_pong(b_data_valid_pong_delay7_18), .mode(1'b0)); +processing_element pe7_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_7_19_NC), .in_a_chain(a7_18to7_19), .in_b(b6_19to7_19), .in_c(matrixC6_19), .out_a(out_a_7_19_NC), .out_a_chain(a7_19to7_20), .out_b(b7_19to8_19), .out_b0(b7_19to8_19_ping), .out_b1(b7_19to8_19_pong), .out_c(matrixC7_19), .b_data_valid_ping(b_data_valid_ping_delay7_19), .b_data_valid_pong(b_data_valid_pong_delay7_19), .mode(1'b0)); +processing_element pe7_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_7_20_NC), .in_a_chain(a7_19to7_20), .in_b(b6_20to7_20), .in_c(matrixC6_20), .out_a(out_a_7_20_NC), .out_a_chain(a7_20to7_21), .out_b(b7_20to8_20), .out_b0(b7_20to8_20_ping), .out_b1(b7_20to8_20_pong), .out_c(matrixC7_20), .b_data_valid_ping(b_data_valid_ping_delay7_20), .b_data_valid_pong(b_data_valid_pong_delay7_20), .mode(1'b0)); +processing_element pe7_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_7_21_NC), .in_a_chain(a7_20to7_21), .in_b(b6_21to7_21), .in_c(matrixC6_21), .out_a(out_a_7_21_NC), .out_a_chain(a7_21to7_22), .out_b(b7_21to8_21), .out_b0(b7_21to8_21_ping), .out_b1(b7_21to8_21_pong), .out_c(matrixC7_21), .b_data_valid_ping(b_data_valid_ping_delay7_21), .b_data_valid_pong(b_data_valid_pong_delay7_21), .mode(1'b0)); +processing_element pe7_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_7_22_NC), .in_a_chain(a7_21to7_22), .in_b(b6_22to7_22), .in_c(matrixC6_22), .out_a(out_a_7_22_NC), .out_a_chain(a7_22to7_23), .out_b(b7_22to8_22), .out_b0(b7_22to8_22_ping), .out_b1(b7_22to8_22_pong), .out_c(matrixC7_22), .b_data_valid_ping(b_data_valid_ping_delay7_22), .b_data_valid_pong(b_data_valid_pong_delay7_22), .mode(1'b0)); +processing_element pe7_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_7_23_NC), .in_a_chain(a7_22to7_23), .in_b(b6_23to7_23), .in_c(matrixC6_23), .out_a(out_a_7_23_NC), .out_a_chain(a7_23to7_24), .out_b(b7_23to8_23), .out_b0(b7_23to8_23_ping), .out_b1(b7_23to8_23_pong), .out_c(matrixC7_23), .b_data_valid_ping(b_data_valid_ping_delay7_23), .b_data_valid_pong(b_data_valid_pong_delay7_23), .mode(1'b0)); +processing_element pe7_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_7_24_NC), .in_a_chain(a7_23to7_24), .in_b(b6_24to7_24), .in_c(matrixC6_24), .out_a(out_a_7_24_NC), .out_a_chain(a7_24to7_25), .out_b(b7_24to8_24), .out_b0(b7_24to8_24_ping), .out_b1(b7_24to8_24_pong), .out_c(matrixC7_24), .b_data_valid_ping(b_data_valid_ping_delay7_24), .b_data_valid_pong(b_data_valid_pong_delay7_24), .mode(1'b0)); +processing_element pe7_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_7_25_NC), .in_a_chain(a7_24to7_25), .in_b(b6_25to7_25), .in_c(matrixC6_25), .out_a(out_a_7_25_NC), .out_a_chain(a7_25to7_26), .out_b(b7_25to8_25), .out_b0(b7_25to8_25_ping), .out_b1(b7_25to8_25_pong), .out_c(matrixC7_25), .b_data_valid_ping(b_data_valid_ping_delay7_25), .b_data_valid_pong(b_data_valid_pong_delay7_25), .mode(1'b0)); +processing_element pe7_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_7_26_NC), .in_a_chain(a7_25to7_26), .in_b(b6_26to7_26), .in_c(matrixC6_26), .out_a(out_a_7_26_NC), .out_a_chain(a7_26to7_27), .out_b(b7_26to8_26), .out_b0(b7_26to8_26_ping), .out_b1(b7_26to8_26_pong), .out_c(matrixC7_26), .b_data_valid_ping(b_data_valid_ping_delay7_26), .b_data_valid_pong(b_data_valid_pong_delay7_26), .mode(1'b0)); +processing_element pe7_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_7_27_NC), .in_a_chain(a7_26to7_27), .in_b(b6_27to7_27), .in_c(matrixC6_27), .out_a(out_a_7_27_NC), .out_a_chain(a7_27to7_28), .out_b(b7_27to8_27), .out_b0(b7_27to8_27_ping), .out_b1(b7_27to8_27_pong), .out_c(matrixC7_27), .b_data_valid_ping(b_data_valid_ping_delay7_27), .b_data_valid_pong(b_data_valid_pong_delay7_27), .mode(1'b0)); +processing_element pe7_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_7_28_NC), .in_a_chain(a7_27to7_28), .in_b(b6_28to7_28), .in_c(matrixC6_28), .out_a(out_a_7_28_NC), .out_a_chain(a7_28to7_29), .out_b(b7_28to8_28), .out_b0(b7_28to8_28_ping), .out_b1(b7_28to8_28_pong), .out_c(matrixC7_28), .b_data_valid_ping(b_data_valid_ping_delay7_28), .b_data_valid_pong(b_data_valid_pong_delay7_28), .mode(1'b0)); +processing_element pe7_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_7_29_NC), .in_a_chain(a7_28to7_29), .in_b(b6_29to7_29), .in_c(matrixC6_29), .out_a(out_a_7_29_NC), .out_a_chain(a7_29to7_30), .out_b(b7_29to8_29), .out_b0(b7_29to8_29_ping), .out_b1(b7_29to8_29_pong), .out_c(matrixC7_29), .b_data_valid_ping(b_data_valid_ping_delay7_29), .b_data_valid_pong(b_data_valid_pong_delay7_29), .mode(1'b0)); +processing_element pe7_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_7_30_NC), .in_a_chain(a7_29to7_30), .in_b(b6_30to7_30), .in_c(matrixC6_30), .out_a(out_a_7_30_NC), .out_a_chain(a7_30to7_31), .out_b(b7_30to8_30), .out_b0(b7_30to8_30_ping), .out_b1(b7_30to8_30_pong), .out_c(matrixC7_30), .b_data_valid_ping(b_data_valid_ping_delay7_30), .b_data_valid_pong(b_data_valid_pong_delay7_30), .mode(1'b0)); +processing_element pe7_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_7_31_NC), .in_a_chain(a7_30to7_31), .in_b(b6_31to7_31), .in_c(matrixC6_31), .out_a(out_a_7_31_NC), .out_a_chain(a7_31to7_32), .out_b(b7_31to8_31), .out_b0(b7_31to8_31_ping), .out_b1(b7_31to8_31_pong), .out_c(matrixC7_31), .b_data_valid_ping(b_data_valid_ping_delay7_31), .b_data_valid_pong(b_data_valid_pong_delay7_31), .mode(1'b0)); +processing_element pe8_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(a8), .in_a_chain(in_a_chain_8_0_NC), .in_b(b7_0to8_0), .in_c(matrixC7_0), .out_a(out_a_8_0_NC), .out_a_chain(a8_0to8_1), .out_b(b8_0to9_0), .out_b0(b8_0to9_0_ping), .out_b1(b8_0to9_0_pong), .out_c(matrixC8_0), .b_data_valid_ping(b_data_valid_ping_delay8_0), .b_data_valid_pong(b_data_valid_pong_delay8_0), .mode(1'b1)); +processing_element pe8_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_8_1_NC), .in_a_chain(a8_0to8_1), .in_b(b7_1to8_1), .in_c(matrixC7_1), .out_a(out_a_8_1_NC), .out_a_chain(a8_1to8_2), .out_b(b8_1to9_1), .out_b0(b8_1to9_1_ping), .out_b1(b8_1to9_1_pong), .out_c(matrixC8_1), .b_data_valid_ping(b_data_valid_ping_delay8_1), .b_data_valid_pong(b_data_valid_pong_delay8_1), .mode(1'b0)); +processing_element pe8_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_8_2_NC), .in_a_chain(a8_1to8_2), .in_b(b7_2to8_2), .in_c(matrixC7_2), .out_a(out_a_8_2_NC), .out_a_chain(a8_2to8_3), .out_b(b8_2to9_2), .out_b0(b8_2to9_2_ping), .out_b1(b8_2to9_2_pong), .out_c(matrixC8_2), .b_data_valid_ping(b_data_valid_ping_delay8_2), .b_data_valid_pong(b_data_valid_pong_delay8_2), .mode(1'b0)); +processing_element pe8_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_8_3_NC), .in_a_chain(a8_2to8_3), .in_b(b7_3to8_3), .in_c(matrixC7_3), .out_a(out_a_8_3_NC), .out_a_chain(a8_3to8_4), .out_b(b8_3to9_3), .out_b0(b8_3to9_3_ping), .out_b1(b8_3to9_3_pong), .out_c(matrixC8_3), .b_data_valid_ping(b_data_valid_ping_delay8_3), .b_data_valid_pong(b_data_valid_pong_delay8_3), .mode(1'b0)); +processing_element pe8_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_8_4_NC), .in_a_chain(a8_3to8_4), .in_b(b7_4to8_4), .in_c(matrixC7_4), .out_a(out_a_8_4_NC), .out_a_chain(a8_4to8_5), .out_b(b8_4to9_4), .out_b0(b8_4to9_4_ping), .out_b1(b8_4to9_4_pong), .out_c(matrixC8_4), .b_data_valid_ping(b_data_valid_ping_delay8_4), .b_data_valid_pong(b_data_valid_pong_delay8_4), .mode(1'b0)); +processing_element pe8_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_8_5_NC), .in_a_chain(a8_4to8_5), .in_b(b7_5to8_5), .in_c(matrixC7_5), .out_a(out_a_8_5_NC), .out_a_chain(a8_5to8_6), .out_b(b8_5to9_5), .out_b0(b8_5to9_5_ping), .out_b1(b8_5to9_5_pong), .out_c(matrixC8_5), .b_data_valid_ping(b_data_valid_ping_delay8_5), .b_data_valid_pong(b_data_valid_pong_delay8_5), .mode(1'b0)); +processing_element pe8_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_8_6_NC), .in_a_chain(a8_5to8_6), .in_b(b7_6to8_6), .in_c(matrixC7_6), .out_a(out_a_8_6_NC), .out_a_chain(a8_6to8_7), .out_b(b8_6to9_6), .out_b0(b8_6to9_6_ping), .out_b1(b8_6to9_6_pong), .out_c(matrixC8_6), .b_data_valid_ping(b_data_valid_ping_delay8_6), .b_data_valid_pong(b_data_valid_pong_delay8_6), .mode(1'b0)); +processing_element pe8_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_8_7_NC), .in_a_chain(a8_6to8_7), .in_b(b7_7to8_7), .in_c(matrixC7_7), .out_a(out_a_8_7_NC), .out_a_chain(a8_7to8_8), .out_b(b8_7to9_7), .out_b0(b8_7to9_7_ping), .out_b1(b8_7to9_7_pong), .out_c(matrixC8_7), .b_data_valid_ping(b_data_valid_ping_delay8_7), .b_data_valid_pong(b_data_valid_pong_delay8_7), .mode(1'b0)); +processing_element pe8_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_8_8_NC), .in_a_chain(a8_7to8_8), .in_b(b7_8to8_8), .in_c(matrixC7_8), .out_a(out_a_8_8_NC), .out_a_chain(a8_8to8_9), .out_b(b8_8to9_8), .out_b0(b8_8to9_8_ping), .out_b1(b8_8to9_8_pong), .out_c(matrixC8_8), .b_data_valid_ping(b_data_valid_ping_delay8_8), .b_data_valid_pong(b_data_valid_pong_delay8_8), .mode(1'b0)); +processing_element pe8_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_8_9_NC), .in_a_chain(a8_8to8_9), .in_b(b7_9to8_9), .in_c(matrixC7_9), .out_a(out_a_8_9_NC), .out_a_chain(a8_9to8_10), .out_b(b8_9to9_9), .out_b0(b8_9to9_9_ping), .out_b1(b8_9to9_9_pong), .out_c(matrixC8_9), .b_data_valid_ping(b_data_valid_ping_delay8_9), .b_data_valid_pong(b_data_valid_pong_delay8_9), .mode(1'b0)); +processing_element pe8_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_8_10_NC), .in_a_chain(a8_9to8_10), .in_b(b7_10to8_10), .in_c(matrixC7_10), .out_a(out_a_8_10_NC), .out_a_chain(a8_10to8_11), .out_b(b8_10to9_10), .out_b0(b8_10to9_10_ping), .out_b1(b8_10to9_10_pong), .out_c(matrixC8_10), .b_data_valid_ping(b_data_valid_ping_delay8_10), .b_data_valid_pong(b_data_valid_pong_delay8_10), .mode(1'b0)); +processing_element pe8_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_8_11_NC), .in_a_chain(a8_10to8_11), .in_b(b7_11to8_11), .in_c(matrixC7_11), .out_a(out_a_8_11_NC), .out_a_chain(a8_11to8_12), .out_b(b8_11to9_11), .out_b0(b8_11to9_11_ping), .out_b1(b8_11to9_11_pong), .out_c(matrixC8_11), .b_data_valid_ping(b_data_valid_ping_delay8_11), .b_data_valid_pong(b_data_valid_pong_delay8_11), .mode(1'b0)); +processing_element pe8_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_8_12_NC), .in_a_chain(a8_11to8_12), .in_b(b7_12to8_12), .in_c(matrixC7_12), .out_a(out_a_8_12_NC), .out_a_chain(a8_12to8_13), .out_b(b8_12to9_12), .out_b0(b8_12to9_12_ping), .out_b1(b8_12to9_12_pong), .out_c(matrixC8_12), .b_data_valid_ping(b_data_valid_ping_delay8_12), .b_data_valid_pong(b_data_valid_pong_delay8_12), .mode(1'b0)); +processing_element pe8_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_8_13_NC), .in_a_chain(a8_12to8_13), .in_b(b7_13to8_13), .in_c(matrixC7_13), .out_a(out_a_8_13_NC), .out_a_chain(a8_13to8_14), .out_b(b8_13to9_13), .out_b0(b8_13to9_13_ping), .out_b1(b8_13to9_13_pong), .out_c(matrixC8_13), .b_data_valid_ping(b_data_valid_ping_delay8_13), .b_data_valid_pong(b_data_valid_pong_delay8_13), .mode(1'b0)); +processing_element pe8_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_8_14_NC), .in_a_chain(a8_13to8_14), .in_b(b7_14to8_14), .in_c(matrixC7_14), .out_a(out_a_8_14_NC), .out_a_chain(a8_14to8_15), .out_b(b8_14to9_14), .out_b0(b8_14to9_14_ping), .out_b1(b8_14to9_14_pong), .out_c(matrixC8_14), .b_data_valid_ping(b_data_valid_ping_delay8_14), .b_data_valid_pong(b_data_valid_pong_delay8_14), .mode(1'b0)); +processing_element pe8_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_8_15_NC), .in_a_chain(a8_14to8_15), .in_b(b7_15to8_15), .in_c(matrixC7_15), .out_a(out_a_8_15_NC), .out_a_chain(a8_15to8_16), .out_b(b8_15to9_15), .out_b0(b8_15to9_15_ping), .out_b1(b8_15to9_15_pong), .out_c(matrixC8_15), .b_data_valid_ping(b_data_valid_ping_delay8_15), .b_data_valid_pong(b_data_valid_pong_delay8_15), .mode(1'b0)); +processing_element pe8_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_8_16_NC), .in_a_chain(a8_15to8_16), .in_b(b7_16to8_16), .in_c(matrixC7_16), .out_a(out_a_8_16_NC), .out_a_chain(a8_16to8_17), .out_b(b8_16to9_16), .out_b0(b8_16to9_16_ping), .out_b1(b8_16to9_16_pong), .out_c(matrixC8_16), .b_data_valid_ping(b_data_valid_ping_delay8_16), .b_data_valid_pong(b_data_valid_pong_delay8_16), .mode(1'b0)); +processing_element pe8_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_8_17_NC), .in_a_chain(a8_16to8_17), .in_b(b7_17to8_17), .in_c(matrixC7_17), .out_a(out_a_8_17_NC), .out_a_chain(a8_17to8_18), .out_b(b8_17to9_17), .out_b0(b8_17to9_17_ping), .out_b1(b8_17to9_17_pong), .out_c(matrixC8_17), .b_data_valid_ping(b_data_valid_ping_delay8_17), .b_data_valid_pong(b_data_valid_pong_delay8_17), .mode(1'b0)); +processing_element pe8_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_8_18_NC), .in_a_chain(a8_17to8_18), .in_b(b7_18to8_18), .in_c(matrixC7_18), .out_a(out_a_8_18_NC), .out_a_chain(a8_18to8_19), .out_b(b8_18to9_18), .out_b0(b8_18to9_18_ping), .out_b1(b8_18to9_18_pong), .out_c(matrixC8_18), .b_data_valid_ping(b_data_valid_ping_delay8_18), .b_data_valid_pong(b_data_valid_pong_delay8_18), .mode(1'b0)); +processing_element pe8_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_8_19_NC), .in_a_chain(a8_18to8_19), .in_b(b7_19to8_19), .in_c(matrixC7_19), .out_a(out_a_8_19_NC), .out_a_chain(a8_19to8_20), .out_b(b8_19to9_19), .out_b0(b8_19to9_19_ping), .out_b1(b8_19to9_19_pong), .out_c(matrixC8_19), .b_data_valid_ping(b_data_valid_ping_delay8_19), .b_data_valid_pong(b_data_valid_pong_delay8_19), .mode(1'b0)); +processing_element pe8_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_8_20_NC), .in_a_chain(a8_19to8_20), .in_b(b7_20to8_20), .in_c(matrixC7_20), .out_a(out_a_8_20_NC), .out_a_chain(a8_20to8_21), .out_b(b8_20to9_20), .out_b0(b8_20to9_20_ping), .out_b1(b8_20to9_20_pong), .out_c(matrixC8_20), .b_data_valid_ping(b_data_valid_ping_delay8_20), .b_data_valid_pong(b_data_valid_pong_delay8_20), .mode(1'b0)); +processing_element pe8_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_8_21_NC), .in_a_chain(a8_20to8_21), .in_b(b7_21to8_21), .in_c(matrixC7_21), .out_a(out_a_8_21_NC), .out_a_chain(a8_21to8_22), .out_b(b8_21to9_21), .out_b0(b8_21to9_21_ping), .out_b1(b8_21to9_21_pong), .out_c(matrixC8_21), .b_data_valid_ping(b_data_valid_ping_delay8_21), .b_data_valid_pong(b_data_valid_pong_delay8_21), .mode(1'b0)); +processing_element pe8_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_8_22_NC), .in_a_chain(a8_21to8_22), .in_b(b7_22to8_22), .in_c(matrixC7_22), .out_a(out_a_8_22_NC), .out_a_chain(a8_22to8_23), .out_b(b8_22to9_22), .out_b0(b8_22to9_22_ping), .out_b1(b8_22to9_22_pong), .out_c(matrixC8_22), .b_data_valid_ping(b_data_valid_ping_delay8_22), .b_data_valid_pong(b_data_valid_pong_delay8_22), .mode(1'b0)); +processing_element pe8_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_8_23_NC), .in_a_chain(a8_22to8_23), .in_b(b7_23to8_23), .in_c(matrixC7_23), .out_a(out_a_8_23_NC), .out_a_chain(a8_23to8_24), .out_b(b8_23to9_23), .out_b0(b8_23to9_23_ping), .out_b1(b8_23to9_23_pong), .out_c(matrixC8_23), .b_data_valid_ping(b_data_valid_ping_delay8_23), .b_data_valid_pong(b_data_valid_pong_delay8_23), .mode(1'b0)); +processing_element pe8_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_8_24_NC), .in_a_chain(a8_23to8_24), .in_b(b7_24to8_24), .in_c(matrixC7_24), .out_a(out_a_8_24_NC), .out_a_chain(a8_24to8_25), .out_b(b8_24to9_24), .out_b0(b8_24to9_24_ping), .out_b1(b8_24to9_24_pong), .out_c(matrixC8_24), .b_data_valid_ping(b_data_valid_ping_delay8_24), .b_data_valid_pong(b_data_valid_pong_delay8_24), .mode(1'b0)); +processing_element pe8_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_8_25_NC), .in_a_chain(a8_24to8_25), .in_b(b7_25to8_25), .in_c(matrixC7_25), .out_a(out_a_8_25_NC), .out_a_chain(a8_25to8_26), .out_b(b8_25to9_25), .out_b0(b8_25to9_25_ping), .out_b1(b8_25to9_25_pong), .out_c(matrixC8_25), .b_data_valid_ping(b_data_valid_ping_delay8_25), .b_data_valid_pong(b_data_valid_pong_delay8_25), .mode(1'b0)); +processing_element pe8_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_8_26_NC), .in_a_chain(a8_25to8_26), .in_b(b7_26to8_26), .in_c(matrixC7_26), .out_a(out_a_8_26_NC), .out_a_chain(a8_26to8_27), .out_b(b8_26to9_26), .out_b0(b8_26to9_26_ping), .out_b1(b8_26to9_26_pong), .out_c(matrixC8_26), .b_data_valid_ping(b_data_valid_ping_delay8_26), .b_data_valid_pong(b_data_valid_pong_delay8_26), .mode(1'b0)); +processing_element pe8_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_8_27_NC), .in_a_chain(a8_26to8_27), .in_b(b7_27to8_27), .in_c(matrixC7_27), .out_a(out_a_8_27_NC), .out_a_chain(a8_27to8_28), .out_b(b8_27to9_27), .out_b0(b8_27to9_27_ping), .out_b1(b8_27to9_27_pong), .out_c(matrixC8_27), .b_data_valid_ping(b_data_valid_ping_delay8_27), .b_data_valid_pong(b_data_valid_pong_delay8_27), .mode(1'b0)); +processing_element pe8_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_8_28_NC), .in_a_chain(a8_27to8_28), .in_b(b7_28to8_28), .in_c(matrixC7_28), .out_a(out_a_8_28_NC), .out_a_chain(a8_28to8_29), .out_b(b8_28to9_28), .out_b0(b8_28to9_28_ping), .out_b1(b8_28to9_28_pong), .out_c(matrixC8_28), .b_data_valid_ping(b_data_valid_ping_delay8_28), .b_data_valid_pong(b_data_valid_pong_delay8_28), .mode(1'b0)); +processing_element pe8_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_8_29_NC), .in_a_chain(a8_28to8_29), .in_b(b7_29to8_29), .in_c(matrixC7_29), .out_a(out_a_8_29_NC), .out_a_chain(a8_29to8_30), .out_b(b8_29to9_29), .out_b0(b8_29to9_29_ping), .out_b1(b8_29to9_29_pong), .out_c(matrixC8_29), .b_data_valid_ping(b_data_valid_ping_delay8_29), .b_data_valid_pong(b_data_valid_pong_delay8_29), .mode(1'b0)); +processing_element pe8_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_8_30_NC), .in_a_chain(a8_29to8_30), .in_b(b7_30to8_30), .in_c(matrixC7_30), .out_a(out_a_8_30_NC), .out_a_chain(a8_30to8_31), .out_b(b8_30to9_30), .out_b0(b8_30to9_30_ping), .out_b1(b8_30to9_30_pong), .out_c(matrixC8_30), .b_data_valid_ping(b_data_valid_ping_delay8_30), .b_data_valid_pong(b_data_valid_pong_delay8_30), .mode(1'b0)); +processing_element pe8_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_8_31_NC), .in_a_chain(a8_30to8_31), .in_b(b7_31to8_31), .in_c(matrixC7_31), .out_a(out_a_8_31_NC), .out_a_chain(a8_31to8_32), .out_b(b8_31to9_31), .out_b0(b8_31to9_31_ping), .out_b1(b8_31to9_31_pong), .out_c(matrixC8_31), .b_data_valid_ping(b_data_valid_ping_delay8_31), .b_data_valid_pong(b_data_valid_pong_delay8_31), .mode(1'b0)); +processing_element pe9_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(a9), .in_a_chain(in_a_chain_9_0_NC), .in_b(b8_0to9_0), .in_c(matrixC8_0), .out_a(out_a_9_0_NC), .out_a_chain(a9_0to9_1), .out_b(b9_0to10_0), .out_b0(b9_0to10_0_ping), .out_b1(b9_0to10_0_pong), .out_c(matrixC9_0), .b_data_valid_ping(b_data_valid_ping_delay9_0), .b_data_valid_pong(b_data_valid_pong_delay9_0), .mode(1'b1)); +processing_element pe9_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_9_1_NC), .in_a_chain(a9_0to9_1), .in_b(b8_1to9_1), .in_c(matrixC8_1), .out_a(out_a_9_1_NC), .out_a_chain(a9_1to9_2), .out_b(b9_1to10_1), .out_b0(b9_1to10_1_ping), .out_b1(b9_1to10_1_pong), .out_c(matrixC9_1), .b_data_valid_ping(b_data_valid_ping_delay9_1), .b_data_valid_pong(b_data_valid_pong_delay9_1), .mode(1'b0)); +processing_element pe9_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_9_2_NC), .in_a_chain(a9_1to9_2), .in_b(b8_2to9_2), .in_c(matrixC8_2), .out_a(out_a_9_2_NC), .out_a_chain(a9_2to9_3), .out_b(b9_2to10_2), .out_b0(b9_2to10_2_ping), .out_b1(b9_2to10_2_pong), .out_c(matrixC9_2), .b_data_valid_ping(b_data_valid_ping_delay9_2), .b_data_valid_pong(b_data_valid_pong_delay9_2), .mode(1'b0)); +processing_element pe9_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_9_3_NC), .in_a_chain(a9_2to9_3), .in_b(b8_3to9_3), .in_c(matrixC8_3), .out_a(out_a_9_3_NC), .out_a_chain(a9_3to9_4), .out_b(b9_3to10_3), .out_b0(b9_3to10_3_ping), .out_b1(b9_3to10_3_pong), .out_c(matrixC9_3), .b_data_valid_ping(b_data_valid_ping_delay9_3), .b_data_valid_pong(b_data_valid_pong_delay9_3), .mode(1'b0)); +processing_element pe9_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_9_4_NC), .in_a_chain(a9_3to9_4), .in_b(b8_4to9_4), .in_c(matrixC8_4), .out_a(out_a_9_4_NC), .out_a_chain(a9_4to9_5), .out_b(b9_4to10_4), .out_b0(b9_4to10_4_ping), .out_b1(b9_4to10_4_pong), .out_c(matrixC9_4), .b_data_valid_ping(b_data_valid_ping_delay9_4), .b_data_valid_pong(b_data_valid_pong_delay9_4), .mode(1'b0)); +processing_element pe9_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_9_5_NC), .in_a_chain(a9_4to9_5), .in_b(b8_5to9_5), .in_c(matrixC8_5), .out_a(out_a_9_5_NC), .out_a_chain(a9_5to9_6), .out_b(b9_5to10_5), .out_b0(b9_5to10_5_ping), .out_b1(b9_5to10_5_pong), .out_c(matrixC9_5), .b_data_valid_ping(b_data_valid_ping_delay9_5), .b_data_valid_pong(b_data_valid_pong_delay9_5), .mode(1'b0)); +processing_element pe9_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_9_6_NC), .in_a_chain(a9_5to9_6), .in_b(b8_6to9_6), .in_c(matrixC8_6), .out_a(out_a_9_6_NC), .out_a_chain(a9_6to9_7), .out_b(b9_6to10_6), .out_b0(b9_6to10_6_ping), .out_b1(b9_6to10_6_pong), .out_c(matrixC9_6), .b_data_valid_ping(b_data_valid_ping_delay9_6), .b_data_valid_pong(b_data_valid_pong_delay9_6), .mode(1'b0)); +processing_element pe9_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_9_7_NC), .in_a_chain(a9_6to9_7), .in_b(b8_7to9_7), .in_c(matrixC8_7), .out_a(out_a_9_7_NC), .out_a_chain(a9_7to9_8), .out_b(b9_7to10_7), .out_b0(b9_7to10_7_ping), .out_b1(b9_7to10_7_pong), .out_c(matrixC9_7), .b_data_valid_ping(b_data_valid_ping_delay9_7), .b_data_valid_pong(b_data_valid_pong_delay9_7), .mode(1'b0)); +processing_element pe9_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_9_8_NC), .in_a_chain(a9_7to9_8), .in_b(b8_8to9_8), .in_c(matrixC8_8), .out_a(out_a_9_8_NC), .out_a_chain(a9_8to9_9), .out_b(b9_8to10_8), .out_b0(b9_8to10_8_ping), .out_b1(b9_8to10_8_pong), .out_c(matrixC9_8), .b_data_valid_ping(b_data_valid_ping_delay9_8), .b_data_valid_pong(b_data_valid_pong_delay9_8), .mode(1'b0)); +processing_element pe9_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_9_9_NC), .in_a_chain(a9_8to9_9), .in_b(b8_9to9_9), .in_c(matrixC8_9), .out_a(out_a_9_9_NC), .out_a_chain(a9_9to9_10), .out_b(b9_9to10_9), .out_b0(b9_9to10_9_ping), .out_b1(b9_9to10_9_pong), .out_c(matrixC9_9), .b_data_valid_ping(b_data_valid_ping_delay9_9), .b_data_valid_pong(b_data_valid_pong_delay9_9), .mode(1'b0)); +processing_element pe9_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_9_10_NC), .in_a_chain(a9_9to9_10), .in_b(b8_10to9_10), .in_c(matrixC8_10), .out_a(out_a_9_10_NC), .out_a_chain(a9_10to9_11), .out_b(b9_10to10_10), .out_b0(b9_10to10_10_ping), .out_b1(b9_10to10_10_pong), .out_c(matrixC9_10), .b_data_valid_ping(b_data_valid_ping_delay9_10), .b_data_valid_pong(b_data_valid_pong_delay9_10), .mode(1'b0)); +processing_element pe9_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_9_11_NC), .in_a_chain(a9_10to9_11), .in_b(b8_11to9_11), .in_c(matrixC8_11), .out_a(out_a_9_11_NC), .out_a_chain(a9_11to9_12), .out_b(b9_11to10_11), .out_b0(b9_11to10_11_ping), .out_b1(b9_11to10_11_pong), .out_c(matrixC9_11), .b_data_valid_ping(b_data_valid_ping_delay9_11), .b_data_valid_pong(b_data_valid_pong_delay9_11), .mode(1'b0)); +processing_element pe9_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_9_12_NC), .in_a_chain(a9_11to9_12), .in_b(b8_12to9_12), .in_c(matrixC8_12), .out_a(out_a_9_12_NC), .out_a_chain(a9_12to9_13), .out_b(b9_12to10_12), .out_b0(b9_12to10_12_ping), .out_b1(b9_12to10_12_pong), .out_c(matrixC9_12), .b_data_valid_ping(b_data_valid_ping_delay9_12), .b_data_valid_pong(b_data_valid_pong_delay9_12), .mode(1'b0)); +processing_element pe9_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_9_13_NC), .in_a_chain(a9_12to9_13), .in_b(b8_13to9_13), .in_c(matrixC8_13), .out_a(out_a_9_13_NC), .out_a_chain(a9_13to9_14), .out_b(b9_13to10_13), .out_b0(b9_13to10_13_ping), .out_b1(b9_13to10_13_pong), .out_c(matrixC9_13), .b_data_valid_ping(b_data_valid_ping_delay9_13), .b_data_valid_pong(b_data_valid_pong_delay9_13), .mode(1'b0)); +processing_element pe9_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_9_14_NC), .in_a_chain(a9_13to9_14), .in_b(b8_14to9_14), .in_c(matrixC8_14), .out_a(out_a_9_14_NC), .out_a_chain(a9_14to9_15), .out_b(b9_14to10_14), .out_b0(b9_14to10_14_ping), .out_b1(b9_14to10_14_pong), .out_c(matrixC9_14), .b_data_valid_ping(b_data_valid_ping_delay9_14), .b_data_valid_pong(b_data_valid_pong_delay9_14), .mode(1'b0)); +processing_element pe9_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_9_15_NC), .in_a_chain(a9_14to9_15), .in_b(b8_15to9_15), .in_c(matrixC8_15), .out_a(out_a_9_15_NC), .out_a_chain(a9_15to9_16), .out_b(b9_15to10_15), .out_b0(b9_15to10_15_ping), .out_b1(b9_15to10_15_pong), .out_c(matrixC9_15), .b_data_valid_ping(b_data_valid_ping_delay9_15), .b_data_valid_pong(b_data_valid_pong_delay9_15), .mode(1'b0)); +processing_element pe9_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_9_16_NC), .in_a_chain(a9_15to9_16), .in_b(b8_16to9_16), .in_c(matrixC8_16), .out_a(out_a_9_16_NC), .out_a_chain(a9_16to9_17), .out_b(b9_16to10_16), .out_b0(b9_16to10_16_ping), .out_b1(b9_16to10_16_pong), .out_c(matrixC9_16), .b_data_valid_ping(b_data_valid_ping_delay9_16), .b_data_valid_pong(b_data_valid_pong_delay9_16), .mode(1'b0)); +processing_element pe9_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_9_17_NC), .in_a_chain(a9_16to9_17), .in_b(b8_17to9_17), .in_c(matrixC8_17), .out_a(out_a_9_17_NC), .out_a_chain(a9_17to9_18), .out_b(b9_17to10_17), .out_b0(b9_17to10_17_ping), .out_b1(b9_17to10_17_pong), .out_c(matrixC9_17), .b_data_valid_ping(b_data_valid_ping_delay9_17), .b_data_valid_pong(b_data_valid_pong_delay9_17), .mode(1'b0)); +processing_element pe9_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_9_18_NC), .in_a_chain(a9_17to9_18), .in_b(b8_18to9_18), .in_c(matrixC8_18), .out_a(out_a_9_18_NC), .out_a_chain(a9_18to9_19), .out_b(b9_18to10_18), .out_b0(b9_18to10_18_ping), .out_b1(b9_18to10_18_pong), .out_c(matrixC9_18), .b_data_valid_ping(b_data_valid_ping_delay9_18), .b_data_valid_pong(b_data_valid_pong_delay9_18), .mode(1'b0)); +processing_element pe9_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_9_19_NC), .in_a_chain(a9_18to9_19), .in_b(b8_19to9_19), .in_c(matrixC8_19), .out_a(out_a_9_19_NC), .out_a_chain(a9_19to9_20), .out_b(b9_19to10_19), .out_b0(b9_19to10_19_ping), .out_b1(b9_19to10_19_pong), .out_c(matrixC9_19), .b_data_valid_ping(b_data_valid_ping_delay9_19), .b_data_valid_pong(b_data_valid_pong_delay9_19), .mode(1'b0)); +processing_element pe9_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_9_20_NC), .in_a_chain(a9_19to9_20), .in_b(b8_20to9_20), .in_c(matrixC8_20), .out_a(out_a_9_20_NC), .out_a_chain(a9_20to9_21), .out_b(b9_20to10_20), .out_b0(b9_20to10_20_ping), .out_b1(b9_20to10_20_pong), .out_c(matrixC9_20), .b_data_valid_ping(b_data_valid_ping_delay9_20), .b_data_valid_pong(b_data_valid_pong_delay9_20), .mode(1'b0)); +processing_element pe9_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_9_21_NC), .in_a_chain(a9_20to9_21), .in_b(b8_21to9_21), .in_c(matrixC8_21), .out_a(out_a_9_21_NC), .out_a_chain(a9_21to9_22), .out_b(b9_21to10_21), .out_b0(b9_21to10_21_ping), .out_b1(b9_21to10_21_pong), .out_c(matrixC9_21), .b_data_valid_ping(b_data_valid_ping_delay9_21), .b_data_valid_pong(b_data_valid_pong_delay9_21), .mode(1'b0)); +processing_element pe9_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_9_22_NC), .in_a_chain(a9_21to9_22), .in_b(b8_22to9_22), .in_c(matrixC8_22), .out_a(out_a_9_22_NC), .out_a_chain(a9_22to9_23), .out_b(b9_22to10_22), .out_b0(b9_22to10_22_ping), .out_b1(b9_22to10_22_pong), .out_c(matrixC9_22), .b_data_valid_ping(b_data_valid_ping_delay9_22), .b_data_valid_pong(b_data_valid_pong_delay9_22), .mode(1'b0)); +processing_element pe9_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_9_23_NC), .in_a_chain(a9_22to9_23), .in_b(b8_23to9_23), .in_c(matrixC8_23), .out_a(out_a_9_23_NC), .out_a_chain(a9_23to9_24), .out_b(b9_23to10_23), .out_b0(b9_23to10_23_ping), .out_b1(b9_23to10_23_pong), .out_c(matrixC9_23), .b_data_valid_ping(b_data_valid_ping_delay9_23), .b_data_valid_pong(b_data_valid_pong_delay9_23), .mode(1'b0)); +processing_element pe9_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_9_24_NC), .in_a_chain(a9_23to9_24), .in_b(b8_24to9_24), .in_c(matrixC8_24), .out_a(out_a_9_24_NC), .out_a_chain(a9_24to9_25), .out_b(b9_24to10_24), .out_b0(b9_24to10_24_ping), .out_b1(b9_24to10_24_pong), .out_c(matrixC9_24), .b_data_valid_ping(b_data_valid_ping_delay9_24), .b_data_valid_pong(b_data_valid_pong_delay9_24), .mode(1'b0)); +processing_element pe9_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_9_25_NC), .in_a_chain(a9_24to9_25), .in_b(b8_25to9_25), .in_c(matrixC8_25), .out_a(out_a_9_25_NC), .out_a_chain(a9_25to9_26), .out_b(b9_25to10_25), .out_b0(b9_25to10_25_ping), .out_b1(b9_25to10_25_pong), .out_c(matrixC9_25), .b_data_valid_ping(b_data_valid_ping_delay9_25), .b_data_valid_pong(b_data_valid_pong_delay9_25), .mode(1'b0)); +processing_element pe9_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_9_26_NC), .in_a_chain(a9_25to9_26), .in_b(b8_26to9_26), .in_c(matrixC8_26), .out_a(out_a_9_26_NC), .out_a_chain(a9_26to9_27), .out_b(b9_26to10_26), .out_b0(b9_26to10_26_ping), .out_b1(b9_26to10_26_pong), .out_c(matrixC9_26), .b_data_valid_ping(b_data_valid_ping_delay9_26), .b_data_valid_pong(b_data_valid_pong_delay9_26), .mode(1'b0)); +processing_element pe9_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_9_27_NC), .in_a_chain(a9_26to9_27), .in_b(b8_27to9_27), .in_c(matrixC8_27), .out_a(out_a_9_27_NC), .out_a_chain(a9_27to9_28), .out_b(b9_27to10_27), .out_b0(b9_27to10_27_ping), .out_b1(b9_27to10_27_pong), .out_c(matrixC9_27), .b_data_valid_ping(b_data_valid_ping_delay9_27), .b_data_valid_pong(b_data_valid_pong_delay9_27), .mode(1'b0)); +processing_element pe9_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_9_28_NC), .in_a_chain(a9_27to9_28), .in_b(b8_28to9_28), .in_c(matrixC8_28), .out_a(out_a_9_28_NC), .out_a_chain(a9_28to9_29), .out_b(b9_28to10_28), .out_b0(b9_28to10_28_ping), .out_b1(b9_28to10_28_pong), .out_c(matrixC9_28), .b_data_valid_ping(b_data_valid_ping_delay9_28), .b_data_valid_pong(b_data_valid_pong_delay9_28), .mode(1'b0)); +processing_element pe9_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_9_29_NC), .in_a_chain(a9_28to9_29), .in_b(b8_29to9_29), .in_c(matrixC8_29), .out_a(out_a_9_29_NC), .out_a_chain(a9_29to9_30), .out_b(b9_29to10_29), .out_b0(b9_29to10_29_ping), .out_b1(b9_29to10_29_pong), .out_c(matrixC9_29), .b_data_valid_ping(b_data_valid_ping_delay9_29), .b_data_valid_pong(b_data_valid_pong_delay9_29), .mode(1'b0)); +processing_element pe9_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_9_30_NC), .in_a_chain(a9_29to9_30), .in_b(b8_30to9_30), .in_c(matrixC8_30), .out_a(out_a_9_30_NC), .out_a_chain(a9_30to9_31), .out_b(b9_30to10_30), .out_b0(b9_30to10_30_ping), .out_b1(b9_30to10_30_pong), .out_c(matrixC9_30), .b_data_valid_ping(b_data_valid_ping_delay9_30), .b_data_valid_pong(b_data_valid_pong_delay9_30), .mode(1'b0)); +processing_element pe9_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_9_31_NC), .in_a_chain(a9_30to9_31), .in_b(b8_31to9_31), .in_c(matrixC8_31), .out_a(out_a_9_31_NC), .out_a_chain(a9_31to9_32), .out_b(b9_31to10_31), .out_b0(b9_31to10_31_ping), .out_b1(b9_31to10_31_pong), .out_c(matrixC9_31), .b_data_valid_ping(b_data_valid_ping_delay9_31), .b_data_valid_pong(b_data_valid_pong_delay9_31), .mode(1'b0)); +processing_element pe10_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(a10), .in_a_chain(in_a_chain_10_0_NC), .in_b(b9_0to10_0), .in_c(matrixC9_0), .out_a(out_a_10_0_NC), .out_a_chain(a10_0to10_1), .out_b(b10_0to11_0), .out_b0(b10_0to11_0_ping), .out_b1(b10_0to11_0_pong), .out_c(matrixC10_0), .b_data_valid_ping(b_data_valid_ping_delay10_0), .b_data_valid_pong(b_data_valid_pong_delay10_0), .mode(1'b1)); +processing_element pe10_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_10_1_NC), .in_a_chain(a10_0to10_1), .in_b(b9_1to10_1), .in_c(matrixC9_1), .out_a(out_a_10_1_NC), .out_a_chain(a10_1to10_2), .out_b(b10_1to11_1), .out_b0(b10_1to11_1_ping), .out_b1(b10_1to11_1_pong), .out_c(matrixC10_1), .b_data_valid_ping(b_data_valid_ping_delay10_1), .b_data_valid_pong(b_data_valid_pong_delay10_1), .mode(1'b0)); +processing_element pe10_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_10_2_NC), .in_a_chain(a10_1to10_2), .in_b(b9_2to10_2), .in_c(matrixC9_2), .out_a(out_a_10_2_NC), .out_a_chain(a10_2to10_3), .out_b(b10_2to11_2), .out_b0(b10_2to11_2_ping), .out_b1(b10_2to11_2_pong), .out_c(matrixC10_2), .b_data_valid_ping(b_data_valid_ping_delay10_2), .b_data_valid_pong(b_data_valid_pong_delay10_2), .mode(1'b0)); +processing_element pe10_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_10_3_NC), .in_a_chain(a10_2to10_3), .in_b(b9_3to10_3), .in_c(matrixC9_3), .out_a(out_a_10_3_NC), .out_a_chain(a10_3to10_4), .out_b(b10_3to11_3), .out_b0(b10_3to11_3_ping), .out_b1(b10_3to11_3_pong), .out_c(matrixC10_3), .b_data_valid_ping(b_data_valid_ping_delay10_3), .b_data_valid_pong(b_data_valid_pong_delay10_3), .mode(1'b0)); +processing_element pe10_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_10_4_NC), .in_a_chain(a10_3to10_4), .in_b(b9_4to10_4), .in_c(matrixC9_4), .out_a(out_a_10_4_NC), .out_a_chain(a10_4to10_5), .out_b(b10_4to11_4), .out_b0(b10_4to11_4_ping), .out_b1(b10_4to11_4_pong), .out_c(matrixC10_4), .b_data_valid_ping(b_data_valid_ping_delay10_4), .b_data_valid_pong(b_data_valid_pong_delay10_4), .mode(1'b0)); +processing_element pe10_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_10_5_NC), .in_a_chain(a10_4to10_5), .in_b(b9_5to10_5), .in_c(matrixC9_5), .out_a(out_a_10_5_NC), .out_a_chain(a10_5to10_6), .out_b(b10_5to11_5), .out_b0(b10_5to11_5_ping), .out_b1(b10_5to11_5_pong), .out_c(matrixC10_5), .b_data_valid_ping(b_data_valid_ping_delay10_5), .b_data_valid_pong(b_data_valid_pong_delay10_5), .mode(1'b0)); +processing_element pe10_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_10_6_NC), .in_a_chain(a10_5to10_6), .in_b(b9_6to10_6), .in_c(matrixC9_6), .out_a(out_a_10_6_NC), .out_a_chain(a10_6to10_7), .out_b(b10_6to11_6), .out_b0(b10_6to11_6_ping), .out_b1(b10_6to11_6_pong), .out_c(matrixC10_6), .b_data_valid_ping(b_data_valid_ping_delay10_6), .b_data_valid_pong(b_data_valid_pong_delay10_6), .mode(1'b0)); +processing_element pe10_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_10_7_NC), .in_a_chain(a10_6to10_7), .in_b(b9_7to10_7), .in_c(matrixC9_7), .out_a(out_a_10_7_NC), .out_a_chain(a10_7to10_8), .out_b(b10_7to11_7), .out_b0(b10_7to11_7_ping), .out_b1(b10_7to11_7_pong), .out_c(matrixC10_7), .b_data_valid_ping(b_data_valid_ping_delay10_7), .b_data_valid_pong(b_data_valid_pong_delay10_7), .mode(1'b0)); +processing_element pe10_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_10_8_NC), .in_a_chain(a10_7to10_8), .in_b(b9_8to10_8), .in_c(matrixC9_8), .out_a(out_a_10_8_NC), .out_a_chain(a10_8to10_9), .out_b(b10_8to11_8), .out_b0(b10_8to11_8_ping), .out_b1(b10_8to11_8_pong), .out_c(matrixC10_8), .b_data_valid_ping(b_data_valid_ping_delay10_8), .b_data_valid_pong(b_data_valid_pong_delay10_8), .mode(1'b0)); +processing_element pe10_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_10_9_NC), .in_a_chain(a10_8to10_9), .in_b(b9_9to10_9), .in_c(matrixC9_9), .out_a(out_a_10_9_NC), .out_a_chain(a10_9to10_10), .out_b(b10_9to11_9), .out_b0(b10_9to11_9_ping), .out_b1(b10_9to11_9_pong), .out_c(matrixC10_9), .b_data_valid_ping(b_data_valid_ping_delay10_9), .b_data_valid_pong(b_data_valid_pong_delay10_9), .mode(1'b0)); +processing_element pe10_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_10_10_NC), .in_a_chain(a10_9to10_10), .in_b(b9_10to10_10), .in_c(matrixC9_10), .out_a(out_a_10_10_NC), .out_a_chain(a10_10to10_11), .out_b(b10_10to11_10), .out_b0(b10_10to11_10_ping), .out_b1(b10_10to11_10_pong), .out_c(matrixC10_10), .b_data_valid_ping(b_data_valid_ping_delay10_10), .b_data_valid_pong(b_data_valid_pong_delay10_10), .mode(1'b0)); +processing_element pe10_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_10_11_NC), .in_a_chain(a10_10to10_11), .in_b(b9_11to10_11), .in_c(matrixC9_11), .out_a(out_a_10_11_NC), .out_a_chain(a10_11to10_12), .out_b(b10_11to11_11), .out_b0(b10_11to11_11_ping), .out_b1(b10_11to11_11_pong), .out_c(matrixC10_11), .b_data_valid_ping(b_data_valid_ping_delay10_11), .b_data_valid_pong(b_data_valid_pong_delay10_11), .mode(1'b0)); +processing_element pe10_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_10_12_NC), .in_a_chain(a10_11to10_12), .in_b(b9_12to10_12), .in_c(matrixC9_12), .out_a(out_a_10_12_NC), .out_a_chain(a10_12to10_13), .out_b(b10_12to11_12), .out_b0(b10_12to11_12_ping), .out_b1(b10_12to11_12_pong), .out_c(matrixC10_12), .b_data_valid_ping(b_data_valid_ping_delay10_12), .b_data_valid_pong(b_data_valid_pong_delay10_12), .mode(1'b0)); +processing_element pe10_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_10_13_NC), .in_a_chain(a10_12to10_13), .in_b(b9_13to10_13), .in_c(matrixC9_13), .out_a(out_a_10_13_NC), .out_a_chain(a10_13to10_14), .out_b(b10_13to11_13), .out_b0(b10_13to11_13_ping), .out_b1(b10_13to11_13_pong), .out_c(matrixC10_13), .b_data_valid_ping(b_data_valid_ping_delay10_13), .b_data_valid_pong(b_data_valid_pong_delay10_13), .mode(1'b0)); +processing_element pe10_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_10_14_NC), .in_a_chain(a10_13to10_14), .in_b(b9_14to10_14), .in_c(matrixC9_14), .out_a(out_a_10_14_NC), .out_a_chain(a10_14to10_15), .out_b(b10_14to11_14), .out_b0(b10_14to11_14_ping), .out_b1(b10_14to11_14_pong), .out_c(matrixC10_14), .b_data_valid_ping(b_data_valid_ping_delay10_14), .b_data_valid_pong(b_data_valid_pong_delay10_14), .mode(1'b0)); +processing_element pe10_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_10_15_NC), .in_a_chain(a10_14to10_15), .in_b(b9_15to10_15), .in_c(matrixC9_15), .out_a(out_a_10_15_NC), .out_a_chain(a10_15to10_16), .out_b(b10_15to11_15), .out_b0(b10_15to11_15_ping), .out_b1(b10_15to11_15_pong), .out_c(matrixC10_15), .b_data_valid_ping(b_data_valid_ping_delay10_15), .b_data_valid_pong(b_data_valid_pong_delay10_15), .mode(1'b0)); +processing_element pe10_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_10_16_NC), .in_a_chain(a10_15to10_16), .in_b(b9_16to10_16), .in_c(matrixC9_16), .out_a(out_a_10_16_NC), .out_a_chain(a10_16to10_17), .out_b(b10_16to11_16), .out_b0(b10_16to11_16_ping), .out_b1(b10_16to11_16_pong), .out_c(matrixC10_16), .b_data_valid_ping(b_data_valid_ping_delay10_16), .b_data_valid_pong(b_data_valid_pong_delay10_16), .mode(1'b0)); +processing_element pe10_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_10_17_NC), .in_a_chain(a10_16to10_17), .in_b(b9_17to10_17), .in_c(matrixC9_17), .out_a(out_a_10_17_NC), .out_a_chain(a10_17to10_18), .out_b(b10_17to11_17), .out_b0(b10_17to11_17_ping), .out_b1(b10_17to11_17_pong), .out_c(matrixC10_17), .b_data_valid_ping(b_data_valid_ping_delay10_17), .b_data_valid_pong(b_data_valid_pong_delay10_17), .mode(1'b0)); +processing_element pe10_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_10_18_NC), .in_a_chain(a10_17to10_18), .in_b(b9_18to10_18), .in_c(matrixC9_18), .out_a(out_a_10_18_NC), .out_a_chain(a10_18to10_19), .out_b(b10_18to11_18), .out_b0(b10_18to11_18_ping), .out_b1(b10_18to11_18_pong), .out_c(matrixC10_18), .b_data_valid_ping(b_data_valid_ping_delay10_18), .b_data_valid_pong(b_data_valid_pong_delay10_18), .mode(1'b0)); +processing_element pe10_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_10_19_NC), .in_a_chain(a10_18to10_19), .in_b(b9_19to10_19), .in_c(matrixC9_19), .out_a(out_a_10_19_NC), .out_a_chain(a10_19to10_20), .out_b(b10_19to11_19), .out_b0(b10_19to11_19_ping), .out_b1(b10_19to11_19_pong), .out_c(matrixC10_19), .b_data_valid_ping(b_data_valid_ping_delay10_19), .b_data_valid_pong(b_data_valid_pong_delay10_19), .mode(1'b0)); +processing_element pe10_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_10_20_NC), .in_a_chain(a10_19to10_20), .in_b(b9_20to10_20), .in_c(matrixC9_20), .out_a(out_a_10_20_NC), .out_a_chain(a10_20to10_21), .out_b(b10_20to11_20), .out_b0(b10_20to11_20_ping), .out_b1(b10_20to11_20_pong), .out_c(matrixC10_20), .b_data_valid_ping(b_data_valid_ping_delay10_20), .b_data_valid_pong(b_data_valid_pong_delay10_20), .mode(1'b0)); +processing_element pe10_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_10_21_NC), .in_a_chain(a10_20to10_21), .in_b(b9_21to10_21), .in_c(matrixC9_21), .out_a(out_a_10_21_NC), .out_a_chain(a10_21to10_22), .out_b(b10_21to11_21), .out_b0(b10_21to11_21_ping), .out_b1(b10_21to11_21_pong), .out_c(matrixC10_21), .b_data_valid_ping(b_data_valid_ping_delay10_21), .b_data_valid_pong(b_data_valid_pong_delay10_21), .mode(1'b0)); +processing_element pe10_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_10_22_NC), .in_a_chain(a10_21to10_22), .in_b(b9_22to10_22), .in_c(matrixC9_22), .out_a(out_a_10_22_NC), .out_a_chain(a10_22to10_23), .out_b(b10_22to11_22), .out_b0(b10_22to11_22_ping), .out_b1(b10_22to11_22_pong), .out_c(matrixC10_22), .b_data_valid_ping(b_data_valid_ping_delay10_22), .b_data_valid_pong(b_data_valid_pong_delay10_22), .mode(1'b0)); +processing_element pe10_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_10_23_NC), .in_a_chain(a10_22to10_23), .in_b(b9_23to10_23), .in_c(matrixC9_23), .out_a(out_a_10_23_NC), .out_a_chain(a10_23to10_24), .out_b(b10_23to11_23), .out_b0(b10_23to11_23_ping), .out_b1(b10_23to11_23_pong), .out_c(matrixC10_23), .b_data_valid_ping(b_data_valid_ping_delay10_23), .b_data_valid_pong(b_data_valid_pong_delay10_23), .mode(1'b0)); +processing_element pe10_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_10_24_NC), .in_a_chain(a10_23to10_24), .in_b(b9_24to10_24), .in_c(matrixC9_24), .out_a(out_a_10_24_NC), .out_a_chain(a10_24to10_25), .out_b(b10_24to11_24), .out_b0(b10_24to11_24_ping), .out_b1(b10_24to11_24_pong), .out_c(matrixC10_24), .b_data_valid_ping(b_data_valid_ping_delay10_24), .b_data_valid_pong(b_data_valid_pong_delay10_24), .mode(1'b0)); +processing_element pe10_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_10_25_NC), .in_a_chain(a10_24to10_25), .in_b(b9_25to10_25), .in_c(matrixC9_25), .out_a(out_a_10_25_NC), .out_a_chain(a10_25to10_26), .out_b(b10_25to11_25), .out_b0(b10_25to11_25_ping), .out_b1(b10_25to11_25_pong), .out_c(matrixC10_25), .b_data_valid_ping(b_data_valid_ping_delay10_25), .b_data_valid_pong(b_data_valid_pong_delay10_25), .mode(1'b0)); +processing_element pe10_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_10_26_NC), .in_a_chain(a10_25to10_26), .in_b(b9_26to10_26), .in_c(matrixC9_26), .out_a(out_a_10_26_NC), .out_a_chain(a10_26to10_27), .out_b(b10_26to11_26), .out_b0(b10_26to11_26_ping), .out_b1(b10_26to11_26_pong), .out_c(matrixC10_26), .b_data_valid_ping(b_data_valid_ping_delay10_26), .b_data_valid_pong(b_data_valid_pong_delay10_26), .mode(1'b0)); +processing_element pe10_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_10_27_NC), .in_a_chain(a10_26to10_27), .in_b(b9_27to10_27), .in_c(matrixC9_27), .out_a(out_a_10_27_NC), .out_a_chain(a10_27to10_28), .out_b(b10_27to11_27), .out_b0(b10_27to11_27_ping), .out_b1(b10_27to11_27_pong), .out_c(matrixC10_27), .b_data_valid_ping(b_data_valid_ping_delay10_27), .b_data_valid_pong(b_data_valid_pong_delay10_27), .mode(1'b0)); +processing_element pe10_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_10_28_NC), .in_a_chain(a10_27to10_28), .in_b(b9_28to10_28), .in_c(matrixC9_28), .out_a(out_a_10_28_NC), .out_a_chain(a10_28to10_29), .out_b(b10_28to11_28), .out_b0(b10_28to11_28_ping), .out_b1(b10_28to11_28_pong), .out_c(matrixC10_28), .b_data_valid_ping(b_data_valid_ping_delay10_28), .b_data_valid_pong(b_data_valid_pong_delay10_28), .mode(1'b0)); +processing_element pe10_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_10_29_NC), .in_a_chain(a10_28to10_29), .in_b(b9_29to10_29), .in_c(matrixC9_29), .out_a(out_a_10_29_NC), .out_a_chain(a10_29to10_30), .out_b(b10_29to11_29), .out_b0(b10_29to11_29_ping), .out_b1(b10_29to11_29_pong), .out_c(matrixC10_29), .b_data_valid_ping(b_data_valid_ping_delay10_29), .b_data_valid_pong(b_data_valid_pong_delay10_29), .mode(1'b0)); +processing_element pe10_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_10_30_NC), .in_a_chain(a10_29to10_30), .in_b(b9_30to10_30), .in_c(matrixC9_30), .out_a(out_a_10_30_NC), .out_a_chain(a10_30to10_31), .out_b(b10_30to11_30), .out_b0(b10_30to11_30_ping), .out_b1(b10_30to11_30_pong), .out_c(matrixC10_30), .b_data_valid_ping(b_data_valid_ping_delay10_30), .b_data_valid_pong(b_data_valid_pong_delay10_30), .mode(1'b0)); +processing_element pe10_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_10_31_NC), .in_a_chain(a10_30to10_31), .in_b(b9_31to10_31), .in_c(matrixC9_31), .out_a(out_a_10_31_NC), .out_a_chain(a10_31to10_32), .out_b(b10_31to11_31), .out_b0(b10_31to11_31_ping), .out_b1(b10_31to11_31_pong), .out_c(matrixC10_31), .b_data_valid_ping(b_data_valid_ping_delay10_31), .b_data_valid_pong(b_data_valid_pong_delay10_31), .mode(1'b0)); +processing_element pe11_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(a11), .in_a_chain(in_a_chain_11_0_NC), .in_b(b10_0to11_0), .in_c(matrixC10_0), .out_a(out_a_11_0_NC), .out_a_chain(a11_0to11_1), .out_b(b11_0to12_0), .out_b0(b11_0to12_0_ping), .out_b1(b11_0to12_0_pong), .out_c(matrixC11_0), .b_data_valid_ping(b_data_valid_ping_delay11_0), .b_data_valid_pong(b_data_valid_pong_delay11_0), .mode(1'b1)); +processing_element pe11_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_11_1_NC), .in_a_chain(a11_0to11_1), .in_b(b10_1to11_1), .in_c(matrixC10_1), .out_a(out_a_11_1_NC), .out_a_chain(a11_1to11_2), .out_b(b11_1to12_1), .out_b0(b11_1to12_1_ping), .out_b1(b11_1to12_1_pong), .out_c(matrixC11_1), .b_data_valid_ping(b_data_valid_ping_delay11_1), .b_data_valid_pong(b_data_valid_pong_delay11_1), .mode(1'b0)); +processing_element pe11_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_11_2_NC), .in_a_chain(a11_1to11_2), .in_b(b10_2to11_2), .in_c(matrixC10_2), .out_a(out_a_11_2_NC), .out_a_chain(a11_2to11_3), .out_b(b11_2to12_2), .out_b0(b11_2to12_2_ping), .out_b1(b11_2to12_2_pong), .out_c(matrixC11_2), .b_data_valid_ping(b_data_valid_ping_delay11_2), .b_data_valid_pong(b_data_valid_pong_delay11_2), .mode(1'b0)); +processing_element pe11_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_11_3_NC), .in_a_chain(a11_2to11_3), .in_b(b10_3to11_3), .in_c(matrixC10_3), .out_a(out_a_11_3_NC), .out_a_chain(a11_3to11_4), .out_b(b11_3to12_3), .out_b0(b11_3to12_3_ping), .out_b1(b11_3to12_3_pong), .out_c(matrixC11_3), .b_data_valid_ping(b_data_valid_ping_delay11_3), .b_data_valid_pong(b_data_valid_pong_delay11_3), .mode(1'b0)); +processing_element pe11_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_11_4_NC), .in_a_chain(a11_3to11_4), .in_b(b10_4to11_4), .in_c(matrixC10_4), .out_a(out_a_11_4_NC), .out_a_chain(a11_4to11_5), .out_b(b11_4to12_4), .out_b0(b11_4to12_4_ping), .out_b1(b11_4to12_4_pong), .out_c(matrixC11_4), .b_data_valid_ping(b_data_valid_ping_delay11_4), .b_data_valid_pong(b_data_valid_pong_delay11_4), .mode(1'b0)); +processing_element pe11_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_11_5_NC), .in_a_chain(a11_4to11_5), .in_b(b10_5to11_5), .in_c(matrixC10_5), .out_a(out_a_11_5_NC), .out_a_chain(a11_5to11_6), .out_b(b11_5to12_5), .out_b0(b11_5to12_5_ping), .out_b1(b11_5to12_5_pong), .out_c(matrixC11_5), .b_data_valid_ping(b_data_valid_ping_delay11_5), .b_data_valid_pong(b_data_valid_pong_delay11_5), .mode(1'b0)); +processing_element pe11_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_11_6_NC), .in_a_chain(a11_5to11_6), .in_b(b10_6to11_6), .in_c(matrixC10_6), .out_a(out_a_11_6_NC), .out_a_chain(a11_6to11_7), .out_b(b11_6to12_6), .out_b0(b11_6to12_6_ping), .out_b1(b11_6to12_6_pong), .out_c(matrixC11_6), .b_data_valid_ping(b_data_valid_ping_delay11_6), .b_data_valid_pong(b_data_valid_pong_delay11_6), .mode(1'b0)); +processing_element pe11_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_11_7_NC), .in_a_chain(a11_6to11_7), .in_b(b10_7to11_7), .in_c(matrixC10_7), .out_a(out_a_11_7_NC), .out_a_chain(a11_7to11_8), .out_b(b11_7to12_7), .out_b0(b11_7to12_7_ping), .out_b1(b11_7to12_7_pong), .out_c(matrixC11_7), .b_data_valid_ping(b_data_valid_ping_delay11_7), .b_data_valid_pong(b_data_valid_pong_delay11_7), .mode(1'b0)); +processing_element pe11_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_11_8_NC), .in_a_chain(a11_7to11_8), .in_b(b10_8to11_8), .in_c(matrixC10_8), .out_a(out_a_11_8_NC), .out_a_chain(a11_8to11_9), .out_b(b11_8to12_8), .out_b0(b11_8to12_8_ping), .out_b1(b11_8to12_8_pong), .out_c(matrixC11_8), .b_data_valid_ping(b_data_valid_ping_delay11_8), .b_data_valid_pong(b_data_valid_pong_delay11_8), .mode(1'b0)); +processing_element pe11_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_11_9_NC), .in_a_chain(a11_8to11_9), .in_b(b10_9to11_9), .in_c(matrixC10_9), .out_a(out_a_11_9_NC), .out_a_chain(a11_9to11_10), .out_b(b11_9to12_9), .out_b0(b11_9to12_9_ping), .out_b1(b11_9to12_9_pong), .out_c(matrixC11_9), .b_data_valid_ping(b_data_valid_ping_delay11_9), .b_data_valid_pong(b_data_valid_pong_delay11_9), .mode(1'b0)); +processing_element pe11_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_11_10_NC), .in_a_chain(a11_9to11_10), .in_b(b10_10to11_10), .in_c(matrixC10_10), .out_a(out_a_11_10_NC), .out_a_chain(a11_10to11_11), .out_b(b11_10to12_10), .out_b0(b11_10to12_10_ping), .out_b1(b11_10to12_10_pong), .out_c(matrixC11_10), .b_data_valid_ping(b_data_valid_ping_delay11_10), .b_data_valid_pong(b_data_valid_pong_delay11_10), .mode(1'b0)); +processing_element pe11_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_11_11_NC), .in_a_chain(a11_10to11_11), .in_b(b10_11to11_11), .in_c(matrixC10_11), .out_a(out_a_11_11_NC), .out_a_chain(a11_11to11_12), .out_b(b11_11to12_11), .out_b0(b11_11to12_11_ping), .out_b1(b11_11to12_11_pong), .out_c(matrixC11_11), .b_data_valid_ping(b_data_valid_ping_delay11_11), .b_data_valid_pong(b_data_valid_pong_delay11_11), .mode(1'b0)); +processing_element pe11_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_11_12_NC), .in_a_chain(a11_11to11_12), .in_b(b10_12to11_12), .in_c(matrixC10_12), .out_a(out_a_11_12_NC), .out_a_chain(a11_12to11_13), .out_b(b11_12to12_12), .out_b0(b11_12to12_12_ping), .out_b1(b11_12to12_12_pong), .out_c(matrixC11_12), .b_data_valid_ping(b_data_valid_ping_delay11_12), .b_data_valid_pong(b_data_valid_pong_delay11_12), .mode(1'b0)); +processing_element pe11_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_11_13_NC), .in_a_chain(a11_12to11_13), .in_b(b10_13to11_13), .in_c(matrixC10_13), .out_a(out_a_11_13_NC), .out_a_chain(a11_13to11_14), .out_b(b11_13to12_13), .out_b0(b11_13to12_13_ping), .out_b1(b11_13to12_13_pong), .out_c(matrixC11_13), .b_data_valid_ping(b_data_valid_ping_delay11_13), .b_data_valid_pong(b_data_valid_pong_delay11_13), .mode(1'b0)); +processing_element pe11_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_11_14_NC), .in_a_chain(a11_13to11_14), .in_b(b10_14to11_14), .in_c(matrixC10_14), .out_a(out_a_11_14_NC), .out_a_chain(a11_14to11_15), .out_b(b11_14to12_14), .out_b0(b11_14to12_14_ping), .out_b1(b11_14to12_14_pong), .out_c(matrixC11_14), .b_data_valid_ping(b_data_valid_ping_delay11_14), .b_data_valid_pong(b_data_valid_pong_delay11_14), .mode(1'b0)); +processing_element pe11_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_11_15_NC), .in_a_chain(a11_14to11_15), .in_b(b10_15to11_15), .in_c(matrixC10_15), .out_a(out_a_11_15_NC), .out_a_chain(a11_15to11_16), .out_b(b11_15to12_15), .out_b0(b11_15to12_15_ping), .out_b1(b11_15to12_15_pong), .out_c(matrixC11_15), .b_data_valid_ping(b_data_valid_ping_delay11_15), .b_data_valid_pong(b_data_valid_pong_delay11_15), .mode(1'b0)); +processing_element pe11_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_11_16_NC), .in_a_chain(a11_15to11_16), .in_b(b10_16to11_16), .in_c(matrixC10_16), .out_a(out_a_11_16_NC), .out_a_chain(a11_16to11_17), .out_b(b11_16to12_16), .out_b0(b11_16to12_16_ping), .out_b1(b11_16to12_16_pong), .out_c(matrixC11_16), .b_data_valid_ping(b_data_valid_ping_delay11_16), .b_data_valid_pong(b_data_valid_pong_delay11_16), .mode(1'b0)); +processing_element pe11_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_11_17_NC), .in_a_chain(a11_16to11_17), .in_b(b10_17to11_17), .in_c(matrixC10_17), .out_a(out_a_11_17_NC), .out_a_chain(a11_17to11_18), .out_b(b11_17to12_17), .out_b0(b11_17to12_17_ping), .out_b1(b11_17to12_17_pong), .out_c(matrixC11_17), .b_data_valid_ping(b_data_valid_ping_delay11_17), .b_data_valid_pong(b_data_valid_pong_delay11_17), .mode(1'b0)); +processing_element pe11_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_11_18_NC), .in_a_chain(a11_17to11_18), .in_b(b10_18to11_18), .in_c(matrixC10_18), .out_a(out_a_11_18_NC), .out_a_chain(a11_18to11_19), .out_b(b11_18to12_18), .out_b0(b11_18to12_18_ping), .out_b1(b11_18to12_18_pong), .out_c(matrixC11_18), .b_data_valid_ping(b_data_valid_ping_delay11_18), .b_data_valid_pong(b_data_valid_pong_delay11_18), .mode(1'b0)); +processing_element pe11_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_11_19_NC), .in_a_chain(a11_18to11_19), .in_b(b10_19to11_19), .in_c(matrixC10_19), .out_a(out_a_11_19_NC), .out_a_chain(a11_19to11_20), .out_b(b11_19to12_19), .out_b0(b11_19to12_19_ping), .out_b1(b11_19to12_19_pong), .out_c(matrixC11_19), .b_data_valid_ping(b_data_valid_ping_delay11_19), .b_data_valid_pong(b_data_valid_pong_delay11_19), .mode(1'b0)); +processing_element pe11_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_11_20_NC), .in_a_chain(a11_19to11_20), .in_b(b10_20to11_20), .in_c(matrixC10_20), .out_a(out_a_11_20_NC), .out_a_chain(a11_20to11_21), .out_b(b11_20to12_20), .out_b0(b11_20to12_20_ping), .out_b1(b11_20to12_20_pong), .out_c(matrixC11_20), .b_data_valid_ping(b_data_valid_ping_delay11_20), .b_data_valid_pong(b_data_valid_pong_delay11_20), .mode(1'b0)); +processing_element pe11_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_11_21_NC), .in_a_chain(a11_20to11_21), .in_b(b10_21to11_21), .in_c(matrixC10_21), .out_a(out_a_11_21_NC), .out_a_chain(a11_21to11_22), .out_b(b11_21to12_21), .out_b0(b11_21to12_21_ping), .out_b1(b11_21to12_21_pong), .out_c(matrixC11_21), .b_data_valid_ping(b_data_valid_ping_delay11_21), .b_data_valid_pong(b_data_valid_pong_delay11_21), .mode(1'b0)); +processing_element pe11_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_11_22_NC), .in_a_chain(a11_21to11_22), .in_b(b10_22to11_22), .in_c(matrixC10_22), .out_a(out_a_11_22_NC), .out_a_chain(a11_22to11_23), .out_b(b11_22to12_22), .out_b0(b11_22to12_22_ping), .out_b1(b11_22to12_22_pong), .out_c(matrixC11_22), .b_data_valid_ping(b_data_valid_ping_delay11_22), .b_data_valid_pong(b_data_valid_pong_delay11_22), .mode(1'b0)); +processing_element pe11_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_11_23_NC), .in_a_chain(a11_22to11_23), .in_b(b10_23to11_23), .in_c(matrixC10_23), .out_a(out_a_11_23_NC), .out_a_chain(a11_23to11_24), .out_b(b11_23to12_23), .out_b0(b11_23to12_23_ping), .out_b1(b11_23to12_23_pong), .out_c(matrixC11_23), .b_data_valid_ping(b_data_valid_ping_delay11_23), .b_data_valid_pong(b_data_valid_pong_delay11_23), .mode(1'b0)); +processing_element pe11_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_11_24_NC), .in_a_chain(a11_23to11_24), .in_b(b10_24to11_24), .in_c(matrixC10_24), .out_a(out_a_11_24_NC), .out_a_chain(a11_24to11_25), .out_b(b11_24to12_24), .out_b0(b11_24to12_24_ping), .out_b1(b11_24to12_24_pong), .out_c(matrixC11_24), .b_data_valid_ping(b_data_valid_ping_delay11_24), .b_data_valid_pong(b_data_valid_pong_delay11_24), .mode(1'b0)); +processing_element pe11_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_11_25_NC), .in_a_chain(a11_24to11_25), .in_b(b10_25to11_25), .in_c(matrixC10_25), .out_a(out_a_11_25_NC), .out_a_chain(a11_25to11_26), .out_b(b11_25to12_25), .out_b0(b11_25to12_25_ping), .out_b1(b11_25to12_25_pong), .out_c(matrixC11_25), .b_data_valid_ping(b_data_valid_ping_delay11_25), .b_data_valid_pong(b_data_valid_pong_delay11_25), .mode(1'b0)); +processing_element pe11_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_11_26_NC), .in_a_chain(a11_25to11_26), .in_b(b10_26to11_26), .in_c(matrixC10_26), .out_a(out_a_11_26_NC), .out_a_chain(a11_26to11_27), .out_b(b11_26to12_26), .out_b0(b11_26to12_26_ping), .out_b1(b11_26to12_26_pong), .out_c(matrixC11_26), .b_data_valid_ping(b_data_valid_ping_delay11_26), .b_data_valid_pong(b_data_valid_pong_delay11_26), .mode(1'b0)); +processing_element pe11_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_11_27_NC), .in_a_chain(a11_26to11_27), .in_b(b10_27to11_27), .in_c(matrixC10_27), .out_a(out_a_11_27_NC), .out_a_chain(a11_27to11_28), .out_b(b11_27to12_27), .out_b0(b11_27to12_27_ping), .out_b1(b11_27to12_27_pong), .out_c(matrixC11_27), .b_data_valid_ping(b_data_valid_ping_delay11_27), .b_data_valid_pong(b_data_valid_pong_delay11_27), .mode(1'b0)); +processing_element pe11_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_11_28_NC), .in_a_chain(a11_27to11_28), .in_b(b10_28to11_28), .in_c(matrixC10_28), .out_a(out_a_11_28_NC), .out_a_chain(a11_28to11_29), .out_b(b11_28to12_28), .out_b0(b11_28to12_28_ping), .out_b1(b11_28to12_28_pong), .out_c(matrixC11_28), .b_data_valid_ping(b_data_valid_ping_delay11_28), .b_data_valid_pong(b_data_valid_pong_delay11_28), .mode(1'b0)); +processing_element pe11_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_11_29_NC), .in_a_chain(a11_28to11_29), .in_b(b10_29to11_29), .in_c(matrixC10_29), .out_a(out_a_11_29_NC), .out_a_chain(a11_29to11_30), .out_b(b11_29to12_29), .out_b0(b11_29to12_29_ping), .out_b1(b11_29to12_29_pong), .out_c(matrixC11_29), .b_data_valid_ping(b_data_valid_ping_delay11_29), .b_data_valid_pong(b_data_valid_pong_delay11_29), .mode(1'b0)); +processing_element pe11_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_11_30_NC), .in_a_chain(a11_29to11_30), .in_b(b10_30to11_30), .in_c(matrixC10_30), .out_a(out_a_11_30_NC), .out_a_chain(a11_30to11_31), .out_b(b11_30to12_30), .out_b0(b11_30to12_30_ping), .out_b1(b11_30to12_30_pong), .out_c(matrixC11_30), .b_data_valid_ping(b_data_valid_ping_delay11_30), .b_data_valid_pong(b_data_valid_pong_delay11_30), .mode(1'b0)); +processing_element pe11_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_11_31_NC), .in_a_chain(a11_30to11_31), .in_b(b10_31to11_31), .in_c(matrixC10_31), .out_a(out_a_11_31_NC), .out_a_chain(a11_31to11_32), .out_b(b11_31to12_31), .out_b0(b11_31to12_31_ping), .out_b1(b11_31to12_31_pong), .out_c(matrixC11_31), .b_data_valid_ping(b_data_valid_ping_delay11_31), .b_data_valid_pong(b_data_valid_pong_delay11_31), .mode(1'b0)); +processing_element pe12_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(a12), .in_a_chain(in_a_chain_12_0_NC), .in_b(b11_0to12_0), .in_c(matrixC11_0), .out_a(out_a_12_0_NC), .out_a_chain(a12_0to12_1), .out_b(b12_0to13_0), .out_b0(b12_0to13_0_ping), .out_b1(b12_0to13_0_pong), .out_c(matrixC12_0), .b_data_valid_ping(b_data_valid_ping_delay12_0), .b_data_valid_pong(b_data_valid_pong_delay12_0), .mode(1'b1)); +processing_element pe12_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_12_1_NC), .in_a_chain(a12_0to12_1), .in_b(b11_1to12_1), .in_c(matrixC11_1), .out_a(out_a_12_1_NC), .out_a_chain(a12_1to12_2), .out_b(b12_1to13_1), .out_b0(b12_1to13_1_ping), .out_b1(b12_1to13_1_pong), .out_c(matrixC12_1), .b_data_valid_ping(b_data_valid_ping_delay12_1), .b_data_valid_pong(b_data_valid_pong_delay12_1), .mode(1'b0)); +processing_element pe12_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_12_2_NC), .in_a_chain(a12_1to12_2), .in_b(b11_2to12_2), .in_c(matrixC11_2), .out_a(out_a_12_2_NC), .out_a_chain(a12_2to12_3), .out_b(b12_2to13_2), .out_b0(b12_2to13_2_ping), .out_b1(b12_2to13_2_pong), .out_c(matrixC12_2), .b_data_valid_ping(b_data_valid_ping_delay12_2), .b_data_valid_pong(b_data_valid_pong_delay12_2), .mode(1'b0)); +processing_element pe12_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_12_3_NC), .in_a_chain(a12_2to12_3), .in_b(b11_3to12_3), .in_c(matrixC11_3), .out_a(out_a_12_3_NC), .out_a_chain(a12_3to12_4), .out_b(b12_3to13_3), .out_b0(b12_3to13_3_ping), .out_b1(b12_3to13_3_pong), .out_c(matrixC12_3), .b_data_valid_ping(b_data_valid_ping_delay12_3), .b_data_valid_pong(b_data_valid_pong_delay12_3), .mode(1'b0)); +processing_element pe12_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_12_4_NC), .in_a_chain(a12_3to12_4), .in_b(b11_4to12_4), .in_c(matrixC11_4), .out_a(out_a_12_4_NC), .out_a_chain(a12_4to12_5), .out_b(b12_4to13_4), .out_b0(b12_4to13_4_ping), .out_b1(b12_4to13_4_pong), .out_c(matrixC12_4), .b_data_valid_ping(b_data_valid_ping_delay12_4), .b_data_valid_pong(b_data_valid_pong_delay12_4), .mode(1'b0)); +processing_element pe12_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_12_5_NC), .in_a_chain(a12_4to12_5), .in_b(b11_5to12_5), .in_c(matrixC11_5), .out_a(out_a_12_5_NC), .out_a_chain(a12_5to12_6), .out_b(b12_5to13_5), .out_b0(b12_5to13_5_ping), .out_b1(b12_5to13_5_pong), .out_c(matrixC12_5), .b_data_valid_ping(b_data_valid_ping_delay12_5), .b_data_valid_pong(b_data_valid_pong_delay12_5), .mode(1'b0)); +processing_element pe12_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_12_6_NC), .in_a_chain(a12_5to12_6), .in_b(b11_6to12_6), .in_c(matrixC11_6), .out_a(out_a_12_6_NC), .out_a_chain(a12_6to12_7), .out_b(b12_6to13_6), .out_b0(b12_6to13_6_ping), .out_b1(b12_6to13_6_pong), .out_c(matrixC12_6), .b_data_valid_ping(b_data_valid_ping_delay12_6), .b_data_valid_pong(b_data_valid_pong_delay12_6), .mode(1'b0)); +processing_element pe12_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_12_7_NC), .in_a_chain(a12_6to12_7), .in_b(b11_7to12_7), .in_c(matrixC11_7), .out_a(out_a_12_7_NC), .out_a_chain(a12_7to12_8), .out_b(b12_7to13_7), .out_b0(b12_7to13_7_ping), .out_b1(b12_7to13_7_pong), .out_c(matrixC12_7), .b_data_valid_ping(b_data_valid_ping_delay12_7), .b_data_valid_pong(b_data_valid_pong_delay12_7), .mode(1'b0)); +processing_element pe12_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_12_8_NC), .in_a_chain(a12_7to12_8), .in_b(b11_8to12_8), .in_c(matrixC11_8), .out_a(out_a_12_8_NC), .out_a_chain(a12_8to12_9), .out_b(b12_8to13_8), .out_b0(b12_8to13_8_ping), .out_b1(b12_8to13_8_pong), .out_c(matrixC12_8), .b_data_valid_ping(b_data_valid_ping_delay12_8), .b_data_valid_pong(b_data_valid_pong_delay12_8), .mode(1'b0)); +processing_element pe12_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_12_9_NC), .in_a_chain(a12_8to12_9), .in_b(b11_9to12_9), .in_c(matrixC11_9), .out_a(out_a_12_9_NC), .out_a_chain(a12_9to12_10), .out_b(b12_9to13_9), .out_b0(b12_9to13_9_ping), .out_b1(b12_9to13_9_pong), .out_c(matrixC12_9), .b_data_valid_ping(b_data_valid_ping_delay12_9), .b_data_valid_pong(b_data_valid_pong_delay12_9), .mode(1'b0)); +processing_element pe12_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_12_10_NC), .in_a_chain(a12_9to12_10), .in_b(b11_10to12_10), .in_c(matrixC11_10), .out_a(out_a_12_10_NC), .out_a_chain(a12_10to12_11), .out_b(b12_10to13_10), .out_b0(b12_10to13_10_ping), .out_b1(b12_10to13_10_pong), .out_c(matrixC12_10), .b_data_valid_ping(b_data_valid_ping_delay12_10), .b_data_valid_pong(b_data_valid_pong_delay12_10), .mode(1'b0)); +processing_element pe12_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_12_11_NC), .in_a_chain(a12_10to12_11), .in_b(b11_11to12_11), .in_c(matrixC11_11), .out_a(out_a_12_11_NC), .out_a_chain(a12_11to12_12), .out_b(b12_11to13_11), .out_b0(b12_11to13_11_ping), .out_b1(b12_11to13_11_pong), .out_c(matrixC12_11), .b_data_valid_ping(b_data_valid_ping_delay12_11), .b_data_valid_pong(b_data_valid_pong_delay12_11), .mode(1'b0)); +processing_element pe12_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_12_12_NC), .in_a_chain(a12_11to12_12), .in_b(b11_12to12_12), .in_c(matrixC11_12), .out_a(out_a_12_12_NC), .out_a_chain(a12_12to12_13), .out_b(b12_12to13_12), .out_b0(b12_12to13_12_ping), .out_b1(b12_12to13_12_pong), .out_c(matrixC12_12), .b_data_valid_ping(b_data_valid_ping_delay12_12), .b_data_valid_pong(b_data_valid_pong_delay12_12), .mode(1'b0)); +processing_element pe12_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_12_13_NC), .in_a_chain(a12_12to12_13), .in_b(b11_13to12_13), .in_c(matrixC11_13), .out_a(out_a_12_13_NC), .out_a_chain(a12_13to12_14), .out_b(b12_13to13_13), .out_b0(b12_13to13_13_ping), .out_b1(b12_13to13_13_pong), .out_c(matrixC12_13), .b_data_valid_ping(b_data_valid_ping_delay12_13), .b_data_valid_pong(b_data_valid_pong_delay12_13), .mode(1'b0)); +processing_element pe12_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_12_14_NC), .in_a_chain(a12_13to12_14), .in_b(b11_14to12_14), .in_c(matrixC11_14), .out_a(out_a_12_14_NC), .out_a_chain(a12_14to12_15), .out_b(b12_14to13_14), .out_b0(b12_14to13_14_ping), .out_b1(b12_14to13_14_pong), .out_c(matrixC12_14), .b_data_valid_ping(b_data_valid_ping_delay12_14), .b_data_valid_pong(b_data_valid_pong_delay12_14), .mode(1'b0)); +processing_element pe12_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_12_15_NC), .in_a_chain(a12_14to12_15), .in_b(b11_15to12_15), .in_c(matrixC11_15), .out_a(out_a_12_15_NC), .out_a_chain(a12_15to12_16), .out_b(b12_15to13_15), .out_b0(b12_15to13_15_ping), .out_b1(b12_15to13_15_pong), .out_c(matrixC12_15), .b_data_valid_ping(b_data_valid_ping_delay12_15), .b_data_valid_pong(b_data_valid_pong_delay12_15), .mode(1'b0)); +processing_element pe12_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_12_16_NC), .in_a_chain(a12_15to12_16), .in_b(b11_16to12_16), .in_c(matrixC11_16), .out_a(out_a_12_16_NC), .out_a_chain(a12_16to12_17), .out_b(b12_16to13_16), .out_b0(b12_16to13_16_ping), .out_b1(b12_16to13_16_pong), .out_c(matrixC12_16), .b_data_valid_ping(b_data_valid_ping_delay12_16), .b_data_valid_pong(b_data_valid_pong_delay12_16), .mode(1'b0)); +processing_element pe12_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_12_17_NC), .in_a_chain(a12_16to12_17), .in_b(b11_17to12_17), .in_c(matrixC11_17), .out_a(out_a_12_17_NC), .out_a_chain(a12_17to12_18), .out_b(b12_17to13_17), .out_b0(b12_17to13_17_ping), .out_b1(b12_17to13_17_pong), .out_c(matrixC12_17), .b_data_valid_ping(b_data_valid_ping_delay12_17), .b_data_valid_pong(b_data_valid_pong_delay12_17), .mode(1'b0)); +processing_element pe12_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_12_18_NC), .in_a_chain(a12_17to12_18), .in_b(b11_18to12_18), .in_c(matrixC11_18), .out_a(out_a_12_18_NC), .out_a_chain(a12_18to12_19), .out_b(b12_18to13_18), .out_b0(b12_18to13_18_ping), .out_b1(b12_18to13_18_pong), .out_c(matrixC12_18), .b_data_valid_ping(b_data_valid_ping_delay12_18), .b_data_valid_pong(b_data_valid_pong_delay12_18), .mode(1'b0)); +processing_element pe12_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_12_19_NC), .in_a_chain(a12_18to12_19), .in_b(b11_19to12_19), .in_c(matrixC11_19), .out_a(out_a_12_19_NC), .out_a_chain(a12_19to12_20), .out_b(b12_19to13_19), .out_b0(b12_19to13_19_ping), .out_b1(b12_19to13_19_pong), .out_c(matrixC12_19), .b_data_valid_ping(b_data_valid_ping_delay12_19), .b_data_valid_pong(b_data_valid_pong_delay12_19), .mode(1'b0)); +processing_element pe12_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_12_20_NC), .in_a_chain(a12_19to12_20), .in_b(b11_20to12_20), .in_c(matrixC11_20), .out_a(out_a_12_20_NC), .out_a_chain(a12_20to12_21), .out_b(b12_20to13_20), .out_b0(b12_20to13_20_ping), .out_b1(b12_20to13_20_pong), .out_c(matrixC12_20), .b_data_valid_ping(b_data_valid_ping_delay12_20), .b_data_valid_pong(b_data_valid_pong_delay12_20), .mode(1'b0)); +processing_element pe12_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_12_21_NC), .in_a_chain(a12_20to12_21), .in_b(b11_21to12_21), .in_c(matrixC11_21), .out_a(out_a_12_21_NC), .out_a_chain(a12_21to12_22), .out_b(b12_21to13_21), .out_b0(b12_21to13_21_ping), .out_b1(b12_21to13_21_pong), .out_c(matrixC12_21), .b_data_valid_ping(b_data_valid_ping_delay12_21), .b_data_valid_pong(b_data_valid_pong_delay12_21), .mode(1'b0)); +processing_element pe12_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_12_22_NC), .in_a_chain(a12_21to12_22), .in_b(b11_22to12_22), .in_c(matrixC11_22), .out_a(out_a_12_22_NC), .out_a_chain(a12_22to12_23), .out_b(b12_22to13_22), .out_b0(b12_22to13_22_ping), .out_b1(b12_22to13_22_pong), .out_c(matrixC12_22), .b_data_valid_ping(b_data_valid_ping_delay12_22), .b_data_valid_pong(b_data_valid_pong_delay12_22), .mode(1'b0)); +processing_element pe12_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_12_23_NC), .in_a_chain(a12_22to12_23), .in_b(b11_23to12_23), .in_c(matrixC11_23), .out_a(out_a_12_23_NC), .out_a_chain(a12_23to12_24), .out_b(b12_23to13_23), .out_b0(b12_23to13_23_ping), .out_b1(b12_23to13_23_pong), .out_c(matrixC12_23), .b_data_valid_ping(b_data_valid_ping_delay12_23), .b_data_valid_pong(b_data_valid_pong_delay12_23), .mode(1'b0)); +processing_element pe12_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_12_24_NC), .in_a_chain(a12_23to12_24), .in_b(b11_24to12_24), .in_c(matrixC11_24), .out_a(out_a_12_24_NC), .out_a_chain(a12_24to12_25), .out_b(b12_24to13_24), .out_b0(b12_24to13_24_ping), .out_b1(b12_24to13_24_pong), .out_c(matrixC12_24), .b_data_valid_ping(b_data_valid_ping_delay12_24), .b_data_valid_pong(b_data_valid_pong_delay12_24), .mode(1'b0)); +processing_element pe12_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_12_25_NC), .in_a_chain(a12_24to12_25), .in_b(b11_25to12_25), .in_c(matrixC11_25), .out_a(out_a_12_25_NC), .out_a_chain(a12_25to12_26), .out_b(b12_25to13_25), .out_b0(b12_25to13_25_ping), .out_b1(b12_25to13_25_pong), .out_c(matrixC12_25), .b_data_valid_ping(b_data_valid_ping_delay12_25), .b_data_valid_pong(b_data_valid_pong_delay12_25), .mode(1'b0)); +processing_element pe12_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_12_26_NC), .in_a_chain(a12_25to12_26), .in_b(b11_26to12_26), .in_c(matrixC11_26), .out_a(out_a_12_26_NC), .out_a_chain(a12_26to12_27), .out_b(b12_26to13_26), .out_b0(b12_26to13_26_ping), .out_b1(b12_26to13_26_pong), .out_c(matrixC12_26), .b_data_valid_ping(b_data_valid_ping_delay12_26), .b_data_valid_pong(b_data_valid_pong_delay12_26), .mode(1'b0)); +processing_element pe12_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_12_27_NC), .in_a_chain(a12_26to12_27), .in_b(b11_27to12_27), .in_c(matrixC11_27), .out_a(out_a_12_27_NC), .out_a_chain(a12_27to12_28), .out_b(b12_27to13_27), .out_b0(b12_27to13_27_ping), .out_b1(b12_27to13_27_pong), .out_c(matrixC12_27), .b_data_valid_ping(b_data_valid_ping_delay12_27), .b_data_valid_pong(b_data_valid_pong_delay12_27), .mode(1'b0)); +processing_element pe12_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_12_28_NC), .in_a_chain(a12_27to12_28), .in_b(b11_28to12_28), .in_c(matrixC11_28), .out_a(out_a_12_28_NC), .out_a_chain(a12_28to12_29), .out_b(b12_28to13_28), .out_b0(b12_28to13_28_ping), .out_b1(b12_28to13_28_pong), .out_c(matrixC12_28), .b_data_valid_ping(b_data_valid_ping_delay12_28), .b_data_valid_pong(b_data_valid_pong_delay12_28), .mode(1'b0)); +processing_element pe12_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_12_29_NC), .in_a_chain(a12_28to12_29), .in_b(b11_29to12_29), .in_c(matrixC11_29), .out_a(out_a_12_29_NC), .out_a_chain(a12_29to12_30), .out_b(b12_29to13_29), .out_b0(b12_29to13_29_ping), .out_b1(b12_29to13_29_pong), .out_c(matrixC12_29), .b_data_valid_ping(b_data_valid_ping_delay12_29), .b_data_valid_pong(b_data_valid_pong_delay12_29), .mode(1'b0)); +processing_element pe12_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_12_30_NC), .in_a_chain(a12_29to12_30), .in_b(b11_30to12_30), .in_c(matrixC11_30), .out_a(out_a_12_30_NC), .out_a_chain(a12_30to12_31), .out_b(b12_30to13_30), .out_b0(b12_30to13_30_ping), .out_b1(b12_30to13_30_pong), .out_c(matrixC12_30), .b_data_valid_ping(b_data_valid_ping_delay12_30), .b_data_valid_pong(b_data_valid_pong_delay12_30), .mode(1'b0)); +processing_element pe12_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_12_31_NC), .in_a_chain(a12_30to12_31), .in_b(b11_31to12_31), .in_c(matrixC11_31), .out_a(out_a_12_31_NC), .out_a_chain(a12_31to12_32), .out_b(b12_31to13_31), .out_b0(b12_31to13_31_ping), .out_b1(b12_31to13_31_pong), .out_c(matrixC12_31), .b_data_valid_ping(b_data_valid_ping_delay12_31), .b_data_valid_pong(b_data_valid_pong_delay12_31), .mode(1'b0)); +processing_element pe13_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(a13), .in_a_chain(in_a_chain_13_0_NC), .in_b(b12_0to13_0), .in_c(matrixC12_0), .out_a(out_a_13_0_NC), .out_a_chain(a13_0to13_1), .out_b(b13_0to14_0), .out_b0(b13_0to14_0_ping), .out_b1(b13_0to14_0_pong), .out_c(matrixC13_0), .b_data_valid_ping(b_data_valid_ping_delay13_0), .b_data_valid_pong(b_data_valid_pong_delay13_0), .mode(1'b1)); +processing_element pe13_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_13_1_NC), .in_a_chain(a13_0to13_1), .in_b(b12_1to13_1), .in_c(matrixC12_1), .out_a(out_a_13_1_NC), .out_a_chain(a13_1to13_2), .out_b(b13_1to14_1), .out_b0(b13_1to14_1_ping), .out_b1(b13_1to14_1_pong), .out_c(matrixC13_1), .b_data_valid_ping(b_data_valid_ping_delay13_1), .b_data_valid_pong(b_data_valid_pong_delay13_1), .mode(1'b0)); +processing_element pe13_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_13_2_NC), .in_a_chain(a13_1to13_2), .in_b(b12_2to13_2), .in_c(matrixC12_2), .out_a(out_a_13_2_NC), .out_a_chain(a13_2to13_3), .out_b(b13_2to14_2), .out_b0(b13_2to14_2_ping), .out_b1(b13_2to14_2_pong), .out_c(matrixC13_2), .b_data_valid_ping(b_data_valid_ping_delay13_2), .b_data_valid_pong(b_data_valid_pong_delay13_2), .mode(1'b0)); +processing_element pe13_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_13_3_NC), .in_a_chain(a13_2to13_3), .in_b(b12_3to13_3), .in_c(matrixC12_3), .out_a(out_a_13_3_NC), .out_a_chain(a13_3to13_4), .out_b(b13_3to14_3), .out_b0(b13_3to14_3_ping), .out_b1(b13_3to14_3_pong), .out_c(matrixC13_3), .b_data_valid_ping(b_data_valid_ping_delay13_3), .b_data_valid_pong(b_data_valid_pong_delay13_3), .mode(1'b0)); +processing_element pe13_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_13_4_NC), .in_a_chain(a13_3to13_4), .in_b(b12_4to13_4), .in_c(matrixC12_4), .out_a(out_a_13_4_NC), .out_a_chain(a13_4to13_5), .out_b(b13_4to14_4), .out_b0(b13_4to14_4_ping), .out_b1(b13_4to14_4_pong), .out_c(matrixC13_4), .b_data_valid_ping(b_data_valid_ping_delay13_4), .b_data_valid_pong(b_data_valid_pong_delay13_4), .mode(1'b0)); +processing_element pe13_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_13_5_NC), .in_a_chain(a13_4to13_5), .in_b(b12_5to13_5), .in_c(matrixC12_5), .out_a(out_a_13_5_NC), .out_a_chain(a13_5to13_6), .out_b(b13_5to14_5), .out_b0(b13_5to14_5_ping), .out_b1(b13_5to14_5_pong), .out_c(matrixC13_5), .b_data_valid_ping(b_data_valid_ping_delay13_5), .b_data_valid_pong(b_data_valid_pong_delay13_5), .mode(1'b0)); +processing_element pe13_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_13_6_NC), .in_a_chain(a13_5to13_6), .in_b(b12_6to13_6), .in_c(matrixC12_6), .out_a(out_a_13_6_NC), .out_a_chain(a13_6to13_7), .out_b(b13_6to14_6), .out_b0(b13_6to14_6_ping), .out_b1(b13_6to14_6_pong), .out_c(matrixC13_6), .b_data_valid_ping(b_data_valid_ping_delay13_6), .b_data_valid_pong(b_data_valid_pong_delay13_6), .mode(1'b0)); +processing_element pe13_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_13_7_NC), .in_a_chain(a13_6to13_7), .in_b(b12_7to13_7), .in_c(matrixC12_7), .out_a(out_a_13_7_NC), .out_a_chain(a13_7to13_8), .out_b(b13_7to14_7), .out_b0(b13_7to14_7_ping), .out_b1(b13_7to14_7_pong), .out_c(matrixC13_7), .b_data_valid_ping(b_data_valid_ping_delay13_7), .b_data_valid_pong(b_data_valid_pong_delay13_7), .mode(1'b0)); +processing_element pe13_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_13_8_NC), .in_a_chain(a13_7to13_8), .in_b(b12_8to13_8), .in_c(matrixC12_8), .out_a(out_a_13_8_NC), .out_a_chain(a13_8to13_9), .out_b(b13_8to14_8), .out_b0(b13_8to14_8_ping), .out_b1(b13_8to14_8_pong), .out_c(matrixC13_8), .b_data_valid_ping(b_data_valid_ping_delay13_8), .b_data_valid_pong(b_data_valid_pong_delay13_8), .mode(1'b0)); +processing_element pe13_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_13_9_NC), .in_a_chain(a13_8to13_9), .in_b(b12_9to13_9), .in_c(matrixC12_9), .out_a(out_a_13_9_NC), .out_a_chain(a13_9to13_10), .out_b(b13_9to14_9), .out_b0(b13_9to14_9_ping), .out_b1(b13_9to14_9_pong), .out_c(matrixC13_9), .b_data_valid_ping(b_data_valid_ping_delay13_9), .b_data_valid_pong(b_data_valid_pong_delay13_9), .mode(1'b0)); +processing_element pe13_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_13_10_NC), .in_a_chain(a13_9to13_10), .in_b(b12_10to13_10), .in_c(matrixC12_10), .out_a(out_a_13_10_NC), .out_a_chain(a13_10to13_11), .out_b(b13_10to14_10), .out_b0(b13_10to14_10_ping), .out_b1(b13_10to14_10_pong), .out_c(matrixC13_10), .b_data_valid_ping(b_data_valid_ping_delay13_10), .b_data_valid_pong(b_data_valid_pong_delay13_10), .mode(1'b0)); +processing_element pe13_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_13_11_NC), .in_a_chain(a13_10to13_11), .in_b(b12_11to13_11), .in_c(matrixC12_11), .out_a(out_a_13_11_NC), .out_a_chain(a13_11to13_12), .out_b(b13_11to14_11), .out_b0(b13_11to14_11_ping), .out_b1(b13_11to14_11_pong), .out_c(matrixC13_11), .b_data_valid_ping(b_data_valid_ping_delay13_11), .b_data_valid_pong(b_data_valid_pong_delay13_11), .mode(1'b0)); +processing_element pe13_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_13_12_NC), .in_a_chain(a13_11to13_12), .in_b(b12_12to13_12), .in_c(matrixC12_12), .out_a(out_a_13_12_NC), .out_a_chain(a13_12to13_13), .out_b(b13_12to14_12), .out_b0(b13_12to14_12_ping), .out_b1(b13_12to14_12_pong), .out_c(matrixC13_12), .b_data_valid_ping(b_data_valid_ping_delay13_12), .b_data_valid_pong(b_data_valid_pong_delay13_12), .mode(1'b0)); +processing_element pe13_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_13_13_NC), .in_a_chain(a13_12to13_13), .in_b(b12_13to13_13), .in_c(matrixC12_13), .out_a(out_a_13_13_NC), .out_a_chain(a13_13to13_14), .out_b(b13_13to14_13), .out_b0(b13_13to14_13_ping), .out_b1(b13_13to14_13_pong), .out_c(matrixC13_13), .b_data_valid_ping(b_data_valid_ping_delay13_13), .b_data_valid_pong(b_data_valid_pong_delay13_13), .mode(1'b0)); +processing_element pe13_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_13_14_NC), .in_a_chain(a13_13to13_14), .in_b(b12_14to13_14), .in_c(matrixC12_14), .out_a(out_a_13_14_NC), .out_a_chain(a13_14to13_15), .out_b(b13_14to14_14), .out_b0(b13_14to14_14_ping), .out_b1(b13_14to14_14_pong), .out_c(matrixC13_14), .b_data_valid_ping(b_data_valid_ping_delay13_14), .b_data_valid_pong(b_data_valid_pong_delay13_14), .mode(1'b0)); +processing_element pe13_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_13_15_NC), .in_a_chain(a13_14to13_15), .in_b(b12_15to13_15), .in_c(matrixC12_15), .out_a(out_a_13_15_NC), .out_a_chain(a13_15to13_16), .out_b(b13_15to14_15), .out_b0(b13_15to14_15_ping), .out_b1(b13_15to14_15_pong), .out_c(matrixC13_15), .b_data_valid_ping(b_data_valid_ping_delay13_15), .b_data_valid_pong(b_data_valid_pong_delay13_15), .mode(1'b0)); +processing_element pe13_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_13_16_NC), .in_a_chain(a13_15to13_16), .in_b(b12_16to13_16), .in_c(matrixC12_16), .out_a(out_a_13_16_NC), .out_a_chain(a13_16to13_17), .out_b(b13_16to14_16), .out_b0(b13_16to14_16_ping), .out_b1(b13_16to14_16_pong), .out_c(matrixC13_16), .b_data_valid_ping(b_data_valid_ping_delay13_16), .b_data_valid_pong(b_data_valid_pong_delay13_16), .mode(1'b0)); +processing_element pe13_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_13_17_NC), .in_a_chain(a13_16to13_17), .in_b(b12_17to13_17), .in_c(matrixC12_17), .out_a(out_a_13_17_NC), .out_a_chain(a13_17to13_18), .out_b(b13_17to14_17), .out_b0(b13_17to14_17_ping), .out_b1(b13_17to14_17_pong), .out_c(matrixC13_17), .b_data_valid_ping(b_data_valid_ping_delay13_17), .b_data_valid_pong(b_data_valid_pong_delay13_17), .mode(1'b0)); +processing_element pe13_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_13_18_NC), .in_a_chain(a13_17to13_18), .in_b(b12_18to13_18), .in_c(matrixC12_18), .out_a(out_a_13_18_NC), .out_a_chain(a13_18to13_19), .out_b(b13_18to14_18), .out_b0(b13_18to14_18_ping), .out_b1(b13_18to14_18_pong), .out_c(matrixC13_18), .b_data_valid_ping(b_data_valid_ping_delay13_18), .b_data_valid_pong(b_data_valid_pong_delay13_18), .mode(1'b0)); +processing_element pe13_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_13_19_NC), .in_a_chain(a13_18to13_19), .in_b(b12_19to13_19), .in_c(matrixC12_19), .out_a(out_a_13_19_NC), .out_a_chain(a13_19to13_20), .out_b(b13_19to14_19), .out_b0(b13_19to14_19_ping), .out_b1(b13_19to14_19_pong), .out_c(matrixC13_19), .b_data_valid_ping(b_data_valid_ping_delay13_19), .b_data_valid_pong(b_data_valid_pong_delay13_19), .mode(1'b0)); +processing_element pe13_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_13_20_NC), .in_a_chain(a13_19to13_20), .in_b(b12_20to13_20), .in_c(matrixC12_20), .out_a(out_a_13_20_NC), .out_a_chain(a13_20to13_21), .out_b(b13_20to14_20), .out_b0(b13_20to14_20_ping), .out_b1(b13_20to14_20_pong), .out_c(matrixC13_20), .b_data_valid_ping(b_data_valid_ping_delay13_20), .b_data_valid_pong(b_data_valid_pong_delay13_20), .mode(1'b0)); +processing_element pe13_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_13_21_NC), .in_a_chain(a13_20to13_21), .in_b(b12_21to13_21), .in_c(matrixC12_21), .out_a(out_a_13_21_NC), .out_a_chain(a13_21to13_22), .out_b(b13_21to14_21), .out_b0(b13_21to14_21_ping), .out_b1(b13_21to14_21_pong), .out_c(matrixC13_21), .b_data_valid_ping(b_data_valid_ping_delay13_21), .b_data_valid_pong(b_data_valid_pong_delay13_21), .mode(1'b0)); +processing_element pe13_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_13_22_NC), .in_a_chain(a13_21to13_22), .in_b(b12_22to13_22), .in_c(matrixC12_22), .out_a(out_a_13_22_NC), .out_a_chain(a13_22to13_23), .out_b(b13_22to14_22), .out_b0(b13_22to14_22_ping), .out_b1(b13_22to14_22_pong), .out_c(matrixC13_22), .b_data_valid_ping(b_data_valid_ping_delay13_22), .b_data_valid_pong(b_data_valid_pong_delay13_22), .mode(1'b0)); +processing_element pe13_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_13_23_NC), .in_a_chain(a13_22to13_23), .in_b(b12_23to13_23), .in_c(matrixC12_23), .out_a(out_a_13_23_NC), .out_a_chain(a13_23to13_24), .out_b(b13_23to14_23), .out_b0(b13_23to14_23_ping), .out_b1(b13_23to14_23_pong), .out_c(matrixC13_23), .b_data_valid_ping(b_data_valid_ping_delay13_23), .b_data_valid_pong(b_data_valid_pong_delay13_23), .mode(1'b0)); +processing_element pe13_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_13_24_NC), .in_a_chain(a13_23to13_24), .in_b(b12_24to13_24), .in_c(matrixC12_24), .out_a(out_a_13_24_NC), .out_a_chain(a13_24to13_25), .out_b(b13_24to14_24), .out_b0(b13_24to14_24_ping), .out_b1(b13_24to14_24_pong), .out_c(matrixC13_24), .b_data_valid_ping(b_data_valid_ping_delay13_24), .b_data_valid_pong(b_data_valid_pong_delay13_24), .mode(1'b0)); +processing_element pe13_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_13_25_NC), .in_a_chain(a13_24to13_25), .in_b(b12_25to13_25), .in_c(matrixC12_25), .out_a(out_a_13_25_NC), .out_a_chain(a13_25to13_26), .out_b(b13_25to14_25), .out_b0(b13_25to14_25_ping), .out_b1(b13_25to14_25_pong), .out_c(matrixC13_25), .b_data_valid_ping(b_data_valid_ping_delay13_25), .b_data_valid_pong(b_data_valid_pong_delay13_25), .mode(1'b0)); +processing_element pe13_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_13_26_NC), .in_a_chain(a13_25to13_26), .in_b(b12_26to13_26), .in_c(matrixC12_26), .out_a(out_a_13_26_NC), .out_a_chain(a13_26to13_27), .out_b(b13_26to14_26), .out_b0(b13_26to14_26_ping), .out_b1(b13_26to14_26_pong), .out_c(matrixC13_26), .b_data_valid_ping(b_data_valid_ping_delay13_26), .b_data_valid_pong(b_data_valid_pong_delay13_26), .mode(1'b0)); +processing_element pe13_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_13_27_NC), .in_a_chain(a13_26to13_27), .in_b(b12_27to13_27), .in_c(matrixC12_27), .out_a(out_a_13_27_NC), .out_a_chain(a13_27to13_28), .out_b(b13_27to14_27), .out_b0(b13_27to14_27_ping), .out_b1(b13_27to14_27_pong), .out_c(matrixC13_27), .b_data_valid_ping(b_data_valid_ping_delay13_27), .b_data_valid_pong(b_data_valid_pong_delay13_27), .mode(1'b0)); +processing_element pe13_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_13_28_NC), .in_a_chain(a13_27to13_28), .in_b(b12_28to13_28), .in_c(matrixC12_28), .out_a(out_a_13_28_NC), .out_a_chain(a13_28to13_29), .out_b(b13_28to14_28), .out_b0(b13_28to14_28_ping), .out_b1(b13_28to14_28_pong), .out_c(matrixC13_28), .b_data_valid_ping(b_data_valid_ping_delay13_28), .b_data_valid_pong(b_data_valid_pong_delay13_28), .mode(1'b0)); +processing_element pe13_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_13_29_NC), .in_a_chain(a13_28to13_29), .in_b(b12_29to13_29), .in_c(matrixC12_29), .out_a(out_a_13_29_NC), .out_a_chain(a13_29to13_30), .out_b(b13_29to14_29), .out_b0(b13_29to14_29_ping), .out_b1(b13_29to14_29_pong), .out_c(matrixC13_29), .b_data_valid_ping(b_data_valid_ping_delay13_29), .b_data_valid_pong(b_data_valid_pong_delay13_29), .mode(1'b0)); +processing_element pe13_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_13_30_NC), .in_a_chain(a13_29to13_30), .in_b(b12_30to13_30), .in_c(matrixC12_30), .out_a(out_a_13_30_NC), .out_a_chain(a13_30to13_31), .out_b(b13_30to14_30), .out_b0(b13_30to14_30_ping), .out_b1(b13_30to14_30_pong), .out_c(matrixC13_30), .b_data_valid_ping(b_data_valid_ping_delay13_30), .b_data_valid_pong(b_data_valid_pong_delay13_30), .mode(1'b0)); +processing_element pe13_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_13_31_NC), .in_a_chain(a13_30to13_31), .in_b(b12_31to13_31), .in_c(matrixC12_31), .out_a(out_a_13_31_NC), .out_a_chain(a13_31to13_32), .out_b(b13_31to14_31), .out_b0(b13_31to14_31_ping), .out_b1(b13_31to14_31_pong), .out_c(matrixC13_31), .b_data_valid_ping(b_data_valid_ping_delay13_31), .b_data_valid_pong(b_data_valid_pong_delay13_31), .mode(1'b0)); +processing_element pe14_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(a14), .in_a_chain(in_a_chain_14_0_NC), .in_b(b13_0to14_0), .in_c(matrixC13_0), .out_a(out_a_14_0_NC), .out_a_chain(a14_0to14_1), .out_b(b14_0to15_0), .out_b0(b14_0to15_0_ping), .out_b1(b14_0to15_0_pong), .out_c(matrixC14_0), .b_data_valid_ping(b_data_valid_ping_delay14_0), .b_data_valid_pong(b_data_valid_pong_delay14_0), .mode(1'b1)); +processing_element pe14_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_14_1_NC), .in_a_chain(a14_0to14_1), .in_b(b13_1to14_1), .in_c(matrixC13_1), .out_a(out_a_14_1_NC), .out_a_chain(a14_1to14_2), .out_b(b14_1to15_1), .out_b0(b14_1to15_1_ping), .out_b1(b14_1to15_1_pong), .out_c(matrixC14_1), .b_data_valid_ping(b_data_valid_ping_delay14_1), .b_data_valid_pong(b_data_valid_pong_delay14_1), .mode(1'b0)); +processing_element pe14_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_14_2_NC), .in_a_chain(a14_1to14_2), .in_b(b13_2to14_2), .in_c(matrixC13_2), .out_a(out_a_14_2_NC), .out_a_chain(a14_2to14_3), .out_b(b14_2to15_2), .out_b0(b14_2to15_2_ping), .out_b1(b14_2to15_2_pong), .out_c(matrixC14_2), .b_data_valid_ping(b_data_valid_ping_delay14_2), .b_data_valid_pong(b_data_valid_pong_delay14_2), .mode(1'b0)); +processing_element pe14_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_14_3_NC), .in_a_chain(a14_2to14_3), .in_b(b13_3to14_3), .in_c(matrixC13_3), .out_a(out_a_14_3_NC), .out_a_chain(a14_3to14_4), .out_b(b14_3to15_3), .out_b0(b14_3to15_3_ping), .out_b1(b14_3to15_3_pong), .out_c(matrixC14_3), .b_data_valid_ping(b_data_valid_ping_delay14_3), .b_data_valid_pong(b_data_valid_pong_delay14_3), .mode(1'b0)); +processing_element pe14_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_14_4_NC), .in_a_chain(a14_3to14_4), .in_b(b13_4to14_4), .in_c(matrixC13_4), .out_a(out_a_14_4_NC), .out_a_chain(a14_4to14_5), .out_b(b14_4to15_4), .out_b0(b14_4to15_4_ping), .out_b1(b14_4to15_4_pong), .out_c(matrixC14_4), .b_data_valid_ping(b_data_valid_ping_delay14_4), .b_data_valid_pong(b_data_valid_pong_delay14_4), .mode(1'b0)); +processing_element pe14_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_14_5_NC), .in_a_chain(a14_4to14_5), .in_b(b13_5to14_5), .in_c(matrixC13_5), .out_a(out_a_14_5_NC), .out_a_chain(a14_5to14_6), .out_b(b14_5to15_5), .out_b0(b14_5to15_5_ping), .out_b1(b14_5to15_5_pong), .out_c(matrixC14_5), .b_data_valid_ping(b_data_valid_ping_delay14_5), .b_data_valid_pong(b_data_valid_pong_delay14_5), .mode(1'b0)); +processing_element pe14_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_14_6_NC), .in_a_chain(a14_5to14_6), .in_b(b13_6to14_6), .in_c(matrixC13_6), .out_a(out_a_14_6_NC), .out_a_chain(a14_6to14_7), .out_b(b14_6to15_6), .out_b0(b14_6to15_6_ping), .out_b1(b14_6to15_6_pong), .out_c(matrixC14_6), .b_data_valid_ping(b_data_valid_ping_delay14_6), .b_data_valid_pong(b_data_valid_pong_delay14_6), .mode(1'b0)); +processing_element pe14_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_14_7_NC), .in_a_chain(a14_6to14_7), .in_b(b13_7to14_7), .in_c(matrixC13_7), .out_a(out_a_14_7_NC), .out_a_chain(a14_7to14_8), .out_b(b14_7to15_7), .out_b0(b14_7to15_7_ping), .out_b1(b14_7to15_7_pong), .out_c(matrixC14_7), .b_data_valid_ping(b_data_valid_ping_delay14_7), .b_data_valid_pong(b_data_valid_pong_delay14_7), .mode(1'b0)); +processing_element pe14_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_14_8_NC), .in_a_chain(a14_7to14_8), .in_b(b13_8to14_8), .in_c(matrixC13_8), .out_a(out_a_14_8_NC), .out_a_chain(a14_8to14_9), .out_b(b14_8to15_8), .out_b0(b14_8to15_8_ping), .out_b1(b14_8to15_8_pong), .out_c(matrixC14_8), .b_data_valid_ping(b_data_valid_ping_delay14_8), .b_data_valid_pong(b_data_valid_pong_delay14_8), .mode(1'b0)); +processing_element pe14_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_14_9_NC), .in_a_chain(a14_8to14_9), .in_b(b13_9to14_9), .in_c(matrixC13_9), .out_a(out_a_14_9_NC), .out_a_chain(a14_9to14_10), .out_b(b14_9to15_9), .out_b0(b14_9to15_9_ping), .out_b1(b14_9to15_9_pong), .out_c(matrixC14_9), .b_data_valid_ping(b_data_valid_ping_delay14_9), .b_data_valid_pong(b_data_valid_pong_delay14_9), .mode(1'b0)); +processing_element pe14_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_14_10_NC), .in_a_chain(a14_9to14_10), .in_b(b13_10to14_10), .in_c(matrixC13_10), .out_a(out_a_14_10_NC), .out_a_chain(a14_10to14_11), .out_b(b14_10to15_10), .out_b0(b14_10to15_10_ping), .out_b1(b14_10to15_10_pong), .out_c(matrixC14_10), .b_data_valid_ping(b_data_valid_ping_delay14_10), .b_data_valid_pong(b_data_valid_pong_delay14_10), .mode(1'b0)); +processing_element pe14_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_14_11_NC), .in_a_chain(a14_10to14_11), .in_b(b13_11to14_11), .in_c(matrixC13_11), .out_a(out_a_14_11_NC), .out_a_chain(a14_11to14_12), .out_b(b14_11to15_11), .out_b0(b14_11to15_11_ping), .out_b1(b14_11to15_11_pong), .out_c(matrixC14_11), .b_data_valid_ping(b_data_valid_ping_delay14_11), .b_data_valid_pong(b_data_valid_pong_delay14_11), .mode(1'b0)); +processing_element pe14_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_14_12_NC), .in_a_chain(a14_11to14_12), .in_b(b13_12to14_12), .in_c(matrixC13_12), .out_a(out_a_14_12_NC), .out_a_chain(a14_12to14_13), .out_b(b14_12to15_12), .out_b0(b14_12to15_12_ping), .out_b1(b14_12to15_12_pong), .out_c(matrixC14_12), .b_data_valid_ping(b_data_valid_ping_delay14_12), .b_data_valid_pong(b_data_valid_pong_delay14_12), .mode(1'b0)); +processing_element pe14_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_14_13_NC), .in_a_chain(a14_12to14_13), .in_b(b13_13to14_13), .in_c(matrixC13_13), .out_a(out_a_14_13_NC), .out_a_chain(a14_13to14_14), .out_b(b14_13to15_13), .out_b0(b14_13to15_13_ping), .out_b1(b14_13to15_13_pong), .out_c(matrixC14_13), .b_data_valid_ping(b_data_valid_ping_delay14_13), .b_data_valid_pong(b_data_valid_pong_delay14_13), .mode(1'b0)); +processing_element pe14_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_14_14_NC), .in_a_chain(a14_13to14_14), .in_b(b13_14to14_14), .in_c(matrixC13_14), .out_a(out_a_14_14_NC), .out_a_chain(a14_14to14_15), .out_b(b14_14to15_14), .out_b0(b14_14to15_14_ping), .out_b1(b14_14to15_14_pong), .out_c(matrixC14_14), .b_data_valid_ping(b_data_valid_ping_delay14_14), .b_data_valid_pong(b_data_valid_pong_delay14_14), .mode(1'b0)); +processing_element pe14_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_14_15_NC), .in_a_chain(a14_14to14_15), .in_b(b13_15to14_15), .in_c(matrixC13_15), .out_a(out_a_14_15_NC), .out_a_chain(a14_15to14_16), .out_b(b14_15to15_15), .out_b0(b14_15to15_15_ping), .out_b1(b14_15to15_15_pong), .out_c(matrixC14_15), .b_data_valid_ping(b_data_valid_ping_delay14_15), .b_data_valid_pong(b_data_valid_pong_delay14_15), .mode(1'b0)); +processing_element pe14_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_14_16_NC), .in_a_chain(a14_15to14_16), .in_b(b13_16to14_16), .in_c(matrixC13_16), .out_a(out_a_14_16_NC), .out_a_chain(a14_16to14_17), .out_b(b14_16to15_16), .out_b0(b14_16to15_16_ping), .out_b1(b14_16to15_16_pong), .out_c(matrixC14_16), .b_data_valid_ping(b_data_valid_ping_delay14_16), .b_data_valid_pong(b_data_valid_pong_delay14_16), .mode(1'b0)); +processing_element pe14_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_14_17_NC), .in_a_chain(a14_16to14_17), .in_b(b13_17to14_17), .in_c(matrixC13_17), .out_a(out_a_14_17_NC), .out_a_chain(a14_17to14_18), .out_b(b14_17to15_17), .out_b0(b14_17to15_17_ping), .out_b1(b14_17to15_17_pong), .out_c(matrixC14_17), .b_data_valid_ping(b_data_valid_ping_delay14_17), .b_data_valid_pong(b_data_valid_pong_delay14_17), .mode(1'b0)); +processing_element pe14_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_14_18_NC), .in_a_chain(a14_17to14_18), .in_b(b13_18to14_18), .in_c(matrixC13_18), .out_a(out_a_14_18_NC), .out_a_chain(a14_18to14_19), .out_b(b14_18to15_18), .out_b0(b14_18to15_18_ping), .out_b1(b14_18to15_18_pong), .out_c(matrixC14_18), .b_data_valid_ping(b_data_valid_ping_delay14_18), .b_data_valid_pong(b_data_valid_pong_delay14_18), .mode(1'b0)); +processing_element pe14_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_14_19_NC), .in_a_chain(a14_18to14_19), .in_b(b13_19to14_19), .in_c(matrixC13_19), .out_a(out_a_14_19_NC), .out_a_chain(a14_19to14_20), .out_b(b14_19to15_19), .out_b0(b14_19to15_19_ping), .out_b1(b14_19to15_19_pong), .out_c(matrixC14_19), .b_data_valid_ping(b_data_valid_ping_delay14_19), .b_data_valid_pong(b_data_valid_pong_delay14_19), .mode(1'b0)); +processing_element pe14_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_14_20_NC), .in_a_chain(a14_19to14_20), .in_b(b13_20to14_20), .in_c(matrixC13_20), .out_a(out_a_14_20_NC), .out_a_chain(a14_20to14_21), .out_b(b14_20to15_20), .out_b0(b14_20to15_20_ping), .out_b1(b14_20to15_20_pong), .out_c(matrixC14_20), .b_data_valid_ping(b_data_valid_ping_delay14_20), .b_data_valid_pong(b_data_valid_pong_delay14_20), .mode(1'b0)); +processing_element pe14_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_14_21_NC), .in_a_chain(a14_20to14_21), .in_b(b13_21to14_21), .in_c(matrixC13_21), .out_a(out_a_14_21_NC), .out_a_chain(a14_21to14_22), .out_b(b14_21to15_21), .out_b0(b14_21to15_21_ping), .out_b1(b14_21to15_21_pong), .out_c(matrixC14_21), .b_data_valid_ping(b_data_valid_ping_delay14_21), .b_data_valid_pong(b_data_valid_pong_delay14_21), .mode(1'b0)); +processing_element pe14_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_14_22_NC), .in_a_chain(a14_21to14_22), .in_b(b13_22to14_22), .in_c(matrixC13_22), .out_a(out_a_14_22_NC), .out_a_chain(a14_22to14_23), .out_b(b14_22to15_22), .out_b0(b14_22to15_22_ping), .out_b1(b14_22to15_22_pong), .out_c(matrixC14_22), .b_data_valid_ping(b_data_valid_ping_delay14_22), .b_data_valid_pong(b_data_valid_pong_delay14_22), .mode(1'b0)); +processing_element pe14_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_14_23_NC), .in_a_chain(a14_22to14_23), .in_b(b13_23to14_23), .in_c(matrixC13_23), .out_a(out_a_14_23_NC), .out_a_chain(a14_23to14_24), .out_b(b14_23to15_23), .out_b0(b14_23to15_23_ping), .out_b1(b14_23to15_23_pong), .out_c(matrixC14_23), .b_data_valid_ping(b_data_valid_ping_delay14_23), .b_data_valid_pong(b_data_valid_pong_delay14_23), .mode(1'b0)); +processing_element pe14_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_14_24_NC), .in_a_chain(a14_23to14_24), .in_b(b13_24to14_24), .in_c(matrixC13_24), .out_a(out_a_14_24_NC), .out_a_chain(a14_24to14_25), .out_b(b14_24to15_24), .out_b0(b14_24to15_24_ping), .out_b1(b14_24to15_24_pong), .out_c(matrixC14_24), .b_data_valid_ping(b_data_valid_ping_delay14_24), .b_data_valid_pong(b_data_valid_pong_delay14_24), .mode(1'b0)); +processing_element pe14_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_14_25_NC), .in_a_chain(a14_24to14_25), .in_b(b13_25to14_25), .in_c(matrixC13_25), .out_a(out_a_14_25_NC), .out_a_chain(a14_25to14_26), .out_b(b14_25to15_25), .out_b0(b14_25to15_25_ping), .out_b1(b14_25to15_25_pong), .out_c(matrixC14_25), .b_data_valid_ping(b_data_valid_ping_delay14_25), .b_data_valid_pong(b_data_valid_pong_delay14_25), .mode(1'b0)); +processing_element pe14_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_14_26_NC), .in_a_chain(a14_25to14_26), .in_b(b13_26to14_26), .in_c(matrixC13_26), .out_a(out_a_14_26_NC), .out_a_chain(a14_26to14_27), .out_b(b14_26to15_26), .out_b0(b14_26to15_26_ping), .out_b1(b14_26to15_26_pong), .out_c(matrixC14_26), .b_data_valid_ping(b_data_valid_ping_delay14_26), .b_data_valid_pong(b_data_valid_pong_delay14_26), .mode(1'b0)); +processing_element pe14_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_14_27_NC), .in_a_chain(a14_26to14_27), .in_b(b13_27to14_27), .in_c(matrixC13_27), .out_a(out_a_14_27_NC), .out_a_chain(a14_27to14_28), .out_b(b14_27to15_27), .out_b0(b14_27to15_27_ping), .out_b1(b14_27to15_27_pong), .out_c(matrixC14_27), .b_data_valid_ping(b_data_valid_ping_delay14_27), .b_data_valid_pong(b_data_valid_pong_delay14_27), .mode(1'b0)); +processing_element pe14_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_14_28_NC), .in_a_chain(a14_27to14_28), .in_b(b13_28to14_28), .in_c(matrixC13_28), .out_a(out_a_14_28_NC), .out_a_chain(a14_28to14_29), .out_b(b14_28to15_28), .out_b0(b14_28to15_28_ping), .out_b1(b14_28to15_28_pong), .out_c(matrixC14_28), .b_data_valid_ping(b_data_valid_ping_delay14_28), .b_data_valid_pong(b_data_valid_pong_delay14_28), .mode(1'b0)); +processing_element pe14_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_14_29_NC), .in_a_chain(a14_28to14_29), .in_b(b13_29to14_29), .in_c(matrixC13_29), .out_a(out_a_14_29_NC), .out_a_chain(a14_29to14_30), .out_b(b14_29to15_29), .out_b0(b14_29to15_29_ping), .out_b1(b14_29to15_29_pong), .out_c(matrixC14_29), .b_data_valid_ping(b_data_valid_ping_delay14_29), .b_data_valid_pong(b_data_valid_pong_delay14_29), .mode(1'b0)); +processing_element pe14_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_14_30_NC), .in_a_chain(a14_29to14_30), .in_b(b13_30to14_30), .in_c(matrixC13_30), .out_a(out_a_14_30_NC), .out_a_chain(a14_30to14_31), .out_b(b14_30to15_30), .out_b0(b14_30to15_30_ping), .out_b1(b14_30to15_30_pong), .out_c(matrixC14_30), .b_data_valid_ping(b_data_valid_ping_delay14_30), .b_data_valid_pong(b_data_valid_pong_delay14_30), .mode(1'b0)); +processing_element pe14_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_14_31_NC), .in_a_chain(a14_30to14_31), .in_b(b13_31to14_31), .in_c(matrixC13_31), .out_a(out_a_14_31_NC), .out_a_chain(a14_31to14_32), .out_b(b14_31to15_31), .out_b0(b14_31to15_31_ping), .out_b1(b14_31to15_31_pong), .out_c(matrixC14_31), .b_data_valid_ping(b_data_valid_ping_delay14_31), .b_data_valid_pong(b_data_valid_pong_delay14_31), .mode(1'b0)); +processing_element pe15_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(a15), .in_a_chain(in_a_chain_15_0_NC), .in_b(b14_0to15_0), .in_c(matrixC14_0), .out_a(out_a_15_0_NC), .out_a_chain(a15_0to15_1), .out_b(b15_0to16_0), .out_b0(b15_0to16_0_ping), .out_b1(b15_0to16_0_pong), .out_c(matrixC15_0), .b_data_valid_ping(b_data_valid_ping_delay15_0), .b_data_valid_pong(b_data_valid_pong_delay15_0), .mode(1'b1)); +processing_element pe15_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_15_1_NC), .in_a_chain(a15_0to15_1), .in_b(b14_1to15_1), .in_c(matrixC14_1), .out_a(out_a_15_1_NC), .out_a_chain(a15_1to15_2), .out_b(b15_1to16_1), .out_b0(b15_1to16_1_ping), .out_b1(b15_1to16_1_pong), .out_c(matrixC15_1), .b_data_valid_ping(b_data_valid_ping_delay15_1), .b_data_valid_pong(b_data_valid_pong_delay15_1), .mode(1'b0)); +processing_element pe15_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_15_2_NC), .in_a_chain(a15_1to15_2), .in_b(b14_2to15_2), .in_c(matrixC14_2), .out_a(out_a_15_2_NC), .out_a_chain(a15_2to15_3), .out_b(b15_2to16_2), .out_b0(b15_2to16_2_ping), .out_b1(b15_2to16_2_pong), .out_c(matrixC15_2), .b_data_valid_ping(b_data_valid_ping_delay15_2), .b_data_valid_pong(b_data_valid_pong_delay15_2), .mode(1'b0)); +processing_element pe15_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_15_3_NC), .in_a_chain(a15_2to15_3), .in_b(b14_3to15_3), .in_c(matrixC14_3), .out_a(out_a_15_3_NC), .out_a_chain(a15_3to15_4), .out_b(b15_3to16_3), .out_b0(b15_3to16_3_ping), .out_b1(b15_3to16_3_pong), .out_c(matrixC15_3), .b_data_valid_ping(b_data_valid_ping_delay15_3), .b_data_valid_pong(b_data_valid_pong_delay15_3), .mode(1'b0)); +processing_element pe15_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_15_4_NC), .in_a_chain(a15_3to15_4), .in_b(b14_4to15_4), .in_c(matrixC14_4), .out_a(out_a_15_4_NC), .out_a_chain(a15_4to15_5), .out_b(b15_4to16_4), .out_b0(b15_4to16_4_ping), .out_b1(b15_4to16_4_pong), .out_c(matrixC15_4), .b_data_valid_ping(b_data_valid_ping_delay15_4), .b_data_valid_pong(b_data_valid_pong_delay15_4), .mode(1'b0)); +processing_element pe15_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_15_5_NC), .in_a_chain(a15_4to15_5), .in_b(b14_5to15_5), .in_c(matrixC14_5), .out_a(out_a_15_5_NC), .out_a_chain(a15_5to15_6), .out_b(b15_5to16_5), .out_b0(b15_5to16_5_ping), .out_b1(b15_5to16_5_pong), .out_c(matrixC15_5), .b_data_valid_ping(b_data_valid_ping_delay15_5), .b_data_valid_pong(b_data_valid_pong_delay15_5), .mode(1'b0)); +processing_element pe15_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_15_6_NC), .in_a_chain(a15_5to15_6), .in_b(b14_6to15_6), .in_c(matrixC14_6), .out_a(out_a_15_6_NC), .out_a_chain(a15_6to15_7), .out_b(b15_6to16_6), .out_b0(b15_6to16_6_ping), .out_b1(b15_6to16_6_pong), .out_c(matrixC15_6), .b_data_valid_ping(b_data_valid_ping_delay15_6), .b_data_valid_pong(b_data_valid_pong_delay15_6), .mode(1'b0)); +processing_element pe15_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_15_7_NC), .in_a_chain(a15_6to15_7), .in_b(b14_7to15_7), .in_c(matrixC14_7), .out_a(out_a_15_7_NC), .out_a_chain(a15_7to15_8), .out_b(b15_7to16_7), .out_b0(b15_7to16_7_ping), .out_b1(b15_7to16_7_pong), .out_c(matrixC15_7), .b_data_valid_ping(b_data_valid_ping_delay15_7), .b_data_valid_pong(b_data_valid_pong_delay15_7), .mode(1'b0)); +processing_element pe15_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_15_8_NC), .in_a_chain(a15_7to15_8), .in_b(b14_8to15_8), .in_c(matrixC14_8), .out_a(out_a_15_8_NC), .out_a_chain(a15_8to15_9), .out_b(b15_8to16_8), .out_b0(b15_8to16_8_ping), .out_b1(b15_8to16_8_pong), .out_c(matrixC15_8), .b_data_valid_ping(b_data_valid_ping_delay15_8), .b_data_valid_pong(b_data_valid_pong_delay15_8), .mode(1'b0)); +processing_element pe15_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_15_9_NC), .in_a_chain(a15_8to15_9), .in_b(b14_9to15_9), .in_c(matrixC14_9), .out_a(out_a_15_9_NC), .out_a_chain(a15_9to15_10), .out_b(b15_9to16_9), .out_b0(b15_9to16_9_ping), .out_b1(b15_9to16_9_pong), .out_c(matrixC15_9), .b_data_valid_ping(b_data_valid_ping_delay15_9), .b_data_valid_pong(b_data_valid_pong_delay15_9), .mode(1'b0)); +processing_element pe15_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_15_10_NC), .in_a_chain(a15_9to15_10), .in_b(b14_10to15_10), .in_c(matrixC14_10), .out_a(out_a_15_10_NC), .out_a_chain(a15_10to15_11), .out_b(b15_10to16_10), .out_b0(b15_10to16_10_ping), .out_b1(b15_10to16_10_pong), .out_c(matrixC15_10), .b_data_valid_ping(b_data_valid_ping_delay15_10), .b_data_valid_pong(b_data_valid_pong_delay15_10), .mode(1'b0)); +processing_element pe15_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_15_11_NC), .in_a_chain(a15_10to15_11), .in_b(b14_11to15_11), .in_c(matrixC14_11), .out_a(out_a_15_11_NC), .out_a_chain(a15_11to15_12), .out_b(b15_11to16_11), .out_b0(b15_11to16_11_ping), .out_b1(b15_11to16_11_pong), .out_c(matrixC15_11), .b_data_valid_ping(b_data_valid_ping_delay15_11), .b_data_valid_pong(b_data_valid_pong_delay15_11), .mode(1'b0)); +processing_element pe15_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_15_12_NC), .in_a_chain(a15_11to15_12), .in_b(b14_12to15_12), .in_c(matrixC14_12), .out_a(out_a_15_12_NC), .out_a_chain(a15_12to15_13), .out_b(b15_12to16_12), .out_b0(b15_12to16_12_ping), .out_b1(b15_12to16_12_pong), .out_c(matrixC15_12), .b_data_valid_ping(b_data_valid_ping_delay15_12), .b_data_valid_pong(b_data_valid_pong_delay15_12), .mode(1'b0)); +processing_element pe15_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_15_13_NC), .in_a_chain(a15_12to15_13), .in_b(b14_13to15_13), .in_c(matrixC14_13), .out_a(out_a_15_13_NC), .out_a_chain(a15_13to15_14), .out_b(b15_13to16_13), .out_b0(b15_13to16_13_ping), .out_b1(b15_13to16_13_pong), .out_c(matrixC15_13), .b_data_valid_ping(b_data_valid_ping_delay15_13), .b_data_valid_pong(b_data_valid_pong_delay15_13), .mode(1'b0)); +processing_element pe15_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_15_14_NC), .in_a_chain(a15_13to15_14), .in_b(b14_14to15_14), .in_c(matrixC14_14), .out_a(out_a_15_14_NC), .out_a_chain(a15_14to15_15), .out_b(b15_14to16_14), .out_b0(b15_14to16_14_ping), .out_b1(b15_14to16_14_pong), .out_c(matrixC15_14), .b_data_valid_ping(b_data_valid_ping_delay15_14), .b_data_valid_pong(b_data_valid_pong_delay15_14), .mode(1'b0)); +processing_element pe15_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_15_15_NC), .in_a_chain(a15_14to15_15), .in_b(b14_15to15_15), .in_c(matrixC14_15), .out_a(out_a_15_15_NC), .out_a_chain(a15_15to15_16), .out_b(b15_15to16_15), .out_b0(b15_15to16_15_ping), .out_b1(b15_15to16_15_pong), .out_c(matrixC15_15), .b_data_valid_ping(b_data_valid_ping_delay15_15), .b_data_valid_pong(b_data_valid_pong_delay15_15), .mode(1'b0)); +processing_element pe15_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_15_16_NC), .in_a_chain(a15_15to15_16), .in_b(b14_16to15_16), .in_c(matrixC14_16), .out_a(out_a_15_16_NC), .out_a_chain(a15_16to15_17), .out_b(b15_16to16_16), .out_b0(b15_16to16_16_ping), .out_b1(b15_16to16_16_pong), .out_c(matrixC15_16), .b_data_valid_ping(b_data_valid_ping_delay15_16), .b_data_valid_pong(b_data_valid_pong_delay15_16), .mode(1'b0)); +processing_element pe15_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_15_17_NC), .in_a_chain(a15_16to15_17), .in_b(b14_17to15_17), .in_c(matrixC14_17), .out_a(out_a_15_17_NC), .out_a_chain(a15_17to15_18), .out_b(b15_17to16_17), .out_b0(b15_17to16_17_ping), .out_b1(b15_17to16_17_pong), .out_c(matrixC15_17), .b_data_valid_ping(b_data_valid_ping_delay15_17), .b_data_valid_pong(b_data_valid_pong_delay15_17), .mode(1'b0)); +processing_element pe15_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_15_18_NC), .in_a_chain(a15_17to15_18), .in_b(b14_18to15_18), .in_c(matrixC14_18), .out_a(out_a_15_18_NC), .out_a_chain(a15_18to15_19), .out_b(b15_18to16_18), .out_b0(b15_18to16_18_ping), .out_b1(b15_18to16_18_pong), .out_c(matrixC15_18), .b_data_valid_ping(b_data_valid_ping_delay15_18), .b_data_valid_pong(b_data_valid_pong_delay15_18), .mode(1'b0)); +processing_element pe15_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_15_19_NC), .in_a_chain(a15_18to15_19), .in_b(b14_19to15_19), .in_c(matrixC14_19), .out_a(out_a_15_19_NC), .out_a_chain(a15_19to15_20), .out_b(b15_19to16_19), .out_b0(b15_19to16_19_ping), .out_b1(b15_19to16_19_pong), .out_c(matrixC15_19), .b_data_valid_ping(b_data_valid_ping_delay15_19), .b_data_valid_pong(b_data_valid_pong_delay15_19), .mode(1'b0)); +processing_element pe15_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_15_20_NC), .in_a_chain(a15_19to15_20), .in_b(b14_20to15_20), .in_c(matrixC14_20), .out_a(out_a_15_20_NC), .out_a_chain(a15_20to15_21), .out_b(b15_20to16_20), .out_b0(b15_20to16_20_ping), .out_b1(b15_20to16_20_pong), .out_c(matrixC15_20), .b_data_valid_ping(b_data_valid_ping_delay15_20), .b_data_valid_pong(b_data_valid_pong_delay15_20), .mode(1'b0)); +processing_element pe15_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_15_21_NC), .in_a_chain(a15_20to15_21), .in_b(b14_21to15_21), .in_c(matrixC14_21), .out_a(out_a_15_21_NC), .out_a_chain(a15_21to15_22), .out_b(b15_21to16_21), .out_b0(b15_21to16_21_ping), .out_b1(b15_21to16_21_pong), .out_c(matrixC15_21), .b_data_valid_ping(b_data_valid_ping_delay15_21), .b_data_valid_pong(b_data_valid_pong_delay15_21), .mode(1'b0)); +processing_element pe15_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_15_22_NC), .in_a_chain(a15_21to15_22), .in_b(b14_22to15_22), .in_c(matrixC14_22), .out_a(out_a_15_22_NC), .out_a_chain(a15_22to15_23), .out_b(b15_22to16_22), .out_b0(b15_22to16_22_ping), .out_b1(b15_22to16_22_pong), .out_c(matrixC15_22), .b_data_valid_ping(b_data_valid_ping_delay15_22), .b_data_valid_pong(b_data_valid_pong_delay15_22), .mode(1'b0)); +processing_element pe15_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_15_23_NC), .in_a_chain(a15_22to15_23), .in_b(b14_23to15_23), .in_c(matrixC14_23), .out_a(out_a_15_23_NC), .out_a_chain(a15_23to15_24), .out_b(b15_23to16_23), .out_b0(b15_23to16_23_ping), .out_b1(b15_23to16_23_pong), .out_c(matrixC15_23), .b_data_valid_ping(b_data_valid_ping_delay15_23), .b_data_valid_pong(b_data_valid_pong_delay15_23), .mode(1'b0)); +processing_element pe15_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_15_24_NC), .in_a_chain(a15_23to15_24), .in_b(b14_24to15_24), .in_c(matrixC14_24), .out_a(out_a_15_24_NC), .out_a_chain(a15_24to15_25), .out_b(b15_24to16_24), .out_b0(b15_24to16_24_ping), .out_b1(b15_24to16_24_pong), .out_c(matrixC15_24), .b_data_valid_ping(b_data_valid_ping_delay15_24), .b_data_valid_pong(b_data_valid_pong_delay15_24), .mode(1'b0)); +processing_element pe15_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_15_25_NC), .in_a_chain(a15_24to15_25), .in_b(b14_25to15_25), .in_c(matrixC14_25), .out_a(out_a_15_25_NC), .out_a_chain(a15_25to15_26), .out_b(b15_25to16_25), .out_b0(b15_25to16_25_ping), .out_b1(b15_25to16_25_pong), .out_c(matrixC15_25), .b_data_valid_ping(b_data_valid_ping_delay15_25), .b_data_valid_pong(b_data_valid_pong_delay15_25), .mode(1'b0)); +processing_element pe15_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_15_26_NC), .in_a_chain(a15_25to15_26), .in_b(b14_26to15_26), .in_c(matrixC14_26), .out_a(out_a_15_26_NC), .out_a_chain(a15_26to15_27), .out_b(b15_26to16_26), .out_b0(b15_26to16_26_ping), .out_b1(b15_26to16_26_pong), .out_c(matrixC15_26), .b_data_valid_ping(b_data_valid_ping_delay15_26), .b_data_valid_pong(b_data_valid_pong_delay15_26), .mode(1'b0)); +processing_element pe15_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_15_27_NC), .in_a_chain(a15_26to15_27), .in_b(b14_27to15_27), .in_c(matrixC14_27), .out_a(out_a_15_27_NC), .out_a_chain(a15_27to15_28), .out_b(b15_27to16_27), .out_b0(b15_27to16_27_ping), .out_b1(b15_27to16_27_pong), .out_c(matrixC15_27), .b_data_valid_ping(b_data_valid_ping_delay15_27), .b_data_valid_pong(b_data_valid_pong_delay15_27), .mode(1'b0)); +processing_element pe15_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_15_28_NC), .in_a_chain(a15_27to15_28), .in_b(b14_28to15_28), .in_c(matrixC14_28), .out_a(out_a_15_28_NC), .out_a_chain(a15_28to15_29), .out_b(b15_28to16_28), .out_b0(b15_28to16_28_ping), .out_b1(b15_28to16_28_pong), .out_c(matrixC15_28), .b_data_valid_ping(b_data_valid_ping_delay15_28), .b_data_valid_pong(b_data_valid_pong_delay15_28), .mode(1'b0)); +processing_element pe15_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_15_29_NC), .in_a_chain(a15_28to15_29), .in_b(b14_29to15_29), .in_c(matrixC14_29), .out_a(out_a_15_29_NC), .out_a_chain(a15_29to15_30), .out_b(b15_29to16_29), .out_b0(b15_29to16_29_ping), .out_b1(b15_29to16_29_pong), .out_c(matrixC15_29), .b_data_valid_ping(b_data_valid_ping_delay15_29), .b_data_valid_pong(b_data_valid_pong_delay15_29), .mode(1'b0)); +processing_element pe15_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_15_30_NC), .in_a_chain(a15_29to15_30), .in_b(b14_30to15_30), .in_c(matrixC14_30), .out_a(out_a_15_30_NC), .out_a_chain(a15_30to15_31), .out_b(b15_30to16_30), .out_b0(b15_30to16_30_ping), .out_b1(b15_30to16_30_pong), .out_c(matrixC15_30), .b_data_valid_ping(b_data_valid_ping_delay15_30), .b_data_valid_pong(b_data_valid_pong_delay15_30), .mode(1'b0)); +processing_element pe15_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_15_31_NC), .in_a_chain(a15_30to15_31), .in_b(b14_31to15_31), .in_c(matrixC14_31), .out_a(out_a_15_31_NC), .out_a_chain(a15_31to15_32), .out_b(b15_31to16_31), .out_b0(b15_31to16_31_ping), .out_b1(b15_31to16_31_pong), .out_c(matrixC15_31), .b_data_valid_ping(b_data_valid_ping_delay15_31), .b_data_valid_pong(b_data_valid_pong_delay15_31), .mode(1'b0)); +processing_element pe16_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(a16), .in_a_chain(in_a_chain_16_0_NC), .in_b(b15_0to16_0), .in_c(matrixC15_0), .out_a(out_a_16_0_NC), .out_a_chain(a16_0to16_1), .out_b(b16_0to17_0), .out_b0(b16_0to17_0_ping), .out_b1(b16_0to17_0_pong), .out_c(matrixC16_0), .b_data_valid_ping(b_data_valid_ping_delay16_0), .b_data_valid_pong(b_data_valid_pong_delay16_0), .mode(1'b1)); +processing_element pe16_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_16_1_NC), .in_a_chain(a16_0to16_1), .in_b(b15_1to16_1), .in_c(matrixC15_1), .out_a(out_a_16_1_NC), .out_a_chain(a16_1to16_2), .out_b(b16_1to17_1), .out_b0(b16_1to17_1_ping), .out_b1(b16_1to17_1_pong), .out_c(matrixC16_1), .b_data_valid_ping(b_data_valid_ping_delay16_1), .b_data_valid_pong(b_data_valid_pong_delay16_1), .mode(1'b0)); +processing_element pe16_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_16_2_NC), .in_a_chain(a16_1to16_2), .in_b(b15_2to16_2), .in_c(matrixC15_2), .out_a(out_a_16_2_NC), .out_a_chain(a16_2to16_3), .out_b(b16_2to17_2), .out_b0(b16_2to17_2_ping), .out_b1(b16_2to17_2_pong), .out_c(matrixC16_2), .b_data_valid_ping(b_data_valid_ping_delay16_2), .b_data_valid_pong(b_data_valid_pong_delay16_2), .mode(1'b0)); +processing_element pe16_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_16_3_NC), .in_a_chain(a16_2to16_3), .in_b(b15_3to16_3), .in_c(matrixC15_3), .out_a(out_a_16_3_NC), .out_a_chain(a16_3to16_4), .out_b(b16_3to17_3), .out_b0(b16_3to17_3_ping), .out_b1(b16_3to17_3_pong), .out_c(matrixC16_3), .b_data_valid_ping(b_data_valid_ping_delay16_3), .b_data_valid_pong(b_data_valid_pong_delay16_3), .mode(1'b0)); +processing_element pe16_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_16_4_NC), .in_a_chain(a16_3to16_4), .in_b(b15_4to16_4), .in_c(matrixC15_4), .out_a(out_a_16_4_NC), .out_a_chain(a16_4to16_5), .out_b(b16_4to17_4), .out_b0(b16_4to17_4_ping), .out_b1(b16_4to17_4_pong), .out_c(matrixC16_4), .b_data_valid_ping(b_data_valid_ping_delay16_4), .b_data_valid_pong(b_data_valid_pong_delay16_4), .mode(1'b0)); +processing_element pe16_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_16_5_NC), .in_a_chain(a16_4to16_5), .in_b(b15_5to16_5), .in_c(matrixC15_5), .out_a(out_a_16_5_NC), .out_a_chain(a16_5to16_6), .out_b(b16_5to17_5), .out_b0(b16_5to17_5_ping), .out_b1(b16_5to17_5_pong), .out_c(matrixC16_5), .b_data_valid_ping(b_data_valid_ping_delay16_5), .b_data_valid_pong(b_data_valid_pong_delay16_5), .mode(1'b0)); +processing_element pe16_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_16_6_NC), .in_a_chain(a16_5to16_6), .in_b(b15_6to16_6), .in_c(matrixC15_6), .out_a(out_a_16_6_NC), .out_a_chain(a16_6to16_7), .out_b(b16_6to17_6), .out_b0(b16_6to17_6_ping), .out_b1(b16_6to17_6_pong), .out_c(matrixC16_6), .b_data_valid_ping(b_data_valid_ping_delay16_6), .b_data_valid_pong(b_data_valid_pong_delay16_6), .mode(1'b0)); +processing_element pe16_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_16_7_NC), .in_a_chain(a16_6to16_7), .in_b(b15_7to16_7), .in_c(matrixC15_7), .out_a(out_a_16_7_NC), .out_a_chain(a16_7to16_8), .out_b(b16_7to17_7), .out_b0(b16_7to17_7_ping), .out_b1(b16_7to17_7_pong), .out_c(matrixC16_7), .b_data_valid_ping(b_data_valid_ping_delay16_7), .b_data_valid_pong(b_data_valid_pong_delay16_7), .mode(1'b0)); +processing_element pe16_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_16_8_NC), .in_a_chain(a16_7to16_8), .in_b(b15_8to16_8), .in_c(matrixC15_8), .out_a(out_a_16_8_NC), .out_a_chain(a16_8to16_9), .out_b(b16_8to17_8), .out_b0(b16_8to17_8_ping), .out_b1(b16_8to17_8_pong), .out_c(matrixC16_8), .b_data_valid_ping(b_data_valid_ping_delay16_8), .b_data_valid_pong(b_data_valid_pong_delay16_8), .mode(1'b0)); +processing_element pe16_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_16_9_NC), .in_a_chain(a16_8to16_9), .in_b(b15_9to16_9), .in_c(matrixC15_9), .out_a(out_a_16_9_NC), .out_a_chain(a16_9to16_10), .out_b(b16_9to17_9), .out_b0(b16_9to17_9_ping), .out_b1(b16_9to17_9_pong), .out_c(matrixC16_9), .b_data_valid_ping(b_data_valid_ping_delay16_9), .b_data_valid_pong(b_data_valid_pong_delay16_9), .mode(1'b0)); +processing_element pe16_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_16_10_NC), .in_a_chain(a16_9to16_10), .in_b(b15_10to16_10), .in_c(matrixC15_10), .out_a(out_a_16_10_NC), .out_a_chain(a16_10to16_11), .out_b(b16_10to17_10), .out_b0(b16_10to17_10_ping), .out_b1(b16_10to17_10_pong), .out_c(matrixC16_10), .b_data_valid_ping(b_data_valid_ping_delay16_10), .b_data_valid_pong(b_data_valid_pong_delay16_10), .mode(1'b0)); +processing_element pe16_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_16_11_NC), .in_a_chain(a16_10to16_11), .in_b(b15_11to16_11), .in_c(matrixC15_11), .out_a(out_a_16_11_NC), .out_a_chain(a16_11to16_12), .out_b(b16_11to17_11), .out_b0(b16_11to17_11_ping), .out_b1(b16_11to17_11_pong), .out_c(matrixC16_11), .b_data_valid_ping(b_data_valid_ping_delay16_11), .b_data_valid_pong(b_data_valid_pong_delay16_11), .mode(1'b0)); +processing_element pe16_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_16_12_NC), .in_a_chain(a16_11to16_12), .in_b(b15_12to16_12), .in_c(matrixC15_12), .out_a(out_a_16_12_NC), .out_a_chain(a16_12to16_13), .out_b(b16_12to17_12), .out_b0(b16_12to17_12_ping), .out_b1(b16_12to17_12_pong), .out_c(matrixC16_12), .b_data_valid_ping(b_data_valid_ping_delay16_12), .b_data_valid_pong(b_data_valid_pong_delay16_12), .mode(1'b0)); +processing_element pe16_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_16_13_NC), .in_a_chain(a16_12to16_13), .in_b(b15_13to16_13), .in_c(matrixC15_13), .out_a(out_a_16_13_NC), .out_a_chain(a16_13to16_14), .out_b(b16_13to17_13), .out_b0(b16_13to17_13_ping), .out_b1(b16_13to17_13_pong), .out_c(matrixC16_13), .b_data_valid_ping(b_data_valid_ping_delay16_13), .b_data_valid_pong(b_data_valid_pong_delay16_13), .mode(1'b0)); +processing_element pe16_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_16_14_NC), .in_a_chain(a16_13to16_14), .in_b(b15_14to16_14), .in_c(matrixC15_14), .out_a(out_a_16_14_NC), .out_a_chain(a16_14to16_15), .out_b(b16_14to17_14), .out_b0(b16_14to17_14_ping), .out_b1(b16_14to17_14_pong), .out_c(matrixC16_14), .b_data_valid_ping(b_data_valid_ping_delay16_14), .b_data_valid_pong(b_data_valid_pong_delay16_14), .mode(1'b0)); +processing_element pe16_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_16_15_NC), .in_a_chain(a16_14to16_15), .in_b(b15_15to16_15), .in_c(matrixC15_15), .out_a(out_a_16_15_NC), .out_a_chain(a16_15to16_16), .out_b(b16_15to17_15), .out_b0(b16_15to17_15_ping), .out_b1(b16_15to17_15_pong), .out_c(matrixC16_15), .b_data_valid_ping(b_data_valid_ping_delay16_15), .b_data_valid_pong(b_data_valid_pong_delay16_15), .mode(1'b0)); +processing_element pe16_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_16_16_NC), .in_a_chain(a16_15to16_16), .in_b(b15_16to16_16), .in_c(matrixC15_16), .out_a(out_a_16_16_NC), .out_a_chain(a16_16to16_17), .out_b(b16_16to17_16), .out_b0(b16_16to17_16_ping), .out_b1(b16_16to17_16_pong), .out_c(matrixC16_16), .b_data_valid_ping(b_data_valid_ping_delay16_16), .b_data_valid_pong(b_data_valid_pong_delay16_16), .mode(1'b0)); +processing_element pe16_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_16_17_NC), .in_a_chain(a16_16to16_17), .in_b(b15_17to16_17), .in_c(matrixC15_17), .out_a(out_a_16_17_NC), .out_a_chain(a16_17to16_18), .out_b(b16_17to17_17), .out_b0(b16_17to17_17_ping), .out_b1(b16_17to17_17_pong), .out_c(matrixC16_17), .b_data_valid_ping(b_data_valid_ping_delay16_17), .b_data_valid_pong(b_data_valid_pong_delay16_17), .mode(1'b0)); +processing_element pe16_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_16_18_NC), .in_a_chain(a16_17to16_18), .in_b(b15_18to16_18), .in_c(matrixC15_18), .out_a(out_a_16_18_NC), .out_a_chain(a16_18to16_19), .out_b(b16_18to17_18), .out_b0(b16_18to17_18_ping), .out_b1(b16_18to17_18_pong), .out_c(matrixC16_18), .b_data_valid_ping(b_data_valid_ping_delay16_18), .b_data_valid_pong(b_data_valid_pong_delay16_18), .mode(1'b0)); +processing_element pe16_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_16_19_NC), .in_a_chain(a16_18to16_19), .in_b(b15_19to16_19), .in_c(matrixC15_19), .out_a(out_a_16_19_NC), .out_a_chain(a16_19to16_20), .out_b(b16_19to17_19), .out_b0(b16_19to17_19_ping), .out_b1(b16_19to17_19_pong), .out_c(matrixC16_19), .b_data_valid_ping(b_data_valid_ping_delay16_19), .b_data_valid_pong(b_data_valid_pong_delay16_19), .mode(1'b0)); +processing_element pe16_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_16_20_NC), .in_a_chain(a16_19to16_20), .in_b(b15_20to16_20), .in_c(matrixC15_20), .out_a(out_a_16_20_NC), .out_a_chain(a16_20to16_21), .out_b(b16_20to17_20), .out_b0(b16_20to17_20_ping), .out_b1(b16_20to17_20_pong), .out_c(matrixC16_20), .b_data_valid_ping(b_data_valid_ping_delay16_20), .b_data_valid_pong(b_data_valid_pong_delay16_20), .mode(1'b0)); +processing_element pe16_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_16_21_NC), .in_a_chain(a16_20to16_21), .in_b(b15_21to16_21), .in_c(matrixC15_21), .out_a(out_a_16_21_NC), .out_a_chain(a16_21to16_22), .out_b(b16_21to17_21), .out_b0(b16_21to17_21_ping), .out_b1(b16_21to17_21_pong), .out_c(matrixC16_21), .b_data_valid_ping(b_data_valid_ping_delay16_21), .b_data_valid_pong(b_data_valid_pong_delay16_21), .mode(1'b0)); +processing_element pe16_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_16_22_NC), .in_a_chain(a16_21to16_22), .in_b(b15_22to16_22), .in_c(matrixC15_22), .out_a(out_a_16_22_NC), .out_a_chain(a16_22to16_23), .out_b(b16_22to17_22), .out_b0(b16_22to17_22_ping), .out_b1(b16_22to17_22_pong), .out_c(matrixC16_22), .b_data_valid_ping(b_data_valid_ping_delay16_22), .b_data_valid_pong(b_data_valid_pong_delay16_22), .mode(1'b0)); +processing_element pe16_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_16_23_NC), .in_a_chain(a16_22to16_23), .in_b(b15_23to16_23), .in_c(matrixC15_23), .out_a(out_a_16_23_NC), .out_a_chain(a16_23to16_24), .out_b(b16_23to17_23), .out_b0(b16_23to17_23_ping), .out_b1(b16_23to17_23_pong), .out_c(matrixC16_23), .b_data_valid_ping(b_data_valid_ping_delay16_23), .b_data_valid_pong(b_data_valid_pong_delay16_23), .mode(1'b0)); +processing_element pe16_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_16_24_NC), .in_a_chain(a16_23to16_24), .in_b(b15_24to16_24), .in_c(matrixC15_24), .out_a(out_a_16_24_NC), .out_a_chain(a16_24to16_25), .out_b(b16_24to17_24), .out_b0(b16_24to17_24_ping), .out_b1(b16_24to17_24_pong), .out_c(matrixC16_24), .b_data_valid_ping(b_data_valid_ping_delay16_24), .b_data_valid_pong(b_data_valid_pong_delay16_24), .mode(1'b0)); +processing_element pe16_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_16_25_NC), .in_a_chain(a16_24to16_25), .in_b(b15_25to16_25), .in_c(matrixC15_25), .out_a(out_a_16_25_NC), .out_a_chain(a16_25to16_26), .out_b(b16_25to17_25), .out_b0(b16_25to17_25_ping), .out_b1(b16_25to17_25_pong), .out_c(matrixC16_25), .b_data_valid_ping(b_data_valid_ping_delay16_25), .b_data_valid_pong(b_data_valid_pong_delay16_25), .mode(1'b0)); +processing_element pe16_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_16_26_NC), .in_a_chain(a16_25to16_26), .in_b(b15_26to16_26), .in_c(matrixC15_26), .out_a(out_a_16_26_NC), .out_a_chain(a16_26to16_27), .out_b(b16_26to17_26), .out_b0(b16_26to17_26_ping), .out_b1(b16_26to17_26_pong), .out_c(matrixC16_26), .b_data_valid_ping(b_data_valid_ping_delay16_26), .b_data_valid_pong(b_data_valid_pong_delay16_26), .mode(1'b0)); +processing_element pe16_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_16_27_NC), .in_a_chain(a16_26to16_27), .in_b(b15_27to16_27), .in_c(matrixC15_27), .out_a(out_a_16_27_NC), .out_a_chain(a16_27to16_28), .out_b(b16_27to17_27), .out_b0(b16_27to17_27_ping), .out_b1(b16_27to17_27_pong), .out_c(matrixC16_27), .b_data_valid_ping(b_data_valid_ping_delay16_27), .b_data_valid_pong(b_data_valid_pong_delay16_27), .mode(1'b0)); +processing_element pe16_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_16_28_NC), .in_a_chain(a16_27to16_28), .in_b(b15_28to16_28), .in_c(matrixC15_28), .out_a(out_a_16_28_NC), .out_a_chain(a16_28to16_29), .out_b(b16_28to17_28), .out_b0(b16_28to17_28_ping), .out_b1(b16_28to17_28_pong), .out_c(matrixC16_28), .b_data_valid_ping(b_data_valid_ping_delay16_28), .b_data_valid_pong(b_data_valid_pong_delay16_28), .mode(1'b0)); +processing_element pe16_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_16_29_NC), .in_a_chain(a16_28to16_29), .in_b(b15_29to16_29), .in_c(matrixC15_29), .out_a(out_a_16_29_NC), .out_a_chain(a16_29to16_30), .out_b(b16_29to17_29), .out_b0(b16_29to17_29_ping), .out_b1(b16_29to17_29_pong), .out_c(matrixC16_29), .b_data_valid_ping(b_data_valid_ping_delay16_29), .b_data_valid_pong(b_data_valid_pong_delay16_29), .mode(1'b0)); +processing_element pe16_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_16_30_NC), .in_a_chain(a16_29to16_30), .in_b(b15_30to16_30), .in_c(matrixC15_30), .out_a(out_a_16_30_NC), .out_a_chain(a16_30to16_31), .out_b(b16_30to17_30), .out_b0(b16_30to17_30_ping), .out_b1(b16_30to17_30_pong), .out_c(matrixC16_30), .b_data_valid_ping(b_data_valid_ping_delay16_30), .b_data_valid_pong(b_data_valid_pong_delay16_30), .mode(1'b0)); +processing_element pe16_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_16_31_NC), .in_a_chain(a16_30to16_31), .in_b(b15_31to16_31), .in_c(matrixC15_31), .out_a(out_a_16_31_NC), .out_a_chain(a16_31to16_32), .out_b(b16_31to17_31), .out_b0(b16_31to17_31_ping), .out_b1(b16_31to17_31_pong), .out_c(matrixC16_31), .b_data_valid_ping(b_data_valid_ping_delay16_31), .b_data_valid_pong(b_data_valid_pong_delay16_31), .mode(1'b0)); +processing_element pe17_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(a17), .in_a_chain(in_a_chain_17_0_NC), .in_b(b16_0to17_0), .in_c(matrixC16_0), .out_a(out_a_17_0_NC), .out_a_chain(a17_0to17_1), .out_b(b17_0to18_0), .out_b0(b17_0to18_0_ping), .out_b1(b17_0to18_0_pong), .out_c(matrixC17_0), .b_data_valid_ping(b_data_valid_ping_delay17_0), .b_data_valid_pong(b_data_valid_pong_delay17_0), .mode(1'b1)); +processing_element pe17_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_17_1_NC), .in_a_chain(a17_0to17_1), .in_b(b16_1to17_1), .in_c(matrixC16_1), .out_a(out_a_17_1_NC), .out_a_chain(a17_1to17_2), .out_b(b17_1to18_1), .out_b0(b17_1to18_1_ping), .out_b1(b17_1to18_1_pong), .out_c(matrixC17_1), .b_data_valid_ping(b_data_valid_ping_delay17_1), .b_data_valid_pong(b_data_valid_pong_delay17_1), .mode(1'b0)); +processing_element pe17_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_17_2_NC), .in_a_chain(a17_1to17_2), .in_b(b16_2to17_2), .in_c(matrixC16_2), .out_a(out_a_17_2_NC), .out_a_chain(a17_2to17_3), .out_b(b17_2to18_2), .out_b0(b17_2to18_2_ping), .out_b1(b17_2to18_2_pong), .out_c(matrixC17_2), .b_data_valid_ping(b_data_valid_ping_delay17_2), .b_data_valid_pong(b_data_valid_pong_delay17_2), .mode(1'b0)); +processing_element pe17_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_17_3_NC), .in_a_chain(a17_2to17_3), .in_b(b16_3to17_3), .in_c(matrixC16_3), .out_a(out_a_17_3_NC), .out_a_chain(a17_3to17_4), .out_b(b17_3to18_3), .out_b0(b17_3to18_3_ping), .out_b1(b17_3to18_3_pong), .out_c(matrixC17_3), .b_data_valid_ping(b_data_valid_ping_delay17_3), .b_data_valid_pong(b_data_valid_pong_delay17_3), .mode(1'b0)); +processing_element pe17_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_17_4_NC), .in_a_chain(a17_3to17_4), .in_b(b16_4to17_4), .in_c(matrixC16_4), .out_a(out_a_17_4_NC), .out_a_chain(a17_4to17_5), .out_b(b17_4to18_4), .out_b0(b17_4to18_4_ping), .out_b1(b17_4to18_4_pong), .out_c(matrixC17_4), .b_data_valid_ping(b_data_valid_ping_delay17_4), .b_data_valid_pong(b_data_valid_pong_delay17_4), .mode(1'b0)); +processing_element pe17_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_17_5_NC), .in_a_chain(a17_4to17_5), .in_b(b16_5to17_5), .in_c(matrixC16_5), .out_a(out_a_17_5_NC), .out_a_chain(a17_5to17_6), .out_b(b17_5to18_5), .out_b0(b17_5to18_5_ping), .out_b1(b17_5to18_5_pong), .out_c(matrixC17_5), .b_data_valid_ping(b_data_valid_ping_delay17_5), .b_data_valid_pong(b_data_valid_pong_delay17_5), .mode(1'b0)); +processing_element pe17_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_17_6_NC), .in_a_chain(a17_5to17_6), .in_b(b16_6to17_6), .in_c(matrixC16_6), .out_a(out_a_17_6_NC), .out_a_chain(a17_6to17_7), .out_b(b17_6to18_6), .out_b0(b17_6to18_6_ping), .out_b1(b17_6to18_6_pong), .out_c(matrixC17_6), .b_data_valid_ping(b_data_valid_ping_delay17_6), .b_data_valid_pong(b_data_valid_pong_delay17_6), .mode(1'b0)); +processing_element pe17_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_17_7_NC), .in_a_chain(a17_6to17_7), .in_b(b16_7to17_7), .in_c(matrixC16_7), .out_a(out_a_17_7_NC), .out_a_chain(a17_7to17_8), .out_b(b17_7to18_7), .out_b0(b17_7to18_7_ping), .out_b1(b17_7to18_7_pong), .out_c(matrixC17_7), .b_data_valid_ping(b_data_valid_ping_delay17_7), .b_data_valid_pong(b_data_valid_pong_delay17_7), .mode(1'b0)); +processing_element pe17_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_17_8_NC), .in_a_chain(a17_7to17_8), .in_b(b16_8to17_8), .in_c(matrixC16_8), .out_a(out_a_17_8_NC), .out_a_chain(a17_8to17_9), .out_b(b17_8to18_8), .out_b0(b17_8to18_8_ping), .out_b1(b17_8to18_8_pong), .out_c(matrixC17_8), .b_data_valid_ping(b_data_valid_ping_delay17_8), .b_data_valid_pong(b_data_valid_pong_delay17_8), .mode(1'b0)); +processing_element pe17_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_17_9_NC), .in_a_chain(a17_8to17_9), .in_b(b16_9to17_9), .in_c(matrixC16_9), .out_a(out_a_17_9_NC), .out_a_chain(a17_9to17_10), .out_b(b17_9to18_9), .out_b0(b17_9to18_9_ping), .out_b1(b17_9to18_9_pong), .out_c(matrixC17_9), .b_data_valid_ping(b_data_valid_ping_delay17_9), .b_data_valid_pong(b_data_valid_pong_delay17_9), .mode(1'b0)); +processing_element pe17_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_17_10_NC), .in_a_chain(a17_9to17_10), .in_b(b16_10to17_10), .in_c(matrixC16_10), .out_a(out_a_17_10_NC), .out_a_chain(a17_10to17_11), .out_b(b17_10to18_10), .out_b0(b17_10to18_10_ping), .out_b1(b17_10to18_10_pong), .out_c(matrixC17_10), .b_data_valid_ping(b_data_valid_ping_delay17_10), .b_data_valid_pong(b_data_valid_pong_delay17_10), .mode(1'b0)); +processing_element pe17_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_17_11_NC), .in_a_chain(a17_10to17_11), .in_b(b16_11to17_11), .in_c(matrixC16_11), .out_a(out_a_17_11_NC), .out_a_chain(a17_11to17_12), .out_b(b17_11to18_11), .out_b0(b17_11to18_11_ping), .out_b1(b17_11to18_11_pong), .out_c(matrixC17_11), .b_data_valid_ping(b_data_valid_ping_delay17_11), .b_data_valid_pong(b_data_valid_pong_delay17_11), .mode(1'b0)); +processing_element pe17_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_17_12_NC), .in_a_chain(a17_11to17_12), .in_b(b16_12to17_12), .in_c(matrixC16_12), .out_a(out_a_17_12_NC), .out_a_chain(a17_12to17_13), .out_b(b17_12to18_12), .out_b0(b17_12to18_12_ping), .out_b1(b17_12to18_12_pong), .out_c(matrixC17_12), .b_data_valid_ping(b_data_valid_ping_delay17_12), .b_data_valid_pong(b_data_valid_pong_delay17_12), .mode(1'b0)); +processing_element pe17_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_17_13_NC), .in_a_chain(a17_12to17_13), .in_b(b16_13to17_13), .in_c(matrixC16_13), .out_a(out_a_17_13_NC), .out_a_chain(a17_13to17_14), .out_b(b17_13to18_13), .out_b0(b17_13to18_13_ping), .out_b1(b17_13to18_13_pong), .out_c(matrixC17_13), .b_data_valid_ping(b_data_valid_ping_delay17_13), .b_data_valid_pong(b_data_valid_pong_delay17_13), .mode(1'b0)); +processing_element pe17_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_17_14_NC), .in_a_chain(a17_13to17_14), .in_b(b16_14to17_14), .in_c(matrixC16_14), .out_a(out_a_17_14_NC), .out_a_chain(a17_14to17_15), .out_b(b17_14to18_14), .out_b0(b17_14to18_14_ping), .out_b1(b17_14to18_14_pong), .out_c(matrixC17_14), .b_data_valid_ping(b_data_valid_ping_delay17_14), .b_data_valid_pong(b_data_valid_pong_delay17_14), .mode(1'b0)); +processing_element pe17_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_17_15_NC), .in_a_chain(a17_14to17_15), .in_b(b16_15to17_15), .in_c(matrixC16_15), .out_a(out_a_17_15_NC), .out_a_chain(a17_15to17_16), .out_b(b17_15to18_15), .out_b0(b17_15to18_15_ping), .out_b1(b17_15to18_15_pong), .out_c(matrixC17_15), .b_data_valid_ping(b_data_valid_ping_delay17_15), .b_data_valid_pong(b_data_valid_pong_delay17_15), .mode(1'b0)); +processing_element pe17_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_17_16_NC), .in_a_chain(a17_15to17_16), .in_b(b16_16to17_16), .in_c(matrixC16_16), .out_a(out_a_17_16_NC), .out_a_chain(a17_16to17_17), .out_b(b17_16to18_16), .out_b0(b17_16to18_16_ping), .out_b1(b17_16to18_16_pong), .out_c(matrixC17_16), .b_data_valid_ping(b_data_valid_ping_delay17_16), .b_data_valid_pong(b_data_valid_pong_delay17_16), .mode(1'b0)); +processing_element pe17_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_17_17_NC), .in_a_chain(a17_16to17_17), .in_b(b16_17to17_17), .in_c(matrixC16_17), .out_a(out_a_17_17_NC), .out_a_chain(a17_17to17_18), .out_b(b17_17to18_17), .out_b0(b17_17to18_17_ping), .out_b1(b17_17to18_17_pong), .out_c(matrixC17_17), .b_data_valid_ping(b_data_valid_ping_delay17_17), .b_data_valid_pong(b_data_valid_pong_delay17_17), .mode(1'b0)); +processing_element pe17_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_17_18_NC), .in_a_chain(a17_17to17_18), .in_b(b16_18to17_18), .in_c(matrixC16_18), .out_a(out_a_17_18_NC), .out_a_chain(a17_18to17_19), .out_b(b17_18to18_18), .out_b0(b17_18to18_18_ping), .out_b1(b17_18to18_18_pong), .out_c(matrixC17_18), .b_data_valid_ping(b_data_valid_ping_delay17_18), .b_data_valid_pong(b_data_valid_pong_delay17_18), .mode(1'b0)); +processing_element pe17_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_17_19_NC), .in_a_chain(a17_18to17_19), .in_b(b16_19to17_19), .in_c(matrixC16_19), .out_a(out_a_17_19_NC), .out_a_chain(a17_19to17_20), .out_b(b17_19to18_19), .out_b0(b17_19to18_19_ping), .out_b1(b17_19to18_19_pong), .out_c(matrixC17_19), .b_data_valid_ping(b_data_valid_ping_delay17_19), .b_data_valid_pong(b_data_valid_pong_delay17_19), .mode(1'b0)); +processing_element pe17_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_17_20_NC), .in_a_chain(a17_19to17_20), .in_b(b16_20to17_20), .in_c(matrixC16_20), .out_a(out_a_17_20_NC), .out_a_chain(a17_20to17_21), .out_b(b17_20to18_20), .out_b0(b17_20to18_20_ping), .out_b1(b17_20to18_20_pong), .out_c(matrixC17_20), .b_data_valid_ping(b_data_valid_ping_delay17_20), .b_data_valid_pong(b_data_valid_pong_delay17_20), .mode(1'b0)); +processing_element pe17_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_17_21_NC), .in_a_chain(a17_20to17_21), .in_b(b16_21to17_21), .in_c(matrixC16_21), .out_a(out_a_17_21_NC), .out_a_chain(a17_21to17_22), .out_b(b17_21to18_21), .out_b0(b17_21to18_21_ping), .out_b1(b17_21to18_21_pong), .out_c(matrixC17_21), .b_data_valid_ping(b_data_valid_ping_delay17_21), .b_data_valid_pong(b_data_valid_pong_delay17_21), .mode(1'b0)); +processing_element pe17_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_17_22_NC), .in_a_chain(a17_21to17_22), .in_b(b16_22to17_22), .in_c(matrixC16_22), .out_a(out_a_17_22_NC), .out_a_chain(a17_22to17_23), .out_b(b17_22to18_22), .out_b0(b17_22to18_22_ping), .out_b1(b17_22to18_22_pong), .out_c(matrixC17_22), .b_data_valid_ping(b_data_valid_ping_delay17_22), .b_data_valid_pong(b_data_valid_pong_delay17_22), .mode(1'b0)); +processing_element pe17_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_17_23_NC), .in_a_chain(a17_22to17_23), .in_b(b16_23to17_23), .in_c(matrixC16_23), .out_a(out_a_17_23_NC), .out_a_chain(a17_23to17_24), .out_b(b17_23to18_23), .out_b0(b17_23to18_23_ping), .out_b1(b17_23to18_23_pong), .out_c(matrixC17_23), .b_data_valid_ping(b_data_valid_ping_delay17_23), .b_data_valid_pong(b_data_valid_pong_delay17_23), .mode(1'b0)); +processing_element pe17_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_17_24_NC), .in_a_chain(a17_23to17_24), .in_b(b16_24to17_24), .in_c(matrixC16_24), .out_a(out_a_17_24_NC), .out_a_chain(a17_24to17_25), .out_b(b17_24to18_24), .out_b0(b17_24to18_24_ping), .out_b1(b17_24to18_24_pong), .out_c(matrixC17_24), .b_data_valid_ping(b_data_valid_ping_delay17_24), .b_data_valid_pong(b_data_valid_pong_delay17_24), .mode(1'b0)); +processing_element pe17_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_17_25_NC), .in_a_chain(a17_24to17_25), .in_b(b16_25to17_25), .in_c(matrixC16_25), .out_a(out_a_17_25_NC), .out_a_chain(a17_25to17_26), .out_b(b17_25to18_25), .out_b0(b17_25to18_25_ping), .out_b1(b17_25to18_25_pong), .out_c(matrixC17_25), .b_data_valid_ping(b_data_valid_ping_delay17_25), .b_data_valid_pong(b_data_valid_pong_delay17_25), .mode(1'b0)); +processing_element pe17_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_17_26_NC), .in_a_chain(a17_25to17_26), .in_b(b16_26to17_26), .in_c(matrixC16_26), .out_a(out_a_17_26_NC), .out_a_chain(a17_26to17_27), .out_b(b17_26to18_26), .out_b0(b17_26to18_26_ping), .out_b1(b17_26to18_26_pong), .out_c(matrixC17_26), .b_data_valid_ping(b_data_valid_ping_delay17_26), .b_data_valid_pong(b_data_valid_pong_delay17_26), .mode(1'b0)); +processing_element pe17_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_17_27_NC), .in_a_chain(a17_26to17_27), .in_b(b16_27to17_27), .in_c(matrixC16_27), .out_a(out_a_17_27_NC), .out_a_chain(a17_27to17_28), .out_b(b17_27to18_27), .out_b0(b17_27to18_27_ping), .out_b1(b17_27to18_27_pong), .out_c(matrixC17_27), .b_data_valid_ping(b_data_valid_ping_delay17_27), .b_data_valid_pong(b_data_valid_pong_delay17_27), .mode(1'b0)); +processing_element pe17_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_17_28_NC), .in_a_chain(a17_27to17_28), .in_b(b16_28to17_28), .in_c(matrixC16_28), .out_a(out_a_17_28_NC), .out_a_chain(a17_28to17_29), .out_b(b17_28to18_28), .out_b0(b17_28to18_28_ping), .out_b1(b17_28to18_28_pong), .out_c(matrixC17_28), .b_data_valid_ping(b_data_valid_ping_delay17_28), .b_data_valid_pong(b_data_valid_pong_delay17_28), .mode(1'b0)); +processing_element pe17_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_17_29_NC), .in_a_chain(a17_28to17_29), .in_b(b16_29to17_29), .in_c(matrixC16_29), .out_a(out_a_17_29_NC), .out_a_chain(a17_29to17_30), .out_b(b17_29to18_29), .out_b0(b17_29to18_29_ping), .out_b1(b17_29to18_29_pong), .out_c(matrixC17_29), .b_data_valid_ping(b_data_valid_ping_delay17_29), .b_data_valid_pong(b_data_valid_pong_delay17_29), .mode(1'b0)); +processing_element pe17_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_17_30_NC), .in_a_chain(a17_29to17_30), .in_b(b16_30to17_30), .in_c(matrixC16_30), .out_a(out_a_17_30_NC), .out_a_chain(a17_30to17_31), .out_b(b17_30to18_30), .out_b0(b17_30to18_30_ping), .out_b1(b17_30to18_30_pong), .out_c(matrixC17_30), .b_data_valid_ping(b_data_valid_ping_delay17_30), .b_data_valid_pong(b_data_valid_pong_delay17_30), .mode(1'b0)); +processing_element pe17_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay48), .in_a(in_a_17_31_NC), .in_a_chain(a17_30to17_31), .in_b(b16_31to17_31), .in_c(matrixC16_31), .out_a(out_a_17_31_NC), .out_a_chain(a17_31to17_32), .out_b(b17_31to18_31), .out_b0(b17_31to18_31_ping), .out_b1(b17_31to18_31_pong), .out_c(matrixC17_31), .b_data_valid_ping(b_data_valid_ping_delay17_31), .b_data_valid_pong(b_data_valid_pong_delay17_31), .mode(1'b0)); +processing_element pe18_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(a18), .in_a_chain(in_a_chain_18_0_NC), .in_b(b17_0to18_0), .in_c(matrixC17_0), .out_a(out_a_18_0_NC), .out_a_chain(a18_0to18_1), .out_b(b18_0to19_0), .out_b0(b18_0to19_0_ping), .out_b1(b18_0to19_0_pong), .out_c(matrixC18_0), .b_data_valid_ping(b_data_valid_ping_delay18_0), .b_data_valid_pong(b_data_valid_pong_delay18_0), .mode(1'b1)); +processing_element pe18_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_18_1_NC), .in_a_chain(a18_0to18_1), .in_b(b17_1to18_1), .in_c(matrixC17_1), .out_a(out_a_18_1_NC), .out_a_chain(a18_1to18_2), .out_b(b18_1to19_1), .out_b0(b18_1to19_1_ping), .out_b1(b18_1to19_1_pong), .out_c(matrixC18_1), .b_data_valid_ping(b_data_valid_ping_delay18_1), .b_data_valid_pong(b_data_valid_pong_delay18_1), .mode(1'b0)); +processing_element pe18_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_18_2_NC), .in_a_chain(a18_1to18_2), .in_b(b17_2to18_2), .in_c(matrixC17_2), .out_a(out_a_18_2_NC), .out_a_chain(a18_2to18_3), .out_b(b18_2to19_2), .out_b0(b18_2to19_2_ping), .out_b1(b18_2to19_2_pong), .out_c(matrixC18_2), .b_data_valid_ping(b_data_valid_ping_delay18_2), .b_data_valid_pong(b_data_valid_pong_delay18_2), .mode(1'b0)); +processing_element pe18_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_18_3_NC), .in_a_chain(a18_2to18_3), .in_b(b17_3to18_3), .in_c(matrixC17_3), .out_a(out_a_18_3_NC), .out_a_chain(a18_3to18_4), .out_b(b18_3to19_3), .out_b0(b18_3to19_3_ping), .out_b1(b18_3to19_3_pong), .out_c(matrixC18_3), .b_data_valid_ping(b_data_valid_ping_delay18_3), .b_data_valid_pong(b_data_valid_pong_delay18_3), .mode(1'b0)); +processing_element pe18_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_18_4_NC), .in_a_chain(a18_3to18_4), .in_b(b17_4to18_4), .in_c(matrixC17_4), .out_a(out_a_18_4_NC), .out_a_chain(a18_4to18_5), .out_b(b18_4to19_4), .out_b0(b18_4to19_4_ping), .out_b1(b18_4to19_4_pong), .out_c(matrixC18_4), .b_data_valid_ping(b_data_valid_ping_delay18_4), .b_data_valid_pong(b_data_valid_pong_delay18_4), .mode(1'b0)); +processing_element pe18_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_18_5_NC), .in_a_chain(a18_4to18_5), .in_b(b17_5to18_5), .in_c(matrixC17_5), .out_a(out_a_18_5_NC), .out_a_chain(a18_5to18_6), .out_b(b18_5to19_5), .out_b0(b18_5to19_5_ping), .out_b1(b18_5to19_5_pong), .out_c(matrixC18_5), .b_data_valid_ping(b_data_valid_ping_delay18_5), .b_data_valid_pong(b_data_valid_pong_delay18_5), .mode(1'b0)); +processing_element pe18_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_18_6_NC), .in_a_chain(a18_5to18_6), .in_b(b17_6to18_6), .in_c(matrixC17_6), .out_a(out_a_18_6_NC), .out_a_chain(a18_6to18_7), .out_b(b18_6to19_6), .out_b0(b18_6to19_6_ping), .out_b1(b18_6to19_6_pong), .out_c(matrixC18_6), .b_data_valid_ping(b_data_valid_ping_delay18_6), .b_data_valid_pong(b_data_valid_pong_delay18_6), .mode(1'b0)); +processing_element pe18_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_18_7_NC), .in_a_chain(a18_6to18_7), .in_b(b17_7to18_7), .in_c(matrixC17_7), .out_a(out_a_18_7_NC), .out_a_chain(a18_7to18_8), .out_b(b18_7to19_7), .out_b0(b18_7to19_7_ping), .out_b1(b18_7to19_7_pong), .out_c(matrixC18_7), .b_data_valid_ping(b_data_valid_ping_delay18_7), .b_data_valid_pong(b_data_valid_pong_delay18_7), .mode(1'b0)); +processing_element pe18_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_18_8_NC), .in_a_chain(a18_7to18_8), .in_b(b17_8to18_8), .in_c(matrixC17_8), .out_a(out_a_18_8_NC), .out_a_chain(a18_8to18_9), .out_b(b18_8to19_8), .out_b0(b18_8to19_8_ping), .out_b1(b18_8to19_8_pong), .out_c(matrixC18_8), .b_data_valid_ping(b_data_valid_ping_delay18_8), .b_data_valid_pong(b_data_valid_pong_delay18_8), .mode(1'b0)); +processing_element pe18_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_18_9_NC), .in_a_chain(a18_8to18_9), .in_b(b17_9to18_9), .in_c(matrixC17_9), .out_a(out_a_18_9_NC), .out_a_chain(a18_9to18_10), .out_b(b18_9to19_9), .out_b0(b18_9to19_9_ping), .out_b1(b18_9to19_9_pong), .out_c(matrixC18_9), .b_data_valid_ping(b_data_valid_ping_delay18_9), .b_data_valid_pong(b_data_valid_pong_delay18_9), .mode(1'b0)); +processing_element pe18_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_18_10_NC), .in_a_chain(a18_9to18_10), .in_b(b17_10to18_10), .in_c(matrixC17_10), .out_a(out_a_18_10_NC), .out_a_chain(a18_10to18_11), .out_b(b18_10to19_10), .out_b0(b18_10to19_10_ping), .out_b1(b18_10to19_10_pong), .out_c(matrixC18_10), .b_data_valid_ping(b_data_valid_ping_delay18_10), .b_data_valid_pong(b_data_valid_pong_delay18_10), .mode(1'b0)); +processing_element pe18_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_18_11_NC), .in_a_chain(a18_10to18_11), .in_b(b17_11to18_11), .in_c(matrixC17_11), .out_a(out_a_18_11_NC), .out_a_chain(a18_11to18_12), .out_b(b18_11to19_11), .out_b0(b18_11to19_11_ping), .out_b1(b18_11to19_11_pong), .out_c(matrixC18_11), .b_data_valid_ping(b_data_valid_ping_delay18_11), .b_data_valid_pong(b_data_valid_pong_delay18_11), .mode(1'b0)); +processing_element pe18_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_18_12_NC), .in_a_chain(a18_11to18_12), .in_b(b17_12to18_12), .in_c(matrixC17_12), .out_a(out_a_18_12_NC), .out_a_chain(a18_12to18_13), .out_b(b18_12to19_12), .out_b0(b18_12to19_12_ping), .out_b1(b18_12to19_12_pong), .out_c(matrixC18_12), .b_data_valid_ping(b_data_valid_ping_delay18_12), .b_data_valid_pong(b_data_valid_pong_delay18_12), .mode(1'b0)); +processing_element pe18_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_18_13_NC), .in_a_chain(a18_12to18_13), .in_b(b17_13to18_13), .in_c(matrixC17_13), .out_a(out_a_18_13_NC), .out_a_chain(a18_13to18_14), .out_b(b18_13to19_13), .out_b0(b18_13to19_13_ping), .out_b1(b18_13to19_13_pong), .out_c(matrixC18_13), .b_data_valid_ping(b_data_valid_ping_delay18_13), .b_data_valid_pong(b_data_valid_pong_delay18_13), .mode(1'b0)); +processing_element pe18_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_18_14_NC), .in_a_chain(a18_13to18_14), .in_b(b17_14to18_14), .in_c(matrixC17_14), .out_a(out_a_18_14_NC), .out_a_chain(a18_14to18_15), .out_b(b18_14to19_14), .out_b0(b18_14to19_14_ping), .out_b1(b18_14to19_14_pong), .out_c(matrixC18_14), .b_data_valid_ping(b_data_valid_ping_delay18_14), .b_data_valid_pong(b_data_valid_pong_delay18_14), .mode(1'b0)); +processing_element pe18_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_18_15_NC), .in_a_chain(a18_14to18_15), .in_b(b17_15to18_15), .in_c(matrixC17_15), .out_a(out_a_18_15_NC), .out_a_chain(a18_15to18_16), .out_b(b18_15to19_15), .out_b0(b18_15to19_15_ping), .out_b1(b18_15to19_15_pong), .out_c(matrixC18_15), .b_data_valid_ping(b_data_valid_ping_delay18_15), .b_data_valid_pong(b_data_valid_pong_delay18_15), .mode(1'b0)); +processing_element pe18_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_18_16_NC), .in_a_chain(a18_15to18_16), .in_b(b17_16to18_16), .in_c(matrixC17_16), .out_a(out_a_18_16_NC), .out_a_chain(a18_16to18_17), .out_b(b18_16to19_16), .out_b0(b18_16to19_16_ping), .out_b1(b18_16to19_16_pong), .out_c(matrixC18_16), .b_data_valid_ping(b_data_valid_ping_delay18_16), .b_data_valid_pong(b_data_valid_pong_delay18_16), .mode(1'b0)); +processing_element pe18_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_18_17_NC), .in_a_chain(a18_16to18_17), .in_b(b17_17to18_17), .in_c(matrixC17_17), .out_a(out_a_18_17_NC), .out_a_chain(a18_17to18_18), .out_b(b18_17to19_17), .out_b0(b18_17to19_17_ping), .out_b1(b18_17to19_17_pong), .out_c(matrixC18_17), .b_data_valid_ping(b_data_valid_ping_delay18_17), .b_data_valid_pong(b_data_valid_pong_delay18_17), .mode(1'b0)); +processing_element pe18_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_18_18_NC), .in_a_chain(a18_17to18_18), .in_b(b17_18to18_18), .in_c(matrixC17_18), .out_a(out_a_18_18_NC), .out_a_chain(a18_18to18_19), .out_b(b18_18to19_18), .out_b0(b18_18to19_18_ping), .out_b1(b18_18to19_18_pong), .out_c(matrixC18_18), .b_data_valid_ping(b_data_valid_ping_delay18_18), .b_data_valid_pong(b_data_valid_pong_delay18_18), .mode(1'b0)); +processing_element pe18_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_18_19_NC), .in_a_chain(a18_18to18_19), .in_b(b17_19to18_19), .in_c(matrixC17_19), .out_a(out_a_18_19_NC), .out_a_chain(a18_19to18_20), .out_b(b18_19to19_19), .out_b0(b18_19to19_19_ping), .out_b1(b18_19to19_19_pong), .out_c(matrixC18_19), .b_data_valid_ping(b_data_valid_ping_delay18_19), .b_data_valid_pong(b_data_valid_pong_delay18_19), .mode(1'b0)); +processing_element pe18_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_18_20_NC), .in_a_chain(a18_19to18_20), .in_b(b17_20to18_20), .in_c(matrixC17_20), .out_a(out_a_18_20_NC), .out_a_chain(a18_20to18_21), .out_b(b18_20to19_20), .out_b0(b18_20to19_20_ping), .out_b1(b18_20to19_20_pong), .out_c(matrixC18_20), .b_data_valid_ping(b_data_valid_ping_delay18_20), .b_data_valid_pong(b_data_valid_pong_delay18_20), .mode(1'b0)); +processing_element pe18_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_18_21_NC), .in_a_chain(a18_20to18_21), .in_b(b17_21to18_21), .in_c(matrixC17_21), .out_a(out_a_18_21_NC), .out_a_chain(a18_21to18_22), .out_b(b18_21to19_21), .out_b0(b18_21to19_21_ping), .out_b1(b18_21to19_21_pong), .out_c(matrixC18_21), .b_data_valid_ping(b_data_valid_ping_delay18_21), .b_data_valid_pong(b_data_valid_pong_delay18_21), .mode(1'b0)); +processing_element pe18_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_18_22_NC), .in_a_chain(a18_21to18_22), .in_b(b17_22to18_22), .in_c(matrixC17_22), .out_a(out_a_18_22_NC), .out_a_chain(a18_22to18_23), .out_b(b18_22to19_22), .out_b0(b18_22to19_22_ping), .out_b1(b18_22to19_22_pong), .out_c(matrixC18_22), .b_data_valid_ping(b_data_valid_ping_delay18_22), .b_data_valid_pong(b_data_valid_pong_delay18_22), .mode(1'b0)); +processing_element pe18_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_18_23_NC), .in_a_chain(a18_22to18_23), .in_b(b17_23to18_23), .in_c(matrixC17_23), .out_a(out_a_18_23_NC), .out_a_chain(a18_23to18_24), .out_b(b18_23to19_23), .out_b0(b18_23to19_23_ping), .out_b1(b18_23to19_23_pong), .out_c(matrixC18_23), .b_data_valid_ping(b_data_valid_ping_delay18_23), .b_data_valid_pong(b_data_valid_pong_delay18_23), .mode(1'b0)); +processing_element pe18_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_18_24_NC), .in_a_chain(a18_23to18_24), .in_b(b17_24to18_24), .in_c(matrixC17_24), .out_a(out_a_18_24_NC), .out_a_chain(a18_24to18_25), .out_b(b18_24to19_24), .out_b0(b18_24to19_24_ping), .out_b1(b18_24to19_24_pong), .out_c(matrixC18_24), .b_data_valid_ping(b_data_valid_ping_delay18_24), .b_data_valid_pong(b_data_valid_pong_delay18_24), .mode(1'b0)); +processing_element pe18_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_18_25_NC), .in_a_chain(a18_24to18_25), .in_b(b17_25to18_25), .in_c(matrixC17_25), .out_a(out_a_18_25_NC), .out_a_chain(a18_25to18_26), .out_b(b18_25to19_25), .out_b0(b18_25to19_25_ping), .out_b1(b18_25to19_25_pong), .out_c(matrixC18_25), .b_data_valid_ping(b_data_valid_ping_delay18_25), .b_data_valid_pong(b_data_valid_pong_delay18_25), .mode(1'b0)); +processing_element pe18_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_18_26_NC), .in_a_chain(a18_25to18_26), .in_b(b17_26to18_26), .in_c(matrixC17_26), .out_a(out_a_18_26_NC), .out_a_chain(a18_26to18_27), .out_b(b18_26to19_26), .out_b0(b18_26to19_26_ping), .out_b1(b18_26to19_26_pong), .out_c(matrixC18_26), .b_data_valid_ping(b_data_valid_ping_delay18_26), .b_data_valid_pong(b_data_valid_pong_delay18_26), .mode(1'b0)); +processing_element pe18_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_18_27_NC), .in_a_chain(a18_26to18_27), .in_b(b17_27to18_27), .in_c(matrixC17_27), .out_a(out_a_18_27_NC), .out_a_chain(a18_27to18_28), .out_b(b18_27to19_27), .out_b0(b18_27to19_27_ping), .out_b1(b18_27to19_27_pong), .out_c(matrixC18_27), .b_data_valid_ping(b_data_valid_ping_delay18_27), .b_data_valid_pong(b_data_valid_pong_delay18_27), .mode(1'b0)); +processing_element pe18_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_18_28_NC), .in_a_chain(a18_27to18_28), .in_b(b17_28to18_28), .in_c(matrixC17_28), .out_a(out_a_18_28_NC), .out_a_chain(a18_28to18_29), .out_b(b18_28to19_28), .out_b0(b18_28to19_28_ping), .out_b1(b18_28to19_28_pong), .out_c(matrixC18_28), .b_data_valid_ping(b_data_valid_ping_delay18_28), .b_data_valid_pong(b_data_valid_pong_delay18_28), .mode(1'b0)); +processing_element pe18_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_18_29_NC), .in_a_chain(a18_28to18_29), .in_b(b17_29to18_29), .in_c(matrixC17_29), .out_a(out_a_18_29_NC), .out_a_chain(a18_29to18_30), .out_b(b18_29to19_29), .out_b0(b18_29to19_29_ping), .out_b1(b18_29to19_29_pong), .out_c(matrixC18_29), .b_data_valid_ping(b_data_valid_ping_delay18_29), .b_data_valid_pong(b_data_valid_pong_delay18_29), .mode(1'b0)); +processing_element pe18_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay48), .in_a(in_a_18_30_NC), .in_a_chain(a18_29to18_30), .in_b(b17_30to18_30), .in_c(matrixC17_30), .out_a(out_a_18_30_NC), .out_a_chain(a18_30to18_31), .out_b(b18_30to19_30), .out_b0(b18_30to19_30_ping), .out_b1(b18_30to19_30_pong), .out_c(matrixC18_30), .b_data_valid_ping(b_data_valid_ping_delay18_30), .b_data_valid_pong(b_data_valid_pong_delay18_30), .mode(1'b0)); +processing_element pe18_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay49), .in_a(in_a_18_31_NC), .in_a_chain(a18_30to18_31), .in_b(b17_31to18_31), .in_c(matrixC17_31), .out_a(out_a_18_31_NC), .out_a_chain(a18_31to18_32), .out_b(b18_31to19_31), .out_b0(b18_31to19_31_ping), .out_b1(b18_31to19_31_pong), .out_c(matrixC18_31), .b_data_valid_ping(b_data_valid_ping_delay18_31), .b_data_valid_pong(b_data_valid_pong_delay18_31), .mode(1'b0)); +processing_element pe19_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(a19), .in_a_chain(in_a_chain_19_0_NC), .in_b(b18_0to19_0), .in_c(matrixC18_0), .out_a(out_a_19_0_NC), .out_a_chain(a19_0to19_1), .out_b(b19_0to20_0), .out_b0(b19_0to20_0_ping), .out_b1(b19_0to20_0_pong), .out_c(matrixC19_0), .b_data_valid_ping(b_data_valid_ping_delay19_0), .b_data_valid_pong(b_data_valid_pong_delay19_0), .mode(1'b1)); +processing_element pe19_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_19_1_NC), .in_a_chain(a19_0to19_1), .in_b(b18_1to19_1), .in_c(matrixC18_1), .out_a(out_a_19_1_NC), .out_a_chain(a19_1to19_2), .out_b(b19_1to20_1), .out_b0(b19_1to20_1_ping), .out_b1(b19_1to20_1_pong), .out_c(matrixC19_1), .b_data_valid_ping(b_data_valid_ping_delay19_1), .b_data_valid_pong(b_data_valid_pong_delay19_1), .mode(1'b0)); +processing_element pe19_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_19_2_NC), .in_a_chain(a19_1to19_2), .in_b(b18_2to19_2), .in_c(matrixC18_2), .out_a(out_a_19_2_NC), .out_a_chain(a19_2to19_3), .out_b(b19_2to20_2), .out_b0(b19_2to20_2_ping), .out_b1(b19_2to20_2_pong), .out_c(matrixC19_2), .b_data_valid_ping(b_data_valid_ping_delay19_2), .b_data_valid_pong(b_data_valid_pong_delay19_2), .mode(1'b0)); +processing_element pe19_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_19_3_NC), .in_a_chain(a19_2to19_3), .in_b(b18_3to19_3), .in_c(matrixC18_3), .out_a(out_a_19_3_NC), .out_a_chain(a19_3to19_4), .out_b(b19_3to20_3), .out_b0(b19_3to20_3_ping), .out_b1(b19_3to20_3_pong), .out_c(matrixC19_3), .b_data_valid_ping(b_data_valid_ping_delay19_3), .b_data_valid_pong(b_data_valid_pong_delay19_3), .mode(1'b0)); +processing_element pe19_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_19_4_NC), .in_a_chain(a19_3to19_4), .in_b(b18_4to19_4), .in_c(matrixC18_4), .out_a(out_a_19_4_NC), .out_a_chain(a19_4to19_5), .out_b(b19_4to20_4), .out_b0(b19_4to20_4_ping), .out_b1(b19_4to20_4_pong), .out_c(matrixC19_4), .b_data_valid_ping(b_data_valid_ping_delay19_4), .b_data_valid_pong(b_data_valid_pong_delay19_4), .mode(1'b0)); +processing_element pe19_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_19_5_NC), .in_a_chain(a19_4to19_5), .in_b(b18_5to19_5), .in_c(matrixC18_5), .out_a(out_a_19_5_NC), .out_a_chain(a19_5to19_6), .out_b(b19_5to20_5), .out_b0(b19_5to20_5_ping), .out_b1(b19_5to20_5_pong), .out_c(matrixC19_5), .b_data_valid_ping(b_data_valid_ping_delay19_5), .b_data_valid_pong(b_data_valid_pong_delay19_5), .mode(1'b0)); +processing_element pe19_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_19_6_NC), .in_a_chain(a19_5to19_6), .in_b(b18_6to19_6), .in_c(matrixC18_6), .out_a(out_a_19_6_NC), .out_a_chain(a19_6to19_7), .out_b(b19_6to20_6), .out_b0(b19_6to20_6_ping), .out_b1(b19_6to20_6_pong), .out_c(matrixC19_6), .b_data_valid_ping(b_data_valid_ping_delay19_6), .b_data_valid_pong(b_data_valid_pong_delay19_6), .mode(1'b0)); +processing_element pe19_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_19_7_NC), .in_a_chain(a19_6to19_7), .in_b(b18_7to19_7), .in_c(matrixC18_7), .out_a(out_a_19_7_NC), .out_a_chain(a19_7to19_8), .out_b(b19_7to20_7), .out_b0(b19_7to20_7_ping), .out_b1(b19_7to20_7_pong), .out_c(matrixC19_7), .b_data_valid_ping(b_data_valid_ping_delay19_7), .b_data_valid_pong(b_data_valid_pong_delay19_7), .mode(1'b0)); +processing_element pe19_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_19_8_NC), .in_a_chain(a19_7to19_8), .in_b(b18_8to19_8), .in_c(matrixC18_8), .out_a(out_a_19_8_NC), .out_a_chain(a19_8to19_9), .out_b(b19_8to20_8), .out_b0(b19_8to20_8_ping), .out_b1(b19_8to20_8_pong), .out_c(matrixC19_8), .b_data_valid_ping(b_data_valid_ping_delay19_8), .b_data_valid_pong(b_data_valid_pong_delay19_8), .mode(1'b0)); +processing_element pe19_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_19_9_NC), .in_a_chain(a19_8to19_9), .in_b(b18_9to19_9), .in_c(matrixC18_9), .out_a(out_a_19_9_NC), .out_a_chain(a19_9to19_10), .out_b(b19_9to20_9), .out_b0(b19_9to20_9_ping), .out_b1(b19_9to20_9_pong), .out_c(matrixC19_9), .b_data_valid_ping(b_data_valid_ping_delay19_9), .b_data_valid_pong(b_data_valid_pong_delay19_9), .mode(1'b0)); +processing_element pe19_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_19_10_NC), .in_a_chain(a19_9to19_10), .in_b(b18_10to19_10), .in_c(matrixC18_10), .out_a(out_a_19_10_NC), .out_a_chain(a19_10to19_11), .out_b(b19_10to20_10), .out_b0(b19_10to20_10_ping), .out_b1(b19_10to20_10_pong), .out_c(matrixC19_10), .b_data_valid_ping(b_data_valid_ping_delay19_10), .b_data_valid_pong(b_data_valid_pong_delay19_10), .mode(1'b0)); +processing_element pe19_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_19_11_NC), .in_a_chain(a19_10to19_11), .in_b(b18_11to19_11), .in_c(matrixC18_11), .out_a(out_a_19_11_NC), .out_a_chain(a19_11to19_12), .out_b(b19_11to20_11), .out_b0(b19_11to20_11_ping), .out_b1(b19_11to20_11_pong), .out_c(matrixC19_11), .b_data_valid_ping(b_data_valid_ping_delay19_11), .b_data_valid_pong(b_data_valid_pong_delay19_11), .mode(1'b0)); +processing_element pe19_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_19_12_NC), .in_a_chain(a19_11to19_12), .in_b(b18_12to19_12), .in_c(matrixC18_12), .out_a(out_a_19_12_NC), .out_a_chain(a19_12to19_13), .out_b(b19_12to20_12), .out_b0(b19_12to20_12_ping), .out_b1(b19_12to20_12_pong), .out_c(matrixC19_12), .b_data_valid_ping(b_data_valid_ping_delay19_12), .b_data_valid_pong(b_data_valid_pong_delay19_12), .mode(1'b0)); +processing_element pe19_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_19_13_NC), .in_a_chain(a19_12to19_13), .in_b(b18_13to19_13), .in_c(matrixC18_13), .out_a(out_a_19_13_NC), .out_a_chain(a19_13to19_14), .out_b(b19_13to20_13), .out_b0(b19_13to20_13_ping), .out_b1(b19_13to20_13_pong), .out_c(matrixC19_13), .b_data_valid_ping(b_data_valid_ping_delay19_13), .b_data_valid_pong(b_data_valid_pong_delay19_13), .mode(1'b0)); +processing_element pe19_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_19_14_NC), .in_a_chain(a19_13to19_14), .in_b(b18_14to19_14), .in_c(matrixC18_14), .out_a(out_a_19_14_NC), .out_a_chain(a19_14to19_15), .out_b(b19_14to20_14), .out_b0(b19_14to20_14_ping), .out_b1(b19_14to20_14_pong), .out_c(matrixC19_14), .b_data_valid_ping(b_data_valid_ping_delay19_14), .b_data_valid_pong(b_data_valid_pong_delay19_14), .mode(1'b0)); +processing_element pe19_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_19_15_NC), .in_a_chain(a19_14to19_15), .in_b(b18_15to19_15), .in_c(matrixC18_15), .out_a(out_a_19_15_NC), .out_a_chain(a19_15to19_16), .out_b(b19_15to20_15), .out_b0(b19_15to20_15_ping), .out_b1(b19_15to20_15_pong), .out_c(matrixC19_15), .b_data_valid_ping(b_data_valid_ping_delay19_15), .b_data_valid_pong(b_data_valid_pong_delay19_15), .mode(1'b0)); +processing_element pe19_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_19_16_NC), .in_a_chain(a19_15to19_16), .in_b(b18_16to19_16), .in_c(matrixC18_16), .out_a(out_a_19_16_NC), .out_a_chain(a19_16to19_17), .out_b(b19_16to20_16), .out_b0(b19_16to20_16_ping), .out_b1(b19_16to20_16_pong), .out_c(matrixC19_16), .b_data_valid_ping(b_data_valid_ping_delay19_16), .b_data_valid_pong(b_data_valid_pong_delay19_16), .mode(1'b0)); +processing_element pe19_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_19_17_NC), .in_a_chain(a19_16to19_17), .in_b(b18_17to19_17), .in_c(matrixC18_17), .out_a(out_a_19_17_NC), .out_a_chain(a19_17to19_18), .out_b(b19_17to20_17), .out_b0(b19_17to20_17_ping), .out_b1(b19_17to20_17_pong), .out_c(matrixC19_17), .b_data_valid_ping(b_data_valid_ping_delay19_17), .b_data_valid_pong(b_data_valid_pong_delay19_17), .mode(1'b0)); +processing_element pe19_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_19_18_NC), .in_a_chain(a19_17to19_18), .in_b(b18_18to19_18), .in_c(matrixC18_18), .out_a(out_a_19_18_NC), .out_a_chain(a19_18to19_19), .out_b(b19_18to20_18), .out_b0(b19_18to20_18_ping), .out_b1(b19_18to20_18_pong), .out_c(matrixC19_18), .b_data_valid_ping(b_data_valid_ping_delay19_18), .b_data_valid_pong(b_data_valid_pong_delay19_18), .mode(1'b0)); +processing_element pe19_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_19_19_NC), .in_a_chain(a19_18to19_19), .in_b(b18_19to19_19), .in_c(matrixC18_19), .out_a(out_a_19_19_NC), .out_a_chain(a19_19to19_20), .out_b(b19_19to20_19), .out_b0(b19_19to20_19_ping), .out_b1(b19_19to20_19_pong), .out_c(matrixC19_19), .b_data_valid_ping(b_data_valid_ping_delay19_19), .b_data_valid_pong(b_data_valid_pong_delay19_19), .mode(1'b0)); +processing_element pe19_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_19_20_NC), .in_a_chain(a19_19to19_20), .in_b(b18_20to19_20), .in_c(matrixC18_20), .out_a(out_a_19_20_NC), .out_a_chain(a19_20to19_21), .out_b(b19_20to20_20), .out_b0(b19_20to20_20_ping), .out_b1(b19_20to20_20_pong), .out_c(matrixC19_20), .b_data_valid_ping(b_data_valid_ping_delay19_20), .b_data_valid_pong(b_data_valid_pong_delay19_20), .mode(1'b0)); +processing_element pe19_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_19_21_NC), .in_a_chain(a19_20to19_21), .in_b(b18_21to19_21), .in_c(matrixC18_21), .out_a(out_a_19_21_NC), .out_a_chain(a19_21to19_22), .out_b(b19_21to20_21), .out_b0(b19_21to20_21_ping), .out_b1(b19_21to20_21_pong), .out_c(matrixC19_21), .b_data_valid_ping(b_data_valid_ping_delay19_21), .b_data_valid_pong(b_data_valid_pong_delay19_21), .mode(1'b0)); +processing_element pe19_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_19_22_NC), .in_a_chain(a19_21to19_22), .in_b(b18_22to19_22), .in_c(matrixC18_22), .out_a(out_a_19_22_NC), .out_a_chain(a19_22to19_23), .out_b(b19_22to20_22), .out_b0(b19_22to20_22_ping), .out_b1(b19_22to20_22_pong), .out_c(matrixC19_22), .b_data_valid_ping(b_data_valid_ping_delay19_22), .b_data_valid_pong(b_data_valid_pong_delay19_22), .mode(1'b0)); +processing_element pe19_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_19_23_NC), .in_a_chain(a19_22to19_23), .in_b(b18_23to19_23), .in_c(matrixC18_23), .out_a(out_a_19_23_NC), .out_a_chain(a19_23to19_24), .out_b(b19_23to20_23), .out_b0(b19_23to20_23_ping), .out_b1(b19_23to20_23_pong), .out_c(matrixC19_23), .b_data_valid_ping(b_data_valid_ping_delay19_23), .b_data_valid_pong(b_data_valid_pong_delay19_23), .mode(1'b0)); +processing_element pe19_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_19_24_NC), .in_a_chain(a19_23to19_24), .in_b(b18_24to19_24), .in_c(matrixC18_24), .out_a(out_a_19_24_NC), .out_a_chain(a19_24to19_25), .out_b(b19_24to20_24), .out_b0(b19_24to20_24_ping), .out_b1(b19_24to20_24_pong), .out_c(matrixC19_24), .b_data_valid_ping(b_data_valid_ping_delay19_24), .b_data_valid_pong(b_data_valid_pong_delay19_24), .mode(1'b0)); +processing_element pe19_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_19_25_NC), .in_a_chain(a19_24to19_25), .in_b(b18_25to19_25), .in_c(matrixC18_25), .out_a(out_a_19_25_NC), .out_a_chain(a19_25to19_26), .out_b(b19_25to20_25), .out_b0(b19_25to20_25_ping), .out_b1(b19_25to20_25_pong), .out_c(matrixC19_25), .b_data_valid_ping(b_data_valid_ping_delay19_25), .b_data_valid_pong(b_data_valid_pong_delay19_25), .mode(1'b0)); +processing_element pe19_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_19_26_NC), .in_a_chain(a19_25to19_26), .in_b(b18_26to19_26), .in_c(matrixC18_26), .out_a(out_a_19_26_NC), .out_a_chain(a19_26to19_27), .out_b(b19_26to20_26), .out_b0(b19_26to20_26_ping), .out_b1(b19_26to20_26_pong), .out_c(matrixC19_26), .b_data_valid_ping(b_data_valid_ping_delay19_26), .b_data_valid_pong(b_data_valid_pong_delay19_26), .mode(1'b0)); +processing_element pe19_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_19_27_NC), .in_a_chain(a19_26to19_27), .in_b(b18_27to19_27), .in_c(matrixC18_27), .out_a(out_a_19_27_NC), .out_a_chain(a19_27to19_28), .out_b(b19_27to20_27), .out_b0(b19_27to20_27_ping), .out_b1(b19_27to20_27_pong), .out_c(matrixC19_27), .b_data_valid_ping(b_data_valid_ping_delay19_27), .b_data_valid_pong(b_data_valid_pong_delay19_27), .mode(1'b0)); +processing_element pe19_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_19_28_NC), .in_a_chain(a19_27to19_28), .in_b(b18_28to19_28), .in_c(matrixC18_28), .out_a(out_a_19_28_NC), .out_a_chain(a19_28to19_29), .out_b(b19_28to20_28), .out_b0(b19_28to20_28_ping), .out_b1(b19_28to20_28_pong), .out_c(matrixC19_28), .b_data_valid_ping(b_data_valid_ping_delay19_28), .b_data_valid_pong(b_data_valid_pong_delay19_28), .mode(1'b0)); +processing_element pe19_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay48), .in_a(in_a_19_29_NC), .in_a_chain(a19_28to19_29), .in_b(b18_29to19_29), .in_c(matrixC18_29), .out_a(out_a_19_29_NC), .out_a_chain(a19_29to19_30), .out_b(b19_29to20_29), .out_b0(b19_29to20_29_ping), .out_b1(b19_29to20_29_pong), .out_c(matrixC19_29), .b_data_valid_ping(b_data_valid_ping_delay19_29), .b_data_valid_pong(b_data_valid_pong_delay19_29), .mode(1'b0)); +processing_element pe19_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay49), .in_a(in_a_19_30_NC), .in_a_chain(a19_29to19_30), .in_b(b18_30to19_30), .in_c(matrixC18_30), .out_a(out_a_19_30_NC), .out_a_chain(a19_30to19_31), .out_b(b19_30to20_30), .out_b0(b19_30to20_30_ping), .out_b1(b19_30to20_30_pong), .out_c(matrixC19_30), .b_data_valid_ping(b_data_valid_ping_delay19_30), .b_data_valid_pong(b_data_valid_pong_delay19_30), .mode(1'b0)); +processing_element pe19_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay50), .in_a(in_a_19_31_NC), .in_a_chain(a19_30to19_31), .in_b(b18_31to19_31), .in_c(matrixC18_31), .out_a(out_a_19_31_NC), .out_a_chain(a19_31to19_32), .out_b(b19_31to20_31), .out_b0(b19_31to20_31_ping), .out_b1(b19_31to20_31_pong), .out_c(matrixC19_31), .b_data_valid_ping(b_data_valid_ping_delay19_31), .b_data_valid_pong(b_data_valid_pong_delay19_31), .mode(1'b0)); +processing_element pe20_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(a20), .in_a_chain(in_a_chain_20_0_NC), .in_b(b19_0to20_0), .in_c(matrixC19_0), .out_a(out_a_20_0_NC), .out_a_chain(a20_0to20_1), .out_b(b20_0to21_0), .out_b0(b20_0to21_0_ping), .out_b1(b20_0to21_0_pong), .out_c(matrixC20_0), .b_data_valid_ping(b_data_valid_ping_delay20_0), .b_data_valid_pong(b_data_valid_pong_delay20_0), .mode(1'b1)); +processing_element pe20_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_20_1_NC), .in_a_chain(a20_0to20_1), .in_b(b19_1to20_1), .in_c(matrixC19_1), .out_a(out_a_20_1_NC), .out_a_chain(a20_1to20_2), .out_b(b20_1to21_1), .out_b0(b20_1to21_1_ping), .out_b1(b20_1to21_1_pong), .out_c(matrixC20_1), .b_data_valid_ping(b_data_valid_ping_delay20_1), .b_data_valid_pong(b_data_valid_pong_delay20_1), .mode(1'b0)); +processing_element pe20_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_20_2_NC), .in_a_chain(a20_1to20_2), .in_b(b19_2to20_2), .in_c(matrixC19_2), .out_a(out_a_20_2_NC), .out_a_chain(a20_2to20_3), .out_b(b20_2to21_2), .out_b0(b20_2to21_2_ping), .out_b1(b20_2to21_2_pong), .out_c(matrixC20_2), .b_data_valid_ping(b_data_valid_ping_delay20_2), .b_data_valid_pong(b_data_valid_pong_delay20_2), .mode(1'b0)); +processing_element pe20_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_20_3_NC), .in_a_chain(a20_2to20_3), .in_b(b19_3to20_3), .in_c(matrixC19_3), .out_a(out_a_20_3_NC), .out_a_chain(a20_3to20_4), .out_b(b20_3to21_3), .out_b0(b20_3to21_3_ping), .out_b1(b20_3to21_3_pong), .out_c(matrixC20_3), .b_data_valid_ping(b_data_valid_ping_delay20_3), .b_data_valid_pong(b_data_valid_pong_delay20_3), .mode(1'b0)); +processing_element pe20_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_20_4_NC), .in_a_chain(a20_3to20_4), .in_b(b19_4to20_4), .in_c(matrixC19_4), .out_a(out_a_20_4_NC), .out_a_chain(a20_4to20_5), .out_b(b20_4to21_4), .out_b0(b20_4to21_4_ping), .out_b1(b20_4to21_4_pong), .out_c(matrixC20_4), .b_data_valid_ping(b_data_valid_ping_delay20_4), .b_data_valid_pong(b_data_valid_pong_delay20_4), .mode(1'b0)); +processing_element pe20_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_20_5_NC), .in_a_chain(a20_4to20_5), .in_b(b19_5to20_5), .in_c(matrixC19_5), .out_a(out_a_20_5_NC), .out_a_chain(a20_5to20_6), .out_b(b20_5to21_5), .out_b0(b20_5to21_5_ping), .out_b1(b20_5to21_5_pong), .out_c(matrixC20_5), .b_data_valid_ping(b_data_valid_ping_delay20_5), .b_data_valid_pong(b_data_valid_pong_delay20_5), .mode(1'b0)); +processing_element pe20_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_20_6_NC), .in_a_chain(a20_5to20_6), .in_b(b19_6to20_6), .in_c(matrixC19_6), .out_a(out_a_20_6_NC), .out_a_chain(a20_6to20_7), .out_b(b20_6to21_6), .out_b0(b20_6to21_6_ping), .out_b1(b20_6to21_6_pong), .out_c(matrixC20_6), .b_data_valid_ping(b_data_valid_ping_delay20_6), .b_data_valid_pong(b_data_valid_pong_delay20_6), .mode(1'b0)); +processing_element pe20_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_20_7_NC), .in_a_chain(a20_6to20_7), .in_b(b19_7to20_7), .in_c(matrixC19_7), .out_a(out_a_20_7_NC), .out_a_chain(a20_7to20_8), .out_b(b20_7to21_7), .out_b0(b20_7to21_7_ping), .out_b1(b20_7to21_7_pong), .out_c(matrixC20_7), .b_data_valid_ping(b_data_valid_ping_delay20_7), .b_data_valid_pong(b_data_valid_pong_delay20_7), .mode(1'b0)); +processing_element pe20_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_20_8_NC), .in_a_chain(a20_7to20_8), .in_b(b19_8to20_8), .in_c(matrixC19_8), .out_a(out_a_20_8_NC), .out_a_chain(a20_8to20_9), .out_b(b20_8to21_8), .out_b0(b20_8to21_8_ping), .out_b1(b20_8to21_8_pong), .out_c(matrixC20_8), .b_data_valid_ping(b_data_valid_ping_delay20_8), .b_data_valid_pong(b_data_valid_pong_delay20_8), .mode(1'b0)); +processing_element pe20_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_20_9_NC), .in_a_chain(a20_8to20_9), .in_b(b19_9to20_9), .in_c(matrixC19_9), .out_a(out_a_20_9_NC), .out_a_chain(a20_9to20_10), .out_b(b20_9to21_9), .out_b0(b20_9to21_9_ping), .out_b1(b20_9to21_9_pong), .out_c(matrixC20_9), .b_data_valid_ping(b_data_valid_ping_delay20_9), .b_data_valid_pong(b_data_valid_pong_delay20_9), .mode(1'b0)); +processing_element pe20_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_20_10_NC), .in_a_chain(a20_9to20_10), .in_b(b19_10to20_10), .in_c(matrixC19_10), .out_a(out_a_20_10_NC), .out_a_chain(a20_10to20_11), .out_b(b20_10to21_10), .out_b0(b20_10to21_10_ping), .out_b1(b20_10to21_10_pong), .out_c(matrixC20_10), .b_data_valid_ping(b_data_valid_ping_delay20_10), .b_data_valid_pong(b_data_valid_pong_delay20_10), .mode(1'b0)); +processing_element pe20_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_20_11_NC), .in_a_chain(a20_10to20_11), .in_b(b19_11to20_11), .in_c(matrixC19_11), .out_a(out_a_20_11_NC), .out_a_chain(a20_11to20_12), .out_b(b20_11to21_11), .out_b0(b20_11to21_11_ping), .out_b1(b20_11to21_11_pong), .out_c(matrixC20_11), .b_data_valid_ping(b_data_valid_ping_delay20_11), .b_data_valid_pong(b_data_valid_pong_delay20_11), .mode(1'b0)); +processing_element pe20_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_20_12_NC), .in_a_chain(a20_11to20_12), .in_b(b19_12to20_12), .in_c(matrixC19_12), .out_a(out_a_20_12_NC), .out_a_chain(a20_12to20_13), .out_b(b20_12to21_12), .out_b0(b20_12to21_12_ping), .out_b1(b20_12to21_12_pong), .out_c(matrixC20_12), .b_data_valid_ping(b_data_valid_ping_delay20_12), .b_data_valid_pong(b_data_valid_pong_delay20_12), .mode(1'b0)); +processing_element pe20_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_20_13_NC), .in_a_chain(a20_12to20_13), .in_b(b19_13to20_13), .in_c(matrixC19_13), .out_a(out_a_20_13_NC), .out_a_chain(a20_13to20_14), .out_b(b20_13to21_13), .out_b0(b20_13to21_13_ping), .out_b1(b20_13to21_13_pong), .out_c(matrixC20_13), .b_data_valid_ping(b_data_valid_ping_delay20_13), .b_data_valid_pong(b_data_valid_pong_delay20_13), .mode(1'b0)); +processing_element pe20_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_20_14_NC), .in_a_chain(a20_13to20_14), .in_b(b19_14to20_14), .in_c(matrixC19_14), .out_a(out_a_20_14_NC), .out_a_chain(a20_14to20_15), .out_b(b20_14to21_14), .out_b0(b20_14to21_14_ping), .out_b1(b20_14to21_14_pong), .out_c(matrixC20_14), .b_data_valid_ping(b_data_valid_ping_delay20_14), .b_data_valid_pong(b_data_valid_pong_delay20_14), .mode(1'b0)); +processing_element pe20_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_20_15_NC), .in_a_chain(a20_14to20_15), .in_b(b19_15to20_15), .in_c(matrixC19_15), .out_a(out_a_20_15_NC), .out_a_chain(a20_15to20_16), .out_b(b20_15to21_15), .out_b0(b20_15to21_15_ping), .out_b1(b20_15to21_15_pong), .out_c(matrixC20_15), .b_data_valid_ping(b_data_valid_ping_delay20_15), .b_data_valid_pong(b_data_valid_pong_delay20_15), .mode(1'b0)); +processing_element pe20_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_20_16_NC), .in_a_chain(a20_15to20_16), .in_b(b19_16to20_16), .in_c(matrixC19_16), .out_a(out_a_20_16_NC), .out_a_chain(a20_16to20_17), .out_b(b20_16to21_16), .out_b0(b20_16to21_16_ping), .out_b1(b20_16to21_16_pong), .out_c(matrixC20_16), .b_data_valid_ping(b_data_valid_ping_delay20_16), .b_data_valid_pong(b_data_valid_pong_delay20_16), .mode(1'b0)); +processing_element pe20_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_20_17_NC), .in_a_chain(a20_16to20_17), .in_b(b19_17to20_17), .in_c(matrixC19_17), .out_a(out_a_20_17_NC), .out_a_chain(a20_17to20_18), .out_b(b20_17to21_17), .out_b0(b20_17to21_17_ping), .out_b1(b20_17to21_17_pong), .out_c(matrixC20_17), .b_data_valid_ping(b_data_valid_ping_delay20_17), .b_data_valid_pong(b_data_valid_pong_delay20_17), .mode(1'b0)); +processing_element pe20_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_20_18_NC), .in_a_chain(a20_17to20_18), .in_b(b19_18to20_18), .in_c(matrixC19_18), .out_a(out_a_20_18_NC), .out_a_chain(a20_18to20_19), .out_b(b20_18to21_18), .out_b0(b20_18to21_18_ping), .out_b1(b20_18to21_18_pong), .out_c(matrixC20_18), .b_data_valid_ping(b_data_valid_ping_delay20_18), .b_data_valid_pong(b_data_valid_pong_delay20_18), .mode(1'b0)); +processing_element pe20_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_20_19_NC), .in_a_chain(a20_18to20_19), .in_b(b19_19to20_19), .in_c(matrixC19_19), .out_a(out_a_20_19_NC), .out_a_chain(a20_19to20_20), .out_b(b20_19to21_19), .out_b0(b20_19to21_19_ping), .out_b1(b20_19to21_19_pong), .out_c(matrixC20_19), .b_data_valid_ping(b_data_valid_ping_delay20_19), .b_data_valid_pong(b_data_valid_pong_delay20_19), .mode(1'b0)); +processing_element pe20_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_20_20_NC), .in_a_chain(a20_19to20_20), .in_b(b19_20to20_20), .in_c(matrixC19_20), .out_a(out_a_20_20_NC), .out_a_chain(a20_20to20_21), .out_b(b20_20to21_20), .out_b0(b20_20to21_20_ping), .out_b1(b20_20to21_20_pong), .out_c(matrixC20_20), .b_data_valid_ping(b_data_valid_ping_delay20_20), .b_data_valid_pong(b_data_valid_pong_delay20_20), .mode(1'b0)); +processing_element pe20_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_20_21_NC), .in_a_chain(a20_20to20_21), .in_b(b19_21to20_21), .in_c(matrixC19_21), .out_a(out_a_20_21_NC), .out_a_chain(a20_21to20_22), .out_b(b20_21to21_21), .out_b0(b20_21to21_21_ping), .out_b1(b20_21to21_21_pong), .out_c(matrixC20_21), .b_data_valid_ping(b_data_valid_ping_delay20_21), .b_data_valid_pong(b_data_valid_pong_delay20_21), .mode(1'b0)); +processing_element pe20_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_20_22_NC), .in_a_chain(a20_21to20_22), .in_b(b19_22to20_22), .in_c(matrixC19_22), .out_a(out_a_20_22_NC), .out_a_chain(a20_22to20_23), .out_b(b20_22to21_22), .out_b0(b20_22to21_22_ping), .out_b1(b20_22to21_22_pong), .out_c(matrixC20_22), .b_data_valid_ping(b_data_valid_ping_delay20_22), .b_data_valid_pong(b_data_valid_pong_delay20_22), .mode(1'b0)); +processing_element pe20_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_20_23_NC), .in_a_chain(a20_22to20_23), .in_b(b19_23to20_23), .in_c(matrixC19_23), .out_a(out_a_20_23_NC), .out_a_chain(a20_23to20_24), .out_b(b20_23to21_23), .out_b0(b20_23to21_23_ping), .out_b1(b20_23to21_23_pong), .out_c(matrixC20_23), .b_data_valid_ping(b_data_valid_ping_delay20_23), .b_data_valid_pong(b_data_valid_pong_delay20_23), .mode(1'b0)); +processing_element pe20_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_20_24_NC), .in_a_chain(a20_23to20_24), .in_b(b19_24to20_24), .in_c(matrixC19_24), .out_a(out_a_20_24_NC), .out_a_chain(a20_24to20_25), .out_b(b20_24to21_24), .out_b0(b20_24to21_24_ping), .out_b1(b20_24to21_24_pong), .out_c(matrixC20_24), .b_data_valid_ping(b_data_valid_ping_delay20_24), .b_data_valid_pong(b_data_valid_pong_delay20_24), .mode(1'b0)); +processing_element pe20_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_20_25_NC), .in_a_chain(a20_24to20_25), .in_b(b19_25to20_25), .in_c(matrixC19_25), .out_a(out_a_20_25_NC), .out_a_chain(a20_25to20_26), .out_b(b20_25to21_25), .out_b0(b20_25to21_25_ping), .out_b1(b20_25to21_25_pong), .out_c(matrixC20_25), .b_data_valid_ping(b_data_valid_ping_delay20_25), .b_data_valid_pong(b_data_valid_pong_delay20_25), .mode(1'b0)); +processing_element pe20_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_20_26_NC), .in_a_chain(a20_25to20_26), .in_b(b19_26to20_26), .in_c(matrixC19_26), .out_a(out_a_20_26_NC), .out_a_chain(a20_26to20_27), .out_b(b20_26to21_26), .out_b0(b20_26to21_26_ping), .out_b1(b20_26to21_26_pong), .out_c(matrixC20_26), .b_data_valid_ping(b_data_valid_ping_delay20_26), .b_data_valid_pong(b_data_valid_pong_delay20_26), .mode(1'b0)); +processing_element pe20_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_20_27_NC), .in_a_chain(a20_26to20_27), .in_b(b19_27to20_27), .in_c(matrixC19_27), .out_a(out_a_20_27_NC), .out_a_chain(a20_27to20_28), .out_b(b20_27to21_27), .out_b0(b20_27to21_27_ping), .out_b1(b20_27to21_27_pong), .out_c(matrixC20_27), .b_data_valid_ping(b_data_valid_ping_delay20_27), .b_data_valid_pong(b_data_valid_pong_delay20_27), .mode(1'b0)); +processing_element pe20_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay48), .in_a(in_a_20_28_NC), .in_a_chain(a20_27to20_28), .in_b(b19_28to20_28), .in_c(matrixC19_28), .out_a(out_a_20_28_NC), .out_a_chain(a20_28to20_29), .out_b(b20_28to21_28), .out_b0(b20_28to21_28_ping), .out_b1(b20_28to21_28_pong), .out_c(matrixC20_28), .b_data_valid_ping(b_data_valid_ping_delay20_28), .b_data_valid_pong(b_data_valid_pong_delay20_28), .mode(1'b0)); +processing_element pe20_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay49), .in_a(in_a_20_29_NC), .in_a_chain(a20_28to20_29), .in_b(b19_29to20_29), .in_c(matrixC19_29), .out_a(out_a_20_29_NC), .out_a_chain(a20_29to20_30), .out_b(b20_29to21_29), .out_b0(b20_29to21_29_ping), .out_b1(b20_29to21_29_pong), .out_c(matrixC20_29), .b_data_valid_ping(b_data_valid_ping_delay20_29), .b_data_valid_pong(b_data_valid_pong_delay20_29), .mode(1'b0)); +processing_element pe20_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay50), .in_a(in_a_20_30_NC), .in_a_chain(a20_29to20_30), .in_b(b19_30to20_30), .in_c(matrixC19_30), .out_a(out_a_20_30_NC), .out_a_chain(a20_30to20_31), .out_b(b20_30to21_30), .out_b0(b20_30to21_30_ping), .out_b1(b20_30to21_30_pong), .out_c(matrixC20_30), .b_data_valid_ping(b_data_valid_ping_delay20_30), .b_data_valid_pong(b_data_valid_pong_delay20_30), .mode(1'b0)); +processing_element pe20_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay51), .in_a(in_a_20_31_NC), .in_a_chain(a20_30to20_31), .in_b(b19_31to20_31), .in_c(matrixC19_31), .out_a(out_a_20_31_NC), .out_a_chain(a20_31to20_32), .out_b(b20_31to21_31), .out_b0(b20_31to21_31_ping), .out_b1(b20_31to21_31_pong), .out_c(matrixC20_31), .b_data_valid_ping(b_data_valid_ping_delay20_31), .b_data_valid_pong(b_data_valid_pong_delay20_31), .mode(1'b0)); +processing_element pe21_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(a21), .in_a_chain(in_a_chain_21_0_NC), .in_b(b20_0to21_0), .in_c(matrixC20_0), .out_a(out_a_21_0_NC), .out_a_chain(a21_0to21_1), .out_b(b21_0to22_0), .out_b0(b21_0to22_0_ping), .out_b1(b21_0to22_0_pong), .out_c(matrixC21_0), .b_data_valid_ping(b_data_valid_ping_delay21_0), .b_data_valid_pong(b_data_valid_pong_delay21_0), .mode(1'b1)); +processing_element pe21_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_21_1_NC), .in_a_chain(a21_0to21_1), .in_b(b20_1to21_1), .in_c(matrixC20_1), .out_a(out_a_21_1_NC), .out_a_chain(a21_1to21_2), .out_b(b21_1to22_1), .out_b0(b21_1to22_1_ping), .out_b1(b21_1to22_1_pong), .out_c(matrixC21_1), .b_data_valid_ping(b_data_valid_ping_delay21_1), .b_data_valid_pong(b_data_valid_pong_delay21_1), .mode(1'b0)); +processing_element pe21_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_21_2_NC), .in_a_chain(a21_1to21_2), .in_b(b20_2to21_2), .in_c(matrixC20_2), .out_a(out_a_21_2_NC), .out_a_chain(a21_2to21_3), .out_b(b21_2to22_2), .out_b0(b21_2to22_2_ping), .out_b1(b21_2to22_2_pong), .out_c(matrixC21_2), .b_data_valid_ping(b_data_valid_ping_delay21_2), .b_data_valid_pong(b_data_valid_pong_delay21_2), .mode(1'b0)); +processing_element pe21_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_21_3_NC), .in_a_chain(a21_2to21_3), .in_b(b20_3to21_3), .in_c(matrixC20_3), .out_a(out_a_21_3_NC), .out_a_chain(a21_3to21_4), .out_b(b21_3to22_3), .out_b0(b21_3to22_3_ping), .out_b1(b21_3to22_3_pong), .out_c(matrixC21_3), .b_data_valid_ping(b_data_valid_ping_delay21_3), .b_data_valid_pong(b_data_valid_pong_delay21_3), .mode(1'b0)); +processing_element pe21_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_21_4_NC), .in_a_chain(a21_3to21_4), .in_b(b20_4to21_4), .in_c(matrixC20_4), .out_a(out_a_21_4_NC), .out_a_chain(a21_4to21_5), .out_b(b21_4to22_4), .out_b0(b21_4to22_4_ping), .out_b1(b21_4to22_4_pong), .out_c(matrixC21_4), .b_data_valid_ping(b_data_valid_ping_delay21_4), .b_data_valid_pong(b_data_valid_pong_delay21_4), .mode(1'b0)); +processing_element pe21_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_21_5_NC), .in_a_chain(a21_4to21_5), .in_b(b20_5to21_5), .in_c(matrixC20_5), .out_a(out_a_21_5_NC), .out_a_chain(a21_5to21_6), .out_b(b21_5to22_5), .out_b0(b21_5to22_5_ping), .out_b1(b21_5to22_5_pong), .out_c(matrixC21_5), .b_data_valid_ping(b_data_valid_ping_delay21_5), .b_data_valid_pong(b_data_valid_pong_delay21_5), .mode(1'b0)); +processing_element pe21_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_21_6_NC), .in_a_chain(a21_5to21_6), .in_b(b20_6to21_6), .in_c(matrixC20_6), .out_a(out_a_21_6_NC), .out_a_chain(a21_6to21_7), .out_b(b21_6to22_6), .out_b0(b21_6to22_6_ping), .out_b1(b21_6to22_6_pong), .out_c(matrixC21_6), .b_data_valid_ping(b_data_valid_ping_delay21_6), .b_data_valid_pong(b_data_valid_pong_delay21_6), .mode(1'b0)); +processing_element pe21_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_21_7_NC), .in_a_chain(a21_6to21_7), .in_b(b20_7to21_7), .in_c(matrixC20_7), .out_a(out_a_21_7_NC), .out_a_chain(a21_7to21_8), .out_b(b21_7to22_7), .out_b0(b21_7to22_7_ping), .out_b1(b21_7to22_7_pong), .out_c(matrixC21_7), .b_data_valid_ping(b_data_valid_ping_delay21_7), .b_data_valid_pong(b_data_valid_pong_delay21_7), .mode(1'b0)); +processing_element pe21_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_21_8_NC), .in_a_chain(a21_7to21_8), .in_b(b20_8to21_8), .in_c(matrixC20_8), .out_a(out_a_21_8_NC), .out_a_chain(a21_8to21_9), .out_b(b21_8to22_8), .out_b0(b21_8to22_8_ping), .out_b1(b21_8to22_8_pong), .out_c(matrixC21_8), .b_data_valid_ping(b_data_valid_ping_delay21_8), .b_data_valid_pong(b_data_valid_pong_delay21_8), .mode(1'b0)); +processing_element pe21_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_21_9_NC), .in_a_chain(a21_8to21_9), .in_b(b20_9to21_9), .in_c(matrixC20_9), .out_a(out_a_21_9_NC), .out_a_chain(a21_9to21_10), .out_b(b21_9to22_9), .out_b0(b21_9to22_9_ping), .out_b1(b21_9to22_9_pong), .out_c(matrixC21_9), .b_data_valid_ping(b_data_valid_ping_delay21_9), .b_data_valid_pong(b_data_valid_pong_delay21_9), .mode(1'b0)); +processing_element pe21_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_21_10_NC), .in_a_chain(a21_9to21_10), .in_b(b20_10to21_10), .in_c(matrixC20_10), .out_a(out_a_21_10_NC), .out_a_chain(a21_10to21_11), .out_b(b21_10to22_10), .out_b0(b21_10to22_10_ping), .out_b1(b21_10to22_10_pong), .out_c(matrixC21_10), .b_data_valid_ping(b_data_valid_ping_delay21_10), .b_data_valid_pong(b_data_valid_pong_delay21_10), .mode(1'b0)); +processing_element pe21_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_21_11_NC), .in_a_chain(a21_10to21_11), .in_b(b20_11to21_11), .in_c(matrixC20_11), .out_a(out_a_21_11_NC), .out_a_chain(a21_11to21_12), .out_b(b21_11to22_11), .out_b0(b21_11to22_11_ping), .out_b1(b21_11to22_11_pong), .out_c(matrixC21_11), .b_data_valid_ping(b_data_valid_ping_delay21_11), .b_data_valid_pong(b_data_valid_pong_delay21_11), .mode(1'b0)); +processing_element pe21_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_21_12_NC), .in_a_chain(a21_11to21_12), .in_b(b20_12to21_12), .in_c(matrixC20_12), .out_a(out_a_21_12_NC), .out_a_chain(a21_12to21_13), .out_b(b21_12to22_12), .out_b0(b21_12to22_12_ping), .out_b1(b21_12to22_12_pong), .out_c(matrixC21_12), .b_data_valid_ping(b_data_valid_ping_delay21_12), .b_data_valid_pong(b_data_valid_pong_delay21_12), .mode(1'b0)); +processing_element pe21_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_21_13_NC), .in_a_chain(a21_12to21_13), .in_b(b20_13to21_13), .in_c(matrixC20_13), .out_a(out_a_21_13_NC), .out_a_chain(a21_13to21_14), .out_b(b21_13to22_13), .out_b0(b21_13to22_13_ping), .out_b1(b21_13to22_13_pong), .out_c(matrixC21_13), .b_data_valid_ping(b_data_valid_ping_delay21_13), .b_data_valid_pong(b_data_valid_pong_delay21_13), .mode(1'b0)); +processing_element pe21_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_21_14_NC), .in_a_chain(a21_13to21_14), .in_b(b20_14to21_14), .in_c(matrixC20_14), .out_a(out_a_21_14_NC), .out_a_chain(a21_14to21_15), .out_b(b21_14to22_14), .out_b0(b21_14to22_14_ping), .out_b1(b21_14to22_14_pong), .out_c(matrixC21_14), .b_data_valid_ping(b_data_valid_ping_delay21_14), .b_data_valid_pong(b_data_valid_pong_delay21_14), .mode(1'b0)); +processing_element pe21_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_21_15_NC), .in_a_chain(a21_14to21_15), .in_b(b20_15to21_15), .in_c(matrixC20_15), .out_a(out_a_21_15_NC), .out_a_chain(a21_15to21_16), .out_b(b21_15to22_15), .out_b0(b21_15to22_15_ping), .out_b1(b21_15to22_15_pong), .out_c(matrixC21_15), .b_data_valid_ping(b_data_valid_ping_delay21_15), .b_data_valid_pong(b_data_valid_pong_delay21_15), .mode(1'b0)); +processing_element pe21_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_21_16_NC), .in_a_chain(a21_15to21_16), .in_b(b20_16to21_16), .in_c(matrixC20_16), .out_a(out_a_21_16_NC), .out_a_chain(a21_16to21_17), .out_b(b21_16to22_16), .out_b0(b21_16to22_16_ping), .out_b1(b21_16to22_16_pong), .out_c(matrixC21_16), .b_data_valid_ping(b_data_valid_ping_delay21_16), .b_data_valid_pong(b_data_valid_pong_delay21_16), .mode(1'b0)); +processing_element pe21_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_21_17_NC), .in_a_chain(a21_16to21_17), .in_b(b20_17to21_17), .in_c(matrixC20_17), .out_a(out_a_21_17_NC), .out_a_chain(a21_17to21_18), .out_b(b21_17to22_17), .out_b0(b21_17to22_17_ping), .out_b1(b21_17to22_17_pong), .out_c(matrixC21_17), .b_data_valid_ping(b_data_valid_ping_delay21_17), .b_data_valid_pong(b_data_valid_pong_delay21_17), .mode(1'b0)); +processing_element pe21_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_21_18_NC), .in_a_chain(a21_17to21_18), .in_b(b20_18to21_18), .in_c(matrixC20_18), .out_a(out_a_21_18_NC), .out_a_chain(a21_18to21_19), .out_b(b21_18to22_18), .out_b0(b21_18to22_18_ping), .out_b1(b21_18to22_18_pong), .out_c(matrixC21_18), .b_data_valid_ping(b_data_valid_ping_delay21_18), .b_data_valid_pong(b_data_valid_pong_delay21_18), .mode(1'b0)); +processing_element pe21_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_21_19_NC), .in_a_chain(a21_18to21_19), .in_b(b20_19to21_19), .in_c(matrixC20_19), .out_a(out_a_21_19_NC), .out_a_chain(a21_19to21_20), .out_b(b21_19to22_19), .out_b0(b21_19to22_19_ping), .out_b1(b21_19to22_19_pong), .out_c(matrixC21_19), .b_data_valid_ping(b_data_valid_ping_delay21_19), .b_data_valid_pong(b_data_valid_pong_delay21_19), .mode(1'b0)); +processing_element pe21_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_21_20_NC), .in_a_chain(a21_19to21_20), .in_b(b20_20to21_20), .in_c(matrixC20_20), .out_a(out_a_21_20_NC), .out_a_chain(a21_20to21_21), .out_b(b21_20to22_20), .out_b0(b21_20to22_20_ping), .out_b1(b21_20to22_20_pong), .out_c(matrixC21_20), .b_data_valid_ping(b_data_valid_ping_delay21_20), .b_data_valid_pong(b_data_valid_pong_delay21_20), .mode(1'b0)); +processing_element pe21_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_21_21_NC), .in_a_chain(a21_20to21_21), .in_b(b20_21to21_21), .in_c(matrixC20_21), .out_a(out_a_21_21_NC), .out_a_chain(a21_21to21_22), .out_b(b21_21to22_21), .out_b0(b21_21to22_21_ping), .out_b1(b21_21to22_21_pong), .out_c(matrixC21_21), .b_data_valid_ping(b_data_valid_ping_delay21_21), .b_data_valid_pong(b_data_valid_pong_delay21_21), .mode(1'b0)); +processing_element pe21_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_21_22_NC), .in_a_chain(a21_21to21_22), .in_b(b20_22to21_22), .in_c(matrixC20_22), .out_a(out_a_21_22_NC), .out_a_chain(a21_22to21_23), .out_b(b21_22to22_22), .out_b0(b21_22to22_22_ping), .out_b1(b21_22to22_22_pong), .out_c(matrixC21_22), .b_data_valid_ping(b_data_valid_ping_delay21_22), .b_data_valid_pong(b_data_valid_pong_delay21_22), .mode(1'b0)); +processing_element pe21_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_21_23_NC), .in_a_chain(a21_22to21_23), .in_b(b20_23to21_23), .in_c(matrixC20_23), .out_a(out_a_21_23_NC), .out_a_chain(a21_23to21_24), .out_b(b21_23to22_23), .out_b0(b21_23to22_23_ping), .out_b1(b21_23to22_23_pong), .out_c(matrixC21_23), .b_data_valid_ping(b_data_valid_ping_delay21_23), .b_data_valid_pong(b_data_valid_pong_delay21_23), .mode(1'b0)); +processing_element pe21_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_21_24_NC), .in_a_chain(a21_23to21_24), .in_b(b20_24to21_24), .in_c(matrixC20_24), .out_a(out_a_21_24_NC), .out_a_chain(a21_24to21_25), .out_b(b21_24to22_24), .out_b0(b21_24to22_24_ping), .out_b1(b21_24to22_24_pong), .out_c(matrixC21_24), .b_data_valid_ping(b_data_valid_ping_delay21_24), .b_data_valid_pong(b_data_valid_pong_delay21_24), .mode(1'b0)); +processing_element pe21_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_21_25_NC), .in_a_chain(a21_24to21_25), .in_b(b20_25to21_25), .in_c(matrixC20_25), .out_a(out_a_21_25_NC), .out_a_chain(a21_25to21_26), .out_b(b21_25to22_25), .out_b0(b21_25to22_25_ping), .out_b1(b21_25to22_25_pong), .out_c(matrixC21_25), .b_data_valid_ping(b_data_valid_ping_delay21_25), .b_data_valid_pong(b_data_valid_pong_delay21_25), .mode(1'b0)); +processing_element pe21_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_21_26_NC), .in_a_chain(a21_25to21_26), .in_b(b20_26to21_26), .in_c(matrixC20_26), .out_a(out_a_21_26_NC), .out_a_chain(a21_26to21_27), .out_b(b21_26to22_26), .out_b0(b21_26to22_26_ping), .out_b1(b21_26to22_26_pong), .out_c(matrixC21_26), .b_data_valid_ping(b_data_valid_ping_delay21_26), .b_data_valid_pong(b_data_valid_pong_delay21_26), .mode(1'b0)); +processing_element pe21_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay48), .in_a(in_a_21_27_NC), .in_a_chain(a21_26to21_27), .in_b(b20_27to21_27), .in_c(matrixC20_27), .out_a(out_a_21_27_NC), .out_a_chain(a21_27to21_28), .out_b(b21_27to22_27), .out_b0(b21_27to22_27_ping), .out_b1(b21_27to22_27_pong), .out_c(matrixC21_27), .b_data_valid_ping(b_data_valid_ping_delay21_27), .b_data_valid_pong(b_data_valid_pong_delay21_27), .mode(1'b0)); +processing_element pe21_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay49), .in_a(in_a_21_28_NC), .in_a_chain(a21_27to21_28), .in_b(b20_28to21_28), .in_c(matrixC20_28), .out_a(out_a_21_28_NC), .out_a_chain(a21_28to21_29), .out_b(b21_28to22_28), .out_b0(b21_28to22_28_ping), .out_b1(b21_28to22_28_pong), .out_c(matrixC21_28), .b_data_valid_ping(b_data_valid_ping_delay21_28), .b_data_valid_pong(b_data_valid_pong_delay21_28), .mode(1'b0)); +processing_element pe21_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay50), .in_a(in_a_21_29_NC), .in_a_chain(a21_28to21_29), .in_b(b20_29to21_29), .in_c(matrixC20_29), .out_a(out_a_21_29_NC), .out_a_chain(a21_29to21_30), .out_b(b21_29to22_29), .out_b0(b21_29to22_29_ping), .out_b1(b21_29to22_29_pong), .out_c(matrixC21_29), .b_data_valid_ping(b_data_valid_ping_delay21_29), .b_data_valid_pong(b_data_valid_pong_delay21_29), .mode(1'b0)); +processing_element pe21_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay51), .in_a(in_a_21_30_NC), .in_a_chain(a21_29to21_30), .in_b(b20_30to21_30), .in_c(matrixC20_30), .out_a(out_a_21_30_NC), .out_a_chain(a21_30to21_31), .out_b(b21_30to22_30), .out_b0(b21_30to22_30_ping), .out_b1(b21_30to22_30_pong), .out_c(matrixC21_30), .b_data_valid_ping(b_data_valid_ping_delay21_30), .b_data_valid_pong(b_data_valid_pong_delay21_30), .mode(1'b0)); +processing_element pe21_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay52), .in_a(in_a_21_31_NC), .in_a_chain(a21_30to21_31), .in_b(b20_31to21_31), .in_c(matrixC20_31), .out_a(out_a_21_31_NC), .out_a_chain(a21_31to21_32), .out_b(b21_31to22_31), .out_b0(b21_31to22_31_ping), .out_b1(b21_31to22_31_pong), .out_c(matrixC21_31), .b_data_valid_ping(b_data_valid_ping_delay21_31), .b_data_valid_pong(b_data_valid_pong_delay21_31), .mode(1'b0)); +processing_element pe22_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(a22), .in_a_chain(in_a_chain_22_0_NC), .in_b(b21_0to22_0), .in_c(matrixC21_0), .out_a(out_a_22_0_NC), .out_a_chain(a22_0to22_1), .out_b(b22_0to23_0), .out_b0(b22_0to23_0_ping), .out_b1(b22_0to23_0_pong), .out_c(matrixC22_0), .b_data_valid_ping(b_data_valid_ping_delay22_0), .b_data_valid_pong(b_data_valid_pong_delay22_0), .mode(1'b1)); +processing_element pe22_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_22_1_NC), .in_a_chain(a22_0to22_1), .in_b(b21_1to22_1), .in_c(matrixC21_1), .out_a(out_a_22_1_NC), .out_a_chain(a22_1to22_2), .out_b(b22_1to23_1), .out_b0(b22_1to23_1_ping), .out_b1(b22_1to23_1_pong), .out_c(matrixC22_1), .b_data_valid_ping(b_data_valid_ping_delay22_1), .b_data_valid_pong(b_data_valid_pong_delay22_1), .mode(1'b0)); +processing_element pe22_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_22_2_NC), .in_a_chain(a22_1to22_2), .in_b(b21_2to22_2), .in_c(matrixC21_2), .out_a(out_a_22_2_NC), .out_a_chain(a22_2to22_3), .out_b(b22_2to23_2), .out_b0(b22_2to23_2_ping), .out_b1(b22_2to23_2_pong), .out_c(matrixC22_2), .b_data_valid_ping(b_data_valid_ping_delay22_2), .b_data_valid_pong(b_data_valid_pong_delay22_2), .mode(1'b0)); +processing_element pe22_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_22_3_NC), .in_a_chain(a22_2to22_3), .in_b(b21_3to22_3), .in_c(matrixC21_3), .out_a(out_a_22_3_NC), .out_a_chain(a22_3to22_4), .out_b(b22_3to23_3), .out_b0(b22_3to23_3_ping), .out_b1(b22_3to23_3_pong), .out_c(matrixC22_3), .b_data_valid_ping(b_data_valid_ping_delay22_3), .b_data_valid_pong(b_data_valid_pong_delay22_3), .mode(1'b0)); +processing_element pe22_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_22_4_NC), .in_a_chain(a22_3to22_4), .in_b(b21_4to22_4), .in_c(matrixC21_4), .out_a(out_a_22_4_NC), .out_a_chain(a22_4to22_5), .out_b(b22_4to23_4), .out_b0(b22_4to23_4_ping), .out_b1(b22_4to23_4_pong), .out_c(matrixC22_4), .b_data_valid_ping(b_data_valid_ping_delay22_4), .b_data_valid_pong(b_data_valid_pong_delay22_4), .mode(1'b0)); +processing_element pe22_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_22_5_NC), .in_a_chain(a22_4to22_5), .in_b(b21_5to22_5), .in_c(matrixC21_5), .out_a(out_a_22_5_NC), .out_a_chain(a22_5to22_6), .out_b(b22_5to23_5), .out_b0(b22_5to23_5_ping), .out_b1(b22_5to23_5_pong), .out_c(matrixC22_5), .b_data_valid_ping(b_data_valid_ping_delay22_5), .b_data_valid_pong(b_data_valid_pong_delay22_5), .mode(1'b0)); +processing_element pe22_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_22_6_NC), .in_a_chain(a22_5to22_6), .in_b(b21_6to22_6), .in_c(matrixC21_6), .out_a(out_a_22_6_NC), .out_a_chain(a22_6to22_7), .out_b(b22_6to23_6), .out_b0(b22_6to23_6_ping), .out_b1(b22_6to23_6_pong), .out_c(matrixC22_6), .b_data_valid_ping(b_data_valid_ping_delay22_6), .b_data_valid_pong(b_data_valid_pong_delay22_6), .mode(1'b0)); +processing_element pe22_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_22_7_NC), .in_a_chain(a22_6to22_7), .in_b(b21_7to22_7), .in_c(matrixC21_7), .out_a(out_a_22_7_NC), .out_a_chain(a22_7to22_8), .out_b(b22_7to23_7), .out_b0(b22_7to23_7_ping), .out_b1(b22_7to23_7_pong), .out_c(matrixC22_7), .b_data_valid_ping(b_data_valid_ping_delay22_7), .b_data_valid_pong(b_data_valid_pong_delay22_7), .mode(1'b0)); +processing_element pe22_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_22_8_NC), .in_a_chain(a22_7to22_8), .in_b(b21_8to22_8), .in_c(matrixC21_8), .out_a(out_a_22_8_NC), .out_a_chain(a22_8to22_9), .out_b(b22_8to23_8), .out_b0(b22_8to23_8_ping), .out_b1(b22_8to23_8_pong), .out_c(matrixC22_8), .b_data_valid_ping(b_data_valid_ping_delay22_8), .b_data_valid_pong(b_data_valid_pong_delay22_8), .mode(1'b0)); +processing_element pe22_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_22_9_NC), .in_a_chain(a22_8to22_9), .in_b(b21_9to22_9), .in_c(matrixC21_9), .out_a(out_a_22_9_NC), .out_a_chain(a22_9to22_10), .out_b(b22_9to23_9), .out_b0(b22_9to23_9_ping), .out_b1(b22_9to23_9_pong), .out_c(matrixC22_9), .b_data_valid_ping(b_data_valid_ping_delay22_9), .b_data_valid_pong(b_data_valid_pong_delay22_9), .mode(1'b0)); +processing_element pe22_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_22_10_NC), .in_a_chain(a22_9to22_10), .in_b(b21_10to22_10), .in_c(matrixC21_10), .out_a(out_a_22_10_NC), .out_a_chain(a22_10to22_11), .out_b(b22_10to23_10), .out_b0(b22_10to23_10_ping), .out_b1(b22_10to23_10_pong), .out_c(matrixC22_10), .b_data_valid_ping(b_data_valid_ping_delay22_10), .b_data_valid_pong(b_data_valid_pong_delay22_10), .mode(1'b0)); +processing_element pe22_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_22_11_NC), .in_a_chain(a22_10to22_11), .in_b(b21_11to22_11), .in_c(matrixC21_11), .out_a(out_a_22_11_NC), .out_a_chain(a22_11to22_12), .out_b(b22_11to23_11), .out_b0(b22_11to23_11_ping), .out_b1(b22_11to23_11_pong), .out_c(matrixC22_11), .b_data_valid_ping(b_data_valid_ping_delay22_11), .b_data_valid_pong(b_data_valid_pong_delay22_11), .mode(1'b0)); +processing_element pe22_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_22_12_NC), .in_a_chain(a22_11to22_12), .in_b(b21_12to22_12), .in_c(matrixC21_12), .out_a(out_a_22_12_NC), .out_a_chain(a22_12to22_13), .out_b(b22_12to23_12), .out_b0(b22_12to23_12_ping), .out_b1(b22_12to23_12_pong), .out_c(matrixC22_12), .b_data_valid_ping(b_data_valid_ping_delay22_12), .b_data_valid_pong(b_data_valid_pong_delay22_12), .mode(1'b0)); +processing_element pe22_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_22_13_NC), .in_a_chain(a22_12to22_13), .in_b(b21_13to22_13), .in_c(matrixC21_13), .out_a(out_a_22_13_NC), .out_a_chain(a22_13to22_14), .out_b(b22_13to23_13), .out_b0(b22_13to23_13_ping), .out_b1(b22_13to23_13_pong), .out_c(matrixC22_13), .b_data_valid_ping(b_data_valid_ping_delay22_13), .b_data_valid_pong(b_data_valid_pong_delay22_13), .mode(1'b0)); +processing_element pe22_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_22_14_NC), .in_a_chain(a22_13to22_14), .in_b(b21_14to22_14), .in_c(matrixC21_14), .out_a(out_a_22_14_NC), .out_a_chain(a22_14to22_15), .out_b(b22_14to23_14), .out_b0(b22_14to23_14_ping), .out_b1(b22_14to23_14_pong), .out_c(matrixC22_14), .b_data_valid_ping(b_data_valid_ping_delay22_14), .b_data_valid_pong(b_data_valid_pong_delay22_14), .mode(1'b0)); +processing_element pe22_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_22_15_NC), .in_a_chain(a22_14to22_15), .in_b(b21_15to22_15), .in_c(matrixC21_15), .out_a(out_a_22_15_NC), .out_a_chain(a22_15to22_16), .out_b(b22_15to23_15), .out_b0(b22_15to23_15_ping), .out_b1(b22_15to23_15_pong), .out_c(matrixC22_15), .b_data_valid_ping(b_data_valid_ping_delay22_15), .b_data_valid_pong(b_data_valid_pong_delay22_15), .mode(1'b0)); +processing_element pe22_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_22_16_NC), .in_a_chain(a22_15to22_16), .in_b(b21_16to22_16), .in_c(matrixC21_16), .out_a(out_a_22_16_NC), .out_a_chain(a22_16to22_17), .out_b(b22_16to23_16), .out_b0(b22_16to23_16_ping), .out_b1(b22_16to23_16_pong), .out_c(matrixC22_16), .b_data_valid_ping(b_data_valid_ping_delay22_16), .b_data_valid_pong(b_data_valid_pong_delay22_16), .mode(1'b0)); +processing_element pe22_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_22_17_NC), .in_a_chain(a22_16to22_17), .in_b(b21_17to22_17), .in_c(matrixC21_17), .out_a(out_a_22_17_NC), .out_a_chain(a22_17to22_18), .out_b(b22_17to23_17), .out_b0(b22_17to23_17_ping), .out_b1(b22_17to23_17_pong), .out_c(matrixC22_17), .b_data_valid_ping(b_data_valid_ping_delay22_17), .b_data_valid_pong(b_data_valid_pong_delay22_17), .mode(1'b0)); +processing_element pe22_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_22_18_NC), .in_a_chain(a22_17to22_18), .in_b(b21_18to22_18), .in_c(matrixC21_18), .out_a(out_a_22_18_NC), .out_a_chain(a22_18to22_19), .out_b(b22_18to23_18), .out_b0(b22_18to23_18_ping), .out_b1(b22_18to23_18_pong), .out_c(matrixC22_18), .b_data_valid_ping(b_data_valid_ping_delay22_18), .b_data_valid_pong(b_data_valid_pong_delay22_18), .mode(1'b0)); +processing_element pe22_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_22_19_NC), .in_a_chain(a22_18to22_19), .in_b(b21_19to22_19), .in_c(matrixC21_19), .out_a(out_a_22_19_NC), .out_a_chain(a22_19to22_20), .out_b(b22_19to23_19), .out_b0(b22_19to23_19_ping), .out_b1(b22_19to23_19_pong), .out_c(matrixC22_19), .b_data_valid_ping(b_data_valid_ping_delay22_19), .b_data_valid_pong(b_data_valid_pong_delay22_19), .mode(1'b0)); +processing_element pe22_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_22_20_NC), .in_a_chain(a22_19to22_20), .in_b(b21_20to22_20), .in_c(matrixC21_20), .out_a(out_a_22_20_NC), .out_a_chain(a22_20to22_21), .out_b(b22_20to23_20), .out_b0(b22_20to23_20_ping), .out_b1(b22_20to23_20_pong), .out_c(matrixC22_20), .b_data_valid_ping(b_data_valid_ping_delay22_20), .b_data_valid_pong(b_data_valid_pong_delay22_20), .mode(1'b0)); +processing_element pe22_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_22_21_NC), .in_a_chain(a22_20to22_21), .in_b(b21_21to22_21), .in_c(matrixC21_21), .out_a(out_a_22_21_NC), .out_a_chain(a22_21to22_22), .out_b(b22_21to23_21), .out_b0(b22_21to23_21_ping), .out_b1(b22_21to23_21_pong), .out_c(matrixC22_21), .b_data_valid_ping(b_data_valid_ping_delay22_21), .b_data_valid_pong(b_data_valid_pong_delay22_21), .mode(1'b0)); +processing_element pe22_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_22_22_NC), .in_a_chain(a22_21to22_22), .in_b(b21_22to22_22), .in_c(matrixC21_22), .out_a(out_a_22_22_NC), .out_a_chain(a22_22to22_23), .out_b(b22_22to23_22), .out_b0(b22_22to23_22_ping), .out_b1(b22_22to23_22_pong), .out_c(matrixC22_22), .b_data_valid_ping(b_data_valid_ping_delay22_22), .b_data_valid_pong(b_data_valid_pong_delay22_22), .mode(1'b0)); +processing_element pe22_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_22_23_NC), .in_a_chain(a22_22to22_23), .in_b(b21_23to22_23), .in_c(matrixC21_23), .out_a(out_a_22_23_NC), .out_a_chain(a22_23to22_24), .out_b(b22_23to23_23), .out_b0(b22_23to23_23_ping), .out_b1(b22_23to23_23_pong), .out_c(matrixC22_23), .b_data_valid_ping(b_data_valid_ping_delay22_23), .b_data_valid_pong(b_data_valid_pong_delay22_23), .mode(1'b0)); +processing_element pe22_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_22_24_NC), .in_a_chain(a22_23to22_24), .in_b(b21_24to22_24), .in_c(matrixC21_24), .out_a(out_a_22_24_NC), .out_a_chain(a22_24to22_25), .out_b(b22_24to23_24), .out_b0(b22_24to23_24_ping), .out_b1(b22_24to23_24_pong), .out_c(matrixC22_24), .b_data_valid_ping(b_data_valid_ping_delay22_24), .b_data_valid_pong(b_data_valid_pong_delay22_24), .mode(1'b0)); +processing_element pe22_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_22_25_NC), .in_a_chain(a22_24to22_25), .in_b(b21_25to22_25), .in_c(matrixC21_25), .out_a(out_a_22_25_NC), .out_a_chain(a22_25to22_26), .out_b(b22_25to23_25), .out_b0(b22_25to23_25_ping), .out_b1(b22_25to23_25_pong), .out_c(matrixC22_25), .b_data_valid_ping(b_data_valid_ping_delay22_25), .b_data_valid_pong(b_data_valid_pong_delay22_25), .mode(1'b0)); +processing_element pe22_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay48), .in_a(in_a_22_26_NC), .in_a_chain(a22_25to22_26), .in_b(b21_26to22_26), .in_c(matrixC21_26), .out_a(out_a_22_26_NC), .out_a_chain(a22_26to22_27), .out_b(b22_26to23_26), .out_b0(b22_26to23_26_ping), .out_b1(b22_26to23_26_pong), .out_c(matrixC22_26), .b_data_valid_ping(b_data_valid_ping_delay22_26), .b_data_valid_pong(b_data_valid_pong_delay22_26), .mode(1'b0)); +processing_element pe22_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay49), .in_a(in_a_22_27_NC), .in_a_chain(a22_26to22_27), .in_b(b21_27to22_27), .in_c(matrixC21_27), .out_a(out_a_22_27_NC), .out_a_chain(a22_27to22_28), .out_b(b22_27to23_27), .out_b0(b22_27to23_27_ping), .out_b1(b22_27to23_27_pong), .out_c(matrixC22_27), .b_data_valid_ping(b_data_valid_ping_delay22_27), .b_data_valid_pong(b_data_valid_pong_delay22_27), .mode(1'b0)); +processing_element pe22_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay50), .in_a(in_a_22_28_NC), .in_a_chain(a22_27to22_28), .in_b(b21_28to22_28), .in_c(matrixC21_28), .out_a(out_a_22_28_NC), .out_a_chain(a22_28to22_29), .out_b(b22_28to23_28), .out_b0(b22_28to23_28_ping), .out_b1(b22_28to23_28_pong), .out_c(matrixC22_28), .b_data_valid_ping(b_data_valid_ping_delay22_28), .b_data_valid_pong(b_data_valid_pong_delay22_28), .mode(1'b0)); +processing_element pe22_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay51), .in_a(in_a_22_29_NC), .in_a_chain(a22_28to22_29), .in_b(b21_29to22_29), .in_c(matrixC21_29), .out_a(out_a_22_29_NC), .out_a_chain(a22_29to22_30), .out_b(b22_29to23_29), .out_b0(b22_29to23_29_ping), .out_b1(b22_29to23_29_pong), .out_c(matrixC22_29), .b_data_valid_ping(b_data_valid_ping_delay22_29), .b_data_valid_pong(b_data_valid_pong_delay22_29), .mode(1'b0)); +processing_element pe22_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay52), .in_a(in_a_22_30_NC), .in_a_chain(a22_29to22_30), .in_b(b21_30to22_30), .in_c(matrixC21_30), .out_a(out_a_22_30_NC), .out_a_chain(a22_30to22_31), .out_b(b22_30to23_30), .out_b0(b22_30to23_30_ping), .out_b1(b22_30to23_30_pong), .out_c(matrixC22_30), .b_data_valid_ping(b_data_valid_ping_delay22_30), .b_data_valid_pong(b_data_valid_pong_delay22_30), .mode(1'b0)); +processing_element pe22_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay53), .in_a(in_a_22_31_NC), .in_a_chain(a22_30to22_31), .in_b(b21_31to22_31), .in_c(matrixC21_31), .out_a(out_a_22_31_NC), .out_a_chain(a22_31to22_32), .out_b(b22_31to23_31), .out_b0(b22_31to23_31_ping), .out_b1(b22_31to23_31_pong), .out_c(matrixC22_31), .b_data_valid_ping(b_data_valid_ping_delay22_31), .b_data_valid_pong(b_data_valid_pong_delay22_31), .mode(1'b0)); +processing_element pe23_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(a23), .in_a_chain(in_a_chain_23_0_NC), .in_b(b22_0to23_0), .in_c(matrixC22_0), .out_a(out_a_23_0_NC), .out_a_chain(a23_0to23_1), .out_b(b23_0to24_0), .out_b0(b23_0to24_0_ping), .out_b1(b23_0to24_0_pong), .out_c(matrixC23_0), .b_data_valid_ping(b_data_valid_ping_delay23_0), .b_data_valid_pong(b_data_valid_pong_delay23_0), .mode(1'b1)); +processing_element pe23_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_23_1_NC), .in_a_chain(a23_0to23_1), .in_b(b22_1to23_1), .in_c(matrixC22_1), .out_a(out_a_23_1_NC), .out_a_chain(a23_1to23_2), .out_b(b23_1to24_1), .out_b0(b23_1to24_1_ping), .out_b1(b23_1to24_1_pong), .out_c(matrixC23_1), .b_data_valid_ping(b_data_valid_ping_delay23_1), .b_data_valid_pong(b_data_valid_pong_delay23_1), .mode(1'b0)); +processing_element pe23_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_23_2_NC), .in_a_chain(a23_1to23_2), .in_b(b22_2to23_2), .in_c(matrixC22_2), .out_a(out_a_23_2_NC), .out_a_chain(a23_2to23_3), .out_b(b23_2to24_2), .out_b0(b23_2to24_2_ping), .out_b1(b23_2to24_2_pong), .out_c(matrixC23_2), .b_data_valid_ping(b_data_valid_ping_delay23_2), .b_data_valid_pong(b_data_valid_pong_delay23_2), .mode(1'b0)); +processing_element pe23_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_23_3_NC), .in_a_chain(a23_2to23_3), .in_b(b22_3to23_3), .in_c(matrixC22_3), .out_a(out_a_23_3_NC), .out_a_chain(a23_3to23_4), .out_b(b23_3to24_3), .out_b0(b23_3to24_3_ping), .out_b1(b23_3to24_3_pong), .out_c(matrixC23_3), .b_data_valid_ping(b_data_valid_ping_delay23_3), .b_data_valid_pong(b_data_valid_pong_delay23_3), .mode(1'b0)); +processing_element pe23_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_23_4_NC), .in_a_chain(a23_3to23_4), .in_b(b22_4to23_4), .in_c(matrixC22_4), .out_a(out_a_23_4_NC), .out_a_chain(a23_4to23_5), .out_b(b23_4to24_4), .out_b0(b23_4to24_4_ping), .out_b1(b23_4to24_4_pong), .out_c(matrixC23_4), .b_data_valid_ping(b_data_valid_ping_delay23_4), .b_data_valid_pong(b_data_valid_pong_delay23_4), .mode(1'b0)); +processing_element pe23_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_23_5_NC), .in_a_chain(a23_4to23_5), .in_b(b22_5to23_5), .in_c(matrixC22_5), .out_a(out_a_23_5_NC), .out_a_chain(a23_5to23_6), .out_b(b23_5to24_5), .out_b0(b23_5to24_5_ping), .out_b1(b23_5to24_5_pong), .out_c(matrixC23_5), .b_data_valid_ping(b_data_valid_ping_delay23_5), .b_data_valid_pong(b_data_valid_pong_delay23_5), .mode(1'b0)); +processing_element pe23_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_23_6_NC), .in_a_chain(a23_5to23_6), .in_b(b22_6to23_6), .in_c(matrixC22_6), .out_a(out_a_23_6_NC), .out_a_chain(a23_6to23_7), .out_b(b23_6to24_6), .out_b0(b23_6to24_6_ping), .out_b1(b23_6to24_6_pong), .out_c(matrixC23_6), .b_data_valid_ping(b_data_valid_ping_delay23_6), .b_data_valid_pong(b_data_valid_pong_delay23_6), .mode(1'b0)); +processing_element pe23_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_23_7_NC), .in_a_chain(a23_6to23_7), .in_b(b22_7to23_7), .in_c(matrixC22_7), .out_a(out_a_23_7_NC), .out_a_chain(a23_7to23_8), .out_b(b23_7to24_7), .out_b0(b23_7to24_7_ping), .out_b1(b23_7to24_7_pong), .out_c(matrixC23_7), .b_data_valid_ping(b_data_valid_ping_delay23_7), .b_data_valid_pong(b_data_valid_pong_delay23_7), .mode(1'b0)); +processing_element pe23_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_23_8_NC), .in_a_chain(a23_7to23_8), .in_b(b22_8to23_8), .in_c(matrixC22_8), .out_a(out_a_23_8_NC), .out_a_chain(a23_8to23_9), .out_b(b23_8to24_8), .out_b0(b23_8to24_8_ping), .out_b1(b23_8to24_8_pong), .out_c(matrixC23_8), .b_data_valid_ping(b_data_valid_ping_delay23_8), .b_data_valid_pong(b_data_valid_pong_delay23_8), .mode(1'b0)); +processing_element pe23_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_23_9_NC), .in_a_chain(a23_8to23_9), .in_b(b22_9to23_9), .in_c(matrixC22_9), .out_a(out_a_23_9_NC), .out_a_chain(a23_9to23_10), .out_b(b23_9to24_9), .out_b0(b23_9to24_9_ping), .out_b1(b23_9to24_9_pong), .out_c(matrixC23_9), .b_data_valid_ping(b_data_valid_ping_delay23_9), .b_data_valid_pong(b_data_valid_pong_delay23_9), .mode(1'b0)); +processing_element pe23_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_23_10_NC), .in_a_chain(a23_9to23_10), .in_b(b22_10to23_10), .in_c(matrixC22_10), .out_a(out_a_23_10_NC), .out_a_chain(a23_10to23_11), .out_b(b23_10to24_10), .out_b0(b23_10to24_10_ping), .out_b1(b23_10to24_10_pong), .out_c(matrixC23_10), .b_data_valid_ping(b_data_valid_ping_delay23_10), .b_data_valid_pong(b_data_valid_pong_delay23_10), .mode(1'b0)); +processing_element pe23_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_23_11_NC), .in_a_chain(a23_10to23_11), .in_b(b22_11to23_11), .in_c(matrixC22_11), .out_a(out_a_23_11_NC), .out_a_chain(a23_11to23_12), .out_b(b23_11to24_11), .out_b0(b23_11to24_11_ping), .out_b1(b23_11to24_11_pong), .out_c(matrixC23_11), .b_data_valid_ping(b_data_valid_ping_delay23_11), .b_data_valid_pong(b_data_valid_pong_delay23_11), .mode(1'b0)); +processing_element pe23_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_23_12_NC), .in_a_chain(a23_11to23_12), .in_b(b22_12to23_12), .in_c(matrixC22_12), .out_a(out_a_23_12_NC), .out_a_chain(a23_12to23_13), .out_b(b23_12to24_12), .out_b0(b23_12to24_12_ping), .out_b1(b23_12to24_12_pong), .out_c(matrixC23_12), .b_data_valid_ping(b_data_valid_ping_delay23_12), .b_data_valid_pong(b_data_valid_pong_delay23_12), .mode(1'b0)); +processing_element pe23_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_23_13_NC), .in_a_chain(a23_12to23_13), .in_b(b22_13to23_13), .in_c(matrixC22_13), .out_a(out_a_23_13_NC), .out_a_chain(a23_13to23_14), .out_b(b23_13to24_13), .out_b0(b23_13to24_13_ping), .out_b1(b23_13to24_13_pong), .out_c(matrixC23_13), .b_data_valid_ping(b_data_valid_ping_delay23_13), .b_data_valid_pong(b_data_valid_pong_delay23_13), .mode(1'b0)); +processing_element pe23_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_23_14_NC), .in_a_chain(a23_13to23_14), .in_b(b22_14to23_14), .in_c(matrixC22_14), .out_a(out_a_23_14_NC), .out_a_chain(a23_14to23_15), .out_b(b23_14to24_14), .out_b0(b23_14to24_14_ping), .out_b1(b23_14to24_14_pong), .out_c(matrixC23_14), .b_data_valid_ping(b_data_valid_ping_delay23_14), .b_data_valid_pong(b_data_valid_pong_delay23_14), .mode(1'b0)); +processing_element pe23_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_23_15_NC), .in_a_chain(a23_14to23_15), .in_b(b22_15to23_15), .in_c(matrixC22_15), .out_a(out_a_23_15_NC), .out_a_chain(a23_15to23_16), .out_b(b23_15to24_15), .out_b0(b23_15to24_15_ping), .out_b1(b23_15to24_15_pong), .out_c(matrixC23_15), .b_data_valid_ping(b_data_valid_ping_delay23_15), .b_data_valid_pong(b_data_valid_pong_delay23_15), .mode(1'b0)); +processing_element pe23_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_23_16_NC), .in_a_chain(a23_15to23_16), .in_b(b22_16to23_16), .in_c(matrixC22_16), .out_a(out_a_23_16_NC), .out_a_chain(a23_16to23_17), .out_b(b23_16to24_16), .out_b0(b23_16to24_16_ping), .out_b1(b23_16to24_16_pong), .out_c(matrixC23_16), .b_data_valid_ping(b_data_valid_ping_delay23_16), .b_data_valid_pong(b_data_valid_pong_delay23_16), .mode(1'b0)); +processing_element pe23_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_23_17_NC), .in_a_chain(a23_16to23_17), .in_b(b22_17to23_17), .in_c(matrixC22_17), .out_a(out_a_23_17_NC), .out_a_chain(a23_17to23_18), .out_b(b23_17to24_17), .out_b0(b23_17to24_17_ping), .out_b1(b23_17to24_17_pong), .out_c(matrixC23_17), .b_data_valid_ping(b_data_valid_ping_delay23_17), .b_data_valid_pong(b_data_valid_pong_delay23_17), .mode(1'b0)); +processing_element pe23_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_23_18_NC), .in_a_chain(a23_17to23_18), .in_b(b22_18to23_18), .in_c(matrixC22_18), .out_a(out_a_23_18_NC), .out_a_chain(a23_18to23_19), .out_b(b23_18to24_18), .out_b0(b23_18to24_18_ping), .out_b1(b23_18to24_18_pong), .out_c(matrixC23_18), .b_data_valid_ping(b_data_valid_ping_delay23_18), .b_data_valid_pong(b_data_valid_pong_delay23_18), .mode(1'b0)); +processing_element pe23_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_23_19_NC), .in_a_chain(a23_18to23_19), .in_b(b22_19to23_19), .in_c(matrixC22_19), .out_a(out_a_23_19_NC), .out_a_chain(a23_19to23_20), .out_b(b23_19to24_19), .out_b0(b23_19to24_19_ping), .out_b1(b23_19to24_19_pong), .out_c(matrixC23_19), .b_data_valid_ping(b_data_valid_ping_delay23_19), .b_data_valid_pong(b_data_valid_pong_delay23_19), .mode(1'b0)); +processing_element pe23_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_23_20_NC), .in_a_chain(a23_19to23_20), .in_b(b22_20to23_20), .in_c(matrixC22_20), .out_a(out_a_23_20_NC), .out_a_chain(a23_20to23_21), .out_b(b23_20to24_20), .out_b0(b23_20to24_20_ping), .out_b1(b23_20to24_20_pong), .out_c(matrixC23_20), .b_data_valid_ping(b_data_valid_ping_delay23_20), .b_data_valid_pong(b_data_valid_pong_delay23_20), .mode(1'b0)); +processing_element pe23_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_23_21_NC), .in_a_chain(a23_20to23_21), .in_b(b22_21to23_21), .in_c(matrixC22_21), .out_a(out_a_23_21_NC), .out_a_chain(a23_21to23_22), .out_b(b23_21to24_21), .out_b0(b23_21to24_21_ping), .out_b1(b23_21to24_21_pong), .out_c(matrixC23_21), .b_data_valid_ping(b_data_valid_ping_delay23_21), .b_data_valid_pong(b_data_valid_pong_delay23_21), .mode(1'b0)); +processing_element pe23_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_23_22_NC), .in_a_chain(a23_21to23_22), .in_b(b22_22to23_22), .in_c(matrixC22_22), .out_a(out_a_23_22_NC), .out_a_chain(a23_22to23_23), .out_b(b23_22to24_22), .out_b0(b23_22to24_22_ping), .out_b1(b23_22to24_22_pong), .out_c(matrixC23_22), .b_data_valid_ping(b_data_valid_ping_delay23_22), .b_data_valid_pong(b_data_valid_pong_delay23_22), .mode(1'b0)); +processing_element pe23_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_23_23_NC), .in_a_chain(a23_22to23_23), .in_b(b22_23to23_23), .in_c(matrixC22_23), .out_a(out_a_23_23_NC), .out_a_chain(a23_23to23_24), .out_b(b23_23to24_23), .out_b0(b23_23to24_23_ping), .out_b1(b23_23to24_23_pong), .out_c(matrixC23_23), .b_data_valid_ping(b_data_valid_ping_delay23_23), .b_data_valid_pong(b_data_valid_pong_delay23_23), .mode(1'b0)); +processing_element pe23_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_23_24_NC), .in_a_chain(a23_23to23_24), .in_b(b22_24to23_24), .in_c(matrixC22_24), .out_a(out_a_23_24_NC), .out_a_chain(a23_24to23_25), .out_b(b23_24to24_24), .out_b0(b23_24to24_24_ping), .out_b1(b23_24to24_24_pong), .out_c(matrixC23_24), .b_data_valid_ping(b_data_valid_ping_delay23_24), .b_data_valid_pong(b_data_valid_pong_delay23_24), .mode(1'b0)); +processing_element pe23_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay48), .in_a(in_a_23_25_NC), .in_a_chain(a23_24to23_25), .in_b(b22_25to23_25), .in_c(matrixC22_25), .out_a(out_a_23_25_NC), .out_a_chain(a23_25to23_26), .out_b(b23_25to24_25), .out_b0(b23_25to24_25_ping), .out_b1(b23_25to24_25_pong), .out_c(matrixC23_25), .b_data_valid_ping(b_data_valid_ping_delay23_25), .b_data_valid_pong(b_data_valid_pong_delay23_25), .mode(1'b0)); +processing_element pe23_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay49), .in_a(in_a_23_26_NC), .in_a_chain(a23_25to23_26), .in_b(b22_26to23_26), .in_c(matrixC22_26), .out_a(out_a_23_26_NC), .out_a_chain(a23_26to23_27), .out_b(b23_26to24_26), .out_b0(b23_26to24_26_ping), .out_b1(b23_26to24_26_pong), .out_c(matrixC23_26), .b_data_valid_ping(b_data_valid_ping_delay23_26), .b_data_valid_pong(b_data_valid_pong_delay23_26), .mode(1'b0)); +processing_element pe23_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay50), .in_a(in_a_23_27_NC), .in_a_chain(a23_26to23_27), .in_b(b22_27to23_27), .in_c(matrixC22_27), .out_a(out_a_23_27_NC), .out_a_chain(a23_27to23_28), .out_b(b23_27to24_27), .out_b0(b23_27to24_27_ping), .out_b1(b23_27to24_27_pong), .out_c(matrixC23_27), .b_data_valid_ping(b_data_valid_ping_delay23_27), .b_data_valid_pong(b_data_valid_pong_delay23_27), .mode(1'b0)); +processing_element pe23_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay51), .in_a(in_a_23_28_NC), .in_a_chain(a23_27to23_28), .in_b(b22_28to23_28), .in_c(matrixC22_28), .out_a(out_a_23_28_NC), .out_a_chain(a23_28to23_29), .out_b(b23_28to24_28), .out_b0(b23_28to24_28_ping), .out_b1(b23_28to24_28_pong), .out_c(matrixC23_28), .b_data_valid_ping(b_data_valid_ping_delay23_28), .b_data_valid_pong(b_data_valid_pong_delay23_28), .mode(1'b0)); +processing_element pe23_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay52), .in_a(in_a_23_29_NC), .in_a_chain(a23_28to23_29), .in_b(b22_29to23_29), .in_c(matrixC22_29), .out_a(out_a_23_29_NC), .out_a_chain(a23_29to23_30), .out_b(b23_29to24_29), .out_b0(b23_29to24_29_ping), .out_b1(b23_29to24_29_pong), .out_c(matrixC23_29), .b_data_valid_ping(b_data_valid_ping_delay23_29), .b_data_valid_pong(b_data_valid_pong_delay23_29), .mode(1'b0)); +processing_element pe23_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay53), .in_a(in_a_23_30_NC), .in_a_chain(a23_29to23_30), .in_b(b22_30to23_30), .in_c(matrixC22_30), .out_a(out_a_23_30_NC), .out_a_chain(a23_30to23_31), .out_b(b23_30to24_30), .out_b0(b23_30to24_30_ping), .out_b1(b23_30to24_30_pong), .out_c(matrixC23_30), .b_data_valid_ping(b_data_valid_ping_delay23_30), .b_data_valid_pong(b_data_valid_pong_delay23_30), .mode(1'b0)); +processing_element pe23_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay54), .in_a(in_a_23_31_NC), .in_a_chain(a23_30to23_31), .in_b(b22_31to23_31), .in_c(matrixC22_31), .out_a(out_a_23_31_NC), .out_a_chain(a23_31to23_32), .out_b(b23_31to24_31), .out_b0(b23_31to24_31_ping), .out_b1(b23_31to24_31_pong), .out_c(matrixC23_31), .b_data_valid_ping(b_data_valid_ping_delay23_31), .b_data_valid_pong(b_data_valid_pong_delay23_31), .mode(1'b0)); +processing_element pe24_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(a24), .in_a_chain(in_a_chain_24_0_NC), .in_b(b23_0to24_0), .in_c(matrixC23_0), .out_a(out_a_24_0_NC), .out_a_chain(a24_0to24_1), .out_b(b24_0to25_0), .out_b0(b24_0to25_0_ping), .out_b1(b24_0to25_0_pong), .out_c(matrixC24_0), .b_data_valid_ping(b_data_valid_ping_delay24_0), .b_data_valid_pong(b_data_valid_pong_delay24_0), .mode(1'b1)); +processing_element pe24_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_24_1_NC), .in_a_chain(a24_0to24_1), .in_b(b23_1to24_1), .in_c(matrixC23_1), .out_a(out_a_24_1_NC), .out_a_chain(a24_1to24_2), .out_b(b24_1to25_1), .out_b0(b24_1to25_1_ping), .out_b1(b24_1to25_1_pong), .out_c(matrixC24_1), .b_data_valid_ping(b_data_valid_ping_delay24_1), .b_data_valid_pong(b_data_valid_pong_delay24_1), .mode(1'b0)); +processing_element pe24_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_24_2_NC), .in_a_chain(a24_1to24_2), .in_b(b23_2to24_2), .in_c(matrixC23_2), .out_a(out_a_24_2_NC), .out_a_chain(a24_2to24_3), .out_b(b24_2to25_2), .out_b0(b24_2to25_2_ping), .out_b1(b24_2to25_2_pong), .out_c(matrixC24_2), .b_data_valid_ping(b_data_valid_ping_delay24_2), .b_data_valid_pong(b_data_valid_pong_delay24_2), .mode(1'b0)); +processing_element pe24_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_24_3_NC), .in_a_chain(a24_2to24_3), .in_b(b23_3to24_3), .in_c(matrixC23_3), .out_a(out_a_24_3_NC), .out_a_chain(a24_3to24_4), .out_b(b24_3to25_3), .out_b0(b24_3to25_3_ping), .out_b1(b24_3to25_3_pong), .out_c(matrixC24_3), .b_data_valid_ping(b_data_valid_ping_delay24_3), .b_data_valid_pong(b_data_valid_pong_delay24_3), .mode(1'b0)); +processing_element pe24_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_24_4_NC), .in_a_chain(a24_3to24_4), .in_b(b23_4to24_4), .in_c(matrixC23_4), .out_a(out_a_24_4_NC), .out_a_chain(a24_4to24_5), .out_b(b24_4to25_4), .out_b0(b24_4to25_4_ping), .out_b1(b24_4to25_4_pong), .out_c(matrixC24_4), .b_data_valid_ping(b_data_valid_ping_delay24_4), .b_data_valid_pong(b_data_valid_pong_delay24_4), .mode(1'b0)); +processing_element pe24_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_24_5_NC), .in_a_chain(a24_4to24_5), .in_b(b23_5to24_5), .in_c(matrixC23_5), .out_a(out_a_24_5_NC), .out_a_chain(a24_5to24_6), .out_b(b24_5to25_5), .out_b0(b24_5to25_5_ping), .out_b1(b24_5to25_5_pong), .out_c(matrixC24_5), .b_data_valid_ping(b_data_valid_ping_delay24_5), .b_data_valid_pong(b_data_valid_pong_delay24_5), .mode(1'b0)); +processing_element pe24_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_24_6_NC), .in_a_chain(a24_5to24_6), .in_b(b23_6to24_6), .in_c(matrixC23_6), .out_a(out_a_24_6_NC), .out_a_chain(a24_6to24_7), .out_b(b24_6to25_6), .out_b0(b24_6to25_6_ping), .out_b1(b24_6to25_6_pong), .out_c(matrixC24_6), .b_data_valid_ping(b_data_valid_ping_delay24_6), .b_data_valid_pong(b_data_valid_pong_delay24_6), .mode(1'b0)); +processing_element pe24_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_24_7_NC), .in_a_chain(a24_6to24_7), .in_b(b23_7to24_7), .in_c(matrixC23_7), .out_a(out_a_24_7_NC), .out_a_chain(a24_7to24_8), .out_b(b24_7to25_7), .out_b0(b24_7to25_7_ping), .out_b1(b24_7to25_7_pong), .out_c(matrixC24_7), .b_data_valid_ping(b_data_valid_ping_delay24_7), .b_data_valid_pong(b_data_valid_pong_delay24_7), .mode(1'b0)); +processing_element pe24_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_24_8_NC), .in_a_chain(a24_7to24_8), .in_b(b23_8to24_8), .in_c(matrixC23_8), .out_a(out_a_24_8_NC), .out_a_chain(a24_8to24_9), .out_b(b24_8to25_8), .out_b0(b24_8to25_8_ping), .out_b1(b24_8to25_8_pong), .out_c(matrixC24_8), .b_data_valid_ping(b_data_valid_ping_delay24_8), .b_data_valid_pong(b_data_valid_pong_delay24_8), .mode(1'b0)); +processing_element pe24_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_24_9_NC), .in_a_chain(a24_8to24_9), .in_b(b23_9to24_9), .in_c(matrixC23_9), .out_a(out_a_24_9_NC), .out_a_chain(a24_9to24_10), .out_b(b24_9to25_9), .out_b0(b24_9to25_9_ping), .out_b1(b24_9to25_9_pong), .out_c(matrixC24_9), .b_data_valid_ping(b_data_valid_ping_delay24_9), .b_data_valid_pong(b_data_valid_pong_delay24_9), .mode(1'b0)); +processing_element pe24_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_24_10_NC), .in_a_chain(a24_9to24_10), .in_b(b23_10to24_10), .in_c(matrixC23_10), .out_a(out_a_24_10_NC), .out_a_chain(a24_10to24_11), .out_b(b24_10to25_10), .out_b0(b24_10to25_10_ping), .out_b1(b24_10to25_10_pong), .out_c(matrixC24_10), .b_data_valid_ping(b_data_valid_ping_delay24_10), .b_data_valid_pong(b_data_valid_pong_delay24_10), .mode(1'b0)); +processing_element pe24_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_24_11_NC), .in_a_chain(a24_10to24_11), .in_b(b23_11to24_11), .in_c(matrixC23_11), .out_a(out_a_24_11_NC), .out_a_chain(a24_11to24_12), .out_b(b24_11to25_11), .out_b0(b24_11to25_11_ping), .out_b1(b24_11to25_11_pong), .out_c(matrixC24_11), .b_data_valid_ping(b_data_valid_ping_delay24_11), .b_data_valid_pong(b_data_valid_pong_delay24_11), .mode(1'b0)); +processing_element pe24_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_24_12_NC), .in_a_chain(a24_11to24_12), .in_b(b23_12to24_12), .in_c(matrixC23_12), .out_a(out_a_24_12_NC), .out_a_chain(a24_12to24_13), .out_b(b24_12to25_12), .out_b0(b24_12to25_12_ping), .out_b1(b24_12to25_12_pong), .out_c(matrixC24_12), .b_data_valid_ping(b_data_valid_ping_delay24_12), .b_data_valid_pong(b_data_valid_pong_delay24_12), .mode(1'b0)); +processing_element pe24_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_24_13_NC), .in_a_chain(a24_12to24_13), .in_b(b23_13to24_13), .in_c(matrixC23_13), .out_a(out_a_24_13_NC), .out_a_chain(a24_13to24_14), .out_b(b24_13to25_13), .out_b0(b24_13to25_13_ping), .out_b1(b24_13to25_13_pong), .out_c(matrixC24_13), .b_data_valid_ping(b_data_valid_ping_delay24_13), .b_data_valid_pong(b_data_valid_pong_delay24_13), .mode(1'b0)); +processing_element pe24_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_24_14_NC), .in_a_chain(a24_13to24_14), .in_b(b23_14to24_14), .in_c(matrixC23_14), .out_a(out_a_24_14_NC), .out_a_chain(a24_14to24_15), .out_b(b24_14to25_14), .out_b0(b24_14to25_14_ping), .out_b1(b24_14to25_14_pong), .out_c(matrixC24_14), .b_data_valid_ping(b_data_valid_ping_delay24_14), .b_data_valid_pong(b_data_valid_pong_delay24_14), .mode(1'b0)); +processing_element pe24_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_24_15_NC), .in_a_chain(a24_14to24_15), .in_b(b23_15to24_15), .in_c(matrixC23_15), .out_a(out_a_24_15_NC), .out_a_chain(a24_15to24_16), .out_b(b24_15to25_15), .out_b0(b24_15to25_15_ping), .out_b1(b24_15to25_15_pong), .out_c(matrixC24_15), .b_data_valid_ping(b_data_valid_ping_delay24_15), .b_data_valid_pong(b_data_valid_pong_delay24_15), .mode(1'b0)); +processing_element pe24_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_24_16_NC), .in_a_chain(a24_15to24_16), .in_b(b23_16to24_16), .in_c(matrixC23_16), .out_a(out_a_24_16_NC), .out_a_chain(a24_16to24_17), .out_b(b24_16to25_16), .out_b0(b24_16to25_16_ping), .out_b1(b24_16to25_16_pong), .out_c(matrixC24_16), .b_data_valid_ping(b_data_valid_ping_delay24_16), .b_data_valid_pong(b_data_valid_pong_delay24_16), .mode(1'b0)); +processing_element pe24_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_24_17_NC), .in_a_chain(a24_16to24_17), .in_b(b23_17to24_17), .in_c(matrixC23_17), .out_a(out_a_24_17_NC), .out_a_chain(a24_17to24_18), .out_b(b24_17to25_17), .out_b0(b24_17to25_17_ping), .out_b1(b24_17to25_17_pong), .out_c(matrixC24_17), .b_data_valid_ping(b_data_valid_ping_delay24_17), .b_data_valid_pong(b_data_valid_pong_delay24_17), .mode(1'b0)); +processing_element pe24_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_24_18_NC), .in_a_chain(a24_17to24_18), .in_b(b23_18to24_18), .in_c(matrixC23_18), .out_a(out_a_24_18_NC), .out_a_chain(a24_18to24_19), .out_b(b24_18to25_18), .out_b0(b24_18to25_18_ping), .out_b1(b24_18to25_18_pong), .out_c(matrixC24_18), .b_data_valid_ping(b_data_valid_ping_delay24_18), .b_data_valid_pong(b_data_valid_pong_delay24_18), .mode(1'b0)); +processing_element pe24_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_24_19_NC), .in_a_chain(a24_18to24_19), .in_b(b23_19to24_19), .in_c(matrixC23_19), .out_a(out_a_24_19_NC), .out_a_chain(a24_19to24_20), .out_b(b24_19to25_19), .out_b0(b24_19to25_19_ping), .out_b1(b24_19to25_19_pong), .out_c(matrixC24_19), .b_data_valid_ping(b_data_valid_ping_delay24_19), .b_data_valid_pong(b_data_valid_pong_delay24_19), .mode(1'b0)); +processing_element pe24_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_24_20_NC), .in_a_chain(a24_19to24_20), .in_b(b23_20to24_20), .in_c(matrixC23_20), .out_a(out_a_24_20_NC), .out_a_chain(a24_20to24_21), .out_b(b24_20to25_20), .out_b0(b24_20to25_20_ping), .out_b1(b24_20to25_20_pong), .out_c(matrixC24_20), .b_data_valid_ping(b_data_valid_ping_delay24_20), .b_data_valid_pong(b_data_valid_pong_delay24_20), .mode(1'b0)); +processing_element pe24_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_24_21_NC), .in_a_chain(a24_20to24_21), .in_b(b23_21to24_21), .in_c(matrixC23_21), .out_a(out_a_24_21_NC), .out_a_chain(a24_21to24_22), .out_b(b24_21to25_21), .out_b0(b24_21to25_21_ping), .out_b1(b24_21to25_21_pong), .out_c(matrixC24_21), .b_data_valid_ping(b_data_valid_ping_delay24_21), .b_data_valid_pong(b_data_valid_pong_delay24_21), .mode(1'b0)); +processing_element pe24_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_24_22_NC), .in_a_chain(a24_21to24_22), .in_b(b23_22to24_22), .in_c(matrixC23_22), .out_a(out_a_24_22_NC), .out_a_chain(a24_22to24_23), .out_b(b24_22to25_22), .out_b0(b24_22to25_22_ping), .out_b1(b24_22to25_22_pong), .out_c(matrixC24_22), .b_data_valid_ping(b_data_valid_ping_delay24_22), .b_data_valid_pong(b_data_valid_pong_delay24_22), .mode(1'b0)); +processing_element pe24_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_24_23_NC), .in_a_chain(a24_22to24_23), .in_b(b23_23to24_23), .in_c(matrixC23_23), .out_a(out_a_24_23_NC), .out_a_chain(a24_23to24_24), .out_b(b24_23to25_23), .out_b0(b24_23to25_23_ping), .out_b1(b24_23to25_23_pong), .out_c(matrixC24_23), .b_data_valid_ping(b_data_valid_ping_delay24_23), .b_data_valid_pong(b_data_valid_pong_delay24_23), .mode(1'b0)); +processing_element pe24_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay48), .in_a(in_a_24_24_NC), .in_a_chain(a24_23to24_24), .in_b(b23_24to24_24), .in_c(matrixC23_24), .out_a(out_a_24_24_NC), .out_a_chain(a24_24to24_25), .out_b(b24_24to25_24), .out_b0(b24_24to25_24_ping), .out_b1(b24_24to25_24_pong), .out_c(matrixC24_24), .b_data_valid_ping(b_data_valid_ping_delay24_24), .b_data_valid_pong(b_data_valid_pong_delay24_24), .mode(1'b0)); +processing_element pe24_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay49), .in_a(in_a_24_25_NC), .in_a_chain(a24_24to24_25), .in_b(b23_25to24_25), .in_c(matrixC23_25), .out_a(out_a_24_25_NC), .out_a_chain(a24_25to24_26), .out_b(b24_25to25_25), .out_b0(b24_25to25_25_ping), .out_b1(b24_25to25_25_pong), .out_c(matrixC24_25), .b_data_valid_ping(b_data_valid_ping_delay24_25), .b_data_valid_pong(b_data_valid_pong_delay24_25), .mode(1'b0)); +processing_element pe24_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay50), .in_a(in_a_24_26_NC), .in_a_chain(a24_25to24_26), .in_b(b23_26to24_26), .in_c(matrixC23_26), .out_a(out_a_24_26_NC), .out_a_chain(a24_26to24_27), .out_b(b24_26to25_26), .out_b0(b24_26to25_26_ping), .out_b1(b24_26to25_26_pong), .out_c(matrixC24_26), .b_data_valid_ping(b_data_valid_ping_delay24_26), .b_data_valid_pong(b_data_valid_pong_delay24_26), .mode(1'b0)); +processing_element pe24_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay51), .in_a(in_a_24_27_NC), .in_a_chain(a24_26to24_27), .in_b(b23_27to24_27), .in_c(matrixC23_27), .out_a(out_a_24_27_NC), .out_a_chain(a24_27to24_28), .out_b(b24_27to25_27), .out_b0(b24_27to25_27_ping), .out_b1(b24_27to25_27_pong), .out_c(matrixC24_27), .b_data_valid_ping(b_data_valid_ping_delay24_27), .b_data_valid_pong(b_data_valid_pong_delay24_27), .mode(1'b0)); +processing_element pe24_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay52), .in_a(in_a_24_28_NC), .in_a_chain(a24_27to24_28), .in_b(b23_28to24_28), .in_c(matrixC23_28), .out_a(out_a_24_28_NC), .out_a_chain(a24_28to24_29), .out_b(b24_28to25_28), .out_b0(b24_28to25_28_ping), .out_b1(b24_28to25_28_pong), .out_c(matrixC24_28), .b_data_valid_ping(b_data_valid_ping_delay24_28), .b_data_valid_pong(b_data_valid_pong_delay24_28), .mode(1'b0)); +processing_element pe24_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay53), .in_a(in_a_24_29_NC), .in_a_chain(a24_28to24_29), .in_b(b23_29to24_29), .in_c(matrixC23_29), .out_a(out_a_24_29_NC), .out_a_chain(a24_29to24_30), .out_b(b24_29to25_29), .out_b0(b24_29to25_29_ping), .out_b1(b24_29to25_29_pong), .out_c(matrixC24_29), .b_data_valid_ping(b_data_valid_ping_delay24_29), .b_data_valid_pong(b_data_valid_pong_delay24_29), .mode(1'b0)); +processing_element pe24_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay54), .in_a(in_a_24_30_NC), .in_a_chain(a24_29to24_30), .in_b(b23_30to24_30), .in_c(matrixC23_30), .out_a(out_a_24_30_NC), .out_a_chain(a24_30to24_31), .out_b(b24_30to25_30), .out_b0(b24_30to25_30_ping), .out_b1(b24_30to25_30_pong), .out_c(matrixC24_30), .b_data_valid_ping(b_data_valid_ping_delay24_30), .b_data_valid_pong(b_data_valid_pong_delay24_30), .mode(1'b0)); +processing_element pe24_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay55), .in_a(in_a_24_31_NC), .in_a_chain(a24_30to24_31), .in_b(b23_31to24_31), .in_c(matrixC23_31), .out_a(out_a_24_31_NC), .out_a_chain(a24_31to24_32), .out_b(b24_31to25_31), .out_b0(b24_31to25_31_ping), .out_b1(b24_31to25_31_pong), .out_c(matrixC24_31), .b_data_valid_ping(b_data_valid_ping_delay24_31), .b_data_valid_pong(b_data_valid_pong_delay24_31), .mode(1'b0)); +processing_element pe25_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(a25), .in_a_chain(in_a_chain_25_0_NC), .in_b(b24_0to25_0), .in_c(matrixC24_0), .out_a(out_a_25_0_NC), .out_a_chain(a25_0to25_1), .out_b(b25_0to26_0), .out_b0(b25_0to26_0_ping), .out_b1(b25_0to26_0_pong), .out_c(matrixC25_0), .b_data_valid_ping(b_data_valid_ping_delay25_0), .b_data_valid_pong(b_data_valid_pong_delay25_0), .mode(1'b1)); +processing_element pe25_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_25_1_NC), .in_a_chain(a25_0to25_1), .in_b(b24_1to25_1), .in_c(matrixC24_1), .out_a(out_a_25_1_NC), .out_a_chain(a25_1to25_2), .out_b(b25_1to26_1), .out_b0(b25_1to26_1_ping), .out_b1(b25_1to26_1_pong), .out_c(matrixC25_1), .b_data_valid_ping(b_data_valid_ping_delay25_1), .b_data_valid_pong(b_data_valid_pong_delay25_1), .mode(1'b0)); +processing_element pe25_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_25_2_NC), .in_a_chain(a25_1to25_2), .in_b(b24_2to25_2), .in_c(matrixC24_2), .out_a(out_a_25_2_NC), .out_a_chain(a25_2to25_3), .out_b(b25_2to26_2), .out_b0(b25_2to26_2_ping), .out_b1(b25_2to26_2_pong), .out_c(matrixC25_2), .b_data_valid_ping(b_data_valid_ping_delay25_2), .b_data_valid_pong(b_data_valid_pong_delay25_2), .mode(1'b0)); +processing_element pe25_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_25_3_NC), .in_a_chain(a25_2to25_3), .in_b(b24_3to25_3), .in_c(matrixC24_3), .out_a(out_a_25_3_NC), .out_a_chain(a25_3to25_4), .out_b(b25_3to26_3), .out_b0(b25_3to26_3_ping), .out_b1(b25_3to26_3_pong), .out_c(matrixC25_3), .b_data_valid_ping(b_data_valid_ping_delay25_3), .b_data_valid_pong(b_data_valid_pong_delay25_3), .mode(1'b0)); +processing_element pe25_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_25_4_NC), .in_a_chain(a25_3to25_4), .in_b(b24_4to25_4), .in_c(matrixC24_4), .out_a(out_a_25_4_NC), .out_a_chain(a25_4to25_5), .out_b(b25_4to26_4), .out_b0(b25_4to26_4_ping), .out_b1(b25_4to26_4_pong), .out_c(matrixC25_4), .b_data_valid_ping(b_data_valid_ping_delay25_4), .b_data_valid_pong(b_data_valid_pong_delay25_4), .mode(1'b0)); +processing_element pe25_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_25_5_NC), .in_a_chain(a25_4to25_5), .in_b(b24_5to25_5), .in_c(matrixC24_5), .out_a(out_a_25_5_NC), .out_a_chain(a25_5to25_6), .out_b(b25_5to26_5), .out_b0(b25_5to26_5_ping), .out_b1(b25_5to26_5_pong), .out_c(matrixC25_5), .b_data_valid_ping(b_data_valid_ping_delay25_5), .b_data_valid_pong(b_data_valid_pong_delay25_5), .mode(1'b0)); +processing_element pe25_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_25_6_NC), .in_a_chain(a25_5to25_6), .in_b(b24_6to25_6), .in_c(matrixC24_6), .out_a(out_a_25_6_NC), .out_a_chain(a25_6to25_7), .out_b(b25_6to26_6), .out_b0(b25_6to26_6_ping), .out_b1(b25_6to26_6_pong), .out_c(matrixC25_6), .b_data_valid_ping(b_data_valid_ping_delay25_6), .b_data_valid_pong(b_data_valid_pong_delay25_6), .mode(1'b0)); +processing_element pe25_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_25_7_NC), .in_a_chain(a25_6to25_7), .in_b(b24_7to25_7), .in_c(matrixC24_7), .out_a(out_a_25_7_NC), .out_a_chain(a25_7to25_8), .out_b(b25_7to26_7), .out_b0(b25_7to26_7_ping), .out_b1(b25_7to26_7_pong), .out_c(matrixC25_7), .b_data_valid_ping(b_data_valid_ping_delay25_7), .b_data_valid_pong(b_data_valid_pong_delay25_7), .mode(1'b0)); +processing_element pe25_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_25_8_NC), .in_a_chain(a25_7to25_8), .in_b(b24_8to25_8), .in_c(matrixC24_8), .out_a(out_a_25_8_NC), .out_a_chain(a25_8to25_9), .out_b(b25_8to26_8), .out_b0(b25_8to26_8_ping), .out_b1(b25_8to26_8_pong), .out_c(matrixC25_8), .b_data_valid_ping(b_data_valid_ping_delay25_8), .b_data_valid_pong(b_data_valid_pong_delay25_8), .mode(1'b0)); +processing_element pe25_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_25_9_NC), .in_a_chain(a25_8to25_9), .in_b(b24_9to25_9), .in_c(matrixC24_9), .out_a(out_a_25_9_NC), .out_a_chain(a25_9to25_10), .out_b(b25_9to26_9), .out_b0(b25_9to26_9_ping), .out_b1(b25_9to26_9_pong), .out_c(matrixC25_9), .b_data_valid_ping(b_data_valid_ping_delay25_9), .b_data_valid_pong(b_data_valid_pong_delay25_9), .mode(1'b0)); +processing_element pe25_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_25_10_NC), .in_a_chain(a25_9to25_10), .in_b(b24_10to25_10), .in_c(matrixC24_10), .out_a(out_a_25_10_NC), .out_a_chain(a25_10to25_11), .out_b(b25_10to26_10), .out_b0(b25_10to26_10_ping), .out_b1(b25_10to26_10_pong), .out_c(matrixC25_10), .b_data_valid_ping(b_data_valid_ping_delay25_10), .b_data_valid_pong(b_data_valid_pong_delay25_10), .mode(1'b0)); +processing_element pe25_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_25_11_NC), .in_a_chain(a25_10to25_11), .in_b(b24_11to25_11), .in_c(matrixC24_11), .out_a(out_a_25_11_NC), .out_a_chain(a25_11to25_12), .out_b(b25_11to26_11), .out_b0(b25_11to26_11_ping), .out_b1(b25_11to26_11_pong), .out_c(matrixC25_11), .b_data_valid_ping(b_data_valid_ping_delay25_11), .b_data_valid_pong(b_data_valid_pong_delay25_11), .mode(1'b0)); +processing_element pe25_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_25_12_NC), .in_a_chain(a25_11to25_12), .in_b(b24_12to25_12), .in_c(matrixC24_12), .out_a(out_a_25_12_NC), .out_a_chain(a25_12to25_13), .out_b(b25_12to26_12), .out_b0(b25_12to26_12_ping), .out_b1(b25_12to26_12_pong), .out_c(matrixC25_12), .b_data_valid_ping(b_data_valid_ping_delay25_12), .b_data_valid_pong(b_data_valid_pong_delay25_12), .mode(1'b0)); +processing_element pe25_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_25_13_NC), .in_a_chain(a25_12to25_13), .in_b(b24_13to25_13), .in_c(matrixC24_13), .out_a(out_a_25_13_NC), .out_a_chain(a25_13to25_14), .out_b(b25_13to26_13), .out_b0(b25_13to26_13_ping), .out_b1(b25_13to26_13_pong), .out_c(matrixC25_13), .b_data_valid_ping(b_data_valid_ping_delay25_13), .b_data_valid_pong(b_data_valid_pong_delay25_13), .mode(1'b0)); +processing_element pe25_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_25_14_NC), .in_a_chain(a25_13to25_14), .in_b(b24_14to25_14), .in_c(matrixC24_14), .out_a(out_a_25_14_NC), .out_a_chain(a25_14to25_15), .out_b(b25_14to26_14), .out_b0(b25_14to26_14_ping), .out_b1(b25_14to26_14_pong), .out_c(matrixC25_14), .b_data_valid_ping(b_data_valid_ping_delay25_14), .b_data_valid_pong(b_data_valid_pong_delay25_14), .mode(1'b0)); +processing_element pe25_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_25_15_NC), .in_a_chain(a25_14to25_15), .in_b(b24_15to25_15), .in_c(matrixC24_15), .out_a(out_a_25_15_NC), .out_a_chain(a25_15to25_16), .out_b(b25_15to26_15), .out_b0(b25_15to26_15_ping), .out_b1(b25_15to26_15_pong), .out_c(matrixC25_15), .b_data_valid_ping(b_data_valid_ping_delay25_15), .b_data_valid_pong(b_data_valid_pong_delay25_15), .mode(1'b0)); +processing_element pe25_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_25_16_NC), .in_a_chain(a25_15to25_16), .in_b(b24_16to25_16), .in_c(matrixC24_16), .out_a(out_a_25_16_NC), .out_a_chain(a25_16to25_17), .out_b(b25_16to26_16), .out_b0(b25_16to26_16_ping), .out_b1(b25_16to26_16_pong), .out_c(matrixC25_16), .b_data_valid_ping(b_data_valid_ping_delay25_16), .b_data_valid_pong(b_data_valid_pong_delay25_16), .mode(1'b0)); +processing_element pe25_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_25_17_NC), .in_a_chain(a25_16to25_17), .in_b(b24_17to25_17), .in_c(matrixC24_17), .out_a(out_a_25_17_NC), .out_a_chain(a25_17to25_18), .out_b(b25_17to26_17), .out_b0(b25_17to26_17_ping), .out_b1(b25_17to26_17_pong), .out_c(matrixC25_17), .b_data_valid_ping(b_data_valid_ping_delay25_17), .b_data_valid_pong(b_data_valid_pong_delay25_17), .mode(1'b0)); +processing_element pe25_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_25_18_NC), .in_a_chain(a25_17to25_18), .in_b(b24_18to25_18), .in_c(matrixC24_18), .out_a(out_a_25_18_NC), .out_a_chain(a25_18to25_19), .out_b(b25_18to26_18), .out_b0(b25_18to26_18_ping), .out_b1(b25_18to26_18_pong), .out_c(matrixC25_18), .b_data_valid_ping(b_data_valid_ping_delay25_18), .b_data_valid_pong(b_data_valid_pong_delay25_18), .mode(1'b0)); +processing_element pe25_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_25_19_NC), .in_a_chain(a25_18to25_19), .in_b(b24_19to25_19), .in_c(matrixC24_19), .out_a(out_a_25_19_NC), .out_a_chain(a25_19to25_20), .out_b(b25_19to26_19), .out_b0(b25_19to26_19_ping), .out_b1(b25_19to26_19_pong), .out_c(matrixC25_19), .b_data_valid_ping(b_data_valid_ping_delay25_19), .b_data_valid_pong(b_data_valid_pong_delay25_19), .mode(1'b0)); +processing_element pe25_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_25_20_NC), .in_a_chain(a25_19to25_20), .in_b(b24_20to25_20), .in_c(matrixC24_20), .out_a(out_a_25_20_NC), .out_a_chain(a25_20to25_21), .out_b(b25_20to26_20), .out_b0(b25_20to26_20_ping), .out_b1(b25_20to26_20_pong), .out_c(matrixC25_20), .b_data_valid_ping(b_data_valid_ping_delay25_20), .b_data_valid_pong(b_data_valid_pong_delay25_20), .mode(1'b0)); +processing_element pe25_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_25_21_NC), .in_a_chain(a25_20to25_21), .in_b(b24_21to25_21), .in_c(matrixC24_21), .out_a(out_a_25_21_NC), .out_a_chain(a25_21to25_22), .out_b(b25_21to26_21), .out_b0(b25_21to26_21_ping), .out_b1(b25_21to26_21_pong), .out_c(matrixC25_21), .b_data_valid_ping(b_data_valid_ping_delay25_21), .b_data_valid_pong(b_data_valid_pong_delay25_21), .mode(1'b0)); +processing_element pe25_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_25_22_NC), .in_a_chain(a25_21to25_22), .in_b(b24_22to25_22), .in_c(matrixC24_22), .out_a(out_a_25_22_NC), .out_a_chain(a25_22to25_23), .out_b(b25_22to26_22), .out_b0(b25_22to26_22_ping), .out_b1(b25_22to26_22_pong), .out_c(matrixC25_22), .b_data_valid_ping(b_data_valid_ping_delay25_22), .b_data_valid_pong(b_data_valid_pong_delay25_22), .mode(1'b0)); +processing_element pe25_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay48), .in_a(in_a_25_23_NC), .in_a_chain(a25_22to25_23), .in_b(b24_23to25_23), .in_c(matrixC24_23), .out_a(out_a_25_23_NC), .out_a_chain(a25_23to25_24), .out_b(b25_23to26_23), .out_b0(b25_23to26_23_ping), .out_b1(b25_23to26_23_pong), .out_c(matrixC25_23), .b_data_valid_ping(b_data_valid_ping_delay25_23), .b_data_valid_pong(b_data_valid_pong_delay25_23), .mode(1'b0)); +processing_element pe25_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay49), .in_a(in_a_25_24_NC), .in_a_chain(a25_23to25_24), .in_b(b24_24to25_24), .in_c(matrixC24_24), .out_a(out_a_25_24_NC), .out_a_chain(a25_24to25_25), .out_b(b25_24to26_24), .out_b0(b25_24to26_24_ping), .out_b1(b25_24to26_24_pong), .out_c(matrixC25_24), .b_data_valid_ping(b_data_valid_ping_delay25_24), .b_data_valid_pong(b_data_valid_pong_delay25_24), .mode(1'b0)); +processing_element pe25_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay50), .in_a(in_a_25_25_NC), .in_a_chain(a25_24to25_25), .in_b(b24_25to25_25), .in_c(matrixC24_25), .out_a(out_a_25_25_NC), .out_a_chain(a25_25to25_26), .out_b(b25_25to26_25), .out_b0(b25_25to26_25_ping), .out_b1(b25_25to26_25_pong), .out_c(matrixC25_25), .b_data_valid_ping(b_data_valid_ping_delay25_25), .b_data_valid_pong(b_data_valid_pong_delay25_25), .mode(1'b0)); +processing_element pe25_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay51), .in_a(in_a_25_26_NC), .in_a_chain(a25_25to25_26), .in_b(b24_26to25_26), .in_c(matrixC24_26), .out_a(out_a_25_26_NC), .out_a_chain(a25_26to25_27), .out_b(b25_26to26_26), .out_b0(b25_26to26_26_ping), .out_b1(b25_26to26_26_pong), .out_c(matrixC25_26), .b_data_valid_ping(b_data_valid_ping_delay25_26), .b_data_valid_pong(b_data_valid_pong_delay25_26), .mode(1'b0)); +processing_element pe25_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay52), .in_a(in_a_25_27_NC), .in_a_chain(a25_26to25_27), .in_b(b24_27to25_27), .in_c(matrixC24_27), .out_a(out_a_25_27_NC), .out_a_chain(a25_27to25_28), .out_b(b25_27to26_27), .out_b0(b25_27to26_27_ping), .out_b1(b25_27to26_27_pong), .out_c(matrixC25_27), .b_data_valid_ping(b_data_valid_ping_delay25_27), .b_data_valid_pong(b_data_valid_pong_delay25_27), .mode(1'b0)); +processing_element pe25_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay53), .in_a(in_a_25_28_NC), .in_a_chain(a25_27to25_28), .in_b(b24_28to25_28), .in_c(matrixC24_28), .out_a(out_a_25_28_NC), .out_a_chain(a25_28to25_29), .out_b(b25_28to26_28), .out_b0(b25_28to26_28_ping), .out_b1(b25_28to26_28_pong), .out_c(matrixC25_28), .b_data_valid_ping(b_data_valid_ping_delay25_28), .b_data_valid_pong(b_data_valid_pong_delay25_28), .mode(1'b0)); +processing_element pe25_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay54), .in_a(in_a_25_29_NC), .in_a_chain(a25_28to25_29), .in_b(b24_29to25_29), .in_c(matrixC24_29), .out_a(out_a_25_29_NC), .out_a_chain(a25_29to25_30), .out_b(b25_29to26_29), .out_b0(b25_29to26_29_ping), .out_b1(b25_29to26_29_pong), .out_c(matrixC25_29), .b_data_valid_ping(b_data_valid_ping_delay25_29), .b_data_valid_pong(b_data_valid_pong_delay25_29), .mode(1'b0)); +processing_element pe25_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay55), .in_a(in_a_25_30_NC), .in_a_chain(a25_29to25_30), .in_b(b24_30to25_30), .in_c(matrixC24_30), .out_a(out_a_25_30_NC), .out_a_chain(a25_30to25_31), .out_b(b25_30to26_30), .out_b0(b25_30to26_30_ping), .out_b1(b25_30to26_30_pong), .out_c(matrixC25_30), .b_data_valid_ping(b_data_valid_ping_delay25_30), .b_data_valid_pong(b_data_valid_pong_delay25_30), .mode(1'b0)); +processing_element pe25_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay56), .in_a(in_a_25_31_NC), .in_a_chain(a25_30to25_31), .in_b(b24_31to25_31), .in_c(matrixC24_31), .out_a(out_a_25_31_NC), .out_a_chain(a25_31to25_32), .out_b(b25_31to26_31), .out_b0(b25_31to26_31_ping), .out_b1(b25_31to26_31_pong), .out_c(matrixC25_31), .b_data_valid_ping(b_data_valid_ping_delay25_31), .b_data_valid_pong(b_data_valid_pong_delay25_31), .mode(1'b0)); +processing_element pe26_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(a26), .in_a_chain(in_a_chain_26_0_NC), .in_b(b25_0to26_0), .in_c(matrixC25_0), .out_a(out_a_26_0_NC), .out_a_chain(a26_0to26_1), .out_b(b26_0to27_0), .out_b0(b26_0to27_0_ping), .out_b1(b26_0to27_0_pong), .out_c(matrixC26_0), .b_data_valid_ping(b_data_valid_ping_delay26_0), .b_data_valid_pong(b_data_valid_pong_delay26_0), .mode(1'b1)); +processing_element pe26_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_26_1_NC), .in_a_chain(a26_0to26_1), .in_b(b25_1to26_1), .in_c(matrixC25_1), .out_a(out_a_26_1_NC), .out_a_chain(a26_1to26_2), .out_b(b26_1to27_1), .out_b0(b26_1to27_1_ping), .out_b1(b26_1to27_1_pong), .out_c(matrixC26_1), .b_data_valid_ping(b_data_valid_ping_delay26_1), .b_data_valid_pong(b_data_valid_pong_delay26_1), .mode(1'b0)); +processing_element pe26_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_26_2_NC), .in_a_chain(a26_1to26_2), .in_b(b25_2to26_2), .in_c(matrixC25_2), .out_a(out_a_26_2_NC), .out_a_chain(a26_2to26_3), .out_b(b26_2to27_2), .out_b0(b26_2to27_2_ping), .out_b1(b26_2to27_2_pong), .out_c(matrixC26_2), .b_data_valid_ping(b_data_valid_ping_delay26_2), .b_data_valid_pong(b_data_valid_pong_delay26_2), .mode(1'b0)); +processing_element pe26_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_26_3_NC), .in_a_chain(a26_2to26_3), .in_b(b25_3to26_3), .in_c(matrixC25_3), .out_a(out_a_26_3_NC), .out_a_chain(a26_3to26_4), .out_b(b26_3to27_3), .out_b0(b26_3to27_3_ping), .out_b1(b26_3to27_3_pong), .out_c(matrixC26_3), .b_data_valid_ping(b_data_valid_ping_delay26_3), .b_data_valid_pong(b_data_valid_pong_delay26_3), .mode(1'b0)); +processing_element pe26_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_26_4_NC), .in_a_chain(a26_3to26_4), .in_b(b25_4to26_4), .in_c(matrixC25_4), .out_a(out_a_26_4_NC), .out_a_chain(a26_4to26_5), .out_b(b26_4to27_4), .out_b0(b26_4to27_4_ping), .out_b1(b26_4to27_4_pong), .out_c(matrixC26_4), .b_data_valid_ping(b_data_valid_ping_delay26_4), .b_data_valid_pong(b_data_valid_pong_delay26_4), .mode(1'b0)); +processing_element pe26_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_26_5_NC), .in_a_chain(a26_4to26_5), .in_b(b25_5to26_5), .in_c(matrixC25_5), .out_a(out_a_26_5_NC), .out_a_chain(a26_5to26_6), .out_b(b26_5to27_5), .out_b0(b26_5to27_5_ping), .out_b1(b26_5to27_5_pong), .out_c(matrixC26_5), .b_data_valid_ping(b_data_valid_ping_delay26_5), .b_data_valid_pong(b_data_valid_pong_delay26_5), .mode(1'b0)); +processing_element pe26_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_26_6_NC), .in_a_chain(a26_5to26_6), .in_b(b25_6to26_6), .in_c(matrixC25_6), .out_a(out_a_26_6_NC), .out_a_chain(a26_6to26_7), .out_b(b26_6to27_6), .out_b0(b26_6to27_6_ping), .out_b1(b26_6to27_6_pong), .out_c(matrixC26_6), .b_data_valid_ping(b_data_valid_ping_delay26_6), .b_data_valid_pong(b_data_valid_pong_delay26_6), .mode(1'b0)); +processing_element pe26_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_26_7_NC), .in_a_chain(a26_6to26_7), .in_b(b25_7to26_7), .in_c(matrixC25_7), .out_a(out_a_26_7_NC), .out_a_chain(a26_7to26_8), .out_b(b26_7to27_7), .out_b0(b26_7to27_7_ping), .out_b1(b26_7to27_7_pong), .out_c(matrixC26_7), .b_data_valid_ping(b_data_valid_ping_delay26_7), .b_data_valid_pong(b_data_valid_pong_delay26_7), .mode(1'b0)); +processing_element pe26_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_26_8_NC), .in_a_chain(a26_7to26_8), .in_b(b25_8to26_8), .in_c(matrixC25_8), .out_a(out_a_26_8_NC), .out_a_chain(a26_8to26_9), .out_b(b26_8to27_8), .out_b0(b26_8to27_8_ping), .out_b1(b26_8to27_8_pong), .out_c(matrixC26_8), .b_data_valid_ping(b_data_valid_ping_delay26_8), .b_data_valid_pong(b_data_valid_pong_delay26_8), .mode(1'b0)); +processing_element pe26_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_26_9_NC), .in_a_chain(a26_8to26_9), .in_b(b25_9to26_9), .in_c(matrixC25_9), .out_a(out_a_26_9_NC), .out_a_chain(a26_9to26_10), .out_b(b26_9to27_9), .out_b0(b26_9to27_9_ping), .out_b1(b26_9to27_9_pong), .out_c(matrixC26_9), .b_data_valid_ping(b_data_valid_ping_delay26_9), .b_data_valid_pong(b_data_valid_pong_delay26_9), .mode(1'b0)); +processing_element pe26_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_26_10_NC), .in_a_chain(a26_9to26_10), .in_b(b25_10to26_10), .in_c(matrixC25_10), .out_a(out_a_26_10_NC), .out_a_chain(a26_10to26_11), .out_b(b26_10to27_10), .out_b0(b26_10to27_10_ping), .out_b1(b26_10to27_10_pong), .out_c(matrixC26_10), .b_data_valid_ping(b_data_valid_ping_delay26_10), .b_data_valid_pong(b_data_valid_pong_delay26_10), .mode(1'b0)); +processing_element pe26_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_26_11_NC), .in_a_chain(a26_10to26_11), .in_b(b25_11to26_11), .in_c(matrixC25_11), .out_a(out_a_26_11_NC), .out_a_chain(a26_11to26_12), .out_b(b26_11to27_11), .out_b0(b26_11to27_11_ping), .out_b1(b26_11to27_11_pong), .out_c(matrixC26_11), .b_data_valid_ping(b_data_valid_ping_delay26_11), .b_data_valid_pong(b_data_valid_pong_delay26_11), .mode(1'b0)); +processing_element pe26_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_26_12_NC), .in_a_chain(a26_11to26_12), .in_b(b25_12to26_12), .in_c(matrixC25_12), .out_a(out_a_26_12_NC), .out_a_chain(a26_12to26_13), .out_b(b26_12to27_12), .out_b0(b26_12to27_12_ping), .out_b1(b26_12to27_12_pong), .out_c(matrixC26_12), .b_data_valid_ping(b_data_valid_ping_delay26_12), .b_data_valid_pong(b_data_valid_pong_delay26_12), .mode(1'b0)); +processing_element pe26_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_26_13_NC), .in_a_chain(a26_12to26_13), .in_b(b25_13to26_13), .in_c(matrixC25_13), .out_a(out_a_26_13_NC), .out_a_chain(a26_13to26_14), .out_b(b26_13to27_13), .out_b0(b26_13to27_13_ping), .out_b1(b26_13to27_13_pong), .out_c(matrixC26_13), .b_data_valid_ping(b_data_valid_ping_delay26_13), .b_data_valid_pong(b_data_valid_pong_delay26_13), .mode(1'b0)); +processing_element pe26_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_26_14_NC), .in_a_chain(a26_13to26_14), .in_b(b25_14to26_14), .in_c(matrixC25_14), .out_a(out_a_26_14_NC), .out_a_chain(a26_14to26_15), .out_b(b26_14to27_14), .out_b0(b26_14to27_14_ping), .out_b1(b26_14to27_14_pong), .out_c(matrixC26_14), .b_data_valid_ping(b_data_valid_ping_delay26_14), .b_data_valid_pong(b_data_valid_pong_delay26_14), .mode(1'b0)); +processing_element pe26_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_26_15_NC), .in_a_chain(a26_14to26_15), .in_b(b25_15to26_15), .in_c(matrixC25_15), .out_a(out_a_26_15_NC), .out_a_chain(a26_15to26_16), .out_b(b26_15to27_15), .out_b0(b26_15to27_15_ping), .out_b1(b26_15to27_15_pong), .out_c(matrixC26_15), .b_data_valid_ping(b_data_valid_ping_delay26_15), .b_data_valid_pong(b_data_valid_pong_delay26_15), .mode(1'b0)); +processing_element pe26_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_26_16_NC), .in_a_chain(a26_15to26_16), .in_b(b25_16to26_16), .in_c(matrixC25_16), .out_a(out_a_26_16_NC), .out_a_chain(a26_16to26_17), .out_b(b26_16to27_16), .out_b0(b26_16to27_16_ping), .out_b1(b26_16to27_16_pong), .out_c(matrixC26_16), .b_data_valid_ping(b_data_valid_ping_delay26_16), .b_data_valid_pong(b_data_valid_pong_delay26_16), .mode(1'b0)); +processing_element pe26_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_26_17_NC), .in_a_chain(a26_16to26_17), .in_b(b25_17to26_17), .in_c(matrixC25_17), .out_a(out_a_26_17_NC), .out_a_chain(a26_17to26_18), .out_b(b26_17to27_17), .out_b0(b26_17to27_17_ping), .out_b1(b26_17to27_17_pong), .out_c(matrixC26_17), .b_data_valid_ping(b_data_valid_ping_delay26_17), .b_data_valid_pong(b_data_valid_pong_delay26_17), .mode(1'b0)); +processing_element pe26_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_26_18_NC), .in_a_chain(a26_17to26_18), .in_b(b25_18to26_18), .in_c(matrixC25_18), .out_a(out_a_26_18_NC), .out_a_chain(a26_18to26_19), .out_b(b26_18to27_18), .out_b0(b26_18to27_18_ping), .out_b1(b26_18to27_18_pong), .out_c(matrixC26_18), .b_data_valid_ping(b_data_valid_ping_delay26_18), .b_data_valid_pong(b_data_valid_pong_delay26_18), .mode(1'b0)); +processing_element pe26_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_26_19_NC), .in_a_chain(a26_18to26_19), .in_b(b25_19to26_19), .in_c(matrixC25_19), .out_a(out_a_26_19_NC), .out_a_chain(a26_19to26_20), .out_b(b26_19to27_19), .out_b0(b26_19to27_19_ping), .out_b1(b26_19to27_19_pong), .out_c(matrixC26_19), .b_data_valid_ping(b_data_valid_ping_delay26_19), .b_data_valid_pong(b_data_valid_pong_delay26_19), .mode(1'b0)); +processing_element pe26_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_26_20_NC), .in_a_chain(a26_19to26_20), .in_b(b25_20to26_20), .in_c(matrixC25_20), .out_a(out_a_26_20_NC), .out_a_chain(a26_20to26_21), .out_b(b26_20to27_20), .out_b0(b26_20to27_20_ping), .out_b1(b26_20to27_20_pong), .out_c(matrixC26_20), .b_data_valid_ping(b_data_valid_ping_delay26_20), .b_data_valid_pong(b_data_valid_pong_delay26_20), .mode(1'b0)); +processing_element pe26_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_26_21_NC), .in_a_chain(a26_20to26_21), .in_b(b25_21to26_21), .in_c(matrixC25_21), .out_a(out_a_26_21_NC), .out_a_chain(a26_21to26_22), .out_b(b26_21to27_21), .out_b0(b26_21to27_21_ping), .out_b1(b26_21to27_21_pong), .out_c(matrixC26_21), .b_data_valid_ping(b_data_valid_ping_delay26_21), .b_data_valid_pong(b_data_valid_pong_delay26_21), .mode(1'b0)); +processing_element pe26_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay48), .in_a(in_a_26_22_NC), .in_a_chain(a26_21to26_22), .in_b(b25_22to26_22), .in_c(matrixC25_22), .out_a(out_a_26_22_NC), .out_a_chain(a26_22to26_23), .out_b(b26_22to27_22), .out_b0(b26_22to27_22_ping), .out_b1(b26_22to27_22_pong), .out_c(matrixC26_22), .b_data_valid_ping(b_data_valid_ping_delay26_22), .b_data_valid_pong(b_data_valid_pong_delay26_22), .mode(1'b0)); +processing_element pe26_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay49), .in_a(in_a_26_23_NC), .in_a_chain(a26_22to26_23), .in_b(b25_23to26_23), .in_c(matrixC25_23), .out_a(out_a_26_23_NC), .out_a_chain(a26_23to26_24), .out_b(b26_23to27_23), .out_b0(b26_23to27_23_ping), .out_b1(b26_23to27_23_pong), .out_c(matrixC26_23), .b_data_valid_ping(b_data_valid_ping_delay26_23), .b_data_valid_pong(b_data_valid_pong_delay26_23), .mode(1'b0)); +processing_element pe26_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay50), .in_a(in_a_26_24_NC), .in_a_chain(a26_23to26_24), .in_b(b25_24to26_24), .in_c(matrixC25_24), .out_a(out_a_26_24_NC), .out_a_chain(a26_24to26_25), .out_b(b26_24to27_24), .out_b0(b26_24to27_24_ping), .out_b1(b26_24to27_24_pong), .out_c(matrixC26_24), .b_data_valid_ping(b_data_valid_ping_delay26_24), .b_data_valid_pong(b_data_valid_pong_delay26_24), .mode(1'b0)); +processing_element pe26_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay51), .in_a(in_a_26_25_NC), .in_a_chain(a26_24to26_25), .in_b(b25_25to26_25), .in_c(matrixC25_25), .out_a(out_a_26_25_NC), .out_a_chain(a26_25to26_26), .out_b(b26_25to27_25), .out_b0(b26_25to27_25_ping), .out_b1(b26_25to27_25_pong), .out_c(matrixC26_25), .b_data_valid_ping(b_data_valid_ping_delay26_25), .b_data_valid_pong(b_data_valid_pong_delay26_25), .mode(1'b0)); +processing_element pe26_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay52), .in_a(in_a_26_26_NC), .in_a_chain(a26_25to26_26), .in_b(b25_26to26_26), .in_c(matrixC25_26), .out_a(out_a_26_26_NC), .out_a_chain(a26_26to26_27), .out_b(b26_26to27_26), .out_b0(b26_26to27_26_ping), .out_b1(b26_26to27_26_pong), .out_c(matrixC26_26), .b_data_valid_ping(b_data_valid_ping_delay26_26), .b_data_valid_pong(b_data_valid_pong_delay26_26), .mode(1'b0)); +processing_element pe26_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay53), .in_a(in_a_26_27_NC), .in_a_chain(a26_26to26_27), .in_b(b25_27to26_27), .in_c(matrixC25_27), .out_a(out_a_26_27_NC), .out_a_chain(a26_27to26_28), .out_b(b26_27to27_27), .out_b0(b26_27to27_27_ping), .out_b1(b26_27to27_27_pong), .out_c(matrixC26_27), .b_data_valid_ping(b_data_valid_ping_delay26_27), .b_data_valid_pong(b_data_valid_pong_delay26_27), .mode(1'b0)); +processing_element pe26_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay54), .in_a(in_a_26_28_NC), .in_a_chain(a26_27to26_28), .in_b(b25_28to26_28), .in_c(matrixC25_28), .out_a(out_a_26_28_NC), .out_a_chain(a26_28to26_29), .out_b(b26_28to27_28), .out_b0(b26_28to27_28_ping), .out_b1(b26_28to27_28_pong), .out_c(matrixC26_28), .b_data_valid_ping(b_data_valid_ping_delay26_28), .b_data_valid_pong(b_data_valid_pong_delay26_28), .mode(1'b0)); +processing_element pe26_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay55), .in_a(in_a_26_29_NC), .in_a_chain(a26_28to26_29), .in_b(b25_29to26_29), .in_c(matrixC25_29), .out_a(out_a_26_29_NC), .out_a_chain(a26_29to26_30), .out_b(b26_29to27_29), .out_b0(b26_29to27_29_ping), .out_b1(b26_29to27_29_pong), .out_c(matrixC26_29), .b_data_valid_ping(b_data_valid_ping_delay26_29), .b_data_valid_pong(b_data_valid_pong_delay26_29), .mode(1'b0)); +processing_element pe26_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay56), .in_a(in_a_26_30_NC), .in_a_chain(a26_29to26_30), .in_b(b25_30to26_30), .in_c(matrixC25_30), .out_a(out_a_26_30_NC), .out_a_chain(a26_30to26_31), .out_b(b26_30to27_30), .out_b0(b26_30to27_30_ping), .out_b1(b26_30to27_30_pong), .out_c(matrixC26_30), .b_data_valid_ping(b_data_valid_ping_delay26_30), .b_data_valid_pong(b_data_valid_pong_delay26_30), .mode(1'b0)); +processing_element pe26_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay57), .in_a(in_a_26_31_NC), .in_a_chain(a26_30to26_31), .in_b(b25_31to26_31), .in_c(matrixC25_31), .out_a(out_a_26_31_NC), .out_a_chain(a26_31to26_32), .out_b(b26_31to27_31), .out_b0(b26_31to27_31_ping), .out_b1(b26_31to27_31_pong), .out_c(matrixC26_31), .b_data_valid_ping(b_data_valid_ping_delay26_31), .b_data_valid_pong(b_data_valid_pong_delay26_31), .mode(1'b0)); +processing_element pe27_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(a27), .in_a_chain(in_a_chain_27_0_NC), .in_b(b26_0to27_0), .in_c(matrixC26_0), .out_a(out_a_27_0_NC), .out_a_chain(a27_0to27_1), .out_b(b27_0to28_0), .out_b0(b27_0to28_0_ping), .out_b1(b27_0to28_0_pong), .out_c(matrixC27_0), .b_data_valid_ping(b_data_valid_ping_delay27_0), .b_data_valid_pong(b_data_valid_pong_delay27_0), .mode(1'b1)); +processing_element pe27_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_27_1_NC), .in_a_chain(a27_0to27_1), .in_b(b26_1to27_1), .in_c(matrixC26_1), .out_a(out_a_27_1_NC), .out_a_chain(a27_1to27_2), .out_b(b27_1to28_1), .out_b0(b27_1to28_1_ping), .out_b1(b27_1to28_1_pong), .out_c(matrixC27_1), .b_data_valid_ping(b_data_valid_ping_delay27_1), .b_data_valid_pong(b_data_valid_pong_delay27_1), .mode(1'b0)); +processing_element pe27_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_27_2_NC), .in_a_chain(a27_1to27_2), .in_b(b26_2to27_2), .in_c(matrixC26_2), .out_a(out_a_27_2_NC), .out_a_chain(a27_2to27_3), .out_b(b27_2to28_2), .out_b0(b27_2to28_2_ping), .out_b1(b27_2to28_2_pong), .out_c(matrixC27_2), .b_data_valid_ping(b_data_valid_ping_delay27_2), .b_data_valid_pong(b_data_valid_pong_delay27_2), .mode(1'b0)); +processing_element pe27_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_27_3_NC), .in_a_chain(a27_2to27_3), .in_b(b26_3to27_3), .in_c(matrixC26_3), .out_a(out_a_27_3_NC), .out_a_chain(a27_3to27_4), .out_b(b27_3to28_3), .out_b0(b27_3to28_3_ping), .out_b1(b27_3to28_3_pong), .out_c(matrixC27_3), .b_data_valid_ping(b_data_valid_ping_delay27_3), .b_data_valid_pong(b_data_valid_pong_delay27_3), .mode(1'b0)); +processing_element pe27_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_27_4_NC), .in_a_chain(a27_3to27_4), .in_b(b26_4to27_4), .in_c(matrixC26_4), .out_a(out_a_27_4_NC), .out_a_chain(a27_4to27_5), .out_b(b27_4to28_4), .out_b0(b27_4to28_4_ping), .out_b1(b27_4to28_4_pong), .out_c(matrixC27_4), .b_data_valid_ping(b_data_valid_ping_delay27_4), .b_data_valid_pong(b_data_valid_pong_delay27_4), .mode(1'b0)); +processing_element pe27_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_27_5_NC), .in_a_chain(a27_4to27_5), .in_b(b26_5to27_5), .in_c(matrixC26_5), .out_a(out_a_27_5_NC), .out_a_chain(a27_5to27_6), .out_b(b27_5to28_5), .out_b0(b27_5to28_5_ping), .out_b1(b27_5to28_5_pong), .out_c(matrixC27_5), .b_data_valid_ping(b_data_valid_ping_delay27_5), .b_data_valid_pong(b_data_valid_pong_delay27_5), .mode(1'b0)); +processing_element pe27_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_27_6_NC), .in_a_chain(a27_5to27_6), .in_b(b26_6to27_6), .in_c(matrixC26_6), .out_a(out_a_27_6_NC), .out_a_chain(a27_6to27_7), .out_b(b27_6to28_6), .out_b0(b27_6to28_6_ping), .out_b1(b27_6to28_6_pong), .out_c(matrixC27_6), .b_data_valid_ping(b_data_valid_ping_delay27_6), .b_data_valid_pong(b_data_valid_pong_delay27_6), .mode(1'b0)); +processing_element pe27_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_27_7_NC), .in_a_chain(a27_6to27_7), .in_b(b26_7to27_7), .in_c(matrixC26_7), .out_a(out_a_27_7_NC), .out_a_chain(a27_7to27_8), .out_b(b27_7to28_7), .out_b0(b27_7to28_7_ping), .out_b1(b27_7to28_7_pong), .out_c(matrixC27_7), .b_data_valid_ping(b_data_valid_ping_delay27_7), .b_data_valid_pong(b_data_valid_pong_delay27_7), .mode(1'b0)); +processing_element pe27_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_27_8_NC), .in_a_chain(a27_7to27_8), .in_b(b26_8to27_8), .in_c(matrixC26_8), .out_a(out_a_27_8_NC), .out_a_chain(a27_8to27_9), .out_b(b27_8to28_8), .out_b0(b27_8to28_8_ping), .out_b1(b27_8to28_8_pong), .out_c(matrixC27_8), .b_data_valid_ping(b_data_valid_ping_delay27_8), .b_data_valid_pong(b_data_valid_pong_delay27_8), .mode(1'b0)); +processing_element pe27_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_27_9_NC), .in_a_chain(a27_8to27_9), .in_b(b26_9to27_9), .in_c(matrixC26_9), .out_a(out_a_27_9_NC), .out_a_chain(a27_9to27_10), .out_b(b27_9to28_9), .out_b0(b27_9to28_9_ping), .out_b1(b27_9to28_9_pong), .out_c(matrixC27_9), .b_data_valid_ping(b_data_valid_ping_delay27_9), .b_data_valid_pong(b_data_valid_pong_delay27_9), .mode(1'b0)); +processing_element pe27_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_27_10_NC), .in_a_chain(a27_9to27_10), .in_b(b26_10to27_10), .in_c(matrixC26_10), .out_a(out_a_27_10_NC), .out_a_chain(a27_10to27_11), .out_b(b27_10to28_10), .out_b0(b27_10to28_10_ping), .out_b1(b27_10to28_10_pong), .out_c(matrixC27_10), .b_data_valid_ping(b_data_valid_ping_delay27_10), .b_data_valid_pong(b_data_valid_pong_delay27_10), .mode(1'b0)); +processing_element pe27_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_27_11_NC), .in_a_chain(a27_10to27_11), .in_b(b26_11to27_11), .in_c(matrixC26_11), .out_a(out_a_27_11_NC), .out_a_chain(a27_11to27_12), .out_b(b27_11to28_11), .out_b0(b27_11to28_11_ping), .out_b1(b27_11to28_11_pong), .out_c(matrixC27_11), .b_data_valid_ping(b_data_valid_ping_delay27_11), .b_data_valid_pong(b_data_valid_pong_delay27_11), .mode(1'b0)); +processing_element pe27_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_27_12_NC), .in_a_chain(a27_11to27_12), .in_b(b26_12to27_12), .in_c(matrixC26_12), .out_a(out_a_27_12_NC), .out_a_chain(a27_12to27_13), .out_b(b27_12to28_12), .out_b0(b27_12to28_12_ping), .out_b1(b27_12to28_12_pong), .out_c(matrixC27_12), .b_data_valid_ping(b_data_valid_ping_delay27_12), .b_data_valid_pong(b_data_valid_pong_delay27_12), .mode(1'b0)); +processing_element pe27_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_27_13_NC), .in_a_chain(a27_12to27_13), .in_b(b26_13to27_13), .in_c(matrixC26_13), .out_a(out_a_27_13_NC), .out_a_chain(a27_13to27_14), .out_b(b27_13to28_13), .out_b0(b27_13to28_13_ping), .out_b1(b27_13to28_13_pong), .out_c(matrixC27_13), .b_data_valid_ping(b_data_valid_ping_delay27_13), .b_data_valid_pong(b_data_valid_pong_delay27_13), .mode(1'b0)); +processing_element pe27_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_27_14_NC), .in_a_chain(a27_13to27_14), .in_b(b26_14to27_14), .in_c(matrixC26_14), .out_a(out_a_27_14_NC), .out_a_chain(a27_14to27_15), .out_b(b27_14to28_14), .out_b0(b27_14to28_14_ping), .out_b1(b27_14to28_14_pong), .out_c(matrixC27_14), .b_data_valid_ping(b_data_valid_ping_delay27_14), .b_data_valid_pong(b_data_valid_pong_delay27_14), .mode(1'b0)); +processing_element pe27_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_27_15_NC), .in_a_chain(a27_14to27_15), .in_b(b26_15to27_15), .in_c(matrixC26_15), .out_a(out_a_27_15_NC), .out_a_chain(a27_15to27_16), .out_b(b27_15to28_15), .out_b0(b27_15to28_15_ping), .out_b1(b27_15to28_15_pong), .out_c(matrixC27_15), .b_data_valid_ping(b_data_valid_ping_delay27_15), .b_data_valid_pong(b_data_valid_pong_delay27_15), .mode(1'b0)); +processing_element pe27_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_27_16_NC), .in_a_chain(a27_15to27_16), .in_b(b26_16to27_16), .in_c(matrixC26_16), .out_a(out_a_27_16_NC), .out_a_chain(a27_16to27_17), .out_b(b27_16to28_16), .out_b0(b27_16to28_16_ping), .out_b1(b27_16to28_16_pong), .out_c(matrixC27_16), .b_data_valid_ping(b_data_valid_ping_delay27_16), .b_data_valid_pong(b_data_valid_pong_delay27_16), .mode(1'b0)); +processing_element pe27_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_27_17_NC), .in_a_chain(a27_16to27_17), .in_b(b26_17to27_17), .in_c(matrixC26_17), .out_a(out_a_27_17_NC), .out_a_chain(a27_17to27_18), .out_b(b27_17to28_17), .out_b0(b27_17to28_17_ping), .out_b1(b27_17to28_17_pong), .out_c(matrixC27_17), .b_data_valid_ping(b_data_valid_ping_delay27_17), .b_data_valid_pong(b_data_valid_pong_delay27_17), .mode(1'b0)); +processing_element pe27_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_27_18_NC), .in_a_chain(a27_17to27_18), .in_b(b26_18to27_18), .in_c(matrixC26_18), .out_a(out_a_27_18_NC), .out_a_chain(a27_18to27_19), .out_b(b27_18to28_18), .out_b0(b27_18to28_18_ping), .out_b1(b27_18to28_18_pong), .out_c(matrixC27_18), .b_data_valid_ping(b_data_valid_ping_delay27_18), .b_data_valid_pong(b_data_valid_pong_delay27_18), .mode(1'b0)); +processing_element pe27_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_27_19_NC), .in_a_chain(a27_18to27_19), .in_b(b26_19to27_19), .in_c(matrixC26_19), .out_a(out_a_27_19_NC), .out_a_chain(a27_19to27_20), .out_b(b27_19to28_19), .out_b0(b27_19to28_19_ping), .out_b1(b27_19to28_19_pong), .out_c(matrixC27_19), .b_data_valid_ping(b_data_valid_ping_delay27_19), .b_data_valid_pong(b_data_valid_pong_delay27_19), .mode(1'b0)); +processing_element pe27_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_27_20_NC), .in_a_chain(a27_19to27_20), .in_b(b26_20to27_20), .in_c(matrixC26_20), .out_a(out_a_27_20_NC), .out_a_chain(a27_20to27_21), .out_b(b27_20to28_20), .out_b0(b27_20to28_20_ping), .out_b1(b27_20to28_20_pong), .out_c(matrixC27_20), .b_data_valid_ping(b_data_valid_ping_delay27_20), .b_data_valid_pong(b_data_valid_pong_delay27_20), .mode(1'b0)); +processing_element pe27_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay48), .in_a(in_a_27_21_NC), .in_a_chain(a27_20to27_21), .in_b(b26_21to27_21), .in_c(matrixC26_21), .out_a(out_a_27_21_NC), .out_a_chain(a27_21to27_22), .out_b(b27_21to28_21), .out_b0(b27_21to28_21_ping), .out_b1(b27_21to28_21_pong), .out_c(matrixC27_21), .b_data_valid_ping(b_data_valid_ping_delay27_21), .b_data_valid_pong(b_data_valid_pong_delay27_21), .mode(1'b0)); +processing_element pe27_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay49), .in_a(in_a_27_22_NC), .in_a_chain(a27_21to27_22), .in_b(b26_22to27_22), .in_c(matrixC26_22), .out_a(out_a_27_22_NC), .out_a_chain(a27_22to27_23), .out_b(b27_22to28_22), .out_b0(b27_22to28_22_ping), .out_b1(b27_22to28_22_pong), .out_c(matrixC27_22), .b_data_valid_ping(b_data_valid_ping_delay27_22), .b_data_valid_pong(b_data_valid_pong_delay27_22), .mode(1'b0)); +processing_element pe27_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay50), .in_a(in_a_27_23_NC), .in_a_chain(a27_22to27_23), .in_b(b26_23to27_23), .in_c(matrixC26_23), .out_a(out_a_27_23_NC), .out_a_chain(a27_23to27_24), .out_b(b27_23to28_23), .out_b0(b27_23to28_23_ping), .out_b1(b27_23to28_23_pong), .out_c(matrixC27_23), .b_data_valid_ping(b_data_valid_ping_delay27_23), .b_data_valid_pong(b_data_valid_pong_delay27_23), .mode(1'b0)); +processing_element pe27_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay51), .in_a(in_a_27_24_NC), .in_a_chain(a27_23to27_24), .in_b(b26_24to27_24), .in_c(matrixC26_24), .out_a(out_a_27_24_NC), .out_a_chain(a27_24to27_25), .out_b(b27_24to28_24), .out_b0(b27_24to28_24_ping), .out_b1(b27_24to28_24_pong), .out_c(matrixC27_24), .b_data_valid_ping(b_data_valid_ping_delay27_24), .b_data_valid_pong(b_data_valid_pong_delay27_24), .mode(1'b0)); +processing_element pe27_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay52), .in_a(in_a_27_25_NC), .in_a_chain(a27_24to27_25), .in_b(b26_25to27_25), .in_c(matrixC26_25), .out_a(out_a_27_25_NC), .out_a_chain(a27_25to27_26), .out_b(b27_25to28_25), .out_b0(b27_25to28_25_ping), .out_b1(b27_25to28_25_pong), .out_c(matrixC27_25), .b_data_valid_ping(b_data_valid_ping_delay27_25), .b_data_valid_pong(b_data_valid_pong_delay27_25), .mode(1'b0)); +processing_element pe27_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay53), .in_a(in_a_27_26_NC), .in_a_chain(a27_25to27_26), .in_b(b26_26to27_26), .in_c(matrixC26_26), .out_a(out_a_27_26_NC), .out_a_chain(a27_26to27_27), .out_b(b27_26to28_26), .out_b0(b27_26to28_26_ping), .out_b1(b27_26to28_26_pong), .out_c(matrixC27_26), .b_data_valid_ping(b_data_valid_ping_delay27_26), .b_data_valid_pong(b_data_valid_pong_delay27_26), .mode(1'b0)); +processing_element pe27_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay54), .in_a(in_a_27_27_NC), .in_a_chain(a27_26to27_27), .in_b(b26_27to27_27), .in_c(matrixC26_27), .out_a(out_a_27_27_NC), .out_a_chain(a27_27to27_28), .out_b(b27_27to28_27), .out_b0(b27_27to28_27_ping), .out_b1(b27_27to28_27_pong), .out_c(matrixC27_27), .b_data_valid_ping(b_data_valid_ping_delay27_27), .b_data_valid_pong(b_data_valid_pong_delay27_27), .mode(1'b0)); +processing_element pe27_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay55), .in_a(in_a_27_28_NC), .in_a_chain(a27_27to27_28), .in_b(b26_28to27_28), .in_c(matrixC26_28), .out_a(out_a_27_28_NC), .out_a_chain(a27_28to27_29), .out_b(b27_28to28_28), .out_b0(b27_28to28_28_ping), .out_b1(b27_28to28_28_pong), .out_c(matrixC27_28), .b_data_valid_ping(b_data_valid_ping_delay27_28), .b_data_valid_pong(b_data_valid_pong_delay27_28), .mode(1'b0)); +processing_element pe27_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay56), .in_a(in_a_27_29_NC), .in_a_chain(a27_28to27_29), .in_b(b26_29to27_29), .in_c(matrixC26_29), .out_a(out_a_27_29_NC), .out_a_chain(a27_29to27_30), .out_b(b27_29to28_29), .out_b0(b27_29to28_29_ping), .out_b1(b27_29to28_29_pong), .out_c(matrixC27_29), .b_data_valid_ping(b_data_valid_ping_delay27_29), .b_data_valid_pong(b_data_valid_pong_delay27_29), .mode(1'b0)); +processing_element pe27_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay57), .in_a(in_a_27_30_NC), .in_a_chain(a27_29to27_30), .in_b(b26_30to27_30), .in_c(matrixC26_30), .out_a(out_a_27_30_NC), .out_a_chain(a27_30to27_31), .out_b(b27_30to28_30), .out_b0(b27_30to28_30_ping), .out_b1(b27_30to28_30_pong), .out_c(matrixC27_30), .b_data_valid_ping(b_data_valid_ping_delay27_30), .b_data_valid_pong(b_data_valid_pong_delay27_30), .mode(1'b0)); +processing_element pe27_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay58), .in_a(in_a_27_31_NC), .in_a_chain(a27_30to27_31), .in_b(b26_31to27_31), .in_c(matrixC26_31), .out_a(out_a_27_31_NC), .out_a_chain(a27_31to27_32), .out_b(b27_31to28_31), .out_b0(b27_31to28_31_ping), .out_b1(b27_31to28_31_pong), .out_c(matrixC27_31), .b_data_valid_ping(b_data_valid_ping_delay27_31), .b_data_valid_pong(b_data_valid_pong_delay27_31), .mode(1'b0)); +processing_element pe28_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(a28), .in_a_chain(in_a_chain_28_0_NC), .in_b(b27_0to28_0), .in_c(matrixC27_0), .out_a(out_a_28_0_NC), .out_a_chain(a28_0to28_1), .out_b(b28_0to29_0), .out_b0(b28_0to29_0_ping), .out_b1(b28_0to29_0_pong), .out_c(matrixC28_0), .b_data_valid_ping(b_data_valid_ping_delay28_0), .b_data_valid_pong(b_data_valid_pong_delay28_0), .mode(1'b1)); +processing_element pe28_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_28_1_NC), .in_a_chain(a28_0to28_1), .in_b(b27_1to28_1), .in_c(matrixC27_1), .out_a(out_a_28_1_NC), .out_a_chain(a28_1to28_2), .out_b(b28_1to29_1), .out_b0(b28_1to29_1_ping), .out_b1(b28_1to29_1_pong), .out_c(matrixC28_1), .b_data_valid_ping(b_data_valid_ping_delay28_1), .b_data_valid_pong(b_data_valid_pong_delay28_1), .mode(1'b0)); +processing_element pe28_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_28_2_NC), .in_a_chain(a28_1to28_2), .in_b(b27_2to28_2), .in_c(matrixC27_2), .out_a(out_a_28_2_NC), .out_a_chain(a28_2to28_3), .out_b(b28_2to29_2), .out_b0(b28_2to29_2_ping), .out_b1(b28_2to29_2_pong), .out_c(matrixC28_2), .b_data_valid_ping(b_data_valid_ping_delay28_2), .b_data_valid_pong(b_data_valid_pong_delay28_2), .mode(1'b0)); +processing_element pe28_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_28_3_NC), .in_a_chain(a28_2to28_3), .in_b(b27_3to28_3), .in_c(matrixC27_3), .out_a(out_a_28_3_NC), .out_a_chain(a28_3to28_4), .out_b(b28_3to29_3), .out_b0(b28_3to29_3_ping), .out_b1(b28_3to29_3_pong), .out_c(matrixC28_3), .b_data_valid_ping(b_data_valid_ping_delay28_3), .b_data_valid_pong(b_data_valid_pong_delay28_3), .mode(1'b0)); +processing_element pe28_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_28_4_NC), .in_a_chain(a28_3to28_4), .in_b(b27_4to28_4), .in_c(matrixC27_4), .out_a(out_a_28_4_NC), .out_a_chain(a28_4to28_5), .out_b(b28_4to29_4), .out_b0(b28_4to29_4_ping), .out_b1(b28_4to29_4_pong), .out_c(matrixC28_4), .b_data_valid_ping(b_data_valid_ping_delay28_4), .b_data_valid_pong(b_data_valid_pong_delay28_4), .mode(1'b0)); +processing_element pe28_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_28_5_NC), .in_a_chain(a28_4to28_5), .in_b(b27_5to28_5), .in_c(matrixC27_5), .out_a(out_a_28_5_NC), .out_a_chain(a28_5to28_6), .out_b(b28_5to29_5), .out_b0(b28_5to29_5_ping), .out_b1(b28_5to29_5_pong), .out_c(matrixC28_5), .b_data_valid_ping(b_data_valid_ping_delay28_5), .b_data_valid_pong(b_data_valid_pong_delay28_5), .mode(1'b0)); +processing_element pe28_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_28_6_NC), .in_a_chain(a28_5to28_6), .in_b(b27_6to28_6), .in_c(matrixC27_6), .out_a(out_a_28_6_NC), .out_a_chain(a28_6to28_7), .out_b(b28_6to29_6), .out_b0(b28_6to29_6_ping), .out_b1(b28_6to29_6_pong), .out_c(matrixC28_6), .b_data_valid_ping(b_data_valid_ping_delay28_6), .b_data_valid_pong(b_data_valid_pong_delay28_6), .mode(1'b0)); +processing_element pe28_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_28_7_NC), .in_a_chain(a28_6to28_7), .in_b(b27_7to28_7), .in_c(matrixC27_7), .out_a(out_a_28_7_NC), .out_a_chain(a28_7to28_8), .out_b(b28_7to29_7), .out_b0(b28_7to29_7_ping), .out_b1(b28_7to29_7_pong), .out_c(matrixC28_7), .b_data_valid_ping(b_data_valid_ping_delay28_7), .b_data_valid_pong(b_data_valid_pong_delay28_7), .mode(1'b0)); +processing_element pe28_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_28_8_NC), .in_a_chain(a28_7to28_8), .in_b(b27_8to28_8), .in_c(matrixC27_8), .out_a(out_a_28_8_NC), .out_a_chain(a28_8to28_9), .out_b(b28_8to29_8), .out_b0(b28_8to29_8_ping), .out_b1(b28_8to29_8_pong), .out_c(matrixC28_8), .b_data_valid_ping(b_data_valid_ping_delay28_8), .b_data_valid_pong(b_data_valid_pong_delay28_8), .mode(1'b0)); +processing_element pe28_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_28_9_NC), .in_a_chain(a28_8to28_9), .in_b(b27_9to28_9), .in_c(matrixC27_9), .out_a(out_a_28_9_NC), .out_a_chain(a28_9to28_10), .out_b(b28_9to29_9), .out_b0(b28_9to29_9_ping), .out_b1(b28_9to29_9_pong), .out_c(matrixC28_9), .b_data_valid_ping(b_data_valid_ping_delay28_9), .b_data_valid_pong(b_data_valid_pong_delay28_9), .mode(1'b0)); +processing_element pe28_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_28_10_NC), .in_a_chain(a28_9to28_10), .in_b(b27_10to28_10), .in_c(matrixC27_10), .out_a(out_a_28_10_NC), .out_a_chain(a28_10to28_11), .out_b(b28_10to29_10), .out_b0(b28_10to29_10_ping), .out_b1(b28_10to29_10_pong), .out_c(matrixC28_10), .b_data_valid_ping(b_data_valid_ping_delay28_10), .b_data_valid_pong(b_data_valid_pong_delay28_10), .mode(1'b0)); +processing_element pe28_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_28_11_NC), .in_a_chain(a28_10to28_11), .in_b(b27_11to28_11), .in_c(matrixC27_11), .out_a(out_a_28_11_NC), .out_a_chain(a28_11to28_12), .out_b(b28_11to29_11), .out_b0(b28_11to29_11_ping), .out_b1(b28_11to29_11_pong), .out_c(matrixC28_11), .b_data_valid_ping(b_data_valid_ping_delay28_11), .b_data_valid_pong(b_data_valid_pong_delay28_11), .mode(1'b0)); +processing_element pe28_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_28_12_NC), .in_a_chain(a28_11to28_12), .in_b(b27_12to28_12), .in_c(matrixC27_12), .out_a(out_a_28_12_NC), .out_a_chain(a28_12to28_13), .out_b(b28_12to29_12), .out_b0(b28_12to29_12_ping), .out_b1(b28_12to29_12_pong), .out_c(matrixC28_12), .b_data_valid_ping(b_data_valid_ping_delay28_12), .b_data_valid_pong(b_data_valid_pong_delay28_12), .mode(1'b0)); +processing_element pe28_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_28_13_NC), .in_a_chain(a28_12to28_13), .in_b(b27_13to28_13), .in_c(matrixC27_13), .out_a(out_a_28_13_NC), .out_a_chain(a28_13to28_14), .out_b(b28_13to29_13), .out_b0(b28_13to29_13_ping), .out_b1(b28_13to29_13_pong), .out_c(matrixC28_13), .b_data_valid_ping(b_data_valid_ping_delay28_13), .b_data_valid_pong(b_data_valid_pong_delay28_13), .mode(1'b0)); +processing_element pe28_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_28_14_NC), .in_a_chain(a28_13to28_14), .in_b(b27_14to28_14), .in_c(matrixC27_14), .out_a(out_a_28_14_NC), .out_a_chain(a28_14to28_15), .out_b(b28_14to29_14), .out_b0(b28_14to29_14_ping), .out_b1(b28_14to29_14_pong), .out_c(matrixC28_14), .b_data_valid_ping(b_data_valid_ping_delay28_14), .b_data_valid_pong(b_data_valid_pong_delay28_14), .mode(1'b0)); +processing_element pe28_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_28_15_NC), .in_a_chain(a28_14to28_15), .in_b(b27_15to28_15), .in_c(matrixC27_15), .out_a(out_a_28_15_NC), .out_a_chain(a28_15to28_16), .out_b(b28_15to29_15), .out_b0(b28_15to29_15_ping), .out_b1(b28_15to29_15_pong), .out_c(matrixC28_15), .b_data_valid_ping(b_data_valid_ping_delay28_15), .b_data_valid_pong(b_data_valid_pong_delay28_15), .mode(1'b0)); +processing_element pe28_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_28_16_NC), .in_a_chain(a28_15to28_16), .in_b(b27_16to28_16), .in_c(matrixC27_16), .out_a(out_a_28_16_NC), .out_a_chain(a28_16to28_17), .out_b(b28_16to29_16), .out_b0(b28_16to29_16_ping), .out_b1(b28_16to29_16_pong), .out_c(matrixC28_16), .b_data_valid_ping(b_data_valid_ping_delay28_16), .b_data_valid_pong(b_data_valid_pong_delay28_16), .mode(1'b0)); +processing_element pe28_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_28_17_NC), .in_a_chain(a28_16to28_17), .in_b(b27_17to28_17), .in_c(matrixC27_17), .out_a(out_a_28_17_NC), .out_a_chain(a28_17to28_18), .out_b(b28_17to29_17), .out_b0(b28_17to29_17_ping), .out_b1(b28_17to29_17_pong), .out_c(matrixC28_17), .b_data_valid_ping(b_data_valid_ping_delay28_17), .b_data_valid_pong(b_data_valid_pong_delay28_17), .mode(1'b0)); +processing_element pe28_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_28_18_NC), .in_a_chain(a28_17to28_18), .in_b(b27_18to28_18), .in_c(matrixC27_18), .out_a(out_a_28_18_NC), .out_a_chain(a28_18to28_19), .out_b(b28_18to29_18), .out_b0(b28_18to29_18_ping), .out_b1(b28_18to29_18_pong), .out_c(matrixC28_18), .b_data_valid_ping(b_data_valid_ping_delay28_18), .b_data_valid_pong(b_data_valid_pong_delay28_18), .mode(1'b0)); +processing_element pe28_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_28_19_NC), .in_a_chain(a28_18to28_19), .in_b(b27_19to28_19), .in_c(matrixC27_19), .out_a(out_a_28_19_NC), .out_a_chain(a28_19to28_20), .out_b(b28_19to29_19), .out_b0(b28_19to29_19_ping), .out_b1(b28_19to29_19_pong), .out_c(matrixC28_19), .b_data_valid_ping(b_data_valid_ping_delay28_19), .b_data_valid_pong(b_data_valid_pong_delay28_19), .mode(1'b0)); +processing_element pe28_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay48), .in_a(in_a_28_20_NC), .in_a_chain(a28_19to28_20), .in_b(b27_20to28_20), .in_c(matrixC27_20), .out_a(out_a_28_20_NC), .out_a_chain(a28_20to28_21), .out_b(b28_20to29_20), .out_b0(b28_20to29_20_ping), .out_b1(b28_20to29_20_pong), .out_c(matrixC28_20), .b_data_valid_ping(b_data_valid_ping_delay28_20), .b_data_valid_pong(b_data_valid_pong_delay28_20), .mode(1'b0)); +processing_element pe28_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay49), .in_a(in_a_28_21_NC), .in_a_chain(a28_20to28_21), .in_b(b27_21to28_21), .in_c(matrixC27_21), .out_a(out_a_28_21_NC), .out_a_chain(a28_21to28_22), .out_b(b28_21to29_21), .out_b0(b28_21to29_21_ping), .out_b1(b28_21to29_21_pong), .out_c(matrixC28_21), .b_data_valid_ping(b_data_valid_ping_delay28_21), .b_data_valid_pong(b_data_valid_pong_delay28_21), .mode(1'b0)); +processing_element pe28_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay50), .in_a(in_a_28_22_NC), .in_a_chain(a28_21to28_22), .in_b(b27_22to28_22), .in_c(matrixC27_22), .out_a(out_a_28_22_NC), .out_a_chain(a28_22to28_23), .out_b(b28_22to29_22), .out_b0(b28_22to29_22_ping), .out_b1(b28_22to29_22_pong), .out_c(matrixC28_22), .b_data_valid_ping(b_data_valid_ping_delay28_22), .b_data_valid_pong(b_data_valid_pong_delay28_22), .mode(1'b0)); +processing_element pe28_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay51), .in_a(in_a_28_23_NC), .in_a_chain(a28_22to28_23), .in_b(b27_23to28_23), .in_c(matrixC27_23), .out_a(out_a_28_23_NC), .out_a_chain(a28_23to28_24), .out_b(b28_23to29_23), .out_b0(b28_23to29_23_ping), .out_b1(b28_23to29_23_pong), .out_c(matrixC28_23), .b_data_valid_ping(b_data_valid_ping_delay28_23), .b_data_valid_pong(b_data_valid_pong_delay28_23), .mode(1'b0)); +processing_element pe28_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay52), .in_a(in_a_28_24_NC), .in_a_chain(a28_23to28_24), .in_b(b27_24to28_24), .in_c(matrixC27_24), .out_a(out_a_28_24_NC), .out_a_chain(a28_24to28_25), .out_b(b28_24to29_24), .out_b0(b28_24to29_24_ping), .out_b1(b28_24to29_24_pong), .out_c(matrixC28_24), .b_data_valid_ping(b_data_valid_ping_delay28_24), .b_data_valid_pong(b_data_valid_pong_delay28_24), .mode(1'b0)); +processing_element pe28_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay53), .in_a(in_a_28_25_NC), .in_a_chain(a28_24to28_25), .in_b(b27_25to28_25), .in_c(matrixC27_25), .out_a(out_a_28_25_NC), .out_a_chain(a28_25to28_26), .out_b(b28_25to29_25), .out_b0(b28_25to29_25_ping), .out_b1(b28_25to29_25_pong), .out_c(matrixC28_25), .b_data_valid_ping(b_data_valid_ping_delay28_25), .b_data_valid_pong(b_data_valid_pong_delay28_25), .mode(1'b0)); +processing_element pe28_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay54), .in_a(in_a_28_26_NC), .in_a_chain(a28_25to28_26), .in_b(b27_26to28_26), .in_c(matrixC27_26), .out_a(out_a_28_26_NC), .out_a_chain(a28_26to28_27), .out_b(b28_26to29_26), .out_b0(b28_26to29_26_ping), .out_b1(b28_26to29_26_pong), .out_c(matrixC28_26), .b_data_valid_ping(b_data_valid_ping_delay28_26), .b_data_valid_pong(b_data_valid_pong_delay28_26), .mode(1'b0)); +processing_element pe28_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay55), .in_a(in_a_28_27_NC), .in_a_chain(a28_26to28_27), .in_b(b27_27to28_27), .in_c(matrixC27_27), .out_a(out_a_28_27_NC), .out_a_chain(a28_27to28_28), .out_b(b28_27to29_27), .out_b0(b28_27to29_27_ping), .out_b1(b28_27to29_27_pong), .out_c(matrixC28_27), .b_data_valid_ping(b_data_valid_ping_delay28_27), .b_data_valid_pong(b_data_valid_pong_delay28_27), .mode(1'b0)); +processing_element pe28_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay56), .in_a(in_a_28_28_NC), .in_a_chain(a28_27to28_28), .in_b(b27_28to28_28), .in_c(matrixC27_28), .out_a(out_a_28_28_NC), .out_a_chain(a28_28to28_29), .out_b(b28_28to29_28), .out_b0(b28_28to29_28_ping), .out_b1(b28_28to29_28_pong), .out_c(matrixC28_28), .b_data_valid_ping(b_data_valid_ping_delay28_28), .b_data_valid_pong(b_data_valid_pong_delay28_28), .mode(1'b0)); +processing_element pe28_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay57), .in_a(in_a_28_29_NC), .in_a_chain(a28_28to28_29), .in_b(b27_29to28_29), .in_c(matrixC27_29), .out_a(out_a_28_29_NC), .out_a_chain(a28_29to28_30), .out_b(b28_29to29_29), .out_b0(b28_29to29_29_ping), .out_b1(b28_29to29_29_pong), .out_c(matrixC28_29), .b_data_valid_ping(b_data_valid_ping_delay28_29), .b_data_valid_pong(b_data_valid_pong_delay28_29), .mode(1'b0)); +processing_element pe28_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay58), .in_a(in_a_28_30_NC), .in_a_chain(a28_29to28_30), .in_b(b27_30to28_30), .in_c(matrixC27_30), .out_a(out_a_28_30_NC), .out_a_chain(a28_30to28_31), .out_b(b28_30to29_30), .out_b0(b28_30to29_30_ping), .out_b1(b28_30to29_30_pong), .out_c(matrixC28_30), .b_data_valid_ping(b_data_valid_ping_delay28_30), .b_data_valid_pong(b_data_valid_pong_delay28_30), .mode(1'b0)); +processing_element pe28_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay59), .in_a(in_a_28_31_NC), .in_a_chain(a28_30to28_31), .in_b(b27_31to28_31), .in_c(matrixC27_31), .out_a(out_a_28_31_NC), .out_a_chain(a28_31to28_32), .out_b(b28_31to29_31), .out_b0(b28_31to29_31_ping), .out_b1(b28_31to29_31_pong), .out_c(matrixC28_31), .b_data_valid_ping(b_data_valid_ping_delay28_31), .b_data_valid_pong(b_data_valid_pong_delay28_31), .mode(1'b0)); +processing_element pe29_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(a29), .in_a_chain(in_a_chain_29_0_NC), .in_b(b28_0to29_0), .in_c(matrixC28_0), .out_a(out_a_29_0_NC), .out_a_chain(a29_0to29_1), .out_b(b29_0to30_0), .out_b0(b29_0to30_0_ping), .out_b1(b29_0to30_0_pong), .out_c(matrixC29_0), .b_data_valid_ping(b_data_valid_ping_delay29_0), .b_data_valid_pong(b_data_valid_pong_delay29_0), .mode(1'b1)); +processing_element pe29_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_29_1_NC), .in_a_chain(a29_0to29_1), .in_b(b28_1to29_1), .in_c(matrixC28_1), .out_a(out_a_29_1_NC), .out_a_chain(a29_1to29_2), .out_b(b29_1to30_1), .out_b0(b29_1to30_1_ping), .out_b1(b29_1to30_1_pong), .out_c(matrixC29_1), .b_data_valid_ping(b_data_valid_ping_delay29_1), .b_data_valid_pong(b_data_valid_pong_delay29_1), .mode(1'b0)); +processing_element pe29_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_29_2_NC), .in_a_chain(a29_1to29_2), .in_b(b28_2to29_2), .in_c(matrixC28_2), .out_a(out_a_29_2_NC), .out_a_chain(a29_2to29_3), .out_b(b29_2to30_2), .out_b0(b29_2to30_2_ping), .out_b1(b29_2to30_2_pong), .out_c(matrixC29_2), .b_data_valid_ping(b_data_valid_ping_delay29_2), .b_data_valid_pong(b_data_valid_pong_delay29_2), .mode(1'b0)); +processing_element pe29_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_29_3_NC), .in_a_chain(a29_2to29_3), .in_b(b28_3to29_3), .in_c(matrixC28_3), .out_a(out_a_29_3_NC), .out_a_chain(a29_3to29_4), .out_b(b29_3to30_3), .out_b0(b29_3to30_3_ping), .out_b1(b29_3to30_3_pong), .out_c(matrixC29_3), .b_data_valid_ping(b_data_valid_ping_delay29_3), .b_data_valid_pong(b_data_valid_pong_delay29_3), .mode(1'b0)); +processing_element pe29_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_29_4_NC), .in_a_chain(a29_3to29_4), .in_b(b28_4to29_4), .in_c(matrixC28_4), .out_a(out_a_29_4_NC), .out_a_chain(a29_4to29_5), .out_b(b29_4to30_4), .out_b0(b29_4to30_4_ping), .out_b1(b29_4to30_4_pong), .out_c(matrixC29_4), .b_data_valid_ping(b_data_valid_ping_delay29_4), .b_data_valid_pong(b_data_valid_pong_delay29_4), .mode(1'b0)); +processing_element pe29_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_29_5_NC), .in_a_chain(a29_4to29_5), .in_b(b28_5to29_5), .in_c(matrixC28_5), .out_a(out_a_29_5_NC), .out_a_chain(a29_5to29_6), .out_b(b29_5to30_5), .out_b0(b29_5to30_5_ping), .out_b1(b29_5to30_5_pong), .out_c(matrixC29_5), .b_data_valid_ping(b_data_valid_ping_delay29_5), .b_data_valid_pong(b_data_valid_pong_delay29_5), .mode(1'b0)); +processing_element pe29_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_29_6_NC), .in_a_chain(a29_5to29_6), .in_b(b28_6to29_6), .in_c(matrixC28_6), .out_a(out_a_29_6_NC), .out_a_chain(a29_6to29_7), .out_b(b29_6to30_6), .out_b0(b29_6to30_6_ping), .out_b1(b29_6to30_6_pong), .out_c(matrixC29_6), .b_data_valid_ping(b_data_valid_ping_delay29_6), .b_data_valid_pong(b_data_valid_pong_delay29_6), .mode(1'b0)); +processing_element pe29_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_29_7_NC), .in_a_chain(a29_6to29_7), .in_b(b28_7to29_7), .in_c(matrixC28_7), .out_a(out_a_29_7_NC), .out_a_chain(a29_7to29_8), .out_b(b29_7to30_7), .out_b0(b29_7to30_7_ping), .out_b1(b29_7to30_7_pong), .out_c(matrixC29_7), .b_data_valid_ping(b_data_valid_ping_delay29_7), .b_data_valid_pong(b_data_valid_pong_delay29_7), .mode(1'b0)); +processing_element pe29_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_29_8_NC), .in_a_chain(a29_7to29_8), .in_b(b28_8to29_8), .in_c(matrixC28_8), .out_a(out_a_29_8_NC), .out_a_chain(a29_8to29_9), .out_b(b29_8to30_8), .out_b0(b29_8to30_8_ping), .out_b1(b29_8to30_8_pong), .out_c(matrixC29_8), .b_data_valid_ping(b_data_valid_ping_delay29_8), .b_data_valid_pong(b_data_valid_pong_delay29_8), .mode(1'b0)); +processing_element pe29_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_29_9_NC), .in_a_chain(a29_8to29_9), .in_b(b28_9to29_9), .in_c(matrixC28_9), .out_a(out_a_29_9_NC), .out_a_chain(a29_9to29_10), .out_b(b29_9to30_9), .out_b0(b29_9to30_9_ping), .out_b1(b29_9to30_9_pong), .out_c(matrixC29_9), .b_data_valid_ping(b_data_valid_ping_delay29_9), .b_data_valid_pong(b_data_valid_pong_delay29_9), .mode(1'b0)); +processing_element pe29_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_29_10_NC), .in_a_chain(a29_9to29_10), .in_b(b28_10to29_10), .in_c(matrixC28_10), .out_a(out_a_29_10_NC), .out_a_chain(a29_10to29_11), .out_b(b29_10to30_10), .out_b0(b29_10to30_10_ping), .out_b1(b29_10to30_10_pong), .out_c(matrixC29_10), .b_data_valid_ping(b_data_valid_ping_delay29_10), .b_data_valid_pong(b_data_valid_pong_delay29_10), .mode(1'b0)); +processing_element pe29_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_29_11_NC), .in_a_chain(a29_10to29_11), .in_b(b28_11to29_11), .in_c(matrixC28_11), .out_a(out_a_29_11_NC), .out_a_chain(a29_11to29_12), .out_b(b29_11to30_11), .out_b0(b29_11to30_11_ping), .out_b1(b29_11to30_11_pong), .out_c(matrixC29_11), .b_data_valid_ping(b_data_valid_ping_delay29_11), .b_data_valid_pong(b_data_valid_pong_delay29_11), .mode(1'b0)); +processing_element pe29_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_29_12_NC), .in_a_chain(a29_11to29_12), .in_b(b28_12to29_12), .in_c(matrixC28_12), .out_a(out_a_29_12_NC), .out_a_chain(a29_12to29_13), .out_b(b29_12to30_12), .out_b0(b29_12to30_12_ping), .out_b1(b29_12to30_12_pong), .out_c(matrixC29_12), .b_data_valid_ping(b_data_valid_ping_delay29_12), .b_data_valid_pong(b_data_valid_pong_delay29_12), .mode(1'b0)); +processing_element pe29_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_29_13_NC), .in_a_chain(a29_12to29_13), .in_b(b28_13to29_13), .in_c(matrixC28_13), .out_a(out_a_29_13_NC), .out_a_chain(a29_13to29_14), .out_b(b29_13to30_13), .out_b0(b29_13to30_13_ping), .out_b1(b29_13to30_13_pong), .out_c(matrixC29_13), .b_data_valid_ping(b_data_valid_ping_delay29_13), .b_data_valid_pong(b_data_valid_pong_delay29_13), .mode(1'b0)); +processing_element pe29_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_29_14_NC), .in_a_chain(a29_13to29_14), .in_b(b28_14to29_14), .in_c(matrixC28_14), .out_a(out_a_29_14_NC), .out_a_chain(a29_14to29_15), .out_b(b29_14to30_14), .out_b0(b29_14to30_14_ping), .out_b1(b29_14to30_14_pong), .out_c(matrixC29_14), .b_data_valid_ping(b_data_valid_ping_delay29_14), .b_data_valid_pong(b_data_valid_pong_delay29_14), .mode(1'b0)); +processing_element pe29_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_29_15_NC), .in_a_chain(a29_14to29_15), .in_b(b28_15to29_15), .in_c(matrixC28_15), .out_a(out_a_29_15_NC), .out_a_chain(a29_15to29_16), .out_b(b29_15to30_15), .out_b0(b29_15to30_15_ping), .out_b1(b29_15to30_15_pong), .out_c(matrixC29_15), .b_data_valid_ping(b_data_valid_ping_delay29_15), .b_data_valid_pong(b_data_valid_pong_delay29_15), .mode(1'b0)); +processing_element pe29_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_29_16_NC), .in_a_chain(a29_15to29_16), .in_b(b28_16to29_16), .in_c(matrixC28_16), .out_a(out_a_29_16_NC), .out_a_chain(a29_16to29_17), .out_b(b29_16to30_16), .out_b0(b29_16to30_16_ping), .out_b1(b29_16to30_16_pong), .out_c(matrixC29_16), .b_data_valid_ping(b_data_valid_ping_delay29_16), .b_data_valid_pong(b_data_valid_pong_delay29_16), .mode(1'b0)); +processing_element pe29_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_29_17_NC), .in_a_chain(a29_16to29_17), .in_b(b28_17to29_17), .in_c(matrixC28_17), .out_a(out_a_29_17_NC), .out_a_chain(a29_17to29_18), .out_b(b29_17to30_17), .out_b0(b29_17to30_17_ping), .out_b1(b29_17to30_17_pong), .out_c(matrixC29_17), .b_data_valid_ping(b_data_valid_ping_delay29_17), .b_data_valid_pong(b_data_valid_pong_delay29_17), .mode(1'b0)); +processing_element pe29_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_29_18_NC), .in_a_chain(a29_17to29_18), .in_b(b28_18to29_18), .in_c(matrixC28_18), .out_a(out_a_29_18_NC), .out_a_chain(a29_18to29_19), .out_b(b29_18to30_18), .out_b0(b29_18to30_18_ping), .out_b1(b29_18to30_18_pong), .out_c(matrixC29_18), .b_data_valid_ping(b_data_valid_ping_delay29_18), .b_data_valid_pong(b_data_valid_pong_delay29_18), .mode(1'b0)); +processing_element pe29_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay48), .in_a(in_a_29_19_NC), .in_a_chain(a29_18to29_19), .in_b(b28_19to29_19), .in_c(matrixC28_19), .out_a(out_a_29_19_NC), .out_a_chain(a29_19to29_20), .out_b(b29_19to30_19), .out_b0(b29_19to30_19_ping), .out_b1(b29_19to30_19_pong), .out_c(matrixC29_19), .b_data_valid_ping(b_data_valid_ping_delay29_19), .b_data_valid_pong(b_data_valid_pong_delay29_19), .mode(1'b0)); +processing_element pe29_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay49), .in_a(in_a_29_20_NC), .in_a_chain(a29_19to29_20), .in_b(b28_20to29_20), .in_c(matrixC28_20), .out_a(out_a_29_20_NC), .out_a_chain(a29_20to29_21), .out_b(b29_20to30_20), .out_b0(b29_20to30_20_ping), .out_b1(b29_20to30_20_pong), .out_c(matrixC29_20), .b_data_valid_ping(b_data_valid_ping_delay29_20), .b_data_valid_pong(b_data_valid_pong_delay29_20), .mode(1'b0)); +processing_element pe29_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay50), .in_a(in_a_29_21_NC), .in_a_chain(a29_20to29_21), .in_b(b28_21to29_21), .in_c(matrixC28_21), .out_a(out_a_29_21_NC), .out_a_chain(a29_21to29_22), .out_b(b29_21to30_21), .out_b0(b29_21to30_21_ping), .out_b1(b29_21to30_21_pong), .out_c(matrixC29_21), .b_data_valid_ping(b_data_valid_ping_delay29_21), .b_data_valid_pong(b_data_valid_pong_delay29_21), .mode(1'b0)); +processing_element pe29_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay51), .in_a(in_a_29_22_NC), .in_a_chain(a29_21to29_22), .in_b(b28_22to29_22), .in_c(matrixC28_22), .out_a(out_a_29_22_NC), .out_a_chain(a29_22to29_23), .out_b(b29_22to30_22), .out_b0(b29_22to30_22_ping), .out_b1(b29_22to30_22_pong), .out_c(matrixC29_22), .b_data_valid_ping(b_data_valid_ping_delay29_22), .b_data_valid_pong(b_data_valid_pong_delay29_22), .mode(1'b0)); +processing_element pe29_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay52), .in_a(in_a_29_23_NC), .in_a_chain(a29_22to29_23), .in_b(b28_23to29_23), .in_c(matrixC28_23), .out_a(out_a_29_23_NC), .out_a_chain(a29_23to29_24), .out_b(b29_23to30_23), .out_b0(b29_23to30_23_ping), .out_b1(b29_23to30_23_pong), .out_c(matrixC29_23), .b_data_valid_ping(b_data_valid_ping_delay29_23), .b_data_valid_pong(b_data_valid_pong_delay29_23), .mode(1'b0)); +processing_element pe29_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay53), .in_a(in_a_29_24_NC), .in_a_chain(a29_23to29_24), .in_b(b28_24to29_24), .in_c(matrixC28_24), .out_a(out_a_29_24_NC), .out_a_chain(a29_24to29_25), .out_b(b29_24to30_24), .out_b0(b29_24to30_24_ping), .out_b1(b29_24to30_24_pong), .out_c(matrixC29_24), .b_data_valid_ping(b_data_valid_ping_delay29_24), .b_data_valid_pong(b_data_valid_pong_delay29_24), .mode(1'b0)); +processing_element pe29_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay54), .in_a(in_a_29_25_NC), .in_a_chain(a29_24to29_25), .in_b(b28_25to29_25), .in_c(matrixC28_25), .out_a(out_a_29_25_NC), .out_a_chain(a29_25to29_26), .out_b(b29_25to30_25), .out_b0(b29_25to30_25_ping), .out_b1(b29_25to30_25_pong), .out_c(matrixC29_25), .b_data_valid_ping(b_data_valid_ping_delay29_25), .b_data_valid_pong(b_data_valid_pong_delay29_25), .mode(1'b0)); +processing_element pe29_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay55), .in_a(in_a_29_26_NC), .in_a_chain(a29_25to29_26), .in_b(b28_26to29_26), .in_c(matrixC28_26), .out_a(out_a_29_26_NC), .out_a_chain(a29_26to29_27), .out_b(b29_26to30_26), .out_b0(b29_26to30_26_ping), .out_b1(b29_26to30_26_pong), .out_c(matrixC29_26), .b_data_valid_ping(b_data_valid_ping_delay29_26), .b_data_valid_pong(b_data_valid_pong_delay29_26), .mode(1'b0)); +processing_element pe29_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay56), .in_a(in_a_29_27_NC), .in_a_chain(a29_26to29_27), .in_b(b28_27to29_27), .in_c(matrixC28_27), .out_a(out_a_29_27_NC), .out_a_chain(a29_27to29_28), .out_b(b29_27to30_27), .out_b0(b29_27to30_27_ping), .out_b1(b29_27to30_27_pong), .out_c(matrixC29_27), .b_data_valid_ping(b_data_valid_ping_delay29_27), .b_data_valid_pong(b_data_valid_pong_delay29_27), .mode(1'b0)); +processing_element pe29_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay57), .in_a(in_a_29_28_NC), .in_a_chain(a29_27to29_28), .in_b(b28_28to29_28), .in_c(matrixC28_28), .out_a(out_a_29_28_NC), .out_a_chain(a29_28to29_29), .out_b(b29_28to30_28), .out_b0(b29_28to30_28_ping), .out_b1(b29_28to30_28_pong), .out_c(matrixC29_28), .b_data_valid_ping(b_data_valid_ping_delay29_28), .b_data_valid_pong(b_data_valid_pong_delay29_28), .mode(1'b0)); +processing_element pe29_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay58), .in_a(in_a_29_29_NC), .in_a_chain(a29_28to29_29), .in_b(b28_29to29_29), .in_c(matrixC28_29), .out_a(out_a_29_29_NC), .out_a_chain(a29_29to29_30), .out_b(b29_29to30_29), .out_b0(b29_29to30_29_ping), .out_b1(b29_29to30_29_pong), .out_c(matrixC29_29), .b_data_valid_ping(b_data_valid_ping_delay29_29), .b_data_valid_pong(b_data_valid_pong_delay29_29), .mode(1'b0)); +processing_element pe29_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay59), .in_a(in_a_29_30_NC), .in_a_chain(a29_29to29_30), .in_b(b28_30to29_30), .in_c(matrixC28_30), .out_a(out_a_29_30_NC), .out_a_chain(a29_30to29_31), .out_b(b29_30to30_30), .out_b0(b29_30to30_30_ping), .out_b1(b29_30to30_30_pong), .out_c(matrixC29_30), .b_data_valid_ping(b_data_valid_ping_delay29_30), .b_data_valid_pong(b_data_valid_pong_delay29_30), .mode(1'b0)); +processing_element pe29_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay60), .in_a(in_a_29_31_NC), .in_a_chain(a29_30to29_31), .in_b(b28_31to29_31), .in_c(matrixC28_31), .out_a(out_a_29_31_NC), .out_a_chain(a29_31to29_32), .out_b(b29_31to30_31), .out_b0(b29_31to30_31_ping), .out_b1(b29_31to30_31_pong), .out_c(matrixC29_31), .b_data_valid_ping(b_data_valid_ping_delay29_31), .b_data_valid_pong(b_data_valid_pong_delay29_31), .mode(1'b0)); +processing_element pe30_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(a30), .in_a_chain(in_a_chain_30_0_NC), .in_b(b29_0to30_0), .in_c(matrixC29_0), .out_a(out_a_30_0_NC), .out_a_chain(a30_0to30_1), .out_b(b30_0to31_0), .out_b0(b30_0to31_0_ping), .out_b1(b30_0to31_0_pong), .out_c(matrixC30_0), .b_data_valid_ping(b_data_valid_ping_delay30_0), .b_data_valid_pong(b_data_valid_pong_delay30_0), .mode(1'b1)); +processing_element pe30_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(in_a_30_1_NC), .in_a_chain(a30_0to30_1), .in_b(b29_1to30_1), .in_c(matrixC29_1), .out_a(out_a_30_1_NC), .out_a_chain(a30_1to30_2), .out_b(b30_1to31_1), .out_b0(b30_1to31_1_ping), .out_b1(b30_1to31_1_pong), .out_c(matrixC30_1), .b_data_valid_ping(b_data_valid_ping_delay30_1), .b_data_valid_pong(b_data_valid_pong_delay30_1), .mode(1'b0)); +processing_element pe30_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_30_2_NC), .in_a_chain(a30_1to30_2), .in_b(b29_2to30_2), .in_c(matrixC29_2), .out_a(out_a_30_2_NC), .out_a_chain(a30_2to30_3), .out_b(b30_2to31_2), .out_b0(b30_2to31_2_ping), .out_b1(b30_2to31_2_pong), .out_c(matrixC30_2), .b_data_valid_ping(b_data_valid_ping_delay30_2), .b_data_valid_pong(b_data_valid_pong_delay30_2), .mode(1'b0)); +processing_element pe30_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_30_3_NC), .in_a_chain(a30_2to30_3), .in_b(b29_3to30_3), .in_c(matrixC29_3), .out_a(out_a_30_3_NC), .out_a_chain(a30_3to30_4), .out_b(b30_3to31_3), .out_b0(b30_3to31_3_ping), .out_b1(b30_3to31_3_pong), .out_c(matrixC30_3), .b_data_valid_ping(b_data_valid_ping_delay30_3), .b_data_valid_pong(b_data_valid_pong_delay30_3), .mode(1'b0)); +processing_element pe30_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_30_4_NC), .in_a_chain(a30_3to30_4), .in_b(b29_4to30_4), .in_c(matrixC29_4), .out_a(out_a_30_4_NC), .out_a_chain(a30_4to30_5), .out_b(b30_4to31_4), .out_b0(b30_4to31_4_ping), .out_b1(b30_4to31_4_pong), .out_c(matrixC30_4), .b_data_valid_ping(b_data_valid_ping_delay30_4), .b_data_valid_pong(b_data_valid_pong_delay30_4), .mode(1'b0)); +processing_element pe30_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_30_5_NC), .in_a_chain(a30_4to30_5), .in_b(b29_5to30_5), .in_c(matrixC29_5), .out_a(out_a_30_5_NC), .out_a_chain(a30_5to30_6), .out_b(b30_5to31_5), .out_b0(b30_5to31_5_ping), .out_b1(b30_5to31_5_pong), .out_c(matrixC30_5), .b_data_valid_ping(b_data_valid_ping_delay30_5), .b_data_valid_pong(b_data_valid_pong_delay30_5), .mode(1'b0)); +processing_element pe30_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_30_6_NC), .in_a_chain(a30_5to30_6), .in_b(b29_6to30_6), .in_c(matrixC29_6), .out_a(out_a_30_6_NC), .out_a_chain(a30_6to30_7), .out_b(b30_6to31_6), .out_b0(b30_6to31_6_ping), .out_b1(b30_6to31_6_pong), .out_c(matrixC30_6), .b_data_valid_ping(b_data_valid_ping_delay30_6), .b_data_valid_pong(b_data_valid_pong_delay30_6), .mode(1'b0)); +processing_element pe30_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_30_7_NC), .in_a_chain(a30_6to30_7), .in_b(b29_7to30_7), .in_c(matrixC29_7), .out_a(out_a_30_7_NC), .out_a_chain(a30_7to30_8), .out_b(b30_7to31_7), .out_b0(b30_7to31_7_ping), .out_b1(b30_7to31_7_pong), .out_c(matrixC30_7), .b_data_valid_ping(b_data_valid_ping_delay30_7), .b_data_valid_pong(b_data_valid_pong_delay30_7), .mode(1'b0)); +processing_element pe30_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_30_8_NC), .in_a_chain(a30_7to30_8), .in_b(b29_8to30_8), .in_c(matrixC29_8), .out_a(out_a_30_8_NC), .out_a_chain(a30_8to30_9), .out_b(b30_8to31_8), .out_b0(b30_8to31_8_ping), .out_b1(b30_8to31_8_pong), .out_c(matrixC30_8), .b_data_valid_ping(b_data_valid_ping_delay30_8), .b_data_valid_pong(b_data_valid_pong_delay30_8), .mode(1'b0)); +processing_element pe30_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_30_9_NC), .in_a_chain(a30_8to30_9), .in_b(b29_9to30_9), .in_c(matrixC29_9), .out_a(out_a_30_9_NC), .out_a_chain(a30_9to30_10), .out_b(b30_9to31_9), .out_b0(b30_9to31_9_ping), .out_b1(b30_9to31_9_pong), .out_c(matrixC30_9), .b_data_valid_ping(b_data_valid_ping_delay30_9), .b_data_valid_pong(b_data_valid_pong_delay30_9), .mode(1'b0)); +processing_element pe30_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_30_10_NC), .in_a_chain(a30_9to30_10), .in_b(b29_10to30_10), .in_c(matrixC29_10), .out_a(out_a_30_10_NC), .out_a_chain(a30_10to30_11), .out_b(b30_10to31_10), .out_b0(b30_10to31_10_ping), .out_b1(b30_10to31_10_pong), .out_c(matrixC30_10), .b_data_valid_ping(b_data_valid_ping_delay30_10), .b_data_valid_pong(b_data_valid_pong_delay30_10), .mode(1'b0)); +processing_element pe30_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_30_11_NC), .in_a_chain(a30_10to30_11), .in_b(b29_11to30_11), .in_c(matrixC29_11), .out_a(out_a_30_11_NC), .out_a_chain(a30_11to30_12), .out_b(b30_11to31_11), .out_b0(b30_11to31_11_ping), .out_b1(b30_11to31_11_pong), .out_c(matrixC30_11), .b_data_valid_ping(b_data_valid_ping_delay30_11), .b_data_valid_pong(b_data_valid_pong_delay30_11), .mode(1'b0)); +processing_element pe30_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_30_12_NC), .in_a_chain(a30_11to30_12), .in_b(b29_12to30_12), .in_c(matrixC29_12), .out_a(out_a_30_12_NC), .out_a_chain(a30_12to30_13), .out_b(b30_12to31_12), .out_b0(b30_12to31_12_ping), .out_b1(b30_12to31_12_pong), .out_c(matrixC30_12), .b_data_valid_ping(b_data_valid_ping_delay30_12), .b_data_valid_pong(b_data_valid_pong_delay30_12), .mode(1'b0)); +processing_element pe30_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_30_13_NC), .in_a_chain(a30_12to30_13), .in_b(b29_13to30_13), .in_c(matrixC29_13), .out_a(out_a_30_13_NC), .out_a_chain(a30_13to30_14), .out_b(b30_13to31_13), .out_b0(b30_13to31_13_ping), .out_b1(b30_13to31_13_pong), .out_c(matrixC30_13), .b_data_valid_ping(b_data_valid_ping_delay30_13), .b_data_valid_pong(b_data_valid_pong_delay30_13), .mode(1'b0)); +processing_element pe30_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_30_14_NC), .in_a_chain(a30_13to30_14), .in_b(b29_14to30_14), .in_c(matrixC29_14), .out_a(out_a_30_14_NC), .out_a_chain(a30_14to30_15), .out_b(b30_14to31_14), .out_b0(b30_14to31_14_ping), .out_b1(b30_14to31_14_pong), .out_c(matrixC30_14), .b_data_valid_ping(b_data_valid_ping_delay30_14), .b_data_valid_pong(b_data_valid_pong_delay30_14), .mode(1'b0)); +processing_element pe30_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_30_15_NC), .in_a_chain(a30_14to30_15), .in_b(b29_15to30_15), .in_c(matrixC29_15), .out_a(out_a_30_15_NC), .out_a_chain(a30_15to30_16), .out_b(b30_15to31_15), .out_b0(b30_15to31_15_ping), .out_b1(b30_15to31_15_pong), .out_c(matrixC30_15), .b_data_valid_ping(b_data_valid_ping_delay30_15), .b_data_valid_pong(b_data_valid_pong_delay30_15), .mode(1'b0)); +processing_element pe30_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_30_16_NC), .in_a_chain(a30_15to30_16), .in_b(b29_16to30_16), .in_c(matrixC29_16), .out_a(out_a_30_16_NC), .out_a_chain(a30_16to30_17), .out_b(b30_16to31_16), .out_b0(b30_16to31_16_ping), .out_b1(b30_16to31_16_pong), .out_c(matrixC30_16), .b_data_valid_ping(b_data_valid_ping_delay30_16), .b_data_valid_pong(b_data_valid_pong_delay30_16), .mode(1'b0)); +processing_element pe30_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_30_17_NC), .in_a_chain(a30_16to30_17), .in_b(b29_17to30_17), .in_c(matrixC29_17), .out_a(out_a_30_17_NC), .out_a_chain(a30_17to30_18), .out_b(b30_17to31_17), .out_b0(b30_17to31_17_ping), .out_b1(b30_17to31_17_pong), .out_c(matrixC30_17), .b_data_valid_ping(b_data_valid_ping_delay30_17), .b_data_valid_pong(b_data_valid_pong_delay30_17), .mode(1'b0)); +processing_element pe30_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay48), .in_a(in_a_30_18_NC), .in_a_chain(a30_17to30_18), .in_b(b29_18to30_18), .in_c(matrixC29_18), .out_a(out_a_30_18_NC), .out_a_chain(a30_18to30_19), .out_b(b30_18to31_18), .out_b0(b30_18to31_18_ping), .out_b1(b30_18to31_18_pong), .out_c(matrixC30_18), .b_data_valid_ping(b_data_valid_ping_delay30_18), .b_data_valid_pong(b_data_valid_pong_delay30_18), .mode(1'b0)); +processing_element pe30_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay49), .in_a(in_a_30_19_NC), .in_a_chain(a30_18to30_19), .in_b(b29_19to30_19), .in_c(matrixC29_19), .out_a(out_a_30_19_NC), .out_a_chain(a30_19to30_20), .out_b(b30_19to31_19), .out_b0(b30_19to31_19_ping), .out_b1(b30_19to31_19_pong), .out_c(matrixC30_19), .b_data_valid_ping(b_data_valid_ping_delay30_19), .b_data_valid_pong(b_data_valid_pong_delay30_19), .mode(1'b0)); +processing_element pe30_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay50), .in_a(in_a_30_20_NC), .in_a_chain(a30_19to30_20), .in_b(b29_20to30_20), .in_c(matrixC29_20), .out_a(out_a_30_20_NC), .out_a_chain(a30_20to30_21), .out_b(b30_20to31_20), .out_b0(b30_20to31_20_ping), .out_b1(b30_20to31_20_pong), .out_c(matrixC30_20), .b_data_valid_ping(b_data_valid_ping_delay30_20), .b_data_valid_pong(b_data_valid_pong_delay30_20), .mode(1'b0)); +processing_element pe30_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay51), .in_a(in_a_30_21_NC), .in_a_chain(a30_20to30_21), .in_b(b29_21to30_21), .in_c(matrixC29_21), .out_a(out_a_30_21_NC), .out_a_chain(a30_21to30_22), .out_b(b30_21to31_21), .out_b0(b30_21to31_21_ping), .out_b1(b30_21to31_21_pong), .out_c(matrixC30_21), .b_data_valid_ping(b_data_valid_ping_delay30_21), .b_data_valid_pong(b_data_valid_pong_delay30_21), .mode(1'b0)); +processing_element pe30_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay52), .in_a(in_a_30_22_NC), .in_a_chain(a30_21to30_22), .in_b(b29_22to30_22), .in_c(matrixC29_22), .out_a(out_a_30_22_NC), .out_a_chain(a30_22to30_23), .out_b(b30_22to31_22), .out_b0(b30_22to31_22_ping), .out_b1(b30_22to31_22_pong), .out_c(matrixC30_22), .b_data_valid_ping(b_data_valid_ping_delay30_22), .b_data_valid_pong(b_data_valid_pong_delay30_22), .mode(1'b0)); +processing_element pe30_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay53), .in_a(in_a_30_23_NC), .in_a_chain(a30_22to30_23), .in_b(b29_23to30_23), .in_c(matrixC29_23), .out_a(out_a_30_23_NC), .out_a_chain(a30_23to30_24), .out_b(b30_23to31_23), .out_b0(b30_23to31_23_ping), .out_b1(b30_23to31_23_pong), .out_c(matrixC30_23), .b_data_valid_ping(b_data_valid_ping_delay30_23), .b_data_valid_pong(b_data_valid_pong_delay30_23), .mode(1'b0)); +processing_element pe30_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay54), .in_a(in_a_30_24_NC), .in_a_chain(a30_23to30_24), .in_b(b29_24to30_24), .in_c(matrixC29_24), .out_a(out_a_30_24_NC), .out_a_chain(a30_24to30_25), .out_b(b30_24to31_24), .out_b0(b30_24to31_24_ping), .out_b1(b30_24to31_24_pong), .out_c(matrixC30_24), .b_data_valid_ping(b_data_valid_ping_delay30_24), .b_data_valid_pong(b_data_valid_pong_delay30_24), .mode(1'b0)); +processing_element pe30_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay55), .in_a(in_a_30_25_NC), .in_a_chain(a30_24to30_25), .in_b(b29_25to30_25), .in_c(matrixC29_25), .out_a(out_a_30_25_NC), .out_a_chain(a30_25to30_26), .out_b(b30_25to31_25), .out_b0(b30_25to31_25_ping), .out_b1(b30_25to31_25_pong), .out_c(matrixC30_25), .b_data_valid_ping(b_data_valid_ping_delay30_25), .b_data_valid_pong(b_data_valid_pong_delay30_25), .mode(1'b0)); +processing_element pe30_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay56), .in_a(in_a_30_26_NC), .in_a_chain(a30_25to30_26), .in_b(b29_26to30_26), .in_c(matrixC29_26), .out_a(out_a_30_26_NC), .out_a_chain(a30_26to30_27), .out_b(b30_26to31_26), .out_b0(b30_26to31_26_ping), .out_b1(b30_26to31_26_pong), .out_c(matrixC30_26), .b_data_valid_ping(b_data_valid_ping_delay30_26), .b_data_valid_pong(b_data_valid_pong_delay30_26), .mode(1'b0)); +processing_element pe30_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay57), .in_a(in_a_30_27_NC), .in_a_chain(a30_26to30_27), .in_b(b29_27to30_27), .in_c(matrixC29_27), .out_a(out_a_30_27_NC), .out_a_chain(a30_27to30_28), .out_b(b30_27to31_27), .out_b0(b30_27to31_27_ping), .out_b1(b30_27to31_27_pong), .out_c(matrixC30_27), .b_data_valid_ping(b_data_valid_ping_delay30_27), .b_data_valid_pong(b_data_valid_pong_delay30_27), .mode(1'b0)); +processing_element pe30_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay58), .in_a(in_a_30_28_NC), .in_a_chain(a30_27to30_28), .in_b(b29_28to30_28), .in_c(matrixC29_28), .out_a(out_a_30_28_NC), .out_a_chain(a30_28to30_29), .out_b(b30_28to31_28), .out_b0(b30_28to31_28_ping), .out_b1(b30_28to31_28_pong), .out_c(matrixC30_28), .b_data_valid_ping(b_data_valid_ping_delay30_28), .b_data_valid_pong(b_data_valid_pong_delay30_28), .mode(1'b0)); +processing_element pe30_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay59), .in_a(in_a_30_29_NC), .in_a_chain(a30_28to30_29), .in_b(b29_29to30_29), .in_c(matrixC29_29), .out_a(out_a_30_29_NC), .out_a_chain(a30_29to30_30), .out_b(b30_29to31_29), .out_b0(b30_29to31_29_ping), .out_b1(b30_29to31_29_pong), .out_c(matrixC30_29), .b_data_valid_ping(b_data_valid_ping_delay30_29), .b_data_valid_pong(b_data_valid_pong_delay30_29), .mode(1'b0)); +processing_element pe30_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay60), .in_a(in_a_30_30_NC), .in_a_chain(a30_29to30_30), .in_b(b29_30to30_30), .in_c(matrixC29_30), .out_a(out_a_30_30_NC), .out_a_chain(a30_30to30_31), .out_b(b30_30to31_30), .out_b0(b30_30to31_30_ping), .out_b1(b30_30to31_30_pong), .out_c(matrixC30_30), .b_data_valid_ping(b_data_valid_ping_delay30_30), .b_data_valid_pong(b_data_valid_pong_delay30_30), .mode(1'b0)); +processing_element pe30_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay61), .in_a(in_a_30_31_NC), .in_a_chain(a30_30to30_31), .in_b(b29_31to30_31), .in_c(matrixC29_31), .out_a(out_a_30_31_NC), .out_a_chain(a30_31to30_32), .out_b(b30_31to31_31), .out_b0(b30_31to31_31_ping), .out_b1(b30_31to31_31_pong), .out_c(matrixC30_31), .b_data_valid_ping(b_data_valid_ping_delay30_31), .b_data_valid_pong(b_data_valid_pong_delay30_31), .mode(1'b0)); +processing_element pe31_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay31), .in_a(a31), .in_a_chain(in_a_chain_31_0_NC), .in_b(b30_0to31_0), .in_c(matrixC30_0), .out_a(out_a_31_0_NC), .out_a_chain(a31_0to31_1), .out_b(b31_0to32_0), .out_b0(b31_0to32_0_ping), .out_b1(b31_0to32_0_pong), .out_c(matrixC31_0), .b_data_valid_ping(b_data_valid_ping_delay31_0), .b_data_valid_pong(b_data_valid_pong_delay31_0), .mode(1'b1)); +processing_element pe31_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay32), .in_a(in_a_31_1_NC), .in_a_chain(a31_0to31_1), .in_b(b30_1to31_1), .in_c(matrixC30_1), .out_a(out_a_31_1_NC), .out_a_chain(a31_1to31_2), .out_b(b31_1to32_1), .out_b0(b31_1to32_1_ping), .out_b1(b31_1to32_1_pong), .out_c(matrixC31_1), .b_data_valid_ping(b_data_valid_ping_delay31_1), .b_data_valid_pong(b_data_valid_pong_delay31_1), .mode(1'b0)); +processing_element pe31_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay33), .in_a(in_a_31_2_NC), .in_a_chain(a31_1to31_2), .in_b(b30_2to31_2), .in_c(matrixC30_2), .out_a(out_a_31_2_NC), .out_a_chain(a31_2to31_3), .out_b(b31_2to32_2), .out_b0(b31_2to32_2_ping), .out_b1(b31_2to32_2_pong), .out_c(matrixC31_2), .b_data_valid_ping(b_data_valid_ping_delay31_2), .b_data_valid_pong(b_data_valid_pong_delay31_2), .mode(1'b0)); +processing_element pe31_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay34), .in_a(in_a_31_3_NC), .in_a_chain(a31_2to31_3), .in_b(b30_3to31_3), .in_c(matrixC30_3), .out_a(out_a_31_3_NC), .out_a_chain(a31_3to31_4), .out_b(b31_3to32_3), .out_b0(b31_3to32_3_ping), .out_b1(b31_3to32_3_pong), .out_c(matrixC31_3), .b_data_valid_ping(b_data_valid_ping_delay31_3), .b_data_valid_pong(b_data_valid_pong_delay31_3), .mode(1'b0)); +processing_element pe31_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay35), .in_a(in_a_31_4_NC), .in_a_chain(a31_3to31_4), .in_b(b30_4to31_4), .in_c(matrixC30_4), .out_a(out_a_31_4_NC), .out_a_chain(a31_4to31_5), .out_b(b31_4to32_4), .out_b0(b31_4to32_4_ping), .out_b1(b31_4to32_4_pong), .out_c(matrixC31_4), .b_data_valid_ping(b_data_valid_ping_delay31_4), .b_data_valid_pong(b_data_valid_pong_delay31_4), .mode(1'b0)); +processing_element pe31_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay36), .in_a(in_a_31_5_NC), .in_a_chain(a31_4to31_5), .in_b(b30_5to31_5), .in_c(matrixC30_5), .out_a(out_a_31_5_NC), .out_a_chain(a31_5to31_6), .out_b(b31_5to32_5), .out_b0(b31_5to32_5_ping), .out_b1(b31_5to32_5_pong), .out_c(matrixC31_5), .b_data_valid_ping(b_data_valid_ping_delay31_5), .b_data_valid_pong(b_data_valid_pong_delay31_5), .mode(1'b0)); +processing_element pe31_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay37), .in_a(in_a_31_6_NC), .in_a_chain(a31_5to31_6), .in_b(b30_6to31_6), .in_c(matrixC30_6), .out_a(out_a_31_6_NC), .out_a_chain(a31_6to31_7), .out_b(b31_6to32_6), .out_b0(b31_6to32_6_ping), .out_b1(b31_6to32_6_pong), .out_c(matrixC31_6), .b_data_valid_ping(b_data_valid_ping_delay31_6), .b_data_valid_pong(b_data_valid_pong_delay31_6), .mode(1'b0)); +processing_element pe31_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay38), .in_a(in_a_31_7_NC), .in_a_chain(a31_6to31_7), .in_b(b30_7to31_7), .in_c(matrixC30_7), .out_a(out_a_31_7_NC), .out_a_chain(a31_7to31_8), .out_b(b31_7to32_7), .out_b0(b31_7to32_7_ping), .out_b1(b31_7to32_7_pong), .out_c(matrixC31_7), .b_data_valid_ping(b_data_valid_ping_delay31_7), .b_data_valid_pong(b_data_valid_pong_delay31_7), .mode(1'b0)); +processing_element pe31_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay39), .in_a(in_a_31_8_NC), .in_a_chain(a31_7to31_8), .in_b(b30_8to31_8), .in_c(matrixC30_8), .out_a(out_a_31_8_NC), .out_a_chain(a31_8to31_9), .out_b(b31_8to32_8), .out_b0(b31_8to32_8_ping), .out_b1(b31_8to32_8_pong), .out_c(matrixC31_8), .b_data_valid_ping(b_data_valid_ping_delay31_8), .b_data_valid_pong(b_data_valid_pong_delay31_8), .mode(1'b0)); +processing_element pe31_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay40), .in_a(in_a_31_9_NC), .in_a_chain(a31_8to31_9), .in_b(b30_9to31_9), .in_c(matrixC30_9), .out_a(out_a_31_9_NC), .out_a_chain(a31_9to31_10), .out_b(b31_9to32_9), .out_b0(b31_9to32_9_ping), .out_b1(b31_9to32_9_pong), .out_c(matrixC31_9), .b_data_valid_ping(b_data_valid_ping_delay31_9), .b_data_valid_pong(b_data_valid_pong_delay31_9), .mode(1'b0)); +processing_element pe31_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay41), .in_a(in_a_31_10_NC), .in_a_chain(a31_9to31_10), .in_b(b30_10to31_10), .in_c(matrixC30_10), .out_a(out_a_31_10_NC), .out_a_chain(a31_10to31_11), .out_b(b31_10to32_10), .out_b0(b31_10to32_10_ping), .out_b1(b31_10to32_10_pong), .out_c(matrixC31_10), .b_data_valid_ping(b_data_valid_ping_delay31_10), .b_data_valid_pong(b_data_valid_pong_delay31_10), .mode(1'b0)); +processing_element pe31_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay42), .in_a(in_a_31_11_NC), .in_a_chain(a31_10to31_11), .in_b(b30_11to31_11), .in_c(matrixC30_11), .out_a(out_a_31_11_NC), .out_a_chain(a31_11to31_12), .out_b(b31_11to32_11), .out_b0(b31_11to32_11_ping), .out_b1(b31_11to32_11_pong), .out_c(matrixC31_11), .b_data_valid_ping(b_data_valid_ping_delay31_11), .b_data_valid_pong(b_data_valid_pong_delay31_11), .mode(1'b0)); +processing_element pe31_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay43), .in_a(in_a_31_12_NC), .in_a_chain(a31_11to31_12), .in_b(b30_12to31_12), .in_c(matrixC30_12), .out_a(out_a_31_12_NC), .out_a_chain(a31_12to31_13), .out_b(b31_12to32_12), .out_b0(b31_12to32_12_ping), .out_b1(b31_12to32_12_pong), .out_c(matrixC31_12), .b_data_valid_ping(b_data_valid_ping_delay31_12), .b_data_valid_pong(b_data_valid_pong_delay31_12), .mode(1'b0)); +processing_element pe31_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay44), .in_a(in_a_31_13_NC), .in_a_chain(a31_12to31_13), .in_b(b30_13to31_13), .in_c(matrixC30_13), .out_a(out_a_31_13_NC), .out_a_chain(a31_13to31_14), .out_b(b31_13to32_13), .out_b0(b31_13to32_13_ping), .out_b1(b31_13to32_13_pong), .out_c(matrixC31_13), .b_data_valid_ping(b_data_valid_ping_delay31_13), .b_data_valid_pong(b_data_valid_pong_delay31_13), .mode(1'b0)); +processing_element pe31_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay45), .in_a(in_a_31_14_NC), .in_a_chain(a31_13to31_14), .in_b(b30_14to31_14), .in_c(matrixC30_14), .out_a(out_a_31_14_NC), .out_a_chain(a31_14to31_15), .out_b(b31_14to32_14), .out_b0(b31_14to32_14_ping), .out_b1(b31_14to32_14_pong), .out_c(matrixC31_14), .b_data_valid_ping(b_data_valid_ping_delay31_14), .b_data_valid_pong(b_data_valid_pong_delay31_14), .mode(1'b0)); +processing_element pe31_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay46), .in_a(in_a_31_15_NC), .in_a_chain(a31_14to31_15), .in_b(b30_15to31_15), .in_c(matrixC30_15), .out_a(out_a_31_15_NC), .out_a_chain(a31_15to31_16), .out_b(b31_15to32_15), .out_b0(b31_15to32_15_ping), .out_b1(b31_15to32_15_pong), .out_c(matrixC31_15), .b_data_valid_ping(b_data_valid_ping_delay31_15), .b_data_valid_pong(b_data_valid_pong_delay31_15), .mode(1'b0)); +processing_element pe31_16(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay47), .in_a(in_a_31_16_NC), .in_a_chain(a31_15to31_16), .in_b(b30_16to31_16), .in_c(matrixC30_16), .out_a(out_a_31_16_NC), .out_a_chain(a31_16to31_17), .out_b(b31_16to32_16), .out_b0(b31_16to32_16_ping), .out_b1(b31_16to32_16_pong), .out_c(matrixC31_16), .b_data_valid_ping(b_data_valid_ping_delay31_16), .b_data_valid_pong(b_data_valid_pong_delay31_16), .mode(1'b0)); +processing_element pe31_17(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay48), .in_a(in_a_31_17_NC), .in_a_chain(a31_16to31_17), .in_b(b30_17to31_17), .in_c(matrixC30_17), .out_a(out_a_31_17_NC), .out_a_chain(a31_17to31_18), .out_b(b31_17to32_17), .out_b0(b31_17to32_17_ping), .out_b1(b31_17to32_17_pong), .out_c(matrixC31_17), .b_data_valid_ping(b_data_valid_ping_delay31_17), .b_data_valid_pong(b_data_valid_pong_delay31_17), .mode(1'b0)); +processing_element pe31_18(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay49), .in_a(in_a_31_18_NC), .in_a_chain(a31_17to31_18), .in_b(b30_18to31_18), .in_c(matrixC30_18), .out_a(out_a_31_18_NC), .out_a_chain(a31_18to31_19), .out_b(b31_18to32_18), .out_b0(b31_18to32_18_ping), .out_b1(b31_18to32_18_pong), .out_c(matrixC31_18), .b_data_valid_ping(b_data_valid_ping_delay31_18), .b_data_valid_pong(b_data_valid_pong_delay31_18), .mode(1'b0)); +processing_element pe31_19(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay50), .in_a(in_a_31_19_NC), .in_a_chain(a31_18to31_19), .in_b(b30_19to31_19), .in_c(matrixC30_19), .out_a(out_a_31_19_NC), .out_a_chain(a31_19to31_20), .out_b(b31_19to32_19), .out_b0(b31_19to32_19_ping), .out_b1(b31_19to32_19_pong), .out_c(matrixC31_19), .b_data_valid_ping(b_data_valid_ping_delay31_19), .b_data_valid_pong(b_data_valid_pong_delay31_19), .mode(1'b0)); +processing_element pe31_20(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay51), .in_a(in_a_31_20_NC), .in_a_chain(a31_19to31_20), .in_b(b30_20to31_20), .in_c(matrixC30_20), .out_a(out_a_31_20_NC), .out_a_chain(a31_20to31_21), .out_b(b31_20to32_20), .out_b0(b31_20to32_20_ping), .out_b1(b31_20to32_20_pong), .out_c(matrixC31_20), .b_data_valid_ping(b_data_valid_ping_delay31_20), .b_data_valid_pong(b_data_valid_pong_delay31_20), .mode(1'b0)); +processing_element pe31_21(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay52), .in_a(in_a_31_21_NC), .in_a_chain(a31_20to31_21), .in_b(b30_21to31_21), .in_c(matrixC30_21), .out_a(out_a_31_21_NC), .out_a_chain(a31_21to31_22), .out_b(b31_21to32_21), .out_b0(b31_21to32_21_ping), .out_b1(b31_21to32_21_pong), .out_c(matrixC31_21), .b_data_valid_ping(b_data_valid_ping_delay31_21), .b_data_valid_pong(b_data_valid_pong_delay31_21), .mode(1'b0)); +processing_element pe31_22(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay53), .in_a(in_a_31_22_NC), .in_a_chain(a31_21to31_22), .in_b(b30_22to31_22), .in_c(matrixC30_22), .out_a(out_a_31_22_NC), .out_a_chain(a31_22to31_23), .out_b(b31_22to32_22), .out_b0(b31_22to32_22_ping), .out_b1(b31_22to32_22_pong), .out_c(matrixC31_22), .b_data_valid_ping(b_data_valid_ping_delay31_22), .b_data_valid_pong(b_data_valid_pong_delay31_22), .mode(1'b0)); +processing_element pe31_23(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay54), .in_a(in_a_31_23_NC), .in_a_chain(a31_22to31_23), .in_b(b30_23to31_23), .in_c(matrixC30_23), .out_a(out_a_31_23_NC), .out_a_chain(a31_23to31_24), .out_b(b31_23to32_23), .out_b0(b31_23to32_23_ping), .out_b1(b31_23to32_23_pong), .out_c(matrixC31_23), .b_data_valid_ping(b_data_valid_ping_delay31_23), .b_data_valid_pong(b_data_valid_pong_delay31_23), .mode(1'b0)); +processing_element pe31_24(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay55), .in_a(in_a_31_24_NC), .in_a_chain(a31_23to31_24), .in_b(b30_24to31_24), .in_c(matrixC30_24), .out_a(out_a_31_24_NC), .out_a_chain(a31_24to31_25), .out_b(b31_24to32_24), .out_b0(b31_24to32_24_ping), .out_b1(b31_24to32_24_pong), .out_c(matrixC31_24), .b_data_valid_ping(b_data_valid_ping_delay31_24), .b_data_valid_pong(b_data_valid_pong_delay31_24), .mode(1'b0)); +processing_element pe31_25(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay56), .in_a(in_a_31_25_NC), .in_a_chain(a31_24to31_25), .in_b(b30_25to31_25), .in_c(matrixC30_25), .out_a(out_a_31_25_NC), .out_a_chain(a31_25to31_26), .out_b(b31_25to32_25), .out_b0(b31_25to32_25_ping), .out_b1(b31_25to32_25_pong), .out_c(matrixC31_25), .b_data_valid_ping(b_data_valid_ping_delay31_25), .b_data_valid_pong(b_data_valid_pong_delay31_25), .mode(1'b0)); +processing_element pe31_26(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay57), .in_a(in_a_31_26_NC), .in_a_chain(a31_25to31_26), .in_b(b30_26to31_26), .in_c(matrixC30_26), .out_a(out_a_31_26_NC), .out_a_chain(a31_26to31_27), .out_b(b31_26to32_26), .out_b0(b31_26to32_26_ping), .out_b1(b31_26to32_26_pong), .out_c(matrixC31_26), .b_data_valid_ping(b_data_valid_ping_delay31_26), .b_data_valid_pong(b_data_valid_pong_delay31_26), .mode(1'b0)); +processing_element pe31_27(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay58), .in_a(in_a_31_27_NC), .in_a_chain(a31_26to31_27), .in_b(b30_27to31_27), .in_c(matrixC30_27), .out_a(out_a_31_27_NC), .out_a_chain(a31_27to31_28), .out_b(b31_27to32_27), .out_b0(b31_27to32_27_ping), .out_b1(b31_27to32_27_pong), .out_c(matrixC31_27), .b_data_valid_ping(b_data_valid_ping_delay31_27), .b_data_valid_pong(b_data_valid_pong_delay31_27), .mode(1'b0)); +processing_element pe31_28(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay59), .in_a(in_a_31_28_NC), .in_a_chain(a31_27to31_28), .in_b(b30_28to31_28), .in_c(matrixC30_28), .out_a(out_a_31_28_NC), .out_a_chain(a31_28to31_29), .out_b(b31_28to32_28), .out_b0(b31_28to32_28_ping), .out_b1(b31_28to32_28_pong), .out_c(matrixC31_28), .b_data_valid_ping(b_data_valid_ping_delay31_28), .b_data_valid_pong(b_data_valid_pong_delay31_28), .mode(1'b0)); +processing_element pe31_29(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay60), .in_a(in_a_31_29_NC), .in_a_chain(a31_28to31_29), .in_b(b30_29to31_29), .in_c(matrixC30_29), .out_a(out_a_31_29_NC), .out_a_chain(a31_29to31_30), .out_b(b31_29to32_29), .out_b0(b31_29to32_29_ping), .out_b1(b31_29to32_29_pong), .out_c(matrixC31_29), .b_data_valid_ping(b_data_valid_ping_delay31_29), .b_data_valid_pong(b_data_valid_pong_delay31_29), .mode(1'b0)); +processing_element pe31_30(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay61), .in_a(in_a_31_30_NC), .in_a_chain(a31_29to31_30), .in_b(b30_30to31_30), .in_c(matrixC30_30), .out_a(out_a_31_30_NC), .out_a_chain(a31_30to31_31), .out_b(b31_30to32_30), .out_b0(b31_30to32_30_ping), .out_b1(b31_30to32_30_pong), .out_c(matrixC31_30), .b_data_valid_ping(b_data_valid_ping_delay31_30), .b_data_valid_pong(b_data_valid_pong_delay31_30), .mode(1'b0)); +processing_element pe31_31(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay62), .in_a(in_a_31_31_NC), .in_a_chain(a31_30to31_31), .in_b(b30_31to31_31), .in_c(matrixC30_31), .out_a(out_a_31_31_NC), .out_a_chain(a31_31to31_32), .out_b(b31_31to32_31), .out_b0(b31_31to32_31_ping), .out_b1(b31_31to32_31_pong), .out_c(matrixC31_31), .b_data_valid_ping(b_data_valid_ping_delay31_31), .b_data_valid_pong(b_data_valid_pong_delay31_31), .mode(1'b0)); + +//assign a_data_out = {a31_31to31_32, a30_31to30_32, a29_31to29_32, a28_31to28_32, a27_31to27_32, a26_31to26_32, a25_31to25_32, a24_31to24_32, a23_31to23_32, a22_31to22_32, a21_31to21_32, a20_31to20_32, a19_31to19_32, a18_31to18_32, a17_31to17_32, a16_31to16_32, a15_31to15_32, a14_31to14_32, a13_31to13_32, a12_31to12_32, a11_31to11_32, a10_31to10_32, a9_31to9_32, a8_31to8_32, a7_31to7_32, a6_31to6_32, a5_31to5_32, a4_31to4_32, a3_31to3_32, a2_31to2_32, a1_31to1_32, a0_31to0_32}; +//assign b_data_out = {b31_31to32_31, b31_30to32_30, b31_29to32_29, b31_28to32_28, b31_27to32_27, b31_26to32_26, b31_25to32_25, b31_24to32_24, b31_23to32_23, b31_22to32_22, b31_21to32_21, b31_20to32_20, b31_19to32_19, b31_18to32_18, b31_17to32_17, b31_16to32_16, b31_15to32_15, b31_14to32_14, b31_13to32_13, b31_12to32_12, b31_11to32_11, b31_10to32_10, b31_9to32_9, b31_8to32_8, b31_7to32_7, b31_6to32_6, b31_5to32_5, b31_4to32_4, b31_3to32_3, b31_2to32_2, b31_1to32_1, b31_0to32_0}; + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Processing element (PE) +////////////////////////////////////////////////////////////////////////// + +module processing_element( + reset, + clk, + b_data_sel, + in_a, + in_a_chain, + in_b, + in_c, + out_a, + out_a_chain, + out_b, + out_b0, + out_b1, + out_c, + b_data_valid_ping, + b_data_valid_pong, + mode + ); + +input reset; +input clk; +input b_data_sel; +input b_data_valid_ping; +input b_data_valid_pong; +input [`DWIDTH-1:0] in_a; +input [`DWIDTH-1:0] in_a_chain; +input [`DWIDTH-1:0] in_b; +input [`DWIDTH-1:0] in_c; +output [`DWIDTH-1:0] out_a; +output [`DWIDTH-1:0] out_a_chain; +output [`DWIDTH-1:0] out_b; +output [`DWIDTH-1:0] out_b0; +output [`DWIDTH-1:0] out_b1; +output [`DWIDTH-1:0] out_c; +input mode; + +`ifdef complex_dsp + + wire [18:0] scanout; + wire [63:0] chainout; //unconnected + wire [63:0] result; + wire [17:0] ax; + wire [18:0] ay; + wire [35:0] bx; + wire [63:0] chainin; //unconnected + wire [18:0] scanin; + wire [11:0] mode_sigs; + + assign mode_sigs = 12'b010101010101; //Any value of mode_sigs (structural, not functional, correctness) + assign ax = {{(18-`DWIDTH){1'b0}}, in_a}; + assign ay = {{(19-`DWIDTH){1'b0}}, in_b}; + assign bx = in_c; + assign scanin = {{(18-`DWIDTH){1'b0}}, in_a_chain}; + //assign chainin = in_c; + + //We will instantiate DSP slices with input chaining and output chaining. + //Input chaining is only supported in the 18x19 mode or the 27x27 mode. + //We will use the input chain provided by the DSP for the A input. For B, the chain will be manual. + + mult_add_int_18x19 u_pe( + .clk(clk), + .reset(reset), + .mode_sigs(mode_sigs), + .ax(ax), + .ay(ay), + .bx(bx), + .chainin(chainin), + .scanin(scanin), + .result(result), + .chainout(chainout), + .scanout(scanout) + ); + +reg [`DWIDTH-1:0] out_b0; +reg [`DWIDTH-1:0] out_b1; + +wire [`DWIDTH-1:0] in_mac; +wire [`DWIDTH-1:0] out_c; + +assign out_c = result; +assign in_mac = (b_data_sel==0)? out_b0 : out_b1; + +//assign out_a = result; +assign out_a_chain = scanout; + +always @(posedge clk)begin + if (reset) begin + out_b0<=0; + end + if(b_data_valid_ping == 1) begin + out_b0<=in_b; + end +end + +always @(posedge clk)begin + if (reset) begin + out_b1<=0; + end + if(b_data_valid_pong == 1) begin + out_b1<=in_b; + end +end + +`else + +reg [`DWIDTH-1:0] out_a; +reg [`DWIDTH-1:0] out_b; +reg [`DWIDTH-1:0] out_b0; +reg [`DWIDTH-1:0] out_b1; + +wire [`DWIDTH-1:0] in_mac; +wire [`DWIDTH-1:0] out_c; +wire [`DWIDTH-1:0] out_mac; + +assign out_c = out_mac; +assign in_mac = (b_data_sel==0)? out_b0 : out_b1; + +seq_mac u_mac(.a(out_a), .b(in_mac), .c(in_c), .out(out_mac), .reset(reset), .clk(clk)); + +always @(posedge clk)begin + if(reset) begin + out_a<=0; + end + else begin + out_a<=mode ? in_a : in_a_chain; + end +end + +assign out_a_chain = out_a; + + +always @(posedge clk)begin + if(reset) begin + out_b<=0; + end + else begin + out_b<=in_b; + end +end + +always @(posedge clk)begin + if (reset) begin + out_b0<=0; + end + if(b_data_valid_ping == 1) begin + out_b0<=in_b; + end +end + +always @(posedge clk)begin + if (reset) begin + out_b1<=0; + end + if(b_data_valid_pong == 1) begin + out_b1<=in_b; + end +end + +`endif + +endmodule + +`ifndef complex_dsp + +////////////////////////////////////////////////////////////////////////// +// Multiply-and-accumulate (MAC) block +////////////////////////////////////////////////////////////////////////// + +module seq_mac(a, b, c, out, reset, clk); + +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +input [`DWIDTH-1:0] c; +input reset; +input clk; +output [`DWIDTH-1:0] out; + +wire [`DWIDTH-1:0] mul_out; +wire [`DWIDTH-1:0] add_out; + +reg [`DWIDTH-1:0] a_flopped; +reg [`DWIDTH-1:0] b_flopped; +reg [`DWIDTH-1:0] c_flopped; + +wire [2*`DWIDTH-1:0] mul_out_temp; +wire [2*`DWIDTH-1:0] mul_out_temp_reg; + +always @(posedge clk) begin + if (reset) begin + a_flopped <= 0; + b_flopped <= 0; + c_flopped <= 0; + end else begin + a_flopped <= a; + b_flopped <= b; + c_flopped <= c; + end +end + +// assign mul_out = a * b; +qmult mult_u1(.i_multiplicand(a_flopped), .i_multiplier(b_flopped), .o_result(mul_out_temp)); + + +// down cast the result +// todo: do a fused multiply add. Truncate only once after the accumulation is complete +assign mul_out = + (mul_out_temp[2*`DWIDTH-1] == 0) ? //positive number + ( + (|(mul_out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 1, that means overlfow + {mul_out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b1}}} : //sign bit and then all 1s + {mul_out_temp[2*`DWIDTH-1] , mul_out_temp[`DWIDTH-2:0]} + ) + : //negative number + ( + (|(mul_out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 0, that means overlfow + {mul_out_temp[2*`DWIDTH-1] , mul_out_temp[`DWIDTH-2:0]} : + {mul_out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b0}}} //sign bit and then all 0s + ); + + +// we just truncate the higher bits of the product +// assign out = mul_out + c_flopped; +qadd add_u1(.a(c_flopped), .b(mul_out), .c(out)); + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Multiplier +////////////////////////////////////////////////////////////////////////// + +module qmult(i_multiplicand,i_multiplier,o_result); + +input [`DWIDTH-1:0] i_multiplicand; +input [`DWIDTH-1:0] i_multiplier; +output [2*`DWIDTH-1:0] o_result; + +assign o_result = i_multiplicand * i_multiplier; +//DW02_mult #(`DWIDTH,`DWIDTH) u_mult(.A(i_multiplicand), .B(i_multiplier), .TC(1'b1), .PRODUCT(o_result)); + +endmodule + +`endif + +////////////////////////////////////////////////////////////////////////// +// Adder +////////////////////////////////////////////////////////////////////////// +// todo: Output should have one extra bit as compared to the inputs + +module qadd(a,b,c); + +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +output [`DWIDTH-1:0] c; + +assign c = a + b; +// DW01_add #(`DWIDTH) u_add(.A(a), .B(b), .CI(1'b0), .SUM(c), .CO()); + +endmodule + +module cfg( + input PCLK, + input PRESETn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output reg [`REG_DATAWIDTH-1:0] PRDATA, + output reg PREADY, + output reg start_tpu, + output reg enable_matmul, + output reg enable_norm, + output reg enable_pool, + output reg enable_activation, + output reg enable_conv_mode, + //TODO: We need to change the precision of compute to a larger + //number. For now, using the DWIDTH variable, but we need a + //HIGH_PRECISION_DWIDTH kind of thing + output reg [`DWIDTH-1:0] mean, + output reg [`DWIDTH-1:0] inv_var, + output reg [`MAX_BITS_POOL-1:0] pool_window_size, + output reg [`AWIDTH-1:0] address_mat_a, + output reg [`AWIDTH-1:0] address_mat_b, + output reg [`AWIDTH-1:0] address_mat_c, + output reg [31:0] num_matrices_A, + output reg [31:0] num_matrices_B, + output reg [`DWIDTH-1:0] matrix_size, + output reg [`DWIDTH-1:0] filter_size, + output reg pool_select, + output reg [`DWIDTH-1:0] k_dimension, + output reg accum_select, + output reg [`MASK_WIDTH-1:0] validity_mask_a_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_a_cols_b_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_b_cols, + output reg save_output_to_accum, + output reg add_accum_to_output, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c, + output reg activation_type, + output reg [3:0] conv_filter_height, + output reg [3:0] conv_filter_width, + output reg [3:0] conv_stride_horiz, + output reg [3:0] conv_stride_verti, + output reg [3:0] conv_padding_left, + output reg [3:0] conv_padding_right, + output reg [3:0] conv_padding_top, + output reg [3:0] conv_padding_bottom, + output reg [15:0] num_channels_inp, + output reg [15:0] num_channels_out, + output reg [15:0] inp_img_height, + output reg [15:0] inp_img_width, + output reg [15:0] out_img_height, + output reg [15:0] out_img_width, + output reg [31:0] batch_size, + output reg pe_reset, + input done_tpu +); + +//Dummy register to sync all other invalid/unimplemented addresses +reg [`REG_DATAWIDTH-1:0] reg_dummy; + + +////////////////////////////////////////////////////// +//Using a simple APB interface. Taken from: +// https://github.com/maomran/APB-Slave +// https://research.ijcaonline.org/volume95/number21/pxc3897047.pdf + +reg [1:0] State; +`define IDLE 2'b00 +`define W_ENABLE 2'b01 +`define R_ENABLE 2'b10 + +always @(posedge PCLK) begin + if (PRESETn == 0) begin + State <= `IDLE; + PRDATA <= 0; + PREADY <= 0; + start_tpu <= 0; + enable_matmul <= 0; + enable_norm <= 0; + enable_pool <= 0; + enable_activation <= 0; + mean <= 0; + inv_var <= 0; + pool_window_size <= 1; + reg_dummy <= 0; + address_mat_a <= 0; + address_mat_b <= 0; + address_mat_c <= 0; + num_matrices_A <= 1; + num_matrices_B <= 1; + matrix_size <= 8; + filter_size <= 2; + pool_select <= 0; + k_dimension <= 8; + accum_select <= 1; + validity_mask_a_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_a_cols_b_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_cols <= {`MASK_WIDTH{1'b1}}; + save_output_to_accum <= 0; + add_accum_to_output <= 0; + address_stride_a <= 1; + address_stride_b <= 1; + address_stride_c <= 1; + activation_type <= 1; + conv_filter_height <= 2; + conv_filter_width <= 2; + conv_stride_horiz <= 1; + conv_stride_verti <= 1; + conv_padding_left <= 0; + conv_padding_right <= 0; + conv_padding_top <= 0; + conv_padding_bottom<= 0; + num_channels_inp <= 4; + num_channels_out <= 4; + inp_img_height <= 8; + inp_img_width <= 8; + out_img_height <= 7; + out_img_width <= 7; + batch_size <= 2; + enable_conv_mode <= 0; + pe_reset <= 0; + end + + else begin + case (State) + `IDLE : begin + PRDATA <= 0; + if (PSEL) begin + if (PWRITE) begin + State <= `W_ENABLE; + end + else begin + State <= `R_ENABLE; + end + end + PREADY <= 0; + pe_reset <= 0; //this register bit auto resets itself + end + + `W_ENABLE : begin + if (PSEL && PWRITE && PENABLE) begin + case (PADDR) + `REG_ENABLES_ADDR : begin + enable_conv_mode <= PWDATA[31]; + enable_activation <= PWDATA[3]; + enable_pool <= PWDATA[2]; + enable_norm <= PWDATA[1]; + enable_matmul <= PWDATA[0]; + end + `REG_STDN_TPU_ADDR : begin + start_tpu <= PWDATA[0]; + pe_reset <= PWDATA[15]; + end + `REG_MEAN_ADDR : mean <= PWDATA[`DWIDTH-1:0]; + `REG_INV_VAR_ADDR : inv_var <= PWDATA[`DWIDTH-1:0]; + `REG_MATRIX_A_ADDR : address_mat_a <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_B_ADDR : address_mat_b <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_C_ADDR : address_mat_c <= PWDATA[`AWIDTH-1:0]; + `REG_VALID_MASK_A_ROWS_ADDR: begin + validity_mask_a_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_A_COLS_B_ROWS_ADDR: begin + validity_mask_a_cols_b_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_COLS_ADDR: begin + validity_mask_b_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_POOL_WINDOW_ADDR: pool_window_size <= PWDATA[`MAX_BITS_POOL-1:0]; + `REG_ACCUM_ACTIONS_ADDR: begin + add_accum_to_output <= PWDATA[1]; + save_output_to_accum <= PWDATA[0]; + end + `REG_MATRIX_A_STRIDE_ADDR : address_stride_a <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_B_STRIDE_ADDR : address_stride_b <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_C_STRIDE_ADDR : address_stride_c <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_ACTIVATION_CSR_ADDR : activation_type <= PWDATA[0]; + `REG_CONV_PARAMS_1_ADDR : begin + conv_filter_height <= PWDATA[3:0]; + conv_filter_width <= PWDATA[7:4]; + conv_stride_horiz <= PWDATA[11:8]; + conv_stride_verti <= PWDATA[15:12]; + conv_padding_left <= PWDATA[19:16]; + conv_padding_right <= PWDATA[23:20]; + conv_padding_top <= PWDATA[27:24]; + conv_padding_bottom<= PWDATA[31:28]; + end + `REG_CONV_PARAMS_2_ADDR : begin + num_channels_inp <= PWDATA[15:0]; + num_channels_out <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_3_ADDR : begin + inp_img_height <= PWDATA[15:0]; + inp_img_width <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_4_ADDR : begin + out_img_height <= PWDATA[15:0]; + out_img_width <= PWDATA[31:16]; + end + `REG_BATCH_SIZE_ADDR : batch_size <= PWDATA[31:0]; + `REG_NUM_MATRICES_A_ADDR : num_matrices_A <= PWDATA[31:0]; + `REG_NUM_MATRICES_B_ADDR : num_matrices_B <= PWDATA[31:0]; + `REG_POOLING_ACCUM_ADDR : begin + pool_select <= PWDATA[0]; + filter_size <= PWDATA[8:1]; + matrix_size <= PWDATA[16:9]; + k_dimension <= PWDATA[24:17]; + accum_select <= PWDATA[25]; + end + default: reg_dummy <= PWDATA; //sink writes to a dummy register + endcase + PREADY <=1; + end + State <= `IDLE; + end + + `R_ENABLE : begin + if (PSEL && !PWRITE && PENABLE) begin + PREADY <= 1; + case (PADDR) + `REG_ENABLES_ADDR : PRDATA <= {28'b0, enable_activation, enable_pool, enable_norm, enable_matmul}; + `REG_STDN_TPU_ADDR : PRDATA <= {done_tpu, 30'b0, start_tpu}; + `REG_MEAN_ADDR : PRDATA <= mean; + `REG_INV_VAR_ADDR : PRDATA <= inv_var; + `REG_MATRIX_A_ADDR : PRDATA <= address_mat_a; + `REG_MATRIX_B_ADDR : PRDATA <= address_mat_b; + `REG_MATRIX_C_ADDR : PRDATA <= address_mat_c; + `REG_VALID_MASK_A_ROWS_ADDR: PRDATA <= validity_mask_a_rows; + `REG_VALID_MASK_A_COLS_B_ROWS_ADDR: PRDATA <= validity_mask_a_cols_b_rows; + `REG_VALID_MASK_B_COLS_ADDR: PRDATA <= validity_mask_b_cols; + `REG_POOL_WINDOW_ADDR : PRDATA <= pool_window_size; + `REG_ACCUM_ACTIONS_ADDR: PRDATA <= {30'b0, add_accum_to_output, save_output_to_accum}; + `REG_MATRIX_A_STRIDE_ADDR : PRDATA <= address_stride_a; + `REG_MATRIX_B_STRIDE_ADDR : PRDATA <= address_stride_b; + `REG_MATRIX_C_STRIDE_ADDR : PRDATA <= address_stride_c; + `REG_ACTIVATION_CSR_ADDR : PRDATA <= {31'b0, activation_type}; + `REG_CONV_PARAMS_1_ADDR : PRDATA <= { + conv_filter_height, + conv_filter_width, + conv_stride_horiz, + conv_stride_verti, + conv_padding_left, + conv_padding_right, + conv_padding_top, + conv_padding_bottom + }; + `REG_CONV_PARAMS_2_ADDR : PRDATA <= { + num_channels_inp, + num_channels_out + }; + `REG_CONV_PARAMS_3_ADDR : PRDATA <= { + inp_img_height, + inp_img_width + }; + `REG_CONV_PARAMS_4_ADDR : PRDATA <= { + out_img_height, + out_img_width + }; + `REG_BATCH_SIZE_ADDR : PRDATA <= batch_size; + `REG_NUM_MATRICES_A_ADDR : PRDATA <= num_matrices_A; + `REG_NUM_MATRICES_B_ADDR : PRDATA <= num_matrices_B; + `REG_POOLING_ACCUM_ADDR : PRDATA <= {6'b0, accum_select, k_dimension, matrix_size, filter_size, pool_select}; + default : PRDATA <= reg_dummy; //read the dummy register for undefined addresses + endcase + end + State <= `IDLE; + end + default: begin + State <= `IDLE; + end + endcase + end +end + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM generate_norm.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// +module norm( + input enable_norm, + input [`DWIDTH-1:0] mean, + input [`DWIDTH-1:0] inv_var, + input in_data_available, + input [`DWIDTH-1:0] inp_data0, + input [`DWIDTH-1:0] inp_data1, + input [`DWIDTH-1:0] inp_data2, + input [`DWIDTH-1:0] inp_data3, + input [`DWIDTH-1:0] inp_data4, + input [`DWIDTH-1:0] inp_data5, + input [`DWIDTH-1:0] inp_data6, + input [`DWIDTH-1:0] inp_data7, + input [`DWIDTH-1:0] inp_data8, + input [`DWIDTH-1:0] inp_data9, + input [`DWIDTH-1:0] inp_data10, + input [`DWIDTH-1:0] inp_data11, + input [`DWIDTH-1:0] inp_data12, + input [`DWIDTH-1:0] inp_data13, + input [`DWIDTH-1:0] inp_data14, + input [`DWIDTH-1:0] inp_data15, + input [`DWIDTH-1:0] inp_data16, + input [`DWIDTH-1:0] inp_data17, + input [`DWIDTH-1:0] inp_data18, + input [`DWIDTH-1:0] inp_data19, + input [`DWIDTH-1:0] inp_data20, + input [`DWIDTH-1:0] inp_data21, + input [`DWIDTH-1:0] inp_data22, + input [`DWIDTH-1:0] inp_data23, + input [`DWIDTH-1:0] inp_data24, + input [`DWIDTH-1:0] inp_data25, + input [`DWIDTH-1:0] inp_data26, + input [`DWIDTH-1:0] inp_data27, + input [`DWIDTH-1:0] inp_data28, + input [`DWIDTH-1:0] inp_data29, + input [`DWIDTH-1:0] inp_data30, + input [`DWIDTH-1:0] inp_data31, + output [`DWIDTH-1:0] out_data0, + output [`DWIDTH-1:0] out_data1, + output [`DWIDTH-1:0] out_data2, + output [`DWIDTH-1:0] out_data3, + output [`DWIDTH-1:0] out_data4, + output [`DWIDTH-1:0] out_data5, + output [`DWIDTH-1:0] out_data6, + output [`DWIDTH-1:0] out_data7, + output [`DWIDTH-1:0] out_data8, + output [`DWIDTH-1:0] out_data9, + output [`DWIDTH-1:0] out_data10, + output [`DWIDTH-1:0] out_data11, + output [`DWIDTH-1:0] out_data12, + output [`DWIDTH-1:0] out_data13, + output [`DWIDTH-1:0] out_data14, + output [`DWIDTH-1:0] out_data15, + output [`DWIDTH-1:0] out_data16, + output [`DWIDTH-1:0] out_data17, + output [`DWIDTH-1:0] out_data18, + output [`DWIDTH-1:0] out_data19, + output [`DWIDTH-1:0] out_data20, + output [`DWIDTH-1:0] out_data21, + output [`DWIDTH-1:0] out_data22, + output [`DWIDTH-1:0] out_data23, + output [`DWIDTH-1:0] out_data24, + output [`DWIDTH-1:0] out_data25, + output [`DWIDTH-1:0] out_data26, + output [`DWIDTH-1:0] out_data27, + output [`DWIDTH-1:0] out_data28, + output [`DWIDTH-1:0] out_data29, + output [`DWIDTH-1:0] out_data30, + output [`DWIDTH-1:0] out_data31, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output reg done_norm, + input clk, + input reset +); + +reg in_data_available1; +reg in_data_available2; +reg in_data_available3; +reg in_data_available4; +reg in_data_available5; +reg in_data_available6; +reg in_data_available7; +reg in_data_available8; +reg in_data_available9; +reg in_data_available10; +reg in_data_available11; +reg in_data_available12; +reg in_data_available13; +reg in_data_available14; +reg in_data_available15; +reg in_data_available16; +reg in_data_available17; +reg in_data_available18; +reg in_data_available19; +reg in_data_available20; +reg in_data_available21; +reg in_data_available22; +reg in_data_available23; +reg in_data_available24; +reg in_data_available25; +reg in_data_available26; +reg in_data_available27; +reg in_data_available28; +reg in_data_available29; +reg in_data_available30; +reg in_data_available31; + +always @(posedge clk) begin + in_data_available1 <= in_data_available; + in_data_available2 <= in_data_available1; + in_data_available3 <= in_data_available2; + in_data_available4 <= in_data_available3; + in_data_available5 <= in_data_available4; + in_data_available6 <= in_data_available5; + in_data_available7 <= in_data_available6; + in_data_available8 <= in_data_available7; + in_data_available9 <= in_data_available8; + in_data_available10 <= in_data_available9; + in_data_available11 <= in_data_available10; + in_data_available12 <= in_data_available11; + in_data_available13 <= in_data_available12; + in_data_available14 <= in_data_available13; + in_data_available15 <= in_data_available14; + in_data_available16 <= in_data_available15; + in_data_available17 <= in_data_available16; + in_data_available18 <= in_data_available17; + in_data_available19 <= in_data_available18; + in_data_available20 <= in_data_available19; + in_data_available21 <= in_data_available20; + in_data_available22 <= in_data_available21; + in_data_available23 <= in_data_available22; + in_data_available24 <= in_data_available23; + in_data_available25 <= in_data_available24; + in_data_available26 <= in_data_available25; + in_data_available27 <= in_data_available26; + in_data_available28 <= in_data_available27; + in_data_available29 <= in_data_available28; + in_data_available30 <= in_data_available29; + in_data_available31 <= in_data_available30; +end + +wire out_data_available_internal; +wire out_data_available_final; + +reg [`DWIDTH-1:0] done_count; + +assign out_data_available = (enable_norm) ? out_data_available_internal : in_data_available; + +always @(posedge clk) begin + if (reset) begin + done_norm <= 0; + done_count <= 0; + end + if (done_count == 4) begin + done_norm <= 1; + end + if (out_data_available_final == 1) begin + done_count <= done_count + 1; + end +end + +norm_sub norm0( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available), + .inp_data(inp_data0), + .out_data(out_data0), + .out_data_available(out_data_available_internal), + .validity_mask(validity_mask[0]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC1; +norm_sub norm1( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available1), + .inp_data(inp_data1), + .out_data(out_data1), + .out_data_available(out_data_available_NC1), + .validity_mask(validity_mask[1]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC2; +norm_sub norm2( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available2), + .inp_data(inp_data2), + .out_data(out_data2), + .out_data_available(out_data_available_NC2), + .validity_mask(validity_mask[2]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC3; +norm_sub norm3( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available3), + .inp_data(inp_data3), + .out_data(out_data3), + .out_data_available(out_data_available_NC3), + .validity_mask(validity_mask[3]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC4; +norm_sub norm4( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available4), + .inp_data(inp_data4), + .out_data(out_data4), + .out_data_available(out_data_available_NC4), + .validity_mask(validity_mask[4]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC5; +norm_sub norm5( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available5), + .inp_data(inp_data5), + .out_data(out_data5), + .out_data_available(out_data_available_NC5), + .validity_mask(validity_mask[5]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC6; +norm_sub norm6( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available6), + .inp_data(inp_data6), + .out_data(out_data6), + .out_data_available(out_data_available_NC6), + .validity_mask(validity_mask[6]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC7; +norm_sub norm7( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available7), + .inp_data(inp_data7), + .out_data(out_data7), + .out_data_available(out_data_available_NC7), + .validity_mask(validity_mask[7]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC8; +norm_sub norm8( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available8), + .inp_data(inp_data8), + .out_data(out_data8), + .out_data_available(out_data_available_NC8), + .validity_mask(validity_mask[8]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC9; +norm_sub norm9( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available9), + .inp_data(inp_data9), + .out_data(out_data9), + .out_data_available(out_data_available_NC9), + .validity_mask(validity_mask[9]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC10; +norm_sub norm10( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available10), + .inp_data(inp_data10), + .out_data(out_data10), + .out_data_available(out_data_available_NC10), + .validity_mask(validity_mask[10]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC11; +norm_sub norm11( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available11), + .inp_data(inp_data11), + .out_data(out_data11), + .out_data_available(out_data_available_NC11), + .validity_mask(validity_mask[11]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC12; +norm_sub norm12( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available12), + .inp_data(inp_data12), + .out_data(out_data12), + .out_data_available(out_data_available_NC12), + .validity_mask(validity_mask[12]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC13; +norm_sub norm13( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available13), + .inp_data(inp_data13), + .out_data(out_data13), + .out_data_available(out_data_available_NC13), + .validity_mask(validity_mask[13]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC14; +norm_sub norm14( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available14), + .inp_data(inp_data14), + .out_data(out_data14), + .out_data_available(out_data_available_NC14), + .validity_mask(validity_mask[14]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC15; +norm_sub norm15( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available15), + .inp_data(inp_data15), + .out_data(out_data15), + .out_data_available(out_data_available_NC15), + .validity_mask(validity_mask[15]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC16; +norm_sub norm16( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available16), + .inp_data(inp_data16), + .out_data(out_data16), + .out_data_available(out_data_available_NC16), + .validity_mask(validity_mask[16]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC17; +norm_sub norm17( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available17), + .inp_data(inp_data17), + .out_data(out_data17), + .out_data_available(out_data_available_NC17), + .validity_mask(validity_mask[17]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC18; +norm_sub norm18( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available18), + .inp_data(inp_data18), + .out_data(out_data18), + .out_data_available(out_data_available_NC18), + .validity_mask(validity_mask[18]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC19; +norm_sub norm19( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available19), + .inp_data(inp_data19), + .out_data(out_data19), + .out_data_available(out_data_available_NC19), + .validity_mask(validity_mask[19]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC20; +norm_sub norm20( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available20), + .inp_data(inp_data20), + .out_data(out_data20), + .out_data_available(out_data_available_NC20), + .validity_mask(validity_mask[20]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC21; +norm_sub norm21( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available21), + .inp_data(inp_data21), + .out_data(out_data21), + .out_data_available(out_data_available_NC21), + .validity_mask(validity_mask[21]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC22; +norm_sub norm22( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available22), + .inp_data(inp_data22), + .out_data(out_data22), + .out_data_available(out_data_available_NC22), + .validity_mask(validity_mask[22]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC23; +norm_sub norm23( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available23), + .inp_data(inp_data23), + .out_data(out_data23), + .out_data_available(out_data_available_NC23), + .validity_mask(validity_mask[23]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC24; +norm_sub norm24( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available24), + .inp_data(inp_data24), + .out_data(out_data24), + .out_data_available(out_data_available_NC24), + .validity_mask(validity_mask[24]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC25; +norm_sub norm25( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available25), + .inp_data(inp_data25), + .out_data(out_data25), + .out_data_available(out_data_available_NC25), + .validity_mask(validity_mask[25]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC26; +norm_sub norm26( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available26), + .inp_data(inp_data26), + .out_data(out_data26), + .out_data_available(out_data_available_NC26), + .validity_mask(validity_mask[26]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC27; +norm_sub norm27( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available27), + .inp_data(inp_data27), + .out_data(out_data27), + .out_data_available(out_data_available_NC27), + .validity_mask(validity_mask[27]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC28; +norm_sub norm28( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available28), + .inp_data(inp_data28), + .out_data(out_data28), + .out_data_available(out_data_available_NC28), + .validity_mask(validity_mask[28]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC29; +norm_sub norm29( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available29), + .inp_data(inp_data29), + .out_data(out_data29), + .out_data_available(out_data_available_NC29), + .validity_mask(validity_mask[29]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC30; +norm_sub norm30( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available30), + .inp_data(inp_data30), + .out_data(out_data30), + .out_data_available(out_data_available_NC30), + .validity_mask(validity_mask[30]), + .clk(clk), + .reset(reset) +); + +norm_sub norm31( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available31), + .inp_data(inp_data31), + .out_data(out_data31), + .out_data_available(out_data_available_final), + .validity_mask(validity_mask[31]), + .clk(clk), + .reset(reset) +); + +endmodule + +module norm_sub( + input enable_norm, + input [`DWIDTH-1:0] mean, + input [`DWIDTH-1:0] inv_var, + input in_data_available, + input [`DWIDTH-1:0] inp_data, + output [`DWIDTH-1:0] out_data, + output out_data_available, + input validity_mask, + input clk, + input reset +); + +reg out_data_available_internal; +wire [`DWIDTH-1:0] out_data_internal; +reg [`DWIDTH-1:0] mean_applied_data; +reg [`DWIDTH-1:0] variance_applied_data; +reg norm_in_progress; + +//Muxing logic to handle the case when this block is disabled +assign out_data_available = (enable_norm) ? out_data_available_internal : in_data_available; +assign out_data = (enable_norm) ? out_data_internal : inp_data; + +always @(posedge clk) begin + if ((reset || ~enable_norm)) begin + mean_applied_data <= 0; + variance_applied_data <= 0; + end else if (in_data_available||norm_in_progress) begin + //Let's apply mean and variance as the input data comes in. + //We have a pipeline here. First stage does the add (to apply the mean) + //and second stage does the multiplication (to apply the variance). + //Note: the following loop is not a loop across multiple columns of data. + //This loop will run in 2 cycle on the same column of data that comes into + //this module in 1 clock. + if (validity_mask == 1'b1) begin + mean_applied_data <= (inp_data - mean); + variance_applied_data <= (mean_applied_data * inv_var); + end + else begin + mean_applied_data <= (inp_data); + variance_applied_data <= (mean_applied_data); + end + end + else begin + mean_applied_data <= 0; + variance_applied_data <= 0; + end +end + +//The data is normalized in two cycles so we are shifting in_data_available by 2 to generate out_data_available +always @(posedge clk) begin + norm_in_progress <= in_data_available; + out_data_available_internal <= norm_in_progress; +end + +assign out_data_internal = variance_applied_data; + +endmodule + +//Simple sual port RAM is not understood by VTR +`ifdef QUARTUS +////////////////////////////////// +// Simple dual port RAM +////////////////////////////////// +module simple_ram ( + addr0, + d0, + we0, + addr1, + q1, + clk); + +parameter AW = 11; +parameter MW = 8; +parameter DW = 8; + +input [AW-1:0] addr0; +input [AW-1:0] addr1; +input [MW*DW-1:0] d0; +input [MW-1:0] we0; +output reg [MW*DW-1:0] q1; +input clk; + +wire we0_coalesced; +assign we0_coalesced = |we0; + +reg [MW*DW-1:0] ram[((1 << AW)-1):0]; + +always @(posedge clk) begin + if (we0_coalesced) ram[addr0] <= d0; +end + +always @(posedge clk) begin + q1 <= ram[addr1]; +end + +endmodule + +`endif + +////////////////////////////////// +// Dual port RAM +////////////////////////////////// +module ram ( + addr0, + d0, + we0, + q0, + addr1, + d1, + we1, + q1, + clk); + +parameter AW = 11; +parameter MW = 8; +parameter DW = 8; + +input [AW-1:0] addr0; +input [AW-1:0] addr1; +input [MW*DW-1:0] d0; +input [MW*DW-1:0] d1; +input [MW-1:0] we0; +input [MW-1:0] we1; +output reg [MW*DW-1:0] q0; +output reg [MW*DW-1:0] q1; +input clk; + +wire we0_coalesced; +assign we0_coalesced = |we0; +wire we1_coalesced; +assign we1_coalesced = |we1; + +`ifndef hard_mem +reg [MW*DW-1:0] ram[((1 << AW)-1):0]; + +always @(posedge clk) begin + if (we0_coalesced) ram[addr0] <= d0; + q0 <= ram[addr0]; +end + +always @(posedge clk) begin + if (we1_coalesced) ram[addr1] <= d1; + q1 <= ram[addr1]; +end + +`else + +defparam u_dual_port_ram.ADDR_WIDTH = AW; +defparam u_dual_port_ram.DATA_WIDTH = MW*DW; + +dual_port_ram u_dual_port_ram( +.addr1(addr0), +.we1(we0_coalesced), +.data1(d0), +.out1(q0), +.addr2(addr1), +.we2(we1_coalesced), +.data2(d1), +.out2(q1), +.clk(clk) +); + +`endif + +endmodule + +//Top level state machine +module control( + input clk, + input reset, + input start_tpu, + input enable_matmul, + input enable_norm, + input enable_activation, + input enable_pool, + output reg start_mat_mul, + input done_mat_mul, + input done_norm, + input done_pool, + input done_activation, + input save_output_to_accum, + output reg done_tpu +); + +reg [3:0] state; + +`define STATE_INIT 4'b0000 +`define STATE_MATMUL 4'b0001 +`define STATE_NORM 4'b0010 +`define STATE_POOL 4'b0011 +`define STATE_ACTIVATION 4'b0100 +`define STATE_DONE 4'b0101 + +////////////////////////////////////////////////////// +// Assumption: We will always run matmul first. That is, matmul is not optional. +// The other blocks - norm, act, pool - are optional. +// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation +////////////////////////////////////////////////////// + +always @( posedge clk) begin + if (reset) begin + state <= `STATE_INIT; + start_mat_mul <= 1'b0; + done_tpu <= 1'b0; + end else begin + case (state) + `STATE_INIT: begin + if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin + if (enable_matmul == 1'b1) begin + start_mat_mul <= 1'b1; + state <= `STATE_MATMUL; + end + end + end + + //start_mat_mul is kinda used as a reset in some logic + //inside the matmul unit. So, we can't make it 0 right away after + //asserting it. + `STATE_MATMUL: begin + if (done_mat_mul == 1'b1) begin + start_mat_mul <= 1'b0; + if(save_output_to_accum) begin + state <= `STATE_DONE; + end + else if (enable_norm) begin + state <= `STATE_NORM; + end + else if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + else begin + start_mat_mul <= 1'b1; + end + end + + `STATE_NORM: begin + if (done_norm == 1'b1) begin + if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_POOL: begin + if (done_pool == 1'b1) begin + if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_ACTIVATION: begin + if (done_activation == 1'b1) begin + state <= `STATE_DONE; + end + end + + `STATE_DONE: begin + //We need to write start_tpu to 0 in the CFG block to get out of this state + if (start_tpu == 1'b0) begin + state <= `STATE_INIT; + done_tpu <= 0; + end + else begin + done_tpu <= 1; + end + end + endcase + end +end +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM generate_accum.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// +module accumulator ( + clk, + resetn, + start_waddr_accum0, + wdata_accum0, + wdata_accum1, + wdata_accum2, + wdata_accum3, + wdata_accum4, + wdata_accum5, + wdata_accum6, + wdata_accum7, + wdata_accum8, + wdata_accum9, + wdata_accum10, + wdata_accum11, + wdata_accum12, + wdata_accum13, + wdata_accum14, + wdata_accum15, + wdata_accum16, + wdata_accum17, + wdata_accum18, + wdata_accum19, + wdata_accum20, + wdata_accum21, + wdata_accum22, + wdata_accum23, + wdata_accum24, + wdata_accum25, + wdata_accum26, + wdata_accum27, + wdata_accum28, + wdata_accum29, + wdata_accum30, + wdata_accum31, + raddr_accum0_pool, + raddr_accum1_pool, + raddr_accum2_pool, + raddr_accum3_pool, + raddr_accum4_pool, + raddr_accum5_pool, + raddr_accum6_pool, + raddr_accum7_pool, + raddr_accum8_pool, + raddr_accum9_pool, + raddr_accum10_pool, + raddr_accum11_pool, + raddr_accum12_pool, + raddr_accum13_pool, + raddr_accum14_pool, + raddr_accum15_pool, + raddr_accum16_pool, + raddr_accum17_pool, + raddr_accum18_pool, + raddr_accum19_pool, + raddr_accum20_pool, + raddr_accum21_pool, + raddr_accum22_pool, + raddr_accum23_pool, + raddr_accum24_pool, + raddr_accum25_pool, + raddr_accum26_pool, + raddr_accum27_pool, + raddr_accum28_pool, + raddr_accum29_pool, + raddr_accum30_pool, + raddr_accum31_pool, + rdata_accum0_pool, + rdata_accum1_pool, + rdata_accum2_pool, + rdata_accum3_pool, + rdata_accum4_pool, + rdata_accum5_pool, + rdata_accum6_pool, + rdata_accum7_pool, + rdata_accum8_pool, + rdata_accum9_pool, + rdata_accum10_pool, + rdata_accum11_pool, + rdata_accum12_pool, + rdata_accum13_pool, + rdata_accum14_pool, + rdata_accum15_pool, + rdata_accum16_pool, + rdata_accum17_pool, + rdata_accum18_pool, + rdata_accum19_pool, + rdata_accum20_pool, + rdata_accum21_pool, + rdata_accum22_pool, + rdata_accum23_pool, + rdata_accum24_pool, + rdata_accum25_pool, + rdata_accum26_pool, + rdata_accum27_pool, + rdata_accum28_pool, + rdata_accum29_pool, + rdata_accum30_pool, + rdata_accum31_pool, + wdata_available, + k_dimension, + buffer_select, + start_pooling, + done_pooling +); + +input clk; +input resetn; +input [`AWIDTH-1:0] start_waddr_accum0; +input [`DWIDTH-1:0] wdata_accum0; +input [`DWIDTH-1:0] wdata_accum1; +input [`DWIDTH-1:0] wdata_accum2; +input [`DWIDTH-1:0] wdata_accum3; +input [`DWIDTH-1:0] wdata_accum4; +input [`DWIDTH-1:0] wdata_accum5; +input [`DWIDTH-1:0] wdata_accum6; +input [`DWIDTH-1:0] wdata_accum7; +input [`DWIDTH-1:0] wdata_accum8; +input [`DWIDTH-1:0] wdata_accum9; +input [`DWIDTH-1:0] wdata_accum10; +input [`DWIDTH-1:0] wdata_accum11; +input [`DWIDTH-1:0] wdata_accum12; +input [`DWIDTH-1:0] wdata_accum13; +input [`DWIDTH-1:0] wdata_accum14; +input [`DWIDTH-1:0] wdata_accum15; +input [`DWIDTH-1:0] wdata_accum16; +input [`DWIDTH-1:0] wdata_accum17; +input [`DWIDTH-1:0] wdata_accum18; +input [`DWIDTH-1:0] wdata_accum19; +input [`DWIDTH-1:0] wdata_accum20; +input [`DWIDTH-1:0] wdata_accum21; +input [`DWIDTH-1:0] wdata_accum22; +input [`DWIDTH-1:0] wdata_accum23; +input [`DWIDTH-1:0] wdata_accum24; +input [`DWIDTH-1:0] wdata_accum25; +input [`DWIDTH-1:0] wdata_accum26; +input [`DWIDTH-1:0] wdata_accum27; +input [`DWIDTH-1:0] wdata_accum28; +input [`DWIDTH-1:0] wdata_accum29; +input [`DWIDTH-1:0] wdata_accum30; +input [`DWIDTH-1:0] wdata_accum31; +input [`AWIDTH-1:0] raddr_accum0_pool; +input [`AWIDTH-1:0] raddr_accum1_pool; +input [`AWIDTH-1:0] raddr_accum2_pool; +input [`AWIDTH-1:0] raddr_accum3_pool; +input [`AWIDTH-1:0] raddr_accum4_pool; +input [`AWIDTH-1:0] raddr_accum5_pool; +input [`AWIDTH-1:0] raddr_accum6_pool; +input [`AWIDTH-1:0] raddr_accum7_pool; +input [`AWIDTH-1:0] raddr_accum8_pool; +input [`AWIDTH-1:0] raddr_accum9_pool; +input [`AWIDTH-1:0] raddr_accum10_pool; +input [`AWIDTH-1:0] raddr_accum11_pool; +input [`AWIDTH-1:0] raddr_accum12_pool; +input [`AWIDTH-1:0] raddr_accum13_pool; +input [`AWIDTH-1:0] raddr_accum14_pool; +input [`AWIDTH-1:0] raddr_accum15_pool; +input [`AWIDTH-1:0] raddr_accum16_pool; +input [`AWIDTH-1:0] raddr_accum17_pool; +input [`AWIDTH-1:0] raddr_accum18_pool; +input [`AWIDTH-1:0] raddr_accum19_pool; +input [`AWIDTH-1:0] raddr_accum20_pool; +input [`AWIDTH-1:0] raddr_accum21_pool; +input [`AWIDTH-1:0] raddr_accum22_pool; +input [`AWIDTH-1:0] raddr_accum23_pool; +input [`AWIDTH-1:0] raddr_accum24_pool; +input [`AWIDTH-1:0] raddr_accum25_pool; +input [`AWIDTH-1:0] raddr_accum26_pool; +input [`AWIDTH-1:0] raddr_accum27_pool; +input [`AWIDTH-1:0] raddr_accum28_pool; +input [`AWIDTH-1:0] raddr_accum29_pool; +input [`AWIDTH-1:0] raddr_accum30_pool; +input [`AWIDTH-1:0] raddr_accum31_pool; +output [`DWIDTH-1:0] rdata_accum0_pool; +output [`DWIDTH-1:0] rdata_accum1_pool; +output [`DWIDTH-1:0] rdata_accum2_pool; +output [`DWIDTH-1:0] rdata_accum3_pool; +output [`DWIDTH-1:0] rdata_accum4_pool; +output [`DWIDTH-1:0] rdata_accum5_pool; +output [`DWIDTH-1:0] rdata_accum6_pool; +output [`DWIDTH-1:0] rdata_accum7_pool; +output [`DWIDTH-1:0] rdata_accum8_pool; +output [`DWIDTH-1:0] rdata_accum9_pool; +output [`DWIDTH-1:0] rdata_accum10_pool; +output [`DWIDTH-1:0] rdata_accum11_pool; +output [`DWIDTH-1:0] rdata_accum12_pool; +output [`DWIDTH-1:0] rdata_accum13_pool; +output [`DWIDTH-1:0] rdata_accum14_pool; +output [`DWIDTH-1:0] rdata_accum15_pool; +output [`DWIDTH-1:0] rdata_accum16_pool; +output [`DWIDTH-1:0] rdata_accum17_pool; +output [`DWIDTH-1:0] rdata_accum18_pool; +output [`DWIDTH-1:0] rdata_accum19_pool; +output [`DWIDTH-1:0] rdata_accum20_pool; +output [`DWIDTH-1:0] rdata_accum21_pool; +output [`DWIDTH-1:0] rdata_accum22_pool; +output [`DWIDTH-1:0] rdata_accum23_pool; +output [`DWIDTH-1:0] rdata_accum24_pool; +output [`DWIDTH-1:0] rdata_accum25_pool; +output [`DWIDTH-1:0] rdata_accum26_pool; +output [`DWIDTH-1:0] rdata_accum27_pool; +output [`DWIDTH-1:0] rdata_accum28_pool; +output [`DWIDTH-1:0] rdata_accum29_pool; +output [`DWIDTH-1:0] rdata_accum30_pool; +output [`DWIDTH-1:0] rdata_accum31_pool; +input wdata_available; +input [7:0] k_dimension; // Number of columns in Matrix A | Number of rows in Matrix B (Assumption: Maximum = 256, can be changed accordingly) +input buffer_select; +output start_pooling; +output done_pooling; + + +parameter MWIDTH = 1; + +reg wdata_available1; +reg wdata_available2; +reg wdata_available3; +reg wdata_available4; +reg wdata_available5; +reg wdata_available6; +reg wdata_available7; +reg wdata_available8; +reg wdata_available9; +reg wdata_available10; +reg wdata_available11; +reg wdata_available12; +reg wdata_available13; +reg wdata_available14; +reg wdata_available15; +reg wdata_available16; +reg wdata_available17; +reg wdata_available18; +reg wdata_available19; +reg wdata_available20; +reg wdata_available21; +reg wdata_available22; +reg wdata_available23; +reg wdata_available24; +reg wdata_available25; +reg wdata_available26; +reg wdata_available27; +reg wdata_available28; +reg wdata_available29; +reg wdata_available30; +reg wdata_available31; + +always @ (posedge clk) begin + wdata_available1 <= wdata_available; + wdata_available2 <= wdata_available1; + wdata_available3 <= wdata_available2; + wdata_available4 <= wdata_available3; + wdata_available5 <= wdata_available4; + wdata_available6 <= wdata_available5; + wdata_available7 <= wdata_available6; + wdata_available8 <= wdata_available7; + wdata_available9 <= wdata_available8; + wdata_available10 <= wdata_available9; + wdata_available11 <= wdata_available10; + wdata_available12 <= wdata_available11; + wdata_available13 <= wdata_available12; + wdata_available14 <= wdata_available13; + wdata_available15 <= wdata_available14; + wdata_available16 <= wdata_available15; + wdata_available17 <= wdata_available16; + wdata_available18 <= wdata_available17; + wdata_available19 <= wdata_available18; + wdata_available20 <= wdata_available19; + wdata_available21 <= wdata_available20; + wdata_available22 <= wdata_available21; + wdata_available23 <= wdata_available22; + wdata_available24 <= wdata_available23; + wdata_available25 <= wdata_available24; + wdata_available26 <= wdata_available25; + wdata_available27 <= wdata_available26; + wdata_available28 <= wdata_available27; + wdata_available29 <= wdata_available28; + wdata_available30 <= wdata_available29; + wdata_available31 <= wdata_available30; +end + +wire wdata_en_ping0; +wire wdata_en_ping1; +wire wdata_en_ping2; +wire wdata_en_ping3; +wire wdata_en_ping4; +wire wdata_en_ping5; +wire wdata_en_ping6; +wire wdata_en_ping7; +wire wdata_en_ping8; +wire wdata_en_ping9; +wire wdata_en_ping10; +wire wdata_en_ping11; +wire wdata_en_ping12; +wire wdata_en_ping13; +wire wdata_en_ping14; +wire wdata_en_ping15; +wire wdata_en_ping16; +wire wdata_en_ping17; +wire wdata_en_ping18; +wire wdata_en_ping19; +wire wdata_en_ping20; +wire wdata_en_ping21; +wire wdata_en_ping22; +wire wdata_en_ping23; +wire wdata_en_ping24; +wire wdata_en_ping25; +wire wdata_en_ping26; +wire wdata_en_ping27; +wire wdata_en_ping28; +wire wdata_en_ping29; +wire wdata_en_ping30; +wire wdata_en_ping31; +wire wdata_en_pong0; +wire wdata_en_pong1; +wire wdata_en_pong2; +wire wdata_en_pong3; +wire wdata_en_pong4; +wire wdata_en_pong5; +wire wdata_en_pong6; +wire wdata_en_pong7; +wire wdata_en_pong8; +wire wdata_en_pong9; +wire wdata_en_pong10; +wire wdata_en_pong11; +wire wdata_en_pong12; +wire wdata_en_pong13; +wire wdata_en_pong14; +wire wdata_en_pong15; +wire wdata_en_pong16; +wire wdata_en_pong17; +wire wdata_en_pong18; +wire wdata_en_pong19; +wire wdata_en_pong20; +wire wdata_en_pong21; +wire wdata_en_pong22; +wire wdata_en_pong23; +wire wdata_en_pong24; +wire wdata_en_pong25; +wire wdata_en_pong26; +wire wdata_en_pong27; +wire wdata_en_pong28; +wire wdata_en_pong29; +wire wdata_en_pong30; +wire wdata_en_pong31; + +assign wdata_en_ping0 = wdata_available & buffer_select; +assign wdata_en_ping1 = wdata_available1 & buffer_select; +assign wdata_en_ping2 = wdata_available2 & buffer_select; +assign wdata_en_ping3 = wdata_available3 & buffer_select; +assign wdata_en_ping4 = wdata_available4 & buffer_select; +assign wdata_en_ping5 = wdata_available5 & buffer_select; +assign wdata_en_ping6 = wdata_available6 & buffer_select; +assign wdata_en_ping7 = wdata_available7 & buffer_select; +assign wdata_en_ping8 = wdata_available8 & buffer_select; +assign wdata_en_ping9 = wdata_available9 & buffer_select; +assign wdata_en_ping10 = wdata_available10 & buffer_select; +assign wdata_en_ping11 = wdata_available11 & buffer_select; +assign wdata_en_ping12 = wdata_available12 & buffer_select; +assign wdata_en_ping13 = wdata_available13 & buffer_select; +assign wdata_en_ping14 = wdata_available14 & buffer_select; +assign wdata_en_ping15 = wdata_available15 & buffer_select; +assign wdata_en_ping16 = wdata_available16 & buffer_select; +assign wdata_en_ping17 = wdata_available17 & buffer_select; +assign wdata_en_ping18 = wdata_available18 & buffer_select; +assign wdata_en_ping19 = wdata_available19 & buffer_select; +assign wdata_en_ping20 = wdata_available20 & buffer_select; +assign wdata_en_ping21 = wdata_available21 & buffer_select; +assign wdata_en_ping22 = wdata_available22 & buffer_select; +assign wdata_en_ping23 = wdata_available23 & buffer_select; +assign wdata_en_ping24 = wdata_available24 & buffer_select; +assign wdata_en_ping25 = wdata_available25 & buffer_select; +assign wdata_en_ping26 = wdata_available26 & buffer_select; +assign wdata_en_ping27 = wdata_available27 & buffer_select; +assign wdata_en_ping28 = wdata_available28 & buffer_select; +assign wdata_en_ping29 = wdata_available29 & buffer_select; +assign wdata_en_ping30 = wdata_available30 & buffer_select; +assign wdata_en_ping31 = wdata_available31 & buffer_select; + +assign wdata_en_pong0 = wdata_available & ~buffer_select; +assign wdata_en_pong1 = wdata_available1 & ~buffer_select; +assign wdata_en_pong2 = wdata_available2 & ~buffer_select; +assign wdata_en_pong3 = wdata_available3 & ~buffer_select; +assign wdata_en_pong4 = wdata_available4 & ~buffer_select; +assign wdata_en_pong5 = wdata_available5 & ~buffer_select; +assign wdata_en_pong6 = wdata_available6 & ~buffer_select; +assign wdata_en_pong7 = wdata_available7 & ~buffer_select; +assign wdata_en_pong8 = wdata_available8 & ~buffer_select; +assign wdata_en_pong9 = wdata_available9 & ~buffer_select; +assign wdata_en_pong10 = wdata_available10 & ~buffer_select; +assign wdata_en_pong11 = wdata_available11 & ~buffer_select; +assign wdata_en_pong12 = wdata_available12 & ~buffer_select; +assign wdata_en_pong13 = wdata_available13 & ~buffer_select; +assign wdata_en_pong14 = wdata_available14 & ~buffer_select; +assign wdata_en_pong15 = wdata_available15 & ~buffer_select; +assign wdata_en_pong16 = wdata_available16 & ~buffer_select; +assign wdata_en_pong17 = wdata_available17 & ~buffer_select; +assign wdata_en_pong18 = wdata_available18 & ~buffer_select; +assign wdata_en_pong19 = wdata_available19 & ~buffer_select; +assign wdata_en_pong20 = wdata_available20 & ~buffer_select; +assign wdata_en_pong21 = wdata_available21 & ~buffer_select; +assign wdata_en_pong22 = wdata_available22 & ~buffer_select; +assign wdata_en_pong23 = wdata_available23 & ~buffer_select; +assign wdata_en_pong24 = wdata_available24 & ~buffer_select; +assign wdata_en_pong25 = wdata_available25 & ~buffer_select; +assign wdata_en_pong26 = wdata_available26 & ~buffer_select; +assign wdata_en_pong27 = wdata_available27 & ~buffer_select; +assign wdata_en_pong28 = wdata_available28 & ~buffer_select; +assign wdata_en_pong29 = wdata_available29 & ~buffer_select; +assign wdata_en_pong30 = wdata_available30 & ~buffer_select; +assign wdata_en_pong31 = wdata_available31 & ~buffer_select; + +reg [7:0] addr_counter; +reg [`AWIDTH-1:0] waddr_accum0; +reg [`AWIDTH-1:0] waddr_accum1; +reg [`AWIDTH-1:0] waddr_accum2; +reg [`AWIDTH-1:0] waddr_accum3; +reg [`AWIDTH-1:0] waddr_accum4; +reg [`AWIDTH-1:0] waddr_accum5; +reg [`AWIDTH-1:0] waddr_accum6; +reg [`AWIDTH-1:0] waddr_accum7; +reg [`AWIDTH-1:0] waddr_accum8; +reg [`AWIDTH-1:0] waddr_accum9; +reg [`AWIDTH-1:0] waddr_accum10; +reg [`AWIDTH-1:0] waddr_accum11; +reg [`AWIDTH-1:0] waddr_accum12; +reg [`AWIDTH-1:0] waddr_accum13; +reg [`AWIDTH-1:0] waddr_accum14; +reg [`AWIDTH-1:0] waddr_accum15; +reg [`AWIDTH-1:0] waddr_accum16; +reg [`AWIDTH-1:0] waddr_accum17; +reg [`AWIDTH-1:0] waddr_accum18; +reg [`AWIDTH-1:0] waddr_accum19; +reg [`AWIDTH-1:0] waddr_accum20; +reg [`AWIDTH-1:0] waddr_accum21; +reg [`AWIDTH-1:0] waddr_accum22; +reg [`AWIDTH-1:0] waddr_accum23; +reg [`AWIDTH-1:0] waddr_accum24; +reg [`AWIDTH-1:0] waddr_accum25; +reg [`AWIDTH-1:0] waddr_accum26; +reg [`AWIDTH-1:0] waddr_accum27; +reg [`AWIDTH-1:0] waddr_accum28; +reg [`AWIDTH-1:0] waddr_accum29; +reg [`AWIDTH-1:0] waddr_accum30; +reg [`AWIDTH-1:0] waddr_accum31; +reg add_accum_mux0; +reg add_accum_mux1; +reg add_accum_mux2; +reg add_accum_mux3; +reg add_accum_mux4; +reg add_accum_mux5; +reg add_accum_mux6; +reg add_accum_mux7; +reg add_accum_mux8; +reg add_accum_mux9; +reg add_accum_mux10; +reg add_accum_mux11; +reg add_accum_mux12; +reg add_accum_mux13; +reg add_accum_mux14; +reg add_accum_mux15; +reg add_accum_mux16; +reg add_accum_mux17; +reg add_accum_mux18; +reg add_accum_mux19; +reg add_accum_mux20; +reg add_accum_mux21; +reg add_accum_mux22; +reg add_accum_mux23; +reg add_accum_mux24; +reg add_accum_mux25; +reg add_accum_mux26; +reg add_accum_mux27; +reg add_accum_mux28; +reg add_accum_mux29; +reg add_accum_mux30; +reg add_accum_mux31; + +always @ (posedge clk) begin + if (~wdata_available | (addr_counter == (k_dimension-1))) begin + add_accum_mux0 <= 0; + addr_counter <= 0; + end + else if (addr_counter == (`MAT_MUL_SIZE-1) & k_dimension != `MAT_MUL_SIZE) begin + add_accum_mux0 <= 1; + addr_counter <= addr_counter + 1; + end + else if (wdata_available) + addr_counter <= addr_counter + 1; +end + +reg start_pooling; +reg done_pooling; +reg [7:0] start_pooling_count; +always @ (posedge clk) begin + if (~resetn) + start_pooling <= 0; + //TODO: Note the hardcodign of value below. + //This value (8'd14) is supposed to be 2*MATMUL_SIZE-2. + //For 8x8 matmul, this is 8'd14 + //For 16x16 matmul, this should be 8'd30 + //For 32x32 matmul, this should be 8'd62 + else if (start_pooling_count > 8'd62) begin + start_pooling <= 0; + done_pooling <= 1; + end + else if (waddr_accum2 != 0 & wdata_available2 == 0) + start_pooling <= 1; +end + +always @ (posedge clk) begin + if (~resetn) + start_pooling_count <= 0; + else if (start_pooling) + start_pooling_count <= start_pooling_count + 1; +end + +reg buffer_select_accum; +wire buffer_select_pool; +reg start_pooling_d1; + +always @ (posedge clk) begin + if (buffer_select_pool) + buffer_select_accum <= 0; + else + buffer_select_accum <= 1; +end + +always @ (posedge clk) begin + start_pooling_d1 <= start_pooling; +end + +assign buffer_select_pool = start_pooling | start_pooling_d1; + +always @ (posedge clk) begin + add_accum_mux1 <= add_accum_mux0; + add_accum_mux2 <= add_accum_mux1; + add_accum_mux3 <= add_accum_mux2; + add_accum_mux4 <= add_accum_mux3; + add_accum_mux5 <= add_accum_mux4; + add_accum_mux6 <= add_accum_mux5; + add_accum_mux7 <= add_accum_mux6; + add_accum_mux8 <= add_accum_mux7; + add_accum_mux9 <= add_accum_mux8; + add_accum_mux10 <= add_accum_mux9; + add_accum_mux11 <= add_accum_mux10; + add_accum_mux12 <= add_accum_mux11; + add_accum_mux13 <= add_accum_mux12; + add_accum_mux14 <= add_accum_mux13; + add_accum_mux15 <= add_accum_mux14; + add_accum_mux16 <= add_accum_mux15; + add_accum_mux17 <= add_accum_mux16; + add_accum_mux18 <= add_accum_mux17; + add_accum_mux19 <= add_accum_mux18; + add_accum_mux20 <= add_accum_mux19; + add_accum_mux21 <= add_accum_mux20; + add_accum_mux22 <= add_accum_mux21; + add_accum_mux23 <= add_accum_mux22; + add_accum_mux24 <= add_accum_mux23; + add_accum_mux25 <= add_accum_mux24; + add_accum_mux26 <= add_accum_mux25; + add_accum_mux27 <= add_accum_mux26; + add_accum_mux28 <= add_accum_mux27; + add_accum_mux29 <= add_accum_mux28; + add_accum_mux30 <= add_accum_mux29; + add_accum_mux31 <= add_accum_mux30; +end + +reg [7:0] waddr_kdim; + +always @ (posedge clk) begin + if (~resetn) + waddr_accum0 <= start_waddr_accum0; + else if (((addr_counter & (`MAT_MUL_SIZE-1)) == (`MAT_MUL_SIZE-1)) & (waddr_kdim > 1)) begin + waddr_accum0 <= waddr_accum0 - (`MAT_MUL_SIZE -1); + end + else if (wdata_available) + waddr_accum0 <= waddr_accum0 + 1; +end + +always @ (posedge clk) begin + if (~resetn | (((addr_counter & (`MAT_MUL_SIZE-1)) == (`MAT_MUL_SIZE-1)) & (waddr_kdim == 1))) begin + waddr_kdim <= k_dimension >> `LOG2_MAT_MUL_SIZE; + end + else if (((addr_counter & (`MAT_MUL_SIZE-1)) == (`MAT_MUL_SIZE-1)) & (waddr_kdim > 1)) begin + waddr_kdim <= waddr_kdim - 1; + end +end + +always @ (posedge clk) begin + waddr_accum1 <= waddr_accum0; + waddr_accum2 <= waddr_accum1; + waddr_accum3 <= waddr_accum2; + waddr_accum4 <= waddr_accum3; + waddr_accum5 <= waddr_accum4; + waddr_accum6 <= waddr_accum5; + waddr_accum7 <= waddr_accum6; + waddr_accum8 <= waddr_accum7; + waddr_accum9 <= waddr_accum8; + waddr_accum10 <= waddr_accum9; + waddr_accum11 <= waddr_accum10; + waddr_accum12 <= waddr_accum11; + waddr_accum13 <= waddr_accum12; + waddr_accum14 <= waddr_accum13; + waddr_accum15 <= waddr_accum14; + waddr_accum16 <= waddr_accum15; + waddr_accum17 <= waddr_accum16; + waddr_accum18 <= waddr_accum17; + waddr_accum19 <= waddr_accum18; + waddr_accum20 <= waddr_accum19; + waddr_accum21 <= waddr_accum20; + waddr_accum22 <= waddr_accum21; + waddr_accum23 <= waddr_accum22; + waddr_accum24 <= waddr_accum23; + waddr_accum25 <= waddr_accum24; + waddr_accum26 <= waddr_accum25; + waddr_accum27 <= waddr_accum26; + waddr_accum28 <= waddr_accum27; + waddr_accum29 <= waddr_accum28; + waddr_accum30 <= waddr_accum29; + waddr_accum31 <= waddr_accum30; +end + +// Data going into the Accumulator Adders +wire [`DWIDTH-1:0] wdata_accum0_in; +wire [`DWIDTH-1:0] wdata_accum1_in; +wire [`DWIDTH-1:0] wdata_accum2_in; +wire [`DWIDTH-1:0] wdata_accum3_in; +wire [`DWIDTH-1:0] wdata_accum4_in; +wire [`DWIDTH-1:0] wdata_accum5_in; +wire [`DWIDTH-1:0] wdata_accum6_in; +wire [`DWIDTH-1:0] wdata_accum7_in; +wire [`DWIDTH-1:0] wdata_accum8_in; +wire [`DWIDTH-1:0] wdata_accum9_in; +wire [`DWIDTH-1:0] wdata_accum10_in; +wire [`DWIDTH-1:0] wdata_accum11_in; +wire [`DWIDTH-1:0] wdata_accum12_in; +wire [`DWIDTH-1:0] wdata_accum13_in; +wire [`DWIDTH-1:0] wdata_accum14_in; +wire [`DWIDTH-1:0] wdata_accum15_in; +wire [`DWIDTH-1:0] wdata_accum16_in; +wire [`DWIDTH-1:0] wdata_accum17_in; +wire [`DWIDTH-1:0] wdata_accum18_in; +wire [`DWIDTH-1:0] wdata_accum19_in; +wire [`DWIDTH-1:0] wdata_accum20_in; +wire [`DWIDTH-1:0] wdata_accum21_in; +wire [`DWIDTH-1:0] wdata_accum22_in; +wire [`DWIDTH-1:0] wdata_accum23_in; +wire [`DWIDTH-1:0] wdata_accum24_in; +wire [`DWIDTH-1:0] wdata_accum25_in; +wire [`DWIDTH-1:0] wdata_accum26_in; +wire [`DWIDTH-1:0] wdata_accum27_in; +wire [`DWIDTH-1:0] wdata_accum28_in; +wire [`DWIDTH-1:0] wdata_accum29_in; +wire [`DWIDTH-1:0] wdata_accum30_in; +wire [`DWIDTH-1:0] wdata_accum31_in; + +// Data written into the PING Accumulators +wire [`DWIDTH-1:0] wdata_accum0_ping; +wire [`DWIDTH-1:0] wdata_accum1_ping; +wire [`DWIDTH-1:0] wdata_accum2_ping; +wire [`DWIDTH-1:0] wdata_accum3_ping; +wire [`DWIDTH-1:0] wdata_accum4_ping; +wire [`DWIDTH-1:0] wdata_accum5_ping; +wire [`DWIDTH-1:0] wdata_accum6_ping; +wire [`DWIDTH-1:0] wdata_accum7_ping; +wire [`DWIDTH-1:0] wdata_accum8_ping; +wire [`DWIDTH-1:0] wdata_accum9_ping; +wire [`DWIDTH-1:0] wdata_accum10_ping; +wire [`DWIDTH-1:0] wdata_accum11_ping; +wire [`DWIDTH-1:0] wdata_accum12_ping; +wire [`DWIDTH-1:0] wdata_accum13_ping; +wire [`DWIDTH-1:0] wdata_accum14_ping; +wire [`DWIDTH-1:0] wdata_accum15_ping; +wire [`DWIDTH-1:0] wdata_accum16_ping; +wire [`DWIDTH-1:0] wdata_accum17_ping; +wire [`DWIDTH-1:0] wdata_accum18_ping; +wire [`DWIDTH-1:0] wdata_accum19_ping; +wire [`DWIDTH-1:0] wdata_accum20_ping; +wire [`DWIDTH-1:0] wdata_accum21_ping; +wire [`DWIDTH-1:0] wdata_accum22_ping; +wire [`DWIDTH-1:0] wdata_accum23_ping; +wire [`DWIDTH-1:0] wdata_accum24_ping; +wire [`DWIDTH-1:0] wdata_accum25_ping; +wire [`DWIDTH-1:0] wdata_accum26_ping; +wire [`DWIDTH-1:0] wdata_accum27_ping; +wire [`DWIDTH-1:0] wdata_accum28_ping; +wire [`DWIDTH-1:0] wdata_accum29_ping; +wire [`DWIDTH-1:0] wdata_accum30_ping; +wire [`DWIDTH-1:0] wdata_accum31_ping; + +wire [`AWIDTH-1:0] raddr_buffer0; +wire [`AWIDTH-1:0] raddr_buffer1; +wire [`AWIDTH-1:0] raddr_buffer2; +wire [`AWIDTH-1:0] raddr_buffer3; +wire [`AWIDTH-1:0] raddr_buffer4; +wire [`AWIDTH-1:0] raddr_buffer5; +wire [`AWIDTH-1:0] raddr_buffer6; +wire [`AWIDTH-1:0] raddr_buffer7; +wire [`AWIDTH-1:0] raddr_buffer8; +wire [`AWIDTH-1:0] raddr_buffer9; +wire [`AWIDTH-1:0] raddr_buffer10; +wire [`AWIDTH-1:0] raddr_buffer11; +wire [`AWIDTH-1:0] raddr_buffer12; +wire [`AWIDTH-1:0] raddr_buffer13; +wire [`AWIDTH-1:0] raddr_buffer14; +wire [`AWIDTH-1:0] raddr_buffer15; +wire [`AWIDTH-1:0] raddr_buffer16; +wire [`AWIDTH-1:0] raddr_buffer17; +wire [`AWIDTH-1:0] raddr_buffer18; +wire [`AWIDTH-1:0] raddr_buffer19; +wire [`AWIDTH-1:0] raddr_buffer20; +wire [`AWIDTH-1:0] raddr_buffer21; +wire [`AWIDTH-1:0] raddr_buffer22; +wire [`AWIDTH-1:0] raddr_buffer23; +wire [`AWIDTH-1:0] raddr_buffer24; +wire [`AWIDTH-1:0] raddr_buffer25; +wire [`AWIDTH-1:0] raddr_buffer26; +wire [`AWIDTH-1:0] raddr_buffer27; +wire [`AWIDTH-1:0] raddr_buffer28; +wire [`AWIDTH-1:0] raddr_buffer29; +wire [`AWIDTH-1:0] raddr_buffer30; +wire [`AWIDTH-1:0] raddr_buffer31; + +wire [`DWIDTH-1:0] rdata_buffer0; +wire [`DWIDTH-1:0] rdata_buffer1; +wire [`DWIDTH-1:0] rdata_buffer2; +wire [`DWIDTH-1:0] rdata_buffer3; +wire [`DWIDTH-1:0] rdata_buffer4; +wire [`DWIDTH-1:0] rdata_buffer5; +wire [`DWIDTH-1:0] rdata_buffer6; +wire [`DWIDTH-1:0] rdata_buffer7; +wire [`DWIDTH-1:0] rdata_buffer8; +wire [`DWIDTH-1:0] rdata_buffer9; +wire [`DWIDTH-1:0] rdata_buffer10; +wire [`DWIDTH-1:0] rdata_buffer11; +wire [`DWIDTH-1:0] rdata_buffer12; +wire [`DWIDTH-1:0] rdata_buffer13; +wire [`DWIDTH-1:0] rdata_buffer14; +wire [`DWIDTH-1:0] rdata_buffer15; +wire [`DWIDTH-1:0] rdata_buffer16; +wire [`DWIDTH-1:0] rdata_buffer17; +wire [`DWIDTH-1:0] rdata_buffer18; +wire [`DWIDTH-1:0] rdata_buffer19; +wire [`DWIDTH-1:0] rdata_buffer20; +wire [`DWIDTH-1:0] rdata_buffer21; +wire [`DWIDTH-1:0] rdata_buffer22; +wire [`DWIDTH-1:0] rdata_buffer23; +wire [`DWIDTH-1:0] rdata_buffer24; +wire [`DWIDTH-1:0] rdata_buffer25; +wire [`DWIDTH-1:0] rdata_buffer26; +wire [`DWIDTH-1:0] rdata_buffer27; +wire [`DWIDTH-1:0] rdata_buffer28; +wire [`DWIDTH-1:0] rdata_buffer29; +wire [`DWIDTH-1:0] rdata_buffer30; +wire [`DWIDTH-1:0] rdata_buffer31; + +wire [`DWIDTH-1:0] rdata_buffer0_pong; +wire [`DWIDTH-1:0] rdata_buffer1_pong; +wire [`DWIDTH-1:0] rdata_buffer2_pong; +wire [`DWIDTH-1:0] rdata_buffer3_pong; +wire [`DWIDTH-1:0] rdata_buffer4_pong; +wire [`DWIDTH-1:0] rdata_buffer5_pong; +wire [`DWIDTH-1:0] rdata_buffer6_pong; +wire [`DWIDTH-1:0] rdata_buffer7_pong; +wire [`DWIDTH-1:0] rdata_buffer8_pong; +wire [`DWIDTH-1:0] rdata_buffer9_pong; +wire [`DWIDTH-1:0] rdata_buffer10_pong; +wire [`DWIDTH-1:0] rdata_buffer11_pong; +wire [`DWIDTH-1:0] rdata_buffer12_pong; +wire [`DWIDTH-1:0] rdata_buffer13_pong; +wire [`DWIDTH-1:0] rdata_buffer14_pong; +wire [`DWIDTH-1:0] rdata_buffer15_pong; +wire [`DWIDTH-1:0] rdata_buffer16_pong; +wire [`DWIDTH-1:0] rdata_buffer17_pong; +wire [`DWIDTH-1:0] rdata_buffer18_pong; +wire [`DWIDTH-1:0] rdata_buffer19_pong; +wire [`DWIDTH-1:0] rdata_buffer20_pong; +wire [`DWIDTH-1:0] rdata_buffer21_pong; +wire [`DWIDTH-1:0] rdata_buffer22_pong; +wire [`DWIDTH-1:0] rdata_buffer23_pong; +wire [`DWIDTH-1:0] rdata_buffer24_pong; +wire [`DWIDTH-1:0] rdata_buffer25_pong; +wire [`DWIDTH-1:0] rdata_buffer26_pong; +wire [`DWIDTH-1:0] rdata_buffer27_pong; +wire [`DWIDTH-1:0] rdata_buffer28_pong; +wire [`DWIDTH-1:0] rdata_buffer29_pong; +wire [`DWIDTH-1:0] rdata_buffer30_pong; +wire [`DWIDTH-1:0] rdata_buffer31_pong; + +// Based on the Accumulator Adder MUX select signal either 0 or data read from the RAM goes into the Adder +assign wdata_accum0_in = (~add_accum_mux0)? 8'b0 : (buffer_select)? rdata_buffer0 : rdata_buffer0_pong; +assign wdata_accum1_in = (~add_accum_mux1)? 8'b0 : (buffer_select)? rdata_buffer1 : rdata_buffer1_pong; +assign wdata_accum2_in = (~add_accum_mux2)? 8'b0 : (buffer_select)? rdata_buffer2 : rdata_buffer2_pong; +assign wdata_accum3_in = (~add_accum_mux3)? 8'b0 : (buffer_select)? rdata_buffer3 : rdata_buffer3_pong; +assign wdata_accum4_in = (~add_accum_mux4)? 8'b0 : (buffer_select)? rdata_buffer4 : rdata_buffer4_pong; +assign wdata_accum5_in = (~add_accum_mux5)? 8'b0 : (buffer_select)? rdata_buffer5 : rdata_buffer5_pong; +assign wdata_accum6_in = (~add_accum_mux6)? 8'b0 : (buffer_select)? rdata_buffer6 : rdata_buffer6_pong; +assign wdata_accum7_in = (~add_accum_mux7)? 8'b0 : (buffer_select)? rdata_buffer7 : rdata_buffer7_pong; +assign wdata_accum8_in = (~add_accum_mux8)? 8'b0 : (buffer_select)? rdata_buffer8 : rdata_buffer8_pong; +assign wdata_accum9_in = (~add_accum_mux9)? 8'b0 : (buffer_select)? rdata_buffer9 : rdata_buffer9_pong; +assign wdata_accum10_in = (~add_accum_mux10)? 8'b0 : (buffer_select)? rdata_buffer10 : rdata_buffer10_pong; +assign wdata_accum11_in = (~add_accum_mux11)? 8'b0 : (buffer_select)? rdata_buffer11 : rdata_buffer11_pong; +assign wdata_accum12_in = (~add_accum_mux12)? 8'b0 : (buffer_select)? rdata_buffer12 : rdata_buffer12_pong; +assign wdata_accum13_in = (~add_accum_mux13)? 8'b0 : (buffer_select)? rdata_buffer13 : rdata_buffer13_pong; +assign wdata_accum14_in = (~add_accum_mux14)? 8'b0 : (buffer_select)? rdata_buffer14 : rdata_buffer14_pong; +assign wdata_accum15_in = (~add_accum_mux15)? 8'b0 : (buffer_select)? rdata_buffer15 : rdata_buffer15_pong; +assign wdata_accum16_in = (~add_accum_mux16)? 8'b0 : (buffer_select)? rdata_buffer16 : rdata_buffer16_pong; +assign wdata_accum17_in = (~add_accum_mux17)? 8'b0 : (buffer_select)? rdata_buffer17 : rdata_buffer17_pong; +assign wdata_accum18_in = (~add_accum_mux18)? 8'b0 : (buffer_select)? rdata_buffer18 : rdata_buffer18_pong; +assign wdata_accum19_in = (~add_accum_mux19)? 8'b0 : (buffer_select)? rdata_buffer19 : rdata_buffer19_pong; +assign wdata_accum20_in = (~add_accum_mux20)? 8'b0 : (buffer_select)? rdata_buffer20 : rdata_buffer20_pong; +assign wdata_accum21_in = (~add_accum_mux21)? 8'b0 : (buffer_select)? rdata_buffer21 : rdata_buffer21_pong; +assign wdata_accum22_in = (~add_accum_mux22)? 8'b0 : (buffer_select)? rdata_buffer22 : rdata_buffer22_pong; +assign wdata_accum23_in = (~add_accum_mux23)? 8'b0 : (buffer_select)? rdata_buffer23 : rdata_buffer23_pong; +assign wdata_accum24_in = (~add_accum_mux24)? 8'b0 : (buffer_select)? rdata_buffer24 : rdata_buffer24_pong; +assign wdata_accum25_in = (~add_accum_mux25)? 8'b0 : (buffer_select)? rdata_buffer25 : rdata_buffer25_pong; +assign wdata_accum26_in = (~add_accum_mux26)? 8'b0 : (buffer_select)? rdata_buffer26 : rdata_buffer26_pong; +assign wdata_accum27_in = (~add_accum_mux27)? 8'b0 : (buffer_select)? rdata_buffer27 : rdata_buffer27_pong; +assign wdata_accum28_in = (~add_accum_mux28)? 8'b0 : (buffer_select)? rdata_buffer28 : rdata_buffer28_pong; +assign wdata_accum29_in = (~add_accum_mux29)? 8'b0 : (buffer_select)? rdata_buffer29 : rdata_buffer29_pong; +assign wdata_accum30_in = (~add_accum_mux30)? 8'b0 : (buffer_select)? rdata_buffer30 : rdata_buffer30_pong; +assign wdata_accum31_in = (~add_accum_mux31)? 8'b0 : (buffer_select)? rdata_buffer31 : rdata_buffer31_pong; + +reg [`AWIDTH-1:0] raddr_accum0; +reg [`AWIDTH-1:0] raddr_accum1; +reg [`AWIDTH-1:0] raddr_accum2; +reg [`AWIDTH-1:0] raddr_accum3; +reg [`AWIDTH-1:0] raddr_accum4; +reg [`AWIDTH-1:0] raddr_accum5; +reg [`AWIDTH-1:0] raddr_accum6; +reg [`AWIDTH-1:0] raddr_accum7; +reg [`AWIDTH-1:0] raddr_accum8; +reg [`AWIDTH-1:0] raddr_accum9; +reg [`AWIDTH-1:0] raddr_accum10; +reg [`AWIDTH-1:0] raddr_accum11; +reg [`AWIDTH-1:0] raddr_accum12; +reg [`AWIDTH-1:0] raddr_accum13; +reg [`AWIDTH-1:0] raddr_accum14; +reg [`AWIDTH-1:0] raddr_accum15; +reg [`AWIDTH-1:0] raddr_accum16; +reg [`AWIDTH-1:0] raddr_accum17; +reg [`AWIDTH-1:0] raddr_accum18; +reg [`AWIDTH-1:0] raddr_accum19; +reg [`AWIDTH-1:0] raddr_accum20; +reg [`AWIDTH-1:0] raddr_accum21; +reg [`AWIDTH-1:0] raddr_accum22; +reg [`AWIDTH-1:0] raddr_accum23; +reg [`AWIDTH-1:0] raddr_accum24; +reg [`AWIDTH-1:0] raddr_accum25; +reg [`AWIDTH-1:0] raddr_accum26; +reg [`AWIDTH-1:0] raddr_accum27; +reg [`AWIDTH-1:0] raddr_accum28; +reg [`AWIDTH-1:0] raddr_accum29; +reg [`AWIDTH-1:0] raddr_accum30; +reg [`AWIDTH-1:0] raddr_accum31; + +// Start reading the address written to after 31 clock cycles to calculate partial sums +always @ (posedge clk) begin + raddr_accum0 <= waddr_accum30; // waddr_accum30 = (waddr_accum0 delayed by 30 clock cycles) + raddr_accum1 <= raddr_accum0; + raddr_accum2 <= raddr_accum1; + raddr_accum3 <= raddr_accum2; + raddr_accum4 <= raddr_accum3; + raddr_accum5 <= raddr_accum4; + raddr_accum6 <= raddr_accum5; + raddr_accum7 <= raddr_accum6; + raddr_accum8 <= raddr_accum7; + raddr_accum9 <= raddr_accum8; + raddr_accum10 <= raddr_accum9; + raddr_accum11 <= raddr_accum10; + raddr_accum12 <= raddr_accum11; + raddr_accum13 <= raddr_accum12; + raddr_accum14 <= raddr_accum13; + raddr_accum15 <= raddr_accum14; + raddr_accum16 <= raddr_accum15; + raddr_accum17 <= raddr_accum16; + raddr_accum18 <= raddr_accum17; + raddr_accum19 <= raddr_accum18; + raddr_accum20 <= raddr_accum19; + raddr_accum21 <= raddr_accum20; + raddr_accum22 <= raddr_accum21; + raddr_accum23 <= raddr_accum22; + raddr_accum24 <= raddr_accum23; + raddr_accum25 <= raddr_accum24; + raddr_accum26 <= raddr_accum25; + raddr_accum27 <= raddr_accum26; + raddr_accum28 <= raddr_accum27; + raddr_accum29 <= raddr_accum28; + raddr_accum30 <= raddr_accum29; + raddr_accum31 <= raddr_accum30; +end + +// Port 0 for each RAM is used for writing the data coming from the matmul as of now, not used for reading +wire [`DWIDTH-1:0] accum0_ping_q0_NC; +wire [`DWIDTH-1:0] accum1_ping_q0_NC; +wire [`DWIDTH-1:0] accum2_ping_q0_NC; +wire [`DWIDTH-1:0] accum3_ping_q0_NC; +wire [`DWIDTH-1:0] accum4_ping_q0_NC; +wire [`DWIDTH-1:0] accum5_ping_q0_NC; +wire [`DWIDTH-1:0] accum6_ping_q0_NC; +wire [`DWIDTH-1:0] accum7_ping_q0_NC; +wire [`DWIDTH-1:0] accum8_ping_q0_NC; +wire [`DWIDTH-1:0] accum9_ping_q0_NC; +wire [`DWIDTH-1:0] accum10_ping_q0_NC; +wire [`DWIDTH-1:0] accum11_ping_q0_NC; +wire [`DWIDTH-1:0] accum12_ping_q0_NC; +wire [`DWIDTH-1:0] accum13_ping_q0_NC; +wire [`DWIDTH-1:0] accum14_ping_q0_NC; +wire [`DWIDTH-1:0] accum15_ping_q0_NC; +wire [`DWIDTH-1:0] accum16_ping_q0_NC; +wire [`DWIDTH-1:0] accum17_ping_q0_NC; +wire [`DWIDTH-1:0] accum18_ping_q0_NC; +wire [`DWIDTH-1:0] accum19_ping_q0_NC; +wire [`DWIDTH-1:0] accum20_ping_q0_NC; +wire [`DWIDTH-1:0] accum21_ping_q0_NC; +wire [`DWIDTH-1:0] accum22_ping_q0_NC; +wire [`DWIDTH-1:0] accum23_ping_q0_NC; +wire [`DWIDTH-1:0] accum24_ping_q0_NC; +wire [`DWIDTH-1:0] accum25_ping_q0_NC; +wire [`DWIDTH-1:0] accum26_ping_q0_NC; +wire [`DWIDTH-1:0] accum27_ping_q0_NC; +wire [`DWIDTH-1:0] accum28_ping_q0_NC; +wire [`DWIDTH-1:0] accum29_ping_q0_NC; +wire [`DWIDTH-1:0] accum30_ping_q0_NC; +wire [`DWIDTH-1:0] accum31_ping_q0_NC; +wire [`DWIDTH-1:0] accum0_pong_q0_NC; +wire [`DWIDTH-1:0] accum1_pong_q0_NC; +wire [`DWIDTH-1:0] accum2_pong_q0_NC; +wire [`DWIDTH-1:0] accum3_pong_q0_NC; +wire [`DWIDTH-1:0] accum4_pong_q0_NC; +wire [`DWIDTH-1:0] accum5_pong_q0_NC; +wire [`DWIDTH-1:0] accum6_pong_q0_NC; +wire [`DWIDTH-1:0] accum7_pong_q0_NC; +wire [`DWIDTH-1:0] accum8_pong_q0_NC; +wire [`DWIDTH-1:0] accum9_pong_q0_NC; +wire [`DWIDTH-1:0] accum10_pong_q0_NC; +wire [`DWIDTH-1:0] accum11_pong_q0_NC; +wire [`DWIDTH-1:0] accum12_pong_q0_NC; +wire [`DWIDTH-1:0] accum13_pong_q0_NC; +wire [`DWIDTH-1:0] accum14_pong_q0_NC; +wire [`DWIDTH-1:0] accum15_pong_q0_NC; +wire [`DWIDTH-1:0] accum16_pong_q0_NC; +wire [`DWIDTH-1:0] accum17_pong_q0_NC; +wire [`DWIDTH-1:0] accum18_pong_q0_NC; +wire [`DWIDTH-1:0] accum19_pong_q0_NC; +wire [`DWIDTH-1:0] accum20_pong_q0_NC; +wire [`DWIDTH-1:0] accum21_pong_q0_NC; +wire [`DWIDTH-1:0] accum22_pong_q0_NC; +wire [`DWIDTH-1:0] accum23_pong_q0_NC; +wire [`DWIDTH-1:0] accum24_pong_q0_NC; +wire [`DWIDTH-1:0] accum25_pong_q0_NC; +wire [`DWIDTH-1:0] accum26_pong_q0_NC; +wire [`DWIDTH-1:0] accum27_pong_q0_NC; +wire [`DWIDTH-1:0] accum28_pong_q0_NC; +wire [`DWIDTH-1:0] accum29_pong_q0_NC; +wire [`DWIDTH-1:0] accum30_pong_q0_NC; +wire [`DWIDTH-1:0] accum31_pong_q0_NC; + +reg buffer_select_pool1; +reg buffer_select_pool2; +reg buffer_select_pool3; +reg buffer_select_pool4; +reg buffer_select_pool5; +reg buffer_select_pool6; +reg buffer_select_pool7; +reg buffer_select_pool8; +reg buffer_select_pool9; +reg buffer_select_pool10; +reg buffer_select_pool11; +reg buffer_select_pool12; +reg buffer_select_pool13; +reg buffer_select_pool14; +reg buffer_select_pool15; +reg buffer_select_pool16; +reg buffer_select_pool17; +reg buffer_select_pool18; +reg buffer_select_pool19; +reg buffer_select_pool20; +reg buffer_select_pool21; +reg buffer_select_pool22; +reg buffer_select_pool23; +reg buffer_select_pool24; +reg buffer_select_pool25; +reg buffer_select_pool26; +reg buffer_select_pool27; +reg buffer_select_pool28; +reg buffer_select_pool29; +reg buffer_select_pool30; +reg buffer_select_pool31; + +always @ (posedge clk) begin +buffer_select_pool1 <= buffer_select_pool; +buffer_select_pool2 <= buffer_select_pool1; +buffer_select_pool3 <= buffer_select_pool2; +buffer_select_pool4 <= buffer_select_pool3; +buffer_select_pool5 <= buffer_select_pool4; +buffer_select_pool6 <= buffer_select_pool5; +buffer_select_pool7 <= buffer_select_pool6; +buffer_select_pool8 <= buffer_select_pool7; +buffer_select_pool9 <= buffer_select_pool8; +buffer_select_pool10 <= buffer_select_pool9; +buffer_select_pool11 <= buffer_select_pool10; +buffer_select_pool12 <= buffer_select_pool11; +buffer_select_pool13 <= buffer_select_pool12; +buffer_select_pool14 <= buffer_select_pool13; +buffer_select_pool15 <= buffer_select_pool14; +buffer_select_pool16 <= buffer_select_pool15; +buffer_select_pool17 <= buffer_select_pool16; +buffer_select_pool18 <= buffer_select_pool17; +buffer_select_pool19 <= buffer_select_pool18; +buffer_select_pool20 <= buffer_select_pool19; +buffer_select_pool21 <= buffer_select_pool20; +buffer_select_pool22 <= buffer_select_pool21; +buffer_select_pool23 <= buffer_select_pool22; +buffer_select_pool24 <= buffer_select_pool23; +buffer_select_pool25 <= buffer_select_pool24; +buffer_select_pool26 <= buffer_select_pool25; +buffer_select_pool27 <= buffer_select_pool26; +buffer_select_pool28 <= buffer_select_pool27; +buffer_select_pool29 <= buffer_select_pool28; +buffer_select_pool30 <= buffer_select_pool29; +buffer_select_pool31 <= buffer_select_pool30; +end + +reg buffer_select_accum1; +reg buffer_select_accum2; +reg buffer_select_accum3; +reg buffer_select_accum4; +reg buffer_select_accum5; +reg buffer_select_accum6; +reg buffer_select_accum7; +reg buffer_select_accum8; +reg buffer_select_accum9; +reg buffer_select_accum10; +reg buffer_select_accum11; +reg buffer_select_accum12; +reg buffer_select_accum13; +reg buffer_select_accum14; +reg buffer_select_accum15; +reg buffer_select_accum16; +reg buffer_select_accum17; +reg buffer_select_accum18; +reg buffer_select_accum19; +reg buffer_select_accum20; +reg buffer_select_accum21; +reg buffer_select_accum22; +reg buffer_select_accum23; +reg buffer_select_accum24; +reg buffer_select_accum25; +reg buffer_select_accum26; +reg buffer_select_accum27; +reg buffer_select_accum28; +reg buffer_select_accum29; +reg buffer_select_accum30; +reg buffer_select_accum31; + +always @ (posedge clk) begin +buffer_select_accum1 <= buffer_select_accum; +buffer_select_accum2 <= buffer_select_accum1; +buffer_select_accum3 <= buffer_select_accum2; +buffer_select_accum4 <= buffer_select_accum3; +buffer_select_accum5 <= buffer_select_accum4; +buffer_select_accum6 <= buffer_select_accum5; +buffer_select_accum7 <= buffer_select_accum6; +buffer_select_accum8 <= buffer_select_accum7; +buffer_select_accum9 <= buffer_select_accum8; +buffer_select_accum10 <= buffer_select_accum9; +buffer_select_accum11 <= buffer_select_accum10; +buffer_select_accum12 <= buffer_select_accum11; +buffer_select_accum13 <= buffer_select_accum12; +buffer_select_accum14 <= buffer_select_accum13; +buffer_select_accum15 <= buffer_select_accum14; +buffer_select_accum16 <= buffer_select_accum15; +buffer_select_accum17 <= buffer_select_accum16; +buffer_select_accum18 <= buffer_select_accum17; +buffer_select_accum19 <= buffer_select_accum18; +buffer_select_accum20 <= buffer_select_accum19; +buffer_select_accum21 <= buffer_select_accum20; +buffer_select_accum22 <= buffer_select_accum21; +buffer_select_accum23 <= buffer_select_accum22; +buffer_select_accum24 <= buffer_select_accum23; +buffer_select_accum25 <= buffer_select_accum24; +buffer_select_accum26 <= buffer_select_accum25; +buffer_select_accum27 <= buffer_select_accum26; +buffer_select_accum28 <= buffer_select_accum27; +buffer_select_accum29 <= buffer_select_accum28; +buffer_select_accum30 <= buffer_select_accum29; +buffer_select_accum31 <= buffer_select_accum30; +end + +assign raddr_buffer0 = (buffer_select_pool)? raddr_accum0_pool : (buffer_select_accum)? raddr_accum0:11'd0; +assign raddr_buffer1 = (buffer_select_pool1)? raddr_accum1_pool : (buffer_select_accum1)? raddr_accum1:11'd0; +assign raddr_buffer2 = (buffer_select_pool2)? raddr_accum2_pool : (buffer_select_accum2)? raddr_accum2:11'd0; +assign raddr_buffer3 = (buffer_select_pool3)? raddr_accum3_pool : (buffer_select_accum3)? raddr_accum3:11'd0; +assign raddr_buffer4 = (buffer_select_pool4)? raddr_accum4_pool : (buffer_select_accum4)? raddr_accum4:11'd0; +assign raddr_buffer5 = (buffer_select_pool5)? raddr_accum5_pool : (buffer_select_accum5)? raddr_accum5:11'd0; +assign raddr_buffer6 = (buffer_select_pool6)? raddr_accum6_pool : (buffer_select_accum6)? raddr_accum6:11'd0; +assign raddr_buffer7 = (buffer_select_pool7)? raddr_accum7_pool : (buffer_select_accum7)? raddr_accum7:11'd0; +assign raddr_buffer8 = (buffer_select_pool8)? raddr_accum8_pool : (buffer_select_accum8)? raddr_accum8:11'd0; +assign raddr_buffer9 = (buffer_select_pool9)? raddr_accum9_pool : (buffer_select_accum9)? raddr_accum9:11'd0; +assign raddr_buffer10 = (buffer_select_pool10)? raddr_accum10_pool : (buffer_select_accum10)? raddr_accum10:11'd0; +assign raddr_buffer11 = (buffer_select_pool11)? raddr_accum11_pool : (buffer_select_accum11)? raddr_accum11:11'd0; +assign raddr_buffer12 = (buffer_select_pool12)? raddr_accum12_pool : (buffer_select_accum12)? raddr_accum12:11'd0; +assign raddr_buffer13 = (buffer_select_pool13)? raddr_accum13_pool : (buffer_select_accum13)? raddr_accum13:11'd0; +assign raddr_buffer14 = (buffer_select_pool14)? raddr_accum14_pool : (buffer_select_accum14)? raddr_accum14:11'd0; +assign raddr_buffer15 = (buffer_select_pool15)? raddr_accum15_pool : (buffer_select_accum15)? raddr_accum15:11'd0; +assign raddr_buffer16 = (buffer_select_pool16)? raddr_accum16_pool : (buffer_select_accum16)? raddr_accum16:11'd0; +assign raddr_buffer17 = (buffer_select_pool17)? raddr_accum17_pool : (buffer_select_accum17)? raddr_accum17:11'd0; +assign raddr_buffer18 = (buffer_select_pool18)? raddr_accum18_pool : (buffer_select_accum18)? raddr_accum18:11'd0; +assign raddr_buffer19 = (buffer_select_pool19)? raddr_accum19_pool : (buffer_select_accum19)? raddr_accum19:11'd0; +assign raddr_buffer20 = (buffer_select_pool20)? raddr_accum20_pool : (buffer_select_accum20)? raddr_accum20:11'd0; +assign raddr_buffer21 = (buffer_select_pool21)? raddr_accum21_pool : (buffer_select_accum21)? raddr_accum21:11'd0; +assign raddr_buffer22 = (buffer_select_pool22)? raddr_accum22_pool : (buffer_select_accum22)? raddr_accum22:11'd0; +assign raddr_buffer23 = (buffer_select_pool23)? raddr_accum23_pool : (buffer_select_accum23)? raddr_accum23:11'd0; +assign raddr_buffer24 = (buffer_select_pool24)? raddr_accum24_pool : (buffer_select_accum24)? raddr_accum24:11'd0; +assign raddr_buffer25 = (buffer_select_pool25)? raddr_accum25_pool : (buffer_select_accum25)? raddr_accum25:11'd0; +assign raddr_buffer26 = (buffer_select_pool26)? raddr_accum26_pool : (buffer_select_accum26)? raddr_accum26:11'd0; +assign raddr_buffer27 = (buffer_select_pool27)? raddr_accum27_pool : (buffer_select_accum27)? raddr_accum27:11'd0; +assign raddr_buffer28 = (buffer_select_pool28)? raddr_accum28_pool : (buffer_select_accum28)? raddr_accum28:11'd0; +assign raddr_buffer29 = (buffer_select_pool29)? raddr_accum29_pool : (buffer_select_accum29)? raddr_accum29:11'd0; +assign raddr_buffer30 = (buffer_select_pool30)? raddr_accum30_pool : (buffer_select_accum30)? raddr_accum30:11'd0; +assign raddr_buffer31 = (buffer_select_pool31)? raddr_accum31_pool : (buffer_select_accum31)? raddr_accum31:11'd0; + +assign rdata_accum0_pool = (buffer_select_pool)? (buffer_select)? rdata_buffer0 : rdata_buffer0_pong : 8'b0; +assign rdata_accum1_pool = (buffer_select_pool1)? (buffer_select)? rdata_buffer1 : rdata_buffer1_pong : 8'b0; +assign rdata_accum2_pool = (buffer_select_pool2)? (buffer_select)? rdata_buffer2 : rdata_buffer2_pong : 8'b0; +assign rdata_accum3_pool = (buffer_select_pool3)? (buffer_select)? rdata_buffer3 : rdata_buffer3_pong : 8'b0; +assign rdata_accum4_pool = (buffer_select_pool4)? (buffer_select)? rdata_buffer4 : rdata_buffer4_pong : 8'b0; +assign rdata_accum5_pool = (buffer_select_pool5)? (buffer_select)? rdata_buffer5 : rdata_buffer5_pong : 8'b0; +assign rdata_accum6_pool = (buffer_select_pool6)? (buffer_select)? rdata_buffer6 : rdata_buffer6_pong : 8'b0; +assign rdata_accum7_pool = (buffer_select_pool7)? (buffer_select)? rdata_buffer7 : rdata_buffer7_pong : 8'b0; +assign rdata_accum8_pool = (buffer_select_pool8)? (buffer_select)? rdata_buffer8 : rdata_buffer8_pong : 8'b0; +assign rdata_accum9_pool = (buffer_select_pool9)? (buffer_select)? rdata_buffer9 : rdata_buffer9_pong : 8'b0; +assign rdata_accum10_pool = (buffer_select_pool10)? (buffer_select)? rdata_buffer10 : rdata_buffer10_pong : 8'b0; +assign rdata_accum11_pool = (buffer_select_pool11)? (buffer_select)? rdata_buffer11 : rdata_buffer11_pong : 8'b0; +assign rdata_accum12_pool = (buffer_select_pool12)? (buffer_select)? rdata_buffer12 : rdata_buffer12_pong : 8'b0; +assign rdata_accum13_pool = (buffer_select_pool13)? (buffer_select)? rdata_buffer13 : rdata_buffer13_pong : 8'b0; +assign rdata_accum14_pool = (buffer_select_pool14)? (buffer_select)? rdata_buffer14 : rdata_buffer14_pong : 8'b0; +assign rdata_accum15_pool = (buffer_select_pool15)? (buffer_select)? rdata_buffer15 : rdata_buffer15_pong : 8'b0; +assign rdata_accum16_pool = (buffer_select_pool16)? (buffer_select)? rdata_buffer16 : rdata_buffer16_pong : 8'b0; +assign rdata_accum17_pool = (buffer_select_pool17)? (buffer_select)? rdata_buffer17 : rdata_buffer17_pong : 8'b0; +assign rdata_accum18_pool = (buffer_select_pool18)? (buffer_select)? rdata_buffer18 : rdata_buffer18_pong : 8'b0; +assign rdata_accum19_pool = (buffer_select_pool19)? (buffer_select)? rdata_buffer19 : rdata_buffer19_pong : 8'b0; +assign rdata_accum20_pool = (buffer_select_pool20)? (buffer_select)? rdata_buffer20 : rdata_buffer20_pong : 8'b0; +assign rdata_accum21_pool = (buffer_select_pool21)? (buffer_select)? rdata_buffer21 : rdata_buffer21_pong : 8'b0; +assign rdata_accum22_pool = (buffer_select_pool22)? (buffer_select)? rdata_buffer22 : rdata_buffer22_pong : 8'b0; +assign rdata_accum23_pool = (buffer_select_pool23)? (buffer_select)? rdata_buffer23 : rdata_buffer23_pong : 8'b0; +assign rdata_accum24_pool = (buffer_select_pool24)? (buffer_select)? rdata_buffer24 : rdata_buffer24_pong : 8'b0; +assign rdata_accum25_pool = (buffer_select_pool25)? (buffer_select)? rdata_buffer25 : rdata_buffer25_pong : 8'b0; +assign rdata_accum26_pool = (buffer_select_pool26)? (buffer_select)? rdata_buffer26 : rdata_buffer26_pong : 8'b0; +assign rdata_accum27_pool = (buffer_select_pool27)? (buffer_select)? rdata_buffer27 : rdata_buffer27_pong : 8'b0; +assign rdata_accum28_pool = (buffer_select_pool28)? (buffer_select)? rdata_buffer28 : rdata_buffer28_pong : 8'b0; +assign rdata_accum29_pool = (buffer_select_pool29)? (buffer_select)? rdata_buffer29 : rdata_buffer29_pong : 8'b0; +assign rdata_accum30_pool = (buffer_select_pool30)? (buffer_select)? rdata_buffer30 : rdata_buffer30_pong : 8'b0; +assign rdata_accum31_pool = (buffer_select_pool31)? (buffer_select)? rdata_buffer31 : rdata_buffer31_pong : 8'b0; + + +//Need to use simple dual port ram for QUARTUS and true dual port RAM for VTR +`ifdef QUARTUS +//////////////////////////////////////////////// +// PING ACCUMULATORS +//////////////////////////////////////////////// + +qadd adder_accum_ping0 (wdata_accum0, wdata_accum0_in, wdata_accum0_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum0_ping ( + .addr0(waddr_accum0), + .d0(wdata_accum0_ping), + .we0(wdata_en_ping0), + .addr1(raddr_buffer0), + .q1(rdata_buffer0), + .clk(clk) +); + +qadd adder_accum_ping1 (wdata_accum1, wdata_accum1_in, wdata_accum1_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum1_ping ( + .addr0(waddr_accum1), + .d0(wdata_accum1_ping), + .we0(wdata_en_ping1), + .addr1(raddr_buffer1), + .q1(rdata_buffer1), + .clk(clk) +); + +qadd adder_accum_ping2 (wdata_accum2, wdata_accum2_in, wdata_accum2_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum2_ping ( + .addr0(waddr_accum2), + .d0(wdata_accum2_ping), + .we0(wdata_en_ping2), + .addr1(raddr_buffer2), + .q1(rdata_buffer2), + .clk(clk) +); + +qadd adder_accum_ping3 (wdata_accum3, wdata_accum3_in, wdata_accum3_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum3_ping ( + .addr0(waddr_accum3), + .d0(wdata_accum3_ping), + .we0(wdata_en_ping3), + .addr1(raddr_buffer3), + .q1(rdata_buffer3), + .clk(clk) +); + +qadd adder_accum_ping4 (wdata_accum4, wdata_accum4_in, wdata_accum4_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum4_ping ( + .addr0(waddr_accum4), + .d0(wdata_accum4_ping), + .we0(wdata_en_ping4), + .addr1(raddr_buffer4), + .q1(rdata_buffer4), + .clk(clk) +); + +qadd adder_accum_ping5 (wdata_accum5, wdata_accum5_in, wdata_accum5_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum5_ping ( + .addr0(waddr_accum5), + .d0(wdata_accum5_ping), + .we0(wdata_en_ping5), + .addr1(raddr_buffer5), + .q1(rdata_buffer5), + .clk(clk) +); + +qadd adder_accum_ping6 (wdata_accum6, wdata_accum6_in, wdata_accum6_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum6_ping ( + .addr0(waddr_accum6), + .d0(wdata_accum6_ping), + .we0(wdata_en_ping6), + .addr1(raddr_buffer6), + .q1(rdata_buffer6), + .clk(clk) +); + +qadd adder_accum_ping7 (wdata_accum7, wdata_accum7_in, wdata_accum7_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum7_ping ( + .addr0(waddr_accum7), + .d0(wdata_accum7_ping), + .we0(wdata_en_ping7), + .addr1(raddr_buffer7), + .q1(rdata_buffer7), + .clk(clk) +); + +qadd adder_accum_ping8 (wdata_accum8, wdata_accum8_in, wdata_accum8_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum8_ping ( + .addr0(waddr_accum8), + .d0(wdata_accum8_ping), + .we0(wdata_en_ping8), + .addr1(raddr_buffer8), + .q1(rdata_buffer8), + .clk(clk) +); + +qadd adder_accum_ping9 (wdata_accum9, wdata_accum9_in, wdata_accum9_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum9_ping ( + .addr0(waddr_accum9), + .d0(wdata_accum9_ping), + .we0(wdata_en_ping9), + .addr1(raddr_buffer9), + .q1(rdata_buffer9), + .clk(clk) +); + +qadd adder_accum_ping10 (wdata_accum10, wdata_accum10_in, wdata_accum10_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum10_ping ( + .addr0(waddr_accum10), + .d0(wdata_accum10_ping), + .we0(wdata_en_ping10), + .addr1(raddr_buffer10), + .q1(rdata_buffer10), + .clk(clk) +); + +qadd adder_accum_ping11 (wdata_accum11, wdata_accum11_in, wdata_accum11_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum11_ping ( + .addr0(waddr_accum11), + .d0(wdata_accum11_ping), + .we0(wdata_en_ping11), + .addr1(raddr_buffer11), + .q1(rdata_buffer11), + .clk(clk) +); + +qadd adder_accum_ping12 (wdata_accum12, wdata_accum12_in, wdata_accum12_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum12_ping ( + .addr0(waddr_accum12), + .d0(wdata_accum12_ping), + .we0(wdata_en_ping12), + .addr1(raddr_buffer12), + .q1(rdata_buffer12), + .clk(clk) +); + +qadd adder_accum_ping13 (wdata_accum13, wdata_accum13_in, wdata_accum13_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum13_ping ( + .addr0(waddr_accum13), + .d0(wdata_accum13_ping), + .we0(wdata_en_ping13), + .addr1(raddr_buffer13), + .q1(rdata_buffer13), + .clk(clk) +); + +qadd adder_accum_ping14 (wdata_accum14, wdata_accum14_in, wdata_accum14_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum14_ping ( + .addr0(waddr_accum14), + .d0(wdata_accum14_ping), + .we0(wdata_en_ping14), + .addr1(raddr_buffer14), + .q1(rdata_buffer14), + .clk(clk) +); + +qadd adder_accum_ping15 (wdata_accum15, wdata_accum15_in, wdata_accum15_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum15_ping ( + .addr0(waddr_accum15), + .d0(wdata_accum15_ping), + .we0(wdata_en_ping15), + .addr1(raddr_buffer15), + .q1(rdata_buffer15), + .clk(clk) +); + +qadd adder_accum_ping16 (wdata_accum16, wdata_accum16_in, wdata_accum16_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum16_ping ( + .addr0(waddr_accum16), + .d0(wdata_accum16_ping), + .we0(wdata_en_ping16), + .addr1(raddr_buffer16), + .q1(rdata_buffer16), + .clk(clk) +); + +qadd adder_accum_ping17 (wdata_accum17, wdata_accum17_in, wdata_accum17_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum17_ping ( + .addr0(waddr_accum17), + .d0(wdata_accum17_ping), + .we0(wdata_en_ping17), + .addr1(raddr_buffer17), + .q1(rdata_buffer17), + .clk(clk) +); + +qadd adder_accum_ping18 (wdata_accum18, wdata_accum18_in, wdata_accum18_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum18_ping ( + .addr0(waddr_accum18), + .d0(wdata_accum18_ping), + .we0(wdata_en_ping18), + .addr1(raddr_buffer18), + .q1(rdata_buffer18), + .clk(clk) +); + +qadd adder_accum_ping19 (wdata_accum19, wdata_accum19_in, wdata_accum19_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum19_ping ( + .addr0(waddr_accum19), + .d0(wdata_accum19_ping), + .we0(wdata_en_ping19), + .addr1(raddr_buffer19), + .q1(rdata_buffer19), + .clk(clk) +); + +qadd adder_accum_ping20 (wdata_accum20, wdata_accum20_in, wdata_accum20_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum20_ping ( + .addr0(waddr_accum20), + .d0(wdata_accum20_ping), + .we0(wdata_en_ping20), + .addr1(raddr_buffer20), + .q1(rdata_buffer20), + .clk(clk) +); + +qadd adder_accum_ping21 (wdata_accum21, wdata_accum21_in, wdata_accum21_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum21_ping ( + .addr0(waddr_accum21), + .d0(wdata_accum21_ping), + .we0(wdata_en_ping21), + .addr1(raddr_buffer21), + .q1(rdata_buffer21), + .clk(clk) +); + +qadd adder_accum_ping22 (wdata_accum22, wdata_accum22_in, wdata_accum22_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum22_ping ( + .addr0(waddr_accum22), + .d0(wdata_accum22_ping), + .we0(wdata_en_ping22), + .addr1(raddr_buffer22), + .q1(rdata_buffer22), + .clk(clk) +); + +qadd adder_accum_ping23 (wdata_accum23, wdata_accum23_in, wdata_accum23_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum23_ping ( + .addr0(waddr_accum23), + .d0(wdata_accum23_ping), + .we0(wdata_en_ping23), + .addr1(raddr_buffer23), + .q1(rdata_buffer23), + .clk(clk) +); + +qadd adder_accum_ping24 (wdata_accum24, wdata_accum24_in, wdata_accum24_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum24_ping ( + .addr0(waddr_accum24), + .d0(wdata_accum24_ping), + .we0(wdata_en_ping24), + .addr1(raddr_buffer24), + .q1(rdata_buffer24), + .clk(clk) +); + +qadd adder_accum_ping25 (wdata_accum25, wdata_accum25_in, wdata_accum25_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum25_ping ( + .addr0(waddr_accum25), + .d0(wdata_accum25_ping), + .we0(wdata_en_ping25), + .addr1(raddr_buffer25), + .q1(rdata_buffer25), + .clk(clk) +); + +qadd adder_accum_ping26 (wdata_accum26, wdata_accum26_in, wdata_accum26_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum26_ping ( + .addr0(waddr_accum26), + .d0(wdata_accum26_ping), + .we0(wdata_en_ping26), + .addr1(raddr_buffer26), + .q1(rdata_buffer26), + .clk(clk) +); + +qadd adder_accum_ping27 (wdata_accum27, wdata_accum27_in, wdata_accum27_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum27_ping ( + .addr0(waddr_accum27), + .d0(wdata_accum27_ping), + .we0(wdata_en_ping27), + .addr1(raddr_buffer27), + .q1(rdata_buffer27), + .clk(clk) +); + +qadd adder_accum_ping28 (wdata_accum28, wdata_accum28_in, wdata_accum28_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum28_ping ( + .addr0(waddr_accum28), + .d0(wdata_accum28_ping), + .we0(wdata_en_ping28), + .addr1(raddr_buffer28), + .q1(rdata_buffer28), + .clk(clk) +); + +qadd adder_accum_ping29 (wdata_accum29, wdata_accum29_in, wdata_accum29_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum29_ping ( + .addr0(waddr_accum29), + .d0(wdata_accum29_ping), + .we0(wdata_en_ping29), + .addr1(raddr_buffer29), + .q1(rdata_buffer29), + .clk(clk) +); + +qadd adder_accum_ping30 (wdata_accum30, wdata_accum30_in, wdata_accum30_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum30_ping ( + .addr0(waddr_accum30), + .d0(wdata_accum30_ping), + .we0(wdata_en_ping30), + .addr1(raddr_buffer30), + .q1(rdata_buffer30), + .clk(clk) +); + +qadd adder_accum_ping31 (wdata_accum31, wdata_accum31_in, wdata_accum31_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum31_ping ( + .addr0(waddr_accum31), + .d0(wdata_accum31_ping), + .we0(wdata_en_ping31), + .addr1(raddr_buffer31), + .q1(rdata_buffer31), + .clk(clk) +); + +wire [`DWIDTH-1:0] wdata_accum0_pong; +wire [`DWIDTH-1:0] wdata_accum1_pong; +wire [`DWIDTH-1:0] wdata_accum2_pong; +wire [`DWIDTH-1:0] wdata_accum3_pong; +wire [`DWIDTH-1:0] wdata_accum4_pong; +wire [`DWIDTH-1:0] wdata_accum5_pong; +wire [`DWIDTH-1:0] wdata_accum6_pong; +wire [`DWIDTH-1:0] wdata_accum7_pong; +wire [`DWIDTH-1:0] wdata_accum8_pong; +wire [`DWIDTH-1:0] wdata_accum9_pong; +wire [`DWIDTH-1:0] wdata_accum10_pong; +wire [`DWIDTH-1:0] wdata_accum11_pong; +wire [`DWIDTH-1:0] wdata_accum12_pong; +wire [`DWIDTH-1:0] wdata_accum13_pong; +wire [`DWIDTH-1:0] wdata_accum14_pong; +wire [`DWIDTH-1:0] wdata_accum15_pong; +wire [`DWIDTH-1:0] wdata_accum16_pong; +wire [`DWIDTH-1:0] wdata_accum17_pong; +wire [`DWIDTH-1:0] wdata_accum18_pong; +wire [`DWIDTH-1:0] wdata_accum19_pong; +wire [`DWIDTH-1:0] wdata_accum20_pong; +wire [`DWIDTH-1:0] wdata_accum21_pong; +wire [`DWIDTH-1:0] wdata_accum22_pong; +wire [`DWIDTH-1:0] wdata_accum23_pong; +wire [`DWIDTH-1:0] wdata_accum24_pong; +wire [`DWIDTH-1:0] wdata_accum25_pong; +wire [`DWIDTH-1:0] wdata_accum26_pong; +wire [`DWIDTH-1:0] wdata_accum27_pong; +wire [`DWIDTH-1:0] wdata_accum28_pong; +wire [`DWIDTH-1:0] wdata_accum29_pong; +wire [`DWIDTH-1:0] wdata_accum30_pong; +wire [`DWIDTH-1:0] wdata_accum31_pong; + +//////////////////////////////////////////////// +// PONG ACCUMULATORS +//////////////////////////////////////////////// + +qadd adder_accum_pong0 (wdata_accum0, wdata_accum0_in, wdata_accum0_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum0_pong ( + .addr0(waddr_accum0), + .d0(wdata_accum0_pong), + .we0(wdata_en_pong0), + .addr1(raddr_buffer0), + .q1(rdata_buffer0_pong), + .clk(clk) +); + +qadd adder_accum_pong1 (wdata_accum1, wdata_accum1_in, wdata_accum1_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum1_pong ( + .addr0(waddr_accum1), + .d0(wdata_accum1_pong), + .we0(wdata_en_pong1), + .addr1(raddr_buffer1), + .q1(rdata_buffer1_pong), + .clk(clk) +); + +qadd adder_accum_pong2 (wdata_accum2, wdata_accum2_in, wdata_accum2_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum2_pong ( + .addr0(waddr_accum2), + .d0(wdata_accum2_pong), + .we0(wdata_en_pong2), + .addr1(raddr_buffer2), + .q1(rdata_buffer2_pong), + .clk(clk) +); + +qadd adder_accum_pong3 (wdata_accum3, wdata_accum3_in, wdata_accum3_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum3_pong ( + .addr0(waddr_accum3), + .d0(wdata_accum3_pong), + .we0(wdata_en_pong3), + .addr1(raddr_buffer3), + .q1(rdata_buffer3_pong), + .clk(clk) +); + +qadd adder_accum_pong4 (wdata_accum4, wdata_accum4_in, wdata_accum4_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum4_pong ( + .addr0(waddr_accum4), + .d0(wdata_accum4_pong), + .we0(wdata_en_pong4), + .addr1(raddr_buffer4), + .q1(rdata_buffer4_pong), + .clk(clk) +); + +qadd adder_accum_pong5 (wdata_accum5, wdata_accum5_in, wdata_accum5_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum5_pong ( + .addr0(waddr_accum5), + .d0(wdata_accum5_pong), + .we0(wdata_en_pong5), + .addr1(raddr_buffer5), + .q1(rdata_buffer5_pong), + .clk(clk) +); + +qadd adder_accum_pong6 (wdata_accum6, wdata_accum6_in, wdata_accum6_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum6_pong ( + .addr0(waddr_accum6), + .d0(wdata_accum6_pong), + .we0(wdata_en_pong6), + .addr1(raddr_buffer6), + .q1(rdata_buffer6_pong), + .clk(clk) +); + +qadd adder_accum_pong7 (wdata_accum7, wdata_accum7_in, wdata_accum7_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum7_pong ( + .addr0(waddr_accum7), + .d0(wdata_accum7_pong), + .we0(wdata_en_pong7), + .addr1(raddr_buffer7), + .q1(rdata_buffer7_pong), + .clk(clk) +); + +qadd adder_accum_pong8 (wdata_accum8, wdata_accum8_in, wdata_accum8_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum8_pong ( + .addr0(waddr_accum8), + .d0(wdata_accum8_pong), + .we0(wdata_en_pong8), + .addr1(raddr_buffer8), + .q1(rdata_buffer8_pong), + .clk(clk) +); + +qadd adder_accum_pong9 (wdata_accum9, wdata_accum9_in, wdata_accum9_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum9_pong ( + .addr0(waddr_accum9), + .d0(wdata_accum9_pong), + .we0(wdata_en_pong9), + .addr1(raddr_buffer9), + .q1(rdata_buffer9_pong), + .clk(clk) +); + +qadd adder_accum_pong10 (wdata_accum10, wdata_accum10_in, wdata_accum10_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum10_pong ( + .addr0(waddr_accum10), + .d0(wdata_accum10_pong), + .we0(wdata_en_pong10), + .addr1(raddr_buffer10), + .q1(rdata_buffer10_pong), + .clk(clk) +); + +qadd adder_accum_pong11 (wdata_accum11, wdata_accum11_in, wdata_accum11_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum11_pong ( + .addr0(waddr_accum11), + .d0(wdata_accum11_pong), + .we0(wdata_en_pong11), + .addr1(raddr_buffer11), + .q1(rdata_buffer11_pong), + .clk(clk) +); + +qadd adder_accum_pong12 (wdata_accum12, wdata_accum12_in, wdata_accum12_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum12_pong ( + .addr0(waddr_accum12), + .d0(wdata_accum12_pong), + .we0(wdata_en_pong12), + .addr1(raddr_buffer12), + .q1(rdata_buffer12_pong), + .clk(clk) +); + +qadd adder_accum_pong13 (wdata_accum13, wdata_accum13_in, wdata_accum13_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum13_pong ( + .addr0(waddr_accum13), + .d0(wdata_accum13_pong), + .we0(wdata_en_pong13), + .addr1(raddr_buffer13), + .q1(rdata_buffer13_pong), + .clk(clk) +); + +qadd adder_accum_pong14 (wdata_accum14, wdata_accum14_in, wdata_accum14_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum14_pong ( + .addr0(waddr_accum14), + .d0(wdata_accum14_pong), + .we0(wdata_en_pong14), + .addr1(raddr_buffer14), + .q1(rdata_buffer14_pong), + .clk(clk) +); + +qadd adder_accum_pong15 (wdata_accum15, wdata_accum15_in, wdata_accum15_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum15_pong ( + .addr0(waddr_accum15), + .d0(wdata_accum15_pong), + .we0(wdata_en_pong15), + .addr1(raddr_buffer15), + .q1(rdata_buffer15_pong), + .clk(clk) +); + +qadd adder_accum_pong16 (wdata_accum16, wdata_accum16_in, wdata_accum16_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum16_pong ( + .addr0(waddr_accum16), + .d0(wdata_accum16_pong), + .we0(wdata_en_pong16), + .addr1(raddr_buffer16), + .q1(rdata_buffer16_pong), + .clk(clk) +); + +qadd adder_accum_pong17 (wdata_accum17, wdata_accum17_in, wdata_accum17_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum17_pong ( + .addr0(waddr_accum17), + .d0(wdata_accum17_pong), + .we0(wdata_en_pong17), + .addr1(raddr_buffer17), + .q1(rdata_buffer17_pong), + .clk(clk) +); + +qadd adder_accum_pong18 (wdata_accum18, wdata_accum18_in, wdata_accum18_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum18_pong ( + .addr0(waddr_accum18), + .d0(wdata_accum18_pong), + .we0(wdata_en_pong18), + .addr1(raddr_buffer18), + .q1(rdata_buffer18_pong), + .clk(clk) +); + +qadd adder_accum_pong19 (wdata_accum19, wdata_accum19_in, wdata_accum19_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum19_pong ( + .addr0(waddr_accum19), + .d0(wdata_accum19_pong), + .we0(wdata_en_pong19), + .addr1(raddr_buffer19), + .q1(rdata_buffer19_pong), + .clk(clk) +); + +qadd adder_accum_pong20 (wdata_accum20, wdata_accum20_in, wdata_accum20_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum20_pong ( + .addr0(waddr_accum20), + .d0(wdata_accum20_pong), + .we0(wdata_en_pong20), + .addr1(raddr_buffer20), + .q1(rdata_buffer20_pong), + .clk(clk) +); + +qadd adder_accum_pong21 (wdata_accum21, wdata_accum21_in, wdata_accum21_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum21_pong ( + .addr0(waddr_accum21), + .d0(wdata_accum21_pong), + .we0(wdata_en_pong21), + .addr1(raddr_buffer21), + .q1(rdata_buffer21_pong), + .clk(clk) +); + +qadd adder_accum_pong22 (wdata_accum22, wdata_accum22_in, wdata_accum22_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum22_pong ( + .addr0(waddr_accum22), + .d0(wdata_accum22_pong), + .we0(wdata_en_pong22), + .addr1(raddr_buffer22), + .q1(rdata_buffer22_pong), + .clk(clk) +); + +qadd adder_accum_pong23 (wdata_accum23, wdata_accum23_in, wdata_accum23_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum23_pong ( + .addr0(waddr_accum23), + .d0(wdata_accum23_pong), + .we0(wdata_en_pong23), + .addr1(raddr_buffer23), + .q1(rdata_buffer23_pong), + .clk(clk) +); + +qadd adder_accum_pong24 (wdata_accum24, wdata_accum24_in, wdata_accum24_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum24_pong ( + .addr0(waddr_accum24), + .d0(wdata_accum24_pong), + .we0(wdata_en_pong24), + .addr1(raddr_buffer24), + .q1(rdata_buffer24_pong), + .clk(clk) +); + +qadd adder_accum_pong25 (wdata_accum25, wdata_accum25_in, wdata_accum25_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum25_pong ( + .addr0(waddr_accum25), + .d0(wdata_accum25_pong), + .we0(wdata_en_pong25), + .addr1(raddr_buffer25), + .q1(rdata_buffer25_pong), + .clk(clk) +); + +qadd adder_accum_pong26 (wdata_accum26, wdata_accum26_in, wdata_accum26_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum26_pong ( + .addr0(waddr_accum26), + .d0(wdata_accum26_pong), + .we0(wdata_en_pong26), + .addr1(raddr_buffer26), + .q1(rdata_buffer26_pong), + .clk(clk) +); + +qadd adder_accum_pong27 (wdata_accum27, wdata_accum27_in, wdata_accum27_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum27_pong ( + .addr0(waddr_accum27), + .d0(wdata_accum27_pong), + .we0(wdata_en_pong27), + .addr1(raddr_buffer27), + .q1(rdata_buffer27_pong), + .clk(clk) +); + +qadd adder_accum_pong28 (wdata_accum28, wdata_accum28_in, wdata_accum28_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum28_pong ( + .addr0(waddr_accum28), + .d0(wdata_accum28_pong), + .we0(wdata_en_pong28), + .addr1(raddr_buffer28), + .q1(rdata_buffer28_pong), + .clk(clk) +); + +qadd adder_accum_pong29 (wdata_accum29, wdata_accum29_in, wdata_accum29_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum29_pong ( + .addr0(waddr_accum29), + .d0(wdata_accum29_pong), + .we0(wdata_en_pong29), + .addr1(raddr_buffer29), + .q1(rdata_buffer29_pong), + .clk(clk) +); + +qadd adder_accum_pong30 (wdata_accum30, wdata_accum30_in, wdata_accum30_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum30_pong ( + .addr0(waddr_accum30), + .d0(wdata_accum30_pong), + .we0(wdata_en_pong30), + .addr1(raddr_buffer30), + .q1(rdata_buffer30_pong), + .clk(clk) +); + +qadd adder_accum_pong31 (wdata_accum31, wdata_accum31_in, wdata_accum31_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum31_pong ( + .addr0(waddr_accum31), + .d0(wdata_accum31_pong), + .we0(wdata_en_pong31), + .addr1(raddr_buffer31), + .q1(rdata_buffer31_pong), + .clk(clk) +); + + +`else + +//////////////////////////////////////////////// +// PING ACCUMULATORS +//////////////////////////////////////////////// + +qadd adder_accum_ping0 (wdata_accum0, wdata_accum0_in, wdata_accum0_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum0_ping ( + .addr0(waddr_accum0), + .d0(wdata_accum0_ping), + .we0(wdata_en_ping0), + .q0(accum0_ping_q0_NC), + .addr1(raddr_buffer0), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer0), + .clk(clk) +); + +qadd adder_accum_ping1 (wdata_accum1, wdata_accum1_in, wdata_accum1_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum1_ping ( + .addr0(waddr_accum1), + .d0(wdata_accum1_ping), + .we0(wdata_en_ping1), + .q0(accum1_ping_q0_NC), + .addr1(raddr_buffer1), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer1), + .clk(clk) +); + +qadd adder_accum_ping2 (wdata_accum2, wdata_accum2_in, wdata_accum2_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum2_ping ( + .addr0(waddr_accum2), + .d0(wdata_accum2_ping), + .we0(wdata_en_ping2), + .q0(accum2_ping_q0_NC), + .addr1(raddr_buffer2), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer2), + .clk(clk) +); + +qadd adder_accum_ping3 (wdata_accum3, wdata_accum3_in, wdata_accum3_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum3_ping ( + .addr0(waddr_accum3), + .d0(wdata_accum3_ping), + .we0(wdata_en_ping3), + .q0(accum3_ping_q0_NC), + .addr1(raddr_buffer3), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer3), + .clk(clk) +); + +qadd adder_accum_ping4 (wdata_accum4, wdata_accum4_in, wdata_accum4_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum4_ping ( + .addr0(waddr_accum4), + .d0(wdata_accum4_ping), + .we0(wdata_en_ping4), + .q0(accum4_ping_q0_NC), + .addr1(raddr_buffer4), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer4), + .clk(clk) +); + +qadd adder_accum_ping5 (wdata_accum5, wdata_accum5_in, wdata_accum5_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum5_ping ( + .addr0(waddr_accum5), + .d0(wdata_accum5_ping), + .we0(wdata_en_ping5), + .q0(accum5_ping_q0_NC), + .addr1(raddr_buffer5), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer5), + .clk(clk) +); + +qadd adder_accum_ping6 (wdata_accum6, wdata_accum6_in, wdata_accum6_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum6_ping ( + .addr0(waddr_accum6), + .d0(wdata_accum6_ping), + .we0(wdata_en_ping6), + .q0(accum6_ping_q0_NC), + .addr1(raddr_buffer6), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer6), + .clk(clk) +); + +qadd adder_accum_ping7 (wdata_accum7, wdata_accum7_in, wdata_accum7_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum7_ping ( + .addr0(waddr_accum7), + .d0(wdata_accum7_ping), + .we0(wdata_en_ping7), + .q0(accum7_ping_q0_NC), + .addr1(raddr_buffer7), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer7), + .clk(clk) +); + +qadd adder_accum_ping8 (wdata_accum8, wdata_accum8_in, wdata_accum8_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum8_ping ( + .addr0(waddr_accum8), + .d0(wdata_accum8_ping), + .we0(wdata_en_ping8), + .q0(accum8_ping_q0_NC), + .addr1(raddr_buffer8), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer8), + .clk(clk) +); + +qadd adder_accum_ping9 (wdata_accum9, wdata_accum9_in, wdata_accum9_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum9_ping ( + .addr0(waddr_accum9), + .d0(wdata_accum9_ping), + .we0(wdata_en_ping9), + .q0(accum9_ping_q0_NC), + .addr1(raddr_buffer9), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer9), + .clk(clk) +); + +qadd adder_accum_ping10 (wdata_accum10, wdata_accum10_in, wdata_accum10_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum10_ping ( + .addr0(waddr_accum10), + .d0(wdata_accum10_ping), + .we0(wdata_en_ping10), + .q0(accum10_ping_q0_NC), + .addr1(raddr_buffer10), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer10), + .clk(clk) +); + +qadd adder_accum_ping11 (wdata_accum11, wdata_accum11_in, wdata_accum11_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum11_ping ( + .addr0(waddr_accum11), + .d0(wdata_accum11_ping), + .we0(wdata_en_ping11), + .q0(accum11_ping_q0_NC), + .addr1(raddr_buffer11), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer11), + .clk(clk) +); + +qadd adder_accum_ping12 (wdata_accum12, wdata_accum12_in, wdata_accum12_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum12_ping ( + .addr0(waddr_accum12), + .d0(wdata_accum12_ping), + .we0(wdata_en_ping12), + .q0(accum12_ping_q0_NC), + .addr1(raddr_buffer12), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer12), + .clk(clk) +); + +qadd adder_accum_ping13 (wdata_accum13, wdata_accum13_in, wdata_accum13_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum13_ping ( + .addr0(waddr_accum13), + .d0(wdata_accum13_ping), + .we0(wdata_en_ping13), + .q0(accum13_ping_q0_NC), + .addr1(raddr_buffer13), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer13), + .clk(clk) +); + +qadd adder_accum_ping14 (wdata_accum14, wdata_accum14_in, wdata_accum14_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum14_ping ( + .addr0(waddr_accum14), + .d0(wdata_accum14_ping), + .we0(wdata_en_ping14), + .q0(accum14_ping_q0_NC), + .addr1(raddr_buffer14), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer14), + .clk(clk) +); + +qadd adder_accum_ping15 (wdata_accum15, wdata_accum15_in, wdata_accum15_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum15_ping ( + .addr0(waddr_accum15), + .d0(wdata_accum15_ping), + .we0(wdata_en_ping15), + .q0(accum15_ping_q0_NC), + .addr1(raddr_buffer15), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer15), + .clk(clk) +); + +qadd adder_accum_ping16 (wdata_accum16, wdata_accum16_in, wdata_accum16_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum16_ping ( + .addr0(waddr_accum16), + .d0(wdata_accum16_ping), + .we0(wdata_en_ping16), + .q0(accum16_ping_q0_NC), + .addr1(raddr_buffer16), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer16), + .clk(clk) +); + +qadd adder_accum_ping17 (wdata_accum17, wdata_accum17_in, wdata_accum17_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum17_ping ( + .addr0(waddr_accum17), + .d0(wdata_accum17_ping), + .we0(wdata_en_ping17), + .q0(accum17_ping_q0_NC), + .addr1(raddr_buffer17), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer17), + .clk(clk) +); + +qadd adder_accum_ping18 (wdata_accum18, wdata_accum18_in, wdata_accum18_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum18_ping ( + .addr0(waddr_accum18), + .d0(wdata_accum18_ping), + .we0(wdata_en_ping18), + .q0(accum18_ping_q0_NC), + .addr1(raddr_buffer18), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer18), + .clk(clk) +); + +qadd adder_accum_ping19 (wdata_accum19, wdata_accum19_in, wdata_accum19_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum19_ping ( + .addr0(waddr_accum19), + .d0(wdata_accum19_ping), + .we0(wdata_en_ping19), + .q0(accum19_ping_q0_NC), + .addr1(raddr_buffer19), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer19), + .clk(clk) +); + +qadd adder_accum_ping20 (wdata_accum20, wdata_accum20_in, wdata_accum20_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum20_ping ( + .addr0(waddr_accum20), + .d0(wdata_accum20_ping), + .we0(wdata_en_ping20), + .q0(accum20_ping_q0_NC), + .addr1(raddr_buffer20), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer20), + .clk(clk) +); + +qadd adder_accum_ping21 (wdata_accum21, wdata_accum21_in, wdata_accum21_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum21_ping ( + .addr0(waddr_accum21), + .d0(wdata_accum21_ping), + .we0(wdata_en_ping21), + .q0(accum21_ping_q0_NC), + .addr1(raddr_buffer21), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer21), + .clk(clk) +); + +qadd adder_accum_ping22 (wdata_accum22, wdata_accum22_in, wdata_accum22_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum22_ping ( + .addr0(waddr_accum22), + .d0(wdata_accum22_ping), + .we0(wdata_en_ping22), + .q0(accum22_ping_q0_NC), + .addr1(raddr_buffer22), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer22), + .clk(clk) +); + +qadd adder_accum_ping23 (wdata_accum23, wdata_accum23_in, wdata_accum23_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum23_ping ( + .addr0(waddr_accum23), + .d0(wdata_accum23_ping), + .we0(wdata_en_ping23), + .q0(accum23_ping_q0_NC), + .addr1(raddr_buffer23), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer23), + .clk(clk) +); + +qadd adder_accum_ping24 (wdata_accum24, wdata_accum24_in, wdata_accum24_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum24_ping ( + .addr0(waddr_accum24), + .d0(wdata_accum24_ping), + .we0(wdata_en_ping24), + .q0(accum24_ping_q0_NC), + .addr1(raddr_buffer24), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer24), + .clk(clk) +); + +qadd adder_accum_ping25 (wdata_accum25, wdata_accum25_in, wdata_accum25_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum25_ping ( + .addr0(waddr_accum25), + .d0(wdata_accum25_ping), + .we0(wdata_en_ping25), + .q0(accum25_ping_q0_NC), + .addr1(raddr_buffer25), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer25), + .clk(clk) +); + +qadd adder_accum_ping26 (wdata_accum26, wdata_accum26_in, wdata_accum26_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum26_ping ( + .addr0(waddr_accum26), + .d0(wdata_accum26_ping), + .we0(wdata_en_ping26), + .q0(accum26_ping_q0_NC), + .addr1(raddr_buffer26), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer26), + .clk(clk) +); + +qadd adder_accum_ping27 (wdata_accum27, wdata_accum27_in, wdata_accum27_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum27_ping ( + .addr0(waddr_accum27), + .d0(wdata_accum27_ping), + .we0(wdata_en_ping27), + .q0(accum27_ping_q0_NC), + .addr1(raddr_buffer27), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer27), + .clk(clk) +); + +qadd adder_accum_ping28 (wdata_accum28, wdata_accum28_in, wdata_accum28_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum28_ping ( + .addr0(waddr_accum28), + .d0(wdata_accum28_ping), + .we0(wdata_en_ping28), + .q0(accum28_ping_q0_NC), + .addr1(raddr_buffer28), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer28), + .clk(clk) +); + +qadd adder_accum_ping29 (wdata_accum29, wdata_accum29_in, wdata_accum29_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum29_ping ( + .addr0(waddr_accum29), + .d0(wdata_accum29_ping), + .we0(wdata_en_ping29), + .q0(accum29_ping_q0_NC), + .addr1(raddr_buffer29), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer29), + .clk(clk) +); + +qadd adder_accum_ping30 (wdata_accum30, wdata_accum30_in, wdata_accum30_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum30_ping ( + .addr0(waddr_accum30), + .d0(wdata_accum30_ping), + .we0(wdata_en_ping30), + .q0(accum30_ping_q0_NC), + .addr1(raddr_buffer30), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer30), + .clk(clk) +); + +qadd adder_accum_ping31 (wdata_accum31, wdata_accum31_in, wdata_accum31_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum31_ping ( + .addr0(waddr_accum31), + .d0(wdata_accum31_ping), + .we0(wdata_en_ping31), + .q0(accum31_ping_q0_NC), + .addr1(raddr_buffer31), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer31), + .clk(clk) +); + +wire [`DWIDTH-1:0] wdata_accum0_pong; +wire [`DWIDTH-1:0] wdata_accum1_pong; +wire [`DWIDTH-1:0] wdata_accum2_pong; +wire [`DWIDTH-1:0] wdata_accum3_pong; +wire [`DWIDTH-1:0] wdata_accum4_pong; +wire [`DWIDTH-1:0] wdata_accum5_pong; +wire [`DWIDTH-1:0] wdata_accum6_pong; +wire [`DWIDTH-1:0] wdata_accum7_pong; +wire [`DWIDTH-1:0] wdata_accum8_pong; +wire [`DWIDTH-1:0] wdata_accum9_pong; +wire [`DWIDTH-1:0] wdata_accum10_pong; +wire [`DWIDTH-1:0] wdata_accum11_pong; +wire [`DWIDTH-1:0] wdata_accum12_pong; +wire [`DWIDTH-1:0] wdata_accum13_pong; +wire [`DWIDTH-1:0] wdata_accum14_pong; +wire [`DWIDTH-1:0] wdata_accum15_pong; +wire [`DWIDTH-1:0] wdata_accum16_pong; +wire [`DWIDTH-1:0] wdata_accum17_pong; +wire [`DWIDTH-1:0] wdata_accum18_pong; +wire [`DWIDTH-1:0] wdata_accum19_pong; +wire [`DWIDTH-1:0] wdata_accum20_pong; +wire [`DWIDTH-1:0] wdata_accum21_pong; +wire [`DWIDTH-1:0] wdata_accum22_pong; +wire [`DWIDTH-1:0] wdata_accum23_pong; +wire [`DWIDTH-1:0] wdata_accum24_pong; +wire [`DWIDTH-1:0] wdata_accum25_pong; +wire [`DWIDTH-1:0] wdata_accum26_pong; +wire [`DWIDTH-1:0] wdata_accum27_pong; +wire [`DWIDTH-1:0] wdata_accum28_pong; +wire [`DWIDTH-1:0] wdata_accum29_pong; +wire [`DWIDTH-1:0] wdata_accum30_pong; +wire [`DWIDTH-1:0] wdata_accum31_pong; + +//////////////////////////////////////////////// +// PONG ACCUMULATORS +//////////////////////////////////////////////// + +qadd adder_accum_pong0 (wdata_accum0, wdata_accum0_in, wdata_accum0_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum0_pong ( + .addr0(waddr_accum0), + .d0(wdata_accum0_pong), + .we0(wdata_en_pong0), + .q0(accum0_pong_q0_NC), + .addr1(raddr_buffer0), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer0_pong), + .clk(clk) +); + +qadd adder_accum_pong1 (wdata_accum1, wdata_accum1_in, wdata_accum1_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum1_pong ( + .addr0(waddr_accum1), + .d0(wdata_accum1_pong), + .we0(wdata_en_pong1), + .q0(accum1_pong_q0_NC), + .addr1(raddr_buffer1), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer1_pong), + .clk(clk) +); + +qadd adder_accum_pong2 (wdata_accum2, wdata_accum2_in, wdata_accum2_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum2_pong ( + .addr0(waddr_accum2), + .d0(wdata_accum2_pong), + .we0(wdata_en_pong2), + .q0(accum2_pong_q0_NC), + .addr1(raddr_buffer2), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer2_pong), + .clk(clk) +); + +qadd adder_accum_pong3 (wdata_accum3, wdata_accum3_in, wdata_accum3_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum3_pong ( + .addr0(waddr_accum3), + .d0(wdata_accum3_pong), + .we0(wdata_en_pong3), + .q0(accum3_pong_q0_NC), + .addr1(raddr_buffer3), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer3_pong), + .clk(clk) +); + +qadd adder_accum_pong4 (wdata_accum4, wdata_accum4_in, wdata_accum4_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum4_pong ( + .addr0(waddr_accum4), + .d0(wdata_accum4_pong), + .we0(wdata_en_pong4), + .q0(accum4_pong_q0_NC), + .addr1(raddr_buffer4), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer4_pong), + .clk(clk) +); + +qadd adder_accum_pong5 (wdata_accum5, wdata_accum5_in, wdata_accum5_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum5_pong ( + .addr0(waddr_accum5), + .d0(wdata_accum5_pong), + .we0(wdata_en_pong5), + .q0(accum5_pong_q0_NC), + .addr1(raddr_buffer5), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer5_pong), + .clk(clk) +); + +qadd adder_accum_pong6 (wdata_accum6, wdata_accum6_in, wdata_accum6_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum6_pong ( + .addr0(waddr_accum6), + .d0(wdata_accum6_pong), + .we0(wdata_en_pong6), + .q0(accum6_pong_q0_NC), + .addr1(raddr_buffer6), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer6_pong), + .clk(clk) +); + +qadd adder_accum_pong7 (wdata_accum7, wdata_accum7_in, wdata_accum7_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum7_pong ( + .addr0(waddr_accum7), + .d0(wdata_accum7_pong), + .we0(wdata_en_pong7), + .q0(accum7_pong_q0_NC), + .addr1(raddr_buffer7), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer7_pong), + .clk(clk) +); + +qadd adder_accum_pong8 (wdata_accum8, wdata_accum8_in, wdata_accum8_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum8_pong ( + .addr0(waddr_accum8), + .d0(wdata_accum8_pong), + .we0(wdata_en_pong8), + .q0(accum8_pong_q0_NC), + .addr1(raddr_buffer8), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer8_pong), + .clk(clk) +); + +qadd adder_accum_pong9 (wdata_accum9, wdata_accum9_in, wdata_accum9_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum9_pong ( + .addr0(waddr_accum9), + .d0(wdata_accum9_pong), + .we0(wdata_en_pong9), + .q0(accum9_pong_q0_NC), + .addr1(raddr_buffer9), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer9_pong), + .clk(clk) +); + +qadd adder_accum_pong10 (wdata_accum10, wdata_accum10_in, wdata_accum10_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum10_pong ( + .addr0(waddr_accum10), + .d0(wdata_accum10_pong), + .we0(wdata_en_pong10), + .q0(accum10_pong_q0_NC), + .addr1(raddr_buffer10), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer10_pong), + .clk(clk) +); + +qadd adder_accum_pong11 (wdata_accum11, wdata_accum11_in, wdata_accum11_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum11_pong ( + .addr0(waddr_accum11), + .d0(wdata_accum11_pong), + .we0(wdata_en_pong11), + .q0(accum11_pong_q0_NC), + .addr1(raddr_buffer11), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer11_pong), + .clk(clk) +); + +qadd adder_accum_pong12 (wdata_accum12, wdata_accum12_in, wdata_accum12_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum12_pong ( + .addr0(waddr_accum12), + .d0(wdata_accum12_pong), + .we0(wdata_en_pong12), + .q0(accum12_pong_q0_NC), + .addr1(raddr_buffer12), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer12_pong), + .clk(clk) +); + +qadd adder_accum_pong13 (wdata_accum13, wdata_accum13_in, wdata_accum13_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum13_pong ( + .addr0(waddr_accum13), + .d0(wdata_accum13_pong), + .we0(wdata_en_pong13), + .q0(accum13_pong_q0_NC), + .addr1(raddr_buffer13), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer13_pong), + .clk(clk) +); + +qadd adder_accum_pong14 (wdata_accum14, wdata_accum14_in, wdata_accum14_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum14_pong ( + .addr0(waddr_accum14), + .d0(wdata_accum14_pong), + .we0(wdata_en_pong14), + .q0(accum14_pong_q0_NC), + .addr1(raddr_buffer14), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer14_pong), + .clk(clk) +); + +qadd adder_accum_pong15 (wdata_accum15, wdata_accum15_in, wdata_accum15_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum15_pong ( + .addr0(waddr_accum15), + .d0(wdata_accum15_pong), + .we0(wdata_en_pong15), + .q0(accum15_pong_q0_NC), + .addr1(raddr_buffer15), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer15_pong), + .clk(clk) +); + +qadd adder_accum_pong16 (wdata_accum16, wdata_accum16_in, wdata_accum16_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum16_pong ( + .addr0(waddr_accum16), + .d0(wdata_accum16_pong), + .we0(wdata_en_pong16), + .q0(accum16_pong_q0_NC), + .addr1(raddr_buffer16), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer16_pong), + .clk(clk) +); + +qadd adder_accum_pong17 (wdata_accum17, wdata_accum17_in, wdata_accum17_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum17_pong ( + .addr0(waddr_accum17), + .d0(wdata_accum17_pong), + .we0(wdata_en_pong17), + .q0(accum17_pong_q0_NC), + .addr1(raddr_buffer17), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer17_pong), + .clk(clk) +); + +qadd adder_accum_pong18 (wdata_accum18, wdata_accum18_in, wdata_accum18_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum18_pong ( + .addr0(waddr_accum18), + .d0(wdata_accum18_pong), + .we0(wdata_en_pong18), + .q0(accum18_pong_q0_NC), + .addr1(raddr_buffer18), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer18_pong), + .clk(clk) +); + +qadd adder_accum_pong19 (wdata_accum19, wdata_accum19_in, wdata_accum19_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum19_pong ( + .addr0(waddr_accum19), + .d0(wdata_accum19_pong), + .we0(wdata_en_pong19), + .q0(accum19_pong_q0_NC), + .addr1(raddr_buffer19), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer19_pong), + .clk(clk) +); + +qadd adder_accum_pong20 (wdata_accum20, wdata_accum20_in, wdata_accum20_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum20_pong ( + .addr0(waddr_accum20), + .d0(wdata_accum20_pong), + .we0(wdata_en_pong20), + .q0(accum20_pong_q0_NC), + .addr1(raddr_buffer20), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer20_pong), + .clk(clk) +); + +qadd adder_accum_pong21 (wdata_accum21, wdata_accum21_in, wdata_accum21_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum21_pong ( + .addr0(waddr_accum21), + .d0(wdata_accum21_pong), + .we0(wdata_en_pong21), + .q0(accum21_pong_q0_NC), + .addr1(raddr_buffer21), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer21_pong), + .clk(clk) +); + +qadd adder_accum_pong22 (wdata_accum22, wdata_accum22_in, wdata_accum22_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum22_pong ( + .addr0(waddr_accum22), + .d0(wdata_accum22_pong), + .we0(wdata_en_pong22), + .q0(accum22_pong_q0_NC), + .addr1(raddr_buffer22), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer22_pong), + .clk(clk) +); + +qadd adder_accum_pong23 (wdata_accum23, wdata_accum23_in, wdata_accum23_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum23_pong ( + .addr0(waddr_accum23), + .d0(wdata_accum23_pong), + .we0(wdata_en_pong23), + .q0(accum23_pong_q0_NC), + .addr1(raddr_buffer23), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer23_pong), + .clk(clk) +); + +qadd adder_accum_pong24 (wdata_accum24, wdata_accum24_in, wdata_accum24_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum24_pong ( + .addr0(waddr_accum24), + .d0(wdata_accum24_pong), + .we0(wdata_en_pong24), + .q0(accum24_pong_q0_NC), + .addr1(raddr_buffer24), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer24_pong), + .clk(clk) +); + +qadd adder_accum_pong25 (wdata_accum25, wdata_accum25_in, wdata_accum25_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum25_pong ( + .addr0(waddr_accum25), + .d0(wdata_accum25_pong), + .we0(wdata_en_pong25), + .q0(accum25_pong_q0_NC), + .addr1(raddr_buffer25), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer25_pong), + .clk(clk) +); + +qadd adder_accum_pong26 (wdata_accum26, wdata_accum26_in, wdata_accum26_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum26_pong ( + .addr0(waddr_accum26), + .d0(wdata_accum26_pong), + .we0(wdata_en_pong26), + .q0(accum26_pong_q0_NC), + .addr1(raddr_buffer26), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer26_pong), + .clk(clk) +); + +qadd adder_accum_pong27 (wdata_accum27, wdata_accum27_in, wdata_accum27_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum27_pong ( + .addr0(waddr_accum27), + .d0(wdata_accum27_pong), + .we0(wdata_en_pong27), + .q0(accum27_pong_q0_NC), + .addr1(raddr_buffer27), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer27_pong), + .clk(clk) +); + +qadd adder_accum_pong28 (wdata_accum28, wdata_accum28_in, wdata_accum28_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum28_pong ( + .addr0(waddr_accum28), + .d0(wdata_accum28_pong), + .we0(wdata_en_pong28), + .q0(accum28_pong_q0_NC), + .addr1(raddr_buffer28), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer28_pong), + .clk(clk) +); + +qadd adder_accum_pong29 (wdata_accum29, wdata_accum29_in, wdata_accum29_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum29_pong ( + .addr0(waddr_accum29), + .d0(wdata_accum29_pong), + .we0(wdata_en_pong29), + .q0(accum29_pong_q0_NC), + .addr1(raddr_buffer29), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer29_pong), + .clk(clk) +); + +qadd adder_accum_pong30 (wdata_accum30, wdata_accum30_in, wdata_accum30_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum30_pong ( + .addr0(waddr_accum30), + .d0(wdata_accum30_pong), + .we0(wdata_en_pong30), + .q0(accum30_pong_q0_NC), + .addr1(raddr_buffer30), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer30_pong), + .clk(clk) +); + +qadd adder_accum_pong31 (wdata_accum31, wdata_accum31_in, wdata_accum31_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum31_pong ( + .addr0(waddr_accum31), + .d0(wdata_accum31_pong), + .we0(wdata_en_pong31), + .q0(accum31_pong_q0_NC), + .addr1(raddr_buffer31), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer31_pong), + .clk(clk) +); + +`endif +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM generate_pool.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + +module pooling( + clk, + resetn, + start_pooling, + pool_select, + pool_norm_valid, + enable_pool, + rdata_accum0_pool, + rdata_accum1_pool, + rdata_accum2_pool, + rdata_accum3_pool, + rdata_accum4_pool, + rdata_accum5_pool, + rdata_accum6_pool, + rdata_accum7_pool, + rdata_accum8_pool, + rdata_accum9_pool, + rdata_accum10_pool, + rdata_accum11_pool, + rdata_accum12_pool, + rdata_accum13_pool, + rdata_accum14_pool, + rdata_accum15_pool, + rdata_accum16_pool, + rdata_accum17_pool, + rdata_accum18_pool, + rdata_accum19_pool, + rdata_accum20_pool, + rdata_accum21_pool, + rdata_accum22_pool, + rdata_accum23_pool, + rdata_accum24_pool, + rdata_accum25_pool, + rdata_accum26_pool, + rdata_accum27_pool, + rdata_accum28_pool, + rdata_accum29_pool, + rdata_accum30_pool, + rdata_accum31_pool, + raddr_accum0_pool, + raddr_accum1_pool, + raddr_accum2_pool, + raddr_accum3_pool, + raddr_accum4_pool, + raddr_accum5_pool, + raddr_accum6_pool, + raddr_accum7_pool, + raddr_accum8_pool, + raddr_accum9_pool, + raddr_accum10_pool, + raddr_accum11_pool, + raddr_accum12_pool, + raddr_accum13_pool, + raddr_accum14_pool, + raddr_accum15_pool, + raddr_accum16_pool, + raddr_accum17_pool, + raddr_accum18_pool, + raddr_accum19_pool, + raddr_accum20_pool, + raddr_accum21_pool, + raddr_accum22_pool, + raddr_accum23_pool, + raddr_accum24_pool, + raddr_accum25_pool, + raddr_accum26_pool, + raddr_accum27_pool, + raddr_accum28_pool, + raddr_accum29_pool, + raddr_accum30_pool, + raddr_accum31_pool, + pool0, + pool1, + pool2, + pool3, + pool4, + pool5, + pool6, + pool7, + pool8, + pool9, + pool10, + pool11, + pool12, + pool13, + pool14, + pool15, + pool16, + pool17, + pool18, + pool19, + pool20, + pool21, + pool22, + pool23, + pool24, + pool25, + pool26, + pool27, + pool28, + pool29, + pool30, + pool31, + matrix_size, + filter_size +); + +input clk; +input resetn; +input start_pooling; +input pool_select; +input enable_pool; +output pool_norm_valid; +output reg [`DWIDTH-1:0] pool0; +output reg [`DWIDTH-1:0] pool1; +output reg [`DWIDTH-1:0] pool2; +output reg [`DWIDTH-1:0] pool3; +output reg [`DWIDTH-1:0] pool4; +output reg [`DWIDTH-1:0] pool5; +output reg [`DWIDTH-1:0] pool6; +output reg [`DWIDTH-1:0] pool7; +output reg [`DWIDTH-1:0] pool8; +output reg [`DWIDTH-1:0] pool9; +output reg [`DWIDTH-1:0] pool10; +output reg [`DWIDTH-1:0] pool11; +output reg [`DWIDTH-1:0] pool12; +output reg [`DWIDTH-1:0] pool13; +output reg [`DWIDTH-1:0] pool14; +output reg [`DWIDTH-1:0] pool15; +output reg [`DWIDTH-1:0] pool16; +output reg [`DWIDTH-1:0] pool17; +output reg [`DWIDTH-1:0] pool18; +output reg [`DWIDTH-1:0] pool19; +output reg [`DWIDTH-1:0] pool20; +output reg [`DWIDTH-1:0] pool21; +output reg [`DWIDTH-1:0] pool22; +output reg [`DWIDTH-1:0] pool23; +output reg [`DWIDTH-1:0] pool24; +output reg [`DWIDTH-1:0] pool25; +output reg [`DWIDTH-1:0] pool26; +output reg [`DWIDTH-1:0] pool27; +output reg [`DWIDTH-1:0] pool28; +output reg [`DWIDTH-1:0] pool29; +output reg [`DWIDTH-1:0] pool30; +output reg [`DWIDTH-1:0] pool31; +input [`DWIDTH-1:0] rdata_accum0_pool; +input [`DWIDTH-1:0] rdata_accum1_pool; +input [`DWIDTH-1:0] rdata_accum2_pool; +input [`DWIDTH-1:0] rdata_accum3_pool; +input [`DWIDTH-1:0] rdata_accum4_pool; +input [`DWIDTH-1:0] rdata_accum5_pool; +input [`DWIDTH-1:0] rdata_accum6_pool; +input [`DWIDTH-1:0] rdata_accum7_pool; +input [`DWIDTH-1:0] rdata_accum8_pool; +input [`DWIDTH-1:0] rdata_accum9_pool; +input [`DWIDTH-1:0] rdata_accum10_pool; +input [`DWIDTH-1:0] rdata_accum11_pool; +input [`DWIDTH-1:0] rdata_accum12_pool; +input [`DWIDTH-1:0] rdata_accum13_pool; +input [`DWIDTH-1:0] rdata_accum14_pool; +input [`DWIDTH-1:0] rdata_accum15_pool; +input [`DWIDTH-1:0] rdata_accum16_pool; +input [`DWIDTH-1:0] rdata_accum17_pool; +input [`DWIDTH-1:0] rdata_accum18_pool; +input [`DWIDTH-1:0] rdata_accum19_pool; +input [`DWIDTH-1:0] rdata_accum20_pool; +input [`DWIDTH-1:0] rdata_accum21_pool; +input [`DWIDTH-1:0] rdata_accum22_pool; +input [`DWIDTH-1:0] rdata_accum23_pool; +input [`DWIDTH-1:0] rdata_accum24_pool; +input [`DWIDTH-1:0] rdata_accum25_pool; +input [`DWIDTH-1:0] rdata_accum26_pool; +input [`DWIDTH-1:0] rdata_accum27_pool; +input [`DWIDTH-1:0] rdata_accum28_pool; +input [`DWIDTH-1:0] rdata_accum29_pool; +input [`DWIDTH-1:0] rdata_accum30_pool; +input [`DWIDTH-1:0] rdata_accum31_pool; +output [`AWIDTH-1:0] raddr_accum0_pool; +output [`AWIDTH-1:0] raddr_accum1_pool; +output [`AWIDTH-1:0] raddr_accum2_pool; +output [`AWIDTH-1:0] raddr_accum3_pool; +output [`AWIDTH-1:0] raddr_accum4_pool; +output [`AWIDTH-1:0] raddr_accum5_pool; +output [`AWIDTH-1:0] raddr_accum6_pool; +output [`AWIDTH-1:0] raddr_accum7_pool; +output [`AWIDTH-1:0] raddr_accum8_pool; +output [`AWIDTH-1:0] raddr_accum9_pool; +output [`AWIDTH-1:0] raddr_accum10_pool; +output [`AWIDTH-1:0] raddr_accum11_pool; +output [`AWIDTH-1:0] raddr_accum12_pool; +output [`AWIDTH-1:0] raddr_accum13_pool; +output [`AWIDTH-1:0] raddr_accum14_pool; +output [`AWIDTH-1:0] raddr_accum15_pool; +output [`AWIDTH-1:0] raddr_accum16_pool; +output [`AWIDTH-1:0] raddr_accum17_pool; +output [`AWIDTH-1:0] raddr_accum18_pool; +output [`AWIDTH-1:0] raddr_accum19_pool; +output [`AWIDTH-1:0] raddr_accum20_pool; +output [`AWIDTH-1:0] raddr_accum21_pool; +output [`AWIDTH-1:0] raddr_accum22_pool; +output [`AWIDTH-1:0] raddr_accum23_pool; +output [`AWIDTH-1:0] raddr_accum24_pool; +output [`AWIDTH-1:0] raddr_accum25_pool; +output [`AWIDTH-1:0] raddr_accum26_pool; +output [`AWIDTH-1:0] raddr_accum27_pool; +output [`AWIDTH-1:0] raddr_accum28_pool; +output [`AWIDTH-1:0] raddr_accum29_pool; +output [`AWIDTH-1:0] raddr_accum30_pool; +output [`AWIDTH-1:0] raddr_accum31_pool; +input [`DWIDTH-1:0] matrix_size; +input [`DWIDTH-1:0] filter_size; + +reg [`AWIDTH-1:0] raddr_accum1_pool; +reg [`AWIDTH-1:0] raddr_accum2_pool; +reg [`AWIDTH-1:0] raddr_accum3_pool; +reg [`AWIDTH-1:0] raddr_accum4_pool; +reg [`AWIDTH-1:0] raddr_accum5_pool; +reg [`AWIDTH-1:0] raddr_accum6_pool; +reg [`AWIDTH-1:0] raddr_accum7_pool; +reg [`AWIDTH-1:0] raddr_accum8_pool; +reg [`AWIDTH-1:0] raddr_accum9_pool; +reg [`AWIDTH-1:0] raddr_accum10_pool; +reg [`AWIDTH-1:0] raddr_accum11_pool; +reg [`AWIDTH-1:0] raddr_accum12_pool; +reg [`AWIDTH-1:0] raddr_accum13_pool; +reg [`AWIDTH-1:0] raddr_accum14_pool; +reg [`AWIDTH-1:0] raddr_accum15_pool; +reg [`AWIDTH-1:0] raddr_accum16_pool; +reg [`AWIDTH-1:0] raddr_accum17_pool; +reg [`AWIDTH-1:0] raddr_accum18_pool; +reg [`AWIDTH-1:0] raddr_accum19_pool; +reg [`AWIDTH-1:0] raddr_accum20_pool; +reg [`AWIDTH-1:0] raddr_accum21_pool; +reg [`AWIDTH-1:0] raddr_accum22_pool; +reg [`AWIDTH-1:0] raddr_accum23_pool; +reg [`AWIDTH-1:0] raddr_accum24_pool; +reg [`AWIDTH-1:0] raddr_accum25_pool; +reg [`AWIDTH-1:0] raddr_accum26_pool; +reg [`AWIDTH-1:0] raddr_accum27_pool; +reg [`AWIDTH-1:0] raddr_accum28_pool; +reg [`AWIDTH-1:0] raddr_accum29_pool; +reg [`AWIDTH-1:0] raddr_accum30_pool; +reg [`AWIDTH-1:0] raddr_accum31_pool; + +reg [7:0] pool_count0; +reg [7:0] pool_count1; +reg [7:0] pool_count2; +reg [7:0] pool_count3; +reg [7:0] pool_count4; +reg [7:0] pool_count5; +reg [7:0] pool_count6; +reg [7:0] pool_count7; +reg [7:0] pool_count8; +reg [7:0] pool_count9; +reg [7:0] pool_count10; +reg [7:0] pool_count11; +reg [7:0] pool_count12; +reg [7:0] pool_count13; +reg [7:0] pool_count14; +reg [7:0] pool_count15; +reg [7:0] pool_count16; +reg [7:0] pool_count17; +reg [7:0] pool_count18; +reg [7:0] pool_count19; +reg [7:0] pool_count20; +reg [7:0] pool_count21; +reg [7:0] pool_count22; +reg [7:0] pool_count23; +reg [7:0] pool_count24; +reg [7:0] pool_count25; +reg [7:0] pool_count26; +reg [7:0] pool_count27; +reg [7:0] pool_count28; +reg [7:0] pool_count29; +reg [7:0] pool_count30; +reg [7:0] pool_count31; +reg [7:0] pool_count32; + +wire [`DWIDTH-1:0] filter_size_int; +assign filter_size_int = (enable_pool)? filter_size : 8'b1; +wire [`DWIDTH-1:0] matrix_size_int; +assign matrix_size_int = (enable_pool)? matrix_size : 8'b1; + +always @ (posedge clk) begin + if (~resetn|~start_pooling) begin + pool_count0 <= 0; + end + else if (pool_count0 == (filter_size_int*filter_size_int)) begin + pool_count0 <= 1; + end + else if (start_pooling) begin + pool_count0 <= pool_count0 + 1; + end +end + +always @ (posedge clk) begin + pool_count1 <= pool_count0; + pool_count2 <= pool_count1; + pool_count3 <= pool_count2; + pool_count4 <= pool_count3; + pool_count5 <= pool_count4; + pool_count6 <= pool_count5; + pool_count7 <= pool_count6; + pool_count8 <= pool_count7; + pool_count9 <= pool_count8; + pool_count10 <= pool_count9; + pool_count11 <= pool_count10; + pool_count12 <= pool_count11; + pool_count13 <= pool_count12; + pool_count14 <= pool_count13; + pool_count15 <= pool_count14; + pool_count16 <= pool_count15; + pool_count17 <= pool_count16; + pool_count18 <= pool_count17; + pool_count19 <= pool_count18; + pool_count20 <= pool_count19; + pool_count21 <= pool_count20; + pool_count22 <= pool_count21; + pool_count23 <= pool_count22; + pool_count24 <= pool_count23; + pool_count25 <= pool_count24; + pool_count26 <= pool_count25; + pool_count27 <= pool_count26; + pool_count28 <= pool_count27; + pool_count29 <= pool_count28; + pool_count30 <= pool_count29; + pool_count31 <= pool_count30; + pool_count32 <= pool_count31; +end + +wire [`DWIDTH-1:0] cmp0; +wire [`DWIDTH-1:0] cmp1; +wire [`DWIDTH-1:0] cmp2; +wire [`DWIDTH-1:0] cmp3; +wire [`DWIDTH-1:0] cmp4; +wire [`DWIDTH-1:0] cmp5; +wire [`DWIDTH-1:0] cmp6; +wire [`DWIDTH-1:0] cmp7; +wire [`DWIDTH-1:0] cmp8; +wire [`DWIDTH-1:0] cmp9; +wire [`DWIDTH-1:0] cmp10; +wire [`DWIDTH-1:0] cmp11; +wire [`DWIDTH-1:0] cmp12; +wire [`DWIDTH-1:0] cmp13; +wire [`DWIDTH-1:0] cmp14; +wire [`DWIDTH-1:0] cmp15; +wire [`DWIDTH-1:0] cmp16; +wire [`DWIDTH-1:0] cmp17; +wire [`DWIDTH-1:0] cmp18; +wire [`DWIDTH-1:0] cmp19; +wire [`DWIDTH-1:0] cmp20; +wire [`DWIDTH-1:0] cmp21; +wire [`DWIDTH-1:0] cmp22; +wire [`DWIDTH-1:0] cmp23; +wire [`DWIDTH-1:0] cmp24; +wire [`DWIDTH-1:0] cmp25; +wire [`DWIDTH-1:0] cmp26; +wire [`DWIDTH-1:0] cmp27; +wire [`DWIDTH-1:0] cmp28; +wire [`DWIDTH-1:0] cmp29; +wire [`DWIDTH-1:0] cmp30; +wire [`DWIDTH-1:0] cmp31; + +reg [`DWIDTH-1:0] compare0; +reg [`DWIDTH-1:0] compare1; +reg [`DWIDTH-1:0] compare2; +reg [`DWIDTH-1:0] compare3; +reg [`DWIDTH-1:0] compare4; +reg [`DWIDTH-1:0] compare5; +reg [`DWIDTH-1:0] compare6; +reg [`DWIDTH-1:0] compare7; +reg [`DWIDTH-1:0] compare8; +reg [`DWIDTH-1:0] compare9; +reg [`DWIDTH-1:0] compare10; +reg [`DWIDTH-1:0] compare11; +reg [`DWIDTH-1:0] compare12; +reg [`DWIDTH-1:0] compare13; +reg [`DWIDTH-1:0] compare14; +reg [`DWIDTH-1:0] compare15; +reg [`DWIDTH-1:0] compare16; +reg [`DWIDTH-1:0] compare17; +reg [`DWIDTH-1:0] compare18; +reg [`DWIDTH-1:0] compare19; +reg [`DWIDTH-1:0] compare20; +reg [`DWIDTH-1:0] compare21; +reg [`DWIDTH-1:0] compare22; +reg [`DWIDTH-1:0] compare23; +reg [`DWIDTH-1:0] compare24; +reg [`DWIDTH-1:0] compare25; +reg [`DWIDTH-1:0] compare26; +reg [`DWIDTH-1:0] compare27; +reg [`DWIDTH-1:0] compare28; +reg [`DWIDTH-1:0] compare29; +reg [`DWIDTH-1:0] compare30; +reg [`DWIDTH-1:0] compare31; + +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg0; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg1; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg2; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg3; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg4; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg5; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg6; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg7; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg8; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg9; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg10; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg11; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg12; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg13; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg14; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg15; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg16; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg17; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg18; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg19; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg20; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg21; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg22; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg23; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg24; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg25; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg26; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg27; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg28; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg29; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg30; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg31; + +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg0_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg1_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg2_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg3_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg4_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg5_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg6_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg7_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg8_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg9_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg10_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg11_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg12_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg13_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg14_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg15_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg16_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg17_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg18_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg19_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg20_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg21_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg22_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg23_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg24_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg25_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg26_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg27_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg28_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg29_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg30_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg31_int; + +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average0; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average1; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average2; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average3; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average4; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average5; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average6; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average7; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average8; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average9; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average10; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average11; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average12; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average13; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average14; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average15; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average16; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average17; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average18; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average19; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average20; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average21; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average22; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average23; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average24; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average25; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average26; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average27; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average28; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average29; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average30; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average31; + +assign pool_norm_valid = (pool_count1 == (filter_size_int*filter_size_int))?1'b1:1'b0; + +reg [`AWIDTH-1:0] x; +reg [`AWIDTH-1:0] y; +reg [`AWIDTH-1:0] k; +assign raddr_accum0_pool = (~resetn|~start_pooling)? 11'h7ff: ((matrix_size_int)*y + x + k); + +always @(posedge clk) begin + if(~resetn|~start_pooling) begin + x<=0; + y<=0; + k<=0; + end + else if (y == (matrix_size_int-1) & x==(filter_size_int-1)) begin + k<=k+filter_size_int; + y<=0; + x<=0; + end + else if (x==(filter_size_int-1)) begin + y<=y+1; + x<=0; + end + else if (start_pooling) begin + x<=x+1; + end +end + +always @ (posedge clk) begin + raddr_accum1_pool <= raddr_accum0_pool; + raddr_accum2_pool <= raddr_accum1_pool; + raddr_accum3_pool <= raddr_accum2_pool; + raddr_accum4_pool <= raddr_accum3_pool; + raddr_accum5_pool <= raddr_accum4_pool; + raddr_accum6_pool <= raddr_accum5_pool; + raddr_accum7_pool <= raddr_accum6_pool; + raddr_accum8_pool <= raddr_accum7_pool; + raddr_accum9_pool <= raddr_accum8_pool; + raddr_accum10_pool <= raddr_accum9_pool; + raddr_accum11_pool <= raddr_accum10_pool; + raddr_accum12_pool <= raddr_accum11_pool; + raddr_accum13_pool <= raddr_accum12_pool; + raddr_accum14_pool <= raddr_accum13_pool; + raddr_accum15_pool <= raddr_accum14_pool; + raddr_accum16_pool <= raddr_accum15_pool; + raddr_accum17_pool <= raddr_accum16_pool; + raddr_accum18_pool <= raddr_accum17_pool; + raddr_accum19_pool <= raddr_accum18_pool; + raddr_accum20_pool <= raddr_accum19_pool; + raddr_accum21_pool <= raddr_accum20_pool; + raddr_accum22_pool <= raddr_accum21_pool; + raddr_accum23_pool <= raddr_accum22_pool; + raddr_accum24_pool <= raddr_accum23_pool; + raddr_accum25_pool <= raddr_accum24_pool; + raddr_accum26_pool <= raddr_accum25_pool; + raddr_accum27_pool <= raddr_accum26_pool; + raddr_accum28_pool <= raddr_accum27_pool; + raddr_accum29_pool <= raddr_accum28_pool; + raddr_accum30_pool <= raddr_accum29_pool; + raddr_accum31_pool <= raddr_accum30_pool; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare0 <= 0; + end + else if (rdata_accum0_pool > cmp0) begin + compare0 <= rdata_accum0_pool; + end + else if (rdata_accum0_pool < cmp0) begin + compare0 <= cmp0; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg0_int <= 0; + end + else begin + avg0_int <= avg0 + rdata_accum0_pool; + end +end + +assign cmp0 = (pool_count0 == 1)? 0 : compare0; +assign avg0 = (pool_count0 == 1)? 0 : avg0_int; +assign average0 = (filter_size_int == 8'b1)? avg0_int : (filter_size_int == 8'b10)? avg0_int >> 2 : (filter_size_int == 8'b11)? avg0_int >> 3 : (filter_size_int == 8'b100)? avg0_int >> 4 : avg0_int; + +wire [`DWIDTH-1:0] pool0_wire; +assign pool0_wire = (pool_count1 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare0 : average0) : 8'b0; +always @(posedge clk) begin + pool0 <= pool0_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare1 <= 0; + end + else if (rdata_accum1_pool > cmp1) begin + compare1 <= rdata_accum1_pool; + end + else if (rdata_accum1_pool < cmp1) begin + compare1 <= cmp1; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg1_int <= 0; + end + else begin + avg1_int <= avg1 + rdata_accum1_pool; + end +end + +assign cmp1 = (pool_count1 == 1)? 0 : compare1; +assign avg1 = (pool_count1 == 1)? 0 : avg1_int; +assign average1 = (filter_size_int == 8'b1)? avg1_int : (filter_size_int == 8'b10)? avg1_int >> 2 : (filter_size_int == 8'b11)? avg1_int >> 3 : (filter_size_int == 8'b100)? avg1_int >> 4 : avg1_int; + +wire [`DWIDTH-1:0] pool1_wire; +assign pool1_wire = (pool_count2 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare1 : average1) : 8'b0; +always @(posedge clk) begin + pool1 <= pool1_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare2 <= 0; + end + else if (rdata_accum2_pool > cmp2) begin + compare2 <= rdata_accum2_pool; + end + else if (rdata_accum2_pool < cmp2) begin + compare2 <= cmp2; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg2_int <= 0; + end + else begin + avg2_int <= avg2 + rdata_accum2_pool; + end +end + +assign cmp2 = (pool_count2 == 1)? 0 : compare2; +assign avg2 = (pool_count2 == 1)? 0 : avg2_int; +assign average2 = (filter_size_int == 8'b1)? avg2_int : (filter_size_int == 8'b10)? avg2_int >> 2 : (filter_size_int == 8'b11)? avg2_int >> 3 : (filter_size_int == 8'b100)? avg2_int >> 4 : avg2_int; + +wire [`DWIDTH-1:0] pool2_wire; +assign pool2_wire = (pool_count3 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare2 : average2) : 8'b0; +always @(posedge clk) begin + pool2 <= pool2_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare3 <= 0; + end + else if (rdata_accum3_pool > cmp3) begin + compare3 <= rdata_accum3_pool; + end + else if (rdata_accum3_pool < cmp3) begin + compare3 <= cmp3; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg3_int <= 0; + end + else begin + avg3_int <= avg3 + rdata_accum3_pool; + end +end + +assign cmp3 = (pool_count3 == 1)? 0 : compare3; +assign avg3 = (pool_count3 == 1)? 0 : avg3_int; +assign average3 = (filter_size_int == 8'b1)? avg3_int : (filter_size_int == 8'b10)? avg3_int >> 2 : (filter_size_int == 8'b11)? avg3_int >> 3 : (filter_size_int == 8'b100)? avg3_int >> 4 : avg3_int; + +wire [`DWIDTH-1:0] pool3_wire; +assign pool3_wire = (pool_count4 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare3 : average3) : 8'b0; +always @(posedge clk) begin + pool3 <= pool3_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare4 <= 0; + end + else if (rdata_accum4_pool > cmp4) begin + compare4 <= rdata_accum4_pool; + end + else if (rdata_accum4_pool < cmp4) begin + compare4 <= cmp4; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg4_int <= 0; + end + else begin + avg4_int <= avg4 + rdata_accum4_pool; + end +end + +assign cmp4 = (pool_count4 == 1)? 0 : compare4; +assign avg4 = (pool_count4 == 1)? 0 : avg4_int; +assign average4 = (filter_size_int == 8'b1)? avg4_int : (filter_size_int == 8'b10)? avg4_int >> 2 : (filter_size_int == 8'b11)? avg4_int >> 3 : (filter_size_int == 8'b100)? avg4_int >> 4 : avg4_int; + +wire [`DWIDTH-1:0] pool4_wire; +assign pool4_wire = (pool_count5 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare4 : average4) : 8'b0; +always @(posedge clk) begin + pool4 <= pool4_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare5 <= 0; + end + else if (rdata_accum5_pool > cmp5) begin + compare5 <= rdata_accum5_pool; + end + else if (rdata_accum5_pool < cmp5) begin + compare5 <= cmp5; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg5_int <= 0; + end + else begin + avg5_int <= avg5 + rdata_accum5_pool; + end +end + +assign cmp5 = (pool_count5 == 1)? 0 : compare5; +assign avg5 = (pool_count5 == 1)? 0 : avg5_int; +assign average5 = (filter_size_int == 8'b1)? avg5_int : (filter_size_int == 8'b10)? avg5_int >> 2 : (filter_size_int == 8'b11)? avg5_int >> 3 : (filter_size_int == 8'b100)? avg5_int >> 4 : avg5_int; + +wire [`DWIDTH-1:0] pool5_wire; +assign pool5_wire = (pool_count6 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare5 : average5) : 8'b0; +always @(posedge clk) begin + pool5 <= pool5_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare6 <= 0; + end + else if (rdata_accum6_pool > cmp6) begin + compare6 <= rdata_accum6_pool; + end + else if (rdata_accum6_pool < cmp6) begin + compare6 <= cmp6; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg6_int <= 0; + end + else begin + avg6_int <= avg6 + rdata_accum6_pool; + end +end + +assign cmp6 = (pool_count6 == 1)? 0 : compare6; +assign avg6 = (pool_count6 == 1)? 0 : avg6_int; +assign average6 = (filter_size_int == 8'b1)? avg6_int : (filter_size_int == 8'b10)? avg6_int >> 2 : (filter_size_int == 8'b11)? avg6_int >> 3 : (filter_size_int == 8'b100)? avg6_int >> 4 : avg6_int; + +wire [`DWIDTH-1:0] pool6_wire; +assign pool6_wire = (pool_count7 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare6 : average6) : 8'b0; +always @(posedge clk) begin + pool6 <= pool6_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare7 <= 0; + end + else if (rdata_accum7_pool > cmp7) begin + compare7 <= rdata_accum7_pool; + end + else if (rdata_accum7_pool < cmp7) begin + compare7 <= cmp7; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg7_int <= 0; + end + else begin + avg7_int <= avg7 + rdata_accum7_pool; + end +end + +assign cmp7 = (pool_count7 == 1)? 0 : compare7; +assign avg7 = (pool_count7 == 1)? 0 : avg7_int; +assign average7 = (filter_size_int == 8'b1)? avg7_int : (filter_size_int == 8'b10)? avg7_int >> 2 : (filter_size_int == 8'b11)? avg7_int >> 3 : (filter_size_int == 8'b100)? avg7_int >> 4 : avg7_int; + +wire [`DWIDTH-1:0] pool7_wire; +assign pool7_wire = (pool_count8 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare7 : average7) : 8'b0; +always @(posedge clk) begin + pool7 <= pool7_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare8 <= 0; + end + else if (rdata_accum8_pool > cmp8) begin + compare8 <= rdata_accum8_pool; + end + else if (rdata_accum8_pool < cmp8) begin + compare8 <= cmp8; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg8_int <= 0; + end + else begin + avg8_int <= avg8 + rdata_accum8_pool; + end +end + +assign cmp8 = (pool_count8 == 1)? 0 : compare8; +assign avg8 = (pool_count8 == 1)? 0 : avg8_int; +assign average8 = (filter_size_int == 8'b1)? avg8_int : (filter_size_int == 8'b10)? avg8_int >> 2 : (filter_size_int == 8'b11)? avg8_int >> 3 : (filter_size_int == 8'b100)? avg8_int >> 4 : avg8_int; + +wire [`DWIDTH-1:0] pool8_wire; +assign pool8_wire = (pool_count9 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare8 : average8) : 8'b0; +always @(posedge clk) begin + pool8 <= pool8_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare9 <= 0; + end + else if (rdata_accum9_pool > cmp9) begin + compare9 <= rdata_accum9_pool; + end + else if (rdata_accum9_pool < cmp9) begin + compare9 <= cmp9; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg9_int <= 0; + end + else begin + avg9_int <= avg9 + rdata_accum9_pool; + end +end + +assign cmp9 = (pool_count9 == 1)? 0 : compare9; +assign avg9 = (pool_count9 == 1)? 0 : avg9_int; +assign average9 = (filter_size_int == 8'b1)? avg9_int : (filter_size_int == 8'b10)? avg9_int >> 2 : (filter_size_int == 8'b11)? avg9_int >> 3 : (filter_size_int == 8'b100)? avg9_int >> 4 : avg9_int; + +wire [`DWIDTH-1:0] pool9_wire; +assign pool9_wire = (pool_count10 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare9 : average9) : 8'b0; +always @(posedge clk) begin + pool9 <= pool9_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare10 <= 0; + end + else if (rdata_accum10_pool > cmp10) begin + compare10 <= rdata_accum10_pool; + end + else if (rdata_accum10_pool < cmp10) begin + compare10 <= cmp10; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg10_int <= 0; + end + else begin + avg10_int <= avg10 + rdata_accum10_pool; + end +end + +assign cmp10 = (pool_count10 == 1)? 0 : compare10; +assign avg10 = (pool_count10 == 1)? 0 : avg10_int; +assign average10 = (filter_size_int == 8'b1)? avg10_int : (filter_size_int == 8'b10)? avg10_int >> 2 : (filter_size_int == 8'b11)? avg10_int >> 3 : (filter_size_int == 8'b100)? avg10_int >> 4 : avg10_int; + +wire [`DWIDTH-1:0] pool10_wire; +assign pool10_wire = (pool_count11 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare10 : average10) : 8'b0; +always @(posedge clk) begin + pool10 <= pool10_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare11 <= 0; + end + else if (rdata_accum11_pool > cmp11) begin + compare11 <= rdata_accum11_pool; + end + else if (rdata_accum11_pool < cmp11) begin + compare11 <= cmp11; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg11_int <= 0; + end + else begin + avg11_int <= avg11 + rdata_accum11_pool; + end +end + +assign cmp11 = (pool_count11 == 1)? 0 : compare11; +assign avg11 = (pool_count11 == 1)? 0 : avg11_int; +assign average11 = (filter_size_int == 8'b1)? avg11_int : (filter_size_int == 8'b10)? avg11_int >> 2 : (filter_size_int == 8'b11)? avg11_int >> 3 : (filter_size_int == 8'b100)? avg11_int >> 4 : avg11_int; + +wire [`DWIDTH-1:0] pool11_wire; +assign pool11_wire = (pool_count12 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare11 : average11) : 8'b0; +always @(posedge clk) begin + pool11 <= pool11_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare12 <= 0; + end + else if (rdata_accum12_pool > cmp12) begin + compare12 <= rdata_accum12_pool; + end + else if (rdata_accum12_pool < cmp12) begin + compare12 <= cmp12; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg12_int <= 0; + end + else begin + avg12_int <= avg12 + rdata_accum12_pool; + end +end + +assign cmp12 = (pool_count12 == 1)? 0 : compare12; +assign avg12 = (pool_count12 == 1)? 0 : avg12_int; +assign average12 = (filter_size_int == 8'b1)? avg12_int : (filter_size_int == 8'b10)? avg12_int >> 2 : (filter_size_int == 8'b11)? avg12_int >> 3 : (filter_size_int == 8'b100)? avg12_int >> 4 : avg12_int; + +wire [`DWIDTH-1:0] pool12_wire; +assign pool12_wire = (pool_count13 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare12 : average12) : 8'b0; +always @(posedge clk) begin + pool12 <= pool12_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare13 <= 0; + end + else if (rdata_accum13_pool > cmp13) begin + compare13 <= rdata_accum13_pool; + end + else if (rdata_accum13_pool < cmp13) begin + compare13 <= cmp13; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg13_int <= 0; + end + else begin + avg13_int <= avg13 + rdata_accum13_pool; + end +end + +assign cmp13 = (pool_count13 == 1)? 0 : compare13; +assign avg13 = (pool_count13 == 1)? 0 : avg13_int; +assign average13 = (filter_size_int == 8'b1)? avg13_int : (filter_size_int == 8'b10)? avg13_int >> 2 : (filter_size_int == 8'b11)? avg13_int >> 3 : (filter_size_int == 8'b100)? avg13_int >> 4 : avg13_int; + +wire [`DWIDTH-1:0] pool13_wire; +assign pool13_wire = (pool_count14 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare13 : average13) : 8'b0; +always @(posedge clk) begin + pool13 <= pool13_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare14 <= 0; + end + else if (rdata_accum14_pool > cmp14) begin + compare14 <= rdata_accum14_pool; + end + else if (rdata_accum14_pool < cmp14) begin + compare14 <= cmp14; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg14_int <= 0; + end + else begin + avg14_int <= avg14 + rdata_accum14_pool; + end +end + +assign cmp14 = (pool_count14 == 1)? 0 : compare14; +assign avg14 = (pool_count14 == 1)? 0 : avg14_int; +assign average14 = (filter_size_int == 8'b1)? avg14_int : (filter_size_int == 8'b10)? avg14_int >> 2 : (filter_size_int == 8'b11)? avg14_int >> 3 : (filter_size_int == 8'b100)? avg14_int >> 4 : avg14_int; + +wire [`DWIDTH-1:0] pool14_wire; +assign pool14_wire = (pool_count15 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare14 : average14) : 8'b0; +always @(posedge clk) begin + pool14 <= pool14_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare15 <= 0; + end + else if (rdata_accum15_pool > cmp15) begin + compare15 <= rdata_accum15_pool; + end + else if (rdata_accum15_pool < cmp15) begin + compare15 <= cmp15; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg15_int <= 0; + end + else begin + avg15_int <= avg15 + rdata_accum15_pool; + end +end + +assign cmp15 = (pool_count15 == 1)? 0 : compare15; +assign avg15 = (pool_count15 == 1)? 0 : avg15_int; +assign average15 = (filter_size_int == 8'b1)? avg15_int : (filter_size_int == 8'b10)? avg15_int >> 2 : (filter_size_int == 8'b11)? avg15_int >> 3 : (filter_size_int == 8'b100)? avg15_int >> 4 : avg15_int; + +wire [`DWIDTH-1:0] pool15_wire; +assign pool15_wire = (pool_count16 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare15 : average15) : 8'b0; +always @(posedge clk) begin + pool15 <= pool15_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare16 <= 0; + end + else if (rdata_accum16_pool > cmp16) begin + compare16 <= rdata_accum16_pool; + end + else if (rdata_accum16_pool < cmp16) begin + compare16 <= cmp16; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg16_int <= 0; + end + else begin + avg16_int <= avg16 + rdata_accum16_pool; + end +end + +assign cmp16 = (pool_count16 == 1)? 0 : compare16; +assign avg16 = (pool_count16 == 1)? 0 : avg16_int; +assign average16 = (filter_size_int == 8'b1)? avg16_int : (filter_size_int == 8'b10)? avg16_int >> 2 : (filter_size_int == 8'b11)? avg16_int >> 3 : (filter_size_int == 8'b100)? avg16_int >> 4 : avg16_int; + +wire [`DWIDTH-1:0] pool16_wire; +assign pool16_wire = (pool_count17 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare16 : average16) : 8'b0; +always @(posedge clk) begin + pool16 <= pool16_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare17 <= 0; + end + else if (rdata_accum17_pool > cmp17) begin + compare17 <= rdata_accum17_pool; + end + else if (rdata_accum17_pool < cmp17) begin + compare17 <= cmp17; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg17_int <= 0; + end + else begin + avg17_int <= avg17 + rdata_accum17_pool; + end +end + +assign cmp17 = (pool_count17 == 1)? 0 : compare17; +assign avg17 = (pool_count17 == 1)? 0 : avg17_int; +assign average17 = (filter_size_int == 8'b1)? avg17_int : (filter_size_int == 8'b10)? avg17_int >> 2 : (filter_size_int == 8'b11)? avg17_int >> 3 : (filter_size_int == 8'b100)? avg17_int >> 4 : avg17_int; + +wire [`DWIDTH-1:0] pool17_wire; +assign pool17_wire = (pool_count18 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare17 : average17) : 8'b0; +always @(posedge clk) begin + pool17 <= pool17_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare18 <= 0; + end + else if (rdata_accum18_pool > cmp18) begin + compare18 <= rdata_accum18_pool; + end + else if (rdata_accum18_pool < cmp18) begin + compare18 <= cmp18; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg18_int <= 0; + end + else begin + avg18_int <= avg18 + rdata_accum18_pool; + end +end + +assign cmp18 = (pool_count18 == 1)? 0 : compare18; +assign avg18 = (pool_count18 == 1)? 0 : avg18_int; +assign average18 = (filter_size_int == 8'b1)? avg18_int : (filter_size_int == 8'b10)? avg18_int >> 2 : (filter_size_int == 8'b11)? avg18_int >> 3 : (filter_size_int == 8'b100)? avg18_int >> 4 : avg18_int; + +wire [`DWIDTH-1:0] pool18_wire; +assign pool18_wire = (pool_count19 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare18 : average18) : 8'b0; +always @(posedge clk) begin + pool18 <= pool18_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare19 <= 0; + end + else if (rdata_accum19_pool > cmp19) begin + compare19 <= rdata_accum19_pool; + end + else if (rdata_accum19_pool < cmp19) begin + compare19 <= cmp19; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg19_int <= 0; + end + else begin + avg19_int <= avg19 + rdata_accum19_pool; + end +end + +assign cmp19 = (pool_count19 == 1)? 0 : compare19; +assign avg19 = (pool_count19 == 1)? 0 : avg19_int; +assign average19 = (filter_size_int == 8'b1)? avg19_int : (filter_size_int == 8'b10)? avg19_int >> 2 : (filter_size_int == 8'b11)? avg19_int >> 3 : (filter_size_int == 8'b100)? avg19_int >> 4 : avg19_int; + +wire [`DWIDTH-1:0] pool19_wire; +assign pool19_wire = (pool_count20 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare19 : average19) : 8'b0; +always @(posedge clk) begin + pool19 <= pool19_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare20 <= 0; + end + else if (rdata_accum20_pool > cmp20) begin + compare20 <= rdata_accum20_pool; + end + else if (rdata_accum20_pool < cmp20) begin + compare20 <= cmp20; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg20_int <= 0; + end + else begin + avg20_int <= avg20 + rdata_accum20_pool; + end +end + +assign cmp20 = (pool_count20 == 1)? 0 : compare20; +assign avg20 = (pool_count20 == 1)? 0 : avg20_int; +assign average20 = (filter_size_int == 8'b1)? avg20_int : (filter_size_int == 8'b10)? avg20_int >> 2 : (filter_size_int == 8'b11)? avg20_int >> 3 : (filter_size_int == 8'b100)? avg20_int >> 4 : avg20_int; + +wire [`DWIDTH-1:0] pool20_wire; +assign pool20_wire = (pool_count21 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare20 : average20) : 8'b0; +always @(posedge clk) begin + pool20 <= pool20_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare21 <= 0; + end + else if (rdata_accum21_pool > cmp21) begin + compare21 <= rdata_accum21_pool; + end + else if (rdata_accum21_pool < cmp21) begin + compare21 <= cmp21; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg21_int <= 0; + end + else begin + avg21_int <= avg21 + rdata_accum21_pool; + end +end + +assign cmp21 = (pool_count21 == 1)? 0 : compare21; +assign avg21 = (pool_count21 == 1)? 0 : avg21_int; +assign average21 = (filter_size_int == 8'b1)? avg21_int : (filter_size_int == 8'b10)? avg21_int >> 2 : (filter_size_int == 8'b11)? avg21_int >> 3 : (filter_size_int == 8'b100)? avg21_int >> 4 : avg21_int; + +wire [`DWIDTH-1:0] pool21_wire; +assign pool21_wire = (pool_count22 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare21 : average21) : 8'b0; +always @(posedge clk) begin + pool21 <= pool21_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare22 <= 0; + end + else if (rdata_accum22_pool > cmp22) begin + compare22 <= rdata_accum22_pool; + end + else if (rdata_accum22_pool < cmp22) begin + compare22 <= cmp22; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg22_int <= 0; + end + else begin + avg22_int <= avg22 + rdata_accum22_pool; + end +end + +assign cmp22 = (pool_count22 == 1)? 0 : compare22; +assign avg22 = (pool_count22 == 1)? 0 : avg22_int; +assign average22 = (filter_size_int == 8'b1)? avg22_int : (filter_size_int == 8'b10)? avg22_int >> 2 : (filter_size_int == 8'b11)? avg22_int >> 3 : (filter_size_int == 8'b100)? avg22_int >> 4 : avg22_int; + +wire [`DWIDTH-1:0] pool22_wire; +assign pool22_wire = (pool_count23 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare22 : average22) : 8'b0; +always @(posedge clk) begin + pool22 <= pool22_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare23 <= 0; + end + else if (rdata_accum23_pool > cmp23) begin + compare23 <= rdata_accum23_pool; + end + else if (rdata_accum23_pool < cmp23) begin + compare23 <= cmp23; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg23_int <= 0; + end + else begin + avg23_int <= avg23 + rdata_accum23_pool; + end +end + +assign cmp23 = (pool_count23 == 1)? 0 : compare23; +assign avg23 = (pool_count23 == 1)? 0 : avg23_int; +assign average23 = (filter_size_int == 8'b1)? avg23_int : (filter_size_int == 8'b10)? avg23_int >> 2 : (filter_size_int == 8'b11)? avg23_int >> 3 : (filter_size_int == 8'b100)? avg23_int >> 4 : avg23_int; + +wire [`DWIDTH-1:0] pool23_wire; +assign pool23_wire = (pool_count24 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare23 : average23) : 8'b0; +always @(posedge clk) begin + pool23 <= pool23_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare24 <= 0; + end + else if (rdata_accum24_pool > cmp24) begin + compare24 <= rdata_accum24_pool; + end + else if (rdata_accum24_pool < cmp24) begin + compare24 <= cmp24; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg24_int <= 0; + end + else begin + avg24_int <= avg24 + rdata_accum24_pool; + end +end + +assign cmp24 = (pool_count24 == 1)? 0 : compare24; +assign avg24 = (pool_count24 == 1)? 0 : avg24_int; +assign average24 = (filter_size_int == 8'b1)? avg24_int : (filter_size_int == 8'b10)? avg24_int >> 2 : (filter_size_int == 8'b11)? avg24_int >> 3 : (filter_size_int == 8'b100)? avg24_int >> 4 : avg24_int; + +wire [`DWIDTH-1:0] pool24_wire; +assign pool24_wire = (pool_count25 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare24 : average24) : 8'b0; +always @(posedge clk) begin + pool24 <= pool24_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare25 <= 0; + end + else if (rdata_accum25_pool > cmp25) begin + compare25 <= rdata_accum25_pool; + end + else if (rdata_accum25_pool < cmp25) begin + compare25 <= cmp25; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg25_int <= 0; + end + else begin + avg25_int <= avg25 + rdata_accum25_pool; + end +end + +assign cmp25 = (pool_count25 == 1)? 0 : compare25; +assign avg25 = (pool_count25 == 1)? 0 : avg25_int; +assign average25 = (filter_size_int == 8'b1)? avg25_int : (filter_size_int == 8'b10)? avg25_int >> 2 : (filter_size_int == 8'b11)? avg25_int >> 3 : (filter_size_int == 8'b100)? avg25_int >> 4 : avg25_int; + +wire [`DWIDTH-1:0] pool25_wire; +assign pool25_wire = (pool_count26 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare25 : average25) : 8'b0; +always @(posedge clk) begin + pool25 <= pool25_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare26 <= 0; + end + else if (rdata_accum26_pool > cmp26) begin + compare26 <= rdata_accum26_pool; + end + else if (rdata_accum26_pool < cmp26) begin + compare26 <= cmp26; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg26_int <= 0; + end + else begin + avg26_int <= avg26 + rdata_accum26_pool; + end +end + +assign cmp26 = (pool_count26 == 1)? 0 : compare26; +assign avg26 = (pool_count26 == 1)? 0 : avg26_int; +assign average26 = (filter_size_int == 8'b1)? avg26_int : (filter_size_int == 8'b10)? avg26_int >> 2 : (filter_size_int == 8'b11)? avg26_int >> 3 : (filter_size_int == 8'b100)? avg26_int >> 4 : avg26_int; + +wire [`DWIDTH-1:0] pool26_wire; +assign pool26_wire = (pool_count27 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare26 : average26) : 8'b0; +always @(posedge clk) begin + pool26 <= pool26_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare27 <= 0; + end + else if (rdata_accum27_pool > cmp27) begin + compare27 <= rdata_accum27_pool; + end + else if (rdata_accum27_pool < cmp27) begin + compare27 <= cmp27; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg27_int <= 0; + end + else begin + avg27_int <= avg27 + rdata_accum27_pool; + end +end + +assign cmp27 = (pool_count27 == 1)? 0 : compare27; +assign avg27 = (pool_count27 == 1)? 0 : avg27_int; +assign average27 = (filter_size_int == 8'b1)? avg27_int : (filter_size_int == 8'b10)? avg27_int >> 2 : (filter_size_int == 8'b11)? avg27_int >> 3 : (filter_size_int == 8'b100)? avg27_int >> 4 : avg27_int; + +wire [`DWIDTH-1:0] pool27_wire; +assign pool27_wire = (pool_count28 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare27 : average27) : 8'b0; +always @(posedge clk) begin + pool27 <= pool27_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare28 <= 0; + end + else if (rdata_accum28_pool > cmp28) begin + compare28 <= rdata_accum28_pool; + end + else if (rdata_accum28_pool < cmp28) begin + compare28 <= cmp28; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg28_int <= 0; + end + else begin + avg28_int <= avg28 + rdata_accum28_pool; + end +end + +assign cmp28 = (pool_count28 == 1)? 0 : compare28; +assign avg28 = (pool_count28 == 1)? 0 : avg28_int; +assign average28 = (filter_size_int == 8'b1)? avg28_int : (filter_size_int == 8'b10)? avg28_int >> 2 : (filter_size_int == 8'b11)? avg28_int >> 3 : (filter_size_int == 8'b100)? avg28_int >> 4 : avg28_int; + +wire [`DWIDTH-1:0] pool28_wire; +assign pool28_wire = (pool_count29 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare28 : average28) : 8'b0; +always @(posedge clk) begin + pool28 <= pool28_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare29 <= 0; + end + else if (rdata_accum29_pool > cmp29) begin + compare29 <= rdata_accum29_pool; + end + else if (rdata_accum29_pool < cmp29) begin + compare29 <= cmp29; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg29_int <= 0; + end + else begin + avg29_int <= avg29 + rdata_accum29_pool; + end +end + +assign cmp29 = (pool_count29 == 1)? 0 : compare29; +assign avg29 = (pool_count29 == 1)? 0 : avg29_int; +assign average29 = (filter_size_int == 8'b1)? avg29_int : (filter_size_int == 8'b10)? avg29_int >> 2 : (filter_size_int == 8'b11)? avg29_int >> 3 : (filter_size_int == 8'b100)? avg29_int >> 4 : avg29_int; + +wire [`DWIDTH-1:0] pool29_wire; +assign pool29_wire = (pool_count30 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare29 : average29) : 8'b0; +always @(posedge clk) begin + pool29 <= pool29_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare30 <= 0; + end + else if (rdata_accum30_pool > cmp30) begin + compare30 <= rdata_accum30_pool; + end + else if (rdata_accum30_pool < cmp30) begin + compare30 <= cmp30; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg30_int <= 0; + end + else begin + avg30_int <= avg30 + rdata_accum30_pool; + end +end + +assign cmp30 = (pool_count30 == 1)? 0 : compare30; +assign avg30 = (pool_count30 == 1)? 0 : avg30_int; +assign average30 = (filter_size_int == 8'b1)? avg30_int : (filter_size_int == 8'b10)? avg30_int >> 2 : (filter_size_int == 8'b11)? avg30_int >> 3 : (filter_size_int == 8'b100)? avg30_int >> 4 : avg30_int; + +wire [`DWIDTH-1:0] pool30_wire; +assign pool30_wire = (pool_count31 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare30 : average30) : 8'b0; +always @(posedge clk) begin + pool30 <= pool30_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare31 <= 0; + end + else if (rdata_accum31_pool > cmp31) begin + compare31 <= rdata_accum31_pool; + end + else if (rdata_accum31_pool < cmp31) begin + compare31 <= cmp31; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg31_int <= 0; + end + else begin + avg31_int <= avg31 + rdata_accum31_pool; + end +end + +assign cmp31 = (pool_count31 == 1)? 0 : compare31; +assign avg31 = (pool_count31 == 1)? 0 : avg31_int; +assign average31 = (filter_size_int == 8'b1)? avg31_int : (filter_size_int == 8'b10)? avg31_int >> 2 : (filter_size_int == 8'b11)? avg31_int >> 3 : (filter_size_int == 8'b100)? avg31_int >> 4 : avg31_int; + +wire [`DWIDTH-1:0] pool31_wire; +assign pool31_wire = (pool_count32 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare31 : average31) : 8'b0; +always @(posedge clk) begin + pool31 <= pool31_wire; +end + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM generate_activation.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// +module activation( + input activation_type, + input enable_activation, + input enable_pool, + input in_data_available, + input [`DWIDTH-1:0] inp_data0, + input [`DWIDTH-1:0] inp_data1, + input [`DWIDTH-1:0] inp_data2, + input [`DWIDTH-1:0] inp_data3, + input [`DWIDTH-1:0] inp_data4, + input [`DWIDTH-1:0] inp_data5, + input [`DWIDTH-1:0] inp_data6, + input [`DWIDTH-1:0] inp_data7, + input [`DWIDTH-1:0] inp_data8, + input [`DWIDTH-1:0] inp_data9, + input [`DWIDTH-1:0] inp_data10, + input [`DWIDTH-1:0] inp_data11, + input [`DWIDTH-1:0] inp_data12, + input [`DWIDTH-1:0] inp_data13, + input [`DWIDTH-1:0] inp_data14, + input [`DWIDTH-1:0] inp_data15, + input [`DWIDTH-1:0] inp_data16, + input [`DWIDTH-1:0] inp_data17, + input [`DWIDTH-1:0] inp_data18, + input [`DWIDTH-1:0] inp_data19, + input [`DWIDTH-1:0] inp_data20, + input [`DWIDTH-1:0] inp_data21, + input [`DWIDTH-1:0] inp_data22, + input [`DWIDTH-1:0] inp_data23, + input [`DWIDTH-1:0] inp_data24, + input [`DWIDTH-1:0] inp_data25, + input [`DWIDTH-1:0] inp_data26, + input [`DWIDTH-1:0] inp_data27, + input [`DWIDTH-1:0] inp_data28, + input [`DWIDTH-1:0] inp_data29, + input [`DWIDTH-1:0] inp_data30, + input [`DWIDTH-1:0] inp_data31, + output [`DWIDTH-1:0] out_data0, + output [`DWIDTH-1:0] out_data1, + output [`DWIDTH-1:0] out_data2, + output [`DWIDTH-1:0] out_data3, + output [`DWIDTH-1:0] out_data4, + output [`DWIDTH-1:0] out_data5, + output [`DWIDTH-1:0] out_data6, + output [`DWIDTH-1:0] out_data7, + output [`DWIDTH-1:0] out_data8, + output [`DWIDTH-1:0] out_data9, + output [`DWIDTH-1:0] out_data10, + output [`DWIDTH-1:0] out_data11, + output [`DWIDTH-1:0] out_data12, + output [`DWIDTH-1:0] out_data13, + output [`DWIDTH-1:0] out_data14, + output [`DWIDTH-1:0] out_data15, + output [`DWIDTH-1:0] out_data16, + output [`DWIDTH-1:0] out_data17, + output [`DWIDTH-1:0] out_data18, + output [`DWIDTH-1:0] out_data19, + output [`DWIDTH-1:0] out_data20, + output [`DWIDTH-1:0] out_data21, + output [`DWIDTH-1:0] out_data22, + output [`DWIDTH-1:0] out_data23, + output [`DWIDTH-1:0] out_data24, + output [`DWIDTH-1:0] out_data25, + output [`DWIDTH-1:0] out_data26, + output [`DWIDTH-1:0] out_data27, + output [`DWIDTH-1:0] out_data28, + output [`DWIDTH-1:0] out_data29, + output [`DWIDTH-1:0] out_data30, + output [`DWIDTH-1:0] out_data31, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output reg done_activation, + input clk, + input reset +); + +reg in_data_available1; +reg in_data_available2; +reg in_data_available3; +reg in_data_available4; +reg in_data_available5; +reg in_data_available6; +reg in_data_available7; +reg in_data_available8; +reg in_data_available9; +reg in_data_available10; +reg in_data_available11; +reg in_data_available12; +reg in_data_available13; +reg in_data_available14; +reg in_data_available15; +reg in_data_available16; +reg in_data_available17; +reg in_data_available18; +reg in_data_available19; +reg in_data_available20; +reg in_data_available21; +reg in_data_available22; +reg in_data_available23; +reg in_data_available24; +reg in_data_available25; +reg in_data_available26; +reg in_data_available27; +reg in_data_available28; +reg in_data_available29; +reg in_data_available30; +reg in_data_available31; + +always @(posedge clk) begin + in_data_available1 <= in_data_available; + in_data_available2 <= in_data_available1; + in_data_available3 <= in_data_available2; + in_data_available4 <= in_data_available3; + in_data_available5 <= in_data_available4; + in_data_available6 <= in_data_available5; + in_data_available7 <= in_data_available6; + in_data_available8 <= in_data_available7; + in_data_available9 <= in_data_available8; + in_data_available10 <= in_data_available9; + in_data_available11 <= in_data_available10; + in_data_available12 <= in_data_available11; + in_data_available13 <= in_data_available12; + in_data_available14 <= in_data_available13; + in_data_available15 <= in_data_available14; + in_data_available16 <= in_data_available15; + in_data_available17 <= in_data_available16; + in_data_available18 <= in_data_available17; + in_data_available19 <= in_data_available18; + in_data_available20 <= in_data_available19; + in_data_available21 <= in_data_available20; + in_data_available22 <= in_data_available21; + in_data_available23 <= in_data_available22; + in_data_available24 <= in_data_available23; + in_data_available25 <= in_data_available24; + in_data_available26 <= in_data_available25; + in_data_available27 <= in_data_available26; + in_data_available28 <= in_data_available27; + in_data_available29 <= in_data_available28; + in_data_available30 <= in_data_available29; + in_data_available31 <= in_data_available30; +end + +wire out_data_available_internal; +assign out_data_available = enable_pool? enable_activation ? out_data_available_internal : in_data_available : in_data_available2; + + +wire out_data_available_final; +reg [`DWIDTH-1:0] act_count; +reg [`DWIDTH-1:0] done_activation_count; + +always @(posedge clk) begin + if (reset) begin + done_activation <= 0; + done_activation_count <= 0; + act_count <= 0; + end + else if (done_activation_count == `MAT_MUL_SIZE) + done_activation <= 0; + else if (act_count == 4) begin + done_activation <= 1; + done_activation_count <= done_activation_count + 1; + end + else if (out_data_available_final == 1) begin + act_count <= act_count + 1; + end +end + +sub_activation activation0( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available), + .inp_data(inp_data0), + .out_data(out_data0), + .out_data_available(out_data_available_internal), + .validity_mask(validity_mask[0]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC1; +sub_activation activation1( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available1), + .inp_data(inp_data1), + .out_data(out_data1), + .out_data_available(out_data_available_NC1), + .validity_mask(validity_mask[1]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC2; +sub_activation activation2( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available2), + .inp_data(inp_data2), + .out_data(out_data2), + .out_data_available(out_data_available_NC2), + .validity_mask(validity_mask[2]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC3; +sub_activation activation3( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available3), + .inp_data(inp_data3), + .out_data(out_data3), + .out_data_available(out_data_available_NC3), + .validity_mask(validity_mask[3]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC4; +sub_activation activation4( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available4), + .inp_data(inp_data4), + .out_data(out_data4), + .out_data_available(out_data_available_NC4), + .validity_mask(validity_mask[4]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC5; +sub_activation activation5( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available5), + .inp_data(inp_data5), + .out_data(out_data5), + .out_data_available(out_data_available_NC5), + .validity_mask(validity_mask[5]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC6; +sub_activation activation6( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available6), + .inp_data(inp_data6), + .out_data(out_data6), + .out_data_available(out_data_available_NC6), + .validity_mask(validity_mask[6]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC7; +sub_activation activation7( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available7), + .inp_data(inp_data7), + .out_data(out_data7), + .out_data_available(out_data_available_NC7), + .validity_mask(validity_mask[7]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC8; +sub_activation activation8( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available8), + .inp_data(inp_data8), + .out_data(out_data8), + .out_data_available(out_data_available_NC8), + .validity_mask(validity_mask[8]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC9; +sub_activation activation9( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available9), + .inp_data(inp_data9), + .out_data(out_data9), + .out_data_available(out_data_available_NC9), + .validity_mask(validity_mask[9]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC10; +sub_activation activation10( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available10), + .inp_data(inp_data10), + .out_data(out_data10), + .out_data_available(out_data_available_NC10), + .validity_mask(validity_mask[10]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC11; +sub_activation activation11( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available11), + .inp_data(inp_data11), + .out_data(out_data11), + .out_data_available(out_data_available_NC11), + .validity_mask(validity_mask[11]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC12; +sub_activation activation12( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available12), + .inp_data(inp_data12), + .out_data(out_data12), + .out_data_available(out_data_available_NC12), + .validity_mask(validity_mask[12]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC13; +sub_activation activation13( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available13), + .inp_data(inp_data13), + .out_data(out_data13), + .out_data_available(out_data_available_NC13), + .validity_mask(validity_mask[13]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC14; +sub_activation activation14( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available14), + .inp_data(inp_data14), + .out_data(out_data14), + .out_data_available(out_data_available_NC14), + .validity_mask(validity_mask[14]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC15; +sub_activation activation15( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available15), + .inp_data(inp_data15), + .out_data(out_data15), + .out_data_available(out_data_available_NC15), + .validity_mask(validity_mask[15]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC16; +sub_activation activation16( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available16), + .inp_data(inp_data16), + .out_data(out_data16), + .out_data_available(out_data_available_NC16), + .validity_mask(validity_mask[16]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC17; +sub_activation activation17( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available17), + .inp_data(inp_data17), + .out_data(out_data17), + .out_data_available(out_data_available_NC17), + .validity_mask(validity_mask[17]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC18; +sub_activation activation18( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available18), + .inp_data(inp_data18), + .out_data(out_data18), + .out_data_available(out_data_available_NC18), + .validity_mask(validity_mask[18]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC19; +sub_activation activation19( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available19), + .inp_data(inp_data19), + .out_data(out_data19), + .out_data_available(out_data_available_NC19), + .validity_mask(validity_mask[19]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC20; +sub_activation activation20( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available20), + .inp_data(inp_data20), + .out_data(out_data20), + .out_data_available(out_data_available_NC20), + .validity_mask(validity_mask[20]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC21; +sub_activation activation21( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available21), + .inp_data(inp_data21), + .out_data(out_data21), + .out_data_available(out_data_available_NC21), + .validity_mask(validity_mask[21]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC22; +sub_activation activation22( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available22), + .inp_data(inp_data22), + .out_data(out_data22), + .out_data_available(out_data_available_NC22), + .validity_mask(validity_mask[22]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC23; +sub_activation activation23( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available23), + .inp_data(inp_data23), + .out_data(out_data23), + .out_data_available(out_data_available_NC23), + .validity_mask(validity_mask[23]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC24; +sub_activation activation24( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available24), + .inp_data(inp_data24), + .out_data(out_data24), + .out_data_available(out_data_available_NC24), + .validity_mask(validity_mask[24]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC25; +sub_activation activation25( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available25), + .inp_data(inp_data25), + .out_data(out_data25), + .out_data_available(out_data_available_NC25), + .validity_mask(validity_mask[25]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC26; +sub_activation activation26( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available26), + .inp_data(inp_data26), + .out_data(out_data26), + .out_data_available(out_data_available_NC26), + .validity_mask(validity_mask[26]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC27; +sub_activation activation27( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available27), + .inp_data(inp_data27), + .out_data(out_data27), + .out_data_available(out_data_available_NC27), + .validity_mask(validity_mask[27]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC28; +sub_activation activation28( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available28), + .inp_data(inp_data28), + .out_data(out_data28), + .out_data_available(out_data_available_NC28), + .validity_mask(validity_mask[28]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC29; +sub_activation activation29( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available29), + .inp_data(inp_data29), + .out_data(out_data29), + .out_data_available(out_data_available_NC29), + .validity_mask(validity_mask[29]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC30; +sub_activation activation30( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available30), + .inp_data(inp_data30), + .out_data(out_data30), + .out_data_available(out_data_available_NC30), + .validity_mask(validity_mask[30]), + .clk(clk), + .reset(reset) +); + +sub_activation activation31( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available31), + .inp_data(inp_data31), + .out_data(out_data31), + .out_data_available(out_data_available_final), + .validity_mask(validity_mask[31]), + .clk(clk), + .reset(reset) +); + +endmodule + +module sub_activation( + input activation_type, + input enable_activation, + input in_data_available, + input [`DWIDTH-1:0] inp_data, + output [`DWIDTH-1:0] out_data, + output out_data_available, + input validity_mask, + input clk, + input reset +); + +reg out_data_available_internal; +reg [`DWIDTH-1:0] out_data_internal; +reg [`DWIDTH-1:0] slope_applied_data_internal; +reg [`DWIDTH-1:0] intercept_applied_data_internal; +reg [`DWIDTH-1:0] relu_applied_data_internal; + +reg [31:0] cycle_count; +reg activation_in_progress; + +reg [3:0] address; +reg [`DWIDTH-1:0] data_slope; +reg [`DWIDTH-1:0] data_intercept; +reg [`DWIDTH-1:0] data_intercept_delayed; + +// If the activation block is not enabled, just forward the input data +assign out_data = enable_activation ? out_data_internal : inp_data; +assign out_data_available = enable_activation ? out_data_available_internal : in_data_available; + +always @(posedge clk) begin + if (reset || ~enable_activation) begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + end + else if(in_data_available || activation_in_progress) begin + cycle_count <= cycle_count + 1; + if(activation_type==1'b1) begin // tanH + slope_applied_data_internal <= data_slope * inp_data; + data_intercept_delayed <= data_intercept; + intercept_applied_data_internal <= slope_applied_data_internal + data_intercept_delayed; + end else begin // ReLU + relu_applied_data_internal <= (inp_data)? {`DWIDTH{1'b0}} : inp_data; + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if (cycle_count==2) begin + out_data_available_internal <= 1; + end + end else begin + if (cycle_count==1) begin + out_data_available_internal <= 1; + end + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if(cycle_count==2) begin + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end else begin + if(cycle_count==1) begin + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end + end + else begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + end +end + +always @ (posedge clk) begin + if (activation_type == 1'b1) + out_data_internal <= intercept_applied_data_internal; + else + out_data_internal <= relu_applied_data_internal; +end + +//Our equation of tanh is Y=AX+B +//A is the slope and B is the intercept. +//We store A in one LUT and B in another. +//LUT for the slope +always @(address) begin + case (address) + 4'b0000: data_slope = 8'd0; + 4'b0001: data_slope = 8'd0; + 4'b0010: data_slope = 8'd2; + 4'b0011: data_slope = 8'd3; + 4'b0100: data_slope = 8'd4; + 4'b0101: data_slope = 8'd0; + 4'b0110: data_slope = 8'd4; + 4'b0111: data_slope = 8'd3; + 4'b1000: data_slope = 8'd2; + 4'b1001: data_slope = 8'd0; + 4'b1010: data_slope = 8'd0; + default: data_slope = 8'd0; + endcase +end + +//LUT for the intercept +always @(address) begin + case (address) + 4'b0000: data_intercept = 8'd127; + 4'b0001: data_intercept = 8'd99; + 4'b0010: data_intercept = 8'd46; + 4'b0011: data_intercept = 8'd18; + 4'b0100: data_intercept = 8'd0; + 4'b0101: data_intercept = 8'd0; + 4'b0110: data_intercept = 8'd0; + 4'b0111: data_intercept = -8'd18; + 4'b1000: data_intercept = -8'd46; + 4'b1001: data_intercept = -8'd99; + 4'b1010: data_intercept = -8'd127; + default: data_intercept = 8'd0; + endcase +end + +//Logic to find address +always @(inp_data) begin + if((inp_data)>=90) begin + address = 4'b0000; + end + else if ((inp_data)>=39 && (inp_data)<90) begin + address = 4'b0001; + end + else if ((inp_data)>=28 && (inp_data)<39) begin + address = 4'b0010; + end + else if ((inp_data)>=16 && (inp_data)<28) begin + address = 4'b0011; + end + else if ((inp_data)>=1 && (inp_data)<16) begin + address = 4'b0100; + end + else if ((inp_data)==0) begin + address = 4'b0101; + end + else if ((inp_data)>-16 && (inp_data)<=-1) begin + address = 4'b0110; + end + else if ((inp_data)>-28 && (inp_data)<=-16) begin + address = 4'b0111; + end + else if ((inp_data)>-39 && (inp_data)<=-28) begin + address = 4'b1000; + end + else if ((inp_data)>-90 && (inp_data)<=-39) begin + address = 4'b1001; + end + else if ((inp_data)<=-90) begin + address = 4'b1010; + end + else begin + address = 4'b0101; + end +end + +//Adding a dummy signal to use validity_mask input, to make ODIN happy +//TODO: Need to correctly use validity_mask +wire [`MASK_WIDTH-1:0] dummy; +assign dummy = validity_mask; + + +endmodule + +module top( + input clk, + input clk_mem, + input reset, + input resetn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output [`REG_DATAWIDTH-1:0] PRDATA, + output PREADY, + input [`AWIDTH-1:0] bram_addr_a_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a_ext, + input [`DESIGN_SIZE-1:0] bram_we_a_ext, + input [`AWIDTH-1:0] bram_addr_b_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b_ext, + input [`DESIGN_SIZE-1:0] bram_we_b_ext +); + +wire [`AWIDTH-1:0] bram_addr_a; +wire [`AWIDTH-1:0] bram_addr_a_for_reading; +reg [`AWIDTH-1:0] bram_addr_a_for_writing; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a; +reg [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a; +wire [`DESIGN_SIZE-1:0] bram_we_a; +wire bram_en_a; +wire [`AWIDTH-1:0] bram_addr_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b; +wire [`DESIGN_SIZE-1:0] bram_we_b; +wire bram_en_b; +reg bram_a_wdata_available; +wire [`AWIDTH-1:0] bram_addr_c_NC; +wire start_tpu; +wire done_tpu; +wire start_mat_mul; +wire done_mat_mul; +wire norm_out_data_available; +wire done_norm; +wire pool_out_data_available; +wire done_pool; +wire activation_out_data_available; +wire done_activation; +wire enable_matmul; +wire enable_norm; +wire enable_activation; +wire enable_pool; +wire [31:0] num_matrices_A; +wire [31:0] num_matrices_B; +wire [`DWIDTH-1:0] matrix_size; +wire [`DWIDTH-1:0] filter_size; +wire pool_select; +wire [`DWIDTH-1:0] k_dimension; +wire accum_select; +wire [`DESIGN_SIZE*`DWIDTH-1:0] matmul_c_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] pool_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] activation_data_out; +wire matmul_c_data_available; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_in_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_in_NC; +wire [`DWIDTH-1:0] mean; +wire [`DWIDTH-1:0] inv_var; +wire [`AWIDTH-1:0] address_mat_a; +wire [`AWIDTH-1:0] address_mat_b; +wire [`AWIDTH-1:0] address_mat_c; +wire [`MASK_WIDTH-1:0] validity_mask_a_rows; +wire [`MASK_WIDTH-1:0] validity_mask_a_cols_b_rows; +wire [`MASK_WIDTH-1:0] validity_mask_b_cols; +wire save_output_to_accum; +wire add_accum_to_output; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +wire [`MAX_BITS_POOL-1:0] pool_window_size; +wire activation_type; +wire [3:0] conv_filter_height; +wire [3:0] conv_filter_width; +wire [3:0] conv_stride_horiz; +wire [3:0] conv_stride_verti; +wire [3:0] conv_padding_left; +wire [3:0] conv_padding_right; +wire [3:0] conv_padding_top; +wire [3:0] conv_padding_bottom; +wire [15:0] num_channels_inp; +wire [15:0] num_channels_out; +wire [15:0] inp_img_height; +wire [15:0] inp_img_width; +wire [15:0] out_img_height; +wire [15:0] out_img_width; +wire [31:0] batch_size; +wire enable_conv_mode; +wire pe_reset; +wire start_pool; +wire pool_norm_valid; + +`ifdef DESIGN_SIZE_32 +wire [`DWIDTH-1:0] matrixC31_0; +wire [`DWIDTH-1:0] matrixC31_1; +wire [`DWIDTH-1:0] matrixC31_2; +wire [`DWIDTH-1:0] matrixC31_3; +wire [`DWIDTH-1:0] matrixC31_4; +wire [`DWIDTH-1:0] matrixC31_5; +wire [`DWIDTH-1:0] matrixC31_6; +wire [`DWIDTH-1:0] matrixC31_7; +wire [`DWIDTH-1:0] matrixC31_8; +wire [`DWIDTH-1:0] matrixC31_9; +wire [`DWIDTH-1:0] matrixC31_10; +wire [`DWIDTH-1:0] matrixC31_11; +wire [`DWIDTH-1:0] matrixC31_12; +wire [`DWIDTH-1:0] matrixC31_13; +wire [`DWIDTH-1:0] matrixC31_14; +wire [`DWIDTH-1:0] matrixC31_15; +wire [`DWIDTH-1:0] matrixC31_16; +wire [`DWIDTH-1:0] matrixC31_17; +wire [`DWIDTH-1:0] matrixC31_18; +wire [`DWIDTH-1:0] matrixC31_19; +wire [`DWIDTH-1:0] matrixC31_20; +wire [`DWIDTH-1:0] matrixC31_21; +wire [`DWIDTH-1:0] matrixC31_22; +wire [`DWIDTH-1:0] matrixC31_23; +wire [`DWIDTH-1:0] matrixC31_24; +wire [`DWIDTH-1:0] matrixC31_25; +wire [`DWIDTH-1:0] matrixC31_26; +wire [`DWIDTH-1:0] matrixC31_27; +wire [`DWIDTH-1:0] matrixC31_28; +wire [`DWIDTH-1:0] matrixC31_29; +wire [`DWIDTH-1:0] matrixC31_30; +wire [`DWIDTH-1:0] matrixC31_31; +`endif +`ifdef DESIGN_SIZE_16 +wire [`DWIDTH-1:0] matrixC15_0; +wire [`DWIDTH-1:0] matrixC15_1; +wire [`DWIDTH-1:0] matrixC15_2; +wire [`DWIDTH-1:0] matrixC15_3; +wire [`DWIDTH-1:0] matrixC15_4; +wire [`DWIDTH-1:0] matrixC15_5; +wire [`DWIDTH-1:0] matrixC15_6; +wire [`DWIDTH-1:0] matrixC15_7; +wire [`DWIDTH-1:0] matrixC15_8; +wire [`DWIDTH-1:0] matrixC15_9; +wire [`DWIDTH-1:0] matrixC15_10; +wire [`DWIDTH-1:0] matrixC15_11; +wire [`DWIDTH-1:0] matrixC15_12; +wire [`DWIDTH-1:0] matrixC15_13; +wire [`DWIDTH-1:0] matrixC15_14; +wire [`DWIDTH-1:0] matrixC15_15; +`endif +`ifdef DESIGN_SIZE_8 +wire [`DWIDTH-1:0] matrixC7_0; +wire [`DWIDTH-1:0] matrixC7_1; +wire [`DWIDTH-1:0] matrixC7_2; +wire [`DWIDTH-1:0] matrixC7_3; +wire [`DWIDTH-1:0] matrixC7_4; +wire [`DWIDTH-1:0] matrixC7_5; +wire [`DWIDTH-1:0] matrixC7_6; +wire [`DWIDTH-1:0] matrixC7_7; +`endif +`ifdef DESIGN_SIZE_4 +wire [`DWIDTH-1:0] matrixC3_0; +wire [`DWIDTH-1:0] matrixC3_1; +wire [`DWIDTH-1:0] matrixC3_2; +wire [`DWIDTH-1:0] matrixC3_3; +`endif + +wire [`AWIDTH-1:0] start_waddr_accum0; + +assign start_waddr_accum0 = 11'b0; + +`ifdef DESIGN_SIZE_8 +wire [`DWIDTH-1:0] rdata_accum0_pool; +wire [`DWIDTH-1:0] rdata_accum1_pool; +wire [`DWIDTH-1:0] rdata_accum2_pool; +wire [`DWIDTH-1:0] rdata_accum3_pool; +wire [`DWIDTH-1:0] rdata_accum4_pool; +wire [`DWIDTH-1:0] rdata_accum5_pool; +wire [`DWIDTH-1:0] rdata_accum6_pool; +wire [`DWIDTH-1:0] rdata_accum7_pool; +wire [`AWIDTH-1:0] raddr_accum0_pool; +wire [`AWIDTH-1:0] raddr_accum1_pool; +wire [`AWIDTH-1:0] raddr_accum2_pool; +wire [`AWIDTH-1:0] raddr_accum3_pool; +wire [`AWIDTH-1:0] raddr_accum4_pool; +wire [`AWIDTH-1:0] raddr_accum5_pool; +wire [`AWIDTH-1:0] raddr_accum6_pool; +wire [`AWIDTH-1:0] raddr_accum7_pool; +`endif + +`ifdef DESIGN_SIZE_16 +wire [`DWIDTH-1:0] rdata_accum0_pool; +wire [`DWIDTH-1:0] rdata_accum1_pool; +wire [`DWIDTH-1:0] rdata_accum2_pool; +wire [`DWIDTH-1:0] rdata_accum3_pool; +wire [`DWIDTH-1:0] rdata_accum4_pool; +wire [`DWIDTH-1:0] rdata_accum5_pool; +wire [`DWIDTH-1:0] rdata_accum6_pool; +wire [`DWIDTH-1:0] rdata_accum7_pool; +wire [`DWIDTH-1:0] rdata_accum8_pool; +wire [`DWIDTH-1:0] rdata_accum9_pool; +wire [`DWIDTH-1:0] rdata_accum10_pool; +wire [`DWIDTH-1:0] rdata_accum11_pool; +wire [`DWIDTH-1:0] rdata_accum12_pool; +wire [`DWIDTH-1:0] rdata_accum13_pool; +wire [`DWIDTH-1:0] rdata_accum14_pool; +wire [`DWIDTH-1:0] rdata_accum15_pool; +wire [`AWIDTH-1:0] raddr_accum0_pool; +wire [`AWIDTH-1:0] raddr_accum1_pool; +wire [`AWIDTH-1:0] raddr_accum2_pool; +wire [`AWIDTH-1:0] raddr_accum3_pool; +wire [`AWIDTH-1:0] raddr_accum4_pool; +wire [`AWIDTH-1:0] raddr_accum5_pool; +wire [`AWIDTH-1:0] raddr_accum6_pool; +wire [`AWIDTH-1:0] raddr_accum7_pool; +wire [`AWIDTH-1:0] raddr_accum8_pool; +wire [`AWIDTH-1:0] raddr_accum9_pool; +wire [`AWIDTH-1:0] raddr_accum10_pool; +wire [`AWIDTH-1:0] raddr_accum11_pool; +wire [`AWIDTH-1:0] raddr_accum12_pool; +wire [`AWIDTH-1:0] raddr_accum13_pool; +wire [`AWIDTH-1:0] raddr_accum14_pool; +wire [`AWIDTH-1:0] raddr_accum15_pool; +`endif + +`ifdef DESIGN_SIZE_32 +wire [`DWIDTH-1:0] rdata_accum0_pool; +wire [`DWIDTH-1:0] rdata_accum1_pool; +wire [`DWIDTH-1:0] rdata_accum2_pool; +wire [`DWIDTH-1:0] rdata_accum3_pool; +wire [`DWIDTH-1:0] rdata_accum4_pool; +wire [`DWIDTH-1:0] rdata_accum5_pool; +wire [`DWIDTH-1:0] rdata_accum6_pool; +wire [`DWIDTH-1:0] rdata_accum7_pool; +wire [`DWIDTH-1:0] rdata_accum8_pool; +wire [`DWIDTH-1:0] rdata_accum9_pool; +wire [`DWIDTH-1:0] rdata_accum10_pool; +wire [`DWIDTH-1:0] rdata_accum11_pool; +wire [`DWIDTH-1:0] rdata_accum12_pool; +wire [`DWIDTH-1:0] rdata_accum13_pool; +wire [`DWIDTH-1:0] rdata_accum14_pool; +wire [`DWIDTH-1:0] rdata_accum15_pool; +wire [`DWIDTH-1:0] rdata_accum16_pool; +wire [`DWIDTH-1:0] rdata_accum17_pool; +wire [`DWIDTH-1:0] rdata_accum18_pool; +wire [`DWIDTH-1:0] rdata_accum19_pool; +wire [`DWIDTH-1:0] rdata_accum20_pool; +wire [`DWIDTH-1:0] rdata_accum21_pool; +wire [`DWIDTH-1:0] rdata_accum22_pool; +wire [`DWIDTH-1:0] rdata_accum23_pool; +wire [`DWIDTH-1:0] rdata_accum24_pool; +wire [`DWIDTH-1:0] rdata_accum25_pool; +wire [`DWIDTH-1:0] rdata_accum26_pool; +wire [`DWIDTH-1:0] rdata_accum27_pool; +wire [`DWIDTH-1:0] rdata_accum28_pool; +wire [`DWIDTH-1:0] rdata_accum29_pool; +wire [`DWIDTH-1:0] rdata_accum30_pool; +wire [`DWIDTH-1:0] rdata_accum31_pool; +wire [`AWIDTH-1:0] raddr_accum0_pool; +wire [`AWIDTH-1:0] raddr_accum1_pool; +wire [`AWIDTH-1:0] raddr_accum2_pool; +wire [`AWIDTH-1:0] raddr_accum3_pool; +wire [`AWIDTH-1:0] raddr_accum4_pool; +wire [`AWIDTH-1:0] raddr_accum5_pool; +wire [`AWIDTH-1:0] raddr_accum6_pool; +wire [`AWIDTH-1:0] raddr_accum7_pool; +wire [`AWIDTH-1:0] raddr_accum8_pool; +wire [`AWIDTH-1:0] raddr_accum9_pool; +wire [`AWIDTH-1:0] raddr_accum10_pool; +wire [`AWIDTH-1:0] raddr_accum11_pool; +wire [`AWIDTH-1:0] raddr_accum12_pool; +wire [`AWIDTH-1:0] raddr_accum13_pool; +wire [`AWIDTH-1:0] raddr_accum14_pool; +wire [`AWIDTH-1:0] raddr_accum15_pool; +wire [`AWIDTH-1:0] raddr_accum16_pool; +wire [`AWIDTH-1:0] raddr_accum17_pool; +wire [`AWIDTH-1:0] raddr_accum18_pool; +wire [`AWIDTH-1:0] raddr_accum19_pool; +wire [`AWIDTH-1:0] raddr_accum20_pool; +wire [`AWIDTH-1:0] raddr_accum21_pool; +wire [`AWIDTH-1:0] raddr_accum22_pool; +wire [`AWIDTH-1:0] raddr_accum23_pool; +wire [`AWIDTH-1:0] raddr_accum24_pool; +wire [`AWIDTH-1:0] raddr_accum25_pool; +wire [`AWIDTH-1:0] raddr_accum26_pool; +wire [`AWIDTH-1:0] raddr_accum27_pool; +wire [`AWIDTH-1:0] raddr_accum28_pool; +wire [`AWIDTH-1:0] raddr_accum29_pool; +wire [`AWIDTH-1:0] raddr_accum30_pool; +wire [`AWIDTH-1:0] raddr_accum31_pool; +`endif + +//Connections for bram a (activation/input matrix) +//bram_addr_a -> connected to u_matmul_4x4 +//bram_rdata_a -> connected to u_matmul_4x4 +//bram_wdata_a -> will come from the last block that is enabled +//bram_we_a -> will be 1 when the last block's data is available +//bram_en_a -> hardcoded to 1 +assign bram_addr_a = (bram_a_wdata_available) ? bram_addr_a_for_writing : bram_addr_a_for_reading; +assign bram_en_a = 1'b1; +assign bram_we_a = (bram_a_wdata_available) ? {`DESIGN_SIZE{1'b1}} : {`DESIGN_SIZE{1'b0}}; + +//Connections for bram b (weights matrix) +//bram_addr_b -> connected to u_matmul_4x4 +//bram_rdata_b -> connected to u_matmul_4x4 +//bram_wdata_b -> hardcoded to 0 (this block only reads from bram b) +//bram_we_b -> hardcoded to 0 (this block only reads from bram b) +//bram_en_b -> hardcoded to 1 +assign bram_wdata_b = {`DESIGN_SIZE*`DWIDTH{1'b0}}; +assign bram_en_b = 1'b1; +assign bram_we_b = {`DESIGN_SIZE{1'b0}}; + +//////////////////////////////////////////////////////////////// +// BRAM matrix A (inputs/activations) +//////////////////////////////////////////////////////////////// +ram #(.AW(`AWIDTH), .MW(`MASK_WIDTH), .DW(`DWIDTH)) matrix_A ( + .addr0(bram_addr_a), + .d0(bram_wdata_a), + .we0(bram_we_a), + .q0(bram_rdata_a), + .addr1(bram_addr_a_ext), + .d1(bram_wdata_a_ext), + .we1(bram_we_a_ext), + .q1(bram_rdata_a_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// BRAM matrix B (weights) +//////////////////////////////////////////////////////////////// +ram #(.AW(`AWIDTH), .MW(`MASK_WIDTH), .DW(`DWIDTH)) matrix_B ( + .addr0(bram_addr_b), + .d0(bram_wdata_b), + .we0(bram_we_b), + .q0(bram_rdata_b), + .addr1(bram_addr_b_ext), + .d1(bram_wdata_b_ext), + .we1(bram_we_b_ext), + .q1(bram_rdata_b_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// Control logic that directs all the operation +//////////////////////////////////////////////////////////////// +control u_control( + .clk(clk), + .reset(reset), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_activation(enable_activation), + .enable_pool(enable_pool), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .done_norm(done_norm), + .done_pool(done_pool), + .done_activation(done_activation), + .save_output_to_accum(save_output_to_accum), + .done_tpu(done_tpu) +); + +//////////////////////////////////////////////////////////////// +// Configuration (register) block +//////////////////////////////////////////////////////////////// +cfg u_cfg( + .PCLK(clk), + .PRESETn(resetn), + .PADDR(PADDR), + .PWRITE(PWRITE), + .PSEL(PSEL), + .PENABLE(PENABLE), + .PWDATA(PWDATA), + .PRDATA(PRDATA), + .PREADY(PREADY), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_pool(enable_pool), + .enable_activation(enable_activation), + .enable_conv_mode(enable_conv_mode), + .mean(mean), + .inv_var(inv_var), + .pool_window_size(pool_window_size), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .num_matrices_A(num_matrices_A), + .num_matrices_B(num_matrices_B), + .matrix_size(matrix_size), + .filter_size(filter_size), + .pool_select(pool_select), + .k_dimension(k_dimension), // Dimension of A = m x k, Dimension of B = k x n + .accum_select(accum_select), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols_b_rows(validity_mask_a_cols_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .save_output_to_accum(save_output_to_accum), + .add_accum_to_output(add_accum_to_output), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .activation_type(activation_type), + .conv_filter_height(conv_filter_height), + .conv_filter_width(conv_filter_width), + .conv_stride_horiz(conv_stride_horiz), + .conv_stride_verti(conv_stride_verti), + .conv_padding_left(conv_padding_left), + .conv_padding_right(conv_padding_right), + .conv_padding_top(conv_padding_top), + .conv_padding_bottom(conv_padding_bottom), + .num_channels_inp(num_channels_inp), + .num_channels_out(num_channels_out), + .inp_img_height(inp_img_height), + .inp_img_width(inp_img_width), + .out_img_height(out_img_height), + .out_img_width(out_img_width), + .batch_size(batch_size), + .pe_reset(pe_reset), + .done_tpu(done_tpu) +); + +//TODO: We want to move the data setup part +//and the interface to BRAM_A and BRAM_B outside +//into its own modules. For now, it is all inside +//the matmul block + +//////////////////////////////////////////////////////////////// +//Matrix multiplier +//Note: the ports on this module to write data to bram c +//are not used in this top module. +//////////////////////////////////////////////////////////////// +`ifdef DESIGN_SIZE_32 +matmul_32x32_systolic u_matmul( +`endif +`ifdef DESIGN_SIZE_16 +matmul_16x16_systolic u_matmul( +`endif +`ifdef DESIGN_SIZE_8 +matmul_8x8_systolic u_matmul( +`endif +`ifdef DESIGN_SIZE_4 +matmul_4x4_systolic u_matmul( +`endif + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .num_matrices_A(num_matrices_A), + .num_matrices_B(num_matrices_B), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .a_data(bram_rdata_a), + .b_data(bram_rdata_b), + .a_data_in(a_data_in_NC), + .b_data_in(b_data_in_NC), + .c_data_in({`DESIGN_SIZE*`DWIDTH{1'b0}}), + .c_data_out(matmul_c_data_out), + .a_data_out(a_data_out_NC), + .b_data_out(b_data_out_NC), + .a_addr(bram_addr_a_for_reading), + .b_addr(bram_addr_b), + .c_addr(bram_addr_c_NC), + .c_data_available(matmul_c_data_available), + `ifdef DESIGN_SIZE_32 + .matrixC31_0(matrixC31_0), + .matrixC31_1(matrixC31_1), + .matrixC31_2(matrixC31_2), + .matrixC31_3(matrixC31_3), + .matrixC31_4(matrixC31_4), + .matrixC31_5(matrixC31_5), + .matrixC31_6(matrixC31_6), + .matrixC31_7(matrixC31_7), + .matrixC31_8(matrixC31_8), + .matrixC31_9(matrixC31_9), + .matrixC31_10(matrixC31_10), + .matrixC31_11(matrixC31_11), + .matrixC31_12(matrixC31_12), + .matrixC31_13(matrixC31_13), + .matrixC31_14(matrixC31_14), + .matrixC31_15(matrixC31_15), + .matrixC31_16(matrixC31_16), + .matrixC31_17(matrixC31_17), + .matrixC31_18(matrixC31_18), + .matrixC31_19(matrixC31_19), + .matrixC31_20(matrixC31_20), + .matrixC31_21(matrixC31_21), + .matrixC31_22(matrixC31_22), + .matrixC31_23(matrixC31_23), + .matrixC31_24(matrixC31_24), + .matrixC31_25(matrixC31_25), + .matrixC31_26(matrixC31_26), + .matrixC31_27(matrixC31_27), + .matrixC31_28(matrixC31_28), + .matrixC31_29(matrixC31_29), + .matrixC31_30(matrixC31_30), + .matrixC31_31(matrixC31_31), + `endif + `ifdef DESIGN_SIZE_16 + .matrixC15_0(matrixC15_0), + .matrixC15_1(matrixC15_1), + .matrixC15_2(matrixC15_2), + .matrixC15_3(matrixC15_3), + .matrixC15_4(matrixC15_4), + .matrixC15_5(matrixC15_5), + .matrixC15_6(matrixC15_6), + .matrixC15_7(matrixC15_7), + .matrixC15_8(matrixC15_8), + .matrixC15_9(matrixC15_9), + .matrixC15_10(matrixC15_10), + .matrixC15_11(matrixC15_11), + .matrixC15_12(matrixC15_12), + .matrixC15_13(matrixC15_13), + .matrixC15_14(matrixC15_14), + .matrixC15_15(matrixC15_15), + `endif + `ifdef DESIGN_SIZE_8 + .matrixC7_0(matrixC7_0), + .matrixC7_1(matrixC7_1), + .matrixC7_2(matrixC7_2), + .matrixC7_3(matrixC7_3), + .matrixC7_4(matrixC7_4), + .matrixC7_5(matrixC7_5), + .matrixC7_6(matrixC7_6), + .matrixC7_7(matrixC7_7), + `endif + `ifdef DESIGN_SIZE_4 + .matrixC3_0(matrixC3_0), + .matrixC3_1(matrixC3_1), + .matrixC3_2(matrixC3_2), + .matrixC3_3(matrixC3_3), + `endif + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols_b_rows(validity_mask_a_cols_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .a_loc(64'd0), + .b_loc(64'd0) +); + +//////////////////////////////////////////////////////////////// +// Accumulator module +//////////////////////////////////////////////////////////////// +accumulator u_accum ( + .clk(clk), + .resetn(resetn), + .k_dimension(k_dimension), // Dimension of A = m x k, Dimension of B = k x n + .buffer_select(accum_select), + .start_pooling(start_pool), + .done_pooling(done_pool), + .wdata_available(matmul_c_data_available), + .start_waddr_accum0(start_waddr_accum0), + `ifdef DESIGN_SIZE_8 + .wdata_accum0(matrixC7_0), + .wdata_accum1(matrixC7_1), + .wdata_accum2(matrixC7_2), + .wdata_accum3(matrixC7_3), + .wdata_accum4(matrixC7_4), + .wdata_accum5(matrixC7_5), + .wdata_accum6(matrixC7_6), + .wdata_accum7(matrixC7_7), + .raddr_accum0_pool(raddr_accum0_pool), + .raddr_accum1_pool(raddr_accum1_pool), + .raddr_accum2_pool(raddr_accum2_pool), + .raddr_accum3_pool(raddr_accum3_pool), + .raddr_accum4_pool(raddr_accum4_pool), + .raddr_accum5_pool(raddr_accum5_pool), + .raddr_accum6_pool(raddr_accum6_pool), + .raddr_accum7_pool(raddr_accum7_pool), + .rdata_accum0_pool(rdata_accum0_pool), + .rdata_accum1_pool(rdata_accum1_pool), + .rdata_accum2_pool(rdata_accum2_pool), + .rdata_accum3_pool(rdata_accum3_pool), + .rdata_accum4_pool(rdata_accum4_pool), + .rdata_accum5_pool(rdata_accum5_pool), + .rdata_accum6_pool(rdata_accum6_pool), + .rdata_accum7_pool(rdata_accum7_pool) + `endif + `ifdef DESIGN_SIZE_16 + .wdata_accum0(matrixC15_0), + .wdata_accum1(matrixC15_1), + .wdata_accum2(matrixC15_2), + .wdata_accum3(matrixC15_3), + .wdata_accum4(matrixC15_4), + .wdata_accum5(matrixC15_5), + .wdata_accum6(matrixC15_6), + .wdata_accum7(matrixC15_7), + .wdata_accum8(matrixC15_8), + .wdata_accum9(matrixC15_9), + .wdata_accum10(matrixC15_10), + .wdata_accum11(matrixC15_11), + .wdata_accum12(matrixC15_12), + .wdata_accum13(matrixC15_13), + .wdata_accum14(matrixC15_14), + .wdata_accum15(matrixC15_15), + .raddr_accum0_pool(raddr_accum0_pool), + .raddr_accum1_pool(raddr_accum1_pool), + .raddr_accum2_pool(raddr_accum2_pool), + .raddr_accum3_pool(raddr_accum3_pool), + .raddr_accum4_pool(raddr_accum4_pool), + .raddr_accum5_pool(raddr_accum5_pool), + .raddr_accum6_pool(raddr_accum6_pool), + .raddr_accum7_pool(raddr_accum7_pool), + .raddr_accum8_pool(raddr_accum8_pool), + .raddr_accum9_pool(raddr_accum9_pool), + .raddr_accum10_pool(raddr_accum10_pool), + .raddr_accum11_pool(raddr_accum11_pool), + .raddr_accum12_pool(raddr_accum12_pool), + .raddr_accum13_pool(raddr_accum13_pool), + .raddr_accum14_pool(raddr_accum14_pool), + .raddr_accum15_pool(raddr_accum15_pool), + .rdata_accum0_pool(rdata_accum0_pool), + .rdata_accum1_pool(rdata_accum1_pool), + .rdata_accum2_pool(rdata_accum2_pool), + .rdata_accum3_pool(rdata_accum3_pool), + .rdata_accum4_pool(rdata_accum4_pool), + .rdata_accum5_pool(rdata_accum5_pool), + .rdata_accum6_pool(rdata_accum6_pool), + .rdata_accum7_pool(rdata_accum7_pool), + .rdata_accum8_pool(rdata_accum8_pool), + .rdata_accum9_pool(rdata_accum9_pool), + .rdata_accum10_pool(rdata_accum10_pool), + .rdata_accum11_pool(rdata_accum11_pool), + .rdata_accum12_pool(rdata_accum12_pool), + .rdata_accum13_pool(rdata_accum13_pool), + .rdata_accum14_pool(rdata_accum14_pool), + .rdata_accum15_pool(rdata_accum15_pool) + `endif + `ifdef DESIGN_SIZE_32 + .wdata_accum0(matrixC31_0), + .wdata_accum1(matrixC31_1), + .wdata_accum2(matrixC31_2), + .wdata_accum3(matrixC31_3), + .wdata_accum4(matrixC31_4), + .wdata_accum5(matrixC31_5), + .wdata_accum6(matrixC31_6), + .wdata_accum7(matrixC31_7), + .wdata_accum8(matrixC31_8), + .wdata_accum9(matrixC31_9), + .wdata_accum10(matrixC31_10), + .wdata_accum11(matrixC31_11), + .wdata_accum12(matrixC31_12), + .wdata_accum13(matrixC31_13), + .wdata_accum14(matrixC31_14), + .wdata_accum15(matrixC31_15), + .wdata_accum16(matrixC31_16), + .wdata_accum17(matrixC31_17), + .wdata_accum18(matrixC31_18), + .wdata_accum19(matrixC31_19), + .wdata_accum20(matrixC31_20), + .wdata_accum21(matrixC31_21), + .wdata_accum22(matrixC31_22), + .wdata_accum23(matrixC31_23), + .wdata_accum24(matrixC31_24), + .wdata_accum25(matrixC31_25), + .wdata_accum26(matrixC31_26), + .wdata_accum27(matrixC31_27), + .wdata_accum28(matrixC31_28), + .wdata_accum29(matrixC31_29), + .wdata_accum30(matrixC31_30), + .wdata_accum31(matrixC31_31), + .raddr_accum0_pool(raddr_accum0_pool), + .raddr_accum1_pool(raddr_accum1_pool), + .raddr_accum2_pool(raddr_accum2_pool), + .raddr_accum3_pool(raddr_accum3_pool), + .raddr_accum4_pool(raddr_accum4_pool), + .raddr_accum5_pool(raddr_accum5_pool), + .raddr_accum6_pool(raddr_accum6_pool), + .raddr_accum7_pool(raddr_accum7_pool), + .raddr_accum8_pool(raddr_accum8_pool), + .raddr_accum9_pool(raddr_accum9_pool), + .raddr_accum10_pool(raddr_accum10_pool), + .raddr_accum11_pool(raddr_accum11_pool), + .raddr_accum12_pool(raddr_accum12_pool), + .raddr_accum13_pool(raddr_accum13_pool), + .raddr_accum14_pool(raddr_accum14_pool), + .raddr_accum15_pool(raddr_accum15_pool), + .raddr_accum16_pool(raddr_accum16_pool), + .raddr_accum17_pool(raddr_accum17_pool), + .raddr_accum18_pool(raddr_accum18_pool), + .raddr_accum19_pool(raddr_accum19_pool), + .raddr_accum20_pool(raddr_accum20_pool), + .raddr_accum21_pool(raddr_accum21_pool), + .raddr_accum22_pool(raddr_accum22_pool), + .raddr_accum23_pool(raddr_accum23_pool), + .raddr_accum24_pool(raddr_accum24_pool), + .raddr_accum25_pool(raddr_accum25_pool), + .raddr_accum26_pool(raddr_accum26_pool), + .raddr_accum27_pool(raddr_accum27_pool), + .raddr_accum28_pool(raddr_accum28_pool), + .raddr_accum29_pool(raddr_accum29_pool), + .raddr_accum30_pool(raddr_accum30_pool), + .raddr_accum31_pool(raddr_accum31_pool), + .rdata_accum0_pool(rdata_accum0_pool), + .rdata_accum1_pool(rdata_accum1_pool), + .rdata_accum2_pool(rdata_accum2_pool), + .rdata_accum3_pool(rdata_accum3_pool), + .rdata_accum4_pool(rdata_accum4_pool), + .rdata_accum5_pool(rdata_accum5_pool), + .rdata_accum6_pool(rdata_accum6_pool), + .rdata_accum7_pool(rdata_accum7_pool), + .rdata_accum8_pool(rdata_accum8_pool), + .rdata_accum9_pool(rdata_accum9_pool), + .rdata_accum10_pool(rdata_accum10_pool), + .rdata_accum11_pool(rdata_accum11_pool), + .rdata_accum12_pool(rdata_accum12_pool), + .rdata_accum13_pool(rdata_accum13_pool), + .rdata_accum14_pool(rdata_accum14_pool), + .rdata_accum15_pool(rdata_accum15_pool), + .rdata_accum16_pool(rdata_accum16_pool), + .rdata_accum17_pool(rdata_accum17_pool), + .rdata_accum18_pool(rdata_accum18_pool), + .rdata_accum19_pool(rdata_accum19_pool), + .rdata_accum20_pool(rdata_accum20_pool), + .rdata_accum21_pool(rdata_accum21_pool), + .rdata_accum22_pool(rdata_accum22_pool), + .rdata_accum23_pool(rdata_accum23_pool), + .rdata_accum24_pool(rdata_accum24_pool), + .rdata_accum25_pool(rdata_accum25_pool), + .rdata_accum26_pool(rdata_accum26_pool), + .rdata_accum27_pool(rdata_accum27_pool), + .rdata_accum28_pool(rdata_accum28_pool), + .rdata_accum29_pool(rdata_accum29_pool), + .rdata_accum30_pool(rdata_accum30_pool), + .rdata_accum31_pool(rdata_accum31_pool) + `endif +); + +wire [`DWIDTH-1:0] pool0; +wire [`DWIDTH-1:0] pool1; +wire [`DWIDTH-1:0] pool2; +wire [`DWIDTH-1:0] pool3; +wire [`DWIDTH-1:0] pool4; +wire [`DWIDTH-1:0] pool5; +wire [`DWIDTH-1:0] pool6; +wire [`DWIDTH-1:0] pool7; +wire [`DWIDTH-1:0] pool8; +wire [`DWIDTH-1:0] pool9; +wire [`DWIDTH-1:0] pool10; +wire [`DWIDTH-1:0] pool11; +wire [`DWIDTH-1:0] pool12; +wire [`DWIDTH-1:0] pool13; +wire [`DWIDTH-1:0] pool14; +wire [`DWIDTH-1:0] pool15; +wire [`DWIDTH-1:0] pool16; +wire [`DWIDTH-1:0] pool17; +wire [`DWIDTH-1:0] pool18; +wire [`DWIDTH-1:0] pool19; +wire [`DWIDTH-1:0] pool20; +wire [`DWIDTH-1:0] pool21; +wire [`DWIDTH-1:0] pool22; +wire [`DWIDTH-1:0] pool23; +wire [`DWIDTH-1:0] pool24; +wire [`DWIDTH-1:0] pool25; +wire [`DWIDTH-1:0] pool26; +wire [`DWIDTH-1:0] pool27; +wire [`DWIDTH-1:0] pool28; +wire [`DWIDTH-1:0] pool29; +wire [`DWIDTH-1:0] pool30; +wire [`DWIDTH-1:0] pool31; + +wire [`DWIDTH-1:0] norm_data_out0; +wire [`DWIDTH-1:0] norm_data_out1; +wire [`DWIDTH-1:0] norm_data_out2; +wire [`DWIDTH-1:0] norm_data_out3; +wire [`DWIDTH-1:0] norm_data_out4; +wire [`DWIDTH-1:0] norm_data_out5; +wire [`DWIDTH-1:0] norm_data_out6; +wire [`DWIDTH-1:0] norm_data_out7; +wire [`DWIDTH-1:0] norm_data_out8; +wire [`DWIDTH-1:0] norm_data_out9; +wire [`DWIDTH-1:0] norm_data_out10; +wire [`DWIDTH-1:0] norm_data_out11; +wire [`DWIDTH-1:0] norm_data_out12; +wire [`DWIDTH-1:0] norm_data_out13; +wire [`DWIDTH-1:0] norm_data_out14; +wire [`DWIDTH-1:0] norm_data_out15; +wire [`DWIDTH-1:0] norm_data_out16; +wire [`DWIDTH-1:0] norm_data_out17; +wire [`DWIDTH-1:0] norm_data_out18; +wire [`DWIDTH-1:0] norm_data_out19; +wire [`DWIDTH-1:0] norm_data_out20; +wire [`DWIDTH-1:0] norm_data_out21; +wire [`DWIDTH-1:0] norm_data_out22; +wire [`DWIDTH-1:0] norm_data_out23; +wire [`DWIDTH-1:0] norm_data_out24; +wire [`DWIDTH-1:0] norm_data_out25; +wire [`DWIDTH-1:0] norm_data_out26; +wire [`DWIDTH-1:0] norm_data_out27; +wire [`DWIDTH-1:0] norm_data_out28; +wire [`DWIDTH-1:0] norm_data_out29; +wire [`DWIDTH-1:0] norm_data_out30; +wire [`DWIDTH-1:0] norm_data_out31; + +wire [`DWIDTH-1:0] act_data_out0; +wire [`DWIDTH-1:0] act_data_out1; +wire [`DWIDTH-1:0] act_data_out2; +wire [`DWIDTH-1:0] act_data_out3; +wire [`DWIDTH-1:0] act_data_out4; +wire [`DWIDTH-1:0] act_data_out5; +wire [`DWIDTH-1:0] act_data_out6; +wire [`DWIDTH-1:0] act_data_out7; +wire [`DWIDTH-1:0] act_data_out8; +wire [`DWIDTH-1:0] act_data_out9; +wire [`DWIDTH-1:0] act_data_out10; +wire [`DWIDTH-1:0] act_data_out11; +wire [`DWIDTH-1:0] act_data_out12; +wire [`DWIDTH-1:0] act_data_out13; +wire [`DWIDTH-1:0] act_data_out14; +wire [`DWIDTH-1:0] act_data_out15; +wire [`DWIDTH-1:0] act_data_out16; +wire [`DWIDTH-1:0] act_data_out17; +wire [`DWIDTH-1:0] act_data_out18; +wire [`DWIDTH-1:0] act_data_out19; +wire [`DWIDTH-1:0] act_data_out20; +wire [`DWIDTH-1:0] act_data_out21; +wire [`DWIDTH-1:0] act_data_out22; +wire [`DWIDTH-1:0] act_data_out23; +wire [`DWIDTH-1:0] act_data_out24; +wire [`DWIDTH-1:0] act_data_out25; +wire [`DWIDTH-1:0] act_data_out26; +wire [`DWIDTH-1:0] act_data_out27; +wire [`DWIDTH-1:0] act_data_out28; +wire [`DWIDTH-1:0] act_data_out29; +wire [`DWIDTH-1:0] act_data_out30; +wire [`DWIDTH-1:0] act_data_out31; + +//////////////////////////////////////////////////////////////// +// Pooling module +//////////////////////////////////////////////////////////////// +pooling u_pooling ( + .clk(clk), + .resetn(resetn), + .matrix_size(matrix_size), + .filter_size(filter_size), + .enable_pool(enable_pool), + .pool_select(pool_select), + .start_pooling(start_pool), + .pool_norm_valid(pool_norm_valid), + `ifdef DESIGN_SIZE_8 + .raddr_accum0_pool(raddr_accum0_pool), + .raddr_accum1_pool(raddr_accum1_pool), + .raddr_accum2_pool(raddr_accum2_pool), + .raddr_accum3_pool(raddr_accum3_pool), + .raddr_accum4_pool(raddr_accum4_pool), + .raddr_accum5_pool(raddr_accum5_pool), + .raddr_accum6_pool(raddr_accum6_pool), + .raddr_accum7_pool(raddr_accum7_pool), + .rdata_accum0_pool(rdata_accum0_pool), + .rdata_accum1_pool(rdata_accum1_pool), + .rdata_accum2_pool(rdata_accum2_pool), + .rdata_accum3_pool(rdata_accum3_pool), + .rdata_accum4_pool(rdata_accum4_pool), + .rdata_accum5_pool(rdata_accum5_pool), + .rdata_accum6_pool(rdata_accum6_pool), + .rdata_accum7_pool(rdata_accum7_pool), + .pool0(pool0), + .pool1(pool1), + .pool2(pool2), + .pool3(pool3), + .pool4(pool4), + .pool5(pool5), + .pool6(pool6), + .pool7(pool7) + `endif + `ifdef DESIGN_SIZE_16 + .raddr_accum0_pool(raddr_accum0_pool), + .raddr_accum1_pool(raddr_accum1_pool), + .raddr_accum2_pool(raddr_accum2_pool), + .raddr_accum3_pool(raddr_accum3_pool), + .raddr_accum4_pool(raddr_accum4_pool), + .raddr_accum5_pool(raddr_accum5_pool), + .raddr_accum6_pool(raddr_accum6_pool), + .raddr_accum7_pool(raddr_accum7_pool), + .raddr_accum8_pool(raddr_accum8_pool), + .raddr_accum9_pool(raddr_accum9_pool), + .raddr_accum10_pool(raddr_accum10_pool), + .raddr_accum11_pool(raddr_accum11_pool), + .raddr_accum12_pool(raddr_accum12_pool), + .raddr_accum13_pool(raddr_accum13_pool), + .raddr_accum14_pool(raddr_accum14_pool), + .raddr_accum15_pool(raddr_accum15_pool), + .rdata_accum0_pool(rdata_accum0_pool), + .rdata_accum1_pool(rdata_accum1_pool), + .rdata_accum2_pool(rdata_accum2_pool), + .rdata_accum3_pool(rdata_accum3_pool), + .rdata_accum4_pool(rdata_accum4_pool), + .rdata_accum5_pool(rdata_accum5_pool), + .rdata_accum6_pool(rdata_accum6_pool), + .rdata_accum7_pool(rdata_accum7_pool), + .rdata_accum8_pool(rdata_accum8_pool), + .rdata_accum9_pool(rdata_accum9_pool), + .rdata_accum10_pool(rdata_accum10_pool), + .rdata_accum11_pool(rdata_accum11_pool), + .rdata_accum12_pool(rdata_accum12_pool), + .rdata_accum13_pool(rdata_accum13_pool), + .rdata_accum14_pool(rdata_accum14_pool), + .rdata_accum15_pool(rdata_accum15_pool), + .pool0(pool0), + .pool1(pool1), + .pool2(pool2), + .pool3(pool3), + .pool4(pool4), + .pool5(pool5), + .pool6(pool6), + .pool7(pool7), + .pool8(pool8), + .pool9(pool9), + .pool10(pool10), + .pool11(pool11), + .pool12(pool12), + .pool13(pool13), + .pool14(pool14), + .pool15(pool15) + `endif + `ifdef DESIGN_SIZE_32 + .raddr_accum0_pool(raddr_accum0_pool), + .raddr_accum1_pool(raddr_accum1_pool), + .raddr_accum2_pool(raddr_accum2_pool), + .raddr_accum3_pool(raddr_accum3_pool), + .raddr_accum4_pool(raddr_accum4_pool), + .raddr_accum5_pool(raddr_accum5_pool), + .raddr_accum6_pool(raddr_accum6_pool), + .raddr_accum7_pool(raddr_accum7_pool), + .raddr_accum8_pool(raddr_accum8_pool), + .raddr_accum9_pool(raddr_accum9_pool), + .raddr_accum10_pool(raddr_accum10_pool), + .raddr_accum11_pool(raddr_accum11_pool), + .raddr_accum12_pool(raddr_accum12_pool), + .raddr_accum13_pool(raddr_accum13_pool), + .raddr_accum14_pool(raddr_accum14_pool), + .raddr_accum15_pool(raddr_accum15_pool), + .raddr_accum16_pool(raddr_accum16_pool), + .raddr_accum17_pool(raddr_accum17_pool), + .raddr_accum18_pool(raddr_accum18_pool), + .raddr_accum19_pool(raddr_accum19_pool), + .raddr_accum20_pool(raddr_accum20_pool), + .raddr_accum21_pool(raddr_accum21_pool), + .raddr_accum22_pool(raddr_accum22_pool), + .raddr_accum23_pool(raddr_accum23_pool), + .raddr_accum24_pool(raddr_accum24_pool), + .raddr_accum25_pool(raddr_accum25_pool), + .raddr_accum26_pool(raddr_accum26_pool), + .raddr_accum27_pool(raddr_accum27_pool), + .raddr_accum28_pool(raddr_accum28_pool), + .raddr_accum29_pool(raddr_accum29_pool), + .raddr_accum30_pool(raddr_accum30_pool), + .raddr_accum31_pool(raddr_accum31_pool), + .rdata_accum0_pool(rdata_accum0_pool), + .rdata_accum1_pool(rdata_accum1_pool), + .rdata_accum2_pool(rdata_accum2_pool), + .rdata_accum3_pool(rdata_accum3_pool), + .rdata_accum4_pool(rdata_accum4_pool), + .rdata_accum5_pool(rdata_accum5_pool), + .rdata_accum6_pool(rdata_accum6_pool), + .rdata_accum7_pool(rdata_accum7_pool), + .rdata_accum8_pool(rdata_accum8_pool), + .rdata_accum9_pool(rdata_accum9_pool), + .rdata_accum10_pool(rdata_accum10_pool), + .rdata_accum11_pool(rdata_accum11_pool), + .rdata_accum12_pool(rdata_accum12_pool), + .rdata_accum13_pool(rdata_accum13_pool), + .rdata_accum14_pool(rdata_accum14_pool), + .rdata_accum15_pool(rdata_accum15_pool), + .rdata_accum16_pool(rdata_accum16_pool), + .rdata_accum17_pool(rdata_accum17_pool), + .rdata_accum18_pool(rdata_accum18_pool), + .rdata_accum19_pool(rdata_accum19_pool), + .rdata_accum20_pool(rdata_accum20_pool), + .rdata_accum21_pool(rdata_accum21_pool), + .rdata_accum22_pool(rdata_accum22_pool), + .rdata_accum23_pool(rdata_accum23_pool), + .rdata_accum24_pool(rdata_accum24_pool), + .rdata_accum25_pool(rdata_accum25_pool), + .rdata_accum26_pool(rdata_accum26_pool), + .rdata_accum27_pool(rdata_accum27_pool), + .rdata_accum28_pool(rdata_accum28_pool), + .rdata_accum29_pool(rdata_accum29_pool), + .rdata_accum30_pool(rdata_accum30_pool), + .rdata_accum31_pool(rdata_accum31_pool), + .pool0(pool0), + .pool1(pool1), + .pool2(pool2), + .pool3(pool3), + .pool4(pool4), + .pool5(pool5), + .pool6(pool6), + .pool7(pool7), + .pool8(pool8), + .pool9(pool9), + .pool10(pool10), + .pool11(pool11), + .pool12(pool12), + .pool13(pool13), + .pool14(pool14), + .pool15(pool15), + .pool16(pool16), + .pool17(pool17), + .pool18(pool18), + .pool19(pool19), + .pool20(pool20), + .pool21(pool21), + .pool22(pool22), + .pool23(pool23), + .pool24(pool24), + .pool25(pool25), + .pool26(pool26), + .pool27(pool27), + .pool28(pool28), + .pool29(pool29), + .pool30(pool30), + .pool31(pool31) + `endif +); + + +//////////////////////////////////////////////////////////////// +// Normalization module +//////////////////////////////////////////////////////////////// +norm u_norm( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(pool_norm_valid), + `ifdef DESIGN_SIZE_8 + .inp_data0(pool0), + .inp_data1(pool1), + .inp_data2(pool2), + .inp_data3(pool3), + .inp_data4(pool4), + .inp_data5(pool5), + .inp_data6(pool6), + .inp_data7(pool7), + .out_data0(norm_data_out0), + .out_data1(norm_data_out1), + .out_data2(norm_data_out2), + .out_data3(norm_data_out3), + .out_data4(norm_data_out4), + .out_data5(norm_data_out5), + .out_data6(norm_data_out6), + .out_data7(norm_data_out7), + `endif + `ifdef DESIGN_SIZE_16 + .inp_data0(pool0), + .inp_data1(pool1), + .inp_data2(pool2), + .inp_data3(pool3), + .inp_data4(pool4), + .inp_data5(pool5), + .inp_data6(pool6), + .inp_data7(pool7), + .inp_data8(pool8), + .inp_data9(pool9), + .inp_data10(pool10), + .inp_data11(pool11), + .inp_data12(pool12), + .inp_data13(pool13), + .inp_data14(pool14), + .inp_data15(pool15), + .out_data0(norm_data_out0), + .out_data1(norm_data_out1), + .out_data2(norm_data_out2), + .out_data3(norm_data_out3), + .out_data4(norm_data_out4), + .out_data5(norm_data_out5), + .out_data6(norm_data_out6), + .out_data7(norm_data_out7), + .out_data8(norm_data_out8), + .out_data9(norm_data_out9), + .out_data10(norm_data_out10), + .out_data11(norm_data_out11), + .out_data12(norm_data_out12), + .out_data13(norm_data_out13), + .out_data14(norm_data_out14), + .out_data15(norm_data_out15), + `endif + `ifdef DESIGN_SIZE_32 + .inp_data0(pool0), + .inp_data1(pool1), + .inp_data2(pool2), + .inp_data3(pool3), + .inp_data4(pool4), + .inp_data5(pool5), + .inp_data6(pool6), + .inp_data7(pool7), + .inp_data8(pool8), + .inp_data9(pool9), + .inp_data10(pool10), + .inp_data11(pool11), + .inp_data12(pool12), + .inp_data13(pool13), + .inp_data14(pool14), + .inp_data15(pool15), + .inp_data16(pool16), + .inp_data17(pool17), + .inp_data18(pool18), + .inp_data19(pool19), + .inp_data20(pool20), + .inp_data21(pool21), + .inp_data22(pool22), + .inp_data23(pool23), + .inp_data24(pool24), + .inp_data25(pool25), + .inp_data26(pool26), + .inp_data27(pool27), + .inp_data28(pool28), + .inp_data29(pool29), + .inp_data30(pool30), + .inp_data31(pool31), + .out_data0(norm_data_out0), + .out_data1(norm_data_out1), + .out_data2(norm_data_out2), + .out_data3(norm_data_out3), + .out_data4(norm_data_out4), + .out_data5(norm_data_out5), + .out_data6(norm_data_out6), + .out_data7(norm_data_out7), + .out_data8(norm_data_out8), + .out_data9(norm_data_out9), + .out_data10(norm_data_out10), + .out_data11(norm_data_out11), + .out_data12(norm_data_out12), + .out_data13(norm_data_out13), + .out_data14(norm_data_out14), + .out_data15(norm_data_out15), + .out_data16(norm_data_out16), + .out_data17(norm_data_out17), + .out_data18(norm_data_out18), + .out_data19(norm_data_out19), + .out_data20(norm_data_out20), + .out_data21(norm_data_out21), + .out_data22(norm_data_out22), + .out_data23(norm_data_out23), + .out_data24(norm_data_out24), + .out_data25(norm_data_out25), + .out_data26(norm_data_out26), + .out_data27(norm_data_out27), + .out_data28(norm_data_out28), + .out_data29(norm_data_out29), + .out_data30(norm_data_out30), + .out_data31(norm_data_out31), + `endif + .out_data_available(norm_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_norm(done_norm), + .clk(clk), + .reset(reset) +); + +//////////////////////////////////////////////////////////////// +// Activation module +//////////////////////////////////////////////////////////////// +activation u_activation( + .activation_type(activation_type), + .enable_activation(enable_activation), + .enable_pool(enable_pool), + .in_data_available(norm_out_data_available), + `ifdef DESIGN_SIZE_8 + .inp_data0(norm_data_out0), + .inp_data1(norm_data_out1), + .inp_data2(norm_data_out2), + .inp_data3(norm_data_out3), + .inp_data4(norm_data_out4), + .inp_data5(norm_data_out5), + .inp_data6(norm_data_out6), + .inp_data7(norm_data_out7), + .out_data0(act_data_out0), + .out_data1(act_data_out1), + .out_data2(act_data_out2), + .out_data3(act_data_out3), + .out_data4(act_data_out4), + .out_data5(act_data_out5), + .out_data6(act_data_out6), + .out_data7(act_data_out7), + `endif + `ifdef DESIGN_SIZE_16 + .inp_data0(norm_data_out0), + .inp_data1(norm_data_out1), + .inp_data2(norm_data_out2), + .inp_data3(norm_data_out3), + .inp_data4(norm_data_out4), + .inp_data5(norm_data_out5), + .inp_data6(norm_data_out6), + .inp_data7(norm_data_out7), + .inp_data8(norm_data_out8), + .inp_data9(norm_data_out9), + .inp_data10(norm_data_out10), + .inp_data11(norm_data_out11), + .inp_data12(norm_data_out12), + .inp_data13(norm_data_out13), + .inp_data14(norm_data_out14), + .inp_data15(norm_data_out15), + .out_data0(act_data_out0), + .out_data1(act_data_out1), + .out_data2(act_data_out2), + .out_data3(act_data_out3), + .out_data4(act_data_out4), + .out_data5(act_data_out5), + .out_data6(act_data_out6), + .out_data7(act_data_out7), + .out_data8(act_data_out8), + .out_data9(act_data_out9), + .out_data10(act_data_out10), + .out_data11(act_data_out11), + .out_data12(act_data_out12), + .out_data13(act_data_out13), + .out_data14(act_data_out14), + .out_data15(act_data_out15), + `endif + `ifdef DESIGN_SIZE_32 + .inp_data0(norm_data_out0), + .inp_data1(norm_data_out1), + .inp_data2(norm_data_out2), + .inp_data3(norm_data_out3), + .inp_data4(norm_data_out4), + .inp_data5(norm_data_out5), + .inp_data6(norm_data_out6), + .inp_data7(norm_data_out7), + .inp_data8(norm_data_out8), + .inp_data9(norm_data_out9), + .inp_data10(norm_data_out10), + .inp_data11(norm_data_out11), + .inp_data12(norm_data_out12), + .inp_data13(norm_data_out13), + .inp_data14(norm_data_out14), + .inp_data15(norm_data_out15), + .inp_data16(norm_data_out16), + .inp_data17(norm_data_out17), + .inp_data18(norm_data_out18), + .inp_data19(norm_data_out19), + .inp_data20(norm_data_out20), + .inp_data21(norm_data_out21), + .inp_data22(norm_data_out22), + .inp_data23(norm_data_out23), + .inp_data24(norm_data_out24), + .inp_data25(norm_data_out25), + .inp_data26(norm_data_out26), + .inp_data27(norm_data_out27), + .inp_data28(norm_data_out28), + .inp_data29(norm_data_out29), + .inp_data30(norm_data_out30), + .inp_data31(norm_data_out31), + .out_data0(act_data_out0), + .out_data1(act_data_out1), + .out_data2(act_data_out2), + .out_data3(act_data_out3), + .out_data4(act_data_out4), + .out_data5(act_data_out5), + .out_data6(act_data_out6), + .out_data7(act_data_out7), + .out_data8(act_data_out8), + .out_data9(act_data_out9), + .out_data10(act_data_out10), + .out_data11(act_data_out11), + .out_data12(act_data_out12), + .out_data13(act_data_out13), + .out_data14(act_data_out14), + .out_data15(act_data_out15), + .out_data16(act_data_out16), + .out_data17(act_data_out17), + .out_data18(act_data_out18), + .out_data19(act_data_out19), + .out_data20(act_data_out20), + .out_data21(act_data_out21), + .out_data22(act_data_out22), + .out_data23(act_data_out23), + .out_data24(act_data_out24), + .out_data25(act_data_out25), + .out_data26(act_data_out26), + .out_data27(act_data_out27), + .out_data28(act_data_out28), + .out_data29(act_data_out29), + .out_data30(act_data_out30), + .out_data31(act_data_out31), + `endif + .out_data_available(activation_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_activation(done_activation), + .clk(clk), + .reset(reset) +); + +//Interface to BRAM to write the output. +//Ideally, we could remove this flop stage. But then we'd +//have to generate the address for the output BRAM in each +//block that could potentially write the output. + +reg activation_out_data_available1; +reg activation_out_data_available2; +reg activation_out_data_available3; +reg activation_out_data_available4; +reg activation_out_data_available5; +reg activation_out_data_available6; +reg activation_out_data_available7; + +`ifdef DESIGN_SIZE_16 +reg activation_out_data_available8; +reg activation_out_data_available9; +reg activation_out_data_available10; +reg activation_out_data_available11; +reg activation_out_data_available12; +reg activation_out_data_available13; +reg activation_out_data_available14; +reg activation_out_data_available15; +`endif + +`ifdef DESIGN_SIZE_32 +reg activation_out_data_available8; +reg activation_out_data_available9; +reg activation_out_data_available10; +reg activation_out_data_available11; +reg activation_out_data_available12; +reg activation_out_data_available13; +reg activation_out_data_available14; +reg activation_out_data_available15; +reg activation_out_data_available16; +reg activation_out_data_available17; +reg activation_out_data_available18; +reg activation_out_data_available19; +reg activation_out_data_available20; +reg activation_out_data_available21; +reg activation_out_data_available22; +reg activation_out_data_available23; +reg activation_out_data_available24; +reg activation_out_data_available25; +reg activation_out_data_available26; +reg activation_out_data_available27; +reg activation_out_data_available28; +reg activation_out_data_available29; +reg activation_out_data_available30; +reg activation_out_data_available31; +`endif + +always @(posedge clk) begin + activation_out_data_available1 <= activation_out_data_available; + activation_out_data_available2 <= activation_out_data_available1; + activation_out_data_available3 <= activation_out_data_available2; + activation_out_data_available4 <= activation_out_data_available3; + activation_out_data_available5 <= activation_out_data_available4; + activation_out_data_available6 <= activation_out_data_available5; + activation_out_data_available7 <= activation_out_data_available6; +end + +`ifdef DESIGN_SIZE_16 +always @(posedge clk) begin + activation_out_data_available8 <= activation_out_data_available7; + activation_out_data_available9 <= activation_out_data_available8; + activation_out_data_available10 <= activation_out_data_available9; + activation_out_data_available11 <= activation_out_data_available10; + activation_out_data_available12 <= activation_out_data_available11; + activation_out_data_available13 <= activation_out_data_available12; + activation_out_data_available14 <= activation_out_data_available13; + activation_out_data_available15 <= activation_out_data_available14; +end +`endif + +`ifdef DESIGN_SIZE_32 +always @(posedge clk) begin + activation_out_data_available8 <= activation_out_data_available7; + activation_out_data_available9 <= activation_out_data_available8; + activation_out_data_available10 <= activation_out_data_available9; + activation_out_data_available11 <= activation_out_data_available10; + activation_out_data_available12 <= activation_out_data_available11; + activation_out_data_available13 <= activation_out_data_available12; + activation_out_data_available14 <= activation_out_data_available13; + activation_out_data_available15 <= activation_out_data_available14; + activation_out_data_available16 <= activation_out_data_available15; + activation_out_data_available17 <= activation_out_data_available16; + activation_out_data_available18 <= activation_out_data_available17; + activation_out_data_available19 <= activation_out_data_available18; + activation_out_data_available20 <= activation_out_data_available19; + activation_out_data_available21 <= activation_out_data_available20; + activation_out_data_available22 <= activation_out_data_available21; + activation_out_data_available23 <= activation_out_data_available22; + activation_out_data_available24 <= activation_out_data_available23; + activation_out_data_available25 <= activation_out_data_available24; + activation_out_data_available26 <= activation_out_data_available25; + activation_out_data_available27 <= activation_out_data_available26; + activation_out_data_available28 <= activation_out_data_available27; + activation_out_data_available29 <= activation_out_data_available28; + activation_out_data_available30 <= activation_out_data_available29; + activation_out_data_available31 <= activation_out_data_available30; +end +`endif + +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data0; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data1; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data2; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data3; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data4; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data5; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data6; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data7; + +`ifdef DESIGN_SIZE_16 +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data8; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data9; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data10; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data11; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data12; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data13; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data14; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data15; +`endif + +`ifdef DESIGN_SIZE_32 +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data8; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data9; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data10; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data11; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data12; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data13; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data14; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data15; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data16; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data17; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data18; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data19; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data20; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data21; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data22; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data23; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data24; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data25; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data26; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data27; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data28; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data29; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data30; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data31; +`endif + +always @(posedge clk) begin + if (reset) begin + final_data0 <= 0; + end + else if (activation_out_data_available) begin + final_data0 <= {act_data_out0[7:0],final_data0[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data1 <= 0; + end + else if (activation_out_data_available1) begin + final_data1 <= {act_data_out1[7:0],final_data1[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data2 <= 0; + end + else if (activation_out_data_available2) begin + final_data2 <= {act_data_out2[7:0],final_data2[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data3 <= 0; + end + else if (activation_out_data_available3) begin + final_data3 <= {act_data_out3[7:0],final_data3[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data4 <= 0; + end + else if (activation_out_data_available4) begin + final_data4 <= {act_data_out4[7:0],final_data4[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data5 <= 0; + end + else if (activation_out_data_available5) begin + final_data5 <= {act_data_out5[7:0],final_data5[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data6 <= 0; + end + else if (activation_out_data_available6) begin + final_data6 <= {act_data_out6[7:0],final_data6[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data7 <= 0; + end + else if (activation_out_data_available7) begin + final_data7 <= {act_data_out7[7:0],final_data7[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +`ifdef DESIGN_SIZE_16 +always @(posedge clk) begin + if (reset) begin + final_data8 <= 0; + end + else if (activation_out_data_available8) begin + final_data8 <= {act_data_out8[7:0],final_data8[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data9 <= 0; + end + else if (activation_out_data_available9) begin + final_data9 <= {act_data_out9[7:0],final_data9[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data10 <= 0; + end + else if (activation_out_data_available10) begin + final_data10 <= {act_data_out10[7:0],final_data10[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data11 <= 0; + end + else if (activation_out_data_available11) begin + final_data11 <= {act_data_out11[7:0],final_data11[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data12 <= 0; + end + else if (activation_out_data_available12) begin + final_data12 <= {act_data_out12[7:0],final_data12[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data13 <= 0; + end + else if (activation_out_data_available13) begin + final_data13 <= {act_data_out13[7:0],final_data13[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data14 <= 0; + end + else if (activation_out_data_available14) begin + final_data14 <= {act_data_out14[7:0],final_data14[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data15 <= 0; + end + else if (activation_out_data_available15) begin + final_data15 <= {act_data_out15[7:0],final_data15[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end +`endif + +`ifdef DESIGN_SIZE_32 +always @(posedge clk) begin + if (reset) begin + final_data8 <= 0; + end + else if (activation_out_data_available8) begin + final_data8 <= {act_data_out8[7:0],final_data8[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data9 <= 0; + end + else if (activation_out_data_available9) begin + final_data9 <= {act_data_out9[7:0],final_data9[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data10 <= 0; + end + else if (activation_out_data_available10) begin + final_data10 <= {act_data_out10[7:0],final_data10[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data11 <= 0; + end + else if (activation_out_data_available11) begin + final_data11 <= {act_data_out11[7:0],final_data11[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data12 <= 0; + end + else if (activation_out_data_available12) begin + final_data12 <= {act_data_out12[7:0],final_data12[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data13 <= 0; + end + else if (activation_out_data_available13) begin + final_data13 <= {act_data_out13[7:0],final_data13[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data14 <= 0; + end + else if (activation_out_data_available14) begin + final_data14 <= {act_data_out14[7:0],final_data14[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data15 <= 0; + end + else if (activation_out_data_available15) begin + final_data15 <= {act_data_out15[7:0],final_data15[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data16 <= 0; + end + else if (activation_out_data_available16) begin + final_data16 <= {act_data_out16[7:0],final_data16[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data17 <= 0; + end + else if (activation_out_data_available17) begin + final_data17 <= {act_data_out17[7:0],final_data17[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data18 <= 0; + end + else if (activation_out_data_available18) begin + final_data18 <= {act_data_out18[7:0],final_data18[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data19 <= 0; + end + else if (activation_out_data_available19) begin + final_data19 <= {act_data_out19[7:0],final_data19[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data20 <= 0; + end + else if (activation_out_data_available20) begin + final_data20 <= {act_data_out20[7:0],final_data20[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data21 <= 0; + end + else if (activation_out_data_available21) begin + final_data21 <= {act_data_out21[7:0],final_data21[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data22 <= 0; + end + else if (activation_out_data_available22) begin + final_data22 <= {act_data_out22[7:0],final_data22[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data23 <= 0; + end + else if (activation_out_data_available23) begin + final_data23 <= {act_data_out23[7:0],final_data23[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data24 <= 0; + end + else if (activation_out_data_available24) begin + final_data24 <= {act_data_out24[7:0],final_data24[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data25 <= 0; + end + else if (activation_out_data_available25) begin + final_data25 <= {act_data_out25[7:0],final_data25[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data26 <= 0; + end + else if (activation_out_data_available26) begin + final_data26 <= {act_data_out26[7:0],final_data26[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data27 <= 0; + end + else if (activation_out_data_available27) begin + final_data27 <= {act_data_out27[7:0],final_data27[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data28 <= 0; + end + else if (activation_out_data_available28) begin + final_data28 <= {act_data_out28[7:0],final_data28[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data29 <= 0; + end + else if (activation_out_data_available29) begin + final_data29 <= {act_data_out29[7:0],final_data29[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data30 <= 0; + end + else if (activation_out_data_available30) begin + final_data30 <= {act_data_out30[7:0],final_data30[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data31 <= 0; + end + else if (activation_out_data_available31) begin + final_data31 <= {act_data_out31[7:0],final_data31[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end +`endif + +reg [31:0] i; + always @(posedge clk) begin + if (reset) begin + i <= 0; + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end + else if (done_activation) begin + i <= i + 1; + case(i) + `ifdef DESIGN_SIZE_8 + 0: begin bram_wdata_a <= final_data0; end + 1: begin bram_wdata_a <= final_data1; end + 2: begin bram_wdata_a <= final_data2; end + 3: begin bram_wdata_a <= final_data3; end + 4: begin bram_wdata_a <= final_data4; end + 5: begin bram_wdata_a <= final_data5; end + 6: begin bram_wdata_a <= final_data6; end + 7: begin bram_wdata_a <= final_data7; end + default : begin bram_wdata_a <= final_data7; end + `endif + `ifdef DESIGN_SIZE_16 + 0: begin bram_wdata_a <= final_data0; end + 1: begin bram_wdata_a <= final_data1; end + 2: begin bram_wdata_a <= final_data2; end + 3: begin bram_wdata_a <= final_data3; end + 4: begin bram_wdata_a <= final_data4; end + 5: begin bram_wdata_a <= final_data5; end + 6: begin bram_wdata_a <= final_data6; end + 7: begin bram_wdata_a <= final_data7; end + 8: begin bram_wdata_a <= final_data8; end + 9: begin bram_wdata_a <= final_data9; end + 10: begin bram_wdata_a <= final_data10; end + 11: begin bram_wdata_a <= final_data11; end + 12: begin bram_wdata_a <= final_data12; end + 13: begin bram_wdata_a <= final_data13; end + 14: begin bram_wdata_a <= final_data14; end + 15: begin bram_wdata_a <= final_data15; end + default : begin bram_wdata_a <= final_data15; end + `endif + `ifdef DESIGN_SIZE_32 + 0: begin bram_wdata_a <= final_data0; end + 1: begin bram_wdata_a <= final_data1; end + 2: begin bram_wdata_a <= final_data2; end + 3: begin bram_wdata_a <= final_data3; end + 4: begin bram_wdata_a <= final_data4; end + 5: begin bram_wdata_a <= final_data5; end + 6: begin bram_wdata_a <= final_data6; end + 7: begin bram_wdata_a <= final_data7; end + 8: begin bram_wdata_a <= final_data8; end + 9: begin bram_wdata_a <= final_data9; end + 10: begin bram_wdata_a <= final_data10; end + 11: begin bram_wdata_a <= final_data11; end + 12: begin bram_wdata_a <= final_data12; end + 13: begin bram_wdata_a <= final_data13; end + 14: begin bram_wdata_a <= final_data14; end + 15: begin bram_wdata_a <= final_data15; end + 16: begin bram_wdata_a <= final_data16; end + 17: begin bram_wdata_a <= final_data17; end + 18: begin bram_wdata_a <= final_data18; end + 19: begin bram_wdata_a <= final_data19; end + 20: begin bram_wdata_a <= final_data20; end + 21: begin bram_wdata_a <= final_data21; end + 22: begin bram_wdata_a <= final_data22; end + 23: begin bram_wdata_a <= final_data23; end + 24: begin bram_wdata_a <= final_data24; end + 25: begin bram_wdata_a <= final_data25; end + 26: begin bram_wdata_a <= final_data26; end + 27: begin bram_wdata_a <= final_data27; end + 28: begin bram_wdata_a <= final_data28; end + 29: begin bram_wdata_a <= final_data29; end + 30: begin bram_wdata_a <= final_data30; end + 31: begin bram_wdata_a <= final_data31; end + default : begin bram_wdata_a <= final_data31; end + `endif + endcase + bram_addr_a_for_writing <= bram_addr_a_for_writing - address_stride_c; + bram_a_wdata_available <= done_activation; + end + else begin + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end + end + + +endmodule + + diff --git a/designs/koios/tpu_like.large.ws/tpu_random.sv b/designs/koios/tpu_like.large.ws/tpu_random.sv new file mode 100644 index 000000000..7b18d166d --- /dev/null +++ b/designs/koios/tpu_like.large.ws/tpu_random.sv @@ -0,0 +1,171 @@ +/* +Random I/Os for tpu.ws +*/ + +`include "../../random_number_generator.sv" + +`define VCS +`define MATMUL_SIZE_32 +`define MORE_TESTS +`define DESIGN_SIZE_32 +`define SIMULATION +`define layer_test + +`define DWIDTH 8 +`define AWIDTH 11 +`define MEM_SIZE 2048 + +`ifdef MATMUL_SIZE_4 +`define MAT_MUL_SIZE 4 +`define MASK_WIDTH 4 +`define LOG2_MAT_MUL_SIZE 2 +`endif + +`ifdef MATMUL_SIZE_8 +`define MAT_MUL_SIZE 8 +`define MASK_WIDTH 8 +`define LOG2_MAT_MUL_SIZE 3 +`endif + +`ifdef MATMUL_SIZE_16 +`define MAT_MUL_SIZE 16 +`define MASK_WIDTH 16 +`define LOG2_MAT_MUL_SIZE 4 +`endif + +`ifdef MATMUL_SIZE_32 +`define MAT_MUL_SIZE 32 +`define MASK_WIDTH 32 +`define LOG2_MAT_MUL_SIZE 5 +`endif + +`ifdef DESIGN_SIZE_4 +`define DESIGN_SIZE 4 +`define LOG2_DESIGN_SIZE 2 +`endif + +`ifdef DESIGN_SIZE_8 +`define DESIGN_SIZE 8 +`define LOG2_DESIGN_SIZE 3 +`endif + +`ifdef DESIGN_SIZE_16 +`define DESIGN_SIZE 16 +`define LOG2_DESIGN_SIZE 4 +`endif + +`ifdef DESIGN_SIZE_32 +`define DESIGN_SIZE 32 +`define LOG2_DESIGN_SIZE 5 +`endif + +`define BB_MAT_MUL_SIZE `MAT_MUL_SIZE +`define NUM_CYCLES_IN_MAC 3 +`define MEM_ACCESS_LATENCY 1 +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 +`define ADDR_STRIDE_WIDTH 8 +`define MAX_BITS_POOL 3 + +module tpu_random ( + input wire logicclk, + input wire logicclk_mem, + input wire logicreset, + input wire logicresetn, + input wire logic[`REG_ADDRWIDTH-1:0] PADDR, + input wire logicPWRITE, + input wire logicPSEL, + input wire logicPENABLE, + input wire logic[`REG_DATAWIDTH-1:0] PWDATA, + output logic[`REG_DATAWIDTH-1:0] PRDATA, + output logicPREADY, + input wire logic[`AWIDTH-1:0] bram_addr_a_ext, + input wire logic[`DESIGN_SIZE-1:0] bram_we_a_ext, + input wire logic[`AWIDTH-1:0] bram_addr_b_ext, + input wire logic[`DESIGN_SIZE-1:0] bram_we_b_ext, + input wire logic[5:0] out_sel, + output logic [7:0] out +); + +logic[`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata[1:0]; +always_comb begin + case(out_sel[5:1]) + 5'd0: out = bram_rdata[out_sel[0]][7:0]; + 5'd1: out = bram_rdata[out_sel[0]][15:8]; + 5'd2: out = bram_rdata[out_sel[0]][23:16]; + 5'd3: out = bram_rdata[out_sel[0]][31:24]; + 5'd4: out = bram_rdata[out_sel[0]][39:32]; + 5'd5: out = bram_rdata[out_sel[0]][47:40]; + 5'd6: out = bram_rdata[out_sel[0]][55:48]; + 5'd7: out = bram_rdata[out_sel[0]][63:56]; + 5'd8: out = bram_rdata[out_sel[0]][71:64]; + 5'd9: out = bram_rdata[out_sel[0]][79:72]; + 5'd10: out = bram_rdata[out_sel[0]][87:80]; + 5'd11: out = bram_rdata[out_sel[0]][95:88]; + 5'd12: out = bram_rdata[out_sel[0]][103:96]; + 5'd13: out = bram_rdata[out_sel[0]][111:104]; + 5'd14: out = bram_rdata[out_sel[0]][119:112]; + 5'd15: out = bram_rdata[out_sel[0]][127:120]; + 5'd16: out = bram_rdata[out_sel[0]][135:128]; + 5'd17: out = bram_rdata[out_sel[0]][143:136]; + 5'd18: out = bram_rdata[out_sel[0]][151:144]; + 5'd19: out = bram_rdata[out_sel[0]][159:152]; + 5'd20: out = bram_rdata[out_sel[0]][167:160]; + 5'd21: out = bram_rdata[out_sel[0]][175:168]; + 5'd22: out = bram_rdata[out_sel[0]][183:176]; + 5'd23: out = bram_rdata[out_sel[0]][191:184]; + 5'd24: out = bram_rdata[out_sel[0]][199:192]; + 5'd25: out = bram_rdata[out_sel[0]][207:200]; + 5'd26: out = bram_rdata[out_sel[0]][215:208]; + 5'd27: out = bram_rdata[out_sel[0]][223:216]; + 5'd28: out = bram_rdata[out_sel[0]][231:224]; + 5'd29: out = bram_rdata[out_sel[0]][239:232]; + 5'd30: out = bram_rdata[out_sel[0]][247:240]; + 5'd31: out = bram_rdata[out_sel[0]][255:248]; + endcase +end + + +logic[`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a_ext; +logic[`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b_ext; +RandomNumberGenerator #( + .RANDOM_WIDTH(`DESIGN_SIZE*`DWIDTH), + .SEED(0) +) tpu0_random_number_generator ( + .clk(logicclk), + .reset(logicreset), + .random_number(bram_wdata_a_ext) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(`DESIGN_SIZE*`DWIDTH), + .SEED(1) +) tpu1_random_number_generator ( + .clk(logicclk), + .reset(logicreset), + .random_number(bram_wdata_b_ext) +); + +top tpu0( + clk, + clk_mem, + reset, + resetn, + PADDR, + PWRITE, + PSEL, + PENABLE, + PWDATA, + PRDATA, + PREADY, + bram_addr_a_ext, + bram_rdata[0], + bram_wdata_a_ext, + bram_we_a_ext, + bram_addr_b_ext, + bram_rdata[1], + bram_wdata_b_ext, + bram_we_b_ext +); + +endmodule \ No newline at end of file diff --git a/designs/koios/tpu_like.small.os/design.yaml b/designs/koios/tpu_like.small.os/design.yaml new file mode 100644 index 000000000..07777e95d --- /dev/null +++ b/designs/koios/tpu_like.small.os/design.yaml @@ -0,0 +1 @@ +top: tpu_random diff --git a/designs/koios/tpu_like.small.os/tpu_like.small.os.v b/designs/koios/tpu_like.small.os/tpu_like.small.os.v new file mode 100644 index 000000000..80f575f55 --- /dev/null +++ b/designs/koios/tpu_like.small.os/tpu_like.small.os.v @@ -0,0 +1,5961 @@ +////////////////////////////////////////////////////////////////////////////// +// Author: Aman Arora +////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +/////////////////////////////////// +// Overview +/////////////////////////////////// +//This design is based on the architecture from Google's TPU v1 [1]. At its heart, +//it uses a 16x16 matrix multiplication unit, instead of a 256x256 matrix multiplication +//unit used by the TPU. The design uses int8 precision. This systolic matrix multiplication +//unit is a output stationary unit, compared to weight stationary architecture used in the TPU. +//The activations are stored in RAM block A, whereas the weights are stored in RAM block B. +//Control and configuration are done through an APB interface, instead of a PCIe interface on +//the TPU. The normalization block applies the mean and variance values to the output of the +//matrix multiplication unit. Pooling unit supports 3 pooling windows - 1x1, 2x2 and 4x4. +//The activation unit supports two activation functions - rectified linear unit (ReLU) and +//the hyperbolic tangent (TanH). The activation unit is the last unit before the results +//are written back to RAM block A, from where they can be read again into the matrix +//multiplication unit for the next layer. +// +//[1] Jouppi et. al., In-Datacenter Performance Analysis of a Tensor Processing Unit, ISCA 2017 + +////////////////////////////////////// +// Module hierarchy +////////////////////////////////////// +// top (the top level design) +// |--- ram matrix_A (the RAM that stores matrix A (activations)) +// |--- ram matrix_B (the RAM that stores matrix B (weights)) +// |--- control u_control (the state machine that controls the operation) +// |--- cfg u_cfg (unit to configure/observe registers using an APB interface) +// |--- matmul_16x16_systolic u_matmul (systolic 16x16 matrix multiplication unit) +// | |--- output_logic (contains logic to shift out the outputs of matmul) +// | |--- systolic_data_setup (contains logic to shift in the inputs of the matmul) +// | |--- systolic_pe_matrix (16x16 matrix of processing elements) +// | |--- processing_element (one processing element) +// | |--- seq_mac (mac block inside each processing element) +// | |--- qmult (multiplier inside each mac) +// | |--- qadd (adder inside each mac) +// |--- norm u_norm (normalization block; applies mean and variance) +// |--- pool u_pool (block that performs pooling) +// |--- activation u_activation(block that applies activation - relu or tanh) + +////////////////////////////////////// +// Tested architectures +////////////////////////////////////// +// This design has been tested with: +// 1. The VTR flagship 40nm architecture. Example: arch/timing/k6_frac_N10_frac_chain_mem32K_40nm.xml +// Properties of this design on this architecture: +// Critical path delay: 8.32 ns +// Clock frequency: 120.19 MHz +// Critical path: Includes the multiplier in the MAC in a PE and inter-CLB routing +// Logic area (used): 1.97532e+08 MWTAs +// Resource usage: 1556 LBs, 8 RAMs, 276 Multipliers +// Runtime (on Intel Xeon E5-2430 2.5GHz with single thread): 3200 sec +// 2. 22nm architectures generated from COFFE. Example: arch/COFFE_22nm/stratix10_arch.xml +// Properties of this design on this architecture: +// Critical path delay: 9.24 ns +// Clock frequency: 108.17 MHz +// Critical path: Includes the multiplier in the MAC in a PE and inter-CLB routing +// Logic area (used): 4.95598e+07 MWTAs +// Resource usage: 1477 LBs, 14 RAMs, 280 Multipliers +// Runtime (on Intel Xeon E5-2430 2.5GHz with single thread): 3400 sec +// 3. 22nm architectures generated from COFFE. Example: arch/COFFE_22nm/k6n10LB_mem20K_complexDSP_customSB_22nm* + +////////////////////////////////////// +// Parameters +////////////////////////////////////// + +//The width of the data. This design uses int8 precision. So, DWIDTH is 8 +//To change to a floating point 16 version, change this to 16 and also +//change the datapath components (like adder and multiplier) to be floating point. +`define DWIDTH 8 + +//This is the size of the matrix multiplier unit. In this design, we have a systolic +//matrix multiplication unit that can multiply 16x16 matrix with a 16x16 matrix. +`define DESIGN_SIZE 16 +`define LOG2_DESIGN_SIZE 5 +`define MAT_MUL_SIZE 16 +`define MASK_WIDTH 16 +`define LOG2_MAT_MUL_SIZE 5 + +//This it the size of the address bus, or the depth of the RAM. Each location of +//the RAM is DWIDTH * MAT_MUL_SIZE wide. So, in this design, we use a total of +//1024 * 16 bytes of memory (i.e. 16 KB). +`define AWIDTH 10 + +//This is the number of clock cycles spent in the mac block +`define NUM_CYCLES_IN_MAC 3 + +//This defines the latency of accessing data from a block ram +`define MEM_ACCESS_LATENCY 1 + +//Data width and address width of the APB interface for registers +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 + +//Width of the stride for each column in the matrices (same as ram address width) +`define ADDR_STRIDE_WIDTH 16 + +//Number of bits to specify the pooling window. We support 3 sizes. +`define MAX_BITS_POOL 3 + +///////////////////////////////////////////////// +// Register specification +///////////////////////////////////////////////// + +//--------------------------------------- +//Addr 0 : Register with enables for various blocks. +//Includes mode of operation (convolution or fully_connected) +//--------------------------------------- +`define REG_ENABLES_ADDR 32'h0 +//Bit 0: enable_matmul +//Bit 1: enable_norm +//Bit 2: enable_pool +//Bit 3: enable_activation +//Bit 31: enable_conv_mode + +//--------------------------------------- +//Addr 4: Register that triggers the whole TPU +//--------------------------------------- +`define REG_STDN_TPU_ADDR 32'h4 +//Bit 0: start_tpu +//Bit 31: done_tpu + +//--------------------------------------- +//Addr 8: Register that stores the mean of the values +//--------------------------------------- +`define REG_MEAN_ADDR 32'h8 +//Bit 7:0: mean + +//--------------------------------------- +//Addr A: Register that stores the inverse variance of the values +//--------------------------------------- +`define REG_INV_VAR_ADDR 32'hA +//Bit 7:0: inv_var + +//--------------------------------------- +//Addr E: Register that stores the starting address of matrix A in BRAM A. +//In fully-connected mode, this register should be programmed with the +//address of the matrix being currently multiplied. That is, the +//address of the matrix of the matmul. So, this register will be +//programmed every time the matmul is kicked off during accumulation stages. +//Use the STRIDE registers to tell the matmul to increment addresses. +//In convolution mode, this register should be programmed with the +//address of the input activation matrix. No need to configure +//this every time the matmul is kicked off for accmulation. Just program it +//once it the beginning. Address increments are handled automatically . +//--------------------------------------- +`define REG_MATRIX_A_ADDR 32'he +//Bit `AWIDTH-1:0 address_mat_a + +//--------------------------------------- +//Addr 12: Register that stores the starting address of matrix B in BRAM B. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_B_ADDR 32'h12 +//Bit `AWIDTH-1:0 address_mat_b + +//--------------------------------------- +//Addr 16: Register that stores the starting address of matrix C in BRAM C. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_C_ADDR 32'h16 +//Bit `AWIDTH-1:0 address_mat_c + +//--------------------------------------- +//Addr 24: Register that controls the accumulation logic +//--------------------------------------- +`define REG_ACCUM_ACTIONS_ADDR 32'h24 +//Bit 0 save_output_to_accumulator +//Bit 1 add_accumulator_to_output + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 28: Register that stores the stride that should be taken to address +//elements in matrix A, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix A in the vertical +//direction. +//--------------------------------------- +`define REG_MATRIX_A_STRIDE_ADDR 32'h28 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_a + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 32: Register that stores the stride that should be taken to address +//elements in matrix B, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix B in the horizontal +//direction. +//--------------------------------------- +`define REG_MATRIX_B_STRIDE_ADDR 32'h32 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_b + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 36: Register that stores the stride that should be taken to address +//elements in matrix C, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix C in the vertical +//direction (this is generally same as address_stride_a). +//--------------------------------------- +`define REG_MATRIX_C_STRIDE_ADDR 32'h36 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_c + +//--------------------------------------- +//Addr 3A: Register that controls the activation block. Currently, the available +//settings are the selector of activation function that will be used. There are +//two options: ReLU and TanH. To use ReLU, clear the LSB of this register. To +//use TanH, set the LSB of this register. +//--------------------------------------- +`define REG_ACTIVATION_CSR_ADDR 32'h3A + +//--------------------------------------- +//Addr 3E: Register defining pooling window size +//--------------------------------------- +`define REG_POOL_WINDOW_ADDR 32'h3E +//Bit `MAX_BITS_POOL-1:0 pool window size + +//--------------------------------------- +//Addr 40: Register defining convolution parameters - 1 +//---------------------------------------- +`define REG_CONV_PARAMS_1_ADDR 32'h40 +//Bits filter_height (R) 3:0 +//Bits filter width (S) 7:4 +//Bits stride_horizontal 11:8 +//Bits stride_vertical 15:12 +//Bits pad_left 19:16 +//Bits pad_right 23:20 +//Bits pad_top 27:24 +//Bits pad_bottom 31:28 + +//--------------------------------------- +//Addr 44: Register defining convolution parameters - 2 +//---------------------------------------- +`define REG_CONV_PARAMS_2_ADDR 32'h44 +//Bits num_channels_input (C) 15:0 +//Bits num_channels_output (K) 31:16 + +//--------------------------------------- +//Addr 48: Register defining convolution parameters - 3 +//---------------------------------------- +`define REG_CONV_PARAMS_3_ADDR 32'h48 +//Bits input_image_height (H) 15:0 +//Bits input_image_width (W) 31:16 + +//--------------------------------------- +//Addr 4C: Register defining convolution parameters - 4 +//---------------------------------------- +`define REG_CONV_PARAMS_4_ADDR 32'h4C +//Bits output_image_height (P) 15:0 +//Bits output_image_width (Q) 31:16 + +//--------------------------------------- +//Addr 50: Register defining batch size +//---------------------------------------- +`define REG_BATCH_SIZE_ADDR 32'h50 +//Bits 31:0 batch_size (number of images, N) + +//--------------------------------------- +//Addresses 54,58,5C: Registers that stores the mask of which parts of the matrices are valid. +// +//Some examples where this is useful: +//1. Input matrix is smaller than the matmul. +// Say we want to multiply a 6x6 using an 8x8 matmul. +// The matmul still operates on the whole 8x8 part, so we need +// to ensure that there are 0s in the BRAMs in the invalid parts. +// But the mask is used by the blocks other than matmul. For ex, +// norm block will use the mask to avoid applying mean and variance +// to invalid parts (so tha they stay 0). +//2. When we start with large matrices, the size of the matrices can +// reduce to something less than the matmul size because of pooling. +// In that case for the next layer, we need to tell blocks like norm, +// what is valid and what is not. +// +//Note: This masks is applied to both x and y directions and also +//applied to both input matrices - A and B. +//--------------------------------------- +`define REG_VALID_MASK_A_ROWS_ADDR 32'h20 +`define REG_VALID_MASK_A_COLS_ADDR 32'h54 +`define REG_VALID_MASK_B_ROWS_ADDR 32'h5c +`define REG_VALID_MASK_B_COLS_ADDR 32'h58 +//Bit `MASK_WIDTH-1:0 validity_mask + +//This used to be a normal signal, but changing it to a `define. +//That's because it's not required to be a variable in this design. +//And ODIN doesn't seem to propagate constants properly. +`define final_mat_mul_size 16 + +///////////////////////////////////// +// Matrix multiplication unit +//////////////////////////////////// + +module matmul_16x16_systolic( + clk, + reset, + pe_reset, + start_mat_mul, + done_mat_mul, + address_mat_a, + address_mat_b, + address_mat_c, + address_stride_a, + address_stride_b, + address_stride_c, + a_data, + b_data, + a_data_in, //Data values coming in from previous matmul - systolic connections + b_data_in, + c_data_in, //Data values coming in from previous matmul - systolic shifting + c_data_out, //Data values going out to next matmul - systolic shifting + a_data_out, + b_data_out, + a_addr, + b_addr, + c_addr, + c_data_available, + + validity_mask_a_rows, + validity_mask_a_cols, + validity_mask_b_rows, + validity_mask_b_cols, + + final_mat_mul_size, + + a_loc, + b_loc +); + + input clk; + input reset; + input pe_reset; + input start_mat_mul; + output done_mat_mul; + input [`AWIDTH-1:0] address_mat_a; + input [`AWIDTH-1:0] address_mat_b; + input [`AWIDTH-1:0] address_mat_c; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + output [`AWIDTH-1:0] a_addr; + output [`AWIDTH-1:0] b_addr; + output [`AWIDTH-1:0] c_addr; + output c_data_available; + + input [`MASK_WIDTH-1:0] validity_mask_a_rows; + input [`MASK_WIDTH-1:0] validity_mask_a_cols; + input [`MASK_WIDTH-1:0] validity_mask_b_rows; + input [`MASK_WIDTH-1:0] validity_mask_b_cols; + +//7:0 is okay here. We aren't going to make a matmul larger than 128x128 +//In fact, these will get optimized out by the synthesis tool, because +//we hardcode them at the instantiation level. + input [7:0] final_mat_mul_size; + + input [7:0] a_loc; + input [7:0] b_loc; + +////////////////////////////////////////////////////////////////////////// +// Logic for clock counting and when to assert done +////////////////////////////////////////////////////////////////////////// + +reg done_mat_mul; +//This is 7 bits because the expectation is that clock count will be pretty +//small. For large matmuls, this will need to increased to have more bits. +//In general, a systolic multiplier takes 4*N-2+P cycles, where N is the size +//of the matmul and P is the number of pipleine stages in the MAC block. +reg [7:0] clk_cnt; + +//Finding out number of cycles to assert matmul done. +//When we have to save the outputs to accumulators, then we don't need to +//shift out data. So, we can assert done_mat_mul early. +//In the normal case, we have to include the time to shift out the results. +//Note: the count expression used to contain "4*final_mat_mul_size", but +//to avoid multiplication, we now use "final_mat_mul_size<<2" +wire [7:0] clk_cnt_for_done; + +assign clk_cnt_for_done = + ((`final_mat_mul_size<<2) - 2 + `NUM_CYCLES_IN_MAC); + +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + clk_cnt <= 0; + done_mat_mul <= 0; + end + else if (clk_cnt == clk_cnt_for_done) begin + done_mat_mul <= 1; + clk_cnt <= clk_cnt + 1; + + end + else if (done_mat_mul == 0) begin + clk_cnt <= clk_cnt + 1; + + end + else begin + done_mat_mul <= 0; + clk_cnt <= clk_cnt + 1; + end +end +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; +wire [`DWIDTH-1:0] a1_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_1; +wire [`DWIDTH-1:0] a3_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_1; +wire [`DWIDTH-1:0] a4_data_delayed_2; +wire [`DWIDTH-1:0] a4_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_1; +wire [`DWIDTH-1:0] a5_data_delayed_2; +wire [`DWIDTH-1:0] a5_data_delayed_3; +wire [`DWIDTH-1:0] a5_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_1; +wire [`DWIDTH-1:0] a6_data_delayed_2; +wire [`DWIDTH-1:0] a6_data_delayed_3; +wire [`DWIDTH-1:0] a6_data_delayed_4; +wire [`DWIDTH-1:0] a6_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_1; +wire [`DWIDTH-1:0] a7_data_delayed_2; +wire [`DWIDTH-1:0] a7_data_delayed_3; +wire [`DWIDTH-1:0] a7_data_delayed_4; +wire [`DWIDTH-1:0] a7_data_delayed_5; +wire [`DWIDTH-1:0] a7_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_1; +wire [`DWIDTH-1:0] a8_data_delayed_2; +wire [`DWIDTH-1:0] a8_data_delayed_3; +wire [`DWIDTH-1:0] a8_data_delayed_4; +wire [`DWIDTH-1:0] a8_data_delayed_5; +wire [`DWIDTH-1:0] a8_data_delayed_6; +wire [`DWIDTH-1:0] a8_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_1; +wire [`DWIDTH-1:0] a9_data_delayed_2; +wire [`DWIDTH-1:0] a9_data_delayed_3; +wire [`DWIDTH-1:0] a9_data_delayed_4; +wire [`DWIDTH-1:0] a9_data_delayed_5; +wire [`DWIDTH-1:0] a9_data_delayed_6; +wire [`DWIDTH-1:0] a9_data_delayed_7; +wire [`DWIDTH-1:0] a9_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_1; +wire [`DWIDTH-1:0] a10_data_delayed_2; +wire [`DWIDTH-1:0] a10_data_delayed_3; +wire [`DWIDTH-1:0] a10_data_delayed_4; +wire [`DWIDTH-1:0] a10_data_delayed_5; +wire [`DWIDTH-1:0] a10_data_delayed_6; +wire [`DWIDTH-1:0] a10_data_delayed_7; +wire [`DWIDTH-1:0] a10_data_delayed_8; +wire [`DWIDTH-1:0] a10_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_1; +wire [`DWIDTH-1:0] a11_data_delayed_2; +wire [`DWIDTH-1:0] a11_data_delayed_3; +wire [`DWIDTH-1:0] a11_data_delayed_4; +wire [`DWIDTH-1:0] a11_data_delayed_5; +wire [`DWIDTH-1:0] a11_data_delayed_6; +wire [`DWIDTH-1:0] a11_data_delayed_7; +wire [`DWIDTH-1:0] a11_data_delayed_8; +wire [`DWIDTH-1:0] a11_data_delayed_9; +wire [`DWIDTH-1:0] a11_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_1; +wire [`DWIDTH-1:0] a12_data_delayed_2; +wire [`DWIDTH-1:0] a12_data_delayed_3; +wire [`DWIDTH-1:0] a12_data_delayed_4; +wire [`DWIDTH-1:0] a12_data_delayed_5; +wire [`DWIDTH-1:0] a12_data_delayed_6; +wire [`DWIDTH-1:0] a12_data_delayed_7; +wire [`DWIDTH-1:0] a12_data_delayed_8; +wire [`DWIDTH-1:0] a12_data_delayed_9; +wire [`DWIDTH-1:0] a12_data_delayed_10; +wire [`DWIDTH-1:0] a12_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_1; +wire [`DWIDTH-1:0] a13_data_delayed_2; +wire [`DWIDTH-1:0] a13_data_delayed_3; +wire [`DWIDTH-1:0] a13_data_delayed_4; +wire [`DWIDTH-1:0] a13_data_delayed_5; +wire [`DWIDTH-1:0] a13_data_delayed_6; +wire [`DWIDTH-1:0] a13_data_delayed_7; +wire [`DWIDTH-1:0] a13_data_delayed_8; +wire [`DWIDTH-1:0] a13_data_delayed_9; +wire [`DWIDTH-1:0] a13_data_delayed_10; +wire [`DWIDTH-1:0] a13_data_delayed_11; +wire [`DWIDTH-1:0] a13_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_1; +wire [`DWIDTH-1:0] a14_data_delayed_2; +wire [`DWIDTH-1:0] a14_data_delayed_3; +wire [`DWIDTH-1:0] a14_data_delayed_4; +wire [`DWIDTH-1:0] a14_data_delayed_5; +wire [`DWIDTH-1:0] a14_data_delayed_6; +wire [`DWIDTH-1:0] a14_data_delayed_7; +wire [`DWIDTH-1:0] a14_data_delayed_8; +wire [`DWIDTH-1:0] a14_data_delayed_9; +wire [`DWIDTH-1:0] a14_data_delayed_10; +wire [`DWIDTH-1:0] a14_data_delayed_11; +wire [`DWIDTH-1:0] a14_data_delayed_12; +wire [`DWIDTH-1:0] a14_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_1; +wire [`DWIDTH-1:0] a15_data_delayed_2; +wire [`DWIDTH-1:0] a15_data_delayed_3; +wire [`DWIDTH-1:0] a15_data_delayed_4; +wire [`DWIDTH-1:0] a15_data_delayed_5; +wire [`DWIDTH-1:0] a15_data_delayed_6; +wire [`DWIDTH-1:0] a15_data_delayed_7; +wire [`DWIDTH-1:0] a15_data_delayed_8; +wire [`DWIDTH-1:0] a15_data_delayed_9; +wire [`DWIDTH-1:0] a15_data_delayed_10; +wire [`DWIDTH-1:0] a15_data_delayed_11; +wire [`DWIDTH-1:0] a15_data_delayed_12; +wire [`DWIDTH-1:0] a15_data_delayed_13; +wire [`DWIDTH-1:0] a15_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_15; +wire [`DWIDTH-1:0] b1_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_1; +wire [`DWIDTH-1:0] b3_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_3; +wire [`DWIDTH-1:0] b4_data_delayed_1; +wire [`DWIDTH-1:0] b4_data_delayed_2; +wire [`DWIDTH-1:0] b4_data_delayed_3; +wire [`DWIDTH-1:0] b4_data_delayed_4; +wire [`DWIDTH-1:0] b5_data_delayed_1; +wire [`DWIDTH-1:0] b5_data_delayed_2; +wire [`DWIDTH-1:0] b5_data_delayed_3; +wire [`DWIDTH-1:0] b5_data_delayed_4; +wire [`DWIDTH-1:0] b5_data_delayed_5; +wire [`DWIDTH-1:0] b6_data_delayed_1; +wire [`DWIDTH-1:0] b6_data_delayed_2; +wire [`DWIDTH-1:0] b6_data_delayed_3; +wire [`DWIDTH-1:0] b6_data_delayed_4; +wire [`DWIDTH-1:0] b6_data_delayed_5; +wire [`DWIDTH-1:0] b6_data_delayed_6; +wire [`DWIDTH-1:0] b7_data_delayed_1; +wire [`DWIDTH-1:0] b7_data_delayed_2; +wire [`DWIDTH-1:0] b7_data_delayed_3; +wire [`DWIDTH-1:0] b7_data_delayed_4; +wire [`DWIDTH-1:0] b7_data_delayed_5; +wire [`DWIDTH-1:0] b7_data_delayed_6; +wire [`DWIDTH-1:0] b7_data_delayed_7; +wire [`DWIDTH-1:0] b8_data_delayed_1; +wire [`DWIDTH-1:0] b8_data_delayed_2; +wire [`DWIDTH-1:0] b8_data_delayed_3; +wire [`DWIDTH-1:0] b8_data_delayed_4; +wire [`DWIDTH-1:0] b8_data_delayed_5; +wire [`DWIDTH-1:0] b8_data_delayed_6; +wire [`DWIDTH-1:0] b8_data_delayed_7; +wire [`DWIDTH-1:0] b8_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_1; +wire [`DWIDTH-1:0] b9_data_delayed_2; +wire [`DWIDTH-1:0] b9_data_delayed_3; +wire [`DWIDTH-1:0] b9_data_delayed_4; +wire [`DWIDTH-1:0] b9_data_delayed_5; +wire [`DWIDTH-1:0] b9_data_delayed_6; +wire [`DWIDTH-1:0] b9_data_delayed_7; +wire [`DWIDTH-1:0] b9_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_1; +wire [`DWIDTH-1:0] b10_data_delayed_2; +wire [`DWIDTH-1:0] b10_data_delayed_3; +wire [`DWIDTH-1:0] b10_data_delayed_4; +wire [`DWIDTH-1:0] b10_data_delayed_5; +wire [`DWIDTH-1:0] b10_data_delayed_6; +wire [`DWIDTH-1:0] b10_data_delayed_7; +wire [`DWIDTH-1:0] b10_data_delayed_8; +wire [`DWIDTH-1:0] b10_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_1; +wire [`DWIDTH-1:0] b11_data_delayed_2; +wire [`DWIDTH-1:0] b11_data_delayed_3; +wire [`DWIDTH-1:0] b11_data_delayed_4; +wire [`DWIDTH-1:0] b11_data_delayed_5; +wire [`DWIDTH-1:0] b11_data_delayed_6; +wire [`DWIDTH-1:0] b11_data_delayed_7; +wire [`DWIDTH-1:0] b11_data_delayed_8; +wire [`DWIDTH-1:0] b11_data_delayed_9; +wire [`DWIDTH-1:0] b11_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_1; +wire [`DWIDTH-1:0] b12_data_delayed_2; +wire [`DWIDTH-1:0] b12_data_delayed_3; +wire [`DWIDTH-1:0] b12_data_delayed_4; +wire [`DWIDTH-1:0] b12_data_delayed_5; +wire [`DWIDTH-1:0] b12_data_delayed_6; +wire [`DWIDTH-1:0] b12_data_delayed_7; +wire [`DWIDTH-1:0] b12_data_delayed_8; +wire [`DWIDTH-1:0] b12_data_delayed_9; +wire [`DWIDTH-1:0] b12_data_delayed_10; +wire [`DWIDTH-1:0] b12_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_1; +wire [`DWIDTH-1:0] b13_data_delayed_2; +wire [`DWIDTH-1:0] b13_data_delayed_3; +wire [`DWIDTH-1:0] b13_data_delayed_4; +wire [`DWIDTH-1:0] b13_data_delayed_5; +wire [`DWIDTH-1:0] b13_data_delayed_6; +wire [`DWIDTH-1:0] b13_data_delayed_7; +wire [`DWIDTH-1:0] b13_data_delayed_8; +wire [`DWIDTH-1:0] b13_data_delayed_9; +wire [`DWIDTH-1:0] b13_data_delayed_10; +wire [`DWIDTH-1:0] b13_data_delayed_11; +wire [`DWIDTH-1:0] b13_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_1; +wire [`DWIDTH-1:0] b14_data_delayed_2; +wire [`DWIDTH-1:0] b14_data_delayed_3; +wire [`DWIDTH-1:0] b14_data_delayed_4; +wire [`DWIDTH-1:0] b14_data_delayed_5; +wire [`DWIDTH-1:0] b14_data_delayed_6; +wire [`DWIDTH-1:0] b14_data_delayed_7; +wire [`DWIDTH-1:0] b14_data_delayed_8; +wire [`DWIDTH-1:0] b14_data_delayed_9; +wire [`DWIDTH-1:0] b14_data_delayed_10; +wire [`DWIDTH-1:0] b14_data_delayed_11; +wire [`DWIDTH-1:0] b14_data_delayed_12; +wire [`DWIDTH-1:0] b14_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_1; +wire [`DWIDTH-1:0] b15_data_delayed_2; +wire [`DWIDTH-1:0] b15_data_delayed_3; +wire [`DWIDTH-1:0] b15_data_delayed_4; +wire [`DWIDTH-1:0] b15_data_delayed_5; +wire [`DWIDTH-1:0] b15_data_delayed_6; +wire [`DWIDTH-1:0] b15_data_delayed_7; +wire [`DWIDTH-1:0] b15_data_delayed_8; +wire [`DWIDTH-1:0] b15_data_delayed_9; +wire [`DWIDTH-1:0] b15_data_delayed_10; +wire [`DWIDTH-1:0] b15_data_delayed_11; +wire [`DWIDTH-1:0] b15_data_delayed_12; +wire [`DWIDTH-1:0] b15_data_delayed_13; +wire [`DWIDTH-1:0] b15_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_15; + + +////////////////////////////////////////////////////////////////////////// +// Instantiation of systolic data setup +////////////////////////////////////////////////////////////////////////// +systolic_data_setup u_systolic_data_setup( +.clk(clk), +.reset(reset), +.start_mat_mul(start_mat_mul), +.a_addr(a_addr), +.b_addr(b_addr), +.address_mat_a(address_mat_a), +.address_mat_b(address_mat_b), +.address_stride_a(address_stride_a), +.address_stride_b(address_stride_b), +.a_data(a_data), +.b_data(b_data), +.clk_cnt(clk_cnt), +.a0_data(a0_data), +.b0_data(b0_data), +.a1_data_delayed_1(a1_data_delayed_1), +.b1_data_delayed_1(b1_data_delayed_1), +.a2_data_delayed_2(a2_data_delayed_2), +.b2_data_delayed_2(b2_data_delayed_2), +.a3_data_delayed_3(a3_data_delayed_3), +.b3_data_delayed_3(b3_data_delayed_3), +.a4_data_delayed_4(a4_data_delayed_4), +.b4_data_delayed_4(b4_data_delayed_4), +.a5_data_delayed_5(a5_data_delayed_5), +.b5_data_delayed_5(b5_data_delayed_5), +.a6_data_delayed_6(a6_data_delayed_6), +.b6_data_delayed_6(b6_data_delayed_6), +.a7_data_delayed_7(a7_data_delayed_7), +.b7_data_delayed_7(b7_data_delayed_7), +.a8_data_delayed_8(a8_data_delayed_8), +.b8_data_delayed_8(b8_data_delayed_8), +.a9_data_delayed_9(a9_data_delayed_9), +.b9_data_delayed_9(b9_data_delayed_9), +.a10_data_delayed_10(a10_data_delayed_10), +.b10_data_delayed_10(b10_data_delayed_10), +.a11_data_delayed_11(a11_data_delayed_11), +.b11_data_delayed_11(b11_data_delayed_11), +.a12_data_delayed_12(a12_data_delayed_12), +.b12_data_delayed_12(b12_data_delayed_12), +.a13_data_delayed_13(a13_data_delayed_13), +.b13_data_delayed_13(b13_data_delayed_13), +.a14_data_delayed_14(a14_data_delayed_14), +.b14_data_delayed_14(b14_data_delayed_14), +.a15_data_delayed_15(a15_data_delayed_15), +.b15_data_delayed_15(b15_data_delayed_15), + +.validity_mask_a_rows(validity_mask_a_rows), +.validity_mask_a_cols(validity_mask_a_cols), +.validity_mask_b_rows(validity_mask_b_rows), +.validity_mask_b_cols(validity_mask_b_cols), + +.final_mat_mul_size(final_mat_mul_size), + +.a_loc(a_loc), +.b_loc(b_loc) +); + +////////////////////////////////////////////////////////////////////////// +// Logic to mux data_in coming from neighboring matmuls +////////////////////////////////////////////////////////////////////////// +wire [`DWIDTH-1:0] a0; +wire [`DWIDTH-1:0] a1; +wire [`DWIDTH-1:0] a2; +wire [`DWIDTH-1:0] a3; +wire [`DWIDTH-1:0] a4; +wire [`DWIDTH-1:0] a5; +wire [`DWIDTH-1:0] a6; +wire [`DWIDTH-1:0] a7; +wire [`DWIDTH-1:0] a8; +wire [`DWIDTH-1:0] a9; +wire [`DWIDTH-1:0] a10; +wire [`DWIDTH-1:0] a11; +wire [`DWIDTH-1:0] a12; +wire [`DWIDTH-1:0] a13; +wire [`DWIDTH-1:0] a14; +wire [`DWIDTH-1:0] a15; +wire [`DWIDTH-1:0] b0; +wire [`DWIDTH-1:0] b1; +wire [`DWIDTH-1:0] b2; +wire [`DWIDTH-1:0] b3; +wire [`DWIDTH-1:0] b4; +wire [`DWIDTH-1:0] b5; +wire [`DWIDTH-1:0] b6; +wire [`DWIDTH-1:0] b7; +wire [`DWIDTH-1:0] b8; +wire [`DWIDTH-1:0] b9; +wire [`DWIDTH-1:0] b10; +wire [`DWIDTH-1:0] b11; +wire [`DWIDTH-1:0] b12; +wire [`DWIDTH-1:0] b13; +wire [`DWIDTH-1:0] b14; +wire [`DWIDTH-1:0] b15; + +wire [`DWIDTH-1:0] a0_data_in; +wire [`DWIDTH-1:0] a1_data_in; +wire [`DWIDTH-1:0] a2_data_in; +wire [`DWIDTH-1:0] a3_data_in; +wire [`DWIDTH-1:0] a4_data_in; +wire [`DWIDTH-1:0] a5_data_in; +wire [`DWIDTH-1:0] a6_data_in; +wire [`DWIDTH-1:0] a7_data_in; +wire [`DWIDTH-1:0] a8_data_in; +wire [`DWIDTH-1:0] a9_data_in; +wire [`DWIDTH-1:0] a10_data_in; +wire [`DWIDTH-1:0] a11_data_in; +wire [`DWIDTH-1:0] a12_data_in; +wire [`DWIDTH-1:0] a13_data_in; +wire [`DWIDTH-1:0] a14_data_in; +wire [`DWIDTH-1:0] a15_data_in; + +assign a0_data_in = a_data_in[1*`DWIDTH-1:0*`DWIDTH]; +assign a1_data_in = a_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign a2_data_in = a_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign a3_data_in = a_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign a4_data_in = a_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign a5_data_in = a_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign a6_data_in = a_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign a7_data_in = a_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign a8_data_in = a_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign a9_data_in = a_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign a10_data_in = a_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign a11_data_in = a_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign a12_data_in = a_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign a13_data_in = a_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign a14_data_in = a_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign a15_data_in = a_data_in[16*`DWIDTH-1:15*`DWIDTH]; + +wire [`DWIDTH-1:0] b0_data_in; +wire [`DWIDTH-1:0] b1_data_in; +wire [`DWIDTH-1:0] b2_data_in; +wire [`DWIDTH-1:0] b3_data_in; +wire [`DWIDTH-1:0] b4_data_in; +wire [`DWIDTH-1:0] b5_data_in; +wire [`DWIDTH-1:0] b6_data_in; +wire [`DWIDTH-1:0] b7_data_in; +wire [`DWIDTH-1:0] b8_data_in; +wire [`DWIDTH-1:0] b9_data_in; +wire [`DWIDTH-1:0] b10_data_in; +wire [`DWIDTH-1:0] b11_data_in; +wire [`DWIDTH-1:0] b12_data_in; +wire [`DWIDTH-1:0] b13_data_in; +wire [`DWIDTH-1:0] b14_data_in; +wire [`DWIDTH-1:0] b15_data_in; + +assign b0_data_in = b_data_in[1*`DWIDTH-1:0*`DWIDTH]; +assign b1_data_in = b_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign b2_data_in = b_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign b3_data_in = b_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign b4_data_in = b_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign b5_data_in = b_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign b6_data_in = b_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign b7_data_in = b_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign b8_data_in = b_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign b9_data_in = b_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign b10_data_in = b_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign b11_data_in = b_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign b12_data_in = b_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign b13_data_in = b_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign b14_data_in = b_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign b15_data_in = b_data_in[16*`DWIDTH-1:15*`DWIDTH]; + +assign a0 = (b_loc==0) ? a0_data : a0_data_in; +assign a1 = (b_loc==0) ? a1_data_delayed_1 : a1_data_in; +assign a2 = (b_loc==0) ? a2_data_delayed_2 : a2_data_in; +assign a3 = (b_loc==0) ? a3_data_delayed_3 : a3_data_in; +assign a4 = (b_loc==0) ? a4_data_delayed_4 : a4_data_in; +assign a5 = (b_loc==0) ? a5_data_delayed_5 : a5_data_in; +assign a6 = (b_loc==0) ? a6_data_delayed_6 : a6_data_in; +assign a7 = (b_loc==0) ? a7_data_delayed_7 : a7_data_in; +assign a8 = (b_loc==0) ? a8_data_delayed_8 : a8_data_in; +assign a9 = (b_loc==0) ? a9_data_delayed_9 : a9_data_in; +assign a10 = (b_loc==0) ? a10_data_delayed_10 : a10_data_in; +assign a11 = (b_loc==0) ? a11_data_delayed_11 : a11_data_in; +assign a12 = (b_loc==0) ? a12_data_delayed_12 : a12_data_in; +assign a13 = (b_loc==0) ? a13_data_delayed_13 : a13_data_in; +assign a14 = (b_loc==0) ? a14_data_delayed_14 : a14_data_in; +assign a15 = (b_loc==0) ? a15_data_delayed_15 : a15_data_in; + +assign b0 = (a_loc==0) ? b0_data : b0_data_in; +assign b1 = (a_loc==0) ? b1_data_delayed_1 : b1_data_in; +assign b2 = (a_loc==0) ? b2_data_delayed_2 : b2_data_in; +assign b3 = (a_loc==0) ? b3_data_delayed_3 : b3_data_in; +assign b4 = (a_loc==0) ? b4_data_delayed_4 : b4_data_in; +assign b5 = (a_loc==0) ? b5_data_delayed_5 : b5_data_in; +assign b6 = (a_loc==0) ? b6_data_delayed_6 : b6_data_in; +assign b7 = (a_loc==0) ? b7_data_delayed_7 : b7_data_in; +assign b8 = (a_loc==0) ? b8_data_delayed_8 : b8_data_in; +assign b9 = (a_loc==0) ? b9_data_delayed_9 : b9_data_in; +assign b10 = (a_loc==0) ? b10_data_delayed_10 : b10_data_in; +assign b11 = (a_loc==0) ? b11_data_delayed_11 : b11_data_in; +assign b12 = (a_loc==0) ? b12_data_delayed_12 : b12_data_in; +assign b13 = (a_loc==0) ? b13_data_delayed_13 : b13_data_in; +assign b14 = (a_loc==0) ? b14_data_delayed_14 : b14_data_in; +assign b15 = (a_loc==0) ? b15_data_delayed_15 : b15_data_in; + +wire [`DWIDTH-1:0] matrixC0_0; +wire [`DWIDTH-1:0] matrixC0_1; +wire [`DWIDTH-1:0] matrixC0_2; +wire [`DWIDTH-1:0] matrixC0_3; +wire [`DWIDTH-1:0] matrixC0_4; +wire [`DWIDTH-1:0] matrixC0_5; +wire [`DWIDTH-1:0] matrixC0_6; +wire [`DWIDTH-1:0] matrixC0_7; +wire [`DWIDTH-1:0] matrixC0_8; +wire [`DWIDTH-1:0] matrixC0_9; +wire [`DWIDTH-1:0] matrixC0_10; +wire [`DWIDTH-1:0] matrixC0_11; +wire [`DWIDTH-1:0] matrixC0_12; +wire [`DWIDTH-1:0] matrixC0_13; +wire [`DWIDTH-1:0] matrixC0_14; +wire [`DWIDTH-1:0] matrixC0_15; +wire [`DWIDTH-1:0] matrixC1_0; +wire [`DWIDTH-1:0] matrixC1_1; +wire [`DWIDTH-1:0] matrixC1_2; +wire [`DWIDTH-1:0] matrixC1_3; +wire [`DWIDTH-1:0] matrixC1_4; +wire [`DWIDTH-1:0] matrixC1_5; +wire [`DWIDTH-1:0] matrixC1_6; +wire [`DWIDTH-1:0] matrixC1_7; +wire [`DWIDTH-1:0] matrixC1_8; +wire [`DWIDTH-1:0] matrixC1_9; +wire [`DWIDTH-1:0] matrixC1_10; +wire [`DWIDTH-1:0] matrixC1_11; +wire [`DWIDTH-1:0] matrixC1_12; +wire [`DWIDTH-1:0] matrixC1_13; +wire [`DWIDTH-1:0] matrixC1_14; +wire [`DWIDTH-1:0] matrixC1_15; +wire [`DWIDTH-1:0] matrixC2_0; +wire [`DWIDTH-1:0] matrixC2_1; +wire [`DWIDTH-1:0] matrixC2_2; +wire [`DWIDTH-1:0] matrixC2_3; +wire [`DWIDTH-1:0] matrixC2_4; +wire [`DWIDTH-1:0] matrixC2_5; +wire [`DWIDTH-1:0] matrixC2_6; +wire [`DWIDTH-1:0] matrixC2_7; +wire [`DWIDTH-1:0] matrixC2_8; +wire [`DWIDTH-1:0] matrixC2_9; +wire [`DWIDTH-1:0] matrixC2_10; +wire [`DWIDTH-1:0] matrixC2_11; +wire [`DWIDTH-1:0] matrixC2_12; +wire [`DWIDTH-1:0] matrixC2_13; +wire [`DWIDTH-1:0] matrixC2_14; +wire [`DWIDTH-1:0] matrixC2_15; +wire [`DWIDTH-1:0] matrixC3_0; +wire [`DWIDTH-1:0] matrixC3_1; +wire [`DWIDTH-1:0] matrixC3_2; +wire [`DWIDTH-1:0] matrixC3_3; +wire [`DWIDTH-1:0] matrixC3_4; +wire [`DWIDTH-1:0] matrixC3_5; +wire [`DWIDTH-1:0] matrixC3_6; +wire [`DWIDTH-1:0] matrixC3_7; +wire [`DWIDTH-1:0] matrixC3_8; +wire [`DWIDTH-1:0] matrixC3_9; +wire [`DWIDTH-1:0] matrixC3_10; +wire [`DWIDTH-1:0] matrixC3_11; +wire [`DWIDTH-1:0] matrixC3_12; +wire [`DWIDTH-1:0] matrixC3_13; +wire [`DWIDTH-1:0] matrixC3_14; +wire [`DWIDTH-1:0] matrixC3_15; +wire [`DWIDTH-1:0] matrixC4_0; +wire [`DWIDTH-1:0] matrixC4_1; +wire [`DWIDTH-1:0] matrixC4_2; +wire [`DWIDTH-1:0] matrixC4_3; +wire [`DWIDTH-1:0] matrixC4_4; +wire [`DWIDTH-1:0] matrixC4_5; +wire [`DWIDTH-1:0] matrixC4_6; +wire [`DWIDTH-1:0] matrixC4_7; +wire [`DWIDTH-1:0] matrixC4_8; +wire [`DWIDTH-1:0] matrixC4_9; +wire [`DWIDTH-1:0] matrixC4_10; +wire [`DWIDTH-1:0] matrixC4_11; +wire [`DWIDTH-1:0] matrixC4_12; +wire [`DWIDTH-1:0] matrixC4_13; +wire [`DWIDTH-1:0] matrixC4_14; +wire [`DWIDTH-1:0] matrixC4_15; +wire [`DWIDTH-1:0] matrixC5_0; +wire [`DWIDTH-1:0] matrixC5_1; +wire [`DWIDTH-1:0] matrixC5_2; +wire [`DWIDTH-1:0] matrixC5_3; +wire [`DWIDTH-1:0] matrixC5_4; +wire [`DWIDTH-1:0] matrixC5_5; +wire [`DWIDTH-1:0] matrixC5_6; +wire [`DWIDTH-1:0] matrixC5_7; +wire [`DWIDTH-1:0] matrixC5_8; +wire [`DWIDTH-1:0] matrixC5_9; +wire [`DWIDTH-1:0] matrixC5_10; +wire [`DWIDTH-1:0] matrixC5_11; +wire [`DWIDTH-1:0] matrixC5_12; +wire [`DWIDTH-1:0] matrixC5_13; +wire [`DWIDTH-1:0] matrixC5_14; +wire [`DWIDTH-1:0] matrixC5_15; +wire [`DWIDTH-1:0] matrixC6_0; +wire [`DWIDTH-1:0] matrixC6_1; +wire [`DWIDTH-1:0] matrixC6_2; +wire [`DWIDTH-1:0] matrixC6_3; +wire [`DWIDTH-1:0] matrixC6_4; +wire [`DWIDTH-1:0] matrixC6_5; +wire [`DWIDTH-1:0] matrixC6_6; +wire [`DWIDTH-1:0] matrixC6_7; +wire [`DWIDTH-1:0] matrixC6_8; +wire [`DWIDTH-1:0] matrixC6_9; +wire [`DWIDTH-1:0] matrixC6_10; +wire [`DWIDTH-1:0] matrixC6_11; +wire [`DWIDTH-1:0] matrixC6_12; +wire [`DWIDTH-1:0] matrixC6_13; +wire [`DWIDTH-1:0] matrixC6_14; +wire [`DWIDTH-1:0] matrixC6_15; +wire [`DWIDTH-1:0] matrixC7_0; +wire [`DWIDTH-1:0] matrixC7_1; +wire [`DWIDTH-1:0] matrixC7_2; +wire [`DWIDTH-1:0] matrixC7_3; +wire [`DWIDTH-1:0] matrixC7_4; +wire [`DWIDTH-1:0] matrixC7_5; +wire [`DWIDTH-1:0] matrixC7_6; +wire [`DWIDTH-1:0] matrixC7_7; +wire [`DWIDTH-1:0] matrixC7_8; +wire [`DWIDTH-1:0] matrixC7_9; +wire [`DWIDTH-1:0] matrixC7_10; +wire [`DWIDTH-1:0] matrixC7_11; +wire [`DWIDTH-1:0] matrixC7_12; +wire [`DWIDTH-1:0] matrixC7_13; +wire [`DWIDTH-1:0] matrixC7_14; +wire [`DWIDTH-1:0] matrixC7_15; +wire [`DWIDTH-1:0] matrixC8_0; +wire [`DWIDTH-1:0] matrixC8_1; +wire [`DWIDTH-1:0] matrixC8_2; +wire [`DWIDTH-1:0] matrixC8_3; +wire [`DWIDTH-1:0] matrixC8_4; +wire [`DWIDTH-1:0] matrixC8_5; +wire [`DWIDTH-1:0] matrixC8_6; +wire [`DWIDTH-1:0] matrixC8_7; +wire [`DWIDTH-1:0] matrixC8_8; +wire [`DWIDTH-1:0] matrixC8_9; +wire [`DWIDTH-1:0] matrixC8_10; +wire [`DWIDTH-1:0] matrixC8_11; +wire [`DWIDTH-1:0] matrixC8_12; +wire [`DWIDTH-1:0] matrixC8_13; +wire [`DWIDTH-1:0] matrixC8_14; +wire [`DWIDTH-1:0] matrixC8_15; +wire [`DWIDTH-1:0] matrixC9_0; +wire [`DWIDTH-1:0] matrixC9_1; +wire [`DWIDTH-1:0] matrixC9_2; +wire [`DWIDTH-1:0] matrixC9_3; +wire [`DWIDTH-1:0] matrixC9_4; +wire [`DWIDTH-1:0] matrixC9_5; +wire [`DWIDTH-1:0] matrixC9_6; +wire [`DWIDTH-1:0] matrixC9_7; +wire [`DWIDTH-1:0] matrixC9_8; +wire [`DWIDTH-1:0] matrixC9_9; +wire [`DWIDTH-1:0] matrixC9_10; +wire [`DWIDTH-1:0] matrixC9_11; +wire [`DWIDTH-1:0] matrixC9_12; +wire [`DWIDTH-1:0] matrixC9_13; +wire [`DWIDTH-1:0] matrixC9_14; +wire [`DWIDTH-1:0] matrixC9_15; +wire [`DWIDTH-1:0] matrixC10_0; +wire [`DWIDTH-1:0] matrixC10_1; +wire [`DWIDTH-1:0] matrixC10_2; +wire [`DWIDTH-1:0] matrixC10_3; +wire [`DWIDTH-1:0] matrixC10_4; +wire [`DWIDTH-1:0] matrixC10_5; +wire [`DWIDTH-1:0] matrixC10_6; +wire [`DWIDTH-1:0] matrixC10_7; +wire [`DWIDTH-1:0] matrixC10_8; +wire [`DWIDTH-1:0] matrixC10_9; +wire [`DWIDTH-1:0] matrixC10_10; +wire [`DWIDTH-1:0] matrixC10_11; +wire [`DWIDTH-1:0] matrixC10_12; +wire [`DWIDTH-1:0] matrixC10_13; +wire [`DWIDTH-1:0] matrixC10_14; +wire [`DWIDTH-1:0] matrixC10_15; +wire [`DWIDTH-1:0] matrixC11_0; +wire [`DWIDTH-1:0] matrixC11_1; +wire [`DWIDTH-1:0] matrixC11_2; +wire [`DWIDTH-1:0] matrixC11_3; +wire [`DWIDTH-1:0] matrixC11_4; +wire [`DWIDTH-1:0] matrixC11_5; +wire [`DWIDTH-1:0] matrixC11_6; +wire [`DWIDTH-1:0] matrixC11_7; +wire [`DWIDTH-1:0] matrixC11_8; +wire [`DWIDTH-1:0] matrixC11_9; +wire [`DWIDTH-1:0] matrixC11_10; +wire [`DWIDTH-1:0] matrixC11_11; +wire [`DWIDTH-1:0] matrixC11_12; +wire [`DWIDTH-1:0] matrixC11_13; +wire [`DWIDTH-1:0] matrixC11_14; +wire [`DWIDTH-1:0] matrixC11_15; +wire [`DWIDTH-1:0] matrixC12_0; +wire [`DWIDTH-1:0] matrixC12_1; +wire [`DWIDTH-1:0] matrixC12_2; +wire [`DWIDTH-1:0] matrixC12_3; +wire [`DWIDTH-1:0] matrixC12_4; +wire [`DWIDTH-1:0] matrixC12_5; +wire [`DWIDTH-1:0] matrixC12_6; +wire [`DWIDTH-1:0] matrixC12_7; +wire [`DWIDTH-1:0] matrixC12_8; +wire [`DWIDTH-1:0] matrixC12_9; +wire [`DWIDTH-1:0] matrixC12_10; +wire [`DWIDTH-1:0] matrixC12_11; +wire [`DWIDTH-1:0] matrixC12_12; +wire [`DWIDTH-1:0] matrixC12_13; +wire [`DWIDTH-1:0] matrixC12_14; +wire [`DWIDTH-1:0] matrixC12_15; +wire [`DWIDTH-1:0] matrixC13_0; +wire [`DWIDTH-1:0] matrixC13_1; +wire [`DWIDTH-1:0] matrixC13_2; +wire [`DWIDTH-1:0] matrixC13_3; +wire [`DWIDTH-1:0] matrixC13_4; +wire [`DWIDTH-1:0] matrixC13_5; +wire [`DWIDTH-1:0] matrixC13_6; +wire [`DWIDTH-1:0] matrixC13_7; +wire [`DWIDTH-1:0] matrixC13_8; +wire [`DWIDTH-1:0] matrixC13_9; +wire [`DWIDTH-1:0] matrixC13_10; +wire [`DWIDTH-1:0] matrixC13_11; +wire [`DWIDTH-1:0] matrixC13_12; +wire [`DWIDTH-1:0] matrixC13_13; +wire [`DWIDTH-1:0] matrixC13_14; +wire [`DWIDTH-1:0] matrixC13_15; +wire [`DWIDTH-1:0] matrixC14_0; +wire [`DWIDTH-1:0] matrixC14_1; +wire [`DWIDTH-1:0] matrixC14_2; +wire [`DWIDTH-1:0] matrixC14_3; +wire [`DWIDTH-1:0] matrixC14_4; +wire [`DWIDTH-1:0] matrixC14_5; +wire [`DWIDTH-1:0] matrixC14_6; +wire [`DWIDTH-1:0] matrixC14_7; +wire [`DWIDTH-1:0] matrixC14_8; +wire [`DWIDTH-1:0] matrixC14_9; +wire [`DWIDTH-1:0] matrixC14_10; +wire [`DWIDTH-1:0] matrixC14_11; +wire [`DWIDTH-1:0] matrixC14_12; +wire [`DWIDTH-1:0] matrixC14_13; +wire [`DWIDTH-1:0] matrixC14_14; +wire [`DWIDTH-1:0] matrixC14_15; +wire [`DWIDTH-1:0] matrixC15_0; +wire [`DWIDTH-1:0] matrixC15_1; +wire [`DWIDTH-1:0] matrixC15_2; +wire [`DWIDTH-1:0] matrixC15_3; +wire [`DWIDTH-1:0] matrixC15_4; +wire [`DWIDTH-1:0] matrixC15_5; +wire [`DWIDTH-1:0] matrixC15_6; +wire [`DWIDTH-1:0] matrixC15_7; +wire [`DWIDTH-1:0] matrixC15_8; +wire [`DWIDTH-1:0] matrixC15_9; +wire [`DWIDTH-1:0] matrixC15_10; +wire [`DWIDTH-1:0] matrixC15_11; +wire [`DWIDTH-1:0] matrixC15_12; +wire [`DWIDTH-1:0] matrixC15_13; +wire [`DWIDTH-1:0] matrixC15_14; +wire [`DWIDTH-1:0] matrixC15_15; + +wire row_latch_en; +////////////////////////////////////////////////////////////////////////// +// Instantiation of the output logic +////////////////////////////////////////////////////////////////////////// +output_logic u_output_logic( +.start_mat_mul(start_mat_mul), +.done_mat_mul(done_mat_mul), +.address_mat_c(address_mat_c), +.address_stride_c(address_stride_c), +.c_data_out(c_data_out), +.c_data_in(c_data_in), +.c_addr(c_addr), +.c_data_available(c_data_available), +.clk_cnt(clk_cnt), +.row_latch_en(row_latch_en), +.final_mat_mul_size(final_mat_mul_size), +.matrixC0_0(matrixC0_0), +.matrixC0_1(matrixC0_1), +.matrixC0_2(matrixC0_2), +.matrixC0_3(matrixC0_3), +.matrixC0_4(matrixC0_4), +.matrixC0_5(matrixC0_5), +.matrixC0_6(matrixC0_6), +.matrixC0_7(matrixC0_7), +.matrixC0_8(matrixC0_8), +.matrixC0_9(matrixC0_9), +.matrixC0_10(matrixC0_10), +.matrixC0_11(matrixC0_11), +.matrixC0_12(matrixC0_12), +.matrixC0_13(matrixC0_13), +.matrixC0_14(matrixC0_14), +.matrixC0_15(matrixC0_15), +.matrixC1_0(matrixC1_0), +.matrixC1_1(matrixC1_1), +.matrixC1_2(matrixC1_2), +.matrixC1_3(matrixC1_3), +.matrixC1_4(matrixC1_4), +.matrixC1_5(matrixC1_5), +.matrixC1_6(matrixC1_6), +.matrixC1_7(matrixC1_7), +.matrixC1_8(matrixC1_8), +.matrixC1_9(matrixC1_9), +.matrixC1_10(matrixC1_10), +.matrixC1_11(matrixC1_11), +.matrixC1_12(matrixC1_12), +.matrixC1_13(matrixC1_13), +.matrixC1_14(matrixC1_14), +.matrixC1_15(matrixC1_15), +.matrixC2_0(matrixC2_0), +.matrixC2_1(matrixC2_1), +.matrixC2_2(matrixC2_2), +.matrixC2_3(matrixC2_3), +.matrixC2_4(matrixC2_4), +.matrixC2_5(matrixC2_5), +.matrixC2_6(matrixC2_6), +.matrixC2_7(matrixC2_7), +.matrixC2_8(matrixC2_8), +.matrixC2_9(matrixC2_9), +.matrixC2_10(matrixC2_10), +.matrixC2_11(matrixC2_11), +.matrixC2_12(matrixC2_12), +.matrixC2_13(matrixC2_13), +.matrixC2_14(matrixC2_14), +.matrixC2_15(matrixC2_15), +.matrixC3_0(matrixC3_0), +.matrixC3_1(matrixC3_1), +.matrixC3_2(matrixC3_2), +.matrixC3_3(matrixC3_3), +.matrixC3_4(matrixC3_4), +.matrixC3_5(matrixC3_5), +.matrixC3_6(matrixC3_6), +.matrixC3_7(matrixC3_7), +.matrixC3_8(matrixC3_8), +.matrixC3_9(matrixC3_9), +.matrixC3_10(matrixC3_10), +.matrixC3_11(matrixC3_11), +.matrixC3_12(matrixC3_12), +.matrixC3_13(matrixC3_13), +.matrixC3_14(matrixC3_14), +.matrixC3_15(matrixC3_15), +.matrixC4_0(matrixC4_0), +.matrixC4_1(matrixC4_1), +.matrixC4_2(matrixC4_2), +.matrixC4_3(matrixC4_3), +.matrixC4_4(matrixC4_4), +.matrixC4_5(matrixC4_5), +.matrixC4_6(matrixC4_6), +.matrixC4_7(matrixC4_7), +.matrixC4_8(matrixC4_8), +.matrixC4_9(matrixC4_9), +.matrixC4_10(matrixC4_10), +.matrixC4_11(matrixC4_11), +.matrixC4_12(matrixC4_12), +.matrixC4_13(matrixC4_13), +.matrixC4_14(matrixC4_14), +.matrixC4_15(matrixC4_15), +.matrixC5_0(matrixC5_0), +.matrixC5_1(matrixC5_1), +.matrixC5_2(matrixC5_2), +.matrixC5_3(matrixC5_3), +.matrixC5_4(matrixC5_4), +.matrixC5_5(matrixC5_5), +.matrixC5_6(matrixC5_6), +.matrixC5_7(matrixC5_7), +.matrixC5_8(matrixC5_8), +.matrixC5_9(matrixC5_9), +.matrixC5_10(matrixC5_10), +.matrixC5_11(matrixC5_11), +.matrixC5_12(matrixC5_12), +.matrixC5_13(matrixC5_13), +.matrixC5_14(matrixC5_14), +.matrixC5_15(matrixC5_15), +.matrixC6_0(matrixC6_0), +.matrixC6_1(matrixC6_1), +.matrixC6_2(matrixC6_2), +.matrixC6_3(matrixC6_3), +.matrixC6_4(matrixC6_4), +.matrixC6_5(matrixC6_5), +.matrixC6_6(matrixC6_6), +.matrixC6_7(matrixC6_7), +.matrixC6_8(matrixC6_8), +.matrixC6_9(matrixC6_9), +.matrixC6_10(matrixC6_10), +.matrixC6_11(matrixC6_11), +.matrixC6_12(matrixC6_12), +.matrixC6_13(matrixC6_13), +.matrixC6_14(matrixC6_14), +.matrixC6_15(matrixC6_15), +.matrixC7_0(matrixC7_0), +.matrixC7_1(matrixC7_1), +.matrixC7_2(matrixC7_2), +.matrixC7_3(matrixC7_3), +.matrixC7_4(matrixC7_4), +.matrixC7_5(matrixC7_5), +.matrixC7_6(matrixC7_6), +.matrixC7_7(matrixC7_7), +.matrixC7_8(matrixC7_8), +.matrixC7_9(matrixC7_9), +.matrixC7_10(matrixC7_10), +.matrixC7_11(matrixC7_11), +.matrixC7_12(matrixC7_12), +.matrixC7_13(matrixC7_13), +.matrixC7_14(matrixC7_14), +.matrixC7_15(matrixC7_15), +.matrixC8_0(matrixC8_0), +.matrixC8_1(matrixC8_1), +.matrixC8_2(matrixC8_2), +.matrixC8_3(matrixC8_3), +.matrixC8_4(matrixC8_4), +.matrixC8_5(matrixC8_5), +.matrixC8_6(matrixC8_6), +.matrixC8_7(matrixC8_7), +.matrixC8_8(matrixC8_8), +.matrixC8_9(matrixC8_9), +.matrixC8_10(matrixC8_10), +.matrixC8_11(matrixC8_11), +.matrixC8_12(matrixC8_12), +.matrixC8_13(matrixC8_13), +.matrixC8_14(matrixC8_14), +.matrixC8_15(matrixC8_15), +.matrixC9_0(matrixC9_0), +.matrixC9_1(matrixC9_1), +.matrixC9_2(matrixC9_2), +.matrixC9_3(matrixC9_3), +.matrixC9_4(matrixC9_4), +.matrixC9_5(matrixC9_5), +.matrixC9_6(matrixC9_6), +.matrixC9_7(matrixC9_7), +.matrixC9_8(matrixC9_8), +.matrixC9_9(matrixC9_9), +.matrixC9_10(matrixC9_10), +.matrixC9_11(matrixC9_11), +.matrixC9_12(matrixC9_12), +.matrixC9_13(matrixC9_13), +.matrixC9_14(matrixC9_14), +.matrixC9_15(matrixC9_15), +.matrixC10_0(matrixC10_0), +.matrixC10_1(matrixC10_1), +.matrixC10_2(matrixC10_2), +.matrixC10_3(matrixC10_3), +.matrixC10_4(matrixC10_4), +.matrixC10_5(matrixC10_5), +.matrixC10_6(matrixC10_6), +.matrixC10_7(matrixC10_7), +.matrixC10_8(matrixC10_8), +.matrixC10_9(matrixC10_9), +.matrixC10_10(matrixC10_10), +.matrixC10_11(matrixC10_11), +.matrixC10_12(matrixC10_12), +.matrixC10_13(matrixC10_13), +.matrixC10_14(matrixC10_14), +.matrixC10_15(matrixC10_15), +.matrixC11_0(matrixC11_0), +.matrixC11_1(matrixC11_1), +.matrixC11_2(matrixC11_2), +.matrixC11_3(matrixC11_3), +.matrixC11_4(matrixC11_4), +.matrixC11_5(matrixC11_5), +.matrixC11_6(matrixC11_6), +.matrixC11_7(matrixC11_7), +.matrixC11_8(matrixC11_8), +.matrixC11_9(matrixC11_9), +.matrixC11_10(matrixC11_10), +.matrixC11_11(matrixC11_11), +.matrixC11_12(matrixC11_12), +.matrixC11_13(matrixC11_13), +.matrixC11_14(matrixC11_14), +.matrixC11_15(matrixC11_15), +.matrixC12_0(matrixC12_0), +.matrixC12_1(matrixC12_1), +.matrixC12_2(matrixC12_2), +.matrixC12_3(matrixC12_3), +.matrixC12_4(matrixC12_4), +.matrixC12_5(matrixC12_5), +.matrixC12_6(matrixC12_6), +.matrixC12_7(matrixC12_7), +.matrixC12_8(matrixC12_8), +.matrixC12_9(matrixC12_9), +.matrixC12_10(matrixC12_10), +.matrixC12_11(matrixC12_11), +.matrixC12_12(matrixC12_12), +.matrixC12_13(matrixC12_13), +.matrixC12_14(matrixC12_14), +.matrixC12_15(matrixC12_15), +.matrixC13_0(matrixC13_0), +.matrixC13_1(matrixC13_1), +.matrixC13_2(matrixC13_2), +.matrixC13_3(matrixC13_3), +.matrixC13_4(matrixC13_4), +.matrixC13_5(matrixC13_5), +.matrixC13_6(matrixC13_6), +.matrixC13_7(matrixC13_7), +.matrixC13_8(matrixC13_8), +.matrixC13_9(matrixC13_9), +.matrixC13_10(matrixC13_10), +.matrixC13_11(matrixC13_11), +.matrixC13_12(matrixC13_12), +.matrixC13_13(matrixC13_13), +.matrixC13_14(matrixC13_14), +.matrixC13_15(matrixC13_15), +.matrixC14_0(matrixC14_0), +.matrixC14_1(matrixC14_1), +.matrixC14_2(matrixC14_2), +.matrixC14_3(matrixC14_3), +.matrixC14_4(matrixC14_4), +.matrixC14_5(matrixC14_5), +.matrixC14_6(matrixC14_6), +.matrixC14_7(matrixC14_7), +.matrixC14_8(matrixC14_8), +.matrixC14_9(matrixC14_9), +.matrixC14_10(matrixC14_10), +.matrixC14_11(matrixC14_11), +.matrixC14_12(matrixC14_12), +.matrixC14_13(matrixC14_13), +.matrixC14_14(matrixC14_14), +.matrixC14_15(matrixC14_15), +.matrixC15_0(matrixC15_0), +.matrixC15_1(matrixC15_1), +.matrixC15_2(matrixC15_2), +.matrixC15_3(matrixC15_3), +.matrixC15_4(matrixC15_4), +.matrixC15_5(matrixC15_5), +.matrixC15_6(matrixC15_6), +.matrixC15_7(matrixC15_7), +.matrixC15_8(matrixC15_8), +.matrixC15_9(matrixC15_9), +.matrixC15_10(matrixC15_10), +.matrixC15_11(matrixC15_11), +.matrixC15_12(matrixC15_12), +.matrixC15_13(matrixC15_13), +.matrixC15_14(matrixC15_14), +.matrixC15_15(matrixC15_15), + +.clk(clk), +.reset(reset) +); + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +systolic_pe_matrix u_systolic_pe_matrix( +.clk(clk), +.reset(reset), +.pe_reset(pe_reset), +.a0(a0), +.a1(a1), +.a2(a2), +.a3(a3), +.a4(a4), +.a5(a5), +.a6(a6), +.a7(a7), +.a8(a8), +.a9(a9), +.a10(a10), +.a11(a11), +.a12(a12), +.a13(a13), +.a14(a14), +.a15(a15), +.b0(b0), +.b1(b1), +.b2(b2), +.b3(b3), +.b4(b4), +.b5(b5), +.b6(b6), +.b7(b7), +.b8(b8), +.b9(b9), +.b10(b10), +.b11(b11), +.b12(b12), +.b13(b13), +.b14(b14), +.b15(b15), +.matrixC0_0(matrixC0_0), +.matrixC0_1(matrixC0_1), +.matrixC0_2(matrixC0_2), +.matrixC0_3(matrixC0_3), +.matrixC0_4(matrixC0_4), +.matrixC0_5(matrixC0_5), +.matrixC0_6(matrixC0_6), +.matrixC0_7(matrixC0_7), +.matrixC0_8(matrixC0_8), +.matrixC0_9(matrixC0_9), +.matrixC0_10(matrixC0_10), +.matrixC0_11(matrixC0_11), +.matrixC0_12(matrixC0_12), +.matrixC0_13(matrixC0_13), +.matrixC0_14(matrixC0_14), +.matrixC0_15(matrixC0_15), +.matrixC1_0(matrixC1_0), +.matrixC1_1(matrixC1_1), +.matrixC1_2(matrixC1_2), +.matrixC1_3(matrixC1_3), +.matrixC1_4(matrixC1_4), +.matrixC1_5(matrixC1_5), +.matrixC1_6(matrixC1_6), +.matrixC1_7(matrixC1_7), +.matrixC1_8(matrixC1_8), +.matrixC1_9(matrixC1_9), +.matrixC1_10(matrixC1_10), +.matrixC1_11(matrixC1_11), +.matrixC1_12(matrixC1_12), +.matrixC1_13(matrixC1_13), +.matrixC1_14(matrixC1_14), +.matrixC1_15(matrixC1_15), +.matrixC2_0(matrixC2_0), +.matrixC2_1(matrixC2_1), +.matrixC2_2(matrixC2_2), +.matrixC2_3(matrixC2_3), +.matrixC2_4(matrixC2_4), +.matrixC2_5(matrixC2_5), +.matrixC2_6(matrixC2_6), +.matrixC2_7(matrixC2_7), +.matrixC2_8(matrixC2_8), +.matrixC2_9(matrixC2_9), +.matrixC2_10(matrixC2_10), +.matrixC2_11(matrixC2_11), +.matrixC2_12(matrixC2_12), +.matrixC2_13(matrixC2_13), +.matrixC2_14(matrixC2_14), +.matrixC2_15(matrixC2_15), +.matrixC3_0(matrixC3_0), +.matrixC3_1(matrixC3_1), +.matrixC3_2(matrixC3_2), +.matrixC3_3(matrixC3_3), +.matrixC3_4(matrixC3_4), +.matrixC3_5(matrixC3_5), +.matrixC3_6(matrixC3_6), +.matrixC3_7(matrixC3_7), +.matrixC3_8(matrixC3_8), +.matrixC3_9(matrixC3_9), +.matrixC3_10(matrixC3_10), +.matrixC3_11(matrixC3_11), +.matrixC3_12(matrixC3_12), +.matrixC3_13(matrixC3_13), +.matrixC3_14(matrixC3_14), +.matrixC3_15(matrixC3_15), +.matrixC4_0(matrixC4_0), +.matrixC4_1(matrixC4_1), +.matrixC4_2(matrixC4_2), +.matrixC4_3(matrixC4_3), +.matrixC4_4(matrixC4_4), +.matrixC4_5(matrixC4_5), +.matrixC4_6(matrixC4_6), +.matrixC4_7(matrixC4_7), +.matrixC4_8(matrixC4_8), +.matrixC4_9(matrixC4_9), +.matrixC4_10(matrixC4_10), +.matrixC4_11(matrixC4_11), +.matrixC4_12(matrixC4_12), +.matrixC4_13(matrixC4_13), +.matrixC4_14(matrixC4_14), +.matrixC4_15(matrixC4_15), +.matrixC5_0(matrixC5_0), +.matrixC5_1(matrixC5_1), +.matrixC5_2(matrixC5_2), +.matrixC5_3(matrixC5_3), +.matrixC5_4(matrixC5_4), +.matrixC5_5(matrixC5_5), +.matrixC5_6(matrixC5_6), +.matrixC5_7(matrixC5_7), +.matrixC5_8(matrixC5_8), +.matrixC5_9(matrixC5_9), +.matrixC5_10(matrixC5_10), +.matrixC5_11(matrixC5_11), +.matrixC5_12(matrixC5_12), +.matrixC5_13(matrixC5_13), +.matrixC5_14(matrixC5_14), +.matrixC5_15(matrixC5_15), +.matrixC6_0(matrixC6_0), +.matrixC6_1(matrixC6_1), +.matrixC6_2(matrixC6_2), +.matrixC6_3(matrixC6_3), +.matrixC6_4(matrixC6_4), +.matrixC6_5(matrixC6_5), +.matrixC6_6(matrixC6_6), +.matrixC6_7(matrixC6_7), +.matrixC6_8(matrixC6_8), +.matrixC6_9(matrixC6_9), +.matrixC6_10(matrixC6_10), +.matrixC6_11(matrixC6_11), +.matrixC6_12(matrixC6_12), +.matrixC6_13(matrixC6_13), +.matrixC6_14(matrixC6_14), +.matrixC6_15(matrixC6_15), +.matrixC7_0(matrixC7_0), +.matrixC7_1(matrixC7_1), +.matrixC7_2(matrixC7_2), +.matrixC7_3(matrixC7_3), +.matrixC7_4(matrixC7_4), +.matrixC7_5(matrixC7_5), +.matrixC7_6(matrixC7_6), +.matrixC7_7(matrixC7_7), +.matrixC7_8(matrixC7_8), +.matrixC7_9(matrixC7_9), +.matrixC7_10(matrixC7_10), +.matrixC7_11(matrixC7_11), +.matrixC7_12(matrixC7_12), +.matrixC7_13(matrixC7_13), +.matrixC7_14(matrixC7_14), +.matrixC7_15(matrixC7_15), +.matrixC8_0(matrixC8_0), +.matrixC8_1(matrixC8_1), +.matrixC8_2(matrixC8_2), +.matrixC8_3(matrixC8_3), +.matrixC8_4(matrixC8_4), +.matrixC8_5(matrixC8_5), +.matrixC8_6(matrixC8_6), +.matrixC8_7(matrixC8_7), +.matrixC8_8(matrixC8_8), +.matrixC8_9(matrixC8_9), +.matrixC8_10(matrixC8_10), +.matrixC8_11(matrixC8_11), +.matrixC8_12(matrixC8_12), +.matrixC8_13(matrixC8_13), +.matrixC8_14(matrixC8_14), +.matrixC8_15(matrixC8_15), +.matrixC9_0(matrixC9_0), +.matrixC9_1(matrixC9_1), +.matrixC9_2(matrixC9_2), +.matrixC9_3(matrixC9_3), +.matrixC9_4(matrixC9_4), +.matrixC9_5(matrixC9_5), +.matrixC9_6(matrixC9_6), +.matrixC9_7(matrixC9_7), +.matrixC9_8(matrixC9_8), +.matrixC9_9(matrixC9_9), +.matrixC9_10(matrixC9_10), +.matrixC9_11(matrixC9_11), +.matrixC9_12(matrixC9_12), +.matrixC9_13(matrixC9_13), +.matrixC9_14(matrixC9_14), +.matrixC9_15(matrixC9_15), +.matrixC10_0(matrixC10_0), +.matrixC10_1(matrixC10_1), +.matrixC10_2(matrixC10_2), +.matrixC10_3(matrixC10_3), +.matrixC10_4(matrixC10_4), +.matrixC10_5(matrixC10_5), +.matrixC10_6(matrixC10_6), +.matrixC10_7(matrixC10_7), +.matrixC10_8(matrixC10_8), +.matrixC10_9(matrixC10_9), +.matrixC10_10(matrixC10_10), +.matrixC10_11(matrixC10_11), +.matrixC10_12(matrixC10_12), +.matrixC10_13(matrixC10_13), +.matrixC10_14(matrixC10_14), +.matrixC10_15(matrixC10_15), +.matrixC11_0(matrixC11_0), +.matrixC11_1(matrixC11_1), +.matrixC11_2(matrixC11_2), +.matrixC11_3(matrixC11_3), +.matrixC11_4(matrixC11_4), +.matrixC11_5(matrixC11_5), +.matrixC11_6(matrixC11_6), +.matrixC11_7(matrixC11_7), +.matrixC11_8(matrixC11_8), +.matrixC11_9(matrixC11_9), +.matrixC11_10(matrixC11_10), +.matrixC11_11(matrixC11_11), +.matrixC11_12(matrixC11_12), +.matrixC11_13(matrixC11_13), +.matrixC11_14(matrixC11_14), +.matrixC11_15(matrixC11_15), +.matrixC12_0(matrixC12_0), +.matrixC12_1(matrixC12_1), +.matrixC12_2(matrixC12_2), +.matrixC12_3(matrixC12_3), +.matrixC12_4(matrixC12_4), +.matrixC12_5(matrixC12_5), +.matrixC12_6(matrixC12_6), +.matrixC12_7(matrixC12_7), +.matrixC12_8(matrixC12_8), +.matrixC12_9(matrixC12_9), +.matrixC12_10(matrixC12_10), +.matrixC12_11(matrixC12_11), +.matrixC12_12(matrixC12_12), +.matrixC12_13(matrixC12_13), +.matrixC12_14(matrixC12_14), +.matrixC12_15(matrixC12_15), +.matrixC13_0(matrixC13_0), +.matrixC13_1(matrixC13_1), +.matrixC13_2(matrixC13_2), +.matrixC13_3(matrixC13_3), +.matrixC13_4(matrixC13_4), +.matrixC13_5(matrixC13_5), +.matrixC13_6(matrixC13_6), +.matrixC13_7(matrixC13_7), +.matrixC13_8(matrixC13_8), +.matrixC13_9(matrixC13_9), +.matrixC13_10(matrixC13_10), +.matrixC13_11(matrixC13_11), +.matrixC13_12(matrixC13_12), +.matrixC13_13(matrixC13_13), +.matrixC13_14(matrixC13_14), +.matrixC13_15(matrixC13_15), +.matrixC14_0(matrixC14_0), +.matrixC14_1(matrixC14_1), +.matrixC14_2(matrixC14_2), +.matrixC14_3(matrixC14_3), +.matrixC14_4(matrixC14_4), +.matrixC14_5(matrixC14_5), +.matrixC14_6(matrixC14_6), +.matrixC14_7(matrixC14_7), +.matrixC14_8(matrixC14_8), +.matrixC14_9(matrixC14_9), +.matrixC14_10(matrixC14_10), +.matrixC14_11(matrixC14_11), +.matrixC14_12(matrixC14_12), +.matrixC14_13(matrixC14_13), +.matrixC14_14(matrixC14_14), +.matrixC14_15(matrixC14_15), +.matrixC15_0(matrixC15_0), +.matrixC15_1(matrixC15_1), +.matrixC15_2(matrixC15_2), +.matrixC15_3(matrixC15_3), +.matrixC15_4(matrixC15_4), +.matrixC15_5(matrixC15_5), +.matrixC15_6(matrixC15_6), +.matrixC15_7(matrixC15_7), +.matrixC15_8(matrixC15_8), +.matrixC15_9(matrixC15_9), +.matrixC15_10(matrixC15_10), +.matrixC15_11(matrixC15_11), +.matrixC15_12(matrixC15_12), +.matrixC15_13(matrixC15_13), +.matrixC15_14(matrixC15_14), +.matrixC15_15(matrixC15_15), + +.a_data_out(a_data_out), +.b_data_out(b_data_out) +); + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Output logic +////////////////////////////////////////////////////////////////////////// +module output_logic( +start_mat_mul, +done_mat_mul, +address_mat_c, +address_stride_c, +c_data_in, +c_data_out, //Data values going out to next matmul - systolic shifting +c_addr, +c_data_available, +clk_cnt, +row_latch_en, +final_mat_mul_size, +matrixC0_0, +matrixC0_1, +matrixC0_2, +matrixC0_3, +matrixC0_4, +matrixC0_5, +matrixC0_6, +matrixC0_7, +matrixC0_8, +matrixC0_9, +matrixC0_10, +matrixC0_11, +matrixC0_12, +matrixC0_13, +matrixC0_14, +matrixC0_15, +matrixC1_0, +matrixC1_1, +matrixC1_2, +matrixC1_3, +matrixC1_4, +matrixC1_5, +matrixC1_6, +matrixC1_7, +matrixC1_8, +matrixC1_9, +matrixC1_10, +matrixC1_11, +matrixC1_12, +matrixC1_13, +matrixC1_14, +matrixC1_15, +matrixC2_0, +matrixC2_1, +matrixC2_2, +matrixC2_3, +matrixC2_4, +matrixC2_5, +matrixC2_6, +matrixC2_7, +matrixC2_8, +matrixC2_9, +matrixC2_10, +matrixC2_11, +matrixC2_12, +matrixC2_13, +matrixC2_14, +matrixC2_15, +matrixC3_0, +matrixC3_1, +matrixC3_2, +matrixC3_3, +matrixC3_4, +matrixC3_5, +matrixC3_6, +matrixC3_7, +matrixC3_8, +matrixC3_9, +matrixC3_10, +matrixC3_11, +matrixC3_12, +matrixC3_13, +matrixC3_14, +matrixC3_15, +matrixC4_0, +matrixC4_1, +matrixC4_2, +matrixC4_3, +matrixC4_4, +matrixC4_5, +matrixC4_6, +matrixC4_7, +matrixC4_8, +matrixC4_9, +matrixC4_10, +matrixC4_11, +matrixC4_12, +matrixC4_13, +matrixC4_14, +matrixC4_15, +matrixC5_0, +matrixC5_1, +matrixC5_2, +matrixC5_3, +matrixC5_4, +matrixC5_5, +matrixC5_6, +matrixC5_7, +matrixC5_8, +matrixC5_9, +matrixC5_10, +matrixC5_11, +matrixC5_12, +matrixC5_13, +matrixC5_14, +matrixC5_15, +matrixC6_0, +matrixC6_1, +matrixC6_2, +matrixC6_3, +matrixC6_4, +matrixC6_5, +matrixC6_6, +matrixC6_7, +matrixC6_8, +matrixC6_9, +matrixC6_10, +matrixC6_11, +matrixC6_12, +matrixC6_13, +matrixC6_14, +matrixC6_15, +matrixC7_0, +matrixC7_1, +matrixC7_2, +matrixC7_3, +matrixC7_4, +matrixC7_5, +matrixC7_6, +matrixC7_7, +matrixC7_8, +matrixC7_9, +matrixC7_10, +matrixC7_11, +matrixC7_12, +matrixC7_13, +matrixC7_14, +matrixC7_15, +matrixC8_0, +matrixC8_1, +matrixC8_2, +matrixC8_3, +matrixC8_4, +matrixC8_5, +matrixC8_6, +matrixC8_7, +matrixC8_8, +matrixC8_9, +matrixC8_10, +matrixC8_11, +matrixC8_12, +matrixC8_13, +matrixC8_14, +matrixC8_15, +matrixC9_0, +matrixC9_1, +matrixC9_2, +matrixC9_3, +matrixC9_4, +matrixC9_5, +matrixC9_6, +matrixC9_7, +matrixC9_8, +matrixC9_9, +matrixC9_10, +matrixC9_11, +matrixC9_12, +matrixC9_13, +matrixC9_14, +matrixC9_15, +matrixC10_0, +matrixC10_1, +matrixC10_2, +matrixC10_3, +matrixC10_4, +matrixC10_5, +matrixC10_6, +matrixC10_7, +matrixC10_8, +matrixC10_9, +matrixC10_10, +matrixC10_11, +matrixC10_12, +matrixC10_13, +matrixC10_14, +matrixC10_15, +matrixC11_0, +matrixC11_1, +matrixC11_2, +matrixC11_3, +matrixC11_4, +matrixC11_5, +matrixC11_6, +matrixC11_7, +matrixC11_8, +matrixC11_9, +matrixC11_10, +matrixC11_11, +matrixC11_12, +matrixC11_13, +matrixC11_14, +matrixC11_15, +matrixC12_0, +matrixC12_1, +matrixC12_2, +matrixC12_3, +matrixC12_4, +matrixC12_5, +matrixC12_6, +matrixC12_7, +matrixC12_8, +matrixC12_9, +matrixC12_10, +matrixC12_11, +matrixC12_12, +matrixC12_13, +matrixC12_14, +matrixC12_15, +matrixC13_0, +matrixC13_1, +matrixC13_2, +matrixC13_3, +matrixC13_4, +matrixC13_5, +matrixC13_6, +matrixC13_7, +matrixC13_8, +matrixC13_9, +matrixC13_10, +matrixC13_11, +matrixC13_12, +matrixC13_13, +matrixC13_14, +matrixC13_15, +matrixC14_0, +matrixC14_1, +matrixC14_2, +matrixC14_3, +matrixC14_4, +matrixC14_5, +matrixC14_6, +matrixC14_7, +matrixC14_8, +matrixC14_9, +matrixC14_10, +matrixC14_11, +matrixC14_12, +matrixC14_13, +matrixC14_14, +matrixC14_15, +matrixC15_0, +matrixC15_1, +matrixC15_2, +matrixC15_3, +matrixC15_4, +matrixC15_5, +matrixC15_6, +matrixC15_7, +matrixC15_8, +matrixC15_9, +matrixC15_10, +matrixC15_11, +matrixC15_12, +matrixC15_13, +matrixC15_14, +matrixC15_15, + +clk, +reset +); + +input clk; +input reset; +input start_mat_mul; +input done_mat_mul; +input [`AWIDTH-1:0] address_mat_c; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; +output [`AWIDTH-1:0] c_addr; +output c_data_available; +input [7:0] clk_cnt; +output row_latch_en; + +input [7:0] final_mat_mul_size; +input [`DWIDTH-1:0] matrixC0_0; +input [`DWIDTH-1:0] matrixC0_1; +input [`DWIDTH-1:0] matrixC0_2; +input [`DWIDTH-1:0] matrixC0_3; +input [`DWIDTH-1:0] matrixC0_4; +input [`DWIDTH-1:0] matrixC0_5; +input [`DWIDTH-1:0] matrixC0_6; +input [`DWIDTH-1:0] matrixC0_7; +input [`DWIDTH-1:0] matrixC0_8; +input [`DWIDTH-1:0] matrixC0_9; +input [`DWIDTH-1:0] matrixC0_10; +input [`DWIDTH-1:0] matrixC0_11; +input [`DWIDTH-1:0] matrixC0_12; +input [`DWIDTH-1:0] matrixC0_13; +input [`DWIDTH-1:0] matrixC0_14; +input [`DWIDTH-1:0] matrixC0_15; +input [`DWIDTH-1:0] matrixC1_0; +input [`DWIDTH-1:0] matrixC1_1; +input [`DWIDTH-1:0] matrixC1_2; +input [`DWIDTH-1:0] matrixC1_3; +input [`DWIDTH-1:0] matrixC1_4; +input [`DWIDTH-1:0] matrixC1_5; +input [`DWIDTH-1:0] matrixC1_6; +input [`DWIDTH-1:0] matrixC1_7; +input [`DWIDTH-1:0] matrixC1_8; +input [`DWIDTH-1:0] matrixC1_9; +input [`DWIDTH-1:0] matrixC1_10; +input [`DWIDTH-1:0] matrixC1_11; +input [`DWIDTH-1:0] matrixC1_12; +input [`DWIDTH-1:0] matrixC1_13; +input [`DWIDTH-1:0] matrixC1_14; +input [`DWIDTH-1:0] matrixC1_15; +input [`DWIDTH-1:0] matrixC2_0; +input [`DWIDTH-1:0] matrixC2_1; +input [`DWIDTH-1:0] matrixC2_2; +input [`DWIDTH-1:0] matrixC2_3; +input [`DWIDTH-1:0] matrixC2_4; +input [`DWIDTH-1:0] matrixC2_5; +input [`DWIDTH-1:0] matrixC2_6; +input [`DWIDTH-1:0] matrixC2_7; +input [`DWIDTH-1:0] matrixC2_8; +input [`DWIDTH-1:0] matrixC2_9; +input [`DWIDTH-1:0] matrixC2_10; +input [`DWIDTH-1:0] matrixC2_11; +input [`DWIDTH-1:0] matrixC2_12; +input [`DWIDTH-1:0] matrixC2_13; +input [`DWIDTH-1:0] matrixC2_14; +input [`DWIDTH-1:0] matrixC2_15; +input [`DWIDTH-1:0] matrixC3_0; +input [`DWIDTH-1:0] matrixC3_1; +input [`DWIDTH-1:0] matrixC3_2; +input [`DWIDTH-1:0] matrixC3_3; +input [`DWIDTH-1:0] matrixC3_4; +input [`DWIDTH-1:0] matrixC3_5; +input [`DWIDTH-1:0] matrixC3_6; +input [`DWIDTH-1:0] matrixC3_7; +input [`DWIDTH-1:0] matrixC3_8; +input [`DWIDTH-1:0] matrixC3_9; +input [`DWIDTH-1:0] matrixC3_10; +input [`DWIDTH-1:0] matrixC3_11; +input [`DWIDTH-1:0] matrixC3_12; +input [`DWIDTH-1:0] matrixC3_13; +input [`DWIDTH-1:0] matrixC3_14; +input [`DWIDTH-1:0] matrixC3_15; +input [`DWIDTH-1:0] matrixC4_0; +input [`DWIDTH-1:0] matrixC4_1; +input [`DWIDTH-1:0] matrixC4_2; +input [`DWIDTH-1:0] matrixC4_3; +input [`DWIDTH-1:0] matrixC4_4; +input [`DWIDTH-1:0] matrixC4_5; +input [`DWIDTH-1:0] matrixC4_6; +input [`DWIDTH-1:0] matrixC4_7; +input [`DWIDTH-1:0] matrixC4_8; +input [`DWIDTH-1:0] matrixC4_9; +input [`DWIDTH-1:0] matrixC4_10; +input [`DWIDTH-1:0] matrixC4_11; +input [`DWIDTH-1:0] matrixC4_12; +input [`DWIDTH-1:0] matrixC4_13; +input [`DWIDTH-1:0] matrixC4_14; +input [`DWIDTH-1:0] matrixC4_15; +input [`DWIDTH-1:0] matrixC5_0; +input [`DWIDTH-1:0] matrixC5_1; +input [`DWIDTH-1:0] matrixC5_2; +input [`DWIDTH-1:0] matrixC5_3; +input [`DWIDTH-1:0] matrixC5_4; +input [`DWIDTH-1:0] matrixC5_5; +input [`DWIDTH-1:0] matrixC5_6; +input [`DWIDTH-1:0] matrixC5_7; +input [`DWIDTH-1:0] matrixC5_8; +input [`DWIDTH-1:0] matrixC5_9; +input [`DWIDTH-1:0] matrixC5_10; +input [`DWIDTH-1:0] matrixC5_11; +input [`DWIDTH-1:0] matrixC5_12; +input [`DWIDTH-1:0] matrixC5_13; +input [`DWIDTH-1:0] matrixC5_14; +input [`DWIDTH-1:0] matrixC5_15; +input [`DWIDTH-1:0] matrixC6_0; +input [`DWIDTH-1:0] matrixC6_1; +input [`DWIDTH-1:0] matrixC6_2; +input [`DWIDTH-1:0] matrixC6_3; +input [`DWIDTH-1:0] matrixC6_4; +input [`DWIDTH-1:0] matrixC6_5; +input [`DWIDTH-1:0] matrixC6_6; +input [`DWIDTH-1:0] matrixC6_7; +input [`DWIDTH-1:0] matrixC6_8; +input [`DWIDTH-1:0] matrixC6_9; +input [`DWIDTH-1:0] matrixC6_10; +input [`DWIDTH-1:0] matrixC6_11; +input [`DWIDTH-1:0] matrixC6_12; +input [`DWIDTH-1:0] matrixC6_13; +input [`DWIDTH-1:0] matrixC6_14; +input [`DWIDTH-1:0] matrixC6_15; +input [`DWIDTH-1:0] matrixC7_0; +input [`DWIDTH-1:0] matrixC7_1; +input [`DWIDTH-1:0] matrixC7_2; +input [`DWIDTH-1:0] matrixC7_3; +input [`DWIDTH-1:0] matrixC7_4; +input [`DWIDTH-1:0] matrixC7_5; +input [`DWIDTH-1:0] matrixC7_6; +input [`DWIDTH-1:0] matrixC7_7; +input [`DWIDTH-1:0] matrixC7_8; +input [`DWIDTH-1:0] matrixC7_9; +input [`DWIDTH-1:0] matrixC7_10; +input [`DWIDTH-1:0] matrixC7_11; +input [`DWIDTH-1:0] matrixC7_12; +input [`DWIDTH-1:0] matrixC7_13; +input [`DWIDTH-1:0] matrixC7_14; +input [`DWIDTH-1:0] matrixC7_15; +input [`DWIDTH-1:0] matrixC8_0; +input [`DWIDTH-1:0] matrixC8_1; +input [`DWIDTH-1:0] matrixC8_2; +input [`DWIDTH-1:0] matrixC8_3; +input [`DWIDTH-1:0] matrixC8_4; +input [`DWIDTH-1:0] matrixC8_5; +input [`DWIDTH-1:0] matrixC8_6; +input [`DWIDTH-1:0] matrixC8_7; +input [`DWIDTH-1:0] matrixC8_8; +input [`DWIDTH-1:0] matrixC8_9; +input [`DWIDTH-1:0] matrixC8_10; +input [`DWIDTH-1:0] matrixC8_11; +input [`DWIDTH-1:0] matrixC8_12; +input [`DWIDTH-1:0] matrixC8_13; +input [`DWIDTH-1:0] matrixC8_14; +input [`DWIDTH-1:0] matrixC8_15; +input [`DWIDTH-1:0] matrixC9_0; +input [`DWIDTH-1:0] matrixC9_1; +input [`DWIDTH-1:0] matrixC9_2; +input [`DWIDTH-1:0] matrixC9_3; +input [`DWIDTH-1:0] matrixC9_4; +input [`DWIDTH-1:0] matrixC9_5; +input [`DWIDTH-1:0] matrixC9_6; +input [`DWIDTH-1:0] matrixC9_7; +input [`DWIDTH-1:0] matrixC9_8; +input [`DWIDTH-1:0] matrixC9_9; +input [`DWIDTH-1:0] matrixC9_10; +input [`DWIDTH-1:0] matrixC9_11; +input [`DWIDTH-1:0] matrixC9_12; +input [`DWIDTH-1:0] matrixC9_13; +input [`DWIDTH-1:0] matrixC9_14; +input [`DWIDTH-1:0] matrixC9_15; +input [`DWIDTH-1:0] matrixC10_0; +input [`DWIDTH-1:0] matrixC10_1; +input [`DWIDTH-1:0] matrixC10_2; +input [`DWIDTH-1:0] matrixC10_3; +input [`DWIDTH-1:0] matrixC10_4; +input [`DWIDTH-1:0] matrixC10_5; +input [`DWIDTH-1:0] matrixC10_6; +input [`DWIDTH-1:0] matrixC10_7; +input [`DWIDTH-1:0] matrixC10_8; +input [`DWIDTH-1:0] matrixC10_9; +input [`DWIDTH-1:0] matrixC10_10; +input [`DWIDTH-1:0] matrixC10_11; +input [`DWIDTH-1:0] matrixC10_12; +input [`DWIDTH-1:0] matrixC10_13; +input [`DWIDTH-1:0] matrixC10_14; +input [`DWIDTH-1:0] matrixC10_15; +input [`DWIDTH-1:0] matrixC11_0; +input [`DWIDTH-1:0] matrixC11_1; +input [`DWIDTH-1:0] matrixC11_2; +input [`DWIDTH-1:0] matrixC11_3; +input [`DWIDTH-1:0] matrixC11_4; +input [`DWIDTH-1:0] matrixC11_5; +input [`DWIDTH-1:0] matrixC11_6; +input [`DWIDTH-1:0] matrixC11_7; +input [`DWIDTH-1:0] matrixC11_8; +input [`DWIDTH-1:0] matrixC11_9; +input [`DWIDTH-1:0] matrixC11_10; +input [`DWIDTH-1:0] matrixC11_11; +input [`DWIDTH-1:0] matrixC11_12; +input [`DWIDTH-1:0] matrixC11_13; +input [`DWIDTH-1:0] matrixC11_14; +input [`DWIDTH-1:0] matrixC11_15; +input [`DWIDTH-1:0] matrixC12_0; +input [`DWIDTH-1:0] matrixC12_1; +input [`DWIDTH-1:0] matrixC12_2; +input [`DWIDTH-1:0] matrixC12_3; +input [`DWIDTH-1:0] matrixC12_4; +input [`DWIDTH-1:0] matrixC12_5; +input [`DWIDTH-1:0] matrixC12_6; +input [`DWIDTH-1:0] matrixC12_7; +input [`DWIDTH-1:0] matrixC12_8; +input [`DWIDTH-1:0] matrixC12_9; +input [`DWIDTH-1:0] matrixC12_10; +input [`DWIDTH-1:0] matrixC12_11; +input [`DWIDTH-1:0] matrixC12_12; +input [`DWIDTH-1:0] matrixC12_13; +input [`DWIDTH-1:0] matrixC12_14; +input [`DWIDTH-1:0] matrixC12_15; +input [`DWIDTH-1:0] matrixC13_0; +input [`DWIDTH-1:0] matrixC13_1; +input [`DWIDTH-1:0] matrixC13_2; +input [`DWIDTH-1:0] matrixC13_3; +input [`DWIDTH-1:0] matrixC13_4; +input [`DWIDTH-1:0] matrixC13_5; +input [`DWIDTH-1:0] matrixC13_6; +input [`DWIDTH-1:0] matrixC13_7; +input [`DWIDTH-1:0] matrixC13_8; +input [`DWIDTH-1:0] matrixC13_9; +input [`DWIDTH-1:0] matrixC13_10; +input [`DWIDTH-1:0] matrixC13_11; +input [`DWIDTH-1:0] matrixC13_12; +input [`DWIDTH-1:0] matrixC13_13; +input [`DWIDTH-1:0] matrixC13_14; +input [`DWIDTH-1:0] matrixC13_15; +input [`DWIDTH-1:0] matrixC14_0; +input [`DWIDTH-1:0] matrixC14_1; +input [`DWIDTH-1:0] matrixC14_2; +input [`DWIDTH-1:0] matrixC14_3; +input [`DWIDTH-1:0] matrixC14_4; +input [`DWIDTH-1:0] matrixC14_5; +input [`DWIDTH-1:0] matrixC14_6; +input [`DWIDTH-1:0] matrixC14_7; +input [`DWIDTH-1:0] matrixC14_8; +input [`DWIDTH-1:0] matrixC14_9; +input [`DWIDTH-1:0] matrixC14_10; +input [`DWIDTH-1:0] matrixC14_11; +input [`DWIDTH-1:0] matrixC14_12; +input [`DWIDTH-1:0] matrixC14_13; +input [`DWIDTH-1:0] matrixC14_14; +input [`DWIDTH-1:0] matrixC14_15; +input [`DWIDTH-1:0] matrixC15_0; +input [`DWIDTH-1:0] matrixC15_1; +input [`DWIDTH-1:0] matrixC15_2; +input [`DWIDTH-1:0] matrixC15_3; +input [`DWIDTH-1:0] matrixC15_4; +input [`DWIDTH-1:0] matrixC15_5; +input [`DWIDTH-1:0] matrixC15_6; +input [`DWIDTH-1:0] matrixC15_7; +input [`DWIDTH-1:0] matrixC15_8; +input [`DWIDTH-1:0] matrixC15_9; +input [`DWIDTH-1:0] matrixC15_10; +input [`DWIDTH-1:0] matrixC15_11; +input [`DWIDTH-1:0] matrixC15_12; +input [`DWIDTH-1:0] matrixC15_13; +input [`DWIDTH-1:0] matrixC15_14; +input [`DWIDTH-1:0] matrixC15_15; +wire row_latch_en; + + +////////////////////////////////////////////////////////////////////////// +// Logic to capture matrix C data from the PEs and shift it out +////////////////////////////////////////////////////////////////////////// +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + (a_loc+b_loc) * `BB_MAT_MUL_SIZE + 10 + `NUM_CYCLES_IN_MAC - 1)); +//Writing the line above to avoid multiplication: +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + ((a_loc+b_loc) << `LOG2_MAT_MUL_SIZE) + 10 + `NUM_CYCLES_IN_MAC - 1)); + +assign row_latch_en = + ((clk_cnt == ((`final_mat_mul_size<<2) - `final_mat_mul_size - 1 +`NUM_CYCLES_IN_MAC))); + +reg c_data_available; +reg [`AWIDTH-1:0] c_addr; +reg start_capturing_c_data; +integer counter; +reg [16*`DWIDTH-1:0] c_data_out; +reg [16*`DWIDTH-1:0] c_data_out_1; +reg [16*`DWIDTH-1:0] c_data_out_2; +reg [16*`DWIDTH-1:0] c_data_out_3; +reg [16*`DWIDTH-1:0] c_data_out_4; +reg [16*`DWIDTH-1:0] c_data_out_5; +reg [16*`DWIDTH-1:0] c_data_out_6; +reg [16*`DWIDTH-1:0] c_data_out_7; +reg [16*`DWIDTH-1:0] c_data_out_8; +reg [16*`DWIDTH-1:0] c_data_out_9; +reg [16*`DWIDTH-1:0] c_data_out_10; +reg [16*`DWIDTH-1:0] c_data_out_11; +reg [16*`DWIDTH-1:0] c_data_out_12; +reg [16*`DWIDTH-1:0] c_data_out_13; +reg [16*`DWIDTH-1:0] c_data_out_14; +reg [16*`DWIDTH-1:0] c_data_out_15; +wire condition_to_start_shifting_output; +assign condition_to_start_shifting_output = + row_latch_en ; + + +//For larger matmuls, this logic will have more entries in the case statement +always @(posedge clk) begin + if (reset | ~start_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c + address_stride_c; + c_data_out <= 0; + counter <= 0; + + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + c_data_out_4 <= 0; + c_data_out_5 <= 0; + c_data_out_6 <= 0; + c_data_out_7 <= 0; + c_data_out_8 <= 0; + c_data_out_9 <= 0; + c_data_out_10 <= 0; + c_data_out_11 <= 0; + c_data_out_12 <= 0; + c_data_out_13 <= 0; + c_data_out_14 <= 0; + c_data_out_15 <= 0; + end else if (condition_to_start_shifting_output) begin + start_capturing_c_data <= 1'b1; + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + c_data_out <= {matrixC15_15, matrixC14_15, matrixC13_15, matrixC12_15, matrixC11_15, matrixC10_15, matrixC9_15, matrixC8_15, matrixC7_15, matrixC6_15, matrixC5_15, matrixC4_15, matrixC3_15, matrixC2_15, matrixC1_15, matrixC0_15}; + c_data_out_1 <= {matrixC15_14, matrixC14_14, matrixC13_14, matrixC12_14, matrixC11_14, matrixC10_14, matrixC9_14, matrixC8_14, matrixC7_14, matrixC6_14, matrixC5_14, matrixC4_14, matrixC3_14, matrixC2_14, matrixC1_14, matrixC0_14}; + c_data_out_2 <= {matrixC15_13, matrixC14_13, matrixC13_13, matrixC12_13, matrixC11_13, matrixC10_13, matrixC9_13, matrixC8_13, matrixC7_13, matrixC6_13, matrixC5_13, matrixC4_13, matrixC3_13, matrixC2_13, matrixC1_13, matrixC0_13}; + c_data_out_3 <= {matrixC15_12, matrixC14_12, matrixC13_12, matrixC12_12, matrixC11_12, matrixC10_12, matrixC9_12, matrixC8_12, matrixC7_12, matrixC6_12, matrixC5_12, matrixC4_12, matrixC3_12, matrixC2_12, matrixC1_12, matrixC0_12}; + c_data_out_4 <= {matrixC15_11, matrixC14_11, matrixC13_11, matrixC12_11, matrixC11_11, matrixC10_11, matrixC9_11, matrixC8_11, matrixC7_11, matrixC6_11, matrixC5_11, matrixC4_11, matrixC3_11, matrixC2_11, matrixC1_11, matrixC0_11}; + c_data_out_5 <= {matrixC15_10, matrixC14_10, matrixC13_10, matrixC12_10, matrixC11_10, matrixC10_10, matrixC9_10, matrixC8_10, matrixC7_10, matrixC6_10, matrixC5_10, matrixC4_10, matrixC3_10, matrixC2_10, matrixC1_10, matrixC0_10}; + c_data_out_6 <= {matrixC15_9, matrixC14_9, matrixC13_9, matrixC12_9, matrixC11_9, matrixC10_9, matrixC9_9, matrixC8_9, matrixC7_9, matrixC6_9, matrixC5_9, matrixC4_9, matrixC3_9, matrixC2_9, matrixC1_9, matrixC0_9}; + c_data_out_7 <= {matrixC15_8, matrixC14_8, matrixC13_8, matrixC12_8, matrixC11_8, matrixC10_8, matrixC9_8, matrixC8_8, matrixC7_8, matrixC6_8, matrixC5_8, matrixC4_8, matrixC3_8, matrixC2_8, matrixC1_8, matrixC0_8}; + c_data_out_8 <= {matrixC15_7, matrixC14_7, matrixC13_7, matrixC12_7, matrixC11_7, matrixC10_7, matrixC9_7, matrixC8_7, matrixC7_7, matrixC6_7, matrixC5_7, matrixC4_7, matrixC3_7, matrixC2_7, matrixC1_7, matrixC0_7}; + c_data_out_9 <= {matrixC15_6, matrixC14_6, matrixC13_6, matrixC12_6, matrixC11_6, matrixC10_6, matrixC9_6, matrixC8_6, matrixC7_6, matrixC6_6, matrixC5_6, matrixC4_6, matrixC3_6, matrixC2_6, matrixC1_6, matrixC0_6}; + c_data_out_10 <= {matrixC15_5, matrixC14_5, matrixC13_5, matrixC12_5, matrixC11_5, matrixC10_5, matrixC9_5, matrixC8_5, matrixC7_5, matrixC6_5, matrixC5_5, matrixC4_5, matrixC3_5, matrixC2_5, matrixC1_5, matrixC0_5}; + c_data_out_11 <= {matrixC15_4, matrixC14_4, matrixC13_4, matrixC12_4, matrixC11_4, matrixC10_4, matrixC9_4, matrixC8_4, matrixC7_4, matrixC6_4, matrixC5_4, matrixC4_4, matrixC3_4, matrixC2_4, matrixC1_4, matrixC0_4}; + c_data_out_12 <= {matrixC15_3, matrixC14_3, matrixC13_3, matrixC12_3, matrixC11_3, matrixC10_3, matrixC9_3, matrixC8_3, matrixC7_3, matrixC6_3, matrixC5_3, matrixC4_3, matrixC3_3, matrixC2_3, matrixC1_3, matrixC0_3}; + c_data_out_13 <= {matrixC15_2, matrixC14_2, matrixC13_2, matrixC12_2, matrixC11_2, matrixC10_2, matrixC9_2, matrixC8_2, matrixC7_2, matrixC6_2, matrixC5_2, matrixC4_2, matrixC3_2, matrixC2_2, matrixC1_2, matrixC0_2}; + c_data_out_14 <= {matrixC15_1, matrixC14_1, matrixC13_1, matrixC12_1, matrixC11_1, matrixC10_1, matrixC9_1, matrixC8_1, matrixC7_1, matrixC6_1, matrixC5_1, matrixC4_1, matrixC3_1, matrixC2_1, matrixC1_1, matrixC0_1}; + c_data_out_15 <= {matrixC15_0, matrixC14_0, matrixC13_0, matrixC12_0, matrixC11_0, matrixC10_0, matrixC9_0, matrixC8_0, matrixC7_0, matrixC6_0, matrixC5_0, matrixC4_0, matrixC3_0, matrixC2_0, matrixC1_0, matrixC0_0}; + + counter <= counter + 1; + end else if (done_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c + address_stride_c; + c_data_out <= 0; + + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + c_data_out_4 <= 0; + c_data_out_5 <= 0; + c_data_out_6 <= 0; + c_data_out_7 <= 0; + c_data_out_8 <= 0; + c_data_out_9 <= 0; + c_data_out_10 <= 0; + c_data_out_11 <= 0; + c_data_out_12 <= 0; + c_data_out_13 <= 0; + c_data_out_14 <= 0; + c_data_out_15 <= 0; + end + else if (counter >= `MAT_MUL_SIZE) begin + c_data_out <= c_data_out_1; + c_addr <= c_addr - address_stride_c; + + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_out_4; + c_data_out_4 <= c_data_out_5; + c_data_out_5 <= c_data_out_6; + c_data_out_6 <= c_data_out_7; + c_data_out_7 <= c_data_out_8; + c_data_out_8 <= c_data_out_9; + c_data_out_9 <= c_data_out_10; + c_data_out_10 <= c_data_out_11; + c_data_out_11 <= c_data_out_12; + c_data_out_12 <= c_data_out_13; + c_data_out_13 <= c_data_out_14; + c_data_out_14 <= c_data_out_15; + c_data_out_15 <= c_data_in; + end + else if (start_capturing_c_data) begin + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + counter <= counter + 1; + c_data_out <= c_data_out_1; + + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_out_4; + c_data_out_4 <= c_data_out_5; + c_data_out_5 <= c_data_out_6; + c_data_out_6 <= c_data_out_7; + c_data_out_7 <= c_data_out_8; + c_data_out_8 <= c_data_out_9; + c_data_out_9 <= c_data_out_10; + c_data_out_10 <= c_data_out_11; + c_data_out_11 <= c_data_out_12; + c_data_out_12 <= c_data_out_13; + c_data_out_13 <= c_data_out_14; + c_data_out_14 <= c_data_out_15; + c_data_out_15 <= c_data_in; + end +end + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolic data setup +////////////////////////////////////////////////////////////////////////// +module systolic_data_setup( +clk, +reset, +start_mat_mul, +a_addr, +b_addr, +address_mat_a, +address_mat_b, +address_stride_a, +address_stride_b, +a_data, +b_data, +clk_cnt, +a0_data, +b0_data, +a1_data_delayed_1, +b1_data_delayed_1, +a2_data_delayed_2, +b2_data_delayed_2, +a3_data_delayed_3, +b3_data_delayed_3, +a4_data_delayed_4, +b4_data_delayed_4, +a5_data_delayed_5, +b5_data_delayed_5, +a6_data_delayed_6, +b6_data_delayed_6, +a7_data_delayed_7, +b7_data_delayed_7, +a8_data_delayed_8, +b8_data_delayed_8, +a9_data_delayed_9, +b9_data_delayed_9, +a10_data_delayed_10, +b10_data_delayed_10, +a11_data_delayed_11, +b11_data_delayed_11, +a12_data_delayed_12, +b12_data_delayed_12, +a13_data_delayed_13, +b13_data_delayed_13, +a14_data_delayed_14, +b14_data_delayed_14, +a15_data_delayed_15, +b15_data_delayed_15, + +validity_mask_a_rows, +validity_mask_a_cols, +validity_mask_b_rows, +validity_mask_b_cols, + +final_mat_mul_size, + +a_loc, +b_loc +); + +input clk; +input reset; +input start_mat_mul; +output [`AWIDTH-1:0] a_addr; +output [`AWIDTH-1:0] b_addr; +input [`AWIDTH-1:0] address_mat_a; +input [`AWIDTH-1:0] address_mat_b; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; +input [7:0] clk_cnt; +output [`DWIDTH-1:0] a0_data; +output [`DWIDTH-1:0] b0_data; +output [`DWIDTH-1:0] a1_data_delayed_1; +output [`DWIDTH-1:0] b1_data_delayed_1; +output [`DWIDTH-1:0] a2_data_delayed_2; +output [`DWIDTH-1:0] b2_data_delayed_2; +output [`DWIDTH-1:0] a3_data_delayed_3; +output [`DWIDTH-1:0] b3_data_delayed_3; +output [`DWIDTH-1:0] a4_data_delayed_4; +output [`DWIDTH-1:0] b4_data_delayed_4; +output [`DWIDTH-1:0] a5_data_delayed_5; +output [`DWIDTH-1:0] b5_data_delayed_5; +output [`DWIDTH-1:0] a6_data_delayed_6; +output [`DWIDTH-1:0] b6_data_delayed_6; +output [`DWIDTH-1:0] a7_data_delayed_7; +output [`DWIDTH-1:0] b7_data_delayed_7; +output [`DWIDTH-1:0] a8_data_delayed_8; +output [`DWIDTH-1:0] b8_data_delayed_8; +output [`DWIDTH-1:0] a9_data_delayed_9; +output [`DWIDTH-1:0] b9_data_delayed_9; +output [`DWIDTH-1:0] a10_data_delayed_10; +output [`DWIDTH-1:0] b10_data_delayed_10; +output [`DWIDTH-1:0] a11_data_delayed_11; +output [`DWIDTH-1:0] b11_data_delayed_11; +output [`DWIDTH-1:0] a12_data_delayed_12; +output [`DWIDTH-1:0] b12_data_delayed_12; +output [`DWIDTH-1:0] a13_data_delayed_13; +output [`DWIDTH-1:0] b13_data_delayed_13; +output [`DWIDTH-1:0] a14_data_delayed_14; +output [`DWIDTH-1:0] b14_data_delayed_14; +output [`DWIDTH-1:0] a15_data_delayed_15; +output [`DWIDTH-1:0] b15_data_delayed_15; + +input [`MASK_WIDTH-1:0] validity_mask_a_rows; +input [`MASK_WIDTH-1:0] validity_mask_a_cols; +input [`MASK_WIDTH-1:0] validity_mask_b_rows; +input [`MASK_WIDTH-1:0] validity_mask_b_cols; + +input [7:0] final_mat_mul_size; + +input [7:0] a_loc; +input [7:0] b_loc; +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM A +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] a_addr; +reg a_mem_access; //flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin + //(clk_cnt >= a_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + + if (reset || ~start_mat_mul || (clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + a_addr <= address_mat_a-address_stride_a; + + a_mem_access <= 0; + end + //else if ((clk_cnt >= a_loc*`MAT_MUL_SIZE) && (clk_cnt < a_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + + else if ((clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (a_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + a_addr <= a_addr + address_stride_a; + + a_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM A +////////////////////////////////////////////////////////////////////////// +reg [7:0] a_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + a_mem_access_counter <= 0; + end + else if (a_mem_access == 1) begin + a_mem_access_counter <= a_mem_access_counter + 1; + end + else begin + a_mem_access_counter <= 0; + end +end + +wire a_data_valid; //flag that tells whether the data from memory is valid +assign a_data_valid = + ((validity_mask_a_cols[0]==1'b0 && a_mem_access_counter==1) || + (validity_mask_a_cols[1]==1'b0 && a_mem_access_counter==2) || + (validity_mask_a_cols[2]==1'b0 && a_mem_access_counter==3) || + (validity_mask_a_cols[3]==1'b0 && a_mem_access_counter==4) || + (validity_mask_a_cols[4]==1'b0 && a_mem_access_counter==5) || + (validity_mask_a_cols[5]==1'b0 && a_mem_access_counter==6) || + (validity_mask_a_cols[6]==1'b0 && a_mem_access_counter==7) || + (validity_mask_a_cols[7]==1'b0 && a_mem_access_counter==8) || + (validity_mask_a_cols[8]==1'b0 && a_mem_access_counter==9) || + (validity_mask_a_cols[9]==1'b0 && a_mem_access_counter==10) || + (validity_mask_a_cols[10]==1'b0 && a_mem_access_counter==11) || + (validity_mask_a_cols[11]==1'b0 && a_mem_access_counter==12) || + (validity_mask_a_cols[12]==1'b0 && a_mem_access_counter==13) || + (validity_mask_a_cols[13]==1'b0 && a_mem_access_counter==14) || + (validity_mask_a_cols[14]==1'b0 && a_mem_access_counter==15) || + (validity_mask_a_cols[15]==1'b0 && a_mem_access_counter==16)) ? + + 1'b0 : (a_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM A (systolic data setup) +////////////////////////////////////////////////////////////////////////// +assign a0_data = a_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[0]}}; +assign a1_data = a_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[1]}}; +assign a2_data = a_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[2]}}; +assign a3_data = a_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[3]}}; +assign a4_data = a_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[4]}}; +assign a5_data = a_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[5]}}; +assign a6_data = a_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[6]}}; +assign a7_data = a_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[7]}}; +assign a8_data = a_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[8]}}; +assign a9_data = a_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[9]}}; +assign a10_data = a_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[10]}}; +assign a11_data = a_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[11]}}; +assign a12_data = a_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[12]}}; +assign a13_data = a_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[13]}}; +assign a14_data = a_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[14]}}; +assign a15_data = a_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[15]}}; + +reg [`DWIDTH-1:0] a1_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_1; +reg [`DWIDTH-1:0] a3_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_1; +reg [`DWIDTH-1:0] a4_data_delayed_2; +reg [`DWIDTH-1:0] a4_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_1; +reg [`DWIDTH-1:0] a5_data_delayed_2; +reg [`DWIDTH-1:0] a5_data_delayed_3; +reg [`DWIDTH-1:0] a5_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_1; +reg [`DWIDTH-1:0] a6_data_delayed_2; +reg [`DWIDTH-1:0] a6_data_delayed_3; +reg [`DWIDTH-1:0] a6_data_delayed_4; +reg [`DWIDTH-1:0] a6_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_1; +reg [`DWIDTH-1:0] a7_data_delayed_2; +reg [`DWIDTH-1:0] a7_data_delayed_3; +reg [`DWIDTH-1:0] a7_data_delayed_4; +reg [`DWIDTH-1:0] a7_data_delayed_5; +reg [`DWIDTH-1:0] a7_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_1; +reg [`DWIDTH-1:0] a8_data_delayed_2; +reg [`DWIDTH-1:0] a8_data_delayed_3; +reg [`DWIDTH-1:0] a8_data_delayed_4; +reg [`DWIDTH-1:0] a8_data_delayed_5; +reg [`DWIDTH-1:0] a8_data_delayed_6; +reg [`DWIDTH-1:0] a8_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_1; +reg [`DWIDTH-1:0] a9_data_delayed_2; +reg [`DWIDTH-1:0] a9_data_delayed_3; +reg [`DWIDTH-1:0] a9_data_delayed_4; +reg [`DWIDTH-1:0] a9_data_delayed_5; +reg [`DWIDTH-1:0] a9_data_delayed_6; +reg [`DWIDTH-1:0] a9_data_delayed_7; +reg [`DWIDTH-1:0] a9_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_1; +reg [`DWIDTH-1:0] a10_data_delayed_2; +reg [`DWIDTH-1:0] a10_data_delayed_3; +reg [`DWIDTH-1:0] a10_data_delayed_4; +reg [`DWIDTH-1:0] a10_data_delayed_5; +reg [`DWIDTH-1:0] a10_data_delayed_6; +reg [`DWIDTH-1:0] a10_data_delayed_7; +reg [`DWIDTH-1:0] a10_data_delayed_8; +reg [`DWIDTH-1:0] a10_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_1; +reg [`DWIDTH-1:0] a11_data_delayed_2; +reg [`DWIDTH-1:0] a11_data_delayed_3; +reg [`DWIDTH-1:0] a11_data_delayed_4; +reg [`DWIDTH-1:0] a11_data_delayed_5; +reg [`DWIDTH-1:0] a11_data_delayed_6; +reg [`DWIDTH-1:0] a11_data_delayed_7; +reg [`DWIDTH-1:0] a11_data_delayed_8; +reg [`DWIDTH-1:0] a11_data_delayed_9; +reg [`DWIDTH-1:0] a11_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_1; +reg [`DWIDTH-1:0] a12_data_delayed_2; +reg [`DWIDTH-1:0] a12_data_delayed_3; +reg [`DWIDTH-1:0] a12_data_delayed_4; +reg [`DWIDTH-1:0] a12_data_delayed_5; +reg [`DWIDTH-1:0] a12_data_delayed_6; +reg [`DWIDTH-1:0] a12_data_delayed_7; +reg [`DWIDTH-1:0] a12_data_delayed_8; +reg [`DWIDTH-1:0] a12_data_delayed_9; +reg [`DWIDTH-1:0] a12_data_delayed_10; +reg [`DWIDTH-1:0] a12_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_1; +reg [`DWIDTH-1:0] a13_data_delayed_2; +reg [`DWIDTH-1:0] a13_data_delayed_3; +reg [`DWIDTH-1:0] a13_data_delayed_4; +reg [`DWIDTH-1:0] a13_data_delayed_5; +reg [`DWIDTH-1:0] a13_data_delayed_6; +reg [`DWIDTH-1:0] a13_data_delayed_7; +reg [`DWIDTH-1:0] a13_data_delayed_8; +reg [`DWIDTH-1:0] a13_data_delayed_9; +reg [`DWIDTH-1:0] a13_data_delayed_10; +reg [`DWIDTH-1:0] a13_data_delayed_11; +reg [`DWIDTH-1:0] a13_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_1; +reg [`DWIDTH-1:0] a14_data_delayed_2; +reg [`DWIDTH-1:0] a14_data_delayed_3; +reg [`DWIDTH-1:0] a14_data_delayed_4; +reg [`DWIDTH-1:0] a14_data_delayed_5; +reg [`DWIDTH-1:0] a14_data_delayed_6; +reg [`DWIDTH-1:0] a14_data_delayed_7; +reg [`DWIDTH-1:0] a14_data_delayed_8; +reg [`DWIDTH-1:0] a14_data_delayed_9; +reg [`DWIDTH-1:0] a14_data_delayed_10; +reg [`DWIDTH-1:0] a14_data_delayed_11; +reg [`DWIDTH-1:0] a14_data_delayed_12; +reg [`DWIDTH-1:0] a14_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_1; +reg [`DWIDTH-1:0] a15_data_delayed_2; +reg [`DWIDTH-1:0] a15_data_delayed_3; +reg [`DWIDTH-1:0] a15_data_delayed_4; +reg [`DWIDTH-1:0] a15_data_delayed_5; +reg [`DWIDTH-1:0] a15_data_delayed_6; +reg [`DWIDTH-1:0] a15_data_delayed_7; +reg [`DWIDTH-1:0] a15_data_delayed_8; +reg [`DWIDTH-1:0] a15_data_delayed_9; +reg [`DWIDTH-1:0] a15_data_delayed_10; +reg [`DWIDTH-1:0] a15_data_delayed_11; +reg [`DWIDTH-1:0] a15_data_delayed_12; +reg [`DWIDTH-1:0] a15_data_delayed_13; +reg [`DWIDTH-1:0] a15_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_15; + + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + a1_data_delayed_1 <= 0; + a2_data_delayed_1 <= 0; + a2_data_delayed_2 <= 0; + a3_data_delayed_1 <= 0; + a3_data_delayed_2 <= 0; + a3_data_delayed_3 <= 0; + a4_data_delayed_1 <= 0; + a4_data_delayed_2 <= 0; + a4_data_delayed_3 <= 0; + a4_data_delayed_4 <= 0; + a5_data_delayed_1 <= 0; + a5_data_delayed_2 <= 0; + a5_data_delayed_3 <= 0; + a5_data_delayed_4 <= 0; + a5_data_delayed_5 <= 0; + a6_data_delayed_1 <= 0; + a6_data_delayed_2 <= 0; + a6_data_delayed_3 <= 0; + a6_data_delayed_4 <= 0; + a6_data_delayed_5 <= 0; + a6_data_delayed_6 <= 0; + a7_data_delayed_1 <= 0; + a7_data_delayed_2 <= 0; + a7_data_delayed_3 <= 0; + a7_data_delayed_4 <= 0; + a7_data_delayed_5 <= 0; + a7_data_delayed_6 <= 0; + a7_data_delayed_7 <= 0; + a8_data_delayed_1 <= 0; + a8_data_delayed_2 <= 0; + a8_data_delayed_3 <= 0; + a8_data_delayed_4 <= 0; + a8_data_delayed_5 <= 0; + a8_data_delayed_6 <= 0; + a8_data_delayed_7 <= 0; + a8_data_delayed_8 <= 0; + a9_data_delayed_1 <= 0; + a9_data_delayed_2 <= 0; + a9_data_delayed_3 <= 0; + a9_data_delayed_4 <= 0; + a9_data_delayed_5 <= 0; + a9_data_delayed_6 <= 0; + a9_data_delayed_7 <= 0; + a9_data_delayed_8 <= 0; + a9_data_delayed_9 <= 0; + a10_data_delayed_1 <= 0; + a10_data_delayed_2 <= 0; + a10_data_delayed_3 <= 0; + a10_data_delayed_4 <= 0; + a10_data_delayed_5 <= 0; + a10_data_delayed_6 <= 0; + a10_data_delayed_7 <= 0; + a10_data_delayed_8 <= 0; + a10_data_delayed_9 <= 0; + a10_data_delayed_10 <= 0; + a11_data_delayed_1 <= 0; + a11_data_delayed_2 <= 0; + a11_data_delayed_3 <= 0; + a11_data_delayed_4 <= 0; + a11_data_delayed_5 <= 0; + a11_data_delayed_6 <= 0; + a11_data_delayed_7 <= 0; + a11_data_delayed_8 <= 0; + a11_data_delayed_9 <= 0; + a11_data_delayed_10 <= 0; + a11_data_delayed_11 <= 0; + a12_data_delayed_1 <= 0; + a12_data_delayed_2 <= 0; + a12_data_delayed_3 <= 0; + a12_data_delayed_4 <= 0; + a12_data_delayed_5 <= 0; + a12_data_delayed_6 <= 0; + a12_data_delayed_7 <= 0; + a12_data_delayed_8 <= 0; + a12_data_delayed_9 <= 0; + a12_data_delayed_10 <= 0; + a12_data_delayed_11 <= 0; + a12_data_delayed_12 <= 0; + a13_data_delayed_1 <= 0; + a13_data_delayed_2 <= 0; + a13_data_delayed_3 <= 0; + a13_data_delayed_4 <= 0; + a13_data_delayed_5 <= 0; + a13_data_delayed_6 <= 0; + a13_data_delayed_7 <= 0; + a13_data_delayed_8 <= 0; + a13_data_delayed_9 <= 0; + a13_data_delayed_10 <= 0; + a13_data_delayed_11 <= 0; + a13_data_delayed_12 <= 0; + a13_data_delayed_13 <= 0; + a14_data_delayed_1 <= 0; + a14_data_delayed_2 <= 0; + a14_data_delayed_3 <= 0; + a14_data_delayed_4 <= 0; + a14_data_delayed_5 <= 0; + a14_data_delayed_6 <= 0; + a14_data_delayed_7 <= 0; + a14_data_delayed_8 <= 0; + a14_data_delayed_9 <= 0; + a14_data_delayed_10 <= 0; + a14_data_delayed_11 <= 0; + a14_data_delayed_12 <= 0; + a14_data_delayed_13 <= 0; + a14_data_delayed_14 <= 0; + a15_data_delayed_1 <= 0; + a15_data_delayed_2 <= 0; + a15_data_delayed_3 <= 0; + a15_data_delayed_4 <= 0; + a15_data_delayed_5 <= 0; + a15_data_delayed_6 <= 0; + a15_data_delayed_7 <= 0; + a15_data_delayed_8 <= 0; + a15_data_delayed_9 <= 0; + a15_data_delayed_10 <= 0; + a15_data_delayed_11 <= 0; + a15_data_delayed_12 <= 0; + a15_data_delayed_13 <= 0; + a15_data_delayed_14 <= 0; + a15_data_delayed_15 <= 0; + + end + else begin + a1_data_delayed_1 <= a1_data; + a2_data_delayed_1 <= a2_data; + a3_data_delayed_1 <= a3_data; + a4_data_delayed_1 <= a4_data; + a5_data_delayed_1 <= a5_data; + a6_data_delayed_1 <= a6_data; + a7_data_delayed_1 <= a7_data; + a8_data_delayed_1 <= a8_data; + a9_data_delayed_1 <= a9_data; + a10_data_delayed_1 <= a10_data; + a11_data_delayed_1 <= a11_data; + a12_data_delayed_1 <= a12_data; + a13_data_delayed_1 <= a13_data; + a14_data_delayed_1 <= a14_data; + a15_data_delayed_1 <= a15_data; + a2_data_delayed_2 <= a2_data_delayed_1; + a3_data_delayed_2 <= a3_data_delayed_1; + a3_data_delayed_3 <= a3_data_delayed_2; + a4_data_delayed_2 <= a4_data_delayed_1; + a4_data_delayed_3 <= a4_data_delayed_2; + a4_data_delayed_4 <= a4_data_delayed_3; + a5_data_delayed_2 <= a5_data_delayed_1; + a5_data_delayed_3 <= a5_data_delayed_2; + a5_data_delayed_4 <= a5_data_delayed_3; + a5_data_delayed_5 <= a5_data_delayed_4; + a6_data_delayed_2 <= a6_data_delayed_1; + a6_data_delayed_3 <= a6_data_delayed_2; + a6_data_delayed_4 <= a6_data_delayed_3; + a6_data_delayed_5 <= a6_data_delayed_4; + a6_data_delayed_6 <= a6_data_delayed_5; + a7_data_delayed_2 <= a7_data_delayed_1; + a7_data_delayed_3 <= a7_data_delayed_2; + a7_data_delayed_4 <= a7_data_delayed_3; + a7_data_delayed_5 <= a7_data_delayed_4; + a7_data_delayed_6 <= a7_data_delayed_5; + a7_data_delayed_7 <= a7_data_delayed_6; + a8_data_delayed_2 <= a8_data_delayed_1; + a8_data_delayed_3 <= a8_data_delayed_2; + a8_data_delayed_4 <= a8_data_delayed_3; + a8_data_delayed_5 <= a8_data_delayed_4; + a8_data_delayed_6 <= a8_data_delayed_5; + a8_data_delayed_7 <= a8_data_delayed_6; + a8_data_delayed_8 <= a8_data_delayed_7; + a9_data_delayed_2 <= a9_data_delayed_1; + a9_data_delayed_3 <= a9_data_delayed_2; + a9_data_delayed_4 <= a9_data_delayed_3; + a9_data_delayed_5 <= a9_data_delayed_4; + a9_data_delayed_6 <= a9_data_delayed_5; + a9_data_delayed_7 <= a9_data_delayed_6; + a9_data_delayed_8 <= a9_data_delayed_7; + a9_data_delayed_9 <= a9_data_delayed_8; + a10_data_delayed_2 <= a10_data_delayed_1; + a10_data_delayed_3 <= a10_data_delayed_2; + a10_data_delayed_4 <= a10_data_delayed_3; + a10_data_delayed_5 <= a10_data_delayed_4; + a10_data_delayed_6 <= a10_data_delayed_5; + a10_data_delayed_7 <= a10_data_delayed_6; + a10_data_delayed_8 <= a10_data_delayed_7; + a10_data_delayed_9 <= a10_data_delayed_8; + a10_data_delayed_10 <= a10_data_delayed_9; + a11_data_delayed_2 <= a11_data_delayed_1; + a11_data_delayed_3 <= a11_data_delayed_2; + a11_data_delayed_4 <= a11_data_delayed_3; + a11_data_delayed_5 <= a11_data_delayed_4; + a11_data_delayed_6 <= a11_data_delayed_5; + a11_data_delayed_7 <= a11_data_delayed_6; + a11_data_delayed_8 <= a11_data_delayed_7; + a11_data_delayed_9 <= a11_data_delayed_8; + a11_data_delayed_10 <= a11_data_delayed_9; + a11_data_delayed_11 <= a11_data_delayed_10; + a12_data_delayed_2 <= a12_data_delayed_1; + a12_data_delayed_3 <= a12_data_delayed_2; + a12_data_delayed_4 <= a12_data_delayed_3; + a12_data_delayed_5 <= a12_data_delayed_4; + a12_data_delayed_6 <= a12_data_delayed_5; + a12_data_delayed_7 <= a12_data_delayed_6; + a12_data_delayed_8 <= a12_data_delayed_7; + a12_data_delayed_9 <= a12_data_delayed_8; + a12_data_delayed_10 <= a12_data_delayed_9; + a12_data_delayed_11 <= a12_data_delayed_10; + a12_data_delayed_12 <= a12_data_delayed_11; + a13_data_delayed_2 <= a13_data_delayed_1; + a13_data_delayed_3 <= a13_data_delayed_2; + a13_data_delayed_4 <= a13_data_delayed_3; + a13_data_delayed_5 <= a13_data_delayed_4; + a13_data_delayed_6 <= a13_data_delayed_5; + a13_data_delayed_7 <= a13_data_delayed_6; + a13_data_delayed_8 <= a13_data_delayed_7; + a13_data_delayed_9 <= a13_data_delayed_8; + a13_data_delayed_10 <= a13_data_delayed_9; + a13_data_delayed_11 <= a13_data_delayed_10; + a13_data_delayed_12 <= a13_data_delayed_11; + a13_data_delayed_13 <= a13_data_delayed_12; + a14_data_delayed_2 <= a14_data_delayed_1; + a14_data_delayed_3 <= a14_data_delayed_2; + a14_data_delayed_4 <= a14_data_delayed_3; + a14_data_delayed_5 <= a14_data_delayed_4; + a14_data_delayed_6 <= a14_data_delayed_5; + a14_data_delayed_7 <= a14_data_delayed_6; + a14_data_delayed_8 <= a14_data_delayed_7; + a14_data_delayed_9 <= a14_data_delayed_8; + a14_data_delayed_10 <= a14_data_delayed_9; + a14_data_delayed_11 <= a14_data_delayed_10; + a14_data_delayed_12 <= a14_data_delayed_11; + a14_data_delayed_13 <= a14_data_delayed_12; + a14_data_delayed_14 <= a14_data_delayed_13; + a15_data_delayed_2 <= a15_data_delayed_1; + a15_data_delayed_3 <= a15_data_delayed_2; + a15_data_delayed_4 <= a15_data_delayed_3; + a15_data_delayed_5 <= a15_data_delayed_4; + a15_data_delayed_6 <= a15_data_delayed_5; + a15_data_delayed_7 <= a15_data_delayed_6; + a15_data_delayed_8 <= a15_data_delayed_7; + a15_data_delayed_9 <= a15_data_delayed_8; + a15_data_delayed_10 <= a15_data_delayed_9; + a15_data_delayed_11 <= a15_data_delayed_10; + a15_data_delayed_12 <= a15_data_delayed_11; + a15_data_delayed_13 <= a15_data_delayed_12; + a15_data_delayed_14 <= a15_data_delayed_13; + a15_data_delayed_15 <= a15_data_delayed_14; + + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM B +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] b_addr; +reg b_mem_access; //flag that tells whether the matmul is trying to access memory or not +always @(posedge clk) begin + //else if (clk_cnt >= b_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + + if ((reset || ~start_mat_mul) || (clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + b_addr <= address_mat_b - address_stride_b; + + b_mem_access <= 0; + end + //else if ((clk_cnt >= b_loc*`MAT_MUL_SIZE) && (clk_cnt < b_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + + else if ((clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (b_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + b_addr <= b_addr + address_stride_b; + + b_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM B +////////////////////////////////////////////////////////////////////////// +reg [7:0] b_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + b_mem_access_counter <= 0; + end + else if (b_mem_access == 1) begin + b_mem_access_counter <= b_mem_access_counter + 1; + end + else begin + b_mem_access_counter <= 0; + end +end + +wire b_data_valid; //flag that tells whether the data from memory is valid +assign b_data_valid = + ((validity_mask_b_rows[0]==1'b0 && b_mem_access_counter==1) || + (validity_mask_b_rows[1]==1'b0 && b_mem_access_counter==2) || + (validity_mask_b_rows[2]==1'b0 && b_mem_access_counter==3) || + (validity_mask_b_rows[3]==1'b0 && b_mem_access_counter==4) || + (validity_mask_b_rows[4]==1'b0 && b_mem_access_counter==5) || + (validity_mask_b_rows[5]==1'b0 && b_mem_access_counter==6) || + (validity_mask_b_rows[6]==1'b0 && b_mem_access_counter==7) || + (validity_mask_b_rows[7]==1'b0 && b_mem_access_counter==8) || + (validity_mask_b_rows[8]==1'b0 && b_mem_access_counter==9) || + (validity_mask_b_rows[9]==1'b0 && b_mem_access_counter==10) || + (validity_mask_b_rows[10]==1'b0 && b_mem_access_counter==11) || + (validity_mask_b_rows[11]==1'b0 && b_mem_access_counter==12) || + (validity_mask_b_rows[12]==1'b0 && b_mem_access_counter==13) || + (validity_mask_b_rows[13]==1'b0 && b_mem_access_counter==14) || + (validity_mask_b_rows[14]==1'b0 && b_mem_access_counter==15) || + (validity_mask_b_rows[15]==1'b0 && b_mem_access_counter==16)) ? + + 1'b0 : (b_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM B (systolic data setup) +////////////////////////////////////////////////////////////////////////// +assign b0_data = b_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[0]}}; +assign b1_data = b_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[1]}}; +assign b2_data = b_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[2]}}; +assign b3_data = b_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[3]}}; +assign b4_data = b_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[4]}}; +assign b5_data = b_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[5]}}; +assign b6_data = b_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[6]}}; +assign b7_data = b_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[7]}}; +assign b8_data = b_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[8]}}; +assign b9_data = b_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[9]}}; +assign b10_data = b_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[10]}}; +assign b11_data = b_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[11]}}; +assign b12_data = b_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[12]}}; +assign b13_data = b_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[13]}}; +assign b14_data = b_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[14]}}; +assign b15_data = b_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[15]}}; + +reg [`DWIDTH-1:0] b1_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_1; +reg [`DWIDTH-1:0] b3_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_1; +reg [`DWIDTH-1:0] b4_data_delayed_2; +reg [`DWIDTH-1:0] b4_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_1; +reg [`DWIDTH-1:0] b5_data_delayed_2; +reg [`DWIDTH-1:0] b5_data_delayed_3; +reg [`DWIDTH-1:0] b5_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_1; +reg [`DWIDTH-1:0] b6_data_delayed_2; +reg [`DWIDTH-1:0] b6_data_delayed_3; +reg [`DWIDTH-1:0] b6_data_delayed_4; +reg [`DWIDTH-1:0] b6_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_1; +reg [`DWIDTH-1:0] b7_data_delayed_2; +reg [`DWIDTH-1:0] b7_data_delayed_3; +reg [`DWIDTH-1:0] b7_data_delayed_4; +reg [`DWIDTH-1:0] b7_data_delayed_5; +reg [`DWIDTH-1:0] b7_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_1; +reg [`DWIDTH-1:0] b8_data_delayed_2; +reg [`DWIDTH-1:0] b8_data_delayed_3; +reg [`DWIDTH-1:0] b8_data_delayed_4; +reg [`DWIDTH-1:0] b8_data_delayed_5; +reg [`DWIDTH-1:0] b8_data_delayed_6; +reg [`DWIDTH-1:0] b8_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_1; +reg [`DWIDTH-1:0] b9_data_delayed_2; +reg [`DWIDTH-1:0] b9_data_delayed_3; +reg [`DWIDTH-1:0] b9_data_delayed_4; +reg [`DWIDTH-1:0] b9_data_delayed_5; +reg [`DWIDTH-1:0] b9_data_delayed_6; +reg [`DWIDTH-1:0] b9_data_delayed_7; +reg [`DWIDTH-1:0] b9_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_1; +reg [`DWIDTH-1:0] b10_data_delayed_2; +reg [`DWIDTH-1:0] b10_data_delayed_3; +reg [`DWIDTH-1:0] b10_data_delayed_4; +reg [`DWIDTH-1:0] b10_data_delayed_5; +reg [`DWIDTH-1:0] b10_data_delayed_6; +reg [`DWIDTH-1:0] b10_data_delayed_7; +reg [`DWIDTH-1:0] b10_data_delayed_8; +reg [`DWIDTH-1:0] b10_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_1; +reg [`DWIDTH-1:0] b11_data_delayed_2; +reg [`DWIDTH-1:0] b11_data_delayed_3; +reg [`DWIDTH-1:0] b11_data_delayed_4; +reg [`DWIDTH-1:0] b11_data_delayed_5; +reg [`DWIDTH-1:0] b11_data_delayed_6; +reg [`DWIDTH-1:0] b11_data_delayed_7; +reg [`DWIDTH-1:0] b11_data_delayed_8; +reg [`DWIDTH-1:0] b11_data_delayed_9; +reg [`DWIDTH-1:0] b11_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_1; +reg [`DWIDTH-1:0] b12_data_delayed_2; +reg [`DWIDTH-1:0] b12_data_delayed_3; +reg [`DWIDTH-1:0] b12_data_delayed_4; +reg [`DWIDTH-1:0] b12_data_delayed_5; +reg [`DWIDTH-1:0] b12_data_delayed_6; +reg [`DWIDTH-1:0] b12_data_delayed_7; +reg [`DWIDTH-1:0] b12_data_delayed_8; +reg [`DWIDTH-1:0] b12_data_delayed_9; +reg [`DWIDTH-1:0] b12_data_delayed_10; +reg [`DWIDTH-1:0] b12_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_1; +reg [`DWIDTH-1:0] b13_data_delayed_2; +reg [`DWIDTH-1:0] b13_data_delayed_3; +reg [`DWIDTH-1:0] b13_data_delayed_4; +reg [`DWIDTH-1:0] b13_data_delayed_5; +reg [`DWIDTH-1:0] b13_data_delayed_6; +reg [`DWIDTH-1:0] b13_data_delayed_7; +reg [`DWIDTH-1:0] b13_data_delayed_8; +reg [`DWIDTH-1:0] b13_data_delayed_9; +reg [`DWIDTH-1:0] b13_data_delayed_10; +reg [`DWIDTH-1:0] b13_data_delayed_11; +reg [`DWIDTH-1:0] b13_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_1; +reg [`DWIDTH-1:0] b14_data_delayed_2; +reg [`DWIDTH-1:0] b14_data_delayed_3; +reg [`DWIDTH-1:0] b14_data_delayed_4; +reg [`DWIDTH-1:0] b14_data_delayed_5; +reg [`DWIDTH-1:0] b14_data_delayed_6; +reg [`DWIDTH-1:0] b14_data_delayed_7; +reg [`DWIDTH-1:0] b14_data_delayed_8; +reg [`DWIDTH-1:0] b14_data_delayed_9; +reg [`DWIDTH-1:0] b14_data_delayed_10; +reg [`DWIDTH-1:0] b14_data_delayed_11; +reg [`DWIDTH-1:0] b14_data_delayed_12; +reg [`DWIDTH-1:0] b14_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_1; +reg [`DWIDTH-1:0] b15_data_delayed_2; +reg [`DWIDTH-1:0] b15_data_delayed_3; +reg [`DWIDTH-1:0] b15_data_delayed_4; +reg [`DWIDTH-1:0] b15_data_delayed_5; +reg [`DWIDTH-1:0] b15_data_delayed_6; +reg [`DWIDTH-1:0] b15_data_delayed_7; +reg [`DWIDTH-1:0] b15_data_delayed_8; +reg [`DWIDTH-1:0] b15_data_delayed_9; +reg [`DWIDTH-1:0] b15_data_delayed_10; +reg [`DWIDTH-1:0] b15_data_delayed_11; +reg [`DWIDTH-1:0] b15_data_delayed_12; +reg [`DWIDTH-1:0] b15_data_delayed_13; +reg [`DWIDTH-1:0] b15_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_15; + + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + b1_data_delayed_1 <= 0; + b2_data_delayed_1 <= 0; + b2_data_delayed_2 <= 0; + b3_data_delayed_1 <= 0; + b3_data_delayed_2 <= 0; + b3_data_delayed_3 <= 0; + b4_data_delayed_1 <= 0; + b4_data_delayed_2 <= 0; + b4_data_delayed_3 <= 0; + b4_data_delayed_4 <= 0; + b5_data_delayed_1 <= 0; + b5_data_delayed_2 <= 0; + b5_data_delayed_3 <= 0; + b5_data_delayed_4 <= 0; + b5_data_delayed_5 <= 0; + b6_data_delayed_1 <= 0; + b6_data_delayed_2 <= 0; + b6_data_delayed_3 <= 0; + b6_data_delayed_4 <= 0; + b6_data_delayed_5 <= 0; + b6_data_delayed_6 <= 0; + b7_data_delayed_1 <= 0; + b7_data_delayed_2 <= 0; + b7_data_delayed_3 <= 0; + b7_data_delayed_4 <= 0; + b7_data_delayed_5 <= 0; + b7_data_delayed_6 <= 0; + b7_data_delayed_7 <= 0; + b8_data_delayed_1 <= 0; + b8_data_delayed_2 <= 0; + b8_data_delayed_3 <= 0; + b8_data_delayed_4 <= 0; + b8_data_delayed_5 <= 0; + b8_data_delayed_6 <= 0; + b8_data_delayed_7 <= 0; + b8_data_delayed_8 <= 0; + b9_data_delayed_1 <= 0; + b9_data_delayed_2 <= 0; + b9_data_delayed_3 <= 0; + b9_data_delayed_4 <= 0; + b9_data_delayed_5 <= 0; + b9_data_delayed_6 <= 0; + b9_data_delayed_7 <= 0; + b9_data_delayed_8 <= 0; + b9_data_delayed_9 <= 0; + b10_data_delayed_1 <= 0; + b10_data_delayed_2 <= 0; + b10_data_delayed_3 <= 0; + b10_data_delayed_4 <= 0; + b10_data_delayed_5 <= 0; + b10_data_delayed_6 <= 0; + b10_data_delayed_7 <= 0; + b10_data_delayed_8 <= 0; + b10_data_delayed_9 <= 0; + b10_data_delayed_10 <= 0; + b11_data_delayed_1 <= 0; + b11_data_delayed_2 <= 0; + b11_data_delayed_3 <= 0; + b11_data_delayed_4 <= 0; + b11_data_delayed_5 <= 0; + b11_data_delayed_6 <= 0; + b11_data_delayed_7 <= 0; + b11_data_delayed_8 <= 0; + b11_data_delayed_9 <= 0; + b11_data_delayed_10 <= 0; + b11_data_delayed_11 <= 0; + b12_data_delayed_1 <= 0; + b12_data_delayed_2 <= 0; + b12_data_delayed_3 <= 0; + b12_data_delayed_4 <= 0; + b12_data_delayed_5 <= 0; + b12_data_delayed_6 <= 0; + b12_data_delayed_7 <= 0; + b12_data_delayed_8 <= 0; + b12_data_delayed_9 <= 0; + b12_data_delayed_10 <= 0; + b12_data_delayed_11 <= 0; + b12_data_delayed_12 <= 0; + b13_data_delayed_1 <= 0; + b13_data_delayed_2 <= 0; + b13_data_delayed_3 <= 0; + b13_data_delayed_4 <= 0; + b13_data_delayed_5 <= 0; + b13_data_delayed_6 <= 0; + b13_data_delayed_7 <= 0; + b13_data_delayed_8 <= 0; + b13_data_delayed_9 <= 0; + b13_data_delayed_10 <= 0; + b13_data_delayed_11 <= 0; + b13_data_delayed_12 <= 0; + b13_data_delayed_13 <= 0; + b14_data_delayed_1 <= 0; + b14_data_delayed_2 <= 0; + b14_data_delayed_3 <= 0; + b14_data_delayed_4 <= 0; + b14_data_delayed_5 <= 0; + b14_data_delayed_6 <= 0; + b14_data_delayed_7 <= 0; + b14_data_delayed_8 <= 0; + b14_data_delayed_9 <= 0; + b14_data_delayed_10 <= 0; + b14_data_delayed_11 <= 0; + b14_data_delayed_12 <= 0; + b14_data_delayed_13 <= 0; + b14_data_delayed_14 <= 0; + b15_data_delayed_1 <= 0; + b15_data_delayed_2 <= 0; + b15_data_delayed_3 <= 0; + b15_data_delayed_4 <= 0; + b15_data_delayed_5 <= 0; + b15_data_delayed_6 <= 0; + b15_data_delayed_7 <= 0; + b15_data_delayed_8 <= 0; + b15_data_delayed_9 <= 0; + b15_data_delayed_10 <= 0; + b15_data_delayed_11 <= 0; + b15_data_delayed_12 <= 0; + b15_data_delayed_13 <= 0; + b15_data_delayed_14 <= 0; + b15_data_delayed_15 <= 0; + + end + else begin + b1_data_delayed_1 <= b1_data; + b2_data_delayed_1 <= b2_data; + b3_data_delayed_1 <= b3_data; + b4_data_delayed_1 <= b4_data; + b5_data_delayed_1 <= b5_data; + b6_data_delayed_1 <= b6_data; + b7_data_delayed_1 <= b7_data; + b8_data_delayed_1 <= b8_data; + b9_data_delayed_1 <= b9_data; + b10_data_delayed_1 <= b10_data; + b11_data_delayed_1 <= b11_data; + b12_data_delayed_1 <= b12_data; + b13_data_delayed_1 <= b13_data; + b14_data_delayed_1 <= b14_data; + b15_data_delayed_1 <= b15_data; + b2_data_delayed_2 <= b2_data_delayed_1; + b3_data_delayed_2 <= b3_data_delayed_1; + b3_data_delayed_3 <= b3_data_delayed_2; + b4_data_delayed_2 <= b4_data_delayed_1; + b4_data_delayed_3 <= b4_data_delayed_2; + b4_data_delayed_4 <= b4_data_delayed_3; + b5_data_delayed_2 <= b5_data_delayed_1; + b5_data_delayed_3 <= b5_data_delayed_2; + b5_data_delayed_4 <= b5_data_delayed_3; + b5_data_delayed_5 <= b5_data_delayed_4; + b6_data_delayed_2 <= b6_data_delayed_1; + b6_data_delayed_3 <= b6_data_delayed_2; + b6_data_delayed_4 <= b6_data_delayed_3; + b6_data_delayed_5 <= b6_data_delayed_4; + b6_data_delayed_6 <= b6_data_delayed_5; + b7_data_delayed_2 <= b7_data_delayed_1; + b7_data_delayed_3 <= b7_data_delayed_2; + b7_data_delayed_4 <= b7_data_delayed_3; + b7_data_delayed_5 <= b7_data_delayed_4; + b7_data_delayed_6 <= b7_data_delayed_5; + b7_data_delayed_7 <= b7_data_delayed_6; + b8_data_delayed_2 <= b8_data_delayed_1; + b8_data_delayed_3 <= b8_data_delayed_2; + b8_data_delayed_4 <= b8_data_delayed_3; + b8_data_delayed_5 <= b8_data_delayed_4; + b8_data_delayed_6 <= b8_data_delayed_5; + b8_data_delayed_7 <= b8_data_delayed_6; + b8_data_delayed_8 <= b8_data_delayed_7; + b9_data_delayed_2 <= b9_data_delayed_1; + b9_data_delayed_3 <= b9_data_delayed_2; + b9_data_delayed_4 <= b9_data_delayed_3; + b9_data_delayed_5 <= b9_data_delayed_4; + b9_data_delayed_6 <= b9_data_delayed_5; + b9_data_delayed_7 <= b9_data_delayed_6; + b9_data_delayed_8 <= b9_data_delayed_7; + b9_data_delayed_9 <= b9_data_delayed_8; + b10_data_delayed_2 <= b10_data_delayed_1; + b10_data_delayed_3 <= b10_data_delayed_2; + b10_data_delayed_4 <= b10_data_delayed_3; + b10_data_delayed_5 <= b10_data_delayed_4; + b10_data_delayed_6 <= b10_data_delayed_5; + b10_data_delayed_7 <= b10_data_delayed_6; + b10_data_delayed_8 <= b10_data_delayed_7; + b10_data_delayed_9 <= b10_data_delayed_8; + b10_data_delayed_10 <= b10_data_delayed_9; + b11_data_delayed_2 <= b11_data_delayed_1; + b11_data_delayed_3 <= b11_data_delayed_2; + b11_data_delayed_4 <= b11_data_delayed_3; + b11_data_delayed_5 <= b11_data_delayed_4; + b11_data_delayed_6 <= b11_data_delayed_5; + b11_data_delayed_7 <= b11_data_delayed_6; + b11_data_delayed_8 <= b11_data_delayed_7; + b11_data_delayed_9 <= b11_data_delayed_8; + b11_data_delayed_10 <= b11_data_delayed_9; + b11_data_delayed_11 <= b11_data_delayed_10; + b12_data_delayed_2 <= b12_data_delayed_1; + b12_data_delayed_3 <= b12_data_delayed_2; + b12_data_delayed_4 <= b12_data_delayed_3; + b12_data_delayed_5 <= b12_data_delayed_4; + b12_data_delayed_6 <= b12_data_delayed_5; + b12_data_delayed_7 <= b12_data_delayed_6; + b12_data_delayed_8 <= b12_data_delayed_7; + b12_data_delayed_9 <= b12_data_delayed_8; + b12_data_delayed_10 <= b12_data_delayed_9; + b12_data_delayed_11 <= b12_data_delayed_10; + b12_data_delayed_12 <= b12_data_delayed_11; + b13_data_delayed_2 <= b13_data_delayed_1; + b13_data_delayed_3 <= b13_data_delayed_2; + b13_data_delayed_4 <= b13_data_delayed_3; + b13_data_delayed_5 <= b13_data_delayed_4; + b13_data_delayed_6 <= b13_data_delayed_5; + b13_data_delayed_7 <= b13_data_delayed_6; + b13_data_delayed_8 <= b13_data_delayed_7; + b13_data_delayed_9 <= b13_data_delayed_8; + b13_data_delayed_10 <= b13_data_delayed_9; + b13_data_delayed_11 <= b13_data_delayed_10; + b13_data_delayed_12 <= b13_data_delayed_11; + b13_data_delayed_13 <= b13_data_delayed_12; + b14_data_delayed_2 <= b14_data_delayed_1; + b14_data_delayed_3 <= b14_data_delayed_2; + b14_data_delayed_4 <= b14_data_delayed_3; + b14_data_delayed_5 <= b14_data_delayed_4; + b14_data_delayed_6 <= b14_data_delayed_5; + b14_data_delayed_7 <= b14_data_delayed_6; + b14_data_delayed_8 <= b14_data_delayed_7; + b14_data_delayed_9 <= b14_data_delayed_8; + b14_data_delayed_10 <= b14_data_delayed_9; + b14_data_delayed_11 <= b14_data_delayed_10; + b14_data_delayed_12 <= b14_data_delayed_11; + b14_data_delayed_13 <= b14_data_delayed_12; + b14_data_delayed_14 <= b14_data_delayed_13; + b15_data_delayed_2 <= b15_data_delayed_1; + b15_data_delayed_3 <= b15_data_delayed_2; + b15_data_delayed_4 <= b15_data_delayed_3; + b15_data_delayed_5 <= b15_data_delayed_4; + b15_data_delayed_6 <= b15_data_delayed_5; + b15_data_delayed_7 <= b15_data_delayed_6; + b15_data_delayed_8 <= b15_data_delayed_7; + b15_data_delayed_9 <= b15_data_delayed_8; + b15_data_delayed_10 <= b15_data_delayed_9; + b15_data_delayed_11 <= b15_data_delayed_10; + b15_data_delayed_12 <= b15_data_delayed_11; + b15_data_delayed_13 <= b15_data_delayed_12; + b15_data_delayed_14 <= b15_data_delayed_13; + b15_data_delayed_15 <= b15_data_delayed_14; + + end +end +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolically connected PEs +////////////////////////////////////////////////////////////////////////// +module systolic_pe_matrix( +clk, +reset, +pe_reset, +a0, +a1, +a2, +a3, +a4, +a5, +a6, +a7, +a8, +a9, +a10, +a11, +a12, +a13, +a14, +a15, +b0, +b1, +b2, +b3, +b4, +b5, +b6, +b7, +b8, +b9, +b10, +b11, +b12, +b13, +b14, +b15, +matrixC0_0, +matrixC0_1, +matrixC0_2, +matrixC0_3, +matrixC0_4, +matrixC0_5, +matrixC0_6, +matrixC0_7, +matrixC0_8, +matrixC0_9, +matrixC0_10, +matrixC0_11, +matrixC0_12, +matrixC0_13, +matrixC0_14, +matrixC0_15, +matrixC1_0, +matrixC1_1, +matrixC1_2, +matrixC1_3, +matrixC1_4, +matrixC1_5, +matrixC1_6, +matrixC1_7, +matrixC1_8, +matrixC1_9, +matrixC1_10, +matrixC1_11, +matrixC1_12, +matrixC1_13, +matrixC1_14, +matrixC1_15, +matrixC2_0, +matrixC2_1, +matrixC2_2, +matrixC2_3, +matrixC2_4, +matrixC2_5, +matrixC2_6, +matrixC2_7, +matrixC2_8, +matrixC2_9, +matrixC2_10, +matrixC2_11, +matrixC2_12, +matrixC2_13, +matrixC2_14, +matrixC2_15, +matrixC3_0, +matrixC3_1, +matrixC3_2, +matrixC3_3, +matrixC3_4, +matrixC3_5, +matrixC3_6, +matrixC3_7, +matrixC3_8, +matrixC3_9, +matrixC3_10, +matrixC3_11, +matrixC3_12, +matrixC3_13, +matrixC3_14, +matrixC3_15, +matrixC4_0, +matrixC4_1, +matrixC4_2, +matrixC4_3, +matrixC4_4, +matrixC4_5, +matrixC4_6, +matrixC4_7, +matrixC4_8, +matrixC4_9, +matrixC4_10, +matrixC4_11, +matrixC4_12, +matrixC4_13, +matrixC4_14, +matrixC4_15, +matrixC5_0, +matrixC5_1, +matrixC5_2, +matrixC5_3, +matrixC5_4, +matrixC5_5, +matrixC5_6, +matrixC5_7, +matrixC5_8, +matrixC5_9, +matrixC5_10, +matrixC5_11, +matrixC5_12, +matrixC5_13, +matrixC5_14, +matrixC5_15, +matrixC6_0, +matrixC6_1, +matrixC6_2, +matrixC6_3, +matrixC6_4, +matrixC6_5, +matrixC6_6, +matrixC6_7, +matrixC6_8, +matrixC6_9, +matrixC6_10, +matrixC6_11, +matrixC6_12, +matrixC6_13, +matrixC6_14, +matrixC6_15, +matrixC7_0, +matrixC7_1, +matrixC7_2, +matrixC7_3, +matrixC7_4, +matrixC7_5, +matrixC7_6, +matrixC7_7, +matrixC7_8, +matrixC7_9, +matrixC7_10, +matrixC7_11, +matrixC7_12, +matrixC7_13, +matrixC7_14, +matrixC7_15, +matrixC8_0, +matrixC8_1, +matrixC8_2, +matrixC8_3, +matrixC8_4, +matrixC8_5, +matrixC8_6, +matrixC8_7, +matrixC8_8, +matrixC8_9, +matrixC8_10, +matrixC8_11, +matrixC8_12, +matrixC8_13, +matrixC8_14, +matrixC8_15, +matrixC9_0, +matrixC9_1, +matrixC9_2, +matrixC9_3, +matrixC9_4, +matrixC9_5, +matrixC9_6, +matrixC9_7, +matrixC9_8, +matrixC9_9, +matrixC9_10, +matrixC9_11, +matrixC9_12, +matrixC9_13, +matrixC9_14, +matrixC9_15, +matrixC10_0, +matrixC10_1, +matrixC10_2, +matrixC10_3, +matrixC10_4, +matrixC10_5, +matrixC10_6, +matrixC10_7, +matrixC10_8, +matrixC10_9, +matrixC10_10, +matrixC10_11, +matrixC10_12, +matrixC10_13, +matrixC10_14, +matrixC10_15, +matrixC11_0, +matrixC11_1, +matrixC11_2, +matrixC11_3, +matrixC11_4, +matrixC11_5, +matrixC11_6, +matrixC11_7, +matrixC11_8, +matrixC11_9, +matrixC11_10, +matrixC11_11, +matrixC11_12, +matrixC11_13, +matrixC11_14, +matrixC11_15, +matrixC12_0, +matrixC12_1, +matrixC12_2, +matrixC12_3, +matrixC12_4, +matrixC12_5, +matrixC12_6, +matrixC12_7, +matrixC12_8, +matrixC12_9, +matrixC12_10, +matrixC12_11, +matrixC12_12, +matrixC12_13, +matrixC12_14, +matrixC12_15, +matrixC13_0, +matrixC13_1, +matrixC13_2, +matrixC13_3, +matrixC13_4, +matrixC13_5, +matrixC13_6, +matrixC13_7, +matrixC13_8, +matrixC13_9, +matrixC13_10, +matrixC13_11, +matrixC13_12, +matrixC13_13, +matrixC13_14, +matrixC13_15, +matrixC14_0, +matrixC14_1, +matrixC14_2, +matrixC14_3, +matrixC14_4, +matrixC14_5, +matrixC14_6, +matrixC14_7, +matrixC14_8, +matrixC14_9, +matrixC14_10, +matrixC14_11, +matrixC14_12, +matrixC14_13, +matrixC14_14, +matrixC14_15, +matrixC15_0, +matrixC15_1, +matrixC15_2, +matrixC15_3, +matrixC15_4, +matrixC15_5, +matrixC15_6, +matrixC15_7, +matrixC15_8, +matrixC15_9, +matrixC15_10, +matrixC15_11, +matrixC15_12, +matrixC15_13, +matrixC15_14, +matrixC15_15, + +a_data_out, +b_data_out +); + +input clk; +input reset; +input pe_reset; +input [`DWIDTH-1:0] a0; +input [`DWIDTH-1:0] a1; +input [`DWIDTH-1:0] a2; +input [`DWIDTH-1:0] a3; +input [`DWIDTH-1:0] a4; +input [`DWIDTH-1:0] a5; +input [`DWIDTH-1:0] a6; +input [`DWIDTH-1:0] a7; +input [`DWIDTH-1:0] a8; +input [`DWIDTH-1:0] a9; +input [`DWIDTH-1:0] a10; +input [`DWIDTH-1:0] a11; +input [`DWIDTH-1:0] a12; +input [`DWIDTH-1:0] a13; +input [`DWIDTH-1:0] a14; +input [`DWIDTH-1:0] a15; +input [`DWIDTH-1:0] b0; +input [`DWIDTH-1:0] b1; +input [`DWIDTH-1:0] b2; +input [`DWIDTH-1:0] b3; +input [`DWIDTH-1:0] b4; +input [`DWIDTH-1:0] b5; +input [`DWIDTH-1:0] b6; +input [`DWIDTH-1:0] b7; +input [`DWIDTH-1:0] b8; +input [`DWIDTH-1:0] b9; +input [`DWIDTH-1:0] b10; +input [`DWIDTH-1:0] b11; +input [`DWIDTH-1:0] b12; +input [`DWIDTH-1:0] b13; +input [`DWIDTH-1:0] b14; +input [`DWIDTH-1:0] b15; +output [`DWIDTH-1:0] matrixC0_0; +output [`DWIDTH-1:0] matrixC0_1; +output [`DWIDTH-1:0] matrixC0_2; +output [`DWIDTH-1:0] matrixC0_3; +output [`DWIDTH-1:0] matrixC0_4; +output [`DWIDTH-1:0] matrixC0_5; +output [`DWIDTH-1:0] matrixC0_6; +output [`DWIDTH-1:0] matrixC0_7; +output [`DWIDTH-1:0] matrixC0_8; +output [`DWIDTH-1:0] matrixC0_9; +output [`DWIDTH-1:0] matrixC0_10; +output [`DWIDTH-1:0] matrixC0_11; +output [`DWIDTH-1:0] matrixC0_12; +output [`DWIDTH-1:0] matrixC0_13; +output [`DWIDTH-1:0] matrixC0_14; +output [`DWIDTH-1:0] matrixC0_15; +output [`DWIDTH-1:0] matrixC1_0; +output [`DWIDTH-1:0] matrixC1_1; +output [`DWIDTH-1:0] matrixC1_2; +output [`DWIDTH-1:0] matrixC1_3; +output [`DWIDTH-1:0] matrixC1_4; +output [`DWIDTH-1:0] matrixC1_5; +output [`DWIDTH-1:0] matrixC1_6; +output [`DWIDTH-1:0] matrixC1_7; +output [`DWIDTH-1:0] matrixC1_8; +output [`DWIDTH-1:0] matrixC1_9; +output [`DWIDTH-1:0] matrixC1_10; +output [`DWIDTH-1:0] matrixC1_11; +output [`DWIDTH-1:0] matrixC1_12; +output [`DWIDTH-1:0] matrixC1_13; +output [`DWIDTH-1:0] matrixC1_14; +output [`DWIDTH-1:0] matrixC1_15; +output [`DWIDTH-1:0] matrixC2_0; +output [`DWIDTH-1:0] matrixC2_1; +output [`DWIDTH-1:0] matrixC2_2; +output [`DWIDTH-1:0] matrixC2_3; +output [`DWIDTH-1:0] matrixC2_4; +output [`DWIDTH-1:0] matrixC2_5; +output [`DWIDTH-1:0] matrixC2_6; +output [`DWIDTH-1:0] matrixC2_7; +output [`DWIDTH-1:0] matrixC2_8; +output [`DWIDTH-1:0] matrixC2_9; +output [`DWIDTH-1:0] matrixC2_10; +output [`DWIDTH-1:0] matrixC2_11; +output [`DWIDTH-1:0] matrixC2_12; +output [`DWIDTH-1:0] matrixC2_13; +output [`DWIDTH-1:0] matrixC2_14; +output [`DWIDTH-1:0] matrixC2_15; +output [`DWIDTH-1:0] matrixC3_0; +output [`DWIDTH-1:0] matrixC3_1; +output [`DWIDTH-1:0] matrixC3_2; +output [`DWIDTH-1:0] matrixC3_3; +output [`DWIDTH-1:0] matrixC3_4; +output [`DWIDTH-1:0] matrixC3_5; +output [`DWIDTH-1:0] matrixC3_6; +output [`DWIDTH-1:0] matrixC3_7; +output [`DWIDTH-1:0] matrixC3_8; +output [`DWIDTH-1:0] matrixC3_9; +output [`DWIDTH-1:0] matrixC3_10; +output [`DWIDTH-1:0] matrixC3_11; +output [`DWIDTH-1:0] matrixC3_12; +output [`DWIDTH-1:0] matrixC3_13; +output [`DWIDTH-1:0] matrixC3_14; +output [`DWIDTH-1:0] matrixC3_15; +output [`DWIDTH-1:0] matrixC4_0; +output [`DWIDTH-1:0] matrixC4_1; +output [`DWIDTH-1:0] matrixC4_2; +output [`DWIDTH-1:0] matrixC4_3; +output [`DWIDTH-1:0] matrixC4_4; +output [`DWIDTH-1:0] matrixC4_5; +output [`DWIDTH-1:0] matrixC4_6; +output [`DWIDTH-1:0] matrixC4_7; +output [`DWIDTH-1:0] matrixC4_8; +output [`DWIDTH-1:0] matrixC4_9; +output [`DWIDTH-1:0] matrixC4_10; +output [`DWIDTH-1:0] matrixC4_11; +output [`DWIDTH-1:0] matrixC4_12; +output [`DWIDTH-1:0] matrixC4_13; +output [`DWIDTH-1:0] matrixC4_14; +output [`DWIDTH-1:0] matrixC4_15; +output [`DWIDTH-1:0] matrixC5_0; +output [`DWIDTH-1:0] matrixC5_1; +output [`DWIDTH-1:0] matrixC5_2; +output [`DWIDTH-1:0] matrixC5_3; +output [`DWIDTH-1:0] matrixC5_4; +output [`DWIDTH-1:0] matrixC5_5; +output [`DWIDTH-1:0] matrixC5_6; +output [`DWIDTH-1:0] matrixC5_7; +output [`DWIDTH-1:0] matrixC5_8; +output [`DWIDTH-1:0] matrixC5_9; +output [`DWIDTH-1:0] matrixC5_10; +output [`DWIDTH-1:0] matrixC5_11; +output [`DWIDTH-1:0] matrixC5_12; +output [`DWIDTH-1:0] matrixC5_13; +output [`DWIDTH-1:0] matrixC5_14; +output [`DWIDTH-1:0] matrixC5_15; +output [`DWIDTH-1:0] matrixC6_0; +output [`DWIDTH-1:0] matrixC6_1; +output [`DWIDTH-1:0] matrixC6_2; +output [`DWIDTH-1:0] matrixC6_3; +output [`DWIDTH-1:0] matrixC6_4; +output [`DWIDTH-1:0] matrixC6_5; +output [`DWIDTH-1:0] matrixC6_6; +output [`DWIDTH-1:0] matrixC6_7; +output [`DWIDTH-1:0] matrixC6_8; +output [`DWIDTH-1:0] matrixC6_9; +output [`DWIDTH-1:0] matrixC6_10; +output [`DWIDTH-1:0] matrixC6_11; +output [`DWIDTH-1:0] matrixC6_12; +output [`DWIDTH-1:0] matrixC6_13; +output [`DWIDTH-1:0] matrixC6_14; +output [`DWIDTH-1:0] matrixC6_15; +output [`DWIDTH-1:0] matrixC7_0; +output [`DWIDTH-1:0] matrixC7_1; +output [`DWIDTH-1:0] matrixC7_2; +output [`DWIDTH-1:0] matrixC7_3; +output [`DWIDTH-1:0] matrixC7_4; +output [`DWIDTH-1:0] matrixC7_5; +output [`DWIDTH-1:0] matrixC7_6; +output [`DWIDTH-1:0] matrixC7_7; +output [`DWIDTH-1:0] matrixC7_8; +output [`DWIDTH-1:0] matrixC7_9; +output [`DWIDTH-1:0] matrixC7_10; +output [`DWIDTH-1:0] matrixC7_11; +output [`DWIDTH-1:0] matrixC7_12; +output [`DWIDTH-1:0] matrixC7_13; +output [`DWIDTH-1:0] matrixC7_14; +output [`DWIDTH-1:0] matrixC7_15; +output [`DWIDTH-1:0] matrixC8_0; +output [`DWIDTH-1:0] matrixC8_1; +output [`DWIDTH-1:0] matrixC8_2; +output [`DWIDTH-1:0] matrixC8_3; +output [`DWIDTH-1:0] matrixC8_4; +output [`DWIDTH-1:0] matrixC8_5; +output [`DWIDTH-1:0] matrixC8_6; +output [`DWIDTH-1:0] matrixC8_7; +output [`DWIDTH-1:0] matrixC8_8; +output [`DWIDTH-1:0] matrixC8_9; +output [`DWIDTH-1:0] matrixC8_10; +output [`DWIDTH-1:0] matrixC8_11; +output [`DWIDTH-1:0] matrixC8_12; +output [`DWIDTH-1:0] matrixC8_13; +output [`DWIDTH-1:0] matrixC8_14; +output [`DWIDTH-1:0] matrixC8_15; +output [`DWIDTH-1:0] matrixC9_0; +output [`DWIDTH-1:0] matrixC9_1; +output [`DWIDTH-1:0] matrixC9_2; +output [`DWIDTH-1:0] matrixC9_3; +output [`DWIDTH-1:0] matrixC9_4; +output [`DWIDTH-1:0] matrixC9_5; +output [`DWIDTH-1:0] matrixC9_6; +output [`DWIDTH-1:0] matrixC9_7; +output [`DWIDTH-1:0] matrixC9_8; +output [`DWIDTH-1:0] matrixC9_9; +output [`DWIDTH-1:0] matrixC9_10; +output [`DWIDTH-1:0] matrixC9_11; +output [`DWIDTH-1:0] matrixC9_12; +output [`DWIDTH-1:0] matrixC9_13; +output [`DWIDTH-1:0] matrixC9_14; +output [`DWIDTH-1:0] matrixC9_15; +output [`DWIDTH-1:0] matrixC10_0; +output [`DWIDTH-1:0] matrixC10_1; +output [`DWIDTH-1:0] matrixC10_2; +output [`DWIDTH-1:0] matrixC10_3; +output [`DWIDTH-1:0] matrixC10_4; +output [`DWIDTH-1:0] matrixC10_5; +output [`DWIDTH-1:0] matrixC10_6; +output [`DWIDTH-1:0] matrixC10_7; +output [`DWIDTH-1:0] matrixC10_8; +output [`DWIDTH-1:0] matrixC10_9; +output [`DWIDTH-1:0] matrixC10_10; +output [`DWIDTH-1:0] matrixC10_11; +output [`DWIDTH-1:0] matrixC10_12; +output [`DWIDTH-1:0] matrixC10_13; +output [`DWIDTH-1:0] matrixC10_14; +output [`DWIDTH-1:0] matrixC10_15; +output [`DWIDTH-1:0] matrixC11_0; +output [`DWIDTH-1:0] matrixC11_1; +output [`DWIDTH-1:0] matrixC11_2; +output [`DWIDTH-1:0] matrixC11_3; +output [`DWIDTH-1:0] matrixC11_4; +output [`DWIDTH-1:0] matrixC11_5; +output [`DWIDTH-1:0] matrixC11_6; +output [`DWIDTH-1:0] matrixC11_7; +output [`DWIDTH-1:0] matrixC11_8; +output [`DWIDTH-1:0] matrixC11_9; +output [`DWIDTH-1:0] matrixC11_10; +output [`DWIDTH-1:0] matrixC11_11; +output [`DWIDTH-1:0] matrixC11_12; +output [`DWIDTH-1:0] matrixC11_13; +output [`DWIDTH-1:0] matrixC11_14; +output [`DWIDTH-1:0] matrixC11_15; +output [`DWIDTH-1:0] matrixC12_0; +output [`DWIDTH-1:0] matrixC12_1; +output [`DWIDTH-1:0] matrixC12_2; +output [`DWIDTH-1:0] matrixC12_3; +output [`DWIDTH-1:0] matrixC12_4; +output [`DWIDTH-1:0] matrixC12_5; +output [`DWIDTH-1:0] matrixC12_6; +output [`DWIDTH-1:0] matrixC12_7; +output [`DWIDTH-1:0] matrixC12_8; +output [`DWIDTH-1:0] matrixC12_9; +output [`DWIDTH-1:0] matrixC12_10; +output [`DWIDTH-1:0] matrixC12_11; +output [`DWIDTH-1:0] matrixC12_12; +output [`DWIDTH-1:0] matrixC12_13; +output [`DWIDTH-1:0] matrixC12_14; +output [`DWIDTH-1:0] matrixC12_15; +output [`DWIDTH-1:0] matrixC13_0; +output [`DWIDTH-1:0] matrixC13_1; +output [`DWIDTH-1:0] matrixC13_2; +output [`DWIDTH-1:0] matrixC13_3; +output [`DWIDTH-1:0] matrixC13_4; +output [`DWIDTH-1:0] matrixC13_5; +output [`DWIDTH-1:0] matrixC13_6; +output [`DWIDTH-1:0] matrixC13_7; +output [`DWIDTH-1:0] matrixC13_8; +output [`DWIDTH-1:0] matrixC13_9; +output [`DWIDTH-1:0] matrixC13_10; +output [`DWIDTH-1:0] matrixC13_11; +output [`DWIDTH-1:0] matrixC13_12; +output [`DWIDTH-1:0] matrixC13_13; +output [`DWIDTH-1:0] matrixC13_14; +output [`DWIDTH-1:0] matrixC13_15; +output [`DWIDTH-1:0] matrixC14_0; +output [`DWIDTH-1:0] matrixC14_1; +output [`DWIDTH-1:0] matrixC14_2; +output [`DWIDTH-1:0] matrixC14_3; +output [`DWIDTH-1:0] matrixC14_4; +output [`DWIDTH-1:0] matrixC14_5; +output [`DWIDTH-1:0] matrixC14_6; +output [`DWIDTH-1:0] matrixC14_7; +output [`DWIDTH-1:0] matrixC14_8; +output [`DWIDTH-1:0] matrixC14_9; +output [`DWIDTH-1:0] matrixC14_10; +output [`DWIDTH-1:0] matrixC14_11; +output [`DWIDTH-1:0] matrixC14_12; +output [`DWIDTH-1:0] matrixC14_13; +output [`DWIDTH-1:0] matrixC14_14; +output [`DWIDTH-1:0] matrixC14_15; +output [`DWIDTH-1:0] matrixC15_0; +output [`DWIDTH-1:0] matrixC15_1; +output [`DWIDTH-1:0] matrixC15_2; +output [`DWIDTH-1:0] matrixC15_3; +output [`DWIDTH-1:0] matrixC15_4; +output [`DWIDTH-1:0] matrixC15_5; +output [`DWIDTH-1:0] matrixC15_6; +output [`DWIDTH-1:0] matrixC15_7; +output [`DWIDTH-1:0] matrixC15_8; +output [`DWIDTH-1:0] matrixC15_9; +output [`DWIDTH-1:0] matrixC15_10; +output [`DWIDTH-1:0] matrixC15_11; +output [`DWIDTH-1:0] matrixC15_12; +output [`DWIDTH-1:0] matrixC15_13; +output [`DWIDTH-1:0] matrixC15_14; +output [`DWIDTH-1:0] matrixC15_15; + +output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + +wire [`DWIDTH-1:0] a0_0to0_1, a0_1to0_2, a0_2to0_3, a0_3to0_4, a0_4to0_5, a0_5to0_6, a0_6to0_7, a0_7to0_8, a0_8to0_9, a0_9to0_10, a0_10to0_11, a0_11to0_12, a0_12to0_13, a0_13to0_14, a0_14to0_15, a0_15to0_16; +wire [`DWIDTH-1:0] a1_0to1_1, a1_1to1_2, a1_2to1_3, a1_3to1_4, a1_4to1_5, a1_5to1_6, a1_6to1_7, a1_7to1_8, a1_8to1_9, a1_9to1_10, a1_10to1_11, a1_11to1_12, a1_12to1_13, a1_13to1_14, a1_14to1_15, a1_15to1_16; +wire [`DWIDTH-1:0] a2_0to2_1, a2_1to2_2, a2_2to2_3, a2_3to2_4, a2_4to2_5, a2_5to2_6, a2_6to2_7, a2_7to2_8, a2_8to2_9, a2_9to2_10, a2_10to2_11, a2_11to2_12, a2_12to2_13, a2_13to2_14, a2_14to2_15, a2_15to2_16; +wire [`DWIDTH-1:0] a3_0to3_1, a3_1to3_2, a3_2to3_3, a3_3to3_4, a3_4to3_5, a3_5to3_6, a3_6to3_7, a3_7to3_8, a3_8to3_9, a3_9to3_10, a3_10to3_11, a3_11to3_12, a3_12to3_13, a3_13to3_14, a3_14to3_15, a3_15to3_16; +wire [`DWIDTH-1:0] a4_0to4_1, a4_1to4_2, a4_2to4_3, a4_3to4_4, a4_4to4_5, a4_5to4_6, a4_6to4_7, a4_7to4_8, a4_8to4_9, a4_9to4_10, a4_10to4_11, a4_11to4_12, a4_12to4_13, a4_13to4_14, a4_14to4_15, a4_15to4_16; +wire [`DWIDTH-1:0] a5_0to5_1, a5_1to5_2, a5_2to5_3, a5_3to5_4, a5_4to5_5, a5_5to5_6, a5_6to5_7, a5_7to5_8, a5_8to5_9, a5_9to5_10, a5_10to5_11, a5_11to5_12, a5_12to5_13, a5_13to5_14, a5_14to5_15, a5_15to5_16; +wire [`DWIDTH-1:0] a6_0to6_1, a6_1to6_2, a6_2to6_3, a6_3to6_4, a6_4to6_5, a6_5to6_6, a6_6to6_7, a6_7to6_8, a6_8to6_9, a6_9to6_10, a6_10to6_11, a6_11to6_12, a6_12to6_13, a6_13to6_14, a6_14to6_15, a6_15to6_16; +wire [`DWIDTH-1:0] a7_0to7_1, a7_1to7_2, a7_2to7_3, a7_3to7_4, a7_4to7_5, a7_5to7_6, a7_6to7_7, a7_7to7_8, a7_8to7_9, a7_9to7_10, a7_10to7_11, a7_11to7_12, a7_12to7_13, a7_13to7_14, a7_14to7_15, a7_15to7_16; +wire [`DWIDTH-1:0] a8_0to8_1, a8_1to8_2, a8_2to8_3, a8_3to8_4, a8_4to8_5, a8_5to8_6, a8_6to8_7, a8_7to8_8, a8_8to8_9, a8_9to8_10, a8_10to8_11, a8_11to8_12, a8_12to8_13, a8_13to8_14, a8_14to8_15, a8_15to8_16; +wire [`DWIDTH-1:0] a9_0to9_1, a9_1to9_2, a9_2to9_3, a9_3to9_4, a9_4to9_5, a9_5to9_6, a9_6to9_7, a9_7to9_8, a9_8to9_9, a9_9to9_10, a9_10to9_11, a9_11to9_12, a9_12to9_13, a9_13to9_14, a9_14to9_15, a9_15to9_16; +wire [`DWIDTH-1:0] a10_0to10_1, a10_1to10_2, a10_2to10_3, a10_3to10_4, a10_4to10_5, a10_5to10_6, a10_6to10_7, a10_7to10_8, a10_8to10_9, a10_9to10_10, a10_10to10_11, a10_11to10_12, a10_12to10_13, a10_13to10_14, a10_14to10_15, a10_15to10_16; +wire [`DWIDTH-1:0] a11_0to11_1, a11_1to11_2, a11_2to11_3, a11_3to11_4, a11_4to11_5, a11_5to11_6, a11_6to11_7, a11_7to11_8, a11_8to11_9, a11_9to11_10, a11_10to11_11, a11_11to11_12, a11_12to11_13, a11_13to11_14, a11_14to11_15, a11_15to11_16; +wire [`DWIDTH-1:0] a12_0to12_1, a12_1to12_2, a12_2to12_3, a12_3to12_4, a12_4to12_5, a12_5to12_6, a12_6to12_7, a12_7to12_8, a12_8to12_9, a12_9to12_10, a12_10to12_11, a12_11to12_12, a12_12to12_13, a12_13to12_14, a12_14to12_15, a12_15to12_16; +wire [`DWIDTH-1:0] a13_0to13_1, a13_1to13_2, a13_2to13_3, a13_3to13_4, a13_4to13_5, a13_5to13_6, a13_6to13_7, a13_7to13_8, a13_8to13_9, a13_9to13_10, a13_10to13_11, a13_11to13_12, a13_12to13_13, a13_13to13_14, a13_14to13_15, a13_15to13_16; +wire [`DWIDTH-1:0] a14_0to14_1, a14_1to14_2, a14_2to14_3, a14_3to14_4, a14_4to14_5, a14_5to14_6, a14_6to14_7, a14_7to14_8, a14_8to14_9, a14_9to14_10, a14_10to14_11, a14_11to14_12, a14_12to14_13, a14_13to14_14, a14_14to14_15, a14_15to14_16; +wire [`DWIDTH-1:0] a15_0to15_1, a15_1to15_2, a15_2to15_3, a15_3to15_4, a15_4to15_5, a15_5to15_6, a15_6to15_7, a15_7to15_8, a15_8to15_9, a15_9to15_10, a15_10to15_11, a15_11to15_12, a15_12to15_13, a15_13to15_14, a15_14to15_15, a15_15to15_16; + +wire [18:0] b0_0to1_0, b1_0to2_0, b2_0to3_0, b3_0to4_0, b4_0to5_0, b5_0to6_0, b6_0to7_0, b7_0to8_0, b8_0to9_0, b9_0to10_0, b10_0to11_0, b11_0to12_0, b12_0to13_0, b13_0to14_0, b14_0to15_0, b15_0to16_0; +wire [18:0] b0_1to1_1, b1_1to2_1, b2_1to3_1, b3_1to4_1, b4_1to5_1, b5_1to6_1, b6_1to7_1, b7_1to8_1, b8_1to9_1, b9_1to10_1, b10_1to11_1, b11_1to12_1, b12_1to13_1, b13_1to14_1, b14_1to15_1, b15_1to16_1; +wire [18:0] b0_2to1_2, b1_2to2_2, b2_2to3_2, b3_2to4_2, b4_2to5_2, b5_2to6_2, b6_2to7_2, b7_2to8_2, b8_2to9_2, b9_2to10_2, b10_2to11_2, b11_2to12_2, b12_2to13_2, b13_2to14_2, b14_2to15_2, b15_2to16_2; +wire [18:0] b0_3to1_3, b1_3to2_3, b2_3to3_3, b3_3to4_3, b4_3to5_3, b5_3to6_3, b6_3to7_3, b7_3to8_3, b8_3to9_3, b9_3to10_3, b10_3to11_3, b11_3to12_3, b12_3to13_3, b13_3to14_3, b14_3to15_3, b15_3to16_3; +wire [18:0] b0_4to1_4, b1_4to2_4, b2_4to3_4, b3_4to4_4, b4_4to5_4, b5_4to6_4, b6_4to7_4, b7_4to8_4, b8_4to9_4, b9_4to10_4, b10_4to11_4, b11_4to12_4, b12_4to13_4, b13_4to14_4, b14_4to15_4, b15_4to16_4; +wire [18:0] b0_5to1_5, b1_5to2_5, b2_5to3_5, b3_5to4_5, b4_5to5_5, b5_5to6_5, b6_5to7_5, b7_5to8_5, b8_5to9_5, b9_5to10_5, b10_5to11_5, b11_5to12_5, b12_5to13_5, b13_5to14_5, b14_5to15_5, b15_5to16_5; +wire [18:0] b0_6to1_6, b1_6to2_6, b2_6to3_6, b3_6to4_6, b4_6to5_6, b5_6to6_6, b6_6to7_6, b7_6to8_6, b8_6to9_6, b9_6to10_6, b10_6to11_6, b11_6to12_6, b12_6to13_6, b13_6to14_6, b14_6to15_6, b15_6to16_6; +wire [18:0] b0_7to1_7, b1_7to2_7, b2_7to3_7, b3_7to4_7, b4_7to5_7, b5_7to6_7, b6_7to7_7, b7_7to8_7, b8_7to9_7, b9_7to10_7, b10_7to11_7, b11_7to12_7, b12_7to13_7, b13_7to14_7, b14_7to15_7, b15_7to16_7; +wire [18:0] b0_8to1_8, b1_8to2_8, b2_8to3_8, b3_8to4_8, b4_8to5_8, b5_8to6_8, b6_8to7_8, b7_8to8_8, b8_8to9_8, b9_8to10_8, b10_8to11_8, b11_8to12_8, b12_8to13_8, b13_8to14_8, b14_8to15_8, b15_8to16_8; +wire [18:0] b0_9to1_9, b1_9to2_9, b2_9to3_9, b3_9to4_9, b4_9to5_9, b5_9to6_9, b6_9to7_9, b7_9to8_9, b8_9to9_9, b9_9to10_9, b10_9to11_9, b11_9to12_9, b12_9to13_9, b13_9to14_9, b14_9to15_9, b15_9to16_9; +wire [18:0] b0_10to1_10, b1_10to2_10, b2_10to3_10, b3_10to4_10, b4_10to5_10, b5_10to6_10, b6_10to7_10, b7_10to8_10, b8_10to9_10, b9_10to10_10, b10_10to11_10, b11_10to12_10, b12_10to13_10, b13_10to14_10, b14_10to15_10, b15_10to16_10; +wire [18:0] b0_11to1_11, b1_11to2_11, b2_11to3_11, b3_11to4_11, b4_11to5_11, b5_11to6_11, b6_11to7_11, b7_11to8_11, b8_11to9_11, b9_11to10_11, b10_11to11_11, b11_11to12_11, b12_11to13_11, b13_11to14_11, b14_11to15_11, b15_11to16_11; +wire [18:0] b0_12to1_12, b1_12to2_12, b2_12to3_12, b3_12to4_12, b4_12to5_12, b5_12to6_12, b6_12to7_12, b7_12to8_12, b8_12to9_12, b9_12to10_12, b10_12to11_12, b11_12to12_12, b12_12to13_12, b13_12to14_12, b14_12to15_12, b15_12to16_12; +wire [18:0] b0_13to1_13, b1_13to2_13, b2_13to3_13, b3_13to4_13, b4_13to5_13, b5_13to6_13, b6_13to7_13, b7_13to8_13, b8_13to9_13, b9_13to10_13, b10_13to11_13, b11_13to12_13, b12_13to13_13, b13_13to14_13, b14_13to15_13, b15_13to16_13; +wire [18:0] b0_14to1_14, b1_14to2_14, b2_14to3_14, b3_14to4_14, b4_14to5_14, b5_14to6_14, b6_14to7_14, b7_14to8_14, b8_14to9_14, b9_14to10_14, b10_14to11_14, b11_14to12_14, b12_14to13_14, b13_14to14_14, b14_14to15_14, b15_14to16_14; +wire [18:0] b0_15to1_15, b1_15to2_15, b2_15to3_15, b3_15to4_15, b4_15to5_15, b5_15to6_15, b6_15to7_15, b7_15to8_15, b8_15to9_15, b9_15to10_15, b10_15to11_15, b11_15to12_15, b12_15to13_15, b13_15to14_15, b14_15to15_15, b15_15to16_15; + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +//For larger matmul, more PEs will be needed +wire effective_rst; +assign effective_rst = reset | pe_reset; + +processing_element_top_edge pe0_0(.reset(effective_rst), .clk(clk), .in_a(a0), .in_b(b0), .out_a(a0_0to0_1), .out_b(b0_0to1_0), .out_c(matrixC0_0)); +processing_element_top_edge pe0_1(.reset(effective_rst), .clk(clk), .in_a(a0_0to0_1), .in_b(b1), .out_a(a0_1to0_2), .out_b(b0_1to1_1), .out_c(matrixC0_1)); +processing_element_top_edge pe0_2(.reset(effective_rst), .clk(clk), .in_a(a0_1to0_2), .in_b(b2), .out_a(a0_2to0_3), .out_b(b0_2to1_2), .out_c(matrixC0_2)); +processing_element_top_edge pe0_3(.reset(effective_rst), .clk(clk), .in_a(a0_2to0_3), .in_b(b3), .out_a(a0_3to0_4), .out_b(b0_3to1_3), .out_c(matrixC0_3)); +processing_element_top_edge pe0_4(.reset(effective_rst), .clk(clk), .in_a(a0_3to0_4), .in_b(b4), .out_a(a0_4to0_5), .out_b(b0_4to1_4), .out_c(matrixC0_4)); +processing_element_top_edge pe0_5(.reset(effective_rst), .clk(clk), .in_a(a0_4to0_5), .in_b(b5), .out_a(a0_5to0_6), .out_b(b0_5to1_5), .out_c(matrixC0_5)); +processing_element_top_edge pe0_6(.reset(effective_rst), .clk(clk), .in_a(a0_5to0_6), .in_b(b6), .out_a(a0_6to0_7), .out_b(b0_6to1_6), .out_c(matrixC0_6)); +processing_element_top_edge pe0_7(.reset(effective_rst), .clk(clk), .in_a(a0_6to0_7), .in_b(b7), .out_a(a0_7to0_8), .out_b(b0_7to1_7), .out_c(matrixC0_7)); +processing_element_top_edge pe0_8(.reset(effective_rst), .clk(clk), .in_a(a0_7to0_8), .in_b(b8), .out_a(a0_8to0_9), .out_b(b0_8to1_8), .out_c(matrixC0_8)); +processing_element_top_edge pe0_9(.reset(effective_rst), .clk(clk), .in_a(a0_8to0_9), .in_b(b9), .out_a(a0_9to0_10), .out_b(b0_9to1_9), .out_c(matrixC0_9)); +processing_element_top_edge pe0_10(.reset(effective_rst), .clk(clk), .in_a(a0_9to0_10), .in_b(b10), .out_a(a0_10to0_11), .out_b(b0_10to1_10), .out_c(matrixC0_10)); +processing_element_top_edge pe0_11(.reset(effective_rst), .clk(clk), .in_a(a0_10to0_11), .in_b(b11), .out_a(a0_11to0_12), .out_b(b0_11to1_11), .out_c(matrixC0_11)); +processing_element_top_edge pe0_12(.reset(effective_rst), .clk(clk), .in_a(a0_11to0_12), .in_b(b12), .out_a(a0_12to0_13), .out_b(b0_12to1_12), .out_c(matrixC0_12)); +processing_element_top_edge pe0_13(.reset(effective_rst), .clk(clk), .in_a(a0_12to0_13), .in_b(b13), .out_a(a0_13to0_14), .out_b(b0_13to1_13), .out_c(matrixC0_13)); +processing_element_top_edge pe0_14(.reset(effective_rst), .clk(clk), .in_a(a0_13to0_14), .in_b(b14), .out_a(a0_14to0_15), .out_b(b0_14to1_14), .out_c(matrixC0_14)); +processing_element_top_edge pe0_15(.reset(effective_rst), .clk(clk), .in_a(a0_14to0_15), .in_b(b15), .out_a(a0_15to0_16), .out_b(b0_15to1_15), .out_c(matrixC0_15)); + +processing_element pe1_0(.reset(effective_rst), .clk(clk), .in_a(a1), .in_b(b0_0to1_0), .out_a(a1_0to1_1), .out_b(b1_0to2_0), .out_c(matrixC1_0)); +processing_element pe2_0(.reset(effective_rst), .clk(clk), .in_a(a2), .in_b(b1_0to2_0), .out_a(a2_0to2_1), .out_b(b2_0to3_0), .out_c(matrixC2_0)); +processing_element pe3_0(.reset(effective_rst), .clk(clk), .in_a(a3), .in_b(b2_0to3_0), .out_a(a3_0to3_1), .out_b(b3_0to4_0), .out_c(matrixC3_0)); +processing_element pe4_0(.reset(effective_rst), .clk(clk), .in_a(a4), .in_b(b3_0to4_0), .out_a(a4_0to4_1), .out_b(b4_0to5_0), .out_c(matrixC4_0)); +processing_element pe5_0(.reset(effective_rst), .clk(clk), .in_a(a5), .in_b(b4_0to5_0), .out_a(a5_0to5_1), .out_b(b5_0to6_0), .out_c(matrixC5_0)); +processing_element pe6_0(.reset(effective_rst), .clk(clk), .in_a(a6), .in_b(b5_0to6_0), .out_a(a6_0to6_1), .out_b(b6_0to7_0), .out_c(matrixC6_0)); +processing_element pe7_0(.reset(effective_rst), .clk(clk), .in_a(a7), .in_b(b6_0to7_0), .out_a(a7_0to7_1), .out_b(b7_0to8_0), .out_c(matrixC7_0)); +processing_element pe8_0(.reset(effective_rst), .clk(clk), .in_a(a8), .in_b(b7_0to8_0), .out_a(a8_0to8_1), .out_b(b8_0to9_0), .out_c(matrixC8_0)); +processing_element pe9_0(.reset(effective_rst), .clk(clk), .in_a(a9), .in_b(b8_0to9_0), .out_a(a9_0to9_1), .out_b(b9_0to10_0), .out_c(matrixC9_0)); +processing_element pe10_0(.reset(effective_rst), .clk(clk), .in_a(a10), .in_b(b9_0to10_0), .out_a(a10_0to10_1), .out_b(b10_0to11_0), .out_c(matrixC10_0)); +processing_element pe11_0(.reset(effective_rst), .clk(clk), .in_a(a11), .in_b(b10_0to11_0), .out_a(a11_0to11_1), .out_b(b11_0to12_0), .out_c(matrixC11_0)); +processing_element pe12_0(.reset(effective_rst), .clk(clk), .in_a(a12), .in_b(b11_0to12_0), .out_a(a12_0to12_1), .out_b(b12_0to13_0), .out_c(matrixC12_0)); +processing_element pe13_0(.reset(effective_rst), .clk(clk), .in_a(a13), .in_b(b12_0to13_0), .out_a(a13_0to13_1), .out_b(b13_0to14_0), .out_c(matrixC13_0)); +processing_element pe14_0(.reset(effective_rst), .clk(clk), .in_a(a14), .in_b(b13_0to14_0), .out_a(a14_0to14_1), .out_b(b14_0to15_0), .out_c(matrixC14_0)); +processing_element_bottom_edge pe15_0(.reset(effective_rst), .clk(clk), .in_a(a15), .in_b(b14_0to15_0), .out_a(a15_0to15_1), .out_b(b15_0to16_0), .out_c(matrixC15_0)); + +processing_element pe1_1(.reset(effective_rst), .clk(clk), .in_a(a1_0to1_1), .in_b(b0_1to1_1), .out_a(a1_1to1_2), .out_b(b1_1to2_1), .out_c(matrixC1_1)); +processing_element pe1_2(.reset(effective_rst), .clk(clk), .in_a(a1_1to1_2), .in_b(b0_2to1_2), .out_a(a1_2to1_3), .out_b(b1_2to2_2), .out_c(matrixC1_2)); +processing_element pe1_3(.reset(effective_rst), .clk(clk), .in_a(a1_2to1_3), .in_b(b0_3to1_3), .out_a(a1_3to1_4), .out_b(b1_3to2_3), .out_c(matrixC1_3)); +processing_element pe1_4(.reset(effective_rst), .clk(clk), .in_a(a1_3to1_4), .in_b(b0_4to1_4), .out_a(a1_4to1_5), .out_b(b1_4to2_4), .out_c(matrixC1_4)); +processing_element pe1_5(.reset(effective_rst), .clk(clk), .in_a(a1_4to1_5), .in_b(b0_5to1_5), .out_a(a1_5to1_6), .out_b(b1_5to2_5), .out_c(matrixC1_5)); +processing_element pe1_6(.reset(effective_rst), .clk(clk), .in_a(a1_5to1_6), .in_b(b0_6to1_6), .out_a(a1_6to1_7), .out_b(b1_6to2_6), .out_c(matrixC1_6)); +processing_element pe1_7(.reset(effective_rst), .clk(clk), .in_a(a1_6to1_7), .in_b(b0_7to1_7), .out_a(a1_7to1_8), .out_b(b1_7to2_7), .out_c(matrixC1_7)); +processing_element pe1_8(.reset(effective_rst), .clk(clk), .in_a(a1_7to1_8), .in_b(b0_8to1_8), .out_a(a1_8to1_9), .out_b(b1_8to2_8), .out_c(matrixC1_8)); +processing_element pe1_9(.reset(effective_rst), .clk(clk), .in_a(a1_8to1_9), .in_b(b0_9to1_9), .out_a(a1_9to1_10), .out_b(b1_9to2_9), .out_c(matrixC1_9)); +processing_element pe1_10(.reset(effective_rst), .clk(clk), .in_a(a1_9to1_10), .in_b(b0_10to1_10), .out_a(a1_10to1_11), .out_b(b1_10to2_10), .out_c(matrixC1_10)); +processing_element pe1_11(.reset(effective_rst), .clk(clk), .in_a(a1_10to1_11), .in_b(b0_11to1_11), .out_a(a1_11to1_12), .out_b(b1_11to2_11), .out_c(matrixC1_11)); +processing_element pe1_12(.reset(effective_rst), .clk(clk), .in_a(a1_11to1_12), .in_b(b0_12to1_12), .out_a(a1_12to1_13), .out_b(b1_12to2_12), .out_c(matrixC1_12)); +processing_element pe1_13(.reset(effective_rst), .clk(clk), .in_a(a1_12to1_13), .in_b(b0_13to1_13), .out_a(a1_13to1_14), .out_b(b1_13to2_13), .out_c(matrixC1_13)); +processing_element pe1_14(.reset(effective_rst), .clk(clk), .in_a(a1_13to1_14), .in_b(b0_14to1_14), .out_a(a1_14to1_15), .out_b(b1_14to2_14), .out_c(matrixC1_14)); +processing_element pe1_15(.reset(effective_rst), .clk(clk), .in_a(a1_14to1_15), .in_b(b0_15to1_15), .out_a(a1_15to1_16), .out_b(b1_15to2_15), .out_c(matrixC1_15)); +processing_element pe2_1(.reset(effective_rst), .clk(clk), .in_a(a2_0to2_1), .in_b(b1_1to2_1), .out_a(a2_1to2_2), .out_b(b2_1to3_1), .out_c(matrixC2_1)); +processing_element pe2_2(.reset(effective_rst), .clk(clk), .in_a(a2_1to2_2), .in_b(b1_2to2_2), .out_a(a2_2to2_3), .out_b(b2_2to3_2), .out_c(matrixC2_2)); +processing_element pe2_3(.reset(effective_rst), .clk(clk), .in_a(a2_2to2_3), .in_b(b1_3to2_3), .out_a(a2_3to2_4), .out_b(b2_3to3_3), .out_c(matrixC2_3)); +processing_element pe2_4(.reset(effective_rst), .clk(clk), .in_a(a2_3to2_4), .in_b(b1_4to2_4), .out_a(a2_4to2_5), .out_b(b2_4to3_4), .out_c(matrixC2_4)); +processing_element pe2_5(.reset(effective_rst), .clk(clk), .in_a(a2_4to2_5), .in_b(b1_5to2_5), .out_a(a2_5to2_6), .out_b(b2_5to3_5), .out_c(matrixC2_5)); +processing_element pe2_6(.reset(effective_rst), .clk(clk), .in_a(a2_5to2_6), .in_b(b1_6to2_6), .out_a(a2_6to2_7), .out_b(b2_6to3_6), .out_c(matrixC2_6)); +processing_element pe2_7(.reset(effective_rst), .clk(clk), .in_a(a2_6to2_7), .in_b(b1_7to2_7), .out_a(a2_7to2_8), .out_b(b2_7to3_7), .out_c(matrixC2_7)); +processing_element pe2_8(.reset(effective_rst), .clk(clk), .in_a(a2_7to2_8), .in_b(b1_8to2_8), .out_a(a2_8to2_9), .out_b(b2_8to3_8), .out_c(matrixC2_8)); +processing_element pe2_9(.reset(effective_rst), .clk(clk), .in_a(a2_8to2_9), .in_b(b1_9to2_9), .out_a(a2_9to2_10), .out_b(b2_9to3_9), .out_c(matrixC2_9)); +processing_element pe2_10(.reset(effective_rst), .clk(clk), .in_a(a2_9to2_10), .in_b(b1_10to2_10), .out_a(a2_10to2_11), .out_b(b2_10to3_10), .out_c(matrixC2_10)); +processing_element pe2_11(.reset(effective_rst), .clk(clk), .in_a(a2_10to2_11), .in_b(b1_11to2_11), .out_a(a2_11to2_12), .out_b(b2_11to3_11), .out_c(matrixC2_11)); +processing_element pe2_12(.reset(effective_rst), .clk(clk), .in_a(a2_11to2_12), .in_b(b1_12to2_12), .out_a(a2_12to2_13), .out_b(b2_12to3_12), .out_c(matrixC2_12)); +processing_element pe2_13(.reset(effective_rst), .clk(clk), .in_a(a2_12to2_13), .in_b(b1_13to2_13), .out_a(a2_13to2_14), .out_b(b2_13to3_13), .out_c(matrixC2_13)); +processing_element pe2_14(.reset(effective_rst), .clk(clk), .in_a(a2_13to2_14), .in_b(b1_14to2_14), .out_a(a2_14to2_15), .out_b(b2_14to3_14), .out_c(matrixC2_14)); +processing_element pe2_15(.reset(effective_rst), .clk(clk), .in_a(a2_14to2_15), .in_b(b1_15to2_15), .out_a(a2_15to2_16), .out_b(b2_15to3_15), .out_c(matrixC2_15)); +processing_element pe3_1(.reset(effective_rst), .clk(clk), .in_a(a3_0to3_1), .in_b(b2_1to3_1), .out_a(a3_1to3_2), .out_b(b3_1to4_1), .out_c(matrixC3_1)); +processing_element pe3_2(.reset(effective_rst), .clk(clk), .in_a(a3_1to3_2), .in_b(b2_2to3_2), .out_a(a3_2to3_3), .out_b(b3_2to4_2), .out_c(matrixC3_2)); +processing_element pe3_3(.reset(effective_rst), .clk(clk), .in_a(a3_2to3_3), .in_b(b2_3to3_3), .out_a(a3_3to3_4), .out_b(b3_3to4_3), .out_c(matrixC3_3)); +processing_element pe3_4(.reset(effective_rst), .clk(clk), .in_a(a3_3to3_4), .in_b(b2_4to3_4), .out_a(a3_4to3_5), .out_b(b3_4to4_4), .out_c(matrixC3_4)); +processing_element pe3_5(.reset(effective_rst), .clk(clk), .in_a(a3_4to3_5), .in_b(b2_5to3_5), .out_a(a3_5to3_6), .out_b(b3_5to4_5), .out_c(matrixC3_5)); +processing_element pe3_6(.reset(effective_rst), .clk(clk), .in_a(a3_5to3_6), .in_b(b2_6to3_6), .out_a(a3_6to3_7), .out_b(b3_6to4_6), .out_c(matrixC3_6)); +processing_element pe3_7(.reset(effective_rst), .clk(clk), .in_a(a3_6to3_7), .in_b(b2_7to3_7), .out_a(a3_7to3_8), .out_b(b3_7to4_7), .out_c(matrixC3_7)); +processing_element pe3_8(.reset(effective_rst), .clk(clk), .in_a(a3_7to3_8), .in_b(b2_8to3_8), .out_a(a3_8to3_9), .out_b(b3_8to4_8), .out_c(matrixC3_8)); +processing_element pe3_9(.reset(effective_rst), .clk(clk), .in_a(a3_8to3_9), .in_b(b2_9to3_9), .out_a(a3_9to3_10), .out_b(b3_9to4_9), .out_c(matrixC3_9)); +processing_element pe3_10(.reset(effective_rst), .clk(clk), .in_a(a3_9to3_10), .in_b(b2_10to3_10), .out_a(a3_10to3_11), .out_b(b3_10to4_10), .out_c(matrixC3_10)); +processing_element pe3_11(.reset(effective_rst), .clk(clk), .in_a(a3_10to3_11), .in_b(b2_11to3_11), .out_a(a3_11to3_12), .out_b(b3_11to4_11), .out_c(matrixC3_11)); +processing_element pe3_12(.reset(effective_rst), .clk(clk), .in_a(a3_11to3_12), .in_b(b2_12to3_12), .out_a(a3_12to3_13), .out_b(b3_12to4_12), .out_c(matrixC3_12)); +processing_element pe3_13(.reset(effective_rst), .clk(clk), .in_a(a3_12to3_13), .in_b(b2_13to3_13), .out_a(a3_13to3_14), .out_b(b3_13to4_13), .out_c(matrixC3_13)); +processing_element pe3_14(.reset(effective_rst), .clk(clk), .in_a(a3_13to3_14), .in_b(b2_14to3_14), .out_a(a3_14to3_15), .out_b(b3_14to4_14), .out_c(matrixC3_14)); +processing_element pe3_15(.reset(effective_rst), .clk(clk), .in_a(a3_14to3_15), .in_b(b2_15to3_15), .out_a(a3_15to3_16), .out_b(b3_15to4_15), .out_c(matrixC3_15)); +processing_element pe4_1(.reset(effective_rst), .clk(clk), .in_a(a4_0to4_1), .in_b(b3_1to4_1), .out_a(a4_1to4_2), .out_b(b4_1to5_1), .out_c(matrixC4_1)); +processing_element pe4_2(.reset(effective_rst), .clk(clk), .in_a(a4_1to4_2), .in_b(b3_2to4_2), .out_a(a4_2to4_3), .out_b(b4_2to5_2), .out_c(matrixC4_2)); +processing_element pe4_3(.reset(effective_rst), .clk(clk), .in_a(a4_2to4_3), .in_b(b3_3to4_3), .out_a(a4_3to4_4), .out_b(b4_3to5_3), .out_c(matrixC4_3)); +processing_element pe4_4(.reset(effective_rst), .clk(clk), .in_a(a4_3to4_4), .in_b(b3_4to4_4), .out_a(a4_4to4_5), .out_b(b4_4to5_4), .out_c(matrixC4_4)); +processing_element pe4_5(.reset(effective_rst), .clk(clk), .in_a(a4_4to4_5), .in_b(b3_5to4_5), .out_a(a4_5to4_6), .out_b(b4_5to5_5), .out_c(matrixC4_5)); +processing_element pe4_6(.reset(effective_rst), .clk(clk), .in_a(a4_5to4_6), .in_b(b3_6to4_6), .out_a(a4_6to4_7), .out_b(b4_6to5_6), .out_c(matrixC4_6)); +processing_element pe4_7(.reset(effective_rst), .clk(clk), .in_a(a4_6to4_7), .in_b(b3_7to4_7), .out_a(a4_7to4_8), .out_b(b4_7to5_7), .out_c(matrixC4_7)); +processing_element pe4_8(.reset(effective_rst), .clk(clk), .in_a(a4_7to4_8), .in_b(b3_8to4_8), .out_a(a4_8to4_9), .out_b(b4_8to5_8), .out_c(matrixC4_8)); +processing_element pe4_9(.reset(effective_rst), .clk(clk), .in_a(a4_8to4_9), .in_b(b3_9to4_9), .out_a(a4_9to4_10), .out_b(b4_9to5_9), .out_c(matrixC4_9)); +processing_element pe4_10(.reset(effective_rst), .clk(clk), .in_a(a4_9to4_10), .in_b(b3_10to4_10), .out_a(a4_10to4_11), .out_b(b4_10to5_10), .out_c(matrixC4_10)); +processing_element pe4_11(.reset(effective_rst), .clk(clk), .in_a(a4_10to4_11), .in_b(b3_11to4_11), .out_a(a4_11to4_12), .out_b(b4_11to5_11), .out_c(matrixC4_11)); +processing_element pe4_12(.reset(effective_rst), .clk(clk), .in_a(a4_11to4_12), .in_b(b3_12to4_12), .out_a(a4_12to4_13), .out_b(b4_12to5_12), .out_c(matrixC4_12)); +processing_element pe4_13(.reset(effective_rst), .clk(clk), .in_a(a4_12to4_13), .in_b(b3_13to4_13), .out_a(a4_13to4_14), .out_b(b4_13to5_13), .out_c(matrixC4_13)); +processing_element pe4_14(.reset(effective_rst), .clk(clk), .in_a(a4_13to4_14), .in_b(b3_14to4_14), .out_a(a4_14to4_15), .out_b(b4_14to5_14), .out_c(matrixC4_14)); +processing_element pe4_15(.reset(effective_rst), .clk(clk), .in_a(a4_14to4_15), .in_b(b3_15to4_15), .out_a(a4_15to4_16), .out_b(b4_15to5_15), .out_c(matrixC4_15)); +processing_element pe5_1(.reset(effective_rst), .clk(clk), .in_a(a5_0to5_1), .in_b(b4_1to5_1), .out_a(a5_1to5_2), .out_b(b5_1to6_1), .out_c(matrixC5_1)); +processing_element pe5_2(.reset(effective_rst), .clk(clk), .in_a(a5_1to5_2), .in_b(b4_2to5_2), .out_a(a5_2to5_3), .out_b(b5_2to6_2), .out_c(matrixC5_2)); +processing_element pe5_3(.reset(effective_rst), .clk(clk), .in_a(a5_2to5_3), .in_b(b4_3to5_3), .out_a(a5_3to5_4), .out_b(b5_3to6_3), .out_c(matrixC5_3)); +processing_element pe5_4(.reset(effective_rst), .clk(clk), .in_a(a5_3to5_4), .in_b(b4_4to5_4), .out_a(a5_4to5_5), .out_b(b5_4to6_4), .out_c(matrixC5_4)); +processing_element pe5_5(.reset(effective_rst), .clk(clk), .in_a(a5_4to5_5), .in_b(b4_5to5_5), .out_a(a5_5to5_6), .out_b(b5_5to6_5), .out_c(matrixC5_5)); +processing_element pe5_6(.reset(effective_rst), .clk(clk), .in_a(a5_5to5_6), .in_b(b4_6to5_6), .out_a(a5_6to5_7), .out_b(b5_6to6_6), .out_c(matrixC5_6)); +processing_element pe5_7(.reset(effective_rst), .clk(clk), .in_a(a5_6to5_7), .in_b(b4_7to5_7), .out_a(a5_7to5_8), .out_b(b5_7to6_7), .out_c(matrixC5_7)); +processing_element pe5_8(.reset(effective_rst), .clk(clk), .in_a(a5_7to5_8), .in_b(b4_8to5_8), .out_a(a5_8to5_9), .out_b(b5_8to6_8), .out_c(matrixC5_8)); +processing_element pe5_9(.reset(effective_rst), .clk(clk), .in_a(a5_8to5_9), .in_b(b4_9to5_9), .out_a(a5_9to5_10), .out_b(b5_9to6_9), .out_c(matrixC5_9)); +processing_element pe5_10(.reset(effective_rst), .clk(clk), .in_a(a5_9to5_10), .in_b(b4_10to5_10), .out_a(a5_10to5_11), .out_b(b5_10to6_10), .out_c(matrixC5_10)); +processing_element pe5_11(.reset(effective_rst), .clk(clk), .in_a(a5_10to5_11), .in_b(b4_11to5_11), .out_a(a5_11to5_12), .out_b(b5_11to6_11), .out_c(matrixC5_11)); +processing_element pe5_12(.reset(effective_rst), .clk(clk), .in_a(a5_11to5_12), .in_b(b4_12to5_12), .out_a(a5_12to5_13), .out_b(b5_12to6_12), .out_c(matrixC5_12)); +processing_element pe5_13(.reset(effective_rst), .clk(clk), .in_a(a5_12to5_13), .in_b(b4_13to5_13), .out_a(a5_13to5_14), .out_b(b5_13to6_13), .out_c(matrixC5_13)); +processing_element pe5_14(.reset(effective_rst), .clk(clk), .in_a(a5_13to5_14), .in_b(b4_14to5_14), .out_a(a5_14to5_15), .out_b(b5_14to6_14), .out_c(matrixC5_14)); +processing_element pe5_15(.reset(effective_rst), .clk(clk), .in_a(a5_14to5_15), .in_b(b4_15to5_15), .out_a(a5_15to5_16), .out_b(b5_15to6_15), .out_c(matrixC5_15)); +processing_element pe6_1(.reset(effective_rst), .clk(clk), .in_a(a6_0to6_1), .in_b(b5_1to6_1), .out_a(a6_1to6_2), .out_b(b6_1to7_1), .out_c(matrixC6_1)); +processing_element pe6_2(.reset(effective_rst), .clk(clk), .in_a(a6_1to6_2), .in_b(b5_2to6_2), .out_a(a6_2to6_3), .out_b(b6_2to7_2), .out_c(matrixC6_2)); +processing_element pe6_3(.reset(effective_rst), .clk(clk), .in_a(a6_2to6_3), .in_b(b5_3to6_3), .out_a(a6_3to6_4), .out_b(b6_3to7_3), .out_c(matrixC6_3)); +processing_element pe6_4(.reset(effective_rst), .clk(clk), .in_a(a6_3to6_4), .in_b(b5_4to6_4), .out_a(a6_4to6_5), .out_b(b6_4to7_4), .out_c(matrixC6_4)); +processing_element pe6_5(.reset(effective_rst), .clk(clk), .in_a(a6_4to6_5), .in_b(b5_5to6_5), .out_a(a6_5to6_6), .out_b(b6_5to7_5), .out_c(matrixC6_5)); +processing_element pe6_6(.reset(effective_rst), .clk(clk), .in_a(a6_5to6_6), .in_b(b5_6to6_6), .out_a(a6_6to6_7), .out_b(b6_6to7_6), .out_c(matrixC6_6)); +processing_element pe6_7(.reset(effective_rst), .clk(clk), .in_a(a6_6to6_7), .in_b(b5_7to6_7), .out_a(a6_7to6_8), .out_b(b6_7to7_7), .out_c(matrixC6_7)); +processing_element pe6_8(.reset(effective_rst), .clk(clk), .in_a(a6_7to6_8), .in_b(b5_8to6_8), .out_a(a6_8to6_9), .out_b(b6_8to7_8), .out_c(matrixC6_8)); +processing_element pe6_9(.reset(effective_rst), .clk(clk), .in_a(a6_8to6_9), .in_b(b5_9to6_9), .out_a(a6_9to6_10), .out_b(b6_9to7_9), .out_c(matrixC6_9)); +processing_element pe6_10(.reset(effective_rst), .clk(clk), .in_a(a6_9to6_10), .in_b(b5_10to6_10), .out_a(a6_10to6_11), .out_b(b6_10to7_10), .out_c(matrixC6_10)); +processing_element pe6_11(.reset(effective_rst), .clk(clk), .in_a(a6_10to6_11), .in_b(b5_11to6_11), .out_a(a6_11to6_12), .out_b(b6_11to7_11), .out_c(matrixC6_11)); +processing_element pe6_12(.reset(effective_rst), .clk(clk), .in_a(a6_11to6_12), .in_b(b5_12to6_12), .out_a(a6_12to6_13), .out_b(b6_12to7_12), .out_c(matrixC6_12)); +processing_element pe6_13(.reset(effective_rst), .clk(clk), .in_a(a6_12to6_13), .in_b(b5_13to6_13), .out_a(a6_13to6_14), .out_b(b6_13to7_13), .out_c(matrixC6_13)); +processing_element pe6_14(.reset(effective_rst), .clk(clk), .in_a(a6_13to6_14), .in_b(b5_14to6_14), .out_a(a6_14to6_15), .out_b(b6_14to7_14), .out_c(matrixC6_14)); +processing_element pe6_15(.reset(effective_rst), .clk(clk), .in_a(a6_14to6_15), .in_b(b5_15to6_15), .out_a(a6_15to6_16), .out_b(b6_15to7_15), .out_c(matrixC6_15)); +processing_element pe7_1(.reset(effective_rst), .clk(clk), .in_a(a7_0to7_1), .in_b(b6_1to7_1), .out_a(a7_1to7_2), .out_b(b7_1to8_1), .out_c(matrixC7_1)); +processing_element pe7_2(.reset(effective_rst), .clk(clk), .in_a(a7_1to7_2), .in_b(b6_2to7_2), .out_a(a7_2to7_3), .out_b(b7_2to8_2), .out_c(matrixC7_2)); +processing_element pe7_3(.reset(effective_rst), .clk(clk), .in_a(a7_2to7_3), .in_b(b6_3to7_3), .out_a(a7_3to7_4), .out_b(b7_3to8_3), .out_c(matrixC7_3)); +processing_element pe7_4(.reset(effective_rst), .clk(clk), .in_a(a7_3to7_4), .in_b(b6_4to7_4), .out_a(a7_4to7_5), .out_b(b7_4to8_4), .out_c(matrixC7_4)); +processing_element pe7_5(.reset(effective_rst), .clk(clk), .in_a(a7_4to7_5), .in_b(b6_5to7_5), .out_a(a7_5to7_6), .out_b(b7_5to8_5), .out_c(matrixC7_5)); +processing_element pe7_6(.reset(effective_rst), .clk(clk), .in_a(a7_5to7_6), .in_b(b6_6to7_6), .out_a(a7_6to7_7), .out_b(b7_6to8_6), .out_c(matrixC7_6)); +processing_element pe7_7(.reset(effective_rst), .clk(clk), .in_a(a7_6to7_7), .in_b(b6_7to7_7), .out_a(a7_7to7_8), .out_b(b7_7to8_7), .out_c(matrixC7_7)); +processing_element pe7_8(.reset(effective_rst), .clk(clk), .in_a(a7_7to7_8), .in_b(b6_8to7_8), .out_a(a7_8to7_9), .out_b(b7_8to8_8), .out_c(matrixC7_8)); +processing_element pe7_9(.reset(effective_rst), .clk(clk), .in_a(a7_8to7_9), .in_b(b6_9to7_9), .out_a(a7_9to7_10), .out_b(b7_9to8_9), .out_c(matrixC7_9)); +processing_element pe7_10(.reset(effective_rst), .clk(clk), .in_a(a7_9to7_10), .in_b(b6_10to7_10), .out_a(a7_10to7_11), .out_b(b7_10to8_10), .out_c(matrixC7_10)); +processing_element pe7_11(.reset(effective_rst), .clk(clk), .in_a(a7_10to7_11), .in_b(b6_11to7_11), .out_a(a7_11to7_12), .out_b(b7_11to8_11), .out_c(matrixC7_11)); +processing_element pe7_12(.reset(effective_rst), .clk(clk), .in_a(a7_11to7_12), .in_b(b6_12to7_12), .out_a(a7_12to7_13), .out_b(b7_12to8_12), .out_c(matrixC7_12)); +processing_element pe7_13(.reset(effective_rst), .clk(clk), .in_a(a7_12to7_13), .in_b(b6_13to7_13), .out_a(a7_13to7_14), .out_b(b7_13to8_13), .out_c(matrixC7_13)); +processing_element pe7_14(.reset(effective_rst), .clk(clk), .in_a(a7_13to7_14), .in_b(b6_14to7_14), .out_a(a7_14to7_15), .out_b(b7_14to8_14), .out_c(matrixC7_14)); +processing_element pe7_15(.reset(effective_rst), .clk(clk), .in_a(a7_14to7_15), .in_b(b6_15to7_15), .out_a(a7_15to7_16), .out_b(b7_15to8_15), .out_c(matrixC7_15)); +processing_element pe8_1(.reset(effective_rst), .clk(clk), .in_a(a8_0to8_1), .in_b(b7_1to8_1), .out_a(a8_1to8_2), .out_b(b8_1to9_1), .out_c(matrixC8_1)); +processing_element pe8_2(.reset(effective_rst), .clk(clk), .in_a(a8_1to8_2), .in_b(b7_2to8_2), .out_a(a8_2to8_3), .out_b(b8_2to9_2), .out_c(matrixC8_2)); +processing_element pe8_3(.reset(effective_rst), .clk(clk), .in_a(a8_2to8_3), .in_b(b7_3to8_3), .out_a(a8_3to8_4), .out_b(b8_3to9_3), .out_c(matrixC8_3)); +processing_element pe8_4(.reset(effective_rst), .clk(clk), .in_a(a8_3to8_4), .in_b(b7_4to8_4), .out_a(a8_4to8_5), .out_b(b8_4to9_4), .out_c(matrixC8_4)); +processing_element pe8_5(.reset(effective_rst), .clk(clk), .in_a(a8_4to8_5), .in_b(b7_5to8_5), .out_a(a8_5to8_6), .out_b(b8_5to9_5), .out_c(matrixC8_5)); +processing_element pe8_6(.reset(effective_rst), .clk(clk), .in_a(a8_5to8_6), .in_b(b7_6to8_6), .out_a(a8_6to8_7), .out_b(b8_6to9_6), .out_c(matrixC8_6)); +processing_element pe8_7(.reset(effective_rst), .clk(clk), .in_a(a8_6to8_7), .in_b(b7_7to8_7), .out_a(a8_7to8_8), .out_b(b8_7to9_7), .out_c(matrixC8_7)); +processing_element pe8_8(.reset(effective_rst), .clk(clk), .in_a(a8_7to8_8), .in_b(b7_8to8_8), .out_a(a8_8to8_9), .out_b(b8_8to9_8), .out_c(matrixC8_8)); +processing_element pe8_9(.reset(effective_rst), .clk(clk), .in_a(a8_8to8_9), .in_b(b7_9to8_9), .out_a(a8_9to8_10), .out_b(b8_9to9_9), .out_c(matrixC8_9)); +processing_element pe8_10(.reset(effective_rst), .clk(clk), .in_a(a8_9to8_10), .in_b(b7_10to8_10), .out_a(a8_10to8_11), .out_b(b8_10to9_10), .out_c(matrixC8_10)); +processing_element pe8_11(.reset(effective_rst), .clk(clk), .in_a(a8_10to8_11), .in_b(b7_11to8_11), .out_a(a8_11to8_12), .out_b(b8_11to9_11), .out_c(matrixC8_11)); +processing_element pe8_12(.reset(effective_rst), .clk(clk), .in_a(a8_11to8_12), .in_b(b7_12to8_12), .out_a(a8_12to8_13), .out_b(b8_12to9_12), .out_c(matrixC8_12)); +processing_element pe8_13(.reset(effective_rst), .clk(clk), .in_a(a8_12to8_13), .in_b(b7_13to8_13), .out_a(a8_13to8_14), .out_b(b8_13to9_13), .out_c(matrixC8_13)); +processing_element pe8_14(.reset(effective_rst), .clk(clk), .in_a(a8_13to8_14), .in_b(b7_14to8_14), .out_a(a8_14to8_15), .out_b(b8_14to9_14), .out_c(matrixC8_14)); +processing_element pe8_15(.reset(effective_rst), .clk(clk), .in_a(a8_14to8_15), .in_b(b7_15to8_15), .out_a(a8_15to8_16), .out_b(b8_15to9_15), .out_c(matrixC8_15)); +processing_element pe9_1(.reset(effective_rst), .clk(clk), .in_a(a9_0to9_1), .in_b(b8_1to9_1), .out_a(a9_1to9_2), .out_b(b9_1to10_1), .out_c(matrixC9_1)); +processing_element pe9_2(.reset(effective_rst), .clk(clk), .in_a(a9_1to9_2), .in_b(b8_2to9_2), .out_a(a9_2to9_3), .out_b(b9_2to10_2), .out_c(matrixC9_2)); +processing_element pe9_3(.reset(effective_rst), .clk(clk), .in_a(a9_2to9_3), .in_b(b8_3to9_3), .out_a(a9_3to9_4), .out_b(b9_3to10_3), .out_c(matrixC9_3)); +processing_element pe9_4(.reset(effective_rst), .clk(clk), .in_a(a9_3to9_4), .in_b(b8_4to9_4), .out_a(a9_4to9_5), .out_b(b9_4to10_4), .out_c(matrixC9_4)); +processing_element pe9_5(.reset(effective_rst), .clk(clk), .in_a(a9_4to9_5), .in_b(b8_5to9_5), .out_a(a9_5to9_6), .out_b(b9_5to10_5), .out_c(matrixC9_5)); +processing_element pe9_6(.reset(effective_rst), .clk(clk), .in_a(a9_5to9_6), .in_b(b8_6to9_6), .out_a(a9_6to9_7), .out_b(b9_6to10_6), .out_c(matrixC9_6)); +processing_element pe9_7(.reset(effective_rst), .clk(clk), .in_a(a9_6to9_7), .in_b(b8_7to9_7), .out_a(a9_7to9_8), .out_b(b9_7to10_7), .out_c(matrixC9_7)); +processing_element pe9_8(.reset(effective_rst), .clk(clk), .in_a(a9_7to9_8), .in_b(b8_8to9_8), .out_a(a9_8to9_9), .out_b(b9_8to10_8), .out_c(matrixC9_8)); +processing_element pe9_9(.reset(effective_rst), .clk(clk), .in_a(a9_8to9_9), .in_b(b8_9to9_9), .out_a(a9_9to9_10), .out_b(b9_9to10_9), .out_c(matrixC9_9)); +processing_element pe9_10(.reset(effective_rst), .clk(clk), .in_a(a9_9to9_10), .in_b(b8_10to9_10), .out_a(a9_10to9_11), .out_b(b9_10to10_10), .out_c(matrixC9_10)); +processing_element pe9_11(.reset(effective_rst), .clk(clk), .in_a(a9_10to9_11), .in_b(b8_11to9_11), .out_a(a9_11to9_12), .out_b(b9_11to10_11), .out_c(matrixC9_11)); +processing_element pe9_12(.reset(effective_rst), .clk(clk), .in_a(a9_11to9_12), .in_b(b8_12to9_12), .out_a(a9_12to9_13), .out_b(b9_12to10_12), .out_c(matrixC9_12)); +processing_element pe9_13(.reset(effective_rst), .clk(clk), .in_a(a9_12to9_13), .in_b(b8_13to9_13), .out_a(a9_13to9_14), .out_b(b9_13to10_13), .out_c(matrixC9_13)); +processing_element pe9_14(.reset(effective_rst), .clk(clk), .in_a(a9_13to9_14), .in_b(b8_14to9_14), .out_a(a9_14to9_15), .out_b(b9_14to10_14), .out_c(matrixC9_14)); +processing_element pe9_15(.reset(effective_rst), .clk(clk), .in_a(a9_14to9_15), .in_b(b8_15to9_15), .out_a(a9_15to9_16), .out_b(b9_15to10_15), .out_c(matrixC9_15)); +processing_element pe10_1(.reset(effective_rst), .clk(clk), .in_a(a10_0to10_1), .in_b(b9_1to10_1), .out_a(a10_1to10_2), .out_b(b10_1to11_1), .out_c(matrixC10_1)); +processing_element pe10_2(.reset(effective_rst), .clk(clk), .in_a(a10_1to10_2), .in_b(b9_2to10_2), .out_a(a10_2to10_3), .out_b(b10_2to11_2), .out_c(matrixC10_2)); +processing_element pe10_3(.reset(effective_rst), .clk(clk), .in_a(a10_2to10_3), .in_b(b9_3to10_3), .out_a(a10_3to10_4), .out_b(b10_3to11_3), .out_c(matrixC10_3)); +processing_element pe10_4(.reset(effective_rst), .clk(clk), .in_a(a10_3to10_4), .in_b(b9_4to10_4), .out_a(a10_4to10_5), .out_b(b10_4to11_4), .out_c(matrixC10_4)); +processing_element pe10_5(.reset(effective_rst), .clk(clk), .in_a(a10_4to10_5), .in_b(b9_5to10_5), .out_a(a10_5to10_6), .out_b(b10_5to11_5), .out_c(matrixC10_5)); +processing_element pe10_6(.reset(effective_rst), .clk(clk), .in_a(a10_5to10_6), .in_b(b9_6to10_6), .out_a(a10_6to10_7), .out_b(b10_6to11_6), .out_c(matrixC10_6)); +processing_element pe10_7(.reset(effective_rst), .clk(clk), .in_a(a10_6to10_7), .in_b(b9_7to10_7), .out_a(a10_7to10_8), .out_b(b10_7to11_7), .out_c(matrixC10_7)); +processing_element pe10_8(.reset(effective_rst), .clk(clk), .in_a(a10_7to10_8), .in_b(b9_8to10_8), .out_a(a10_8to10_9), .out_b(b10_8to11_8), .out_c(matrixC10_8)); +processing_element pe10_9(.reset(effective_rst), .clk(clk), .in_a(a10_8to10_9), .in_b(b9_9to10_9), .out_a(a10_9to10_10), .out_b(b10_9to11_9), .out_c(matrixC10_9)); +processing_element pe10_10(.reset(effective_rst), .clk(clk), .in_a(a10_9to10_10), .in_b(b9_10to10_10), .out_a(a10_10to10_11), .out_b(b10_10to11_10), .out_c(matrixC10_10)); +processing_element pe10_11(.reset(effective_rst), .clk(clk), .in_a(a10_10to10_11), .in_b(b9_11to10_11), .out_a(a10_11to10_12), .out_b(b10_11to11_11), .out_c(matrixC10_11)); +processing_element pe10_12(.reset(effective_rst), .clk(clk), .in_a(a10_11to10_12), .in_b(b9_12to10_12), .out_a(a10_12to10_13), .out_b(b10_12to11_12), .out_c(matrixC10_12)); +processing_element pe10_13(.reset(effective_rst), .clk(clk), .in_a(a10_12to10_13), .in_b(b9_13to10_13), .out_a(a10_13to10_14), .out_b(b10_13to11_13), .out_c(matrixC10_13)); +processing_element pe10_14(.reset(effective_rst), .clk(clk), .in_a(a10_13to10_14), .in_b(b9_14to10_14), .out_a(a10_14to10_15), .out_b(b10_14to11_14), .out_c(matrixC10_14)); +processing_element pe10_15(.reset(effective_rst), .clk(clk), .in_a(a10_14to10_15), .in_b(b9_15to10_15), .out_a(a10_15to10_16), .out_b(b10_15to11_15), .out_c(matrixC10_15)); +processing_element pe11_1(.reset(effective_rst), .clk(clk), .in_a(a11_0to11_1), .in_b(b10_1to11_1), .out_a(a11_1to11_2), .out_b(b11_1to12_1), .out_c(matrixC11_1)); +processing_element pe11_2(.reset(effective_rst), .clk(clk), .in_a(a11_1to11_2), .in_b(b10_2to11_2), .out_a(a11_2to11_3), .out_b(b11_2to12_2), .out_c(matrixC11_2)); +processing_element pe11_3(.reset(effective_rst), .clk(clk), .in_a(a11_2to11_3), .in_b(b10_3to11_3), .out_a(a11_3to11_4), .out_b(b11_3to12_3), .out_c(matrixC11_3)); +processing_element pe11_4(.reset(effective_rst), .clk(clk), .in_a(a11_3to11_4), .in_b(b10_4to11_4), .out_a(a11_4to11_5), .out_b(b11_4to12_4), .out_c(matrixC11_4)); +processing_element pe11_5(.reset(effective_rst), .clk(clk), .in_a(a11_4to11_5), .in_b(b10_5to11_5), .out_a(a11_5to11_6), .out_b(b11_5to12_5), .out_c(matrixC11_5)); +processing_element pe11_6(.reset(effective_rst), .clk(clk), .in_a(a11_5to11_6), .in_b(b10_6to11_6), .out_a(a11_6to11_7), .out_b(b11_6to12_6), .out_c(matrixC11_6)); +processing_element pe11_7(.reset(effective_rst), .clk(clk), .in_a(a11_6to11_7), .in_b(b10_7to11_7), .out_a(a11_7to11_8), .out_b(b11_7to12_7), .out_c(matrixC11_7)); +processing_element pe11_8(.reset(effective_rst), .clk(clk), .in_a(a11_7to11_8), .in_b(b10_8to11_8), .out_a(a11_8to11_9), .out_b(b11_8to12_8), .out_c(matrixC11_8)); +processing_element pe11_9(.reset(effective_rst), .clk(clk), .in_a(a11_8to11_9), .in_b(b10_9to11_9), .out_a(a11_9to11_10), .out_b(b11_9to12_9), .out_c(matrixC11_9)); +processing_element pe11_10(.reset(effective_rst), .clk(clk), .in_a(a11_9to11_10), .in_b(b10_10to11_10), .out_a(a11_10to11_11), .out_b(b11_10to12_10), .out_c(matrixC11_10)); +processing_element pe11_11(.reset(effective_rst), .clk(clk), .in_a(a11_10to11_11), .in_b(b10_11to11_11), .out_a(a11_11to11_12), .out_b(b11_11to12_11), .out_c(matrixC11_11)); +processing_element pe11_12(.reset(effective_rst), .clk(clk), .in_a(a11_11to11_12), .in_b(b10_12to11_12), .out_a(a11_12to11_13), .out_b(b11_12to12_12), .out_c(matrixC11_12)); +processing_element pe11_13(.reset(effective_rst), .clk(clk), .in_a(a11_12to11_13), .in_b(b10_13to11_13), .out_a(a11_13to11_14), .out_b(b11_13to12_13), .out_c(matrixC11_13)); +processing_element pe11_14(.reset(effective_rst), .clk(clk), .in_a(a11_13to11_14), .in_b(b10_14to11_14), .out_a(a11_14to11_15), .out_b(b11_14to12_14), .out_c(matrixC11_14)); +processing_element pe11_15(.reset(effective_rst), .clk(clk), .in_a(a11_14to11_15), .in_b(b10_15to11_15), .out_a(a11_15to11_16), .out_b(b11_15to12_15), .out_c(matrixC11_15)); +processing_element pe12_1(.reset(effective_rst), .clk(clk), .in_a(a12_0to12_1), .in_b(b11_1to12_1), .out_a(a12_1to12_2), .out_b(b12_1to13_1), .out_c(matrixC12_1)); +processing_element pe12_2(.reset(effective_rst), .clk(clk), .in_a(a12_1to12_2), .in_b(b11_2to12_2), .out_a(a12_2to12_3), .out_b(b12_2to13_2), .out_c(matrixC12_2)); +processing_element pe12_3(.reset(effective_rst), .clk(clk), .in_a(a12_2to12_3), .in_b(b11_3to12_3), .out_a(a12_3to12_4), .out_b(b12_3to13_3), .out_c(matrixC12_3)); +processing_element pe12_4(.reset(effective_rst), .clk(clk), .in_a(a12_3to12_4), .in_b(b11_4to12_4), .out_a(a12_4to12_5), .out_b(b12_4to13_4), .out_c(matrixC12_4)); +processing_element pe12_5(.reset(effective_rst), .clk(clk), .in_a(a12_4to12_5), .in_b(b11_5to12_5), .out_a(a12_5to12_6), .out_b(b12_5to13_5), .out_c(matrixC12_5)); +processing_element pe12_6(.reset(effective_rst), .clk(clk), .in_a(a12_5to12_6), .in_b(b11_6to12_6), .out_a(a12_6to12_7), .out_b(b12_6to13_6), .out_c(matrixC12_6)); +processing_element pe12_7(.reset(effective_rst), .clk(clk), .in_a(a12_6to12_7), .in_b(b11_7to12_7), .out_a(a12_7to12_8), .out_b(b12_7to13_7), .out_c(matrixC12_7)); +processing_element pe12_8(.reset(effective_rst), .clk(clk), .in_a(a12_7to12_8), .in_b(b11_8to12_8), .out_a(a12_8to12_9), .out_b(b12_8to13_8), .out_c(matrixC12_8)); +processing_element pe12_9(.reset(effective_rst), .clk(clk), .in_a(a12_8to12_9), .in_b(b11_9to12_9), .out_a(a12_9to12_10), .out_b(b12_9to13_9), .out_c(matrixC12_9)); +processing_element pe12_10(.reset(effective_rst), .clk(clk), .in_a(a12_9to12_10), .in_b(b11_10to12_10), .out_a(a12_10to12_11), .out_b(b12_10to13_10), .out_c(matrixC12_10)); +processing_element pe12_11(.reset(effective_rst), .clk(clk), .in_a(a12_10to12_11), .in_b(b11_11to12_11), .out_a(a12_11to12_12), .out_b(b12_11to13_11), .out_c(matrixC12_11)); +processing_element pe12_12(.reset(effective_rst), .clk(clk), .in_a(a12_11to12_12), .in_b(b11_12to12_12), .out_a(a12_12to12_13), .out_b(b12_12to13_12), .out_c(matrixC12_12)); +processing_element pe12_13(.reset(effective_rst), .clk(clk), .in_a(a12_12to12_13), .in_b(b11_13to12_13), .out_a(a12_13to12_14), .out_b(b12_13to13_13), .out_c(matrixC12_13)); +processing_element pe12_14(.reset(effective_rst), .clk(clk), .in_a(a12_13to12_14), .in_b(b11_14to12_14), .out_a(a12_14to12_15), .out_b(b12_14to13_14), .out_c(matrixC12_14)); +processing_element pe12_15(.reset(effective_rst), .clk(clk), .in_a(a12_14to12_15), .in_b(b11_15to12_15), .out_a(a12_15to12_16), .out_b(b12_15to13_15), .out_c(matrixC12_15)); +processing_element pe13_1(.reset(effective_rst), .clk(clk), .in_a(a13_0to13_1), .in_b(b12_1to13_1), .out_a(a13_1to13_2), .out_b(b13_1to14_1), .out_c(matrixC13_1)); +processing_element pe13_2(.reset(effective_rst), .clk(clk), .in_a(a13_1to13_2), .in_b(b12_2to13_2), .out_a(a13_2to13_3), .out_b(b13_2to14_2), .out_c(matrixC13_2)); +processing_element pe13_3(.reset(effective_rst), .clk(clk), .in_a(a13_2to13_3), .in_b(b12_3to13_3), .out_a(a13_3to13_4), .out_b(b13_3to14_3), .out_c(matrixC13_3)); +processing_element pe13_4(.reset(effective_rst), .clk(clk), .in_a(a13_3to13_4), .in_b(b12_4to13_4), .out_a(a13_4to13_5), .out_b(b13_4to14_4), .out_c(matrixC13_4)); +processing_element pe13_5(.reset(effective_rst), .clk(clk), .in_a(a13_4to13_5), .in_b(b12_5to13_5), .out_a(a13_5to13_6), .out_b(b13_5to14_5), .out_c(matrixC13_5)); +processing_element pe13_6(.reset(effective_rst), .clk(clk), .in_a(a13_5to13_6), .in_b(b12_6to13_6), .out_a(a13_6to13_7), .out_b(b13_6to14_6), .out_c(matrixC13_6)); +processing_element pe13_7(.reset(effective_rst), .clk(clk), .in_a(a13_6to13_7), .in_b(b12_7to13_7), .out_a(a13_7to13_8), .out_b(b13_7to14_7), .out_c(matrixC13_7)); +processing_element pe13_8(.reset(effective_rst), .clk(clk), .in_a(a13_7to13_8), .in_b(b12_8to13_8), .out_a(a13_8to13_9), .out_b(b13_8to14_8), .out_c(matrixC13_8)); +processing_element pe13_9(.reset(effective_rst), .clk(clk), .in_a(a13_8to13_9), .in_b(b12_9to13_9), .out_a(a13_9to13_10), .out_b(b13_9to14_9), .out_c(matrixC13_9)); +processing_element pe13_10(.reset(effective_rst), .clk(clk), .in_a(a13_9to13_10), .in_b(b12_10to13_10), .out_a(a13_10to13_11), .out_b(b13_10to14_10), .out_c(matrixC13_10)); +processing_element pe13_11(.reset(effective_rst), .clk(clk), .in_a(a13_10to13_11), .in_b(b12_11to13_11), .out_a(a13_11to13_12), .out_b(b13_11to14_11), .out_c(matrixC13_11)); +processing_element pe13_12(.reset(effective_rst), .clk(clk), .in_a(a13_11to13_12), .in_b(b12_12to13_12), .out_a(a13_12to13_13), .out_b(b13_12to14_12), .out_c(matrixC13_12)); +processing_element pe13_13(.reset(effective_rst), .clk(clk), .in_a(a13_12to13_13), .in_b(b12_13to13_13), .out_a(a13_13to13_14), .out_b(b13_13to14_13), .out_c(matrixC13_13)); +processing_element pe13_14(.reset(effective_rst), .clk(clk), .in_a(a13_13to13_14), .in_b(b12_14to13_14), .out_a(a13_14to13_15), .out_b(b13_14to14_14), .out_c(matrixC13_14)); +processing_element pe13_15(.reset(effective_rst), .clk(clk), .in_a(a13_14to13_15), .in_b(b12_15to13_15), .out_a(a13_15to13_16), .out_b(b13_15to14_15), .out_c(matrixC13_15)); +processing_element pe14_1(.reset(effective_rst), .clk(clk), .in_a(a14_0to14_1), .in_b(b13_1to14_1), .out_a(a14_1to14_2), .out_b(b14_1to15_1), .out_c(matrixC14_1)); +processing_element pe14_2(.reset(effective_rst), .clk(clk), .in_a(a14_1to14_2), .in_b(b13_2to14_2), .out_a(a14_2to14_3), .out_b(b14_2to15_2), .out_c(matrixC14_2)); +processing_element pe14_3(.reset(effective_rst), .clk(clk), .in_a(a14_2to14_3), .in_b(b13_3to14_3), .out_a(a14_3to14_4), .out_b(b14_3to15_3), .out_c(matrixC14_3)); +processing_element pe14_4(.reset(effective_rst), .clk(clk), .in_a(a14_3to14_4), .in_b(b13_4to14_4), .out_a(a14_4to14_5), .out_b(b14_4to15_4), .out_c(matrixC14_4)); +processing_element pe14_5(.reset(effective_rst), .clk(clk), .in_a(a14_4to14_5), .in_b(b13_5to14_5), .out_a(a14_5to14_6), .out_b(b14_5to15_5), .out_c(matrixC14_5)); +processing_element pe14_6(.reset(effective_rst), .clk(clk), .in_a(a14_5to14_6), .in_b(b13_6to14_6), .out_a(a14_6to14_7), .out_b(b14_6to15_6), .out_c(matrixC14_6)); +processing_element pe14_7(.reset(effective_rst), .clk(clk), .in_a(a14_6to14_7), .in_b(b13_7to14_7), .out_a(a14_7to14_8), .out_b(b14_7to15_7), .out_c(matrixC14_7)); +processing_element pe14_8(.reset(effective_rst), .clk(clk), .in_a(a14_7to14_8), .in_b(b13_8to14_8), .out_a(a14_8to14_9), .out_b(b14_8to15_8), .out_c(matrixC14_8)); +processing_element pe14_9(.reset(effective_rst), .clk(clk), .in_a(a14_8to14_9), .in_b(b13_9to14_9), .out_a(a14_9to14_10), .out_b(b14_9to15_9), .out_c(matrixC14_9)); +processing_element pe14_10(.reset(effective_rst), .clk(clk), .in_a(a14_9to14_10), .in_b(b13_10to14_10), .out_a(a14_10to14_11), .out_b(b14_10to15_10), .out_c(matrixC14_10)); +processing_element pe14_11(.reset(effective_rst), .clk(clk), .in_a(a14_10to14_11), .in_b(b13_11to14_11), .out_a(a14_11to14_12), .out_b(b14_11to15_11), .out_c(matrixC14_11)); +processing_element pe14_12(.reset(effective_rst), .clk(clk), .in_a(a14_11to14_12), .in_b(b13_12to14_12), .out_a(a14_12to14_13), .out_b(b14_12to15_12), .out_c(matrixC14_12)); +processing_element pe14_13(.reset(effective_rst), .clk(clk), .in_a(a14_12to14_13), .in_b(b13_13to14_13), .out_a(a14_13to14_14), .out_b(b14_13to15_13), .out_c(matrixC14_13)); +processing_element pe14_14(.reset(effective_rst), .clk(clk), .in_a(a14_13to14_14), .in_b(b13_14to14_14), .out_a(a14_14to14_15), .out_b(b14_14to15_14), .out_c(matrixC14_14)); +processing_element pe14_15(.reset(effective_rst), .clk(clk), .in_a(a14_14to14_15), .in_b(b13_15to14_15), .out_a(a14_15to14_16), .out_b(b14_15to15_15), .out_c(matrixC14_15)); +processing_element_bottom_edge pe15_1(.reset(effective_rst), .clk(clk), .in_a(a15_0to15_1), .in_b(b14_1to15_1), .out_a(a15_1to15_2), .out_b(b15_1to16_1), .out_c(matrixC15_1)); +processing_element_bottom_edge pe15_2(.reset(effective_rst), .clk(clk), .in_a(a15_1to15_2), .in_b(b14_2to15_2), .out_a(a15_2to15_3), .out_b(b15_2to16_2), .out_c(matrixC15_2)); +processing_element_bottom_edge pe15_3(.reset(effective_rst), .clk(clk), .in_a(a15_2to15_3), .in_b(b14_3to15_3), .out_a(a15_3to15_4), .out_b(b15_3to16_3), .out_c(matrixC15_3)); +processing_element_bottom_edge pe15_4(.reset(effective_rst), .clk(clk), .in_a(a15_3to15_4), .in_b(b14_4to15_4), .out_a(a15_4to15_5), .out_b(b15_4to16_4), .out_c(matrixC15_4)); +processing_element_bottom_edge pe15_5(.reset(effective_rst), .clk(clk), .in_a(a15_4to15_5), .in_b(b14_5to15_5), .out_a(a15_5to15_6), .out_b(b15_5to16_5), .out_c(matrixC15_5)); +processing_element_bottom_edge pe15_6(.reset(effective_rst), .clk(clk), .in_a(a15_5to15_6), .in_b(b14_6to15_6), .out_a(a15_6to15_7), .out_b(b15_6to16_6), .out_c(matrixC15_6)); +processing_element_bottom_edge pe15_7(.reset(effective_rst), .clk(clk), .in_a(a15_6to15_7), .in_b(b14_7to15_7), .out_a(a15_7to15_8), .out_b(b15_7to16_7), .out_c(matrixC15_7)); +processing_element_bottom_edge pe15_8(.reset(effective_rst), .clk(clk), .in_a(a15_7to15_8), .in_b(b14_8to15_8), .out_a(a15_8to15_9), .out_b(b15_8to16_8), .out_c(matrixC15_8)); +processing_element_bottom_edge pe15_9(.reset(effective_rst), .clk(clk), .in_a(a15_8to15_9), .in_b(b14_9to15_9), .out_a(a15_9to15_10), .out_b(b15_9to16_9), .out_c(matrixC15_9)); +processing_element_bottom_edge pe15_10(.reset(effective_rst), .clk(clk), .in_a(a15_9to15_10), .in_b(b14_10to15_10), .out_a(a15_10to15_11), .out_b(b15_10to16_10), .out_c(matrixC15_10)); +processing_element_bottom_edge pe15_11(.reset(effective_rst), .clk(clk), .in_a(a15_10to15_11), .in_b(b14_11to15_11), .out_a(a15_11to15_12), .out_b(b15_11to16_11), .out_c(matrixC15_11)); +processing_element_bottom_edge pe15_12(.reset(effective_rst), .clk(clk), .in_a(a15_11to15_12), .in_b(b14_12to15_12), .out_a(a15_12to15_13), .out_b(b15_12to16_12), .out_c(matrixC15_12)); +processing_element_bottom_edge pe15_13(.reset(effective_rst), .clk(clk), .in_a(a15_12to15_13), .in_b(b14_13to15_13), .out_a(a15_13to15_14), .out_b(b15_13to16_13), .out_c(matrixC15_13)); +processing_element_bottom_edge pe15_14(.reset(effective_rst), .clk(clk), .in_a(a15_13to15_14), .in_b(b14_14to15_14), .out_a(a15_14to15_15), .out_b(b15_14to16_14), .out_c(matrixC15_14)); +processing_element_bottom_edge pe15_15(.reset(effective_rst), .clk(clk), .in_a(a15_14to15_15), .in_b(b14_15to15_15), .out_a(a15_15to15_16), .out_b(b15_15to16_15), .out_c(matrixC15_15)); +//assign a_data_out = {a15_15to15_16,a14_15to14_16,a13_15to13_16,a12_15to12_16,a11_15to11_16,a10_15to10_16,a9_15to9_16,a8_15to8_16,a7_15to7_16,a6_15to6_16,a5_15to5_16,a4_15to4_16,a3_15to3_16,a2_15to2_16,a1_15to1_16,a0_15to0_16}; +//assign b_data_out = {b15_15to16_15,b15_14to16_14,b15_13to16_13,b15_12to16_12,b15_11to16_11,b15_10to16_10,b15_9to16_9,b15_8to16_8,b15_7to16_7,b15_6to16_6,b15_5to16_5,b15_4to16_4,b15_3to16_3,b15_2to16_2,b15_1to16_1,b15_0to16_0}; + +endmodule + +module processing_element( + reset, + clk, + in_a, + in_b, + out_a, + out_b, + out_c + ); + +`ifdef complex_dsp + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [18:0] in_b; + output reg [`DWIDTH-1:0] out_a; + output [18:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + wire [18:0] scanout; + wire [63:0] chainout; //unconnected + wire [63:0] result; + wire [17:0] ax; + wire [18:0] ay; //unconnected + wire [35:0] bx; + wire [63:0] chainin; //unconnected + wire [18:0] scanin; + wire [11:0] mode_sigs; + + assign mode_sigs = 12'b010101010101; //Any value of mode_sigs (structural, not functional, correctness) + assign ax = {{(18-`DWIDTH){1'b0}}, in_a}; + //assign ay = {{(19-`DWIDTH){1'b0}}, in_b}; + assign bx = 36'b0; + assign scanin = in_b; + + //We will instantiate DSP slices with input chaining. + //Input chaining is only supported in the 18x19 mode or the 27x27 mode. + //We will use the input chain provided by the DSP for the B input. For A, the chain will be manual. + + mult_add_int_18x19 u_pe( + .clk(clk), + .reset(reset), + .mode_sigs(mode_sigs), + .ax(ax), + .ay(ay), + .bx(bx), + .chainin(chainin), + .scanin(scanin), + .result(result), + .chainout(chainout), + .scanout(scanout) + ); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + end + else begin + out_a<=in_a; + end + end + + assign out_b = scanout; + assign out_c = result[`DWIDTH-1:0]; + +`else + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [18:0] in_b; + output reg [`DWIDTH-1:0] out_a; + output reg [18:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + wire [`DWIDTH-1:0] out_mac; + + assign out_c = out_mac; + + seq_mac u_mac(.a(in_a), .b(in_b[`DWIDTH-1:0]), .out(out_mac), .reset(reset), .clk(clk)); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + out_b<=0; + end + else begin + out_a<=in_a; + out_b<=in_b; + end + end + +`endif + +endmodule + +module processing_element_top_edge( + reset, + clk, + in_a, + in_b, + out_a, + out_b, + out_c + ); + +`ifdef complex_dsp + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [18:0] in_b; + output reg [`DWIDTH-1:0] out_a; + output [18:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + wire [18:0] scanout; + wire [63:0] chainout; //unconnected + wire [63:0] result; + wire [17:0] ax; + wire [18:0] ay; + wire [35:0] bx; + wire [63:0] chainin; //unconnected + wire [18:0] scanin; //unconnected + wire [11:0] mode_sigs; + + assign mode_sigs = 12'b010101010101; //Any value of mode_sigs (structural, not functional, correctness) + assign ax = {{(18-`DWIDTH){1'b0}}, in_a}; + assign ay = {{(19-`DWIDTH){1'b0}}, in_b}; + assign bx = 36'b0; + + //We will instantiate DSP slices with input chaining. + //Input chaining is only supported in the 18x19 mode or the 27x27 mode. + //We will use the input chain provided by the DSP for the B input. For A, the chain will be manual. + + mult_add_int_18x19 u_pe( + .clk(clk), + .reset(reset), + .mode_sigs(mode_sigs), + .ax(ax), + .ay(ay), + .bx(bx), + .chainin(chainin), + .scanin(scanin), + .result(result), + .chainout(chainout), + .scanout(scanout) + ); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + end + else begin + out_a<=in_a; + end + end + + assign out_b = scanout; + assign out_c = result[`DWIDTH-1:0]; + +`else + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [18:0] in_b; + output reg [`DWIDTH-1:0] out_a; + output reg [18:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + wire [`DWIDTH-1:0] out_mac; + + assign out_c = out_mac; + + seq_mac u_mac(.a(in_a), .b(in_b[`DWIDTH-1:0]), .out(out_mac), .reset(reset), .clk(clk)); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + out_b<=0; + end + else begin + out_a<=in_a; + out_b<=in_b; + end + end + +`endif + +endmodule + +module processing_element_bottom_edge( + reset, + clk, + in_a, + in_b, + out_a, + out_b, + out_c + ); + +`ifdef complex_dsp + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [18:0] in_b; + output reg [`DWIDTH-1:0] out_a; + output [18:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + wire [18:0] scanout; //unconnected + wire [63:0] chainout; //unconnected + wire [63:0] result; + wire [17:0] ax; + wire [18:0] ay; //unconnected + wire [35:0] bx; + wire [63:0] chainin; //unconnected + wire [18:0] scanin; + wire [11:0] mode_sigs; + + assign mode_sigs = 12'b010101010101; //Any value of mode_sigs (structural, not functional, correctness) + assign ax = {{(18-`DWIDTH){1'b0}}, in_a}; + //assign ay = {{(19-`DWIDTH){1'b0}}, in_b}; + assign bx = 36'b0; + assign scanin = in_b; + + //We will instantiate DSP slices with input chaining. + //Input chaining is only supported in the 18x19 mode or the 27x27 mode. + //We will use the input chain provided by the DSP for the B input. For A, the chain will be manual. + + mult_add_int_18x19 u_pe( + .clk(clk), + .reset(reset), + .mode_sigs(mode_sigs), + .ax(ax), + .ay(ay), + .bx(bx), + .chainin(chainin), + .scanin(scanin), + .result(result), + .chainout(chainout), + .scanout(scanout) + ); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + end + else begin + out_a<=in_a; + end + end + + //assign out_b = scanout; + assign out_c = result[`DWIDTH-1:0]; + +`else + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [18:0] in_b; + output reg [`DWIDTH-1:0] out_a; + output reg [18:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + wire [`DWIDTH-1:0] out_mac; + + assign out_c = out_mac; + + seq_mac u_mac(.a(in_a), .b(in_b[`DWIDTH-1:0]), .out(out_mac), .reset(reset), .clk(clk)); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + out_b<=0; + end + else begin + out_a<=in_a; + out_b<=in_b; + end + end + +`endif + +endmodule + +`ifndef complex_dsp +module seq_mac(a, b, out, reset, clk); +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +input reset; +input clk; +output [`DWIDTH-1:0] out; + +reg [2*`DWIDTH-1:0] out_temp; +wire [`DWIDTH-1:0] mul_out; +wire [2*`DWIDTH-1:0] add_out; + +reg [`DWIDTH-1:0] a_flopped; +reg [`DWIDTH-1:0] b_flopped; + +wire [2*`DWIDTH-1:0] mul_out_temp; +reg [2*`DWIDTH-1:0] mul_out_temp_reg; + +always @(posedge clk) begin + a_flopped <= a; + b_flopped <= b; +end + +//assign mul_out = a * b; +qmult mult_u1(.i_multiplicand(a_flopped), .i_multiplier(b_flopped), .o_result(mul_out_temp)); + +always @(posedge clk) begin + mul_out_temp_reg <= mul_out_temp; +end + +//we just truncate the higher bits of the product +//assign add_out = mul_out + out; +qadd add_u1(.a(out_temp), .b(mul_out_temp_reg), .c(add_out)); + +always @(posedge clk) begin + out_temp <= add_out; +end + +//down cast the result +assign out = + (out_temp[2*`DWIDTH-1] == 0) ? //positive number + ( + (|(out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 1, that means overlfow + {out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b1}}} : //sign bit and then all 1s + {out_temp[2*`DWIDTH-1] , out_temp[`DWIDTH-2:0]} + ) + : //negative number + ( + (|(out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 0, that means overlfow + {out_temp[2*`DWIDTH-1] , out_temp[`DWIDTH-2:0]} : + {out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b0}}} //sign bit and then all 0s + ); + +endmodule + +module qmult(i_multiplicand,i_multiplier,o_result); +input [`DWIDTH-1:0] i_multiplicand; +input [`DWIDTH-1:0] i_multiplier; +output [2*`DWIDTH-1:0] o_result; + +assign o_result = i_multiplicand * i_multiplier; +//DW02_mult #(`DWIDTH,`DWIDTH) u_mult(.A(i_multiplicand), .B(i_multiplier), .TC(1'b1), .PRODUCT(o_result)); + +endmodule + +module qadd(a,b,c); +input [2*`DWIDTH-1:0] a; +input [2*`DWIDTH-1:0] b; +output [2*`DWIDTH-1:0] c; + +assign c = a + b; +//DW01_add #(`DWIDTH) u_add(.A(a), .B(b), .CI(1'b0), .SUM(c), .CO()); +endmodule +`endif + +////////////////////////////////////////////// +// Configuration block +////////////////////////////////////////////// + +module cfg( + input PCLK, + input PRESETn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output reg [`REG_DATAWIDTH-1:0] PRDATA, + output reg PREADY, + output reg start_tpu, + output reg enable_matmul, + output reg enable_norm, + output reg enable_pool, + output reg enable_activation, + output reg enable_conv_mode, + output reg [`DWIDTH-1:0] mean, + output reg [`DWIDTH-1:0] inv_var, + output reg [`MAX_BITS_POOL-1:0] pool_window_size, + output reg [`AWIDTH-1:0] address_mat_a, + output reg [`AWIDTH-1:0] address_mat_b, + output reg [`AWIDTH-1:0] address_mat_c, + output reg [`MASK_WIDTH-1:0] validity_mask_a_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_a_cols, + output reg [`MASK_WIDTH-1:0] validity_mask_b_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_b_cols, + output reg save_output_to_accum, + output reg add_accum_to_output, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c, + output reg activation_type, + output reg [3:0] conv_filter_height, + output reg [3:0] conv_filter_width, + output reg [3:0] conv_stride_horiz, + output reg [3:0] conv_stride_verti, + output reg [3:0] conv_padding_left, + output reg [3:0] conv_padding_right, + output reg [3:0] conv_padding_top, + output reg [3:0] conv_padding_bottom, + output reg [15:0] num_channels_inp, + output reg [15:0] num_channels_out, + output reg [15:0] inp_img_height, + output reg [15:0] inp_img_width, + output reg [15:0] out_img_height, + output reg [15:0] out_img_width, + output reg [31:0] batch_size, + output reg pe_reset, + input done_tpu +); + +//Dummy register to sync all other invalid/unimplemented addresses +reg [`REG_DATAWIDTH-1:0] reg_dummy; + + +////////////////////////////////////////////////////// +//Using a simple APB interface. Taken from: +// https://github.com/maomran/APB-Slave +// https://research.ijcaonline.org/volume95/number21/pxc3897047.pdf + +reg [1:0] State; +`define IDLE 2'b00 +`define W_ENABLE 2'b01 +`define R_ENABLE 2'b10 + +always @(posedge PCLK) begin + if (PRESETn == 0) begin + State <= `IDLE; + PRDATA <= 0; + PREADY <= 0; + start_tpu <= 0; + enable_matmul <= 0; + enable_norm <= 0; + enable_pool <= 0; + enable_activation <= 0; + mean <= 0; + inv_var <= 0; + pool_window_size <= 1; + reg_dummy <= 0; + address_mat_a <= 0; + address_mat_b <= 0; + address_mat_c <= 0; + validity_mask_a_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_a_cols <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_cols <= {`MASK_WIDTH{1'b1}}; + save_output_to_accum <= 0; + add_accum_to_output <= 0; + address_stride_a <= `DESIGN_SIZE; + address_stride_b <= `DESIGN_SIZE; + address_stride_c <= `DESIGN_SIZE; + activation_type <= 1; + conv_filter_height <= 2; + conv_filter_width <= 2; + conv_stride_horiz <= 1; + conv_stride_verti <= 1; + conv_padding_left <= 0; + conv_padding_right <= 0; + conv_padding_top <= 0; + conv_padding_bottom<= 0; + num_channels_inp <= 4; + num_channels_out <= 4; + inp_img_height <= 8; + inp_img_width <= 8; + out_img_height <= 7; + out_img_width <= 7; + batch_size <= 2; + enable_conv_mode <= 0; + pe_reset <= 0; + end + + else begin + case (State) + `IDLE : begin + PRDATA <= 0; + if (PSEL) begin + if (PWRITE) begin + State <= `W_ENABLE; + end + else begin + State <= `R_ENABLE; + end + end + PREADY <= 0; + pe_reset <= 0; //this register bit auto resets itself + end + + `W_ENABLE : begin + if (PSEL && PWRITE && PENABLE) begin + case (PADDR) + `REG_ENABLES_ADDR : begin + enable_conv_mode <= PWDATA[31]; + enable_activation <= PWDATA[3]; + enable_pool <= PWDATA[2]; + enable_norm <= PWDATA[1]; + enable_matmul <= PWDATA[0]; + end + `REG_STDN_TPU_ADDR : begin + start_tpu <= PWDATA[0]; + pe_reset <= PWDATA[15]; + end + `REG_MEAN_ADDR : mean <= PWDATA[`DWIDTH-1:0]; + `REG_INV_VAR_ADDR : inv_var <= PWDATA[`DWIDTH-1:0]; + `REG_MATRIX_A_ADDR : address_mat_a <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_B_ADDR : address_mat_b <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_C_ADDR : address_mat_c <= PWDATA[`AWIDTH-1:0]; + `REG_VALID_MASK_A_ROWS_ADDR: begin + validity_mask_a_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_A_COLS_ADDR: begin + validity_mask_a_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_ROWS_ADDR: begin + validity_mask_b_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_COLS_ADDR: begin + validity_mask_b_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_POOL_WINDOW_ADDR: pool_window_size <= PWDATA[`MAX_BITS_POOL-1:0]; + `REG_ACCUM_ACTIONS_ADDR: begin + add_accum_to_output <= PWDATA[1]; + save_output_to_accum <= PWDATA[0]; + end + `REG_MATRIX_A_STRIDE_ADDR : address_stride_a <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_B_STRIDE_ADDR : address_stride_b <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_C_STRIDE_ADDR : address_stride_c <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_ACTIVATION_CSR_ADDR : activation_type <= PWDATA[0]; + `REG_CONV_PARAMS_1_ADDR : begin + conv_filter_height <= PWDATA[3:0]; + conv_filter_width <= PWDATA[7:4]; + conv_stride_horiz <= PWDATA[11:8]; + conv_stride_verti <= PWDATA[15:12]; + conv_padding_left <= PWDATA[19:16]; + conv_padding_right <= PWDATA[23:20]; + conv_padding_top <= PWDATA[27:24]; + conv_padding_bottom<= PWDATA[31:28]; + end + `REG_CONV_PARAMS_2_ADDR : begin + num_channels_inp <= PWDATA[15:0]; + num_channels_out <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_3_ADDR : begin + inp_img_height <= PWDATA[15:0]; + inp_img_width <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_4_ADDR : begin + out_img_height <= PWDATA[15:0]; + out_img_width <= PWDATA[31:16]; + end + `REG_BATCH_SIZE_ADDR : batch_size <= PWDATA[31:0]; + default: reg_dummy <= PWDATA; //sink writes to a dummy register + endcase + PREADY <=1; + end + State <= `IDLE; + end + + `R_ENABLE : begin + if (PSEL && !PWRITE && PENABLE) begin + PREADY <= 1; + case (PADDR) + `REG_ENABLES_ADDR : PRDATA <= {28'b0, enable_activation, enable_pool, enable_norm, enable_matmul}; + `REG_STDN_TPU_ADDR : PRDATA <= {done_tpu, 30'b0, start_tpu}; + `REG_MEAN_ADDR : PRDATA <= mean; + `REG_INV_VAR_ADDR : PRDATA <= inv_var; + `REG_MATRIX_A_ADDR : PRDATA <= address_mat_a; + `REG_MATRIX_B_ADDR : PRDATA <= address_mat_b; + `REG_MATRIX_C_ADDR : PRDATA <= address_mat_c; + `REG_VALID_MASK_A_ROWS_ADDR: PRDATA <= validity_mask_a_rows; + `REG_VALID_MASK_A_COLS_ADDR: PRDATA <= validity_mask_a_cols; + `REG_VALID_MASK_B_ROWS_ADDR: PRDATA <= validity_mask_b_rows; + `REG_VALID_MASK_B_COLS_ADDR: PRDATA <= validity_mask_b_cols; + `REG_POOL_WINDOW_ADDR : PRDATA <= pool_window_size; + `REG_ACCUM_ACTIONS_ADDR: PRDATA <= {30'b0, add_accum_to_output, save_output_to_accum}; + `REG_MATRIX_A_STRIDE_ADDR : PRDATA <= address_stride_a; + `REG_MATRIX_B_STRIDE_ADDR : PRDATA <= address_stride_b; + `REG_MATRIX_C_STRIDE_ADDR : PRDATA <= address_stride_c; + `REG_ACTIVATION_CSR_ADDR : PRDATA <= {31'b0, activation_type}; + `REG_CONV_PARAMS_1_ADDR : PRDATA <= { + conv_filter_height, + conv_filter_width, + conv_stride_horiz, + conv_stride_verti, + conv_padding_left, + conv_padding_right, + conv_padding_top, + conv_padding_bottom + }; + `REG_CONV_PARAMS_2_ADDR : PRDATA <= { + num_channels_inp, + num_channels_out + }; + `REG_CONV_PARAMS_3_ADDR : PRDATA <= { + inp_img_height, + inp_img_width + }; + `REG_CONV_PARAMS_4_ADDR : PRDATA <= { + out_img_height, + out_img_width + }; + `REG_BATCH_SIZE_ADDR : PRDATA <= batch_size; + default : PRDATA <= reg_dummy; //read the dummy register for undefined addresses + endcase + end + State <= `IDLE; + end + default: begin + State <= `IDLE; + end + endcase + end +end + +endmodule + + +//////////////////////////////////////////////// +// Normalization block +//////////////////////////////////////////////// + +module norm( + input enable_norm, + input [`DWIDTH-1:0] mean, + input [`DWIDTH-1:0] inv_var, + input in_data_available, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_norm, + input clk, + input reset +); + +reg out_data_available_internal; +wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] mean_applied_data; +reg [`DESIGN_SIZE*`DWIDTH-1:0] variance_applied_data; +reg done_norm_internal; +reg norm_in_progress; +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +//Muxing logic to handle the case when this block is disabled +assign out_data_available = (enable_norm) ? out_data_available_internal : in_data_available_flopped; +assign out_data = (enable_norm) ? out_data_internal : inp_data_flopped; +assign done_norm = (enable_norm) ? done_norm_internal : 1'b1; + +//inp_data will have multiple elements in it. the number of elements is the same as size of the matmul. +//on each clock edge, if in_data_available is 1, then we will normalize the inputs. + +//the code uses the funky part-select syntax. example: +//wire [7:0] byteN = word[byte_num*8 +: 8]; +//byte_num*8 is the starting point. 8 is the width is the part-select (has to be constant).in_data_available +//+: indicates the part-select increases from the starting point +//-: indicates the part-select decreases from the starting point +//another example: +//loc = 3; +//PA[loc -:4] = PA[loc+1 +:4]; // equivalent to PA[3:0] = PA[7:4]; + +reg [31:0] cycle_count; +reg [31:0] i; +always @(posedge clk) begin + if ((reset || ~enable_norm)) begin + mean_applied_data <= 0; + variance_applied_data <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + done_norm_internal <= 0; + norm_in_progress <= 0; + in_data_available_flopped <= in_data_available; + inp_data_flopped <= inp_data; + end else if (in_data_available || norm_in_progress) begin + cycle_count <= cycle_count + 1; + //Let's apply mean and variance as the input data comes in. + //We have a pipeline here. First stage does the add (to apply the mean) + //and second stage does the multiplication (to apply the variance). + //Note: the following loop is not a loop across multiple columns of data. + //This loop will run in 2 cycle on the same column of data that comes into + //this module in 1 clock. + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if (validity_mask[i] == 1'b1) begin + mean_applied_data[i*`DWIDTH +: `DWIDTH] <= (inp_data[i*`DWIDTH +: `DWIDTH] - mean); + variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH] * inv_var); + end + else begin + mean_applied_data[i*`DWIDTH +: `DWIDTH] <= (inp_data[i*`DWIDTH +: `DWIDTH]); + variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH]); + end + end + + //Out data is available starting with the second clock cycle because + //in the first cycle, we only apply the mean. + if(cycle_count==2) begin + out_data_available_internal <= 1; + end + + //When we've normalized values N times, where N is the matmul + //size, that means we're done. But there is one additional cycle + //that is taken in the beginning (when we are applying the mean to the first + //column of data). We can call this the Initiation Interval of the pipeline. + //So, for a 4x4 matmul, this block takes 5 cycles. + if(cycle_count==(`DESIGN_SIZE+1)) begin + done_norm_internal <= 1'b1; + norm_in_progress <= 0; + end + else begin + norm_in_progress <= 1; + end + end + else begin + mean_applied_data <= 0; + variance_applied_data <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + done_norm_internal <= 0; + norm_in_progress <= 0; + end +end + +assign out_data_internal = variance_applied_data; + +endmodule + +////////////////////////////////// +// Dual port RAM +////////////////////////////////// + +module ram ( + addr0, + d0, + we0, + q0, + addr1, + d1, + we1, + q1, + clk); + +input [`AWIDTH-1:0] addr0; +input [`AWIDTH-1:0] addr1; +input [`DESIGN_SIZE*`DWIDTH-1:0] d0; +input [`DESIGN_SIZE*`DWIDTH-1:0] d1; +input [`DESIGN_SIZE-1:0] we0; +input [`DESIGN_SIZE-1:0] we1; +output [`DESIGN_SIZE*`DWIDTH-1:0] q0; +output [`DESIGN_SIZE*`DWIDTH-1:0] q1; +input clk; + +genvar i; + +generate +`ifdef QUARTUS + for (i=0;i<`DESIGN_SIZE;i=i+1) begin: gen_dp1 +`else + for (i=0;i<`DESIGN_SIZE;i=i+1) begin +`endif + dpram_original #(.AWIDTH(`AWIDTH),.DWIDTH(`DWIDTH),.NUM_WORDS(1<<`AWIDTH)) dp1 (.clk(clk),.address_a(addr0),.address_b(addr1),.wren_a(we0[i]),.wren_b(we1[i]),.data_a(d0[i*`DWIDTH +: `DWIDTH]),.data_b(d1[i*`DWIDTH +: `DWIDTH]),.out_a(q0[i*`DWIDTH +: `DWIDTH]),.out_b(q1[i*`DWIDTH +: `DWIDTH])); + end +endgenerate + +endmodule + +module dpram_original ( + clk, + address_a, + address_b, + wren_a, + wren_b, + data_a, + data_b, + out_a, + out_b +); +parameter AWIDTH=10; +parameter NUM_WORDS=1024; +parameter DWIDTH=32; +input clk; +input [(AWIDTH-1):0] address_a; +input [(AWIDTH-1):0] address_b; +input wren_a; +input wren_b; +input [(DWIDTH-1):0] data_a; +input [(DWIDTH-1):0] data_b; +output reg [(DWIDTH-1):0] out_a; +output reg [(DWIDTH-1):0] out_b; + +`ifndef hard_mem + +reg [DWIDTH-1:0] ram[NUM_WORDS-1:0]; +always @ (posedge clk) begin + if (wren_a) begin + ram[address_a] <= data_a; + end + else begin + out_a <= ram[address_a]; + end +end + +always @ (posedge clk) begin + if (wren_b) begin + ram[address_b] <= data_b; + end + else begin + out_b <= ram[address_b]; + end +end + +`else + +defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; +defparam u_dual_port_ram.DATA_WIDTH = DWIDTH; + +dual_port_ram u_dual_port_ram( +.addr1(address_a), +.we1(wren_a), +.data1(data_a), +.out1(out_a), +.addr2(address_b), +.we2(wren_b), +.data2(data_b), +.out2(out_b), +.clk(clk) +); + +`endif +endmodule + +//////////////////////////////////////////////// +// Control unit +//////////////////////////////////////////////// + +module control( + input clk, + input reset, + input start_tpu, + input enable_matmul, + input enable_norm, + input enable_activation, + input enable_pool, + output reg start_mat_mul, + input done_mat_mul, + input done_norm, + input done_pool, + input done_activation, + input save_output_to_accum, + output reg done_tpu +); + +reg [3:0] state; + +`define STATE_INIT 4'b0000 +`define STATE_MATMUL 4'b0001 +`define STATE_NORM 4'b0010 +`define STATE_POOL 4'b0011 +`define STATE_ACTIVATION 4'b0100 +`define STATE_DONE 4'b0101 + +////////////////////////////////////////////////////// +// Assumption: We will always run matmul first. That is, matmul is not optional. +// The other blocks - norm, act, pool - are optional. +// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation +////////////////////////////////////////////////////// + +always @( posedge clk) begin + if (reset) begin + state <= `STATE_INIT; + start_mat_mul <= 1'b0; + done_tpu <= 1'b0; + end else begin + case (state) + `STATE_INIT: begin + if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin + if (enable_matmul == 1'b1) begin + start_mat_mul <= 1'b1; + state <= `STATE_MATMUL; + end + end + end + + //start_mat_mul is kinda used as a reset in some logic + //inside the matmul unit. So, we can't make it 0 right away after + //asserting it. + `STATE_MATMUL: begin + if (done_mat_mul == 1'b1) begin + start_mat_mul <= 1'b0; + if(save_output_to_accum) begin + state <= `STATE_DONE; + end + else if (enable_norm) begin + state <= `STATE_NORM; + end + else if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + else begin + start_mat_mul <= 1'b1; + end + end + + `STATE_NORM: begin + if (done_norm == 1'b1) begin + if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_POOL: begin + if (done_pool == 1'b1) begin + if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_ACTIVATION: begin + if (done_activation == 1'b1) begin + state <= `STATE_DONE; + end + end + + `STATE_DONE: begin + //We need to write start_tpu to 0 in the CFG block to get out of this state + if (start_tpu == 1'b0) begin + state <= `STATE_INIT; + done_tpu <= 0; + end + else begin + done_tpu <= 1; + end + end + endcase + end +end +endmodule + +//////////////////////////////////////////////// +// Pooling block +//////////////////////////////////////////////// + +module pool( + input enable_pool, + input in_data_available, + input [`MAX_BITS_POOL-1:0] pool_window_size, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_pool, + input clk, + input reset +); + +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +reg [`DESIGN_SIZE*`DWIDTH-1:0] out_data_temp; +reg done_pool_temp; +reg out_data_available_temp; +reg [31:0] i,j; +reg [31:0] cycle_count; + +always @(posedge clk) begin + if (reset || ~enable_pool || ~in_data_available) begin + out_data_temp <= 0; + done_pool_temp <= 0; + out_data_available_temp <= 0; + cycle_count <= 0; + in_data_available_flopped <= in_data_available; + inp_data_flopped <= inp_data; + end + + else if (in_data_available) begin + cycle_count <= cycle_count + 1; + out_data_available_temp <= 1; + + case (pool_window_size) + 1: begin + out_data_temp <= inp_data; + end + 2: begin + for (i = 0; i < `DESIGN_SIZE/2; i = i + 8) begin + out_data_temp[ i +: 8] <= (inp_data[i*2 +: 8] + inp_data[i*2 + 8 +: 8]) >> 1; + end + end + 4: begin + for (i = 0; i < `DESIGN_SIZE/4; i = i + 8) begin + //TODO: If 3 adders are the critical path, break into 2 cycles + out_data_temp[ i +: 8] <= (inp_data[i*4 +: 8] + inp_data[i*4 + 8 +: 8] + inp_data[i*4 + 16 +: 8] + inp_data[i*4 + 24 +: 8]) >> 2; + end + end + endcase + + if(cycle_count==`DESIGN_SIZE) begin + done_pool_temp <= 1'b1; + end + end +end + +assign out_data = enable_pool ? out_data_temp : inp_data_flopped; +assign out_data_available = enable_pool ? out_data_available_temp : in_data_available_flopped; +assign done_pool = enable_pool ? done_pool_temp : 1'b1; + +//Adding a dummy signal to use validity_mask input, to make ODIN happy +wire [`MASK_WIDTH-1:0] dummy; +assign dummy = validity_mask; + +endmodule + +//////////////////////////////////////////////// +// Activation block +//////////////////////////////////////////////// + +module activation( + input activation_type, + input enable_activation, + input in_data_available, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_activation, + input clk, + input reset +); + +reg done_activation_internal; +reg out_data_available_internal; +wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] slope_applied_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] intercept_applied_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] relu_applied_data_internal; +reg [31:0] i; +reg [31:0] cycle_count; +reg activation_in_progress; + +reg [(`DESIGN_SIZE*4)-1:0] address; +reg [(`DESIGN_SIZE*8)-1:0] data_slope; +reg [(`DESIGN_SIZE*8)-1:0] data_slope_flopped; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept_delayed; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept_flopped; + +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +always @(posedge clk) begin + if (reset) begin + inp_data_flopped <= 0; + data_slope_flopped <= 0; + end else begin + inp_data_flopped <= inp_data; + data_slope_flopped <= data_slope; + end +end + +// If the activation block is not enabled, just forward the input data +assign out_data = enable_activation ? out_data_internal : inp_data_flopped; +assign done_activation = enable_activation ? done_activation_internal : 1'b1; +assign out_data_available = enable_activation ? out_data_available_internal : in_data_available_flopped; + +always @(posedge clk) begin + if (reset || ~enable_activation) begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + data_intercept_flopped <= 0; + done_activation_internal <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + in_data_available_flopped <= in_data_available; + end else if(in_data_available || activation_in_progress) begin + cycle_count <= cycle_count + 1; + + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if(activation_type==1'b1) begin // tanH + slope_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= data_slope_flopped[i*8 +: 8] * inp_data_flopped[i*`DWIDTH +:`DWIDTH]; + data_intercept_flopped[i*8 +: 8] <= data_intercept[i*8 +: 8]; + data_intercept_delayed[i*8 +: 8] <= data_intercept_flopped[i*8 +: 8]; + intercept_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= slope_applied_data_internal[i*`DWIDTH +:`DWIDTH] + data_intercept_delayed[i*8 +: 8]; + end else begin // ReLU + relu_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= inp_data[i*`DWIDTH] ? {`DWIDTH{1'b0}} : inp_data[i*`DWIDTH +:`DWIDTH]; + end + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if (cycle_count==3) begin + out_data_available_internal <= 1; + end + end else begin + if (cycle_count==2) begin + out_data_available_internal <= 1; + end + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if(cycle_count==(`DESIGN_SIZE+2)) begin + done_activation_internal <= 1'b1; + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end else begin + if(cycle_count==(`DESIGN_SIZE+1)) begin + done_activation_internal <= 1'b1; + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end + end + else begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + data_intercept_flopped <= 0; + done_activation_internal <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + end +end + +assign out_data_internal = (activation_type) ? intercept_applied_data_internal : relu_applied_data_internal; + +//Our equation of tanh is Y=AX+B +//A is the slope and B is the intercept. +//We store A in one LUT and B in another. +//LUT for the slope +always @(address) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + case (address[i*4+:4]) + 4'b0000: data_slope[i*8+:8] = 8'd0; + 4'b0001: data_slope[i*8+:8] = 8'd0; + 4'b0010: data_slope[i*8+:8] = 8'd2; + 4'b0011: data_slope[i*8+:8] = 8'd3; + 4'b0100: data_slope[i*8+:8] = 8'd4; + 4'b0101: data_slope[i*8+:8] = 8'd0; + 4'b0110: data_slope[i*8+:8] = 8'd4; + 4'b0111: data_slope[i*8+:8] = 8'd3; + 4'b1000: data_slope[i*8+:8] = 8'd2; + 4'b1001: data_slope[i*8+:8] = 8'd0; + 4'b1010: data_slope[i*8+:8] = 8'd0; + default: data_slope[i*8+:8] = 8'd0; + endcase + end +end + +//LUT for the intercept +always @(address) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + case (address[i*4+:4]) + 4'b0000: data_intercept[i*8+:8] = 8'd127; + 4'b0001: data_intercept[i*8+:8] = 8'd99; + 4'b0010: data_intercept[i*8+:8] = 8'd46; + 4'b0011: data_intercept[i*8+:8] = 8'd18; + 4'b0100: data_intercept[i*8+:8] = 8'd0; + 4'b0101: data_intercept[i*8+:8] = 8'd0; + 4'b0110: data_intercept[i*8+:8] = 8'd0; + 4'b0111: data_intercept[i*8+:8] = -8'd18; + 4'b1000: data_intercept[i*8+:8] = -8'd46; + 4'b1001: data_intercept[i*8+:8] = -8'd99; + 4'b1010: data_intercept[i*8+:8] = -8'd127; + default: data_intercept[i*8+:8] = 8'd0; + endcase + end +end + +//Logic to find address +always @(inp_data) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if((inp_data[i*`DWIDTH +:`DWIDTH])>=90) begin + address[i*4+:4] = 4'b0000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=39 && (inp_data[i*`DWIDTH +:`DWIDTH])<90) begin + address[i*4+:4] = 4'b0001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=28 && (inp_data[i*`DWIDTH +:`DWIDTH])<39) begin + address[i*4+:4] = 4'b0010; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=16 && (inp_data[i*`DWIDTH +:`DWIDTH])<28) begin + address[i*4+:4] = 4'b0011; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=1 && (inp_data[i*`DWIDTH +:`DWIDTH])<16) begin + address[i*4+:4] = 4'b0100; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])==0) begin + address[i*4+:4] = 4'b0101; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-16 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-1) begin + address[i*4+:4] = 4'b0110; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-28 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-16) begin + address[i*4+:4] = 4'b0111; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-39 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-28) begin + address[i*4+:4] = 4'b1000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-90 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-39) begin + address[i*4+:4] = 4'b1001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])<=-90) begin + address[i*4+:4] = 4'b1010; + end + else begin + address[i*4+:4] = 4'b0101; + end + end +end + +//Adding a dummy signal to use validity_mask input, to make ODIN happy +//TODO: Need to correctly use validity_mask +wire [`MASK_WIDTH-1:0] dummy; +assign dummy = validity_mask; + +endmodule + + +////////////////////////////////////////////////////// +// Top module +////////////////////////////////////////////////////// + +module top( + input clk, + input clk_mem, + input reset, + input resetn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output [`REG_DATAWIDTH-1:0] PRDATA, + output PREADY, + input [`AWIDTH-1:0] bram_addr_a_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a_ext, + input [`DESIGN_SIZE-1:0] bram_we_a_ext, + input [`AWIDTH-1:0] bram_addr_b_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b_ext, + input [`DESIGN_SIZE-1:0] bram_we_b_ext +); + +wire [`AWIDTH-1:0] bram_addr_a; +wire [`AWIDTH-1:0] bram_addr_a_for_reading; +reg [`AWIDTH-1:0] bram_addr_a_for_writing; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a; +reg [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a; +wire [`DESIGN_SIZE-1:0] bram_we_a; +wire bram_en_a; +wire [`AWIDTH-1:0] bram_addr_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b; +wire [`DESIGN_SIZE-1:0] bram_we_b; +wire bram_en_b; +reg bram_a_wdata_available; +wire [`AWIDTH-1:0] bram_addr_c_NC; +wire start_tpu; +wire done_tpu; +wire start_mat_mul; +wire done_mat_mul; +wire norm_out_data_available; +wire done_norm; +wire pool_out_data_available; +wire done_pool; +wire activation_out_data_available; +wire done_activation; +wire enable_matmul; +wire enable_norm; +wire enable_activation; +wire enable_pool; +wire [`DESIGN_SIZE*`DWIDTH-1:0] matmul_c_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] norm_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] pool_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] activation_data_out; +wire matmul_c_data_available; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_in_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_in_NC; +wire [`DWIDTH-1:0] mean; +wire [`DWIDTH-1:0] inv_var; +wire [`AWIDTH-1:0] address_mat_a; +wire [`AWIDTH-1:0] address_mat_b; +wire [`AWIDTH-1:0] address_mat_c; +wire [`MASK_WIDTH-1:0] validity_mask_a_rows; +wire [`MASK_WIDTH-1:0] validity_mask_a_cols; +wire [`MASK_WIDTH-1:0] validity_mask_b_rows; +wire [`MASK_WIDTH-1:0] validity_mask_b_cols; +wire save_output_to_accum; +wire add_accum_to_output; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +wire [`MAX_BITS_POOL-1:0] pool_window_size; +wire activation_type; +wire [3:0] conv_filter_height; +wire [3:0] conv_filter_width; +wire [3:0] conv_stride_horiz; +wire [3:0] conv_stride_verti; +wire [3:0] conv_padding_left; +wire [3:0] conv_padding_right; +wire [3:0] conv_padding_top; +wire [3:0] conv_padding_bottom; +wire [15:0] num_channels_inp; +wire [15:0] num_channels_out; +wire [15:0] inp_img_height; +wire [15:0] inp_img_width; +wire [15:0] out_img_height; +wire [15:0] out_img_width; +wire [31:0] batch_size; +wire enable_conv_mode; +wire pe_reset; + +//Connections for bram a (activation/input matrix) +//bram_addr_a -> connected to u_matmul_4x4 +//bram_rdata_a -> connected to u_matmul_4x4 +//bram_wdata_a -> will come from the last block that is enabled +//bram_we_a -> will be 1 when the last block's data is available +//bram_en_a -> hardcoded to 1 +assign bram_addr_a = (bram_a_wdata_available) ? bram_addr_a_for_writing : bram_addr_a_for_reading; +assign bram_en_a = 1'b1; +assign bram_we_a = (bram_a_wdata_available) ? {`DESIGN_SIZE{1'b1}} : {`DESIGN_SIZE{1'b0}}; + +//Connections for bram b (weights matrix) +//bram_addr_b -> connected to u_matmul_4x4 +//bram_rdata_b -> connected to u_matmul_4x4 +//bram_wdata_b -> hardcoded to 0 (this block only reads from bram b) +//bram_we_b -> hardcoded to 0 (this block only reads from bram b) +//bram_en_b -> hardcoded to 1 +assign bram_wdata_b = {`DESIGN_SIZE*`DWIDTH{1'b0}}; +assign bram_en_b = 1'b1; +assign bram_we_b = {`DESIGN_SIZE{1'b0}}; + +//////////////////////////////////////////////////////////////// +// BRAM matrix A (inputs/activations) +//////////////////////////////////////////////////////////////// +ram matrix_A ( + .addr0(bram_addr_a), + .d0(bram_wdata_a), + .we0(bram_we_a), + .q0(bram_rdata_a), + .addr1(bram_addr_a_ext), + .d1(bram_wdata_a_ext), + .we1(bram_we_a_ext), + .q1(bram_rdata_a_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// BRAM matrix B (weights) +//////////////////////////////////////////////////////////////// +ram matrix_B ( + .addr0(bram_addr_b), + .d0(bram_wdata_b), + .we0(bram_we_b), + .q0(bram_rdata_b), + .addr1(bram_addr_b_ext), + .d1(bram_wdata_b_ext), + .we1(bram_we_b_ext), + .q1(bram_rdata_b_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// Control logic that directs all the operation +//////////////////////////////////////////////////////////////// +control u_control( + .clk(clk), + .reset(reset), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_activation(enable_activation), + .enable_pool(enable_pool), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .done_norm(done_norm), + .done_pool(done_pool), + .done_activation(done_activation), + .save_output_to_accum(save_output_to_accum), + .done_tpu(done_tpu) +); + +//////////////////////////////////////////////////////////////// +// Configuration (register) block +//////////////////////////////////////////////////////////////// +cfg u_cfg( + .PCLK(clk), + .PRESETn(resetn), + .PADDR(PADDR), + .PWRITE(PWRITE), + .PSEL(PSEL), + .PENABLE(PENABLE), + .PWDATA(PWDATA), + .PRDATA(PRDATA), + .PREADY(PREADY), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_pool(enable_pool), + .enable_activation(enable_activation), + .enable_conv_mode(enable_conv_mode), + .mean(mean), + .inv_var(inv_var), + .pool_window_size(pool_window_size), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols(validity_mask_a_cols), + .validity_mask_b_rows(validity_mask_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .save_output_to_accum(save_output_to_accum), + .add_accum_to_output(add_accum_to_output), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .activation_type(activation_type), + .conv_filter_height(conv_filter_height), + .conv_filter_width(conv_filter_width), + .conv_stride_horiz(conv_stride_horiz), + .conv_stride_verti(conv_stride_verti), + .conv_padding_left(conv_padding_left), + .conv_padding_right(conv_padding_right), + .conv_padding_top(conv_padding_top), + .conv_padding_bottom(conv_padding_bottom), + .num_channels_inp(num_channels_inp), + .num_channels_out(num_channels_out), + .inp_img_height(inp_img_height), + .inp_img_width(inp_img_width), + .out_img_height(out_img_height), + .out_img_width(out_img_width), + .batch_size(batch_size), + .pe_reset(pe_reset), + .done_tpu(done_tpu) +); + +//TODO: We want to move the data setup part +//and the interface to BRAM_A and BRAM_B outside +//into its own modules. For now, it is all inside +//the matmul block + +//////////////////////////////////////////////////////////////// +//Matrix multiplier +//Note: the ports on this module to write data to bram c +//are not used in this top module. +//////////////////////////////////////////////////////////////// +matmul_16x16_systolic u_matmul( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .a_data(bram_rdata_a), + .b_data(bram_rdata_b), + .a_data_in(a_data_in_NC), + .b_data_in(b_data_in_NC), + .c_data_in({`DESIGN_SIZE*`DWIDTH{1'b0}}), + .c_data_out(matmul_c_data_out), + .a_data_out(a_data_out_NC), + .b_data_out(b_data_out_NC), + .a_addr(bram_addr_a_for_reading), + .b_addr(bram_addr_b), + .c_addr(bram_addr_c_NC), + .c_data_available(matmul_c_data_available), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols(validity_mask_a_cols), + .validity_mask_b_rows(validity_mask_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .final_mat_mul_size(8'd16), + .a_loc(8'd0), + .b_loc(8'd0) +); + +//////////////////////////////////////////////////////////////// +// Normalization module +//////////////////////////////////////////////////////////////// +norm u_norm( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(matmul_c_data_available), + .inp_data(matmul_c_data_out), + .out_data(norm_data_out), + .out_data_available(norm_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_norm(done_norm), + .clk(clk), + .reset(reset) +); + +//////////////////////////////////////////////////////////////// +// Pooling module +//////////////////////////////////////////////////////////////// +pool u_pool( + .enable_pool(enable_pool), + .in_data_available(norm_out_data_available), + .pool_window_size(pool_window_size), + .inp_data(norm_data_out), + .out_data(pool_data_out), + .out_data_available(pool_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_pool(done_pool), + .clk(clk), + .reset(reset) +); + +//////////////////////////////////////////////////////////////// +// Activation module +//////////////////////////////////////////////////////////////// +activation u_activation( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(pool_out_data_available), + .inp_data(pool_data_out), + .out_data(activation_data_out), + .out_data_available(activation_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_activation(done_activation), + .clk(clk), + .reset(reset) +); + +//Interface to BRAM to write the output. +//Ideally, we could remove this flop stage. But then we'd +//have to generate the address for the output BRAM in each +//block that could potentially write the output. +always @(posedge clk) begin + if (reset) begin + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end + else if (activation_out_data_available) begin + bram_wdata_a <= activation_data_out; + bram_addr_a_for_writing <= bram_addr_a_for_writing - address_stride_c; + bram_a_wdata_available <= activation_out_data_available; + end + else begin + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end +end + +endmodule + + diff --git a/designs/koios/tpu_like.small.os/tpu_random.sv b/designs/koios/tpu_like.small.os/tpu_random.sv new file mode 100644 index 000000000..23da3d9d0 --- /dev/null +++ b/designs/koios/tpu_like.small.os/tpu_random.sv @@ -0,0 +1,130 @@ +/* +Random I/Os for TPU +*/ + +`include "../../random_number_generator.sv" + +//The width of the data. This design uses int8 precision. So, DWIDTH is 8 +//To change to a floating point 16 version, change this to 16 and also +//change the datapath components (like adder and multiplier) to be floating point. +`define DWIDTH 8 + +//This is the size of the matrix multiplier unit. In this design, we have a systolic +//matrix multiplication unit that can multiply 16x16 matrix with a 16x16 matrix. +`define DESIGN_SIZE 16 +`define LOG2_DESIGN_SIZE 5 +`define MAT_MUL_SIZE 16 +`define MASK_WIDTH 16 +`define LOG2_MAT_MUL_SIZE 5 + +//This it the size of the address bus, or the depth of the RAM. Each location of +//the RAM is DWIDTH * MAT_MUL_SIZE wide. So, in this design, we use a total of +//1024 * 16 bytes of memory (i.e. 16 KB). +`define AWIDTH 10 + +//This is the number of clock cycles spent in the mac block +`define NUM_CYCLES_IN_MAC 3 + +//This defines the latency of accessing data from a block ram +`define MEM_ACCESS_LATENCY 1 + +//Data width and address width of the APB interface for registers +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 + +//Width of the stride for each column in the matrices (same as ram address width) +`define ADDR_STRIDE_WIDTH 16 + +//Number of bits to specify the pooling window. We support 3 sizes. +`define MAX_BITS_POOL 3 + +module tpu_random( + input wire logic clk, + input wire logic clk_mem, + input wire logic reset, + input wire logic resetn, + input wire logic [`REG_ADDRWIDTH-1:0] PADDR, + input wire logic PWRITE, + input wire logic PSEL, + input wire logic PENABLE, + input wire logic [`REG_DATAWIDTH-1:0] PWDATA, + output logic [`REG_DATAWIDTH-1:0] PRDATA, + output logic PREADY, + input wire logic [`AWIDTH-1:0] bram_addr_a_ext, + input wire logic [`DESIGN_SIZE-1:0] bram_we_a_ext, + input wire logic [`AWIDTH-1:0] bram_addr_b_ext, + input wire logic [`DESIGN_SIZE-1:0] bram_we_b_ext, + input wire logic [4:0] o_sel, + output logic [7:0] o_data +); + +logic [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a_ext; +logic [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b_ext; + +RandomNumberGenerator #( + .RANDOM_WIDTH(`DESIGN_SIZE*`DWIDTH), + .SEED(0) +) rng ( + .clk(clk), + .reset(reset), + .random_number(bram_wdata_a_ext) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(`DESIGN_SIZE*`DWIDTH), + .SEED(0) +) rng2 ( + .clk(clk), + .reset(reset), + .random_number(bram_wdata_b_ext) +); + +logic [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata[1:0]; + +always_comb begin + case(o_sel[4:1]) + 4'd0: o_data = bram_rdata[o_sel[0]][7:0]; + 4'd1: o_data = bram_rdata[o_sel[0]][15:8]; + 4'd2: o_data = bram_rdata[o_sel[0]][23:16]; + 4'd3: o_data = bram_rdata[o_sel[0]][31:24]; + 4'd4: o_data = bram_rdata[o_sel[0]][39:32]; + 4'd5: o_data = bram_rdata[o_sel[0]][47:40]; + 4'd6: o_data = bram_rdata[o_sel[0]][55:48]; + 4'd7: o_data = bram_rdata[o_sel[0]][63:56]; + 4'd8: o_data = bram_rdata[o_sel[0]][71:64]; + 4'd9: o_data = bram_rdata[o_sel[0]][79:72]; + 4'd10: o_data = bram_rdata[o_sel[0]][87:80]; + 4'd11: o_data = bram_rdata[o_sel[0]][95:88]; + 4'd12: o_data = bram_rdata[o_sel[0]][103:96]; + 4'd13: o_data = bram_rdata[o_sel[0]][111:104]; + 4'd14: o_data = bram_rdata[o_sel[0]][119:112]; + 4'd15: o_data = bram_rdata[o_sel[0]][127:120]; + default: o_data = 8'b0; + endcase +end + + + +top tpu0( + clk, + clk_mem, + reset, + resetn, + PADDR, + PWRITE, + PSEL, + PENABLE, + PWDATA, + PRDATA, + PREADY, + bram_addr_a_ext, + bram_rdata[0], + bram_wdata_a_ext, + bram_we_a_ext, + bram_addr_b_ext, + bram_rdata[1], + bram_wdata_b_ext, + bram_we_b_ext +); + +endmodule \ No newline at end of file diff --git a/designs/koios/tpu_like.small.ws/design.yaml b/designs/koios/tpu_like.small.ws/design.yaml new file mode 100644 index 000000000..fd07addb7 --- /dev/null +++ b/designs/koios/tpu_like.small.ws/design.yaml @@ -0,0 +1 @@ +top: tpu_random \ No newline at end of file diff --git a/designs/koios/tpu_like.small.ws/tpu_like.small.ws.v b/designs/koios/tpu_like.small.ws/tpu_like.small.ws.v new file mode 100644 index 000000000..1c2b5c6ab --- /dev/null +++ b/designs/koios/tpu_like.small.ws/tpu_like.small.ws.v @@ -0,0 +1,10537 @@ +`timescale 1ns/1ns +`define VCS +`define MATMUL_SIZE_16 +`define MORE_TESTS +`define DESIGN_SIZE_16 +`define SIMULATION +`define layer_test + +`define DWIDTH 8 +`define AWIDTH 11 +`define MEM_SIZE 2048 + +`ifdef MATMUL_SIZE_4 +`define MAT_MUL_SIZE 4 +`define MASK_WIDTH 4 +`define LOG2_MAT_MUL_SIZE 2 +`endif + +`ifdef MATMUL_SIZE_8 +`define MAT_MUL_SIZE 8 +`define MASK_WIDTH 8 +`define LOG2_MAT_MUL_SIZE 3 +`endif + +`ifdef MATMUL_SIZE_16 +`define MAT_MUL_SIZE 16 +`define MASK_WIDTH 16 +`define LOG2_MAT_MUL_SIZE 4 +`endif + +`ifdef MATMUL_SIZE_32 +`define MAT_MUL_SIZE 32 +`define MASK_WIDTH 32 +`define LOG2_MAT_MUL_SIZE 5 +`endif + +`ifdef DESIGN_SIZE_4 +`define DESIGN_SIZE 4 +`define LOG2_DESIGN_SIZE 2 +`endif + +`ifdef DESIGN_SIZE_8 +`define DESIGN_SIZE 8 +`define LOG2_DESIGN_SIZE 3 +`endif + +`ifdef DESIGN_SIZE_16 +`define DESIGN_SIZE 16 +`define LOG2_DESIGN_SIZE 4 +`endif + +`ifdef DESIGN_SIZE_32 +`define DESIGN_SIZE 32 +`define LOG2_DESIGN_SIZE 5 +`endif + +`define BB_MAT_MUL_SIZE `MAT_MUL_SIZE +`define NUM_CYCLES_IN_MAC 3 +`define MEM_ACCESS_LATENCY 1 +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 +`define ADDR_STRIDE_WIDTH 8 +`define MAX_BITS_POOL 3 + +///////////////////////////////////////////////// +//How to use fully-connected mode? +///////////////////////////////////////////////// +//TODO: See layer test and accum test and write documentation + +///////////////////////////////////////////////// +//How to use convolution mode? +///////////////////////////////////////////////// + +//Matrix A (input activation matrix) +//---------------------------------- +//* This matrix is the non-expanded matrix (ie. this contains +// the same number of elements as the input activation tensor). +// It doesn't contain the expanded GEMM M matrix corresponding +// to this convolution. +//* This matrix is expected to have been padded though. That is, +// if there are any padding rows/columns to be added, the software +// should do that and store the padded matrix in the BRAM. +//* Initial address of matrix A is to be programmed once in the +// beginning of calculation of each output tile. We don't have +// to reprogram the address of A every time during accumulation. +//* The register containing stride of the matrix A is not used +// in convolution mode. Address strides for each read are determined +// on the basis of C,R,S values internally in the RTL. This is because +// strides are not fixed. They vary for every read. +//* This matrix is laid out in NCHW format. + +//Matrix B (weight matrix) +//---------------------------------- +//* This matrix is the non-expanded matrix (ie. this contains +// the same number of elements as the weight tensor). +// It doesn't contain the expanded GEMM N matrix corresponding +// to this convolution. +//* There is no concept of padding for this matrix. +//* Initial address of matrix B is to be programmed once in the +// beginning of calculation of each output tile. We don't have +// to reprogram the address of B every time during accumulation. +//* The register containing stride of the matrix B is not used +// in the RTL. Address strides for each read are determined +// on the basis of C,R,S values internally in the RTL. +//* This matrix is laid out in NCHW format, but it is transposed. +// So technically, the format is WHCN. + +//Matrix C (output activation matrix) +//---------------------------------- +//* This matrix is the non-expanded matrix (ie. this contains +// the same number of elements as the output activation tensor). +// It contains the GEMM matrix corresponding +// to this convolution. +//* There is no concept of padding for this matrix. +//* Initial address of matrix C is to be programmed in the +// beginning of calculation of each output tile. +// There is no concept of programming the address of C for +// accumulation. We write the matrix C only after all accumulations +// have finished. +//* The register containing stride of the matrix C is not used +// in the RTL. That is because the stride is known and is equal to +// out_img_width * out_img_height, and RTL just uses that directly. +//* This matrix is laid out in NCHW format. + +///////////////////////////////////////////////// +//Register specification +///////////////////////////////////////////////// +//--------------------------------------- +//Addr 0 : Register with enables for various blocks. +//Includes mode of operation (convolution or fully_connected) +//--------------------------------------- +`define REG_ENABLES_ADDR 32'h0 +//Bit 0: enable_matmul +//Bit 1: enable_norm +//Bit 2: enable_pool +//Bit 3: enable_activation +//Bit 31: enable_conv_mode + +//--------------------------------------- +//Addr 4: Register that triggers the whole TPU +//--------------------------------------- +`define REG_STDN_TPU_ADDR 32'h4 +//Bit 0: start_tpu +//Bit 31: done_tpu + +//--------------------------------------- +//Addr 8: Register that stores the mean of the values +//--------------------------------------- +`define REG_MEAN_ADDR 32'h8 +//Bit 7:0: mean + +//--------------------------------------- +//Addr A: Register that stores the inverse variance of the values +//--------------------------------------- +`define REG_INV_VAR_ADDR 32'hA +//Bit 7:0: inv_var + +//--------------------------------------- +//Addr E: Register that stores the starting address of matrix A in BRAM A. +//In fully-connected mode, this register should be programmed with the +//address of the matrix being currently multiplied. That is, the +//address of the matrix of the matmul. So, this register will be +//programmed every time the matmul is kicked off during accumulation stages. +//Use the STRIDE registers to tell the matmul to increment addresses. +//In convolution mode, this register should be programmed with the +//address of the input activation matrix. No need to configure +//this every time the matmul is kicked off for accmulation. Just program it +//once it the beginning. Address increments are handled automatically . +//--------------------------------------- +`define REG_MATRIX_A_ADDR 32'he +//Bit `AWIDTH-1:0 address_mat_a + +//--------------------------------------- +//Addr 12: Register that stores the starting address of matrix B in BRAM B. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_B_ADDR 32'h12 +//Bit `AWIDTH-1:0 address_mat_b + +//--------------------------------------- +//Addr 16: Register that stores the starting address of matrix C in BRAM C. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_C_ADDR 32'h16 +//Bit `AWIDTH-1:0 address_mat_c + + + +//--------------------------------------- +//Addr 24: Register that controls the accumulation logic +//--------------------------------------- +`define REG_ACCUM_ACTIONS_ADDR 32'h24 +//Bit 0 save_output_to_accumulator +//Bit 1 add_accumulator_to_output + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 28: Register that stores the stride that should be taken to address +//elements in matrix A, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix A in the vertical +//direction. +//--------------------------------------- +`define REG_MATRIX_A_STRIDE_ADDR 32'h28 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_a + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 32: Register that stores the stride that should be taken to address +//elements in matrix B, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix B in the horizontal +//direction. +//--------------------------------------- +`define REG_MATRIX_B_STRIDE_ADDR 32'h32 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_b + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 36: Register that stores the stride that should be taken to address +//elements in matrix C, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix C in the vertical +//direction (this is generally same as address_stride_a). +//--------------------------------------- +`define REG_MATRIX_C_STRIDE_ADDR 32'h36 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_c + +//--------------------------------------- +//Addr 3A: Register that controls the activation block. Currently, the available +//settings are the selector of activation function that will be used. There are +//two options: ReLU and TanH. To use ReLU, clear the LSB of this register. To +//use TanH, set the LSB of this register. +//--------------------------------------- +`define REG_ACTIVATION_CSR_ADDR 32'h3A + +//--------------------------------------- +//Addr 3E: Register defining pooling window size +//--------------------------------------- +`define REG_POOL_WINDOW_ADDR 32'h3E +//Bit `MAX_BITS_POOL-1:0 pool window size + +//--------------------------------------- +//Addr 40: Register defining convolution parameters - 1 +//---------------------------------------- +`define REG_CONV_PARAMS_1_ADDR 32'h40 +//Bits filter_height (R) 3:0 +//Bits filter width (S) 7:4 +//Bits stride_horizontal 11:8 +//Bits stride_vertical 15:12 +//Bits pad_left 19:16 +//Bits pad_right 23:20 +//Bits pad_top 27:24 +//Bits pad_bottom 31:28 + +//--------------------------------------- +//Addr 44: Register defining convolution parameters - 2 +//---------------------------------------- +`define REG_CONV_PARAMS_2_ADDR 32'h44 +//Bits num_channels_input (C) 15:0 +//Bits num_channels_output (K) 31:16 + +//--------------------------------------- +//Addr 48: Register defining convolution parameters - 3 +//---------------------------------------- +`define REG_CONV_PARAMS_3_ADDR 32'h48 +//Bits input_image_height (H) 15:0 +//Bits input_image_width (W) 31:16 + +//--------------------------------------- +//Addr 4C: Register defining convolution parameters - 4 +//---------------------------------------- +`define REG_CONV_PARAMS_4_ADDR 32'h4C +//Bits output_image_height (P) 15:0 +//Bits output_image_width (Q) 31:16 + +//--------------------------------------- +//Addr 50: Register defining batch size +//---------------------------------------- +`define REG_BATCH_SIZE_ADDR 32'h50 +//Bits 31:0 batch_size (number of images, N) + +//--------------------------------------- +//Addresses 54,58,5C: Registers that stores the mask of which parts of the matrices are valid. +// +//Some examples where this is useful: +//1. Input matrix is smaller than the matmul. +// Say we want to multiply a 6x6 using an 8x8 matmul. +// The matmul still operates on the whole 8x8 part, so we need +// to ensure that there are 0s in the BRAMs in the invalid parts. +// But the mask is used by the blocks other than matmul. For ex, +// norm block will use the mask to avoid applying mean and variance +// to invalid parts (so tha they stay 0). +//2. When we start with large matrices, the size of the matrices can +// reduce to something less than the matmul size because of pooling. +// In that case for the next layer, we need to tell blocks like norm, +// what is valid and what is not. +// +//Note: This masks is applied to both x and y directions and also +//applied to both input matrices - A and B. +//--------------------------------------- +`define REG_VALID_MASK_A_ROWS_ADDR 32'h20 +`define REG_VALID_MASK_A_COLS_B_ROWS_ADDR 32'h54 +`define REG_VALID_MASK_B_COLS_ADDR 32'h58 +//Bit `MASK_WIDTH-1:0 validity_mask + +//--------------------------------------- +//Addr 60-64: Register defining number of design sized matrices +//that the input matrices can be divided into. +//---------------------------------------- +`define REG_NUM_MATRICES_A_ADDR 32'h60 +`define REG_NUM_MATRICES_B_ADDR 32'h64 + +//--------------------------------------- +//Addr 68: Register defining the pooling constants +//---------------------------------------- +`define REG_POOLING_ACCUM_ADDR 32'h68 + +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM generate_matmul.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + +module matmul_16x16_systolic( + clk, + reset, + pe_reset, + start_mat_mul, + done_mat_mul, + num_matrices_A, + num_matrices_B, + address_mat_a, + address_mat_b, + address_stride_a, + address_stride_b, + a_data, + b_data, + a_data_in, // Data values coming in from previous matmul - systolic connections + b_data_in, // Data values coming in from previous matmul - weight matrix + c_data_in, // Data values coming in from previous matmul - systolic shifting + c_data_out, // Data values going out to next matmul - systolic shifting + a_data_out, + b_data_out, + a_addr, + b_addr, + c_addr, + c_data_available, + matrixC15_0, + matrixC15_1, + matrixC15_2, + matrixC15_3, + matrixC15_4, + matrixC15_5, + matrixC15_6, + matrixC15_7, + matrixC15_8, + matrixC15_9, + matrixC15_10, + matrixC15_11, + matrixC15_12, + matrixC15_13, + matrixC15_14, + matrixC15_15, + validity_mask_a_rows, + validity_mask_a_cols_b_rows, + validity_mask_b_cols, + a_loc, + b_loc +); + +input clk; +input reset; +input pe_reset; +input start_mat_mul; +output done_mat_mul; +input [31:0] num_matrices_A; // Number of 16x16 matrices the input matrix can be divided into +input [31:0] num_matrices_B; // Number of 16x16 matrices the weight matrix can be divided into +input [`AWIDTH-1:0] address_mat_a; +input [`AWIDTH-1:0] address_mat_b; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; +output [`AWIDTH-1:0] a_addr; +output [`AWIDTH-1:0] b_addr; +output [`AWIDTH-1:0] c_addr; +output c_data_available; +output [`DWIDTH-1:0] matrixC15_0; +output [`DWIDTH-1:0] matrixC15_1; +output [`DWIDTH-1:0] matrixC15_2; +output [`DWIDTH-1:0] matrixC15_3; +output [`DWIDTH-1:0] matrixC15_4; +output [`DWIDTH-1:0] matrixC15_5; +output [`DWIDTH-1:0] matrixC15_6; +output [`DWIDTH-1:0] matrixC15_7; +output [`DWIDTH-1:0] matrixC15_8; +output [`DWIDTH-1:0] matrixC15_9; +output [`DWIDTH-1:0] matrixC15_10; +output [`DWIDTH-1:0] matrixC15_11; +output [`DWIDTH-1:0] matrixC15_12; +output [`DWIDTH-1:0] matrixC15_13; +output [`DWIDTH-1:0] matrixC15_14; +output [`DWIDTH-1:0] matrixC15_15; +input [`MASK_WIDTH-1:0] validity_mask_a_rows; +input [`MASK_WIDTH-1:0] validity_mask_a_cols_b_rows; +input [`MASK_WIDTH-1:0] validity_mask_b_cols; +input [31:0] a_loc; +input [31:0] b_loc; + +////////////////////////////////////////////////////////////////////////// +// Logic for clock counting and when to assert done +////////////////////////////////////////////////////////////////////////// + +reg done_mat_mul; +// This is set to 31 bits in accordance with the previous simulations. +// In general, a systolic multiplier takes 4*N-2+P cycles, where N is the size +// of the matmul and P is the number of pipeline stages in the MAC block. +reg [31:0] clk_cnt; + +// Finding out number of cycles to assert matmul done. +// When we have to save the outputs to accumulators, then we don't need to +// shift out data. So, we can assert done_mat_mul early. +// Note: the count expression used to contain "num_matrices_16x16*8", but +// to avoid multiplication, we now use "num_matrices_16x16 << 3" +wire [31:0] clk_cnt_for_done; +assign clk_cnt_for_done = +((num_matrices_A << (2*`LOG2_MAT_MUL_SIZE -1)) + 1 + `NUM_CYCLES_IN_MAC) ; + +always @(posedge clk) begin +if (reset || ~start_mat_mul) begin + clk_cnt <= 0; + done_mat_mul <= 0; +end +else if (clk_cnt == clk_cnt_for_done) begin + done_mat_mul <= 1; + clk_cnt <= clk_cnt + 1; +end +else if (done_mat_mul == 0) begin + clk_cnt <= clk_cnt + 1; +end +else begin + done_mat_mul <= 0; + clk_cnt <= clk_cnt + 1; +end +end + +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; +wire [`DWIDTH-1:0] a1_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_1; +wire [`DWIDTH-1:0] a3_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_1; +wire [`DWIDTH-1:0] a4_data_delayed_2; +wire [`DWIDTH-1:0] a4_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_1; +wire [`DWIDTH-1:0] a5_data_delayed_2; +wire [`DWIDTH-1:0] a5_data_delayed_3; +wire [`DWIDTH-1:0] a5_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_1; +wire [`DWIDTH-1:0] a6_data_delayed_2; +wire [`DWIDTH-1:0] a6_data_delayed_3; +wire [`DWIDTH-1:0] a6_data_delayed_4; +wire [`DWIDTH-1:0] a6_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_1; +wire [`DWIDTH-1:0] a7_data_delayed_2; +wire [`DWIDTH-1:0] a7_data_delayed_3; +wire [`DWIDTH-1:0] a7_data_delayed_4; +wire [`DWIDTH-1:0] a7_data_delayed_5; +wire [`DWIDTH-1:0] a7_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_1; +wire [`DWIDTH-1:0] a8_data_delayed_2; +wire [`DWIDTH-1:0] a8_data_delayed_3; +wire [`DWIDTH-1:0] a8_data_delayed_4; +wire [`DWIDTH-1:0] a8_data_delayed_5; +wire [`DWIDTH-1:0] a8_data_delayed_6; +wire [`DWIDTH-1:0] a8_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_1; +wire [`DWIDTH-1:0] a9_data_delayed_2; +wire [`DWIDTH-1:0] a9_data_delayed_3; +wire [`DWIDTH-1:0] a9_data_delayed_4; +wire [`DWIDTH-1:0] a9_data_delayed_5; +wire [`DWIDTH-1:0] a9_data_delayed_6; +wire [`DWIDTH-1:0] a9_data_delayed_7; +wire [`DWIDTH-1:0] a9_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_1; +wire [`DWIDTH-1:0] a10_data_delayed_2; +wire [`DWIDTH-1:0] a10_data_delayed_3; +wire [`DWIDTH-1:0] a10_data_delayed_4; +wire [`DWIDTH-1:0] a10_data_delayed_5; +wire [`DWIDTH-1:0] a10_data_delayed_6; +wire [`DWIDTH-1:0] a10_data_delayed_7; +wire [`DWIDTH-1:0] a10_data_delayed_8; +wire [`DWIDTH-1:0] a10_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_1; +wire [`DWIDTH-1:0] a11_data_delayed_2; +wire [`DWIDTH-1:0] a11_data_delayed_3; +wire [`DWIDTH-1:0] a11_data_delayed_4; +wire [`DWIDTH-1:0] a11_data_delayed_5; +wire [`DWIDTH-1:0] a11_data_delayed_6; +wire [`DWIDTH-1:0] a11_data_delayed_7; +wire [`DWIDTH-1:0] a11_data_delayed_8; +wire [`DWIDTH-1:0] a11_data_delayed_9; +wire [`DWIDTH-1:0] a11_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_1; +wire [`DWIDTH-1:0] a12_data_delayed_2; +wire [`DWIDTH-1:0] a12_data_delayed_3; +wire [`DWIDTH-1:0] a12_data_delayed_4; +wire [`DWIDTH-1:0] a12_data_delayed_5; +wire [`DWIDTH-1:0] a12_data_delayed_6; +wire [`DWIDTH-1:0] a12_data_delayed_7; +wire [`DWIDTH-1:0] a12_data_delayed_8; +wire [`DWIDTH-1:0] a12_data_delayed_9; +wire [`DWIDTH-1:0] a12_data_delayed_10; +wire [`DWIDTH-1:0] a12_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_1; +wire [`DWIDTH-1:0] a13_data_delayed_2; +wire [`DWIDTH-1:0] a13_data_delayed_3; +wire [`DWIDTH-1:0] a13_data_delayed_4; +wire [`DWIDTH-1:0] a13_data_delayed_5; +wire [`DWIDTH-1:0] a13_data_delayed_6; +wire [`DWIDTH-1:0] a13_data_delayed_7; +wire [`DWIDTH-1:0] a13_data_delayed_8; +wire [`DWIDTH-1:0] a13_data_delayed_9; +wire [`DWIDTH-1:0] a13_data_delayed_10; +wire [`DWIDTH-1:0] a13_data_delayed_11; +wire [`DWIDTH-1:0] a13_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_1; +wire [`DWIDTH-1:0] a14_data_delayed_2; +wire [`DWIDTH-1:0] a14_data_delayed_3; +wire [`DWIDTH-1:0] a14_data_delayed_4; +wire [`DWIDTH-1:0] a14_data_delayed_5; +wire [`DWIDTH-1:0] a14_data_delayed_6; +wire [`DWIDTH-1:0] a14_data_delayed_7; +wire [`DWIDTH-1:0] a14_data_delayed_8; +wire [`DWIDTH-1:0] a14_data_delayed_9; +wire [`DWIDTH-1:0] a14_data_delayed_10; +wire [`DWIDTH-1:0] a14_data_delayed_11; +wire [`DWIDTH-1:0] a14_data_delayed_12; +wire [`DWIDTH-1:0] a14_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_1; +wire [`DWIDTH-1:0] a15_data_delayed_2; +wire [`DWIDTH-1:0] a15_data_delayed_3; +wire [`DWIDTH-1:0] a15_data_delayed_4; +wire [`DWIDTH-1:0] a15_data_delayed_5; +wire [`DWIDTH-1:0] a15_data_delayed_6; +wire [`DWIDTH-1:0] a15_data_delayed_7; +wire [`DWIDTH-1:0] a15_data_delayed_8; +wire [`DWIDTH-1:0] a15_data_delayed_9; +wire [`DWIDTH-1:0] a15_data_delayed_10; +wire [`DWIDTH-1:0] a15_data_delayed_11; +wire [`DWIDTH-1:0] a15_data_delayed_12; +wire [`DWIDTH-1:0] a15_data_delayed_13; +wire [`DWIDTH-1:0] a15_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_15; +wire [`DWIDTH-1:0] b1_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_1; +wire [`DWIDTH-1:0] b3_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_3; +wire [`DWIDTH-1:0] b4_data_delayed_1; +wire [`DWIDTH-1:0] b4_data_delayed_2; +wire [`DWIDTH-1:0] b4_data_delayed_3; +wire [`DWIDTH-1:0] b4_data_delayed_4; +wire [`DWIDTH-1:0] b5_data_delayed_1; +wire [`DWIDTH-1:0] b5_data_delayed_2; +wire [`DWIDTH-1:0] b5_data_delayed_3; +wire [`DWIDTH-1:0] b5_data_delayed_4; +wire [`DWIDTH-1:0] b5_data_delayed_5; +wire [`DWIDTH-1:0] b6_data_delayed_1; +wire [`DWIDTH-1:0] b6_data_delayed_2; +wire [`DWIDTH-1:0] b6_data_delayed_3; +wire [`DWIDTH-1:0] b6_data_delayed_4; +wire [`DWIDTH-1:0] b6_data_delayed_5; +wire [`DWIDTH-1:0] b6_data_delayed_6; +wire [`DWIDTH-1:0] b7_data_delayed_1; +wire [`DWIDTH-1:0] b7_data_delayed_2; +wire [`DWIDTH-1:0] b7_data_delayed_3; +wire [`DWIDTH-1:0] b7_data_delayed_4; +wire [`DWIDTH-1:0] b7_data_delayed_5; +wire [`DWIDTH-1:0] b7_data_delayed_6; +wire [`DWIDTH-1:0] b7_data_delayed_7; +wire [`DWIDTH-1:0] b8_data_delayed_1; +wire [`DWIDTH-1:0] b8_data_delayed_2; +wire [`DWIDTH-1:0] b8_data_delayed_3; +wire [`DWIDTH-1:0] b8_data_delayed_4; +wire [`DWIDTH-1:0] b8_data_delayed_5; +wire [`DWIDTH-1:0] b8_data_delayed_6; +wire [`DWIDTH-1:0] b8_data_delayed_7; +wire [`DWIDTH-1:0] b8_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_1; +wire [`DWIDTH-1:0] b9_data_delayed_2; +wire [`DWIDTH-1:0] b9_data_delayed_3; +wire [`DWIDTH-1:0] b9_data_delayed_4; +wire [`DWIDTH-1:0] b9_data_delayed_5; +wire [`DWIDTH-1:0] b9_data_delayed_6; +wire [`DWIDTH-1:0] b9_data_delayed_7; +wire [`DWIDTH-1:0] b9_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_1; +wire [`DWIDTH-1:0] b10_data_delayed_2; +wire [`DWIDTH-1:0] b10_data_delayed_3; +wire [`DWIDTH-1:0] b10_data_delayed_4; +wire [`DWIDTH-1:0] b10_data_delayed_5; +wire [`DWIDTH-1:0] b10_data_delayed_6; +wire [`DWIDTH-1:0] b10_data_delayed_7; +wire [`DWIDTH-1:0] b10_data_delayed_8; +wire [`DWIDTH-1:0] b10_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_1; +wire [`DWIDTH-1:0] b11_data_delayed_2; +wire [`DWIDTH-1:0] b11_data_delayed_3; +wire [`DWIDTH-1:0] b11_data_delayed_4; +wire [`DWIDTH-1:0] b11_data_delayed_5; +wire [`DWIDTH-1:0] b11_data_delayed_6; +wire [`DWIDTH-1:0] b11_data_delayed_7; +wire [`DWIDTH-1:0] b11_data_delayed_8; +wire [`DWIDTH-1:0] b11_data_delayed_9; +wire [`DWIDTH-1:0] b11_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_1; +wire [`DWIDTH-1:0] b12_data_delayed_2; +wire [`DWIDTH-1:0] b12_data_delayed_3; +wire [`DWIDTH-1:0] b12_data_delayed_4; +wire [`DWIDTH-1:0] b12_data_delayed_5; +wire [`DWIDTH-1:0] b12_data_delayed_6; +wire [`DWIDTH-1:0] b12_data_delayed_7; +wire [`DWIDTH-1:0] b12_data_delayed_8; +wire [`DWIDTH-1:0] b12_data_delayed_9; +wire [`DWIDTH-1:0] b12_data_delayed_10; +wire [`DWIDTH-1:0] b12_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_1; +wire [`DWIDTH-1:0] b13_data_delayed_2; +wire [`DWIDTH-1:0] b13_data_delayed_3; +wire [`DWIDTH-1:0] b13_data_delayed_4; +wire [`DWIDTH-1:0] b13_data_delayed_5; +wire [`DWIDTH-1:0] b13_data_delayed_6; +wire [`DWIDTH-1:0] b13_data_delayed_7; +wire [`DWIDTH-1:0] b13_data_delayed_8; +wire [`DWIDTH-1:0] b13_data_delayed_9; +wire [`DWIDTH-1:0] b13_data_delayed_10; +wire [`DWIDTH-1:0] b13_data_delayed_11; +wire [`DWIDTH-1:0] b13_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_1; +wire [`DWIDTH-1:0] b14_data_delayed_2; +wire [`DWIDTH-1:0] b14_data_delayed_3; +wire [`DWIDTH-1:0] b14_data_delayed_4; +wire [`DWIDTH-1:0] b14_data_delayed_5; +wire [`DWIDTH-1:0] b14_data_delayed_6; +wire [`DWIDTH-1:0] b14_data_delayed_7; +wire [`DWIDTH-1:0] b14_data_delayed_8; +wire [`DWIDTH-1:0] b14_data_delayed_9; +wire [`DWIDTH-1:0] b14_data_delayed_10; +wire [`DWIDTH-1:0] b14_data_delayed_11; +wire [`DWIDTH-1:0] b14_data_delayed_12; +wire [`DWIDTH-1:0] b14_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_1; +wire [`DWIDTH-1:0] b15_data_delayed_2; +wire [`DWIDTH-1:0] b15_data_delayed_3; +wire [`DWIDTH-1:0] b15_data_delayed_4; +wire [`DWIDTH-1:0] b15_data_delayed_5; +wire [`DWIDTH-1:0] b15_data_delayed_6; +wire [`DWIDTH-1:0] b15_data_delayed_7; +wire [`DWIDTH-1:0] b15_data_delayed_8; +wire [`DWIDTH-1:0] b15_data_delayed_9; +wire [`DWIDTH-1:0] b15_data_delayed_10; +wire [`DWIDTH-1:0] b15_data_delayed_11; +wire [`DWIDTH-1:0] b15_data_delayed_12; +wire [`DWIDTH-1:0] b15_data_delayed_13; +wire [`DWIDTH-1:0] b15_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_15; + +reg b_data_sel; // MUX select for Ping-Pong buffers containing the weights in the matmul +reg b_data_valid_ping; +reg b_data_valid_pong; + +always @ (posedge clk) begin + if ((clk_cnt >= 16'd1 && clk_cnt <= 16'd8)||(clk_cnt >= 16'd17 && clk_cnt <= 16'd24)) + b_data_valid_pong <= 1'b1; + else + b_data_valid_pong <= 1'b0; +end + +always @ (posedge clk) begin + if ((clk_cnt >= 16'd9 && clk_cnt <= 16'd16)) + b_data_valid_ping <= 1'b1; + else + b_data_valid_ping <= 1'b0; +end + +always @ (posedge clk) begin + if ((clk_cnt >= 16'd10 && clk_cnt <= 16'd17)||(clk_cnt >= 16'd26 && clk_cnt <= 16'd33)) + b_data_sel <= 1'b1; + else + b_data_sel <= 1'b0; +end + +////////////////////////////////////////////////////////////////////////// +// Instantiation of systolic data setup +////////////////////////////////////////////////////////////////////////// +systolic_data_setup u_systolic_data_setup( + .clk(clk), + .reset(reset), + .start_mat_mul(start_mat_mul), + .a_addr(a_addr), + .b_addr(b_addr), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .a_data(a_data), + .b_data(b_data), + .clk_cnt(clk_cnt), + .a0_data(a0_data), + .a1_data_delayed_1(a1_data_delayed_1), + .a2_data_delayed_2(a2_data_delayed_2), + .a3_data_delayed_3(a3_data_delayed_3), + .a4_data_delayed_4(a4_data_delayed_4), + .a5_data_delayed_5(a5_data_delayed_5), + .a6_data_delayed_6(a6_data_delayed_6), + .a7_data_delayed_7(a7_data_delayed_7), + .a8_data_delayed_8(a8_data_delayed_8), + .a9_data_delayed_9(a9_data_delayed_9), + .a10_data_delayed_10(a10_data_delayed_10), + .a11_data_delayed_11(a11_data_delayed_11), + .a12_data_delayed_12(a12_data_delayed_12), + .a13_data_delayed_13(a13_data_delayed_13), + .a14_data_delayed_14(a14_data_delayed_14), + .a15_data_delayed_15(a15_data_delayed_15), + .b0_data(b0_data), + .b1_data_delayed_1(b1_data_delayed_1), + .b2_data_delayed_2(b2_data_delayed_2), + .b3_data_delayed_3(b3_data_delayed_3), + .b4_data_delayed_4(b4_data_delayed_4), + .b5_data_delayed_5(b5_data_delayed_5), + .b6_data_delayed_6(b6_data_delayed_6), + .b7_data_delayed_7(b7_data_delayed_7), + .b8_data_delayed_8(b8_data_delayed_8), + .b9_data_delayed_9(b9_data_delayed_9), + .b10_data_delayed_10(b10_data_delayed_10), + .b11_data_delayed_11(b11_data_delayed_11), + .b12_data_delayed_12(b12_data_delayed_12), + .b13_data_delayed_13(b13_data_delayed_13), + .b14_data_delayed_14(b14_data_delayed_14), + .b15_data_delayed_15(b15_data_delayed_15), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols_b_rows(validity_mask_a_cols_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .num_matrices_A(num_matrices_A), + .num_matrices_B(num_matrices_B), + .a_loc(a_loc), + .b_loc(b_loc) +); + +////////////////////////////////////////////////////////////////////////// +// Logic to mux data_in coming from neighboring matmuls +////////////////////////////////////////////////////////////////////////// +wire [`DWIDTH-1:0] a0; +wire [`DWIDTH-1:0] a1; +wire [`DWIDTH-1:0] a2; +wire [`DWIDTH-1:0] a3; +wire [`DWIDTH-1:0] a4; +wire [`DWIDTH-1:0] a5; +wire [`DWIDTH-1:0] a6; +wire [`DWIDTH-1:0] a7; +wire [`DWIDTH-1:0] a8; +wire [`DWIDTH-1:0] a9; +wire [`DWIDTH-1:0] a10; +wire [`DWIDTH-1:0] a11; +wire [`DWIDTH-1:0] a12; +wire [`DWIDTH-1:0] a13; +wire [`DWIDTH-1:0] a14; +wire [`DWIDTH-1:0] a15; +wire [`DWIDTH-1:0] b0; +wire [`DWIDTH-1:0] b1; +wire [`DWIDTH-1:0] b2; +wire [`DWIDTH-1:0] b3; +wire [`DWIDTH-1:0] b4; +wire [`DWIDTH-1:0] b5; +wire [`DWIDTH-1:0] b6; +wire [`DWIDTH-1:0] b7; +wire [`DWIDTH-1:0] b8; +wire [`DWIDTH-1:0] b9; +wire [`DWIDTH-1:0] b10; +wire [`DWIDTH-1:0] b11; +wire [`DWIDTH-1:0] b12; +wire [`DWIDTH-1:0] b13; +wire [`DWIDTH-1:0] b14; +wire [`DWIDTH-1:0] b15; +wire [`DWIDTH-1:0] c0; +wire [`DWIDTH-1:0] c1; +wire [`DWIDTH-1:0] c2; +wire [`DWIDTH-1:0] c3; +wire [`DWIDTH-1:0] c4; +wire [`DWIDTH-1:0] c5; +wire [`DWIDTH-1:0] c6; +wire [`DWIDTH-1:0] c7; +wire [`DWIDTH-1:0] c8; +wire [`DWIDTH-1:0] c9; +wire [`DWIDTH-1:0] c10; +wire [`DWIDTH-1:0] c11; +wire [`DWIDTH-1:0] c12; +wire [`DWIDTH-1:0] c13; +wire [`DWIDTH-1:0] c14; +wire [`DWIDTH-1:0] c15; + +wire [`DWIDTH-1:0] a0_data_in; +wire [`DWIDTH-1:0] a1_data_in; +wire [`DWIDTH-1:0] a2_data_in; +wire [`DWIDTH-1:0] a3_data_in; +wire [`DWIDTH-1:0] a4_data_in; +wire [`DWIDTH-1:0] a5_data_in; +wire [`DWIDTH-1:0] a6_data_in; +wire [`DWIDTH-1:0] a7_data_in; +wire [`DWIDTH-1:0] a8_data_in; +wire [`DWIDTH-1:0] a9_data_in; +wire [`DWIDTH-1:0] a10_data_in; +wire [`DWIDTH-1:0] a11_data_in; +wire [`DWIDTH-1:0] a12_data_in; +wire [`DWIDTH-1:0] a13_data_in; +wire [`DWIDTH-1:0] a14_data_in; +wire [`DWIDTH-1:0] a15_data_in; +assign a0_data_in = a_data_in[`DWIDTH-1:0]; +assign a1_data_in = a_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign a2_data_in = a_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign a3_data_in = a_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign a4_data_in = a_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign a5_data_in = a_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign a6_data_in = a_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign a7_data_in = a_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign a8_data_in = a_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign a9_data_in = a_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign a10_data_in = a_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign a11_data_in = a_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign a12_data_in = a_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign a13_data_in = a_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign a14_data_in = a_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign a15_data_in = a_data_in[16*`DWIDTH-1:15*`DWIDTH]; + +wire [`DWIDTH-1:0] b0_data_in; +wire [`DWIDTH-1:0] b1_data_in; +wire [`DWIDTH-1:0] b2_data_in; +wire [`DWIDTH-1:0] b3_data_in; +wire [`DWIDTH-1:0] b4_data_in; +wire [`DWIDTH-1:0] b5_data_in; +wire [`DWIDTH-1:0] b6_data_in; +wire [`DWIDTH-1:0] b7_data_in; +wire [`DWIDTH-1:0] b8_data_in; +wire [`DWIDTH-1:0] b9_data_in; +wire [`DWIDTH-1:0] b10_data_in; +wire [`DWIDTH-1:0] b11_data_in; +wire [`DWIDTH-1:0] b12_data_in; +wire [`DWIDTH-1:0] b13_data_in; +wire [`DWIDTH-1:0] b14_data_in; +wire [`DWIDTH-1:0] b15_data_in; +assign b0_data_in = b_data_in[`DWIDTH-1:0]; +assign b1_data_in = b_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign b2_data_in = b_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign b3_data_in = b_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign b4_data_in = b_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign b5_data_in = b_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign b6_data_in = b_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign b7_data_in = b_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign b8_data_in = b_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign b9_data_in = b_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign b10_data_in = b_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign b11_data_in = b_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign b12_data_in = b_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign b13_data_in = b_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign b14_data_in = b_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign b15_data_in = b_data_in[16*`DWIDTH-1:15*`DWIDTH]; + +// If b_loc is 0, that means this matmul block is on the top-row of the +// final large matmul. In that case, b will take inputs from mem. +// If b_loc != 0, that means this matmul block is not on the top-row of the +// final large matmul. In that case, b will take inputs from the matmul on top +// of this one. +assign a0 = (b_loc==0) ? a0_data : a0_data_in; +assign a1 = (b_loc==0) ? a1_data_delayed_1 : a1_data_in; +assign a2 = (b_loc==0) ? a2_data_delayed_2 : a2_data_in; +assign a3 = (b_loc==0) ? a3_data_delayed_3 : a3_data_in; +assign a4 = (b_loc==0) ? a4_data_delayed_4 : a4_data_in; +assign a5 = (b_loc==0) ? a5_data_delayed_5 : a5_data_in; +assign a6 = (b_loc==0) ? a6_data_delayed_6 : a6_data_in; +assign a7 = (b_loc==0) ? a7_data_delayed_7 : a7_data_in; +assign a8 = (b_loc==0) ? a8_data_delayed_8 : a8_data_in; +assign a9 = (b_loc==0) ? a9_data_delayed_9 : a9_data_in; +assign a10 = (b_loc==0) ? a10_data_delayed_10 : a10_data_in; +assign a11 = (b_loc==0) ? a11_data_delayed_11 : a11_data_in; +assign a12 = (b_loc==0) ? a12_data_delayed_12 : a12_data_in; +assign a13 = (b_loc==0) ? a13_data_delayed_13 : a13_data_in; +assign a14 = (b_loc==0) ? a14_data_delayed_14 : a14_data_in; +assign a15 = (b_loc==0) ? a15_data_delayed_15 : a15_data_in; + +/// If a_loc is 0, that means this matmul block is on the left-col of the +// final large matmul. In that case, a will take inputs from mem. +// If a_loc != 0, that means this matmul block is not on the left-col of the +// final large matmul. In that case, a will take inputs from the matmul on left +// of this one. +assign b0 = (a_loc==0) ? b0_data : b0_data_in; +assign b1 = (a_loc==0) ? b1_data_delayed_1 : b1_data_in; +assign b2 = (a_loc==0) ? b2_data_delayed_2 : b2_data_in; +assign b3 = (a_loc==0) ? b3_data_delayed_3 : b3_data_in; +assign b4 = (a_loc==0) ? b4_data_delayed_4 : b4_data_in; +assign b5 = (a_loc==0) ? b5_data_delayed_5 : b5_data_in; +assign b6 = (a_loc==0) ? b6_data_delayed_6 : b6_data_in; +assign b7 = (a_loc==0) ? b7_data_delayed_7 : b7_data_in; +assign b8 = (a_loc==0) ? b8_data_delayed_8 : b8_data_in; +assign b9 = (a_loc==0) ? b9_data_delayed_9 : b9_data_in; +assign b10 = (a_loc==0) ? b10_data_delayed_10 : b10_data_in; +assign b11 = (a_loc==0) ? b11_data_delayed_11 : b11_data_in; +assign b12 = (a_loc==0) ? b12_data_delayed_12 : b12_data_in; +assign b13 = (a_loc==0) ? b13_data_delayed_13 : b13_data_in; +assign b14 = (a_loc==0) ? b14_data_delayed_14 : b14_data_in; +assign b15 = (a_loc==0) ? b15_data_delayed_15 : b15_data_in; + +assign c0 = c_data_in[`DWIDTH-1:0]; +assign c1 = c_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign c2 = c_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign c3 = c_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign c4 = c_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign c5 = c_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign c6 = c_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign c7 = c_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign c8 = c_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign c9 = c_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign c10 = c_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign c11 = c_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign c12 = c_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign c13 = c_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign c14 = c_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign c15 = c_data_in[16*`DWIDTH-1:15*`DWIDTH]; + +wire [`DWIDTH-1:0] matrixC0_0; +wire [`DWIDTH-1:0] matrixC0_1; +wire [`DWIDTH-1:0] matrixC0_2; +wire [`DWIDTH-1:0] matrixC0_3; +wire [`DWIDTH-1:0] matrixC0_4; +wire [`DWIDTH-1:0] matrixC0_5; +wire [`DWIDTH-1:0] matrixC0_6; +wire [`DWIDTH-1:0] matrixC0_7; +wire [`DWIDTH-1:0] matrixC0_8; +wire [`DWIDTH-1:0] matrixC0_9; +wire [`DWIDTH-1:0] matrixC0_10; +wire [`DWIDTH-1:0] matrixC0_11; +wire [`DWIDTH-1:0] matrixC0_12; +wire [`DWIDTH-1:0] matrixC0_13; +wire [`DWIDTH-1:0] matrixC0_14; +wire [`DWIDTH-1:0] matrixC0_15; +wire [`DWIDTH-1:0] matrixC1_0; +wire [`DWIDTH-1:0] matrixC1_1; +wire [`DWIDTH-1:0] matrixC1_2; +wire [`DWIDTH-1:0] matrixC1_3; +wire [`DWIDTH-1:0] matrixC1_4; +wire [`DWIDTH-1:0] matrixC1_5; +wire [`DWIDTH-1:0] matrixC1_6; +wire [`DWIDTH-1:0] matrixC1_7; +wire [`DWIDTH-1:0] matrixC1_8; +wire [`DWIDTH-1:0] matrixC1_9; +wire [`DWIDTH-1:0] matrixC1_10; +wire [`DWIDTH-1:0] matrixC1_11; +wire [`DWIDTH-1:0] matrixC1_12; +wire [`DWIDTH-1:0] matrixC1_13; +wire [`DWIDTH-1:0] matrixC1_14; +wire [`DWIDTH-1:0] matrixC1_15; +wire [`DWIDTH-1:0] matrixC2_0; +wire [`DWIDTH-1:0] matrixC2_1; +wire [`DWIDTH-1:0] matrixC2_2; +wire [`DWIDTH-1:0] matrixC2_3; +wire [`DWIDTH-1:0] matrixC2_4; +wire [`DWIDTH-1:0] matrixC2_5; +wire [`DWIDTH-1:0] matrixC2_6; +wire [`DWIDTH-1:0] matrixC2_7; +wire [`DWIDTH-1:0] matrixC2_8; +wire [`DWIDTH-1:0] matrixC2_9; +wire [`DWIDTH-1:0] matrixC2_10; +wire [`DWIDTH-1:0] matrixC2_11; +wire [`DWIDTH-1:0] matrixC2_12; +wire [`DWIDTH-1:0] matrixC2_13; +wire [`DWIDTH-1:0] matrixC2_14; +wire [`DWIDTH-1:0] matrixC2_15; +wire [`DWIDTH-1:0] matrixC3_0; +wire [`DWIDTH-1:0] matrixC3_1; +wire [`DWIDTH-1:0] matrixC3_2; +wire [`DWIDTH-1:0] matrixC3_3; +wire [`DWIDTH-1:0] matrixC3_4; +wire [`DWIDTH-1:0] matrixC3_5; +wire [`DWIDTH-1:0] matrixC3_6; +wire [`DWIDTH-1:0] matrixC3_7; +wire [`DWIDTH-1:0] matrixC3_8; +wire [`DWIDTH-1:0] matrixC3_9; +wire [`DWIDTH-1:0] matrixC3_10; +wire [`DWIDTH-1:0] matrixC3_11; +wire [`DWIDTH-1:0] matrixC3_12; +wire [`DWIDTH-1:0] matrixC3_13; +wire [`DWIDTH-1:0] matrixC3_14; +wire [`DWIDTH-1:0] matrixC3_15; +wire [`DWIDTH-1:0] matrixC4_0; +wire [`DWIDTH-1:0] matrixC4_1; +wire [`DWIDTH-1:0] matrixC4_2; +wire [`DWIDTH-1:0] matrixC4_3; +wire [`DWIDTH-1:0] matrixC4_4; +wire [`DWIDTH-1:0] matrixC4_5; +wire [`DWIDTH-1:0] matrixC4_6; +wire [`DWIDTH-1:0] matrixC4_7; +wire [`DWIDTH-1:0] matrixC4_8; +wire [`DWIDTH-1:0] matrixC4_9; +wire [`DWIDTH-1:0] matrixC4_10; +wire [`DWIDTH-1:0] matrixC4_11; +wire [`DWIDTH-1:0] matrixC4_12; +wire [`DWIDTH-1:0] matrixC4_13; +wire [`DWIDTH-1:0] matrixC4_14; +wire [`DWIDTH-1:0] matrixC4_15; +wire [`DWIDTH-1:0] matrixC5_0; +wire [`DWIDTH-1:0] matrixC5_1; +wire [`DWIDTH-1:0] matrixC5_2; +wire [`DWIDTH-1:0] matrixC5_3; +wire [`DWIDTH-1:0] matrixC5_4; +wire [`DWIDTH-1:0] matrixC5_5; +wire [`DWIDTH-1:0] matrixC5_6; +wire [`DWIDTH-1:0] matrixC5_7; +wire [`DWIDTH-1:0] matrixC5_8; +wire [`DWIDTH-1:0] matrixC5_9; +wire [`DWIDTH-1:0] matrixC5_10; +wire [`DWIDTH-1:0] matrixC5_11; +wire [`DWIDTH-1:0] matrixC5_12; +wire [`DWIDTH-1:0] matrixC5_13; +wire [`DWIDTH-1:0] matrixC5_14; +wire [`DWIDTH-1:0] matrixC5_15; +wire [`DWIDTH-1:0] matrixC6_0; +wire [`DWIDTH-1:0] matrixC6_1; +wire [`DWIDTH-1:0] matrixC6_2; +wire [`DWIDTH-1:0] matrixC6_3; +wire [`DWIDTH-1:0] matrixC6_4; +wire [`DWIDTH-1:0] matrixC6_5; +wire [`DWIDTH-1:0] matrixC6_6; +wire [`DWIDTH-1:0] matrixC6_7; +wire [`DWIDTH-1:0] matrixC6_8; +wire [`DWIDTH-1:0] matrixC6_9; +wire [`DWIDTH-1:0] matrixC6_10; +wire [`DWIDTH-1:0] matrixC6_11; +wire [`DWIDTH-1:0] matrixC6_12; +wire [`DWIDTH-1:0] matrixC6_13; +wire [`DWIDTH-1:0] matrixC6_14; +wire [`DWIDTH-1:0] matrixC6_15; +wire [`DWIDTH-1:0] matrixC7_0; +wire [`DWIDTH-1:0] matrixC7_1; +wire [`DWIDTH-1:0] matrixC7_2; +wire [`DWIDTH-1:0] matrixC7_3; +wire [`DWIDTH-1:0] matrixC7_4; +wire [`DWIDTH-1:0] matrixC7_5; +wire [`DWIDTH-1:0] matrixC7_6; +wire [`DWIDTH-1:0] matrixC7_7; +wire [`DWIDTH-1:0] matrixC7_8; +wire [`DWIDTH-1:0] matrixC7_9; +wire [`DWIDTH-1:0] matrixC7_10; +wire [`DWIDTH-1:0] matrixC7_11; +wire [`DWIDTH-1:0] matrixC7_12; +wire [`DWIDTH-1:0] matrixC7_13; +wire [`DWIDTH-1:0] matrixC7_14; +wire [`DWIDTH-1:0] matrixC7_15; +wire [`DWIDTH-1:0] matrixC8_0; +wire [`DWIDTH-1:0] matrixC8_1; +wire [`DWIDTH-1:0] matrixC8_2; +wire [`DWIDTH-1:0] matrixC8_3; +wire [`DWIDTH-1:0] matrixC8_4; +wire [`DWIDTH-1:0] matrixC8_5; +wire [`DWIDTH-1:0] matrixC8_6; +wire [`DWIDTH-1:0] matrixC8_7; +wire [`DWIDTH-1:0] matrixC8_8; +wire [`DWIDTH-1:0] matrixC8_9; +wire [`DWIDTH-1:0] matrixC8_10; +wire [`DWIDTH-1:0] matrixC8_11; +wire [`DWIDTH-1:0] matrixC8_12; +wire [`DWIDTH-1:0] matrixC8_13; +wire [`DWIDTH-1:0] matrixC8_14; +wire [`DWIDTH-1:0] matrixC8_15; +wire [`DWIDTH-1:0] matrixC9_0; +wire [`DWIDTH-1:0] matrixC9_1; +wire [`DWIDTH-1:0] matrixC9_2; +wire [`DWIDTH-1:0] matrixC9_3; +wire [`DWIDTH-1:0] matrixC9_4; +wire [`DWIDTH-1:0] matrixC9_5; +wire [`DWIDTH-1:0] matrixC9_6; +wire [`DWIDTH-1:0] matrixC9_7; +wire [`DWIDTH-1:0] matrixC9_8; +wire [`DWIDTH-1:0] matrixC9_9; +wire [`DWIDTH-1:0] matrixC9_10; +wire [`DWIDTH-1:0] matrixC9_11; +wire [`DWIDTH-1:0] matrixC9_12; +wire [`DWIDTH-1:0] matrixC9_13; +wire [`DWIDTH-1:0] matrixC9_14; +wire [`DWIDTH-1:0] matrixC9_15; +wire [`DWIDTH-1:0] matrixC10_0; +wire [`DWIDTH-1:0] matrixC10_1; +wire [`DWIDTH-1:0] matrixC10_2; +wire [`DWIDTH-1:0] matrixC10_3; +wire [`DWIDTH-1:0] matrixC10_4; +wire [`DWIDTH-1:0] matrixC10_5; +wire [`DWIDTH-1:0] matrixC10_6; +wire [`DWIDTH-1:0] matrixC10_7; +wire [`DWIDTH-1:0] matrixC10_8; +wire [`DWIDTH-1:0] matrixC10_9; +wire [`DWIDTH-1:0] matrixC10_10; +wire [`DWIDTH-1:0] matrixC10_11; +wire [`DWIDTH-1:0] matrixC10_12; +wire [`DWIDTH-1:0] matrixC10_13; +wire [`DWIDTH-1:0] matrixC10_14; +wire [`DWIDTH-1:0] matrixC10_15; +wire [`DWIDTH-1:0] matrixC11_0; +wire [`DWIDTH-1:0] matrixC11_1; +wire [`DWIDTH-1:0] matrixC11_2; +wire [`DWIDTH-1:0] matrixC11_3; +wire [`DWIDTH-1:0] matrixC11_4; +wire [`DWIDTH-1:0] matrixC11_5; +wire [`DWIDTH-1:0] matrixC11_6; +wire [`DWIDTH-1:0] matrixC11_7; +wire [`DWIDTH-1:0] matrixC11_8; +wire [`DWIDTH-1:0] matrixC11_9; +wire [`DWIDTH-1:0] matrixC11_10; +wire [`DWIDTH-1:0] matrixC11_11; +wire [`DWIDTH-1:0] matrixC11_12; +wire [`DWIDTH-1:0] matrixC11_13; +wire [`DWIDTH-1:0] matrixC11_14; +wire [`DWIDTH-1:0] matrixC11_15; +wire [`DWIDTH-1:0] matrixC12_0; +wire [`DWIDTH-1:0] matrixC12_1; +wire [`DWIDTH-1:0] matrixC12_2; +wire [`DWIDTH-1:0] matrixC12_3; +wire [`DWIDTH-1:0] matrixC12_4; +wire [`DWIDTH-1:0] matrixC12_5; +wire [`DWIDTH-1:0] matrixC12_6; +wire [`DWIDTH-1:0] matrixC12_7; +wire [`DWIDTH-1:0] matrixC12_8; +wire [`DWIDTH-1:0] matrixC12_9; +wire [`DWIDTH-1:0] matrixC12_10; +wire [`DWIDTH-1:0] matrixC12_11; +wire [`DWIDTH-1:0] matrixC12_12; +wire [`DWIDTH-1:0] matrixC12_13; +wire [`DWIDTH-1:0] matrixC12_14; +wire [`DWIDTH-1:0] matrixC12_15; +wire [`DWIDTH-1:0] matrixC13_0; +wire [`DWIDTH-1:0] matrixC13_1; +wire [`DWIDTH-1:0] matrixC13_2; +wire [`DWIDTH-1:0] matrixC13_3; +wire [`DWIDTH-1:0] matrixC13_4; +wire [`DWIDTH-1:0] matrixC13_5; +wire [`DWIDTH-1:0] matrixC13_6; +wire [`DWIDTH-1:0] matrixC13_7; +wire [`DWIDTH-1:0] matrixC13_8; +wire [`DWIDTH-1:0] matrixC13_9; +wire [`DWIDTH-1:0] matrixC13_10; +wire [`DWIDTH-1:0] matrixC13_11; +wire [`DWIDTH-1:0] matrixC13_12; +wire [`DWIDTH-1:0] matrixC13_13; +wire [`DWIDTH-1:0] matrixC13_14; +wire [`DWIDTH-1:0] matrixC13_15; +wire [`DWIDTH-1:0] matrixC14_0; +wire [`DWIDTH-1:0] matrixC14_1; +wire [`DWIDTH-1:0] matrixC14_2; +wire [`DWIDTH-1:0] matrixC14_3; +wire [`DWIDTH-1:0] matrixC14_4; +wire [`DWIDTH-1:0] matrixC14_5; +wire [`DWIDTH-1:0] matrixC14_6; +wire [`DWIDTH-1:0] matrixC14_7; +wire [`DWIDTH-1:0] matrixC14_8; +wire [`DWIDTH-1:0] matrixC14_9; +wire [`DWIDTH-1:0] matrixC14_10; +wire [`DWIDTH-1:0] matrixC14_11; +wire [`DWIDTH-1:0] matrixC14_12; +wire [`DWIDTH-1:0] matrixC14_13; +wire [`DWIDTH-1:0] matrixC14_14; +wire [`DWIDTH-1:0] matrixC14_15; +wire [`DWIDTH-1:0] matrixC15_0; +wire [`DWIDTH-1:0] matrixC15_1; +wire [`DWIDTH-1:0] matrixC15_2; +wire [`DWIDTH-1:0] matrixC15_3; +wire [`DWIDTH-1:0] matrixC15_4; +wire [`DWIDTH-1:0] matrixC15_5; +wire [`DWIDTH-1:0] matrixC15_6; +wire [`DWIDTH-1:0] matrixC15_7; +wire [`DWIDTH-1:0] matrixC15_8; +wire [`DWIDTH-1:0] matrixC15_9; +wire [`DWIDTH-1:0] matrixC15_10; +wire [`DWIDTH-1:0] matrixC15_11; +wire [`DWIDTH-1:0] matrixC15_12; +wire [`DWIDTH-1:0] matrixC15_13; +wire [`DWIDTH-1:0] matrixC15_14; +wire [`DWIDTH-1:0] matrixC15_15; + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +systolic_pe_matrix u_systolic_pe_matrix( + .reset(reset), + .clk(clk), + .pe_reset(pe_reset), + .b_data_sel(b_data_sel), + .b_data_valid_ping(b_data_valid_ping), + .b_data_valid_pong(b_data_valid_pong), + .a0(a0), + .a1(a1), + .a2(a2), + .a3(a3), + .a4(a4), + .a5(a5), + .a6(a6), + .a7(a7), + .a8(a8), + .a9(a9), + .a10(a10), + .a11(a11), + .a12(a12), + .a13(a13), + .a14(a14), + .a15(a15), + .b0(b0), + .b1(b1), + .b2(b2), + .b3(b3), + .b4(b4), + .b5(b5), + .b6(b6), + .b7(b7), + .b8(b8), + .b9(b9), + .b10(b10), + .b11(b11), + .b12(b12), + .b13(b13), + .b14(b14), + .b15(b15), + .c0(c0), + .c1(c1), + .c2(c2), + .c3(c3), + .c4(c4), + .c5(c5), + .c6(c6), + .c7(c7), + .c8(c8), + .c9(c9), + .c10(c10), + .c11(c11), + .c12(c12), + .c13(c13), + .c14(c14), + .c15(c15), + .matrixC0_0(matrixC0_0), + .matrixC0_1(matrixC0_1), + .matrixC0_2(matrixC0_2), + .matrixC0_3(matrixC0_3), + .matrixC0_4(matrixC0_4), + .matrixC0_5(matrixC0_5), + .matrixC0_6(matrixC0_6), + .matrixC0_7(matrixC0_7), + .matrixC0_8(matrixC0_8), + .matrixC0_9(matrixC0_9), + .matrixC0_10(matrixC0_10), + .matrixC0_11(matrixC0_11), + .matrixC0_12(matrixC0_12), + .matrixC0_13(matrixC0_13), + .matrixC0_14(matrixC0_14), + .matrixC0_15(matrixC0_15), + .matrixC1_0(matrixC1_0), + .matrixC1_1(matrixC1_1), + .matrixC1_2(matrixC1_2), + .matrixC1_3(matrixC1_3), + .matrixC1_4(matrixC1_4), + .matrixC1_5(matrixC1_5), + .matrixC1_6(matrixC1_6), + .matrixC1_7(matrixC1_7), + .matrixC1_8(matrixC1_8), + .matrixC1_9(matrixC1_9), + .matrixC1_10(matrixC1_10), + .matrixC1_11(matrixC1_11), + .matrixC1_12(matrixC1_12), + .matrixC1_13(matrixC1_13), + .matrixC1_14(matrixC1_14), + .matrixC1_15(matrixC1_15), + .matrixC2_0(matrixC2_0), + .matrixC2_1(matrixC2_1), + .matrixC2_2(matrixC2_2), + .matrixC2_3(matrixC2_3), + .matrixC2_4(matrixC2_4), + .matrixC2_5(matrixC2_5), + .matrixC2_6(matrixC2_6), + .matrixC2_7(matrixC2_7), + .matrixC2_8(matrixC2_8), + .matrixC2_9(matrixC2_9), + .matrixC2_10(matrixC2_10), + .matrixC2_11(matrixC2_11), + .matrixC2_12(matrixC2_12), + .matrixC2_13(matrixC2_13), + .matrixC2_14(matrixC2_14), + .matrixC2_15(matrixC2_15), + .matrixC3_0(matrixC3_0), + .matrixC3_1(matrixC3_1), + .matrixC3_2(matrixC3_2), + .matrixC3_3(matrixC3_3), + .matrixC3_4(matrixC3_4), + .matrixC3_5(matrixC3_5), + .matrixC3_6(matrixC3_6), + .matrixC3_7(matrixC3_7), + .matrixC3_8(matrixC3_8), + .matrixC3_9(matrixC3_9), + .matrixC3_10(matrixC3_10), + .matrixC3_11(matrixC3_11), + .matrixC3_12(matrixC3_12), + .matrixC3_13(matrixC3_13), + .matrixC3_14(matrixC3_14), + .matrixC3_15(matrixC3_15), + .matrixC4_0(matrixC4_0), + .matrixC4_1(matrixC4_1), + .matrixC4_2(matrixC4_2), + .matrixC4_3(matrixC4_3), + .matrixC4_4(matrixC4_4), + .matrixC4_5(matrixC4_5), + .matrixC4_6(matrixC4_6), + .matrixC4_7(matrixC4_7), + .matrixC4_8(matrixC4_8), + .matrixC4_9(matrixC4_9), + .matrixC4_10(matrixC4_10), + .matrixC4_11(matrixC4_11), + .matrixC4_12(matrixC4_12), + .matrixC4_13(matrixC4_13), + .matrixC4_14(matrixC4_14), + .matrixC4_15(matrixC4_15), + .matrixC5_0(matrixC5_0), + .matrixC5_1(matrixC5_1), + .matrixC5_2(matrixC5_2), + .matrixC5_3(matrixC5_3), + .matrixC5_4(matrixC5_4), + .matrixC5_5(matrixC5_5), + .matrixC5_6(matrixC5_6), + .matrixC5_7(matrixC5_7), + .matrixC5_8(matrixC5_8), + .matrixC5_9(matrixC5_9), + .matrixC5_10(matrixC5_10), + .matrixC5_11(matrixC5_11), + .matrixC5_12(matrixC5_12), + .matrixC5_13(matrixC5_13), + .matrixC5_14(matrixC5_14), + .matrixC5_15(matrixC5_15), + .matrixC6_0(matrixC6_0), + .matrixC6_1(matrixC6_1), + .matrixC6_2(matrixC6_2), + .matrixC6_3(matrixC6_3), + .matrixC6_4(matrixC6_4), + .matrixC6_5(matrixC6_5), + .matrixC6_6(matrixC6_6), + .matrixC6_7(matrixC6_7), + .matrixC6_8(matrixC6_8), + .matrixC6_9(matrixC6_9), + .matrixC6_10(matrixC6_10), + .matrixC6_11(matrixC6_11), + .matrixC6_12(matrixC6_12), + .matrixC6_13(matrixC6_13), + .matrixC6_14(matrixC6_14), + .matrixC6_15(matrixC6_15), + .matrixC7_0(matrixC7_0), + .matrixC7_1(matrixC7_1), + .matrixC7_2(matrixC7_2), + .matrixC7_3(matrixC7_3), + .matrixC7_4(matrixC7_4), + .matrixC7_5(matrixC7_5), + .matrixC7_6(matrixC7_6), + .matrixC7_7(matrixC7_7), + .matrixC7_8(matrixC7_8), + .matrixC7_9(matrixC7_9), + .matrixC7_10(matrixC7_10), + .matrixC7_11(matrixC7_11), + .matrixC7_12(matrixC7_12), + .matrixC7_13(matrixC7_13), + .matrixC7_14(matrixC7_14), + .matrixC7_15(matrixC7_15), + .matrixC8_0(matrixC8_0), + .matrixC8_1(matrixC8_1), + .matrixC8_2(matrixC8_2), + .matrixC8_3(matrixC8_3), + .matrixC8_4(matrixC8_4), + .matrixC8_5(matrixC8_5), + .matrixC8_6(matrixC8_6), + .matrixC8_7(matrixC8_7), + .matrixC8_8(matrixC8_8), + .matrixC8_9(matrixC8_9), + .matrixC8_10(matrixC8_10), + .matrixC8_11(matrixC8_11), + .matrixC8_12(matrixC8_12), + .matrixC8_13(matrixC8_13), + .matrixC8_14(matrixC8_14), + .matrixC8_15(matrixC8_15), + .matrixC9_0(matrixC9_0), + .matrixC9_1(matrixC9_1), + .matrixC9_2(matrixC9_2), + .matrixC9_3(matrixC9_3), + .matrixC9_4(matrixC9_4), + .matrixC9_5(matrixC9_5), + .matrixC9_6(matrixC9_6), + .matrixC9_7(matrixC9_7), + .matrixC9_8(matrixC9_8), + .matrixC9_9(matrixC9_9), + .matrixC9_10(matrixC9_10), + .matrixC9_11(matrixC9_11), + .matrixC9_12(matrixC9_12), + .matrixC9_13(matrixC9_13), + .matrixC9_14(matrixC9_14), + .matrixC9_15(matrixC9_15), + .matrixC10_0(matrixC10_0), + .matrixC10_1(matrixC10_1), + .matrixC10_2(matrixC10_2), + .matrixC10_3(matrixC10_3), + .matrixC10_4(matrixC10_4), + .matrixC10_5(matrixC10_5), + .matrixC10_6(matrixC10_6), + .matrixC10_7(matrixC10_7), + .matrixC10_8(matrixC10_8), + .matrixC10_9(matrixC10_9), + .matrixC10_10(matrixC10_10), + .matrixC10_11(matrixC10_11), + .matrixC10_12(matrixC10_12), + .matrixC10_13(matrixC10_13), + .matrixC10_14(matrixC10_14), + .matrixC10_15(matrixC10_15), + .matrixC11_0(matrixC11_0), + .matrixC11_1(matrixC11_1), + .matrixC11_2(matrixC11_2), + .matrixC11_3(matrixC11_3), + .matrixC11_4(matrixC11_4), + .matrixC11_5(matrixC11_5), + .matrixC11_6(matrixC11_6), + .matrixC11_7(matrixC11_7), + .matrixC11_8(matrixC11_8), + .matrixC11_9(matrixC11_9), + .matrixC11_10(matrixC11_10), + .matrixC11_11(matrixC11_11), + .matrixC11_12(matrixC11_12), + .matrixC11_13(matrixC11_13), + .matrixC11_14(matrixC11_14), + .matrixC11_15(matrixC11_15), + .matrixC12_0(matrixC12_0), + .matrixC12_1(matrixC12_1), + .matrixC12_2(matrixC12_2), + .matrixC12_3(matrixC12_3), + .matrixC12_4(matrixC12_4), + .matrixC12_5(matrixC12_5), + .matrixC12_6(matrixC12_6), + .matrixC12_7(matrixC12_7), + .matrixC12_8(matrixC12_8), + .matrixC12_9(matrixC12_9), + .matrixC12_10(matrixC12_10), + .matrixC12_11(matrixC12_11), + .matrixC12_12(matrixC12_12), + .matrixC12_13(matrixC12_13), + .matrixC12_14(matrixC12_14), + .matrixC12_15(matrixC12_15), + .matrixC13_0(matrixC13_0), + .matrixC13_1(matrixC13_1), + .matrixC13_2(matrixC13_2), + .matrixC13_3(matrixC13_3), + .matrixC13_4(matrixC13_4), + .matrixC13_5(matrixC13_5), + .matrixC13_6(matrixC13_6), + .matrixC13_7(matrixC13_7), + .matrixC13_8(matrixC13_8), + .matrixC13_9(matrixC13_9), + .matrixC13_10(matrixC13_10), + .matrixC13_11(matrixC13_11), + .matrixC13_12(matrixC13_12), + .matrixC13_13(matrixC13_13), + .matrixC13_14(matrixC13_14), + .matrixC13_15(matrixC13_15), + .matrixC14_0(matrixC14_0), + .matrixC14_1(matrixC14_1), + .matrixC14_2(matrixC14_2), + .matrixC14_3(matrixC14_3), + .matrixC14_4(matrixC14_4), + .matrixC14_5(matrixC14_5), + .matrixC14_6(matrixC14_6), + .matrixC14_7(matrixC14_7), + .matrixC14_8(matrixC14_8), + .matrixC14_9(matrixC14_9), + .matrixC14_10(matrixC14_10), + .matrixC14_11(matrixC14_11), + .matrixC14_12(matrixC14_12), + .matrixC14_13(matrixC14_13), + .matrixC14_14(matrixC14_14), + .matrixC14_15(matrixC14_15), + .matrixC15_0(matrixC15_0), + .matrixC15_1(matrixC15_1), + .matrixC15_2(matrixC15_2), + .matrixC15_3(matrixC15_3), + .matrixC15_4(matrixC15_4), + .matrixC15_5(matrixC15_5), + .matrixC15_6(matrixC15_6), + .matrixC15_7(matrixC15_7), + .matrixC15_8(matrixC15_8), + .matrixC15_9(matrixC15_9), + .matrixC15_10(matrixC15_10), + .matrixC15_11(matrixC15_11), + .matrixC15_12(matrixC15_12), + .matrixC15_13(matrixC15_13), + .matrixC15_14(matrixC15_14), + .matrixC15_15(matrixC15_15), + .a_data_out(a_data_out), + .b_data_out(b_data_out) +); + +wire c_data_available; + +assign c_data_available = (clk_cnt > (`LOG2_MAT_MUL_SIZE-1+(`MAT_MUL_SIZE << 1)) & clk_cnt <= ((`LOG2_MAT_MUL_SIZE+(`MAT_MUL_SIZE << 1)) + (num_matrices_A << `LOG2_MAT_MUL_SIZE)-1)); + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Systolic data setup +////////////////////////////////////////////////////////////////////////// +module systolic_data_setup( + clk, + reset, + start_mat_mul, + a_addr, + b_addr, + address_mat_a, + address_mat_b, + address_stride_a, + address_stride_b, + a_data, + b_data, + clk_cnt, + a0_data, + a1_data_delayed_1, + a2_data_delayed_2, + a3_data_delayed_3, + a4_data_delayed_4, + a5_data_delayed_5, + a6_data_delayed_6, + a7_data_delayed_7, + a8_data_delayed_8, + a9_data_delayed_9, + a10_data_delayed_10, + a11_data_delayed_11, + a12_data_delayed_12, + a13_data_delayed_13, + a14_data_delayed_14, + a15_data_delayed_15, + b0_data, + b1_data_delayed_1, + b2_data_delayed_2, + b3_data_delayed_3, + b4_data_delayed_4, + b5_data_delayed_5, + b6_data_delayed_6, + b7_data_delayed_7, + b8_data_delayed_8, + b9_data_delayed_9, + b10_data_delayed_10, + b11_data_delayed_11, + b12_data_delayed_12, + b13_data_delayed_13, + b14_data_delayed_14, + b15_data_delayed_15, + validity_mask_a_rows, + validity_mask_a_cols_b_rows, + validity_mask_b_cols, + num_matrices_A, + num_matrices_B, + a_loc, + b_loc +); + +input clk; +input reset; +input start_mat_mul; +output [`AWIDTH-1:0] a_addr; +output [`AWIDTH-1:0] b_addr; +input [`AWIDTH-1:0] address_mat_a; +input [`AWIDTH-1:0] address_mat_b; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; +input [31:0] clk_cnt; +output [`DWIDTH-1:0] a0_data; +output [`DWIDTH-1:0] a1_data_delayed_1; +output [`DWIDTH-1:0] a2_data_delayed_2; +output [`DWIDTH-1:0] a3_data_delayed_3; +output [`DWIDTH-1:0] a4_data_delayed_4; +output [`DWIDTH-1:0] a5_data_delayed_5; +output [`DWIDTH-1:0] a6_data_delayed_6; +output [`DWIDTH-1:0] a7_data_delayed_7; +output [`DWIDTH-1:0] a8_data_delayed_8; +output [`DWIDTH-1:0] a9_data_delayed_9; +output [`DWIDTH-1:0] a10_data_delayed_10; +output [`DWIDTH-1:0] a11_data_delayed_11; +output [`DWIDTH-1:0] a12_data_delayed_12; +output [`DWIDTH-1:0] a13_data_delayed_13; +output [`DWIDTH-1:0] a14_data_delayed_14; +output [`DWIDTH-1:0] a15_data_delayed_15; +output [`DWIDTH-1:0] b0_data; +output [`DWIDTH-1:0] b1_data_delayed_1; +output [`DWIDTH-1:0] b2_data_delayed_2; +output [`DWIDTH-1:0] b3_data_delayed_3; +output [`DWIDTH-1:0] b4_data_delayed_4; +output [`DWIDTH-1:0] b5_data_delayed_5; +output [`DWIDTH-1:0] b6_data_delayed_6; +output [`DWIDTH-1:0] b7_data_delayed_7; +output [`DWIDTH-1:0] b8_data_delayed_8; +output [`DWIDTH-1:0] b9_data_delayed_9; +output [`DWIDTH-1:0] b10_data_delayed_10; +output [`DWIDTH-1:0] b11_data_delayed_11; +output [`DWIDTH-1:0] b12_data_delayed_12; +output [`DWIDTH-1:0] b13_data_delayed_13; +output [`DWIDTH-1:0] b14_data_delayed_14; +output [`DWIDTH-1:0] b15_data_delayed_15; +input [`MASK_WIDTH-1:0] validity_mask_a_rows; +input [`MASK_WIDTH-1:0] validity_mask_a_cols_b_rows; +input [`MASK_WIDTH-1:0] validity_mask_b_cols; +input [31:0] num_matrices_A; +input [31:0] num_matrices_B; +input [31:0] a_loc; +input [31:0] b_loc; + +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; + +wire a_data_valid; // flag that tells whether the data from memory is valid +wire b_data_valid; // flag that tells whether the data from memory is valid + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM A +////////////////////////////////////////////////////////////////////////// + +reg [`AWIDTH-1:0] a_addr; +reg a_mem_access; // flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin +if ((reset || ~start_mat_mul) || (clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)+`MAT_MUL_SIZE+(num_matrices_A << `LOG2_MAT_MUL_SIZE))) begin + a_addr <= address_mat_a-address_stride_a; + a_mem_access <= 0; +end +else if ((clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)+`MAT_MUL_SIZE) && (clk_cnt < (a_loc<<`LOG2_MAT_MUL_SIZE)+`MAT_MUL_SIZE+(num_matrices_A << `LOG2_MAT_MUL_SIZE))) begin + a_addr <= a_addr + address_stride_a; + a_mem_access <= 1; +end +end + + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM A +////////////////////////////////////////////////////////////////////////// + +reg [31:0] a_mem_access_counter; + +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + a_mem_access_counter <= 0; + end + else if (a_mem_access == 1) begin + a_mem_access_counter <= a_mem_access_counter + 1; + end + else begin + a_mem_access_counter <= 0; + end +end + +assign a_data_valid = + ((validity_mask_a_cols_b_rows[0]==1'b0 && a_mem_access_counter==1) || + (validity_mask_a_cols_b_rows[1]==1'b0 && a_mem_access_counter==2) || + (validity_mask_a_cols_b_rows[2]==1'b0 && a_mem_access_counter==3) || + (validity_mask_a_cols_b_rows[3]==1'b0 && a_mem_access_counter==4) || + (validity_mask_a_cols_b_rows[4]==1'b0 && a_mem_access_counter==5) || + (validity_mask_a_cols_b_rows[5]==1'b0 && a_mem_access_counter==6) || + (validity_mask_a_cols_b_rows[6]==1'b0 && a_mem_access_counter==7) || + (validity_mask_a_cols_b_rows[7]==1'b0 && a_mem_access_counter==8) || + (validity_mask_a_cols_b_rows[8]==1'b0 && a_mem_access_counter==9) || + (validity_mask_a_cols_b_rows[9]==1'b0 && a_mem_access_counter==10) || + (validity_mask_a_cols_b_rows[10]==1'b0 && a_mem_access_counter==11) || + (validity_mask_a_cols_b_rows[11]==1'b0 && a_mem_access_counter==12) || + (validity_mask_a_cols_b_rows[12]==1'b0 && a_mem_access_counter==13) || + (validity_mask_a_cols_b_rows[13]==1'b0 && a_mem_access_counter==14) || + (validity_mask_a_cols_b_rows[14]==1'b0 && a_mem_access_counter==15) || + (validity_mask_a_cols_b_rows[15]==1'b0 && a_mem_access_counter==16)) ? + 1'b0 : (a_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM A (systolic data setup) +////////////////////////////////////////////////////////////////////////// + +// Slice data into chunks and qualify it with whether it is valid or not +assign a0_data = a_data[`DWIDTH-1:0] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[0]}}; +assign a1_data = a_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[1]}}; +assign a2_data = a_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[2]}}; +assign a3_data = a_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[3]}}; +assign a4_data = a_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[4]}}; +assign a5_data = a_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[5]}}; +assign a6_data = a_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[6]}}; +assign a7_data = a_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[7]}}; +assign a8_data = a_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[8]}}; +assign a9_data = a_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[9]}}; +assign a10_data = a_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[10]}}; +assign a11_data = a_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[11]}}; +assign a12_data = a_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[12]}}; +assign a13_data = a_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[13]}}; +assign a14_data = a_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[14]}}; +assign a15_data = a_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[15]}}; + +// For larger matmuls, more such delaying flops will be needed +reg [`DWIDTH-1:0] a1_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_1; +reg [`DWIDTH-1:0] a3_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_1; +reg [`DWIDTH-1:0] a4_data_delayed_2; +reg [`DWIDTH-1:0] a4_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_1; +reg [`DWIDTH-1:0] a5_data_delayed_2; +reg [`DWIDTH-1:0] a5_data_delayed_3; +reg [`DWIDTH-1:0] a5_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_1; +reg [`DWIDTH-1:0] a6_data_delayed_2; +reg [`DWIDTH-1:0] a6_data_delayed_3; +reg [`DWIDTH-1:0] a6_data_delayed_4; +reg [`DWIDTH-1:0] a6_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_1; +reg [`DWIDTH-1:0] a7_data_delayed_2; +reg [`DWIDTH-1:0] a7_data_delayed_3; +reg [`DWIDTH-1:0] a7_data_delayed_4; +reg [`DWIDTH-1:0] a7_data_delayed_5; +reg [`DWIDTH-1:0] a7_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_1; +reg [`DWIDTH-1:0] a8_data_delayed_2; +reg [`DWIDTH-1:0] a8_data_delayed_3; +reg [`DWIDTH-1:0] a8_data_delayed_4; +reg [`DWIDTH-1:0] a8_data_delayed_5; +reg [`DWIDTH-1:0] a8_data_delayed_6; +reg [`DWIDTH-1:0] a8_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_1; +reg [`DWIDTH-1:0] a9_data_delayed_2; +reg [`DWIDTH-1:0] a9_data_delayed_3; +reg [`DWIDTH-1:0] a9_data_delayed_4; +reg [`DWIDTH-1:0] a9_data_delayed_5; +reg [`DWIDTH-1:0] a9_data_delayed_6; +reg [`DWIDTH-1:0] a9_data_delayed_7; +reg [`DWIDTH-1:0] a9_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_1; +reg [`DWIDTH-1:0] a10_data_delayed_2; +reg [`DWIDTH-1:0] a10_data_delayed_3; +reg [`DWIDTH-1:0] a10_data_delayed_4; +reg [`DWIDTH-1:0] a10_data_delayed_5; +reg [`DWIDTH-1:0] a10_data_delayed_6; +reg [`DWIDTH-1:0] a10_data_delayed_7; +reg [`DWIDTH-1:0] a10_data_delayed_8; +reg [`DWIDTH-1:0] a10_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_1; +reg [`DWIDTH-1:0] a11_data_delayed_2; +reg [`DWIDTH-1:0] a11_data_delayed_3; +reg [`DWIDTH-1:0] a11_data_delayed_4; +reg [`DWIDTH-1:0] a11_data_delayed_5; +reg [`DWIDTH-1:0] a11_data_delayed_6; +reg [`DWIDTH-1:0] a11_data_delayed_7; +reg [`DWIDTH-1:0] a11_data_delayed_8; +reg [`DWIDTH-1:0] a11_data_delayed_9; +reg [`DWIDTH-1:0] a11_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_1; +reg [`DWIDTH-1:0] a12_data_delayed_2; +reg [`DWIDTH-1:0] a12_data_delayed_3; +reg [`DWIDTH-1:0] a12_data_delayed_4; +reg [`DWIDTH-1:0] a12_data_delayed_5; +reg [`DWIDTH-1:0] a12_data_delayed_6; +reg [`DWIDTH-1:0] a12_data_delayed_7; +reg [`DWIDTH-1:0] a12_data_delayed_8; +reg [`DWIDTH-1:0] a12_data_delayed_9; +reg [`DWIDTH-1:0] a12_data_delayed_10; +reg [`DWIDTH-1:0] a12_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_1; +reg [`DWIDTH-1:0] a13_data_delayed_2; +reg [`DWIDTH-1:0] a13_data_delayed_3; +reg [`DWIDTH-1:0] a13_data_delayed_4; +reg [`DWIDTH-1:0] a13_data_delayed_5; +reg [`DWIDTH-1:0] a13_data_delayed_6; +reg [`DWIDTH-1:0] a13_data_delayed_7; +reg [`DWIDTH-1:0] a13_data_delayed_8; +reg [`DWIDTH-1:0] a13_data_delayed_9; +reg [`DWIDTH-1:0] a13_data_delayed_10; +reg [`DWIDTH-1:0] a13_data_delayed_11; +reg [`DWIDTH-1:0] a13_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_1; +reg [`DWIDTH-1:0] a14_data_delayed_2; +reg [`DWIDTH-1:0] a14_data_delayed_3; +reg [`DWIDTH-1:0] a14_data_delayed_4; +reg [`DWIDTH-1:0] a14_data_delayed_5; +reg [`DWIDTH-1:0] a14_data_delayed_6; +reg [`DWIDTH-1:0] a14_data_delayed_7; +reg [`DWIDTH-1:0] a14_data_delayed_8; +reg [`DWIDTH-1:0] a14_data_delayed_9; +reg [`DWIDTH-1:0] a14_data_delayed_10; +reg [`DWIDTH-1:0] a14_data_delayed_11; +reg [`DWIDTH-1:0] a14_data_delayed_12; +reg [`DWIDTH-1:0] a14_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_1; +reg [`DWIDTH-1:0] a15_data_delayed_2; +reg [`DWIDTH-1:0] a15_data_delayed_3; +reg [`DWIDTH-1:0] a15_data_delayed_4; +reg [`DWIDTH-1:0] a15_data_delayed_5; +reg [`DWIDTH-1:0] a15_data_delayed_6; +reg [`DWIDTH-1:0] a15_data_delayed_7; +reg [`DWIDTH-1:0] a15_data_delayed_8; +reg [`DWIDTH-1:0] a15_data_delayed_9; +reg [`DWIDTH-1:0] a15_data_delayed_10; +reg [`DWIDTH-1:0] a15_data_delayed_11; +reg [`DWIDTH-1:0] a15_data_delayed_12; +reg [`DWIDTH-1:0] a15_data_delayed_13; +reg [`DWIDTH-1:0] a15_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_15; + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + a1_data_delayed_1 <= 0; + a2_data_delayed_1 <= 0; + a2_data_delayed_2 <= 0; + a3_data_delayed_1 <= 0; + a3_data_delayed_2 <= 0; + a3_data_delayed_3 <= 0; + a4_data_delayed_1 <= 0; + a4_data_delayed_2 <= 0; + a4_data_delayed_3 <= 0; + a4_data_delayed_4 <= 0; + a5_data_delayed_1 <= 0; + a5_data_delayed_2 <= 0; + a5_data_delayed_3 <= 0; + a5_data_delayed_4 <= 0; + a5_data_delayed_5 <= 0; + a6_data_delayed_1 <= 0; + a6_data_delayed_2 <= 0; + a6_data_delayed_3 <= 0; + a6_data_delayed_4 <= 0; + a6_data_delayed_5 <= 0; + a6_data_delayed_6 <= 0; + a7_data_delayed_1 <= 0; + a7_data_delayed_2 <= 0; + a7_data_delayed_3 <= 0; + a7_data_delayed_4 <= 0; + a7_data_delayed_5 <= 0; + a7_data_delayed_6 <= 0; + a7_data_delayed_7 <= 0; + a8_data_delayed_1 <= 0; + a8_data_delayed_2 <= 0; + a8_data_delayed_3 <= 0; + a8_data_delayed_4 <= 0; + a8_data_delayed_5 <= 0; + a8_data_delayed_6 <= 0; + a8_data_delayed_7 <= 0; + a8_data_delayed_8 <= 0; + a9_data_delayed_1 <= 0; + a9_data_delayed_2 <= 0; + a9_data_delayed_3 <= 0; + a9_data_delayed_4 <= 0; + a9_data_delayed_5 <= 0; + a9_data_delayed_6 <= 0; + a9_data_delayed_7 <= 0; + a9_data_delayed_8 <= 0; + a9_data_delayed_9 <= 0; + a10_data_delayed_1 <= 0; + a10_data_delayed_2 <= 0; + a10_data_delayed_3 <= 0; + a10_data_delayed_4 <= 0; + a10_data_delayed_5 <= 0; + a10_data_delayed_6 <= 0; + a10_data_delayed_7 <= 0; + a10_data_delayed_8 <= 0; + a10_data_delayed_9 <= 0; + a10_data_delayed_10 <= 0; + a11_data_delayed_1 <= 0; + a11_data_delayed_2 <= 0; + a11_data_delayed_3 <= 0; + a11_data_delayed_4 <= 0; + a11_data_delayed_5 <= 0; + a11_data_delayed_6 <= 0; + a11_data_delayed_7 <= 0; + a11_data_delayed_8 <= 0; + a11_data_delayed_9 <= 0; + a11_data_delayed_10 <= 0; + a11_data_delayed_11 <= 0; + a12_data_delayed_1 <= 0; + a12_data_delayed_2 <= 0; + a12_data_delayed_3 <= 0; + a12_data_delayed_4 <= 0; + a12_data_delayed_5 <= 0; + a12_data_delayed_6 <= 0; + a12_data_delayed_7 <= 0; + a12_data_delayed_8 <= 0; + a12_data_delayed_9 <= 0; + a12_data_delayed_10 <= 0; + a12_data_delayed_11 <= 0; + a12_data_delayed_12 <= 0; + a13_data_delayed_1 <= 0; + a13_data_delayed_2 <= 0; + a13_data_delayed_3 <= 0; + a13_data_delayed_4 <= 0; + a13_data_delayed_5 <= 0; + a13_data_delayed_6 <= 0; + a13_data_delayed_7 <= 0; + a13_data_delayed_8 <= 0; + a13_data_delayed_9 <= 0; + a13_data_delayed_10 <= 0; + a13_data_delayed_11 <= 0; + a13_data_delayed_12 <= 0; + a13_data_delayed_13 <= 0; + a14_data_delayed_1 <= 0; + a14_data_delayed_2 <= 0; + a14_data_delayed_3 <= 0; + a14_data_delayed_4 <= 0; + a14_data_delayed_5 <= 0; + a14_data_delayed_6 <= 0; + a14_data_delayed_7 <= 0; + a14_data_delayed_8 <= 0; + a14_data_delayed_9 <= 0; + a14_data_delayed_10 <= 0; + a14_data_delayed_11 <= 0; + a14_data_delayed_12 <= 0; + a14_data_delayed_13 <= 0; + a14_data_delayed_14 <= 0; + a15_data_delayed_1 <= 0; + a15_data_delayed_2 <= 0; + a15_data_delayed_3 <= 0; + a15_data_delayed_4 <= 0; + a15_data_delayed_5 <= 0; + a15_data_delayed_6 <= 0; + a15_data_delayed_7 <= 0; + a15_data_delayed_8 <= 0; + a15_data_delayed_9 <= 0; + a15_data_delayed_10 <= 0; + a15_data_delayed_11 <= 0; + a15_data_delayed_12 <= 0; + a15_data_delayed_13 <= 0; + a15_data_delayed_14 <= 0; + a15_data_delayed_15 <= 0; + end + else begin + a1_data_delayed_1 <= a1_data; + a2_data_delayed_1 <= a2_data; + a2_data_delayed_2 <= a2_data_delayed_1; + a3_data_delayed_1 <= a3_data; + a3_data_delayed_2 <= a3_data_delayed_1; + a3_data_delayed_3 <= a3_data_delayed_2; + a4_data_delayed_1 <= a4_data; + a4_data_delayed_2 <= a4_data_delayed_1; + a4_data_delayed_3 <= a4_data_delayed_2; + a4_data_delayed_4 <= a4_data_delayed_3; + a5_data_delayed_1 <= a5_data; + a5_data_delayed_2 <= a5_data_delayed_1; + a5_data_delayed_3 <= a5_data_delayed_2; + a5_data_delayed_4 <= a5_data_delayed_3; + a5_data_delayed_5 <= a5_data_delayed_4; + a6_data_delayed_1 <= a6_data; + a6_data_delayed_2 <= a6_data_delayed_1; + a6_data_delayed_3 <= a6_data_delayed_2; + a6_data_delayed_4 <= a6_data_delayed_3; + a6_data_delayed_5 <= a6_data_delayed_4; + a6_data_delayed_6 <= a6_data_delayed_5; + a7_data_delayed_1 <= a7_data; + a7_data_delayed_2 <= a7_data_delayed_1; + a7_data_delayed_3 <= a7_data_delayed_2; + a7_data_delayed_4 <= a7_data_delayed_3; + a7_data_delayed_5 <= a7_data_delayed_4; + a7_data_delayed_6 <= a7_data_delayed_5; + a7_data_delayed_7 <= a7_data_delayed_6; + a8_data_delayed_1 <= a8_data; + a8_data_delayed_2 <= a8_data_delayed_1; + a8_data_delayed_3 <= a8_data_delayed_2; + a8_data_delayed_4 <= a8_data_delayed_3; + a8_data_delayed_5 <= a8_data_delayed_4; + a8_data_delayed_6 <= a8_data_delayed_5; + a8_data_delayed_7 <= a8_data_delayed_6; + a8_data_delayed_8 <= a8_data_delayed_7; + a9_data_delayed_1 <= a9_data; + a9_data_delayed_2 <= a9_data_delayed_1; + a9_data_delayed_3 <= a9_data_delayed_2; + a9_data_delayed_4 <= a9_data_delayed_3; + a9_data_delayed_5 <= a9_data_delayed_4; + a9_data_delayed_6 <= a9_data_delayed_5; + a9_data_delayed_7 <= a9_data_delayed_6; + a9_data_delayed_8 <= a9_data_delayed_7; + a9_data_delayed_9 <= a9_data_delayed_8; + a10_data_delayed_1 <= a10_data; + a10_data_delayed_2 <= a10_data_delayed_1; + a10_data_delayed_3 <= a10_data_delayed_2; + a10_data_delayed_4 <= a10_data_delayed_3; + a10_data_delayed_5 <= a10_data_delayed_4; + a10_data_delayed_6 <= a10_data_delayed_5; + a10_data_delayed_7 <= a10_data_delayed_6; + a10_data_delayed_8 <= a10_data_delayed_7; + a10_data_delayed_9 <= a10_data_delayed_8; + a10_data_delayed_10 <= a10_data_delayed_9; + a11_data_delayed_1 <= a11_data; + a11_data_delayed_2 <= a11_data_delayed_1; + a11_data_delayed_3 <= a11_data_delayed_2; + a11_data_delayed_4 <= a11_data_delayed_3; + a11_data_delayed_5 <= a11_data_delayed_4; + a11_data_delayed_6 <= a11_data_delayed_5; + a11_data_delayed_7 <= a11_data_delayed_6; + a11_data_delayed_8 <= a11_data_delayed_7; + a11_data_delayed_9 <= a11_data_delayed_8; + a11_data_delayed_10 <= a11_data_delayed_9; + a11_data_delayed_11 <= a11_data_delayed_10; + a12_data_delayed_1 <= a12_data; + a12_data_delayed_2 <= a12_data_delayed_1; + a12_data_delayed_3 <= a12_data_delayed_2; + a12_data_delayed_4 <= a12_data_delayed_3; + a12_data_delayed_5 <= a12_data_delayed_4; + a12_data_delayed_6 <= a12_data_delayed_5; + a12_data_delayed_7 <= a12_data_delayed_6; + a12_data_delayed_8 <= a12_data_delayed_7; + a12_data_delayed_9 <= a12_data_delayed_8; + a12_data_delayed_10 <= a12_data_delayed_9; + a12_data_delayed_11 <= a12_data_delayed_10; + a12_data_delayed_12 <= a12_data_delayed_11; + a13_data_delayed_1 <= a13_data; + a13_data_delayed_2 <= a13_data_delayed_1; + a13_data_delayed_3 <= a13_data_delayed_2; + a13_data_delayed_4 <= a13_data_delayed_3; + a13_data_delayed_5 <= a13_data_delayed_4; + a13_data_delayed_6 <= a13_data_delayed_5; + a13_data_delayed_7 <= a13_data_delayed_6; + a13_data_delayed_8 <= a13_data_delayed_7; + a13_data_delayed_9 <= a13_data_delayed_8; + a13_data_delayed_10 <= a13_data_delayed_9; + a13_data_delayed_11 <= a13_data_delayed_10; + a13_data_delayed_12 <= a13_data_delayed_11; + a13_data_delayed_13 <= a13_data_delayed_12; + a14_data_delayed_1 <= a14_data; + a14_data_delayed_2 <= a14_data_delayed_1; + a14_data_delayed_3 <= a14_data_delayed_2; + a14_data_delayed_4 <= a14_data_delayed_3; + a14_data_delayed_5 <= a14_data_delayed_4; + a14_data_delayed_6 <= a14_data_delayed_5; + a14_data_delayed_7 <= a14_data_delayed_6; + a14_data_delayed_8 <= a14_data_delayed_7; + a14_data_delayed_9 <= a14_data_delayed_8; + a14_data_delayed_10 <= a14_data_delayed_9; + a14_data_delayed_11 <= a14_data_delayed_10; + a14_data_delayed_12 <= a14_data_delayed_11; + a14_data_delayed_13 <= a14_data_delayed_12; + a14_data_delayed_14 <= a14_data_delayed_13; + a15_data_delayed_1 <= a15_data; + a15_data_delayed_2 <= a15_data_delayed_1; + a15_data_delayed_3 <= a15_data_delayed_2; + a15_data_delayed_4 <= a15_data_delayed_3; + a15_data_delayed_5 <= a15_data_delayed_4; + a15_data_delayed_6 <= a15_data_delayed_5; + a15_data_delayed_7 <= a15_data_delayed_6; + a15_data_delayed_8 <= a15_data_delayed_7; + a15_data_delayed_9 <= a15_data_delayed_8; + a15_data_delayed_10 <= a15_data_delayed_9; + a15_data_delayed_11 <= a15_data_delayed_10; + a15_data_delayed_12 <= a15_data_delayed_11; + a15_data_delayed_13 <= a15_data_delayed_12; + a15_data_delayed_14 <= a15_data_delayed_13; + a15_data_delayed_15 <= a15_data_delayed_14; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM B +////////////////////////////////////////////////////////////////////////// + +reg [`AWIDTH-1:0] b_addr; +reg b_mem_access; // flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin + if ((reset || ~start_mat_mul) || (clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)+num_matrices_B << `LOG2_MAT_MUL_SIZE)) begin + b_addr <= address_mat_b - address_stride_b; + b_mem_access <= 0; + end + else if ((clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (b_loc<<`LOG2_MAT_MUL_SIZE)+num_matrices_B << `LOG2_MAT_MUL_SIZE)) begin + b_addr <= b_addr + address_stride_b; + b_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM B +////////////////////////////////////////////////////////////////////////// + +reg [7:0] b_mem_access_counter; + +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + b_mem_access_counter <= 0; + end + else if (b_mem_access == 1) begin + b_mem_access_counter <= b_mem_access_counter + 1; + end + else begin + b_mem_access_counter <= 0; + end +end + +assign b_data_valid = + ((validity_mask_a_cols_b_rows[0]==1'b0 && b_mem_access_counter==1) || + (validity_mask_a_cols_b_rows[1]==1'b0 && b_mem_access_counter==2) || + (validity_mask_a_cols_b_rows[2]==1'b0 && b_mem_access_counter==3) || + (validity_mask_a_cols_b_rows[3]==1'b0 && b_mem_access_counter==4) || + (validity_mask_a_cols_b_rows[4]==1'b0 && b_mem_access_counter==5) || + (validity_mask_a_cols_b_rows[5]==1'b0 && b_mem_access_counter==6) || + (validity_mask_a_cols_b_rows[6]==1'b0 && b_mem_access_counter==7) || + (validity_mask_a_cols_b_rows[7]==1'b0 && b_mem_access_counter==8) || + (validity_mask_a_cols_b_rows[8]==1'b0 && b_mem_access_counter==9) || + (validity_mask_a_cols_b_rows[9]==1'b0 && b_mem_access_counter==10) || + (validity_mask_a_cols_b_rows[10]==1'b0 && b_mem_access_counter==11) || + (validity_mask_a_cols_b_rows[11]==1'b0 && b_mem_access_counter==12) || + (validity_mask_a_cols_b_rows[12]==1'b0 && b_mem_access_counter==13) || + (validity_mask_a_cols_b_rows[13]==1'b0 && b_mem_access_counter==14) || + (validity_mask_a_cols_b_rows[14]==1'b0 && b_mem_access_counter==15) || + (validity_mask_a_cols_b_rows[15]==1'b0 && b_mem_access_counter==16)) ? + 1'b0 : (b_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM B (systolic data setup) +////////////////////////////////////////////////////////////////////////// + +// Slice data into chunks and qualify it with whether it is valid or not +assign b0_data = b_data[`DWIDTH-1:0] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[0]}}; +assign b1_data = b_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[1]}}; +assign b2_data = b_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[2]}}; +assign b3_data = b_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[3]}}; +assign b4_data = b_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[4]}}; +assign b5_data = b_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[5]}}; +assign b6_data = b_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[6]}}; +assign b7_data = b_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[7]}}; +assign b8_data = b_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[8]}}; +assign b9_data = b_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[9]}}; +assign b10_data = b_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[10]}}; +assign b11_data = b_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[11]}}; +assign b12_data = b_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[12]}}; +assign b13_data = b_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[13]}}; +assign b14_data = b_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[14]}}; +assign b15_data = b_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[15]}}; + +// For larger matmuls, more such delaying flops will be needed +reg [`DWIDTH-1:0] b1_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_1; +reg [`DWIDTH-1:0] b3_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_1; +reg [`DWIDTH-1:0] b4_data_delayed_2; +reg [`DWIDTH-1:0] b4_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_1; +reg [`DWIDTH-1:0] b5_data_delayed_2; +reg [`DWIDTH-1:0] b5_data_delayed_3; +reg [`DWIDTH-1:0] b5_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_1; +reg [`DWIDTH-1:0] b6_data_delayed_2; +reg [`DWIDTH-1:0] b6_data_delayed_3; +reg [`DWIDTH-1:0] b6_data_delayed_4; +reg [`DWIDTH-1:0] b6_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_1; +reg [`DWIDTH-1:0] b7_data_delayed_2; +reg [`DWIDTH-1:0] b7_data_delayed_3; +reg [`DWIDTH-1:0] b7_data_delayed_4; +reg [`DWIDTH-1:0] b7_data_delayed_5; +reg [`DWIDTH-1:0] b7_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_1; +reg [`DWIDTH-1:0] b8_data_delayed_2; +reg [`DWIDTH-1:0] b8_data_delayed_3; +reg [`DWIDTH-1:0] b8_data_delayed_4; +reg [`DWIDTH-1:0] b8_data_delayed_5; +reg [`DWIDTH-1:0] b8_data_delayed_6; +reg [`DWIDTH-1:0] b8_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_1; +reg [`DWIDTH-1:0] b9_data_delayed_2; +reg [`DWIDTH-1:0] b9_data_delayed_3; +reg [`DWIDTH-1:0] b9_data_delayed_4; +reg [`DWIDTH-1:0] b9_data_delayed_5; +reg [`DWIDTH-1:0] b9_data_delayed_6; +reg [`DWIDTH-1:0] b9_data_delayed_7; +reg [`DWIDTH-1:0] b9_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_1; +reg [`DWIDTH-1:0] b10_data_delayed_2; +reg [`DWIDTH-1:0] b10_data_delayed_3; +reg [`DWIDTH-1:0] b10_data_delayed_4; +reg [`DWIDTH-1:0] b10_data_delayed_5; +reg [`DWIDTH-1:0] b10_data_delayed_6; +reg [`DWIDTH-1:0] b10_data_delayed_7; +reg [`DWIDTH-1:0] b10_data_delayed_8; +reg [`DWIDTH-1:0] b10_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_1; +reg [`DWIDTH-1:0] b11_data_delayed_2; +reg [`DWIDTH-1:0] b11_data_delayed_3; +reg [`DWIDTH-1:0] b11_data_delayed_4; +reg [`DWIDTH-1:0] b11_data_delayed_5; +reg [`DWIDTH-1:0] b11_data_delayed_6; +reg [`DWIDTH-1:0] b11_data_delayed_7; +reg [`DWIDTH-1:0] b11_data_delayed_8; +reg [`DWIDTH-1:0] b11_data_delayed_9; +reg [`DWIDTH-1:0] b11_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_1; +reg [`DWIDTH-1:0] b12_data_delayed_2; +reg [`DWIDTH-1:0] b12_data_delayed_3; +reg [`DWIDTH-1:0] b12_data_delayed_4; +reg [`DWIDTH-1:0] b12_data_delayed_5; +reg [`DWIDTH-1:0] b12_data_delayed_6; +reg [`DWIDTH-1:0] b12_data_delayed_7; +reg [`DWIDTH-1:0] b12_data_delayed_8; +reg [`DWIDTH-1:0] b12_data_delayed_9; +reg [`DWIDTH-1:0] b12_data_delayed_10; +reg [`DWIDTH-1:0] b12_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_1; +reg [`DWIDTH-1:0] b13_data_delayed_2; +reg [`DWIDTH-1:0] b13_data_delayed_3; +reg [`DWIDTH-1:0] b13_data_delayed_4; +reg [`DWIDTH-1:0] b13_data_delayed_5; +reg [`DWIDTH-1:0] b13_data_delayed_6; +reg [`DWIDTH-1:0] b13_data_delayed_7; +reg [`DWIDTH-1:0] b13_data_delayed_8; +reg [`DWIDTH-1:0] b13_data_delayed_9; +reg [`DWIDTH-1:0] b13_data_delayed_10; +reg [`DWIDTH-1:0] b13_data_delayed_11; +reg [`DWIDTH-1:0] b13_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_1; +reg [`DWIDTH-1:0] b14_data_delayed_2; +reg [`DWIDTH-1:0] b14_data_delayed_3; +reg [`DWIDTH-1:0] b14_data_delayed_4; +reg [`DWIDTH-1:0] b14_data_delayed_5; +reg [`DWIDTH-1:0] b14_data_delayed_6; +reg [`DWIDTH-1:0] b14_data_delayed_7; +reg [`DWIDTH-1:0] b14_data_delayed_8; +reg [`DWIDTH-1:0] b14_data_delayed_9; +reg [`DWIDTH-1:0] b14_data_delayed_10; +reg [`DWIDTH-1:0] b14_data_delayed_11; +reg [`DWIDTH-1:0] b14_data_delayed_12; +reg [`DWIDTH-1:0] b14_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_1; +reg [`DWIDTH-1:0] b15_data_delayed_2; +reg [`DWIDTH-1:0] b15_data_delayed_3; +reg [`DWIDTH-1:0] b15_data_delayed_4; +reg [`DWIDTH-1:0] b15_data_delayed_5; +reg [`DWIDTH-1:0] b15_data_delayed_6; +reg [`DWIDTH-1:0] b15_data_delayed_7; +reg [`DWIDTH-1:0] b15_data_delayed_8; +reg [`DWIDTH-1:0] b15_data_delayed_9; +reg [`DWIDTH-1:0] b15_data_delayed_10; +reg [`DWIDTH-1:0] b15_data_delayed_11; +reg [`DWIDTH-1:0] b15_data_delayed_12; +reg [`DWIDTH-1:0] b15_data_delayed_13; +reg [`DWIDTH-1:0] b15_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_15; + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + b1_data_delayed_1 <= 0; + b2_data_delayed_1 <= 0; + b2_data_delayed_2 <= 0; + b3_data_delayed_1 <= 0; + b3_data_delayed_2 <= 0; + b3_data_delayed_3 <= 0; + b4_data_delayed_1 <= 0; + b4_data_delayed_2 <= 0; + b4_data_delayed_3 <= 0; + b4_data_delayed_4 <= 0; + b5_data_delayed_1 <= 0; + b5_data_delayed_2 <= 0; + b5_data_delayed_3 <= 0; + b5_data_delayed_4 <= 0; + b5_data_delayed_5 <= 0; + b6_data_delayed_1 <= 0; + b6_data_delayed_2 <= 0; + b6_data_delayed_3 <= 0; + b6_data_delayed_4 <= 0; + b6_data_delayed_5 <= 0; + b6_data_delayed_6 <= 0; + b7_data_delayed_1 <= 0; + b7_data_delayed_2 <= 0; + b7_data_delayed_3 <= 0; + b7_data_delayed_4 <= 0; + b7_data_delayed_5 <= 0; + b7_data_delayed_6 <= 0; + b7_data_delayed_7 <= 0; + b8_data_delayed_1 <= 0; + b8_data_delayed_2 <= 0; + b8_data_delayed_3 <= 0; + b8_data_delayed_4 <= 0; + b8_data_delayed_5 <= 0; + b8_data_delayed_6 <= 0; + b8_data_delayed_7 <= 0; + b8_data_delayed_8 <= 0; + b9_data_delayed_1 <= 0; + b9_data_delayed_2 <= 0; + b9_data_delayed_3 <= 0; + b9_data_delayed_4 <= 0; + b9_data_delayed_5 <= 0; + b9_data_delayed_6 <= 0; + b9_data_delayed_7 <= 0; + b9_data_delayed_8 <= 0; + b9_data_delayed_9 <= 0; + b10_data_delayed_1 <= 0; + b10_data_delayed_2 <= 0; + b10_data_delayed_3 <= 0; + b10_data_delayed_4 <= 0; + b10_data_delayed_5 <= 0; + b10_data_delayed_6 <= 0; + b10_data_delayed_7 <= 0; + b10_data_delayed_8 <= 0; + b10_data_delayed_9 <= 0; + b10_data_delayed_10 <= 0; + b11_data_delayed_1 <= 0; + b11_data_delayed_2 <= 0; + b11_data_delayed_3 <= 0; + b11_data_delayed_4 <= 0; + b11_data_delayed_5 <= 0; + b11_data_delayed_6 <= 0; + b11_data_delayed_7 <= 0; + b11_data_delayed_8 <= 0; + b11_data_delayed_9 <= 0; + b11_data_delayed_10 <= 0; + b11_data_delayed_11 <= 0; + b12_data_delayed_1 <= 0; + b12_data_delayed_2 <= 0; + b12_data_delayed_3 <= 0; + b12_data_delayed_4 <= 0; + b12_data_delayed_5 <= 0; + b12_data_delayed_6 <= 0; + b12_data_delayed_7 <= 0; + b12_data_delayed_8 <= 0; + b12_data_delayed_9 <= 0; + b12_data_delayed_10 <= 0; + b12_data_delayed_11 <= 0; + b12_data_delayed_12 <= 0; + b13_data_delayed_1 <= 0; + b13_data_delayed_2 <= 0; + b13_data_delayed_3 <= 0; + b13_data_delayed_4 <= 0; + b13_data_delayed_5 <= 0; + b13_data_delayed_6 <= 0; + b13_data_delayed_7 <= 0; + b13_data_delayed_8 <= 0; + b13_data_delayed_9 <= 0; + b13_data_delayed_10 <= 0; + b13_data_delayed_11 <= 0; + b13_data_delayed_12 <= 0; + b13_data_delayed_13 <= 0; + b14_data_delayed_1 <= 0; + b14_data_delayed_2 <= 0; + b14_data_delayed_3 <= 0; + b14_data_delayed_4 <= 0; + b14_data_delayed_5 <= 0; + b14_data_delayed_6 <= 0; + b14_data_delayed_7 <= 0; + b14_data_delayed_8 <= 0; + b14_data_delayed_9 <= 0; + b14_data_delayed_10 <= 0; + b14_data_delayed_11 <= 0; + b14_data_delayed_12 <= 0; + b14_data_delayed_13 <= 0; + b14_data_delayed_14 <= 0; + b15_data_delayed_1 <= 0; + b15_data_delayed_2 <= 0; + b15_data_delayed_3 <= 0; + b15_data_delayed_4 <= 0; + b15_data_delayed_5 <= 0; + b15_data_delayed_6 <= 0; + b15_data_delayed_7 <= 0; + b15_data_delayed_8 <= 0; + b15_data_delayed_9 <= 0; + b15_data_delayed_10 <= 0; + b15_data_delayed_11 <= 0; + b15_data_delayed_12 <= 0; + b15_data_delayed_13 <= 0; + b15_data_delayed_14 <= 0; + b15_data_delayed_15 <= 0; + end + else begin + b1_data_delayed_1 <= b1_data; + b2_data_delayed_1 <= b2_data; + b2_data_delayed_2 <= b2_data_delayed_1; + b3_data_delayed_1 <= b3_data; + b3_data_delayed_2 <= b3_data_delayed_1; + b3_data_delayed_3 <= b3_data_delayed_2; + b4_data_delayed_1 <= b4_data; + b4_data_delayed_2 <= b4_data_delayed_1; + b4_data_delayed_3 <= b4_data_delayed_2; + b4_data_delayed_4 <= b4_data_delayed_3; + b5_data_delayed_1 <= b5_data; + b5_data_delayed_2 <= b5_data_delayed_1; + b5_data_delayed_3 <= b5_data_delayed_2; + b5_data_delayed_4 <= b5_data_delayed_3; + b5_data_delayed_5 <= b5_data_delayed_4; + b6_data_delayed_1 <= b6_data; + b6_data_delayed_2 <= b6_data_delayed_1; + b6_data_delayed_3 <= b6_data_delayed_2; + b6_data_delayed_4 <= b6_data_delayed_3; + b6_data_delayed_5 <= b6_data_delayed_4; + b6_data_delayed_6 <= b6_data_delayed_5; + b7_data_delayed_1 <= b7_data; + b7_data_delayed_2 <= b7_data_delayed_1; + b7_data_delayed_3 <= b7_data_delayed_2; + b7_data_delayed_4 <= b7_data_delayed_3; + b7_data_delayed_5 <= b7_data_delayed_4; + b7_data_delayed_6 <= b7_data_delayed_5; + b7_data_delayed_7 <= b7_data_delayed_6; + b8_data_delayed_1 <= b8_data; + b8_data_delayed_2 <= b8_data_delayed_1; + b8_data_delayed_3 <= b8_data_delayed_2; + b8_data_delayed_4 <= b8_data_delayed_3; + b8_data_delayed_5 <= b8_data_delayed_4; + b8_data_delayed_6 <= b8_data_delayed_5; + b8_data_delayed_7 <= b8_data_delayed_6; + b8_data_delayed_8 <= b8_data_delayed_7; + b9_data_delayed_1 <= b9_data; + b9_data_delayed_2 <= b9_data_delayed_1; + b9_data_delayed_3 <= b9_data_delayed_2; + b9_data_delayed_4 <= b9_data_delayed_3; + b9_data_delayed_5 <= b9_data_delayed_4; + b9_data_delayed_6 <= b9_data_delayed_5; + b9_data_delayed_7 <= b9_data_delayed_6; + b9_data_delayed_8 <= b9_data_delayed_7; + b9_data_delayed_9 <= b9_data_delayed_8; + b10_data_delayed_1 <= b10_data; + b10_data_delayed_2 <= b10_data_delayed_1; + b10_data_delayed_3 <= b10_data_delayed_2; + b10_data_delayed_4 <= b10_data_delayed_3; + b10_data_delayed_5 <= b10_data_delayed_4; + b10_data_delayed_6 <= b10_data_delayed_5; + b10_data_delayed_7 <= b10_data_delayed_6; + b10_data_delayed_8 <= b10_data_delayed_7; + b10_data_delayed_9 <= b10_data_delayed_8; + b10_data_delayed_10 <= b10_data_delayed_9; + b11_data_delayed_1 <= b11_data; + b11_data_delayed_2 <= b11_data_delayed_1; + b11_data_delayed_3 <= b11_data_delayed_2; + b11_data_delayed_4 <= b11_data_delayed_3; + b11_data_delayed_5 <= b11_data_delayed_4; + b11_data_delayed_6 <= b11_data_delayed_5; + b11_data_delayed_7 <= b11_data_delayed_6; + b11_data_delayed_8 <= b11_data_delayed_7; + b11_data_delayed_9 <= b11_data_delayed_8; + b11_data_delayed_10 <= b11_data_delayed_9; + b11_data_delayed_11 <= b11_data_delayed_10; + b12_data_delayed_1 <= b12_data; + b12_data_delayed_2 <= b12_data_delayed_1; + b12_data_delayed_3 <= b12_data_delayed_2; + b12_data_delayed_4 <= b12_data_delayed_3; + b12_data_delayed_5 <= b12_data_delayed_4; + b12_data_delayed_6 <= b12_data_delayed_5; + b12_data_delayed_7 <= b12_data_delayed_6; + b12_data_delayed_8 <= b12_data_delayed_7; + b12_data_delayed_9 <= b12_data_delayed_8; + b12_data_delayed_10 <= b12_data_delayed_9; + b12_data_delayed_11 <= b12_data_delayed_10; + b12_data_delayed_12 <= b12_data_delayed_11; + b13_data_delayed_1 <= b13_data; + b13_data_delayed_2 <= b13_data_delayed_1; + b13_data_delayed_3 <= b13_data_delayed_2; + b13_data_delayed_4 <= b13_data_delayed_3; + b13_data_delayed_5 <= b13_data_delayed_4; + b13_data_delayed_6 <= b13_data_delayed_5; + b13_data_delayed_7 <= b13_data_delayed_6; + b13_data_delayed_8 <= b13_data_delayed_7; + b13_data_delayed_9 <= b13_data_delayed_8; + b13_data_delayed_10 <= b13_data_delayed_9; + b13_data_delayed_11 <= b13_data_delayed_10; + b13_data_delayed_12 <= b13_data_delayed_11; + b13_data_delayed_13 <= b13_data_delayed_12; + b14_data_delayed_1 <= b14_data; + b14_data_delayed_2 <= b14_data_delayed_1; + b14_data_delayed_3 <= b14_data_delayed_2; + b14_data_delayed_4 <= b14_data_delayed_3; + b14_data_delayed_5 <= b14_data_delayed_4; + b14_data_delayed_6 <= b14_data_delayed_5; + b14_data_delayed_7 <= b14_data_delayed_6; + b14_data_delayed_8 <= b14_data_delayed_7; + b14_data_delayed_9 <= b14_data_delayed_8; + b14_data_delayed_10 <= b14_data_delayed_9; + b14_data_delayed_11 <= b14_data_delayed_10; + b14_data_delayed_12 <= b14_data_delayed_11; + b14_data_delayed_13 <= b14_data_delayed_12; + b14_data_delayed_14 <= b14_data_delayed_13; + b15_data_delayed_1 <= b15_data; + b15_data_delayed_2 <= b15_data_delayed_1; + b15_data_delayed_3 <= b15_data_delayed_2; + b15_data_delayed_4 <= b15_data_delayed_3; + b15_data_delayed_5 <= b15_data_delayed_4; + b15_data_delayed_6 <= b15_data_delayed_5; + b15_data_delayed_7 <= b15_data_delayed_6; + b15_data_delayed_8 <= b15_data_delayed_7; + b15_data_delayed_9 <= b15_data_delayed_8; + b15_data_delayed_10 <= b15_data_delayed_9; + b15_data_delayed_11 <= b15_data_delayed_10; + b15_data_delayed_12 <= b15_data_delayed_11; + b15_data_delayed_13 <= b15_data_delayed_12; + b15_data_delayed_14 <= b15_data_delayed_13; + b15_data_delayed_15 <= b15_data_delayed_14; + end +end + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Systolically connected PEs +////////////////////////////////////////////////////////////////////////// + +module systolic_pe_matrix( + reset, + clk, + pe_reset, + b_data_sel, + a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, + b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15, + c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, + matrixC0_0, + matrixC0_1, + matrixC0_2, + matrixC0_3, + matrixC0_4, + matrixC0_5, + matrixC0_6, + matrixC0_7, + matrixC0_8, + matrixC0_9, + matrixC0_10, + matrixC0_11, + matrixC0_12, + matrixC0_13, + matrixC0_14, + matrixC0_15, + matrixC1_0, + matrixC1_1, + matrixC1_2, + matrixC1_3, + matrixC1_4, + matrixC1_5, + matrixC1_6, + matrixC1_7, + matrixC1_8, + matrixC1_9, + matrixC1_10, + matrixC1_11, + matrixC1_12, + matrixC1_13, + matrixC1_14, + matrixC1_15, + matrixC2_0, + matrixC2_1, + matrixC2_2, + matrixC2_3, + matrixC2_4, + matrixC2_5, + matrixC2_6, + matrixC2_7, + matrixC2_8, + matrixC2_9, + matrixC2_10, + matrixC2_11, + matrixC2_12, + matrixC2_13, + matrixC2_14, + matrixC2_15, + matrixC3_0, + matrixC3_1, + matrixC3_2, + matrixC3_3, + matrixC3_4, + matrixC3_5, + matrixC3_6, + matrixC3_7, + matrixC3_8, + matrixC3_9, + matrixC3_10, + matrixC3_11, + matrixC3_12, + matrixC3_13, + matrixC3_14, + matrixC3_15, + matrixC4_0, + matrixC4_1, + matrixC4_2, + matrixC4_3, + matrixC4_4, + matrixC4_5, + matrixC4_6, + matrixC4_7, + matrixC4_8, + matrixC4_9, + matrixC4_10, + matrixC4_11, + matrixC4_12, + matrixC4_13, + matrixC4_14, + matrixC4_15, + matrixC5_0, + matrixC5_1, + matrixC5_2, + matrixC5_3, + matrixC5_4, + matrixC5_5, + matrixC5_6, + matrixC5_7, + matrixC5_8, + matrixC5_9, + matrixC5_10, + matrixC5_11, + matrixC5_12, + matrixC5_13, + matrixC5_14, + matrixC5_15, + matrixC6_0, + matrixC6_1, + matrixC6_2, + matrixC6_3, + matrixC6_4, + matrixC6_5, + matrixC6_6, + matrixC6_7, + matrixC6_8, + matrixC6_9, + matrixC6_10, + matrixC6_11, + matrixC6_12, + matrixC6_13, + matrixC6_14, + matrixC6_15, + matrixC7_0, + matrixC7_1, + matrixC7_2, + matrixC7_3, + matrixC7_4, + matrixC7_5, + matrixC7_6, + matrixC7_7, + matrixC7_8, + matrixC7_9, + matrixC7_10, + matrixC7_11, + matrixC7_12, + matrixC7_13, + matrixC7_14, + matrixC7_15, + matrixC8_0, + matrixC8_1, + matrixC8_2, + matrixC8_3, + matrixC8_4, + matrixC8_5, + matrixC8_6, + matrixC8_7, + matrixC8_8, + matrixC8_9, + matrixC8_10, + matrixC8_11, + matrixC8_12, + matrixC8_13, + matrixC8_14, + matrixC8_15, + matrixC9_0, + matrixC9_1, + matrixC9_2, + matrixC9_3, + matrixC9_4, + matrixC9_5, + matrixC9_6, + matrixC9_7, + matrixC9_8, + matrixC9_9, + matrixC9_10, + matrixC9_11, + matrixC9_12, + matrixC9_13, + matrixC9_14, + matrixC9_15, + matrixC10_0, + matrixC10_1, + matrixC10_2, + matrixC10_3, + matrixC10_4, + matrixC10_5, + matrixC10_6, + matrixC10_7, + matrixC10_8, + matrixC10_9, + matrixC10_10, + matrixC10_11, + matrixC10_12, + matrixC10_13, + matrixC10_14, + matrixC10_15, + matrixC11_0, + matrixC11_1, + matrixC11_2, + matrixC11_3, + matrixC11_4, + matrixC11_5, + matrixC11_6, + matrixC11_7, + matrixC11_8, + matrixC11_9, + matrixC11_10, + matrixC11_11, + matrixC11_12, + matrixC11_13, + matrixC11_14, + matrixC11_15, + matrixC12_0, + matrixC12_1, + matrixC12_2, + matrixC12_3, + matrixC12_4, + matrixC12_5, + matrixC12_6, + matrixC12_7, + matrixC12_8, + matrixC12_9, + matrixC12_10, + matrixC12_11, + matrixC12_12, + matrixC12_13, + matrixC12_14, + matrixC12_15, + matrixC13_0, + matrixC13_1, + matrixC13_2, + matrixC13_3, + matrixC13_4, + matrixC13_5, + matrixC13_6, + matrixC13_7, + matrixC13_8, + matrixC13_9, + matrixC13_10, + matrixC13_11, + matrixC13_12, + matrixC13_13, + matrixC13_14, + matrixC13_15, + matrixC14_0, + matrixC14_1, + matrixC14_2, + matrixC14_3, + matrixC14_4, + matrixC14_5, + matrixC14_6, + matrixC14_7, + matrixC14_8, + matrixC14_9, + matrixC14_10, + matrixC14_11, + matrixC14_12, + matrixC14_13, + matrixC14_14, + matrixC14_15, + matrixC15_0, + matrixC15_1, + matrixC15_2, + matrixC15_3, + matrixC15_4, + matrixC15_5, + matrixC15_6, + matrixC15_7, + matrixC15_8, + matrixC15_9, + matrixC15_10, + matrixC15_11, + matrixC15_12, + matrixC15_13, + matrixC15_14, + matrixC15_15, + a_data_out, + b_data_out, + b_data_valid_ping, + b_data_valid_pong +); + +input clk; +input reset; +input pe_reset; +input b_data_sel; +input b_data_valid_ping; +input b_data_valid_pong; +input [`DWIDTH-1:0] a0; +input [`DWIDTH-1:0] a1; +input [`DWIDTH-1:0] a2; +input [`DWIDTH-1:0] a3; +input [`DWIDTH-1:0] a4; +input [`DWIDTH-1:0] a5; +input [`DWIDTH-1:0] a6; +input [`DWIDTH-1:0] a7; +input [`DWIDTH-1:0] a8; +input [`DWIDTH-1:0] a9; +input [`DWIDTH-1:0] a10; +input [`DWIDTH-1:0] a11; +input [`DWIDTH-1:0] a12; +input [`DWIDTH-1:0] a13; +input [`DWIDTH-1:0] a14; +input [`DWIDTH-1:0] a15; +input [`DWIDTH-1:0] b0; +input [`DWIDTH-1:0] b1; +input [`DWIDTH-1:0] b2; +input [`DWIDTH-1:0] b3; +input [`DWIDTH-1:0] b4; +input [`DWIDTH-1:0] b5; +input [`DWIDTH-1:0] b6; +input [`DWIDTH-1:0] b7; +input [`DWIDTH-1:0] b8; +input [`DWIDTH-1:0] b9; +input [`DWIDTH-1:0] b10; +input [`DWIDTH-1:0] b11; +input [`DWIDTH-1:0] b12; +input [`DWIDTH-1:0] b13; +input [`DWIDTH-1:0] b14; +input [`DWIDTH-1:0] b15; +input [`DWIDTH-1:0] c0; +input [`DWIDTH-1:0] c1; +input [`DWIDTH-1:0] c2; +input [`DWIDTH-1:0] c3; +input [`DWIDTH-1:0] c4; +input [`DWIDTH-1:0] c5; +input [`DWIDTH-1:0] c6; +input [`DWIDTH-1:0] c7; +input [`DWIDTH-1:0] c8; +input [`DWIDTH-1:0] c9; +input [`DWIDTH-1:0] c10; +input [`DWIDTH-1:0] c11; +input [`DWIDTH-1:0] c12; +input [`DWIDTH-1:0] c13; +input [`DWIDTH-1:0] c14; +input [`DWIDTH-1:0] c15; +output [`DWIDTH-1:0] matrixC0_0; +output [`DWIDTH-1:0] matrixC0_1; +output [`DWIDTH-1:0] matrixC0_2; +output [`DWIDTH-1:0] matrixC0_3; +output [`DWIDTH-1:0] matrixC0_4; +output [`DWIDTH-1:0] matrixC0_5; +output [`DWIDTH-1:0] matrixC0_6; +output [`DWIDTH-1:0] matrixC0_7; +output [`DWIDTH-1:0] matrixC0_8; +output [`DWIDTH-1:0] matrixC0_9; +output [`DWIDTH-1:0] matrixC0_10; +output [`DWIDTH-1:0] matrixC0_11; +output [`DWIDTH-1:0] matrixC0_12; +output [`DWIDTH-1:0] matrixC0_13; +output [`DWIDTH-1:0] matrixC0_14; +output [`DWIDTH-1:0] matrixC0_15; +output [`DWIDTH-1:0] matrixC1_0; +output [`DWIDTH-1:0] matrixC1_1; +output [`DWIDTH-1:0] matrixC1_2; +output [`DWIDTH-1:0] matrixC1_3; +output [`DWIDTH-1:0] matrixC1_4; +output [`DWIDTH-1:0] matrixC1_5; +output [`DWIDTH-1:0] matrixC1_6; +output [`DWIDTH-1:0] matrixC1_7; +output [`DWIDTH-1:0] matrixC1_8; +output [`DWIDTH-1:0] matrixC1_9; +output [`DWIDTH-1:0] matrixC1_10; +output [`DWIDTH-1:0] matrixC1_11; +output [`DWIDTH-1:0] matrixC1_12; +output [`DWIDTH-1:0] matrixC1_13; +output [`DWIDTH-1:0] matrixC1_14; +output [`DWIDTH-1:0] matrixC1_15; +output [`DWIDTH-1:0] matrixC2_0; +output [`DWIDTH-1:0] matrixC2_1; +output [`DWIDTH-1:0] matrixC2_2; +output [`DWIDTH-1:0] matrixC2_3; +output [`DWIDTH-1:0] matrixC2_4; +output [`DWIDTH-1:0] matrixC2_5; +output [`DWIDTH-1:0] matrixC2_6; +output [`DWIDTH-1:0] matrixC2_7; +output [`DWIDTH-1:0] matrixC2_8; +output [`DWIDTH-1:0] matrixC2_9; +output [`DWIDTH-1:0] matrixC2_10; +output [`DWIDTH-1:0] matrixC2_11; +output [`DWIDTH-1:0] matrixC2_12; +output [`DWIDTH-1:0] matrixC2_13; +output [`DWIDTH-1:0] matrixC2_14; +output [`DWIDTH-1:0] matrixC2_15; +output [`DWIDTH-1:0] matrixC3_0; +output [`DWIDTH-1:0] matrixC3_1; +output [`DWIDTH-1:0] matrixC3_2; +output [`DWIDTH-1:0] matrixC3_3; +output [`DWIDTH-1:0] matrixC3_4; +output [`DWIDTH-1:0] matrixC3_5; +output [`DWIDTH-1:0] matrixC3_6; +output [`DWIDTH-1:0] matrixC3_7; +output [`DWIDTH-1:0] matrixC3_8; +output [`DWIDTH-1:0] matrixC3_9; +output [`DWIDTH-1:0] matrixC3_10; +output [`DWIDTH-1:0] matrixC3_11; +output [`DWIDTH-1:0] matrixC3_12; +output [`DWIDTH-1:0] matrixC3_13; +output [`DWIDTH-1:0] matrixC3_14; +output [`DWIDTH-1:0] matrixC3_15; +output [`DWIDTH-1:0] matrixC4_0; +output [`DWIDTH-1:0] matrixC4_1; +output [`DWIDTH-1:0] matrixC4_2; +output [`DWIDTH-1:0] matrixC4_3; +output [`DWIDTH-1:0] matrixC4_4; +output [`DWIDTH-1:0] matrixC4_5; +output [`DWIDTH-1:0] matrixC4_6; +output [`DWIDTH-1:0] matrixC4_7; +output [`DWIDTH-1:0] matrixC4_8; +output [`DWIDTH-1:0] matrixC4_9; +output [`DWIDTH-1:0] matrixC4_10; +output [`DWIDTH-1:0] matrixC4_11; +output [`DWIDTH-1:0] matrixC4_12; +output [`DWIDTH-1:0] matrixC4_13; +output [`DWIDTH-1:0] matrixC4_14; +output [`DWIDTH-1:0] matrixC4_15; +output [`DWIDTH-1:0] matrixC5_0; +output [`DWIDTH-1:0] matrixC5_1; +output [`DWIDTH-1:0] matrixC5_2; +output [`DWIDTH-1:0] matrixC5_3; +output [`DWIDTH-1:0] matrixC5_4; +output [`DWIDTH-1:0] matrixC5_5; +output [`DWIDTH-1:0] matrixC5_6; +output [`DWIDTH-1:0] matrixC5_7; +output [`DWIDTH-1:0] matrixC5_8; +output [`DWIDTH-1:0] matrixC5_9; +output [`DWIDTH-1:0] matrixC5_10; +output [`DWIDTH-1:0] matrixC5_11; +output [`DWIDTH-1:0] matrixC5_12; +output [`DWIDTH-1:0] matrixC5_13; +output [`DWIDTH-1:0] matrixC5_14; +output [`DWIDTH-1:0] matrixC5_15; +output [`DWIDTH-1:0] matrixC6_0; +output [`DWIDTH-1:0] matrixC6_1; +output [`DWIDTH-1:0] matrixC6_2; +output [`DWIDTH-1:0] matrixC6_3; +output [`DWIDTH-1:0] matrixC6_4; +output [`DWIDTH-1:0] matrixC6_5; +output [`DWIDTH-1:0] matrixC6_6; +output [`DWIDTH-1:0] matrixC6_7; +output [`DWIDTH-1:0] matrixC6_8; +output [`DWIDTH-1:0] matrixC6_9; +output [`DWIDTH-1:0] matrixC6_10; +output [`DWIDTH-1:0] matrixC6_11; +output [`DWIDTH-1:0] matrixC6_12; +output [`DWIDTH-1:0] matrixC6_13; +output [`DWIDTH-1:0] matrixC6_14; +output [`DWIDTH-1:0] matrixC6_15; +output [`DWIDTH-1:0] matrixC7_0; +output [`DWIDTH-1:0] matrixC7_1; +output [`DWIDTH-1:0] matrixC7_2; +output [`DWIDTH-1:0] matrixC7_3; +output [`DWIDTH-1:0] matrixC7_4; +output [`DWIDTH-1:0] matrixC7_5; +output [`DWIDTH-1:0] matrixC7_6; +output [`DWIDTH-1:0] matrixC7_7; +output [`DWIDTH-1:0] matrixC7_8; +output [`DWIDTH-1:0] matrixC7_9; +output [`DWIDTH-1:0] matrixC7_10; +output [`DWIDTH-1:0] matrixC7_11; +output [`DWIDTH-1:0] matrixC7_12; +output [`DWIDTH-1:0] matrixC7_13; +output [`DWIDTH-1:0] matrixC7_14; +output [`DWIDTH-1:0] matrixC7_15; +output [`DWIDTH-1:0] matrixC8_0; +output [`DWIDTH-1:0] matrixC8_1; +output [`DWIDTH-1:0] matrixC8_2; +output [`DWIDTH-1:0] matrixC8_3; +output [`DWIDTH-1:0] matrixC8_4; +output [`DWIDTH-1:0] matrixC8_5; +output [`DWIDTH-1:0] matrixC8_6; +output [`DWIDTH-1:0] matrixC8_7; +output [`DWIDTH-1:0] matrixC8_8; +output [`DWIDTH-1:0] matrixC8_9; +output [`DWIDTH-1:0] matrixC8_10; +output [`DWIDTH-1:0] matrixC8_11; +output [`DWIDTH-1:0] matrixC8_12; +output [`DWIDTH-1:0] matrixC8_13; +output [`DWIDTH-1:0] matrixC8_14; +output [`DWIDTH-1:0] matrixC8_15; +output [`DWIDTH-1:0] matrixC9_0; +output [`DWIDTH-1:0] matrixC9_1; +output [`DWIDTH-1:0] matrixC9_2; +output [`DWIDTH-1:0] matrixC9_3; +output [`DWIDTH-1:0] matrixC9_4; +output [`DWIDTH-1:0] matrixC9_5; +output [`DWIDTH-1:0] matrixC9_6; +output [`DWIDTH-1:0] matrixC9_7; +output [`DWIDTH-1:0] matrixC9_8; +output [`DWIDTH-1:0] matrixC9_9; +output [`DWIDTH-1:0] matrixC9_10; +output [`DWIDTH-1:0] matrixC9_11; +output [`DWIDTH-1:0] matrixC9_12; +output [`DWIDTH-1:0] matrixC9_13; +output [`DWIDTH-1:0] matrixC9_14; +output [`DWIDTH-1:0] matrixC9_15; +output [`DWIDTH-1:0] matrixC10_0; +output [`DWIDTH-1:0] matrixC10_1; +output [`DWIDTH-1:0] matrixC10_2; +output [`DWIDTH-1:0] matrixC10_3; +output [`DWIDTH-1:0] matrixC10_4; +output [`DWIDTH-1:0] matrixC10_5; +output [`DWIDTH-1:0] matrixC10_6; +output [`DWIDTH-1:0] matrixC10_7; +output [`DWIDTH-1:0] matrixC10_8; +output [`DWIDTH-1:0] matrixC10_9; +output [`DWIDTH-1:0] matrixC10_10; +output [`DWIDTH-1:0] matrixC10_11; +output [`DWIDTH-1:0] matrixC10_12; +output [`DWIDTH-1:0] matrixC10_13; +output [`DWIDTH-1:0] matrixC10_14; +output [`DWIDTH-1:0] matrixC10_15; +output [`DWIDTH-1:0] matrixC11_0; +output [`DWIDTH-1:0] matrixC11_1; +output [`DWIDTH-1:0] matrixC11_2; +output [`DWIDTH-1:0] matrixC11_3; +output [`DWIDTH-1:0] matrixC11_4; +output [`DWIDTH-1:0] matrixC11_5; +output [`DWIDTH-1:0] matrixC11_6; +output [`DWIDTH-1:0] matrixC11_7; +output [`DWIDTH-1:0] matrixC11_8; +output [`DWIDTH-1:0] matrixC11_9; +output [`DWIDTH-1:0] matrixC11_10; +output [`DWIDTH-1:0] matrixC11_11; +output [`DWIDTH-1:0] matrixC11_12; +output [`DWIDTH-1:0] matrixC11_13; +output [`DWIDTH-1:0] matrixC11_14; +output [`DWIDTH-1:0] matrixC11_15; +output [`DWIDTH-1:0] matrixC12_0; +output [`DWIDTH-1:0] matrixC12_1; +output [`DWIDTH-1:0] matrixC12_2; +output [`DWIDTH-1:0] matrixC12_3; +output [`DWIDTH-1:0] matrixC12_4; +output [`DWIDTH-1:0] matrixC12_5; +output [`DWIDTH-1:0] matrixC12_6; +output [`DWIDTH-1:0] matrixC12_7; +output [`DWIDTH-1:0] matrixC12_8; +output [`DWIDTH-1:0] matrixC12_9; +output [`DWIDTH-1:0] matrixC12_10; +output [`DWIDTH-1:0] matrixC12_11; +output [`DWIDTH-1:0] matrixC12_12; +output [`DWIDTH-1:0] matrixC12_13; +output [`DWIDTH-1:0] matrixC12_14; +output [`DWIDTH-1:0] matrixC12_15; +output [`DWIDTH-1:0] matrixC13_0; +output [`DWIDTH-1:0] matrixC13_1; +output [`DWIDTH-1:0] matrixC13_2; +output [`DWIDTH-1:0] matrixC13_3; +output [`DWIDTH-1:0] matrixC13_4; +output [`DWIDTH-1:0] matrixC13_5; +output [`DWIDTH-1:0] matrixC13_6; +output [`DWIDTH-1:0] matrixC13_7; +output [`DWIDTH-1:0] matrixC13_8; +output [`DWIDTH-1:0] matrixC13_9; +output [`DWIDTH-1:0] matrixC13_10; +output [`DWIDTH-1:0] matrixC13_11; +output [`DWIDTH-1:0] matrixC13_12; +output [`DWIDTH-1:0] matrixC13_13; +output [`DWIDTH-1:0] matrixC13_14; +output [`DWIDTH-1:0] matrixC13_15; +output [`DWIDTH-1:0] matrixC14_0; +output [`DWIDTH-1:0] matrixC14_1; +output [`DWIDTH-1:0] matrixC14_2; +output [`DWIDTH-1:0] matrixC14_3; +output [`DWIDTH-1:0] matrixC14_4; +output [`DWIDTH-1:0] matrixC14_5; +output [`DWIDTH-1:0] matrixC14_6; +output [`DWIDTH-1:0] matrixC14_7; +output [`DWIDTH-1:0] matrixC14_8; +output [`DWIDTH-1:0] matrixC14_9; +output [`DWIDTH-1:0] matrixC14_10; +output [`DWIDTH-1:0] matrixC14_11; +output [`DWIDTH-1:0] matrixC14_12; +output [`DWIDTH-1:0] matrixC14_13; +output [`DWIDTH-1:0] matrixC14_14; +output [`DWIDTH-1:0] matrixC14_15; +output [`DWIDTH-1:0] matrixC15_0; +output [`DWIDTH-1:0] matrixC15_1; +output [`DWIDTH-1:0] matrixC15_2; +output [`DWIDTH-1:0] matrixC15_3; +output [`DWIDTH-1:0] matrixC15_4; +output [`DWIDTH-1:0] matrixC15_5; +output [`DWIDTH-1:0] matrixC15_6; +output [`DWIDTH-1:0] matrixC15_7; +output [`DWIDTH-1:0] matrixC15_8; +output [`DWIDTH-1:0] matrixC15_9; +output [`DWIDTH-1:0] matrixC15_10; +output [`DWIDTH-1:0] matrixC15_11; +output [`DWIDTH-1:0] matrixC15_12; +output [`DWIDTH-1:0] matrixC15_13; +output [`DWIDTH-1:0] matrixC15_14; +output [`DWIDTH-1:0] matrixC15_15; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + + +wire [`DWIDTH-1:0] a0_0to0_1, a0_1to0_2, a0_2to0_3, a0_3to0_4, a0_4to0_5, a0_5to0_6, a0_6to0_7, a0_7to0_8, a0_8to0_9, a0_9to0_10, a0_10to0_11, a0_11to0_12, a0_12to0_13, a0_13to0_14, a0_14to0_15, a0_15to0_16; +wire [`DWIDTH-1:0] a1_0to1_1, a1_1to1_2, a1_2to1_3, a1_3to1_4, a1_4to1_5, a1_5to1_6, a1_6to1_7, a1_7to1_8, a1_8to1_9, a1_9to1_10, a1_10to1_11, a1_11to1_12, a1_12to1_13, a1_13to1_14, a1_14to1_15, a1_15to1_16; +wire [`DWIDTH-1:0] a2_0to2_1, a2_1to2_2, a2_2to2_3, a2_3to2_4, a2_4to2_5, a2_5to2_6, a2_6to2_7, a2_7to2_8, a2_8to2_9, a2_9to2_10, a2_10to2_11, a2_11to2_12, a2_12to2_13, a2_13to2_14, a2_14to2_15, a2_15to2_16; +wire [`DWIDTH-1:0] a3_0to3_1, a3_1to3_2, a3_2to3_3, a3_3to3_4, a3_4to3_5, a3_5to3_6, a3_6to3_7, a3_7to3_8, a3_8to3_9, a3_9to3_10, a3_10to3_11, a3_11to3_12, a3_12to3_13, a3_13to3_14, a3_14to3_15, a3_15to3_16; +wire [`DWIDTH-1:0] a4_0to4_1, a4_1to4_2, a4_2to4_3, a4_3to4_4, a4_4to4_5, a4_5to4_6, a4_6to4_7, a4_7to4_8, a4_8to4_9, a4_9to4_10, a4_10to4_11, a4_11to4_12, a4_12to4_13, a4_13to4_14, a4_14to4_15, a4_15to4_16; +wire [`DWIDTH-1:0] a5_0to5_1, a5_1to5_2, a5_2to5_3, a5_3to5_4, a5_4to5_5, a5_5to5_6, a5_6to5_7, a5_7to5_8, a5_8to5_9, a5_9to5_10, a5_10to5_11, a5_11to5_12, a5_12to5_13, a5_13to5_14, a5_14to5_15, a5_15to5_16; +wire [`DWIDTH-1:0] a6_0to6_1, a6_1to6_2, a6_2to6_3, a6_3to6_4, a6_4to6_5, a6_5to6_6, a6_6to6_7, a6_7to6_8, a6_8to6_9, a6_9to6_10, a6_10to6_11, a6_11to6_12, a6_12to6_13, a6_13to6_14, a6_14to6_15, a6_15to6_16; +wire [`DWIDTH-1:0] a7_0to7_1, a7_1to7_2, a7_2to7_3, a7_3to7_4, a7_4to7_5, a7_5to7_6, a7_6to7_7, a7_7to7_8, a7_8to7_9, a7_9to7_10, a7_10to7_11, a7_11to7_12, a7_12to7_13, a7_13to7_14, a7_14to7_15, a7_15to7_16; +wire [`DWIDTH-1:0] a8_0to8_1, a8_1to8_2, a8_2to8_3, a8_3to8_4, a8_4to8_5, a8_5to8_6, a8_6to8_7, a8_7to8_8, a8_8to8_9, a8_9to8_10, a8_10to8_11, a8_11to8_12, a8_12to8_13, a8_13to8_14, a8_14to8_15, a8_15to8_16; +wire [`DWIDTH-1:0] a9_0to9_1, a9_1to9_2, a9_2to9_3, a9_3to9_4, a9_4to9_5, a9_5to9_6, a9_6to9_7, a9_7to9_8, a9_8to9_9, a9_9to9_10, a9_10to9_11, a9_11to9_12, a9_12to9_13, a9_13to9_14, a9_14to9_15, a9_15to9_16; +wire [`DWIDTH-1:0] a10_0to10_1, a10_1to10_2, a10_2to10_3, a10_3to10_4, a10_4to10_5, a10_5to10_6, a10_6to10_7, a10_7to10_8, a10_8to10_9, a10_9to10_10, a10_10to10_11, a10_11to10_12, a10_12to10_13, a10_13to10_14, a10_14to10_15, a10_15to10_16; +wire [`DWIDTH-1:0] a11_0to11_1, a11_1to11_2, a11_2to11_3, a11_3to11_4, a11_4to11_5, a11_5to11_6, a11_6to11_7, a11_7to11_8, a11_8to11_9, a11_9to11_10, a11_10to11_11, a11_11to11_12, a11_12to11_13, a11_13to11_14, a11_14to11_15, a11_15to11_16; +wire [`DWIDTH-1:0] a12_0to12_1, a12_1to12_2, a12_2to12_3, a12_3to12_4, a12_4to12_5, a12_5to12_6, a12_6to12_7, a12_7to12_8, a12_8to12_9, a12_9to12_10, a12_10to12_11, a12_11to12_12, a12_12to12_13, a12_13to12_14, a12_14to12_15, a12_15to12_16; +wire [`DWIDTH-1:0] a13_0to13_1, a13_1to13_2, a13_2to13_3, a13_3to13_4, a13_4to13_5, a13_5to13_6, a13_6to13_7, a13_7to13_8, a13_8to13_9, a13_9to13_10, a13_10to13_11, a13_11to13_12, a13_12to13_13, a13_13to13_14, a13_14to13_15, a13_15to13_16; +wire [`DWIDTH-1:0] a14_0to14_1, a14_1to14_2, a14_2to14_3, a14_3to14_4, a14_4to14_5, a14_5to14_6, a14_6to14_7, a14_7to14_8, a14_8to14_9, a14_9to14_10, a14_10to14_11, a14_11to14_12, a14_12to14_13, a14_13to14_14, a14_14to14_15, a14_15to14_16; +wire [`DWIDTH-1:0] a15_0to15_1, a15_1to15_2, a15_2to15_3, a15_3to15_4, a15_4to15_5, a15_5to15_6, a15_6to15_7, a15_7to15_8, a15_8to15_9, a15_9to15_10, a15_10to15_11, a15_11to15_12, a15_12to15_13, a15_13to15_14, a15_14to15_15, a15_15to15_16; + +wire [`DWIDTH-1:0] b0_0to1_0, b1_0to2_0, b2_0to3_0, b3_0to4_0, b4_0to5_0, b5_0to6_0, b6_0to7_0, b7_0to8_0, b8_0to9_0, b9_0to10_0, b10_0to11_0, b11_0to12_0, b12_0to13_0, b13_0to14_0, b14_0to15_0, b15_0to16_0; +wire [`DWIDTH-1:0] b0_1to1_1, b1_1to2_1, b2_1to3_1, b3_1to4_1, b4_1to5_1, b5_1to6_1, b6_1to7_1, b7_1to8_1, b8_1to9_1, b9_1to10_1, b10_1to11_1, b11_1to12_1, b12_1to13_1, b13_1to14_1, b14_1to15_1, b15_1to16_1; +wire [`DWIDTH-1:0] b0_2to1_2, b1_2to2_2, b2_2to3_2, b3_2to4_2, b4_2to5_2, b5_2to6_2, b6_2to7_2, b7_2to8_2, b8_2to9_2, b9_2to10_2, b10_2to11_2, b11_2to12_2, b12_2to13_2, b13_2to14_2, b14_2to15_2, b15_2to16_2; +wire [`DWIDTH-1:0] b0_3to1_3, b1_3to2_3, b2_3to3_3, b3_3to4_3, b4_3to5_3, b5_3to6_3, b6_3to7_3, b7_3to8_3, b8_3to9_3, b9_3to10_3, b10_3to11_3, b11_3to12_3, b12_3to13_3, b13_3to14_3, b14_3to15_3, b15_3to16_3; +wire [`DWIDTH-1:0] b0_4to1_4, b1_4to2_4, b2_4to3_4, b3_4to4_4, b4_4to5_4, b5_4to6_4, b6_4to7_4, b7_4to8_4, b8_4to9_4, b9_4to10_4, b10_4to11_4, b11_4to12_4, b12_4to13_4, b13_4to14_4, b14_4to15_4, b15_4to16_4; +wire [`DWIDTH-1:0] b0_5to1_5, b1_5to2_5, b2_5to3_5, b3_5to4_5, b4_5to5_5, b5_5to6_5, b6_5to7_5, b7_5to8_5, b8_5to9_5, b9_5to10_5, b10_5to11_5, b11_5to12_5, b12_5to13_5, b13_5to14_5, b14_5to15_5, b15_5to16_5; +wire [`DWIDTH-1:0] b0_6to1_6, b1_6to2_6, b2_6to3_6, b3_6to4_6, b4_6to5_6, b5_6to6_6, b6_6to7_6, b7_6to8_6, b8_6to9_6, b9_6to10_6, b10_6to11_6, b11_6to12_6, b12_6to13_6, b13_6to14_6, b14_6to15_6, b15_6to16_6; +wire [`DWIDTH-1:0] b0_7to1_7, b1_7to2_7, b2_7to3_7, b3_7to4_7, b4_7to5_7, b5_7to6_7, b6_7to7_7, b7_7to8_7, b8_7to9_7, b9_7to10_7, b10_7to11_7, b11_7to12_7, b12_7to13_7, b13_7to14_7, b14_7to15_7, b15_7to16_7; +wire [`DWIDTH-1:0] b0_8to1_8, b1_8to2_8, b2_8to3_8, b3_8to4_8, b4_8to5_8, b5_8to6_8, b6_8to7_8, b7_8to8_8, b8_8to9_8, b9_8to10_8, b10_8to11_8, b11_8to12_8, b12_8to13_8, b13_8to14_8, b14_8to15_8, b15_8to16_8; +wire [`DWIDTH-1:0] b0_9to1_9, b1_9to2_9, b2_9to3_9, b3_9to4_9, b4_9to5_9, b5_9to6_9, b6_9to7_9, b7_9to8_9, b8_9to9_9, b9_9to10_9, b10_9to11_9, b11_9to12_9, b12_9to13_9, b13_9to14_9, b14_9to15_9, b15_9to16_9; +wire [`DWIDTH-1:0] b0_10to1_10, b1_10to2_10, b2_10to3_10, b3_10to4_10, b4_10to5_10, b5_10to6_10, b6_10to7_10, b7_10to8_10, b8_10to9_10, b9_10to10_10, b10_10to11_10, b11_10to12_10, b12_10to13_10, b13_10to14_10, b14_10to15_10, b15_10to16_10; +wire [`DWIDTH-1:0] b0_11to1_11, b1_11to2_11, b2_11to3_11, b3_11to4_11, b4_11to5_11, b5_11to6_11, b6_11to7_11, b7_11to8_11, b8_11to9_11, b9_11to10_11, b10_11to11_11, b11_11to12_11, b12_11to13_11, b13_11to14_11, b14_11to15_11, b15_11to16_11; +wire [`DWIDTH-1:0] b0_12to1_12, b1_12to2_12, b2_12to3_12, b3_12to4_12, b4_12to5_12, b5_12to6_12, b6_12to7_12, b7_12to8_12, b8_12to9_12, b9_12to10_12, b10_12to11_12, b11_12to12_12, b12_12to13_12, b13_12to14_12, b14_12to15_12, b15_12to16_12; +wire [`DWIDTH-1:0] b0_13to1_13, b1_13to2_13, b2_13to3_13, b3_13to4_13, b4_13to5_13, b5_13to6_13, b6_13to7_13, b7_13to8_13, b8_13to9_13, b9_13to10_13, b10_13to11_13, b11_13to12_13, b12_13to13_13, b13_13to14_13, b14_13to15_13, b15_13to16_13; +wire [`DWIDTH-1:0] b0_14to1_14, b1_14to2_14, b2_14to3_14, b3_14to4_14, b4_14to5_14, b5_14to6_14, b6_14to7_14, b7_14to8_14, b8_14to9_14, b9_14to10_14, b10_14to11_14, b11_14to12_14, b12_14to13_14, b13_14to14_14, b14_14to15_14, b15_14to16_14; +wire [`DWIDTH-1:0] b0_15to1_15, b1_15to2_15, b2_15to3_15, b3_15to4_15, b4_15to5_15, b5_15to6_15, b6_15to7_15, b7_15to8_15, b8_15to9_15, b9_15to10_15, b10_15to11_15, b11_15to12_15, b12_15to13_15, b13_15to14_15, b14_15to15_15, b15_15to16_15; + +wire [`DWIDTH-1:0] b0_0to1_0_ping, b1_0to2_0_ping, b2_0to3_0_ping, b3_0to4_0_ping, b4_0to5_0_ping, b5_0to6_0_ping, b6_0to7_0_ping, b7_0to8_0_ping, b8_0to9_0_ping, b9_0to10_0_ping, b10_0to11_0_ping, b11_0to12_0_ping, b12_0to13_0_ping, b13_0to14_0_ping, b14_0to15_0_ping, b15_0to16_0_ping; +wire [`DWIDTH-1:0] b0_1to1_1_ping, b1_1to2_1_ping, b2_1to3_1_ping, b3_1to4_1_ping, b4_1to5_1_ping, b5_1to6_1_ping, b6_1to7_1_ping, b7_1to8_1_ping, b8_1to9_1_ping, b9_1to10_1_ping, b10_1to11_1_ping, b11_1to12_1_ping, b12_1to13_1_ping, b13_1to14_1_ping, b14_1to15_1_ping, b15_1to16_1_ping; +wire [`DWIDTH-1:0] b0_2to1_2_ping, b1_2to2_2_ping, b2_2to3_2_ping, b3_2to4_2_ping, b4_2to5_2_ping, b5_2to6_2_ping, b6_2to7_2_ping, b7_2to8_2_ping, b8_2to9_2_ping, b9_2to10_2_ping, b10_2to11_2_ping, b11_2to12_2_ping, b12_2to13_2_ping, b13_2to14_2_ping, b14_2to15_2_ping, b15_2to16_2_ping; +wire [`DWIDTH-1:0] b0_3to1_3_ping, b1_3to2_3_ping, b2_3to3_3_ping, b3_3to4_3_ping, b4_3to5_3_ping, b5_3to6_3_ping, b6_3to7_3_ping, b7_3to8_3_ping, b8_3to9_3_ping, b9_3to10_3_ping, b10_3to11_3_ping, b11_3to12_3_ping, b12_3to13_3_ping, b13_3to14_3_ping, b14_3to15_3_ping, b15_3to16_3_ping; +wire [`DWIDTH-1:0] b0_4to1_4_ping, b1_4to2_4_ping, b2_4to3_4_ping, b3_4to4_4_ping, b4_4to5_4_ping, b5_4to6_4_ping, b6_4to7_4_ping, b7_4to8_4_ping, b8_4to9_4_ping, b9_4to10_4_ping, b10_4to11_4_ping, b11_4to12_4_ping, b12_4to13_4_ping, b13_4to14_4_ping, b14_4to15_4_ping, b15_4to16_4_ping; +wire [`DWIDTH-1:0] b0_5to1_5_ping, b1_5to2_5_ping, b2_5to3_5_ping, b3_5to4_5_ping, b4_5to5_5_ping, b5_5to6_5_ping, b6_5to7_5_ping, b7_5to8_5_ping, b8_5to9_5_ping, b9_5to10_5_ping, b10_5to11_5_ping, b11_5to12_5_ping, b12_5to13_5_ping, b13_5to14_5_ping, b14_5to15_5_ping, b15_5to16_5_ping; +wire [`DWIDTH-1:0] b0_6to1_6_ping, b1_6to2_6_ping, b2_6to3_6_ping, b3_6to4_6_ping, b4_6to5_6_ping, b5_6to6_6_ping, b6_6to7_6_ping, b7_6to8_6_ping, b8_6to9_6_ping, b9_6to10_6_ping, b10_6to11_6_ping, b11_6to12_6_ping, b12_6to13_6_ping, b13_6to14_6_ping, b14_6to15_6_ping, b15_6to16_6_ping; +wire [`DWIDTH-1:0] b0_7to1_7_ping, b1_7to2_7_ping, b2_7to3_7_ping, b3_7to4_7_ping, b4_7to5_7_ping, b5_7to6_7_ping, b6_7to7_7_ping, b7_7to8_7_ping, b8_7to9_7_ping, b9_7to10_7_ping, b10_7to11_7_ping, b11_7to12_7_ping, b12_7to13_7_ping, b13_7to14_7_ping, b14_7to15_7_ping, b15_7to16_7_ping; +wire [`DWIDTH-1:0] b0_8to1_8_ping, b1_8to2_8_ping, b2_8to3_8_ping, b3_8to4_8_ping, b4_8to5_8_ping, b5_8to6_8_ping, b6_8to7_8_ping, b7_8to8_8_ping, b8_8to9_8_ping, b9_8to10_8_ping, b10_8to11_8_ping, b11_8to12_8_ping, b12_8to13_8_ping, b13_8to14_8_ping, b14_8to15_8_ping, b15_8to16_8_ping; +wire [`DWIDTH-1:0] b0_9to1_9_ping, b1_9to2_9_ping, b2_9to3_9_ping, b3_9to4_9_ping, b4_9to5_9_ping, b5_9to6_9_ping, b6_9to7_9_ping, b7_9to8_9_ping, b8_9to9_9_ping, b9_9to10_9_ping, b10_9to11_9_ping, b11_9to12_9_ping, b12_9to13_9_ping, b13_9to14_9_ping, b14_9to15_9_ping, b15_9to16_9_ping; +wire [`DWIDTH-1:0] b0_10to1_10_ping, b1_10to2_10_ping, b2_10to3_10_ping, b3_10to4_10_ping, b4_10to5_10_ping, b5_10to6_10_ping, b6_10to7_10_ping, b7_10to8_10_ping, b8_10to9_10_ping, b9_10to10_10_ping, b10_10to11_10_ping, b11_10to12_10_ping, b12_10to13_10_ping, b13_10to14_10_ping, b14_10to15_10_ping, b15_10to16_10_ping; +wire [`DWIDTH-1:0] b0_11to1_11_ping, b1_11to2_11_ping, b2_11to3_11_ping, b3_11to4_11_ping, b4_11to5_11_ping, b5_11to6_11_ping, b6_11to7_11_ping, b7_11to8_11_ping, b8_11to9_11_ping, b9_11to10_11_ping, b10_11to11_11_ping, b11_11to12_11_ping, b12_11to13_11_ping, b13_11to14_11_ping, b14_11to15_11_ping, b15_11to16_11_ping; +wire [`DWIDTH-1:0] b0_12to1_12_ping, b1_12to2_12_ping, b2_12to3_12_ping, b3_12to4_12_ping, b4_12to5_12_ping, b5_12to6_12_ping, b6_12to7_12_ping, b7_12to8_12_ping, b8_12to9_12_ping, b9_12to10_12_ping, b10_12to11_12_ping, b11_12to12_12_ping, b12_12to13_12_ping, b13_12to14_12_ping, b14_12to15_12_ping, b15_12to16_12_ping; +wire [`DWIDTH-1:0] b0_13to1_13_ping, b1_13to2_13_ping, b2_13to3_13_ping, b3_13to4_13_ping, b4_13to5_13_ping, b5_13to6_13_ping, b6_13to7_13_ping, b7_13to8_13_ping, b8_13to9_13_ping, b9_13to10_13_ping, b10_13to11_13_ping, b11_13to12_13_ping, b12_13to13_13_ping, b13_13to14_13_ping, b14_13to15_13_ping, b15_13to16_13_ping; +wire [`DWIDTH-1:0] b0_14to1_14_ping, b1_14to2_14_ping, b2_14to3_14_ping, b3_14to4_14_ping, b4_14to5_14_ping, b5_14to6_14_ping, b6_14to7_14_ping, b7_14to8_14_ping, b8_14to9_14_ping, b9_14to10_14_ping, b10_14to11_14_ping, b11_14to12_14_ping, b12_14to13_14_ping, b13_14to14_14_ping, b14_14to15_14_ping, b15_14to16_14_ping; +wire [`DWIDTH-1:0] b0_15to1_15_ping, b1_15to2_15_ping, b2_15to3_15_ping, b3_15to4_15_ping, b4_15to5_15_ping, b5_15to6_15_ping, b6_15to7_15_ping, b7_15to8_15_ping, b8_15to9_15_ping, b9_15to10_15_ping, b10_15to11_15_ping, b11_15to12_15_ping, b12_15to13_15_ping, b13_15to14_15_ping, b14_15to15_15_ping, b15_15to16_15_ping; + +wire [`DWIDTH-1:0] b0_0to1_0_pong, b1_0to2_0_pong, b2_0to3_0_pong, b3_0to4_0_pong, b4_0to5_0_pong, b5_0to6_0_pong, b6_0to7_0_pong, b7_0to8_0_pong, b8_0to9_0_pong, b9_0to10_0_pong, b10_0to11_0_pong, b11_0to12_0_pong, b12_0to13_0_pong, b13_0to14_0_pong, b14_0to15_0_pong, b15_0to16_0_pong; +wire [`DWIDTH-1:0] b0_1to1_1_pong, b1_1to2_1_pong, b2_1to3_1_pong, b3_1to4_1_pong, b4_1to5_1_pong, b5_1to6_1_pong, b6_1to7_1_pong, b7_1to8_1_pong, b8_1to9_1_pong, b9_1to10_1_pong, b10_1to11_1_pong, b11_1to12_1_pong, b12_1to13_1_pong, b13_1to14_1_pong, b14_1to15_1_pong, b15_1to16_1_pong; +wire [`DWIDTH-1:0] b0_2to1_2_pong, b1_2to2_2_pong, b2_2to3_2_pong, b3_2to4_2_pong, b4_2to5_2_pong, b5_2to6_2_pong, b6_2to7_2_pong, b7_2to8_2_pong, b8_2to9_2_pong, b9_2to10_2_pong, b10_2to11_2_pong, b11_2to12_2_pong, b12_2to13_2_pong, b13_2to14_2_pong, b14_2to15_2_pong, b15_2to16_2_pong; +wire [`DWIDTH-1:0] b0_3to1_3_pong, b1_3to2_3_pong, b2_3to3_3_pong, b3_3to4_3_pong, b4_3to5_3_pong, b5_3to6_3_pong, b6_3to7_3_pong, b7_3to8_3_pong, b8_3to9_3_pong, b9_3to10_3_pong, b10_3to11_3_pong, b11_3to12_3_pong, b12_3to13_3_pong, b13_3to14_3_pong, b14_3to15_3_pong, b15_3to16_3_pong; +wire [`DWIDTH-1:0] b0_4to1_4_pong, b1_4to2_4_pong, b2_4to3_4_pong, b3_4to4_4_pong, b4_4to5_4_pong, b5_4to6_4_pong, b6_4to7_4_pong, b7_4to8_4_pong, b8_4to9_4_pong, b9_4to10_4_pong, b10_4to11_4_pong, b11_4to12_4_pong, b12_4to13_4_pong, b13_4to14_4_pong, b14_4to15_4_pong, b15_4to16_4_pong; +wire [`DWIDTH-1:0] b0_5to1_5_pong, b1_5to2_5_pong, b2_5to3_5_pong, b3_5to4_5_pong, b4_5to5_5_pong, b5_5to6_5_pong, b6_5to7_5_pong, b7_5to8_5_pong, b8_5to9_5_pong, b9_5to10_5_pong, b10_5to11_5_pong, b11_5to12_5_pong, b12_5to13_5_pong, b13_5to14_5_pong, b14_5to15_5_pong, b15_5to16_5_pong; +wire [`DWIDTH-1:0] b0_6to1_6_pong, b1_6to2_6_pong, b2_6to3_6_pong, b3_6to4_6_pong, b4_6to5_6_pong, b5_6to6_6_pong, b6_6to7_6_pong, b7_6to8_6_pong, b8_6to9_6_pong, b9_6to10_6_pong, b10_6to11_6_pong, b11_6to12_6_pong, b12_6to13_6_pong, b13_6to14_6_pong, b14_6to15_6_pong, b15_6to16_6_pong; +wire [`DWIDTH-1:0] b0_7to1_7_pong, b1_7to2_7_pong, b2_7to3_7_pong, b3_7to4_7_pong, b4_7to5_7_pong, b5_7to6_7_pong, b6_7to7_7_pong, b7_7to8_7_pong, b8_7to9_7_pong, b9_7to10_7_pong, b10_7to11_7_pong, b11_7to12_7_pong, b12_7to13_7_pong, b13_7to14_7_pong, b14_7to15_7_pong, b15_7to16_7_pong; +wire [`DWIDTH-1:0] b0_8to1_8_pong, b1_8to2_8_pong, b2_8to3_8_pong, b3_8to4_8_pong, b4_8to5_8_pong, b5_8to6_8_pong, b6_8to7_8_pong, b7_8to8_8_pong, b8_8to9_8_pong, b9_8to10_8_pong, b10_8to11_8_pong, b11_8to12_8_pong, b12_8to13_8_pong, b13_8to14_8_pong, b14_8to15_8_pong, b15_8to16_8_pong; +wire [`DWIDTH-1:0] b0_9to1_9_pong, b1_9to2_9_pong, b2_9to3_9_pong, b3_9to4_9_pong, b4_9to5_9_pong, b5_9to6_9_pong, b6_9to7_9_pong, b7_9to8_9_pong, b8_9to9_9_pong, b9_9to10_9_pong, b10_9to11_9_pong, b11_9to12_9_pong, b12_9to13_9_pong, b13_9to14_9_pong, b14_9to15_9_pong, b15_9to16_9_pong; +wire [`DWIDTH-1:0] b0_10to1_10_pong, b1_10to2_10_pong, b2_10to3_10_pong, b3_10to4_10_pong, b4_10to5_10_pong, b5_10to6_10_pong, b6_10to7_10_pong, b7_10to8_10_pong, b8_10to9_10_pong, b9_10to10_10_pong, b10_10to11_10_pong, b11_10to12_10_pong, b12_10to13_10_pong, b13_10to14_10_pong, b14_10to15_10_pong, b15_10to16_10_pong; +wire [`DWIDTH-1:0] b0_11to1_11_pong, b1_11to2_11_pong, b2_11to3_11_pong, b3_11to4_11_pong, b4_11to5_11_pong, b5_11to6_11_pong, b6_11to7_11_pong, b7_11to8_11_pong, b8_11to9_11_pong, b9_11to10_11_pong, b10_11to11_11_pong, b11_11to12_11_pong, b12_11to13_11_pong, b13_11to14_11_pong, b14_11to15_11_pong, b15_11to16_11_pong; +wire [`DWIDTH-1:0] b0_12to1_12_pong, b1_12to2_12_pong, b2_12to3_12_pong, b3_12to4_12_pong, b4_12to5_12_pong, b5_12to6_12_pong, b6_12to7_12_pong, b7_12to8_12_pong, b8_12to9_12_pong, b9_12to10_12_pong, b10_12to11_12_pong, b11_12to12_12_pong, b12_12to13_12_pong, b13_12to14_12_pong, b14_12to15_12_pong, b15_12to16_12_pong; +wire [`DWIDTH-1:0] b0_13to1_13_pong, b1_13to2_13_pong, b2_13to3_13_pong, b3_13to4_13_pong, b4_13to5_13_pong, b5_13to6_13_pong, b6_13to7_13_pong, b7_13to8_13_pong, b8_13to9_13_pong, b9_13to10_13_pong, b10_13to11_13_pong, b11_13to12_13_pong, b12_13to13_13_pong, b13_13to14_13_pong, b14_13to15_13_pong, b15_13to16_13_pong; +wire [`DWIDTH-1:0] b0_14to1_14_pong, b1_14to2_14_pong, b2_14to3_14_pong, b3_14to4_14_pong, b4_14to5_14_pong, b5_14to6_14_pong, b6_14to7_14_pong, b7_14to8_14_pong, b8_14to9_14_pong, b9_14to10_14_pong, b10_14to11_14_pong, b11_14to12_14_pong, b12_14to13_14_pong, b13_14to14_14_pong, b14_14to15_14_pong, b15_14to16_14_pong; +wire [`DWIDTH-1:0] b0_15to1_15_pong, b1_15to2_15_pong, b2_15to3_15_pong, b3_15to4_15_pong, b4_15to5_15_pong, b5_15to6_15_pong, b6_15to7_15_pong, b7_15to8_15_pong, b8_15to9_15_pong, b9_15to10_15_pong, b10_15to11_15_pong, b11_15to12_15_pong, b12_15to13_15_pong, b13_15to14_15_pong, b14_15to15_15_pong, b15_15to16_15_pong; + +reg [`DWIDTH-1:0] b0_data, b1_data, b2_data, b3_data, b4_data, b5_data, b6_data, b7_data, b8_data, b9_data, b10_data, b11_data, b12_data, b13_data, b14_data, b15_data; + +wire effective_rst; +assign effective_rst = reset | pe_reset; + +reg b_data_sel_delay1; +reg b_data_sel_delay2; +reg b_data_sel_delay3; +reg b_data_sel_delay4; +reg b_data_sel_delay5; +reg b_data_sel_delay6; +reg b_data_sel_delay7; +reg b_data_sel_delay8; +reg b_data_sel_delay9; +reg b_data_sel_delay10; +reg b_data_sel_delay11; +reg b_data_sel_delay12; +reg b_data_sel_delay13; +reg b_data_sel_delay14; +reg b_data_sel_delay15; +reg b_data_sel_delay16; +reg b_data_sel_delay17; +reg b_data_sel_delay18; +reg b_data_sel_delay19; +reg b_data_sel_delay20; +reg b_data_sel_delay21; +reg b_data_sel_delay22; +reg b_data_sel_delay23; +reg b_data_sel_delay24; +reg b_data_sel_delay25; +reg b_data_sel_delay26; +reg b_data_sel_delay27; +reg b_data_sel_delay28; +reg b_data_sel_delay29; +reg b_data_sel_delay30; + +always @ (posedge clk) begin + if (reset) begin + b_data_sel_delay1 <= 0; + b_data_sel_delay2 <= 0; + b_data_sel_delay3 <= 0; + b_data_sel_delay4 <= 0; + b_data_sel_delay5 <= 0; + b_data_sel_delay6 <= 0; + b_data_sel_delay7 <= 0; + b_data_sel_delay8 <= 0; + b_data_sel_delay9 <= 0; + b_data_sel_delay10 <= 0; + b_data_sel_delay11 <= 0; + b_data_sel_delay12 <= 0; + b_data_sel_delay13 <= 0; + b_data_sel_delay14 <= 0; + b_data_sel_delay15 <= 0; + b_data_sel_delay16 <= 0; + b_data_sel_delay17 <= 0; + b_data_sel_delay18 <= 0; + b_data_sel_delay19 <= 0; + b_data_sel_delay20 <= 0; + b_data_sel_delay21 <= 0; + b_data_sel_delay22 <= 0; + b_data_sel_delay23 <= 0; + b_data_sel_delay24 <= 0; + b_data_sel_delay25 <= 0; + b_data_sel_delay26 <= 0; + b_data_sel_delay27 <= 0; + b_data_sel_delay28 <= 0; + b_data_sel_delay29 <= 0; + b_data_sel_delay30 <= 0; + end + else begin + b_data_sel_delay1 <= b_data_sel; + b_data_sel_delay2 <= b_data_sel_delay1; + b_data_sel_delay3 <= b_data_sel_delay2; + b_data_sel_delay4 <= b_data_sel_delay3; + b_data_sel_delay5 <= b_data_sel_delay4; + b_data_sel_delay6 <= b_data_sel_delay5; + b_data_sel_delay7 <= b_data_sel_delay6; + b_data_sel_delay8 <= b_data_sel_delay7; + b_data_sel_delay9 <= b_data_sel_delay8; + b_data_sel_delay10 <= b_data_sel_delay9; + b_data_sel_delay11 <= b_data_sel_delay10; + b_data_sel_delay12 <= b_data_sel_delay11; + b_data_sel_delay13 <= b_data_sel_delay12; + b_data_sel_delay14 <= b_data_sel_delay13; + b_data_sel_delay15 <= b_data_sel_delay14; + b_data_sel_delay16 <= b_data_sel_delay15; + b_data_sel_delay17 <= b_data_sel_delay16; + b_data_sel_delay18 <= b_data_sel_delay17; + b_data_sel_delay19 <= b_data_sel_delay18; + b_data_sel_delay20 <= b_data_sel_delay19; + b_data_sel_delay21 <= b_data_sel_delay20; + b_data_sel_delay22 <= b_data_sel_delay21; + b_data_sel_delay23 <= b_data_sel_delay22; + b_data_sel_delay24 <= b_data_sel_delay23; + b_data_sel_delay25 <= b_data_sel_delay24; + b_data_sel_delay26 <= b_data_sel_delay25; + b_data_sel_delay27 <= b_data_sel_delay26; + b_data_sel_delay28 <= b_data_sel_delay27; + b_data_sel_delay29 <= b_data_sel_delay28; + b_data_sel_delay30 <= b_data_sel_delay29; + end +end + +// Signals for Each PONG buffer + +reg b_data_valid_pong_delay0_1; +reg b_data_valid_pong_delay0_2; +reg b_data_valid_pong_delay0_3; +reg b_data_valid_pong_delay0_4; +reg b_data_valid_pong_delay0_5; +reg b_data_valid_pong_delay0_6; +reg b_data_valid_pong_delay0_7; +reg b_data_valid_pong_delay0_8; +reg b_data_valid_pong_delay0_9; +reg b_data_valid_pong_delay0_10; +reg b_data_valid_pong_delay0_11; +reg b_data_valid_pong_delay0_12; +reg b_data_valid_pong_delay0_13; +reg b_data_valid_pong_delay0_14; +reg b_data_valid_pong_delay0_15; +reg b_data_valid_pong_delay0_16; +reg b_data_valid_pong_delay0_17; +reg b_data_valid_pong_delay0_18; +reg b_data_valid_pong_delay0_19; +reg b_data_valid_pong_delay0_20; +reg b_data_valid_pong_delay0_21; +reg b_data_valid_pong_delay0_22; +reg b_data_valid_pong_delay0_23; +reg b_data_valid_pong_delay0_24; +reg b_data_valid_pong_delay0_25; +reg b_data_valid_pong_delay0_26; +reg b_data_valid_pong_delay0_27; +reg b_data_valid_pong_delay0_28; +reg b_data_valid_pong_delay0_29; +reg b_data_valid_pong_delay0_30; +wire b_data_valid_pong_delay1_0; +wire b_data_valid_pong_delay2_0; +wire b_data_valid_pong_delay3_0; +wire b_data_valid_pong_delay4_0; +wire b_data_valid_pong_delay5_0; +wire b_data_valid_pong_delay6_0; +wire b_data_valid_pong_delay7_0; +wire b_data_valid_pong_delay8_0; +wire b_data_valid_pong_delay9_0; +wire b_data_valid_pong_delay10_0; +wire b_data_valid_pong_delay11_0; +wire b_data_valid_pong_delay12_0; +wire b_data_valid_pong_delay13_0; +wire b_data_valid_pong_delay14_0; +wire b_data_valid_pong_delay15_0; +wire b_data_valid_pong_delay1_1; +wire b_data_valid_pong_delay2_1; +wire b_data_valid_pong_delay3_1; +wire b_data_valid_pong_delay4_1; +wire b_data_valid_pong_delay5_1; +wire b_data_valid_pong_delay6_1; +wire b_data_valid_pong_delay7_1; +wire b_data_valid_pong_delay8_1; +wire b_data_valid_pong_delay9_1; +wire b_data_valid_pong_delay10_1; +wire b_data_valid_pong_delay11_1; +wire b_data_valid_pong_delay12_1; +wire b_data_valid_pong_delay13_1; +wire b_data_valid_pong_delay14_1; +wire b_data_valid_pong_delay15_1; +wire b_data_valid_pong_delay1_2; +wire b_data_valid_pong_delay2_2; +wire b_data_valid_pong_delay3_2; +wire b_data_valid_pong_delay4_2; +wire b_data_valid_pong_delay5_2; +wire b_data_valid_pong_delay6_2; +wire b_data_valid_pong_delay7_2; +wire b_data_valid_pong_delay8_2; +wire b_data_valid_pong_delay9_2; +wire b_data_valid_pong_delay10_2; +wire b_data_valid_pong_delay11_2; +wire b_data_valid_pong_delay12_2; +wire b_data_valid_pong_delay13_2; +wire b_data_valid_pong_delay14_2; +wire b_data_valid_pong_delay15_2; +wire b_data_valid_pong_delay1_3; +wire b_data_valid_pong_delay2_3; +wire b_data_valid_pong_delay3_3; +wire b_data_valid_pong_delay4_3; +wire b_data_valid_pong_delay5_3; +wire b_data_valid_pong_delay6_3; +wire b_data_valid_pong_delay7_3; +wire b_data_valid_pong_delay8_3; +wire b_data_valid_pong_delay9_3; +wire b_data_valid_pong_delay10_3; +wire b_data_valid_pong_delay11_3; +wire b_data_valid_pong_delay12_3; +wire b_data_valid_pong_delay13_3; +wire b_data_valid_pong_delay14_3; +wire b_data_valid_pong_delay15_3; +wire b_data_valid_pong_delay1_4; +wire b_data_valid_pong_delay2_4; +wire b_data_valid_pong_delay3_4; +wire b_data_valid_pong_delay4_4; +wire b_data_valid_pong_delay5_4; +wire b_data_valid_pong_delay6_4; +wire b_data_valid_pong_delay7_4; +wire b_data_valid_pong_delay8_4; +wire b_data_valid_pong_delay9_4; +wire b_data_valid_pong_delay10_4; +wire b_data_valid_pong_delay11_4; +wire b_data_valid_pong_delay12_4; +wire b_data_valid_pong_delay13_4; +wire b_data_valid_pong_delay14_4; +wire b_data_valid_pong_delay15_4; +wire b_data_valid_pong_delay1_5; +wire b_data_valid_pong_delay2_5; +wire b_data_valid_pong_delay3_5; +wire b_data_valid_pong_delay4_5; +wire b_data_valid_pong_delay5_5; +wire b_data_valid_pong_delay6_5; +wire b_data_valid_pong_delay7_5; +wire b_data_valid_pong_delay8_5; +wire b_data_valid_pong_delay9_5; +wire b_data_valid_pong_delay10_5; +wire b_data_valid_pong_delay11_5; +wire b_data_valid_pong_delay12_5; +wire b_data_valid_pong_delay13_5; +wire b_data_valid_pong_delay14_5; +wire b_data_valid_pong_delay15_5; +wire b_data_valid_pong_delay1_6; +wire b_data_valid_pong_delay2_6; +wire b_data_valid_pong_delay3_6; +wire b_data_valid_pong_delay4_6; +wire b_data_valid_pong_delay5_6; +wire b_data_valid_pong_delay6_6; +wire b_data_valid_pong_delay7_6; +wire b_data_valid_pong_delay8_6; +wire b_data_valid_pong_delay9_6; +wire b_data_valid_pong_delay10_6; +wire b_data_valid_pong_delay11_6; +wire b_data_valid_pong_delay12_6; +wire b_data_valid_pong_delay13_6; +wire b_data_valid_pong_delay14_6; +wire b_data_valid_pong_delay15_6; +wire b_data_valid_pong_delay1_7; +wire b_data_valid_pong_delay2_7; +wire b_data_valid_pong_delay3_7; +wire b_data_valid_pong_delay4_7; +wire b_data_valid_pong_delay5_7; +wire b_data_valid_pong_delay6_7; +wire b_data_valid_pong_delay7_7; +wire b_data_valid_pong_delay8_7; +wire b_data_valid_pong_delay9_7; +wire b_data_valid_pong_delay10_7; +wire b_data_valid_pong_delay11_7; +wire b_data_valid_pong_delay12_7; +wire b_data_valid_pong_delay13_7; +wire b_data_valid_pong_delay14_7; +wire b_data_valid_pong_delay15_7; +wire b_data_valid_pong_delay1_8; +wire b_data_valid_pong_delay2_8; +wire b_data_valid_pong_delay3_8; +wire b_data_valid_pong_delay4_8; +wire b_data_valid_pong_delay5_8; +wire b_data_valid_pong_delay6_8; +wire b_data_valid_pong_delay7_8; +wire b_data_valid_pong_delay8_8; +wire b_data_valid_pong_delay9_8; +wire b_data_valid_pong_delay10_8; +wire b_data_valid_pong_delay11_8; +wire b_data_valid_pong_delay12_8; +wire b_data_valid_pong_delay13_8; +wire b_data_valid_pong_delay14_8; +wire b_data_valid_pong_delay15_8; +wire b_data_valid_pong_delay1_9; +wire b_data_valid_pong_delay2_9; +wire b_data_valid_pong_delay3_9; +wire b_data_valid_pong_delay4_9; +wire b_data_valid_pong_delay5_9; +wire b_data_valid_pong_delay6_9; +wire b_data_valid_pong_delay7_9; +wire b_data_valid_pong_delay8_9; +wire b_data_valid_pong_delay9_9; +wire b_data_valid_pong_delay10_9; +wire b_data_valid_pong_delay11_9; +wire b_data_valid_pong_delay12_9; +wire b_data_valid_pong_delay13_9; +wire b_data_valid_pong_delay14_9; +wire b_data_valid_pong_delay15_9; +wire b_data_valid_pong_delay1_10; +wire b_data_valid_pong_delay2_10; +wire b_data_valid_pong_delay3_10; +wire b_data_valid_pong_delay4_10; +wire b_data_valid_pong_delay5_10; +wire b_data_valid_pong_delay6_10; +wire b_data_valid_pong_delay7_10; +wire b_data_valid_pong_delay8_10; +wire b_data_valid_pong_delay9_10; +wire b_data_valid_pong_delay10_10; +wire b_data_valid_pong_delay11_10; +wire b_data_valid_pong_delay12_10; +wire b_data_valid_pong_delay13_10; +wire b_data_valid_pong_delay14_10; +wire b_data_valid_pong_delay15_10; +wire b_data_valid_pong_delay1_11; +wire b_data_valid_pong_delay2_11; +wire b_data_valid_pong_delay3_11; +wire b_data_valid_pong_delay4_11; +wire b_data_valid_pong_delay5_11; +wire b_data_valid_pong_delay6_11; +wire b_data_valid_pong_delay7_11; +wire b_data_valid_pong_delay8_11; +wire b_data_valid_pong_delay9_11; +wire b_data_valid_pong_delay10_11; +wire b_data_valid_pong_delay11_11; +wire b_data_valid_pong_delay12_11; +wire b_data_valid_pong_delay13_11; +wire b_data_valid_pong_delay14_11; +wire b_data_valid_pong_delay15_11; +wire b_data_valid_pong_delay1_12; +wire b_data_valid_pong_delay2_12; +wire b_data_valid_pong_delay3_12; +wire b_data_valid_pong_delay4_12; +wire b_data_valid_pong_delay5_12; +wire b_data_valid_pong_delay6_12; +wire b_data_valid_pong_delay7_12; +wire b_data_valid_pong_delay8_12; +wire b_data_valid_pong_delay9_12; +wire b_data_valid_pong_delay10_12; +wire b_data_valid_pong_delay11_12; +wire b_data_valid_pong_delay12_12; +wire b_data_valid_pong_delay13_12; +wire b_data_valid_pong_delay14_12; +wire b_data_valid_pong_delay15_12; +wire b_data_valid_pong_delay1_13; +wire b_data_valid_pong_delay2_13; +wire b_data_valid_pong_delay3_13; +wire b_data_valid_pong_delay4_13; +wire b_data_valid_pong_delay5_13; +wire b_data_valid_pong_delay6_13; +wire b_data_valid_pong_delay7_13; +wire b_data_valid_pong_delay8_13; +wire b_data_valid_pong_delay9_13; +wire b_data_valid_pong_delay10_13; +wire b_data_valid_pong_delay11_13; +wire b_data_valid_pong_delay12_13; +wire b_data_valid_pong_delay13_13; +wire b_data_valid_pong_delay14_13; +wire b_data_valid_pong_delay15_13; +wire b_data_valid_pong_delay1_14; +wire b_data_valid_pong_delay2_14; +wire b_data_valid_pong_delay3_14; +wire b_data_valid_pong_delay4_14; +wire b_data_valid_pong_delay5_14; +wire b_data_valid_pong_delay6_14; +wire b_data_valid_pong_delay7_14; +wire b_data_valid_pong_delay8_14; +wire b_data_valid_pong_delay9_14; +wire b_data_valid_pong_delay10_14; +wire b_data_valid_pong_delay11_14; +wire b_data_valid_pong_delay12_14; +wire b_data_valid_pong_delay13_14; +wire b_data_valid_pong_delay14_14; +wire b_data_valid_pong_delay15_14; +wire b_data_valid_pong_delay1_15; +wire b_data_valid_pong_delay2_15; +wire b_data_valid_pong_delay3_15; +wire b_data_valid_pong_delay4_15; +wire b_data_valid_pong_delay5_15; +wire b_data_valid_pong_delay6_15; +wire b_data_valid_pong_delay7_15; +wire b_data_valid_pong_delay8_15; +wire b_data_valid_pong_delay9_15; +wire b_data_valid_pong_delay10_15; +wire b_data_valid_pong_delay11_15; +wire b_data_valid_pong_delay12_15; +wire b_data_valid_pong_delay13_15; +wire b_data_valid_pong_delay14_15; +wire b_data_valid_pong_delay15_15; + +always @ (posedge clk) begin + b_data_valid_pong_delay0_1 <= b_data_valid_pong; + b_data_valid_pong_delay0_2 <= b_data_valid_pong_delay0_1; + b_data_valid_pong_delay0_3 <= b_data_valid_pong_delay0_2; + b_data_valid_pong_delay0_4 <= b_data_valid_pong_delay0_3; + b_data_valid_pong_delay0_5 <= b_data_valid_pong_delay0_4; + b_data_valid_pong_delay0_6 <= b_data_valid_pong_delay0_5; + b_data_valid_pong_delay0_7 <= b_data_valid_pong_delay0_6; + b_data_valid_pong_delay0_8 <= b_data_valid_pong_delay0_7; + b_data_valid_pong_delay0_9 <= b_data_valid_pong_delay0_8; + b_data_valid_pong_delay0_10 <= b_data_valid_pong_delay0_9; + b_data_valid_pong_delay0_11 <= b_data_valid_pong_delay0_10; + b_data_valid_pong_delay0_12 <= b_data_valid_pong_delay0_11; + b_data_valid_pong_delay0_13 <= b_data_valid_pong_delay0_12; + b_data_valid_pong_delay0_14 <= b_data_valid_pong_delay0_13; + b_data_valid_pong_delay0_15 <= b_data_valid_pong_delay0_14; + b_data_valid_pong_delay0_16 <= b_data_valid_pong_delay0_15; + b_data_valid_pong_delay0_17 <= b_data_valid_pong_delay0_16; + b_data_valid_pong_delay0_18 <= b_data_valid_pong_delay0_17; + b_data_valid_pong_delay0_19 <= b_data_valid_pong_delay0_18; + b_data_valid_pong_delay0_20 <= b_data_valid_pong_delay0_19; + b_data_valid_pong_delay0_21 <= b_data_valid_pong_delay0_20; + b_data_valid_pong_delay0_22 <= b_data_valid_pong_delay0_21; + b_data_valid_pong_delay0_23 <= b_data_valid_pong_delay0_22; + b_data_valid_pong_delay0_24 <= b_data_valid_pong_delay0_23; + b_data_valid_pong_delay0_25 <= b_data_valid_pong_delay0_24; + b_data_valid_pong_delay0_26 <= b_data_valid_pong_delay0_25; + b_data_valid_pong_delay0_27 <= b_data_valid_pong_delay0_26; + b_data_valid_pong_delay0_28 <= b_data_valid_pong_delay0_27; + b_data_valid_pong_delay0_29 <= b_data_valid_pong_delay0_28; + b_data_valid_pong_delay0_30 <= b_data_valid_pong_delay0_29; +end + +assign b_data_valid_pong_delay1_0 = b_data_valid_pong & b_data_valid_pong_delay0_1; +assign b_data_valid_pong_delay2_0 = b_data_valid_pong & b_data_valid_pong_delay0_2; +assign b_data_valid_pong_delay3_0 = b_data_valid_pong & b_data_valid_pong_delay0_3; +assign b_data_valid_pong_delay4_0 = b_data_valid_pong & b_data_valid_pong_delay0_4; +assign b_data_valid_pong_delay5_0 = b_data_valid_pong & b_data_valid_pong_delay0_5; +assign b_data_valid_pong_delay6_0 = b_data_valid_pong & b_data_valid_pong_delay0_6; +assign b_data_valid_pong_delay7_0 = b_data_valid_pong & b_data_valid_pong_delay0_7; +assign b_data_valid_pong_delay8_0 = b_data_valid_pong & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay9_0 = b_data_valid_pong & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay10_0 = b_data_valid_pong & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay11_0 = b_data_valid_pong & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay12_0 = b_data_valid_pong & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay13_0 = b_data_valid_pong & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay14_0 = b_data_valid_pong & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay15_0 = b_data_valid_pong & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay1_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_2; +assign b_data_valid_pong_delay2_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_3; +assign b_data_valid_pong_delay3_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_4; +assign b_data_valid_pong_delay4_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_5; +assign b_data_valid_pong_delay5_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_6; +assign b_data_valid_pong_delay6_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_7; +assign b_data_valid_pong_delay7_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay8_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay9_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay10_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay11_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay12_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay13_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay14_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay15_1 = b_data_valid_pong_delay0_1 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay1_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_3; +assign b_data_valid_pong_delay2_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_4; +assign b_data_valid_pong_delay3_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_5; +assign b_data_valid_pong_delay4_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_6; +assign b_data_valid_pong_delay5_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_7; +assign b_data_valid_pong_delay6_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay7_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay8_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay9_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay10_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay11_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay12_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay13_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay14_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay15_2 = b_data_valid_pong_delay0_2 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay1_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_4; +assign b_data_valid_pong_delay2_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_5; +assign b_data_valid_pong_delay3_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_6; +assign b_data_valid_pong_delay4_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_7; +assign b_data_valid_pong_delay5_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay6_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay7_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay8_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay9_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay10_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay11_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay12_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay13_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay14_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay15_3 = b_data_valid_pong_delay0_3 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay1_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_5; +assign b_data_valid_pong_delay2_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_6; +assign b_data_valid_pong_delay3_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_7; +assign b_data_valid_pong_delay4_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay5_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay6_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay7_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay8_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay9_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay10_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay11_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay12_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay13_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay14_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay15_4 = b_data_valid_pong_delay0_4 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay1_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_6; +assign b_data_valid_pong_delay2_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_7; +assign b_data_valid_pong_delay3_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay4_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay5_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay6_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay7_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay8_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay9_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay10_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay11_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay12_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay13_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay14_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay15_5 = b_data_valid_pong_delay0_5 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay1_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_7; +assign b_data_valid_pong_delay2_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay3_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay4_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay5_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay6_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay7_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay8_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay9_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay10_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay11_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay12_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay13_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay14_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay15_6 = b_data_valid_pong_delay0_6 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay1_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_8; +assign b_data_valid_pong_delay2_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay3_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay4_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay5_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay6_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay7_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay8_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay9_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay10_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay11_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay12_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay13_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay14_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay15_7 = b_data_valid_pong_delay0_7 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay1_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_9; +assign b_data_valid_pong_delay2_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay3_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay4_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay5_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay6_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay7_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay8_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay9_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay10_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay11_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay12_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay13_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay14_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay15_8 = b_data_valid_pong_delay0_8 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay1_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_10; +assign b_data_valid_pong_delay2_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay3_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay4_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay5_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay6_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay7_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay8_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay9_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay10_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay11_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay12_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay13_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay14_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay15_9 = b_data_valid_pong_delay0_9 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay1_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_11; +assign b_data_valid_pong_delay2_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay3_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay4_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay5_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay6_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay7_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay8_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay9_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay10_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay11_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay12_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay13_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay14_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay15_10 = b_data_valid_pong_delay0_10 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay1_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_12; +assign b_data_valid_pong_delay2_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay3_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay4_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay5_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay6_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay7_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay8_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay9_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay10_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay11_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay12_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay13_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay14_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay15_11 = b_data_valid_pong_delay0_11 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay1_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_13; +assign b_data_valid_pong_delay2_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay3_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay4_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay5_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay6_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay7_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay8_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay9_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay10_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay11_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay12_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay13_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay14_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay15_12 = b_data_valid_pong_delay0_12 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay1_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_14; +assign b_data_valid_pong_delay2_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay3_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay4_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay5_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay6_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay7_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay8_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay9_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay10_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay11_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay12_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay13_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay14_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay15_13 = b_data_valid_pong_delay0_13 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay1_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_15; +assign b_data_valid_pong_delay2_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay3_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay4_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay5_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay6_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay7_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay8_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay9_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay10_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay11_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay12_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay13_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay14_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay15_14 = b_data_valid_pong_delay0_14 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay1_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_16; +assign b_data_valid_pong_delay2_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_17; +assign b_data_valid_pong_delay3_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_18; +assign b_data_valid_pong_delay4_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_19; +assign b_data_valid_pong_delay5_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_20; +assign b_data_valid_pong_delay6_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_21; +assign b_data_valid_pong_delay7_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_22; +assign b_data_valid_pong_delay8_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_23; +assign b_data_valid_pong_delay9_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_24; +assign b_data_valid_pong_delay10_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_25; +assign b_data_valid_pong_delay11_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_26; +assign b_data_valid_pong_delay12_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_27; +assign b_data_valid_pong_delay13_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_28; +assign b_data_valid_pong_delay14_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_29; +assign b_data_valid_pong_delay15_15 = b_data_valid_pong_delay0_15 & b_data_valid_pong_delay0_30; + +// Signals for Each PING buffer + +reg b_data_valid_ping_delay0_1; +reg b_data_valid_ping_delay0_2; +reg b_data_valid_ping_delay0_3; +reg b_data_valid_ping_delay0_4; +reg b_data_valid_ping_delay0_5; +reg b_data_valid_ping_delay0_6; +reg b_data_valid_ping_delay0_7; +reg b_data_valid_ping_delay0_8; +reg b_data_valid_ping_delay0_9; +reg b_data_valid_ping_delay0_10; +reg b_data_valid_ping_delay0_11; +reg b_data_valid_ping_delay0_12; +reg b_data_valid_ping_delay0_13; +reg b_data_valid_ping_delay0_14; +reg b_data_valid_ping_delay0_15; +reg b_data_valid_ping_delay0_16; +reg b_data_valid_ping_delay0_17; +reg b_data_valid_ping_delay0_18; +reg b_data_valid_ping_delay0_19; +reg b_data_valid_ping_delay0_20; +reg b_data_valid_ping_delay0_21; +reg b_data_valid_ping_delay0_22; +reg b_data_valid_ping_delay0_23; +reg b_data_valid_ping_delay0_24; +reg b_data_valid_ping_delay0_25; +reg b_data_valid_ping_delay0_26; +reg b_data_valid_ping_delay0_27; +reg b_data_valid_ping_delay0_28; +reg b_data_valid_ping_delay0_29; +reg b_data_valid_ping_delay0_30; +wire b_data_valid_ping_delay1_0; +wire b_data_valid_ping_delay2_0; +wire b_data_valid_ping_delay3_0; +wire b_data_valid_ping_delay4_0; +wire b_data_valid_ping_delay5_0; +wire b_data_valid_ping_delay6_0; +wire b_data_valid_ping_delay7_0; +wire b_data_valid_ping_delay8_0; +wire b_data_valid_ping_delay9_0; +wire b_data_valid_ping_delay10_0; +wire b_data_valid_ping_delay11_0; +wire b_data_valid_ping_delay12_0; +wire b_data_valid_ping_delay13_0; +wire b_data_valid_ping_delay14_0; +wire b_data_valid_ping_delay15_0; +wire b_data_valid_ping_delay1_1; +wire b_data_valid_ping_delay2_1; +wire b_data_valid_ping_delay3_1; +wire b_data_valid_ping_delay4_1; +wire b_data_valid_ping_delay5_1; +wire b_data_valid_ping_delay6_1; +wire b_data_valid_ping_delay7_1; +wire b_data_valid_ping_delay8_1; +wire b_data_valid_ping_delay9_1; +wire b_data_valid_ping_delay10_1; +wire b_data_valid_ping_delay11_1; +wire b_data_valid_ping_delay12_1; +wire b_data_valid_ping_delay13_1; +wire b_data_valid_ping_delay14_1; +wire b_data_valid_ping_delay15_1; +wire b_data_valid_ping_delay1_2; +wire b_data_valid_ping_delay2_2; +wire b_data_valid_ping_delay3_2; +wire b_data_valid_ping_delay4_2; +wire b_data_valid_ping_delay5_2; +wire b_data_valid_ping_delay6_2; +wire b_data_valid_ping_delay7_2; +wire b_data_valid_ping_delay8_2; +wire b_data_valid_ping_delay9_2; +wire b_data_valid_ping_delay10_2; +wire b_data_valid_ping_delay11_2; +wire b_data_valid_ping_delay12_2; +wire b_data_valid_ping_delay13_2; +wire b_data_valid_ping_delay14_2; +wire b_data_valid_ping_delay15_2; +wire b_data_valid_ping_delay1_3; +wire b_data_valid_ping_delay2_3; +wire b_data_valid_ping_delay3_3; +wire b_data_valid_ping_delay4_3; +wire b_data_valid_ping_delay5_3; +wire b_data_valid_ping_delay6_3; +wire b_data_valid_ping_delay7_3; +wire b_data_valid_ping_delay8_3; +wire b_data_valid_ping_delay9_3; +wire b_data_valid_ping_delay10_3; +wire b_data_valid_ping_delay11_3; +wire b_data_valid_ping_delay12_3; +wire b_data_valid_ping_delay13_3; +wire b_data_valid_ping_delay14_3; +wire b_data_valid_ping_delay15_3; +wire b_data_valid_ping_delay1_4; +wire b_data_valid_ping_delay2_4; +wire b_data_valid_ping_delay3_4; +wire b_data_valid_ping_delay4_4; +wire b_data_valid_ping_delay5_4; +wire b_data_valid_ping_delay6_4; +wire b_data_valid_ping_delay7_4; +wire b_data_valid_ping_delay8_4; +wire b_data_valid_ping_delay9_4; +wire b_data_valid_ping_delay10_4; +wire b_data_valid_ping_delay11_4; +wire b_data_valid_ping_delay12_4; +wire b_data_valid_ping_delay13_4; +wire b_data_valid_ping_delay14_4; +wire b_data_valid_ping_delay15_4; +wire b_data_valid_ping_delay1_5; +wire b_data_valid_ping_delay2_5; +wire b_data_valid_ping_delay3_5; +wire b_data_valid_ping_delay4_5; +wire b_data_valid_ping_delay5_5; +wire b_data_valid_ping_delay6_5; +wire b_data_valid_ping_delay7_5; +wire b_data_valid_ping_delay8_5; +wire b_data_valid_ping_delay9_5; +wire b_data_valid_ping_delay10_5; +wire b_data_valid_ping_delay11_5; +wire b_data_valid_ping_delay12_5; +wire b_data_valid_ping_delay13_5; +wire b_data_valid_ping_delay14_5; +wire b_data_valid_ping_delay15_5; +wire b_data_valid_ping_delay1_6; +wire b_data_valid_ping_delay2_6; +wire b_data_valid_ping_delay3_6; +wire b_data_valid_ping_delay4_6; +wire b_data_valid_ping_delay5_6; +wire b_data_valid_ping_delay6_6; +wire b_data_valid_ping_delay7_6; +wire b_data_valid_ping_delay8_6; +wire b_data_valid_ping_delay9_6; +wire b_data_valid_ping_delay10_6; +wire b_data_valid_ping_delay11_6; +wire b_data_valid_ping_delay12_6; +wire b_data_valid_ping_delay13_6; +wire b_data_valid_ping_delay14_6; +wire b_data_valid_ping_delay15_6; +wire b_data_valid_ping_delay1_7; +wire b_data_valid_ping_delay2_7; +wire b_data_valid_ping_delay3_7; +wire b_data_valid_ping_delay4_7; +wire b_data_valid_ping_delay5_7; +wire b_data_valid_ping_delay6_7; +wire b_data_valid_ping_delay7_7; +wire b_data_valid_ping_delay8_7; +wire b_data_valid_ping_delay9_7; +wire b_data_valid_ping_delay10_7; +wire b_data_valid_ping_delay11_7; +wire b_data_valid_ping_delay12_7; +wire b_data_valid_ping_delay13_7; +wire b_data_valid_ping_delay14_7; +wire b_data_valid_ping_delay15_7; +wire b_data_valid_ping_delay1_8; +wire b_data_valid_ping_delay2_8; +wire b_data_valid_ping_delay3_8; +wire b_data_valid_ping_delay4_8; +wire b_data_valid_ping_delay5_8; +wire b_data_valid_ping_delay6_8; +wire b_data_valid_ping_delay7_8; +wire b_data_valid_ping_delay8_8; +wire b_data_valid_ping_delay9_8; +wire b_data_valid_ping_delay10_8; +wire b_data_valid_ping_delay11_8; +wire b_data_valid_ping_delay12_8; +wire b_data_valid_ping_delay13_8; +wire b_data_valid_ping_delay14_8; +wire b_data_valid_ping_delay15_8; +wire b_data_valid_ping_delay1_9; +wire b_data_valid_ping_delay2_9; +wire b_data_valid_ping_delay3_9; +wire b_data_valid_ping_delay4_9; +wire b_data_valid_ping_delay5_9; +wire b_data_valid_ping_delay6_9; +wire b_data_valid_ping_delay7_9; +wire b_data_valid_ping_delay8_9; +wire b_data_valid_ping_delay9_9; +wire b_data_valid_ping_delay10_9; +wire b_data_valid_ping_delay11_9; +wire b_data_valid_ping_delay12_9; +wire b_data_valid_ping_delay13_9; +wire b_data_valid_ping_delay14_9; +wire b_data_valid_ping_delay15_9; +wire b_data_valid_ping_delay1_10; +wire b_data_valid_ping_delay2_10; +wire b_data_valid_ping_delay3_10; +wire b_data_valid_ping_delay4_10; +wire b_data_valid_ping_delay5_10; +wire b_data_valid_ping_delay6_10; +wire b_data_valid_ping_delay7_10; +wire b_data_valid_ping_delay8_10; +wire b_data_valid_ping_delay9_10; +wire b_data_valid_ping_delay10_10; +wire b_data_valid_ping_delay11_10; +wire b_data_valid_ping_delay12_10; +wire b_data_valid_ping_delay13_10; +wire b_data_valid_ping_delay14_10; +wire b_data_valid_ping_delay15_10; +wire b_data_valid_ping_delay1_11; +wire b_data_valid_ping_delay2_11; +wire b_data_valid_ping_delay3_11; +wire b_data_valid_ping_delay4_11; +wire b_data_valid_ping_delay5_11; +wire b_data_valid_ping_delay6_11; +wire b_data_valid_ping_delay7_11; +wire b_data_valid_ping_delay8_11; +wire b_data_valid_ping_delay9_11; +wire b_data_valid_ping_delay10_11; +wire b_data_valid_ping_delay11_11; +wire b_data_valid_ping_delay12_11; +wire b_data_valid_ping_delay13_11; +wire b_data_valid_ping_delay14_11; +wire b_data_valid_ping_delay15_11; +wire b_data_valid_ping_delay1_12; +wire b_data_valid_ping_delay2_12; +wire b_data_valid_ping_delay3_12; +wire b_data_valid_ping_delay4_12; +wire b_data_valid_ping_delay5_12; +wire b_data_valid_ping_delay6_12; +wire b_data_valid_ping_delay7_12; +wire b_data_valid_ping_delay8_12; +wire b_data_valid_ping_delay9_12; +wire b_data_valid_ping_delay10_12; +wire b_data_valid_ping_delay11_12; +wire b_data_valid_ping_delay12_12; +wire b_data_valid_ping_delay13_12; +wire b_data_valid_ping_delay14_12; +wire b_data_valid_ping_delay15_12; +wire b_data_valid_ping_delay1_13; +wire b_data_valid_ping_delay2_13; +wire b_data_valid_ping_delay3_13; +wire b_data_valid_ping_delay4_13; +wire b_data_valid_ping_delay5_13; +wire b_data_valid_ping_delay6_13; +wire b_data_valid_ping_delay7_13; +wire b_data_valid_ping_delay8_13; +wire b_data_valid_ping_delay9_13; +wire b_data_valid_ping_delay10_13; +wire b_data_valid_ping_delay11_13; +wire b_data_valid_ping_delay12_13; +wire b_data_valid_ping_delay13_13; +wire b_data_valid_ping_delay14_13; +wire b_data_valid_ping_delay15_13; +wire b_data_valid_ping_delay1_14; +wire b_data_valid_ping_delay2_14; +wire b_data_valid_ping_delay3_14; +wire b_data_valid_ping_delay4_14; +wire b_data_valid_ping_delay5_14; +wire b_data_valid_ping_delay6_14; +wire b_data_valid_ping_delay7_14; +wire b_data_valid_ping_delay8_14; +wire b_data_valid_ping_delay9_14; +wire b_data_valid_ping_delay10_14; +wire b_data_valid_ping_delay11_14; +wire b_data_valid_ping_delay12_14; +wire b_data_valid_ping_delay13_14; +wire b_data_valid_ping_delay14_14; +wire b_data_valid_ping_delay15_14; +wire b_data_valid_ping_delay1_15; +wire b_data_valid_ping_delay2_15; +wire b_data_valid_ping_delay3_15; +wire b_data_valid_ping_delay4_15; +wire b_data_valid_ping_delay5_15; +wire b_data_valid_ping_delay6_15; +wire b_data_valid_ping_delay7_15; +wire b_data_valid_ping_delay8_15; +wire b_data_valid_ping_delay9_15; +wire b_data_valid_ping_delay10_15; +wire b_data_valid_ping_delay11_15; +wire b_data_valid_ping_delay12_15; +wire b_data_valid_ping_delay13_15; +wire b_data_valid_ping_delay14_15; +wire b_data_valid_ping_delay15_15; + +always @ (posedge clk) begin + b_data_valid_ping_delay0_1 <= b_data_valid_ping; + b_data_valid_ping_delay0_2 <= b_data_valid_ping_delay0_1; + b_data_valid_ping_delay0_3 <= b_data_valid_ping_delay0_2; + b_data_valid_ping_delay0_4 <= b_data_valid_ping_delay0_3; + b_data_valid_ping_delay0_5 <= b_data_valid_ping_delay0_4; + b_data_valid_ping_delay0_6 <= b_data_valid_ping_delay0_5; + b_data_valid_ping_delay0_7 <= b_data_valid_ping_delay0_6; + b_data_valid_ping_delay0_8 <= b_data_valid_ping_delay0_7; + b_data_valid_ping_delay0_9 <= b_data_valid_ping_delay0_8; + b_data_valid_ping_delay0_10 <= b_data_valid_ping_delay0_9; + b_data_valid_ping_delay0_11 <= b_data_valid_ping_delay0_10; + b_data_valid_ping_delay0_12 <= b_data_valid_ping_delay0_11; + b_data_valid_ping_delay0_13 <= b_data_valid_ping_delay0_12; + b_data_valid_ping_delay0_14 <= b_data_valid_ping_delay0_13; + b_data_valid_ping_delay0_15 <= b_data_valid_ping_delay0_14; + b_data_valid_ping_delay0_16 <= b_data_valid_ping_delay0_15; + b_data_valid_ping_delay0_17 <= b_data_valid_ping_delay0_16; + b_data_valid_ping_delay0_18 <= b_data_valid_ping_delay0_17; + b_data_valid_ping_delay0_19 <= b_data_valid_ping_delay0_18; + b_data_valid_ping_delay0_20 <= b_data_valid_ping_delay0_19; + b_data_valid_ping_delay0_21 <= b_data_valid_ping_delay0_20; + b_data_valid_ping_delay0_22 <= b_data_valid_ping_delay0_21; + b_data_valid_ping_delay0_23 <= b_data_valid_ping_delay0_22; + b_data_valid_ping_delay0_24 <= b_data_valid_ping_delay0_23; + b_data_valid_ping_delay0_25 <= b_data_valid_ping_delay0_24; + b_data_valid_ping_delay0_26 <= b_data_valid_ping_delay0_25; + b_data_valid_ping_delay0_27 <= b_data_valid_ping_delay0_26; + b_data_valid_ping_delay0_28 <= b_data_valid_ping_delay0_27; + b_data_valid_ping_delay0_29 <= b_data_valid_ping_delay0_28; + b_data_valid_ping_delay0_30 <= b_data_valid_ping_delay0_29; +end + +assign b_data_valid_ping_delay1_0 = b_data_valid_ping & b_data_valid_ping_delay0_1; +assign b_data_valid_ping_delay2_0 = b_data_valid_ping & b_data_valid_ping_delay0_2; +assign b_data_valid_ping_delay3_0 = b_data_valid_ping & b_data_valid_ping_delay0_3; +assign b_data_valid_ping_delay4_0 = b_data_valid_ping & b_data_valid_ping_delay0_4; +assign b_data_valid_ping_delay5_0 = b_data_valid_ping & b_data_valid_ping_delay0_5; +assign b_data_valid_ping_delay6_0 = b_data_valid_ping & b_data_valid_ping_delay0_6; +assign b_data_valid_ping_delay7_0 = b_data_valid_ping & b_data_valid_ping_delay0_7; +assign b_data_valid_ping_delay8_0 = b_data_valid_ping & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay9_0 = b_data_valid_ping & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay10_0 = b_data_valid_ping & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay11_0 = b_data_valid_ping & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay12_0 = b_data_valid_ping & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay13_0 = b_data_valid_ping & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay14_0 = b_data_valid_ping & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay15_0 = b_data_valid_ping & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay1_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_2; +assign b_data_valid_ping_delay2_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_3; +assign b_data_valid_ping_delay3_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_4; +assign b_data_valid_ping_delay4_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_5; +assign b_data_valid_ping_delay5_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_6; +assign b_data_valid_ping_delay6_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_7; +assign b_data_valid_ping_delay7_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay8_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay9_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay10_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay11_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay12_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay13_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay14_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay15_1 = b_data_valid_ping_delay0_1 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay1_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_3; +assign b_data_valid_ping_delay2_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_4; +assign b_data_valid_ping_delay3_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_5; +assign b_data_valid_ping_delay4_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_6; +assign b_data_valid_ping_delay5_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_7; +assign b_data_valid_ping_delay6_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay7_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay8_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay9_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay10_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay11_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay12_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay13_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay14_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay15_2 = b_data_valid_ping_delay0_2 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay1_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_4; +assign b_data_valid_ping_delay2_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_5; +assign b_data_valid_ping_delay3_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_6; +assign b_data_valid_ping_delay4_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_7; +assign b_data_valid_ping_delay5_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay6_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay7_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay8_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay9_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay10_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay11_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay12_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay13_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay14_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay15_3 = b_data_valid_ping_delay0_3 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay1_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_5; +assign b_data_valid_ping_delay2_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_6; +assign b_data_valid_ping_delay3_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_7; +assign b_data_valid_ping_delay4_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay5_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay6_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay7_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay8_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay9_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay10_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay11_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay12_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay13_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay14_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay15_4 = b_data_valid_ping_delay0_4 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay1_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_6; +assign b_data_valid_ping_delay2_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_7; +assign b_data_valid_ping_delay3_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay4_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay5_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay6_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay7_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay8_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay9_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay10_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay11_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay12_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay13_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay14_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay15_5 = b_data_valid_ping_delay0_5 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay1_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_7; +assign b_data_valid_ping_delay2_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay3_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay4_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay5_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay6_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay7_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay8_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay9_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay10_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay11_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay12_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay13_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay14_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay15_6 = b_data_valid_ping_delay0_6 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay1_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_8; +assign b_data_valid_ping_delay2_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay3_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay4_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay5_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay6_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay7_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay8_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay9_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay10_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay11_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay12_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay13_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay14_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay15_7 = b_data_valid_ping_delay0_7 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay1_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_9; +assign b_data_valid_ping_delay2_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay3_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay4_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay5_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay6_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay7_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay8_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay9_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay10_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay11_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay12_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay13_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay14_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay15_8 = b_data_valid_ping_delay0_8 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay1_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_10; +assign b_data_valid_ping_delay2_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay3_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay4_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay5_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay6_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay7_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay8_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay9_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay10_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay11_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay12_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay13_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay14_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay15_9 = b_data_valid_ping_delay0_9 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay1_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_11; +assign b_data_valid_ping_delay2_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay3_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay4_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay5_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay6_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay7_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay8_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay9_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay10_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay11_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay12_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay13_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay14_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay15_10 = b_data_valid_ping_delay0_10 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay1_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_12; +assign b_data_valid_ping_delay2_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay3_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay4_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay5_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay6_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay7_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay8_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay9_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay10_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay11_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay12_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay13_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay14_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay15_11 = b_data_valid_ping_delay0_11 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay1_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_13; +assign b_data_valid_ping_delay2_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay3_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay4_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay5_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay6_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay7_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay8_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay9_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay10_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay11_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay12_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay13_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay14_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay15_12 = b_data_valid_ping_delay0_12 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay1_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_14; +assign b_data_valid_ping_delay2_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay3_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay4_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay5_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay6_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay7_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay8_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay9_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay10_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay11_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay12_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay13_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay14_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay15_13 = b_data_valid_ping_delay0_13 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay1_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_15; +assign b_data_valid_ping_delay2_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay3_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay4_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay5_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay6_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay7_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay8_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay9_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay10_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay11_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay12_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay13_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay14_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay15_14 = b_data_valid_ping_delay0_14 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay1_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_16; +assign b_data_valid_ping_delay2_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_17; +assign b_data_valid_ping_delay3_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_18; +assign b_data_valid_ping_delay4_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_19; +assign b_data_valid_ping_delay5_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_20; +assign b_data_valid_ping_delay6_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_21; +assign b_data_valid_ping_delay7_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_22; +assign b_data_valid_ping_delay8_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_23; +assign b_data_valid_ping_delay9_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_24; +assign b_data_valid_ping_delay10_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_25; +assign b_data_valid_ping_delay11_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_26; +assign b_data_valid_ping_delay12_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_27; +assign b_data_valid_ping_delay13_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_28; +assign b_data_valid_ping_delay14_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_29; +assign b_data_valid_ping_delay15_15 = b_data_valid_ping_delay0_15 & b_data_valid_ping_delay0_30; + +wire [`DWIDTH-1:0] in_a_0_0_NC, in_a_0_1_NC, in_a_0_2_NC, in_a_0_3_NC, in_a_0_4_NC, in_a_0_5_NC, in_a_0_6_NC, in_a_0_7_NC, in_a_0_8_NC, in_a_0_9_NC, in_a_0_10_NC, in_a_0_11_NC, in_a_0_12_NC, in_a_0_13_NC, in_a_0_14_NC, in_a_0_15_NC, in_a_1_0_NC, in_a_1_1_NC, in_a_1_2_NC, in_a_1_3_NC, in_a_1_4_NC, in_a_1_5_NC, in_a_1_6_NC, in_a_1_7_NC, in_a_1_8_NC, in_a_1_9_NC, in_a_1_10_NC, in_a_1_11_NC, in_a_1_12_NC, in_a_1_13_NC, in_a_1_14_NC, in_a_1_15_NC, in_a_2_0_NC, in_a_2_1_NC, in_a_2_2_NC, in_a_2_3_NC, in_a_2_4_NC, in_a_2_5_NC, in_a_2_6_NC, in_a_2_7_NC, in_a_2_8_NC, in_a_2_9_NC, in_a_2_10_NC, in_a_2_11_NC, in_a_2_12_NC, in_a_2_13_NC, in_a_2_14_NC, in_a_2_15_NC, in_a_3_0_NC, in_a_3_1_NC, in_a_3_2_NC, in_a_3_3_NC, in_a_3_4_NC, in_a_3_5_NC, in_a_3_6_NC, in_a_3_7_NC, in_a_3_8_NC, in_a_3_9_NC, in_a_3_10_NC, in_a_3_11_NC, in_a_3_12_NC, in_a_3_13_NC, in_a_3_14_NC, in_a_3_15_NC, in_a_4_0_NC, in_a_4_1_NC, in_a_4_2_NC, in_a_4_3_NC, in_a_4_4_NC, in_a_4_5_NC, in_a_4_6_NC, in_a_4_7_NC, in_a_4_8_NC, in_a_4_9_NC, in_a_4_10_NC, in_a_4_11_NC, in_a_4_12_NC, in_a_4_13_NC, in_a_4_14_NC, in_a_4_15_NC, in_a_5_0_NC, in_a_5_1_NC, in_a_5_2_NC, in_a_5_3_NC, in_a_5_4_NC, in_a_5_5_NC, in_a_5_6_NC, in_a_5_7_NC, in_a_5_8_NC, in_a_5_9_NC, in_a_5_10_NC, in_a_5_11_NC, in_a_5_12_NC, in_a_5_13_NC, in_a_5_14_NC, in_a_5_15_NC, in_a_6_0_NC, in_a_6_1_NC, in_a_6_2_NC, in_a_6_3_NC, in_a_6_4_NC, in_a_6_5_NC, in_a_6_6_NC, in_a_6_7_NC, in_a_6_8_NC, in_a_6_9_NC, in_a_6_10_NC, in_a_6_11_NC, in_a_6_12_NC, in_a_6_13_NC, in_a_6_14_NC, in_a_6_15_NC, in_a_7_0_NC, in_a_7_1_NC, in_a_7_2_NC, in_a_7_3_NC, in_a_7_4_NC, in_a_7_5_NC, in_a_7_6_NC, in_a_7_7_NC, in_a_7_8_NC, in_a_7_9_NC, in_a_7_10_NC, in_a_7_11_NC, in_a_7_12_NC, in_a_7_13_NC, in_a_7_14_NC, in_a_7_15_NC, in_a_8_0_NC, in_a_8_1_NC, in_a_8_2_NC, in_a_8_3_NC, in_a_8_4_NC, in_a_8_5_NC, in_a_8_6_NC, in_a_8_7_NC, in_a_8_8_NC, in_a_8_9_NC, in_a_8_10_NC, in_a_8_11_NC, in_a_8_12_NC, in_a_8_13_NC, in_a_8_14_NC, in_a_8_15_NC, in_a_9_0_NC, in_a_9_1_NC, in_a_9_2_NC, in_a_9_3_NC, in_a_9_4_NC, in_a_9_5_NC, in_a_9_6_NC, in_a_9_7_NC, in_a_9_8_NC, in_a_9_9_NC, in_a_9_10_NC, in_a_9_11_NC, in_a_9_12_NC, in_a_9_13_NC, in_a_9_14_NC, in_a_9_15_NC, in_a_10_0_NC, in_a_10_1_NC, in_a_10_2_NC, in_a_10_3_NC, in_a_10_4_NC, in_a_10_5_NC, in_a_10_6_NC, in_a_10_7_NC, in_a_10_8_NC, in_a_10_9_NC, in_a_10_10_NC, in_a_10_11_NC, in_a_10_12_NC, in_a_10_13_NC, in_a_10_14_NC, in_a_10_15_NC, in_a_11_0_NC, in_a_11_1_NC, in_a_11_2_NC, in_a_11_3_NC, in_a_11_4_NC, in_a_11_5_NC, in_a_11_6_NC, in_a_11_7_NC, in_a_11_8_NC, in_a_11_9_NC, in_a_11_10_NC, in_a_11_11_NC, in_a_11_12_NC, in_a_11_13_NC, in_a_11_14_NC, in_a_11_15_NC, in_a_12_0_NC, in_a_12_1_NC, in_a_12_2_NC, in_a_12_3_NC, in_a_12_4_NC, in_a_12_5_NC, in_a_12_6_NC, in_a_12_7_NC, in_a_12_8_NC, in_a_12_9_NC, in_a_12_10_NC, in_a_12_11_NC, in_a_12_12_NC, in_a_12_13_NC, in_a_12_14_NC, in_a_12_15_NC, in_a_13_0_NC, in_a_13_1_NC, in_a_13_2_NC, in_a_13_3_NC, in_a_13_4_NC, in_a_13_5_NC, in_a_13_6_NC, in_a_13_7_NC, in_a_13_8_NC, in_a_13_9_NC, in_a_13_10_NC, in_a_13_11_NC, in_a_13_12_NC, in_a_13_13_NC, in_a_13_14_NC, in_a_13_15_NC, in_a_14_0_NC, in_a_14_1_NC, in_a_14_2_NC, in_a_14_3_NC, in_a_14_4_NC, in_a_14_5_NC, in_a_14_6_NC, in_a_14_7_NC, in_a_14_8_NC, in_a_14_9_NC, in_a_14_10_NC, in_a_14_11_NC, in_a_14_12_NC, in_a_14_13_NC, in_a_14_14_NC, in_a_14_15_NC, in_a_15_0_NC, in_a_15_1_NC, in_a_15_2_NC, in_a_15_3_NC, in_a_15_4_NC, in_a_15_5_NC, in_a_15_6_NC, in_a_15_7_NC, in_a_15_8_NC, in_a_15_9_NC, in_a_15_10_NC, in_a_15_11_NC, in_a_15_12_NC, in_a_15_13_NC, in_a_15_14_NC, in_a_15_15_NC; + +wire [`DWIDTH-1:0] in_a_chain_0_0_NC, in_a_chain_0_1_NC, in_a_chain_0_2_NC, in_a_chain_0_3_NC, in_a_chain_0_4_NC, in_a_chain_0_5_NC, in_a_chain_0_6_NC, in_a_chain_0_7_NC, in_a_chain_0_8_NC, in_a_chain_0_9_NC, in_a_chain_0_10_NC, in_a_chain_0_11_NC, in_a_chain_0_12_NC, in_a_chain_0_13_NC, in_a_chain_0_14_NC, in_a_chain_0_15_NC, in_a_chain_1_0_NC, in_a_chain_1_1_NC, in_a_chain_1_2_NC, in_a_chain_1_3_NC, in_a_chain_1_4_NC, in_a_chain_1_5_NC, in_a_chain_1_6_NC, in_a_chain_1_7_NC, in_a_chain_1_8_NC, in_a_chain_1_9_NC, in_a_chain_1_10_NC, in_a_chain_1_11_NC, in_a_chain_1_12_NC, in_a_chain_1_13_NC, in_a_chain_1_14_NC, in_a_chain_1_15_NC, in_a_chain_2_0_NC, in_a_chain_2_1_NC, in_a_chain_2_2_NC, in_a_chain_2_3_NC, in_a_chain_2_4_NC, in_a_chain_2_5_NC, in_a_chain_2_6_NC, in_a_chain_2_7_NC, in_a_chain_2_8_NC, in_a_chain_2_9_NC, in_a_chain_2_10_NC, in_a_chain_2_11_NC, in_a_chain_2_12_NC, in_a_chain_2_13_NC, in_a_chain_2_14_NC, in_a_chain_2_15_NC, in_a_chain_3_0_NC, in_a_chain_3_1_NC, in_a_chain_3_2_NC, in_a_chain_3_3_NC, in_a_chain_3_4_NC, in_a_chain_3_5_NC, in_a_chain_3_6_NC, in_a_chain_3_7_NC, in_a_chain_3_8_NC, in_a_chain_3_9_NC, in_a_chain_3_10_NC, in_a_chain_3_11_NC, in_a_chain_3_12_NC, in_a_chain_3_13_NC, in_a_chain_3_14_NC, in_a_chain_3_15_NC, in_a_chain_4_0_NC, in_a_chain_4_1_NC, in_a_chain_4_2_NC, in_a_chain_4_3_NC, in_a_chain_4_4_NC, in_a_chain_4_5_NC, in_a_chain_4_6_NC, in_a_chain_4_7_NC, in_a_chain_4_8_NC, in_a_chain_4_9_NC, in_a_chain_4_10_NC, in_a_chain_4_11_NC, in_a_chain_4_12_NC, in_a_chain_4_13_NC, in_a_chain_4_14_NC, in_a_chain_4_15_NC, in_a_chain_5_0_NC, in_a_chain_5_1_NC, in_a_chain_5_2_NC, in_a_chain_5_3_NC, in_a_chain_5_4_NC, in_a_chain_5_5_NC, in_a_chain_5_6_NC, in_a_chain_5_7_NC, in_a_chain_5_8_NC, in_a_chain_5_9_NC, in_a_chain_5_10_NC, in_a_chain_5_11_NC, in_a_chain_5_12_NC, in_a_chain_5_13_NC, in_a_chain_5_14_NC, in_a_chain_5_15_NC, in_a_chain_6_0_NC, in_a_chain_6_1_NC, in_a_chain_6_2_NC, in_a_chain_6_3_NC, in_a_chain_6_4_NC, in_a_chain_6_5_NC, in_a_chain_6_6_NC, in_a_chain_6_7_NC, in_a_chain_6_8_NC, in_a_chain_6_9_NC, in_a_chain_6_10_NC, in_a_chain_6_11_NC, in_a_chain_6_12_NC, in_a_chain_6_13_NC, in_a_chain_6_14_NC, in_a_chain_6_15_NC, in_a_chain_7_0_NC, in_a_chain_7_1_NC, in_a_chain_7_2_NC, in_a_chain_7_3_NC, in_a_chain_7_4_NC, in_a_chain_7_5_NC, in_a_chain_7_6_NC, in_a_chain_7_7_NC, in_a_chain_7_8_NC, in_a_chain_7_9_NC, in_a_chain_7_10_NC, in_a_chain_7_11_NC, in_a_chain_7_12_NC, in_a_chain_7_13_NC, in_a_chain_7_14_NC, in_a_chain_7_15_NC, in_a_chain_8_0_NC, in_a_chain_8_1_NC, in_a_chain_8_2_NC, in_a_chain_8_3_NC, in_a_chain_8_4_NC, in_a_chain_8_5_NC, in_a_chain_8_6_NC, in_a_chain_8_7_NC, in_a_chain_8_8_NC, in_a_chain_8_9_NC, in_a_chain_8_10_NC, in_a_chain_8_11_NC, in_a_chain_8_12_NC, in_a_chain_8_13_NC, in_a_chain_8_14_NC, in_a_chain_8_15_NC, in_a_chain_9_0_NC, in_a_chain_9_1_NC, in_a_chain_9_2_NC, in_a_chain_9_3_NC, in_a_chain_9_4_NC, in_a_chain_9_5_NC, in_a_chain_9_6_NC, in_a_chain_9_7_NC, in_a_chain_9_8_NC, in_a_chain_9_9_NC, in_a_chain_9_10_NC, in_a_chain_9_11_NC, in_a_chain_9_12_NC, in_a_chain_9_13_NC, in_a_chain_9_14_NC, in_a_chain_9_15_NC, in_a_chain_10_0_NC, in_a_chain_10_1_NC, in_a_chain_10_2_NC, in_a_chain_10_3_NC, in_a_chain_10_4_NC, in_a_chain_10_5_NC, in_a_chain_10_6_NC, in_a_chain_10_7_NC, in_a_chain_10_8_NC, in_a_chain_10_9_NC, in_a_chain_10_10_NC, in_a_chain_10_11_NC, in_a_chain_10_12_NC, in_a_chain_10_13_NC, in_a_chain_10_14_NC, in_a_chain_10_15_NC, in_a_chain_11_0_NC, in_a_chain_11_1_NC, in_a_chain_11_2_NC, in_a_chain_11_3_NC, in_a_chain_11_4_NC, in_a_chain_11_5_NC, in_a_chain_11_6_NC, in_a_chain_11_7_NC, in_a_chain_11_8_NC, in_a_chain_11_9_NC, in_a_chain_11_10_NC, in_a_chain_11_11_NC, in_a_chain_11_12_NC, in_a_chain_11_13_NC, in_a_chain_11_14_NC, in_a_chain_11_15_NC, in_a_chain_12_0_NC, in_a_chain_12_1_NC, in_a_chain_12_2_NC, in_a_chain_12_3_NC, in_a_chain_12_4_NC, in_a_chain_12_5_NC, in_a_chain_12_6_NC, in_a_chain_12_7_NC, in_a_chain_12_8_NC, in_a_chain_12_9_NC, in_a_chain_12_10_NC, in_a_chain_12_11_NC, in_a_chain_12_12_NC, in_a_chain_12_13_NC, in_a_chain_12_14_NC, in_a_chain_12_15_NC, in_a_chain_13_0_NC, in_a_chain_13_1_NC, in_a_chain_13_2_NC, in_a_chain_13_3_NC, in_a_chain_13_4_NC, in_a_chain_13_5_NC, in_a_chain_13_6_NC, in_a_chain_13_7_NC, in_a_chain_13_8_NC, in_a_chain_13_9_NC, in_a_chain_13_10_NC, in_a_chain_13_11_NC, in_a_chain_13_12_NC, in_a_chain_13_13_NC, in_a_chain_13_14_NC, in_a_chain_13_15_NC, in_a_chain_14_0_NC, in_a_chain_14_1_NC, in_a_chain_14_2_NC, in_a_chain_14_3_NC, in_a_chain_14_4_NC, in_a_chain_14_5_NC, in_a_chain_14_6_NC, in_a_chain_14_7_NC, in_a_chain_14_8_NC, in_a_chain_14_9_NC, in_a_chain_14_10_NC, in_a_chain_14_11_NC, in_a_chain_14_12_NC, in_a_chain_14_13_NC, in_a_chain_14_14_NC, in_a_chain_14_15_NC, in_a_chain_15_0_NC, in_a_chain_15_1_NC, in_a_chain_15_2_NC, in_a_chain_15_3_NC, in_a_chain_15_4_NC, in_a_chain_15_5_NC, in_a_chain_15_6_NC, in_a_chain_15_7_NC, in_a_chain_15_8_NC, in_a_chain_15_9_NC, in_a_chain_15_10_NC, in_a_chain_15_11_NC, in_a_chain_15_12_NC, in_a_chain_15_13_NC, in_a_chain_15_14_NC, in_a_chain_15_15_NC; + +wire [`DWIDTH-1:0] out_a_0_0_NC, out_a_0_1_NC, out_a_0_2_NC, out_a_0_3_NC, out_a_0_4_NC, out_a_0_5_NC, out_a_0_6_NC, out_a_0_7_NC, out_a_0_8_NC, out_a_0_9_NC, out_a_0_10_NC, out_a_0_11_NC, out_a_0_12_NC, out_a_0_13_NC, out_a_0_14_NC, out_a_0_15_NC, out_a_1_0_NC, out_a_1_1_NC, out_a_1_2_NC, out_a_1_3_NC, out_a_1_4_NC, out_a_1_5_NC, out_a_1_6_NC, out_a_1_7_NC, out_a_1_8_NC, out_a_1_9_NC, out_a_1_10_NC, out_a_1_11_NC, out_a_1_12_NC, out_a_1_13_NC, out_a_1_14_NC, out_a_1_15_NC, out_a_2_0_NC, out_a_2_1_NC, out_a_2_2_NC, out_a_2_3_NC, out_a_2_4_NC, out_a_2_5_NC, out_a_2_6_NC, out_a_2_7_NC, out_a_2_8_NC, out_a_2_9_NC, out_a_2_10_NC, out_a_2_11_NC, out_a_2_12_NC, out_a_2_13_NC, out_a_2_14_NC, out_a_2_15_NC, out_a_3_0_NC, out_a_3_1_NC, out_a_3_2_NC, out_a_3_3_NC, out_a_3_4_NC, out_a_3_5_NC, out_a_3_6_NC, out_a_3_7_NC, out_a_3_8_NC, out_a_3_9_NC, out_a_3_10_NC, out_a_3_11_NC, out_a_3_12_NC, out_a_3_13_NC, out_a_3_14_NC, out_a_3_15_NC, out_a_4_0_NC, out_a_4_1_NC, out_a_4_2_NC, out_a_4_3_NC, out_a_4_4_NC, out_a_4_5_NC, out_a_4_6_NC, out_a_4_7_NC, out_a_4_8_NC, out_a_4_9_NC, out_a_4_10_NC, out_a_4_11_NC, out_a_4_12_NC, out_a_4_13_NC, out_a_4_14_NC, out_a_4_15_NC, out_a_5_0_NC, out_a_5_1_NC, out_a_5_2_NC, out_a_5_3_NC, out_a_5_4_NC, out_a_5_5_NC, out_a_5_6_NC, out_a_5_7_NC, out_a_5_8_NC, out_a_5_9_NC, out_a_5_10_NC, out_a_5_11_NC, out_a_5_12_NC, out_a_5_13_NC, out_a_5_14_NC, out_a_5_15_NC, out_a_6_0_NC, out_a_6_1_NC, out_a_6_2_NC, out_a_6_3_NC, out_a_6_4_NC, out_a_6_5_NC, out_a_6_6_NC, out_a_6_7_NC, out_a_6_8_NC, out_a_6_9_NC, out_a_6_10_NC, out_a_6_11_NC, out_a_6_12_NC, out_a_6_13_NC, out_a_6_14_NC, out_a_6_15_NC, out_a_7_0_NC, out_a_7_1_NC, out_a_7_2_NC, out_a_7_3_NC, out_a_7_4_NC, out_a_7_5_NC, out_a_7_6_NC, out_a_7_7_NC, out_a_7_8_NC, out_a_7_9_NC, out_a_7_10_NC, out_a_7_11_NC, out_a_7_12_NC, out_a_7_13_NC, out_a_7_14_NC, out_a_7_15_NC, out_a_8_0_NC, out_a_8_1_NC, out_a_8_2_NC, out_a_8_3_NC, out_a_8_4_NC, out_a_8_5_NC, out_a_8_6_NC, out_a_8_7_NC, out_a_8_8_NC, out_a_8_9_NC, out_a_8_10_NC, out_a_8_11_NC, out_a_8_12_NC, out_a_8_13_NC, out_a_8_14_NC, out_a_8_15_NC, out_a_9_0_NC, out_a_9_1_NC, out_a_9_2_NC, out_a_9_3_NC, out_a_9_4_NC, out_a_9_5_NC, out_a_9_6_NC, out_a_9_7_NC, out_a_9_8_NC, out_a_9_9_NC, out_a_9_10_NC, out_a_9_11_NC, out_a_9_12_NC, out_a_9_13_NC, out_a_9_14_NC, out_a_9_15_NC, out_a_10_0_NC, out_a_10_1_NC, out_a_10_2_NC, out_a_10_3_NC, out_a_10_4_NC, out_a_10_5_NC, out_a_10_6_NC, out_a_10_7_NC, out_a_10_8_NC, out_a_10_9_NC, out_a_10_10_NC, out_a_10_11_NC, out_a_10_12_NC, out_a_10_13_NC, out_a_10_14_NC, out_a_10_15_NC, out_a_11_0_NC, out_a_11_1_NC, out_a_11_2_NC, out_a_11_3_NC, out_a_11_4_NC, out_a_11_5_NC, out_a_11_6_NC, out_a_11_7_NC, out_a_11_8_NC, out_a_11_9_NC, out_a_11_10_NC, out_a_11_11_NC, out_a_11_12_NC, out_a_11_13_NC, out_a_11_14_NC, out_a_11_15_NC, out_a_12_0_NC, out_a_12_1_NC, out_a_12_2_NC, out_a_12_3_NC, out_a_12_4_NC, out_a_12_5_NC, out_a_12_6_NC, out_a_12_7_NC, out_a_12_8_NC, out_a_12_9_NC, out_a_12_10_NC, out_a_12_11_NC, out_a_12_12_NC, out_a_12_13_NC, out_a_12_14_NC, out_a_12_15_NC, out_a_13_0_NC, out_a_13_1_NC, out_a_13_2_NC, out_a_13_3_NC, out_a_13_4_NC, out_a_13_5_NC, out_a_13_6_NC, out_a_13_7_NC, out_a_13_8_NC, out_a_13_9_NC, out_a_13_10_NC, out_a_13_11_NC, out_a_13_12_NC, out_a_13_13_NC, out_a_13_14_NC, out_a_13_15_NC, out_a_14_0_NC, out_a_14_1_NC, out_a_14_2_NC, out_a_14_3_NC, out_a_14_4_NC, out_a_14_5_NC, out_a_14_6_NC, out_a_14_7_NC, out_a_14_8_NC, out_a_14_9_NC, out_a_14_10_NC, out_a_14_11_NC, out_a_14_12_NC, out_a_14_13_NC, out_a_14_14_NC, out_a_14_15_NC, out_a_15_0_NC, out_a_15_1_NC, out_a_15_2_NC, out_a_15_3_NC, out_a_15_4_NC, out_a_15_5_NC, out_a_15_6_NC, out_a_15_7_NC, out_a_15_8_NC, out_a_15_9_NC, out_a_15_10_NC, out_a_15_11_NC, out_a_15_12_NC, out_a_15_13_NC, out_a_15_14_NC, out_a_15_15_NC; + +processing_element pe0_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel), .in_a(a0), .in_a_chain(in_a_chain_0_0_NC), .in_b(b0), .in_c(c0), .out_a(out_a_0_0_NC), .out_a_chain(a0_0to0_1), .out_b(b0_0to1_0), .out_b0(b0_0to1_0_ping), .out_b1(b0_0to1_0_pong), .out_c(matrixC0_0), .b_data_valid_ping(b_data_valid_ping), .b_data_valid_pong(b_data_valid_pong ), .mode(1'b1)); +processing_element pe0_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay1), .in_a(in_a_0_1_NC), .in_a_chain(a0_0to0_1), .in_b(b1), .in_c(c1), .out_a(out_a_0_1_NC), .out_a_chain(a0_1to0_2), .out_b(b0_1to1_1), .out_b0(b0_1to1_1_ping), .out_b1(b0_1to1_1_pong), .out_c(matrixC0_1), .b_data_valid_ping(b_data_valid_ping_delay0_1), .b_data_valid_pong(b_data_valid_pong_delay0_1), .mode(1'b0)); +processing_element pe0_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay2), .in_a(in_a_0_2_NC), .in_a_chain(a0_1to0_2), .in_b(b2), .in_c(c2), .out_a(out_a_0_2_NC), .out_a_chain(a0_2to0_3), .out_b(b0_2to1_2), .out_b0(b0_2to1_2_ping), .out_b1(b0_2to1_2_pong), .out_c(matrixC0_2), .b_data_valid_ping(b_data_valid_ping_delay0_2), .b_data_valid_pong(b_data_valid_pong_delay0_2), .mode(1'b0)); +processing_element pe0_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay3), .in_a(in_a_0_3_NC), .in_a_chain(a0_2to0_3), .in_b(b3), .in_c(c3), .out_a(out_a_0_3_NC), .out_a_chain(a0_3to0_4), .out_b(b0_3to1_3), .out_b0(b0_3to1_3_ping), .out_b1(b0_3to1_3_pong), .out_c(matrixC0_3), .b_data_valid_ping(b_data_valid_ping_delay0_3), .b_data_valid_pong(b_data_valid_pong_delay0_3), .mode(1'b0)); +processing_element pe0_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay4), .in_a(in_a_0_4_NC), .in_a_chain(a0_3to0_4), .in_b(b4), .in_c(c4), .out_a(out_a_0_4_NC), .out_a_chain(a0_4to0_5), .out_b(b0_4to1_4), .out_b0(b0_4to1_4_ping), .out_b1(b0_4to1_4_pong), .out_c(matrixC0_4), .b_data_valid_ping(b_data_valid_ping_delay0_4), .b_data_valid_pong(b_data_valid_pong_delay0_4), .mode(1'b0)); +processing_element pe0_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay5), .in_a(in_a_0_5_NC), .in_a_chain(a0_4to0_5), .in_b(b5), .in_c(c5), .out_a(out_a_0_5_NC), .out_a_chain(a0_5to0_6), .out_b(b0_5to1_5), .out_b0(b0_5to1_5_ping), .out_b1(b0_5to1_5_pong), .out_c(matrixC0_5), .b_data_valid_ping(b_data_valid_ping_delay0_5), .b_data_valid_pong(b_data_valid_pong_delay0_5), .mode(1'b0)); +processing_element pe0_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay6), .in_a(in_a_0_6_NC), .in_a_chain(a0_5to0_6), .in_b(b6), .in_c(c6), .out_a(out_a_0_6_NC), .out_a_chain(a0_6to0_7), .out_b(b0_6to1_6), .out_b0(b0_6to1_6_ping), .out_b1(b0_6to1_6_pong), .out_c(matrixC0_6), .b_data_valid_ping(b_data_valid_ping_delay0_6), .b_data_valid_pong(b_data_valid_pong_delay0_6), .mode(1'b0)); +processing_element pe0_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(in_a_0_7_NC), .in_a_chain(a0_6to0_7), .in_b(b7), .in_c(c7), .out_a(out_a_0_7_NC), .out_a_chain(a0_7to0_8), .out_b(b0_7to1_7), .out_b0(b0_7to1_7_ping), .out_b1(b0_7to1_7_pong), .out_c(matrixC0_7), .b_data_valid_ping(b_data_valid_ping_delay0_7), .b_data_valid_pong(b_data_valid_pong_delay0_7), .mode(1'b0)); +processing_element pe0_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_0_8_NC), .in_a_chain(a0_7to0_8), .in_b(b8), .in_c(c8), .out_a(out_a_0_8_NC), .out_a_chain(a0_8to0_9), .out_b(b0_8to1_8), .out_b0(b0_8to1_8_ping), .out_b1(b0_8to1_8_pong), .out_c(matrixC0_8), .b_data_valid_ping(b_data_valid_ping_delay0_8), .b_data_valid_pong(b_data_valid_pong_delay0_8), .mode(1'b0)); +processing_element pe0_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_0_9_NC), .in_a_chain(a0_8to0_9), .in_b(b9), .in_c(c9), .out_a(out_a_0_9_NC), .out_a_chain(a0_9to0_10), .out_b(b0_9to1_9), .out_b0(b0_9to1_9_ping), .out_b1(b0_9to1_9_pong), .out_c(matrixC0_9), .b_data_valid_ping(b_data_valid_ping_delay0_9), .b_data_valid_pong(b_data_valid_pong_delay0_9), .mode(1'b0)); +processing_element pe0_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_0_10_NC), .in_a_chain(a0_9to0_10), .in_b(b10), .in_c(c10), .out_a(out_a_0_10_NC), .out_a_chain(a0_10to0_11), .out_b(b0_10to1_10), .out_b0(b0_10to1_10_ping), .out_b1(b0_10to1_10_pong), .out_c(matrixC0_10), .b_data_valid_ping(b_data_valid_ping_delay0_10), .b_data_valid_pong(b_data_valid_pong_delay0_10), .mode(1'b0)); +processing_element pe0_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_0_11_NC), .in_a_chain(a0_10to0_11), .in_b(b11), .in_c(c11), .out_a(out_a_0_11_NC), .out_a_chain(a0_11to0_12), .out_b(b0_11to1_11), .out_b0(b0_11to1_11_ping), .out_b1(b0_11to1_11_pong), .out_c(matrixC0_11), .b_data_valid_ping(b_data_valid_ping_delay0_11), .b_data_valid_pong(b_data_valid_pong_delay0_11), .mode(1'b0)); +processing_element pe0_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_0_12_NC), .in_a_chain(a0_11to0_12), .in_b(b12), .in_c(c12), .out_a(out_a_0_12_NC), .out_a_chain(a0_12to0_13), .out_b(b0_12to1_12), .out_b0(b0_12to1_12_ping), .out_b1(b0_12to1_12_pong), .out_c(matrixC0_12), .b_data_valid_ping(b_data_valid_ping_delay0_12), .b_data_valid_pong(b_data_valid_pong_delay0_12), .mode(1'b0)); +processing_element pe0_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_0_13_NC), .in_a_chain(a0_12to0_13), .in_b(b13), .in_c(c13), .out_a(out_a_0_13_NC), .out_a_chain(a0_13to0_14), .out_b(b0_13to1_13), .out_b0(b0_13to1_13_ping), .out_b1(b0_13to1_13_pong), .out_c(matrixC0_13), .b_data_valid_ping(b_data_valid_ping_delay0_13), .b_data_valid_pong(b_data_valid_pong_delay0_13), .mode(1'b0)); +processing_element pe0_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_0_14_NC), .in_a_chain(a0_13to0_14), .in_b(b14), .in_c(c14), .out_a(out_a_0_14_NC), .out_a_chain(a0_14to0_15), .out_b(b0_14to1_14), .out_b0(b0_14to1_14_ping), .out_b1(b0_14to1_14_pong), .out_c(matrixC0_14), .b_data_valid_ping(b_data_valid_ping_delay0_14), .b_data_valid_pong(b_data_valid_pong_delay0_14), .mode(1'b0)); +processing_element pe0_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_0_15_NC), .in_a_chain(a0_14to0_15), .in_b(b15), .in_c(c15), .out_a(out_a_0_15_NC), .out_a_chain(a0_15to0_16), .out_b(b0_15to1_15), .out_b0(b0_15to1_15_ping), .out_b1(b0_15to1_15_pong), .out_c(matrixC0_15), .b_data_valid_ping(b_data_valid_ping_delay0_15), .b_data_valid_pong(b_data_valid_pong_delay0_15), .mode(1'b0)); +processing_element pe1_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay1), .in_a(a1), .in_a_chain(in_a_chain_1_0_NC), .in_b(b0_0to1_0), .in_c(matrixC0_0), .out_a(out_a_1_0_NC), .out_a_chain(a1_0to1_1), .out_b(b1_0to2_0), .out_b0(b1_0to2_0_ping), .out_b1(b1_0to2_0_pong), .out_c(matrixC1_0), .b_data_valid_ping(b_data_valid_ping_delay1_0), .b_data_valid_pong(b_data_valid_pong_delay1_0), .mode(1'b1)); +processing_element pe1_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay2), .in_a(in_a_1_1_NC), .in_a_chain(a1_0to1_1), .in_b(b0_1to1_1), .in_c(matrixC0_1), .out_a(out_a_1_1_NC), .out_a_chain(a1_1to1_2), .out_b(b1_1to2_1), .out_b0(b1_1to2_1_ping), .out_b1(b1_1to2_1_pong), .out_c(matrixC1_1), .b_data_valid_ping(b_data_valid_ping_delay1_1), .b_data_valid_pong(b_data_valid_pong_delay1_1), .mode(1'b0)); +processing_element pe1_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay3), .in_a(in_a_1_2_NC), .in_a_chain(a1_1to1_2), .in_b(b0_2to1_2), .in_c(matrixC0_2), .out_a(out_a_1_2_NC), .out_a_chain(a1_2to1_3), .out_b(b1_2to2_2), .out_b0(b1_2to2_2_ping), .out_b1(b1_2to2_2_pong), .out_c(matrixC1_2), .b_data_valid_ping(b_data_valid_ping_delay1_2), .b_data_valid_pong(b_data_valid_pong_delay1_2), .mode(1'b0)); +processing_element pe1_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay4), .in_a(in_a_1_3_NC), .in_a_chain(a1_2to1_3), .in_b(b0_3to1_3), .in_c(matrixC0_3), .out_a(out_a_1_3_NC), .out_a_chain(a1_3to1_4), .out_b(b1_3to2_3), .out_b0(b1_3to2_3_ping), .out_b1(b1_3to2_3_pong), .out_c(matrixC1_3), .b_data_valid_ping(b_data_valid_ping_delay1_3), .b_data_valid_pong(b_data_valid_pong_delay1_3), .mode(1'b0)); +processing_element pe1_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay5), .in_a(in_a_1_4_NC), .in_a_chain(a1_3to1_4), .in_b(b0_4to1_4), .in_c(matrixC0_4), .out_a(out_a_1_4_NC), .out_a_chain(a1_4to1_5), .out_b(b1_4to2_4), .out_b0(b1_4to2_4_ping), .out_b1(b1_4to2_4_pong), .out_c(matrixC1_4), .b_data_valid_ping(b_data_valid_ping_delay1_4), .b_data_valid_pong(b_data_valid_pong_delay1_4), .mode(1'b0)); +processing_element pe1_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay6), .in_a(in_a_1_5_NC), .in_a_chain(a1_4to1_5), .in_b(b0_5to1_5), .in_c(matrixC0_5), .out_a(out_a_1_5_NC), .out_a_chain(a1_5to1_6), .out_b(b1_5to2_5), .out_b0(b1_5to2_5_ping), .out_b1(b1_5to2_5_pong), .out_c(matrixC1_5), .b_data_valid_ping(b_data_valid_ping_delay1_5), .b_data_valid_pong(b_data_valid_pong_delay1_5), .mode(1'b0)); +processing_element pe1_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(in_a_1_6_NC), .in_a_chain(a1_5to1_6), .in_b(b0_6to1_6), .in_c(matrixC0_6), .out_a(out_a_1_6_NC), .out_a_chain(a1_6to1_7), .out_b(b1_6to2_6), .out_b0(b1_6to2_6_ping), .out_b1(b1_6to2_6_pong), .out_c(matrixC1_6), .b_data_valid_ping(b_data_valid_ping_delay1_6), .b_data_valid_pong(b_data_valid_pong_delay1_6), .mode(1'b0)); +processing_element pe1_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_1_7_NC), .in_a_chain(a1_6to1_7), .in_b(b0_7to1_7), .in_c(matrixC0_7), .out_a(out_a_1_7_NC), .out_a_chain(a1_7to1_8), .out_b(b1_7to2_7), .out_b0(b1_7to2_7_ping), .out_b1(b1_7to2_7_pong), .out_c(matrixC1_7), .b_data_valid_ping(b_data_valid_ping_delay1_7), .b_data_valid_pong(b_data_valid_pong_delay1_7), .mode(1'b0)); +processing_element pe1_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_1_8_NC), .in_a_chain(a1_7to1_8), .in_b(b0_8to1_8), .in_c(matrixC0_8), .out_a(out_a_1_8_NC), .out_a_chain(a1_8to1_9), .out_b(b1_8to2_8), .out_b0(b1_8to2_8_ping), .out_b1(b1_8to2_8_pong), .out_c(matrixC1_8), .b_data_valid_ping(b_data_valid_ping_delay1_8), .b_data_valid_pong(b_data_valid_pong_delay1_8), .mode(1'b0)); +processing_element pe1_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_1_9_NC), .in_a_chain(a1_8to1_9), .in_b(b0_9to1_9), .in_c(matrixC0_9), .out_a(out_a_1_9_NC), .out_a_chain(a1_9to1_10), .out_b(b1_9to2_9), .out_b0(b1_9to2_9_ping), .out_b1(b1_9to2_9_pong), .out_c(matrixC1_9), .b_data_valid_ping(b_data_valid_ping_delay1_9), .b_data_valid_pong(b_data_valid_pong_delay1_9), .mode(1'b0)); +processing_element pe1_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_1_10_NC), .in_a_chain(a1_9to1_10), .in_b(b0_10to1_10), .in_c(matrixC0_10), .out_a(out_a_1_10_NC), .out_a_chain(a1_10to1_11), .out_b(b1_10to2_10), .out_b0(b1_10to2_10_ping), .out_b1(b1_10to2_10_pong), .out_c(matrixC1_10), .b_data_valid_ping(b_data_valid_ping_delay1_10), .b_data_valid_pong(b_data_valid_pong_delay1_10), .mode(1'b0)); +processing_element pe1_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_1_11_NC), .in_a_chain(a1_10to1_11), .in_b(b0_11to1_11), .in_c(matrixC0_11), .out_a(out_a_1_11_NC), .out_a_chain(a1_11to1_12), .out_b(b1_11to2_11), .out_b0(b1_11to2_11_ping), .out_b1(b1_11to2_11_pong), .out_c(matrixC1_11), .b_data_valid_ping(b_data_valid_ping_delay1_11), .b_data_valid_pong(b_data_valid_pong_delay1_11), .mode(1'b0)); +processing_element pe1_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_1_12_NC), .in_a_chain(a1_11to1_12), .in_b(b0_12to1_12), .in_c(matrixC0_12), .out_a(out_a_1_12_NC), .out_a_chain(a1_12to1_13), .out_b(b1_12to2_12), .out_b0(b1_12to2_12_ping), .out_b1(b1_12to2_12_pong), .out_c(matrixC1_12), .b_data_valid_ping(b_data_valid_ping_delay1_12), .b_data_valid_pong(b_data_valid_pong_delay1_12), .mode(1'b0)); +processing_element pe1_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_1_13_NC), .in_a_chain(a1_12to1_13), .in_b(b0_13to1_13), .in_c(matrixC0_13), .out_a(out_a_1_13_NC), .out_a_chain(a1_13to1_14), .out_b(b1_13to2_13), .out_b0(b1_13to2_13_ping), .out_b1(b1_13to2_13_pong), .out_c(matrixC1_13), .b_data_valid_ping(b_data_valid_ping_delay1_13), .b_data_valid_pong(b_data_valid_pong_delay1_13), .mode(1'b0)); +processing_element pe1_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_1_14_NC), .in_a_chain(a1_13to1_14), .in_b(b0_14to1_14), .in_c(matrixC0_14), .out_a(out_a_1_14_NC), .out_a_chain(a1_14to1_15), .out_b(b1_14to2_14), .out_b0(b1_14to2_14_ping), .out_b1(b1_14to2_14_pong), .out_c(matrixC1_14), .b_data_valid_ping(b_data_valid_ping_delay1_14), .b_data_valid_pong(b_data_valid_pong_delay1_14), .mode(1'b0)); +processing_element pe1_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_1_15_NC), .in_a_chain(a1_14to1_15), .in_b(b0_15to1_15), .in_c(matrixC0_15), .out_a(out_a_1_15_NC), .out_a_chain(a1_15to1_16), .out_b(b1_15to2_15), .out_b0(b1_15to2_15_ping), .out_b1(b1_15to2_15_pong), .out_c(matrixC1_15), .b_data_valid_ping(b_data_valid_ping_delay1_15), .b_data_valid_pong(b_data_valid_pong_delay1_15), .mode(1'b0)); +processing_element pe2_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay2), .in_a(a2), .in_a_chain(in_a_chain_2_0_NC), .in_b(b1_0to2_0), .in_c(matrixC1_0), .out_a(out_a_2_0_NC), .out_a_chain(a2_0to2_1), .out_b(b2_0to3_0), .out_b0(b2_0to3_0_ping), .out_b1(b2_0to3_0_pong), .out_c(matrixC2_0), .b_data_valid_ping(b_data_valid_ping_delay2_0), .b_data_valid_pong(b_data_valid_pong_delay2_0), .mode(1'b1)); +processing_element pe2_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay3), .in_a(in_a_2_1_NC), .in_a_chain(a2_0to2_1), .in_b(b1_1to2_1), .in_c(matrixC1_1), .out_a(out_a_2_1_NC), .out_a_chain(a2_1to2_2), .out_b(b2_1to3_1), .out_b0(b2_1to3_1_ping), .out_b1(b2_1to3_1_pong), .out_c(matrixC2_1), .b_data_valid_ping(b_data_valid_ping_delay2_1), .b_data_valid_pong(b_data_valid_pong_delay2_1), .mode(1'b0)); +processing_element pe2_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay4), .in_a(in_a_2_2_NC), .in_a_chain(a2_1to2_2), .in_b(b1_2to2_2), .in_c(matrixC1_2), .out_a(out_a_2_2_NC), .out_a_chain(a2_2to2_3), .out_b(b2_2to3_2), .out_b0(b2_2to3_2_ping), .out_b1(b2_2to3_2_pong), .out_c(matrixC2_2), .b_data_valid_ping(b_data_valid_ping_delay2_2), .b_data_valid_pong(b_data_valid_pong_delay2_2), .mode(1'b0)); +processing_element pe2_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay5), .in_a(in_a_2_3_NC), .in_a_chain(a2_2to2_3), .in_b(b1_3to2_3), .in_c(matrixC1_3), .out_a(out_a_2_3_NC), .out_a_chain(a2_3to2_4), .out_b(b2_3to3_3), .out_b0(b2_3to3_3_ping), .out_b1(b2_3to3_3_pong), .out_c(matrixC2_3), .b_data_valid_ping(b_data_valid_ping_delay2_3), .b_data_valid_pong(b_data_valid_pong_delay2_3), .mode(1'b0)); +processing_element pe2_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay6), .in_a(in_a_2_4_NC), .in_a_chain(a2_3to2_4), .in_b(b1_4to2_4), .in_c(matrixC1_4), .out_a(out_a_2_4_NC), .out_a_chain(a2_4to2_5), .out_b(b2_4to3_4), .out_b0(b2_4to3_4_ping), .out_b1(b2_4to3_4_pong), .out_c(matrixC2_4), .b_data_valid_ping(b_data_valid_ping_delay2_4), .b_data_valid_pong(b_data_valid_pong_delay2_4), .mode(1'b0)); +processing_element pe2_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(in_a_2_5_NC), .in_a_chain(a2_4to2_5), .in_b(b1_5to2_5), .in_c(matrixC1_5), .out_a(out_a_2_5_NC), .out_a_chain(a2_5to2_6), .out_b(b2_5to3_5), .out_b0(b2_5to3_5_ping), .out_b1(b2_5to3_5_pong), .out_c(matrixC2_5), .b_data_valid_ping(b_data_valid_ping_delay2_5), .b_data_valid_pong(b_data_valid_pong_delay2_5), .mode(1'b0)); +processing_element pe2_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_2_6_NC), .in_a_chain(a2_5to2_6), .in_b(b1_6to2_6), .in_c(matrixC1_6), .out_a(out_a_2_6_NC), .out_a_chain(a2_6to2_7), .out_b(b2_6to3_6), .out_b0(b2_6to3_6_ping), .out_b1(b2_6to3_6_pong), .out_c(matrixC2_6), .b_data_valid_ping(b_data_valid_ping_delay2_6), .b_data_valid_pong(b_data_valid_pong_delay2_6), .mode(1'b0)); +processing_element pe2_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_2_7_NC), .in_a_chain(a2_6to2_7), .in_b(b1_7to2_7), .in_c(matrixC1_7), .out_a(out_a_2_7_NC), .out_a_chain(a2_7to2_8), .out_b(b2_7to3_7), .out_b0(b2_7to3_7_ping), .out_b1(b2_7to3_7_pong), .out_c(matrixC2_7), .b_data_valid_ping(b_data_valid_ping_delay2_7), .b_data_valid_pong(b_data_valid_pong_delay2_7), .mode(1'b0)); +processing_element pe2_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_2_8_NC), .in_a_chain(a2_7to2_8), .in_b(b1_8to2_8), .in_c(matrixC1_8), .out_a(out_a_2_8_NC), .out_a_chain(a2_8to2_9), .out_b(b2_8to3_8), .out_b0(b2_8to3_8_ping), .out_b1(b2_8to3_8_pong), .out_c(matrixC2_8), .b_data_valid_ping(b_data_valid_ping_delay2_8), .b_data_valid_pong(b_data_valid_pong_delay2_8), .mode(1'b0)); +processing_element pe2_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_2_9_NC), .in_a_chain(a2_8to2_9), .in_b(b1_9to2_9), .in_c(matrixC1_9), .out_a(out_a_2_9_NC), .out_a_chain(a2_9to2_10), .out_b(b2_9to3_9), .out_b0(b2_9to3_9_ping), .out_b1(b2_9to3_9_pong), .out_c(matrixC2_9), .b_data_valid_ping(b_data_valid_ping_delay2_9), .b_data_valid_pong(b_data_valid_pong_delay2_9), .mode(1'b0)); +processing_element pe2_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_2_10_NC), .in_a_chain(a2_9to2_10), .in_b(b1_10to2_10), .in_c(matrixC1_10), .out_a(out_a_2_10_NC), .out_a_chain(a2_10to2_11), .out_b(b2_10to3_10), .out_b0(b2_10to3_10_ping), .out_b1(b2_10to3_10_pong), .out_c(matrixC2_10), .b_data_valid_ping(b_data_valid_ping_delay2_10), .b_data_valid_pong(b_data_valid_pong_delay2_10), .mode(1'b0)); +processing_element pe2_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_2_11_NC), .in_a_chain(a2_10to2_11), .in_b(b1_11to2_11), .in_c(matrixC1_11), .out_a(out_a_2_11_NC), .out_a_chain(a2_11to2_12), .out_b(b2_11to3_11), .out_b0(b2_11to3_11_ping), .out_b1(b2_11to3_11_pong), .out_c(matrixC2_11), .b_data_valid_ping(b_data_valid_ping_delay2_11), .b_data_valid_pong(b_data_valid_pong_delay2_11), .mode(1'b0)); +processing_element pe2_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_2_12_NC), .in_a_chain(a2_11to2_12), .in_b(b1_12to2_12), .in_c(matrixC1_12), .out_a(out_a_2_12_NC), .out_a_chain(a2_12to2_13), .out_b(b2_12to3_12), .out_b0(b2_12to3_12_ping), .out_b1(b2_12to3_12_pong), .out_c(matrixC2_12), .b_data_valid_ping(b_data_valid_ping_delay2_12), .b_data_valid_pong(b_data_valid_pong_delay2_12), .mode(1'b0)); +processing_element pe2_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_2_13_NC), .in_a_chain(a2_12to2_13), .in_b(b1_13to2_13), .in_c(matrixC1_13), .out_a(out_a_2_13_NC), .out_a_chain(a2_13to2_14), .out_b(b2_13to3_13), .out_b0(b2_13to3_13_ping), .out_b1(b2_13to3_13_pong), .out_c(matrixC2_13), .b_data_valid_ping(b_data_valid_ping_delay2_13), .b_data_valid_pong(b_data_valid_pong_delay2_13), .mode(1'b0)); +processing_element pe2_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_2_14_NC), .in_a_chain(a2_13to2_14), .in_b(b1_14to2_14), .in_c(matrixC1_14), .out_a(out_a_2_14_NC), .out_a_chain(a2_14to2_15), .out_b(b2_14to3_14), .out_b0(b2_14to3_14_ping), .out_b1(b2_14to3_14_pong), .out_c(matrixC2_14), .b_data_valid_ping(b_data_valid_ping_delay2_14), .b_data_valid_pong(b_data_valid_pong_delay2_14), .mode(1'b0)); +processing_element pe2_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_2_15_NC), .in_a_chain(a2_14to2_15), .in_b(b1_15to2_15), .in_c(matrixC1_15), .out_a(out_a_2_15_NC), .out_a_chain(a2_15to2_16), .out_b(b2_15to3_15), .out_b0(b2_15to3_15_ping), .out_b1(b2_15to3_15_pong), .out_c(matrixC2_15), .b_data_valid_ping(b_data_valid_ping_delay2_15), .b_data_valid_pong(b_data_valid_pong_delay2_15), .mode(1'b0)); +processing_element pe3_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay3), .in_a(a3), .in_a_chain(in_a_chain_3_0_NC), .in_b(b2_0to3_0), .in_c(matrixC2_0), .out_a(out_a_3_0_NC), .out_a_chain(a3_0to3_1), .out_b(b3_0to4_0), .out_b0(b3_0to4_0_ping), .out_b1(b3_0to4_0_pong), .out_c(matrixC3_0), .b_data_valid_ping(b_data_valid_ping_delay3_0), .b_data_valid_pong(b_data_valid_pong_delay3_0), .mode(1'b1)); +processing_element pe3_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay4), .in_a(in_a_3_1_NC), .in_a_chain(a3_0to3_1), .in_b(b2_1to3_1), .in_c(matrixC2_1), .out_a(out_a_3_1_NC), .out_a_chain(a3_1to3_2), .out_b(b3_1to4_1), .out_b0(b3_1to4_1_ping), .out_b1(b3_1to4_1_pong), .out_c(matrixC3_1), .b_data_valid_ping(b_data_valid_ping_delay3_1), .b_data_valid_pong(b_data_valid_pong_delay3_1), .mode(1'b0)); +processing_element pe3_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay5), .in_a(in_a_3_2_NC), .in_a_chain(a3_1to3_2), .in_b(b2_2to3_2), .in_c(matrixC2_2), .out_a(out_a_3_2_NC), .out_a_chain(a3_2to3_3), .out_b(b3_2to4_2), .out_b0(b3_2to4_2_ping), .out_b1(b3_2to4_2_pong), .out_c(matrixC3_2), .b_data_valid_ping(b_data_valid_ping_delay3_2), .b_data_valid_pong(b_data_valid_pong_delay3_2), .mode(1'b0)); +processing_element pe3_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay6), .in_a(in_a_3_3_NC), .in_a_chain(a3_2to3_3), .in_b(b2_3to3_3), .in_c(matrixC2_3), .out_a(out_a_3_3_NC), .out_a_chain(a3_3to3_4), .out_b(b3_3to4_3), .out_b0(b3_3to4_3_ping), .out_b1(b3_3to4_3_pong), .out_c(matrixC3_3), .b_data_valid_ping(b_data_valid_ping_delay3_3), .b_data_valid_pong(b_data_valid_pong_delay3_3), .mode(1'b0)); +processing_element pe3_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(in_a_3_4_NC), .in_a_chain(a3_3to3_4), .in_b(b2_4to3_4), .in_c(matrixC2_4), .out_a(out_a_3_4_NC), .out_a_chain(a3_4to3_5), .out_b(b3_4to4_4), .out_b0(b3_4to4_4_ping), .out_b1(b3_4to4_4_pong), .out_c(matrixC3_4), .b_data_valid_ping(b_data_valid_ping_delay3_4), .b_data_valid_pong(b_data_valid_pong_delay3_4), .mode(1'b0)); +processing_element pe3_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_3_5_NC), .in_a_chain(a3_4to3_5), .in_b(b2_5to3_5), .in_c(matrixC2_5), .out_a(out_a_3_5_NC), .out_a_chain(a3_5to3_6), .out_b(b3_5to4_5), .out_b0(b3_5to4_5_ping), .out_b1(b3_5to4_5_pong), .out_c(matrixC3_5), .b_data_valid_ping(b_data_valid_ping_delay3_5), .b_data_valid_pong(b_data_valid_pong_delay3_5), .mode(1'b0)); +processing_element pe3_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_3_6_NC), .in_a_chain(a3_5to3_6), .in_b(b2_6to3_6), .in_c(matrixC2_6), .out_a(out_a_3_6_NC), .out_a_chain(a3_6to3_7), .out_b(b3_6to4_6), .out_b0(b3_6to4_6_ping), .out_b1(b3_6to4_6_pong), .out_c(matrixC3_6), .b_data_valid_ping(b_data_valid_ping_delay3_6), .b_data_valid_pong(b_data_valid_pong_delay3_6), .mode(1'b0)); +processing_element pe3_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_3_7_NC), .in_a_chain(a3_6to3_7), .in_b(b2_7to3_7), .in_c(matrixC2_7), .out_a(out_a_3_7_NC), .out_a_chain(a3_7to3_8), .out_b(b3_7to4_7), .out_b0(b3_7to4_7_ping), .out_b1(b3_7to4_7_pong), .out_c(matrixC3_7), .b_data_valid_ping(b_data_valid_ping_delay3_7), .b_data_valid_pong(b_data_valid_pong_delay3_7), .mode(1'b0)); +processing_element pe3_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_3_8_NC), .in_a_chain(a3_7to3_8), .in_b(b2_8to3_8), .in_c(matrixC2_8), .out_a(out_a_3_8_NC), .out_a_chain(a3_8to3_9), .out_b(b3_8to4_8), .out_b0(b3_8to4_8_ping), .out_b1(b3_8to4_8_pong), .out_c(matrixC3_8), .b_data_valid_ping(b_data_valid_ping_delay3_8), .b_data_valid_pong(b_data_valid_pong_delay3_8), .mode(1'b0)); +processing_element pe3_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_3_9_NC), .in_a_chain(a3_8to3_9), .in_b(b2_9to3_9), .in_c(matrixC2_9), .out_a(out_a_3_9_NC), .out_a_chain(a3_9to3_10), .out_b(b3_9to4_9), .out_b0(b3_9to4_9_ping), .out_b1(b3_9to4_9_pong), .out_c(matrixC3_9), .b_data_valid_ping(b_data_valid_ping_delay3_9), .b_data_valid_pong(b_data_valid_pong_delay3_9), .mode(1'b0)); +processing_element pe3_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_3_10_NC), .in_a_chain(a3_9to3_10), .in_b(b2_10to3_10), .in_c(matrixC2_10), .out_a(out_a_3_10_NC), .out_a_chain(a3_10to3_11), .out_b(b3_10to4_10), .out_b0(b3_10to4_10_ping), .out_b1(b3_10to4_10_pong), .out_c(matrixC3_10), .b_data_valid_ping(b_data_valid_ping_delay3_10), .b_data_valid_pong(b_data_valid_pong_delay3_10), .mode(1'b0)); +processing_element pe3_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_3_11_NC), .in_a_chain(a3_10to3_11), .in_b(b2_11to3_11), .in_c(matrixC2_11), .out_a(out_a_3_11_NC), .out_a_chain(a3_11to3_12), .out_b(b3_11to4_11), .out_b0(b3_11to4_11_ping), .out_b1(b3_11to4_11_pong), .out_c(matrixC3_11), .b_data_valid_ping(b_data_valid_ping_delay3_11), .b_data_valid_pong(b_data_valid_pong_delay3_11), .mode(1'b0)); +processing_element pe3_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_3_12_NC), .in_a_chain(a3_11to3_12), .in_b(b2_12to3_12), .in_c(matrixC2_12), .out_a(out_a_3_12_NC), .out_a_chain(a3_12to3_13), .out_b(b3_12to4_12), .out_b0(b3_12to4_12_ping), .out_b1(b3_12to4_12_pong), .out_c(matrixC3_12), .b_data_valid_ping(b_data_valid_ping_delay3_12), .b_data_valid_pong(b_data_valid_pong_delay3_12), .mode(1'b0)); +processing_element pe3_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_3_13_NC), .in_a_chain(a3_12to3_13), .in_b(b2_13to3_13), .in_c(matrixC2_13), .out_a(out_a_3_13_NC), .out_a_chain(a3_13to3_14), .out_b(b3_13to4_13), .out_b0(b3_13to4_13_ping), .out_b1(b3_13to4_13_pong), .out_c(matrixC3_13), .b_data_valid_ping(b_data_valid_ping_delay3_13), .b_data_valid_pong(b_data_valid_pong_delay3_13), .mode(1'b0)); +processing_element pe3_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_3_14_NC), .in_a_chain(a3_13to3_14), .in_b(b2_14to3_14), .in_c(matrixC2_14), .out_a(out_a_3_14_NC), .out_a_chain(a3_14to3_15), .out_b(b3_14to4_14), .out_b0(b3_14to4_14_ping), .out_b1(b3_14to4_14_pong), .out_c(matrixC3_14), .b_data_valid_ping(b_data_valid_ping_delay3_14), .b_data_valid_pong(b_data_valid_pong_delay3_14), .mode(1'b0)); +processing_element pe3_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_3_15_NC), .in_a_chain(a3_14to3_15), .in_b(b2_15to3_15), .in_c(matrixC2_15), .out_a(out_a_3_15_NC), .out_a_chain(a3_15to3_16), .out_b(b3_15to4_15), .out_b0(b3_15to4_15_ping), .out_b1(b3_15to4_15_pong), .out_c(matrixC3_15), .b_data_valid_ping(b_data_valid_ping_delay3_15), .b_data_valid_pong(b_data_valid_pong_delay3_15), .mode(1'b0)); +processing_element pe4_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay4), .in_a(a4), .in_a_chain(in_a_chain_4_0_NC), .in_b(b3_0to4_0), .in_c(matrixC3_0), .out_a(out_a_4_0_NC), .out_a_chain(a4_0to4_1), .out_b(b4_0to5_0), .out_b0(b4_0to5_0_ping), .out_b1(b4_0to5_0_pong), .out_c(matrixC4_0), .b_data_valid_ping(b_data_valid_ping_delay4_0), .b_data_valid_pong(b_data_valid_pong_delay4_0), .mode(1'b1)); +processing_element pe4_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay5), .in_a(in_a_4_1_NC), .in_a_chain(a4_0to4_1), .in_b(b3_1to4_1), .in_c(matrixC3_1), .out_a(out_a_4_1_NC), .out_a_chain(a4_1to4_2), .out_b(b4_1to5_1), .out_b0(b4_1to5_1_ping), .out_b1(b4_1to5_1_pong), .out_c(matrixC4_1), .b_data_valid_ping(b_data_valid_ping_delay4_1), .b_data_valid_pong(b_data_valid_pong_delay4_1), .mode(1'b0)); +processing_element pe4_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay6), .in_a(in_a_4_2_NC), .in_a_chain(a4_1to4_2), .in_b(b3_2to4_2), .in_c(matrixC3_2), .out_a(out_a_4_2_NC), .out_a_chain(a4_2to4_3), .out_b(b4_2to5_2), .out_b0(b4_2to5_2_ping), .out_b1(b4_2to5_2_pong), .out_c(matrixC4_2), .b_data_valid_ping(b_data_valid_ping_delay4_2), .b_data_valid_pong(b_data_valid_pong_delay4_2), .mode(1'b0)); +processing_element pe4_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(in_a_4_3_NC), .in_a_chain(a4_2to4_3), .in_b(b3_3to4_3), .in_c(matrixC3_3), .out_a(out_a_4_3_NC), .out_a_chain(a4_3to4_4), .out_b(b4_3to5_3), .out_b0(b4_3to5_3_ping), .out_b1(b4_3to5_3_pong), .out_c(matrixC4_3), .b_data_valid_ping(b_data_valid_ping_delay4_3), .b_data_valid_pong(b_data_valid_pong_delay4_3), .mode(1'b0)); +processing_element pe4_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_4_4_NC), .in_a_chain(a4_3to4_4), .in_b(b3_4to4_4), .in_c(matrixC3_4), .out_a(out_a_4_4_NC), .out_a_chain(a4_4to4_5), .out_b(b4_4to5_4), .out_b0(b4_4to5_4_ping), .out_b1(b4_4to5_4_pong), .out_c(matrixC4_4), .b_data_valid_ping(b_data_valid_ping_delay4_4), .b_data_valid_pong(b_data_valid_pong_delay4_4), .mode(1'b0)); +processing_element pe4_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_4_5_NC), .in_a_chain(a4_4to4_5), .in_b(b3_5to4_5), .in_c(matrixC3_5), .out_a(out_a_4_5_NC), .out_a_chain(a4_5to4_6), .out_b(b4_5to5_5), .out_b0(b4_5to5_5_ping), .out_b1(b4_5to5_5_pong), .out_c(matrixC4_5), .b_data_valid_ping(b_data_valid_ping_delay4_5), .b_data_valid_pong(b_data_valid_pong_delay4_5), .mode(1'b0)); +processing_element pe4_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_4_6_NC), .in_a_chain(a4_5to4_6), .in_b(b3_6to4_6), .in_c(matrixC3_6), .out_a(out_a_4_6_NC), .out_a_chain(a4_6to4_7), .out_b(b4_6to5_6), .out_b0(b4_6to5_6_ping), .out_b1(b4_6to5_6_pong), .out_c(matrixC4_6), .b_data_valid_ping(b_data_valid_ping_delay4_6), .b_data_valid_pong(b_data_valid_pong_delay4_6), .mode(1'b0)); +processing_element pe4_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_4_7_NC), .in_a_chain(a4_6to4_7), .in_b(b3_7to4_7), .in_c(matrixC3_7), .out_a(out_a_4_7_NC), .out_a_chain(a4_7to4_8), .out_b(b4_7to5_7), .out_b0(b4_7to5_7_ping), .out_b1(b4_7to5_7_pong), .out_c(matrixC4_7), .b_data_valid_ping(b_data_valid_ping_delay4_7), .b_data_valid_pong(b_data_valid_pong_delay4_7), .mode(1'b0)); +processing_element pe4_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_4_8_NC), .in_a_chain(a4_7to4_8), .in_b(b3_8to4_8), .in_c(matrixC3_8), .out_a(out_a_4_8_NC), .out_a_chain(a4_8to4_9), .out_b(b4_8to5_8), .out_b0(b4_8to5_8_ping), .out_b1(b4_8to5_8_pong), .out_c(matrixC4_8), .b_data_valid_ping(b_data_valid_ping_delay4_8), .b_data_valid_pong(b_data_valid_pong_delay4_8), .mode(1'b0)); +processing_element pe4_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_4_9_NC), .in_a_chain(a4_8to4_9), .in_b(b3_9to4_9), .in_c(matrixC3_9), .out_a(out_a_4_9_NC), .out_a_chain(a4_9to4_10), .out_b(b4_9to5_9), .out_b0(b4_9to5_9_ping), .out_b1(b4_9to5_9_pong), .out_c(matrixC4_9), .b_data_valid_ping(b_data_valid_ping_delay4_9), .b_data_valid_pong(b_data_valid_pong_delay4_9), .mode(1'b0)); +processing_element pe4_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_4_10_NC), .in_a_chain(a4_9to4_10), .in_b(b3_10to4_10), .in_c(matrixC3_10), .out_a(out_a_4_10_NC), .out_a_chain(a4_10to4_11), .out_b(b4_10to5_10), .out_b0(b4_10to5_10_ping), .out_b1(b4_10to5_10_pong), .out_c(matrixC4_10), .b_data_valid_ping(b_data_valid_ping_delay4_10), .b_data_valid_pong(b_data_valid_pong_delay4_10), .mode(1'b0)); +processing_element pe4_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_4_11_NC), .in_a_chain(a4_10to4_11), .in_b(b3_11to4_11), .in_c(matrixC3_11), .out_a(out_a_4_11_NC), .out_a_chain(a4_11to4_12), .out_b(b4_11to5_11), .out_b0(b4_11to5_11_ping), .out_b1(b4_11to5_11_pong), .out_c(matrixC4_11), .b_data_valid_ping(b_data_valid_ping_delay4_11), .b_data_valid_pong(b_data_valid_pong_delay4_11), .mode(1'b0)); +processing_element pe4_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_4_12_NC), .in_a_chain(a4_11to4_12), .in_b(b3_12to4_12), .in_c(matrixC3_12), .out_a(out_a_4_12_NC), .out_a_chain(a4_12to4_13), .out_b(b4_12to5_12), .out_b0(b4_12to5_12_ping), .out_b1(b4_12to5_12_pong), .out_c(matrixC4_12), .b_data_valid_ping(b_data_valid_ping_delay4_12), .b_data_valid_pong(b_data_valid_pong_delay4_12), .mode(1'b0)); +processing_element pe4_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_4_13_NC), .in_a_chain(a4_12to4_13), .in_b(b3_13to4_13), .in_c(matrixC3_13), .out_a(out_a_4_13_NC), .out_a_chain(a4_13to4_14), .out_b(b4_13to5_13), .out_b0(b4_13to5_13_ping), .out_b1(b4_13to5_13_pong), .out_c(matrixC4_13), .b_data_valid_ping(b_data_valid_ping_delay4_13), .b_data_valid_pong(b_data_valid_pong_delay4_13), .mode(1'b0)); +processing_element pe4_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_4_14_NC), .in_a_chain(a4_13to4_14), .in_b(b3_14to4_14), .in_c(matrixC3_14), .out_a(out_a_4_14_NC), .out_a_chain(a4_14to4_15), .out_b(b4_14to5_14), .out_b0(b4_14to5_14_ping), .out_b1(b4_14to5_14_pong), .out_c(matrixC4_14), .b_data_valid_ping(b_data_valid_ping_delay4_14), .b_data_valid_pong(b_data_valid_pong_delay4_14), .mode(1'b0)); +processing_element pe4_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_4_15_NC), .in_a_chain(a4_14to4_15), .in_b(b3_15to4_15), .in_c(matrixC3_15), .out_a(out_a_4_15_NC), .out_a_chain(a4_15to4_16), .out_b(b4_15to5_15), .out_b0(b4_15to5_15_ping), .out_b1(b4_15to5_15_pong), .out_c(matrixC4_15), .b_data_valid_ping(b_data_valid_ping_delay4_15), .b_data_valid_pong(b_data_valid_pong_delay4_15), .mode(1'b0)); +processing_element pe5_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay5), .in_a(a5), .in_a_chain(in_a_chain_5_0_NC), .in_b(b4_0to5_0), .in_c(matrixC4_0), .out_a(out_a_5_0_NC), .out_a_chain(a5_0to5_1), .out_b(b5_0to6_0), .out_b0(b5_0to6_0_ping), .out_b1(b5_0to6_0_pong), .out_c(matrixC5_0), .b_data_valid_ping(b_data_valid_ping_delay5_0), .b_data_valid_pong(b_data_valid_pong_delay5_0), .mode(1'b1)); +processing_element pe5_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay6), .in_a(in_a_5_1_NC), .in_a_chain(a5_0to5_1), .in_b(b4_1to5_1), .in_c(matrixC4_1), .out_a(out_a_5_1_NC), .out_a_chain(a5_1to5_2), .out_b(b5_1to6_1), .out_b0(b5_1to6_1_ping), .out_b1(b5_1to6_1_pong), .out_c(matrixC5_1), .b_data_valid_ping(b_data_valid_ping_delay5_1), .b_data_valid_pong(b_data_valid_pong_delay5_1), .mode(1'b0)); +processing_element pe5_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(in_a_5_2_NC), .in_a_chain(a5_1to5_2), .in_b(b4_2to5_2), .in_c(matrixC4_2), .out_a(out_a_5_2_NC), .out_a_chain(a5_2to5_3), .out_b(b5_2to6_2), .out_b0(b5_2to6_2_ping), .out_b1(b5_2to6_2_pong), .out_c(matrixC5_2), .b_data_valid_ping(b_data_valid_ping_delay5_2), .b_data_valid_pong(b_data_valid_pong_delay5_2), .mode(1'b0)); +processing_element pe5_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_5_3_NC), .in_a_chain(a5_2to5_3), .in_b(b4_3to5_3), .in_c(matrixC4_3), .out_a(out_a_5_3_NC), .out_a_chain(a5_3to5_4), .out_b(b5_3to6_3), .out_b0(b5_3to6_3_ping), .out_b1(b5_3to6_3_pong), .out_c(matrixC5_3), .b_data_valid_ping(b_data_valid_ping_delay5_3), .b_data_valid_pong(b_data_valid_pong_delay5_3), .mode(1'b0)); +processing_element pe5_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_5_4_NC), .in_a_chain(a5_3to5_4), .in_b(b4_4to5_4), .in_c(matrixC4_4), .out_a(out_a_5_4_NC), .out_a_chain(a5_4to5_5), .out_b(b5_4to6_4), .out_b0(b5_4to6_4_ping), .out_b1(b5_4to6_4_pong), .out_c(matrixC5_4), .b_data_valid_ping(b_data_valid_ping_delay5_4), .b_data_valid_pong(b_data_valid_pong_delay5_4), .mode(1'b0)); +processing_element pe5_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_5_5_NC), .in_a_chain(a5_4to5_5), .in_b(b4_5to5_5), .in_c(matrixC4_5), .out_a(out_a_5_5_NC), .out_a_chain(a5_5to5_6), .out_b(b5_5to6_5), .out_b0(b5_5to6_5_ping), .out_b1(b5_5to6_5_pong), .out_c(matrixC5_5), .b_data_valid_ping(b_data_valid_ping_delay5_5), .b_data_valid_pong(b_data_valid_pong_delay5_5), .mode(1'b0)); +processing_element pe5_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_5_6_NC), .in_a_chain(a5_5to5_6), .in_b(b4_6to5_6), .in_c(matrixC4_6), .out_a(out_a_5_6_NC), .out_a_chain(a5_6to5_7), .out_b(b5_6to6_6), .out_b0(b5_6to6_6_ping), .out_b1(b5_6to6_6_pong), .out_c(matrixC5_6), .b_data_valid_ping(b_data_valid_ping_delay5_6), .b_data_valid_pong(b_data_valid_pong_delay5_6), .mode(1'b0)); +processing_element pe5_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_5_7_NC), .in_a_chain(a5_6to5_7), .in_b(b4_7to5_7), .in_c(matrixC4_7), .out_a(out_a_5_7_NC), .out_a_chain(a5_7to5_8), .out_b(b5_7to6_7), .out_b0(b5_7to6_7_ping), .out_b1(b5_7to6_7_pong), .out_c(matrixC5_7), .b_data_valid_ping(b_data_valid_ping_delay5_7), .b_data_valid_pong(b_data_valid_pong_delay5_7), .mode(1'b0)); +processing_element pe5_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_5_8_NC), .in_a_chain(a5_7to5_8), .in_b(b4_8to5_8), .in_c(matrixC4_8), .out_a(out_a_5_8_NC), .out_a_chain(a5_8to5_9), .out_b(b5_8to6_8), .out_b0(b5_8to6_8_ping), .out_b1(b5_8to6_8_pong), .out_c(matrixC5_8), .b_data_valid_ping(b_data_valid_ping_delay5_8), .b_data_valid_pong(b_data_valid_pong_delay5_8), .mode(1'b0)); +processing_element pe5_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_5_9_NC), .in_a_chain(a5_8to5_9), .in_b(b4_9to5_9), .in_c(matrixC4_9), .out_a(out_a_5_9_NC), .out_a_chain(a5_9to5_10), .out_b(b5_9to6_9), .out_b0(b5_9to6_9_ping), .out_b1(b5_9to6_9_pong), .out_c(matrixC5_9), .b_data_valid_ping(b_data_valid_ping_delay5_9), .b_data_valid_pong(b_data_valid_pong_delay5_9), .mode(1'b0)); +processing_element pe5_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_5_10_NC), .in_a_chain(a5_9to5_10), .in_b(b4_10to5_10), .in_c(matrixC4_10), .out_a(out_a_5_10_NC), .out_a_chain(a5_10to5_11), .out_b(b5_10to6_10), .out_b0(b5_10to6_10_ping), .out_b1(b5_10to6_10_pong), .out_c(matrixC5_10), .b_data_valid_ping(b_data_valid_ping_delay5_10), .b_data_valid_pong(b_data_valid_pong_delay5_10), .mode(1'b0)); +processing_element pe5_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_5_11_NC), .in_a_chain(a5_10to5_11), .in_b(b4_11to5_11), .in_c(matrixC4_11), .out_a(out_a_5_11_NC), .out_a_chain(a5_11to5_12), .out_b(b5_11to6_11), .out_b0(b5_11to6_11_ping), .out_b1(b5_11to6_11_pong), .out_c(matrixC5_11), .b_data_valid_ping(b_data_valid_ping_delay5_11), .b_data_valid_pong(b_data_valid_pong_delay5_11), .mode(1'b0)); +processing_element pe5_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_5_12_NC), .in_a_chain(a5_11to5_12), .in_b(b4_12to5_12), .in_c(matrixC4_12), .out_a(out_a_5_12_NC), .out_a_chain(a5_12to5_13), .out_b(b5_12to6_12), .out_b0(b5_12to6_12_ping), .out_b1(b5_12to6_12_pong), .out_c(matrixC5_12), .b_data_valid_ping(b_data_valid_ping_delay5_12), .b_data_valid_pong(b_data_valid_pong_delay5_12), .mode(1'b0)); +processing_element pe5_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_5_13_NC), .in_a_chain(a5_12to5_13), .in_b(b4_13to5_13), .in_c(matrixC4_13), .out_a(out_a_5_13_NC), .out_a_chain(a5_13to5_14), .out_b(b5_13to6_13), .out_b0(b5_13to6_13_ping), .out_b1(b5_13to6_13_pong), .out_c(matrixC5_13), .b_data_valid_ping(b_data_valid_ping_delay5_13), .b_data_valid_pong(b_data_valid_pong_delay5_13), .mode(1'b0)); +processing_element pe5_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_5_14_NC), .in_a_chain(a5_13to5_14), .in_b(b4_14to5_14), .in_c(matrixC4_14), .out_a(out_a_5_14_NC), .out_a_chain(a5_14to5_15), .out_b(b5_14to6_14), .out_b0(b5_14to6_14_ping), .out_b1(b5_14to6_14_pong), .out_c(matrixC5_14), .b_data_valid_ping(b_data_valid_ping_delay5_14), .b_data_valid_pong(b_data_valid_pong_delay5_14), .mode(1'b0)); +processing_element pe5_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_5_15_NC), .in_a_chain(a5_14to5_15), .in_b(b4_15to5_15), .in_c(matrixC4_15), .out_a(out_a_5_15_NC), .out_a_chain(a5_15to5_16), .out_b(b5_15to6_15), .out_b0(b5_15to6_15_ping), .out_b1(b5_15to6_15_pong), .out_c(matrixC5_15), .b_data_valid_ping(b_data_valid_ping_delay5_15), .b_data_valid_pong(b_data_valid_pong_delay5_15), .mode(1'b0)); +processing_element pe6_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay6), .in_a(a6), .in_a_chain(in_a_chain_6_0_NC), .in_b(b5_0to6_0), .in_c(matrixC5_0), .out_a(out_a_6_0_NC), .out_a_chain(a6_0to6_1), .out_b(b6_0to7_0), .out_b0(b6_0to7_0_ping), .out_b1(b6_0to7_0_pong), .out_c(matrixC6_0), .b_data_valid_ping(b_data_valid_ping_delay6_0), .b_data_valid_pong(b_data_valid_pong_delay6_0), .mode(1'b1)); +processing_element pe6_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(in_a_6_1_NC), .in_a_chain(a6_0to6_1), .in_b(b5_1to6_1), .in_c(matrixC5_1), .out_a(out_a_6_1_NC), .out_a_chain(a6_1to6_2), .out_b(b6_1to7_1), .out_b0(b6_1to7_1_ping), .out_b1(b6_1to7_1_pong), .out_c(matrixC6_1), .b_data_valid_ping(b_data_valid_ping_delay6_1), .b_data_valid_pong(b_data_valid_pong_delay6_1), .mode(1'b0)); +processing_element pe6_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_6_2_NC), .in_a_chain(a6_1to6_2), .in_b(b5_2to6_2), .in_c(matrixC5_2), .out_a(out_a_6_2_NC), .out_a_chain(a6_2to6_3), .out_b(b6_2to7_2), .out_b0(b6_2to7_2_ping), .out_b1(b6_2to7_2_pong), .out_c(matrixC6_2), .b_data_valid_ping(b_data_valid_ping_delay6_2), .b_data_valid_pong(b_data_valid_pong_delay6_2), .mode(1'b0)); +processing_element pe6_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_6_3_NC), .in_a_chain(a6_2to6_3), .in_b(b5_3to6_3), .in_c(matrixC5_3), .out_a(out_a_6_3_NC), .out_a_chain(a6_3to6_4), .out_b(b6_3to7_3), .out_b0(b6_3to7_3_ping), .out_b1(b6_3to7_3_pong), .out_c(matrixC6_3), .b_data_valid_ping(b_data_valid_ping_delay6_3), .b_data_valid_pong(b_data_valid_pong_delay6_3), .mode(1'b0)); +processing_element pe6_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_6_4_NC), .in_a_chain(a6_3to6_4), .in_b(b5_4to6_4), .in_c(matrixC5_4), .out_a(out_a_6_4_NC), .out_a_chain(a6_4to6_5), .out_b(b6_4to7_4), .out_b0(b6_4to7_4_ping), .out_b1(b6_4to7_4_pong), .out_c(matrixC6_4), .b_data_valid_ping(b_data_valid_ping_delay6_4), .b_data_valid_pong(b_data_valid_pong_delay6_4), .mode(1'b0)); +processing_element pe6_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_6_5_NC), .in_a_chain(a6_4to6_5), .in_b(b5_5to6_5), .in_c(matrixC5_5), .out_a(out_a_6_5_NC), .out_a_chain(a6_5to6_6), .out_b(b6_5to7_5), .out_b0(b6_5to7_5_ping), .out_b1(b6_5to7_5_pong), .out_c(matrixC6_5), .b_data_valid_ping(b_data_valid_ping_delay6_5), .b_data_valid_pong(b_data_valid_pong_delay6_5), .mode(1'b0)); +processing_element pe6_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_6_6_NC), .in_a_chain(a6_5to6_6), .in_b(b5_6to6_6), .in_c(matrixC5_6), .out_a(out_a_6_6_NC), .out_a_chain(a6_6to6_7), .out_b(b6_6to7_6), .out_b0(b6_6to7_6_ping), .out_b1(b6_6to7_6_pong), .out_c(matrixC6_6), .b_data_valid_ping(b_data_valid_ping_delay6_6), .b_data_valid_pong(b_data_valid_pong_delay6_6), .mode(1'b0)); +processing_element pe6_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_6_7_NC), .in_a_chain(a6_6to6_7), .in_b(b5_7to6_7), .in_c(matrixC5_7), .out_a(out_a_6_7_NC), .out_a_chain(a6_7to6_8), .out_b(b6_7to7_7), .out_b0(b6_7to7_7_ping), .out_b1(b6_7to7_7_pong), .out_c(matrixC6_7), .b_data_valid_ping(b_data_valid_ping_delay6_7), .b_data_valid_pong(b_data_valid_pong_delay6_7), .mode(1'b0)); +processing_element pe6_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_6_8_NC), .in_a_chain(a6_7to6_8), .in_b(b5_8to6_8), .in_c(matrixC5_8), .out_a(out_a_6_8_NC), .out_a_chain(a6_8to6_9), .out_b(b6_8to7_8), .out_b0(b6_8to7_8_ping), .out_b1(b6_8to7_8_pong), .out_c(matrixC6_8), .b_data_valid_ping(b_data_valid_ping_delay6_8), .b_data_valid_pong(b_data_valid_pong_delay6_8), .mode(1'b0)); +processing_element pe6_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_6_9_NC), .in_a_chain(a6_8to6_9), .in_b(b5_9to6_9), .in_c(matrixC5_9), .out_a(out_a_6_9_NC), .out_a_chain(a6_9to6_10), .out_b(b6_9to7_9), .out_b0(b6_9to7_9_ping), .out_b1(b6_9to7_9_pong), .out_c(matrixC6_9), .b_data_valid_ping(b_data_valid_ping_delay6_9), .b_data_valid_pong(b_data_valid_pong_delay6_9), .mode(1'b0)); +processing_element pe6_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_6_10_NC), .in_a_chain(a6_9to6_10), .in_b(b5_10to6_10), .in_c(matrixC5_10), .out_a(out_a_6_10_NC), .out_a_chain(a6_10to6_11), .out_b(b6_10to7_10), .out_b0(b6_10to7_10_ping), .out_b1(b6_10to7_10_pong), .out_c(matrixC6_10), .b_data_valid_ping(b_data_valid_ping_delay6_10), .b_data_valid_pong(b_data_valid_pong_delay6_10), .mode(1'b0)); +processing_element pe6_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_6_11_NC), .in_a_chain(a6_10to6_11), .in_b(b5_11to6_11), .in_c(matrixC5_11), .out_a(out_a_6_11_NC), .out_a_chain(a6_11to6_12), .out_b(b6_11to7_11), .out_b0(b6_11to7_11_ping), .out_b1(b6_11to7_11_pong), .out_c(matrixC6_11), .b_data_valid_ping(b_data_valid_ping_delay6_11), .b_data_valid_pong(b_data_valid_pong_delay6_11), .mode(1'b0)); +processing_element pe6_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_6_12_NC), .in_a_chain(a6_11to6_12), .in_b(b5_12to6_12), .in_c(matrixC5_12), .out_a(out_a_6_12_NC), .out_a_chain(a6_12to6_13), .out_b(b6_12to7_12), .out_b0(b6_12to7_12_ping), .out_b1(b6_12to7_12_pong), .out_c(matrixC6_12), .b_data_valid_ping(b_data_valid_ping_delay6_12), .b_data_valid_pong(b_data_valid_pong_delay6_12), .mode(1'b0)); +processing_element pe6_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_6_13_NC), .in_a_chain(a6_12to6_13), .in_b(b5_13to6_13), .in_c(matrixC5_13), .out_a(out_a_6_13_NC), .out_a_chain(a6_13to6_14), .out_b(b6_13to7_13), .out_b0(b6_13to7_13_ping), .out_b1(b6_13to7_13_pong), .out_c(matrixC6_13), .b_data_valid_ping(b_data_valid_ping_delay6_13), .b_data_valid_pong(b_data_valid_pong_delay6_13), .mode(1'b0)); +processing_element pe6_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_6_14_NC), .in_a_chain(a6_13to6_14), .in_b(b5_14to6_14), .in_c(matrixC5_14), .out_a(out_a_6_14_NC), .out_a_chain(a6_14to6_15), .out_b(b6_14to7_14), .out_b0(b6_14to7_14_ping), .out_b1(b6_14to7_14_pong), .out_c(matrixC6_14), .b_data_valid_ping(b_data_valid_ping_delay6_14), .b_data_valid_pong(b_data_valid_pong_delay6_14), .mode(1'b0)); +processing_element pe6_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_6_15_NC), .in_a_chain(a6_14to6_15), .in_b(b5_15to6_15), .in_c(matrixC5_15), .out_a(out_a_6_15_NC), .out_a_chain(a6_15to6_16), .out_b(b6_15to7_15), .out_b0(b6_15to7_15_ping), .out_b1(b6_15to7_15_pong), .out_c(matrixC6_15), .b_data_valid_ping(b_data_valid_ping_delay6_15), .b_data_valid_pong(b_data_valid_pong_delay6_15), .mode(1'b0)); +processing_element pe7_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay7), .in_a(a7), .in_a_chain(in_a_chain_7_0_NC), .in_b(b6_0to7_0), .in_c(matrixC6_0), .out_a(out_a_7_0_NC), .out_a_chain(a7_0to7_1), .out_b(b7_0to8_0), .out_b0(b7_0to8_0_ping), .out_b1(b7_0to8_0_pong), .out_c(matrixC7_0), .b_data_valid_ping(b_data_valid_ping_delay7_0), .b_data_valid_pong(b_data_valid_pong_delay7_0), .mode(1'b1)); +processing_element pe7_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(in_a_7_1_NC), .in_a_chain(a7_0to7_1), .in_b(b6_1to7_1), .in_c(matrixC6_1), .out_a(out_a_7_1_NC), .out_a_chain(a7_1to7_2), .out_b(b7_1to8_1), .out_b0(b7_1to8_1_ping), .out_b1(b7_1to8_1_pong), .out_c(matrixC7_1), .b_data_valid_ping(b_data_valid_ping_delay7_1), .b_data_valid_pong(b_data_valid_pong_delay7_1), .mode(1'b0)); +processing_element pe7_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_7_2_NC), .in_a_chain(a7_1to7_2), .in_b(b6_2to7_2), .in_c(matrixC6_2), .out_a(out_a_7_2_NC), .out_a_chain(a7_2to7_3), .out_b(b7_2to8_2), .out_b0(b7_2to8_2_ping), .out_b1(b7_2to8_2_pong), .out_c(matrixC7_2), .b_data_valid_ping(b_data_valid_ping_delay7_2), .b_data_valid_pong(b_data_valid_pong_delay7_2), .mode(1'b0)); +processing_element pe7_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_7_3_NC), .in_a_chain(a7_2to7_3), .in_b(b6_3to7_3), .in_c(matrixC6_3), .out_a(out_a_7_3_NC), .out_a_chain(a7_3to7_4), .out_b(b7_3to8_3), .out_b0(b7_3to8_3_ping), .out_b1(b7_3to8_3_pong), .out_c(matrixC7_3), .b_data_valid_ping(b_data_valid_ping_delay7_3), .b_data_valid_pong(b_data_valid_pong_delay7_3), .mode(1'b0)); +processing_element pe7_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_7_4_NC), .in_a_chain(a7_3to7_4), .in_b(b6_4to7_4), .in_c(matrixC6_4), .out_a(out_a_7_4_NC), .out_a_chain(a7_4to7_5), .out_b(b7_4to8_4), .out_b0(b7_4to8_4_ping), .out_b1(b7_4to8_4_pong), .out_c(matrixC7_4), .b_data_valid_ping(b_data_valid_ping_delay7_4), .b_data_valid_pong(b_data_valid_pong_delay7_4), .mode(1'b0)); +processing_element pe7_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_7_5_NC), .in_a_chain(a7_4to7_5), .in_b(b6_5to7_5), .in_c(matrixC6_5), .out_a(out_a_7_5_NC), .out_a_chain(a7_5to7_6), .out_b(b7_5to8_5), .out_b0(b7_5to8_5_ping), .out_b1(b7_5to8_5_pong), .out_c(matrixC7_5), .b_data_valid_ping(b_data_valid_ping_delay7_5), .b_data_valid_pong(b_data_valid_pong_delay7_5), .mode(1'b0)); +processing_element pe7_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_7_6_NC), .in_a_chain(a7_5to7_6), .in_b(b6_6to7_6), .in_c(matrixC6_6), .out_a(out_a_7_6_NC), .out_a_chain(a7_6to7_7), .out_b(b7_6to8_6), .out_b0(b7_6to8_6_ping), .out_b1(b7_6to8_6_pong), .out_c(matrixC7_6), .b_data_valid_ping(b_data_valid_ping_delay7_6), .b_data_valid_pong(b_data_valid_pong_delay7_6), .mode(1'b0)); +processing_element pe7_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_7_7_NC), .in_a_chain(a7_6to7_7), .in_b(b6_7to7_7), .in_c(matrixC6_7), .out_a(out_a_7_7_NC), .out_a_chain(a7_7to7_8), .out_b(b7_7to8_7), .out_b0(b7_7to8_7_ping), .out_b1(b7_7to8_7_pong), .out_c(matrixC7_7), .b_data_valid_ping(b_data_valid_ping_delay7_7), .b_data_valid_pong(b_data_valid_pong_delay7_7), .mode(1'b0)); +processing_element pe7_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_7_8_NC), .in_a_chain(a7_7to7_8), .in_b(b6_8to7_8), .in_c(matrixC6_8), .out_a(out_a_7_8_NC), .out_a_chain(a7_8to7_9), .out_b(b7_8to8_8), .out_b0(b7_8to8_8_ping), .out_b1(b7_8to8_8_pong), .out_c(matrixC7_8), .b_data_valid_ping(b_data_valid_ping_delay7_8), .b_data_valid_pong(b_data_valid_pong_delay7_8), .mode(1'b0)); +processing_element pe7_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_7_9_NC), .in_a_chain(a7_8to7_9), .in_b(b6_9to7_9), .in_c(matrixC6_9), .out_a(out_a_7_9_NC), .out_a_chain(a7_9to7_10), .out_b(b7_9to8_9), .out_b0(b7_9to8_9_ping), .out_b1(b7_9to8_9_pong), .out_c(matrixC7_9), .b_data_valid_ping(b_data_valid_ping_delay7_9), .b_data_valid_pong(b_data_valid_pong_delay7_9), .mode(1'b0)); +processing_element pe7_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_7_10_NC), .in_a_chain(a7_9to7_10), .in_b(b6_10to7_10), .in_c(matrixC6_10), .out_a(out_a_7_10_NC), .out_a_chain(a7_10to7_11), .out_b(b7_10to8_10), .out_b0(b7_10to8_10_ping), .out_b1(b7_10to8_10_pong), .out_c(matrixC7_10), .b_data_valid_ping(b_data_valid_ping_delay7_10), .b_data_valid_pong(b_data_valid_pong_delay7_10), .mode(1'b0)); +processing_element pe7_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_7_11_NC), .in_a_chain(a7_10to7_11), .in_b(b6_11to7_11), .in_c(matrixC6_11), .out_a(out_a_7_11_NC), .out_a_chain(a7_11to7_12), .out_b(b7_11to8_11), .out_b0(b7_11to8_11_ping), .out_b1(b7_11to8_11_pong), .out_c(matrixC7_11), .b_data_valid_ping(b_data_valid_ping_delay7_11), .b_data_valid_pong(b_data_valid_pong_delay7_11), .mode(1'b0)); +processing_element pe7_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_7_12_NC), .in_a_chain(a7_11to7_12), .in_b(b6_12to7_12), .in_c(matrixC6_12), .out_a(out_a_7_12_NC), .out_a_chain(a7_12to7_13), .out_b(b7_12to8_12), .out_b0(b7_12to8_12_ping), .out_b1(b7_12to8_12_pong), .out_c(matrixC7_12), .b_data_valid_ping(b_data_valid_ping_delay7_12), .b_data_valid_pong(b_data_valid_pong_delay7_12), .mode(1'b0)); +processing_element pe7_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_7_13_NC), .in_a_chain(a7_12to7_13), .in_b(b6_13to7_13), .in_c(matrixC6_13), .out_a(out_a_7_13_NC), .out_a_chain(a7_13to7_14), .out_b(b7_13to8_13), .out_b0(b7_13to8_13_ping), .out_b1(b7_13to8_13_pong), .out_c(matrixC7_13), .b_data_valid_ping(b_data_valid_ping_delay7_13), .b_data_valid_pong(b_data_valid_pong_delay7_13), .mode(1'b0)); +processing_element pe7_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_7_14_NC), .in_a_chain(a7_13to7_14), .in_b(b6_14to7_14), .in_c(matrixC6_14), .out_a(out_a_7_14_NC), .out_a_chain(a7_14to7_15), .out_b(b7_14to8_14), .out_b0(b7_14to8_14_ping), .out_b1(b7_14to8_14_pong), .out_c(matrixC7_14), .b_data_valid_ping(b_data_valid_ping_delay7_14), .b_data_valid_pong(b_data_valid_pong_delay7_14), .mode(1'b0)); +processing_element pe7_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_7_15_NC), .in_a_chain(a7_14to7_15), .in_b(b6_15to7_15), .in_c(matrixC6_15), .out_a(out_a_7_15_NC), .out_a_chain(a7_15to7_16), .out_b(b7_15to8_15), .out_b0(b7_15to8_15_ping), .out_b1(b7_15to8_15_pong), .out_c(matrixC7_15), .b_data_valid_ping(b_data_valid_ping_delay7_15), .b_data_valid_pong(b_data_valid_pong_delay7_15), .mode(1'b0)); +processing_element pe8_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay8), .in_a(a8), .in_a_chain(in_a_chain_8_0_NC), .in_b(b7_0to8_0), .in_c(matrixC7_0), .out_a(out_a_8_0_NC), .out_a_chain(a8_0to8_1), .out_b(b8_0to9_0), .out_b0(b8_0to9_0_ping), .out_b1(b8_0to9_0_pong), .out_c(matrixC8_0), .b_data_valid_ping(b_data_valid_ping_delay8_0), .b_data_valid_pong(b_data_valid_pong_delay8_0), .mode(1'b1)); +processing_element pe8_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(in_a_8_1_NC), .in_a_chain(a8_0to8_1), .in_b(b7_1to8_1), .in_c(matrixC7_1), .out_a(out_a_8_1_NC), .out_a_chain(a8_1to8_2), .out_b(b8_1to9_1), .out_b0(b8_1to9_1_ping), .out_b1(b8_1to9_1_pong), .out_c(matrixC8_1), .b_data_valid_ping(b_data_valid_ping_delay8_1), .b_data_valid_pong(b_data_valid_pong_delay8_1), .mode(1'b0)); +processing_element pe8_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_8_2_NC), .in_a_chain(a8_1to8_2), .in_b(b7_2to8_2), .in_c(matrixC7_2), .out_a(out_a_8_2_NC), .out_a_chain(a8_2to8_3), .out_b(b8_2to9_2), .out_b0(b8_2to9_2_ping), .out_b1(b8_2to9_2_pong), .out_c(matrixC8_2), .b_data_valid_ping(b_data_valid_ping_delay8_2), .b_data_valid_pong(b_data_valid_pong_delay8_2), .mode(1'b0)); +processing_element pe8_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_8_3_NC), .in_a_chain(a8_2to8_3), .in_b(b7_3to8_3), .in_c(matrixC7_3), .out_a(out_a_8_3_NC), .out_a_chain(a8_3to8_4), .out_b(b8_3to9_3), .out_b0(b8_3to9_3_ping), .out_b1(b8_3to9_3_pong), .out_c(matrixC8_3), .b_data_valid_ping(b_data_valid_ping_delay8_3), .b_data_valid_pong(b_data_valid_pong_delay8_3), .mode(1'b0)); +processing_element pe8_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_8_4_NC), .in_a_chain(a8_3to8_4), .in_b(b7_4to8_4), .in_c(matrixC7_4), .out_a(out_a_8_4_NC), .out_a_chain(a8_4to8_5), .out_b(b8_4to9_4), .out_b0(b8_4to9_4_ping), .out_b1(b8_4to9_4_pong), .out_c(matrixC8_4), .b_data_valid_ping(b_data_valid_ping_delay8_4), .b_data_valid_pong(b_data_valid_pong_delay8_4), .mode(1'b0)); +processing_element pe8_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_8_5_NC), .in_a_chain(a8_4to8_5), .in_b(b7_5to8_5), .in_c(matrixC7_5), .out_a(out_a_8_5_NC), .out_a_chain(a8_5to8_6), .out_b(b8_5to9_5), .out_b0(b8_5to9_5_ping), .out_b1(b8_5to9_5_pong), .out_c(matrixC8_5), .b_data_valid_ping(b_data_valid_ping_delay8_5), .b_data_valid_pong(b_data_valid_pong_delay8_5), .mode(1'b0)); +processing_element pe8_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_8_6_NC), .in_a_chain(a8_5to8_6), .in_b(b7_6to8_6), .in_c(matrixC7_6), .out_a(out_a_8_6_NC), .out_a_chain(a8_6to8_7), .out_b(b8_6to9_6), .out_b0(b8_6to9_6_ping), .out_b1(b8_6to9_6_pong), .out_c(matrixC8_6), .b_data_valid_ping(b_data_valid_ping_delay8_6), .b_data_valid_pong(b_data_valid_pong_delay8_6), .mode(1'b0)); +processing_element pe8_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_8_7_NC), .in_a_chain(a8_6to8_7), .in_b(b7_7to8_7), .in_c(matrixC7_7), .out_a(out_a_8_7_NC), .out_a_chain(a8_7to8_8), .out_b(b8_7to9_7), .out_b0(b8_7to9_7_ping), .out_b1(b8_7to9_7_pong), .out_c(matrixC8_7), .b_data_valid_ping(b_data_valid_ping_delay8_7), .b_data_valid_pong(b_data_valid_pong_delay8_7), .mode(1'b0)); +processing_element pe8_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_8_8_NC), .in_a_chain(a8_7to8_8), .in_b(b7_8to8_8), .in_c(matrixC7_8), .out_a(out_a_8_8_NC), .out_a_chain(a8_8to8_9), .out_b(b8_8to9_8), .out_b0(b8_8to9_8_ping), .out_b1(b8_8to9_8_pong), .out_c(matrixC8_8), .b_data_valid_ping(b_data_valid_ping_delay8_8), .b_data_valid_pong(b_data_valid_pong_delay8_8), .mode(1'b0)); +processing_element pe8_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_8_9_NC), .in_a_chain(a8_8to8_9), .in_b(b7_9to8_9), .in_c(matrixC7_9), .out_a(out_a_8_9_NC), .out_a_chain(a8_9to8_10), .out_b(b8_9to9_9), .out_b0(b8_9to9_9_ping), .out_b1(b8_9to9_9_pong), .out_c(matrixC8_9), .b_data_valid_ping(b_data_valid_ping_delay8_9), .b_data_valid_pong(b_data_valid_pong_delay8_9), .mode(1'b0)); +processing_element pe8_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_8_10_NC), .in_a_chain(a8_9to8_10), .in_b(b7_10to8_10), .in_c(matrixC7_10), .out_a(out_a_8_10_NC), .out_a_chain(a8_10to8_11), .out_b(b8_10to9_10), .out_b0(b8_10to9_10_ping), .out_b1(b8_10to9_10_pong), .out_c(matrixC8_10), .b_data_valid_ping(b_data_valid_ping_delay8_10), .b_data_valid_pong(b_data_valid_pong_delay8_10), .mode(1'b0)); +processing_element pe8_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_8_11_NC), .in_a_chain(a8_10to8_11), .in_b(b7_11to8_11), .in_c(matrixC7_11), .out_a(out_a_8_11_NC), .out_a_chain(a8_11to8_12), .out_b(b8_11to9_11), .out_b0(b8_11to9_11_ping), .out_b1(b8_11to9_11_pong), .out_c(matrixC8_11), .b_data_valid_ping(b_data_valid_ping_delay8_11), .b_data_valid_pong(b_data_valid_pong_delay8_11), .mode(1'b0)); +processing_element pe8_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_8_12_NC), .in_a_chain(a8_11to8_12), .in_b(b7_12to8_12), .in_c(matrixC7_12), .out_a(out_a_8_12_NC), .out_a_chain(a8_12to8_13), .out_b(b8_12to9_12), .out_b0(b8_12to9_12_ping), .out_b1(b8_12to9_12_pong), .out_c(matrixC8_12), .b_data_valid_ping(b_data_valid_ping_delay8_12), .b_data_valid_pong(b_data_valid_pong_delay8_12), .mode(1'b0)); +processing_element pe8_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_8_13_NC), .in_a_chain(a8_12to8_13), .in_b(b7_13to8_13), .in_c(matrixC7_13), .out_a(out_a_8_13_NC), .out_a_chain(a8_13to8_14), .out_b(b8_13to9_13), .out_b0(b8_13to9_13_ping), .out_b1(b8_13to9_13_pong), .out_c(matrixC8_13), .b_data_valid_ping(b_data_valid_ping_delay8_13), .b_data_valid_pong(b_data_valid_pong_delay8_13), .mode(1'b0)); +processing_element pe8_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_8_14_NC), .in_a_chain(a8_13to8_14), .in_b(b7_14to8_14), .in_c(matrixC7_14), .out_a(out_a_8_14_NC), .out_a_chain(a8_14to8_15), .out_b(b8_14to9_14), .out_b0(b8_14to9_14_ping), .out_b1(b8_14to9_14_pong), .out_c(matrixC8_14), .b_data_valid_ping(b_data_valid_ping_delay8_14), .b_data_valid_pong(b_data_valid_pong_delay8_14), .mode(1'b0)); +processing_element pe8_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_8_15_NC), .in_a_chain(a8_14to8_15), .in_b(b7_15to8_15), .in_c(matrixC7_15), .out_a(out_a_8_15_NC), .out_a_chain(a8_15to8_16), .out_b(b8_15to9_15), .out_b0(b8_15to9_15_ping), .out_b1(b8_15to9_15_pong), .out_c(matrixC8_15), .b_data_valid_ping(b_data_valid_ping_delay8_15), .b_data_valid_pong(b_data_valid_pong_delay8_15), .mode(1'b0)); +processing_element pe9_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay9), .in_a(a9), .in_a_chain(in_a_chain_9_0_NC), .in_b(b8_0to9_0), .in_c(matrixC8_0), .out_a(out_a_9_0_NC), .out_a_chain(a9_0to9_1), .out_b(b9_0to10_0), .out_b0(b9_0to10_0_ping), .out_b1(b9_0to10_0_pong), .out_c(matrixC9_0), .b_data_valid_ping(b_data_valid_ping_delay9_0), .b_data_valid_pong(b_data_valid_pong_delay9_0), .mode(1'b1)); +processing_element pe9_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(in_a_9_1_NC), .in_a_chain(a9_0to9_1), .in_b(b8_1to9_1), .in_c(matrixC8_1), .out_a(out_a_9_1_NC), .out_a_chain(a9_1to9_2), .out_b(b9_1to10_1), .out_b0(b9_1to10_1_ping), .out_b1(b9_1to10_1_pong), .out_c(matrixC9_1), .b_data_valid_ping(b_data_valid_ping_delay9_1), .b_data_valid_pong(b_data_valid_pong_delay9_1), .mode(1'b0)); +processing_element pe9_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_9_2_NC), .in_a_chain(a9_1to9_2), .in_b(b8_2to9_2), .in_c(matrixC8_2), .out_a(out_a_9_2_NC), .out_a_chain(a9_2to9_3), .out_b(b9_2to10_2), .out_b0(b9_2to10_2_ping), .out_b1(b9_2to10_2_pong), .out_c(matrixC9_2), .b_data_valid_ping(b_data_valid_ping_delay9_2), .b_data_valid_pong(b_data_valid_pong_delay9_2), .mode(1'b0)); +processing_element pe9_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_9_3_NC), .in_a_chain(a9_2to9_3), .in_b(b8_3to9_3), .in_c(matrixC8_3), .out_a(out_a_9_3_NC), .out_a_chain(a9_3to9_4), .out_b(b9_3to10_3), .out_b0(b9_3to10_3_ping), .out_b1(b9_3to10_3_pong), .out_c(matrixC9_3), .b_data_valid_ping(b_data_valid_ping_delay9_3), .b_data_valid_pong(b_data_valid_pong_delay9_3), .mode(1'b0)); +processing_element pe9_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_9_4_NC), .in_a_chain(a9_3to9_4), .in_b(b8_4to9_4), .in_c(matrixC8_4), .out_a(out_a_9_4_NC), .out_a_chain(a9_4to9_5), .out_b(b9_4to10_4), .out_b0(b9_4to10_4_ping), .out_b1(b9_4to10_4_pong), .out_c(matrixC9_4), .b_data_valid_ping(b_data_valid_ping_delay9_4), .b_data_valid_pong(b_data_valid_pong_delay9_4), .mode(1'b0)); +processing_element pe9_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_9_5_NC), .in_a_chain(a9_4to9_5), .in_b(b8_5to9_5), .in_c(matrixC8_5), .out_a(out_a_9_5_NC), .out_a_chain(a9_5to9_6), .out_b(b9_5to10_5), .out_b0(b9_5to10_5_ping), .out_b1(b9_5to10_5_pong), .out_c(matrixC9_5), .b_data_valid_ping(b_data_valid_ping_delay9_5), .b_data_valid_pong(b_data_valid_pong_delay9_5), .mode(1'b0)); +processing_element pe9_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_9_6_NC), .in_a_chain(a9_5to9_6), .in_b(b8_6to9_6), .in_c(matrixC8_6), .out_a(out_a_9_6_NC), .out_a_chain(a9_6to9_7), .out_b(b9_6to10_6), .out_b0(b9_6to10_6_ping), .out_b1(b9_6to10_6_pong), .out_c(matrixC9_6), .b_data_valid_ping(b_data_valid_ping_delay9_6), .b_data_valid_pong(b_data_valid_pong_delay9_6), .mode(1'b0)); +processing_element pe9_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_9_7_NC), .in_a_chain(a9_6to9_7), .in_b(b8_7to9_7), .in_c(matrixC8_7), .out_a(out_a_9_7_NC), .out_a_chain(a9_7to9_8), .out_b(b9_7to10_7), .out_b0(b9_7to10_7_ping), .out_b1(b9_7to10_7_pong), .out_c(matrixC9_7), .b_data_valid_ping(b_data_valid_ping_delay9_7), .b_data_valid_pong(b_data_valid_pong_delay9_7), .mode(1'b0)); +processing_element pe9_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_9_8_NC), .in_a_chain(a9_7to9_8), .in_b(b8_8to9_8), .in_c(matrixC8_8), .out_a(out_a_9_8_NC), .out_a_chain(a9_8to9_9), .out_b(b9_8to10_8), .out_b0(b9_8to10_8_ping), .out_b1(b9_8to10_8_pong), .out_c(matrixC9_8), .b_data_valid_ping(b_data_valid_ping_delay9_8), .b_data_valid_pong(b_data_valid_pong_delay9_8), .mode(1'b0)); +processing_element pe9_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_9_9_NC), .in_a_chain(a9_8to9_9), .in_b(b8_9to9_9), .in_c(matrixC8_9), .out_a(out_a_9_9_NC), .out_a_chain(a9_9to9_10), .out_b(b9_9to10_9), .out_b0(b9_9to10_9_ping), .out_b1(b9_9to10_9_pong), .out_c(matrixC9_9), .b_data_valid_ping(b_data_valid_ping_delay9_9), .b_data_valid_pong(b_data_valid_pong_delay9_9), .mode(1'b0)); +processing_element pe9_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_9_10_NC), .in_a_chain(a9_9to9_10), .in_b(b8_10to9_10), .in_c(matrixC8_10), .out_a(out_a_9_10_NC), .out_a_chain(a9_10to9_11), .out_b(b9_10to10_10), .out_b0(b9_10to10_10_ping), .out_b1(b9_10to10_10_pong), .out_c(matrixC9_10), .b_data_valid_ping(b_data_valid_ping_delay9_10), .b_data_valid_pong(b_data_valid_pong_delay9_10), .mode(1'b0)); +processing_element pe9_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_9_11_NC), .in_a_chain(a9_10to9_11), .in_b(b8_11to9_11), .in_c(matrixC8_11), .out_a(out_a_9_11_NC), .out_a_chain(a9_11to9_12), .out_b(b9_11to10_11), .out_b0(b9_11to10_11_ping), .out_b1(b9_11to10_11_pong), .out_c(matrixC9_11), .b_data_valid_ping(b_data_valid_ping_delay9_11), .b_data_valid_pong(b_data_valid_pong_delay9_11), .mode(1'b0)); +processing_element pe9_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_9_12_NC), .in_a_chain(a9_11to9_12), .in_b(b8_12to9_12), .in_c(matrixC8_12), .out_a(out_a_9_12_NC), .out_a_chain(a9_12to9_13), .out_b(b9_12to10_12), .out_b0(b9_12to10_12_ping), .out_b1(b9_12to10_12_pong), .out_c(matrixC9_12), .b_data_valid_ping(b_data_valid_ping_delay9_12), .b_data_valid_pong(b_data_valid_pong_delay9_12), .mode(1'b0)); +processing_element pe9_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_9_13_NC), .in_a_chain(a9_12to9_13), .in_b(b8_13to9_13), .in_c(matrixC8_13), .out_a(out_a_9_13_NC), .out_a_chain(a9_13to9_14), .out_b(b9_13to10_13), .out_b0(b9_13to10_13_ping), .out_b1(b9_13to10_13_pong), .out_c(matrixC9_13), .b_data_valid_ping(b_data_valid_ping_delay9_13), .b_data_valid_pong(b_data_valid_pong_delay9_13), .mode(1'b0)); +processing_element pe9_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_9_14_NC), .in_a_chain(a9_13to9_14), .in_b(b8_14to9_14), .in_c(matrixC8_14), .out_a(out_a_9_14_NC), .out_a_chain(a9_14to9_15), .out_b(b9_14to10_14), .out_b0(b9_14to10_14_ping), .out_b1(b9_14to10_14_pong), .out_c(matrixC9_14), .b_data_valid_ping(b_data_valid_ping_delay9_14), .b_data_valid_pong(b_data_valid_pong_delay9_14), .mode(1'b0)); +processing_element pe9_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_9_15_NC), .in_a_chain(a9_14to9_15), .in_b(b8_15to9_15), .in_c(matrixC8_15), .out_a(out_a_9_15_NC), .out_a_chain(a9_15to9_16), .out_b(b9_15to10_15), .out_b0(b9_15to10_15_ping), .out_b1(b9_15to10_15_pong), .out_c(matrixC9_15), .b_data_valid_ping(b_data_valid_ping_delay9_15), .b_data_valid_pong(b_data_valid_pong_delay9_15), .mode(1'b0)); +processing_element pe10_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay10), .in_a(a10), .in_a_chain(in_a_chain_10_0_NC), .in_b(b9_0to10_0), .in_c(matrixC9_0), .out_a(out_a_10_0_NC), .out_a_chain(a10_0to10_1), .out_b(b10_0to11_0), .out_b0(b10_0to11_0_ping), .out_b1(b10_0to11_0_pong), .out_c(matrixC10_0), .b_data_valid_ping(b_data_valid_ping_delay10_0), .b_data_valid_pong(b_data_valid_pong_delay10_0), .mode(1'b1)); +processing_element pe10_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(in_a_10_1_NC), .in_a_chain(a10_0to10_1), .in_b(b9_1to10_1), .in_c(matrixC9_1), .out_a(out_a_10_1_NC), .out_a_chain(a10_1to10_2), .out_b(b10_1to11_1), .out_b0(b10_1to11_1_ping), .out_b1(b10_1to11_1_pong), .out_c(matrixC10_1), .b_data_valid_ping(b_data_valid_ping_delay10_1), .b_data_valid_pong(b_data_valid_pong_delay10_1), .mode(1'b0)); +processing_element pe10_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_10_2_NC), .in_a_chain(a10_1to10_2), .in_b(b9_2to10_2), .in_c(matrixC9_2), .out_a(out_a_10_2_NC), .out_a_chain(a10_2to10_3), .out_b(b10_2to11_2), .out_b0(b10_2to11_2_ping), .out_b1(b10_2to11_2_pong), .out_c(matrixC10_2), .b_data_valid_ping(b_data_valid_ping_delay10_2), .b_data_valid_pong(b_data_valid_pong_delay10_2), .mode(1'b0)); +processing_element pe10_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_10_3_NC), .in_a_chain(a10_2to10_3), .in_b(b9_3to10_3), .in_c(matrixC9_3), .out_a(out_a_10_3_NC), .out_a_chain(a10_3to10_4), .out_b(b10_3to11_3), .out_b0(b10_3to11_3_ping), .out_b1(b10_3to11_3_pong), .out_c(matrixC10_3), .b_data_valid_ping(b_data_valid_ping_delay10_3), .b_data_valid_pong(b_data_valid_pong_delay10_3), .mode(1'b0)); +processing_element pe10_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_10_4_NC), .in_a_chain(a10_3to10_4), .in_b(b9_4to10_4), .in_c(matrixC9_4), .out_a(out_a_10_4_NC), .out_a_chain(a10_4to10_5), .out_b(b10_4to11_4), .out_b0(b10_4to11_4_ping), .out_b1(b10_4to11_4_pong), .out_c(matrixC10_4), .b_data_valid_ping(b_data_valid_ping_delay10_4), .b_data_valid_pong(b_data_valid_pong_delay10_4), .mode(1'b0)); +processing_element pe10_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_10_5_NC), .in_a_chain(a10_4to10_5), .in_b(b9_5to10_5), .in_c(matrixC9_5), .out_a(out_a_10_5_NC), .out_a_chain(a10_5to10_6), .out_b(b10_5to11_5), .out_b0(b10_5to11_5_ping), .out_b1(b10_5to11_5_pong), .out_c(matrixC10_5), .b_data_valid_ping(b_data_valid_ping_delay10_5), .b_data_valid_pong(b_data_valid_pong_delay10_5), .mode(1'b0)); +processing_element pe10_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_10_6_NC), .in_a_chain(a10_5to10_6), .in_b(b9_6to10_6), .in_c(matrixC9_6), .out_a(out_a_10_6_NC), .out_a_chain(a10_6to10_7), .out_b(b10_6to11_6), .out_b0(b10_6to11_6_ping), .out_b1(b10_6to11_6_pong), .out_c(matrixC10_6), .b_data_valid_ping(b_data_valid_ping_delay10_6), .b_data_valid_pong(b_data_valid_pong_delay10_6), .mode(1'b0)); +processing_element pe10_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_10_7_NC), .in_a_chain(a10_6to10_7), .in_b(b9_7to10_7), .in_c(matrixC9_7), .out_a(out_a_10_7_NC), .out_a_chain(a10_7to10_8), .out_b(b10_7to11_7), .out_b0(b10_7to11_7_ping), .out_b1(b10_7to11_7_pong), .out_c(matrixC10_7), .b_data_valid_ping(b_data_valid_ping_delay10_7), .b_data_valid_pong(b_data_valid_pong_delay10_7), .mode(1'b0)); +processing_element pe10_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_10_8_NC), .in_a_chain(a10_7to10_8), .in_b(b9_8to10_8), .in_c(matrixC9_8), .out_a(out_a_10_8_NC), .out_a_chain(a10_8to10_9), .out_b(b10_8to11_8), .out_b0(b10_8to11_8_ping), .out_b1(b10_8to11_8_pong), .out_c(matrixC10_8), .b_data_valid_ping(b_data_valid_ping_delay10_8), .b_data_valid_pong(b_data_valid_pong_delay10_8), .mode(1'b0)); +processing_element pe10_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_10_9_NC), .in_a_chain(a10_8to10_9), .in_b(b9_9to10_9), .in_c(matrixC9_9), .out_a(out_a_10_9_NC), .out_a_chain(a10_9to10_10), .out_b(b10_9to11_9), .out_b0(b10_9to11_9_ping), .out_b1(b10_9to11_9_pong), .out_c(matrixC10_9), .b_data_valid_ping(b_data_valid_ping_delay10_9), .b_data_valid_pong(b_data_valid_pong_delay10_9), .mode(1'b0)); +processing_element pe10_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_10_10_NC), .in_a_chain(a10_9to10_10), .in_b(b9_10to10_10), .in_c(matrixC9_10), .out_a(out_a_10_10_NC), .out_a_chain(a10_10to10_11), .out_b(b10_10to11_10), .out_b0(b10_10to11_10_ping), .out_b1(b10_10to11_10_pong), .out_c(matrixC10_10), .b_data_valid_ping(b_data_valid_ping_delay10_10), .b_data_valid_pong(b_data_valid_pong_delay10_10), .mode(1'b0)); +processing_element pe10_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_10_11_NC), .in_a_chain(a10_10to10_11), .in_b(b9_11to10_11), .in_c(matrixC9_11), .out_a(out_a_10_11_NC), .out_a_chain(a10_11to10_12), .out_b(b10_11to11_11), .out_b0(b10_11to11_11_ping), .out_b1(b10_11to11_11_pong), .out_c(matrixC10_11), .b_data_valid_ping(b_data_valid_ping_delay10_11), .b_data_valid_pong(b_data_valid_pong_delay10_11), .mode(1'b0)); +processing_element pe10_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_10_12_NC), .in_a_chain(a10_11to10_12), .in_b(b9_12to10_12), .in_c(matrixC9_12), .out_a(out_a_10_12_NC), .out_a_chain(a10_12to10_13), .out_b(b10_12to11_12), .out_b0(b10_12to11_12_ping), .out_b1(b10_12to11_12_pong), .out_c(matrixC10_12), .b_data_valid_ping(b_data_valid_ping_delay10_12), .b_data_valid_pong(b_data_valid_pong_delay10_12), .mode(1'b0)); +processing_element pe10_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_10_13_NC), .in_a_chain(a10_12to10_13), .in_b(b9_13to10_13), .in_c(matrixC9_13), .out_a(out_a_10_13_NC), .out_a_chain(a10_13to10_14), .out_b(b10_13to11_13), .out_b0(b10_13to11_13_ping), .out_b1(b10_13to11_13_pong), .out_c(matrixC10_13), .b_data_valid_ping(b_data_valid_ping_delay10_13), .b_data_valid_pong(b_data_valid_pong_delay10_13), .mode(1'b0)); +processing_element pe10_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_10_14_NC), .in_a_chain(a10_13to10_14), .in_b(b9_14to10_14), .in_c(matrixC9_14), .out_a(out_a_10_14_NC), .out_a_chain(a10_14to10_15), .out_b(b10_14to11_14), .out_b0(b10_14to11_14_ping), .out_b1(b10_14to11_14_pong), .out_c(matrixC10_14), .b_data_valid_ping(b_data_valid_ping_delay10_14), .b_data_valid_pong(b_data_valid_pong_delay10_14), .mode(1'b0)); +processing_element pe10_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_10_15_NC), .in_a_chain(a10_14to10_15), .in_b(b9_15to10_15), .in_c(matrixC9_15), .out_a(out_a_10_15_NC), .out_a_chain(a10_15to10_16), .out_b(b10_15to11_15), .out_b0(b10_15to11_15_ping), .out_b1(b10_15to11_15_pong), .out_c(matrixC10_15), .b_data_valid_ping(b_data_valid_ping_delay10_15), .b_data_valid_pong(b_data_valid_pong_delay10_15), .mode(1'b0)); +processing_element pe11_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay11), .in_a(a11), .in_a_chain(in_a_chain_11_0_NC), .in_b(b10_0to11_0), .in_c(matrixC10_0), .out_a(out_a_11_0_NC), .out_a_chain(a11_0to11_1), .out_b(b11_0to12_0), .out_b0(b11_0to12_0_ping), .out_b1(b11_0to12_0_pong), .out_c(matrixC11_0), .b_data_valid_ping(b_data_valid_ping_delay11_0), .b_data_valid_pong(b_data_valid_pong_delay11_0), .mode(1'b1)); +processing_element pe11_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(in_a_11_1_NC), .in_a_chain(a11_0to11_1), .in_b(b10_1to11_1), .in_c(matrixC10_1), .out_a(out_a_11_1_NC), .out_a_chain(a11_1to11_2), .out_b(b11_1to12_1), .out_b0(b11_1to12_1_ping), .out_b1(b11_1to12_1_pong), .out_c(matrixC11_1), .b_data_valid_ping(b_data_valid_ping_delay11_1), .b_data_valid_pong(b_data_valid_pong_delay11_1), .mode(1'b0)); +processing_element pe11_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_11_2_NC), .in_a_chain(a11_1to11_2), .in_b(b10_2to11_2), .in_c(matrixC10_2), .out_a(out_a_11_2_NC), .out_a_chain(a11_2to11_3), .out_b(b11_2to12_2), .out_b0(b11_2to12_2_ping), .out_b1(b11_2to12_2_pong), .out_c(matrixC11_2), .b_data_valid_ping(b_data_valid_ping_delay11_2), .b_data_valid_pong(b_data_valid_pong_delay11_2), .mode(1'b0)); +processing_element pe11_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_11_3_NC), .in_a_chain(a11_2to11_3), .in_b(b10_3to11_3), .in_c(matrixC10_3), .out_a(out_a_11_3_NC), .out_a_chain(a11_3to11_4), .out_b(b11_3to12_3), .out_b0(b11_3to12_3_ping), .out_b1(b11_3to12_3_pong), .out_c(matrixC11_3), .b_data_valid_ping(b_data_valid_ping_delay11_3), .b_data_valid_pong(b_data_valid_pong_delay11_3), .mode(1'b0)); +processing_element pe11_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_11_4_NC), .in_a_chain(a11_3to11_4), .in_b(b10_4to11_4), .in_c(matrixC10_4), .out_a(out_a_11_4_NC), .out_a_chain(a11_4to11_5), .out_b(b11_4to12_4), .out_b0(b11_4to12_4_ping), .out_b1(b11_4to12_4_pong), .out_c(matrixC11_4), .b_data_valid_ping(b_data_valid_ping_delay11_4), .b_data_valid_pong(b_data_valid_pong_delay11_4), .mode(1'b0)); +processing_element pe11_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_11_5_NC), .in_a_chain(a11_4to11_5), .in_b(b10_5to11_5), .in_c(matrixC10_5), .out_a(out_a_11_5_NC), .out_a_chain(a11_5to11_6), .out_b(b11_5to12_5), .out_b0(b11_5to12_5_ping), .out_b1(b11_5to12_5_pong), .out_c(matrixC11_5), .b_data_valid_ping(b_data_valid_ping_delay11_5), .b_data_valid_pong(b_data_valid_pong_delay11_5), .mode(1'b0)); +processing_element pe11_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_11_6_NC), .in_a_chain(a11_5to11_6), .in_b(b10_6to11_6), .in_c(matrixC10_6), .out_a(out_a_11_6_NC), .out_a_chain(a11_6to11_7), .out_b(b11_6to12_6), .out_b0(b11_6to12_6_ping), .out_b1(b11_6to12_6_pong), .out_c(matrixC11_6), .b_data_valid_ping(b_data_valid_ping_delay11_6), .b_data_valid_pong(b_data_valid_pong_delay11_6), .mode(1'b0)); +processing_element pe11_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_11_7_NC), .in_a_chain(a11_6to11_7), .in_b(b10_7to11_7), .in_c(matrixC10_7), .out_a(out_a_11_7_NC), .out_a_chain(a11_7to11_8), .out_b(b11_7to12_7), .out_b0(b11_7to12_7_ping), .out_b1(b11_7to12_7_pong), .out_c(matrixC11_7), .b_data_valid_ping(b_data_valid_ping_delay11_7), .b_data_valid_pong(b_data_valid_pong_delay11_7), .mode(1'b0)); +processing_element pe11_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_11_8_NC), .in_a_chain(a11_7to11_8), .in_b(b10_8to11_8), .in_c(matrixC10_8), .out_a(out_a_11_8_NC), .out_a_chain(a11_8to11_9), .out_b(b11_8to12_8), .out_b0(b11_8to12_8_ping), .out_b1(b11_8to12_8_pong), .out_c(matrixC11_8), .b_data_valid_ping(b_data_valid_ping_delay11_8), .b_data_valid_pong(b_data_valid_pong_delay11_8), .mode(1'b0)); +processing_element pe11_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_11_9_NC), .in_a_chain(a11_8to11_9), .in_b(b10_9to11_9), .in_c(matrixC10_9), .out_a(out_a_11_9_NC), .out_a_chain(a11_9to11_10), .out_b(b11_9to12_9), .out_b0(b11_9to12_9_ping), .out_b1(b11_9to12_9_pong), .out_c(matrixC11_9), .b_data_valid_ping(b_data_valid_ping_delay11_9), .b_data_valid_pong(b_data_valid_pong_delay11_9), .mode(1'b0)); +processing_element pe11_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_11_10_NC), .in_a_chain(a11_9to11_10), .in_b(b10_10to11_10), .in_c(matrixC10_10), .out_a(out_a_11_10_NC), .out_a_chain(a11_10to11_11), .out_b(b11_10to12_10), .out_b0(b11_10to12_10_ping), .out_b1(b11_10to12_10_pong), .out_c(matrixC11_10), .b_data_valid_ping(b_data_valid_ping_delay11_10), .b_data_valid_pong(b_data_valid_pong_delay11_10), .mode(1'b0)); +processing_element pe11_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_11_11_NC), .in_a_chain(a11_10to11_11), .in_b(b10_11to11_11), .in_c(matrixC10_11), .out_a(out_a_11_11_NC), .out_a_chain(a11_11to11_12), .out_b(b11_11to12_11), .out_b0(b11_11to12_11_ping), .out_b1(b11_11to12_11_pong), .out_c(matrixC11_11), .b_data_valid_ping(b_data_valid_ping_delay11_11), .b_data_valid_pong(b_data_valid_pong_delay11_11), .mode(1'b0)); +processing_element pe11_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_11_12_NC), .in_a_chain(a11_11to11_12), .in_b(b10_12to11_12), .in_c(matrixC10_12), .out_a(out_a_11_12_NC), .out_a_chain(a11_12to11_13), .out_b(b11_12to12_12), .out_b0(b11_12to12_12_ping), .out_b1(b11_12to12_12_pong), .out_c(matrixC11_12), .b_data_valid_ping(b_data_valid_ping_delay11_12), .b_data_valid_pong(b_data_valid_pong_delay11_12), .mode(1'b0)); +processing_element pe11_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_11_13_NC), .in_a_chain(a11_12to11_13), .in_b(b10_13to11_13), .in_c(matrixC10_13), .out_a(out_a_11_13_NC), .out_a_chain(a11_13to11_14), .out_b(b11_13to12_13), .out_b0(b11_13to12_13_ping), .out_b1(b11_13to12_13_pong), .out_c(matrixC11_13), .b_data_valid_ping(b_data_valid_ping_delay11_13), .b_data_valid_pong(b_data_valid_pong_delay11_13), .mode(1'b0)); +processing_element pe11_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_11_14_NC), .in_a_chain(a11_13to11_14), .in_b(b10_14to11_14), .in_c(matrixC10_14), .out_a(out_a_11_14_NC), .out_a_chain(a11_14to11_15), .out_b(b11_14to12_14), .out_b0(b11_14to12_14_ping), .out_b1(b11_14to12_14_pong), .out_c(matrixC11_14), .b_data_valid_ping(b_data_valid_ping_delay11_14), .b_data_valid_pong(b_data_valid_pong_delay11_14), .mode(1'b0)); +processing_element pe11_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_11_15_NC), .in_a_chain(a11_14to11_15), .in_b(b10_15to11_15), .in_c(matrixC10_15), .out_a(out_a_11_15_NC), .out_a_chain(a11_15to11_16), .out_b(b11_15to12_15), .out_b0(b11_15to12_15_ping), .out_b1(b11_15to12_15_pong), .out_c(matrixC11_15), .b_data_valid_ping(b_data_valid_ping_delay11_15), .b_data_valid_pong(b_data_valid_pong_delay11_15), .mode(1'b0)); +processing_element pe12_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay12), .in_a(a12), .in_a_chain(in_a_chain_12_0_NC), .in_b(b11_0to12_0), .in_c(matrixC11_0), .out_a(out_a_12_0_NC), .out_a_chain(a12_0to12_1), .out_b(b12_0to13_0), .out_b0(b12_0to13_0_ping), .out_b1(b12_0to13_0_pong), .out_c(matrixC12_0), .b_data_valid_ping(b_data_valid_ping_delay12_0), .b_data_valid_pong(b_data_valid_pong_delay12_0), .mode(1'b1)); +processing_element pe12_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(in_a_12_1_NC), .in_a_chain(a12_0to12_1), .in_b(b11_1to12_1), .in_c(matrixC11_1), .out_a(out_a_12_1_NC), .out_a_chain(a12_1to12_2), .out_b(b12_1to13_1), .out_b0(b12_1to13_1_ping), .out_b1(b12_1to13_1_pong), .out_c(matrixC12_1), .b_data_valid_ping(b_data_valid_ping_delay12_1), .b_data_valid_pong(b_data_valid_pong_delay12_1), .mode(1'b0)); +processing_element pe12_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_12_2_NC), .in_a_chain(a12_1to12_2), .in_b(b11_2to12_2), .in_c(matrixC11_2), .out_a(out_a_12_2_NC), .out_a_chain(a12_2to12_3), .out_b(b12_2to13_2), .out_b0(b12_2to13_2_ping), .out_b1(b12_2to13_2_pong), .out_c(matrixC12_2), .b_data_valid_ping(b_data_valid_ping_delay12_2), .b_data_valid_pong(b_data_valid_pong_delay12_2), .mode(1'b0)); +processing_element pe12_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_12_3_NC), .in_a_chain(a12_2to12_3), .in_b(b11_3to12_3), .in_c(matrixC11_3), .out_a(out_a_12_3_NC), .out_a_chain(a12_3to12_4), .out_b(b12_3to13_3), .out_b0(b12_3to13_3_ping), .out_b1(b12_3to13_3_pong), .out_c(matrixC12_3), .b_data_valid_ping(b_data_valid_ping_delay12_3), .b_data_valid_pong(b_data_valid_pong_delay12_3), .mode(1'b0)); +processing_element pe12_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_12_4_NC), .in_a_chain(a12_3to12_4), .in_b(b11_4to12_4), .in_c(matrixC11_4), .out_a(out_a_12_4_NC), .out_a_chain(a12_4to12_5), .out_b(b12_4to13_4), .out_b0(b12_4to13_4_ping), .out_b1(b12_4to13_4_pong), .out_c(matrixC12_4), .b_data_valid_ping(b_data_valid_ping_delay12_4), .b_data_valid_pong(b_data_valid_pong_delay12_4), .mode(1'b0)); +processing_element pe12_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_12_5_NC), .in_a_chain(a12_4to12_5), .in_b(b11_5to12_5), .in_c(matrixC11_5), .out_a(out_a_12_5_NC), .out_a_chain(a12_5to12_6), .out_b(b12_5to13_5), .out_b0(b12_5to13_5_ping), .out_b1(b12_5to13_5_pong), .out_c(matrixC12_5), .b_data_valid_ping(b_data_valid_ping_delay12_5), .b_data_valid_pong(b_data_valid_pong_delay12_5), .mode(1'b0)); +processing_element pe12_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_12_6_NC), .in_a_chain(a12_5to12_6), .in_b(b11_6to12_6), .in_c(matrixC11_6), .out_a(out_a_12_6_NC), .out_a_chain(a12_6to12_7), .out_b(b12_6to13_6), .out_b0(b12_6to13_6_ping), .out_b1(b12_6to13_6_pong), .out_c(matrixC12_6), .b_data_valid_ping(b_data_valid_ping_delay12_6), .b_data_valid_pong(b_data_valid_pong_delay12_6), .mode(1'b0)); +processing_element pe12_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_12_7_NC), .in_a_chain(a12_6to12_7), .in_b(b11_7to12_7), .in_c(matrixC11_7), .out_a(out_a_12_7_NC), .out_a_chain(a12_7to12_8), .out_b(b12_7to13_7), .out_b0(b12_7to13_7_ping), .out_b1(b12_7to13_7_pong), .out_c(matrixC12_7), .b_data_valid_ping(b_data_valid_ping_delay12_7), .b_data_valid_pong(b_data_valid_pong_delay12_7), .mode(1'b0)); +processing_element pe12_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_12_8_NC), .in_a_chain(a12_7to12_8), .in_b(b11_8to12_8), .in_c(matrixC11_8), .out_a(out_a_12_8_NC), .out_a_chain(a12_8to12_9), .out_b(b12_8to13_8), .out_b0(b12_8to13_8_ping), .out_b1(b12_8to13_8_pong), .out_c(matrixC12_8), .b_data_valid_ping(b_data_valid_ping_delay12_8), .b_data_valid_pong(b_data_valid_pong_delay12_8), .mode(1'b0)); +processing_element pe12_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_12_9_NC), .in_a_chain(a12_8to12_9), .in_b(b11_9to12_9), .in_c(matrixC11_9), .out_a(out_a_12_9_NC), .out_a_chain(a12_9to12_10), .out_b(b12_9to13_9), .out_b0(b12_9to13_9_ping), .out_b1(b12_9to13_9_pong), .out_c(matrixC12_9), .b_data_valid_ping(b_data_valid_ping_delay12_9), .b_data_valid_pong(b_data_valid_pong_delay12_9), .mode(1'b0)); +processing_element pe12_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_12_10_NC), .in_a_chain(a12_9to12_10), .in_b(b11_10to12_10), .in_c(matrixC11_10), .out_a(out_a_12_10_NC), .out_a_chain(a12_10to12_11), .out_b(b12_10to13_10), .out_b0(b12_10to13_10_ping), .out_b1(b12_10to13_10_pong), .out_c(matrixC12_10), .b_data_valid_ping(b_data_valid_ping_delay12_10), .b_data_valid_pong(b_data_valid_pong_delay12_10), .mode(1'b0)); +processing_element pe12_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_12_11_NC), .in_a_chain(a12_10to12_11), .in_b(b11_11to12_11), .in_c(matrixC11_11), .out_a(out_a_12_11_NC), .out_a_chain(a12_11to12_12), .out_b(b12_11to13_11), .out_b0(b12_11to13_11_ping), .out_b1(b12_11to13_11_pong), .out_c(matrixC12_11), .b_data_valid_ping(b_data_valid_ping_delay12_11), .b_data_valid_pong(b_data_valid_pong_delay12_11), .mode(1'b0)); +processing_element pe12_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_12_12_NC), .in_a_chain(a12_11to12_12), .in_b(b11_12to12_12), .in_c(matrixC11_12), .out_a(out_a_12_12_NC), .out_a_chain(a12_12to12_13), .out_b(b12_12to13_12), .out_b0(b12_12to13_12_ping), .out_b1(b12_12to13_12_pong), .out_c(matrixC12_12), .b_data_valid_ping(b_data_valid_ping_delay12_12), .b_data_valid_pong(b_data_valid_pong_delay12_12), .mode(1'b0)); +processing_element pe12_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_12_13_NC), .in_a_chain(a12_12to12_13), .in_b(b11_13to12_13), .in_c(matrixC11_13), .out_a(out_a_12_13_NC), .out_a_chain(a12_13to12_14), .out_b(b12_13to13_13), .out_b0(b12_13to13_13_ping), .out_b1(b12_13to13_13_pong), .out_c(matrixC12_13), .b_data_valid_ping(b_data_valid_ping_delay12_13), .b_data_valid_pong(b_data_valid_pong_delay12_13), .mode(1'b0)); +processing_element pe12_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_12_14_NC), .in_a_chain(a12_13to12_14), .in_b(b11_14to12_14), .in_c(matrixC11_14), .out_a(out_a_12_14_NC), .out_a_chain(a12_14to12_15), .out_b(b12_14to13_14), .out_b0(b12_14to13_14_ping), .out_b1(b12_14to13_14_pong), .out_c(matrixC12_14), .b_data_valid_ping(b_data_valid_ping_delay12_14), .b_data_valid_pong(b_data_valid_pong_delay12_14), .mode(1'b0)); +processing_element pe12_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_12_15_NC), .in_a_chain(a12_14to12_15), .in_b(b11_15to12_15), .in_c(matrixC11_15), .out_a(out_a_12_15_NC), .out_a_chain(a12_15to12_16), .out_b(b12_15to13_15), .out_b0(b12_15to13_15_ping), .out_b1(b12_15to13_15_pong), .out_c(matrixC12_15), .b_data_valid_ping(b_data_valid_ping_delay12_15), .b_data_valid_pong(b_data_valid_pong_delay12_15), .mode(1'b0)); +processing_element pe13_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay13), .in_a(a13), .in_a_chain(in_a_chain_13_0_NC), .in_b(b12_0to13_0), .in_c(matrixC12_0), .out_a(out_a_13_0_NC), .out_a_chain(a13_0to13_1), .out_b(b13_0to14_0), .out_b0(b13_0to14_0_ping), .out_b1(b13_0to14_0_pong), .out_c(matrixC13_0), .b_data_valid_ping(b_data_valid_ping_delay13_0), .b_data_valid_pong(b_data_valid_pong_delay13_0), .mode(1'b1)); +processing_element pe13_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(in_a_13_1_NC), .in_a_chain(a13_0to13_1), .in_b(b12_1to13_1), .in_c(matrixC12_1), .out_a(out_a_13_1_NC), .out_a_chain(a13_1to13_2), .out_b(b13_1to14_1), .out_b0(b13_1to14_1_ping), .out_b1(b13_1to14_1_pong), .out_c(matrixC13_1), .b_data_valid_ping(b_data_valid_ping_delay13_1), .b_data_valid_pong(b_data_valid_pong_delay13_1), .mode(1'b0)); +processing_element pe13_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_13_2_NC), .in_a_chain(a13_1to13_2), .in_b(b12_2to13_2), .in_c(matrixC12_2), .out_a(out_a_13_2_NC), .out_a_chain(a13_2to13_3), .out_b(b13_2to14_2), .out_b0(b13_2to14_2_ping), .out_b1(b13_2to14_2_pong), .out_c(matrixC13_2), .b_data_valid_ping(b_data_valid_ping_delay13_2), .b_data_valid_pong(b_data_valid_pong_delay13_2), .mode(1'b0)); +processing_element pe13_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_13_3_NC), .in_a_chain(a13_2to13_3), .in_b(b12_3to13_3), .in_c(matrixC12_3), .out_a(out_a_13_3_NC), .out_a_chain(a13_3to13_4), .out_b(b13_3to14_3), .out_b0(b13_3to14_3_ping), .out_b1(b13_3to14_3_pong), .out_c(matrixC13_3), .b_data_valid_ping(b_data_valid_ping_delay13_3), .b_data_valid_pong(b_data_valid_pong_delay13_3), .mode(1'b0)); +processing_element pe13_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_13_4_NC), .in_a_chain(a13_3to13_4), .in_b(b12_4to13_4), .in_c(matrixC12_4), .out_a(out_a_13_4_NC), .out_a_chain(a13_4to13_5), .out_b(b13_4to14_4), .out_b0(b13_4to14_4_ping), .out_b1(b13_4to14_4_pong), .out_c(matrixC13_4), .b_data_valid_ping(b_data_valid_ping_delay13_4), .b_data_valid_pong(b_data_valid_pong_delay13_4), .mode(1'b0)); +processing_element pe13_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_13_5_NC), .in_a_chain(a13_4to13_5), .in_b(b12_5to13_5), .in_c(matrixC12_5), .out_a(out_a_13_5_NC), .out_a_chain(a13_5to13_6), .out_b(b13_5to14_5), .out_b0(b13_5to14_5_ping), .out_b1(b13_5to14_5_pong), .out_c(matrixC13_5), .b_data_valid_ping(b_data_valid_ping_delay13_5), .b_data_valid_pong(b_data_valid_pong_delay13_5), .mode(1'b0)); +processing_element pe13_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_13_6_NC), .in_a_chain(a13_5to13_6), .in_b(b12_6to13_6), .in_c(matrixC12_6), .out_a(out_a_13_6_NC), .out_a_chain(a13_6to13_7), .out_b(b13_6to14_6), .out_b0(b13_6to14_6_ping), .out_b1(b13_6to14_6_pong), .out_c(matrixC13_6), .b_data_valid_ping(b_data_valid_ping_delay13_6), .b_data_valid_pong(b_data_valid_pong_delay13_6), .mode(1'b0)); +processing_element pe13_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_13_7_NC), .in_a_chain(a13_6to13_7), .in_b(b12_7to13_7), .in_c(matrixC12_7), .out_a(out_a_13_7_NC), .out_a_chain(a13_7to13_8), .out_b(b13_7to14_7), .out_b0(b13_7to14_7_ping), .out_b1(b13_7to14_7_pong), .out_c(matrixC13_7), .b_data_valid_ping(b_data_valid_ping_delay13_7), .b_data_valid_pong(b_data_valid_pong_delay13_7), .mode(1'b0)); +processing_element pe13_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_13_8_NC), .in_a_chain(a13_7to13_8), .in_b(b12_8to13_8), .in_c(matrixC12_8), .out_a(out_a_13_8_NC), .out_a_chain(a13_8to13_9), .out_b(b13_8to14_8), .out_b0(b13_8to14_8_ping), .out_b1(b13_8to14_8_pong), .out_c(matrixC13_8), .b_data_valid_ping(b_data_valid_ping_delay13_8), .b_data_valid_pong(b_data_valid_pong_delay13_8), .mode(1'b0)); +processing_element pe13_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_13_9_NC), .in_a_chain(a13_8to13_9), .in_b(b12_9to13_9), .in_c(matrixC12_9), .out_a(out_a_13_9_NC), .out_a_chain(a13_9to13_10), .out_b(b13_9to14_9), .out_b0(b13_9to14_9_ping), .out_b1(b13_9to14_9_pong), .out_c(matrixC13_9), .b_data_valid_ping(b_data_valid_ping_delay13_9), .b_data_valid_pong(b_data_valid_pong_delay13_9), .mode(1'b0)); +processing_element pe13_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_13_10_NC), .in_a_chain(a13_9to13_10), .in_b(b12_10to13_10), .in_c(matrixC12_10), .out_a(out_a_13_10_NC), .out_a_chain(a13_10to13_11), .out_b(b13_10to14_10), .out_b0(b13_10to14_10_ping), .out_b1(b13_10to14_10_pong), .out_c(matrixC13_10), .b_data_valid_ping(b_data_valid_ping_delay13_10), .b_data_valid_pong(b_data_valid_pong_delay13_10), .mode(1'b0)); +processing_element pe13_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_13_11_NC), .in_a_chain(a13_10to13_11), .in_b(b12_11to13_11), .in_c(matrixC12_11), .out_a(out_a_13_11_NC), .out_a_chain(a13_11to13_12), .out_b(b13_11to14_11), .out_b0(b13_11to14_11_ping), .out_b1(b13_11to14_11_pong), .out_c(matrixC13_11), .b_data_valid_ping(b_data_valid_ping_delay13_11), .b_data_valid_pong(b_data_valid_pong_delay13_11), .mode(1'b0)); +processing_element pe13_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_13_12_NC), .in_a_chain(a13_11to13_12), .in_b(b12_12to13_12), .in_c(matrixC12_12), .out_a(out_a_13_12_NC), .out_a_chain(a13_12to13_13), .out_b(b13_12to14_12), .out_b0(b13_12to14_12_ping), .out_b1(b13_12to14_12_pong), .out_c(matrixC13_12), .b_data_valid_ping(b_data_valid_ping_delay13_12), .b_data_valid_pong(b_data_valid_pong_delay13_12), .mode(1'b0)); +processing_element pe13_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_13_13_NC), .in_a_chain(a13_12to13_13), .in_b(b12_13to13_13), .in_c(matrixC12_13), .out_a(out_a_13_13_NC), .out_a_chain(a13_13to13_14), .out_b(b13_13to14_13), .out_b0(b13_13to14_13_ping), .out_b1(b13_13to14_13_pong), .out_c(matrixC13_13), .b_data_valid_ping(b_data_valid_ping_delay13_13), .b_data_valid_pong(b_data_valid_pong_delay13_13), .mode(1'b0)); +processing_element pe13_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_13_14_NC), .in_a_chain(a13_13to13_14), .in_b(b12_14to13_14), .in_c(matrixC12_14), .out_a(out_a_13_14_NC), .out_a_chain(a13_14to13_15), .out_b(b13_14to14_14), .out_b0(b13_14to14_14_ping), .out_b1(b13_14to14_14_pong), .out_c(matrixC13_14), .b_data_valid_ping(b_data_valid_ping_delay13_14), .b_data_valid_pong(b_data_valid_pong_delay13_14), .mode(1'b0)); +processing_element pe13_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_13_15_NC), .in_a_chain(a13_14to13_15), .in_b(b12_15to13_15), .in_c(matrixC12_15), .out_a(out_a_13_15_NC), .out_a_chain(a13_15to13_16), .out_b(b13_15to14_15), .out_b0(b13_15to14_15_ping), .out_b1(b13_15to14_15_pong), .out_c(matrixC13_15), .b_data_valid_ping(b_data_valid_ping_delay13_15), .b_data_valid_pong(b_data_valid_pong_delay13_15), .mode(1'b0)); +processing_element pe14_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay14), .in_a(a14), .in_a_chain(in_a_chain_14_0_NC), .in_b(b13_0to14_0), .in_c(matrixC13_0), .out_a(out_a_14_0_NC), .out_a_chain(a14_0to14_1), .out_b(b14_0to15_0), .out_b0(b14_0to15_0_ping), .out_b1(b14_0to15_0_pong), .out_c(matrixC14_0), .b_data_valid_ping(b_data_valid_ping_delay14_0), .b_data_valid_pong(b_data_valid_pong_delay14_0), .mode(1'b1)); +processing_element pe14_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(in_a_14_1_NC), .in_a_chain(a14_0to14_1), .in_b(b13_1to14_1), .in_c(matrixC13_1), .out_a(out_a_14_1_NC), .out_a_chain(a14_1to14_2), .out_b(b14_1to15_1), .out_b0(b14_1to15_1_ping), .out_b1(b14_1to15_1_pong), .out_c(matrixC14_1), .b_data_valid_ping(b_data_valid_ping_delay14_1), .b_data_valid_pong(b_data_valid_pong_delay14_1), .mode(1'b0)); +processing_element pe14_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_14_2_NC), .in_a_chain(a14_1to14_2), .in_b(b13_2to14_2), .in_c(matrixC13_2), .out_a(out_a_14_2_NC), .out_a_chain(a14_2to14_3), .out_b(b14_2to15_2), .out_b0(b14_2to15_2_ping), .out_b1(b14_2to15_2_pong), .out_c(matrixC14_2), .b_data_valid_ping(b_data_valid_ping_delay14_2), .b_data_valid_pong(b_data_valid_pong_delay14_2), .mode(1'b0)); +processing_element pe14_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_14_3_NC), .in_a_chain(a14_2to14_3), .in_b(b13_3to14_3), .in_c(matrixC13_3), .out_a(out_a_14_3_NC), .out_a_chain(a14_3to14_4), .out_b(b14_3to15_3), .out_b0(b14_3to15_3_ping), .out_b1(b14_3to15_3_pong), .out_c(matrixC14_3), .b_data_valid_ping(b_data_valid_ping_delay14_3), .b_data_valid_pong(b_data_valid_pong_delay14_3), .mode(1'b0)); +processing_element pe14_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_14_4_NC), .in_a_chain(a14_3to14_4), .in_b(b13_4to14_4), .in_c(matrixC13_4), .out_a(out_a_14_4_NC), .out_a_chain(a14_4to14_5), .out_b(b14_4to15_4), .out_b0(b14_4to15_4_ping), .out_b1(b14_4to15_4_pong), .out_c(matrixC14_4), .b_data_valid_ping(b_data_valid_ping_delay14_4), .b_data_valid_pong(b_data_valid_pong_delay14_4), .mode(1'b0)); +processing_element pe14_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_14_5_NC), .in_a_chain(a14_4to14_5), .in_b(b13_5to14_5), .in_c(matrixC13_5), .out_a(out_a_14_5_NC), .out_a_chain(a14_5to14_6), .out_b(b14_5to15_5), .out_b0(b14_5to15_5_ping), .out_b1(b14_5to15_5_pong), .out_c(matrixC14_5), .b_data_valid_ping(b_data_valid_ping_delay14_5), .b_data_valid_pong(b_data_valid_pong_delay14_5), .mode(1'b0)); +processing_element pe14_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_14_6_NC), .in_a_chain(a14_5to14_6), .in_b(b13_6to14_6), .in_c(matrixC13_6), .out_a(out_a_14_6_NC), .out_a_chain(a14_6to14_7), .out_b(b14_6to15_6), .out_b0(b14_6to15_6_ping), .out_b1(b14_6to15_6_pong), .out_c(matrixC14_6), .b_data_valid_ping(b_data_valid_ping_delay14_6), .b_data_valid_pong(b_data_valid_pong_delay14_6), .mode(1'b0)); +processing_element pe14_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_14_7_NC), .in_a_chain(a14_6to14_7), .in_b(b13_7to14_7), .in_c(matrixC13_7), .out_a(out_a_14_7_NC), .out_a_chain(a14_7to14_8), .out_b(b14_7to15_7), .out_b0(b14_7to15_7_ping), .out_b1(b14_7to15_7_pong), .out_c(matrixC14_7), .b_data_valid_ping(b_data_valid_ping_delay14_7), .b_data_valid_pong(b_data_valid_pong_delay14_7), .mode(1'b0)); +processing_element pe14_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_14_8_NC), .in_a_chain(a14_7to14_8), .in_b(b13_8to14_8), .in_c(matrixC13_8), .out_a(out_a_14_8_NC), .out_a_chain(a14_8to14_9), .out_b(b14_8to15_8), .out_b0(b14_8to15_8_ping), .out_b1(b14_8to15_8_pong), .out_c(matrixC14_8), .b_data_valid_ping(b_data_valid_ping_delay14_8), .b_data_valid_pong(b_data_valid_pong_delay14_8), .mode(1'b0)); +processing_element pe14_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_14_9_NC), .in_a_chain(a14_8to14_9), .in_b(b13_9to14_9), .in_c(matrixC13_9), .out_a(out_a_14_9_NC), .out_a_chain(a14_9to14_10), .out_b(b14_9to15_9), .out_b0(b14_9to15_9_ping), .out_b1(b14_9to15_9_pong), .out_c(matrixC14_9), .b_data_valid_ping(b_data_valid_ping_delay14_9), .b_data_valid_pong(b_data_valid_pong_delay14_9), .mode(1'b0)); +processing_element pe14_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_14_10_NC), .in_a_chain(a14_9to14_10), .in_b(b13_10to14_10), .in_c(matrixC13_10), .out_a(out_a_14_10_NC), .out_a_chain(a14_10to14_11), .out_b(b14_10to15_10), .out_b0(b14_10to15_10_ping), .out_b1(b14_10to15_10_pong), .out_c(matrixC14_10), .b_data_valid_ping(b_data_valid_ping_delay14_10), .b_data_valid_pong(b_data_valid_pong_delay14_10), .mode(1'b0)); +processing_element pe14_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_14_11_NC), .in_a_chain(a14_10to14_11), .in_b(b13_11to14_11), .in_c(matrixC13_11), .out_a(out_a_14_11_NC), .out_a_chain(a14_11to14_12), .out_b(b14_11to15_11), .out_b0(b14_11to15_11_ping), .out_b1(b14_11to15_11_pong), .out_c(matrixC14_11), .b_data_valid_ping(b_data_valid_ping_delay14_11), .b_data_valid_pong(b_data_valid_pong_delay14_11), .mode(1'b0)); +processing_element pe14_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_14_12_NC), .in_a_chain(a14_11to14_12), .in_b(b13_12to14_12), .in_c(matrixC13_12), .out_a(out_a_14_12_NC), .out_a_chain(a14_12to14_13), .out_b(b14_12to15_12), .out_b0(b14_12to15_12_ping), .out_b1(b14_12to15_12_pong), .out_c(matrixC14_12), .b_data_valid_ping(b_data_valid_ping_delay14_12), .b_data_valid_pong(b_data_valid_pong_delay14_12), .mode(1'b0)); +processing_element pe14_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_14_13_NC), .in_a_chain(a14_12to14_13), .in_b(b13_13to14_13), .in_c(matrixC13_13), .out_a(out_a_14_13_NC), .out_a_chain(a14_13to14_14), .out_b(b14_13to15_13), .out_b0(b14_13to15_13_ping), .out_b1(b14_13to15_13_pong), .out_c(matrixC14_13), .b_data_valid_ping(b_data_valid_ping_delay14_13), .b_data_valid_pong(b_data_valid_pong_delay14_13), .mode(1'b0)); +processing_element pe14_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_14_14_NC), .in_a_chain(a14_13to14_14), .in_b(b13_14to14_14), .in_c(matrixC13_14), .out_a(out_a_14_14_NC), .out_a_chain(a14_14to14_15), .out_b(b14_14to15_14), .out_b0(b14_14to15_14_ping), .out_b1(b14_14to15_14_pong), .out_c(matrixC14_14), .b_data_valid_ping(b_data_valid_ping_delay14_14), .b_data_valid_pong(b_data_valid_pong_delay14_14), .mode(1'b0)); +processing_element pe14_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_14_15_NC), .in_a_chain(a14_14to14_15), .in_b(b13_15to14_15), .in_c(matrixC13_15), .out_a(out_a_14_15_NC), .out_a_chain(a14_15to14_16), .out_b(b14_15to15_15), .out_b0(b14_15to15_15_ping), .out_b1(b14_15to15_15_pong), .out_c(matrixC14_15), .b_data_valid_ping(b_data_valid_ping_delay14_15), .b_data_valid_pong(b_data_valid_pong_delay14_15), .mode(1'b0)); +processing_element pe15_0(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay15), .in_a(a15), .in_a_chain(in_a_chain_15_0_NC), .in_b(b14_0to15_0), .in_c(matrixC14_0), .out_a(out_a_15_0_NC), .out_a_chain(a15_0to15_1), .out_b(b15_0to16_0), .out_b0(b15_0to16_0_ping), .out_b1(b15_0to16_0_pong), .out_c(matrixC15_0), .b_data_valid_ping(b_data_valid_ping_delay15_0), .b_data_valid_pong(b_data_valid_pong_delay15_0), .mode(1'b1)); +processing_element pe15_1(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay16), .in_a(in_a_15_1_NC), .in_a_chain(a15_0to15_1), .in_b(b14_1to15_1), .in_c(matrixC14_1), .out_a(out_a_15_1_NC), .out_a_chain(a15_1to15_2), .out_b(b15_1to16_1), .out_b0(b15_1to16_1_ping), .out_b1(b15_1to16_1_pong), .out_c(matrixC15_1), .b_data_valid_ping(b_data_valid_ping_delay15_1), .b_data_valid_pong(b_data_valid_pong_delay15_1), .mode(1'b0)); +processing_element pe15_2(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay17), .in_a(in_a_15_2_NC), .in_a_chain(a15_1to15_2), .in_b(b14_2to15_2), .in_c(matrixC14_2), .out_a(out_a_15_2_NC), .out_a_chain(a15_2to15_3), .out_b(b15_2to16_2), .out_b0(b15_2to16_2_ping), .out_b1(b15_2to16_2_pong), .out_c(matrixC15_2), .b_data_valid_ping(b_data_valid_ping_delay15_2), .b_data_valid_pong(b_data_valid_pong_delay15_2), .mode(1'b0)); +processing_element pe15_3(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay18), .in_a(in_a_15_3_NC), .in_a_chain(a15_2to15_3), .in_b(b14_3to15_3), .in_c(matrixC14_3), .out_a(out_a_15_3_NC), .out_a_chain(a15_3to15_4), .out_b(b15_3to16_3), .out_b0(b15_3to16_3_ping), .out_b1(b15_3to16_3_pong), .out_c(matrixC15_3), .b_data_valid_ping(b_data_valid_ping_delay15_3), .b_data_valid_pong(b_data_valid_pong_delay15_3), .mode(1'b0)); +processing_element pe15_4(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay19), .in_a(in_a_15_4_NC), .in_a_chain(a15_3to15_4), .in_b(b14_4to15_4), .in_c(matrixC14_4), .out_a(out_a_15_4_NC), .out_a_chain(a15_4to15_5), .out_b(b15_4to16_4), .out_b0(b15_4to16_4_ping), .out_b1(b15_4to16_4_pong), .out_c(matrixC15_4), .b_data_valid_ping(b_data_valid_ping_delay15_4), .b_data_valid_pong(b_data_valid_pong_delay15_4), .mode(1'b0)); +processing_element pe15_5(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay20), .in_a(in_a_15_5_NC), .in_a_chain(a15_4to15_5), .in_b(b14_5to15_5), .in_c(matrixC14_5), .out_a(out_a_15_5_NC), .out_a_chain(a15_5to15_6), .out_b(b15_5to16_5), .out_b0(b15_5to16_5_ping), .out_b1(b15_5to16_5_pong), .out_c(matrixC15_5), .b_data_valid_ping(b_data_valid_ping_delay15_5), .b_data_valid_pong(b_data_valid_pong_delay15_5), .mode(1'b0)); +processing_element pe15_6(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay21), .in_a(in_a_15_6_NC), .in_a_chain(a15_5to15_6), .in_b(b14_6to15_6), .in_c(matrixC14_6), .out_a(out_a_15_6_NC), .out_a_chain(a15_6to15_7), .out_b(b15_6to16_6), .out_b0(b15_6to16_6_ping), .out_b1(b15_6to16_6_pong), .out_c(matrixC15_6), .b_data_valid_ping(b_data_valid_ping_delay15_6), .b_data_valid_pong(b_data_valid_pong_delay15_6), .mode(1'b0)); +processing_element pe15_7(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay22), .in_a(in_a_15_7_NC), .in_a_chain(a15_6to15_7), .in_b(b14_7to15_7), .in_c(matrixC14_7), .out_a(out_a_15_7_NC), .out_a_chain(a15_7to15_8), .out_b(b15_7to16_7), .out_b0(b15_7to16_7_ping), .out_b1(b15_7to16_7_pong), .out_c(matrixC15_7), .b_data_valid_ping(b_data_valid_ping_delay15_7), .b_data_valid_pong(b_data_valid_pong_delay15_7), .mode(1'b0)); +processing_element pe15_8(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay23), .in_a(in_a_15_8_NC), .in_a_chain(a15_7to15_8), .in_b(b14_8to15_8), .in_c(matrixC14_8), .out_a(out_a_15_8_NC), .out_a_chain(a15_8to15_9), .out_b(b15_8to16_8), .out_b0(b15_8to16_8_ping), .out_b1(b15_8to16_8_pong), .out_c(matrixC15_8), .b_data_valid_ping(b_data_valid_ping_delay15_8), .b_data_valid_pong(b_data_valid_pong_delay15_8), .mode(1'b0)); +processing_element pe15_9(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay24), .in_a(in_a_15_9_NC), .in_a_chain(a15_8to15_9), .in_b(b14_9to15_9), .in_c(matrixC14_9), .out_a(out_a_15_9_NC), .out_a_chain(a15_9to15_10), .out_b(b15_9to16_9), .out_b0(b15_9to16_9_ping), .out_b1(b15_9to16_9_pong), .out_c(matrixC15_9), .b_data_valid_ping(b_data_valid_ping_delay15_9), .b_data_valid_pong(b_data_valid_pong_delay15_9), .mode(1'b0)); +processing_element pe15_10(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay25), .in_a(in_a_15_10_NC), .in_a_chain(a15_9to15_10), .in_b(b14_10to15_10), .in_c(matrixC14_10), .out_a(out_a_15_10_NC), .out_a_chain(a15_10to15_11), .out_b(b15_10to16_10), .out_b0(b15_10to16_10_ping), .out_b1(b15_10to16_10_pong), .out_c(matrixC15_10), .b_data_valid_ping(b_data_valid_ping_delay15_10), .b_data_valid_pong(b_data_valid_pong_delay15_10), .mode(1'b0)); +processing_element pe15_11(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay26), .in_a(in_a_15_11_NC), .in_a_chain(a15_10to15_11), .in_b(b14_11to15_11), .in_c(matrixC14_11), .out_a(out_a_15_11_NC), .out_a_chain(a15_11to15_12), .out_b(b15_11to16_11), .out_b0(b15_11to16_11_ping), .out_b1(b15_11to16_11_pong), .out_c(matrixC15_11), .b_data_valid_ping(b_data_valid_ping_delay15_11), .b_data_valid_pong(b_data_valid_pong_delay15_11), .mode(1'b0)); +processing_element pe15_12(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay27), .in_a(in_a_15_12_NC), .in_a_chain(a15_11to15_12), .in_b(b14_12to15_12), .in_c(matrixC14_12), .out_a(out_a_15_12_NC), .out_a_chain(a15_12to15_13), .out_b(b15_12to16_12), .out_b0(b15_12to16_12_ping), .out_b1(b15_12to16_12_pong), .out_c(matrixC15_12), .b_data_valid_ping(b_data_valid_ping_delay15_12), .b_data_valid_pong(b_data_valid_pong_delay15_12), .mode(1'b0)); +processing_element pe15_13(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay28), .in_a(in_a_15_13_NC), .in_a_chain(a15_12to15_13), .in_b(b14_13to15_13), .in_c(matrixC14_13), .out_a(out_a_15_13_NC), .out_a_chain(a15_13to15_14), .out_b(b15_13to16_13), .out_b0(b15_13to16_13_ping), .out_b1(b15_13to16_13_pong), .out_c(matrixC15_13), .b_data_valid_ping(b_data_valid_ping_delay15_13), .b_data_valid_pong(b_data_valid_pong_delay15_13), .mode(1'b0)); +processing_element pe15_14(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay29), .in_a(in_a_15_14_NC), .in_a_chain(a15_13to15_14), .in_b(b14_14to15_14), .in_c(matrixC14_14), .out_a(out_a_15_14_NC), .out_a_chain(a15_14to15_15), .out_b(b15_14to16_14), .out_b0(b15_14to16_14_ping), .out_b1(b15_14to16_14_pong), .out_c(matrixC15_14), .b_data_valid_ping(b_data_valid_ping_delay15_14), .b_data_valid_pong(b_data_valid_pong_delay15_14), .mode(1'b0)); +processing_element pe15_15(.reset(effective_rst), .clk(clk), .b_data_sel(b_data_sel_delay30), .in_a(in_a_15_15_NC), .in_a_chain(a15_14to15_15), .in_b(b14_15to15_15), .in_c(matrixC14_15), .out_a(out_a_15_15_NC), .out_a_chain(a15_15to15_16), .out_b(b15_15to16_15), .out_b0(b15_15to16_15_ping), .out_b1(b15_15to16_15_pong), .out_c(matrixC15_15), .b_data_valid_ping(b_data_valid_ping_delay15_15), .b_data_valid_pong(b_data_valid_pong_delay15_15), .mode(1'b0)); + +//assign a_data_out = {a15_15to15_16, a14_15to14_16, a13_15to13_16, a12_15to12_16, a11_15to11_16, a10_15to10_16, a9_15to9_16, a8_15to8_16, a7_15to7_16, a6_15to6_16, a5_15to5_16, a4_15to4_16, a3_15to3_16, a2_15to2_16, a1_15to1_16, a0_15to0_16}; +//assign b_data_out = {b15_15to16_15, b15_14to16_14, b15_13to16_13, b15_12to16_12, b15_11to16_11, b15_10to16_10, b15_9to16_9, b15_8to16_8, b15_7to16_7, b15_6to16_6, b15_5to16_5, b15_4to16_4, b15_3to16_3, b15_2to16_2, b15_1to16_1, b15_0to16_0}; + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Processing element (PE) +////////////////////////////////////////////////////////////////////////// + +module processing_element( + reset, + clk, + b_data_sel, + in_a, + in_a_chain, + in_b, + in_c, + out_a, + out_a_chain, + out_b, + out_b0, + out_b1, + out_c, + b_data_valid_ping, + b_data_valid_pong, + mode + ); + +input reset; +input clk; +input b_data_sel; +input b_data_valid_ping; +input b_data_valid_pong; +input [`DWIDTH-1:0] in_a; +input [`DWIDTH-1:0] in_a_chain; +input [`DWIDTH-1:0] in_b; +input [`DWIDTH-1:0] in_c; +output [`DWIDTH-1:0] out_a; +output [`DWIDTH-1:0] out_a_chain; +output [`DWIDTH-1:0] out_b; +output [`DWIDTH-1:0] out_b0; +output [`DWIDTH-1:0] out_b1; +output [`DWIDTH-1:0] out_c; +input mode; + +`ifdef complex_dsp + + wire [18:0] scanout; + wire [63:0] chainout; //unconnected + wire [63:0] result; + wire [17:0] ax; + wire [18:0] ay; + wire [35:0] bx; + wire [63:0] chainin; //unconnected + wire [18:0] scanin; + wire [11:0] mode_sigs; + + assign mode_sigs = 12'b010101010101; //Any value of mode_sigs (structural, not functional, correctness) + assign ax = {{(18-`DWIDTH){1'b0}}, in_a}; + assign ay = {{(19-`DWIDTH){1'b0}}, in_b}; + assign bx = in_c; + assign scanin = {{(18-`DWIDTH){1'b0}}, in_a_chain}; + //assign chainin = in_c; + + //We will instantiate DSP slices with input chaining and output chaining. + //Input chaining is only supported in the 18x19 mode or the 27x27 mode. + //We will use the input chain provided by the DSP for the A input. For B, the chain will be manual. + + mult_add_int_18x19 u_pe( + .clk(clk), + .reset(reset), + .mode_sigs(mode_sigs), + .ax(ax), + .ay(ay), + .bx(bx), + .chainin(chainin), + .scanin(scanin), + .result(result), + .chainout(chainout), + .scanout(scanout) + ); + +reg [`DWIDTH-1:0] out_b0; +reg [`DWIDTH-1:0] out_b1; + +wire [`DWIDTH-1:0] in_mac; +wire [`DWIDTH-1:0] out_c; + +assign out_c = result; +assign in_mac = (b_data_sel==0)? out_b0 : out_b1; + +//assign out_a = result; +assign out_a_chain = scanout; + +always @(posedge clk)begin + if (reset) begin + out_b0<=0; + end + if(b_data_valid_ping == 1) begin + out_b0<=in_b; + end +end + +always @(posedge clk)begin + if (reset) begin + out_b1<=0; + end + if(b_data_valid_pong == 1) begin + out_b1<=in_b; + end +end + +`else + +reg [`DWIDTH-1:0] out_a; +reg [`DWIDTH-1:0] out_b; +reg [`DWIDTH-1:0] out_b0; +reg [`DWIDTH-1:0] out_b1; + +wire [`DWIDTH-1:0] in_mac; +wire [`DWIDTH-1:0] out_c; +wire [`DWIDTH-1:0] out_mac; + +assign out_c = out_mac; +assign in_mac = (b_data_sel==0)? out_b0 : out_b1; + +seq_mac u_mac(.a(out_a), .b(in_mac), .c(in_c), .out(out_mac), .reset(reset), .clk(clk)); + +always @(posedge clk)begin + if(reset) begin + out_a<=0; + end + else begin + out_a<=mode ? in_a : in_a_chain; + end +end + +assign out_a_chain = out_a; + +always @(posedge clk)begin + if(reset) begin + out_b<=0; + end + else begin + out_b<=in_b; + end +end + +always @(posedge clk)begin + if (reset) begin + out_b0<=0; + end + if(b_data_valid_ping == 1) begin + out_b0<=in_b; + end +end + +always @(posedge clk)begin + if (reset) begin + out_b1<=0; + end + if(b_data_valid_pong == 1) begin + out_b1<=in_b; + end +end + +`endif + +endmodule + +`ifndef complex_dsp + +////////////////////////////////////////////////////////////////////////// +// Multiply-and-accumulate (MAC) block +////////////////////////////////////////////////////////////////////////// + +module seq_mac(a, b, c, out, reset, clk); + +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +input [`DWIDTH-1:0] c; +input reset; +input clk; +output [`DWIDTH-1:0] out; + +wire [`DWIDTH-1:0] mul_out; +wire [`DWIDTH-1:0] add_out; + +reg [`DWIDTH-1:0] a_flopped; +reg [`DWIDTH-1:0] b_flopped; +reg [`DWIDTH-1:0] c_flopped; + +wire [2*`DWIDTH-1:0] mul_out_temp; +wire [2*`DWIDTH-1:0] mul_out_temp_reg; + +always @(posedge clk) begin + if (reset) begin + a_flopped <= 0; + b_flopped <= 0; + c_flopped <= 0; + end else begin + a_flopped <= a; + b_flopped <= b; + c_flopped <= c; + end +end + +// assign mul_out = a * b; +qmult mult_u1(.i_multiplicand(a_flopped), .i_multiplier(b_flopped), .o_result(mul_out_temp)); + + +// down cast the result +// todo: do a fused multiply add. Truncate only once after the accumulation is complete +assign mul_out = + (mul_out_temp[2*`DWIDTH-1] == 0) ? //positive number + ( + (|(mul_out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 1, that means overlfow + {mul_out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b1}}} : //sign bit and then all 1s + {mul_out_temp[2*`DWIDTH-1] , mul_out_temp[`DWIDTH-2:0]} + ) + : //negative number + ( + (|(mul_out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 0, that means overlfow + {mul_out_temp[2*`DWIDTH-1] , mul_out_temp[`DWIDTH-2:0]} : + {mul_out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b0}}} //sign bit and then all 0s + ); + + +// we just truncate the higher bits of the product +// assign out = mul_out + c_flopped; +qadd add_u1(.a(c_flopped), .b(mul_out), .c(out)); + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Multiplier +////////////////////////////////////////////////////////////////////////// + +module qmult(i_multiplicand,i_multiplier,o_result); + +input [`DWIDTH-1:0] i_multiplicand; +input [`DWIDTH-1:0] i_multiplier; +output [2*`DWIDTH-1:0] o_result; + +assign o_result = i_multiplicand * i_multiplier; +//DW02_mult #(`DWIDTH,`DWIDTH) u_mult(.A(i_multiplicand), .B(i_multiplier), .TC(1'b1), .PRODUCT(o_result)); + +endmodule + +`endif + +////////////////////////////////////////////////////////////////////////// +// Adder +////////////////////////////////////////////////////////////////////////// +// todo: Output should have one extra bit as compared to the inputs + +module qadd(a,b,c); + +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +output [`DWIDTH-1:0] c; + +assign c = a + b; +// DW01_add #(`DWIDTH) u_add(.A(a), .B(b), .CI(1'b0), .SUM(c), .CO()); + +endmodule + +module cfg( + input PCLK, + input PRESETn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output reg [`REG_DATAWIDTH-1:0] PRDATA, + output reg PREADY, + output reg start_tpu, + output reg enable_matmul, + output reg enable_norm, + output reg enable_pool, + output reg enable_activation, + output reg enable_conv_mode, + //TODO: We need to change the precision of compute to a larger + //number. For now, using the DWIDTH variable, but we need a + //HIGH_PRECISION_DWIDTH kind of thing + output reg [`DWIDTH-1:0] mean, + output reg [`DWIDTH-1:0] inv_var, + output reg [`MAX_BITS_POOL-1:0] pool_window_size, + output reg [`AWIDTH-1:0] address_mat_a, + output reg [`AWIDTH-1:0] address_mat_b, + output reg [`AWIDTH-1:0] address_mat_c, + output reg [31:0] num_matrices_A, + output reg [31:0] num_matrices_B, + output reg [`DWIDTH-1:0] matrix_size, + output reg [`DWIDTH-1:0] filter_size, + output reg pool_select, + output reg [`DWIDTH-1:0] k_dimension, + output reg accum_select, + output reg [`MASK_WIDTH-1:0] validity_mask_a_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_a_cols_b_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_b_cols, + output reg save_output_to_accum, + output reg add_accum_to_output, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c, + output reg activation_type, + output reg [3:0] conv_filter_height, + output reg [3:0] conv_filter_width, + output reg [3:0] conv_stride_horiz, + output reg [3:0] conv_stride_verti, + output reg [3:0] conv_padding_left, + output reg [3:0] conv_padding_right, + output reg [3:0] conv_padding_top, + output reg [3:0] conv_padding_bottom, + output reg [15:0] num_channels_inp, + output reg [15:0] num_channels_out, + output reg [15:0] inp_img_height, + output reg [15:0] inp_img_width, + output reg [15:0] out_img_height, + output reg [15:0] out_img_width, + output reg [31:0] batch_size, + output reg pe_reset, + input done_tpu +); + +//Dummy register to sync all other invalid/unimplemented addresses +reg [`REG_DATAWIDTH-1:0] reg_dummy; + + +////////////////////////////////////////////////////// +//Using a simple APB interface. Taken from: +// https://github.com/maomran/APB-Slave +// https://research.ijcaonline.org/volume95/number21/pxc3897047.pdf + +reg [1:0] State; +`define IDLE 2'b00 +`define W_ENABLE 2'b01 +`define R_ENABLE 2'b10 + +always @(posedge PCLK) begin + if (PRESETn == 0) begin + State <= `IDLE; + PRDATA <= 0; + PREADY <= 0; + start_tpu <= 0; + enable_matmul <= 0; + enable_norm <= 0; + enable_pool <= 0; + enable_activation <= 0; + mean <= 0; + inv_var <= 0; + pool_window_size <= 1; + reg_dummy <= 0; + address_mat_a <= 0; + address_mat_b <= 0; + address_mat_c <= 0; + num_matrices_A <= 1; + num_matrices_B <= 1; + matrix_size <= 8; + filter_size <= 2; + pool_select <= 0; + k_dimension <= 8; + accum_select <= 1; + validity_mask_a_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_a_cols_b_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_cols <= {`MASK_WIDTH{1'b1}}; + save_output_to_accum <= 0; + add_accum_to_output <= 0; + address_stride_a <= 1; + address_stride_b <= 1; + address_stride_c <= 1; + activation_type <= 1; + conv_filter_height <= 2; + conv_filter_width <= 2; + conv_stride_horiz <= 1; + conv_stride_verti <= 1; + conv_padding_left <= 0; + conv_padding_right <= 0; + conv_padding_top <= 0; + conv_padding_bottom<= 0; + num_channels_inp <= 4; + num_channels_out <= 4; + inp_img_height <= 8; + inp_img_width <= 8; + out_img_height <= 7; + out_img_width <= 7; + batch_size <= 2; + enable_conv_mode <= 0; + pe_reset <= 0; + end + + else begin + case (State) + `IDLE : begin + PRDATA <= 0; + if (PSEL) begin + if (PWRITE) begin + State <= `W_ENABLE; + end + else begin + State <= `R_ENABLE; + end + end + PREADY <= 0; + pe_reset <= 0; //this register bit auto resets itself + end + + `W_ENABLE : begin + if (PSEL && PWRITE && PENABLE) begin + case (PADDR) + `REG_ENABLES_ADDR : begin + enable_conv_mode <= PWDATA[31]; + enable_activation <= PWDATA[3]; + enable_pool <= PWDATA[2]; + enable_norm <= PWDATA[1]; + enable_matmul <= PWDATA[0]; + end + `REG_STDN_TPU_ADDR : begin + start_tpu <= PWDATA[0]; + pe_reset <= PWDATA[15]; + end + `REG_MEAN_ADDR : mean <= PWDATA[`DWIDTH-1:0]; + `REG_INV_VAR_ADDR : inv_var <= PWDATA[`DWIDTH-1:0]; + `REG_MATRIX_A_ADDR : address_mat_a <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_B_ADDR : address_mat_b <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_C_ADDR : address_mat_c <= PWDATA[`AWIDTH-1:0]; + `REG_VALID_MASK_A_ROWS_ADDR: begin + validity_mask_a_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_A_COLS_B_ROWS_ADDR: begin + validity_mask_a_cols_b_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_COLS_ADDR: begin + validity_mask_b_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_POOL_WINDOW_ADDR: pool_window_size <= PWDATA[`MAX_BITS_POOL-1:0]; + `REG_ACCUM_ACTIONS_ADDR: begin + add_accum_to_output <= PWDATA[1]; + save_output_to_accum <= PWDATA[0]; + end + `REG_MATRIX_A_STRIDE_ADDR : address_stride_a <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_B_STRIDE_ADDR : address_stride_b <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_C_STRIDE_ADDR : address_stride_c <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_ACTIVATION_CSR_ADDR : activation_type <= PWDATA[0]; + `REG_CONV_PARAMS_1_ADDR : begin + conv_filter_height <= PWDATA[3:0]; + conv_filter_width <= PWDATA[7:4]; + conv_stride_horiz <= PWDATA[11:8]; + conv_stride_verti <= PWDATA[15:12]; + conv_padding_left <= PWDATA[19:16]; + conv_padding_right <= PWDATA[23:20]; + conv_padding_top <= PWDATA[27:24]; + conv_padding_bottom<= PWDATA[31:28]; + end + `REG_CONV_PARAMS_2_ADDR : begin + num_channels_inp <= PWDATA[15:0]; + num_channels_out <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_3_ADDR : begin + inp_img_height <= PWDATA[15:0]; + inp_img_width <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_4_ADDR : begin + out_img_height <= PWDATA[15:0]; + out_img_width <= PWDATA[31:16]; + end + `REG_BATCH_SIZE_ADDR : batch_size <= PWDATA[31:0]; + `REG_NUM_MATRICES_A_ADDR : num_matrices_A <= PWDATA[31:0]; + `REG_NUM_MATRICES_B_ADDR : num_matrices_B <= PWDATA[31:0]; + `REG_POOLING_ACCUM_ADDR : begin + pool_select <= PWDATA[0]; + filter_size <= PWDATA[8:1]; + matrix_size <= PWDATA[16:9]; + k_dimension <= PWDATA[24:17]; + accum_select <= PWDATA[25]; + end + default: reg_dummy <= PWDATA; //sink writes to a dummy register + endcase + PREADY <=1; + end + State <= `IDLE; + end + + `R_ENABLE : begin + if (PSEL && !PWRITE && PENABLE) begin + PREADY <= 1; + case (PADDR) + `REG_ENABLES_ADDR : PRDATA <= {28'b0, enable_activation, enable_pool, enable_norm, enable_matmul}; + `REG_STDN_TPU_ADDR : PRDATA <= {done_tpu, 30'b0, start_tpu}; + `REG_MEAN_ADDR : PRDATA <= mean; + `REG_INV_VAR_ADDR : PRDATA <= inv_var; + `REG_MATRIX_A_ADDR : PRDATA <= address_mat_a; + `REG_MATRIX_B_ADDR : PRDATA <= address_mat_b; + `REG_MATRIX_C_ADDR : PRDATA <= address_mat_c; + `REG_VALID_MASK_A_ROWS_ADDR: PRDATA <= validity_mask_a_rows; + `REG_VALID_MASK_A_COLS_B_ROWS_ADDR: PRDATA <= validity_mask_a_cols_b_rows; + `REG_VALID_MASK_B_COLS_ADDR: PRDATA <= validity_mask_b_cols; + `REG_POOL_WINDOW_ADDR : PRDATA <= pool_window_size; + `REG_ACCUM_ACTIONS_ADDR: PRDATA <= {30'b0, add_accum_to_output, save_output_to_accum}; + `REG_MATRIX_A_STRIDE_ADDR : PRDATA <= address_stride_a; + `REG_MATRIX_B_STRIDE_ADDR : PRDATA <= address_stride_b; + `REG_MATRIX_C_STRIDE_ADDR : PRDATA <= address_stride_c; + `REG_ACTIVATION_CSR_ADDR : PRDATA <= {31'b0, activation_type}; + `REG_CONV_PARAMS_1_ADDR : PRDATA <= { + conv_filter_height, + conv_filter_width, + conv_stride_horiz, + conv_stride_verti, + conv_padding_left, + conv_padding_right, + conv_padding_top, + conv_padding_bottom + }; + `REG_CONV_PARAMS_2_ADDR : PRDATA <= { + num_channels_inp, + num_channels_out + }; + `REG_CONV_PARAMS_3_ADDR : PRDATA <= { + inp_img_height, + inp_img_width + }; + `REG_CONV_PARAMS_4_ADDR : PRDATA <= { + out_img_height, + out_img_width + }; + `REG_BATCH_SIZE_ADDR : PRDATA <= batch_size; + `REG_NUM_MATRICES_A_ADDR : PRDATA <= num_matrices_A; + `REG_NUM_MATRICES_B_ADDR : PRDATA <= num_matrices_B; + `REG_POOLING_ACCUM_ADDR : PRDATA <= {6'b0, accum_select, k_dimension, matrix_size, filter_size, pool_select}; + default : PRDATA <= reg_dummy; //read the dummy register for undefined addresses + endcase + end + State <= `IDLE; + end + default: begin + State <= `IDLE; + end + endcase + end +end + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM generate_norm.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// +module norm( + input enable_norm, + input [`DWIDTH-1:0] mean, + input [`DWIDTH-1:0] inv_var, + input in_data_available, + input [`DWIDTH-1:0] inp_data0, + input [`DWIDTH-1:0] inp_data1, + input [`DWIDTH-1:0] inp_data2, + input [`DWIDTH-1:0] inp_data3, + input [`DWIDTH-1:0] inp_data4, + input [`DWIDTH-1:0] inp_data5, + input [`DWIDTH-1:0] inp_data6, + input [`DWIDTH-1:0] inp_data7, + input [`DWIDTH-1:0] inp_data8, + input [`DWIDTH-1:0] inp_data9, + input [`DWIDTH-1:0] inp_data10, + input [`DWIDTH-1:0] inp_data11, + input [`DWIDTH-1:0] inp_data12, + input [`DWIDTH-1:0] inp_data13, + input [`DWIDTH-1:0] inp_data14, + input [`DWIDTH-1:0] inp_data15, + output [`DWIDTH-1:0] out_data0, + output [`DWIDTH-1:0] out_data1, + output [`DWIDTH-1:0] out_data2, + output [`DWIDTH-1:0] out_data3, + output [`DWIDTH-1:0] out_data4, + output [`DWIDTH-1:0] out_data5, + output [`DWIDTH-1:0] out_data6, + output [`DWIDTH-1:0] out_data7, + output [`DWIDTH-1:0] out_data8, + output [`DWIDTH-1:0] out_data9, + output [`DWIDTH-1:0] out_data10, + output [`DWIDTH-1:0] out_data11, + output [`DWIDTH-1:0] out_data12, + output [`DWIDTH-1:0] out_data13, + output [`DWIDTH-1:0] out_data14, + output [`DWIDTH-1:0] out_data15, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output reg done_norm, + input clk, + input reset +); + +reg in_data_available1; +reg in_data_available2; +reg in_data_available3; +reg in_data_available4; +reg in_data_available5; +reg in_data_available6; +reg in_data_available7; +reg in_data_available8; +reg in_data_available9; +reg in_data_available10; +reg in_data_available11; +reg in_data_available12; +reg in_data_available13; +reg in_data_available14; +reg in_data_available15; + +always @(posedge clk) begin + in_data_available1 <= in_data_available; + in_data_available2 <= in_data_available1; + in_data_available3 <= in_data_available2; + in_data_available4 <= in_data_available3; + in_data_available5 <= in_data_available4; + in_data_available6 <= in_data_available5; + in_data_available7 <= in_data_available6; + in_data_available8 <= in_data_available7; + in_data_available9 <= in_data_available8; + in_data_available10 <= in_data_available9; + in_data_available11 <= in_data_available10; + in_data_available12 <= in_data_available11; + in_data_available13 <= in_data_available12; + in_data_available14 <= in_data_available13; + in_data_available15 <= in_data_available14; +end + +wire out_data_available_internal; +wire out_data_available_final; + +reg [`DWIDTH-1:0] done_count; + +assign out_data_available = (enable_norm) ? out_data_available_internal : in_data_available; + +always @(posedge clk) begin + if (reset) begin + done_norm <= 0; + done_count <= 0; + end + if (done_count == 4) begin + done_norm <= 1; + end + if (out_data_available_final == 1) begin + done_count <= done_count + 1; + end +end + +norm_sub norm0( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available), + .inp_data(inp_data0), + .out_data(out_data0), + .out_data_available(out_data_available_internal), + .validity_mask(validity_mask[0]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC1; +norm_sub norm1( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available1), + .inp_data(inp_data1), + .out_data(out_data1), + .out_data_available(out_data_available_NC1), + .validity_mask(validity_mask[1]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC2; +norm_sub norm2( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available2), + .inp_data(inp_data2), + .out_data(out_data2), + .out_data_available(out_data_available_NC2), + .validity_mask(validity_mask[2]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC3; +norm_sub norm3( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available3), + .inp_data(inp_data3), + .out_data(out_data3), + .out_data_available(out_data_available_NC3), + .validity_mask(validity_mask[3]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC4; +norm_sub norm4( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available4), + .inp_data(inp_data4), + .out_data(out_data4), + .out_data_available(out_data_available_NC4), + .validity_mask(validity_mask[4]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC5; +norm_sub norm5( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available5), + .inp_data(inp_data5), + .out_data(out_data5), + .out_data_available(out_data_available_NC5), + .validity_mask(validity_mask[5]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC6; +norm_sub norm6( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available6), + .inp_data(inp_data6), + .out_data(out_data6), + .out_data_available(out_data_available_NC6), + .validity_mask(validity_mask[6]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC7; +norm_sub norm7( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available7), + .inp_data(inp_data7), + .out_data(out_data7), + .out_data_available(out_data_available_NC7), + .validity_mask(validity_mask[7]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC8; +norm_sub norm8( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available8), + .inp_data(inp_data8), + .out_data(out_data8), + .out_data_available(out_data_available_NC8), + .validity_mask(validity_mask[8]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC9; +norm_sub norm9( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available9), + .inp_data(inp_data9), + .out_data(out_data9), + .out_data_available(out_data_available_NC9), + .validity_mask(validity_mask[9]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC10; +norm_sub norm10( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available10), + .inp_data(inp_data10), + .out_data(out_data10), + .out_data_available(out_data_available_NC10), + .validity_mask(validity_mask[10]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC11; +norm_sub norm11( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available11), + .inp_data(inp_data11), + .out_data(out_data11), + .out_data_available(out_data_available_NC11), + .validity_mask(validity_mask[11]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC12; +norm_sub norm12( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available12), + .inp_data(inp_data12), + .out_data(out_data12), + .out_data_available(out_data_available_NC12), + .validity_mask(validity_mask[12]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC13; +norm_sub norm13( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available13), + .inp_data(inp_data13), + .out_data(out_data13), + .out_data_available(out_data_available_NC13), + .validity_mask(validity_mask[13]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC14; +norm_sub norm14( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available14), + .inp_data(inp_data14), + .out_data(out_data14), + .out_data_available(out_data_available_NC14), + .validity_mask(validity_mask[14]), + .clk(clk), + .reset(reset) +); + +norm_sub norm15( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(in_data_available15), + .inp_data(inp_data15), + .out_data(out_data15), + .out_data_available(out_data_available_final), + .validity_mask(validity_mask[15]), + .clk(clk), + .reset(reset) +); + +endmodule + +module norm_sub( + input enable_norm, + input [`DWIDTH-1:0] mean, + input [`DWIDTH-1:0] inv_var, + input in_data_available, + input [`DWIDTH-1:0] inp_data, + output [`DWIDTH-1:0] out_data, + output out_data_available, + input validity_mask, + input clk, + input reset +); + +reg out_data_available_internal; +wire [`DWIDTH-1:0] out_data_internal; +reg [`DWIDTH-1:0] mean_applied_data; +reg [`DWIDTH-1:0] variance_applied_data; +reg norm_in_progress; + +//Muxing logic to handle the case when this block is disabled +assign out_data_available = (enable_norm) ? out_data_available_internal : in_data_available; +assign out_data = (enable_norm) ? out_data_internal : inp_data; + +always @(posedge clk) begin + if ((reset || ~enable_norm)) begin + mean_applied_data <= 0; + variance_applied_data <= 0; + end else if (in_data_available||norm_in_progress) begin + //Let's apply mean and variance as the input data comes in. + //We have a pipeline here. First stage does the add (to apply the mean) + //and second stage does the multiplication (to apply the variance). + //Note: the following loop is not a loop across multiple columns of data. + //This loop will run in 2 cycle on the same column of data that comes into + //this module in 1 clock. + if (validity_mask == 1'b1) begin + mean_applied_data <= (inp_data - mean); + variance_applied_data <= (mean_applied_data * inv_var); + end + else begin + mean_applied_data <= (inp_data); + variance_applied_data <= (mean_applied_data); + end + end + else begin + mean_applied_data <= 0; + variance_applied_data <= 0; + end +end + +//The data is normalized in two cycles so we are shifting in_data_available by 2 to generate out_data_available +always @(posedge clk) begin + norm_in_progress <= in_data_available; + out_data_available_internal <= norm_in_progress; +end + +assign out_data_internal = variance_applied_data; + +endmodule + +//Simple sual port RAM is not understood by VTR +`ifdef QUARTUS +////////////////////////////////// +// Simple dual port RAM +////////////////////////////////// +module simple_ram ( + addr0, + d0, + we0, + addr1, + q1, + clk); + +parameter AW = 11; +parameter MW = 8; +parameter DW = 8; + +input [AW-1:0] addr0; +input [AW-1:0] addr1; +input [MW*DW-1:0] d0; +input [MW-1:0] we0; +output reg [MW*DW-1:0] q1; +input clk; + +wire we0_coalesced; +assign we0_coalesced = |we0; + +reg [MW*DW-1:0] ram[((1 << AW)-1):0]; + +always @(posedge clk) begin + if (we0_coalesced) ram[addr0] <= d0; +end + +always @(posedge clk) begin + q1 <= ram[addr1]; +end + +endmodule + +`endif + +////////////////////////////////// +// Dual port RAM +////////////////////////////////// +module ram ( + addr0, + d0, + we0, + q0, + addr1, + d1, + we1, + q1, + clk); + +parameter AW = 11; +parameter MW = 8; +parameter DW = 8; + +input [AW-1:0] addr0; +input [AW-1:0] addr1; +input [MW*DW-1:0] d0; +input [MW*DW-1:0] d1; +input [MW-1:0] we0; +input [MW-1:0] we1; +output reg [MW*DW-1:0] q0; +output reg [MW*DW-1:0] q1; +input clk; + +wire we0_coalesced; +assign we0_coalesced = |we0; +wire we1_coalesced; +assign we1_coalesced = |we1; + +`ifndef hard_mem +reg [MW*DW-1:0] ram[((1 << AW)-1):0]; + +always @(posedge clk) begin + if (we0_coalesced) ram[addr0] <= d0; + q0 <= ram[addr0]; +end + +always @(posedge clk) begin + if (we1_coalesced) ram[addr1] <= d1; + q1 <= ram[addr1]; +end + +`else + +defparam u_dual_port_ram.ADDR_WIDTH = AW; +defparam u_dual_port_ram.DATA_WIDTH = MW*DW; + +dual_port_ram u_dual_port_ram( +.addr1(addr0), +.we1(we0_coalesced), +.data1(d0), +.out1(q0), +.addr2(addr1), +.we2(we1_coalesced), +.data2(d1), +.out2(q1), +.clk(clk) +); + +`endif + +endmodule + +//Top level state machine +module control( + input clk, + input reset, + input start_tpu, + input enable_matmul, + input enable_norm, + input enable_activation, + input enable_pool, + output reg start_mat_mul, + input done_mat_mul, + input done_norm, + input done_pool, + input done_activation, + input save_output_to_accum, + output reg done_tpu +); + +reg [3:0] state; + +`define STATE_INIT 4'b0000 +`define STATE_MATMUL 4'b0001 +`define STATE_NORM 4'b0010 +`define STATE_POOL 4'b0011 +`define STATE_ACTIVATION 4'b0100 +`define STATE_DONE 4'b0101 + +////////////////////////////////////////////////////// +// Assumption: We will always run matmul first. That is, matmul is not optional. +// The other blocks - norm, act, pool - are optional. +// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation +////////////////////////////////////////////////////// + +always @( posedge clk) begin + if (reset) begin + state <= `STATE_INIT; + start_mat_mul <= 1'b0; + done_tpu <= 1'b0; + end else begin + case (state) + `STATE_INIT: begin + if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin + if (enable_matmul == 1'b1) begin + start_mat_mul <= 1'b1; + state <= `STATE_MATMUL; + end + end + end + + //start_mat_mul is kinda used as a reset in some logic + //inside the matmul unit. So, we can't make it 0 right away after + //asserting it. + `STATE_MATMUL: begin + if (done_mat_mul == 1'b1) begin + start_mat_mul <= 1'b0; + if(save_output_to_accum) begin + state <= `STATE_DONE; + end + else if (enable_norm) begin + state <= `STATE_NORM; + end + else if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + else begin + start_mat_mul <= 1'b1; + end + end + + `STATE_NORM: begin + if (done_norm == 1'b1) begin + if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_POOL: begin + if (done_pool == 1'b1) begin + if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_ACTIVATION: begin + if (done_activation == 1'b1) begin + state <= `STATE_DONE; + end + end + + `STATE_DONE: begin + //We need to write start_tpu to 0 in the CFG block to get out of this state + if (start_tpu == 1'b0) begin + state <= `STATE_INIT; + done_tpu <= 0; + end + else begin + done_tpu <= 1; + end + end + endcase + end +end +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM generate_accum.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// +module accumulator ( + clk, + resetn, + start_waddr_accum0, + wdata_accum0, + wdata_accum1, + wdata_accum2, + wdata_accum3, + wdata_accum4, + wdata_accum5, + wdata_accum6, + wdata_accum7, + wdata_accum8, + wdata_accum9, + wdata_accum10, + wdata_accum11, + wdata_accum12, + wdata_accum13, + wdata_accum14, + wdata_accum15, + raddr_accum0_pool, + raddr_accum1_pool, + raddr_accum2_pool, + raddr_accum3_pool, + raddr_accum4_pool, + raddr_accum5_pool, + raddr_accum6_pool, + raddr_accum7_pool, + raddr_accum8_pool, + raddr_accum9_pool, + raddr_accum10_pool, + raddr_accum11_pool, + raddr_accum12_pool, + raddr_accum13_pool, + raddr_accum14_pool, + raddr_accum15_pool, + rdata_accum0_pool, + rdata_accum1_pool, + rdata_accum2_pool, + rdata_accum3_pool, + rdata_accum4_pool, + rdata_accum5_pool, + rdata_accum6_pool, + rdata_accum7_pool, + rdata_accum8_pool, + rdata_accum9_pool, + rdata_accum10_pool, + rdata_accum11_pool, + rdata_accum12_pool, + rdata_accum13_pool, + rdata_accum14_pool, + rdata_accum15_pool, + wdata_available, + k_dimension, + buffer_select, + start_pooling, + done_pooling +); + +input clk; +input resetn; +input [`AWIDTH-1:0] start_waddr_accum0; +input [`DWIDTH-1:0] wdata_accum0; +input [`DWIDTH-1:0] wdata_accum1; +input [`DWIDTH-1:0] wdata_accum2; +input [`DWIDTH-1:0] wdata_accum3; +input [`DWIDTH-1:0] wdata_accum4; +input [`DWIDTH-1:0] wdata_accum5; +input [`DWIDTH-1:0] wdata_accum6; +input [`DWIDTH-1:0] wdata_accum7; +input [`DWIDTH-1:0] wdata_accum8; +input [`DWIDTH-1:0] wdata_accum9; +input [`DWIDTH-1:0] wdata_accum10; +input [`DWIDTH-1:0] wdata_accum11; +input [`DWIDTH-1:0] wdata_accum12; +input [`DWIDTH-1:0] wdata_accum13; +input [`DWIDTH-1:0] wdata_accum14; +input [`DWIDTH-1:0] wdata_accum15; +input [`AWIDTH-1:0] raddr_accum0_pool; +input [`AWIDTH-1:0] raddr_accum1_pool; +input [`AWIDTH-1:0] raddr_accum2_pool; +input [`AWIDTH-1:0] raddr_accum3_pool; +input [`AWIDTH-1:0] raddr_accum4_pool; +input [`AWIDTH-1:0] raddr_accum5_pool; +input [`AWIDTH-1:0] raddr_accum6_pool; +input [`AWIDTH-1:0] raddr_accum7_pool; +input [`AWIDTH-1:0] raddr_accum8_pool; +input [`AWIDTH-1:0] raddr_accum9_pool; +input [`AWIDTH-1:0] raddr_accum10_pool; +input [`AWIDTH-1:0] raddr_accum11_pool; +input [`AWIDTH-1:0] raddr_accum12_pool; +input [`AWIDTH-1:0] raddr_accum13_pool; +input [`AWIDTH-1:0] raddr_accum14_pool; +input [`AWIDTH-1:0] raddr_accum15_pool; +output [`DWIDTH-1:0] rdata_accum0_pool; +output [`DWIDTH-1:0] rdata_accum1_pool; +output [`DWIDTH-1:0] rdata_accum2_pool; +output [`DWIDTH-1:0] rdata_accum3_pool; +output [`DWIDTH-1:0] rdata_accum4_pool; +output [`DWIDTH-1:0] rdata_accum5_pool; +output [`DWIDTH-1:0] rdata_accum6_pool; +output [`DWIDTH-1:0] rdata_accum7_pool; +output [`DWIDTH-1:0] rdata_accum8_pool; +output [`DWIDTH-1:0] rdata_accum9_pool; +output [`DWIDTH-1:0] rdata_accum10_pool; +output [`DWIDTH-1:0] rdata_accum11_pool; +output [`DWIDTH-1:0] rdata_accum12_pool; +output [`DWIDTH-1:0] rdata_accum13_pool; +output [`DWIDTH-1:0] rdata_accum14_pool; +output [`DWIDTH-1:0] rdata_accum15_pool; +input wdata_available; +input [7:0] k_dimension; // Number of columns in Matrix A | Number of rows in Matrix B (Assumption: Maximum = 256, can be changed accordingly) +input buffer_select; +output start_pooling; +output done_pooling; + + +parameter MWIDTH = 1; + +reg wdata_available1; +reg wdata_available2; +reg wdata_available3; +reg wdata_available4; +reg wdata_available5; +reg wdata_available6; +reg wdata_available7; +reg wdata_available8; +reg wdata_available9; +reg wdata_available10; +reg wdata_available11; +reg wdata_available12; +reg wdata_available13; +reg wdata_available14; +reg wdata_available15; + +always @ (posedge clk) begin + wdata_available1 <= wdata_available; + wdata_available2 <= wdata_available1; + wdata_available3 <= wdata_available2; + wdata_available4 <= wdata_available3; + wdata_available5 <= wdata_available4; + wdata_available6 <= wdata_available5; + wdata_available7 <= wdata_available6; + wdata_available8 <= wdata_available7; + wdata_available9 <= wdata_available8; + wdata_available10 <= wdata_available9; + wdata_available11 <= wdata_available10; + wdata_available12 <= wdata_available11; + wdata_available13 <= wdata_available12; + wdata_available14 <= wdata_available13; + wdata_available15 <= wdata_available14; +end + +wire wdata_en_ping0; +wire wdata_en_ping1; +wire wdata_en_ping2; +wire wdata_en_ping3; +wire wdata_en_ping4; +wire wdata_en_ping5; +wire wdata_en_ping6; +wire wdata_en_ping7; +wire wdata_en_ping8; +wire wdata_en_ping9; +wire wdata_en_ping10; +wire wdata_en_ping11; +wire wdata_en_ping12; +wire wdata_en_ping13; +wire wdata_en_ping14; +wire wdata_en_ping15; +wire wdata_en_pong0; +wire wdata_en_pong1; +wire wdata_en_pong2; +wire wdata_en_pong3; +wire wdata_en_pong4; +wire wdata_en_pong5; +wire wdata_en_pong6; +wire wdata_en_pong7; +wire wdata_en_pong8; +wire wdata_en_pong9; +wire wdata_en_pong10; +wire wdata_en_pong11; +wire wdata_en_pong12; +wire wdata_en_pong13; +wire wdata_en_pong14; +wire wdata_en_pong15; + +assign wdata_en_ping0 = wdata_available & buffer_select; +assign wdata_en_ping1 = wdata_available1 & buffer_select; +assign wdata_en_ping2 = wdata_available2 & buffer_select; +assign wdata_en_ping3 = wdata_available3 & buffer_select; +assign wdata_en_ping4 = wdata_available4 & buffer_select; +assign wdata_en_ping5 = wdata_available5 & buffer_select; +assign wdata_en_ping6 = wdata_available6 & buffer_select; +assign wdata_en_ping7 = wdata_available7 & buffer_select; +assign wdata_en_ping8 = wdata_available8 & buffer_select; +assign wdata_en_ping9 = wdata_available9 & buffer_select; +assign wdata_en_ping10 = wdata_available10 & buffer_select; +assign wdata_en_ping11 = wdata_available11 & buffer_select; +assign wdata_en_ping12 = wdata_available12 & buffer_select; +assign wdata_en_ping13 = wdata_available13 & buffer_select; +assign wdata_en_ping14 = wdata_available14 & buffer_select; +assign wdata_en_ping15 = wdata_available15 & buffer_select; + +assign wdata_en_pong0 = wdata_available & ~buffer_select; +assign wdata_en_pong1 = wdata_available1 & ~buffer_select; +assign wdata_en_pong2 = wdata_available2 & ~buffer_select; +assign wdata_en_pong3 = wdata_available3 & ~buffer_select; +assign wdata_en_pong4 = wdata_available4 & ~buffer_select; +assign wdata_en_pong5 = wdata_available5 & ~buffer_select; +assign wdata_en_pong6 = wdata_available6 & ~buffer_select; +assign wdata_en_pong7 = wdata_available7 & ~buffer_select; +assign wdata_en_pong8 = wdata_available8 & ~buffer_select; +assign wdata_en_pong9 = wdata_available9 & ~buffer_select; +assign wdata_en_pong10 = wdata_available10 & ~buffer_select; +assign wdata_en_pong11 = wdata_available11 & ~buffer_select; +assign wdata_en_pong12 = wdata_available12 & ~buffer_select; +assign wdata_en_pong13 = wdata_available13 & ~buffer_select; +assign wdata_en_pong14 = wdata_available14 & ~buffer_select; +assign wdata_en_pong15 = wdata_available15 & ~buffer_select; + +reg [7:0] addr_counter; +reg [`AWIDTH-1:0] waddr_accum0; +reg [`AWIDTH-1:0] waddr_accum1; +reg [`AWIDTH-1:0] waddr_accum2; +reg [`AWIDTH-1:0] waddr_accum3; +reg [`AWIDTH-1:0] waddr_accum4; +reg [`AWIDTH-1:0] waddr_accum5; +reg [`AWIDTH-1:0] waddr_accum6; +reg [`AWIDTH-1:0] waddr_accum7; +reg [`AWIDTH-1:0] waddr_accum8; +reg [`AWIDTH-1:0] waddr_accum9; +reg [`AWIDTH-1:0] waddr_accum10; +reg [`AWIDTH-1:0] waddr_accum11; +reg [`AWIDTH-1:0] waddr_accum12; +reg [`AWIDTH-1:0] waddr_accum13; +reg [`AWIDTH-1:0] waddr_accum14; +reg [`AWIDTH-1:0] waddr_accum15; +reg add_accum_mux0; +reg add_accum_mux1; +reg add_accum_mux2; +reg add_accum_mux3; +reg add_accum_mux4; +reg add_accum_mux5; +reg add_accum_mux6; +reg add_accum_mux7; +reg add_accum_mux8; +reg add_accum_mux9; +reg add_accum_mux10; +reg add_accum_mux11; +reg add_accum_mux12; +reg add_accum_mux13; +reg add_accum_mux14; +reg add_accum_mux15; + +always @ (posedge clk) begin + if (~wdata_available | (addr_counter == (k_dimension-1))) begin + add_accum_mux0 <= 0; + addr_counter <= 0; + end + else if (addr_counter == (`MAT_MUL_SIZE-1) & k_dimension != `MAT_MUL_SIZE) begin + add_accum_mux0 <= 1; + addr_counter <= addr_counter + 1; + end + else if (wdata_available) + addr_counter <= addr_counter + 1; +end + +reg start_pooling; +reg done_pooling; +reg [7:0] start_pooling_count; +always @ (posedge clk) begin + if (~resetn) + start_pooling <= 0; + //TODO: Note the hardcodign of value below. + //This value (8'd14) is supposed to be 2*MATMUL_SIZE-2. + //For 8x8 matmul, this is 8'd14 + //For 16x16 matmul, this should be 8'd30 + //For 32x32 matmul, this should be 8'd62 + else if (start_pooling_count > 8'd30) begin + start_pooling <= 0; + done_pooling <= 1; + end + else if (waddr_accum2 != 0 & wdata_available2 == 0) + start_pooling <= 1; +end + +always @ (posedge clk) begin + if (~resetn) + start_pooling_count <= 0; + else if (start_pooling) + start_pooling_count <= start_pooling_count + 1; +end + +reg buffer_select_accum; +wire buffer_select_pool; +reg start_pooling_d1; + +always @ (posedge clk) begin + if (buffer_select_pool) + buffer_select_accum <= 0; + else + buffer_select_accum <= 1; +end + +always @ (posedge clk) begin + start_pooling_d1 <= start_pooling; +end + +assign buffer_select_pool = start_pooling | start_pooling_d1; + +always @ (posedge clk) begin + add_accum_mux1 <= add_accum_mux0; + add_accum_mux2 <= add_accum_mux1; + add_accum_mux3 <= add_accum_mux2; + add_accum_mux4 <= add_accum_mux3; + add_accum_mux5 <= add_accum_mux4; + add_accum_mux6 <= add_accum_mux5; + add_accum_mux7 <= add_accum_mux6; + add_accum_mux8 <= add_accum_mux7; + add_accum_mux9 <= add_accum_mux8; + add_accum_mux10 <= add_accum_mux9; + add_accum_mux11 <= add_accum_mux10; + add_accum_mux12 <= add_accum_mux11; + add_accum_mux13 <= add_accum_mux12; + add_accum_mux14 <= add_accum_mux13; + add_accum_mux15 <= add_accum_mux14; +end + +reg [7:0] waddr_kdim; + +always @ (posedge clk) begin + if (~resetn) + waddr_accum0 <= start_waddr_accum0; + else if (((addr_counter & (`MAT_MUL_SIZE-1)) == (`MAT_MUL_SIZE-1)) & (waddr_kdim > 1)) begin + waddr_accum0 <= waddr_accum0 - (`MAT_MUL_SIZE -1); + end + else if (wdata_available) + waddr_accum0 <= waddr_accum0 + 1; +end + +always @ (posedge clk) begin + if (~resetn | (((addr_counter & (`MAT_MUL_SIZE-1)) == (`MAT_MUL_SIZE-1)) & (waddr_kdim == 1))) begin + waddr_kdim <= k_dimension >> `LOG2_MAT_MUL_SIZE; + end + else if (((addr_counter & (`MAT_MUL_SIZE-1)) == (`MAT_MUL_SIZE-1)) & (waddr_kdim > 1)) begin + waddr_kdim <= waddr_kdim - 1; + end +end + +always @ (posedge clk) begin + waddr_accum1 <= waddr_accum0; + waddr_accum2 <= waddr_accum1; + waddr_accum3 <= waddr_accum2; + waddr_accum4 <= waddr_accum3; + waddr_accum5 <= waddr_accum4; + waddr_accum6 <= waddr_accum5; + waddr_accum7 <= waddr_accum6; + waddr_accum8 <= waddr_accum7; + waddr_accum9 <= waddr_accum8; + waddr_accum10 <= waddr_accum9; + waddr_accum11 <= waddr_accum10; + waddr_accum12 <= waddr_accum11; + waddr_accum13 <= waddr_accum12; + waddr_accum14 <= waddr_accum13; + waddr_accum15 <= waddr_accum14; +end + +// Data going into the Accumulator Adders +wire [`DWIDTH-1:0] wdata_accum0_in; +wire [`DWIDTH-1:0] wdata_accum1_in; +wire [`DWIDTH-1:0] wdata_accum2_in; +wire [`DWIDTH-1:0] wdata_accum3_in; +wire [`DWIDTH-1:0] wdata_accum4_in; +wire [`DWIDTH-1:0] wdata_accum5_in; +wire [`DWIDTH-1:0] wdata_accum6_in; +wire [`DWIDTH-1:0] wdata_accum7_in; +wire [`DWIDTH-1:0] wdata_accum8_in; +wire [`DWIDTH-1:0] wdata_accum9_in; +wire [`DWIDTH-1:0] wdata_accum10_in; +wire [`DWIDTH-1:0] wdata_accum11_in; +wire [`DWIDTH-1:0] wdata_accum12_in; +wire [`DWIDTH-1:0] wdata_accum13_in; +wire [`DWIDTH-1:0] wdata_accum14_in; +wire [`DWIDTH-1:0] wdata_accum15_in; + +// Data written into the PING Accumulators +wire [`DWIDTH-1:0] wdata_accum0_ping; +wire [`DWIDTH-1:0] wdata_accum1_ping; +wire [`DWIDTH-1:0] wdata_accum2_ping; +wire [`DWIDTH-1:0] wdata_accum3_ping; +wire [`DWIDTH-1:0] wdata_accum4_ping; +wire [`DWIDTH-1:0] wdata_accum5_ping; +wire [`DWIDTH-1:0] wdata_accum6_ping; +wire [`DWIDTH-1:0] wdata_accum7_ping; +wire [`DWIDTH-1:0] wdata_accum8_ping; +wire [`DWIDTH-1:0] wdata_accum9_ping; +wire [`DWIDTH-1:0] wdata_accum10_ping; +wire [`DWIDTH-1:0] wdata_accum11_ping; +wire [`DWIDTH-1:0] wdata_accum12_ping; +wire [`DWIDTH-1:0] wdata_accum13_ping; +wire [`DWIDTH-1:0] wdata_accum14_ping; +wire [`DWIDTH-1:0] wdata_accum15_ping; + +wire [`AWIDTH-1:0] raddr_buffer0; +wire [`AWIDTH-1:0] raddr_buffer1; +wire [`AWIDTH-1:0] raddr_buffer2; +wire [`AWIDTH-1:0] raddr_buffer3; +wire [`AWIDTH-1:0] raddr_buffer4; +wire [`AWIDTH-1:0] raddr_buffer5; +wire [`AWIDTH-1:0] raddr_buffer6; +wire [`AWIDTH-1:0] raddr_buffer7; +wire [`AWIDTH-1:0] raddr_buffer8; +wire [`AWIDTH-1:0] raddr_buffer9; +wire [`AWIDTH-1:0] raddr_buffer10; +wire [`AWIDTH-1:0] raddr_buffer11; +wire [`AWIDTH-1:0] raddr_buffer12; +wire [`AWIDTH-1:0] raddr_buffer13; +wire [`AWIDTH-1:0] raddr_buffer14; +wire [`AWIDTH-1:0] raddr_buffer15; + +wire [`DWIDTH-1:0] rdata_buffer0; +wire [`DWIDTH-1:0] rdata_buffer1; +wire [`DWIDTH-1:0] rdata_buffer2; +wire [`DWIDTH-1:0] rdata_buffer3; +wire [`DWIDTH-1:0] rdata_buffer4; +wire [`DWIDTH-1:0] rdata_buffer5; +wire [`DWIDTH-1:0] rdata_buffer6; +wire [`DWIDTH-1:0] rdata_buffer7; +wire [`DWIDTH-1:0] rdata_buffer8; +wire [`DWIDTH-1:0] rdata_buffer9; +wire [`DWIDTH-1:0] rdata_buffer10; +wire [`DWIDTH-1:0] rdata_buffer11; +wire [`DWIDTH-1:0] rdata_buffer12; +wire [`DWIDTH-1:0] rdata_buffer13; +wire [`DWIDTH-1:0] rdata_buffer14; +wire [`DWIDTH-1:0] rdata_buffer15; + +wire [`DWIDTH-1:0] rdata_buffer0_pong; +wire [`DWIDTH-1:0] rdata_buffer1_pong; +wire [`DWIDTH-1:0] rdata_buffer2_pong; +wire [`DWIDTH-1:0] rdata_buffer3_pong; +wire [`DWIDTH-1:0] rdata_buffer4_pong; +wire [`DWIDTH-1:0] rdata_buffer5_pong; +wire [`DWIDTH-1:0] rdata_buffer6_pong; +wire [`DWIDTH-1:0] rdata_buffer7_pong; +wire [`DWIDTH-1:0] rdata_buffer8_pong; +wire [`DWIDTH-1:0] rdata_buffer9_pong; +wire [`DWIDTH-1:0] rdata_buffer10_pong; +wire [`DWIDTH-1:0] rdata_buffer11_pong; +wire [`DWIDTH-1:0] rdata_buffer12_pong; +wire [`DWIDTH-1:0] rdata_buffer13_pong; +wire [`DWIDTH-1:0] rdata_buffer14_pong; +wire [`DWIDTH-1:0] rdata_buffer15_pong; + +// Based on the Accumulator Adder MUX select signal either 0 or data read from the RAM goes into the Adder +assign wdata_accum0_in = (~add_accum_mux0)? 8'b0 : (buffer_select)? rdata_buffer0 : rdata_buffer0_pong; +assign wdata_accum1_in = (~add_accum_mux1)? 8'b0 : (buffer_select)? rdata_buffer1 : rdata_buffer1_pong; +assign wdata_accum2_in = (~add_accum_mux2)? 8'b0 : (buffer_select)? rdata_buffer2 : rdata_buffer2_pong; +assign wdata_accum3_in = (~add_accum_mux3)? 8'b0 : (buffer_select)? rdata_buffer3 : rdata_buffer3_pong; +assign wdata_accum4_in = (~add_accum_mux4)? 8'b0 : (buffer_select)? rdata_buffer4 : rdata_buffer4_pong; +assign wdata_accum5_in = (~add_accum_mux5)? 8'b0 : (buffer_select)? rdata_buffer5 : rdata_buffer5_pong; +assign wdata_accum6_in = (~add_accum_mux6)? 8'b0 : (buffer_select)? rdata_buffer6 : rdata_buffer6_pong; +assign wdata_accum7_in = (~add_accum_mux7)? 8'b0 : (buffer_select)? rdata_buffer7 : rdata_buffer7_pong; +assign wdata_accum8_in = (~add_accum_mux8)? 8'b0 : (buffer_select)? rdata_buffer8 : rdata_buffer8_pong; +assign wdata_accum9_in = (~add_accum_mux9)? 8'b0 : (buffer_select)? rdata_buffer9 : rdata_buffer9_pong; +assign wdata_accum10_in = (~add_accum_mux10)? 8'b0 : (buffer_select)? rdata_buffer10 : rdata_buffer10_pong; +assign wdata_accum11_in = (~add_accum_mux11)? 8'b0 : (buffer_select)? rdata_buffer11 : rdata_buffer11_pong; +assign wdata_accum12_in = (~add_accum_mux12)? 8'b0 : (buffer_select)? rdata_buffer12 : rdata_buffer12_pong; +assign wdata_accum13_in = (~add_accum_mux13)? 8'b0 : (buffer_select)? rdata_buffer13 : rdata_buffer13_pong; +assign wdata_accum14_in = (~add_accum_mux14)? 8'b0 : (buffer_select)? rdata_buffer14 : rdata_buffer14_pong; +assign wdata_accum15_in = (~add_accum_mux15)? 8'b0 : (buffer_select)? rdata_buffer15 : rdata_buffer15_pong; + +reg [`AWIDTH-1:0] raddr_accum0; +reg [`AWIDTH-1:0] raddr_accum1; +reg [`AWIDTH-1:0] raddr_accum2; +reg [`AWIDTH-1:0] raddr_accum3; +reg [`AWIDTH-1:0] raddr_accum4; +reg [`AWIDTH-1:0] raddr_accum5; +reg [`AWIDTH-1:0] raddr_accum6; +reg [`AWIDTH-1:0] raddr_accum7; +reg [`AWIDTH-1:0] raddr_accum8; +reg [`AWIDTH-1:0] raddr_accum9; +reg [`AWIDTH-1:0] raddr_accum10; +reg [`AWIDTH-1:0] raddr_accum11; +reg [`AWIDTH-1:0] raddr_accum12; +reg [`AWIDTH-1:0] raddr_accum13; +reg [`AWIDTH-1:0] raddr_accum14; +reg [`AWIDTH-1:0] raddr_accum15; + +// Start reading the address written to after 15 clock cycles to calculate partial sums +always @ (posedge clk) begin + raddr_accum0 <= waddr_accum14; // waddr_accum14 = (waddr_accum0 delayed by 14 clock cycles) + raddr_accum1 <= raddr_accum0; + raddr_accum2 <= raddr_accum1; + raddr_accum3 <= raddr_accum2; + raddr_accum4 <= raddr_accum3; + raddr_accum5 <= raddr_accum4; + raddr_accum6 <= raddr_accum5; + raddr_accum7 <= raddr_accum6; + raddr_accum8 <= raddr_accum7; + raddr_accum9 <= raddr_accum8; + raddr_accum10 <= raddr_accum9; + raddr_accum11 <= raddr_accum10; + raddr_accum12 <= raddr_accum11; + raddr_accum13 <= raddr_accum12; + raddr_accum14 <= raddr_accum13; + raddr_accum15 <= raddr_accum14; +end + +// Port 0 for each RAM is used for writing the data coming from the matmul as of now, not used for reading +wire [`DWIDTH-1:0] accum0_ping_q0_NC; +wire [`DWIDTH-1:0] accum1_ping_q0_NC; +wire [`DWIDTH-1:0] accum2_ping_q0_NC; +wire [`DWIDTH-1:0] accum3_ping_q0_NC; +wire [`DWIDTH-1:0] accum4_ping_q0_NC; +wire [`DWIDTH-1:0] accum5_ping_q0_NC; +wire [`DWIDTH-1:0] accum6_ping_q0_NC; +wire [`DWIDTH-1:0] accum7_ping_q0_NC; +wire [`DWIDTH-1:0] accum8_ping_q0_NC; +wire [`DWIDTH-1:0] accum9_ping_q0_NC; +wire [`DWIDTH-1:0] accum10_ping_q0_NC; +wire [`DWIDTH-1:0] accum11_ping_q0_NC; +wire [`DWIDTH-1:0] accum12_ping_q0_NC; +wire [`DWIDTH-1:0] accum13_ping_q0_NC; +wire [`DWIDTH-1:0] accum14_ping_q0_NC; +wire [`DWIDTH-1:0] accum15_ping_q0_NC; +wire [`DWIDTH-1:0] accum0_pong_q0_NC; +wire [`DWIDTH-1:0] accum1_pong_q0_NC; +wire [`DWIDTH-1:0] accum2_pong_q0_NC; +wire [`DWIDTH-1:0] accum3_pong_q0_NC; +wire [`DWIDTH-1:0] accum4_pong_q0_NC; +wire [`DWIDTH-1:0] accum5_pong_q0_NC; +wire [`DWIDTH-1:0] accum6_pong_q0_NC; +wire [`DWIDTH-1:0] accum7_pong_q0_NC; +wire [`DWIDTH-1:0] accum8_pong_q0_NC; +wire [`DWIDTH-1:0] accum9_pong_q0_NC; +wire [`DWIDTH-1:0] accum10_pong_q0_NC; +wire [`DWIDTH-1:0] accum11_pong_q0_NC; +wire [`DWIDTH-1:0] accum12_pong_q0_NC; +wire [`DWIDTH-1:0] accum13_pong_q0_NC; +wire [`DWIDTH-1:0] accum14_pong_q0_NC; +wire [`DWIDTH-1:0] accum15_pong_q0_NC; + +reg buffer_select_pool1; +reg buffer_select_pool2; +reg buffer_select_pool3; +reg buffer_select_pool4; +reg buffer_select_pool5; +reg buffer_select_pool6; +reg buffer_select_pool7; +reg buffer_select_pool8; +reg buffer_select_pool9; +reg buffer_select_pool10; +reg buffer_select_pool11; +reg buffer_select_pool12; +reg buffer_select_pool13; +reg buffer_select_pool14; +reg buffer_select_pool15; + +always @ (posedge clk) begin +buffer_select_pool1 <= buffer_select_pool; +buffer_select_pool2 <= buffer_select_pool1; +buffer_select_pool3 <= buffer_select_pool2; +buffer_select_pool4 <= buffer_select_pool3; +buffer_select_pool5 <= buffer_select_pool4; +buffer_select_pool6 <= buffer_select_pool5; +buffer_select_pool7 <= buffer_select_pool6; +buffer_select_pool8 <= buffer_select_pool7; +buffer_select_pool9 <= buffer_select_pool8; +buffer_select_pool10 <= buffer_select_pool9; +buffer_select_pool11 <= buffer_select_pool10; +buffer_select_pool12 <= buffer_select_pool11; +buffer_select_pool13 <= buffer_select_pool12; +buffer_select_pool14 <= buffer_select_pool13; +buffer_select_pool15 <= buffer_select_pool14; +end + +reg buffer_select_accum1; +reg buffer_select_accum2; +reg buffer_select_accum3; +reg buffer_select_accum4; +reg buffer_select_accum5; +reg buffer_select_accum6; +reg buffer_select_accum7; +reg buffer_select_accum8; +reg buffer_select_accum9; +reg buffer_select_accum10; +reg buffer_select_accum11; +reg buffer_select_accum12; +reg buffer_select_accum13; +reg buffer_select_accum14; +reg buffer_select_accum15; + +always @ (posedge clk) begin +buffer_select_accum1 <= buffer_select_accum; +buffer_select_accum2 <= buffer_select_accum1; +buffer_select_accum3 <= buffer_select_accum2; +buffer_select_accum4 <= buffer_select_accum3; +buffer_select_accum5 <= buffer_select_accum4; +buffer_select_accum6 <= buffer_select_accum5; +buffer_select_accum7 <= buffer_select_accum6; +buffer_select_accum8 <= buffer_select_accum7; +buffer_select_accum9 <= buffer_select_accum8; +buffer_select_accum10 <= buffer_select_accum9; +buffer_select_accum11 <= buffer_select_accum10; +buffer_select_accum12 <= buffer_select_accum11; +buffer_select_accum13 <= buffer_select_accum12; +buffer_select_accum14 <= buffer_select_accum13; +buffer_select_accum15 <= buffer_select_accum14; +end + +assign raddr_buffer0 = (buffer_select_pool)? raddr_accum0_pool : (buffer_select_accum)? raddr_accum0:11'd0; +assign raddr_buffer1 = (buffer_select_pool1)? raddr_accum1_pool : (buffer_select_accum1)? raddr_accum1:11'd0; +assign raddr_buffer2 = (buffer_select_pool2)? raddr_accum2_pool : (buffer_select_accum2)? raddr_accum2:11'd0; +assign raddr_buffer3 = (buffer_select_pool3)? raddr_accum3_pool : (buffer_select_accum3)? raddr_accum3:11'd0; +assign raddr_buffer4 = (buffer_select_pool4)? raddr_accum4_pool : (buffer_select_accum4)? raddr_accum4:11'd0; +assign raddr_buffer5 = (buffer_select_pool5)? raddr_accum5_pool : (buffer_select_accum5)? raddr_accum5:11'd0; +assign raddr_buffer6 = (buffer_select_pool6)? raddr_accum6_pool : (buffer_select_accum6)? raddr_accum6:11'd0; +assign raddr_buffer7 = (buffer_select_pool7)? raddr_accum7_pool : (buffer_select_accum7)? raddr_accum7:11'd0; +assign raddr_buffer8 = (buffer_select_pool8)? raddr_accum8_pool : (buffer_select_accum8)? raddr_accum8:11'd0; +assign raddr_buffer9 = (buffer_select_pool9)? raddr_accum9_pool : (buffer_select_accum9)? raddr_accum9:11'd0; +assign raddr_buffer10 = (buffer_select_pool10)? raddr_accum10_pool : (buffer_select_accum10)? raddr_accum10:11'd0; +assign raddr_buffer11 = (buffer_select_pool11)? raddr_accum11_pool : (buffer_select_accum11)? raddr_accum11:11'd0; +assign raddr_buffer12 = (buffer_select_pool12)? raddr_accum12_pool : (buffer_select_accum12)? raddr_accum12:11'd0; +assign raddr_buffer13 = (buffer_select_pool13)? raddr_accum13_pool : (buffer_select_accum13)? raddr_accum13:11'd0; +assign raddr_buffer14 = (buffer_select_pool14)? raddr_accum14_pool : (buffer_select_accum14)? raddr_accum14:11'd0; +assign raddr_buffer15 = (buffer_select_pool15)? raddr_accum15_pool : (buffer_select_accum15)? raddr_accum15:11'd0; + +assign rdata_accum0_pool = (buffer_select_pool)? (buffer_select)? rdata_buffer0 : rdata_buffer0_pong : 8'b0; +assign rdata_accum1_pool = (buffer_select_pool1)? (buffer_select)? rdata_buffer1 : rdata_buffer1_pong : 8'b0; +assign rdata_accum2_pool = (buffer_select_pool2)? (buffer_select)? rdata_buffer2 : rdata_buffer2_pong : 8'b0; +assign rdata_accum3_pool = (buffer_select_pool3)? (buffer_select)? rdata_buffer3 : rdata_buffer3_pong : 8'b0; +assign rdata_accum4_pool = (buffer_select_pool4)? (buffer_select)? rdata_buffer4 : rdata_buffer4_pong : 8'b0; +assign rdata_accum5_pool = (buffer_select_pool5)? (buffer_select)? rdata_buffer5 : rdata_buffer5_pong : 8'b0; +assign rdata_accum6_pool = (buffer_select_pool6)? (buffer_select)? rdata_buffer6 : rdata_buffer6_pong : 8'b0; +assign rdata_accum7_pool = (buffer_select_pool7)? (buffer_select)? rdata_buffer7 : rdata_buffer7_pong : 8'b0; +assign rdata_accum8_pool = (buffer_select_pool8)? (buffer_select)? rdata_buffer8 : rdata_buffer8_pong : 8'b0; +assign rdata_accum9_pool = (buffer_select_pool9)? (buffer_select)? rdata_buffer9 : rdata_buffer9_pong : 8'b0; +assign rdata_accum10_pool = (buffer_select_pool10)? (buffer_select)? rdata_buffer10 : rdata_buffer10_pong : 8'b0; +assign rdata_accum11_pool = (buffer_select_pool11)? (buffer_select)? rdata_buffer11 : rdata_buffer11_pong : 8'b0; +assign rdata_accum12_pool = (buffer_select_pool12)? (buffer_select)? rdata_buffer12 : rdata_buffer12_pong : 8'b0; +assign rdata_accum13_pool = (buffer_select_pool13)? (buffer_select)? rdata_buffer13 : rdata_buffer13_pong : 8'b0; +assign rdata_accum14_pool = (buffer_select_pool14)? (buffer_select)? rdata_buffer14 : rdata_buffer14_pong : 8'b0; +assign rdata_accum15_pool = (buffer_select_pool15)? (buffer_select)? rdata_buffer15 : rdata_buffer15_pong : 8'b0; + +//Need to use simple dual port ram for QUARTUS and true dual port RAM for VTR + +`ifdef QUARTUS + +//////////////////////////////////////////////// +// PING ACCUMULATORS +//////////////////////////////////////////////// + +qadd adder_accum_ping0 (wdata_accum0, wdata_accum0_in, wdata_accum0_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum0_ping ( + .addr0(waddr_accum0), + .d0(wdata_accum0_ping), + .we0(wdata_en_ping0), + .addr1(raddr_buffer0), + .q1(rdata_buffer0), + .clk(clk) +); + +qadd adder_accum_ping1 (wdata_accum1, wdata_accum1_in, wdata_accum1_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum1_ping ( + .addr0(waddr_accum1), + .d0(wdata_accum1_ping), + .we0(wdata_en_ping1), + .addr1(raddr_buffer1), + .q1(rdata_buffer1), + .clk(clk) +); + +qadd adder_accum_ping2 (wdata_accum2, wdata_accum2_in, wdata_accum2_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum2_ping ( + .addr0(waddr_accum2), + .d0(wdata_accum2_ping), + .we0(wdata_en_ping2), + .addr1(raddr_buffer2), + .q1(rdata_buffer2), + .clk(clk) +); + +qadd adder_accum_ping3 (wdata_accum3, wdata_accum3_in, wdata_accum3_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum3_ping ( + .addr0(waddr_accum3), + .d0(wdata_accum3_ping), + .we0(wdata_en_ping3), + .addr1(raddr_buffer3), + .q1(rdata_buffer3), + .clk(clk) +); + +qadd adder_accum_ping4 (wdata_accum4, wdata_accum4_in, wdata_accum4_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum4_ping ( + .addr0(waddr_accum4), + .d0(wdata_accum4_ping), + .we0(wdata_en_ping4), + .addr1(raddr_buffer4), + .q1(rdata_buffer4), + .clk(clk) +); + +qadd adder_accum_ping5 (wdata_accum5, wdata_accum5_in, wdata_accum5_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum5_ping ( + .addr0(waddr_accum5), + .d0(wdata_accum5_ping), + .we0(wdata_en_ping5), + .addr1(raddr_buffer5), + .q1(rdata_buffer5), + .clk(clk) +); + +qadd adder_accum_ping6 (wdata_accum6, wdata_accum6_in, wdata_accum6_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum6_ping ( + .addr0(waddr_accum6), + .d0(wdata_accum6_ping), + .we0(wdata_en_ping6), + .addr1(raddr_buffer6), + .q1(rdata_buffer6), + .clk(clk) +); + +qadd adder_accum_ping7 (wdata_accum7, wdata_accum7_in, wdata_accum7_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum7_ping ( + .addr0(waddr_accum7), + .d0(wdata_accum7_ping), + .we0(wdata_en_ping7), + .addr1(raddr_buffer7), + .q1(rdata_buffer7), + .clk(clk) +); + +qadd adder_accum_ping8 (wdata_accum8, wdata_accum8_in, wdata_accum8_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum8_ping ( + .addr0(waddr_accum8), + .d0(wdata_accum8_ping), + .we0(wdata_en_ping8), + .addr1(raddr_buffer8), + .q1(rdata_buffer8), + .clk(clk) +); + +qadd adder_accum_ping9 (wdata_accum9, wdata_accum9_in, wdata_accum9_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum9_ping ( + .addr0(waddr_accum9), + .d0(wdata_accum9_ping), + .we0(wdata_en_ping9), + .addr1(raddr_buffer9), + .q1(rdata_buffer9), + .clk(clk) +); + +qadd adder_accum_ping10 (wdata_accum10, wdata_accum10_in, wdata_accum10_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum10_ping ( + .addr0(waddr_accum10), + .d0(wdata_accum10_ping), + .we0(wdata_en_ping10), + .addr1(raddr_buffer10), + .q1(rdata_buffer10), + .clk(clk) +); + +qadd adder_accum_ping11 (wdata_accum11, wdata_accum11_in, wdata_accum11_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum11_ping ( + .addr0(waddr_accum11), + .d0(wdata_accum11_ping), + .we0(wdata_en_ping11), + .addr1(raddr_buffer11), + .q1(rdata_buffer11), + .clk(clk) +); + +qadd adder_accum_ping12 (wdata_accum12, wdata_accum12_in, wdata_accum12_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum12_ping ( + .addr0(waddr_accum12), + .d0(wdata_accum12_ping), + .we0(wdata_en_ping12), + .addr1(raddr_buffer12), + .q1(rdata_buffer12), + .clk(clk) +); + +qadd adder_accum_ping13 (wdata_accum13, wdata_accum13_in, wdata_accum13_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum13_ping ( + .addr0(waddr_accum13), + .d0(wdata_accum13_ping), + .we0(wdata_en_ping13), + .addr1(raddr_buffer13), + .q1(rdata_buffer13), + .clk(clk) +); + +qadd adder_accum_ping14 (wdata_accum14, wdata_accum14_in, wdata_accum14_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum14_ping ( + .addr0(waddr_accum14), + .d0(wdata_accum14_ping), + .we0(wdata_en_ping14), + .addr1(raddr_buffer14), + .q1(rdata_buffer14), + .clk(clk) +); + +qadd adder_accum_ping15 (wdata_accum15, wdata_accum15_in, wdata_accum15_ping); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum15_ping ( + .addr0(waddr_accum15), + .d0(wdata_accum15_ping), + .we0(wdata_en_ping15), + .addr1(raddr_buffer15), + .q1(rdata_buffer15), + .clk(clk) +); + +wire [`DWIDTH-1:0] wdata_accum0_pong; +wire [`DWIDTH-1:0] wdata_accum1_pong; +wire [`DWIDTH-1:0] wdata_accum2_pong; +wire [`DWIDTH-1:0] wdata_accum3_pong; +wire [`DWIDTH-1:0] wdata_accum4_pong; +wire [`DWIDTH-1:0] wdata_accum5_pong; +wire [`DWIDTH-1:0] wdata_accum6_pong; +wire [`DWIDTH-1:0] wdata_accum7_pong; +wire [`DWIDTH-1:0] wdata_accum8_pong; +wire [`DWIDTH-1:0] wdata_accum9_pong; +wire [`DWIDTH-1:0] wdata_accum10_pong; +wire [`DWIDTH-1:0] wdata_accum11_pong; +wire [`DWIDTH-1:0] wdata_accum12_pong; +wire [`DWIDTH-1:0] wdata_accum13_pong; +wire [`DWIDTH-1:0] wdata_accum14_pong; +wire [`DWIDTH-1:0] wdata_accum15_pong; + +//////////////////////////////////////////////// +// PONG ACCUMULATORS +//////////////////////////////////////////////// + +qadd adder_accum_pong0 (wdata_accum0, wdata_accum0_in, wdata_accum0_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum0_pong ( + .addr0(waddr_accum0), + .d0(wdata_accum0_pong), + .we0(wdata_en_pong0), + .addr1(raddr_buffer0), + .q1(rdata_buffer0_pong), + .clk(clk) +); + +qadd adder_accum_pong1 (wdata_accum1, wdata_accum1_in, wdata_accum1_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum1_pong ( + .addr0(waddr_accum1), + .d0(wdata_accum1_pong), + .we0(wdata_en_pong1), + .addr1(raddr_buffer1), + .q1(rdata_buffer1_pong), + .clk(clk) +); + +qadd adder_accum_pong2 (wdata_accum2, wdata_accum2_in, wdata_accum2_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum2_pong ( + .addr0(waddr_accum2), + .d0(wdata_accum2_pong), + .we0(wdata_en_pong2), + .addr1(raddr_buffer2), + .q1(rdata_buffer2_pong), + .clk(clk) +); + +qadd adder_accum_pong3 (wdata_accum3, wdata_accum3_in, wdata_accum3_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum3_pong ( + .addr0(waddr_accum3), + .d0(wdata_accum3_pong), + .we0(wdata_en_pong3), + .addr1(raddr_buffer3), + .q1(rdata_buffer3_pong), + .clk(clk) +); + +qadd adder_accum_pong4 (wdata_accum4, wdata_accum4_in, wdata_accum4_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum4_pong ( + .addr0(waddr_accum4), + .d0(wdata_accum4_pong), + .we0(wdata_en_pong4), + .addr1(raddr_buffer4), + .q1(rdata_buffer4_pong), + .clk(clk) +); + +qadd adder_accum_pong5 (wdata_accum5, wdata_accum5_in, wdata_accum5_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum5_pong ( + .addr0(waddr_accum5), + .d0(wdata_accum5_pong), + .we0(wdata_en_pong5), + .addr1(raddr_buffer5), + .q1(rdata_buffer5_pong), + .clk(clk) +); + +qadd adder_accum_pong6 (wdata_accum6, wdata_accum6_in, wdata_accum6_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum6_pong ( + .addr0(waddr_accum6), + .d0(wdata_accum6_pong), + .we0(wdata_en_pong6), + .addr1(raddr_buffer6), + .q1(rdata_buffer6_pong), + .clk(clk) +); + +qadd adder_accum_pong7 (wdata_accum7, wdata_accum7_in, wdata_accum7_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum7_pong ( + .addr0(waddr_accum7), + .d0(wdata_accum7_pong), + .we0(wdata_en_pong7), + .addr1(raddr_buffer7), + .q1(rdata_buffer7_pong), + .clk(clk) +); + +qadd adder_accum_pong8 (wdata_accum8, wdata_accum8_in, wdata_accum8_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum8_pong ( + .addr0(waddr_accum8), + .d0(wdata_accum8_pong), + .we0(wdata_en_pong8), + .addr1(raddr_buffer8), + .q1(rdata_buffer8_pong), + .clk(clk) +); + +qadd adder_accum_pong9 (wdata_accum9, wdata_accum9_in, wdata_accum9_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum9_pong ( + .addr0(waddr_accum9), + .d0(wdata_accum9_pong), + .we0(wdata_en_pong9), + .addr1(raddr_buffer9), + .q1(rdata_buffer9_pong), + .clk(clk) +); + +qadd adder_accum_pong10 (wdata_accum10, wdata_accum10_in, wdata_accum10_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum10_pong ( + .addr0(waddr_accum10), + .d0(wdata_accum10_pong), + .we0(wdata_en_pong10), + .addr1(raddr_buffer10), + .q1(rdata_buffer10_pong), + .clk(clk) +); + +qadd adder_accum_pong11 (wdata_accum11, wdata_accum11_in, wdata_accum11_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum11_pong ( + .addr0(waddr_accum11), + .d0(wdata_accum11_pong), + .we0(wdata_en_pong11), + .addr1(raddr_buffer11), + .q1(rdata_buffer11_pong), + .clk(clk) +); + +qadd adder_accum_pong12 (wdata_accum12, wdata_accum12_in, wdata_accum12_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum12_pong ( + .addr0(waddr_accum12), + .d0(wdata_accum12_pong), + .we0(wdata_en_pong12), + .addr1(raddr_buffer12), + .q1(rdata_buffer12_pong), + .clk(clk) +); + +qadd adder_accum_pong13 (wdata_accum13, wdata_accum13_in, wdata_accum13_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum13_pong ( + .addr0(waddr_accum13), + .d0(wdata_accum13_pong), + .we0(wdata_en_pong13), + .addr1(raddr_buffer13), + .q1(rdata_buffer13_pong), + .clk(clk) +); + +qadd adder_accum_pong14 (wdata_accum14, wdata_accum14_in, wdata_accum14_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum14_pong ( + .addr0(waddr_accum14), + .d0(wdata_accum14_pong), + .we0(wdata_en_pong14), + .addr1(raddr_buffer14), + .q1(rdata_buffer14_pong), + .clk(clk) +); + +qadd adder_accum_pong15 (wdata_accum15, wdata_accum15_in, wdata_accum15_pong); +simple_ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum15_pong ( + .addr0(waddr_accum15), + .d0(wdata_accum15_pong), + .we0(wdata_en_pong15), + .addr1(raddr_buffer15), + .q1(rdata_buffer15_pong), + .clk(clk) +); + + +`else + +//////////////////////////////////////////////// +// PING ACCUMULATORS +//////////////////////////////////////////////// + +qadd adder_accum_ping0 (wdata_accum0, wdata_accum0_in, wdata_accum0_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum0_ping ( + .addr0(waddr_accum0), + .d0(wdata_accum0_ping), + .we0(wdata_en_ping0), + .q0(accum0_ping_q0_NC), + .addr1(raddr_buffer0), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer0), + .clk(clk) +); + +qadd adder_accum_ping1 (wdata_accum1, wdata_accum1_in, wdata_accum1_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum1_ping ( + .addr0(waddr_accum1), + .d0(wdata_accum1_ping), + .we0(wdata_en_ping1), + .q0(accum1_ping_q0_NC), + .addr1(raddr_buffer1), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer1), + .clk(clk) +); + +qadd adder_accum_ping2 (wdata_accum2, wdata_accum2_in, wdata_accum2_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum2_ping ( + .addr0(waddr_accum2), + .d0(wdata_accum2_ping), + .we0(wdata_en_ping2), + .q0(accum2_ping_q0_NC), + .addr1(raddr_buffer2), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer2), + .clk(clk) +); + +qadd adder_accum_ping3 (wdata_accum3, wdata_accum3_in, wdata_accum3_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum3_ping ( + .addr0(waddr_accum3), + .d0(wdata_accum3_ping), + .we0(wdata_en_ping3), + .q0(accum3_ping_q0_NC), + .addr1(raddr_buffer3), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer3), + .clk(clk) +); + +qadd adder_accum_ping4 (wdata_accum4, wdata_accum4_in, wdata_accum4_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum4_ping ( + .addr0(waddr_accum4), + .d0(wdata_accum4_ping), + .we0(wdata_en_ping4), + .q0(accum4_ping_q0_NC), + .addr1(raddr_buffer4), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer4), + .clk(clk) +); + +qadd adder_accum_ping5 (wdata_accum5, wdata_accum5_in, wdata_accum5_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum5_ping ( + .addr0(waddr_accum5), + .d0(wdata_accum5_ping), + .we0(wdata_en_ping5), + .q0(accum5_ping_q0_NC), + .addr1(raddr_buffer5), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer5), + .clk(clk) +); + +qadd adder_accum_ping6 (wdata_accum6, wdata_accum6_in, wdata_accum6_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum6_ping ( + .addr0(waddr_accum6), + .d0(wdata_accum6_ping), + .we0(wdata_en_ping6), + .q0(accum6_ping_q0_NC), + .addr1(raddr_buffer6), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer6), + .clk(clk) +); + +qadd adder_accum_ping7 (wdata_accum7, wdata_accum7_in, wdata_accum7_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum7_ping ( + .addr0(waddr_accum7), + .d0(wdata_accum7_ping), + .we0(wdata_en_ping7), + .q0(accum7_ping_q0_NC), + .addr1(raddr_buffer7), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer7), + .clk(clk) +); + +qadd adder_accum_ping8 (wdata_accum8, wdata_accum8_in, wdata_accum8_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum8_ping ( + .addr0(waddr_accum8), + .d0(wdata_accum8_ping), + .we0(wdata_en_ping8), + .q0(accum8_ping_q0_NC), + .addr1(raddr_buffer8), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer8), + .clk(clk) +); + +qadd adder_accum_ping9 (wdata_accum9, wdata_accum9_in, wdata_accum9_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum9_ping ( + .addr0(waddr_accum9), + .d0(wdata_accum9_ping), + .we0(wdata_en_ping9), + .q0(accum9_ping_q0_NC), + .addr1(raddr_buffer9), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer9), + .clk(clk) +); + +qadd adder_accum_ping10 (wdata_accum10, wdata_accum10_in, wdata_accum10_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum10_ping ( + .addr0(waddr_accum10), + .d0(wdata_accum10_ping), + .we0(wdata_en_ping10), + .q0(accum10_ping_q0_NC), + .addr1(raddr_buffer10), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer10), + .clk(clk) +); + +qadd adder_accum_ping11 (wdata_accum11, wdata_accum11_in, wdata_accum11_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum11_ping ( + .addr0(waddr_accum11), + .d0(wdata_accum11_ping), + .we0(wdata_en_ping11), + .q0(accum11_ping_q0_NC), + .addr1(raddr_buffer11), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer11), + .clk(clk) +); + +qadd adder_accum_ping12 (wdata_accum12, wdata_accum12_in, wdata_accum12_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum12_ping ( + .addr0(waddr_accum12), + .d0(wdata_accum12_ping), + .we0(wdata_en_ping12), + .q0(accum12_ping_q0_NC), + .addr1(raddr_buffer12), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer12), + .clk(clk) +); + +qadd adder_accum_ping13 (wdata_accum13, wdata_accum13_in, wdata_accum13_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum13_ping ( + .addr0(waddr_accum13), + .d0(wdata_accum13_ping), + .we0(wdata_en_ping13), + .q0(accum13_ping_q0_NC), + .addr1(raddr_buffer13), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer13), + .clk(clk) +); + +qadd adder_accum_ping14 (wdata_accum14, wdata_accum14_in, wdata_accum14_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum14_ping ( + .addr0(waddr_accum14), + .d0(wdata_accum14_ping), + .we0(wdata_en_ping14), + .q0(accum14_ping_q0_NC), + .addr1(raddr_buffer14), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer14), + .clk(clk) +); + +qadd adder_accum_ping15 (wdata_accum15, wdata_accum15_in, wdata_accum15_ping); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum15_ping ( + .addr0(waddr_accum15), + .d0(wdata_accum15_ping), + .we0(wdata_en_ping15), + .q0(accum15_ping_q0_NC), + .addr1(raddr_buffer15), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer15), + .clk(clk) +); + +wire [`DWIDTH-1:0] wdata_accum0_pong; +wire [`DWIDTH-1:0] wdata_accum1_pong; +wire [`DWIDTH-1:0] wdata_accum2_pong; +wire [`DWIDTH-1:0] wdata_accum3_pong; +wire [`DWIDTH-1:0] wdata_accum4_pong; +wire [`DWIDTH-1:0] wdata_accum5_pong; +wire [`DWIDTH-1:0] wdata_accum6_pong; +wire [`DWIDTH-1:0] wdata_accum7_pong; +wire [`DWIDTH-1:0] wdata_accum8_pong; +wire [`DWIDTH-1:0] wdata_accum9_pong; +wire [`DWIDTH-1:0] wdata_accum10_pong; +wire [`DWIDTH-1:0] wdata_accum11_pong; +wire [`DWIDTH-1:0] wdata_accum12_pong; +wire [`DWIDTH-1:0] wdata_accum13_pong; +wire [`DWIDTH-1:0] wdata_accum14_pong; +wire [`DWIDTH-1:0] wdata_accum15_pong; + +//////////////////////////////////////////////// +// PONG ACCUMULATORS +//////////////////////////////////////////////// + +qadd adder_accum_pong0 (wdata_accum0, wdata_accum0_in, wdata_accum0_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum0_pong ( + .addr0(waddr_accum0), + .d0(wdata_accum0_pong), + .we0(wdata_en_pong0), + .q0(accum0_pong_q0_NC), + .addr1(raddr_buffer0), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer0_pong), + .clk(clk) +); + +qadd adder_accum_pong1 (wdata_accum1, wdata_accum1_in, wdata_accum1_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum1_pong ( + .addr0(waddr_accum1), + .d0(wdata_accum1_pong), + .we0(wdata_en_pong1), + .q0(accum1_pong_q0_NC), + .addr1(raddr_buffer1), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer1_pong), + .clk(clk) +); + +qadd adder_accum_pong2 (wdata_accum2, wdata_accum2_in, wdata_accum2_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum2_pong ( + .addr0(waddr_accum2), + .d0(wdata_accum2_pong), + .we0(wdata_en_pong2), + .q0(accum2_pong_q0_NC), + .addr1(raddr_buffer2), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer2_pong), + .clk(clk) +); + +qadd adder_accum_pong3 (wdata_accum3, wdata_accum3_in, wdata_accum3_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum3_pong ( + .addr0(waddr_accum3), + .d0(wdata_accum3_pong), + .we0(wdata_en_pong3), + .q0(accum3_pong_q0_NC), + .addr1(raddr_buffer3), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer3_pong), + .clk(clk) +); + +qadd adder_accum_pong4 (wdata_accum4, wdata_accum4_in, wdata_accum4_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum4_pong ( + .addr0(waddr_accum4), + .d0(wdata_accum4_pong), + .we0(wdata_en_pong4), + .q0(accum4_pong_q0_NC), + .addr1(raddr_buffer4), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer4_pong), + .clk(clk) +); + +qadd adder_accum_pong5 (wdata_accum5, wdata_accum5_in, wdata_accum5_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum5_pong ( + .addr0(waddr_accum5), + .d0(wdata_accum5_pong), + .we0(wdata_en_pong5), + .q0(accum5_pong_q0_NC), + .addr1(raddr_buffer5), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer5_pong), + .clk(clk) +); + +qadd adder_accum_pong6 (wdata_accum6, wdata_accum6_in, wdata_accum6_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum6_pong ( + .addr0(waddr_accum6), + .d0(wdata_accum6_pong), + .we0(wdata_en_pong6), + .q0(accum6_pong_q0_NC), + .addr1(raddr_buffer6), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer6_pong), + .clk(clk) +); + +qadd adder_accum_pong7 (wdata_accum7, wdata_accum7_in, wdata_accum7_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum7_pong ( + .addr0(waddr_accum7), + .d0(wdata_accum7_pong), + .we0(wdata_en_pong7), + .q0(accum7_pong_q0_NC), + .addr1(raddr_buffer7), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer7_pong), + .clk(clk) +); + +qadd adder_accum_pong8 (wdata_accum8, wdata_accum8_in, wdata_accum8_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum8_pong ( + .addr0(waddr_accum8), + .d0(wdata_accum8_pong), + .we0(wdata_en_pong8), + .q0(accum8_pong_q0_NC), + .addr1(raddr_buffer8), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer8_pong), + .clk(clk) +); + +qadd adder_accum_pong9 (wdata_accum9, wdata_accum9_in, wdata_accum9_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum9_pong ( + .addr0(waddr_accum9), + .d0(wdata_accum9_pong), + .we0(wdata_en_pong9), + .q0(accum9_pong_q0_NC), + .addr1(raddr_buffer9), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer9_pong), + .clk(clk) +); + +qadd adder_accum_pong10 (wdata_accum10, wdata_accum10_in, wdata_accum10_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum10_pong ( + .addr0(waddr_accum10), + .d0(wdata_accum10_pong), + .we0(wdata_en_pong10), + .q0(accum10_pong_q0_NC), + .addr1(raddr_buffer10), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer10_pong), + .clk(clk) +); + +qadd adder_accum_pong11 (wdata_accum11, wdata_accum11_in, wdata_accum11_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum11_pong ( + .addr0(waddr_accum11), + .d0(wdata_accum11_pong), + .we0(wdata_en_pong11), + .q0(accum11_pong_q0_NC), + .addr1(raddr_buffer11), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer11_pong), + .clk(clk) +); + +qadd adder_accum_pong12 (wdata_accum12, wdata_accum12_in, wdata_accum12_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum12_pong ( + .addr0(waddr_accum12), + .d0(wdata_accum12_pong), + .we0(wdata_en_pong12), + .q0(accum12_pong_q0_NC), + .addr1(raddr_buffer12), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer12_pong), + .clk(clk) +); + +qadd adder_accum_pong13 (wdata_accum13, wdata_accum13_in, wdata_accum13_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum13_pong ( + .addr0(waddr_accum13), + .d0(wdata_accum13_pong), + .we0(wdata_en_pong13), + .q0(accum13_pong_q0_NC), + .addr1(raddr_buffer13), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer13_pong), + .clk(clk) +); + +qadd adder_accum_pong14 (wdata_accum14, wdata_accum14_in, wdata_accum14_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum14_pong ( + .addr0(waddr_accum14), + .d0(wdata_accum14_pong), + .we0(wdata_en_pong14), + .q0(accum14_pong_q0_NC), + .addr1(raddr_buffer14), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer14_pong), + .clk(clk) +); + +qadd adder_accum_pong15 (wdata_accum15, wdata_accum15_in, wdata_accum15_pong); +ram #(.AW(`AWIDTH), .MW(MWIDTH), .DW(`DWIDTH)) accum15_pong ( + .addr0(waddr_accum15), + .d0(wdata_accum15_pong), + .we0(wdata_en_pong15), + .q0(accum15_pong_q0_NC), + .addr1(raddr_buffer15), + .d1(8'b0), + .we1(1'b0), + .q1(rdata_buffer15_pong), + .clk(clk) +); + +`endif + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM generate_pool.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// + +module pooling( + clk, + resetn, + start_pooling, + pool_select, + pool_norm_valid, + enable_pool, + rdata_accum0_pool, + rdata_accum1_pool, + rdata_accum2_pool, + rdata_accum3_pool, + rdata_accum4_pool, + rdata_accum5_pool, + rdata_accum6_pool, + rdata_accum7_pool, + rdata_accum8_pool, + rdata_accum9_pool, + rdata_accum10_pool, + rdata_accum11_pool, + rdata_accum12_pool, + rdata_accum13_pool, + rdata_accum14_pool, + rdata_accum15_pool, + raddr_accum0_pool, + raddr_accum1_pool, + raddr_accum2_pool, + raddr_accum3_pool, + raddr_accum4_pool, + raddr_accum5_pool, + raddr_accum6_pool, + raddr_accum7_pool, + raddr_accum8_pool, + raddr_accum9_pool, + raddr_accum10_pool, + raddr_accum11_pool, + raddr_accum12_pool, + raddr_accum13_pool, + raddr_accum14_pool, + raddr_accum15_pool, + pool0, + pool1, + pool2, + pool3, + pool4, + pool5, + pool6, + pool7, + pool8, + pool9, + pool10, + pool11, + pool12, + pool13, + pool14, + pool15, + matrix_size, + filter_size +); + +input clk; +input resetn; +input start_pooling; +input pool_select; +input enable_pool; +output pool_norm_valid; +output reg [`DWIDTH-1:0] pool0; +output reg [`DWIDTH-1:0] pool1; +output reg [`DWIDTH-1:0] pool2; +output reg [`DWIDTH-1:0] pool3; +output reg [`DWIDTH-1:0] pool4; +output reg [`DWIDTH-1:0] pool5; +output reg [`DWIDTH-1:0] pool6; +output reg [`DWIDTH-1:0] pool7; +output reg [`DWIDTH-1:0] pool8; +output reg [`DWIDTH-1:0] pool9; +output reg [`DWIDTH-1:0] pool10; +output reg [`DWIDTH-1:0] pool11; +output reg [`DWIDTH-1:0] pool12; +output reg [`DWIDTH-1:0] pool13; +output reg [`DWIDTH-1:0] pool14; +output reg [`DWIDTH-1:0] pool15; +input [`DWIDTH-1:0] rdata_accum0_pool; +input [`DWIDTH-1:0] rdata_accum1_pool; +input [`DWIDTH-1:0] rdata_accum2_pool; +input [`DWIDTH-1:0] rdata_accum3_pool; +input [`DWIDTH-1:0] rdata_accum4_pool; +input [`DWIDTH-1:0] rdata_accum5_pool; +input [`DWIDTH-1:0] rdata_accum6_pool; +input [`DWIDTH-1:0] rdata_accum7_pool; +input [`DWIDTH-1:0] rdata_accum8_pool; +input [`DWIDTH-1:0] rdata_accum9_pool; +input [`DWIDTH-1:0] rdata_accum10_pool; +input [`DWIDTH-1:0] rdata_accum11_pool; +input [`DWIDTH-1:0] rdata_accum12_pool; +input [`DWIDTH-1:0] rdata_accum13_pool; +input [`DWIDTH-1:0] rdata_accum14_pool; +input [`DWIDTH-1:0] rdata_accum15_pool; +output [`AWIDTH-1:0] raddr_accum0_pool; +output [`AWIDTH-1:0] raddr_accum1_pool; +output [`AWIDTH-1:0] raddr_accum2_pool; +output [`AWIDTH-1:0] raddr_accum3_pool; +output [`AWIDTH-1:0] raddr_accum4_pool; +output [`AWIDTH-1:0] raddr_accum5_pool; +output [`AWIDTH-1:0] raddr_accum6_pool; +output [`AWIDTH-1:0] raddr_accum7_pool; +output [`AWIDTH-1:0] raddr_accum8_pool; +output [`AWIDTH-1:0] raddr_accum9_pool; +output [`AWIDTH-1:0] raddr_accum10_pool; +output [`AWIDTH-1:0] raddr_accum11_pool; +output [`AWIDTH-1:0] raddr_accum12_pool; +output [`AWIDTH-1:0] raddr_accum13_pool; +output [`AWIDTH-1:0] raddr_accum14_pool; +output [`AWIDTH-1:0] raddr_accum15_pool; +input [`DWIDTH-1:0] matrix_size; +input [`DWIDTH-1:0] filter_size; + +reg [`AWIDTH-1:0] raddr_accum1_pool; +reg [`AWIDTH-1:0] raddr_accum2_pool; +reg [`AWIDTH-1:0] raddr_accum3_pool; +reg [`AWIDTH-1:0] raddr_accum4_pool; +reg [`AWIDTH-1:0] raddr_accum5_pool; +reg [`AWIDTH-1:0] raddr_accum6_pool; +reg [`AWIDTH-1:0] raddr_accum7_pool; +reg [`AWIDTH-1:0] raddr_accum8_pool; +reg [`AWIDTH-1:0] raddr_accum9_pool; +reg [`AWIDTH-1:0] raddr_accum10_pool; +reg [`AWIDTH-1:0] raddr_accum11_pool; +reg [`AWIDTH-1:0] raddr_accum12_pool; +reg [`AWIDTH-1:0] raddr_accum13_pool; +reg [`AWIDTH-1:0] raddr_accum14_pool; +reg [`AWIDTH-1:0] raddr_accum15_pool; + +reg [7:0] pool_count0; +reg [7:0] pool_count1; +reg [7:0] pool_count2; +reg [7:0] pool_count3; +reg [7:0] pool_count4; +reg [7:0] pool_count5; +reg [7:0] pool_count6; +reg [7:0] pool_count7; +reg [7:0] pool_count8; +reg [7:0] pool_count9; +reg [7:0] pool_count10; +reg [7:0] pool_count11; +reg [7:0] pool_count12; +reg [7:0] pool_count13; +reg [7:0] pool_count14; +reg [7:0] pool_count15; +reg [7:0] pool_count16; + +wire [`DWIDTH-1:0] filter_size_int; +assign filter_size_int = (enable_pool)? filter_size : 8'b1; +wire [`DWIDTH-1:0] matrix_size_int; +assign matrix_size_int = (enable_pool)? matrix_size : 8'b1; + +always @ (posedge clk) begin + if (~resetn|~start_pooling) begin + pool_count0 <= 0; + end + else if (pool_count0 == (filter_size_int*filter_size_int)) begin + pool_count0 <= 1; + end + else if (start_pooling) begin + pool_count0 <= pool_count0 + 1; + end +end + +always @ (posedge clk) begin + pool_count1 <= pool_count0; + pool_count2 <= pool_count1; + pool_count3 <= pool_count2; + pool_count4 <= pool_count3; + pool_count5 <= pool_count4; + pool_count6 <= pool_count5; + pool_count7 <= pool_count6; + pool_count8 <= pool_count7; + pool_count9 <= pool_count8; + pool_count10 <= pool_count9; + pool_count11 <= pool_count10; + pool_count12 <= pool_count11; + pool_count13 <= pool_count12; + pool_count14 <= pool_count13; + pool_count15 <= pool_count14; + pool_count16 <= pool_count15; +end + +wire [`DWIDTH-1:0] cmp0; +wire [`DWIDTH-1:0] cmp1; +wire [`DWIDTH-1:0] cmp2; +wire [`DWIDTH-1:0] cmp3; +wire [`DWIDTH-1:0] cmp4; +wire [`DWIDTH-1:0] cmp5; +wire [`DWIDTH-1:0] cmp6; +wire [`DWIDTH-1:0] cmp7; +wire [`DWIDTH-1:0] cmp8; +wire [`DWIDTH-1:0] cmp9; +wire [`DWIDTH-1:0] cmp10; +wire [`DWIDTH-1:0] cmp11; +wire [`DWIDTH-1:0] cmp12; +wire [`DWIDTH-1:0] cmp13; +wire [`DWIDTH-1:0] cmp14; +wire [`DWIDTH-1:0] cmp15; + +reg [`DWIDTH-1:0] compare0; +reg [`DWIDTH-1:0] compare1; +reg [`DWIDTH-1:0] compare2; +reg [`DWIDTH-1:0] compare3; +reg [`DWIDTH-1:0] compare4; +reg [`DWIDTH-1:0] compare5; +reg [`DWIDTH-1:0] compare6; +reg [`DWIDTH-1:0] compare7; +reg [`DWIDTH-1:0] compare8; +reg [`DWIDTH-1:0] compare9; +reg [`DWIDTH-1:0] compare10; +reg [`DWIDTH-1:0] compare11; +reg [`DWIDTH-1:0] compare12; +reg [`DWIDTH-1:0] compare13; +reg [`DWIDTH-1:0] compare14; +reg [`DWIDTH-1:0] compare15; + +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg0; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg1; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg2; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg3; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg4; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg5; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg6; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg7; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg8; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg9; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg10; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg11; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg12; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg13; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg14; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] avg15; + +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg0_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg1_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg2_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg3_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg4_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg5_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg6_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg7_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg8_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg9_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg10_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg11_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg12_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg13_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg14_int; +reg [`DWIDTH+`MAT_MUL_SIZE-1:0] avg15_int; + +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average0; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average1; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average2; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average3; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average4; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average5; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average6; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average7; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average8; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average9; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average10; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average11; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average12; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average13; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average14; +wire [`DWIDTH+`MAT_MUL_SIZE-1:0] average15; + +assign pool_norm_valid = (pool_count1 == (filter_size_int*filter_size_int))?1'b1:1'b0; + +reg [`AWIDTH-1:0] x; +reg [`AWIDTH-1:0] y; +reg [`AWIDTH-1:0] k; +assign raddr_accum0_pool = (~resetn|~start_pooling)? 11'h7ff: ((matrix_size_int)*y + x + k); + +always @(posedge clk) begin + if(~resetn|~start_pooling) begin + x<=0; + y<=0; + k<=0; + end + else if (y == (matrix_size_int-1) & x==(filter_size_int-1)) begin + k<=k+filter_size_int; + y<=0; + x<=0; + end + else if (x==(filter_size_int-1)) begin + y<=y+1; + x<=0; + end + else if (start_pooling) begin + x<=x+1; + end +end + +always @ (posedge clk) begin + raddr_accum1_pool <= raddr_accum0_pool; + raddr_accum2_pool <= raddr_accum1_pool; + raddr_accum3_pool <= raddr_accum2_pool; + raddr_accum4_pool <= raddr_accum3_pool; + raddr_accum5_pool <= raddr_accum4_pool; + raddr_accum6_pool <= raddr_accum5_pool; + raddr_accum7_pool <= raddr_accum6_pool; + raddr_accum8_pool <= raddr_accum7_pool; + raddr_accum9_pool <= raddr_accum8_pool; + raddr_accum10_pool <= raddr_accum9_pool; + raddr_accum11_pool <= raddr_accum10_pool; + raddr_accum12_pool <= raddr_accum11_pool; + raddr_accum13_pool <= raddr_accum12_pool; + raddr_accum14_pool <= raddr_accum13_pool; + raddr_accum15_pool <= raddr_accum14_pool; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare0 <= 0; + end + else if (rdata_accum0_pool > cmp0) begin + compare0 <= rdata_accum0_pool; + end + else if (rdata_accum0_pool < cmp0) begin + compare0 <= cmp0; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg0_int <= 0; + end + else begin + avg0_int <= avg0 + rdata_accum0_pool; + end +end + +assign cmp0 = (pool_count0 == 1)? 0 : compare0; +assign avg0 = (pool_count0 == 1)? 0 : avg0_int; +assign average0 = (filter_size_int == 8'b1)? avg0_int : (filter_size_int == 8'b10)? avg0_int >> 2 : (filter_size_int == 8'b11)? avg0_int >> 3 : (filter_size_int == 8'b100)? avg0_int >> 4 : avg0_int; + +wire [`DWIDTH-1:0] pool0_wire; +assign pool0_wire = (pool_count1 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare0 : average0) : 8'b0; +always @(posedge clk) begin + pool0 <= pool0_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare1 <= 0; + end + else if (rdata_accum1_pool > cmp1) begin + compare1 <= rdata_accum1_pool; + end + else if (rdata_accum1_pool < cmp1) begin + compare1 <= cmp1; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg1_int <= 0; + end + else begin + avg1_int <= avg1 + rdata_accum1_pool; + end +end + +assign cmp1 = (pool_count1 == 1)? 0 : compare1; +assign avg1 = (pool_count1 == 1)? 0 : avg1_int; +assign average1 = (filter_size_int == 8'b1)? avg1_int : (filter_size_int == 8'b10)? avg1_int >> 2 : (filter_size_int == 8'b11)? avg1_int >> 3 : (filter_size_int == 8'b100)? avg1_int >> 4 : avg1_int; + +wire [`DWIDTH-1:0] pool1_wire; +assign pool1_wire = (pool_count2 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare1 : average1) : 8'b0; +always @(posedge clk) begin + pool1 <= pool1_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare2 <= 0; + end + else if (rdata_accum2_pool > cmp2) begin + compare2 <= rdata_accum2_pool; + end + else if (rdata_accum2_pool < cmp2) begin + compare2 <= cmp2; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg2_int <= 0; + end + else begin + avg2_int <= avg2 + rdata_accum2_pool; + end +end + +assign cmp2 = (pool_count2 == 1)? 0 : compare2; +assign avg2 = (pool_count2 == 1)? 0 : avg2_int; +assign average2 = (filter_size_int == 8'b1)? avg2_int : (filter_size_int == 8'b10)? avg2_int >> 2 : (filter_size_int == 8'b11)? avg2_int >> 3 : (filter_size_int == 8'b100)? avg2_int >> 4 : avg2_int; + +wire [`DWIDTH-1:0] pool2_wire; +assign pool2_wire = (pool_count3 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare2 : average2) : 8'b0; +always @(posedge clk) begin + pool2 <= pool2_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare3 <= 0; + end + else if (rdata_accum3_pool > cmp3) begin + compare3 <= rdata_accum3_pool; + end + else if (rdata_accum3_pool < cmp3) begin + compare3 <= cmp3; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg3_int <= 0; + end + else begin + avg3_int <= avg3 + rdata_accum3_pool; + end +end + +assign cmp3 = (pool_count3 == 1)? 0 : compare3; +assign avg3 = (pool_count3 == 1)? 0 : avg3_int; +assign average3 = (filter_size_int == 8'b1)? avg3_int : (filter_size_int == 8'b10)? avg3_int >> 2 : (filter_size_int == 8'b11)? avg3_int >> 3 : (filter_size_int == 8'b100)? avg3_int >> 4 : avg3_int; + +wire [`DWIDTH-1:0] pool3_wire; +assign pool3_wire = (pool_count4 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare3 : average3) : 8'b0; +always @(posedge clk) begin + pool3 <= pool3_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare4 <= 0; + end + else if (rdata_accum4_pool > cmp4) begin + compare4 <= rdata_accum4_pool; + end + else if (rdata_accum4_pool < cmp4) begin + compare4 <= cmp4; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg4_int <= 0; + end + else begin + avg4_int <= avg4 + rdata_accum4_pool; + end +end + +assign cmp4 = (pool_count4 == 1)? 0 : compare4; +assign avg4 = (pool_count4 == 1)? 0 : avg4_int; +assign average4 = (filter_size_int == 8'b1)? avg4_int : (filter_size_int == 8'b10)? avg4_int >> 2 : (filter_size_int == 8'b11)? avg4_int >> 3 : (filter_size_int == 8'b100)? avg4_int >> 4 : avg4_int; + +wire [`DWIDTH-1:0] pool4_wire; +assign pool4_wire = (pool_count5 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare4 : average4) : 8'b0; +always @(posedge clk) begin + pool4 <= pool4_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare5 <= 0; + end + else if (rdata_accum5_pool > cmp5) begin + compare5 <= rdata_accum5_pool; + end + else if (rdata_accum5_pool < cmp5) begin + compare5 <= cmp5; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg5_int <= 0; + end + else begin + avg5_int <= avg5 + rdata_accum5_pool; + end +end + +assign cmp5 = (pool_count5 == 1)? 0 : compare5; +assign avg5 = (pool_count5 == 1)? 0 : avg5_int; +assign average5 = (filter_size_int == 8'b1)? avg5_int : (filter_size_int == 8'b10)? avg5_int >> 2 : (filter_size_int == 8'b11)? avg5_int >> 3 : (filter_size_int == 8'b100)? avg5_int >> 4 : avg5_int; + +wire [`DWIDTH-1:0] pool5_wire; +assign pool5_wire = (pool_count6 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare5 : average5) : 8'b0; +always @(posedge clk) begin + pool5 <= pool5_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare6 <= 0; + end + else if (rdata_accum6_pool > cmp6) begin + compare6 <= rdata_accum6_pool; + end + else if (rdata_accum6_pool < cmp6) begin + compare6 <= cmp6; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg6_int <= 0; + end + else begin + avg6_int <= avg6 + rdata_accum6_pool; + end +end + +assign cmp6 = (pool_count6 == 1)? 0 : compare6; +assign avg6 = (pool_count6 == 1)? 0 : avg6_int; +assign average6 = (filter_size_int == 8'b1)? avg6_int : (filter_size_int == 8'b10)? avg6_int >> 2 : (filter_size_int == 8'b11)? avg6_int >> 3 : (filter_size_int == 8'b100)? avg6_int >> 4 : avg6_int; + +wire [`DWIDTH-1:0] pool6_wire; +assign pool6_wire = (pool_count7 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare6 : average6) : 8'b0; +always @(posedge clk) begin + pool6 <= pool6_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare7 <= 0; + end + else if (rdata_accum7_pool > cmp7) begin + compare7 <= rdata_accum7_pool; + end + else if (rdata_accum7_pool < cmp7) begin + compare7 <= cmp7; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg7_int <= 0; + end + else begin + avg7_int <= avg7 + rdata_accum7_pool; + end +end + +assign cmp7 = (pool_count7 == 1)? 0 : compare7; +assign avg7 = (pool_count7 == 1)? 0 : avg7_int; +assign average7 = (filter_size_int == 8'b1)? avg7_int : (filter_size_int == 8'b10)? avg7_int >> 2 : (filter_size_int == 8'b11)? avg7_int >> 3 : (filter_size_int == 8'b100)? avg7_int >> 4 : avg7_int; + +wire [`DWIDTH-1:0] pool7_wire; +assign pool7_wire = (pool_count8 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare7 : average7) : 8'b0; +always @(posedge clk) begin + pool7 <= pool7_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare8 <= 0; + end + else if (rdata_accum8_pool > cmp8) begin + compare8 <= rdata_accum8_pool; + end + else if (rdata_accum8_pool < cmp8) begin + compare8 <= cmp8; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg8_int <= 0; + end + else begin + avg8_int <= avg8 + rdata_accum8_pool; + end +end + +assign cmp8 = (pool_count8 == 1)? 0 : compare8; +assign avg8 = (pool_count8 == 1)? 0 : avg8_int; +assign average8 = (filter_size_int == 8'b1)? avg8_int : (filter_size_int == 8'b10)? avg8_int >> 2 : (filter_size_int == 8'b11)? avg8_int >> 3 : (filter_size_int == 8'b100)? avg8_int >> 4 : avg8_int; + +wire [`DWIDTH-1:0] pool8_wire; +assign pool8_wire = (pool_count9 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare8 : average8) : 8'b0; +always @(posedge clk) begin + pool8 <= pool8_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare9 <= 0; + end + else if (rdata_accum9_pool > cmp9) begin + compare9 <= rdata_accum9_pool; + end + else if (rdata_accum9_pool < cmp9) begin + compare9 <= cmp9; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg9_int <= 0; + end + else begin + avg9_int <= avg9 + rdata_accum9_pool; + end +end + +assign cmp9 = (pool_count9 == 1)? 0 : compare9; +assign avg9 = (pool_count9 == 1)? 0 : avg9_int; +assign average9 = (filter_size_int == 8'b1)? avg9_int : (filter_size_int == 8'b10)? avg9_int >> 2 : (filter_size_int == 8'b11)? avg9_int >> 3 : (filter_size_int == 8'b100)? avg9_int >> 4 : avg9_int; + +wire [`DWIDTH-1:0] pool9_wire; +assign pool9_wire = (pool_count10 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare9 : average9) : 8'b0; +always @(posedge clk) begin + pool9 <= pool9_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare10 <= 0; + end + else if (rdata_accum10_pool > cmp10) begin + compare10 <= rdata_accum10_pool; + end + else if (rdata_accum10_pool < cmp10) begin + compare10 <= cmp10; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg10_int <= 0; + end + else begin + avg10_int <= avg10 + rdata_accum10_pool; + end +end + +assign cmp10 = (pool_count10 == 1)? 0 : compare10; +assign avg10 = (pool_count10 == 1)? 0 : avg10_int; +assign average10 = (filter_size_int == 8'b1)? avg10_int : (filter_size_int == 8'b10)? avg10_int >> 2 : (filter_size_int == 8'b11)? avg10_int >> 3 : (filter_size_int == 8'b100)? avg10_int >> 4 : avg10_int; + +wire [`DWIDTH-1:0] pool10_wire; +assign pool10_wire = (pool_count11 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare10 : average10) : 8'b0; +always @(posedge clk) begin + pool10 <= pool10_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare11 <= 0; + end + else if (rdata_accum11_pool > cmp11) begin + compare11 <= rdata_accum11_pool; + end + else if (rdata_accum11_pool < cmp11) begin + compare11 <= cmp11; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg11_int <= 0; + end + else begin + avg11_int <= avg11 + rdata_accum11_pool; + end +end + +assign cmp11 = (pool_count11 == 1)? 0 : compare11; +assign avg11 = (pool_count11 == 1)? 0 : avg11_int; +assign average11 = (filter_size_int == 8'b1)? avg11_int : (filter_size_int == 8'b10)? avg11_int >> 2 : (filter_size_int == 8'b11)? avg11_int >> 3 : (filter_size_int == 8'b100)? avg11_int >> 4 : avg11_int; + +wire [`DWIDTH-1:0] pool11_wire; +assign pool11_wire = (pool_count12 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare11 : average11) : 8'b0; +always @(posedge clk) begin + pool11 <= pool11_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare12 <= 0; + end + else if (rdata_accum12_pool > cmp12) begin + compare12 <= rdata_accum12_pool; + end + else if (rdata_accum12_pool < cmp12) begin + compare12 <= cmp12; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg12_int <= 0; + end + else begin + avg12_int <= avg12 + rdata_accum12_pool; + end +end + +assign cmp12 = (pool_count12 == 1)? 0 : compare12; +assign avg12 = (pool_count12 == 1)? 0 : avg12_int; +assign average12 = (filter_size_int == 8'b1)? avg12_int : (filter_size_int == 8'b10)? avg12_int >> 2 : (filter_size_int == 8'b11)? avg12_int >> 3 : (filter_size_int == 8'b100)? avg12_int >> 4 : avg12_int; + +wire [`DWIDTH-1:0] pool12_wire; +assign pool12_wire = (pool_count13 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare12 : average12) : 8'b0; +always @(posedge clk) begin + pool12 <= pool12_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare13 <= 0; + end + else if (rdata_accum13_pool > cmp13) begin + compare13 <= rdata_accum13_pool; + end + else if (rdata_accum13_pool < cmp13) begin + compare13 <= cmp13; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg13_int <= 0; + end + else begin + avg13_int <= avg13 + rdata_accum13_pool; + end +end + +assign cmp13 = (pool_count13 == 1)? 0 : compare13; +assign avg13 = (pool_count13 == 1)? 0 : avg13_int; +assign average13 = (filter_size_int == 8'b1)? avg13_int : (filter_size_int == 8'b10)? avg13_int >> 2 : (filter_size_int == 8'b11)? avg13_int >> 3 : (filter_size_int == 8'b100)? avg13_int >> 4 : avg13_int; + +wire [`DWIDTH-1:0] pool13_wire; +assign pool13_wire = (pool_count14 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare13 : average13) : 8'b0; +always @(posedge clk) begin + pool13 <= pool13_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare14 <= 0; + end + else if (rdata_accum14_pool > cmp14) begin + compare14 <= rdata_accum14_pool; + end + else if (rdata_accum14_pool < cmp14) begin + compare14 <= cmp14; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg14_int <= 0; + end + else begin + avg14_int <= avg14 + rdata_accum14_pool; + end +end + +assign cmp14 = (pool_count14 == 1)? 0 : compare14; +assign avg14 = (pool_count14 == 1)? 0 : avg14_int; +assign average14 = (filter_size_int == 8'b1)? avg14_int : (filter_size_int == 8'b10)? avg14_int >> 2 : (filter_size_int == 8'b11)? avg14_int >> 3 : (filter_size_int == 8'b100)? avg14_int >> 4 : avg14_int; + +wire [`DWIDTH-1:0] pool14_wire; +assign pool14_wire = (pool_count15 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare14 : average14) : 8'b0; +always @(posedge clk) begin + pool14 <= pool14_wire; +end + +always @ (posedge clk) begin + if (~resetn) begin + compare15 <= 0; + end + else if (rdata_accum15_pool > cmp15) begin + compare15 <= rdata_accum15_pool; + end + else if (rdata_accum15_pool < cmp15) begin + compare15 <= cmp15; + end +end + +always @ (posedge clk) begin + if (~resetn) begin + avg15_int <= 0; + end + else begin + avg15_int <= avg15 + rdata_accum15_pool; + end +end + +assign cmp15 = (pool_count15 == 1)? 0 : compare15; +assign avg15 = (pool_count15 == 1)? 0 : avg15_int; +assign average15 = (filter_size_int == 8'b1)? avg15_int : (filter_size_int == 8'b10)? avg15_int >> 2 : (filter_size_int == 8'b11)? avg15_int >> 3 : (filter_size_int == 8'b100)? avg15_int >> 4 : avg15_int; + +wire [`DWIDTH-1:0] pool15_wire; +assign pool15_wire = (pool_count16 == (filter_size_int*filter_size_int))? ((pool_select == 0)? compare15 : average15) : 8'b0; +always @(posedge clk) begin + pool15 <= pool15_wire; +end + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// THIS FILE WAS AUTOMATICALLY GENERATED FROM generate_activation.v.mako +// DO NOT EDIT +//////////////////////////////////////////////////////////////////////////////// +module activation( + input activation_type, + input enable_activation, + input enable_pool, + input in_data_available, + input [`DWIDTH-1:0] inp_data0, + input [`DWIDTH-1:0] inp_data1, + input [`DWIDTH-1:0] inp_data2, + input [`DWIDTH-1:0] inp_data3, + input [`DWIDTH-1:0] inp_data4, + input [`DWIDTH-1:0] inp_data5, + input [`DWIDTH-1:0] inp_data6, + input [`DWIDTH-1:0] inp_data7, + input [`DWIDTH-1:0] inp_data8, + input [`DWIDTH-1:0] inp_data9, + input [`DWIDTH-1:0] inp_data10, + input [`DWIDTH-1:0] inp_data11, + input [`DWIDTH-1:0] inp_data12, + input [`DWIDTH-1:0] inp_data13, + input [`DWIDTH-1:0] inp_data14, + input [`DWIDTH-1:0] inp_data15, + output [`DWIDTH-1:0] out_data0, + output [`DWIDTH-1:0] out_data1, + output [`DWIDTH-1:0] out_data2, + output [`DWIDTH-1:0] out_data3, + output [`DWIDTH-1:0] out_data4, + output [`DWIDTH-1:0] out_data5, + output [`DWIDTH-1:0] out_data6, + output [`DWIDTH-1:0] out_data7, + output [`DWIDTH-1:0] out_data8, + output [`DWIDTH-1:0] out_data9, + output [`DWIDTH-1:0] out_data10, + output [`DWIDTH-1:0] out_data11, + output [`DWIDTH-1:0] out_data12, + output [`DWIDTH-1:0] out_data13, + output [`DWIDTH-1:0] out_data14, + output [`DWIDTH-1:0] out_data15, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output reg done_activation, + input clk, + input reset +); + +reg in_data_available1; +reg in_data_available2; +reg in_data_available3; +reg in_data_available4; +reg in_data_available5; +reg in_data_available6; +reg in_data_available7; +reg in_data_available8; +reg in_data_available9; +reg in_data_available10; +reg in_data_available11; +reg in_data_available12; +reg in_data_available13; +reg in_data_available14; +reg in_data_available15; + +always @(posedge clk) begin + in_data_available1 <= in_data_available; + in_data_available2 <= in_data_available1; + in_data_available3 <= in_data_available2; + in_data_available4 <= in_data_available3; + in_data_available5 <= in_data_available4; + in_data_available6 <= in_data_available5; + in_data_available7 <= in_data_available6; + in_data_available8 <= in_data_available7; + in_data_available9 <= in_data_available8; + in_data_available10 <= in_data_available9; + in_data_available11 <= in_data_available10; + in_data_available12 <= in_data_available11; + in_data_available13 <= in_data_available12; + in_data_available14 <= in_data_available13; + in_data_available15 <= in_data_available14; +end + +wire out_data_available_internal; +assign out_data_available = enable_pool? enable_activation ? out_data_available_internal : in_data_available : in_data_available2; + + +wire out_data_available_final; +reg [`DWIDTH-1:0] act_count; +reg [`DWIDTH-1:0] done_activation_count; + +always @(posedge clk) begin + if (reset) begin + done_activation <= 0; + done_activation_count <= 0; + act_count <= 0; + end + else if (done_activation_count == `MAT_MUL_SIZE) + done_activation <= 0; + else if (act_count == 4) begin + done_activation <= 1; + done_activation_count <= done_activation_count + 1; + end + else if (out_data_available_final == 1) begin + act_count <= act_count + 1; + end +end + +sub_activation activation0( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available), + .inp_data(inp_data0), + .out_data(out_data0), + .out_data_available(out_data_available_internal), + .validity_mask(validity_mask[0]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC1; +sub_activation activation1( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available1), + .inp_data(inp_data1), + .out_data(out_data1), + .out_data_available(out_data_available_NC1), + .validity_mask(validity_mask[1]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC2; +sub_activation activation2( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available2), + .inp_data(inp_data2), + .out_data(out_data2), + .out_data_available(out_data_available_NC2), + .validity_mask(validity_mask[2]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC3; +sub_activation activation3( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available3), + .inp_data(inp_data3), + .out_data(out_data3), + .out_data_available(out_data_available_NC3), + .validity_mask(validity_mask[3]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC4; +sub_activation activation4( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available4), + .inp_data(inp_data4), + .out_data(out_data4), + .out_data_available(out_data_available_NC4), + .validity_mask(validity_mask[4]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC5; +sub_activation activation5( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available5), + .inp_data(inp_data5), + .out_data(out_data5), + .out_data_available(out_data_available_NC5), + .validity_mask(validity_mask[5]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC6; +sub_activation activation6( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available6), + .inp_data(inp_data6), + .out_data(out_data6), + .out_data_available(out_data_available_NC6), + .validity_mask(validity_mask[6]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC7; +sub_activation activation7( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available7), + .inp_data(inp_data7), + .out_data(out_data7), + .out_data_available(out_data_available_NC7), + .validity_mask(validity_mask[7]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC8; +sub_activation activation8( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available8), + .inp_data(inp_data8), + .out_data(out_data8), + .out_data_available(out_data_available_NC8), + .validity_mask(validity_mask[8]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC9; +sub_activation activation9( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available9), + .inp_data(inp_data9), + .out_data(out_data9), + .out_data_available(out_data_available_NC9), + .validity_mask(validity_mask[9]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC10; +sub_activation activation10( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available10), + .inp_data(inp_data10), + .out_data(out_data10), + .out_data_available(out_data_available_NC10), + .validity_mask(validity_mask[10]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC11; +sub_activation activation11( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available11), + .inp_data(inp_data11), + .out_data(out_data11), + .out_data_available(out_data_available_NC11), + .validity_mask(validity_mask[11]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC12; +sub_activation activation12( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available12), + .inp_data(inp_data12), + .out_data(out_data12), + .out_data_available(out_data_available_NC12), + .validity_mask(validity_mask[12]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC13; +sub_activation activation13( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available13), + .inp_data(inp_data13), + .out_data(out_data13), + .out_data_available(out_data_available_NC13), + .validity_mask(validity_mask[13]), + .clk(clk), + .reset(reset) +); + +wire out_data_available_NC14; +sub_activation activation14( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available14), + .inp_data(inp_data14), + .out_data(out_data14), + .out_data_available(out_data_available_NC14), + .validity_mask(validity_mask[14]), + .clk(clk), + .reset(reset) +); + +sub_activation activation15( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(in_data_available15), + .inp_data(inp_data15), + .out_data(out_data15), + .out_data_available(out_data_available_final), + .validity_mask(validity_mask[15]), + .clk(clk), + .reset(reset) +); + +endmodule + +module sub_activation( + input activation_type, + input enable_activation, + input in_data_available, + input [`DWIDTH-1:0] inp_data, + output [`DWIDTH-1:0] out_data, + output out_data_available, + input validity_mask, + input clk, + input reset +); + +reg out_data_available_internal; +reg [`DWIDTH-1:0] out_data_internal; +reg [`DWIDTH-1:0] slope_applied_data_internal; +reg [`DWIDTH-1:0] intercept_applied_data_internal; +reg [`DWIDTH-1:0] relu_applied_data_internal; + +reg [31:0] cycle_count; +reg activation_in_progress; + +reg [3:0] address; +reg [`DWIDTH-1:0] data_slope; +reg [`DWIDTH-1:0] data_intercept; +reg [`DWIDTH-1:0] data_intercept_delayed; + +// If the activation block is not enabled, just forward the input data +assign out_data = enable_activation ? out_data_internal : inp_data; +assign out_data_available = enable_activation ? out_data_available_internal : in_data_available; + +always @(posedge clk) begin + if (reset || ~enable_activation) begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + end + else if(in_data_available || activation_in_progress) begin + cycle_count <= cycle_count + 1; + if(activation_type==1'b1) begin // tanH + slope_applied_data_internal <= data_slope * inp_data; + data_intercept_delayed <= data_intercept; + intercept_applied_data_internal <= slope_applied_data_internal + data_intercept_delayed; + end else begin // ReLU + relu_applied_data_internal <= (inp_data)? {`DWIDTH{1'b0}} : inp_data; + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if (cycle_count==2) begin + out_data_available_internal <= 1; + end + end else begin + if (cycle_count==1) begin + out_data_available_internal <= 1; + end + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if(cycle_count==2) begin + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end else begin + if(cycle_count==1) begin + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end + end + else begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + end +end + +always @ (posedge clk) begin + if (activation_type == 1'b1) + out_data_internal <= intercept_applied_data_internal; + else + out_data_internal <= relu_applied_data_internal; +end + +//Our equation of tanh is Y=AX+B +//A is the slope and B is the intercept. +//We store A in one LUT and B in another. +//LUT for the slope +always @(address) begin + case (address) + 4'b0000: data_slope = 8'd0; + 4'b0001: data_slope = 8'd0; + 4'b0010: data_slope = 8'd2; + 4'b0011: data_slope = 8'd3; + 4'b0100: data_slope = 8'd4; + 4'b0101: data_slope = 8'd0; + 4'b0110: data_slope = 8'd4; + 4'b0111: data_slope = 8'd3; + 4'b1000: data_slope = 8'd2; + 4'b1001: data_slope = 8'd0; + 4'b1010: data_slope = 8'd0; + default: data_slope = 8'd0; + endcase +end + +//LUT for the intercept +always @(address) begin + case (address) + 4'b0000: data_intercept = 8'd127; + 4'b0001: data_intercept = 8'd99; + 4'b0010: data_intercept = 8'd46; + 4'b0011: data_intercept = 8'd18; + 4'b0100: data_intercept = 8'd0; + 4'b0101: data_intercept = 8'd0; + 4'b0110: data_intercept = 8'd0; + 4'b0111: data_intercept = -8'd18; + 4'b1000: data_intercept = -8'd46; + 4'b1001: data_intercept = -8'd99; + 4'b1010: data_intercept = -8'd127; + default: data_intercept = 8'd0; + endcase +end + +//Logic to find address +always @(inp_data) begin + if((inp_data)>=90) begin + address = 4'b0000; + end + else if ((inp_data)>=39 && (inp_data)<90) begin + address = 4'b0001; + end + else if ((inp_data)>=28 && (inp_data)<39) begin + address = 4'b0010; + end + else if ((inp_data)>=16 && (inp_data)<28) begin + address = 4'b0011; + end + else if ((inp_data)>=1 && (inp_data)<16) begin + address = 4'b0100; + end + else if ((inp_data)==0) begin + address = 4'b0101; + end + else if ((inp_data)>-16 && (inp_data)<=-1) begin + address = 4'b0110; + end + else if ((inp_data)>-28 && (inp_data)<=-16) begin + address = 4'b0111; + end + else if ((inp_data)>-39 && (inp_data)<=-28) begin + address = 4'b1000; + end + else if ((inp_data)>-90 && (inp_data)<=-39) begin + address = 4'b1001; + end + else if ((inp_data)<=-90) begin + address = 4'b1010; + end + else begin + address = 4'b0101; + end +end + +//Adding a dummy signal to use validity_mask input, to make ODIN happy +//TODO: Need to correctly use validity_mask +wire [`MASK_WIDTH-1:0] dummy; +assign dummy = validity_mask; + + +endmodule + +module top( + input clk, + input clk_mem, + input reset, + input resetn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output [`REG_DATAWIDTH-1:0] PRDATA, + output PREADY, + input [`AWIDTH-1:0] bram_addr_a_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a_ext, + input [`DESIGN_SIZE-1:0] bram_we_a_ext, + input [`AWIDTH-1:0] bram_addr_b_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b_ext, + input [`DESIGN_SIZE-1:0] bram_we_b_ext +); + +wire [`AWIDTH-1:0] bram_addr_a; +wire [`AWIDTH-1:0] bram_addr_a_for_reading; +reg [`AWIDTH-1:0] bram_addr_a_for_writing; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a; +reg [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a; +wire [`DESIGN_SIZE-1:0] bram_we_a; +wire bram_en_a; +wire [`AWIDTH-1:0] bram_addr_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b; +wire [`DESIGN_SIZE-1:0] bram_we_b; +wire bram_en_b; +reg bram_a_wdata_available; +wire [`AWIDTH-1:0] bram_addr_c_NC; +wire start_tpu; +wire done_tpu; +wire start_mat_mul; +wire done_mat_mul; +wire norm_out_data_available; +wire done_norm; +wire pool_out_data_available; +wire done_pool; +wire activation_out_data_available; +wire done_activation; +wire enable_matmul; +wire enable_norm; +wire enable_activation; +wire enable_pool; +wire [31:0] num_matrices_A; +wire [31:0] num_matrices_B; +wire [`DWIDTH-1:0] matrix_size; +wire [`DWIDTH-1:0] filter_size; +wire pool_select; +wire [`DWIDTH-1:0] k_dimension; +wire accum_select; +wire [`DESIGN_SIZE*`DWIDTH-1:0] matmul_c_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] pool_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] activation_data_out; +wire matmul_c_data_available; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_in_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_in_NC; +wire [`DWIDTH-1:0] mean; +wire [`DWIDTH-1:0] inv_var; +wire [`AWIDTH-1:0] address_mat_a; +wire [`AWIDTH-1:0] address_mat_b; +wire [`AWIDTH-1:0] address_mat_c; +wire [`MASK_WIDTH-1:0] validity_mask_a_rows; +wire [`MASK_WIDTH-1:0] validity_mask_a_cols_b_rows; +wire [`MASK_WIDTH-1:0] validity_mask_b_cols; +wire save_output_to_accum; +wire add_accum_to_output; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +wire [`MAX_BITS_POOL-1:0] pool_window_size; +wire activation_type; +wire [3:0] conv_filter_height; +wire [3:0] conv_filter_width; +wire [3:0] conv_stride_horiz; +wire [3:0] conv_stride_verti; +wire [3:0] conv_padding_left; +wire [3:0] conv_padding_right; +wire [3:0] conv_padding_top; +wire [3:0] conv_padding_bottom; +wire [15:0] num_channels_inp; +wire [15:0] num_channels_out; +wire [15:0] inp_img_height; +wire [15:0] inp_img_width; +wire [15:0] out_img_height; +wire [15:0] out_img_width; +wire [31:0] batch_size; +wire enable_conv_mode; +wire pe_reset; +wire start_pool; +wire pool_norm_valid; + +`ifdef DESIGN_SIZE_32 +wire [`DWIDTH-1:0] matrixC31_0; +wire [`DWIDTH-1:0] matrixC31_1; +wire [`DWIDTH-1:0] matrixC31_2; +wire [`DWIDTH-1:0] matrixC31_3; +wire [`DWIDTH-1:0] matrixC31_4; +wire [`DWIDTH-1:0] matrixC31_5; +wire [`DWIDTH-1:0] matrixC31_6; +wire [`DWIDTH-1:0] matrixC31_7; +wire [`DWIDTH-1:0] matrixC31_8; +wire [`DWIDTH-1:0] matrixC31_9; +wire [`DWIDTH-1:0] matrixC31_10; +wire [`DWIDTH-1:0] matrixC31_11; +wire [`DWIDTH-1:0] matrixC31_12; +wire [`DWIDTH-1:0] matrixC31_13; +wire [`DWIDTH-1:0] matrixC31_14; +wire [`DWIDTH-1:0] matrixC31_15; +wire [`DWIDTH-1:0] matrixC31_16; +wire [`DWIDTH-1:0] matrixC31_17; +wire [`DWIDTH-1:0] matrixC31_18; +wire [`DWIDTH-1:0] matrixC31_19; +wire [`DWIDTH-1:0] matrixC31_20; +wire [`DWIDTH-1:0] matrixC31_21; +wire [`DWIDTH-1:0] matrixC31_22; +wire [`DWIDTH-1:0] matrixC31_23; +wire [`DWIDTH-1:0] matrixC31_24; +wire [`DWIDTH-1:0] matrixC31_25; +wire [`DWIDTH-1:0] matrixC31_26; +wire [`DWIDTH-1:0] matrixC31_27; +wire [`DWIDTH-1:0] matrixC31_28; +wire [`DWIDTH-1:0] matrixC31_29; +wire [`DWIDTH-1:0] matrixC31_30; +wire [`DWIDTH-1:0] matrixC31_31; +`endif +`ifdef DESIGN_SIZE_16 +wire [`DWIDTH-1:0] matrixC15_0; +wire [`DWIDTH-1:0] matrixC15_1; +wire [`DWIDTH-1:0] matrixC15_2; +wire [`DWIDTH-1:0] matrixC15_3; +wire [`DWIDTH-1:0] matrixC15_4; +wire [`DWIDTH-1:0] matrixC15_5; +wire [`DWIDTH-1:0] matrixC15_6; +wire [`DWIDTH-1:0] matrixC15_7; +wire [`DWIDTH-1:0] matrixC15_8; +wire [`DWIDTH-1:0] matrixC15_9; +wire [`DWIDTH-1:0] matrixC15_10; +wire [`DWIDTH-1:0] matrixC15_11; +wire [`DWIDTH-1:0] matrixC15_12; +wire [`DWIDTH-1:0] matrixC15_13; +wire [`DWIDTH-1:0] matrixC15_14; +wire [`DWIDTH-1:0] matrixC15_15; +`endif +`ifdef DESIGN_SIZE_8 +wire [`DWIDTH-1:0] matrixC7_0; +wire [`DWIDTH-1:0] matrixC7_1; +wire [`DWIDTH-1:0] matrixC7_2; +wire [`DWIDTH-1:0] matrixC7_3; +wire [`DWIDTH-1:0] matrixC7_4; +wire [`DWIDTH-1:0] matrixC7_5; +wire [`DWIDTH-1:0] matrixC7_6; +wire [`DWIDTH-1:0] matrixC7_7; +`endif +`ifdef DESIGN_SIZE_4 +wire [`DWIDTH-1:0] matrixC3_0; +wire [`DWIDTH-1:0] matrixC3_1; +wire [`DWIDTH-1:0] matrixC3_2; +wire [`DWIDTH-1:0] matrixC3_3; +`endif + +wire [`AWIDTH-1:0] start_waddr_accum0; + +assign start_waddr_accum0 = 11'b0; + +`ifdef DESIGN_SIZE_8 +wire [`DWIDTH-1:0] rdata_accum0_pool; +wire [`DWIDTH-1:0] rdata_accum1_pool; +wire [`DWIDTH-1:0] rdata_accum2_pool; +wire [`DWIDTH-1:0] rdata_accum3_pool; +wire [`DWIDTH-1:0] rdata_accum4_pool; +wire [`DWIDTH-1:0] rdata_accum5_pool; +wire [`DWIDTH-1:0] rdata_accum6_pool; +wire [`DWIDTH-1:0] rdata_accum7_pool; +wire [`AWIDTH-1:0] raddr_accum0_pool; +wire [`AWIDTH-1:0] raddr_accum1_pool; +wire [`AWIDTH-1:0] raddr_accum2_pool; +wire [`AWIDTH-1:0] raddr_accum3_pool; +wire [`AWIDTH-1:0] raddr_accum4_pool; +wire [`AWIDTH-1:0] raddr_accum5_pool; +wire [`AWIDTH-1:0] raddr_accum6_pool; +wire [`AWIDTH-1:0] raddr_accum7_pool; +`endif + +`ifdef DESIGN_SIZE_16 +wire [`DWIDTH-1:0] rdata_accum0_pool; +wire [`DWIDTH-1:0] rdata_accum1_pool; +wire [`DWIDTH-1:0] rdata_accum2_pool; +wire [`DWIDTH-1:0] rdata_accum3_pool; +wire [`DWIDTH-1:0] rdata_accum4_pool; +wire [`DWIDTH-1:0] rdata_accum5_pool; +wire [`DWIDTH-1:0] rdata_accum6_pool; +wire [`DWIDTH-1:0] rdata_accum7_pool; +wire [`DWIDTH-1:0] rdata_accum8_pool; +wire [`DWIDTH-1:0] rdata_accum9_pool; +wire [`DWIDTH-1:0] rdata_accum10_pool; +wire [`DWIDTH-1:0] rdata_accum11_pool; +wire [`DWIDTH-1:0] rdata_accum12_pool; +wire [`DWIDTH-1:0] rdata_accum13_pool; +wire [`DWIDTH-1:0] rdata_accum14_pool; +wire [`DWIDTH-1:0] rdata_accum15_pool; +wire [`AWIDTH-1:0] raddr_accum0_pool; +wire [`AWIDTH-1:0] raddr_accum1_pool; +wire [`AWIDTH-1:0] raddr_accum2_pool; +wire [`AWIDTH-1:0] raddr_accum3_pool; +wire [`AWIDTH-1:0] raddr_accum4_pool; +wire [`AWIDTH-1:0] raddr_accum5_pool; +wire [`AWIDTH-1:0] raddr_accum6_pool; +wire [`AWIDTH-1:0] raddr_accum7_pool; +wire [`AWIDTH-1:0] raddr_accum8_pool; +wire [`AWIDTH-1:0] raddr_accum9_pool; +wire [`AWIDTH-1:0] raddr_accum10_pool; +wire [`AWIDTH-1:0] raddr_accum11_pool; +wire [`AWIDTH-1:0] raddr_accum12_pool; +wire [`AWIDTH-1:0] raddr_accum13_pool; +wire [`AWIDTH-1:0] raddr_accum14_pool; +wire [`AWIDTH-1:0] raddr_accum15_pool; +`endif + +`ifdef DESIGN_SIZE_32 +wire [`DWIDTH-1:0] rdata_accum0_pool; +wire [`DWIDTH-1:0] rdata_accum1_pool; +wire [`DWIDTH-1:0] rdata_accum2_pool; +wire [`DWIDTH-1:0] rdata_accum3_pool; +wire [`DWIDTH-1:0] rdata_accum4_pool; +wire [`DWIDTH-1:0] rdata_accum5_pool; +wire [`DWIDTH-1:0] rdata_accum6_pool; +wire [`DWIDTH-1:0] rdata_accum7_pool; +wire [`DWIDTH-1:0] rdata_accum8_pool; +wire [`DWIDTH-1:0] rdata_accum9_pool; +wire [`DWIDTH-1:0] rdata_accum10_pool; +wire [`DWIDTH-1:0] rdata_accum11_pool; +wire [`DWIDTH-1:0] rdata_accum12_pool; +wire [`DWIDTH-1:0] rdata_accum13_pool; +wire [`DWIDTH-1:0] rdata_accum14_pool; +wire [`DWIDTH-1:0] rdata_accum15_pool; +wire [`DWIDTH-1:0] rdata_accum16_pool; +wire [`DWIDTH-1:0] rdata_accum17_pool; +wire [`DWIDTH-1:0] rdata_accum18_pool; +wire [`DWIDTH-1:0] rdata_accum19_pool; +wire [`DWIDTH-1:0] rdata_accum20_pool; +wire [`DWIDTH-1:0] rdata_accum21_pool; +wire [`DWIDTH-1:0] rdata_accum22_pool; +wire [`DWIDTH-1:0] rdata_accum23_pool; +wire [`DWIDTH-1:0] rdata_accum24_pool; +wire [`DWIDTH-1:0] rdata_accum25_pool; +wire [`DWIDTH-1:0] rdata_accum26_pool; +wire [`DWIDTH-1:0] rdata_accum27_pool; +wire [`DWIDTH-1:0] rdata_accum28_pool; +wire [`DWIDTH-1:0] rdata_accum29_pool; +wire [`DWIDTH-1:0] rdata_accum30_pool; +wire [`DWIDTH-1:0] rdata_accum31_pool; +wire [`AWIDTH-1:0] raddr_accum0_pool; +wire [`AWIDTH-1:0] raddr_accum1_pool; +wire [`AWIDTH-1:0] raddr_accum2_pool; +wire [`AWIDTH-1:0] raddr_accum3_pool; +wire [`AWIDTH-1:0] raddr_accum4_pool; +wire [`AWIDTH-1:0] raddr_accum5_pool; +wire [`AWIDTH-1:0] raddr_accum6_pool; +wire [`AWIDTH-1:0] raddr_accum7_pool; +wire [`AWIDTH-1:0] raddr_accum8_pool; +wire [`AWIDTH-1:0] raddr_accum9_pool; +wire [`AWIDTH-1:0] raddr_accum10_pool; +wire [`AWIDTH-1:0] raddr_accum11_pool; +wire [`AWIDTH-1:0] raddr_accum12_pool; +wire [`AWIDTH-1:0] raddr_accum13_pool; +wire [`AWIDTH-1:0] raddr_accum14_pool; +wire [`AWIDTH-1:0] raddr_accum15_pool; +wire [`AWIDTH-1:0] raddr_accum16_pool; +wire [`AWIDTH-1:0] raddr_accum17_pool; +wire [`AWIDTH-1:0] raddr_accum18_pool; +wire [`AWIDTH-1:0] raddr_accum19_pool; +wire [`AWIDTH-1:0] raddr_accum20_pool; +wire [`AWIDTH-1:0] raddr_accum21_pool; +wire [`AWIDTH-1:0] raddr_accum22_pool; +wire [`AWIDTH-1:0] raddr_accum23_pool; +wire [`AWIDTH-1:0] raddr_accum24_pool; +wire [`AWIDTH-1:0] raddr_accum25_pool; +wire [`AWIDTH-1:0] raddr_accum26_pool; +wire [`AWIDTH-1:0] raddr_accum27_pool; +wire [`AWIDTH-1:0] raddr_accum28_pool; +wire [`AWIDTH-1:0] raddr_accum29_pool; +wire [`AWIDTH-1:0] raddr_accum30_pool; +wire [`AWIDTH-1:0] raddr_accum31_pool; +`endif + +//Connections for bram a (activation/input matrix) +//bram_addr_a -> connected to u_matmul_4x4 +//bram_rdata_a -> connected to u_matmul_4x4 +//bram_wdata_a -> will come from the last block that is enabled +//bram_we_a -> will be 1 when the last block's data is available +//bram_en_a -> hardcoded to 1 +assign bram_addr_a = (bram_a_wdata_available) ? bram_addr_a_for_writing : bram_addr_a_for_reading; +assign bram_en_a = 1'b1; +assign bram_we_a = (bram_a_wdata_available) ? {`DESIGN_SIZE{1'b1}} : {`DESIGN_SIZE{1'b0}}; + +//Connections for bram b (weights matrix) +//bram_addr_b -> connected to u_matmul_4x4 +//bram_rdata_b -> connected to u_matmul_4x4 +//bram_wdata_b -> hardcoded to 0 (this block only reads from bram b) +//bram_we_b -> hardcoded to 0 (this block only reads from bram b) +//bram_en_b -> hardcoded to 1 +assign bram_wdata_b = {`DESIGN_SIZE*`DWIDTH{1'b0}}; +assign bram_en_b = 1'b1; +assign bram_we_b = {`DESIGN_SIZE{1'b0}}; + +//////////////////////////////////////////////////////////////// +// BRAM matrix A (inputs/activations) +//////////////////////////////////////////////////////////////// +ram #(.AW(`AWIDTH), .MW(`MASK_WIDTH), .DW(`DWIDTH)) matrix_A ( + .addr0(bram_addr_a), + .d0(bram_wdata_a), + .we0(bram_we_a), + .q0(bram_rdata_a), + .addr1(bram_addr_a_ext), + .d1(bram_wdata_a_ext), + .we1(bram_we_a_ext), + .q1(bram_rdata_a_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// BRAM matrix B (weights) +//////////////////////////////////////////////////////////////// +ram #(.AW(`AWIDTH), .MW(`MASK_WIDTH), .DW(`DWIDTH)) matrix_B ( + .addr0(bram_addr_b), + .d0(bram_wdata_b), + .we0(bram_we_b), + .q0(bram_rdata_b), + .addr1(bram_addr_b_ext), + .d1(bram_wdata_b_ext), + .we1(bram_we_b_ext), + .q1(bram_rdata_b_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// Control logic that directs all the operation +//////////////////////////////////////////////////////////////// +control u_control( + .clk(clk), + .reset(reset), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_activation(enable_activation), + .enable_pool(enable_pool), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .done_norm(done_norm), + .done_pool(done_pool), + .done_activation(done_activation), + .save_output_to_accum(save_output_to_accum), + .done_tpu(done_tpu) +); + +//////////////////////////////////////////////////////////////// +// Configuration (register) block +//////////////////////////////////////////////////////////////// +cfg u_cfg( + .PCLK(clk), + .PRESETn(resetn), + .PADDR(PADDR), + .PWRITE(PWRITE), + .PSEL(PSEL), + .PENABLE(PENABLE), + .PWDATA(PWDATA), + .PRDATA(PRDATA), + .PREADY(PREADY), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_pool(enable_pool), + .enable_activation(enable_activation), + .enable_conv_mode(enable_conv_mode), + .mean(mean), + .inv_var(inv_var), + .pool_window_size(pool_window_size), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .num_matrices_A(num_matrices_A), + .num_matrices_B(num_matrices_B), + .matrix_size(matrix_size), + .filter_size(filter_size), + .pool_select(pool_select), + .k_dimension(k_dimension), // Dimension of A = m x k, Dimension of B = k x n + .accum_select(accum_select), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols_b_rows(validity_mask_a_cols_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .save_output_to_accum(save_output_to_accum), + .add_accum_to_output(add_accum_to_output), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .activation_type(activation_type), + .conv_filter_height(conv_filter_height), + .conv_filter_width(conv_filter_width), + .conv_stride_horiz(conv_stride_horiz), + .conv_stride_verti(conv_stride_verti), + .conv_padding_left(conv_padding_left), + .conv_padding_right(conv_padding_right), + .conv_padding_top(conv_padding_top), + .conv_padding_bottom(conv_padding_bottom), + .num_channels_inp(num_channels_inp), + .num_channels_out(num_channels_out), + .inp_img_height(inp_img_height), + .inp_img_width(inp_img_width), + .out_img_height(out_img_height), + .out_img_width(out_img_width), + .batch_size(batch_size), + .pe_reset(pe_reset), + .done_tpu(done_tpu) +); + +//TODO: We want to move the data setup part +//and the interface to BRAM_A and BRAM_B outside +//into its own modules. For now, it is all inside +//the matmul block + +//////////////////////////////////////////////////////////////// +//Matrix multiplier +//Note: the ports on this module to write data to bram c +//are not used in this top module. +//////////////////////////////////////////////////////////////// +`ifdef DESIGN_SIZE_32 +matmul_32x32_systolic u_matmul( +`endif +`ifdef DESIGN_SIZE_16 +matmul_16x16_systolic u_matmul( +`endif +`ifdef DESIGN_SIZE_8 +matmul_8x8_systolic u_matmul( +`endif +`ifdef DESIGN_SIZE_4 +matmul_4x4_systolic u_matmul( +`endif + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .num_matrices_A(num_matrices_A), + .num_matrices_B(num_matrices_B), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .a_data(bram_rdata_a), + .b_data(bram_rdata_b), + .a_data_in(a_data_in_NC), + .b_data_in(b_data_in_NC), + .c_data_in({`DESIGN_SIZE*`DWIDTH{1'b0}}), + .c_data_out(matmul_c_data_out), + .a_data_out(a_data_out_NC), + .b_data_out(b_data_out_NC), + .a_addr(bram_addr_a_for_reading), + .b_addr(bram_addr_b), + .c_addr(bram_addr_c_NC), + .c_data_available(matmul_c_data_available), + `ifdef DESIGN_SIZE_32 + .matrixC31_0(matrixC31_0), + .matrixC31_1(matrixC31_1), + .matrixC31_2(matrixC31_2), + .matrixC31_3(matrixC31_3), + .matrixC31_4(matrixC31_4), + .matrixC31_5(matrixC31_5), + .matrixC31_6(matrixC31_6), + .matrixC31_7(matrixC31_7), + .matrixC31_8(matrixC31_8), + .matrixC31_9(matrixC31_9), + .matrixC31_10(matrixC31_10), + .matrixC31_11(matrixC31_11), + .matrixC31_12(matrixC31_12), + .matrixC31_13(matrixC31_13), + .matrixC31_14(matrixC31_14), + .matrixC31_15(matrixC31_15), + .matrixC31_16(matrixC31_16), + .matrixC31_17(matrixC31_17), + .matrixC31_18(matrixC31_18), + .matrixC31_19(matrixC31_19), + .matrixC31_20(matrixC31_20), + .matrixC31_21(matrixC31_21), + .matrixC31_22(matrixC31_22), + .matrixC31_23(matrixC31_23), + .matrixC31_24(matrixC31_24), + .matrixC31_25(matrixC31_25), + .matrixC31_26(matrixC31_26), + .matrixC31_27(matrixC31_27), + .matrixC31_28(matrixC31_28), + .matrixC31_29(matrixC31_29), + .matrixC31_30(matrixC31_30), + .matrixC31_31(matrixC31_31), + `endif + `ifdef DESIGN_SIZE_16 + .matrixC15_0(matrixC15_0), + .matrixC15_1(matrixC15_1), + .matrixC15_2(matrixC15_2), + .matrixC15_3(matrixC15_3), + .matrixC15_4(matrixC15_4), + .matrixC15_5(matrixC15_5), + .matrixC15_6(matrixC15_6), + .matrixC15_7(matrixC15_7), + .matrixC15_8(matrixC15_8), + .matrixC15_9(matrixC15_9), + .matrixC15_10(matrixC15_10), + .matrixC15_11(matrixC15_11), + .matrixC15_12(matrixC15_12), + .matrixC15_13(matrixC15_13), + .matrixC15_14(matrixC15_14), + .matrixC15_15(matrixC15_15), + `endif + `ifdef DESIGN_SIZE_8 + .matrixC7_0(matrixC7_0), + .matrixC7_1(matrixC7_1), + .matrixC7_2(matrixC7_2), + .matrixC7_3(matrixC7_3), + .matrixC7_4(matrixC7_4), + .matrixC7_5(matrixC7_5), + .matrixC7_6(matrixC7_6), + .matrixC7_7(matrixC7_7), + `endif + `ifdef DESIGN_SIZE_4 + .matrixC3_0(matrixC3_0), + .matrixC3_1(matrixC3_1), + .matrixC3_2(matrixC3_2), + .matrixC3_3(matrixC3_3), + `endif + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols_b_rows(validity_mask_a_cols_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .a_loc(32'd0), + .b_loc(32'd0) +); + +//////////////////////////////////////////////////////////////// +// Accumulator module +//////////////////////////////////////////////////////////////// +accumulator u_accum ( + .clk(clk), + .resetn(resetn), + .k_dimension(k_dimension), // Dimension of A = m x k, Dimension of B = k x n + .buffer_select(accum_select), + .start_pooling(start_pool), + .done_pooling(done_pool), + .wdata_available(matmul_c_data_available), + .start_waddr_accum0(start_waddr_accum0), + `ifdef DESIGN_SIZE_8 + .wdata_accum0(matrixC7_0), + .wdata_accum1(matrixC7_1), + .wdata_accum2(matrixC7_2), + .wdata_accum3(matrixC7_3), + .wdata_accum4(matrixC7_4), + .wdata_accum5(matrixC7_5), + .wdata_accum6(matrixC7_6), + .wdata_accum7(matrixC7_7), + .raddr_accum0_pool(raddr_accum0_pool), + .raddr_accum1_pool(raddr_accum1_pool), + .raddr_accum2_pool(raddr_accum2_pool), + .raddr_accum3_pool(raddr_accum3_pool), + .raddr_accum4_pool(raddr_accum4_pool), + .raddr_accum5_pool(raddr_accum5_pool), + .raddr_accum6_pool(raddr_accum6_pool), + .raddr_accum7_pool(raddr_accum7_pool), + .rdata_accum0_pool(rdata_accum0_pool), + .rdata_accum1_pool(rdata_accum1_pool), + .rdata_accum2_pool(rdata_accum2_pool), + .rdata_accum3_pool(rdata_accum3_pool), + .rdata_accum4_pool(rdata_accum4_pool), + .rdata_accum5_pool(rdata_accum5_pool), + .rdata_accum6_pool(rdata_accum6_pool), + .rdata_accum7_pool(rdata_accum7_pool) + `endif + `ifdef DESIGN_SIZE_16 + .wdata_accum0(matrixC15_0), + .wdata_accum1(matrixC15_1), + .wdata_accum2(matrixC15_2), + .wdata_accum3(matrixC15_3), + .wdata_accum4(matrixC15_4), + .wdata_accum5(matrixC15_5), + .wdata_accum6(matrixC15_6), + .wdata_accum7(matrixC15_7), + .wdata_accum8(matrixC15_8), + .wdata_accum9(matrixC15_9), + .wdata_accum10(matrixC15_10), + .wdata_accum11(matrixC15_11), + .wdata_accum12(matrixC15_12), + .wdata_accum13(matrixC15_13), + .wdata_accum14(matrixC15_14), + .wdata_accum15(matrixC15_15), + .raddr_accum0_pool(raddr_accum0_pool), + .raddr_accum1_pool(raddr_accum1_pool), + .raddr_accum2_pool(raddr_accum2_pool), + .raddr_accum3_pool(raddr_accum3_pool), + .raddr_accum4_pool(raddr_accum4_pool), + .raddr_accum5_pool(raddr_accum5_pool), + .raddr_accum6_pool(raddr_accum6_pool), + .raddr_accum7_pool(raddr_accum7_pool), + .raddr_accum8_pool(raddr_accum8_pool), + .raddr_accum9_pool(raddr_accum9_pool), + .raddr_accum10_pool(raddr_accum10_pool), + .raddr_accum11_pool(raddr_accum11_pool), + .raddr_accum12_pool(raddr_accum12_pool), + .raddr_accum13_pool(raddr_accum13_pool), + .raddr_accum14_pool(raddr_accum14_pool), + .raddr_accum15_pool(raddr_accum15_pool), + .rdata_accum0_pool(rdata_accum0_pool), + .rdata_accum1_pool(rdata_accum1_pool), + .rdata_accum2_pool(rdata_accum2_pool), + .rdata_accum3_pool(rdata_accum3_pool), + .rdata_accum4_pool(rdata_accum4_pool), + .rdata_accum5_pool(rdata_accum5_pool), + .rdata_accum6_pool(rdata_accum6_pool), + .rdata_accum7_pool(rdata_accum7_pool), + .rdata_accum8_pool(rdata_accum8_pool), + .rdata_accum9_pool(rdata_accum9_pool), + .rdata_accum10_pool(rdata_accum10_pool), + .rdata_accum11_pool(rdata_accum11_pool), + .rdata_accum12_pool(rdata_accum12_pool), + .rdata_accum13_pool(rdata_accum13_pool), + .rdata_accum14_pool(rdata_accum14_pool), + .rdata_accum15_pool(rdata_accum15_pool) + `endif + `ifdef DESIGN_SIZE_32 + .wdata_accum0(matrixC31_0), + .wdata_accum1(matrixC31_1), + .wdata_accum2(matrixC31_2), + .wdata_accum3(matrixC31_3), + .wdata_accum4(matrixC31_4), + .wdata_accum5(matrixC31_5), + .wdata_accum6(matrixC31_6), + .wdata_accum7(matrixC31_7), + .wdata_accum8(matrixC31_8), + .wdata_accum9(matrixC31_9), + .wdata_accum10(matrixC31_10), + .wdata_accum11(matrixC31_11), + .wdata_accum12(matrixC31_12), + .wdata_accum13(matrixC31_13), + .wdata_accum14(matrixC31_14), + .wdata_accum15(matrixC31_15), + .wdata_accum16(matrixC31_16), + .wdata_accum17(matrixC31_17), + .wdata_accum18(matrixC31_18), + .wdata_accum19(matrixC31_19), + .wdata_accum20(matrixC31_20), + .wdata_accum21(matrixC31_21), + .wdata_accum22(matrixC31_22), + .wdata_accum23(matrixC31_23), + .wdata_accum24(matrixC31_24), + .wdata_accum25(matrixC31_25), + .wdata_accum26(matrixC31_26), + .wdata_accum27(matrixC31_27), + .wdata_accum28(matrixC31_28), + .wdata_accum29(matrixC31_29), + .wdata_accum30(matrixC31_30), + .wdata_accum31(matrixC31_31), + .raddr_accum0_pool(raddr_accum0_pool), + .raddr_accum1_pool(raddr_accum1_pool), + .raddr_accum2_pool(raddr_accum2_pool), + .raddr_accum3_pool(raddr_accum3_pool), + .raddr_accum4_pool(raddr_accum4_pool), + .raddr_accum5_pool(raddr_accum5_pool), + .raddr_accum6_pool(raddr_accum6_pool), + .raddr_accum7_pool(raddr_accum7_pool), + .raddr_accum8_pool(raddr_accum8_pool), + .raddr_accum9_pool(raddr_accum9_pool), + .raddr_accum10_pool(raddr_accum10_pool), + .raddr_accum11_pool(raddr_accum11_pool), + .raddr_accum12_pool(raddr_accum12_pool), + .raddr_accum13_pool(raddr_accum13_pool), + .raddr_accum14_pool(raddr_accum14_pool), + .raddr_accum15_pool(raddr_accum15_pool), + .raddr_accum16_pool(raddr_accum16_pool), + .raddr_accum17_pool(raddr_accum17_pool), + .raddr_accum18_pool(raddr_accum18_pool), + .raddr_accum19_pool(raddr_accum19_pool), + .raddr_accum20_pool(raddr_accum20_pool), + .raddr_accum21_pool(raddr_accum21_pool), + .raddr_accum22_pool(raddr_accum22_pool), + .raddr_accum23_pool(raddr_accum23_pool), + .raddr_accum24_pool(raddr_accum24_pool), + .raddr_accum25_pool(raddr_accum25_pool), + .raddr_accum26_pool(raddr_accum26_pool), + .raddr_accum27_pool(raddr_accum27_pool), + .raddr_accum28_pool(raddr_accum28_pool), + .raddr_accum29_pool(raddr_accum29_pool), + .raddr_accum30_pool(raddr_accum30_pool), + .raddr_accum31_pool(raddr_accum31_pool), + .rdata_accum0_pool(rdata_accum0_pool), + .rdata_accum1_pool(rdata_accum1_pool), + .rdata_accum2_pool(rdata_accum2_pool), + .rdata_accum3_pool(rdata_accum3_pool), + .rdata_accum4_pool(rdata_accum4_pool), + .rdata_accum5_pool(rdata_accum5_pool), + .rdata_accum6_pool(rdata_accum6_pool), + .rdata_accum7_pool(rdata_accum7_pool), + .rdata_accum8_pool(rdata_accum8_pool), + .rdata_accum9_pool(rdata_accum9_pool), + .rdata_accum10_pool(rdata_accum10_pool), + .rdata_accum11_pool(rdata_accum11_pool), + .rdata_accum12_pool(rdata_accum12_pool), + .rdata_accum13_pool(rdata_accum13_pool), + .rdata_accum14_pool(rdata_accum14_pool), + .rdata_accum15_pool(rdata_accum15_pool), + .rdata_accum16_pool(rdata_accum16_pool), + .rdata_accum17_pool(rdata_accum17_pool), + .rdata_accum18_pool(rdata_accum18_pool), + .rdata_accum19_pool(rdata_accum19_pool), + .rdata_accum20_pool(rdata_accum20_pool), + .rdata_accum21_pool(rdata_accum21_pool), + .rdata_accum22_pool(rdata_accum22_pool), + .rdata_accum23_pool(rdata_accum23_pool), + .rdata_accum24_pool(rdata_accum24_pool), + .rdata_accum25_pool(rdata_accum25_pool), + .rdata_accum26_pool(rdata_accum26_pool), + .rdata_accum27_pool(rdata_accum27_pool), + .rdata_accum28_pool(rdata_accum28_pool), + .rdata_accum29_pool(rdata_accum29_pool), + .rdata_accum30_pool(rdata_accum30_pool), + .rdata_accum31_pool(rdata_accum31_pool) + `endif +); + +wire [`DWIDTH-1:0] pool0; +wire [`DWIDTH-1:0] pool1; +wire [`DWIDTH-1:0] pool2; +wire [`DWIDTH-1:0] pool3; +wire [`DWIDTH-1:0] pool4; +wire [`DWIDTH-1:0] pool5; +wire [`DWIDTH-1:0] pool6; +wire [`DWIDTH-1:0] pool7; +wire [`DWIDTH-1:0] pool8; +wire [`DWIDTH-1:0] pool9; +wire [`DWIDTH-1:0] pool10; +wire [`DWIDTH-1:0] pool11; +wire [`DWIDTH-1:0] pool12; +wire [`DWIDTH-1:0] pool13; +wire [`DWIDTH-1:0] pool14; +wire [`DWIDTH-1:0] pool15; +wire [`DWIDTH-1:0] pool16; +wire [`DWIDTH-1:0] pool17; +wire [`DWIDTH-1:0] pool18; +wire [`DWIDTH-1:0] pool19; +wire [`DWIDTH-1:0] pool20; +wire [`DWIDTH-1:0] pool21; +wire [`DWIDTH-1:0] pool22; +wire [`DWIDTH-1:0] pool23; +wire [`DWIDTH-1:0] pool24; +wire [`DWIDTH-1:0] pool25; +wire [`DWIDTH-1:0] pool26; +wire [`DWIDTH-1:0] pool27; +wire [`DWIDTH-1:0] pool28; +wire [`DWIDTH-1:0] pool29; +wire [`DWIDTH-1:0] pool30; +wire [`DWIDTH-1:0] pool31; + +wire [`DWIDTH-1:0] norm_data_out0; +wire [`DWIDTH-1:0] norm_data_out1; +wire [`DWIDTH-1:0] norm_data_out2; +wire [`DWIDTH-1:0] norm_data_out3; +wire [`DWIDTH-1:0] norm_data_out4; +wire [`DWIDTH-1:0] norm_data_out5; +wire [`DWIDTH-1:0] norm_data_out6; +wire [`DWIDTH-1:0] norm_data_out7; +wire [`DWIDTH-1:0] norm_data_out8; +wire [`DWIDTH-1:0] norm_data_out9; +wire [`DWIDTH-1:0] norm_data_out10; +wire [`DWIDTH-1:0] norm_data_out11; +wire [`DWIDTH-1:0] norm_data_out12; +wire [`DWIDTH-1:0] norm_data_out13; +wire [`DWIDTH-1:0] norm_data_out14; +wire [`DWIDTH-1:0] norm_data_out15; +wire [`DWIDTH-1:0] norm_data_out16; +wire [`DWIDTH-1:0] norm_data_out17; +wire [`DWIDTH-1:0] norm_data_out18; +wire [`DWIDTH-1:0] norm_data_out19; +wire [`DWIDTH-1:0] norm_data_out20; +wire [`DWIDTH-1:0] norm_data_out21; +wire [`DWIDTH-1:0] norm_data_out22; +wire [`DWIDTH-1:0] norm_data_out23; +wire [`DWIDTH-1:0] norm_data_out24; +wire [`DWIDTH-1:0] norm_data_out25; +wire [`DWIDTH-1:0] norm_data_out26; +wire [`DWIDTH-1:0] norm_data_out27; +wire [`DWIDTH-1:0] norm_data_out28; +wire [`DWIDTH-1:0] norm_data_out29; +wire [`DWIDTH-1:0] norm_data_out30; +wire [`DWIDTH-1:0] norm_data_out31; + +wire [`DWIDTH-1:0] act_data_out0; +wire [`DWIDTH-1:0] act_data_out1; +wire [`DWIDTH-1:0] act_data_out2; +wire [`DWIDTH-1:0] act_data_out3; +wire [`DWIDTH-1:0] act_data_out4; +wire [`DWIDTH-1:0] act_data_out5; +wire [`DWIDTH-1:0] act_data_out6; +wire [`DWIDTH-1:0] act_data_out7; +wire [`DWIDTH-1:0] act_data_out8; +wire [`DWIDTH-1:0] act_data_out9; +wire [`DWIDTH-1:0] act_data_out10; +wire [`DWIDTH-1:0] act_data_out11; +wire [`DWIDTH-1:0] act_data_out12; +wire [`DWIDTH-1:0] act_data_out13; +wire [`DWIDTH-1:0] act_data_out14; +wire [`DWIDTH-1:0] act_data_out15; +wire [`DWIDTH-1:0] act_data_out16; +wire [`DWIDTH-1:0] act_data_out17; +wire [`DWIDTH-1:0] act_data_out18; +wire [`DWIDTH-1:0] act_data_out19; +wire [`DWIDTH-1:0] act_data_out20; +wire [`DWIDTH-1:0] act_data_out21; +wire [`DWIDTH-1:0] act_data_out22; +wire [`DWIDTH-1:0] act_data_out23; +wire [`DWIDTH-1:0] act_data_out24; +wire [`DWIDTH-1:0] act_data_out25; +wire [`DWIDTH-1:0] act_data_out26; +wire [`DWIDTH-1:0] act_data_out27; +wire [`DWIDTH-1:0] act_data_out28; +wire [`DWIDTH-1:0] act_data_out29; +wire [`DWIDTH-1:0] act_data_out30; +wire [`DWIDTH-1:0] act_data_out31; + +//////////////////////////////////////////////////////////////// +// Pooling module +//////////////////////////////////////////////////////////////// +pooling u_pooling ( + .clk(clk), + .resetn(resetn), + .matrix_size(matrix_size), + .filter_size(filter_size), + .enable_pool(enable_pool), + .pool_select(pool_select), + .start_pooling(start_pool), + .pool_norm_valid(pool_norm_valid), + `ifdef DESIGN_SIZE_8 + .raddr_accum0_pool(raddr_accum0_pool), + .raddr_accum1_pool(raddr_accum1_pool), + .raddr_accum2_pool(raddr_accum2_pool), + .raddr_accum3_pool(raddr_accum3_pool), + .raddr_accum4_pool(raddr_accum4_pool), + .raddr_accum5_pool(raddr_accum5_pool), + .raddr_accum6_pool(raddr_accum6_pool), + .raddr_accum7_pool(raddr_accum7_pool), + .rdata_accum0_pool(rdata_accum0_pool), + .rdata_accum1_pool(rdata_accum1_pool), + .rdata_accum2_pool(rdata_accum2_pool), + .rdata_accum3_pool(rdata_accum3_pool), + .rdata_accum4_pool(rdata_accum4_pool), + .rdata_accum5_pool(rdata_accum5_pool), + .rdata_accum6_pool(rdata_accum6_pool), + .rdata_accum7_pool(rdata_accum7_pool), + .pool0(pool0), + .pool1(pool1), + .pool2(pool2), + .pool3(pool3), + .pool4(pool4), + .pool5(pool5), + .pool6(pool6), + .pool7(pool7) + `endif + `ifdef DESIGN_SIZE_16 + .raddr_accum0_pool(raddr_accum0_pool), + .raddr_accum1_pool(raddr_accum1_pool), + .raddr_accum2_pool(raddr_accum2_pool), + .raddr_accum3_pool(raddr_accum3_pool), + .raddr_accum4_pool(raddr_accum4_pool), + .raddr_accum5_pool(raddr_accum5_pool), + .raddr_accum6_pool(raddr_accum6_pool), + .raddr_accum7_pool(raddr_accum7_pool), + .raddr_accum8_pool(raddr_accum8_pool), + .raddr_accum9_pool(raddr_accum9_pool), + .raddr_accum10_pool(raddr_accum10_pool), + .raddr_accum11_pool(raddr_accum11_pool), + .raddr_accum12_pool(raddr_accum12_pool), + .raddr_accum13_pool(raddr_accum13_pool), + .raddr_accum14_pool(raddr_accum14_pool), + .raddr_accum15_pool(raddr_accum15_pool), + .rdata_accum0_pool(rdata_accum0_pool), + .rdata_accum1_pool(rdata_accum1_pool), + .rdata_accum2_pool(rdata_accum2_pool), + .rdata_accum3_pool(rdata_accum3_pool), + .rdata_accum4_pool(rdata_accum4_pool), + .rdata_accum5_pool(rdata_accum5_pool), + .rdata_accum6_pool(rdata_accum6_pool), + .rdata_accum7_pool(rdata_accum7_pool), + .rdata_accum8_pool(rdata_accum8_pool), + .rdata_accum9_pool(rdata_accum9_pool), + .rdata_accum10_pool(rdata_accum10_pool), + .rdata_accum11_pool(rdata_accum11_pool), + .rdata_accum12_pool(rdata_accum12_pool), + .rdata_accum13_pool(rdata_accum13_pool), + .rdata_accum14_pool(rdata_accum14_pool), + .rdata_accum15_pool(rdata_accum15_pool), + .pool0(pool0), + .pool1(pool1), + .pool2(pool2), + .pool3(pool3), + .pool4(pool4), + .pool5(pool5), + .pool6(pool6), + .pool7(pool7), + .pool8(pool8), + .pool9(pool9), + .pool10(pool10), + .pool11(pool11), + .pool12(pool12), + .pool13(pool13), + .pool14(pool14), + .pool15(pool15) + `endif + `ifdef DESIGN_SIZE_32 + .raddr_accum0_pool(raddr_accum0_pool), + .raddr_accum1_pool(raddr_accum1_pool), + .raddr_accum2_pool(raddr_accum2_pool), + .raddr_accum3_pool(raddr_accum3_pool), + .raddr_accum4_pool(raddr_accum4_pool), + .raddr_accum5_pool(raddr_accum5_pool), + .raddr_accum6_pool(raddr_accum6_pool), + .raddr_accum7_pool(raddr_accum7_pool), + .raddr_accum8_pool(raddr_accum8_pool), + .raddr_accum9_pool(raddr_accum9_pool), + .raddr_accum10_pool(raddr_accum10_pool), + .raddr_accum11_pool(raddr_accum11_pool), + .raddr_accum12_pool(raddr_accum12_pool), + .raddr_accum13_pool(raddr_accum13_pool), + .raddr_accum14_pool(raddr_accum14_pool), + .raddr_accum15_pool(raddr_accum15_pool), + .raddr_accum16_pool(raddr_accum16_pool), + .raddr_accum17_pool(raddr_accum17_pool), + .raddr_accum18_pool(raddr_accum18_pool), + .raddr_accum19_pool(raddr_accum19_pool), + .raddr_accum20_pool(raddr_accum20_pool), + .raddr_accum21_pool(raddr_accum21_pool), + .raddr_accum22_pool(raddr_accum22_pool), + .raddr_accum23_pool(raddr_accum23_pool), + .raddr_accum24_pool(raddr_accum24_pool), + .raddr_accum25_pool(raddr_accum25_pool), + .raddr_accum26_pool(raddr_accum26_pool), + .raddr_accum27_pool(raddr_accum27_pool), + .raddr_accum28_pool(raddr_accum28_pool), + .raddr_accum29_pool(raddr_accum29_pool), + .raddr_accum30_pool(raddr_accum30_pool), + .raddr_accum31_pool(raddr_accum31_pool), + .rdata_accum0_pool(rdata_accum0_pool), + .rdata_accum1_pool(rdata_accum1_pool), + .rdata_accum2_pool(rdata_accum2_pool), + .rdata_accum3_pool(rdata_accum3_pool), + .rdata_accum4_pool(rdata_accum4_pool), + .rdata_accum5_pool(rdata_accum5_pool), + .rdata_accum6_pool(rdata_accum6_pool), + .rdata_accum7_pool(rdata_accum7_pool), + .rdata_accum8_pool(rdata_accum8_pool), + .rdata_accum9_pool(rdata_accum9_pool), + .rdata_accum10_pool(rdata_accum10_pool), + .rdata_accum11_pool(rdata_accum11_pool), + .rdata_accum12_pool(rdata_accum12_pool), + .rdata_accum13_pool(rdata_accum13_pool), + .rdata_accum14_pool(rdata_accum14_pool), + .rdata_accum15_pool(rdata_accum15_pool), + .rdata_accum16_pool(rdata_accum16_pool), + .rdata_accum17_pool(rdata_accum17_pool), + .rdata_accum18_pool(rdata_accum18_pool), + .rdata_accum19_pool(rdata_accum19_pool), + .rdata_accum20_pool(rdata_accum20_pool), + .rdata_accum21_pool(rdata_accum21_pool), + .rdata_accum22_pool(rdata_accum22_pool), + .rdata_accum23_pool(rdata_accum23_pool), + .rdata_accum24_pool(rdata_accum24_pool), + .rdata_accum25_pool(rdata_accum25_pool), + .rdata_accum26_pool(rdata_accum26_pool), + .rdata_accum27_pool(rdata_accum27_pool), + .rdata_accum28_pool(rdata_accum28_pool), + .rdata_accum29_pool(rdata_accum29_pool), + .rdata_accum30_pool(rdata_accum30_pool), + .rdata_accum31_pool(rdata_accum31_pool), + .pool0(pool0), + .pool1(pool1), + .pool2(pool2), + .pool3(pool3), + .pool4(pool4), + .pool5(pool5), + .pool6(pool6), + .pool7(pool7), + .pool8(pool8), + .pool9(pool9), + .pool10(pool10), + .pool11(pool11), + .pool12(pool12), + .pool13(pool13), + .pool14(pool14), + .pool15(pool15), + .pool16(pool16), + .pool17(pool17), + .pool18(pool18), + .pool19(pool19), + .pool20(pool20), + .pool21(pool21), + .pool22(pool22), + .pool23(pool23), + .pool24(pool24), + .pool25(pool25), + .pool26(pool26), + .pool27(pool27), + .pool28(pool28), + .pool29(pool29), + .pool30(pool30), + .pool31(pool31) + `endif +); + + +//////////////////////////////////////////////////////////////// +// Normalization module +//////////////////////////////////////////////////////////////// +norm u_norm( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(pool_norm_valid), + `ifdef DESIGN_SIZE_8 + .inp_data0(pool0), + .inp_data1(pool1), + .inp_data2(pool2), + .inp_data3(pool3), + .inp_data4(pool4), + .inp_data5(pool5), + .inp_data6(pool6), + .inp_data7(pool7), + .out_data0(norm_data_out0), + .out_data1(norm_data_out1), + .out_data2(norm_data_out2), + .out_data3(norm_data_out3), + .out_data4(norm_data_out4), + .out_data5(norm_data_out5), + .out_data6(norm_data_out6), + .out_data7(norm_data_out7), + `endif + `ifdef DESIGN_SIZE_16 + .inp_data0(pool0), + .inp_data1(pool1), + .inp_data2(pool2), + .inp_data3(pool3), + .inp_data4(pool4), + .inp_data5(pool5), + .inp_data6(pool6), + .inp_data7(pool7), + .inp_data8(pool8), + .inp_data9(pool9), + .inp_data10(pool10), + .inp_data11(pool11), + .inp_data12(pool12), + .inp_data13(pool13), + .inp_data14(pool14), + .inp_data15(pool15), + .out_data0(norm_data_out0), + .out_data1(norm_data_out1), + .out_data2(norm_data_out2), + .out_data3(norm_data_out3), + .out_data4(norm_data_out4), + .out_data5(norm_data_out5), + .out_data6(norm_data_out6), + .out_data7(norm_data_out7), + .out_data8(norm_data_out8), + .out_data9(norm_data_out9), + .out_data10(norm_data_out10), + .out_data11(norm_data_out11), + .out_data12(norm_data_out12), + .out_data13(norm_data_out13), + .out_data14(norm_data_out14), + .out_data15(norm_data_out15), + `endif + `ifdef DESIGN_SIZE_32 + .inp_data0(pool0), + .inp_data1(pool1), + .inp_data2(pool2), + .inp_data3(pool3), + .inp_data4(pool4), + .inp_data5(pool5), + .inp_data6(pool6), + .inp_data7(pool7), + .inp_data8(pool8), + .inp_data9(pool9), + .inp_data10(pool10), + .inp_data11(pool11), + .inp_data12(pool12), + .inp_data13(pool13), + .inp_data14(pool14), + .inp_data15(pool15), + .inp_data16(pool16), + .inp_data17(pool17), + .inp_data18(pool18), + .inp_data19(pool19), + .inp_data20(pool20), + .inp_data21(pool21), + .inp_data22(pool22), + .inp_data23(pool23), + .inp_data24(pool24), + .inp_data25(pool25), + .inp_data26(pool26), + .inp_data27(pool27), + .inp_data28(pool28), + .inp_data29(pool29), + .inp_data30(pool30), + .inp_data31(pool31), + .out_data0(norm_data_out0), + .out_data1(norm_data_out1), + .out_data2(norm_data_out2), + .out_data3(norm_data_out3), + .out_data4(norm_data_out4), + .out_data5(norm_data_out5), + .out_data6(norm_data_out6), + .out_data7(norm_data_out7), + .out_data8(norm_data_out8), + .out_data9(norm_data_out9), + .out_data10(norm_data_out10), + .out_data11(norm_data_out11), + .out_data12(norm_data_out12), + .out_data13(norm_data_out13), + .out_data14(norm_data_out14), + .out_data15(norm_data_out15), + .out_data16(norm_data_out16), + .out_data17(norm_data_out17), + .out_data18(norm_data_out18), + .out_data19(norm_data_out19), + .out_data20(norm_data_out20), + .out_data21(norm_data_out21), + .out_data22(norm_data_out22), + .out_data23(norm_data_out23), + .out_data24(norm_data_out24), + .out_data25(norm_data_out25), + .out_data26(norm_data_out26), + .out_data27(norm_data_out27), + .out_data28(norm_data_out28), + .out_data29(norm_data_out29), + .out_data30(norm_data_out30), + .out_data31(norm_data_out31), + `endif + .out_data_available(norm_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_norm(done_norm), + .clk(clk), + .reset(reset) +); + +//////////////////////////////////////////////////////////////// +// Activation module +//////////////////////////////////////////////////////////////// +activation u_activation( + .activation_type(activation_type), + .enable_activation(enable_activation), + .enable_pool(enable_pool), + .in_data_available(norm_out_data_available), + `ifdef DESIGN_SIZE_8 + .inp_data0(norm_data_out0), + .inp_data1(norm_data_out1), + .inp_data2(norm_data_out2), + .inp_data3(norm_data_out3), + .inp_data4(norm_data_out4), + .inp_data5(norm_data_out5), + .inp_data6(norm_data_out6), + .inp_data7(norm_data_out7), + .out_data0(act_data_out0), + .out_data1(act_data_out1), + .out_data2(act_data_out2), + .out_data3(act_data_out3), + .out_data4(act_data_out4), + .out_data5(act_data_out5), + .out_data6(act_data_out6), + .out_data7(act_data_out7), + `endif + `ifdef DESIGN_SIZE_16 + .inp_data0(norm_data_out0), + .inp_data1(norm_data_out1), + .inp_data2(norm_data_out2), + .inp_data3(norm_data_out3), + .inp_data4(norm_data_out4), + .inp_data5(norm_data_out5), + .inp_data6(norm_data_out6), + .inp_data7(norm_data_out7), + .inp_data8(norm_data_out8), + .inp_data9(norm_data_out9), + .inp_data10(norm_data_out10), + .inp_data11(norm_data_out11), + .inp_data12(norm_data_out12), + .inp_data13(norm_data_out13), + .inp_data14(norm_data_out14), + .inp_data15(norm_data_out15), + .out_data0(act_data_out0), + .out_data1(act_data_out1), + .out_data2(act_data_out2), + .out_data3(act_data_out3), + .out_data4(act_data_out4), + .out_data5(act_data_out5), + .out_data6(act_data_out6), + .out_data7(act_data_out7), + .out_data8(act_data_out8), + .out_data9(act_data_out9), + .out_data10(act_data_out10), + .out_data11(act_data_out11), + .out_data12(act_data_out12), + .out_data13(act_data_out13), + .out_data14(act_data_out14), + .out_data15(act_data_out15), + `endif + `ifdef DESIGN_SIZE_32 + .inp_data0(norm_data_out0), + .inp_data1(norm_data_out1), + .inp_data2(norm_data_out2), + .inp_data3(norm_data_out3), + .inp_data4(norm_data_out4), + .inp_data5(norm_data_out5), + .inp_data6(norm_data_out6), + .inp_data7(norm_data_out7), + .inp_data8(norm_data_out8), + .inp_data9(norm_data_out9), + .inp_data10(norm_data_out10), + .inp_data11(norm_data_out11), + .inp_data12(norm_data_out12), + .inp_data13(norm_data_out13), + .inp_data14(norm_data_out14), + .inp_data15(norm_data_out15), + .inp_data16(norm_data_out16), + .inp_data17(norm_data_out17), + .inp_data18(norm_data_out18), + .inp_data19(norm_data_out19), + .inp_data20(norm_data_out20), + .inp_data21(norm_data_out21), + .inp_data22(norm_data_out22), + .inp_data23(norm_data_out23), + .inp_data24(norm_data_out24), + .inp_data25(norm_data_out25), + .inp_data26(norm_data_out26), + .inp_data27(norm_data_out27), + .inp_data28(norm_data_out28), + .inp_data29(norm_data_out29), + .inp_data30(norm_data_out30), + .inp_data31(norm_data_out31), + .out_data0(act_data_out0), + .out_data1(act_data_out1), + .out_data2(act_data_out2), + .out_data3(act_data_out3), + .out_data4(act_data_out4), + .out_data5(act_data_out5), + .out_data6(act_data_out6), + .out_data7(act_data_out7), + .out_data8(act_data_out8), + .out_data9(act_data_out9), + .out_data10(act_data_out10), + .out_data11(act_data_out11), + .out_data12(act_data_out12), + .out_data13(act_data_out13), + .out_data14(act_data_out14), + .out_data15(act_data_out15), + .out_data16(act_data_out16), + .out_data17(act_data_out17), + .out_data18(act_data_out18), + .out_data19(act_data_out19), + .out_data20(act_data_out20), + .out_data21(act_data_out21), + .out_data22(act_data_out22), + .out_data23(act_data_out23), + .out_data24(act_data_out24), + .out_data25(act_data_out25), + .out_data26(act_data_out26), + .out_data27(act_data_out27), + .out_data28(act_data_out28), + .out_data29(act_data_out29), + .out_data30(act_data_out30), + .out_data31(act_data_out31), + `endif + .out_data_available(activation_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_activation(done_activation), + .clk(clk), + .reset(reset) +); + +//Interface to BRAM to write the output. +//Ideally, we could remove this flop stage. But then we'd +//have to generate the address for the output BRAM in each +//block that could potentially write the output. + +reg activation_out_data_available1; +reg activation_out_data_available2; +reg activation_out_data_available3; +reg activation_out_data_available4; +reg activation_out_data_available5; +reg activation_out_data_available6; +reg activation_out_data_available7; + +`ifdef DESIGN_SIZE_16 +reg activation_out_data_available8; +reg activation_out_data_available9; +reg activation_out_data_available10; +reg activation_out_data_available11; +reg activation_out_data_available12; +reg activation_out_data_available13; +reg activation_out_data_available14; +reg activation_out_data_available15; +`endif + +`ifdef DESIGN_SIZE_32 +reg activation_out_data_available8; +reg activation_out_data_available9; +reg activation_out_data_available10; +reg activation_out_data_available11; +reg activation_out_data_available12; +reg activation_out_data_available13; +reg activation_out_data_available14; +reg activation_out_data_available15; +reg activation_out_data_available16; +reg activation_out_data_available17; +reg activation_out_data_available18; +reg activation_out_data_available19; +reg activation_out_data_available20; +reg activation_out_data_available21; +reg activation_out_data_available22; +reg activation_out_data_available23; +reg activation_out_data_available24; +reg activation_out_data_available25; +reg activation_out_data_available26; +reg activation_out_data_available27; +reg activation_out_data_available28; +reg activation_out_data_available29; +reg activation_out_data_available30; +reg activation_out_data_available31; +`endif + +always @(posedge clk) begin + activation_out_data_available1 <= activation_out_data_available; + activation_out_data_available2 <= activation_out_data_available1; + activation_out_data_available3 <= activation_out_data_available2; + activation_out_data_available4 <= activation_out_data_available3; + activation_out_data_available5 <= activation_out_data_available4; + activation_out_data_available6 <= activation_out_data_available5; + activation_out_data_available7 <= activation_out_data_available6; +end + +`ifdef DESIGN_SIZE_16 +always @(posedge clk) begin + activation_out_data_available8 <= activation_out_data_available7; + activation_out_data_available9 <= activation_out_data_available8; + activation_out_data_available10 <= activation_out_data_available9; + activation_out_data_available11 <= activation_out_data_available10; + activation_out_data_available12 <= activation_out_data_available11; + activation_out_data_available13 <= activation_out_data_available12; + activation_out_data_available14 <= activation_out_data_available13; + activation_out_data_available15 <= activation_out_data_available14; +end +`endif + +`ifdef DESIGN_SIZE_32 +always @(posedge clk) begin + activation_out_data_available8 <= activation_out_data_available7; + activation_out_data_available9 <= activation_out_data_available8; + activation_out_data_available10 <= activation_out_data_available9; + activation_out_data_available11 <= activation_out_data_available10; + activation_out_data_available12 <= activation_out_data_available11; + activation_out_data_available13 <= activation_out_data_available12; + activation_out_data_available14 <= activation_out_data_available13; + activation_out_data_available15 <= activation_out_data_available14; + activation_out_data_available16 <= activation_out_data_available15; + activation_out_data_available17 <= activation_out_data_available16; + activation_out_data_available18 <= activation_out_data_available17; + activation_out_data_available19 <= activation_out_data_available18; + activation_out_data_available20 <= activation_out_data_available19; + activation_out_data_available21 <= activation_out_data_available20; + activation_out_data_available22 <= activation_out_data_available21; + activation_out_data_available23 <= activation_out_data_available22; + activation_out_data_available24 <= activation_out_data_available23; + activation_out_data_available25 <= activation_out_data_available24; + activation_out_data_available26 <= activation_out_data_available25; + activation_out_data_available27 <= activation_out_data_available26; + activation_out_data_available28 <= activation_out_data_available27; + activation_out_data_available29 <= activation_out_data_available28; + activation_out_data_available30 <= activation_out_data_available29; + activation_out_data_available31 <= activation_out_data_available30; +end +`endif + +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data0; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data1; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data2; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data3; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data4; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data5; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data6; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data7; + +`ifdef DESIGN_SIZE_16 +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data8; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data9; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data10; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data11; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data12; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data13; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data14; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data15; +`endif + +`ifdef DESIGN_SIZE_32 +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data8; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data9; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data10; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data11; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data12; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data13; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data14; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data15; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data16; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data17; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data18; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data19; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data20; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data21; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data22; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data23; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data24; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data25; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data26; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data27; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data28; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data29; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data30; +reg [(`MAT_MUL_SIZE*`DWIDTH)-1:0] final_data31; +`endif + +always @(posedge clk) begin + if (reset) begin + final_data0 <= 0; + end + else if (activation_out_data_available) begin + final_data0 <= {act_data_out0[7:0],final_data0[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data1 <= 0; + end + else if (activation_out_data_available1) begin + final_data1 <= {act_data_out1[7:0],final_data1[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data2 <= 0; + end + else if (activation_out_data_available2) begin + final_data2 <= {act_data_out2[7:0],final_data2[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data3 <= 0; + end + else if (activation_out_data_available3) begin + final_data3 <= {act_data_out3[7:0],final_data3[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data4 <= 0; + end + else if (activation_out_data_available4) begin + final_data4 <= {act_data_out4[7:0],final_data4[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data5 <= 0; + end + else if (activation_out_data_available5) begin + final_data5 <= {act_data_out5[7:0],final_data5[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data6 <= 0; + end + else if (activation_out_data_available6) begin + final_data6 <= {act_data_out6[7:0],final_data6[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data7 <= 0; + end + else if (activation_out_data_available7) begin + final_data7 <= {act_data_out7[7:0],final_data7[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +`ifdef DESIGN_SIZE_16 +always @(posedge clk) begin + if (reset) begin + final_data8 <= 0; + end + else if (activation_out_data_available8) begin + final_data8 <= {act_data_out8[7:0],final_data8[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data9 <= 0; + end + else if (activation_out_data_available9) begin + final_data9 <= {act_data_out9[7:0],final_data9[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data10 <= 0; + end + else if (activation_out_data_available10) begin + final_data10 <= {act_data_out10[7:0],final_data10[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data11 <= 0; + end + else if (activation_out_data_available11) begin + final_data11 <= {act_data_out11[7:0],final_data11[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data12 <= 0; + end + else if (activation_out_data_available12) begin + final_data12 <= {act_data_out12[7:0],final_data12[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data13 <= 0; + end + else if (activation_out_data_available13) begin + final_data13 <= {act_data_out13[7:0],final_data13[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data14 <= 0; + end + else if (activation_out_data_available14) begin + final_data14 <= {act_data_out14[7:0],final_data14[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data15 <= 0; + end + else if (activation_out_data_available15) begin + final_data15 <= {act_data_out15[7:0],final_data15[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end +`endif + +`ifdef DESIGN_SIZE_32 +always @(posedge clk) begin + if (reset) begin + final_data8 <= 0; + end + else if (activation_out_data_available8) begin + final_data8 <= {act_data_out8[7:0],final_data8[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data9 <= 0; + end + else if (activation_out_data_available9) begin + final_data9 <= {act_data_out9[7:0],final_data9[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data10 <= 0; + end + else if (activation_out_data_available10) begin + final_data10 <= {act_data_out10[7:0],final_data10[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data11 <= 0; + end + else if (activation_out_data_available11) begin + final_data11 <= {act_data_out11[7:0],final_data11[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data12 <= 0; + end + else if (activation_out_data_available12) begin + final_data12 <= {act_data_out12[7:0],final_data12[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data13 <= 0; + end + else if (activation_out_data_available13) begin + final_data13 <= {act_data_out13[7:0],final_data13[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data14 <= 0; + end + else if (activation_out_data_available14) begin + final_data14 <= {act_data_out14[7:0],final_data14[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data15 <= 0; + end + else if (activation_out_data_available15) begin + final_data15 <= {act_data_out15[7:0],final_data15[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data16 <= 0; + end + else if (activation_out_data_available16) begin + final_data16 <= {act_data_out16[7:0],final_data16[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data17 <= 0; + end + else if (activation_out_data_available17) begin + final_data17 <= {act_data_out17[7:0],final_data17[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data18 <= 0; + end + else if (activation_out_data_available18) begin + final_data18 <= {act_data_out18[7:0],final_data18[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data19 <= 0; + end + else if (activation_out_data_available19) begin + final_data19 <= {act_data_out19[7:0],final_data19[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data20 <= 0; + end + else if (activation_out_data_available20) begin + final_data20 <= {act_data_out20[7:0],final_data20[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data21 <= 0; + end + else if (activation_out_data_available21) begin + final_data21 <= {act_data_out21[7:0],final_data21[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data22 <= 0; + end + else if (activation_out_data_available22) begin + final_data22 <= {act_data_out22[7:0],final_data22[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data23 <= 0; + end + else if (activation_out_data_available23) begin + final_data23 <= {act_data_out23[7:0],final_data23[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data24 <= 0; + end + else if (activation_out_data_available24) begin + final_data24 <= {act_data_out24[7:0],final_data24[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data25 <= 0; + end + else if (activation_out_data_available25) begin + final_data25 <= {act_data_out25[7:0],final_data25[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data26 <= 0; + end + else if (activation_out_data_available26) begin + final_data26 <= {act_data_out26[7:0],final_data26[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data27 <= 0; + end + else if (activation_out_data_available27) begin + final_data27 <= {act_data_out27[7:0],final_data27[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data28 <= 0; + end + else if (activation_out_data_available28) begin + final_data28 <= {act_data_out28[7:0],final_data28[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data29 <= 0; + end + else if (activation_out_data_available29) begin + final_data29 <= {act_data_out29[7:0],final_data29[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data30 <= 0; + end + else if (activation_out_data_available30) begin + final_data30 <= {act_data_out30[7:0],final_data30[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end + +always @(posedge clk) begin + if (reset) begin + final_data31 <= 0; + end + else if (activation_out_data_available31) begin + final_data31 <= {act_data_out31[7:0],final_data31[(`MAT_MUL_SIZE*`DWIDTH)-1:8]}; + end +end +`endif + +reg [31:0] i; + always @(posedge clk) begin + if (reset) begin + i <= 0; + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end + else if (done_activation) begin + i <= i + 1; + case(i) + `ifdef DESIGN_SIZE_8 + 0: begin bram_wdata_a <= final_data0; end + 1: begin bram_wdata_a <= final_data1; end + 2: begin bram_wdata_a <= final_data2; end + 3: begin bram_wdata_a <= final_data3; end + 4: begin bram_wdata_a <= final_data4; end + 5: begin bram_wdata_a <= final_data5; end + 6: begin bram_wdata_a <= final_data6; end + 7: begin bram_wdata_a <= final_data7; end + default : begin bram_wdata_a <= final_data7; end + `endif + `ifdef DESIGN_SIZE_16 + 0: begin bram_wdata_a <= final_data0; end + 1: begin bram_wdata_a <= final_data1; end + 2: begin bram_wdata_a <= final_data2; end + 3: begin bram_wdata_a <= final_data3; end + 4: begin bram_wdata_a <= final_data4; end + 5: begin bram_wdata_a <= final_data5; end + 6: begin bram_wdata_a <= final_data6; end + 7: begin bram_wdata_a <= final_data7; end + 8: begin bram_wdata_a <= final_data8; end + 9: begin bram_wdata_a <= final_data9; end + 10: begin bram_wdata_a <= final_data10; end + 11: begin bram_wdata_a <= final_data11; end + 12: begin bram_wdata_a <= final_data12; end + 13: begin bram_wdata_a <= final_data13; end + 14: begin bram_wdata_a <= final_data14; end + 15: begin bram_wdata_a <= final_data15; end + default : begin bram_wdata_a <= final_data15; end + `endif + `ifdef DESIGN_SIZE_32 + 0: begin bram_wdata_a <= final_data0; end + 1: begin bram_wdata_a <= final_data1; end + 2: begin bram_wdata_a <= final_data2; end + 3: begin bram_wdata_a <= final_data3; end + 4: begin bram_wdata_a <= final_data4; end + 5: begin bram_wdata_a <= final_data5; end + 6: begin bram_wdata_a <= final_data6; end + 7: begin bram_wdata_a <= final_data7; end + 8: begin bram_wdata_a <= final_data8; end + 9: begin bram_wdata_a <= final_data9; end + 10: begin bram_wdata_a <= final_data10; end + 11: begin bram_wdata_a <= final_data11; end + 12: begin bram_wdata_a <= final_data12; end + 13: begin bram_wdata_a <= final_data13; end + 14: begin bram_wdata_a <= final_data14; end + 15: begin bram_wdata_a <= final_data15; end + 16: begin bram_wdata_a <= final_data16; end + 17: begin bram_wdata_a <= final_data17; end + 18: begin bram_wdata_a <= final_data18; end + 19: begin bram_wdata_a <= final_data19; end + 20: begin bram_wdata_a <= final_data20; end + 21: begin bram_wdata_a <= final_data21; end + 22: begin bram_wdata_a <= final_data22; end + 23: begin bram_wdata_a <= final_data23; end + 24: begin bram_wdata_a <= final_data24; end + 25: begin bram_wdata_a <= final_data25; end + 26: begin bram_wdata_a <= final_data26; end + 27: begin bram_wdata_a <= final_data27; end + 28: begin bram_wdata_a <= final_data28; end + 29: begin bram_wdata_a <= final_data29; end + 30: begin bram_wdata_a <= final_data30; end + 31: begin bram_wdata_a <= final_data31; end + default : begin bram_wdata_a <= final_data31; end + `endif + endcase + bram_addr_a_for_writing <= bram_addr_a_for_writing - address_stride_c; + bram_a_wdata_available <= done_activation; + end + else begin + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end + end + + +endmodule + + diff --git a/designs/koios/tpu_like.small.ws/tpu_random.sv b/designs/koios/tpu_like.small.ws/tpu_random.sv new file mode 100644 index 000000000..17ef028e0 --- /dev/null +++ b/designs/koios/tpu_like.small.ws/tpu_random.sv @@ -0,0 +1,155 @@ +/* +Random I/Os for tpu.ws +*/ + +`include "../../random_number_generator.sv" + +`define VCS +`define MATMUL_SIZE_16 +`define MORE_TESTS +`define DESIGN_SIZE_16 +`define SIMULATION +`define layer_test + +`define DWIDTH 8 +`define AWIDTH 11 +`define MEM_SIZE 2048 + +`ifdef MATMUL_SIZE_4 +`define MAT_MUL_SIZE 4 +`define MASK_WIDTH 4 +`define LOG2_MAT_MUL_SIZE 2 +`endif + +`ifdef MATMUL_SIZE_8 +`define MAT_MUL_SIZE 8 +`define MASK_WIDTH 8 +`define LOG2_MAT_MUL_SIZE 3 +`endif + +`ifdef MATMUL_SIZE_16 +`define MAT_MUL_SIZE 16 +`define MASK_WIDTH 16 +`define LOG2_MAT_MUL_SIZE 4 +`endif + +`ifdef MATMUL_SIZE_32 +`define MAT_MUL_SIZE 32 +`define MASK_WIDTH 32 +`define LOG2_MAT_MUL_SIZE 5 +`endif + +`ifdef DESIGN_SIZE_4 +`define DESIGN_SIZE 4 +`define LOG2_DESIGN_SIZE 2 +`endif + +`ifdef DESIGN_SIZE_8 +`define DESIGN_SIZE 8 +`define LOG2_DESIGN_SIZE 3 +`endif + +`ifdef DESIGN_SIZE_16 +`define DESIGN_SIZE 16 +`define LOG2_DESIGN_SIZE 4 +`endif + +`ifdef DESIGN_SIZE_32 +`define DESIGN_SIZE 32 +`define LOG2_DESIGN_SIZE 5 +`endif + +`define BB_MAT_MUL_SIZE `MAT_MUL_SIZE +`define NUM_CYCLES_IN_MAC 3 +`define MEM_ACCESS_LATENCY 1 +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 +`define ADDR_STRIDE_WIDTH 8 +`define MAX_BITS_POOL 3 + +module tpu_random ( + input wire logicclk, + input wire logicclk_mem, + input wire logicreset, + input wire logicresetn, + input wire logic[`REG_ADDRWIDTH-1:0] PADDR, + input wire logicPWRITE, + input wire logicPSEL, + input wire logicPENABLE, + input wire logic[`REG_DATAWIDTH-1:0] PWDATA, + output logic[`REG_DATAWIDTH-1:0] PRDATA, + output logicPREADY, + input wire logic[`AWIDTH-1:0] bram_addr_a_ext, + input wire logic[`DESIGN_SIZE-1:0] bram_we_a_ext, + input wire logic[`AWIDTH-1:0] bram_addr_b_ext, + input wire logic[`DESIGN_SIZE-1:0] bram_we_b_ext, + input wire logic[4:0] out_sel, + output logic [7:0] out +); + +logic[`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata[1:0]; +always_comb begin + case(out_sel[4:1]) + 4'd0: out = bram_rdata[out_sel[0]][7:0]; + 4'd1: out = bram_rdata[out_sel[0]][15:8]; + 4'd2: out = bram_rdata[out_sel[0]][23:16]; + 4'd3: out = bram_rdata[out_sel[0]][31:24]; + 4'd4: out = bram_rdata[out_sel[0]][39:32]; + 4'd5: out = bram_rdata[out_sel[0]][47:40]; + 4'd6: out = bram_rdata[out_sel[0]][55:48]; + 4'd7: out = bram_rdata[out_sel[0]][63:56]; + 4'd8: out = bram_rdata[out_sel[0]][71:64]; + 4'd9: out = bram_rdata[out_sel[0]][79:72]; + 4'd10: out = bram_rdata[out_sel[0]][87:80]; + 4'd11: out = bram_rdata[out_sel[0]][95:88]; + 4'd12: out = bram_rdata[out_sel[0]][103:96]; + 4'd13: out = bram_rdata[out_sel[0]][111:104]; + 4'd14: out = bram_rdata[out_sel[0]][119:112]; + 4'd15: out = bram_rdata[out_sel[0]][127:120]; + endcase +end + + +logic[`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a_ext; +logic[`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b_ext; +RandomNumberGenerator #( + .RANDOM_WIDTH(`DESIGN_SIZE*`DWIDTH), + .SEED(0) +) tpu0_random_number_generator ( + .clk(logicclk), + .reset(logicreset), + .random_number(bram_wdata_a_ext) +); + +RandomNumberGenerator #( + .RANDOM_WIDTH(`DESIGN_SIZE*`DWIDTH), + .SEED(1) +) tpu1_random_number_generator ( + .clk(logicclk), + .reset(logicreset), + .random_number(bram_wdata_b_ext) +); + +top tpu0( + clk, + clk_mem, + reset, + resetn, + PADDR, + PWRITE, + PSEL, + PENABLE, + PWDATA, + PRDATA, + PREADY, + bram_addr_a_ext, + bram_rdata[0], + bram_wdata_a_ext, + bram_we_a_ext, + bram_addr_b_ext, + bram_rdata[1], + bram_wdata_b_ext, + bram_we_b_ext +); + +endmodule \ No newline at end of file diff --git a/designs/ooc/a25_decode/a25_decode_random.sv b/designs/ooc/a25_decode/a25_decode_random.sv index e01790313..6bc7e36cb 100644 --- a/designs/ooc/a25_decode/a25_decode_random.sv +++ b/designs/ooc/a25_decode/a25_decode_random.sv @@ -2,7 +2,7 @@ * a25_decode top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module a25_decode_random( input logic clk, diff --git a/designs/ooc/a25_execute/a25_execute_random.sv b/designs/ooc/a25_execute/a25_execute_random.sv index e78479d08..56a071e34 100644 --- a/designs/ooc/a25_execute/a25_execute_random.sv +++ b/designs/ooc/a25_execute/a25_execute_random.sv @@ -2,7 +2,7 @@ * a25_execute top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module a25_execute_random( input logic clk, diff --git a/designs/ooc/a25_fetch/a25_fetch_random.sv b/designs/ooc/a25_fetch/a25_fetch_random.sv index b24396870..456efa431 100644 --- a/designs/ooc/a25_fetch/a25_fetch_random.sv +++ b/designs/ooc/a25_fetch/a25_fetch_random.sv @@ -2,7 +2,7 @@ * a25_fetch top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module a25_fetch_random( input logic clk, diff --git a/designs/ooc/a25_mem/a25_mem_random.sv b/designs/ooc/a25_mem/a25_mem_random.sv index b27f65d69..f03e48e6b 100644 --- a/designs/ooc/a25_mem/a25_mem_random.sv +++ b/designs/ooc/a25_mem/a25_mem_random.sv @@ -2,7 +2,7 @@ * a25_mem top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module a25_mem_random( input logic clk, diff --git a/designs/ooc/a25_wishbone/a25_wishbone_random.sv b/designs/ooc/a25_wishbone/a25_wishbone_random.sv index 04234bb9a..847ddd432 100644 --- a/designs/ooc/a25_wishbone/a25_wishbone_random.sv +++ b/designs/ooc/a25_wishbone/a25_wishbone_random.sv @@ -2,7 +2,7 @@ * a25_wishbone top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module a25_wishbone_random( input logic clk, diff --git a/designs/ooc/aes128/aes128_random.sv b/designs/ooc/aes128/aes128_random.sv index b284c5d8b..3f0624b29 100644 --- a/designs/ooc/aes128/aes128_random.sv +++ b/designs/ooc/aes128/aes128_random.sv @@ -2,7 +2,7 @@ * aes128 top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module aes128_random( input logic clk, diff --git a/designs/ooc/ahbctrl/ahbctrl_random.sv b/designs/ooc/ahbctrl/ahbctrl_random.sv index 204ca00b6..96c123329 100644 --- a/designs/ooc/ahbctrl/ahbctrl_random.sv +++ b/designs/ooc/ahbctrl/ahbctrl_random.sv @@ -2,7 +2,7 @@ * ahbctrl top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module ahbctrl_random( input logic clk, diff --git a/designs/ooc/ahbjtag/ahbjtag_random.sv b/designs/ooc/ahbjtag/ahbjtag_random.sv index 64fc70c75..c5afd6f06 100644 --- a/designs/ooc/ahbjtag/ahbjtag_random.sv +++ b/designs/ooc/ahbjtag/ahbjtag_random.sv @@ -2,7 +2,7 @@ * ahbjtag top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module ahbjtag_random( input logic clk, diff --git a/designs/ooc/ahbuart/ahbuart_random.sv b/designs/ooc/ahbuart/ahbuart_random.sv index f02ba8ebc..75aef945b 100644 --- a/designs/ooc/ahbuart/ahbuart_random.sv +++ b/designs/ooc/ahbuart/ahbuart_random.sv @@ -2,7 +2,7 @@ * ahbuart top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module ahbuart_random( input logic clk, diff --git a/designs/ooc/amber/amber_random.sv b/designs/ooc/amber/amber_random.sv index d3425f643..34bbb9758 100644 --- a/designs/ooc/amber/amber_random.sv +++ b/designs/ooc/amber/amber_random.sv @@ -2,7 +2,7 @@ * amber top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module amber_random ( input logic clk, diff --git a/designs/ooc/apbctrl/apbctrl_random.sv b/designs/ooc/apbctrl/apbctrl_random.sv index 26ff79ba2..abb161b5c 100644 --- a/designs/ooc/apbctrl/apbctrl_random.sv +++ b/designs/ooc/apbctrl/apbctrl_random.sv @@ -2,7 +2,7 @@ * apbctrl top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module apbctrl_random( input logic clk, diff --git a/designs/ooc/bubblesort/bubblesort_random.sv b/designs/ooc/bubblesort/bubblesort_random.sv index 91932dd75..bf39fe199 100644 --- a/designs/ooc/bubblesort/bubblesort_random.sv +++ b/designs/ooc/bubblesort/bubblesort_random.sv @@ -2,7 +2,7 @@ * bubblesort top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module bubblesort_random( input logic clk, diff --git a/designs/ooc/des3_area/des3_area_random.sv b/designs/ooc/des3_area/des3_area_random.sv index afc60cf70..1024e6f5b 100644 --- a/designs/ooc/des3_area/des3_area_random.sv +++ b/designs/ooc/des3_area/des3_area_random.sv @@ -2,7 +2,7 @@ * des3_area top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module des3_area_random( input logic clk, diff --git a/designs/ooc/des3_perf/des3_perf_random.sv b/designs/ooc/des3_perf/des3_perf_random.sv index f975678f9..563020759 100644 --- a/designs/ooc/des3_perf/des3_perf_random.sv +++ b/designs/ooc/des3_perf/des3_perf_random.sv @@ -2,7 +2,7 @@ * des3_perf top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module des3_perf_random( input logic clk, diff --git a/designs/ooc/dsu3/dsu3_random.sv b/designs/ooc/dsu3/dsu3_random.sv index ad5b88fcd..a9fc0667b 100644 --- a/designs/ooc/dsu3/dsu3_random.sv +++ b/designs/ooc/dsu3/dsu3_random.sv @@ -2,7 +2,7 @@ * dsu3 top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module dsu3_random( input logic clk, diff --git a/designs/ooc/grethm/grethm_random.sv b/designs/ooc/grethm/grethm_random.sv index c240b4e16..55485e254 100644 --- a/designs/ooc/grethm/grethm_random.sv +++ b/designs/ooc/grethm/grethm_random.sv @@ -2,7 +2,7 @@ * grethm top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module grethm_random( input logic clk, diff --git a/designs/ooc/irqmp/irqmp_random.sv b/designs/ooc/irqmp/irqmp_random.sv index bd33ced8f..9173e2675 100644 --- a/designs/ooc/irqmp/irqmp_random.sv +++ b/designs/ooc/irqmp/irqmp_random.sv @@ -2,7 +2,7 @@ * irqmp top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module irqmp_random( input logic clk, diff --git a/designs/ooc/leon3s/leon3s_random.sv b/designs/ooc/leon3s/leon3s_random.sv index 7e19a6a27..1a3b6e53a 100644 --- a/designs/ooc/leon3s/leon3s_random.sv +++ b/designs/ooc/leon3s/leon3s_random.sv @@ -2,7 +2,7 @@ * leon3s top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module leon3s_random( input logic clk, diff --git a/designs/ooc/m32632/m32632_random.sv b/designs/ooc/m32632/m32632_random.sv index 4df3a2dfa..e7ad59255 100644 --- a/designs/ooc/m32632/m32632_random.sv +++ b/designs/ooc/m32632/m32632_random.sv @@ -2,7 +2,7 @@ * m32632 top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module m32632_random ( input logic clk, diff --git a/designs/ooc/mctrl/mctrl_random.sv b/designs/ooc/mctrl/mctrl_random.sv index b4e490d6c..ae2fe2041 100644 --- a/designs/ooc/mctrl/mctrl_random.sv +++ b/designs/ooc/mctrl/mctrl_random.sv @@ -2,7 +2,7 @@ * mctrl top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module mctrl_random( input logic clk, diff --git a/designs/ooc/md5_pipelined/md5_pipelined_random.sv b/designs/ooc/md5_pipelined/md5_pipelined_random.sv index 8884b9145..5b542cab8 100644 --- a/designs/ooc/md5_pipelined/md5_pipelined_random.sv +++ b/designs/ooc/md5_pipelined/md5_pipelined_random.sv @@ -2,7 +2,7 @@ * md5_pipelined top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" `include "md5_pipelined.v" module md5_pipelined_random( diff --git a/designs/ooc/mpeg2fpga/mpeg2fpga_random.sv b/designs/ooc/mpeg2fpga/mpeg2fpga_random.sv index 4acdedf91..daa9020b6 100644 --- a/designs/ooc/mpeg2fpga/mpeg2fpga_random.sv +++ b/designs/ooc/mpeg2fpga/mpeg2fpga_random.sv @@ -2,7 +2,7 @@ * mpeg2fpga top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" `include "mpeg2fpga.v" module mpeg2fpga_random( diff --git a/designs/ooc/sha3_high_throughput/sha3_high_throughput_random.sv b/designs/ooc/sha3_high_throughput/sha3_high_throughput_random.sv index 4dea51bde..02d9ccb28 100644 --- a/designs/ooc/sha3_high_throughput/sha3_high_throughput_random.sv +++ b/designs/ooc/sha3_high_throughput/sha3_high_throughput_random.sv @@ -2,7 +2,7 @@ * sha3_high_throughput top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module sha3_high_throughput_random( input logic clk, diff --git a/designs/ooc/sha3_low_throughput/sha3_low_throughput_random.sv b/designs/ooc/sha3_low_throughput/sha3_low_throughput_random.sv index 161642ed8..c42ab4537 100644 --- a/designs/ooc/sha3_low_throughput/sha3_low_throughput_random.sv +++ b/designs/ooc/sha3_low_throughput/sha3_low_throughput_random.sv @@ -2,7 +2,7 @@ * sha3_low_throughput top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module sha3_low_throughput_random( input logic clk, diff --git a/designs/ooc/spimctrl/spimctrl_random.sv b/designs/ooc/spimctrl/spimctrl_random.sv index 25c5ee5d0..02ebb290d 100644 --- a/designs/ooc/spimctrl/spimctrl_random.sv +++ b/designs/ooc/spimctrl/spimctrl_random.sv @@ -2,7 +2,7 @@ * spimctrl top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module spimctrl_random( input logic clk, diff --git a/designs/ooc/sudoku/sudoku_random.sv b/designs/ooc/sudoku/sudoku_random.sv index 1b9f4f3d3..06d73a504 100644 --- a/designs/ooc/sudoku/sudoku_random.sv +++ b/designs/ooc/sudoku/sudoku_random.sv @@ -2,7 +2,7 @@ * sudoku top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module sudoku_random( input logic clk, diff --git a/designs/ooc/random_number_generator.sv b/designs/random_number_generator.sv similarity index 100% rename from designs/ooc/random_number_generator.sv rename to designs/random_number_generator.sv diff --git a/designs/vtr_benchmarks/bgm/bgm_random.sv b/designs/vtr_benchmarks/bgm/bgm_random.sv index fa1818203..29c1d9833 100644 --- a/designs/vtr_benchmarks/bgm/bgm_random.sv +++ b/designs/vtr_benchmarks/bgm/bgm_random.sv @@ -2,7 +2,7 @@ * bgm top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module bgm_random( input logic clk, diff --git a/designs/vtr_benchmarks/boundtop/paj_boundtop_hierarchy_no_mem_random.sv b/designs/vtr_benchmarks/boundtop/paj_boundtop_hierarchy_no_mem_random.sv index 555fee661..7f2ffab6e 100644 --- a/designs/vtr_benchmarks/boundtop/paj_boundtop_hierarchy_no_mem_random.sv +++ b/designs/vtr_benchmarks/boundtop/paj_boundtop_hierarchy_no_mem_random.sv @@ -2,7 +2,7 @@ * paj_boundtop_hierarchy_no_mem top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module paj_boundtop_hierarchy_no_mem_random( input logic clk, diff --git a/designs/vtr_benchmarks/mcml/mcml_random.sv b/designs/vtr_benchmarks/mcml/mcml_random.sv index d403e2b27..7d26d49db 100644 --- a/designs/vtr_benchmarks/mcml/mcml_random.sv +++ b/designs/vtr_benchmarks/mcml/mcml_random.sv @@ -2,7 +2,7 @@ * mcml top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module mcml_random( input logic reset, diff --git a/designs/vtr_benchmarks/mkDelayWorker32B/mkDelayWorker32B_random.sv b/designs/vtr_benchmarks/mkDelayWorker32B/mkDelayWorker32B_random.sv index 71a002684..5217a8081 100644 --- a/designs/vtr_benchmarks/mkDelayWorker32B/mkDelayWorker32B_random.sv +++ b/designs/vtr_benchmarks/mkDelayWorker32B/mkDelayWorker32B_random.sv @@ -2,7 +2,7 @@ * mkDelayWorker32B top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module mkDelayWorker32B_random( input logic clk, diff --git a/designs/vtr_benchmarks/mkPktMerge/mkPktMerge_random.sv b/designs/vtr_benchmarks/mkPktMerge/mkPktMerge_random.sv index 6e0bf867c..0dce99c77 100644 --- a/designs/vtr_benchmarks/mkPktMerge/mkPktMerge_random.sv +++ b/designs/vtr_benchmarks/mkPktMerge/mkPktMerge_random.sv @@ -2,7 +2,7 @@ * mkPktMerge top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module mkPktMerge_random( input logic clk, diff --git a/designs/vtr_benchmarks/mkSMAdapter4B/mkSMAdapter4B_random.sv b/designs/vtr_benchmarks/mkSMAdapter4B/mkSMAdapter4B_random.sv index 8c471ef2e..6f02de4ba 100644 --- a/designs/vtr_benchmarks/mkSMAdapter4B/mkSMAdapter4B_random.sv +++ b/designs/vtr_benchmarks/mkSMAdapter4B/mkSMAdapter4B_random.sv @@ -2,7 +2,7 @@ * mkSMAdapter4B top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module mkSMAdapter4B_random( input logic clk, diff --git a/designs/vtr_benchmarks/or1200/or1200_flat_random.sv b/designs/vtr_benchmarks/or1200/or1200_flat_random.sv index b96dd4159..02de73507 100644 --- a/designs/vtr_benchmarks/or1200/or1200_flat_random.sv +++ b/designs/vtr_benchmarks/or1200/or1200_flat_random.sv @@ -2,7 +2,7 @@ * or1200_flat top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module or1200_flat_random( input logic clk, diff --git a/designs/vtr_benchmarks/raygentop/paj_raygentop_hierarchy_no_mem_random.sv b/designs/vtr_benchmarks/raygentop/paj_raygentop_hierarchy_no_mem_random.sv index 70d54af73..1f05f13fe 100644 --- a/designs/vtr_benchmarks/raygentop/paj_raygentop_hierarchy_no_mem_random.sv +++ b/designs/vtr_benchmarks/raygentop/paj_raygentop_hierarchy_no_mem_random.sv @@ -2,7 +2,7 @@ * paj_raygentop_hierarchy_no_mem top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module paj_raygentop_hierarchy_no_mem_random( input logic clk, diff --git a/designs/vtr_benchmarks/stereovision0/sv_chip0_hierarchy_no_mem_random.sv b/designs/vtr_benchmarks/stereovision0/sv_chip0_hierarchy_no_mem_random.sv index 465a9de3c..8562503f0 100644 --- a/designs/vtr_benchmarks/stereovision0/sv_chip0_hierarchy_no_mem_random.sv +++ b/designs/vtr_benchmarks/stereovision0/sv_chip0_hierarchy_no_mem_random.sv @@ -2,7 +2,7 @@ * sv_chip0_hierarchy_no_mem top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module sv_chip0_hierarchy_no_mem_random( input clk, diff --git a/designs/vtr_benchmarks/stereovision2/sv_chip2_hierarchy_no_mem_random.sv b/designs/vtr_benchmarks/stereovision2/sv_chip2_hierarchy_no_mem_random.sv index cde90f8bb..86d37b5c9 100644 --- a/designs/vtr_benchmarks/stereovision2/sv_chip2_hierarchy_no_mem_random.sv +++ b/designs/vtr_benchmarks/stereovision2/sv_chip2_hierarchy_no_mem_random.sv @@ -2,7 +2,7 @@ * sv_chip2_hierarchy_no_mem top level module that incorporates the random number generator * to allow bitstream generation without Vivado interferance */ -`include "../random_number_generator.sv" +`include "../../random_number_generator.sv" module sv_chip2_hierarchy_no_mem_random( input logic clk, diff --git a/tests/weekly/vivado_koios.yaml b/tests/weekly/vivado_koios.yaml new file mode 100644 index 000000000..9be374282 --- /dev/null +++ b/tests/weekly/vivado_koios.yaml @@ -0,0 +1,37 @@ +designs: + # These succeeded Vivado Implementation (bitstream generated) with and without phys_opt_design (no declared clock) + # Part chosen was xc7a200tsbg484-1 + - koios/attention_layer + - koios/bnn + - koios/bwave_like.fixed.large + - koios/bwave_like.fixed.small + - koios/bwave_like.float.small + - koios/clstm_like.large + - koios/conv_layer + - koios/dla_like.medium + - koios/dla_like.small + - koios/eltwise_layer + - koios/lenet + - koios/clstm_like.small + - koios/spmv + - koios/test + - koios/tpu_like.large.ws + - koios/tpu_like.large.os + - koios/tpu_like.small.ws + - koios/tpu_like.small.os + - koios/robot_rl + - koios/softmax + - koios/lstm + - koios/reduction_layer + + # - koios/dla_like.large + # - koios/dnnweaver Needs more slices, 160K+ LUTs + # - koios/tdarknet_like.small Needs 1600+ BRAMs + # - koios/gemm_layer 200k LUTS + + # - koios/conv_layer_hls Critical Warnings in synthesis + # - koios/clstm_like.medium too many I/Os + # - koios/bwave_like.float.large # too many I/Os, need to condense output + # - koios/tdarknet_like.large # Vivado synth fails -> comb assignment to registers + +flow: Vivado \ No newline at end of file